/* SPDX-License-Identifier: GPL-2.0 OR MIT */
#ifndef __LINUX_OVERFLOW_H
#define __LINUX_OVERFLOW_H

#include <linux/compiler.h>

/*
 * We need to compute the minimum and maximum values representable in a given
 * type. These macros may also be useful elsewhere. It would seem more obvious
 * to do something like:
 *
 * #define type_min(T) (T)(is_signed_type(T) ? (T)1 << (8*sizeof(T)-1) : 0)
 * #define type_max(T) (T)(is_signed_type(T) ? ((T)1 << (8*sizeof(T)-1)) - 1 : ~(T)0)
 *
 * Unfortunately, the middle expressions, strictly speaking, have
 * undefined behaviour, and at least some versions of gcc warn about
 * the type_max expression (but not if -fsanitize=undefined is in
 * effect; in that case, the warning is deferred to runtime...).
 *
 * The slightly excessive casting in type_min is to make sure the
 * macros also produce sensible values for the exotic type _Bool. [The
 * overflow checkers only almost work for _Bool, but that's
 * a-feature-not-a-bug, since people shouldn't be doing arithmetic on
 * _Bools. Besides, the gcc builtins don't allow _Bool* as third
 * argument.]
 *
 * Idea stolen from
 * https://mail-index.netbsd.org/tech-misc/2007/02/05/0000.html -
 * credit to Christian Biere.
 */
#define is_signed_type(type)       (((type)(-1)) < (type)1)
#define __type_half_max(type) ((type)1 << (8*sizeof(type) - 1 - is_signed_type(type)))
#define type_max(T) ((T)((__type_half_max(T) - 1) + __type_half_max(T)))
#define type_min(T) ((T)((T)-type_max(T)-(T)1))

/*
 * For simplicity and code hygiene, the fallback code below insists on
 * a, b and *d having the same type (similar to the min() and max()
 * macros), whereas gcc's type-generic overflow checkers accept
 * different types. Hence we don't just make check_add_overflow an
 * alias for __builtin_add_overflow, but add type checks similar to
 * below.
 */
#define check_add_overflow(a, b, d) ({		\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	typeof(d) __d = (d);			\
	(void) (&__a == &__b);			\
	(void) (&__a == __d);			\
	__builtin_add_overflow(__a, __b, __d);	\
})

#define check_sub_overflow(a, b, d) ({		\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	typeof(d) __d = (d);			\
	(void) (&__a == &__b);			\
	(void) (&__a == __d);			\
	__builtin_sub_overflow(__a, __b, __d);	\
})

#define check_mul_overflow(a, b, d) ({		\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	typeof(d) __d = (d);			\
	(void) (&__a == &__b);			\
	(void) (&__a == __d);			\
	__builtin_mul_overflow(__a, __b, __d);	\
})

/**
 * array_size() - Calculate size of 2-dimensional array.
 *
 * @a: dimension one
 * @b: dimension two
 *
 * Calculates size of 2-dimensional array: @a * @b.
 *
 * Returns: number of bytes needed to represent the array or SIZE_MAX on
 * overflow.
 */
static inline __must_check size_t array_size(size_t a, size_t b)
{
	size_t bytes;

	if (check_mul_overflow(a, b, &bytes))
		return SIZE_MAX;

	return bytes;
}

/**
 * array3_size() - Calculate size of 3-dimensional array.
 *
 * @a: dimension one
 * @b: dimension two
 * @c: dimension three
 *
 * Calculates size of 3-dimensional array: @a * @b * @c.
 *
 * Returns: number of bytes needed to represent the array or SIZE_MAX on
 * overflow.
 */
static inline __must_check size_t array3_size(size_t a, size_t b, size_t c)
{
	size_t bytes;

	if (check_mul_overflow(a, b, &bytes))
		return SIZE_MAX;
	if (check_mul_overflow(bytes, c, &bytes))
		return SIZE_MAX;

	return bytes;
}

static inline __must_check size_t __ab_c_size(size_t n, size_t size, size_t c)
{
	size_t bytes;

	if (check_mul_overflow(n, size, &bytes))
		return SIZE_MAX;
	if (check_add_overflow(bytes, c, &bytes))
		return SIZE_MAX;

	return bytes;
}

/**
 * struct_size() - Calculate size of structure with trailing array.
 * @p: Pointer to the structure.
 * @member: Name of the array member.
 * @n: Number of elements in the array.
 *
 * Calculates size of memory needed for structure @p followed by an
 * array of @n @member elements.
 *
 * Return: number of bytes needed or SIZE_MAX on overflow.
 */
#define struct_size(p, member, n)					\
	__ab_c_size(n,							\
		    sizeof(*(p)->member) + __must_be_array((p)->member),\
		    sizeof(*(p)))

#endif /* __LINUX_OVERFLOW_H */
/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/device.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
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<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
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<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/accel/qaic/mhi_controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/qaic/mhi_controller.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
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<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/nfit/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/nfit/core.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/numa/hmat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/numa/hmat.c</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/numa/srat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/numa/srat.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/osl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/osl.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/processor_thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/processor_thermal.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/property.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/resource.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/scan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/scan.c</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/tables.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/tables.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/thermal.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/acpi/thermal_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/thermal_lib.c</a> (renamed from drivers/thermal/thermal_acpi.c)</td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/acpi/utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/utils.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binder_alloc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc.c</a></td><td class='right'>861</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 5.1%;'/><td class='none' style='width: 89.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binder_alloc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc.h</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binder_alloc_selftest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc_selftest.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binder_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_trace.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/android/binderfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binderfs.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ata/libata-scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ata/libata-scsi.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ata/pata_pxa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ata/pata_pxa.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/atmtcp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/atmtcp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/eni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/eni.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/idt77105.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/idt77105.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/iphase.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/iphase.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/nicstar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/nicstar.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/solos-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/solos-pci.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/atm/suni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/suni.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/auxdisplay/img-ascii-lcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/auxdisplay/img-ascii-lcd.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/arch_numa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/arch_numa.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/arch_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/arch_topology.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/auxiliary.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/auxiliary.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/bus.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/class.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/container.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/container.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/core.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/cpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/cpu.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/dd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/dd.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/devcoredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/devcoredump.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/firmware_loader/sysfs_upload.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/firmware_loader/sysfs_upload.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/init.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/isa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/isa.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/memory.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/node.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/node.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/clock_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/clock_ops.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/main.c</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/qos.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/runtime.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/runtime.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/power/trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/trace.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/property.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/internal.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regcache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regcache.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regmap-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-debugfs.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regmap-kunit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-kunit.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regmap-ram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-ram.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regmap-raw-ram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-raw-ram.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/regmap/regmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/soc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/base/swnode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/swnode.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bcma/driver_pci_host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bcma/driver_pci_host.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/aoe/aoeblk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/aoe/aoeblk.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/drbd/drbd_actlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/drbd/drbd_actlog.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/floppy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/floppy.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/loop.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/loop.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/nbd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/nbd.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/null_blk/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/null_blk/main.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/null_blk/zoned.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/null_blk/zoned.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/rnbd/rnbd-clt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-clt.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/rnbd/rnbd-proto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-proto.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/rnbd/rnbd-srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-srv.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/ublk_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/ublk_drv.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/virtio_blk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/virtio_blk.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/xen-blkback/common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/xen-blkback/common.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/zram/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/Kconfig</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/zram/zram_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/zram_drv.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/block/zram/zram_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/zram_drv.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/btintel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btintel.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/btintel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btintel.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/btmtkuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btmtkuart.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/btnxpuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btnxpuart.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/btusb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btusb.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/hci_qca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_qca.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/hci_serdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_serdev.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bluetooth/hci_vhci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_vhci.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/fsl-mc/fsl-mc-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/fsl-mc/fsl-mc-bus.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/hisi_lpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/hisi_lpc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/imx-weim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/imx-weim.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/ep/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/internal.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/ep/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/main.c</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/ep/ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/ring.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/host/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/init.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/host/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/internal.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/host/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/main.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/host/pci_generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/pci_generic.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/mhi/host/pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/pm.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/moxtet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/moxtet.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/omap-ocp2scp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/omap-ocp2scp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/omap_l3_smx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/omap_l3_smx.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/qcom-ssc-block-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/qcom-ssc-block-bus.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/simple-pm-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/simple-pm-bus.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/sun50i-de2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/sun50i-de2.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/sunxi-rsb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/sunxi-rsb.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/tegra-aconnect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/tegra-aconnect.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/tegra-gmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/tegra-gmi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/ti-pwmss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ti-pwmss.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/ti-sysc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ti-sysc.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/bus/ts-nbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ts-nbus.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cache/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/Kconfig</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cache/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/cache/sifive_ccache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/sifive_ccache.c</a> (renamed from drivers/soc/sifive/sifive_ccache.c)</td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cdx/cdx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cdx/cdx.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/atmel-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/atmel-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/cctrng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/cctrng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/core.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/exynos-trng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/exynos-trng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/ingenic-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/ingenic-rng.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/jh7110-trng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/jh7110-trng.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/ks-sa-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/ks-sa-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/mxc-rnga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/mxc-rnga.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/n2-drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/n2-drv.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/npcm-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/npcm-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/omap-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/omap-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/stm32-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/stm32-rng.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/timeriomem-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/timeriomem-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/virtio-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/virtio-rng.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/hw_random/xgene-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/xgene-rng.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/ipmi/ipmi_msghandler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_msghandler.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/ipmi/ipmi_si_hardcode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_si_hardcode.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/ipmi/ipmi_si_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_si_platform.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/ppdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ppdev.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/random.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/random.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/tpm/tpm_i2c_nuvoton.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/tpm/tpm_i2c_nuvoton.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/tpm/tpm_tis_i2c_cr50.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/tpm/tpm_tis_i2c_cr50.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/ttyprintk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ttyprintk.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/char/virtio_console.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/virtio_console.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/clk-renesas-pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-renesas-pcie.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/clk-si5341.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-si5341.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/clk-si5351.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-si5351.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/clk-sp7021.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-sp7021.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/clk-versaclock3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-versaclock3.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/hisilicon/clk-hi3620.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/hisilicon/clk-hi3620.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/imx/clk-imx8qxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-imx8qxp.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/imx/clk-pll14xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-pll14xx.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/imx/clk-scu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-scu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/Kconfig</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt7988-apmixed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-apmixed.c</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt7988-eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-eth.c</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt7988-infracfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-infracfg.c</a></td><td class='right'>275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt7988-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-topckgen.c</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt7988-xfipll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-xfipll.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt8188-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt8188-topckgen.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mt8195-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt8195-topckgen.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mux.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-mux.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mux.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-pll.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mediatek/clk-pll.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-pll.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/meson/g12a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/meson/g12a.c</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/meson/g12a.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/meson/g12a.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/microchip/clk-mpfs-ccc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/microchip/clk-mpfs-ccc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/mmp/clk-of-pxa168.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mmp/clk-of-pxa168.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/Kconfig</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/Makefile</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/apss-ipq-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/apss-ipq-pll.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/camcc-sc8280xp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/camcc-sc8280xp.c</a></td><td class='right'>3045</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 36.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 63.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/clk-branch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-branch.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/clk-branch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-branch.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/clk-rpmh.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-rpmh.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/dispcc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/dispcc-sm8550.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/dispcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/dispcc-sm8650.c</a></td><td class='right'>1818</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 78.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/ecpricc-qdu1000.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/ecpricc-qdu1000.c</a></td><td class='right'>2456</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 29.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 70.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gcc-msm8939.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-msm8939.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gcc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-sm8550.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-sm8650.c</a></td><td class='right'>3849</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 46.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 53.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gcc-x1e80100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-x1e80100.c</a></td><td class='right'>6808</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 82.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 17.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gpucc-sm8150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8150.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gpucc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8550.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/gpucc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8650.c</a></td><td class='right'>663</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/qcom/tcsrcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/tcsrcc-sm8650.c</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/qcom/videocc-sm8150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/videocc-sm8150.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/renesas/r8a779g0-cpg-mssr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/r8a779g0-cpg-mssr.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/renesas/r9a08g045-cpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/r9a08g045-cpg.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/renesas/rzg2l-cpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/rzg2l-cpg.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/rockchip/clk-rk3128.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/rockchip/clk-rk3128.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/rockchip/clk-rk3568.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/rockchip/clk-rk3568.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/samsung/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/samsung/clk-cpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-cpu.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/samsung/clk-gs101.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-gs101.c</a></td><td class='right'>2518</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 30.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 69.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/samsung/clk-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-pll.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/samsung/clk-pll.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-pll.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/samsung/clk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk.h</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh7100-audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7100-audio.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh7100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7100.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh7110-aon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-aon.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh7110-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-isp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh7110-sys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-sys.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/starfive/clk-starfive-jh71x0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh71x0.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/clk/stm32/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/Kconfig</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/clk-stm32-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32-core.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/clk-stm32-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32-core.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/clk/stm32/clk-stm32mp1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32mp1.c</a> (renamed from drivers/clk/clk-stm32mp1.c)</td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/clk-stm32mp13.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32mp13.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/reset-stm32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/reset-stm32.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/stm32/reset-stm32.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/reset-stm32.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/sunxi-ng/ccu_nkm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/sunxi-ng/ccu_nkm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/xilinx/clk-xlnx-clock-wizard.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/xilinx/clk-xlnx-clock-wizard.c</a></td><td class='right'>628</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 92.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/zynqmp/clk-mux-zynqmp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/zynqmp/clk-mux-zynqmp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clk/zynqmp/divider.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/zynqmp/divider.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clocksource/timer-cadence-ttc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-cadence-ttc.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clocksource/timer-ep93xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-ep93xx.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clocksource/timer-riscv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-riscv.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/clocksource/timer-ti-dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-ti-dm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/comedi/comedi_fops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/comedi/comedi_fops.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/connector/cn_proc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/connector/cn_proc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/connector/connector.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/connector/connector.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/amd-pstate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/amd-pstate.c</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/armada-8k-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/armada-8k-cpufreq.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/cppc_cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/cppc_cpufreq.c</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/cpufreq.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/imx6q-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/imx6q-cpufreq.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/intel_pstate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/intel_pstate.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/qcom-cpufreq-nvmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/qcom-cpufreq-nvmem.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpufreq/scmi-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/scmi-cpufreq.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cpuidle/cpuidle-haltpoll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpuidle/cpuidle-haltpoll.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/amcc/crypto4xx_alg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_alg.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/amcc/crypto4xx_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_core.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/amcc/crypto4xx_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_core.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/amlogic/amlogic-gxl-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amlogic/amlogic-gxl-cipher.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/aspeed/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/aspeed/Kconfig</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/aspeed/aspeed-hace-crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/aspeed/aspeed-hace-crypto.c</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/atmel-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/atmel-aes.c</a></td><td class='right'>214</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/atmel-tdes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/atmel-tdes.c</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/axis/artpec6_crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/axis/artpec6_crypto.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/bcm/cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/bcm/cipher.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/cavium/cpt/cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/cavium/cpt/cptvf_algs.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/cavium/nitrox/nitrox_skcipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/cavium/nitrox/nitrox_skcipher.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/ccp/ccp-crypto-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/ccp-crypto-aes.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/ccp/ccp-ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/ccp-ops.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/ccp/sev-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/sev-dev.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/ccree/cc_aead.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccree/cc_aead.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/ccree/cc_cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccree/cc_cipher.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/gemini/sl3516-ce-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/gemini/sl3516-ce-cipher.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hifn_795x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hifn_795x.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/debugfs.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/hpre/hpre_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/hpre/hpre_main.c</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/qm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/qm.c</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/qm_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/qm_common.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/sec2/sec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/sec2/sec_crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_crypto.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/sec2/sec_crypto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_crypto.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/sec2/sec_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_main.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/sgl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sgl.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/hisilicon/zip/zip_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/zip/zip_main.c</a></td><td class='right'>229</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/inside-secure/safexcel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/inside-secure/safexcel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/inside-secure/safexcel_cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel_cipher.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/Kconfig</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/Makefile</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/iaa_crypto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto.h</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/iaa_crypto_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_main.c</a></td><td class='right'>2193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 26.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 73.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/iaa_crypto_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_stats.c</a></td><td class='right'>312</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/iaa/iaa_crypto_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_stats.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_420xx/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c</a></td><td class='right'>528</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_420xx/adf_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_drv.c</a></td><td class='right'>202</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c</a></td><td class='right'>339</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_drv.c</a></td><td class='right'>277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_accel_devices.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_accel_engine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_accel_engine.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_admin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_admin.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_admin.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_admin.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_common.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_dbgfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_dbgfs.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_fw_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_fw_config.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_config.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_config.c</a></td><td class='right'>287</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_config.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c</a></td><td class='right'>238</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_init.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_rl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_rl.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_rl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_rl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_telemetry.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_telemetry.c</a></td><td class='right'>288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_telemetry.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_telemetry.h</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c</a></td><td class='right'>710</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_hw.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/qat_hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/qat_hal.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/intel/qat/qat_common/qat_uclo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/qat_uclo.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/cesa/cesa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/cesa/cesa.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx/otx_cptvf_algs.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/cn10k_cpt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/cn10k_cpt.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/cn10k_cpt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/cn10k_cpt.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_common.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h</a></td><td class='right'>298</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptlf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptlf.c</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptlf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptlf.h</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/n2_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/n2_core.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/rockchip/rk3288_crypto_skcipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/rockchip/rk3288_crypto_skcipher.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/sa2ul.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/sa2ul.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/sahara.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/sahara.c</a></td><td class='right'>837</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 5.7%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/starfive/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/starfive/jh7110-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-aes.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/starfive/jh7110-cryp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-cryp.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/starfive/jh7110-cryp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-cryp.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/starfive/jh7110-rsa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-rsa.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/stm32/stm32-crc32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/stm32/stm32-crc32.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/stm32/stm32-cryp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/stm32/stm32-cryp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/virtio/virtio_crypto_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/virtio/virtio_crypto_common.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/crypto/virtio/virtio_crypto_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/virtio/virtio_crypto_core.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/acpi.c</a></td><td class='right'>155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/cxl/core/cdat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/cdat.c</a></td><td class='right'>521</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/core.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/hdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/hdm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/mbox.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/memdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/memdev.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pci.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/pmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pmem.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pmu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/port.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/region.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/core/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/trace.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/cxl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxl.h</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/cxlmem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxlmem.h</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/cxlpci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxlpci.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/mem.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/pci.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/cxl/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/port.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/bus.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/bus.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/bus.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/cxl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/cxl.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/dax-private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/dax-private.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/hmem/hmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/hmem/hmem.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/kmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/kmem.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/pmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/pmem.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dax/super.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/super.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/devfreq/devfreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/devfreq/devfreq.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma-buf/dma-resv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma-buf/dma-resv.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/Kconfig</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/apple-admac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/apple-admac.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/dma-axi-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dma-axi-dmac.c</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/dmaengine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dmaengine.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/dmatest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dmatest.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/dw-edma/dw-edma-v0-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dw-edma/dw-edma-v0-debugfs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dw-edma/dw-hdma-v0-debugfs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/fsl-edma-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-edma-common.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/fsl-edma-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-edma-main.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/fsl-qdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-qdma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/bus.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/cdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/cdev.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/dma/idxd/defaults.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/defaults.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/device.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/dma.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/idxd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/idxd.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/init.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/irq.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/registers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/registers.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/idxd/submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/submit.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/imx-sdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/imx-sdma.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/dma/ls2x-apb-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ls2x-apb-dma.c</a></td><td class='right'>705</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/milbeaut-hdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/milbeaut-hdmac.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/milbeaut-xdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/milbeaut-xdmac.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/pl330.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/pl330.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/sf-pdma/sf-pdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sf-pdma/sf-pdma.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/sf-pdma/sf-pdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sf-pdma/sf-pdma.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/sh/rz-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/rz-dmac.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/sh/shdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/shdma.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/sh/usb-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/usb-dmac.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ste_dma40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ste_dma40.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/stm32-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/stm32-dma.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/tegra186-gpc-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/tegra186-gpc-dma.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/tegra210-adma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/tegra210-adma.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-psil-am62.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-psil-am62a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62a.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-psil-am62p.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62p.c</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-psil-priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-priv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-psil.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/ti/k3-udma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-udma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/uniphier-mdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/uniphier-mdmac.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/uniphier-xdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/uniphier-xdmac.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/xilinx/xdma-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xdma-regs.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/xilinx/xdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xdma.c</a></td><td class='right'>349</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dma/xilinx/xilinx_dpdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xilinx_dpdma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dpll/dpll_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dpll/dpll_core.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/dpll/dpll_netlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dpll/dpll_netlink.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/altera_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/altera_edac.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/amd64_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/amd64_edac.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/amd64_edac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/amd64_edac.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/armada_xp_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/armada_xp_edac.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/aspeed_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/aspeed_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/bluefield_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/bluefield_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/cell_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/cell_edac.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/cpc925_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/cpc925_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/dmc520_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/dmc520_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/edac_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_device.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/edac_device_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_device_sysfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/edac_mc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_mc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/edac_module.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_module.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/edac_pci_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_pci_sysfs.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/fsl_ddr_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/fsl_ddr_edac.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/fsl_ddr_edac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/fsl_ddr_edac.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/highbank_l2_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/highbank_l2_edac.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/highbank_mc_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/highbank_mc_edac.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/i7core_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/i7core_edac.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/igen6_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/igen6_edac.c</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/layerscape_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/layerscape_edac.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/mce_amd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/mce_amd.c</a></td><td class='right'>526</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 5.8%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/mpc85xx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/mpc85xx_edac.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/npcm_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/npcm_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/octeon_edac-l2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-l2c.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/octeon_edac-lmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-lmc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/octeon_edac-pc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-pc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/octeon_edac-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-pci.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/pnd2_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/pnd2_edac.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/ppc4xx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/ppc4xx_edac.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/qcom_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/qcom_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/sb_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/sb_edac.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/skx_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/skx_common.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/synopsys_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/synopsys_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/thunderx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/thunderx_edac.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/ti_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/ti_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/versal_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/versal_edac.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/xgene_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/xgene_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/edac/zynqmp_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/zynqmp_edac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/extcon/extcon-qcom-spmi-misc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon-qcom-spmi-misc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/extcon/extcon-usbc-tusb320.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon-usbc-tusb320.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/extcon/extcon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firewire/.kunitconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/.kunitconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firewire/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/Kconfig</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firewire/core-device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/core-device.c</a></td><td class='right'>140</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firewire/device-attribute-test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/device-attribute-test.c</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firewire/ohci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/ohci.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firewire/sbp2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/sbp2.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_ffa/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_ffa/driver.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/Kconfig</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/base.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/clock.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/driver.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/optee.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/optee.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/perf.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/power.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/powercap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/powercap.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/protocols.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/protocols.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/reset.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/sensors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/sensors.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/system.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/system.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scmi/voltage.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/voltage.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/arm_scpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scpi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/Kconfig</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/dev-path-parser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/dev-path-parser.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/efi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/efi.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/Makefile.zboot?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/Makefile.zboot</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/loongarch-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch-stub.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/loongarch-stub.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch-stub.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/loongarch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/x86-5lvl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/x86-5lvl.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/libstub/x86-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/x86-stub.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/memmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/memmap.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/efi/stmm/mm_communication.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/stmm/mm_communication.h</a></td><td class='right'>236</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/efi/stmm/tee_stmm_efi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/stmm/tee_stmm_efi.c</a></td><td class='right'>616</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/unaccepted_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/unaccepted_memory.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/efi/vars.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/vars.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/google/coreboot_table.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/google/coreboot_table.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/google/framebuffer-coreboot.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/google/framebuffer-coreboot.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/imx/imx-dsp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/imx/imx-dsp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/meson/meson_sm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/meson/meson_sm.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/microchip/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/Kconfig</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/microchip/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/firmware/microchip/mpfs-auto-update.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/mpfs-auto-update.c</a></td><td class='right'>494</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/mtk-adsp-ipc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/mtk-adsp-ipc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/qcom/qcom_qseecom_uefisecapp.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/qemu_fw_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/qemu_fw_cfg.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/raspberrypi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/raspberrypi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/stratix10-rsu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/stratix10-rsu.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/stratix10-svc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/stratix10-svc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/ti_sci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/ti_sci.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/turris-mox-rwtm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/turris-mox-rwtm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/firmware/xilinx/zynqmp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/xilinx/zynqmp.c</a></td><td class='right'>396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/altera-fpga2sdram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-fpga2sdram.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/altera-freeze-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-freeze-bridge.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/altera-hps2fpga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-hps2fpga.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/dfl-afu-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-afu-main.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/dfl-fme-br.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-br.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/dfl-fme-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-main.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/dfl-fme-region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-region.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/dfl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/intel-m10-bmc-sec-update.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/intel-m10-bmc-sec-update.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/of-fpga-region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/of-fpga-region.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/socfpga-a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/socfpga-a10.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/stratix10-soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/stratix10-soc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/xilinx-pr-decoupler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/xilinx-pr-decoupler.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/fpga/zynq-fpga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/zynq-fpga.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gnss/serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/serial.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gnss/sirf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/sirf.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gnss/ubx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/ubx.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/Kconfig</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-dwapb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-dwapb.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-elkhartlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-elkhartlake.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-en7523.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-en7523.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-ixp4xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-ixp4xx.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-max730x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-max730x.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-mlxbf3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mlxbf3.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mmio.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-mockup.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mockup.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-npcm-sgpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-npcm-sgpio.c</a></td><td class='right'>619</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-pmic-eic-sprd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-pmic-eic-sprd.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-rtd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-rtd.c</a></td><td class='right'>607</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-sifive.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-sifive.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-sim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-sim.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-stmpe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-stmpe.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-tangier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tangier.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-tangier.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tangier.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-tps65219.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tps65219.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-wm831x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-wm831x.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-wm8994.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-wm8994.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpio-xilinx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-xilinx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib-cdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-cdev.c</a></td><td class='right'>655</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib-of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-of.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib-sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-sysfs.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib-sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-sysfs.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib.c</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpio/gpiolib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a></td><td class='right'>199</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a></td><td class='right'>172</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a></td><td class='right'>414</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/athub_v3_0.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/atom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/atom.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/soc15.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/soc15.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/soc15.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/soc15.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v6_7.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a></td><td class='right'>664</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a></td><td class='right'>185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a></td><td class='right'>125</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a></td><td class='right'>535</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a></td><td class='right'>829</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.2%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 90.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a></td><td class='right'>232</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c</a></td><td class='right'>216</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/Makefile</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/basics/conversion.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/basics/conversion.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/bios/command_table2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/command_table2.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc.c</a></td><td class='right'>398</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a></td><td class='right'>187</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a></td><td class='right'>487</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 4.6%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_state.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_state.c</a></td><td class='right'>867</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a></td><td class='right'>290</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_plane.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_plane.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_plane_priv.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_state.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_state.h</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_state_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_state_priv.h</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_stream.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_stream_priv.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_types.h</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce100/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce100/Makefile</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn302/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn302/Makefile</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn303/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn303/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn314/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn314/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn315/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn315/Makefile</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn316/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn316/Makefile</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/Makefile</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn321/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn321/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dc_features.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dc_features.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/dsc/dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dsc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a></td><td class='right'>271</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c)</td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/abm.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/link.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/link.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/inc/resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a></td><td class='right'>198</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a></td><td class='right'>379</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/Makefile</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c)</td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c)</td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/Makefile</a></td><td class='right'>199</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c)</td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c)</td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c)</td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c)</td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c)</td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c)</td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h)</td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c)</td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c)</td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h</a> (renamed from drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h)</td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/include/audio_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/audio_types.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/hdcp_msg_types.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/amd_shared.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/amd_shared.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/amdgpu_reg_state.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/amdgpu_reg_state.h</a></td><td class='right'>153</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/kgd_pp_interface.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/kgd_pp_interface.h</a></td><td class='right'>116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/include/mes_v11_api_def.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/mes_v11_api_def.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/amdgpu_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/amdgpu_dpm.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/amdgpu_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/amdgpu_pm.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c</a></td><td class='right'>273</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu_internal.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/arm/malidp_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/arm/malidp_crtc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/ast/ast_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ast/ast_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/aux-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/aux-bridge.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/aux-hpd-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/aux-hpd-bridge.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/panel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/panel.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/parade-ps8640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/parade-ps8640.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/synopsys/dw-hdmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/bridge/ti-sn65dsi86.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/ti-sn65dsi86.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/ci/build.sh?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ci/build.sh</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/display/drm_dp_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/display/drm_dp_helper.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/display/drm_dp_mst_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/display/drm_dp_mst_topology.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_atomic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_atomic_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_helper.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_atomic_state_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_state_helper.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_atomic_uapi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_uapi.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_auth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_auth.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_crtc.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_edid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_edid.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_exec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_exec.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_framebuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_framebuffer.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_gpuvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_gpuvm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_modes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_modes.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_plane.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_prime.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_prime.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_property.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/drm_syncobj.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_syncobj.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos5433_drm_decon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos5433_drm_decon.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos7_drm_decon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos7_drm_decon.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_dp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_dma.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_dpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_dpi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_drv.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_fimc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_fimc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_fimd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_fimd.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_g2d.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_g2d.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_gsc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_mic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_mic.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_rotator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_rotator.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_scaler.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_drm_vidi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_vidi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_hdmi.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/exynos/exynos_mixer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_mixer.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/gma500/cdv_intel_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/cdv_intel_dp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/gma500/intel_gmbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/intel_gmbus.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/gma500/psb_intel_sdvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/psb_intel_sdvo.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/hyperv/hyperv_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/hyperv/hyperv_drm_drv.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/Kconfig.debug?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/Kconfig.debug</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/i9xx_wm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/i9xx_wm.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/icl_dsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/icl_dsi.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_backlight.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_backlight.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_bios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_bios.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_bw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_bw.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_cdclk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cdclk.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_crt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crt.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crtc.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crtc_state_dump.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_cursor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cursor.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_cx0_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cx0_phy.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_ddi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_ddi.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_ddi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_ddi.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_core.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_debugfs.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_device.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_driver.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_irq.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_power.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_display_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_types.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dmc.c</a></td><td class='right'>147</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dmc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dmc_regs.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dp_link_training.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp_link_training.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dp_mst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp_mst.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dpll_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dpll_mgr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dsb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dsi_vbt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsi_vbt.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dsi_vbt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsi_vbt.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_dvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dvo.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb.c</a></td><td class='right'>181</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fb_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb_bo.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fb_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb_bo.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fbc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fbdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev.c</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fbdev_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev_fb.c</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_fbdev_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev_fb.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_gmbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_gmbus.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_hdmi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_lvds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_lvds.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_psr.c</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_psr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_psr.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_sdvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_sdvo.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_snps_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_snps_phy.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_tc.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_tv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_tv.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_vblank.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_vblank.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/intel_vdsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_vdsc.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/skl_scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/skl_scaler.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/skl_universal_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/skl_universal_plane.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/display/vlv_dsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/vlv_dsi.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_context.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_context_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_context_types.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_internal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_internal.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_object.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_object.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_object_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_object_types.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_phys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_phys.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_shmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_shmem.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/i915_gem_stolen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_stolen.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/huge_pages.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/huge_pages.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gem/selftests/mock_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/mock_context.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/gen8_ppgtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/gen8_ppgtt.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_breadcrumbs.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_context.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_context_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context_types.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_cs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_pm.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_regs.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_types.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_engine_user.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_user.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_execlists_submission.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_execlists_submission.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_ggtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_ggtt.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gsc.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt_mcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_mcr.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gt_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_regs.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gtt.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_gtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gtt.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_lrc.c</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_reset.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_sseu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_sseu.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/intel_workarounds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_workarounds.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_engine_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_engine_cs.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_gt_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_gt_pm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_lrc.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_reset.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_rps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_rps.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/selftest_slpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_slpc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc.h</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_log.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_uc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_uc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/selftest_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/selftest_guc.c</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/gvt/interrupt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gvt/interrupt.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_cmd_parser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_cmd_parser.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_debugfs.c</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_driver.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_drm_client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_drm_client.c</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_drm_client.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_drm_client.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_gpu_error.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_gpu_error.c</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_gpu_error.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_gpu_error.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_hwmon.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_memcpy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_memcpy.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_perf.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_perf_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_perf_types.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_pmu.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/i915_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_sysfs.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_memory_region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_memory_region.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_memory_region.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_memory_region.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_runtime_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_runtime_pm.c</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_runtime_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_runtime_pm.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_wakeref.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_wakeref.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/intel_wakeref.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_wakeref.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/pxp/intel_pxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_irq.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/pxp/intel_pxp_session.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_session.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/pxp/intel_pxp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_types.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/selftests/i915_syncmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/i915_syncmap.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/selftests/igt_live_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/igt_live_test.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/i915/selftests/igt_live_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/igt_live_test.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/imagination/pvr_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_device.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/imagination/pvr_hwrt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_hwrt.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/imagination/pvr_job.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_job.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/imagination/pvr_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_vm.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/imagination/pvr_vm_mips.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_vm_mips.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/lima/lima_ctx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/lima/lima_ctx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/loongson/lsdc_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/loongson/lsdc_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_cec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_cec.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_aal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_aal.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_ccorr.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_drv.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_gamma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_gamma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_merge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_merge.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c</a></td><td class='right'>248</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_dp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_dpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_dpi.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_crtc.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_drv.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_drm_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_drv.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_mdp_rdma.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mediatek/mtk_padding.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_padding.c</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_drv.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_g200er.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200er.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_g200ev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200ev.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_g200se.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200se.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/mgag200/mgag200_mode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_mode.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/adreno/a5xx_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/a5xx_gpu.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/adreno/a6xx_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/a6xx_gpu.c</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/adreno/adreno_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_device.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/adreno/adreno_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_gpu.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/adreno/adreno_gpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_gpu.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h</a></td><td class='right'>457</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c</a></td><td class='right'>141</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_aux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_aux.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_debug.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_debug.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_display.c</a></td><td class='right'>369</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_display.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_drm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_drm.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_power.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dp/dp_power.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_power.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dsi/dsi_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/dsi_cfg.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dsi/dsi_cfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/dsi_cfg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/hdmi/hdmi_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_debugfs.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_drv.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_drv.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_gem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_gem_shrinker.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem_shrinker.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_gem_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem_submit.c</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gpu.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_mdss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_mdss.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_mdss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_mdss.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_rd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_rd.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/msm/msm_ringbuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_ringbuffer.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/dispnv50/disp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/dispnv50/disp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nouveau_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_bo.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nouveau_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_fence.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nouveau_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_fence.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nouveau_uvmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_uvmm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nouveau_vmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_vmm.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/panel/panel-novatek-nt36523.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-novatek-nt36523.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/panfrost/panfrost_devfreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panfrost/panfrost_devfreq.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/panfrost/panfrost_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panfrost/panfrost_gem.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/atombios_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/atombios_encoders.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/clearstate_evergreen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/clearstate_evergreen.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/dce3_1_afmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/dce3_1_afmt.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/dce6_afmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/dce6_afmt.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/evergreen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/evergreen.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/evergreen_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/evergreen_hdmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/r100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/r100.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/r600_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/r600_cs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_atombios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_atombios.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_audio.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_audio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_audio.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_combios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_combios.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_display.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_encoders.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_mode.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_ring.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/radeon_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_vm.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/si.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/si.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/sumo_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/sumo_dpm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/radeon/trinity_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/trinity_dpm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/rockchip/inno_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/inno_hdmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/rockchip/rk3066_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/rk3066_hdmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/rockchip_drm_vop2.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/solomon/ssd130x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/solomon/ssd130x.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/tests/drm_exec_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/tests/drm_exec_test.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/tests/drm_kunit_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/tests/drm_kunit_helpers.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/ttm/tests/ttm_device_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/tests/ttm_device_test.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/ttm/tests/ttm_pool_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/tests/ttm_pool_test.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/ttm/ttm_pool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/ttm_pool.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/v3d/v3d_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/v3d/v3d_debugfs.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/gpu/drm/vc4/tests/vc4_mock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/vc4/tests/vc4_mock.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/.gitignore?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/.gitignore</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/.kunitconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/.kunitconfig</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/Kconfig.debug?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig.debug</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/Kconfig.profile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig.profile</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Makefile</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/gsc_command_header_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_command_header_abi.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_actions_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_actions_abi.h</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h</a></td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_errors_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_errors_abi.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_klvs_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_klvs_abi.h</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/abi/guc_messages_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_messages_abi.h</a></td><td class='right'>234</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_active.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_active.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_config.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_step.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/ext/i915_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/ext/i915_irq.c</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/ext/i915_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/ext/i915_utils.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/intel_fb_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fb_bo.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/intel_fb_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fb_bo.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/intel_fbdev_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fbdev_fb.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/intel_fbdev_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fbdev_fb.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_display_misc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_display_misc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_display_rps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_display_rps.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_dsb_buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_dsb_buffer.c</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_fb_pin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_fb_pin.c</a></td><td class='right'>384</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_hdcp_gsc.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/display/xe_plane_initial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_plane_initial.c</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/instructions/xe_gsc_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_gsc_commands.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/instructions/xe_instr_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_instr_defs.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/instructions/xe_mi_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_mi_commands.h</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_engine_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_engine_regs.h</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_gpu_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gpu_commands.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_gsc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gsc_regs.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_gt_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gt_regs.h</a></td><td class='right'>478</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_guc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_guc_regs.h</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_lrc_layout.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_lrc_layout.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_mchbar_regs.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_reg_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_reg_defs.h</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_regs.h</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/regs/xe_sriov_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_sriov_regs.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/Makefile</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo.c</a></td><td class='right'>352</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_bo_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo_test.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_bo_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo_test.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf.c</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_dma_buf_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf_test.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_dma_buf_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf_test.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_lmtt_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_lmtt_test.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate.c</a></td><td class='right'>444</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_migrate_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate_test.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_migrate_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate_test.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_mocs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_mocs_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs_test.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_mocs_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs_test.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_pci_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci_test.c</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_pci_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci_test.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_rtp_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_rtp_test.c</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_test.h</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/tests/xe_wa_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_wa_test.c</a></td><td class='right'>170</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_assert.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_assert.h</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bb_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb_types.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo.c</a></td><td class='right'>2269</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo.h</a></td><td class='right'>355</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_doc.h</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo_evict.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_evict.c</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo_evict.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_evict.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_bo_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_types.h</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_debugfs.c</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_debugfs.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_devcoredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump.c</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_devcoredump.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_devcoredump_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump_types.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device.c</a></td><td class='right'>700</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device.h</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_device_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_sysfs.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_device_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_sysfs.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_device_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_types.h</a></td><td class='right'>545</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_display.c</a></td><td class='right'>422</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_display.h</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_dma_buf.c</a></td><td class='right'>322</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_dma_buf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_dma_buf.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_drm_client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drm_client.c</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_drm_client.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drm_client.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drv.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_exec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec.c</a></td><td class='right'>351</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_exec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_exec_queue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue.c</a></td><td class='right'>961</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_exec_queue.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue.h</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_exec_queue_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue_types.h</a></td><td class='right'>224</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_execlist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist.c</a></td><td class='right'>474</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_execlist.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_execlist_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist_types.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_force_wake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake.c</a></td><td class='right'>199</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_force_wake.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_force_wake_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake_types.h</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gen_wa_oob.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gen_wa_oob.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ggtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt.c</a></td><td class='right'>428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ggtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ggtt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt_types.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gpu_scheduler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler.c</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gpu_scheduler.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler_types.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc.c</a></td><td class='right'>438</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gsc_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_submit.c</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gsc_submit.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_submit.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gsc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_types.h</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt.c</a></td><td class='right'>778</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt.h</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_ccs_mode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_ccs_mode.c</a></td><td class='right'>191</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_ccs_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_ccs_mode.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_clock.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_clock.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_clock.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_debugfs.c</a></td><td class='right'>249</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_debugfs.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_freq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_freq.c</a></td><td class='right'>222</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_freq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_freq.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_idle.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle.c</a></td><td class='right'>192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_idle.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_idle_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle_types.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_mcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_mcr.c</a></td><td class='right'>685</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_mcr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_mcr.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_pagefault.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_pagefault.c</a></td><td class='right'>646</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_pagefault.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_pagefault.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_printk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_printk.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_sysfs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs_types.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c</a></td><td class='right'>406</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_topology.c</a></td><td class='right'>169</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_topology.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_topology.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_gt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_types.h</a></td><td class='right'>363</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc.c</a></td><td class='right'>916</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc.h</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ads.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads.c</a></td><td class='right'>672</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ads.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ads_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads_types.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ct.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct.c</a></td><td class='right'>1320</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ct.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_ct_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct_types.h</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_debugfs.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_debugfs.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_exec_queue_types.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_fwif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_fwif.h</a></td><td class='right'>361</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_hwconfig.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_hwconfig.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_hwconfig.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_hwconfig.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_log.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_log.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_log_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log_types.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_pc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc.c</a></td><td class='right'>1000</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_pc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_pc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc_types.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit.c</a></td><td class='right'>1989</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 24.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 76.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_submit.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_submit_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit_types.h</a></td><td class='right'>155</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_guc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_types.h</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_heci_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_heci_gsc.c</a></td><td class='right'>234</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_heci_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_heci_gsc.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_huc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc.c</a></td><td class='right'>307</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_huc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_huc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_debugfs.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_huc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_debugfs.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_huc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_types.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_engine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine.c</a></td><td class='right'>883</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_engine.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c</a></td><td class='right'>675</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_engine_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_types.h</a></td><td class='right'>225</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence.c</a></td><td class='right'>230</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hw_fence_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence_types.h</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hwmon.c</a></td><td class='right'>776</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_hwmon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hwmon.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_irq.c</a></td><td class='right'>666</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_irq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_irq.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lmtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt.c</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lmtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lmtt_2l.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_2l.c</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lmtt_ml.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_ml.c</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lmtt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_types.h</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc.c</a></td><td class='right'>1272</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 15.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 84.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lrc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc.h</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_lrc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc_types.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_macros.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_macros.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_map.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_map.h</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate.c</a></td><td class='right'>1439</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_migrate.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate.h</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_migrate_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate_doc.h</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mmio.c</a></td><td class='right'>524</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_mmio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mmio.h</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_mocs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mocs.c</a></td><td class='right'>580</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_mocs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mocs.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_module.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_module.c</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_module.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_module.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pat.c</a></td><td class='right'>459</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pat.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pat.h</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci.c</a></td><td class='right'>951</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pci_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci_types.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pcode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode.c</a></td><td class='right'>296</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pcode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pcode_api.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode_api.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_platform_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_platform_types.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pm.c</a></td><td class='right'>405</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pm.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_preempt_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence.c</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_preempt_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence.h</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_preempt_fence_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence_types.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt.c</a></td><td class='right'>1653</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 19.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 80.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_types.h</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pt_walk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_walk.c</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_pt_walk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_walk.h</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_query.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_query.c</a></td><td class='right'>552</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_query.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_query.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_range_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_range_fence.c</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_range_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_range_fence.h</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_reg_sr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr.c</a></td><td class='right'>284</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_reg_sr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_reg_sr_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr_types.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_reg_whitelist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_whitelist.c</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_reg_whitelist.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_whitelist.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_res_cursor.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_res_cursor.h</a></td><td class='right'>240</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ring_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops.c</a></td><td class='right'>482</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ring_ops.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ring_ops_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops_types.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_rtp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp.c</a></td><td class='right'>325</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_rtp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp.h</a></td><td class='right'>430</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_rtp_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp_helpers.h</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_rtp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp_types.h</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sa_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa_types.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sched_job.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job.c</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sched_job.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job.h</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sched_job_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job_types.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sriov.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sriov_printk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov_printk.h</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sriov_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov_types.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_step.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step.c</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_step.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_step_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step_types.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync.c</a></td><td class='right'>344</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sync.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_sync_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync_types.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tile.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile.c</a></td><td class='right'>185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tile.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tile_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tile_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tile_sysfs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs_types.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_trace.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_trace.h</a></td><td class='right'>608</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_sys_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_sys_mgr.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_sys_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_sys_mgr.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr.c</a></td><td class='right'>480</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tuning.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tuning.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_tuning.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tuning.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc.c</a></td><td class='right'>258</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_debugfs.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_debugfs.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw.c</a></td><td class='right'>882</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw.h</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_fw_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw_abi.h</a></td><td class='right'>321</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_fw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw_types.h</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_uc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_types.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm.c</a></td><td class='right'>3212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 38.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 61.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_vm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm.h</a></td><td class='right'>263</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_vm_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm_doc.h</a></td><td class='right'>555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_vm_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm_types.h</a></td><td class='right'>373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa.c</a></td><td class='right'>895</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wa_oob.rules?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa_oob.rules</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wait_user_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wait_user_fence.c</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wait_user_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wait_user_fence.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wopcm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm.c</a></td><td class='right'>270</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wopcm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/gpu/drm/xe/xe_wopcm_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm_types.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/greybus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/greybus/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/greybus/gb-beagleplay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/greybus/gb-beagleplay.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/Kconfig</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/amd-sfh-hid/amd_sfh_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/amd_sfh_common.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-apple.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-apple.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-ids.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-ids.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-lenovo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-lenovo.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-magicmouse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-magicmouse.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/hid/hid-mcp2200.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-mcp2200.c</a></td><td class='right'>392</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-mcp2221.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-mcp2221.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-nintendo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-nintendo.c</a></td><td class='right'>968</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.2%;'/><td class='rem' style='width: 3.5%;'/><td class='none' style='width: 88.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-quirks.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-quirks.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-sensor-hub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-sensor-hub.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/hid-steam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-steam.c</a></td><td class='right'>547</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/i2c-hid/i2c-hid-acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-acpi.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/i2c-hid/i2c-hid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-core.c</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/i2c-hid/i2c-hid-of-elan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-of-elan.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/intel-ish-hid/ipc/pci-ish.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ipc/pci-ish.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/intel-ish-hid/ishtp-fw-loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp-fw-loader.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/intel-ish-hid/ishtp-hid-client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp-hid-client.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/intel-ish-hid/ishtp/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp/bus.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/intel-ish-hid/ishtp/client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp/client.c</a></td><td class='right'>185</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/uhid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/uhid.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/wacom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/wacom_sys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_sys.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/wacom_wac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_wac.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hid/wacom_wac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_wac.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hsi/controllers/omap_ssi_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hsi/controllers/omap_ssi_core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hv/hv_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hv/hv_common.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/acpi_power_meter.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/acpi_power_meter.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/aquacomputer_d5next.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/aquacomputer_d5next.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/aspeed-pwm-tacho.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/aspeed-pwm-tacho.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/corsair-cpro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/corsair-cpro.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/corsair-psu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/corsair-psu.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/dell-smm-hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/dell-smm-hwmon.c</a></td><td class='right'>604</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/emc1403.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/emc1403.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/hwmon/gigabyte_waterforce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/gigabyte_waterforce.c</a></td><td class='right'>430</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/hp-wmi-sensors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/hp-wmi-sensors.c</a></td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/k10temp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/k10temp.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/lm75.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/lm75.c</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/ltc2991.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/ltc2991.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/max31827.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/max31827.c</a></td><td class='right'>274</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/max6650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/max6650.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/nct6775-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-core.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/nct6775-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-i2c.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/nct6775-platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-platform.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/nct6775.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/npcm750-pwm-fan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/npcm750-pwm-fan.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/nzxt-kraken2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nzxt-kraken2.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/pc87360.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pc87360.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/peci/dimmtemp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/peci/dimmtemp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/Kconfig</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/lm25066.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/lm25066.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/ltc4286.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/ltc4286.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/mp2856.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/mp2856.c</a></td><td class='right'>466</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/hwmon/pmbus/mp5990.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/mp5990.c</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/pwm-fan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pwm-fan.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/sht4x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/sht4x.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/smsc47m1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/smsc47m1.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwmon/tmp513.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/tmp513.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwspinlock/hwspinlock_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwspinlock/hwspinlock_core.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwspinlock/qcom_hwspinlock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwspinlock/qcom_hwspinlock.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-core.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-dummy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-dummy.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-etm-perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm-perf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-etm4x-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm4x-core.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-etm4x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm4x.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-funnel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-funnel.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-replicator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-replicator.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tmc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc-core.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tmc-etr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc-etr.c</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tpda.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpda.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tpda.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpda.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tpdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpdm.c</a></td><td class='right'>718</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 91.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-tpdm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpdm.h</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-trbe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-trbe.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/coresight-trbe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-trbe.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/ultrasoc-smb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/ultrasoc-smb.c</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/coresight/ultrasoc-smb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/ultrasoc-smb.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/ptt/hisi_ptt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/ptt/hisi_ptt.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/hwtracing/ptt/hisi_ptt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/ptt/hisi_ptt.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-ali1535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali1535.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-ali1563.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali1563.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-ali15x3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali15x3.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-amd756.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-amd756.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-amd8111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-amd8111.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-aspeed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-aspeed.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-cpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-cpm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-elektor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-elektor.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-gpio.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-i801.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-i801.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-ibm_iic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ibm_iic.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-imx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-iop3xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-iop3xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-isch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-isch.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-kempld.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-kempld.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-mlxcpld.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-mlxcpld.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-nforce2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-nforce2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-npcm7xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-npcm7xx.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-pasemi-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-pasemi-pci.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-piix4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-piix4.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-qcom-geni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-qcom-geni.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-rcar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-rcar.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-rk3x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-rk3x.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-s3c2410.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-s3c2410.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-scmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-scmi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-sh7760.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sh7760.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-sibyte.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sibyte.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-sis5595.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis5595.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-sis630.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis630.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-sis96x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis96x.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-stm32f7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-stm32f7.c</a></td><td class='right'>342</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 95.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-via.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-via.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-viapro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-viapro.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/i2c-wmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-wmt.c</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/busses/scx200_acb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/scx200_acb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/i2c-core-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-core-base.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/i2c-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-core.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/i2c-smbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-smbus.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/i2c-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-stub.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i2c/muxes/i2c-mux-reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/muxes/i2c-mux-reg.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master.c</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/i3c-master-cdns.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/i3c-master-cdns.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/cmd_v1.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/mipi-i3c-hci/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/core.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/mipi-i3c-hci/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/dma.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/mipi-i3c-hci/hci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/hci.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/i3c/master/svc-i3c-master.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/svc-i3c-master.c</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/idle/intel_idle.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/idle/intel_idle.c</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/accel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/Kconfig</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/accel/bmi088-accel-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/bmi088-accel-core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/accel/bmi088-accel-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/bmi088-accel-spi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/accel/kionix-kx022a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/kionix-kx022a.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/Kconfig</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/ad7091r-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r-base.c</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/ad7091r-base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r-base.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/ad7091r5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r5.c</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/adc/ad7091r8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r8.c</a></td><td class='right'>272</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/ad9467.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad9467.c</a></td><td class='right'>207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/adi-axi-adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/adi-axi-adc.c</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/imx93_adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/imx93_adc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/adc/max34408.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/max34408.c</a></td><td class='right'>276</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/mcp3564.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/mcp3564.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/mcp3911.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/mcp3911.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/meson_saradc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/meson_saradc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/adc/ti_am335x_adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ti_am335x_adc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/amplifiers/hmc425a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/amplifiers/hmc425a.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/buffer/industrialio-buffer-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/buffer/industrialio-buffer-dma.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/buffer/industrialio-triggered-buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/buffer/industrialio-triggered-buffer.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/chemical/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/chemical/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/chemical/ags02ma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/ags02ma.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/chemical/pms7003.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/pms7003.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/chemical/scd30_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/scd30_serial.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/chemical/sps30_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/sps30_serial.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/common/ms_sensors/ms_sensors_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/common/ms_sensors/ms_sensors_i2c.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/dac/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/dac/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/dac/ad5791.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/ad5791.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/dac/mcp4821.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/mcp4821.c</a></td><td class='right'>236</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/frequency/adf4377.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/frequency/adf4377.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/frequency/admv1014.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/frequency/admv1014.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/humidity/hdc3020.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/humidity/hdc3020.c</a></td><td class='right'>473</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/adis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/adis.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/adis16475.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/adis16475.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/Kconfig</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/Makefile</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/bmi323.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323.h</a></td><td class='right'>209</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/bmi323_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_core.c</a></td><td class='right'>2139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 25.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 74.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/bmi323_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_i2c.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/imu/bmi323/bmi323_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_spi.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/bno055/bno055_ser_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bno055/bno055_ser_core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_mpu6050/inv_mpu_core.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/industrialio-buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/industrialio-buffer.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/industrialio-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/industrialio-core.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/Kconfig</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/hid-sensor-als.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/hid-sensor-als.c</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/light/isl76682.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/isl76682.c</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/light/ltr390.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/ltr390.c</a></td><td class='right'>196</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/ltrf216a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/ltrf216a.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/pa12203001.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/pa12203001.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/light/rohm-bu27008.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/rohm-bu27008.c</a></td><td class='right'>201</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/light/veml6075.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/veml6075.c</a></td><td class='right'>474</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/magnetometer/tmag5273.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/magnetometer/tmag5273.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/Kconfig</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/bmp280-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-core.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/bmp280-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-i2c.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/bmp280-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-spi.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/pressure/bmp280.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/pressure/hsc030pa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa.c</a></td><td class='right'>494</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/pressure/hsc030pa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa.h</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/pressure/hsc030pa_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa_i2c.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/pressure/hsc030pa_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa_spi.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/proximity/irsd200.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/proximity/irsd200.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/proximity/sx9324.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/proximity/sx9324.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/resolver/ad2s1210.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/resolver/ad2s1210.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/temperature/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/Kconfig</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iio/temperature/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/temperature/mcp9600.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/mcp9600.c</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/iio/temperature/mlx90635.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/mlx90635.c</a></td><td class='right'>1097</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 13.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 86.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/core/umem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/core/umem.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/core/verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/core/verbs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/bnxt_re.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/bnxt_re.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/hw_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/hw_counters.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/ib_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/ib_verbs.c</a></td><td class='right'>233</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/ib_verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/ib_verbs.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/main.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_fp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_fp.c</a></td><td class='right'>215</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_fp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_fp.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_res.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_res.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_res.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_res.h</a></td><td class='right'>117</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/qplib_sp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_sp.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/bnxt_re/roce_hsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/roce_hsi.h</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa_admin_cmds_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_admin_cmds_defs.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa_com_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_com_cmd.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa_com_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_com_cmd.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_main.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/efa/efa_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_verbs.c</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/erdma/erdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/erdma/erdma_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_hw.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/erdma/erdma_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_main.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/erdma/erdma_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_verbs.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/erdma/erdma_verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_verbs.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hfi1/user_exp_rcv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hfi1/user_exp_rcv.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hfi1/user_sdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hfi1/user_sdma.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_ah.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_ah.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_cmd.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_cq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_cq.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_debugfs.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_debugfs.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_device.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_hw_v2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_hw_v2.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_main.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_mr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_mr.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_pd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_pd.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_qp.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/hns/hns_roce_srq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_srq.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/hw.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/main.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/utils.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/verbs.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/irdma/verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/verbs.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mana/cq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/cq.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mana/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/device.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mana/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/main.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mana/mana_ib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/mana_ib.h</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mana/qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/qp.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mlx5/devx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/devx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mlx5/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/dm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mlx5/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/main.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mlx5/mr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/mr.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mthca/mthca_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mthca/mthca_cmd.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/hw/mthca/mthca_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mthca/mthca_main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_cm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_cm.c</a></td><td class='right'>145</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_main.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_mem.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_mem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_mem.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_qp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp_rx.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_qp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp_tx.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/sw/siw/siw_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_verbs.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/ipoib/ipoib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/ipoib/ipoib_ib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_ib.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/ipoib/ipoib_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_main.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/ipoib/ipoib_multicast.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_multicast.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/iser/iscsi_iser.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iscsi_iser.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/iser/iser_initiator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_initiator.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/iser/iser_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_memory.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/iser/iser_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_verbs.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/rtrs/rtrs-clt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs-clt.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/rtrs/rtrs-srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs-srv.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/infiniband/ulp/rtrs/rtrs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/input.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/input.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/joystick/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/joystick/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/input/joystick/adafruit-seesaw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/adafruit-seesaw.c</a></td><td class='right'>315</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/joystick/as5011.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/as5011.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/joystick/pxrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/pxrc.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/joystick/xpad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/xpad.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/atkbd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/atkbd.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/cap11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/cap11xx.c</a></td><td class='right'>253</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/gpio_keys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/gpio_keys.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/ipaq-micro-keys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/ipaq-micro-keys.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/omap-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/omap-keypad.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/omap4-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/omap4-keypad.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/qt1050.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/qt1050.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/keyboard/tca6416-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/tca6416-keypad.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/da7280.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/da7280.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/da9063_onkey.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/da9063_onkey.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/ims-pcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/ims-pcu.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/iqs269a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/iqs269a.c</a></td><td class='right'>335</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/max77693-haptic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/max77693-haptic.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/pwm-beeper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/pwm-beeper.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/pwm-vibra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/pwm-vibra.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/misc/soc_button_array.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/soc_button_array.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/amimouse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/amimouse.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/cyapa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/cyapa_gen3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen3.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/cyapa_gen5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen5.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/cyapa_gen6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen6.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/elan_i2c_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/elan_i2c_core.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/navpoint.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/navpoint.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/mouse/synaptics.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/synaptics.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/rmi4/rmi_f01.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/rmi4/rmi_f01.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/rmi4/rmi_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/rmi4/rmi_spi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/serio/i8042-acpipnpio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/serio/i8042-acpipnpio.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/atmel_mxt_ts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/atmel_mxt_ts.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/edt-ft5x06.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/edt-ft5x06.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/hideep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/hideep.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/hycon-hy46xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/hycon-hy46xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/ilitek_ts_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/ilitek_ts_i2c.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/iqs5xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/iqs5xx.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/iqs7211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/iqs7211.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/melfas_mip4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/melfas_mip4.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/sur40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/sur40.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/usbtouchscreen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/usbtouchscreen.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/wdt87xx_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/wdt87xx_i2c.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/touchscreen/zforce_ts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/zforce_ts.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/input/vivaldi-fmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/vivaldi-fmap.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/core.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/imx/imx8mm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mm.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/imx/imx8mn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mn.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/imx/imx8mp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mp.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/imx/imx8mq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mq.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/Kconfig</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/icc-rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/icc-rpm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/icc-rpm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/icc-rpm.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/msm8916.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8916.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/msm8939.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8939.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/msm8974.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8974.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/msm8996.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8996.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/osm-l3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/osm-l3.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/qcm2290.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/qcm2290.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/qcs404.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/qcs404.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/sdm660.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sdm660.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/sm6115.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm6115.c</a></td><td class='right'>1423</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/sm8250.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8250.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8650.c</a></td><td class='right'>1674</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 79.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/sm8650.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8650.h</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/smd-rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/smd-rpm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/x1e80100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/x1e80100.c</a></td><td class='right'>2328</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 28.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 71.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/interconnect/qcom/x1e80100.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/x1e80100.h</a></td><td class='right'>192</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/interconnect/samsung/exynos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/samsung/exynos.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/amd_iommu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/amd_iommu.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/amd_iommu_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/amd_iommu_types.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/init.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/io_pgtable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/io_pgtable.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/io_pgtable_v2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/io_pgtable_v2.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/amd/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/iommu.c</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/apple-dart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/apple-dart.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu/arm-smmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu/arm-smmu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/arm/arm-smmu/qcom_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/qcom_iommu.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/dma-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/dma-iommu.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/debugfs.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/dmar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/dmar.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/iommu.c</a></td><td class='right'>259</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/iommu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/iommu.h</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/irq_remapping.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/irq_remapping.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/nested.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/nested.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/pasid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/pasid.c</a></td><td class='right'>274</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/pasid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/pasid.h</a></td><td class='right'>223</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/intel/svm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/svm.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/io-pgtable-arm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/io-pgtable-arm.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/io-pgtable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/io-pgtable.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommu-sva.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommu-sva.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommu.c</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/device.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/hw_pagetable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/hw_pagetable.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/ioas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/ioas.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/iommufd_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/iommufd_private.h</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/iommufd_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/iommufd_test.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/main.c</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/selftest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/selftest.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/iommufd/vfio_compat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/vfio_compat.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/mtk_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/mtk_iommu.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/mtk_iommu_v1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/mtk_iommu_v1.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/of_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/of_iommu.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/omap-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/omap-iommu.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/sprd-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/sprd-iommu.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/iommu/virtio-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/virtio-iommu.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ipack/devices/ipoctal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ipack/devices/ipoctal.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ipack/ipack.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ipack/ipack.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/irqchip/irq-gic-v3-its.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-gic-v3-its.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/irqchip/irq-gic-v4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-gic-v4.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/irqchip/irq-qcom-mpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-qcom-mpm.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/irqchip/irq-renesas-rzg2l.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-renesas-rzg2l.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/irqchip/irq-xtensa-pic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-xtensa-pic.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/isdn/capi/capi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/isdn/capi/capi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/Kconfig</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/led-class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/led-class.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/led-triggers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/led-triggers.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/leds-aw200xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-aw200xx.c</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/leds-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-gpio.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/leds/leds-max5970.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-max5970.c</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/leds-pwm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-pwm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/leds/leds-sun50i-a100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-sun50i-a100.c</a></td><td class='right'>584</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/leds-syscon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-syscon.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/leds-tca6507.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-tca6507.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/rgb/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/rgb/leds-pwm-multicolor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/leds-pwm-multicolor.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/rgb/leds-qcom-lpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/leds-qcom-lpg.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/trigger/ledtrig-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-gpio.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/trigger/ledtrig-netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-netdev.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/trigger/ledtrig-panic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-panic.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/leds/trigger/ledtrig-tty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-tty.c</a></td><td class='right'>247</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/Kconfig</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/mailbox/apple-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/apple-mailbox.c</a></td><td class='right'>441</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.3%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/arm_mhuv2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/arm_mhuv2.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/bcm-flexrm-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/bcm-flexrm-mailbox.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/bcm-pdc-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/bcm-pdc-mailbox.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/imx-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/imx-mailbox.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/mailbox-test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/mailbox-test.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/mtk-cmdq-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/mtk-cmdq-mailbox.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/omap-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/omap-mailbox.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/qcom-apcs-ipc-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/qcom-apcs-ipc-mailbox.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/qcom-ipcc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/qcom-ipcc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/stm32-ipcc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/stm32-ipcc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/sun6i-msgbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/sun6i-msgbox.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/tegra-hsp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/tegra-hsp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mailbox/zynqmp-ipi-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/zynqmp-ipi-mailbox.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mcb/mcb-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mcb/mcb-core.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/Kconfig</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/Makefile</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/btree.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/btree.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/journal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/journal.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/movinggc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/movinggc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/request.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/request.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/request.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/request.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/super.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/super.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/bcache/writeback.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/writeback.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-bufio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-bufio.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-crypt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-crypt.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-flakey.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-flakey.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-integrity.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-integrity.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-kcopyd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-kcopyd.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-raid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-raid.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-table.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-table.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-verity-fec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity-fec.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-verity-target.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity-target.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-verity.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-zoned-metadata.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-zoned-metadata.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm-zoned-target.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-zoned-target.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/md-autodetect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md-autodetect.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/md/md-faulty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md-faulty.c</a></td><td class='right'>365</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.4%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/md/md-linear.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md-linear.c</a></td><td class='right'>318</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.8%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/md/md-multipath.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md-multipath.c</a></td><td class='right'>471</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.7%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/md.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md.c</a></td><td class='right'>500</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/md.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid1-10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid1-10.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid1.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid10.c</a></td><td class='right'>271</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid5-cache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5-cache.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid5-ppl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5-ppl.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5.c</a></td><td class='right'>207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/md/raid5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/cec/core/cec-adap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/cec/core/cec-adap.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/cec/platform/cros-ec/cros-ec-cec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/cec/platform/cros-ec/cros-ec-cec.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/common/saa7146/saa7146_fops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/saa7146/saa7146_fops.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/common/videobuf2/videobuf2-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-core.c</a></td><td class='right'>518</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/common/videobuf2/videobuf2-dma-sg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-dma-sg.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/common/videobuf2/videobuf2-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-v4l2.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/dvb-core/dvb_vb2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-core/dvb_vb2.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/dvb-core/dvbdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-core/dvbdev.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/dvb-frontends/m88ds3103.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-frontends/m88ds3103.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/dvb-frontends/rtl2832_sdr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-frontends/rtl2832_sdr.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/Kconfig</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv7180.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7180.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv7183.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7183.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv748x/adv748x-afe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-afe.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv748x/adv748x-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-csi2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv748x/adv748x-hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-hdmi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv7511-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7511-v4l2.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv7604.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7604.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/adv7842.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7842.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ak7375.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ak7375.c</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/alvium-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/alvium-csi2.c</a></td><td class='right'>2558</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 30.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 69.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/alvium-csi2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/alvium-csi2.h</a></td><td class='right'>475</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ar0521.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ar0521.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/ccs-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-core.c</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/ccs-reg-access.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-reg-access.c</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/ccs-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-regs.h</a></td><td class='right'>906</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 5.5%;'/><td class='none' style='width: 89.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/ccs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ccs/smiapp-reg-defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/smiapp-reg-defs.h</a></td><td class='right'>951</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 5.7%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ds90ub913.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub913.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ds90ub953.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub953.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ds90ub960.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub960.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/et8ek8/et8ek8_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/et8ek8/et8ek8_driver.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/gc0308.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/gc0308.c</a></td><td class='right'>1451</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/gc2145.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/gc2145.c</a></td><td class='right'>1450</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 17.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 82.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/hi556.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi556.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/hi846.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi846.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/hi847.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi847.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx208.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx208.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx214.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx214.c</a></td><td class='right'>207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx219.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx219.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx258.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx258.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx274.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx274.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx290.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx290.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx296.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx296.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx319.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx319.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx334.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx334.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx335.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx335.c</a></td><td class='right'>227</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx355.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx355.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx412.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx412.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/imx415.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx415.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/isl7998x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/isl7998x.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/max9286.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/max9286.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9m001.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m001.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9m111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m111.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9m114.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m114.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9p031.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9p031.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9t112.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9t112.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9v011.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v011.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9v032.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v032.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/mt9v111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v111.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/og01a1b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/og01a1b.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov01a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov01a10.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov02a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov02a10.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov08d10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov08d10.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov08x40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov08x40.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov13858.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov13858.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov13b10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov13b10.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov2640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2640.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov2659.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2659.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov2680.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2680.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov2685.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2685.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov2740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2740.c</a></td><td class='right'>396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov4689.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov4689.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5640.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5645.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5645.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5647.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5647.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5648.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5648.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5670.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5670.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5675.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5675.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5693.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5693.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov5695.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5695.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov64a40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov64a40.c</a></td><td class='right'>3690</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 44.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 55.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov6650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov6650.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov7251.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7251.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov7670.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7670.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov772x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov772x.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov7740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7740.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov8856.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8856.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov8858.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8858.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov8865.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8865.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov9282.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9282.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov9640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9640.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov9650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9650.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/ov9734.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9734.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/rj54n1cb0c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/rj54n1cb0c.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/s5c73m3/s5c73m3-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5c73m3/s5c73m3-core.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/s5k5baf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5k5baf.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/s5k6a3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5k6a3.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/saa6752hs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/saa6752hs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/st-mipid02.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/st-mipid02.c</a></td><td class='right'>481</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 3.9%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/st-vgxy61.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/st-vgxy61.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tc358746.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tc358746.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tda1997x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tda1997x.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/thp7312.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/thp7312.c</a></td><td class='right'>2256</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 27.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 72.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tvp514x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp514x.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tvp5150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp5150.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tvp7002.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp7002.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/i2c/tw9900.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tw9900.c</a></td><td class='right'>781</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/tw9910.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tw9910.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/i2c/video-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/video-i2c.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/mc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/mc/Kconfig</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/mc/mc-device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/mc/mc-device.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/bt8xx/bttv-driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/bt8xx/bttv-driver.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/bt8xx/bttv-vbi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/bt8xx/bttv-vbi.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cobalt/cobalt-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cobalt/cobalt-v4l2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx18/cx18-streams.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx18/cx18-streams.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx23885/cx23885-417.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-417.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx23885/cx23885-dvb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-dvb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx23885/cx23885-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-video.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx25821/cx25821-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx25821/cx25821-video.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx88/cx88-blackbird.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-blackbird.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx88/cx88-dvb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-dvb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/cx88/cx88-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-video.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/ddbridge/ddbridge-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ddbridge/ddbridge-main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/dt3155/dt3155.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/dt3155/dt3155.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/intel/ipu-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ipu-bridge.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/intel/ipu3/ipu3-cio2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ipu3/ipu3-cio2.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/intel/ivsc/mei_csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ivsc/mei_csi.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/ivtv/ivtv-driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ivtv/ivtv-driver.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/ivtv/ivtv-streams.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ivtv/ivtv-streams.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/mgb4/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/mgb4/mgb4_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_core.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/mgb4/mgb4_vin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_vin.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/mgb4/mgb4_vout.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_vout.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/netup_unidvb/netup_unidvb_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/netup_unidvb/netup_unidvb_core.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/solo6x10/solo6x10-offsets.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/solo6x10/solo6x10-offsets.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/tw5864/tw5864-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw5864/tw5864-video.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/tw68/tw68-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw68/tw68-video.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/tw686x/tw686x-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw686x/tw686x-video.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/pci/zoran/zoran_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/zoran/zoran_driver.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/amphion/vpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/amphion/vpu_cmds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_cmds.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/amphion/vpu_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/amphion/vpu_dbg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_dbg.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/amphion/vpu_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_v4l2.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/aspeed/aspeed-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/aspeed/aspeed-video.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/atmel/atmel-isi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/atmel/atmel-isi.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/cadence/cdns-csi2rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/cadence/cdns-csi2rx.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/cadence/cdns-csi2tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/cadence/cdns-csi2tx.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/Kconfig</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/Kconfig</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-bit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-bit.c</a> (renamed from drivers/media/platform/chips-media/coda-bit.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-common.c</a> (renamed from drivers/media/platform/chips-media/coda-common.c)</td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-gdi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-gdi.c</a> (renamed from drivers/media/platform/chips-media/coda-gdi.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-h264.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-h264.c</a> (renamed from drivers/media/platform/chips-media/coda-h264.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-jpeg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-jpeg.c</a> (renamed from drivers/media/platform/chips-media/coda-jpeg.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-mpeg2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-mpeg2.c</a> (renamed from drivers/media/platform/chips-media/coda-mpeg2.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda-mpeg4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-mpeg4.c</a> (renamed from drivers/media/platform/chips-media/coda-mpeg4.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda.h</a> (renamed from drivers/media/platform/chips-media/coda.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/coda_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda_regs.h</a> (renamed from drivers/media/platform/chips-media/coda_regs.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/imx-vdoa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/imx-vdoa.c</a> (renamed from drivers/media/platform/chips-media/imx-vdoa.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/imx-vdoa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/imx-vdoa.h</a> (renamed from drivers/media/platform/chips-media/imx-vdoa.h)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/coda/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/trace.h</a> (renamed from drivers/media/platform/chips-media/trace.h)</td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/Kconfig</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/Makefile</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-helper.c</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-helper.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-helper.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-hw.c</a></td><td class='right'>2551</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 30.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 69.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-regdefine.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-regdefine.h</a></td><td class='right'>732</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vdi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vdi.c</a></td><td class='right'>205</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vdi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vdi.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c</a></td><td class='right'>1932</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 23.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 76.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c</a></td><td class='right'>1794</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 78.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu.c</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu.h</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuapi.c</a></td><td class='right'>960</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuapi.h</a></td><td class='right'>870</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h</a></td><td class='right'>77</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuerror.h</a></td><td class='right'>292</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/chips-media/wave5/wave5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5.h</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/microchip/microchip-csi2dc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-csi2dc.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/microchip/microchip-isc-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-isc-base.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/microchip/microchip-isc-scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-isc-scaler.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nuvoton/npcm-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nuvoton/npcm-video.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nvidia/tegra-vde/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nvidia/tegra-vde/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nvidia/tegra-vde/v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nvidia/tegra-vde/v4l2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx-mipi-csis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx-mipi-csis.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx7-media-csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx7-media-csi.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/nxp/imx8mq-mipi-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8mq-mipi-csi2.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-csid-gen2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid-gen2.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-csid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-csid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-csiphy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csiphy.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-ispif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-ispif.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe-170.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-170.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe-4-1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-1.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe-4-7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-7.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe-4-8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-8.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe-480.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-480.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe.c</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss-vfe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe.h</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss.c</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/camss/camss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/venus/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/core.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/venus/vdec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/vdec.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/qcom/venus/venc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/venc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rcar-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-isp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-vin/rcar-csi2.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rcar-vin/rcar-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-vin/rcar-dma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rcar_drif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar_drif.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/renesas-ceu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/renesas-ceu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/sh_vou.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/sh_vou.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_brx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_brx.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_clu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_clu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_entity.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_entity.c</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_entity.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_entity.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_hgo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hgo.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_hgt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hgt.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_histo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_histo.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_hsit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hsit.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_lif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_lif.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_lut.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_lut.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_pipe.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_rpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rpf.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_rwpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_rwpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_sru.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_sru.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_uds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_uds.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_uif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_uif.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_video.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/renesas/vsp1/vsp1_wpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_wpf.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rga/rga-buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga-buf.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rga/rga-hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga-hw.c</a></td><td class='right'>146</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rga/rga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga.c</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rga/rga.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-common.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c</a></td><td class='right'>136</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos-gsc/gsc-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos-gsc/gsc-core.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/fimc-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-capture.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/fimc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/fimc-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-isp.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/fimc-lite.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-lite.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/exynos4-is/mipi-csis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/mipi-csis.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s3c-camif/camif-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s3c-camif/camif-capture.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c</a></td><td class='right'>299</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/st/sti/hva/hva-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/sti/hva/hva-v4l2.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/Kconfig</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmi.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c</a></td><td class='right'>956</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c</a></td><td class='right'>565</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h</a></td><td class='right'>217</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c</a></td><td class='right'>604</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c</a></td><td class='right'>440</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-di/sun8i-di.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/am437x/am437x-vpfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/am437x/am437x-vpfe.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/cal/cal-camerarx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/cal/cal-camerarx.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/cal/cal-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/cal/cal-video.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/davinci/vpif_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/davinci/vpif_capture.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/davinci/vpif_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/davinci/vpif_display.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap/omap_vout.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap/omap_vout.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap3isp/ispccdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispccdc.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap3isp/ispccp2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispccp2.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap3isp/ispcsi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispcsi2.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap3isp/isppreview.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/isppreview.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/ti/omap3isp/ispresizer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispresizer.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_drv.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_g2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_hw.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_postproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_postproc.c</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/verisilicon/hantro_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_v4l2.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/video-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/video-mux.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/xilinx/xilinx-csi2rxss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-csi2rxss.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/xilinx/xilinx-tpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-tpg.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/platform/xilinx/xilinx-vip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-vip.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/rc/ir-hix5hd2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/ir-hix5hd2.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/rc/meson-ir-tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/meson-ir-tx.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/rc/pwm-ir-tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/pwm-ir-tx.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vicodec/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vicodec/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vicodec/vicodec-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vicodec/vicodec-core.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vidtv/vidtv_pes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vidtv/vidtv_pes.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vimc/vimc-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-capture.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vimc/vimc-debayer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-debayer.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vimc/vimc-scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-scaler.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vimc/vimc-sensor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-sensor.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-core.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-dec.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-dec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-dec.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-trace-av1.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-trace-av1.h</a></td><td class='right'>314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-trace-points.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-trace-points.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-video.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl-video.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-video.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/visl/visl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-core.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-meta-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-meta-cap.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-meta-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-meta-out.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-touch-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-touch-cap.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-vbi-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vbi-cap.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-vbi-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vbi-out.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-vid-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vid-cap.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/test-drivers/vivid/vivid-vid-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vid-out.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/airspy/airspy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/airspy/airspy.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/cx231xx/cx231xx-417.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-417.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/cx231xx/cx231xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/cx231xx/cx231xx-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-video.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/dvb-usb/cxusb-analog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/dvb-usb/cxusb-analog.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/em28xx/em28xx-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/em28xx/em28xx-video.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/gspca/gspca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/gspca/gspca.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/hackrf/hackrf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/hackrf/hackrf.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/pvrusb2/pvrusb2-context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/pvrusb2/pvrusb2-context.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/stk1160/stk1160-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/stk1160/stk1160-video.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/usbtv/usbtv-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/usbtv/usbtv-video.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/uvc/uvc_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/uvc/uvc_driver.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/usb/uvc/uvc_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/uvc/uvc_video.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-async.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-async.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-cci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-cci.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-common.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-compat-ioctl32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-compat-ioctl32.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-dev.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-fwnode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-fwnode.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-ioctl.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-mem2mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-mem2mem.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/media/v4l2-core/v4l2-subdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-subdev.c</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/brcmstb_dpfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/brcmstb_dpfe.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/brcmstb_memc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/brcmstb_memc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/emif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/emif.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/fsl-corenet-cf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/fsl-corenet-cf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/fsl_ifc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/fsl_ifc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/jz4780-nemc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/jz4780-nemc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/mtk-smi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/mtk-smi.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/omap-gpmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/omap-gpmc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/renesas-rpc-if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/renesas-rpc-if.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/samsung/exynos5422-dmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/samsung/exynos5422-dmc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/stm32-fmc2-ebi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/stm32-fmc2-ebi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/tegra/tegra186-emc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra186-emc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/tegra/tegra186.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra186.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/tegra/tegra210-emc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra210-emc-core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/ti-aemif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/ti-aemif.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/memory/ti-emif-pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/ti-emif-pm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/ab8500-sysctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/ab8500-sysctrl.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/cros_ec_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/cros_ec_dev.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/cs42l43-sdw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/cs42l43-sdw.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/da9062-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/da9062-core.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/exynos-lpass.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/exynos-lpass.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/fsl-imx25-tsadc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/fsl-imx25-tsadc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/hi655x-pmic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/hi655x-pmic.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/intel-lpss-acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss-acpi.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/intel-lpss-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss-pci.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/intel-lpss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/intel-lpss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/kempld-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/kempld-core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/mcp-sa11x0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/mcp-sa11x0.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/mxs-lradc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/mxs-lradc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/omap-usb-host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/omap-usb-host.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/omap-usb-tll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/omap-usb-tll.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/pcf50633-adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/pcf50633-adc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/qcom-pm8xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/qcom-pm8xxx.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/qcom-spmi-pmic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/qcom-spmi-pmic.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/rave-sp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/rave-sp.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/rk8xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/rk8xx-core.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/sm501.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/sm501.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/stm32-timers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/stm32-timers.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/syscon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/syscon.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/ti_am335x_tscadc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/ti_am335x_tscadc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/tps65086.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps65086.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/tps65911-comparator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps65911-comparator.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/tps6594-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps6594-core.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/tps6594-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps6594-spi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/twl4030-audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/twl4030-audio.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mfd/twl6030-irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/twl6030-irq.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/Kconfig</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/bcm-vk/bcm_vk_tty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/bcm-vk/bcm_vk_tty.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/cardreader/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/cardreader/rts5264.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rts5264.c</a></td><td class='right'>886</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/cardreader/rts5264.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rts5264.h</a></td><td class='right'>278</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/cardreader/rtsx_pcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rtsx_pcr.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/cardreader/rtsx_pcr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rtsx_pcr.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/cxl/cxl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cxl/cxl.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/dw-xdata-pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/dw-xdata-pcie.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/eeprom/at24.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/eeprom/at24.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/eeprom/ee1004.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/eeprom/ee1004.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/genwqe/card_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/genwqe/card_dev.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/genwqe/card_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/genwqe/card_utils.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/lis3lv02d/lis3lv02d_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/lis3lv02d/lis3lv02d_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/lkdtm/heap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/lkdtm/heap.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/Kconfig</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/Makefile</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/client.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/gsc_proxy/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/gsc_proxy/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/hdcp/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/hdcp/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/mei/platform-vsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/platform-vsc.c</a></td><td class='right'>450</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/pxp/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/pxp/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/mei/pxp/mei_pxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/pxp/mei_pxp.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/mei/vsc-fw-loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-fw-loader.c</a></td><td class='right'>770</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/mei/vsc-tp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-tp.c</a></td><td class='right'>555</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/mei/vsc-tp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-tp.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/misc/nsm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/nsm.c</a></td><td class='right'>506</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/ocxl/afu_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/afu_irq.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/ocxl/context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/context.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/ocxl/file.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/file.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/ocxl/link.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/link.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/ocxl/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/pci_endpoint_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pci_endpoint_test.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/pvpanic/pvpanic-mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic-mmio.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/pvpanic/pvpanic-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic-pci.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/pvpanic/pvpanic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/pvpanic/pvpanic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/vmw_vmci/vmci_handle_array.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/vmw_vmci/vmci_handle_array.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/misc/vmw_vmci/vmci_handle_array.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/vmw_vmci/vmci_handle_array.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/block.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/block.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/core.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/host.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/mmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/mmc.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/mmc_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/mmc_test.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/core/sdio_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/sdio_uart.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/cqhci-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/cqhci-core.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/meson-mx-sdhc-mmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/meson-mx-sdhc-mmc.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/mmc_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmc_spi.c</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/mmci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmci.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/mmci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmci.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/mtk-sd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mtk-sd.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/rtsx_pci_sdmmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/rtsx_pci_sdmmc.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-brcmstb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-brcmstb.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-of-dwcmshc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-of-dwcmshc.c</a></td><td class='right'>349</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-omap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-omap.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-pci-gli.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-pci-gli.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-sprd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-sprd.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-xenon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-xenon.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci-xenon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-xenon.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mmc/host/sdhci_am654.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci_am654.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/maps/vmu-flash.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/maps/vmu-flash.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/mtd_blkdevs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/mtd_blkdevs.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/mtdcore.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/mtdcore.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/bcma_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcma_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/brcmnand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmnand.c</a></td><td class='right'>408</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 95.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/brcmnand.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmnand.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/brcmnand/iproc_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/iproc_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/diskonchip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/diskonchip.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/fsl_ifc_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/fsl_ifc_nand.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/meson_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/meson_nand.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/nand_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/nand_base.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/pl35x-nand-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/pl35x-nand-controller.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/rockchip-nand-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/rockchip-nand-controller.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/s3c2410.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/s3c2410.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/raw/txx9ndfmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/txx9ndfmc.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/nand/spi/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/spi/core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/atmel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/atmel.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/core.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/core.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/micron-st.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/micron-st.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/sfdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sfdp.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/sfdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sfdp.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/spansion.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/spansion.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/sst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sst.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/swp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/swp.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/spi-nor/sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sysfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ssfdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ssfdc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/Kconfig</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/block.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/block.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/debug.c</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/debug.h</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/io.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mtd/ubi/ubi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/ubi.h</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/mux/mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mux/mmio.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/amt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/amt.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/arcnet/arcdevice.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/arcnet/arcdevice.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/arcnet/com20020-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/arcnet/com20020-pci.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/bonding/bond_alb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/bonding/bond_alb.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/bonding/bond_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/bonding/bond_main.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/can/c_can/c_can_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/c_can/c_can_platform.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/can/flexcan/flexcan-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/flexcan/flexcan-core.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/can/mscan/mpc5xxx_can.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/mscan/mpc5xxx_can.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/can/usb/peak_usb/pcan_usb_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/usb/peak_usb/pcan_usb_core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/can/xilinx_can.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/xilinx_can.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/bcm_sf2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/bcm_sf2.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/bcm_sf2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/bcm_sf2.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/lantiq_gswip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/lantiq_gswip.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/microchip/ksz8.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/microchip/ksz8795.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8795.c</a></td><td class='right'>152</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/microchip/ksz8795_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8795_reg.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/microchip/ksz_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz_common.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/microchip/ksz_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz_common.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mt7530.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mt7530.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/chip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/chip.c</a></td><td class='right'>418</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/chip.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/chip.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/global1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/global1.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/pcs-639x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/pcs-639x.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/serdes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/serdes.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/mv88e6xxx/serdes.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/serdes.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/qca/qca8k-8xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-8xxx.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/qca/qca8k-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-common.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/qca/qca8k-leds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-leds.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/qca/qca8k.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/realtek/rtl8365mb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8365mb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/realtek/rtl8366-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8366-core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/realtek/rtl8366rb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8366rb.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/sja1105/sja1105_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/sja1105/sja1105_main.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/dsa/vitesse-vsc73xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/vitesse-vsc73xx-core.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_eth_com.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_eth_com.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_ethtool.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_netdev.c</a></td><td class='right'>732</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 7.8%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_netdev.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_netdev.h</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_xdp.c</a></td><td class='right'>468</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amazon/ena/ena_xdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_xdp.h</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/amd/xgbe/xgbe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amd/xgbe/xgbe.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ring.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_ring.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ring.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/aquantia/atlantic/aq_vec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_vec.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/asix/ax88796c_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/asix/ax88796c_main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/asix/ax88796c_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/asix/ax88796c_main.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/atheros/atl1e/atl1e_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/atheros/atl1e/atl1e_main.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt.c</a></td><td class='right'>2685</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.4%;'/><td class='rem' style='width: 10.0%;'/><td class='none' style='width: 67.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt.h</a></td><td class='right'>512</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c</a></td><td class='right'>752</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 90.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h</a></td><td class='right'>521</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.7%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/genet/bcmgenet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/genet/bcmgenet.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/broadcom/tg3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/tg3.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/brocade/bna/bnad_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/brocade/bna/bnad_ethtool.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cadence/macb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cadence/macb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb_main.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cadence/macb_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb_ptp.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/chelsio/cxgb3/adapter.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb3/adapter.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cisco/enic/enic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cisco/enic/enic_ethtool.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/cortina/gemini.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cortina/gemini.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/dlink/dl2k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/dlink/dl2k.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/emulex/benet/be_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/emulex/benet/be_ethtool.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ezchip/nps_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ezchip/nps_enet.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/enetc/enetc_ethtool.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/enetc/enetc_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/enetc/enetc_pf.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/freescale/fec_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/fec_main.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/fungible/funeth/funeth_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/fungible/funeth/funeth_ethtool.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_adminq.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_adminq.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_dqo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_dqo.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_ethtool.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_main.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_register.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_register.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_rx.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_tx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/google/gve/gve_tx_dqo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_tx_dqo.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_enet.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_enet.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_enet.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_ethtool.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3_enet.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/huawei/hinic/hinic_ethtool.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ibm/ibmvnic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ibm/ibmvnic.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000/e1000_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000/e1000_hw.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/80003es2lan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/80003es2lan.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/82571.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/82571.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/defines.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/defines.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/ethtool.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/ich8lan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/ich8lan.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/mac.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/netdev.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/e1000e/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/phy.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/fm10k/fm10k_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_pf.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/fm10k/fm10k_vf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_vf.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e.h</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq.c</a></td><td class='right'>229</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_common.c</a></td><td class='right'>214</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_dcb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_dcb.c</a></td><td class='right'>285</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_ddp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ddp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_debug.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_debugfs.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_diag.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_diag.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ethtool.c</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_main.c</a></td><td class='right'>744</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 4.8%;'/><td class='none' style='width: 91.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_nvm.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_prototype.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_prototype.h</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ptp.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_register.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_register.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_txrx.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_txrx.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_type.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c</a></td><td class='right'>115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/i40e/i40e_xsk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_xsk.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adminq.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adminq.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_adv_rss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_adv_rss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_common.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_ethtool.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_fdir.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_fdir.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_fdir.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_main.c</a></td><td class='right'>206</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_txrx.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_txrx.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_virtchnl.c</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_adminq_cmd.h</a></td><td class='right'>210</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_base.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_base.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_common.c</a></td><td class='right'>334</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 3.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_common.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_dcb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_dcb_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb_lib.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_dcb_nl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb_nl.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_debugfs.c</a></td><td class='right'>667</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_devlink.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_devlink.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_devlink.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_dpll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dpll.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_eswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch.c</a></td><td class='right'>568</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_eswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_eswitch_br.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch_br.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ethtool.c</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fdir.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_flex_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_pipe.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_flex_pipe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_pipe.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_flex_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_type.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_flow.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flow.c</a></td><td class='right'>482</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.4%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_flow.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flow.h</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_fwlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fwlog.c</a></td><td class='right'>470</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_fwlog.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fwlog.h</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_hw_autogen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hw_autogen.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hwmon.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_hwmon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hwmon.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_lag.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lag.c</a></td><td class='right'>131</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_lag.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lag.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h</a></td><td class='right'>412</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lib.c</a></td><td class='right'>327</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lib.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_main.c</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_nvm.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp.c</a></td><td class='right'>319</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ptp_consts.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_consts.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ptp_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_hw.c</a></td><td class='right'>444</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 2.7%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_ptp_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_hw.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_repr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_repr.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_repr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_repr.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_sched.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_sched.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_sriov.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_switch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_switch.c</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_tc_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_tc_lib.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_txrx_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx_lib.c</a></td><td class='right'>207</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_txrx_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx_lib.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_type.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_vf_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_vf_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_vf_lib_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib_private.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl.c</a></td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_virtchnl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ice/ice_xsk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_xsk.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_ethtool.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_lib.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_txrx.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/idpf_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_virtchnl.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/idpf/virtchnl2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/virtchnl2.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/e1000_82575.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_82575.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/e1000_i210.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_i210.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/e1000_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_mac.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/e1000_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_nvm.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/e1000_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_phy.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/igb_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/igb_ethtool.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igb/igb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/igb_main.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igbvf/mbx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igbvf/mbx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igbvf/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igbvf/netdev.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_base.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_base.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_defines.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_defines.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_ethtool.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_i225.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_i225.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_main.c</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_phy.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_ptp.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_regs.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/igc/igc_tsn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_tsn.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_common.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_main.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_type.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c</a></td><td class='right'>167</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/intel/ixgbevf/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbevf/ethtool.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/mvmdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvmdio.c</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/mvneta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvneta.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c</a></td><td class='right'>102</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c</a></td><td class='right'>925</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 11.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 88.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_config.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_main.c</a></td><td class='right'>266</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_main.h</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c</a></td><td class='right'>449</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h</a></td><td class='right'>167</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h</a></td><td class='right'>416</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.h</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeon_ep/octep_tx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.h</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mbox.h</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/mcs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/mcs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/npc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/npc.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rpm.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c</a></td><td class='right'>856</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.8%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c</a></td><td class='right'>243</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mediatek/mtk_eth_soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_eth_soc.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mediatek/mtk_wed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_wed.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mediatek/mtk_wed_wo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_wed_wo.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx4/en_ethtool.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/cmd.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/dpll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/dpll.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/params.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/params.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/qos.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/trap.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c</a></td><td class='right'>443</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_common.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_main.c</a></td><td class='right'>189</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_rep.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_rx.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_stats.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_core.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/main.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/port.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlx5/core/vport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/vport.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/cmd.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/core.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/core.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/pci.c</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/reg.h</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/resources.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/resources.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c</a></td><td class='right'>853</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.0%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/micrel/ks8851.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/micrel/ks8851_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851_common.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/micrel/ks8851_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851_spi.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microchip/lan743x_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/lan743x_ethtool.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microchip/lan743x_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/lan743x_main.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microsoft/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microsoft/mana/gdma_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/gdma_main.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microsoft/mana/hw_channel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/hw_channel.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microsoft/mana/mana_en.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/mana_en.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/microsoft/mana/mana_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/mana_ethtool.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/mscc/ocelot_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mscc/ocelot_stats.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/neterion/s2io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/neterion/s2io.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/flower/lag_conf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/flower/lag_conf.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c</a></td><td class='right'>127</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfd3/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfd3/dp.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfdk/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfdk/dp.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfp_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_devlink.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfp_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfp_net_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_common.c</a></td><td class='right'>199</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c</a></td><td class='right'>537</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_debugfs.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_dev.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_dev.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_dev.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_ethtool.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_lif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_lif.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_lif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_lif.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_main.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_stats.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/pensando/ionic/ionic_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_txrx.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qlogic/qed/qed_cxt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qed/qed_cxt.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qlogic/qede/qede_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qede/qede_ethtool.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qlogic/qla3xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qla3xxx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qualcomm/qca_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_debug.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qualcomm/qca_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_spi.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qualcomm/qca_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_uart.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/Kconfig</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/r8169.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/r8169_firmware.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_firmware.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/r8169_leds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_leds.c</a></td><td class='right'>157</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/realtek/r8169_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_main.c</a></td><td class='right'>234</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/Kconfig</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/Makefile</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/ravb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/ravb_main.c</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/rcar_gen4_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rcar_gen4_ptp.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/rcar_gen4_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rcar_gen4_ptp.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/rswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rswitch.c</a></td><td class='right'>393</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/renesas/rswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rswitch.h</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ef10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ef10.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ef100_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ef100_ethtool.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/efx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/efx.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ethtool_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool_common.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ethtool_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool_common.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/falcon/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/falcon/ethtool.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/net_driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/net_driver.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ptp.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ptp.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/rx_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/rx_common.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/efx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/efx.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/ethtool_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool_common.c</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/ethtool_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool_common.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/net_driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/net_driver.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ptp.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ptp.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/sfc/siena/siena.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/siena.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/socionext/netsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/socionext/netsec.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/common.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac5.c</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwmac5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac5.h</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/hwif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/hwif.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/hwif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/hwif.h</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/mmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/mmc.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/mmc_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/mmc_core.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_est.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_est.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_est.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_est.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_main.c</a></td><td class='right'>164</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/Kconfig</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/am65-cpsw-ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-ethtool.c</a></td><td class='right'>272</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/am65-cpsw-nuss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-nuss.c</a></td><td class='right'>281</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/am65-cpsw-nuss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-nuss.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/am65-cpsw-qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-qos.c</a></td><td class='right'>708</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.5%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 91.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/am65-cpsw-qos.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-qos.h</a></td><td class='right'>186</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/cpsw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/cpsw.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/cpsw_new.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/cpsw_new.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/ti/davinci_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/davinci_mdio.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/toshiba/ps3_gelic_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/toshiba/ps3_gelic_net.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/toshiba/ps3_gelic_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/toshiba/ps3_gelic_net.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.c</a></td><td class='right'>238</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_ethtool.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_hw.c</a></td><td class='right'>275</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_hw.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_lib.c</a></td><td class='right'>239</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_lib.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/libwx/wx_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_type.h</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/ngbe/ngbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_main.c</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/ngbe/ngbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_type.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/txgbe/txgbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_main.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_type.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/xilinx/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/xilinx/xilinx_axienet.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/xilinx_axienet.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ethernet/xilinx/xilinx_axienet_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/xilinx_axienet_main.c</a></td><td class='right'>667</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 92.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/fjes/fjes_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/fjes/fjes_main.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/geneve.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/geneve.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/hyperv/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/hyperv/netvsc_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/netvsc_drv.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/hyperv/rndis_filter.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/rndis_filter.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ieee802154/fakelb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ieee802154/fakelb.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ieee802154/mac802154_hwsim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ieee802154/mac802154_hwsim.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ipa/data/ipa_data-v5.5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/data/ipa_data-v5.5.c</a></td><td class='right'>487</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/gsi_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/gsi_reg.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_data.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_main.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_mem.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_reg.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_reg.h</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipa/ipa_version.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_version.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/ipa/reg/ipa_reg-v5.5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/reg/ipa_reg-v5.5.c</a></td><td class='right'>565</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ipvlan/ipvlan_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipvlan/ipvlan_main.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/macsec.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/macvlan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/macvlan.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/mdio/mdio-bcm-unimac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-bcm-unimac.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/mdio/mdio-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-gpio.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/mdio/mdio-mux-bcm-iproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-mux-bcm-iproc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/mdio/mdio-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-mux.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/netdevsim/bpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/bpf.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/netdevsim/macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/macsec.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/netdevsim/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/netdev.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/netkit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netkit.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/pcs/pcs-rzn1-miic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/pcs/pcs-rzn1-miic.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/Kconfig</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/Makefile</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/adin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/adin.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia.h</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/Kconfig</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/aquantia.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia.h</a></td><td class='right'>122</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/aquantia_firmware.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_firmware.c</a></td><td class='right'>374</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/aquantia_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_hwmon.c</a> (renamed from drivers/net/phy/aquantia_hwmon.c)</td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/net/phy/aquantia/aquantia_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_main.c</a> (renamed from drivers/net/phy/aquantia_main.c)</td><td class='right'>137</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/at803x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/at803x.c</a></td><td class='right'>1092</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.7%;'/><td class='rem' style='width: 5.5%;'/><td class='none' style='width: 86.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/ax88796b_rust.rs?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/ax88796b_rust.rs</a></td><td class='right'>135</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/bcm-phy-ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm-phy-ptp.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/bcm54140.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm54140.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/bcm84881.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm84881.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/broadcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/broadcom.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/dp83640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/dp83640.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/dp83tg720.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/dp83tg720.c</a></td><td class='right'>188</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/marvell10g.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/marvell10g.c</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/mdio_bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mdio_bus.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/mdio_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mdio_device.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/micrel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/micrel.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/mscc/mscc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/mscc/mscc_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc_main.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/mscc/mscc_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc_ptp.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/nxp-c45-tja11xx-macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx-macsec.c</a></td><td class='right'>1729</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 20.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 79.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/nxp-c45-tja11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx.c</a></td><td class='right'>94</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/phy/nxp-c45-tja11xx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx.h</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/nxp-tja11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-tja11xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/phy-c45.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy-c45.c</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/phy-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy-core.c</a></td><td class='right'>204</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/phy_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy_device.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/phylink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phylink.c</a></td><td class='right'>324</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/sfp-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/sfp-bus.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/sfp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/sfp.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/phy/smsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/smsc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/ppp/ppp_async.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ppp/ppp_async.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/slip/slhc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/slip/slhc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/slip/slip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/slip/slip.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/team/team.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/team/team.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/usb/ax88172a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/ax88172a.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/usb/ax88179_178a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/ax88179_178a.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/usb/hso.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/hso.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/usb/lan78xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/lan78xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/usb/r8152.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/r8152.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/veth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/veth.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/virtio_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/virtio_net.c</a></td><td class='right'>395</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.6%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/vmxnet3/vmxnet3_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vmxnet3/vmxnet3_ethtool.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/vxlan/vxlan_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_core.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/vxlan/vxlan_mdb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_mdb.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/vxlan/vxlan_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_private.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wan/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wan/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/Kconfig</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/Makefile</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/framer-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/framer-core.c</a></td><td class='right'>882</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/pef2256/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/Makefile</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/pef2256/pef2256-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/pef2256-regs.h</a></td><td class='right'>250</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wan/framer/pef2256/pef2256.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/pef2256.c</a></td><td class='right'>880</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wan/fsl_ucc_hdlc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/fsl_ucc_hdlc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wan/ixp4xx_hss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/ixp4xx_hss.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wan/slic_ds26522.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/slic_ds26522.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/bmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/bmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/ce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/ce.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/core.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/core.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/coredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/coredump.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/coredump.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/coredump.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/debug.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/debugfs_sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/debugfs_sta.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/htc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/htc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htc.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/htt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/htt_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt_rx.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/htt_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt_tx.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/hw.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/hw.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/mac.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/pci.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/pci.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/rx_desc.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/sdio.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/thermal.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/usb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/usb.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/wmi-tlv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi-tlv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath10k/wow.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wow.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/ahb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ahb.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/ce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ce.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/ce.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ce.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/core.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dbring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dbring.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dbring.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dbring.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debug.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debug.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs_sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_sta.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/debugfs_sta.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_sta.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_rx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_tx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/dp_tx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_tx.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/fw.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hal_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_desc.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hal_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_rx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hal_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_rx.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hif.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/htc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/htc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/htc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/htc.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hw.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hw.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mac.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mac.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/mhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mhi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/mhi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mhi.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/pcic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/pcic.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/peer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/peer.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/peer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/peer.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/qmi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/qmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/qmi.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/reg.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/reg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/rx_desc.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/spectral.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/spectral.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/spectral.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/spectral.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/thermal.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/thermal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/thermal.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/trace.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wmi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wmi.h</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath11k/wow.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wow.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/core.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dbring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dbring.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/debug.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp_mon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_mon.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp_mon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_mon.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_rx.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_rx.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/dp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_tx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hal_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal_rx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hal_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal_rx.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hif.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hw.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hw.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mac.c</a></td><td class='right'>190</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mac.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/mhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mhi.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/pci.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/pci.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/peer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/peer.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/qmi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/qmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/qmi.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/reg.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/reg.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/rx_desc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/wmi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath12k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/wmi.h</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath5k/ahb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath5k/ahb.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath5k/eeprom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath5k/eeprom.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/Kconfig</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/common-init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/common-init.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/common-spectral.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/common-spectral.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/debug.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/hif_usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/hif_usb.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/htc_drv_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_debug.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/htc_drv_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_init.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_txrx.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/htc_hst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_hst.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/init.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/link.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/link.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/main.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/ath9k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/pci.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ath/wcn36xx/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/wcn36xx/main.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/Kconfig</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/atmel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/atmel.c</a></td><td class='right'>4452</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 53.7%;'/><td class='none' style='width: 46.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/atmel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/atmel.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/atmel_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/atmel_cs.c</a></td><td class='right'>292</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.5%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/atmel/atmel_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/atmel_pci.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/cisco/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/cisco/Kconfig</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/cisco/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/cisco/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/cisco/airo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/cisco/airo.c</a></td><td class='right'>8288</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 100.0%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/cisco/airo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/cisco/airo.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/cisco/airo_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/cisco/airo_cs.c</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.6%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlegacy/4965-mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlegacy/4965-mac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlegacy/common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlegacy/common.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/fw/api/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/fw/api/debug.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/fw/dbg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/fw/dbg.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/fw/dbg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/fw/dbg.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/fw/file.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/fw/file.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-config.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-csr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-csr.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-dbg-tlv.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-devtrace-data.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-devtrace-iwlwifi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-devtrace-iwlwifi.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-devtrace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-devtrace.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-devtrace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-devtrace.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-op-mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-op-mode.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-trans.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-trans.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/iwl-trans.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/iwl-trans.h</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/coex.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/coex.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/d3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/d3.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/ftm-responder.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/fw.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/mld-mac80211.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/mld-sta.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/mvm.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/ops.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/phy-ctxt.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/scan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/scan.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/sta.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/mvm/tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/mvm/tx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/drv.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/internal.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/rx.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/trans-gen2.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/trans.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/trans.c</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/tx-gen2.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intel/iwlwifi/pcie/tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intel/iwlwifi/pcie/tx.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/Kconfig</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/Makefile</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap.h</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_80211.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_80211.h</a></td><td class='right'>97</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_80211_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_80211_rx.c</a></td><td class='right'>1116</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 13.5%;'/><td class='none' style='width: 86.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_80211_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_80211_tx.c</a></td><td class='right'>554</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.7%;'/><td class='none' style='width: 93.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_ap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_ap.c</a></td><td class='right'>3277</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 39.5%;'/><td class='none' style='width: 60.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_ap.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_ap.h</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.2%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_common.h</a></td><td class='right'>420</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.1%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_config.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_cs.c</a></td><td class='right'>710</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 8.6%;'/><td class='none' style='width: 91.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_download.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_download.c</a></td><td class='right'>810</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 9.8%;'/><td class='none' style='width: 90.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_hw.c</a></td><td class='right'>3387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 40.9%;'/><td class='none' style='width: 59.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_info.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_info.c</a></td><td class='right'>509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.1%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_ioctl.c</a></td><td class='right'>3847</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 46.4%;'/><td class='none' style='width: 53.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_main.c</a></td><td class='right'>1123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 13.5%;'/><td class='none' style='width: 86.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_pci.c</a></td><td class='right'>445</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.4%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_plx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_plx.c</a></td><td class='right'>617</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.4%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_proc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_proc.c</a></td><td class='right'>411</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.0%;'/><td class='none' style='width: 95.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/hostap/hostap_wlan.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/hostap/hostap_wlan.h</a></td><td class='right'>1051</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 12.7%;'/><td class='none' style='width: 87.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/Kconfig</a></td><td class='right'>143</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/Makefile</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/airport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/airport.c</a></td><td class='right'>268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.2%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/cfg.c</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.5%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/cfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/cfg.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/fw.c</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.7%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/fw.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hermes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hermes.c</a></td><td class='right'>778</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 9.4%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hermes.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hermes.h</a></td><td class='right'>534</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 6.4%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hermes_dld.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hermes_dld.c</a></td><td class='right'>477</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 5.8%;'/><td class='none' style='width: 94.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hermes_dld.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hermes_dld.h</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hermes_rid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hermes_rid.h</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hw.c</a></td><td class='right'>1362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 16.4%;'/><td class='none' style='width: 83.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/hw.h</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/main.c</a></td><td class='right'>2414</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 29.1%;'/><td class='none' style='width: 70.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/main.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/mic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/mic.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/mic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/mic.h</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco.h</a></td><td class='right'>251</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_cs.c</a></td><td class='right'>350</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.2%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_nortel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_nortel.c</a></td><td class='right'>314</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.8%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_pci.c</a></td><td class='right'>257</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_pci.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_plx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_plx.c</a></td><td class='right'>362</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.4%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_tmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_tmd.c</a></td><td class='right'>237</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/orinoco_usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/orinoco_usb.c</a></td><td class='right'>1787</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 21.6%;'/><td class='none' style='width: 78.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/scan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/scan.c</a></td><td class='right'>259</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.1%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/scan.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/scan.h</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/spectrum_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/spectrum_cs.c</a></td><td class='right'>328</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/wext.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/wext.c</a></td><td class='right'>1428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 17.2%;'/><td class='none' style='width: 82.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/intersil/orinoco/wext.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/intersil/orinoco/wext.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/Kconfig</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/ray_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/ray_cs.c</a></td><td class='right'>2824</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 34.1%;'/><td class='none' style='width: 65.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/ray_cs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/ray_cs.h</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/rayctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/rayctl.h</a></td><td class='right'>734</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 8.9%;'/><td class='none' style='width: 91.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/rndis_wlan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/rndis_wlan.c</a></td><td class='right'>3760</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 45.4%;'/><td class='none' style='width: 54.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/wl3501.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/wl3501.h</a></td><td class='right'>615</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.4%;'/><td class='none' style='width: 92.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/legacy/wl3501_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/legacy/wl3501_cs.c</a></td><td class='right'>2036</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 24.6%;'/><td class='none' style='width: 75.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/libertas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/libertas/Kconfig</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/libertas/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/libertas/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/libertas/if_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/libertas/if_cs.c</a></td><td class='right'>957</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 11.5%;'/><td class='none' style='width: 88.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/cfg80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/cfg80211.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/cmdevt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/cmdevt.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/fw.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/ioctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/ioctl.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/join.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/join.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/main.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/scan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/scan.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/sdio.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/sdio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/sdio.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/sta_ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/sta_ioctl.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/uap_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/uap_cmd.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/marvell/mwifiex/usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/marvell/mwifiex/usb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/dma.c</a></td><td class='right'>268</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/dma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/dma.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/eeprom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/eeprom.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mac80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mac80211.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mmio.c</a></td><td class='right'>108</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76.h</a></td><td class='right'>105</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7603/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7603/dma.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7603/soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7603/soc.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7615/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7615/dma.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7615/mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7615/mcu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7615/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7615/sdio.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7615/soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7615/soc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76_connac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76_connac.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/dma.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/init.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/mac.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/main.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/mcu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/mcu.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/mmio.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7915/soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7915/soc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/init.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/main.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/mcu.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/mt7921.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/pci.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/sdio.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7921/sdio_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7921/sdio_mac.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7925/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7925/main.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7925/mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7925/mcu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7925/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7925/pci.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt792x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt792x.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt792x_acpi_sar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt792x_acpi_sar.c</a></td><td class='right'>53</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt792x_acpi_sar.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt792x_acpi_sar.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt792x_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt792x_mac.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/debugfs.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/dma.c</a></td><td class='right'>398</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/eeprom.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/init.c</a></td><td class='right'>520</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.9%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/mac.c</a></td><td class='right'>219</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/main.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/mcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/mcu.c</a></td><td class='right'>642</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.4%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/mcu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/mcu.h</a></td><td class='right'>253</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/mmio.c</a></td><td class='right'>295</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h</a></td><td class='right'>160</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/pci.c</a></td><td class='right'>79</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/mt7996/regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/mt7996/regs.h</a></td><td class='right'>182</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/mediatek/mt76/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/mediatek/mt76/sdio.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/microchip/wilc1000/cfg80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/microchip/wilc1000/cfg80211.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/microchip/wilc1000/hif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/microchip/wilc1000/hif.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/microchip/wilc1000/hif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/microchip/wilc1000/hif.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/microchip/wilc1000/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/microchip/wilc1000/sdio.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/purelifi/plfxlc/usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/purelifi/plfxlc/usb.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2800.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2800.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2800lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2800lib.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2x00.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2x00.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2x00dev.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2x00link.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2x00link.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2x00mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2x00mac.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/ralink/rt2x00/rt2x00queue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ralink/rt2x00/rt2x00queue.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/base.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/pci.c</a></td><td class='right'>99</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/pci.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtlwifi/wifi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtlwifi/wifi.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/debug.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/debug.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/fw.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/mac80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/mac80211.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/main.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/main.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/sdio.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw88/tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw88/tx.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/acpi.c</a></td><td class='right'>81</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/acpi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/acpi.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/cam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/cam.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/coex.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/coex.c</a></td><td class='right'>652</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/coex.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/coex.h</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/core.c</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/core.h</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/debug.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/debug.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/efuse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/efuse.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/efuse.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/efuse.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/efuse_be.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/efuse_be.c</a></td><td class='right'>420</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/fw.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/fw.h</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/mac.c</a></td><td class='right'>853</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.4%;'/><td class='rem' style='width: 2.9%;'/><td class='none' style='width: 89.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/mac.h</a></td><td class='right'>150</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/mac80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/mac80211.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/mac_be.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/mac_be.c</a></td><td class='right'>1841</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/pci.c</a></td><td class='right'>345</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/pci.h</a></td><td class='right'>519</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/pci_be.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/pci_be.c</a></td><td class='right'>509</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/phy.c</a></td><td class='right'>511</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 93.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/phy.h</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/ps.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/ps.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/reg.h</a></td><td class='right'>3212</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 38.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 61.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/regd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/regd.c</a></td><td class='right'>175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8851b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8851b.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8851be.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8851be.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852a.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852ae.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852ae.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852b.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852be.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852be.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852c.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852c.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852c.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8852ce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8852ce.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8922a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8922a.c</a></td><td class='right'>710</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8922a.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8922a.h</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/rtw8922ae.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/rtw8922ae.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/sar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/sar.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/ser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/ser.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/txrx.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/realtek/rtw89/wow.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/realtek/rtw89/wow.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/silabs/wfx/sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/silabs/wfx/sta.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/virtual/mac80211_hwsim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/virtual/mac80211_hwsim.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/zydas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/zydas/Kconfig</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wireless/zydas/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/zydas/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/zydas/zd1201.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/zydas/zd1201.c</a></td><td class='right'>1909</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 23.0%;'/><td class='none' style='width: 77.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/net/wireless/zydas/zd1201.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/zydas/zd1201.h</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/net/wwan/qcom_bam_dmux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wwan/qcom_bam_dmux.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nfc/pn533/uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nfc/pn533/uart.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nfc/s3fwrn5/uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nfc/s3fwrn5/uart.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nubus/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nubus/bus.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/btt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/btt.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/btt_devs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/btt_devs.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/bus.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/dax_devs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/dax_devs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/dimm_devs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/dimm_devs.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/namespace_devs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/namespace_devs.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/pfn_devs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/pfn_devs.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvdimm/virtio_pmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvdimm/virtio_pmem.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/common/keyring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/common/keyring.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/Kconfig</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/core.c</a></td><td class='right'>346</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/fabrics.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/fabrics.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/fc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/fc.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/ioctl.c</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/multipath.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/multipath.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/nvme.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/nvme.h</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/pci.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/pr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/pr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/rdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/rdma.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/sysfs.c</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/tcp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/tcp.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/host/zns.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/host/zns.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/Kconfig</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/configfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/configfs.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/core.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/fc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/fc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/fcloop.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/fcloop.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/passthru.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/passthru.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/rdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/rdma.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/tcp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/tcp.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/trace.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvme/target/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvme/target/trace.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/brcm_nvram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/brcm_nvram.c</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/core.c</a></td><td class='right'>353</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/imx-ocotp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/imx-ocotp.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/nvmem/internals.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/internals.h</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/nvmem/layouts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/layouts.c</a></td><td class='right'>201</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/layouts/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/layouts/Kconfig</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/layouts/onie-tlv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/layouts/onie-tlv.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/layouts/sl28vpd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/layouts/sl28vpd.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/mtk-efuse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/mtk-efuse.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/stm32-romem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/stm32-romem.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/nvmem/u-boot-env.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/nvmem/u-boot-env.c</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/address.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/address.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/base.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/device.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/dynamic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/dynamic.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/overlay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/overlay.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/platform.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/property.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/unittest-data/tests-phandle.dtsi?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/unittest-data/tests-phandle.dtsi</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/of/unittest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/of/unittest.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/opp/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/opp/core.c</a></td><td class='right'>294</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 1.5%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/opp/of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/opp/of.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/opp/opp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/opp/opp.h</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/opp/ti-opp-supply.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/opp/ti-opp-supply.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/parisc/power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/parisc/power.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/parport/parport_pc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/parport/parport_pc.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/parport/parport_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/parport/parport_serial.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/parport/share.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/parport/share.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/access.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/access.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/cadence/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/cadence/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/cadence/pci-j721e.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/cadence/pci-j721e.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/cadence/pcie-cadence-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/cadence/pcie-cadence-ep.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/cadence/pcie-cadence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/cadence/pcie-cadence.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-dra7xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-dra7xx.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-exynos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-exynos.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-imx6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-imx6.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-keystone.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-keystone.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-layerscape-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-layerscape-ep.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-layerscape.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-layerscape.c</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pci-meson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pci-meson.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-al.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-al.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-armada8k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-armada8k.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-artpec6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-artpec6.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-bt1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-bt1.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-designware-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-designware-ep.c</a></td><td class='right'>197</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-designware-host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-designware-host.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-designware-plat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-designware-plat.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-designware.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-designware.h</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-dw-rockchip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-dw-rockchip.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-fu740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-fu740.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-histb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-histb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-intel-gw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-intel-gw.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-keembay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-keembay.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-kirin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-kirin.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-qcom-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-qcom-ep.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-qcom.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-rcar-gen4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-rcar-gen4.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-spear13xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-spear13xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-tegra194.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-tegra194.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-uniphier-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-uniphier-ep.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-uniphier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-uniphier.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/dwc/pcie-visconti.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/dwc/pcie-visconti.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pci-host-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pci-host-common.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pci-host-generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pci-host-generic.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pci-hyperv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pci-hyperv.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pci-loongson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pci-loongson.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-brcmstb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-brcmstb.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-iproc-platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-iproc-platform.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-mediatek-gen3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-mediatek-gen3.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-mediatek.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-mediatek.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-rcar-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-rcar-ep.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-rcar-host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-rcar-host.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-rockchip-ep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-rockchip-ep.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-rockchip-host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-rockchip-host.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-xilinx-dma-pl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-xilinx-dma-pl.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/pcie-xilinx-nwl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/pcie-xilinx-nwl.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/controller/vmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/controller/vmd.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/endpoint/functions/pci-epf-mhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/endpoint/functions/pci-epf-mhi.c</a></td><td class='right'>320</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/endpoint/functions/pci-epf-ntb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/endpoint/functions/pci-epf-ntb.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/endpoint/functions/pci-epf-test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/endpoint/functions/pci-epf-test.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/endpoint/functions/pci-epf-vntb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/endpoint/functions/pci-epf-vntb.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/endpoint/pci-epc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/endpoint/pci-epc-core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/hotplug/acpiphp_glue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/hotplug/acpiphp_glue.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/iov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/iov.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/pci.c</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/pci.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/pcie/aer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/pcie/aer.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/pcie/aspm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/pcie/aspm.c</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/probe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/probe.c</a></td><td class='right'>218</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/quirks.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/quirks.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/setup-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/setup-bus.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/setup-res.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/setup-res.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pci/switch/switchtec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pci/switch/switchtec.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/bcm63xx_pcmcia.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/bcm63xx_pcmcia.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/db1xxx_ss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/db1xxx_ss.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/electra_cf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/electra_cf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/omap_cf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/omap_cf.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/pxa2xx_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/pxa2xx_base.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/sa1100_generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/sa1100_generic.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pcmcia/xxs1500_ss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pcmcia/xxs1500_ss.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/Kconfig</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/apple_m1_cpu_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/apple_m1_cpu_pmu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm-cmn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm-cmn.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm_cspmu/arm_cspmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm_cspmu/arm_cspmu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm_dsu_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm_dsu_pmu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm_pmu.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm_pmuv3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm_pmuv3.c</a></td><td class='right'>242</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/arm_spe_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/arm_spe_pmu.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/perf/dwc_pcie_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/dwc_pcie_pmu.c</a></td><td class='right'>792</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/fsl_imx8_ddr_perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/fsl_imx8_ddr_perf.c</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/fsl_imx9_ddr_perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/fsl_imx9_ddr_perf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/perf/hisilicon/hisi_uncore_uc_pmu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/mediatek/phy-mtk-tphy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/mediatek/phy-mtk-tphy.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/phy-can-transceiver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/phy-can-transceiver.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/phy-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/phy-core.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-combo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-combo.c</a></td><td class='right'>174</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-pcie.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-ufs.c</a></td><td class='right'>114</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp-usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp-usb.c</a></td><td class='right'>344</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/qualcomm/phy-qcom-qmp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/qualcomm/phy-qcom-qmp.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/renesas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/renesas/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/rockchip/phy-rockchip-inno-usb2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/rockchip/phy-rockchip-inno-usb2.c</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/sunplus/phy-sunplus-usb2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/sunplus/phy-sunplus-usb2.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/ti/phy-gmii-sel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/ti/phy-gmii-sel.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/phy/ti/phy-j721e-wiz.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/phy/ti/phy-j721e-wiz.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/Kconfig</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/bcm/pinctrl-ns.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/bcm/pinctrl-ns.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/cirrus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/cirrus/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/core.c</a></td><td class='right'>65</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/core.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/devicetree.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/devicetree.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/freescale/pinctrl-imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/freescale/pinctrl-imx.c</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/Kconfig</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-alderlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-alderlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-baytrail.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-baytrail.c</a></td><td class='right'>240</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-broxton.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-broxton.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-cannonlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-cannonlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-cedarfork.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-cedarfork.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-denverton.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-denverton.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-elkhartlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-elkhartlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-emmitsburg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-emmitsburg.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-geminilake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-geminilake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-icelake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-icelake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-intel-platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-intel-platform.c</a></td><td class='right'>225</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-intel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-intel.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-intel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-intel.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-jasperlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-jasperlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-lakefield.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-lakefield.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-lewisburg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-lewisburg.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-lynxpoint.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-lynxpoint.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-meteorlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-meteorlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-meteorpoint.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-meteorpoint.c</a></td><td class='right'>465</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-sunrisepoint.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-sunrisepoint.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-tangier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-tangier.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/intel/pinctrl-tigerlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/intel/pinctrl-tigerlake.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-moore.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-moore.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-moore.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-moore.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt2701.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt2701.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt2712.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt2712.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt6795.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt6795.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8167.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8167.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8173.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8173.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8183.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8183.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8186.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8186.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8188.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8188.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8192.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8192.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8195.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8195.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8365.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8365.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mt8516.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mt8516.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-mtk-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-mtk-common.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-paris.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-paris.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/mediatek/pinctrl-paris.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/mediatek/pinctrl-paris.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/nomadik/pinctrl-abx500.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/nomadik/pinctrl-abx500.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/nomadik/pinctrl-nomadik.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/nomadik/pinctrl-nomadik.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/nuvoton/pinctrl-wpcm450.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/nxp/pinctrl-s32cc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/nxp/pinctrl-s32cc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinconf-generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinconf-generic.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinconf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinconf.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinconf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinconf.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-amd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-amd.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-amd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-amd.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-as3722.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-as3722.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-at91-pio4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-at91-pio4.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-cy8c95x0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-cy8c95x0.c</a></td><td class='right'>473</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 1.7%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-equilibrium.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-equilibrium.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-ingenic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-ingenic.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-keembay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-keembay.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-pef2256.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-pef2256.c</a></td><td class='right'>358</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-single.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-single.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-tps6594.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-tps6594.c</a></td><td class='right'>373</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-utils.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinctrl-utils.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinctrl-utils.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinmux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinmux.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/pinmux.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/pinmux.h</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/Kconfig.msm?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/Kconfig.msm</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-lpass-lpi.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-lpass-lpi.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-msm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-msm.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-msm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-msm.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm4450.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm4450.c</a></td><td class='right'>1014</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-sm8650.c</a></td><td class='right'>1762</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 21.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 78.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pinctrl/qcom/pinctrl-x1e80100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/qcom/pinctrl-x1e80100.c</a></td><td class='right'>1876</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 22.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 77.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/realtek/pinctrl-rtd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/realtek/pinctrl-rtd.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/renesas/pinctrl-rza1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/renesas/pinctrl-rza1.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/renesas/pinctrl-rza2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/renesas/pinctrl-rza2.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/renesas/pinctrl-rzg2l.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/renesas/pinctrl-rzg2l.c</a></td><td class='right'>171</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/renesas/pinctrl-rzv2m.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/renesas/pinctrl-rzv2m.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/samsung/pinctrl-exynos-arm64.c</a></td><td class='right'>280</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/samsung/pinctrl-exynos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/samsung/pinctrl-exynos.c</a></td><td class='right'>111</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/samsung/pinctrl-exynos.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/samsung/pinctrl-exynos.h</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/samsung/pinctrl-samsung.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/samsung/pinctrl-samsung.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/samsung/pinctrl-samsung.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/samsung/pinctrl-samsung.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/stm32/pinctrl-stm32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/stm32/pinctrl-stm32.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/sunplus/sppctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/sunplus/sppctl.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pinctrl/tegra/pinctrl-tegra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pinctrl/tegra/pinctrl-tegra.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/cros_ec_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/cros_ec_debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/cros_ec_ishtp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/cros_ec_ishtp.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/cros_ec_sensorhub_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/cros_ec_sensorhub_ring.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/cros_ec_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/cros_ec_uart.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/cros_ec_vbc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/cros_ec_vbc.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/wilco_ec/event.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/wilco_ec/event.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/chrome/wilco_ec/telemetry.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/chrome/wilco_ec/telemetry.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/goldfish/goldfish_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/goldfish/goldfish_pipe.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/mellanox/mlxbf-bootctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/mellanox/mlxbf-bootctl.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/mellanox/mlxbf-pmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/mellanox/mlxbf-pmc.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/mellanox/mlxbf-tmfifo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/mellanox/mlxbf-tmfifo.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/mips/rs780e-acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/mips/rs780e-acpi.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/bus.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/controller.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/controller.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/core.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/ssh_packet_layer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/ssh_packet_layer.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/aggregator/ssh_packet_layer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/aggregator/ssh_packet_layer.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/surface/surface_acpi_notify.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/surface/surface_acpi_notify.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/Kconfig</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/acer-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/acer-wmi.c</a></td><td class='right'>377</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/Kconfig</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmc/pmc-quirks.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmc/pmc-quirks.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmc/pmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmc/pmc.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmc/pmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmc/pmc.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/acpi.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/core.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/pmf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/pmf.h</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/spc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/spc.c</a></td><td class='right'>158</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/sps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/sps.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/pmf/tee-if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/pmf/tee-if.c</a></td><td class='right'>472</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/amd/wbrf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/amd/wbrf.c</a></td><td class='right'>317</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/asus-laptop.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/asus-laptop.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/asus-nb-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/asus-nb-wmi.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/asus-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/asus-wmi.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/asus-wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/asus-wmi.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/dell/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/dell/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/dell/alienware-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/dell/alienware-wmi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/dell/dcdbas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/dell/dcdbas.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/dell/dell-smbios-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/dell/dell-smbios-wmi.c</a></td><td class='right'>173</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/hp/hp-bioscfg/passwdobj-attributes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/hp/hp-bioscfg/passwdobj-attributes.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/hp/hp-wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/hp/hp-wmi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/chtwc_int33fe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/chtwc_int33fe.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/adl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/adl.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/arl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/arl.c</a></td><td class='right'>729</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/cnp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/cnp.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/core.c</a></td><td class='right'>291</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 96.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/core.h</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/core_ssram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/core_ssram.c</a></td><td class='right'>267</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.8%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/icl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/icl.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/lnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/lnl.c</a></td><td class='right'>549</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/mtl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/mtl.c</a></td><td class='right'>93</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/spt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/spt.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmc/tgl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmc/tgl.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmt/class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmt/class.c</a></td><td class='right'>43</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmt/class.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmt/class.h</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmt/crashlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmt/crashlog.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmt/telemetry.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmt/telemetry.c</a></td><td class='right'>193</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/pmt/telemetry.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/pmt/telemetry.h</a></td><td class='right'>126</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/tpmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/tpmi.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/vbtn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/vbtn.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/vsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/vsec.c</a></td><td class='right'>129</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/vsec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/vsec.h</a></td><td class='right'>45</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/wmi/sbl-fw-update.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/wmi/sbl-fw-update.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel/wmi/thunderbolt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel/wmi/thunderbolt.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/intel_ips.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/intel_ips.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/lenovo-yogabook.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/lenovo-yogabook.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/platform/x86/silicom-platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/silicom-platform.c</a></td><td class='right'>1004</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 87.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/thinkpad_acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/thinkpad_acpi.c</a></td><td class='right'>104</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/wmi.c</a></td><td class='right'>496</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 4.5%;'/><td class='none' style='width: 94.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/x86-android-tablets/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/x86-android-tablets/core.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/x86-android-tablets/lenovo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/x86-android-tablets/lenovo.c</a></td><td class='right'>124</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/platform/x86/x86-android-tablets/x86-android-tablets.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/platform/x86/x86-android-tablets/x86-android-tablets.h</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/amlogic/meson-ee-pwrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/amlogic/meson-ee-pwrc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/pmdomain/arm/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/arm/Kconfig</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/arm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/arm/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/arm/scmi_perf_domain.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/arm/scmi_perf_domain.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/pmdomain/arm/scpi_pm_domain.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/arm/scpi_pm_domain.c</a> (renamed from drivers/firmware/scpi_pm_domain.c)</td><td class='right'>0</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/pmdomain/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/core.c</a> (renamed from drivers/base/power/domain.c)</td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='mov'><a href='/cgit/linux.git/diff/drivers/pmdomain/governor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/governor.c</a> (renamed from drivers/base/power/domain_governor.c)</td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/gpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/gpc.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/gpcv2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/gpcv2.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/imx8m-blk-ctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/imx8m-blk-ctrl.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/imx8mp-blk-ctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/imx8mp-blk-ctrl.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/imx93-blk-ctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/imx93-blk-ctrl.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/imx/imx93-pd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/imx/imx93-pd.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/qcom/cpr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/qcom/cpr.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/qcom/rpmhpd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/qcom/rpmhpd.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/qcom/rpmpd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/qcom/rpmpd.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pmdomain/xilinx/zynqmp-pm-domains.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pmdomain/xilinx/zynqmp-pm-domains.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pnp/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pnp/driver.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pnp/isapnp/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pnp/isapnp/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pnp/pnpacpi/rsparser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pnp/pnpacpi/rsparser.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pnp/pnpbios/bioscalls.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pnp/pnpbios/bioscalls.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/as3722-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/as3722-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/at91-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/at91-poweroff.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/at91-reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/at91-reset.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/at91-sama5d2_shdwc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/at91-sama5d2_shdwc.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/atc260x-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/atc260x-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/gpio-restart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/gpio-restart.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/ltc2952-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/ltc2952-poweroff.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/mt6323-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/mt6323-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/pwr-mlxbf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/pwr-mlxbf.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/qnap-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/qnap-poweroff.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/regulator-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/regulator-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/restart-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/restart-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/rmobile-reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/rmobile-reset.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/syscon-poweroff.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/syscon-poweroff.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/reset/tps65086-restart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/reset/tps65086-restart.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/bq24190_charger.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/bq24190_charger.c</a></td><td class='right'>457</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.3%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/bq256xx_charger.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/bq256xx_charger.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/bq27xxx_battery.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/bq27xxx_battery.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/bq27xxx_battery_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/bq27xxx_battery_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/cw2015_battery.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/cw2015_battery.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/power_supply_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/power_supply_core.c</a></td><td class='right'>167</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/qcom_battmgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/qcom_battmgr.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/power/supply/qcom_pmi8998_charger.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/power/supply/qcom_pmi8998_charger.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/powercap/dtpm_cpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/powercap/dtpm_cpu.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/powercap/dtpm_devfreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/powercap/dtpm_devfreq.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ptp/ptp_ines.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ptp/ptp_ines.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ptp/ptp_ocp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ptp/ptp_ocp.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/core.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-atmel-hlcdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-atmel-hlcdc.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-atmel-tcb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-atmel-tcb.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-bcm-kona.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-bcm-kona.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-bcm2835.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-bcm2835.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-berlin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-berlin.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-brcmstb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-brcmstb.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-crc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-crc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-cros-ec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-cros-ec.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-dwc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-dwc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-img.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-img.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-imx-tpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-imx-tpm.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-jz4740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-jz4740.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-lpc18xx-sct.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-lpc18xx-sct.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-lpc32xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-lpc32xx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-mediatek.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-mediatek.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-meson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-meson.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-omap-dmtimer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-omap-dmtimer.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-renesas-tpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-renesas-tpu.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-rockchip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-rockchip.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-samsung.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-samsung.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-sti.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-sti.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-stm32-lp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-stm32-lp.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-stm32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-stm32.c</a></td><td class='right'>106</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-stmpe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-stmpe.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-tegra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-tegra.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-tiecap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-tiecap.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-tiehrpwm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-tiehrpwm.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-twl-led.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-twl-led.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-twl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-twl.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/pwm-vt8500.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/pwm-vt8500.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/pwm/sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/pwm/sysfs.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rapidio/devices/tsi721.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rapidio/devices/tsi721.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rapidio/devices/tsi721_dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rapidio/devices/tsi721_dma.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/arizona-ldo1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/arizona-ldo1.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/bd9571mwv-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/bd9571mwv-regulator.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/core.c</a></td><td class='right'>130</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/db8500-prcmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/db8500-prcmu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/regulator/event.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/event.c</a></td><td class='right'>91</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/of_regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/of_regulator.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/palmas-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/palmas-regulator.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/pwm-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/pwm-regulator.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/qcom-rpmh-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/qcom-rpmh-regulator.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/qcom_smd-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/qcom_smd-regulator.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/qcom_spmi-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/qcom_spmi-regulator.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/regulator/regnl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/regnl.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/stm32-vrefbuf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/stm32-vrefbuf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/stpmic1_regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/stpmic1_regulator.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/uniphier-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/uniphier-regulator.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/userspace-consumer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/userspace-consumer.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/virtual.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/virtual.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/regulator/wm8350-regulator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/regulator/wm8350-regulator.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/remoteproc/imx_dsp_rproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/remoteproc/imx_dsp_rproc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/remoteproc/qcom_q6v5_pas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/remoteproc/qcom_q6v5_pas.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/remoteproc/ti_k3_dsp_remoteproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/remoteproc/ti_k3_dsp_remoteproc.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/core.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/hisilicon/hi6220_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/hisilicon/hi6220_reset.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-brcmstb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-brcmstb.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-meson-audio-arb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-meson-audio-arb.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-meson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-meson.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-npcm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-npcm.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-qcom-aoss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-qcom-aoss.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-qcom-pdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-qcom-pdc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-simple.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-simple.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-sunplus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-sunplus.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/reset-uniphier-glue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/reset-uniphier-glue.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/reset/sti/reset-syscfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/reset/sti/reset-syscfg.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rpmsg/virtio_rpmsg_bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rpmsg/virtio_rpmsg_bus.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/Kconfig</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/class.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-ac100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-ac100.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-cmos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-cmos.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-da9063.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-da9063.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-ds3232.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-ds3232.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-ma35d1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-ma35d1.c</a></td><td class='right'>304</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-max31335.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-max31335.c</a></td><td class='right'>697</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 8.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 91.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-mc146818-lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-mc146818-lib.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-nct3018y.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-nct3018y.c</a></td><td class='right'>52</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-rv8803.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-rv8803.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/rtc/rtc-tps6594.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/rtc/rtc-tps6594.c</a></td><td class='right'>454</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/block/dasd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/block/dasd.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/block/scm_blk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/block/scm_blk.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/char/con3215.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/char/con3215.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/char/con3270.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/char/con3270.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/char/uvdevice.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/char/uvdevice.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/chsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/chsc.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/chsc_sch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/chsc_sch.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/cio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/cio.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/cio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/cio.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/css.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/css.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/device.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/device_pgid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/device_pgid.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/eadm_sch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/eadm_sch.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/vfio_ccw_chp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/vfio_ccw_chp.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/vfio_ccw_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/vfio_ccw_drv.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/vfio_ccw_fsm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/vfio_ccw_fsm.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/cio/vfio_ccw_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/cio/vfio_ccw_ops.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/ap_bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/ap_bus.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/ap_bus.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/ap_bus.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/ap_card.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/ap_card.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/ap_queue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/ap_queue.c</a></td><td class='right'>200</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/vfio_ap_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/vfio_ap_ops.c</a></td><td class='right'>300</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 96.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/vfio_ap_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/vfio_ap_private.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/zcrypt_api.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/zcrypt_api.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/crypto/zcrypt_cex4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/crypto/zcrypt_cex4.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/net/ism.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/net/ism.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/net/ism_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/net/ism_drv.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/s390/scsi/zfcp_fc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/s390/scsi/zfcp_fc.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/3w-sas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/3w-sas.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/a3000.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/a3000.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/a4000t.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/a4000t.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aacraid/aacraid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aacraid/aacraid.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aacraid/commsup.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aacraid/commsup.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aacraid/linit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aacraid/linit.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aacraid/src.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aacraid/src.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aic7xxx/aic7770_osm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aic7xxx/aic7770_osm.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aic7xxx/aic7xxx_osm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aic7xxx/aic7xxx_osm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/aic7xxx/aic7xxx_osm_pci.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/arcmsr/arcmsr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/arcmsr/arcmsr.h</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/arcmsr/arcmsr_hba.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/arcmsr/arcmsr_hba.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/atari_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/atari_scsi.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/be2iscsi/be_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/be2iscsi/be_main.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/bfa/bfad_bsg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/bfa/bfad_bsg.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/bnx2fc/bnx2fc_fcoe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/bnx2fc/bnx2fc_fcoe.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/bvme6000_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/bvme6000_scsi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/ch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/ch.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/csiostor/csio_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/csiostor/csio_init.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/dc395x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/dc395x.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/elx/libefc/efc_node.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/elx/libefc/efc_node.h</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fcoe/fcoe_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fcoe/fcoe_sysfs.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic.h</a></td><td class='right'>68</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_debugfs.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_fcs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_fcs.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_isr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_isr.c</a></td><td class='right'>168</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_main.c</a></td><td class='right'>144</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_res.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_res.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_scsi.c</a></td><td class='right'>869</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.8%;'/><td class='rem' style='width: 4.7%;'/><td class='none' style='width: 89.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_stats.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/fnic_trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/fnic_trace.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/vnic_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/vnic_dev.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/fnic/vnic_scsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/fnic/vnic_scsi.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/hisi_sas/hisi_sas_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/hisi_sas/hisi_sas_main.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/hisi_sas/hisi_sas_v3_hw.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/ibmvscsi/ibmvfc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/ibmvscsi/ibmvfc.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/ibmvscsi/ibmvscsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/ibmvscsi/ibmvscsi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/ipr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/ipr.c</a></td><td class='right'>55</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/isci/request.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/isci/request.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/isci/request.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/isci/request.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/isci/task.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/isci/task.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/jazz_esp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/jazz_esp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/libfc/fc_fcp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/libfc/fc_fcp.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_attr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_attr.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_els.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_els.c</a></td><td class='right'>67</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_hbadisc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_hbadisc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_init.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_mbox.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_mem.c</a></td><td class='right'>47</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_sli.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_sli.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_sli.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_sli.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_version.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_version.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/lpfc/lpfc_vmid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/lpfc/lpfc_vmid.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mac_esp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mac_esp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mac_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mac_scsi.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi/mpi30_ioc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi/mpi30_ioc.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi3mr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi3mr.h</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi3mr_app.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi3mr_app.c</a></td><td class='right'>536</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 93.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi3mr_fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi3mr_fw.c</a></td><td class='right'>120</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi3mr_os.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi3mr_os.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpi3mr/mpi3mr_transport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpi3mr/mpi3mr_transport.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpi/mpi2_image.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpi/mpi2_image.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpi/mpi2_ioc.h</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_base.c</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_base.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_config.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_config.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_ctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_ctl.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_scsih.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_scsih.c</a></td><td class='right'>56</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_transport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_transport.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_trigger_pages.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_trigger_pages.h</a></td><td class='right'>44</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mpt3sas/mpt3sas_warpdrive.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mpt3sas/mpt3sas_warpdrive.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/mvme16x_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/mvme16x_scsi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/qla2xxx/qla_os.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/qla2xxx/qla_os.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/qlogicpti.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/qlogicpti.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/scsi_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/scsi_debug.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/scsi_error.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/scsi_error.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sd.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sd_zbc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sd_zbc.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sgiwd93.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sgiwd93.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/smartpqi/smartpqi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/smartpqi/smartpqi.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/smartpqi/smartpqi_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/smartpqi/smartpqi_init.c</a></td><td class='right'>89</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sni_53c710.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sni_53c710.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sun3_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sun3_scsi.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sun3x_esp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sun3x_esp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/sun_esp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/sun_esp.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/scsi/virtio_scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/scsi/virtio_scsi.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/sh/maple/maple.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/sh/maple/maple.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/apple/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/Kconfig</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/apple/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/Makefile</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/soc/apple/mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/mailbox.c</a></td><td class='right'>437</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/soc/apple/mailbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/mailbox.h</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/apple/rtkit-internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/rtkit-internal.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/apple/rtkit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/apple/rtkit.c</a></td><td class='right'>133</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/fsl/qe/qmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/fsl/qe/qmc.c</a></td><td class='right'>658</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.0%;'/><td class='rem' style='width: 1.9%;'/><td class='none' style='width: 92.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/fsl/qe/tsa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/fsl/qe/tsa.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/hisilicon/kunpeng_hccs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/hisilicon/kunpeng_hccs.c</a></td><td class='right'>152</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/hisilicon/kunpeng_hccs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/hisilicon/kunpeng_hccs.h</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/mediatek/mt8188-mmsys.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/mediatek/mt8188-mmsys.h</a></td><td class='right'>210</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/mediatek/mtk-mmsys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/mediatek/mtk-mmsys.c</a></td><td class='right'>39</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/mediatek/mtk-mmsys.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/mediatek/mtk-mmsys.h</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/mediatek/mtk-mutex.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/mediatek/mtk-mutex.c</a></td><td class='right'>51</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/mediatek/mtk-svs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/mediatek/mtk-svs.c</a></td><td class='right'>1678</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 12.1%;'/><td class='rem' style='width: 8.2%;'/><td class='none' style='width: 79.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/microchip/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/microchip/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/microchip/mpfs-sys-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/microchip/mpfs-sys-controller.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/pxa/ssp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/pxa/ssp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/Kconfig</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/llcc-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/llcc-qcom.c</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/pmic_glink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/pmic_glink.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/pmic_glink_altmode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/pmic_glink_altmode.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/soc/qcom/pmic_pdcharger_ulog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/pmic_pdcharger_ulog.c</a></td><td class='right'>166</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/soc/qcom/pmic_pdcharger_ulog.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/pmic_pdcharger_ulog.h</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/qcom/socinfo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/qcom/socinfo.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/renesas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/renesas/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/renesas/renesas-soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/renesas/renesas-soc.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/samsung/exynos-chipid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/samsung/exynos-chipid.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/soc/sifive/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/sifive/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/soc/sifive/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/sifive/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/ti/k3-socinfo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/ti/k3-socinfo.c</a></td><td class='right'>73</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/xilinx/xlnx_event_manager.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/xilinx/xlnx_event_manager.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soc/xilinx/zynqmp_power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soc/xilinx/zynqmp_power.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/amd_manager.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/amd_manager.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/bus.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/generic_bandwidth_allocation.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/generic_bandwidth_allocation.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/intel_ace2x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/intel_ace2x.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/intel_auxdevice.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/intel_auxdevice.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/master.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/master.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/qcom.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/slave.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/slave.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/soundwire/stream.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/soundwire/stream.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/Kconfig</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/atmel-quadspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/atmel-quadspi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-ath79.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-ath79.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-atmel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-atmel.c</a></td><td class='right'>95</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-axi-spi-engine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-axi-spi-engine.c</a></td><td class='right'>519</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.0%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 93.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-bcm-qspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-bcm-qspi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-cadence-quadspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-cadence-quadspi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-cadence-xspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-cadence-xspi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-cadence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-cadence.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-coldfire-qspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-coldfire-qspi.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-cs42l43.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-cs42l43.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-dw-mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-dw-mmio.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-geni-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-geni-qcom.c</a></td><td class='right'>96</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-imx.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-ingenic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-ingenic.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-intel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-intel.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-ljca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-ljca.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-mem.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-mpc52xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-mpc52xx.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-npcm-fiu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-npcm-fiu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-pl022.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-pl022.c</a></td><td class='right'>382</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 3.8%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sh-msiof.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sh-msiof.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sprd-adi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sprd-adi.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sprd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sprd.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-st-ssc4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-st-ssc4.c</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-stm32-qspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-stm32-qspi.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-stm32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-stm32.c</a></td><td class='right'>638</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.5%;'/><td class='rem' style='width: 2.2%;'/><td class='none' style='width: 92.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sun4i.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sun4i.c</a></td><td class='right'>72</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sun6i.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sun6i.c</a></td><td class='right'>148</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-sunplus-sp7021.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-sunplus-sp7021.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-synquacer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-synquacer.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-tegra114.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-tegra114.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-tegra20-sflash.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-tegra20-sflash.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-tegra20-slink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-tegra20-slink.c</a></td><td class='right'>98</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-tegra210-quad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-tegra210-quad.c</a></td><td class='right'>80</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-ti-qspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-ti-qspi.c</a></td><td class='right'>103</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-topcliff-pch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-topcliff-pch.c</a></td><td class='right'>226</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 97.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-uniphier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-uniphier.c</a></td><td class='right'>194</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 97.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-wpcm-fiu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-wpcm-fiu.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-xcomm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-xcomm.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-xilinx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-xilinx.c</a></td><td class='right'>58</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-xlp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-xlp.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-xtensa-xtfpga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-xtensa-xtfpga.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-zynq-qspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-zynq-qspi.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi-zynqmp-gqspi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi-zynqmp-gqspi.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spi/spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spi/spi.c</a></td><td class='right'>262</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spmi/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spmi/hisi-spmi-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/hisi-spmi-controller.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/spmi/spmi-devres.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/spmi-devres.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spmi/spmi-mtk-pmif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/spmi-mtk-pmif.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spmi/spmi-pmic-arb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/spmi-pmic-arb.c</a></td><td class='right'>87</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/spmi/spmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/spmi/spmi.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/greybus/i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/greybus/i2c.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/i2c/atomisp-gc0310.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/i2c/atomisp-gc0310.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/i2c/atomisp-gc2235.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/i2c/atomisp-gc2235.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/i2c/atomisp-ov2722.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/i2c/atomisp-ov2722.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/pci/atomisp_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/pci/atomisp_cmd.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/pci/atomisp_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/pci/atomisp_csi2.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/pci/atomisp_ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/pci/atomisp_ioctl.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/pci/atomisp_subdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/pci/atomisp_subdev.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/atomisp/pci/atomisp_tpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/atomisp/pci/atomisp_tpg.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/deprecated/atmel/atmel-isc-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/deprecated/atmel/atmel-isc-base.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-ic-prp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-ic-prp.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-ic-prpencvf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-ic-prpencvf.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-media-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-media-capture.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-media-csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-media-csi.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-media-utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-media-utils.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-media-vdic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-media-vdic.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx-media.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx-media.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/imx/imx6-mipi-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/imx/imx6-mipi-csi2.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/ipu3/ipu3-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/ipu3/ipu3-v4l2.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/meson/vdec/vdec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/meson/vdec/vdec.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/omap4iss/iss_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/omap4iss/iss_csi2.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/omap4iss/iss_ipipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/omap4iss/iss_ipipe.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/omap4iss/iss_ipipeif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/omap4iss/iss_ipipeif.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/omap4iss/iss_resizer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/omap4iss/iss_resizer.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/rkvdec/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/rkvdec/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/rkvdec/rkvdec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/rkvdec/rkvdec.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/Kconfig</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/Kconfig</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/Makefile</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/TODO.txt?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/TODO.txt</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-camss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-camss.c</a></td><td class='right'>436</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-camss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-camss.h</a></td><td class='right'>134</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-capture.c</a></td><td class='right'>603</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 7.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-capture.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-capture.h</a></td><td class='right'>86</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-isp-hw-ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-isp-hw-ops.c</a></td><td class='right'>445</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-isp.c</a></td><td class='right'>385</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-isp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-isp.h</a></td><td class='right'>428</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-video.c</a></td><td class='right'>572</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/staging/media/starfive/camss/stf-video.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/starfive/camss/stf-video.h</a></td><td class='right'>100</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/cedrus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/cedrus/Kconfig</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/cedrus/TODO?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/cedrus/TODO</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/cedrus/cedrus_h264.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/cedrus/cedrus_h264.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/cedrus/cedrus_h265.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/cedrus/cedrus_h265.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_capture.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_params.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_proc.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/tegra-video/csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/tegra-video/csi.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/tegra-video/vi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/tegra-video/vi.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/media/tegra-video/vip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/media/tegra-video/vip.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/dot11d.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/dot11d.c</a></td><td class='right'>165</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.0%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/dot11d.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/dot11d.h</a></td><td class='right'>84</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c</a></td><td class='right'>41</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/rtl_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/rtl_core.c</a></td><td class='right'>101</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 98.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/rtl_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/rtl_core.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/rtl_dm.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl8192e/rtl_wx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl8192e/rtl_wx.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_BAProc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_BAProc.c</a></td><td class='right'>228</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.4%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_HT.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_HT.h</a></td><td class='right'>35</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_HTProc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_HTProc.c</a></td><td class='right'>371</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 2.8%;'/><td class='none' style='width: 95.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_Qos.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_Qos.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_TS.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_TS.h</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtl819x_TSProc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtl819x_TSProc.c</a></td><td class='right'>156</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib.h</a></td><td class='right'>71</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_module.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_module.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_rx.c</a></td><td class='right'>82</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.7%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_softmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_softmac.c</a></td><td class='right'>387</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 3.9%;'/><td class='none' style='width: 95.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_softmac_wx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_softmac_wx.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_tx.c</a></td><td class='right'>66</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8192e/rtllib_wx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8192e/rtllib_wx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/os_intfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/os_intfs.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl8712_efuse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl8712_efuse.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl8712_recv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl8712_recv.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl8712_xmit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl8712_xmit.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl871x_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl871x_cmd.c</a></td><td class='right'>159</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl871x_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl871x_cmd.h</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl871x_ioctl_linux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl871x_ioctl_linux.c</a></td><td class='right'>203</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 1.6%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/TODO?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/TODO</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c</a></td><td class='right'>271</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 96.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c</a></td><td class='right'>668</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 4.6%;'/><td class='none' style='width: 91.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c</a></td><td class='right'>113</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vme_user/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vme_user/Kconfig</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vme_user/vme.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vme_user/vme.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vt6655/card.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vt6655/card.c</a></td><td class='right'>90</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vt6655/card.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vt6655/card.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vt6655/device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vt6655/device.h</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vt6655/device_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vt6655/device_main.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/staging/vt6655/rxtx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/staging/vt6655/rxtx.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/target/target_core_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/target/target_core_device.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/target/target_core_pr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/target/target_core_pr.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/target/target_core_transport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/target/target_core_transport.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/target/target_core_xcopy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/target/target_core_xcopy.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/call.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/call.c</a></td><td class='right'>161</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/core.c</a></td><td class='right'>62</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/device.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/ffa_abi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/ffa_abi.c</a></td><td class='right'>107</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/optee_ffa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/optee_ffa.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/optee_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/optee_private.h</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/optee/smc_abi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/optee/smc_abi.c</a></td><td class='right'>112</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/tee_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/tee_core.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tee/tee_shm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tee/tee_shm.c</a></td><td class='right'>78</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/amlogic_thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/amlogic_thermal.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/cpuidle_cooling.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/cpuidle_cooling.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/gov_power_allocator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/gov_power_allocator.c</a></td><td class='right'>366</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.6%;'/><td class='rem' style='width: 1.8%;'/><td class='none' style='width: 95.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/intel/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/intel/int340x_thermal/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/intel/int340x_thermal/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/intel/int340x_thermal/int340x_thermal_zone.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/intel/int340x_thermal/int340x_thermal_zone.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/intel/intel_hfi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/intel/intel_hfi.c</a></td><td class='right'>119</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/loongson2_thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/loongson2_thermal.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/samsung/exynos_tmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/samsung/exynos_tmu.c</a></td><td class='right'>529</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.2%;'/><td class='rem' style='width: 3.2%;'/><td class='none' style='width: 93.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/sun8i_thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/sun8i_thermal.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_core.c</a></td><td class='right'>231</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 97.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_core.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_debugfs.c</a></td><td class='right'>839</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 10.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 89.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_debugfs.h</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_helpers.c</a></td><td class='right'>38</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_hwmon.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_netlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_netlink.c</a></td><td class='right'>139</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_netlink.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_netlink.h</a></td><td class='right'>75</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_of.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_sysfs.c</a></td><td class='right'>121</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_trace_ipa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_trace_ipa.h</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thermal/thermal_trip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thermal/thermal_trip.c</a></td><td class='right'>76</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/domain.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/domain.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/icm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/icm.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/nhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/nhi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/nhi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/nhi.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/switch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/switch.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/tb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/tb.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/tb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/tb.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/tmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/tmu.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/tunnel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/tunnel.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/usb4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/usb4.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/thunderbolt/xdomain.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/thunderbolt/xdomain.c</a></td><td class='right'>54</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/amiserial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/amiserial.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/ehv_bytechan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/ehv_bytechan.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/goldfish.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/goldfish.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_console.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_console.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_console.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_console.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_dcc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_dcc.c</a></td><td class='right'>32</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_iucv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_iucv.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_opal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_opal.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_riscv_sbi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_riscv_sbi.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_rtas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_rtas.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_udbg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_udbg.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_vio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_vio.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvc_xen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvc_xen.c</a></td><td class='right'>23</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/hvc/hvsi_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/hvc/hvsi_lib.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/ipwireless/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/ipwireless/main.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/mips_ejtag_fdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/mips_ejtag_fdc.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/moxa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/moxa.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/mxser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/mxser.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/n_gsm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/n_gsm.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/n_hdlc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/n_hdlc.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/nozomi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/nozomi.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serdev/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serdev/core.c</a></td><td class='right'>31</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serdev/serdev-ttyport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serdev/serdev-ttyport.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_aspeed_vuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_aspeed_vuart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_bcm2835aux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_bcm2835aux.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_bcm7271.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_bcm7271.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_core.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_dw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_dw.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_dwlib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_dwlib.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_early.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_early.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_em.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_em.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_exar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_exar.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_fsl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_fsl.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_ingenic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_ingenic.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_ioc3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_ioc3.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_lpc18xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_lpc18xx.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_lpss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_lpss.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_mtk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_mtk.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_of.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_omap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_omap.c</a></td><td class='right'>21</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_pci.c</a></td><td class='right'>61</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_pci1xxxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_pci1xxxx.c</a></td><td class='right'>210</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_pxa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_pxa.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_tegra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_tegra.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/8250_uniphier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/8250_uniphier.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/8250/serial_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/8250/serial_cs.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/Kconfig</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/altera_jtaguart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/altera_jtaguart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/altera_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/altera_uart.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/amba-pl011.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/amba-pl011.c</a></td><td class='right'>380</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 2.3%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/apbuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/apbuart.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/ar933x_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/ar933x_uart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/atmel_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/atmel_serial.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/bcm63xx_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/bcm63xx_uart.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/clps711x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/clps711x.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/cpm_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/cpm_uart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/digicolor-usart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/digicolor-usart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/earlycon-riscv-sbi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/earlycon-riscv-sbi.c</a></td><td class='right'>27</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/esp32_acm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/esp32_acm.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/esp32_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/esp32_uart.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/fsl_linflexuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/fsl_linflexuart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/fsl_lpuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/fsl_lpuart.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/imx.c</a></td><td class='right'>63</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/jsm/jsm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/jsm/jsm.h</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/jsm/jsm_cls.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/jsm/jsm_cls.c</a></td><td class='right'>36</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/jsm/jsm_neo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/jsm/jsm_neo.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/lantiq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/lantiq.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/liteuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/liteuart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/lpc32xx_hs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/lpc32xx_hs.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/ma35d1_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/ma35d1_serial.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/max310x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/max310x.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/mcf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/mcf.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/meson_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/meson_uart.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/milbeaut_usio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/milbeaut_usio.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/mpc52xx_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/mpc52xx_uart.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/msm_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/msm_serial.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/mxs-auart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/mxs-auart.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/omap-serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/omap-serial.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/owl-uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/owl-uart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/pic32_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/pic32_uart.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/qcom_geni_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/qcom_geni_serial.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/rda-uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/rda-uart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/rp2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/rp2.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sa1100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sa1100.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/samsung_tty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/samsung_tty.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sc16is7xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sc16is7xx.c</a></td><td class='right'>561</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.5%;'/><td class='rem' style='width: 3.3%;'/><td class='none' style='width: 93.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sccnxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sccnxp.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/serial-tegra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/serial-tegra.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/serial_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/serial_core.c</a></td><td class='right'>88</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/serial_txx9.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/serial_txx9.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sh-sci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sh-sci.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sifive.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sifive.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sprd_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sprd_serial.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/st-asc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/st-asc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/stm32-usart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/stm32-usart.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sunhv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sunhv.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sunplus-uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sunplus-uart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sunsab.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sunsab.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sunsu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sunsu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/sunzilog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/sunzilog.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/tegra-tcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/tegra-tcu.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/timbuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/timbuart.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/uartlite.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/uartlite.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/ucc_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/ucc_uart.c</a></td><td class='right'>34</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/serial/xilinx_uartps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/serial/xilinx_uartps.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/sysrq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/sysrq.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/tty_io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/tty_io.c</a></td><td class='right'>49</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/tty_ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/tty_ioctl.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/tty_port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/tty_port.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/vt/consolemap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/vt/consolemap.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/tty/vt/keyboard.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/tty/vt/keyboard.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/core/ufs-fault-injection.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/core/ufs-fault-injection.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/core/ufs-fault-injection.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/core/ufs-fault-injection.h</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/core/ufs-sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/core/ufs-sysfs.c</a></td><td class='right'>151</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/core/ufshcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/core/ufshcd.c</a></td><td class='right'>184</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.7%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufs-exynos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufs-exynos.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufs-hisi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufs-hisi.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufs-mediatek.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufs-mediatek.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufs-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufs-qcom.c</a></td><td class='right'>485</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 4.2%;'/><td class='none' style='width: 94.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufs-qcom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufs-qcom.h</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufshcd-pltfrm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufshcd-pltfrm.c</a></td><td class='right'>123</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 98.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/ufs/host/ufshcd-pltfrm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ufs/host/ufshcd-pltfrm.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/uio/uio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/uio/uio.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/atm/ueagle-atm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/atm/ueagle-atm.c</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/cdns3/cdns3-gadget.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/cdns3/cdns3-gadget.c</a></td><td class='right'>149</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.3%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 98.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/cdns3/cdns3-gadget.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/cdns3/cdns3-gadget.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/cdns3/cdns3-plat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/cdns3/cdns3-plat.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/cdns3/cdns3-starfive.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/cdns3/cdns3-starfive.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/cdns3/cdnsp-debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/cdns3/cdnsp-debug.h</a></td><td class='right'>354</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.1%;'/><td class='rem' style='width: 2.1%;'/><td class='none' style='width: 95.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/chipidea/ci_hdrc_imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/chipidea/ci_hdrc_imx.c</a></td><td class='right'>17</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/chipidea/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/chipidea/core.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/chipidea/udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/chipidea/udc.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/class/cdc-acm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/class/cdc-acm.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/driver.c</a></td><td class='right'>64</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/generic.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/hub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/hub.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/quirks.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/quirks.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/usb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/core/usb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/core/usb.h</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc2/params.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc2/params.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/core.c</a></td><td class='right'>60</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.5%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/core.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/dwc3-imx8mp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/dwc3-imx8mp.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/dwc3-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/dwc3-qcom.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/dwc3-xilinx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/dwc3-xilinx.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/ep0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/ep0.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/gadget.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/gadget.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/dwc3/gadget.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/dwc3/gadget.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/fotg210/fotg210-hcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/fotg210/fotg210-hcd.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/fotg210/fotg210-udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/fotg210/fotg210-udc.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/configfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/configfs.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_fs.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_hid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_hid.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_midi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_midi.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_ncm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_ncm.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_tcm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_tcm.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_uac1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_uac1.c</a></td><td class='right'>83</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_uac2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_uac2.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_uvc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_uvc.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/f_uvc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/f_uvc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/u_ether.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/u_ether.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/u_ncm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/u_ncm.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/u_uvc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/u_uvc.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/uvc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/uvc.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/uvc_configfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/uvc_configfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/uvc_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/uvc_v4l2.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/uvc_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/uvc_video.c</a></td><td class='right'>445</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.1%;'/><td class='rem' style='width: 1.3%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/function/uvc_video.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/function/uvc_video.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/legacy/webcam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/legacy/webcam.c</a></td><td class='right'>333</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 1.0%;'/><td class='none' style='width: 96.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/at91_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/at91_udc.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/atmel_usba_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/atmel_usba_udc.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/cdns2/cdns2-debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/cdns2/cdns2-debug.h</a></td><td class='right'>138</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/core.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/fsl_udc_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/fsl_udc_core.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/gr_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/gr_udc.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/lpc32xx_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/lpc32xx_udc.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/max3420_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/max3420_udc.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/mv_udc_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/mv_udc_core.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/gadget/udc/pxa25x_udc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/gadget/udc/pxa25x_udc.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/fsl-mph-dr-of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/fsl-mph-dr-of.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/max3421-hcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/max3421-hcd.c</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-dbgcap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-dbgcap.c</a></td><td class='right'>132</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.8%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-dbgcap.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-dbgcap.h</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-mem.c</a></td><td class='right'>110</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-mtk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-mtk.c</a></td><td class='right'>40</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-mtk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-mtk.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-pci.c</a></td><td class='right'>142</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 1.2%;'/><td class='none' style='width: 98.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-plat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-plat.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci-ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci-ring.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci.c</a></td><td class='right'>213</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.5%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/host/xhci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/host/xhci.h</a></td><td class='right'>19</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/misc/iowarrior.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/misc/iowarrior.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/misc/onboard_usb_hub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/misc/onboard_usb_hub.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/misc/onboard_usb_hub.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/misc/onboard_usb_hub.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/misc/qcom_eud.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/misc/qcom_eud.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/misc/yurex.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/misc/yurex.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/mon/mon_bin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/mon/mon_bin.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/mon/mon_stat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/mon/mon_stat.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/mon/mon_text.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/mon/mon_text.c</a></td><td class='right'>28</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/phy/phy-generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/phy/phy-generic.c</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/phy/phy-mxs-usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/phy/phy-mxs-usb.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/phy/phy-twl6030-usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/phy/phy-twl6030-usb.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/serial/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/serial/bus.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/serial/ftdi_sio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/serial/ftdi_sio.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/serial/ftdi_sio_ids.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/serial/ftdi_sio_ids.h</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/serial/option.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/serial/option.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/serial/usb-serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/serial/usb-serial.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/storage/sierra_ms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/storage/sierra_ms.c</a></td><td class='right'>16</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/storage/uas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/storage/uas.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/storage/unusual_devs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/storage/unusual_devs.h</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/class.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/mux/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/mux/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/mux/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/mux/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/usb/typec/mux/wcd939x-usbss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/mux/wcd939x-usbss.c</a></td><td class='right'>779</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 9.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 90.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/pd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/pd.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/tcpm/tcpci_maxim_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/tcpm/tcpci_maxim_core.c</a></td><td class='right'>20</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/tcpm/tcpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/tcpm/tcpm.c</a></td><td class='right'>419</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.9%;'/><td class='rem' style='width: 1.1%;'/><td class='none' style='width: 94.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/tipd/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/tipd/core.c</a></td><td class='right'>177</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.9%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/tipd/tps6598x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/tipd/tps6598x.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/ucsi/ucsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/ucsi/ucsi.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/ucsi/ucsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/ucsi/ucsi.h</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/typec/ucsi/ucsi_glink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/typec/ucsi/ucsi_glink.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/usbip/stub_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/usbip/stub_main.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/usbip/vudc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/usbip/vudc.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/usbip/vudc_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/usbip/vudc_dev.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/usb/usbip/vudc_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/usb/usbip/vudc_main.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/alibaba/eni_vdpa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/alibaba/eni_vdpa.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/mlx5/core/mlx5_vdpa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/mlx5/core/mlx5_vdpa.h</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/mlx5/core/mr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/mlx5/core/mr.c</a></td><td class='right'>69</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/mlx5/net/mlx5_vnet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/mlx5/net/mlx5_vnet.c</a></td><td class='right'>216</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 97.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/pds/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/pds/debugfs.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/pds/vdpa_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/pds/vdpa_dev.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/vdpa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/vdpa.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vdpa/vdpa_user/vduse_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vdpa/vdpa_user/vduse_dev.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/Kconfig</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/vfio/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/debugfs.c</a></td><td class='right'>92</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 98.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c</a></td><td class='right'>7</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/pds/dirty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/pds/dirty.c</a></td><td class='right'>309</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.3%;'/><td class='rem' style='width: 1.4%;'/><td class='none' style='width: 96.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/pds/dirty.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/pds/dirty.h</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/pds/pci_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/pds/pci_drv.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/pds/vfio_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/pds/vfio_dev.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/pds/vfio_dev.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/pds/vfio_dev.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/vfio_pci_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/vfio_pci_core.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/vfio_pci_intrs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/vfio_pci_intrs.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/pci/vfio_pci_rdwr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/vfio_pci_rdwr.c</a></td><td class='right'>57</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/vfio/pci/virtio/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/virtio/Kconfig</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/vfio/pci/virtio/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/virtio/Makefile</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/vfio/pci/virtio/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/pci/virtio/main.c</a></td><td class='right'>576</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 6.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 93.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/platform/vfio_platform_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/platform/vfio_platform_irq.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/vfio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/vfio.h</a></td><td class='right'>14</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.2%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/vfio_iommu_type1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/vfio_iommu_type1.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vfio/vfio_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vfio/vfio_main.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vhost/vdpa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vhost/vdpa.c</a></td><td class='right'>30</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vhost/vhost.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vhost/vhost.c</a></td><td class='right'>10</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vhost/vhost.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vhost/vhost.h</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/vhost/vsock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/vhost/vsock.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/Kconfig</a></td><td class='right'>18</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/backlight/cr_bllcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/cr_bllcd.c</a></td><td class='right'>264</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.2%;'/><td class='none' style='width: 96.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/hx8357.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/hx8357.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 99.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/ili922x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/ili922x.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/lm3630a_bl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/lm3630a_bl.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/lp855x_bl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/lp855x_bl.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/video/backlight/mp3309c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/mp3309c.c</a></td><td class='right'>444</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 5.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 94.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/backlight/pwm_bl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/backlight/pwm_bl.c</a></td><td class='right'>46</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/console/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/console/Kconfig</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/Kconfig</a></td><td class='right'>70</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 99.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/Makefile</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/amba-clcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/amba-clcd.c</a></td><td class='right'>986</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 11.9%;'/><td class='none' style='width: 88.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/core/fb_ddc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/core/fb_ddc.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/core/fb_defio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/core/fb_defio.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/cyber2000fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/cyber2000fb.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/fsl-diu-fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/fsl-diu-fb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/hgafb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/hgafb.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/hyperv_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/hyperv_fb.c</a></td><td class='right'>26</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.2%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/i740fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/i740fb.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/imxfb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/imxfb.c</a></td><td class='right'>179</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.2%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 97.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/Makefile</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/intelfb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/intelfb.h</a></td><td class='right'>382</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 4.6%;'/><td class='none' style='width: 95.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/intelfb_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/intelfb_i2c.c</a></td><td class='right'>209</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.5%;'/><td class='none' style='width: 97.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/intelfbdrv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/intelfbdrv.c</a></td><td class='right'>1680</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 20.3%;'/><td class='none' style='width: 79.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/intelfbhw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/intelfbhw.c</a></td><td class='right'>2115</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 25.5%;'/><td class='none' style='width: 74.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/intelfb/intelfbhw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/intelfb/intelfbhw.h</a></td><td class='right'>609</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 7.3%;'/><td class='none' style='width: 92.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/matrox/i2c-matroxfb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/matrox/i2c-matroxfb.c</a></td><td class='right'>15</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/mmp/hw/mmp_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/mmp/hw/mmp_spi.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/s3fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/s3fb.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/sis/sis_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/sis/sis_main.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.4%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/ssd1307fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/ssd1307fb.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/stifb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/stifb.c</a></td><td class='right'>109</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.7%;'/><td class='rem' style='width: 0.6%;'/><td class='none' style='width: 98.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/tdfxfb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/tdfxfb.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/tridentfb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/tridentfb.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/vermilion/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/vermilion/Makefile</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/vermilion/cr_pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/vermilion/cr_pll.c</a></td><td class='right'>195</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 2.4%;'/><td class='none' style='width: 97.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/vermilion/vermilion.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/vermilion/vermilion.c</a></td><td class='right'>1175</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 14.2%;'/><td class='none' style='width: 85.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit/linux.git/diff/drivers/video/fbdev/vermilion/vermilion.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/vermilion/vermilion.h</a></td><td class='right'>245</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 3.0%;'/><td class='none' style='width: 97.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/fbdev/via/via_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/fbdev/via/via_i2c.c</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/logo/pnmtologo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/logo/pnmtologo.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/video/sticore.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/video/sticore.c</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/acrn/ioeventfd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/acrn/ioeventfd.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/coco/sev-guest/sev-guest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/coco/sev-guest/sev-guest.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/vboxguest/vboxguest_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/vboxguest/vboxguest_core.c</a></td><td class='right'>154</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.1%;'/><td class='rem' style='width: 0.8%;'/><td class='none' style='width: 98.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/vboxguest/vboxguest_linux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/vboxguest/vboxguest_linux.c</a></td><td class='right'>22</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/vboxguest/vboxguest_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/vboxguest/vboxguest_utils.c</a></td><td class='right'>33</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virt/vmgenid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virt/vmgenid.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/Kconfig</a></td><td class='right'>5</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio.c</a></td><td class='right'>37</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_balloon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_balloon.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_mem.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_pci_admin_legacy_io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_pci_admin_legacy_io.c</a></td><td class='right'>244</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 2.9%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 97.1%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_pci_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_pci_common.c</a></td><td class='right'>48</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.6%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_pci_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_pci_common.h</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_pci_modern.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_pci_modern.c</a></td><td class='right'>259</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 3.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 96.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_pci_modern_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_pci_modern_dev.c</a></td><td class='right'>24</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/virtio/virtio_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/virtio/virtio_ring.c</a></td><td class='right'>6</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/w1/masters/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/masters/Kconfig</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/w1/masters/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/masters/Makefile</a></td><td class='right'>1</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='add'><a href='/cgit/linux.git/diff/drivers/w1/masters/amd_axi_w1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/masters/amd_axi_w1.c</a></td><td class='right'>396</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 4.8%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 95.2%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/w1/masters/ds2490.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/masters/ds2490.c</a></td><td class='right'>25</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/w1/masters/w1-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/masters/w1-gpio.c</a></td><td class='right'>118</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.9%;'/><td class='none' style='width: 98.6%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/w1/slaves/w1_ds2433.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/w1/slaves/w1_ds2433.c</a></td><td class='right'>162</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 1.6%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 98.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/at91sam9_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/at91sam9_wdt.c</a></td><td class='right'>12</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/bcm2835_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/bcm2835_wdt.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/hpwdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/hpwdt.c</a></td><td class='right'>9</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/it87_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/it87_wdt.c</a></td><td class='right'>29</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.7%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/mlx_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/mlx_wdt.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/mtk_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/mtk_wdt.c</a></td><td class='right'>42</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.5%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.5%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/rti_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/rti_wdt.c</a></td><td class='right'>13</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.8%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/s3c2410_wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/s3c2410_wdt.c</a></td><td class='right'>85</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.9%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/starfive-wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/starfive-wdt.c</a></td><td class='right'>8</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/txx9wdt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/txx9wdt.c</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.1%;'/><td class='rem' style='width: 0.1%;'/><td class='none' style='width: 99.9%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/watchdog/watchdog_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/watchdog/watchdog_dev.c</a></td><td class='right'>3</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/xen/events/events_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/xen/events/events_base.c</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/xen/gntdev-dmabuf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/xen/gntdev-dmabuf.c</a></td><td class='right'>50</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.3%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.4%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/xen/privcmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/xen/privcmd.c</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 0.0%;'/><td class='none' style='width: 100.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit/linux.git/diff/drivers/xen/xenbus/xenbus_client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/xen/xenbus/xenbus_client.c</a></td><td class='right'>59</td><td class='graph'><table summary='file diffstat' width='100%'><tr><td class='add' style='width: 0.4%;'/><td class='rem' style='width: 0.3%;'/><td class='none' style='width: 99.3%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>5020 files changed, 284600 insertions, 129193 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/drivers/Makefile b/drivers/Makefile<br/>index d828329c268d..37fd6ce3bd7f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/Makefile</a></div><div class='hunk'>@@ -71,9 +71,8 @@ obj-y				+= gpu/</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_CONNECTOR)		+= connector/</div><div class='ctx'> </div><div class='del'>-# i810fb and intelfb depend on char/agp/</div><div class='add'>+# i810fb depends on char/agp/</div><div class='ctx'> obj-$(CONFIG_FB_I810)           += video/fbdev/i810/</div><div class='del'>-obj-$(CONFIG_FB_INTEL)          += video/fbdev/intelfb/</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_PARPORT)		+= parport/</div><div class='ctx'> obj-y				+= base/ block/ misc/ mfd/ nfc/</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c<br/>index 9711e8fc979d..a73bd4be94b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/device.c</a></div><div class='hunk'>@@ -853,6 +853,9 @@ static int device_early_init(struct hl_device *hdev)</div><div class='ctx'> 		gaudi2_set_asic_funcs(hdev);</div><div class='ctx'> 		strscpy(hdev-&gt;asic_name, "GAUDI2B", sizeof(hdev-&gt;asic_name));</div><div class='ctx'> 		break;</div><div class='add'>+	case ASIC_GAUDI2C:</div><div class='add'>+		gaudi2_set_asic_funcs(hdev);</div><div class='add'>+		strscpy(hdev-&gt;asic_name, "GAUDI2C", sizeof(hdev-&gt;asic_name));</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Unrecognized ASIC type %d\n",</div><div class='hunk'>@@ -1041,18 +1044,21 @@ static bool is_pci_link_healthy(struct hl_device *hdev)</div><div class='ctx'> 	return (vendor_id == PCI_VENDOR_ID_HABANALABS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void hl_device_eq_heartbeat(struct hl_device *hdev)</div><div class='add'>+static int hl_device_eq_heartbeat_check(struct hl_device *hdev)</div><div class='ctx'> {</div><div class='del'>-	u64 event_mask = HL_NOTIFIER_EVENT_DEVICE_RESET | HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE;</div><div class='ctx'> 	struct asic_fixed_properties *prop = &amp;hdev-&gt;asic_prop;</div><div class='ctx'> </div><div class='ctx'> 	if (!prop-&gt;cpucp_info.eq_health_check_supported)</div><div class='del'>-		return;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	if (hdev-&gt;eq_heartbeat_received)</div><div class='add'>+	if (hdev-&gt;eq_heartbeat_received) {</div><div class='ctx'> 		hdev-&gt;eq_heartbeat_received = false;</div><div class='del'>-	else</div><div class='del'>-		hl_device_cond_reset(hdev, HL_DRV_RESET_HARD, event_mask);</div><div class='add'>+	} else {</div><div class='add'>+		dev_err(hdev-&gt;dev, "EQ heartbeat event was not received!\n");</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hl_device_heartbeat(struct work_struct *work)</div><div class='hunk'>@@ -1069,10 +1075,9 @@ static void hl_device_heartbeat(struct work_struct *work)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * For EQ health check need to check if driver received the heartbeat eq event</div><div class='ctx'> 	 * in order to validate the eq is working.</div><div class='add'>+	 * Only if both the EQ is healthy and we managed to send the next heartbeat reschedule.</div><div class='ctx'> 	 */</div><div class='del'>-	hl_device_eq_heartbeat(hdev);</div><div class='del'>-</div><div class='del'>-	if (!hdev-&gt;asic_funcs-&gt;send_heartbeat(hdev))</div><div class='add'>+	if ((!hl_device_eq_heartbeat_check(hdev)) &amp;&amp; (!hdev-&gt;asic_funcs-&gt;send_heartbeat(hdev)))</div><div class='ctx'> 		goto reschedule;</div><div class='ctx'> </div><div class='ctx'> 	if (hl_device_operational(hdev, NULL))</div><div class='hunk'>@@ -2035,7 +2040,7 @@ device_reset:</div><div class='ctx'> 	if (ctx)</div><div class='ctx'> 		hl_ctx_put(ctx);</div><div class='ctx'> </div><div class='del'>-	return hl_device_reset(hdev, flags);</div><div class='add'>+	return hl_device_reset(hdev, flags | HL_DRV_RESET_HARD);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64 event_mask)</div><div class='hunk'>@@ -2044,7 +2049,7 @@ static void hl_notifier_event_send(struct hl_notifier_event *notifier_event, u64</div><div class='ctx'> 	notifier_event-&gt;events_mask |= event_mask;</div><div class='ctx'> </div><div class='ctx'> 	if (notifier_event-&gt;eventfd)</div><div class='del'>-		eventfd_signal(notifier_event-&gt;eventfd, 1);</div><div class='add'>+		eventfd_signal(notifier_event-&gt;eventfd);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;notifier_event-&gt;lock);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/firmware_if.c b/drivers/accel/habanalabs/common/firmware_if.c<br/>index 47e8384134aa..3558a6a8e192 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/firmware_if.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/firmware_if.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/firmware_if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/firmware_if.c</a></div><div class='hunk'>@@ -646,39 +646,27 @@ int hl_fw_send_heartbeat(struct hl_device *hdev)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val,</div><div class='del'>-								u32 sts_val)</div><div class='add'>+static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val, u32 sts_val)</div><div class='ctx'> {</div><div class='ctx'> 	bool err_exists = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!(err_val &amp; CPU_BOOT_ERR0_ENABLED))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_DRAM_INIT_FAIL) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot error - DRAM initialization failed\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_DRAM_INIT_FAIL)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot error - DRAM initialization failed\n");</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_FIT_CORRUPTED) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_FIT_CORRUPTED)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - FIT image corrupted\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_TS_INIT_FAIL) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot error - Thermal Sensor initialization failed\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_TS_INIT_FAIL)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot error - Thermal Sensor initialization failed\n");</div><div class='ctx'> </div><div class='ctx'> 	if (err_val &amp; CPU_BOOT_ERR0_BMC_WAIT_SKIPPED) {</div><div class='ctx'> 		if (hdev-&gt;bmc_enable) {</div><div class='del'>-			dev_err(hdev-&gt;dev,</div><div class='del'>-				"Device boot error - Skipped waiting for BMC\n");</div><div class='del'>-			err_exists = true;</div><div class='add'>+			dev_err(hdev-&gt;dev, "Device boot error - Skipped waiting for BMC\n");</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_info(hdev-&gt;dev,</div><div class='del'>-				"Device boot message - Skipped waiting for BMC\n");</div><div class='add'>+			dev_info(hdev-&gt;dev, "Device boot message - Skipped waiting for BMC\n");</div><div class='ctx'> 			/* This is an info so we don't want it to disable the</div><div class='ctx'> 			 * device</div><div class='ctx'> 			 */</div><div class='hunk'>@@ -686,48 +674,29 @@ static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_NIC_DATA_NOT_RDY) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot error - Serdes data from BMC not available\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_NIC_DATA_NOT_RDY)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot error - Serdes data from BMC not available\n");</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_NIC_FW_FAIL) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot error - NIC F/W initialization failed\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_NIC_FW_FAIL)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot error - NIC F/W initialization failed\n");</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_SECURITY_NOT_RDY) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot warning - security not ready\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_SECURITY_NOT_RDY)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot warning - security not ready\n");</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_SECURITY_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_SECURITY_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - security failure\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_EFUSE_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_EFUSE_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - eFuse failure\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_SEC_IMG_VER_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_SEC_IMG_VER_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - Failed to load preboot secondary image\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_PLL_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_PLL_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - PLL failure\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - Failed to set threshold for temperature sensor\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (err_val &amp; CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL) {</div><div class='ctx'> 		/* Ignore this bit, don't prevent driver loading */</div><div class='hunk'>@@ -735,52 +704,32 @@ static bool fw_report_boot_dev0(struct hl_device *hdev, u32 err_val,</div><div class='ctx'> 		err_val &amp;= ~CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_BINNING_FAIL) {</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_BINNING_FAIL)</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - binning failure\n");</div><div class='del'>-		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (sts_val &amp; CPU_BOOT_DEV_STS0_ENABLED)</div><div class='ctx'> 		dev_dbg(hdev-&gt;dev, "Device status0 %#x\n", sts_val);</div><div class='ctx'> </div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_DRAM_SKIPPED)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot warning - Skipped DRAM initialization\n");</div><div class='add'>+</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL)</div><div class='add'>+		dev_err(hdev-&gt;dev, "Device boot error - ARC memory scrub failed\n");</div><div class='add'>+</div><div class='add'>+	/* All warnings should go here in order not to reach the unknown error validation */</div><div class='ctx'> 	if (err_val &amp; CPU_BOOT_ERR0_EEPROM_FAIL) {</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Device boot error - EEPROM failure detected\n");</div><div class='ctx'> 		err_exists = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* All warnings should go here in order not to reach the unknown error validation */</div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_DRAM_SKIPPED) {</div><div class='del'>-		dev_warn(hdev-&gt;dev,</div><div class='del'>-			"Device boot warning - Skipped DRAM initialization\n");</div><div class='del'>-		/* This is a warning so we don't want it to disable the</div><div class='del'>-		 * device</div><div class='del'>-		 */</div><div class='del'>-		err_val &amp;= ~CPU_BOOT_ERR0_DRAM_SKIPPED;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_PRI_IMG_VER_FAIL)</div><div class='add'>+		dev_warn(hdev-&gt;dev, "Device boot warning - Failed to load preboot primary image\n");</div><div class='ctx'> </div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_PRI_IMG_VER_FAIL) {</div><div class='del'>-		dev_warn(hdev-&gt;dev,</div><div class='del'>-			"Device boot warning - Failed to load preboot primary image\n");</div><div class='del'>-		/* This is a warning so we don't want it to disable the</div><div class='del'>-		 * device as we have a secondary preboot image</div><div class='del'>-		 */</div><div class='del'>-		err_val &amp;= ~CPU_BOOT_ERR0_PRI_IMG_VER_FAIL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (err_val &amp; CPU_BOOT_ERR0_TPM_FAIL) {</div><div class='del'>-		dev_warn(hdev-&gt;dev,</div><div class='del'>-			"Device boot warning - TPM failure\n");</div><div class='del'>-		/* This is a warning so we don't want it to disable the</div><div class='del'>-		 * device</div><div class='del'>-		 */</div><div class='del'>-		err_val &amp;= ~CPU_BOOT_ERR0_TPM_FAIL;</div><div class='del'>-	}</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR0_TPM_FAIL)</div><div class='add'>+		dev_warn(hdev-&gt;dev, "Device boot warning - TPM failure\n");</div><div class='ctx'> </div><div class='del'>-	if (!err_exists &amp;&amp; (err_val &amp; ~CPU_BOOT_ERR0_ENABLED)) {</div><div class='del'>-		dev_err(hdev-&gt;dev,</div><div class='del'>-			"Device boot error - unknown ERR0 error 0x%08x\n", err_val);</div><div class='add'>+	if (err_val &amp; CPU_BOOT_ERR_FATAL_MASK)</div><div class='ctx'> 		err_exists = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* return error only if it's in the predefined mask */</div><div class='ctx'> 	if (err_exists &amp;&amp; ((err_val &amp; ~CPU_BOOT_ERR0_ENABLED) &amp;</div><div class='hunk'>@@ -3295,6 +3244,14 @@ int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_in</div><div class='ctx'> 					HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int hl_fw_get_dev_info_signed(struct hl_device *hdev,</div><div class='add'>+			      struct cpucp_dev_info_signed *dev_info_signed, u32 nonce)</div><div class='add'>+{</div><div class='add'>+	return hl_fw_get_sec_attest_data(hdev, CPUCP_PACKET_INFO_SIGNED_GET, dev_info_signed,</div><div class='add'>+					 sizeof(struct cpucp_dev_info_signed), nonce,</div><div class='add'>+					 HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode,</div><div class='ctx'> 						dma_addr_t buff, u32 *size)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h<br/>index 1655c101c705..2a900c9941fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/habanalabs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/habanalabs.h</a></div><div class='hunk'>@@ -1262,6 +1262,7 @@ struct hl_dec {</div><div class='ctx'>  * @ASIC_GAUDI_SEC: Gaudi secured device (HL-2000).</div><div class='ctx'>  * @ASIC_GAUDI2: Gaudi2 device.</div><div class='ctx'>  * @ASIC_GAUDI2B: Gaudi2B device.</div><div class='add'>+ * @ASIC_GAUDI2C: Gaudi2C device.</div><div class='ctx'>  */</div><div class='ctx'> enum hl_asic_type {</div><div class='ctx'> 	ASIC_INVALID,</div><div class='hunk'>@@ -1270,6 +1271,7 @@ enum hl_asic_type {</div><div class='ctx'> 	ASIC_GAUDI_SEC,</div><div class='ctx'> 	ASIC_GAUDI2,</div><div class='ctx'> 	ASIC_GAUDI2B,</div><div class='add'>+	ASIC_GAUDI2C,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct hl_cs_parser;</div><div class='hunk'>@@ -3519,6 +3521,9 @@ struct hl_device {</div><div class='ctx'> 	u8				heartbeat;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Retrieve PCI device name in case of a PCI device or dev name in simulator */</div><div class='add'>+#define HL_DEV_NAME(hdev)	\</div><div class='add'>+		((hdev)-&gt;pdev ? dev_name(&amp;(hdev)-&gt;pdev-&gt;dev) : "NA-DEVICE")</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct hl_cs_encaps_sig_handle - encapsulated signals handle structure</div><div class='hunk'>@@ -3594,6 +3599,14 @@ static inline bool hl_is_fw_sw_ver_below(struct hl_device *hdev, u32 fw_sw_major</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool hl_is_fw_sw_ver_equal_or_greater(struct hl_device *hdev, u32 fw_sw_major,</div><div class='add'>+							u32 fw_sw_minor)</div><div class='add'>+{</div><div class='add'>+	return (hdev-&gt;fw_sw_major_ver &gt; fw_sw_major ||</div><div class='add'>+			(hdev-&gt;fw_sw_major_ver == fw_sw_major &amp;&amp;</div><div class='add'>+					hdev-&gt;fw_sw_minor_ver &gt;= fw_sw_minor));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Kernel module functions that can be accessed by entire module</div><div class='ctx'>  */</div><div class='hunk'>@@ -3954,6 +3967,8 @@ long hl_fw_get_max_power(struct hl_device *hdev);</div><div class='ctx'> void hl_fw_set_max_power(struct hl_device *hdev);</div><div class='ctx'> int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_info *sec_attest_info,</div><div class='ctx'> 				u32 nonce);</div><div class='add'>+int hl_fw_get_dev_info_signed(struct hl_device *hdev,</div><div class='add'>+			      struct cpucp_dev_info_signed *dev_info_signed, u32 nonce);</div><div class='ctx'> int hl_set_voltage(struct hl_device *hdev, int sensor_index, u32 attr, long value);</div><div class='ctx'> int hl_set_current(struct hl_device *hdev, int sensor_index, u32 attr, long value);</div><div class='ctx'> int hl_set_power(struct hl_device *hdev, int sensor_index, u32 attr, long value);</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c<br/>index 306a5bc9bf89..e542fd40e16c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/habanalabs_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/habanalabs_drv.c</a></div><div class='hunk'>@@ -141,6 +141,9 @@ static enum hl_asic_type get_asic_type(struct hl_device *hdev)</div><div class='ctx'> 		case REV_ID_B:</div><div class='ctx'> 			asic_type = ASIC_GAUDI2B;</div><div class='ctx'> 			break;</div><div class='add'>+		case REV_ID_C:</div><div class='add'>+			asic_type = ASIC_GAUDI2C;</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -670,6 +673,38 @@ static pci_ers_result_t hl_pci_err_slot_reset(struct pci_dev *pdev)</div><div class='ctx'> 	return PCI_ERS_RESULT_RECOVERED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void hl_pci_reset_prepare(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct hl_device *hdev;</div><div class='add'>+</div><div class='add'>+	hdev = pci_get_drvdata(pdev);</div><div class='add'>+	if (!hdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	hdev-&gt;disabled = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hl_pci_reset_done(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct hl_device *hdev;</div><div class='add'>+	u32 flags;</div><div class='add'>+</div><div class='add'>+	hdev = pci_get_drvdata(pdev);</div><div class='add'>+	if (!hdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Schedule a thread to trigger hard reset.</div><div class='add'>+	 * The reason for this handler, is for rare cases where the driver is up</div><div class='add'>+	 * and FLR occurs. This is valid only when working with no VM, so FW handles FLR</div><div class='add'>+	 * and resets the device. FW will go back preboot stage, so driver needs to perform</div><div class='add'>+	 * hard reset in order to load FW fit again.</div><div class='add'>+	 */</div><div class='add'>+	flags = HL_DRV_RESET_HARD | HL_DRV_RESET_BYPASS_REQ_TO_FW;</div><div class='add'>+</div><div class='add'>+	hl_device_reset(hdev, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dev_pm_ops hl_pm_ops = {</div><div class='ctx'> 	.suspend = hl_pmops_suspend,</div><div class='ctx'> 	.resume = hl_pmops_resume,</div><div class='hunk'>@@ -679,6 +714,8 @@ static const struct pci_error_handlers hl_pci_err_handler = {</div><div class='ctx'> 	.error_detected = hl_pci_err_detected,</div><div class='ctx'> 	.slot_reset = hl_pci_err_slot_reset,</div><div class='ctx'> 	.resume = hl_pci_err_resume,</div><div class='add'>+	.reset_prepare = hl_pci_reset_prepare,</div><div class='add'>+	.reset_done = hl_pci_reset_done,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct pci_driver hl_pci_driver = {</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c<br/>index 8ef36effb95b..1dd6e23172ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs_ioctl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/habanalabs_ioctl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/habanalabs_ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/habanalabs_ioctl.c</a></div><div class='hunk'>@@ -19,6 +19,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/msr.h&gt;</div><div class='ctx'> </div><div class='add'>+/* make sure there is space for all the signed info */</div><div class='add'>+static_assert(sizeof(struct cpucp_info) &lt;= SEC_DEV_INFO_BUF_SZ);</div><div class='add'>+</div><div class='ctx'> static u32 hl_debug_struct_size[HL_DEBUG_OP_TIMESTAMP + 1] = {</div><div class='ctx'> 	[HL_DEBUG_OP_ETR] = sizeof(struct hl_debug_params_etr),</div><div class='ctx'> 	[HL_DEBUG_OP_ETF] = sizeof(struct hl_debug_params_etf),</div><div class='hunk'>@@ -685,7 +688,7 @@ static int sec_attest_info(struct hl_fpriv *hpriv, struct hl_info_args *args)</div><div class='ctx'> 	if (!sec_attest_info)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	info = kmalloc(sizeof(*info), GFP_KERNEL);</div><div class='add'>+	info = kzalloc(sizeof(*info), GFP_KERNEL);</div><div class='ctx'> 	if (!info) {</div><div class='ctx'> 		rc = -ENOMEM;</div><div class='ctx'> 		goto free_sec_attest_info;</div><div class='hunk'>@@ -719,6 +722,53 @@ free_sec_attest_info:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dev_info_signed(struct hl_fpriv *hpriv, struct hl_info_args *args)</div><div class='add'>+{</div><div class='add'>+	void __user *out = (void __user *) (uintptr_t) args-&gt;return_pointer;</div><div class='add'>+	struct cpucp_dev_info_signed *dev_info_signed;</div><div class='add'>+	struct hl_info_signed *info;</div><div class='add'>+	u32 max_size = args-&gt;return_size;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if ((!max_size) || (!out))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dev_info_signed = kzalloc(sizeof(*dev_info_signed), GFP_KERNEL);</div><div class='add'>+	if (!dev_info_signed)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	info = kzalloc(sizeof(*info), GFP_KERNEL);</div><div class='add'>+	if (!info) {</div><div class='add'>+		rc = -ENOMEM;</div><div class='add'>+		goto free_dev_info_signed;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = hl_fw_get_dev_info_signed(hpriv-&gt;hdev,</div><div class='add'>+					dev_info_signed, args-&gt;sec_attest_nonce);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto free_info;</div><div class='add'>+</div><div class='add'>+	info-&gt;nonce = le32_to_cpu(dev_info_signed-&gt;nonce);</div><div class='add'>+	info-&gt;info_sig_len = dev_info_signed-&gt;info_sig_len;</div><div class='add'>+	info-&gt;pub_data_len = le16_to_cpu(dev_info_signed-&gt;pub_data_len);</div><div class='add'>+	info-&gt;certificate_len = le16_to_cpu(dev_info_signed-&gt;certificate_len);</div><div class='add'>+	info-&gt;dev_info_len = sizeof(struct cpucp_info);</div><div class='add'>+	memcpy(&amp;info-&gt;info_sig, &amp;dev_info_signed-&gt;info_sig, sizeof(info-&gt;info_sig));</div><div class='add'>+	memcpy(&amp;info-&gt;public_data, &amp;dev_info_signed-&gt;public_data, sizeof(info-&gt;public_data));</div><div class='add'>+	memcpy(&amp;info-&gt;certificate, &amp;dev_info_signed-&gt;certificate, sizeof(info-&gt;certificate));</div><div class='add'>+	memcpy(&amp;info-&gt;dev_info, &amp;dev_info_signed-&gt;info, info-&gt;dev_info_len);</div><div class='add'>+</div><div class='add'>+	rc = copy_to_user(out, info, min_t(size_t, max_size, sizeof(*info))) ? -EFAULT : 0;</div><div class='add'>+</div><div class='add'>+free_info:</div><div class='add'>+	kfree(info);</div><div class='add'>+free_dev_info_signed:</div><div class='add'>+	kfree(dev_info_signed);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> static int eventfd_register(struct hl_fpriv *hpriv, struct hl_info_args *args)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='hunk'>@@ -1089,6 +1139,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,</div><div class='ctx'> 	case HL_INFO_FW_GENERIC_REQ:</div><div class='ctx'> 		return send_fw_generic_request(hdev, args);</div><div class='ctx'> </div><div class='add'>+	case HL_INFO_DEV_SIGNED:</div><div class='add'>+		return dev_info_signed(hpriv, args);</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(dev, "Invalid request %d\n", args-&gt;op);</div><div class='ctx'> 		rc = -EINVAL;</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/hwmon.c b/drivers/accel/habanalabs/common/hwmon.c<br/>index 8598056216e7..1ee2ee07e9ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/hwmon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/hwmon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/hwmon.c</a></div><div class='hunk'>@@ -578,10 +578,6 @@ int hl_get_temperature(struct hl_device *hdev,</div><div class='ctx'> 				CPUCP_PKT_CTL_OPCODE_SHIFT);</div><div class='ctx'> 	pkt.sensor_index = __cpu_to_le16(sensor_index);</div><div class='ctx'> 	pkt.type = __cpu_to_le16(attr);</div><div class='del'>-</div><div class='del'>-	dev_dbg(hdev-&gt;dev, "get temp, ctl 0x%x, sensor %d, type %d\n",</div><div class='del'>-		pkt.ctl, pkt.sensor_index, pkt.type);</div><div class='del'>-</div><div class='ctx'> 	rc = hdev-&gt;asic_funcs-&gt;send_cpu_message(hdev, (u32 *) &amp;pkt, sizeof(pkt),</div><div class='ctx'> 						0, &amp;result);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/accel/habanalabs/common/memory.c b/drivers/accel/habanalabs/common/memory.c<br/>index 0b8689fe0b64..3348ad12c237 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/memory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/memory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/memory.c</a></div><div class='hunk'>@@ -955,8 +955,8 @@ static int map_phys_pg_pack(struct hl_ctx *ctx, u64 vaddr,</div><div class='ctx'> 				(i + 1) == phys_pg_pack-&gt;npages);</div><div class='ctx'> 		if (rc) {</div><div class='ctx'> 			dev_err(hdev-&gt;dev,</div><div class='del'>-				"map failed for handle %u, npages: %llu, mapped: %llu",</div><div class='del'>-				phys_pg_pack-&gt;handle, phys_pg_pack-&gt;npages,</div><div class='add'>+				"map failed (%d) for handle %u, npages: %llu, mapped: %llu\n",</div><div class='add'>+				rc, phys_pg_pack-&gt;handle, phys_pg_pack-&gt;npages,</div><div class='ctx'> 				mapped_pg_cnt);</div><div class='ctx'> 			goto err;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1186,7 +1186,8 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device</div><div class='ctx'> </div><div class='ctx'> 	rc = map_phys_pg_pack(ctx, ret_vaddr, phys_pg_pack);</div><div class='ctx'> 	if (rc) {</div><div class='del'>-		dev_err(hdev-&gt;dev, "mapping page pack failed for handle %u\n", handle);</div><div class='add'>+		dev_err(hdev-&gt;dev, "mapping page pack failed (%d) for handle %u\n",</div><div class='add'>+			rc, handle);</div><div class='ctx'> 		mutex_unlock(&amp;hdev-&gt;mmu_lock);</div><div class='ctx'> 		goto map_err;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/mmu/mmu.c b/drivers/accel/habanalabs/common/mmu/mmu.c<br/>index b2145716c605..b654302a68fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/mmu/mmu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/mmu/mmu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/mmu/mmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/mmu/mmu.c</a></div><div class='hunk'>@@ -596,6 +596,7 @@ int hl_mmu_if_set_funcs(struct hl_device *hdev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ASIC_GAUDI2:</div><div class='ctx'> 	case ASIC_GAUDI2B:</div><div class='add'>+	case ASIC_GAUDI2C:</div><div class='ctx'> 		/* MMUs in Gaudi2 are always host resident */</div><div class='ctx'> 		hl_mmu_v2_hr_set_funcs(hdev, &amp;hdev-&gt;mmu_func[MMU_HR_PGT]);</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/accel/habanalabs/common/sysfs.c b/drivers/accel/habanalabs/common/sysfs.c<br/>index 01f89f029355..8a9f98832157 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/common/sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/common/sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/common/sysfs.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include "habanalabs.h"</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='ctx'> static ssize_t clk_max_freq_mhz_show(struct device *dev, struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='hunk'>@@ -80,12 +81,27 @@ static ssize_t vrm_ver_show(struct device *dev, struct device_attribute *attr, c</div><div class='ctx'> {</div><div class='ctx'> 	struct hl_device *hdev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct cpucp_info *cpucp_info;</div><div class='add'>+	u32 infineon_second_stage_version;</div><div class='add'>+	u32 infineon_second_stage_first_instance;</div><div class='add'>+	u32 infineon_second_stage_second_instance;</div><div class='add'>+	u32 infineon_second_stage_third_instance;</div><div class='add'>+	u32 mask = 0xff;</div><div class='ctx'> </div><div class='ctx'> 	cpucp_info = &amp;hdev-&gt;asic_prop.cpucp_info;</div><div class='ctx'> </div><div class='add'>+	infineon_second_stage_version = le32_to_cpu(cpucp_info-&gt;infineon_second_stage_version);</div><div class='add'>+	infineon_second_stage_first_instance = infineon_second_stage_version &amp; mask;</div><div class='add'>+	infineon_second_stage_second_instance =</div><div class='add'>+					(infineon_second_stage_version &gt;&gt; 8) &amp; mask;</div><div class='add'>+	infineon_second_stage_third_instance =</div><div class='add'>+					(infineon_second_stage_version &gt;&gt; 16) &amp; mask;</div><div class='add'>+</div><div class='ctx'> 	if (cpucp_info-&gt;infineon_second_stage_version)</div><div class='del'>-		return sprintf(buf, "%#04x %#04x\n", le32_to_cpu(cpucp_info-&gt;infineon_version),</div><div class='del'>-				le32_to_cpu(cpucp_info-&gt;infineon_second_stage_version));</div><div class='add'>+		return sprintf(buf, "%#04x %#04x:%#04x:%#04x\n",</div><div class='add'>+				le32_to_cpu(cpucp_info-&gt;infineon_version),</div><div class='add'>+				infineon_second_stage_first_instance,</div><div class='add'>+				infineon_second_stage_second_instance,</div><div class='add'>+				infineon_second_stage_third_instance);</div><div class='ctx'> 	else</div><div class='ctx'> 		return sprintf(buf, "%#04x\n", le32_to_cpu(cpucp_info-&gt;infineon_version));</div><div class='ctx'> }</div><div class='hunk'>@@ -251,6 +267,9 @@ static ssize_t device_type_show(struct device *dev,</div><div class='ctx'> 	case ASIC_GAUDI2B:</div><div class='ctx'> 		str = "GAUDI2B";</div><div class='ctx'> 		break;</div><div class='add'>+	case ASIC_GAUDI2C:</div><div class='add'>+		str = "GAUDI2C";</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(hdev-&gt;dev, "Unrecognized ASIC type %d\n",</div><div class='ctx'> 				hdev-&gt;asic_type);</div><div class='hunk'>@@ -383,6 +402,21 @@ static ssize_t security_enabled_show(struct device *dev,</div><div class='ctx'> 	return sprintf(buf, "%d\n", hdev-&gt;asic_prop.fw_security_enabled);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t module_id_show(struct device *dev,</div><div class='add'>+				struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct hl_device *hdev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", le32_to_cpu(hdev-&gt;asic_prop.cpucp_info.card_location));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t parent_device_show(struct device *dev, struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct hl_device *hdev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%s\n", HL_DEV_NAME(hdev));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static DEVICE_ATTR_RO(armcp_kernel_ver);</div><div class='ctx'> static DEVICE_ATTR_RO(armcp_ver);</div><div class='ctx'> static DEVICE_ATTR_RO(cpld_ver);</div><div class='hunk'>@@ -402,6 +436,8 @@ static DEVICE_ATTR_RO(thermal_ver);</div><div class='ctx'> static DEVICE_ATTR_RO(uboot_ver);</div><div class='ctx'> static DEVICE_ATTR_RO(fw_os_ver);</div><div class='ctx'> static DEVICE_ATTR_RO(security_enabled);</div><div class='add'>+static DEVICE_ATTR_RO(module_id);</div><div class='add'>+static DEVICE_ATTR_RO(parent_device);</div><div class='ctx'> </div><div class='ctx'> static struct bin_attribute bin_attr_eeprom = {</div><div class='ctx'> 	.attr = {.name = "eeprom", .mode = (0444)},</div><div class='hunk'>@@ -427,6 +463,8 @@ static struct attribute *hl_dev_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_uboot_ver.attr,</div><div class='ctx'> 	&amp;dev_attr_fw_os_ver.attr,</div><div class='ctx'> 	&amp;dev_attr_security_enabled.attr,</div><div class='add'>+	&amp;dev_attr_module_id.attr,</div><div class='add'>+	&amp;dev_attr_parent_device.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c<br/>index 819660c684cf..e0e5615ef9b0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/gaudi2/gaudi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/gaudi2/gaudi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/gaudi2/gaudi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/gaudi2/gaudi2.c</a></div><div class='hunk'>@@ -7858,39 +7858,44 @@ static bool gaudi2_handle_ecc_event(struct hl_device *hdev, u16 event_type,</div><div class='ctx'> 	return !!ecc_data-&gt;is_critical;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void handle_lower_qman_data_on_err(struct hl_device *hdev, u64 qman_base, u64 event_mask)</div><div class='add'>+static void handle_lower_qman_data_on_err(struct hl_device *hdev, u64 qman_base, u32 engine_id)</div><div class='ctx'> {</div><div class='del'>-	u32 lo, hi, cq_ptr_size, arc_cq_ptr_size;</div><div class='del'>-	u64 cq_ptr, arc_cq_ptr, cp_current_inst;</div><div class='add'>+	struct undefined_opcode_info *undef_opcode = &amp;hdev-&gt;captured_err_info.undef_opcode;</div><div class='add'>+	u64 cq_ptr, cp_current_inst;</div><div class='add'>+	u32 lo, hi, cq_size, cp_sts;</div><div class='add'>+	bool is_arc_cq;</div><div class='ctx'> </div><div class='del'>-	lo = RREG32(qman_base + QM_CQ_PTR_LO_4_OFFSET);</div><div class='del'>-	hi = RREG32(qman_base + QM_CQ_PTR_HI_4_OFFSET);</div><div class='del'>-	cq_ptr = ((u64) hi) &lt;&lt; 32 | lo;</div><div class='del'>-	cq_ptr_size = RREG32(qman_base + QM_CQ_TSIZE_4_OFFSET);</div><div class='add'>+	cp_sts = RREG32(qman_base + QM_CP_STS_4_OFFSET);</div><div class='add'>+	is_arc_cq = FIELD_GET(PDMA0_QM_CP_STS_CUR_CQ_MASK, cp_sts); /* 0 - legacy CQ, 1 - ARC_CQ */</div><div class='ctx'> </div><div class='del'>-	lo = RREG32(qman_base + QM_ARC_CQ_PTR_LO_OFFSET);</div><div class='del'>-	hi = RREG32(qman_base + QM_ARC_CQ_PTR_HI_OFFSET);</div><div class='del'>-	arc_cq_ptr = ((u64) hi) &lt;&lt; 32 | lo;</div><div class='del'>-	arc_cq_ptr_size = RREG32(qman_base + QM_ARC_CQ_TSIZE_OFFSET);</div><div class='add'>+	if (is_arc_cq) {</div><div class='add'>+		lo = RREG32(qman_base + QM_ARC_CQ_PTR_LO_STS_OFFSET);</div><div class='add'>+		hi = RREG32(qman_base + QM_ARC_CQ_PTR_HI_STS_OFFSET);</div><div class='add'>+		cq_ptr = ((u64) hi) &lt;&lt; 32 | lo;</div><div class='add'>+		cq_size = RREG32(qman_base + QM_ARC_CQ_TSIZE_STS_OFFSET);</div><div class='add'>+	} else {</div><div class='add'>+		lo = RREG32(qman_base + QM_CQ_PTR_LO_STS_4_OFFSET);</div><div class='add'>+		hi = RREG32(qman_base + QM_CQ_PTR_HI_STS_4_OFFSET);</div><div class='add'>+		cq_ptr = ((u64) hi) &lt;&lt; 32 | lo;</div><div class='add'>+		cq_size = RREG32(qman_base + QM_CQ_TSIZE_STS_4_OFFSET);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	lo = RREG32(qman_base + QM_CP_CURRENT_INST_LO_4_OFFSET);</div><div class='ctx'> 	hi = RREG32(qman_base + QM_CP_CURRENT_INST_HI_4_OFFSET);</div><div class='ctx'> 	cp_current_inst = ((u64) hi) &lt;&lt; 32 | lo;</div><div class='ctx'> </div><div class='ctx'> 	dev_info(hdev-&gt;dev,</div><div class='del'>-		"LowerQM. CQ: {ptr %#llx, size %u}, ARC_CQ: {ptr %#llx, size %u}, CP: {instruction %#llx}\n",</div><div class='del'>-		cq_ptr, cq_ptr_size, arc_cq_ptr, arc_cq_ptr_size, cp_current_inst);</div><div class='add'>+		"LowerQM. %sCQ: {ptr %#llx, size %u}, CP: {instruction %#018llx}\n",</div><div class='add'>+		is_arc_cq ? "ARC_" : "", cq_ptr, cq_size, cp_current_inst);</div><div class='ctx'> </div><div class='del'>-	if (event_mask &amp; HL_NOTIFIER_EVENT_UNDEFINED_OPCODE) {</div><div class='del'>-		if (arc_cq_ptr) {</div><div class='del'>-			hdev-&gt;captured_err_info.undef_opcode.cq_addr = arc_cq_ptr;</div><div class='del'>-			hdev-&gt;captured_err_info.undef_opcode.cq_size = arc_cq_ptr_size;</div><div class='del'>-		} else {</div><div class='del'>-			hdev-&gt;captured_err_info.undef_opcode.cq_addr = cq_ptr;</div><div class='del'>-			hdev-&gt;captured_err_info.undef_opcode.cq_size = cq_ptr_size;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		hdev-&gt;captured_err_info.undef_opcode.stream_id = QMAN_STREAMS;</div><div class='add'>+	if (undef_opcode-&gt;write_enable) {</div><div class='add'>+		memset(undef_opcode, 0, sizeof(*undef_opcode));</div><div class='add'>+		undef_opcode-&gt;timestamp = ktime_get();</div><div class='add'>+		undef_opcode-&gt;cq_addr = cq_ptr;</div><div class='add'>+		undef_opcode-&gt;cq_size = cq_size;</div><div class='add'>+		undef_opcode-&gt;engine_id = engine_id;</div><div class='add'>+		undef_opcode-&gt;stream_id = QMAN_STREAMS;</div><div class='add'>+		undef_opcode-&gt;write_enable = 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -7929,21 +7934,12 @@ static int gaudi2_handle_qman_err_generic(struct hl_device *hdev, u16 event_type</div><div class='ctx'> 				error_count++;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-		if (i == QMAN_STREAMS &amp;&amp; error_count) {</div><div class='del'>-			/* check for undefined opcode */</div><div class='del'>-			if (glbl_sts_val &amp; PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK &amp;&amp;</div><div class='del'>-					hdev-&gt;captured_err_info.undef_opcode.write_enable) {</div><div class='del'>-				memset(&amp;hdev-&gt;captured_err_info.undef_opcode, 0,</div><div class='del'>-						sizeof(hdev-&gt;captured_err_info.undef_opcode));</div><div class='del'>-</div><div class='del'>-				hdev-&gt;captured_err_info.undef_opcode.write_enable = false;</div><div class='del'>-				hdev-&gt;captured_err_info.undef_opcode.timestamp = ktime_get();</div><div class='del'>-				hdev-&gt;captured_err_info.undef_opcode.engine_id =</div><div class='del'>-							gaudi2_queue_id_to_engine_id[qid_base];</div><div class='del'>-				*event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			handle_lower_qman_data_on_err(hdev, qman_base, *event_mask);</div><div class='add'>+		/* Check for undefined opcode error in lower QM */</div><div class='add'>+		if ((i == QMAN_STREAMS) &amp;&amp;</div><div class='add'>+				(glbl_sts_val &amp; PDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK)) {</div><div class='add'>+			handle_lower_qman_data_on_err(hdev, qman_base,</div><div class='add'>+							gaudi2_queue_id_to_engine_id[qid_base]);</div><div class='add'>+			*event_mask |= HL_NOTIFIER_EVENT_UNDEFINED_OPCODE;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -10007,6 +10003,8 @@ static void gaudi2_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_ent</div><div class='ctx'> 		error_count = gaudi2_handle_pcie_drain(hdev, &amp;eq_entry-&gt;pcie_drain_ind_data);</div><div class='ctx'> 		reset_flags |= HL_DRV_RESET_FW_FATAL_ERR;</div><div class='ctx'> 		event_mask |= HL_NOTIFIER_EVENT_GENERAL_HW_ERR;</div><div class='add'>+		if (hl_is_fw_sw_ver_equal_or_greater(hdev, 1, 13))</div><div class='add'>+			is_critical = true;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case GAUDI2_EVENT_PSOC59_RPM_ERROR_OR_DRAIN:</div><div class='head'>diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h<br/>index a08378d0802b..d21fcd3880b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h</a></div><div class='hunk'>@@ -242,14 +242,15 @@</div><div class='ctx'> #define QM_FENCE2_OFFSET		(mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE)</div><div class='ctx'> #define QM_SEI_STATUS_OFFSET		(mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE)</div><div class='ctx'> </div><div class='del'>-#define QM_CQ_PTR_LO_4_OFFSET		(mmPDMA0_QM_CQ_PTR_LO_4 - mmPDMA0_QM_BASE)</div><div class='del'>-#define QM_CQ_PTR_HI_4_OFFSET		(mmPDMA0_QM_CQ_PTR_HI_4 - mmPDMA0_QM_BASE)</div><div class='del'>-#define QM_CQ_TSIZE_4_OFFSET		(mmPDMA0_QM_CQ_TSIZE_4 - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_CQ_TSIZE_STS_4_OFFSET	(mmPDMA0_QM_CQ_TSIZE_STS_4 - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_CQ_PTR_LO_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_LO_STS_4 - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_CQ_PTR_HI_STS_4_OFFSET	(mmPDMA0_QM_CQ_PTR_HI_STS_4 - mmPDMA0_QM_BASE)</div><div class='ctx'> </div><div class='del'>-#define QM_ARC_CQ_PTR_LO_OFFSET		(mmPDMA0_QM_ARC_CQ_PTR_LO - mmPDMA0_QM_BASE)</div><div class='del'>-#define QM_ARC_CQ_PTR_HI_OFFSET		(mmPDMA0_QM_ARC_CQ_PTR_HI - mmPDMA0_QM_BASE)</div><div class='del'>-#define QM_ARC_CQ_TSIZE_OFFSET		(mmPDMA0_QM_ARC_CQ_TSIZE - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_ARC_CQ_TSIZE_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_TSIZE_STS - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_ARC_CQ_PTR_LO_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_LO_STS - mmPDMA0_QM_BASE)</div><div class='add'>+#define QM_ARC_CQ_PTR_HI_STS_OFFSET	(mmPDMA0_QM_ARC_CQ_PTR_HI_STS - mmPDMA0_QM_BASE)</div><div class='ctx'> </div><div class='add'>+#define QM_CP_STS_4_OFFSET		(mmPDMA0_QM_CP_STS_4 - mmPDMA0_QM_BASE)</div><div class='ctx'> #define QM_CP_CURRENT_INST_LO_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_LO_4 - mmPDMA0_QM_BASE)</div><div class='ctx'> #define QM_CP_CURRENT_INST_HI_4_OFFSET	(mmPDMA0_QM_CP_CURRENT_INST_HI_4 - mmPDMA0_QM_BASE)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h b/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h<br/>index f5d497dc9bdc..4f951cada077 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/habanalabs/include/hw_ip/pci/pci_general.h</a></div><div class='hunk'>@@ -25,6 +25,7 @@ enum hl_revision_id {</div><div class='ctx'> 	REV_ID_INVALID				= 0x00,</div><div class='ctx'> 	REV_ID_A				= 0x01,</div><div class='ctx'> 	REV_ID_B				= 0x02,</div><div class='add'>+	REV_ID_C				= 0x03</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif /* INCLUDE_PCI_GENERAL_H_ */</div><div class='head'>diff --git a/drivers/accel/ivpu/ivpu_hw_37xx.c b/drivers/accel/ivpu/ivpu_hw_37xx.c<br/>index e33dfe3089af..574cdeefb66b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/ivpu/ivpu_hw_37xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/ivpu/ivpu_hw_37xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/ivpu/ivpu_hw_37xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/ivpu/ivpu_hw_37xx.c</a></div><div class='hunk'>@@ -54,10 +54,12 @@</div><div class='ctx'> </div><div class='ctx'> #define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) &lt;&lt; 32) | ICB_0_IRQ_MASK)</div><div class='ctx'> </div><div class='del'>-#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)) | \</div><div class='del'>-			   (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \</div><div class='add'>+#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \</div><div class='ctx'> 			   (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, UFI_ERR)))</div><div class='ctx'> </div><div class='add'>+#define BUTTRESS_ALL_IRQ_MASK (BUTTRESS_IRQ_MASK | \</div><div class='add'>+			       (REG_FLD(VPU_37XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)))</div><div class='add'>+</div><div class='ctx'> #define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)</div><div class='ctx'> #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)</div><div class='ctx'> </div><div class='hunk'>@@ -75,8 +77,12 @@ static void ivpu_hw_wa_init(struct ivpu_device *vdev)</div><div class='ctx'> 	vdev-&gt;wa.clear_runtime_mem = false;</div><div class='ctx'> 	vdev-&gt;wa.d3hot_after_power_off = true;</div><div class='ctx'> </div><div class='del'>-	if (ivpu_device_id(vdev) == PCI_DEVICE_ID_MTL &amp;&amp; ivpu_revision(vdev) &lt; 4)</div><div class='add'>+	REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, BUTTRESS_ALL_IRQ_MASK);</div><div class='add'>+	if (REGB_RD32(VPU_37XX_BUTTRESS_INTERRUPT_STAT) == BUTTRESS_ALL_IRQ_MASK) {</div><div class='add'>+		/* Writing 1s does not clear the interrupt status register */</div><div class='ctx'> 		vdev-&gt;wa.interrupt_clear_with_0 = true;</div><div class='add'>+		REGB_WR32(VPU_37XX_BUTTRESS_INTERRUPT_STAT, 0x0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	IVPU_PRINT_WA(punit_disabled);</div><div class='ctx'> 	IVPU_PRINT_WA(clear_runtime_mem);</div><div class='head'>diff --git a/drivers/accel/qaic/mhi_controller.c b/drivers/accel/qaic/mhi_controller.c<br/>index 364eede0ac02..51cb85d0387b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/qaic/mhi_controller.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/qaic/mhi_controller.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/qaic/mhi_controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/qaic/mhi_controller.c</a></div><div class='hunk'>@@ -436,8 +436,21 @@ static struct mhi_controller_config aic100_config = {</div><div class='ctx'> </div><div class='ctx'> static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out)</div><div class='ctx'> {</div><div class='del'>-	u32 tmp = readl_relaxed(addr);</div><div class='add'>+	u32 tmp;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * SOC_HW_VERSION quirk</div><div class='add'>+	 * The SOC_HW_VERSION register (offset 0x224) is not reliable and</div><div class='add'>+	 * may contain uninitialized values, including 0xFFFFFFFF. This could</div><div class='add'>+	 * cause a false positive link down error.  Instead, intercept any</div><div class='add'>+	 * reads and provide the correct value of the register.</div><div class='add'>+	 */</div><div class='add'>+	if (addr - mhi_cntrl-&gt;regs == 0x224) {</div><div class='add'>+		*out = 0x60110200;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tmp = readl_relaxed(addr);</div><div class='ctx'> 	if (tmp == U32_MAX)</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/accel/qaic/qaic_data.c b/drivers/accel/qaic/qaic_data.c<br/>index f88d925c8001..2459fe4a3f95 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/accel/qaic/qaic_data.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/accel/qaic/qaic_data.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/accel/qaic/qaic_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/accel/qaic/qaic_data.c</a></div><div class='hunk'>@@ -457,7 +457,7 @@ static int create_sgt(struct qaic_device *qdev, struct sg_table **sgt_out, u64 s</div><div class='ctx'> 		 * later</div><div class='ctx'> 		 */</div><div class='ctx'> 		buf_extra = (PAGE_SIZE - size % PAGE_SIZE) % PAGE_SIZE;</div><div class='del'>-		max_order = min(MAX_ORDER, get_order(size));</div><div class='add'>+		max_order = min(MAX_PAGE_ORDER, get_order(size));</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* allocate a single page for book keeping */</div><div class='ctx'> 		nr_pages = 1;</div><div class='hunk'>@@ -787,7 +787,6 @@ struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_</div><div class='ctx'> 	struct dma_buf_attachment *attach;</div><div class='ctx'> 	struct drm_gem_object *obj;</div><div class='ctx'> 	struct qaic_bo *bo;</div><div class='del'>-	size_t size;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	bo = qaic_alloc_init_bo();</div><div class='hunk'>@@ -805,13 +804,12 @@ struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_</div><div class='ctx'> 		goto attach_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	size = PAGE_ALIGN(attach-&gt;dmabuf-&gt;size);</div><div class='del'>-	if (size == 0) {</div><div class='add'>+	if (!attach-&gt;dmabuf-&gt;size) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto size_align_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_gem_private_object_init(dev, obj, size);</div><div class='add'>+	drm_gem_private_object_init(dev, obj, attach-&gt;dmabuf-&gt;size);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * skipping dma_buf_map_attachment() as we do not know the direction</div><div class='ctx'> 	 * just yet. Once the direction is known in the subsequent IOCTL to</div><div class='head'>diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig<br/>index f819e760ff19..3c3f8037ebed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/Kconfig</a></div><div class='hunk'>@@ -61,6 +61,10 @@ config ACPI_CCA_REQUIRED</div><div class='ctx'> config ACPI_TABLE_LIB</div><div class='ctx'> 	bool</div><div class='ctx'> </div><div class='add'>+config ACPI_THERMAL_LIB</div><div class='add'>+       depends on THERMAL</div><div class='add'>+       bool</div><div class='add'>+</div><div class='ctx'> config ACPI_DEBUGGER</div><div class='ctx'> 	bool "AML debugger interface"</div><div class='ctx'> 	select ACPI_DEBUG</div><div class='hunk'>@@ -310,7 +314,6 @@ config ACPI_HOTPLUG_CPU</div><div class='ctx'> 	bool</div><div class='ctx'> 	depends on ACPI_PROCESSOR &amp;&amp; HOTPLUG_CPU</div><div class='ctx'> 	select ACPI_CONTAINER</div><div class='del'>-	default y</div><div class='ctx'> </div><div class='ctx'> config ACPI_PROCESSOR_AGGREGATOR</div><div class='ctx'> 	tristate "Processor Aggregator"</div><div class='hunk'>@@ -327,6 +330,7 @@ config ACPI_THERMAL</div><div class='ctx'> 	tristate "Thermal Zone"</div><div class='ctx'> 	depends on ACPI_PROCESSOR</div><div class='ctx'> 	select THERMAL</div><div class='add'>+	select ACPI_THERMAL_LIB</div><div class='ctx'> 	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  This driver supports ACPI thermal zones.  Most mobile and</div><div class='head'>diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile<br/>index eaa09bf52f17..12ef8180d272 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/Makefile</a></div><div class='hunk'>@@ -37,7 +37,7 @@ acpi-$(CONFIG_ACPI_SLEEP)	+= proc.o</div><div class='ctx'> # ACPI Bus and Device Drivers</div><div class='ctx'> #</div><div class='ctx'> acpi-y				+= bus.o glue.o</div><div class='del'>-acpi-y				+= scan.o</div><div class='add'>+acpi-y				+= scan.o mipi-disco-img.o</div><div class='ctx'> acpi-y				+= resource.o</div><div class='ctx'> acpi-y				+= acpi_processor.o</div><div class='ctx'> acpi-y				+= processor_core.o</div><div class='hunk'>@@ -89,6 +89,7 @@ obj-$(CONFIG_ACPI_TAD)		+= acpi_tad.o</div><div class='ctx'> obj-$(CONFIG_ACPI_PCI_SLOT)	+= pci_slot.o</div><div class='ctx'> obj-$(CONFIG_ACPI_PROCESSOR)	+= processor.o</div><div class='ctx'> obj-$(CONFIG_ACPI)		+= container.o</div><div class='add'>+obj-$(CONFIG_ACPI_THERMAL_LIB)	+= thermal_lib.o</div><div class='ctx'> obj-$(CONFIG_ACPI_THERMAL)	+= thermal.o</div><div class='ctx'> obj-$(CONFIG_ACPI_PLATFORM_PROFILE) 	+= platform_profile.o</div><div class='ctx'> obj-$(CONFIG_ACPI_NFIT)		+= nfit/</div><div class='head'>diff --git a/drivers/acpi/acpi_extlog.c b/drivers/acpi/acpi_extlog.c<br/>index e120a96e1eae..ca87a0939135 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_extlog.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_extlog.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_extlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_extlog.c</a></div><div class='hunk'>@@ -145,9 +145,14 @@ static int extlog_print(struct notifier_block *nb, unsigned long val,</div><div class='ctx'> 	static u32 err_seq;</div><div class='ctx'> </div><div class='ctx'> 	estatus = extlog_elog_entry_check(cpu, bank);</div><div class='del'>-	if (estatus == NULL || (mce-&gt;kflags &amp; MCE_HANDLED_CEC))</div><div class='add'>+	if (!estatus)</div><div class='ctx'> 		return NOTIFY_DONE;</div><div class='ctx'> </div><div class='add'>+	if (mce-&gt;kflags &amp; MCE_HANDLED_CEC) {</div><div class='add'>+		estatus-&gt;block_status = 0;</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	memcpy(elog_buf, (void *)estatus, ELOG_ENTRY_LEN);</div><div class='ctx'> 	/* clear record status to enable BIOS to update it again */</div><div class='ctx'> 	estatus-&gt;block_status = 0;</div><div class='hunk'>@@ -303,9 +308,10 @@ err:</div><div class='ctx'> static void __exit extlog_exit(void)</div><div class='ctx'> {</div><div class='ctx'> 	mce_unregister_decode_chain(&amp;extlog_mce_dec);</div><div class='del'>-	((struct extlog_l1_head *)extlog_l1_addr)-&gt;flags &amp;= ~FLAG_OS_OPTIN;</div><div class='del'>-	if (extlog_l1_addr)</div><div class='add'>+	if (extlog_l1_addr) {</div><div class='add'>+		((struct extlog_l1_head *)extlog_l1_addr)-&gt;flags &amp;= ~FLAG_OS_OPTIN;</div><div class='ctx'> 		acpi_os_unmap_iomem(extlog_l1_addr, l1_size);</div><div class='add'>+	}</div><div class='ctx'> 	if (elog_addr)</div><div class='ctx'> 		acpi_os_unmap_iomem(elog_addr, elog_size);</div><div class='ctx'> 	release_mem_region(elog_base, elog_size);</div><div class='head'>diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c<br/>index c5598b6d5db8..794962c5c88e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_lpit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_lpit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_lpit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_lpit.c</a></div><div class='hunk'>@@ -105,7 +105,7 @@ static void lpit_update_residency(struct lpit_residency_info *info,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;frequency = lpit_native-&gt;counter_frequency ?</div><div class='del'>-				lpit_native-&gt;counter_frequency : tsc_khz * 1000;</div><div class='add'>+				lpit_native-&gt;counter_frequency : mul_u32_u32(tsc_khz, 1000U);</div><div class='ctx'> 	if (!info-&gt;frequency)</div><div class='ctx'> 		info-&gt;frequency = 1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c<br/>index 875de44961bf..04e273167e92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_lpss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_lpss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_lpss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_lpss.c</a></div><div class='hunk'>@@ -167,13 +167,9 @@ static struct pwm_lookup byt_pwm_lookup[] = {</div><div class='ctx'> </div><div class='ctx'> static void byt_pwm_setup(struct lpss_private_data *pdata)</div><div class='ctx'> {</div><div class='del'>-	u64 uid;</div><div class='del'>-</div><div class='ctx'> 	/* Only call pwm_add_table for the first PWM controller */</div><div class='del'>-	if (acpi_dev_uid_to_integer(pdata-&gt;adev, &amp;uid) || uid != 1)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));</div><div class='add'>+	if (acpi_dev_uid_match(pdata-&gt;adev, 1))</div><div class='add'>+		pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define LPSS_I2C_ENABLE			0x6c</div><div class='hunk'>@@ -218,13 +214,9 @@ static struct pwm_lookup bsw_pwm_lookup[] = {</div><div class='ctx'> </div><div class='ctx'> static void bsw_pwm_setup(struct lpss_private_data *pdata)</div><div class='ctx'> {</div><div class='del'>-	u64 uid;</div><div class='del'>-</div><div class='ctx'> 	/* Only call pwm_add_table for the first PWM controller */</div><div class='del'>-	if (acpi_dev_uid_to_integer(pdata-&gt;adev, &amp;uid) || uid != 1)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));</div><div class='add'>+	if (acpi_dev_uid_match(pdata-&gt;adev, 1))</div><div class='add'>+		pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct property_entry lpt_spi_properties[] = {</div><div class='hunk'>@@ -461,8 +453,9 @@ static int register_device_clock(struct acpi_device *adev,</div><div class='ctx'> 		if (!clk_name)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		clk = clk_register_fractional_divider(NULL, clk_name, parent,</div><div class='add'>+						      0, prv_base, 1, 15, 16, 15,</div><div class='ctx'> 						      CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,</div><div class='del'>-						      prv_base, 1, 15, 16, 15, 0, NULL);</div><div class='add'>+						      NULL);</div><div class='ctx'> 		parent = clk_name;</div><div class='ctx'> </div><div class='ctx'> 		clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);</div><div class='hunk'>@@ -570,34 +563,6 @@ static struct device *acpi_lpss_find_device(const char *hid, const char *uid)</div><div class='ctx'> 	return bus_find_device(&amp;pci_bus_type, NULL, &amp;data, match_hid_uid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool acpi_lpss_dep(struct acpi_device *adev, acpi_handle handle)</div><div class='del'>-{</div><div class='del'>-	struct acpi_handle_list dep_devices;</div><div class='del'>-	acpi_status status;</div><div class='del'>-	bool ret = false;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!acpi_has_method(adev-&gt;handle, "_DEP"))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	status = acpi_evaluate_reference(adev-&gt;handle, "_DEP", NULL,</div><div class='del'>-					 &amp;dep_devices);</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='del'>-		dev_dbg(&amp;adev-&gt;dev, "Failed to evaluate _DEP.\n");</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dep_devices.count; i++) {</div><div class='del'>-		if (dep_devices.handles[i] == handle) {</div><div class='del'>-			ret = true;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	acpi_handle_list_free(&amp;dep_devices);</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void acpi_lpss_link_consumer(struct device *dev1,</div><div class='ctx'> 				    const struct lpss_device_links *link)</div><div class='ctx'> {</div><div class='hunk'>@@ -608,7 +573,7 @@ static void acpi_lpss_link_consumer(struct device *dev1,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if ((link-&gt;dep_missing_ids &amp;&amp; dmi_check_system(link-&gt;dep_missing_ids))</div><div class='del'>-	    || acpi_lpss_dep(ACPI_COMPANION(dev2), ACPI_HANDLE(dev1)))</div><div class='add'>+	    || acpi_device_dep(ACPI_HANDLE(dev2), ACPI_HANDLE(dev1)))</div><div class='ctx'> 		device_link_add(dev2, dev1, link-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	put_device(dev2);</div><div class='hunk'>@@ -624,7 +589,7 @@ static void acpi_lpss_link_supplier(struct device *dev1,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if ((link-&gt;dep_missing_ids &amp;&amp; dmi_check_system(link-&gt;dep_missing_ids))</div><div class='del'>-	    || acpi_lpss_dep(ACPI_COMPANION(dev1), ACPI_HANDLE(dev2)))</div><div class='add'>+	    || acpi_device_dep(ACPI_HANDLE(dev1), ACPI_HANDLE(dev2)))</div><div class='ctx'> 		device_link_add(dev1, dev2, link-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	put_device(dev2);</div><div class='head'>diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c<br/>index 0f5218e361df..4fe2ef54088c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_processor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_processor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_processor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_processor.c</a></div><div class='hunk'>@@ -184,24 +184,6 @@ static void __init acpi_pcc_cpufreq_init(void) {}</div><div class='ctx'> </div><div class='ctx'> /* Initialization */</div><div class='ctx'> #ifdef CONFIG_ACPI_HOTPLUG_CPU</div><div class='del'>-int __weak acpi_map_cpu(acpi_handle handle,</div><div class='del'>-		phys_cpuid_t physid, u32 acpi_id, int *pcpu)</div><div class='del'>-{</div><div class='del'>-	return -ENODEV;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int __weak acpi_unmap_cpu(int cpu)</div><div class='del'>-{</div><div class='del'>-	return -ENODEV;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int __weak arch_register_cpu(int cpu)</div><div class='del'>-{</div><div class='del'>-	return -ENODEV;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void __weak arch_unregister_cpu(int cpu) {}</div><div class='del'>-</div><div class='ctx'> static int acpi_processor_hotadd_init(struct acpi_processor *pr)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long long sta;</div><div class='head'>diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c<br/>index d321ca7160d9..4afdda9db019 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_video.c</a></div><div class='hunk'>@@ -67,7 +67,7 @@ MODULE_PARM_DESC(hw_changes_brightness,</div><div class='ctx'> static bool device_id_scheme = false;</div><div class='ctx'> module_param(device_id_scheme, bool, 0444);</div><div class='ctx'> </div><div class='del'>-static int only_lcd = -1;</div><div class='add'>+static int only_lcd;</div><div class='ctx'> module_param(only_lcd, int, 0444);</div><div class='ctx'> </div><div class='ctx'> static bool may_report_brightness_keys;</div><div class='hunk'>@@ -253,8 +253,7 @@ static const struct backlight_ops acpi_backlight_ops = {</div><div class='ctx'> static int video_get_max_state(struct thermal_cooling_device *cooling_dev,</div><div class='ctx'> 			       unsigned long *state)</div><div class='ctx'> {</div><div class='del'>-	struct acpi_device *device = cooling_dev-&gt;devdata;</div><div class='del'>-	struct acpi_video_device *video = acpi_driver_data(device);</div><div class='add'>+	struct acpi_video_device *video = cooling_dev-&gt;devdata;</div><div class='ctx'> </div><div class='ctx'> 	*state = video-&gt;brightness-&gt;count - ACPI_VIDEO_FIRST_LEVEL - 1;</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -263,8 +262,7 @@ static int video_get_max_state(struct thermal_cooling_device *cooling_dev,</div><div class='ctx'> static int video_get_cur_state(struct thermal_cooling_device *cooling_dev,</div><div class='ctx'> 			       unsigned long *state)</div><div class='ctx'> {</div><div class='del'>-	struct acpi_device *device = cooling_dev-&gt;devdata;</div><div class='del'>-	struct acpi_video_device *video = acpi_driver_data(device);</div><div class='add'>+	struct acpi_video_device *video = cooling_dev-&gt;devdata;</div><div class='ctx'> 	unsigned long long level;</div><div class='ctx'> 	int offset;</div><div class='ctx'> </div><div class='hunk'>@@ -283,8 +281,7 @@ static int video_get_cur_state(struct thermal_cooling_device *cooling_dev,</div><div class='ctx'> static int</div><div class='ctx'> video_set_cur_state(struct thermal_cooling_device *cooling_dev, unsigned long state)</div><div class='ctx'> {</div><div class='del'>-	struct acpi_device *device = cooling_dev-&gt;devdata;</div><div class='del'>-	struct acpi_video_device *video = acpi_driver_data(device);</div><div class='add'>+	struct acpi_video_device *video = cooling_dev-&gt;devdata;</div><div class='ctx'> 	int level;</div><div class='ctx'> </div><div class='ctx'> 	if (state &gt;= video-&gt;brightness-&gt;count - ACPI_VIDEO_FIRST_LEVEL)</div><div class='hunk'>@@ -503,6 +500,15 @@ static const struct dmi_system_id video_dmi_table[] = {</div><div class='ctx'> 		DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3350"),</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+	 .callback = video_set_report_key_events,</div><div class='add'>+	 .driver_data = (void *)((uintptr_t)REPORT_BRIGHTNESS_KEY_EVENTS),</div><div class='add'>+	 .ident = "COLORFUL X15 AT 23",</div><div class='add'>+	 .matches = {</div><div class='add'>+		DMI_MATCH(DMI_SYS_VENDOR, "COLORFUL"),</div><div class='add'>+		DMI_MATCH(DMI_PRODUCT_NAME, "X15 AT 23"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Some machines change the brightness themselves when a brightness</div><div class='ctx'> 	 * hotkey gets pressed, despite us telling them not to. In this case</div><div class='hunk'>@@ -1125,7 +1131,6 @@ static int acpi_video_bus_get_one_device(struct acpi_device *device, void *arg)</div><div class='ctx'> </div><div class='ctx'> 	strcpy(acpi_device_name(device), ACPI_VIDEO_DEVICE_NAME);</div><div class='ctx'> 	strcpy(acpi_device_class(device), ACPI_VIDEO_CLASS);</div><div class='del'>-	device-&gt;driver_data = data;</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;device_id = device_id;</div><div class='ctx'> 	data-&gt;video = video;</div><div class='hunk'>@@ -1717,12 +1722,12 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device)</div><div class='ctx'> 		return;</div><div class='ctx'> 	count++;</div><div class='ctx'> </div><div class='del'>-	acpi_get_parent(device-&gt;dev-&gt;handle, &amp;acpi_parent);</div><div class='del'>-</div><div class='del'>-	pdev = acpi_get_pci_dev(acpi_parent);</div><div class='del'>-	if (pdev) {</div><div class='del'>-		parent = &amp;pdev-&gt;dev;</div><div class='del'>-		pci_dev_put(pdev);</div><div class='add'>+	if (ACPI_SUCCESS(acpi_get_parent(device-&gt;dev-&gt;handle, &amp;acpi_parent))) {</div><div class='add'>+		pdev = acpi_get_pci_dev(acpi_parent);</div><div class='add'>+		if (pdev) {</div><div class='add'>+			parent = &amp;pdev-&gt;dev;</div><div class='add'>+			pci_dev_put(pdev);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;props, 0, sizeof(struct backlight_properties));</div><div class='hunk'>@@ -1747,8 +1752,8 @@ static void acpi_video_dev_register_backlight(struct acpi_video_device *device)</div><div class='ctx'> 	device-&gt;backlight-&gt;props.brightness =</div><div class='ctx'> 			acpi_video_get_brightness(device-&gt;backlight);</div><div class='ctx'> </div><div class='del'>-	device-&gt;cooling_dev = thermal_cooling_device_register("LCD",</div><div class='del'>-				device-&gt;dev, &amp;video_cooling_ops);</div><div class='add'>+	device-&gt;cooling_dev = thermal_cooling_device_register("LCD", device,</div><div class='add'>+							      &amp;video_cooling_ops);</div><div class='ctx'> 	if (IS_ERR(device-&gt;cooling_dev)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Set cooling_dev to NULL so we don't crash trying to free it.</div><div class='hunk'>@@ -2141,57 +2146,6 @@ static int __init intel_opregion_present(void)</div><div class='ctx'> 	return opregion;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* Check if the chassis-type indicates there is no builtin LCD panel */</div><div class='del'>-static bool dmi_is_desktop(void)</div><div class='del'>-{</div><div class='del'>-	const char *chassis_type;</div><div class='del'>-	unsigned long type;</div><div class='del'>-</div><div class='del'>-	chassis_type = dmi_get_system_info(DMI_CHASSIS_TYPE);</div><div class='del'>-	if (!chassis_type)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	if (kstrtoul(chassis_type, 10, &amp;type) != 0)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	switch (type) {</div><div class='del'>-	case 0x03: /* Desktop */</div><div class='del'>-	case 0x04: /* Low Profile Desktop */</div><div class='del'>-	case 0x05: /* Pizza Box */</div><div class='del'>-	case 0x06: /* Mini Tower */</div><div class='del'>-	case 0x07: /* Tower */</div><div class='del'>-	case 0x10: /* Lunch Box */</div><div class='del'>-	case 0x11: /* Main Server Chassis */</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * We're seeing a lot of bogus backlight interfaces on newer machines</div><div class='del'>- * without a LCD such as desktops, servers and HDMI sticks. Checking the</div><div class='del'>- * lcd flag fixes this, enable this by default on any machines which are:</div><div class='del'>- * 1.  Win8 ready (where we also prefer the native backlight driver, so</div><div class='del'>- *     normally the acpi_video code should not register there anyways); *and*</div><div class='del'>- * 2.1 Report a desktop/server DMI chassis-type, or</div><div class='del'>- * 2.2 Are an ACPI-reduced-hardware platform (and thus won't use the EC for</div><div class='del'>-       backlight control)</div><div class='del'>- */</div><div class='del'>-static bool should_check_lcd_flag(void)</div><div class='del'>-{</div><div class='del'>-	if (!acpi_osi_is_win8())</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	if (dmi_is_desktop())</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	if (acpi_reduced_hardware())</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int acpi_video_register(void)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -2205,9 +2159,6 @@ int acpi_video_register(void)</div><div class='ctx'> 		goto leave;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (only_lcd == -1)</div><div class='del'>-		only_lcd = should_check_lcd_flag();</div><div class='del'>-</div><div class='ctx'> 	dmi_check_system(video_dmi_table);</div><div class='ctx'> </div><div class='ctx'> 	ret = acpi_bus_register_driver(&amp;acpi_video_bus);</div><div class='head'>diff --git a/drivers/acpi/acpi_watchdog.c b/drivers/acpi/acpi_watchdog.c<br/>index ca28183f4d13..8e9e001da38f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_watchdog.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/acpi_watchdog.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/acpi_watchdog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/acpi_watchdog.c</a></div><div class='hunk'>@@ -81,7 +81,7 @@ static const struct acpi_table_wdat *acpi_watchdog_get_wdat(void)</div><div class='ctx'> 	return wdat;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='add'>+/*</div><div class='ctx'>  * Returns true if this system should prefer ACPI based watchdog instead of</div><div class='ctx'>  * the native one (which are typically the same hardware).</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c<br/>index 013eb621dc92..89fb9331c611 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/apei/einj.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/apei/einj.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/apei/einj.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/apei/einj.c</a></div><div class='hunk'>@@ -73,6 +73,7 @@ static u32 notrigger;</div><div class='ctx'> </div><div class='ctx'> static u32 vendor_flags;</div><div class='ctx'> static struct debugfs_blob_wrapper vendor_blob;</div><div class='add'>+static struct debugfs_blob_wrapper vendor_errors;</div><div class='ctx'> static char vendor_dev[64];</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -182,6 +183,21 @@ static int einj_timedout(u64 *t)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void get_oem_vendor_struct(u64 paddr, int offset,</div><div class='add'>+				  struct vendor_error_type_extension *v)</div><div class='add'>+{</div><div class='add'>+	unsigned long vendor_size;</div><div class='add'>+	u64 target_pa = paddr + offset + sizeof(struct vendor_error_type_extension);</div><div class='add'>+</div><div class='add'>+	vendor_size = v-&gt;length - sizeof(struct vendor_error_type_extension);</div><div class='add'>+</div><div class='add'>+	if (vendor_size)</div><div class='add'>+		vendor_errors.data = acpi_os_map_memory(target_pa, vendor_size);</div><div class='add'>+</div><div class='add'>+	if (vendor_errors.data)</div><div class='add'>+		vendor_errors.size = vendor_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void check_vendor_extension(u64 paddr,</div><div class='ctx'> 				   struct set_error_type_with_address *v5param)</div><div class='ctx'> {</div><div class='hunk'>@@ -194,6 +210,7 @@ static void check_vendor_extension(u64 paddr,</div><div class='ctx'> 	v = acpi_os_map_iomem(paddr + offset, sizeof(*v));</div><div class='ctx'> 	if (!v)</div><div class='ctx'> 		return;</div><div class='add'>+	get_oem_vendor_struct(paddr, offset, v);</div><div class='ctx'> 	sbdf = v-&gt;pcie_sbdf;</div><div class='ctx'> 	sprintf(vendor_dev, "%x:%x:%x.%x vendor_id=%x device_id=%x rev_id=%x\n",</div><div class='ctx'> 		sbdf &gt;&gt; 24, (sbdf &gt;&gt; 16) &amp; 0xff,</div><div class='hunk'>@@ -577,38 +594,40 @@ static u64 error_param2;</div><div class='ctx'> static u64 error_param3;</div><div class='ctx'> static u64 error_param4;</div><div class='ctx'> static struct dentry *einj_debug_dir;</div><div class='del'>-static const char * const einj_error_type_string[] = {</div><div class='del'>-	"0x00000001\tProcessor Correctable\n",</div><div class='del'>-	"0x00000002\tProcessor Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00000004\tProcessor Uncorrectable fatal\n",</div><div class='del'>-	"0x00000008\tMemory Correctable\n",</div><div class='del'>-	"0x00000010\tMemory Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00000020\tMemory Uncorrectable fatal\n",</div><div class='del'>-	"0x00000040\tPCI Express Correctable\n",</div><div class='del'>-	"0x00000080\tPCI Express Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00000100\tPCI Express Uncorrectable fatal\n",</div><div class='del'>-	"0x00000200\tPlatform Correctable\n",</div><div class='del'>-	"0x00000400\tPlatform Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00000800\tPlatform Uncorrectable fatal\n",</div><div class='del'>-	"0x00001000\tCXL.cache Protocol Correctable\n",</div><div class='del'>-	"0x00002000\tCXL.cache Protocol Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00004000\tCXL.cache Protocol Uncorrectable fatal\n",</div><div class='del'>-	"0x00008000\tCXL.mem Protocol Correctable\n",</div><div class='del'>-	"0x00010000\tCXL.mem Protocol Uncorrectable non-fatal\n",</div><div class='del'>-	"0x00020000\tCXL.mem Protocol Uncorrectable fatal\n",</div><div class='add'>+static struct { u32 mask; const char *str; } const einj_error_type_string[] = {</div><div class='add'>+	{ BIT(0), "Processor Correctable" },</div><div class='add'>+	{ BIT(1), "Processor Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(2), "Processor Uncorrectable fatal" },</div><div class='add'>+	{ BIT(3), "Memory Correctable" },</div><div class='add'>+	{ BIT(4), "Memory Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(5), "Memory Uncorrectable fatal" },</div><div class='add'>+	{ BIT(6), "PCI Express Correctable" },</div><div class='add'>+	{ BIT(7), "PCI Express Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(8), "PCI Express Uncorrectable fatal" },</div><div class='add'>+	{ BIT(9), "Platform Correctable" },</div><div class='add'>+	{ BIT(10), "Platform Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(11), "Platform Uncorrectable fatal"},</div><div class='add'>+	{ BIT(12), "CXL.cache Protocol Correctable" },</div><div class='add'>+	{ BIT(13), "CXL.cache Protocol Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(14), "CXL.cache Protocol Uncorrectable fatal" },</div><div class='add'>+	{ BIT(15), "CXL.mem Protocol Correctable" },</div><div class='add'>+	{ BIT(16), "CXL.mem Protocol Uncorrectable non-fatal" },</div><div class='add'>+	{ BIT(17), "CXL.mem Protocol Uncorrectable fatal" },</div><div class='add'>+	{ BIT(31), "Vendor Defined Error Types" },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int available_error_type_show(struct seq_file *m, void *v)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='del'>-	u32 available_error_type = 0;</div><div class='add'>+	u32 error_type = 0;</div><div class='ctx'> </div><div class='del'>-	rc = einj_get_available_error_type(&amp;available_error_type);</div><div class='add'>+	rc = einj_get_available_error_type(&amp;error_type);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	for (int pos = 0; pos &lt; ARRAY_SIZE(einj_error_type_string); pos++)</div><div class='del'>-		if (available_error_type &amp; BIT(pos))</div><div class='del'>-			seq_puts(m, einj_error_type_string[pos]);</div><div class='add'>+		if (error_type &amp; einj_error_type_string[pos].mask)</div><div class='add'>+			seq_printf(m, "0x%08x\t%s\n", einj_error_type_string[pos].mask,</div><div class='add'>+				   einj_error_type_string[pos].str);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -767,6 +786,10 @@ static int __init einj_init(void)</div><div class='ctx'> 				   einj_debug_dir, &amp;vendor_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (vendor_errors.size)</div><div class='add'>+		debugfs_create_blob("oem_error", 0600, einj_debug_dir,</div><div class='add'>+				    &amp;vendor_errors);</div><div class='add'>+</div><div class='ctx'> 	pr_info("Error INJection is initialized.\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -792,6 +815,8 @@ static void __exit einj_exit(void)</div><div class='ctx'> 			sizeof(struct einj_parameter);</div><div class='ctx'> </div><div class='ctx'> 		acpi_os_unmap_iomem(einj_param, size);</div><div class='add'>+		if (vendor_errors.size)</div><div class='add'>+			acpi_os_unmap_memory(vendor_errors.data, vendor_errors.size);</div><div class='ctx'> 	}</div><div class='ctx'> 	einj_exec_ctx_init(&amp;ctx);</div><div class='ctx'> 	apei_exec_post_unmap_gars(&amp;ctx);</div><div class='head'>diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c<br/>index 63ad0541db38..7b7c605166e0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/apei/ghes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/apei/ghes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/apei/ghes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/apei/ghes.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/timer.h&gt;</div><div class='ctx'> #include &lt;linux/cper.h&gt;</div><div class='add'>+#include &lt;linux/cxl-event.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/ratelimit.h&gt;</div><div class='hunk'>@@ -102,6 +103,20 @@ static inline bool is_hest_type_generic_v2(struct ghes *ghes)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * A platform may describe one error source for the handling of synchronous</div><div class='add'>+ * errors (e.g. MCE or SEA), or for handling asynchronous errors (e.g. SCI</div><div class='add'>+ * or External Interrupt). On x86, the HEST notifications are always</div><div class='add'>+ * asynchronous, so only SEA on ARM is delivered as a synchronous</div><div class='add'>+ * notification.</div><div class='add'>+ */</div><div class='add'>+static inline bool is_hest_sync_notify(struct ghes *ghes)</div><div class='add'>+{</div><div class='add'>+	u8 notify_type = ghes-&gt;generic-&gt;notify.type;</div><div class='add'>+</div><div class='add'>+	return notify_type == ACPI_HEST_NOTIFY_SEA;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * This driver isn't really modular, however for the time being,</div><div class='ctx'>  * continuing to use module_param is the easiest way to remain</div><div class='ctx'>  * compatible with existing boot arg use cases.</div><div class='hunk'>@@ -489,7 +504,7 @@ static bool ghes_do_memory_failure(u64 physical_addr, int flags)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata,</div><div class='del'>-				       int sev)</div><div class='add'>+				       int sev, bool sync)</div><div class='ctx'> {</div><div class='ctx'> 	int flags = -1;</div><div class='ctx'> 	int sec_sev = ghes_severity(gdata-&gt;error_severity);</div><div class='hunk'>@@ -503,7 +518,7 @@ static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata,</div><div class='ctx'> 	    (gdata-&gt;flags &amp; CPER_SEC_ERROR_THRESHOLD_EXCEEDED))</div><div class='ctx'> 		flags = MF_SOFT_OFFLINE;</div><div class='ctx'> 	if (sev == GHES_SEV_RECOVERABLE &amp;&amp; sec_sev == GHES_SEV_RECOVERABLE)</div><div class='del'>-		flags = 0;</div><div class='add'>+		flags = sync ? MF_ACTION_REQUIRED : 0;</div><div class='ctx'> </div><div class='ctx'> 	if (flags != -1)</div><div class='ctx'> 		return ghes_do_memory_failure(mem_err-&gt;physical_addr, flags);</div><div class='hunk'>@@ -511,9 +526,11 @@ static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata,</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, int sev)</div><div class='add'>+static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata,</div><div class='add'>+				       int sev, bool sync)</div><div class='ctx'> {</div><div class='ctx'> 	struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata);</div><div class='add'>+	int flags = sync ? MF_ACTION_REQUIRED : 0;</div><div class='ctx'> 	bool queued = false;</div><div class='ctx'> 	int sec_sev, i;</div><div class='ctx'> 	char *p;</div><div class='hunk'>@@ -538,7 +555,7 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, int s</div><div class='ctx'> 		 * and don't filter out 'corrected' error here.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (is_cache &amp;&amp; has_pa) {</div><div class='del'>-			queued = ghes_do_memory_failure(err_info-&gt;physical_fault_addr, 0);</div><div class='add'>+			queued = ghes_do_memory_failure(err_info-&gt;physical_fault_addr, flags);</div><div class='ctx'> 			p += err_info-&gt;length;</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -657,6 +674,78 @@ static void ghes_defer_non_standard_event(struct acpi_hest_generic_data *gdata,</div><div class='ctx'> 	schedule_work(&amp;entry-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Only a single callback can be registered for CXL CPER events.</div><div class='add'>+ */</div><div class='add'>+static DECLARE_RWSEM(cxl_cper_rw_sem);</div><div class='add'>+static cxl_cper_callback cper_callback;</div><div class='add'>+</div><div class='add'>+/* CXL Event record UUIDs are formatted as GUIDs and reported in section type */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * General Media Event Record</div><div class='add'>+ * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43</div><div class='add'>+ */</div><div class='add'>+#define CPER_SEC_CXL_GEN_MEDIA_GUID					\</div><div class='add'>+	GUID_INIT(0xfbcd0a77, 0xc260, 0x417f,				\</div><div class='add'>+		  0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * DRAM Event Record</div><div class='add'>+ * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44</div><div class='add'>+ */</div><div class='add'>+#define CPER_SEC_CXL_DRAM_GUID						\</div><div class='add'>+	GUID_INIT(0x601dcbb3, 0x9c06, 0x4eab,				\</div><div class='add'>+		  0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Memory Module Event Record</div><div class='add'>+ * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45</div><div class='add'>+ */</div><div class='add'>+#define CPER_SEC_CXL_MEM_MODULE_GUID					\</div><div class='add'>+	GUID_INIT(0xfe927475, 0xdd59, 0x4339,				\</div><div class='add'>+		  0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74)</div><div class='add'>+</div><div class='add'>+static void cxl_cper_post_event(enum cxl_event_type event_type,</div><div class='add'>+				struct cxl_cper_event_rec *rec)</div><div class='add'>+{</div><div class='add'>+	if (rec-&gt;hdr.length &lt;= sizeof(rec-&gt;hdr) ||</div><div class='add'>+	    rec-&gt;hdr.length &gt; sizeof(*rec)) {</div><div class='add'>+		pr_err(FW_WARN "CXL CPER Invalid section length (%u)\n",</div><div class='add'>+		       rec-&gt;hdr.length);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(rec-&gt;hdr.validation_bits &amp; CPER_CXL_COMP_EVENT_LOG_VALID)) {</div><div class='add'>+		pr_err(FW_WARN "CXL CPER invalid event\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	guard(rwsem_read)(&amp;cxl_cper_rw_sem);</div><div class='add'>+	if (cper_callback)</div><div class='add'>+		cper_callback(event_type, rec);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int cxl_cper_register_callback(cxl_cper_callback callback)</div><div class='add'>+{</div><div class='add'>+	guard(rwsem_write)(&amp;cxl_cper_rw_sem);</div><div class='add'>+	if (cper_callback)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	cper_callback = callback;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_cper_register_callback, CXL);</div><div class='add'>+</div><div class='add'>+int cxl_cper_unregister_callback(cxl_cper_callback callback)</div><div class='add'>+{</div><div class='add'>+	guard(rwsem_write)(&amp;cxl_cper_rw_sem);</div><div class='add'>+	if (callback != cper_callback)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	cper_callback = NULL;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_callback, CXL);</div><div class='add'>+</div><div class='ctx'> static bool ghes_do_proc(struct ghes *ghes,</div><div class='ctx'> 			 const struct acpi_hest_generic_status *estatus)</div><div class='ctx'> {</div><div class='hunk'>@@ -666,6 +755,7 @@ static bool ghes_do_proc(struct ghes *ghes,</div><div class='ctx'> 	const guid_t *fru_id = &amp;guid_null;</div><div class='ctx'> 	char *fru_text = "";</div><div class='ctx'> 	bool queued = false;</div><div class='add'>+	bool sync = is_hest_sync_notify(ghes);</div><div class='ctx'> </div><div class='ctx'> 	sev = ghes_severity(estatus-&gt;error_severity);</div><div class='ctx'> 	apei_estatus_for_each_section(estatus, gdata) {</div><div class='hunk'>@@ -683,13 +773,29 @@ static bool ghes_do_proc(struct ghes *ghes,</div><div class='ctx'> 			atomic_notifier_call_chain(&amp;ghes_report_chain, sev, mem_err);</div><div class='ctx'> </div><div class='ctx'> 			arch_apei_report_mem_error(sev, mem_err);</div><div class='del'>-			queued = ghes_handle_memory_failure(gdata, sev);</div><div class='add'>+			queued = ghes_handle_memory_failure(gdata, sev, sync);</div><div class='ctx'> 		}</div><div class='ctx'> 		else if (guid_equal(sec_type, &amp;CPER_SEC_PCIE)) {</div><div class='ctx'> 			ghes_handle_aer(gdata);</div><div class='ctx'> 		}</div><div class='ctx'> 		else if (guid_equal(sec_type, &amp;CPER_SEC_PROC_ARM)) {</div><div class='del'>-			queued = ghes_handle_arm_hw_error(gdata, sev);</div><div class='add'>+			queued = ghes_handle_arm_hw_error(gdata, sev, sync);</div><div class='add'>+		} else if (guid_equal(sec_type, &amp;CPER_SEC_CXL_GEN_MEDIA_GUID)) {</div><div class='add'>+			struct cxl_cper_event_rec *rec =</div><div class='add'>+				acpi_hest_get_payload(gdata);</div><div class='add'>+</div><div class='add'>+			cxl_cper_post_event(CXL_CPER_EVENT_GEN_MEDIA, rec);</div><div class='add'>+		} else if (guid_equal(sec_type, &amp;CPER_SEC_CXL_DRAM_GUID)) {</div><div class='add'>+			struct cxl_cper_event_rec *rec =</div><div class='add'>+				acpi_hest_get_payload(gdata);</div><div class='add'>+</div><div class='add'>+			cxl_cper_post_event(CXL_CPER_EVENT_DRAM, rec);</div><div class='add'>+		} else if (guid_equal(sec_type,</div><div class='add'>+				      &amp;CPER_SEC_CXL_MEM_MODULE_GUID)) {</div><div class='add'>+			struct cxl_cper_event_rec *rec =</div><div class='add'>+				acpi_hest_get_payload(gdata);</div><div class='add'>+</div><div class='add'>+			cxl_cper_post_event(CXL_CPER_EVENT_MEM_MODULE, rec);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			void *err = acpi_hest_get_payload(gdata);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile<br/>index 143debc1ba4a..726944648c9b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/arm64/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/arm64/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/arm64/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/arm64/Makefile</a></div><div class='hunk'>@@ -5,3 +5,4 @@ obj-$(CONFIG_ACPI_GTDT) 	+= gtdt.o</div><div class='ctx'> obj-$(CONFIG_ACPI_APMT) 	+= apmt.o</div><div class='ctx'> obj-$(CONFIG_ARM_AMBA)		+= amba.o</div><div class='ctx'> obj-y				+= dma.o init.o</div><div class='add'>+obj-y				+= thermal_cpufreq.o</div><div class='head'>diff --git a/drivers/acpi/arm64/thermal_cpufreq.c b/drivers/acpi/arm64/thermal_cpufreq.c<br/>new file mode 100644<br/>index 000000000000..582854914c5c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/arm64/thermal_cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/arm64/thermal_cpufreq.c</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/export.h&gt;</div><div class='add'>+</div><div class='add'>+#include "../internal.h"</div><div class='add'>+</div><div class='add'>+#define SMCCC_SOC_ID_T241      0x036b0241</div><div class='add'>+</div><div class='add'>+int acpi_arch_thermal_cpufreq_pctg(void)</div><div class='add'>+{</div><div class='add'>+	s32 soc_id = arm_smccc_get_soc_id_version();</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check JEP106 code for NVIDIA Tegra241 chip (036b:0241) and</div><div class='add'>+	 * reduce the CPUFREQ Thermal reduction percentage to 5%.</div><div class='add'>+	 */</div><div class='add'>+	if (soc_id == SMCCC_SOC_ID_T241)</div><div class='add'>+		return 5;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(acpi_arch_thermal_cpufreq_pctg);</div><div class='head'>diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c<br/>index 72e64c0718c9..569bd15f211b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/bus.c</a></div><div class='hunk'>@@ -408,7 +408,7 @@ static void acpi_bus_decode_usb_osc(const char *msg, u32 bits)</div><div class='ctx'> static u8 sb_usb_uuid_str[] = "23A0D13A-26AB-486C-9C5F-0FFA525A575A";</div><div class='ctx'> static void acpi_bus_osc_negotiate_usb_control(void)</div><div class='ctx'> {</div><div class='del'>-	u32 capbuf[3];</div><div class='add'>+	u32 capbuf[3], *capbuf_ret;</div><div class='ctx'> 	struct acpi_osc_context context = {</div><div class='ctx'> 		.uuid_str = sb_usb_uuid_str,</div><div class='ctx'> 		.rev = 1,</div><div class='hunk'>@@ -428,7 +428,12 @@ static void acpi_bus_osc_negotiate_usb_control(void)</div><div class='ctx'> 	control = OSC_USB_USB3_TUNNELING | OSC_USB_DP_TUNNELING |</div><div class='ctx'> 		  OSC_USB_PCIE_TUNNELING | OSC_USB_XDOMAIN;</div><div class='ctx'> </div><div class='del'>-	capbuf[OSC_QUERY_DWORD] = 0;</div><div class='add'>+	/*</div><div class='add'>+	 * Run _OSC first with query bit set, trying to get control over</div><div class='add'>+	 * all tunneling. The platform can then clear out bits in the</div><div class='add'>+	 * control dword that it does not want to grant to the OS.</div><div class='add'>+	 */</div><div class='add'>+	capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;</div><div class='ctx'> 	capbuf[OSC_SUPPORT_DWORD] = 0;</div><div class='ctx'> 	capbuf[OSC_CONTROL_DWORD] = control;</div><div class='ctx'> </div><div class='hunk'>@@ -441,8 +446,29 @@ static void acpi_bus_osc_negotiate_usb_control(void)</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Run _OSC again now with query bit clear and the control dword</div><div class='add'>+	 * matching what the platform granted (which may not have all</div><div class='add'>+	 * the control bits set).</div><div class='add'>+	 */</div><div class='add'>+	capbuf_ret = context.ret.pointer;</div><div class='add'>+</div><div class='add'>+	capbuf[OSC_QUERY_DWORD] = 0;</div><div class='add'>+	capbuf[OSC_CONTROL_DWORD] = capbuf_ret[OSC_CONTROL_DWORD];</div><div class='add'>+</div><div class='add'>+	kfree(context.ret.pointer);</div><div class='add'>+</div><div class='add'>+	status = acpi_run_osc(handle, &amp;context);</div><div class='add'>+	if (ACPI_FAILURE(status))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (context.ret.length != sizeof(capbuf)) {</div><div class='add'>+		pr_info("USB4 _OSC: returned invalid length buffer\n");</div><div class='add'>+		goto out_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	osc_sb_native_usb4_control =</div><div class='del'>-		control &amp;  acpi_osc_ctx_get_pci_control(&amp;context);</div><div class='add'>+		control &amp; acpi_osc_ctx_get_pci_control(&amp;context);</div><div class='ctx'> </div><div class='ctx'> 	acpi_bus_decode_usb_osc("USB4 _OSC: OS supports", control);</div><div class='ctx'> 	acpi_bus_decode_usb_osc("USB4 _OSC: OS controls",</div><div class='head'>diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c<br/>index 1e76a64cce0a..cc61020756be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/button.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/button.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/button.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/button.c</a></div><div class='hunk'>@@ -480,6 +480,7 @@ static int acpi_button_suspend(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> static int acpi_button_resume(struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	struct input_dev *input;</div><div class='ctx'> 	struct acpi_device *device = to_acpi_device(dev);</div><div class='ctx'> 	struct acpi_button *button = acpi_driver_data(device);</div><div class='ctx'> </div><div class='hunk'>@@ -489,6 +490,14 @@ static int acpi_button_resume(struct device *dev)</div><div class='ctx'> 		button-&gt;last_time = ktime_get();</div><div class='ctx'> 		acpi_lid_initialize_state(device);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (button-&gt;type == ACPI_BUTTON_TYPE_POWER) {</div><div class='add'>+		input = button-&gt;input;</div><div class='add'>+		input_report_key(input, KEY_WAKEUP, 1);</div><div class='add'>+		input_sync(input);</div><div class='add'>+		input_report_key(input, KEY_WAKEUP, 0);</div><div class='add'>+		input_sync(input);</div><div class='add'>+	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='hunk'>@@ -579,6 +588,7 @@ static int acpi_button_add(struct acpi_device *device)</div><div class='ctx'> 	switch (button-&gt;type) {</div><div class='ctx'> 	case ACPI_BUTTON_TYPE_POWER:</div><div class='ctx'> 		input_set_capability(input, EV_KEY, KEY_POWER);</div><div class='add'>+		input_set_capability(input, EV_KEY, KEY_WAKEUP);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case ACPI_BUTTON_TYPE_SLEEP:</div><div class='head'>diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c<br/>index 7ff269a78c20..d155a86a8614 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/cppc_acpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/cppc_acpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/cppc_acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/cppc_acpi.c</a></div><div class='hunk'>@@ -39,6 +39,9 @@</div><div class='ctx'> #include &lt;linux/rwsem.h&gt;</div><div class='ctx'> #include &lt;linux/wait.h&gt;</div><div class='ctx'> #include &lt;linux/topology.h&gt;</div><div class='add'>+#include &lt;linux/dmi.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;acpi/cppc_acpi.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -1760,3 +1763,104 @@ unsigned int cppc_get_transition_latency(int cpu_num)</div><div class='ctx'> 	return latency_ns;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(cppc_get_transition_latency);</div><div class='add'>+</div><div class='add'>+/* Minimum struct length needed for the DMI processor entry we want */</div><div class='add'>+#define DMI_ENTRY_PROCESSOR_MIN_LENGTH	48</div><div class='add'>+</div><div class='add'>+/* Offset in the DMI processor structure for the max frequency */</div><div class='add'>+#define DMI_PROCESSOR_MAX_SPEED		0x14</div><div class='add'>+</div><div class='add'>+/* Callback function used to retrieve the max frequency from DMI */</div><div class='add'>+static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)</div><div class='add'>+{</div><div class='add'>+	const u8 *dmi_data = (const u8 *)dm;</div><div class='add'>+	u16 *mhz = (u16 *)private;</div><div class='add'>+</div><div class='add'>+	if (dm-&gt;type == DMI_ENTRY_PROCESSOR &amp;&amp;</div><div class='add'>+	    dm-&gt;length &gt;= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {</div><div class='add'>+		u16 val = (u16)get_unaligned((const u16 *)</div><div class='add'>+				(dmi_data + DMI_PROCESSOR_MAX_SPEED));</div><div class='add'>+		*mhz = val &gt; *mhz ? val : *mhz;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Look up the max frequency in DMI */</div><div class='add'>+static u64 cppc_get_dmi_max_khz(void)</div><div class='add'>+{</div><div class='add'>+	u16 mhz = 0;</div><div class='add'>+</div><div class='add'>+	dmi_walk(cppc_find_dmi_mhz, &amp;mhz);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Real stupid fallback value, just in case there is no</div><div class='add'>+	 * actual value set.</div><div class='add'>+	 */</div><div class='add'>+	mhz = mhz ? mhz : 1;</div><div class='add'>+</div><div class='add'>+	return KHZ_PER_MHZ * mhz;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * If CPPC lowest_freq and nominal_freq registers are exposed then we can</div><div class='add'>+ * use them to convert perf to freq and vice versa. The conversion is</div><div class='add'>+ * extrapolated as an affine function passing by the 2 points:</div><div class='add'>+ *  - (Low perf, Low freq)</div><div class='add'>+ *  - (Nominal perf, Nominal freq)</div><div class='add'>+ */</div><div class='add'>+unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)</div><div class='add'>+{</div><div class='add'>+	s64 retval, offset = 0;</div><div class='add'>+	static u64 max_khz;</div><div class='add'>+	u64 mul, div;</div><div class='add'>+</div><div class='add'>+	if (caps-&gt;lowest_freq &amp;&amp; caps-&gt;nominal_freq) {</div><div class='add'>+		mul = caps-&gt;nominal_freq - caps-&gt;lowest_freq;</div><div class='add'>+		mul *= KHZ_PER_MHZ;</div><div class='add'>+		div = caps-&gt;nominal_perf - caps-&gt;lowest_perf;</div><div class='add'>+		offset = caps-&gt;nominal_freq * KHZ_PER_MHZ -</div><div class='add'>+			 div64_u64(caps-&gt;nominal_perf * mul, div);</div><div class='add'>+	} else {</div><div class='add'>+		if (!max_khz)</div><div class='add'>+			max_khz = cppc_get_dmi_max_khz();</div><div class='add'>+		mul = max_khz;</div><div class='add'>+		div = caps-&gt;highest_perf;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	retval = offset + div64_u64(perf * mul, div);</div><div class='add'>+	if (retval &gt;= 0)</div><div class='add'>+		return retval;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(cppc_perf_to_khz);</div><div class='add'>+</div><div class='add'>+unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)</div><div class='add'>+{</div><div class='add'>+	s64 retval, offset = 0;</div><div class='add'>+	static u64 max_khz;</div><div class='add'>+	u64  mul, div;</div><div class='add'>+</div><div class='add'>+	if (caps-&gt;lowest_freq &amp;&amp; caps-&gt;nominal_freq) {</div><div class='add'>+		mul = caps-&gt;nominal_perf - caps-&gt;lowest_perf;</div><div class='add'>+		div = caps-&gt;nominal_freq - caps-&gt;lowest_freq;</div><div class='add'>+		/*</div><div class='add'>+		 * We don't need to convert to kHz for computing offset and can</div><div class='add'>+		 * directly use nominal_freq and lowest_freq as the div64_u64</div><div class='add'>+		 * will remove the frequency unit.</div><div class='add'>+		 */</div><div class='add'>+		offset = caps-&gt;nominal_perf -</div><div class='add'>+			 div64_u64(caps-&gt;nominal_freq * mul, div);</div><div class='add'>+		/* But we need it for computing the perf level. */</div><div class='add'>+		div *= KHZ_PER_MHZ;</div><div class='add'>+	} else {</div><div class='add'>+		if (!max_khz)</div><div class='add'>+			max_khz = cppc_get_dmi_max_khz();</div><div class='add'>+		mul = caps-&gt;highest_perf;</div><div class='add'>+		div = max_khz;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	retval = offset + div64_u64(freq * mul, div);</div><div class='add'>+	if (retval &gt;= 0)</div><div class='add'>+		return retval;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(cppc_khz_to_perf);</div><div class='head'>diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c<br/>index a59c11df7375..dbdee2924594 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/ec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/ec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/ec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/ec.c</a></div><div class='hunk'>@@ -525,12 +525,10 @@ static void acpi_ec_clear(struct acpi_ec *ec)</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_enable_event(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (acpi_ec_started(ec))</div><div class='ctx'> 		__acpi_ec_enable_event(ec);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	/* Drain additional events if hardware requires that */</div><div class='ctx'> 	if (EC_FLAGS_CLEAR_ON_RESUME)</div><div class='hunk'>@@ -546,11 +544,9 @@ static void __acpi_ec_flush_work(void)</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_disable_event(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	__acpi_ec_disable_event(ec);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * When ec_freeze_events is true, we need to flush events in</div><div class='hunk'>@@ -571,10 +567,9 @@ void acpi_ec_flush_work(void)</div><div class='ctx'> </div><div class='ctx'> static bool acpi_ec_guard_event(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	bool guarded;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If firmware SCI_EVT clearing timing is "event", we actually</div><div class='ctx'> 	 * don't know when the SCI_EVT will be cleared by firmware after</div><div class='hunk'>@@ -590,31 +585,29 @@ static bool acpi_ec_guard_event(struct acpi_ec *ec)</div><div class='ctx'> 	guarded = ec_event_clearing == ACPI_EC_EVT_TIMING_EVENT &amp;&amp;</div><div class='ctx'> 		ec-&gt;event_state != EC_EVENT_READY &amp;&amp;</div><div class='ctx'> 		(!ec-&gt;curr || ec-&gt;curr-&gt;command != ACPI_EC_COMMAND_QUERY);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	return guarded;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ec_transaction_polled(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (ec-&gt;curr &amp;&amp; (ec-&gt;curr-&gt;flags &amp; ACPI_EC_COMMAND_POLL))</div><div class='ctx'> 		ret = 1;</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ec_transaction_completed(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (ec-&gt;curr &amp;&amp; (ec-&gt;curr-&gt;flags &amp; ACPI_EC_COMMAND_COMPLETE))</div><div class='ctx'> 		ret = 1;</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -756,7 +749,6 @@ static int ec_guard(struct acpi_ec *ec)</div><div class='ctx'> </div><div class='ctx'> static int ec_poll(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	int repeat = 5; /* number of command restarts */</div><div class='ctx'> </div><div class='ctx'> 	while (repeat--) {</div><div class='hunk'>@@ -765,14 +757,14 @@ static int ec_poll(struct acpi_ec *ec)</div><div class='ctx'> 		do {</div><div class='ctx'> 			if (!ec_guard(ec))</div><div class='ctx'> 				return 0;</div><div class='del'>-			spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+			spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 			advance_transaction(ec, false);</div><div class='del'>-			spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+			spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 		} while (time_before(jiffies, delay));</div><div class='ctx'> 		pr_debug("controller reset, restart transaction\n");</div><div class='del'>-		spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+		spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 		start_transaction(ec);</div><div class='del'>-		spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+		spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	return -ETIME;</div><div class='ctx'> }</div><div class='hunk'>@@ -780,11 +772,10 @@ static int ec_poll(struct acpi_ec *ec)</div><div class='ctx'> static int acpi_ec_transaction_unlocked(struct acpi_ec *ec,</div><div class='ctx'> 					struct transaction *t)</div><div class='ctx'> {</div><div class='del'>-	unsigned long tmp;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* start transaction */</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, tmp);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	/* Enable GPE for command processing (IBF=0/OBF=1) */</div><div class='ctx'> 	if (!acpi_ec_submit_flushable_request(ec)) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -795,11 +786,11 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec,</div><div class='ctx'> 	ec-&gt;curr = t;</div><div class='ctx'> 	ec_dbg_req("Command(%s) started", acpi_ec_cmd_string(t-&gt;command));</div><div class='ctx'> 	start_transaction(ec);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, tmp);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	ret = ec_poll(ec);</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, tmp);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (t-&gt;irq_count == ec_storm_threshold)</div><div class='ctx'> 		acpi_ec_unmask_events(ec);</div><div class='ctx'> 	ec_dbg_req("Command(%s) stopped", acpi_ec_cmd_string(t-&gt;command));</div><div class='hunk'>@@ -808,7 +799,7 @@ static int acpi_ec_transaction_unlocked(struct acpi_ec *ec,</div><div class='ctx'> 	acpi_ec_complete_request(ec);</div><div class='ctx'> 	ec_dbg_ref(ec, "Decrease command");</div><div class='ctx'> unlock:</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, tmp);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -936,9 +927,7 @@ EXPORT_SYMBOL(ec_get_handle);</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_start(struct acpi_ec *ec, bool resuming)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (!test_and_set_bit(EC_FLAGS_STARTED, &amp;ec-&gt;flags)) {</div><div class='ctx'> 		ec_dbg_drv("Starting EC");</div><div class='ctx'> 		/* Enable GPE for event processing (SCI_EVT=1) */</div><div class='hunk'>@@ -948,31 +937,28 @@ static void acpi_ec_start(struct acpi_ec *ec, bool resuming)</div><div class='ctx'> 		}</div><div class='ctx'> 		ec_log_drv("EC started");</div><div class='ctx'> 	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool acpi_ec_stopped(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	bool flushed;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	flushed = acpi_ec_flushed(ec);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 	return flushed;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_stop(struct acpi_ec *ec, bool suspending)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	if (acpi_ec_started(ec)) {</div><div class='ctx'> 		ec_dbg_drv("Stopping EC");</div><div class='ctx'> 		set_bit(EC_FLAGS_STOPPED, &amp;ec-&gt;flags);</div><div class='del'>-		spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+		spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> 		wait_event(ec-&gt;wait, acpi_ec_stopped(ec));</div><div class='del'>-		spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+		spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 		/* Disable GPE for event processing (SCI_EVT=1) */</div><div class='ctx'> 		if (!suspending) {</div><div class='ctx'> 			acpi_ec_complete_request(ec);</div><div class='hunk'>@@ -983,29 +969,25 @@ static void acpi_ec_stop(struct acpi_ec *ec, bool suspending)</div><div class='ctx'> 		clear_bit(EC_FLAGS_STOPPED, &amp;ec-&gt;flags);</div><div class='ctx'> 		ec_log_drv("EC stopped");</div><div class='ctx'> 	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_enter_noirq(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	ec-&gt;busy_polling = true;</div><div class='ctx'> 	ec-&gt;polling_guard = 0;</div><div class='ctx'> 	ec_log_drv("interrupt blocked");</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_leave_noirq(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	ec-&gt;busy_polling = ec_busy_polling;</div><div class='ctx'> 	ec-&gt;polling_guard = ec_polling_guard;</div><div class='ctx'> 	ec_log_drv("interrupt unblocked");</div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void acpi_ec_block_transactions(void)</div><div class='hunk'>@@ -1137,9 +1119,9 @@ static void acpi_ec_event_processor(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	ec_dbg_evt("Query(0x%02x) stopped", handler-&gt;query_bit);</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> 	ec-&gt;queries_in_progress--;</div><div class='del'>-	spin_unlock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	acpi_ec_put_query_handler(handler);</div><div class='ctx'> 	kfree(q);</div><div class='hunk'>@@ -1202,12 +1184,12 @@ static int acpi_ec_submit_query(struct acpi_ec *ec)</div><div class='ctx'> 	 */</div><div class='ctx'> 	ec_dbg_evt("Query(0x%02x) scheduled", value);</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	ec-&gt;queries_in_progress++;</div><div class='ctx'> 	queue_work(ec_query_wq, &amp;q-&gt;work);</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1223,14 +1205,14 @@ static void acpi_ec_event_handler(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	ec_dbg_evt("Event started");</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	while (ec-&gt;events_to_process) {</div><div class='del'>-		spin_unlock_irq(&amp;ec-&gt;lock);</div><div class='add'>+		spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		acpi_ec_submit_query(ec);</div><div class='ctx'> </div><div class='del'>-		spin_lock_irq(&amp;ec-&gt;lock);</div><div class='add'>+		spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		ec-&gt;events_to_process--;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1247,11 +1229,11 @@ static void acpi_ec_event_handler(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 		ec_dbg_evt("Event stopped");</div><div class='ctx'> </div><div class='del'>-		spin_unlock_irq(&amp;ec-&gt;lock);</div><div class='add'>+		spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		guard_timeout = !!ec_guard(ec);</div><div class='ctx'> </div><div class='del'>-		spin_lock_irq(&amp;ec-&gt;lock);</div><div class='add'>+		spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		/* Take care of SCI_EVT unless someone else is doing that. */</div><div class='ctx'> 		if (guard_timeout &amp;&amp; !ec-&gt;curr)</div><div class='hunk'>@@ -1264,7 +1246,7 @@ static void acpi_ec_event_handler(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	ec-&gt;events_in_progress--;</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irq(&amp;ec-&gt;lock);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void clear_gpe_and_advance_transaction(struct acpi_ec *ec, bool interrupt)</div><div class='hunk'>@@ -1289,13 +1271,11 @@ static void clear_gpe_and_advance_transaction(struct acpi_ec *ec, bool interrupt</div><div class='ctx'> </div><div class='ctx'> static void acpi_ec_handle_interrupt(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_lock(&amp;ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	clear_gpe_and_advance_transaction(ec, true);</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irqrestore(&amp;ec-&gt;lock, flags);</div><div class='add'>+	spin_unlock(&amp;ec-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 acpi_ec_gpe_handler(acpi_handle gpe_device,</div><div class='hunk'>@@ -1458,8 +1438,8 @@ static bool install_gpe_event_handler(struct acpi_ec *ec)</div><div class='ctx'> </div><div class='ctx'> static bool install_gpio_irq_event_handler(struct acpi_ec *ec)</div><div class='ctx'> {</div><div class='del'>-	return request_irq(ec-&gt;irq, acpi_ec_irq_handler, IRQF_SHARED,</div><div class='del'>-			   "ACPI EC", ec) &gt;= 0;</div><div class='add'>+	return request_threaded_irq(ec-&gt;irq, NULL, acpi_ec_irq_handler,</div><div class='add'>+				    IRQF_SHARED | IRQF_ONESHOT, "ACPI EC", ec) &gt;= 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2105,7 +2085,7 @@ bool acpi_ec_dispatch_gpe(void)</div><div class='ctx'> 	 * Dispatch the EC GPE in-band, but do not report wakeup in any case</div><div class='ctx'> 	 * to allow the caller to process events properly after that.</div><div class='ctx'> 	 */</div><div class='del'>-	spin_lock_irq(&amp;first_ec-&gt;lock);</div><div class='add'>+	spin_lock(&amp;first_ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (acpi_ec_gpe_status_set(first_ec)) {</div><div class='ctx'> 		pm_pr_dbg("ACPI EC GPE status set\n");</div><div class='hunk'>@@ -2114,7 +2094,7 @@ bool acpi_ec_dispatch_gpe(void)</div><div class='ctx'> 		work_in_progress = acpi_ec_work_in_progress(first_ec);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irq(&amp;first_ec-&gt;lock);</div><div class='add'>+	spin_unlock(&amp;first_ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (!work_in_progress)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -2127,11 +2107,11 @@ bool acpi_ec_dispatch_gpe(void)</div><div class='ctx'> </div><div class='ctx'> 		pm_pr_dbg("ACPI EC work flushed\n");</div><div class='ctx'> </div><div class='del'>-		spin_lock_irq(&amp;first_ec-&gt;lock);</div><div class='add'>+		spin_lock(&amp;first_ec-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		work_in_progress = acpi_ec_work_in_progress(first_ec);</div><div class='ctx'> </div><div class='del'>-		spin_unlock_irq(&amp;first_ec-&gt;lock);</div><div class='add'>+		spin_unlock(&amp;first_ec-&gt;lock);</div><div class='ctx'> 	} while (work_in_progress &amp;&amp; !pm_wakeup_pending());</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='head'>diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h<br/>index 866c7c4ed233..6588525c45ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/internal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/internal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/internal.h</a></div><div class='hunk'>@@ -85,6 +85,20 @@ bool acpi_scan_is_offline(struct acpi_device *adev, bool uevent);</div><div class='ctx'> acpi_status acpi_sysfs_table_handler(u32 event, void *table, void *context);</div><div class='ctx'> void acpi_scan_table_notify(void);</div><div class='ctx'> </div><div class='add'>+int acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp);</div><div class='add'>+int acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp);</div><div class='add'>+int acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp);</div><div class='add'>+int acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_ARM64</div><div class='add'>+int acpi_arch_thermal_cpufreq_pctg(void);</div><div class='add'>+#else</div><div class='add'>+static inline int acpi_arch_thermal_cpufreq_pctg(void)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /* --------------------------------------------------------------------------</div><div class='ctx'>                      Device Node Initialization / Removal</div><div class='ctx'>    -------------------------------------------------------------------------- */</div><div class='hunk'>@@ -148,8 +162,11 @@ int acpi_wakeup_device_init(void);</div><div class='ctx'> #ifdef CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC</div><div class='ctx'> void acpi_early_processor_control_setup(void);</div><div class='ctx'> void acpi_early_processor_set_pdc(void);</div><div class='del'>-</div><div class='add'>+#ifdef CONFIG_X86</div><div class='ctx'> void acpi_proc_quirk_mwait_check(void);</div><div class='add'>+#else</div><div class='add'>+static inline void acpi_proc_quirk_mwait_check(void) {}</div><div class='add'>+#endif</div><div class='ctx'> bool processor_physically_present(acpi_handle handle);</div><div class='ctx'> #else</div><div class='ctx'> static inline void acpi_early_processor_control_setup(void) {}</div><div class='hunk'>@@ -276,4 +293,13 @@ void acpi_init_lpit(void);</div><div class='ctx'> static inline void acpi_init_lpit(void) { }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+/*--------------------------------------------------------------------------</div><div class='add'>+		ACPI _CRS CSI-2 and MIPI DisCo for Imaging</div><div class='add'>+  -------------------------------------------------------------------------- */</div><div class='add'>+</div><div class='add'>+void acpi_mipi_check_crs_csi2(acpi_handle handle);</div><div class='add'>+void acpi_mipi_scan_crs_csi2(void);</div><div class='add'>+void acpi_mipi_init_crs_csi2_swnodes(void);</div><div class='add'>+void acpi_mipi_crs_csi2_cleanup(void);</div><div class='add'>+</div><div class='ctx'> #endif /* _ACPI_INTERNAL_H_ */</div><div class='head'>diff --git a/drivers/acpi/mipi-disco-img.c b/drivers/acpi/mipi-disco-img.c<br/>new file mode 100644<br/>index 000000000000..7286cf4579bc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/mipi-disco-img.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/mipi-disco-img.c</a></div><div class='hunk'>@@ -0,0 +1,725 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * MIPI DisCo for Imaging support.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Intel Corporation</div><div class='add'>+ *</div><div class='add'>+ * Support MIPI DisCo for Imaging by parsing ACPI _CRS CSI-2 records defined in</div><div class='add'>+ * Section 6.4.3.8.2.4 "Camera Serial Interface (CSI-2) Connection Resource</div><div class='add'>+ * Descriptor" of ACPI 6.5 and using device properties defined by the MIPI DisCo</div><div class='add'>+ * for Imaging specification.</div><div class='add'>+ *</div><div class='add'>+ * The implementation looks for the information in the ACPI namespace (CSI-2</div><div class='add'>+ * resource descriptors in _CRS) and constructs software nodes compatible with</div><div class='add'>+ * Documentation/firmware-guide/acpi/dsd/graph.rst to represent the CSI-2</div><div class='add'>+ * connection graph.  The software nodes are then populated with the data</div><div class='add'>+ * extracted from the _CRS CSI-2 resource descriptors and the MIPI DisCo</div><div class='add'>+ * for Imaging device properties present in _DSD for the ACPI device objects</div><div class='add'>+ * with CSI-2 connections.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/limits.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/overflow.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+</div><div class='add'>+#include "internal.h"</div><div class='add'>+</div><div class='add'>+static LIST_HEAD(acpi_mipi_crs_csi2_list);</div><div class='add'>+</div><div class='add'>+static void acpi_mipi_data_tag(acpi_handle handle, void *context)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Connection data extracted from one _CRS CSI-2 resource descriptor. */</div><div class='add'>+struct crs_csi2_connection {</div><div class='add'>+	struct list_head entry;</div><div class='add'>+	struct acpi_resource_csi2_serialbus csi2_data;</div><div class='add'>+	acpi_handle remote_handle;</div><div class='add'>+	char remote_name[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Data extracted from _CRS CSI-2 resource descriptors for one device. */</div><div class='add'>+struct crs_csi2 {</div><div class='add'>+	struct list_head entry;</div><div class='add'>+	acpi_handle handle;</div><div class='add'>+	struct acpi_device_software_nodes *swnodes;</div><div class='add'>+	struct list_head connections;</div><div class='add'>+	u32 port_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct csi2_resources_walk_data {</div><div class='add'>+	acpi_handle handle;</div><div class='add'>+	struct list_head connections;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static acpi_status parse_csi2_resource(struct acpi_resource *res, void *context)</div><div class='add'>+{</div><div class='add'>+	struct csi2_resources_walk_data *crwd = context;</div><div class='add'>+	struct acpi_resource_csi2_serialbus *csi2_res;</div><div class='add'>+	struct acpi_resource_source *csi2_res_src;</div><div class='add'>+	u16 csi2_res_src_length;</div><div class='add'>+	struct crs_csi2_connection *conn;</div><div class='add'>+	acpi_handle remote_handle;</div><div class='add'>+</div><div class='add'>+	if (res-&gt;type != ACPI_RESOURCE_TYPE_SERIAL_BUS)</div><div class='add'>+		return AE_OK;</div><div class='add'>+</div><div class='add'>+	csi2_res = &amp;res-&gt;data.csi2_serial_bus;</div><div class='add'>+</div><div class='add'>+	if (csi2_res-&gt;type != ACPI_RESOURCE_SERIAL_TYPE_CSI2)</div><div class='add'>+		return AE_OK;</div><div class='add'>+</div><div class='add'>+	csi2_res_src = &amp;csi2_res-&gt;resource_source;</div><div class='add'>+	if (ACPI_FAILURE(acpi_get_handle(NULL, csi2_res_src-&gt;string_ptr,</div><div class='add'>+					 &amp;remote_handle))) {</div><div class='add'>+		acpi_handle_debug(crwd-&gt;handle,</div><div class='add'>+				  "unable to find resource source\n");</div><div class='add'>+		return AE_OK;</div><div class='add'>+	}</div><div class='add'>+	csi2_res_src_length = csi2_res_src-&gt;string_length;</div><div class='add'>+	if (!csi2_res_src_length) {</div><div class='add'>+		acpi_handle_debug(crwd-&gt;handle,</div><div class='add'>+				  "invalid resource source string length\n");</div><div class='add'>+		return AE_OK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	conn = kmalloc(struct_size(conn, remote_name, csi2_res_src_length + 1),</div><div class='add'>+		       GFP_KERNEL);</div><div class='add'>+	if (!conn)</div><div class='add'>+		return AE_OK;</div><div class='add'>+</div><div class='add'>+	conn-&gt;csi2_data = *csi2_res;</div><div class='add'>+	strscpy(conn-&gt;remote_name, csi2_res_src-&gt;string_ptr, csi2_res_src_length);</div><div class='add'>+	conn-&gt;csi2_data.resource_source.string_ptr = conn-&gt;remote_name;</div><div class='add'>+	conn-&gt;remote_handle = remote_handle;</div><div class='add'>+</div><div class='add'>+	list_add(&amp;conn-&gt;entry, &amp;crwd-&gt;connections);</div><div class='add'>+</div><div class='add'>+	return AE_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct crs_csi2 *acpi_mipi_add_crs_csi2(acpi_handle handle,</div><div class='add'>+					       struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *csi2;</div><div class='add'>+</div><div class='add'>+	csi2 = kzalloc(sizeof(*csi2), GFP_KERNEL);</div><div class='add'>+	if (!csi2)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	csi2-&gt;handle = handle;</div><div class='add'>+	INIT_LIST_HEAD(&amp;csi2-&gt;connections);</div><div class='add'>+	csi2-&gt;port_count = 1;</div><div class='add'>+</div><div class='add'>+	if (ACPI_FAILURE(acpi_attach_data(handle, acpi_mipi_data_tag, csi2))) {</div><div class='add'>+		kfree(csi2);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_add(&amp;csi2-&gt;entry, list);</div><div class='add'>+</div><div class='add'>+	return csi2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct crs_csi2 *acpi_mipi_get_crs_csi2(acpi_handle handle)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *csi2;</div><div class='add'>+</div><div class='add'>+	if (ACPI_FAILURE(acpi_get_data_full(handle, acpi_mipi_data_tag,</div><div class='add'>+					    (void **)&amp;csi2, NULL)))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return csi2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void csi_csr2_release_connections(struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2_connection *conn, *conn_tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(conn, conn_tmp, list, entry) {</div><div class='add'>+		list_del(&amp;conn-&gt;entry);</div><div class='add'>+		kfree(conn);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void acpi_mipi_del_crs_csi2(struct crs_csi2 *csi2)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;csi2-&gt;entry);</div><div class='add'>+	acpi_detach_data(csi2-&gt;handle, acpi_mipi_data_tag);</div><div class='add'>+	kfree(csi2-&gt;swnodes);</div><div class='add'>+	csi_csr2_release_connections(&amp;csi2-&gt;connections);</div><div class='add'>+	kfree(csi2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * acpi_mipi_check_crs_csi2 - Look for CSI-2 resources in _CRS</div><div class='add'>+ * @handle: Device object handle to evaluate _CRS for.</div><div class='add'>+ *</div><div class='add'>+ * Find all CSI-2 resource descriptors in the given device's _CRS</div><div class='add'>+ * and collect them into a list.</div><div class='add'>+ */</div><div class='add'>+void acpi_mipi_check_crs_csi2(acpi_handle handle)</div><div class='add'>+{</div><div class='add'>+	struct csi2_resources_walk_data crwd = {</div><div class='add'>+		.handle = handle,</div><div class='add'>+		.connections = LIST_HEAD_INIT(crwd.connections),</div><div class='add'>+	};</div><div class='add'>+	struct crs_csi2 *csi2;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Avoid allocating _CRS CSI-2 objects for devices without any CSI-2</div><div class='add'>+	 * resource descriptions in _CRS to reduce overhead.</div><div class='add'>+	 */</div><div class='add'>+	acpi_walk_resources(handle, METHOD_NAME__CRS, parse_csi2_resource, &amp;crwd);</div><div class='add'>+	if (list_empty(&amp;crwd.connections))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Create a _CRS CSI-2 entry to store the extracted connection</div><div class='add'>+	 * information and add it to the global list.</div><div class='add'>+	 */</div><div class='add'>+	csi2 = acpi_mipi_add_crs_csi2(handle, &amp;acpi_mipi_crs_csi2_list);</div><div class='add'>+	if (!csi2) {</div><div class='add'>+		csi_csr2_release_connections(&amp;crwd.connections);</div><div class='add'>+		return; /* Nothing really can be done about this. */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_replace(&amp;crwd.connections, &amp;csi2-&gt;connections);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define NO_CSI2_PORT (UINT_MAX - 1)</div><div class='add'>+</div><div class='add'>+static void alloc_crs_csi2_swnodes(struct crs_csi2 *csi2)</div><div class='add'>+{</div><div class='add'>+	size_t port_count = csi2-&gt;port_count;</div><div class='add'>+	struct acpi_device_software_nodes *swnodes;</div><div class='add'>+	size_t alloc_size;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Allocate memory for ports, node pointers (number of nodes +</div><div class='add'>+	 * 1 (guardian), nodes (root + number of ports * 2 (because for</div><div class='add'>+	 * every port there is an endpoint)).</div><div class='add'>+	 */</div><div class='add'>+	if (check_mul_overflow(sizeof(*swnodes-&gt;ports) +</div><div class='add'>+			       sizeof(*swnodes-&gt;nodes) * 2 +</div><div class='add'>+			       sizeof(*swnodes-&gt;nodeptrs) * 2,</div><div class='add'>+			       port_count, &amp;alloc_size) ||</div><div class='add'>+	    check_add_overflow(sizeof(*swnodes) +</div><div class='add'>+			       sizeof(*swnodes-&gt;nodes) +</div><div class='add'>+			       sizeof(*swnodes-&gt;nodeptrs) * 2,</div><div class='add'>+			       alloc_size, &amp;alloc_size)) {</div><div class='add'>+		acpi_handle_info(csi2-&gt;handle,</div><div class='add'>+				 "too many _CRS CSI-2 resource handles (%zu)",</div><div class='add'>+				 port_count);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	swnodes = kmalloc(alloc_size, GFP_KERNEL);</div><div class='add'>+	if (!swnodes)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	swnodes-&gt;ports = (struct acpi_device_software_node_port *)(swnodes + 1);</div><div class='add'>+	swnodes-&gt;nodes = (struct software_node *)(swnodes-&gt;ports + port_count);</div><div class='add'>+	swnodes-&gt;nodeptrs = (const struct software_node **)(swnodes-&gt;nodes + 1 +</div><div class='add'>+				2 * port_count);</div><div class='add'>+	swnodes-&gt;num_ports = port_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 2 * port_count + 1; i++)</div><div class='add'>+		swnodes-&gt;nodeptrs[i] = &amp;swnodes-&gt;nodes[i];</div><div class='add'>+</div><div class='add'>+	swnodes-&gt;nodeptrs[i] = NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; port_count; i++)</div><div class='add'>+		swnodes-&gt;ports[i].port_nr = NO_CSI2_PORT;</div><div class='add'>+</div><div class='add'>+	csi2-&gt;swnodes = swnodes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define ACPI_CRS_CSI2_PHY_TYPE_C	0</div><div class='add'>+#define ACPI_CRS_CSI2_PHY_TYPE_D	1</div><div class='add'>+</div><div class='add'>+static unsigned int next_csi2_port_index(struct acpi_device_software_nodes *swnodes,</div><div class='add'>+					 unsigned int port_nr)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; swnodes-&gt;num_ports; i++) {</div><div class='add'>+		struct acpi_device_software_node_port *port = &amp;swnodes-&gt;ports[i];</div><div class='add'>+</div><div class='add'>+		if (port-&gt;port_nr == port_nr)</div><div class='add'>+			return i;</div><div class='add'>+</div><div class='add'>+		if (port-&gt;port_nr == NO_CSI2_PORT) {</div><div class='add'>+			port-&gt;port_nr = port_nr;</div><div class='add'>+			return i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NO_CSI2_PORT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Print graph port name into a buffer, return non-zero on failure. */</div><div class='add'>+#define GRAPH_PORT_NAME(var, num)					    \</div><div class='add'>+	(snprintf((var), sizeof(var), SWNODE_GRAPH_PORT_NAME_FMT, (num)) &gt;= \</div><div class='add'>+	 sizeof(var))</div><div class='add'>+</div><div class='add'>+static void extract_crs_csi2_conn_info(acpi_handle local_handle,</div><div class='add'>+				       struct acpi_device_software_nodes *local_swnodes,</div><div class='add'>+				       struct crs_csi2_connection *conn)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *remote_csi2 = acpi_mipi_get_crs_csi2(conn-&gt;remote_handle);</div><div class='add'>+	struct acpi_device_software_nodes *remote_swnodes;</div><div class='add'>+	struct acpi_device_software_node_port *local_port, *remote_port;</div><div class='add'>+	struct software_node *local_node, *remote_node;</div><div class='add'>+	unsigned int local_index, remote_index;</div><div class='add'>+	unsigned int bus_type;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If the previous steps have failed to make room for a _CRS CSI-2</div><div class='add'>+	 * representation for the remote end of the given connection, skip it.</div><div class='add'>+	 */</div><div class='add'>+	if (!remote_csi2)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	remote_swnodes = remote_csi2-&gt;swnodes;</div><div class='add'>+	if (!remote_swnodes)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (conn-&gt;csi2_data.phy_type) {</div><div class='add'>+	case ACPI_CRS_CSI2_PHY_TYPE_C:</div><div class='add'>+		bus_type = V4L2_FWNODE_BUS_TYPE_CSI2_CPHY;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case ACPI_CRS_CSI2_PHY_TYPE_D:</div><div class='add'>+		bus_type = V4L2_FWNODE_BUS_TYPE_CSI2_DPHY;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		acpi_handle_info(local_handle, "unknown CSI-2 PHY type %u\n",</div><div class='add'>+				 conn-&gt;csi2_data.phy_type);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	local_index = next_csi2_port_index(local_swnodes,</div><div class='add'>+					   conn-&gt;csi2_data.local_port_instance);</div><div class='add'>+	if (WARN_ON_ONCE(local_index &gt;= local_swnodes-&gt;num_ports))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	remote_index = next_csi2_port_index(remote_swnodes,</div><div class='add'>+					    conn-&gt;csi2_data.resource_source.index);</div><div class='add'>+	if (WARN_ON_ONCE(remote_index &gt;= remote_swnodes-&gt;num_ports))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	local_port = &amp;local_swnodes-&gt;ports[local_index];</div><div class='add'>+	local_node = &amp;local_swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_EP(local_index)];</div><div class='add'>+	local_port-&gt;crs_csi2_local = true;</div><div class='add'>+</div><div class='add'>+	remote_port = &amp;remote_swnodes-&gt;ports[remote_index];</div><div class='add'>+	remote_node = &amp;remote_swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_EP(remote_index)];</div><div class='add'>+</div><div class='add'>+	local_port-&gt;remote_ep[0] = SOFTWARE_NODE_REFERENCE(remote_node);</div><div class='add'>+	remote_port-&gt;remote_ep[0] = SOFTWARE_NODE_REFERENCE(local_node);</div><div class='add'>+</div><div class='add'>+	local_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_REMOTE_EP] =</div><div class='add'>+			PROPERTY_ENTRY_REF_ARRAY("remote-endpoint",</div><div class='add'>+						 local_port-&gt;remote_ep);</div><div class='add'>+</div><div class='add'>+	local_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_BUS_TYPE] =</div><div class='add'>+			PROPERTY_ENTRY_U32("bus-type", bus_type);</div><div class='add'>+</div><div class='add'>+	local_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_REG] =</div><div class='add'>+			PROPERTY_ENTRY_U32("reg", 0);</div><div class='add'>+</div><div class='add'>+	local_port-&gt;port_props[ACPI_DEVICE_SWNODE_PORT_REG] =</div><div class='add'>+			PROPERTY_ENTRY_U32("reg", conn-&gt;csi2_data.local_port_instance);</div><div class='add'>+</div><div class='add'>+	if (GRAPH_PORT_NAME(local_port-&gt;port_name,</div><div class='add'>+			    conn-&gt;csi2_data.local_port_instance))</div><div class='add'>+		acpi_handle_info(local_handle, "local port %u name too long",</div><div class='add'>+				 conn-&gt;csi2_data.local_port_instance);</div><div class='add'>+</div><div class='add'>+	remote_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_REMOTE_EP] =</div><div class='add'>+			PROPERTY_ENTRY_REF_ARRAY("remote-endpoint",</div><div class='add'>+						 remote_port-&gt;remote_ep);</div><div class='add'>+</div><div class='add'>+	remote_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_BUS_TYPE] =</div><div class='add'>+			PROPERTY_ENTRY_U32("bus-type", bus_type);</div><div class='add'>+</div><div class='add'>+	remote_port-&gt;ep_props[ACPI_DEVICE_SWNODE_EP_REG] =</div><div class='add'>+			PROPERTY_ENTRY_U32("reg", 0);</div><div class='add'>+</div><div class='add'>+	remote_port-&gt;port_props[ACPI_DEVICE_SWNODE_PORT_REG] =</div><div class='add'>+			PROPERTY_ENTRY_U32("reg", conn-&gt;csi2_data.resource_source.index);</div><div class='add'>+</div><div class='add'>+	if (GRAPH_PORT_NAME(remote_port-&gt;port_name,</div><div class='add'>+			    conn-&gt;csi2_data.resource_source.index))</div><div class='add'>+		acpi_handle_info(local_handle, "remote port %u name too long",</div><div class='add'>+				 conn-&gt;csi2_data.resource_source.index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void prepare_crs_csi2_swnodes(struct crs_csi2 *csi2)</div><div class='add'>+{</div><div class='add'>+	struct acpi_device_software_nodes *local_swnodes = csi2-&gt;swnodes;</div><div class='add'>+	acpi_handle local_handle = csi2-&gt;handle;</div><div class='add'>+	struct crs_csi2_connection *conn;</div><div class='add'>+</div><div class='add'>+	/* Bail out if the allocation of swnodes has failed. */</div><div class='add'>+	if (!local_swnodes)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(conn, &amp;csi2-&gt;connections, entry)</div><div class='add'>+		extract_crs_csi2_conn_info(local_handle, local_swnodes, conn);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * acpi_mipi_scan_crs_csi2 - Create ACPI _CRS CSI-2 software nodes</div><div class='add'>+ *</div><div class='add'>+ * Note that this function must be called before any struct acpi_device objects</div><div class='add'>+ * are bound to any ACPI drivers or scan handlers, so it cannot assume the</div><div class='add'>+ * existence of struct acpi_device objects for every device present in the ACPI</div><div class='add'>+ * namespace.</div><div class='add'>+ *</div><div class='add'>+ * acpi_scan_lock in scan.c must be held when calling this function.</div><div class='add'>+ */</div><div class='add'>+void acpi_mipi_scan_crs_csi2(void)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *csi2;</div><div class='add'>+	LIST_HEAD(aux_list);</div><div class='add'>+</div><div class='add'>+	/* Count references to each ACPI handle in the CSI-2 connection graph. */</div><div class='add'>+	list_for_each_entry(csi2, &amp;acpi_mipi_crs_csi2_list, entry) {</div><div class='add'>+		struct crs_csi2_connection *conn;</div><div class='add'>+</div><div class='add'>+		list_for_each_entry(conn, &amp;csi2-&gt;connections, entry) {</div><div class='add'>+			struct crs_csi2 *remote_csi2;</div><div class='add'>+</div><div class='add'>+			csi2-&gt;port_count++;</div><div class='add'>+</div><div class='add'>+			remote_csi2 = acpi_mipi_get_crs_csi2(conn-&gt;remote_handle);</div><div class='add'>+			if (remote_csi2) {</div><div class='add'>+				remote_csi2-&gt;port_count++;</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+			/*</div><div class='add'>+			 * The remote endpoint has no _CRS CSI-2 list entry yet,</div><div class='add'>+			 * so create one for it and add it to the list.</div><div class='add'>+			 */</div><div class='add'>+			acpi_mipi_add_crs_csi2(conn-&gt;remote_handle, &amp;aux_list);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	list_splice(&amp;aux_list, &amp;acpi_mipi_crs_csi2_list);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Allocate software nodes for representing the CSI-2 information.</div><div class='add'>+	 *</div><div class='add'>+	 * This needs to be done for all of the list entries in one go, because</div><div class='add'>+	 * they may point to each other without restrictions and the next step</div><div class='add'>+	 * relies on the availability of swnodes memory for each list entry.</div><div class='add'>+	 */</div><div class='add'>+	list_for_each_entry(csi2, &amp;acpi_mipi_crs_csi2_list, entry)</div><div class='add'>+		alloc_crs_csi2_swnodes(csi2);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set up software node properties using data from _CRS CSI-2 resource</div><div class='add'>+	 * descriptors.</div><div class='add'>+	 */</div><div class='add'>+	list_for_each_entry(csi2, &amp;acpi_mipi_crs_csi2_list, entry)</div><div class='add'>+		prepare_crs_csi2_swnodes(csi2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Get the index of the next property in the property array, with a given</div><div class='add'>+ * maximum value.</div><div class='add'>+ */</div><div class='add'>+#define NEXT_PROPERTY(index, max)			\</div><div class='add'>+	(WARN_ON((index) &gt; ACPI_DEVICE_SWNODE_##max) ?	\</div><div class='add'>+	 ACPI_DEVICE_SWNODE_##max : (index)++)</div><div class='add'>+</div><div class='add'>+static void init_csi2_port_local(struct acpi_device *adev,</div><div class='add'>+				 struct acpi_device_software_node_port *port,</div><div class='add'>+				 struct fwnode_handle *port_fwnode,</div><div class='add'>+				 unsigned int index)</div><div class='add'>+{</div><div class='add'>+	acpi_handle handle = acpi_device_handle(adev);</div><div class='add'>+	unsigned int num_link_freqs;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_count_u64(port_fwnode, "mipi-img-link-frequencies");</div><div class='add'>+	if (ret &lt;= 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	num_link_freqs = ret;</div><div class='add'>+	if (num_link_freqs &gt; ACPI_DEVICE_CSI2_DATA_LANES) {</div><div class='add'>+		acpi_handle_info(handle, "Too many link frequencies: %u\n",</div><div class='add'>+				 num_link_freqs);</div><div class='add'>+		num_link_freqs = ACPI_DEVICE_CSI2_DATA_LANES;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_read_u64_array(port_fwnode,</div><div class='add'>+					     "mipi-img-link-frequencies",</div><div class='add'>+					     port-&gt;link_frequencies,</div><div class='add'>+					     num_link_freqs);</div><div class='add'>+	if (ret) {</div><div class='add'>+		acpi_handle_info(handle, "Unable to get link frequencies (%d)\n",</div><div class='add'>+				 ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	port-&gt;ep_props[NEXT_PROPERTY(index, EP_LINK_FREQUENCIES)] =</div><div class='add'>+				PROPERTY_ENTRY_U64_ARRAY_LEN("link-frequencies",</div><div class='add'>+							     port-&gt;link_frequencies,</div><div class='add'>+							     num_link_freqs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_csi2_port(struct acpi_device *adev,</div><div class='add'>+			   struct acpi_device_software_nodes *swnodes,</div><div class='add'>+			   struct acpi_device_software_node_port *port,</div><div class='add'>+			   struct fwnode_handle *port_fwnode,</div><div class='add'>+			   unsigned int port_index)</div><div class='add'>+{</div><div class='add'>+	unsigned int ep_prop_index = ACPI_DEVICE_SWNODE_EP_CLOCK_LANES;</div><div class='add'>+	acpi_handle handle = acpi_device_handle(adev);</div><div class='add'>+	u8 val[ACPI_DEVICE_CSI2_DATA_LANES];</div><div class='add'>+	int num_lanes = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (GRAPH_PORT_NAME(port-&gt;port_name, port-&gt;port_nr))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_PORT(port_index)] =</div><div class='add'>+			SOFTWARE_NODE(port-&gt;port_name, port-&gt;port_props,</div><div class='add'>+				      &amp;swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_ROOT]);</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_read_u8(port_fwnode, "mipi-img-clock-lane", val);</div><div class='add'>+	if (!ret)</div><div class='add'>+		port-&gt;ep_props[NEXT_PROPERTY(ep_prop_index, EP_CLOCK_LANES)] =</div><div class='add'>+			PROPERTY_ENTRY_U32("clock-lanes", val[0]);</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_count_u8(port_fwnode, "mipi-img-data-lanes");</div><div class='add'>+	if (ret &gt; 0) {</div><div class='add'>+		num_lanes = ret;</div><div class='add'>+</div><div class='add'>+		if (num_lanes &gt; ACPI_DEVICE_CSI2_DATA_LANES) {</div><div class='add'>+			acpi_handle_info(handle, "Too many data lanes: %u\n",</div><div class='add'>+					 num_lanes);</div><div class='add'>+			num_lanes = ACPI_DEVICE_CSI2_DATA_LANES;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = fwnode_property_read_u8_array(port_fwnode,</div><div class='add'>+						    "mipi-img-data-lanes",</div><div class='add'>+						    val, num_lanes);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			unsigned int i;</div><div class='add'>+</div><div class='add'>+			for (i = 0; i &lt; num_lanes; i++)</div><div class='add'>+				port-&gt;data_lanes[i] = val[i];</div><div class='add'>+</div><div class='add'>+			port-&gt;ep_props[NEXT_PROPERTY(ep_prop_index, EP_DATA_LANES)] =</div><div class='add'>+				PROPERTY_ENTRY_U32_ARRAY_LEN("data-lanes",</div><div class='add'>+							     port-&gt;data_lanes,</div><div class='add'>+							     num_lanes);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_count_u8(port_fwnode, "mipi-img-lane-polarities");</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		acpi_handle_debug(handle, "Lane polarity bytes missing\n");</div><div class='add'>+	} else if (ret * BITS_PER_TYPE(u8) &lt; num_lanes + 1) {</div><div class='add'>+		acpi_handle_info(handle, "Too few lane polarity bits (%zu vs. %d)\n",</div><div class='add'>+				 ret * BITS_PER_TYPE(u8), num_lanes + 1);</div><div class='add'>+	} else {</div><div class='add'>+		unsigned long mask = 0;</div><div class='add'>+		int byte_count = ret;</div><div class='add'>+		unsigned int i;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The total number of lanes is ACPI_DEVICE_CSI2_DATA_LANES + 1</div><div class='add'>+		 * (data lanes + clock lane).  It is not expected to ever be</div><div class='add'>+		 * greater than the number of bits in an unsigned long</div><div class='add'>+		 * variable, but ensure that this is the case.</div><div class='add'>+		 */</div><div class='add'>+		BUILD_BUG_ON(BITS_PER_TYPE(unsigned long) &lt;= ACPI_DEVICE_CSI2_DATA_LANES);</div><div class='add'>+</div><div class='add'>+		if (byte_count &gt; sizeof(mask)) {</div><div class='add'>+			acpi_handle_info(handle, "Too many lane polarities: %d\n",</div><div class='add'>+					 byte_count);</div><div class='add'>+			byte_count = sizeof(mask);</div><div class='add'>+		}</div><div class='add'>+		fwnode_property_read_u8_array(port_fwnode, "mipi-img-lane-polarities",</div><div class='add'>+					      val, byte_count);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; byte_count; i++)</div><div class='add'>+			mask |= (unsigned long)val[i] &lt;&lt; BITS_PER_TYPE(u8) * i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt;= num_lanes; i++)</div><div class='add'>+			port-&gt;lane_polarities[i] = test_bit(i, &amp;mask);</div><div class='add'>+</div><div class='add'>+		port-&gt;ep_props[NEXT_PROPERTY(ep_prop_index, EP_LANE_POLARITIES)] =</div><div class='add'>+				PROPERTY_ENTRY_U32_ARRAY_LEN("lane-polarities",</div><div class='add'>+							     port-&gt;lane_polarities,</div><div class='add'>+							     num_lanes + 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_EP(port_index)] =</div><div class='add'>+		SOFTWARE_NODE("endpoint@0", swnodes-&gt;ports[port_index].ep_props,</div><div class='add'>+			      &amp;swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_PORT(port_index)]);</div><div class='add'>+</div><div class='add'>+	if (port-&gt;crs_csi2_local)</div><div class='add'>+		init_csi2_port_local(adev, port, port_fwnode, ep_prop_index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MIPI_IMG_PORT_PREFIX "mipi-img-port-"</div><div class='add'>+</div><div class='add'>+static struct fwnode_handle *get_mipi_port_handle(struct fwnode_handle *adev_fwnode,</div><div class='add'>+						  unsigned int port_nr)</div><div class='add'>+{</div><div class='add'>+	char port_name[sizeof(MIPI_IMG_PORT_PREFIX) + 2];</div><div class='add'>+</div><div class='add'>+	if (snprintf(port_name, sizeof(port_name), "%s%u",</div><div class='add'>+		     MIPI_IMG_PORT_PREFIX, port_nr) &gt;= sizeof(port_name))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return fwnode_get_named_child_node(adev_fwnode, port_name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_crs_csi2_swnodes(struct crs_csi2 *csi2)</div><div class='add'>+{</div><div class='add'>+	struct acpi_buffer buffer = { .length = ACPI_ALLOCATE_BUFFER };</div><div class='add'>+	struct acpi_device_software_nodes *swnodes = csi2-&gt;swnodes;</div><div class='add'>+	acpi_handle handle = csi2-&gt;handle;</div><div class='add'>+	unsigned int prop_index = 0;</div><div class='add'>+	struct fwnode_handle *adev_fwnode;</div><div class='add'>+	struct acpi_device *adev;</div><div class='add'>+	acpi_status status;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Bail out if the swnodes are not available (either they have not been</div><div class='add'>+	 * allocated or they have been assigned to the device already).</div><div class='add'>+	 */</div><div class='add'>+	if (!swnodes)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	adev = acpi_fetch_acpi_dev(handle);</div><div class='add'>+	if (!adev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	adev_fwnode = acpi_fwnode_handle(adev);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If the "rotation" property is not present, but _PLD is there,</div><div class='add'>+	 * evaluate it to get the "rotation" value.</div><div class='add'>+	 */</div><div class='add'>+	if (!fwnode_property_present(adev_fwnode, "rotation")) {</div><div class='add'>+		struct acpi_pld_info *pld;</div><div class='add'>+</div><div class='add'>+		status = acpi_get_physical_device_location(handle, &amp;pld);</div><div class='add'>+		if (ACPI_SUCCESS(status)) {</div><div class='add'>+			swnodes-&gt;dev_props[NEXT_PROPERTY(prop_index, DEV_ROTATION)] =</div><div class='add'>+					PROPERTY_ENTRY_U32("rotation",</div><div class='add'>+							   pld-&gt;rotation * 45U);</div><div class='add'>+			kfree(pld);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-clock-frequency", &amp;val))</div><div class='add'>+		swnodes-&gt;dev_props[NEXT_PROPERTY(prop_index, DEV_CLOCK_FREQUENCY)] =</div><div class='add'>+			PROPERTY_ENTRY_U32("clock-frequency", val);</div><div class='add'>+</div><div class='add'>+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-led-max-current", &amp;val))</div><div class='add'>+		swnodes-&gt;dev_props[NEXT_PROPERTY(prop_index, DEV_LED_MAX_MICROAMP)] =</div><div class='add'>+			PROPERTY_ENTRY_U32("led-max-microamp", val);</div><div class='add'>+</div><div class='add'>+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-flash-max-current", &amp;val))</div><div class='add'>+		swnodes-&gt;dev_props[NEXT_PROPERTY(prop_index, DEV_FLASH_MAX_MICROAMP)] =</div><div class='add'>+			PROPERTY_ENTRY_U32("flash-max-microamp", val);</div><div class='add'>+</div><div class='add'>+	if (!fwnode_property_read_u32(adev_fwnode, "mipi-img-flash-max-timeout-us", &amp;val))</div><div class='add'>+		swnodes-&gt;dev_props[NEXT_PROPERTY(prop_index, DEV_FLASH_MAX_TIMEOUT_US)] =</div><div class='add'>+			PROPERTY_ENTRY_U32("flash-max-timeout-us", val);</div><div class='add'>+</div><div class='add'>+	status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &amp;buffer);</div><div class='add'>+	if (ACPI_FAILURE(status)) {</div><div class='add'>+		acpi_handle_info(handle, "Unable to get the path name\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	swnodes-&gt;nodes[ACPI_DEVICE_SWNODE_ROOT] =</div><div class='add'>+			SOFTWARE_NODE(buffer.pointer, swnodes-&gt;dev_props, NULL);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; swnodes-&gt;num_ports; i++) {</div><div class='add'>+		struct acpi_device_software_node_port *port = &amp;swnodes-&gt;ports[i];</div><div class='add'>+		struct fwnode_handle *port_fwnode;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The MIPI DisCo for Imaging specification defines _DSD device</div><div class='add'>+		 * properties for providing CSI-2 port parameters that can be</div><div class='add'>+		 * accessed through the generic device properties framework.  To</div><div class='add'>+		 * access them, it is first necessary to find the data node</div><div class='add'>+		 * representing the port under the given ACPI device object.</div><div class='add'>+		 */</div><div class='add'>+		port_fwnode = get_mipi_port_handle(adev_fwnode, port-&gt;port_nr);</div><div class='add'>+		if (!port_fwnode) {</div><div class='add'>+			acpi_handle_info(handle,</div><div class='add'>+					 "MIPI port name too long for port %u\n",</div><div class='add'>+					 port-&gt;port_nr);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		init_csi2_port(adev, swnodes, port, port_fwnode, i);</div><div class='add'>+</div><div class='add'>+		fwnode_handle_put(port_fwnode);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = software_node_register_node_group(swnodes-&gt;nodeptrs);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		acpi_handle_info(handle,</div><div class='add'>+				 "Unable to register software nodes (%d)\n", ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	adev-&gt;swnodes = swnodes;</div><div class='add'>+	adev_fwnode-&gt;secondary = software_node_fwnode(swnodes-&gt;nodes);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Prevents the swnodes from this csi2 entry from being assigned again</div><div class='add'>+	 * or freed prematurely.</div><div class='add'>+	 */</div><div class='add'>+	csi2-&gt;swnodes = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * acpi_mipi_init_crs_csi2_swnodes - Initialize _CRS CSI-2 software nodes</div><div class='add'>+ *</div><div class='add'>+ * Use MIPI DisCo for Imaging device properties to finalize the initialization</div><div class='add'>+ * of CSI-2 software nodes for all ACPI device objects that have been already</div><div class='add'>+ * enumerated.</div><div class='add'>+ */</div><div class='add'>+void acpi_mipi_init_crs_csi2_swnodes(void)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *csi2, *csi2_tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(csi2, csi2_tmp, &amp;acpi_mipi_crs_csi2_list, entry)</div><div class='add'>+		init_crs_csi2_swnodes(csi2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * acpi_mipi_crs_csi2_cleanup - Free _CRS CSI-2 temporary data</div><div class='add'>+ */</div><div class='add'>+void acpi_mipi_crs_csi2_cleanup(void)</div><div class='add'>+{</div><div class='add'>+	struct crs_csi2 *csi2, *csi2_tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(csi2, csi2_tmp, &amp;acpi_mipi_crs_csi2_list, entry)</div><div class='add'>+		acpi_mipi_del_crs_csi2(csi2);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/acpi/nfit/core.c b/drivers/acpi/nfit/core.c<br/>index 992385537757..802f8a56d1fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/nfit/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/nfit/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/nfit/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/nfit/core.c</a></div><div class='hunk'>@@ -1186,7 +1186,7 @@ static ssize_t bus_dsm_mask_show(struct device *dev,</div><div class='ctx'> 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);</div><div class='ctx'> 	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%#lx\n", acpi_desc-&gt;bus_dsm_mask);</div><div class='add'>+	return sysfs_emit(buf, "%#lx\n", acpi_desc-&gt;bus_dsm_mask);</div><div class='ctx'> }</div><div class='ctx'> static struct device_attribute dev_attr_bus_dsm_mask =</div><div class='ctx'> 		__ATTR(dsm_mask, 0444, bus_dsm_mask_show, NULL);</div><div class='hunk'>@@ -1198,7 +1198,7 @@ static ssize_t revision_show(struct device *dev,</div><div class='ctx'> 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);</div><div class='ctx'> 	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", acpi_desc-&gt;acpi_header.revision);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", acpi_desc-&gt;acpi_header.revision);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(revision);</div><div class='ctx'> </div><div class='hunk'>@@ -1209,7 +1209,7 @@ static ssize_t hw_error_scrub_show(struct device *dev,</div><div class='ctx'> 	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);</div><div class='ctx'> 	struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", acpi_desc-&gt;scrub_mode);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", acpi_desc-&gt;scrub_mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1278,7 +1278,7 @@ static ssize_t scrub_show(struct device *dev,</div><div class='ctx'> 	mutex_lock(&amp;acpi_desc-&gt;init_mutex);</div><div class='ctx'> 	busy = test_bit(ARS_BUSY, &amp;acpi_desc-&gt;scrub_flags)</div><div class='ctx'> 		&amp;&amp; !test_bit(ARS_CANCEL, &amp;acpi_desc-&gt;scrub_flags);</div><div class='del'>-	rc = sprintf(buf, "%d%s", acpi_desc-&gt;scrub_count, busy ? "+\n" : "\n");</div><div class='add'>+	rc = sysfs_emit(buf, "%d%s", acpi_desc-&gt;scrub_count, busy ? "+\n" : "\n");</div><div class='ctx'> 	/* Allow an admin to poll the busy state at a higher rate */</div><div class='ctx'> 	if (busy &amp;&amp; capable(CAP_SYS_RAWIO) &amp;&amp; !test_and_set_bit(ARS_POLL,</div><div class='ctx'> 				&amp;acpi_desc-&gt;scrub_flags)) {</div><div class='hunk'>@@ -1382,7 +1382,7 @@ static ssize_t handle_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%#x\n", memdev-&gt;device_handle);</div><div class='add'>+	return sysfs_emit(buf, "%#x\n", memdev-&gt;device_handle);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(handle);</div><div class='ctx'> </div><div class='hunk'>@@ -1391,7 +1391,7 @@ static ssize_t phys_id_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%#x\n", memdev-&gt;physical_id);</div><div class='add'>+	return sysfs_emit(buf, "%#x\n", memdev-&gt;physical_id);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(phys_id);</div><div class='ctx'> </div><div class='hunk'>@@ -1400,7 +1400,7 @@ static ssize_t vendor_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;vendor_id));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;vendor_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(vendor);</div><div class='ctx'> </div><div class='hunk'>@@ -1409,7 +1409,7 @@ static ssize_t rev_id_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;revision_id));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;revision_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(rev_id);</div><div class='ctx'> </div><div class='hunk'>@@ -1418,7 +1418,7 @@ static ssize_t device_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;device_id));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;device_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(device);</div><div class='ctx'> </div><div class='hunk'>@@ -1427,7 +1427,7 @@ static ssize_t subsystem_vendor_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;subsystem_vendor_id));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;subsystem_vendor_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(subsystem_vendor);</div><div class='ctx'> </div><div class='hunk'>@@ -1436,7 +1436,7 @@ static ssize_t subsystem_rev_id_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n",</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n",</div><div class='ctx'> 			be16_to_cpu(dcr-&gt;subsystem_revision_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(subsystem_rev_id);</div><div class='hunk'>@@ -1446,7 +1446,7 @@ static ssize_t subsystem_device_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;subsystem_device_id));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", be16_to_cpu(dcr-&gt;subsystem_device_id));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(subsystem_device);</div><div class='ctx'> </div><div class='hunk'>@@ -1465,7 +1465,7 @@ static ssize_t format_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", le16_to_cpu(dcr-&gt;code));</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", le16_to_cpu(dcr-&gt;code));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(format);</div><div class='ctx'> </div><div class='hunk'>@@ -1498,7 +1498,7 @@ static ssize_t format1_show(struct device *dev,</div><div class='ctx'> 				continue;</div><div class='ctx'> 			if (nfit_dcr-&gt;dcr-&gt;code == dcr-&gt;code)</div><div class='ctx'> 				continue;</div><div class='del'>-			rc = sprintf(buf, "0x%04x\n",</div><div class='add'>+			rc = sysfs_emit(buf, "0x%04x\n",</div><div class='ctx'> 					le16_to_cpu(nfit_dcr-&gt;dcr-&gt;code));</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1515,7 +1515,7 @@ static ssize_t formats_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct nvdimm *nvdimm = to_nvdimm(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", num_nvdimm_formats(nvdimm));</div><div class='add'>+	return sysfs_emit(buf, "%d\n", num_nvdimm_formats(nvdimm));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(formats);</div><div class='ctx'> </div><div class='hunk'>@@ -1524,7 +1524,7 @@ static ssize_t serial_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%08x\n", be32_to_cpu(dcr-&gt;serial_number));</div><div class='add'>+	return sysfs_emit(buf, "0x%08x\n", be32_to_cpu(dcr-&gt;serial_number));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(serial);</div><div class='ctx'> </div><div class='hunk'>@@ -1536,7 +1536,7 @@ static ssize_t family_show(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	if (nfit_mem-&gt;family &lt; 0)</div><div class='ctx'> 		return -ENXIO;</div><div class='del'>-	return sprintf(buf, "%d\n", nfit_mem-&gt;family);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", nfit_mem-&gt;family);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(family);</div><div class='ctx'> </div><div class='hunk'>@@ -1548,7 +1548,7 @@ static ssize_t dsm_mask_show(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	if (nfit_mem-&gt;family &lt; 0)</div><div class='ctx'> 		return -ENXIO;</div><div class='del'>-	return sprintf(buf, "%#lx\n", nfit_mem-&gt;dsm_mask);</div><div class='add'>+	return sysfs_emit(buf, "%#lx\n", nfit_mem-&gt;dsm_mask);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(dsm_mask);</div><div class='ctx'> </div><div class='hunk'>@@ -1562,7 +1562,7 @@ static ssize_t flags_show(struct device *dev,</div><div class='ctx'> 	if (test_bit(NFIT_MEM_DIRTY, &amp;nfit_mem-&gt;flags))</div><div class='ctx'> 		flags |= ACPI_NFIT_MEM_FLUSH_FAILED;</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%s%s%s%s%s%s%s\n",</div><div class='add'>+	return sysfs_emit(buf, "%s%s%s%s%s%s%s\n",</div><div class='ctx'> 		flags &amp; ACPI_NFIT_MEM_SAVE_FAILED ? "save_fail " : "",</div><div class='ctx'> 		flags &amp; ACPI_NFIT_MEM_RESTORE_FAILED ? "restore_fail " : "",</div><div class='ctx'> 		flags &amp; ACPI_NFIT_MEM_FLUSH_FAILED ? "flush_fail " : "",</div><div class='hunk'>@@ -1579,7 +1579,7 @@ static ssize_t id_show(struct device *dev,</div><div class='ctx'> 	struct nvdimm *nvdimm = to_nvdimm(dev);</div><div class='ctx'> 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%s\n", nfit_mem-&gt;id);</div><div class='add'>+	return sysfs_emit(buf, "%s\n", nfit_mem-&gt;id);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(id);</div><div class='ctx'> </div><div class='hunk'>@@ -1589,7 +1589,7 @@ static ssize_t dirty_shutdown_show(struct device *dev,</div><div class='ctx'> 	struct nvdimm *nvdimm = to_nvdimm(dev);</div><div class='ctx'> 	struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", nfit_mem-&gt;dirty_shutdown);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", nfit_mem-&gt;dirty_shutdown);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(dirty_shutdown);</div><div class='ctx'> </div><div class='hunk'>@@ -2172,7 +2172,7 @@ static ssize_t range_index_show(struct device *dev,</div><div class='ctx'> 	struct nd_region *nd_region = to_nd_region(dev);</div><div class='ctx'> 	struct nfit_spa *nfit_spa = nd_region_provider_data(nd_region);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", nfit_spa-&gt;spa-&gt;range_index);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", nfit_spa-&gt;spa-&gt;range_index);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(range_index);</div><div class='ctx'> </div><div class='hunk'>@@ -2257,26 +2257,23 @@ static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,</div><div class='ctx'> 		struct nd_region_desc *ndr_desc,</div><div class='ctx'> 		struct acpi_nfit_system_address *spa)</div><div class='ctx'> {</div><div class='add'>+	u16 nr = ndr_desc-&gt;num_mappings;</div><div class='add'>+	struct nfit_set_info2 *info2 __free(kfree) =</div><div class='add'>+		kcalloc(nr, sizeof(*info2), GFP_KERNEL);</div><div class='add'>+	struct nfit_set_info *info __free(kfree) =</div><div class='add'>+		kcalloc(nr, sizeof(*info), GFP_KERNEL);</div><div class='ctx'> 	struct device *dev = acpi_desc-&gt;dev;</div><div class='ctx'> 	struct nd_interleave_set *nd_set;</div><div class='del'>-	u16 nr = ndr_desc-&gt;num_mappings;</div><div class='del'>-	struct nfit_set_info2 *info2;</div><div class='del'>-	struct nfit_set_info *info;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (!info || !info2)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL);</div><div class='ctx'> 	if (!nd_set)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	import_guid(&amp;nd_set-&gt;type_guid, spa-&gt;range_guid);</div><div class='ctx'> </div><div class='del'>-	info = devm_kcalloc(dev, nr, sizeof(*info), GFP_KERNEL);</div><div class='del'>-	if (!info)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	info2 = devm_kcalloc(dev, nr, sizeof(*info2), GFP_KERNEL);</div><div class='del'>-	if (!info2)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; nr; i++) {</div><div class='ctx'> 		struct nd_mapping_desc *mapping = &amp;ndr_desc-&gt;mapping[i];</div><div class='ctx'> 		struct nvdimm *nvdimm = mapping-&gt;nvdimm;</div><div class='hunk'>@@ -2337,8 +2334,6 @@ static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ndr_desc-&gt;nd_set = nd_set;</div><div class='del'>-	devm_kfree(dev, info);</div><div class='del'>-	devm_kfree(dev, info2);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c<br/>index 9ef5f1bdcfdb..d6b85f0f6082 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/numa/hmat.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/numa/hmat.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/numa/hmat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/numa/hmat.c</a></div><div class='hunk'>@@ -58,14 +58,22 @@ struct target_cache {</div><div class='ctx'> 	struct node_cache_attrs cache_attrs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum {</div><div class='add'>+	NODE_ACCESS_CLASS_0 = 0,</div><div class='add'>+	NODE_ACCESS_CLASS_1,</div><div class='add'>+	NODE_ACCESS_CLASS_GENPORT_SINK,</div><div class='add'>+	NODE_ACCESS_CLASS_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct memory_target {</div><div class='ctx'> 	struct list_head node;</div><div class='ctx'> 	unsigned int memory_pxm;</div><div class='ctx'> 	unsigned int processor_pxm;</div><div class='ctx'> 	struct resource memregions;</div><div class='del'>-	struct node_hmem_attrs hmem_attrs[2];</div><div class='add'>+	struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];</div><div class='ctx'> 	struct list_head caches;</div><div class='ctx'> 	struct node_cache_attrs cache_attrs;</div><div class='add'>+	u8 gen_port_device_handle[ACPI_SRAT_DEVICE_HANDLE_SIZE];</div><div class='ctx'> 	bool registered;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -100,6 +108,47 @@ static struct memory_target *find_mem_target(unsigned int mem_pxm)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct memory_target *acpi_find_genport_target(u32 uid)</div><div class='add'>+{</div><div class='add'>+	struct memory_target *target;</div><div class='add'>+	u32 target_uid;</div><div class='add'>+	u8 *uid_ptr;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(target, &amp;targets, node) {</div><div class='add'>+		uid_ptr = target-&gt;gen_port_device_handle + 8;</div><div class='add'>+		target_uid = *(u32 *)uid_ptr;</div><div class='add'>+		if (uid == target_uid)</div><div class='add'>+			return target;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * acpi_get_genport_coordinates - Retrieve the access coordinates for a generic port</div><div class='add'>+ * @uid: ACPI unique id</div><div class='add'>+ * @coord: The access coordinates written back out for the generic port</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success. Errno on failure.</div><div class='add'>+ *</div><div class='add'>+ * Only supports device handles that are ACPI. Assume ACPI0016 HID for CXL.</div><div class='add'>+ */</div><div class='add'>+int acpi_get_genport_coordinates(u32 uid,</div><div class='add'>+				 struct access_coordinate *coord)</div><div class='add'>+{</div><div class='add'>+	struct memory_target *target;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;target_lock);</div><div class='add'>+	target = acpi_find_genport_target(uid);</div><div class='add'>+	if (!target)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	*coord = target-&gt;coord[NODE_ACCESS_CLASS_GENPORT_SINK];</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(acpi_get_genport_coordinates, CXL);</div><div class='add'>+</div><div class='ctx'> static __init void alloc_memory_initiator(unsigned int cpu_pxm)</div><div class='ctx'> {</div><div class='ctx'> 	struct memory_initiator *initiator;</div><div class='hunk'>@@ -120,8 +169,7 @@ static __init void alloc_memory_initiator(unsigned int cpu_pxm)</div><div class='ctx'> 	list_add_tail(&amp;initiator-&gt;node, &amp;initiators);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __init void alloc_memory_target(unsigned int mem_pxm,</div><div class='del'>-		resource_size_t start, resource_size_t len)</div><div class='add'>+static __init struct memory_target *alloc_target(unsigned int mem_pxm)</div><div class='ctx'> {</div><div class='ctx'> 	struct memory_target *target;</div><div class='ctx'> </div><div class='hunk'>@@ -129,7 +177,7 @@ static __init void alloc_memory_target(unsigned int mem_pxm,</div><div class='ctx'> 	if (!target) {</div><div class='ctx'> 		target = kzalloc(sizeof(*target), GFP_KERNEL);</div><div class='ctx'> 		if (!target)</div><div class='del'>-			return;</div><div class='add'>+			return NULL;</div><div class='ctx'> 		target-&gt;memory_pxm = mem_pxm;</div><div class='ctx'> 		target-&gt;processor_pxm = PXM_INVAL;</div><div class='ctx'> 		target-&gt;memregions = (struct resource) {</div><div class='hunk'>@@ -142,6 +190,19 @@ static __init void alloc_memory_target(unsigned int mem_pxm,</div><div class='ctx'> 		INIT_LIST_HEAD(&amp;target-&gt;caches);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return target;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static __init void alloc_memory_target(unsigned int mem_pxm,</div><div class='add'>+				       resource_size_t start,</div><div class='add'>+				       resource_size_t len)</div><div class='add'>+{</div><div class='add'>+	struct memory_target *target;</div><div class='add'>+</div><div class='add'>+	target = alloc_target(mem_pxm);</div><div class='add'>+	if (!target)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * There are potentially multiple ranges per PXM, so record each</div><div class='ctx'> 	 * in the per-target memregions resource tree.</div><div class='hunk'>@@ -152,6 +213,18 @@ static __init void alloc_memory_target(unsigned int mem_pxm,</div><div class='ctx'> 				start, start + len, mem_pxm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static __init void alloc_genport_target(unsigned int mem_pxm, u8 *handle)</div><div class='add'>+{</div><div class='add'>+	struct memory_target *target;</div><div class='add'>+</div><div class='add'>+	target = alloc_target(mem_pxm);</div><div class='add'>+	if (!target)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memcpy(target-&gt;gen_port_device_handle, handle,</div><div class='add'>+	       ACPI_SRAT_DEVICE_HANDLE_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static __init const char *hmat_data_type(u8 type)</div><div class='ctx'> {</div><div class='ctx'> 	switch (type) {</div><div class='hunk'>@@ -228,24 +301,24 @@ static void hmat_update_target_access(struct memory_target *target,</div><div class='ctx'> {</div><div class='ctx'> 	switch (type) {</div><div class='ctx'> 	case ACPI_HMAT_ACCESS_LATENCY:</div><div class='del'>-		target-&gt;hmem_attrs[access].read_latency = value;</div><div class='del'>-		target-&gt;hmem_attrs[access].write_latency = value;</div><div class='add'>+		target-&gt;coord[access].read_latency = value;</div><div class='add'>+		target-&gt;coord[access].write_latency = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACPI_HMAT_READ_LATENCY:</div><div class='del'>-		target-&gt;hmem_attrs[access].read_latency = value;</div><div class='add'>+		target-&gt;coord[access].read_latency = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACPI_HMAT_WRITE_LATENCY:</div><div class='del'>-		target-&gt;hmem_attrs[access].write_latency = value;</div><div class='add'>+		target-&gt;coord[access].write_latency = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACPI_HMAT_ACCESS_BANDWIDTH:</div><div class='del'>-		target-&gt;hmem_attrs[access].read_bandwidth = value;</div><div class='del'>-		target-&gt;hmem_attrs[access].write_bandwidth = value;</div><div class='add'>+		target-&gt;coord[access].read_bandwidth = value;</div><div class='add'>+		target-&gt;coord[access].write_bandwidth = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACPI_HMAT_READ_BANDWIDTH:</div><div class='del'>-		target-&gt;hmem_attrs[access].read_bandwidth = value;</div><div class='add'>+		target-&gt;coord[access].read_bandwidth = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ACPI_HMAT_WRITE_BANDWIDTH:</div><div class='del'>-		target-&gt;hmem_attrs[access].write_bandwidth = value;</div><div class='add'>+		target-&gt;coord[access].write_bandwidth = value;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -291,11 +364,28 @@ static __init void hmat_add_locality(struct acpi_hmat_locality *hmat_loc)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static __init void hmat_update_target(unsigned int tgt_pxm, unsigned int init_pxm,</div><div class='add'>+				      u8 mem_hier, u8 type, u32 value)</div><div class='add'>+{</div><div class='add'>+	struct memory_target *target = find_mem_target(tgt_pxm);</div><div class='add'>+</div><div class='add'>+	if (mem_hier != ACPI_HMAT_MEMORY)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (target &amp;&amp; target-&gt;processor_pxm == init_pxm) {</div><div class='add'>+		hmat_update_target_access(target, type, value,</div><div class='add'>+					  NODE_ACCESS_CLASS_0);</div><div class='add'>+		/* If the node has a CPU, update access 1 */</div><div class='add'>+		if (node_state(pxm_to_node(init_pxm), N_CPU))</div><div class='add'>+			hmat_update_target_access(target, type, value,</div><div class='add'>+						  NODE_ACCESS_CLASS_1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static __init int hmat_parse_locality(union acpi_subtable_headers *header,</div><div class='ctx'> 				      const unsigned long end)</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_hmat_locality *hmat_loc = (void *)header;</div><div class='del'>-	struct memory_target *target;</div><div class='ctx'> 	unsigned int init, targ, total_size, ipds, tpds;</div><div class='ctx'> 	u32 *inits, *targs, value;</div><div class='ctx'> 	u16 *entries;</div><div class='hunk'>@@ -336,15 +426,8 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,</div><div class='ctx'> 				inits[init], targs[targ], value,</div><div class='ctx'> 				hmat_data_type_suffix(type));</div><div class='ctx'> </div><div class='del'>-			if (mem_hier == ACPI_HMAT_MEMORY) {</div><div class='del'>-				target = find_mem_target(targs[targ]);</div><div class='del'>-				if (target &amp;&amp; target-&gt;processor_pxm == inits[init]) {</div><div class='del'>-					hmat_update_target_access(target, type, value, 0);</div><div class='del'>-					/* If the node has a CPU, update access 1 */</div><div class='del'>-					if (node_state(pxm_to_node(inits[init]), N_CPU))</div><div class='del'>-						hmat_update_target_access(target, type, value, 1);</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='add'>+			hmat_update_target(targs[targ], inits[init],</div><div class='add'>+					   mem_hier, type, value);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -491,6 +574,27 @@ static __init int srat_parse_mem_affinity(union acpi_subtable_headers *header,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static __init int srat_parse_genport_affinity(union acpi_subtable_headers *header,</div><div class='add'>+					      const unsigned long end)</div><div class='add'>+{</div><div class='add'>+	struct acpi_srat_generic_affinity *ga = (void *)header;</div><div class='add'>+</div><div class='add'>+	if (!ga)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!(ga-&gt;flags &amp; ACPI_SRAT_GENERIC_AFFINITY_ENABLED))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Skip PCI device_handle for now */</div><div class='add'>+	if (ga-&gt;device_handle_type != 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	alloc_genport_target(ga-&gt;proximity_domain,</div><div class='add'>+			     (u8 *)ga-&gt;device_handle);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u32 hmat_initiator_perf(struct memory_target *target,</div><div class='ctx'> 			       struct memory_initiator *initiator,</div><div class='ctx'> 			       struct acpi_hmat_locality *hmat_loc)</div><div class='hunk'>@@ -592,6 +696,11 @@ static void hmat_update_target_attrs(struct memory_target *target,</div><div class='ctx'> 	u32 best = 0;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/* Don't update for generic port if there's no device handle */</div><div class='add'>+	if (access == NODE_ACCESS_CLASS_GENPORT_SINK &amp;&amp;</div><div class='add'>+	    !(*(u16 *)target-&gt;gen_port_device_handle))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	bitmap_zero(p_nodes, MAX_NUMNODES);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If the Address Range Structure provides a local processor pxm, set</div><div class='hunk'>@@ -661,6 +770,14 @@ static void __hmat_register_target_initiators(struct memory_target *target,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void hmat_register_generic_target_initiators(struct memory_target *target)</div><div class='add'>+{</div><div class='add'>+	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);</div><div class='add'>+</div><div class='add'>+	__hmat_register_target_initiators(target, p_nodes,</div><div class='add'>+					  NODE_ACCESS_CLASS_GENPORT_SINK);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void hmat_register_target_initiators(struct memory_target *target)</div><div class='ctx'> {</div><div class='ctx'> 	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);</div><div class='hunk'>@@ -681,7 +798,7 @@ static void hmat_register_target_cache(struct memory_target *target)</div><div class='ctx'> static void hmat_register_target_perf(struct memory_target *target, int access)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned mem_nid = pxm_to_node(target-&gt;memory_pxm);</div><div class='del'>-	node_set_perf_attrs(mem_nid, &amp;target-&gt;hmem_attrs[access], access);</div><div class='add'>+	node_set_perf_attrs(mem_nid, &amp;target-&gt;coord[access], access);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hmat_register_target_devices(struct memory_target *target)</div><div class='hunk'>@@ -713,6 +830,17 @@ static void hmat_register_target(struct memory_target *target)</div><div class='ctx'> 	hmat_register_target_devices(target);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * Register generic port perf numbers. The nid may not be</div><div class='add'>+	 * initialized and is still NUMA_NO_NODE.</div><div class='add'>+	 */</div><div class='add'>+	mutex_lock(&amp;target_lock);</div><div class='add'>+	if (*(u16 *)target-&gt;gen_port_device_handle) {</div><div class='add'>+		hmat_register_generic_target_initiators(target);</div><div class='add'>+		target-&gt;registered = true;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;target_lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Skip offline nodes. This can happen when memory</div><div class='ctx'> 	 * marked EFI_MEMORY_SP, "specific purpose", is applied</div><div class='ctx'> 	 * to all the memory in a proximity domain leading to</div><div class='hunk'>@@ -726,8 +854,8 @@ static void hmat_register_target(struct memory_target *target)</div><div class='ctx'> 	if (!target-&gt;registered) {</div><div class='ctx'> 		hmat_register_target_initiators(target);</div><div class='ctx'> 		hmat_register_target_cache(target);</div><div class='del'>-		hmat_register_target_perf(target, 0);</div><div class='del'>-		hmat_register_target_perf(target, 1);</div><div class='add'>+		hmat_register_target_perf(target, NODE_ACCESS_CLASS_0);</div><div class='add'>+		hmat_register_target_perf(target, NODE_ACCESS_CLASS_1);</div><div class='ctx'> 		target-&gt;registered = true;</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;target_lock);</div><div class='hunk'>@@ -765,7 +893,7 @@ static int hmat_set_default_dram_perf(void)</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	int nid, pxm;</div><div class='ctx'> 	struct memory_target *target;</div><div class='del'>-	struct node_hmem_attrs *attrs;</div><div class='add'>+	struct access_coordinate *attrs;</div><div class='ctx'> </div><div class='ctx'> 	if (!default_dram_type)</div><div class='ctx'> 		return -EIO;</div><div class='hunk'>@@ -775,7 +903,7 @@ static int hmat_set_default_dram_perf(void)</div><div class='ctx'> 		target = find_mem_target(pxm);</div><div class='ctx'> 		if (!target)</div><div class='ctx'> 			continue;</div><div class='del'>-		attrs = &amp;target-&gt;hmem_attrs[1];</div><div class='add'>+		attrs = &amp;target-&gt;coord[1];</div><div class='ctx'> 		rc = mt_set_default_dram_perf(nid, attrs, "ACPI HMAT");</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			return rc;</div><div class='hunk'>@@ -789,7 +917,7 @@ static int hmat_calculate_adistance(struct notifier_block *self,</div><div class='ctx'> {</div><div class='ctx'> 	static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);</div><div class='ctx'> 	struct memory_target *target;</div><div class='del'>-	struct node_hmem_attrs *perf;</div><div class='add'>+	struct access_coordinate *perf;</div><div class='ctx'> 	int *adist = data;</div><div class='ctx'> 	int pxm;</div><div class='ctx'> </div><div class='hunk'>@@ -802,7 +930,7 @@ static int hmat_calculate_adistance(struct notifier_block *self,</div><div class='ctx'> 	hmat_update_target_attrs(target, p_nodes, 1);</div><div class='ctx'> 	mutex_unlock(&amp;target_lock);</div><div class='ctx'> </div><div class='del'>-	perf = &amp;target-&gt;hmem_attrs[1];</div><div class='add'>+	perf = &amp;target-&gt;coord[1];</div><div class='ctx'> </div><div class='ctx'> 	if (mt_perf_to_adistance(perf, adist))</div><div class='ctx'> 		return NOTIFY_OK;</div><div class='hunk'>@@ -870,6 +998,13 @@ static __init int hmat_init(void)</div><div class='ctx'> 				ACPI_SRAT_TYPE_MEMORY_AFFINITY,</div><div class='ctx'> 				srat_parse_mem_affinity, 0) &lt; 0)</div><div class='ctx'> 		goto out_put;</div><div class='add'>+</div><div class='add'>+	if (acpi_table_parse_entries(ACPI_SIG_SRAT,</div><div class='add'>+				     sizeof(struct acpi_table_srat),</div><div class='add'>+				     ACPI_SRAT_TYPE_GENERIC_PORT_AFFINITY,</div><div class='add'>+				     srat_parse_genport_affinity, 0) &lt; 0)</div><div class='add'>+		goto out_put;</div><div class='add'>+</div><div class='ctx'> 	acpi_put_table(tbl);</div><div class='ctx'> </div><div class='ctx'> 	status = acpi_get_table(ACPI_SIG_HMAT, 0, &amp;tbl);</div><div class='head'>diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c<br/>index 12f330b0eac0..0214518fc582 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/numa/srat.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/numa/srat.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/numa/srat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/numa/srat.c</a></div><div class='hunk'>@@ -67,9 +67,9 @@ int acpi_map_pxm_to_node(int pxm)</div><div class='ctx'> 	node = pxm_to_node_map[pxm];</div><div class='ctx'> </div><div class='ctx'> 	if (node == NUMA_NO_NODE) {</div><div class='del'>-		if (nodes_weight(nodes_found_map) &gt;= MAX_NUMNODES)</div><div class='del'>-			return NUMA_NO_NODE;</div><div class='ctx'> 		node = first_unset_node(nodes_found_map);</div><div class='add'>+		if (node &gt;= MAX_NUMNODES)</div><div class='add'>+			return NUMA_NO_NODE;</div><div class='ctx'> 		__acpi_map_pxm_to_node(pxm, node);</div><div class='ctx'> 		node_set(node, nodes_found_map);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -183,7 +183,7 @@ static int __init slit_valid(struct acpi_table_slit *slit)</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	int d = slit-&gt;locality_count;</div><div class='ctx'> 	for (i = 0; i &lt; d; i++) {</div><div class='del'>-		for (j = 0; j &lt; d; j++)  {</div><div class='add'>+		for (j = 0; j &lt; d; j++) {</div><div class='ctx'> 			u8 val = slit-&gt;entry[d*i + j];</div><div class='ctx'> 			if (i == j) {</div><div class='ctx'> 				if (val != LOCAL_DISTANCE)</div><div class='hunk'>@@ -430,7 +430,7 @@ acpi_parse_gi_affinity(union acpi_subtable_headers *header,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	node = acpi_map_pxm_to_node(gi_affinity-&gt;proximity_domain);</div><div class='del'>-	if (node == NUMA_NO_NODE || node &gt;= MAX_NUMNODES) {</div><div class='add'>+	if (node == NUMA_NO_NODE) {</div><div class='ctx'> 		pr_err("SRAT: Too many proximity domains.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -532,7 +532,7 @@ int __init acpi_numa_init(void)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/* fake_pxm is the next unused PXM value after SRAT parsing */</div><div class='del'>-	for (i = 0, fake_pxm = -1; i &lt; MAX_NUMNODES - 1; i++) {</div><div class='add'>+	for (i = 0, fake_pxm = -1; i &lt; MAX_NUMNODES; i++) {</div><div class='ctx'> 		if (node_to_pxm_map[i] &gt; fake_pxm)</div><div class='ctx'> 			fake_pxm = node_to_pxm_map[i];</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c<br/>index c09cc3c68633..70af3fbbebe5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/osl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/osl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/osl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/osl.c</a></div><div class='hunk'>@@ -544,11 +544,7 @@ acpi_os_predefined_override(const struct acpi_predefined_names *init_val,</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t acpi_irq(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='del'>-	u32 handled;</div><div class='del'>-</div><div class='del'>-	handled = (*acpi_irq_handler) (acpi_irq_context);</div><div class='del'>-</div><div class='del'>-	if (handled) {</div><div class='add'>+	if ((*acpi_irq_handler)(acpi_irq_context)) {</div><div class='ctx'> 		acpi_irq_handled++;</div><div class='ctx'> 		return IRQ_HANDLED;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -582,7 +578,8 @@ acpi_os_install_interrupt_handler(u32 gsi, acpi_osd_handler handler,</div><div class='ctx'> </div><div class='ctx'> 	acpi_irq_handler = handler;</div><div class='ctx'> 	acpi_irq_context = context;</div><div class='del'>-	if (request_irq(irq, acpi_irq, IRQF_SHARED, "acpi", acpi_irq)) {</div><div class='add'>+	if (request_threaded_irq(irq, NULL, acpi_irq, IRQF_SHARED | IRQF_ONESHOT,</div><div class='add'>+			         "acpi", acpi_irq)) {</div><div class='ctx'> 		pr_err("SCI (IRQ%d) allocation failed\n", irq);</div><div class='ctx'> 		acpi_irq_handler = NULL;</div><div class='ctx'> 		return AE_NOT_ACQUIRED;</div><div class='hunk'>@@ -1063,9 +1060,7 @@ int __init acpi_debugger_init(void)</div><div class='ctx'> acpi_status acpi_os_execute(acpi_execute_type type,</div><div class='ctx'> 			    acpi_osd_exec_callback function, void *context)</div><div class='ctx'> {</div><div class='del'>-	acpi_status status = AE_OK;</div><div class='ctx'> 	struct acpi_os_dpc *dpc;</div><div class='del'>-	struct workqueue_struct *queue;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ACPI_DEBUG_PRINT((ACPI_DB_EXEC,</div><div class='hunk'>@@ -1076,9 +1071,9 @@ acpi_status acpi_os_execute(acpi_execute_type type,</div><div class='ctx'> 		ret = acpi_debugger_create_thread(function, context);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			pr_err("Kernel thread creation failed\n");</div><div class='del'>-			status = AE_ERROR;</div><div class='add'>+			return AE_ERROR;</div><div class='ctx'> 		}</div><div class='del'>-		goto out_thread;</div><div class='add'>+		return AE_OK;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1096,43 +1091,41 @@ acpi_status acpi_os_execute(acpi_execute_type type,</div><div class='ctx'> </div><div class='ctx'> 	dpc-&gt;function = function;</div><div class='ctx'> 	dpc-&gt;context = context;</div><div class='add'>+	INIT_WORK(&amp;dpc-&gt;work, acpi_os_execute_deferred);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * To prevent lockdep from complaining unnecessarily, make sure that</div><div class='ctx'> 	 * there is a different static lockdep key for each workqueue by using</div><div class='ctx'> 	 * INIT_WORK() for each of them separately.</div><div class='ctx'> 	 */</div><div class='del'>-	if (type == OSL_NOTIFY_HANDLER) {</div><div class='del'>-		queue = kacpi_notify_wq;</div><div class='del'>-		INIT_WORK(&amp;dpc-&gt;work, acpi_os_execute_deferred);</div><div class='del'>-	} else if (type == OSL_GPE_HANDLER) {</div><div class='del'>-		queue = kacpid_wq;</div><div class='del'>-		INIT_WORK(&amp;dpc-&gt;work, acpi_os_execute_deferred);</div><div class='del'>-	} else {</div><div class='add'>+	switch (type) {</div><div class='add'>+	case OSL_NOTIFY_HANDLER:</div><div class='add'>+		ret = queue_work(kacpi_notify_wq, &amp;dpc-&gt;work);</div><div class='add'>+		break;</div><div class='add'>+	case OSL_GPE_HANDLER:</div><div class='add'>+		/*</div><div class='add'>+		 * On some machines, a software-initiated SMI causes corruption</div><div class='add'>+		 * unless the SMI runs on CPU 0.  An SMI can be initiated by</div><div class='add'>+		 * any AML, but typically it's done in GPE-related methods that</div><div class='add'>+		 * are run via workqueues, so we can avoid the known corruption</div><div class='add'>+		 * cases by always queueing on CPU 0.</div><div class='add'>+		 */</div><div class='add'>+		ret = queue_work_on(0, kacpid_wq, &amp;dpc-&gt;work);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='ctx'> 		pr_err("Unsupported os_execute type %d.\n", type);</div><div class='del'>-		status = AE_ERROR;</div><div class='add'>+		goto err;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	if (ACPI_FAILURE(status))</div><div class='del'>-		goto err_workqueue;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * On some machines, a software-initiated SMI causes corruption unless</div><div class='del'>-	 * the SMI runs on CPU 0.  An SMI can be initiated by any AML, but</div><div class='del'>-	 * typically it's done in GPE-related methods that are run via</div><div class='del'>-	 * workqueues, so we can avoid the known corruption cases by always</div><div class='del'>-	 * queueing on CPU 0.</div><div class='del'>-	 */</div><div class='del'>-	ret = queue_work_on(0, queue, &amp;dpc-&gt;work);</div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		pr_err("Unable to queue work\n");</div><div class='del'>-		status = AE_ERROR;</div><div class='add'>+		goto err;</div><div class='ctx'> 	}</div><div class='del'>-err_workqueue:</div><div class='del'>-	if (ACPI_FAILURE(status))</div><div class='del'>-		kfree(dpc);</div><div class='del'>-out_thread:</div><div class='del'>-	return status;</div><div class='add'>+</div><div class='add'>+	return AE_OK;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	kfree(dpc);</div><div class='add'>+	return AE_ERROR;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(acpi_os_execute);</div><div class='ctx'> </div><div class='hunk'>@@ -1522,20 +1515,18 @@ void acpi_os_delete_lock(acpi_spinlock handle)</div><div class='ctx'> acpi_cpu_flags acpi_os_acquire_lock(acpi_spinlock lockp)</div><div class='ctx'> 	__acquires(lockp)</div><div class='ctx'> {</div><div class='del'>-	acpi_cpu_flags flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(lockp, flags);</div><div class='del'>-	return flags;</div><div class='add'>+	spin_lock(lockp);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Release a spinlock. See above.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-void acpi_os_release_lock(acpi_spinlock lockp, acpi_cpu_flags flags)</div><div class='add'>+void acpi_os_release_lock(acpi_spinlock lockp, acpi_cpu_flags not_used)</div><div class='ctx'> 	__releases(lockp)</div><div class='ctx'> {</div><div class='del'>-	spin_unlock_irqrestore(lockp, flags);</div><div class='add'>+	spin_unlock(lockp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifndef ACPI_USE_LOCAL_CACHE</div><div class='hunk'>@@ -1672,7 +1663,7 @@ acpi_status __init acpi_os_initialize(void)</div><div class='ctx'> acpi_status __init acpi_os_initialize1(void)</div><div class='ctx'> {</div><div class='ctx'> 	kacpid_wq = alloc_workqueue("kacpid", 0, 1);</div><div class='del'>-	kacpi_notify_wq = alloc_workqueue("kacpi_notify", 0, 1);</div><div class='add'>+	kacpi_notify_wq = alloc_workqueue("kacpi_notify", 0, 0);</div><div class='ctx'> 	kacpi_hotplug_wq = alloc_ordered_workqueue("kacpi_hotplug", 0);</div><div class='ctx'> 	BUG_ON(!kacpid_wq);</div><div class='ctx'> 	BUG_ON(!kacpi_notify_wq);</div><div class='head'>diff --git a/drivers/acpi/processor_thermal.c b/drivers/acpi/processor_thermal.c<br/>index b7c6287eccca..1219adb11ab9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/processor_thermal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/processor_thermal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/processor_thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/processor_thermal.c</a></div><div class='hunk'>@@ -17,6 +17,8 @@</div><div class='ctx'> #include &lt;acpi/processor.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "internal.h"</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_CPU_FREQ</div><div class='ctx'> </div><div class='ctx'> /* If a passive cooling situation is detected, primarily CPUfreq is used, as it</div><div class='hunk'>@@ -26,12 +28,21 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #define CPUFREQ_THERMAL_MIN_STEP 0</div><div class='del'>-#define CPUFREQ_THERMAL_MAX_STEP 3</div><div class='ctx'> </div><div class='del'>-static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_pctg);</div><div class='add'>+static int cpufreq_thermal_max_step __read_mostly = 3;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Minimum throttle percentage for processor_thermal cooling device.</div><div class='add'>+ * The processor_thermal driver uses it to calculate the percentage amount by</div><div class='add'>+ * which cpu frequency must be reduced for each cooling state. This is also used</div><div class='add'>+ * to calculate the maximum number of throttling steps or cooling states.</div><div class='add'>+ */</div><div class='add'>+static int cpufreq_thermal_reduction_pctg __read_mostly = 20;</div><div class='ctx'> </div><div class='del'>-#define reduction_pctg(cpu) \</div><div class='del'>-	per_cpu(cpufreq_thermal_reduction_pctg, phys_package_first_cpu(cpu))</div><div class='add'>+static DEFINE_PER_CPU(unsigned int, cpufreq_thermal_reduction_step);</div><div class='add'>+</div><div class='add'>+#define reduction_step(cpu) \</div><div class='add'>+	per_cpu(cpufreq_thermal_reduction_step, phys_package_first_cpu(cpu))</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Emulate "per package data" using per cpu data (which should really be</div><div class='hunk'>@@ -71,7 +82,7 @@ static int cpufreq_get_max_state(unsigned int cpu)</div><div class='ctx'> 	if (!cpu_has_cpufreq(cpu))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return CPUFREQ_THERMAL_MAX_STEP;</div><div class='add'>+	return cpufreq_thermal_max_step;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cpufreq_get_cur_state(unsigned int cpu)</div><div class='hunk'>@@ -79,7 +90,7 @@ static int cpufreq_get_cur_state(unsigned int cpu)</div><div class='ctx'> 	if (!cpu_has_cpufreq(cpu))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return reduction_pctg(cpu);</div><div class='add'>+	return reduction_step(cpu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cpufreq_set_cur_state(unsigned int cpu, int state)</div><div class='hunk'>@@ -92,7 +103,7 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state)</div><div class='ctx'> 	if (!cpu_has_cpufreq(cpu))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	reduction_pctg(cpu) = state;</div><div class='add'>+	reduction_step(cpu) = state;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Update all the CPUs in the same package because they all</div><div class='hunk'>@@ -113,7 +124,8 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state)</div><div class='ctx'> 		if (!policy)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		max_freq = (policy-&gt;cpuinfo.max_freq * (100 - reduction_pctg(i) * 20)) / 100;</div><div class='add'>+		max_freq = (policy-&gt;cpuinfo.max_freq *</div><div class='add'>+			    (100 - reduction_step(i) * cpufreq_thermal_reduction_pctg)) / 100;</div><div class='ctx'> </div><div class='ctx'> 		cpufreq_cpu_put(policy);</div><div class='ctx'> </div><div class='hunk'>@@ -126,10 +138,29 @@ static int cpufreq_set_cur_state(unsigned int cpu, int state)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void acpi_thermal_cpufreq_config(void)</div><div class='add'>+{</div><div class='add'>+	int cpufreq_pctg = acpi_arch_thermal_cpufreq_pctg();</div><div class='add'>+</div><div class='add'>+	if (!cpufreq_pctg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cpufreq_thermal_reduction_pctg = cpufreq_pctg;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Derive the MAX_STEP from minimum throttle percentage so that the reduction</div><div class='add'>+	 * percentage doesn't end up becoming negative. Also, cap the MAX_STEP so that</div><div class='add'>+	 * the CPU performance doesn't become 0.</div><div class='add'>+	 */</div><div class='add'>+	cpufreq_thermal_max_step = (100 / cpufreq_pctg) - 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void acpi_thermal_cpufreq_init(struct cpufreq_policy *policy)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int cpu;</div><div class='ctx'> </div><div class='add'>+	acpi_thermal_cpufreq_config();</div><div class='add'>+</div><div class='ctx'> 	for_each_cpu(cpu, policy-&gt;related_cpus) {</div><div class='ctx'> 		struct acpi_processor *pr = per_cpu(processors, cpu);</div><div class='ctx'> 		int ret;</div><div class='hunk'>@@ -190,7 +221,7 @@ static int acpi_processor_max_state(struct acpi_processor *pr)</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * There exists four states according to</div><div class='del'>-	 * cpufreq_thermal_reduction_pctg. 0, 1, 2, 3</div><div class='add'>+	 * cpufreq_thermal_reduction_step. 0, 1, 2, 3</div><div class='ctx'> 	 */</div><div class='ctx'> 	max_state += cpufreq_get_max_state(pr-&gt;id);</div><div class='ctx'> 	if (pr-&gt;flags.throttling)</div><div class='head'>diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c<br/>index 6979a3f9f90a..a6ead5204046 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/property.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/property.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/property.c</a></div><div class='hunk'>@@ -2,14 +2,17 @@</div><div class='ctx'> /*</div><div class='ctx'>  * ACPI device specific properties support.</div><div class='ctx'>  *</div><div class='del'>- * Copyright (C) 2014, Intel Corporation</div><div class='add'>+ * Copyright (C) 2014 - 2023, Intel Corporation</div><div class='ctx'>  * All rights reserved.</div><div class='ctx'>  *</div><div class='ctx'>  * Authors: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;</div><div class='ctx'>  *          Darren Hart &lt;dvhart@linux.intel.com&gt;</div><div class='ctx'>  *          Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;</div><div class='add'>+ *          Sakari Ailus &lt;sakari.ailus@linux.intel.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#define pr_fmt(fmt) "ACPI: " fmt</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/export.h&gt;</div><div class='hunk'>@@ -801,27 +804,15 @@ static int acpi_get_ref_args(struct fwnode_reference_args *args,</div><div class='ctx'> 	u32 nargs = 0, i;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Find the referred data extension node under the</div><div class='del'>-	 * referred device node.</div><div class='del'>-	 */</div><div class='del'>-	for (; *element &lt; end &amp;&amp; (*element)-&gt;type == ACPI_TYPE_STRING;</div><div class='del'>-	     (*element)++) {</div><div class='del'>-		const char *child_name = (*element)-&gt;string.pointer;</div><div class='del'>-</div><div class='del'>-		ref_fwnode = acpi_fwnode_get_named_child_node(ref_fwnode, child_name);</div><div class='del'>-		if (!ref_fwnode)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='ctx'> 	 * Assume the following integer elements are all args. Stop counting on</div><div class='del'>-	 * the first reference or end of the package arguments. In case of</div><div class='del'>-	 * neither reference, nor integer, return an error, we can't parse it.</div><div class='add'>+	 * the first reference (possibly represented as a string) or end of the</div><div class='add'>+	 * package arguments. In case of neither reference, nor integer, return</div><div class='add'>+	 * an error, we can't parse it.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; (*element) + i &lt; end &amp;&amp; i &lt; num_args; i++) {</div><div class='ctx'> 		acpi_object_type type = (*element)[i].type;</div><div class='ctx'> </div><div class='del'>-		if (type == ACPI_TYPE_LOCAL_REFERENCE)</div><div class='add'>+		if (type == ACPI_TYPE_LOCAL_REFERENCE || type == ACPI_TYPE_STRING)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		if (type == ACPI_TYPE_INTEGER)</div><div class='hunk'>@@ -845,6 +836,44 @@ static int acpi_get_ref_args(struct fwnode_reference_args *args,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct fwnode_handle *acpi_parse_string_ref(const struct fwnode_handle *fwnode,</div><div class='add'>+						   const char *refstring)</div><div class='add'>+{</div><div class='add'>+	acpi_handle scope, handle;</div><div class='add'>+	struct acpi_data_node *dn;</div><div class='add'>+	struct acpi_device *device;</div><div class='add'>+	acpi_status status;</div><div class='add'>+</div><div class='add'>+	if (is_acpi_device_node(fwnode)) {</div><div class='add'>+		scope = to_acpi_device_node(fwnode)-&gt;handle;</div><div class='add'>+	} else if (is_acpi_data_node(fwnode)) {</div><div class='add'>+		scope = to_acpi_data_node(fwnode)-&gt;handle;</div><div class='add'>+	} else {</div><div class='add'>+		pr_debug("Bad node type for node %pfw\n", fwnode);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	status = acpi_get_handle(scope, refstring, &amp;handle);</div><div class='add'>+	if (ACPI_FAILURE(status)) {</div><div class='add'>+		acpi_handle_debug(scope, "Unable to get an ACPI handle for %s\n",</div><div class='add'>+				  refstring);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	device = acpi_fetch_acpi_dev(handle);</div><div class='add'>+	if (device)</div><div class='add'>+		return acpi_fwnode_handle(device);</div><div class='add'>+</div><div class='add'>+	status = acpi_get_data_full(handle, acpi_nondev_subnode_tag,</div><div class='add'>+				    (void **)&amp;dn, NULL);</div><div class='add'>+	if (ACPI_FAILURE(status) || !dn) {</div><div class='add'>+		acpi_handle_debug(handle, "Subnode not found\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;dn-&gt;fwnode;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * __acpi_node_get_property_reference - returns handle to the referenced object</div><div class='ctx'>  * @fwnode: Firmware node to get the property from</div><div class='hunk'>@@ -852,6 +881,7 @@ static int acpi_get_ref_args(struct fwnode_reference_args *args,</div><div class='ctx'>  * @index: Index of the reference to return</div><div class='ctx'>  * @num_args: Maximum number of arguments after each reference</div><div class='ctx'>  * @args: Location to store the returned reference with optional arguments</div><div class='add'>+ *	  (may be NULL)</div><div class='ctx'>  *</div><div class='ctx'>  * Find property with @name, verifify that it is a package containing at least</div><div class='ctx'>  * one object reference and if so, store the ACPI device object pointer to the</div><div class='hunk'>@@ -887,6 +917,7 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,</div><div class='ctx'> 	const union acpi_object *element, *end;</div><div class='ctx'> 	const union acpi_object *obj;</div><div class='ctx'> 	const struct acpi_device_data *data;</div><div class='add'>+	struct fwnode_handle *ref_fwnode;</div><div class='ctx'> 	struct acpi_device *device;</div><div class='ctx'> 	int ret, idx = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -908,18 +939,35 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,</div><div class='ctx'> 		if (!device)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='add'>+		if (!args)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='ctx'> 		args-&gt;fwnode = acpi_fwnode_handle(device);</div><div class='ctx'> 		args-&gt;nargs = 0;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	case ACPI_TYPE_STRING:</div><div class='add'>+		if (index)</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		ref_fwnode = acpi_parse_string_ref(fwnode, obj-&gt;string.pointer);</div><div class='add'>+		if (!ref_fwnode)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		args-&gt;fwnode = ref_fwnode;</div><div class='add'>+		args-&gt;nargs = 0;</div><div class='add'>+</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	case ACPI_TYPE_PACKAGE:</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If it is not a single reference, then it is a package of</div><div class='del'>-		 * references followed by number of ints as follows:</div><div class='add'>+		 * references, followed by number of ints as follows:</div><div class='ctx'> 		 *</div><div class='ctx'> 		 *  Package () { REF, INT, REF, INT, INT }</div><div class='ctx'> 		 *</div><div class='del'>-		 * The index argument is then used to determine which reference</div><div class='del'>-		 * the caller wants (along with the arguments).</div><div class='add'>+		 * Here, REF may be either a local reference or a string. The</div><div class='add'>+		 * index argument is then used to determine which reference the</div><div class='add'>+		 * caller wants (along with the arguments).</div><div class='ctx'> 		 */</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -951,6 +999,24 @@ int __acpi_node_get_property_reference(const struct fwnode_handle *fwnode,</div><div class='ctx'> 				return 0;</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='add'>+		case ACPI_TYPE_STRING:</div><div class='add'>+			ref_fwnode = acpi_parse_string_ref(fwnode,</div><div class='add'>+							   element-&gt;string.pointer);</div><div class='add'>+			if (!ref_fwnode)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			element++;</div><div class='add'>+</div><div class='add'>+			ret = acpi_get_ref_args(idx == index ? args : NULL,</div><div class='add'>+						ref_fwnode, &amp;element, end,</div><div class='add'>+						num_args);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			if (idx == index)</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='ctx'> 		case ACPI_TYPE_INTEGER:</div><div class='ctx'> 			if (idx == index)</div><div class='ctx'> 				return -ENOENT;</div><div class='head'>diff --git a/drivers/acpi/resource.c b/drivers/acpi/resource.c<br/>index 9bd9f79cd409..dacad1d846c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/resource.c</a></div><div class='hunk'>@@ -462,6 +462,13 @@ static const struct dmi_system_id irq1_level_low_skip_override[] = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		/* Asus ExpertBook B1502CGA */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "B1502CGA"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		/* Asus ExpertBook B2402CBA */</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),</div><div class='hunk'>@@ -483,6 +490,20 @@ static const struct dmi_system_id irq1_level_low_skip_override[] = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		/* Asus Vivobook E1504GA */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "E1504GA"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		/* Asus Vivobook E1504GAB */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "E1504GAB"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		/* LG Electronics 17U70P */</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "LG Electronics"),</div><div class='hunk'>@@ -511,6 +532,13 @@ static const struct dmi_system_id irq1_edge_low_force_override[] = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		/* TongFang GMxXGxx sold as Eluktronics Inc. RP-15 */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Eluktronics Inc."),</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "RP-15"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		/* TongFang GM6XGxX/TUXEDO Stellaris 16 Gen5 AMD */</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_BOARD_NAME, "GM6XGxX"),</div><div class='hunk'>@@ -548,6 +576,18 @@ static const struct dmi_system_id irq1_edge_low_force_override[] = {</div><div class='ctx'> 			DMI_MATCH(DMI_BOARD_NAME, "GM6BG0Q"),</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+		/* Infinity E15-5A165-BM */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "GM5RG1E0009COM"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		/* Infinity E15-5A305-1M */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_BOARD_NAME, "GM5RGEE0016COM"),</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c<br/>index fa5dd71a80fa..e6ed1ba91e5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/scan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/scan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/scan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/scan.c</a></div><div class='hunk'>@@ -1532,7 +1532,6 @@ int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map)</div><div class='ctx'> 			r-&gt;cpu_start = rentry-&gt;res-&gt;start;</div><div class='ctx'> 			r-&gt;dma_start = rentry-&gt;res-&gt;start - rentry-&gt;offset;</div><div class='ctx'> 			r-&gt;size = resource_size(rentry-&gt;res);</div><div class='del'>-			r-&gt;offset = rentry-&gt;offset;</div><div class='ctx'> 			r++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1562,23 +1561,27 @@ static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev)</div><div class='ctx'> 	return fwspec ? fwspec-&gt;ops : NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev,</div><div class='del'>-						       const u32 *id_in)</div><div class='add'>+static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> 	const struct iommu_ops *ops;</div><div class='ctx'> </div><div class='add'>+	/* Serialise to make dev-&gt;iommu stable under our potential fwspec */</div><div class='add'>+	mutex_lock(&amp;iommu_probe_device_lock);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we already translated the fwspec there is nothing left to do,</div><div class='ctx'> 	 * return the iommu_ops.</div><div class='ctx'> 	 */</div><div class='ctx'> 	ops = acpi_iommu_fwspec_ops(dev);</div><div class='del'>-	if (ops)</div><div class='del'>-		return ops;</div><div class='add'>+	if (ops) {</div><div class='add'>+		mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	err = iort_iommu_configure_id(dev, id_in);</div><div class='ctx'> 	if (err &amp;&amp; err != -EPROBE_DEFER)</div><div class='ctx'> 		err = viot_iommu_configure(dev);</div><div class='add'>+	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we have reason to believe the IOMMU driver missed the initial</div><div class='hunk'>@@ -1589,12 +1592,14 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	/* Ignore all other errors apart from EPROBE_DEFER */</div><div class='ctx'> 	if (err == -EPROBE_DEFER) {</div><div class='del'>-		return ERR_PTR(err);</div><div class='add'>+		return err;</div><div class='ctx'> 	} else if (err) {</div><div class='ctx'> 		dev_dbg(dev, "Adding to IOMMU failed: %d\n", err);</div><div class='del'>-		return NULL;</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> 	}</div><div class='del'>-	return acpi_iommu_fwspec_ops(dev);</div><div class='add'>+	if (!acpi_iommu_fwspec_ops(dev))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #else /* !CONFIG_IOMMU_API */</div><div class='hunk'>@@ -1606,10 +1611,9 @@ int acpi_iommu_fwspec_init(struct device *dev, u32 id,</div><div class='ctx'> 	return -ENODEV;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev,</div><div class='del'>-						       const u32 *id_in)</div><div class='add'>+static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in)</div><div class='ctx'> {</div><div class='del'>-	return NULL;</div><div class='add'>+	return -ENODEV;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #endif /* !CONFIG_IOMMU_API */</div><div class='hunk'>@@ -1623,7 +1627,7 @@ static const struct iommu_ops *acpi_iommu_configure_id(struct device *dev,</div><div class='ctx'> int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr,</div><div class='ctx'> 			  const u32 *input_id)</div><div class='ctx'> {</div><div class='del'>-	const struct iommu_ops *iommu;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (attr == DEV_DMA_NOT_SUPPORTED) {</div><div class='ctx'> 		set_dma_ops(dev, &amp;dma_dummy_ops);</div><div class='hunk'>@@ -1632,12 +1636,16 @@ int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr,</div><div class='ctx'> </div><div class='ctx'> 	acpi_arch_dma_setup(dev);</div><div class='ctx'> </div><div class='del'>-	iommu = acpi_iommu_configure_id(dev, input_id);</div><div class='del'>-	if (PTR_ERR(iommu) == -EPROBE_DEFER)</div><div class='add'>+	ret = acpi_iommu_configure_id(dev, input_id);</div><div class='add'>+	if (ret == -EPROBE_DEFER)</div><div class='ctx'> 		return -EPROBE_DEFER;</div><div class='ctx'> </div><div class='del'>-	arch_setup_dma_ops(dev, 0, U64_MAX,</div><div class='del'>-				iommu, attr == DEV_DMA_COHERENT);</div><div class='add'>+	/*</div><div class='add'>+	 * Historically this routine doesn't fail driver probing due to errors</div><div class='add'>+	 * in acpi_iommu_configure_id()</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	arch_setup_dma_ops(dev, 0, U64_MAX, attr == DEV_DMA_COHERENT);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1727,6 +1735,7 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device)</div><div class='ctx'> 	 * Some ACPI devs contain SerialBus resources even though they are not</div><div class='ctx'> 	 * attached to a serial bus at all.</div><div class='ctx'> 	 */</div><div class='add'>+		{ACPI_VIDEO_HID, },</div><div class='ctx'> 		{"MSHW0028", },</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * HIDs of device with an UartSerialBusV2 resource for which userspace</div><div class='hunk'>@@ -1976,10 +1985,9 @@ static void acpi_scan_init_hotplug(struct acpi_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 acpi_scan_check_dep(acpi_handle handle, bool check_dep)</div><div class='add'>+static u32 acpi_scan_check_dep(acpi_handle handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_handle_list dep_devices;</div><div class='del'>-	acpi_status status;</div><div class='ctx'> 	u32 count;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -1989,12 +1997,10 @@ static u32 acpi_scan_check_dep(acpi_handle handle, bool check_dep)</div><div class='ctx'> 	 * 2. ACPI nodes describing USB ports.</div><div class='ctx'> 	 * Still, checking for _HID catches more then just these cases ...</div><div class='ctx'> 	 */</div><div class='del'>-	if (!check_dep || !acpi_has_method(handle, "_DEP") ||</div><div class='del'>-	    !acpi_has_method(handle, "_HID"))</div><div class='add'>+	if (!acpi_has_method(handle, "_DEP") || !acpi_has_method(handle, "_HID"))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_reference(handle, "_DEP", NULL, &amp;dep_devices);</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='add'>+	if (!acpi_evaluate_reference(handle, "_DEP", NULL, &amp;dep_devices)) {</div><div class='ctx'> 		acpi_handle_debug(handle, "Failed to evaluate _DEP.\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2003,6 +2009,7 @@ static u32 acpi_scan_check_dep(acpi_handle handle, bool check_dep)</div><div class='ctx'> 		struct acpi_device_info *info;</div><div class='ctx'> 		struct acpi_dep_data *dep;</div><div class='ctx'> 		bool skip, honor_dep;</div><div class='add'>+		acpi_status status;</div><div class='ctx'> </div><div class='ctx'> 		status = acpi_get_object_info(dep_devices.handles[i], &amp;info);</div><div class='ctx'> 		if (ACPI_FAILURE(status)) {</div><div class='hunk'>@@ -2036,7 +2043,13 @@ static u32 acpi_scan_check_dep(acpi_handle handle, bool check_dep)</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static acpi_status acpi_bus_check_add(acpi_handle handle, bool check_dep,</div><div class='add'>+static acpi_status acpi_scan_check_crs_csi2_cb(acpi_handle handle, u32 a, void *b, void **c)</div><div class='add'>+{</div><div class='add'>+	acpi_mipi_check_crs_csi2(handle);</div><div class='add'>+	return AE_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static acpi_status acpi_bus_check_add(acpi_handle handle, bool first_pass,</div><div class='ctx'> 				      struct acpi_device **adev_p)</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_device *device = acpi_fetch_acpi_dev(handle);</div><div class='hunk'>@@ -2054,9 +2067,25 @@ static acpi_status acpi_bus_check_add(acpi_handle handle, bool check_dep,</div><div class='ctx'> 		if (acpi_device_should_be_hidden(handle))</div><div class='ctx'> 			return AE_OK;</div><div class='ctx'> </div><div class='del'>-		/* Bail out if there are dependencies. */</div><div class='del'>-		if (acpi_scan_check_dep(handle, check_dep) &gt; 0)</div><div class='del'>-			return AE_CTRL_DEPTH;</div><div class='add'>+		if (first_pass) {</div><div class='add'>+			acpi_mipi_check_crs_csi2(handle);</div><div class='add'>+</div><div class='add'>+			/* Bail out if there are dependencies. */</div><div class='add'>+			if (acpi_scan_check_dep(handle) &gt; 0) {</div><div class='add'>+				/*</div><div class='add'>+				 * The entire CSI-2 connection graph needs to be</div><div class='add'>+				 * extracted before any drivers or scan handlers</div><div class='add'>+				 * are bound to struct device objects, so scan</div><div class='add'>+				 * _CRS CSI-2 resource descriptors for all</div><div class='add'>+				 * devices below the current handle.</div><div class='add'>+				 */</div><div class='add'>+				acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,</div><div class='add'>+						    ACPI_UINT32_MAX,</div><div class='add'>+						    acpi_scan_check_crs_csi2_cb,</div><div class='add'>+						    NULL, NULL, NULL);</div><div class='add'>+				return AE_CTRL_DEPTH;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case ACPI_TYPE_ANY:	/* for ACPI_ROOT_OBJECT */</div><div class='hunk'>@@ -2079,10 +2108,10 @@ static acpi_status acpi_bus_check_add(acpi_handle handle, bool check_dep,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * If check_dep is true at this point, the device has no dependencies,</div><div class='add'>+	 * If first_pass is true at this point, the device has no dependencies,</div><div class='ctx'> 	 * or the creation of the device object would have been postponed above.</div><div class='ctx'> 	 */</div><div class='del'>-	acpi_add_single_object(&amp;device, handle, type, !check_dep);</div><div class='add'>+	acpi_add_single_object(&amp;device, handle, type, !first_pass);</div><div class='ctx'> 	if (!device)</div><div class='ctx'> 		return AE_CTRL_DEPTH;</div><div class='ctx'> </div><div class='hunk'>@@ -2426,6 +2455,13 @@ static void acpi_scan_postponed_branch(acpi_handle handle)</div><div class='ctx'> </div><div class='ctx'> 	acpi_walk_namespace(ACPI_TYPE_ANY, handle, ACPI_UINT32_MAX,</div><div class='ctx'> 			    acpi_bus_check_add_2, NULL, NULL, (void **)&amp;adev);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Populate the ACPI _CRS CSI-2 software nodes for the ACPI devices that</div><div class='add'>+	 * have been added above.</div><div class='add'>+	 */</div><div class='add'>+	acpi_mipi_init_crs_csi2_swnodes();</div><div class='add'>+</div><div class='ctx'> 	acpi_bus_attach(adev, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2494,12 +2530,22 @@ int acpi_bus_scan(acpi_handle handle)</div><div class='ctx'> 	if (!device)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Set up ACPI _CRS CSI-2 software nodes using information extracted</div><div class='add'>+	 * from the _CRS CSI-2 resource descriptors during the ACPI namespace</div><div class='add'>+	 * walk above and MIPI DisCo for Imaging device properties.</div><div class='add'>+	 */</div><div class='add'>+	acpi_mipi_scan_crs_csi2();</div><div class='add'>+	acpi_mipi_init_crs_csi2_swnodes();</div><div class='add'>+</div><div class='ctx'> 	acpi_bus_attach(device, (void *)true);</div><div class='ctx'> </div><div class='ctx'> 	/* Pass 2: Enumerate all of the remaining devices. */</div><div class='ctx'> </div><div class='ctx'> 	acpi_scan_postponed();</div><div class='ctx'> </div><div class='add'>+	acpi_mipi_crs_csi2_cleanup();</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(acpi_bus_scan);</div><div class='head'>diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c<br/>index c1516337f668..b07f7d091d13 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/tables.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/tables.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/tables.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/tables.c</a></div><div class='hunk'>@@ -251,8 +251,9 @@ int __init_or_acpilib acpi_table_parse_entries_array(</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	count = acpi_parse_entries_array(id, table_size, table_header,</div><div class='del'>-			proc, proc_num, max_entries);</div><div class='add'>+	count = acpi_parse_entries_array(id, table_size,</div><div class='add'>+					 (union fw_table_header *)table_header,</div><div class='add'>+					 proc, proc_num, max_entries);</div><div class='ctx'> </div><div class='ctx'> 	acpi_put_table(table_header);</div><div class='ctx'> 	return count;</div><div class='head'>diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c<br/>index f74d81abdbfc..4748e8061253 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/thermal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/thermal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/thermal.c</a></div><div class='hunk'>@@ -31,6 +31,8 @@</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> #include &lt;linux/units.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "internal.h"</div><div class='add'>+</div><div class='ctx'> #define ACPI_THERMAL_CLASS		"thermal_zone"</div><div class='ctx'> #define ACPI_THERMAL_DEVICE_NAME	"Thermal Zone"</div><div class='ctx'> #define ACPI_THERMAL_NOTIFY_TEMPERATURE	0x80</div><div class='hunk'>@@ -90,7 +92,7 @@ struct acpi_thermal_passive {</div><div class='ctx'> 	struct acpi_thermal_trip trip;</div><div class='ctx'> 	unsigned long tc1;</div><div class='ctx'> 	unsigned long tc2;</div><div class='del'>-	unsigned long tsp;</div><div class='add'>+	unsigned long delay;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct acpi_thermal_active {</div><div class='hunk'>@@ -188,24 +190,19 @@ static int active_trip_index(struct acpi_thermal *tz,</div><div class='ctx'> </div><div class='ctx'> static long get_passive_temp(struct acpi_thermal *tz)</div><div class='ctx'> {</div><div class='del'>-	unsigned long long tmp;</div><div class='del'>-	acpi_status status;</div><div class='add'>+	int temp;</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, "_PSV", NULL, &amp;tmp);</div><div class='del'>-	if (ACPI_FAILURE(status))</div><div class='add'>+	if (acpi_passive_trip_temp(tz-&gt;device, &amp;temp))</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='ctx'> </div><div class='del'>-	return tmp;</div><div class='add'>+	return temp;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static long get_active_temp(struct acpi_thermal *tz, int index)</div><div class='ctx'> {</div><div class='del'>-	char method[] = { '_', 'A', 'C', '0' + index, '\0' };</div><div class='del'>-	unsigned long long tmp;</div><div class='del'>-	acpi_status status;</div><div class='add'>+	int temp;</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, method, NULL, &amp;tmp);</div><div class='del'>-	if (ACPI_FAILURE(status))</div><div class='add'>+	if (acpi_active_trip_temp(tz-&gt;device, index, &amp;temp))</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -215,10 +212,10 @@ static long get_active_temp(struct acpi_thermal *tz, int index)</div><div class='ctx'> 	if (act &gt; 0) {</div><div class='ctx'> 		unsigned long long override = celsius_to_deci_kelvin(act);</div><div class='ctx'> </div><div class='del'>-		if (tmp &gt; override)</div><div class='del'>-			tmp = override;</div><div class='add'>+		if (temp &gt; override)</div><div class='add'>+			return override;</div><div class='ctx'> 	}</div><div class='del'>-	return tmp;</div><div class='add'>+	return temp;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void acpi_thermal_update_trip(struct acpi_thermal *tz,</div><div class='hunk'>@@ -247,7 +244,6 @@ static bool update_trip_devices(struct acpi_thermal *tz,</div><div class='ctx'> {</div><div class='ctx'> 	struct acpi_handle_list devices = { 0 };</div><div class='ctx'> 	char method[] = "_PSL";</div><div class='del'>-	acpi_status status;</div><div class='ctx'> </div><div class='ctx'> 	if (index != ACPI_THERMAL_TRIP_PASSIVE) {</div><div class='ctx'> 		method[1] = 'A';</div><div class='hunk'>@@ -255,8 +251,7 @@ static bool update_trip_devices(struct acpi_thermal *tz,</div><div class='ctx'> 		method[3] = '0' + index;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_reference(tz-&gt;device-&gt;handle, method, NULL, &amp;devices);</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='add'>+	if (!acpi_evaluate_reference(tz-&gt;device-&gt;handle, method, NULL, &amp;devices)) {</div><div class='ctx'> 		acpi_handle_info(tz-&gt;device-&gt;handle, "%s evaluation failure\n", method);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -297,6 +292,7 @@ static int acpi_thermal_adjust_trip(struct thermal_trip *trip, void *data)</div><div class='ctx'> 	struct acpi_thermal_trip *acpi_trip = trip-&gt;priv;</div><div class='ctx'> 	struct adjust_trip_data *atd = data;</div><div class='ctx'> 	struct acpi_thermal *tz = atd-&gt;tz;</div><div class='add'>+	int temp;</div><div class='ctx'> </div><div class='ctx'> 	if (!acpi_trip || !acpi_thermal_trip_valid(acpi_trip))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -307,9 +303,11 @@ static int acpi_thermal_adjust_trip(struct thermal_trip *trip, void *data)</div><div class='ctx'> 		acpi_thermal_update_trip_devices(tz, trip);</div><div class='ctx'> </div><div class='ctx'> 	if (acpi_thermal_trip_valid(acpi_trip))</div><div class='del'>-		trip-&gt;temperature = acpi_thermal_temp(tz, acpi_trip-&gt;temp_dk);</div><div class='add'>+		temp = acpi_thermal_temp(tz, acpi_trip-&gt;temp_dk);</div><div class='ctx'> 	else</div><div class='del'>-		trip-&gt;temperature = THERMAL_TEMP_INVALID;</div><div class='add'>+		temp = THERMAL_TEMP_INVALID;</div><div class='add'>+</div><div class='add'>+	thermal_zone_set_trip_temp(tz-&gt;thermal_zone, trip, temp);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -339,13 +337,12 @@ static void acpi_thermal_trips_update(struct acpi_thermal *tz, u32 event)</div><div class='ctx'> 					dev_name(&amp;adev-&gt;dev), event, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long acpi_thermal_get_critical_trip(struct acpi_thermal *tz)</div><div class='add'>+static int acpi_thermal_get_critical_trip(struct acpi_thermal *tz)</div><div class='ctx'> {</div><div class='del'>-	unsigned long long tmp;</div><div class='del'>-	acpi_status status;</div><div class='add'>+	int temp;</div><div class='ctx'> </div><div class='ctx'> 	if (crt &gt; 0) {</div><div class='del'>-		tmp = celsius_to_deci_kelvin(crt);</div><div class='add'>+		temp = celsius_to_deci_kelvin(crt);</div><div class='ctx'> 		goto set;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (crt == -1) {</div><div class='hunk'>@@ -353,38 +350,34 @@ static long acpi_thermal_get_critical_trip(struct acpi_thermal *tz)</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, "_CRT", NULL, &amp;tmp);</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='del'>-		acpi_handle_debug(tz-&gt;device-&gt;handle, "No critical threshold\n");</div><div class='add'>+	if (acpi_critical_trip_temp(tz-&gt;device, &amp;temp))</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='del'>-	}</div><div class='del'>-	if (tmp &lt;= 2732) {</div><div class='add'>+</div><div class='add'>+	if (temp &lt;= 2732) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Below zero (Celsius) values clearly aren't right for sure,</div><div class='ctx'> 		 * so discard them as invalid.</div><div class='ctx'> 		 */</div><div class='del'>-		pr_info(FW_BUG "Invalid critical threshold (%llu)\n", tmp);</div><div class='add'>+		pr_info(FW_BUG "Invalid critical threshold (%d)\n", temp);</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> set:</div><div class='del'>-	acpi_handle_debug(tz-&gt;device-&gt;handle, "Critical threshold [%llu]\n", tmp);</div><div class='del'>-	return tmp;</div><div class='add'>+	acpi_handle_debug(tz-&gt;device-&gt;handle, "Critical threshold [%d]\n", temp);</div><div class='add'>+	return temp;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long acpi_thermal_get_hot_trip(struct acpi_thermal *tz)</div><div class='add'>+static int acpi_thermal_get_hot_trip(struct acpi_thermal *tz)</div><div class='ctx'> {</div><div class='del'>-	unsigned long long tmp;</div><div class='del'>-	acpi_status status;</div><div class='add'>+	int temp;</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, "_HOT", NULL, &amp;tmp);</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='add'>+	if (acpi_hot_trip_temp(tz-&gt;device, &amp;temp) || temp == THERMAL_TEMP_INVALID) {</div><div class='ctx'> 		acpi_handle_debug(tz-&gt;device-&gt;handle, "No hot threshold\n");</div><div class='ctx'> 		return THERMAL_TEMP_INVALID;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	acpi_handle_debug(tz-&gt;device-&gt;handle, "Hot threshold [%llu]\n", tmp);</div><div class='del'>-	return tmp;</div><div class='add'>+	acpi_handle_debug(tz-&gt;device-&gt;handle, "Hot threshold [%d]\n", temp);</div><div class='add'>+	return temp;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool passive_trip_params_init(struct acpi_thermal *tz)</div><div class='hunk'>@@ -404,11 +397,17 @@ static bool passive_trip_params_init(struct acpi_thermal *tz)</div><div class='ctx'> </div><div class='ctx'> 	tz-&gt;trips.passive.tc2 = tmp;</div><div class='ctx'> </div><div class='add'>+	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, "_TFP", NULL, &amp;tmp);</div><div class='add'>+	if (ACPI_SUCCESS(status)) {</div><div class='add'>+		tz-&gt;trips.passive.delay = tmp;</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	status = acpi_evaluate_integer(tz-&gt;device-&gt;handle, "_TSP", NULL, &amp;tmp);</div><div class='ctx'> 	if (ACPI_FAILURE(status))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	tz-&gt;trips.passive.tsp = tmp;</div><div class='add'>+	tz-&gt;trips.passive.delay = tmp * 100;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -904,7 +903,7 @@ static int acpi_thermal_add(struct acpi_device *device)</div><div class='ctx'> </div><div class='ctx'> 	acpi_trip = &amp;tz-&gt;trips.passive.trip;</div><div class='ctx'> 	if (acpi_thermal_trip_valid(acpi_trip)) {</div><div class='del'>-		passive_delay = tz-&gt;trips.passive.tsp * 100;</div><div class='add'>+		passive_delay = tz-&gt;trips.passive.delay;</div><div class='ctx'> </div><div class='ctx'> 		trip-&gt;type = THERMAL_TRIP_PASSIVE;</div><div class='ctx'> 		trip-&gt;temperature = acpi_thermal_temp(tz, acpi_trip-&gt;temp_dk);</div><div class='hunk'>@@ -1142,6 +1141,7 @@ static void __exit acpi_thermal_exit(void)</div><div class='ctx'> module_init(acpi_thermal_init);</div><div class='ctx'> module_exit(acpi_thermal_exit);</div><div class='ctx'> </div><div class='add'>+MODULE_IMPORT_NS(ACPI_THERMAL);</div><div class='ctx'> MODULE_AUTHOR("Paul Diefenbaugh");</div><div class='ctx'> MODULE_DESCRIPTION("ACPI Thermal Zone Driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/thermal/thermal_acpi.c b/drivers/acpi/thermal_lib.c<br/>index 43eaf0f2ff49..4e0519ca9739 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/thermal/thermal_acpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/thermal/thermal_acpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/thermal_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/thermal_lib.c</a></div><div class='hunk'>@@ -3,12 +3,13 @@</div><div class='ctx'>  * Copyright 2023 Linaro Limited</div><div class='ctx'>  * Copyright 2023 Intel Corporation</div><div class='ctx'>  *</div><div class='del'>- * Library routines for populating a generic thermal trip point structure</div><div class='del'>- * with data obtained by evaluating a specific object in the ACPI Namespace.</div><div class='add'>+ * Library routines for retrieving trip point temperature values from the</div><div class='add'>+ * platform firmware via ACPI.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/units.h&gt;</div><div class='ctx'> #include &lt;linux/thermal.h&gt;</div><div class='add'>+#include "internal.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Minimum temperature for full military grade is 218°K (-55°C) and</div><div class='hunk'>@@ -17,11 +18,11 @@</div><div class='ctx'>  * firmware. Any values out of these boundaries may be considered</div><div class='ctx'>  * bogus and we can assume the firmware has no data to provide.</div><div class='ctx'>  */</div><div class='del'>-#define TEMP_MIN_DECIK	2180</div><div class='del'>-#define TEMP_MAX_DECIK	4480</div><div class='add'>+#define TEMP_MIN_DECIK	2180ULL</div><div class='add'>+#define TEMP_MAX_DECIK	4480ULL</div><div class='ctx'> </div><div class='del'>-static int thermal_acpi_trip_temp(struct acpi_device *adev, char *obj_name,</div><div class='del'>-				  int *ret_temp)</div><div class='add'>+static int acpi_trip_temp(struct acpi_device *adev, char *obj_name,</div><div class='add'>+			  int *ret_temp)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long long temp;</div><div class='ctx'> 	acpi_status status;</div><div class='hunk'>@@ -33,7 +34,7 @@ static int thermal_acpi_trip_temp(struct acpi_device *adev, char *obj_name,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (temp &gt;= TEMP_MIN_DECIK &amp;&amp; temp &lt;= TEMP_MAX_DECIK) {</div><div class='del'>-		*ret_temp = deci_kelvin_to_millicelsius(temp);</div><div class='add'>+		*ret_temp = temp;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		acpi_handle_debug(adev-&gt;handle, "%s result %llu out of range\n",</div><div class='ctx'> 				  obj_name, temp);</div><div class='hunk'>@@ -43,6 +44,48 @@ static int thermal_acpi_trip_temp(struct acpi_device *adev, char *obj_name,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp)</div><div class='add'>+{</div><div class='add'>+	char obj_name[] = {'_', 'A', 'C', '0' + id, '\0'};</div><div class='add'>+</div><div class='add'>+	if (id &lt; 0 || id &gt; 9)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return acpi_trip_temp(adev, obj_name, ret_temp);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(acpi_active_trip_temp, ACPI_THERMAL);</div><div class='add'>+</div><div class='add'>+int acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='add'>+{</div><div class='add'>+	return acpi_trip_temp(adev, "_PSV", ret_temp);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(acpi_passive_trip_temp, ACPI_THERMAL);</div><div class='add'>+</div><div class='add'>+int acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='add'>+{</div><div class='add'>+	return acpi_trip_temp(adev, "_HOT", ret_temp);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(acpi_hot_trip_temp, ACPI_THERMAL);</div><div class='add'>+</div><div class='add'>+int acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='add'>+{</div><div class='add'>+	return acpi_trip_temp(adev, "_CRT", ret_temp);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(acpi_critical_trip_temp, ACPI_THERMAL);</div><div class='add'>+</div><div class='add'>+static int thermal_temp(int error, int temp_decik, int *ret_temp)</div><div class='add'>+{</div><div class='add'>+	if (error)</div><div class='add'>+		return error;</div><div class='add'>+</div><div class='add'>+	if (temp_decik == THERMAL_TEMP_INVALID)</div><div class='add'>+		*ret_temp = THERMAL_TEMP_INVALID;</div><div class='add'>+	else</div><div class='add'>+		*ret_temp = deci_kelvin_to_millicelsius(temp_decik);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * thermal_acpi_active_trip_temp - Retrieve active trip point temperature</div><div class='ctx'>  * @adev: Target thermal zone ACPI device object.</div><div class='hunk'>@@ -57,12 +100,10 @@ static int thermal_acpi_trip_temp(struct acpi_device *adev, char *obj_name,</div><div class='ctx'>  */</div><div class='ctx'> int thermal_acpi_active_trip_temp(struct acpi_device *adev, int id, int *ret_temp)</div><div class='ctx'> {</div><div class='del'>-	char obj_name[] = {'_', 'A', 'C', '0' + id, '\0'};</div><div class='del'>-</div><div class='del'>-	if (id &lt; 0 || id &gt; 9)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	int temp_decik;</div><div class='add'>+	int ret = acpi_active_trip_temp(adev, id, &amp;temp_decik);</div><div class='ctx'> </div><div class='del'>-	return thermal_acpi_trip_temp(adev, obj_name, ret_temp);</div><div class='add'>+	return thermal_temp(ret, temp_decik, ret_temp);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(thermal_acpi_active_trip_temp);</div><div class='ctx'> </div><div class='hunk'>@@ -78,7 +119,10 @@ EXPORT_SYMBOL_GPL(thermal_acpi_active_trip_temp);</div><div class='ctx'>  */</div><div class='ctx'> int thermal_acpi_passive_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='ctx'> {</div><div class='del'>-	return thermal_acpi_trip_temp(adev, "_PSV", ret_temp);</div><div class='add'>+	int temp_decik;</div><div class='add'>+	int ret = acpi_passive_trip_temp(adev, &amp;temp_decik);</div><div class='add'>+</div><div class='add'>+	return thermal_temp(ret, temp_decik, ret_temp);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(thermal_acpi_passive_trip_temp);</div><div class='ctx'> </div><div class='hunk'>@@ -95,7 +139,10 @@ EXPORT_SYMBOL_GPL(thermal_acpi_passive_trip_temp);</div><div class='ctx'>  */</div><div class='ctx'> int thermal_acpi_hot_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='ctx'> {</div><div class='del'>-	return thermal_acpi_trip_temp(adev, "_HOT", ret_temp);</div><div class='add'>+	int temp_decik;</div><div class='add'>+	int ret = acpi_hot_trip_temp(adev, &amp;temp_decik);</div><div class='add'>+</div><div class='add'>+	return thermal_temp(ret, temp_decik, ret_temp);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(thermal_acpi_hot_trip_temp);</div><div class='ctx'> </div><div class='hunk'>@@ -111,6 +158,9 @@ EXPORT_SYMBOL_GPL(thermal_acpi_hot_trip_temp);</div><div class='ctx'>  */</div><div class='ctx'> int thermal_acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp)</div><div class='ctx'> {</div><div class='del'>-	return thermal_acpi_trip_temp(adev, "_CRT", ret_temp);</div><div class='add'>+	int temp_decik;</div><div class='add'>+	int ret = acpi_critical_trip_temp(adev, &amp;temp_decik);</div><div class='add'>+</div><div class='add'>+	return thermal_temp(ret, temp_decik, ret_temp);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(thermal_acpi_critical_trip_temp);</div><div class='head'>diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c<br/>index 28c75242fca9..abac5cc25477 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/acpi/utils.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/acpi/utils.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/acpi/utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/acpi/utils.c</a></div><div class='hunk'>@@ -329,21 +329,18 @@ const char *acpi_get_subsystem_id(acpi_handle handle)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(acpi_get_subsystem_id);</div><div class='ctx'> </div><div class='del'>-acpi_status</div><div class='del'>-acpi_evaluate_reference(acpi_handle handle,</div><div class='del'>-			acpi_string pathname,</div><div class='del'>-			struct acpi_object_list *arguments,</div><div class='del'>-			struct acpi_handle_list *list)</div><div class='add'>+bool acpi_evaluate_reference(acpi_handle handle, acpi_string pathname,</div><div class='add'>+			     struct acpi_object_list *arguments,</div><div class='add'>+			     struct acpi_handle_list *list)</div><div class='ctx'> {</div><div class='del'>-	acpi_status status = AE_OK;</div><div class='del'>-	union acpi_object *package = NULL;</div><div class='del'>-	union acpi_object *element = NULL;</div><div class='ctx'> 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };</div><div class='del'>-	u32 i = 0;</div><div class='del'>-</div><div class='add'>+	union acpi_object *package;</div><div class='add'>+	acpi_status status;</div><div class='add'>+	bool ret = false;</div><div class='add'>+	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	if (!list)</div><div class='del'>-		return AE_BAD_PARAMETER;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* Evaluate object. */</div><div class='ctx'> </div><div class='hunk'>@@ -353,62 +350,47 @@ acpi_evaluate_reference(acpi_handle handle,</div><div class='ctx'> </div><div class='ctx'> 	package = buffer.pointer;</div><div class='ctx'> </div><div class='del'>-	if ((buffer.length == 0) || !package) {</div><div class='del'>-		status = AE_BAD_DATA;</div><div class='del'>-		acpi_util_eval_error(handle, pathname, status);</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='del'>-	if (package-&gt;type != ACPI_TYPE_PACKAGE) {</div><div class='del'>-		status = AE_BAD_DATA;</div><div class='del'>-		acpi_util_eval_error(handle, pathname, status);</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='del'>-	if (!package-&gt;package.count) {</div><div class='del'>-		status = AE_BAD_DATA;</div><div class='del'>-		acpi_util_eval_error(handle, pathname, status);</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='add'>+	if (buffer.length == 0 || !package ||</div><div class='add'>+	    package-&gt;type != ACPI_TYPE_PACKAGE || !package-&gt;package.count)</div><div class='add'>+		goto err;</div><div class='ctx'> </div><div class='del'>-	list-&gt;handles = kcalloc(package-&gt;package.count, sizeof(*list-&gt;handles), GFP_KERNEL);</div><div class='del'>-	if (!list-&gt;handles) {</div><div class='del'>-		kfree(package);</div><div class='del'>-		return AE_NO_MEMORY;</div><div class='del'>-	}</div><div class='ctx'> 	list-&gt;count = package-&gt;package.count;</div><div class='add'>+	list-&gt;handles = kcalloc(list-&gt;count, sizeof(*list-&gt;handles), GFP_KERNEL);</div><div class='add'>+	if (!list-&gt;handles)</div><div class='add'>+		goto err_clear;</div><div class='ctx'> </div><div class='ctx'> 	/* Extract package data. */</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; list-&gt;count; i++) {</div><div class='add'>+		union acpi_object *element = &amp;(package-&gt;package.elements[i]);</div><div class='ctx'> </div><div class='del'>-		element = &amp;(package-&gt;package.elements[i]);</div><div class='del'>-</div><div class='del'>-		if (element-&gt;type != ACPI_TYPE_LOCAL_REFERENCE) {</div><div class='del'>-			status = AE_BAD_DATA;</div><div class='del'>-			acpi_util_eval_error(handle, pathname, status);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='add'>+		if (element-&gt;type != ACPI_TYPE_LOCAL_REFERENCE ||</div><div class='add'>+		    !element-&gt;reference.handle)</div><div class='add'>+			goto err_free;</div><div class='ctx'> </div><div class='del'>-		if (!element-&gt;reference.handle) {</div><div class='del'>-			status = AE_NULL_ENTRY;</div><div class='del'>-			acpi_util_eval_error(handle, pathname, status);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='ctx'> 		/* Get the  acpi_handle. */</div><div class='ctx'> </div><div class='ctx'> 		list-&gt;handles[i] = element-&gt;reference.handle;</div><div class='ctx'> 		acpi_handle_debug(list-&gt;handles[i], "Found in reference list\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-end:</div><div class='del'>-	if (ACPI_FAILURE(status)) {</div><div class='del'>-		list-&gt;count = 0;</div><div class='del'>-		kfree(list-&gt;handles);</div><div class='del'>-		list-&gt;handles = NULL;</div><div class='del'>-	}</div><div class='add'>+	ret = true;</div><div class='ctx'> </div><div class='add'>+end:</div><div class='ctx'> 	kfree(buffer.pointer);</div><div class='ctx'> </div><div class='del'>-	return status;</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+err_free:</div><div class='add'>+	kfree(list-&gt;handles);</div><div class='add'>+	list-&gt;handles = NULL;</div><div class='add'>+</div><div class='add'>+err_clear:</div><div class='add'>+	list-&gt;count = 0;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	acpi_util_eval_error(handle, pathname, status);</div><div class='add'>+	goto end;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> EXPORT_SYMBOL(acpi_evaluate_reference);</div><div class='hunk'>@@ -426,7 +408,7 @@ bool acpi_handle_list_equal(struct acpi_handle_list *list1,</div><div class='ctx'> {</div><div class='ctx'> 	return list1-&gt;count == list2-&gt;count &amp;&amp;</div><div class='ctx'> 		!memcmp(list1-&gt;handles, list2-&gt;handles,</div><div class='del'>-		        list1-&gt;count * sizeof(acpi_handle));</div><div class='add'>+		        list1-&gt;count * sizeof(*list1-&gt;handles));</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(acpi_handle_list_equal);</div><div class='ctx'> </div><div class='hunk'>@@ -468,6 +450,40 @@ void acpi_handle_list_free(struct acpi_handle_list *list)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(acpi_handle_list_free);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * acpi_device_dep - Check ACPI device dependency</div><div class='add'>+ * @target: ACPI handle of the target ACPI device.</div><div class='add'>+ * @match: ACPI handle to look up in the target's _DEP list.</div><div class='add'>+ *</div><div class='add'>+ * Return true if @match is present in the list returned by _DEP for</div><div class='add'>+ * @target or false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool acpi_device_dep(acpi_handle target, acpi_handle match)</div><div class='add'>+{</div><div class='add'>+	struct acpi_handle_list dep_devices;</div><div class='add'>+	bool ret = false;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!acpi_has_method(target, "_DEP"))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!acpi_evaluate_reference(target, "_DEP", NULL, &amp;dep_devices)) {</div><div class='add'>+		acpi_handle_debug(target, "Failed to evaluate _DEP.\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dep_devices.count; i++) {</div><div class='add'>+		if (dep_devices.handles[i] == match) {</div><div class='add'>+			ret = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	acpi_handle_list_free(&amp;dep_devices);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(acpi_device_dep);</div><div class='add'>+</div><div class='ctx'> acpi_status</div><div class='ctx'> acpi_get_physical_device_location(acpi_handle handle, struct acpi_pld_info **pld)</div><div class='ctx'> {</div><div class='hunk'>@@ -825,54 +841,6 @@ bool acpi_check_dsm(acpi_handle handle, const guid_t *guid, u64 rev, u64 funcs)</div><div class='ctx'> EXPORT_SYMBOL(acpi_check_dsm);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * acpi_dev_uid_match - Match device by supplied UID</div><div class='del'>- * @adev: ACPI device to match.</div><div class='del'>- * @uid2: Unique ID of the device.</div><div class='del'>- *</div><div class='del'>- * Matches UID in @adev with given @uid2.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- *  - %true if matches.</div><div class='del'>- *  - %false otherwise.</div><div class='del'>- */</div><div class='del'>-bool acpi_dev_uid_match(struct acpi_device *adev, const char *uid2)</div><div class='del'>-{</div><div class='del'>-	const char *uid1 = acpi_device_uid(adev);</div><div class='del'>-</div><div class='del'>-	return uid1 &amp;&amp; uid2 &amp;&amp; !strcmp(uid1, uid2);</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(acpi_dev_uid_match);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * acpi_dev_hid_uid_match - Match device by supplied HID and UID</div><div class='del'>- * @adev: ACPI device to match.</div><div class='del'>- * @hid2: Hardware ID of the device.</div><div class='del'>- * @uid2: Unique ID of the device, pass NULL to not check _UID.</div><div class='del'>- *</div><div class='del'>- * Matches HID and UID in @adev with given @hid2 and @uid2. Absence of @uid2</div><div class='del'>- * will be treated as a match. If user wants to validate @uid2, it should be</div><div class='del'>- * done before calling this function.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- *  - %true if matches or @uid2 is NULL.</div><div class='del'>- *  - %false otherwise.</div><div class='del'>- */</div><div class='del'>-bool acpi_dev_hid_uid_match(struct acpi_device *adev,</div><div class='del'>-			    const char *hid2, const char *uid2)</div><div class='del'>-{</div><div class='del'>-	const char *hid1 = acpi_device_hid(adev);</div><div class='del'>-</div><div class='del'>-	if (strcmp(hid1, hid2))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	if (!uid2)</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	return acpi_dev_uid_match(adev, uid2);</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL(acpi_dev_hid_uid_match);</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * acpi_dev_uid_to_integer - treat ACPI device _UID as integer</div><div class='ctx'>  * @adev: ACPI device to get _UID from</div><div class='ctx'>  * @integer: output buffer for integer</div><div class='head'>diff --git a/drivers/android/binder.c b/drivers/android/binder.c<br/>index 92128aae2d06..8dd23b19e997 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder.c</a></div><div class='hunk'>@@ -1921,7 +1921,7 @@ static void binder_deferred_fd_close(int fd)</div><div class='ctx'> 	if (!twcb)</div><div class='ctx'> 		return;</div><div class='ctx'> 	init_task_work(&amp;twcb-&gt;twork, binder_do_fd_close);</div><div class='del'>-	twcb-&gt;file = close_fd_get_file(fd);</div><div class='add'>+	twcb-&gt;file = file_close_fd(fd);</div><div class='ctx'> 	if (twcb-&gt;file) {</div><div class='ctx'> 		// pin it until binder_do_fd_close(); see comments there</div><div class='ctx'> 		get_file(twcb-&gt;file);</div><div class='hunk'>@@ -2077,9 +2077,8 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,</div><div class='ctx'> 			 * Convert the address to an offset relative to</div><div class='ctx'> 			 * the base of the transaction buffer.</div><div class='ctx'> 			 */</div><div class='del'>-			fda_offset =</div><div class='del'>-			    (parent-&gt;buffer - (uintptr_t)buffer-&gt;user_data) +</div><div class='del'>-			    fda-&gt;parent_offset;</div><div class='add'>+			fda_offset = parent-&gt;buffer - buffer-&gt;user_data +</div><div class='add'>+				fda-&gt;parent_offset;</div><div class='ctx'> 			for (fd_index = 0; fd_index &lt; fda-&gt;num_fds;</div><div class='ctx'> 			     fd_index++) {</div><div class='ctx'> 				u32 fd;</div><div class='hunk'>@@ -2597,7 +2596,7 @@ static int binder_translate_fd_array(struct list_head *pf_head,</div><div class='ctx'> 	 * Convert the address to an offset relative to</div><div class='ctx'> 	 * the base of the transaction buffer.</div><div class='ctx'> 	 */</div><div class='del'>-	fda_offset = (parent-&gt;buffer - (uintptr_t)t-&gt;buffer-&gt;user_data) +</div><div class='add'>+	fda_offset = parent-&gt;buffer - t-&gt;buffer-&gt;user_data +</div><div class='ctx'> 		fda-&gt;parent_offset;</div><div class='ctx'> 	sender_ufda_base = (void __user *)(uintptr_t)sender_uparent-&gt;buffer +</div><div class='ctx'> 				fda-&gt;parent_offset;</div><div class='hunk'>@@ -2672,8 +2671,9 @@ static int binder_fixup_parent(struct list_head *pf_head,</div><div class='ctx'> 				  proc-&gt;pid, thread-&gt;pid);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	buffer_offset = bp-&gt;parent_offset +</div><div class='del'>-			(uintptr_t)parent-&gt;buffer - (uintptr_t)b-&gt;user_data;</div><div class='add'>+</div><div class='add'>+	buffer_offset = bp-&gt;parent_offset + parent-&gt;buffer - b-&gt;user_data;</div><div class='add'>+</div><div class='ctx'> 	return binder_add_fixup(pf_head, buffer_offset, bp-&gt;buffer, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3225,7 +3225,7 @@ static void binder_transaction(struct binder_proc *proc,</div><div class='ctx'> </div><div class='ctx'> 	t-&gt;buffer = binder_alloc_new_buf(&amp;target_proc-&gt;alloc, tr-&gt;data_size,</div><div class='ctx'> 		tr-&gt;offsets_size, extra_buffers_size,</div><div class='del'>-		!reply &amp;&amp; (t-&gt;flags &amp; TF_ONE_WAY), current-&gt;tgid);</div><div class='add'>+		!reply &amp;&amp; (t-&gt;flags &amp; TF_ONE_WAY));</div><div class='ctx'> 	if (IS_ERR(t-&gt;buffer)) {</div><div class='ctx'> 		char *s;</div><div class='ctx'> </div><div class='hunk'>@@ -3250,7 +3250,7 @@ static void binder_transaction(struct binder_proc *proc,</div><div class='ctx'> 				    ALIGN(extra_buffers_size, sizeof(void *)) -</div><div class='ctx'> 				    ALIGN(secctx_sz, sizeof(u64));</div><div class='ctx'> </div><div class='del'>-		t-&gt;security_ctx = (uintptr_t)t-&gt;buffer-&gt;user_data + buf_offset;</div><div class='add'>+		t-&gt;security_ctx = t-&gt;buffer-&gt;user_data + buf_offset;</div><div class='ctx'> 		err = binder_alloc_copy_to_buffer(&amp;target_proc-&gt;alloc,</div><div class='ctx'> 						  t-&gt;buffer, buf_offset,</div><div class='ctx'> 						  secctx, secctx_sz);</div><div class='hunk'>@@ -3527,8 +3527,7 @@ static void binder_transaction(struct binder_proc *proc,</div><div class='ctx'> 				goto err_translate_failed;</div><div class='ctx'> 			}</div><div class='ctx'> 			/* Fixup buffer pointer to target proc address space */</div><div class='del'>-			bp-&gt;buffer = (uintptr_t)</div><div class='del'>-				t-&gt;buffer-&gt;user_data + sg_buf_offset;</div><div class='add'>+			bp-&gt;buffer = t-&gt;buffer-&gt;user_data + sg_buf_offset;</div><div class='ctx'> 			sg_buf_offset += ALIGN(bp-&gt;length, sizeof(u64));</div><div class='ctx'> </div><div class='ctx'> 			num_valid = (buffer_offset - off_start_offset) /</div><div class='hunk'>@@ -4698,7 +4697,7 @@ retry:</div><div class='ctx'> 		}</div><div class='ctx'> 		trd-&gt;data_size = t-&gt;buffer-&gt;data_size;</div><div class='ctx'> 		trd-&gt;offsets_size = t-&gt;buffer-&gt;offsets_size;</div><div class='del'>-		trd-&gt;data.ptr.buffer = (uintptr_t)t-&gt;buffer-&gt;user_data;</div><div class='add'>+		trd-&gt;data.ptr.buffer = t-&gt;buffer-&gt;user_data;</div><div class='ctx'> 		trd-&gt;data.ptr.offsets = trd-&gt;data.ptr.buffer +</div><div class='ctx'> 					ALIGN(t-&gt;buffer-&gt;data_size,</div><div class='ctx'> 					    sizeof(void *));</div><div class='hunk'>@@ -5030,7 +5029,7 @@ static __poll_t binder_poll(struct file *filp,</div><div class='ctx'> </div><div class='ctx'> 	thread = binder_get_thread(proc);</div><div class='ctx'> 	if (!thread)</div><div class='del'>-		return POLLERR;</div><div class='add'>+		return EPOLLERR;</div><div class='ctx'> </div><div class='ctx'> 	binder_inner_proc_lock(thread-&gt;proc);</div><div class='ctx'> 	thread-&gt;looper |= BINDER_LOOPER_STATE_POLL;</div><div class='hunk'>@@ -5981,9 +5980,9 @@ static void print_binder_transaction_ilocked(struct seq_file *m,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (buffer-&gt;target_node)</div><div class='ctx'> 		seq_printf(m, " node %d", buffer-&gt;target_node-&gt;debug_id);</div><div class='del'>-	seq_printf(m, " size %zd:%zd data %pK\n",</div><div class='add'>+	seq_printf(m, " size %zd:%zd offset %lx\n",</div><div class='ctx'> 		   buffer-&gt;data_size, buffer-&gt;offsets_size,</div><div class='del'>-		   buffer-&gt;user_data);</div><div class='add'>+		   proc-&gt;alloc.buffer - buffer-&gt;user_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void print_binder_work_ilocked(struct seq_file *m,</div><div class='head'>diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c<br/>index 138f6d43d13b..e0e4dc38b692 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binder_alloc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #include "binder_alloc.h"</div><div class='ctx'> #include "binder_trace.h"</div><div class='ctx'> </div><div class='del'>-struct list_lru binder_alloc_lru;</div><div class='add'>+struct list_lru binder_freelist;</div><div class='ctx'> </div><div class='ctx'> static DEFINE_MUTEX(binder_alloc_mmap_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -125,23 +125,20 @@ static void binder_insert_allocated_buffer_locked(</div><div class='ctx'> </div><div class='ctx'> static struct binder_buffer *binder_alloc_prepare_to_free_locked(</div><div class='ctx'> 		struct binder_alloc *alloc,</div><div class='del'>-		uintptr_t user_ptr)</div><div class='add'>+		unsigned long user_ptr)</div><div class='ctx'> {</div><div class='ctx'> 	struct rb_node *n = alloc-&gt;allocated_buffers.rb_node;</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='del'>-	void __user *uptr;</div><div class='del'>-</div><div class='del'>-	uptr = (void __user *)user_ptr;</div><div class='ctx'> </div><div class='ctx'> 	while (n) {</div><div class='ctx'> 		buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='ctx'> 		BUG_ON(buffer-&gt;free);</div><div class='ctx'> </div><div class='del'>-		if (uptr &lt; buffer-&gt;user_data)</div><div class='add'>+		if (user_ptr &lt; buffer-&gt;user_data) {</div><div class='ctx'> 			n = n-&gt;rb_left;</div><div class='del'>-		else if (uptr &gt; buffer-&gt;user_data)</div><div class='add'>+		} else if (user_ptr &gt; buffer-&gt;user_data) {</div><div class='ctx'> 			n = n-&gt;rb_right;</div><div class='del'>-		else {</div><div class='add'>+		} else {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Guard against user threads attempting to</div><div class='ctx'> 			 * free the buffer when in use by kernel or</div><div class='hunk'>@@ -168,145 +165,168 @@ static struct binder_buffer *binder_alloc_prepare_to_free_locked(</div><div class='ctx'>  * Return:	Pointer to buffer or NULL</div><div class='ctx'>  */</div><div class='ctx'> struct binder_buffer *binder_alloc_prepare_to_free(struct binder_alloc *alloc,</div><div class='del'>-						   uintptr_t user_ptr)</div><div class='add'>+						   unsigned long user_ptr)</div><div class='ctx'> {</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	buffer = binder_alloc_prepare_to_free_locked(alloc, user_ptr);</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	return buffer;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int binder_update_page_range(struct binder_alloc *alloc, int allocate,</div><div class='del'>-				    void __user *start, void __user *end)</div><div class='add'>+static inline void</div><div class='add'>+binder_set_installed_page(struct binder_lru_page *lru_page,</div><div class='add'>+			  struct page *page)</div><div class='add'>+{</div><div class='add'>+	/* Pairs with acquire in binder_get_installed_page() */</div><div class='add'>+	smp_store_release(&amp;lru_page-&gt;page_ptr, page);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct page *</div><div class='add'>+binder_get_installed_page(struct binder_lru_page *lru_page)</div><div class='add'>+{</div><div class='add'>+	/* Pairs with release in binder_set_installed_page() */</div><div class='add'>+	return smp_load_acquire(&amp;lru_page-&gt;page_ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void binder_lru_freelist_add(struct binder_alloc *alloc,</div><div class='add'>+				    unsigned long start, unsigned long end)</div><div class='ctx'> {</div><div class='del'>-	void __user *page_addr;</div><div class='del'>-	unsigned long user_page_addr;</div><div class='ctx'> 	struct binder_lru_page *page;</div><div class='del'>-	struct vm_area_struct *vma = NULL;</div><div class='del'>-	struct mm_struct *mm = NULL;</div><div class='del'>-	bool need_mm = false;</div><div class='add'>+	unsigned long page_addr;</div><div class='ctx'> </div><div class='del'>-	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-		     "%d: %s pages %pK-%pK\n", alloc-&gt;pid,</div><div class='del'>-		     allocate ? "allocate" : "free", start, end);</div><div class='add'>+	trace_binder_update_page_range(alloc, false, start, end);</div><div class='ctx'> </div><div class='del'>-	if (end &lt;= start)</div><div class='del'>-		return 0;</div><div class='add'>+	for (page_addr = start; page_addr &lt; end; page_addr += PAGE_SIZE) {</div><div class='add'>+		size_t index;</div><div class='add'>+		int ret;</div><div class='ctx'> </div><div class='del'>-	trace_binder_update_page_range(alloc, allocate, start, end);</div><div class='add'>+		index = (page_addr - alloc-&gt;buffer) / PAGE_SIZE;</div><div class='add'>+		page = &amp;alloc-&gt;pages[index];</div><div class='ctx'> </div><div class='del'>-	if (allocate == 0)</div><div class='del'>-		goto free_range;</div><div class='add'>+		if (!binder_get_installed_page(page))</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-	for (page_addr = start; page_addr &lt; end; page_addr += PAGE_SIZE) {</div><div class='del'>-		page = &amp;alloc-&gt;pages[(page_addr - alloc-&gt;buffer) / PAGE_SIZE];</div><div class='del'>-		if (!page-&gt;page_ptr) {</div><div class='del'>-			need_mm = true;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='add'>+		trace_binder_free_lru_start(alloc, index);</div><div class='add'>+</div><div class='add'>+		ret = list_lru_add_obj(&amp;binder_freelist, &amp;page-&gt;lru);</div><div class='add'>+		WARN_ON(!ret);</div><div class='add'>+</div><div class='add'>+		trace_binder_free_lru_end(alloc, index);</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int binder_install_single_page(struct binder_alloc *alloc,</div><div class='add'>+				      struct binder_lru_page *lru_page,</div><div class='add'>+				      unsigned long addr)</div><div class='add'>+{</div><div class='add'>+	struct page *page;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (need_mm &amp;&amp; mmget_not_zero(alloc-&gt;mm))</div><div class='del'>-		mm = alloc-&gt;mm;</div><div class='add'>+	if (!mmget_not_zero(alloc-&gt;mm))</div><div class='add'>+		return -ESRCH;</div><div class='ctx'> </div><div class='del'>-	if (mm) {</div><div class='del'>-		mmap_write_lock(mm);</div><div class='del'>-		vma = alloc-&gt;vma;</div><div class='add'>+	/*</div><div class='add'>+	 * Protected with mmap_sem in write mode as multiple tasks</div><div class='add'>+	 * might race to install the same page.</div><div class='add'>+	 */</div><div class='add'>+	mmap_write_lock(alloc-&gt;mm);</div><div class='add'>+	if (binder_get_installed_page(lru_page))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (!alloc-&gt;vma) {</div><div class='add'>+		pr_err("%d: %s failed, no vma\n", alloc-&gt;pid, __func__);</div><div class='add'>+		ret = -ESRCH;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!vma &amp;&amp; need_mm) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='del'>-				   "%d: binder_alloc_buf failed to map pages in userspace, no vma\n",</div><div class='del'>-				   alloc-&gt;pid);</div><div class='del'>-		goto err_no_vma;</div><div class='add'>+	page = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO);</div><div class='add'>+	if (!page) {</div><div class='add'>+		pr_err("%d: failed to allocate page\n", alloc-&gt;pid);</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (page_addr = start; page_addr &lt; end; page_addr += PAGE_SIZE) {</div><div class='add'>+	ret = vm_insert_page(alloc-&gt;vma, addr, page);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_err("%d: %s failed to insert page at offset %lx with %d\n",</div><div class='add'>+		       alloc-&gt;pid, __func__, addr - alloc-&gt;buffer, ret);</div><div class='add'>+		__free_page(page);</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Mark page installation complete and safe to use */</div><div class='add'>+	binder_set_installed_page(lru_page, page);</div><div class='add'>+out:</div><div class='add'>+	mmap_write_unlock(alloc-&gt;mm);</div><div class='add'>+	mmput_async(alloc-&gt;mm);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int binder_install_buffer_pages(struct binder_alloc *alloc,</div><div class='add'>+				       struct binder_buffer *buffer,</div><div class='add'>+				       size_t size)</div><div class='add'>+{</div><div class='add'>+	struct binder_lru_page *page;</div><div class='add'>+	unsigned long start, final;</div><div class='add'>+	unsigned long page_addr;</div><div class='add'>+</div><div class='add'>+	start = buffer-&gt;user_data &amp; PAGE_MASK;</div><div class='add'>+	final = PAGE_ALIGN(buffer-&gt;user_data + size);</div><div class='add'>+</div><div class='add'>+	for (page_addr = start; page_addr &lt; final; page_addr += PAGE_SIZE) {</div><div class='add'>+		unsigned long index;</div><div class='ctx'> 		int ret;</div><div class='del'>-		bool on_lru;</div><div class='del'>-		size_t index;</div><div class='ctx'> </div><div class='ctx'> 		index = (page_addr - alloc-&gt;buffer) / PAGE_SIZE;</div><div class='ctx'> 		page = &amp;alloc-&gt;pages[index];</div><div class='ctx'> </div><div class='del'>-		if (page-&gt;page_ptr) {</div><div class='del'>-			trace_binder_alloc_lru_start(alloc, index);</div><div class='del'>-</div><div class='del'>-			on_lru = list_lru_del(&amp;binder_alloc_lru, &amp;page-&gt;lru);</div><div class='del'>-			WARN_ON(!on_lru);</div><div class='del'>-</div><div class='del'>-			trace_binder_alloc_lru_end(alloc, index);</div><div class='add'>+		if (binder_get_installed_page(page))</div><div class='ctx'> 			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (WARN_ON(!vma))</div><div class='del'>-			goto err_page_ptr_cleared;</div><div class='ctx'> </div><div class='ctx'> 		trace_binder_alloc_page_start(alloc, index);</div><div class='del'>-		page-&gt;page_ptr = alloc_page(GFP_KERNEL |</div><div class='del'>-					    __GFP_HIGHMEM |</div><div class='del'>-					    __GFP_ZERO);</div><div class='del'>-		if (!page-&gt;page_ptr) {</div><div class='del'>-			pr_err("%d: binder_alloc_buf failed for page at %pK\n",</div><div class='del'>-				alloc-&gt;pid, page_addr);</div><div class='del'>-			goto err_alloc_page_failed;</div><div class='del'>-		}</div><div class='del'>-		page-&gt;alloc = alloc;</div><div class='del'>-		INIT_LIST_HEAD(&amp;page-&gt;lru);</div><div class='del'>-</div><div class='del'>-		user_page_addr = (uintptr_t)page_addr;</div><div class='del'>-		ret = vm_insert_page(vma, user_page_addr, page[0].page_ptr);</div><div class='del'>-		if (ret) {</div><div class='del'>-			pr_err("%d: binder_alloc_buf failed to map page at %lx in userspace\n",</div><div class='del'>-			       alloc-&gt;pid, user_page_addr);</div><div class='del'>-			goto err_vm_insert_page_failed;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='del'>-		if (index + 1 &gt; alloc-&gt;pages_high)</div><div class='del'>-			alloc-&gt;pages_high = index + 1;</div><div class='add'>+		ret = binder_install_single_page(alloc, page, page_addr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='ctx'> 		trace_binder_alloc_page_end(alloc, index);</div><div class='ctx'> 	}</div><div class='del'>-	if (mm) {</div><div class='del'>-		mmap_write_unlock(mm);</div><div class='del'>-		mmput(mm);</div><div class='del'>-	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-free_range:</div><div class='del'>-	for (page_addr = end - PAGE_SIZE; 1; page_addr -= PAGE_SIZE) {</div><div class='del'>-		bool ret;</div><div class='del'>-		size_t index;</div><div class='add'>+/* The range of pages should exclude those shared with other buffers */</div><div class='add'>+static void binder_lru_freelist_del(struct binder_alloc *alloc,</div><div class='add'>+				    unsigned long start, unsigned long end)</div><div class='add'>+{</div><div class='add'>+	struct binder_lru_page *page;</div><div class='add'>+	unsigned long page_addr;</div><div class='add'>+</div><div class='add'>+	trace_binder_update_page_range(alloc, true, start, end);</div><div class='add'>+</div><div class='add'>+	for (page_addr = start; page_addr &lt; end; page_addr += PAGE_SIZE) {</div><div class='add'>+		unsigned long index;</div><div class='add'>+		bool on_lru;</div><div class='ctx'> </div><div class='ctx'> 		index = (page_addr - alloc-&gt;buffer) / PAGE_SIZE;</div><div class='ctx'> 		page = &amp;alloc-&gt;pages[index];</div><div class='ctx'> </div><div class='del'>-		trace_binder_free_lru_start(alloc, index);</div><div class='add'>+		if (page-&gt;page_ptr) {</div><div class='add'>+			trace_binder_alloc_lru_start(alloc, index);</div><div class='ctx'> </div><div class='del'>-		ret = list_lru_add(&amp;binder_alloc_lru, &amp;page-&gt;lru);</div><div class='del'>-		WARN_ON(!ret);</div><div class='add'>+			on_lru = list_lru_del_obj(&amp;binder_freelist, &amp;page-&gt;lru);</div><div class='add'>+			WARN_ON(!on_lru);</div><div class='ctx'> </div><div class='del'>-		trace_binder_free_lru_end(alloc, index);</div><div class='del'>-		if (page_addr == start)</div><div class='del'>-			break;</div><div class='del'>-		continue;</div><div class='del'>-</div><div class='del'>-err_vm_insert_page_failed:</div><div class='del'>-		__free_page(page-&gt;page_ptr);</div><div class='del'>-		page-&gt;page_ptr = NULL;</div><div class='del'>-err_alloc_page_failed:</div><div class='del'>-err_page_ptr_cleared:</div><div class='del'>-		if (page_addr == start)</div><div class='del'>-			break;</div><div class='del'>-	}</div><div class='del'>-err_no_vma:</div><div class='del'>-	if (mm) {</div><div class='del'>-		mmap_write_unlock(mm);</div><div class='del'>-		mmput(mm);</div><div class='add'>+			trace_binder_alloc_lru_end(alloc, index);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (index + 1 &gt; alloc-&gt;pages_high)</div><div class='add'>+			alloc-&gt;pages_high = index + 1;</div><div class='ctx'> 	}</div><div class='del'>-	return vma ? -ENOMEM : -ESRCH;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void binder_alloc_set_vma(struct binder_alloc *alloc,</div><div class='hunk'>@@ -323,7 +343,44 @@ static inline struct vm_area_struct *binder_alloc_get_vma(</div><div class='ctx'> 	return smp_load_acquire(&amp;alloc-&gt;vma);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)</div><div class='add'>+static void debug_no_space_locked(struct binder_alloc *alloc)</div><div class='add'>+{</div><div class='add'>+	size_t largest_alloc_size = 0;</div><div class='add'>+	struct binder_buffer *buffer;</div><div class='add'>+	size_t allocated_buffers = 0;</div><div class='add'>+	size_t largest_free_size = 0;</div><div class='add'>+	size_t total_alloc_size = 0;</div><div class='add'>+	size_t total_free_size = 0;</div><div class='add'>+	size_t free_buffers = 0;</div><div class='add'>+	size_t buffer_size;</div><div class='add'>+	struct rb_node *n;</div><div class='add'>+</div><div class='add'>+	for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n; n = rb_next(n)) {</div><div class='add'>+		buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='add'>+		buffer_size = binder_alloc_buffer_size(alloc, buffer);</div><div class='add'>+		allocated_buffers++;</div><div class='add'>+		total_alloc_size += buffer_size;</div><div class='add'>+		if (buffer_size &gt; largest_alloc_size)</div><div class='add'>+			largest_alloc_size = buffer_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (n = rb_first(&amp;alloc-&gt;free_buffers); n; n = rb_next(n)) {</div><div class='add'>+		buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='add'>+		buffer_size = binder_alloc_buffer_size(alloc, buffer);</div><div class='add'>+		free_buffers++;</div><div class='add'>+		total_free_size += buffer_size;</div><div class='add'>+		if (buffer_size &gt; largest_free_size)</div><div class='add'>+			largest_free_size = buffer_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='add'>+			   "allocated: %zd (num: %zd largest: %zd), free: %zd (num: %zd largest: %zd)\n",</div><div class='add'>+			   total_alloc_size, allocated_buffers,</div><div class='add'>+			   largest_alloc_size, total_free_size,</div><div class='add'>+			   free_buffers, largest_free_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool debug_low_async_space_locked(struct binder_alloc *alloc)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Find the amount and size of buffers allocated by the current caller;</div><div class='hunk'>@@ -332,10 +389,20 @@ static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)</div><div class='ctx'> 	 * and at some point we'll catch them in the act. This is more efficient</div><div class='ctx'> 	 * than keeping a map per pid.</div><div class='ctx'> 	 */</div><div class='del'>-	struct rb_node *n;</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='ctx'> 	size_t total_alloc_size = 0;</div><div class='add'>+	int pid = current-&gt;tgid;</div><div class='ctx'> 	size_t num_buffers = 0;</div><div class='add'>+	struct rb_node *n;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Only start detecting spammers once we have less than 20% of async</div><div class='add'>+	 * space left (which is less than 10% of total buffer size).</div><div class='add'>+	 */</div><div class='add'>+	if (alloc-&gt;free_async_space &gt;= alloc-&gt;buffer_size / 10) {</div><div class='add'>+		alloc-&gt;oneway_spam_detected = false;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n != NULL;</div><div class='ctx'> 		 n = rb_next(n)) {</div><div class='hunk'>@@ -344,8 +411,7 @@ static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (!buffer-&gt;async_transaction)</div><div class='ctx'> 			continue;</div><div class='del'>-		total_alloc_size += binder_alloc_buffer_size(alloc, buffer)</div><div class='del'>-			+ sizeof(struct binder_buffer);</div><div class='add'>+		total_alloc_size += binder_alloc_buffer_size(alloc, buffer);</div><div class='ctx'> 		num_buffers++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -366,58 +432,28 @@ static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Callers preallocate @new_buffer, it is freed by this function if unused */</div><div class='ctx'> static struct binder_buffer *binder_alloc_new_buf_locked(</div><div class='ctx'> 				struct binder_alloc *alloc,</div><div class='del'>-				size_t data_size,</div><div class='del'>-				size_t offsets_size,</div><div class='del'>-				size_t extra_buffers_size,</div><div class='del'>-				int is_async,</div><div class='del'>-				int pid)</div><div class='add'>+				struct binder_buffer *new_buffer,</div><div class='add'>+				size_t size,</div><div class='add'>+				int is_async)</div><div class='ctx'> {</div><div class='ctx'> 	struct rb_node *n = alloc-&gt;free_buffers.rb_node;</div><div class='add'>+	struct rb_node *best_fit = NULL;</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='add'>+	unsigned long next_used_page;</div><div class='add'>+	unsigned long curr_last_page;</div><div class='ctx'> 	size_t buffer_size;</div><div class='del'>-	struct rb_node *best_fit = NULL;</div><div class='del'>-	void __user *has_page_addr;</div><div class='del'>-	void __user *end_page_addr;</div><div class='del'>-	size_t size, data_offsets_size;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	/* Check binder_alloc is fully initialized */</div><div class='del'>-	if (!binder_alloc_get_vma(alloc)) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='del'>-				   "%d: binder_alloc_buf, no vma\n",</div><div class='del'>-				   alloc-&gt;pid);</div><div class='del'>-		return ERR_PTR(-ESRCH);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	data_offsets_size = ALIGN(data_size, sizeof(void *)) +</div><div class='del'>-		ALIGN(offsets_size, sizeof(void *));</div><div class='ctx'> </div><div class='del'>-	if (data_offsets_size &lt; data_size || data_offsets_size &lt; offsets_size) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				"%d: got transaction with invalid size %zd-%zd\n",</div><div class='del'>-				alloc-&gt;pid, data_size, offsets_size);</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-	}</div><div class='del'>-	size = data_offsets_size + ALIGN(extra_buffers_size, sizeof(void *));</div><div class='del'>-	if (size &lt; data_offsets_size || size &lt; extra_buffers_size) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				"%d: got transaction with invalid extra_buffers_size %zd\n",</div><div class='del'>-				alloc-&gt;pid, extra_buffers_size);</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-	}</div><div class='del'>-	if (is_async &amp;&amp;</div><div class='del'>-	    alloc-&gt;free_async_space &lt; size + sizeof(struct binder_buffer)) {</div><div class='add'>+	if (is_async &amp;&amp; alloc-&gt;free_async_space &lt; size) {</div><div class='ctx'> 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='ctx'> 			     "%d: binder_alloc_buf size %zd failed, no async space left\n",</div><div class='ctx'> 			      alloc-&gt;pid, size);</div><div class='del'>-		return ERR_PTR(-ENOSPC);</div><div class='add'>+		buffer = ERR_PTR(-ENOSPC);</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Pad 0-size buffers so they get assigned unique addresses */</div><div class='del'>-	size = max(size, sizeof(void *));</div><div class='del'>-</div><div class='ctx'> 	while (n) {</div><div class='ctx'> 		buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='ctx'> 		BUG_ON(!buffer-&gt;free);</div><div class='hunk'>@@ -426,121 +462,92 @@ static struct binder_buffer *binder_alloc_new_buf_locked(</div><div class='ctx'> 		if (size &lt; buffer_size) {</div><div class='ctx'> 			best_fit = n;</div><div class='ctx'> 			n = n-&gt;rb_left;</div><div class='del'>-		} else if (size &gt; buffer_size)</div><div class='add'>+		} else if (size &gt; buffer_size) {</div><div class='ctx'> 			n = n-&gt;rb_right;</div><div class='del'>-		else {</div><div class='add'>+		} else {</div><div class='ctx'> 			best_fit = n;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (best_fit == NULL) {</div><div class='del'>-		size_t allocated_buffers = 0;</div><div class='del'>-		size_t largest_alloc_size = 0;</div><div class='del'>-		size_t total_alloc_size = 0;</div><div class='del'>-		size_t free_buffers = 0;</div><div class='del'>-		size_t largest_free_size = 0;</div><div class='del'>-		size_t total_free_size = 0;</div><div class='del'>-</div><div class='del'>-		for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n != NULL;</div><div class='del'>-		     n = rb_next(n)) {</div><div class='del'>-			buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='del'>-			buffer_size = binder_alloc_buffer_size(alloc, buffer);</div><div class='del'>-			allocated_buffers++;</div><div class='del'>-			total_alloc_size += buffer_size;</div><div class='del'>-			if (buffer_size &gt; largest_alloc_size)</div><div class='del'>-				largest_alloc_size = buffer_size;</div><div class='del'>-		}</div><div class='del'>-		for (n = rb_first(&amp;alloc-&gt;free_buffers); n != NULL;</div><div class='del'>-		     n = rb_next(n)) {</div><div class='del'>-			buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='del'>-			buffer_size = binder_alloc_buffer_size(alloc, buffer);</div><div class='del'>-			free_buffers++;</div><div class='del'>-			total_free_size += buffer_size;</div><div class='del'>-			if (buffer_size &gt; largest_free_size)</div><div class='del'>-				largest_free_size = buffer_size;</div><div class='del'>-		}</div><div class='add'>+</div><div class='add'>+	if (unlikely(!best_fit)) {</div><div class='ctx'> 		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='ctx'> 				   "%d: binder_alloc_buf size %zd failed, no address space\n",</div><div class='ctx'> 				   alloc-&gt;pid, size);</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='del'>-				   "allocated: %zd (num: %zd largest: %zd), free: %zd (num: %zd largest: %zd)\n",</div><div class='del'>-				   total_alloc_size, allocated_buffers,</div><div class='del'>-				   largest_alloc_size, total_free_size,</div><div class='del'>-				   free_buffers, largest_free_size);</div><div class='del'>-		return ERR_PTR(-ENOSPC);</div><div class='add'>+		debug_no_space_locked(alloc);</div><div class='add'>+		buffer = ERR_PTR(-ENOSPC);</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='del'>-	if (n == NULL) {</div><div class='add'>+</div><div class='add'>+	if (buffer_size != size) {</div><div class='add'>+		/* Found an oversized buffer and needs to be split */</div><div class='ctx'> 		buffer = rb_entry(best_fit, struct binder_buffer, rb_node);</div><div class='ctx'> 		buffer_size = binder_alloc_buffer_size(alloc, buffer);</div><div class='add'>+</div><div class='add'>+		WARN_ON(n || buffer_size == size);</div><div class='add'>+		new_buffer-&gt;user_data = buffer-&gt;user_data + size;</div><div class='add'>+		list_add(&amp;new_buffer-&gt;entry, &amp;buffer-&gt;entry);</div><div class='add'>+		new_buffer-&gt;free = 1;</div><div class='add'>+		binder_insert_free_buffer(alloc, new_buffer);</div><div class='add'>+		new_buffer = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='ctx'> 		     "%d: binder_alloc_buf size %zd got buffer %pK size %zd\n",</div><div class='ctx'> 		      alloc-&gt;pid, size, buffer, buffer_size);</div><div class='ctx'> </div><div class='del'>-	has_page_addr = (void __user *)</div><div class='del'>-		(((uintptr_t)buffer-&gt;user_data + buffer_size) &amp; PAGE_MASK);</div><div class='del'>-	WARN_ON(n &amp;&amp; buffer_size != size);</div><div class='del'>-	end_page_addr =</div><div class='del'>-		(void __user *)PAGE_ALIGN((uintptr_t)buffer-&gt;user_data + size);</div><div class='del'>-	if (end_page_addr &gt; has_page_addr)</div><div class='del'>-		end_page_addr = has_page_addr;</div><div class='del'>-	ret = binder_update_page_range(alloc, 1, (void __user *)</div><div class='del'>-		PAGE_ALIGN((uintptr_t)buffer-&gt;user_data), end_page_addr);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ERR_PTR(ret);</div><div class='del'>-</div><div class='del'>-	if (buffer_size != size) {</div><div class='del'>-		struct binder_buffer *new_buffer;</div><div class='del'>-</div><div class='del'>-		new_buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);</div><div class='del'>-		if (!new_buffer) {</div><div class='del'>-			pr_err("%s: %d failed to alloc new buffer struct\n",</div><div class='del'>-			       __func__, alloc-&gt;pid);</div><div class='del'>-			goto err_alloc_buf_struct_failed;</div><div class='del'>-		}</div><div class='del'>-		new_buffer-&gt;user_data = (u8 __user *)buffer-&gt;user_data + size;</div><div class='del'>-		list_add(&amp;new_buffer-&gt;entry, &amp;buffer-&gt;entry);</div><div class='del'>-		new_buffer-&gt;free = 1;</div><div class='del'>-		binder_insert_free_buffer(alloc, new_buffer);</div><div class='del'>-	}</div><div class='add'>+	/*</div><div class='add'>+	 * Now we remove the pages from the freelist. A clever calculation</div><div class='add'>+	 * with buffer_size determines if the last page is shared with an</div><div class='add'>+	 * adjacent in-use buffer. In such case, the page has been already</div><div class='add'>+	 * removed from the freelist so we trim our range short.</div><div class='add'>+	 */</div><div class='add'>+	next_used_page = (buffer-&gt;user_data + buffer_size) &amp; PAGE_MASK;</div><div class='add'>+	curr_last_page = PAGE_ALIGN(buffer-&gt;user_data + size);</div><div class='add'>+	binder_lru_freelist_del(alloc, PAGE_ALIGN(buffer-&gt;user_data),</div><div class='add'>+				min(next_used_page, curr_last_page));</div><div class='ctx'> </div><div class='del'>-	rb_erase(best_fit, &amp;alloc-&gt;free_buffers);</div><div class='add'>+	rb_erase(&amp;buffer-&gt;rb_node, &amp;alloc-&gt;free_buffers);</div><div class='ctx'> 	buffer-&gt;free = 0;</div><div class='ctx'> 	buffer-&gt;allow_user_free = 0;</div><div class='ctx'> 	binder_insert_allocated_buffer_locked(alloc, buffer);</div><div class='del'>-	binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-		     "%d: binder_alloc_buf size %zd got %pK\n",</div><div class='del'>-		      alloc-&gt;pid, size, buffer);</div><div class='del'>-	buffer-&gt;data_size = data_size;</div><div class='del'>-	buffer-&gt;offsets_size = offsets_size;</div><div class='ctx'> 	buffer-&gt;async_transaction = is_async;</div><div class='del'>-	buffer-&gt;extra_buffers_size = extra_buffers_size;</div><div class='del'>-	buffer-&gt;pid = pid;</div><div class='ctx'> 	buffer-&gt;oneway_spam_suspect = false;</div><div class='ctx'> 	if (is_async) {</div><div class='del'>-		alloc-&gt;free_async_space -= size + sizeof(struct binder_buffer);</div><div class='add'>+		alloc-&gt;free_async_space -= size;</div><div class='ctx'> 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC,</div><div class='ctx'> 			     "%d: binder_alloc_buf size %zd async free %zd\n",</div><div class='ctx'> 			      alloc-&gt;pid, size, alloc-&gt;free_async_space);</div><div class='del'>-		if (alloc-&gt;free_async_space &lt; alloc-&gt;buffer_size / 10) {</div><div class='del'>-			/*</div><div class='del'>-			 * Start detecting spammers once we have less than 20%</div><div class='del'>-			 * of async space left (which is less than 10% of total</div><div class='del'>-			 * buffer size).</div><div class='del'>-			 */</div><div class='del'>-			buffer-&gt;oneway_spam_suspect = debug_low_async_space_locked(alloc, pid);</div><div class='del'>-		} else {</div><div class='del'>-			alloc-&gt;oneway_spam_detected = false;</div><div class='del'>-		}</div><div class='add'>+		if (debug_low_async_space_locked(alloc))</div><div class='add'>+			buffer-&gt;oneway_spam_suspect = true;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	/* Discard possibly unused new_buffer */</div><div class='add'>+	kfree(new_buffer);</div><div class='ctx'> 	return buffer;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-err_alloc_buf_struct_failed:</div><div class='del'>-	binder_update_page_range(alloc, 0, (void __user *)</div><div class='del'>-				 PAGE_ALIGN((uintptr_t)buffer-&gt;user_data),</div><div class='del'>-				 end_page_addr);</div><div class='del'>-	return ERR_PTR(-ENOMEM);</div><div class='add'>+/* Calculate the sanitized total size, returns 0 for invalid request */</div><div class='add'>+static inline size_t sanitized_size(size_t data_size,</div><div class='add'>+				    size_t offsets_size,</div><div class='add'>+				    size_t extra_buffers_size)</div><div class='add'>+{</div><div class='add'>+	size_t total, tmp;</div><div class='add'>+</div><div class='add'>+	/* Align to pointer size and check for overflows */</div><div class='add'>+	tmp = ALIGN(data_size, sizeof(void *)) +</div><div class='add'>+		ALIGN(offsets_size, sizeof(void *));</div><div class='add'>+	if (tmp &lt; data_size || tmp &lt; offsets_size)</div><div class='add'>+		return 0;</div><div class='add'>+	total = tmp + ALIGN(extra_buffers_size, sizeof(void *));</div><div class='add'>+	if (total &lt; tmp || total &lt; extra_buffers_size)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Pad 0-sized buffers so they get a unique address */</div><div class='add'>+	total = max(total, sizeof(void *));</div><div class='add'>+</div><div class='add'>+	return total;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -550,87 +557,101 @@ err_alloc_buf_struct_failed:</div><div class='ctx'>  * @offsets_size:       user specified buffer offset</div><div class='ctx'>  * @extra_buffers_size: size of extra space for meta-data (eg, security context)</div><div class='ctx'>  * @is_async:           buffer for async transaction</div><div class='del'>- * @pid:				pid to attribute allocation to (used for debugging)</div><div class='ctx'>  *</div><div class='ctx'>  * Allocate a new buffer given the requested sizes. Returns</div><div class='ctx'>  * the kernel version of the buffer pointer. The size allocated</div><div class='ctx'>  * is the sum of the three given sizes (each rounded up to</div><div class='ctx'>  * pointer-sized boundary)</div><div class='ctx'>  *</div><div class='del'>- * Return:	The allocated buffer or %NULL if error</div><div class='add'>+ * Return:	The allocated buffer or %ERR_PTR(-errno) if error</div><div class='ctx'>  */</div><div class='ctx'> struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,</div><div class='ctx'> 					   size_t data_size,</div><div class='ctx'> 					   size_t offsets_size,</div><div class='ctx'> 					   size_t extra_buffers_size,</div><div class='del'>-					   int is_async,</div><div class='del'>-					   int pid)</div><div class='add'>+					   int is_async)</div><div class='ctx'> {</div><div class='del'>-	struct binder_buffer *buffer;</div><div class='add'>+	struct binder_buffer *buffer, *next;</div><div class='add'>+	size_t size;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Check binder_alloc is fully initialized */</div><div class='add'>+	if (!binder_alloc_get_vma(alloc)) {</div><div class='add'>+		binder_alloc_debug(BINDER_DEBUG_USER_ERROR,</div><div class='add'>+				   "%d: binder_alloc_buf, no vma\n",</div><div class='add'>+				   alloc-&gt;pid);</div><div class='add'>+		return ERR_PTR(-ESRCH);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = sanitized_size(data_size, offsets_size, extra_buffers_size);</div><div class='add'>+	if (unlikely(!size)) {</div><div class='add'>+		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='add'>+				   "%d: got transaction with invalid size %zd-%zd-%zd\n",</div><div class='add'>+				   alloc-&gt;pid, data_size, offsets_size,</div><div class='add'>+				   extra_buffers_size);</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Preallocate the next buffer */</div><div class='add'>+	next = kzalloc(sizeof(*next), GFP_KERNEL);</div><div class='add'>+	if (!next)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='del'>-	buffer = binder_alloc_new_buf_locked(alloc, data_size, offsets_size,</div><div class='del'>-					     extra_buffers_size, is_async, pid);</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='add'>+	buffer = binder_alloc_new_buf_locked(alloc, next, size, is_async);</div><div class='add'>+	if (IS_ERR(buffer)) {</div><div class='add'>+		spin_unlock(&amp;alloc-&gt;lock);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	buffer-&gt;data_size = data_size;</div><div class='add'>+	buffer-&gt;offsets_size = offsets_size;</div><div class='add'>+	buffer-&gt;extra_buffers_size = extra_buffers_size;</div><div class='add'>+	buffer-&gt;pid = current-&gt;tgid;</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ret = binder_install_buffer_pages(alloc, buffer, size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		binder_alloc_free_buf(alloc, buffer);</div><div class='add'>+		buffer = ERR_PTR(ret);</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='ctx'> 	return buffer;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __user *buffer_start_page(struct binder_buffer *buffer)</div><div class='add'>+static unsigned long buffer_start_page(struct binder_buffer *buffer)</div><div class='ctx'> {</div><div class='del'>-	return (void __user *)((uintptr_t)buffer-&gt;user_data &amp; PAGE_MASK);</div><div class='add'>+	return buffer-&gt;user_data &amp; PAGE_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __user *prev_buffer_end_page(struct binder_buffer *buffer)</div><div class='add'>+static unsigned long prev_buffer_end_page(struct binder_buffer *buffer)</div><div class='ctx'> {</div><div class='del'>-	return (void __user *)</div><div class='del'>-		(((uintptr_t)(buffer-&gt;user_data) - 1) &amp; PAGE_MASK);</div><div class='add'>+	return (buffer-&gt;user_data - 1) &amp; PAGE_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void binder_delete_free_buffer(struct binder_alloc *alloc,</div><div class='ctx'> 				      struct binder_buffer *buffer)</div><div class='ctx'> {</div><div class='del'>-	struct binder_buffer *prev, *next = NULL;</div><div class='del'>-	bool to_free = true;</div><div class='add'>+	struct binder_buffer *prev, *next;</div><div class='add'>+</div><div class='add'>+	if (PAGE_ALIGNED(buffer-&gt;user_data))</div><div class='add'>+		goto skip_freelist;</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(alloc-&gt;buffers.next == &amp;buffer-&gt;entry);</div><div class='ctx'> 	prev = binder_buffer_prev(buffer);</div><div class='ctx'> 	BUG_ON(!prev-&gt;free);</div><div class='del'>-	if (prev_buffer_end_page(prev) == buffer_start_page(buffer)) {</div><div class='del'>-		to_free = false;</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				   "%d: merge free, buffer %pK share page with %pK\n",</div><div class='del'>-				   alloc-&gt;pid, buffer-&gt;user_data,</div><div class='del'>-				   prev-&gt;user_data);</div><div class='del'>-	}</div><div class='add'>+	if (prev_buffer_end_page(prev) == buffer_start_page(buffer))</div><div class='add'>+		goto skip_freelist;</div><div class='ctx'> </div><div class='ctx'> 	if (!list_is_last(&amp;buffer-&gt;entry, &amp;alloc-&gt;buffers)) {</div><div class='ctx'> 		next = binder_buffer_next(buffer);</div><div class='del'>-		if (buffer_start_page(next) == buffer_start_page(buffer)) {</div><div class='del'>-			to_free = false;</div><div class='del'>-			binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-					   "%d: merge free, buffer %pK share page with %pK\n",</div><div class='del'>-					   alloc-&gt;pid,</div><div class='del'>-					   buffer-&gt;user_data,</div><div class='del'>-					   next-&gt;user_data);</div><div class='del'>-		}</div><div class='add'>+		if (buffer_start_page(next) == buffer_start_page(buffer))</div><div class='add'>+			goto skip_freelist;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (PAGE_ALIGNED(buffer-&gt;user_data)) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				   "%d: merge free, buffer start %pK is page aligned\n",</div><div class='del'>-				   alloc-&gt;pid, buffer-&gt;user_data);</div><div class='del'>-		to_free = false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (to_free) {</div><div class='del'>-		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				   "%d: merge free, buffer %pK do not share page with %pK or %pK\n",</div><div class='del'>-				   alloc-&gt;pid, buffer-&gt;user_data,</div><div class='del'>-				   prev-&gt;user_data,</div><div class='del'>-				   next ? next-&gt;user_data : NULL);</div><div class='del'>-		binder_update_page_range(alloc, 0, buffer_start_page(buffer),</div><div class='del'>-					 buffer_start_page(buffer) + PAGE_SIZE);</div><div class='del'>-	}</div><div class='add'>+	binder_lru_freelist_add(alloc, buffer_start_page(buffer),</div><div class='add'>+				buffer_start_page(buffer) + PAGE_SIZE);</div><div class='add'>+skip_freelist:</div><div class='ctx'> 	list_del(&amp;buffer-&gt;entry);</div><div class='ctx'> 	kfree(buffer);</div><div class='ctx'> }</div><div class='hunk'>@@ -657,17 +678,14 @@ static void binder_free_buf_locked(struct binder_alloc *alloc,</div><div class='ctx'> 	BUG_ON(buffer-&gt;user_data &gt; alloc-&gt;buffer + alloc-&gt;buffer_size);</div><div class='ctx'> </div><div class='ctx'> 	if (buffer-&gt;async_transaction) {</div><div class='del'>-		alloc-&gt;free_async_space += buffer_size + sizeof(struct binder_buffer);</div><div class='del'>-</div><div class='add'>+		alloc-&gt;free_async_space += buffer_size;</div><div class='ctx'> 		binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC,</div><div class='ctx'> 			     "%d: binder_free_buf size %zd async free %zd\n",</div><div class='ctx'> 			      alloc-&gt;pid, size, alloc-&gt;free_async_space);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	binder_update_page_range(alloc, 0,</div><div class='del'>-		(void __user *)PAGE_ALIGN((uintptr_t)buffer-&gt;user_data),</div><div class='del'>-		(void __user *)(((uintptr_t)</div><div class='del'>-			  buffer-&gt;user_data + buffer_size) &amp; PAGE_MASK));</div><div class='add'>+	binder_lru_freelist_add(alloc, PAGE_ALIGN(buffer-&gt;user_data),</div><div class='add'>+				(buffer-&gt;user_data + buffer_size) &amp; PAGE_MASK);</div><div class='ctx'> </div><div class='ctx'> 	rb_erase(&amp;buffer-&gt;rb_node, &amp;alloc-&gt;allocated_buffers);</div><div class='ctx'> 	buffer-&gt;free = 1;</div><div class='hunk'>@@ -691,8 +709,68 @@ static void binder_free_buf_locked(struct binder_alloc *alloc,</div><div class='ctx'> 	binder_insert_free_buffer(alloc, buffer);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * binder_alloc_get_page() - get kernel pointer for given buffer offset</div><div class='add'>+ * @alloc: binder_alloc for this proc</div><div class='add'>+ * @buffer: binder buffer to be accessed</div><div class='add'>+ * @buffer_offset: offset into @buffer data</div><div class='add'>+ * @pgoffp: address to copy final page offset to</div><div class='add'>+ *</div><div class='add'>+ * Lookup the struct page corresponding to the address</div><div class='add'>+ * at @buffer_offset into @buffer-&gt;user_data. If @pgoffp is not</div><div class='add'>+ * NULL, the byte-offset into the page is written there.</div><div class='add'>+ *</div><div class='add'>+ * The caller is responsible to ensure that the offset points</div><div class='add'>+ * to a valid address within the @buffer and that @buffer is</div><div class='add'>+ * not freeable by the user. Since it can't be freed, we are</div><div class='add'>+ * guaranteed that the corresponding elements of @alloc-&gt;pages[]</div><div class='add'>+ * cannot change.</div><div class='add'>+ *</div><div class='add'>+ * Return: struct page</div><div class='add'>+ */</div><div class='add'>+static struct page *binder_alloc_get_page(struct binder_alloc *alloc,</div><div class='add'>+					  struct binder_buffer *buffer,</div><div class='add'>+					  binder_size_t buffer_offset,</div><div class='add'>+					  pgoff_t *pgoffp)</div><div class='add'>+{</div><div class='add'>+	binder_size_t buffer_space_offset = buffer_offset +</div><div class='add'>+		(buffer-&gt;user_data - alloc-&gt;buffer);</div><div class='add'>+	pgoff_t pgoff = buffer_space_offset &amp; ~PAGE_MASK;</div><div class='add'>+	size_t index = buffer_space_offset &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	struct binder_lru_page *lru_page;</div><div class='add'>+</div><div class='add'>+	lru_page = &amp;alloc-&gt;pages[index];</div><div class='add'>+	*pgoffp = pgoff;</div><div class='add'>+	return lru_page-&gt;page_ptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * binder_alloc_clear_buf() - zero out buffer</div><div class='add'>+ * @alloc: binder_alloc for this proc</div><div class='add'>+ * @buffer: binder buffer to be cleared</div><div class='add'>+ *</div><div class='add'>+ * memset the given buffer to 0</div><div class='add'>+ */</div><div class='ctx'> static void binder_alloc_clear_buf(struct binder_alloc *alloc,</div><div class='del'>-				   struct binder_buffer *buffer);</div><div class='add'>+				   struct binder_buffer *buffer)</div><div class='add'>+{</div><div class='add'>+	size_t bytes = binder_alloc_buffer_size(alloc, buffer);</div><div class='add'>+	binder_size_t buffer_offset = 0;</div><div class='add'>+</div><div class='add'>+	while (bytes) {</div><div class='add'>+		unsigned long size;</div><div class='add'>+		struct page *page;</div><div class='add'>+		pgoff_t pgoff;</div><div class='add'>+</div><div class='add'>+		page = binder_alloc_get_page(alloc, buffer,</div><div class='add'>+					     buffer_offset, &amp;pgoff);</div><div class='add'>+		size = min_t(size_t, bytes, PAGE_SIZE - pgoff);</div><div class='add'>+		memset_page(page, pgoff, 0, size);</div><div class='add'>+		bytes -= size;</div><div class='add'>+		buffer_offset += size;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * binder_alloc_free_buf() - free a binder buffer</div><div class='ctx'>  * @alloc:	binder_alloc for this proc</div><div class='hunk'>@@ -706,18 +784,18 @@ void binder_alloc_free_buf(struct binder_alloc *alloc,</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We could eliminate the call to binder_alloc_clear_buf()</div><div class='ctx'> 	 * from binder_alloc_deferred_release() by moving this to</div><div class='del'>-	 * binder_alloc_free_buf_locked(). However, that could</div><div class='del'>-	 * increase contention for the alloc mutex if clear_on_free</div><div class='del'>-	 * is used frequently for large buffers. The mutex is not</div><div class='add'>+	 * binder_free_buf_locked(). However, that could</div><div class='add'>+	 * increase contention for the alloc-&gt;lock if clear_on_free</div><div class='add'>+	 * is used frequently for large buffers. This lock is not</div><div class='ctx'> 	 * needed for correctness here.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (buffer-&gt;clear_on_free) {</div><div class='ctx'> 		binder_alloc_clear_buf(alloc, buffer);</div><div class='ctx'> 		buffer-&gt;clear_on_free = false;</div><div class='ctx'> 	}</div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	binder_free_buf_locked(alloc, buffer);</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -736,9 +814,9 @@ void binder_alloc_free_buf(struct binder_alloc *alloc,</div><div class='ctx'> int binder_alloc_mmap_handler(struct binder_alloc *alloc,</div><div class='ctx'> 			      struct vm_area_struct *vma)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='del'>-	const char *failure_string;</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='add'>+	const char *failure_string;</div><div class='add'>+	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(vma-&gt;vm_mm != alloc-&gt;mm)) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -756,7 +834,7 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc,</div><div class='ctx'> 				   SZ_4M);</div><div class='ctx'> 	mutex_unlock(&amp;binder_alloc_mmap_lock);</div><div class='ctx'> </div><div class='del'>-	alloc-&gt;buffer = (void __user *)vma-&gt;vm_start;</div><div class='add'>+	alloc-&gt;buffer = vma-&gt;vm_start;</div><div class='ctx'> </div><div class='ctx'> 	alloc-&gt;pages = kcalloc(alloc-&gt;buffer_size / PAGE_SIZE,</div><div class='ctx'> 			       sizeof(alloc-&gt;pages[0]),</div><div class='hunk'>@@ -767,6 +845,11 @@ int binder_alloc_mmap_handler(struct binder_alloc *alloc,</div><div class='ctx'> 		goto err_alloc_pages_failed;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; alloc-&gt;buffer_size / PAGE_SIZE; i++) {</div><div class='add'>+		alloc-&gt;pages[i].alloc = alloc;</div><div class='add'>+		INIT_LIST_HEAD(&amp;alloc-&gt;pages[i].lru);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);</div><div class='ctx'> 	if (!buffer) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='hunk'>@@ -789,7 +872,7 @@ err_alloc_buf_struct_failed:</div><div class='ctx'> 	kfree(alloc-&gt;pages);</div><div class='ctx'> 	alloc-&gt;pages = NULL;</div><div class='ctx'> err_alloc_pages_failed:</div><div class='del'>-	alloc-&gt;buffer = NULL;</div><div class='add'>+	alloc-&gt;buffer = 0;</div><div class='ctx'> 	mutex_lock(&amp;binder_alloc_mmap_lock);</div><div class='ctx'> 	alloc-&gt;buffer_size = 0;</div><div class='ctx'> err_already_mapped:</div><div class='hunk'>@@ -810,7 +893,7 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)</div><div class='ctx'> 	struct binder_buffer *buffer;</div><div class='ctx'> </div><div class='ctx'> 	buffers = 0;</div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	BUG_ON(alloc-&gt;vma);</div><div class='ctx'> </div><div class='ctx'> 	while ((n = rb_first(&amp;alloc-&gt;allocated_buffers))) {</div><div class='hunk'>@@ -842,25 +925,25 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; alloc-&gt;buffer_size / PAGE_SIZE; i++) {</div><div class='del'>-			void __user *page_addr;</div><div class='add'>+			unsigned long page_addr;</div><div class='ctx'> 			bool on_lru;</div><div class='ctx'> </div><div class='ctx'> 			if (!alloc-&gt;pages[i].page_ptr)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			on_lru = list_lru_del(&amp;binder_alloc_lru,</div><div class='del'>-					      &amp;alloc-&gt;pages[i].lru);</div><div class='add'>+			on_lru = list_lru_del_obj(&amp;binder_freelist,</div><div class='add'>+						  &amp;alloc-&gt;pages[i].lru);</div><div class='ctx'> 			page_addr = alloc-&gt;buffer + i * PAGE_SIZE;</div><div class='ctx'> 			binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC,</div><div class='del'>-				     "%s: %d: page %d at %pK %s\n",</div><div class='del'>-				     __func__, alloc-&gt;pid, i, page_addr,</div><div class='add'>+				     "%s: %d: page %d %s\n",</div><div class='add'>+				     __func__, alloc-&gt;pid, i,</div><div class='ctx'> 				     on_lru ? "on lru" : "active");</div><div class='ctx'> 			__free_page(alloc-&gt;pages[i].page_ptr);</div><div class='ctx'> 			page_count++;</div><div class='ctx'> 		}</div><div class='ctx'> 		kfree(alloc-&gt;pages);</div><div class='ctx'> 	}</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	if (alloc-&gt;mm)</div><div class='ctx'> 		mmdrop(alloc-&gt;mm);</div><div class='ctx'> </div><div class='hunk'>@@ -869,16 +952,6 @@ void binder_alloc_deferred_release(struct binder_alloc *alloc)</div><div class='ctx'> 		     __func__, alloc-&gt;pid, buffers, page_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void print_binder_buffer(struct seq_file *m, const char *prefix,</div><div class='del'>-				struct binder_buffer *buffer)</div><div class='del'>-{</div><div class='del'>-	seq_printf(m, "%s %d: %pK size %zd:%zd:%zd %s\n",</div><div class='del'>-		   prefix, buffer-&gt;debug_id, buffer-&gt;user_data,</div><div class='del'>-		   buffer-&gt;data_size, buffer-&gt;offsets_size,</div><div class='del'>-		   buffer-&gt;extra_buffers_size,</div><div class='del'>-		   buffer-&gt;transaction ? "active" : "delivered");</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * binder_alloc_print_allocated() - print buffer info</div><div class='ctx'>  * @m:     seq_file for output via seq_printf()</div><div class='hunk'>@@ -890,13 +963,20 @@ static void print_binder_buffer(struct seq_file *m, const char *prefix,</div><div class='ctx'> void binder_alloc_print_allocated(struct seq_file *m,</div><div class='ctx'> 				  struct binder_alloc *alloc)</div><div class='ctx'> {</div><div class='add'>+	struct binder_buffer *buffer;</div><div class='ctx'> 	struct rb_node *n;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='del'>-	for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n != NULL; n = rb_next(n))</div><div class='del'>-		print_binder_buffer(m, "  buffer",</div><div class='del'>-				    rb_entry(n, struct binder_buffer, rb_node));</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='add'>+	for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n; n = rb_next(n)) {</div><div class='add'>+		buffer = rb_entry(n, struct binder_buffer, rb_node);</div><div class='add'>+		seq_printf(m, "  buffer %d: %lx size %zd:%zd:%zd %s\n",</div><div class='add'>+			   buffer-&gt;debug_id,</div><div class='add'>+			   buffer-&gt;user_data - alloc-&gt;buffer,</div><div class='add'>+			   buffer-&gt;data_size, buffer-&gt;offsets_size,</div><div class='add'>+			   buffer-&gt;extra_buffers_size,</div><div class='add'>+			   buffer-&gt;transaction ? "active" : "delivered");</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -913,7 +993,7 @@ void binder_alloc_print_pages(struct seq_file *m,</div><div class='ctx'> 	int lru = 0;</div><div class='ctx'> 	int free = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Make sure the binder_alloc is fully initialized, otherwise we might</div><div class='ctx'> 	 * read inconsistent state.</div><div class='hunk'>@@ -929,7 +1009,7 @@ void binder_alloc_print_pages(struct seq_file *m,</div><div class='ctx'> 				lru++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	seq_printf(m, "  pages: %d:%d:%d\n", active, lru, free);</div><div class='ctx'> 	seq_printf(m, "  pages high watermark: %zu\n", alloc-&gt;pages_high);</div><div class='ctx'> }</div><div class='hunk'>@@ -945,10 +1025,10 @@ int binder_alloc_get_allocated_count(struct binder_alloc *alloc)</div><div class='ctx'> 	struct rb_node *n;</div><div class='ctx'> 	int count = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	for (n = rb_first(&amp;alloc-&gt;allocated_buffers); n != NULL; n = rb_next(n))</div><div class='ctx'> 		count++;</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -981,33 +1061,39 @@ enum lru_status binder_alloc_free_page(struct list_head *item,</div><div class='ctx'> 				       void *cb_arg)</div><div class='ctx'> 	__must_hold(lock)</div><div class='ctx'> {</div><div class='del'>-	struct mm_struct *mm = NULL;</div><div class='del'>-	struct binder_lru_page *page = container_of(item,</div><div class='del'>-						    struct binder_lru_page,</div><div class='del'>-						    lru);</div><div class='del'>-	struct binder_alloc *alloc;</div><div class='del'>-	uintptr_t page_addr;</div><div class='del'>-	size_t index;</div><div class='add'>+	struct binder_lru_page *page = container_of(item, typeof(*page), lru);</div><div class='add'>+	struct binder_alloc *alloc = page-&gt;alloc;</div><div class='add'>+	struct mm_struct *mm = alloc-&gt;mm;</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='add'>+	struct page *page_to_free;</div><div class='add'>+	unsigned long page_addr;</div><div class='add'>+	size_t index;</div><div class='ctx'> </div><div class='del'>-	alloc = page-&gt;alloc;</div><div class='del'>-	if (!mutex_trylock(&amp;alloc-&gt;mutex))</div><div class='del'>-		goto err_get_alloc_mutex_failed;</div><div class='del'>-</div><div class='add'>+	if (!mmget_not_zero(mm))</div><div class='add'>+		goto err_mmget;</div><div class='add'>+	if (!mmap_read_trylock(mm))</div><div class='add'>+		goto err_mmap_read_lock_failed;</div><div class='add'>+	if (!spin_trylock(&amp;alloc-&gt;lock))</div><div class='add'>+		goto err_get_alloc_lock_failed;</div><div class='ctx'> 	if (!page-&gt;page_ptr)</div><div class='ctx'> 		goto err_page_already_freed;</div><div class='ctx'> </div><div class='ctx'> 	index = page - alloc-&gt;pages;</div><div class='del'>-	page_addr = (uintptr_t)alloc-&gt;buffer + index * PAGE_SIZE;</div><div class='add'>+	page_addr = alloc-&gt;buffer + index * PAGE_SIZE;</div><div class='ctx'> </div><div class='del'>-	mm = alloc-&gt;mm;</div><div class='del'>-	if (!mmget_not_zero(mm))</div><div class='del'>-		goto err_mmget;</div><div class='del'>-	if (!mmap_read_trylock(mm))</div><div class='del'>-		goto err_mmap_read_lock_failed;</div><div class='del'>-	vma = binder_alloc_get_vma(alloc);</div><div class='add'>+	vma = vma_lookup(mm, page_addr);</div><div class='add'>+	if (vma &amp;&amp; vma != binder_alloc_get_vma(alloc))</div><div class='add'>+		goto err_invalid_vma;</div><div class='add'>+</div><div class='add'>+	trace_binder_unmap_kernel_start(alloc, index);</div><div class='add'>+</div><div class='add'>+	page_to_free = page-&gt;page_ptr;</div><div class='add'>+	page-&gt;page_ptr = NULL;</div><div class='add'>+</div><div class='add'>+	trace_binder_unmap_kernel_end(alloc, index);</div><div class='ctx'> </div><div class='ctx'> 	list_lru_isolate(lru, item);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	spin_unlock(lock);</div><div class='ctx'> </div><div class='ctx'> 	if (vma) {</div><div class='hunk'>@@ -1017,39 +1103,35 @@ enum lru_status binder_alloc_free_page(struct list_head *item,</div><div class='ctx'> </div><div class='ctx'> 		trace_binder_unmap_user_end(alloc, index);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	mmap_read_unlock(mm);</div><div class='ctx'> 	mmput_async(mm);</div><div class='del'>-</div><div class='del'>-	trace_binder_unmap_kernel_start(alloc, index);</div><div class='del'>-</div><div class='del'>-	__free_page(page-&gt;page_ptr);</div><div class='del'>-	page-&gt;page_ptr = NULL;</div><div class='del'>-</div><div class='del'>-	trace_binder_unmap_kernel_end(alloc, index);</div><div class='add'>+	__free_page(page_to_free);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(lock);</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='ctx'> 	return LRU_REMOVED_RETRY;</div><div class='ctx'> </div><div class='add'>+err_invalid_vma:</div><div class='add'>+err_page_already_freed:</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='add'>+err_get_alloc_lock_failed:</div><div class='add'>+	mmap_read_unlock(mm);</div><div class='ctx'> err_mmap_read_lock_failed:</div><div class='ctx'> 	mmput_async(mm);</div><div class='ctx'> err_mmget:</div><div class='del'>-err_page_already_freed:</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='del'>-err_get_alloc_mutex_failed:</div><div class='ctx'> 	return LRU_SKIP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned long</div><div class='ctx'> binder_shrink_count(struct shrinker *shrink, struct shrink_control *sc)</div><div class='ctx'> {</div><div class='del'>-	return list_lru_count(&amp;binder_alloc_lru);</div><div class='add'>+	return list_lru_count(&amp;binder_freelist);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned long</div><div class='ctx'> binder_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)</div><div class='ctx'> {</div><div class='del'>-	return list_lru_walk(&amp;binder_alloc_lru, binder_alloc_free_page,</div><div class='add'>+	return list_lru_walk(&amp;binder_freelist, binder_alloc_free_page,</div><div class='ctx'> 			    NULL, sc-&gt;nr_to_scan);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1067,7 +1149,7 @@ void binder_alloc_init(struct binder_alloc *alloc)</div><div class='ctx'> 	alloc-&gt;pid = current-&gt;group_leader-&gt;pid;</div><div class='ctx'> 	alloc-&gt;mm = current-&gt;mm;</div><div class='ctx'> 	mmgrab(alloc-&gt;mm);</div><div class='del'>-	mutex_init(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock_init(&amp;alloc-&gt;lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;alloc-&gt;buffers);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1075,13 +1157,13 @@ int binder_alloc_shrinker_init(void)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = list_lru_init(&amp;binder_alloc_lru);</div><div class='add'>+	ret = list_lru_init(&amp;binder_freelist);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	binder_shrinker = shrinker_alloc(0, "android-binder");</div><div class='ctx'> 	if (!binder_shrinker) {</div><div class='del'>-		list_lru_destroy(&amp;binder_alloc_lru);</div><div class='add'>+		list_lru_destroy(&amp;binder_freelist);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1096,7 +1178,7 @@ int binder_alloc_shrinker_init(void)</div><div class='ctx'> void binder_alloc_shrinker_exit(void)</div><div class='ctx'> {</div><div class='ctx'> 	shrinker_free(binder_shrinker);</div><div class='del'>-	list_lru_destroy(&amp;binder_alloc_lru);</div><div class='add'>+	list_lru_destroy(&amp;binder_freelist);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1132,68 +1214,6 @@ static inline bool check_buffer(struct binder_alloc *alloc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * binder_alloc_get_page() - get kernel pointer for given buffer offset</div><div class='del'>- * @alloc: binder_alloc for this proc</div><div class='del'>- * @buffer: binder buffer to be accessed</div><div class='del'>- * @buffer_offset: offset into @buffer data</div><div class='del'>- * @pgoffp: address to copy final page offset to</div><div class='del'>- *</div><div class='del'>- * Lookup the struct page corresponding to the address</div><div class='del'>- * at @buffer_offset into @buffer-&gt;user_data. If @pgoffp is not</div><div class='del'>- * NULL, the byte-offset into the page is written there.</div><div class='del'>- *</div><div class='del'>- * The caller is responsible to ensure that the offset points</div><div class='del'>- * to a valid address within the @buffer and that @buffer is</div><div class='del'>- * not freeable by the user. Since it can't be freed, we are</div><div class='del'>- * guaranteed that the corresponding elements of @alloc-&gt;pages[]</div><div class='del'>- * cannot change.</div><div class='del'>- *</div><div class='del'>- * Return: struct page</div><div class='del'>- */</div><div class='del'>-static struct page *binder_alloc_get_page(struct binder_alloc *alloc,</div><div class='del'>-					  struct binder_buffer *buffer,</div><div class='del'>-					  binder_size_t buffer_offset,</div><div class='del'>-					  pgoff_t *pgoffp)</div><div class='del'>-{</div><div class='del'>-	binder_size_t buffer_space_offset = buffer_offset +</div><div class='del'>-		(buffer-&gt;user_data - alloc-&gt;buffer);</div><div class='del'>-	pgoff_t pgoff = buffer_space_offset &amp; ~PAGE_MASK;</div><div class='del'>-	size_t index = buffer_space_offset &gt;&gt; PAGE_SHIFT;</div><div class='del'>-	struct binder_lru_page *lru_page;</div><div class='del'>-</div><div class='del'>-	lru_page = &amp;alloc-&gt;pages[index];</div><div class='del'>-	*pgoffp = pgoff;</div><div class='del'>-	return lru_page-&gt;page_ptr;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * binder_alloc_clear_buf() - zero out buffer</div><div class='del'>- * @alloc: binder_alloc for this proc</div><div class='del'>- * @buffer: binder buffer to be cleared</div><div class='del'>- *</div><div class='del'>- * memset the given buffer to 0</div><div class='del'>- */</div><div class='del'>-static void binder_alloc_clear_buf(struct binder_alloc *alloc,</div><div class='del'>-				   struct binder_buffer *buffer)</div><div class='del'>-{</div><div class='del'>-	size_t bytes = binder_alloc_buffer_size(alloc, buffer);</div><div class='del'>-	binder_size_t buffer_offset = 0;</div><div class='del'>-</div><div class='del'>-	while (bytes) {</div><div class='del'>-		unsigned long size;</div><div class='del'>-		struct page *page;</div><div class='del'>-		pgoff_t pgoff;</div><div class='del'>-</div><div class='del'>-		page = binder_alloc_get_page(alloc, buffer,</div><div class='del'>-					     buffer_offset, &amp;pgoff);</div><div class='del'>-		size = min_t(size_t, bytes, PAGE_SIZE - pgoff);</div><div class='del'>-		memset_page(page, pgoff, 0, size);</div><div class='del'>-		bytes -= size;</div><div class='del'>-		buffer_offset += size;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * binder_alloc_copy_user_to_buffer() - copy src user to tgt user</div><div class='ctx'>  * @alloc: binder_alloc for this proc</div><div class='ctx'>  * @buffer: binder buffer to be accessed</div><div class='hunk'>@@ -1287,4 +1307,3 @@ int binder_alloc_copy_from_buffer(struct binder_alloc *alloc,</div><div class='ctx'> 	return binder_alloc_do_buffer_copy(alloc, false, buffer, buffer_offset,</div><div class='ctx'> 					   dest, bytes);</div><div class='ctx'> }</div><div class='del'>-</div><div class='head'>diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h<br/>index dc1e2b01dd64..70387234477e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binder_alloc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc.h</a></div><div class='hunk'>@@ -9,13 +9,13 @@</div><div class='ctx'> #include &lt;linux/rbtree.h&gt;</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/mm.h&gt;</div><div class='del'>-#include &lt;linux/rtmutex.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/list_lru.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/android/binder.h&gt;</div><div class='ctx'> </div><div class='del'>-extern struct list_lru binder_alloc_lru;</div><div class='add'>+extern struct list_lru binder_freelist;</div><div class='ctx'> struct binder_transaction;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -49,21 +49,19 @@ struct binder_buffer {</div><div class='ctx'> 	unsigned async_transaction:1;</div><div class='ctx'> 	unsigned oneway_spam_suspect:1;</div><div class='ctx'> 	unsigned debug_id:27;</div><div class='del'>-</div><div class='ctx'> 	struct binder_transaction *transaction;</div><div class='del'>-</div><div class='ctx'> 	struct binder_node *target_node;</div><div class='ctx'> 	size_t data_size;</div><div class='ctx'> 	size_t offsets_size;</div><div class='ctx'> 	size_t extra_buffers_size;</div><div class='del'>-	void __user *user_data;</div><div class='del'>-	int    pid;</div><div class='add'>+	unsigned long user_data;</div><div class='add'>+	int pid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct binder_lru_page - page object used for binder shrinker</div><div class='ctx'>  * @page_ptr: pointer to physical page in mmap'd space</div><div class='del'>- * @lru:      entry in binder_alloc_lru</div><div class='add'>+ * @lru:      entry in binder_freelist</div><div class='ctx'>  * @alloc:    binder_alloc for a proc</div><div class='ctx'>  */</div><div class='ctx'> struct binder_lru_page {</div><div class='hunk'>@@ -74,7 +72,7 @@ struct binder_lru_page {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct binder_alloc - per-binder proc state for binder allocator</div><div class='del'>- * @mutex:              protects binder_alloc fields</div><div class='add'>+ * @lock:               protects binder_alloc fields</div><div class='ctx'>  * @vma:                vm_area_struct passed to mmap_handler</div><div class='ctx'>  *                      (invariant after mmap)</div><div class='ctx'>  * @mm:                 copy of task-&gt;mm (invariant after open)</div><div class='hunk'>@@ -98,10 +96,10 @@ struct binder_lru_page {</div><div class='ctx'>  * struct binder_buffer objects used to track the user buffers</div><div class='ctx'>  */</div><div class='ctx'> struct binder_alloc {</div><div class='del'>-	struct mutex mutex;</div><div class='add'>+	spinlock_t lock;</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='ctx'> 	struct mm_struct *mm;</div><div class='del'>-	void __user *buffer;</div><div class='add'>+	unsigned long buffer;</div><div class='ctx'> 	struct list_head buffers;</div><div class='ctx'> 	struct rb_root free_buffers;</div><div class='ctx'> 	struct rb_root allocated_buffers;</div><div class='hunk'>@@ -121,27 +119,26 @@ static inline void binder_selftest_alloc(struct binder_alloc *alloc) {}</div><div class='ctx'> enum lru_status binder_alloc_free_page(struct list_head *item,</div><div class='ctx'> 				       struct list_lru_one *lru,</div><div class='ctx'> 				       spinlock_t *lock, void *cb_arg);</div><div class='del'>-extern struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,</div><div class='del'>-						  size_t data_size,</div><div class='del'>-						  size_t offsets_size,</div><div class='del'>-						  size_t extra_buffers_size,</div><div class='del'>-						  int is_async,</div><div class='del'>-						  int pid);</div><div class='del'>-extern void binder_alloc_init(struct binder_alloc *alloc);</div><div class='del'>-extern int binder_alloc_shrinker_init(void);</div><div class='del'>-extern void binder_alloc_shrinker_exit(void);</div><div class='del'>-extern void binder_alloc_vma_close(struct binder_alloc *alloc);</div><div class='del'>-extern struct binder_buffer *</div><div class='add'>+struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,</div><div class='add'>+					   size_t data_size,</div><div class='add'>+					   size_t offsets_size,</div><div class='add'>+					   size_t extra_buffers_size,</div><div class='add'>+					   int is_async);</div><div class='add'>+void binder_alloc_init(struct binder_alloc *alloc);</div><div class='add'>+int binder_alloc_shrinker_init(void);</div><div class='add'>+void binder_alloc_shrinker_exit(void);</div><div class='add'>+void binder_alloc_vma_close(struct binder_alloc *alloc);</div><div class='add'>+struct binder_buffer *</div><div class='ctx'> binder_alloc_prepare_to_free(struct binder_alloc *alloc,</div><div class='del'>-			     uintptr_t user_ptr);</div><div class='del'>-extern void binder_alloc_free_buf(struct binder_alloc *alloc,</div><div class='del'>-				  struct binder_buffer *buffer);</div><div class='del'>-extern int binder_alloc_mmap_handler(struct binder_alloc *alloc,</div><div class='del'>-				     struct vm_area_struct *vma);</div><div class='del'>-extern void binder_alloc_deferred_release(struct binder_alloc *alloc);</div><div class='del'>-extern int binder_alloc_get_allocated_count(struct binder_alloc *alloc);</div><div class='del'>-extern void binder_alloc_print_allocated(struct seq_file *m,</div><div class='del'>-					 struct binder_alloc *alloc);</div><div class='add'>+			     unsigned long user_ptr);</div><div class='add'>+void binder_alloc_free_buf(struct binder_alloc *alloc,</div><div class='add'>+			   struct binder_buffer *buffer);</div><div class='add'>+int binder_alloc_mmap_handler(struct binder_alloc *alloc,</div><div class='add'>+			      struct vm_area_struct *vma);</div><div class='add'>+void binder_alloc_deferred_release(struct binder_alloc *alloc);</div><div class='add'>+int binder_alloc_get_allocated_count(struct binder_alloc *alloc);</div><div class='add'>+void binder_alloc_print_allocated(struct seq_file *m,</div><div class='add'>+				  struct binder_alloc *alloc);</div><div class='ctx'> void binder_alloc_print_pages(struct seq_file *m,</div><div class='ctx'> 			      struct binder_alloc *alloc);</div><div class='ctx'> </div><div class='hunk'>@@ -156,9 +153,9 @@ binder_alloc_get_free_async_space(struct binder_alloc *alloc)</div><div class='ctx'> {</div><div class='ctx'> 	size_t free_async_space;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_lock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	free_async_space = alloc-&gt;free_async_space;</div><div class='del'>-	mutex_unlock(&amp;alloc-&gt;mutex);</div><div class='add'>+	spin_unlock(&amp;alloc-&gt;lock);</div><div class='ctx'> 	return free_async_space;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/android/binder_alloc_selftest.c b/drivers/android/binder_alloc_selftest.c<br/>index c2b323bc3b3a..81442fe20a69 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc_selftest.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binder_alloc_selftest.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binder_alloc_selftest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_alloc_selftest.c</a></div><div class='hunk'>@@ -72,6 +72,10 @@ enum buf_end_align_type {</div><div class='ctx'> 	 * buf1 ]|[ buf2 | buf2 | buf2 ][ ...</div><div class='ctx'> 	 */</div><div class='ctx'> 	NEXT_NEXT_UNALIGNED,</div><div class='add'>+	/**</div><div class='add'>+	 * @LOOP_END: The number of enum values in &amp;buf_end_align_type.</div><div class='add'>+	 * It is used for controlling loop termination.</div><div class='add'>+	 */</div><div class='ctx'> 	LOOP_END,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -93,11 +97,11 @@ static bool check_buffer_pages_allocated(struct binder_alloc *alloc,</div><div class='ctx'> 					 struct binder_buffer *buffer,</div><div class='ctx'> 					 size_t size)</div><div class='ctx'> {</div><div class='del'>-	void __user *page_addr;</div><div class='del'>-	void __user *end;</div><div class='add'>+	unsigned long page_addr;</div><div class='add'>+	unsigned long end;</div><div class='ctx'> 	int page_index;</div><div class='ctx'> </div><div class='del'>-	end = (void __user *)PAGE_ALIGN((uintptr_t)buffer-&gt;user_data + size);</div><div class='add'>+	end = PAGE_ALIGN(buffer-&gt;user_data + size);</div><div class='ctx'> 	page_addr = buffer-&gt;user_data;</div><div class='ctx'> 	for (; page_addr &lt; end; page_addr += PAGE_SIZE) {</div><div class='ctx'> 		page_index = (page_addr - alloc-&gt;buffer) / PAGE_SIZE;</div><div class='hunk'>@@ -119,7 +123,7 @@ static void binder_selftest_alloc_buf(struct binder_alloc *alloc,</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; BUFFER_NUM; i++) {</div><div class='del'>-		buffers[i] = binder_alloc_new_buf(alloc, sizes[i], 0, 0, 0, 0);</div><div class='add'>+		buffers[i] = binder_alloc_new_buf(alloc, sizes[i], 0, 0, 0);</div><div class='ctx'> 		if (IS_ERR(buffers[i]) ||</div><div class='ctx'> 		    !check_buffer_pages_allocated(alloc, buffers[i],</div><div class='ctx'> 						  sizes[i])) {</div><div class='hunk'>@@ -158,8 +162,8 @@ static void binder_selftest_free_page(struct binder_alloc *alloc)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	unsigned long count;</div><div class='ctx'> </div><div class='del'>-	while ((count = list_lru_count(&amp;binder_alloc_lru))) {</div><div class='del'>-		list_lru_walk(&amp;binder_alloc_lru, binder_alloc_free_page,</div><div class='add'>+	while ((count = list_lru_count(&amp;binder_freelist))) {</div><div class='add'>+		list_lru_walk(&amp;binder_freelist, binder_alloc_free_page,</div><div class='ctx'> 			      NULL, count);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -183,7 +187,7 @@ static void binder_selftest_alloc_free(struct binder_alloc *alloc,</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate from lru. */</div><div class='ctx'> 	binder_selftest_alloc_buf(alloc, buffers, sizes, seq);</div><div class='del'>-	if (list_lru_count(&amp;binder_alloc_lru))</div><div class='add'>+	if (list_lru_count(&amp;binder_freelist))</div><div class='ctx'> 		pr_err("lru list should be empty but is not\n");</div><div class='ctx'> </div><div class='ctx'> 	binder_selftest_free_buf(alloc, buffers, sizes, seq, end);</div><div class='head'>diff --git a/drivers/android/binder_trace.h b/drivers/android/binder_trace.h<br/>index 8cc07e6a4273..fe38c6fc65d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binder_trace.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binder_trace.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binder_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binder_trace.h</a></div><div class='hunk'>@@ -317,7 +317,7 @@ DEFINE_EVENT(binder_buffer_class, binder_transaction_update_buffer_release,</div><div class='ctx'> </div><div class='ctx'> TRACE_EVENT(binder_update_page_range,</div><div class='ctx'> 	TP_PROTO(struct binder_alloc *alloc, bool allocate,</div><div class='del'>-		 void __user *start, void __user *end),</div><div class='add'>+		 unsigned long start, unsigned long end),</div><div class='ctx'> 	TP_ARGS(alloc, allocate, start, end),</div><div class='ctx'> 	TP_STRUCT__entry(</div><div class='ctx'> 		__field(int, proc)</div><div class='head'>diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c<br/>index 1224ab7aa070..3001d754ac36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/android/binderfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/android/binderfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/android/binderfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/android/binderfs.c</a></div><div class='hunk'>@@ -29,7 +29,6 @@</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> #include &lt;linux/user_namespace.h&gt;</div><div class='ctx'> #include &lt;linux/xarray.h&gt;</div><div class='del'>-#include &lt;uapi/asm-generic/errno-base.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/android/binder.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/android/binderfs.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c<br/>index c10ff8985203..0a0f483124c3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/ata/libata-scsi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/ata/libata-scsi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/ata/libata-scsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ata/libata-scsi.c</a></div><div class='hunk'>@@ -1055,9 +1055,14 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)</div><div class='ctx'> 		 * Ask the sd driver to issue START STOP UNIT on runtime suspend</div><div class='ctx'> 		 * and resume and shutdown only. For system level suspend/resume,</div><div class='ctx'> 		 * devices power state is handled directly by libata EH.</div><div class='add'>+		 * Given that disks are always spun up on system resume, also</div><div class='add'>+		 * make sure that the sd driver forces runtime suspended disks</div><div class='add'>+		 * to be resumed to correctly reflect the power state of the</div><div class='add'>+		 * device.</div><div class='ctx'> 		 */</div><div class='del'>-		sdev-&gt;manage_runtime_start_stop = true;</div><div class='del'>-		sdev-&gt;manage_shutdown = true;</div><div class='add'>+		sdev-&gt;manage_runtime_start_stop = 1;</div><div class='add'>+		sdev-&gt;manage_shutdown = 1;</div><div class='add'>+		sdev-&gt;force_runtime_start_on_system_start = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='head'>diff --git a/drivers/ata/pata_pxa.c b/drivers/ata/pata_pxa.c<br/>index 5275c6464f57..538bd3423d85 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/ata/pata_pxa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/ata/pata_pxa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/ata/pata_pxa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ata/pata_pxa.c</a></div><div class='hunk'>@@ -274,10 +274,9 @@ static int pxa_ata_probe(struct platform_device *pdev)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Request the DMA channel</div><div class='ctx'> 	 */</div><div class='del'>-	data-&gt;dma_chan =</div><div class='del'>-		dma_request_slave_channel(&amp;pdev-&gt;dev, "data");</div><div class='del'>-	if (!data-&gt;dma_chan)</div><div class='del'>-		return -EBUSY;</div><div class='add'>+	data-&gt;dma_chan = dma_request_chan(&amp;pdev-&gt;dev, "data");</div><div class='add'>+	if (IS_ERR(data-&gt;dma_chan))</div><div class='add'>+		return PTR_ERR(data-&gt;dma_chan);</div><div class='ctx'> 	ret = dmaengine_slave_config(data-&gt;dma_chan, &amp;config);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "dma configuration failed: %d\n", ret);</div><div class='head'>diff --git a/drivers/atm/atmtcp.c b/drivers/atm/atmtcp.c<br/>index 96bea1ab1ecc..d4aa0f353b6c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/atmtcp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/atmtcp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/atmtcp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/atmtcp.c</a></div><div class='hunk'>@@ -494,6 +494,7 @@ static void __exit atmtcp_exit(void)</div><div class='ctx'> 	deregister_atm_ioctl(&amp;atmtcp_ioctl_ops);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("ATM over TCP");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> module_init(atmtcp_init);</div><div class='ctx'> module_exit(atmtcp_exit);</div><div class='head'>diff --git a/drivers/atm/eni.c b/drivers/atm/eni.c<br/>index a31ffe16e626..3011cf1a84a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/eni.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/eni.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/eni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/eni.c</a></div><div class='hunk'>@@ -2318,4 +2318,5 @@ static int __init eni_init(void)</div><div class='ctx'> module_init(eni_init);</div><div class='ctx'> /* @@@ since exit routine not defined, this module can not be unloaded */</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("Efficient Networks ENI155P ATM NIC driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/atm/idt77105.c b/drivers/atm/idt77105.c<br/>index bfca7b8a6f31..fcd70e094a2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/idt77105.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/idt77105.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/idt77105.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/idt77105.c</a></div><div class='hunk'>@@ -372,4 +372,5 @@ static void __exit idt77105_exit(void)</div><div class='ctx'> </div><div class='ctx'> module_exit(idt77105_exit);</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("IDT77105 PHY driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c<br/>index 9bba8f280a4d..d213adcefe33 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/iphase.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/iphase.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/iphase.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/iphase.c</a></div><div class='hunk'>@@ -90,6 +90,7 @@ module_param(IA_RX_BUF, int, 0);</div><div class='ctx'> module_param(IA_RX_BUF_SZ, int, 0);</div><div class='ctx'> module_param(IADebugFlag, uint, 0644);</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("Driver for Interphase ATM PCI NICs");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> </div><div class='ctx'> /**************************** IA_LIB **********************************/</div><div class='head'>diff --git a/drivers/atm/nicstar.c b/drivers/atm/nicstar.c<br/>index 1a50de39f5b5..27153d6bc781 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/nicstar.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/nicstar.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/nicstar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/nicstar.c</a></div><div class='hunk'>@@ -171,6 +171,7 @@ static const struct atmdev_ops atm_ops = {</div><div class='ctx'> static struct timer_list ns_timer;</div><div class='ctx'> static char *mac[NS_MAX_CARDS];</div><div class='ctx'> module_param_array(mac, charp, NULL, 0);</div><div class='add'>+MODULE_DESCRIPTION("ATM NIC driver for IDT 77201/77211 \"NICStAR\" and Fore ForeRunnerLE.");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> </div><div class='ctx'> /* Functions */</div><div class='head'>diff --git a/drivers/atm/solos-pci.c b/drivers/atm/solos-pci.c<br/>index 94fbc3abe60e..d3c30a28c410 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/solos-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/solos-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/solos-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/solos-pci.c</a></div><div class='hunk'>@@ -449,9 +449,9 @@ static ssize_t console_show(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	unsigned int len;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;card-&gt;cli_queue_lock);</div><div class='add'>+	spin_lock_bh(&amp;card-&gt;cli_queue_lock);</div><div class='ctx'> 	skb = skb_dequeue(&amp;card-&gt;cli_queue[SOLOS_CHAN(atmdev)]);</div><div class='del'>-	spin_unlock(&amp;card-&gt;cli_queue_lock);</div><div class='add'>+	spin_unlock_bh(&amp;card-&gt;cli_queue_lock);</div><div class='ctx'> 	if(skb == NULL)</div><div class='ctx'> 		return sprintf(buf, "No data.\n");</div><div class='ctx'> </div><div class='hunk'>@@ -956,14 +956,14 @@ static void pclose(struct atm_vcc *vcc)</div><div class='ctx'> 	struct pkt_hdr *header;</div><div class='ctx'> </div><div class='ctx'> 	/* Remove any yet-to-be-transmitted packets from the pending queue */</div><div class='del'>-	spin_lock(&amp;card-&gt;tx_queue_lock);</div><div class='add'>+	spin_lock_bh(&amp;card-&gt;tx_queue_lock);</div><div class='ctx'> 	skb_queue_walk_safe(&amp;card-&gt;tx_queue[port], skb, tmpskb) {</div><div class='ctx'> 		if (SKB_CB(skb)-&gt;vcc == vcc) {</div><div class='ctx'> 			skb_unlink(skb, &amp;card-&gt;tx_queue[port]);</div><div class='ctx'> 			solos_pop(vcc, skb);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	spin_unlock(&amp;card-&gt;tx_queue_lock);</div><div class='add'>+	spin_unlock_bh(&amp;card-&gt;tx_queue_lock);</div><div class='ctx'> </div><div class='ctx'> 	skb = alloc_skb(sizeof(*header), GFP_KERNEL);</div><div class='ctx'> 	if (!skb) {</div><div class='head'>diff --git a/drivers/atm/suni.c b/drivers/atm/suni.c<br/>index 21e5acc766b8..32802ea9521c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/atm/suni.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/atm/suni.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/atm/suni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/atm/suni.c</a></div><div class='hunk'>@@ -387,4 +387,5 @@ int suni_init(struct atm_dev *dev)</div><div class='ctx'> </div><div class='ctx'> EXPORT_SYMBOL(suni_init);</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("S/UNI PHY driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/auxdisplay/img-ascii-lcd.c b/drivers/auxdisplay/img-ascii-lcd.c<br/>index fa23e415f260..56efda0740fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/auxdisplay/img-ascii-lcd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/auxdisplay/img-ascii-lcd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/auxdisplay/img-ascii-lcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/auxdisplay/img-ascii-lcd.c</a></div><div class='hunk'>@@ -8,9 +8,9 @@</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/syscon.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/of_address.h&gt;</div><div class='del'>-#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -225,17 +225,11 @@ MODULE_DEVICE_TABLE(of, img_ascii_lcd_matches);</div><div class='ctx'>  */</div><div class='ctx'> static int img_ascii_lcd_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *match;</div><div class='del'>-	const struct img_ascii_lcd_config *cfg;</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	const struct img_ascii_lcd_config *cfg = device_get_match_data(dev);</div><div class='ctx'> 	struct img_ascii_lcd_ctx *ctx;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	match = of_match_device(img_ascii_lcd_matches, dev);</div><div class='del'>-	if (!match)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	cfg = match-&gt;data;</div><div class='ctx'> 	ctx = devm_kzalloc(dev, sizeof(*ctx) + cfg-&gt;num_chars, GFP_KERNEL);</div><div class='ctx'> 	if (!ctx)</div><div class='ctx'> 		return -ENOMEM;</div><div class='head'>diff --git a/drivers/base/arch_numa.c b/drivers/base/arch_numa.c<br/>index eaa31e567d1e..5b59d133b6af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/arch_numa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/arch_numa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/arch_numa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/arch_numa.c</a></div><div class='hunk'>@@ -144,7 +144,7 @@ void __init early_map_cpu_to_node(unsigned int cpu, int nid)</div><div class='ctx'> unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;</div><div class='ctx'> EXPORT_SYMBOL(__per_cpu_offset);</div><div class='ctx'> </div><div class='del'>-static int __init early_cpu_to_node(int cpu)</div><div class='add'>+int __init early_cpu_to_node(int cpu)</div><div class='ctx'> {</div><div class='ctx'> 	return cpu_to_node_map[cpu];</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c<br/>index b741b5ba82bd..018ac202de34 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/arch_topology.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/arch_topology.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/arch_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/arch_topology.c</a></div><div class='hunk'>@@ -19,6 +19,7 @@</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/rcupdate.h&gt;</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define CREATE_TRACE_POINTS</div><div class='ctx'> #include &lt;trace/events/thermal_pressure.h&gt;</div><div class='hunk'>@@ -26,7 +27,8 @@</div><div class='ctx'> static DEFINE_PER_CPU(struct scale_freq_data __rcu *, sft_data);</div><div class='ctx'> static struct cpumask scale_freq_counters_mask;</div><div class='ctx'> static bool scale_freq_invariant;</div><div class='del'>-static DEFINE_PER_CPU(u32, freq_factor) = 1;</div><div class='add'>+DEFINE_PER_CPU(unsigned long, capacity_freq_ref) = 1;</div><div class='add'>+EXPORT_PER_CPU_SYMBOL_GPL(capacity_freq_ref);</div><div class='ctx'> </div><div class='ctx'> static bool supports_scale_freq_counters(const struct cpumask *cpus)</div><div class='ctx'> {</div><div class='hunk'>@@ -170,9 +172,9 @@ DEFINE_PER_CPU(unsigned long, thermal_pressure);</div><div class='ctx'>  * operating on stale data when hot-plug is used for some CPUs. The</div><div class='ctx'>  * @capped_freq reflects the currently allowed max CPUs frequency due to</div><div class='ctx'>  * thermal capping. It might be also a boost frequency value, which is bigger</div><div class='del'>- * than the internal 'freq_factor' max frequency. In such case the pressure</div><div class='del'>- * value should simply be removed, since this is an indication that there is</div><div class='del'>- * no thermal throttling. The @capped_freq must be provided in kHz.</div><div class='add'>+ * than the internal 'capacity_freq_ref' max frequency. In such case the</div><div class='add'>+ * pressure value should simply be removed, since this is an indication that</div><div class='add'>+ * there is no thermal throttling. The @capped_freq must be provided in kHz.</div><div class='ctx'>  */</div><div class='ctx'> void topology_update_thermal_pressure(const struct cpumask *cpus,</div><div class='ctx'> 				      unsigned long capped_freq)</div><div class='hunk'>@@ -183,10 +185,7 @@ void topology_update_thermal_pressure(const struct cpumask *cpus,</div><div class='ctx'> </div><div class='ctx'> 	cpu = cpumask_first(cpus);</div><div class='ctx'> 	max_capacity = arch_scale_cpu_capacity(cpu);</div><div class='del'>-	max_freq = per_cpu(freq_factor, cpu);</div><div class='del'>-</div><div class='del'>-	/* Convert to MHz scale which is used in 'freq_factor' */</div><div class='del'>-	capped_freq /= 1000;</div><div class='add'>+	max_freq = arch_scale_freq_ref(cpu);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Handle properly the boost frequencies, which should simply clean</div><div class='hunk'>@@ -220,20 +219,34 @@ static DECLARE_WORK(update_topology_flags_work, update_topology_flags_workfn);</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR_RO(cpu_capacity);</div><div class='ctx'> </div><div class='del'>-static int register_cpu_capacity_sysctl(void)</div><div class='add'>+static int cpu_capacity_sysctl_add(unsigned int cpu)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-	struct device *cpu;</div><div class='add'>+	struct device *cpu_dev = get_cpu_device(cpu);</div><div class='ctx'> </div><div class='del'>-	for_each_possible_cpu(i) {</div><div class='del'>-		cpu = get_cpu_device(i);</div><div class='del'>-		if (!cpu) {</div><div class='del'>-			pr_err("%s: too early to get CPU%d device!\n",</div><div class='del'>-			       __func__, i);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-		device_create_file(cpu, &amp;dev_attr_cpu_capacity);</div><div class='del'>-	}</div><div class='add'>+	if (!cpu_dev)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	device_create_file(cpu_dev, &amp;dev_attr_cpu_capacity);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cpu_capacity_sysctl_remove(unsigned int cpu)</div><div class='add'>+{</div><div class='add'>+	struct device *cpu_dev = get_cpu_device(cpu);</div><div class='add'>+</div><div class='add'>+	if (!cpu_dev)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	device_remove_file(cpu_dev, &amp;dev_attr_cpu_capacity);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int register_cpu_capacity_sysctl(void)</div><div class='add'>+{</div><div class='add'>+	cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "topology/cpu-capacity",</div><div class='add'>+			  cpu_capacity_sysctl_add, cpu_capacity_sysctl_remove);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -279,13 +292,13 @@ void topology_normalize_cpu_scale(void)</div><div class='ctx'> </div><div class='ctx'> 	capacity_scale = 1;</div><div class='ctx'> 	for_each_possible_cpu(cpu) {</div><div class='del'>-		capacity = raw_capacity[cpu] * per_cpu(freq_factor, cpu);</div><div class='add'>+		capacity = raw_capacity[cpu] * per_cpu(capacity_freq_ref, cpu);</div><div class='ctx'> 		capacity_scale = max(capacity, capacity_scale);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("cpu_capacity: capacity_scale=%llu\n", capacity_scale);</div><div class='ctx'> 	for_each_possible_cpu(cpu) {</div><div class='del'>-		capacity = raw_capacity[cpu] * per_cpu(freq_factor, cpu);</div><div class='add'>+		capacity = raw_capacity[cpu] * per_cpu(capacity_freq_ref, cpu);</div><div class='ctx'> 		capacity = div64_u64(capacity &lt;&lt; SCHED_CAPACITY_SHIFT,</div><div class='ctx'> 			capacity_scale);</div><div class='ctx'> 		topology_set_cpu_scale(cpu, capacity);</div><div class='hunk'>@@ -321,15 +334,15 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)</div><div class='ctx'> 			cpu_node, raw_capacity[cpu]);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * Update freq_factor for calculating early boot cpu capacities.</div><div class='add'>+		 * Update capacity_freq_ref for calculating early boot CPU capacities.</div><div class='ctx'> 		 * For non-clk CPU DVFS mechanism, there's no way to get the</div><div class='ctx'> 		 * frequency value now, assuming they are running at the same</div><div class='del'>-		 * frequency (by keeping the initial freq_factor value).</div><div class='add'>+		 * frequency (by keeping the initial capacity_freq_ref value).</div><div class='ctx'> 		 */</div><div class='ctx'> 		cpu_clk = of_clk_get(cpu_node, 0);</div><div class='ctx'> 		if (!PTR_ERR_OR_ZERO(cpu_clk)) {</div><div class='del'>-			per_cpu(freq_factor, cpu) =</div><div class='del'>-				clk_get_rate(cpu_clk) / 1000;</div><div class='add'>+			per_cpu(capacity_freq_ref, cpu) =</div><div class='add'>+				clk_get_rate(cpu_clk) / HZ_PER_KHZ;</div><div class='ctx'> 			clk_put(cpu_clk);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -345,11 +358,16 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)</div><div class='ctx'> 	return !ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void __weak freq_inv_set_max_ratio(int cpu, u64 max_rate)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_ACPI_CPPC_LIB</div><div class='ctx'> #include &lt;acpi/cppc_acpi.h&gt;</div><div class='ctx'> </div><div class='ctx'> void topology_init_cpu_capacity_cppc(void)</div><div class='ctx'> {</div><div class='add'>+	u64 capacity, capacity_scale = 0;</div><div class='ctx'> 	struct cppc_perf_caps perf_caps;</div><div class='ctx'> 	int cpu;</div><div class='ctx'> </div><div class='hunk'>@@ -366,6 +384,10 @@ void topology_init_cpu_capacity_cppc(void)</div><div class='ctx'> 		    (perf_caps.highest_perf &gt;= perf_caps.nominal_perf) &amp;&amp;</div><div class='ctx'> 		    (perf_caps.highest_perf &gt;= perf_caps.lowest_perf)) {</div><div class='ctx'> 			raw_capacity[cpu] = perf_caps.highest_perf;</div><div class='add'>+			capacity_scale = max_t(u64, capacity_scale, raw_capacity[cpu]);</div><div class='add'>+</div><div class='add'>+			per_cpu(capacity_freq_ref, cpu) = cppc_perf_to_khz(&amp;perf_caps, raw_capacity[cpu]);</div><div class='add'>+</div><div class='ctx'> 			pr_debug("cpu_capacity: CPU%d cpu_capacity=%u (raw).\n",</div><div class='ctx'> 				 cpu, raw_capacity[cpu]);</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -376,7 +398,18 @@ void topology_init_cpu_capacity_cppc(void)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	topology_normalize_cpu_scale();</div><div class='add'>+	for_each_possible_cpu(cpu) {</div><div class='add'>+		freq_inv_set_max_ratio(cpu,</div><div class='add'>+				       per_cpu(capacity_freq_ref, cpu) * HZ_PER_KHZ);</div><div class='add'>+</div><div class='add'>+		capacity = raw_capacity[cpu];</div><div class='add'>+		capacity = div64_u64(capacity &lt;&lt; SCHED_CAPACITY_SHIFT,</div><div class='add'>+				     capacity_scale);</div><div class='add'>+		topology_set_cpu_scale(cpu, capacity);</div><div class='add'>+		pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n",</div><div class='add'>+			cpu, topology_get_cpu_scale(cpu));</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	schedule_work(&amp;update_topology_flags_work);</div><div class='ctx'> 	pr_debug("cpu_capacity: cpu_capacity initialization done\n");</div><div class='ctx'> </div><div class='hunk'>@@ -410,8 +443,11 @@ init_cpu_capacity_callback(struct notifier_block *nb,</div><div class='ctx'> </div><div class='ctx'> 	cpumask_andnot(cpus_to_visit, cpus_to_visit, policy-&gt;related_cpus);</div><div class='ctx'> </div><div class='del'>-	for_each_cpu(cpu, policy-&gt;related_cpus)</div><div class='del'>-		per_cpu(freq_factor, cpu) = policy-&gt;cpuinfo.max_freq / 1000;</div><div class='add'>+	for_each_cpu(cpu, policy-&gt;related_cpus) {</div><div class='add'>+		per_cpu(capacity_freq_ref, cpu) = policy-&gt;cpuinfo.max_freq;</div><div class='add'>+		freq_inv_set_max_ratio(cpu,</div><div class='add'>+				       per_cpu(capacity_freq_ref, cpu) * HZ_PER_KHZ);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (cpumask_empty(cpus_to_visit)) {</div><div class='ctx'> 		topology_normalize_cpu_scale();</div><div class='head'>diff --git a/drivers/base/auxiliary.c b/drivers/base/auxiliary.c<br/>index 4d4c2c8d26c4..d3a2c40c2f12 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/auxiliary.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/auxiliary.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/auxiliary.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/auxiliary.c</a></div><div class='hunk'>@@ -244,7 +244,7 @@ static void auxiliary_bus_shutdown(struct device *dev)</div><div class='ctx'> 		auxdrv-&gt;shutdown(auxdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct bus_type auxiliary_bus_type = {</div><div class='add'>+static const struct bus_type auxiliary_bus_type = {</div><div class='ctx'> 	.name = "auxiliary",</div><div class='ctx'> 	.probe = auxiliary_bus_probe,</div><div class='ctx'> 	.remove = auxiliary_bus_remove,</div><div class='head'>diff --git a/drivers/base/bus.c b/drivers/base/bus.c<br/>index 84a21084d67d..daee55c9b2d9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/bus.c</a></div><div class='hunk'>@@ -1030,7 +1030,7 @@ static void device_insertion_sort_klist(struct device *a, struct list_head *list</div><div class='ctx'> 	list_move_tail(&amp;a-&gt;p-&gt;knode_bus.n_node, list);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void bus_sort_breadthfirst(struct bus_type *bus,</div><div class='add'>+void bus_sort_breadthfirst(const struct bus_type *bus,</div><div class='ctx'> 			   int (*compare)(const struct device *a,</div><div class='ctx'> 					  const struct device *b))</div><div class='ctx'> {</div><div class='hunk'>@@ -1194,7 +1194,7 @@ static void system_root_device_release(struct device *dev)</div><div class='ctx'> 	kfree(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int subsys_register(struct bus_type *subsys,</div><div class='add'>+static int subsys_register(const struct bus_type *subsys,</div><div class='ctx'> 			   const struct attribute_group **groups,</div><div class='ctx'> 			   struct kobject *parent_of_root)</div><div class='ctx'> {</div><div class='hunk'>@@ -1264,7 +1264,7 @@ err_sp:</div><div class='ctx'>  * directory itself and not some create fake root-device placed in</div><div class='ctx'>  * /sys/devices/system/&lt;name&gt;.</div><div class='ctx'>  */</div><div class='del'>-int subsys_system_register(struct bus_type *subsys,</div><div class='add'>+int subsys_system_register(const struct bus_type *subsys,</div><div class='ctx'> 			   const struct attribute_group **groups)</div><div class='ctx'> {</div><div class='ctx'> 	return subsys_register(subsys, groups, &amp;system_kset-&gt;kobj);</div><div class='hunk'>@@ -1282,7 +1282,7 @@ EXPORT_SYMBOL_GPL(subsys_system_register);</div><div class='ctx'>  * There's no restriction on device naming.  This is for kernel software</div><div class='ctx'>  * constructs which need sysfs interface.</div><div class='ctx'>  */</div><div class='del'>-int subsys_virtual_register(struct bus_type *subsys,</div><div class='add'>+int subsys_virtual_register(const struct bus_type *subsys,</div><div class='ctx'> 			    const struct attribute_group **groups)</div><div class='ctx'> {</div><div class='ctx'> 	struct kobject *virtual_dir;</div><div class='head'>diff --git a/drivers/base/class.c b/drivers/base/class.c<br/>index 7e78aee0fd6c..7b38fdf8e1d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/class.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/class.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/class.c</a></div><div class='hunk'>@@ -213,6 +213,7 @@ int class_register(const struct class *cls)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_out:</div><div class='add'>+	lockdep_unregister_key(key);</div><div class='ctx'> 	kfree(cp);</div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/base/container.c b/drivers/base/container.c<br/>index 1ba42d2d3532..f40588ebc3f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/container.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/container.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/container.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/container.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@ static int container_offline(struct device *dev)</div><div class='ctx'> 	return cdev-&gt;offline ? cdev-&gt;offline(cdev) : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct bus_type container_subsys = {</div><div class='add'>+const struct bus_type container_subsys = {</div><div class='ctx'> 	.name = CONTAINER_BUS_NAME,</div><div class='ctx'> 	.dev_name = CONTAINER_BUS_NAME,</div><div class='ctx'> 	.online = trivial_online,</div><div class='head'>diff --git a/drivers/base/core.c b/drivers/base/core.c<br/>index 67ba592afc77..14d46af40f9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/core.c</a></div><div class='hunk'>@@ -298,7 +298,7 @@ static inline bool device_link_flag_is_sync_state_only(u32 flags)</div><div class='ctx'>  * Check if @target depends on @dev or any device dependent on it (its child or</div><div class='ctx'>  * its consumer etc).  Return 1 if that is the case or 0 otherwise.</div><div class='ctx'>  */</div><div class='del'>-int device_is_dependent(struct device *dev, void *target)</div><div class='add'>+static int device_is_dependent(struct device *dev, void *target)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_link *link;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1641,7 +1641,7 @@ static void device_links_purge(struct device *dev)</div><div class='ctx'> #define FW_DEVLINK_FLAGS_RPM		(FW_DEVLINK_FLAGS_ON | \</div><div class='ctx'> 					 DL_FLAG_PM_RUNTIME)</div><div class='ctx'> </div><div class='del'>-static u32 fw_devlink_flags = FW_DEVLINK_FLAGS_ON;</div><div class='add'>+static u32 fw_devlink_flags = FW_DEVLINK_FLAGS_RPM;</div><div class='ctx'> static int __init fw_devlink_setup(char *arg)</div><div class='ctx'> {</div><div class='ctx'> 	if (!arg)</div><div class='hunk'>@@ -4944,13 +4944,14 @@ define_dev_printk_level(_dev_info, KERN_INFO);</div><div class='ctx'>  *</div><div class='ctx'>  * 	return dev_err_probe(dev, err, ...);</div><div class='ctx'>  *</div><div class='del'>- * Note that it is deemed acceptable to use this function for error</div><div class='del'>- * prints during probe even if the @err is known to never be -EPROBE_DEFER.</div><div class='add'>+ * Using this helper in your probe function is totally fine even if @err is</div><div class='add'>+ * known to never be -EPROBE_DEFER.</div><div class='ctx'>  * The benefit compared to a normal dev_err() is the standardized format</div><div class='del'>- * of the error code and the fact that the error code is returned.</div><div class='add'>+ * of the error code, it being emitted symbolically (i.e. you get "EAGAIN"</div><div class='add'>+ * instead of "-35") and the fact that the error code is returned which allows</div><div class='add'>+ * more compact error paths.</div><div class='ctx'>  *</div><div class='ctx'>  * Returns @err.</div><div class='del'>- *</div><div class='ctx'>  */</div><div class='ctx'> int dev_err_probe(const struct device *dev, int err, const char *fmt, ...)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c<br/>index 9ea22e165acd..47de0f140ba6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/cpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/cpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/cpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/cpu.c</a></div><div class='hunk'>@@ -144,7 +144,7 @@ static DEVICE_ATTR(release, S_IWUSR, NULL, cpu_release_store);</div><div class='ctx'> #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */</div><div class='ctx'> #endif /* CONFIG_HOTPLUG_CPU */</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_KEXEC</div><div class='add'>+#ifdef CONFIG_KEXEC_CORE</div><div class='ctx'> #include &lt;linux/kexec.h&gt;</div><div class='ctx'> </div><div class='ctx'> static ssize_t crash_notes_show(struct device *dev,</div><div class='hunk'>@@ -189,14 +189,14 @@ static const struct attribute_group crash_note_cpu_attr_group = {</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> static const struct attribute_group *common_cpu_attr_groups[] = {</div><div class='del'>-#ifdef CONFIG_KEXEC</div><div class='add'>+#ifdef CONFIG_KEXEC_CORE</div><div class='ctx'> 	&amp;crash_note_cpu_attr_group,</div><div class='ctx'> #endif</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct attribute_group *hotplugable_cpu_attr_groups[] = {</div><div class='del'>-#ifdef CONFIG_KEXEC</div><div class='add'>+#ifdef CONFIG_KEXEC_CORE</div><div class='ctx'> 	&amp;crash_note_cpu_attr_group,</div><div class='ctx'> #endif</div><div class='ctx'> 	NULL</div><div class='hunk'>@@ -525,19 +525,42 @@ bool cpu_is_hotpluggable(unsigned int cpu)</div><div class='ctx'> EXPORT_SYMBOL_GPL(cpu_is_hotpluggable);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_GENERIC_CPU_DEVICES</div><div class='del'>-static DEFINE_PER_CPU(struct cpu, cpu_devices);</div><div class='del'>-#endif</div><div class='add'>+DEFINE_PER_CPU(struct cpu, cpu_devices);</div><div class='add'>+</div><div class='add'>+bool __weak arch_cpu_is_hotpluggable(int cpu)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int __weak arch_register_cpu(int cpu)</div><div class='add'>+{</div><div class='add'>+	struct cpu *c = &amp;per_cpu(cpu_devices, cpu);</div><div class='add'>+</div><div class='add'>+	c-&gt;hotpluggable = arch_cpu_is_hotpluggable(cpu);</div><div class='add'>+</div><div class='add'>+	return register_cpu(c, cpu);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_HOTPLUG_CPU</div><div class='add'>+void __weak arch_unregister_cpu(int num)</div><div class='add'>+{</div><div class='add'>+	unregister_cpu(&amp;per_cpu(cpu_devices, num));</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_HOTPLUG_CPU */</div><div class='add'>+#endif /* CONFIG_GENERIC_CPU_DEVICES */</div><div class='ctx'> </div><div class='ctx'> static void __init cpu_dev_register_generic(void)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_GENERIC_CPU_DEVICES</div><div class='del'>-	int i;</div><div class='add'>+	int i, ret;</div><div class='ctx'> </div><div class='del'>-	for_each_possible_cpu(i) {</div><div class='del'>-		if (register_cpu(&amp;per_cpu(cpu_devices, i), i))</div><div class='del'>-			panic("Failed to register CPU device");</div><div class='add'>+	if (!IS_ENABLED(CONFIG_GENERIC_CPU_DEVICES))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for_each_present_cpu(i) {</div><div class='add'>+		ret = arch_register_cpu(i);</div><div class='add'>+		if (ret)</div><div class='add'>+			pr_warn("register_cpu %d failed (%d)\n", i, ret);</div><div class='ctx'> 	}</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_GENERIC_CPU_VULNERABILITIES</div><div class='head'>diff --git a/drivers/base/dd.c b/drivers/base/dd.c<br/>index 0c3725c3eefa..85152537dbf1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/dd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/dd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/dd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/dd.c</a></div><div class='hunk'>@@ -313,7 +313,7 @@ static void deferred_probe_timeout_work_func(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;deferred_probe_mutex);</div><div class='ctx'> 	list_for_each_entry(p, &amp;deferred_probe_pending_list, deferred_probe)</div><div class='del'>-		dev_info(p-&gt;device, "deferred probe pending\n");</div><div class='add'>+		dev_info(p-&gt;device, "deferred probe pending: %s", p-&gt;deferred_probe_reason ?: "(reason unknown)\n");</div><div class='ctx'> 	mutex_unlock(&amp;deferred_probe_mutex);</div><div class='ctx'> </div><div class='ctx'> 	fw_devlink_probing_done();</div><div class='head'>diff --git a/drivers/base/devcoredump.c b/drivers/base/devcoredump.c<br/>index 91536ee05f14..7e2d1f0d903a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/devcoredump.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/devcoredump.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/devcoredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/devcoredump.c</a></div><div class='hunk'>@@ -362,6 +362,7 @@ void dev_coredumpm(struct device *dev, struct module *owner,</div><div class='ctx'> 	devcd-&gt;devcd_dev.class = &amp;devcd_class;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;devcd-&gt;mutex);</div><div class='add'>+	dev_set_uevent_suppress(&amp;devcd-&gt;devcd_dev, true);</div><div class='ctx'> 	if (device_add(&amp;devcd-&gt;devcd_dev))</div><div class='ctx'> 		goto put_device;</div><div class='ctx'> </div><div class='hunk'>@@ -376,6 +377,8 @@ void dev_coredumpm(struct device *dev, struct module *owner,</div><div class='ctx'> 		              "devcoredump"))</div><div class='ctx'> 		dev_warn(dev, "devcoredump create_link failed\n");</div><div class='ctx'> </div><div class='add'>+	dev_set_uevent_suppress(&amp;devcd-&gt;devcd_dev, false);</div><div class='add'>+	kobject_uevent(&amp;devcd-&gt;devcd_dev.kobj, KOBJ_ADD);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;devcd-&gt;del_wk, devcd_del);</div><div class='ctx'> 	schedule_delayed_work(&amp;devcd-&gt;del_wk, DEVCD_TIMEOUT);</div><div class='ctx'> 	mutex_unlock(&amp;devcd-&gt;mutex);</div><div class='head'>diff --git a/drivers/base/firmware_loader/sysfs_upload.c b/drivers/base/firmware_loader/sysfs_upload.c<br/>index a0af8f5f13d8..829270067d16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/firmware_loader/sysfs_upload.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/firmware_loader/sysfs_upload.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/firmware_loader/sysfs_upload.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/firmware_loader/sysfs_upload.c</a></div><div class='hunk'>@@ -27,6 +27,7 @@ static const char * const fw_upload_err_str[] = {</div><div class='ctx'> 	[FW_UPLOAD_ERR_INVALID_SIZE] = "invalid-file-size",</div><div class='ctx'> 	[FW_UPLOAD_ERR_RW_ERROR]     = "read-write-error",</div><div class='ctx'> 	[FW_UPLOAD_ERR_WEAROUT]	     = "flash-wearout",</div><div class='add'>+	[FW_UPLOAD_ERR_FW_INVALID]   = "firmware-invalid",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const char *fw_upload_progress(struct device *dev,</div><div class='head'>diff --git a/drivers/base/init.c b/drivers/base/init.c<br/>index 397eb9880cec..c4954835128c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/init.c</a></div><div class='hunk'>@@ -35,8 +35,8 @@ void __init driver_init(void)</div><div class='ctx'> 	of_core_init();</div><div class='ctx'> 	platform_bus_init();</div><div class='ctx'> 	auxiliary_bus_init();</div><div class='del'>-	cpu_dev_init();</div><div class='ctx'> 	memory_dev_init();</div><div class='ctx'> 	node_dev_init();</div><div class='add'>+	cpu_dev_init();</div><div class='ctx'> 	container_dev_init();</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/base/isa.c b/drivers/base/isa.c<br/>index 675ad3139224..e23d0b49a793 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/isa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/isa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/isa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/isa.c</a></div><div class='hunk'>@@ -82,7 +82,7 @@ static int isa_bus_resume(struct device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct bus_type isa_bus_type = {</div><div class='add'>+static const struct bus_type isa_bus_type = {</div><div class='ctx'> 	.name		= "isa",</div><div class='ctx'> 	.match		= isa_bus_match,</div><div class='ctx'> 	.probe		= isa_bus_probe,</div><div class='head'>diff --git a/drivers/base/memory.c b/drivers/base/memory.c<br/>index f3b9a4d0fa3b..14f964a7719b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/memory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/memory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/memory.c</a></div><div class='hunk'>@@ -68,7 +68,7 @@ static inline unsigned long phys_to_block_id(unsigned long phys)</div><div class='ctx'> static int memory_subsys_online(struct device *dev);</div><div class='ctx'> static int memory_subsys_offline(struct device *dev);</div><div class='ctx'> </div><div class='del'>-static struct bus_type memory_subsys = {</div><div class='add'>+static const struct bus_type memory_subsys = {</div><div class='ctx'> 	.name = MEMORY_CLASS_NAME,</div><div class='ctx'> 	.dev_name = MEMORY_CLASS_NAME,</div><div class='ctx'> 	.online = memory_subsys_online,</div><div class='hunk'>@@ -180,6 +180,9 @@ static inline unsigned long memblk_nr_poison(struct memory_block *mem)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Must acquire mem_hotplug_lock in write mode.</div><div class='add'>+ */</div><div class='ctx'> static int memory_block_online(struct memory_block *mem)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long start_pfn = section_nr_to_pfn(mem-&gt;start_section_nr);</div><div class='hunk'>@@ -204,10 +207,11 @@ static int memory_block_online(struct memory_block *mem)</div><div class='ctx'> 	if (mem-&gt;altmap)</div><div class='ctx'> 		nr_vmemmap_pages = mem-&gt;altmap-&gt;free;</div><div class='ctx'> </div><div class='add'>+	mem_hotplug_begin();</div><div class='ctx'> 	if (nr_vmemmap_pages) {</div><div class='ctx'> 		ret = mhp_init_memmap_on_memory(start_pfn, nr_vmemmap_pages, zone);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = online_pages(start_pfn + nr_vmemmap_pages,</div><div class='hunk'>@@ -215,7 +219,7 @@ static int memory_block_online(struct memory_block *mem)</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		if (nr_vmemmap_pages)</div><div class='ctx'> 			mhp_deinit_memmap_on_memory(start_pfn, nr_vmemmap_pages);</div><div class='del'>-		return ret;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -227,9 +231,14 @@ static int memory_block_online(struct memory_block *mem)</div><div class='ctx'> 					  nr_vmemmap_pages);</div><div class='ctx'> </div><div class='ctx'> 	mem-&gt;zone = zone;</div><div class='add'>+out:</div><div class='add'>+	mem_hotplug_done();</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Must acquire mem_hotplug_lock in write mode.</div><div class='add'>+ */</div><div class='ctx'> static int memory_block_offline(struct memory_block *mem)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long start_pfn = section_nr_to_pfn(mem-&gt;start_section_nr);</div><div class='hunk'>@@ -247,6 +256,7 @@ static int memory_block_offline(struct memory_block *mem)</div><div class='ctx'> 	if (mem-&gt;altmap)</div><div class='ctx'> 		nr_vmemmap_pages = mem-&gt;altmap-&gt;free;</div><div class='ctx'> </div><div class='add'>+	mem_hotplug_begin();</div><div class='ctx'> 	if (nr_vmemmap_pages)</div><div class='ctx'> 		adjust_present_page_count(pfn_to_page(start_pfn), mem-&gt;group,</div><div class='ctx'> 					  -nr_vmemmap_pages);</div><div class='hunk'>@@ -258,13 +268,15 @@ static int memory_block_offline(struct memory_block *mem)</div><div class='ctx'> 		if (nr_vmemmap_pages)</div><div class='ctx'> 			adjust_present_page_count(pfn_to_page(start_pfn),</div><div class='ctx'> 						  mem-&gt;group, nr_vmemmap_pages);</div><div class='del'>-		return ret;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (nr_vmemmap_pages)</div><div class='ctx'> 		mhp_deinit_memmap_on_memory(start_pfn, nr_vmemmap_pages);</div><div class='ctx'> </div><div class='ctx'> 	mem-&gt;zone = NULL;</div><div class='add'>+out:</div><div class='add'>+	mem_hotplug_done();</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/base/node.c b/drivers/base/node.c<br/>index 493d533f8375..1c05640461dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/node.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/node.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/node.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/node.c</a></div><div class='hunk'>@@ -21,7 +21,7 @@</div><div class='ctx'> #include &lt;linux/swap.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='del'>-static struct bus_type node_subsys = {</div><div class='add'>+static const struct bus_type node_subsys = {</div><div class='ctx'> 	.name = "node",</div><div class='ctx'> 	.dev_name = "node",</div><div class='ctx'> };</div><div class='hunk'>@@ -74,14 +74,14 @@ static BIN_ATTR_RO(cpulist, CPULIST_FILE_MAX_BYTES);</div><div class='ctx'>  * @dev:	Device for this memory access class</div><div class='ctx'>  * @list_node:	List element in the node's access list</div><div class='ctx'>  * @access:	The access class rank</div><div class='del'>- * @hmem_attrs: Heterogeneous memory performance attributes</div><div class='add'>+ * @coord:	Heterogeneous memory performance coordinates</div><div class='ctx'>  */</div><div class='ctx'> struct node_access_nodes {</div><div class='ctx'> 	struct device		dev;</div><div class='ctx'> 	struct list_head	list_node;</div><div class='ctx'> 	unsigned int		access;</div><div class='ctx'> #ifdef CONFIG_HMEM_REPORTING</div><div class='del'>-	struct node_hmem_attrs	hmem_attrs;</div><div class='add'>+	struct access_coordinate	coord;</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> #define to_access_nodes(dev) container_of(dev, struct node_access_nodes, dev)</div><div class='hunk'>@@ -167,7 +167,7 @@ static ssize_t property##_show(struct device *dev,			\</div><div class='ctx'> 			   char *buf)					\</div><div class='ctx'> {									\</div><div class='ctx'> 	return sysfs_emit(buf, "%u\n",					\</div><div class='del'>-			  to_access_nodes(dev)-&gt;hmem_attrs.property);	\</div><div class='add'>+			  to_access_nodes(dev)-&gt;coord.property);	\</div><div class='ctx'> }									\</div><div class='ctx'> static DEVICE_ATTR_RO(property)</div><div class='ctx'> </div><div class='hunk'>@@ -187,10 +187,10 @@ static struct attribute *access_attrs[] = {</div><div class='ctx'> /**</div><div class='ctx'>  * node_set_perf_attrs - Set the performance values for given access class</div><div class='ctx'>  * @nid: Node identifier to be set</div><div class='del'>- * @hmem_attrs: Heterogeneous memory performance attributes</div><div class='add'>+ * @coord: Heterogeneous memory performance coordinates</div><div class='ctx'>  * @access: The access class the for the given attributes</div><div class='ctx'>  */</div><div class='del'>-void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,</div><div class='add'>+void node_set_perf_attrs(unsigned int nid, struct access_coordinate *coord,</div><div class='ctx'> 			 unsigned int access)</div><div class='ctx'> {</div><div class='ctx'> 	struct node_access_nodes *c;</div><div class='hunk'>@@ -205,7 +205,7 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	c-&gt;hmem_attrs = *hmem_attrs;</div><div class='add'>+	c-&gt;coord = *coord;</div><div class='ctx'> 	for (i = 0; access_attrs[i] != NULL; i++) {</div><div class='ctx'> 		if (sysfs_add_file_to_group(&amp;c-&gt;dev.kobj, access_attrs[i],</div><div class='ctx'> 					    "initiators")) {</div><div class='hunk'>@@ -868,11 +868,15 @@ int __register_one_node(int nid)</div><div class='ctx'> {</div><div class='ctx'> 	int error;</div><div class='ctx'> 	int cpu;</div><div class='add'>+	struct node *node;</div><div class='ctx'> </div><div class='del'>-	node_devices[nid] = kzalloc(sizeof(struct node), GFP_KERNEL);</div><div class='del'>-	if (!node_devices[nid])</div><div class='add'>+	node = kzalloc(sizeof(struct node), GFP_KERNEL);</div><div class='add'>+	if (!node)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	INIT_LIST_HEAD(&amp;node-&gt;access_list);</div><div class='add'>+	node_devices[nid] = node;</div><div class='add'>+</div><div class='ctx'> 	error = register_node(node_devices[nid], nid);</div><div class='ctx'> </div><div class='ctx'> 	/* link cpu under this node */</div><div class='hunk'>@@ -881,7 +885,6 @@ int __register_one_node(int nid)</div><div class='ctx'> 			register_cpu_under_node(cpu, nid);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	INIT_LIST_HEAD(&amp;node_devices[nid]-&gt;access_list);</div><div class='ctx'> 	node_init_caches(nid);</div><div class='ctx'> </div><div class='ctx'> 	return error;</div><div class='head'>diff --git a/drivers/base/power/Makefile b/drivers/base/power/Makefile<br/>index 8fdd0073eeeb..01f11629d241 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/Makefile</a></div><div class='hunk'>@@ -2,7 +2,6 @@</div><div class='ctx'> obj-$(CONFIG_PM)	+= sysfs.o generic_ops.o common.o qos.o runtime.o wakeirq.o</div><div class='ctx'> obj-$(CONFIG_PM_SLEEP)	+= main.o wakeup.o wakeup_stats.o</div><div class='ctx'> obj-$(CONFIG_PM_TRACE_RTC)	+= trace.o</div><div class='del'>-obj-$(CONFIG_PM_GENERIC_DOMAINS)	+=  domain.o domain_governor.o</div><div class='ctx'> obj-$(CONFIG_HAVE_CLK)	+= clock_ops.o</div><div class='ctx'> obj-$(CONFIG_PM_QOS_KUNIT_TEST) += qos-test.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/base/power/clock_ops.c b/drivers/base/power/clock_ops.c<br/>index 4110c19c08dc..e18ba676cdf6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/clock_ops.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/clock_ops.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/clock_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/clock_ops.c</a></div><div class='hunk'>@@ -793,7 +793,7 @@ static int pm_clk_notify(struct notifier_block *nb,</div><div class='ctx'>  * the remaining members of @clknb should be populated prior to calling this</div><div class='ctx'>  * routine.</div><div class='ctx'>  */</div><div class='del'>-void pm_clk_add_notifier(struct bus_type *bus,</div><div class='add'>+void pm_clk_add_notifier(const struct bus_type *bus,</div><div class='ctx'> 				 struct pm_clk_notifier_block *clknb)</div><div class='ctx'> {</div><div class='ctx'> 	if (!bus || !clknb)</div><div class='head'>diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c<br/>index f85f3515c258..fadcd0379dc2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/main.c</a></div><div class='hunk'>@@ -587,7 +587,7 @@ bool dev_pm_skip_resume(struct device *dev)</div><div class='ctx'>  * The driver of @dev will not receive interrupts while this function is being</div><div class='ctx'>  * executed.</div><div class='ctx'>  */</div><div class='del'>-static int device_resume_noirq(struct device *dev, pm_message_t state, bool async)</div><div class='add'>+static void device_resume_noirq(struct device *dev, pm_message_t state, bool async)</div><div class='ctx'> {</div><div class='ctx'> 	pm_callback_t callback = NULL;</div><div class='ctx'> 	const char *info = NULL;</div><div class='hunk'>@@ -655,7 +655,13 @@ Skip:</div><div class='ctx'> Out:</div><div class='ctx'> 	complete_all(&amp;dev-&gt;power.completion);</div><div class='ctx'> 	TRACE_RESUME(error);</div><div class='del'>-	return error;</div><div class='add'>+</div><div class='add'>+	if (error) {</div><div class='add'>+		suspend_stats.failed_resume_noirq++;</div><div class='add'>+		dpm_save_failed_step(SUSPEND_RESUME_NOIRQ);</div><div class='add'>+		dpm_save_failed_dev(dev_name(dev));</div><div class='add'>+		pm_dev_err(dev, state, async ? " async noirq" : " noirq", error);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool is_async(struct device *dev)</div><div class='hunk'>@@ -669,23 +675,29 @@ static bool dpm_async_fn(struct device *dev, async_func_t func)</div><div class='ctx'> 	reinit_completion(&amp;dev-&gt;power.completion);</div><div class='ctx'> </div><div class='ctx'> 	if (is_async(dev)) {</div><div class='add'>+		dev-&gt;power.async_in_progress = true;</div><div class='add'>+</div><div class='ctx'> 		get_device(dev);</div><div class='del'>-		async_schedule_dev(func, dev);</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='add'>+		if (async_schedule_dev_nocall(func, dev))</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+		put_device(dev);</div><div class='add'>+	}</div><div class='add'>+	/*</div><div class='add'>+	 * Because async_schedule_dev_nocall() above has returned false or it</div><div class='add'>+	 * has not been called at all, func() is not running and it is safe to</div><div class='add'>+	 * update the async_in_progress flag without extra synchronization.</div><div class='add'>+	 */</div><div class='add'>+	dev-&gt;power.async_in_progress = false;</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void async_resume_noirq(void *data, async_cookie_t cookie)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = data;</div><div class='del'>-	int error;</div><div class='del'>-</div><div class='del'>-	error = device_resume_noirq(dev, pm_transition, true);</div><div class='del'>-	if (error)</div><div class='del'>-		pm_dev_err(dev, pm_transition, " async", error);</div><div class='ctx'> </div><div class='add'>+	device_resume_noirq(dev, pm_transition, true);</div><div class='ctx'> 	put_device(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -699,35 +711,27 @@ static void dpm_noirq_resume_devices(pm_message_t state)</div><div class='ctx'> 	pm_transition = state;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Advanced the async threads upfront,</div><div class='del'>-	 * in case the starting of async threads is</div><div class='del'>-	 * delayed by non-async resuming devices.</div><div class='add'>+	 * Trigger the resume of "async" devices upfront so they don't have to</div><div class='add'>+	 * wait for the "non-async" ones they don't depend on.</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(dev, &amp;dpm_noirq_list, power.entry)</div><div class='ctx'> 		dpm_async_fn(dev, async_resume_noirq);</div><div class='ctx'> </div><div class='ctx'> 	while (!list_empty(&amp;dpm_noirq_list)) {</div><div class='ctx'> 		dev = to_device(dpm_noirq_list.next);</div><div class='del'>-		get_device(dev);</div><div class='ctx'> 		list_move_tail(&amp;dev-&gt;power.entry, &amp;dpm_late_early_list);</div><div class='ctx'> </div><div class='del'>-		mutex_unlock(&amp;dpm_list_mtx);</div><div class='add'>+		if (!dev-&gt;power.async_in_progress) {</div><div class='add'>+			get_device(dev);</div><div class='ctx'> </div><div class='del'>-		if (!is_async(dev)) {</div><div class='del'>-			int error;</div><div class='add'>+			mutex_unlock(&amp;dpm_list_mtx);</div><div class='ctx'> </div><div class='del'>-			error = device_resume_noirq(dev, state, false);</div><div class='del'>-			if (error) {</div><div class='del'>-				suspend_stats.failed_resume_noirq++;</div><div class='del'>-				dpm_save_failed_step(SUSPEND_RESUME_NOIRQ);</div><div class='del'>-				dpm_save_failed_dev(dev_name(dev));</div><div class='del'>-				pm_dev_err(dev, state, " noirq", error);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+			device_resume_noirq(dev, state, false);</div><div class='ctx'> </div><div class='del'>-		put_device(dev);</div><div class='add'>+			put_device(dev);</div><div class='ctx'> </div><div class='del'>-		mutex_lock(&amp;dpm_list_mtx);</div><div class='add'>+			mutex_lock(&amp;dpm_list_mtx);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;dpm_list_mtx);</div><div class='ctx'> 	async_synchronize_full();</div><div class='hunk'>@@ -758,7 +762,7 @@ void dpm_resume_noirq(pm_message_t state)</div><div class='ctx'>  *</div><div class='ctx'>  * Runtime PM is disabled for @dev while this function is being executed.</div><div class='ctx'>  */</div><div class='del'>-static int device_resume_early(struct device *dev, pm_message_t state, bool async)</div><div class='add'>+static void device_resume_early(struct device *dev, pm_message_t state, bool async)</div><div class='ctx'> {</div><div class='ctx'> 	pm_callback_t callback = NULL;</div><div class='ctx'> 	const char *info = NULL;</div><div class='hunk'>@@ -811,18 +815,20 @@ Out:</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_enable(dev);</div><div class='ctx'> 	complete_all(&amp;dev-&gt;power.completion);</div><div class='del'>-	return error;</div><div class='add'>+</div><div class='add'>+	if (error) {</div><div class='add'>+		suspend_stats.failed_resume_early++;</div><div class='add'>+		dpm_save_failed_step(SUSPEND_RESUME_EARLY);</div><div class='add'>+		dpm_save_failed_dev(dev_name(dev));</div><div class='add'>+		pm_dev_err(dev, state, async ? " async early" : " early", error);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void async_resume_early(void *data, async_cookie_t cookie)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = data;</div><div class='del'>-	int error;</div><div class='del'>-</div><div class='del'>-	error = device_resume_early(dev, pm_transition, true);</div><div class='del'>-	if (error)</div><div class='del'>-		pm_dev_err(dev, pm_transition, " async", error);</div><div class='ctx'> </div><div class='add'>+	device_resume_early(dev, pm_transition, true);</div><div class='ctx'> 	put_device(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -840,35 +846,27 @@ void dpm_resume_early(pm_message_t state)</div><div class='ctx'> 	pm_transition = state;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Advanced the async threads upfront,</div><div class='del'>-	 * in case the starting of async threads is</div><div class='del'>-	 * delayed by non-async resuming devices.</div><div class='add'>+	 * Trigger the resume of "async" devices upfront so they don't have to</div><div class='add'>+	 * wait for the "non-async" ones they don't depend on.</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(dev, &amp;dpm_late_early_list, power.entry)</div><div class='ctx'> 		dpm_async_fn(dev, async_resume_early);</div><div class='ctx'> </div><div class='ctx'> 	while (!list_empty(&amp;dpm_late_early_list)) {</div><div class='ctx'> 		dev = to_device(dpm_late_early_list.next);</div><div class='del'>-		get_device(dev);</div><div class='ctx'> 		list_move_tail(&amp;dev-&gt;power.entry, &amp;dpm_suspended_list);</div><div class='ctx'> </div><div class='del'>-		mutex_unlock(&amp;dpm_list_mtx);</div><div class='add'>+		if (!dev-&gt;power.async_in_progress) {</div><div class='add'>+			get_device(dev);</div><div class='ctx'> </div><div class='del'>-		if (!is_async(dev)) {</div><div class='del'>-			int error;</div><div class='add'>+			mutex_unlock(&amp;dpm_list_mtx);</div><div class='ctx'> </div><div class='del'>-			error = device_resume_early(dev, state, false);</div><div class='del'>-			if (error) {</div><div class='del'>-				suspend_stats.failed_resume_early++;</div><div class='del'>-				dpm_save_failed_step(SUSPEND_RESUME_EARLY);</div><div class='del'>-				dpm_save_failed_dev(dev_name(dev));</div><div class='del'>-				pm_dev_err(dev, state, " early", error);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+			device_resume_early(dev, state, false);</div><div class='ctx'> </div><div class='del'>-		put_device(dev);</div><div class='add'>+			put_device(dev);</div><div class='ctx'> </div><div class='del'>-		mutex_lock(&amp;dpm_list_mtx);</div><div class='add'>+			mutex_lock(&amp;dpm_list_mtx);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;dpm_list_mtx);</div><div class='ctx'> 	async_synchronize_full();</div><div class='hunk'>@@ -893,7 +891,7 @@ EXPORT_SYMBOL_GPL(dpm_resume_start);</div><div class='ctx'>  * @state: PM transition of the system being carried out.</div><div class='ctx'>  * @async: If true, the device is being resumed asynchronously.</div><div class='ctx'>  */</div><div class='del'>-static int device_resume(struct device *dev, pm_message_t state, bool async)</div><div class='add'>+static void device_resume(struct device *dev, pm_message_t state, bool async)</div><div class='ctx'> {</div><div class='ctx'> 	pm_callback_t callback = NULL;</div><div class='ctx'> 	const char *info = NULL;</div><div class='hunk'>@@ -975,17 +973,19 @@ static int device_resume(struct device *dev, pm_message_t state, bool async)</div><div class='ctx'> </div><div class='ctx'> 	TRACE_RESUME(error);</div><div class='ctx'> </div><div class='del'>-	return error;</div><div class='add'>+	if (error) {</div><div class='add'>+		suspend_stats.failed_resume++;</div><div class='add'>+		dpm_save_failed_step(SUSPEND_RESUME);</div><div class='add'>+		dpm_save_failed_dev(dev_name(dev));</div><div class='add'>+		pm_dev_err(dev, state, async ? " async" : "", error);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void async_resume(void *data, async_cookie_t cookie)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = data;</div><div class='del'>-	int error;</div><div class='ctx'> </div><div class='del'>-	error = device_resume(dev, pm_transition, true);</div><div class='del'>-	if (error)</div><div class='del'>-		pm_dev_err(dev, pm_transition, " async", error);</div><div class='add'>+	device_resume(dev, pm_transition, true);</div><div class='ctx'> 	put_device(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1008,27 +1008,26 @@ void dpm_resume(pm_message_t state)</div><div class='ctx'> 	pm_transition = state;</div><div class='ctx'> 	async_error = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Trigger the resume of "async" devices upfront so they don't have to</div><div class='add'>+	 * wait for the "non-async" ones they don't depend on.</div><div class='add'>+	 */</div><div class='ctx'> 	list_for_each_entry(dev, &amp;dpm_suspended_list, power.entry)</div><div class='ctx'> 		dpm_async_fn(dev, async_resume);</div><div class='ctx'> </div><div class='ctx'> 	while (!list_empty(&amp;dpm_suspended_list)) {</div><div class='ctx'> 		dev = to_device(dpm_suspended_list.next);</div><div class='add'>+</div><div class='ctx'> 		get_device(dev);</div><div class='del'>-		if (!is_async(dev)) {</div><div class='del'>-			int error;</div><div class='ctx'> </div><div class='add'>+		if (!dev-&gt;power.async_in_progress) {</div><div class='ctx'> 			mutex_unlock(&amp;dpm_list_mtx);</div><div class='ctx'> </div><div class='del'>-			error = device_resume(dev, state, false);</div><div class='del'>-			if (error) {</div><div class='del'>-				suspend_stats.failed_resume++;</div><div class='del'>-				dpm_save_failed_step(SUSPEND_RESUME);</div><div class='del'>-				dpm_save_failed_dev(dev_name(dev));</div><div class='del'>-				pm_dev_err(dev, state, "", error);</div><div class='del'>-			}</div><div class='add'>+			device_resume(dev, state, false);</div><div class='ctx'> </div><div class='ctx'> 			mutex_lock(&amp;dpm_list_mtx);</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='ctx'> 		if (!list_empty(&amp;dev-&gt;power.entry))</div><div class='ctx'> 			list_move_tail(&amp;dev-&gt;power.entry, &amp;dpm_prepared_list);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c<br/>index 8e93167f1783..bd77f6734f14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/qos.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/qos.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/qos.c</a></div><div class='hunk'>@@ -201,7 +201,7 @@ static int dev_pm_qos_constraints_allocate(struct device *dev)</div><div class='ctx'> 	if (!qos)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	n = kzalloc(3 * sizeof(*n), GFP_KERNEL);</div><div class='add'>+	n = kcalloc(3, sizeof(*n), GFP_KERNEL);</div><div class='ctx'> 	if (!n) {</div><div class='ctx'> 		kfree(qos);</div><div class='ctx'> 		return -ENOMEM;</div><div class='head'>diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c<br/>index 4545669cb973..05793c9fbb84 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/runtime.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/runtime.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/runtime.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/runtime.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/pm_wakeirq.h&gt;</div><div class='add'>+#include &lt;linux/rculist.h&gt;</div><div class='ctx'> #include &lt;trace/events/rpm.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "../base.h"</div><div class='head'>diff --git a/drivers/base/power/trace.c b/drivers/base/power/trace.c<br/>index 72b7a92337b1..cd6e559648b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/power/trace.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/power/trace.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/power/trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/power/trace.c</a></div><div class='hunk'>@@ -120,7 +120,7 @@ static unsigned int read_magic_time(void)</div><div class='ctx'> 	struct rtc_time time;</div><div class='ctx'> 	unsigned int val;</div><div class='ctx'> </div><div class='del'>-	if (mc146818_get_time(&amp;time) &lt; 0) {</div><div class='add'>+	if (mc146818_get_time(&amp;time, 1000) &lt; 0) {</div><div class='ctx'> 		pr_err("Unable to read current time from RTC\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/base/property.c b/drivers/base/property.c<br/>index 8c40abed7852..a1b01ab42052 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/property.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/property.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/property.c</a></div><div class='hunk'>@@ -473,7 +473,7 @@ int fwnode_property_match_string(const struct fwnode_handle *fwnode,</div><div class='ctx'> 	const char **values;</div><div class='ctx'> 	int nval, ret;</div><div class='ctx'> </div><div class='del'>-	nval = fwnode_property_read_string_array(fwnode, propname, NULL, 0);</div><div class='add'>+	nval = fwnode_property_string_array_count(fwnode, propname);</div><div class='ctx'> 	if (nval &lt; 0)</div><div class='ctx'> 		return nval;</div><div class='ctx'> </div><div class='hunk'>@@ -499,6 +499,41 @@ out_free:</div><div class='ctx'> EXPORT_SYMBOL_GPL(fwnode_property_match_string);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * fwnode_property_match_property_string - find a property string value in an array and return index</div><div class='add'>+ * @fwnode: Firmware node to get the property of</div><div class='add'>+ * @propname: Name of the property holding the string value</div><div class='add'>+ * @array: String array to search in</div><div class='add'>+ * @n: Size of the @array</div><div class='add'>+ *</div><div class='add'>+ * Find a property string value in a given @array and if it is found return</div><div class='add'>+ * the index back.</div><div class='add'>+ *</div><div class='add'>+ * Return: index, starting from %0, if the string value was found in the @array (success),</div><div class='add'>+ *	   %-ENOENT when the string value was not found in the @array,</div><div class='add'>+ *	   %-EINVAL if given arguments are not valid,</div><div class='add'>+ *	   %-ENODATA if the property does not have a value,</div><div class='add'>+ *	   %-EPROTO or %-EILSEQ if the property is not a string,</div><div class='add'>+ *	   %-ENXIO if no suitable firmware interface is present.</div><div class='add'>+ */</div><div class='add'>+int fwnode_property_match_property_string(const struct fwnode_handle *fwnode,</div><div class='add'>+	const char *propname, const char * const *array, size_t n)</div><div class='add'>+{</div><div class='add'>+	const char *string;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_read_string(fwnode, propname, &amp;string);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = match_string(array, n, string);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		ret = -ENOENT;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(fwnode_property_match_property_string);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * fwnode_property_get_reference_args() - Find a reference with arguments</div><div class='ctx'>  * @fwnode:	Firmware node where to look for the reference</div><div class='ctx'>  * @prop:	The name of the property</div><div class='hunk'>@@ -508,6 +543,7 @@ EXPORT_SYMBOL_GPL(fwnode_property_match_string);</div><div class='ctx'>  * @nargs:	Number of arguments. Ignored if @nargs_prop is non-NULL.</div><div class='ctx'>  * @index:	Index of the reference, from zero onwards.</div><div class='ctx'>  * @args:	Result structure with reference and integer arguments.</div><div class='add'>+ *		May be NULL.</div><div class='ctx'>  *</div><div class='ctx'>  * Obtain a reference based on a named property in an fwnode, with</div><div class='ctx'>  * integer arguments.</div><div class='hunk'>@@ -595,6 +631,34 @@ const char *fwnode_get_name_prefix(const struct fwnode_handle *fwnode)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * fwnode_name_eq - Return true if node name is equal</div><div class='add'>+ * @fwnode: The firmware node</div><div class='add'>+ * @name: The name to which to compare the node name</div><div class='add'>+ *</div><div class='add'>+ * Compare the name provided as an argument to the name of the node, stopping</div><div class='add'>+ * the comparison at either NUL or '@' character, whichever comes first. This</div><div class='add'>+ * function is generally used for comparing node names while ignoring the</div><div class='add'>+ * possible unit address of the node.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the node name matches with the name provided in the @name</div><div class='add'>+ * argument, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool fwnode_name_eq(const struct fwnode_handle *fwnode, const char *name)</div><div class='add'>+{</div><div class='add'>+	const char *node_name;</div><div class='add'>+	ptrdiff_t len;</div><div class='add'>+</div><div class='add'>+	node_name = fwnode_get_name(fwnode);</div><div class='add'>+	if (!node_name)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	len = strchrnul(node_name, '@') - node_name;</div><div class='add'>+</div><div class='add'>+	return str_has_prefix(node_name, name) == len;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(fwnode_name_eq);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * fwnode_get_parent - Return parent firwmare node</div><div class='ctx'>  * @fwnode: Firmware whose parent is retrieved</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h<br/>index 9a9ea514c2d8..583dd5d7d46b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/internal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/internal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/internal.h</a></div><div class='hunk'>@@ -318,6 +318,7 @@ struct regmap_ram_data {</div><div class='ctx'> 	bool *read;</div><div class='ctx'> 	bool *written;</div><div class='ctx'> 	enum regmap_endian reg_endian;</div><div class='add'>+	bool (*noinc_reg)(struct regmap_ram_data *data, unsigned int reg);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c<br/>index 92592f944a3d..ac63a73ccdaa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regcache.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regcache.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regcache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regcache.c</a></div><div class='hunk'>@@ -410,8 +410,7 @@ out:</div><div class='ctx'> 			rb_entry(node, struct regmap_range_node, node);</div><div class='ctx'> </div><div class='ctx'> 		/* If there's nothing in the cache there's nothing to sync */</div><div class='del'>-		ret = regcache_read(map, this-&gt;selector_reg, &amp;i);</div><div class='del'>-		if (ret != 0)</div><div class='add'>+		if (regcache_read(map, this-&gt;selector_reg, &amp;i) != 0)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		ret = _regmap_write(map, this-&gt;selector_reg, i);</div><div class='head'>diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c<br/>index bdd80b73c3e6..fb84cda92a75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regmap-debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-debugfs.c</a></div><div class='hunk'>@@ -226,8 +226,8 @@ static ssize_t regmap_read_debugfs(struct regmap *map, unsigned int from,</div><div class='ctx'> 	if (*ppos &lt; 0 || !count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (count &gt; (PAGE_SIZE &lt;&lt; MAX_ORDER))</div><div class='del'>-		count = PAGE_SIZE &lt;&lt; MAX_ORDER;</div><div class='add'>+	if (count &gt; (PAGE_SIZE &lt;&lt; MAX_PAGE_ORDER))</div><div class='add'>+		count = PAGE_SIZE &lt;&lt; MAX_PAGE_ORDER;</div><div class='ctx'> </div><div class='ctx'> 	buf = kmalloc(count, GFP_KERNEL);</div><div class='ctx'> 	if (!buf)</div><div class='hunk'>@@ -373,8 +373,8 @@ static ssize_t regmap_reg_ranges_read_file(struct file *file,</div><div class='ctx'> 	if (*ppos &lt; 0 || !count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (count &gt; (PAGE_SIZE &lt;&lt; MAX_ORDER))</div><div class='del'>-		count = PAGE_SIZE &lt;&lt; MAX_ORDER;</div><div class='add'>+	if (count &gt; (PAGE_SIZE &lt;&lt; MAX_PAGE_ORDER))</div><div class='add'>+		count = PAGE_SIZE &lt;&lt; MAX_PAGE_ORDER;</div><div class='ctx'> </div><div class='ctx'> 	buf = kmalloc(count, GFP_KERNEL);</div><div class='ctx'> 	if (!buf)</div><div class='head'>diff --git a/drivers/base/regmap/regmap-kunit.c b/drivers/base/regmap/regmap-kunit.c<br/>index e14cc03a17f6..026bdcb45127 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-kunit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regmap-kunit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-kunit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-kunit.c</a></div><div class='hunk'>@@ -1186,6 +1186,65 @@ static void raw_write(struct kunit *test)</div><div class='ctx'> 	regmap_exit(map);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool reg_zero(struct device *dev, unsigned int reg)</div><div class='add'>+{</div><div class='add'>+	return reg == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool ram_reg_zero(struct regmap_ram_data *data, unsigned int reg)</div><div class='add'>+{</div><div class='add'>+	return reg == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void raw_noinc_write(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct raw_test_types *t = (struct raw_test_types *)test-&gt;param_value;</div><div class='add'>+	struct regmap *map;</div><div class='add'>+	struct regmap_config config;</div><div class='add'>+	struct regmap_ram_data *data;</div><div class='add'>+	unsigned int val, val_test, val_last;</div><div class='add'>+	u16 val_array[BLOCK_TEST_SIZE];</div><div class='add'>+</div><div class='add'>+	config = raw_regmap_config;</div><div class='add'>+	config.volatile_reg = reg_zero;</div><div class='add'>+	config.writeable_noinc_reg = reg_zero;</div><div class='add'>+	config.readable_noinc_reg = reg_zero;</div><div class='add'>+</div><div class='add'>+	map = gen_raw_regmap(&amp;config, t, &amp;data);</div><div class='add'>+	KUNIT_ASSERT_FALSE(test, IS_ERR(map));</div><div class='add'>+	if (IS_ERR(map))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	data-&gt;noinc_reg = ram_reg_zero;</div><div class='add'>+</div><div class='add'>+	get_random_bytes(&amp;val_array, sizeof(val_array));</div><div class='add'>+</div><div class='add'>+	if (config.val_format_endian == REGMAP_ENDIAN_BIG) {</div><div class='add'>+		val_test = be16_to_cpu(val_array[1]) + 100;</div><div class='add'>+		val_last = be16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]);</div><div class='add'>+	} else {</div><div class='add'>+		val_test = le16_to_cpu(val_array[1]) + 100;</div><div class='add'>+		val_last = le16_to_cpu(val_array[BLOCK_TEST_SIZE - 1]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Put some data into the register following the noinc register */</div><div class='add'>+	KUNIT_EXPECT_EQ(test, 0, regmap_write(map, 1, val_test));</div><div class='add'>+</div><div class='add'>+	/* Write some data to the noinc register */</div><div class='add'>+	KUNIT_EXPECT_EQ(test, 0, regmap_noinc_write(map, 0, val_array,</div><div class='add'>+						    sizeof(val_array)));</div><div class='add'>+</div><div class='add'>+	/* We should read back the last value written */</div><div class='add'>+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 0, &amp;val));</div><div class='add'>+	KUNIT_ASSERT_EQ(test, val_last, val);</div><div class='add'>+</div><div class='add'>+	/* Make sure we didn't touch the register after the noinc register */</div><div class='add'>+	KUNIT_EXPECT_EQ(test, 0, regmap_read(map, 1, &amp;val));</div><div class='add'>+	KUNIT_ASSERT_EQ(test, val_test, val);</div><div class='add'>+</div><div class='add'>+	regmap_exit(map);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void raw_sync(struct kunit *test)</div><div class='ctx'> {</div><div class='ctx'> 	struct raw_test_types *t = (struct raw_test_types *)test-&gt;param_value;</div><div class='hunk'>@@ -1284,6 +1343,7 @@ static struct kunit_case regmap_test_cases[] = {</div><div class='ctx'> 	KUNIT_CASE_PARAM(raw_read_defaults, raw_test_types_gen_params),</div><div class='ctx'> 	KUNIT_CASE_PARAM(raw_write_read_single, raw_test_types_gen_params),</div><div class='ctx'> 	KUNIT_CASE_PARAM(raw_write, raw_test_types_gen_params),</div><div class='add'>+	KUNIT_CASE_PARAM(raw_noinc_write, raw_test_types_gen_params),</div><div class='ctx'> 	KUNIT_CASE_PARAM(raw_sync, raw_test_cache_types_gen_params),</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/base/regmap/regmap-ram.c b/drivers/base/regmap/regmap-ram.c<br/>index 85f34a5dee04..192d6b131dff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-ram.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regmap-ram.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-ram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-ram.c</a></div><div class='hunk'>@@ -65,12 +65,12 @@ struct regmap *__regmap_init_ram(const struct regmap_config *config,</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	data-&gt;read = kcalloc(sizeof(bool), config-&gt;max_register + 1,</div><div class='add'>+	data-&gt;read = kcalloc(config-&gt;max_register + 1, sizeof(bool),</div><div class='ctx'> 			     GFP_KERNEL);</div><div class='ctx'> 	if (!data-&gt;read)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	data-&gt;written = kcalloc(sizeof(bool), config-&gt;max_register + 1,</div><div class='add'>+	data-&gt;written = kcalloc(config-&gt;max_register + 1, sizeof(bool),</div><div class='ctx'> 				GFP_KERNEL);</div><div class='ctx'> 	if (!data-&gt;written)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='head'>diff --git a/drivers/base/regmap/regmap-raw-ram.c b/drivers/base/regmap/regmap-raw-ram.c<br/>index c9b800885f3b..93ae07b503fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-raw-ram.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regmap-raw-ram.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap-raw-ram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap-raw-ram.c</a></div><div class='hunk'>@@ -41,10 +41,15 @@ static int regmap_raw_ram_gather_write(void *context,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	r = decode_reg(data-&gt;reg_endian, reg);</div><div class='del'>-	memcpy(&amp;our_buf[r], val, val_len);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; val_len / 2; i++)</div><div class='del'>-		data-&gt;written[r + i] = true;</div><div class='add'>+	if (data-&gt;noinc_reg &amp;&amp; data-&gt;noinc_reg(data, r)) {</div><div class='add'>+		memcpy(&amp;our_buf[r], val + val_len - 2, 2);</div><div class='add'>+		data-&gt;written[r] = true;</div><div class='add'>+	} else {</div><div class='add'>+		memcpy(&amp;our_buf[r], val, val_len);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; val_len / 2; i++)</div><div class='add'>+			data-&gt;written[r + i] = true;</div><div class='add'>+	}</div><div class='ctx'> 	</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -70,10 +75,16 @@ static int regmap_raw_ram_read(void *context,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	r = decode_reg(data-&gt;reg_endian, reg);</div><div class='del'>-	memcpy(val, &amp;our_buf[r], val_len);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; val_len / 2; i++)</div><div class='del'>-		data-&gt;read[r + i] = true;</div><div class='add'>+	if (data-&gt;noinc_reg &amp;&amp; data-&gt;noinc_reg(data, r)) {</div><div class='add'>+		for (i = 0; i &lt; val_len; i += 2)</div><div class='add'>+			memcpy(val + i, &amp;our_buf[r], 2);</div><div class='add'>+		data-&gt;read[r] = true;</div><div class='add'>+	} else {</div><div class='add'>+		memcpy(val, &amp;our_buf[r], val_len);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; val_len / 2; i++)</div><div class='add'>+			data-&gt;read[r + i] = true;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -111,12 +122,12 @@ struct regmap *__regmap_init_raw_ram(const struct regmap_config *config,</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	data-&gt;read = kcalloc(sizeof(bool), config-&gt;max_register + 1,</div><div class='add'>+	data-&gt;read = kcalloc(config-&gt;max_register + 1, sizeof(bool),</div><div class='ctx'> 			     GFP_KERNEL);</div><div class='ctx'> 	if (!data-&gt;read)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	data-&gt;written = kcalloc(sizeof(bool), config-&gt;max_register + 1,</div><div class='add'>+	data-&gt;written = kcalloc(config-&gt;max_register + 1, sizeof(bool),</div><div class='ctx'> 				GFP_KERNEL);</div><div class='ctx'> 	if (!data-&gt;written)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='head'>diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c<br/>index ea6157747199..6db77d8e45f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/regmap/regmap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/regmap/regmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/regmap/regmap.c</a></div><div class='hunk'>@@ -2136,7 +2136,7 @@ static int regmap_noinc_readwrite(struct regmap *map, unsigned int reg,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * regmap_noinc_write(): Write data from a register without incrementing the</div><div class='add'>+ * regmap_noinc_write(): Write data to a register without incrementing the</div><div class='ctx'>  *			register number</div><div class='ctx'>  *</div><div class='ctx'>  * @map: Register map to write to</div><div class='head'>diff --git a/drivers/base/soc.c b/drivers/base/soc.c<br/>index 8dec5228fde3..282c38aece0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/soc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/soc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/soc.c</a></div><div class='hunk'>@@ -28,7 +28,7 @@ struct soc_device {</div><div class='ctx'> 	int soc_dev_num;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct bus_type soc_bus_type = {</div><div class='add'>+static const struct bus_type soc_bus_type = {</div><div class='ctx'> 	.name  = "soc",</div><div class='ctx'> };</div><div class='ctx'> static bool soc_bus_registered;</div><div class='hunk'>@@ -106,7 +106,7 @@ static void soc_release(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);</div><div class='ctx'> </div><div class='del'>-	ida_simple_remove(&amp;soc_ida, soc_dev-&gt;soc_dev_num);</div><div class='add'>+	ida_free(&amp;soc_ida, soc_dev-&gt;soc_dev_num);</div><div class='ctx'> 	kfree(soc_dev-&gt;dev.groups);</div><div class='ctx'> 	kfree(soc_dev);</div><div class='ctx'> }</div><div class='hunk'>@@ -155,7 +155,7 @@ struct soc_device *soc_device_register(struct soc_device_attribute *soc_dev_attr</div><div class='ctx'> 	soc_attr_groups[1] = soc_dev_attr-&gt;custom_attr_group;</div><div class='ctx'> </div><div class='ctx'> 	/* Fetch a unique (reclaimable) SOC ID. */</div><div class='del'>-	ret = ida_simple_get(&amp;soc_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	ret = ida_alloc(&amp;soc_ida, GFP_KERNEL);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto out3;</div><div class='ctx'> 	soc_dev-&gt;soc_dev_num = ret;</div><div class='head'>diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c<br/>index 1886995a0b3a..36512fb75a20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/base/swnode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/base/swnode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/base/swnode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/base/swnode.c</a></div><div class='hunk'>@@ -541,6 +541,9 @@ software_node_get_reference_args(const struct fwnode_handle *fwnode,</div><div class='ctx'> 	if (nargs &gt; NR_FWNODE_REFERENCE_ARGS)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!args)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	args-&gt;fwnode = software_node_get(refnode);</div><div class='ctx'> 	args-&gt;nargs = nargs;</div><div class='ctx'> </div><div class='hunk'>@@ -747,10 +750,10 @@ static void software_node_release(struct kobject *kobj)</div><div class='ctx'> 	struct swnode *swnode = kobj_to_swnode(kobj);</div><div class='ctx'> </div><div class='ctx'> 	if (swnode-&gt;parent) {</div><div class='del'>-		ida_simple_remove(&amp;swnode-&gt;parent-&gt;child_ids, swnode-&gt;id);</div><div class='add'>+		ida_free(&amp;swnode-&gt;parent-&gt;child_ids, swnode-&gt;id);</div><div class='ctx'> 		list_del(&amp;swnode-&gt;entry);</div><div class='ctx'> 	} else {</div><div class='del'>-		ida_simple_remove(&amp;swnode_root_ids, swnode-&gt;id);</div><div class='add'>+		ida_free(&amp;swnode_root_ids, swnode-&gt;id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (swnode-&gt;allocated)</div><div class='hunk'>@@ -776,8 +779,8 @@ swnode_register(const struct software_node *node, struct swnode *parent,</div><div class='ctx'> 	if (!swnode)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	ret = ida_simple_get(parent ? &amp;parent-&gt;child_ids : &amp;swnode_root_ids,</div><div class='del'>-			     0, 0, GFP_KERNEL);</div><div class='add'>+	ret = ida_alloc(parent ? &amp;parent-&gt;child_ids : &amp;swnode_root_ids,</div><div class='add'>+			GFP_KERNEL);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		kfree(swnode);</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='head'>diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c<br/>index aa0581cda718..ed3be52ab63d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bcma/driver_pci_host.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bcma/driver_pci_host.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bcma/driver_pci_host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bcma/driver_pci_host.c</a></div><div class='hunk'>@@ -280,7 +280,7 @@ static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev,</div><div class='ctx'> 	/* check for Header type 0 */</div><div class='ctx'> 	bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &amp;byte_val,</div><div class='ctx'> 				sizeof(u8));</div><div class='del'>-	if ((byte_val &amp; 0x7F) != PCI_HEADER_TYPE_NORMAL)</div><div class='add'>+	if ((byte_val &amp; PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)</div><div class='ctx'> 		return cap_ptr;</div><div class='ctx'> </div><div class='ctx'> 	/* check if the capability pointer field exists */</div><div class='head'>diff --git a/drivers/block/aoe/aoeblk.c b/drivers/block/aoe/aoeblk.c<br/>index cf6883756155..d2dbf8aaccb5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/aoe/aoeblk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/aoe/aoeblk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/aoe/aoeblk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/aoe/aoeblk.c</a></div><div class='hunk'>@@ -383,7 +383,8 @@ aoeblk_gdalloc(void *vp)</div><div class='ctx'> 	WARN_ON(d-&gt;flags &amp; DEVFL_TKILL);</div><div class='ctx'> 	WARN_ON(d-&gt;gd);</div><div class='ctx'> 	WARN_ON(d-&gt;flags &amp; DEVFL_UP);</div><div class='del'>-	blk_queue_max_hw_sectors(gd-&gt;queue, BLK_DEF_MAX_SECTORS);</div><div class='add'>+	/* random number picked from the history block max_sectors cap */</div><div class='add'>+	blk_queue_max_hw_sectors(gd-&gt;queue, 2560u);</div><div class='ctx'> 	blk_queue_io_opt(gd-&gt;queue, SZ_2M);</div><div class='ctx'> 	d-&gt;bufpool = mp;</div><div class='ctx'> 	d-&gt;blkq = gd-&gt;queue;</div><div class='head'>diff --git a/drivers/block/drbd/drbd_actlog.c b/drivers/block/drbd/drbd_actlog.c<br/>index 64b3a1c76f03..742b2908ff68 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/drbd/drbd_actlog.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/drbd/drbd_actlog.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/drbd/drbd_actlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/drbd/drbd_actlog.c</a></div><div class='hunk'>@@ -838,8 +838,8 @@ static bool plausible_request_size(int size)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* clear the bit corresponding to the piece of storage in question:</div><div class='del'>- * size byte of data starting from sector.  Only clear a bits of the affected</div><div class='del'>- * one ore more _aligned_ BM_BLOCK_SIZE blocks.</div><div class='add'>+ * size byte of data starting from sector.  Only clear bits of the affected</div><div class='add'>+ * one or more _aligned_ BM_BLOCK_SIZE blocks.</div><div class='ctx'>  *</div><div class='ctx'>  * called by worker on C_SYNC_TARGET and receiver on SyncSource.</div><div class='ctx'>  *</div><div class='hunk'>@@ -957,7 +957,9 @@ static int _is_in_al(struct drbd_device *device, unsigned int enr)</div><div class='ctx'>  * @device:	DRBD device.</div><div class='ctx'>  * @sector:	The sector number.</div><div class='ctx'>  *</div><div class='del'>- * This functions sleeps on al_wait. Returns 0 on success, -EINTR if interrupted.</div><div class='add'>+ * This functions sleeps on al_wait.</div><div class='add'>+ *</div><div class='add'>+ * Returns: %0 on success, -EINTR if interrupted.</div><div class='ctx'>  */</div><div class='ctx'> int drbd_rs_begin_io(struct drbd_device *device, sector_t sector)</div><div class='ctx'> {</div><div class='hunk'>@@ -1004,11 +1006,13 @@ retry:</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * drbd_try_rs_begin_io() - Gets an extent in the resync LRU cache, does not sleep</div><div class='del'>- * @device:	DRBD device.</div><div class='add'>+ * @peer_device: DRBD device.</div><div class='ctx'>  * @sector:	The sector number.</div><div class='ctx'>  *</div><div class='ctx'>  * Gets an extent in the resync LRU cache, sets it to BME_NO_WRITES, then</div><div class='del'>- * tries to set it to BME_LOCKED. Returns 0 upon success, and -EAGAIN</div><div class='add'>+ * tries to set it to BME_LOCKED.</div><div class='add'>+ *</div><div class='add'>+ * Returns: %0 upon success, and -EAGAIN</div><div class='ctx'>  * if there is still application IO going on in this area.</div><div class='ctx'>  */</div><div class='ctx'> int drbd_try_rs_begin_io(struct drbd_peer_device *peer_device, sector_t sector)</div><div class='hunk'>@@ -1190,7 +1194,7 @@ void drbd_rs_cancel_all(struct drbd_device *device)</div><div class='ctx'>  * drbd_rs_del_all() - Gracefully remove all extents from the resync LRU</div><div class='ctx'>  * @device:	DRBD device.</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 upon success, -EAGAIN if at least one reference count was</div><div class='add'>+ * Returns: %0 upon success, -EAGAIN if at least one reference count was</div><div class='ctx'>  * not zero.</div><div class='ctx'>  */</div><div class='ctx'> int drbd_rs_del_all(struct drbd_device *device)</div><div class='head'>diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c<br/>index 11114a5d9e5c..d0e41d52d6a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/floppy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/floppy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/floppy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/floppy.c</a></div><div class='hunk'>@@ -3079,7 +3079,7 @@ static void raw_cmd_free(struct floppy_raw_cmd **ptr)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define MAX_LEN (1UL &lt;&lt; MAX_ORDER &lt;&lt; PAGE_SHIFT)</div><div class='add'>+#define MAX_LEN (1UL &lt;&lt; MAX_PAGE_ORDER &lt;&lt; PAGE_SHIFT)</div><div class='ctx'> </div><div class='ctx'> static int raw_cmd_copyin(int cmd, void __user *param,</div><div class='ctx'> 				 struct floppy_raw_cmd **rcmd)</div><div class='head'>diff --git a/drivers/block/loop.c b/drivers/block/loop.c<br/>index 9f2d412fc560..f8145499da38 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/loop.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/loop.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/loop.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/loop.c</a></div><div class='hunk'>@@ -165,39 +165,37 @@ static loff_t get_loop_size(struct loop_device *lo, struct file *file)</div><div class='ctx'> 	return get_size(lo-&gt;lo_offset, lo-&gt;lo_sizelimit, file);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * We support direct I/O only if lo_offset is aligned with the logical I/O size</div><div class='add'>+ * of backing device, and the logical block size of loop is bigger than that of</div><div class='add'>+ * the backing device.</div><div class='add'>+ */</div><div class='add'>+static bool lo_bdev_can_use_dio(struct loop_device *lo,</div><div class='add'>+		struct block_device *backing_bdev)</div><div class='add'>+{</div><div class='add'>+	unsigned short sb_bsize = bdev_logical_block_size(backing_bdev);</div><div class='add'>+</div><div class='add'>+	if (queue_logical_block_size(lo-&gt;lo_queue) &lt; sb_bsize)</div><div class='add'>+		return false;</div><div class='add'>+	if (lo-&gt;lo_offset &amp; (sb_bsize - 1))</div><div class='add'>+		return false;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void __loop_update_dio(struct loop_device *lo, bool dio)</div><div class='ctx'> {</div><div class='ctx'> 	struct file *file = lo-&gt;lo_backing_file;</div><div class='del'>-	struct address_space *mapping = file-&gt;f_mapping;</div><div class='del'>-	struct inode *inode = mapping-&gt;host;</div><div class='del'>-	unsigned short sb_bsize = 0;</div><div class='del'>-	unsigned dio_align = 0;</div><div class='add'>+	struct inode *inode = file-&gt;f_mapping-&gt;host;</div><div class='add'>+	struct block_device *backing_bdev = NULL;</div><div class='ctx'> 	bool use_dio;</div><div class='ctx'> </div><div class='del'>-	if (inode-&gt;i_sb-&gt;s_bdev) {</div><div class='del'>-		sb_bsize = bdev_logical_block_size(inode-&gt;i_sb-&gt;s_bdev);</div><div class='del'>-		dio_align = sb_bsize - 1;</div><div class='del'>-	}</div><div class='add'>+	if (S_ISBLK(inode-&gt;i_mode))</div><div class='add'>+		backing_bdev = I_BDEV(inode);</div><div class='add'>+	else if (inode-&gt;i_sb-&gt;s_bdev)</div><div class='add'>+		backing_bdev = inode-&gt;i_sb-&gt;s_bdev;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * We support direct I/O only if lo_offset is aligned with the</div><div class='del'>-	 * logical I/O size of backing device, and the logical block</div><div class='del'>-	 * size of loop is bigger than the backing device's.</div><div class='del'>-	 *</div><div class='del'>-	 * TODO: the above condition may be loosed in the future, and</div><div class='del'>-	 * direct I/O may be switched runtime at that time because most</div><div class='del'>-	 * of requests in sane applications should be PAGE_SIZE aligned</div><div class='del'>-	 */</div><div class='del'>-	if (dio) {</div><div class='del'>-		if (queue_logical_block_size(lo-&gt;lo_queue) &gt;= sb_bsize &amp;&amp;</div><div class='del'>-		    !(lo-&gt;lo_offset &amp; dio_align) &amp;&amp;</div><div class='del'>-		    (file-&gt;f_mode &amp; FMODE_CAN_ODIRECT))</div><div class='del'>-			use_dio = true;</div><div class='del'>-		else</div><div class='del'>-			use_dio = false;</div><div class='del'>-	} else {</div><div class='del'>-		use_dio = false;</div><div class='del'>-	}</div><div class='add'>+	use_dio = dio &amp;&amp; (file-&gt;f_mode &amp; FMODE_CAN_ODIRECT) &amp;&amp;</div><div class='add'>+		(!backing_bdev || lo_bdev_can_use_dio(lo, backing_bdev));</div><div class='ctx'> </div><div class='ctx'> 	if (lo-&gt;use_dio == use_dio)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -245,9 +243,7 @@ static int lo_write_bvec(struct file *file, struct bio_vec *bvec, loff_t *ppos)</div><div class='ctx'> </div><div class='ctx'> 	iov_iter_bvec(&amp;i, ITER_SOURCE, bvec, 1, bvec-&gt;bv_len);</div><div class='ctx'> </div><div class='del'>-	file_start_write(file);</div><div class='ctx'> 	bw = vfs_iter_write(file, &amp;i, ppos, 0);</div><div class='del'>-	file_end_write(file);</div><div class='ctx'> </div><div class='ctx'> 	if (likely(bw ==  bvec-&gt;bv_len))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1303,8 +1299,6 @@ loop_set_status(struct loop_device *lo, const struct loop_info64 *info)</div><div class='ctx'> 		loop_set_size(lo, new_size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	loop_config_discard(lo);</div><div class='del'>-</div><div class='ctx'> 	/* update dio if lo_offset or transfer is changed */</div><div class='ctx'> 	__loop_update_dio(lo, lo-&gt;use_dio);</div><div class='ctx'> </div><div class='hunk'>@@ -2038,7 +2032,8 @@ static int loop_add(int i)</div><div class='ctx'> 	}</div><div class='ctx'> 	lo-&gt;lo_queue = lo-&gt;lo_disk-&gt;queue;</div><div class='ctx'> </div><div class='del'>-	blk_queue_max_hw_sectors(lo-&gt;lo_queue, BLK_DEF_MAX_SECTORS);</div><div class='add'>+	/* random number picked from the history block max_sectors cap */</div><div class='add'>+	blk_queue_max_hw_sectors(lo-&gt;lo_queue, 2560u);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * By default, we do buffer IO, so it doesn't make sense to enable</div><div class='head'>diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c<br/>index b6414e1e645b..33a8f37bb6a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/nbd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/nbd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/nbd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/nbd.c</a></div><div class='hunk'>@@ -334,10 +334,8 @@ static int nbd_set_size(struct nbd_device *nbd, loff_t bytesize,</div><div class='ctx'> 	if (!nbd-&gt;pid)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (nbd-&gt;config-&gt;flags &amp; NBD_FLAG_SEND_TRIM) {</div><div class='del'>-		nbd-&gt;disk-&gt;queue-&gt;limits.discard_granularity = blksize;</div><div class='add'>+	if (nbd-&gt;config-&gt;flags &amp; NBD_FLAG_SEND_TRIM)</div><div class='ctx'> 		blk_queue_max_discard_sectors(nbd-&gt;disk-&gt;queue, UINT_MAX);</div><div class='del'>-	}</div><div class='ctx'> 	blk_queue_logical_block_size(nbd-&gt;disk-&gt;queue, blksize);</div><div class='ctx'> 	blk_queue_physical_block_size(nbd-&gt;disk-&gt;queue, blksize);</div><div class='ctx'> </div><div class='hunk'>@@ -510,7 +508,7 @@ static int __sock_xmit(struct nbd_device *nbd, struct socket *sock, int send,</div><div class='ctx'> 		       struct iov_iter *iter, int msg_flags, int *sent)</div><div class='ctx'> {</div><div class='ctx'> 	int result;</div><div class='del'>-	struct msghdr msg;</div><div class='add'>+	struct msghdr msg = {} ;</div><div class='ctx'> 	unsigned int noreclaim_flag;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(!sock)) {</div><div class='hunk'>@@ -526,10 +524,6 @@ static int __sock_xmit(struct nbd_device *nbd, struct socket *sock, int send,</div><div class='ctx'> 	do {</div><div class='ctx'> 		sock-&gt;sk-&gt;sk_allocation = GFP_NOIO | __GFP_MEMALLOC;</div><div class='ctx'> 		sock-&gt;sk-&gt;sk_use_task_frag = false;</div><div class='del'>-		msg.msg_name = NULL;</div><div class='del'>-		msg.msg_namelen = 0;</div><div class='del'>-		msg.msg_control = NULL;</div><div class='del'>-		msg.msg_controllen = 0;</div><div class='ctx'> 		msg.msg_flags = msg_flags | MSG_NOSIGNAL;</div><div class='ctx'> </div><div class='ctx'> 		if (send)</div><div class='hunk'>@@ -1357,7 +1351,6 @@ static void nbd_config_put(struct nbd_device *nbd)</div><div class='ctx'> 		nbd-&gt;config = NULL;</div><div class='ctx'> </div><div class='ctx'> 		nbd-&gt;tag_set.timeout = 0;</div><div class='del'>-		nbd-&gt;disk-&gt;queue-&gt;limits.discard_granularity = 0;</div><div class='ctx'> 		blk_queue_max_discard_sectors(nbd-&gt;disk-&gt;queue, 0);</div><div class='ctx'> </div><div class='ctx'> 		mutex_unlock(&amp;nbd-&gt;config_lock);</div><div class='hunk'>@@ -1850,7 +1843,6 @@ static struct nbd_device *nbd_dev_add(int index, unsigned int refs)</div><div class='ctx'> 	 * Tell the block layer that we are not a rotational device</div><div class='ctx'> 	 */</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_NONROT, disk-&gt;queue);</div><div class='del'>-	disk-&gt;queue-&gt;limits.discard_granularity = 0;</div><div class='ctx'> 	blk_queue_max_discard_sectors(disk-&gt;queue, 0);</div><div class='ctx'> 	blk_queue_max_segment_size(disk-&gt;queue, UINT_MAX);</div><div class='ctx'> 	blk_queue_max_segments(disk-&gt;queue, USHRT_MAX);</div><div class='head'>diff --git a/drivers/block/null_blk/main.c b/drivers/block/null_blk/main.c<br/>index 3021d58ca51c..36755f263e8e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/null_blk/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/null_blk/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/null_blk/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/null_blk/main.c</a></div><div class='hunk'>@@ -1840,7 +1840,7 @@ static void null_del_dev(struct nullb *nullb)</div><div class='ctx'> </div><div class='ctx'> 	dev = nullb-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	ida_simple_remove(&amp;nullb_indexes, nullb-&gt;index);</div><div class='add'>+	ida_free(&amp;nullb_indexes, nullb-&gt;index);</div><div class='ctx'> </div><div class='ctx'> 	list_del_init(&amp;nullb-&gt;list);</div><div class='ctx'> </div><div class='hunk'>@@ -1880,7 +1880,6 @@ static void null_config_discard(struct nullb *nullb)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	nullb-&gt;q-&gt;limits.discard_granularity = nullb-&gt;dev-&gt;blocksize;</div><div class='ctx'> 	blk_queue_max_discard_sectors(nullb-&gt;q, UINT_MAX &gt;&gt; 9);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2175,7 +2174,7 @@ static int null_add_dev(struct nullb_device *dev)</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_NONROT, nullb-&gt;q);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;lock);</div><div class='del'>-	rv = ida_simple_get(&amp;nullb_indexes, 0, 0, GFP_KERNEL);</div><div class='add'>+	rv = ida_alloc(&amp;nullb_indexes, GFP_KERNEL);</div><div class='ctx'> 	if (rv &lt; 0) {</div><div class='ctx'> 		mutex_unlock(&amp;lock);</div><div class='ctx'> 		goto out_cleanup_zone;</div><div class='hunk'>@@ -2186,10 +2185,8 @@ static int null_add_dev(struct nullb_device *dev)</div><div class='ctx'> </div><div class='ctx'> 	blk_queue_logical_block_size(nullb-&gt;q, dev-&gt;blocksize);</div><div class='ctx'> 	blk_queue_physical_block_size(nullb-&gt;q, dev-&gt;blocksize);</div><div class='del'>-	if (!dev-&gt;max_sectors)</div><div class='del'>-		dev-&gt;max_sectors = queue_max_hw_sectors(nullb-&gt;q);</div><div class='del'>-	dev-&gt;max_sectors = min(dev-&gt;max_sectors, BLK_DEF_MAX_SECTORS);</div><div class='del'>-	blk_queue_max_hw_sectors(nullb-&gt;q, dev-&gt;max_sectors);</div><div class='add'>+	if (dev-&gt;max_sectors)</div><div class='add'>+		blk_queue_max_hw_sectors(nullb-&gt;q, dev-&gt;max_sectors);</div><div class='ctx'> </div><div class='ctx'> 	if (dev-&gt;virt_boundary)</div><div class='ctx'> 		blk_queue_virt_boundary(nullb-&gt;q, PAGE_SIZE - 1);</div><div class='hunk'>@@ -2289,12 +2286,6 @@ static int __init null_init(void)</div><div class='ctx'> 		g_bs = PAGE_SIZE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (g_max_sectors &gt; BLK_DEF_MAX_SECTORS) {</div><div class='del'>-		pr_warn("invalid max sectors\n");</div><div class='del'>-		pr_warn("defaults max sectors to %u\n", BLK_DEF_MAX_SECTORS);</div><div class='del'>-		g_max_sectors = BLK_DEF_MAX_SECTORS;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (g_home_node != NUMA_NO_NODE &amp;&amp; g_home_node &gt;= nr_online_nodes) {</div><div class='ctx'> 		pr_err("invalid home_node value\n");</div><div class='ctx'> 		g_home_node = NUMA_NO_NODE;</div><div class='head'>diff --git a/drivers/block/null_blk/zoned.c b/drivers/block/null_blk/zoned.c<br/>index 55c5b48bc276..6f5e0994862e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/null_blk/zoned.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/null_blk/zoned.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/null_blk/zoned.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/null_blk/zoned.c</a></div><div class='hunk'>@@ -159,7 +159,7 @@ int null_register_zoned_dev(struct nullb *nullb)</div><div class='ctx'> 	struct nullb_device *dev = nullb-&gt;dev;</div><div class='ctx'> 	struct request_queue *q = nullb-&gt;q;</div><div class='ctx'> </div><div class='del'>-	disk_set_zoned(nullb-&gt;disk, BLK_ZONED_HM);</div><div class='add'>+	disk_set_zoned(nullb-&gt;disk);</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_ZONE_RESETALL, q);</div><div class='ctx'> 	blk_queue_required_elevator_features(q, ELEVATOR_F_ZBD_SEQ_WRITE);</div><div class='ctx'> 	blk_queue_chunk_sectors(q, dev-&gt;zone_size_sects);</div><div class='head'>diff --git a/drivers/block/rnbd/rnbd-clt.c b/drivers/block/rnbd/rnbd-clt.c<br/>index b0550b68645d..4044c369d22a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-clt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/rnbd/rnbd-clt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-clt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-clt.c</a></div><div class='hunk'>@@ -1006,10 +1006,10 @@ static int rnbd_client_xfer_request(struct rnbd_clt_dev *dev,</div><div class='ctx'> 	msg.prio	= cpu_to_le16(req_get_ioprio(rq));</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * We only support discards with single segment for now.</div><div class='add'>+	 * We only support discards/WRITE_ZEROES with single segment for now.</div><div class='ctx'> 	 * See queue limits.</div><div class='ctx'> 	 */</div><div class='del'>-	if (req_op(rq) != REQ_OP_DISCARD)</div><div class='add'>+	if ((req_op(rq) != REQ_OP_DISCARD) &amp;&amp; (req_op(rq) != REQ_OP_WRITE_ZEROES))</div><div class='ctx'> 		sg_cnt = blk_rq_map_sg(dev-&gt;queue, rq, iu-&gt;sgt.sgl);</div><div class='ctx'> </div><div class='ctx'> 	if (sg_cnt == 0)</div><div class='hunk'>@@ -1362,6 +1362,8 @@ static void setup_request_queue(struct rnbd_clt_dev *dev,</div><div class='ctx'> 	blk_queue_write_cache(dev-&gt;queue,</div><div class='ctx'> 			      !!(rsp-&gt;cache_policy &amp; RNBD_WRITEBACK),</div><div class='ctx'> 			      !!(rsp-&gt;cache_policy &amp; RNBD_FUA));</div><div class='add'>+	blk_queue_max_write_zeroes_sectors(dev-&gt;queue,</div><div class='add'>+					   le32_to_cpu(rsp-&gt;max_write_zeroes_sectors));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rnbd_clt_setup_gen_disk(struct rnbd_clt_dev *dev,</div><div class='hunk'>@@ -1567,8 +1569,8 @@ struct rnbd_clt_dev *rnbd_clt_map_device(const char *sessname,</div><div class='ctx'> </div><div class='ctx'> 	dev = init_dev(sess, access_mode, pathname, nr_poll_queues);</div><div class='ctx'> 	if (IS_ERR(dev)) {</div><div class='del'>-		pr_err("map_device: failed to map device '%s' from session %s, can't initialize device, err: %ld\n",</div><div class='del'>-		       pathname, sess-&gt;sessname, PTR_ERR(dev));</div><div class='add'>+		pr_err("map_device: failed to map device '%s' from session %s, can't initialize device, err: %pe\n",</div><div class='add'>+		       pathname, sess-&gt;sessname, dev);</div><div class='ctx'> 		ret = PTR_ERR(dev);</div><div class='ctx'> 		goto put_sess;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1626,10 +1628,11 @@ struct rnbd_clt_dev *rnbd_clt_map_device(const char *sessname,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rnbd_clt_info(dev,</div><div class='del'>-		       "map_device: Device mapped as %s (nsectors: %llu, logical_block_size: %d, physical_block_size: %d, max_discard_sectors: %d, discard_granularity: %d, discard_alignment: %d, secure_discard: %d, max_segments: %d, max_hw_sectors: %d, wc: %d, fua: %d)\n",</div><div class='add'>+		       "map_device: Device mapped as %s (nsectors: %llu, logical_block_size: %d, physical_block_size: %d, max_write_zeroes_sectors: %d, max_discard_sectors: %d, discard_granularity: %d, discard_alignment: %d, secure_discard: %d, max_segments: %d, max_hw_sectors: %d, wc: %d, fua: %d)\n",</div><div class='ctx'> 		       dev-&gt;gd-&gt;disk_name, le64_to_cpu(rsp-&gt;nsectors),</div><div class='ctx'> 		       le16_to_cpu(rsp-&gt;logical_block_size),</div><div class='ctx'> 		       le16_to_cpu(rsp-&gt;physical_block_size),</div><div class='add'>+		       le32_to_cpu(rsp-&gt;max_write_zeroes_sectors),</div><div class='ctx'> 		       le32_to_cpu(rsp-&gt;max_discard_sectors),</div><div class='ctx'> 		       le32_to_cpu(rsp-&gt;discard_granularity),</div><div class='ctx'> 		       le32_to_cpu(rsp-&gt;discard_alignment),</div><div class='head'>diff --git a/drivers/block/rnbd/rnbd-proto.h b/drivers/block/rnbd/rnbd-proto.h<br/>index e32f8f2c868a..f35be51d213c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-proto.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/rnbd/rnbd-proto.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-proto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-proto.h</a></div><div class='hunk'>@@ -128,7 +128,7 @@ enum rnbd_cache_policy {</div><div class='ctx'>  * @device_id:		device_id on server side to identify the device</div><div class='ctx'>  * @nsectors:		number of sectors in the usual 512b unit</div><div class='ctx'>  * @max_hw_sectors:	max hardware sectors in the usual 512b unit</div><div class='del'>- * @max_write_same_sectors: max sectors for WRITE SAME in the 512b unit</div><div class='add'>+ * @max_write_zeroes_sectors: max sectors for WRITE ZEROES in the 512b unit</div><div class='ctx'>  * @max_discard_sectors: max. sectors that can be discarded at once in 512b</div><div class='ctx'>  * unit.</div><div class='ctx'>  * @discard_granularity: size of the internal discard allocation unit in bytes</div><div class='hunk'>@@ -145,7 +145,7 @@ struct rnbd_msg_open_rsp {</div><div class='ctx'> 	__le32			device_id;</div><div class='ctx'> 	__le64			nsectors;</div><div class='ctx'> 	__le32			max_hw_sectors;</div><div class='del'>-	__le32			max_write_same_sectors;</div><div class='add'>+	__le32			max_write_zeroes_sectors;</div><div class='ctx'> 	__le32			max_discard_sectors;</div><div class='ctx'> 	__le32			discard_granularity;</div><div class='ctx'> 	__le32			discard_alignment;</div><div class='hunk'>@@ -186,7 +186,7 @@ struct rnbd_msg_io {</div><div class='ctx'>  * @RNBD_OP_FLUSH:	     flush the volatile write cache</div><div class='ctx'>  * @RNBD_OP_DISCARD:        discard sectors</div><div class='ctx'>  * @RNBD_OP_SECURE_ERASE:   securely erase sectors</div><div class='del'>- * @RNBD_OP_WRITE_SAME:     write the same sectors many times</div><div class='add'>+ * @RNBD_OP_WRITE_ZEROES:   write zeroes sectors</div><div class='ctx'> </div><div class='ctx'>  * @RNBD_F_SYNC:	     request is sync (sync write or read)</div><div class='ctx'>  * @RNBD_F_FUA:             forced unit access</div><div class='hunk'>@@ -199,7 +199,7 @@ enum rnbd_io_flags {</div><div class='ctx'> 	RNBD_OP_FLUSH		= 2,</div><div class='ctx'> 	RNBD_OP_DISCARD	= 3,</div><div class='ctx'> 	RNBD_OP_SECURE_ERASE	= 4,</div><div class='del'>-	RNBD_OP_WRITE_SAME	= 5,</div><div class='add'>+	RNBD_OP_WRITE_ZEROES	= 5,</div><div class='ctx'> </div><div class='ctx'> 	/* Flags */</div><div class='ctx'> 	RNBD_F_SYNC  = 1&lt;&lt;(RNBD_OP_BITS + 0),</div><div class='hunk'>@@ -236,6 +236,9 @@ static inline blk_opf_t rnbd_to_bio_flags(u32 rnbd_opf)</div><div class='ctx'> 	case RNBD_OP_SECURE_ERASE:</div><div class='ctx'> 		bio_opf = REQ_OP_SECURE_ERASE;</div><div class='ctx'> 		break;</div><div class='add'>+	case RNBD_OP_WRITE_ZEROES:</div><div class='add'>+		bio_opf = REQ_OP_WRITE_ZEROES;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		WARN(1, "Unknown RNBD type: %d (flags %d)\n",</div><div class='ctx'> 		     rnbd_op(rnbd_opf), rnbd_opf);</div><div class='hunk'>@@ -268,6 +271,9 @@ static inline u32 rq_to_rnbd_flags(struct request *rq)</div><div class='ctx'> 	case REQ_OP_SECURE_ERASE:</div><div class='ctx'> 		rnbd_opf = RNBD_OP_SECURE_ERASE;</div><div class='ctx'> 		break;</div><div class='add'>+	case REQ_OP_WRITE_ZEROES:</div><div class='add'>+		rnbd_opf = RNBD_OP_WRITE_ZEROES;</div><div class='add'>+		break;</div><div class='ctx'> 	case REQ_OP_FLUSH:</div><div class='ctx'> 		rnbd_opf = RNBD_OP_FLUSH;</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/block/rnbd/rnbd-srv.c b/drivers/block/rnbd/rnbd-srv.c<br/>index 65de51f3dfd9..3a0d5dcec6f2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-srv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/rnbd/rnbd-srv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/rnbd/rnbd-srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/rnbd/rnbd-srv.c</a></div><div class='hunk'>@@ -136,8 +136,8 @@ static int process_rdma(struct rnbd_srv_session *srv_sess,</div><div class='ctx'> </div><div class='ctx'> 	sess_dev = rnbd_get_sess_dev(dev_id, srv_sess);</div><div class='ctx'> 	if (IS_ERR(sess_dev)) {</div><div class='del'>-		pr_err_ratelimited("Got I/O request on session %s for unknown device id %d\n",</div><div class='del'>-				   srv_sess-&gt;sessname, dev_id);</div><div class='add'>+		pr_err_ratelimited("Got I/O request on session %s for unknown device id %d: %pe\n",</div><div class='add'>+				   srv_sess-&gt;sessname, dev_id, sess_dev);</div><div class='ctx'> 		err = -ENOTCONN;</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -544,7 +544,8 @@ static void rnbd_srv_fill_msg_open_rsp(struct rnbd_msg_open_rsp *rsp,</div><div class='ctx'> 	rsp-&gt;max_segments = cpu_to_le16(bdev_max_segments(bdev));</div><div class='ctx'> 	rsp-&gt;max_hw_sectors =</div><div class='ctx'> 		cpu_to_le32(queue_max_hw_sectors(bdev_get_queue(bdev)));</div><div class='del'>-	rsp-&gt;max_write_same_sectors = 0;</div><div class='add'>+	rsp-&gt;max_write_zeroes_sectors =</div><div class='add'>+		cpu_to_le32(bdev_write_zeroes_sectors(bdev));</div><div class='ctx'> 	rsp-&gt;max_discard_sectors = cpu_to_le32(bdev_max_discard_sectors(bdev));</div><div class='ctx'> 	rsp-&gt;discard_granularity = cpu_to_le32(bdev_discard_granularity(bdev));</div><div class='ctx'> 	rsp-&gt;discard_alignment = cpu_to_le32(bdev_discard_alignment(bdev));</div><div class='hunk'>@@ -585,6 +586,7 @@ static char *rnbd_srv_get_full_path(struct rnbd_srv_session *srv_sess,</div><div class='ctx'> {</div><div class='ctx'> 	char *full_path;</div><div class='ctx'> 	char *a, *b;</div><div class='add'>+	int len;</div><div class='ctx'> </div><div class='ctx'> 	full_path = kmalloc(PATH_MAX, GFP_KERNEL);</div><div class='ctx'> 	if (!full_path)</div><div class='hunk'>@@ -596,19 +598,19 @@ static char *rnbd_srv_get_full_path(struct rnbd_srv_session *srv_sess,</div><div class='ctx'> 	 */</div><div class='ctx'> 	a = strnstr(dev_search_path, "%SESSNAME%", sizeof(dev_search_path));</div><div class='ctx'> 	if (a) {</div><div class='del'>-		int len = a - dev_search_path;</div><div class='add'>+		len = a - dev_search_path;</div><div class='ctx'> </div><div class='ctx'> 		len = snprintf(full_path, PATH_MAX, "%.*s/%s/%s", len,</div><div class='ctx'> 			       dev_search_path, srv_sess-&gt;sessname, dev_name);</div><div class='del'>-		if (len &gt;= PATH_MAX) {</div><div class='del'>-			pr_err("Too long path: %s, %s, %s\n",</div><div class='del'>-			       dev_search_path, srv_sess-&gt;sessname, dev_name);</div><div class='del'>-			kfree(full_path);</div><div class='del'>-			return ERR_PTR(-EINVAL);</div><div class='del'>-		}</div><div class='ctx'> 	} else {</div><div class='del'>-		snprintf(full_path, PATH_MAX, "%s/%s",</div><div class='del'>-			 dev_search_path, dev_name);</div><div class='add'>+		len = snprintf(full_path, PATH_MAX, "%s/%s",</div><div class='add'>+			       dev_search_path, dev_name);</div><div class='add'>+	}</div><div class='add'>+	if (len &gt;= PATH_MAX) {</div><div class='add'>+		pr_err("Too long path: %s, %s, %s\n",</div><div class='add'>+		       dev_search_path, srv_sess-&gt;sessname, dev_name);</div><div class='add'>+		kfree(full_path);</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* eliminitate duplicated slashes */</div><div class='hunk'>@@ -709,24 +711,24 @@ static int process_msg_open(struct rnbd_srv_session *srv_sess,</div><div class='ctx'> 	full_path = rnbd_srv_get_full_path(srv_sess, open_msg-&gt;dev_name);</div><div class='ctx'> 	if (IS_ERR(full_path)) {</div><div class='ctx'> 		ret = PTR_ERR(full_path);</div><div class='del'>-		pr_err("Opening device '%s' for client %s failed, failed to get device full path, err: %d\n",</div><div class='del'>-		       open_msg-&gt;dev_name, srv_sess-&gt;sessname, ret);</div><div class='add'>+		pr_err("Opening device '%s' for client %s failed, failed to get device full path, err: %pe\n",</div><div class='add'>+		       open_msg-&gt;dev_name, srv_sess-&gt;sessname, full_path);</div><div class='ctx'> 		goto reject;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	bdev_handle = bdev_open_by_path(full_path, open_flags, NULL, NULL);</div><div class='ctx'> 	if (IS_ERR(bdev_handle)) {</div><div class='ctx'> 		ret = PTR_ERR(bdev_handle);</div><div class='del'>-		pr_err("Opening device '%s' on session %s failed, failed to open the block device, err: %d\n",</div><div class='del'>-		       full_path, srv_sess-&gt;sessname, ret);</div><div class='add'>+		pr_err("Opening device '%s' on session %s failed, failed to open the block device, err: %pe\n",</div><div class='add'>+		       full_path, srv_sess-&gt;sessname, bdev_handle);</div><div class='ctx'> 		goto free_path;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	srv_dev = rnbd_srv_get_or_create_srv_dev(bdev_handle-&gt;bdev, srv_sess,</div><div class='ctx'> 						  open_msg-&gt;access_mode);</div><div class='ctx'> 	if (IS_ERR(srv_dev)) {</div><div class='del'>-		pr_err("Opening device '%s' on session %s failed, creating srv_dev failed, err: %ld\n",</div><div class='del'>-		       full_path, srv_sess-&gt;sessname, PTR_ERR(srv_dev));</div><div class='add'>+		pr_err("Opening device '%s' on session %s failed, creating srv_dev failed, err: %pe\n",</div><div class='add'>+		       full_path, srv_sess-&gt;sessname, srv_dev);</div><div class='ctx'> 		ret = PTR_ERR(srv_dev);</div><div class='ctx'> 		goto blkdev_put;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -736,8 +738,8 @@ static int process_msg_open(struct rnbd_srv_session *srv_sess,</div><div class='ctx'> 				open_msg-&gt;access_mode == RNBD_ACCESS_RO,</div><div class='ctx'> 				srv_dev);</div><div class='ctx'> 	if (IS_ERR(srv_sess_dev)) {</div><div class='del'>-		pr_err("Opening device '%s' on session %s failed, creating sess_dev failed, err: %ld\n",</div><div class='del'>-		       full_path, srv_sess-&gt;sessname, PTR_ERR(srv_sess_dev));</div><div class='add'>+		pr_err("Opening device '%s' on session %s failed, creating sess_dev failed, err: %pe\n",</div><div class='add'>+		       full_path, srv_sess-&gt;sessname, srv_sess_dev);</div><div class='ctx'> 		ret = PTR_ERR(srv_sess_dev);</div><div class='ctx'> 		goto srv_dev_put;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -818,7 +820,7 @@ static int __init rnbd_srv_init_module(void)</div><div class='ctx'> 	};</div><div class='ctx'> 	rtrs_ctx = rtrs_srv_open(&amp;rtrs_ops, port_nr);</div><div class='ctx'> 	if (IS_ERR(rtrs_ctx)) {</div><div class='del'>-		pr_err("rtrs_srv_open(), err: %d\n", err);</div><div class='add'>+		pr_err("rtrs_srv_open(), err: %pe\n", rtrs_ctx);</div><div class='ctx'> 		return PTR_ERR(rtrs_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/block/ublk_drv.c b/drivers/block/ublk_drv.c<br/>index 83600b45e12a..1dfb2e77898b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/ublk_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/ublk_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/ublk_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/ublk_drv.c</a></div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> #include &lt;linux/cdev.h&gt;</div><div class='del'>-#include &lt;linux/io_uring.h&gt;</div><div class='add'>+#include &lt;linux/io_uring/cmd.h&gt;</div><div class='ctx'> #include &lt;linux/blk-mq.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/mm.h&gt;</div><div class='hunk'>@@ -250,7 +250,7 @@ static int ublk_dev_param_zoned_apply(struct ublk_device *ub)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ublk_param_zoned *p = &amp;ub-&gt;params.zoned;</div><div class='ctx'> </div><div class='del'>-	disk_set_zoned(ub-&gt;ub_disk, BLK_ZONED_HM);</div><div class='add'>+	disk_set_zoned(ub-&gt;ub_disk);</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_ZONE_RESETALL, ub-&gt;ub_disk-&gt;queue);</div><div class='ctx'> 	blk_queue_required_elevator_features(ub-&gt;ub_disk-&gt;queue,</div><div class='ctx'> 					     ELEVATOR_F_ZBD_SEQ_WRITE);</div><div class='hunk'>@@ -893,12 +893,9 @@ static int ublk_map_io(const struct ublk_queue *ubq, const struct request *req,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ublk_need_map_req(req)) {</div><div class='ctx'> 		struct iov_iter iter;</div><div class='del'>-		struct iovec iov;</div><div class='ctx'> 		const int dir = ITER_DEST;</div><div class='ctx'> </div><div class='del'>-		import_single_range(dir, u64_to_user_ptr(io-&gt;addr), rq_bytes,</div><div class='del'>-				&amp;iov, &amp;iter);</div><div class='del'>-</div><div class='add'>+		import_ubuf(dir, u64_to_user_ptr(io-&gt;addr), rq_bytes, &amp;iter);</div><div class='ctx'> 		return ublk_copy_user_pages(req, 0, &amp;iter, dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	return rq_bytes;</div><div class='hunk'>@@ -915,13 +912,11 @@ static int ublk_unmap_io(const struct ublk_queue *ubq,</div><div class='ctx'> </div><div class='ctx'> 	if (ublk_need_unmap_req(req)) {</div><div class='ctx'> 		struct iov_iter iter;</div><div class='del'>-		struct iovec iov;</div><div class='ctx'> 		const int dir = ITER_SOURCE;</div><div class='ctx'> </div><div class='ctx'> 		WARN_ON_ONCE(io-&gt;res &gt; rq_bytes);</div><div class='ctx'> </div><div class='del'>-		import_single_range(dir, u64_to_user_ptr(io-&gt;addr), io-&gt;res,</div><div class='del'>-				&amp;iov, &amp;iter);</div><div class='add'>+		import_ubuf(dir, u64_to_user_ptr(io-&gt;addr), io-&gt;res, &amp;iter);</div><div class='ctx'> 		return ublk_copy_user_pages(req, 0, &amp;iter, dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	return rq_bytes;</div><div class='head'>diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c<br/>index d53d6aa8ee69..5bf98fd6a651 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/virtio_blk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/virtio_blk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/virtio_blk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/virtio_blk.c</a></div><div class='hunk'>@@ -367,8 +367,6 @@ static void virtblk_done(struct virtqueue *vq)</div><div class='ctx'> 				blk_mq_complete_request(req);</div><div class='ctx'> 			req_done = true;</div><div class='ctx'> 		}</div><div class='del'>-		if (unlikely(virtqueue_is_broken(vq)))</div><div class='del'>-			break;</div><div class='ctx'> 	} while (!virtqueue_enable_cb(vq));</div><div class='ctx'> </div><div class='ctx'> 	/* In case queue is stopped waiting for more buffers. */</div><div class='hunk'>@@ -722,52 +720,15 @@ fail_report:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void virtblk_revalidate_zones(struct virtio_blk *vblk)</div><div class='del'>-{</div><div class='del'>-	u8 model;</div><div class='del'>-</div><div class='del'>-	virtio_cread(vblk-&gt;vdev, struct virtio_blk_config,</div><div class='del'>-		     zoned.model, &amp;model);</div><div class='del'>-	switch (model) {</div><div class='del'>-	default:</div><div class='del'>-		dev_err(&amp;vblk-&gt;vdev-&gt;dev, "unknown zone model %d\n", model);</div><div class='del'>-		fallthrough;</div><div class='del'>-	case VIRTIO_BLK_Z_NONE:</div><div class='del'>-	case VIRTIO_BLK_Z_HA:</div><div class='del'>-		disk_set_zoned(vblk-&gt;disk, BLK_ZONED_NONE);</div><div class='del'>-		return;</div><div class='del'>-	case VIRTIO_BLK_Z_HM:</div><div class='del'>-		WARN_ON_ONCE(!vblk-&gt;zone_sectors);</div><div class='del'>-		if (!blk_revalidate_disk_zones(vblk-&gt;disk, NULL))</div><div class='del'>-			set_capacity_and_notify(vblk-&gt;disk, 0);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int virtblk_probe_zoned_device(struct virtio_device *vdev,</div><div class='ctx'> 				       struct virtio_blk *vblk,</div><div class='ctx'> 				       struct request_queue *q)</div><div class='ctx'> {</div><div class='ctx'> 	u32 v, wg;</div><div class='del'>-	u8 model;</div><div class='del'>-</div><div class='del'>-	virtio_cread(vdev, struct virtio_blk_config,</div><div class='del'>-		     zoned.model, &amp;model);</div><div class='del'>-</div><div class='del'>-	switch (model) {</div><div class='del'>-	case VIRTIO_BLK_Z_NONE:</div><div class='del'>-	case VIRTIO_BLK_Z_HA:</div><div class='del'>-		/* Present the host-aware device as non-zoned */</div><div class='del'>-		return 0;</div><div class='del'>-	case VIRTIO_BLK_Z_HM:</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		dev_err(&amp;vdev-&gt;dev, "unsupported zone model %d\n", model);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;vdev-&gt;dev, "probing host-managed zoned device\n");</div><div class='ctx'> </div><div class='del'>-	disk_set_zoned(vblk-&gt;disk, BLK_ZONED_HM);</div><div class='add'>+	disk_set_zoned(vblk-&gt;disk);</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_ZONE_RESETALL, q);</div><div class='ctx'> </div><div class='ctx'> 	virtio_cread(vdev, struct virtio_blk_config,</div><div class='hunk'>@@ -839,23 +800,12 @@ static int virtblk_probe_zoned_device(struct virtio_device *vdev,</div><div class='ctx'>  */</div><div class='ctx'> #define virtblk_report_zones       NULL</div><div class='ctx'> </div><div class='del'>-static inline void virtblk_revalidate_zones(struct virtio_blk *vblk)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline int virtblk_probe_zoned_device(struct virtio_device *vdev,</div><div class='ctx'> 			struct virtio_blk *vblk, struct request_queue *q)</div><div class='ctx'> {</div><div class='del'>-	u8 model;</div><div class='del'>-</div><div class='del'>-	virtio_cread(vdev, struct virtio_blk_config, zoned.model, &amp;model);</div><div class='del'>-	if (model == VIRTIO_BLK_Z_HM) {</div><div class='del'>-		dev_err(&amp;vdev-&gt;dev,</div><div class='del'>-			"virtio_blk: zoned devices are not supported");</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	dev_err(&amp;vdev-&gt;dev,</div><div class='add'>+		"virtio_blk: zoned devices are not supported");</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> #endif /* CONFIG_BLK_DEV_ZONED */</div><div class='ctx'> </div><div class='hunk'>@@ -1005,7 +955,6 @@ static void virtblk_config_changed_work(struct work_struct *work)</div><div class='ctx'> 	struct virtio_blk *vblk =</div><div class='ctx'> 		container_of(work, struct virtio_blk, config_work);</div><div class='ctx'> </div><div class='del'>-	virtblk_revalidate_zones(vblk);</div><div class='ctx'> 	virtblk_update_capacity(vblk, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1019,12 +968,12 @@ static void virtblk_config_changed(struct virtio_device *vdev)</div><div class='ctx'> static int init_vq(struct virtio_blk *vblk)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='del'>-	int i;</div><div class='add'>+	unsigned short i;</div><div class='ctx'> 	vq_callback_t **callbacks;</div><div class='ctx'> 	const char **names;</div><div class='ctx'> 	struct virtqueue **vqs;</div><div class='ctx'> 	unsigned short num_vqs;</div><div class='del'>-	unsigned int num_poll_vqs;</div><div class='add'>+	unsigned short num_poll_vqs;</div><div class='ctx'> 	struct virtio_device *vdev = vblk-&gt;vdev;</div><div class='ctx'> 	struct irq_affinity desc = { 0, };</div><div class='ctx'> </div><div class='hunk'>@@ -1068,13 +1017,13 @@ static int init_vq(struct virtio_blk *vblk)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_vqs - num_poll_vqs; i++) {</div><div class='ctx'> 		callbacks[i] = virtblk_done;</div><div class='del'>-		snprintf(vblk-&gt;vqs[i].name, VQ_NAME_LEN, "req.%d", i);</div><div class='add'>+		snprintf(vblk-&gt;vqs[i].name, VQ_NAME_LEN, "req.%u", i);</div><div class='ctx'> 		names[i] = vblk-&gt;vqs[i].name;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (; i &lt; num_vqs; i++) {</div><div class='ctx'> 		callbacks[i] = NULL;</div><div class='del'>-		snprintf(vblk-&gt;vqs[i].name, VQ_NAME_LEN, "req_poll.%d", i);</div><div class='add'>+		snprintf(vblk-&gt;vqs[i].name, VQ_NAME_LEN, "req_poll.%u", i);</div><div class='ctx'> 		names[i] = vblk-&gt;vqs[i].name;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1570,9 +1519,26 @@ static int virtblk_probe(struct virtio_device *vdev)</div><div class='ctx'> 	 * placed after the virtio_device_ready() call above.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (virtio_has_feature(vdev, VIRTIO_BLK_F_ZONED)) {</div><div class='del'>-		err = virtblk_probe_zoned_device(vdev, vblk, q);</div><div class='del'>-		if (err)</div><div class='add'>+		u8 model;</div><div class='add'>+</div><div class='add'>+		virtio_cread(vdev, struct virtio_blk_config, zoned.model,</div><div class='add'>+				&amp;model);</div><div class='add'>+		switch (model) {</div><div class='add'>+		case VIRTIO_BLK_Z_NONE:</div><div class='add'>+		case VIRTIO_BLK_Z_HA:</div><div class='add'>+			/* Present the host-aware device as non-zoned */</div><div class='add'>+			break;</div><div class='add'>+		case VIRTIO_BLK_Z_HM:</div><div class='add'>+			err = virtblk_probe_zoned_device(vdev, vblk, q);</div><div class='add'>+			if (err)</div><div class='add'>+				goto out_cleanup_disk;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			dev_err(&amp;vdev-&gt;dev, "unsupported zone model %d\n",</div><div class='add'>+				model);</div><div class='add'>+			err = -EINVAL;</div><div class='ctx'> 			goto out_cleanup_disk;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = device_add_disk(&amp;vdev-&gt;dev, vblk-&gt;disk, virtblk_attr_groups);</div><div class='head'>diff --git a/drivers/block/xen-blkback/common.h b/drivers/block/xen-blkback/common.h<br/>index 5ff50e76cee5..1432c83183d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/xen-blkback/common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/xen-blkback/common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/xen-blkback/common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/xen-blkback/common.h</a></div><div class='hunk'>@@ -132,7 +132,7 @@ struct blkif_x86_32_request {</div><div class='ctx'> struct blkif_x86_64_request_rw {</div><div class='ctx'> 	uint8_t        nr_segments;  /* number of segments                   */</div><div class='ctx'> 	blkif_vdev_t   handle;       /* only for read/write requests         */</div><div class='del'>-	uint32_t       _pad1;        /* offsetof(blkif_reqest..,u.rw.id)==8  */</div><div class='add'>+	uint32_t       _pad1;        /* offsetof(blkif_request..,u.rw.id)==8 */</div><div class='ctx'> 	uint64_t       id;</div><div class='ctx'> 	blkif_sector_t sector_number;/* start sector idx on disk (r/w only)  */</div><div class='ctx'> 	struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];</div><div class='head'>diff --git a/drivers/block/zram/Kconfig b/drivers/block/zram/Kconfig<br/>index 0386b7da02aa..7b29cce60ab2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/zram/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/zram/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/zram/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/Kconfig</a></div><div class='hunk'>@@ -59,8 +59,8 @@ config ZRAM_WRITEBACK</div><div class='ctx'>        bool "Write back incompressible or idle page to backing device"</div><div class='ctx'>        depends on ZRAM</div><div class='ctx'>        help</div><div class='del'>-	 With incompressible page, there is no memory saving to keep it</div><div class='del'>-	 in memory. Instead, write it out to backing device.</div><div class='add'>+	 This lets zram entries (incompressible or idle pages) be written</div><div class='add'>+	 back to a backing device, helping save memory.</div><div class='ctx'> 	 For this feature, admin should set up backing device via</div><div class='ctx'> 	 /sys/block/zramX/backing_dev.</div><div class='ctx'> </div><div class='hunk'>@@ -69,9 +69,18 @@ config ZRAM_WRITEBACK</div><div class='ctx'> </div><div class='ctx'> 	 See Documentation/admin-guide/blockdev/zram.rst for more information.</div><div class='ctx'> </div><div class='add'>+config ZRAM_TRACK_ENTRY_ACTIME</div><div class='add'>+	bool "Track access time of zram entries"</div><div class='add'>+	depends on ZRAM</div><div class='add'>+	help</div><div class='add'>+	  With this feature zram tracks access time of every stored</div><div class='add'>+	  entry (page), which can be used for a more fine grained IDLE</div><div class='add'>+	  pages writeback.</div><div class='add'>+</div><div class='ctx'> config ZRAM_MEMORY_TRACKING</div><div class='ctx'> 	bool "Track zRam block status"</div><div class='ctx'> 	depends on ZRAM &amp;&amp; DEBUG_FS</div><div class='add'>+	select ZRAM_TRACK_ENTRY_ACTIME</div><div class='ctx'> 	help</div><div class='ctx'> 	  With this feature, admin can track the state of allocated blocks</div><div class='ctx'> 	  of zRAM. Admin could see the information via</div><div class='hunk'>@@ -86,4 +95,4 @@ config ZRAM_MULTI_COMP</div><div class='ctx'> 	  This will enable multi-compression streams, so that ZRAM can</div><div class='ctx'> 	  re-compress pages using a potentially slower but more effective</div><div class='ctx'> 	  compression algorithm. Note, that IDLE page recompression</div><div class='del'>-	  requires ZRAM_MEMORY_TRACKING.</div><div class='add'>+	  requires ZRAM_TRACK_ENTRY_ACTIME.</div><div class='head'>diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c<br/>index d77d3664ca08..6772e0c654fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/zram/zram_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/zram/zram_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/zram/zram_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/zram_drv.c</a></div><div class='hunk'>@@ -174,6 +174,14 @@ static inline u32 zram_get_priority(struct zram *zram, u32 index)</div><div class='ctx'> 	return prio &amp; ZRAM_COMP_PRIORITY_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void zram_accessed(struct zram *zram, u32 index)</div><div class='add'>+{</div><div class='add'>+	zram_clear_flag(zram, index, ZRAM_IDLE);</div><div class='add'>+#ifdef CONFIG_ZRAM_TRACK_ENTRY_ACTIME</div><div class='add'>+	zram-&gt;table[index].ac_time = ktime_get_boottime();</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void update_used_max(struct zram *zram,</div><div class='ctx'> 					const unsigned long pages)</div><div class='ctx'> {</div><div class='hunk'>@@ -293,8 +301,9 @@ static void mark_idle(struct zram *zram, ktime_t cutoff)</div><div class='ctx'> 		zram_slot_lock(zram, index);</div><div class='ctx'> 		if (zram_allocated(zram, index) &amp;&amp;</div><div class='ctx'> 				!zram_test_flag(zram, index, ZRAM_UNDER_WB)) {</div><div class='del'>-#ifdef CONFIG_ZRAM_MEMORY_TRACKING</div><div class='del'>-			is_idle = !cutoff || ktime_after(cutoff, zram-&gt;table[index].ac_time);</div><div class='add'>+#ifdef CONFIG_ZRAM_TRACK_ENTRY_ACTIME</div><div class='add'>+			is_idle = !cutoff || ktime_after(cutoff,</div><div class='add'>+							 zram-&gt;table[index].ac_time);</div><div class='ctx'> #endif</div><div class='ctx'> 			if (is_idle)</div><div class='ctx'> 				zram_set_flag(zram, index, ZRAM_IDLE);</div><div class='hunk'>@@ -317,7 +326,7 @@ static ssize_t idle_store(struct device *dev,</div><div class='ctx'> 		 */</div><div class='ctx'> 		u64 age_sec;</div><div class='ctx'> </div><div class='del'>-		if (IS_ENABLED(CONFIG_ZRAM_MEMORY_TRACKING) &amp;&amp; !kstrtoull(buf, 0, &amp;age_sec))</div><div class='add'>+		if (IS_ENABLED(CONFIG_ZRAM_TRACK_ENTRY_ACTIME) &amp;&amp; !kstrtoull(buf, 0, &amp;age_sec))</div><div class='ctx'> 			cutoff_time = ktime_sub(ktime_get_boottime(),</div><div class='ctx'> 					ns_to_ktime(age_sec * NSEC_PER_SEC));</div><div class='ctx'> 		else</div><div class='hunk'>@@ -841,12 +850,6 @@ static void zram_debugfs_destroy(void)</div><div class='ctx'> 	debugfs_remove_recursive(zram_debugfs_root);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void zram_accessed(struct zram *zram, u32 index)</div><div class='del'>-{</div><div class='del'>-	zram_clear_flag(zram, index, ZRAM_IDLE);</div><div class='del'>-	zram-&gt;table[index].ac_time = ktime_get_boottime();</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static ssize_t read_block_state(struct file *file, char __user *buf,</div><div class='ctx'> 				size_t count, loff_t *ppos)</div><div class='ctx'> {</div><div class='hunk'>@@ -930,10 +933,6 @@ static void zram_debugfs_unregister(struct zram *zram)</div><div class='ctx'> #else</div><div class='ctx'> static void zram_debugfs_create(void) {};</div><div class='ctx'> static void zram_debugfs_destroy(void) {};</div><div class='del'>-static void zram_accessed(struct zram *zram, u32 index)</div><div class='del'>-{</div><div class='del'>-	zram_clear_flag(zram, index, ZRAM_IDLE);</div><div class='del'>-};</div><div class='ctx'> static void zram_debugfs_register(struct zram *zram) {};</div><div class='ctx'> static void zram_debugfs_unregister(struct zram *zram) {};</div><div class='ctx'> #endif</div><div class='hunk'>@@ -1254,7 +1253,7 @@ static void zram_free_page(struct zram *zram, size_t index)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long handle;</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_ZRAM_MEMORY_TRACKING</div><div class='add'>+#ifdef CONFIG_ZRAM_TRACK_ENTRY_ACTIME</div><div class='ctx'> 	zram-&gt;table[index].ac_time = 0;</div><div class='ctx'> #endif</div><div class='ctx'> 	if (zram_test_flag(zram, index, ZRAM_IDLE))</div><div class='hunk'>@@ -1322,9 +1321,9 @@ static int zram_read_from_zspool(struct zram *zram, struct page *page,</div><div class='ctx'> 		void *mem;</div><div class='ctx'> </div><div class='ctx'> 		value = handle ? zram_get_element(zram, index) : 0;</div><div class='del'>-		mem = kmap_atomic(page);</div><div class='add'>+		mem = kmap_local_page(page);</div><div class='ctx'> 		zram_fill_page(mem, PAGE_SIZE, value);</div><div class='del'>-		kunmap_atomic(mem);</div><div class='add'>+		kunmap_local(mem);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1337,14 +1336,14 @@ static int zram_read_from_zspool(struct zram *zram, struct page *page,</div><div class='ctx'> </div><div class='ctx'> 	src = zs_map_object(zram-&gt;mem_pool, handle, ZS_MM_RO);</div><div class='ctx'> 	if (size == PAGE_SIZE) {</div><div class='del'>-		dst = kmap_atomic(page);</div><div class='add'>+		dst = kmap_local_page(page);</div><div class='ctx'> 		memcpy(dst, src, PAGE_SIZE);</div><div class='del'>-		kunmap_atomic(dst);</div><div class='add'>+		kunmap_local(dst);</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	} else {</div><div class='del'>-		dst = kmap_atomic(page);</div><div class='add'>+		dst = kmap_local_page(page);</div><div class='ctx'> 		ret = zcomp_decompress(zstrm, src, size, dst);</div><div class='del'>-		kunmap_atomic(dst);</div><div class='add'>+		kunmap_local(dst);</div><div class='ctx'> 		zcomp_stream_put(zram-&gt;comps[prio]);</div><div class='ctx'> 	}</div><div class='ctx'> 	zs_unmap_object(zram-&gt;mem_pool, handle);</div><div class='hunk'>@@ -1417,21 +1416,21 @@ static int zram_write_page(struct zram *zram, struct page *page, u32 index)</div><div class='ctx'> 	unsigned long element = 0;</div><div class='ctx'> 	enum zram_pageflags flags = 0;</div><div class='ctx'> </div><div class='del'>-	mem = kmap_atomic(page);</div><div class='add'>+	mem = kmap_local_page(page);</div><div class='ctx'> 	if (page_same_filled(mem, &amp;element)) {</div><div class='del'>-		kunmap_atomic(mem);</div><div class='add'>+		kunmap_local(mem);</div><div class='ctx'> 		/* Free memory associated with this sector now. */</div><div class='ctx'> 		flags = ZRAM_SAME;</div><div class='ctx'> 		atomic64_inc(&amp;zram-&gt;stats.same_pages);</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='del'>-	kunmap_atomic(mem);</div><div class='add'>+	kunmap_local(mem);</div><div class='ctx'> </div><div class='ctx'> compress_again:</div><div class='ctx'> 	zstrm = zcomp_stream_get(zram-&gt;comps[ZRAM_PRIMARY_COMP]);</div><div class='del'>-	src = kmap_atomic(page);</div><div class='add'>+	src = kmap_local_page(page);</div><div class='ctx'> 	ret = zcomp_compress(zstrm, src, &amp;comp_len);</div><div class='del'>-	kunmap_atomic(src);</div><div class='add'>+	kunmap_local(src);</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(ret)) {</div><div class='ctx'> 		zcomp_stream_put(zram-&gt;comps[ZRAM_PRIMARY_COMP]);</div><div class='hunk'>@@ -1495,10 +1494,10 @@ compress_again:</div><div class='ctx'> </div><div class='ctx'> 	src = zstrm-&gt;buffer;</div><div class='ctx'> 	if (comp_len == PAGE_SIZE)</div><div class='del'>-		src = kmap_atomic(page);</div><div class='add'>+		src = kmap_local_page(page);</div><div class='ctx'> 	memcpy(dst, src, comp_len);</div><div class='ctx'> 	if (comp_len == PAGE_SIZE)</div><div class='del'>-		kunmap_atomic(src);</div><div class='add'>+		kunmap_local(src);</div><div class='ctx'> </div><div class='ctx'> 	zcomp_stream_put(zram-&gt;comps[ZRAM_PRIMARY_COMP]);</div><div class='ctx'> 	zs_unmap_object(zram-&gt;mem_pool, handle);</div><div class='hunk'>@@ -1615,9 +1614,9 @@ static int zram_recompress(struct zram *zram, u32 index, struct page *page,</div><div class='ctx'> </div><div class='ctx'> 		num_recomps++;</div><div class='ctx'> 		zstrm = zcomp_stream_get(zram-&gt;comps[prio]);</div><div class='del'>-		src = kmap_atomic(page);</div><div class='add'>+		src = kmap_local_page(page);</div><div class='ctx'> 		ret = zcomp_compress(zstrm, src, &amp;comp_len_new);</div><div class='del'>-		kunmap_atomic(src);</div><div class='add'>+		kunmap_local(src);</div><div class='ctx'> </div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			zcomp_stream_put(zram-&gt;comps[prio]);</div><div class='hunk'>@@ -2227,7 +2226,6 @@ static int zram_add(void)</div><div class='ctx'> 					ZRAM_LOGICAL_BLOCK_SIZE);</div><div class='ctx'> 	blk_queue_io_min(zram-&gt;disk-&gt;queue, PAGE_SIZE);</div><div class='ctx'> 	blk_queue_io_opt(zram-&gt;disk-&gt;queue, PAGE_SIZE);</div><div class='del'>-	zram-&gt;disk-&gt;queue-&gt;limits.discard_granularity = PAGE_SIZE;</div><div class='ctx'> 	blk_queue_max_discard_sectors(zram-&gt;disk-&gt;queue, UINT_MAX);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='head'>diff --git a/drivers/block/zram/zram_drv.h b/drivers/block/zram/zram_drv.h<br/>index d090753f97be..3b94d12f41b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/block/zram/zram_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/block/zram/zram_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/block/zram/zram_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/block/zram/zram_drv.h</a></div><div class='hunk'>@@ -69,7 +69,7 @@ struct zram_table_entry {</div><div class='ctx'> 		unsigned long element;</div><div class='ctx'> 	};</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-#ifdef CONFIG_ZRAM_MEMORY_TRACKING</div><div class='add'>+#ifdef CONFIG_ZRAM_TRACK_ENTRY_ACTIME</div><div class='ctx'> 	ktime_t ac_time;</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/bluetooth/btintel.c b/drivers/bluetooth/btintel.c<br/>index 2462796a512a..cdc5c08824a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/btintel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/btintel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/btintel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btintel.c</a></div><div class='hunk'>@@ -535,6 +535,8 @@ static int btintel_version_info_tlv(struct hci_dev *hdev,</div><div class='ctx'> 	bt_dev_info(hdev, "%s timestamp %u.%u buildtype %u build %u", variant,</div><div class='ctx'> 		    2000 + (version-&gt;timestamp &gt;&gt; 8), version-&gt;timestamp &amp; 0xff,</div><div class='ctx'> 		    version-&gt;build_type, version-&gt;build_num);</div><div class='add'>+	if (version-&gt;img_type == 0x03)</div><div class='add'>+		bt_dev_info(hdev, "Firmware SHA1: 0x%8.8x", version-&gt;git_sha1);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -630,6 +632,9 @@ static int btintel_parse_version_tlv(struct hci_dev *hdev,</div><div class='ctx'> 			memcpy(&amp;version-&gt;otp_bd_addr, tlv-&gt;val,</div><div class='ctx'> 							sizeof(bdaddr_t));</div><div class='ctx'> 			break;</div><div class='add'>+		case INTEL_TLV_GIT_SHA1:</div><div class='add'>+			version-&gt;git_sha1 = get_unaligned_le32(tlv-&gt;val);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			/* Ignore rest of information */</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/bluetooth/btintel.h b/drivers/bluetooth/btintel.h<br/>index 3a2d5b4219dd..d19fcdb9ff0b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/btintel.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/btintel.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/btintel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btintel.h</a></div><div class='hunk'>@@ -41,7 +41,8 @@ enum {</div><div class='ctx'> 	INTEL_TLV_LIMITED_CCE,</div><div class='ctx'> 	INTEL_TLV_SBE_TYPE,</div><div class='ctx'> 	INTEL_TLV_OTP_BDADDR,</div><div class='del'>-	INTEL_TLV_UNLOCKED_STATE</div><div class='add'>+	INTEL_TLV_UNLOCKED_STATE,</div><div class='add'>+	INTEL_TLV_GIT_SHA1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct intel_tlv {</div><div class='hunk'>@@ -69,6 +70,7 @@ struct intel_version_tlv {</div><div class='ctx'> 	u8	min_fw_build_yy;</div><div class='ctx'> 	u8	limited_cce;</div><div class='ctx'> 	u8	sbe_type;</div><div class='add'>+	u32	git_sha1;</div><div class='ctx'> 	bdaddr_t otp_bd_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/bluetooth/btmtkuart.c b/drivers/bluetooth/btmtkuart.c<br/>index 935feab815d9..3c84fcbda01a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/btmtkuart.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/btmtkuart.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/btmtkuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btmtkuart.c</a></div><div class='hunk'>@@ -336,7 +336,7 @@ mtk_stp_split(struct btmtkuart_dev *bdev, const unsigned char *data, int count,</div><div class='ctx'> 	return data;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count)</div><div class='add'>+static void btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct btmtkuart_dev *bdev = hci_get_drvdata(hdev);</div><div class='ctx'> 	const unsigned char *p_left = data, *p_h4;</div><div class='hunk'>@@ -375,25 +375,20 @@ static int btmtkuart_recv(struct hci_dev *hdev, const u8 *data, size_t count)</div><div class='ctx'> 			bt_dev_err(bdev-&gt;hdev,</div><div class='ctx'> 				   "Frame reassembly failed (%d)", err);</div><div class='ctx'> 			bdev-&gt;rx_skb = NULL;</div><div class='del'>-			return err;</div><div class='add'>+			return;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		sz_left -= sz_h4;</div><div class='ctx'> 		p_left += sz_h4;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int btmtkuart_receive_buf(struct serdev_device *serdev, const u8 *data,</div><div class='del'>-				 size_t count)</div><div class='add'>+static ssize_t btmtkuart_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				     const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct btmtkuart_dev *bdev = serdev_device_get_drvdata(serdev);</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='del'>-	err = btmtkuart_recv(bdev-&gt;hdev, data, count);</div><div class='del'>-	if (err &lt; 0)</div><div class='del'>-		return err;</div><div class='add'>+	btmtkuart_recv(bdev-&gt;hdev, data, count);</div><div class='ctx'> </div><div class='ctx'> 	bdev-&gt;hdev-&gt;stat.byte_rx += count;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/bluetooth/btnxpuart.c b/drivers/bluetooth/btnxpuart.c<br/>index b7e66b7ac570..1d592ac413d1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/btnxpuart.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/btnxpuart.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/btnxpuart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btnxpuart.c</a></div><div class='hunk'>@@ -1264,8 +1264,8 @@ static const struct h4_recv_pkt nxp_recv_pkts[] = {</div><div class='ctx'> 	{ NXP_RECV_FW_REQ_V3,   .recv = nxp_recv_fw_req_v3 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int btnxpuart_receive_buf(struct serdev_device *serdev, const u8 *data,</div><div class='del'>-				 size_t count)</div><div class='add'>+static ssize_t btnxpuart_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				     const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct btnxpuart_dev *nxpdev = serdev_device_get_drvdata(serdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1276,11 +1276,9 @@ static int btnxpuart_receive_buf(struct serdev_device *serdev, const u8 *data,</div><div class='ctx'> 	if (IS_ERR(nxpdev-&gt;rx_skb)) {</div><div class='ctx'> 		int err = PTR_ERR(nxpdev-&gt;rx_skb);</div><div class='ctx'> 		/* Safe to ignore out-of-sync bootloader signatures */</div><div class='del'>-		if (is_fw_downloading(nxpdev))</div><div class='del'>-			return count;</div><div class='del'>-		bt_dev_err(nxpdev-&gt;hdev, "Frame reassembly failed (%d)", err);</div><div class='del'>-		nxpdev-&gt;rx_skb = NULL;</div><div class='del'>-		return err;</div><div class='add'>+		if (!is_fw_downloading(nxpdev))</div><div class='add'>+			bt_dev_err(nxpdev-&gt;hdev, "Frame reassembly failed (%d)", err);</div><div class='add'>+		return count;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!is_fw_downloading(nxpdev))</div><div class='ctx'> 		nxpdev-&gt;hdev-&gt;stat.byte_rx += count;</div><div class='head'>diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c<br/>index b8e9de887b5d..d31edad7a056 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/btusb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/btusb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/btusb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/btusb.c</a></div><div class='hunk'>@@ -550,6 +550,8 @@ static const struct usb_device_id quirks_table[] = {</div><div class='ctx'> 						     BTUSB_WIDEBAND_SPEECH },</div><div class='ctx'> 	{ USB_DEVICE(0x13d3, 0x3571), .driver_info = BTUSB_REALTEK |</div><div class='ctx'> 						     BTUSB_WIDEBAND_SPEECH },</div><div class='add'>+	{ USB_DEVICE(0x13d3, 0x3572), .driver_info = BTUSB_REALTEK |</div><div class='add'>+						     BTUSB_WIDEBAND_SPEECH },</div><div class='ctx'> </div><div class='ctx'> 	/* Realtek Bluetooth devices */</div><div class='ctx'> 	{ USB_VENDOR_AND_INTERFACE_INFO(0x0bda, 0xe0, 0x01, 0x01),</div><div class='hunk'>@@ -4629,6 +4631,10 @@ static int btusb_suspend(struct usb_interface *intf, pm_message_t message)</div><div class='ctx'> </div><div class='ctx'> 	BT_DBG("intf %p", intf);</div><div class='ctx'> </div><div class='add'>+	/* Don't suspend if there are connections */</div><div class='add'>+	if (hci_conn_count(data-&gt;hdev))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='ctx'> 	if (data-&gt;suspend_count++)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -4790,10 +4796,8 @@ static struct usb_driver btusb_driver = {</div><div class='ctx'> 	.disable_hub_initiated_lpm = 1,</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DEV_COREDUMP</div><div class='del'>-	.drvwrap = {</div><div class='del'>-		.driver = {</div><div class='del'>-			.coredump = btusb_coredump,</div><div class='del'>-		},</div><div class='add'>+	.driver = {</div><div class='add'>+		.coredump = btusb_coredump,</div><div class='ctx'> 	},</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c<br/>index 067e248e3599..94b8c406f0c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_qca.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/hci_qca.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_qca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_qca.c</a></div><div class='hunk'>@@ -1815,6 +1815,24 @@ static void hci_coredump_qca(struct hci_dev *hdev)</div><div class='ctx'> 	kfree_skb(skb);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int qca_get_data_path_id(struct hci_dev *hdev, __u8 *data_path_id)</div><div class='add'>+{</div><div class='add'>+	/* QCA uses 1 as non-HCI data path id for HFP */</div><div class='add'>+	*data_path_id = 1;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int qca_configure_hfp_offload(struct hci_dev *hdev)</div><div class='add'>+{</div><div class='add'>+	bt_dev_info(hdev, "HFP non-HCI data transport is supported");</div><div class='add'>+	hdev-&gt;get_data_path_id = qca_get_data_path_id;</div><div class='add'>+	/* Do not need to send HCI_Configure_Data_Path to configure non-HCI</div><div class='add'>+	 * data transport path for QCA controllers, so set below field as NULL.</div><div class='add'>+	 */</div><div class='add'>+	hdev-&gt;get_codec_config_data = NULL;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int qca_setup(struct hci_uart *hu)</div><div class='ctx'> {</div><div class='ctx'> 	struct hci_dev *hdev = hu-&gt;hdev;</div><div class='hunk'>@@ -1969,6 +1987,10 @@ out:</div><div class='ctx'> 		hu-&gt;hdev-&gt;set_bdaddr = qca_set_bdaddr_rome;</div><div class='ctx'> 	else</div><div class='ctx'> 		hu-&gt;hdev-&gt;set_bdaddr = qca_set_bdaddr;</div><div class='add'>+</div><div class='add'>+	if (soc_type == QCA_QCA2066)</div><div class='add'>+		qca_configure_hfp_offload(hdev);</div><div class='add'>+</div><div class='ctx'> 	qca-&gt;fw_version = le16_to_cpu(ver.patch_ver);</div><div class='ctx'> 	qca-&gt;controller_id = le16_to_cpu(ver.rom_ver);</div><div class='ctx'> 	hci_devcd_register(hdev, hci_coredump_qca, qca_dmp_hdr, NULL);</div><div class='hunk'>@@ -2039,6 +2061,7 @@ static const struct qca_device_data qca_soc_data_wcn3998 __maybe_unused = {</div><div class='ctx'> static const struct qca_device_data qca_soc_data_qca2066 __maybe_unused = {</div><div class='ctx'> 	.soc_type = QCA_QCA2066,</div><div class='ctx'> 	.num_vregs = 0,</div><div class='add'>+	.capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct qca_device_data qca_soc_data_qca6390 __maybe_unused = {</div><div class='head'>diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c<br/>index f16fd79bc02b..39c8b567da3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_serdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/hci_serdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_serdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_serdev.c</a></div><div class='hunk'>@@ -271,8 +271,8 @@ static void hci_uart_write_wakeup(struct serdev_device *serdev)</div><div class='ctx'>  *</div><div class='ctx'>  * Return: number of processed bytes</div><div class='ctx'>  */</div><div class='del'>-static int hci_uart_receive_buf(struct serdev_device *serdev, const u8 *data,</div><div class='del'>-				   size_t count)</div><div class='add'>+static ssize_t hci_uart_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				    const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct hci_uart *hu = serdev_device_get_drvdata(serdev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c<br/>index f3892e9ce800..572d68d52965 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_vhci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bluetooth/hci_vhci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bluetooth/hci_vhci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bluetooth/hci_vhci.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;asm/unaligned.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/atomic.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='hunk'>@@ -44,6 +45,7 @@ struct vhci_data {</div><div class='ctx'> 	bool wakeup;</div><div class='ctx'> 	__u16 msft_opcode;</div><div class='ctx'> 	bool aosp_capable;</div><div class='add'>+	atomic_t initialized;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int vhci_open_dev(struct hci_dev *hdev)</div><div class='hunk'>@@ -75,11 +77,10 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)</div><div class='ctx'> </div><div class='ctx'> 	memcpy(skb_push(skb, 1), &amp;hci_skb_pkt_type(skb), 1);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;data-&gt;open_mutex);</div><div class='ctx'> 	skb_queue_tail(&amp;data-&gt;readq, skb);</div><div class='del'>-	mutex_unlock(&amp;data-&gt;open_mutex);</div><div class='ctx'> </div><div class='del'>-	wake_up_interruptible(&amp;data-&gt;read_wait);</div><div class='add'>+	if (atomic_read(&amp;data-&gt;initialized))</div><div class='add'>+		wake_up_interruptible(&amp;data-&gt;read_wait);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -464,7 +465,8 @@ static int __vhci_create_device(struct vhci_data *data, __u8 opcode)</div><div class='ctx'> 	skb_put_u8(skb, 0xff);</div><div class='ctx'> 	skb_put_u8(skb, opcode);</div><div class='ctx'> 	put_unaligned_le16(hdev-&gt;id, skb_put(skb, 2));</div><div class='del'>-	skb_queue_tail(&amp;data-&gt;readq, skb);</div><div class='add'>+	skb_queue_head(&amp;data-&gt;readq, skb);</div><div class='add'>+	atomic_inc(&amp;data-&gt;initialized);</div><div class='ctx'> </div><div class='ctx'> 	wake_up_interruptible(&amp;data-&gt;read_wait);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c<br/>index 2f6d5002e43d..78b96cd63de9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/fsl-mc/fsl-mc-bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/fsl-mc/fsl-mc-bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/fsl-mc/fsl-mc-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/fsl-mc/fsl-mc-bus.c</a></div><div class='hunk'>@@ -1167,14 +1167,11 @@ error_cleanup_mc_io:</div><div class='ctx'>  * fsl_mc_bus_remove - callback invoked when the root MC bus is being</div><div class='ctx'>  * removed</div><div class='ctx'>  */</div><div class='del'>-static int fsl_mc_bus_remove(struct platform_device *pdev)</div><div class='add'>+static void fsl_mc_bus_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fsl_mc *mc = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct fsl_mc_io *mc_io;</div><div class='ctx'> </div><div class='del'>-	if (!fsl_mc_is_root_dprc(&amp;mc-&gt;root_mc_bus_dev-&gt;dev))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	mc_io = mc-&gt;root_mc_bus_dev-&gt;mc_io;</div><div class='ctx'> 	fsl_mc_device_remove(mc-&gt;root_mc_bus_dev);</div><div class='ctx'> 	fsl_destroy_mc_io(mc_io);</div><div class='hunk'>@@ -1190,13 +1187,6 @@ static int fsl_mc_bus_remove(struct platform_device *pdev)</div><div class='ctx'> 		       (GCR1_P1_STOP | GCR1_P2_STOP),</div><div class='ctx'> 		       mc-&gt;fsl_mc_regs + FSL_MC_GCR1);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void fsl_mc_bus_shutdown(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	fsl_mc_bus_remove(pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id fsl_mc_bus_match_table[] = {</div><div class='hunk'>@@ -1220,8 +1210,8 @@ static struct platform_driver fsl_mc_bus_driver = {</div><div class='ctx'> 		   .acpi_match_table = fsl_mc_bus_acpi_match_table,</div><div class='ctx'> 		   },</div><div class='ctx'> 	.probe = fsl_mc_bus_probe,</div><div class='del'>-	.remove = fsl_mc_bus_remove,</div><div class='del'>-	.shutdown = fsl_mc_bus_shutdown,</div><div class='add'>+	.remove_new = fsl_mc_bus_remove,</div><div class='add'>+	.shutdown = fsl_mc_bus_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int fsl_mc_bus_notifier(struct notifier_block *nb,</div><div class='head'>diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c<br/>index cdc4e38c113e..09340adbacc2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/hisi_lpc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/hisi_lpc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/hisi_lpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/hisi_lpc.c</a></div><div class='hunk'>@@ -657,7 +657,7 @@ static int hisi_lpc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hisi_lpc_remove(struct platform_device *pdev)</div><div class='add'>+static void hisi_lpc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct hisi_lpc_dev *lpcdev = dev_get_drvdata(dev);</div><div class='hunk'>@@ -669,8 +669,6 @@ static int hisi_lpc_remove(struct platform_device *pdev)</div><div class='ctx'> 		of_platform_depopulate(dev);</div><div class='ctx'> </div><div class='ctx'> 	logic_pio_unregister_range(range);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id hisi_lpc_of_match[] = {</div><div class='hunk'>@@ -691,6 +689,6 @@ static struct platform_driver hisi_lpc_driver = {</div><div class='ctx'> 		.acpi_match_table = hisi_lpc_acpi_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = hisi_lpc_probe,</div><div class='del'>-	.remove = hisi_lpc_remove,</div><div class='add'>+	.remove_new = hisi_lpc_remove,</div><div class='ctx'> };</div><div class='ctx'> builtin_platform_driver(hisi_lpc_driver);</div><div class='head'>diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c<br/>index 42c9386a7b42..6b5da73c8541 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/imx-weim.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/imx-weim.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/imx-weim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/imx-weim.c</a></div><div class='hunk'>@@ -11,7 +11,10 @@</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/of_address.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/syscon.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/syscon/imx6q-iomuxc-gpr.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='hunk'>@@ -202,9 +205,7 @@ static int weim_timing_setup(struct device *dev, struct device_node *np,</div><div class='ctx'> </div><div class='ctx'> static int weim_parse_dt(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *of_id = of_match_device(weim_id_table,</div><div class='del'>-							   &amp;pdev-&gt;dev);</div><div class='del'>-	const struct imx_weim_devtype *devtype = of_id-&gt;data;</div><div class='add'>+	const struct imx_weim_devtype *devtype = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> 	int ret = 0, have_child = 0;</div><div class='ctx'> 	struct device_node *child;</div><div class='ctx'> 	struct weim_priv *priv;</div><div class='head'>diff --git a/drivers/bus/mhi/ep/internal.h b/drivers/bus/mhi/ep/internal.h<br/>index a2125fa5fe2f..577965f95fda 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/internal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/ep/internal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/internal.h</a></div><div class='hunk'>@@ -126,6 +126,7 @@ struct mhi_ep_ring {</div><div class='ctx'> 	union mhi_ep_ring_ctx *ring_ctx;</div><div class='ctx'> 	struct mhi_ring_element *ring_cache;</div><div class='ctx'> 	enum mhi_ep_ring_type type;</div><div class='add'>+	struct delayed_work intmodt_work;</div><div class='ctx'> 	u64 rbase;</div><div class='ctx'> 	size_t rd_offset;</div><div class='ctx'> 	size_t wr_offset;</div><div class='hunk'>@@ -135,7 +136,9 @@ struct mhi_ep_ring {</div><div class='ctx'> 	u32 ch_id;</div><div class='ctx'> 	u32 er_index;</div><div class='ctx'> 	u32 irq_vector;</div><div class='add'>+	u32 intmodt;</div><div class='ctx'> 	bool started;</div><div class='add'>+	bool irq_pending;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mhi_ep_cmd {</div><div class='hunk'>@@ -159,6 +162,7 @@ struct mhi_ep_chan {</div><div class='ctx'> 	void (*xfer_cb)(struct mhi_ep_device *mhi_dev, struct mhi_result *result);</div><div class='ctx'> 	enum mhi_ch_state state;</div><div class='ctx'> 	enum dma_data_direction dir;</div><div class='add'>+	size_t rd_offset;</div><div class='ctx'> 	u64 tre_loc;</div><div class='ctx'> 	u32 tre_size;</div><div class='ctx'> 	u32 tre_bytes_left;</div><div class='head'>diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c<br/>index 600881808982..65fc1d738bec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/ep/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/main.c</a></div><div class='hunk'>@@ -54,11 +54,27 @@ static int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 ring_idx,</div><div class='ctx'> 	mutex_unlock(&amp;mhi_cntrl-&gt;event_lock);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Raise IRQ to host only if the BEI flag is not set in TRE. Host might</div><div class='del'>-	 * set this flag for interrupt moderation as per MHI protocol.</div><div class='add'>+	 * As per the MHI specification, section 4.3, Interrupt moderation:</div><div class='add'>+	 *</div><div class='add'>+	 * 1. If BEI flag is not set, cancel any pending intmodt work if started</div><div class='add'>+	 * for the event ring and raise IRQ immediately.</div><div class='add'>+	 *</div><div class='add'>+	 * 2. If both BEI and intmodt are set, and if no IRQ is pending for the</div><div class='add'>+	 * same event ring, start the IRQ delayed work as per the value of</div><div class='add'>+	 * intmodt. If previous IRQ is pending, then do nothing as the pending</div><div class='add'>+	 * IRQ is enough for the host to process the current event ring element.</div><div class='add'>+	 *</div><div class='add'>+	 * 3. If BEI is set and intmodt is not set, no need to raise IRQ.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!bei)</div><div class='add'>+	if (!bei) {</div><div class='add'>+		if (READ_ONCE(ring-&gt;irq_pending))</div><div class='add'>+			cancel_delayed_work(&amp;ring-&gt;intmodt_work);</div><div class='add'>+</div><div class='ctx'> 		mhi_cntrl-&gt;raise_irq(mhi_cntrl, ring-&gt;irq_vector);</div><div class='add'>+	} else if (ring-&gt;intmodt &amp;&amp; !READ_ONCE(ring-&gt;irq_pending)) {</div><div class='add'>+		WRITE_ONCE(ring-&gt;irq_pending, true);</div><div class='add'>+		schedule_delayed_work(&amp;ring-&gt;intmodt_work, msecs_to_jiffies(ring-&gt;intmodt));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -71,45 +87,77 @@ err_unlock:</div><div class='ctx'> static int mhi_ep_send_completion_event(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring,</div><div class='ctx'> 					struct mhi_ring_element *tre, u32 len, enum mhi_ev_ccs code)</div><div class='ctx'> {</div><div class='del'>-	struct mhi_ring_element event = {};</div><div class='add'>+	struct mhi_ring_element *event;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	event = kmem_cache_zalloc(mhi_cntrl-&gt;ev_ring_el_cache, GFP_KERNEL | GFP_DMA);</div><div class='add'>+	if (!event)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	event.ptr = cpu_to_le64(ring-&gt;rbase + ring-&gt;rd_offset * sizeof(*tre));</div><div class='del'>-	event.dword[0] = MHI_TRE_EV_DWORD0(code, len);</div><div class='del'>-	event.dword[1] = MHI_TRE_EV_DWORD1(ring-&gt;ch_id, MHI_PKT_TYPE_TX_EVENT);</div><div class='add'>+	event-&gt;ptr = cpu_to_le64(ring-&gt;rbase + ring-&gt;rd_offset * sizeof(*tre));</div><div class='add'>+	event-&gt;dword[0] = MHI_TRE_EV_DWORD0(code, len);</div><div class='add'>+	event-&gt;dword[1] = MHI_TRE_EV_DWORD1(ring-&gt;ch_id, MHI_PKT_TYPE_TX_EVENT);</div><div class='ctx'> </div><div class='del'>-	return mhi_ep_send_event(mhi_cntrl, ring-&gt;er_index, &amp;event, MHI_TRE_DATA_GET_BEI(tre));</div><div class='add'>+	ret = mhi_ep_send_event(mhi_cntrl, ring-&gt;er_index, event, MHI_TRE_DATA_GET_BEI(tre));</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;ev_ring_el_cache, event);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state)</div><div class='ctx'> {</div><div class='del'>-	struct mhi_ring_element event = {};</div><div class='add'>+	struct mhi_ring_element *event;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	event.dword[0] = MHI_SC_EV_DWORD0(state);</div><div class='del'>-	event.dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_STATE_CHANGE_EVENT);</div><div class='add'>+	event = kmem_cache_zalloc(mhi_cntrl-&gt;ev_ring_el_cache, GFP_KERNEL | GFP_DMA);</div><div class='add'>+	if (!event)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	return mhi_ep_send_event(mhi_cntrl, 0, &amp;event, 0);</div><div class='add'>+	event-&gt;dword[0] = MHI_SC_EV_DWORD0(state);</div><div class='add'>+	event-&gt;dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_STATE_CHANGE_EVENT);</div><div class='add'>+</div><div class='add'>+	ret = mhi_ep_send_event(mhi_cntrl, 0, event, 0);</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;ev_ring_el_cache, event);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ee_type exec_env)</div><div class='ctx'> {</div><div class='del'>-	struct mhi_ring_element event = {};</div><div class='add'>+	struct mhi_ring_element *event;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	event.dword[0] = MHI_EE_EV_DWORD0(exec_env);</div><div class='del'>-	event.dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_EE_EVENT);</div><div class='add'>+	event = kmem_cache_zalloc(mhi_cntrl-&gt;ev_ring_el_cache, GFP_KERNEL | GFP_DMA);</div><div class='add'>+	if (!event)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	event-&gt;dword[0] = MHI_EE_EV_DWORD0(exec_env);</div><div class='add'>+	event-&gt;dword[1] = MHI_SC_EV_DWORD1(MHI_PKT_TYPE_EE_EVENT);</div><div class='ctx'> </div><div class='del'>-	return mhi_ep_send_event(mhi_cntrl, 0, &amp;event, 0);</div><div class='add'>+	ret = mhi_ep_send_event(mhi_cntrl, 0, event, 0);</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;ev_ring_el_cache, event);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mhi_ep_send_cmd_comp_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ev_ccs code)</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_ring *ring = &amp;mhi_cntrl-&gt;mhi_cmd-&gt;ring;</div><div class='del'>-	struct mhi_ring_element event = {};</div><div class='add'>+	struct mhi_ring_element *event;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	event = kmem_cache_zalloc(mhi_cntrl-&gt;ev_ring_el_cache, GFP_KERNEL | GFP_DMA);</div><div class='add'>+	if (!event)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	event-&gt;ptr = cpu_to_le64(ring-&gt;rbase + ring-&gt;rd_offset * sizeof(struct mhi_ring_element));</div><div class='add'>+	event-&gt;dword[0] = MHI_CC_EV_DWORD0(code);</div><div class='add'>+	event-&gt;dword[1] = MHI_CC_EV_DWORD1(MHI_PKT_TYPE_CMD_COMPLETION_EVENT);</div><div class='ctx'> </div><div class='del'>-	event.ptr = cpu_to_le64(ring-&gt;rbase + ring-&gt;rd_offset * sizeof(struct mhi_ring_element));</div><div class='del'>-	event.dword[0] = MHI_CC_EV_DWORD0(code);</div><div class='del'>-	event.dword[1] = MHI_CC_EV_DWORD1(MHI_PKT_TYPE_CMD_COMPLETION_EVENT);</div><div class='add'>+	ret = mhi_ep_send_event(mhi_cntrl, 0, event, 0);</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;ev_ring_el_cache, event);</div><div class='ctx'> </div><div class='del'>-	return mhi_ep_send_event(mhi_cntrl, 0, &amp;event, 0);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_element *el)</div><div class='hunk'>@@ -151,6 +199,8 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele</div><div class='ctx'> </div><div class='ctx'> 				goto err_unlock;</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			mhi_chan-&gt;rd_offset = ch_ring-&gt;rd_offset;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Set channel state to RUNNING */</div><div class='hunk'>@@ -280,22 +330,85 @@ bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_dev, enum dma_data_directio</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = mhi_dev-&gt;mhi_cntrl;</div><div class='ctx'> 	struct mhi_ep_ring *ring = &amp;mhi_cntrl-&gt;mhi_chan[mhi_chan-&gt;chan].ring;</div><div class='ctx'> </div><div class='del'>-	return !!(ring-&gt;rd_offset == ring-&gt;wr_offset);</div><div class='add'>+	return !!(mhi_chan-&gt;rd_offset == ring-&gt;wr_offset);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty);</div><div class='ctx'> </div><div class='add'>+static void mhi_ep_read_completion(struct mhi_ep_buf_info *buf_info)</div><div class='add'>+{</div><div class='add'>+	struct mhi_ep_device *mhi_dev = buf_info-&gt;mhi_dev;</div><div class='add'>+	struct mhi_ep_cntrl *mhi_cntrl = mhi_dev-&gt;mhi_cntrl;</div><div class='add'>+	struct mhi_ep_chan *mhi_chan = mhi_dev-&gt;ul_chan;</div><div class='add'>+	struct mhi_ep_ring *ring = &amp;mhi_cntrl-&gt;mhi_chan[mhi_chan-&gt;chan].ring;</div><div class='add'>+	struct mhi_ring_element *el = &amp;ring-&gt;ring_cache[ring-&gt;rd_offset];</div><div class='add'>+	struct mhi_result result = {};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (mhi_chan-&gt;xfer_cb) {</div><div class='add'>+		result.buf_addr = buf_info-&gt;cb_buf;</div><div class='add'>+		result.dir = mhi_chan-&gt;dir;</div><div class='add'>+		result.bytes_xferd = buf_info-&gt;size;</div><div class='add'>+</div><div class='add'>+		mhi_chan-&gt;xfer_cb(mhi_dev, &amp;result);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The host will split the data packet into multiple TREs if it can't fit</div><div class='add'>+	 * the packet in a single TRE. In that case, CHAIN flag will be set by the</div><div class='add'>+	 * host for all TREs except the last one.</div><div class='add'>+	 */</div><div class='add'>+	if (buf_info-&gt;code != MHI_EV_CC_OVERFLOW) {</div><div class='add'>+		if (MHI_TRE_DATA_GET_CHAIN(el)) {</div><div class='add'>+			/*</div><div class='add'>+			 * IEOB (Interrupt on End of Block) flag will be set by the host if</div><div class='add'>+			 * it expects the completion event for all TREs of a TD.</div><div class='add'>+			 */</div><div class='add'>+			if (MHI_TRE_DATA_GET_IEOB(el)) {</div><div class='add'>+				ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,</div><div class='add'>+							     MHI_TRE_DATA_GET_LEN(el),</div><div class='add'>+							     MHI_EV_CC_EOB);</div><div class='add'>+				if (ret &lt; 0) {</div><div class='add'>+					dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev,</div><div class='add'>+						"Error sending transfer compl. event\n");</div><div class='add'>+					goto err_free_tre_buf;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/*</div><div class='add'>+			 * IEOT (Interrupt on End of Transfer) flag will be set by the host</div><div class='add'>+			 * for the last TRE of the TD and expects the completion event for</div><div class='add'>+			 * the same.</div><div class='add'>+			 */</div><div class='add'>+			if (MHI_TRE_DATA_GET_IEOT(el)) {</div><div class='add'>+				ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,</div><div class='add'>+							     MHI_TRE_DATA_GET_LEN(el),</div><div class='add'>+							     MHI_EV_CC_EOT);</div><div class='add'>+				if (ret &lt; 0) {</div><div class='add'>+					dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev,</div><div class='add'>+						"Error sending transfer compl. event\n");</div><div class='add'>+					goto err_free_tre_buf;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mhi_ep_ring_inc_index(ring);</div><div class='add'>+</div><div class='add'>+err_free_tre_buf:</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;tre_buf_cache, buf_info-&gt;cb_buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='del'>-				struct mhi_ep_ring *ring,</div><div class='del'>-				struct mhi_result *result,</div><div class='del'>-				u32 len)</div><div class='add'>+			       struct mhi_ep_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_chan *mhi_chan = &amp;mhi_cntrl-&gt;mhi_chan[ring-&gt;ch_id];</div><div class='ctx'> 	struct device *dev = &amp;mhi_cntrl-&gt;mhi_dev-&gt;dev;</div><div class='ctx'> 	size_t tr_len, read_offset, write_offset;</div><div class='add'>+	struct mhi_ep_buf_info buf_info = {};</div><div class='add'>+	u32 len = MHI_EP_DEFAULT_MTU;</div><div class='ctx'> 	struct mhi_ring_element *el;</div><div class='ctx'> 	bool tr_done = false;</div><div class='del'>-	void *write_addr;</div><div class='del'>-	u64 read_addr;</div><div class='add'>+	void *buf_addr;</div><div class='ctx'> 	u32 buf_left;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -308,7 +421,7 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='ctx'> 			return -ENODEV;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		el = &amp;ring-&gt;ring_cache[ring-&gt;rd_offset];</div><div class='add'>+		el = &amp;ring-&gt;ring_cache[mhi_chan-&gt;rd_offset];</div><div class='ctx'> </div><div class='ctx'> 		/* Check if there is data pending to be read from previous read operation */</div><div class='ctx'> 		if (mhi_chan-&gt;tre_bytes_left) {</div><div class='hunk'>@@ -324,81 +437,51 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='ctx'> </div><div class='ctx'> 		read_offset = mhi_chan-&gt;tre_size - mhi_chan-&gt;tre_bytes_left;</div><div class='ctx'> 		write_offset = len - buf_left;</div><div class='del'>-		read_addr = mhi_chan-&gt;tre_loc + read_offset;</div><div class='del'>-		write_addr = result-&gt;buf_addr + write_offset;</div><div class='add'>+</div><div class='add'>+		buf_addr = kmem_cache_zalloc(mhi_cntrl-&gt;tre_buf_cache, GFP_KERNEL | GFP_DMA);</div><div class='add'>+		if (!buf_addr)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		buf_info.host_addr = mhi_chan-&gt;tre_loc + read_offset;</div><div class='add'>+		buf_info.dev_addr = buf_addr + write_offset;</div><div class='add'>+		buf_info.size = tr_len;</div><div class='add'>+		buf_info.cb = mhi_ep_read_completion;</div><div class='add'>+		buf_info.cb_buf = buf_addr;</div><div class='add'>+		buf_info.mhi_dev = mhi_chan-&gt;mhi_dev;</div><div class='add'>+</div><div class='add'>+		if (mhi_chan-&gt;tre_bytes_left - tr_len)</div><div class='add'>+			buf_info.code = MHI_EV_CC_OVERFLOW;</div><div class='ctx'> </div><div class='ctx'> 		dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring-&gt;ch_id);</div><div class='del'>-		ret = mhi_cntrl-&gt;read_from_host(mhi_cntrl, read_addr, write_addr, tr_len);</div><div class='add'>+		ret = mhi_cntrl-&gt;read_async(mhi_cntrl, &amp;buf_info);</div><div class='ctx'> 		if (ret &lt; 0) {</div><div class='ctx'> 			dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev, "Error reading from channel\n");</div><div class='del'>-			return ret;</div><div class='add'>+			goto err_free_buf_addr;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		buf_left -= tr_len;</div><div class='ctx'> 		mhi_chan-&gt;tre_bytes_left -= tr_len;</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * Once the TRE (Transfer Ring Element) of a TD (Transfer Descriptor) has been</div><div class='del'>-		 * read completely:</div><div class='del'>-		 *</div><div class='del'>-		 * 1. Send completion event to the host based on the flags set in TRE.</div><div class='del'>-		 * 2. Increment the local read offset of the transfer ring.</div><div class='del'>-		 */</div><div class='ctx'> 		if (!mhi_chan-&gt;tre_bytes_left) {</div><div class='del'>-			/*</div><div class='del'>-			 * The host will split the data packet into multiple TREs if it can't fit</div><div class='del'>-			 * the packet in a single TRE. In that case, CHAIN flag will be set by the</div><div class='del'>-			 * host for all TREs except the last one.</div><div class='del'>-			 */</div><div class='del'>-			if (MHI_TRE_DATA_GET_CHAIN(el)) {</div><div class='del'>-				/*</div><div class='del'>-				 * IEOB (Interrupt on End of Block) flag will be set by the host if</div><div class='del'>-				 * it expects the completion event for all TREs of a TD.</div><div class='del'>-				 */</div><div class='del'>-				if (MHI_TRE_DATA_GET_IEOB(el)) {</div><div class='del'>-					ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,</div><div class='del'>-								     MHI_TRE_DATA_GET_LEN(el),</div><div class='del'>-								     MHI_EV_CC_EOB);</div><div class='del'>-					if (ret &lt; 0) {</div><div class='del'>-						dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev,</div><div class='del'>-							"Error sending transfer compl. event\n");</div><div class='del'>-						return ret;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='del'>-				/*</div><div class='del'>-				 * IEOT (Interrupt on End of Transfer) flag will be set by the host</div><div class='del'>-				 * for the last TRE of the TD and expects the completion event for</div><div class='del'>-				 * the same.</div><div class='del'>-				 */</div><div class='del'>-				if (MHI_TRE_DATA_GET_IEOT(el)) {</div><div class='del'>-					ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el,</div><div class='del'>-								     MHI_TRE_DATA_GET_LEN(el),</div><div class='del'>-								     MHI_EV_CC_EOT);</div><div class='del'>-					if (ret &lt; 0) {</div><div class='del'>-						dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev,</div><div class='del'>-							"Error sending transfer compl. event\n");</div><div class='del'>-						return ret;</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-</div><div class='add'>+			if (MHI_TRE_DATA_GET_IEOT(el))</div><div class='ctx'> 				tr_done = true;</div><div class='del'>-			}</div><div class='ctx'> </div><div class='del'>-			mhi_ep_ring_inc_index(ring);</div><div class='add'>+			mhi_chan-&gt;rd_offset = (mhi_chan-&gt;rd_offset + 1) % ring-&gt;ring_size;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		result-&gt;bytes_xferd += tr_len;</div><div class='ctx'> 	} while (buf_left &amp;&amp; !tr_done);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+err_free_buf_addr:</div><div class='add'>+	kmem_cache_free(mhi_cntrl-&gt;tre_buf_cache, buf_addr);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring, struct mhi_ring_element *el)</div><div class='add'>+static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = ring-&gt;mhi_cntrl;</div><div class='ctx'> 	struct mhi_result result = {};</div><div class='del'>-	u32 len = MHI_EP_DEFAULT_MTU;</div><div class='ctx'> 	struct mhi_ep_chan *mhi_chan;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -419,44 +502,59 @@ static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring, struct mhi_ring_elem</div><div class='ctx'> 		mhi_chan-&gt;xfer_cb(mhi_chan-&gt;mhi_dev, &amp;result);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* UL channel */</div><div class='del'>-		result.buf_addr = kzalloc(len, GFP_KERNEL);</div><div class='del'>-		if (!result.buf_addr)</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 		do {</div><div class='del'>-			ret = mhi_ep_read_channel(mhi_cntrl, ring, &amp;result, len);</div><div class='add'>+			ret = mhi_ep_read_channel(mhi_cntrl, ring);</div><div class='ctx'> 			if (ret &lt; 0) {</div><div class='ctx'> 				dev_err(&amp;mhi_chan-&gt;mhi_dev-&gt;dev, "Failed to read channel\n");</div><div class='del'>-				kfree(result.buf_addr);</div><div class='ctx'> 				return ret;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			result.dir = mhi_chan-&gt;dir;</div><div class='del'>-			mhi_chan-&gt;xfer_cb(mhi_chan-&gt;mhi_dev, &amp;result);</div><div class='del'>-			result.bytes_xferd = 0;</div><div class='del'>-			memset(result.buf_addr, 0, len);</div><div class='del'>-</div><div class='ctx'> 			/* Read until the ring becomes empty */</div><div class='ctx'> 		} while (!mhi_ep_queue_is_empty(mhi_chan-&gt;mhi_dev, DMA_TO_DEVICE));</div><div class='del'>-</div><div class='del'>-		kfree(result.buf_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mhi_ep_skb_completion(struct mhi_ep_buf_info *buf_info)</div><div class='add'>+{</div><div class='add'>+	struct mhi_ep_device *mhi_dev = buf_info-&gt;mhi_dev;</div><div class='add'>+	struct mhi_ep_cntrl *mhi_cntrl = mhi_dev-&gt;mhi_cntrl;</div><div class='add'>+	struct mhi_ep_chan *mhi_chan = mhi_dev-&gt;dl_chan;</div><div class='add'>+	struct mhi_ep_ring *ring = &amp;mhi_cntrl-&gt;mhi_chan[mhi_chan-&gt;chan].ring;</div><div class='add'>+	struct mhi_ring_element *el = &amp;ring-&gt;ring_cache[ring-&gt;rd_offset];</div><div class='add'>+	struct device *dev = &amp;mhi_dev-&gt;dev;</div><div class='add'>+	struct mhi_result result = {};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (mhi_chan-&gt;xfer_cb) {</div><div class='add'>+		result.buf_addr = buf_info-&gt;cb_buf;</div><div class='add'>+		result.dir = mhi_chan-&gt;dir;</div><div class='add'>+		result.bytes_xferd = buf_info-&gt;size;</div><div class='add'>+</div><div class='add'>+		mhi_chan-&gt;xfer_cb(mhi_dev, &amp;result);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el, buf_info-&gt;size,</div><div class='add'>+					   buf_info-&gt;code);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Error sending transfer completion event\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mhi_ep_ring_inc_index(ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* TODO: Handle partially formed TDs */</div><div class='ctx'> int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb)</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = mhi_dev-&gt;mhi_cntrl;</div><div class='ctx'> 	struct mhi_ep_chan *mhi_chan = mhi_dev-&gt;dl_chan;</div><div class='ctx'> 	struct device *dev = &amp;mhi_chan-&gt;mhi_dev-&gt;dev;</div><div class='add'>+	struct mhi_ep_buf_info buf_info = {};</div><div class='ctx'> 	struct mhi_ring_element *el;</div><div class='ctx'> 	u32 buf_left, read_offset;</div><div class='ctx'> 	struct mhi_ep_ring *ring;</div><div class='del'>-	enum mhi_ev_ccs code;</div><div class='del'>-	void *read_addr;</div><div class='del'>-	u64 write_addr;</div><div class='ctx'> 	size_t tr_len;</div><div class='ctx'> 	u32 tre_len;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -480,40 +578,44 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb)</div><div class='ctx'> 			goto err_exit;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		el = &amp;ring-&gt;ring_cache[ring-&gt;rd_offset];</div><div class='add'>+		el = &amp;ring-&gt;ring_cache[mhi_chan-&gt;rd_offset];</div><div class='ctx'> 		tre_len = MHI_TRE_DATA_GET_LEN(el);</div><div class='ctx'> </div><div class='ctx'> 		tr_len = min(buf_left, tre_len);</div><div class='ctx'> 		read_offset = skb-&gt;len - buf_left;</div><div class='del'>-		read_addr = skb-&gt;data + read_offset;</div><div class='del'>-		write_addr = MHI_TRE_DATA_GET_PTR(el);</div><div class='ctx'> </div><div class='del'>-		dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring-&gt;ch_id);</div><div class='del'>-		ret = mhi_cntrl-&gt;write_to_host(mhi_cntrl, read_addr, write_addr, tr_len);</div><div class='del'>-		if (ret &lt; 0) {</div><div class='del'>-			dev_err(dev, "Error writing to the channel\n");</div><div class='del'>-			goto err_exit;</div><div class='del'>-		}</div><div class='add'>+		buf_info.dev_addr = skb-&gt;data + read_offset;</div><div class='add'>+		buf_info.host_addr = MHI_TRE_DATA_GET_PTR(el);</div><div class='add'>+		buf_info.size = tr_len;</div><div class='add'>+		buf_info.cb = mhi_ep_skb_completion;</div><div class='add'>+		buf_info.cb_buf = skb;</div><div class='add'>+		buf_info.mhi_dev = mhi_dev;</div><div class='ctx'> </div><div class='del'>-		buf_left -= tr_len;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * For all TREs queued by the host for DL channel, only the EOT flag will be set.</div><div class='ctx'> 		 * If the packet doesn't fit into a single TRE, send the OVERFLOW event to</div><div class='ctx'> 		 * the host so that the host can adjust the packet boundary to next TREs. Else send</div><div class='ctx'> 		 * the EOT event to the host indicating the packet boundary.</div><div class='ctx'> 		 */</div><div class='del'>-		if (buf_left)</div><div class='del'>-			code = MHI_EV_CC_OVERFLOW;</div><div class='add'>+		if (buf_left - tr_len)</div><div class='add'>+			buf_info.code = MHI_EV_CC_OVERFLOW;</div><div class='ctx'> 		else</div><div class='del'>-			code = MHI_EV_CC_EOT;</div><div class='add'>+			buf_info.code = MHI_EV_CC_EOT;</div><div class='ctx'> </div><div class='del'>-		ret = mhi_ep_send_completion_event(mhi_cntrl, ring, el, tr_len, code);</div><div class='del'>-		if (ret) {</div><div class='del'>-			dev_err(dev, "Error sending transfer completion event\n");</div><div class='add'>+		dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring-&gt;ch_id);</div><div class='add'>+		ret = mhi_cntrl-&gt;write_async(mhi_cntrl, &amp;buf_info);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(dev, "Error writing to the channel\n");</div><div class='ctx'> 			goto err_exit;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		mhi_ep_ring_inc_index(ring);</div><div class='add'>+		buf_left -= tr_len;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Update the read offset cached in mhi_chan. Actual read offset</div><div class='add'>+		 * will be updated by the completion handler.</div><div class='add'>+		 */</div><div class='add'>+		mhi_chan-&gt;rd_offset = (mhi_chan-&gt;rd_offset + 1) % ring-&gt;ring_size;</div><div class='ctx'> 	} while (buf_left);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;mhi_chan-&gt;lock);</div><div class='hunk'>@@ -714,7 +816,6 @@ static void mhi_ep_ch_ring_worker(struct work_struct *work)</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, ch_ring_work);</div><div class='ctx'> 	struct device *dev = &amp;mhi_cntrl-&gt;mhi_dev-&gt;dev;</div><div class='ctx'> 	struct mhi_ep_ring_item *itr, *tmp;</div><div class='del'>-	struct mhi_ring_element *el;</div><div class='ctx'> 	struct mhi_ep_ring *ring;</div><div class='ctx'> 	struct mhi_ep_chan *chan;</div><div class='ctx'> 	unsigned long flags;</div><div class='hunk'>@@ -748,31 +849,29 @@ static void mhi_ep_ch_ring_worker(struct work_struct *work)</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "Error updating write offset for ring\n");</div><div class='ctx'> 			mutex_unlock(&amp;chan-&gt;lock);</div><div class='del'>-			kfree(itr);</div><div class='add'>+			kmem_cache_free(mhi_cntrl-&gt;ring_item_cache, itr);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Sanity check to make sure there are elements in the ring */</div><div class='del'>-		if (ring-&gt;rd_offset == ring-&gt;wr_offset) {</div><div class='add'>+		if (chan-&gt;rd_offset == ring-&gt;wr_offset) {</div><div class='ctx'> 			mutex_unlock(&amp;chan-&gt;lock);</div><div class='del'>-			kfree(itr);</div><div class='add'>+			kmem_cache_free(mhi_cntrl-&gt;ring_item_cache, itr);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		el = &amp;ring-&gt;ring_cache[ring-&gt;rd_offset];</div><div class='del'>-</div><div class='ctx'> 		dev_dbg(dev, "Processing the ring for channel (%u)\n", ring-&gt;ch_id);</div><div class='del'>-		ret = mhi_ep_process_ch_ring(ring, el);</div><div class='add'>+		ret = mhi_ep_process_ch_ring(ring);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "Error processing ring for channel (%u): %d\n",</div><div class='ctx'> 				ring-&gt;ch_id, ret);</div><div class='ctx'> 			mutex_unlock(&amp;chan-&gt;lock);</div><div class='del'>-			kfree(itr);</div><div class='add'>+			kmem_cache_free(mhi_cntrl-&gt;ring_item_cache, itr);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		mutex_unlock(&amp;chan-&gt;lock);</div><div class='del'>-		kfree(itr);</div><div class='add'>+		kmem_cache_free(mhi_cntrl-&gt;ring_item_cache, itr);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -828,7 +927,7 @@ static void mhi_ep_queue_channel_db(struct mhi_ep_cntrl *mhi_cntrl, unsigned lon</div><div class='ctx'> 		u32 ch_id = ch_idx + i;</div><div class='ctx'> </div><div class='ctx'> 		ring = &amp;mhi_cntrl-&gt;mhi_chan[ch_id].ring;</div><div class='del'>-		item = kzalloc(sizeof(*item), GFP_ATOMIC);</div><div class='add'>+		item = kmem_cache_zalloc(mhi_cntrl-&gt;ring_item_cache, GFP_ATOMIC);</div><div class='ctx'> 		if (!item)</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='hunk'>@@ -1365,6 +1464,10 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='ctx'> 	if (!mhi_cntrl || !mhi_cntrl-&gt;cntrl_dev || !mhi_cntrl-&gt;mmio || !mhi_cntrl-&gt;irq)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!mhi_cntrl-&gt;read_sync || !mhi_cntrl-&gt;write_sync ||</div><div class='add'>+	    !mhi_cntrl-&gt;read_async || !mhi_cntrl-&gt;write_async)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	ret = mhi_ep_chan_init(mhi_cntrl, config);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -1375,6 +1478,29 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='ctx'> 		goto err_free_ch;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	mhi_cntrl-&gt;ev_ring_el_cache = kmem_cache_create("mhi_ep_event_ring_el",</div><div class='add'>+							sizeof(struct mhi_ring_element), 0,</div><div class='add'>+							SLAB_CACHE_DMA, NULL);</div><div class='add'>+	if (!mhi_cntrl-&gt;ev_ring_el_cache) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_free_cmd;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mhi_cntrl-&gt;tre_buf_cache = kmem_cache_create("mhi_ep_tre_buf", MHI_EP_DEFAULT_MTU, 0,</div><div class='add'>+						      SLAB_CACHE_DMA, NULL);</div><div class='add'>+	if (!mhi_cntrl-&gt;tre_buf_cache) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_destroy_ev_ring_el_cache;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mhi_cntrl-&gt;ring_item_cache = kmem_cache_create("mhi_ep_ring_item",</div><div class='add'>+							sizeof(struct mhi_ep_ring_item), 0,</div><div class='add'>+							0, NULL);</div><div class='add'>+	if (!mhi_cntrl-&gt;ev_ring_el_cache) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_destroy_tre_buf_cache;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	INIT_WORK(&amp;mhi_cntrl-&gt;state_work, mhi_ep_state_worker);</div><div class='ctx'> 	INIT_WORK(&amp;mhi_cntrl-&gt;reset_work, mhi_ep_reset_worker);</div><div class='ctx'> 	INIT_WORK(&amp;mhi_cntrl-&gt;cmd_ring_work, mhi_ep_cmd_ring_worker);</div><div class='hunk'>@@ -1383,7 +1509,7 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,</div><div class='ctx'> 	mhi_cntrl-&gt;wq = alloc_workqueue("mhi_ep_wq", 0, 0);</div><div class='ctx'> 	if (!mhi_cntrl-&gt;wq) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='del'>-		goto err_free_cmd;</div><div class='add'>+		goto err_destroy_ring_item_cache;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;mhi_cntrl-&gt;st_transition_list);</div><div class='hunk'>@@ -1442,6 +1568,12 @@ err_ida_free:</div><div class='ctx'> 	ida_free(&amp;mhi_ep_cntrl_ida, mhi_cntrl-&gt;index);</div><div class='ctx'> err_destroy_wq:</div><div class='ctx'> 	destroy_workqueue(mhi_cntrl-&gt;wq);</div><div class='add'>+err_destroy_ring_item_cache:</div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;ring_item_cache);</div><div class='add'>+err_destroy_ev_ring_el_cache:</div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;ev_ring_el_cache);</div><div class='add'>+err_destroy_tre_buf_cache:</div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;tre_buf_cache);</div><div class='ctx'> err_free_cmd:</div><div class='ctx'> 	kfree(mhi_cntrl-&gt;mhi_cmd);</div><div class='ctx'> err_free_ch:</div><div class='hunk'>@@ -1463,6 +1595,9 @@ void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl)</div><div class='ctx'> </div><div class='ctx'> 	free_irq(mhi_cntrl-&gt;irq, mhi_cntrl);</div><div class='ctx'> </div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;tre_buf_cache);</div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;ev_ring_el_cache);</div><div class='add'>+	kmem_cache_destroy(mhi_cntrl-&gt;ring_item_cache);</div><div class='ctx'> 	kfree(mhi_cntrl-&gt;mhi_cmd);</div><div class='ctx'> 	kfree(mhi_cntrl-&gt;mhi_chan);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/bus/mhi/ep/ring.c b/drivers/bus/mhi/ep/ring.c<br/>index 115518ec76a4..aeb53b2c34a8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/ring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/ep/ring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/ep/ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/ep/ring.c</a></div><div class='hunk'>@@ -30,7 +30,8 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end)</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = ring-&gt;mhi_cntrl;</div><div class='ctx'> 	struct device *dev = &amp;mhi_cntrl-&gt;mhi_dev-&gt;dev;</div><div class='del'>-	size_t start, copy_size;</div><div class='add'>+	struct mhi_ep_buf_info buf_info = {};</div><div class='add'>+	size_t start;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Don't proceed in the case of event ring. This happens during mhi_ep_ring_start(). */</div><div class='hunk'>@@ -43,30 +44,34 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, size_t end)</div><div class='ctx'> </div><div class='ctx'> 	start = ring-&gt;wr_offset;</div><div class='ctx'> 	if (start &lt; end) {</div><div class='del'>-		copy_size = (end - start) * sizeof(struct mhi_ring_element);</div><div class='del'>-		ret = mhi_cntrl-&gt;read_from_host(mhi_cntrl, ring-&gt;rbase +</div><div class='del'>-						(start * sizeof(struct mhi_ring_element)),</div><div class='del'>-						&amp;ring-&gt;ring_cache[start], copy_size);</div><div class='add'>+		buf_info.size = (end - start) * sizeof(struct mhi_ring_element);</div><div class='add'>+		buf_info.host_addr = ring-&gt;rbase + (start * sizeof(struct mhi_ring_element));</div><div class='add'>+		buf_info.dev_addr = &amp;ring-&gt;ring_cache[start];</div><div class='add'>+</div><div class='add'>+		ret = mhi_cntrl-&gt;read_sync(mhi_cntrl, &amp;buf_info);</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	} else {</div><div class='del'>-		copy_size = (ring-&gt;ring_size - start) * sizeof(struct mhi_ring_element);</div><div class='del'>-		ret = mhi_cntrl-&gt;read_from_host(mhi_cntrl, ring-&gt;rbase +</div><div class='del'>-						(start * sizeof(struct mhi_ring_element)),</div><div class='del'>-						&amp;ring-&gt;ring_cache[start], copy_size);</div><div class='add'>+		buf_info.size = (ring-&gt;ring_size - start) * sizeof(struct mhi_ring_element);</div><div class='add'>+		buf_info.host_addr = ring-&gt;rbase + (start * sizeof(struct mhi_ring_element));</div><div class='add'>+		buf_info.dev_addr = &amp;ring-&gt;ring_cache[start];</div><div class='add'>+</div><div class='add'>+		ret = mhi_cntrl-&gt;read_sync(mhi_cntrl, &amp;buf_info);</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='ctx'> 			return ret;</div><div class='ctx'> </div><div class='ctx'> 		if (end) {</div><div class='del'>-			ret = mhi_cntrl-&gt;read_from_host(mhi_cntrl, ring-&gt;rbase,</div><div class='del'>-							&amp;ring-&gt;ring_cache[0],</div><div class='del'>-							end * sizeof(struct mhi_ring_element));</div><div class='add'>+			buf_info.host_addr = ring-&gt;rbase;</div><div class='add'>+			buf_info.dev_addr = &amp;ring-&gt;ring_cache[0];</div><div class='add'>+			buf_info.size = end * sizeof(struct mhi_ring_element);</div><div class='add'>+</div><div class='add'>+			ret = mhi_cntrl-&gt;read_sync(mhi_cntrl, &amp;buf_info);</div><div class='ctx'> 			if (ret &lt; 0)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, copy_size);</div><div class='add'>+	dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, buf_info.size);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -102,6 +107,7 @@ int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ring_element *e</div><div class='ctx'> {</div><div class='ctx'> 	struct mhi_ep_cntrl *mhi_cntrl = ring-&gt;mhi_cntrl;</div><div class='ctx'> 	struct device *dev = &amp;mhi_cntrl-&gt;mhi_dev-&gt;dev;</div><div class='add'>+	struct mhi_ep_buf_info buf_info = {};</div><div class='ctx'> 	size_t old_offset = 0;</div><div class='ctx'> 	u32 num_free_elem;</div><div class='ctx'> 	__le64 rp;</div><div class='hunk'>@@ -133,12 +139,11 @@ int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, struct mhi_ring_element *e</div><div class='ctx'> 	rp = cpu_to_le64(ring-&gt;rd_offset * sizeof(*el) + ring-&gt;rbase);</div><div class='ctx'> 	memcpy_toio((void __iomem *) &amp;ring-&gt;ring_ctx-&gt;generic.rp, &amp;rp, sizeof(u64));</div><div class='ctx'> </div><div class='del'>-	ret = mhi_cntrl-&gt;write_to_host(mhi_cntrl, el, ring-&gt;rbase + (old_offset * sizeof(*el)),</div><div class='del'>-				       sizeof(*el));</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+	buf_info.host_addr = ring-&gt;rbase + (old_offset * sizeof(*el));</div><div class='add'>+	buf_info.dev_addr = el;</div><div class='add'>+	buf_info.size = sizeof(*el);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return mhi_cntrl-&gt;write_sync(mhi_cntrl, &amp;buf_info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32 id)</div><div class='hunk'>@@ -157,6 +162,15 @@ void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type, u32</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mhi_ep_raise_irq(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct mhi_ep_ring *ring = container_of(work, struct mhi_ep_ring, intmodt_work.work);</div><div class='add'>+	struct mhi_ep_cntrl *mhi_cntrl = ring-&gt;mhi_cntrl;</div><div class='add'>+</div><div class='add'>+	mhi_cntrl-&gt;raise_irq(mhi_cntrl, ring-&gt;irq_vector);</div><div class='add'>+	WRITE_ONCE(ring-&gt;irq_pending, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring,</div><div class='ctx'> 			union mhi_ep_ring_ctx *ctx)</div><div class='ctx'> {</div><div class='hunk'>@@ -173,8 +187,13 @@ int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring,</div><div class='ctx'> 	if (ring-&gt;type == RING_TYPE_CH)</div><div class='ctx'> 		ring-&gt;er_index = le32_to_cpu(ring-&gt;ring_ctx-&gt;ch.erindex);</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;type == RING_TYPE_ER)</div><div class='add'>+	if (ring-&gt;type == RING_TYPE_ER) {</div><div class='ctx'> 		ring-&gt;irq_vector = le32_to_cpu(ring-&gt;ring_ctx-&gt;ev.msivec);</div><div class='add'>+		ring-&gt;intmodt = FIELD_GET(EV_CTX_INTMODT_MASK,</div><div class='add'>+					  le32_to_cpu(ring-&gt;ring_ctx-&gt;ev.intmod));</div><div class='add'>+</div><div class='add'>+		INIT_DELAYED_WORK(&amp;ring-&gt;intmodt_work, mhi_ep_raise_irq);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* During ring init, both rp and wp are equal */</div><div class='ctx'> 	memcpy_fromio(&amp;val, (void __iomem *) &amp;ring-&gt;ring_ctx-&gt;generic.rp, sizeof(u64));</div><div class='hunk'>@@ -201,6 +220,9 @@ int mhi_ep_ring_start(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring,</div><div class='ctx'> </div><div class='ctx'> void mhi_ep_ring_reset(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_ring *ring)</div><div class='ctx'> {</div><div class='add'>+	if (ring-&gt;type == RING_TYPE_ER)</div><div class='add'>+		cancel_delayed_work_sync(&amp;ring-&gt;intmodt_work);</div><div class='add'>+</div><div class='ctx'> 	ring-&gt;started = false;</div><div class='ctx'> 	kfree(ring-&gt;ring_cache);</div><div class='ctx'> 	ring-&gt;ring_cache = NULL;</div><div class='head'>diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c<br/>index f78aefd2d7a3..65ceac1837f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/host/init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/init.c</a></div><div class='hunk'>@@ -881,6 +881,7 @@ static int parse_config(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 	if (!mhi_cntrl-&gt;timeout_ms)</div><div class='ctx'> 		mhi_cntrl-&gt;timeout_ms = MHI_TIMEOUT_MS;</div><div class='ctx'> </div><div class='add'>+	mhi_cntrl-&gt;ready_timeout_ms = config-&gt;ready_timeout_ms;</div><div class='ctx'> 	mhi_cntrl-&gt;bounce_buf = config-&gt;use_bounce_buf;</div><div class='ctx'> 	mhi_cntrl-&gt;buffer_len = config-&gt;buf_len;</div><div class='ctx'> 	if (!mhi_cntrl-&gt;buffer_len)</div><div class='head'>diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/internal.h<br/>index 2e139e76de4c..30ac415a3000 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/internal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/host/internal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/internal.h</a></div><div class='hunk'>@@ -321,7 +321,7 @@ int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 				    u32 *out);</div><div class='ctx'> int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 				    void __iomem *base, u32 offset, u32 mask,</div><div class='del'>-				    u32 val, u32 delayus);</div><div class='add'>+				    u32 val, u32 delayus, u32 timeout_ms);</div><div class='ctx'> void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,</div><div class='ctx'> 		   u32 offset, u32 val);</div><div class='ctx'> int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl,</div><div class='head'>diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c<br/>index dcf627b36e82..abb561db9ae1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/host/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/main.c</a></div><div class='hunk'>@@ -40,10 +40,11 @@ int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> </div><div class='ctx'> int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 				    void __iomem *base, u32 offset,</div><div class='del'>-				    u32 mask, u32 val, u32 delayus)</div><div class='add'>+				    u32 mask, u32 val, u32 delayus,</div><div class='add'>+				    u32 timeout_ms)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='del'>-	u32 out, retry = (mhi_cntrl-&gt;timeout_ms * 1000) / delayus;</div><div class='add'>+	u32 out, retry = (timeout_ms * 1000) / delayus;</div><div class='ctx'> </div><div class='ctx'> 	while (retry--) {</div><div class='ctx'> 		ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &amp;out);</div><div class='hunk'>@@ -268,7 +269,8 @@ static void mhi_del_ring_element(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> </div><div class='ctx'> static bool is_valid_ring_ptr(struct mhi_ring *ring, dma_addr_t addr)</div><div class='ctx'> {</div><div class='del'>-	return addr &gt;= ring-&gt;iommu_base &amp;&amp; addr &lt; ring-&gt;iommu_base + ring-&gt;len;</div><div class='add'>+	return addr &gt;= ring-&gt;iommu_base &amp;&amp; addr &lt; ring-&gt;iommu_base + ring-&gt;len &amp;&amp;</div><div class='add'>+			!(addr &amp; (sizeof(struct mhi_ring_element) - 1));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mhi_destroy_device(struct device *dev, void *data)</div><div class='hunk'>@@ -642,6 +644,8 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 			mhi_del_ring_element(mhi_cntrl, tre_ring);</div><div class='ctx'> 			local_rp = tre_ring-&gt;rp;</div><div class='ctx'> </div><div class='add'>+			read_unlock_bh(&amp;mhi_chan-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 			/* notify client */</div><div class='ctx'> 			mhi_chan-&gt;xfer_cb(mhi_chan-&gt;mhi_dev, &amp;result);</div><div class='ctx'> </div><div class='hunk'>@@ -667,6 +671,8 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl,</div><div class='ctx'> 					kfree(buf_info-&gt;cb_buf);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			read_lock_bh(&amp;mhi_chan-&gt;lock);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	} /* CC_EOT */</div><div class='hunk'>@@ -1122,17 +1128,15 @@ static int mhi_queue(struct mhi_device *mhi_dev, struct mhi_buf_info *buf_info,</div><div class='ctx'> 	if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl-&gt;pm_state)))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='del'>-	read_lock_irqsave(&amp;mhi_cntrl-&gt;pm_lock, flags);</div><div class='del'>-</div><div class='ctx'> 	ret = mhi_is_ring_full(mhi_cntrl, tre_ring);</div><div class='del'>-	if (unlikely(ret)) {</div><div class='del'>-		ret = -EAGAIN;</div><div class='del'>-		goto exit_unlock;</div><div class='del'>-	}</div><div class='add'>+	if (unlikely(ret))</div><div class='add'>+		return -EAGAIN;</div><div class='ctx'> </div><div class='ctx'> 	ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf_info, mflags);</div><div class='ctx'> 	if (unlikely(ret))</div><div class='del'>-		goto exit_unlock;</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	read_lock_irqsave(&amp;mhi_cntrl-&gt;pm_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	/* Packet is queued, take a usage ref to exit M3 if necessary</div><div class='ctx'> 	 * for host-&gt;device buffer, balanced put is done on buffer completion</div><div class='hunk'>@@ -1152,7 +1156,6 @@ static int mhi_queue(struct mhi_device *mhi_dev, struct mhi_buf_info *buf_info,</div><div class='ctx'> 	if (dir == DMA_FROM_DEVICE)</div><div class='ctx'> 		mhi_cntrl-&gt;runtime_put(mhi_cntrl);</div><div class='ctx'> </div><div class='del'>-exit_unlock:</div><div class='ctx'> 	read_unlock_irqrestore(&amp;mhi_cntrl-&gt;pm_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1204,6 +1207,9 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,</div><div class='ctx'> 	int eot, eob, chain, bei;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/* Protect accesses for reading and incrementing WP */</div><div class='add'>+	write_lock_bh(&amp;mhi_chan-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	buf_ring = &amp;mhi_chan-&gt;buf_ring;</div><div class='ctx'> 	tre_ring = &amp;mhi_chan-&gt;tre_ring;</div><div class='ctx'> </div><div class='hunk'>@@ -1221,8 +1227,10 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,</div><div class='ctx'> </div><div class='ctx'> 	if (!info-&gt;pre_mapped) {</div><div class='ctx'> 		ret = mhi_cntrl-&gt;map_single(mhi_cntrl, buf_info);</div><div class='del'>-		if (ret)</div><div class='add'>+		if (ret) {</div><div class='add'>+			write_unlock_bh(&amp;mhi_chan-&gt;lock);</div><div class='ctx'> 			return ret;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	eob = !!(flags &amp; MHI_EOB);</div><div class='hunk'>@@ -1239,6 +1247,8 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,</div><div class='ctx'> 	mhi_add_ring_element(mhi_cntrl, tre_ring);</div><div class='ctx'> 	mhi_add_ring_element(mhi_cntrl, buf_ring);</div><div class='ctx'> </div><div class='add'>+	write_unlock_bh(&amp;mhi_chan-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c<br/>index 08f3f039dbdd..cd6cd14b3d29 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/pci_generic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/host/pci_generic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/pci_generic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/pci_generic.c</a></div><div class='hunk'>@@ -269,6 +269,16 @@ static struct mhi_event_config modem_qcom_v1_mhi_events[] = {</div><div class='ctx'> 	MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct mhi_controller_config modem_qcom_v2_mhiv_config = {</div><div class='add'>+	.max_channels = 128,</div><div class='add'>+	.timeout_ms = 8000,</div><div class='add'>+	.ready_timeout_ms = 50000,</div><div class='add'>+	.num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),</div><div class='add'>+	.ch_cfg = modem_qcom_v1_mhi_channels,</div><div class='add'>+	.num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),</div><div class='add'>+	.event_cfg = modem_qcom_v1_mhi_events,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {</div><div class='ctx'> 	.max_channels = 128,</div><div class='ctx'> 	.timeout_ms = 8000,</div><div class='hunk'>@@ -278,6 +288,16 @@ static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {</div><div class='ctx'> 	.event_cfg = modem_qcom_v1_mhi_events,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {</div><div class='add'>+	.name = "qcom-sdx75m",</div><div class='add'>+	.fw = "qcom/sdx75m/xbl.elf",</div><div class='add'>+	.edl = "qcom/sdx75m/edl.mbn",</div><div class='add'>+	.config = &amp;modem_qcom_v2_mhiv_config,</div><div class='add'>+	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,</div><div class='add'>+	.dma_data_width = 32,</div><div class='add'>+	.sideband_wake = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {</div><div class='ctx'> 	.name = "qcom-sdx65m",</div><div class='ctx'> 	.fw = "qcom/sdx65m/xbl.elf",</div><div class='hunk'>@@ -600,6 +620,8 @@ static const struct pci_device_id mhi_pci_id_table[] = {</div><div class='ctx'> 		.driver_data = (kernel_ulong_t) &amp;mhi_telit_fn990_info },</div><div class='ctx'> 	{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),</div><div class='ctx'> 		.driver_data = (kernel_ulong_t) &amp;mhi_qcom_sdx65_info },</div><div class='add'>+	{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),</div><div class='add'>+		.driver_data = (kernel_ulong_t) &amp;mhi_qcom_sdx75_info },</div><div class='ctx'> 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */</div><div class='ctx'> 		.driver_data = (kernel_ulong_t) &amp;mhi_quectel_em1xx_info },</div><div class='ctx'> 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */</div><div class='head'>diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c<br/>index 8a4362d75fc4..a2f2feef1476 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/mhi/host/pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/mhi/host/pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/mhi/host/pm.c</a></div><div class='hunk'>@@ -163,6 +163,7 @@ int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> 	enum mhi_pm_state cur_state;</div><div class='ctx'> 	struct device *dev = &amp;mhi_cntrl-&gt;mhi_dev-&gt;dev;</div><div class='ctx'> 	u32 interval_us = 25000; /* poll register field every 25 milliseconds */</div><div class='add'>+	u32 timeout_ms;</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	/* Check if device entered error state */</div><div class='hunk'>@@ -173,14 +174,18 @@ int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for RESET to be cleared and READY bit to be set by the device */</div><div class='ctx'> 	ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl-&gt;regs, MHICTRL,</div><div class='del'>-				 MHICTRL_RESET_MASK, 0, interval_us);</div><div class='add'>+				 MHICTRL_RESET_MASK, 0, interval_us,</div><div class='add'>+				 mhi_cntrl-&gt;timeout_ms);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Device failed to clear MHI Reset\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	timeout_ms = mhi_cntrl-&gt;ready_timeout_ms ?</div><div class='add'>+		mhi_cntrl-&gt;ready_timeout_ms : mhi_cntrl-&gt;timeout_ms;</div><div class='ctx'> 	ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl-&gt;regs, MHISTATUS,</div><div class='del'>-				 MHISTATUS_READY_MASK, 1, interval_us);</div><div class='add'>+				 MHISTATUS_READY_MASK, 1, interval_us,</div><div class='add'>+				 timeout_ms);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Device failed to enter MHI Ready\n");</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -479,7 +484,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> </div><div class='ctx'> 		/* Wait for the reset bit to be cleared by the device */</div><div class='ctx'> 		ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl-&gt;regs, MHICTRL,</div><div class='del'>-				 MHICTRL_RESET_MASK, 0, 25000);</div><div class='add'>+				 MHICTRL_RESET_MASK, 0, 25000, mhi_cntrl-&gt;timeout_ms);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			dev_err(dev, "Device failed to clear MHI Reset\n");</div><div class='ctx'> </div><div class='hunk'>@@ -492,8 +497,8 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> 		if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {</div><div class='ctx'> 			/* wait for ready to be set */</div><div class='ctx'> 			ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl-&gt;regs,</div><div class='del'>-						 MHISTATUS,</div><div class='del'>-						 MHISTATUS_READY_MASK, 1, 25000);</div><div class='add'>+						 MHISTATUS, MHISTATUS_READY_MASK,</div><div class='add'>+						 1, 25000, mhi_cntrl-&gt;timeout_ms);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				dev_err(dev, "Device failed to enter READY state\n");</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1111,7 +1116,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> 	if (state == MHI_STATE_SYS_ERR) {</div><div class='ctx'> 		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);</div><div class='ctx'> 		ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl-&gt;regs, MHICTRL,</div><div class='del'>-				 MHICTRL_RESET_MASK, 0, interval_us);</div><div class='add'>+				 MHICTRL_RESET_MASK, 0, interval_us,</div><div class='add'>+				 mhi_cntrl-&gt;timeout_ms);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_info(dev, "Failed to reset MHI due to syserr state\n");</div><div class='ctx'> 			goto error_exit;</div><div class='hunk'>@@ -1202,14 +1208,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);</div><div class='ctx'> int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = mhi_async_power_up(mhi_cntrl);</div><div class='add'>+	u32 timeout_ms;</div><div class='ctx'> </div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	/* Some devices need more time to set ready during power up */</div><div class='add'>+	timeout_ms = mhi_cntrl-&gt;ready_timeout_ms ?</div><div class='add'>+		mhi_cntrl-&gt;ready_timeout_ms : mhi_cntrl-&gt;timeout_ms;</div><div class='ctx'> 	wait_event_timeout(mhi_cntrl-&gt;state_event,</div><div class='ctx'> 			   MHI_IN_MISSION_MODE(mhi_cntrl-&gt;ee) ||</div><div class='ctx'> 			   MHI_PM_IN_ERROR_STATE(mhi_cntrl-&gt;pm_state),</div><div class='del'>-			   msecs_to_jiffies(mhi_cntrl-&gt;timeout_ms));</div><div class='add'>+			   msecs_to_jiffies(timeout_ms));</div><div class='ctx'> </div><div class='ctx'> 	ret = (MHI_IN_MISSION_MODE(mhi_cntrl-&gt;ee)) ? 0 : -ETIMEDOUT;</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/bus/moxtet.c b/drivers/bus/moxtet.c<br/>index 5eb0fe73ddc4..641c1a6adc8a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/moxtet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/moxtet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/moxtet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/moxtet.c</a></div><div class='hunk'>@@ -102,7 +102,7 @@ static int moxtet_match(struct device *dev, struct device_driver *drv)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct bus_type moxtet_bus_type = {</div><div class='add'>+static const struct bus_type moxtet_bus_type = {</div><div class='ctx'> 	.name		= "moxtet",</div><div class='ctx'> 	.dev_groups	= moxtet_dev_groups,</div><div class='ctx'> 	.match		= moxtet_match,</div><div class='hunk'>@@ -755,7 +755,7 @@ static int moxtet_irq_setup(struct moxtet *moxtet)</div><div class='ctx'> 	moxtet-&gt;irq.masked = ~0;</div><div class='ctx'> </div><div class='ctx'> 	ret = request_threaded_irq(moxtet-&gt;dev_irq, NULL, moxtet_irq_thread_fn,</div><div class='del'>-				   IRQF_ONESHOT, "moxtet", moxtet);</div><div class='add'>+				   IRQF_SHARED | IRQF_ONESHOT, "moxtet", moxtet);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> </div><div class='hunk'>@@ -830,6 +830,12 @@ static void moxtet_remove(struct spi_device *spi)</div><div class='ctx'> 	mutex_destroy(&amp;moxtet-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct spi_device_id moxtet_spi_ids[] = {</div><div class='add'>+	{ "moxtet" },</div><div class='add'>+	{ },</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, moxtet_spi_ids);</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id moxtet_dt_ids[] = {</div><div class='ctx'> 	{ .compatible = "cznic,moxtet" },</div><div class='ctx'> 	{},</div><div class='hunk'>@@ -841,6 +847,7 @@ static struct spi_driver moxtet_spi_driver = {</div><div class='ctx'> 		.name		= "moxtet",</div><div class='ctx'> 		.of_match_table = moxtet_dt_ids,</div><div class='ctx'> 	},</div><div class='add'>+	.id_table	= moxtet_spi_ids,</div><div class='ctx'> 	.probe		= moxtet_probe,</div><div class='ctx'> 	.remove		= moxtet_remove,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c<br/>index e02d0656242b..7d7479ba0a75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/omap-ocp2scp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/omap-ocp2scp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/omap-ocp2scp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/omap-ocp2scp.c</a></div><div class='hunk'>@@ -84,12 +84,10 @@ err0:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int omap_ocp2scp_remove(struct platform_device *pdev)</div><div class='add'>+static void omap_ocp2scp_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	device_for_each_child(&amp;pdev-&gt;dev, NULL, ocp2scp_remove_devices);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_OF</div><div class='hunk'>@@ -103,7 +101,7 @@ MODULE_DEVICE_TABLE(of, omap_ocp2scp_id_table);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver omap_ocp2scp_driver = {</div><div class='ctx'> 	.probe		= omap_ocp2scp_probe,</div><div class='del'>-	.remove		= omap_ocp2scp_remove,</div><div class='add'>+	.remove_new	= omap_ocp2scp_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "omap-ocp2scp",</div><div class='ctx'> 		.of_match_table = of_match_ptr(omap_ocp2scp_id_table),</div><div class='head'>diff --git a/drivers/bus/omap_l3_smx.c b/drivers/bus/omap_l3_smx.c<br/>index 31774648be9d..ee6d29925e4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/omap_l3_smx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/omap_l3_smx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/omap_l3_smx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/omap_l3_smx.c</a></div><div class='hunk'>@@ -261,7 +261,7 @@ err0:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int omap3_l3_remove(struct platform_device *pdev)</div><div class='add'>+static void omap3_l3_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct omap3_l3         *l3 = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -269,13 +269,11 @@ static int omap3_l3_remove(struct platform_device *pdev)</div><div class='ctx'> 	free_irq(l3-&gt;debug_irq, l3);</div><div class='ctx'> 	iounmap(l3-&gt;rt);</div><div class='ctx'> 	kfree(l3);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver omap3_l3_driver = {</div><div class='ctx'> 	.probe		= omap3_l3_probe,</div><div class='del'>-	.remove         = omap3_l3_remove,</div><div class='add'>+	.remove_new     = omap3_l3_remove,</div><div class='ctx'> 	.driver         = {</div><div class='ctx'> 		.name   = "omap_l3_smx",</div><div class='ctx'> 		.of_match_table = of_match_ptr(omap3_l3_match),</div><div class='head'>diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c<br/>index 3fef18a43c01..5931974a21fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/qcom-ssc-block-bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/qcom-ssc-block-bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/qcom-ssc-block-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/qcom-ssc-block-bus.c</a></div><div class='hunk'>@@ -350,7 +350,7 @@ static int qcom_ssc_block_bus_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qcom_ssc_block_bus_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_ssc_block_bus_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -363,8 +363,6 @@ static int qcom_ssc_block_bus_remove(struct platform_device *pdev)</div><div class='ctx'> 	qcom_ssc_block_bus_pds_detach(&amp;pdev-&gt;dev, data-&gt;pds, data-&gt;num_pds);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_clk_destroy(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id qcom_ssc_block_bus_of_match[] = {</div><div class='hunk'>@@ -375,7 +373,7 @@ MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcom_ssc_block_bus_driver = {</div><div class='ctx'> 	.probe = qcom_ssc_block_bus_probe,</div><div class='del'>-	.remove = qcom_ssc_block_bus_remove,</div><div class='add'>+	.remove_new = qcom_ssc_block_bus_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom-ssc-block-bus",</div><div class='ctx'> 		.of_match_table = qcom_ssc_block_bus_of_match,</div><div class='head'>diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c<br/>index aafcc481de91..50870c827889 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/simple-pm-bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/simple-pm-bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/simple-pm-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/simple-pm-bus.c</a></div><div class='hunk'>@@ -74,17 +74,16 @@ static int simple_pm_bus_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int simple_pm_bus_remove(struct platform_device *pdev)</div><div class='add'>+static void simple_pm_bus_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	const void *data = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (pdev-&gt;driver_override || data)</div><div class='del'>-		return 0;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "%s\n", __func__);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int simple_pm_bus_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -129,7 +128,7 @@ MODULE_DEVICE_TABLE(of, simple_pm_bus_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver simple_pm_bus_driver = {</div><div class='ctx'> 	.probe = simple_pm_bus_probe,</div><div class='del'>-	.remove = simple_pm_bus_remove,</div><div class='add'>+	.remove_new = simple_pm_bus_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "simple-pm-bus",</div><div class='ctx'> 		.of_match_table = simple_pm_bus_of_match,</div><div class='head'>diff --git a/drivers/bus/sun50i-de2.c b/drivers/bus/sun50i-de2.c<br/>index 414f29cdedf0..3339311ce068 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/sun50i-de2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/sun50i-de2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/sun50i-de2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/sun50i-de2.c</a></div><div class='hunk'>@@ -24,10 +24,9 @@ static int sun50i_de2_bus_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sun50i_de2_bus_remove(struct platform_device *pdev)</div><div class='add'>+static void sun50i_de2_bus_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	sunxi_sram_release(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id sun50i_de2_bus_of_match[] = {</div><div class='hunk'>@@ -37,7 +36,7 @@ static const struct of_device_id sun50i_de2_bus_of_match[] = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sun50i_de2_bus_driver = {</div><div class='ctx'> 	.probe = sun50i_de2_bus_probe,</div><div class='del'>-	.remove = sun50i_de2_bus_remove,</div><div class='add'>+	.remove_new = sun50i_de2_bus_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "sun50i-de2-bus",</div><div class='ctx'> 		.of_match_table = sun50i_de2_bus_of_match,</div><div class='head'>diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c<br/>index db0ed4e5d315..fd3e9d82340a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/sunxi-rsb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/sunxi-rsb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/sunxi-rsb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/sunxi-rsb.c</a></div><div class='hunk'>@@ -817,15 +817,13 @@ static int sunxi_rsb_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sunxi_rsb_remove(struct platform_device *pdev)</div><div class='add'>+static void sunxi_rsb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sunxi_rsb *rsb = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	device_for_each_child(rsb-&gt;dev, NULL, sunxi_rsb_remove_devices);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	sunxi_rsb_hw_exit(rsb);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pm_ops sunxi_rsb_dev_pm_ops = {</div><div class='hunk'>@@ -842,7 +840,7 @@ MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sunxi_rsb_driver = {</div><div class='ctx'> 	.probe = sunxi_rsb_probe,</div><div class='del'>-	.remove	= sunxi_rsb_remove,</div><div class='add'>+	.remove_new = sunxi_rsb_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = RSB_CTRL_NAME,</div><div class='ctx'> 		.of_match_table = sunxi_rsb_of_match_table,</div><div class='head'>diff --git a/drivers/bus/tegra-aconnect.c b/drivers/bus/tegra-aconnect.c<br/>index ac58142301f4..de80008bff92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/tegra-aconnect.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/tegra-aconnect.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/tegra-aconnect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/tegra-aconnect.c</a></div><div class='hunk'>@@ -53,11 +53,9 @@ static int tegra_aconnect_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tegra_aconnect_remove(struct platform_device *pdev)</div><div class='add'>+static void tegra_aconnect_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int tegra_aconnect_runtime_resume(struct device *dev)</div><div class='hunk'>@@ -106,7 +104,7 @@ MODULE_DEVICE_TABLE(of, tegra_aconnect_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver tegra_aconnect_driver = {</div><div class='ctx'> 	.probe = tegra_aconnect_probe,</div><div class='del'>-	.remove = tegra_aconnect_remove,</div><div class='add'>+	.remove_new = tegra_aconnect_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "tegra-aconnect",</div><div class='ctx'> 		.of_match_table = tegra_aconnect_of_match,</div><div class='head'>diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c<br/>index 59919e99f7cc..f5d6414df9f2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/tegra-gmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/tegra-gmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/tegra-gmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/tegra-gmi.c</a></div><div class='hunk'>@@ -258,14 +258,12 @@ static int tegra_gmi_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tegra_gmi_remove(struct platform_device *pdev)</div><div class='add'>+static void tegra_gmi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tegra_gmi *gmi = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	of_platform_depopulate(gmi-&gt;dev);</div><div class='ctx'> 	tegra_gmi_disable(gmi);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused tegra_gmi_runtime_resume(struct device *dev)</div><div class='hunk'>@@ -305,7 +303,7 @@ MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver tegra_gmi_driver = {</div><div class='ctx'> 	.probe = tegra_gmi_probe,</div><div class='del'>-	.remove = tegra_gmi_remove,</div><div class='add'>+	.remove_new = tegra_gmi_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "tegra-gmi",</div><div class='ctx'> 		.of_match_table	= tegra_gmi_id_table,</div><div class='head'>diff --git a/drivers/bus/ti-pwmss.c b/drivers/bus/ti-pwmss.c<br/>index 480a4de76cd4..4969c556e752 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/ti-pwmss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/ti-pwmss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/ti-pwmss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ti-pwmss.c</a></div><div class='hunk'>@@ -33,10 +33,9 @@ static int pwmss_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pwmss_remove(struct platform_device *pdev)</div><div class='add'>+static void pwmss_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver pwmss_driver = {</div><div class='hunk'>@@ -45,7 +44,7 @@ static struct platform_driver pwmss_driver = {</div><div class='ctx'> 		.of_match_table	= pwmss_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe	= pwmss_probe,</div><div class='del'>-	.remove	= pwmss_remove,</div><div class='add'>+	.remove_new = pwmss_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(pwmss_driver);</div><div class='head'>diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c<br/>index d57bc066dce6..245e5e827d0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/ti-sysc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/ti-sysc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/ti-sysc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ti-sysc.c</a></div><div class='hunk'>@@ -2158,13 +2158,23 @@ static int sysc_reset(struct sysc *ddata)</div><div class='ctx'> 		sysc_val = sysc_read_sysconfig(ddata);</div><div class='ctx'> 		sysc_val |= sysc_mask;</div><div class='ctx'> 		sysc_write(ddata, sysc_offset, sysc_val);</div><div class='del'>-		/* Flush posted write */</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Some devices need a delay before reading registers</div><div class='add'>+		 * after reset. Presumably a srst_udelay is not needed</div><div class='add'>+		 * for devices that use a rstctrl register reset.</div><div class='add'>+		 */</div><div class='add'>+		if (ddata-&gt;cfg.srst_udelay)</div><div class='add'>+			fsleep(ddata-&gt;cfg.srst_udelay);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Flush posted write. For devices needing srst_udelay</div><div class='add'>+		 * this should trigger an interconnect error if the</div><div class='add'>+		 * srst_udelay value is needed but not configured.</div><div class='add'>+		 */</div><div class='ctx'> 		sysc_val = sysc_read_sysconfig(ddata);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ddata-&gt;cfg.srst_udelay)</div><div class='del'>-		fsleep(ddata-&gt;cfg.srst_udelay);</div><div class='del'>-</div><div class='ctx'> 	if (ddata-&gt;post_reset_quirk)</div><div class='ctx'> 		ddata-&gt;post_reset_quirk(ddata);</div><div class='ctx'> </div><div class='hunk'>@@ -3387,7 +3397,7 @@ unprepare:</div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sysc_remove(struct platform_device *pdev)</div><div class='add'>+static void sysc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sysc *ddata = platform_get_drvdata(pdev);</div><div class='ctx'> 	int error;</div><div class='hunk'>@@ -3412,8 +3422,6 @@ static int sysc_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> unprepare:</div><div class='ctx'> 	sysc_unprepare(ddata);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id sysc_match[] = {</div><div class='hunk'>@@ -3439,7 +3447,7 @@ MODULE_DEVICE_TABLE(of, sysc_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sysc_driver = {</div><div class='ctx'> 	.probe		= sysc_probe,</div><div class='del'>-	.remove		= sysc_remove,</div><div class='add'>+	.remove_new	= sysc_remove,</div><div class='ctx'> 	.driver         = {</div><div class='ctx'> 		.name   = "ti-sysc",</div><div class='ctx'> 		.of_match_table	= sysc_match,</div><div class='head'>diff --git a/drivers/bus/ts-nbus.c b/drivers/bus/ts-nbus.c<br/>index 38c886dc2ed6..4fa932cb0915 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/bus/ts-nbus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/bus/ts-nbus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/bus/ts-nbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/bus/ts-nbus.c</a></div><div class='hunk'>@@ -331,7 +331,7 @@ static int ts_nbus_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ts_nbus_remove(struct platform_device *pdev)</div><div class='add'>+static void ts_nbus_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ts_nbus *ts_nbus = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -339,8 +339,6 @@ static int ts_nbus_remove(struct platform_device *pdev)</div><div class='ctx'> 	mutex_lock(&amp;ts_nbus-&gt;lock);</div><div class='ctx'> 	pwm_disable(ts_nbus-&gt;pwm);</div><div class='ctx'> 	mutex_unlock(&amp;ts_nbus-&gt;lock);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ts_nbus_of_match[] = {</div><div class='hunk'>@@ -351,7 +349,7 @@ MODULE_DEVICE_TABLE(of, ts_nbus_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ts_nbus_driver = {</div><div class='ctx'> 	.probe		= ts_nbus_probe,</div><div class='del'>-	.remove		= ts_nbus_remove,</div><div class='add'>+	.remove_new	= ts_nbus_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "ts_nbus",</div><div class='ctx'> 		.of_match_table = ts_nbus_of_match,</div><div class='head'>diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig<br/>index d6e5e3abaad8..9345ce4976d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cache/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cache/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cache/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/Kconfig</a></div><div class='hunk'>@@ -8,4 +8,10 @@ config AX45MP_L2_CACHE</div><div class='ctx'> 	help</div><div class='ctx'> 	  Support for the L2 cache controller on Andes Technology AX45MP platforms.</div><div class='ctx'> </div><div class='add'>+config SIFIVE_CCACHE</div><div class='add'>+	bool "Sifive Composable Cache controller"</div><div class='add'>+	depends on ARCH_SIFIVE || ARCH_STARFIVE</div><div class='add'>+	help</div><div class='add'>+	  Support for the composable cache controller on SiFive platforms.</div><div class='add'>+</div><div class='ctx'> endmenu</div><div class='head'>diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile<br/>index 2012e7fb978d..7657cff3bd6c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cache/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cache/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cache/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/Makefile</a></div><div class='hunk'>@@ -1,3 +1,4 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> </div><div class='del'>-obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o</div><div class='add'>+obj-$(CONFIG_AX45MP_L2_CACHE)	+= ax45mp_cache.o</div><div class='add'>+obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o</div><div class='head'>diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/cache/sifive_ccache.c<br/>index 3684f5b40a80..89ed6cd6b059 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/soc/sifive/sifive_ccache.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/soc/sifive/sifive_ccache.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cache/sifive_ccache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cache/sifive_ccache.c</a></div><div class='hunk'>@@ -8,13 +8,16 @@</div><div class='ctx'> </div><div class='ctx'> #define pr_fmt(fmt) "CCACHE: " fmt</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/of_irq.h&gt;</div><div class='ctx'> #include &lt;linux/of_address.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;asm/cacheflush.h&gt;</div><div class='ctx'> #include &lt;asm/cacheinfo.h&gt;</div><div class='add'>+#include &lt;asm/dma-noncoherent.h&gt;</div><div class='ctx'> #include &lt;soc/sifive/sifive_ccache.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100</div><div class='hunk'>@@ -39,10 +42,14 @@</div><div class='ctx'> #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)</div><div class='ctx'> #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)</div><div class='ctx'> </div><div class='add'>+#define SIFIVE_CCACHE_FLUSH64 0x200</div><div class='add'>+#define SIFIVE_CCACHE_FLUSH32 0x240</div><div class='add'>+</div><div class='ctx'> #define SIFIVE_CCACHE_WAYENABLE 0x08</div><div class='ctx'> #define SIFIVE_CCACHE_ECCINJECTERR 0x40</div><div class='ctx'> </div><div class='ctx'> #define SIFIVE_CCACHE_MAX_ECCINTR 4</div><div class='add'>+#define SIFIVE_CCACHE_LINE_SIZE 64</div><div class='ctx'> </div><div class='ctx'> static void __iomem *ccache_base;</div><div class='ctx'> static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];</div><div class='hunk'>@@ -56,6 +63,11 @@ enum {</div><div class='ctx'> 	DIR_UNCORR,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum {</div><div class='add'>+	QUIRK_NONSTANDARD_CACHE_OPS	= BIT(0),</div><div class='add'>+	QUIRK_BROKEN_DATA_UNCORR	= BIT(1),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_DEBUG_FS</div><div class='ctx'> static struct dentry *sifive_test;</div><div class='ctx'> </div><div class='hunk'>@@ -106,6 +118,8 @@ static void ccache_config_read(void)</div><div class='ctx'> static const struct of_device_id sifive_ccache_ids[] = {</div><div class='ctx'> 	{ .compatible = "sifive,fu540-c000-ccache" },</div><div class='ctx'> 	{ .compatible = "sifive,fu740-c000-ccache" },</div><div class='add'>+	{ .compatible = "starfive,jh7100-ccache",</div><div class='add'>+	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },</div><div class='ctx'> 	{ .compatible = "sifive,ccache0" },</div><div class='ctx'> 	{ /* end of table */ }</div><div class='ctx'> };</div><div class='hunk'>@@ -124,6 +138,34 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS</div><div class='add'>+static void ccache_flush_range(phys_addr_t start, size_t len)</div><div class='add'>+{</div><div class='add'>+	phys_addr_t end = start + len;</div><div class='add'>+	phys_addr_t line;</div><div class='add'>+</div><div class='add'>+	if (!len)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mb();</div><div class='add'>+	for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line &lt; end;</div><div class='add'>+			line += SIFIVE_CCACHE_LINE_SIZE) {</div><div class='add'>+#ifdef CONFIG_32BIT</div><div class='add'>+		writel(line &gt;&gt; 4, ccache_base + SIFIVE_CCACHE_FLUSH32);</div><div class='add'>+#else</div><div class='add'>+		writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);</div><div class='add'>+#endif</div><div class='add'>+		mb();</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {</div><div class='add'>+	.wback = &amp;ccache_flush_range,</div><div class='add'>+	.inv = &amp;ccache_flush_range,</div><div class='add'>+	.wback_inv = &amp;ccache_flush_range,</div><div class='add'>+};</div><div class='add'>+#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */</div><div class='add'>+</div><div class='ctx'> static int ccache_largest_wayenabled(void)</div><div class='ctx'> {</div><div class='ctx'> 	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) &amp; 0xFF;</div><div class='hunk'>@@ -210,11 +252,15 @@ static int __init sifive_ccache_init(void)</div><div class='ctx'> 	struct device_node *np;</div><div class='ctx'> 	struct resource res;</div><div class='ctx'> 	int i, rc, intr_num;</div><div class='add'>+	const struct of_device_id *match;</div><div class='add'>+	unsigned long quirks;</div><div class='ctx'> </div><div class='del'>-	np = of_find_matching_node(NULL, sifive_ccache_ids);</div><div class='add'>+	np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &amp;match);</div><div class='ctx'> 	if (!np)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='add'>+	quirks = (uintptr_t)match-&gt;data;</div><div class='add'>+</div><div class='ctx'> 	if (of_address_to_resource(np, 0, &amp;res)) {</div><div class='ctx'> 		rc = -ENODEV;</div><div class='ctx'> 		goto err_node_put;</div><div class='hunk'>@@ -240,6 +286,10 @@ static int __init sifive_ccache_init(void)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; intr_num; i++) {</div><div class='ctx'> 		g_irq[i] = irq_of_parse_and_map(np, i);</div><div class='add'>+</div><div class='add'>+		if (i == DATA_UNCORR &amp;&amp; (quirks &amp; QUIRK_BROKEN_DATA_UNCORR))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",</div><div class='ctx'> 				 NULL);</div><div class='ctx'> 		if (rc) {</div><div class='hunk'>@@ -249,6 +299,14 @@ static int __init sifive_ccache_init(void)</div><div class='ctx'> 	}</div><div class='ctx'> 	of_node_put(np);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS</div><div class='add'>+	if (quirks &amp; QUIRK_NONSTANDARD_CACHE_OPS) {</div><div class='add'>+		riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;</div><div class='add'>+		riscv_noncoherent_supported();</div><div class='add'>+		riscv_noncoherent_register_cache_ops(&amp;ccache_mgmt_ops);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	ccache_config_read();</div><div class='ctx'> </div><div class='ctx'> 	ccache_cache_ops.get_priv_group = ccache_get_priv_group;</div><div class='hunk'>@@ -269,4 +327,4 @@ err_node_put:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-device_initcall(sifive_ccache_init);</div><div class='add'>+arch_initcall(sifive_ccache_init);</div><div class='head'>diff --git a/drivers/cdx/cdx.c b/drivers/cdx/cdx.c<br/>index 4461c6c9313f..b74d76afccb6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cdx/cdx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cdx/cdx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cdx/cdx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cdx/cdx.c</a></div><div class='hunk'>@@ -57,13 +57,17 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/mm.h&gt;</div><div class='ctx'> #include &lt;linux/idr.h&gt;</div><div class='ctx'> #include &lt;linux/cdx/cdx_bus.h&gt;</div><div class='ctx'> #include &lt;linux/iommu.h&gt;</div><div class='ctx'> #include &lt;linux/dma-map-ops.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include "cdx.h"</div><div class='ctx'> </div><div class='ctx'> /* Default DMA mask for devices on a CDX bus */</div><div class='hunk'>@@ -74,9 +78,13 @@</div><div class='ctx'> static DEFINE_IDA(cdx_controller_ida);</div><div class='ctx'> /* Lock to protect controller ops */</div><div class='ctx'> static DEFINE_MUTEX(cdx_controller_lock);</div><div class='add'>+/* Debugfs dir for cdx bus */</div><div class='add'>+static struct dentry *cdx_debugfs_dir;</div><div class='ctx'> </div><div class='ctx'> static char *compat_node_name = "xlnx,versal-net-cdx";</div><div class='ctx'> </div><div class='add'>+static void cdx_destroy_res_attr(struct cdx_device *cdx_dev, int num);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * cdx_dev_reset - Reset a CDX device</div><div class='ctx'>  * @dev: CDX device</div><div class='hunk'>@@ -145,6 +153,8 @@ static int cdx_unregister_device(struct device *dev,</div><div class='ctx'> 		if (cdx_dev-&gt;enabled &amp;&amp; cdx-&gt;ops-&gt;bus_disable)</div><div class='ctx'> 			cdx-&gt;ops-&gt;bus_disable(cdx, cdx_dev-&gt;bus_num);</div><div class='ctx'> 	} else {</div><div class='add'>+		cdx_destroy_res_attr(cdx_dev, MAX_CDX_DEV_RESOURCES);</div><div class='add'>+		debugfs_remove_recursive(cdx_dev-&gt;debugfs_dir);</div><div class='ctx'> 		kfree(cdx_dev-&gt;driver_override);</div><div class='ctx'> 		cdx_dev-&gt;driver_override = NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -548,6 +558,31 @@ static const struct attribute_group *cdx_dev_groups[] = {</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int cdx_debug_resource_show(struct seq_file *s, void *data)</div><div class='add'>+{</div><div class='add'>+	struct cdx_device *cdx_dev = s-&gt;private;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_CDX_DEV_RESOURCES; i++) {</div><div class='add'>+		struct resource *res =  &amp;cdx_dev-&gt;res[i];</div><div class='add'>+</div><div class='add'>+		seq_printf(s, "%pr\n", res);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(cdx_debug_resource);</div><div class='add'>+</div><div class='add'>+static void cdx_device_debugfs_init(struct cdx_device *cdx_dev)</div><div class='add'>+{</div><div class='add'>+	cdx_dev-&gt;debugfs_dir = debugfs_create_dir(dev_name(&amp;cdx_dev-&gt;dev), cdx_debugfs_dir);</div><div class='add'>+	if (IS_ERR(cdx_dev-&gt;debugfs_dir))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("resource", 0444, cdx_dev-&gt;debugfs_dir, cdx_dev,</div><div class='add'>+			    &amp;cdx_debug_resource_fops);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t rescan_store(const struct bus_type *bus,</div><div class='ctx'> 			    const char *buf, size_t count)</div><div class='ctx'> {</div><div class='hunk'>@@ -569,12 +604,12 @@ static ssize_t rescan_store(const struct bus_type *bus,</div><div class='ctx'> </div><div class='ctx'> 	/* Rescan all the devices */</div><div class='ctx'> 	for_each_compatible_node(np, NULL, compat_node_name) {</div><div class='del'>-		if (!np)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 		pd = of_find_device_by_node(np);</div><div class='del'>-		if (!pd)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		if (!pd) {</div><div class='add'>+			of_node_put(np);</div><div class='add'>+			count = -EINVAL;</div><div class='add'>+			goto unlock;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		cdx = platform_get_drvdata(pd);</div><div class='ctx'> 		if (cdx &amp;&amp; cdx-&gt;controller_registered &amp;&amp; cdx-&gt;ops-&gt;scan)</div><div class='hunk'>@@ -583,6 +618,7 @@ static ssize_t rescan_store(const struct bus_type *bus,</div><div class='ctx'> 		put_device(&amp;pd-&gt;dev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+unlock:</div><div class='ctx'> 	mutex_unlock(&amp;cdx_controller_lock);</div><div class='ctx'> </div><div class='ctx'> 	return count;</div><div class='hunk'>@@ -640,11 +676,105 @@ static void cdx_device_release(struct device *dev)</div><div class='ctx'> 	kfree(cdx_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct vm_operations_struct cdx_phys_vm_ops = {</div><div class='add'>+#ifdef CONFIG_HAVE_IOREMAP_PROT</div><div class='add'>+	.access = generic_access_phys,</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * cdx_mmap_resource - map a CDX resource into user memory space</div><div class='add'>+ * @fp: File pointer. Not used in this function, but required where</div><div class='add'>+ *      this API is registered as a callback.</div><div class='add'>+ * @kobj: kobject for mapping</div><div class='add'>+ * @attr: struct bin_attribute for the file being mapped</div><div class='add'>+ * @vma: struct vm_area_struct passed into the mmap</div><div class='add'>+ *</div><div class='add'>+ * Use the regular CDX mapping routines to map a CDX resource into userspace.</div><div class='add'>+ *</div><div class='add'>+ * Return: true on success, false otherwise.</div><div class='add'>+ */</div><div class='add'>+static int cdx_mmap_resource(struct file *fp, struct kobject *kobj,</div><div class='add'>+			     struct bin_attribute *attr,</div><div class='add'>+			     struct vm_area_struct *vma)</div><div class='add'>+{</div><div class='add'>+	struct cdx_device *cdx_dev = to_cdx_device(kobj_to_dev(kobj));</div><div class='add'>+	int num = (unsigned long)attr-&gt;private;</div><div class='add'>+	struct resource *res;</div><div class='add'>+	unsigned long size;</div><div class='add'>+</div><div class='add'>+	res = &amp;cdx_dev-&gt;res[num];</div><div class='add'>+	if (iomem_is_exclusive(res-&gt;start))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Make sure the caller is mapping a valid resource for this device */</div><div class='add'>+	size = ((cdx_resource_len(cdx_dev, num) - 1) &gt;&gt; PAGE_SHIFT) + 1;</div><div class='add'>+	if (vma-&gt;vm_pgoff + vma_pages(vma) &gt; size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Map memory region and vm-&gt;vm_pgoff is expected to be an</div><div class='add'>+	 * offset within that region.</div><div class='add'>+	 */</div><div class='add'>+	vma-&gt;vm_page_prot = pgprot_device(vma-&gt;vm_page_prot);</div><div class='add'>+	vma-&gt;vm_pgoff += (cdx_resource_start(cdx_dev, num) &gt;&gt; PAGE_SHIFT);</div><div class='add'>+	vma-&gt;vm_ops = &amp;cdx_phys_vm_ops;</div><div class='add'>+	return io_remap_pfn_range(vma, vma-&gt;vm_start, vma-&gt;vm_pgoff,</div><div class='add'>+				  vma-&gt;vm_end - vma-&gt;vm_start,</div><div class='add'>+				  vma-&gt;vm_page_prot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void cdx_destroy_res_attr(struct cdx_device *cdx_dev, int num)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* removing the bin attributes */</div><div class='add'>+	for (i = 0; i &lt; num; i++) {</div><div class='add'>+		struct bin_attribute *res_attr;</div><div class='add'>+</div><div class='add'>+		res_attr = cdx_dev-&gt;res_attr[i];</div><div class='add'>+		if (res_attr) {</div><div class='add'>+			sysfs_remove_bin_file(&amp;cdx_dev-&gt;dev.kobj, res_attr);</div><div class='add'>+			kfree(res_attr);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define CDX_RES_ATTR_NAME_LEN	10</div><div class='add'>+static int cdx_create_res_attr(struct cdx_device *cdx_dev, int num)</div><div class='add'>+{</div><div class='add'>+	struct bin_attribute *res_attr;</div><div class='add'>+	char *res_attr_name;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	res_attr = kzalloc(sizeof(*res_attr) + CDX_RES_ATTR_NAME_LEN, GFP_ATOMIC);</div><div class='add'>+	if (!res_attr)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	res_attr_name = (char *)(res_attr + 1);</div><div class='add'>+</div><div class='add'>+	sysfs_bin_attr_init(res_attr);</div><div class='add'>+</div><div class='add'>+	cdx_dev-&gt;res_attr[num] = res_attr;</div><div class='add'>+	sprintf(res_attr_name, "resource%d", num);</div><div class='add'>+</div><div class='add'>+	res_attr-&gt;mmap = cdx_mmap_resource;</div><div class='add'>+	res_attr-&gt;attr.name = res_attr_name;</div><div class='add'>+	res_attr-&gt;attr.mode = 0600;</div><div class='add'>+	res_attr-&gt;size = cdx_resource_len(cdx_dev, num);</div><div class='add'>+	res_attr-&gt;private = (void *)(unsigned long)num;</div><div class='add'>+	ret = sysfs_create_bin_file(&amp;cdx_dev-&gt;dev.kobj, res_attr);</div><div class='add'>+	if (ret)</div><div class='add'>+		kfree(res_attr);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int cdx_device_add(struct cdx_dev_params *dev_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct cdx_controller *cdx = dev_params-&gt;cdx;</div><div class='ctx'> 	struct cdx_device *cdx_dev;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	cdx_dev = kzalloc(sizeof(*cdx_dev), GFP_KERNEL);</div><div class='ctx'> 	if (!cdx_dev)</div><div class='hunk'>@@ -687,7 +817,28 @@ int cdx_device_add(struct cdx_dev_params *dev_params)</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Create resource&lt;N&gt; attributes */</div><div class='add'>+	for (i = 0; i &lt; MAX_CDX_DEV_RESOURCES; i++) {</div><div class='add'>+		if (cdx_resource_flags(cdx_dev, i) &amp; IORESOURCE_MEM) {</div><div class='add'>+			/* skip empty resources */</div><div class='add'>+			if (!cdx_resource_len(cdx_dev, i))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			ret = cdx_create_res_attr(cdx_dev, i);</div><div class='add'>+			if (ret != 0) {</div><div class='add'>+				dev_err(&amp;cdx_dev-&gt;dev,</div><div class='add'>+					"cdx device resource&lt;%d&gt; file creation failed: %d", i, ret);</div><div class='add'>+				goto resource_create_fail;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cdx_device_debugfs_init(cdx_dev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+resource_create_fail:</div><div class='add'>+	cdx_destroy_res_attr(cdx_dev, i);</div><div class='add'>+	device_del(&amp;cdx_dev-&gt;dev);</div><div class='ctx'> fail:</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Do not free cdx_dev here as it would be freed in</div><div class='hunk'>@@ -788,6 +939,12 @@ EXPORT_SYMBOL_NS_GPL(cdx_unregister_controller, CDX_BUS_CONTROLLER);</div><div class='ctx'> </div><div class='ctx'> static int __init cdx_bus_init(void)</div><div class='ctx'> {</div><div class='del'>-	return bus_register(&amp;cdx_bus_type);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bus_register(&amp;cdx_bus_type);</div><div class='add'>+	if (!ret)</div><div class='add'>+		cdx_debugfs_dir = debugfs_create_dir(cdx_bus_type.name, NULL);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> postcore_initcall(cdx_bus_init);</div><div class='head'>diff --git a/drivers/char/hw_random/atmel-rng.c b/drivers/char/hw_random/atmel-rng.c<br/>index a37367ebcbac..e9157255f851 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/atmel-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/atmel-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/atmel-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/atmel-rng.c</a></div><div class='hunk'>@@ -161,15 +161,13 @@ static int atmel_trng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int atmel_trng_remove(struct platform_device *pdev)</div><div class='add'>+static void atmel_trng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct atmel_trng *trng = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	atmel_trng_cleanup(trng);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_set_suspended(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused atmel_trng_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -218,7 +216,7 @@ MODULE_DEVICE_TABLE(of, atmel_trng_dt_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver atmel_trng_driver = {</div><div class='ctx'> 	.probe		= atmel_trng_probe,</div><div class='del'>-	.remove		= atmel_trng_remove,</div><div class='add'>+	.remove_new	= atmel_trng_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "atmel-trng",</div><div class='ctx'> 		.pm	= pm_ptr(&amp;atmel_trng_pm_ops),</div><div class='head'>diff --git a/drivers/char/hw_random/cctrng.c b/drivers/char/hw_random/cctrng.c<br/>index 1abbff04a015..c0d2f824769f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/cctrng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/cctrng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/cctrng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/cctrng.c</a></div><div class='hunk'>@@ -560,7 +560,7 @@ post_pm_err:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cctrng_remove(struct platform_device *pdev)</div><div class='add'>+static void cctrng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct cctrng_drvdata *drvdata = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='hunk'>@@ -570,8 +570,6 @@ static int cctrng_remove(struct platform_device *pdev)</div><div class='ctx'> 	cc_trng_pm_fini(drvdata);</div><div class='ctx'> </div><div class='ctx'> 	dev_info(dev, "ARM cctrng device terminated\n");</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused cctrng_suspend(struct device *dev)</div><div class='hunk'>@@ -654,7 +652,7 @@ static struct platform_driver cctrng_driver = {</div><div class='ctx'> 		.pm = &amp;cctrng_pm,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = cctrng_probe,</div><div class='del'>-	.remove = cctrng_remove,</div><div class='add'>+	.remove_new = cctrng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(cctrng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c<br/>index 420f155d251f..a3bbdd6e60fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/core.c</a></div><div class='hunk'>@@ -23,10 +23,13 @@</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='ctx'> #include &lt;linux/sched/signal.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define RNG_MODULE_NAME		"hw_random"</div><div class='ctx'> </div><div class='add'>+#define RNG_BUFFER_SIZE (SMP_CACHE_BYTES &lt; 32 ? 32 : SMP_CACHE_BYTES)</div><div class='add'>+</div><div class='ctx'> static struct hwrng *current_rng;</div><div class='ctx'> /* the current rng has been explicitly chosen by user via sysfs */</div><div class='ctx'> static int cur_rng_set_by_user;</div><div class='hunk'>@@ -58,7 +61,7 @@ static inline int rng_get_data(struct hwrng *rng, u8 *buffer, size_t size,</div><div class='ctx'> </div><div class='ctx'> static size_t rng_buffer_size(void)</div><div class='ctx'> {</div><div class='del'>-	return SMP_CACHE_BYTES &lt; 32 ? 32 : SMP_CACHE_BYTES;</div><div class='add'>+	return RNG_BUFFER_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void add_early_randomness(struct hwrng *rng)</div><div class='hunk'>@@ -209,6 +212,7 @@ static inline int rng_get_data(struct hwrng *rng, u8 *buffer, size_t size,</div><div class='ctx'> static ssize_t rng_dev_read(struct file *filp, char __user *buf,</div><div class='ctx'> 			    size_t size, loff_t *offp)</div><div class='ctx'> {</div><div class='add'>+	u8 buffer[RNG_BUFFER_SIZE];</div><div class='ctx'> 	ssize_t ret = 0;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> 	int bytes_read, len;</div><div class='hunk'>@@ -236,34 +240,37 @@ static ssize_t rng_dev_read(struct file *filp, char __user *buf,</div><div class='ctx'> 			if (bytes_read &lt; 0) {</div><div class='ctx'> 				err = bytes_read;</div><div class='ctx'> 				goto out_unlock_reading;</div><div class='add'>+			} else if (bytes_read == 0 &amp;&amp;</div><div class='add'>+				   (filp-&gt;f_flags &amp; O_NONBLOCK)) {</div><div class='add'>+				err = -EAGAIN;</div><div class='add'>+				goto out_unlock_reading;</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='ctx'> 			data_avail = bytes_read;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!data_avail) {</div><div class='del'>-			if (filp-&gt;f_flags &amp; O_NONBLOCK) {</div><div class='del'>-				err = -EAGAIN;</div><div class='del'>-				goto out_unlock_reading;</div><div class='del'>-			}</div><div class='del'>-		} else {</div><div class='del'>-			len = data_avail;</div><div class='add'>+		len = data_avail;</div><div class='add'>+		if (len) {</div><div class='ctx'> 			if (len &gt; size)</div><div class='ctx'> 				len = size;</div><div class='ctx'> </div><div class='ctx'> 			data_avail -= len;</div><div class='ctx'> </div><div class='del'>-			if (copy_to_user(buf + ret, rng_buffer + data_avail,</div><div class='del'>-								len)) {</div><div class='add'>+			memcpy(buffer, rng_buffer + data_avail, len);</div><div class='add'>+		}</div><div class='add'>+		mutex_unlock(&amp;reading_mutex);</div><div class='add'>+		put_rng(rng);</div><div class='add'>+</div><div class='add'>+		if (len) {</div><div class='add'>+			if (copy_to_user(buf + ret, buffer, len)) {</div><div class='ctx'> 				err = -EFAULT;</div><div class='del'>-				goto out_unlock_reading;</div><div class='add'>+				goto out;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			size -= len;</div><div class='ctx'> 			ret += len;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		mutex_unlock(&amp;reading_mutex);</div><div class='del'>-		put_rng(rng);</div><div class='ctx'> </div><div class='ctx'> 		if (need_resched())</div><div class='ctx'> 			schedule_timeout_interruptible(1);</div><div class='hunk'>@@ -274,6 +281,7 @@ static ssize_t rng_dev_read(struct file *filp, char __user *buf,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='add'>+	memzero_explicit(buffer, sizeof(buffer));</div><div class='ctx'> 	return ret ? : err;</div><div class='ctx'> </div><div class='ctx'> out_unlock_reading:</div><div class='head'>diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c<br/>index 30207b7ac5f4..0ed5d22fe667 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/exynos-trng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/exynos-trng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/exynos-trng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/exynos-trng.c</a></div><div class='hunk'>@@ -173,7 +173,7 @@ err_pm_get:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_trng_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_trng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos_trng_dev *trng =  platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -181,8 +181,6 @@ static int exynos_trng_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int exynos_trng_suspend(struct device *dev)</div><div class='hunk'>@@ -223,7 +221,7 @@ static struct platform_driver exynos_trng_driver = {</div><div class='ctx'> 		.of_match_table = exynos_trng_dt_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = exynos_trng_probe,</div><div class='del'>-	.remove = exynos_trng_remove,</div><div class='add'>+	.remove_new = exynos_trng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(exynos_trng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/ingenic-rng.c b/drivers/char/hw_random/ingenic-rng.c<br/>index 4f18c3fa5427..2f9b6483c4a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/ingenic-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/ingenic-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/ingenic-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/ingenic-rng.c</a></div><div class='hunk'>@@ -11,7 +11,7 @@</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -114,15 +114,13 @@ static int ingenic_rng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ingenic_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void ingenic_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ingenic_rng *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	hwrng_unregister(&amp;priv-&gt;rng);</div><div class='ctx'> </div><div class='ctx'> 	writel(0, priv-&gt;base + RNG_REG_ERNG_OFFSET);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ingenic_rng_of_match[] = {</div><div class='hunk'>@@ -134,7 +132,7 @@ MODULE_DEVICE_TABLE(of, ingenic_rng_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ingenic_rng_driver = {</div><div class='ctx'> 	.probe		= ingenic_rng_probe,</div><div class='del'>-	.remove		= ingenic_rng_remove,</div><div class='add'>+	.remove_new	= ingenic_rng_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "ingenic-rng",</div><div class='ctx'> 		.of_match_table = ingenic_rng_of_match,</div><div class='head'>diff --git a/drivers/char/hw_random/jh7110-trng.c b/drivers/char/hw_random/jh7110-trng.c<br/>index 38474d48a25e..9776f4daa044 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/jh7110-trng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/jh7110-trng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/jh7110-trng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/jh7110-trng.c</a></div><div class='hunk'>@@ -300,7 +300,7 @@ static int starfive_trng_probe(struct platform_device *pdev)</div><div class='ctx'> 	ret = devm_request_irq(&amp;pdev-&gt;dev, irq, starfive_trng_irq, 0, pdev-&gt;name,</div><div class='ctx'> 			       (void *)trng);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(&amp;pdev-&gt;dev, irq,</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, ret,</div><div class='ctx'> 				     "Failed to register interrupt handler\n");</div><div class='ctx'> </div><div class='ctx'> 	trng-&gt;hclk = devm_clk_get(&amp;pdev-&gt;dev, "hclk");</div><div class='hunk'>@@ -369,8 +369,12 @@ static int __maybe_unused starfive_trng_resume(struct device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static DEFINE_SIMPLE_DEV_PM_OPS(starfive_trng_pm_ops, starfive_trng_suspend,</div><div class='del'>-				starfive_trng_resume);</div><div class='add'>+static const struct dev_pm_ops starfive_trng_pm_ops = {</div><div class='add'>+	SET_SYSTEM_SLEEP_PM_OPS(starfive_trng_suspend,</div><div class='add'>+				starfive_trng_resume)</div><div class='add'>+	SET_RUNTIME_PM_OPS(starfive_trng_suspend,</div><div class='add'>+			   starfive_trng_resume, NULL)</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id trng_dt_ids[] __maybe_unused = {</div><div class='ctx'> 	{ .compatible = "starfive,jh7110-trng" },</div><div class='head'>diff --git a/drivers/char/hw_random/ks-sa-rng.c b/drivers/char/hw_random/ks-sa-rng.c<br/>index dff7b9db7044..36c34252b4f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/ks-sa-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/ks-sa-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/ks-sa-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/ks-sa-rng.c</a></div><div class='hunk'>@@ -241,12 +241,10 @@ static int ks_sa_rng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return devm_hwrng_register(&amp;pdev-&gt;dev, &amp;ks_sa_rng-&gt;rng);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ks_sa_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void ks_sa_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ks_sa_rng_dt_match[] = {</div><div class='hunk'>@@ -263,7 +261,7 @@ static struct platform_driver ks_sa_rng_driver = {</div><div class='ctx'> 		.of_match_table = ks_sa_rng_dt_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= ks_sa_rng_probe,</div><div class='del'>-	.remove		= ks_sa_rng_remove,</div><div class='add'>+	.remove_new	= ks_sa_rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(ks_sa_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/mxc-rnga.c b/drivers/char/hw_random/mxc-rnga.c<br/>index 008763c988ed..07ec000e4cd7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/mxc-rnga.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/mxc-rnga.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/mxc-rnga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/mxc-rnga.c</a></div><div class='hunk'>@@ -176,15 +176,13 @@ err_ioremap:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit mxc_rnga_remove(struct platform_device *pdev)</div><div class='add'>+static void __exit mxc_rnga_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mxc_rng *mxc_rng = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	hwrng_unregister(&amp;mxc_rng-&gt;rng);</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(mxc_rng-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mxc_rnga_of_match[] = {</div><div class='hunk'>@@ -199,7 +197,7 @@ static struct platform_driver mxc_rnga_driver = {</div><div class='ctx'> 		.name = "mxc_rnga",</div><div class='ctx'> 		.of_match_table = mxc_rnga_of_match,</div><div class='ctx'> 	},</div><div class='del'>-	.remove = __exit_p(mxc_rnga_remove),</div><div class='add'>+	.remove_new = __exit_p(mxc_rnga_remove),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver_probe(mxc_rnga_driver, mxc_rnga_probe);</div><div class='head'>diff --git a/drivers/char/hw_random/n2-drv.c b/drivers/char/hw_random/n2-drv.c<br/>index aaae16b98475..2e669e7c14d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/n2-drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/n2-drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/n2-drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/n2-drv.c</a></div><div class='hunk'>@@ -781,7 +781,7 @@ out:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int n2rng_remove(struct platform_device *op)</div><div class='add'>+static void n2rng_remove(struct platform_device *op)</div><div class='ctx'> {</div><div class='ctx'> 	struct n2rng *np = platform_get_drvdata(op);</div><div class='ctx'> </div><div class='hunk'>@@ -790,8 +790,6 @@ static int n2rng_remove(struct platform_device *op)</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;np-&gt;work);</div><div class='ctx'> </div><div class='ctx'> 	sun4v_hvapi_unregister(HV_GRP_RNG);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct n2rng_template n2_template = {</div><div class='hunk'>@@ -860,7 +858,7 @@ static struct platform_driver n2rng_driver = {</div><div class='ctx'> 		.of_match_table = n2rng_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= n2rng_probe,</div><div class='del'>-	.remove		= n2rng_remove,</div><div class='add'>+	.remove_new	= n2rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(n2rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/npcm-rng.c b/drivers/char/hw_random/npcm-rng.c<br/>index 8a304b754217..bce8c4829a1f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/npcm-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/npcm-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/npcm-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/npcm-rng.c</a></div><div class='hunk'>@@ -126,15 +126,13 @@ static int npcm_rng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int npcm_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void npcm_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct npcm_rng *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	devm_hwrng_unregister(&amp;pdev-&gt;dev, &amp;priv-&gt;rng);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_set_suspended(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM</div><div class='hunk'>@@ -178,7 +176,7 @@ static struct platform_driver npcm_rng_driver = {</div><div class='ctx'> 		.of_match_table = of_match_ptr(rng_dt_id),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= npcm_rng_probe,</div><div class='del'>-	.remove		= npcm_rng_remove,</div><div class='add'>+	.remove_new	= npcm_rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(npcm_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c<br/>index be03f76a2a80..d4c02e900466 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/omap-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/omap-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/omap-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/omap-rng.c</a></div><div class='hunk'>@@ -509,7 +509,7 @@ err_ioremap:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int omap_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void omap_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct omap_rng_dev *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -521,8 +521,6 @@ static int omap_rng_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(priv-&gt;clk);</div><div class='ctx'> 	clk_disable_unprepare(priv-&gt;clk_reg);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused omap_rng_suspend(struct device *dev)</div><div class='hunk'>@@ -560,7 +558,7 @@ static struct platform_driver omap_rng_driver = {</div><div class='ctx'> 		.of_match_table = of_match_ptr(omap_rng_of_match),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= omap_rng_probe,</div><div class='del'>-	.remove		= omap_rng_remove,</div><div class='add'>+	.remove_new	= omap_rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(omap_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/stm32-rng.c b/drivers/char/hw_random/stm32-rng.c<br/>index 41e1dbea5d2e..379bc245c520 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/stm32-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/stm32-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/stm32-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/stm32-rng.c</a></div><div class='hunk'>@@ -325,6 +325,7 @@ static int stm32_rng_init(struct hwrng *rng)</div><div class='ctx'> 							(!(reg &amp; RNG_CR_CONDRST)),</div><div class='ctx'> 							10, 50000);</div><div class='ctx'> 		if (err) {</div><div class='add'>+			clk_disable_unprepare(priv-&gt;clk);</div><div class='ctx'> 			dev_err((struct device *)priv-&gt;rng.priv,</div><div class='ctx'> 				"%s: timeout %x!\n", __func__, reg);</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -362,11 +363,9 @@ static int stm32_rng_init(struct hwrng *rng)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stm32_rng_remove(struct platform_device *ofdev)</div><div class='add'>+static void stm32_rng_remove(struct platform_device *ofdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;ofdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused stm32_rng_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -557,7 +556,7 @@ static struct platform_driver stm32_rng_driver = {</div><div class='ctx'> 		.of_match_table = stm32_rng_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = stm32_rng_probe,</div><div class='del'>-	.remove = stm32_rng_remove,</div><div class='add'>+	.remove_new = stm32_rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(stm32_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/timeriomem-rng.c b/drivers/char/hw_random/timeriomem-rng.c<br/>index 3db9d868efb1..65b8260339f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/timeriomem-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/timeriomem-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/timeriomem-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/timeriomem-rng.c</a></div><div class='hunk'>@@ -174,13 +174,11 @@ static int timeriomem_rng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int timeriomem_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void timeriomem_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct timeriomem_rng_private *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	hrtimer_cancel(&amp;priv-&gt;timer);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id timeriomem_rng_match[] = {</div><div class='hunk'>@@ -195,7 +193,7 @@ static struct platform_driver timeriomem_rng_driver = {</div><div class='ctx'> 		.of_match_table	= timeriomem_rng_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= timeriomem_rng_probe,</div><div class='del'>-	.remove		= timeriomem_rng_remove,</div><div class='add'>+	.remove_new	= timeriomem_rng_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(timeriomem_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c<br/>index e41a84e6b4b5..7a4b45393acb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/virtio-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/virtio-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/virtio-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/virtio-rng.c</a></div><div class='hunk'>@@ -135,7 +135,7 @@ static int probe_common(struct virtio_device *vdev)</div><div class='ctx'> 	if (!vi)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	vi-&gt;index = index = ida_simple_get(&amp;rng_index_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	vi-&gt;index = index = ida_alloc(&amp;rng_index_ida, GFP_KERNEL);</div><div class='ctx'> 	if (index &lt; 0) {</div><div class='ctx'> 		err = index;</div><div class='ctx'> 		goto err_ida;</div><div class='hunk'>@@ -166,7 +166,7 @@ static int probe_common(struct virtio_device *vdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_find:</div><div class='del'>-	ida_simple_remove(&amp;rng_index_ida, index);</div><div class='add'>+	ida_free(&amp;rng_index_ida, index);</div><div class='ctx'> err_ida:</div><div class='ctx'> 	kfree(vi);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -184,7 +184,7 @@ static void remove_common(struct virtio_device *vdev)</div><div class='ctx'> 		hwrng_unregister(&amp;vi-&gt;hwrng);</div><div class='ctx'> 	virtio_reset_device(vdev);</div><div class='ctx'> 	vdev-&gt;config-&gt;del_vqs(vdev);</div><div class='del'>-	ida_simple_remove(&amp;rng_index_ida, vi-&gt;index);</div><div class='add'>+	ida_free(&amp;rng_index_ida, vi-&gt;index);</div><div class='ctx'> 	kfree(vi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -208,7 +208,6 @@ static void virtrng_scan(struct virtio_device *vdev)</div><div class='ctx'> 		vi-&gt;hwrng_register_done = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_PM_SLEEP</div><div class='ctx'> static int virtrng_freeze(struct virtio_device *vdev)</div><div class='ctx'> {</div><div class='ctx'> 	remove_common(vdev);</div><div class='hunk'>@@ -238,7 +237,6 @@ static int virtrng_restore(struct virtio_device *vdev)</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> static const struct virtio_device_id id_table[] = {</div><div class='ctx'> 	{ VIRTIO_ID_RNG, VIRTIO_DEV_ANY_ID },</div><div class='hunk'>@@ -252,10 +250,8 @@ static struct virtio_driver virtio_rng_driver = {</div><div class='ctx'> 	.probe =	virtrng_probe,</div><div class='ctx'> 	.remove =	virtrng_remove,</div><div class='ctx'> 	.scan =		virtrng_scan,</div><div class='del'>-#ifdef CONFIG_PM_SLEEP</div><div class='del'>-	.freeze =	virtrng_freeze,</div><div class='del'>-	.restore =	virtrng_restore,</div><div class='del'>-#endif</div><div class='add'>+	.freeze =	pm_sleep_ptr(virtrng_freeze),</div><div class='add'>+	.restore =	pm_sleep_ptr(virtrng_restore),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_virtio_driver(virtio_rng_driver);</div><div class='head'>diff --git a/drivers/char/hw_random/xgene-rng.c b/drivers/char/hw_random/xgene-rng.c<br/>index 7382724bf501..642d13519464 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/hw_random/xgene-rng.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/hw_random/xgene-rng.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/hw_random/xgene-rng.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/hw_random/xgene-rng.c</a></div><div class='hunk'>@@ -357,15 +357,13 @@ static int xgene_rng_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xgene_rng_remove(struct platform_device *pdev)</div><div class='add'>+static void xgene_rng_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	rc = device_init_wakeup(&amp;pdev-&gt;dev, 0);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "RNG init wakeup failed error %d\n", rc);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id xgene_rng_of_match[] = {</div><div class='hunk'>@@ -377,7 +375,7 @@ MODULE_DEVICE_TABLE(of, xgene_rng_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver xgene_rng_driver = {</div><div class='ctx'> 	.probe = xgene_rng_probe,</div><div class='del'>-	.remove	= xgene_rng_remove,</div><div class='add'>+	.remove_new = xgene_rng_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "xgene-rng",</div><div class='ctx'> 		.of_match_table = xgene_rng_of_match,</div><div class='head'>diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c<br/>index d6f14279684d..b0eedc4595b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_msghandler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/ipmi/ipmi_msghandler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_msghandler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_msghandler.c</a></div><div class='hunk'>@@ -3053,7 +3053,7 @@ static void cleanup_bmc_work(struct work_struct *work)</div><div class='ctx'> 	int id = bmc-&gt;pdev.id; /* Unregister overwrites id */</div><div class='ctx'> </div><div class='ctx'> 	platform_device_unregister(&amp;bmc-&gt;pdev);</div><div class='del'>-	ida_simple_remove(&amp;ipmi_bmc_ida, id);</div><div class='add'>+	ida_free(&amp;ipmi_bmc_ida, id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -3169,7 +3169,7 @@ static int __ipmi_bmc_register(struct ipmi_smi *intf,</div><div class='ctx'> </div><div class='ctx'> 		bmc-&gt;pdev.name = "ipmi_bmc";</div><div class='ctx'> </div><div class='del'>-		rv = ida_simple_get(&amp;ipmi_bmc_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+		rv = ida_alloc(&amp;ipmi_bmc_ida, GFP_KERNEL);</div><div class='ctx'> 		if (rv &lt; 0) {</div><div class='ctx'> 			kfree(bmc);</div><div class='ctx'> 			goto out;</div><div class='head'>diff --git a/drivers/char/ipmi/ipmi_si_hardcode.c b/drivers/char/ipmi/ipmi_si_hardcode.c<br/>index ed5e91b1e040..0c92fa3eee88 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_si_hardcode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/ipmi/ipmi_si_hardcode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_si_hardcode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_si_hardcode.c</a></div><div class='hunk'>@@ -80,10 +80,10 @@ static void __init ipmi_hardcode_init_one(const char *si_type_str,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	p.regsize = regsizes[i];</div><div class='add'>+	p.regspacing = regspacings[i];</div><div class='ctx'> 	p.slave_addr = slave_addrs[i];</div><div class='ctx'> 	p.addr_source = SI_HARDCODED;</div><div class='ctx'> 	p.regshift = regshifts[i];</div><div class='del'>-	p.regsize = regsizes[i];</div><div class='ctx'> 	p.addr = addr;</div><div class='ctx'> 	p.space = addr_space;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/char/ipmi/ipmi_si_platform.c b/drivers/char/ipmi/ipmi_si_platform.c<br/>index c3d8ac7873ba..cd2edd8f8a03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_si_platform.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/ipmi/ipmi_si_platform.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/ipmi/ipmi_si_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ipmi/ipmi_si_platform.c</a></div><div class='hunk'>@@ -11,10 +11,11 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='del'>-#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/of_address.h&gt;</div><div class='ctx'> #include &lt;linux/of_irq.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include "ipmi_si.h"</div><div class='ctx'> #include "ipmi_dmi.h"</div><div class='hunk'>@@ -224,7 +225,6 @@ MODULE_DEVICE_TABLE(of, of_ipmi_match);</div><div class='ctx'> </div><div class='ctx'> static int of_ipmi_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *match;</div><div class='ctx'> 	struct si_sm_io io;</div><div class='ctx'> 	struct resource resource;</div><div class='ctx'> 	const __be32 *regsize, *regspacing, *regshift;</div><div class='hunk'>@@ -237,10 +237,6 @@ static int of_ipmi_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dev_info(&amp;pdev-&gt;dev, "probing via device tree\n");</div><div class='ctx'> </div><div class='del'>-	match = of_match_device(of_ipmi_match, &amp;pdev-&gt;dev);</div><div class='del'>-	if (!match)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='ctx'> 	if (!of_device_is_available(np))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -269,7 +265,7 @@ static int of_ipmi_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;io, 0, sizeof(io));</div><div class='del'>-	io.si_type	= (unsigned long) match-&gt;data;</div><div class='add'>+	io.si_type	= (enum si_type)device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> 	io.addr_source	= SI_DEVICETREE;</div><div class='ctx'> 	io.irq_setup	= ipmi_std_irq_setup;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/char/ppdev.c b/drivers/char/ppdev.c<br/>index 4c188e9e477c..ee951b265213 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/ppdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/ppdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/ppdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ppdev.c</a></div><div class='hunk'>@@ -299,7 +299,7 @@ static int register_device(int minor, struct pp_struct *pp)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	index = ida_simple_get(&amp;ida_index, 0, 0, GFP_KERNEL);</div><div class='add'>+	index = ida_alloc(&amp;ida_index, GFP_KERNEL);</div><div class='ctx'> 	memset(&amp;ppdev_cb, 0, sizeof(ppdev_cb));</div><div class='ctx'> 	ppdev_cb.irq_func = pp_irq;</div><div class='ctx'> 	ppdev_cb.flags = (pp-&gt;flags &amp; PP_EXCL) ? PARPORT_FLAG_EXCL : 0;</div><div class='hunk'>@@ -310,7 +310,7 @@ static int register_device(int minor, struct pp_struct *pp)</div><div class='ctx'> 	if (!pdev) {</div><div class='ctx'> 		pr_warn("%s: failed to register device!\n", name);</div><div class='ctx'> 		rc = -ENXIO;</div><div class='del'>-		ida_simple_remove(&amp;ida_index, index);</div><div class='add'>+		ida_free(&amp;ida_index, index);</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -750,7 +750,7 @@ static int pp_release(struct inode *inode, struct file *file)</div><div class='ctx'> </div><div class='ctx'> 	if (pp-&gt;pdev) {</div><div class='ctx'> 		parport_unregister_device(pp-&gt;pdev);</div><div class='del'>-		ida_simple_remove(&amp;ida_index, pp-&gt;index);</div><div class='add'>+		ida_free(&amp;ida_index, pp-&gt;index);</div><div class='ctx'> 		pp-&gt;pdev = NULL;</div><div class='ctx'> 		pr_debug(CHRDEV "%x: unregistered pardevice\n", minor);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/char/random.c b/drivers/char/random.c<br/>index 4a9c79391dee..456be28ba67c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/random.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/random.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/random.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/random.c</a></div><div class='hunk'>@@ -1364,7 +1364,6 @@ static void __cold try_to_generate_entropy(void)</div><div class='ctx'> SYSCALL_DEFINE3(getrandom, char __user *, ubuf, size_t, len, unsigned int, flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct iov_iter iter;</div><div class='del'>-	struct iovec iov;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; ~(GRND_NONBLOCK | GRND_RANDOM | GRND_INSECURE))</div><div class='hunk'>@@ -1385,7 +1384,7 @@ SYSCALL_DEFINE3(getrandom, char __user *, ubuf, size_t, len, unsigned int, flags</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = import_single_range(ITER_DEST, ubuf, len, &amp;iov, &amp;iter);</div><div class='add'>+	ret = import_ubuf(ITER_DEST, ubuf, len, &amp;iter);</div><div class='ctx'> 	if (unlikely(ret))</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	return get_random_bytes_user(&amp;iter);</div><div class='hunk'>@@ -1491,7 +1490,6 @@ static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	case RNDADDENTROPY: {</div><div class='ctx'> 		struct iov_iter iter;</div><div class='del'>-		struct iovec iov;</div><div class='ctx'> 		ssize_t ret;</div><div class='ctx'> 		int len;</div><div class='ctx'> </div><div class='hunk'>@@ -1503,7 +1501,7 @@ static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		if (get_user(len, p++))</div><div class='ctx'> 			return -EFAULT;</div><div class='del'>-		ret = import_single_range(ITER_SOURCE, p, len, &amp;iov, &amp;iter);</div><div class='add'>+		ret = import_ubuf(ITER_SOURCE, p, len, &amp;iter);</div><div class='ctx'> 		if (unlikely(ret))</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		ret = write_pool_user(&amp;iter);</div><div class='head'>diff --git a/drivers/char/tpm/tpm_i2c_nuvoton.c b/drivers/char/tpm/tpm_i2c_nuvoton.c<br/>index d7be03c41098..5490f7e0fa43 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/tpm/tpm_i2c_nuvoton.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/tpm/tpm_i2c_nuvoton.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/tpm/tpm_i2c_nuvoton.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/tpm/tpm_i2c_nuvoton.c</a></div><div class='hunk'>@@ -19,7 +19,8 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/wait.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include "tpm.h"</div><div class='ctx'> </div><div class='ctx'> /* I2C interface offsets */</div><div class='hunk'>@@ -524,7 +525,6 @@ static int get_vid(struct i2c_client *client, u32 *res)</div><div class='ctx'> </div><div class='ctx'> static int i2c_nuvoton_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='del'>-	const struct i2c_device_id *id = i2c_client_get_device_id(client);</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	struct tpm_chip *chip;</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='hunk'>@@ -546,15 +546,8 @@ static int i2c_nuvoton_probe(struct i2c_client *client)</div><div class='ctx'> 	if (!priv)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;of_node) {</div><div class='del'>-		const struct of_device_id *of_id;</div><div class='del'>-</div><div class='del'>-		of_id = of_match_device(dev-&gt;driver-&gt;of_match_table, dev);</div><div class='del'>-		if (of_id &amp;&amp; of_id-&gt;data == OF_IS_TPM2)</div><div class='del'>-			chip-&gt;flags |= TPM_CHIP_FLAG_TPM2;</div><div class='del'>-	} else</div><div class='del'>-		if (id-&gt;driver_data == I2C_IS_TPM2)</div><div class='del'>-			chip-&gt;flags |= TPM_CHIP_FLAG_TPM2;</div><div class='add'>+	if (i2c_get_match_data(client))</div><div class='add'>+		chip-&gt;flags |= TPM_CHIP_FLAG_TPM2;</div><div class='ctx'> </div><div class='ctx'> 	init_waitqueue_head(&amp;priv-&gt;read_queue);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/char/tpm/tpm_tis_i2c_cr50.c b/drivers/char/tpm/tpm_tis_i2c_cr50.c<br/>index e70abd69e1ae..adf22992138e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/tpm/tpm_tis_i2c_cr50.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/tpm/tpm_tis_i2c_cr50.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/tpm/tpm_tis_i2c_cr50.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/tpm/tpm_tis_i2c_cr50.c</a></div><div class='hunk'>@@ -235,7 +235,7 @@ out:</div><div class='ctx'>  * @len:	Number of bytes to write.</div><div class='ctx'>  *</div><div class='ctx'>  * The provided address is prepended to the data in 'buffer', the</div><div class='del'>- * cobined address+data is sent to the TPM, then wait for TPM to</div><div class='add'>+ * combined address+data is sent to the TPM, then wait for TPM to</div><div class='ctx'>  * indicate it is done writing.</div><div class='ctx'>  *</div><div class='ctx'>  * Return:</div><div class='hunk'>@@ -671,7 +671,6 @@ MODULE_DEVICE_TABLE(of, of_cr50_i2c_match);</div><div class='ctx'> /**</div><div class='ctx'>  * tpm_cr50_i2c_probe() - Driver probe function.</div><div class='ctx'>  * @client:	I2C client information.</div><div class='del'>- * @id:		I2C device id.</div><div class='ctx'>  *</div><div class='ctx'>  * Return:</div><div class='ctx'>  * - 0:		Success.</div><div class='head'>diff --git a/drivers/char/ttyprintk.c b/drivers/char/ttyprintk.c<br/>index 5af804c17a75..4c806a189ee5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/ttyprintk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/ttyprintk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/ttyprintk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/ttyprintk.c</a></div><div class='hunk'>@@ -40,7 +40,7 @@ static struct ttyprintk_port tpk_port;</div><div class='ctx'> </div><div class='ctx'> static int tpk_curr;</div><div class='ctx'> </div><div class='del'>-static char tpk_buffer[TPK_STR_SIZE + 4];</div><div class='add'>+static u8 tpk_buffer[TPK_STR_SIZE + 4];</div><div class='ctx'> </div><div class='ctx'> static void tpk_flush(void)</div><div class='ctx'> {</div><div class='hunk'>@@ -51,9 +51,9 @@ static void tpk_flush(void)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tpk_printk(const u8 *buf, int count)</div><div class='add'>+static int tpk_printk(const u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	size_t i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		if (tpk_curr &gt;= TPK_STR_SIZE) {</div><div class='head'>diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c<br/>index 431e9e5bf9c1..035f89f1a251 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/char/virtio_console.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/char/virtio_console.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/char/virtio_console.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/char/virtio_console.c</a></div><div class='hunk'>@@ -230,9 +230,6 @@ struct port {</div><div class='ctx'> 	bool guest_connected;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* This is the very early arch-specified put chars function. */</div><div class='del'>-static int (*early_put_chars)(u32, const char *, int);</div><div class='del'>-</div><div class='ctx'> static struct port *find_port_by_vtermno(u32 vtermno)</div><div class='ctx'> {</div><div class='ctx'> 	struct port *port;</div><div class='hunk'>@@ -653,7 +650,7 @@ done:</div><div class='ctx'>  * Give out the data that's requested from the buffer that we have</div><div class='ctx'>  * queued up.</div><div class='ctx'>  */</div><div class='del'>-static ssize_t fill_readbuf(struct port *port, char __user *out_buf,</div><div class='add'>+static ssize_t fill_readbuf(struct port *port, u8 __user *out_buf,</div><div class='ctx'> 			    size_t out_count, bool to_user)</div><div class='ctx'> {</div><div class='ctx'> 	struct port_buffer *buf;</div><div class='hunk'>@@ -672,7 +669,7 @@ static ssize_t fill_readbuf(struct port *port, char __user *out_buf,</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return -EFAULT;</div><div class='ctx'> 	} else {</div><div class='del'>-		memcpy((__force char *)out_buf, buf-&gt;buf + buf-&gt;offset,</div><div class='add'>+		memcpy((__force u8 *)out_buf, buf-&gt;buf + buf-&gt;offset,</div><div class='ctx'> 		       out_count);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1107,16 +1104,13 @@ static const struct file_operations port_fops = {</div><div class='ctx'>  * it to finish: inefficient in theory, but in practice</div><div class='ctx'>  * implementations will do it immediately.</div><div class='ctx'>  */</div><div class='del'>-static int put_chars(u32 vtermno, const char *buf, int count)</div><div class='add'>+static ssize_t put_chars(u32 vtermno, const u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct port *port;</div><div class='ctx'> 	struct scatterlist sg[1];</div><div class='ctx'> 	void *data;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (unlikely(early_put_chars))</div><div class='del'>-		return early_put_chars(vtermno, buf, count);</div><div class='del'>-</div><div class='ctx'> 	port = find_port_by_vtermno(vtermno);</div><div class='ctx'> 	if (!port)</div><div class='ctx'> 		return -EPIPE;</div><div class='hunk'>@@ -1138,14 +1132,10 @@ static int put_chars(u32 vtermno, const char *buf, int count)</div><div class='ctx'>  * We call out to fill_readbuf that gets us the required data from the</div><div class='ctx'>  * buffers that are queued up.</div><div class='ctx'>  */</div><div class='del'>-static int get_chars(u32 vtermno, char *buf, int count)</div><div class='add'>+static ssize_t get_chars(u32 vtermno, u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct port *port;</div><div class='ctx'> </div><div class='del'>-	/* If we've not set up the port yet, we have no input to give. */</div><div class='del'>-	if (unlikely(early_put_chars))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	port = find_port_by_vtermno(vtermno);</div><div class='ctx'> 	if (!port)</div><div class='ctx'> 		return -EPIPE;</div><div class='hunk'>@@ -1153,7 +1143,7 @@ static int get_chars(u32 vtermno, char *buf, int count)</div><div class='ctx'> 	/* If we don't have an input queue yet, we can't get input. */</div><div class='ctx'> 	BUG_ON(!port-&gt;in_vq);</div><div class='ctx'> </div><div class='del'>-	return fill_readbuf(port, (__force char __user *)buf, count, false);</div><div class='add'>+	return fill_readbuf(port, (__force u8 __user *)buf, count, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void resize_console(struct port *port)</div><div class='hunk'>@@ -1201,21 +1191,6 @@ static const struct hv_ops hv_ops = {</div><div class='ctx'> 	.notifier_hangup = notifier_del_vio,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Console drivers are initialized very early so boot messages can go</div><div class='del'>- * out, so we do things slightly differently from the generic virtio</div><div class='del'>- * initialization of the net and block drivers.</div><div class='del'>- *</div><div class='del'>- * At this stage, the console is output-only.  It's too early to set</div><div class='del'>- * up a virtqueue, so we let the drivers do some boutique early-output</div><div class='del'>- * thing.</div><div class='del'>- */</div><div class='del'>-int __init virtio_cons_early_init(int (*put_chars)(u32, const char *, int))</div><div class='del'>-{</div><div class='del'>-	early_put_chars = put_chars;</div><div class='del'>-	return hvc_instantiate(0, 0, &amp;hv_ops);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int init_port_console(struct port *port)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1256,13 +1231,6 @@ static int init_port_console(struct port *port)</div><div class='ctx'> 	spin_unlock_irq(&amp;pdrvdata_lock);</div><div class='ctx'> 	port-&gt;guest_connected = true;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Start using the new console output if this is the first</div><div class='del'>-	 * console to come up.</div><div class='del'>-	 */</div><div class='del'>-	if (early_put_chars)</div><div class='del'>-		early_put_chars = NULL;</div><div class='del'>-</div><div class='ctx'> 	/* Notify host of port being opened */</div><div class='ctx'> 	send_control_msg(port, VIRTIO_CONSOLE_PORT_OPEN, 1);</div><div class='ctx'> </div><div class='hunk'>@@ -1999,7 +1967,6 @@ static int virtcons_probe(struct virtio_device *vdev)</div><div class='ctx'> 	struct ports_device *portdev;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	bool multiport;</div><div class='del'>-	bool early = early_put_chars != NULL;</div><div class='ctx'> </div><div class='ctx'> 	/* We only need a config space if features are offered */</div><div class='ctx'> 	if (!vdev-&gt;config-&gt;get &amp;&amp;</div><div class='hunk'>@@ -2010,9 +1977,6 @@ static int virtcons_probe(struct virtio_device *vdev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Ensure to read early_put_chars now */</div><div class='del'>-	barrier();</div><div class='del'>-</div><div class='ctx'> 	portdev = kmalloc(sizeof(*portdev), GFP_KERNEL);</div><div class='ctx'> 	if (!portdev) {</div><div class='ctx'> 		err = -ENOMEM;</div><div class='hunk'>@@ -2100,18 +2064,6 @@ static int virtcons_probe(struct virtio_device *vdev)</div><div class='ctx'> 	__send_control_msg(portdev, VIRTIO_CONSOLE_BAD_ID,</div><div class='ctx'> 			   VIRTIO_CONSOLE_DEVICE_READY, 1);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * If there was an early virtio console, assume that there are no</div><div class='del'>-	 * other consoles. We need to wait until the hvc_alloc matches the</div><div class='del'>-	 * hvc_instantiate, otherwise tty_open will complain, resulting in</div><div class='del'>-	 * a "Warning: unable to open an initial console" boot failure.</div><div class='del'>-	 * Without multiport this is done in add_port above. With multiport</div><div class='del'>-	 * this might take some host&lt;-&gt;guest communication - thus we have to</div><div class='del'>-	 * wait.</div><div class='del'>-	 */</div><div class='del'>-	if (multiport &amp;&amp; early)</div><div class='del'>-		wait_for_completion(&amp;early_console_added);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> free_chrdev:</div><div class='head'>diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig<br/>index c30d0d396f7a..50af5fc7f570 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/Kconfig</a></div><div class='hunk'>@@ -414,16 +414,6 @@ config COMMON_CLK_VC7</div><div class='ctx'> 	  Renesas Versaclock7 is a family of configurable clock generator</div><div class='ctx'> 	  and jitter attenuator ICs with fractional and integer dividers.</div><div class='ctx'> </div><div class='del'>-config COMMON_CLK_STM32MP135</div><div class='del'>-	def_bool COMMON_CLK &amp;&amp; MACH_STM32MP13</div><div class='del'>-	help</div><div class='del'>-	  Support for stm32mp135 SoC family clocks</div><div class='del'>-</div><div class='del'>-config COMMON_CLK_STM32MP157</div><div class='del'>-	def_bool COMMON_CLK &amp;&amp; MACH_STM32MP157</div><div class='del'>-	help</div><div class='del'>-	  Support for stm32mp157 SoC family clocks</div><div class='del'>-</div><div class='ctx'> config COMMON_CLK_STM32F</div><div class='ctx'> 	def_bool COMMON_CLK &amp;&amp; (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)</div><div class='ctx'> 	help</div><div class='hunk'>@@ -504,6 +494,7 @@ source "drivers/clk/starfive/Kconfig"</div><div class='ctx'> source "drivers/clk/sunxi/Kconfig"</div><div class='ctx'> source "drivers/clk/sunxi-ng/Kconfig"</div><div class='ctx'> source "drivers/clk/tegra/Kconfig"</div><div class='add'>+source "drivers/clk/stm32/Kconfig"</div><div class='ctx'> source "drivers/clk/ti/Kconfig"</div><div class='ctx'> source "drivers/clk/uniphier/Kconfig"</div><div class='ctx'> source "drivers/clk/visconti/Kconfig"</div><div class='head'>diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile<br/>index ed71f2e0ee36..14fa8d4ecc1f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/Makefile</a></div><div class='hunk'>@@ -70,7 +70,6 @@ obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_SP7021)		+= clk-sp7021.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o</div><div class='del'>-obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_TPS68470)      += clk-tps68470.o</div><div class='ctx'> obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o</div><div class='ctx'> obj-$(CONFIG_CLK_TWL)			+= clk-twl.o</div><div class='head'>diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c<br/>index 380245f635d6..53e21ac302e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-renesas-pcie.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-renesas-pcie.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/clk-renesas-pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-renesas-pcie.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'>  * Currently supported:</div><div class='ctx'>  *   - 9FGV0241</div><div class='ctx'>  *   - 9FGV0441</div><div class='add'>+ *   - 9FGV0841</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (C) 2022 Marek Vasut &lt;marex@denx.de&gt;</div><div class='ctx'>  */</div><div class='hunk'>@@ -42,6 +43,7 @@</div><div class='ctx'> #define RS9_REG_DID				0x6</div><div class='ctx'> #define RS9_REG_BCP				0x7</div><div class='ctx'> </div><div class='add'>+#define RS9_REG_VID_MASK			GENMASK(3, 0)</div><div class='ctx'> #define RS9_REG_VID_IDT				0x01</div><div class='ctx'> </div><div class='ctx'> #define RS9_REG_DID_TYPE_FGV			(0x0 &lt;&lt; RS9_REG_DID_TYPE_SHIFT)</div><div class='hunk'>@@ -49,16 +51,10 @@</div><div class='ctx'> #define RS9_REG_DID_TYPE_DMV			(0x2 &lt;&lt; RS9_REG_DID_TYPE_SHIFT)</div><div class='ctx'> #define RS9_REG_DID_TYPE_SHIFT			0x6</div><div class='ctx'> </div><div class='del'>-/* Supported Renesas 9-series models. */</div><div class='del'>-enum rs9_model {</div><div class='del'>-	RENESAS_9FGV0241,</div><div class='del'>-	RENESAS_9FGV0441,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* Structure to describe features of a particular 9-series model */</div><div class='ctx'> struct rs9_chip_info {</div><div class='del'>-	const enum rs9_model	model;</div><div class='ctx'> 	unsigned int		num_clks;</div><div class='add'>+	u8			outshift;</div><div class='ctx'> 	u8			did;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -160,14 +156,12 @@ static const struct regmap_config rs9_regmap_config = {</div><div class='ctx'> </div><div class='ctx'> static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)</div><div class='ctx'> {</div><div class='del'>-	enum rs9_model model = rs9-&gt;chip_info-&gt;model;</div><div class='del'>-</div><div class='del'>-	if (model == RENESAS_9FGV0241)</div><div class='del'>-		return BIT(idx) + 1;</div><div class='del'>-	else if (model == RENESAS_9FGV0441)</div><div class='del'>-		return BIT(idx);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	/*</div><div class='add'>+	 * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),</div><div class='add'>+	 * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.</div><div class='add'>+	 * Increment the index in the 9FGV0241 special case here.</div><div class='add'>+	 */</div><div class='add'>+	return BIT(idx + rs9-&gt;chip_info-&gt;outshift);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)</div><div class='hunk'>@@ -333,6 +327,7 @@ static int rs9_probe(struct i2c_client *client)</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	vid &amp;= RS9_REG_VID_MASK;</div><div class='ctx'> 	if (vid != RS9_REG_VID_IDT || did != rs9-&gt;chip_info-&gt;did)</div><div class='ctx'> 		return dev_err_probe(&amp;client-&gt;dev, -ENODEV,</div><div class='ctx'> 				     "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n",</div><div class='hunk'>@@ -380,20 +375,27 @@ static int __maybe_unused rs9_resume(struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct rs9_chip_info renesas_9fgv0241_info = {</div><div class='del'>-	.model		= RENESAS_9FGV0241,</div><div class='ctx'> 	.num_clks	= 2,</div><div class='add'>+	.outshift	= 1,</div><div class='ctx'> 	.did		= RS9_REG_DID_TYPE_FGV | 0x02,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rs9_chip_info renesas_9fgv0441_info = {</div><div class='del'>-	.model		= RENESAS_9FGV0441,</div><div class='ctx'> 	.num_clks	= 4,</div><div class='add'>+	.outshift	= 0,</div><div class='ctx'> 	.did		= RS9_REG_DID_TYPE_FGV | 0x04,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct rs9_chip_info renesas_9fgv0841_info = {</div><div class='add'>+	.num_clks	= 8,</div><div class='add'>+	.outshift	= 0,</div><div class='add'>+	.did		= RS9_REG_DID_TYPE_FGV | 0x08,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct i2c_device_id rs9_id[] = {</div><div class='ctx'> 	{ "9fgv0241", .driver_data = (kernel_ulong_t)&amp;renesas_9fgv0241_info },</div><div class='ctx'> 	{ "9fgv0441", .driver_data = (kernel_ulong_t)&amp;renesas_9fgv0441_info },</div><div class='add'>+	{ "9fgv0841", .driver_data = (kernel_ulong_t)&amp;renesas_9fgv0841_info },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, rs9_id);</div><div class='hunk'>@@ -401,6 +403,7 @@ MODULE_DEVICE_TABLE(i2c, rs9_id);</div><div class='ctx'> static const struct of_device_id clk_rs9_of_match[] = {</div><div class='ctx'> 	{ .compatible = "renesas,9fgv0241", .data = &amp;renesas_9fgv0241_info },</div><div class='ctx'> 	{ .compatible = "renesas,9fgv0441", .data = &amp;renesas_9fgv0441_info },</div><div class='add'>+	{ .compatible = "renesas,9fgv0841", .data = &amp;renesas_9fgv0841_info },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, clk_rs9_of_match);</div><div class='head'>diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c<br/>index 845b451511d2..6e8dd7387cfd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-si5341.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-si5341.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/clk-si5341.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-si5341.c</a></div><div class='hunk'>@@ -895,10 +895,8 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	r[0] = r_div ? (r_div &amp; 0xff) : 1;</div><div class='ctx'> 	r[1] = (r_div &gt;&gt; 8) &amp; 0xff;</div><div class='ctx'> 	r[2] = (r_div &gt;&gt; 16) &amp; 0xff;</div><div class='del'>-	err = regmap_bulk_write(output-&gt;data-&gt;regmap,</div><div class='add'>+	return regmap_bulk_write(output-&gt;data-&gt;regmap,</div><div class='ctx'> 			SI5341_OUT_R_REG(output), r, 3);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)</div><div class='head'>diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c<br/>index a9a0bc448a4b..4ce83c5265b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-si5351.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-si5351.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/clk-si5351.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-si5351.c</a></div><div class='hunk'>@@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> {</div><div class='ctx'> 	struct si5351_hw_data *hwdata =</div><div class='ctx'> 		container_of(hw, struct si5351_hw_data, hw);</div><div class='add'>+	struct si5351_platform_data *pdata =</div><div class='add'>+		hwdata-&gt;drvdata-&gt;client-&gt;dev.platform_data;</div><div class='ctx'> 	u8 reg = (hwdata-&gt;num == 0) ? SI5351_PLLA_PARAMETERS :</div><div class='ctx'> 		SI5351_PLLB_PARAMETERS;</div><div class='ctx'> </div><div class='hunk'>@@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 		(hwdata-&gt;params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);</div><div class='ctx'> </div><div class='ctx'> 	/* Do a pll soft reset on the affected pll */</div><div class='del'>-	si5351_reg_write(hwdata-&gt;drvdata, SI5351_PLL_RESET,</div><div class='del'>-			 hwdata-&gt;num == 0 ? SI5351_PLL_RESET_A :</div><div class='del'>-					    SI5351_PLL_RESET_B);</div><div class='add'>+	if (pdata-&gt;pll_reset[hwdata-&gt;num])</div><div class='add'>+		si5351_reg_write(hwdata-&gt;drvdata, SI5351_PLL_RESET,</div><div class='add'>+				 hwdata-&gt;num == 0 ? SI5351_PLL_RESET_A :</div><div class='add'>+						    SI5351_PLL_RESET_B);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;hwdata-&gt;drvdata-&gt;client-&gt;dev,</div><div class='ctx'> 		"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",</div><div class='hunk'>@@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Parse PLL reset mode. For compatibility with older device trees, the</div><div class='add'>+	 * default is to always reset a PLL after setting its rate.</div><div class='add'>+	 */</div><div class='add'>+	pdata-&gt;pll_reset[0] = true;</div><div class='add'>+	pdata-&gt;pll_reset[1] = true;</div><div class='add'>+</div><div class='add'>+	of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) {</div><div class='add'>+		if (num &gt;= 2) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev,</div><div class='add'>+				"invalid pll %d on pll-reset-mode prop\n", num);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		p = of_prop_next_u32(prop, p, &amp;val);</div><div class='add'>+		if (!p) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev,</div><div class='add'>+				"missing pll-reset-mode for pll %d\n", num);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (val) {</div><div class='add'>+		case 0:</div><div class='add'>+			/* Reset PLL whenever its rate is adjusted */</div><div class='add'>+			pdata-&gt;pll_reset[num] = true;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			/* Don't reset PLL whenever its rate is adjusted */</div><div class='add'>+			pdata-&gt;pll_reset[num] = false;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			dev_err(&amp;client-&gt;dev,</div><div class='add'>+				"invalid pll-reset-mode %d for pll %d\n", val,</div><div class='add'>+				num);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* per clkout properties */</div><div class='ctx'> 	for_each_child_of_node(np, child) {</div><div class='ctx'> 		if (of_property_read_u32(child, "reg", &amp;num)) {</div><div class='head'>diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c<br/>index 01d3c4c7b0b2..7cb7d501d7a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-sp7021.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-sp7021.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/clk-sp7021.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-sp7021.c</a></div><div class='hunk'>@@ -604,14 +604,14 @@ static int sp7021_clk_probe(struct platform_device *pdev)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	clk_base = devm_platform_ioremap_resource(pdev, 0);</div><div class='del'>-	if (!clk_base)</div><div class='del'>-		return -ENXIO;</div><div class='add'>+	if (IS_ERR(clk_base))</div><div class='add'>+		return PTR_ERR(clk_base);</div><div class='ctx'> 	pll_base = devm_platform_ioremap_resource(pdev, 1);</div><div class='del'>-	if (!pll_base)</div><div class='del'>-		return -ENXIO;</div><div class='add'>+	if (IS_ERR(pll_base))</div><div class='add'>+		return PTR_ERR(pll_base);</div><div class='ctx'> 	sys_base = devm_platform_ioremap_resource(pdev, 2);</div><div class='del'>-	if (!sys_base)</div><div class='del'>-		return -ENXIO;</div><div class='add'>+	if (IS_ERR(sys_base))</div><div class='add'>+		return PTR_ERR(sys_base);</div><div class='ctx'> </div><div class='ctx'> 	/* enable default clks */</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(sp_clken); i++)</div><div class='head'>diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c<br/>index 00930d7bca77..76d7ea1964c3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-versaclock3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-versaclock3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/clk-versaclock3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/clk-versaclock3.c</a></div><div class='hunk'>@@ -37,7 +37,7 @@</div><div class='ctx'> #define VC3_PLL1_M_DIV(n)		((n) &amp; GENMASK(5, 0))</div><div class='ctx'> </div><div class='ctx'> #define VC3_PLL1_VCO_N_DIVIDER		0x9</div><div class='del'>-#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB	0x0a</div><div class='add'>+#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB	0xa</div><div class='ctx'> </div><div class='ctx'> #define VC3_OUT_DIV1_DIV2_CTRL		0xf</div><div class='ctx'> </div><div class='hunk'>@@ -148,16 +148,16 @@ struct vc3_pfd_data {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct vc3_pll_data {</div><div class='add'>+	unsigned long vco_min;</div><div class='add'>+	unsigned long vco_max;</div><div class='ctx'> 	u8 num;</div><div class='ctx'> 	u8 int_div_msb_offs;</div><div class='ctx'> 	u8 int_div_lsb_offs;</div><div class='del'>-	unsigned long vco_min;</div><div class='del'>-	unsigned long vco_max;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct vc3_div_data {</div><div class='del'>-	u8 offs;</div><div class='ctx'> 	const struct clk_div_table *table;</div><div class='add'>+	u8 offs;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> 	u8 width;</div><div class='ctx'> 	u8 flags;</div><div class='hunk'>@@ -210,7 +210,7 @@ static const struct clk_div_table div3_divs[] = {</div><div class='ctx'> </div><div class='ctx'> static struct clk_hw *clk_out[6];</div><div class='ctx'> </div><div class='del'>-static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw)</div><div class='add'>+static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *pfd_mux = vc3-&gt;data;</div><div class='hunk'>@@ -226,9 +226,8 @@ static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index)</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *pfd_mux = vc3-&gt;data;</div><div class='ctx'> </div><div class='del'>-	regmap_update_bits(vc3-&gt;regmap, pfd_mux-&gt;offs, pfd_mux-&gt;bitmsk,</div><div class='del'>-			   index ? pfd_mux-&gt;bitmsk : 0);</div><div class='del'>-	return 0;</div><div class='add'>+	return regmap_update_bits(vc3-&gt;regmap, pfd_mux-&gt;offs, pfd_mux-&gt;bitmsk,</div><div class='add'>+				  index ? pfd_mux-&gt;bitmsk : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct clk_ops vc3_pfd_mux_ops = {</div><div class='hunk'>@@ -440,7 +439,7 @@ static const struct clk_ops vc3_pll_ops = {</div><div class='ctx'> 	.set_rate = vc3_pll_set_rate,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw)</div><div class='add'>+static u8 vc3_div_mux_get_parent(struct clk_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *div_mux = vc3-&gt;data;</div><div class='hunk'>@@ -456,10 +455,8 @@ static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index)</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *div_mux = vc3-&gt;data;</div><div class='ctx'> </div><div class='del'>-	regmap_update_bits(vc3-&gt;regmap, div_mux-&gt;offs, div_mux-&gt;bitmsk,</div><div class='del'>-			   index ? div_mux-&gt;bitmsk : 0);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return regmap_update_bits(vc3-&gt;regmap, div_mux-&gt;offs, div_mux-&gt;bitmsk,</div><div class='add'>+				  index ? div_mux-&gt;bitmsk : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct clk_ops vc3_div_mux_ops = {</div><div class='hunk'>@@ -477,7 +474,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table,</div><div class='ctx'> 		if (clkt-&gt;val == val)</div><div class='ctx'> 			return clkt-&gt;div;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,</div><div class='hunk'>@@ -524,10 +521,9 @@ static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> </div><div class='ctx'> 	value = divider_get_val(rate, parent_rate, div_data-&gt;table,</div><div class='ctx'> 				div_data-&gt;width, div_data-&gt;flags);</div><div class='del'>-	regmap_update_bits(vc3-&gt;regmap, div_data-&gt;offs,</div><div class='del'>-			   VC3_DIV_MASK(div_data-&gt;width) &lt;&lt; div_data-&gt;shift,</div><div class='del'>-			   value &lt;&lt; div_data-&gt;shift);</div><div class='del'>-	return 0;</div><div class='add'>+	return regmap_update_bits(vc3-&gt;regmap, div_data-&gt;offs,</div><div class='add'>+				  VC3_DIV_MASK(div_data-&gt;width) &lt;&lt; div_data-&gt;shift,</div><div class='add'>+				  value &lt;&lt; div_data-&gt;shift);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct clk_ops vc3_div_ops = {</div><div class='hunk'>@@ -539,11 +535,9 @@ static const struct clk_ops vc3_div_ops = {</div><div class='ctx'> static int vc3_clk_mux_determine_rate(struct clk_hw *hw,</div><div class='ctx'> 				      struct clk_rate_request *req)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='ctx'> 	int frc;</div><div class='ctx'> </div><div class='del'>-	ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT);</div><div class='del'>-	if (ret) {</div><div class='add'>+	if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) {</div><div class='ctx'> 		/* The below check is equivalent to (best_parent_rate/rate) */</div><div class='ctx'> 		if (req-&gt;best_parent_rate &gt;= req-&gt;rate) {</div><div class='ctx'> 			frc = DIV_ROUND_CLOSEST_ULL(req-&gt;best_parent_rate,</div><div class='hunk'>@@ -552,13 +546,12 @@ static int vc3_clk_mux_determine_rate(struct clk_hw *hw,</div><div class='ctx'> 			return clk_mux_determine_rate_flags(hw, req,</div><div class='ctx'> 							    CLK_SET_RATE_PARENT);</div><div class='ctx'> 		}</div><div class='del'>-		ret = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw)</div><div class='add'>+static u8 vc3_clk_mux_get_parent(struct clk_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *clk_mux = vc3-&gt;data;</div><div class='hunk'>@@ -574,9 +567,8 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index)</div><div class='ctx'> 	struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);</div><div class='ctx'> 	const struct vc3_clk_data *clk_mux = vc3-&gt;data;</div><div class='ctx'> </div><div class='del'>-	regmap_update_bits(vc3-&gt;regmap, clk_mux-&gt;offs,</div><div class='del'>-			   clk_mux-&gt;bitmsk, index ? clk_mux-&gt;bitmsk : 0);</div><div class='del'>-	return 0;</div><div class='add'>+	return regmap_update_bits(vc3-&gt;regmap, clk_mux-&gt;offs, clk_mux-&gt;bitmsk,</div><div class='add'>+				  index ? clk_mux-&gt;bitmsk : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct clk_ops vc3_clk_mux_ops = {</div><div class='hunk'>@@ -605,7 +597,7 @@ static struct vc3_hw_data clk_pfd_mux[] = {</div><div class='ctx'> 			.offs = VC3_PLL_OP_CTRL,</div><div class='ctx'> 			.bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pfd2_mux",</div><div class='ctx'> 			.ops = &amp;vc3_pfd_mux_ops,</div><div class='ctx'> 			.parent_data = pfd_mux_parent_data,</div><div class='hunk'>@@ -618,7 +610,7 @@ static struct vc3_hw_data clk_pfd_mux[] = {</div><div class='ctx'> 			.offs = VC3_GENERAL_CTR,</div><div class='ctx'> 			.bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pfd3_mux",</div><div class='ctx'> 			.ops = &amp;vc3_pfd_mux_ops,</div><div class='ctx'> 			.parent_data = pfd_mux_parent_data,</div><div class='hunk'>@@ -636,7 +628,7 @@ static struct vc3_hw_data clk_pfd[] = {</div><div class='ctx'> 			.mdiv1_bitmsk = VC3_PLL1_M_DIV1,</div><div class='ctx'> 			.mdiv2_bitmsk = VC3_PLL1_M_DIV2</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pfd1",</div><div class='ctx'> 			.ops = &amp;vc3_pfd_ops,</div><div class='ctx'> 			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='hunk'>@@ -653,7 +645,7 @@ static struct vc3_hw_data clk_pfd[] = {</div><div class='ctx'> 			.mdiv1_bitmsk = VC3_PLL2_M_DIV1,</div><div class='ctx'> 			.mdiv2_bitmsk = VC3_PLL2_M_DIV2</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pfd2",</div><div class='ctx'> 			.ops = &amp;vc3_pfd_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -670,7 +662,7 @@ static struct vc3_hw_data clk_pfd[] = {</div><div class='ctx'> 			.mdiv1_bitmsk = VC3_PLL3_M_DIV1,</div><div class='ctx'> 			.mdiv2_bitmsk = VC3_PLL3_M_DIV2</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pfd3",</div><div class='ctx'> 			.ops = &amp;vc3_pfd_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -691,7 +683,7 @@ static struct vc3_hw_data clk_pll[] = {</div><div class='ctx'> 			.vco_min = VC3_PLL1_VCO_MIN,</div><div class='ctx'> 			.vco_max = VC3_PLL1_VCO_MAX</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pll1",</div><div class='ctx'> 			.ops = &amp;vc3_pll_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -709,7 +701,7 @@ static struct vc3_hw_data clk_pll[] = {</div><div class='ctx'> 			.vco_min = VC3_PLL2_VCO_MIN,</div><div class='ctx'> 			.vco_max = VC3_PLL2_VCO_MAX</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pll2",</div><div class='ctx'> 			.ops = &amp;vc3_pll_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -727,7 +719,7 @@ static struct vc3_hw_data clk_pll[] = {</div><div class='ctx'> 			.vco_min = VC3_PLL3_VCO_MIN,</div><div class='ctx'> 			.vco_max = VC3_PLL3_VCO_MAX</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "pll3",</div><div class='ctx'> 			.ops = &amp;vc3_pll_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -760,7 +752,7 @@ static struct vc3_hw_data clk_div_mux[] = {</div><div class='ctx'> 			.offs = VC3_GENERAL_CTR,</div><div class='ctx'> 			.bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div1_mux",</div><div class='ctx'> 			.ops = &amp;vc3_div_mux_ops,</div><div class='ctx'> 			.parent_data = div_mux_parent_data[VC3_DIV1_MUX],</div><div class='hunk'>@@ -773,7 +765,7 @@ static struct vc3_hw_data clk_div_mux[] = {</div><div class='ctx'> 			.offs = VC3_PLL3_CHARGE_PUMP_CTRL,</div><div class='ctx'> 			.bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div3_mux",</div><div class='ctx'> 			.ops = &amp;vc3_div_mux_ops,</div><div class='ctx'> 			.parent_data = div_mux_parent_data[VC3_DIV3_MUX],</div><div class='hunk'>@@ -786,7 +778,7 @@ static struct vc3_hw_data clk_div_mux[] = {</div><div class='ctx'> 			.offs = VC3_OUTPUT_CTR,</div><div class='ctx'> 			.bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div4_mux",</div><div class='ctx'> 			.ops = &amp;vc3_div_mux_ops,</div><div class='ctx'> 			.parent_data = div_mux_parent_data[VC3_DIV4_MUX],</div><div class='hunk'>@@ -805,7 +797,7 @@ static struct vc3_hw_data clk_div[] = {</div><div class='ctx'> 			.width = 4,</div><div class='ctx'> 			.flags = CLK_DIVIDER_READ_ONLY</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div1",</div><div class='ctx'> 			.ops = &amp;vc3_div_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -823,7 +815,7 @@ static struct vc3_hw_data clk_div[] = {</div><div class='ctx'> 			.width = 4,</div><div class='ctx'> 			.flags = CLK_DIVIDER_READ_ONLY</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div2",</div><div class='ctx'> 			.ops = &amp;vc3_div_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -841,7 +833,7 @@ static struct vc3_hw_data clk_div[] = {</div><div class='ctx'> 			.width = 4,</div><div class='ctx'> 			.flags = CLK_DIVIDER_READ_ONLY</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div3",</div><div class='ctx'> 			.ops = &amp;vc3_div_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -859,7 +851,7 @@ static struct vc3_hw_data clk_div[] = {</div><div class='ctx'> 			.width = 4,</div><div class='ctx'> 			.flags = CLK_DIVIDER_READ_ONLY</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div4",</div><div class='ctx'> 			.ops = &amp;vc3_div_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -877,7 +869,7 @@ static struct vc3_hw_data clk_div[] = {</div><div class='ctx'> 			.width = 4,</div><div class='ctx'> 			.flags = CLK_DIVIDER_READ_ONLY</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "div5",</div><div class='ctx'> 			.ops = &amp;vc3_div_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -895,7 +887,7 @@ static struct vc3_hw_data clk_mux[] = {</div><div class='ctx'> 			.offs = VC3_SE1_DIV4_CTRL,</div><div class='ctx'> 			.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "se1_mux",</div><div class='ctx'> 			.ops = &amp;vc3_clk_mux_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -911,7 +903,7 @@ static struct vc3_hw_data clk_mux[] = {</div><div class='ctx'> 			.offs = VC3_SE2_CTRL_REG0,</div><div class='ctx'> 			.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "se2_mux",</div><div class='ctx'> 			.ops = &amp;vc3_clk_mux_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -927,7 +919,7 @@ static struct vc3_hw_data clk_mux[] = {</div><div class='ctx'> 			.offs = VC3_SE3_DIFF1_CTRL_REG,</div><div class='ctx'> 			.bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "se3_mux",</div><div class='ctx'> 			.ops = &amp;vc3_clk_mux_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -943,7 +935,7 @@ static struct vc3_hw_data clk_mux[] = {</div><div class='ctx'> 			.offs = VC3_DIFF1_CTRL_REG,</div><div class='ctx'> 			.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "diff1_mux",</div><div class='ctx'> 			.ops = &amp;vc3_clk_mux_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='hunk'>@@ -959,7 +951,7 @@ static struct vc3_hw_data clk_mux[] = {</div><div class='ctx'> 			.offs = VC3_DIFF2_CTRL_REG,</div><div class='ctx'> 			.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL</div><div class='ctx'> 		},</div><div class='del'>-		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data) {</div><div class='ctx'> 			.name = "diff2_mux",</div><div class='ctx'> 			.ops = &amp;vc3_clk_mux_ops,</div><div class='ctx'> 			.parent_hws = (const struct clk_hw *[]) {</div><div class='head'>diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c<br/>index 2d7186905abd..5d0226530fdb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/hisilicon/clk-hi3620.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/hisilicon/clk-hi3620.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/hisilicon/clk-hi3620.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/hisilicon/clk-hi3620.c</a></div><div class='hunk'>@@ -466,8 +466,10 @@ static void __init hi3620_mmc_clk_init(struct device_node *node)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	clk_data-&gt;clks = kcalloc(num, sizeof(*clk_data-&gt;clks), GFP_KERNEL);</div><div class='del'>-	if (!clk_data-&gt;clks)</div><div class='add'>+	if (!clk_data-&gt;clks) {</div><div class='add'>+		kfree(clk_data);</div><div class='ctx'> 		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num; i++) {</div><div class='ctx'> 		struct hisi_mmc_clock *mmc_clk = &amp;hi3620_mmc_clks[i];</div><div class='head'>diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c<br/>index 41f0a45aa162..7d8883916cac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-imx8qxp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/imx/clk-imx8qxp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-imx8qxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-imx8qxp.c</a></div><div class='hunk'>@@ -66,6 +66,22 @@ static const char * const lcd_pxl_sels[] = {</div><div class='ctx'> 	"lcd_pxl_bypass_div_clk",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const char *const lvds0_sels[] = {</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"mipi0_lvds_bypass_clk",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const lvds1_sels[] = {</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"clk_dummy",</div><div class='add'>+	"mipi1_lvds_bypass_clk",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const char * const mipi_sels[] = {</div><div class='ctx'> 	"clk_dummy",</div><div class='ctx'> 	"clk_dummy",</div><div class='hunk'>@@ -207,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* MIPI-LVDS SS */</div><div class='ctx'> 	imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);</div><div class='ctx'> 	imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);</div><div class='del'>-	imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);</div><div class='ctx'> 	imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);</div><div class='del'>-	imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);</div><div class='add'>+	imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);</div><div class='add'>+	imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);</div><div class='ctx'> 	imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);</div><div class='ctx'> 	imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);</div><div class='ctx'> 	imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);</div><div class='hunk'>@@ -219,9 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);</div><div class='ctx'> 	imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);</div><div class='del'>-	imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);</div><div class='ctx'> 	imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);</div><div class='del'>-	imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);</div><div class='add'>+	imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);</div><div class='add'>+	imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);</div><div class='ctx'> </div><div class='ctx'> 	imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);</div><div class='ctx'> 	imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);</div><div class='head'>diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c<br/>index 0d58d85c375e..d63564dbb12c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-pll14xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/imx/clk-pll14xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-pll14xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-pll14xx.c</a></div><div class='hunk'>@@ -104,15 +104,15 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings(</div><div class='ctx'> static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,</div><div class='ctx'> 			      int sdiv, int kdiv, unsigned long prate)</div><div class='ctx'> {</div><div class='del'>-	u64 fvco = prate;</div><div class='add'>+	u64 fout = prate;</div><div class='ctx'> </div><div class='del'>-	/* fvco = (m * 65536 + k) * Fin / (p * 65536) */</div><div class='del'>-	fvco *= (mdiv * 65536 + kdiv);</div><div class='add'>+	/* fout = (m * 65536 + k) * Fin / (p * 65536) / (1 &lt;&lt; sdiv) */</div><div class='add'>+	fout *= (mdiv * 65536 + kdiv);</div><div class='ctx'> 	pdiv *= 65536;</div><div class='ctx'> </div><div class='del'>-	do_div(fvco, pdiv &lt;&lt; sdiv);</div><div class='add'>+	do_div(fout, pdiv &lt;&lt; sdiv);</div><div class='ctx'> </div><div class='del'>-	return fvco;</div><div class='add'>+	return fout;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv,</div><div class='hunk'>@@ -131,7 +131,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat</div><div class='ctx'> {</div><div class='ctx'> 	u32 pll_div_ctl0, pll_div_ctl1;</div><div class='ctx'> 	int mdiv, pdiv, sdiv, kdiv;</div><div class='del'>-	long fvco, rate_min, rate_max, dist, best = LONG_MAX;</div><div class='add'>+	long fout, rate_min, rate_max, dist, best = LONG_MAX;</div><div class='ctx'> 	const struct imx_pll14xx_rate_table *tt;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -143,6 +143,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat</div><div class='ctx'> 	 * d) -32768 &lt;= k &lt;= 32767</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * fvco = (m * 65536 + k) * prate / (p * 65536)</div><div class='add'>+	 * fout = (m * 65536 + k) * prate / (p * 65536) / (1 &lt;&lt; sdiv)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/* First try if we can get the desired rate from one of the static entries */</div><div class='hunk'>@@ -173,8 +174,8 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat</div><div class='ctx'> 		pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -&gt; %d\n",</div><div class='ctx'> 			 clk_hw_get_name(&amp;pll-&gt;hw), prate, rate,</div><div class='ctx'> 			 FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);</div><div class='del'>-		fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);</div><div class='del'>-		t-&gt;rate = (unsigned int)fvco;</div><div class='add'>+		fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);</div><div class='add'>+		t-&gt;rate = (unsigned int)fout;</div><div class='ctx'> 		t-&gt;mdiv = mdiv;</div><div class='ctx'> 		t-&gt;pdiv = pdiv;</div><div class='ctx'> 		t-&gt;sdiv = sdiv;</div><div class='hunk'>@@ -190,13 +191,13 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat</div><div class='ctx'> 			mdiv = clamp(mdiv, 64, 1023);</div><div class='ctx'> </div><div class='ctx'> 			kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);</div><div class='del'>-			fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);</div><div class='add'>+			fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);</div><div class='ctx'> </div><div class='ctx'> 			/* best match */</div><div class='del'>-			dist = abs((long)rate - (long)fvco);</div><div class='add'>+			dist = abs((long)rate - (long)fout);</div><div class='ctx'> 			if (dist &lt; best) {</div><div class='ctx'> 				best = dist;</div><div class='del'>-				t-&gt;rate = (unsigned int)fvco;</div><div class='add'>+				t-&gt;rate = (unsigned int)fout;</div><div class='ctx'> 				t-&gt;mdiv = mdiv;</div><div class='ctx'> 				t-&gt;pdiv = pdiv;</div><div class='ctx'> 				t-&gt;sdiv = sdiv;</div><div class='head'>diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c<br/>index be89180dd19c..e48a904c0013 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-scu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/imx/clk-scu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/imx/clk-scu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/imx/clk-scu.c</a></div><div class='hunk'>@@ -886,8 +886,10 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!imx_clk_is_resource_owned(rsrc_id))</div><div class='add'>+	if (!imx_clk_is_resource_owned(rsrc_id)) {</div><div class='add'>+		kfree(clk_node);</div><div class='ctx'> 		return NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	clk = kzalloc(sizeof(*clk), GFP_KERNEL);</div><div class='ctx'> 	if (!clk) {</div><div class='head'>diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig<br/>index 48b42d11111c..70a005e7e1b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/Kconfig</a></div><div class='hunk'>@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS</div><div class='ctx'> 	  This driver adds support for clocks for Ethernet and SGMII</div><div class='ctx'> 	  required on MediaTek MT7986 SoC.</div><div class='ctx'> </div><div class='add'>+config COMMON_CLK_MT7988</div><div class='add'>+	tristate "Clock driver for MediaTek MT7988"</div><div class='add'>+	depends on ARCH_MEDIATEK || COMPILE_TEST</div><div class='add'>+	select COMMON_CLK_MEDIATEK</div><div class='add'>+	default ARCH_MEDIATEK</div><div class='add'>+	help</div><div class='add'>+	  This driver supports MediaTek MT7988 basic clocks and clocks</div><div class='add'>+	  required for various periperals found on this SoC.</div><div class='add'>+</div><div class='ctx'> config COMMON_CLK_MT8135</div><div class='ctx'> 	tristate "Clock driver for MediaTek MT8135"</div><div class='ctx'> 	depends on (ARCH_MEDIATEK &amp;&amp; ARM) || COMPILE_TEST</div><div class='head'>diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile<br/>index dbeaa5b41177..eeccfa039896 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/Makefile</a></div><div class='hunk'>@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediatek/clk-mt7988-apmixed.c<br/>new file mode 100644<br/>index 000000000000..baf9564351a3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt7988-apmixed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-apmixed.c</a></div><div class='hunk'>@@ -0,0 +1,114 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Sam Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ * Author: Xiufeng Li &lt;Xiufeng.Li@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include "clk-mtk.h"</div><div class='add'>+#include "clk-gate.h"</div><div class='add'>+#include "clk-mux.h"</div><div class='add'>+#include "clk-pll.h"</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+</div><div class='add'>+#define MT7988_PLL_FMAX (2500UL * MHZ)</div><div class='add'>+#define MT7988_PCW_CHG_BIT 2</div><div class='add'>+</div><div class='add'>+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg,	\</div><div class='add'>+	    _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift,		\</div><div class='add'>+	    _pcw_chg_reg)									\</div><div class='add'>+	{											\</div><div class='add'>+		.id = _id,									\</div><div class='add'>+		.name = _name,									\</div><div class='add'>+		.reg = _reg,									\</div><div class='add'>+		.pwr_reg = _pwr_reg,								\</div><div class='add'>+		.en_mask = _en_mask,								\</div><div class='add'>+		.flags = _flags,								\</div><div class='add'>+		.rst_bar_mask = BIT(_rst_bar_mask),						\</div><div class='add'>+		.fmax = MT7988_PLL_FMAX,							\</div><div class='add'>+		.pcwbits = _pcwbits,								\</div><div class='add'>+		.pd_reg = _pd_reg,								\</div><div class='add'>+		.pd_shift = _pd_shift,								\</div><div class='add'>+		.tuner_reg = _tuner_reg,							\</div><div class='add'>+		.tuner_en_reg = _tuner_en_reg,							\</div><div class='add'>+		.tuner_en_bit = _tuner_en_bit,							\</div><div class='add'>+		.pcw_reg = _pcw_reg,								\</div><div class='add'>+		.pcw_shift = _pcw_shift,							\</div><div class='add'>+		.pcw_chg_reg = _pcw_chg_reg,							\</div><div class='add'>+		.pcw_chg_bit = MT7988_PCW_CHG_BIT,						\</div><div class='add'>+		.parent_name = "clkxtal",							\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mtk_pll_data plls[] = {</div><div class='add'>+	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,</div><div class='add'>+	    0, 0, 0x0108, 0, 0x0104),</div><div class='add'>+	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,</div><div class='add'>+	    0, 0, 0, 0x0118, 0, 0x0114),</div><div class='add'>+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,</div><div class='add'>+	    0, 0, 0, 0x0128, 0, 0x0124),</div><div class='add'>+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,</div><div class='add'>+	    0x0700, 1, 0x0138, 0, 0x0134),</div><div class='add'>+	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,</div><div class='add'>+	    0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),</div><div class='add'>+	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,</div><div class='add'>+	    32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),</div><div class='add'>+	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,</div><div class='add'>+	    0, 0, 0x0168, 0, 0x0164),</div><div class='add'>+	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,</div><div class='add'>+	    0x0178, 0, 0x0174),</div><div class='add'>+	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,</div><div class='add'>+	    0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),</div><div class='add'>+	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,</div><div class='add'>+	    0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),</div><div class='add'>+	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,</div><div class='add'>+	    0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),</div><div class='add'>+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,</div><div class='add'>+	    0, 0x0318, 0, 0x0314),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id of_match_clk_mt7988_apmixed[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt7988-apmixedsys" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int clk_mt7988_apmixed_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct clk_hw_onecell_data *clk_data;</div><div class='add'>+	struct device_node *node = pdev-&gt;dev.of_node;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));</div><div class='add'>+	if (!clk_data)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);</div><div class='add'>+	if (r)</div><div class='add'>+		goto free_apmixed_data;</div><div class='add'>+</div><div class='add'>+	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);</div><div class='add'>+	if (r)</div><div class='add'>+		goto unregister_plls;</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+</div><div class='add'>+unregister_plls:</div><div class='add'>+	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);</div><div class='add'>+free_apmixed_data:</div><div class='add'>+	mtk_free_clk_data(clk_data);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver clk_mt7988_apmixed_drv = {</div><div class='add'>+	.probe = clk_mt7988_apmixed_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "clk-mt7988-apmixed",</div><div class='add'>+		.of_match_table = of_match_clk_mt7988_apmixed,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+builtin_platform_driver(clk_mt7988_apmixed_drv);</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt7988-eth.c b/drivers/clk/mediatek/clk-mt7988-eth.c<br/>new file mode 100644<br/>index 000000000000..adf4a9d39b38<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt7988-eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-eth.c</a></div><div class='hunk'>@@ -0,0 +1,150 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Sam Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ * Author: Xiufeng Li &lt;Xiufeng.Li@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include "clk-mtk.h"</div><div class='add'>+#include "clk-gate.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/mediatek,mt7988-resets.h&gt;</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs ethdma_cg_regs = {</div><div class='add'>+	.set_ofs = 0x30,</div><div class='add'>+	.clr_ofs = 0x30,</div><div class='add'>+	.sta_ofs = 0x30,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GATE_ETHDMA(_id, _name, _parent, _shift)		\</div><div class='add'>+	{							\</div><div class='add'>+		.id = _id,					\</div><div class='add'>+		.name = _name,					\</div><div class='add'>+		.parent_name = _parent,				\</div><div class='add'>+		.regs = &amp;ethdma_cg_regs,			\</div><div class='add'>+		.shift = _shift,				\</div><div class='add'>+		.ops = &amp;mtk_clk_gate_ops_no_setclr_inv,		\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate ethdma_clks[] = {</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),</div><div class='add'>+	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc ethdma_desc = {</div><div class='add'>+	.clks = ethdma_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(ethdma_clks),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs sgmii_cg_regs = {</div><div class='add'>+	.set_ofs = 0xe4,</div><div class='add'>+	.clr_ofs = 0xe4,</div><div class='add'>+	.sta_ofs = 0xe4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GATE_SGMII(_id, _name, _parent, _shift)			\</div><div class='add'>+	{							\</div><div class='add'>+		.id = _id,					\</div><div class='add'>+		.name = _name,					\</div><div class='add'>+		.parent_name = _parent,				\</div><div class='add'>+		.regs = &amp;sgmii_cg_regs,				\</div><div class='add'>+		.shift = _shift,				\</div><div class='add'>+		.ops = &amp;mtk_clk_gate_ops_no_setclr_inv,		\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate sgmii0_clks[] = {</div><div class='add'>+	GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),</div><div class='add'>+	GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc sgmii0_desc = {</div><div class='add'>+	.clks = sgmii0_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(sgmii0_clks),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate sgmii1_clks[] = {</div><div class='add'>+	GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),</div><div class='add'>+	GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc sgmii1_desc = {</div><div class='add'>+	.clks = sgmii1_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(sgmii1_clks),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs ethwarp_cg_regs = {</div><div class='add'>+	.set_ofs = 0x14,</div><div class='add'>+	.clr_ofs = 0x14,</div><div class='add'>+	.sta_ofs = 0x14,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GATE_ETHWARP(_id, _name, _parent, _shift)		\</div><div class='add'>+	{							\</div><div class='add'>+		.id = _id,					\</div><div class='add'>+		.name = _name,					\</div><div class='add'>+		.parent_name = _parent,				\</div><div class='add'>+		.regs = &amp;ethwarp_cg_regs,			\</div><div class='add'>+		.shift = _shift,				\</div><div class='add'>+		.ops = &amp;mtk_clk_gate_ops_no_setclr_inv,		\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate ethwarp_clks[] = {</div><div class='add'>+	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),</div><div class='add'>+	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),</div><div class='add'>+	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u16 ethwarp_rst_ofs[] = { 0x8 };</div><div class='add'>+</div><div class='add'>+static u16 ethwarp_idx_map[] = {</div><div class='add'>+	[MT7988_ETHWARP_RST_SWITCH] = 9,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_rst_desc ethwarp_rst_desc = {</div><div class='add'>+	.version = MTK_RST_SIMPLE,</div><div class='add'>+	.rst_bank_ofs = ethwarp_rst_ofs,</div><div class='add'>+	.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),</div><div class='add'>+	.rst_idx_map = ethwarp_idx_map,</div><div class='add'>+	.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc ethwarp_desc = {</div><div class='add'>+	.clks = ethwarp_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(ethwarp_clks),</div><div class='add'>+	.rst_desc = &amp;ethwarp_rst_desc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id of_match_clk_mt7988_eth[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt7988-ethsys", .data = &amp;ethdma_desc },</div><div class='add'>+	{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &amp;sgmii0_desc },</div><div class='add'>+	{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &amp;sgmii1_desc },</div><div class='add'>+	{ .compatible = "mediatek,mt7988-ethwarp", .data = &amp;ethwarp_desc },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);</div><div class='add'>+</div><div class='add'>+static struct platform_driver clk_mt7988_eth_drv = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "clk-mt7988-eth",</div><div class='add'>+		.of_match_table = of_match_clk_mt7988_eth,</div><div class='add'>+	},</div><div class='add'>+	.probe = mtk_clk_simple_probe,</div><div class='add'>+	.remove_new = mtk_clk_simple_remove,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(clk_mt7988_eth_drv);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c<br/>new file mode 100644<br/>index 000000000000..8011ef278bea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt7988-infracfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-infracfg.c</a></div><div class='hunk'>@@ -0,0 +1,275 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Sam Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ * Author: Xiufeng Li &lt;Xiufeng.Li@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include "clk-mtk.h"</div><div class='add'>+#include "clk-gate.h"</div><div class='add'>+#include "clk-mux.h"</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+</div><div class='add'>+static DEFINE_SPINLOCK(mt7988_clk_lock);</div><div class='add'>+</div><div class='add'>+static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",</div><div class='add'>+								   "uart_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",</div><div class='add'>+								   "uart_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",</div><div class='add'>+								   "uart_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",</div><div class='add'>+								 "csw_infra_f26m_sel", "sysaxi_sel",</div><div class='add'>+								 "pwm_sel" };</div><div class='add'>+</div><div class='add'>+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {</div><div class='add'>+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {</div><div class='add'>+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {</div><div class='add'>+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {</div><div class='add'>+	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_mux infra_muxes[] = {</div><div class='add'>+	/* MODULE_CLK_SEL_0 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",</div><div class='add'>+			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",</div><div class='add'>+			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",</div><div class='add'>+			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,</div><div class='add'>+			     0x0010, 0x0014, 14, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,</div><div class='add'>+			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),</div><div class='add'>+	/* MODULE_CLK_SEL_1 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",</div><div class='add'>+			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,</div><div class='add'>+			     -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",</div><div class='add'>+			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,</div><div class='add'>+			     -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",</div><div class='add'>+			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,</div><div class='add'>+			     -1, -1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",</div><div class='add'>+			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,</div><div class='add'>+			     -1, -1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs infra0_cg_regs = {</div><div class='add'>+	.set_ofs = 0x10,</div><div class='add'>+	.clr_ofs = 0x14,</div><div class='add'>+	.sta_ofs = 0x18,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs infra1_cg_regs = {</div><div class='add'>+	.set_ofs = 0x40,</div><div class='add'>+	.clr_ofs = 0x44,</div><div class='add'>+	.sta_ofs = 0x48,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs infra2_cg_regs = {</div><div class='add'>+	.set_ofs = 0x50,</div><div class='add'>+	.clr_ofs = 0x54,</div><div class='add'>+	.sta_ofs = 0x58,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs infra3_cg_regs = {</div><div class='add'>+	.set_ofs = 0x60,</div><div class='add'>+	.clr_ofs = 0x64,</div><div class='add'>+	.sta_ofs = 0x68,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                                 \</div><div class='add'>+	GATE_MTK_FLAGS(_id, _name, _parent, &amp;infra0_cg_regs, _shift, &amp;mtk_clk_gate_ops_setclr, \</div><div class='add'>+		       _flags)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                                 \</div><div class='add'>+	GATE_MTK_FLAGS(_id, _name, _parent, &amp;infra1_cg_regs, _shift, &amp;mtk_clk_gate_ops_setclr, \</div><div class='add'>+		       _flags)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                                 \</div><div class='add'>+	GATE_MTK_FLAGS(_id, _name, _parent, &amp;infra2_cg_regs, _shift, &amp;mtk_clk_gate_ops_setclr, \</div><div class='add'>+		       _flags)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                                 \</div><div class='add'>+	GATE_MTK_FLAGS(_id, _name, _parent, &amp;infra3_cg_regs, _shift, &amp;mtk_clk_gate_ops_setclr, \</div><div class='add'>+		       _flags)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)</div><div class='add'>+</div><div class='add'>+#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate infra_clks[] = {</div><div class='add'>+	/* INFRA0 */</div><div class='add'>+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",</div><div class='add'>+		    "csw_infra_f26m_sel", 7),</div><div class='add'>+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",</div><div class='add'>+		    "csw_infra_f26m_sel", 8),</div><div class='add'>+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",</div><div class='add'>+		    "csw_infra_f26m_sel", 9),</div><div class='add'>+	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",</div><div class='add'>+		    "csw_infra_f26m_sel", 10),</div><div class='add'>+	/* INFRA1 */</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),</div><div class='add'>+	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	/* JTAG */</div><div class='add'>+	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),</div><div class='add'>+	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),</div><div class='add'>+	/* INFRA2 */</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",</div><div class='add'>+		    0),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),</div><div class='add'>+	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),</div><div class='add'>+	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),</div><div class='add'>+	GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),</div><div class='add'>+	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),</div><div class='add'>+	/* INFRA3 */</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),</div><div class='add'>+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,</div><div class='add'>+			  CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",</div><div class='add'>+			  9, CLK_IS_CRITICAL),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",</div><div class='add'>+		    "infra_pcie_gfmux_tl_o_p0_sel", 20),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",</div><div class='add'>+		    "infra_pcie_gfmux_tl_o_p1_sel", 21),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",</div><div class='add'>+		    "infra_pcie_gfmux_tl_o_p2_sel", 22),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",</div><div class='add'>+		    "infra_pcie_gfmux_tl_o_p3_sel", 23),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),</div><div class='add'>+	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc infra_desc = {</div><div class='add'>+	.clks = infra_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(infra_clks),</div><div class='add'>+	.mux_clks = infra_muxes,</div><div class='add'>+	.num_mux_clks = ARRAY_SIZE(infra_muxes),</div><div class='add'>+	.clk_lock = &amp;mt7988_clk_lock,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id of_match_clk_mt7988_infracfg[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt7988-infracfg", .data = &amp;infra_desc },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);</div><div class='add'>+</div><div class='add'>+static struct platform_driver clk_mt7988_infracfg_drv = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "clk-mt7988-infracfg",</div><div class='add'>+		.of_match_table = of_match_clk_mt7988_infracfg,</div><div class='add'>+	},</div><div class='add'>+	.probe = mtk_clk_simple_probe,</div><div class='add'>+	.remove_new = mtk_clk_simple_remove,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(clk_mt7988_infracfg_drv);</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt7988-topckgen.c b/drivers/clk/mediatek/clk-mt7988-topckgen.c<br/>new file mode 100644<br/>index 000000000000..760f8e0d2f26<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt7988-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-topckgen.c</a></div><div class='hunk'>@@ -0,0 +1,325 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ * Author: Sam Shih &lt;sam.shih@mediatek.com&gt;</div><div class='add'>+ * Author: Xiufeng Li &lt;Xiufeng.Li@mediatek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include "clk-mtk.h"</div><div class='add'>+#include "clk-gate.h"</div><div class='add'>+#include "clk-mux.h"</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+</div><div class='add'>+static DEFINE_SPINLOCK(mt7988_clk_lock);</div><div class='add'>+</div><div class='add'>+static const struct mtk_fixed_clk top_fixed_clks[] = {</div><div class='add'>+	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_fixed_factor top_divs[] = {</div><div class='add'>+	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),</div><div class='add'>+	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),</div><div class='add'>+	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),</div><div class='add'>+	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),</div><div class='add'>+	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),</div><div class='add'>+	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),</div><div class='add'>+	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),</div><div class='add'>+	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),</div><div class='add'>+	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),</div><div class='add'>+	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),</div><div class='add'>+	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),</div><div class='add'>+	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),</div><div class='add'>+	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),</div><div class='add'>+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),</div><div class='add'>+	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),</div><div class='add'>+	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };</div><div class='add'>+static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };</div><div class='add'>+static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };</div><div class='add'>+static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };</div><div class='add'>+static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };</div><div class='add'>+static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",    "mmpll",</div><div class='add'>+						  "net1pll_d4", "net1pll_d5", "mpll" };</div><div class='add'>+static const char *const eip197_parents[] = { "top_xtal", "netsyspll",	"net2pll",</div><div class='add'>+					      "mmpll",	  "net1pll_d4", "net1pll_d5" };</div><div class='add'>+static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };</div><div class='add'>+static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };</div><div class='add'>+static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };</div><div class='add'>+static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",	 "mmpll_d2",</div><div class='add'>+						 "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };</div><div class='add'>+static const char *const spi_parents[] = { "top_xtal",	    "mpll_d2",	    "mmpll_d4",</div><div class='add'>+					   "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",</div><div class='add'>+					   "mpll_d4",	    "net1pll_d8_d4" };</div><div class='add'>+static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",</div><div class='add'>+					     "mpll_d4",	 "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };</div><div class='add'>+static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",</div><div class='add'>+					      "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",</div><div class='add'>+					      "mmpll_d6_d2", "mpll_d8" };</div><div class='add'>+static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",</div><div class='add'>+					   "mpll_d4",  "mpll_d8_d2",	"top_rtc_32k" };</div><div class='add'>+static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",</div><div class='add'>+					   "net1pll_d8_d4" };</div><div class='add'>+static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };</div><div class='add'>+static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",</div><div class='add'>+						   "mpll_d8_d2", "top_rtc_32k" };</div><div class='add'>+static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };</div><div class='add'>+static const char *const aud_parents[] = { "top_xtal", "apll2" };</div><div class='add'>+static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };</div><div class='add'>+static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };</div><div class='add'>+static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };</div><div class='add'>+static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };</div><div class='add'>+static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };</div><div class='add'>+static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };</div><div class='add'>+static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };</div><div class='add'>+static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };</div><div class='add'>+static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };</div><div class='add'>+static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };</div><div class='add'>+static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };</div><div class='add'>+static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };</div><div class='add'>+static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };</div><div class='add'>+static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };</div><div class='add'>+static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };</div><div class='add'>+static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };</div><div class='add'>+static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };</div><div class='add'>+</div><div class='add'>+static const struct mtk_mux top_muxes[] = {</div><div class='add'>+	/* CLK_CFG_0 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,</div><div class='add'>+			     0, 2, 7, 0x1c0, 0),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,</div><div class='add'>+			     0x004, 0x008, 8, 2, 15, 0x1C0, 1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,</div><div class='add'>+			     0x004, 0x008, 16, 2, 23, 0x1C0, 2),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,</div><div class='add'>+			     0x004, 0x008, 24, 2, 31, 0x1C0, 3),</div><div class='add'>+	/* CLK_CFG_1 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,</div><div class='add'>+			     0x018, 0, 1, 7, 0x1C0, 4),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,</div><div class='add'>+			     0x014, 0x018, 8, 3, 15, 0x1C0, 5),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,</div><div class='add'>+			     0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,</div><div class='add'>+			     24, 3, 31, 0x1c0, 7),</div><div class='add'>+	/* CLK_CFG_2 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,</div><div class='add'>+				   0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,</div><div class='add'>+			     15, 0x1c0, 9),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,</div><div class='add'>+			     0x024, 0x028, 16, 2, 23, 0x1C0, 10),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,</div><div class='add'>+			     0x024, 0x028, 24, 3, 31, 0x1C0, 11),</div><div class='add'>+	/* CLK_CFG_3 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,</div><div class='add'>+			     0x1c0, 12),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,</div><div class='add'>+			     8, 3, 15, 0x1c0, 13),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,</div><div class='add'>+			     3, 23, 0x1c0, 14),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,</div><div class='add'>+			     24, 3, 31, 0x1c0, 15),</div><div class='add'>+	/* CLK_CFG_4 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,</div><div class='add'>+			     0x1c0, 16),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,</div><div class='add'>+			     0x1c0, 17),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",</div><div class='add'>+			     pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,</div><div class='add'>+			     0x044, 0x048, 24, 3, 31, 0x1C0, 19),</div><div class='add'>+	/* CLK_CFG_5 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,</div><div class='add'>+			     0x054, 0x058, 0, 3, 7, 0x1C0, 20),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,</div><div class='add'>+			     0x054, 0x058, 8, 3, 15, 0x1C0, 21),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,</div><div class='add'>+			     0x054, 0x058, 16, 3, 23, 0x1C0, 22),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,</div><div class='add'>+			     0x058, 24, 1, 31, 0x1C0, 23),</div><div class='add'>+	/* CLK_CFG_6 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,</div><div class='add'>+			     0x064, 0x068, 0, 1, 7, 0x1C0, 24),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,</div><div class='add'>+			     0x068, 8, 1, 15, 0x1C0, 25),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,</div><div class='add'>+			     0x064, 0x068, 16, 1, 23, 0x1C0, 26),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,</div><div class='add'>+			     0x064, 0x068, 24, 1, 31, 0x1C0, 27),</div><div class='add'>+	/* CLK_CFG_7 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,</div><div class='add'>+			     0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,</div><div class='add'>+			     0x1c0, 29),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,</div><div class='add'>+			     1, 23, 0x1c0, 30),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,</div><div class='add'>+			     2, 31, 0x1c4, 0),</div><div class='add'>+	/* CLK_CFG_8 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,</div><div class='add'>+			     0, 1, 7, 0x1c4, 1),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,</div><div class='add'>+			     8, 1, 15, 0x1c4, 2),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,</div><div class='add'>+			     0x088, 16, 1, 23, 0x1c4, 3),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",</div><div class='add'>+			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),</div><div class='add'>+	/* CLK_CFG_9 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",</div><div class='add'>+			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,</div><div class='add'>+			     1, 15, 0x1c4, 6),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,</div><div class='add'>+				   0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,</div><div class='add'>+			     1, 31, 0x1c4, 8),</div><div class='add'>+	/* CLK_CFG_10 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,</div><div class='add'>+				   0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,</div><div class='add'>+			     0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,</div><div class='add'>+			     0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),</div><div class='add'>+	/* CLK_CFG_11 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,</div><div class='add'>+				   0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,</div><div class='add'>+				   0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,</div><div class='add'>+			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,</div><div class='add'>+			     0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,</div><div class='add'>+			     0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),</div><div class='add'>+	/* CLK_CFG_12 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,</div><div class='add'>+			     0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,</div><div class='add'>+			     0x0c8, 8, 2, 15, 0x1C4, 18),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,</div><div class='add'>+			     0x0c8, 16, 1, 23, 0x1C4, 19),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,</div><div class='add'>+				   0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),</div><div class='add'>+	/* CLK_CFG_13 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,</div><div class='add'>+				   0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,</div><div class='add'>+				   0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,</div><div class='add'>+			     0x0d8, 16, 1, 23, 0x1C4, 23),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,</div><div class='add'>+			     0x0d8, 24, 1, 31, 0x1C4, 24),</div><div class='add'>+	/* CLK_CFG_14 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,</div><div class='add'>+			     0x0e8, 0, 1, 7, 0x1C4, 25),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,</div><div class='add'>+			     0x0e8, 8, 1, 15, 0x1C4, 26),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,</div><div class='add'>+			     0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,</div><div class='add'>+			     0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),</div><div class='add'>+	/* CLK_CFG_15 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,</div><div class='add'>+			     0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,</div><div class='add'>+			     0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,</div><div class='add'>+			     23, 0x1c8, 0),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,</div><div class='add'>+			     31, 0x1C8, 1),</div><div class='add'>+	/* CLK_CFG_16 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,</div><div class='add'>+			     0, 1, 7, 0x1c8, 2),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,</div><div class='add'>+			     0x104, 0x108, 8, 1, 15, 0x1C8, 3),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",</div><div class='add'>+			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",</div><div class='add'>+			     pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),</div><div class='add'>+	/* CLK_CFG_17 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,</div><div class='add'>+			     0, 2, 7, 0x1c8, 6),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",</div><div class='add'>+			     netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",</div><div class='add'>+			     pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,</div><div class='add'>+			     0x114, 0x118, 24, 2, 31, 0x1C8, 9),</div><div class='add'>+	/* CLK_CFG_18 */</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,</div><div class='add'>+			     0x128, 0, 1, 7, 0x1c8, 10),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,</div><div class='add'>+			     8, 2, 15, 0x1c8, 11),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_composite top_aud_divs[] = {</div><div class='add'>+	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc topck_desc = {</div><div class='add'>+	.fixed_clks = top_fixed_clks,</div><div class='add'>+	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),</div><div class='add'>+	.factor_clks = top_divs,</div><div class='add'>+	.num_factor_clks = ARRAY_SIZE(top_divs),</div><div class='add'>+	.mux_clks = top_muxes,</div><div class='add'>+	.num_mux_clks = ARRAY_SIZE(top_muxes),</div><div class='add'>+	.composite_clks = top_aud_divs,</div><div class='add'>+	.num_composite_clks = ARRAY_SIZE(top_aud_divs),</div><div class='add'>+	.clk_lock = &amp;mt7988_clk_lock,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };</div><div class='add'>+</div><div class='add'>+static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };</div><div class='add'>+</div><div class='add'>+static struct mtk_composite mcu_muxes[] = {</div><div class='add'>+	/* bus_pll_divider_cfg */</div><div class='add'>+	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,</div><div class='add'>+		       CLK_IS_CRITICAL),</div><div class='add'>+	/* mp2_pll_divider_cfg */</div><div class='add'>+	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,</div><div class='add'>+		       CLK_IS_CRITICAL),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc mcusys_desc = {</div><div class='add'>+	.composite_clks = mcu_muxes,</div><div class='add'>+	.num_composite_clks = ARRAY_SIZE(mcu_muxes),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id of_match_clk_mt7988_topckgen[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt7988-topckgen", .data = &amp;topck_desc },</div><div class='add'>+	{ .compatible = "mediatek,mt7988-mcusys", .data = &amp;mcusys_desc },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);</div><div class='add'>+</div><div class='add'>+static struct platform_driver clk_mt7988_topckgen_drv = {</div><div class='add'>+	.probe = mtk_clk_simple_probe,</div><div class='add'>+	.remove_new = mtk_clk_simple_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "clk-mt7988-topckgen",</div><div class='add'>+		.of_match_table = of_match_clk_mt7988_topckgen,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_platform_driver(clk_mt7988_topckgen_drv);</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt7988-xfipll.c b/drivers/clk/mediatek/clk-mt7988-xfipll.c<br/>new file mode 100644<br/>index 000000000000..9b9ca5471158<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt7988-xfipll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt7988-xfipll.c</a></div><div class='hunk'>@@ -0,0 +1,82 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Daniel Golle &lt;daniel@makrotopia.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include "clk-mtk.h"</div><div class='add'>+#include "clk-gate.h"</div><div class='add'>+#include &lt;dt-bindings/clock/mediatek,mt7988-clk.h&gt;</div><div class='add'>+</div><div class='add'>+/* Register to control USXGMII XFI PLL analog */</div><div class='add'>+#define XFI_PLL_ANA_GLB8		0x108</div><div class='add'>+#define RG_XFI_PLL_ANA_SWWA		0x02283248</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate_regs xfipll_cg_regs = {</div><div class='add'>+	.set_ofs = 0x8,</div><div class='add'>+	.clr_ofs = 0x8,</div><div class='add'>+	.sta_ofs = 0x8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GATE_XFIPLL(_id, _name, _parent, _shift)		\</div><div class='add'>+	{							\</div><div class='add'>+		.id = _id,					\</div><div class='add'>+		.name = _name,					\</div><div class='add'>+		.parent_name = _parent,				\</div><div class='add'>+		.regs = &amp;xfipll_cg_regs,			\</div><div class='add'>+		.shift = _shift,				\</div><div class='add'>+		.ops = &amp;mtk_clk_gate_ops_no_setclr_inv,		\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mtk_fixed_factor xfipll_divs[] = {</div><div class='add'>+	FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_gate xfipll_clks[] = {</div><div class='add'>+	GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_clk_desc xfipll_desc = {</div><div class='add'>+	.clks = xfipll_clks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(xfipll_clks),</div><div class='add'>+	.factor_clks = xfipll_divs,</div><div class='add'>+	.num_factor_clks = ARRAY_SIZE(xfipll_divs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int clk_mt7988_xfipll_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device_node *node = pdev-&gt;dev.of_node;</div><div class='add'>+	void __iomem *base = of_iomap(node, 0);</div><div class='add'>+</div><div class='add'>+	if (!base)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Apply software workaround for USXGMII PLL TCL issue */</div><div class='add'>+	writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);</div><div class='add'>+	iounmap(base);</div><div class='add'>+</div><div class='add'>+	return mtk_clk_simple_probe(pdev);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id of_match_clk_mt7988_xfipll[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt7988-xfi-pll", .data = &amp;xfipll_desc },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);</div><div class='add'>+</div><div class='add'>+static struct platform_driver clk_mt7988_xfipll_drv = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "clk-mt7988-xfipll",</div><div class='add'>+		.of_match_table = of_match_clk_mt7988_xfipll,</div><div class='add'>+	},</div><div class='add'>+	.probe = clk_mt7988_xfipll_probe,</div><div class='add'>+	.remove_new = mtk_clk_simple_remove,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(clk_mt7988_xfipll_drv);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c<br/>index e330a4f9a0c3..f7ec599b20af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt8188-topckgen.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-mt8188-topckgen.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt8188-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt8188-topckgen.c</a></div><div class='hunk'>@@ -475,29 +475,28 @@ static const char * const sspm_parents[] = {</div><div class='ctx'> 	"mainpll_d4_d2"</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using</div><div class='add'>+ * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate</div><div class='add'>+ * in dual output case, which would lead to corruption of functionality loss.</div><div class='add'>+ */</div><div class='ctx'> static const char * const dp_parents[] = {</div><div class='ctx'> 	"clk26m",</div><div class='del'>-	"tvdpll1_d2",</div><div class='ctx'> 	"tvdpll2_d2",</div><div class='del'>-	"tvdpll1_d4",</div><div class='ctx'> 	"tvdpll2_d4",</div><div class='del'>-	"tvdpll1_d8",</div><div class='ctx'> 	"tvdpll2_d8",</div><div class='del'>-	"tvdpll1_d16",</div><div class='ctx'> 	"tvdpll2_d16"</div><div class='ctx'> };</div><div class='add'>+static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };</div><div class='ctx'> </div><div class='ctx'> static const char * const edp_parents[] = {</div><div class='ctx'> 	"clk26m",</div><div class='ctx'> 	"tvdpll1_d2",</div><div class='del'>-	"tvdpll2_d2",</div><div class='ctx'> 	"tvdpll1_d4",</div><div class='del'>-	"tvdpll2_d4",</div><div class='ctx'> 	"tvdpll1_d8",</div><div class='del'>-	"tvdpll2_d8",</div><div class='del'>-	"tvdpll1_d16",</div><div class='del'>-	"tvdpll2_d16"</div><div class='add'>+	"tvdpll1_d16"</div><div class='ctx'> };</div><div class='add'>+static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };</div><div class='ctx'> </div><div class='ctx'> static const char * const dpi_parents[] = {</div><div class='ctx'> 	"clk26m",</div><div class='hunk'>@@ -1038,10 +1037,12 @@ static const struct mtk_mux top_mtk_muxes[] = {</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",</div><div class='ctx'> 			     sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),</div><div class='ctx'> 	/* CLK_CFG_9 */</div><div class='del'>-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",</div><div class='del'>-			     dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4),</div><div class='del'>-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",</div><div class='del'>-			     edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",</div><div class='add'>+				     dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094,</div><div class='add'>+				     0, 4, 7, 0x08, 4),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",</div><div class='add'>+				     edp_parents, edp_parents_idx, 0x08C, 0x090, 0x094,</div><div class='add'>+				     8, 4, 15, 0x08, 5),</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",</div><div class='ctx'> 			     dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c<br/>index 5c426a1c94c7..8f713a3341a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt8195-topckgen.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-mt8195-topckgen.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mt8195-topckgen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mt8195-topckgen.c</a></div><div class='hunk'>@@ -415,17 +415,28 @@ static const char * const pwrmcu_parents[] = {</div><div class='ctx'> 	"mainpll_d4_d2"</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using</div><div class='add'>+ * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate</div><div class='add'>+ * in dual output case, which would lead to corruption of functionality loss.</div><div class='add'>+ */</div><div class='ctx'> static const char * const dp_parents[] = {</div><div class='ctx'> 	"clk26m",</div><div class='del'>-	"tvdpll1_d2",</div><div class='ctx'> 	"tvdpll2_d2",</div><div class='del'>-	"tvdpll1_d4",</div><div class='ctx'> 	"tvdpll2_d4",</div><div class='del'>-	"tvdpll1_d8",</div><div class='ctx'> 	"tvdpll2_d8",</div><div class='del'>-	"tvdpll1_d16",</div><div class='ctx'> 	"tvdpll2_d16"</div><div class='ctx'> };</div><div class='add'>+static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };</div><div class='add'>+</div><div class='add'>+static const char * const edp_parents[] = {</div><div class='add'>+	"clk26m",</div><div class='add'>+	"tvdpll1_d2",</div><div class='add'>+	"tvdpll1_d4",</div><div class='add'>+	"tvdpll1_d8",</div><div class='add'>+	"tvdpll1_d16"</div><div class='add'>+};</div><div class='add'>+static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };</div><div class='ctx'> </div><div class='ctx'> static const char * const disp_pwm_parents[] = {</div><div class='ctx'> 	"clk26m",</div><div class='hunk'>@@ -957,11 +968,11 @@ static const struct mtk_mux top_mtk_muxes[] = {</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",</div><div class='ctx'> 		pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,</div><div class='ctx'> 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),</div><div class='del'>-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",</div><div class='del'>-		dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",</div><div class='add'>+		dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),</div><div class='ctx'> 	/* CLK_CFG_10 */</div><div class='del'>-	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",</div><div class='del'>-		dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),</div><div class='add'>+	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",</div><div class='add'>+		edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",</div><div class='ctx'> 		dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),</div><div class='ctx'> 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c<br/>index c93bc7f926e5..60990296450b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mux.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-mux.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mux.c</a></div><div class='hunk'>@@ -89,6 +89,17 @@ static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)</div><div class='ctx'> 	regmap_read(mux-&gt;regmap, mux-&gt;data-&gt;mux_ofs, &amp;val);</div><div class='ctx'> 	val = (val &gt;&gt; mux-&gt;data-&gt;mux_shift) &amp; mask;</div><div class='ctx'> </div><div class='add'>+	if (mux-&gt;data-&gt;parent_index) {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; mux-&gt;data-&gt;num_parents; i++)</div><div class='add'>+			if (mux-&gt;data-&gt;parent_index[i] == val)</div><div class='add'>+				return i;</div><div class='add'>+</div><div class='add'>+		/* Not found: return an impossible index to generate error */</div><div class='add'>+		return mux-&gt;data-&gt;num_parents + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -104,6 +115,9 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)</div><div class='ctx'> 	else</div><div class='ctx'> 		__acquire(mux-&gt;lock);</div><div class='ctx'> </div><div class='add'>+	if (mux-&gt;data-&gt;parent_index)</div><div class='add'>+		index = mux-&gt;data-&gt;parent_index[index];</div><div class='add'>+</div><div class='ctx'> 	regmap_read(mux-&gt;regmap, mux-&gt;data-&gt;mux_ofs, &amp;orig);</div><div class='ctx'> 	val = (orig &amp; ~(mask &lt;&lt; mux-&gt;data-&gt;mux_shift))</div><div class='ctx'> 			| (index &lt;&lt; mux-&gt;data-&gt;mux_shift);</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h<br/>index 7ecb963b0ec6..943ad1d7ce4b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mux.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-mux.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-mux.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-mux.h</a></div><div class='hunk'>@@ -21,6 +21,7 @@ struct mtk_mux {</div><div class='ctx'> 	int id;</div><div class='ctx'> 	const char *name;</div><div class='ctx'> 	const char * const *parent_names;</div><div class='add'>+	const u8 *parent_index;</div><div class='ctx'> 	unsigned int flags;</div><div class='ctx'> </div><div class='ctx'> 	u32 mux_ofs;</div><div class='hunk'>@@ -37,9 +38,10 @@ struct mtk_mux {</div><div class='ctx'> 	signed char num_parents;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,		\</div><div class='del'>-			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='del'>-			_gate, _upd_ofs, _upd, _flags, _ops) {		\</div><div class='add'>+#define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx,		\</div><div class='add'>+			 _num_parents, _mux_ofs, _mux_set_ofs,		\</div><div class='add'>+			 _mux_clr_ofs, _shift, _width, _gate, _upd_ofs,	\</div><div class='add'>+			 _upd, _flags, _ops) {				\</div><div class='ctx'> 		.id = _id,						\</div><div class='ctx'> 		.name = _name,						\</div><div class='ctx'> 		.mux_ofs = _mux_ofs,					\</div><div class='hunk'>@@ -51,11 +53,28 @@ struct mtk_mux {</div><div class='ctx'> 		.gate_shift = _gate,					\</div><div class='ctx'> 		.upd_shift = _upd,					\</div><div class='ctx'> 		.parent_names = _parents,				\</div><div class='del'>-		.num_parents = ARRAY_SIZE(_parents),			\</div><div class='add'>+		.parent_index = _paridx,				\</div><div class='add'>+		.num_parents = _num_parents,				\</div><div class='ctx'> 		.flags = _flags,					\</div><div class='ctx'> 		.ops = &amp;_ops,						\</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,		\</div><div class='add'>+			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='add'>+			_gate, _upd_ofs, _upd, _flags, _ops)		\</div><div class='add'>+		__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,		\</div><div class='add'>+			NULL, ARRAY_SIZE(_parents), _mux_ofs,		\</div><div class='add'>+			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='add'>+			_gate, _upd_ofs, _upd, _flags, _ops)		\</div><div class='add'>+</div><div class='add'>+#define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx,	\</div><div class='add'>+			 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,	\</div><div class='add'>+			 _width, _gate, _upd_ofs, _upd, _flags, _ops)	\</div><div class='add'>+		__GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,		\</div><div class='add'>+			_paridx, ARRAY_SIZE(_paridx), _mux_ofs,		\</div><div class='add'>+			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='add'>+			_gate, _upd_ofs, _upd, _flags, _ops)		\</div><div class='add'>+</div><div class='ctx'> extern const struct clk_ops mtk_mux_clr_set_upd_ops;</div><div class='ctx'> extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;</div><div class='ctx'> </div><div class='hunk'>@@ -67,6 +86,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;</div><div class='ctx'> 			_gate, _upd_ofs, _upd, _flags,			\</div><div class='ctx'> 			mtk_mux_gate_clr_set_upd_ops)</div><div class='ctx'> </div><div class='add'>+#define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents,	\</div><div class='add'>+			_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,	\</div><div class='add'>+			_shift, _width, _gate, _upd_ofs, _upd, _flags)	\</div><div class='add'>+		GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents,	\</div><div class='add'>+			_paridx, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,	\</div><div class='add'>+			_shift, _width, _gate, _upd_ofs, _upd, _flags,	\</div><div class='add'>+			mtk_mux_gate_clr_set_upd_ops)</div><div class='add'>+</div><div class='ctx'> #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,		\</div><div class='ctx'> 			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='ctx'> 			_gate, _upd_ofs, _upd)				\</div><div class='hunk'>@@ -75,6 +102,14 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;</div><div class='ctx'> 			_width, _gate, _upd_ofs, _upd,			\</div><div class='ctx'> 			CLK_SET_RATE_PARENT)</div><div class='ctx'> </div><div class='add'>+#define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx,	\</div><div class='add'>+			_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,	\</div><div class='add'>+			_width, _gate, _upd_ofs, _upd)			\</div><div class='add'>+		MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name,		\</div><div class='add'>+			_parents, _paridx, _mux_ofs, _mux_set_ofs,	\</div><div class='add'>+			_mux_clr_ofs, _shift, _width, _gate, _upd_ofs,	\</div><div class='add'>+			_upd, CLK_SET_RATE_PARENT)</div><div class='add'>+</div><div class='ctx'> #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,			\</div><div class='ctx'> 			_mux_set_ofs, _mux_clr_ofs, _shift, _width,	\</div><div class='ctx'> 			_upd_ofs, _upd)					\</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c<br/>index 513ab6b1b322..ce453e1718e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-pll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-pll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-pll.c</a></div><div class='hunk'>@@ -23,7 +23,7 @@</div><div class='ctx'> #define CON0_BASE_EN		BIT(0)</div><div class='ctx'> #define CON0_PWR_ON		BIT(0)</div><div class='ctx'> #define CON0_ISO_EN		BIT(1)</div><div class='del'>-#define PCW_CHG_MASK		BIT(31)</div><div class='add'>+#define PCW_CHG_BIT		31</div><div class='ctx'> </div><div class='ctx'> #define AUDPLL_TUNER_EN		BIT(31)</div><div class='ctx'> </div><div class='hunk'>@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,</div><div class='ctx'> 			pll-&gt;data-&gt;pcw_shift);</div><div class='ctx'> 	val |= pcw &lt;&lt; pll-&gt;data-&gt;pcw_shift;</div><div class='ctx'> 	writel(val, pll-&gt;pcw_addr);</div><div class='del'>-	chg = readl(pll-&gt;pcw_chg_addr) | PCW_CHG_MASK;</div><div class='add'>+	chg = readl(pll-&gt;pcw_chg_addr) |</div><div class='add'>+	      BIT(pll-&gt;data-&gt;pcw_chg_bit ? : PCW_CHG_BIT);</div><div class='ctx'> 	writel(chg, pll-&gt;pcw_chg_addr);</div><div class='ctx'> 	if (pll-&gt;tuner_addr)</div><div class='ctx'> 		writel(val + 1, pll-&gt;tuner_addr);</div><div class='head'>diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h<br/>index f17278ff15d7..285c8db958b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-pll.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mediatek/clk-pll.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mediatek/clk-pll.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mediatek/clk-pll.h</a></div><div class='hunk'>@@ -48,6 +48,7 @@ struct mtk_pll_data {</div><div class='ctx'> 	const char *parent_name;</div><div class='ctx'> 	u32 en_reg;</div><div class='ctx'> 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */</div><div class='add'>+	u8 pcw_chg_bit;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c<br/>index f373a8d48b1d..90f4c6103014 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/meson/g12a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/meson/g12a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/meson/g12a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/meson/g12a.c</a></div><div class='hunk'>@@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_regmap g12a_cts_encl_sel = {</div><div class='add'>+	.data = &amp;(struct clk_regmap_mux_data){</div><div class='add'>+		.offset = HHI_VIID_CLK_DIV,</div><div class='add'>+		.mask = 0xf,</div><div class='add'>+		.shift = 12,</div><div class='add'>+		.table = mux_table_cts_sel,</div><div class='add'>+	},</div><div class='add'>+	.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "cts_encl_sel",</div><div class='add'>+		.ops = &amp;clk_regmap_mux_ops,</div><div class='add'>+		.parent_hws = g12a_cts_parent_hws,</div><div class='add'>+		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),</div><div class='add'>+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct clk_regmap g12a_cts_vdac_sel = {</div><div class='ctx'> 	.data = &amp;(struct clk_regmap_mux_data){</div><div class='ctx'> 		.offset = HHI_VIID_CLK_DIV,</div><div class='hunk'>@@ -3628,6 +3644,22 @@ static struct clk_regmap g12a_cts_encp = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_regmap g12a_cts_encl = {</div><div class='add'>+	.data = &amp;(struct clk_regmap_gate_data){</div><div class='add'>+		.offset = HHI_VID_CLK_CNTL2,</div><div class='add'>+		.bit_idx = 3,</div><div class='add'>+	},</div><div class='add'>+	.hw.init = &amp;(struct clk_init_data) {</div><div class='add'>+		.name = "cts_encl",</div><div class='add'>+		.ops = &amp;clk_regmap_gate_ops,</div><div class='add'>+		.parent_hws = (const struct clk_hw *[]) {</div><div class='add'>+			&amp;g12a_cts_encl_sel.hw</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct clk_regmap g12a_cts_vdac = {</div><div class='ctx'> 	.data = &amp;(struct clk_regmap_gate_data){</div><div class='ctx'> 		.offset = HHI_VID_CLK_CNTL2,</div><div class='hunk'>@@ -3722,6 +3754,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* MIPI ISP Clocks */</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {</div><div class='add'>+	{ .fw_name = "xtal", },</div><div class='add'>+	{ .hw = &amp;g12a_gp0_pll.hw },</div><div class='add'>+	{ .hw = &amp;g12a_hifi_pll.hw },</div><div class='add'>+	{ .hw = &amp;g12a_fclk_div2p5.hw },</div><div class='add'>+	{ .hw = &amp;g12a_fclk_div3.hw },</div><div class='add'>+	{ .hw = &amp;g12a_fclk_div4.hw },</div><div class='add'>+	{ .hw = &amp;g12a_fclk_div5.hw },</div><div class='add'>+	{ .hw = &amp;g12a_fclk_div7.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap g12b_mipi_isp_sel = {</div><div class='add'>+	.data = &amp;(struct clk_regmap_mux_data){</div><div class='add'>+		.offset = HHI_ISP_CLK_CNTL,</div><div class='add'>+		.mask = 7,</div><div class='add'>+		.shift = 9,</div><div class='add'>+	},</div><div class='add'>+	.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "mipi_isp_sel",</div><div class='add'>+		.ops = &amp;clk_regmap_mux_ops,</div><div class='add'>+		.parent_data = g12b_mipi_isp_parent_data,</div><div class='add'>+		.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap g12b_mipi_isp_div = {</div><div class='add'>+	.data = &amp;(struct clk_regmap_div_data){</div><div class='add'>+		.offset = HHI_ISP_CLK_CNTL,</div><div class='add'>+		.shift = 0,</div><div class='add'>+		.width = 7,</div><div class='add'>+	},</div><div class='add'>+	.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "mipi_isp_div",</div><div class='add'>+		.ops = &amp;clk_regmap_divider_ops,</div><div class='add'>+		.parent_hws = (const struct clk_hw *[]) {</div><div class='add'>+			&amp;g12b_mipi_isp_sel.hw</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap g12b_mipi_isp = {</div><div class='add'>+	.data = &amp;(struct clk_regmap_gate_data){</div><div class='add'>+		.offset = HHI_ISP_CLK_CNTL,</div><div class='add'>+		.bit_idx = 8,</div><div class='add'>+	},</div><div class='add'>+	.hw.init = &amp;(struct clk_init_data) {</div><div class='add'>+		.name = "mipi_isp",</div><div class='add'>+		.ops = &amp;clk_regmap_gate_ops,</div><div class='add'>+		.parent_hws = (const struct clk_hw *[]) {</div><div class='add'>+			&amp;g12b_mipi_isp_div.hw</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* HDMI Clocks */</div><div class='ctx'> </div><div class='ctx'> static const struct clk_parent_data g12a_hdmi_parent_data[] = {</div><div class='hunk'>@@ -4214,9 +4306,12 @@ static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);</div><div class='ctx'> static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);</div><div class='ctx'> static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);</div><div class='ctx'> static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);</div><div class='add'>+static MESON_GATE(g12b_mipi_isp_gate,		HHI_GCLK_MPEG2,	17);</div><div class='ctx'> static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);</div><div class='ctx'> static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);</div><div class='ctx'> static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);</div><div class='add'>+static MESON_GATE(g12b_csi_phy1,		HHI_GCLK_MPEG2,	28);</div><div class='add'>+static MESON_GATE(g12b_csi_phy0,		HHI_GCLK_MPEG2,	29);</div><div class='ctx'> static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);</div><div class='ctx'> </div><div class='ctx'> static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);</div><div class='hunk'>@@ -4407,10 +4502,12 @@ static struct clk_hw *g12a_hw_clks[] = {</div><div class='ctx'> 	[CLKID_VCLK2_DIV12]		= &amp;g12a_vclk2_div12.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI_SEL]		= &amp;g12a_cts_enci_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP_SEL]		= &amp;g12a_cts_encp_sel.hw,</div><div class='add'>+	[CLKID_CTS_ENCL_SEL]		= &amp;g12a_cts_encl_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC_SEL]		= &amp;g12a_cts_vdac_sel.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX_SEL]		= &amp;g12a_hdmi_tx_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI]		= &amp;g12a_cts_enci.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP]		= &amp;g12a_cts_encp.hw,</div><div class='add'>+	[CLKID_CTS_ENCL]		= &amp;g12a_cts_encl.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC]		= &amp;g12a_cts_vdac.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX]			= &amp;g12a_hdmi_tx.hw,</div><div class='ctx'> 	[CLKID_HDMI_SEL]		= &amp;g12a_hdmi_sel.hw,</div><div class='hunk'>@@ -4632,10 +4729,12 @@ static struct clk_hw *g12b_hw_clks[] = {</div><div class='ctx'> 	[CLKID_VCLK2_DIV12]		= &amp;g12a_vclk2_div12.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI_SEL]		= &amp;g12a_cts_enci_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP_SEL]		= &amp;g12a_cts_encp_sel.hw,</div><div class='add'>+	[CLKID_CTS_ENCL_SEL]		= &amp;g12a_cts_encl_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC_SEL]		= &amp;g12a_cts_vdac_sel.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX_SEL]		= &amp;g12a_hdmi_tx_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI]		= &amp;g12a_cts_enci.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP]		= &amp;g12a_cts_encp.hw,</div><div class='add'>+	[CLKID_CTS_ENCL]		= &amp;g12a_cts_encl.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC]		= &amp;g12a_cts_vdac.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX]			= &amp;g12a_hdmi_tx.hw,</div><div class='ctx'> 	[CLKID_HDMI_SEL]		= &amp;g12a_hdmi_sel.hw,</div><div class='hunk'>@@ -4729,6 +4828,12 @@ static struct clk_hw *g12b_hw_clks[] = {</div><div class='ctx'> 	[CLKID_MIPI_DSI_PXCLK_SEL]	= &amp;g12a_mipi_dsi_pxclk_sel.hw,</div><div class='ctx'> 	[CLKID_MIPI_DSI_PXCLK_DIV]	= &amp;g12a_mipi_dsi_pxclk_div.hw,</div><div class='ctx'> 	[CLKID_MIPI_DSI_PXCLK]		= &amp;g12a_mipi_dsi_pxclk.hw,</div><div class='add'>+	[CLKID_MIPI_ISP_SEL]		= &amp;g12b_mipi_isp_sel.hw,</div><div class='add'>+	[CLKID_MIPI_ISP_DIV]		= &amp;g12b_mipi_isp_div.hw,</div><div class='add'>+	[CLKID_MIPI_ISP]		= &amp;g12b_mipi_isp.hw,</div><div class='add'>+	[CLKID_MIPI_ISP_GATE]		= &amp;g12b_mipi_isp_gate.hw,</div><div class='add'>+	[CLKID_MIPI_ISP_CSI_PHY0]	= &amp;g12b_csi_phy0.hw,</div><div class='add'>+	[CLKID_MIPI_ISP_CSI_PHY1]	= &amp;g12b_csi_phy1.hw,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_hw *sm1_hw_clks[] = {</div><div class='hunk'>@@ -4892,10 +4997,12 @@ static struct clk_hw *sm1_hw_clks[] = {</div><div class='ctx'> 	[CLKID_VCLK2_DIV12]		= &amp;g12a_vclk2_div12.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI_SEL]		= &amp;g12a_cts_enci_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP_SEL]		= &amp;g12a_cts_encp_sel.hw,</div><div class='add'>+	[CLKID_CTS_ENCL_SEL]		= &amp;g12a_cts_encl_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC_SEL]		= &amp;g12a_cts_vdac_sel.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX_SEL]		= &amp;g12a_hdmi_tx_sel.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCI]		= &amp;g12a_cts_enci.hw,</div><div class='ctx'> 	[CLKID_CTS_ENCP]		= &amp;g12a_cts_encp.hw,</div><div class='add'>+	[CLKID_CTS_ENCL]		= &amp;g12a_cts_encl.hw,</div><div class='ctx'> 	[CLKID_CTS_VDAC]		= &amp;g12a_cts_vdac.hw,</div><div class='ctx'> 	[CLKID_HDMI_TX]			= &amp;g12a_hdmi_tx.hw,</div><div class='ctx'> 	[CLKID_HDMI_SEL]		= &amp;g12a_hdmi_sel.hw,</div><div class='hunk'>@@ -5123,10 +5230,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {</div><div class='ctx'> 	&amp;g12a_vclk2_div12_en,</div><div class='ctx'> 	&amp;g12a_cts_enci_sel,</div><div class='ctx'> 	&amp;g12a_cts_encp_sel,</div><div class='add'>+	&amp;g12a_cts_encl_sel,</div><div class='ctx'> 	&amp;g12a_cts_vdac_sel,</div><div class='ctx'> 	&amp;g12a_hdmi_tx_sel,</div><div class='ctx'> 	&amp;g12a_cts_enci,</div><div class='ctx'> 	&amp;g12a_cts_encp,</div><div class='add'>+	&amp;g12a_cts_encl,</div><div class='ctx'> 	&amp;g12a_cts_vdac,</div><div class='ctx'> 	&amp;g12a_hdmi_tx,</div><div class='ctx'> 	&amp;g12a_hdmi_sel,</div><div class='hunk'>@@ -5221,6 +5330,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {</div><div class='ctx'> 	&amp;g12a_mipi_dsi_pxclk_sel,</div><div class='ctx'> 	&amp;g12a_mipi_dsi_pxclk_div,</div><div class='ctx'> 	&amp;g12a_mipi_dsi_pxclk,</div><div class='add'>+	&amp;g12b_mipi_isp_sel,</div><div class='add'>+	&amp;g12b_mipi_isp_div,</div><div class='add'>+	&amp;g12b_mipi_isp,</div><div class='add'>+	&amp;g12b_mipi_isp_gate,</div><div class='add'>+	&amp;g12b_csi_phy1,</div><div class='add'>+	&amp;g12b_csi_phy0,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct reg_sequence g12a_init_regs[] = {</div><div class='head'>diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h<br/>index f11ee3c59849..27df99c4565a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/meson/g12a.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/meson/g12a.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/meson/g12a.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/meson/g12a.h</a></div><div class='hunk'>@@ -70,6 +70,7 @@</div><div class='ctx'> #define HHI_MALI_CLK_CNTL		0x1b0</div><div class='ctx'> #define HHI_VPU_CLKC_CNTL		0x1b4</div><div class='ctx'> #define HHI_VPU_CLK_CNTL		0x1bC</div><div class='add'>+#define HHI_ISP_CLK_CNTL		0x1C0</div><div class='ctx'> #define HHI_NNA_CLK_CNTL		0x1C8</div><div class='ctx'> #define HHI_HDMI_CLK_CNTL		0x1CC</div><div class='ctx'> #define HHI_VDEC_CLK_CNTL		0x1E0</div><div class='head'>diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c<br/>index bce61c45e967..3a3ea2d142f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/microchip/clk-mpfs-ccc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/microchip/clk-mpfs-ccc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/microchip/clk-mpfs-ccc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/microchip/clk-mpfs-ccc.c</a></div><div class='hunk'>@@ -4,8 +4,8 @@</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries</div><div class='ctx'>  */</div><div class='del'>-#include "asm-generic/errno-base.h"</div><div class='ctx'> #include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='head'>diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c<br/>index fb0df64cf053..c5a7ba1deaa3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/mmp/clk-of-pxa168.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/mmp/clk-of-pxa168.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/mmp/clk-of-pxa168.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/mmp/clk-of-pxa168.c</a></div><div class='hunk'>@@ -308,18 +308,21 @@ static void __init pxa168_clk_init(struct device_node *np)</div><div class='ctx'> 	pxa_unit-&gt;mpmu_base = of_iomap(np, 0);</div><div class='ctx'> 	if (!pxa_unit-&gt;mpmu_base) {</div><div class='ctx'> 		pr_err("failed to map mpmu registers\n");</div><div class='add'>+		kfree(pxa_unit);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pxa_unit-&gt;apmu_base = of_iomap(np, 1);</div><div class='ctx'> 	if (!pxa_unit-&gt;apmu_base) {</div><div class='ctx'> 		pr_err("failed to map apmu registers\n");</div><div class='add'>+		kfree(pxa_unit);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pxa_unit-&gt;apbc_base = of_iomap(np, 2);</div><div class='ctx'> 	if (!pxa_unit-&gt;apbc_base) {</div><div class='ctx'> 		pr_err("failed to map apbc registers\n");</div><div class='add'>+		kfree(pxa_unit);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig<br/>index ad1acd9b7426..2a9da0939377 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/Kconfig</a></div><div class='hunk'>@@ -20,6 +20,16 @@ menuconfig COMMON_CLK_QCOM</div><div class='ctx'> </div><div class='ctx'> if COMMON_CLK_QCOM</div><div class='ctx'> </div><div class='add'>+config CLK_X1E80100_GCC</div><div class='add'>+	tristate "X1E80100 Global Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='add'>+	select QCOM_GDSC</div><div class='add'>+	help</div><div class='add'>+	  Support for the global clock controller on Qualcomm Technologies, Inc</div><div class='add'>+	  X1E80100 devices.</div><div class='add'>+	  Say Y if you want to use peripheral devices such as UART, SPI, I2C,</div><div class='add'>+	  USB, UFS, SD/eMMC, PCIe, etc.</div><div class='add'>+</div><div class='ctx'> config QCOM_A53PLL</div><div class='ctx'> 	tristate "MSM8916 A53 PLL"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -427,6 +437,15 @@ config SC_CAMCC_7280</div><div class='ctx'> 	  Say Y if you want to support camera devices and functionality such as</div><div class='ctx'> 	  capturing pictures.</div><div class='ctx'> </div><div class='add'>+config SC_CAMCC_8280XP</div><div class='add'>+	tristate "SC8280XP Camera Clock Controller"</div><div class='add'>+	select SC_GCC_8280XP</div><div class='add'>+	help</div><div class='add'>+	  Support for the camera clock controller on Qualcomm Technologies, Inc</div><div class='add'>+	  SC8280XP devices.</div><div class='add'>+	  Say Y if you want to support camera devices and functionality such as</div><div class='add'>+	  capturing pictures.</div><div class='add'>+</div><div class='ctx'> config SC_DISPCC_7180</div><div class='ctx'> 	tristate "SC7180 Display Clock Controller"</div><div class='ctx'> 	depends on ARM64 || COMPILE_TEST</div><div class='hunk'>@@ -668,6 +687,15 @@ config QDU_GCC_1000</div><div class='ctx'> 	  QRU1000 devices. Say Y if you want to use peripheral</div><div class='ctx'> 	  devices such as UART, SPI, I2C, USB, SD, PCIe, etc.</div><div class='ctx'> </div><div class='add'>+config QDU_ECPRICC_1000</div><div class='add'>+	tristate "QDU1000/QRU1000 ECPRI Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='add'>+	select QDU_GCC_1000</div><div class='add'>+	help</div><div class='add'>+	  Support for the ECPRI clock controller on QDU1000 and</div><div class='add'>+	  QRU1000 devices. Say Y if you want to support the ECPRI</div><div class='add'>+	  clock controller functionality such as Ethernet.</div><div class='add'>+</div><div class='ctx'> config SDM_GCC_845</div><div class='ctx'> 	tristate "SDM845/SDM670 Global Clock Controller"</div><div class='ctx'> 	depends on ARM64 || COMPILE_TEST</div><div class='hunk'>@@ -767,6 +795,7 @@ config SM_CAMCC_8450</div><div class='ctx'> </div><div class='ctx'> config SM_CAMCC_8550</div><div class='ctx'> 	tristate "SM8550 Camera Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='ctx'> 	select SM_GCC_8550</div><div class='ctx'> 	help</div><div class='ctx'> 	  Support for the camera clock controller on SM8550 devices.</div><div class='hunk'>@@ -842,6 +871,16 @@ config SM_DISPCC_8550</div><div class='ctx'> 	  Say Y if you want to support display devices and functionality such as</div><div class='ctx'> 	  splash screen.</div><div class='ctx'> </div><div class='add'>+config SM_DISPCC_8650</div><div class='add'>+	tristate "SM8650 Display Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='add'>+	select SM_GCC_8650</div><div class='add'>+	help</div><div class='add'>+	  Support for the display clock controller on Qualcomm Technologies, Inc</div><div class='add'>+	  SM8650 devices.</div><div class='add'>+	  Say Y if you want to support display devices and functionality such as</div><div class='add'>+	  splash screen.</div><div class='add'>+</div><div class='ctx'> config SM_GCC_4450</div><div class='ctx'> 	tristate "SM4450 Global Clock Controller"</div><div class='ctx'> 	depends on ARM64 || COMPILE_TEST</div><div class='hunk'>@@ -938,6 +977,15 @@ config SM_GCC_8550</div><div class='ctx'> 	  Say Y if you want to use peripheral devices such as UART,</div><div class='ctx'> 	  SPI, I2C, USB, SD/UFS, PCIe etc.</div><div class='ctx'> </div><div class='add'>+config SM_GCC_8650</div><div class='add'>+	tristate "SM8650 Global Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='add'>+	select QCOM_GDSC</div><div class='add'>+	help</div><div class='add'>+	  Support for the global clock controller on SM8650 devices.</div><div class='add'>+	  Say Y if you want to use peripheral devices such as UART,</div><div class='add'>+	  SPI, I2C, USB, SD/UFS, PCIe etc.</div><div class='add'>+</div><div class='ctx'> config SM_GPUCC_6115</div><div class='ctx'> 	tristate "SM6115 Graphics Clock Controller"</div><div class='ctx'> 	select SM_GCC_6115</div><div class='hunk'>@@ -1019,6 +1067,14 @@ config SM_GPUCC_8550</div><div class='ctx'> 	  Say Y if you want to support graphics controller devices and</div><div class='ctx'> 	  functionality such as 3D graphics.</div><div class='ctx'> </div><div class='add'>+config SM_GPUCC_8650</div><div class='add'>+	tristate "SM8650 Graphics Clock Controller"</div><div class='add'>+	select SM_GCC_8650</div><div class='add'>+	help</div><div class='add'>+	  Support for the graphics clock controller on SM8650 devices.</div><div class='add'>+	  Say Y if you want to support graphics controller devices and</div><div class='add'>+	  functionality such as 3D graphics.</div><div class='add'>+</div><div class='ctx'> config SM_TCSRCC_8550</div><div class='ctx'> 	tristate "SM8550 TCSR Clock Controller"</div><div class='ctx'> 	depends on ARM64 || COMPILE_TEST</div><div class='hunk'>@@ -1027,6 +1083,14 @@ config SM_TCSRCC_8550</div><div class='ctx'> 	  Support for the TCSR clock controller on SM8550 devices.</div><div class='ctx'> 	  Say Y if you want to use peripheral devices such as SD/UFS.</div><div class='ctx'> </div><div class='add'>+config SM_TCSRCC_8650</div><div class='add'>+	tristate "SM8650 TCSR Clock Controller"</div><div class='add'>+	depends on ARM64 || COMPILE_TEST</div><div class='add'>+	select QCOM_GDSC</div><div class='add'>+	help</div><div class='add'>+	  Support for the TCSR clock controller on SM8650 devices.</div><div class='add'>+	  Say Y if you want to use peripheral devices such as SD/UFS.</div><div class='add'>+</div><div class='ctx'> config SM_VIDEOCC_8150</div><div class='ctx'> 	tristate "SM8150 Video Clock Controller"</div><div class='ctx'> 	depends on ARM64 || COMPILE_TEST</div><div class='head'>diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile<br/>index 17edd73f9839..582e06dc1d93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/Makefile</a></div><div class='hunk'>@@ -21,6 +21,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o</div><div class='ctx'> obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o</div><div class='ctx'> obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o</div><div class='ctx'> obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o</div><div class='add'>+obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o</div><div class='ctx'> obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o</div><div class='ctx'> obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o</div><div class='ctx'> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o</div><div class='hunk'>@@ -65,9 +66,11 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o</div><div class='ctx'> obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o</div><div class='ctx'> obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o</div><div class='ctx'> obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o</div><div class='add'>+obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o</div><div class='ctx'> obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o</div><div class='ctx'> obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o</div><div class='ctx'> obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o</div><div class='add'>+obj-$(CONFIG_SC_CAMCC_8280XP) += camcc-sc8280xp.o</div><div class='ctx'> obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o</div><div class='ctx'> obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o</div><div class='ctx'> obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o</div><div class='hunk'>@@ -110,6 +113,7 @@ obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o</div><div class='ctx'> obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o</div><div class='ctx'> obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o</div><div class='ctx'> obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o</div><div class='add'>+obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o</div><div class='hunk'>@@ -121,6 +125,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o</div><div class='ctx'> obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o</div><div class='add'>+obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o</div><div class='hunk'>@@ -130,7 +135,9 @@ obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_8450) += gpucc-sm8450.o</div><div class='ctx'> obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o</div><div class='add'>+obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o</div><div class='ctx'> obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o</div><div class='add'>+obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o</div><div class='ctx'> obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o</div><div class='ctx'> obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o</div><div class='ctx'> obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o</div><div class='head'>diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c<br/>index 41279e5437a6..678b805f13d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/apss-ipq-pll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/apss-ipq-pll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/apss-ipq-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/apss-ipq-pll.c</a></div><div class='hunk'>@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct alpha_pll_config ipq5018_pll_config = {</div><div class='add'>+	.l = 0x32,</div><div class='add'>+	.config_ctl_val = 0x4001075b,</div><div class='add'>+	.config_ctl_hi_val = 0x304,</div><div class='add'>+	.main_output_mask = BIT(0),</div><div class='add'>+	.aux_output_mask = BIT(1),</div><div class='add'>+	.early_output_mask = BIT(3),</div><div class='add'>+	.alpha_en_mask = BIT(24),</div><div class='add'>+	.status_val = 0x3,</div><div class='add'>+	.status_mask = GENMASK(10, 8),</div><div class='add'>+	.lock_det = BIT(2),</div><div class='add'>+	.test_ctl_hi_val = 0x00400003,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct alpha_pll_config ipq5332_pll_config = {</div><div class='ctx'> 	.l = 0x2d,</div><div class='ctx'> 	.config_ctl_val = 0x4001075b,</div><div class='hunk'>@@ -129,6 +143,12 @@ struct apss_pll_data {</div><div class='ctx'> 	const struct alpha_pll_config *pll_config;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct apss_pll_data ipq5018_pll_data = {</div><div class='add'>+	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,</div><div class='add'>+	.pll = &amp;ipq_pll_stromer_plus,</div><div class='add'>+	.pll_config = &amp;ipq5018_pll_config,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct apss_pll_data ipq5332_pll_data = {</div><div class='ctx'> 	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,</div><div class='ctx'> 	.pll = &amp;ipq_pll_stromer_plus,</div><div class='hunk'>@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id apss_ipq_pll_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,ipq5018-a53pll", .data = &amp;ipq5018_pll_data },</div><div class='ctx'> 	{ .compatible = "qcom,ipq5332-a53pll", .data = &amp;ipq5332_pll_data },</div><div class='ctx'> 	{ .compatible = "qcom,ipq6018-a53pll", .data = &amp;ipq6018_pll_data },</div><div class='ctx'> 	{ .compatible = "qcom,ipq8074-a53pll", .data = &amp;ipq8074_pll_data },</div><div class='head'>diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c<br/>new file mode 100644<br/>index 000000000000..3dcd79b01515<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/camcc-sc8280xp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/camcc-sc8280xp.c</a></div><div class='hunk'>@@ -0,0 +1,3045 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sc8280xp-camcc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "common.h"</div><div class='add'>+#include "gdsc.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	DT_IFACE,</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_BI_TCXO_AO,</div><div class='add'>+	DT_SLEEP_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_CAMCC_PLL0_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL0_OUT_MAIN,</div><div class='add'>+	P_CAMCC_PLL0_OUT_ODD,</div><div class='add'>+	P_CAMCC_PLL1_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL2_OUT_AUX,</div><div class='add'>+	P_CAMCC_PLL2_OUT_EARLY,</div><div class='add'>+	P_CAMCC_PLL3_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL4_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL5_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL6_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL7_OUT_EVEN,</div><div class='add'>+	P_CAMCC_PLL7_OUT_ODD,</div><div class='add'>+	P_SLEEP_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct pll_vco lucid_vco[] = {</div><div class='add'>+	{ 249600000, 1800000000, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct pll_vco zonda_vco[] = {</div><div class='add'>+	{ 595200000, 3600000000, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll0_config = {</div><div class='add'>+	.l = 0x3e,</div><div class='add'>+	.alpha = 0x8000,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00003100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll0_out_even = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll0_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll0_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll0.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll0_out_odd[] = {</div><div class='add'>+	{ 0x3, 3 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll0_out_odd = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.post_div_shift = 12,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll0_out_odd,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_odd),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll0_out_odd",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll0.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll1_config = {</div><div class='add'>+	.l = 0x21,</div><div class='add'>+	.alpha = 0x5555,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00000100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll1 = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll1",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll1_out_even = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll1_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll1_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll1.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll2_config = {</div><div class='add'>+	.l = 0x32,</div><div class='add'>+	.alpha = 0x0,</div><div class='add'>+	.config_ctl_val = 0x08200800,</div><div class='add'>+	.config_ctl_hi_val = 0x05028011,</div><div class='add'>+	.config_ctl_hi1_val = 0x08000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll2 = {</div><div class='add'>+	.offset = 0x2000,</div><div class='add'>+	.vco_table = zonda_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(zonda_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll2",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_zonda_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll3_config = {</div><div class='add'>+	.l = 0x29,</div><div class='add'>+	.alpha = 0xaaaa,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00000100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll3 = {</div><div class='add'>+	.offset = 0x3000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll3",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll3_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll3_out_even = {</div><div class='add'>+	.offset = 0x3000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll3_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll3_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll3_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll3.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll4_config = {</div><div class='add'>+	.l = 0x29,</div><div class='add'>+	.alpha = 0xaaaa,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00000100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll4 = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll4",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll4_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll4_out_even = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll4_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll4_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll4_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll4.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll5_config = {</div><div class='add'>+	.l = 0x29,</div><div class='add'>+	.alpha = 0xaaaa,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00000100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll5 = {</div><div class='add'>+	.offset = 0x10000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll5",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll5_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll5_out_even = {</div><div class='add'>+	.offset = 0x10000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll5_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll5_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll5_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll5.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll6_config = {</div><div class='add'>+	.l = 0x29,</div><div class='add'>+	.alpha = 0xaaaa,</div><div class='add'>+	.config_ctl_val = 0x20486699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00000100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll6 = {</div><div class='add'>+	.offset = 0x11000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll6",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll6_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll6_out_even = {</div><div class='add'>+	.offset = 0x11000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll6_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll6_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll6_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll6.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct alpha_pll_config camcc_pll7_config = {</div><div class='add'>+	.l = 0x32,</div><div class='add'>+	.alpha = 0x0,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00002261,</div><div class='add'>+	.config_ctl_hi1_val = 0x2a9a699c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x01800000,</div><div class='add'>+	.user_ctl_val = 0x00003100,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+	.user_ctl_hi1_val = 0x00000000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll camcc_pll7 = {</div><div class='add'>+	.offset = 0x12000,</div><div class='add'>+	.vco_table = lucid_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_pll7",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_5lpe_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll7_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll7_out_even = {</div><div class='add'>+	.offset = 0x12000,</div><div class='add'>+	.post_div_shift = 8,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll7_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll7_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll7.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_camcc_pll7_out_odd[] = {</div><div class='add'>+	{ 0x3, 3 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv camcc_pll7_out_odd = {</div><div class='add'>+	.offset = 0x12000,</div><div class='add'>+	.post_div_shift = 12,</div><div class='add'>+	.post_div_table = post_div_table_camcc_pll7_out_odd,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_odd),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_pll7_out_odd",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;camcc_pll7.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_EVEN, 2 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_ODD, 3 },</div><div class='add'>+	{ P_CAMCC_PLL7_OUT_EVEN, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_even.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_odd.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll7_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL2_OUT_AUX, 2 },</div><div class='add'>+	{ P_CAMCC_PLL2_OUT_EARLY, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll2.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll2.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_EVEN, 2 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_ODD, 3 },</div><div class='add'>+	{ P_CAMCC_PLL7_OUT_ODD, 4 },</div><div class='add'>+	{ P_CAMCC_PLL7_OUT_EVEN, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_even.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_odd.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll7_out_odd.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll7_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_3[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_EVEN, 2 },</div><div class='add'>+	{ P_CAMCC_PLL0_OUT_ODD, 3 },</div><div class='add'>+	{ P_CAMCC_PLL7_OUT_EVEN, 5 },</div><div class='add'>+	{ P_CAMCC_PLL3_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_3[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_even.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll0_out_odd.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll7_out_even.clkr.hw },</div><div class='add'>+	{ .hw = &amp;camcc_pll3_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_4[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL3_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_4[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll3_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_5[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL4_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_5[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll4_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_6[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL5_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_6[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll5_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_7[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL6_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_7[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll6_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_8[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_CAMCC_PLL1_OUT_EVEN, 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_8[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;camcc_pll1_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_9[] = {</div><div class='add'>+	{ P_SLEEP_CLK, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_9[] = {</div><div class='add'>+	{ .fw_name = "sleep_clk" },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map camcc_parent_map_10[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data camcc_parent_data_10_ao[] = {</div><div class='add'>+	{ .fw_name = "bi_tcxo_ao" },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_bps_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x7010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_camcc_bps_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_bps_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0),</div><div class='add'>+	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_camnoc_axi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc170,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_camnoc_axi_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_camnoc_axi_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_cci_0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc108,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_cci_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_cci_0_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_cci_1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc124,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_cci_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_cci_1_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_cci_2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc204,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_cci_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_cci_2_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_cci_3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc220,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_cci_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_cci_3_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_cphy_rx_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa064,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_cphy_rx_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_cphy_rx_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_csi0phytimer_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6004,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_csi0phytimer_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_csi1phytimer_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6028,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_csi1phytimer_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_csi2phytimer_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x604c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_csi2phytimer_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_csi3phytimer_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6074,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_csi3phytimer_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),</div><div class='add'>+	F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_fast_ahb_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x703c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_fast_ahb_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_fast_ahb_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_icp_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc0b8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_icp_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_icp_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_0_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_0_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa03c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_0_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xb010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_1_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_1_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xb03c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_1_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_2_clk_src[] = {</div><div class='add'>+	F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xf010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_6,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_2_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_6,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_6),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_2_csid_clk_src[] = {</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_2_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xf03c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_2_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_3_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xf07c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_7,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_3_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_7,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_7),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_3_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xf0a8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_3_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ife_lite_0_clk_src[] = {</div><div class='add'>+	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc004,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_0_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_0_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc020,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_0_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc048,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_1_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_1_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc064,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_1_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc240,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_2_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_2_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc25c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_2_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc284,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_3_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ife_lite_3_csid_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc2a0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ife_lite_3_csid_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_ipe_0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_8,</div><div class='add'>+	.freq_tbl = ftbl_camcc_ipe_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_ipe_0_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_8,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_8),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_jpeg_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc08c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_jpeg_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_jpeg_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {</div><div class='add'>+	F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0),</div><div class='add'>+	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),</div><div class='add'>+	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),</div><div class='add'>+	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_lrme_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc144,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_camcc_lrme_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_lrme_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),</div><div class='add'>+	F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5004,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk0_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5024,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk1_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5044,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk2_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5064,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk3_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5084,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk4_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x50a4,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk5_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x50c4,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk6_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_mclk7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x50e4,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_camcc_mclk0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_mclk7_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {</div><div class='add'>+	F(32000, P_SLEEP_CLK, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_sleep_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc1e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_9,</div><div class='add'>+	.freq_tbl = ftbl_camcc_sleep_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_sleep_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_9,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_9),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_slow_ahb_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x7058,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_camcc_slow_ahb_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_slow_ahb_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 camcc_xo_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xc1cc,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = camcc_parent_map_10,</div><div class='add'>+	.freq_tbl = ftbl_camcc_xo_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "camcc_xo_clk_src",</div><div class='add'>+		.parent_data = camcc_parent_data_10_ao,</div><div class='add'>+		.num_parents = ARRAY_SIZE(camcc_parent_data_10_ao),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_bps_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x7070,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7070,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_bps_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_bps_areg_clk = {</div><div class='add'>+	.halt_reg = 0x7054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_bps_areg_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_fast_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_bps_axi_clk = {</div><div class='add'>+	.halt_reg = 0x7038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_bps_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_bps_clk = {</div><div class='add'>+	.halt_reg = 0x7028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_bps_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_bps_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_camnoc_axi_clk = {</div><div class='add'>+	.halt_reg = 0xc18c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc18c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_camnoc_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_camnoc_dcd_xo_clk = {</div><div class='add'>+	.halt_reg = 0xc194,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc194,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_camnoc_dcd_xo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_xo_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_cci_0_clk = {</div><div class='add'>+	.halt_reg = 0xc120,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc120,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_cci_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cci_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_cci_1_clk = {</div><div class='add'>+	.halt_reg = 0xc13c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc13c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_cci_1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cci_1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_cci_2_clk = {</div><div class='add'>+	.halt_reg = 0xc21c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc21c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_cci_2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cci_2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_cci_3_clk = {</div><div class='add'>+	.halt_reg = 0xc238,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc238,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_cci_3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cci_3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_core_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xc1c8,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc1c8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_core_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_cpas_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xc168,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc168,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_cpas_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csi0phytimer_clk = {</div><div class='add'>+	.halt_reg = 0x601c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x601c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csi0phytimer_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_csi0phytimer_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csi1phytimer_clk = {</div><div class='add'>+	.halt_reg = 0x6040,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csi1phytimer_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_csi1phytimer_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csi2phytimer_clk = {</div><div class='add'>+	.halt_reg = 0x6064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csi2phytimer_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_csi2phytimer_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csi3phytimer_clk = {</div><div class='add'>+	.halt_reg = 0x608c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x608c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csi3phytimer_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_csi3phytimer_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csiphy0_clk = {</div><div class='add'>+	.halt_reg = 0x6020,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csiphy0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csiphy1_clk = {</div><div class='add'>+	.halt_reg = 0x6044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csiphy1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csiphy2_clk = {</div><div class='add'>+	.halt_reg = 0x6068,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csiphy2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_csiphy3_clk = {</div><div class='add'>+	.halt_reg = 0x6090,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x6090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_csiphy3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_gdsc_clk = {</div><div class='add'>+	.halt_reg = 0xc1e4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc1e4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_gdsc_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_xo_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_icp_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xc0d8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc0d8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_icp_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_icp_clk = {</div><div class='add'>+	.halt_reg = 0xc0d0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc0d0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_icp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_icp_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_0_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa080,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa080,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_0_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_0_clk = {</div><div class='add'>+	.halt_reg = 0xa028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_0_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xa07c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa07c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_0_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_0_csid_clk = {</div><div class='add'>+	.halt_reg = 0xa054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_0_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_0_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_0_dsp_clk = {</div><div class='add'>+	.halt_reg = 0xa038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_0_dsp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_1_axi_clk = {</div><div class='add'>+	.halt_reg = 0xb068,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xb068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_1_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_1_clk = {</div><div class='add'>+	.halt_reg = 0xb028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xb028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_1_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xb064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xb064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_1_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_1_csid_clk = {</div><div class='add'>+	.halt_reg = 0xb054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xb054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_1_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_1_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_1_dsp_clk = {</div><div class='add'>+	.halt_reg = 0xb038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xb038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_1_dsp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_2_axi_clk = {</div><div class='add'>+	.halt_reg = 0xf068,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_2_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_2_clk = {</div><div class='add'>+	.halt_reg = 0xf028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_2_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xf064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_2_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_2_csid_clk = {</div><div class='add'>+	.halt_reg = 0xf054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_2_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_2_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_2_dsp_clk = {</div><div class='add'>+	.halt_reg = 0xf038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_2_dsp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_3_axi_clk = {</div><div class='add'>+	.halt_reg = 0xf0d4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf0d4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_3_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_3_clk = {</div><div class='add'>+	.halt_reg = 0xf094,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf094,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_3_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xf0d0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf0d0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_3_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_3_csid_clk = {</div><div class='add'>+	.halt_reg = 0xf0c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf0c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_3_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_3_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_3_dsp_clk = {</div><div class='add'>+	.halt_reg = 0xf0a4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf0a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_3_dsp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_0_clk = {</div><div class='add'>+	.halt_reg = 0xc01c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc01c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_0_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xc040,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_0_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_0_csid_clk = {</div><div class='add'>+	.halt_reg = 0xc038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_0_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_0_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_1_clk = {</div><div class='add'>+	.halt_reg = 0xc060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_1_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xc084,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc084,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_1_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_1_csid_clk = {</div><div class='add'>+	.halt_reg = 0xc07c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc07c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_1_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_1_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_2_clk = {</div><div class='add'>+	.halt_reg = 0xc258,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc258,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_2_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xc27c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc27c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_2_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_2_csid_clk = {</div><div class='add'>+	.halt_reg = 0xc274,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc274,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_2_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_2_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_3_clk = {</div><div class='add'>+	.halt_reg = 0xc29c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc29c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_3_cphy_rx_clk = {</div><div class='add'>+	.halt_reg = 0xc2c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc2c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_3_cphy_rx_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_cphy_rx_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ife_lite_3_csid_clk = {</div><div class='add'>+	.halt_reg = 0xc2b8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc2b8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ife_lite_3_csid_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ife_lite_3_csid_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_0_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x8040,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_0_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_0_areg_clk = {</div><div class='add'>+	.halt_reg = 0x803c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x803c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_0_areg_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_fast_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_0_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_0_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_0_clk = {</div><div class='add'>+	.halt_reg = 0x8028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ipe_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_1_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x9028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_1_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_slow_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_1_areg_clk = {</div><div class='add'>+	.halt_reg = 0x9024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_1_areg_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_fast_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_1_axi_clk = {</div><div class='add'>+	.halt_reg = 0x9020,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_1_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_camnoc_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_ipe_1_clk = {</div><div class='add'>+	.halt_reg = 0x9010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_ipe_1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_ipe_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_jpeg_clk = {</div><div class='add'>+	.halt_reg = 0xc0a4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc0a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_jpeg_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_jpeg_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_lrme_clk = {</div><div class='add'>+	.halt_reg = 0xc15c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc15c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_lrme_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_lrme_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk0_clk = {</div><div class='add'>+	.halt_reg = 0x501c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x501c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk1_clk = {</div><div class='add'>+	.halt_reg = 0x503c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x503c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk2_clk = {</div><div class='add'>+	.halt_reg = 0x505c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x505c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk3_clk = {</div><div class='add'>+	.halt_reg = 0x507c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x507c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk4_clk = {</div><div class='add'>+	.halt_reg = 0x509c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x509c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk5_clk = {</div><div class='add'>+	.halt_reg = 0x50bc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x50bc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk6_clk = {</div><div class='add'>+	.halt_reg = 0x50dc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x50dc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_mclk7_clk = {</div><div class='add'>+	.halt_reg = 0x50fc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x50fc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_mclk7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_mclk7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch camcc_sleep_clk = {</div><div class='add'>+	.halt_reg = 0xc200,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc200,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "camcc_sleep_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camcc_sleep_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc titan_top_gdsc;</div><div class='add'>+</div><div class='add'>+static struct gdsc bps_gdsc = {</div><div class='add'>+	.gdscr = 0x7004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "bps_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = HW_CTRL | RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ife_0_gdsc = {</div><div class='add'>+	.gdscr = 0xa004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ife_0_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ife_1_gdsc = {</div><div class='add'>+	.gdscr = 0xb004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ife_1_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ife_2_gdsc = {</div><div class='add'>+	.gdscr = 0xf004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ife_2_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ife_3_gdsc = {</div><div class='add'>+	.gdscr = 0xf070,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ife_3_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ipe_0_gdsc = {</div><div class='add'>+	.gdscr = 0x8004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ipe_0_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = HW_CTRL | RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ipe_1_gdsc = {</div><div class='add'>+	.gdscr = 0x9004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ipe_1_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = HW_CTRL | RETAIN_FF_ENABLE,</div><div class='add'>+	.parent = &amp;titan_top_gdsc.pd,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc titan_top_gdsc = {</div><div class='add'>+	.gdscr = 0xc1bc,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "titan_top_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.flags = RETAIN_FF_ENABLE,</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *camcc_sc8280xp_clocks[] = {</div><div class='add'>+	[CAMCC_BPS_AHB_CLK] = &amp;camcc_bps_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_BPS_AREG_CLK] = &amp;camcc_bps_areg_clk.clkr,</div><div class='add'>+	[CAMCC_BPS_AXI_CLK] = &amp;camcc_bps_axi_clk.clkr,</div><div class='add'>+	[CAMCC_BPS_CLK] = &amp;camcc_bps_clk.clkr,</div><div class='add'>+	[CAMCC_BPS_CLK_SRC] = &amp;camcc_bps_clk_src.clkr,</div><div class='add'>+	[CAMCC_CAMNOC_AXI_CLK] = &amp;camcc_camnoc_axi_clk.clkr,</div><div class='add'>+	[CAMCC_CAMNOC_AXI_CLK_SRC] = &amp;camcc_camnoc_axi_clk_src.clkr,</div><div class='add'>+	[CAMCC_CAMNOC_DCD_XO_CLK] = &amp;camcc_camnoc_dcd_xo_clk.clkr,</div><div class='add'>+	[CAMCC_CCI_0_CLK] = &amp;camcc_cci_0_clk.clkr,</div><div class='add'>+	[CAMCC_CCI_0_CLK_SRC] = &amp;camcc_cci_0_clk_src.clkr,</div><div class='add'>+	[CAMCC_CCI_1_CLK] = &amp;camcc_cci_1_clk.clkr,</div><div class='add'>+	[CAMCC_CCI_1_CLK_SRC] = &amp;camcc_cci_1_clk_src.clkr,</div><div class='add'>+	[CAMCC_CCI_2_CLK] = &amp;camcc_cci_2_clk.clkr,</div><div class='add'>+	[CAMCC_CCI_2_CLK_SRC] = &amp;camcc_cci_2_clk_src.clkr,</div><div class='add'>+	[CAMCC_CCI_3_CLK] = &amp;camcc_cci_3_clk.clkr,</div><div class='add'>+	[CAMCC_CCI_3_CLK_SRC] = &amp;camcc_cci_3_clk_src.clkr,</div><div class='add'>+	[CAMCC_CORE_AHB_CLK] = &amp;camcc_core_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_CPAS_AHB_CLK] = &amp;camcc_cpas_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_CPHY_RX_CLK_SRC] = &amp;camcc_cphy_rx_clk_src.clkr,</div><div class='add'>+	[CAMCC_CSI0PHYTIMER_CLK] = &amp;camcc_csi0phytimer_clk.clkr,</div><div class='add'>+	[CAMCC_CSI0PHYTIMER_CLK_SRC] = &amp;camcc_csi0phytimer_clk_src.clkr,</div><div class='add'>+	[CAMCC_CSI1PHYTIMER_CLK] = &amp;camcc_csi1phytimer_clk.clkr,</div><div class='add'>+	[CAMCC_CSI1PHYTIMER_CLK_SRC] = &amp;camcc_csi1phytimer_clk_src.clkr,</div><div class='add'>+	[CAMCC_CSI2PHYTIMER_CLK] = &amp;camcc_csi2phytimer_clk.clkr,</div><div class='add'>+	[CAMCC_CSI2PHYTIMER_CLK_SRC] = &amp;camcc_csi2phytimer_clk_src.clkr,</div><div class='add'>+	[CAMCC_CSI3PHYTIMER_CLK] = &amp;camcc_csi3phytimer_clk.clkr,</div><div class='add'>+	[CAMCC_CSI3PHYTIMER_CLK_SRC] = &amp;camcc_csi3phytimer_clk_src.clkr,</div><div class='add'>+	[CAMCC_CSIPHY0_CLK] = &amp;camcc_csiphy0_clk.clkr,</div><div class='add'>+	[CAMCC_CSIPHY1_CLK] = &amp;camcc_csiphy1_clk.clkr,</div><div class='add'>+	[CAMCC_CSIPHY2_CLK] = &amp;camcc_csiphy2_clk.clkr,</div><div class='add'>+	[CAMCC_CSIPHY3_CLK] = &amp;camcc_csiphy3_clk.clkr,</div><div class='add'>+	[CAMCC_FAST_AHB_CLK_SRC] = &amp;camcc_fast_ahb_clk_src.clkr,</div><div class='add'>+	[CAMCC_GDSC_CLK] = &amp;camcc_gdsc_clk.clkr,</div><div class='add'>+	[CAMCC_ICP_AHB_CLK] = &amp;camcc_icp_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_ICP_CLK] = &amp;camcc_icp_clk.clkr,</div><div class='add'>+	[CAMCC_ICP_CLK_SRC] = &amp;camcc_icp_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_0_AXI_CLK] = &amp;camcc_ife_0_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_0_CLK] = &amp;camcc_ife_0_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_0_CLK_SRC] = &amp;camcc_ife_0_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_0_CPHY_RX_CLK] = &amp;camcc_ife_0_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_0_CSID_CLK] = &amp;camcc_ife_0_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_0_CSID_CLK_SRC] = &amp;camcc_ife_0_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_0_DSP_CLK] = &amp;camcc_ife_0_dsp_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_1_AXI_CLK] = &amp;camcc_ife_1_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_1_CLK] = &amp;camcc_ife_1_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_1_CLK_SRC] = &amp;camcc_ife_1_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_1_CPHY_RX_CLK] = &amp;camcc_ife_1_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_1_CSID_CLK] = &amp;camcc_ife_1_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_1_CSID_CLK_SRC] = &amp;camcc_ife_1_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_1_DSP_CLK] = &amp;camcc_ife_1_dsp_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_2_AXI_CLK] = &amp;camcc_ife_2_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_2_CLK] = &amp;camcc_ife_2_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_2_CLK_SRC] = &amp;camcc_ife_2_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_2_CPHY_RX_CLK] = &amp;camcc_ife_2_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_2_CSID_CLK] = &amp;camcc_ife_2_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_2_CSID_CLK_SRC] = &amp;camcc_ife_2_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_2_DSP_CLK] = &amp;camcc_ife_2_dsp_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_3_AXI_CLK] = &amp;camcc_ife_3_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_3_CLK] = &amp;camcc_ife_3_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_3_CLK_SRC] = &amp;camcc_ife_3_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_3_CPHY_RX_CLK] = &amp;camcc_ife_3_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_3_CSID_CLK] = &amp;camcc_ife_3_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_3_CSID_CLK_SRC] = &amp;camcc_ife_3_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_3_DSP_CLK] = &amp;camcc_ife_3_dsp_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_0_CLK] = &amp;camcc_ife_lite_0_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_0_CLK_SRC] = &amp;camcc_ife_lite_0_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_0_CPHY_RX_CLK] = &amp;camcc_ife_lite_0_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_0_CSID_CLK] = &amp;camcc_ife_lite_0_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_0_CSID_CLK_SRC] = &amp;camcc_ife_lite_0_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_1_CLK] = &amp;camcc_ife_lite_1_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_1_CLK_SRC] = &amp;camcc_ife_lite_1_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_1_CPHY_RX_CLK] = &amp;camcc_ife_lite_1_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_1_CSID_CLK] = &amp;camcc_ife_lite_1_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_1_CSID_CLK_SRC] = &amp;camcc_ife_lite_1_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_2_CLK] = &amp;camcc_ife_lite_2_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_2_CLK_SRC] = &amp;camcc_ife_lite_2_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_2_CPHY_RX_CLK] = &amp;camcc_ife_lite_2_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_2_CSID_CLK] = &amp;camcc_ife_lite_2_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_2_CSID_CLK_SRC] = &amp;camcc_ife_lite_2_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_3_CLK] = &amp;camcc_ife_lite_3_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_3_CLK_SRC] = &amp;camcc_ife_lite_3_clk_src.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_3_CPHY_RX_CLK] = &amp;camcc_ife_lite_3_cphy_rx_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_3_CSID_CLK] = &amp;camcc_ife_lite_3_csid_clk.clkr,</div><div class='add'>+	[CAMCC_IFE_LITE_3_CSID_CLK_SRC] = &amp;camcc_ife_lite_3_csid_clk_src.clkr,</div><div class='add'>+	[CAMCC_IPE_0_AHB_CLK] = &amp;camcc_ipe_0_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_0_AREG_CLK] = &amp;camcc_ipe_0_areg_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_0_AXI_CLK] = &amp;camcc_ipe_0_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_0_CLK] = &amp;camcc_ipe_0_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_0_CLK_SRC] = &amp;camcc_ipe_0_clk_src.clkr,</div><div class='add'>+	[CAMCC_IPE_1_AHB_CLK] = &amp;camcc_ipe_1_ahb_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_1_AREG_CLK] = &amp;camcc_ipe_1_areg_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_1_AXI_CLK] = &amp;camcc_ipe_1_axi_clk.clkr,</div><div class='add'>+	[CAMCC_IPE_1_CLK] = &amp;camcc_ipe_1_clk.clkr,</div><div class='add'>+	[CAMCC_JPEG_CLK] = &amp;camcc_jpeg_clk.clkr,</div><div class='add'>+	[CAMCC_JPEG_CLK_SRC] = &amp;camcc_jpeg_clk_src.clkr,</div><div class='add'>+	[CAMCC_LRME_CLK] = &amp;camcc_lrme_clk.clkr,</div><div class='add'>+	[CAMCC_LRME_CLK_SRC] = &amp;camcc_lrme_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK0_CLK] = &amp;camcc_mclk0_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK0_CLK_SRC] = &amp;camcc_mclk0_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK1_CLK] = &amp;camcc_mclk1_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK1_CLK_SRC] = &amp;camcc_mclk1_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK2_CLK] = &amp;camcc_mclk2_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK2_CLK_SRC] = &amp;camcc_mclk2_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK3_CLK] = &amp;camcc_mclk3_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK3_CLK_SRC] = &amp;camcc_mclk3_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK4_CLK] = &amp;camcc_mclk4_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK4_CLK_SRC] = &amp;camcc_mclk4_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK5_CLK] = &amp;camcc_mclk5_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK5_CLK_SRC] = &amp;camcc_mclk5_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK6_CLK] = &amp;camcc_mclk6_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK6_CLK_SRC] = &amp;camcc_mclk6_clk_src.clkr,</div><div class='add'>+	[CAMCC_MCLK7_CLK] = &amp;camcc_mclk7_clk.clkr,</div><div class='add'>+	[CAMCC_MCLK7_CLK_SRC] = &amp;camcc_mclk7_clk_src.clkr,</div><div class='add'>+	[CAMCC_PLL0] = &amp;camcc_pll0.clkr,</div><div class='add'>+	[CAMCC_PLL0_OUT_EVEN] = &amp;camcc_pll0_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL0_OUT_ODD] = &amp;camcc_pll0_out_odd.clkr,</div><div class='add'>+	[CAMCC_PLL1] = &amp;camcc_pll1.clkr,</div><div class='add'>+	[CAMCC_PLL1_OUT_EVEN] = &amp;camcc_pll1_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL2] = &amp;camcc_pll2.clkr,</div><div class='add'>+	[CAMCC_PLL3] = &amp;camcc_pll3.clkr,</div><div class='add'>+	[CAMCC_PLL3_OUT_EVEN] = &amp;camcc_pll3_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL4] = &amp;camcc_pll4.clkr,</div><div class='add'>+	[CAMCC_PLL4_OUT_EVEN] = &amp;camcc_pll4_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL5] = &amp;camcc_pll5.clkr,</div><div class='add'>+	[CAMCC_PLL5_OUT_EVEN] = &amp;camcc_pll5_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL6] = &amp;camcc_pll6.clkr,</div><div class='add'>+	[CAMCC_PLL6_OUT_EVEN] = &amp;camcc_pll6_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL7] = &amp;camcc_pll7.clkr,</div><div class='add'>+	[CAMCC_PLL7_OUT_EVEN] = &amp;camcc_pll7_out_even.clkr,</div><div class='add'>+	[CAMCC_PLL7_OUT_ODD] = &amp;camcc_pll7_out_odd.clkr,</div><div class='add'>+	[CAMCC_SLEEP_CLK] = &amp;camcc_sleep_clk.clkr,</div><div class='add'>+	[CAMCC_SLEEP_CLK_SRC] = &amp;camcc_sleep_clk_src.clkr,</div><div class='add'>+	[CAMCC_SLOW_AHB_CLK_SRC] = &amp;camcc_slow_ahb_clk_src.clkr,</div><div class='add'>+	[CAMCC_XO_CLK_SRC] = &amp;camcc_xo_clk_src.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc *camcc_sc8280xp_gdscs[] = {</div><div class='add'>+	[BPS_GDSC] = &amp;bps_gdsc,</div><div class='add'>+	[IFE_0_GDSC] = &amp;ife_0_gdsc,</div><div class='add'>+	[IFE_1_GDSC] = &amp;ife_1_gdsc,</div><div class='add'>+	[IFE_2_GDSC] = &amp;ife_2_gdsc,</div><div class='add'>+	[IFE_3_GDSC] = &amp;ife_3_gdsc,</div><div class='add'>+	[IPE_0_GDSC] = &amp;ipe_0_gdsc,</div><div class='add'>+	[IPE_1_GDSC] = &amp;ipe_1_gdsc,</div><div class='add'>+	[TITAN_TOP_GDSC] = &amp;titan_top_gdsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map camcc_sc8280xp_resets[] = {</div><div class='add'>+	[CAMCC_BPS_BCR] = { 0x7000 },</div><div class='add'>+	[CAMCC_CAMNOC_BCR] = { 0xc16c },</div><div class='add'>+	[CAMCC_CCI_BCR] = { 0xc104 },</div><div class='add'>+	[CAMCC_CPAS_BCR] = { 0xc164 },</div><div class='add'>+	[CAMCC_CSI0PHY_BCR] = { 0x6000 },</div><div class='add'>+	[CAMCC_CSI1PHY_BCR] = { 0x6024 },</div><div class='add'>+	[CAMCC_CSI2PHY_BCR] = { 0x6048 },</div><div class='add'>+	[CAMCC_CSI3PHY_BCR] = { 0x6070 },</div><div class='add'>+	[CAMCC_ICP_BCR] = { 0xc0b4 },</div><div class='add'>+	[CAMCC_IFE_0_BCR] = { 0xa000 },</div><div class='add'>+	[CAMCC_IFE_1_BCR] = { 0xb000 },</div><div class='add'>+	[CAMCC_IFE_2_BCR] = { 0xf000 },</div><div class='add'>+	[CAMCC_IFE_3_BCR] = { 0xf06c },</div><div class='add'>+	[CAMCC_IFE_LITE_0_BCR] = { 0xc000 },</div><div class='add'>+	[CAMCC_IFE_LITE_1_BCR] = { 0xc044 },</div><div class='add'>+	[CAMCC_IFE_LITE_2_BCR] = { 0xc23c },</div><div class='add'>+	[CAMCC_IFE_LITE_3_BCR] = { 0xc280 },</div><div class='add'>+	[CAMCC_IPE_0_BCR] = { 0x8000 },</div><div class='add'>+	[CAMCC_IPE_1_BCR] = { 0x9000 },</div><div class='add'>+	[CAMCC_JPEG_BCR] = { 0xc088 },</div><div class='add'>+	[CAMCC_LRME_BCR] = { 0xc140 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config camcc_sc8280xp_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x13020,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_cc_desc camcc_sc8280xp_desc = {</div><div class='add'>+	.config = &amp;camcc_sc8280xp_regmap_config,</div><div class='add'>+	.clks = camcc_sc8280xp_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(camcc_sc8280xp_clocks),</div><div class='add'>+	.resets = camcc_sc8280xp_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(camcc_sc8280xp_resets),</div><div class='add'>+	.gdscs = camcc_sc8280xp_gdscs,</div><div class='add'>+	.num_gdscs = ARRAY_SIZE(camcc_sc8280xp_gdscs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id camcc_sc8280xp_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,sc8280xp-camcc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, camcc_sc8280xp_match_table);</div><div class='add'>+</div><div class='add'>+static int camcc_sc8280xp_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;camcc_sc8280xp_desc);</div><div class='add'>+	if (IS_ERR(regmap)) {</div><div class='add'>+		ret = PTR_ERR(regmap);</div><div class='add'>+		goto err_put_rpm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll0, regmap, &amp;camcc_pll0_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll1, regmap, &amp;camcc_pll1_config);</div><div class='add'>+	clk_zonda_pll_configure(&amp;camcc_pll2, regmap, &amp;camcc_pll2_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll3, regmap, &amp;camcc_pll3_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll4, regmap, &amp;camcc_pll4_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll5, regmap, &amp;camcc_pll5_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll6, regmap, &amp;camcc_pll6_config);</div><div class='add'>+	clk_lucid_pll_configure(&amp;camcc_pll7, regmap, &amp;camcc_pll7_config);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Keep camcc_gdsc_clk always enabled:</div><div class='add'>+	 */</div><div class='add'>+	regmap_update_bits(regmap, 0xc1e4, BIT(0), 1);</div><div class='add'>+</div><div class='add'>+	ret = qcom_cc_really_probe(pdev, &amp;camcc_sc8280xp_desc, regmap);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_disable;</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_disable:</div><div class='add'>+	regmap_update_bits(regmap, 0xc1e4, BIT(0), 0);</div><div class='add'>+err_put_rpm:</div><div class='add'>+	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver camcc_sc8280xp_driver = {</div><div class='add'>+	.probe = camcc_sc8280xp_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "camcc-sc8280xp",</div><div class='add'>+		.of_match_table = camcc_sc8280xp_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_platform_driver(camcc_sc8280xp_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QCOM CAMCC SC8280XP Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c<br/>index fc4735f74f0f..c1dba33ac31a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-branch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/clk-branch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-branch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-branch.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2013, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='hunk'>@@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw)</div><div class='ctx'> 	clk_branch_toggle(hw, false, clk_branch2_check_halt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int clk_branch2_mem_enable(struct clk_hw *hw)</div><div class='add'>+{</div><div class='add'>+	struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);</div><div class='add'>+	struct clk_branch branch = mem_br-&gt;branch;</div><div class='add'>+	u32 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	regmap_update_bits(branch.clkr.regmap, mem_br-&gt;mem_enable_reg,</div><div class='add'>+			   mem_br-&gt;mem_enable_ack_mask, mem_br-&gt;mem_enable_ack_mask);</div><div class='add'>+</div><div class='add'>+	ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br-&gt;mem_ack_reg,</div><div class='add'>+				       val, val &amp; mem_br-&gt;mem_enable_ack_mask, 0, 200);</div><div class='add'>+	if (ret) {</div><div class='add'>+		WARN(1, "%s mem enable failed\n", clk_hw_get_name(&amp;branch.clkr.hw));</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return clk_branch2_enable(hw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clk_branch2_mem_disable(struct clk_hw *hw)</div><div class='add'>+{</div><div class='add'>+	struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);</div><div class='add'>+</div><div class='add'>+	regmap_update_bits(mem_br-&gt;branch.clkr.regmap, mem_br-&gt;mem_enable_reg,</div><div class='add'>+			   mem_br-&gt;mem_enable_ack_mask, 0);</div><div class='add'>+</div><div class='add'>+	return clk_branch2_disable(hw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct clk_ops clk_branch2_mem_ops = {</div><div class='add'>+	.enable = clk_branch2_mem_enable,</div><div class='add'>+	.disable = clk_branch2_mem_disable,</div><div class='add'>+	.is_enabled = clk_is_enabled_regmap,</div><div class='add'>+};</div><div class='add'>+EXPORT_SYMBOL_GPL(clk_branch2_mem_ops);</div><div class='add'>+</div><div class='ctx'> const struct clk_ops clk_branch2_ops = {</div><div class='ctx'> 	.enable = clk_branch2_enable,</div><div class='ctx'> 	.disable = clk_branch2_disable,</div><div class='head'>diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h<br/>index 0cf800b9d08d..8ffed603c050 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-branch.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/clk-branch.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-branch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-branch.h</a></div><div class='hunk'>@@ -38,6 +38,23 @@ struct clk_branch {</div><div class='ctx'> 	struct clk_regmap clkr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct clk_mem_branch - gating clock which are associated with memories</div><div class='add'>+ *</div><div class='add'>+ * @mem_enable_reg: branch clock memory gating register</div><div class='add'>+ * @mem_ack_reg: branch clock memory ack register</div><div class='add'>+ * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg</div><div class='add'>+ * @branch: branch clock gating handle</div><div class='add'>+ *</div><div class='add'>+ * Clock which can gate its memories.</div><div class='add'>+ */</div><div class='add'>+struct clk_mem_branch {</div><div class='add'>+	u32	mem_enable_reg;</div><div class='add'>+	u32	mem_ack_reg;</div><div class='add'>+	u32	mem_enable_ack_mask;</div><div class='add'>+	struct clk_branch branch;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Branch clock common bits for HLOS-owned clocks */</div><div class='ctx'> #define CBCR_CLK_OFF			BIT(31)</div><div class='ctx'> #define CBCR_NOC_FSM_STATUS		GENMASK(30, 28)</div><div class='hunk'>@@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops;</div><div class='ctx'> extern const struct clk_ops clk_branch2_ops;</div><div class='ctx'> extern const struct clk_ops clk_branch_simple_ops;</div><div class='ctx'> extern const struct clk_ops clk_branch2_aon_ops;</div><div class='add'>+extern const struct clk_ops clk_branch2_mem_ops;</div><div class='ctx'> </div><div class='ctx'> #define to_clk_branch(_hw) \</div><div class='ctx'> 	container_of(to_clk_regmap(_hw), struct clk_branch, clkr)</div><div class='ctx'> </div><div class='add'>+#define to_clk_mem_branch(_hw) \</div><div class='add'>+	container_of(to_clk_branch(_hw), struct clk_mem_branch, branch)</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c<br/>index 5d853fd43294..bb82abeed88f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-rpmh.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/clk-rpmh.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/clk-rpmh.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/clk-rpmh.c</a></div><div class='hunk'>@@ -372,6 +372,9 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);</div><div class='ctx'> DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);</div><div class='ctx'> DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);</div><div class='ctx'> </div><div class='add'>+DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);</div><div class='add'>+DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);</div><div class='add'>+DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2);</div><div class='ctx'> DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);</div><div class='ctx'> DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);</div><div class='ctx'> DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);</div><div class='hunk'>@@ -630,6 +633,37 @@ static const struct clk_rpmh_desc clk_rpmh_sm8550 = {</div><div class='ctx'> 	.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_hw *sm8650_rpmh_clocks[] = {</div><div class='add'>+	[RPMH_CXO_CLK]		= &amp;clk_rpmh_bi_tcxo_div2.hw,</div><div class='add'>+	[RPMH_CXO_CLK_A]	= &amp;clk_rpmh_bi_tcxo_div2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK1]	= &amp;clk_rpmh_clk6_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK1_A]	= &amp;clk_rpmh_clk6_a2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK2]	= &amp;clk_rpmh_clk7_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK2_A]	= &amp;clk_rpmh_clk7_a2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK3]	= &amp;clk_rpmh_clk8_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK3_A]	= &amp;clk_rpmh_clk8_a2_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK1]		= &amp;clk_rpmh_clk1_a1.hw,</div><div class='add'>+	[RPMH_RF_CLK1_A]	= &amp;clk_rpmh_clk1_a1_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK2]		= &amp;clk_rpmh_clk2_a1.hw,</div><div class='add'>+	[RPMH_RF_CLK2_A]	= &amp;clk_rpmh_clk2_a1_ao.hw,</div><div class='add'>+	/*</div><div class='add'>+	 * The clka3 RPMh resource is missing in cmd-db</div><div class='add'>+	 * for current platforms, while the clka3 exists</div><div class='add'>+	 * on the PMK8550, the clock is unconnected and</div><div class='add'>+	 * unused.</div><div class='add'>+	 */</div><div class='add'>+	[RPMH_RF_CLK4]		= &amp;clk_rpmh_clk4_a2.hw,</div><div class='add'>+	[RPMH_RF_CLK4_A]	= &amp;clk_rpmh_clk4_a2_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK5]		= &amp;clk_rpmh_clk5_a2.hw,</div><div class='add'>+	[RPMH_RF_CLK5_A]	= &amp;clk_rpmh_clk5_a2_ao.hw,</div><div class='add'>+	[RPMH_IPA_CLK]		= &amp;clk_rpmh_ipa.hw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_rpmh_desc clk_rpmh_sm8650 = {</div><div class='add'>+	.clks = sm8650_rpmh_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct clk_hw *sc7280_rpmh_clocks[] = {</div><div class='ctx'> 	[RPMH_CXO_CLK]      = &amp;clk_rpmh_bi_tcxo_div4.hw,</div><div class='ctx'> 	[RPMH_CXO_CLK_A]    = &amp;clk_rpmh_bi_tcxo_div4_ao.hw,</div><div class='hunk'>@@ -737,6 +771,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 = {</div><div class='ctx'> 	.num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_hw *x1e80100_rpmh_clocks[] = {</div><div class='add'>+	[RPMH_CXO_CLK]		= &amp;clk_rpmh_bi_tcxo_div2.hw,</div><div class='add'>+	[RPMH_CXO_CLK_A]	= &amp;clk_rpmh_bi_tcxo_div2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK1]	= &amp;clk_rpmh_clk6_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK1_A]	= &amp;clk_rpmh_clk6_a2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK2]	= &amp;clk_rpmh_clk7_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK2_A]	= &amp;clk_rpmh_clk7_a2_ao.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK3]	= &amp;clk_rpmh_clk8_a2.hw,</div><div class='add'>+	[RPMH_LN_BB_CLK3_A]	= &amp;clk_rpmh_clk8_a2_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK3]		= &amp;clk_rpmh_clk3_a2.hw,</div><div class='add'>+	[RPMH_RF_CLK3_A]	= &amp;clk_rpmh_clk3_a2_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK4]		= &amp;clk_rpmh_clk4_a2.hw,</div><div class='add'>+	[RPMH_RF_CLK4_A]	= &amp;clk_rpmh_clk4_a2_ao.hw,</div><div class='add'>+	[RPMH_RF_CLK5]		= &amp;clk_rpmh_clk5_a2.hw,</div><div class='add'>+	[RPMH_RF_CLK5_A]	= &amp;clk_rpmh_clk5_a2_ao.hw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {</div><div class='add'>+	.clks = x1e80100_rpmh_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,</div><div class='ctx'> 					 void *data)</div><div class='ctx'> {</div><div class='hunk'>@@ -837,7 +893,9 @@ static const struct of_device_id clk_rpmh_match_table[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sm8350-rpmh-clk", .data = &amp;clk_rpmh_sm8350},</div><div class='ctx'> 	{ .compatible = "qcom,sm8450-rpmh-clk", .data = &amp;clk_rpmh_sm8450},</div><div class='ctx'> 	{ .compatible = "qcom,sm8550-rpmh-clk", .data = &amp;clk_rpmh_sm8550},</div><div class='add'>+	{ .compatible = "qcom,sm8650-rpmh-clk", .data = &amp;clk_rpmh_sm8650},</div><div class='ctx'> 	{ .compatible = "qcom,sc7280-rpmh-clk", .data = &amp;clk_rpmh_sc7280},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-rpmh-clk", .data = &amp;clk_rpmh_x1e80100},</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);</div><div class='head'>diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c<br/>index aefa19f3c2c5..f96d8b81fd9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/dispcc-sm8550.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/dispcc-sm8550.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/dispcc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/dispcc-sm8550.c</a></div><div class='hunk'>@@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = {</div><div class='ctx'> 	.config_ctl_val = 0x20485699,</div><div class='ctx'> 	.config_ctl_hi_val = 0x00182261,</div><div class='ctx'> 	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='ctx'> 	.user_ctl_val = 0x00000000,</div><div class='ctx'> 	.user_ctl_hi_val = 0x00000005,</div><div class='ctx'> };</div><div class='hunk'>@@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = {</div><div class='ctx'> 	.config_ctl_val = 0x20485699,</div><div class='ctx'> 	.config_ctl_hi_val = 0x00182261,</div><div class='ctx'> 	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='ctx'> 	.user_ctl_val = 0x00000000,</div><div class='ctx'> 	.user_ctl_hi_val = 0x00000005,</div><div class='ctx'> };</div><div class='hunk'>@@ -1766,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_put_rpm;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	clk_lucid_evo_pll_configure(&amp;disp_cc_pll0, regmap, &amp;disp_cc_pll0_config);</div><div class='del'>-	clk_lucid_evo_pll_configure(&amp;disp_cc_pll1, regmap, &amp;disp_cc_pll1_config);</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;disp_cc_pll0, regmap, &amp;disp_cc_pll0_config);</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;disp_cc_pll1, regmap, &amp;disp_cc_pll1_config);</div><div class='ctx'> </div><div class='ctx'> 	/* Enable clock gating for MDP clocks */</div><div class='ctx'> 	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);</div><div class='head'>diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c<br/>new file mode 100644<br/>index 000000000000..f3b1d9d16bae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/dispcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/dispcc-sm8650.c</a></div><div class='hunk'>@@ -0,0 +1,1818 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved</div><div class='add'>+ * Copyright (c) 2023, Linaro Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sm8650-dispcc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "common.h"</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-pll.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "clk-regmap-divider.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+#include "gdsc.h"</div><div class='add'>+</div><div class='add'>+/* Need to match the order of clocks in DT binding */</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_BI_TCXO_AO,</div><div class='add'>+	DT_AHB_CLK,</div><div class='add'>+	DT_SLEEP_CLK,</div><div class='add'>+</div><div class='add'>+	DT_DSI0_PHY_PLL_OUT_BYTECLK,</div><div class='add'>+	DT_DSI0_PHY_PLL_OUT_DSICLK,</div><div class='add'>+	DT_DSI1_PHY_PLL_OUT_BYTECLK,</div><div class='add'>+	DT_DSI1_PHY_PLL_OUT_DSICLK,</div><div class='add'>+</div><div class='add'>+	DT_DP0_PHY_PLL_LINK_CLK,</div><div class='add'>+	DT_DP0_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	DT_DP1_PHY_PLL_LINK_CLK,</div><div class='add'>+	DT_DP1_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	DT_DP2_PHY_PLL_LINK_CLK,</div><div class='add'>+	DT_DP2_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	DT_DP3_PHY_PLL_LINK_CLK,</div><div class='add'>+	DT_DP3_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DISP_CC_MISC_CMD	0xF000</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_DISP_CC_PLL0_OUT_MAIN,</div><div class='add'>+	P_DISP_CC_PLL1_OUT_EVEN,</div><div class='add'>+	P_DISP_CC_PLL1_OUT_MAIN,</div><div class='add'>+	P_DP0_PHY_PLL_LINK_CLK,</div><div class='add'>+	P_DP0_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	P_DP1_PHY_PLL_LINK_CLK,</div><div class='add'>+	P_DP1_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	P_DP2_PHY_PLL_LINK_CLK,</div><div class='add'>+	P_DP2_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	P_DP3_PHY_PLL_LINK_CLK,</div><div class='add'>+	P_DP3_PHY_PLL_VCO_DIV_CLK,</div><div class='add'>+	P_DSI0_PHY_PLL_OUT_BYTECLK,</div><div class='add'>+	P_DSI0_PHY_PLL_OUT_DSICLK,</div><div class='add'>+	P_DSI1_PHY_PLL_OUT_BYTECLK,</div><div class='add'>+	P_DSI1_PHY_PLL_OUT_DSICLK,</div><div class='add'>+	P_SLEEP_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct pll_vco lucid_ole_vco[] = {</div><div class='add'>+	{ 249600000, 2100000000, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct alpha_pll_config disp_cc_pll0_config = {</div><div class='add'>+	.l = 0xd,</div><div class='add'>+	.alpha = 0x6492,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000005,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll disp_cc_pll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.vco_table = lucid_ole_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_ole_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_pll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_reset_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct alpha_pll_config disp_cc_pll1_config = {</div><div class='add'>+	.l = 0x1f,</div><div class='add'>+	.alpha = 0x4000,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000005,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll disp_cc_pll1 = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.vco_table = lucid_ole_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_ole_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_pll1",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_reset_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO_AO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },</div><div class='add'>+	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },</div><div class='add'>+	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },</div><div class='add'>+	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },</div><div class='add'>+	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },</div><div class='add'>+	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },</div><div class='add'>+	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },</div><div class='add'>+	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },</div><div class='add'>+	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_3[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DP1_PHY_PLL_LINK_CLK, 2 },</div><div class='add'>+	{ P_DP2_PHY_PLL_LINK_CLK, 3 },</div><div class='add'>+	{ P_DP3_PHY_PLL_LINK_CLK, 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_3[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DP1_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP2_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP3_PHY_PLL_LINK_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_4[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DP0_PHY_PLL_LINK_CLK, 1 },</div><div class='add'>+	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },</div><div class='add'>+	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },</div><div class='add'>+	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },</div><div class='add'>+	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_4[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DP0_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_5[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },</div><div class='add'>+	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_5[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },</div><div class='add'>+	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_6[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_6[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;disp_cc_pll1.clkr.hw },</div><div class='add'>+	{ .hw = &amp;disp_cc_pll1.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_7[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DP0_PHY_PLL_LINK_CLK, 1 },</div><div class='add'>+	{ P_DP1_PHY_PLL_LINK_CLK, 2 },</div><div class='add'>+	{ P_DP2_PHY_PLL_LINK_CLK, 3 },</div><div class='add'>+	{ P_DP3_PHY_PLL_LINK_CLK, 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_7[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_DP0_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP1_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP2_PHY_PLL_LINK_CLK },</div><div class='add'>+	{ .index = DT_DP3_PHY_PLL_LINK_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_8[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_8[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;disp_cc_pll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;disp_cc_pll1.clkr.hw },</div><div class='add'>+	{ .hw = &amp;disp_cc_pll1.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map disp_cc_parent_map_9[] = {</div><div class='add'>+	{ P_SLEEP_CLK, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data disp_cc_parent_data_9[] = {</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),</div><div class='add'>+	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x82e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_6,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_ahb_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_6,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8108,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_byte0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_byte2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8124,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_byte1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_byte2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81bc,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx0_aux_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {</div><div class='add'>+	F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),</div><div class='add'>+	F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),</div><div class='add'>+	F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),</div><div class='add'>+	F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8170,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_7,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx0_link_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_7,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x818c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx0_pixel0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81a4,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx0_pixel1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8220,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx1_aux_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8204,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx1_link_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81d4,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx1_pixel0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81ec,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx1_pixel1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8284,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx2_aux_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8238,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx2_link_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8254,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx2_pixel0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x826c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx2_pixel1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x82d0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx3_aux_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x82b4,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx3_link_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x829c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx3_pixel0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_dp_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8140,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_esc0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8158,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_esc1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x80d8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_8,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_mdp_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_8,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x80a8,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_pclk0_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_pixel_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x80c0,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_pclk1_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_pixel_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x80f0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_vsync_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {</div><div class='add'>+	F(32000, P_SLEEP_CLK, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_sleep_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xe05c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_9,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_sleep_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_sleep_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_9,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 disp_cc_xo_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xe03c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = disp_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_xo_clk_src",</div><div class='add'>+		.parent_data = disp_cc_parent_data_0_ao,</div><div class='add'>+		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {</div><div class='add'>+	.reg = 0x8120,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_byte0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_byte0_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {</div><div class='add'>+	.reg = 0x813c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_byte1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_byte1_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {</div><div class='add'>+	.reg = 0x8188,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx0_link_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_dptx0_link_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {</div><div class='add'>+	.reg = 0x821c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx1_link_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_dptx1_link_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {</div><div class='add'>+	.reg = 0x8250,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx2_link_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_dptx2_link_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {</div><div class='add'>+	.reg = 0x82cc,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "disp_cc_mdss_dptx3_link_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;disp_cc_mdss_dptx3_link_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_accu_clk = {</div><div class='add'>+	.halt_reg = 0xe058,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xe058,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_accu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_xo_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_ahb1_clk = {</div><div class='add'>+	.halt_reg = 0xa020,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_ahb1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x80a4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_byte0_clk = {</div><div class='add'>+	.halt_reg = 0x8028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_byte0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_byte0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_byte0_intf_clk = {</div><div class='add'>+	.halt_reg = 0x802c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x802c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_byte0_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_byte0_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_byte1_clk = {</div><div class='add'>+	.halt_reg = 0x8030,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8030,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_byte1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_byte1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_byte1_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8034,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8034,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_byte1_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_byte1_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8058,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8058,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {</div><div class='add'>+	.halt_reg = 0x804c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x804c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_crypto_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_link_clk = {</div><div class='add'>+	.halt_reg = 0x8040,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_link_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8048,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8048,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {</div><div class='add'>+	.halt_reg = 0x8050,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8050,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_pixel0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {</div><div class='add'>+	.halt_reg = 0x8054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_pixel1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8074,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8074,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {</div><div class='add'>+	.halt_reg = 0x8070,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8070,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_crypto_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_link_clk = {</div><div class='add'>+	.halt_reg = 0x8064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_link_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x806c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x806c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {</div><div class='add'>+	.halt_reg = 0x805c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x805c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_pixel0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {</div><div class='add'>+	.halt_reg = 0x8060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_pixel1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8068,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {</div><div class='add'>+	.halt_reg = 0x808c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x808c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {</div><div class='add'>+	.halt_reg = 0x8088,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_crypto_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_link_clk = {</div><div class='add'>+	.halt_reg = 0x8080,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8080,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_link_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8084,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8084,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {</div><div class='add'>+	.halt_reg = 0x8078,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8078,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_pixel0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {</div><div class='add'>+	.halt_reg = 0x807c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x807c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx2_pixel1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {</div><div class='add'>+	.halt_reg = 0x809c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x809c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx3_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {</div><div class='add'>+	.halt_reg = 0x80a0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80a0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx3_crypto_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx3_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx3_link_clk = {</div><div class='add'>+	.halt_reg = 0x8094,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8094,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx3_link_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx3_link_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {</div><div class='add'>+	.halt_reg = 0x8098,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8098,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx3_link_intf_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {</div><div class='add'>+	.halt_reg = 0x8090,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_dptx3_pixel0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_esc0_clk = {</div><div class='add'>+	.halt_reg = 0x8038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_esc0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_esc0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_esc1_clk = {</div><div class='add'>+	.halt_reg = 0x803c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x803c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_esc1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_esc1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_mdp1_clk = {</div><div class='add'>+	.halt_reg = 0xa004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_mdp1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_mdp_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_mdp_clk = {</div><div class='add'>+	.halt_reg = 0x800c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x800c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_mdp_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_mdp_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {</div><div class='add'>+	.halt_reg = 0xa010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_mdp_lut1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_mdp_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_mdp_lut_clk = {</div><div class='add'>+	.halt_reg = 0x8018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_mdp_lut_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_mdp_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xc004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_non_gdsc_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_pclk0_clk = {</div><div class='add'>+	.halt_reg = 0x8004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_pclk0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_pclk0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_pclk1_clk = {</div><div class='add'>+	.halt_reg = 0x8008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_pclk1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_pclk1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xc00c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc00c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_rscc_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {</div><div class='add'>+	.halt_reg = 0xc008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xc008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_rscc_vsync_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_vsync_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_vsync1_clk = {</div><div class='add'>+	.halt_reg = 0xa01c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa01c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_vsync1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_vsync_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_mdss_vsync_clk = {</div><div class='add'>+	.halt_reg = 0x8024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_mdss_vsync_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_mdss_vsync_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch disp_cc_sleep_clk = {</div><div class='add'>+	.halt_reg = 0xe074,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xe074,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "disp_cc_sleep_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;disp_cc_sleep_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc mdss_gdsc = {</div><div class='add'>+	.gdscr = 0x9000,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "mdss_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = HW_CTRL | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc mdss_int2_gdsc = {</div><div class='add'>+	.gdscr = 0xb000,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "mdss_int2_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = HW_CTRL | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *disp_cc_sm8650_clocks[] = {</div><div class='add'>+	[DISP_CC_MDSS_ACCU_CLK] = &amp;disp_cc_mdss_accu_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_AHB1_CLK] = &amp;disp_cc_mdss_ahb1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_AHB_CLK] = &amp;disp_cc_mdss_ahb_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_AHB_CLK_SRC] = &amp;disp_cc_mdss_ahb_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE0_CLK] = &amp;disp_cc_mdss_byte0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &amp;disp_cc_mdss_byte0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &amp;disp_cc_mdss_byte0_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &amp;disp_cc_mdss_byte0_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE1_CLK] = &amp;disp_cc_mdss_byte1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &amp;disp_cc_mdss_byte1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &amp;disp_cc_mdss_byte1_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &amp;disp_cc_mdss_byte1_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &amp;disp_cc_mdss_dptx0_aux_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &amp;disp_cc_mdss_dptx0_aux_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &amp;disp_cc_mdss_dptx0_crypto_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &amp;disp_cc_mdss_dptx0_link_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &amp;disp_cc_mdss_dptx0_link_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &amp;disp_cc_mdss_dptx0_link_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &amp;disp_cc_mdss_dptx0_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &amp;disp_cc_mdss_dptx0_pixel0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &amp;disp_cc_mdss_dptx0_pixel0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &amp;disp_cc_mdss_dptx0_pixel1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &amp;disp_cc_mdss_dptx0_pixel1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =</div><div class='add'>+		&amp;disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &amp;disp_cc_mdss_dptx1_aux_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &amp;disp_cc_mdss_dptx1_aux_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &amp;disp_cc_mdss_dptx1_crypto_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &amp;disp_cc_mdss_dptx1_link_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &amp;disp_cc_mdss_dptx1_link_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &amp;disp_cc_mdss_dptx1_link_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &amp;disp_cc_mdss_dptx1_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &amp;disp_cc_mdss_dptx1_pixel0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &amp;disp_cc_mdss_dptx1_pixel0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &amp;disp_cc_mdss_dptx1_pixel1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &amp;disp_cc_mdss_dptx1_pixel1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =</div><div class='add'>+		&amp;disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &amp;disp_cc_mdss_dptx2_aux_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &amp;disp_cc_mdss_dptx2_aux_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &amp;disp_cc_mdss_dptx2_crypto_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &amp;disp_cc_mdss_dptx2_link_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &amp;disp_cc_mdss_dptx2_link_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &amp;disp_cc_mdss_dptx2_link_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &amp;disp_cc_mdss_dptx2_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &amp;disp_cc_mdss_dptx2_pixel0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &amp;disp_cc_mdss_dptx2_pixel0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &amp;disp_cc_mdss_dptx2_pixel1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &amp;disp_cc_mdss_dptx2_pixel1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &amp;disp_cc_mdss_dptx3_aux_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &amp;disp_cc_mdss_dptx3_aux_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &amp;disp_cc_mdss_dptx3_crypto_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &amp;disp_cc_mdss_dptx3_link_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &amp;disp_cc_mdss_dptx3_link_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &amp;disp_cc_mdss_dptx3_link_div_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &amp;disp_cc_mdss_dptx3_link_intf_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &amp;disp_cc_mdss_dptx3_pixel0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &amp;disp_cc_mdss_dptx3_pixel0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_ESC0_CLK] = &amp;disp_cc_mdss_esc0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_ESC0_CLK_SRC] = &amp;disp_cc_mdss_esc0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_ESC1_CLK] = &amp;disp_cc_mdss_esc1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_ESC1_CLK_SRC] = &amp;disp_cc_mdss_esc1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_MDP1_CLK] = &amp;disp_cc_mdss_mdp1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_MDP_CLK] = &amp;disp_cc_mdss_mdp_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_MDP_CLK_SRC] = &amp;disp_cc_mdss_mdp_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_MDP_LUT1_CLK] = &amp;disp_cc_mdss_mdp_lut1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_MDP_LUT_CLK] = &amp;disp_cc_mdss_mdp_lut_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &amp;disp_cc_mdss_non_gdsc_ahb_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_PCLK0_CLK] = &amp;disp_cc_mdss_pclk0_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &amp;disp_cc_mdss_pclk0_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_PCLK1_CLK] = &amp;disp_cc_mdss_pclk1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &amp;disp_cc_mdss_pclk1_clk_src.clkr,</div><div class='add'>+	[DISP_CC_MDSS_RSCC_AHB_CLK] = &amp;disp_cc_mdss_rscc_ahb_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &amp;disp_cc_mdss_rscc_vsync_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_VSYNC1_CLK] = &amp;disp_cc_mdss_vsync1_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_VSYNC_CLK] = &amp;disp_cc_mdss_vsync_clk.clkr,</div><div class='add'>+	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &amp;disp_cc_mdss_vsync_clk_src.clkr,</div><div class='add'>+	[DISP_CC_PLL0] = &amp;disp_cc_pll0.clkr,</div><div class='add'>+	[DISP_CC_PLL1] = &amp;disp_cc_pll1.clkr,</div><div class='add'>+	[DISP_CC_SLEEP_CLK] = &amp;disp_cc_sleep_clk.clkr,</div><div class='add'>+	[DISP_CC_SLEEP_CLK_SRC] = &amp;disp_cc_sleep_clk_src.clkr,</div><div class='add'>+	[DISP_CC_XO_CLK_SRC] = &amp;disp_cc_xo_clk_src.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map disp_cc_sm8650_resets[] = {</div><div class='add'>+	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },</div><div class='add'>+	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },</div><div class='add'>+	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc *disp_cc_sm8650_gdscs[] = {</div><div class='add'>+	[MDSS_GDSC] = &amp;mdss_gdsc,</div><div class='add'>+	[MDSS_INT2_GDSC] = &amp;mdss_int2_gdsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config disp_cc_sm8650_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x11008,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_cc_desc disp_cc_sm8650_desc = {</div><div class='add'>+	.config = &amp;disp_cc_sm8650_regmap_config,</div><div class='add'>+	.clks = disp_cc_sm8650_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(disp_cc_sm8650_clocks),</div><div class='add'>+	.resets = disp_cc_sm8650_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(disp_cc_sm8650_resets),</div><div class='add'>+	.gdscs = disp_cc_sm8650_gdscs,</div><div class='add'>+	.num_gdscs = ARRAY_SIZE(disp_cc_sm8650_gdscs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id disp_cc_sm8650_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,sm8650-dispcc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, disp_cc_sm8650_match_table);</div><div class='add'>+</div><div class='add'>+static int disp_cc_sm8650_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;disp_cc_sm8650_desc);</div><div class='add'>+	if (IS_ERR(regmap)) {</div><div class='add'>+		ret = PTR_ERR(regmap);</div><div class='add'>+		goto err_put_rpm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;disp_cc_pll0, regmap, &amp;disp_cc_pll0_config);</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;disp_cc_pll1, regmap, &amp;disp_cc_pll1_config);</div><div class='add'>+</div><div class='add'>+	/* Enable clock gating for MDP clocks */</div><div class='add'>+	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);</div><div class='add'>+</div><div class='add'>+	/* Keep clocks always enabled */</div><div class='add'>+	regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */</div><div class='add'>+</div><div class='add'>+	ret = qcom_cc_really_probe(pdev, &amp;disp_cc_sm8650_desc, regmap);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_put_rpm;</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_put_rpm:</div><div class='add'>+	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver disp_cc_sm8650_driver = {</div><div class='add'>+	.probe = disp_cc_sm8650_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "disp_cc-sm8650",</div><div class='add'>+		.of_match_table = disp_cc_sm8650_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init disp_cc_sm8650_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;disp_cc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+subsys_initcall(disp_cc_sm8650_init);</div><div class='add'>+</div><div class='add'>+static void __exit disp_cc_sm8650_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;disp_cc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(disp_cc_sm8650_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-qdu1000.c<br/>new file mode 100644<br/>index 000000000000..c628054a7025<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/ecpricc-qdu1000.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/ecpricc-qdu1000.c</a></div><div class='hunk'>@@ -0,0 +1,2456 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,qdu1000-ecpricc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "clk-regmap-divider.h"</div><div class='add'>+#include "clk-regmap-mux.h"</div><div class='add'>+#include "common.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN,</div><div class='add'>+	DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_ECPRI_CC_PLL0_OUT_MAIN,</div><div class='add'>+	P_ECPRI_CC_PLL1_OUT_MAIN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL0_OUT_MAIN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL1_OUT_EVEN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL2_OUT_MAIN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL3_OUT_MAIN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL4_OUT_MAIN,</div><div class='add'>+	P_GCC_ECPRI_CC_GPLL5_OUT_EVEN,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct pll_vco lucid_evo_vco[] = {</div><div class='add'>+	{ 249600000, 2020000000, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* 700 MHz configuration */</div><div class='add'>+static const struct alpha_pll_config ecpri_cc_pll0_config = {</div><div class='add'>+	.l = 0x24,</div><div class='add'>+	.alpha = 0x7555,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x32aa299c,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll ecpri_cc_pll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.vco_table = lucid_evo_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_evo_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_pll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_evo_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* 806 MHz configuration */</div><div class='add'>+static const struct alpha_pll_config ecpri_cc_pll1_config = {</div><div class='add'>+	.l = 0x29,</div><div class='add'>+	.alpha = 0xfaaa,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x32aa299c,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000805,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll ecpri_cc_pll1 = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.vco_table = lucid_evo_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_evo_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x0,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_pll1",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_evo_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map ecpri_cc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },</div><div class='add'>+	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data ecpri_cc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll1.clkr.hw },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll0.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map ecpri_cc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 2 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 3 },</div><div class='add'>+	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data ecpri_cc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll1.clkr.hw },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll0.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map ecpri_cc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },</div><div class='add'>+	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data ecpri_cc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll1.clkr.hw },</div><div class='add'>+	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },</div><div class='add'>+	{ .hw = &amp;ecpri_cc_pll0.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_ecpri_clk_src[] = {</div><div class='add'>+	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_ecpri_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9034,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_ecpri_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_ecpri_dma_clk_src[] = {</div><div class='add'>+	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_ecpri_dma_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9080,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_ecpri_dma_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_ecpri_dma_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_ecpri_fast_clk_src[] = {</div><div class='add'>+	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	F(600000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_ecpri_fast_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x904c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_ecpri_fast_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_ecpri_fast_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_ecpri_oran_clk_src[] = {</div><div class='add'>+	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_ecpri_oran_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9064,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_ecpri_oran_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_ecpri_oran_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src[] = {</div><div class='add'>+	F(201500000, P_ECPRI_CC_PLL1_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(403000000, P_ECPRI_CC_PLL1_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_c2c0_hm_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81b0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_c2c0_hm_ff_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src[] = {</div><div class='add'>+	F(100000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_c2c_hm_macsec_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8150,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81c8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh0_hm_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8168,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh0_hm_ff_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh0_macsec_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8108,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh0_macsec_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh1_hm_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8180,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh1_hm_ff_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src[] = {</div><div class='add'>+	F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh1_macsec_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8120,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh1_macsec_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh2_hm_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8198,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh2_hm_ff_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_fh2_macsec_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8138,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh2_macsec_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src[] = {</div><div class='add'>+	F(533000000, P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(700000000, P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	F(806000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8228,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8240,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81e0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x81f8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8210,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_ecpri_cc_mss_emac_clk_src[] = {</div><div class='add'>+	F(403000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 ecpri_cc_mss_emac_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xe00c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = ecpri_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_ecpri_cc_mss_emac_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_mss_emac_clk_src",</div><div class='add'>+		.parent_data = ecpri_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_ecpri_fast_div2_clk_src = {</div><div class='add'>+	.reg = 0x907c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_ecpri_fast_div2_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_ecpri_fast_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src = {</div><div class='add'>+	.reg = 0x8290,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src = {</div><div class='add'>+	.reg = 0x8294,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src = {</div><div class='add'>+	.reg = 0x8298,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src = {</div><div class='add'>+	.reg = 0x829c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src = {</div><div class='add'>+	.reg = 0x8260,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src = {</div><div class='add'>+	.reg = 0x8264,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src = {</div><div class='add'>+	.reg = 0x8268,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src = {</div><div class='add'>+	.reg = 0x826c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src = {</div><div class='add'>+	.reg = 0x8270,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src = {</div><div class='add'>+	.reg = 0x8274,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src = {</div><div class='add'>+	.reg = 0x8278,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src = {</div><div class='add'>+	.reg = 0x827c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src = {</div><div class='add'>+	.reg = 0x8280,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src = {</div><div class='add'>+	.reg = 0x8284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src = {</div><div class='add'>+	.reg = 0x8288,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src = {</div><div class='add'>+	.reg = 0x828c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_cg_clk = {</div><div class='add'>+	.halt_reg = 0x900c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x900c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_cg_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_dma_clk = {</div><div class='add'>+	.halt_reg = 0x902c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x902c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_dma_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_dma_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_dma_noc_clk = {</div><div class='add'>+	.halt_reg = 0xf004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_dma_noc_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_dma_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_fast_clk = {</div><div class='add'>+	.halt_reg = 0x9014,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_fast_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_fast_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_fast_div2_clk = {</div><div class='add'>+	.halt_reg = 0x901c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x901c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_fast_div2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_fast_div2_noc_clk = {</div><div class='add'>+	.halt_reg = 0xf008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xf008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_fast_div2_noc_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_fr_clk = {</div><div class='add'>+	.halt_reg = 0x9004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_fr_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_ecpri_oran_div2_clk = {</div><div class='add'>+	.halt_reg = 0x9024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_ecpri_oran_div2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_oran_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_c2c0_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x80cc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80cc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_c2c0_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x80d0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80d0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_c2c1_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8410,</div><div class='add'>+	.mem_ack_reg = 0x8424,</div><div class='add'>+	.mem_enable_ack_mask = BIT(0),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80b4,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80b4,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8410,</div><div class='add'>+	.mem_ack_reg = 0x8424,</div><div class='add'>+	.mem_enable_ack_mask = BIT(1),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80bc,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80bc,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8410,</div><div class='add'>+	.mem_ack_reg = 0x8424,</div><div class='add'>+	.mem_enable_ack_mask = BIT(4),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80ac,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80ac,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8414,</div><div class='add'>+	.mem_ack_reg = 0x8428,</div><div class='add'>+	.mem_enable_ack_mask = BIT(0),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80d8,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80d8,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8414,</div><div class='add'>+	.mem_ack_reg = 0x8428,</div><div class='add'>+	.mem_enable_ack_mask = BIT(1),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80e0,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80e0,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x80f0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80f0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(0),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x800c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x800c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(1),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8014,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8014,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(2),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x801c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x801c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(3),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8024,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8024,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x8034,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x8034,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_fh_0_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(0),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8044,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8044,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(1),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x804c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x804c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(2),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8054,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8054,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(3),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x805c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x805c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x806c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x806c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_fh_1_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(0),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x807c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x807c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(1),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8084,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8084,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(2),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x808c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x808c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(3),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8094,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8094,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = {</div><div class='add'>+	.halt_reg = 0x80a4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_100g_fh_2_udp_fifo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(4),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8004,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8004,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_macsec_0_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(4),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x803c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x803c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_macsec_1_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(4),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8074,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8074,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_fh_macsec_2_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8410,</div><div class='add'>+	.mem_ack_reg = 0x8424,</div><div class='add'>+	.mem_enable_ack_mask = BIT(5),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80c4,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80c4,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8414,</div><div class='add'>+	.mem_ack_reg = 0x8428,</div><div class='add'>+	.mem_enable_ack_mask = BIT(5),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x80e8,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x80e8,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(5),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x802c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x802c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841c,</div><div class='add'>+	.mem_enable_ack_mask = BIT(5),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x8064,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x8064,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(5),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0x809c,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0x809c,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk",</div><div class='add'>+				.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+					&amp;ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr.hw,</div><div class='add'>+				},</div><div class='add'>+				.num_parents = 1,</div><div class='add'>+				.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_dbg_nfapi_axi_clk = {</div><div class='add'>+	.halt_reg = 0x80f4,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80f4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_dbg_nfapi_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_dma_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = {</div><div class='add'>+	.halt_reg = 0x80fc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x80fc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_eth_dbg_noc_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_mss_emac_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8404,</div><div class='add'>+	.mem_ack_reg = 0x8418,</div><div class='add'>+	.mem_enable_ack_mask = BIT(6),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0xd140,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0xd140,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_phy_0_ock_sram_clk",</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8408,</div><div class='add'>+	.mem_ack_reg = 0x841C,</div><div class='add'>+	.mem_enable_ack_mask = BIT(6),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0xd148,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0xd148,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_phy_1_ock_sram_clk",</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {</div><div class='add'>+	.mem_enable_reg = 0x840c,</div><div class='add'>+	.mem_ack_reg = 0x8420,</div><div class='add'>+	.mem_enable_ack_mask = BIT(6),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0xd150,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0xd150,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_phy_2_ock_sram_clk",</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8410,</div><div class='add'>+	.mem_ack_reg = 0x8424,</div><div class='add'>+	.mem_enable_ack_mask = BIT(6),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0xd158,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0xd158,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_phy_3_ock_sram_clk",</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {</div><div class='add'>+	.mem_enable_reg = 0x8414,</div><div class='add'>+	.mem_ack_reg = 0x8428,</div><div class='add'>+	.mem_enable_ack_mask = BIT(6),</div><div class='add'>+	.branch = {</div><div class='add'>+		.halt_reg = 0xd160,</div><div class='add'>+		.halt_check = BRANCH_HALT,</div><div class='add'>+		.clkr = {</div><div class='add'>+			.enable_reg = 0xd160,</div><div class='add'>+			.enable_mask = BIT(0),</div><div class='add'>+			.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+				.name = "ecpri_cc_eth_phy_4_ock_sram_clk",</div><div class='add'>+				.ops = &amp;clk_branch2_mem_ops,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_mss_emac_clk = {</div><div class='add'>+	.halt_reg = 0xe008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xe008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_mss_emac_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_mss_emac_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_mss_oran_clk = {</div><div class='add'>+	.halt_reg = 0xe004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xe004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_mss_oran_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;ecpri_cc_ecpri_oran_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane0_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane0_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane0_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd050,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd050,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane0_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane1_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane1_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane1_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane1_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane2_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane2_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane2_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd058,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd058,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane2_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane3_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd00c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd00c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane3_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy0_lane3_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd05c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd05c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy0_lane3_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane0_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane0_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane0_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane0_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane1_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd014,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane1_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane1_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane1_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane2_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane2_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane2_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd068,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane2_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane3_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd01c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd01c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane3_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy1_lane3_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd06c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd06c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy1_lane3_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane0_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd020,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane0_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane0_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd070,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd070,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane0_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane1_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane1_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane1_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd074,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd074,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane1_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane2_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane2_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane2_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd078,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd078,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane2_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane3_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd02c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd02c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane3_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy2_lane3_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd07c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd07c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy2_lane3_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane0_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd030,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd030,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane0_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane0_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd080,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd080,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane0_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane1_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd034,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd034,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane1_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane1_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd084,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd084,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane1_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane2_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd038,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd038,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane2_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane2_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd088,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane2_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane3_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd03c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd03c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane3_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy3_lane3_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd08c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd08c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy3_lane3_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane0_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd040,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane0_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane0_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd090,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane0_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane1_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane1_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane1_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd094,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd094,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane1_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane2_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd048,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd048,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane2_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane2_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd098,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd098,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane2_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane3_rx_clk = {</div><div class='add'>+	.halt_reg = 0xd04c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd04c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane3_rx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch ecpri_cc_phy4_lane3_tx_clk = {</div><div class='add'>+	.halt_reg = 0xd09c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xd09c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "ecpri_cc_phy4_lane3_tx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *ecpri_cc_qdu1000_clocks[] = {</div><div class='add'>+	[ECPRI_CC_ECPRI_CG_CLK] = &amp;ecpri_cc_ecpri_cg_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_CLK_SRC] = &amp;ecpri_cc_ecpri_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_DMA_CLK] = &amp;ecpri_cc_ecpri_dma_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_DMA_CLK_SRC] = &amp;ecpri_cc_ecpri_dma_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_DMA_NOC_CLK] = &amp;ecpri_cc_ecpri_dma_noc_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FAST_CLK] = &amp;ecpri_cc_ecpri_fast_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FAST_CLK_SRC] = &amp;ecpri_cc_ecpri_fast_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FAST_DIV2_CLK] = &amp;ecpri_cc_ecpri_fast_div2_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC] = &amp;ecpri_cc_ecpri_fast_div2_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK] = &amp;ecpri_cc_ecpri_fast_div2_noc_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_FR_CLK] = &amp;ecpri_cc_ecpri_fr_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_ORAN_CLK_SRC] = &amp;ecpri_cc_ecpri_oran_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ECPRI_ORAN_DIV2_CLK] = &amp;ecpri_cc_ecpri_oran_div2_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC] = &amp;ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_c2c0_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_c2c1_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK] = &amp;ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK] = &amp;ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK] = &amp;ecpri_cc_eth_100g_c2c_hm_macsec_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC] = &amp;ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC] = &amp;ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC] = &amp;ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK] = &amp;ecpri_cc_eth_100g_fh_0_hm_ff_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK] = &amp;ecpri_cc_eth_100g_fh_0_hm_ff_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK] = &amp;ecpri_cc_eth_100g_fh_0_hm_ff_2_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK] = &amp;ecpri_cc_eth_100g_fh_0_hm_ff_3_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_fh_0_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK] = &amp;ecpri_cc_eth_100g_fh_1_hm_ff_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK] = &amp;ecpri_cc_eth_100g_fh_1_hm_ff_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK] = &amp;ecpri_cc_eth_100g_fh_1_hm_ff_2_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK] = &amp;ecpri_cc_eth_100g_fh_1_hm_ff_3_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_fh_1_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK] = &amp;ecpri_cc_eth_100g_fh_2_hm_ff_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK] = &amp;ecpri_cc_eth_100g_fh_2_hm_ff_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK] = &amp;ecpri_cc_eth_100g_fh_2_hm_ff_2_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK] = &amp;ecpri_cc_eth_100g_fh_2_hm_ff_3_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK] = &amp;ecpri_cc_eth_100g_fh_2_udp_fifo_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK] = &amp;ecpri_cc_eth_100g_fh_macsec_0_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK] = &amp;ecpri_cc_eth_100g_fh_macsec_1_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK] = &amp;ecpri_cc_eth_100g_fh_macsec_2_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK] = &amp;ecpri_cc_eth_100g_mac_c2c_hm_ref_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC] = &amp;ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC] =</div><div class='add'>+		&amp;ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK] = &amp;ecpri_cc_eth_100g_mac_fh0_hm_ref_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC] = &amp;ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK] = &amp;ecpri_cc_eth_100g_mac_fh1_hm_ref_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC] = &amp;ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK] = &amp;ecpri_cc_eth_100g_mac_fh2_hm_ref_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC] = &amp;ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK] = &amp;ecpri_cc_eth_dbg_nfapi_axi_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_DBG_NOC_AXI_CLK] = &amp;ecpri_cc_eth_dbg_noc_axi_clk.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK] = &amp;ecpri_cc_eth_phy_0_ock_sram_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK] = &amp;ecpri_cc_eth_phy_1_ock_sram_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK] = &amp;ecpri_cc_eth_phy_2_ock_sram_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK] = &amp;ecpri_cc_eth_phy_3_ock_sram_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK] = &amp;ecpri_cc_eth_phy_4_ock_sram_clk.branch.clkr,</div><div class='add'>+	[ECPRI_CC_MSS_EMAC_CLK] = &amp;ecpri_cc_mss_emac_clk.clkr,</div><div class='add'>+	[ECPRI_CC_MSS_EMAC_CLK_SRC] = &amp;ecpri_cc_mss_emac_clk_src.clkr,</div><div class='add'>+	[ECPRI_CC_MSS_ORAN_CLK] = &amp;ecpri_cc_mss_oran_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE0_RX_CLK] = &amp;ecpri_cc_phy0_lane0_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE0_TX_CLK] = &amp;ecpri_cc_phy0_lane0_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE1_RX_CLK] = &amp;ecpri_cc_phy0_lane1_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE1_TX_CLK] = &amp;ecpri_cc_phy0_lane1_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE2_RX_CLK] = &amp;ecpri_cc_phy0_lane2_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE2_TX_CLK] = &amp;ecpri_cc_phy0_lane2_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE3_RX_CLK] = &amp;ecpri_cc_phy0_lane3_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY0_LANE3_TX_CLK] = &amp;ecpri_cc_phy0_lane3_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE0_RX_CLK] = &amp;ecpri_cc_phy1_lane0_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE0_TX_CLK] = &amp;ecpri_cc_phy1_lane0_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE1_RX_CLK] = &amp;ecpri_cc_phy1_lane1_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE1_TX_CLK] = &amp;ecpri_cc_phy1_lane1_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE2_RX_CLK] = &amp;ecpri_cc_phy1_lane2_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE2_TX_CLK] = &amp;ecpri_cc_phy1_lane2_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE3_RX_CLK] = &amp;ecpri_cc_phy1_lane3_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY1_LANE3_TX_CLK] = &amp;ecpri_cc_phy1_lane3_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE0_RX_CLK] = &amp;ecpri_cc_phy2_lane0_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE0_TX_CLK] = &amp;ecpri_cc_phy2_lane0_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE1_RX_CLK] = &amp;ecpri_cc_phy2_lane1_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE1_TX_CLK] = &amp;ecpri_cc_phy2_lane1_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE2_RX_CLK] = &amp;ecpri_cc_phy2_lane2_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE2_TX_CLK] = &amp;ecpri_cc_phy2_lane2_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE3_RX_CLK] = &amp;ecpri_cc_phy2_lane3_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY2_LANE3_TX_CLK] = &amp;ecpri_cc_phy2_lane3_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE0_RX_CLK] = &amp;ecpri_cc_phy3_lane0_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE0_TX_CLK] = &amp;ecpri_cc_phy3_lane0_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE1_RX_CLK] = &amp;ecpri_cc_phy3_lane1_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE1_TX_CLK] = &amp;ecpri_cc_phy3_lane1_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE2_RX_CLK] = &amp;ecpri_cc_phy3_lane2_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE2_TX_CLK] = &amp;ecpri_cc_phy3_lane2_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE3_RX_CLK] = &amp;ecpri_cc_phy3_lane3_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY3_LANE3_TX_CLK] = &amp;ecpri_cc_phy3_lane3_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE0_RX_CLK] = &amp;ecpri_cc_phy4_lane0_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE0_TX_CLK] = &amp;ecpri_cc_phy4_lane0_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE1_RX_CLK] = &amp;ecpri_cc_phy4_lane1_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE1_TX_CLK] = &amp;ecpri_cc_phy4_lane1_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE2_RX_CLK] = &amp;ecpri_cc_phy4_lane2_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE2_TX_CLK] = &amp;ecpri_cc_phy4_lane2_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE3_RX_CLK] = &amp;ecpri_cc_phy4_lane3_rx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PHY4_LANE3_TX_CLK] = &amp;ecpri_cc_phy4_lane3_tx_clk.clkr,</div><div class='add'>+	[ECPRI_CC_PLL0] = &amp;ecpri_cc_pll0.clkr,</div><div class='add'>+	[ECPRI_CC_PLL1] = &amp;ecpri_cc_pll1.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map ecpri_cc_qdu1000_resets[] = {</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR] = { 0x9000 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR] = { 0x80a8 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR] = { 0x8000 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR] = { 0x8038 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR] = { 0x8070 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR] = { 0x8104 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR] = { 0xe000 },</div><div class='add'>+	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR] = { 0xf000 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config ecpri_cc_qdu1000_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x31bf0,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_cc_desc ecpri_cc_qdu1000_desc = {</div><div class='add'>+	.config = &amp;ecpri_cc_qdu1000_regmap_config,</div><div class='add'>+	.clks = ecpri_cc_qdu1000_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(ecpri_cc_qdu1000_clocks),</div><div class='add'>+	.resets = ecpri_cc_qdu1000_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(ecpri_cc_qdu1000_resets),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ecpri_cc_qdu1000_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,qdu1000-ecpricc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ecpri_cc_qdu1000_match_table);</div><div class='add'>+</div><div class='add'>+static int ecpri_cc_qdu1000_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;ecpri_cc_qdu1000_desc);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+</div><div class='add'>+	clk_lucid_evo_pll_configure(&amp;ecpri_cc_pll0, regmap, &amp;ecpri_cc_pll0_config);</div><div class='add'>+	clk_lucid_evo_pll_configure(&amp;ecpri_cc_pll1, regmap, &amp;ecpri_cc_pll1_config);</div><div class='add'>+</div><div class='add'>+	return qcom_cc_really_probe(pdev, &amp;ecpri_cc_qdu1000_desc, regmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver ecpri_cc_qdu1000_driver = {</div><div class='add'>+	.probe = ecpri_cc_qdu1000_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "ecpri_cc-qdu1000",</div><div class='add'>+		.of_match_table = ecpri_cc_qdu1000_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_platform_driver(ecpri_cc_qdu1000_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI ECPRICC QDU1000 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c<br/>index b45f97c07eeb..7b9a3e99b589 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-msm8939.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/gcc-msm8939.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-msm8939.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-msm8939.c</a></div><div class='hunk'>@@ -696,7 +696,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {</div><div class='add'>+static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = {</div><div class='ctx'> 	F(100000000, P_GPLL0, 8, 0,	0),</div><div class='ctx'> 	F(200000000, P_GPLL0, 4, 0,	0),</div><div class='ctx'> 	{ }</div><div class='hunk'>@@ -706,7 +706,7 @@ static struct clk_rcg2 csi0_clk_src = {</div><div class='ctx'> 	.cmd_rcgr = 0x4e020,</div><div class='ctx'> 	.hid_width = 5,</div><div class='ctx'> 	.parent_map = gcc_xo_gpll0_map,</div><div class='del'>-	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,</div><div class='add'>+	.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,</div><div class='ctx'> 	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='ctx'> 		.name = "csi0_clk_src",</div><div class='ctx'> 		.parent_data = gcc_xo_gpll0_parent_data,</div><div class='hunk'>@@ -719,7 +719,7 @@ static struct clk_rcg2 csi1_clk_src = {</div><div class='ctx'> 	.cmd_rcgr = 0x4f020,</div><div class='ctx'> 	.hid_width = 5,</div><div class='ctx'> 	.parent_map = gcc_xo_gpll0_map,</div><div class='del'>-	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,</div><div class='add'>+	.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,</div><div class='ctx'> 	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='ctx'> 		.name = "csi1_clk_src",</div><div class='ctx'> 		.parent_data = gcc_xo_gpll0_parent_data,</div><div class='hunk'>@@ -728,6 +728,19 @@ static struct clk_rcg2 csi1_clk_src = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_rcg2 csi2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x3c020,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_xo_gpll0_map,</div><div class='add'>+	.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "csi2_clk_src",</div><div class='add'>+		.parent_data = gcc_xo_gpll0_parent_data,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),</div><div class='add'>+		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {</div><div class='ctx'> 	F(19200000, P_XO, 1, 0, 0),</div><div class='ctx'> 	F(50000000, P_GPLL0, 16, 0, 0),</div><div class='hunk'>@@ -2385,6 +2398,91 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_branch gcc_camss_csi2_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x3c040,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3c040,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_camss_csi2_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;camss_ahb_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camss_csi2_clk = {</div><div class='add'>+	.halt_reg = 0x3c03c,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3c03c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_camss_csi2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;csi2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camss_csi2phy_clk = {</div><div class='add'>+	.halt_reg = 0x3c048,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3c048,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_camss_csi2phy_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;csi2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camss_csi2pix_clk = {</div><div class='add'>+	.halt_reg = 0x3c058,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3c058,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_camss_csi2pix_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;csi2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camss_csi2rdi_clk = {</div><div class='add'>+	.halt_reg = 0x3c050,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3c050,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_camss_csi2rdi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;csi2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct clk_branch gcc_camss_csi_vfe0_clk = {</div><div class='ctx'> 	.halt_reg = 0x58050,</div><div class='ctx'> 	.clkr = {</div><div class='hunk'>@@ -3682,6 +3780,7 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {</div><div class='ctx'> 	[APSS_AHB_CLK_SRC] = &amp;apss_ahb_clk_src.clkr,</div><div class='ctx'> 	[CSI0_CLK_SRC] = &amp;csi0_clk_src.clkr,</div><div class='ctx'> 	[CSI1_CLK_SRC] = &amp;csi1_clk_src.clkr,</div><div class='add'>+	[CSI2_CLK_SRC] = &amp;csi2_clk_src.clkr,</div><div class='ctx'> 	[GFX3D_CLK_SRC] = &amp;gfx3d_clk_src.clkr,</div><div class='ctx'> 	[VFE0_CLK_SRC] = &amp;vfe0_clk_src.clkr,</div><div class='ctx'> 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &amp;blsp1_qup1_i2c_apps_clk_src.clkr,</div><div class='hunk'>@@ -3751,6 +3850,11 @@ static struct clk_regmap *gcc_msm8939_clocks[] = {</div><div class='ctx'> 	[GCC_CAMSS_CSI1PHY_CLK] = &amp;gcc_camss_csi1phy_clk.clkr,</div><div class='ctx'> 	[GCC_CAMSS_CSI1PIX_CLK] = &amp;gcc_camss_csi1pix_clk.clkr,</div><div class='ctx'> 	[GCC_CAMSS_CSI1RDI_CLK] = &amp;gcc_camss_csi1rdi_clk.clkr,</div><div class='add'>+	[GCC_CAMSS_CSI2_AHB_CLK] = &amp;gcc_camss_csi2_ahb_clk.clkr,</div><div class='add'>+	[GCC_CAMSS_CSI2_CLK] = &amp;gcc_camss_csi2_clk.clkr,</div><div class='add'>+	[GCC_CAMSS_CSI2PHY_CLK] = &amp;gcc_camss_csi2phy_clk.clkr,</div><div class='add'>+	[GCC_CAMSS_CSI2PIX_CLK] = &amp;gcc_camss_csi2pix_clk.clkr,</div><div class='add'>+	[GCC_CAMSS_CSI2RDI_CLK] = &amp;gcc_camss_csi2rdi_clk.clkr,</div><div class='ctx'> 	[GCC_CAMSS_CSI_VFE0_CLK] = &amp;gcc_camss_csi_vfe0_clk.clkr,</div><div class='ctx'> 	[GCC_CAMSS_GP0_CLK] = &amp;gcc_camss_gp0_clk.clkr,</div><div class='ctx'> 	[GCC_CAMSS_GP1_CLK] = &amp;gcc_camss_gp1_clk.clkr,</div><div class='head'>diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c<br/>index 586126c4dd90..b883dffe5f7a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/gcc-sm8550.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-sm8550.c</a></div><div class='hunk'>@@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_1,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -416,7 +416,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_1,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -431,7 +431,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_1,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -451,7 +451,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_2,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -471,7 +471,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -486,7 +486,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_2,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -501,7 +501,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -521,7 +521,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {</div><div class='hunk'>@@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {</div><div class='hunk'>@@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {</div><div class='hunk'>@@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {</div><div class='hunk'>@@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {</div><div class='hunk'>@@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {</div><div class='hunk'>@@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {</div><div class='hunk'>@@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {</div><div class='hunk'>@@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {</div><div class='hunk'>@@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {</div><div class='hunk'>@@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {</div><div class='hunk'>@@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {</div><div class='hunk'>@@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {</div><div class='hunk'>@@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {</div><div class='hunk'>@@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_8,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_8),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {</div><div class='hunk'>@@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {</div><div class='ctx'> 	.parent_data = gcc_parent_data_0,</div><div class='ctx'> 	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 	.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-	.ops = &amp;clk_rcg2_ops,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {</div><div class='hunk'>@@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_9,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_9),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1071,7 +1071,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1093,7 +1093,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_3,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1114,7 +1114,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_4,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_0,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {</div><div class='ctx'> 		.parent_data = gcc_parent_data_2,</div><div class='ctx'> 		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='ctx'> 		.flags = CLK_SET_RATE_PARENT,</div><div class='del'>-		.ops = &amp;clk_rcg2_ops,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -2998,38 +2998,46 @@ static struct clk_branch gcc_video_axi1_clk = {</div><div class='ctx'> </div><div class='ctx'> static struct gdsc pcie_0_gdsc = {</div><div class='ctx'> 	.gdscr = 0x6b004,</div><div class='add'>+	.collapse_ctrl = 0x52020,</div><div class='add'>+	.collapse_mask = BIT(0),</div><div class='ctx'> 	.pd = {</div><div class='ctx'> 		.name = "pcie_0_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc pcie_0_phy_gdsc = {</div><div class='ctx'> 	.gdscr = 0x6c000,</div><div class='add'>+	.collapse_ctrl = 0x52020,</div><div class='add'>+	.collapse_mask = BIT(3),</div><div class='ctx'> 	.pd = {</div><div class='ctx'> 		.name = "pcie_0_phy_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc pcie_1_gdsc = {</div><div class='ctx'> 	.gdscr = 0x8d004,</div><div class='add'>+	.collapse_ctrl = 0x52020,</div><div class='add'>+	.collapse_mask = BIT(1),</div><div class='ctx'> 	.pd = {</div><div class='ctx'> 		.name = "pcie_1_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc pcie_1_phy_gdsc = {</div><div class='ctx'> 	.gdscr = 0x8e000,</div><div class='add'>+	.collapse_ctrl = 0x52020,</div><div class='add'>+	.collapse_mask = BIT(4),</div><div class='ctx'> 	.pd = {</div><div class='ctx'> 		.name = "pcie_1_phy_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc ufs_phy_gdsc = {</div><div class='hunk'>@@ -3038,7 +3046,7 @@ static struct gdsc ufs_phy_gdsc = {</div><div class='ctx'> 		.name = "ufs_phy_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc ufs_mem_phy_gdsc = {</div><div class='hunk'>@@ -3047,7 +3055,7 @@ static struct gdsc ufs_mem_phy_gdsc = {</div><div class='ctx'> 		.name = "ufs_mem_phy_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc usb30_prim_gdsc = {</div><div class='hunk'>@@ -3056,7 +3064,7 @@ static struct gdsc usb30_prim_gdsc = {</div><div class='ctx'> 		.name = "usb30_prim_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct gdsc usb3_phy_gdsc = {</div><div class='hunk'>@@ -3065,7 +3073,7 @@ static struct gdsc usb3_phy_gdsc = {</div><div class='ctx'> 		.name = "usb3_phy_gdsc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.pwrsts = PWRSTS_OFF_ON,</div><div class='del'>-	.flags = POLL_CFG_GDSCR,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct clk_regmap *gcc_sm8550_clocks[] = {</div><div class='head'>diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c<br/>new file mode 100644<br/>index 000000000000..9174dd82308c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-sm8650.c</a></div><div class='hunk'>@@ -0,0 +1,3849 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sm8650-gcc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "clk-regmap-divider.h"</div><div class='add'>+#include "clk-regmap-mux.h"</div><div class='add'>+#include "clk-regmap-phy-mux.h"</div><div class='add'>+#include "gdsc.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+/* Need to match the order of clocks in DT binding */</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_BI_TCXO_AO,</div><div class='add'>+	DT_SLEEP_CLK,</div><div class='add'>+</div><div class='add'>+	DT_PCIE_0_PIPE,</div><div class='add'>+	DT_PCIE_1_PIPE,</div><div class='add'>+	DT_PCIE_1_PHY_AUX,</div><div class='add'>+</div><div class='add'>+	DT_UFS_PHY_RX_SYMBOL_0,</div><div class='add'>+	DT_UFS_PHY_RX_SYMBOL_1,</div><div class='add'>+	DT_UFS_PHY_TX_SYMBOL_0,</div><div class='add'>+</div><div class='add'>+	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_GCC_GPLL0_OUT_EVEN,</div><div class='add'>+	P_GCC_GPLL0_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL1_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL3_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL4_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL6_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL7_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL9_OUT_MAIN,</div><div class='add'>+	P_PCIE_0_PIPE_CLK,</div><div class='add'>+	P_PCIE_1_PHY_AUX_CLK,</div><div class='add'>+	P_PCIE_1_PIPE_CLK,</div><div class='add'>+	P_SLEEP_CLK,</div><div class='add'>+	P_UFS_PHY_RX_SYMBOL_0_CLK,</div><div class='add'>+	P_UFS_PHY_RX_SYMBOL_1_CLK,</div><div class='add'>+	P_UFS_PHY_TX_SYMBOL_0_CLK,</div><div class='add'>+	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll0_ao = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x57020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll0_ao",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO_AO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.post_div_shift = 10,</div><div class='add'>+	.post_div_table = post_div_table_gcc_gpll0_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gpll0_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_gpll0.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ole_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even_ao = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.post_div_shift = 10,</div><div class='add'>+	.post_div_table = post_div_table_gcc_gpll0_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gpll0_out_even_ao",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_gpll0_ao.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ole_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll1 = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll1",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll1_ao = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x57020,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll1_ao",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO_AO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll3 = {</div><div class='add'>+	.offset = 0x3000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll3",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll3_ao = {</div><div class='add'>+	.offset = 0x3000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x57020,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll3_ao",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO_AO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll4 = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll4",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll4_ao = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x57020,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll4_ao",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO_AO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll6 = {</div><div class='add'>+	.offset = 0x6000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll6",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll6_ao = {</div><div class='add'>+	.offset = 0x6000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x57020,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll6_ao",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO_AO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll7 = {</div><div class='add'>+	.offset = 0x7000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll7",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll9 = {</div><div class='add'>+	.offset = 0x9000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(9),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll9",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_SLEEP_CLK, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL1_OUT_MAIN, 4 },</div><div class='add'>+	{ P_GCC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll1.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll4.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_3[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_3[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll4.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_4[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_SLEEP_CLK, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_4[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_5[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_5[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_8[] = {</div><div class='add'>+	{ P_PCIE_1_PHY_AUX_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_8[] = {</div><div class='add'>+	{ .index = DT_PCIE_1_PHY_AUX },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_10[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL7_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_10[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll7.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_11[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL9_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_11[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll9.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll4.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_12[] = {</div><div class='add'>+	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_12[] = {</div><div class='add'>+	{ .index = DT_UFS_PHY_RX_SYMBOL_0 },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_13[] = {</div><div class='add'>+	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_13[] = {</div><div class='add'>+	{ .index = DT_UFS_PHY_RX_SYMBOL_1 },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_14[] = {</div><div class='add'>+	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_14[] = {</div><div class='add'>+	{ .index = DT_UFS_PHY_TX_SYMBOL_0 },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_15[] = {</div><div class='add'>+	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_15[] = {</div><div class='add'>+	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {</div><div class='add'>+	.reg = 0x6b070,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_0_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {</div><div class='add'>+	.reg = 0x8d094,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_8,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_phy_aux_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_8,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_8),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {</div><div class='add'>+	.reg = 0x8d078,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_1_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {</div><div class='add'>+	.reg = 0x77064,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_12,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_12,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_12),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {</div><div class='add'>+	.reg = 0x770e0,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_13,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_13,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_13),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {</div><div class='add'>+	.reg = 0x77054,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_14,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_14,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_14),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {</div><div class='add'>+	.reg = 0x3906c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_15,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_pipe_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_15,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_15),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {</div><div class='add'>+	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x64004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp1_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x65004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp2_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x66004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp3_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6b074,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_0_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6b058,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_0_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8d07c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_1_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8d060,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_1_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {</div><div class='add'>+	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pdm2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x33010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pdm2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pdm2_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17008,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s0_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17024,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s1_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17040,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s2_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1705c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s3_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17078,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s4_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17094,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s5_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x170b0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s6_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x170cc,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s7_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x170e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s8_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17104,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_i2c_s9_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = {</div><div class='add'>+	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),</div><div class='add'>+	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_qspi_ref_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x188a0,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_qspi_ref_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),</div><div class='add'>+	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),</div><div class='add'>+	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),</div><div class='add'>+	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s0_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18010,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s0_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s1_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18148,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s1_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s3_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18290,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s3_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s4_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x183c8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s4_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s5_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18500,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s5_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s6_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18638,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s6_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s7_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18770,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s7_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src[] = {</div><div class='add'>+	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e9d4,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap2_ibi_ctrl_0_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s0_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e010,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s0_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s1_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e148,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s1_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s2_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e280,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s2_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s3_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e3b8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s3_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s4_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e4f0,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s4_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s5_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e628,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s5_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s6_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_10,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_10),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e760,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_10,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s6_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s7_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e898,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s7_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = {</div><div class='add'>+	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),</div><div class='add'>+	F(400000000, P_GCC_GPLL0_OUT_MAIN, 1.5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap3_qspi_ref_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x19018,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap3_qspi_ref_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {</div><div class='add'>+	F(400000, P_BI_TCXO, 12, 1, 4),</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x14018,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_11,</div><div class='add'>+	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_sdcc2_apps_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_11,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_11),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {</div><div class='add'>+	F(400000, P_BI_TCXO, 12, 1, 4),</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x16018,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_sdcc4_apps_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77030,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_axi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77080,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_ice_core_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {</div><div class='add'>+	F(9600000, P_BI_TCXO, 2, 0, 0),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x770b4,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77098,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_unipro_core_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {</div><div class='add'>+	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),</div><div class='add'>+	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x3902c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x39044,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x39070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb3_prim_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {</div><div class='add'>+	.reg = 0x18280,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap1_s2_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = {</div><div class='add'>+	.reg = 0x19010,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap3_s0_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0x3905c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {</div><div class='add'>+	.halt_reg = 0x10064,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x10064,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(12),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_noc_pcie_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {</div><div class='add'>+	.halt_reg = 0x770e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770e4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770e4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_ufs_phy_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {</div><div class='add'>+	.halt_reg = 0x770e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770e4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770e4,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x3908c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x3908c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3908c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb3_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_boot_rom_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x38004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x38004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_boot_rom_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camera_hf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x26010,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x26010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x26010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_camera_hf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camera_sf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2601c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2601c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2601c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_camera_sf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x10050,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x10050,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x39088,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x39088,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb3_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x10058,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x10058,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie_sf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ddrss_gpu_axi_clk = {</div><div class='add'>+	.halt_reg = 0x71154,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x71154,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71154,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ddrss_gpu_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_aon_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {</div><div class='add'>+	.halt_reg = 0x10074,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x10074,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ddrss_pcie_sf_qtb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_disp_hf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2700c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2700c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2700c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_disp_hf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp1_clk = {</div><div class='add'>+	.halt_reg = 0x64000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x64000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp2_clk = {</div><div class='add'>+	.halt_reg = 0x65000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x65000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp3_clk = {</div><div class='add'>+	.halt_reg = 0x66000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x66000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_gpll0_clk_src = {</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_gpll0_clk_src",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gpll0.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_gpll0_div_clk_src",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gpll0_out_even.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {</div><div class='add'>+	.halt_reg = 0x71010,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x71010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_memnoc_gfx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {</div><div class='add'>+	.halt_reg = 0x71018,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_snoc_dvm_gfx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_aux_clk = {</div><div class='add'>+	.halt_reg = 0x6b03c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_0_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x6b038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x6b038,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b02c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x6b02c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x6b054,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_0_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x6b048,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_0_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b020,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x6b020,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8d038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x8d034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x8d034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x8d028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8d044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x8d05c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x8d050,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x8d01c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm2_clk = {</div><div class='add'>+	.halt_reg = 0x3300c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3300c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pdm2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x33004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x33004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x33004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm_xo4_clk = {</div><div class='add'>+	.halt_reg = 0x33008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x33008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm_xo4_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x26008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x26008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x26008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_camera_nrt_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2600c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2600c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2600c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_camera_rt_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_disp_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x27008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x27008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x27008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_disp_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_gpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x71008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x71008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_gpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_pcie_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x6b018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x6b018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(11),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_pcie_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32014,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32014,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_cv_cpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_cvp_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32010,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_v_cpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x3200c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x3200c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3200c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_vcodec_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_core_clk = {</div><div class='add'>+	.halt_reg = 0x23004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(8),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s0_clk = {</div><div class='add'>+	.halt_reg = 0x17004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s1_clk = {</div><div class='add'>+	.halt_reg = 0x17020,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(11),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s2_clk = {</div><div class='add'>+	.halt_reg = 0x1703c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(12),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s3_clk = {</div><div class='add'>+	.halt_reg = 0x17058,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(13),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s4_clk = {</div><div class='add'>+	.halt_reg = 0x17074,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(14),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s5_clk = {</div><div class='add'>+	.halt_reg = 0x17090,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s6_clk = {</div><div class='add'>+	.halt_reg = 0x170ac,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s7_clk = {</div><div class='add'>+	.halt_reg = 0x170c8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s8_clk = {</div><div class='add'>+	.halt_reg = 0x170e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(14),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s8_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s8_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s9_clk = {</div><div class='add'>+	.halt_reg = 0x17100,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s9_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_i2c_s9_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23000,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23000,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_i2c_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x23154,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(18),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_core_clk = {</div><div class='add'>+	.halt_reg = 0x23144,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {</div><div class='add'>+	.halt_reg = 0x1889c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_qspi_ref_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {</div><div class='add'>+	.halt_reg = 0x18004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {</div><div class='add'>+	.halt_reg = 0x1813c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {</div><div class='add'>+	.halt_reg = 0x18274,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {</div><div class='add'>+	.halt_reg = 0x18284,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {</div><div class='add'>+	.halt_reg = 0x183bc,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {</div><div class='add'>+	.halt_reg = 0x184f4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {</div><div class='add'>+	.halt_reg = 0x1862c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s7_clk = {</div><div class='add'>+	.halt_reg = 0x18764,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x232a4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_core_clk = {</div><div class='add'>+	.halt_reg = 0x23294,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_2_clk = {</div><div class='add'>+	.halt_reg = 0x1e9cc,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1e9cc,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_ibi_ctrl_2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_3_clk = {</div><div class='add'>+	.halt_reg = 0x1e9d0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1e9d0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_ibi_ctrl_3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s0_clk = {</div><div class='add'>+	.halt_reg = 0x1e004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s1_clk = {</div><div class='add'>+	.halt_reg = 0x1e13c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s2_clk = {</div><div class='add'>+	.halt_reg = 0x1e274,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s3_clk = {</div><div class='add'>+	.halt_reg = 0x1e3ac,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s4_clk = {</div><div class='add'>+	.halt_reg = 0x1e4e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(8),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s5_clk = {</div><div class='add'>+	.halt_reg = 0x1e61c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(9),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s6_clk = {</div><div class='add'>+	.halt_reg = 0x1e754,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s7_clk = {</div><div class='add'>+	.halt_reg = 0x1e88c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x233f4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap3_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap3_core_clk = {</div><div class='add'>+	.halt_reg = 0x233e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap3_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = {</div><div class='add'>+	.halt_reg = 0x19014,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap3_qspi_ref_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap3_s0_clk = {</div><div class='add'>+	.halt_reg = 0x19004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap3_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap3_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2313c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2313c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_1_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23140,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23140,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_1_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_ibi_2_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x1e9c4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1e9c4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_ibi_2_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_ibi_3_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x1e9c8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1e9c8,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_ibi_3_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2328c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2328c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23290,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23290,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x233dc,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x233dc,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_3_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x233e0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x233e0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(31),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_3_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc2_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x14010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x14010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc2_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc2_apps_clk = {</div><div class='add'>+	.halt_reg = 0x14004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x14004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc2_apps_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_sdcc2_apps_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc4_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x16010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x16010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc4_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc4_apps_clk = {</div><div class='add'>+	.halt_reg = 0x16004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x16004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc4_apps_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_sdcc4_apps_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x77024,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77024,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_axi_clk = {</div><div class='add'>+	.halt_reg = 0x77018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {</div><div class='add'>+	.halt_reg = 0x77018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77018,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_axi_hw_ctl_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_ice_core_clk = {</div><div class='add'>+	.halt_reg = 0x77074,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77074,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77074,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_ice_core_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_ice_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {</div><div class='add'>+	.halt_reg = 0x77074,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77074,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77074,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_ice_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x770b0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770b0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {</div><div class='add'>+	.halt_reg = 0x770b0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770b0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770b0,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {</div><div class='add'>+	.halt_reg = 0x7702c,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7702c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {</div><div class='add'>+	.halt_reg = 0x770cc,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770cc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {</div><div class='add'>+	.halt_reg = 0x77028,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_tx_symbol_0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {</div><div class='add'>+	.halt_reg = 0x77068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_unipro_core_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_unipro_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {</div><div class='add'>+	.halt_reg = 0x77068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77068,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_unipro_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_master_clk = {</div><div class='add'>+	.halt_reg = 0x39018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0x39028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_sleep_clk = {</div><div class='add'>+	.halt_reg = 0x39024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x39060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {</div><div class='add'>+	.halt_reg = 0x39064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_com_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x39068,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.hwcg_reg = 0x39068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_video_axi0_clk = {</div><div class='add'>+	.halt_reg = 0x32018,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x32018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_video_axi0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_video_axi1_clk = {</div><div class='add'>+	.halt_reg = 0x32024,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x32024,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_video_axi1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc pcie_0_gdsc = {</div><div class='add'>+	.gdscr = 0x6b004,</div><div class='add'>+	.collapse_ctrl = 0x5214c,</div><div class='add'>+	.collapse_mask = BIT(0),</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "pcie_0_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc pcie_0_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x6c000,</div><div class='add'>+	.collapse_ctrl = 0x5214c,</div><div class='add'>+	.collapse_mask = BIT(3),</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "pcie_0_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc pcie_1_gdsc = {</div><div class='add'>+	.gdscr = 0x8d004,</div><div class='add'>+	.collapse_ctrl = 0x5214c,</div><div class='add'>+	.collapse_mask = BIT(1),</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "pcie_1_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc pcie_1_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x8e000,</div><div class='add'>+	.collapse_ctrl = 0x5214c,</div><div class='add'>+	.collapse_mask = BIT(4),</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "pcie_1_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ufs_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x77004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ufs_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc ufs_mem_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x9e000,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "ufs_mem_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc usb30_prim_gdsc = {</div><div class='add'>+	.gdscr = 0x39004,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "usb30_prim_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc usb3_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x50018,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "usb3_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *gcc_sm8650_clocks[] = {</div><div class='add'>+	[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &amp;gcc_aggre_noc_pcie_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &amp;gcc_aggre_ufs_phy_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &amp;gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &amp;gcc_aggre_usb3_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_BOOT_ROM_AHB_CLK] = &amp;gcc_boot_rom_ahb_clk.clkr,</div><div class='add'>+	[GCC_CAMERA_HF_AXI_CLK] = &amp;gcc_camera_hf_axi_clk.clkr,</div><div class='add'>+	[GCC_CAMERA_SF_AXI_CLK] = &amp;gcc_camera_sf_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &amp;gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &amp;gcc_cfg_noc_usb3_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE_SF_AXI_CLK] = &amp;gcc_cnoc_pcie_sf_axi_clk.clkr,</div><div class='add'>+	[GCC_DDRSS_GPU_AXI_CLK] = &amp;gcc_ddrss_gpu_axi_clk.clkr,</div><div class='add'>+	[GCC_DDRSS_PCIE_SF_QTB_CLK] = &amp;gcc_ddrss_pcie_sf_qtb_clk.clkr,</div><div class='add'>+	[GCC_DISP_HF_AXI_CLK] = &amp;gcc_disp_hf_axi_clk.clkr,</div><div class='add'>+	[GCC_GP1_CLK] = &amp;gcc_gp1_clk.clkr,</div><div class='add'>+	[GCC_GP1_CLK_SRC] = &amp;gcc_gp1_clk_src.clkr,</div><div class='add'>+	[GCC_GP2_CLK] = &amp;gcc_gp2_clk.clkr,</div><div class='add'>+	[GCC_GP2_CLK_SRC] = &amp;gcc_gp2_clk_src.clkr,</div><div class='add'>+	[GCC_GP3_CLK] = &amp;gcc_gp3_clk.clkr,</div><div class='add'>+	[GCC_GP3_CLK_SRC] = &amp;gcc_gp3_clk_src.clkr,</div><div class='add'>+	[GCC_GPLL0] = &amp;gcc_gpll0.clkr,</div><div class='add'>+	[GCC_GPLL0_OUT_EVEN] = &amp;gcc_gpll0_out_even.clkr,</div><div class='add'>+	[GCC_GPLL1] = &amp;gcc_gpll1.clkr,</div><div class='add'>+	[GCC_GPLL3] = &amp;gcc_gpll3.clkr,</div><div class='add'>+	[GCC_GPLL4] = &amp;gcc_gpll4.clkr,</div><div class='add'>+	[GCC_GPLL6] = &amp;gcc_gpll6.clkr,</div><div class='add'>+	[GCC_GPLL7] = &amp;gcc_gpll7.clkr,</div><div class='add'>+	[GCC_GPLL9] = &amp;gcc_gpll9.clkr,</div><div class='add'>+	[GCC_GPU_GPLL0_CLK_SRC] = &amp;gcc_gpu_gpll0_clk_src.clkr,</div><div class='add'>+	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &amp;gcc_gpu_gpll0_div_clk_src.clkr,</div><div class='add'>+	[GCC_GPU_MEMNOC_GFX_CLK] = &amp;gcc_gpu_memnoc_gfx_clk.clkr,</div><div class='add'>+	[GCC_GPU_SNOC_DVM_GFX_CLK] = &amp;gcc_gpu_snoc_dvm_gfx_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_AUX_CLK] = &amp;gcc_pcie_0_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_AUX_CLK_SRC] = &amp;gcc_pcie_0_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_0_CFG_AHB_CLK] = &amp;gcc_pcie_0_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_MSTR_AXI_CLK] = &amp;gcc_pcie_0_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_PHY_RCHNG_CLK] = &amp;gcc_pcie_0_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_0_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_0_PIPE_CLK] = &amp;gcc_pcie_0_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_PIPE_CLK_SRC] = &amp;gcc_pcie_0_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_0_SLV_AXI_CLK] = &amp;gcc_pcie_0_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_0_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_AUX_CLK] = &amp;gcc_pcie_1_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_AUX_CLK_SRC] = &amp;gcc_pcie_1_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_CFG_AHB_CLK] = &amp;gcc_pcie_1_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_MSTR_AXI_CLK] = &amp;gcc_pcie_1_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_PHY_AUX_CLK] = &amp;gcc_pcie_1_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &amp;gcc_pcie_1_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_PHY_RCHNG_CLK] = &amp;gcc_pcie_1_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_1_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_PIPE_CLK] = &amp;gcc_pcie_1_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_PIPE_CLK_SRC] = &amp;gcc_pcie_1_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_SLV_AXI_CLK] = &amp;gcc_pcie_1_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_1_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PDM2_CLK] = &amp;gcc_pdm2_clk.clkr,</div><div class='add'>+	[GCC_PDM2_CLK_SRC] = &amp;gcc_pdm2_clk_src.clkr,</div><div class='add'>+	[GCC_PDM_AHB_CLK] = &amp;gcc_pdm_ahb_clk.clkr,</div><div class='add'>+	[GCC_PDM_XO4_CLK] = &amp;gcc_pdm_xo4_clk.clkr,</div><div class='add'>+	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &amp;gcc_qmip_camera_nrt_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &amp;gcc_qmip_camera_rt_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_DISP_AHB_CLK] = &amp;gcc_qmip_disp_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_GPU_AHB_CLK] = &amp;gcc_qmip_gpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_PCIE_AHB_CLK] = &amp;gcc_qmip_pcie_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &amp;gcc_qmip_video_cv_cpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &amp;gcc_qmip_video_cvp_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &amp;gcc_qmip_video_v_cpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &amp;gcc_qmip_video_vcodec_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_CORE_CLK] = &amp;gcc_qupv3_i2c_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S0_CLK] = &amp;gcc_qupv3_i2c_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S0_CLK_SRC] = &amp;gcc_qupv3_i2c_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S1_CLK] = &amp;gcc_qupv3_i2c_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S1_CLK_SRC] = &amp;gcc_qupv3_i2c_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S2_CLK] = &amp;gcc_qupv3_i2c_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S2_CLK_SRC] = &amp;gcc_qupv3_i2c_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S3_CLK] = &amp;gcc_qupv3_i2c_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S3_CLK_SRC] = &amp;gcc_qupv3_i2c_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S4_CLK] = &amp;gcc_qupv3_i2c_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S4_CLK_SRC] = &amp;gcc_qupv3_i2c_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S5_CLK] = &amp;gcc_qupv3_i2c_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S5_CLK_SRC] = &amp;gcc_qupv3_i2c_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S6_CLK] = &amp;gcc_qupv3_i2c_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S6_CLK_SRC] = &amp;gcc_qupv3_i2c_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S7_CLK] = &amp;gcc_qupv3_i2c_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S7_CLK_SRC] = &amp;gcc_qupv3_i2c_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S8_CLK] = &amp;gcc_qupv3_i2c_s8_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S8_CLK_SRC] = &amp;gcc_qupv3_i2c_s8_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S9_CLK] = &amp;gcc_qupv3_i2c_s9_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S9_CLK_SRC] = &amp;gcc_qupv3_i2c_s9_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_I2C_S_AHB_CLK] = &amp;gcc_qupv3_i2c_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &amp;gcc_qupv3_wrap1_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_CORE_CLK] = &amp;gcc_qupv3_wrap1_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &amp;gcc_qupv3_wrap1_qspi_ref_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &amp;gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S0_CLK] = &amp;gcc_qupv3_wrap1_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &amp;gcc_qupv3_wrap1_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S1_CLK] = &amp;gcc_qupv3_wrap1_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &amp;gcc_qupv3_wrap1_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S2_CLK] = &amp;gcc_qupv3_wrap1_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &amp;gcc_qupv3_wrap1_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S3_CLK] = &amp;gcc_qupv3_wrap1_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &amp;gcc_qupv3_wrap1_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S4_CLK] = &amp;gcc_qupv3_wrap1_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &amp;gcc_qupv3_wrap1_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S5_CLK] = &amp;gcc_qupv3_wrap1_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &amp;gcc_qupv3_wrap1_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S6_CLK] = &amp;gcc_qupv3_wrap1_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &amp;gcc_qupv3_wrap1_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S7_CLK] = &amp;gcc_qupv3_wrap1_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &amp;gcc_qupv3_wrap1_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &amp;gcc_qupv3_wrap2_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_CORE_CLK] = &amp;gcc_qupv3_wrap2_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC] = &amp;gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK] = &amp;gcc_qupv3_wrap2_ibi_ctrl_2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK] = &amp;gcc_qupv3_wrap2_ibi_ctrl_3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S0_CLK] = &amp;gcc_qupv3_wrap2_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &amp;gcc_qupv3_wrap2_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S1_CLK] = &amp;gcc_qupv3_wrap2_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &amp;gcc_qupv3_wrap2_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S2_CLK] = &amp;gcc_qupv3_wrap2_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &amp;gcc_qupv3_wrap2_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S3_CLK] = &amp;gcc_qupv3_wrap2_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &amp;gcc_qupv3_wrap2_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S4_CLK] = &amp;gcc_qupv3_wrap2_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &amp;gcc_qupv3_wrap2_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S5_CLK] = &amp;gcc_qupv3_wrap2_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &amp;gcc_qupv3_wrap2_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S6_CLK] = &amp;gcc_qupv3_wrap2_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &amp;gcc_qupv3_wrap2_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S7_CLK] = &amp;gcc_qupv3_wrap2_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &amp;gcc_qupv3_wrap2_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &amp;gcc_qupv3_wrap3_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_CORE_CLK] = &amp;gcc_qupv3_wrap3_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &amp;gcc_qupv3_wrap3_qspi_ref_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &amp;gcc_qupv3_wrap3_qspi_ref_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_S0_CLK] = &amp;gcc_qupv3_wrap3_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &amp;gcc_qupv3_wrap3_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &amp;gcc_qupv3_wrap_1_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &amp;gcc_qupv3_wrap_1_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK] = &amp;gcc_qupv3_wrap_2_ibi_2_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK] = &amp;gcc_qupv3_wrap_2_ibi_3_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &amp;gcc_qupv3_wrap_2_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &amp;gcc_qupv3_wrap_2_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_3_M_AHB_CLK] = &amp;gcc_qupv3_wrap_3_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_3_S_AHB_CLK] = &amp;gcc_qupv3_wrap_3_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_AHB_CLK] = &amp;gcc_sdcc2_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_APPS_CLK] = &amp;gcc_sdcc2_apps_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_APPS_CLK_SRC] = &amp;gcc_sdcc2_apps_clk_src.clkr,</div><div class='add'>+	[GCC_SDCC4_AHB_CLK] = &amp;gcc_sdcc4_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC4_APPS_CLK] = &amp;gcc_sdcc4_apps_clk.clkr,</div><div class='add'>+	[GCC_SDCC4_APPS_CLK_SRC] = &amp;gcc_sdcc4_apps_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AHB_CLK] = &amp;gcc_ufs_phy_ahb_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AXI_CLK] = &amp;gcc_ufs_phy_axi_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AXI_CLK_SRC] = &amp;gcc_ufs_phy_axi_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &amp;gcc_ufs_phy_axi_hw_ctl_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_ICE_CORE_CLK] = &amp;gcc_ufs_phy_ice_core_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &amp;gcc_ufs_phy_ice_core_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &amp;gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_PHY_AUX_CLK] = &amp;gcc_ufs_phy_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &amp;gcc_ufs_phy_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &amp;gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &amp;gcc_ufs_phy_rx_symbol_0_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &amp;gcc_ufs_phy_rx_symbol_0_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &amp;gcc_ufs_phy_rx_symbol_1_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &amp;gcc_ufs_phy_rx_symbol_1_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &amp;gcc_ufs_phy_tx_symbol_0_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &amp;gcc_ufs_phy_tx_symbol_0_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &amp;gcc_ufs_phy_unipro_core_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &amp;gcc_ufs_phy_unipro_core_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &amp;gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MASTER_CLK] = &amp;gcc_usb30_prim_master_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &amp;gcc_usb30_prim_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &amp;gcc_usb30_prim_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb30_prim_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_SLEEP_CLK] = &amp;gcc_usb30_prim_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_AUX_CLK] = &amp;gcc_usb3_prim_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &amp;gcc_usb3_prim_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &amp;gcc_usb3_prim_phy_com_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &amp;gcc_usb3_prim_phy_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &amp;gcc_usb3_prim_phy_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_VIDEO_AXI0_CLK] = &amp;gcc_video_axi0_clk.clkr,</div><div class='add'>+	[GCC_VIDEO_AXI1_CLK] = &amp;gcc_video_axi1_clk.clkr,</div><div class='add'>+	[GCC_GPLL0_AO] = &amp;gcc_gpll0_ao.clkr,</div><div class='add'>+	[GCC_GPLL0_OUT_EVEN_AO] = &amp;gcc_gpll0_out_even_ao.clkr,</div><div class='add'>+	[GCC_GPLL1_AO] = &amp;gcc_gpll1_ao.clkr,</div><div class='add'>+	[GCC_GPLL3_AO] = &amp;gcc_gpll3_ao.clkr,</div><div class='add'>+	[GCC_GPLL4_AO] = &amp;gcc_gpll4_ao.clkr,</div><div class='add'>+	[GCC_GPLL6_AO] = &amp;gcc_gpll6_ao.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map gcc_sm8650_resets[] = {</div><div class='add'>+	[GCC_CAMERA_BCR] = { 0x26000 },</div><div class='add'>+	[GCC_DISPLAY_BCR] = { 0x27000 },</div><div class='add'>+	[GCC_GPU_BCR] = { 0x71000 },</div><div class='add'>+	[GCC_PCIE_0_BCR] = { 0x6b000 },</div><div class='add'>+	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },</div><div class='add'>+	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },</div><div class='add'>+	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },</div><div class='add'>+	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },</div><div class='add'>+	[GCC_PCIE_1_BCR] = { 0x8d000 },</div><div class='add'>+	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },</div><div class='add'>+	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },</div><div class='add'>+	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },</div><div class='add'>+	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },</div><div class='add'>+	[GCC_PCIE_PHY_BCR] = { 0x6f000 },</div><div class='add'>+	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },</div><div class='add'>+	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },</div><div class='add'>+	[GCC_PDM_BCR] = { 0x33000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_3_BCR] = { 0x19000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },</div><div class='add'>+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },</div><div class='add'>+	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },</div><div class='add'>+	[GCC_SDCC2_BCR] = { 0x14000 },</div><div class='add'>+	[GCC_SDCC4_BCR] = { 0x16000 },</div><div class='add'>+	[GCC_UFS_PHY_BCR] = { 0x77000 },</div><div class='add'>+	[GCC_USB30_PRIM_BCR] = { 0x39000 },</div><div class='add'>+	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },</div><div class='add'>+	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },</div><div class='add'>+	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },</div><div class='add'>+	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },</div><div class='add'>+	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },</div><div class='add'>+	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },</div><div class='add'>+	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },</div><div class='add'>+	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },</div><div class='add'>+	[GCC_VIDEO_BCR] = { 0x32000 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc *gcc_sm8650_gdscs[] = {</div><div class='add'>+	[PCIE_0_GDSC] = &amp;pcie_0_gdsc,</div><div class='add'>+	[PCIE_0_PHY_GDSC] = &amp;pcie_0_phy_gdsc,</div><div class='add'>+	[PCIE_1_GDSC] = &amp;pcie_1_gdsc,</div><div class='add'>+	[PCIE_1_PHY_GDSC] = &amp;pcie_1_phy_gdsc,</div><div class='add'>+	[UFS_PHY_GDSC] = &amp;ufs_phy_gdsc,</div><div class='add'>+	[UFS_MEM_PHY_GDSC] = &amp;ufs_mem_phy_gdsc,</div><div class='add'>+	[USB30_PRIM_GDSC] = &amp;usb30_prim_gdsc,</div><div class='add'>+	[USB3_PHY_GDSC] = &amp;usb3_phy_gdsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config gcc_sm8650_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x1f41f0,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_cc_desc gcc_sm8650_desc = {</div><div class='add'>+	.config = &amp;gcc_sm8650_regmap_config,</div><div class='add'>+	.clks = gcc_sm8650_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(gcc_sm8650_clocks),</div><div class='add'>+	.resets = gcc_sm8650_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(gcc_sm8650_resets),</div><div class='add'>+	.gdscs = gcc_sm8650_gdscs,</div><div class='add'>+	.num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gcc_sm8650_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,sm8650-gcc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, gcc_sm8650_match_table);</div><div class='add'>+</div><div class='add'>+static int gcc_sm8650_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;gcc_sm8650_desc);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+</div><div class='add'>+	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,</div><div class='add'>+				       ARRAY_SIZE(gcc_dfs_clocks));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Keep the critical clock always-On */</div><div class='add'>+	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */</div><div class='add'>+</div><div class='add'>+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);</div><div class='add'>+</div><div class='add'>+	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */</div><div class='add'>+	regmap_write(regmap, 0x52150, 0x0);</div><div class='add'>+</div><div class='add'>+	return qcom_cc_really_probe(pdev, &amp;gcc_sm8650_desc, regmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver gcc_sm8650_driver = {</div><div class='add'>+	.probe = gcc_sm8650_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "gcc-sm8650",</div><div class='add'>+		.of_match_table = gcc_sm8650_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init gcc_sm8650_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;gcc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+subsys_initcall(gcc_sm8650_init);</div><div class='add'>+</div><div class='add'>+static void __exit gcc_sm8650_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;gcc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(gcc_sm8650_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI GCC SM8650 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c<br/>new file mode 100644<br/>index 000000000000..d7182d6e9783<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gcc-x1e80100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gcc-x1e80100.c</a></div><div class='hunk'>@@ -0,0 +1,6808 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,x1e80100-gcc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "clk-regmap-divider.h"</div><div class='add'>+#include "clk-regmap-mux.h"</div><div class='add'>+#include "clk-regmap-phy-mux.h"</div><div class='add'>+#include "gdsc.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_SLEEP_CLK,</div><div class='add'>+	DT_PCIE_3_PIPE,</div><div class='add'>+	DT_PCIE_4_PIPE,</div><div class='add'>+	DT_PCIE_5_PIPE,</div><div class='add'>+	DT_PCIE_6A_PIPE,</div><div class='add'>+	DT_PCIE_6B_PIPE,</div><div class='add'>+	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,</div><div class='add'>+	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,</div><div class='add'>+	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_GCC_GPLL0_OUT_EVEN,</div><div class='add'>+	P_GCC_GPLL0_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL4_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL7_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL8_OUT_MAIN,</div><div class='add'>+	P_GCC_GPLL9_OUT_MAIN,</div><div class='add'>+	P_SLEEP_CLK,</div><div class='add'>+	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,</div><div class='add'>+	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,</div><div class='add'>+	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52030,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {</div><div class='add'>+	{ 0x1, 2 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.post_div_shift = 10,</div><div class='add'>+	.post_div_table = post_div_table_gcc_gpll0_out_even,</div><div class='add'>+	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),</div><div class='add'>+	.width = 4,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gpll0_out_even",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_gpll0.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_alpha_pll_postdiv_lucid_ole_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll4 = {</div><div class='add'>+	.offset = 0x4000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52030,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll4",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll7 = {</div><div class='add'>+	.offset = 0x7000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52030,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll7",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll8 = {</div><div class='add'>+	.offset = 0x8000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52030,</div><div class='add'>+		.enable_mask = BIT(8),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll8",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gcc_gpll9 = {</div><div class='add'>+	.offset = 0x9000,</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52030,</div><div class='add'>+		.enable_mask = BIT(9),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpll9",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data) {</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_fixed_lucid_ole_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_SLEEP_CLK, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_SLEEP_CLK, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_3[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_3[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_4[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL8_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_4[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll8.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_5[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL7_OUT_MAIN, 2 },</div><div class='add'>+	{ P_SLEEP_CLK, 5 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_5[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll7.clkr.hw },</div><div class='add'>+	{ .index = DT_SLEEP_CLK },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_6[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL7_OUT_MAIN, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_6[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll7.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_7[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_7[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll4.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_8[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL7_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_8[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll7.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_9[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GCC_GPLL9_OUT_MAIN, 2 },</div><div class='add'>+	{ P_GCC_GPLL4_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GCC_GPLL0_OUT_EVEN, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_10[] = {</div><div class='add'>+	{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_10[] = {</div><div class='add'>+	{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_11[] = {</div><div class='add'>+	{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_11[] = {</div><div class='add'>+	{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_12[] = {</div><div class='add'>+	{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gcc_parent_map_12[] = {</div><div class='add'>+	{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },</div><div class='add'>+	{ P_BI_TCXO, 2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gcc_parent_data_9[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll9.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll4.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gcc_gpll0_out_even.clkr.hw },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {</div><div class='add'>+	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x64004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp1_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x65004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp2_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_gp3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x66004,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_gcc_gp1_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_gp3_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa0180,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_0_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa0054,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_0_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2c180,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_1_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2c054,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_1_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x13180,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_2_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x13054,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_2_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x5808c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_3_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x58070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_3_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6b080,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_4_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x6b064,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_4_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2f080,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_5_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2f064,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_5_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x3108c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6a_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x31070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6a_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8d08c,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6b_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x8d070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6b_phy_rchng_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa400c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_rscc_xo_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {</div><div class='add'>+	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_pdm2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x33010,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pdm2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pdm2_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s0_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42010,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s0_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s1_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42148,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s1_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s2_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42288,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s2_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s3_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x423c8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s3_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {</div><div class='add'>+	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),</div><div class='add'>+	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),</div><div class='add'>+	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),</div><div class='add'>+	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),</div><div class='add'>+	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),</div><div class='add'>+	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s4_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42500,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s4_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s5_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42638,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s5_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s6_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x42770,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s6_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap0_s7_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x428a8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap0_s7_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s0_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18010,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s0_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s1_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18148,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s1_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s2_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18288,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s2_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s3_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x183c8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s3_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s4_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18500,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s4_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s5_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18638,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s5_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s6_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x18770,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s6_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap1_s7_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x188a8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap1_s7_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s0_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e010,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s0_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s1_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e148,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s1_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s2_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e288,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s2_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s3_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e3c8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s3_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s4_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e500,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s4_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s5_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e638,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s5_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s6_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_8,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_8),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e770,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_8,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s6_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {</div><div class='add'>+	.name = "gcc_qupv3_wrap2_s7_clk_src",</div><div class='add'>+	.parent_data = gcc_parent_data_0,</div><div class='add'>+	.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+	.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+	.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1e8a8,</div><div class='add'>+	.mnd_width = 16,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;gcc_qupv3_wrap2_s7_clk_src_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {</div><div class='add'>+	F(400000, P_BI_TCXO, 12, 1, 4),</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x14018,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_9,</div><div class='add'>+	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_sdcc2_apps_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_9,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_9),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_floor_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {</div><div class='add'>+	F(400000, P_BI_TCXO, 12, 1, 4),</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x16018,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_sdcc4_apps_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_floor_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {</div><div class='add'>+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77030,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_axi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {</div><div class='add'>+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),</div><div class='add'>+	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77080,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_7,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_ice_core_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_7,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_7),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x770b4,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {</div><div class='add'>+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),</div><div class='add'>+	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x77098,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_ufs_phy_unipro_core_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {</div><div class='add'>+	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),</div><div class='add'>+	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb20_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2902c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb20_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb20_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x29158,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb20_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {</div><div class='add'>+	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),</div><div class='add'>+	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),</div><div class='add'>+	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1702c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_mp_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x17158,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_mp_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x3902c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x39044,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa102c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_sec_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa1044,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_sec_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa202c,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_tert_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa2044,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_tert_mock_utmi_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x172a0,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb3_mp_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x39074,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb3_prim_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa1074,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb3_sec_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0xa2074,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb3_tert_phy_aux_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {</div><div class='add'>+	F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),</div><div class='add'>+	F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_0_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9f024,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_0_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),</div><div class='add'>+	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9f0e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_0_phy_pcie_pipe_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9f08c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_0_sb_if_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9f070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_6,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_0_tmu_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_6,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_6),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_1_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2b024,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_1_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2b0e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2b08c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_1_sb_if_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x2b070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_6,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_1_tmu_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_6,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_6),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_2_master_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x11024,</div><div class='add'>+	.mnd_width = 8,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_4,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_2_master_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_4,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_4),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x110e8,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_5,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_2_phy_pcie_pipe_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_5,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x1108c,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_3,</div><div class='add'>+	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_2_sb_if_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_3,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_3),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x11070,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gcc_parent_map_6,</div><div class='add'>+	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb4_2_tmu_clk_src",</div><div class='add'>+		.parent_data = gcc_parent_data_6,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gcc_parent_data_6),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = {</div><div class='add'>+	.reg = 0x58088,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_pcie_3_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_3_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = {</div><div class='add'>+	.reg = 0x5806c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_3_pipe_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_pcie_3_pipe_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {</div><div class='add'>+	.reg = 0x6b07c,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_pcie_4_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_4_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {</div><div class='add'>+	.reg = 0x6b060,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_4_pipe_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_pcie_4_pipe_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {</div><div class='add'>+	.reg = 0x2f07c,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_pcie_5_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_5_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {</div><div class='add'>+	.reg = 0x2f060,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_5_pipe_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_pcie_5_pipe_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = {</div><div class='add'>+	.reg = 0x31088,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_pcie_6a_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_6A_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = {</div><div class='add'>+	.reg = 0x3106c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6a_pipe_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_pcie_6a_pipe_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = {</div><div class='add'>+	.reg = 0x8d088,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_pcie_6b_pipe_clk_src",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_PCIE_6B_PIPE,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_regmap_phy_mux_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = {</div><div class='add'>+	.reg = 0x8d06c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_pcie_6b_pipe_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_pcie_6b_pipe_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = {</div><div class='add'>+	.reg = 0x42284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap0_s2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap0_s2_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = {</div><div class='add'>+	.reg = 0x423c4,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap0_s3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap0_s3_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = {</div><div class='add'>+	.reg = 0x18284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap1_s2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap1_s2_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = {</div><div class='add'>+	.reg = 0x183c4,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap1_s3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap1_s3_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = {</div><div class='add'>+	.reg = 0x1e284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap2_s2_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap2_s2_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = {</div><div class='add'>+	.reg = 0x1e3c4,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_qupv3_wrap2_s3_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_qupv3_wrap2_s3_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0x29284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb20_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb20_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0x17284,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0x3905c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0xa105c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {</div><div class='add'>+	.reg = 0xa205c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+			&amp;gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2d17c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d17c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2d17c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_noc_usb_north_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2d174,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d174,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2d174,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_noc_usb_south_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {</div><div class='add'>+	.halt_reg = 0x770e4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770e4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770e4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_ufs_phy_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2928c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2928c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2928c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb2_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb20_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {</div><div class='add'>+	.halt_reg = 0x173d0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x173d0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x173d0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb3_mp_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_mp_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x39090,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x39090,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb3_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa1090,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa1090,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb3_sec_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_sec_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa2090,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa2090,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2090,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb3_tert_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_tert_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb4_0_axi_clk = {</div><div class='add'>+	.halt_reg = 0x9f118,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x9f118,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f118,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb4_0_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_0_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb4_1_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2b118,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2b118,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b118,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb4_1_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_1_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb4_2_axi_clk = {</div><div class='add'>+	.halt_reg = 0x11118,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x11118,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11118,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb4_2_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_2_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_aggre_usb_noc_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2d034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2d034,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_aggre_usb_noc_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_av1e_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x4a004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x4a004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x4a004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_av1e_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_av1e_axi_clk = {</div><div class='add'>+	.halt_reg = 0x4a008,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x4a008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x4a008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_av1e_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_av1e_xo_clk = {</div><div class='add'>+	.halt_reg = 0x4a014,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x4a014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_av1e_xo_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_boot_rom_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x38004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x38004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_boot_rom_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camera_hf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x26010,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x26010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x26010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_camera_hf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_camera_sf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2601c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2601c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2601c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_camera_sf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x10028,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x10028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x1002c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1002c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x10030,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x10030,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x29288,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x29288,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x29288,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb2_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb20_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {</div><div class='add'>+	.halt_reg = 0x173cc,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x173cc,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x173cc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb3_mp_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_mp_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {</div><div class='add'>+	.halt_reg = 0x3908c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x3908c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3908c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb3_prim_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa108c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa108c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa108c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb3_sec_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_sec_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa208c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa208c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa208c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb3_tert_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_tert_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2d024,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d024,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb_anoc_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2d028,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb_anoc_north_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2d02c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d02c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {</div><div class='add'>+	.halt_reg = 0x2c2b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie1_tunnel_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = {</div><div class='add'>+	.halt_reg = 0x132b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(31),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie2_tunnel_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x10014,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x10014,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie_north_sf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x10018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x10018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(12),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie_south_sf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_cnoc_pcie_tunnel_clk = {</div><div class='add'>+	.halt_reg = 0xa02b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa02b4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_cnoc_pcie_tunnel_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ddrss_gpu_axi_clk = {</div><div class='add'>+	.halt_reg = 0x7115c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x7115c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7115c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ddrss_gpu_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_disp_hf_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2700c,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2700c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2700c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_disp_hf_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_disp_xo_clk = {</div><div class='add'>+	.halt_reg = 0x27018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x27018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_disp_xo_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp1_clk = {</div><div class='add'>+	.halt_reg = 0x64000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x64000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp2_clk = {</div><div class='add'>+	.halt_reg = 0x65000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x65000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gp3_clk = {</div><div class='add'>+	.halt_reg = 0x66000,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x66000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gp3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gp3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x71004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x71004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_gpll0_cph_clk_src",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gpll0.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_gpll0_div_cph_clk_src",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_gpll0_out_even.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {</div><div class='add'>+	.halt_reg = 0x71010,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x71010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_memnoc_gfx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {</div><div class='add'>+	.halt_reg = 0x71018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_gpu_snoc_dvm_gfx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie0_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0xa0050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie0_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_0_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie1_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x2c050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(31),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie1_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie2_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x13050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie2_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_2_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_aux_clk = {</div><div class='add'>+	.halt_reg = 0xa0038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_0_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xa0034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa0034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa0028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0xa0028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_pipe_clk = {</div><div class='add'>+	.halt_reg = 0xa0044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa001c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa001c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0xa0018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_0_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_aux_clk = {</div><div class='add'>+	.halt_reg = 0x2c038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_1_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2c034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2c034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2c028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2c028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x2c044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2c01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2c01c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2c018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_1_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_aux_clk = {</div><div class='add'>+	.halt_reg = 0x13038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_2_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x13034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x13034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x13028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x13028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x13044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x1301c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x1301c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x13018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(18),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_2_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_aux_clk = {</div><div class='add'>+	.halt_reg = 0x58038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_3_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x58034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x58034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x58028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x58028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(31),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x58044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_phy_aux_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x5805c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_3_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x58050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_pipediv2_clk = {</div><div class='add'>+	.halt_reg = 0x58060,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_pipediv2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_3_pipe_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x5801c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x5801c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x58018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_3_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_aux_clk = {</div><div class='add'>+	.halt_reg = 0x6b038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_4_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x6b034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x6b034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x6b028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x6b050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_4_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x6b044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_pipediv2_clk = {</div><div class='add'>+	.halt_reg = 0x6b054,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_pipediv2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_4_pipe_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x6b01c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x6b018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_4_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_aux_clk = {</div><div class='add'>+	.halt_reg = 0x2f038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_5_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2f034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2f034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2f028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x2f028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(14),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x2f050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(18),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_5_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x2f044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_pipediv2_clk = {</div><div class='add'>+	.halt_reg = 0x2f054,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_pipediv2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_5_pipe_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2f01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2f01c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(13),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2f018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(12),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_5_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_aux_clk = {</div><div class='add'>+	.halt_reg = 0x31038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6a_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x31034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x31034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x31028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x31028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x31044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_phy_aux_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x3105c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6a_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x31050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_pipediv2_clk = {</div><div class='add'>+	.halt_reg = 0x31060,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_pipediv2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6a_pipe_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x3101c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x3101c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x31018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52018,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6a_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8d038,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(29),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6b_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x8d034,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x8d034,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_mstr_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d028,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x8d028,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_mstr_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x8d044,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_phy_aux_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {</div><div class='add'>+	.halt_reg = 0x8d05c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_phy_rchng_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6b_phy_rchng_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x8d050,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(30),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_pipediv2_clk = {</div><div class='add'>+	.halt_reg = 0x8d060,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_pipediv2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_6b_pipe_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_slv_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d01c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x8d01c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_slv_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = {</div><div class='add'>+	.halt_reg = 0x8d018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52000,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_6b_slv_q2a_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_rscc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0xa4008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa4008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(18),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_rscc_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pcie_rscc_xo_clk = {</div><div class='add'>+	.halt_reg = 0xa4004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pcie_rscc_xo_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pcie_rscc_xo_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm2_clk = {</div><div class='add'>+	.halt_reg = 0x3300c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3300c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_pdm2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x33004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x33004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x33004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_pdm_xo4_clk = {</div><div class='add'>+	.halt_reg = 0x33008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x33008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_pdm_xo4_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_av1e_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x4a018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x4a018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x4a018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_av1e_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x26008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x26008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x26008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_camera_nrt_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2600c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2600c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2600c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_camera_rt_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_disp_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x27008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x27008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x27008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_disp_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_gpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x71008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x71008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x71008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_gpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32014,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32014,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_cv_cpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32008,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_cvp_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x32010,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x32010,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_v_cpu_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x3200c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x3200c,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x3200c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qmip_video_vcodec_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x23018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(9),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_core_clk = {</div><div class='add'>+	.halt_reg = 0x23008,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(8),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {</div><div class='add'>+	.halt_reg = 0x42280,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_qspi_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {</div><div class='add'>+	.halt_reg = 0x423c0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_qspi_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {</div><div class='add'>+	.halt_reg = 0x42004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {</div><div class='add'>+	.halt_reg = 0x4213c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(11),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {</div><div class='add'>+	.halt_reg = 0x42274,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(12),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {</div><div class='add'>+	.halt_reg = 0x423b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(13),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {</div><div class='add'>+	.halt_reg = 0x424f4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(14),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {</div><div class='add'>+	.halt_reg = 0x4262c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(15),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s6_clk = {</div><div class='add'>+	.halt_reg = 0x42764,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap0_s7_clk = {</div><div class='add'>+	.halt_reg = 0x4289c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap0_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap0_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x23168,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(18),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_core_clk = {</div><div class='add'>+	.halt_reg = 0x23158,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {</div><div class='add'>+	.halt_reg = 0x18280,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_qspi_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {</div><div class='add'>+	.halt_reg = 0x183c0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_qspi_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {</div><div class='add'>+	.halt_reg = 0x18004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(22),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {</div><div class='add'>+	.halt_reg = 0x1813c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(23),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {</div><div class='add'>+	.halt_reg = 0x18274,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(24),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {</div><div class='add'>+	.halt_reg = 0x183b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(25),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {</div><div class='add'>+	.halt_reg = 0x184f4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(26),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {</div><div class='add'>+	.halt_reg = 0x1862c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(27),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {</div><div class='add'>+	.halt_reg = 0x18764,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(28),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap1_s7_clk = {</div><div class='add'>+	.halt_reg = 0x1889c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(16),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap1_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap1_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {</div><div class='add'>+	.halt_reg = 0x232b8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(3),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_core_2x_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_core_clk = {</div><div class='add'>+	.halt_reg = 0x232a8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_core_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {</div><div class='add'>+	.halt_reg = 0x1e280,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_qspi_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s2_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {</div><div class='add'>+	.halt_reg = 0x1e3c0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_qspi_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s3_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s0_clk = {</div><div class='add'>+	.halt_reg = 0x1e004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(4),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s0_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s0_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s1_clk = {</div><div class='add'>+	.halt_reg = 0x1e13c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(5),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s1_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s1_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s2_clk = {</div><div class='add'>+	.halt_reg = 0x1e274,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s2_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s3_clk = {</div><div class='add'>+	.halt_reg = 0x1e3b4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s3_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s4_clk = {</div><div class='add'>+	.halt_reg = 0x1e4f4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(8),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s4_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s4_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s5_clk = {</div><div class='add'>+	.halt_reg = 0x1e62c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(9),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s5_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s5_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s6_clk = {</div><div class='add'>+	.halt_reg = 0x1e764,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(10),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s6_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s6_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap2_s7_clk = {</div><div class='add'>+	.halt_reg = 0x1e89c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(17),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap2_s7_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_qupv3_wrap2_s7_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23000,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23000,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(6),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_0_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23004,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52020,</div><div class='add'>+		.enable_mask = BIT(7),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_0_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23150,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23150,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(20),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_1_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x23154,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x23154,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52008,</div><div class='add'>+		.enable_mask = BIT(21),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_1_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x232a0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x232a0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(2),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_m_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x232a4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x232a4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_qupv3_wrap_2_s_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc2_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x14010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x14010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc2_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc2_apps_clk = {</div><div class='add'>+	.halt_reg = 0x14004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x14004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc2_apps_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_sdcc2_apps_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc4_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x16010,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x16010,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc4_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sdcc4_apps_clk = {</div><div class='add'>+	.halt_reg = 0x16004,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x16004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sdcc4_apps_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_sdcc4_apps_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_sys_noc_usb_axi_clk = {</div><div class='add'>+	.halt_reg = 0x2d014,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2d014,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2d014,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_sys_noc_usb_axi_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x77024,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77024,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_axi_clk = {</div><div class='add'>+	.halt_reg = 0x77018,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_axi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_axi_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_ice_core_clk = {</div><div class='add'>+	.halt_reg = 0x77074,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77074,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77074,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_ice_core_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_ice_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x770b0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x770b0,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {</div><div class='add'>+	.halt_reg = 0x7702c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7702c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {</div><div class='add'>+	.halt_reg = 0x770cc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x770cc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_rx_symbol_1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {</div><div class='add'>+	.halt_reg = 0x77028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_tx_symbol_0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {</div><div class='add'>+	.halt_reg = 0x77068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x77068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x77068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_ufs_phy_unipro_core_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_ufs_phy_unipro_core_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb20_master_clk = {</div><div class='add'>+	.halt_reg = 0x29018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x29018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb20_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb20_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb20_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0x29028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x29028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb20_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb20_sleep_clk = {</div><div class='add'>+	.halt_reg = 0x29024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x29024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb20_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_mp_master_clk = {</div><div class='add'>+	.halt_reg = 0x17018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_mp_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_mp_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0x17028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_mp_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_mp_sleep_clk = {</div><div class='add'>+	.halt_reg = 0x17024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_mp_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_master_clk = {</div><div class='add'>+	.halt_reg = 0x39018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0x39028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_prim_sleep_clk = {</div><div class='add'>+	.halt_reg = 0x39024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_prim_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_sec_master_clk = {</div><div class='add'>+	.halt_reg = 0xa1018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_sec_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_sec_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0xa1028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_sec_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_sec_sleep_clk = {</div><div class='add'>+	.halt_reg = 0xa1024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_sec_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_tert_master_clk = {</div><div class='add'>+	.halt_reg = 0xa2018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_tert_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_tert_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {</div><div class='add'>+	.halt_reg = 0xa2028,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_tert_mock_utmi_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb30_tert_sleep_clk = {</div><div class='add'>+	.halt_reg = 0xa2024,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb30_tert_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_mp_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x17288,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17288,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_mp_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_mp_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {</div><div class='add'>+	.halt_reg = 0x1728c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x1728c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_mp_phy_com_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_mp_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {</div><div class='add'>+	.halt_reg = 0x17290,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17290,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_mp_phy_pipe_0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {</div><div class='add'>+	.halt_reg = 0x17298,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x17298,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_mp_phy_pipe_1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0x39060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {</div><div class='add'>+	.halt_reg = 0x39064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_com_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {</div><div class='add'>+	.reg = 0x3906c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_10,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_usb3_prim_phy_pipe_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_10,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_10),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x39068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x39068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x39068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_prim_phy_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_sec_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0xa1060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_sec_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_sec_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {</div><div class='add'>+	.halt_reg = 0xa1064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_sec_phy_com_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_sec_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {</div><div class='add'>+	.reg = 0xa106c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_11,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_usb3_sec_phy_pipe_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_11,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_11),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {</div><div class='add'>+	.halt_reg = 0xa1068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa1068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa1068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_sec_phy_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_tert_phy_aux_clk = {</div><div class='add'>+	.halt_reg = 0xa2060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_tert_phy_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_tert_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {</div><div class='add'>+	.halt_reg = 0xa2064,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2064,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_tert_phy_com_aux_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_tert_phy_aux_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {</div><div class='add'>+	.reg = 0xa206c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 2,</div><div class='add'>+	.parent_map = gcc_parent_map_12,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gcc_usb3_tert_phy_pipe_clk_src",</div><div class='add'>+			.parent_data = gcc_parent_data_12,</div><div class='add'>+			.num_parents = ARRAY_SIZE(gcc_parent_data_12),</div><div class='add'>+			.ops = &amp;clk_regmap_mux_closest_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {</div><div class='add'>+	.halt_reg = 0xa2068,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0xa2068,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0xa2068,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb3_tert_phy_pipe_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x9f0a8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x9f0a8,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f0a8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_dp0_clk = {</div><div class='add'>+	.halt_reg = 0x9f060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_dp0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_dp1_clk = {</div><div class='add'>+	.halt_reg = 0x9f108,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f108,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_dp1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_master_clk = {</div><div class='add'>+	.halt_reg = 0x9f018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_0_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x9f0d8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f0d8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x9f048,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52010,</div><div class='add'>+		.enable_mask = BIT(19),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_phy_pcie_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_phy_rx0_clk = {</div><div class='add'>+	.halt_reg = 0x9f0b0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f0b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_phy_rx0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_phy_rx1_clk = {</div><div class='add'>+	.halt_reg = 0x9f0c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f0c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_phy_rx1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x9f0a4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x9f0a4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f0a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_phy_usb_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_sb_if_clk = {</div><div class='add'>+	.halt_reg = 0x9f044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_sb_if_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_0_sb_if_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_sys_clk = {</div><div class='add'>+	.halt_reg = 0x9f054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_sys_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_0_tmu_clk = {</div><div class='add'>+	.halt_reg = 0x9f088,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x9f088,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9f088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_0_tmu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_0_tmu_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x2b0a8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2b0a8,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b0a8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_dp0_clk = {</div><div class='add'>+	.halt_reg = 0x2b060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_dp0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_dp1_clk = {</div><div class='add'>+	.halt_reg = 0x2b108,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b108,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_dp1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_master_clk = {</div><div class='add'>+	.halt_reg = 0x2b018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_1_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x2b0d8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b0d8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x2b048,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_phy_pcie_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_phy_rx0_clk = {</div><div class='add'>+	.halt_reg = 0x2b0b0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b0b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_phy_rx0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_phy_rx1_clk = {</div><div class='add'>+	.halt_reg = 0x2b0c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b0c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_phy_rx1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x2b0a4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2b0a4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b0a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_phy_usb_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_sb_if_clk = {</div><div class='add'>+	.halt_reg = 0x2b044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_sb_if_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_1_sb_if_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_sys_clk = {</div><div class='add'>+	.halt_reg = 0x2b054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_sys_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_1_tmu_clk = {</div><div class='add'>+	.halt_reg = 0x2b088,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x2b088,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x2b088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_1_tmu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_1_tmu_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x110a8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x110a8,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x110a8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_cfg_ahb_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_dp0_clk = {</div><div class='add'>+	.halt_reg = 0x11060,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11060,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_dp0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_dp1_clk = {</div><div class='add'>+	.halt_reg = 0x11108,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11108,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_dp1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_master_clk = {</div><div class='add'>+	.halt_reg = 0x11018,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_master_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_2_master_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x110d8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x110d8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x11048,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x52028,</div><div class='add'>+		.enable_mask = BIT(1),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_phy_pcie_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_phy_rx0_clk = {</div><div class='add'>+	.halt_reg = 0x110b0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x110b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_phy_rx0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_phy_rx1_clk = {</div><div class='add'>+	.halt_reg = 0x110c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x110c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_phy_rx1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {</div><div class='add'>+	.halt_reg = 0x110a4,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x110a4,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x110a4,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_phy_usb_pipe_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_sb_if_clk = {</div><div class='add'>+	.halt_reg = 0x11044,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11044,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_sb_if_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_2_sb_if_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_sys_clk = {</div><div class='add'>+	.halt_reg = 0x11054,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11054,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_sys_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_usb4_2_tmu_clk = {</div><div class='add'>+	.halt_reg = 0x11088,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.hwcg_reg = 0x11088,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x11088,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_usb4_2_tmu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]) {</div><div class='add'>+				&amp;gcc_usb4_2_tmu_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_video_axi0_clk = {</div><div class='add'>+	.halt_reg = 0x32018,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x32018,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32018,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_video_axi0_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gcc_video_axi1_clk = {</div><div class='add'>+	.halt_reg = 0x32024,</div><div class='add'>+	.halt_check = BRANCH_HALT_SKIP,</div><div class='add'>+	.hwcg_reg = 0x32024,</div><div class='add'>+	.hwcg_bit = 1,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x32024,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+			.name = "gcc_video_axi1_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_0_tunnel_gdsc = {</div><div class='add'>+	.gdscr = 0xa0004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_0_tunnel_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_1_tunnel_gdsc = {</div><div class='add'>+	.gdscr = 0x2c004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_1_tunnel_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_2_tunnel_gdsc = {</div><div class='add'>+	.gdscr = 0x13004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_2_tunnel_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_3_gdsc = {</div><div class='add'>+	.gdscr = 0x58004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_3_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_3_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x3e000,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_3_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_4_gdsc = {</div><div class='add'>+	.gdscr = 0x6b004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_4_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_4_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x6c000,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_4_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_5_gdsc = {</div><div class='add'>+	.gdscr = 0x2f004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_5_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_5_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x30000,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_5_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_6_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x8e000,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_6_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_6a_gdsc = {</div><div class='add'>+	.gdscr = 0x31004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_6a_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_pcie_6b_gdsc = {</div><div class='add'>+	.gdscr = 0x8d004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_pcie_6b_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_ufs_mem_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x9e000,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_ufs_mem_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_ufs_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x77004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_ufs_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb20_prim_gdsc = {</div><div class='add'>+	.gdscr = 0x29004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb20_prim_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb30_mp_gdsc = {</div><div class='add'>+	.gdscr = 0x17004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb30_mp_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb30_prim_gdsc = {</div><div class='add'>+	.gdscr = 0x39004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb30_prim_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb30_sec_gdsc = {</div><div class='add'>+	.gdscr = 0xa1004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb30_sec_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb30_tert_gdsc = {</div><div class='add'>+	.gdscr = 0xa2004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb30_tert_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x1900c,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb3_mp_ss0_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x5400c,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb3_mp_ss1_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb4_0_gdsc = {</div><div class='add'>+	.gdscr = 0x9f004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb4_0_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb4_1_gdsc = {</div><div class='add'>+	.gdscr = 0x2b004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb4_1_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb4_2_gdsc = {</div><div class='add'>+	.gdscr = 0x11004,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0xf,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb4_2_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb_0_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x50024,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb_0_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb_1_phy_gdsc = {</div><div class='add'>+	.gdscr = 0x2a024,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb_1_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gcc_usb_2_phy_gdsc = {</div><div class='add'>+	.gdscr = 0xa3024,</div><div class='add'>+	.en_rest_wait_val = 0x2,</div><div class='add'>+	.en_few_wait_val = 0x2,</div><div class='add'>+	.clk_dis_wait_val = 0x2,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gcc_usb_2_phy_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_RET_ON,</div><div class='add'>+	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *gcc_x1e80100_clocks[] = {</div><div class='add'>+	[GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &amp;gcc_aggre_noc_usb_north_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &amp;gcc_aggre_noc_usb_south_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &amp;gcc_aggre_ufs_phy_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &amp;gcc_aggre_usb2_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB3_MP_AXI_CLK] = &amp;gcc_aggre_usb3_mp_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &amp;gcc_aggre_usb3_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &amp;gcc_aggre_usb3_sec_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB3_TERT_AXI_CLK] = &amp;gcc_aggre_usb3_tert_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB4_0_AXI_CLK] = &amp;gcc_aggre_usb4_0_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB4_1_AXI_CLK] = &amp;gcc_aggre_usb4_1_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB4_2_AXI_CLK] = &amp;gcc_aggre_usb4_2_axi_clk.clkr,</div><div class='add'>+	[GCC_AGGRE_USB_NOC_AXI_CLK] = &amp;gcc_aggre_usb_noc_axi_clk.clkr,</div><div class='add'>+	[GCC_AV1E_AHB_CLK] = &amp;gcc_av1e_ahb_clk.clkr,</div><div class='add'>+	[GCC_AV1E_AXI_CLK] = &amp;gcc_av1e_axi_clk.clkr,</div><div class='add'>+	[GCC_AV1E_XO_CLK] = &amp;gcc_av1e_xo_clk.clkr,</div><div class='add'>+	[GCC_BOOT_ROM_AHB_CLK] = &amp;gcc_boot_rom_ahb_clk.clkr,</div><div class='add'>+	[GCC_CAMERA_HF_AXI_CLK] = &amp;gcc_camera_hf_axi_clk.clkr,</div><div class='add'>+	[GCC_CAMERA_SF_AXI_CLK] = &amp;gcc_camera_sf_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &amp;gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &amp;gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &amp;gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &amp;gcc_cfg_noc_usb2_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &amp;gcc_cfg_noc_usb3_mp_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &amp;gcc_cfg_noc_usb3_prim_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &amp;gcc_cfg_noc_usb3_sec_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &amp;gcc_cfg_noc_usb3_tert_axi_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &amp;gcc_cfg_noc_usb_anoc_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &amp;gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr,</div><div class='add'>+	[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &amp;gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE1_TUNNEL_CLK] = &amp;gcc_cnoc_pcie1_tunnel_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE2_TUNNEL_CLK] = &amp;gcc_cnoc_pcie2_tunnel_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &amp;gcc_cnoc_pcie_north_sf_axi_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &amp;gcc_cnoc_pcie_south_sf_axi_clk.clkr,</div><div class='add'>+	[GCC_CNOC_PCIE_TUNNEL_CLK] = &amp;gcc_cnoc_pcie_tunnel_clk.clkr,</div><div class='add'>+	[GCC_DDRSS_GPU_AXI_CLK] = &amp;gcc_ddrss_gpu_axi_clk.clkr,</div><div class='add'>+	[GCC_DISP_HF_AXI_CLK] = &amp;gcc_disp_hf_axi_clk.clkr,</div><div class='add'>+	[GCC_DISP_XO_CLK] = &amp;gcc_disp_xo_clk.clkr,</div><div class='add'>+	[GCC_GP1_CLK] = &amp;gcc_gp1_clk.clkr,</div><div class='add'>+	[GCC_GP1_CLK_SRC] = &amp;gcc_gp1_clk_src.clkr,</div><div class='add'>+	[GCC_GP2_CLK] = &amp;gcc_gp2_clk.clkr,</div><div class='add'>+	[GCC_GP2_CLK_SRC] = &amp;gcc_gp2_clk_src.clkr,</div><div class='add'>+	[GCC_GP3_CLK] = &amp;gcc_gp3_clk.clkr,</div><div class='add'>+	[GCC_GP3_CLK_SRC] = &amp;gcc_gp3_clk_src.clkr,</div><div class='add'>+	[GCC_GPLL0] = &amp;gcc_gpll0.clkr,</div><div class='add'>+	[GCC_GPLL0_OUT_EVEN] = &amp;gcc_gpll0_out_even.clkr,</div><div class='add'>+	[GCC_GPLL4] = &amp;gcc_gpll4.clkr,</div><div class='add'>+	[GCC_GPLL7] = &amp;gcc_gpll7.clkr,</div><div class='add'>+	[GCC_GPLL8] = &amp;gcc_gpll8.clkr,</div><div class='add'>+	[GCC_GPLL9] = &amp;gcc_gpll9.clkr,</div><div class='add'>+	[GCC_GPU_CFG_AHB_CLK] = &amp;gcc_gpu_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_GPU_GPLL0_CPH_CLK_SRC] = &amp;gcc_gpu_gpll0_cph_clk_src.clkr,</div><div class='add'>+	[GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &amp;gcc_gpu_gpll0_div_cph_clk_src.clkr,</div><div class='add'>+	[GCC_GPU_MEMNOC_GFX_CLK] = &amp;gcc_gpu_memnoc_gfx_clk.clkr,</div><div class='add'>+	[GCC_GPU_SNOC_DVM_GFX_CLK] = &amp;gcc_gpu_snoc_dvm_gfx_clk.clkr,</div><div class='add'>+	[GCC_PCIE0_PHY_RCHNG_CLK] = &amp;gcc_pcie0_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE1_PHY_RCHNG_CLK] = &amp;gcc_pcie1_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE2_PHY_RCHNG_CLK] = &amp;gcc_pcie2_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_AUX_CLK] = &amp;gcc_pcie_0_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_AUX_CLK_SRC] = &amp;gcc_pcie_0_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_0_CFG_AHB_CLK] = &amp;gcc_pcie_0_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_MSTR_AXI_CLK] = &amp;gcc_pcie_0_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_0_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_0_PIPE_CLK] = &amp;gcc_pcie_0_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_SLV_AXI_CLK] = &amp;gcc_pcie_0_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_0_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_AUX_CLK] = &amp;gcc_pcie_1_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_AUX_CLK_SRC] = &amp;gcc_pcie_1_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_CFG_AHB_CLK] = &amp;gcc_pcie_1_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_MSTR_AXI_CLK] = &amp;gcc_pcie_1_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_1_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_1_PIPE_CLK] = &amp;gcc_pcie_1_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_SLV_AXI_CLK] = &amp;gcc_pcie_1_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_1_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_AUX_CLK] = &amp;gcc_pcie_2_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_AUX_CLK_SRC] = &amp;gcc_pcie_2_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_2_CFG_AHB_CLK] = &amp;gcc_pcie_2_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_MSTR_AXI_CLK] = &amp;gcc_pcie_2_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_2_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_2_PIPE_CLK] = &amp;gcc_pcie_2_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_SLV_AXI_CLK] = &amp;gcc_pcie_2_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_2_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_AUX_CLK] = &amp;gcc_pcie_3_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_AUX_CLK_SRC] = &amp;gcc_pcie_3_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_3_CFG_AHB_CLK] = &amp;gcc_pcie_3_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_MSTR_AXI_CLK] = &amp;gcc_pcie_3_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_PHY_AUX_CLK] = &amp;gcc_pcie_3_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_PHY_RCHNG_CLK] = &amp;gcc_pcie_3_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_3_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_3_PIPE_CLK] = &amp;gcc_pcie_3_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_PIPE_CLK_SRC] = &amp;gcc_pcie_3_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &amp;gcc_pcie_3_pipe_div_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_3_PIPEDIV2_CLK] = &amp;gcc_pcie_3_pipediv2_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_SLV_AXI_CLK] = &amp;gcc_pcie_3_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_3_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_AUX_CLK] = &amp;gcc_pcie_4_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_AUX_CLK_SRC] = &amp;gcc_pcie_4_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_4_CFG_AHB_CLK] = &amp;gcc_pcie_4_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_MSTR_AXI_CLK] = &amp;gcc_pcie_4_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_PHY_RCHNG_CLK] = &amp;gcc_pcie_4_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_4_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_4_PIPE_CLK] = &amp;gcc_pcie_4_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_PIPE_CLK_SRC] = &amp;gcc_pcie_4_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &amp;gcc_pcie_4_pipe_div_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_4_PIPEDIV2_CLK] = &amp;gcc_pcie_4_pipediv2_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_SLV_AXI_CLK] = &amp;gcc_pcie_4_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_4_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_AUX_CLK] = &amp;gcc_pcie_5_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_AUX_CLK_SRC] = &amp;gcc_pcie_5_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_5_CFG_AHB_CLK] = &amp;gcc_pcie_5_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_MSTR_AXI_CLK] = &amp;gcc_pcie_5_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_PHY_RCHNG_CLK] = &amp;gcc_pcie_5_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_5_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_5_PIPE_CLK] = &amp;gcc_pcie_5_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_PIPE_CLK_SRC] = &amp;gcc_pcie_5_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &amp;gcc_pcie_5_pipe_div_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_5_PIPEDIV2_CLK] = &amp;gcc_pcie_5_pipediv2_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_SLV_AXI_CLK] = &amp;gcc_pcie_5_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_5_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_AUX_CLK] = &amp;gcc_pcie_6a_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_AUX_CLK_SRC] = &amp;gcc_pcie_6a_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6A_CFG_AHB_CLK] = &amp;gcc_pcie_6a_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_MSTR_AXI_CLK] = &amp;gcc_pcie_6a_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PHY_AUX_CLK] = &amp;gcc_pcie_6a_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PHY_RCHNG_CLK] = &amp;gcc_pcie_6a_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_6a_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PIPE_CLK] = &amp;gcc_pcie_6a_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PIPE_CLK_SRC] = &amp;gcc_pcie_6a_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &amp;gcc_pcie_6a_pipe_div_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6A_PIPEDIV2_CLK] = &amp;gcc_pcie_6a_pipediv2_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_SLV_AXI_CLK] = &amp;gcc_pcie_6a_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_6a_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_AUX_CLK] = &amp;gcc_pcie_6b_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_AUX_CLK_SRC] = &amp;gcc_pcie_6b_aux_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6B_CFG_AHB_CLK] = &amp;gcc_pcie_6b_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_MSTR_AXI_CLK] = &amp;gcc_pcie_6b_mstr_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PHY_AUX_CLK] = &amp;gcc_pcie_6b_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PHY_RCHNG_CLK] = &amp;gcc_pcie_6b_phy_rchng_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &amp;gcc_pcie_6b_phy_rchng_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PIPE_CLK] = &amp;gcc_pcie_6b_pipe_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PIPE_CLK_SRC] = &amp;gcc_pcie_6b_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &amp;gcc_pcie_6b_pipe_div_clk_src.clkr,</div><div class='add'>+	[GCC_PCIE_6B_PIPEDIV2_CLK] = &amp;gcc_pcie_6b_pipediv2_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_SLV_AXI_CLK] = &amp;gcc_pcie_6b_slv_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &amp;gcc_pcie_6b_slv_q2a_axi_clk.clkr,</div><div class='add'>+	[GCC_PCIE_RSCC_AHB_CLK] = &amp;gcc_pcie_rscc_ahb_clk.clkr,</div><div class='add'>+	[GCC_PCIE_RSCC_XO_CLK] = &amp;gcc_pcie_rscc_xo_clk.clkr,</div><div class='add'>+	[GCC_PCIE_RSCC_XO_CLK_SRC] = &amp;gcc_pcie_rscc_xo_clk_src.clkr,</div><div class='add'>+	[GCC_PDM2_CLK] = &amp;gcc_pdm2_clk.clkr,</div><div class='add'>+	[GCC_PDM2_CLK_SRC] = &amp;gcc_pdm2_clk_src.clkr,</div><div class='add'>+	[GCC_PDM_AHB_CLK] = &amp;gcc_pdm_ahb_clk.clkr,</div><div class='add'>+	[GCC_PDM_XO4_CLK] = &amp;gcc_pdm_xo4_clk.clkr,</div><div class='add'>+	[GCC_QMIP_AV1E_AHB_CLK] = &amp;gcc_qmip_av1e_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &amp;gcc_qmip_camera_nrt_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &amp;gcc_qmip_camera_rt_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_DISP_AHB_CLK] = &amp;gcc_qmip_disp_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_GPU_AHB_CLK] = &amp;gcc_qmip_gpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &amp;gcc_qmip_video_cv_cpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &amp;gcc_qmip_video_cvp_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &amp;gcc_qmip_video_v_cpu_ahb_clk.clkr,</div><div class='add'>+	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &amp;gcc_qmip_video_vcodec_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &amp;gcc_qupv3_wrap0_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_CORE_CLK] = &amp;gcc_qupv3_wrap0_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &amp;gcc_qupv3_wrap0_qspi_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &amp;gcc_qupv3_wrap0_qspi_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S0_CLK] = &amp;gcc_qupv3_wrap0_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &amp;gcc_qupv3_wrap0_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S1_CLK] = &amp;gcc_qupv3_wrap0_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &amp;gcc_qupv3_wrap0_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S2_CLK] = &amp;gcc_qupv3_wrap0_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &amp;gcc_qupv3_wrap0_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap0_s2_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S3_CLK] = &amp;gcc_qupv3_wrap0_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &amp;gcc_qupv3_wrap0_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap0_s3_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S4_CLK] = &amp;gcc_qupv3_wrap0_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &amp;gcc_qupv3_wrap0_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S5_CLK] = &amp;gcc_qupv3_wrap0_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &amp;gcc_qupv3_wrap0_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S6_CLK] = &amp;gcc_qupv3_wrap0_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &amp;gcc_qupv3_wrap0_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S7_CLK] = &amp;gcc_qupv3_wrap0_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &amp;gcc_qupv3_wrap0_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &amp;gcc_qupv3_wrap1_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_CORE_CLK] = &amp;gcc_qupv3_wrap1_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &amp;gcc_qupv3_wrap1_qspi_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &amp;gcc_qupv3_wrap1_qspi_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S0_CLK] = &amp;gcc_qupv3_wrap1_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &amp;gcc_qupv3_wrap1_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S1_CLK] = &amp;gcc_qupv3_wrap1_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &amp;gcc_qupv3_wrap1_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S2_CLK] = &amp;gcc_qupv3_wrap1_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &amp;gcc_qupv3_wrap1_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap1_s2_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S3_CLK] = &amp;gcc_qupv3_wrap1_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &amp;gcc_qupv3_wrap1_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap1_s3_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S4_CLK] = &amp;gcc_qupv3_wrap1_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &amp;gcc_qupv3_wrap1_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S5_CLK] = &amp;gcc_qupv3_wrap1_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &amp;gcc_qupv3_wrap1_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S6_CLK] = &amp;gcc_qupv3_wrap1_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &amp;gcc_qupv3_wrap1_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S7_CLK] = &amp;gcc_qupv3_wrap1_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &amp;gcc_qupv3_wrap1_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &amp;gcc_qupv3_wrap2_core_2x_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_CORE_CLK] = &amp;gcc_qupv3_wrap2_core_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &amp;gcc_qupv3_wrap2_qspi_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &amp;gcc_qupv3_wrap2_qspi_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S0_CLK] = &amp;gcc_qupv3_wrap2_s0_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &amp;gcc_qupv3_wrap2_s0_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S1_CLK] = &amp;gcc_qupv3_wrap2_s1_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &amp;gcc_qupv3_wrap2_s1_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S2_CLK] = &amp;gcc_qupv3_wrap2_s2_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &amp;gcc_qupv3_wrap2_s2_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap2_s2_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S3_CLK] = &amp;gcc_qupv3_wrap2_s3_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &amp;gcc_qupv3_wrap2_s3_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &amp;gcc_qupv3_wrap2_s3_div_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S4_CLK] = &amp;gcc_qupv3_wrap2_s4_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &amp;gcc_qupv3_wrap2_s4_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S5_CLK] = &amp;gcc_qupv3_wrap2_s5_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &amp;gcc_qupv3_wrap2_s5_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S6_CLK] = &amp;gcc_qupv3_wrap2_s6_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &amp;gcc_qupv3_wrap2_s6_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S7_CLK] = &amp;gcc_qupv3_wrap2_s7_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &amp;gcc_qupv3_wrap2_s7_clk_src.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &amp;gcc_qupv3_wrap_0_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &amp;gcc_qupv3_wrap_0_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &amp;gcc_qupv3_wrap_1_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &amp;gcc_qupv3_wrap_1_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &amp;gcc_qupv3_wrap_2_m_ahb_clk.clkr,</div><div class='add'>+	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &amp;gcc_qupv3_wrap_2_s_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_AHB_CLK] = &amp;gcc_sdcc2_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_APPS_CLK] = &amp;gcc_sdcc2_apps_clk.clkr,</div><div class='add'>+	[GCC_SDCC2_APPS_CLK_SRC] = &amp;gcc_sdcc2_apps_clk_src.clkr,</div><div class='add'>+	[GCC_SDCC4_AHB_CLK] = &amp;gcc_sdcc4_ahb_clk.clkr,</div><div class='add'>+	[GCC_SDCC4_APPS_CLK] = &amp;gcc_sdcc4_apps_clk.clkr,</div><div class='add'>+	[GCC_SDCC4_APPS_CLK_SRC] = &amp;gcc_sdcc4_apps_clk_src.clkr,</div><div class='add'>+	[GCC_SYS_NOC_USB_AXI_CLK] = &amp;gcc_sys_noc_usb_axi_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AHB_CLK] = &amp;gcc_ufs_phy_ahb_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AXI_CLK] = &amp;gcc_ufs_phy_axi_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_AXI_CLK_SRC] = &amp;gcc_ufs_phy_axi_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_ICE_CORE_CLK] = &amp;gcc_ufs_phy_ice_core_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &amp;gcc_ufs_phy_ice_core_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_PHY_AUX_CLK] = &amp;gcc_ufs_phy_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &amp;gcc_ufs_phy_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &amp;gcc_ufs_phy_rx_symbol_0_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &amp;gcc_ufs_phy_rx_symbol_1_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &amp;gcc_ufs_phy_tx_symbol_0_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &amp;gcc_ufs_phy_unipro_core_clk.clkr,</div><div class='add'>+	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &amp;gcc_ufs_phy_unipro_core_clk_src.clkr,</div><div class='add'>+	[GCC_USB20_MASTER_CLK] = &amp;gcc_usb20_master_clk.clkr,</div><div class='add'>+	[GCC_USB20_MASTER_CLK_SRC] = &amp;gcc_usb20_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB20_MOCK_UTMI_CLK] = &amp;gcc_usb20_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb20_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb20_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB20_SLEEP_CLK] = &amp;gcc_usb20_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB30_MP_MASTER_CLK] = &amp;gcc_usb30_mp_master_clk.clkr,</div><div class='add'>+	[GCC_USB30_MP_MASTER_CLK_SRC] = &amp;gcc_usb30_mp_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_MP_MOCK_UTMI_CLK] = &amp;gcc_usb30_mp_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb30_mp_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_MP_SLEEP_CLK] = &amp;gcc_usb30_mp_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MASTER_CLK] = &amp;gcc_usb30_prim_master_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &amp;gcc_usb30_prim_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &amp;gcc_usb30_prim_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb30_prim_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_PRIM_SLEEP_CLK] = &amp;gcc_usb30_prim_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB30_SEC_MASTER_CLK] = &amp;gcc_usb30_sec_master_clk.clkr,</div><div class='add'>+	[GCC_USB30_SEC_MASTER_CLK_SRC] = &amp;gcc_usb30_sec_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &amp;gcc_usb30_sec_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb30_sec_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_SEC_SLEEP_CLK] = &amp;gcc_usb30_sec_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB30_TERT_MASTER_CLK] = &amp;gcc_usb30_tert_master_clk.clkr,</div><div class='add'>+	[GCC_USB30_TERT_MASTER_CLK_SRC] = &amp;gcc_usb30_tert_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_TERT_MOCK_UTMI_CLK] = &amp;gcc_usb30_tert_mock_utmi_clk.clkr,</div><div class='add'>+	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &amp;gcc_usb30_tert_mock_utmi_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &amp;gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,</div><div class='add'>+	[GCC_USB30_TERT_SLEEP_CLK] = &amp;gcc_usb30_tert_sleep_clk.clkr,</div><div class='add'>+	[GCC_USB3_MP_PHY_AUX_CLK] = &amp;gcc_usb3_mp_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &amp;gcc_usb3_mp_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &amp;gcc_usb3_mp_phy_com_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &amp;gcc_usb3_mp_phy_pipe_0_clk.clkr,</div><div class='add'>+	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &amp;gcc_usb3_mp_phy_pipe_1_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_AUX_CLK] = &amp;gcc_usb3_prim_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &amp;gcc_usb3_prim_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &amp;gcc_usb3_prim_phy_com_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &amp;gcc_usb3_prim_phy_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &amp;gcc_usb3_prim_phy_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_SEC_PHY_AUX_CLK] = &amp;gcc_usb3_sec_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &amp;gcc_usb3_sec_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &amp;gcc_usb3_sec_phy_com_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_SEC_PHY_PIPE_CLK] = &amp;gcc_usb3_sec_phy_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &amp;gcc_usb3_sec_phy_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_TERT_PHY_AUX_CLK] = &amp;gcc_usb3_tert_phy_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &amp;gcc_usb3_tert_phy_aux_clk_src.clkr,</div><div class='add'>+	[GCC_USB3_TERT_PHY_COM_AUX_CLK] = &amp;gcc_usb3_tert_phy_com_aux_clk.clkr,</div><div class='add'>+	[GCC_USB3_TERT_PHY_PIPE_CLK] = &amp;gcc_usb3_tert_phy_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &amp;gcc_usb3_tert_phy_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_0_CFG_AHB_CLK] = &amp;gcc_usb4_0_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_DP0_CLK] = &amp;gcc_usb4_0_dp0_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_DP1_CLK] = &amp;gcc_usb4_0_dp1_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_MASTER_CLK] = &amp;gcc_usb4_0_master_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_MASTER_CLK_SRC] = &amp;gcc_usb4_0_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &amp;gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &amp;gcc_usb4_0_phy_pcie_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &amp;gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_RX0_CLK] = &amp;gcc_usb4_0_phy_rx0_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_RX1_CLK] = &amp;gcc_usb4_0_phy_rx1_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &amp;gcc_usb4_0_phy_usb_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_SB_IF_CLK] = &amp;gcc_usb4_0_sb_if_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_SB_IF_CLK_SRC] = &amp;gcc_usb4_0_sb_if_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_0_SYS_CLK] = &amp;gcc_usb4_0_sys_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_TMU_CLK] = &amp;gcc_usb4_0_tmu_clk.clkr,</div><div class='add'>+	[GCC_USB4_0_TMU_CLK_SRC] = &amp;gcc_usb4_0_tmu_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_1_CFG_AHB_CLK] = &amp;gcc_usb4_1_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_DP0_CLK] = &amp;gcc_usb4_1_dp0_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_DP1_CLK] = &amp;gcc_usb4_1_dp1_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_MASTER_CLK] = &amp;gcc_usb4_1_master_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_MASTER_CLK_SRC] = &amp;gcc_usb4_1_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &amp;gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &amp;gcc_usb4_1_phy_pcie_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &amp;gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_RX0_CLK] = &amp;gcc_usb4_1_phy_rx0_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_RX1_CLK] = &amp;gcc_usb4_1_phy_rx1_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &amp;gcc_usb4_1_phy_usb_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_SB_IF_CLK] = &amp;gcc_usb4_1_sb_if_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_SB_IF_CLK_SRC] = &amp;gcc_usb4_1_sb_if_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_1_SYS_CLK] = &amp;gcc_usb4_1_sys_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_TMU_CLK] = &amp;gcc_usb4_1_tmu_clk.clkr,</div><div class='add'>+	[GCC_USB4_1_TMU_CLK_SRC] = &amp;gcc_usb4_1_tmu_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_2_CFG_AHB_CLK] = &amp;gcc_usb4_2_cfg_ahb_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_DP0_CLK] = &amp;gcc_usb4_2_dp0_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_DP1_CLK] = &amp;gcc_usb4_2_dp1_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_MASTER_CLK] = &amp;gcc_usb4_2_master_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_MASTER_CLK_SRC] = &amp;gcc_usb4_2_master_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &amp;gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &amp;gcc_usb4_2_phy_pcie_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &amp;gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_RX0_CLK] = &amp;gcc_usb4_2_phy_rx0_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_RX1_CLK] = &amp;gcc_usb4_2_phy_rx1_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &amp;gcc_usb4_2_phy_usb_pipe_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_SB_IF_CLK] = &amp;gcc_usb4_2_sb_if_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_SB_IF_CLK_SRC] = &amp;gcc_usb4_2_sb_if_clk_src.clkr,</div><div class='add'>+	[GCC_USB4_2_SYS_CLK] = &amp;gcc_usb4_2_sys_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_TMU_CLK] = &amp;gcc_usb4_2_tmu_clk.clkr,</div><div class='add'>+	[GCC_USB4_2_TMU_CLK_SRC] = &amp;gcc_usb4_2_tmu_clk_src.clkr,</div><div class='add'>+	[GCC_VIDEO_AXI0_CLK] = &amp;gcc_video_axi0_clk.clkr,</div><div class='add'>+	[GCC_VIDEO_AXI1_CLK] = &amp;gcc_video_axi1_clk.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc *gcc_x1e80100_gdscs[] = {</div><div class='add'>+	[GCC_PCIE_0_TUNNEL_GDSC] = &amp;gcc_pcie_0_tunnel_gdsc,</div><div class='add'>+	[GCC_PCIE_1_TUNNEL_GDSC] = &amp;gcc_pcie_1_tunnel_gdsc,</div><div class='add'>+	[GCC_PCIE_2_TUNNEL_GDSC] = &amp;gcc_pcie_2_tunnel_gdsc,</div><div class='add'>+	[GCC_PCIE_3_GDSC] = &amp;gcc_pcie_3_gdsc,</div><div class='add'>+	[GCC_PCIE_3_PHY_GDSC] = &amp;gcc_pcie_3_phy_gdsc,</div><div class='add'>+	[GCC_PCIE_4_GDSC] = &amp;gcc_pcie_4_gdsc,</div><div class='add'>+	[GCC_PCIE_4_PHY_GDSC] = &amp;gcc_pcie_4_phy_gdsc,</div><div class='add'>+	[GCC_PCIE_5_GDSC] = &amp;gcc_pcie_5_gdsc,</div><div class='add'>+	[GCC_PCIE_5_PHY_GDSC] = &amp;gcc_pcie_5_phy_gdsc,</div><div class='add'>+	[GCC_PCIE_6_PHY_GDSC] = &amp;gcc_pcie_6_phy_gdsc,</div><div class='add'>+	[GCC_PCIE_6A_GDSC] = &amp;gcc_pcie_6a_gdsc,</div><div class='add'>+	[GCC_PCIE_6B_GDSC] = &amp;gcc_pcie_6b_gdsc,</div><div class='add'>+	[GCC_UFS_MEM_PHY_GDSC] = &amp;gcc_ufs_mem_phy_gdsc,</div><div class='add'>+	[GCC_UFS_PHY_GDSC] = &amp;gcc_ufs_phy_gdsc,</div><div class='add'>+	[GCC_USB20_PRIM_GDSC] = &amp;gcc_usb20_prim_gdsc,</div><div class='add'>+	[GCC_USB30_MP_GDSC] = &amp;gcc_usb30_mp_gdsc,</div><div class='add'>+	[GCC_USB30_PRIM_GDSC] = &amp;gcc_usb30_prim_gdsc,</div><div class='add'>+	[GCC_USB30_SEC_GDSC] = &amp;gcc_usb30_sec_gdsc,</div><div class='add'>+	[GCC_USB30_TERT_GDSC] = &amp;gcc_usb30_tert_gdsc,</div><div class='add'>+	[GCC_USB3_MP_SS0_PHY_GDSC] = &amp;gcc_usb3_mp_ss0_phy_gdsc,</div><div class='add'>+	[GCC_USB3_MP_SS1_PHY_GDSC] = &amp;gcc_usb3_mp_ss1_phy_gdsc,</div><div class='add'>+	[GCC_USB4_0_GDSC] = &amp;gcc_usb4_0_gdsc,</div><div class='add'>+	[GCC_USB4_1_GDSC] = &amp;gcc_usb4_1_gdsc,</div><div class='add'>+	[GCC_USB4_2_GDSC] = &amp;gcc_usb4_2_gdsc,</div><div class='add'>+	[GCC_USB_0_PHY_GDSC] = &amp;gcc_usb_0_phy_gdsc,</div><div class='add'>+	[GCC_USB_1_PHY_GDSC] = &amp;gcc_usb_1_phy_gdsc,</div><div class='add'>+	[GCC_USB_2_PHY_GDSC] = &amp;gcc_usb_2_phy_gdsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map gcc_x1e80100_resets[] = {</div><div class='add'>+	[GCC_AV1E_BCR] = { 0x4a000 },</div><div class='add'>+	[GCC_CAMERA_BCR] = { 0x26000 },</div><div class='add'>+	[GCC_DISPLAY_BCR] = { 0x27000 },</div><div class='add'>+	[GCC_GPU_BCR] = { 0x71000 },</div><div class='add'>+	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },</div><div class='add'>+	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },</div><div class='add'>+	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },</div><div class='add'>+	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },</div><div class='add'>+	[GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },</div><div class='add'>+	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },</div><div class='add'>+	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },</div><div class='add'>+	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },</div><div class='add'>+	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },</div><div class='add'>+	[GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },</div><div class='add'>+	[GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },</div><div class='add'>+	[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },</div><div class='add'>+	[GCC_PCIE_2_PHY_BCR] = { 0xa501c },</div><div class='add'>+	[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },</div><div class='add'>+	[GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },</div><div class='add'>+	[GCC_PCIE_3_BCR] = { 0x58000 },</div><div class='add'>+	[GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },</div><div class='add'>+	[GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },</div><div class='add'>+	[GCC_PCIE_3_PHY_BCR] = { 0xab01c },</div><div class='add'>+	[GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },</div><div class='add'>+	[GCC_PCIE_4_BCR] = { 0x6b000 },</div><div class='add'>+	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },</div><div class='add'>+	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },</div><div class='add'>+	[GCC_PCIE_4_PHY_BCR] = { 0xb301c },</div><div class='add'>+	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },</div><div class='add'>+	[GCC_PCIE_5_BCR] = { 0x2f000 },</div><div class='add'>+	[GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },</div><div class='add'>+	[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },</div><div class='add'>+	[GCC_PCIE_5_PHY_BCR] = { 0xaa01c },</div><div class='add'>+	[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },</div><div class='add'>+	[GCC_PCIE_6A_BCR] = { 0x31000 },</div><div class='add'>+	[GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },</div><div class='add'>+	[GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },</div><div class='add'>+	[GCC_PCIE_6A_PHY_BCR] = { 0xac01c },</div><div class='add'>+	[GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },</div><div class='add'>+	[GCC_PCIE_6B_BCR] = { 0x8d000 },</div><div class='add'>+	[GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },</div><div class='add'>+	[GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },</div><div class='add'>+	[GCC_PCIE_6B_PHY_BCR] = { 0xb501c },</div><div class='add'>+	[GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },</div><div class='add'>+	[GCC_PCIE_PHY_BCR] = { 0x6f000 },</div><div class='add'>+	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },</div><div class='add'>+	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },</div><div class='add'>+	[GCC_PCIE_RSCC_BCR] = { 0xa4000 },</div><div class='add'>+	[GCC_PDM_BCR] = { 0x33000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },</div><div class='add'>+	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },</div><div class='add'>+	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },</div><div class='add'>+	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },</div><div class='add'>+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },</div><div class='add'>+	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },</div><div class='add'>+	[GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },</div><div class='add'>+	[GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },</div><div class='add'>+	[GCC_SDCC2_BCR] = { 0x14000 },</div><div class='add'>+	[GCC_SDCC4_BCR] = { 0x16000 },</div><div class='add'>+	[GCC_UFS_PHY_BCR] = { 0x77000 },</div><div class='add'>+	[GCC_USB20_PRIM_BCR] = { 0x29000 },</div><div class='add'>+	[GCC_USB30_MP_BCR] = { 0x17000 },</div><div class='add'>+	[GCC_USB30_PRIM_BCR] = { 0x39000 },</div><div class='add'>+	[GCC_USB30_SEC_BCR] = { 0xa1000 },</div><div class='add'>+	[GCC_USB30_TERT_BCR] = { 0xa2000 },</div><div class='add'>+	[GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },</div><div class='add'>+	[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },</div><div class='add'>+	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },</div><div class='add'>+	[GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },</div><div class='add'>+	[GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },</div><div class='add'>+	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },</div><div class='add'>+	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },</div><div class='add'>+	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },</div><div class='add'>+	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },</div><div class='add'>+	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },</div><div class='add'>+	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },</div><div class='add'>+	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },</div><div class='add'>+	[GCC_USB4_0_BCR] = { 0x9f000 },</div><div class='add'>+	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },</div><div class='add'>+	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },</div><div class='add'>+	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },</div><div class='add'>+	[GCC_USB4_1_BCR] = { 0x2b000 },</div><div class='add'>+	[GCC_USB4_2_BCR] = { 0x11000 },</div><div class='add'>+	[GCC_USB_0_PHY_BCR] = { 0x50020 },</div><div class='add'>+	[GCC_USB_1_PHY_BCR] = { 0x2a020 },</div><div class='add'>+	[GCC_USB_2_PHY_BCR] = { 0xa3020 },</div><div class='add'>+	[GCC_VIDEO_BCR] = { 0x32000 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),</div><div class='add'>+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config gcc_x1e80100_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x1f41f0,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_cc_desc gcc_x1e80100_desc = {</div><div class='add'>+	.config = &amp;gcc_x1e80100_regmap_config,</div><div class='add'>+	.clks = gcc_x1e80100_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(gcc_x1e80100_clocks),</div><div class='add'>+	.resets = gcc_x1e80100_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),</div><div class='add'>+	.gdscs = gcc_x1e80100_gdscs,</div><div class='add'>+	.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gcc_x1e80100_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,x1e80100-gcc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table);</div><div class='add'>+</div><div class='add'>+static int gcc_x1e80100_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;gcc_x1e80100_desc);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+</div><div class='add'>+	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,</div><div class='add'>+				       ARRAY_SIZE(gcc_dfs_clocks));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Keep the critical clock always-On */</div><div class='add'>+	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */</div><div class='add'>+	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */</div><div class='add'>+</div><div class='add'>+	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */</div><div class='add'>+	regmap_write(regmap, 0x52224, 0x0);</div><div class='add'>+</div><div class='add'>+	return qcom_cc_really_probe(pdev, &amp;gcc_x1e80100_desc, regmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver gcc_x1e80100_driver = {</div><div class='add'>+	.probe = gcc_x1e80100_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "gcc-x1e80100",</div><div class='add'>+		.of_match_table = gcc_x1e80100_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init gcc_x1e80100_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;gcc_x1e80100_driver);</div><div class='add'>+}</div><div class='add'>+subsys_initcall(gcc_x1e80100_init);</div><div class='add'>+</div><div class='add'>+static void __exit gcc_x1e80100_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;gcc_x1e80100_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(gcc_x1e80100_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI GCC X1E80100 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c<br/>index 8422fd047493..c89a5b59ddb7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gpucc-sm8150.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/gpucc-sm8150.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gpucc-sm8150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8150.c</a></div><div class='hunk'>@@ -37,8 +37,8 @@ static struct alpha_pll_config gpu_cc_pll1_config = {</div><div class='ctx'> 	.config_ctl_hi_val = 0x00002267,</div><div class='ctx'> 	.config_ctl_hi1_val = 0x00000024,</div><div class='ctx'> 	.test_ctl_val = 0x00000000,</div><div class='del'>-	.test_ctl_hi_val = 0x00000002,</div><div class='del'>-	.test_ctl_hi1_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi1_val = 0x00000020,</div><div class='ctx'> 	.user_ctl_val = 0x00000000,</div><div class='ctx'> 	.user_ctl_hi_val = 0x00000805,</div><div class='ctx'> 	.user_ctl_hi1_val = 0x000000d0,</div><div class='head'>diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c<br/>index 420dcb27b47d..2fa8673424d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gpucc-sm8550.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/gpucc-sm8550.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gpucc-sm8550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8550.c</a></div><div class='hunk'>@@ -35,12 +35,12 @@ enum {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct pll_vco lucid_ole_vco[] = {</div><div class='del'>-	{ 249600000, 2300000000, 0 },</div><div class='add'>+	{ 249600000, 2000000000, 0 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct alpha_pll_config gpu_cc_pll0_config = {</div><div class='del'>-	.l = 0x0d,</div><div class='del'>-	.alpha = 0x0,</div><div class='add'>+	.l = 0x1e,</div><div class='add'>+	.alpha = 0xbaaa,</div><div class='ctx'> 	.config_ctl_val = 0x20485699,</div><div class='ctx'> 	.config_ctl_hi_val = 0x00182261,</div><div class='ctx'> 	.config_ctl_hi1_val = 0x82aa299c,</div><div class='head'>diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c<br/>new file mode 100644<br/>index 000000000000..03307e482aca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/gpucc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/gpucc-sm8650.c</a></div><div class='hunk'>@@ -0,0 +1,663 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sm8650-gpucc.h&gt;</div><div class='add'>+#include &lt;dt-bindings/reset/qcom,sm8650-gpucc.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-alpha-pll.h"</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-rcg.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "clk-regmap-divider.h"</div><div class='add'>+#include "clk-regmap-mux.h"</div><div class='add'>+#include "clk-regmap-phy-mux.h"</div><div class='add'>+#include "gdsc.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO,</div><div class='add'>+	DT_GPLL0_OUT_MAIN,</div><div class='add'>+	DT_GPLL0_OUT_MAIN_DIV,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	P_BI_TCXO,</div><div class='add'>+	P_GPLL0_OUT_MAIN,</div><div class='add'>+	P_GPLL0_OUT_MAIN_DIV,</div><div class='add'>+	P_GPU_CC_PLL0_OUT_MAIN,</div><div class='add'>+	P_GPU_CC_PLL1_OUT_MAIN,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct pll_vco lucid_ole_vco[] = {</div><div class='add'>+	{ 249600000, 2100000000, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct alpha_pll_config gpu_cc_pll0_config = {</div><div class='add'>+	.l = 0x20,</div><div class='add'>+	.alpha = 0x4aaa,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000005,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gpu_cc_pll0 = {</div><div class='add'>+	.offset = 0x0,</div><div class='add'>+	.vco_table = lucid_ole_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_ole_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_pll0",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_evo_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct alpha_pll_config gpu_cc_pll1_config = {</div><div class='add'>+	.l = 0x1b,</div><div class='add'>+	.alpha = 0x1555,</div><div class='add'>+	.config_ctl_val = 0x20485699,</div><div class='add'>+	.config_ctl_hi_val = 0x00182261,</div><div class='add'>+	.config_ctl_hi1_val = 0x82aa299c,</div><div class='add'>+	.test_ctl_val = 0x00000000,</div><div class='add'>+	.test_ctl_hi_val = 0x00000003,</div><div class='add'>+	.test_ctl_hi1_val = 0x00009000,</div><div class='add'>+	.test_ctl_hi2_val = 0x00000034,</div><div class='add'>+	.user_ctl_val = 0x00000000,</div><div class='add'>+	.user_ctl_hi_val = 0x00000005,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_alpha_pll gpu_cc_pll1 = {</div><div class='add'>+	.offset = 0x1000,</div><div class='add'>+	.vco_table = lucid_ole_vco,</div><div class='add'>+	.num_vco = ARRAY_SIZE(lucid_ole_vco),</div><div class='add'>+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],</div><div class='add'>+	.clkr = {</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_pll1",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_alpha_pll_lucid_evo_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gpu_cc_parent_map_0[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN_DIV, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gpu_cc_parent_data_0[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN_DIV },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gpu_cc_parent_map_1[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },</div><div class='add'>+	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN_DIV, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gpu_cc_parent_data_1[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gpu_cc_pll0.clkr.hw },</div><div class='add'>+	{ .hw = &amp;gpu_cc_pll1.clkr.hw },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN_DIV },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct parent_map gpu_cc_parent_map_2[] = {</div><div class='add'>+	{ P_BI_TCXO, 0 },</div><div class='add'>+	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN, 5 },</div><div class='add'>+	{ P_GPLL0_OUT_MAIN_DIV, 6 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_parent_data gpu_cc_parent_data_2[] = {</div><div class='add'>+	{ .index = DT_BI_TCXO },</div><div class='add'>+	{ .hw = &amp;gpu_cc_pll1.clkr.hw },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN },</div><div class='add'>+	{ .index = DT_GPLL0_OUT_MAIN_DIV },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {</div><div class='add'>+	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gpu_cc_ff_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9474,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gpu_cc_parent_map_0,</div><div class='add'>+	.freq_tbl = ftbl_gpu_cc_ff_clk_src,</div><div class='add'>+	.hw_clk_ctrl = true,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "gpu_cc_ff_clk_src",</div><div class='add'>+		.parent_data = gpu_cc_parent_data_0,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {</div><div class='add'>+	F(19200000, P_BI_TCXO, 1, 0, 0),</div><div class='add'>+	F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gpu_cc_gmu_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x9318,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gpu_cc_parent_map_1,</div><div class='add'>+	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,</div><div class='add'>+	.hw_clk_ctrl = true,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "gpu_cc_gmu_clk_src",</div><div class='add'>+		.parent_data = gpu_cc_parent_data_1,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {</div><div class='add'>+	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),</div><div class='add'>+	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_rcg2 gpu_cc_hub_clk_src = {</div><div class='add'>+	.cmd_rcgr = 0x93ec,</div><div class='add'>+	.mnd_width = 0,</div><div class='add'>+	.hid_width = 5,</div><div class='add'>+	.parent_map = gpu_cc_parent_map_2,</div><div class='add'>+	.freq_tbl = ftbl_gpu_cc_hub_clk_src,</div><div class='add'>+	.hw_clk_ctrl = true,</div><div class='add'>+	.clkr.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+		.name = "gpu_cc_hub_clk_src",</div><div class='add'>+		.parent_data = gpu_cc_parent_data_2,</div><div class='add'>+		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_rcg2_shared_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap_div gpu_cc_hub_div_clk_src = {</div><div class='add'>+	.reg = 0x942c,</div><div class='add'>+	.shift = 0,</div><div class='add'>+	.width = 4,</div><div class='add'>+	.clkr.hw.init = &amp;(const struct clk_init_data) {</div><div class='add'>+		.name = "gpu_cc_hub_div_clk_src",</div><div class='add'>+		.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+			&amp;gpu_cc_hub_clk_src.clkr.hw,</div><div class='add'>+		},</div><div class='add'>+		.num_parents = 1,</div><div class='add'>+		.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+		.ops = &amp;clk_regmap_div_ro_ops,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x911c,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x911c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_hub_div_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_crc_ahb_clk = {</div><div class='add'>+	.halt_reg = 0x9120,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9120,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_crc_ahb_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_hub_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_cx_accu_shift_clk = {</div><div class='add'>+	.halt_reg = 0x9160,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9160,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_cx_accu_shift_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_cx_ff_clk = {</div><div class='add'>+	.halt_reg = 0x914c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x914c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_cx_ff_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_ff_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_cx_gmu_clk = {</div><div class='add'>+	.halt_reg = 0x913c,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x913c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_cx_gmu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_gmu_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_aon_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_cxo_aon_clk = {</div><div class='add'>+	.halt_reg = 0x9004,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9004,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_cxo_aon_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_cxo_clk = {</div><div class='add'>+	.halt_reg = 0x9144,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9144,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_cxo_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_demet_clk = {</div><div class='add'>+	.halt_reg = 0x900c,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x900c,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_demet_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_aon_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_freq_measure_clk = {</div><div class='add'>+	.halt_reg = 0x9008,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9008,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_freq_measure_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_gfx3d_clk = {</div><div class='add'>+	.halt_reg = 0x90a8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90a8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_gfx3d_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = {</div><div class='add'>+	.halt_reg = 0x90c8,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90c8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_gfx3d_rdvm_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_gmu_clk = {</div><div class='add'>+	.halt_reg = 0x90bc,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90bc,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_gmu_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_gmu_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_vsense_clk = {</div><div class='add'>+	.halt_reg = 0x90b0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90b0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_vsense_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_accu_shift_clk = {</div><div class='add'>+	.halt_reg = 0x90d0,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90d0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_accu_shift_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_gx_ff_clk = {</div><div class='add'>+	.halt_reg = 0x90c0,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x90c0,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_gx_ff_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_ff_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {</div><div class='add'>+	.halt_reg = 0x7000,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x7000,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_hub_aon_clk = {</div><div class='add'>+	.halt_reg = 0x93e8,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x93e8,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_hub_aon_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_hub_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_aon_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_hub_cx_int_clk = {</div><div class='add'>+	.halt_reg = 0x9148,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9148,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_hub_cx_int_clk",</div><div class='add'>+			.parent_hws = (const struct clk_hw*[]){</div><div class='add'>+				&amp;gpu_cc_hub_clk_src.clkr.hw,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.flags = CLK_SET_RATE_PARENT,</div><div class='add'>+			.ops = &amp;clk_branch2_aon_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_memnoc_gfx_clk = {</div><div class='add'>+	.halt_reg = 0x9150,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9150,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_memnoc_gfx_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_sleep_clk = {</div><div class='add'>+	.halt_reg = 0x9134,</div><div class='add'>+	.halt_check = BRANCH_HALT_VOTED,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9134,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_sleep_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch gpu_cc_dpm_clk = {</div><div class='add'>+	.halt_reg = 0x9164,</div><div class='add'>+	.halt_check = BRANCH_HALT,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x9164,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(const struct clk_init_data){</div><div class='add'>+			.name = "gpu_cc_dpm_clk",</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gpu_cx_gdsc = {</div><div class='add'>+	.gdscr = 0x9108,</div><div class='add'>+	.gds_hw_ctrl = 0x9168,</div><div class='add'>+	.clk_dis_wait_val = 8,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gpu_cx_gdsc",</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = VOTABLE | RETAIN_FF_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc gpu_gx_gdsc = {</div><div class='add'>+	.gdscr = 0x905c,</div><div class='add'>+	.clamp_io_ctrl = 0x9504,</div><div class='add'>+	.resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR,</div><div class='add'>+				     GPUCC_GPU_CC_ACD_BCR,</div><div class='add'>+				     GPUCC_GPU_CC_GX_ACD_IROOT_BCR },</div><div class='add'>+	.reset_count = 3,</div><div class='add'>+	.pd = {</div><div class='add'>+		.name = "gpu_gx_gdsc",</div><div class='add'>+		.power_on = gdsc_gx_do_nothing_enable,</div><div class='add'>+	},</div><div class='add'>+	.pwrsts = PWRSTS_OFF_ON,</div><div class='add'>+	.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *gpu_cc_sm8650_clocks[] = {</div><div class='add'>+	[GPU_CC_AHB_CLK] = &amp;gpu_cc_ahb_clk.clkr,</div><div class='add'>+	[GPU_CC_CRC_AHB_CLK] = &amp;gpu_cc_crc_ahb_clk.clkr,</div><div class='add'>+	[GPU_CC_CX_ACCU_SHIFT_CLK] = &amp;gpu_cc_cx_accu_shift_clk.clkr,</div><div class='add'>+	[GPU_CC_CX_FF_CLK] = &amp;gpu_cc_cx_ff_clk.clkr,</div><div class='add'>+	[GPU_CC_CX_GMU_CLK] = &amp;gpu_cc_cx_gmu_clk.clkr,</div><div class='add'>+	[GPU_CC_CXO_AON_CLK] = &amp;gpu_cc_cxo_aon_clk.clkr,</div><div class='add'>+	[GPU_CC_CXO_CLK] = &amp;gpu_cc_cxo_clk.clkr,</div><div class='add'>+	[GPU_CC_DEMET_CLK] = &amp;gpu_cc_demet_clk.clkr,</div><div class='add'>+	[GPU_CC_DPM_CLK] = &amp;gpu_cc_dpm_clk.clkr,</div><div class='add'>+	[GPU_CC_FF_CLK_SRC] = &amp;gpu_cc_ff_clk_src.clkr,</div><div class='add'>+	[GPU_CC_FREQ_MEASURE_CLK] = &amp;gpu_cc_freq_measure_clk.clkr,</div><div class='add'>+	[GPU_CC_GMU_CLK_SRC] = &amp;gpu_cc_gmu_clk_src.clkr,</div><div class='add'>+	[GPU_CC_GX_ACCU_SHIFT_CLK] = &amp;gpu_cc_gx_accu_shift_clk.clkr,</div><div class='add'>+	[GPU_CC_GX_FF_CLK] = &amp;gpu_cc_gx_ff_clk.clkr,</div><div class='add'>+	[GPU_CC_GX_GFX3D_CLK] = &amp;gpu_cc_gx_gfx3d_clk.clkr,</div><div class='add'>+	[GPU_CC_GX_GFX3D_RDVM_CLK] = &amp;gpu_cc_gx_gfx3d_rdvm_clk.clkr,</div><div class='add'>+	[GPU_CC_GX_GMU_CLK] = &amp;gpu_cc_gx_gmu_clk.clkr,</div><div class='add'>+	[GPU_CC_GX_VSENSE_CLK] = &amp;gpu_cc_gx_vsense_clk.clkr,</div><div class='add'>+	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &amp;gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,</div><div class='add'>+	[GPU_CC_HUB_AON_CLK] = &amp;gpu_cc_hub_aon_clk.clkr,</div><div class='add'>+	[GPU_CC_HUB_CLK_SRC] = &amp;gpu_cc_hub_clk_src.clkr,</div><div class='add'>+	[GPU_CC_HUB_CX_INT_CLK] = &amp;gpu_cc_hub_cx_int_clk.clkr,</div><div class='add'>+	[GPU_CC_HUB_DIV_CLK_SRC] = &amp;gpu_cc_hub_div_clk_src.clkr,</div><div class='add'>+	[GPU_CC_MEMNOC_GFX_CLK] = &amp;gpu_cc_memnoc_gfx_clk.clkr,</div><div class='add'>+	[GPU_CC_PLL0] = &amp;gpu_cc_pll0.clkr,</div><div class='add'>+	[GPU_CC_PLL1] = &amp;gpu_cc_pll1.clkr,</div><div class='add'>+	[GPU_CC_SLEEP_CLK] = &amp;gpu_cc_sleep_clk.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_reset_map gpu_cc_sm8650_resets[] = {</div><div class='add'>+	[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },</div><div class='add'>+	[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },</div><div class='add'>+	[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },</div><div class='add'>+	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },</div><div class='add'>+	[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },</div><div class='add'>+	[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },</div><div class='add'>+	[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },</div><div class='add'>+	[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },</div><div class='add'>+	[GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct gdsc *gpu_cc_sm8650_gdscs[] = {</div><div class='add'>+	[GPU_CX_GDSC] = &amp;gpu_cx_gdsc,</div><div class='add'>+	[GPU_GX_GDSC] = &amp;gpu_gx_gdsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config gpu_cc_sm8650_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0xa000,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_cc_desc gpu_cc_sm8650_desc = {</div><div class='add'>+	.config = &amp;gpu_cc_sm8650_regmap_config,</div><div class='add'>+	.clks = gpu_cc_sm8650_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks),</div><div class='add'>+	.resets = gpu_cc_sm8650_resets,</div><div class='add'>+	.num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets),</div><div class='add'>+	.gdscs = gpu_cc_sm8650_gdscs,</div><div class='add'>+	.num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gpu_cc_sm8650_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,sm8650-gpucc" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table);</div><div class='add'>+</div><div class='add'>+static int gpu_cc_sm8650_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	regmap = qcom_cc_map(pdev, &amp;gpu_cc_sm8650_desc);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;gpu_cc_pll0, regmap, &amp;gpu_cc_pll0_config);</div><div class='add'>+	clk_lucid_ole_pll_configure(&amp;gpu_cc_pll1, regmap, &amp;gpu_cc_pll1_config);</div><div class='add'>+</div><div class='add'>+	return qcom_cc_really_probe(pdev, &amp;gpu_cc_sm8650_desc, regmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver gpu_cc_sm8650_driver = {</div><div class='add'>+	.probe = gpu_cc_sm8650_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "sm8650-gpucc",</div><div class='add'>+		.of_match_table = gpu_cc_sm8650_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_platform_driver(gpu_cc_sm8650_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/tcsrcc-sm8650.c b/drivers/clk/qcom/tcsrcc-sm8650.c<br/>new file mode 100644<br/>index 000000000000..11c7d6df48c7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/tcsrcc-sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/tcsrcc-sm8650.c</a></div><div class='hunk'>@@ -0,0 +1,182 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/qcom,sm8650-tcsr.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk-branch.h"</div><div class='add'>+#include "clk-regmap.h"</div><div class='add'>+#include "common.h"</div><div class='add'>+#include "reset.h"</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	DT_BI_TCXO_PAD,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_pcie_0_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31100,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31100,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_pcie_0_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_pcie_1_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31114,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31114,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_pcie_1_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_ufs_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31110,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31110,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_ufs_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_ufs_pad_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31104,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31104,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_ufs_pad_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_usb2_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31118,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31118,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_usb2_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_branch tcsr_usb3_clkref_en = {</div><div class='add'>+	.halt_reg = 0x31108,</div><div class='add'>+	.halt_check = BRANCH_HALT_DELAY,</div><div class='add'>+	.clkr = {</div><div class='add'>+		.enable_reg = 0x31108,</div><div class='add'>+		.enable_mask = BIT(0),</div><div class='add'>+		.hw.init = &amp;(struct clk_init_data){</div><div class='add'>+			.name = "tcsr_usb3_clkref_en",</div><div class='add'>+			.parent_data = &amp;(const struct clk_parent_data){</div><div class='add'>+				.index = DT_BI_TCXO_PAD,</div><div class='add'>+			},</div><div class='add'>+			.num_parents = 1,</div><div class='add'>+			.ops = &amp;clk_branch2_ops,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct clk_regmap *tcsr_cc_sm8650_clocks[] = {</div><div class='add'>+	[TCSR_PCIE_0_CLKREF_EN] = &amp;tcsr_pcie_0_clkref_en.clkr,</div><div class='add'>+	[TCSR_PCIE_1_CLKREF_EN] = &amp;tcsr_pcie_1_clkref_en.clkr,</div><div class='add'>+	[TCSR_UFS_CLKREF_EN] = &amp;tcsr_ufs_clkref_en.clkr,</div><div class='add'>+	[TCSR_UFS_PAD_CLKREF_EN] = &amp;tcsr_ufs_pad_clkref_en.clkr,</div><div class='add'>+	[TCSR_USB2_CLKREF_EN] = &amp;tcsr_usb2_clkref_en.clkr,</div><div class='add'>+	[TCSR_USB3_CLKREF_EN] = &amp;tcsr_usb3_clkref_en.clkr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config tcsr_cc_sm8650_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.max_register = 0x3b000,</div><div class='add'>+	.fast_io = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_cc_desc tcsr_cc_sm8650_desc = {</div><div class='add'>+	.config = &amp;tcsr_cc_sm8650_regmap_config,</div><div class='add'>+	.clks = tcsr_cc_sm8650_clocks,</div><div class='add'>+	.num_clks = ARRAY_SIZE(tcsr_cc_sm8650_clocks),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id tcsr_cc_sm8650_match_table[] = {</div><div class='add'>+	{ .compatible = "qcom,sm8650-tcsr" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, tcsr_cc_sm8650_match_table);</div><div class='add'>+</div><div class='add'>+static int tcsr_cc_sm8650_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	return qcom_cc_probe(pdev, &amp;tcsr_cc_sm8650_desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver tcsr_cc_sm8650_driver = {</div><div class='add'>+	.probe = tcsr_cc_sm8650_probe,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "tcsr_cc-sm8650",</div><div class='add'>+		.of_match_table = tcsr_cc_sm8650_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init tcsr_cc_sm8650_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;tcsr_cc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+subsys_initcall(tcsr_cc_sm8650_init);</div><div class='add'>+</div><div class='add'>+static void __exit tcsr_cc_sm8650_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;tcsr_cc_sm8650_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(tcsr_cc_sm8650_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c<br/>index 1afdbe4a249d..f1456eaa87c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/qcom/videocc-sm8150.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/qcom/videocc-sm8150.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/qcom/videocc-sm8150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/qcom/videocc-sm8150.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> #include &lt;linux/clk-provider.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/qcom,videocc-sm8150.h&gt;</div><div class='hunk'>@@ -33,6 +34,7 @@ static struct alpha_pll_config video_pll0_config = {</div><div class='ctx'> 	.config_ctl_val = 0x20485699,</div><div class='ctx'> 	.config_ctl_hi_val = 0x00002267,</div><div class='ctx'> 	.config_ctl_hi1_val = 0x00000024,</div><div class='add'>+	.test_ctl_hi1_val = 0x00000020,</div><div class='ctx'> 	.user_ctl_val = 0x00000000,</div><div class='ctx'> 	.user_ctl_hi_val = 0x00000805,</div><div class='ctx'> 	.user_ctl_hi1_val = 0x000000D0,</div><div class='hunk'>@@ -214,6 +216,10 @@ static const struct regmap_config video_cc_sm8150_regmap_config = {</div><div class='ctx'> </div><div class='ctx'> static const struct qcom_reset_map video_cc_sm8150_resets[] = {</div><div class='ctx'> 	[VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },</div><div class='add'>+	[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },</div><div class='add'>+	[VIDEO_CC_MVS0_BCR] = { 0x870 },</div><div class='add'>+	[VIDEO_CC_MVS1_BCR] = { 0x8b0 },</div><div class='add'>+	[VIDEO_CC_MVSC_BCR] = { 0x810 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct qcom_cc_desc video_cc_sm8150_desc = {</div><div class='hunk'>@@ -235,17 +241,32 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table);</div><div class='ctx'> static int video_cc_sm8150_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	regmap = qcom_cc_map(pdev, &amp;video_cc_sm8150_desc);</div><div class='del'>-	if (IS_ERR(regmap))</div><div class='add'>+	if (IS_ERR(regmap)) {</div><div class='add'>+		pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 		return PTR_ERR(regmap);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	clk_trion_pll_configure(&amp;video_pll0, regmap, &amp;video_pll0_config);</div><div class='ctx'> </div><div class='ctx'> 	/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */</div><div class='ctx'> 	regmap_update_bits(regmap, 0x984, 0x1, 0x1);</div><div class='ctx'> </div><div class='del'>-	return qcom_cc_really_probe(pdev, &amp;video_cc_sm8150_desc, regmap);</div><div class='add'>+	ret = qcom_cc_really_probe(pdev, &amp;video_cc_sm8150_desc, regmap);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver video_cc_sm8150_driver = {</div><div class='head'>diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c<br/>index 7cc580d67362..5974adcef3ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/renesas/r8a779g0-cpg-mssr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/renesas/r8a779g0-cpg-mssr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/renesas/r8a779g0-cpg-mssr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/r8a779g0-cpg-mssr.c</a></div><div class='hunk'>@@ -192,6 +192,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {</div><div class='ctx'> 	DEF_MOD("msi3",		621,	R8A779G0_CLK_MSO),</div><div class='ctx'> 	DEF_MOD("msi4",		622,	R8A779G0_CLK_MSO),</div><div class='ctx'> 	DEF_MOD("msi5",		623,	R8A779G0_CLK_MSO),</div><div class='add'>+	DEF_MOD("pciec0",	624,	R8A779G0_CLK_S0D2_HSC),</div><div class='add'>+	DEF_MOD("pscie1",	625,	R8A779G0_CLK_S0D2_HSC),</div><div class='ctx'> 	DEF_MOD("pwm",		628,	R8A779G0_CLK_SASYNCPERD4),</div><div class='ctx'> 	DEF_MOD("rpc-if",	629,	R8A779G0_CLK_RPCD2),</div><div class='ctx'> 	DEF_MOD("scif0",	702,	R8A779G0_CLK_SASYNCPERD4),</div><div class='hunk'>@@ -235,6 +237,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {</div><div class='ctx'> 	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),</div><div class='ctx'> 	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CL16M),</div><div class='ctx'> 	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),</div><div class='add'>+	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),</div><div class='ctx'> 	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),</div><div class='ctx'> 	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c<br/>index 4394cb241d99..2582ba95256e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/renesas/r9a08g045-cpg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/renesas/r9a08g045-cpg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/renesas/r9a08g045-cpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/r9a08g045-cpg.c</a></div><div class='hunk'>@@ -181,13 +181,16 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {</div><div class='ctx'> 	DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,</div><div class='ctx'> 		    dtable_1_32, 0, 0, 0, NULL),</div><div class='ctx'> 	DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),</div><div class='add'>+	DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),</div><div class='ctx'> 	DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),</div><div class='ctx'> 	DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),</div><div class='ctx'> 	DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),</div><div class='add'>+	DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {</div><div class='ctx'> 	DEF_MOD("gic_gicclk",		R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),</div><div class='add'>+	DEF_MOD("ia55_pclk",		R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),</div><div class='ctx'> 	DEF_MOD("ia55_clk",		R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),</div><div class='ctx'> 	DEF_MOD("dmac_aclk",		R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),</div><div class='ctx'> 	DEF_MOD("sdhi0_imclk",		R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),</div><div class='hunk'>@@ -202,6 +205,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {</div><div class='ctx'> 	DEF_MOD("sdhi2_imclk2",		R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),</div><div class='ctx'> 	DEF_MOD("sdhi2_clk_hs",		R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),</div><div class='ctx'> 	DEF_MOD("sdhi2_aclk",		R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),</div><div class='add'>+	DEF_COUPLED("eth0_axi",		R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),</div><div class='add'>+	DEF_COUPLED("eth0_chi",		R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),</div><div class='add'>+	DEF_MOD("eth0_refclk",		R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),</div><div class='add'>+	DEF_COUPLED("eth1_axi",		R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),</div><div class='add'>+	DEF_COUPLED("eth1_chi",		R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),</div><div class='add'>+	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),</div><div class='ctx'> 	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),</div><div class='ctx'> 	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),</div><div class='ctx'> };</div><div class='hunk'>@@ -209,9 +218,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {</div><div class='ctx'> static const struct rzg2l_reset r9a08g045_resets[] = {</div><div class='ctx'> 	DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),</div><div class='ctx'> 	DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),</div><div class='add'>+	DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),</div><div class='ctx'> 	DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),</div><div class='ctx'> 	DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),</div><div class='ctx'> 	DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),</div><div class='add'>+	DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),</div><div class='add'>+	DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),</div><div class='ctx'> 	DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),</div><div class='ctx'> 	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),</div><div class='ctx'> 	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),</div><div class='hunk'>@@ -220,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {</div><div class='ctx'> </div><div class='ctx'> static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {</div><div class='ctx'> 	MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,</div><div class='add'>+	MOD_CLK_BASE + R9A08G045_IA55_PCLK,</div><div class='ctx'> 	MOD_CLK_BASE + R9A08G045_IA55_CLK,</div><div class='ctx'> 	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c<br/>index 764bd72cf059..3d2daa4ba2a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/renesas/rzg2l-cpg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/renesas/rzg2l-cpg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/renesas/rzg2l-cpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/renesas/rzg2l-cpg.c</a></div><div class='hunk'>@@ -1410,41 +1410,33 @@ fail:</div><div class='ctx'> </div><div class='ctx'> #define rcdev_to_priv(x)	container_of(x, struct rzg2l_cpg_priv, rcdev)</div><div class='ctx'> </div><div class='del'>-static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,</div><div class='del'>-			   unsigned long id)</div><div class='del'>-{</div><div class='del'>-	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);</div><div class='del'>-	const struct rzg2l_cpg_info *info = priv-&gt;info;</div><div class='del'>-	unsigned int reg = info-&gt;resets[id].off;</div><div class='del'>-	u32 dis = BIT(info-&gt;resets[id].bit);</div><div class='del'>-	u32 we = dis &lt;&lt; 16;</div><div class='del'>-</div><div class='del'>-	dev_dbg(rcdev-&gt;dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));</div><div class='del'>-</div><div class='del'>-	/* Reset module */</div><div class='del'>-	writel(we, priv-&gt;base + CLK_RST_R(reg));</div><div class='del'>-</div><div class='del'>-	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */</div><div class='del'>-	udelay(35);</div><div class='del'>-</div><div class='del'>-	/* Release module from reset state */</div><div class='del'>-	writel(we | dis, priv-&gt;base + CLK_RST_R(reg));</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,</div><div class='ctx'> 			    unsigned long id)</div><div class='ctx'> {</div><div class='ctx'> 	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);</div><div class='ctx'> 	const struct rzg2l_cpg_info *info = priv-&gt;info;</div><div class='ctx'> 	unsigned int reg = info-&gt;resets[id].off;</div><div class='del'>-	u32 value = BIT(info-&gt;resets[id].bit) &lt;&lt; 16;</div><div class='add'>+	u32 mask = BIT(info-&gt;resets[id].bit);</div><div class='add'>+	s8 monbit = info-&gt;resets[id].monbit;</div><div class='add'>+	u32 value = mask &lt;&lt; 16;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(rcdev-&gt;dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));</div><div class='ctx'> </div><div class='ctx'> 	writel(value, priv-&gt;base + CLK_RST_R(reg));</div><div class='del'>-	return 0;</div><div class='add'>+</div><div class='add'>+	if (info-&gt;has_clk_mon_regs) {</div><div class='add'>+		reg = CLK_MRST_R(reg);</div><div class='add'>+	} else if (monbit &gt;= 0) {</div><div class='add'>+		reg = CPG_RST_MON;</div><div class='add'>+		mask = BIT(monbit);</div><div class='add'>+	} else {</div><div class='add'>+		/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */</div><div class='add'>+		udelay(35);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return readl_poll_timeout_atomic(priv-&gt;base + reg, value,</div><div class='add'>+					 value &amp; mask, 10, 200);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,</div><div class='hunk'>@@ -1453,14 +1445,40 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,</div><div class='ctx'> 	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);</div><div class='ctx'> 	const struct rzg2l_cpg_info *info = priv-&gt;info;</div><div class='ctx'> 	unsigned int reg = info-&gt;resets[id].off;</div><div class='del'>-	u32 dis = BIT(info-&gt;resets[id].bit);</div><div class='del'>-	u32 value = (dis &lt;&lt; 16) | dis;</div><div class='add'>+	u32 mask = BIT(info-&gt;resets[id].bit);</div><div class='add'>+	s8 monbit = info-&gt;resets[id].monbit;</div><div class='add'>+	u32 value = (mask &lt;&lt; 16) | mask;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(rcdev-&gt;dev, "deassert id:%ld offset:0x%x\n", id,</div><div class='ctx'> 		CLK_RST_R(reg));</div><div class='ctx'> </div><div class='ctx'> 	writel(value, priv-&gt;base + CLK_RST_R(reg));</div><div class='del'>-	return 0;</div><div class='add'>+</div><div class='add'>+	if (info-&gt;has_clk_mon_regs) {</div><div class='add'>+		reg = CLK_MRST_R(reg);</div><div class='add'>+	} else if (monbit &gt;= 0) {</div><div class='add'>+		reg = CPG_RST_MON;</div><div class='add'>+		mask = BIT(monbit);</div><div class='add'>+	} else {</div><div class='add'>+		/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */</div><div class='add'>+		udelay(35);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return readl_poll_timeout_atomic(priv-&gt;base + reg, value,</div><div class='add'>+					 !(value &amp; mask), 10, 200);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,</div><div class='add'>+			   unsigned long id)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = rzg2l_cpg_assert(rcdev, id);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return rzg2l_cpg_deassert(rcdev, id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,</div><div class='hunk'>@@ -1468,18 +1486,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,</div><div class='ctx'> {</div><div class='ctx'> 	struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);</div><div class='ctx'> 	const struct rzg2l_cpg_info *info = priv-&gt;info;</div><div class='del'>-	unsigned int reg = info-&gt;resets[id].off;</div><div class='del'>-	u32 bitmask = BIT(info-&gt;resets[id].bit);</div><div class='ctx'> 	s8 monbit = info-&gt;resets[id].monbit;</div><div class='add'>+	unsigned int reg;</div><div class='add'>+	u32 bitmask;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;has_clk_mon_regs) {</div><div class='del'>-		return !!(readl(priv-&gt;base + CLK_MRST_R(reg)) &amp; bitmask);</div><div class='add'>+		reg = CLK_MRST_R(info-&gt;resets[id].off);</div><div class='add'>+		bitmask = BIT(info-&gt;resets[id].bit);</div><div class='ctx'> 	} else if (monbit &gt;= 0) {</div><div class='del'>-		u32 monbitmask = BIT(monbit);</div><div class='del'>-</div><div class='del'>-		return !!(readl(priv-&gt;base + CPG_RST_MON) &amp; monbitmask);</div><div class='add'>+		reg = CPG_RST_MON;</div><div class='add'>+		bitmask = BIT(monbit);</div><div class='add'>+	} else {</div><div class='add'>+		return -ENOTSUPP;</div><div class='ctx'> 	}</div><div class='del'>-	return -ENOTSUPP;</div><div class='add'>+</div><div class='add'>+	return !!(readl(priv-&gt;base + reg) &amp; bitmask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct reset_control_ops rzg2l_cpg_reset_ops = {</div><div class='head'>diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c<br/>index aa53797dbfc1..75071e0cd321 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/rockchip/clk-rk3128.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/rockchip/clk-rk3128.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/rockchip/clk-rk3128.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/rockchip/clk-rk3128.c</a></div><div class='hunk'>@@ -138,7 +138,7 @@ PNAME(mux_pll_src_5plls_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480</div><div class='ctx'> PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "gpll_div2", "usb480m" };</div><div class='ctx'> PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "gpll_div2" };</div><div class='ctx'> </div><div class='del'>-PNAME(mux_aclk_peri_src_p)	= { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };</div><div class='add'>+PNAME(mux_clk_peri_src_p)	= { "gpll", "cpll", "gpll_div2", "gpll_div3" };</div><div class='ctx'> PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "gpll_div2", "xin24m" };</div><div class='ctx'> PNAME(mux_clk_cif_out_src_p)		= { "clk_cif_src", "xin24m" };</div><div class='ctx'> PNAME(mux_sclk_vop_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };</div><div class='hunk'>@@ -275,23 +275,17 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {</div><div class='ctx'> 			RK2928_CLKGATE_CON(0), 11, GFLAGS),</div><div class='ctx'> </div><div class='ctx'> 	/* PD_PERI */</div><div class='del'>-	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,</div><div class='add'>+	COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0,</div><div class='add'>+			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 0, GFLAGS),</div><div class='del'>-	GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,</div><div class='del'>-			RK2928_CLKGATE_CON(2), 0, GFLAGS),</div><div class='del'>-	GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,</div><div class='del'>-			RK2928_CLKGATE_CON(2), 0, GFLAGS),</div><div class='del'>-	GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,</div><div class='del'>-			RK2928_CLKGATE_CON(2), 0, GFLAGS),</div><div class='del'>-	COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,</div><div class='del'>-			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),</div><div class='del'>-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,</div><div class='add'>+</div><div class='add'>+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", 0,</div><div class='ctx'> 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 3, GFLAGS),</div><div class='del'>-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,</div><div class='add'>+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", 0,</div><div class='ctx'> 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 2, GFLAGS),</div><div class='del'>-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,</div><div class='add'>+	GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 1, GFLAGS),</div><div class='ctx'> </div><div class='ctx'> 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,</div><div class='hunk'>@@ -316,7 +310,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {</div><div class='ctx'> 	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 15, GFLAGS),</div><div class='ctx'> </div><div class='del'>-	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,</div><div class='add'>+	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,</div><div class='ctx'> 			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,</div><div class='ctx'> 			RK2928_CLKGATE_CON(2), 11, GFLAGS),</div><div class='ctx'> </div><div class='hunk'>@@ -490,7 +484,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {</div><div class='ctx'> 	GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),</div><div class='ctx'> 	GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),</div><div class='ctx'> 	GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),</div><div class='del'>-	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),</div><div class='add'>+	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),</div><div class='ctx'> 	GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),</div><div class='ctx'> 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),</div><div class='ctx'> 	GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),</div><div class='head'>diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c<br/>index 16dabe2b9c47..b786ddc9af2a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/rockchip/clk-rk3568.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/rockchip/clk-rk3568.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/rockchip/clk-rk3568.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/rockchip/clk-rk3568.c</a></div><div class='hunk'>@@ -72,12 +72,15 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {</div><div class='ctx'> 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),</div><div class='add'>+	RK3036_PLL_RATE(292500000, 1, 195, 4, 4, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),</div><div class='add'>+	RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),</div><div class='add'>+	RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),</div><div class='ctx'> 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),</div><div class='hunk'>@@ -1592,6 +1595,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {</div><div class='ctx'> 	"hclk_php",</div><div class='ctx'> 	"pclk_php",</div><div class='ctx'> 	"hclk_usb",</div><div class='add'>+	"pclk_usb",</div><div class='ctx'> 	"hclk_vo",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile<br/>index ebbeacabe88f..3056944a5a54 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/samsung/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/samsung/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/Makefile</a></div><div class='hunk'>@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o</div><div class='ctx'> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o</div><div class='ctx'> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o</div><div class='ctx'> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o</div><div class='add'>+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o</div><div class='ctx'> obj-$(CONFIG_S3C64XX_COMMON_CLK)	+= clk-s3c64xx.o</div><div class='ctx'> obj-$(CONFIG_S5PV210_COMMON_CLK)	+= clk-s5pv210.o clk-s5pv210-audss.o</div><div class='ctx'> obj-$(CONFIG_TESLA_FSD_COMMON_CLK)	+= clk-fsd.o</div><div class='head'>diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h<br/>index fc9f67a3b22e..0164bd9ad021 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-cpu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/samsung/clk-cpu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-cpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-cpu.h</a></div><div class='hunk'>@@ -11,10 +11,10 @@</div><div class='ctx'> #include "clk.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct exynos_cpuclk_data: config data to setup cpu clocks.</div><div class='del'>- * @prate: frequency of the primary parent clock (in KHz).</div><div class='del'>- * @div0: value to be programmed in the div_cpu0 register.</div><div class='del'>- * @div1: value to be programmed in the div_cpu1 register.</div><div class='add'>+ * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks</div><div class='add'>+ * @prate: frequency of the primary parent clock (in KHz)</div><div class='add'>+ * @div0: value to be programmed in the div_cpu0 register</div><div class='add'>+ * @div1: value to be programmed in the div_cpu1 register</div><div class='ctx'>  *</div><div class='ctx'>  * This structure holds the divider configuration data for dividers in the CPU</div><div class='ctx'>  * clock domain. The parent frequency at which these divider values are valid is</div><div class='hunk'>@@ -29,17 +29,17 @@ struct exynos_cpuclk_cfg_data {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct exynos_cpuclk: information about clock supplied to a CPU core.</div><div class='del'>- * @hw:	handle between CCF and CPU clock.</div><div class='del'>- * @alt_parent: alternate parent clock to use when switching the speed</div><div class='del'>- *	of the primary parent clock.</div><div class='del'>- * @ctrl_base:	base address of the clock controller.</div><div class='del'>- * @lock: cpu clock domain register access lock.</div><div class='del'>- * @cfg: cpu clock rate configuration data.</div><div class='del'>- * @num_cfgs: number of array elements in @cfg array.</div><div class='del'>- * @clk_nb: clock notifier registered for changes in clock speed of the</div><div class='del'>- *	primary parent clock.</div><div class='del'>- * @flags: configuration flags for the CPU clock.</div><div class='add'>+ * struct exynos_cpuclk - information about clock supplied to a CPU core</div><div class='add'>+ * @hw:		handle between CCF and CPU clock</div><div class='add'>+ * @alt_parent:	alternate parent clock to use when switching the speed</div><div class='add'>+ *		of the primary parent clock</div><div class='add'>+ * @ctrl_base:	base address of the clock controller</div><div class='add'>+ * @lock:	cpu clock domain register access lock</div><div class='add'>+ * @cfg:	cpu clock rate configuration data</div><div class='add'>+ * @num_cfgs:	number of array elements in @cfg array</div><div class='add'>+ * @clk_nb:	clock notifier registered for changes in clock speed of the</div><div class='add'>+ *		primary parent clock</div><div class='add'>+ * @flags:	configuration flags for the CPU clock</div><div class='ctx'>  *</div><div class='ctx'>  * This structure holds information required for programming the CPU clock for</div><div class='ctx'>  * various clock speeds.</div><div class='head'>diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c<br/>new file mode 100644<br/>index 000000000000..0964bb11657f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-gs101.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-gs101.c</a></div><div class='hunk'>@@ -0,0 +1,2518 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Linaro Ltd.</div><div class='add'>+ * Author: Peter Griffin &lt;peter.griffin@linaro.org&gt;</div><div class='add'>+ *</div><div class='add'>+ * Common Clock Framework support for GS101.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/clk-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/clock/google,gs101.h&gt;</div><div class='add'>+</div><div class='add'>+#include "clk.h"</div><div class='add'>+#include "clk-exynos-arm64.h"</div><div class='add'>+</div><div class='add'>+/* NOTE: Must be equal to the last clock ID increased by one */</div><div class='add'>+#define CLKS_NR_TOP	(CLK_GOUT_CMU_TPU_UART + 1)</div><div class='add'>+#define CLKS_NR_APM	(CLK_APM_PLL_DIV16_APM + 1)</div><div class='add'>+#define CLKS_NR_MISC	(CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)</div><div class='add'>+</div><div class='add'>+/* ---- CMU_TOP ------------------------------------------------------------- */</div><div class='add'>+</div><div class='add'>+/* Register Offset definitions for CMU_TOP (0x1e080000) */</div><div class='add'>+</div><div class='add'>+#define PLL_LOCKTIME_PLL_SHARED0			0x0000</div><div class='add'>+#define PLL_LOCKTIME_PLL_SHARED1			0x0004</div><div class='add'>+#define PLL_LOCKTIME_PLL_SHARED2			0x0008</div><div class='add'>+#define PLL_LOCKTIME_PLL_SHARED3			0x000c</div><div class='add'>+#define PLL_LOCKTIME_PLL_SPARE				0x0010</div><div class='add'>+#define PLL_CON0_PLL_SHARED0				0x0100</div><div class='add'>+#define PLL_CON1_PLL_SHARED0				0x0104</div><div class='add'>+#define PLL_CON2_PLL_SHARED0				0x0108</div><div class='add'>+#define PLL_CON3_PLL_SHARED0				0x010c</div><div class='add'>+#define PLL_CON4_PLL_SHARED0				0x0110</div><div class='add'>+#define PLL_CON0_PLL_SHARED1				0x0140</div><div class='add'>+#define PLL_CON1_PLL_SHARED1				0x0144</div><div class='add'>+#define PLL_CON2_PLL_SHARED1				0x0148</div><div class='add'>+#define PLL_CON3_PLL_SHARED1				0x014c</div><div class='add'>+#define PLL_CON4_PLL_SHARED1				0x0150</div><div class='add'>+#define PLL_CON0_PLL_SHARED2				0x0180</div><div class='add'>+#define PLL_CON1_PLL_SHARED2				0x0184</div><div class='add'>+#define PLL_CON2_PLL_SHARED2				0x0188</div><div class='add'>+#define PLL_CON3_PLL_SHARED2				0x018c</div><div class='add'>+#define PLL_CON4_PLL_SHARED2				0x0190</div><div class='add'>+#define PLL_CON0_PLL_SHARED3				0x01c0</div><div class='add'>+#define PLL_CON1_PLL_SHARED3				0x01c4</div><div class='add'>+#define PLL_CON2_PLL_SHARED3				0x01c8</div><div class='add'>+#define PLL_CON3_PLL_SHARED3				0x01cc</div><div class='add'>+#define PLL_CON4_PLL_SHARED3				0x01d0</div><div class='add'>+#define PLL_CON0_PLL_SPARE				0x0200</div><div class='add'>+#define PLL_CON1_PLL_SPARE				0x0204</div><div class='add'>+#define PLL_CON2_PLL_SPARE				0x0208</div><div class='add'>+#define PLL_CON3_PLL_SPARE				0x020c</div><div class='add'>+#define PLL_CON4_PLL_SPARE				0x0210</div><div class='add'>+#define CMU_CMU_TOP_CONTROLLER_OPTION			0x0800</div><div class='add'>+#define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0		0x0810</div><div class='add'>+#define CMU_HCHGEN_CLKMUX_CMU_BOOST			0x0840</div><div class='add'>+#define CMU_HCHGEN_CLKMUX_TOP_BOOST			0x0844</div><div class='add'>+#define CMU_HCHGEN_CLKMUX				0x0850</div><div class='add'>+#define POWER_FAIL_DETECT_PLL				0x0864</div><div class='add'>+#define EARLY_WAKEUP_FORCED_0_ENABLE			0x0870</div><div class='add'>+#define EARLY_WAKEUP_FORCED_1_ENABLE			0x0874</div><div class='add'>+#define EARLY_WAKEUP_APM_CTRL				0x0878</div><div class='add'>+#define EARLY_WAKEUP_CLUSTER0_CTRL			0x087c</div><div class='add'>+#define EARLY_WAKEUP_DPU_CTRL				0x0880</div><div class='add'>+#define EARLY_WAKEUP_CSIS_CTRL				0x0884</div><div class='add'>+#define EARLY_WAKEUP_APM_DEST				0x0890</div><div class='add'>+#define EARLY_WAKEUP_CLUSTER0_DEST			0x0894</div><div class='add'>+#define EARLY_WAKEUP_DPU_DEST				0x0898</div><div class='add'>+#define EARLY_WAKEUP_CSIS_DEST				0x089c</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_APM			0x08c0</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_APM_SET			0x08c4</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_APM_CLEAR			0x08c8</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0			0x08d0</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET		0x08d4</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR		0x08d8</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_DPU			0x08e0</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_DPU_SET			0x08e4</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR			0x08e8</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CSIS			0x08f0</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CSIS_SET			0x08f4</div><div class='add'>+#define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR			0x08f8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_BO_BUS			0x1000</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS			0x1004</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS			0x1008</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS			0x100c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0			0x1010</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1			0x1014</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2			0x1018</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3			0x101c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4			0x1020</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5			0x1024</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6			0x1028</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7			0x102c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST		0x1030</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1	0x1034</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS			0x1038</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG		0x103c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH		0x1040</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH		0x1044</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH		0x1048</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS			0x104c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS			0x1050</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS			0x1054</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS			0x1058</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_EH_BUS			0x105c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D			0x1060</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL			0x1064</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA		0x1068</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD			0x106c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB			0x1070</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH		0x1074</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0			0x1078</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1			0x107c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC			0x1080</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HPM			0x1084</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS			0x1088</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC		0x108c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD		0x1090</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG		0x1094</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS			0x1098</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE		0x109c</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS			0x10a0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD		0x10a4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE		0x10a8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD		0x10ac</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS			0x10b0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS			0x10b4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC		0x10b8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC		0x10bc</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC			0x10c0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP			0x10c4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH		0x10c8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS			0x10cc</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS			0x10d0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS			0x10d4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA			0x10d8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS		0x10dc</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP		0x10e0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS		0x10e4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP		0x10e8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS			0x10ec</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1	0x10f0</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF		0x10f4</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS			0x10f8</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU			0x10fc</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL		0x1100</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_TPU_UART			0x1104</div><div class='add'>+#define CLK_CON_MUX_MUX_CMU_CMUREF			0x1108</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_BO_BUS			0x1800</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_BUS0_BUS			0x1804</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_BUS1_BUS			0x1808</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_BUS2_BUS			0x180c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK0			0x1810</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK1			0x1814</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK2			0x1818</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK3			0x181c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK4			0x1820</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK5			0x1824</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK6			0x1828</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CIS_CLK7			0x182c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CORE_BUS			0x1830</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG			0x1834</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH		0x1838</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH		0x183c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH		0x1840</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_CSIS_BUS			0x1844</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_DISP_BUS			0x1848</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_DNS_BUS			0x184c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_DPU_BUS			0x1850</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_EH_BUS			0x1854</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G2D_G2D			0x1858</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G2D_MSCL			0x185c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G3AA_G3AA			0x1860</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G3D_BUSD			0x1864</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G3D_GLB			0x1868</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH			0x186c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_GDC_GDC0			0x1870</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_GDC_GDC1			0x1874</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_GDC_SCSC			0x1878</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HPM				0x187c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI0_BUS			0x1880</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC			0x1884</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD		0x1888</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG		0x188c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI1_BUS			0x1890</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI1_PCIE			0x1894</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI2_BUS			0x1898</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD		0x189c</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI2_PCIE			0x18a0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD		0x18a4</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_IPP_BUS			0x18a8</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_ITP_BUS			0x18ac</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MCSC_ITSC			0x18b0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MCSC_MCSC			0x18b4</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MFC_MFC			0x18b8</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MIF_BUSP			0x18bc</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MISC_BUS			0x18c0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_MISC_SSS			0x18c4</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_OTP				0x18c8</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PDP_BUS			0x18cc</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PDP_VRA			0x18d0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PERIC0_BUS			0x18d4</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PERIC0_IP			0x18d8</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PERIC1_BUS			0x18dc</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_PERIC1_IP			0x18e0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_TNR_BUS			0x18e4</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_TPU_BUS			0x18e8</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_TPU_TPU			0x18ec</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_TPU_TPUCTL			0x18f0</div><div class='add'>+#define CLK_CON_DIV_CLKCMU_TPU_UART			0x18f4</div><div class='add'>+#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST		0x18f8</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF			0x18fc</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED0_DIV2			0x1900</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED0_DIV3			0x1904</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED0_DIV4			0x1908</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED0_DIV5			0x190c</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED1_DIV2			0x1910</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED1_DIV3			0x1914</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED1_DIV4			0x1918</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED2_DIV2			0x191c</div><div class='add'>+#define CLK_CON_DIV_PLL_SHARED3_DIV2			0x1920</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_BUS0_BOOST			0x2000</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_BUS1_BOOST			0x2004</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_BUS2_BOOST			0x2008</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_CORE_BOOST			0x200c</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST			0x2010</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST			0x2014</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST			0x2018</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_MIF_BOOST			0x201c</div><div class='add'>+#define CLK_CON_GAT_CLKCMU_MIF_SWITCH			0x2020</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_BO_BUS			0x2024</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS		0x2028</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS		0x202c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS		0x2030</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0		0x2034</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1		0x2038</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2		0x203c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3		0x2040</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4		0x2044</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5		0x2048</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6		0x204c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7		0x2050</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST		0x2054</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS		0x2058</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS		0x205c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH		0x2060</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH		0x2064</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH		0x2068</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS		0x206c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS		0x2070</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS			0x2074</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS			0x2078</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_EH_BUS			0x207c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D			0x2080</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL		0x2084</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA		0x2088</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD		0x208c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB			0x2090</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH		0x2094</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0		0x2098</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1		0x209c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC		0x20a0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HPM			0x20a4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS		0x20a8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC		0x20ac</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD		0x20b0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG		0x20b4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS		0x20b8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE		0x20bc</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS		0x20c0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD		0x20c4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE		0x20c8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD		0x20cc</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS			0x20d0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS			0x20d4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC		0x20d8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC		0x20dc</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC			0x20e0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP		0x20e4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS		0x20e8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS		0x20ec</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS			0x20f0</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA			0x20f4</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS		0x20f8</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP		0x20fc</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS		0x2100</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP		0x2104</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS			0x2108</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF		0x210c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS			0x2110</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU			0x2114</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL		0x2118</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_TPU_UART		0x211c</div><div class='add'>+#define DMYQCH_CON_CMU_TOP_CMUREF_QCH			0x3000</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0		0x3004</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1		0x3008</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2		0x300c</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3		0x3010</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4		0x3014</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5		0x3018</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6		0x301c</div><div class='add'>+#define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7		0x3020</div><div class='add'>+#define DMYQCH_CON_OTP_QCH				0x3024</div><div class='add'>+#define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP			0x3c00</div><div class='add'>+#define QUEUE_ENTRY0_BLK_CMU_CMU_TOP			0x3c10</div><div class='add'>+#define QUEUE_ENTRY1_BLK_CMU_CMU_TOP			0x3c14</div><div class='add'>+#define QUEUE_ENTRY2_BLK_CMU_CMU_TOP			0x3c18</div><div class='add'>+#define QUEUE_ENTRY3_BLK_CMU_CMU_TOP			0x3c1c</div><div class='add'>+#define QUEUE_ENTRY4_BLK_CMU_CMU_TOP			0x3c20</div><div class='add'>+#define QUEUE_ENTRY5_BLK_CMU_CMU_TOP			0x3c24</div><div class='add'>+#define QUEUE_ENTRY6_BLK_CMU_CMU_TOP			0x3c28</div><div class='add'>+#define QUEUE_ENTRY7_BLK_CMU_CMU_TOP			0x3c2c</div><div class='add'>+#define MIFMIRROR_QUEUE_CTRL_REG			0x3e00</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY0				0x3e10</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY1				0x3e14</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY2				0x3e18</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY3				0x3e1c</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY4				0x3e20</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY5				0x3e24</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY6				0x3e28</div><div class='add'>+#define MIFMIRROR_QUEUE_ENTRY7				0x3e2c</div><div class='add'>+#define MIFMIRROR_QUEUE_BUSY				0x3e30</div><div class='add'>+#define GENERALIO_ACD_CHANNEL_0				0x3f00</div><div class='add'>+#define GENERALIO_ACD_CHANNEL_1				0x3f04</div><div class='add'>+#define GENERALIO_ACD_CHANNEL_2				0x3f08</div><div class='add'>+#define GENERALIO_ACD_CHANNEL_3				0x3f0c</div><div class='add'>+#define GENERALIO_ACD_MASK				0x3f14</div><div class='add'>+</div><div class='add'>+static const unsigned long cmu_top_clk_regs[] __initconst = {</div><div class='add'>+	PLL_LOCKTIME_PLL_SHARED0,</div><div class='add'>+	PLL_LOCKTIME_PLL_SHARED1,</div><div class='add'>+	PLL_LOCKTIME_PLL_SHARED2,</div><div class='add'>+	PLL_LOCKTIME_PLL_SHARED3,</div><div class='add'>+	PLL_LOCKTIME_PLL_SPARE,</div><div class='add'>+	PLL_CON0_PLL_SHARED0,</div><div class='add'>+	PLL_CON1_PLL_SHARED0,</div><div class='add'>+	PLL_CON2_PLL_SHARED0,</div><div class='add'>+	PLL_CON3_PLL_SHARED0,</div><div class='add'>+	PLL_CON4_PLL_SHARED0,</div><div class='add'>+	PLL_CON0_PLL_SHARED1,</div><div class='add'>+	PLL_CON1_PLL_SHARED1,</div><div class='add'>+	PLL_CON2_PLL_SHARED1,</div><div class='add'>+	PLL_CON3_PLL_SHARED1,</div><div class='add'>+	PLL_CON4_PLL_SHARED1,</div><div class='add'>+	PLL_CON0_PLL_SHARED2,</div><div class='add'>+	PLL_CON1_PLL_SHARED2,</div><div class='add'>+	PLL_CON2_PLL_SHARED2,</div><div class='add'>+	PLL_CON3_PLL_SHARED2,</div><div class='add'>+	PLL_CON4_PLL_SHARED2,</div><div class='add'>+	PLL_CON0_PLL_SHARED3,</div><div class='add'>+	PLL_CON1_PLL_SHARED3,</div><div class='add'>+	PLL_CON2_PLL_SHARED3,</div><div class='add'>+	PLL_CON3_PLL_SHARED3,</div><div class='add'>+	PLL_CON4_PLL_SHARED3,</div><div class='add'>+	PLL_CON0_PLL_SPARE,</div><div class='add'>+	PLL_CON1_PLL_SPARE,</div><div class='add'>+	PLL_CON2_PLL_SPARE,</div><div class='add'>+	PLL_CON3_PLL_SPARE,</div><div class='add'>+	PLL_CON4_PLL_SPARE,</div><div class='add'>+	CMU_CMU_TOP_CONTROLLER_OPTION,</div><div class='add'>+	CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,</div><div class='add'>+	CMU_HCHGEN_CLKMUX_CMU_BOOST,</div><div class='add'>+	CMU_HCHGEN_CLKMUX_TOP_BOOST,</div><div class='add'>+	CMU_HCHGEN_CLKMUX,</div><div class='add'>+	POWER_FAIL_DETECT_PLL,</div><div class='add'>+	EARLY_WAKEUP_FORCED_0_ENABLE,</div><div class='add'>+	EARLY_WAKEUP_FORCED_1_ENABLE,</div><div class='add'>+	EARLY_WAKEUP_APM_CTRL,</div><div class='add'>+	EARLY_WAKEUP_CLUSTER0_CTRL,</div><div class='add'>+	EARLY_WAKEUP_DPU_CTRL,</div><div class='add'>+	EARLY_WAKEUP_CSIS_CTRL,</div><div class='add'>+	EARLY_WAKEUP_APM_DEST,</div><div class='add'>+	EARLY_WAKEUP_CLUSTER0_DEST,</div><div class='add'>+	EARLY_WAKEUP_DPU_DEST,</div><div class='add'>+	EARLY_WAKEUP_CSIS_DEST,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_APM,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_APM_SET,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_APM_CLEAR,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CLUSTER0,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_DPU,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_DPU_SET,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CSIS,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CSIS_SET,</div><div class='add'>+	EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_BO_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_EH_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HPM,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_TPU_UART,</div><div class='add'>+	CLK_CON_MUX_MUX_CMU_CMUREF,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_BO_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_BUS0_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_BUS1_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_BUS2_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK0,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK1,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK2,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK3,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK4,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK5,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK6,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CIS_CLK7,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CORE_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CPUCL0_DBG,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_CSIS_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_DISP_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_DNS_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_DPU_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_EH_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G2D_G2D,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G2D_MSCL,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G3AA_G3AA,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G3D_BUSD,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G3D_GLB,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_G3D_SWITCH,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_GDC_GDC0,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_GDC_GDC1,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_GDC_SCSC,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HPM,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI0_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI0_DPGTC,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI1_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI1_PCIE,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI2_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI2_PCIE,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_IPP_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_ITP_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MCSC_ITSC,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MCSC_MCSC,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MFC_MFC,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MIF_BUSP,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MISC_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_MISC_SSS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_OTP,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PDP_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PDP_VRA,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PERIC0_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PERIC0_IP,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PERIC1_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_PERIC1_IP,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_TNR_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_TPU_BUS,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_TPU_TPU,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_TPU_TPUCTL,</div><div class='add'>+	CLK_CON_DIV_CLKCMU_TPU_UART,</div><div class='add'>+	CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_CMU_CMUREF,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED0_DIV2,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED0_DIV3,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED0_DIV4,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED0_DIV5,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED1_DIV2,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED1_DIV3,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED1_DIV4,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED2_DIV2,</div><div class='add'>+	CLK_CON_DIV_PLL_SHARED3_DIV2,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_BUS0_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_BUS1_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_BUS2_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_CORE_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_MIF_BOOST,</div><div class='add'>+	CLK_CON_GAT_CLKCMU_MIF_SWITCH,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_BO_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_EH_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HPM,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_TPU_UART,</div><div class='add'>+	DMYQCH_CON_CMU_TOP_CMUREF_QCH,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,</div><div class='add'>+	DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,</div><div class='add'>+	DMYQCH_CON_OTP_QCH,</div><div class='add'>+	QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY0_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY1_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY2_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY3_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY4_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY5_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY6_BLK_CMU_CMU_TOP,</div><div class='add'>+	QUEUE_ENTRY7_BLK_CMU_CMU_TOP,</div><div class='add'>+	MIFMIRROR_QUEUE_CTRL_REG,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY0,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY1,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY2,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY3,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY4,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY5,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY6,</div><div class='add'>+	MIFMIRROR_QUEUE_ENTRY7,</div><div class='add'>+	MIFMIRROR_QUEUE_BUSY,</div><div class='add'>+	GENERALIO_ACD_CHANNEL_0,</div><div class='add'>+	GENERALIO_ACD_CHANNEL_1,</div><div class='add'>+	GENERALIO_ACD_CHANNEL_2,</div><div class='add'>+	GENERALIO_ACD_CHANNEL_3,</div><div class='add'>+	GENERALIO_ACD_MASK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {</div><div class='add'>+	/* CMU_TOP_PURECLKCOMP */</div><div class='add'>+	PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",</div><div class='add'>+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,</div><div class='add'>+	    NULL),</div><div class='add'>+	PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",</div><div class='add'>+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,</div><div class='add'>+	    NULL),</div><div class='add'>+	PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",</div><div class='add'>+	    PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,</div><div class='add'>+	    NULL),</div><div class='add'>+	PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",</div><div class='add'>+	    PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,</div><div class='add'>+	    NULL),</div><div class='add'>+	PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",</div><div class='add'>+	    PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,</div><div class='add'>+	    NULL),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* List of parent clocks for Muxes in CMU_TOP */</div><div class='add'>+PNAME(mout_pll_shared0_p)	= { "oscclk", "fout_shared0_pll" };</div><div class='add'>+PNAME(mout_pll_shared1_p)	= { "oscclk", "fout_shared1_pll" };</div><div class='add'>+PNAME(mout_pll_shared2_p)	= { "oscclk", "fout_shared2_pll" };</div><div class='add'>+PNAME(mout_pll_shared3_p)	= { "oscclk", "fout_shared3_pll" };</div><div class='add'>+PNAME(mout_pll_spare_p)		= { "oscclk", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_bo_bus_p)	= { "fout_shared2_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_bus0_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_bus1_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_bus2_bus_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div5", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_cis_clk0_7_p)	= { "oscclk", "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_cmu_boost_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2" };</div><div class='add'>+PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost",</div><div class='add'>+					"gout_cmu_boost_option1" };</div><div class='add'>+PNAME(mout_cmu_core_bus_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div5", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_cpucl0_dbg_p)	= { "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2", "fout_spare_pll",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_cpucl0_switch_p)	= { "fout_shared1_pll", "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2", "fout_shared2_pll",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_cpucl1_switch_p)	= { "fout_shared1_pll", "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2", "fout_shared2_pll",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_cpucl2_switch_p)	= { "fout_shared1_pll", "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2", "fout_shared2_pll",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_csis_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_disp_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_dns_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_dpu_p)		= { "dout_cmu_shared0_div3",</div><div class='add'>+				    "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_eh_bus_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div5", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_g2d_g2d_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_g2d_mscl_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_g3aa_g3aa_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_g3d_busd_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_g3d_glb_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_g3d_switch_p)	= { "fout_shared2_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "fout_spare_pll", "fout_spare_pll"};</div><div class='add'>+PNAME(mout_cmu_gdc_gdc0_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_gdc_gdc1_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_gdc_scsc_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_hpm_p)		= { "oscclk", "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2" };</div><div class='add'>+PNAME(mout_cmu_hsi0_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_hsi0_dpgtc_p)	= { "oscclk", "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_hsi0_usb31drd_p)	= { "oscclk", "dout_cmu_shared2_div2" };</div><div class='add'>+PNAME(mout_cmu_hsi0_usbdpdbg_p)	= { "oscclk", "dout_cmu_shared2_div2" };</div><div class='add'>+PNAME(mout_cmu_hsi1_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2",</div><div class='add'>+				    "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_hsi1_pcie_p)	= { "oscclk", "dout_cmu_shared2_div2" };</div><div class='add'>+PNAME(mout_cmu_hsi2_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_hsi2_mmc_card_p)	= { "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div4", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_hsi2_pcie0_p)	= { "oscclk", "dout_cmu_shared2_div2" };</div><div class='add'>+PNAME(mout_cmu_hsi2_ufs_embd_p)	= { "oscclk", "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_ipp_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_itp_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_mcsc_itsc_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_mcsc_mcsc_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_mfc_mfc_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2", "fout_spare_pll",</div><div class='add'>+				    "oscclk", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_mif_busp_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared0_div5", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_mif_switch_p)	= { "fout_shared0_pll", "fout_shared1_pll",</div><div class='add'>+				    "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "fout_shared3_pll", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_misc_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_misc_sss_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_pdp_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_pdp_vra_p)	= { "fout_shared2_pll", "dout_cmu_shared0_div3",</div><div class='add'>+				    "fout_shared3_pll", "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_peric0_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_peric0_ip_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_peric1_bus_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_peric1_ip_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_tnr_bus_p)	= { "dout_cmu_shared0_div3", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "fout_spare_pll", "oscclk" };</div><div class='add'>+PNAME(mout_cmu_top_boost_option1_p) = { "oscclk",</div><div class='add'>+					"gout_cmu_boost_option1" };</div><div class='add'>+PNAME(mout_cmu_top_cmuref_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared1_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2" };</div><div class='add'>+PNAME(mout_cmu_tpu_bus_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll",</div><div class='add'>+				    "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4",</div><div class='add'>+				    "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_tpu_tpu_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll",</div><div class='add'>+				    "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_tpu_tpuctl_p)	= { "dout_cmu_shared0_div2",</div><div class='add'>+				    "dout_cmu_shared1_div2",</div><div class='add'>+				    "fout_shared2_pll", "fout_shared3_pll",</div><div class='add'>+				    "dout_cmu_shared0_div3",</div><div class='add'>+				    "dout_cmu_shared1_div3",</div><div class='add'>+				    "dout_cmu_shared0_div4", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_tpu_uart_p)	= { "dout_cmu_shared0_div4",</div><div class='add'>+				    "dout_cmu_shared2_div2",</div><div class='add'>+				    "dout_cmu_shared3_div2", "fout_spare_pll" };</div><div class='add'>+PNAME(mout_cmu_cmuref_p)	= { "mout_cmu_top_boost_option1",</div><div class='add'>+				    "dout_cmu_cmuref" };</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Register name to clock name mangling strategy used in this file</div><div class='add'>+ *</div><div class='add'>+ * Replace PLL_CON0_PLL	           with CLK_MOUT_PLL and mout_pll</div><div class='add'>+ * Replace CLK_CON_MUX_MUX_CLKCMU  with CLK_MOUT_CMU and mout_cmu</div><div class='add'>+ * Replace CLK_CON_DIV_CLKCMU      with CLK_DOUT_CMU and dout_cmu</div><div class='add'>+ * Replace CLK_CON_DIV_DIV_CLKCMU  with CLK_DOUT_CMU and dout_cmu</div><div class='add'>+ * Replace CLK_CON_GAT_CLKCMU      with CLK_GOUT_CMU and gout_cmu</div><div class='add'>+ * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu</div><div class='add'>+ *</div><div class='add'>+ * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {</div><div class='add'>+	MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,</div><div class='add'>+	    PLL_CON0_PLL_SHARED0, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,</div><div class='add'>+	    PLL_CON0_PLL_SHARED1, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,</div><div class='add'>+	    PLL_CON0_PLL_SHARED2, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,</div><div class='add'>+	    PLL_CON0_PLL_SHARED3, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p,</div><div class='add'>+	    PLL_CON0_PLL_SPARE, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1",</div><div class='add'>+	    mout_cmu_cmu_boost_option1_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg",</div><div class='add'>+	    mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",</div><div class='add'>+	    mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,</div><div class='add'>+	    0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",</div><div class='add'>+	    mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,</div><div class='add'>+	    0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",</div><div class='add'>+	    mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,</div><div class='add'>+	    0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",</div><div class='add'>+	    mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",</div><div class='add'>+	    mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",</div><div class='add'>+	    mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,</div><div class='add'>+	    0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg",</div><div class='add'>+	    mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,</div><div class='add'>+	    0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card",</div><div class='add'>+	    mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,</div><div class='add'>+	    0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd",</div><div class='add'>+	    mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,</div><div class='add'>+	    0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",</div><div class='add'>+	    mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",</div><div class='add'>+	    mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",</div><div class='add'>+	    mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1",</div><div class='add'>+	    mout_cmu_top_boost_option1_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref",</div><div class='add'>+	    mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl",</div><div class='add'>+	    mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),</div><div class='add'>+	MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),</div><div class='add'>+	MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {</div><div class='add'>+	DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg",</div><div class='add'>+	    "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",</div><div class='add'>+	    "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",</div><div class='add'>+	    "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",</div><div class='add'>+	    "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",</div><div class='add'>+	    "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HPM, 0, 2),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc",</div><div class='add'>+	    "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",</div><div class='add'>+	    "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card",</div><div class='add'>+	    "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd",</div><div class='add'>+	    "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus",</div><div class='add'>+	    "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus",</div><div class='add'>+	    "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl",</div><div class='add'>+	    "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",</div><div class='add'>+	    CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),</div><div class='add'>+	DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2",</div><div class='add'>+	    "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3",</div><div class='add'>+	    "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4",</div><div class='add'>+	    "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5",</div><div class='add'>+	    "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2",</div><div class='add'>+	    "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3",</div><div class='add'>+	    "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4",</div><div class='add'>+	    "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2",</div><div class='add'>+	    "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2",</div><div class='add'>+	    "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {</div><div class='add'>+	FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",</div><div class='add'>+		"gout_cmu_hsi0_usbdpdbg", 1, 4, 0),</div><div class='add'>+	FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",</div><div class='add'>+	     "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",</div><div class='add'>+	     "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",</div><div class='add'>+	     "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",</div><div class='add'>+	     "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",</div><div class='add'>+	     "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",</div><div class='add'>+	     "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",</div><div class='add'>+	     CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",</div><div class='add'>+	     "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",</div><div class='add'>+	     "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",</div><div class='add'>+	     "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",</div><div class='add'>+	     "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",</div><div class='add'>+	     "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",</div><div class='add'>+	     "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",</div><div class='add'>+	     "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",</div><div class='add'>+	     "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",</div><div class='add'>+	     "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",</div><div class='add'>+	     "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_cmu_info top_cmu_info __initconst = {</div><div class='add'>+	.pll_clks		= cmu_top_pll_clks,</div><div class='add'>+	.nr_pll_clks		= ARRAY_SIZE(cmu_top_pll_clks),</div><div class='add'>+	.mux_clks		= cmu_top_mux_clks,</div><div class='add'>+	.nr_mux_clks		= ARRAY_SIZE(cmu_top_mux_clks),</div><div class='add'>+	.div_clks		= cmu_top_div_clks,</div><div class='add'>+	.nr_div_clks		= ARRAY_SIZE(cmu_top_div_clks),</div><div class='add'>+	.fixed_factor_clks	= cmu_top_ffactor,</div><div class='add'>+	.nr_fixed_factor_clks	= ARRAY_SIZE(cmu_top_ffactor),</div><div class='add'>+	.gate_clks		= cmu_top_gate_clks,</div><div class='add'>+	.nr_gate_clks		= ARRAY_SIZE(cmu_top_gate_clks),</div><div class='add'>+	.nr_clk_ids		= CLKS_NR_TOP,</div><div class='add'>+	.clk_regs		= cmu_top_clk_regs,</div><div class='add'>+	.nr_clk_regs		= ARRAY_SIZE(cmu_top_clk_regs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void __init gs101_cmu_top_init(struct device_node *np)</div><div class='add'>+{</div><div class='add'>+	exynos_arm64_register_cmu(NULL, np, &amp;top_cmu_info);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Register CMU_TOP early, as it's a dependency for other early domains */</div><div class='add'>+CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",</div><div class='add'>+	       gs101_cmu_top_init);</div><div class='add'>+</div><div class='add'>+/* ---- CMU_APM ------------------------------------------------------------- */</div><div class='add'>+</div><div class='add'>+/* Register Offset definitions for CMU_APM (0x17400000) */</div><div class='add'>+#define APM_CMU_APM_CONTROLLER_OPTION							0x0800</div><div class='add'>+#define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0						0x0810</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC							0x1000</div><div class='add'>+#define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC						0x1004</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_APM_BOOST							0x1800</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_APM_USI0_UART						0x1804</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_APM_USI0_USI						0x1808</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_APM_USI1_UART						0x180c</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK				0x2000</div><div class='add'>+#define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1						0x2004</div><div class='add'>+#define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1						0x2008</div><div class='add'>+#define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1						0x200c</div><div class='add'>+#define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC						0x2010</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK			0x2014</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK		0x2018</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK			0x201c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK				0x2020</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK				0x2024</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK			0x2028</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK			0x202c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK			0x2030</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK			0x2034</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK			0x2038</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK			0x203c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK				0x2040</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK				0x2044</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK			0x2048</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK				0x204c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK				0x2050</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK			0x2054</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK			0x2058</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK			0x205c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK			0x2060</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK			0x2064</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK		0x2068</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK			0x206c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK			0x2070</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK			0x2074</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK			0x207c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK			0x2080</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK			0x2084</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK			0x2088</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK			0x208c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK			0x2090</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK			0x2094</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK			0x2098</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK		0x209c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK		0x20a0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK		0x20a4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK				0x20a8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK			0x20ac</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK				0x20b0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK				0x20b4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK			0x20b8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK			0x20bc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK	0x20c0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2			0x20c4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK				0x20cc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK				0x20d0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK				0x20d4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK			0x20d8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK			0x20dc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK				0x20e0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK				0x20e4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK			0x20e8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK			0x20ec</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK				0x20f0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK				0x20f4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK				0x20f8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK				0x20fc</div><div class='add'>+#define PCH_CON_LHM_AXI_G_SWD_PCH							0x3000</div><div class='add'>+#define PCH_CON_LHM_AXI_P_AOCAPM_PCH							0x3004</div><div class='add'>+#define PCH_CON_LHM_AXI_P_APM_PCH							0x3008</div><div class='add'>+#define PCH_CON_LHS_AXI_D_APM_PCH							0x300c</div><div class='add'>+#define PCH_CON_LHS_AXI_G_DBGCORE_PCH							0x3010</div><div class='add'>+#define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH							0x3014</div><div class='add'>+#define QCH_CON_APBIF_GPIO_ALIVE_QCH							0x3018</div><div class='add'>+#define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH						0x301c</div><div class='add'>+#define QCH_CON_APBIF_PMU_ALIVE_QCH							0x3020</div><div class='add'>+#define QCH_CON_APBIF_RTC_QCH								0x3024</div><div class='add'>+#define QCH_CON_APBIF_TRTC_QCH								0x3028</div><div class='add'>+#define QCH_CON_APM_CMU_APM_QCH								0x302c</div><div class='add'>+#define QCH_CON_APM_USI0_UART_QCH							0x3030</div><div class='add'>+#define QCH_CON_APM_USI0_USI_QCH							0x3034</div><div class='add'>+#define QCH_CON_APM_USI1_UART_QCH							0x3038</div><div class='add'>+#define QCH_CON_D_TZPC_APM_QCH								0x303c</div><div class='add'>+#define QCH_CON_GPC_APM_QCH								0x3040</div><div class='add'>+#define QCH_CON_GREBEINTEGRATION_QCH_DBG						0x3044</div><div class='add'>+#define QCH_CON_GREBEINTEGRATION_QCH_GREBE						0x3048</div><div class='add'>+#define QCH_CON_INTMEM_QCH								0x304c</div><div class='add'>+#define QCH_CON_LHM_AXI_G_SWD_QCH							0x3050</div><div class='add'>+#define QCH_CON_LHM_AXI_P_AOCAPM_QCH							0x3054</div><div class='add'>+#define QCH_CON_LHM_AXI_P_APM_QCH							0x3058</div><div class='add'>+#define QCH_CON_LHS_AXI_D_APM_QCH							0x305c</div><div class='add'>+#define QCH_CON_LHS_AXI_G_DBGCORE_QCH							0x3060</div><div class='add'>+#define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH							0x3064</div><div class='add'>+#define QCH_CON_MAILBOX_APM_AOC_QCH							0x3068</div><div class='add'>+#define QCH_CON_MAILBOX_APM_AP_QCH							0x306c</div><div class='add'>+#define QCH_CON_MAILBOX_APM_GSA_QCH							0x3070</div><div class='add'>+#define QCH_CON_MAILBOX_APM_SWD_QCH							0x3078</div><div class='add'>+#define QCH_CON_MAILBOX_APM_TPU_QCH							0x307c</div><div class='add'>+#define QCH_CON_MAILBOX_AP_AOC_QCH							0x3080</div><div class='add'>+#define QCH_CON_MAILBOX_AP_DBGCORE_QCH							0x3084</div><div class='add'>+#define QCH_CON_PMU_INTR_GEN_QCH							0x3088</div><div class='add'>+#define QCH_CON_ROM_CRC32_HOST_QCH							0x308c</div><div class='add'>+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE						0x3090</div><div class='add'>+#define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG					0x3094</div><div class='add'>+#define QCH_CON_SPEEDY_APM_QCH								0x3098</div><div class='add'>+#define QCH_CON_SPEEDY_SUB_APM_QCH							0x309c</div><div class='add'>+#define QCH_CON_SSMT_D_APM_QCH								0x30a0</div><div class='add'>+#define QCH_CON_SSMT_G_DBGCORE_QCH							0x30a4</div><div class='add'>+#define QCH_CON_SS_DBGCORE_QCH_DBG							0x30a8</div><div class='add'>+#define QCH_CON_SS_DBGCORE_QCH_GREBE							0x30ac</div><div class='add'>+#define QCH_CON_SYSMMU_D_APM_QCH							0x30b0</div><div class='add'>+#define QCH_CON_SYSREG_APM_QCH								0x30b8</div><div class='add'>+#define QCH_CON_UASC_APM_QCH								0x30bc</div><div class='add'>+#define QCH_CON_UASC_DBGCORE_QCH							0x30c0</div><div class='add'>+#define QCH_CON_UASC_G_SWD_QCH								0x30c4</div><div class='add'>+#define QCH_CON_UASC_P_AOCAPM_QCH							0x30c8</div><div class='add'>+#define QCH_CON_UASC_P_APM_QCH								0x30cc</div><div class='add'>+#define QCH_CON_WDT_APM_QCH								0x30d0</div><div class='add'>+#define QUEUE_CTRL_REG_BLK_APM_CMU_APM							0x3c00</div><div class='add'>+</div><div class='add'>+static const unsigned long apm_clk_regs[] __initconst = {</div><div class='add'>+	APM_CMU_APM_CONTROLLER_OPTION,</div><div class='add'>+	CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,</div><div class='add'>+	CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_APM_BOOST,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_APM_USI0_UART,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_APM_USI0_USI,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_APM_USI1_UART,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,</div><div class='add'>+	CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,</div><div class='add'>+	CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,</div><div class='add'>+	CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+PNAME(mout_apm_func_p)		= { "oscclk", "mout_apm_funcsrc",</div><div class='add'>+				    "pad_clk_apm", "oscclk" };</div><div class='add'>+PNAME(mout_apm_funcsrc_p)	= { "pll_alv_div2_apm", "pll_alv_div4_apm",</div><div class='add'>+				    "pll_alv_div16_apm" };</div><div class='add'>+</div><div class='add'>+static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {</div><div class='add'>+	FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),</div><div class='add'>+	FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),</div><div class='add'>+	FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {</div><div class='add'>+	MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_div_clock apm_div_clks[] __initconst = {</div><div class='add'>+	DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),</div><div class='add'>+	DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),</div><div class='add'>+	DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),</div><div class='add'>+	DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,</div><div class='add'>+	     "gout_apm_apm_cmu_apm_pclk", "mout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",</div><div class='add'>+	     "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",</div><div class='add'>+	     "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",</div><div class='add'>+	     "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,</div><div class='add'>+	     "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,</div><div class='add'>+	     "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,</div><div class='add'>+	     "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,</div><div class='add'>+	     "gout_apm_apbif_rtc_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,</div><div class='add'>+	     "gout_apm_apbif_trtc_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,</div><div class='add'>+	     "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,</div><div class='add'>+	     "gout_apm_apm_usi0_uart_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,</div><div class='add'>+	     "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,</div><div class='add'>+	     "gout_apm_apm_usi0_usi_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,</div><div class='add'>+	     "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,</div><div class='add'>+	     "gout_apm_apm_usi1_uart_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,</div><div class='add'>+	     "gout_apm_d_tzpc_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_GPC_APM_PCLK,</div><div class='add'>+	     "gout_apm_gpc_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,</div><div class='add'>+	     "gout_apm_grebeintegration_hclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_INTMEM_ACLK,</div><div class='add'>+	     "gout_apm_intmem_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_INTMEM_PCLK,</div><div class='add'>+	     "gout_apm_intmem_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,</div><div class='add'>+	     "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,</div><div class='add'>+	     "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,</div><div class='add'>+	     "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,</div><div class='add'>+	     "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,</div><div class='add'>+	     "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,</div><div class='add'>+	     "gout_apm_lhs_axi_g_scan2dram_i_clk",</div><div class='add'>+	     "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,</div><div class='add'>+	     "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,</div><div class='add'>+	     "gout_apm_pmu_intr_gen_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,</div><div class='add'>+	     "gout_apm_rom_crc32_host_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,</div><div class='add'>+	     "gout_apm_rom_crc32_host_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,</div><div class='add'>+	     "gout_apm_clk_apm_bus_clk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,</div><div class='add'>+	     "gout_apm_clk_apm_usi0_uart_clk",</div><div class='add'>+	     "dout_apm_usi0_uart",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,</div><div class='add'>+	     "gout_apm_clk_apm_usi0_usi_clk",</div><div class='add'>+	     "dout_apm_usi0_usi",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,</div><div class='add'>+	     "gout_apm_clk_apm_usi1_uart_clk",</div><div class='add'>+	     "dout_apm_usi1_uart",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,</div><div class='add'>+	     "gout_apm_speedy_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,</div><div class='add'>+	     "gout_apm_speedy_sub_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,</div><div class='add'>+	     "gout_apm_ssmt_d_apm_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,</div><div class='add'>+	     "gout_apm_ssmt_d_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,</div><div class='add'>+	     "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,</div><div class='add'>+	     "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,</div><div class='add'>+	     "gout_apm_ss_dbgcore_ss_dbgcore_hclk",</div><div class='add'>+	     "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,</div><div class='add'>+	     "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,</div><div class='add'>+	     "gout_apm_sysreg_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_APM_ACLK,</div><div class='add'>+	     "gout_apm_uasc_apm_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_APM_PCLK,</div><div class='add'>+	     "gout_apm_uasc_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,</div><div class='add'>+	     "gout_apm_uasc_dbgcore_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,</div><div class='add'>+	     "gout_apm_uasc_dbgcore_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,</div><div class='add'>+	     "gout_apm_uasc_g_swd_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,</div><div class='add'>+	     "gout_apm_uasc_g_swd_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,</div><div class='add'>+	     "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,</div><div class='add'>+	     "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,</div><div class='add'>+	     "gout_apm_uasc_p_apm_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,</div><div class='add'>+	     "gout_apm_uasc_p_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_WDT_APM_PCLK,</div><div class='add'>+	     "gout_apm_wdt_apm_pclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,</div><div class='add'>+	     "gout_apm_xiu_dp_apm_aclk", "gout_apm_func",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_cmu_info apm_cmu_info __initconst = {</div><div class='add'>+	.mux_clks		= apm_mux_clks,</div><div class='add'>+	.nr_mux_clks		= ARRAY_SIZE(apm_mux_clks),</div><div class='add'>+	.div_clks		= apm_div_clks,</div><div class='add'>+	.nr_div_clks		= ARRAY_SIZE(apm_div_clks),</div><div class='add'>+	.gate_clks		= apm_gate_clks,</div><div class='add'>+	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),</div><div class='add'>+	.fixed_clks		= apm_fixed_clks,</div><div class='add'>+	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),</div><div class='add'>+	.nr_clk_ids		= CLKS_NR_APM,</div><div class='add'>+	.clk_regs		= apm_clk_regs,</div><div class='add'>+	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ---- CMU_MISC ------------------------------------------------------------ */</div><div class='add'>+</div><div class='add'>+/* Register Offset definitions for CMU_MISC (0x10010000) */</div><div class='add'>+#define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER					0x0600</div><div class='add'>+#define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER					0x0604</div><div class='add'>+#define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER					0x0610</div><div class='add'>+#define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER					0x0614</div><div class='add'>+#define MISC_CMU_MISC_CONTROLLER_OPTION						0x0800</div><div class='add'>+#define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0					0x0810</div><div class='add'>+#define CLK_CON_MUX_MUX_CLK_MISC_GIC						0x1000</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_MISC_BUSP						0x1800</div><div class='add'>+#define CLK_CON_DIV_DIV_CLK_MISC_GIC						0x1804</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK		0x2000</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK		0x2004</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK		0x2008</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK		0x200c</div><div class='add'>+#define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK	0x2010</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM		0x2014</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM		0x2018</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM		0x201c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A			0x2020</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK		0x2024</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK			0x2028</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK			0x202c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK	0x2030</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK		0x2034</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK		0x2038</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK		0x203c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK		0x2040</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK	0x2044</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK		0x2048</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK			0x204c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK		0x2050</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK		0x2054</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK		0x2058</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK			0x205c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK			0x2060</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK			0x2064</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK			0x2068</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK			0x206c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK			0x2070</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK			0x2074</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK			0x2078</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK			0x207c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK		0x2080</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK		0x2084</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK			0x2088</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK			0x208c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK			0x2090</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK			0x2094</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK			0x2098</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK			0x209c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK	0x20a0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK	0x20a4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK	0x20a8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK	0x20ac</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK			0x20b0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK			0x20b4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK			0x20b8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK			0x20bc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK			0x20c0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK			0x20c4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK			0x20c8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK		0x20cc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK		0x20d0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK			0x20d4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK			0x20d8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK			0x20dc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK			0x20e0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK			0x20e4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK			0x20e8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK			0x20ec</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK			0x20f0</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2		0x20f4</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1		0x20f8</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK		0x20fc</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK			0x2100</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK			0x2104</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK		0x2108</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK		0x210c</div><div class='add'>+#define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK			0x2110</div><div class='add'>+#define DMYQCH_CON_PPMU_DMA_QCH							0x3000</div><div class='add'>+#define DMYQCH_CON_PUF_QCH							0x3004</div><div class='add'>+#define PCH_CON_LHM_AXI_D_SSS_PCH						0x300c</div><div class='add'>+#define PCH_CON_LHM_AXI_P_GIC_PCH						0x3010</div><div class='add'>+#define PCH_CON_LHM_AXI_P_MISC_PCH						0x3014</div><div class='add'>+#define PCH_CON_LHS_ACEL_D_MISC_PCH						0x3018</div><div class='add'>+#define PCH_CON_LHS_AST_IRI_GICCPU_PCH						0x301c</div><div class='add'>+#define PCH_CON_LHS_AXI_D_SSS_PCH						0x3020</div><div class='add'>+#define QCH_CON_ADM_AHB_SSS_QCH							0x3024</div><div class='add'>+#define QCH_CON_DIT_QCH								0x3028</div><div class='add'>+#define QCH_CON_GIC_QCH								0x3030</div><div class='add'>+#define QCH_CON_LHM_AST_ICC_CPUGIC_QCH						0x3038</div><div class='add'>+#define QCH_CON_LHM_AXI_D_SSS_QCH						0x303c</div><div class='add'>+#define QCH_CON_LHM_AXI_P_GIC_QCH						0x3040</div><div class='add'>+#define QCH_CON_LHM_AXI_P_MISC_QCH						0x3044</div><div class='add'>+#define QCH_CON_LHS_ACEL_D_MISC_QCH						0x3048</div><div class='add'>+#define QCH_CON_LHS_AST_IRI_GICCPU_QCH						0x304c</div><div class='add'>+#define QCH_CON_LHS_AXI_D_SSS_QCH						0x3050</div><div class='add'>+#define QCH_CON_MCT_QCH								0x3054</div><div class='add'>+#define QCH_CON_MISC_CMU_MISC_QCH						0x3058</div><div class='add'>+#define QCH_CON_OTP_CON_BIRA_QCH						0x305c</div><div class='add'>+#define QCH_CON_OTP_CON_BISR_QCH						0x3060</div><div class='add'>+#define QCH_CON_OTP_CON_TOP_QCH							0x3064</div><div class='add'>+#define QCH_CON_PDMA_QCH							0x3068</div><div class='add'>+#define QCH_CON_PPMU_MISC_QCH							0x306c</div><div class='add'>+#define QCH_CON_QE_DIT_QCH							0x3070</div><div class='add'>+#define QCH_CON_QE_PDMA_QCH							0x3074</div><div class='add'>+#define QCH_CON_QE_PPMU_DMA_QCH							0x3078</div><div class='add'>+#define QCH_CON_QE_RTIC_QCH							0x307c</div><div class='add'>+#define QCH_CON_QE_SPDMA_QCH							0x3080</div><div class='add'>+#define QCH_CON_QE_SSS_QCH							0x3084</div><div class='add'>+#define QCH_CON_RTIC_QCH							0x3088</div><div class='add'>+#define QCH_CON_SPDMA_QCH							0x308c</div><div class='add'>+#define QCH_CON_SSMT_DIT_QCH							0x3090</div><div class='add'>+#define QCH_CON_SSMT_PDMA_QCH							0x3094</div><div class='add'>+#define QCH_CON_SSMT_PPMU_DMA_QCH						0x3098</div><div class='add'>+#define QCH_CON_SSMT_RTIC_QCH							0x309c</div><div class='add'>+#define QCH_CON_SSMT_SPDMA_QCH							0x30a0</div><div class='add'>+#define QCH_CON_SSMT_SSS_QCH							0x30a4</div><div class='add'>+#define QCH_CON_SSS_QCH								0x30a8</div><div class='add'>+#define QCH_CON_SYSMMU_MISC_QCH							0x30ac</div><div class='add'>+#define QCH_CON_SYSMMU_SSS_QCH							0x30b0</div><div class='add'>+#define QCH_CON_SYSREG_MISC_QCH							0x30b4</div><div class='add'>+#define QCH_CON_TMU_SUB_QCH							0x30b8</div><div class='add'>+#define QCH_CON_TMU_TOP_QCH							0x30bc</div><div class='add'>+#define QCH_CON_WDT_CLUSTER0_QCH						0x30c0</div><div class='add'>+#define QCH_CON_WDT_CLUSTER1_QCH						0x30c4</div><div class='add'>+#define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC					0x3c00</div><div class='add'>+</div><div class='add'>+static const unsigned long misc_clk_regs[] __initconst = {</div><div class='add'>+	PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,</div><div class='add'>+	PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,</div><div class='add'>+	PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,</div><div class='add'>+	PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,</div><div class='add'>+	MISC_CMU_MISC_CONTROLLER_OPTION,</div><div class='add'>+	CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,</div><div class='add'>+	CLK_CON_MUX_MUX_CLK_MISC_GIC,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_MISC_BUSP,</div><div class='add'>+	CLK_CON_DIV_DIV_CLK_MISC_GIC,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,</div><div class='add'>+	CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,</div><div class='add'>+	DMYQCH_CON_PPMU_DMA_QCH,</div><div class='add'>+	DMYQCH_CON_PUF_QCH,</div><div class='add'>+	PCH_CON_LHM_AXI_D_SSS_PCH,</div><div class='add'>+	PCH_CON_LHM_AXI_P_GIC_PCH,</div><div class='add'>+	PCH_CON_LHM_AXI_P_MISC_PCH,</div><div class='add'>+	PCH_CON_LHS_ACEL_D_MISC_PCH,</div><div class='add'>+	PCH_CON_LHS_AST_IRI_GICCPU_PCH,</div><div class='add'>+	PCH_CON_LHS_AXI_D_SSS_PCH,</div><div class='add'>+	QCH_CON_ADM_AHB_SSS_QCH,</div><div class='add'>+	QCH_CON_DIT_QCH,</div><div class='add'>+	QCH_CON_GIC_QCH,</div><div class='add'>+	QCH_CON_LHM_AST_ICC_CPUGIC_QCH,</div><div class='add'>+	QCH_CON_LHM_AXI_D_SSS_QCH,</div><div class='add'>+	QCH_CON_LHM_AXI_P_GIC_QCH,</div><div class='add'>+	QCH_CON_LHM_AXI_P_MISC_QCH,</div><div class='add'>+	QCH_CON_LHS_ACEL_D_MISC_QCH,</div><div class='add'>+	QCH_CON_LHS_AST_IRI_GICCPU_QCH,</div><div class='add'>+	QCH_CON_LHS_AXI_D_SSS_QCH,</div><div class='add'>+	QCH_CON_MCT_QCH,</div><div class='add'>+	QCH_CON_MISC_CMU_MISC_QCH,</div><div class='add'>+	QCH_CON_OTP_CON_BIRA_QCH,</div><div class='add'>+	QCH_CON_OTP_CON_BISR_QCH,</div><div class='add'>+	QCH_CON_OTP_CON_TOP_QCH,</div><div class='add'>+	QCH_CON_PDMA_QCH,</div><div class='add'>+	QCH_CON_PPMU_MISC_QCH,</div><div class='add'>+	QCH_CON_QE_DIT_QCH,</div><div class='add'>+	QCH_CON_QE_PDMA_QCH,</div><div class='add'>+	QCH_CON_QE_PPMU_DMA_QCH,</div><div class='add'>+	QCH_CON_QE_RTIC_QCH,</div><div class='add'>+	QCH_CON_QE_SPDMA_QCH,</div><div class='add'>+	QCH_CON_QE_SSS_QCH,</div><div class='add'>+	QCH_CON_RTIC_QCH,</div><div class='add'>+	QCH_CON_SPDMA_QCH,</div><div class='add'>+	QCH_CON_SSMT_DIT_QCH,</div><div class='add'>+	QCH_CON_SSMT_PDMA_QCH,</div><div class='add'>+	QCH_CON_SSMT_PPMU_DMA_QCH,</div><div class='add'>+	QCH_CON_SSMT_RTIC_QCH,</div><div class='add'>+	QCH_CON_SSMT_SPDMA_QCH,</div><div class='add'>+	QCH_CON_SSMT_SSS_QCH,</div><div class='add'>+	QCH_CON_SSS_QCH,</div><div class='add'>+	QCH_CON_SYSMMU_MISC_QCH,</div><div class='add'>+	QCH_CON_SYSMMU_SSS_QCH,</div><div class='add'>+	QCH_CON_SYSREG_MISC_QCH,</div><div class='add'>+	QCH_CON_TMU_SUB_QCH,</div><div class='add'>+	QCH_CON_TMU_TOP_QCH,</div><div class='add'>+	QCH_CON_WDT_CLUSTER0_QCH,</div><div class='add'>+	QCH_CON_WDT_CLUSTER1_QCH,</div><div class='add'>+	QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+ /* List of parent clocks for Muxes in CMU_MISC */</div><div class='add'>+PNAME(mout_misc_bus_user_p)		= { "oscclk", "dout_cmu_misc_bus" };</div><div class='add'>+PNAME(mout_misc_sss_user_p)		= { "oscclk", "dout_cmu_misc_sss" };</div><div class='add'>+PNAME(mout_misc_gic_p)			= { "dout_misc_gic", "oscclk" };</div><div class='add'>+</div><div class='add'>+static const struct samsung_mux_clock misc_mux_clks[] __initconst = {</div><div class='add'>+	MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,</div><div class='add'>+	    PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,</div><div class='add'>+	    PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),</div><div class='add'>+	MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p,</div><div class='add'>+	    CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_div_clock misc_div_clks[] __initconst = {</div><div class='add'>+	DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),</div><div class='add'>+	DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",</div><div class='add'>+	    CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_gate_clock misc_gate_clks[] __initconst = {</div><div class='add'>+	GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,</div><div class='add'>+	     "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,</div><div class='add'>+	     "gout_misc_otp_con_bira_i_oscclk", "oscclk",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,</div><div class='add'>+	     "gout_misc_otp_con_bisr_i_oscclk", "oscclk",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,</div><div class='add'>+	     "gout_misc_otp_con_top_i_oscclk", "oscclk",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,</div><div class='add'>+	     "gout_misc_clk_misc_oscclk_clk", "oscclk",</div><div class='add'>+	     CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,</div><div class='add'>+	     "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,</div><div class='add'>+	     "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,</div><div class='add'>+	     "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_GIC_GICCLK,</div><div class='add'>+	     "gout_misc_gic_gicclk", "mout_misc_gic",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,</div><div class='add'>+	     "gout_misc_gpc_misc_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,</div><div class='add'>+	     "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,</div><div class='add'>+	     "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,</div><div class='add'>+	     "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,</div><div class='add'>+	     "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,</div><div class='add'>+	     "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,</div><div class='add'>+	     "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,</div><div class='add'>+	     "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",</div><div class='add'>+	     "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,</div><div class='add'>+	     "gout_misc_otp_con_bira_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,</div><div class='add'>+	     "gout_misc_otp_con_bisr_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,</div><div class='add'>+	     "gout_misc_otp_con_top_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",</div><div class='add'>+	     "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,</div><div class='add'>+	     "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,</div><div class='add'>+	     "gout_misc_ppmu_misc_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_PUF_I_CLK,</div><div class='add'>+	     "gout_misc_puf_i_clk", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_DIT_ACLK,</div><div class='add'>+	     "gout_misc_qe_dit_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_DIT_PCLK,</div><div class='add'>+	     "gout_misc_qe_dit_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,</div><div class='add'>+	     "gout_misc_qe_pdma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,</div><div class='add'>+	     "gout_misc_qe_pdma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,</div><div class='add'>+	     "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,</div><div class='add'>+	     "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,</div><div class='add'>+	     "gout_misc_qe_rtic_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,</div><div class='add'>+	     "gout_misc_qe_rtic_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,</div><div class='add'>+	     "gout_misc_qe_spdma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,</div><div class='add'>+	     "gout_misc_qe_spdma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_SSS_ACLK,</div><div class='add'>+	     "gout_misc_qe_sss_aclk", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_QE_SSS_PCLK,</div><div class='add'>+	     "gout_misc_qe_sss_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,</div><div class='add'>+	     "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,</div><div class='add'>+	     "gout_misc_clk_misc_busp_clk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,</div><div class='add'>+	     "gout_misc_clk_misc_gic_clk", "mout_misc_gic",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,</div><div class='add'>+	     "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_RTIC_I_ACLK,</div><div class='add'>+	     "gout_misc_rtic_i_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",</div><div class='add'>+	     "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SPDMA_ACLK,</div><div class='add'>+	     "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_dit_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_pdma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_rtic_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_spdma_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,</div><div class='add'>+	     "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,</div><div class='add'>+	     "gout_misc_ssmt_sss_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSS_I_ACLK,</div><div class='add'>+	     "gout_misc_sss_i_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SSS_I_PCLK,</div><div class='add'>+	     "gout_misc_sss_i_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,</div><div class='add'>+	     "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,</div><div class='add'>+	     "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,</div><div class='add'>+	     "gout_misc_sysreg_misc_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,</div><div class='add'>+	     "gout_misc_tmu_sub_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,</div><div class='add'>+	     "gout_misc_tmu_top_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,</div><div class='add'>+	     "gout_misc_wdt_cluster0_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,</div><div class='add'>+	     "gout_misc_wdt_cluster1_pclk", "dout_misc_busp",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+	GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,</div><div class='add'>+	     "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user",</div><div class='add'>+	     CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,</div><div class='add'>+	     21, 0, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct samsung_cmu_info misc_cmu_info __initconst = {</div><div class='add'>+	.mux_clks		= misc_mux_clks,</div><div class='add'>+	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),</div><div class='add'>+	.div_clks		= misc_div_clks,</div><div class='add'>+	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),</div><div class='add'>+	.gate_clks		= misc_gate_clks,</div><div class='add'>+	.nr_gate_clks		= ARRAY_SIZE(misc_gate_clks),</div><div class='add'>+	.nr_clk_ids		= CLKS_NR_MISC,</div><div class='add'>+	.clk_regs		= misc_clk_regs,</div><div class='add'>+	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),</div><div class='add'>+	.clk_name		= "dout_cmu_misc_bus",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* ---- platform_driver ----------------------------------------------------- */</div><div class='add'>+</div><div class='add'>+static int __init gs101_cmu_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	const struct samsung_cmu_info *info;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	info = of_device_get_match_data(dev);</div><div class='add'>+	exynos_arm64_register_cmu(dev, dev-&gt;of_node, info);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gs101_cmu_of_match[] = {</div><div class='add'>+	{</div><div class='add'>+		.compatible = "google,gs101-cmu-apm",</div><div class='add'>+		.data = &amp;apm_cmu_info,</div><div class='add'>+	}, {</div><div class='add'>+		.compatible = "google,gs101-cmu-misc",</div><div class='add'>+		.data = &amp;misc_cmu_info,</div><div class='add'>+	}, {</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct platform_driver gs101_cmu_driver __refdata = {</div><div class='add'>+	.driver	= {</div><div class='add'>+		.name = "gs101-cmu",</div><div class='add'>+		.of_match_table = gs101_cmu_of_match,</div><div class='add'>+		.suppress_bind_attrs = true,</div><div class='add'>+	},</div><div class='add'>+	.probe = gs101_cmu_probe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init gs101_cmu_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;gs101_cmu_driver);</div><div class='add'>+}</div><div class='add'>+core_initcall(gs101_cmu_init);</div><div class='head'>diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c<br/>index 74934c6182ce..4bbdf5e91650 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-pll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/samsung/clk-pll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-pll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-pll.c</a></div><div class='hunk'>@@ -443,6 +443,9 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,</div><div class='ctx'> 	sdiv = (pll_con3 &gt;&gt; PLL0822X_SDIV_SHIFT) &amp; PLL0822X_SDIV_MASK;</div><div class='ctx'> </div><div class='ctx'> 	fvco *= mdiv;</div><div class='add'>+	if (pll-&gt;type == pll_0516x)</div><div class='add'>+		fvco *= 2;</div><div class='add'>+</div><div class='ctx'> 	do_div(fvco, (pdiv &lt;&lt; sdiv));</div><div class='ctx'> </div><div class='ctx'> 	return (unsigned long)fvco;</div><div class='hunk'>@@ -1316,6 +1319,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,</div><div class='ctx'> 	case pll_1417x:</div><div class='ctx'> 	case pll_0818x:</div><div class='ctx'> 	case pll_0822x:</div><div class='add'>+	case pll_0516x:</div><div class='add'>+	case pll_0517x:</div><div class='add'>+	case pll_0518x:</div><div class='ctx'> 		pll-&gt;enable_offs = PLL0822X_ENABLE_SHIFT;</div><div class='ctx'> 		pll-&gt;lock_offs = PLL0822X_LOCK_STAT_SHIFT;</div><div class='ctx'> 		if (!pll-&gt;rate_table)</div><div class='head'>diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h<br/>index 0725d485c6ee..ffd3d52c0dec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-pll.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/samsung/clk-pll.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk-pll.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk-pll.h</a></div><div class='hunk'>@@ -38,6 +38,9 @@ enum samsung_pll_type {</div><div class='ctx'> 	pll_0822x,</div><div class='ctx'> 	pll_0831x,</div><div class='ctx'> 	pll_142xx,</div><div class='add'>+	pll_0516x,</div><div class='add'>+	pll_0517x,</div><div class='add'>+	pll_0518x,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \</div><div class='head'>diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h<br/>index ab9c3d7a25b3..516b716407e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/samsung/clk.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/samsung/clk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/samsung/clk.h</a></div><div class='hunk'>@@ -14,11 +14,11 @@</div><div class='ctx'> #include "clk-pll.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_clk_provider: information about clock provider</div><div class='del'>- * @reg_base: virtual address for the register base.</div><div class='del'>- * @dev: clock provider device needed for runtime PM.</div><div class='del'>- * @lock: maintains exclusion between callbacks for a given clock-provider.</div><div class='del'>- * @clk_data: holds clock related data like clk_hw* and number of clocks.</div><div class='add'>+ * struct samsung_clk_provider - information about clock provider</div><div class='add'>+ * @reg_base: virtual address for the register base</div><div class='add'>+ * @dev: clock provider device needed for runtime PM</div><div class='add'>+ * @lock: maintains exclusion between callbacks for a given clock-provider</div><div class='add'>+ * @clk_data: holds clock related data like clk_hw* and number of clocks</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_clk_provider {</div><div class='ctx'> 	void __iomem *reg_base;</div><div class='hunk'>@@ -29,10 +29,10 @@ struct samsung_clk_provider {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_clock_alias: information about mux clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @dev_name: name of the device to which this clock belongs.</div><div class='del'>- * @alias: optional clock alias name to be assigned to this clock.</div><div class='add'>+ * struct samsung_clock_alias - information about mux clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @dev_name: name of the device to which this clock belongs</div><div class='add'>+ * @alias: optional clock alias name to be assigned to this clock</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_clock_alias {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -50,12 +50,12 @@ struct samsung_clock_alias {</div><div class='ctx'> #define MHZ (1000 * 1000)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_fixed_rate_clock: information about fixed-rate clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @name: name of this fixed-rate clock.</div><div class='del'>- * @parent_name: optional parent clock name.</div><div class='del'>- * @flags: optional fixed-rate clock flags.</div><div class='del'>- * @fixed-rate: fixed clock rate of this clock.</div><div class='add'>+ * struct samsung_fixed_rate_clock - information about fixed-rate clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this fixed-rate clock</div><div class='add'>+ * @parent_name: optional parent clock name</div><div class='add'>+ * @flags: optional fixed-rate clock flags</div><div class='add'>+ * @fixed_rate: fixed clock rate of this clock</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_fixed_rate_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -74,14 +74,14 @@ struct samsung_fixed_rate_clock {</div><div class='ctx'> 		.fixed_rate	= frate,		\</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * struct samsung_fixed_factor_clock: information about fixed-factor clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @name: name of this fixed-factor clock.</div><div class='del'>- * @parent_name: parent clock name.</div><div class='del'>- * @mult: fixed multiplication factor.</div><div class='del'>- * @div: fixed division factor.</div><div class='del'>- * @flags: optional fixed-factor clock flags.</div><div class='add'>+/**</div><div class='add'>+ * struct samsung_fixed_factor_clock - information about fixed-factor clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this fixed-factor clock</div><div class='add'>+ * @parent_name: parent clock name</div><div class='add'>+ * @mult: fixed multiplication factor</div><div class='add'>+ * @div: fixed division factor</div><div class='add'>+ * @flags: optional fixed-factor clock flags</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_fixed_factor_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -103,16 +103,16 @@ struct samsung_fixed_factor_clock {</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_mux_clock: information about mux clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @name: name of this mux clock.</div><div class='del'>- * @parent_names: array of pointer to parent clock names.</div><div class='del'>- * @num_parents: number of parents listed in @parent_names.</div><div class='del'>- * @flags: optional flags for basic clock.</div><div class='del'>- * @offset: offset of the register for configuring the mux.</div><div class='del'>- * @shift: starting bit location of the mux control bit-field in @reg.</div><div class='del'>- * @width: width of the mux control bit-field in @reg.</div><div class='del'>- * @mux_flags: flags for mux-type clock.</div><div class='add'>+ * struct samsung_mux_clock - information about mux clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this mux clock</div><div class='add'>+ * @parent_names: array of pointer to parent clock names</div><div class='add'>+ * @num_parents: number of parents listed in @parent_names</div><div class='add'>+ * @flags: optional flags for basic clock</div><div class='add'>+ * @offset: offset of the register for configuring the mux</div><div class='add'>+ * @shift: starting bit location of the mux control bit-field in @reg</div><div class='add'>+ * @width: width of the mux control bit-field in @reg</div><div class='add'>+ * @mux_flags: flags for mux-type clock</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_mux_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -146,14 +146,16 @@ struct samsung_mux_clock {</div><div class='ctx'> 	__MUX(_id, cname, pnames, o, s, w, f, mf)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * struct samsung_div_clock: information about div clock</div><div class='del'>- * @name: name of this div clock.</div><div class='del'>- * @parent_name: name of the parent clock.</div><div class='del'>- * @flags: optional flags for basic clock.</div><div class='del'>- * @offset: offset of the register for configuring the div.</div><div class='del'>- * @shift: starting bit location of the div control bit-field in @reg.</div><div class='del'>- * @div_flags: flags for div-type clock.</div><div class='add'>+ * struct samsung_div_clock - information about div clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this div clock</div><div class='add'>+ * @parent_name: name of the parent clock</div><div class='add'>+ * @flags: optional flags for basic clock</div><div class='add'>+ * @offset: offset of the register for configuring the div</div><div class='add'>+ * @shift: starting bit location of the div control bit-field in @reg</div><div class='add'>+ * @width: width of the bitfield</div><div class='add'>+ * @div_flags: flags for div-type clock</div><div class='add'>+ * @table: array of divider/value pairs ending with a div set to 0</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_div_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -190,14 +192,14 @@ struct samsung_div_clock {</div><div class='ctx'> 	__DIV(_id, cname, pname, o, s, w, 0, 0, t)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_gate_clock: information about gate clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @name: name of this gate clock.</div><div class='del'>- * @parent_name: name of the parent clock.</div><div class='del'>- * @flags: optional flags for basic clock.</div><div class='del'>- * @offset: offset of the register for configuring the gate.</div><div class='del'>- * @bit_idx: bit index of the gate control bit-field in @reg.</div><div class='del'>- * @gate_flags: flags for gate-type clock.</div><div class='add'>+ * struct samsung_gate_clock - information about gate clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this gate clock</div><div class='add'>+ * @parent_name: name of the parent clock</div><div class='add'>+ * @flags: optional flags for basic clock</div><div class='add'>+ * @offset: offset of the register for configuring the gate</div><div class='add'>+ * @bit_idx: bit index of the gate control bit-field in @reg</div><div class='add'>+ * @gate_flags: flags for gate-type clock</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_gate_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -226,9 +228,9 @@ struct samsung_gate_clock {</div><div class='ctx'> #define PNAME(x) static const char * const x[] __initconst</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_clk_reg_dump: register dump of clock controller registers.</div><div class='del'>- * @offset: clock register offset from the controller base address.</div><div class='del'>- * @value: the value to be register at offset.</div><div class='add'>+ * struct samsung_clk_reg_dump - register dump of clock controller registers</div><div class='add'>+ * @offset: clock register offset from the controller base address</div><div class='add'>+ * @value: the value to be register at offset</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_clk_reg_dump {</div><div class='ctx'> 	u32	offset;</div><div class='hunk'>@@ -236,14 +238,15 @@ struct samsung_clk_reg_dump {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct samsung_pll_clock: information about pll clock</div><div class='del'>- * @id: platform specific id of the clock.</div><div class='del'>- * @name: name of this pll clock.</div><div class='del'>- * @parent_name: name of the parent clock.</div><div class='del'>- * @flags: optional flags for basic clock.</div><div class='del'>- * @con_offset: offset of the register for configuring the PLL.</div><div class='del'>- * @lock_offset: offset of the register for locking the PLL.</div><div class='del'>- * @type: Type of PLL to be registered.</div><div class='add'>+ * struct samsung_pll_clock - information about pll clock</div><div class='add'>+ * @id: platform specific id of the clock</div><div class='add'>+ * @name: name of this pll clock</div><div class='add'>+ * @parent_name: name of the parent clock</div><div class='add'>+ * @flags: optional flags for basic clock</div><div class='add'>+ * @con_offset: offset of the register for configuring the PLL</div><div class='add'>+ * @lock_offset: offset of the register for locking the PLL</div><div class='add'>+ * @type: type of PLL to be registered</div><div class='add'>+ * @rate_table: array of PLL settings for possible PLL rates</div><div class='ctx'>  */</div><div class='ctx'> struct samsung_pll_clock {</div><div class='ctx'> 	unsigned int		id;</div><div class='hunk'>@@ -302,39 +305,51 @@ struct samsung_clock_reg_cache {</div><div class='ctx'> 	unsigned int rsuspend_num;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct samsung_cmu_info - all clocks information needed for CMU registration</div><div class='add'>+ * @pll_clks: list of PLL clocks</div><div class='add'>+ * @nr_pll_clks: count of clocks in @pll_clks</div><div class='add'>+ * @mux_clks: list of mux clocks</div><div class='add'>+ * @nr_mux_clks: count of clocks in @mux_clks</div><div class='add'>+ * @div_clks: list of div clocks</div><div class='add'>+ * @nr_div_clks: count of clocks in @div_clks</div><div class='add'>+ * @gate_clks: list of gate clocks</div><div class='add'>+ * @nr_gate_clks: count of clocks in @gate_clks</div><div class='add'>+ * @fixed_clks: list of fixed clocks</div><div class='add'>+ * @nr_fixed_clks: count clocks in @fixed_clks</div><div class='add'>+ * @fixed_factor_clks: list of fixed factor clocks</div><div class='add'>+ * @nr_fixed_factor_clks: count of clocks in @fixed_factor_clks</div><div class='add'>+ * @nr_clk_ids: total number of clocks with IDs assigned</div><div class='add'>+ * @cpu_clks: list of CPU clocks</div><div class='add'>+ * @nr_cpu_clks: count of clocks in @cpu_clks</div><div class='add'>+ * @clk_regs: list of clock registers</div><div class='add'>+ * @nr_clk_regs: count of clock registers in @clk_regs</div><div class='add'>+ * @suspend_regs: list of clock registers to set before suspend</div><div class='add'>+ * @nr_suspend_regs: count of clock registers in @suspend_regs</div><div class='add'>+ * @clk_name: name of the parent clock needed for CMU register access</div><div class='add'>+ */</div><div class='ctx'> struct samsung_cmu_info {</div><div class='del'>-	/* list of pll clocks and respective count */</div><div class='ctx'> 	const struct samsung_pll_clock *pll_clks;</div><div class='ctx'> 	unsigned int nr_pll_clks;</div><div class='del'>-	/* list of mux clocks and respective count */</div><div class='ctx'> 	const struct samsung_mux_clock *mux_clks;</div><div class='ctx'> 	unsigned int nr_mux_clks;</div><div class='del'>-	/* list of div clocks and respective count */</div><div class='ctx'> 	const struct samsung_div_clock *div_clks;</div><div class='ctx'> 	unsigned int nr_div_clks;</div><div class='del'>-	/* list of gate clocks and respective count */</div><div class='ctx'> 	const struct samsung_gate_clock *gate_clks;</div><div class='ctx'> 	unsigned int nr_gate_clks;</div><div class='del'>-	/* list of fixed clocks and respective count */</div><div class='ctx'> 	const struct samsung_fixed_rate_clock *fixed_clks;</div><div class='ctx'> 	unsigned int nr_fixed_clks;</div><div class='del'>-	/* list of fixed factor clocks and respective count */</div><div class='ctx'> 	const struct samsung_fixed_factor_clock *fixed_factor_clks;</div><div class='ctx'> 	unsigned int nr_fixed_factor_clks;</div><div class='del'>-	/* total number of clocks with IDs assigned*/</div><div class='ctx'> 	unsigned int nr_clk_ids;</div><div class='del'>-	/* list of cpu clocks and respective count */</div><div class='ctx'> 	const struct samsung_cpu_clock *cpu_clks;</div><div class='ctx'> 	unsigned int nr_cpu_clks;</div><div class='ctx'> </div><div class='del'>-	/* list and number of clocks registers */</div><div class='ctx'> 	const unsigned long *clk_regs;</div><div class='ctx'> 	unsigned int nr_clk_regs;</div><div class='ctx'> </div><div class='del'>-	/* list and number of clocks registers to set before suspend */</div><div class='ctx'> 	const struct samsung_clk_reg_dump *suspend_regs;</div><div class='ctx'> 	unsigned int nr_suspend_regs;</div><div class='del'>-	/* name of the parent clock needed for CMU register access */</div><div class='ctx'> 	const char *clk_name;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c<br/>index ee4bda14a40e..1fcf4e62f347 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7100-audio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh7100-audio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7100-audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7100-audio.c</a></div><div class='hunk'>@@ -79,7 +79,7 @@ static const struct jh71x0_clk_data jh7100_audclk_data[] = {</div><div class='ctx'> 	JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),</div><div class='ctx'> 	JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),</div><div class='del'>-	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2,</div><div class='ctx'> 		    JH7100_AUDCLK_VAD_INTMEM,</div><div class='ctx'> 		    JH7100_AUDCLK_AUDIO_12288),</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c<br/>index 69cc11ea7e33..03f6f26a15d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7100.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh7100.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7100.c</a></div><div class='hunk'>@@ -24,48 +24,48 @@</div><div class='ctx'> #define JH7100_CLK_GMAC_GR_MII_RX	(JH7100_CLK_END + 3)</div><div class='ctx'> </div><div class='ctx'> static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_AUD,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL1_OUT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3,</div><div class='ctx'> 		    JH7100_CLK_OSC_AUD,</div><div class='ctx'> 		    JH7100_CLK_PLL0_OUT,</div><div class='ctx'> 		    JH7100_CLK_PLL2_OUT),</div><div class='hunk'>@@ -76,7 +76,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_OSC_AUD),</div><div class='ctx'> 	JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),</div><div class='hunk'>@@ -142,7 +142,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {</div><div class='ctx'> 	JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),</div><div class='ctx'> 	JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),</div><div class='ctx'> 	JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_CPU_AXI,</div><div class='ctx'> 		    JH7100_CLK_NNEBUS_SRC1),</div><div class='ctx'> 	JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),</div><div class='hunk'>@@ -166,7 +166,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,</div><div class='ctx'> 		    JH7100_CLK_USBPHY_ROOTDIV),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_OSC_SYS,</div><div class='ctx'> 		    JH7100_CLK_USBPHY_PLLDIV25M),</div><div class='ctx'> 	JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),</div><div class='hunk'>@@ -200,12 +200,12 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),</div><div class='ctx'> 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 3,</div><div class='ctx'> 		    JH7100_CLK_GMAC_GTX,</div><div class='ctx'> 		    JH7100_CLK_GMAC_TX_INV,</div><div class='ctx'> 		    JH7100_CLK_GMAC_RMII_TX),</div><div class='ctx'> 	JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),</div><div class='del'>-	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,</div><div class='add'>+	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 0, 2,</div><div class='ctx'> 		    JH7100_CLK_GMAC_GR_MII_RX,</div><div class='ctx'> 		    JH7100_CLK_GMAC_RMII_RX),</div><div class='ctx'> 	JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),</div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c<br/>index 62954eb7b50a..418efdad719b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-aon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh7110-aon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-aon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-aon.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> static const struct jh71x0_clk_data jh7110_aonclk_data[] = {</div><div class='ctx'> 	/* source */</div><div class='ctx'> 	JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),</div><div class='del'>-	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 0, 2,</div><div class='ctx'> 		    JH7110_AONCLK_OSC_DIV4,</div><div class='ctx'> 		    JH7110_AONCLK_OSC),</div><div class='ctx'> 	/* gmac0 */</div><div class='hunk'>@@ -39,7 +39,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {</div><div class='ctx'> 		    JH7110_AONCLK_GMAC0_GTXCLK,</div><div class='ctx'> 		    JH7110_AONCLK_GMAC0_RMII_RTX),</div><div class='ctx'> 	JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),</div><div class='del'>-	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 0, 2,</div><div class='ctx'> 		    JH7110_AONCLK_GMAC0_RGMII_RXIN,</div><div class='ctx'> 		    JH7110_AONCLK_GMAC0_RMII_RTX),</div><div class='ctx'> 	JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),</div><div class='hunk'>@@ -48,7 +48,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {</div><div class='ctx'> 	/* rtc */</div><div class='ctx'> 	JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),</div><div class='ctx'> 	JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),</div><div class='del'>-	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 0, 2,</div><div class='ctx'> 		    JH7110_AONCLK_RTC_OSC,</div><div class='ctx'> 		    JH7110_AONCLK_RTC_INTERNAL),</div><div class='ctx'> 	JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),</div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c<br/>index ce034ed28532..929b8788279e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-isp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh7110-isp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-isp.c</a></div><div class='hunk'>@@ -53,7 +53,7 @@ static const struct jh71x0_clk_data jh7110_ispclk_data[] = {</div><div class='ctx'> 		    JH7110_ISPCLK_MIPI_RX0_PXL),</div><div class='ctx'> 	JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,</div><div class='ctx'> 		    JH7110_ISPCLK_MIPI_RX0_PXL),</div><div class='del'>-	JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 0, 2,</div><div class='ctx'> 		    JH7110_ISPCLK_MIPI_RX0_PXL,</div><div class='ctx'> 		    JH7110_ISPCLK_DVP_INV),</div><div class='ctx'> 	/* ispv2_top_wrapper */</div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c<br/>index 3884eff9fe93..8f5e5abfa178 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-sys.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh7110-sys.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh7110-sys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh7110-sys.c</a></div><div class='hunk'>@@ -36,18 +36,18 @@</div><div class='ctx'> </div><div class='ctx'> static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	/* root */</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_OSC,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL0_OUT),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL2_OUT,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL1_OUT),</div><div class='ctx'> 	JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL0_OUT,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL2_OUT),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_OSC,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL2_OUT),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),</div><div class='hunk'>@@ -62,7 +62,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_MCLK_INNER,</div><div class='ctx'> 		    JH7110_SYSCLK_MCLK_EXT),</div><div class='ctx'> 	JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),</div><div class='hunk'>@@ -96,7 +96,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4,</div><div class='ctx'> 		    JH7110_SYSCLK_OSC_DIV2,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL1_DIV2,</div><div class='ctx'> 		    JH7110_SYSCLK_PLL1_DIV4,</div><div class='hunk'>@@ -186,7 +186,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,</div><div class='ctx'> 		    JH7110_SYSCLK_GMAC1_RMII_REFIN),</div><div class='ctx'> 	JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_GMAC1_RGMII_RXIN,</div><div class='ctx'> 		    JH7110_SYSCLK_GMAC1_RMII_RTX),</div><div class='ctx'> 	JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),</div><div class='hunk'>@@ -270,11 +270,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX0_BCLK_MST_INV,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX0_BCLK_MST),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk",	2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX0_BCLK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX_BCLK_EXT),</div><div class='ctx'> 	JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX0_LRCK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX_LRCK_EXT),</div><div class='ctx'> 	/* i2stx1 */</div><div class='hunk'>@@ -285,11 +285,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX1_BCLK_MST_INV,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX1_BCLK_MST),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX1_BCLK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX_BCLK_EXT),</div><div class='ctx'> 	JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX1_LRCK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2STX_LRCK_EXT),</div><div class='ctx'> 	/* i2srx */</div><div class='hunk'>@@ -300,11 +300,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_BCLK_MST_INV,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_BCLK_MST),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_BCLK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_BCLK_EXT),</div><div class='ctx'> 	JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_LRCK_MST,</div><div class='ctx'> 		    JH7110_SYSCLK_I2SRX_LRCK_EXT),</div><div class='ctx'> 	/* pdm */</div><div class='hunk'>@@ -314,7 +314,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {</div><div class='ctx'> 	JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),</div><div class='ctx'> 	JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),</div><div class='ctx'> 	JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),</div><div class='del'>-	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,</div><div class='add'>+	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 0, 2,</div><div class='ctx'> 		    JH7110_SYSCLK_TDM_INTERNAL,</div><div class='ctx'> 		    JH7110_SYSCLK_TDM_EXT),</div><div class='ctx'> 	JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),</div><div class='head'>diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h<br/>index 34bb11c72eb7..23e052fc1549 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh71x0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/starfive/clk-starfive-jh71x0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/starfive/clk-starfive-jh71x0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/starfive/clk-starfive-jh71x0.h</a></div><div class='hunk'>@@ -61,10 +61,10 @@ struct jh71x0_clk_data {</div><div class='ctx'> 	.parents = { [0] = _parent },						\</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define JH71X0__MUX(_idx, _name, _nparents, ...)				\</div><div class='add'>+#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...)			\</div><div class='ctx'> [_idx] = {									\</div><div class='ctx'> 	.name = _name,								\</div><div class='del'>-	.flags = 0,								\</div><div class='add'>+	.flags = _flags,							\</div><div class='ctx'> 	.max = ((_nparents) - 1) &lt;&lt; JH71X0_CLK_MUX_SHIFT,			\</div><div class='ctx'> 	.parents = { __VA_ARGS__ },						\</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig<br/>new file mode 100644<br/>index 000000000000..3c8493a94a11<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+# common clock support for STMicroelectronics SoC family.</div><div class='add'>+</div><div class='add'>+menuconfig COMMON_CLK_STM32MP</div><div class='add'>+	bool "Clock support for common STM32MP clocks"</div><div class='add'>+	depends on ARCH_STM32 || COMPILE_TEST</div><div class='add'>+	default y</div><div class='add'>+	select RESET_CONTROLLER</div><div class='add'>+	help</div><div class='add'>+	  Support for STM32MP SoC family clocks.</div><div class='add'>+</div><div class='add'>+if COMMON_CLK_STM32MP</div><div class='add'>+</div><div class='add'>+config COMMON_CLK_STM32MP135</div><div class='add'>+	bool "Clock driver for stm32mp13x clocks"</div><div class='add'>+	depends on ARM || COMPILE_TEST</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Support for stm32mp13x SoC family clocks.</div><div class='add'>+</div><div class='add'>+config COMMON_CLK_STM32MP157</div><div class='add'>+	bool "Clock driver for stm32mp15x clocks"</div><div class='add'>+	depends on ARM || COMPILE_TEST</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Support for stm32mp15x SoC family clocks.</div><div class='add'>+</div><div class='add'>+endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile<br/>index 95bd2230bba0..5ced7fe3ddec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/Makefile</a></div><div class='hunk'>@@ -1 +1,2 @@</div><div class='ctx'> obj-$(CONFIG_COMMON_CLK_STM32MP135)	+= clk-stm32mp13.o clk-stm32-core.o reset-stm32.o</div><div class='add'>+obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o reset-stm32.o</div><div class='head'>diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c<br/>index 067b918a8894..58705fcad334 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/clk-stm32-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32-core.c</a></div><div class='hunk'>@@ -70,6 +70,7 @@ static int stm32_rcc_clock_init(struct device *dev,</div><div class='ctx'> int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,</div><div class='ctx'> 		   void __iomem *base)</div><div class='ctx'> {</div><div class='add'>+	const struct stm32_rcc_match_data *rcc_match_data;</div><div class='ctx'> 	const struct of_device_id *match;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -79,8 +80,10 @@ int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	rcc_match_data = match-&gt;data;</div><div class='add'>+</div><div class='ctx'> 	/* RCC Reset Configuration */</div><div class='del'>-	err = stm32_rcc_reset_init(dev, match, base);</div><div class='add'>+	err = stm32_rcc_reset_init(dev, rcc_match_data-&gt;reset_data, base);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		pr_err("stm32 reset failed to initialize\n");</div><div class='ctx'> 		return err;</div><div class='head'>diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h<br/>index 76cffda02308..bb5aa19a792d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32-core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/clk-stm32-core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32-core.h</a></div><div class='hunk'>@@ -70,15 +70,12 @@ struct stm32_rcc_match_data {</div><div class='ctx'> 	const struct clock_config	*tab_clocks;</div><div class='ctx'> 	unsigned int			maxbinding;</div><div class='ctx'> 	struct clk_stm32_clock_data	*clock_data;</div><div class='del'>-	u32				clear_offset;</div><div class='add'>+	struct clk_stm32_reset_data	*reset_data;</div><div class='ctx'> 	int (*check_security)(void __iomem *base,</div><div class='ctx'> 			      const struct clock_config *cfg);</div><div class='ctx'> 	int (*multi_mux)(void __iomem *base, const struct clock_config *cfg);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,</div><div class='del'>-			 void __iomem *base);</div><div class='del'>-</div><div class='ctx'> int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,</div><div class='ctx'> 		   void __iomem *base);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c<br/>index 939779f66867..7e2337297402 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/clk-stm32mp1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/clk-stm32mp1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32mp1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32mp1.c</a></div><div class='hunk'>@@ -20,6 +20,10 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;dt-bindings/clock/stm32mp1-clks.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "reset-stm32.h"</div><div class='add'>+</div><div class='add'>+#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)</div><div class='add'>+</div><div class='ctx'> static DEFINE_SPINLOCK(rlock);</div><div class='ctx'> </div><div class='ctx'> #define RCC_OCENSETR		0x0C</div><div class='hunk'>@@ -2137,22 +2141,27 @@ struct stm32_rcc_match_data {</div><div class='ctx'> 	const struct clock_config *cfg;</div><div class='ctx'> 	unsigned int num;</div><div class='ctx'> 	unsigned int maxbinding;</div><div class='del'>-	u32 clear_offset;</div><div class='add'>+	struct clk_stm32_reset_data *reset_data;</div><div class='ctx'> 	bool (*check_security)(const struct clock_config *cfg);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_stm32_reset_data stm32mp1_reset_data = {</div><div class='add'>+	.nr_lines	= STM32MP1_RESET_ID_MASK,</div><div class='add'>+	.clear_offset	= RCC_CLR,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct stm32_rcc_match_data stm32mp1_data = {</div><div class='ctx'> 	.cfg		= stm32mp1_clock_cfg,</div><div class='ctx'> 	.num		= ARRAY_SIZE(stm32mp1_clock_cfg),</div><div class='ctx'> 	.maxbinding	= STM32MP1_LAST_CLK,</div><div class='del'>-	.clear_offset	= RCC_CLR,</div><div class='add'>+	.reset_data	= &amp;stm32mp1_reset_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct stm32_rcc_match_data stm32mp1_data_secure = {</div><div class='ctx'> 	.cfg		= stm32mp1_clock_cfg,</div><div class='ctx'> 	.num		= ARRAY_SIZE(stm32mp1_clock_cfg),</div><div class='ctx'> 	.maxbinding	= STM32MP1_LAST_CLK,</div><div class='del'>-	.clear_offset	= RCC_CLR,</div><div class='add'>+	.reset_data	= &amp;stm32mp1_reset_data,</div><div class='ctx'> 	.check_security = &amp;stm32_check_security</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -2193,113 +2202,6 @@ static int stm32_register_hw_clk(struct device *dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define STM32_RESET_ID_MASK GENMASK(15, 0)</div><div class='del'>-</div><div class='del'>-struct stm32_reset_data {</div><div class='del'>-	/* reset lock */</div><div class='del'>-	spinlock_t			lock;</div><div class='del'>-	struct reset_controller_dev	rcdev;</div><div class='del'>-	void __iomem			*membase;</div><div class='del'>-	u32				clear_offset;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static inline struct stm32_reset_data *</div><div class='del'>-to_stm32_reset_data(struct reset_controller_dev *rcdev)</div><div class='del'>-{</div><div class='del'>-	return container_of(rcdev, struct stm32_reset_data, rcdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int stm32_reset_update(struct reset_controller_dev *rcdev,</div><div class='del'>-			      unsigned long id, bool assert)</div><div class='del'>-{</div><div class='del'>-	struct stm32_reset_data *data = to_stm32_reset_data(rcdev);</div><div class='del'>-	int reg_width = sizeof(u32);</div><div class='del'>-	int bank = id / (reg_width * BITS_PER_BYTE);</div><div class='del'>-	int offset = id % (reg_width * BITS_PER_BYTE);</div><div class='del'>-</div><div class='del'>-	if (data-&gt;clear_offset) {</div><div class='del'>-		void __iomem *addr;</div><div class='del'>-</div><div class='del'>-		addr = data-&gt;membase + (bank * reg_width);</div><div class='del'>-		if (!assert)</div><div class='del'>-			addr += data-&gt;clear_offset;</div><div class='del'>-</div><div class='del'>-		writel(BIT(offset), addr);</div><div class='del'>-</div><div class='del'>-	} else {</div><div class='del'>-		unsigned long flags;</div><div class='del'>-		u32 reg;</div><div class='del'>-</div><div class='del'>-		spin_lock_irqsave(&amp;data-&gt;lock, flags);</div><div class='del'>-</div><div class='del'>-		reg = readl(data-&gt;membase + (bank * reg_width));</div><div class='del'>-</div><div class='del'>-		if (assert)</div><div class='del'>-			reg |= BIT(offset);</div><div class='del'>-		else</div><div class='del'>-			reg &amp;= ~BIT(offset);</div><div class='del'>-</div><div class='del'>-		writel(reg, data-&gt;membase + (bank * reg_width));</div><div class='del'>-</div><div class='del'>-		spin_unlock_irqrestore(&amp;data-&gt;lock, flags);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int stm32_reset_assert(struct reset_controller_dev *rcdev,</div><div class='del'>-			      unsigned long id)</div><div class='del'>-{</div><div class='del'>-	return stm32_reset_update(rcdev, id, true);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,</div><div class='del'>-				unsigned long id)</div><div class='del'>-{</div><div class='del'>-	return stm32_reset_update(rcdev, id, false);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int stm32_reset_status(struct reset_controller_dev *rcdev,</div><div class='del'>-			      unsigned long id)</div><div class='del'>-{</div><div class='del'>-	struct stm32_reset_data *data = to_stm32_reset_data(rcdev);</div><div class='del'>-	int reg_width = sizeof(u32);</div><div class='del'>-	int bank = id / (reg_width * BITS_PER_BYTE);</div><div class='del'>-	int offset = id % (reg_width * BITS_PER_BYTE);</div><div class='del'>-	u32 reg;</div><div class='del'>-</div><div class='del'>-	reg = readl(data-&gt;membase + (bank * reg_width));</div><div class='del'>-</div><div class='del'>-	return !!(reg &amp; BIT(offset));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct reset_control_ops stm32_reset_ops = {</div><div class='del'>-	.assert		= stm32_reset_assert,</div><div class='del'>-	.deassert	= stm32_reset_deassert,</div><div class='del'>-	.status		= stm32_reset_status,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,</div><div class='del'>-				const struct of_device_id *match)</div><div class='del'>-{</div><div class='del'>-	const struct stm32_rcc_match_data *data = match-&gt;data;</div><div class='del'>-	struct stm32_reset_data *reset_data = NULL;</div><div class='del'>-</div><div class='del'>-	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);</div><div class='del'>-	if (!reset_data)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	spin_lock_init(&amp;reset_data-&gt;lock);</div><div class='del'>-	reset_data-&gt;membase = base;</div><div class='del'>-	reset_data-&gt;rcdev.owner = THIS_MODULE;</div><div class='del'>-	reset_data-&gt;rcdev.ops = &amp;stm32_reset_ops;</div><div class='del'>-	reset_data-&gt;rcdev.of_node = dev_of_node(dev);</div><div class='del'>-	reset_data-&gt;rcdev.nr_resets = STM32_RESET_ID_MASK;</div><div class='del'>-	reset_data-&gt;clear_offset = data-&gt;clear_offset;</div><div class='del'>-</div><div class='del'>-	return reset_controller_register(&amp;reset_data-&gt;rcdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,</div><div class='ctx'> 				const struct of_device_id *match)</div><div class='ctx'> {</div><div class='hunk'>@@ -2342,6 +2244,7 @@ static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,</div><div class='ctx'> static int stm32_rcc_init(struct device *dev, void __iomem *base,</div><div class='ctx'> 			  const struct of_device_id *match_data)</div><div class='ctx'> {</div><div class='add'>+	const struct stm32_rcc_match_data *rcc_match_data;</div><div class='ctx'> 	const struct of_device_id *match;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -2351,8 +2254,10 @@ static int stm32_rcc_init(struct device *dev, void __iomem *base,</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	rcc_match_data = match-&gt;data;</div><div class='add'>+</div><div class='ctx'> 	/* RCC Reset Configuration */</div><div class='del'>-	err = stm32_rcc_reset_init(dev, base, match);</div><div class='add'>+	err = stm32_rcc_reset_init(dev, rcc_match_data-&gt;reset_data, base);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		pr_err("stm32mp1 reset failed to initialize\n");</div><div class='ctx'> 		return err;</div><div class='head'>diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c<br/>index c4a737482fe5..d4ecb3c34a1b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32mp13.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/clk-stm32mp13.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/clk-stm32mp13.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/clk-stm32mp13.c</a></div><div class='hunk'>@@ -10,8 +10,10 @@</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;dt-bindings/clock/stm32mp13-clks.h&gt;</div><div class='ctx'> #include "clk-stm32-core.h"</div><div class='add'>+#include "reset-stm32.h"</div><div class='ctx'> #include "stm32mp13_rcc.h"</div><div class='ctx'> </div><div class='add'>+#define STM32MP1_RESET_ID_MASK GENMASK(15, 0)</div><div class='ctx'> #define RCC_CLR_OFFSET		0x4</div><div class='ctx'> </div><div class='ctx'> /* STM32 Gates definition */</div><div class='hunk'>@@ -1511,13 +1513,18 @@ static struct clk_stm32_clock_data stm32mp13_clock_data = {</div><div class='ctx'> 	.is_multi_mux	= stm32mp13_is_multi_mux,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct clk_stm32_reset_data stm32mp13_reset_data = {</div><div class='add'>+	.nr_lines	= STM32MP1_RESET_ID_MASK,</div><div class='add'>+	.clear_offset	= RCC_CLR_OFFSET,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct stm32_rcc_match_data stm32mp13_data = {</div><div class='ctx'> 	.tab_clocks	= stm32mp13_clock_cfg,</div><div class='ctx'> 	.num_clocks	= ARRAY_SIZE(stm32mp13_clock_cfg),</div><div class='ctx'> 	.clock_data	= &amp;stm32mp13_clock_data,</div><div class='ctx'> 	.check_security = &amp;stm32mp13_clock_is_provided_by_secure,</div><div class='ctx'> 	.maxbinding	= STM32MP1_LAST_CLK,</div><div class='del'>-	.clear_offset	= RCC_CLR_OFFSET,</div><div class='add'>+	.reset_data	= &amp;stm32mp13_reset_data,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id stm32mp13_match_data[] = {</div><div class='head'>diff --git a/drivers/clk/stm32/reset-stm32.c b/drivers/clk/stm32/reset-stm32.c<br/>index e89381528af9..14c2ee1eebee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/reset-stm32.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/reset-stm32.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/reset-stm32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/reset-stm32.c</a></div><div class='hunk'>@@ -11,9 +11,7 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> </div><div class='del'>-#include "clk-stm32-core.h"</div><div class='del'>-</div><div class='del'>-#define STM32_RESET_ID_MASK GENMASK(15, 0)</div><div class='add'>+#include "reset-stm32.h"</div><div class='ctx'> </div><div class='ctx'> struct stm32_reset_data {</div><div class='ctx'> 	/* reset lock */</div><div class='hunk'>@@ -99,24 +97,22 @@ static const struct reset_control_ops stm32_reset_ops = {</div><div class='ctx'> 	.status		= stm32_reset_status,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,</div><div class='add'>+int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,</div><div class='ctx'> 			 void __iomem *base)</div><div class='ctx'> {</div><div class='del'>-	const struct stm32_rcc_match_data *data = match-&gt;data;</div><div class='del'>-	struct stm32_reset_data *reset_data = NULL;</div><div class='del'>-</div><div class='del'>-	data = match-&gt;data;</div><div class='add'>+	struct stm32_reset_data *reset_data;</div><div class='ctx'> </div><div class='ctx'> 	reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);</div><div class='ctx'> 	if (!reset_data)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;reset_data-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	reset_data-&gt;membase = base;</div><div class='ctx'> 	reset_data-&gt;rcdev.owner = THIS_MODULE;</div><div class='ctx'> 	reset_data-&gt;rcdev.ops = &amp;stm32_reset_ops;</div><div class='ctx'> 	reset_data-&gt;rcdev.of_node = dev_of_node(dev);</div><div class='del'>-	reset_data-&gt;rcdev.nr_resets = STM32_RESET_ID_MASK;</div><div class='add'>+	reset_data-&gt;rcdev.nr_resets = data-&gt;nr_lines;</div><div class='ctx'> 	reset_data-&gt;clear_offset = data-&gt;clear_offset;</div><div class='ctx'> </div><div class='ctx'> 	return reset_controller_register(&amp;reset_data-&gt;rcdev);</div><div class='head'>diff --git a/drivers/clk/stm32/reset-stm32.h b/drivers/clk/stm32/reset-stm32.h<br/>index 6eb6ea4b55ab..8cf1cc9be480 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/stm32/reset-stm32.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/stm32/reset-stm32.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/stm32/reset-stm32.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/stm32/reset-stm32.h</a></div><div class='hunk'>@@ -4,5 +4,11 @@</div><div class='ctx'>  * Author: Gabriel Fernandez &lt;gabriel.fernandez@foss.st.com&gt; for STMicroelectronics.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-int stm32_rcc_reset_init(struct device *dev, const struct of_device_id *match,</div><div class='add'>+struct clk_stm32_reset_data {</div><div class='add'>+	const struct reset_control_ops *ops;</div><div class='add'>+	unsigned int nr_lines;</div><div class='add'>+	u32 clear_offset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int stm32_rcc_reset_init(struct device *dev, struct clk_stm32_reset_data *data,</div><div class='ctx'> 			 void __iomem *base);</div><div class='head'>diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c<br/>index eed64547ad42..853f84398e2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/sunxi-ng/ccu_nkm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/sunxi-ng/ccu_nkm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/sunxi-ng/ccu_nkm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/sunxi-ng/ccu_nkm.c</a></div><div class='hunk'>@@ -21,17 +21,16 @@ static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common</div><div class='ctx'> 						       unsigned long *parent, unsigned long rate,</div><div class='ctx'> 						       struct _ccu_nkm *nkm)</div><div class='ctx'> {</div><div class='del'>-	unsigned long best_rate = 0, best_parent_rate = *parent, tmp_parent = *parent;</div><div class='add'>+	unsigned long best_rate = 0, best_parent_rate = *parent;</div><div class='ctx'> 	unsigned long best_n = 0, best_k = 0, best_m = 0;</div><div class='ctx'> 	unsigned long _n, _k, _m;</div><div class='ctx'> </div><div class='ctx'> 	for (_k = nkm-&gt;min_k; _k &lt;= nkm-&gt;max_k; _k++) {</div><div class='ctx'> 		for (_n = nkm-&gt;min_n; _n &lt;= nkm-&gt;max_n; _n++) {</div><div class='ctx'> 			for (_m = nkm-&gt;min_m; _m &lt;= nkm-&gt;max_m; _m++) {</div><div class='del'>-				unsigned long tmp_rate;</div><div class='add'>+				unsigned long tmp_rate, tmp_parent;</div><div class='ctx'> </div><div class='ctx'> 				tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));</div><div class='del'>-</div><div class='ctx'> 				tmp_rate = tmp_parent * _n * _k / _m;</div><div class='ctx'> </div><div class='ctx'> 				if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||</div><div class='head'>diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c<br/>index d56822ce6126..6a6e5d9292e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/xilinx/clk-xlnx-clock-wizard.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/xilinx/clk-xlnx-clock-wizard.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/xilinx/clk-xlnx-clock-wizard.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/xilinx/clk-xlnx-clock-wizard.c</a></div><div class='hunk'>@@ -23,15 +23,41 @@</div><div class='ctx'> #define WZRD_NUM_OUTPUTS	7</div><div class='ctx'> #define WZRD_ACLK_MAX_FREQ	250000000UL</div><div class='ctx'> </div><div class='del'>-#define WZRD_CLK_CFG_REG(n)	(0x200 + 4 * (n))</div><div class='add'>+#define WZRD_CLK_CFG_REG(v, n)	(0x200 + 0x130 * (v) + 4 * (n))</div><div class='ctx'> </div><div class='ctx'> #define WZRD_CLKOUT0_FRAC_EN	BIT(18)</div><div class='del'>-#define WZRD_CLKFBOUT_FRAC_EN	BIT(26)</div><div class='add'>+#define WZRD_CLKFBOUT_1		0</div><div class='add'>+#define WZRD_CLKFBOUT_2		1</div><div class='add'>+#define WZRD_CLKOUT0_1		2</div><div class='add'>+#define WZRD_CLKOUT0_2		3</div><div class='add'>+#define WZRD_DESKEW_2		20</div><div class='add'>+#define WZRD_DIVCLK		21</div><div class='add'>+#define WZRD_CLKFBOUT_4		51</div><div class='add'>+#define WZRD_CLKFBOUT_3		48</div><div class='add'>+#define WZRD_DUTY_CYCLE		2</div><div class='add'>+#define WZRD_O_DIV		4</div><div class='add'>+</div><div class='add'>+#define WZRD_CLKFBOUT_FRAC_EN	BIT(1)</div><div class='add'>+#define WZRD_CLKFBOUT_PREDIV2	(BIT(11) | BIT(12) | BIT(9))</div><div class='add'>+#define WZRD_MULT_PREDIV2	(BIT(10) | BIT(9) | BIT(12))</div><div class='add'>+#define WZRD_CLKFBOUT_EDGE	BIT(8)</div><div class='add'>+#define WZRD_P5EN		BIT(13)</div><div class='add'>+#define WZRD_P5EN_SHIFT		13</div><div class='add'>+#define WZRD_P5FEDGE		BIT(15)</div><div class='add'>+#define WZRD_DIVCLK_EDGE	BIT(10)</div><div class='add'>+#define WZRD_P5FEDGE_SHIFT	15</div><div class='add'>+#define WZRD_CLKOUT0_PREDIV2	BIT(11)</div><div class='add'>+#define WZRD_EDGE_SHIFT		8</div><div class='ctx'> </div><div class='ctx'> #define WZRD_CLKFBOUT_MULT_SHIFT	8</div><div class='ctx'> #define WZRD_CLKFBOUT_MULT_MASK		(0xff &lt;&lt; WZRD_CLKFBOUT_MULT_SHIFT)</div><div class='add'>+#define WZRD_CLKFBOUT_L_SHIFT	0</div><div class='add'>+#define WZRD_CLKFBOUT_H_SHIFT	8</div><div class='add'>+#define WZRD_CLKFBOUT_L_MASK	GENMASK(7, 0)</div><div class='add'>+#define WZRD_CLKFBOUT_H_MASK	GENMASK(15, 8)</div><div class='ctx'> #define WZRD_CLKFBOUT_FRAC_SHIFT	16</div><div class='ctx'> #define WZRD_CLKFBOUT_FRAC_MASK		(0x3ff &lt;&lt; WZRD_CLKFBOUT_FRAC_SHIFT)</div><div class='add'>+#define WZRD_VERSAL_FRAC_MASK		GENMASK(5, 0)</div><div class='ctx'> #define WZRD_DIVCLK_DIVIDE_SHIFT	0</div><div class='ctx'> #define WZRD_DIVCLK_DIVIDE_MASK		(0xff &lt;&lt; WZRD_DIVCLK_DIVIDE_SHIFT)</div><div class='ctx'> #define WZRD_CLKOUT_DIVIDE_SHIFT	0</div><div class='hunk'>@@ -45,6 +71,7 @@</div><div class='ctx'> #define WZRD_DR_STATUS_REG_OFFSET	0x04</div><div class='ctx'> #define WZRD_DR_LOCK_BIT_MASK		0x00000001</div><div class='ctx'> #define WZRD_DR_INIT_REG_OFFSET		0x25C</div><div class='add'>+#define WZRD_DR_INIT_VERSAL_OFFSET	0x14</div><div class='ctx'> #define WZRD_DR_DIV_TO_PHASE_OFFSET	4</div><div class='ctx'> #define WZRD_DR_BEGIN_DYNA_RECONF	0x03</div><div class='ctx'> #define WZRD_DR_BEGIN_DYNA_RECONF_5_2	0x07</div><div class='hunk'>@@ -52,6 +79,8 @@</div><div class='ctx'> </div><div class='ctx'> #define WZRD_USEC_POLL		10</div><div class='ctx'> #define WZRD_TIMEOUT_POLL		1000</div><div class='add'>+#define WZRD_FRAC_GRADIENT		64</div><div class='add'>+#define PREDIV2_MULT			2</div><div class='ctx'> </div><div class='ctx'> /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */</div><div class='ctx'> #define DIV_O				0x01</div><div class='hunk'>@@ -65,6 +94,14 @@</div><div class='ctx'> #define WZRD_VCO_MAX			1600000000</div><div class='ctx'> #define WZRD_O_MIN			1</div><div class='ctx'> #define WZRD_O_MAX			128</div><div class='add'>+#define VER_WZRD_M_MIN			4</div><div class='add'>+#define VER_WZRD_M_MAX			432</div><div class='add'>+#define VER_WZRD_D_MIN			1</div><div class='add'>+#define VER_WZRD_D_MAX			123</div><div class='add'>+#define VER_WZRD_VCO_MIN		2160000000ULL</div><div class='add'>+#define VER_WZRD_VCO_MAX		4320000000ULL</div><div class='add'>+#define VER_WZRD_O_MIN			2</div><div class='add'>+#define VER_WZRD_O_MAX			511</div><div class='ctx'> #define WZRD_MIN_ERR			20000</div><div class='ctx'> #define WZRD_FRAC_POINTS		1000</div><div class='ctx'> </div><div class='hunk'>@@ -135,6 +172,10 @@ struct clk_wzrd_divider {</div><div class='ctx'> 	spinlock_t *lock;  /* divider lock */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct versal_clk_data {</div><div class='add'>+	bool is_versal;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)</div><div class='ctx'> </div><div class='ctx'> /* maximum frequencies for input/output clocks per speed grade */</div><div class='hunk'>@@ -147,6 +188,31 @@ static const unsigned long clk_wzrd_max_freq[] = {</div><div class='ctx'> /* spin lock variable for clk_wzrd */</div><div class='ctx'> static DEFINE_SPINLOCK(clkwzrd_lock);</div><div class='ctx'> </div><div class='add'>+static unsigned long clk_wzrd_recalc_rate_ver(struct clk_hw *hw,</div><div class='add'>+					      unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	void __iomem *div_addr = divider-&gt;base + divider-&gt;offset;</div><div class='add'>+	u32 div, p5en, edge, prediv2, all;</div><div class='add'>+	unsigned int vall, valh;</div><div class='add'>+</div><div class='add'>+	edge = !!(readl(div_addr) &amp; WZRD_CLKFBOUT_EDGE);</div><div class='add'>+	p5en = !!(readl(div_addr) &amp; WZRD_P5EN);</div><div class='add'>+	prediv2 = !!(readl(div_addr) &amp; WZRD_CLKOUT0_PREDIV2);</div><div class='add'>+	vall = readl(div_addr + 4) &amp; WZRD_CLKFBOUT_L_MASK;</div><div class='add'>+	valh = readl(div_addr + 4) &gt;&gt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	all = valh + vall + edge;</div><div class='add'>+	if (!all)</div><div class='add'>+		all = 1;</div><div class='add'>+</div><div class='add'>+	if (prediv2)</div><div class='add'>+		div = 2 * all + prediv2 * p5en;</div><div class='add'>+	else</div><div class='add'>+		div = all;</div><div class='add'>+</div><div class='add'>+	return DIV_ROUND_UP_ULL((u64)parent_rate, div);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,</div><div class='ctx'> 					  unsigned long parent_rate)</div><div class='ctx'> {</div><div class='hunk'>@@ -161,19 +227,64 @@ static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,</div><div class='ctx'> 			divider-&gt;flags, divider-&gt;width);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int clk_wzrd_ver_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,</div><div class='add'>+					 unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	void __iomem *div_addr = divider-&gt;base + divider-&gt;offset;</div><div class='add'>+	u32 value, regh, edged, p5en, p5fedge, regval, regval1;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(divider-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	value = DIV_ROUND_CLOSEST(parent_rate, rate);</div><div class='add'>+</div><div class='add'>+	regh = (value / 4);</div><div class='add'>+	regval1 = readl(div_addr);</div><div class='add'>+	regval1 |= WZRD_CLKFBOUT_PREDIV2;</div><div class='add'>+	regval1 = regval1 &amp; ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);</div><div class='add'>+	if (value % 4 &gt; 1) {</div><div class='add'>+		edged = 1;</div><div class='add'>+		regval1 |= (edged &lt;&lt; WZRD_EDGE_SHIFT);</div><div class='add'>+	}</div><div class='add'>+	p5fedge = value % 2;</div><div class='add'>+	p5en = value % 2;</div><div class='add'>+	regval1 = regval1 | p5en &lt;&lt; WZRD_P5EN_SHIFT | p5fedge &lt;&lt; WZRD_P5FEDGE_SHIFT;</div><div class='add'>+	writel(regval1, div_addr);</div><div class='add'>+</div><div class='add'>+	regval = regh | regh &lt;&lt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	writel(regval, div_addr + 4);</div><div class='add'>+	/* Check status register */</div><div class='add'>+	err = readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='add'>+					value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+					WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_reconfig;</div><div class='add'>+</div><div class='add'>+	/* Initiate reconfiguration */</div><div class='add'>+	writel(WZRD_DR_BEGIN_DYNA_RECONF,</div><div class='add'>+	       divider-&gt;base + WZRD_DR_INIT_VERSAL_OFFSET);</div><div class='add'>+</div><div class='add'>+	/* Check status register */</div><div class='add'>+	err = readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='add'>+					value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+					WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+err_reconfig:</div><div class='add'>+	spin_unlock_irqrestore(divider-&gt;lock, flags);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 				     unsigned long parent_rate)</div><div class='ctx'> {</div><div class='del'>-	int err;</div><div class='del'>-	u32 value;</div><div class='del'>-	unsigned long flags = 0;</div><div class='ctx'> 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='ctx'> 	void __iomem *div_addr = divider-&gt;base + divider-&gt;offset;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u32 value;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-	if (divider-&gt;lock)</div><div class='del'>-		spin_lock_irqsave(divider-&gt;lock, flags);</div><div class='del'>-	else</div><div class='del'>-		__acquire(divider-&gt;lock);</div><div class='add'>+	spin_lock_irqsave(divider-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	value = DIV_ROUND_CLOSEST(parent_rate, rate);</div><div class='ctx'> </div><div class='hunk'>@@ -185,9 +296,9 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);</div><div class='ctx'> </div><div class='ctx'> 	/* Check status register */</div><div class='del'>-	err = readl_poll_timeout(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='del'>-				 value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='del'>-				 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+	err = readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='add'>+					value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+					WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_reconfig;</div><div class='ctx'> </div><div class='hunk'>@@ -198,14 +309,11 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	       divider-&gt;base + WZRD_DR_INIT_REG_OFFSET);</div><div class='ctx'> </div><div class='ctx'> 	/* Check status register */</div><div class='del'>-	err = readl_poll_timeout(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='del'>-				 value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='del'>-				 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+	err = readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET,</div><div class='add'>+					value, value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+					WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='ctx'> err_reconfig:</div><div class='del'>-	if (divider-&gt;lock)</div><div class='del'>-		spin_unlock_irqrestore(divider-&gt;lock, flags);</div><div class='del'>-	else</div><div class='del'>-		__release(divider-&gt;lock);</div><div class='add'>+	spin_unlock_irqrestore(divider-&gt;lock, flags);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -223,18 +331,66 @@ static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	return *prate / div;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int clk_wzrd_get_divisors_ver(struct clk_hw *hw, unsigned long rate,</div><div class='add'>+				     unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	u64 vco_freq, freq, diff, vcomin, vcomax;</div><div class='add'>+	u32 m, d, o;</div><div class='add'>+	u32 mmin, mmax, dmin, dmax, omin, omax;</div><div class='add'>+</div><div class='add'>+	mmin = VER_WZRD_M_MIN;</div><div class='add'>+	mmax = VER_WZRD_M_MAX;</div><div class='add'>+	dmin = VER_WZRD_D_MIN;</div><div class='add'>+	dmax = VER_WZRD_D_MAX;</div><div class='add'>+	omin = VER_WZRD_O_MIN;</div><div class='add'>+	omax = VER_WZRD_O_MAX;</div><div class='add'>+	vcomin = VER_WZRD_VCO_MIN;</div><div class='add'>+	vcomax = VER_WZRD_VCO_MAX;</div><div class='add'>+</div><div class='add'>+	for (m = mmin; m &lt;= mmax; m++) {</div><div class='add'>+		for (d = dmin; d &lt;= dmax; d++) {</div><div class='add'>+			vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);</div><div class='add'>+			if (vco_freq &gt;= vcomin &amp;&amp; vco_freq &lt;= vcomax) {</div><div class='add'>+				for (o = omin; o &lt;= omax; o++) {</div><div class='add'>+					freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);</div><div class='add'>+					diff = abs(freq - rate);</div><div class='add'>+</div><div class='add'>+					if (diff &lt; WZRD_MIN_ERR) {</div><div class='add'>+						divider-&gt;m = m;</div><div class='add'>+						divider-&gt;d = d;</div><div class='add'>+						divider-&gt;o = o;</div><div class='add'>+						return 0;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return -EBUSY;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 				 unsigned long parent_rate)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='del'>-	unsigned long vco_freq, freq, diff;</div><div class='add'>+	u64 vco_freq, freq, diff, vcomin, vcomax;</div><div class='ctx'> 	u32 m, d, o;</div><div class='del'>-</div><div class='del'>-	for (m = WZRD_M_MIN; m &lt;= WZRD_M_MAX; m++) {</div><div class='del'>-		for (d = WZRD_D_MIN; d &lt;= WZRD_D_MAX; d++) {</div><div class='add'>+	u32 mmin, mmax, dmin, dmax, omin, omax;</div><div class='add'>+</div><div class='add'>+	mmin = WZRD_M_MIN;</div><div class='add'>+	mmax = WZRD_M_MAX;</div><div class='add'>+	dmin = WZRD_D_MIN;</div><div class='add'>+	dmax = WZRD_D_MAX;</div><div class='add'>+	omin = WZRD_O_MIN;</div><div class='add'>+	omax = WZRD_O_MAX;</div><div class='add'>+	vcomin = WZRD_VCO_MIN;</div><div class='add'>+	vcomax = WZRD_VCO_MAX;</div><div class='add'>+</div><div class='add'>+	for (m = mmin; m &lt;= mmax; m++) {</div><div class='add'>+		for (d = dmin; d &lt;= dmax; d++) {</div><div class='ctx'> 			vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);</div><div class='del'>-			if (vco_freq &gt;= WZRD_VCO_MIN &amp;&amp; vco_freq &lt;= WZRD_VCO_MAX) {</div><div class='del'>-				for (o = WZRD_O_MIN; o &lt;= WZRD_O_MAX; o++) {</div><div class='add'>+			if (vco_freq &gt;= vcomin &amp;&amp; vco_freq &lt;= vcomax) {</div><div class='add'>+				for (o = omin; o &lt;= omax; o++) {</div><div class='ctx'> 					freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);</div><div class='ctx'> 					diff = abs(freq - rate);</div><div class='ctx'> </div><div class='hunk'>@@ -251,12 +407,99 @@ static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	return -EBUSY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)</div><div class='add'>+{</div><div class='add'>+	u32 value;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* Check status register */</div><div class='add'>+	err = readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET, value,</div><div class='add'>+					value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+					WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+	if (err)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	/* Initiate reconfiguration */</div><div class='add'>+	writel(WZRD_DR_BEGIN_DYNA_RECONF, div_addr);</div><div class='add'>+	/* Check status register */</div><div class='add'>+	return readl_poll_timeout_atomic(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET, value,</div><div class='add'>+				 value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='add'>+				 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int clk_wzrd_dynamic_ver_all_nolock(struct clk_hw *hw, unsigned long rate,</div><div class='add'>+					   unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	void __iomem *div_addr;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = clk_wzrd_get_divisors_ver(hw, rate, parent_rate);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	writel(0, divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));</div><div class='add'>+</div><div class='add'>+	m = divider-&gt;m;</div><div class='add'>+	edged = m % WZRD_DUTY_CYCLE;</div><div class='add'>+	regh = m / WZRD_DUTY_CYCLE;</div><div class='add'>+	regval1 = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_CLKFBOUT_1));</div><div class='add'>+	regval1 |= WZRD_MULT_PREDIV2;</div><div class='add'>+	if (edged)</div><div class='add'>+		regval1 = regval1 | WZRD_CLKFBOUT_EDGE;</div><div class='add'>+	else</div><div class='add'>+		regval1 = regval1 &amp; ~WZRD_CLKFBOUT_EDGE;</div><div class='add'>+</div><div class='add'>+	writel(regval1, divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_CLKFBOUT_1));</div><div class='add'>+	regval1 = regh | regh &lt;&lt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	writel(regval1, divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_CLKFBOUT_2));</div><div class='add'>+</div><div class='add'>+	value2 = divider-&gt;d;</div><div class='add'>+	edged = value2 % WZRD_DUTY_CYCLE;</div><div class='add'>+	regh = (value2 / WZRD_DUTY_CYCLE);</div><div class='add'>+	regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged);</div><div class='add'>+	writel(regval1, divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_DESKEW_2));</div><div class='add'>+	regval1 = regh | regh &lt;&lt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	writel(regval1, divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));</div><div class='add'>+</div><div class='add'>+	value = divider-&gt;o;</div><div class='add'>+	regh = value / WZRD_O_DIV;</div><div class='add'>+	regval1 = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_CLKOUT0_1));</div><div class='add'>+	regval1 |= WZRD_CLKFBOUT_PREDIV2;</div><div class='add'>+	regval1 = regval1 &amp; ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);</div><div class='add'>+</div><div class='add'>+	if (value % WZRD_O_DIV &gt; 1) {</div><div class='add'>+		edged = 1;</div><div class='add'>+		regval1 |= edged &lt;&lt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p5fedge = value % WZRD_DUTY_CYCLE;</div><div class='add'>+	p5en = value % WZRD_DUTY_CYCLE;</div><div class='add'>+</div><div class='add'>+	regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge);</div><div class='add'>+	writel(regval1, divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							 WZRD_CLKOUT0_1));</div><div class='add'>+	regval = regh | regh &lt;&lt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+	writel(regval, divider-&gt;base + WZRD_CLK_CFG_REG(1,</div><div class='add'>+							WZRD_CLKOUT0_2));</div><div class='add'>+	div_addr = divider-&gt;base + WZRD_DR_INIT_VERSAL_OFFSET;</div><div class='add'>+</div><div class='add'>+	return clk_wzrd_reconfig(divider, div_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 				       unsigned long parent_rate)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='ctx'> 	unsigned long vco_freq, rate_div, clockout0_div;</div><div class='del'>-	u32 reg, pre, value, f;</div><div class='add'>+	void __iomem *div_addr = divider-&gt;base;</div><div class='add'>+	u32 reg, pre, f;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = clk_wzrd_get_divisors(hw, rate, parent_rate);</div><div class='hunk'>@@ -275,35 +518,22 @@ static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |</div><div class='ctx'> 	      FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, f);</div><div class='ctx'> </div><div class='del'>-	writel(reg, divider-&gt;base + WZRD_CLK_CFG_REG(2));</div><div class='add'>+	writel(reg, divider-&gt;base + WZRD_CLK_CFG_REG(0, 2));</div><div class='ctx'> 	/* Set divisor and clear phase offset */</div><div class='ctx'> 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider-&gt;m) |</div><div class='ctx'> 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider-&gt;d);</div><div class='del'>-	writel(reg, divider-&gt;base + WZRD_CLK_CFG_REG(0));</div><div class='del'>-	writel(divider-&gt;o, divider-&gt;base + WZRD_CLK_CFG_REG(2));</div><div class='del'>-	writel(0, divider-&gt;base + WZRD_CLK_CFG_REG(3));</div><div class='del'>-	/* Check status register */</div><div class='del'>-	err = readl_poll_timeout(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET, value,</div><div class='del'>-				 value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='del'>-				 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='del'>-	if (err)</div><div class='del'>-		return -ETIMEDOUT;</div><div class='del'>-</div><div class='del'>-	/* Initiate reconfiguration */</div><div class='del'>-	writel(WZRD_DR_BEGIN_DYNA_RECONF,</div><div class='del'>-	       divider-&gt;base + WZRD_DR_INIT_REG_OFFSET);</div><div class='del'>-</div><div class='del'>-	/* Check status register */</div><div class='del'>-	return readl_poll_timeout(divider-&gt;base + WZRD_DR_STATUS_REG_OFFSET, value,</div><div class='del'>-				 value &amp; WZRD_DR_LOCK_BIT_MASK,</div><div class='del'>-				 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);</div><div class='add'>+	writel(reg, divider-&gt;base + WZRD_CLK_CFG_REG(0, 0));</div><div class='add'>+	writel(divider-&gt;o, divider-&gt;base + WZRD_CLK_CFG_REG(0, 2));</div><div class='add'>+	writel(0, divider-&gt;base + WZRD_CLK_CFG_REG(0, 3));</div><div class='add'>+	div_addr = divider-&gt;base + WZRD_DR_INIT_REG_OFFSET;</div><div class='add'>+	return clk_wzrd_reconfig(divider, div_addr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 				unsigned long parent_rate)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='del'>-	unsigned long flags = 0;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(divider-&gt;lock, flags);</div><div class='hunk'>@@ -315,21 +545,103 @@ static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int clk_wzrd_dynamic_all_ver(struct clk_hw *hw, unsigned long rate,</div><div class='add'>+				    unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(divider-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	ret = clk_wzrd_dynamic_ver_all_nolock(hw, rate, parent_rate);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(divider-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,</div><div class='ctx'> 					      unsigned long parent_rate)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='ctx'> 	u32 m, d, o, div, reg, f;</div><div class='ctx'> </div><div class='del'>-	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(0));</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(0, 0));</div><div class='ctx'> 	d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);</div><div class='ctx'> 	m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg);</div><div class='del'>-	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(2));</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(0, 2));</div><div class='ctx'> 	o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);</div><div class='ctx'> 	f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg);</div><div class='ctx'> </div><div class='ctx'> 	div = DIV_ROUND_CLOSEST(d * (WZRD_FRAC_POINTS * o + f), WZRD_FRAC_POINTS);</div><div class='ctx'> 	return divider_recalc_rate(hw, parent_rate * m, div, divider-&gt;table,</div><div class='add'>+		divider-&gt;flags, divider-&gt;width);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long clk_wzrd_recalc_rate_all_ver(struct clk_hw *hw,</div><div class='add'>+						  unsigned long parent_rate)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);</div><div class='add'>+	u32 edged, div2, p5en, edge, prediv2, all, regl, regh, mult;</div><div class='add'>+	u32 div, reg;</div><div class='add'>+</div><div class='add'>+	edge = !!(readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &amp;</div><div class='add'>+			WZRD_CLKFBOUT_EDGE);</div><div class='add'>+</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));</div><div class='add'>+	regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);</div><div class='add'>+	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);</div><div class='add'>+</div><div class='add'>+	mult = regl + regh + edge;</div><div class='add'>+	if (!mult)</div><div class='add'>+		mult = 1;</div><div class='add'>+</div><div class='add'>+	regl = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &amp;</div><div class='add'>+		     WZRD_CLKFBOUT_FRAC_EN;</div><div class='add'>+	if (regl) {</div><div class='add'>+		regl = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))</div><div class='add'>+				&amp; WZRD_VERSAL_FRAC_MASK;</div><div class='add'>+		mult = mult * WZRD_FRAC_GRADIENT + regl;</div><div class='add'>+		parent_rate = DIV_ROUND_CLOSEST((parent_rate * mult), WZRD_FRAC_GRADIENT);</div><div class='add'>+	} else {</div><div class='add'>+		parent_rate = parent_rate * mult;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* O Calculation */</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));</div><div class='add'>+	edged = FIELD_GET(WZRD_CLKFBOUT_EDGE, reg);</div><div class='add'>+	p5en = FIELD_GET(WZRD_P5EN, reg);</div><div class='add'>+	prediv2 = FIELD_GET(WZRD_CLKOUT0_PREDIV2, reg);</div><div class='add'>+</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));</div><div class='add'>+	/* Low time */</div><div class='add'>+	regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);</div><div class='add'>+	/* High time */</div><div class='add'>+	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);</div><div class='add'>+	all = regh + regl + edged;</div><div class='add'>+	if (!all)</div><div class='add'>+		all = 1;</div><div class='add'>+</div><div class='add'>+	if (prediv2)</div><div class='add'>+		div2 = PREDIV2_MULT * all + p5en;</div><div class='add'>+	else</div><div class='add'>+		div2 = all;</div><div class='add'>+</div><div class='add'>+	/* D calculation */</div><div class='add'>+	edged = !!(readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &amp;</div><div class='add'>+		     WZRD_DIVCLK_EDGE);</div><div class='add'>+	reg = readl(divider-&gt;base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));</div><div class='add'>+	/* Low time */</div><div class='add'>+	regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);</div><div class='add'>+	/* High time */</div><div class='add'>+	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);</div><div class='add'>+	div = regl + regh + edged;</div><div class='add'>+	if (!div)</div><div class='add'>+		div = 1;</div><div class='add'>+</div><div class='add'>+	div = div * div2;</div><div class='add'>+	return divider_recalc_rate(hw, parent_rate, div, divider-&gt;table,</div><div class='ctx'> 			divider-&gt;flags, divider-&gt;width);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -360,6 +672,18 @@ static long clk_wzrd_round_rate_all(struct clk_hw *hw, unsigned long rate,</div><div class='ctx'> 	return rate;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct clk_ops clk_wzrd_ver_divider_ops = {</div><div class='add'>+	.round_rate = clk_wzrd_round_rate,</div><div class='add'>+	.set_rate = clk_wzrd_ver_dynamic_reconfig,</div><div class='add'>+	.recalc_rate = clk_wzrd_recalc_rate_ver,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct clk_ops clk_wzrd_ver_div_all_ops = {</div><div class='add'>+	.round_rate = clk_wzrd_round_rate_all,</div><div class='add'>+	.set_rate = clk_wzrd_dynamic_all_ver,</div><div class='add'>+	.recalc_rate = clk_wzrd_recalc_rate_all_ver,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct clk_ops clk_wzrd_clk_divider_ops = {</div><div class='ctx'> 	.round_rate = clk_wzrd_round_rate,</div><div class='ctx'> 	.set_rate = clk_wzrd_dynamic_reconfig,</div><div class='hunk'>@@ -484,6 +808,53 @@ static struct clk *clk_wzrd_register_divf(struct device *dev,</div><div class='ctx'> 	return hw-&gt;clk;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct clk *clk_wzrd_ver_register_divider(struct device *dev,</div><div class='add'>+						 const char *name,</div><div class='add'>+						 const char *parent_name,</div><div class='add'>+						 unsigned long flags,</div><div class='add'>+						 void __iomem *base,</div><div class='add'>+						 u16 offset,</div><div class='add'>+						 u8 shift, u8 width,</div><div class='add'>+						 u8 clk_divider_flags,</div><div class='add'>+						 u32 div_type,</div><div class='add'>+						 spinlock_t *lock)</div><div class='add'>+{</div><div class='add'>+	struct clk_wzrd_divider *div;</div><div class='add'>+	struct clk_hw *hw;</div><div class='add'>+	struct clk_init_data init;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);</div><div class='add'>+	if (!div)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	init.name = name;</div><div class='add'>+	if (clk_divider_flags &amp; CLK_DIVIDER_READ_ONLY)</div><div class='add'>+		init.ops = &amp;clk_divider_ro_ops;</div><div class='add'>+	else if (div_type == DIV_O)</div><div class='add'>+		init.ops = &amp;clk_wzrd_ver_divider_ops;</div><div class='add'>+	else</div><div class='add'>+		init.ops = &amp;clk_wzrd_ver_div_all_ops;</div><div class='add'>+	init.flags = flags;</div><div class='add'>+	init.parent_names =  &amp;parent_name;</div><div class='add'>+	init.num_parents =  1;</div><div class='add'>+</div><div class='add'>+	div-&gt;base = base;</div><div class='add'>+	div-&gt;offset = offset;</div><div class='add'>+	div-&gt;shift = shift;</div><div class='add'>+	div-&gt;width = width;</div><div class='add'>+	div-&gt;flags = clk_divider_flags;</div><div class='add'>+	div-&gt;lock = lock;</div><div class='add'>+	div-&gt;hw.init = &amp;init;</div><div class='add'>+</div><div class='add'>+	hw = &amp;div-&gt;hw;</div><div class='add'>+	ret = devm_clk_hw_register(dev, hw);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+</div><div class='add'>+	return hw-&gt;clk;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct clk *clk_wzrd_register_divider(struct device *dev,</div><div class='ctx'> 					     const char *name,</div><div class='ctx'> 					     const char *parent_name,</div><div class='hunk'>@@ -588,18 +959,24 @@ static int __maybe_unused clk_wzrd_resume(struct device *dev)</div><div class='ctx'> static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,</div><div class='ctx'> 			 clk_wzrd_resume);</div><div class='ctx'> </div><div class='add'>+static const struct versal_clk_data versal_data = {</div><div class='add'>+	.is_versal	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	int i, ret;</div><div class='add'>+	const char *clkout_name, *clk_name, *clk_mul_name;</div><div class='add'>+	u32 regl, regh, edge, regld, reghd, edged, div;</div><div class='add'>+	struct device_node *np = pdev-&gt;dev.of_node;</div><div class='add'>+	const struct versal_clk_data *data;</div><div class='add'>+	struct clk_wzrd *clk_wzrd;</div><div class='add'>+	unsigned long flags = 0;</div><div class='add'>+	void __iomem *ctrl_reg;</div><div class='ctx'> 	u32 reg, reg_f, mult;</div><div class='add'>+	bool is_versal = false;</div><div class='ctx'> 	unsigned long rate;</div><div class='del'>-	const char *clk_name;</div><div class='del'>-	void __iomem *ctrl_reg;</div><div class='del'>-	struct clk_wzrd *clk_wzrd;</div><div class='del'>-	const char *clkout_name;</div><div class='del'>-	struct device_node *np = pdev-&gt;dev.of_node;</div><div class='ctx'> 	int nr_outputs;</div><div class='del'>-	unsigned long flags = 0;</div><div class='add'>+	int i, ret;</div><div class='ctx'> </div><div class='ctx'> 	clk_wzrd = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*clk_wzrd), GFP_KERNEL);</div><div class='ctx'> 	if (!clk_wzrd)</div><div class='hunk'>@@ -641,6 +1018,10 @@ static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_disable_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	data = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (data)</div><div class='add'>+		is_versal = data-&gt;is_versal;</div><div class='add'>+</div><div class='ctx'> 	ret = of_property_read_u32(np, "xlnx,nr-outputs", &amp;nr_outputs);</div><div class='ctx'> 	if (ret || nr_outputs &gt; WZRD_NUM_OUTPUTS) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -653,26 +1034,61 @@ static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_disable_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (nr_outputs == 1) {</div><div class='del'>-		clk_wzrd-&gt;clkout[0] = clk_wzrd_register_divider</div><div class='add'>+	if (is_versal) {</div><div class='add'>+		if (nr_outputs == 1) {</div><div class='add'>+			clk_wzrd-&gt;clkout[0] = clk_wzrd_ver_register_divider</div><div class='ctx'> 				(&amp;pdev-&gt;dev, clkout_name,</div><div class='ctx'> 				__clk_get_name(clk_wzrd-&gt;clk_in1), 0,</div><div class='del'>-				clk_wzrd-&gt;base, WZRD_CLK_CFG_REG(3),</div><div class='add'>+				clk_wzrd-&gt;base, WZRD_CLK_CFG_REG(is_versal, 3),</div><div class='ctx'> 				WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='ctx'> 				WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='ctx'> 				CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='ctx'> 				DIV_ALL, &amp;clkwzrd_lock);</div><div class='ctx'> </div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	reg = readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(0));</div><div class='del'>-	reg_f = reg &amp; WZRD_CLKFBOUT_FRAC_MASK;</div><div class='del'>-	reg_f =  reg_f &gt;&gt; WZRD_CLKFBOUT_FRAC_SHIFT;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+		/* register multiplier */</div><div class='add'>+		edge = !!(readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 0)) &amp;</div><div class='add'>+				BIT(8));</div><div class='add'>+		regl = (readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 1)) &amp;</div><div class='add'>+			     WZRD_CLKFBOUT_L_MASK) &gt;&gt; WZRD_CLKFBOUT_L_SHIFT;</div><div class='add'>+		regh = (readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 1)) &amp;</div><div class='add'>+			     WZRD_CLKFBOUT_H_MASK) &gt;&gt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+		mult = regl + regh + edge;</div><div class='add'>+		if (!mult)</div><div class='add'>+			mult = 1;</div><div class='add'>+		mult = mult * WZRD_FRAC_GRADIENT;</div><div class='add'>+</div><div class='add'>+		regl = readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 51)) &amp;</div><div class='add'>+			     WZRD_CLKFBOUT_FRAC_EN;</div><div class='add'>+		if (regl) {</div><div class='add'>+			regl = readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 48)) &amp;</div><div class='add'>+				WZRD_VERSAL_FRAC_MASK;</div><div class='add'>+			mult = mult + regl;</div><div class='add'>+		}</div><div class='add'>+		div = 64;</div><div class='add'>+	} else {</div><div class='add'>+		if (nr_outputs == 1) {</div><div class='add'>+			clk_wzrd-&gt;clkout[0] = clk_wzrd_register_divider</div><div class='add'>+				(&amp;pdev-&gt;dev, clkout_name,</div><div class='add'>+				__clk_get_name(clk_wzrd-&gt;clk_in1), 0,</div><div class='add'>+				clk_wzrd-&gt;base, WZRD_CLK_CFG_REG(is_versal, 3),</div><div class='add'>+				WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='add'>+				WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='add'>+				CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='add'>+				DIV_ALL, &amp;clkwzrd_lock);</div><div class='ctx'> </div><div class='del'>-	reg = reg &amp; WZRD_CLKFBOUT_MULT_MASK;</div><div class='del'>-	reg =  reg &gt;&gt; WZRD_CLKFBOUT_MULT_SHIFT;</div><div class='del'>-	mult = (reg * 1000) + reg_f;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+		reg = readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 0));</div><div class='add'>+		reg_f = reg &amp; WZRD_CLKFBOUT_FRAC_MASK;</div><div class='add'>+		reg_f =  reg_f &gt;&gt; WZRD_CLKFBOUT_FRAC_SHIFT;</div><div class='add'>+</div><div class='add'>+		reg = reg &amp; WZRD_CLKFBOUT_MULT_MASK;</div><div class='add'>+		reg =  reg &gt;&gt; WZRD_CLKFBOUT_MULT_SHIFT;</div><div class='add'>+		mult = (reg * 1000) + reg_f;</div><div class='add'>+		div = 1000;</div><div class='add'>+	}</div><div class='ctx'> 	clk_name = devm_kasprintf(&amp;pdev-&gt;dev, GFP_KERNEL, "%s_mul", dev_name(&amp;pdev-&gt;dev));</div><div class='ctx'> 	if (!clk_name) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='hunk'>@@ -681,7 +1097,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> 	clk_wzrd-&gt;clks_internal[wzrd_clk_mul] = clk_register_fixed_factor</div><div class='ctx'> 			(&amp;pdev-&gt;dev, clk_name,</div><div class='ctx'> 			 __clk_get_name(clk_wzrd-&gt;clk_in1),</div><div class='del'>-			0, mult, 1000);</div><div class='add'>+			0, mult, div);</div><div class='ctx'> 	if (IS_ERR(clk_wzrd-&gt;clks_internal[wzrd_clk_mul])) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "unable to register fixed-factor clock\n");</div><div class='ctx'> 		ret = PTR_ERR(clk_wzrd-&gt;clks_internal[wzrd_clk_mul]);</div><div class='hunk'>@@ -694,13 +1110,29 @@ static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_rm_int_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ctrl_reg = clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(0);</div><div class='del'>-	/* register div */</div><div class='del'>-	clk_wzrd-&gt;clks_internal[wzrd_clk_mul_div] = clk_register_divider</div><div class='add'>+	if (is_versal) {</div><div class='add'>+		edged = !!(readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 20)) &amp;</div><div class='add'>+			     BIT(10));</div><div class='add'>+		regld = (readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 21)) &amp;</div><div class='add'>+			     WZRD_CLKFBOUT_L_MASK) &gt;&gt; WZRD_CLKFBOUT_L_SHIFT;</div><div class='add'>+		reghd = (readl(clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 21)) &amp;</div><div class='add'>+		     WZRD_CLKFBOUT_H_MASK) &gt;&gt; WZRD_CLKFBOUT_H_SHIFT;</div><div class='add'>+		div = (regld  + reghd + edged);</div><div class='add'>+		if (!div)</div><div class='add'>+			div = 1;</div><div class='add'>+</div><div class='add'>+		clk_mul_name = __clk_get_name(clk_wzrd-&gt;clks_internal[wzrd_clk_mul]);</div><div class='add'>+		clk_wzrd-&gt;clks_internal[wzrd_clk_mul_div] =</div><div class='add'>+			clk_register_fixed_factor(&amp;pdev-&gt;dev, clk_name,</div><div class='add'>+						  clk_mul_name, 0, 1, div);</div><div class='add'>+	} else {</div><div class='add'>+		ctrl_reg = clk_wzrd-&gt;base + WZRD_CLK_CFG_REG(is_versal, 0);</div><div class='add'>+		clk_wzrd-&gt;clks_internal[wzrd_clk_mul_div] = clk_register_divider</div><div class='ctx'> 			(&amp;pdev-&gt;dev, clk_name,</div><div class='ctx'> 			 __clk_get_name(clk_wzrd-&gt;clks_internal[wzrd_clk_mul]),</div><div class='ctx'> 			flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |</div><div class='ctx'> 			CLK_DIVIDER_ALLOW_ZERO, &amp;clkwzrd_lock);</div><div class='add'>+	}</div><div class='ctx'> 	if (IS_ERR(clk_wzrd-&gt;clks_internal[wzrd_clk_mul_div])) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "unable to register divider clock\n");</div><div class='ctx'> 		ret = PTR_ERR(clk_wzrd-&gt;clks_internal[wzrd_clk_mul_div]);</div><div class='hunk'>@@ -716,24 +1148,35 @@ static int clk_wzrd_probe(struct platform_device *pdev)</div><div class='ctx'> 			goto err_rm_int_clk;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!i)</div><div class='del'>-			clk_wzrd-&gt;clkout[i] = clk_wzrd_register_divf</div><div class='del'>-				(&amp;pdev-&gt;dev, clkout_name,</div><div class='del'>-				clk_name, flags,</div><div class='del'>-				clk_wzrd-&gt;base, (WZRD_CLK_CFG_REG(2) + i * 12),</div><div class='del'>-				WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='del'>-				WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='del'>-				CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='del'>-				DIV_O, &amp;clkwzrd_lock);</div><div class='del'>-		else</div><div class='del'>-			clk_wzrd-&gt;clkout[i] = clk_wzrd_register_divider</div><div class='del'>-				(&amp;pdev-&gt;dev, clkout_name,</div><div class='del'>-				clk_name, 0,</div><div class='del'>-				clk_wzrd-&gt;base, (WZRD_CLK_CFG_REG(2) + i * 12),</div><div class='del'>-				WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='del'>-				WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='del'>-				CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='del'>-				DIV_O, &amp;clkwzrd_lock);</div><div class='add'>+		if (is_versal) {</div><div class='add'>+			clk_wzrd-&gt;clkout[i] = clk_wzrd_ver_register_divider</div><div class='add'>+						(&amp;pdev-&gt;dev,</div><div class='add'>+						 clkout_name, clk_name, 0,</div><div class='add'>+						 clk_wzrd-&gt;base,</div><div class='add'>+						 (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),</div><div class='add'>+						 WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='add'>+						 WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='add'>+						 CLK_DIVIDER_ONE_BASED |</div><div class='add'>+						 CLK_DIVIDER_ALLOW_ZERO,</div><div class='add'>+						 DIV_O, &amp;clkwzrd_lock);</div><div class='add'>+		} else {</div><div class='add'>+			if (!i)</div><div class='add'>+				clk_wzrd-&gt;clkout[i] = clk_wzrd_register_divf</div><div class='add'>+					(&amp;pdev-&gt;dev, clkout_name, clk_name, flags, clk_wzrd-&gt;base,</div><div class='add'>+					(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),</div><div class='add'>+					WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='add'>+					WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='add'>+					CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='add'>+					DIV_O, &amp;clkwzrd_lock);</div><div class='add'>+			else</div><div class='add'>+				clk_wzrd-&gt;clkout[i] = clk_wzrd_register_divider</div><div class='add'>+					(&amp;pdev-&gt;dev, clkout_name, clk_name, 0, clk_wzrd-&gt;base,</div><div class='add'>+					(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),</div><div class='add'>+					WZRD_CLKOUT_DIVIDE_SHIFT,</div><div class='add'>+					WZRD_CLKOUT_DIVIDE_WIDTH,</div><div class='add'>+					CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,</div><div class='add'>+					DIV_O, &amp;clkwzrd_lock);</div><div class='add'>+		}</div><div class='ctx'> 		if (IS_ERR(clk_wzrd-&gt;clkout[i])) {</div><div class='ctx'> 			int j;</div><div class='ctx'> </div><div class='hunk'>@@ -799,9 +1242,10 @@ static void clk_wzrd_remove(struct platform_device *pdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id clk_wzrd_ids[] = {</div><div class='del'>-	{ .compatible = "xlnx,clocking-wizard" },</div><div class='del'>-	{ .compatible = "xlnx,clocking-wizard-v5.2" },</div><div class='del'>-	{ .compatible = "xlnx,clocking-wizard-v6.0" },</div><div class='add'>+	{ .compatible = "xlnx,versal-clk-wizard", .data = &amp;versal_data },</div><div class='add'>+	{ .compatible = "xlnx,clocking-wizard"   },</div><div class='add'>+	{ .compatible = "xlnx,clocking-wizard-v5.2"   },</div><div class='add'>+	{ .compatible = "xlnx,clocking-wizard-v6.0"  },</div><div class='ctx'> 	{ },</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, clk_wzrd_ids);</div><div class='head'>diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c<br/>index 60359333f26d..9b5d3050b742 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/zynqmp/clk-mux-zynqmp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/zynqmp/clk-mux-zynqmp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/zynqmp/clk-mux-zynqmp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/zynqmp/clk-mux-zynqmp.c</a></div><div class='hunk'>@@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)</div><div class='ctx'> static const struct clk_ops zynqmp_clk_mux_ops = {</div><div class='ctx'> 	.get_parent = zynqmp_clk_mux_get_parent,</div><div class='ctx'> 	.set_parent = zynqmp_clk_mux_set_parent,</div><div class='del'>-	.determine_rate = __clk_mux_determine_rate,</div><div class='add'>+	.determine_rate = __clk_mux_determine_rate_closest,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct clk_ops zynqmp_clk_mux_ro_ops = {</div><div class='head'>diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c<br/>index 33a3b2a22659..5a00487ae408 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clk/zynqmp/divider.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clk/zynqmp/divider.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clk/zynqmp/divider.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clk/zynqmp/divider.c</a></div><div class='hunk'>@@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,</div><div class='ctx'> 	return DIV_ROUND_UP_ULL(parent_rate, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void zynqmp_get_divider2_val(struct clk_hw *hw,</div><div class='del'>-				    unsigned long rate,</div><div class='del'>-				    struct zynqmp_clk_divider *divider,</div><div class='del'>-				    u32 *bestdiv)</div><div class='del'>-{</div><div class='del'>-	int div1;</div><div class='del'>-	int div2;</div><div class='del'>-	long error = LONG_MAX;</div><div class='del'>-	unsigned long div1_prate;</div><div class='del'>-	struct clk_hw *div1_parent_hw;</div><div class='del'>-	struct zynqmp_clk_divider *pdivider;</div><div class='del'>-	struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);</div><div class='del'>-</div><div class='del'>-	if (!div2_parent_hw)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	pdivider = to_zynqmp_clk_divider(div2_parent_hw);</div><div class='del'>-	if (!pdivider)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	div1_parent_hw = clk_hw_get_parent(div2_parent_hw);</div><div class='del'>-	if (!div1_parent_hw)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	div1_prate = clk_hw_get_rate(div1_parent_hw);</div><div class='del'>-	*bestdiv = 1;</div><div class='del'>-	for (div1 = 1; div1 &lt;= pdivider-&gt;max_div;) {</div><div class='del'>-		for (div2 = 1; div2 &lt;= divider-&gt;max_div;) {</div><div class='del'>-			long new_error = ((div1_prate / div1) / div2) - rate;</div><div class='del'>-</div><div class='del'>-			if (abs(new_error) &lt; abs(error)) {</div><div class='del'>-				*bestdiv = div2;</div><div class='del'>-				error = new_error;</div><div class='del'>-			}</div><div class='del'>-			if (divider-&gt;flags &amp; CLK_DIVIDER_POWER_OF_TWO)</div><div class='del'>-				div2 = div2 &lt;&lt; 1;</div><div class='del'>-			else</div><div class='del'>-				div2++;</div><div class='del'>-		}</div><div class='del'>-		if (pdivider-&gt;flags &amp; CLK_DIVIDER_POWER_OF_TWO)</div><div class='del'>-			div1 = div1 &lt;&lt; 1;</div><div class='del'>-		else</div><div class='del'>-			div1++;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * zynqmp_clk_divider_round_rate() - Round rate of divider clock</div><div class='ctx'>  * @hw:			handle between common and hardware-specific interfaces</div><div class='hunk'>@@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,</div><div class='ctx'> 	u32 div_type = divider-&gt;div_type;</div><div class='ctx'> 	u32 bestdiv;</div><div class='ctx'> 	int ret;</div><div class='add'>+	u8 width;</div><div class='ctx'> </div><div class='ctx'> 	/* if read only, just return current value */</div><div class='ctx'> 	if (divider-&gt;flags &amp; CLK_DIVIDER_READ_ONLY) {</div><div class='hunk'>@@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,</div><div class='ctx'> 		return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bestdiv = zynqmp_divider_get_val(*prate, rate, divider-&gt;flags);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * In case of two divisors, compute best divider values and return</div><div class='del'>-	 * divider2 value based on compute value. div1 will  be automatically</div><div class='del'>-	 * set to optimum based on required total divider value.</div><div class='del'>-	 */</div><div class='del'>-	if (div_type == TYPE_DIV2 &amp;&amp;</div><div class='del'>-	    (clk_hw_get_flags(hw) &amp; CLK_SET_RATE_PARENT)) {</div><div class='del'>-		zynqmp_get_divider2_val(hw, rate, divider, &amp;bestdiv);</div><div class='del'>-	}</div><div class='add'>+	width = fls(divider-&gt;max_div);</div><div class='ctx'> </div><div class='del'>-	if ((clk_hw_get_flags(hw) &amp; CLK_SET_RATE_PARENT) &amp;&amp; divider-&gt;is_frac)</div><div class='del'>-		bestdiv = rate % *prate ? 1 : bestdiv;</div><div class='add'>+	rate = divider_round_rate(hw, rate, prate, NULL, width, divider-&gt;flags);</div><div class='ctx'> </div><div class='del'>-	bestdiv = min_t(u32, bestdiv, divider-&gt;max_div);</div><div class='del'>-	*prate = rate * bestdiv;</div><div class='add'>+	if (divider-&gt;is_frac &amp;&amp; (clk_hw_get_flags(hw) &amp; CLK_SET_RATE_PARENT) &amp;&amp; (rate % *prate))</div><div class='add'>+		*prate = rate;</div><div class='ctx'> </div><div class='ctx'> 	return rate;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c<br/>index 32daaac9b132..ca7a06489c40 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-cadence-ttc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clocksource/timer-cadence-ttc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-cadence-ttc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-cadence-ttc.c</a></div><div class='hunk'>@@ -69,7 +69,7 @@</div><div class='ctx'>  * @base_addr:	Base address of timer</div><div class='ctx'>  * @freq:	Timer input clock frequency</div><div class='ctx'>  * @clk:	Associated clock source</div><div class='del'>- * @clk_rate_change_nb	Notifier block for clock rate changes</div><div class='add'>+ * @clk_rate_change_nb:	Notifier block for clock rate changes</div><div class='ctx'>  */</div><div class='ctx'> struct ttc_timer {</div><div class='ctx'> 	void __iomem *base_addr;</div><div class='hunk'>@@ -134,7 +134,7 @@ static void ttc_set_interval(struct ttc_timer *timer,</div><div class='ctx'>  * @irq:	IRQ number of the Timer</div><div class='ctx'>  * @dev_id:	void pointer to the ttc_timer instance</div><div class='ctx'>  *</div><div class='del'>- * returns: Always IRQ_HANDLED - success</div><div class='add'>+ * Returns: Always IRQ_HANDLED - success</div><div class='ctx'>  **/</div><div class='ctx'> static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -151,8 +151,9 @@ static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * __ttc_clocksource_read - Reads the timer counter register</div><div class='add'>+ * @cs: &amp;clocksource to read from</div><div class='ctx'>  *</div><div class='del'>- * returns: Current timer counter register value</div><div class='add'>+ * Returns: Current timer counter register value</div><div class='ctx'>  **/</div><div class='ctx'> static u64 __ttc_clocksource_read(struct clocksource *cs)</div><div class='ctx'> {</div><div class='hunk'>@@ -173,7 +174,7 @@ static u64 notrace ttc_sched_clock_read(void)</div><div class='ctx'>  * @cycles:	Timer interval ticks</div><div class='ctx'>  * @evt:	Address of clock event instance</div><div class='ctx'>  *</div><div class='del'>- * returns: Always 0 - success</div><div class='add'>+ * Returns: Always %0 - success</div><div class='ctx'>  **/</div><div class='ctx'> static int ttc_set_next_event(unsigned long cycles,</div><div class='ctx'> 					struct clock_event_device *evt)</div><div class='hunk'>@@ -186,9 +187,12 @@ static int ttc_set_next_event(unsigned long cycles,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer</div><div class='del'>- *</div><div class='add'>+ * ttc_shutdown - Sets the state of timer</div><div class='ctx'>  * @evt:	Address of clock event instance</div><div class='add'>+ *</div><div class='add'>+ * Used for shutdown or oneshot.</div><div class='add'>+ *</div><div class='add'>+ * Returns: Always %0 - success</div><div class='ctx'>  **/</div><div class='ctx'> static int ttc_shutdown(struct clock_event_device *evt)</div><div class='ctx'> {</div><div class='hunk'>@@ -202,6 +206,12 @@ static int ttc_shutdown(struct clock_event_device *evt)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ttc_set_periodic - Sets the state of timer</div><div class='add'>+ * @evt:	Address of clock event instance</div><div class='add'>+ *</div><div class='add'>+ * Returns: Always %0 - success</div><div class='add'>+ */</div><div class='ctx'> static int ttc_set_periodic(struct clock_event_device *evt)</div><div class='ctx'> {</div><div class='ctx'> 	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);</div><div class='head'>diff --git a/drivers/clocksource/timer-ep93xx.c b/drivers/clocksource/timer-ep93xx.c<br/>index bc0ca6e12334..6981ff3ac8a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-ep93xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clocksource/timer-ep93xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-ep93xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-ep93xx.c</a></div><div class='hunk'>@@ -155,9 +155,8 @@ static int __init ep93xx_timer_of_init(struct device_node *np)</div><div class='ctx'> 	ep93xx_tcu = tcu;</div><div class='ctx'> </div><div class='ctx'> 	irq = irq_of_parse_and_map(np, 0);</div><div class='del'>-	if (irq == 0)</div><div class='del'>-		irq = -EINVAL;</div><div class='del'>-	if (irq &lt; 0) {</div><div class='add'>+	if (!irq) {</div><div class='add'>+		ret = -EINVAL;</div><div class='ctx'> 		pr_err("EP93XX Timer Can't parse IRQ %d", irq);</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c<br/>index 57857c0dfba9..e66dcbd66566 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-riscv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clocksource/timer-riscv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-riscv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-riscv.c</a></div><div class='hunk'>@@ -61,12 +61,19 @@ static int riscv_clock_next_event(unsigned long delta,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int riscv_clock_shutdown(struct clock_event_device *evt)</div><div class='add'>+{</div><div class='add'>+	riscv_clock_event_stop();</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static unsigned int riscv_clock_event_irq;</div><div class='ctx'> static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {</div><div class='ctx'> 	.name			= "riscv_timer_clockevent",</div><div class='ctx'> 	.features		= CLOCK_EVT_FEAT_ONESHOT,</div><div class='ctx'> 	.rating			= 100,</div><div class='ctx'> 	.set_next_event		= riscv_clock_next_event,</div><div class='add'>+	.set_state_shutdown	= riscv_clock_shutdown,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c<br/>index 5f60f6bd3386..56acf2617262 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-ti-dm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/clocksource/timer-ti-dm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/clocksource/timer-ti-dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/clocksource/timer-ti-dm.c</a></div><div class='hunk'>@@ -183,7 +183,7 @@ static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg)</div><div class='ctx'>  * dmtimer_write - write timer registers in posted and non-posted mode</div><div class='ctx'>  * @timer:      timer pointer over which write operation is to perform</div><div class='ctx'>  * @reg:        lowest byte holds the register offset</div><div class='del'>- * @value:      data to write into the register</div><div class='add'>+ * @val:        data to write into the register</div><div class='ctx'>  *</div><div class='ctx'>  * The posted mode bit is encoded in reg. Note that in posted mode, the write</div><div class='ctx'>  * pending bit must be checked. Otherwise a write on a register which has a</div><div class='hunk'>@@ -949,7 +949,7 @@ static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie,</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * omap_dm_timer_set_int_disable - disable timer interrupts</div><div class='del'>- * @timer:	pointer to timer handle</div><div class='add'>+ * @cookie:	pointer to timer cookie</div><div class='ctx'>  * @mask:	bit mask of interrupts to be disabled</div><div class='ctx'>  *</div><div class='ctx'>  * Disables the specified timer interrupts for a timer.</div><div class='head'>diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c<br/>index 1548dea15df1..1b481731df96 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/comedi/comedi_fops.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/comedi/comedi_fops.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/comedi/comedi_fops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/comedi/comedi_fops.c</a></div><div class='hunk'>@@ -1714,8 +1714,8 @@ static int __comedi_get_user_chanlist(struct comedi_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	lockdep_assert_held(&amp;dev-&gt;mutex);</div><div class='ctx'> 	cmd-&gt;chanlist = NULL;</div><div class='del'>-	chanlist = memdup_user(user_chanlist,</div><div class='del'>-			       cmd-&gt;chanlist_len * sizeof(unsigned int));</div><div class='add'>+	chanlist = memdup_array_user(user_chanlist,</div><div class='add'>+				     cmd-&gt;chanlist_len, sizeof(unsigned int));</div><div class='ctx'> 	if (IS_ERR(chanlist))</div><div class='ctx'> 		return PTR_ERR(chanlist);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/connector/cn_proc.c b/drivers/connector/cn_proc.c<br/>index 44b19e696176..3d5e6d705fc6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/connector/cn_proc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/connector/cn_proc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/connector/cn_proc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/connector/cn_proc.c</a></div><div class='hunk'>@@ -108,8 +108,9 @@ static inline void send_msg(struct cn_msg *msg)</div><div class='ctx'> 		filter_data[1] = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	cn_netlink_send_mult(msg, msg-&gt;len, 0, CN_IDX_PROC, GFP_NOWAIT,</div><div class='del'>-			     cn_filter, (void *)filter_data);</div><div class='add'>+	if (cn_netlink_send_mult(msg, msg-&gt;len, 0, CN_IDX_PROC, GFP_NOWAIT,</div><div class='add'>+			     cn_filter, (void *)filter_data) == -ESRCH)</div><div class='add'>+		atomic_set(&amp;proc_event_num_listeners, 0);</div><div class='ctx'> </div><div class='ctx'> 	local_unlock(&amp;local_event.lock);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/connector/connector.c b/drivers/connector/connector.c<br/>index 7f7b94f616a6..4028e8eeba82 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/connector/connector.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/connector/connector.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/connector/connector.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/connector/connector.c</a></div><div class='hunk'>@@ -59,9 +59,8 @@ static int cn_already_initialized;</div><div class='ctx'>  * both, or if both are zero then the group is looked up and sent there.</div><div class='ctx'>  */</div><div class='ctx'> int cn_netlink_send_mult(struct cn_msg *msg, u16 len, u32 portid, u32 __group,</div><div class='del'>-	gfp_t gfp_mask,</div><div class='del'>-	int (*filter)(struct sock *dsk, struct sk_buff *skb, void *data),</div><div class='del'>-	void *filter_data)</div><div class='add'>+			 gfp_t gfp_mask, netlink_filter_fn filter,</div><div class='add'>+			 void *filter_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct cn_callback_entry *__cbq;</div><div class='ctx'> 	unsigned int size;</div><div class='head'>diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c<br/>index 9a1e194d5cf8..1f6186475715 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/amd-pstate.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/amd-pstate.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/amd-pstate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/amd-pstate.c</a></div><div class='hunk'>@@ -307,11 +307,11 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)</div><div class='ctx'> 		highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);</div><div class='ctx'> </div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;highest_perf, highest_perf);</div><div class='del'>-</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;max_limit_perf, highest_perf);</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));</div><div class='del'>-</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;min_limit_perf, AMD_CPPC_LOWEST_PERF(cap1));</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -329,11 +329,12 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)</div><div class='ctx'> 		highest_perf = cppc_perf.highest_perf;</div><div class='ctx'> </div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;highest_perf, highest_perf);</div><div class='del'>-</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;max_limit_perf, highest_perf);</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;nominal_perf, cppc_perf.nominal_perf);</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;lowest_nonlinear_perf,</div><div class='ctx'> 		   cppc_perf.lowest_nonlinear_perf);</div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;lowest_perf, cppc_perf.lowest_perf);</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;min_limit_perf, cppc_perf.lowest_perf);</div><div class='ctx'> </div><div class='ctx'> 	if (cppc_state == AMD_PSTATE_ACTIVE)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -432,6 +433,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,</div><div class='ctx'> 	u64 prev = READ_ONCE(cpudata-&gt;cppc_req_cached);</div><div class='ctx'> 	u64 value = prev;</div><div class='ctx'> </div><div class='add'>+	min_perf = clamp_t(unsigned long, min_perf, cpudata-&gt;min_limit_perf,</div><div class='add'>+			cpudata-&gt;max_limit_perf);</div><div class='add'>+	max_perf = clamp_t(unsigned long, max_perf, cpudata-&gt;min_limit_perf,</div><div class='add'>+			cpudata-&gt;max_limit_perf);</div><div class='ctx'> 	des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);</div><div class='ctx'> </div><div class='ctx'> 	if ((cppc_state == AMD_PSTATE_GUIDED) &amp;&amp; (gov_flags &amp; CPUFREQ_GOV_DYNAMIC_SWITCHING)) {</div><div class='hunk'>@@ -470,6 +475,22 @@ static int amd_pstate_verify(struct cpufreq_policy_data *policy)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy)</div><div class='add'>+{</div><div class='add'>+	u32 max_limit_perf, min_limit_perf;</div><div class='add'>+	struct amd_cpudata *cpudata = policy-&gt;driver_data;</div><div class='add'>+</div><div class='add'>+	max_limit_perf = div_u64(policy-&gt;max * cpudata-&gt;highest_perf, cpudata-&gt;max_freq);</div><div class='add'>+	min_limit_perf = div_u64(policy-&gt;min * cpudata-&gt;highest_perf, cpudata-&gt;max_freq);</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;max_limit_perf, max_limit_perf);</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;min_limit_perf, min_limit_perf);</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;max_limit_freq, policy-&gt;max);</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;min_limit_freq, policy-&gt;min);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int amd_pstate_update_freq(struct cpufreq_policy *policy,</div><div class='ctx'> 				  unsigned int target_freq, bool fast_switch)</div><div class='ctx'> {</div><div class='hunk'>@@ -480,6 +501,9 @@ static int amd_pstate_update_freq(struct cpufreq_policy *policy,</div><div class='ctx'> 	if (!cpudata-&gt;max_freq)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='add'>+	if (policy-&gt;min != cpudata-&gt;min_limit_freq || policy-&gt;max != cpudata-&gt;max_limit_freq)</div><div class='add'>+		amd_pstate_update_min_max_limit(policy);</div><div class='add'>+</div><div class='ctx'> 	cap_perf = READ_ONCE(cpudata-&gt;highest_perf);</div><div class='ctx'> 	min_perf = READ_ONCE(cpudata-&gt;lowest_perf);</div><div class='ctx'> 	max_perf = cap_perf;</div><div class='hunk'>@@ -518,7 +542,9 @@ static int amd_pstate_target(struct cpufreq_policy *policy,</div><div class='ctx'> static unsigned int amd_pstate_fast_switch(struct cpufreq_policy *policy,</div><div class='ctx'> 				  unsigned int target_freq)</div><div class='ctx'> {</div><div class='del'>-	return amd_pstate_update_freq(policy, target_freq, true);</div><div class='add'>+	if (!amd_pstate_update_freq(policy, target_freq, true))</div><div class='add'>+		return target_freq;</div><div class='add'>+	return policy-&gt;cur;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amd_pstate_adjust_perf(unsigned int cpu,</div><div class='hunk'>@@ -532,6 +558,10 @@ static void amd_pstate_adjust_perf(unsigned int cpu,</div><div class='ctx'> 	struct amd_cpudata *cpudata = policy-&gt;driver_data;</div><div class='ctx'> 	unsigned int target_freq;</div><div class='ctx'> </div><div class='add'>+	if (policy-&gt;min != cpudata-&gt;min_limit_freq || policy-&gt;max != cpudata-&gt;max_limit_freq)</div><div class='add'>+		amd_pstate_update_min_max_limit(policy);</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> 	cap_perf = READ_ONCE(cpudata-&gt;highest_perf);</div><div class='ctx'> 	lowest_nonlinear_perf = READ_ONCE(cpudata-&gt;lowest_nonlinear_perf);</div><div class='ctx'> 	max_freq = READ_ONCE(cpudata-&gt;max_freq);</div><div class='hunk'>@@ -745,6 +775,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)</div><div class='ctx'> 	/* Initial processor data capability frequencies */</div><div class='ctx'> 	cpudata-&gt;max_freq = max_freq;</div><div class='ctx'> 	cpudata-&gt;min_freq = min_freq;</div><div class='add'>+	cpudata-&gt;max_limit_freq = max_freq;</div><div class='add'>+	cpudata-&gt;min_limit_freq = min_freq;</div><div class='ctx'> 	cpudata-&gt;nominal_freq = nominal_freq;</div><div class='ctx'> 	cpudata-&gt;lowest_nonlinear_freq = lowest_nonlinear_freq;</div><div class='ctx'> </div><div class='hunk'>@@ -850,11 +882,16 @@ static ssize_t show_energy_performance_available_preferences(</div><div class='ctx'> {</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	int offset = 0;</div><div class='add'>+	struct amd_cpudata *cpudata = policy-&gt;driver_data;</div><div class='add'>+</div><div class='add'>+	if (cpudata-&gt;policy == CPUFREQ_POLICY_PERFORMANCE)</div><div class='add'>+		return sysfs_emit_at(buf, offset, "%s\n",</div><div class='add'>+				energy_perf_strings[EPP_INDEX_PERFORMANCE]);</div><div class='ctx'> </div><div class='ctx'> 	while (energy_perf_strings[i] != NULL)</div><div class='ctx'> 		offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]);</div><div class='ctx'> </div><div class='del'>-	sysfs_emit_at(buf, offset, "\n");</div><div class='add'>+	offset += sysfs_emit_at(buf, offset, "\n");</div><div class='ctx'> </div><div class='ctx'> 	return offset;</div><div class='ctx'> }</div><div class='hunk'>@@ -1183,16 +1220,25 @@ static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void amd_pstate_epp_init(unsigned int cpu)</div><div class='add'>+static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy)</div><div class='ctx'> {</div><div class='del'>-	struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);</div><div class='ctx'> 	struct amd_cpudata *cpudata = policy-&gt;driver_data;</div><div class='del'>-	u32 max_perf, min_perf;</div><div class='add'>+	u32 max_perf, min_perf, min_limit_perf, max_limit_perf;</div><div class='ctx'> 	u64 value;</div><div class='ctx'> 	s16 epp;</div><div class='ctx'> </div><div class='ctx'> 	max_perf = READ_ONCE(cpudata-&gt;highest_perf);</div><div class='ctx'> 	min_perf = READ_ONCE(cpudata-&gt;lowest_perf);</div><div class='add'>+	max_limit_perf = div_u64(policy-&gt;max * cpudata-&gt;highest_perf, cpudata-&gt;max_freq);</div><div class='add'>+	min_limit_perf = div_u64(policy-&gt;min * cpudata-&gt;highest_perf, cpudata-&gt;max_freq);</div><div class='add'>+</div><div class='add'>+	max_perf = clamp_t(unsigned long, max_perf, cpudata-&gt;min_limit_perf,</div><div class='add'>+			cpudata-&gt;max_limit_perf);</div><div class='add'>+	min_perf = clamp_t(unsigned long, min_perf, cpudata-&gt;min_limit_perf,</div><div class='add'>+			cpudata-&gt;max_limit_perf);</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;max_limit_perf, max_limit_perf);</div><div class='add'>+	WRITE_ONCE(cpudata-&gt;min_limit_perf, min_limit_perf);</div><div class='ctx'> </div><div class='ctx'> 	value = READ_ONCE(cpudata-&gt;cppc_req_cached);</div><div class='ctx'> </div><div class='hunk'>@@ -1210,9 +1256,6 @@ static void amd_pstate_epp_init(unsigned int cpu)</div><div class='ctx'> 	value &amp;= ~AMD_CPPC_DES_PERF(~0L);</div><div class='ctx'> 	value |= AMD_CPPC_DES_PERF(0);</div><div class='ctx'> </div><div class='del'>-	if (cpudata-&gt;epp_policy == cpudata-&gt;policy)</div><div class='del'>-		goto skip_epp;</div><div class='del'>-</div><div class='ctx'> 	cpudata-&gt;epp_policy = cpudata-&gt;policy;</div><div class='ctx'> </div><div class='ctx'> 	/* Get BIOS pre-defined epp value */</div><div class='hunk'>@@ -1222,7 +1265,7 @@ static void amd_pstate_epp_init(unsigned int cpu)</div><div class='ctx'> 		 * This return value can only be negative for shared_memory</div><div class='ctx'> 		 * systems where EPP register read/write not supported.</div><div class='ctx'> 		 */</div><div class='del'>-		goto skip_epp;</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (cpudata-&gt;policy == CPUFREQ_POLICY_PERFORMANCE)</div><div class='hunk'>@@ -1236,8 +1279,6 @@ static void amd_pstate_epp_init(unsigned int cpu)</div><div class='ctx'> </div><div class='ctx'> 	WRITE_ONCE(cpudata-&gt;cppc_req_cached, value);</div><div class='ctx'> 	amd_pstate_set_epp(cpudata, epp);</div><div class='del'>-skip_epp:</div><div class='del'>-	cpufreq_cpu_put(policy);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)</div><div class='hunk'>@@ -1252,7 +1293,7 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)</div><div class='ctx'> </div><div class='ctx'> 	cpudata-&gt;policy = policy-&gt;policy;</div><div class='ctx'> </div><div class='del'>-	amd_pstate_epp_init(policy-&gt;cpu);</div><div class='add'>+	amd_pstate_epp_update_limit(policy);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/cpufreq/armada-8k-cpufreq.c b/drivers/cpufreq/armada-8k-cpufreq.c<br/>index 8afefdea4d80..ce5a5641b6dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/armada-8k-cpufreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/armada-8k-cpufreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/armada-8k-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/armada-8k-cpufreq.c</a></div><div class='hunk'>@@ -57,7 +57,7 @@ static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk,</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		clk = clk_get(cpu_dev, 0);</div><div class='add'>+		clk = clk_get(cpu_dev, NULL);</div><div class='ctx'> 		if (IS_ERR(clk)) {</div><div class='ctx'> 			pr_warn("Cannot get clock for CPU %d\n", cpu);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -165,7 +165,7 @@ static int __init armada_8k_cpufreq_init(void)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		clk = clk_get(cpu_dev, 0);</div><div class='add'>+		clk = clk_get(cpu_dev, NULL);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(clk)) {</div><div class='ctx'> 			pr_err("Cannot get clock for CPU %d\n", cpu);</div><div class='head'>diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c<br/>index fe08ca419b3d..64420d9cfd1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/cppc_cpufreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/cppc_cpufreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/cppc_cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/cppc_cpufreq.c</a></div><div class='hunk'>@@ -16,7 +16,6 @@</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/cpu.h&gt;</div><div class='ctx'> #include &lt;linux/cpufreq.h&gt;</div><div class='del'>-#include &lt;linux/dmi.h&gt;</div><div class='ctx'> #include &lt;linux/irq_work.h&gt;</div><div class='ctx'> #include &lt;linux/kthread.h&gt;</div><div class='ctx'> #include &lt;linux/time.h&gt;</div><div class='hunk'>@@ -27,12 +26,6 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;acpi/cppc_acpi.h&gt;</div><div class='ctx'> </div><div class='del'>-/* Minimum struct length needed for the DMI processor entry we want */</div><div class='del'>-#define DMI_ENTRY_PROCESSOR_MIN_LENGTH	48</div><div class='del'>-</div><div class='del'>-/* Offset in the DMI processor structure for the max frequency */</div><div class='del'>-#define DMI_PROCESSOR_MAX_SPEED		0x14</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * This list contains information parsed from per CPU ACPI _CPC and _PSD</div><div class='ctx'>  * structures: e.g. the highest and lowest supported performance, capabilities,</div><div class='hunk'>@@ -291,97 +284,9 @@ static inline void cppc_freq_invariance_exit(void)</div><div class='ctx'> }</div><div class='ctx'> #endif /* CONFIG_ACPI_CPPC_CPUFREQ_FIE */</div><div class='ctx'> </div><div class='del'>-/* Callback function used to retrieve the max frequency from DMI */</div><div class='del'>-static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)</div><div class='del'>-{</div><div class='del'>-	const u8 *dmi_data = (const u8 *)dm;</div><div class='del'>-	u16 *mhz = (u16 *)private;</div><div class='del'>-</div><div class='del'>-	if (dm-&gt;type == DMI_ENTRY_PROCESSOR &amp;&amp;</div><div class='del'>-	    dm-&gt;length &gt;= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {</div><div class='del'>-		u16 val = (u16)get_unaligned((const u16 *)</div><div class='del'>-				(dmi_data + DMI_PROCESSOR_MAX_SPEED));</div><div class='del'>-		*mhz = val &gt; *mhz ? val : *mhz;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Look up the max frequency in DMI */</div><div class='del'>-static u64 cppc_get_dmi_max_khz(void)</div><div class='del'>-{</div><div class='del'>-	u16 mhz = 0;</div><div class='del'>-</div><div class='del'>-	dmi_walk(cppc_find_dmi_mhz, &amp;mhz);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Real stupid fallback value, just in case there is no</div><div class='del'>-	 * actual value set.</div><div class='del'>-	 */</div><div class='del'>-	mhz = mhz ? mhz : 1;</div><div class='del'>-</div><div class='del'>-	return (1000 * mhz);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * If CPPC lowest_freq and nominal_freq registers are exposed then we can</div><div class='del'>- * use them to convert perf to freq and vice versa. The conversion is</div><div class='del'>- * extrapolated as an affine function passing by the 2 points:</div><div class='del'>- *  - (Low perf, Low freq)</div><div class='del'>- *  - (Nominal perf, Nominal perf)</div><div class='del'>- */</div><div class='del'>-static unsigned int cppc_cpufreq_perf_to_khz(struct cppc_cpudata *cpu_data,</div><div class='del'>-					     unsigned int perf)</div><div class='del'>-{</div><div class='del'>-	struct cppc_perf_caps *caps = &amp;cpu_data-&gt;perf_caps;</div><div class='del'>-	s64 retval, offset = 0;</div><div class='del'>-	static u64 max_khz;</div><div class='del'>-	u64 mul, div;</div><div class='del'>-</div><div class='del'>-	if (caps-&gt;lowest_freq &amp;&amp; caps-&gt;nominal_freq) {</div><div class='del'>-		mul = caps-&gt;nominal_freq - caps-&gt;lowest_freq;</div><div class='del'>-		div = caps-&gt;nominal_perf - caps-&gt;lowest_perf;</div><div class='del'>-		offset = caps-&gt;nominal_freq - div64_u64(caps-&gt;nominal_perf * mul, div);</div><div class='del'>-	} else {</div><div class='del'>-		if (!max_khz)</div><div class='del'>-			max_khz = cppc_get_dmi_max_khz();</div><div class='del'>-		mul = max_khz;</div><div class='del'>-		div = caps-&gt;highest_perf;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	retval = offset + div64_u64(perf * mul, div);</div><div class='del'>-	if (retval &gt;= 0)</div><div class='del'>-		return retval;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static unsigned int cppc_cpufreq_khz_to_perf(struct cppc_cpudata *cpu_data,</div><div class='del'>-					     unsigned int freq)</div><div class='del'>-{</div><div class='del'>-	struct cppc_perf_caps *caps = &amp;cpu_data-&gt;perf_caps;</div><div class='del'>-	s64 retval, offset = 0;</div><div class='del'>-	static u64 max_khz;</div><div class='del'>-	u64  mul, div;</div><div class='del'>-</div><div class='del'>-	if (caps-&gt;lowest_freq &amp;&amp; caps-&gt;nominal_freq) {</div><div class='del'>-		mul = caps-&gt;nominal_perf - caps-&gt;lowest_perf;</div><div class='del'>-		div = caps-&gt;nominal_freq - caps-&gt;lowest_freq;</div><div class='del'>-		offset = caps-&gt;nominal_perf - div64_u64(caps-&gt;nominal_freq * mul, div);</div><div class='del'>-	} else {</div><div class='del'>-		if (!max_khz)</div><div class='del'>-			max_khz = cppc_get_dmi_max_khz();</div><div class='del'>-		mul = caps-&gt;highest_perf;</div><div class='del'>-		div = max_khz;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	retval = offset + div64_u64(freq * mul, div);</div><div class='del'>-	if (retval &gt;= 0)</div><div class='del'>-		return retval;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,</div><div class='ctx'> 				   unsigned int target_freq,</div><div class='ctx'> 				   unsigned int relation)</div><div class='del'>-</div><div class='ctx'> {</div><div class='ctx'> 	struct cppc_cpudata *cpu_data = policy-&gt;driver_data;</div><div class='ctx'> 	unsigned int cpu = policy-&gt;cpu;</div><div class='hunk'>@@ -389,7 +294,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,</div><div class='ctx'> 	u32 desired_perf;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	desired_perf = cppc_cpufreq_khz_to_perf(cpu_data, target_freq);</div><div class='add'>+	desired_perf = cppc_khz_to_perf(&amp;cpu_data-&gt;perf_caps, target_freq);</div><div class='ctx'> 	/* Return if it is exactly the same perf */</div><div class='ctx'> 	if (desired_perf == cpu_data-&gt;perf_ctrls.desired_perf)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -417,7 +322,7 @@ static unsigned int cppc_cpufreq_fast_switch(struct cpufreq_policy *policy,</div><div class='ctx'> 	u32 desired_perf;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	desired_perf = cppc_cpufreq_khz_to_perf(cpu_data, target_freq);</div><div class='add'>+	desired_perf = cppc_khz_to_perf(&amp;cpu_data-&gt;perf_caps, target_freq);</div><div class='ctx'> 	cpu_data-&gt;perf_ctrls.desired_perf = desired_perf;</div><div class='ctx'> 	ret = cppc_set_perf(cpu, &amp;cpu_data-&gt;perf_ctrls);</div><div class='ctx'> </div><div class='hunk'>@@ -530,7 +435,7 @@ static int cppc_get_cpu_power(struct device *cpu_dev,</div><div class='ctx'> 	min_step = min_cap / CPPC_EM_CAP_STEP;</div><div class='ctx'> 	max_step = max_cap / CPPC_EM_CAP_STEP;</div><div class='ctx'> </div><div class='del'>-	perf_prev = cppc_cpufreq_khz_to_perf(cpu_data, *KHz);</div><div class='add'>+	perf_prev = cppc_khz_to_perf(perf_caps, *KHz);</div><div class='ctx'> 	step = perf_prev / perf_step;</div><div class='ctx'> </div><div class='ctx'> 	if (step &gt; max_step)</div><div class='hunk'>@@ -550,8 +455,8 @@ static int cppc_get_cpu_power(struct device *cpu_dev,</div><div class='ctx'> 			perf = step * perf_step;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	*KHz = cppc_cpufreq_perf_to_khz(cpu_data, perf);</div><div class='del'>-	perf_check = cppc_cpufreq_khz_to_perf(cpu_data, *KHz);</div><div class='add'>+	*KHz = cppc_perf_to_khz(perf_caps, perf);</div><div class='add'>+	perf_check = cppc_khz_to_perf(perf_caps, *KHz);</div><div class='ctx'> 	step_check = perf_check / perf_step;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -561,8 +466,8 @@ static int cppc_get_cpu_power(struct device *cpu_dev,</div><div class='ctx'> 	 */</div><div class='ctx'> 	while ((*KHz == prev_freq) || (step_check != step)) {</div><div class='ctx'> 		perf++;</div><div class='del'>-		*KHz = cppc_cpufreq_perf_to_khz(cpu_data, perf);</div><div class='del'>-		perf_check = cppc_cpufreq_khz_to_perf(cpu_data, *KHz);</div><div class='add'>+		*KHz = cppc_perf_to_khz(perf_caps, perf);</div><div class='add'>+		perf_check = cppc_khz_to_perf(perf_caps, *KHz);</div><div class='ctx'> 		step_check = perf_check / perf_step;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -591,7 +496,7 @@ static int cppc_get_cpu_cost(struct device *cpu_dev, unsigned long KHz,</div><div class='ctx'> 	perf_caps = &amp;cpu_data-&gt;perf_caps;</div><div class='ctx'> 	max_cap = arch_scale_cpu_capacity(cpu_dev-&gt;id);</div><div class='ctx'> </div><div class='del'>-	perf_prev = cppc_cpufreq_khz_to_perf(cpu_data, KHz);</div><div class='add'>+	perf_prev = cppc_khz_to_perf(perf_caps, KHz);</div><div class='ctx'> 	perf_step = CPPC_EM_CAP_STEP * perf_caps-&gt;highest_perf / max_cap;</div><div class='ctx'> 	step = perf_prev / perf_step;</div><div class='ctx'> </div><div class='hunk'>@@ -679,10 +584,6 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu)</div><div class='ctx'> 		goto free_mask;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Convert the lowest and nominal freq from MHz to KHz */</div><div class='del'>-	cpu_data-&gt;perf_caps.lowest_freq *= 1000;</div><div class='del'>-	cpu_data-&gt;perf_caps.nominal_freq *= 1000;</div><div class='del'>-</div><div class='ctx'> 	list_add(&amp;cpu_data-&gt;node, &amp;cpu_data_list);</div><div class='ctx'> </div><div class='ctx'> 	return cpu_data;</div><div class='hunk'>@@ -724,20 +625,16 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)</div><div class='ctx'> 	 * Set min to lowest nonlinear perf to avoid any efficiency penalty (see</div><div class='ctx'> 	 * Section 8.4.7.1.1.5 of ACPI 6.1 spec)</div><div class='ctx'> 	 */</div><div class='del'>-	policy-&gt;min = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-					       caps-&gt;lowest_nonlinear_perf);</div><div class='del'>-	policy-&gt;max = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-					       caps-&gt;nominal_perf);</div><div class='add'>+	policy-&gt;min = cppc_perf_to_khz(caps, caps-&gt;lowest_nonlinear_perf);</div><div class='add'>+	policy-&gt;max = cppc_perf_to_khz(caps, caps-&gt;nominal_perf);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Set cpuinfo.min_freq to Lowest to make the full range of performance</div><div class='ctx'> 	 * available if userspace wants to use any perf between lowest &amp; lowest</div><div class='ctx'> 	 * nonlinear perf</div><div class='ctx'> 	 */</div><div class='del'>-	policy-&gt;cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-							    caps-&gt;lowest_perf);</div><div class='del'>-	policy-&gt;cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-							    caps-&gt;nominal_perf);</div><div class='add'>+	policy-&gt;cpuinfo.min_freq = cppc_perf_to_khz(caps, caps-&gt;lowest_perf);</div><div class='add'>+	policy-&gt;cpuinfo.max_freq = cppc_perf_to_khz(caps, caps-&gt;nominal_perf);</div><div class='ctx'> </div><div class='ctx'> 	policy-&gt;transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu);</div><div class='ctx'> 	policy-&gt;shared_type = cpu_data-&gt;shared_type;</div><div class='hunk'>@@ -773,7 +670,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)</div><div class='ctx'> 		boost_supported = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Set policy-&gt;cur to max now. The governors will adjust later. */</div><div class='del'>-	policy-&gt;cur = cppc_cpufreq_perf_to_khz(cpu_data, caps-&gt;highest_perf);</div><div class='add'>+	policy-&gt;cur = cppc_perf_to_khz(caps, caps-&gt;highest_perf);</div><div class='ctx'> 	cpu_data-&gt;perf_ctrls.desired_perf =  caps-&gt;highest_perf;</div><div class='ctx'> </div><div class='ctx'> 	ret = cppc_set_perf(cpu, &amp;cpu_data-&gt;perf_ctrls);</div><div class='hunk'>@@ -863,7 +760,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpu)</div><div class='ctx'> 	delivered_perf = cppc_perf_from_fbctrs(cpu_data, &amp;fb_ctrs_t0,</div><div class='ctx'> 					       &amp;fb_ctrs_t1);</div><div class='ctx'> </div><div class='del'>-	return cppc_cpufreq_perf_to_khz(cpu_data, delivered_perf);</div><div class='add'>+	return cppc_perf_to_khz(&amp;cpu_data-&gt;perf_caps, delivered_perf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state)</div><div class='hunk'>@@ -878,11 +775,9 @@ static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (state)</div><div class='del'>-		policy-&gt;max = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-						       caps-&gt;highest_perf);</div><div class='add'>+		policy-&gt;max = cppc_perf_to_khz(caps, caps-&gt;highest_perf);</div><div class='ctx'> 	else</div><div class='del'>-		policy-&gt;max = cppc_cpufreq_perf_to_khz(cpu_data,</div><div class='del'>-						       caps-&gt;nominal_perf);</div><div class='add'>+		policy-&gt;max = cppc_perf_to_khz(caps, caps-&gt;nominal_perf);</div><div class='ctx'> 	policy-&gt;cpuinfo.max_freq = policy-&gt;max;</div><div class='ctx'> </div><div class='ctx'> 	ret = freq_qos_update_request(policy-&gt;max_freq_req, policy-&gt;max);</div><div class='hunk'>@@ -937,7 +832,7 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu)</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='del'>-	return cppc_cpufreq_perf_to_khz(cpu_data, desired_perf);</div><div class='add'>+	return cppc_perf_to_khz(&amp;cpu_data-&gt;perf_caps, desired_perf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void cppc_check_hisi_workaround(void)</div><div class='head'>diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c<br/>index 934d35f570b7..44db4f59c4cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/cpufreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/cpufreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/cpufreq.c</a></div><div class='hunk'>@@ -454,7 +454,7 @@ void cpufreq_freq_transition_end(struct cpufreq_policy *policy,</div><div class='ctx'> </div><div class='ctx'> 	arch_set_freq_scale(policy-&gt;related_cpus,</div><div class='ctx'> 			    policy-&gt;cur,</div><div class='del'>-			    policy-&gt;cpuinfo.max_freq);</div><div class='add'>+			    arch_scale_freq_ref(policy-&gt;cpu));</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;policy-&gt;transition_lock);</div><div class='ctx'> 	policy-&gt;transition_ongoing = false;</div><div class='hunk'>@@ -2174,7 +2174,7 @@ unsigned int cpufreq_driver_fast_switch(struct cpufreq_policy *policy,</div><div class='ctx'> </div><div class='ctx'> 	policy-&gt;cur = freq;</div><div class='ctx'> 	arch_set_freq_scale(policy-&gt;related_cpus, freq,</div><div class='del'>-			    policy-&gt;cpuinfo.max_freq);</div><div class='add'>+			    arch_scale_freq_ref(policy-&gt;cpu));</div><div class='ctx'> 	cpufreq_stats_record_transition(policy, freq);</div><div class='ctx'> </div><div class='ctx'> 	if (trace_cpu_frequency_enabled()) {</div><div class='head'>diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c<br/>index 494d044b9e72..33728c242f66 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/imx6q-cpufreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/imx6q-cpufreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/imx6q-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/imx6q-cpufreq.c</a></div><div class='hunk'>@@ -327,7 +327,7 @@ static int imx6ul_opp_check_speed_grading(struct device *dev)</div><div class='ctx'> 			imx6x_disable_freq_in_opp(dev, 696000000);</div><div class='ctx'> </div><div class='ctx'> 	if (of_machine_is_compatible("fsl,imx6ull")) {</div><div class='del'>-		if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)</div><div class='add'>+		if (val &lt; OCOTP_CFG3_6ULL_SPEED_792MHZ)</div><div class='ctx'> 			imx6x_disable_freq_in_opp(dev, 792000000);</div><div class='ctx'> </div><div class='ctx'> 		if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)</div><div class='head'>diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c<br/>index a534a1f7f1ee..2ca70b0b5fdc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/intel_pstate.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/intel_pstate.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/intel_pstate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/intel_pstate.c</a></div><div class='hunk'>@@ -302,7 +302,10 @@ static bool hwp_forced __read_mostly;</div><div class='ctx'> </div><div class='ctx'> static struct cpufreq_driver *intel_pstate_driver __read_mostly;</div><div class='ctx'> </div><div class='del'>-#define HYBRID_SCALING_FACTOR	78741</div><div class='add'>+#define HYBRID_SCALING_FACTOR		78741</div><div class='add'>+#define HYBRID_SCALING_FACTOR_MTL	80000</div><div class='add'>+</div><div class='add'>+static int hybrid_scaling_factor = HYBRID_SCALING_FACTOR;</div><div class='ctx'> </div><div class='ctx'> static inline int core_get_scaling(void)</div><div class='ctx'> {</div><div class='hunk'>@@ -422,7 +425,7 @@ static int intel_pstate_cppc_get_scaling(int cpu)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!ret &amp;&amp; cppc_perf.nominal_perf &amp;&amp; cppc_perf.nominal_freq &amp;&amp;</div><div class='ctx'> 	    cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)</div><div class='del'>-		return HYBRID_SCALING_FACTOR;</div><div class='add'>+		return hybrid_scaling_factor;</div><div class='ctx'> </div><div class='ctx'> 	return core_get_scaling();</div><div class='ctx'> }</div><div class='hunk'>@@ -1692,13 +1695,6 @@ static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)</div><div class='ctx'> 	cpudata-&gt;epp_default = intel_pstate_get_epp(cpudata, 0);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * If this CPU gen doesn't call for change in balance_perf</div><div class='del'>-	 * EPP return.</div><div class='del'>-	 */</div><div class='del'>-	if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='ctx'> 	 * If the EPP is set by firmware, which means that firmware enabled HWP</div><div class='ctx'> 	 * - Is equal or less than 0x80 (default balance_perf EPP)</div><div class='ctx'> 	 * - But less performance oriented than performance EPP</div><div class='hunk'>@@ -1711,6 +1707,13 @@ static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * If this CPU gen doesn't call for change in balance_perf</div><div class='add'>+	 * EPP return.</div><div class='add'>+	 */</div><div class='add'>+	if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Use hard coded value per gen to update the balance_perf</div><div class='ctx'> 	 * and default EPP.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -1968,7 +1971,7 @@ static int hwp_get_cpu_scaling(int cpu)</div><div class='ctx'> 	smp_call_function_single(cpu, hybrid_get_type, &amp;cpu_type, 1);</div><div class='ctx'> 	/* P-cores have a smaller perf level-to-freqency scaling factor. */</div><div class='ctx'> 	if (cpu_type == 0x40)</div><div class='del'>-		return HYBRID_SCALING_FACTOR;</div><div class='add'>+		return hybrid_scaling_factor;</div><div class='ctx'> </div><div class='ctx'> 	/* Use default core scaling for E-cores */</div><div class='ctx'> 	if (cpu_type == 0x20)</div><div class='hunk'>@@ -2406,6 +2409,7 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {</div><div class='ctx'> 	X86_MATCH(ICELAKE_X,		core_funcs),</div><div class='ctx'> 	X86_MATCH(TIGERLAKE,		core_funcs),</div><div class='ctx'> 	X86_MATCH(SAPPHIRERAPIDS_X,	core_funcs),</div><div class='add'>+	X86_MATCH(EMERALDRAPIDS_X,      core_funcs),</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);</div><div class='hunk'>@@ -3398,6 +3402,11 @@ static const struct x86_cpu_id intel_epp_balance_perf[] = {</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {</div><div class='add'>+	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int __init intel_pstate_init(void)</div><div class='ctx'> {</div><div class='ctx'> 	static struct cpudata **_all_cpu_data;</div><div class='hunk'>@@ -3488,9 +3497,16 @@ hwp_cpu_matched:</div><div class='ctx'> </div><div class='ctx'> 	if (hwp_active) {</div><div class='ctx'> 		const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);</div><div class='add'>+		const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);</div><div class='ctx'> </div><div class='ctx'> 		if (id)</div><div class='ctx'> 			epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id-&gt;driver_data;</div><div class='add'>+</div><div class='add'>+		if (hybrid_id) {</div><div class='add'>+			hybrid_scaling_factor = hybrid_id-&gt;driver_data;</div><div class='add'>+			pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;intel_pstate_driver_lock);</div><div class='head'>diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c<br/>index 6355a39418c5..ea05d9d67490 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/qcom-cpufreq-nvmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/qcom-cpufreq-nvmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/qcom-cpufreq-nvmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/qcom-cpufreq-nvmem.c</a></div><div class='hunk'>@@ -23,8 +23,10 @@</div><div class='ctx'> #include &lt;linux/nvmem-consumer.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/pm_domain.h&gt;</div><div class='ctx'> #include &lt;linux/pm_opp.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/soc/qcom/smem.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -55,6 +57,7 @@ struct qcom_cpufreq_match_data {</div><div class='ctx'> </div><div class='ctx'> struct qcom_cpufreq_drv_cpu {</div><div class='ctx'> 	int opp_token;</div><div class='add'>+	struct device **virt_devs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct qcom_cpufreq_drv {</div><div class='hunk'>@@ -424,6 +427,30 @@ static const struct qcom_cpufreq_match_data match_data_ipq8074 = {</div><div class='ctx'> 	.get_version = qcom_cpufreq_ipq8074_name_version,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void qcom_cpufreq_suspend_virt_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)</div><div class='add'>+{</div><div class='add'>+	const char * const *name = drv-&gt;data-&gt;genpd_names;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!drv-&gt;cpus[cpu].virt_devs)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; *name; i++, name++)</div><div class='add'>+		device_set_awake_path(drv-&gt;cpus[cpu].virt_devs[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void qcom_cpufreq_put_virt_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)</div><div class='add'>+{</div><div class='add'>+	const char * const *name = drv-&gt;data-&gt;genpd_names;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!drv-&gt;cpus[cpu].virt_devs)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; *name; i++, name++)</div><div class='add'>+		pm_runtime_put(drv-&gt;cpus[cpu].virt_devs[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int qcom_cpufreq_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_cpufreq_drv *drv;</div><div class='hunk'>@@ -478,6 +505,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)</div><div class='ctx'> 	of_node_put(np);</div><div class='ctx'> </div><div class='ctx'> 	for_each_possible_cpu(cpu) {</div><div class='add'>+		struct device **virt_devs = NULL;</div><div class='ctx'> 		struct dev_pm_opp_config config = {</div><div class='ctx'> 			.supported_hw = NULL,</div><div class='ctx'> 		};</div><div class='hunk'>@@ -498,7 +526,7 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 		if (drv-&gt;data-&gt;genpd_names) {</div><div class='ctx'> 			config.genpd_names = drv-&gt;data-&gt;genpd_names;</div><div class='del'>-			config.virt_devs = NULL;</div><div class='add'>+			config.virt_devs = &amp;virt_devs;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (config.supported_hw || config.genpd_names) {</div><div class='hunk'>@@ -509,6 +537,27 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)</div><div class='ctx'> 				goto free_opp;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (virt_devs) {</div><div class='add'>+			const char * const *name = config.genpd_names;</div><div class='add'>+			int i, j;</div><div class='add'>+</div><div class='add'>+			for (i = 0; *name; i++, name++) {</div><div class='add'>+				ret = pm_runtime_resume_and_get(virt_devs[i]);</div><div class='add'>+				if (ret) {</div><div class='add'>+					dev_err(cpu_dev, "failed to resume %s: %d\n",</div><div class='add'>+						*name, ret);</div><div class='add'>+</div><div class='add'>+					/* Rollback previous PM runtime calls */</div><div class='add'>+					name = config.genpd_names;</div><div class='add'>+					for (j = 0; *name &amp;&amp; j &lt; i; j++, name++)</div><div class='add'>+						pm_runtime_put(virt_devs[j]);</div><div class='add'>+</div><div class='add'>+					goto free_opp;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			drv-&gt;cpus[cpu].virt_devs = virt_devs;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,</div><div class='hunk'>@@ -522,8 +571,10 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)</div><div class='ctx'> 	dev_err(cpu_dev, "Failed to register platform device\n");</div><div class='ctx'> </div><div class='ctx'> free_opp:</div><div class='del'>-	for_each_possible_cpu(cpu)</div><div class='add'>+	for_each_possible_cpu(cpu) {</div><div class='add'>+		qcom_cpufreq_put_virt_devs(drv, cpu);</div><div class='ctx'> 		dev_pm_opp_clear_config(drv-&gt;cpus[cpu].opp_token);</div><div class='add'>+	}</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -534,15 +585,31 @@ static void qcom_cpufreq_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	platform_device_unregister(cpufreq_dt_pdev);</div><div class='ctx'> </div><div class='del'>-	for_each_possible_cpu(cpu)</div><div class='add'>+	for_each_possible_cpu(cpu) {</div><div class='add'>+		qcom_cpufreq_put_virt_devs(drv, cpu);</div><div class='ctx'> 		dev_pm_opp_clear_config(drv-&gt;cpus[cpu].opp_token);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int qcom_cpufreq_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev);</div><div class='add'>+	unsigned int cpu;</div><div class='add'>+</div><div class='add'>+	for_each_possible_cpu(cpu)</div><div class='add'>+		qcom_cpufreq_suspend_virt_devs(drv, cpu);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL);</div><div class='add'>+</div><div class='ctx'> static struct platform_driver qcom_cpufreq_driver = {</div><div class='ctx'> 	.probe = qcom_cpufreq_probe,</div><div class='ctx'> 	.remove_new = qcom_cpufreq_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom-cpufreq-nvmem",</div><div class='add'>+		.pm = pm_sleep_ptr(&amp;qcom_cpufreq_pm_ops),</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c<br/>index c8a7ccc42c16..4ee23f4ebf4a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpufreq/scmi-cpufreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpufreq/scmi-cpufreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpufreq/scmi-cpufreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpufreq/scmi-cpufreq.c</a></div><div class='hunk'>@@ -334,8 +334,11 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_COMMON_CLK</div><div class='ctx'> 	/* dummy clock provider as needed by OPP if clocks property is used */</div><div class='del'>-	if (of_property_present(dev-&gt;of_node, "#clock-cells"))</div><div class='del'>-		devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL);</div><div class='add'>+	if (of_property_present(dev-&gt;of_node, "#clock-cells")) {</div><div class='add'>+		ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			return dev_err_probe(dev, ret, "%s: registering clock provider failed\n", __func__);</div><div class='add'>+	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	ret = cpufreq_register_driver(&amp;scmi_cpufreq_driver);</div><div class='head'>diff --git a/drivers/cpuidle/cpuidle-haltpoll.c b/drivers/cpuidle/cpuidle-haltpoll.c<br/>index e66df22f9695..d8515d5c0853 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cpuidle/cpuidle-haltpoll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cpuidle/cpuidle-haltpoll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cpuidle/cpuidle-haltpoll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cpuidle/cpuidle-haltpoll.c</a></div><div class='hunk'>@@ -25,13 +25,12 @@ MODULE_PARM_DESC(force, "Load unconditionally");</div><div class='ctx'> static struct cpuidle_device __percpu *haltpoll_cpuidle_devices;</div><div class='ctx'> static enum cpuhp_state haltpoll_hp_state;</div><div class='ctx'> </div><div class='del'>-static int default_enter_idle(struct cpuidle_device *dev,</div><div class='del'>-			      struct cpuidle_driver *drv, int index)</div><div class='add'>+static __cpuidle int default_enter_idle(struct cpuidle_device *dev,</div><div class='add'>+					struct cpuidle_driver *drv, int index)</div><div class='ctx'> {</div><div class='del'>-	if (current_clr_polling_and_test()) {</div><div class='del'>-		local_irq_enable();</div><div class='add'>+	if (current_clr_polling_and_test())</div><div class='ctx'> 		return index;</div><div class='del'>-	}</div><div class='add'>+</div><div class='ctx'> 	arch_cpu_idle();</div><div class='ctx'> 	return index;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig<br/>index 79c3bb9c99c3..0991f026cb07 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/Kconfig</a></div><div class='hunk'>@@ -306,6 +306,7 @@ config CRYPTO_DEV_SAHARA</div><div class='ctx'> 	select CRYPTO_SKCIPHER</div><div class='ctx'> 	select CRYPTO_AES</div><div class='ctx'> 	select CRYPTO_ECB</div><div class='add'>+	select CRYPTO_ENGINE</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option enables support for the SAHARA HW crypto accelerator</div><div class='ctx'> 	  found in some Freescale i.MX chips.</div><div class='head'>diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c<br/>index 8d4c42863a62..1262a7773ef3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c</a></div><div class='hunk'>@@ -431,8 +431,8 @@ int sun8i_ce_cipher_init(struct crypto_tfm *tfm)</div><div class='ctx'> 		return PTR_ERR(op-&gt;fallback_tfm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sktfm-&gt;reqsize = sizeof(struct sun8i_cipher_req_ctx) +</div><div class='del'>-			 crypto_skcipher_reqsize(op-&gt;fallback_tfm);</div><div class='add'>+	crypto_skcipher_set_reqsize(sktfm, sizeof(struct sun8i_cipher_req_ctx) +</div><div class='add'>+				    crypto_skcipher_reqsize(op-&gt;fallback_tfm));</div><div class='ctx'> </div><div class='ctx'> 	memcpy(algt-&gt;fbname,</div><div class='ctx'> 	       crypto_tfm_alg_driver_name(crypto_skcipher_tfm(op-&gt;fallback_tfm)),</div><div class='head'>diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c<br/>index 7fa359725ec7..9b9605ce8ee6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-cipher.c</a></div><div class='hunk'>@@ -405,9 +405,8 @@ int sun8i_ss_cipher_init(struct crypto_tfm *tfm)</div><div class='ctx'> 		return PTR_ERR(op-&gt;fallback_tfm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sktfm-&gt;reqsize = sizeof(struct sun8i_cipher_req_ctx) +</div><div class='del'>-			 crypto_skcipher_reqsize(op-&gt;fallback_tfm);</div><div class='del'>-</div><div class='add'>+	crypto_skcipher_set_reqsize(sktfm, sizeof(struct sun8i_cipher_req_ctx) +</div><div class='add'>+				    crypto_skcipher_reqsize(op-&gt;fallback_tfm));</div><div class='ctx'> </div><div class='ctx'> 	memcpy(algt-&gt;fbname,</div><div class='ctx'> 	       crypto_tfm_alg_driver_name(crypto_skcipher_tfm(op-&gt;fallback_tfm)),</div><div class='head'>diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c<br/>index d70b105dcfa1..753f67a36dc5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c</a></div><div class='hunk'>@@ -30,33 +30,16 @@ static int sun8i_ss_hashkey(struct sun8i_ss_hash_tfm_ctx *tfmctx, const u8 *key,</div><div class='ctx'> 			    unsigned int keylen)</div><div class='ctx'> {</div><div class='ctx'> 	struct crypto_shash *xtfm;</div><div class='del'>-	struct shash_desc *sdesc;</div><div class='del'>-	size_t len;</div><div class='del'>-	int ret = 0;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	xtfm = crypto_alloc_shash("sha1", 0, CRYPTO_ALG_NEED_FALLBACK);</div><div class='ctx'> 	if (IS_ERR(xtfm))</div><div class='ctx'> 		return PTR_ERR(xtfm);</div><div class='ctx'> </div><div class='del'>-	len = sizeof(*sdesc) + crypto_shash_descsize(xtfm);</div><div class='del'>-	sdesc = kmalloc(len, GFP_KERNEL);</div><div class='del'>-	if (!sdesc) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto err_hashkey_sdesc;</div><div class='del'>-	}</div><div class='del'>-	sdesc-&gt;tfm = xtfm;</div><div class='del'>-</div><div class='del'>-	ret = crypto_shash_init(sdesc);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(tfmctx-&gt;ss-&gt;dev, "shash init error ret=%d\n", ret);</div><div class='del'>-		goto err_hashkey;</div><div class='del'>-	}</div><div class='del'>-	ret = crypto_shash_finup(sdesc, key, keylen, tfmctx-&gt;key);</div><div class='add'>+	ret = crypto_shash_tfm_digest(xtfm, key, keylen, tfmctx-&gt;key);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		dev_err(tfmctx-&gt;ss-&gt;dev, "shash finup error\n");</div><div class='del'>-err_hashkey:</div><div class='del'>-	kfree(sdesc);</div><div class='del'>-err_hashkey_sdesc:</div><div class='add'>+		dev_err(tfmctx-&gt;ss-&gt;dev, "shash digest error ret=%d\n", ret);</div><div class='add'>+</div><div class='ctx'> 	crypto_free_shash(xtfm);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/amcc/crypto4xx_alg.c b/drivers/crypto/amcc/crypto4xx_alg.c<br/>index ded732242732..e0af611a95d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_alg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/amcc/crypto4xx_alg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_alg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_alg.c</a></div><div class='hunk'>@@ -181,13 +181,6 @@ int crypto4xx_setkey_aes_cbc(struct crypto_skcipher *cipher,</div><div class='ctx'> 				    CRYPTO_FEEDBACK_MODE_NO_FB);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int crypto4xx_setkey_aes_cfb(struct crypto_skcipher *cipher,</div><div class='del'>-			     const u8 *key, unsigned int keylen)</div><div class='del'>-{</div><div class='del'>-	return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_CFB,</div><div class='del'>-				    CRYPTO_FEEDBACK_MODE_128BIT_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int crypto4xx_setkey_aes_ecb(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen)</div><div class='ctx'> {</div><div class='hunk'>@@ -195,13 +188,6 @@ int crypto4xx_setkey_aes_ecb(struct crypto_skcipher *cipher,</div><div class='ctx'> 				    CRYPTO_FEEDBACK_MODE_NO_FB);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int crypto4xx_setkey_aes_ofb(struct crypto_skcipher *cipher,</div><div class='del'>-			     const u8 *key, unsigned int keylen)</div><div class='del'>-{</div><div class='del'>-	return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_OFB,</div><div class='del'>-				    CRYPTO_FEEDBACK_MODE_64BIT_OFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int crypto4xx_setkey_rfc3686(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c<br/>index 8d53372245ad..6006703fb6d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/amcc/crypto4xx_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_core.c</a></div><div class='hunk'>@@ -1211,26 +1211,6 @@ static struct crypto4xx_alg_common crypto4xx_alg[] = {</div><div class='ctx'> 	} },</div><div class='ctx'> 	{ .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {</div><div class='ctx'> 		.base = {</div><div class='del'>-			.cra_name = "cfb(aes)",</div><div class='del'>-			.cra_driver_name = "cfb-aes-ppc4xx",</div><div class='del'>-			.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct crypto4xx_ctx),</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-		.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-		.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-		.ivsize	= AES_IV_SIZE,</div><div class='del'>-		.setkey	= crypto4xx_setkey_aes_cfb,</div><div class='del'>-		.encrypt = crypto4xx_encrypt_iv_stream,</div><div class='del'>-		.decrypt = crypto4xx_decrypt_iv_stream,</div><div class='del'>-		.init = crypto4xx_sk_init,</div><div class='del'>-		.exit = crypto4xx_sk_exit,</div><div class='del'>-	} },</div><div class='del'>-	{ .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {</div><div class='del'>-		.base = {</div><div class='ctx'> 			.cra_name = "ctr(aes)",</div><div class='ctx'> 			.cra_driver_name = "ctr-aes-ppc4xx",</div><div class='ctx'> 			.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,</div><div class='hunk'>@@ -1289,26 +1269,6 @@ static struct crypto4xx_alg_common crypto4xx_alg[] = {</div><div class='ctx'> 		.init = crypto4xx_sk_init,</div><div class='ctx'> 		.exit = crypto4xx_sk_exit,</div><div class='ctx'> 	} },</div><div class='del'>-	{ .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {</div><div class='del'>-		.base = {</div><div class='del'>-			.cra_name = "ofb(aes)",</div><div class='del'>-			.cra_driver_name = "ofb-aes-ppc4xx",</div><div class='del'>-			.cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct crypto4xx_ctx),</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-		.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-		.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-		.ivsize	= AES_IV_SIZE,</div><div class='del'>-		.setkey	= crypto4xx_setkey_aes_ofb,</div><div class='del'>-		.encrypt = crypto4xx_encrypt_iv_stream,</div><div class='del'>-		.decrypt = crypto4xx_decrypt_iv_stream,</div><div class='del'>-		.init = crypto4xx_sk_init,</div><div class='del'>-		.exit = crypto4xx_sk_exit,</div><div class='del'>-	} },</div><div class='ctx'> </div><div class='ctx'> 	/* AEAD */</div><div class='ctx'> 	{ .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {</div><div class='head'>diff --git a/drivers/crypto/amcc/crypto4xx_core.h b/drivers/crypto/amcc/crypto4xx_core.h<br/>index 56c10668c0ab..96355d463b04 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/amcc/crypto4xx_core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/amcc/crypto4xx_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amcc/crypto4xx_core.h</a></div><div class='hunk'>@@ -162,14 +162,10 @@ int crypto4xx_build_pd(struct crypto_async_request *req,</div><div class='ctx'> 		       struct scatterlist *dst_tmp);</div><div class='ctx'> int crypto4xx_setkey_aes_cbc(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen);</div><div class='del'>-int crypto4xx_setkey_aes_cfb(struct crypto_skcipher *cipher,</div><div class='del'>-			     const u8 *key, unsigned int keylen);</div><div class='ctx'> int crypto4xx_setkey_aes_ctr(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen);</div><div class='ctx'> int crypto4xx_setkey_aes_ecb(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen);</div><div class='del'>-int crypto4xx_setkey_aes_ofb(struct crypto_skcipher *cipher,</div><div class='del'>-			     const u8 *key, unsigned int keylen);</div><div class='ctx'> int crypto4xx_setkey_rfc3686(struct crypto_skcipher *cipher,</div><div class='ctx'> 			     const u8 *key, unsigned int keylen);</div><div class='ctx'> int crypto4xx_encrypt_ctr(struct skcipher_request *req);</div><div class='head'>diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/amlogic/amlogic-gxl-cipher.c<br/>index 3308406612fc..29048da6f50a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/amlogic/amlogic-gxl-cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/amlogic/amlogic-gxl-cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/amlogic/amlogic-gxl-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/amlogic/amlogic-gxl-cipher.c</a></div><div class='hunk'>@@ -327,8 +327,8 @@ int meson_cipher_init(struct crypto_tfm *tfm)</div><div class='ctx'> 		return PTR_ERR(op-&gt;fallback_tfm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sktfm-&gt;reqsize = sizeof(struct meson_cipher_req_ctx) +</div><div class='del'>-			 crypto_skcipher_reqsize(op-&gt;fallback_tfm);</div><div class='add'>+	crypto_skcipher_set_reqsize(sktfm, sizeof(struct meson_cipher_req_ctx) +</div><div class='add'>+				    crypto_skcipher_reqsize(op-&gt;fallback_tfm));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig<br/>index db6c5b4cdc40..e93f2f82b418 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/aspeed/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/aspeed/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/aspeed/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/aspeed/Kconfig</a></div><div class='hunk'>@@ -38,14 +38,12 @@ config CRYPTO_DEV_ASPEED_HACE_CRYPTO</div><div class='ctx'> 	select CRYPTO_DES</div><div class='ctx'> 	select CRYPTO_ECB</div><div class='ctx'> 	select CRYPTO_CBC</div><div class='del'>-	select CRYPTO_CFB</div><div class='del'>-	select CRYPTO_OFB</div><div class='ctx'> 	select CRYPTO_CTR</div><div class='ctx'> 	help</div><div class='ctx'> 	  Select here to enable Aspeed Hash &amp; Crypto Engine (HACE)</div><div class='ctx'> 	  crypto driver.</div><div class='ctx'> 	  Supports AES/DES symmetric-key encryption and decryption</div><div class='del'>-	  with ECB/CBC/CFB/OFB/CTR options.</div><div class='add'>+	  with ECB/CBC/CTR options.</div><div class='ctx'> </div><div class='ctx'> config CRYPTO_DEV_ASPEED_ACRY</div><div class='ctx'> 	bool "Enable Aspeed ACRY RSA Engine"</div><div class='head'>diff --git a/drivers/crypto/aspeed/aspeed-hace-crypto.c b/drivers/crypto/aspeed/aspeed-hace-crypto.c<br/>index f0eddb7854e5..a72dfebc53ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/aspeed/aspeed-hace-crypto.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/aspeed/aspeed-hace-crypto.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/aspeed/aspeed-hace-crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/aspeed/aspeed-hace-crypto.c</a></div><div class='hunk'>@@ -473,30 +473,6 @@ static int aspeed_tdes_ctr_encrypt(struct skcipher_request *req)</div><div class='ctx'> 				HACE_CMD_TRIPLE_DES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aspeed_tdes_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB |</div><div class='del'>-				HACE_CMD_TRIPLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_tdes_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB |</div><div class='del'>-				HACE_CMD_TRIPLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_tdes_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB |</div><div class='del'>-				HACE_CMD_TRIPLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_tdes_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB |</div><div class='del'>-				HACE_CMD_TRIPLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int aspeed_tdes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC |</div><div class='hunk'>@@ -533,30 +509,6 @@ static int aspeed_des_ctr_encrypt(struct skcipher_request *req)</div><div class='ctx'> 				HACE_CMD_SINGLE_DES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aspeed_des_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB |</div><div class='del'>-				HACE_CMD_SINGLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_des_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB |</div><div class='del'>-				HACE_CMD_SINGLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_des_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB |</div><div class='del'>-				HACE_CMD_SINGLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_des_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_des_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB |</div><div class='del'>-				HACE_CMD_SINGLE_DES);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int aspeed_des_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return aspeed_des_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC |</div><div class='hunk'>@@ -659,26 +611,6 @@ static int aspeed_aes_ctr_encrypt(struct skcipher_request *req)</div><div class='ctx'> 	return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CTR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aspeed_aes_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_OFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_aes_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_OFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_aes_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int aspeed_aes_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return aspeed_aes_crypt(req, HACE_CMD_ENCRYPT | HACE_CMD_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int aspeed_aes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return aspeed_aes_crypt(req, HACE_CMD_DECRYPT | HACE_CMD_CBC);</div><div class='hunk'>@@ -792,60 +724,6 @@ static struct aspeed_hace_alg aspeed_crypto_algs[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= AES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize	= AES_MAX_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_aes_setkey,</div><div class='del'>-			.encrypt	= aspeed_aes_cfb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_aes_cfb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "cfb(aes)",</div><div class='del'>-				.cra_driver_name	= "aspeed-cfb-aes",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= 1,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= AES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize	= AES_MAX_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_aes_setkey,</div><div class='del'>-			.encrypt	= aspeed_aes_ofb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_aes_ofb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "ofb(aes)",</div><div class='del'>-				.cra_driver_name	= "aspeed-ofb-aes",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= 1,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='ctx'> 			.min_keysize	= DES_KEY_SIZE,</div><div class='ctx'> 			.max_keysize	= DES_KEY_SIZE,</div><div class='ctx'> 			.setkey		= aspeed_des_setkey,</div><div class='hunk'>@@ -899,60 +777,6 @@ static struct aspeed_hace_alg aspeed_crypto_algs[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= DES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.max_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_des_setkey,</div><div class='del'>-			.encrypt	= aspeed_des_cfb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_des_cfb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "cfb(des)",</div><div class='del'>-				.cra_driver_name	= "aspeed-cfb-des",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= DES_BLOCK_SIZE,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= DES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.max_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_des_setkey,</div><div class='del'>-			.encrypt	= aspeed_des_ofb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_des_ofb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "ofb(des)",</div><div class='del'>-				.cra_driver_name	= "aspeed-ofb-des",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= DES_BLOCK_SIZE,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='ctx'> 			.min_keysize	= DES3_EDE_KEY_SIZE,</div><div class='ctx'> 			.max_keysize	= DES3_EDE_KEY_SIZE,</div><div class='ctx'> 			.setkey		= aspeed_des_setkey,</div><div class='hunk'>@@ -1004,60 +828,6 @@ static struct aspeed_hace_alg aspeed_crypto_algs[] = {</div><div class='ctx'> 			.do_one_request = aspeed_crypto_do_request,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= DES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= DES3_EDE_KEY_SIZE,</div><div class='del'>-			.max_keysize	= DES3_EDE_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_des_setkey,</div><div class='del'>-			.encrypt	= aspeed_tdes_cfb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_tdes_cfb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "cfb(des3_ede)",</div><div class='del'>-				.cra_driver_name	= "aspeed-cfb-tdes",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= DES_BLOCK_SIZE,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg.skcipher.base = {</div><div class='del'>-			.ivsize		= DES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize	= DES3_EDE_KEY_SIZE,</div><div class='del'>-			.max_keysize	= DES3_EDE_KEY_SIZE,</div><div class='del'>-			.setkey		= aspeed_des_setkey,</div><div class='del'>-			.encrypt	= aspeed_tdes_ofb_encrypt,</div><div class='del'>-			.decrypt	= aspeed_tdes_ofb_decrypt,</div><div class='del'>-			.init		= aspeed_crypto_cra_init,</div><div class='del'>-			.exit		= aspeed_crypto_cra_exit,</div><div class='del'>-			.base = {</div><div class='del'>-				.cra_name		= "ofb(des3_ede)",</div><div class='del'>-				.cra_driver_name	= "aspeed-ofb-tdes",</div><div class='del'>-				.cra_priority		= 300,</div><div class='del'>-				.cra_flags		= CRYPTO_ALG_KERN_DRIVER_ONLY |</div><div class='del'>-							  CRYPTO_ALG_ASYNC |</div><div class='del'>-							  CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-				.cra_blocksize		= DES_BLOCK_SIZE,</div><div class='del'>-				.cra_ctxsize		= sizeof(struct aspeed_cipher_ctx),</div><div class='del'>-				.cra_alignmask		= 0x0f,</div><div class='del'>-				.cra_module		= THIS_MODULE,</div><div class='del'>-			}</div><div class='del'>-		},</div><div class='del'>-		.alg.skcipher.op = {</div><div class='del'>-			.do_one_request = aspeed_crypto_do_request,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct aspeed_hace_alg aspeed_crypto_algs_g6[] = {</div><div class='head'>diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c<br/>index d1d93e897892..8bd64fc37e75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/atmel-aes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/atmel-aes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/atmel-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/atmel-aes.c</a></div><div class='hunk'>@@ -46,11 +46,6 @@</div><div class='ctx'> #define ATMEL_AES_BUFFER_ORDER	2</div><div class='ctx'> #define ATMEL_AES_BUFFER_SIZE	(PAGE_SIZE &lt;&lt; ATMEL_AES_BUFFER_ORDER)</div><div class='ctx'> </div><div class='del'>-#define CFB8_BLOCK_SIZE		1</div><div class='del'>-#define CFB16_BLOCK_SIZE	2</div><div class='del'>-#define CFB32_BLOCK_SIZE	4</div><div class='del'>-#define CFB64_BLOCK_SIZE	8</div><div class='del'>-</div><div class='ctx'> #define SIZE_IN_WORDS(x)	((x) &gt;&gt; 2)</div><div class='ctx'> </div><div class='ctx'> /* AES flags */</div><div class='hunk'>@@ -60,12 +55,6 @@</div><div class='ctx'> #define AES_FLAGS_OPMODE_MASK	(AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)</div><div class='ctx'> #define AES_FLAGS_ECB		AES_MR_OPMOD_ECB</div><div class='ctx'> #define AES_FLAGS_CBC		AES_MR_OPMOD_CBC</div><div class='del'>-#define AES_FLAGS_OFB		AES_MR_OPMOD_OFB</div><div class='del'>-#define AES_FLAGS_CFB128	(AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)</div><div class='del'>-#define AES_FLAGS_CFB64		(AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)</div><div class='del'>-#define AES_FLAGS_CFB32		(AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)</div><div class='del'>-#define AES_FLAGS_CFB16		(AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)</div><div class='del'>-#define AES_FLAGS_CFB8		(AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)</div><div class='ctx'> #define AES_FLAGS_CTR		AES_MR_OPMOD_CTR</div><div class='ctx'> #define AES_FLAGS_GCM		AES_MR_OPMOD_GCM</div><div class='ctx'> #define AES_FLAGS_XTS		AES_MR_OPMOD_XTS</div><div class='hunk'>@@ -87,7 +76,6 @@</div><div class='ctx'> </div><div class='ctx'> struct atmel_aes_caps {</div><div class='ctx'> 	bool			has_dualbuff;</div><div class='del'>-	bool			has_cfb64;</div><div class='ctx'> 	bool			has_gcm;</div><div class='ctx'> 	bool			has_xts;</div><div class='ctx'> 	bool			has_authenc;</div><div class='hunk'>@@ -860,22 +848,6 @@ static int atmel_aes_dma_start(struct atmel_aes_dev *dd,</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	switch (dd-&gt;ctx-&gt;block_size) {</div><div class='del'>-	case CFB8_BLOCK_SIZE:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;</div><div class='del'>-		maxburst = 1;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case CFB16_BLOCK_SIZE:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;</div><div class='del'>-		maxburst = 1;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case CFB32_BLOCK_SIZE:</div><div class='del'>-	case CFB64_BLOCK_SIZE:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;</div><div class='del'>-		maxburst = 1;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='ctx'> 	case AES_BLOCK_SIZE:</div><div class='ctx'> 		addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;</div><div class='ctx'> 		maxburst = dd-&gt;caps.max_burst_size;</div><div class='hunk'>@@ -1103,7 +1075,7 @@ static int atmel_aes_crypt(struct skcipher_request *req, unsigned long mode)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * ECB, CBC, CFB, OFB or CTR mode require the plaintext and ciphertext</div><div class='add'>+	 * ECB, CBC or CTR mode require the plaintext and ciphertext</div><div class='ctx'> 	 * to have a positve integer length.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!req-&gt;cryptlen &amp;&amp; opmode != AES_FLAGS_XTS)</div><div class='hunk'>@@ -1113,27 +1085,7 @@ static int atmel_aes_crypt(struct skcipher_request *req, unsigned long mode)</div><div class='ctx'> 	    !IS_ALIGNED(req-&gt;cryptlen, crypto_skcipher_blocksize(skcipher)))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	switch (mode &amp; AES_FLAGS_OPMODE_MASK) {</div><div class='del'>-	case AES_FLAGS_CFB8:</div><div class='del'>-		ctx-&gt;block_size = CFB8_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case AES_FLAGS_CFB16:</div><div class='del'>-		ctx-&gt;block_size = CFB16_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case AES_FLAGS_CFB32:</div><div class='del'>-		ctx-&gt;block_size = CFB32_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case AES_FLAGS_CFB64:</div><div class='del'>-		ctx-&gt;block_size = CFB64_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		ctx-&gt;block_size = AES_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	ctx-&gt;block_size = AES_BLOCK_SIZE;</div><div class='ctx'> 	ctx-&gt;is_aead = false;</div><div class='ctx'> </div><div class='ctx'> 	rctx = skcipher_request_ctx(req);</div><div class='hunk'>@@ -1188,66 +1140,6 @@ static int atmel_aes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> 	return atmel_aes_crypt(req, AES_FLAGS_CBC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int atmel_aes_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_OFB | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_OFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB128);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb64_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb64_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB64);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb32_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb32_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB32);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb16_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb16_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB16);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb8_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_aes_cfb8_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_aes_crypt(req, AES_FLAGS_CFB8);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int atmel_aes_ctr_encrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return atmel_aes_crypt(req, AES_FLAGS_CTR | AES_FLAGS_ENCRYPT);</div><div class='hunk'>@@ -1319,76 +1211,6 @@ static struct skcipher_alg aes_algs[] = {</div><div class='ctx'> 	.ivsize			= AES_BLOCK_SIZE,</div><div class='ctx'> },</div><div class='ctx'> {</div><div class='del'>-	.base.cra_name		= "ofb(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-ofb-aes",</div><div class='del'>-	.base.cra_blocksize	= 1,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_ofb_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_ofb_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb-aes",</div><div class='del'>-	.base.cra_blocksize	= 1,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_cfb_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_cfb_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb32(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb32-aes",</div><div class='del'>-	.base.cra_blocksize	= CFB32_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_cfb32_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_cfb32_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb16(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb16-aes",</div><div class='del'>-	.base.cra_blocksize	= CFB16_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_cfb16_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_cfb16_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb8(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb8-aes",</div><div class='del'>-	.base.cra_blocksize	= CFB8_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_cfb8_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_cfb8_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='del'>-{</div><div class='ctx'> 	.base.cra_name		= "ctr(aes)",</div><div class='ctx'> 	.base.cra_driver_name	= "atmel-ctr-aes",</div><div class='ctx'> 	.base.cra_blocksize	= 1,</div><div class='hunk'>@@ -1404,21 +1226,6 @@ static struct skcipher_alg aes_algs[] = {</div><div class='ctx'> },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct skcipher_alg aes_cfb64_alg = {</div><div class='del'>-	.base.cra_name		= "cfb64(aes)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb64-aes",</div><div class='del'>-	.base.cra_blocksize	= CFB64_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct atmel_aes_ctx),</div><div class='del'>-</div><div class='del'>-	.init			= atmel_aes_init_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_aes_setkey,</div><div class='del'>-	.encrypt		= atmel_aes_cfb64_encrypt,</div><div class='del'>-	.decrypt		= atmel_aes_cfb64_decrypt,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> </div><div class='ctx'> /* gcm aead functions */</div><div class='ctx'> </div><div class='hunk'>@@ -2407,9 +2214,6 @@ static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)</div><div class='ctx'> 	if (dd-&gt;caps.has_gcm)</div><div class='ctx'> 		crypto_unregister_aead(&amp;aes_gcm_alg);</div><div class='ctx'> </div><div class='del'>-	if (dd-&gt;caps.has_cfb64)</div><div class='del'>-		crypto_unregister_skcipher(&amp;aes_cfb64_alg);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(aes_algs); i++)</div><div class='ctx'> 		crypto_unregister_skcipher(&amp;aes_algs[i]);</div><div class='ctx'> }</div><div class='hunk'>@@ -2434,14 +2238,6 @@ static int atmel_aes_register_algs(struct atmel_aes_dev *dd)</div><div class='ctx'> 			goto err_aes_algs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dd-&gt;caps.has_cfb64) {</div><div class='del'>-		atmel_aes_crypto_alg_init(&amp;aes_cfb64_alg.base);</div><div class='del'>-</div><div class='del'>-		err = crypto_register_skcipher(&amp;aes_cfb64_alg);</div><div class='del'>-		if (err)</div><div class='del'>-			goto err_aes_cfb64_alg;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (dd-&gt;caps.has_gcm) {</div><div class='ctx'> 		atmel_aes_crypto_alg_init(&amp;aes_gcm_alg.base);</div><div class='ctx'> </div><div class='hunk'>@@ -2482,8 +2278,6 @@ err_aes_authenc_alg:</div><div class='ctx'> err_aes_xts_alg:</div><div class='ctx'> 	crypto_unregister_aead(&amp;aes_gcm_alg);</div><div class='ctx'> err_aes_gcm_alg:</div><div class='del'>-	crypto_unregister_skcipher(&amp;aes_cfb64_alg);</div><div class='del'>-err_aes_cfb64_alg:</div><div class='ctx'> 	i = ARRAY_SIZE(aes_algs);</div><div class='ctx'> err_aes_algs:</div><div class='ctx'> 	for (j = 0; j &lt; i; j++)</div><div class='hunk'>@@ -2495,7 +2289,6 @@ err_aes_algs:</div><div class='ctx'> static void atmel_aes_get_cap(struct atmel_aes_dev *dd)</div><div class='ctx'> {</div><div class='ctx'> 	dd-&gt;caps.has_dualbuff = 0;</div><div class='del'>-	dd-&gt;caps.has_cfb64 = 0;</div><div class='ctx'> 	dd-&gt;caps.has_gcm = 0;</div><div class='ctx'> 	dd-&gt;caps.has_xts = 0;</div><div class='ctx'> 	dd-&gt;caps.has_authenc = 0;</div><div class='hunk'>@@ -2507,7 +2300,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)</div><div class='ctx'> 	case 0x600:</div><div class='ctx'> 	case 0x500:</div><div class='ctx'> 		dd-&gt;caps.has_dualbuff = 1;</div><div class='del'>-		dd-&gt;caps.has_cfb64 = 1;</div><div class='ctx'> 		dd-&gt;caps.has_gcm = 1;</div><div class='ctx'> 		dd-&gt;caps.has_xts = 1;</div><div class='ctx'> 		dd-&gt;caps.has_authenc = 1;</div><div class='hunk'>@@ -2515,13 +2307,11 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 0x200:</div><div class='ctx'> 		dd-&gt;caps.has_dualbuff = 1;</div><div class='del'>-		dd-&gt;caps.has_cfb64 = 1;</div><div class='ctx'> 		dd-&gt;caps.has_gcm = 1;</div><div class='ctx'> 		dd-&gt;caps.max_burst_size = 4;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 0x130:</div><div class='ctx'> 		dd-&gt;caps.has_dualbuff = 1;</div><div class='del'>-		dd-&gt;caps.has_cfb64 = 1;</div><div class='ctx'> 		dd-&gt;caps.max_burst_size = 4;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 0x120:</div><div class='head'>diff --git a/drivers/crypto/atmel-tdes.c b/drivers/crypto/atmel-tdes.c<br/>index 27b7000e25bc..dcc2380a5889 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/atmel-tdes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/atmel-tdes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/atmel-tdes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/atmel-tdes.c</a></div><div class='hunk'>@@ -45,11 +45,6 @@</div><div class='ctx'> #define TDES_FLAGS_OPMODE_MASK	(TDES_MR_OPMOD_MASK | TDES_MR_CFBS_MASK)</div><div class='ctx'> #define TDES_FLAGS_ECB		TDES_MR_OPMOD_ECB</div><div class='ctx'> #define TDES_FLAGS_CBC		TDES_MR_OPMOD_CBC</div><div class='del'>-#define TDES_FLAGS_OFB		TDES_MR_OPMOD_OFB</div><div class='del'>-#define TDES_FLAGS_CFB64	(TDES_MR_OPMOD_CFB | TDES_MR_CFBS_64b)</div><div class='del'>-#define TDES_FLAGS_CFB32	(TDES_MR_OPMOD_CFB | TDES_MR_CFBS_32b)</div><div class='del'>-#define TDES_FLAGS_CFB16	(TDES_MR_OPMOD_CFB | TDES_MR_CFBS_16b)</div><div class='del'>-#define TDES_FLAGS_CFB8		(TDES_MR_OPMOD_CFB | TDES_MR_CFBS_8b)</div><div class='ctx'> </div><div class='ctx'> #define TDES_FLAGS_MODE_MASK	(TDES_FLAGS_OPMODE_MASK | TDES_FLAGS_ENCRYPT)</div><div class='ctx'> </div><div class='hunk'>@@ -60,13 +55,8 @@</div><div class='ctx'> </div><div class='ctx'> #define ATMEL_TDES_QUEUE_LENGTH	50</div><div class='ctx'> </div><div class='del'>-#define CFB8_BLOCK_SIZE		1</div><div class='del'>-#define CFB16_BLOCK_SIZE	2</div><div class='del'>-#define CFB32_BLOCK_SIZE	4</div><div class='del'>-</div><div class='ctx'> struct atmel_tdes_caps {</div><div class='ctx'> 	bool	has_dma;</div><div class='del'>-	u32		has_cfb_3keys;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct atmel_tdes_dev;</div><div class='hunk'>@@ -376,7 +366,6 @@ static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,</div><div class='ctx'> 				dma_addr_t dma_addr_in,</div><div class='ctx'> 				dma_addr_t dma_addr_out, int length)</div><div class='ctx'> {</div><div class='del'>-	struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd-&gt;req);</div><div class='ctx'> 	int len32;</div><div class='ctx'> </div><div class='ctx'> 	dd-&gt;dma_size = length;</div><div class='hunk'>@@ -386,19 +375,7 @@ static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,</div><div class='ctx'> 					   DMA_TO_DEVICE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	switch (rctx-&gt;mode &amp; TDES_FLAGS_OPMODE_MASK) {</div><div class='del'>-	case TDES_FLAGS_CFB8:</div><div class='del'>-		len32 = DIV_ROUND_UP(length, sizeof(u8));</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case TDES_FLAGS_CFB16:</div><div class='del'>-		len32 = DIV_ROUND_UP(length, sizeof(u16));</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		len32 = DIV_ROUND_UP(length, sizeof(u32));</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	len32 = DIV_ROUND_UP(length, sizeof(u32));</div><div class='ctx'> </div><div class='ctx'> 	atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);</div><div class='ctx'> 	atmel_tdes_write(dd, TDES_TPR, dma_addr_in);</div><div class='hunk'>@@ -419,7 +396,6 @@ static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,</div><div class='ctx'> 				dma_addr_t dma_addr_in,</div><div class='ctx'> 				dma_addr_t dma_addr_out, int length)</div><div class='ctx'> {</div><div class='del'>-	struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd-&gt;req);</div><div class='ctx'> 	struct scatterlist sg[2];</div><div class='ctx'> 	struct dma_async_tx_descriptor	*in_desc, *out_desc;</div><div class='ctx'> 	enum dma_slave_buswidth addr_width;</div><div class='hunk'>@@ -431,19 +407,7 @@ static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,</div><div class='ctx'> 					   DMA_TO_DEVICE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	switch (rctx-&gt;mode &amp; TDES_FLAGS_OPMODE_MASK) {</div><div class='del'>-	case TDES_FLAGS_CFB8:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case TDES_FLAGS_CFB16:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='add'>+	addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;</div><div class='ctx'> </div><div class='ctx'> 	dd-&gt;dma_lch_in.dma_conf.dst_addr_width = addr_width;</div><div class='ctx'> 	dd-&gt;dma_lch_out.dma_conf.src_addr_width = addr_width;</div><div class='hunk'>@@ -680,39 +644,11 @@ static int atmel_tdes_crypt(struct skcipher_request *req, unsigned long mode)</div><div class='ctx'> 	if (!req-&gt;cryptlen)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	switch (mode &amp; TDES_FLAGS_OPMODE_MASK) {</div><div class='del'>-	case TDES_FLAGS_CFB8:</div><div class='del'>-		if (!IS_ALIGNED(req-&gt;cryptlen, CFB8_BLOCK_SIZE)) {</div><div class='del'>-			dev_dbg(dev, "request size is not exact amount of CFB8 blocks\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		ctx-&gt;block_size = CFB8_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case TDES_FLAGS_CFB16:</div><div class='del'>-		if (!IS_ALIGNED(req-&gt;cryptlen, CFB16_BLOCK_SIZE)) {</div><div class='del'>-			dev_dbg(dev, "request size is not exact amount of CFB16 blocks\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		ctx-&gt;block_size = CFB16_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case TDES_FLAGS_CFB32:</div><div class='del'>-		if (!IS_ALIGNED(req-&gt;cryptlen, CFB32_BLOCK_SIZE)) {</div><div class='del'>-			dev_dbg(dev, "request size is not exact amount of CFB32 blocks\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		ctx-&gt;block_size = CFB32_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		if (!IS_ALIGNED(req-&gt;cryptlen, DES_BLOCK_SIZE)) {</div><div class='del'>-			dev_dbg(dev, "request size is not exact amount of DES blocks\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		ctx-&gt;block_size = DES_BLOCK_SIZE;</div><div class='del'>-		break;</div><div class='add'>+	if (!IS_ALIGNED(req-&gt;cryptlen, DES_BLOCK_SIZE)) {</div><div class='add'>+		dev_dbg(dev, "request size is not exact amount of DES blocks\n");</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='add'>+	ctx-&gt;block_size = DES_BLOCK_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	rctx-&gt;mode = mode;</div><div class='ctx'> </div><div class='hunk'>@@ -832,55 +768,6 @@ static int atmel_tdes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return atmel_tdes_crypt(req, TDES_FLAGS_CBC);</div><div class='ctx'> }</div><div class='del'>-static int atmel_tdes_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB64 | TDES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB64);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb8_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB8 | TDES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb8_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB8);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb16_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB16 | TDES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb16_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB16);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb32_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB32 | TDES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_cfb32_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_CFB32);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_OFB | TDES_FLAGS_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_tdes_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return atmel_tdes_crypt(req, TDES_FLAGS_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> static int atmel_tdes_init_tfm(struct crypto_skcipher *tfm)</div><div class='ctx'> {</div><div class='hunk'>@@ -932,71 +819,6 @@ static struct skcipher_alg tdes_algs[] = {</div><div class='ctx'> 	.decrypt		= atmel_tdes_cbc_decrypt,</div><div class='ctx'> },</div><div class='ctx'> {</div><div class='del'>-	.base.cra_name		= "cfb(des)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb-des",</div><div class='del'>-	.base.cra_blocksize	= DES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_alignmask	= 0x7,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= atmel_des_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_cfb_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_cfb_decrypt,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb8(des)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb8-des",</div><div class='del'>-	.base.cra_blocksize	= CFB8_BLOCK_SIZE,</div><div class='del'>-	.base.cra_alignmask	= 0,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= atmel_des_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_cfb8_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_cfb8_decrypt,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb16(des)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb16-des",</div><div class='del'>-	.base.cra_blocksize	= CFB16_BLOCK_SIZE,</div><div class='del'>-	.base.cra_alignmask	= 0x1,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= atmel_des_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_cfb16_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_cfb16_decrypt,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "cfb32(des)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-cfb32-des",</div><div class='del'>-	.base.cra_blocksize	= CFB32_BLOCK_SIZE,</div><div class='del'>-	.base.cra_alignmask	= 0x3,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= atmel_des_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_cfb32_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_cfb32_decrypt,</div><div class='del'>-},</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "ofb(des)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-ofb-des",</div><div class='del'>-	.base.cra_blocksize	= 1,</div><div class='del'>-	.base.cra_alignmask	= 0x7,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES_KEY_SIZE,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= atmel_des_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_ofb_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_ofb_decrypt,</div><div class='del'>-},</div><div class='del'>-{</div><div class='ctx'> 	.base.cra_name		= "ecb(des3_ede)",</div><div class='ctx'> 	.base.cra_driver_name	= "atmel-ecb-tdes",</div><div class='ctx'> 	.base.cra_blocksize	= DES_BLOCK_SIZE,</div><div class='hunk'>@@ -1021,19 +843,6 @@ static struct skcipher_alg tdes_algs[] = {</div><div class='ctx'> 	.decrypt		= atmel_tdes_cbc_decrypt,</div><div class='ctx'> 	.ivsize			= DES_BLOCK_SIZE,</div><div class='ctx'> },</div><div class='del'>-{</div><div class='del'>-	.base.cra_name		= "ofb(des3_ede)",</div><div class='del'>-	.base.cra_driver_name	= "atmel-ofb-tdes",</div><div class='del'>-	.base.cra_blocksize	= DES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_alignmask	= 0x7,</div><div class='del'>-</div><div class='del'>-	.min_keysize		= DES3_EDE_KEY_SIZE,</div><div class='del'>-	.max_keysize		= DES3_EDE_KEY_SIZE,</div><div class='del'>-	.setkey			= atmel_tdes_setkey,</div><div class='del'>-	.encrypt		= atmel_tdes_ofb_encrypt,</div><div class='del'>-	.decrypt		= atmel_tdes_ofb_decrypt,</div><div class='del'>-	.ivsize			= DES_BLOCK_SIZE,</div><div class='del'>-},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void atmel_tdes_queue_task(unsigned long data)</div><div class='hunk'>@@ -1121,14 +930,12 @@ static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd)</div><div class='ctx'> {</div><div class='ctx'> </div><div class='ctx'> 	dd-&gt;caps.has_dma = 0;</div><div class='del'>-	dd-&gt;caps.has_cfb_3keys = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* keep only major version number */</div><div class='ctx'> 	switch (dd-&gt;hw_version &amp; 0xf00) {</div><div class='ctx'> 	case 0x800:</div><div class='ctx'> 	case 0x700:</div><div class='ctx'> 		dd-&gt;caps.has_dma = 1;</div><div class='del'>-		dd-&gt;caps.has_cfb_3keys = 1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 0x600:</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c<br/>index ef9fe13ffa59..dbc1d483f2af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/axis/artpec6_crypto.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/axis/artpec6_crypto.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/axis/artpec6_crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/axis/artpec6_crypto.c</a></div><div class='hunk'>@@ -1535,7 +1535,8 @@ static int artpec6_crypto_aes_ecb_init(struct crypto_skcipher *tfm)</div><div class='ctx'> {</div><div class='ctx'> 	struct artpec6_cryptotfm_context *ctx = crypto_skcipher_ctx(tfm);</div><div class='ctx'> </div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct artpec6_crypto_request_context);</div><div class='add'>+	crypto_skcipher_set_reqsize(tfm,</div><div class='add'>+				    sizeof(struct artpec6_crypto_request_context));</div><div class='ctx'> 	ctx-&gt;crypto_type = ARTPEC6_CRYPTO_CIPHER_AES_ECB;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1551,7 +1552,8 @@ static int artpec6_crypto_aes_ctr_init(struct crypto_skcipher *tfm)</div><div class='ctx'> 	if (IS_ERR(ctx-&gt;fallback))</div><div class='ctx'> 		return PTR_ERR(ctx-&gt;fallback);</div><div class='ctx'> </div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct artpec6_crypto_request_context);</div><div class='add'>+	crypto_skcipher_set_reqsize(tfm,</div><div class='add'>+				    sizeof(struct artpec6_crypto_request_context));</div><div class='ctx'> 	ctx-&gt;crypto_type = ARTPEC6_CRYPTO_CIPHER_AES_CTR;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1561,7 +1563,8 @@ static int artpec6_crypto_aes_cbc_init(struct crypto_skcipher *tfm)</div><div class='ctx'> {</div><div class='ctx'> 	struct artpec6_cryptotfm_context *ctx = crypto_skcipher_ctx(tfm);</div><div class='ctx'> </div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct artpec6_crypto_request_context);</div><div class='add'>+	crypto_skcipher_set_reqsize(tfm,</div><div class='add'>+				    sizeof(struct artpec6_crypto_request_context));</div><div class='ctx'> 	ctx-&gt;crypto_type = ARTPEC6_CRYPTO_CIPHER_AES_CBC;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1571,7 +1574,8 @@ static int artpec6_crypto_aes_xts_init(struct crypto_skcipher *tfm)</div><div class='ctx'> {</div><div class='ctx'> 	struct artpec6_cryptotfm_context *ctx = crypto_skcipher_ctx(tfm);</div><div class='ctx'> </div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct artpec6_crypto_request_context);</div><div class='add'>+	crypto_skcipher_set_reqsize(tfm,</div><div class='add'>+				    sizeof(struct artpec6_crypto_request_context));</div><div class='ctx'> 	ctx-&gt;crypto_type = ARTPEC6_CRYPTO_CIPHER_AES_XTS;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/crypto/bcm/cipher.c b/drivers/crypto/bcm/cipher.c<br/>index 10968ddb146b..1a3ecd44cbaf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/bcm/cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/bcm/cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/bcm/cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/bcm/cipher.c</a></div><div class='hunk'>@@ -3517,25 +3517,6 @@ static struct iproc_alg_s driver_algs[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='ctx'> 	 .alg.skcipher = {</div><div class='del'>-			.base.cra_name = "ofb(des)",</div><div class='del'>-			.base.cra_driver_name = "ofb-des-iproc",</div><div class='del'>-			.base.cra_blocksize = DES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize = DES_KEY_SIZE,</div><div class='del'>-			.max_keysize = DES_KEY_SIZE,</div><div class='del'>-			.ivsize = DES_BLOCK_SIZE,</div><div class='del'>-			},</div><div class='del'>-	 .cipher_info = {</div><div class='del'>-			 .alg = CIPHER_ALG_DES,</div><div class='del'>-			 .mode = CIPHER_MODE_OFB,</div><div class='del'>-			 },</div><div class='del'>-	 .auth_info = {</div><div class='del'>-		       .alg = HASH_ALG_NONE,</div><div class='del'>-		       .mode = HASH_MODE_NONE,</div><div class='del'>-		       },</div><div class='del'>-	 },</div><div class='del'>-	{</div><div class='del'>-	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='del'>-	 .alg.skcipher = {</div><div class='ctx'> 			.base.cra_name = "cbc(des)",</div><div class='ctx'> 			.base.cra_driver_name = "cbc-des-iproc",</div><div class='ctx'> 			.base.cra_blocksize = DES_BLOCK_SIZE,</div><div class='hunk'>@@ -3574,25 +3555,6 @@ static struct iproc_alg_s driver_algs[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='ctx'> 	 .alg.skcipher = {</div><div class='del'>-			.base.cra_name = "ofb(des3_ede)",</div><div class='del'>-			.base.cra_driver_name = "ofb-des3-iproc",</div><div class='del'>-			.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,</div><div class='del'>-			.min_keysize = DES3_EDE_KEY_SIZE,</div><div class='del'>-			.max_keysize = DES3_EDE_KEY_SIZE,</div><div class='del'>-			.ivsize = DES3_EDE_BLOCK_SIZE,</div><div class='del'>-			},</div><div class='del'>-	 .cipher_info = {</div><div class='del'>-			 .alg = CIPHER_ALG_3DES,</div><div class='del'>-			 .mode = CIPHER_MODE_OFB,</div><div class='del'>-			 },</div><div class='del'>-	 .auth_info = {</div><div class='del'>-		       .alg = HASH_ALG_NONE,</div><div class='del'>-		       .mode = HASH_MODE_NONE,</div><div class='del'>-		       },</div><div class='del'>-	 },</div><div class='del'>-	{</div><div class='del'>-	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='del'>-	 .alg.skcipher = {</div><div class='ctx'> 			.base.cra_name = "cbc(des3_ede)",</div><div class='ctx'> 			.base.cra_driver_name = "cbc-des3-iproc",</div><div class='ctx'> 			.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,</div><div class='hunk'>@@ -3631,25 +3593,6 @@ static struct iproc_alg_s driver_algs[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='ctx'> 	 .alg.skcipher = {</div><div class='del'>-			.base.cra_name = "ofb(aes)",</div><div class='del'>-			.base.cra_driver_name = "ofb-aes-iproc",</div><div class='del'>-			.base.cra_blocksize = AES_BLOCK_SIZE,</div><div class='del'>-			.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-			.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-			},</div><div class='del'>-	 .cipher_info = {</div><div class='del'>-			 .alg = CIPHER_ALG_AES,</div><div class='del'>-			 .mode = CIPHER_MODE_OFB,</div><div class='del'>-			 },</div><div class='del'>-	 .auth_info = {</div><div class='del'>-		       .alg = HASH_ALG_NONE,</div><div class='del'>-		       .mode = HASH_MODE_NONE,</div><div class='del'>-		       },</div><div class='del'>-	 },</div><div class='del'>-	{</div><div class='del'>-	 .type = CRYPTO_ALG_TYPE_SKCIPHER,</div><div class='del'>-	 .alg.skcipher = {</div><div class='ctx'> 			.base.cra_name = "cbc(aes)",</div><div class='ctx'> 			.base.cra_driver_name = "cbc-aes-iproc",</div><div class='ctx'> 			.base.cra_blocksize = AES_BLOCK_SIZE,</div><div class='head'>diff --git a/drivers/crypto/cavium/cpt/cptvf_algs.c b/drivers/crypto/cavium/cpt/cptvf_algs.c<br/>index ee476c6c7f82..219fe9be7606 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/cavium/cpt/cptvf_algs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/cavium/cpt/cptvf_algs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/cavium/cpt/cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/cavium/cpt/cptvf_algs.c</a></div><div class='hunk'>@@ -311,12 +311,6 @@ static int cvm_ecb_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,</div><div class='ctx'> 	return cvm_setkey(cipher, key, keylen, AES_ECB);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cvm_cfb_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,</div><div class='del'>-			      u32 keylen)</div><div class='del'>-{</div><div class='del'>-	return cvm_setkey(cipher, key, keylen, AES_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int cvm_cbc_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,</div><div class='ctx'> 			       u32 keylen)</div><div class='ctx'> {</div><div class='hunk'>@@ -394,24 +388,6 @@ static struct skcipher_alg algs[] = { {</div><div class='ctx'> }, {</div><div class='ctx'> 	.base.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='ctx'> 				  CRYPTO_ALG_ALLOCATES_MEMORY,</div><div class='del'>-	.base.cra_blocksize	= AES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct cvm_enc_ctx),</div><div class='del'>-	.base.cra_alignmask	= 7,</div><div class='del'>-	.base.cra_priority	= 4001,</div><div class='del'>-	.base.cra_name		= "cfb(aes)",</div><div class='del'>-	.base.cra_driver_name	= "cavium-cfb-aes",</div><div class='del'>-	.base.cra_module	= THIS_MODULE,</div><div class='del'>-</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= cvm_cfb_aes_setkey,</div><div class='del'>-	.encrypt		= cvm_encrypt,</div><div class='del'>-	.decrypt		= cvm_decrypt,</div><div class='del'>-	.init			= cvm_enc_dec_init,</div><div class='del'>-}, {</div><div class='del'>-	.base.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='del'>-				  CRYPTO_ALG_ALLOCATES_MEMORY,</div><div class='ctx'> 	.base.cra_blocksize	= DES3_EDE_BLOCK_SIZE,</div><div class='ctx'> 	.base.cra_ctxsize	= sizeof(struct cvm_des3_ctx),</div><div class='ctx'> 	.base.cra_alignmask	= 7,</div><div class='head'>diff --git a/drivers/crypto/cavium/nitrox/nitrox_skcipher.c b/drivers/crypto/cavium/nitrox/nitrox_skcipher.c<br/>index 138261dcd032..6e5e667bab75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/cavium/nitrox/nitrox_skcipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/cavium/nitrox/nitrox_skcipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/cavium/nitrox/nitrox_skcipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/cavium/nitrox/nitrox_skcipher.c</a></div><div class='hunk'>@@ -421,25 +421,6 @@ static struct skcipher_alg nitrox_skciphers[] = { {</div><div class='ctx'> 	.exit = nitrox_skcipher_exit,</div><div class='ctx'> }, {</div><div class='ctx'> 	.base = {</div><div class='del'>-		.cra_name = "cfb(aes)",</div><div class='del'>-		.cra_driver_name = "n5_cfb(aes)",</div><div class='del'>-		.cra_priority = PRIO,</div><div class='del'>-		.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY,</div><div class='del'>-		.cra_blocksize = AES_BLOCK_SIZE,</div><div class='del'>-		.cra_ctxsize = sizeof(struct nitrox_crypto_ctx),</div><div class='del'>-		.cra_alignmask = 0,</div><div class='del'>-		.cra_module = THIS_MODULE,</div><div class='del'>-	},</div><div class='del'>-	.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-	.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-	.setkey = nitrox_aes_setkey,</div><div class='del'>-	.encrypt = nitrox_aes_encrypt,</div><div class='del'>-	.decrypt = nitrox_aes_decrypt,</div><div class='del'>-	.init = nitrox_skcipher_init,</div><div class='del'>-	.exit = nitrox_skcipher_exit,</div><div class='del'>-}, {</div><div class='del'>-	.base = {</div><div class='ctx'> 		.cra_name = "xts(aes)",</div><div class='ctx'> 		.cra_driver_name = "n5_xts(aes)",</div><div class='ctx'> 		.cra_priority = PRIO,</div><div class='head'>diff --git a/drivers/crypto/ccp/ccp-crypto-aes.c b/drivers/crypto/ccp/ccp-crypto-aes.c<br/>index 918e223f21b6..d11daaf47f06 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/ccp-crypto-aes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/ccp/ccp-crypto-aes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/ccp-crypto-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/ccp-crypto-aes.c</a></div><div class='hunk'>@@ -267,24 +267,6 @@ static struct ccp_aes_def aes_algs[] = {</div><div class='ctx'> 		.alg_defaults	= &amp;ccp_aes_defaults,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.mode		= CCP_AES_MODE_CFB,</div><div class='del'>-		.version	= CCP_VERSION(3, 0),</div><div class='del'>-		.name		= "cfb(aes)",</div><div class='del'>-		.driver_name	= "cfb-aes-ccp",</div><div class='del'>-		.blocksize	= 1,</div><div class='del'>-		.ivsize		= AES_BLOCK_SIZE,</div><div class='del'>-		.alg_defaults	= &amp;ccp_aes_defaults,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.mode		= CCP_AES_MODE_OFB,</div><div class='del'>-		.version	= CCP_VERSION(3, 0),</div><div class='del'>-		.name		= "ofb(aes)",</div><div class='del'>-		.driver_name	= "ofb-aes-ccp",</div><div class='del'>-		.blocksize	= 1,</div><div class='del'>-		.ivsize		= AES_BLOCK_SIZE,</div><div class='del'>-		.alg_defaults	= &amp;ccp_aes_defaults,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.mode		= CCP_AES_MODE_CTR,</div><div class='ctx'> 		.version	= CCP_VERSION(3, 0),</div><div class='ctx'> 		.name		= "ctr(aes)",</div><div class='head'>diff --git a/drivers/crypto/ccp/ccp-ops.c b/drivers/crypto/ccp/ccp-ops.c<br/>index aa4e1a500691..cb8e99936abb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/ccp-ops.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/ccp/ccp-ops.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/ccp-ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/ccp-ops.c</a></div><div class='hunk'>@@ -179,8 +179,11 @@ static int ccp_init_dm_workarea(struct ccp_dm_workarea *wa,</div><div class='ctx'> </div><div class='ctx'> 		wa-&gt;dma.address = dma_map_single(wa-&gt;dev, wa-&gt;address, len,</div><div class='ctx'> 						 dir);</div><div class='del'>-		if (dma_mapping_error(wa-&gt;dev, wa-&gt;dma.address))</div><div class='add'>+		if (dma_mapping_error(wa-&gt;dev, wa-&gt;dma.address)) {</div><div class='add'>+			kfree(wa-&gt;address);</div><div class='add'>+			wa-&gt;address = NULL;</div><div class='ctx'> 			return -ENOMEM;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		wa-&gt;dma.length = len;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c<br/>index fcaccd0b5a65..e4d3f45242f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/sev-dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/ccp/sev-dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/ccp/sev-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccp/sev-dev.c</a></div><div class='hunk'>@@ -906,7 +906,7 @@ static int sev_ioctl_do_get_id2(struct sev_issue_cmd *argp)</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The length of the ID shouldn't be assumed by software since</div><div class='ctx'> 		 * it may change in the future.  The allocation size is limited</div><div class='del'>-		 * to 1 &lt;&lt; (PAGE_SHIFT + MAX_ORDER) by the page allocator.</div><div class='add'>+		 * to 1 &lt;&lt; (PAGE_SHIFT + MAX_PAGE_ORDER) by the page allocator.</div><div class='ctx'> 		 * If the allocation fails, simply return ENOMEM rather than</div><div class='ctx'> 		 * warning in the kernel log.</div><div class='ctx'> 		 */</div><div class='head'>diff --git a/drivers/crypto/ccree/cc_aead.c b/drivers/crypto/ccree/cc_aead.c<br/>index 109ffb375fc6..5ef39d682389 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/ccree/cc_aead.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/ccree/cc_aead.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/ccree/cc_aead.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccree/cc_aead.c</a></div><div class='hunk'>@@ -2569,9 +2569,13 @@ static struct cc_crypto_alg *cc_create_aead_alg(struct cc_alg_template *tmpl,</div><div class='ctx'> </div><div class='ctx'> 	alg = &amp;tmpl-&gt;template_aead;</div><div class='ctx'> </div><div class='del'>-	snprintf(alg-&gt;base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl-&gt;name);</div><div class='del'>-	snprintf(alg-&gt;base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='del'>-		 tmpl-&gt;driver_name);</div><div class='add'>+	if (snprintf(alg-&gt;base.cra_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='add'>+		     tmpl-&gt;name) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+	if (snprintf(alg-&gt;base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='add'>+		     tmpl-&gt;driver_name) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='ctx'> 	alg-&gt;base.cra_module = THIS_MODULE;</div><div class='ctx'> 	alg-&gt;base.cra_priority = CC_CRA_PRIO;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c<br/>index 2cd44d7457a4..cd66a580e8b6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/ccree/cc_cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/ccree/cc_cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/ccree/cc_cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/ccree/cc_cipher.c</a></div><div class='hunk'>@@ -1080,24 +1080,6 @@ static const struct cc_alg_template skcipher_algs[] = {</div><div class='ctx'> 		.sec_func = true,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.name = "ofb(paes)",</div><div class='del'>-		.driver_name = "ofb-paes-ccree",</div><div class='del'>-		.blocksize = AES_BLOCK_SIZE,</div><div class='del'>-		.template_skcipher = {</div><div class='del'>-			.setkey = cc_cipher_sethkey,</div><div class='del'>-			.encrypt = cc_cipher_encrypt,</div><div class='del'>-			.decrypt = cc_cipher_decrypt,</div><div class='del'>-			.min_keysize = CC_HW_KEY_SIZE,</div><div class='del'>-			.max_keysize = CC_HW_KEY_SIZE,</div><div class='del'>-			.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-			},</div><div class='del'>-		.cipher_mode = DRV_CIPHER_OFB,</div><div class='del'>-		.flow_mode = S_DIN_to_AES,</div><div class='del'>-		.min_hw_rev = CC_HW_REV_712,</div><div class='del'>-		.std_body = CC_STD_NIST,</div><div class='del'>-		.sec_func = true,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.name = "cts(cbc(paes))",</div><div class='ctx'> 		.driver_name = "cts-cbc-paes-ccree",</div><div class='ctx'> 		.blocksize = AES_BLOCK_SIZE,</div><div class='hunk'>@@ -1206,23 +1188,6 @@ static const struct cc_alg_template skcipher_algs[] = {</div><div class='ctx'> 		.std_body = CC_STD_NIST,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.name = "ofb(aes)",</div><div class='del'>-		.driver_name = "ofb-aes-ccree",</div><div class='del'>-		.blocksize = 1,</div><div class='del'>-		.template_skcipher = {</div><div class='del'>-			.setkey = cc_cipher_setkey,</div><div class='del'>-			.encrypt = cc_cipher_encrypt,</div><div class='del'>-			.decrypt = cc_cipher_decrypt,</div><div class='del'>-			.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-			.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-			},</div><div class='del'>-		.cipher_mode = DRV_CIPHER_OFB,</div><div class='del'>-		.flow_mode = S_DIN_to_AES,</div><div class='del'>-		.min_hw_rev = CC_HW_REV_630,</div><div class='del'>-		.std_body = CC_STD_NIST,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.name = "cts(cbc(aes))",</div><div class='ctx'> 		.driver_name = "cts-cbc-aes-ccree",</div><div class='ctx'> 		.blocksize = AES_BLOCK_SIZE,</div><div class='hunk'>@@ -1427,9 +1392,13 @@ static struct cc_crypto_alg *cc_create_alg(const struct cc_alg_template *tmpl,</div><div class='ctx'> </div><div class='ctx'> 	memcpy(alg, &amp;tmpl-&gt;template_skcipher, sizeof(*alg));</div><div class='ctx'> </div><div class='del'>-	snprintf(alg-&gt;base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl-&gt;name);</div><div class='del'>-	snprintf(alg-&gt;base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='del'>-		 tmpl-&gt;driver_name);</div><div class='add'>+	if (snprintf(alg-&gt;base.cra_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='add'>+		     tmpl-&gt;name) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+	if (snprintf(alg-&gt;base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",</div><div class='add'>+		     tmpl-&gt;driver_name) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='ctx'> 	alg-&gt;base.cra_module = THIS_MODULE;</div><div class='ctx'> 	alg-&gt;base.cra_priority = CC_CRA_PRIO;</div><div class='ctx'> 	alg-&gt;base.cra_blocksize = tmpl-&gt;blocksize;</div><div class='head'>diff --git a/drivers/crypto/gemini/sl3516-ce-cipher.c b/drivers/crypto/gemini/sl3516-ce-cipher.c<br/>index 49dce9e0a834..583010b2d007 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/gemini/sl3516-ce-cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/gemini/sl3516-ce-cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/gemini/sl3516-ce-cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/gemini/sl3516-ce-cipher.c</a></div><div class='hunk'>@@ -332,8 +332,8 @@ int sl3516_ce_cipher_init(struct crypto_tfm *tfm)</div><div class='ctx'> 		return PTR_ERR(op-&gt;fallback_tfm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sktfm-&gt;reqsize = sizeof(struct sl3516_ce_cipher_req_ctx) +</div><div class='del'>-			 crypto_skcipher_reqsize(op-&gt;fallback_tfm);</div><div class='add'>+	crypto_skcipher_set_reqsize(sktfm, sizeof(struct sl3516_ce_cipher_req_ctx) +</div><div class='add'>+				    crypto_skcipher_reqsize(op-&gt;fallback_tfm));</div><div class='ctx'> </div><div class='ctx'> 	dev_info(op-&gt;ce-&gt;dev, "Fallback for %s is %s\n",</div><div class='ctx'> 		 crypto_tfm_alg_driver_name(&amp;sktfm-&gt;base),</div><div class='head'>diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c<br/>index 7bddc3c786c1..b4a4ec35bce0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hifn_795x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hifn_795x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hifn_795x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hifn_795x.c</a></div><div class='hunk'>@@ -2096,16 +2096,6 @@ static inline int hifn_encrypt_aes_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_encrypt_aes_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_encrypt_aes_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * AES decryption functions.</div><div class='hunk'>@@ -2120,16 +2110,6 @@ static inline int hifn_decrypt_aes_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_decrypt_aes_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_decrypt_aes_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * DES ecryption functions.</div><div class='hunk'>@@ -2144,16 +2124,6 @@ static inline int hifn_encrypt_des_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_encrypt_des_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_encrypt_des_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * DES decryption functions.</div><div class='hunk'>@@ -2168,16 +2138,6 @@ static inline int hifn_decrypt_des_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_decrypt_des_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_decrypt_des_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * 3DES ecryption functions.</div><div class='hunk'>@@ -2192,16 +2152,6 @@ static inline int hifn_encrypt_3des_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_encrypt_3des_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_encrypt_3des_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,</div><div class='del'>-			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> /* 3DES decryption functions. */</div><div class='ctx'> static inline int hifn_decrypt_3des_ecb(struct skcipher_request *req)</div><div class='hunk'>@@ -2214,16 +2164,6 @@ static inline int hifn_decrypt_3des_cbc(struct skcipher_request *req)</div><div class='ctx'> 	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='ctx'> 			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);</div><div class='ctx'> }</div><div class='del'>-static inline int hifn_decrypt_3des_cfb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-static inline int hifn_decrypt_3des_ofb(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,</div><div class='del'>-			ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> struct hifn_alg_template {</div><div class='ctx'> 	char name[CRYPTO_MAX_ALG_NAME];</div><div class='hunk'>@@ -2234,29 +2174,9 @@ struct hifn_alg_template {</div><div class='ctx'> </div><div class='ctx'> static const struct hifn_alg_template hifn_alg_templates[] = {</div><div class='ctx'> 	/*</div><div class='del'>-	 * 3DES ECB, CBC, CFB and OFB modes.</div><div class='add'>+	 * 3DES ECB and CBC modes.</div><div class='ctx'> 	 */</div><div class='ctx'> 	{</div><div class='del'>-		.name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	HIFN_3DES_KEY_LENGTH,</div><div class='del'>-			.max_keysize	=	HIFN_3DES_KEY_LENGTH,</div><div class='del'>-			.setkey		=	hifn_des3_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_3des_cfb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_3des_cfb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	HIFN_3DES_KEY_LENGTH,</div><div class='del'>-			.max_keysize	=	HIFN_3DES_KEY_LENGTH,</div><div class='del'>-			.setkey		=	hifn_des3_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_3des_ofb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_3des_ofb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,</div><div class='ctx'> 		.skcipher = {</div><div class='ctx'> 			.ivsize		=	HIFN_IV_LENGTH,</div><div class='hunk'>@@ -2279,29 +2199,9 @@ static const struct hifn_alg_template hifn_alg_templates[] = {</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * DES ECB, CBC, CFB and OFB modes.</div><div class='add'>+	 * DES ECB and CBC modes.</div><div class='ctx'> 	 */</div><div class='ctx'> 	{</div><div class='del'>-		.name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	HIFN_DES_KEY_LENGTH,</div><div class='del'>-			.max_keysize	=	HIFN_DES_KEY_LENGTH,</div><div class='del'>-			.setkey		=	hifn_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_des_cfb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_des_cfb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	HIFN_DES_KEY_LENGTH,</div><div class='del'>-			.max_keysize	=	HIFN_DES_KEY_LENGTH,</div><div class='del'>-			.setkey		=	hifn_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_des_ofb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_des_ofb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,</div><div class='ctx'> 		.skcipher = {</div><div class='ctx'> 			.ivsize		=	HIFN_IV_LENGTH,</div><div class='hunk'>@@ -2324,7 +2224,7 @@ static const struct hifn_alg_template hifn_alg_templates[] = {</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * AES ECB, CBC, CFB and OFB modes.</div><div class='add'>+	 * AES ECB and CBC modes.</div><div class='ctx'> 	 */</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,</div><div class='hunk'>@@ -2347,26 +2247,6 @@ static const struct hifn_alg_template hifn_alg_templates[] = {</div><div class='ctx'> 			.decrypt	=	hifn_decrypt_aes_cbc,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='del'>-	{</div><div class='del'>-		.name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize	=	AES_MAX_KEY_SIZE,</div><div class='del'>-			.setkey		=	hifn_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_aes_cfb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_aes_cfb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,</div><div class='del'>-		.skcipher = {</div><div class='del'>-			.min_keysize	=	AES_MIN_KEY_SIZE,</div><div class='del'>-			.max_keysize	=	AES_MAX_KEY_SIZE,</div><div class='del'>-			.setkey		=	hifn_setkey,</div><div class='del'>-			.encrypt	=	hifn_encrypt_aes_ofb,</div><div class='del'>-			.decrypt	=	hifn_decrypt_aes_ofb,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int hifn_init_tfm(struct crypto_skcipher *tfm)</div><div class='head'>diff --git a/drivers/crypto/hisilicon/debugfs.c b/drivers/crypto/hisilicon/debugfs.c<br/>index 7e8186fe0512..80ed4b2d209c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/debugfs.c</a></div><div class='hunk'>@@ -31,6 +31,10 @@ static const char * const qm_debug_file_name[] = {</div><div class='ctx'> 	[CLEAR_ENABLE] = "clear_enable",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const char * const qm_s[] = {</div><div class='add'>+	"work", "stop",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct qm_dfx_item {</div><div class='ctx'> 	const char *name;</div><div class='ctx'> 	u32 offset;</div><div class='hunk'>@@ -53,34 +57,34 @@ static struct qm_dfx_item qm_dfx_files[] = {</div><div class='ctx'> #define CNT_CYC_REGS_NUM		10</div><div class='ctx'> static const struct debugfs_reg32 qm_dfx_regs[] = {</div><div class='ctx'> 	/* XXX_CNT are reading clear register */</div><div class='del'>-	{"QM_ECC_1BIT_CNT               ",  0x104000ull},</div><div class='del'>-	{"QM_ECC_MBIT_CNT               ",  0x104008ull},</div><div class='del'>-	{"QM_DFX_MB_CNT                 ",  0x104018ull},</div><div class='del'>-	{"QM_DFX_DB_CNT                 ",  0x104028ull},</div><div class='del'>-	{"QM_DFX_SQE_CNT                ",  0x104038ull},</div><div class='del'>-	{"QM_DFX_CQE_CNT                ",  0x104048ull},</div><div class='del'>-	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050ull},</div><div class='del'>-	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058ull},</div><div class='del'>-	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060ull},</div><div class='del'>-	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4ull},</div><div class='del'>-	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},</div><div class='del'>-	{"QM_ECC_1BIT_INF               ",  0x104004ull},</div><div class='del'>-	{"QM_ECC_MBIT_INF               ",  0x10400cull},</div><div class='del'>-	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0ull},</div><div class='del'>-	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4ull},</div><div class='del'>-	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8ull},</div><div class='del'>-	{"QM_DFX_FF_ST0                 ",  0x1040c8ull},</div><div class='del'>-	{"QM_DFX_FF_ST1                 ",  0x1040ccull},</div><div class='del'>-	{"QM_DFX_FF_ST2                 ",  0x1040d0ull},</div><div class='del'>-	{"QM_DFX_FF_ST3                 ",  0x1040d4ull},</div><div class='del'>-	{"QM_DFX_FF_ST4                 ",  0x1040d8ull},</div><div class='del'>-	{"QM_DFX_FF_ST5                 ",  0x1040dcull},</div><div class='del'>-	{"QM_DFX_FF_ST6                 ",  0x1040e0ull},</div><div class='del'>-	{"QM_IN_IDLE_ST                 ",  0x1040e4ull},</div><div class='add'>+	{"QM_ECC_1BIT_CNT               ",  0x104000},</div><div class='add'>+	{"QM_ECC_MBIT_CNT               ",  0x104008},</div><div class='add'>+	{"QM_DFX_MB_CNT                 ",  0x104018},</div><div class='add'>+	{"QM_DFX_DB_CNT                 ",  0x104028},</div><div class='add'>+	{"QM_DFX_SQE_CNT                ",  0x104038},</div><div class='add'>+	{"QM_DFX_CQE_CNT                ",  0x104048},</div><div class='add'>+	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050},</div><div class='add'>+	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058},</div><div class='add'>+	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060},</div><div class='add'>+	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4},</div><div class='add'>+	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},</div><div class='add'>+	{"QM_ECC_1BIT_INF               ",  0x104004},</div><div class='add'>+	{"QM_ECC_MBIT_INF               ",  0x10400c},</div><div class='add'>+	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0},</div><div class='add'>+	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4},</div><div class='add'>+	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8},</div><div class='add'>+	{"QM_DFX_FF_ST0                 ",  0x1040c8},</div><div class='add'>+	{"QM_DFX_FF_ST1                 ",  0x1040cc},</div><div class='add'>+	{"QM_DFX_FF_ST2                 ",  0x1040d0},</div><div class='add'>+	{"QM_DFX_FF_ST3                 ",  0x1040d4},</div><div class='add'>+	{"QM_DFX_FF_ST4                 ",  0x1040d8},</div><div class='add'>+	{"QM_DFX_FF_ST5                 ",  0x1040dc},</div><div class='add'>+	{"QM_DFX_FF_ST6                 ",  0x1040e0},</div><div class='add'>+	{"QM_IN_IDLE_ST                 ",  0x1040e4},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct debugfs_reg32 qm_vf_dfx_regs[] = {</div><div class='del'>-	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},</div><div class='add'>+	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* define the QM's dfx regs region and region length */</div><div class='head'>diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c<br/>index 56777099ef69..3255b2a070c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/hpre/hpre_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/hpre/hpre_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/hpre/hpre_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/hpre/hpre_main.c</a></div><div class='hunk'>@@ -118,8 +118,6 @@</div><div class='ctx'> #define HPRE_DFX_COMMON2_LEN		0xE</div><div class='ctx'> #define HPRE_DFX_CORE_LEN		0x43</div><div class='ctx'> </div><div class='del'>-#define HPRE_DEV_ALG_MAX_LEN	256</div><div class='del'>-</div><div class='ctx'> static const char hpre_name[] = "hisi_hpre";</div><div class='ctx'> static struct dentry *hpre_debugfs_root;</div><div class='ctx'> static const struct pci_device_id hpre_dev_ids[] = {</div><div class='hunk'>@@ -135,12 +133,7 @@ struct hpre_hw_error {</div><div class='ctx'> 	const char *msg;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct hpre_dev_alg {</div><div class='del'>-	u32 alg_msk;</div><div class='del'>-	const char *alg;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct hpre_dev_alg hpre_dev_algs[] = {</div><div class='add'>+static const struct qm_dev_alg hpre_dev_algs[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.alg_msk = BIT(0),</div><div class='ctx'> 		.alg = "rsa\n"</div><div class='hunk'>@@ -233,6 +226,20 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = {</div><div class='ctx'> 	{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum hpre_pre_store_cap_idx {</div><div class='add'>+	HPRE_CLUSTER_NUM_CAP_IDX = 0x0,</div><div class='add'>+	HPRE_CORE_ENABLE_BITMAP_CAP_IDX,</div><div class='add'>+	HPRE_DRV_ALG_BITMAP_CAP_IDX,</div><div class='add'>+	HPRE_DEV_ALG_BITMAP_CAP_IDX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 hpre_pre_store_caps[] = {</div><div class='add'>+	HPRE_CLUSTER_NUM_CAP,</div><div class='add'>+	HPRE_CORE_ENABLE_BITMAP_CAP,</div><div class='add'>+	HPRE_DRV_ALG_BITMAP_CAP,</div><div class='add'>+	HPRE_DEV_ALG_BITMAP_CAP,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct hpre_hw_error hpre_hw_errors[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.int_msk = BIT(0),</div><div class='hunk'>@@ -355,42 +362,13 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)</div><div class='ctx'> {</div><div class='ctx'> 	u32 cap_val;</div><div class='ctx'> </div><div class='del'>-	cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm-&gt;cap_ver);</div><div class='add'>+	cap_val = qm-&gt;cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;</div><div class='ctx'> 	if (alg &amp; cap_val)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hpre_set_qm_algs(struct hisi_qm *qm)</div><div class='del'>-{</div><div class='del'>-	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='del'>-	char *algs, *ptr;</div><div class='del'>-	u32 alg_msk;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!qm-&gt;use_sva)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);</div><div class='del'>-	if (!algs)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm-&gt;cap_ver);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(hpre_dev_algs); i++)</div><div class='del'>-		if (alg_msk &amp; hpre_dev_algs[i].alg_msk)</div><div class='del'>-			strcat(algs, hpre_dev_algs[i].alg);</div><div class='del'>-</div><div class='del'>-	ptr = strrchr(algs, '\n');</div><div class='del'>-	if (ptr)</div><div class='del'>-		*ptr = '\0';</div><div class='del'>-</div><div class='del'>-	qm-&gt;uacce-&gt;algs = algs;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int hpre_diff_regs_show(struct seq_file *s, void *unused)</div><div class='ctx'> {</div><div class='ctx'> 	struct hisi_qm *qm = s-&gt;private;</div><div class='hunk'>@@ -460,16 +438,6 @@ static u32 vfs_num;</div><div class='ctx'> module_param_cb(vfs_num, &amp;vfs_num_ops, &amp;vfs_num, 0444);</div><div class='ctx'> MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");</div><div class='ctx'> </div><div class='del'>-static inline int hpre_cluster_num(struct hisi_qm *qm)</div><div class='del'>-{</div><div class='del'>-	return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm-&gt;cap_ver);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline int hpre_cluster_core_mask(struct hisi_qm *qm)</div><div class='del'>-{</div><div class='del'>-	return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm-&gt;cap_ver);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct hisi_qp *hpre_create_qp(u8 type)</div><div class='ctx'> {</div><div class='ctx'> 	int node = cpu_to_node(smp_processor_id());</div><div class='hunk'>@@ -536,13 +504,15 @@ static int hpre_cfg_by_dsm(struct hisi_qm *qm)</div><div class='ctx'> </div><div class='ctx'> static int hpre_set_cluster(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	u32 cluster_core_mask = hpre_cluster_core_mask(qm);</div><div class='del'>-	u8 clusters_num = hpre_cluster_num(qm);</div><div class='ctx'> 	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='ctx'> 	unsigned long offset;</div><div class='add'>+	u32 cluster_core_mask;</div><div class='add'>+	u8 clusters_num;</div><div class='ctx'> 	u32 val = 0;</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='add'>+	cluster_core_mask = qm-&gt;cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val;</div><div class='add'>+	clusters_num = qm-&gt;cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;</div><div class='ctx'> 	for (i = 0; i &lt; clusters_num; i++) {</div><div class='ctx'> 		offset = i * HPRE_CLSTR_ADDR_INTRVL;</div><div class='ctx'> </div><div class='hunk'>@@ -737,11 +707,12 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)</div><div class='ctx'> </div><div class='ctx'> static void hpre_cnt_regs_clear(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	u8 clusters_num = hpre_cluster_num(qm);</div><div class='ctx'> 	unsigned long offset;</div><div class='add'>+	u8 clusters_num;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* clear clusterX/cluster_ctrl */</div><div class='add'>+	clusters_num = qm-&gt;cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;</div><div class='ctx'> 	for (i = 0; i &lt; clusters_num; i++) {</div><div class='ctx'> 		offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;</div><div class='ctx'> 		writel(0x0, qm-&gt;io_base + offset + HPRE_CLUSTER_INQURY);</div><div class='hunk'>@@ -1028,13 +999,14 @@ static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)</div><div class='ctx'> </div><div class='ctx'> static int hpre_cluster_debugfs_init(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	u8 clusters_num = hpre_cluster_num(qm);</div><div class='ctx'> 	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='ctx'> 	char buf[HPRE_DBGFS_VAL_MAX_LEN];</div><div class='ctx'> 	struct debugfs_regset32 *regset;</div><div class='ctx'> 	struct dentry *tmp_d;</div><div class='add'>+	u8 clusters_num;</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> </div><div class='add'>+	clusters_num = qm-&gt;cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;</div><div class='ctx'> 	for (i = 0; i &lt; clusters_num; i++) {</div><div class='ctx'> 		ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);</div><div class='ctx'> 		if (ret &gt;= HPRE_DBGFS_VAL_MAX_LEN)</div><div class='hunk'>@@ -1139,8 +1111,37 @@ static void hpre_debugfs_exit(struct hisi_qm *qm)</div><div class='ctx'> 	debugfs_remove_recursive(qm-&gt;debug.debug_root);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int hpre_pre_store_cap_reg(struct hisi_qm *qm)</div><div class='add'>+{</div><div class='add'>+	struct hisi_qm_cap_record *hpre_cap;</div><div class='add'>+	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='add'>+	size_t i, size;</div><div class='add'>+</div><div class='add'>+	size = ARRAY_SIZE(hpre_pre_store_caps);</div><div class='add'>+	hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL);</div><div class='add'>+	if (!hpre_cap)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; size; i++) {</div><div class='add'>+		hpre_cap[i].type = hpre_pre_store_caps[i];</div><div class='add'>+		hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,</div><div class='add'>+				      hpre_pre_store_caps[i], qm-&gt;cap_ver);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val &gt; HPRE_CLUSTERS_NUM_MAX) {</div><div class='add'>+		dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n",</div><div class='add'>+			hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	qm-&gt;cap_tables.dev_cap_table = hpre_cap;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='add'>+	u64 alg_msk;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (pdev-&gt;revision == QM_HW_V1) {</div><div class='hunk'>@@ -1171,7 +1172,16 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = hpre_set_qm_algs(qm);</div><div class='add'>+	/* Fetch and save the value of capability registers */</div><div class='add'>+	ret = hpre_pre_store_cap_reg(qm);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pci_err(pdev, "Failed to pre-store capability registers!\n");</div><div class='add'>+		hisi_qm_uninit(qm);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alg_msk = qm-&gt;cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;</div><div class='add'>+	ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pci_err(pdev, "Failed to set hpre algs!\n");</div><div class='ctx'> 		hisi_qm_uninit(qm);</div><div class='hunk'>@@ -1184,11 +1194,12 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	int cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);</div><div class='ctx'> 	int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);</div><div class='del'>-	u8 clusters_num = hpre_cluster_num(qm);</div><div class='ctx'> 	struct qm_debug *debug = &amp;qm-&gt;debug;</div><div class='ctx'> 	void __iomem *io_base;</div><div class='add'>+	u8 clusters_num;</div><div class='ctx'> 	int i, j, idx;</div><div class='ctx'> </div><div class='add'>+	clusters_num = qm-&gt;cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;</div><div class='ctx'> 	debug-&gt;last_words = kcalloc(cluster_dfx_regs_num * clusters_num +</div><div class='ctx'> 			com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);</div><div class='ctx'> 	if (!debug-&gt;last_words)</div><div class='hunk'>@@ -1225,10 +1236,10 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	int cluster_dfx_regs_num =  ARRAY_SIZE(hpre_cluster_dfx_regs);</div><div class='ctx'> 	int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);</div><div class='del'>-	u8 clusters_num = hpre_cluster_num(qm);</div><div class='ctx'> 	struct qm_debug *debug = &amp;qm-&gt;debug;</div><div class='ctx'> 	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='ctx'> 	void __iomem *io_base;</div><div class='add'>+	u8 clusters_num;</div><div class='ctx'> 	int i, j, idx;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='hunk'>@@ -1243,6 +1254,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)</div><div class='ctx'> 			  hpre_com_dfx_regs[i].name, debug-&gt;last_words[i], val);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	clusters_num = qm-&gt;cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;</div><div class='ctx'> 	for (i = 0; i &lt; clusters_num; i++) {</div><div class='ctx'> 		io_base = qm-&gt;io_base + hpre_cluster_offsets[i];</div><div class='ctx'> 		for (j = 0; j &lt;  cluster_dfx_regs_num; j++) {</div><div class='head'>diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c<br/>index 18599f3634c3..4b20b94e6371 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/qm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/qm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/qm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/qm.c</a></div><div class='hunk'>@@ -129,16 +129,21 @@</div><div class='ctx'> #define QM_FIFO_OVERFLOW_TYPE		0xc0</div><div class='ctx'> #define QM_FIFO_OVERFLOW_TYPE_SHIFT	6</div><div class='ctx'> #define QM_FIFO_OVERFLOW_VF		0x3f</div><div class='add'>+#define QM_FIFO_OVERFLOW_QP_SHIFT	16</div><div class='ctx'> #define QM_ABNORMAL_INF01		0x100014</div><div class='ctx'> #define QM_DB_TIMEOUT_TYPE		0xc0</div><div class='ctx'> #define QM_DB_TIMEOUT_TYPE_SHIFT	6</div><div class='ctx'> #define QM_DB_TIMEOUT_VF		0x3f</div><div class='add'>+#define QM_DB_TIMEOUT_QP_SHIFT		16</div><div class='add'>+#define QM_ABNORMAL_INF02		0x100018</div><div class='add'>+#define QM_AXI_POISON_ERR		BIT(22)</div><div class='ctx'> #define QM_RAS_CE_ENABLE		0x1000ec</div><div class='ctx'> #define QM_RAS_FE_ENABLE		0x1000f0</div><div class='ctx'> #define QM_RAS_NFE_ENABLE		0x1000f4</div><div class='ctx'> #define QM_RAS_CE_THRESHOLD		0x1000f8</div><div class='ctx'> #define QM_RAS_CE_TIMES_PER_IRQ		1</div><div class='ctx'> #define QM_OOO_SHUTDOWN_SEL		0x1040f8</div><div class='add'>+#define QM_AXI_RRESP_ERR		BIT(0)</div><div class='ctx'> #define QM_ECC_MBIT			BIT(2)</div><div class='ctx'> #define QM_DB_TIMEOUT			BIT(10)</div><div class='ctx'> #define QM_OF_FIFO_OF			BIT(11)</div><div class='hunk'>@@ -229,6 +234,8 @@</div><div class='ctx'> #define QM_QOS_MAX_CIR_U		6</div><div class='ctx'> #define QM_AUTOSUSPEND_DELAY		3000</div><div class='ctx'> </div><div class='add'>+#define QM_DEV_ALG_MAX_LEN		256</div><div class='add'>+</div><div class='ctx'> #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \</div><div class='ctx'> 	(((hop_num) &lt;&lt; QM_CQ_HOP_NUM_SHIFT) | \</div><div class='ctx'> 	((pg_sz) &lt;&lt; QM_CQ_PAGE_SIZE_SHIFT) | \</div><div class='hunk'>@@ -294,6 +301,13 @@ enum qm_basic_type {</div><div class='ctx'> 	QM_VF_IRQ_NUM_CAP,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum qm_pre_store_cap_idx {</div><div class='add'>+	QM_EQ_IRQ_TYPE_CAP_IDX = 0x0,</div><div class='add'>+	QM_AEQ_IRQ_TYPE_CAP_IDX,</div><div class='add'>+	QM_ABN_IRQ_TYPE_CAP_IDX,</div><div class='add'>+	QM_PF2VF_IRQ_TYPE_CAP_IDX,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct hisi_qm_cap_info qm_cap_info_comm[] = {</div><div class='ctx'> 	{QM_SUPPORT_DB_ISOLATION, 0x30,   0, BIT(0),  0x0, 0x0, 0x0},</div><div class='ctx'> 	{QM_SUPPORT_FUNC_QOS,     0x3100, 0, BIT(8),  0x0, 0x0, 0x1},</div><div class='hunk'>@@ -323,6 +337,13 @@ static const struct hisi_qm_cap_info qm_basic_info[] = {</div><div class='ctx'> 	{QM_VF_IRQ_NUM_CAP,     0x311c,   0,  GENMASK(15, 0), 0x1,       0x2,       0x3},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const u32 qm_pre_store_caps[] = {</div><div class='add'>+	QM_EQ_IRQ_TYPE_CAP,</div><div class='add'>+	QM_AEQ_IRQ_TYPE_CAP,</div><div class='add'>+	QM_ABN_IRQ_TYPE_CAP,</div><div class='add'>+	QM_PF2VF_IRQ_TYPE_CAP,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct qm_mailbox {</div><div class='ctx'> 	__le16 w0;</div><div class='ctx'> 	__le16 queue_num;</div><div class='hunk'>@@ -386,7 +407,6 @@ static const struct hisi_qm_hw_error qm_hw_error[] = {</div><div class='ctx'> 	{ .int_msk = BIT(12), .msg = "qm_db_random_invalid" },</div><div class='ctx'> 	{ .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },</div><div class='ctx'> 	{ .int_msk = BIT(14), .msg = "qm_flr_timeout" },</div><div class='del'>-	{ /* sentinel */ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const char * const qm_db_timeout[] = {</div><div class='hunk'>@@ -397,10 +417,6 @@ static const char * const qm_fifo_overflow[] = {</div><div class='ctx'> 	"cq", "eq", "aeq",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const char * const qp_s[] = {</div><div class='del'>-	"none", "init", "start", "stop", "close",</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct qm_typical_qos_table {</div><div class='ctx'> 	u32 start;</div><div class='ctx'> 	u32 end;</div><div class='hunk'>@@ -428,85 +444,6 @@ static struct qm_typical_qos_table shaper_cbs_s[] = {</div><div class='ctx'> </div><div class='ctx'> static void qm_irqs_unregister(struct hisi_qm *qm);</div><div class='ctx'> </div><div class='del'>-static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)</div><div class='del'>-{</div><div class='del'>-	enum qm_state curr = atomic_read(&amp;qm-&gt;status.flags);</div><div class='del'>-	bool avail = false;</div><div class='del'>-</div><div class='del'>-	switch (curr) {</div><div class='del'>-	case QM_INIT:</div><div class='del'>-		if (new == QM_START || new == QM_CLOSE)</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	case QM_START:</div><div class='del'>-		if (new == QM_STOP)</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	case QM_STOP:</div><div class='del'>-		if (new == QM_CLOSE || new == QM_START)</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;qm-&gt;pdev-&gt;dev, "change qm state from %s to %s\n",</div><div class='del'>-		qm_s[curr], qm_s[new]);</div><div class='del'>-</div><div class='del'>-	if (!avail)</div><div class='del'>-		dev_warn(&amp;qm-&gt;pdev-&gt;dev, "Can not change qm state from %s to %s\n",</div><div class='del'>-			 qm_s[curr], qm_s[new]);</div><div class='del'>-</div><div class='del'>-	return avail;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,</div><div class='del'>-			      enum qp_state new)</div><div class='del'>-{</div><div class='del'>-	enum qm_state qm_curr = atomic_read(&amp;qm-&gt;status.flags);</div><div class='del'>-	enum qp_state qp_curr = 0;</div><div class='del'>-	bool avail = false;</div><div class='del'>-</div><div class='del'>-	if (qp)</div><div class='del'>-		qp_curr = atomic_read(&amp;qp-&gt;qp_status.flags);</div><div class='del'>-</div><div class='del'>-	switch (new) {</div><div class='del'>-	case QP_INIT:</div><div class='del'>-		if (qm_curr == QM_START || qm_curr == QM_INIT)</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	case QP_START:</div><div class='del'>-		if ((qm_curr == QM_START &amp;&amp; qp_curr == QP_INIT) ||</div><div class='del'>-		    (qm_curr == QM_START &amp;&amp; qp_curr == QP_STOP))</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	case QP_STOP:</div><div class='del'>-		if ((qm_curr == QM_START &amp;&amp; qp_curr == QP_START) ||</div><div class='del'>-		    (qp_curr == QP_INIT))</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	case QP_CLOSE:</div><div class='del'>-		if ((qm_curr == QM_START &amp;&amp; qp_curr == QP_INIT) ||</div><div class='del'>-		    (qm_curr == QM_START &amp;&amp; qp_curr == QP_STOP) ||</div><div class='del'>-		    (qm_curr == QM_STOP &amp;&amp; qp_curr == QP_STOP)  ||</div><div class='del'>-		    (qm_curr == QM_STOP &amp;&amp; qp_curr == QP_INIT))</div><div class='del'>-			avail = true;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;qm-&gt;pdev-&gt;dev, "change qp state from %s to %s in QM %s\n",</div><div class='del'>-		qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);</div><div class='del'>-</div><div class='del'>-	if (!avail)</div><div class='del'>-		dev_warn(&amp;qm-&gt;pdev-&gt;dev,</div><div class='del'>-			 "Can not change qp state from %s to %s in QM %s\n",</div><div class='del'>-			 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);</div><div class='del'>-</div><div class='del'>-	return avail;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u32 qm_get_hw_error_status(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	return readl(qm-&gt;io_base + QM_ABNORMAL_INT_STATUS);</div><div class='hunk'>@@ -660,9 +597,6 @@ int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,</div><div class='ctx'> 	struct qm_mailbox mailbox;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(&amp;qm-&gt;pdev-&gt;dev, "QM mailbox request to q%u: %u-%llx\n",</div><div class='del'>-		queue, cmd, (unsigned long long)dma_addr);</div><div class='del'>-</div><div class='ctx'> 	qm_mb_pre_init(&amp;mailbox, cmd, dma_addr, queue, op);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;qm-&gt;mailbox_lock);</div><div class='hunk'>@@ -828,6 +762,40 @@ static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits,</div><div class='ctx'> 	*high_bits = (depth &gt;&gt; QM_XQ_DEPTH_SHIFT) &amp; QM_XQ_DEPTH_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,</div><div class='add'>+		     u32 dev_algs_size)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='add'>+	char *algs, *ptr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!qm-&gt;uacce)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (dev_algs_size &gt;= QM_DEV_ALG_MAX_LEN) {</div><div class='add'>+		dev_err(dev, "algs size %u is equal or larger than %d.\n",</div><div class='add'>+			dev_algs_size, QM_DEV_ALG_MAX_LEN);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);</div><div class='add'>+	if (!algs)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dev_algs_size; i++)</div><div class='add'>+		if (alg_msk &amp; dev_algs[i].alg_msk)</div><div class='add'>+			strcat(algs, dev_algs[i].alg);</div><div class='add'>+</div><div class='add'>+	ptr = strrchr(algs, '\n');</div><div class='add'>+	if (ptr) {</div><div class='add'>+		*ptr = '\0';</div><div class='add'>+		qm-&gt;uacce-&gt;algs = algs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(hisi_qm_set_algs);</div><div class='add'>+</div><div class='ctx'> static u32 qm_get_irq_num(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	if (qm-&gt;fun_type == QM_HW_PF)</div><div class='hunk'>@@ -1406,7 +1374,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)</div><div class='ctx'> {</div><div class='ctx'> 	const struct hisi_qm_hw_error *err;</div><div class='ctx'> 	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='del'>-	u32 reg_val, type, vf_num;</div><div class='add'>+	u32 reg_val, type, vf_num, qp_id;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(qm_hw_error); i++) {</div><div class='hunk'>@@ -1422,19 +1390,24 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)</div><div class='ctx'> 			type = (reg_val &amp; QM_DB_TIMEOUT_TYPE) &gt;&gt;</div><div class='ctx'> 			       QM_DB_TIMEOUT_TYPE_SHIFT;</div><div class='ctx'> 			vf_num = reg_val &amp; QM_DB_TIMEOUT_VF;</div><div class='del'>-			dev_err(dev, "qm %s doorbell timeout in function %u\n",</div><div class='del'>-				qm_db_timeout[type], vf_num);</div><div class='add'>+			qp_id = reg_val &gt;&gt; QM_DB_TIMEOUT_QP_SHIFT;</div><div class='add'>+			dev_err(dev, "qm %s doorbell timeout in function %u qp %u\n",</div><div class='add'>+				qm_db_timeout[type], vf_num, qp_id);</div><div class='ctx'> 		} else if (err-&gt;int_msk &amp; QM_OF_FIFO_OF) {</div><div class='ctx'> 			reg_val = readl(qm-&gt;io_base + QM_ABNORMAL_INF00);</div><div class='ctx'> 			type = (reg_val &amp; QM_FIFO_OVERFLOW_TYPE) &gt;&gt;</div><div class='ctx'> 			       QM_FIFO_OVERFLOW_TYPE_SHIFT;</div><div class='ctx'> 			vf_num = reg_val &amp; QM_FIFO_OVERFLOW_VF;</div><div class='del'>-</div><div class='add'>+			qp_id = reg_val &gt;&gt; QM_FIFO_OVERFLOW_QP_SHIFT;</div><div class='ctx'> 			if (type &lt; ARRAY_SIZE(qm_fifo_overflow))</div><div class='del'>-				dev_err(dev, "qm %s fifo overflow in function %u\n",</div><div class='del'>-					qm_fifo_overflow[type], vf_num);</div><div class='add'>+				dev_err(dev, "qm %s fifo overflow in function %u qp %u\n",</div><div class='add'>+					qm_fifo_overflow[type], vf_num, qp_id);</div><div class='ctx'> 			else</div><div class='ctx'> 				dev_err(dev, "unknown error type\n");</div><div class='add'>+		} else if (err-&gt;int_msk &amp; QM_AXI_RRESP_ERR) {</div><div class='add'>+			reg_val = readl(qm-&gt;io_base + QM_ABNORMAL_INF02);</div><div class='add'>+			if (reg_val &amp; QM_AXI_POISON_ERR)</div><div class='add'>+				dev_err(dev, "qm axi poison error happened\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1843,8 +1816,10 @@ static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)</div><div class='ctx'> 	struct hisi_qp *qp;</div><div class='ctx'> 	int qp_id;</div><div class='ctx'> </div><div class='del'>-	if (!qm_qp_avail_state(qm, NULL, QP_INIT))</div><div class='add'>+	if (atomic_read(&amp;qm-&gt;status.flags) == QM_STOP) {</div><div class='add'>+		dev_info_ratelimited(dev, "failed to create qp as qm is stop!\n");</div><div class='ctx'> 		return ERR_PTR(-EPERM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (qm-&gt;qp_in_used == qm-&gt;qp_num) {</div><div class='ctx'> 		dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",</div><div class='hunk'>@@ -1871,7 +1846,6 @@ static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)</div><div class='ctx'> 	qp-&gt;alg_type = alg_type;</div><div class='ctx'> 	qp-&gt;is_in_kernel = true;</div><div class='ctx'> 	qm-&gt;qp_in_used++;</div><div class='del'>-	atomic_set(&amp;qp-&gt;qp_status.flags, QP_INIT);</div><div class='ctx'> </div><div class='ctx'> 	return qp;</div><div class='ctx'> }</div><div class='hunk'>@@ -1914,11 +1888,6 @@ static void hisi_qm_release_qp(struct hisi_qp *qp)</div><div class='ctx'> </div><div class='ctx'> 	down_write(&amp;qm-&gt;qps_lock);</div><div class='ctx'> </div><div class='del'>-	if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {</div><div class='del'>-		up_write(&amp;qm-&gt;qps_lock);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	qm-&gt;qp_in_used--;</div><div class='ctx'> 	idr_remove(&amp;qm-&gt;qp_idr, qp-&gt;qp_id);</div><div class='ctx'> </div><div class='hunk'>@@ -1966,6 +1935,11 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)</div><div class='ctx'> 		cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp-&gt;cq_depth));</div><div class='ctx'> 		cqc.w8 = 0; /* rand_qc */</div><div class='ctx'> 	}</div><div class='add'>+	/*</div><div class='add'>+	 * Enable request finishing interrupts defaultly.</div><div class='add'>+	 * So, there will be some interrupts until disabling</div><div class='add'>+	 * this.</div><div class='add'>+	 */</div><div class='ctx'> 	cqc.dw6 = cpu_to_le32(1 &lt;&lt; QM_CQ_PHASE_SHIFT | 1 &lt;&lt; QM_CQ_FLAG_SHIFT);</div><div class='ctx'> 	cqc.base_l = cpu_to_le32(lower_32_bits(qp-&gt;cqe_dma));</div><div class='ctx'> 	cqc.base_h = cpu_to_le32(upper_32_bits(qp-&gt;cqe_dma));</div><div class='hunk'>@@ -1998,8 +1972,10 @@ static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)</div><div class='ctx'> 	u32 pasid = arg;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!qm_qp_avail_state(qm, qp, QP_START))</div><div class='add'>+	if (atomic_read(&amp;qm-&gt;status.flags) == QM_STOP) {</div><div class='add'>+		dev_info_ratelimited(dev, "failed to start qp as qm is stop!\n");</div><div class='ctx'> 		return -EPERM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = qm_qp_ctx_cfg(qp, qp_id, pasid);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -2121,21 +2097,17 @@ static int qm_stop_qp_nolock(struct hisi_qp *qp)</div><div class='ctx'> 	 * is_resetting flag should be set negative so that this qp will not</div><div class='ctx'> 	 * be restarted after reset.</div><div class='ctx'> 	 */</div><div class='del'>-	if (atomic_read(&amp;qp-&gt;qp_status.flags) == QP_STOP) {</div><div class='add'>+	if (atomic_read(&amp;qp-&gt;qp_status.flags) != QP_START) {</div><div class='ctx'> 		qp-&gt;is_resetting = false;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!qm_qp_avail_state(qp-&gt;qm, qp, QP_STOP))</div><div class='del'>-		return -EPERM;</div><div class='del'>-</div><div class='ctx'> 	atomic_set(&amp;qp-&gt;qp_status.flags, QP_STOP);</div><div class='ctx'> </div><div class='ctx'> 	ret = qm_drain_qp(qp);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		dev_err(dev, "Failed to drain out data for stopping!\n");</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	flush_workqueue(qp-&gt;qm-&gt;wq);</div><div class='ctx'> 	if (unlikely(qp-&gt;is_resetting &amp;&amp; atomic_read(&amp;qp-&gt;qp_status.used)))</div><div class='ctx'> 		qp_stop_fail_cb(qp);</div><div class='hunk'>@@ -2855,13 +2827,8 @@ void hisi_qm_uninit(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	qm_cmd_uninit(qm);</div><div class='ctx'> 	hisi_qm_unint_work(qm);</div><div class='del'>-	down_write(&amp;qm-&gt;qps_lock);</div><div class='del'>-</div><div class='del'>-	if (!qm_avail_state(qm, QM_CLOSE)) {</div><div class='del'>-		up_write(&amp;qm-&gt;qps_lock);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='add'>+	down_write(&amp;qm-&gt;qps_lock);</div><div class='ctx'> 	hisi_qm_memory_uninit(qm);</div><div class='ctx'> 	hisi_qm_set_state(qm, QM_NOT_READY);</div><div class='ctx'> 	up_write(&amp;qm-&gt;qps_lock);</div><div class='hunk'>@@ -3035,11 +3002,6 @@ int hisi_qm_start(struct hisi_qm *qm)</div><div class='ctx'> </div><div class='ctx'> 	down_write(&amp;qm-&gt;qps_lock);</div><div class='ctx'> </div><div class='del'>-	if (!qm_avail_state(qm, QM_START)) {</div><div class='del'>-		up_write(&amp;qm-&gt;qps_lock);</div><div class='del'>-		return -EPERM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	dev_dbg(dev, "qm start with %u queue pairs\n", qm-&gt;qp_num);</div><div class='ctx'> </div><div class='ctx'> 	if (!qm-&gt;qp_num) {</div><div class='hunk'>@@ -3049,10 +3011,12 @@ int hisi_qm_start(struct hisi_qm *qm)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = __hisi_qm_start(qm);</div><div class='del'>-	if (!ret)</div><div class='del'>-		atomic_set(&amp;qm-&gt;status.flags, QM_START);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_unlock;</div><div class='ctx'> </div><div class='add'>+	atomic_set(&amp;qm-&gt;status.flags, QM_WORK);</div><div class='ctx'> 	hisi_qm_set_state(qm, QM_READY);</div><div class='add'>+</div><div class='ctx'> err_unlock:</div><div class='ctx'> 	up_write(&amp;qm-&gt;qps_lock);</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -3149,10 +3113,11 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)</div><div class='ctx'> 	down_write(&amp;qm-&gt;qps_lock);</div><div class='ctx'> </div><div class='ctx'> 	qm-&gt;status.stop_reason = r;</div><div class='del'>-	if (!qm_avail_state(qm, QM_STOP)) {</div><div class='del'>-		ret = -EPERM;</div><div class='add'>+	if (atomic_read(&amp;qm-&gt;status.flags) == QM_STOP)</div><div class='ctx'> 		goto err_unlock;</div><div class='del'>-	}</div><div class='add'>+</div><div class='add'>+	/* Stop all the request sending at first. */</div><div class='add'>+	atomic_set(&amp;qm-&gt;status.flags, QM_STOP);</div><div class='ctx'> </div><div class='ctx'> 	if (qm-&gt;status.stop_reason == QM_SOFT_RESET ||</div><div class='ctx'> 	    qm-&gt;status.stop_reason == QM_DOWN) {</div><div class='hunk'>@@ -3176,7 +3141,6 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	qm_clear_queues(qm);</div><div class='del'>-	atomic_set(&amp;qm-&gt;status.flags, QM_STOP);</div><div class='ctx'> </div><div class='ctx'> err_unlock:</div><div class='ctx'> 	up_write(&amp;qm-&gt;qps_lock);</div><div class='hunk'>@@ -3966,6 +3930,11 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set)</div><div class='ctx'> 	int pos;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Since function qm_set_vf_mse is called only after SRIOV is enabled,</div><div class='add'>+	 * pci_find_ext_capability cannot return 0, pos does not need to be</div><div class='add'>+	 * checked.</div><div class='add'>+	 */</div><div class='ctx'> 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);</div><div class='ctx'> 	pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &amp;sriov_ctrl);</div><div class='ctx'> 	if (set)</div><div class='hunk'>@@ -4816,7 +4785,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm *qm)</div><div class='ctx'> 	if (qm-&gt;fun_type == QM_HW_VF)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_ABN_IRQ_TYPE_MASK))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -4833,7 +4802,7 @@ static int qm_register_abnormal_irq(struct hisi_qm *qm)</div><div class='ctx'> 	if (qm-&gt;fun_type == QM_HW_VF)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_ABN_IRQ_TYPE_MASK))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -4850,7 +4819,7 @@ static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm)</div><div class='ctx'> 	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -4864,7 +4833,7 @@ static int qm_register_mb_cmd_irq(struct hisi_qm *qm)</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -4881,7 +4850,7 @@ static void qm_unregister_aeq_irq(struct hisi_qm *qm)</div><div class='ctx'> 	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -4895,7 +4864,7 @@ static int qm_register_aeq_irq(struct hisi_qm *qm)</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -4913,7 +4882,7 @@ static void qm_unregister_eq_irq(struct hisi_qm *qm)</div><div class='ctx'> 	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -4927,7 +4896,7 @@ static int qm_register_eq_irq(struct hisi_qm *qm)</div><div class='ctx'> 	u32 irq_vector, val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm-&gt;cap_ver);</div><div class='add'>+	val = qm-&gt;cap_tables.qm_cap_table[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;</div><div class='ctx'> 	if (!((val &gt;&gt; QM_IRQ_TYPE_SHIFT) &amp; QM_IRQ_TYPE_MASK))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -5015,7 +4984,29 @@ static int qm_get_qp_num(struct hisi_qm *qm)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void qm_get_hw_caps(struct hisi_qm *qm)</div><div class='add'>+static int qm_pre_store_irq_type_caps(struct hisi_qm *qm)</div><div class='add'>+{</div><div class='add'>+	struct hisi_qm_cap_record *qm_cap;</div><div class='add'>+	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='add'>+	size_t i, size;</div><div class='add'>+</div><div class='add'>+	size = ARRAY_SIZE(qm_pre_store_caps);</div><div class='add'>+	qm_cap = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*qm_cap) * size, GFP_KERNEL);</div><div class='add'>+	if (!qm_cap)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; size; i++) {</div><div class='add'>+		qm_cap[i].type = qm_pre_store_caps[i];</div><div class='add'>+		qm_cap[i].cap_val = hisi_qm_get_hw_info(qm, qm_basic_info,</div><div class='add'>+							qm_pre_store_caps[i], qm-&gt;cap_ver);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	qm-&gt;cap_tables.qm_cap_table = qm_cap;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int qm_get_hw_caps(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='ctx'> 	const struct hisi_qm_cap_info *cap_info = qm-&gt;fun_type == QM_HW_PF ?</div><div class='ctx'> 						  qm_cap_info_pf : qm_cap_info_vf;</div><div class='hunk'>@@ -5046,6 +5037,9 @@ static void qm_get_hw_caps(struct hisi_qm *qm)</div><div class='ctx'> 		if (val)</div><div class='ctx'> 			set_bit(cap_info[i].type, &amp;qm-&gt;caps);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/* Fetch and save the value of irq type related capability registers */</div><div class='add'>+	return qm_pre_store_irq_type_caps(qm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qm_get_pci_res(struct hisi_qm *qm)</div><div class='hunk'>@@ -5067,7 +5061,10 @@ static int qm_get_pci_res(struct hisi_qm *qm)</div><div class='ctx'> 		goto err_request_mem_regions;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	qm_get_hw_caps(qm);</div><div class='add'>+	ret = qm_get_hw_caps(qm);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_ioremap;</div><div class='add'>+</div><div class='ctx'> 	if (test_bit(QM_SUPPORT_DB_ISOLATION, &amp;qm-&gt;caps)) {</div><div class='ctx'> 		qm-&gt;db_interval = QM_QP_DB_INTERVAL;</div><div class='ctx'> 		qm-&gt;db_phys_base = pci_resource_start(pdev, PCI_BAR_4);</div><div class='hunk'>@@ -5340,7 +5337,6 @@ int hisi_qm_init(struct hisi_qm *qm)</div><div class='ctx'> 		goto err_free_qm_memory;</div><div class='ctx'> </div><div class='ctx'> 	qm_cmd_init(qm);</div><div class='del'>-	atomic_set(&amp;qm-&gt;status.flags, QM_INIT);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/hisilicon/qm_common.h b/drivers/crypto/hisilicon/qm_common.h<br/>index 7b0b15c83ec1..0760bf55f13e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/qm_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/qm_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/qm_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/qm_common.h</a></div><div class='hunk'>@@ -72,10 +72,6 @@ struct qm_aeqc {</div><div class='ctx'> 	__le32 dw6;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const char * const qm_s[] = {</div><div class='del'>-	"init", "start", "close", "stop",</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op);</div><div class='ctx'> void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);</div><div class='ctx'> void hisi_qm_set_algqos_init(struct hisi_qm *qm);</div><div class='head'>diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h<br/>index 3e57fc04b377..410c83712e28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/sec2/sec.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec.h</a></div><div class='hunk'>@@ -220,6 +220,13 @@ enum sec_cap_type {</div><div class='ctx'> 	SEC_CORE4_ALG_BITMAP_HIGH,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum sec_cap_reg_record_idx {</div><div class='add'>+	SEC_DRV_ALG_BITMAP_LOW_IDX = 0x0,</div><div class='add'>+	SEC_DRV_ALG_BITMAP_HIGH_IDX,</div><div class='add'>+	SEC_DEV_ALG_BITMAP_LOW_IDX,</div><div class='add'>+	SEC_DEV_ALG_BITMAP_HIGH_IDX,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> void sec_destroy_qps(struct hisi_qp **qps, int qp_num);</div><div class='ctx'> struct hisi_qp **sec_create_qps(void);</div><div class='ctx'> int sec_register_to_crypto(struct hisi_qm *qm);</div><div class='head'>diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c<br/>index 6fcabbc87860..f028dcfd0ead 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_crypto.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/sec2/sec_crypto.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_crypto.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_crypto.c</a></div><div class='hunk'>@@ -850,6 +850,7 @@ static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key,</div><div class='ctx'> 		ret = sec_skcipher_aes_sm4_setkey(c_ctx, keylen, c_mode);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='add'>+		dev_err(dev, "sec c_alg err!\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -879,15 +880,11 @@ static int sec_setkey_##name(struct crypto_skcipher *tfm, const u8 *key,\</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(aes_ecb, SEC_CALG_AES, SEC_CMODE_ECB)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(aes_cbc, SEC_CALG_AES, SEC_CMODE_CBC)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(aes_xts, SEC_CALG_AES, SEC_CMODE_XTS)</div><div class='del'>-GEN_SEC_SETKEY_FUNC(aes_ofb, SEC_CALG_AES, SEC_CMODE_OFB)</div><div class='del'>-GEN_SEC_SETKEY_FUNC(aes_cfb, SEC_CALG_AES, SEC_CMODE_CFB)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(aes_ctr, SEC_CALG_AES, SEC_CMODE_CTR)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(3des_ecb, SEC_CALG_3DES, SEC_CMODE_ECB)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(3des_cbc, SEC_CALG_3DES, SEC_CMODE_CBC)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(sm4_xts, SEC_CALG_SM4, SEC_CMODE_XTS)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(sm4_cbc, SEC_CALG_SM4, SEC_CMODE_CBC)</div><div class='del'>-GEN_SEC_SETKEY_FUNC(sm4_ofb, SEC_CALG_SM4, SEC_CMODE_OFB)</div><div class='del'>-GEN_SEC_SETKEY_FUNC(sm4_cfb, SEC_CALG_SM4, SEC_CMODE_CFB)</div><div class='ctx'> GEN_SEC_SETKEY_FUNC(sm4_ctr, SEC_CALG_SM4, SEC_CMODE_CTR)</div><div class='ctx'> </div><div class='ctx'> static int sec_cipher_pbuf_map(struct sec_ctx *ctx, struct sec_req *req,</div><div class='hunk'>@@ -1176,7 +1173,8 @@ static int sec_aead_setkey(struct crypto_aead *tfm, const u8 *key,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (crypto_authenc_extractkeys(&amp;keys, key, keylen))</div><div class='add'>+	ret = crypto_authenc_extractkeys(&amp;keys, key, keylen);</div><div class='add'>+	if (ret)</div><div class='ctx'> 		goto bad_key;</div><div class='ctx'> </div><div class='ctx'> 	ret = sec_aead_aes_set_key(c_ctx, &amp;keys);</div><div class='hunk'>@@ -1193,6 +1191,7 @@ static int sec_aead_setkey(struct crypto_aead *tfm, const u8 *key,</div><div class='ctx'> </div><div class='ctx'> 	if ((ctx-&gt;a_ctx.mac_len &amp; SEC_SQE_LEN_RATE_MASK)  ||</div><div class='ctx'> 	    (ctx-&gt;a_ctx.a_key_len &amp; SEC_SQE_LEN_RATE_MASK)) {</div><div class='add'>+		ret = -EINVAL;</div><div class='ctx'> 		dev_err(dev, "MAC or AUTH key length error!\n");</div><div class='ctx'> 		goto bad_key;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1201,7 +1200,7 @@ static int sec_aead_setkey(struct crypto_aead *tfm, const u8 *key,</div><div class='ctx'> </div><div class='ctx'> bad_key:</div><div class='ctx'> 	memzero_explicit(&amp;keys, sizeof(struct crypto_authenc_keys));</div><div class='del'>-	return -EINVAL;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -2032,8 +2031,6 @@ static int sec_skcipher_cryptlen_check(struct sec_ctx *ctx,</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='del'>-	case SEC_CMODE_CFB:</div><div class='del'>-	case SEC_CMODE_OFB:</div><div class='ctx'> 	case SEC_CMODE_CTR:</div><div class='ctx'> 		if (unlikely(ctx-&gt;sec-&gt;qm.ver &lt; QM_HW_V3)) {</div><div class='ctx'> 			dev_err(dev, "skcipher HW version error!\n");</div><div class='hunk'>@@ -2198,16 +2195,6 @@ static struct sec_skcipher sec_skciphers[] = {</div><div class='ctx'> 					SEC_XTS_MAX_KEY_SIZE, AES_BLOCK_SIZE, AES_BLOCK_SIZE),</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.alg_msk = BIT(4),</div><div class='del'>-		.alg = SEC_SKCIPHER_ALG("ofb(aes)", sec_setkey_aes_ofb,	AES_MIN_KEY_SIZE,</div><div class='del'>-					AES_MAX_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg_msk = BIT(5),</div><div class='del'>-		.alg = SEC_SKCIPHER_ALG("cfb(aes)", sec_setkey_aes_cfb,	AES_MIN_KEY_SIZE,</div><div class='del'>-					AES_MAX_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.alg_msk = BIT(12),</div><div class='ctx'> 		.alg = SEC_SKCIPHER_ALG("cbc(sm4)", sec_setkey_sm4_cbc,	AES_MIN_KEY_SIZE,</div><div class='ctx'> 					AES_MIN_KEY_SIZE, AES_BLOCK_SIZE, AES_BLOCK_SIZE),</div><div class='hunk'>@@ -2223,16 +2210,6 @@ static struct sec_skcipher sec_skciphers[] = {</div><div class='ctx'> 					SEC_XTS_MIN_KEY_SIZE, AES_BLOCK_SIZE, AES_BLOCK_SIZE),</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.alg_msk = BIT(15),</div><div class='del'>-		.alg = SEC_SKCIPHER_ALG("ofb(sm4)", sec_setkey_sm4_ofb,	AES_MIN_KEY_SIZE,</div><div class='del'>-					AES_MIN_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.alg_msk = BIT(16),</div><div class='del'>-		.alg = SEC_SKCIPHER_ALG("cfb(sm4)", sec_setkey_sm4_cfb,	AES_MIN_KEY_SIZE,</div><div class='del'>-					AES_MIN_KEY_SIZE, SEC_MIN_BLOCK_SZ, AES_BLOCK_SIZE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.alg_msk = BIT(23),</div><div class='ctx'> 		.alg = SEC_SKCIPHER_ALG("ecb(des3_ede)", sec_setkey_3des_ecb, SEC_DES3_3KEY_SIZE,</div><div class='ctx'> 					SEC_DES3_3KEY_SIZE, DES3_EDE_BLOCK_SIZE, 0),</div><div class='hunk'>@@ -2547,9 +2524,12 @@ err:</div><div class='ctx'> </div><div class='ctx'> int sec_register_to_crypto(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);</div><div class='add'>+	u64 alg_mask;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,</div><div class='add'>+				      SEC_DRV_ALG_BITMAP_LOW_IDX);</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;sec_algs_lock);</div><div class='ctx'> 	if (sec_available_devs) {</div><div class='ctx'> 		sec_available_devs++;</div><div class='hunk'>@@ -2578,7 +2558,10 @@ unlock:</div><div class='ctx'> </div><div class='ctx'> void sec_unregister_from_crypto(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);</div><div class='add'>+	u64 alg_mask;</div><div class='add'>+</div><div class='add'>+	alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,</div><div class='add'>+				      SEC_DRV_ALG_BITMAP_LOW_IDX);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;sec_algs_lock);</div><div class='ctx'> 	if (--sec_available_devs)</div><div class='head'>diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.h b/drivers/crypto/hisilicon/sec2/sec_crypto.h<br/>index d033f63b583f..27a0ee5ad913 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_crypto.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/sec2/sec_crypto.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_crypto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_crypto.h</a></div><div class='hunk'>@@ -37,8 +37,6 @@ enum sec_mac_len {</div><div class='ctx'> enum sec_cmode {</div><div class='ctx'> 	SEC_CMODE_ECB    = 0x0,</div><div class='ctx'> 	SEC_CMODE_CBC    = 0x1,</div><div class='del'>-	SEC_CMODE_CFB    = 0x2,</div><div class='del'>-	SEC_CMODE_OFB    = 0x3,</div><div class='ctx'> 	SEC_CMODE_CTR    = 0x4,</div><div class='ctx'> 	SEC_CMODE_CCM    = 0x5,</div><div class='ctx'> 	SEC_CMODE_GCM    = 0x6,</div><div class='head'>diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c<br/>index 0e56a47eb862..7bb99381bbdf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/sec2/sec_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sec2/sec_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sec2/sec_main.c</a></div><div class='hunk'>@@ -120,7 +120,6 @@</div><div class='ctx'> 					GENMASK_ULL(42, 25))</div><div class='ctx'> #define SEC_AEAD_BITMAP			(GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \</div><div class='ctx'> 					GENMASK_ULL(45, 43))</div><div class='del'>-#define SEC_DEV_ALG_MAX_LEN		256</div><div class='ctx'> </div><div class='ctx'> struct sec_hw_error {</div><div class='ctx'> 	u32 int_msk;</div><div class='hunk'>@@ -132,11 +131,6 @@ struct sec_dfx_item {</div><div class='ctx'> 	u32 offset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct sec_dev_alg {</div><div class='del'>-	u64 alg_msk;</div><div class='del'>-	const char *algs;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const char sec_name[] = "hisi_sec2";</div><div class='ctx'> static struct dentry *sec_debugfs_root;</div><div class='ctx'> </div><div class='hunk'>@@ -159,7 +153,7 @@ static const struct hisi_qm_cap_info sec_basic_info[] = {</div><div class='ctx'> 	{SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},</div><div class='ctx'> 	{SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},</div><div class='ctx'> 	{SEC_CORE_ENABLE_BITMAP, 0x3140, 32, GENMASK(31, 0), 0x17F, 0x17F, 0xF},</div><div class='del'>-	{SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x187F0FF},</div><div class='add'>+	{SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF},</div><div class='ctx'> 	{SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},</div><div class='ctx'> 	{SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},</div><div class='ctx'> 	{SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},</div><div class='hunk'>@@ -173,15 +167,22 @@ static const struct hisi_qm_cap_info sec_basic_info[] = {</div><div class='ctx'> 	{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct sec_dev_alg sec_dev_algs[] = { {</div><div class='add'>+static const u32 sec_pre_store_caps[] = {</div><div class='add'>+	SEC_DRV_ALG_BITMAP_LOW,</div><div class='add'>+	SEC_DRV_ALG_BITMAP_HIGH,</div><div class='add'>+	SEC_DEV_ALG_BITMAP_LOW,</div><div class='add'>+	SEC_DEV_ALG_BITMAP_HIGH,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qm_dev_alg sec_dev_algs[] = { {</div><div class='ctx'> 		.alg_msk = SEC_CIPHER_BITMAP,</div><div class='del'>-		.algs = "cipher\n",</div><div class='add'>+		.alg = "cipher\n",</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.alg_msk = SEC_DIGEST_BITMAP,</div><div class='del'>-		.algs = "digest\n",</div><div class='add'>+		.alg = "digest\n",</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.alg_msk = SEC_AEAD_BITMAP,</div><div class='del'>-		.algs = "aead\n",</div><div class='add'>+		.alg = "aead\n",</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -394,8 +395,8 @@ u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)</div><div class='ctx'> {</div><div class='ctx'> 	u32 cap_val_h, cap_val_l;</div><div class='ctx'> </div><div class='del'>-	cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm-&gt;cap_ver);</div><div class='del'>-	cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm-&gt;cap_ver);</div><div class='add'>+	cap_val_h = qm-&gt;cap_tables.dev_cap_table[high].cap_val;</div><div class='add'>+	cap_val_l = qm-&gt;cap_tables.dev_cap_table[low].cap_val;</div><div class='ctx'> </div><div class='ctx'> 	return ((u64)cap_val_h &lt;&lt; SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;</div><div class='ctx'> }</div><div class='hunk'>@@ -1077,37 +1078,31 @@ static int sec_pf_probe_init(struct sec_dev *sec)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sec_set_qm_algs(struct hisi_qm *qm)</div><div class='add'>+static int sec_pre_store_cap_reg(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='del'>-	char *algs, *ptr;</div><div class='del'>-	u64 alg_mask;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!qm-&gt;use_sva)</div><div class='del'>-		return 0;</div><div class='add'>+	struct hisi_qm_cap_record *sec_cap;</div><div class='add'>+	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='add'>+	size_t i, size;</div><div class='ctx'> </div><div class='del'>-	algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);</div><div class='del'>-	if (!algs)</div><div class='add'>+	size = ARRAY_SIZE(sec_pre_store_caps);</div><div class='add'>+	sec_cap = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*sec_cap) * size, GFP_KERNEL);</div><div class='add'>+	if (!sec_cap)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(sec_dev_algs); i++)</div><div class='del'>-		if (alg_mask &amp; sec_dev_algs[i].alg_msk)</div><div class='del'>-			strcat(algs, sec_dev_algs[i].algs);</div><div class='del'>-</div><div class='del'>-	ptr = strrchr(algs, '\n');</div><div class='del'>-	if (ptr)</div><div class='del'>-		*ptr = '\0';</div><div class='add'>+	for (i = 0; i &lt; size; i++) {</div><div class='add'>+		sec_cap[i].type = sec_pre_store_caps[i];</div><div class='add'>+		sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info,</div><div class='add'>+				     sec_pre_store_caps[i], qm-&gt;cap_ver);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	qm-&gt;uacce-&gt;algs = algs;</div><div class='add'>+	qm-&gt;cap_tables.dev_cap_table = sec_cap;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='add'>+	u64 alg_msk;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	qm-&gt;pdev = pdev;</div><div class='hunk'>@@ -1142,7 +1137,16 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = sec_set_qm_algs(qm);</div><div class='add'>+	/* Fetch and save the value of capability registers */</div><div class='add'>+	ret = sec_pre_store_cap_reg(qm);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pci_err(qm-&gt;pdev, "Failed to pre-store capability registers!\n");</div><div class='add'>+		hisi_qm_uninit(qm);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX);</div><div class='add'>+	ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pci_err(qm-&gt;pdev, "Failed to set sec algs!\n");</div><div class='ctx'> 		hisi_qm_uninit(qm);</div><div class='head'>diff --git a/drivers/crypto/hisilicon/sgl.c b/drivers/crypto/hisilicon/sgl.c<br/>index 3df7a256e919..0beca257c20b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sgl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/sgl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/sgl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/sgl.c</a></div><div class='hunk'>@@ -70,11 +70,11 @@ struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,</div><div class='ctx'> 			 HISI_ACC_SGL_ALIGN_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * the pool may allocate a block of memory of size PAGE_SIZE * 2^MAX_ORDER,</div><div class='add'>+	 * the pool may allocate a block of memory of size PAGE_SIZE * 2^MAX_PAGE_ORDER,</div><div class='ctx'> 	 * block size may exceed 2^31 on ia64, so the max of block size is 2^31</div><div class='ctx'> 	 */</div><div class='del'>-	block_size = 1 &lt;&lt; (PAGE_SHIFT + MAX_ORDER &lt; 32 ?</div><div class='del'>-			   PAGE_SHIFT + MAX_ORDER : 31);</div><div class='add'>+	block_size = 1 &lt;&lt; (PAGE_SHIFT + MAX_PAGE_ORDER &lt; 32 ?</div><div class='add'>+			   PAGE_SHIFT + MAX_PAGE_ORDER : 31);</div><div class='ctx'> 	sgl_num_per_block = block_size / sgl_size;</div><div class='ctx'> 	block_num = count / sgl_num_per_block;</div><div class='ctx'> 	remain_sgl = count % sgl_num_per_block;</div><div class='hunk'>@@ -121,10 +121,10 @@ struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,</div><div class='ctx'> 	return pool;</div><div class='ctx'> </div><div class='ctx'> err_free_mem:</div><div class='del'>-	for (j = 0; j &lt; i; j++) {</div><div class='add'>+	for (j = 0; j &lt; i; j++)</div><div class='ctx'> 		dma_free_coherent(dev, block_size, block[j].sgl,</div><div class='ctx'> 				  block[j].sgl_dma);</div><div class='del'>-	}</div><div class='add'>+</div><div class='ctx'> 	kfree_sensitive(pool);</div><div class='ctx'> 	return ERR_PTR(-ENOMEM);</div><div class='ctx'> }</div><div class='hunk'>@@ -140,7 +140,7 @@ EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);</div><div class='ctx'> void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_block *block;</div><div class='del'>-	int i;</div><div class='add'>+	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	if (!dev || !pool)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -196,9 +196,10 @@ static void update_hw_sgl_sum_sge(struct hisi_acc_hw_sgl *hw_sgl, u16 sum)</div><div class='ctx'> static void clear_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)</div><div class='ctx'> {</div><div class='ctx'> 	struct acc_hw_sge *hw_sge = hw_sgl-&gt;sge_entries;</div><div class='add'>+	u16 entry_sum = le16_to_cpu(hw_sgl-&gt;entry_sum_in_sgl);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; le16_to_cpu(hw_sgl-&gt;entry_sum_in_sgl); i++) {</div><div class='add'>+	for (i = 0; i &lt; entry_sum; i++) {</div><div class='ctx'> 		hw_sge[i].page_ctrl = NULL;</div><div class='ctx'> 		hw_sge[i].buf = 0;</div><div class='ctx'> 		hw_sge[i].len = 0;</div><div class='hunk'>@@ -223,10 +224,11 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,</div><div class='ctx'> 			      u32 index, dma_addr_t *hw_sgl_dma)</div><div class='ctx'> {</div><div class='ctx'> 	struct hisi_acc_hw_sgl *curr_hw_sgl;</div><div class='add'>+	unsigned int i, sg_n_mapped;</div><div class='ctx'> 	dma_addr_t curr_sgl_dma = 0;</div><div class='ctx'> 	struct acc_hw_sge *curr_hw_sge;</div><div class='ctx'> 	struct scatterlist *sg;</div><div class='del'>-	int i, sg_n, sg_n_mapped;</div><div class='add'>+	int sg_n;</div><div class='ctx'> </div><div class='ctx'> 	if (!dev || !sgl || !pool || !hw_sgl_dma)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='head'>diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisilicon/zip/zip_main.c<br/>index db4c964cd649..479ba8a1d6b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/zip/zip_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/hisilicon/zip/zip_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/hisilicon/zip/zip_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/hisilicon/zip/zip_main.c</a></div><div class='hunk'>@@ -74,7 +74,6 @@</div><div class='ctx'> #define HZIP_AXI_SHUTDOWN_ENABLE	BIT(14)</div><div class='ctx'> #define HZIP_WR_PORT			BIT(11)</div><div class='ctx'> </div><div class='del'>-#define HZIP_DEV_ALG_MAX_LEN		256</div><div class='ctx'> #define HZIP_ALG_ZLIB_BIT		GENMASK(1, 0)</div><div class='ctx'> #define HZIP_ALG_GZIP_BIT		GENMASK(3, 2)</div><div class='ctx'> #define HZIP_ALG_DEFLATE_BIT		GENMASK(5, 4)</div><div class='hunk'>@@ -107,6 +106,14 @@</div><div class='ctx'> #define HZIP_CLOCK_GATED_EN		(HZIP_CORE_GATED_EN | \</div><div class='ctx'> 					 HZIP_CORE_GATED_OOO_EN)</div><div class='ctx'> </div><div class='add'>+/* zip comp high performance */</div><div class='add'>+#define HZIP_HIGH_PERF_OFFSET		0x301208</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	HZIP_HIGH_COMP_RATE,</div><div class='add'>+	HZIP_HIGH_COMP_PERF,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const char hisi_zip_name[] = "hisi_zip";</div><div class='ctx'> static struct dentry *hzip_debugfs_root;</div><div class='ctx'> </div><div class='hunk'>@@ -120,23 +127,18 @@ struct zip_dfx_item {</div><div class='ctx'> 	u32 offset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct zip_dev_alg {</div><div class='del'>-	u32 alg_msk;</div><div class='del'>-	const char *algs;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct zip_dev_alg zip_dev_algs[] = { {</div><div class='add'>+static const struct qm_dev_alg zip_dev_algs[] = { {</div><div class='ctx'> 		.alg_msk = HZIP_ALG_ZLIB_BIT,</div><div class='del'>-		.algs = "zlib\n",</div><div class='add'>+		.alg = "zlib\n",</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.alg_msk = HZIP_ALG_GZIP_BIT,</div><div class='del'>-		.algs = "gzip\n",</div><div class='add'>+		.alg = "gzip\n",</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.alg_msk = HZIP_ALG_DEFLATE_BIT,</div><div class='del'>-		.algs = "deflate\n",</div><div class='add'>+		.alg = "deflate\n",</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.alg_msk = HZIP_ALG_LZ77_BIT,</div><div class='del'>-		.algs = "lz77_zstd\n",</div><div class='add'>+		.alg = "lz77_zstd\n",</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -247,6 +249,26 @@ static struct hisi_qm_cap_info zip_basic_cap_info[] = {</div><div class='ctx'> 	{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum zip_pre_store_cap_idx {</div><div class='add'>+	ZIP_CORE_NUM_CAP_IDX = 0x0,</div><div class='add'>+	ZIP_CLUSTER_COMP_NUM_CAP_IDX,</div><div class='add'>+	ZIP_CLUSTER_DECOMP_NUM_CAP_IDX,</div><div class='add'>+	ZIP_DECOMP_ENABLE_BITMAP_IDX,</div><div class='add'>+	ZIP_COMP_ENABLE_BITMAP_IDX,</div><div class='add'>+	ZIP_DRV_ALG_BITMAP_IDX,</div><div class='add'>+	ZIP_DEV_ALG_BITMAP_IDX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 zip_pre_store_caps[] = {</div><div class='add'>+	ZIP_CORE_NUM_CAP,</div><div class='add'>+	ZIP_CLUSTER_COMP_NUM_CAP,</div><div class='add'>+	ZIP_CLUSTER_DECOMP_NUM_CAP,</div><div class='add'>+	ZIP_DECOMP_ENABLE_BITMAP,</div><div class='add'>+	ZIP_COMP_ENABLE_BITMAP,</div><div class='add'>+	ZIP_DRV_ALG_BITMAP,</div><div class='add'>+	ZIP_DEV_ALG_BITMAP,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum {</div><div class='ctx'> 	HZIP_COMP_CORE0,</div><div class='ctx'> 	HZIP_COMP_CORE1,</div><div class='hunk'>@@ -270,28 +292,28 @@ static const u64 core_offsets[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct debugfs_reg32 hzip_dfx_regs[] = {</div><div class='del'>-	{"HZIP_GET_BD_NUM                ",  0x00ull},</div><div class='del'>-	{"HZIP_GET_RIGHT_BD              ",  0x04ull},</div><div class='del'>-	{"HZIP_GET_ERROR_BD              ",  0x08ull},</div><div class='del'>-	{"HZIP_DONE_BD_NUM               ",  0x0cull},</div><div class='del'>-	{"HZIP_WORK_CYCLE                ",  0x10ull},</div><div class='del'>-	{"HZIP_IDLE_CYCLE                ",  0x18ull},</div><div class='del'>-	{"HZIP_MAX_DELAY                 ",  0x20ull},</div><div class='del'>-	{"HZIP_MIN_DELAY                 ",  0x24ull},</div><div class='del'>-	{"HZIP_AVG_DELAY                 ",  0x28ull},</div><div class='del'>-	{"HZIP_MEM_VISIBLE_DATA          ",  0x30ull},</div><div class='del'>-	{"HZIP_MEM_VISIBLE_ADDR          ",  0x34ull},</div><div class='del'>-	{"HZIP_CONSUMED_BYTE             ",  0x38ull},</div><div class='del'>-	{"HZIP_PRODUCED_BYTE             ",  0x40ull},</div><div class='del'>-	{"HZIP_COMP_INF                  ",  0x70ull},</div><div class='del'>-	{"HZIP_PRE_OUT                   ",  0x78ull},</div><div class='del'>-	{"HZIP_BD_RD                     ",  0x7cull},</div><div class='del'>-	{"HZIP_BD_WR                     ",  0x80ull},</div><div class='del'>-	{"HZIP_GET_BD_AXI_ERR_NUM        ",  0x84ull},</div><div class='del'>-	{"HZIP_GET_BD_PARSE_ERR_NUM      ",  0x88ull},</div><div class='del'>-	{"HZIP_ADD_BD_AXI_ERR_NUM        ",  0x8cull},</div><div class='del'>-	{"HZIP_DECOMP_STF_RELOAD_CURR_ST ",  0x94ull},</div><div class='del'>-	{"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9cull},</div><div class='add'>+	{"HZIP_GET_BD_NUM                ",  0x00},</div><div class='add'>+	{"HZIP_GET_RIGHT_BD              ",  0x04},</div><div class='add'>+	{"HZIP_GET_ERROR_BD              ",  0x08},</div><div class='add'>+	{"HZIP_DONE_BD_NUM               ",  0x0c},</div><div class='add'>+	{"HZIP_WORK_CYCLE                ",  0x10},</div><div class='add'>+	{"HZIP_IDLE_CYCLE                ",  0x18},</div><div class='add'>+	{"HZIP_MAX_DELAY                 ",  0x20},</div><div class='add'>+	{"HZIP_MIN_DELAY                 ",  0x24},</div><div class='add'>+	{"HZIP_AVG_DELAY                 ",  0x28},</div><div class='add'>+	{"HZIP_MEM_VISIBLE_DATA          ",  0x30},</div><div class='add'>+	{"HZIP_MEM_VISIBLE_ADDR          ",  0x34},</div><div class='add'>+	{"HZIP_CONSUMED_BYTE             ",  0x38},</div><div class='add'>+	{"HZIP_PRODUCED_BYTE             ",  0x40},</div><div class='add'>+	{"HZIP_COMP_INF                  ",  0x70},</div><div class='add'>+	{"HZIP_PRE_OUT                   ",  0x78},</div><div class='add'>+	{"HZIP_BD_RD                     ",  0x7c},</div><div class='add'>+	{"HZIP_BD_WR                     ",  0x80},</div><div class='add'>+	{"HZIP_GET_BD_AXI_ERR_NUM        ",  0x84},</div><div class='add'>+	{"HZIP_GET_BD_PARSE_ERR_NUM      ",  0x88},</div><div class='add'>+	{"HZIP_ADD_BD_AXI_ERR_NUM        ",  0x8c},</div><div class='add'>+	{"HZIP_DECOMP_STF_RELOAD_CURR_ST ",  0x94},</div><div class='add'>+	{"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9c},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct debugfs_reg32 hzip_com_dfx_regs[] = {</div><div class='hunk'>@@ -303,11 +325,11 @@ static const struct debugfs_reg32 hzip_com_dfx_regs[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct debugfs_reg32 hzip_dump_dfx_regs[] = {</div><div class='del'>-	{"HZIP_GET_BD_NUM                ",  0x00ull},</div><div class='del'>-	{"HZIP_GET_RIGHT_BD              ",  0x04ull},</div><div class='del'>-	{"HZIP_GET_ERROR_BD              ",  0x08ull},</div><div class='del'>-	{"HZIP_DONE_BD_NUM               ",  0x0cull},</div><div class='del'>-	{"HZIP_MAX_DELAY                 ",  0x20ull},</div><div class='add'>+	{"HZIP_GET_BD_NUM                ",  0x00},</div><div class='add'>+	{"HZIP_GET_RIGHT_BD              ",  0x04},</div><div class='add'>+	{"HZIP_GET_ERROR_BD              ",  0x08},</div><div class='add'>+	{"HZIP_DONE_BD_NUM               ",  0x0c},</div><div class='add'>+	{"HZIP_MAX_DELAY                 ",  0x20},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* define the ZIP's dfx regs region and region length */</div><div class='hunk'>@@ -352,6 +374,37 @@ static int hzip_diff_regs_show(struct seq_file *s, void *unused)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs);</div><div class='add'>+</div><div class='add'>+static int perf_mode_set(const char *val, const struct kernel_param *kp)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 n;</div><div class='add'>+</div><div class='add'>+	if (!val)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32(val, 10, &amp;n);</div><div class='add'>+	if (ret != 0 || (n != HZIP_HIGH_COMP_PERF &amp;&amp;</div><div class='add'>+			 n != HZIP_HIGH_COMP_RATE))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return param_set_int(val, kp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kernel_param_ops zip_com_perf_ops = {</div><div class='add'>+	.set = perf_mode_set,</div><div class='add'>+	.get = param_get_int,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * perf_mode = 0 means enable high compression rate mode,</div><div class='add'>+ * perf_mode = 1 means enable high compression performance mode.</div><div class='add'>+ * These two modes only apply to the compression direction.</div><div class='add'>+ */</div><div class='add'>+static u32 perf_mode = HZIP_HIGH_COMP_RATE;</div><div class='add'>+module_param_cb(perf_mode, &amp;zip_com_perf_ops, &amp;perf_mode, 0444);</div><div class='add'>+MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)");</div><div class='add'>+</div><div class='ctx'> static const struct kernel_param_ops zip_uacce_mode_ops = {</div><div class='ctx'> 	.set = uacce_mode_set,</div><div class='ctx'> 	.get = param_get_int,</div><div class='hunk'>@@ -410,40 +463,33 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)</div><div class='ctx'> {</div><div class='ctx'> 	u32 cap_val;</div><div class='ctx'> </div><div class='del'>-	cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm-&gt;cap_ver);</div><div class='add'>+	cap_val = qm-&gt;cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val;</div><div class='ctx'> 	if ((alg &amp; cap_val) == alg)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hisi_zip_set_qm_algs(struct hisi_qm *qm)</div><div class='add'>+static int hisi_zip_set_high_perf(struct hisi_qm *qm)</div><div class='ctx'> {</div><div class='del'>-	struct device *dev = &amp;qm-&gt;pdev-&gt;dev;</div><div class='del'>-	char *algs, *ptr;</div><div class='del'>-	u32 alg_mask;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!qm-&gt;use_sva)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);</div><div class='del'>-	if (!algs)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm-&gt;cap_ver);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(zip_dev_algs); i++)</div><div class='del'>-		if (alg_mask &amp; zip_dev_algs[i].alg_msk)</div><div class='del'>-			strcat(algs, zip_dev_algs[i].algs);</div><div class='del'>-</div><div class='del'>-	ptr = strrchr(algs, '\n');</div><div class='del'>-	if (ptr)</div><div class='del'>-		*ptr = '\0';</div><div class='add'>+	u32 val;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	qm-&gt;uacce-&gt;algs = algs;</div><div class='add'>+	val = readl_relaxed(qm-&gt;io_base + HZIP_HIGH_PERF_OFFSET);</div><div class='add'>+	if (perf_mode == HZIP_HIGH_COMP_PERF)</div><div class='add'>+		val |= HZIP_HIGH_COMP_PERF;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~HZIP_HIGH_COMP_PERF;</div><div class='add'>+</div><div class='add'>+	/* Set perf mode */</div><div class='add'>+	writel(val, qm-&gt;io_base + HZIP_HIGH_PERF_OFFSET);</div><div class='add'>+	ret = readl_relaxed_poll_timeout(qm-&gt;io_base + HZIP_HIGH_PERF_OFFSET,</div><div class='add'>+					 val, val == perf_mode, HZIP_DELAY_1_US,</div><div class='add'>+					 HZIP_POLL_TIMEOUT_US);</div><div class='add'>+	if (ret)</div><div class='add'>+		pci_err(qm-&gt;pdev, "failed to set perf mode\n");</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)</div><div class='hunk'>@@ -542,10 +588,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* let's open all compression/decompression cores */</div><div class='del'>-	dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,</div><div class='del'>-				       ZIP_DECOMP_ENABLE_BITMAP, qm-&gt;cap_ver);</div><div class='del'>-	comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,</div><div class='del'>-				      ZIP_COMP_ENABLE_BITMAP, qm-&gt;cap_ver);</div><div class='add'>+	dcomp_bm = qm-&gt;cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val;</div><div class='add'>+	comp_bm = qm-&gt;cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val;</div><div class='ctx'> 	writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);</div><div class='ctx'> </div><div class='ctx'> 	/* enable sqc,cqc writeback */</div><div class='hunk'>@@ -772,9 +816,8 @@ static int hisi_zip_core_debug_init(struct hisi_qm *qm)</div><div class='ctx'> 	char buf[HZIP_BUF_SIZE];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm-&gt;cap_ver);</div><div class='del'>-	zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,</div><div class='del'>-						qm-&gt;cap_ver);</div><div class='add'>+	zip_core_num = qm-&gt;cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;</div><div class='add'>+	zip_comp_core_num = qm-&gt;cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; zip_core_num; i++) {</div><div class='ctx'> 		if (i &lt; zip_comp_core_num)</div><div class='hunk'>@@ -916,7 +959,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)</div><div class='ctx'> 	u32 zip_core_num;</div><div class='ctx'> 	int i, j, idx;</div><div class='ctx'> </div><div class='del'>-	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm-&gt;cap_ver);</div><div class='add'>+	zip_core_num = qm-&gt;cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;</div><div class='ctx'> </div><div class='ctx'> 	debug-&gt;last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num,</div><div class='ctx'> 				    sizeof(unsigned int), GFP_KERNEL);</div><div class='hunk'>@@ -972,9 +1015,9 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)</div><div class='ctx'> 				 hzip_com_dfx_regs[i].name, debug-&gt;last_words[i], val);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm-&gt;cap_ver);</div><div class='del'>-	zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,</div><div class='del'>-						qm-&gt;cap_ver);</div><div class='add'>+	zip_core_num = qm-&gt;cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;</div><div class='add'>+	zip_comp_core_num = qm-&gt;cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; zip_core_num; i++) {</div><div class='ctx'> 		if (i &lt; zip_comp_core_num)</div><div class='ctx'> 			scnprintf(buf, sizeof(buf), "Comp_core-%d", i);</div><div class='hunk'>@@ -1115,6 +1158,10 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	ret = hisi_zip_set_high_perf(qm);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	hisi_zip_open_sva_prefetch(qm);</div><div class='ctx'> 	hisi_qm_dev_err_init(qm);</div><div class='ctx'> 	hisi_zip_debug_regs_clear(qm);</div><div class='hunk'>@@ -1126,8 +1173,31 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int zip_pre_store_cap_reg(struct hisi_qm *qm)</div><div class='add'>+{</div><div class='add'>+	struct hisi_qm_cap_record *zip_cap;</div><div class='add'>+	struct pci_dev *pdev = qm-&gt;pdev;</div><div class='add'>+	size_t i, size;</div><div class='add'>+</div><div class='add'>+	size = ARRAY_SIZE(zip_pre_store_caps);</div><div class='add'>+	zip_cap = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*zip_cap) * size, GFP_KERNEL);</div><div class='add'>+	if (!zip_cap)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; size; i++) {</div><div class='add'>+		zip_cap[i].type = zip_pre_store_caps[i];</div><div class='add'>+		zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info,</div><div class='add'>+				     zip_pre_store_caps[i], qm-&gt;cap_ver);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	qm-&gt;cap_tables.dev_cap_table = zip_cap;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='add'>+	u64 alg_msk;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	qm-&gt;pdev = pdev;</div><div class='hunk'>@@ -1163,7 +1233,16 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = hisi_zip_set_qm_algs(qm);</div><div class='add'>+	/* Fetch and save the value of capability registers */</div><div class='add'>+	ret = zip_pre_store_cap_reg(qm);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pci_err(qm-&gt;pdev, "Failed to pre-store capability registers!\n");</div><div class='add'>+		hisi_qm_uninit(qm);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alg_msk = qm-&gt;cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val;</div><div class='add'>+	ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pci_err(qm-&gt;pdev, "Failed to set zip algs!\n");</div><div class='ctx'> 		hisi_qm_uninit(qm);</div><div class='head'>diff --git a/drivers/crypto/inside-secure/safexcel.c b/drivers/crypto/inside-secure/safexcel.c<br/>index 76da14af74b5..f5c1912aa564 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/inside-secure/safexcel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel.c</a></div><div class='hunk'>@@ -1191,8 +1191,6 @@ static struct safexcel_alg_template *safexcel_algs[] = {</div><div class='ctx'> 	&amp;safexcel_alg_cbc_des3_ede,</div><div class='ctx'> 	&amp;safexcel_alg_ecb_aes,</div><div class='ctx'> 	&amp;safexcel_alg_cbc_aes,</div><div class='del'>-	&amp;safexcel_alg_cfb_aes,</div><div class='del'>-	&amp;safexcel_alg_ofb_aes,</div><div class='ctx'> 	&amp;safexcel_alg_ctr_aes,</div><div class='ctx'> 	&amp;safexcel_alg_md5,</div><div class='ctx'> 	&amp;safexcel_alg_sha1,</div><div class='hunk'>@@ -1231,8 +1229,6 @@ static struct safexcel_alg_template *safexcel_algs[] = {</div><div class='ctx'> 	&amp;safexcel_alg_hmac_sm3,</div><div class='ctx'> 	&amp;safexcel_alg_ecb_sm4,</div><div class='ctx'> 	&amp;safexcel_alg_cbc_sm4,</div><div class='del'>-	&amp;safexcel_alg_ofb_sm4,</div><div class='del'>-	&amp;safexcel_alg_cfb_sm4,</div><div class='ctx'> 	&amp;safexcel_alg_ctr_sm4,</div><div class='ctx'> 	&amp;safexcel_alg_authenc_hmac_sha1_cbc_sm4,</div><div class='ctx'> 	&amp;safexcel_alg_authenc_hmac_sm3_cbc_sm4,</div><div class='head'>diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h<br/>index 47ef6c7cd02c..d0059ce954dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/inside-secure/safexcel.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel.h</a></div><div class='hunk'>@@ -933,8 +933,6 @@ extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_ecb_aes;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_cbc_aes;</div><div class='del'>-extern struct safexcel_alg_template safexcel_alg_cfb_aes;</div><div class='del'>-extern struct safexcel_alg_template safexcel_alg_ofb_aes;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_ctr_aes;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_md5;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_sha1;</div><div class='hunk'>@@ -973,8 +971,6 @@ extern struct safexcel_alg_template safexcel_alg_sm3;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_hmac_sm3;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_ecb_sm4;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_cbc_sm4;</div><div class='del'>-extern struct safexcel_alg_template safexcel_alg_ofb_sm4;</div><div class='del'>-extern struct safexcel_alg_template safexcel_alg_cfb_sm4;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_ctr_sm4;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;</div><div class='ctx'> extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;</div><div class='head'>diff --git a/drivers/crypto/inside-secure/safexcel_cipher.c b/drivers/crypto/inside-secure/safexcel_cipher.c<br/>index 272c28b5a088..42677f7458b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel_cipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/inside-secure/safexcel_cipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/inside-secure/safexcel_cipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/inside-secure/safexcel_cipher.c</a></div><div class='hunk'>@@ -742,9 +742,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring,</div><div class='ctx'> 				max(totlen_src, totlen_dst));</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='del'>-		if (sreq-&gt;nr_src &gt; 0)</div><div class='del'>-			dma_map_sg(priv-&gt;dev, src, sreq-&gt;nr_src,</div><div class='del'>-				   DMA_BIDIRECTIONAL);</div><div class='add'>+		if (sreq-&gt;nr_src &gt; 0 &amp;&amp;</div><div class='add'>+		    !dma_map_sg(priv-&gt;dev, src, sreq-&gt;nr_src, DMA_BIDIRECTIONAL))</div><div class='add'>+			return -EIO;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (unlikely(totlen_src &amp;&amp; (sreq-&gt;nr_src &lt;= 0))) {</div><div class='ctx'> 			dev_err(priv-&gt;dev, "Source buffer not large enough (need %d bytes)!",</div><div class='hunk'>@@ -752,8 +752,9 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (sreq-&gt;nr_src &gt; 0)</div><div class='del'>-			dma_map_sg(priv-&gt;dev, src, sreq-&gt;nr_src, DMA_TO_DEVICE);</div><div class='add'>+		if (sreq-&gt;nr_src &gt; 0 &amp;&amp;</div><div class='add'>+		    !dma_map_sg(priv-&gt;dev, src, sreq-&gt;nr_src, DMA_TO_DEVICE))</div><div class='add'>+			return -EIO;</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(totlen_dst &amp;&amp; (sreq-&gt;nr_dst &lt;= 0))) {</div><div class='ctx'> 			dev_err(priv-&gt;dev, "Dest buffer not large enough (need %d bytes)!",</div><div class='hunk'>@@ -762,9 +763,11 @@ static int safexcel_send_req(struct crypto_async_request *base, int ring,</div><div class='ctx'> 			goto unmap;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (sreq-&gt;nr_dst &gt; 0)</div><div class='del'>-			dma_map_sg(priv-&gt;dev, dst, sreq-&gt;nr_dst,</div><div class='del'>-				   DMA_FROM_DEVICE);</div><div class='add'>+		if (sreq-&gt;nr_dst &gt; 0 &amp;&amp;</div><div class='add'>+		    !dma_map_sg(priv-&gt;dev, dst, sreq-&gt;nr_dst, DMA_FROM_DEVICE)) {</div><div class='add'>+			ret = -EIO;</div><div class='add'>+			goto unmap;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(ctx-&gt;base.ctxr-&gt;data, ctx-&gt;key, ctx-&gt;key_len);</div><div class='hunk'>@@ -1349,82 +1352,6 @@ struct safexcel_alg_template safexcel_alg_cbc_aes = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int safexcel_skcipher_aes_cfb_cra_init(struct crypto_tfm *tfm)</div><div class='del'>-{</div><div class='del'>-	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='del'>-</div><div class='del'>-	safexcel_skcipher_cra_init(tfm);</div><div class='del'>-	ctx-&gt;alg  = SAFEXCEL_AES;</div><div class='del'>-	ctx-&gt;blocksz = AES_BLOCK_SIZE;</div><div class='del'>-	ctx-&gt;mode = CONTEXT_CONTROL_CRYPTO_MODE_CFB;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct safexcel_alg_template safexcel_alg_cfb_aes = {</div><div class='del'>-	.type = SAFEXCEL_ALG_TYPE_SKCIPHER,</div><div class='del'>-	.algo_mask = SAFEXCEL_ALG_AES | SAFEXCEL_ALG_AES_XFB,</div><div class='del'>-	.alg.skcipher = {</div><div class='del'>-		.setkey = safexcel_skcipher_aes_setkey,</div><div class='del'>-		.encrypt = safexcel_encrypt,</div><div class='del'>-		.decrypt = safexcel_decrypt,</div><div class='del'>-		.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-		.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-		.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-		.base = {</div><div class='del'>-			.cra_name = "cfb(aes)",</div><div class='del'>-			.cra_driver_name = "safexcel-cfb-aes",</div><div class='del'>-			.cra_priority = SAFEXCEL_CRA_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				     CRYPTO_ALG_ALLOCATES_MEMORY |</div><div class='del'>-				     CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct safexcel_cipher_ctx),</div><div class='del'>-			.cra_alignmask = 0,</div><div class='del'>-			.cra_init = safexcel_skcipher_aes_cfb_cra_init,</div><div class='del'>-			.cra_exit = safexcel_skcipher_cra_exit,</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int safexcel_skcipher_aes_ofb_cra_init(struct crypto_tfm *tfm)</div><div class='del'>-{</div><div class='del'>-	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='del'>-</div><div class='del'>-	safexcel_skcipher_cra_init(tfm);</div><div class='del'>-	ctx-&gt;alg  = SAFEXCEL_AES;</div><div class='del'>-	ctx-&gt;blocksz = AES_BLOCK_SIZE;</div><div class='del'>-	ctx-&gt;mode = CONTEXT_CONTROL_CRYPTO_MODE_OFB;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct safexcel_alg_template safexcel_alg_ofb_aes = {</div><div class='del'>-	.type = SAFEXCEL_ALG_TYPE_SKCIPHER,</div><div class='del'>-	.algo_mask = SAFEXCEL_ALG_AES | SAFEXCEL_ALG_AES_XFB,</div><div class='del'>-	.alg.skcipher = {</div><div class='del'>-		.setkey = safexcel_skcipher_aes_setkey,</div><div class='del'>-		.encrypt = safexcel_encrypt,</div><div class='del'>-		.decrypt = safexcel_decrypt,</div><div class='del'>-		.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-		.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-		.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-		.base = {</div><div class='del'>-			.cra_name = "ofb(aes)",</div><div class='del'>-			.cra_driver_name = "safexcel-ofb-aes",</div><div class='del'>-			.cra_priority = SAFEXCEL_CRA_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				     CRYPTO_ALG_ALLOCATES_MEMORY |</div><div class='del'>-				     CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct safexcel_cipher_ctx),</div><div class='del'>-			.cra_alignmask = 0,</div><div class='del'>-			.cra_init = safexcel_skcipher_aes_ofb_cra_init,</div><div class='del'>-			.cra_exit = safexcel_skcipher_cra_exit,</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static int safexcel_skcipher_aesctr_setkey(struct crypto_skcipher *ctfm,</div><div class='ctx'> 					   const u8 *key, unsigned int len)</div><div class='ctx'> {</div><div class='hunk'>@@ -3183,82 +3110,6 @@ struct safexcel_alg_template safexcel_alg_cbc_sm4 = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int safexcel_skcipher_sm4_ofb_cra_init(struct crypto_tfm *tfm)</div><div class='del'>-{</div><div class='del'>-	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='del'>-</div><div class='del'>-	safexcel_skcipher_cra_init(tfm);</div><div class='del'>-	ctx-&gt;alg  = SAFEXCEL_SM4;</div><div class='del'>-	ctx-&gt;blocksz = SM4_BLOCK_SIZE;</div><div class='del'>-	ctx-&gt;mode = CONTEXT_CONTROL_CRYPTO_MODE_OFB;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct safexcel_alg_template safexcel_alg_ofb_sm4 = {</div><div class='del'>-	.type = SAFEXCEL_ALG_TYPE_SKCIPHER,</div><div class='del'>-	.algo_mask = SAFEXCEL_ALG_SM4 | SAFEXCEL_ALG_AES_XFB,</div><div class='del'>-	.alg.skcipher = {</div><div class='del'>-		.setkey = safexcel_skcipher_sm4_setkey,</div><div class='del'>-		.encrypt = safexcel_encrypt,</div><div class='del'>-		.decrypt = safexcel_decrypt,</div><div class='del'>-		.min_keysize = SM4_KEY_SIZE,</div><div class='del'>-		.max_keysize = SM4_KEY_SIZE,</div><div class='del'>-		.ivsize = SM4_BLOCK_SIZE,</div><div class='del'>-		.base = {</div><div class='del'>-			.cra_name = "ofb(sm4)",</div><div class='del'>-			.cra_driver_name = "safexcel-ofb-sm4",</div><div class='del'>-			.cra_priority = SAFEXCEL_CRA_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				     CRYPTO_ALG_ALLOCATES_MEMORY |</div><div class='del'>-				     CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct safexcel_cipher_ctx),</div><div class='del'>-			.cra_alignmask = 0,</div><div class='del'>-			.cra_init = safexcel_skcipher_sm4_ofb_cra_init,</div><div class='del'>-			.cra_exit = safexcel_skcipher_cra_exit,</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int safexcel_skcipher_sm4_cfb_cra_init(struct crypto_tfm *tfm)</div><div class='del'>-{</div><div class='del'>-	struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='del'>-</div><div class='del'>-	safexcel_skcipher_cra_init(tfm);</div><div class='del'>-	ctx-&gt;alg  = SAFEXCEL_SM4;</div><div class='del'>-	ctx-&gt;blocksz = SM4_BLOCK_SIZE;</div><div class='del'>-	ctx-&gt;mode = CONTEXT_CONTROL_CRYPTO_MODE_CFB;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct safexcel_alg_template safexcel_alg_cfb_sm4 = {</div><div class='del'>-	.type = SAFEXCEL_ALG_TYPE_SKCIPHER,</div><div class='del'>-	.algo_mask = SAFEXCEL_ALG_SM4 | SAFEXCEL_ALG_AES_XFB,</div><div class='del'>-	.alg.skcipher = {</div><div class='del'>-		.setkey = safexcel_skcipher_sm4_setkey,</div><div class='del'>-		.encrypt = safexcel_encrypt,</div><div class='del'>-		.decrypt = safexcel_decrypt,</div><div class='del'>-		.min_keysize = SM4_KEY_SIZE,</div><div class='del'>-		.max_keysize = SM4_KEY_SIZE,</div><div class='del'>-		.ivsize = SM4_BLOCK_SIZE,</div><div class='del'>-		.base = {</div><div class='del'>-			.cra_name = "cfb(sm4)",</div><div class='del'>-			.cra_driver_name = "safexcel-cfb-sm4",</div><div class='del'>-			.cra_priority = SAFEXCEL_CRA_PRIORITY,</div><div class='del'>-			.cra_flags = CRYPTO_ALG_ASYNC |</div><div class='del'>-				     CRYPTO_ALG_ALLOCATES_MEMORY |</div><div class='del'>-				     CRYPTO_ALG_KERN_DRIVER_ONLY,</div><div class='del'>-			.cra_blocksize = 1,</div><div class='del'>-			.cra_ctxsize = sizeof(struct safexcel_cipher_ctx),</div><div class='del'>-			.cra_alignmask = 0,</div><div class='del'>-			.cra_init = safexcel_skcipher_sm4_cfb_cra_init,</div><div class='del'>-			.cra_exit = safexcel_skcipher_cra_exit,</div><div class='del'>-			.cra_module = THIS_MODULE,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static int safexcel_skcipher_sm4ctr_setkey(struct crypto_skcipher *ctfm,</div><div class='ctx'> 					   const u8 *key, unsigned int len)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/crypto/intel/Kconfig b/drivers/crypto/intel/Kconfig<br/>index 3d90c87d4094..f38cd62a3f67 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/Kconfig</a></div><div class='hunk'>@@ -3,3 +3,4 @@</div><div class='ctx'> source "drivers/crypto/intel/keembay/Kconfig"</div><div class='ctx'> source "drivers/crypto/intel/ixp4xx/Kconfig"</div><div class='ctx'> source "drivers/crypto/intel/qat/Kconfig"</div><div class='add'>+source "drivers/crypto/intel/iaa/Kconfig"</div><div class='head'>diff --git a/drivers/crypto/intel/Makefile b/drivers/crypto/intel/Makefile<br/>index b3d0352ae188..2f56f6d34cf0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/Makefile</a></div><div class='hunk'>@@ -3,3 +3,4 @@</div><div class='ctx'> obj-y += keembay/</div><div class='ctx'> obj-y += ixp4xx/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/</div><div class='add'>+obj-$(CONFIG_CRYPTO_DEV_IAA_CRYPTO) += iaa/</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/Kconfig b/drivers/crypto/intel/iaa/Kconfig<br/>new file mode 100644<br/>index 000000000000..d53f4b1d494f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+config CRYPTO_DEV_IAA_CRYPTO</div><div class='add'>+	tristate "Support for Intel(R) IAA Compression Accelerator"</div><div class='add'>+	depends on CRYPTO_DEFLATE</div><div class='add'>+	depends on INTEL_IDXD</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  This driver supports acceleration for compression and</div><div class='add'>+	  decompression with the Intel Analytics Accelerator (IAA)</div><div class='add'>+	  hardware using the cryptographic API.  If you choose 'M'</div><div class='add'>+	  here, the module will be called iaa_crypto.</div><div class='add'>+</div><div class='add'>+config CRYPTO_DEV_IAA_CRYPTO_STATS</div><div class='add'>+	bool "Enable Intel(R) IAA Compression Accelerator Statistics"</div><div class='add'>+	depends on CRYPTO_DEV_IAA_CRYPTO</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Enable statistics for the IAA compression accelerator.</div><div class='add'>+	  These include per-device and per-workqueue statistics in</div><div class='add'>+	  addition to global driver statistics.</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/Makefile b/drivers/crypto/intel/iaa/Makefile<br/>new file mode 100644<br/>index 000000000000..b64b208d2344<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/Makefile</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# Makefile for IAA crypto device drivers</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+ccflags-y += -I $(srctree)/drivers/dma/idxd -DDEFAULT_SYMBOL_NAMESPACE=IDXD</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_CRYPTO_DEV_IAA_CRYPTO) := iaa_crypto.o</div><div class='add'>+</div><div class='add'>+iaa_crypto-y := iaa_crypto_main.o iaa_crypto_comp_fixed.o</div><div class='add'>+</div><div class='add'>+iaa_crypto-$(CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS) += iaa_crypto_stats.o</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/iaa_crypto.h b/drivers/crypto/intel/iaa/iaa_crypto.h<br/>new file mode 100644<br/>index 000000000000..014420f7beb0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/iaa_crypto.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto.h</a></div><div class='hunk'>@@ -0,0 +1,173 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Copyright(c) 2021 Intel Corporation. All rights rsvd. */</div><div class='add'>+</div><div class='add'>+#ifndef __IAA_CRYPTO_H__</div><div class='add'>+#define __IAA_CRYPTO_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/crypto.h&gt;</div><div class='add'>+#include &lt;linux/idxd.h&gt;</div><div class='add'>+#include &lt;uapi/linux/idxd.h&gt;</div><div class='add'>+</div><div class='add'>+#define IDXD_SUBDRIVER_NAME		"crypto"</div><div class='add'>+</div><div class='add'>+#define IAA_DECOMP_ENABLE		BIT(0)</div><div class='add'>+#define IAA_DECOMP_FLUSH_OUTPUT		BIT(1)</div><div class='add'>+#define IAA_DECOMP_CHECK_FOR_EOB	BIT(2)</div><div class='add'>+#define IAA_DECOMP_STOP_ON_EOB		BIT(3)</div><div class='add'>+#define IAA_DECOMP_SUPPRESS_OUTPUT	BIT(9)</div><div class='add'>+</div><div class='add'>+#define IAA_COMP_FLUSH_OUTPUT		BIT(1)</div><div class='add'>+#define IAA_COMP_APPEND_EOB		BIT(2)</div><div class='add'>+</div><div class='add'>+#define IAA_COMPLETION_TIMEOUT		1000000</div><div class='add'>+</div><div class='add'>+#define IAA_ANALYTICS_ERROR		0x0a</div><div class='add'>+#define IAA_ERROR_DECOMP_BUF_OVERFLOW	0x0b</div><div class='add'>+#define IAA_ERROR_COMP_BUF_OVERFLOW	0x19</div><div class='add'>+#define IAA_ERROR_WATCHDOG_EXPIRED	0x24</div><div class='add'>+</div><div class='add'>+#define IAA_COMP_MODES_MAX		2</div><div class='add'>+</div><div class='add'>+#define FIXED_HDR			0x2</div><div class='add'>+#define FIXED_HDR_SIZE			3</div><div class='add'>+</div><div class='add'>+#define IAA_COMP_FLAGS			(IAA_COMP_FLUSH_OUTPUT | \</div><div class='add'>+					 IAA_COMP_APPEND_EOB)</div><div class='add'>+</div><div class='add'>+#define IAA_DECOMP_FLAGS		(IAA_DECOMP_ENABLE |	   \</div><div class='add'>+					 IAA_DECOMP_FLUSH_OUTPUT | \</div><div class='add'>+					 IAA_DECOMP_CHECK_FOR_EOB | \</div><div class='add'>+					 IAA_DECOMP_STOP_ON_EOB)</div><div class='add'>+</div><div class='add'>+/* Representation of IAA workqueue */</div><div class='add'>+struct iaa_wq {</div><div class='add'>+	struct list_head	list;</div><div class='add'>+</div><div class='add'>+	struct idxd_wq		*wq;</div><div class='add'>+	int			ref;</div><div class='add'>+	bool			remove;</div><div class='add'>+</div><div class='add'>+	struct iaa_device	*iaa_device;</div><div class='add'>+</div><div class='add'>+	u64			comp_calls;</div><div class='add'>+	u64			comp_bytes;</div><div class='add'>+	u64			decomp_calls;</div><div class='add'>+	u64			decomp_bytes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct iaa_device_compression_mode {</div><div class='add'>+	const char			*name;</div><div class='add'>+</div><div class='add'>+	struct aecs_comp_table_record	*aecs_comp_table;</div><div class='add'>+	struct aecs_decomp_table_record	*aecs_decomp_table;</div><div class='add'>+</div><div class='add'>+	dma_addr_t			aecs_comp_table_dma_addr;</div><div class='add'>+	dma_addr_t			aecs_decomp_table_dma_addr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Representation of IAA device with wqs, populated by probe */</div><div class='add'>+struct iaa_device {</div><div class='add'>+	struct list_head		list;</div><div class='add'>+	struct idxd_device		*idxd;</div><div class='add'>+</div><div class='add'>+	struct iaa_device_compression_mode	*compression_modes[IAA_COMP_MODES_MAX];</div><div class='add'>+</div><div class='add'>+	int				n_wq;</div><div class='add'>+	struct list_head		wqs;</div><div class='add'>+</div><div class='add'>+	u64				comp_calls;</div><div class='add'>+	u64				comp_bytes;</div><div class='add'>+	u64				decomp_calls;</div><div class='add'>+	u64				decomp_bytes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct wq_table_entry {</div><div class='add'>+	struct idxd_wq **wqs;</div><div class='add'>+	int	max_wqs;</div><div class='add'>+	int	n_wqs;</div><div class='add'>+	int	cur_wq;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define IAA_AECS_ALIGN			32</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Analytics Engine Configuration and State (AECS) contains parameters and</div><div class='add'>+ * internal state of the analytics engine.</div><div class='add'>+ */</div><div class='add'>+struct aecs_comp_table_record {</div><div class='add'>+	u32 crc;</div><div class='add'>+	u32 xor_checksum;</div><div class='add'>+	u32 reserved0[5];</div><div class='add'>+	u32 num_output_accum_bits;</div><div class='add'>+	u8 output_accum[256];</div><div class='add'>+	u32 ll_sym[286];</div><div class='add'>+	u32 reserved1;</div><div class='add'>+	u32 reserved2;</div><div class='add'>+	u32 d_sym[30];</div><div class='add'>+	u32 reserved_padding[2];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* AECS for decompress */</div><div class='add'>+struct aecs_decomp_table_record {</div><div class='add'>+	u32 crc;</div><div class='add'>+	u32 xor_checksum;</div><div class='add'>+	u32 low_filter_param;</div><div class='add'>+	u32 high_filter_param;</div><div class='add'>+	u32 output_mod_idx;</div><div class='add'>+	u32 drop_init_decomp_out_bytes;</div><div class='add'>+	u32 reserved[36];</div><div class='add'>+	u32 output_accum_data[2];</div><div class='add'>+	u32 out_bits_valid;</div><div class='add'>+	u32 bit_off_indexing;</div><div class='add'>+	u32 input_accum_data[64];</div><div class='add'>+	u8  size_qw[32];</div><div class='add'>+	u32 decomp_state[1220];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+int iaa_aecs_init_fixed(void);</div><div class='add'>+void iaa_aecs_cleanup_fixed(void);</div><div class='add'>+</div><div class='add'>+typedef int (*iaa_dev_comp_init_fn_t) (struct iaa_device_compression_mode *mode);</div><div class='add'>+typedef int (*iaa_dev_comp_free_fn_t) (struct iaa_device_compression_mode *mode);</div><div class='add'>+</div><div class='add'>+struct iaa_compression_mode {</div><div class='add'>+	const char		*name;</div><div class='add'>+	u32			*ll_table;</div><div class='add'>+	int			ll_table_size;</div><div class='add'>+	u32			*d_table;</div><div class='add'>+	int			d_table_size;</div><div class='add'>+	u32			*header_table;</div><div class='add'>+	int			header_table_size;</div><div class='add'>+	u16			gen_decomp_table_flags;</div><div class='add'>+	iaa_dev_comp_init_fn_t	init;</div><div class='add'>+	iaa_dev_comp_free_fn_t	free;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int add_iaa_compression_mode(const char *name,</div><div class='add'>+			     const u32 *ll_table,</div><div class='add'>+			     int ll_table_size,</div><div class='add'>+			     const u32 *d_table,</div><div class='add'>+			     int d_table_size,</div><div class='add'>+			     const u8 *header_table,</div><div class='add'>+			     int header_table_size,</div><div class='add'>+			     u16 gen_decomp_table_flags,</div><div class='add'>+			     iaa_dev_comp_init_fn_t init,</div><div class='add'>+			     iaa_dev_comp_free_fn_t free);</div><div class='add'>+</div><div class='add'>+void remove_iaa_compression_mode(const char *name);</div><div class='add'>+</div><div class='add'>+enum iaa_mode {</div><div class='add'>+	IAA_MODE_FIXED,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct iaa_compression_ctx {</div><div class='add'>+	enum iaa_mode	mode;</div><div class='add'>+	bool		verify_compress;</div><div class='add'>+	bool		async_mode;</div><div class='add'>+	bool		use_irq;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern struct list_head iaa_devices;</div><div class='add'>+extern struct mutex iaa_devices_lock;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c b/drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c<br/>new file mode 100644<br/>index 000000000000..45cf5d74f0fb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_comp_fixed.c</a></div><div class='hunk'>@@ -0,0 +1,92 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright(c) 2021 Intel Corporation. All rights rsvd. */</div><div class='add'>+</div><div class='add'>+#include "idxd.h"</div><div class='add'>+#include "iaa_crypto.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Fixed Huffman tables the IAA hardware requires to implement RFC-1951.</div><div class='add'>+ */</div><div class='add'>+static const u32 fixed_ll_sym[286] = {</div><div class='add'>+	0x40030, 0x40031, 0x40032, 0x40033, 0x40034, 0x40035, 0x40036, 0x40037,</div><div class='add'>+	0x40038, 0x40039, 0x4003A, 0x4003B, 0x4003C, 0x4003D, 0x4003E, 0x4003F,</div><div class='add'>+	0x40040, 0x40041, 0x40042, 0x40043, 0x40044, 0x40045, 0x40046, 0x40047,</div><div class='add'>+	0x40048, 0x40049, 0x4004A, 0x4004B, 0x4004C, 0x4004D, 0x4004E, 0x4004F,</div><div class='add'>+	0x40050, 0x40051, 0x40052, 0x40053, 0x40054, 0x40055, 0x40056, 0x40057,</div><div class='add'>+	0x40058, 0x40059, 0x4005A, 0x4005B, 0x4005C, 0x4005D, 0x4005E, 0x4005F,</div><div class='add'>+	0x40060, 0x40061, 0x40062, 0x40063, 0x40064, 0x40065, 0x40066, 0x40067,</div><div class='add'>+	0x40068, 0x40069, 0x4006A, 0x4006B, 0x4006C, 0x4006D, 0x4006E, 0x4006F,</div><div class='add'>+	0x40070, 0x40071, 0x40072, 0x40073, 0x40074, 0x40075, 0x40076, 0x40077,</div><div class='add'>+	0x40078, 0x40079, 0x4007A, 0x4007B, 0x4007C, 0x4007D, 0x4007E, 0x4007F,</div><div class='add'>+	0x40080, 0x40081, 0x40082, 0x40083, 0x40084, 0x40085, 0x40086, 0x40087,</div><div class='add'>+	0x40088, 0x40089, 0x4008A, 0x4008B, 0x4008C, 0x4008D, 0x4008E, 0x4008F,</div><div class='add'>+	0x40090, 0x40091, 0x40092, 0x40093, 0x40094, 0x40095, 0x40096, 0x40097,</div><div class='add'>+	0x40098, 0x40099, 0x4009A, 0x4009B, 0x4009C, 0x4009D, 0x4009E, 0x4009F,</div><div class='add'>+	0x400A0, 0x400A1, 0x400A2, 0x400A3, 0x400A4, 0x400A5, 0x400A6, 0x400A7,</div><div class='add'>+	0x400A8, 0x400A9, 0x400AA, 0x400AB, 0x400AC, 0x400AD, 0x400AE, 0x400AF,</div><div class='add'>+	0x400B0, 0x400B1, 0x400B2, 0x400B3, 0x400B4, 0x400B5, 0x400B6, 0x400B7,</div><div class='add'>+	0x400B8, 0x400B9, 0x400BA, 0x400BB, 0x400BC, 0x400BD, 0x400BE, 0x400BF,</div><div class='add'>+	0x48190, 0x48191, 0x48192, 0x48193, 0x48194, 0x48195, 0x48196, 0x48197,</div><div class='add'>+	0x48198, 0x48199, 0x4819A, 0x4819B, 0x4819C, 0x4819D, 0x4819E, 0x4819F,</div><div class='add'>+	0x481A0, 0x481A1, 0x481A2, 0x481A3, 0x481A4, 0x481A5, 0x481A6, 0x481A7,</div><div class='add'>+	0x481A8, 0x481A9, 0x481AA, 0x481AB, 0x481AC, 0x481AD, 0x481AE, 0x481AF,</div><div class='add'>+	0x481B0, 0x481B1, 0x481B2, 0x481B3, 0x481B4, 0x481B5, 0x481B6, 0x481B7,</div><div class='add'>+	0x481B8, 0x481B9, 0x481BA, 0x481BB, 0x481BC, 0x481BD, 0x481BE, 0x481BF,</div><div class='add'>+	0x481C0, 0x481C1, 0x481C2, 0x481C3, 0x481C4, 0x481C5, 0x481C6, 0x481C7,</div><div class='add'>+	0x481C8, 0x481C9, 0x481CA, 0x481CB, 0x481CC, 0x481CD, 0x481CE, 0x481CF,</div><div class='add'>+	0x481D0, 0x481D1, 0x481D2, 0x481D3, 0x481D4, 0x481D5, 0x481D6, 0x481D7,</div><div class='add'>+	0x481D8, 0x481D9, 0x481DA, 0x481DB, 0x481DC, 0x481DD, 0x481DE, 0x481DF,</div><div class='add'>+	0x481E0, 0x481E1, 0x481E2, 0x481E3, 0x481E4, 0x481E5, 0x481E6, 0x481E7,</div><div class='add'>+	0x481E8, 0x481E9, 0x481EA, 0x481EB, 0x481EC, 0x481ED, 0x481EE, 0x481EF,</div><div class='add'>+	0x481F0, 0x481F1, 0x481F2, 0x481F3, 0x481F4, 0x481F5, 0x481F6, 0x481F7,</div><div class='add'>+	0x481F8, 0x481F9, 0x481FA, 0x481FB, 0x481FC, 0x481FD, 0x481FE, 0x481FF,</div><div class='add'>+	0x38000, 0x38001, 0x38002, 0x38003, 0x38004, 0x38005, 0x38006, 0x38007,</div><div class='add'>+	0x38008, 0x38009, 0x3800A, 0x3800B, 0x3800C, 0x3800D, 0x3800E, 0x3800F,</div><div class='add'>+	0x38010, 0x38011, 0x38012, 0x38013, 0x38014, 0x38015, 0x38016, 0x38017,</div><div class='add'>+	0x400C0, 0x400C1, 0x400C2, 0x400C3, 0x400C4, 0x400C5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 fixed_d_sym[30] = {</div><div class='add'>+	0x28000, 0x28001, 0x28002, 0x28003, 0x28004, 0x28005, 0x28006, 0x28007,</div><div class='add'>+	0x28008, 0x28009, 0x2800A, 0x2800B, 0x2800C, 0x2800D, 0x2800E, 0x2800F,</div><div class='add'>+	0x28010, 0x28011, 0x28012, 0x28013, 0x28014, 0x28015, 0x28016, 0x28017,</div><div class='add'>+	0x28018, 0x28019, 0x2801A, 0x2801B, 0x2801C, 0x2801D</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int init_fixed_mode(struct iaa_device_compression_mode *mode)</div><div class='add'>+{</div><div class='add'>+	struct aecs_comp_table_record *comp_table = mode-&gt;aecs_comp_table;</div><div class='add'>+	u32 bfinal = 1;</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	/* Configure aecs table using fixed Huffman table */</div><div class='add'>+	comp_table-&gt;crc = 0;</div><div class='add'>+	comp_table-&gt;xor_checksum = 0;</div><div class='add'>+	offset = comp_table-&gt;num_output_accum_bits / 8;</div><div class='add'>+	comp_table-&gt;output_accum[offset] = FIXED_HDR | bfinal;</div><div class='add'>+	comp_table-&gt;num_output_accum_bits = FIXED_HDR_SIZE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int iaa_aecs_init_fixed(void)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = add_iaa_compression_mode("fixed",</div><div class='add'>+				       fixed_ll_sym,</div><div class='add'>+				       sizeof(fixed_ll_sym),</div><div class='add'>+				       fixed_d_sym,</div><div class='add'>+				       sizeof(fixed_d_sym),</div><div class='add'>+				       NULL, 0, 0,</div><div class='add'>+				       init_fixed_mode, NULL);</div><div class='add'>+	if (!ret)</div><div class='add'>+		pr_debug("IAA fixed compression mode initialized\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void iaa_aecs_cleanup_fixed(void)</div><div class='add'>+{</div><div class='add'>+	remove_iaa_compression_mode("fixed");</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/intel/iaa/iaa_crypto_main.c<br/>new file mode 100644<br/>index 000000000000..dfd3baf0a8d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/iaa_crypto_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_main.c</a></div><div class='hunk'>@@ -0,0 +1,2193 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright(c) 2021 Intel Corporation. All rights rsvd. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/iommu.h&gt;</div><div class='add'>+#include &lt;uapi/linux/idxd.h&gt;</div><div class='add'>+#include &lt;linux/highmem.h&gt;</div><div class='add'>+#include &lt;linux/sched/smt.h&gt;</div><div class='add'>+#include &lt;crypto/internal/acompress.h&gt;</div><div class='add'>+</div><div class='add'>+#include "idxd.h"</div><div class='add'>+#include "iaa_crypto.h"</div><div class='add'>+#include "iaa_crypto_stats.h"</div><div class='add'>+</div><div class='add'>+#ifdef pr_fmt</div><div class='add'>+#undef pr_fmt</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define pr_fmt(fmt)			"idxd: " IDXD_SUBDRIVER_NAME ": " fmt</div><div class='add'>+</div><div class='add'>+#define IAA_ALG_PRIORITY               300</div><div class='add'>+</div><div class='add'>+/* number of iaa instances probed */</div><div class='add'>+static unsigned int nr_iaa;</div><div class='add'>+static unsigned int nr_cpus;</div><div class='add'>+static unsigned int nr_nodes;</div><div class='add'>+static unsigned int nr_cpus_per_node;</div><div class='add'>+</div><div class='add'>+/* Number of physical cpus sharing each iaa instance */</div><div class='add'>+static unsigned int cpus_per_iaa;</div><div class='add'>+</div><div class='add'>+static struct crypto_comp *deflate_generic_tfm;</div><div class='add'>+</div><div class='add'>+/* Per-cpu lookup table for balanced wqs */</div><div class='add'>+static struct wq_table_entry __percpu *wq_table;</div><div class='add'>+</div><div class='add'>+static struct idxd_wq *wq_table_next_wq(int cpu)</div><div class='add'>+{</div><div class='add'>+	struct wq_table_entry *entry = per_cpu_ptr(wq_table, cpu);</div><div class='add'>+</div><div class='add'>+	if (++entry-&gt;cur_wq &gt;= entry-&gt;n_wqs)</div><div class='add'>+		entry-&gt;cur_wq = 0;</div><div class='add'>+</div><div class='add'>+	if (!entry-&gt;wqs[entry-&gt;cur_wq])</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	pr_debug("%s: returning wq at idx %d (iaa wq %d.%d) from cpu %d\n", __func__,</div><div class='add'>+		 entry-&gt;cur_wq, entry-&gt;wqs[entry-&gt;cur_wq]-&gt;idxd-&gt;id,</div><div class='add'>+		 entry-&gt;wqs[entry-&gt;cur_wq]-&gt;id, cpu);</div><div class='add'>+</div><div class='add'>+	return entry-&gt;wqs[entry-&gt;cur_wq];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wq_table_add(int cpu, struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct wq_table_entry *entry = per_cpu_ptr(wq_table, cpu);</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(entry-&gt;n_wqs == entry-&gt;max_wqs))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	entry-&gt;wqs[entry-&gt;n_wqs++] = wq;</div><div class='add'>+</div><div class='add'>+	pr_debug("%s: added iaa wq %d.%d to idx %d of cpu %d\n", __func__,</div><div class='add'>+		 entry-&gt;wqs[entry-&gt;n_wqs - 1]-&gt;idxd-&gt;id,</div><div class='add'>+		 entry-&gt;wqs[entry-&gt;n_wqs - 1]-&gt;id, entry-&gt;n_wqs - 1, cpu);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wq_table_free_entry(int cpu)</div><div class='add'>+{</div><div class='add'>+	struct wq_table_entry *entry = per_cpu_ptr(wq_table, cpu);</div><div class='add'>+</div><div class='add'>+	kfree(entry-&gt;wqs);</div><div class='add'>+	memset(entry, 0, sizeof(*entry));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wq_table_clear_entry(int cpu)</div><div class='add'>+{</div><div class='add'>+	struct wq_table_entry *entry = per_cpu_ptr(wq_table, cpu);</div><div class='add'>+</div><div class='add'>+	entry-&gt;n_wqs = 0;</div><div class='add'>+	entry-&gt;cur_wq = 0;</div><div class='add'>+	memset(entry-&gt;wqs, 0, entry-&gt;max_wqs * sizeof(struct idxd_wq *));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+LIST_HEAD(iaa_devices);</div><div class='add'>+DEFINE_MUTEX(iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+/* If enabled, IAA hw crypto algos are registered, unavailable otherwise */</div><div class='add'>+static bool iaa_crypto_enabled;</div><div class='add'>+static bool iaa_crypto_registered;</div><div class='add'>+</div><div class='add'>+/* Verify results of IAA compress or not */</div><div class='add'>+static bool iaa_verify_compress = true;</div><div class='add'>+</div><div class='add'>+static ssize_t verify_compress_show(struct device_driver *driver, char *buf)</div><div class='add'>+{</div><div class='add'>+	return sprintf(buf, "%d\n", iaa_verify_compress);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t verify_compress_store(struct device_driver *driver,</div><div class='add'>+				     const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	int ret = -EBUSY;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	if (iaa_crypto_enabled)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = kstrtobool(buf, &amp;iaa_verify_compress);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = count;</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+static DRIVER_ATTR_RW(verify_compress);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The iaa crypto driver supports three 'sync' methods determining how</div><div class='add'>+ * compressions and decompressions are performed:</div><div class='add'>+ *</div><div class='add'>+ * - sync:      the compression or decompression completes before</div><div class='add'>+ *              returning.  This is the mode used by the async crypto</div><div class='add'>+ *              interface when the sync mode is set to 'sync' and by</div><div class='add'>+ *              the sync crypto interface regardless of setting.</div><div class='add'>+ *</div><div class='add'>+ * - async:     the compression or decompression is submitted and returns</div><div class='add'>+ *              immediately.  Completion interrupts are not used so</div><div class='add'>+ *              the caller is responsible for polling the descriptor</div><div class='add'>+ *              for completion.  This mode is applicable to only the</div><div class='add'>+ *              async crypto interface and is ignored for anything</div><div class='add'>+ *              else.</div><div class='add'>+ *</div><div class='add'>+ * - async_irq: the compression or decompression is submitted and</div><div class='add'>+ *              returns immediately.  Completion interrupts are</div><div class='add'>+ *              enabled so the caller can wait for the completion and</div><div class='add'>+ *              yield to other threads.  When the compression or</div><div class='add'>+ *              decompression completes, the completion is signaled</div><div class='add'>+ *              and the caller awakened.  This mode is applicable to</div><div class='add'>+ *              only the async crypto interface and is ignored for</div><div class='add'>+ *              anything else.</div><div class='add'>+ *</div><div class='add'>+ * These modes can be set using the iaa_crypto sync_mode driver</div><div class='add'>+ * attribute.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Use async mode */</div><div class='add'>+static bool async_mode;</div><div class='add'>+/* Use interrupts */</div><div class='add'>+static bool use_irq;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * set_iaa_sync_mode - Set IAA sync mode</div><div class='add'>+ * @name: The name of the sync mode</div><div class='add'>+ *</div><div class='add'>+ * Make the IAA sync mode named @name the current sync mode used by</div><div class='add'>+ * compression/decompression.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static int set_iaa_sync_mode(const char *name)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (sysfs_streq(name, "sync")) {</div><div class='add'>+		async_mode = false;</div><div class='add'>+		use_irq = false;</div><div class='add'>+	} else if (sysfs_streq(name, "async")) {</div><div class='add'>+		async_mode = true;</div><div class='add'>+		use_irq = false;</div><div class='add'>+	} else if (sysfs_streq(name, "async_irq")) {</div><div class='add'>+		async_mode = true;</div><div class='add'>+		use_irq = true;</div><div class='add'>+	} else {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t sync_mode_show(struct device_driver *driver, char *buf)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!async_mode &amp;&amp; !use_irq)</div><div class='add'>+		ret = sprintf(buf, "%s\n", "sync");</div><div class='add'>+	else if (async_mode &amp;&amp; !use_irq)</div><div class='add'>+		ret = sprintf(buf, "%s\n", "async");</div><div class='add'>+	else if (async_mode &amp;&amp; use_irq)</div><div class='add'>+		ret = sprintf(buf, "%s\n", "async_irq");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t sync_mode_store(struct device_driver *driver,</div><div class='add'>+			       const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	int ret = -EBUSY;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	if (iaa_crypto_enabled)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = set_iaa_sync_mode(buf);</div><div class='add'>+	if (ret == 0)</div><div class='add'>+		ret = count;</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+static DRIVER_ATTR_RW(sync_mode);</div><div class='add'>+</div><div class='add'>+static struct iaa_compression_mode *iaa_compression_modes[IAA_COMP_MODES_MAX];</div><div class='add'>+</div><div class='add'>+static int find_empty_iaa_compression_mode(void)</div><div class='add'>+{</div><div class='add'>+	int i = -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; IAA_COMP_MODES_MAX; i++) {</div><div class='add'>+		if (iaa_compression_modes[i])</div><div class='add'>+			continue;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct iaa_compression_mode *find_iaa_compression_mode(const char *name, int *idx)</div><div class='add'>+{</div><div class='add'>+	struct iaa_compression_mode *mode;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; IAA_COMP_MODES_MAX; i++) {</div><div class='add'>+		mode = iaa_compression_modes[i];</div><div class='add'>+		if (!mode)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!strcmp(mode-&gt;name, name)) {</div><div class='add'>+			*idx = i;</div><div class='add'>+			return iaa_compression_modes[i];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_iaa_compression_mode(struct iaa_compression_mode *mode)</div><div class='add'>+{</div><div class='add'>+	kfree(mode-&gt;name);</div><div class='add'>+	kfree(mode-&gt;ll_table);</div><div class='add'>+	kfree(mode-&gt;d_table);</div><div class='add'>+	kfree(mode-&gt;header_table);</div><div class='add'>+</div><div class='add'>+	kfree(mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * IAA Compression modes are defined by an ll_table, a d_table, and an</div><div class='add'>+ * optional header_table.  These tables are typically generated and</div><div class='add'>+ * captured using statistics collected from running actual</div><div class='add'>+ * compress/decompress workloads.</div><div class='add'>+ *</div><div class='add'>+ * A module or other kernel code can add and remove compression modes</div><div class='add'>+ * with a given name using the exported @add_iaa_compression_mode()</div><div class='add'>+ * and @remove_iaa_compression_mode functions.</div><div class='add'>+ *</div><div class='add'>+ * When a new compression mode is added, the tables are saved in a</div><div class='add'>+ * global compression mode list.  When IAA devices are added, a</div><div class='add'>+ * per-IAA device dma mapping is created for each IAA device, for each</div><div class='add'>+ * compression mode.  These are the tables used to do the actual</div><div class='add'>+ * compression/deccompression and are unmapped if/when the devices are</div><div class='add'>+ * removed.  Currently, compression modes must be added before any</div><div class='add'>+ * device is added, and removed after all devices have been removed.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * remove_iaa_compression_mode - Remove an IAA compression mode</div><div class='add'>+ * @name: The name the compression mode will be known as</div><div class='add'>+ *</div><div class='add'>+ * Remove the IAA compression mode named @name.</div><div class='add'>+ */</div><div class='add'>+void remove_iaa_compression_mode(const char *name)</div><div class='add'>+{</div><div class='add'>+	struct iaa_compression_mode *mode;</div><div class='add'>+	int idx;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	if (!list_empty(&amp;iaa_devices))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	mode = find_iaa_compression_mode(name, &amp;idx);</div><div class='add'>+	if (mode) {</div><div class='add'>+		free_iaa_compression_mode(mode);</div><div class='add'>+		iaa_compression_modes[idx] = NULL;</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(remove_iaa_compression_mode);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * add_iaa_compression_mode - Add an IAA compression mode</div><div class='add'>+ * @name: The name the compression mode will be known as</div><div class='add'>+ * @ll_table: The ll table</div><div class='add'>+ * @ll_table_size: The ll table size in bytes</div><div class='add'>+ * @d_table: The d table</div><div class='add'>+ * @d_table_size: The d table size in bytes</div><div class='add'>+ * @header_table: Optional header table</div><div class='add'>+ * @header_table_size: Optional header table size in bytes</div><div class='add'>+ * @gen_decomp_table_flags: Otional flags used to generate the decomp table</div><div class='add'>+ * @init: Optional callback function to init the compression mode data</div><div class='add'>+ * @free: Optional callback function to free the compression mode data</div><div class='add'>+ *</div><div class='add'>+ * Add a new IAA compression mode named @name.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 if successful, errcode otherwise.</div><div class='add'>+ */</div><div class='add'>+int add_iaa_compression_mode(const char *name,</div><div class='add'>+			     const u32 *ll_table,</div><div class='add'>+			     int ll_table_size,</div><div class='add'>+			     const u32 *d_table,</div><div class='add'>+			     int d_table_size,</div><div class='add'>+			     const u8 *header_table,</div><div class='add'>+			     int header_table_size,</div><div class='add'>+			     u16 gen_decomp_table_flags,</div><div class='add'>+			     iaa_dev_comp_init_fn_t init,</div><div class='add'>+			     iaa_dev_comp_free_fn_t free)</div><div class='add'>+{</div><div class='add'>+	struct iaa_compression_mode *mode;</div><div class='add'>+	int idx, ret = -ENOMEM;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	if (!list_empty(&amp;iaa_devices)) {</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode = kzalloc(sizeof(*mode), GFP_KERNEL);</div><div class='add'>+	if (!mode)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	mode-&gt;name = kstrdup(name, GFP_KERNEL);</div><div class='add'>+	if (!mode-&gt;name)</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	if (ll_table) {</div><div class='add'>+		mode-&gt;ll_table = kzalloc(ll_table_size, GFP_KERNEL);</div><div class='add'>+		if (!mode-&gt;ll_table)</div><div class='add'>+			goto free;</div><div class='add'>+		memcpy(mode-&gt;ll_table, ll_table, ll_table_size);</div><div class='add'>+		mode-&gt;ll_table_size = ll_table_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (d_table) {</div><div class='add'>+		mode-&gt;d_table = kzalloc(d_table_size, GFP_KERNEL);</div><div class='add'>+		if (!mode-&gt;d_table)</div><div class='add'>+			goto free;</div><div class='add'>+		memcpy(mode-&gt;d_table, d_table, d_table_size);</div><div class='add'>+		mode-&gt;d_table_size = d_table_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (header_table) {</div><div class='add'>+		mode-&gt;header_table = kzalloc(header_table_size, GFP_KERNEL);</div><div class='add'>+		if (!mode-&gt;header_table)</div><div class='add'>+			goto free;</div><div class='add'>+		memcpy(mode-&gt;header_table, header_table, header_table_size);</div><div class='add'>+		mode-&gt;header_table_size = header_table_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode-&gt;gen_decomp_table_flags = gen_decomp_table_flags;</div><div class='add'>+</div><div class='add'>+	mode-&gt;init = init;</div><div class='add'>+	mode-&gt;free = free;</div><div class='add'>+</div><div class='add'>+	idx = find_empty_iaa_compression_mode();</div><div class='add'>+	if (idx &lt; 0)</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	pr_debug("IAA compression mode %s added at idx %d\n",</div><div class='add'>+		 mode-&gt;name, idx);</div><div class='add'>+</div><div class='add'>+	iaa_compression_modes[idx] = mode;</div><div class='add'>+</div><div class='add'>+	ret = 0;</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+free:</div><div class='add'>+	free_iaa_compression_mode(mode);</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(add_iaa_compression_mode);</div><div class='add'>+</div><div class='add'>+static struct iaa_device_compression_mode *</div><div class='add'>+get_iaa_device_compression_mode(struct iaa_device *iaa_device, int idx)</div><div class='add'>+{</div><div class='add'>+	return iaa_device-&gt;compression_modes[idx];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_device_compression_mode(struct iaa_device *iaa_device,</div><div class='add'>+					 struct iaa_device_compression_mode *device_mode)</div><div class='add'>+{</div><div class='add'>+	size_t size = sizeof(struct aecs_comp_table_record) + IAA_AECS_ALIGN;</div><div class='add'>+	struct device *dev = &amp;iaa_device-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	kfree(device_mode-&gt;name);</div><div class='add'>+</div><div class='add'>+	if (device_mode-&gt;aecs_comp_table)</div><div class='add'>+		dma_free_coherent(dev, size, device_mode-&gt;aecs_comp_table,</div><div class='add'>+				  device_mode-&gt;aecs_comp_table_dma_addr);</div><div class='add'>+	if (device_mode-&gt;aecs_decomp_table)</div><div class='add'>+		dma_free_coherent(dev, size, device_mode-&gt;aecs_decomp_table,</div><div class='add'>+				  device_mode-&gt;aecs_decomp_table_dma_addr);</div><div class='add'>+</div><div class='add'>+	kfree(device_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define IDXD_OP_FLAG_AECS_RW_TGLS       0x400000</div><div class='add'>+#define IAX_AECS_DEFAULT_FLAG (IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CC)</div><div class='add'>+#define IAX_AECS_COMPRESS_FLAG	(IAX_AECS_DEFAULT_FLAG | IDXD_OP_FLAG_RD_SRC2_AECS)</div><div class='add'>+#define IAX_AECS_DECOMPRESS_FLAG (IAX_AECS_DEFAULT_FLAG | IDXD_OP_FLAG_RD_SRC2_AECS)</div><div class='add'>+#define IAX_AECS_GEN_FLAG (IAX_AECS_DEFAULT_FLAG | \</div><div class='add'>+						IDXD_OP_FLAG_WR_SRC2_AECS_COMP | \</div><div class='add'>+						IDXD_OP_FLAG_AECS_RW_TGLS)</div><div class='add'>+</div><div class='add'>+static int check_completion(struct device *dev,</div><div class='add'>+			    struct iax_completion_record *comp,</div><div class='add'>+			    bool compress,</div><div class='add'>+			    bool only_once);</div><div class='add'>+</div><div class='add'>+static int decompress_header(struct iaa_device_compression_mode *device_mode,</div><div class='add'>+			     struct iaa_compression_mode *mode,</div><div class='add'>+			     struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	dma_addr_t src_addr, src2_addr;</div><div class='add'>+	struct idxd_desc *idxd_desc;</div><div class='add'>+	struct iax_hw_desc *desc;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	idxd_desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);</div><div class='add'>+	if (IS_ERR(idxd_desc))</div><div class='add'>+		return PTR_ERR(idxd_desc);</div><div class='add'>+</div><div class='add'>+	desc = idxd_desc-&gt;iax_hw;</div><div class='add'>+</div><div class='add'>+	dev = &amp;wq-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	src_addr = dma_map_single(dev, (void *)mode-&gt;header_table,</div><div class='add'>+				  mode-&gt;header_table_size, DMA_TO_DEVICE);</div><div class='add'>+	dev_dbg(dev, "%s: mode-&gt;name %s, src_addr %llx, dev %p, src %p, slen %d\n",</div><div class='add'>+		__func__, mode-&gt;name, src_addr,	dev,</div><div class='add'>+		mode-&gt;header_table, mode-&gt;header_table_size);</div><div class='add'>+	if (unlikely(dma_mapping_error(dev, src_addr))) {</div><div class='add'>+		dev_dbg(dev, "dma_map_single err, exiting\n");</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	desc-&gt;flags = IAX_AECS_GEN_FLAG;</div><div class='add'>+	desc-&gt;opcode = IAX_OPCODE_DECOMPRESS;</div><div class='add'>+</div><div class='add'>+	desc-&gt;src1_addr = (u64)src_addr;</div><div class='add'>+	desc-&gt;src1_size = mode-&gt;header_table_size;</div><div class='add'>+</div><div class='add'>+	src2_addr = device_mode-&gt;aecs_decomp_table_dma_addr;</div><div class='add'>+	desc-&gt;src2_addr = (u64)src2_addr;</div><div class='add'>+	desc-&gt;src2_size = 1088;</div><div class='add'>+	dev_dbg(dev, "%s: mode-&gt;name %s, src2_addr %llx, dev %p, src2_size %d\n",</div><div class='add'>+		__func__, mode-&gt;name, desc-&gt;src2_addr, dev, desc-&gt;src2_size);</div><div class='add'>+	desc-&gt;max_dst_size = 0; // suppressed output</div><div class='add'>+</div><div class='add'>+	desc-&gt;decompr_flags = mode-&gt;gen_decomp_table_flags;</div><div class='add'>+</div><div class='add'>+	desc-&gt;priv = 0;</div><div class='add'>+</div><div class='add'>+	desc-&gt;completion_addr = idxd_desc-&gt;compl_dma;</div><div class='add'>+</div><div class='add'>+	ret = idxd_submit_desc(wq, idxd_desc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_err("%s: submit_desc failed ret=0x%x\n", __func__, ret);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = check_completion(dev, idxd_desc-&gt;iax_completion, false, false);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_dbg(dev, "%s: mode-&gt;name %s check_completion failed ret=%d\n",</div><div class='add'>+			__func__, mode-&gt;name, ret);</div><div class='add'>+	else</div><div class='add'>+		dev_dbg(dev, "%s: mode-&gt;name %s succeeded\n", __func__,</div><div class='add'>+			mode-&gt;name);</div><div class='add'>+out:</div><div class='add'>+	dma_unmap_single(dev, src_addr, 1088, DMA_TO_DEVICE);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int init_device_compression_mode(struct iaa_device *iaa_device,</div><div class='add'>+					struct iaa_compression_mode *mode,</div><div class='add'>+					int idx, struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	size_t size = sizeof(struct aecs_comp_table_record) + IAA_AECS_ALIGN;</div><div class='add'>+	struct device *dev = &amp;iaa_device-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+	struct iaa_device_compression_mode *device_mode;</div><div class='add'>+	int ret = -ENOMEM;</div><div class='add'>+</div><div class='add'>+	device_mode = kzalloc(sizeof(*device_mode), GFP_KERNEL);</div><div class='add'>+	if (!device_mode)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	device_mode-&gt;name = kstrdup(mode-&gt;name, GFP_KERNEL);</div><div class='add'>+	if (!device_mode-&gt;name)</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	device_mode-&gt;aecs_comp_table = dma_alloc_coherent(dev, size,</div><div class='add'>+							  &amp;device_mode-&gt;aecs_comp_table_dma_addr, GFP_KERNEL);</div><div class='add'>+	if (!device_mode-&gt;aecs_comp_table)</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	device_mode-&gt;aecs_decomp_table = dma_alloc_coherent(dev, size,</div><div class='add'>+							    &amp;device_mode-&gt;aecs_decomp_table_dma_addr, GFP_KERNEL);</div><div class='add'>+	if (!device_mode-&gt;aecs_decomp_table)</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	/* Add Huffman table to aecs */</div><div class='add'>+	memset(device_mode-&gt;aecs_comp_table, 0, sizeof(*device_mode-&gt;aecs_comp_table));</div><div class='add'>+	memcpy(device_mode-&gt;aecs_comp_table-&gt;ll_sym, mode-&gt;ll_table, mode-&gt;ll_table_size);</div><div class='add'>+	memcpy(device_mode-&gt;aecs_comp_table-&gt;d_sym, mode-&gt;d_table, mode-&gt;d_table_size);</div><div class='add'>+</div><div class='add'>+	if (mode-&gt;header_table) {</div><div class='add'>+		ret = decompress_header(device_mode, mode, wq);</div><div class='add'>+		if (ret) {</div><div class='add'>+			pr_debug("iaa header decompression failed: ret=%d\n", ret);</div><div class='add'>+			goto free;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mode-&gt;init) {</div><div class='add'>+		ret = mode-&gt;init(device_mode);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* mode index should match iaa_compression_modes idx */</div><div class='add'>+	iaa_device-&gt;compression_modes[idx] = device_mode;</div><div class='add'>+</div><div class='add'>+	pr_debug("IAA %s compression mode initialized for iaa device %d\n",</div><div class='add'>+		 mode-&gt;name, iaa_device-&gt;idxd-&gt;id);</div><div class='add'>+</div><div class='add'>+	ret = 0;</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+free:</div><div class='add'>+	pr_debug("IAA %s compression mode initialization failed for iaa device %d\n",</div><div class='add'>+		 mode-&gt;name, iaa_device-&gt;idxd-&gt;id);</div><div class='add'>+</div><div class='add'>+	free_device_compression_mode(iaa_device, device_mode);</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int init_device_compression_modes(struct iaa_device *iaa_device,</div><div class='add'>+					 struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_compression_mode *mode;</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; IAA_COMP_MODES_MAX; i++) {</div><div class='add'>+		mode = iaa_compression_modes[i];</div><div class='add'>+		if (!mode)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ret = init_device_compression_mode(iaa_device, mode, i, wq);</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void remove_device_compression_modes(struct iaa_device *iaa_device)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device_compression_mode *device_mode;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; IAA_COMP_MODES_MAX; i++) {</div><div class='add'>+		device_mode = iaa_device-&gt;compression_modes[i];</div><div class='add'>+		if (!device_mode)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		free_device_compression_mode(iaa_device, device_mode);</div><div class='add'>+		iaa_device-&gt;compression_modes[i] = NULL;</div><div class='add'>+		if (iaa_compression_modes[i]-&gt;free)</div><div class='add'>+			iaa_compression_modes[i]-&gt;free(device_mode);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct iaa_device *iaa_device_alloc(void)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	iaa_device = kzalloc(sizeof(*iaa_device), GFP_KERNEL);</div><div class='add'>+	if (!iaa_device)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;iaa_device-&gt;wqs);</div><div class='add'>+</div><div class='add'>+	return iaa_device;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool iaa_has_wq(struct iaa_device *iaa_device, struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_wq, &amp;iaa_device-&gt;wqs, list) {</div><div class='add'>+		if (iaa_wq-&gt;wq == wq)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct iaa_device *add_iaa_device(struct idxd_device *idxd)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	iaa_device = iaa_device_alloc();</div><div class='add'>+	if (!iaa_device)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	iaa_device-&gt;idxd = idxd;</div><div class='add'>+</div><div class='add'>+	list_add_tail(&amp;iaa_device-&gt;list, &amp;iaa_devices);</div><div class='add'>+</div><div class='add'>+	nr_iaa++;</div><div class='add'>+</div><div class='add'>+	return iaa_device;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int init_iaa_device(struct iaa_device *iaa_device, struct iaa_wq *iaa_wq)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	ret = init_device_compression_modes(iaa_device, iaa_wq-&gt;wq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void del_iaa_device(struct iaa_device *iaa_device)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;iaa_device-&gt;list);</div><div class='add'>+</div><div class='add'>+	nr_iaa--;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int add_iaa_wq(struct iaa_device *iaa_device, struct idxd_wq *wq,</div><div class='add'>+		      struct iaa_wq **new_wq)</div><div class='add'>+{</div><div class='add'>+	struct idxd_device *idxd = iaa_device-&gt;idxd;</div><div class='add'>+	struct pci_dev *pdev = idxd-&gt;pdev;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+</div><div class='add'>+	iaa_wq = kzalloc(sizeof(*iaa_wq), GFP_KERNEL);</div><div class='add'>+	if (!iaa_wq)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	iaa_wq-&gt;wq = wq;</div><div class='add'>+	iaa_wq-&gt;iaa_device = iaa_device;</div><div class='add'>+	idxd_wq_set_private(wq, iaa_wq);</div><div class='add'>+</div><div class='add'>+	list_add_tail(&amp;iaa_wq-&gt;list, &amp;iaa_device-&gt;wqs);</div><div class='add'>+</div><div class='add'>+	iaa_device-&gt;n_wq++;</div><div class='add'>+</div><div class='add'>+	if (new_wq)</div><div class='add'>+		*new_wq = iaa_wq;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "added wq %d to iaa device %d, n_wq %d\n",</div><div class='add'>+		wq-&gt;id, iaa_device-&gt;idxd-&gt;id, iaa_device-&gt;n_wq);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void del_iaa_wq(struct iaa_device *iaa_device, struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct idxd_device *idxd = iaa_device-&gt;idxd;</div><div class='add'>+	struct pci_dev *pdev = idxd-&gt;pdev;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_wq, &amp;iaa_device-&gt;wqs, list) {</div><div class='add'>+		if (iaa_wq-&gt;wq == wq) {</div><div class='add'>+			list_del(&amp;iaa_wq-&gt;list);</div><div class='add'>+			iaa_device-&gt;n_wq--;</div><div class='add'>+</div><div class='add'>+			dev_dbg(dev, "removed wq %d from iaa_device %d, n_wq %d, nr_iaa %d\n",</div><div class='add'>+				wq-&gt;id, iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+				iaa_device-&gt;n_wq, nr_iaa);</div><div class='add'>+</div><div class='add'>+			if (iaa_device-&gt;n_wq == 0)</div><div class='add'>+				del_iaa_device(iaa_device);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_wq_table(void)</div><div class='add'>+{</div><div class='add'>+	int cpu;</div><div class='add'>+</div><div class='add'>+	for (cpu = 0; cpu &lt; nr_cpus; cpu++)</div><div class='add'>+		wq_table_clear_entry(cpu);</div><div class='add'>+</div><div class='add'>+	pr_debug("cleared wq table\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_iaa_device(struct iaa_device *iaa_device)</div><div class='add'>+{</div><div class='add'>+	if (!iaa_device)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	remove_device_compression_modes(iaa_device);</div><div class='add'>+	kfree(iaa_device);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __free_iaa_wq(struct iaa_wq *iaa_wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	if (!iaa_wq)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	iaa_device = iaa_wq-&gt;iaa_device;</div><div class='add'>+	if (iaa_device-&gt;n_wq == 0)</div><div class='add'>+		free_iaa_device(iaa_wq-&gt;iaa_device);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_iaa_wq(struct iaa_wq *iaa_wq)</div><div class='add'>+{</div><div class='add'>+	struct idxd_wq *wq;</div><div class='add'>+</div><div class='add'>+	__free_iaa_wq(iaa_wq);</div><div class='add'>+</div><div class='add'>+	wq = iaa_wq-&gt;wq;</div><div class='add'>+</div><div class='add'>+	kfree(iaa_wq);</div><div class='add'>+	idxd_wq_set_private(wq, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_wq_get(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	if (iaa_wq &amp;&amp; !iaa_wq-&gt;remove) {</div><div class='add'>+		iaa_wq-&gt;ref++;</div><div class='add'>+		idxd_wq_get(wq);</div><div class='add'>+	} else {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_wq_put(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	bool free = false;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	if (iaa_wq) {</div><div class='add'>+		iaa_wq-&gt;ref--;</div><div class='add'>+		if (iaa_wq-&gt;ref == 0 &amp;&amp; iaa_wq-&gt;remove) {</div><div class='add'>+			idxd_wq_set_private(wq, NULL);</div><div class='add'>+			free = true;</div><div class='add'>+		}</div><div class='add'>+		idxd_wq_put(wq);</div><div class='add'>+	} else {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+	if (free) {</div><div class='add'>+		__free_iaa_wq(iaa_wq);</div><div class='add'>+		kfree(iaa_wq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_wq_table(void)</div><div class='add'>+{</div><div class='add'>+	int cpu;</div><div class='add'>+</div><div class='add'>+	for (cpu = 0; cpu &lt; nr_cpus; cpu++)</div><div class='add'>+		wq_table_free_entry(cpu);</div><div class='add'>+</div><div class='add'>+	free_percpu(wq_table);</div><div class='add'>+</div><div class='add'>+	pr_debug("freed wq table\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alloc_wq_table(int max_wqs)</div><div class='add'>+{</div><div class='add'>+	struct wq_table_entry *entry;</div><div class='add'>+	int cpu;</div><div class='add'>+</div><div class='add'>+	wq_table = alloc_percpu(struct wq_table_entry);</div><div class='add'>+	if (!wq_table)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (cpu = 0; cpu &lt; nr_cpus; cpu++) {</div><div class='add'>+		entry = per_cpu_ptr(wq_table, cpu);</div><div class='add'>+		entry-&gt;wqs = kcalloc(max_wqs, sizeof(struct wq *), GFP_KERNEL);</div><div class='add'>+		if (!entry-&gt;wqs) {</div><div class='add'>+			free_wq_table();</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		entry-&gt;max_wqs = max_wqs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pr_debug("initialized wq table\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int save_iaa_wq(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device, *found = NULL;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_device, &amp;iaa_devices, list) {</div><div class='add'>+		if (iaa_device-&gt;idxd == wq-&gt;idxd) {</div><div class='add'>+			idxd = iaa_device-&gt;idxd;</div><div class='add'>+			pdev = idxd-&gt;pdev;</div><div class='add'>+			dev = &amp;pdev-&gt;dev;</div><div class='add'>+			/*</div><div class='add'>+			 * Check to see that we don't already have this wq.</div><div class='add'>+			 * Shouldn't happen but we don't control probing.</div><div class='add'>+			 */</div><div class='add'>+			if (iaa_has_wq(iaa_device, wq)) {</div><div class='add'>+				dev_dbg(dev, "same wq probed multiple times for iaa_device %p\n",</div><div class='add'>+					iaa_device);</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			found = iaa_device;</div><div class='add'>+</div><div class='add'>+			ret = add_iaa_wq(iaa_device, wq, NULL);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto out;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!found) {</div><div class='add'>+		struct iaa_device *new_device;</div><div class='add'>+		struct iaa_wq *new_wq;</div><div class='add'>+</div><div class='add'>+		new_device = add_iaa_device(wq-&gt;idxd);</div><div class='add'>+		if (!new_device) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = add_iaa_wq(new_device, wq, &amp;new_wq);</div><div class='add'>+		if (ret) {</div><div class='add'>+			del_iaa_device(new_device);</div><div class='add'>+			free_iaa_device(new_device);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = init_iaa_device(new_device, new_wq);</div><div class='add'>+		if (ret) {</div><div class='add'>+			del_iaa_wq(new_device, new_wq-&gt;wq);</div><div class='add'>+			del_iaa_device(new_device);</div><div class='add'>+			free_iaa_wq(new_wq);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(nr_iaa == 0))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cpus_per_iaa = (nr_nodes * nr_cpus_per_node) / nr_iaa;</div><div class='add'>+out:</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void remove_iaa_wq(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_device, &amp;iaa_devices, list) {</div><div class='add'>+		if (iaa_has_wq(iaa_device, wq)) {</div><div class='add'>+			del_iaa_wq(iaa_device, wq);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (nr_iaa)</div><div class='add'>+		cpus_per_iaa = (nr_nodes * nr_cpus_per_node) / nr_iaa;</div><div class='add'>+	else</div><div class='add'>+		cpus_per_iaa = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wq_table_add_wqs(int iaa, int cpu)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device, *found_device = NULL;</div><div class='add'>+	int ret = 0, cur_iaa = 0, n_wqs_added = 0;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_device, &amp;iaa_devices, list) {</div><div class='add'>+		idxd = iaa_device-&gt;idxd;</div><div class='add'>+		pdev = idxd-&gt;pdev;</div><div class='add'>+		dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+		if (cur_iaa != iaa) {</div><div class='add'>+			cur_iaa++;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		found_device = iaa_device;</div><div class='add'>+		dev_dbg(dev, "getting wq from iaa_device %d, cur_iaa %d\n",</div><div class='add'>+			found_device-&gt;idxd-&gt;id, cur_iaa);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!found_device) {</div><div class='add'>+		found_device = list_first_entry_or_null(&amp;iaa_devices,</div><div class='add'>+							struct iaa_device, list);</div><div class='add'>+		if (!found_device) {</div><div class='add'>+			pr_debug("couldn't find any iaa devices with wqs!\n");</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+		cur_iaa = 0;</div><div class='add'>+</div><div class='add'>+		idxd = found_device-&gt;idxd;</div><div class='add'>+		pdev = idxd-&gt;pdev;</div><div class='add'>+		dev = &amp;pdev-&gt;dev;</div><div class='add'>+		dev_dbg(dev, "getting wq from only iaa_device %d, cur_iaa %d\n",</div><div class='add'>+			found_device-&gt;idxd-&gt;id, cur_iaa);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_wq, &amp;found_device-&gt;wqs, list) {</div><div class='add'>+		wq_table_add(cpu, iaa_wq-&gt;wq);</div><div class='add'>+		pr_debug("rebalance: added wq for cpu=%d: iaa wq %d.%d\n",</div><div class='add'>+			 cpu, iaa_wq-&gt;wq-&gt;idxd-&gt;id, iaa_wq-&gt;wq-&gt;id);</div><div class='add'>+		n_wqs_added++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!n_wqs_added) {</div><div class='add'>+		pr_debug("couldn't find any iaa wqs!\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Rebalance the wq table so that given a cpu, it's easy to find the</div><div class='add'>+ * closest IAA instance.  The idea is to try to choose the most</div><div class='add'>+ * appropriate IAA instance for a caller and spread available</div><div class='add'>+ * workqueues around to clients.</div><div class='add'>+ */</div><div class='add'>+static void rebalance_wq_table(void)</div><div class='add'>+{</div><div class='add'>+	const struct cpumask *node_cpus;</div><div class='add'>+	int node, cpu, iaa = -1;</div><div class='add'>+</div><div class='add'>+	if (nr_iaa == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pr_debug("rebalance: nr_nodes=%d, nr_cpus %d, nr_iaa %d, cpus_per_iaa %d\n",</div><div class='add'>+		 nr_nodes, nr_cpus, nr_iaa, cpus_per_iaa);</div><div class='add'>+</div><div class='add'>+	clear_wq_table();</div><div class='add'>+</div><div class='add'>+	if (nr_iaa == 1) {</div><div class='add'>+		for (cpu = 0; cpu &lt; nr_cpus; cpu++) {</div><div class='add'>+			if (WARN_ON(wq_table_add_wqs(0, cpu))) {</div><div class='add'>+				pr_debug("could not add any wqs for iaa 0 to cpu %d!\n", cpu);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_node_with_cpus(node) {</div><div class='add'>+		node_cpus = cpumask_of_node(node);</div><div class='add'>+</div><div class='add'>+		for (cpu = 0; cpu &lt; nr_cpus_per_node; cpu++) {</div><div class='add'>+			int node_cpu = cpumask_nth(cpu, node_cpus);</div><div class='add'>+</div><div class='add'>+			if (WARN_ON(node_cpu &gt;= nr_cpu_ids)) {</div><div class='add'>+				pr_debug("node_cpu %d doesn't exist!\n", node_cpu);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if ((cpu % cpus_per_iaa) == 0)</div><div class='add'>+				iaa++;</div><div class='add'>+</div><div class='add'>+			if (WARN_ON(wq_table_add_wqs(iaa, node_cpu))) {</div><div class='add'>+				pr_debug("could not add any wqs for iaa %d to cpu %d!\n", iaa, cpu);</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int check_completion(struct device *dev,</div><div class='add'>+				   struct iax_completion_record *comp,</div><div class='add'>+				   bool compress,</div><div class='add'>+				   bool only_once)</div><div class='add'>+{</div><div class='add'>+	char *op_str = compress ? "compress" : "decompress";</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	while (!comp-&gt;status) {</div><div class='add'>+		if (only_once)</div><div class='add'>+			return -EAGAIN;</div><div class='add'>+		cpu_relax();</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (comp-&gt;status != IAX_COMP_SUCCESS) {</div><div class='add'>+		if (comp-&gt;status == IAA_ERROR_WATCHDOG_EXPIRED) {</div><div class='add'>+			ret = -ETIMEDOUT;</div><div class='add'>+			dev_dbg(dev, "%s timed out, size=0x%x\n",</div><div class='add'>+				op_str, comp-&gt;output_size);</div><div class='add'>+			update_completion_timeout_errs();</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (comp-&gt;status == IAA_ANALYTICS_ERROR &amp;&amp;</div><div class='add'>+		    comp-&gt;error_code == IAA_ERROR_COMP_BUF_OVERFLOW &amp;&amp; compress) {</div><div class='add'>+			ret = -E2BIG;</div><div class='add'>+			dev_dbg(dev, "compressed &gt; uncompressed size,"</div><div class='add'>+				" not compressing, size=0x%x\n",</div><div class='add'>+				comp-&gt;output_size);</div><div class='add'>+			update_completion_comp_buf_overflow_errs();</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (comp-&gt;status == IAA_ERROR_DECOMP_BUF_OVERFLOW) {</div><div class='add'>+			ret = -EOVERFLOW;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		dev_dbg(dev, "iaa %s status=0x%x, error=0x%x, size=0x%x\n",</div><div class='add'>+			op_str, comp-&gt;status, comp-&gt;error_code, comp-&gt;output_size);</div><div class='add'>+		print_hex_dump(KERN_INFO, "cmp-rec: ", DUMP_PREFIX_OFFSET, 8, 1, comp, 64, 0);</div><div class='add'>+		update_completion_einval_errs();</div><div class='add'>+</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int deflate_generic_decompress(struct acomp_req *req)</div><div class='add'>+{</div><div class='add'>+	void *src, *dst;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	src = kmap_local_page(sg_page(req-&gt;src)) + req-&gt;src-&gt;offset;</div><div class='add'>+	dst = kmap_local_page(sg_page(req-&gt;dst)) + req-&gt;dst-&gt;offset;</div><div class='add'>+</div><div class='add'>+	ret = crypto_comp_decompress(deflate_generic_tfm,</div><div class='add'>+				     src, req-&gt;slen, dst, &amp;req-&gt;dlen);</div><div class='add'>+</div><div class='add'>+	kunmap_local(src);</div><div class='add'>+	kunmap_local(dst);</div><div class='add'>+</div><div class='add'>+	update_total_sw_decomp_calls();</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_remap_for_verify(struct device *dev, struct iaa_wq *iaa_wq,</div><div class='add'>+				struct acomp_req *req,</div><div class='add'>+				dma_addr_t *src_addr, dma_addr_t *dst_addr);</div><div class='add'>+</div><div class='add'>+static int iaa_compress_verify(struct crypto_tfm *tfm, struct acomp_req *req,</div><div class='add'>+			       struct idxd_wq *wq,</div><div class='add'>+			       dma_addr_t src_addr, unsigned int slen,</div><div class='add'>+			       dma_addr_t dst_addr, unsigned int *dlen,</div><div class='add'>+			       u32 compression_crc);</div><div class='add'>+</div><div class='add'>+static void iaa_desc_complete(struct idxd_desc *idxd_desc,</div><div class='add'>+			      enum idxd_complete_type comp_type,</div><div class='add'>+			      bool free_desc, void *__ctx,</div><div class='add'>+			      u32 *status)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device_compression_mode *active_compression_mode;</div><div class='add'>+	struct iaa_compression_ctx *compression_ctx;</div><div class='add'>+	struct crypto_ctx *ctx = __ctx;</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret, err = 0;</div><div class='add'>+</div><div class='add'>+	compression_ctx = crypto_tfm_ctx(ctx-&gt;tfm);</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(idxd_desc-&gt;wq);</div><div class='add'>+	iaa_device = iaa_wq-&gt;iaa_device;</div><div class='add'>+	idxd = iaa_device-&gt;idxd;</div><div class='add'>+	pdev = idxd-&gt;pdev;</div><div class='add'>+	dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	active_compression_mode = get_iaa_device_compression_mode(iaa_device,</div><div class='add'>+								  compression_ctx-&gt;mode);</div><div class='add'>+	dev_dbg(dev, "%s: compression mode %s,"</div><div class='add'>+		" ctx-&gt;src_addr %llx, ctx-&gt;dst_addr %llx\n", __func__,</div><div class='add'>+		active_compression_mode-&gt;name,</div><div class='add'>+		ctx-&gt;src_addr, ctx-&gt;dst_addr);</div><div class='add'>+</div><div class='add'>+	ret = check_completion(dev, idxd_desc-&gt;iax_completion,</div><div class='add'>+			       ctx-&gt;compress, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "%s: check_completion failed ret=%d\n", __func__, ret);</div><div class='add'>+		if (!ctx-&gt;compress &amp;&amp;</div><div class='add'>+		    idxd_desc-&gt;iax_completion-&gt;status == IAA_ANALYTICS_ERROR) {</div><div class='add'>+			pr_warn("%s: falling back to deflate-generic decompress, "</div><div class='add'>+				"analytics error code %x\n", __func__,</div><div class='add'>+				idxd_desc-&gt;iax_completion-&gt;error_code);</div><div class='add'>+			ret = deflate_generic_decompress(ctx-&gt;req);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_dbg(dev, "%s: deflate-generic failed ret=%d\n",</div><div class='add'>+					__func__, ret);</div><div class='add'>+				err = -EIO;</div><div class='add'>+				goto err;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			err = -EIO;</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		ctx-&gt;req-&gt;dlen = idxd_desc-&gt;iax_completion-&gt;output_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update stats */</div><div class='add'>+	if (ctx-&gt;compress) {</div><div class='add'>+		update_total_comp_bytes_out(ctx-&gt;req-&gt;dlen);</div><div class='add'>+		update_wq_comp_bytes(iaa_wq-&gt;wq, ctx-&gt;req-&gt;dlen);</div><div class='add'>+	} else {</div><div class='add'>+		update_total_decomp_bytes_in(ctx-&gt;req-&gt;dlen);</div><div class='add'>+		update_wq_decomp_bytes(iaa_wq-&gt;wq, ctx-&gt;req-&gt;dlen);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;compress &amp;&amp; compression_ctx-&gt;verify_compress) {</div><div class='add'>+		dma_addr_t src_addr, dst_addr;</div><div class='add'>+		u32 compression_crc;</div><div class='add'>+</div><div class='add'>+		compression_crc = idxd_desc-&gt;iax_completion-&gt;crc;</div><div class='add'>+</div><div class='add'>+		ret = iaa_remap_for_verify(dev, iaa_wq, ctx-&gt;req, &amp;src_addr, &amp;dst_addr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(dev, "%s: compress verify remap failed ret=%d\n", __func__, ret);</div><div class='add'>+			err = -EIO;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = iaa_compress_verify(ctx-&gt;tfm, ctx-&gt;req, iaa_wq-&gt;wq, src_addr,</div><div class='add'>+					  ctx-&gt;req-&gt;slen, dst_addr, &amp;ctx-&gt;req-&gt;dlen,</div><div class='add'>+					  compression_crc);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(dev, "%s: compress verify failed ret=%d\n", __func__, ret);</div><div class='add'>+			err = -EIO;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dma_unmap_sg(dev, ctx-&gt;req-&gt;dst, sg_nents(ctx-&gt;req-&gt;dst), DMA_TO_DEVICE);</div><div class='add'>+		dma_unmap_sg(dev, ctx-&gt;req-&gt;src, sg_nents(ctx-&gt;req-&gt;src), DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+err:</div><div class='add'>+	dma_unmap_sg(dev, ctx-&gt;req-&gt;dst, sg_nents(ctx-&gt;req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+	dma_unmap_sg(dev, ctx-&gt;req-&gt;src, sg_nents(ctx-&gt;req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+out:</div><div class='add'>+	if (ret != 0)</div><div class='add'>+		dev_dbg(dev, "asynchronous compress failed ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;req-&gt;base.complete)</div><div class='add'>+		acomp_request_complete(ctx-&gt;req, err);</div><div class='add'>+</div><div class='add'>+	if (free_desc)</div><div class='add'>+		idxd_free_desc(idxd_desc-&gt;wq, idxd_desc);</div><div class='add'>+	iaa_wq_put(idxd_desc-&gt;wq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_compress(struct crypto_tfm *tfm,	struct acomp_req *req,</div><div class='add'>+			struct idxd_wq *wq,</div><div class='add'>+			dma_addr_t src_addr, unsigned int slen,</div><div class='add'>+			dma_addr_t dst_addr, unsigned int *dlen,</div><div class='add'>+			u32 *compression_crc,</div><div class='add'>+			bool disable_async)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device_compression_mode *active_compression_mode;</div><div class='add'>+	struct iaa_compression_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+	struct idxd_desc *idxd_desc;</div><div class='add'>+	struct iax_hw_desc *desc;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	iaa_device = iaa_wq-&gt;iaa_device;</div><div class='add'>+	idxd = iaa_device-&gt;idxd;</div><div class='add'>+	pdev = idxd-&gt;pdev;</div><div class='add'>+	dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	active_compression_mode = get_iaa_device_compression_mode(iaa_device, ctx-&gt;mode);</div><div class='add'>+</div><div class='add'>+	idxd_desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);</div><div class='add'>+	if (IS_ERR(idxd_desc)) {</div><div class='add'>+		dev_dbg(dev, "idxd descriptor allocation failed\n");</div><div class='add'>+		dev_dbg(dev, "iaa compress failed: ret=%ld\n", PTR_ERR(idxd_desc));</div><div class='add'>+		return PTR_ERR(idxd_desc);</div><div class='add'>+	}</div><div class='add'>+	desc = idxd_desc-&gt;iax_hw;</div><div class='add'>+</div><div class='add'>+	desc-&gt;flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR |</div><div class='add'>+		IDXD_OP_FLAG_RD_SRC2_AECS | IDXD_OP_FLAG_CC;</div><div class='add'>+	desc-&gt;opcode = IAX_OPCODE_COMPRESS;</div><div class='add'>+	desc-&gt;compr_flags = IAA_COMP_FLAGS;</div><div class='add'>+	desc-&gt;priv = 0;</div><div class='add'>+</div><div class='add'>+	desc-&gt;src1_addr = (u64)src_addr;</div><div class='add'>+	desc-&gt;src1_size = slen;</div><div class='add'>+	desc-&gt;dst_addr = (u64)dst_addr;</div><div class='add'>+	desc-&gt;max_dst_size = *dlen;</div><div class='add'>+	desc-&gt;src2_addr = active_compression_mode-&gt;aecs_comp_table_dma_addr;</div><div class='add'>+	desc-&gt;src2_size = sizeof(struct aecs_comp_table_record);</div><div class='add'>+	desc-&gt;completion_addr = idxd_desc-&gt;compl_dma;</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;use_irq &amp;&amp; !disable_async) {</div><div class='add'>+		desc-&gt;flags |= IDXD_OP_FLAG_RCI;</div><div class='add'>+</div><div class='add'>+		idxd_desc-&gt;crypto.req = req;</div><div class='add'>+		idxd_desc-&gt;crypto.tfm = tfm;</div><div class='add'>+		idxd_desc-&gt;crypto.src_addr = src_addr;</div><div class='add'>+		idxd_desc-&gt;crypto.dst_addr = dst_addr;</div><div class='add'>+		idxd_desc-&gt;crypto.compress = true;</div><div class='add'>+</div><div class='add'>+		dev_dbg(dev, "%s use_async_irq: compression mode %s,"</div><div class='add'>+			" src_addr %llx, dst_addr %llx\n", __func__,</div><div class='add'>+			active_compression_mode-&gt;name,</div><div class='add'>+			src_addr, dst_addr);</div><div class='add'>+	} else if (ctx-&gt;async_mode &amp;&amp; !disable_async)</div><div class='add'>+		req-&gt;base.data = idxd_desc;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "%s: compression mode %s,"</div><div class='add'>+		" desc-&gt;src1_addr %llx, desc-&gt;src1_size %d,"</div><div class='add'>+		" desc-&gt;dst_addr %llx, desc-&gt;max_dst_size %d,"</div><div class='add'>+		" desc-&gt;src2_addr %llx, desc-&gt;src2_size %d\n", __func__,</div><div class='add'>+		active_compression_mode-&gt;name,</div><div class='add'>+		desc-&gt;src1_addr, desc-&gt;src1_size, desc-&gt;dst_addr,</div><div class='add'>+		desc-&gt;max_dst_size, desc-&gt;src2_addr, desc-&gt;src2_size);</div><div class='add'>+</div><div class='add'>+	ret = idxd_submit_desc(wq, idxd_desc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "submit_desc failed ret=%d\n", ret);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update stats */</div><div class='add'>+	update_total_comp_calls();</div><div class='add'>+	update_wq_comp_calls(wq);</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;async_mode &amp;&amp; !disable_async) {</div><div class='add'>+		ret = -EINPROGRESS;</div><div class='add'>+		dev_dbg(dev, "%s: returning -EINPROGRESS\n", __func__);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = check_completion(dev, idxd_desc-&gt;iax_completion, true, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "check_completion failed ret=%d\n", ret);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*dlen = idxd_desc-&gt;iax_completion-&gt;output_size;</div><div class='add'>+</div><div class='add'>+	/* Update stats */</div><div class='add'>+	update_total_comp_bytes_out(*dlen);</div><div class='add'>+	update_wq_comp_bytes(wq, *dlen);</div><div class='add'>+</div><div class='add'>+	*compression_crc = idxd_desc-&gt;iax_completion-&gt;crc;</div><div class='add'>+</div><div class='add'>+	if (!ctx-&gt;async_mode)</div><div class='add'>+		idxd_free_desc(wq, idxd_desc);</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+err:</div><div class='add'>+	idxd_free_desc(wq, idxd_desc);</div><div class='add'>+	dev_dbg(dev, "iaa compress failed: ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_remap_for_verify(struct device *dev, struct iaa_wq *iaa_wq,</div><div class='add'>+				struct acomp_req *req,</div><div class='add'>+				dma_addr_t *src_addr, dma_addr_t *dst_addr)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	int nr_sgs;</div><div class='add'>+</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_FROM_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "verify: couldn't map src sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	*src_addr = sg_dma_address(req-&gt;src);</div><div class='add'>+	dev_dbg(dev, "verify: dma_map_sg, src_addr %llx, nr_sgs %d, req-&gt;src %p,"</div><div class='add'>+		" req-&gt;slen %d, sg_dma_len(sg) %d\n", *src_addr, nr_sgs,</div><div class='add'>+		req-&gt;src, req-&gt;slen, sg_dma_len(req-&gt;src));</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_TO_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "verify: couldn't map dst sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_FROM_DEVICE);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	*dst_addr = sg_dma_address(req-&gt;dst);</div><div class='add'>+	dev_dbg(dev, "verify: dma_map_sg, dst_addr %llx, nr_sgs %d, req-&gt;dst %p,"</div><div class='add'>+		" req-&gt;dlen %d, sg_dma_len(sg) %d\n", *dst_addr, nr_sgs,</div><div class='add'>+		req-&gt;dst, req-&gt;dlen, sg_dma_len(req-&gt;dst));</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_compress_verify(struct crypto_tfm *tfm, struct acomp_req *req,</div><div class='add'>+			       struct idxd_wq *wq,</div><div class='add'>+			       dma_addr_t src_addr, unsigned int slen,</div><div class='add'>+			       dma_addr_t dst_addr, unsigned int *dlen,</div><div class='add'>+			       u32 compression_crc)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device_compression_mode *active_compression_mode;</div><div class='add'>+	struct iaa_compression_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+	struct idxd_desc *idxd_desc;</div><div class='add'>+	struct iax_hw_desc *desc;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	iaa_device = iaa_wq-&gt;iaa_device;</div><div class='add'>+	idxd = iaa_device-&gt;idxd;</div><div class='add'>+	pdev = idxd-&gt;pdev;</div><div class='add'>+	dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	active_compression_mode = get_iaa_device_compression_mode(iaa_device, ctx-&gt;mode);</div><div class='add'>+</div><div class='add'>+	idxd_desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);</div><div class='add'>+	if (IS_ERR(idxd_desc)) {</div><div class='add'>+		dev_dbg(dev, "idxd descriptor allocation failed\n");</div><div class='add'>+		dev_dbg(dev, "iaa compress failed: ret=%ld\n",</div><div class='add'>+			PTR_ERR(idxd_desc));</div><div class='add'>+		return PTR_ERR(idxd_desc);</div><div class='add'>+	}</div><div class='add'>+	desc = idxd_desc-&gt;iax_hw;</div><div class='add'>+</div><div class='add'>+	/* Verify (optional) - decompress and check crc, suppress dest write */</div><div class='add'>+</div><div class='add'>+	desc-&gt;flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CC;</div><div class='add'>+	desc-&gt;opcode = IAX_OPCODE_DECOMPRESS;</div><div class='add'>+	desc-&gt;decompr_flags = IAA_DECOMP_FLAGS | IAA_DECOMP_SUPPRESS_OUTPUT;</div><div class='add'>+	desc-&gt;priv = 0;</div><div class='add'>+</div><div class='add'>+	desc-&gt;src1_addr = (u64)dst_addr;</div><div class='add'>+	desc-&gt;src1_size = *dlen;</div><div class='add'>+	desc-&gt;dst_addr = (u64)src_addr;</div><div class='add'>+	desc-&gt;max_dst_size = slen;</div><div class='add'>+	desc-&gt;completion_addr = idxd_desc-&gt;compl_dma;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "(verify) compression mode %s,"</div><div class='add'>+		" desc-&gt;src1_addr %llx, desc-&gt;src1_size %d,"</div><div class='add'>+		" desc-&gt;dst_addr %llx, desc-&gt;max_dst_size %d,"</div><div class='add'>+		" desc-&gt;src2_addr %llx, desc-&gt;src2_size %d\n",</div><div class='add'>+		active_compression_mode-&gt;name,</div><div class='add'>+		desc-&gt;src1_addr, desc-&gt;src1_size, desc-&gt;dst_addr,</div><div class='add'>+		desc-&gt;max_dst_size, desc-&gt;src2_addr, desc-&gt;src2_size);</div><div class='add'>+</div><div class='add'>+	ret = idxd_submit_desc(wq, idxd_desc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "submit_desc (verify) failed ret=%d\n", ret);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = check_completion(dev, idxd_desc-&gt;iax_completion, false, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "(verify) check_completion failed ret=%d\n", ret);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (compression_crc != idxd_desc-&gt;iax_completion-&gt;crc) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		dev_dbg(dev, "(verify) iaa comp/decomp crc mismatch:"</div><div class='add'>+			" comp=0x%x, decomp=0x%x\n", compression_crc,</div><div class='add'>+			idxd_desc-&gt;iax_completion-&gt;crc);</div><div class='add'>+		print_hex_dump(KERN_INFO, "cmp-rec: ", DUMP_PREFIX_OFFSET,</div><div class='add'>+			       8, 1, idxd_desc-&gt;iax_completion, 64, 0);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	idxd_free_desc(wq, idxd_desc);</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+err:</div><div class='add'>+	idxd_free_desc(wq, idxd_desc);</div><div class='add'>+	dev_dbg(dev, "iaa compress failed: ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_decompress(struct crypto_tfm *tfm, struct acomp_req *req,</div><div class='add'>+			  struct idxd_wq *wq,</div><div class='add'>+			  dma_addr_t src_addr, unsigned int slen,</div><div class='add'>+			  dma_addr_t dst_addr, unsigned int *dlen,</div><div class='add'>+			  bool disable_async)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device_compression_mode *active_compression_mode;</div><div class='add'>+	struct iaa_compression_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+	struct idxd_desc *idxd_desc;</div><div class='add'>+	struct iax_hw_desc *desc;</div><div class='add'>+	struct idxd_device *idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	iaa_device = iaa_wq-&gt;iaa_device;</div><div class='add'>+	idxd = iaa_device-&gt;idxd;</div><div class='add'>+	pdev = idxd-&gt;pdev;</div><div class='add'>+	dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	active_compression_mode = get_iaa_device_compression_mode(iaa_device, ctx-&gt;mode);</div><div class='add'>+</div><div class='add'>+	idxd_desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);</div><div class='add'>+	if (IS_ERR(idxd_desc)) {</div><div class='add'>+		dev_dbg(dev, "idxd descriptor allocation failed\n");</div><div class='add'>+		dev_dbg(dev, "iaa decompress failed: ret=%ld\n",</div><div class='add'>+			PTR_ERR(idxd_desc));</div><div class='add'>+		return PTR_ERR(idxd_desc);</div><div class='add'>+	}</div><div class='add'>+	desc = idxd_desc-&gt;iax_hw;</div><div class='add'>+</div><div class='add'>+	desc-&gt;flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CC;</div><div class='add'>+	desc-&gt;opcode = IAX_OPCODE_DECOMPRESS;</div><div class='add'>+	desc-&gt;max_dst_size = PAGE_SIZE;</div><div class='add'>+	desc-&gt;decompr_flags = IAA_DECOMP_FLAGS;</div><div class='add'>+	desc-&gt;priv = 0;</div><div class='add'>+</div><div class='add'>+	desc-&gt;src1_addr = (u64)src_addr;</div><div class='add'>+	desc-&gt;dst_addr = (u64)dst_addr;</div><div class='add'>+	desc-&gt;max_dst_size = *dlen;</div><div class='add'>+	desc-&gt;src1_size = slen;</div><div class='add'>+	desc-&gt;completion_addr = idxd_desc-&gt;compl_dma;</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;use_irq &amp;&amp; !disable_async) {</div><div class='add'>+		desc-&gt;flags |= IDXD_OP_FLAG_RCI;</div><div class='add'>+</div><div class='add'>+		idxd_desc-&gt;crypto.req = req;</div><div class='add'>+		idxd_desc-&gt;crypto.tfm = tfm;</div><div class='add'>+		idxd_desc-&gt;crypto.src_addr = src_addr;</div><div class='add'>+		idxd_desc-&gt;crypto.dst_addr = dst_addr;</div><div class='add'>+		idxd_desc-&gt;crypto.compress = false;</div><div class='add'>+</div><div class='add'>+		dev_dbg(dev, "%s: use_async_irq compression mode %s,"</div><div class='add'>+			" src_addr %llx, dst_addr %llx\n", __func__,</div><div class='add'>+			active_compression_mode-&gt;name,</div><div class='add'>+			src_addr, dst_addr);</div><div class='add'>+	} else if (ctx-&gt;async_mode &amp;&amp; !disable_async)</div><div class='add'>+		req-&gt;base.data = idxd_desc;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "%s: decompression mode %s,"</div><div class='add'>+		" desc-&gt;src1_addr %llx, desc-&gt;src1_size %d,"</div><div class='add'>+		" desc-&gt;dst_addr %llx, desc-&gt;max_dst_size %d,"</div><div class='add'>+		" desc-&gt;src2_addr %llx, desc-&gt;src2_size %d\n", __func__,</div><div class='add'>+		active_compression_mode-&gt;name,</div><div class='add'>+		desc-&gt;src1_addr, desc-&gt;src1_size, desc-&gt;dst_addr,</div><div class='add'>+		desc-&gt;max_dst_size, desc-&gt;src2_addr, desc-&gt;src2_size);</div><div class='add'>+</div><div class='add'>+	ret = idxd_submit_desc(wq, idxd_desc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "submit_desc failed ret=%d\n", ret);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update stats */</div><div class='add'>+	update_total_decomp_calls();</div><div class='add'>+	update_wq_decomp_calls(wq);</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;async_mode &amp;&amp; !disable_async) {</div><div class='add'>+		ret = -EINPROGRESS;</div><div class='add'>+		dev_dbg(dev, "%s: returning -EINPROGRESS\n", __func__);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = check_completion(dev, idxd_desc-&gt;iax_completion, false, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(dev, "%s: check_completion failed ret=%d\n", __func__, ret);</div><div class='add'>+		if (idxd_desc-&gt;iax_completion-&gt;status == IAA_ANALYTICS_ERROR) {</div><div class='add'>+			pr_warn("%s: falling back to deflate-generic decompress, "</div><div class='add'>+				"analytics error code %x\n", __func__,</div><div class='add'>+				idxd_desc-&gt;iax_completion-&gt;error_code);</div><div class='add'>+			ret = deflate_generic_decompress(req);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_dbg(dev, "%s: deflate-generic failed ret=%d\n",</div><div class='add'>+					__func__, ret);</div><div class='add'>+				goto err;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		req-&gt;dlen = idxd_desc-&gt;iax_completion-&gt;output_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*dlen = req-&gt;dlen;</div><div class='add'>+</div><div class='add'>+	if (!ctx-&gt;async_mode)</div><div class='add'>+		idxd_free_desc(wq, idxd_desc);</div><div class='add'>+</div><div class='add'>+	/* Update stats */</div><div class='add'>+	update_total_decomp_bytes_in(slen);</div><div class='add'>+	update_wq_decomp_bytes(wq, slen);</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+err:</div><div class='add'>+	idxd_free_desc(wq, idxd_desc);</div><div class='add'>+	dev_dbg(dev, "iaa decompress failed: ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_comp_acompress(struct acomp_req *req)</div><div class='add'>+{</div><div class='add'>+	struct iaa_compression_ctx *compression_ctx;</div><div class='add'>+	struct crypto_tfm *tfm = req-&gt;base.tfm;</div><div class='add'>+	dma_addr_t src_addr, dst_addr;</div><div class='add'>+	bool disable_async = false;</div><div class='add'>+	int nr_sgs, cpu, ret = 0;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	u32 compression_crc;</div><div class='add'>+	struct idxd_wq *wq;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int order = -1;</div><div class='add'>+</div><div class='add'>+	compression_ctx = crypto_tfm_ctx(tfm);</div><div class='add'>+</div><div class='add'>+	if (!iaa_crypto_enabled) {</div><div class='add'>+		pr_debug("iaa_crypto disabled, not compressing\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;src || !req-&gt;slen) {</div><div class='add'>+		pr_debug("invalid src, not compressing\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cpu = get_cpu();</div><div class='add'>+	wq = wq_table_next_wq(cpu);</div><div class='add'>+	put_cpu();</div><div class='add'>+	if (!wq) {</div><div class='add'>+		pr_debug("no wq configured for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = iaa_wq_get(wq);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("no wq available for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;dst) {</div><div class='add'>+		gfp_t flags = req-&gt;flags &amp; CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC;</div><div class='add'>+</div><div class='add'>+		/* incompressible data will always be &lt; 2 * slen */</div><div class='add'>+		req-&gt;dlen = 2 * req-&gt;slen;</div><div class='add'>+		order = order_base_2(round_up(req-&gt;dlen, PAGE_SIZE) / PAGE_SIZE);</div><div class='add'>+		req-&gt;dst = sgl_alloc_order(req-&gt;dlen, order, false, flags, NULL);</div><div class='add'>+		if (!req-&gt;dst) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			order = -1;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+		disable_async = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev = &amp;wq-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map src sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	src_addr = sg_dma_address(req-&gt;src);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, src_addr %llx, nr_sgs %d, req-&gt;src %p,"</div><div class='add'>+		" req-&gt;slen %d, sg_dma_len(sg) %d\n", src_addr, nr_sgs,</div><div class='add'>+		req-&gt;src, req-&gt;slen, sg_dma_len(req-&gt;src));</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map dst sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto err_map_dst;</div><div class='add'>+	}</div><div class='add'>+	dst_addr = sg_dma_address(req-&gt;dst);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, dst_addr %llx, nr_sgs %d, req-&gt;dst %p,"</div><div class='add'>+		" req-&gt;dlen %d, sg_dma_len(sg) %d\n", dst_addr, nr_sgs,</div><div class='add'>+		req-&gt;dst, req-&gt;dlen, sg_dma_len(req-&gt;dst));</div><div class='add'>+</div><div class='add'>+	ret = iaa_compress(tfm, req, wq, src_addr, req-&gt;slen, dst_addr,</div><div class='add'>+			   &amp;req-&gt;dlen, &amp;compression_crc, disable_async);</div><div class='add'>+	if (ret == -EINPROGRESS)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!ret &amp;&amp; compression_ctx-&gt;verify_compress) {</div><div class='add'>+		ret = iaa_remap_for_verify(dev, iaa_wq, req, &amp;src_addr, &amp;dst_addr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(dev, "%s: compress verify remap failed ret=%d\n", __func__, ret);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = iaa_compress_verify(tfm, req, wq, src_addr, req-&gt;slen,</div><div class='add'>+					  dst_addr, &amp;req-&gt;dlen, compression_crc);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_dbg(dev, "asynchronous compress verification failed ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+		dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_TO_DEVICE);</div><div class='add'>+		dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_dbg(dev, "asynchronous compress failed ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+err_map_dst:</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+out:</div><div class='add'>+	iaa_wq_put(wq);</div><div class='add'>+</div><div class='add'>+	if (order &gt;= 0)</div><div class='add'>+		sgl_free_order(req-&gt;dst, order);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_comp_adecompress_alloc_dest(struct acomp_req *req)</div><div class='add'>+{</div><div class='add'>+	gfp_t flags = req-&gt;flags &amp; CRYPTO_TFM_REQ_MAY_SLEEP ?</div><div class='add'>+		GFP_KERNEL : GFP_ATOMIC;</div><div class='add'>+	struct crypto_tfm *tfm = req-&gt;base.tfm;</div><div class='add'>+	dma_addr_t src_addr, dst_addr;</div><div class='add'>+	int nr_sgs, cpu, ret = 0;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct idxd_wq *wq;</div><div class='add'>+	int order = -1;</div><div class='add'>+</div><div class='add'>+	cpu = get_cpu();</div><div class='add'>+	wq = wq_table_next_wq(cpu);</div><div class='add'>+	put_cpu();</div><div class='add'>+	if (!wq) {</div><div class='add'>+		pr_debug("no wq configured for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = iaa_wq_get(wq);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("no wq available for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+</div><div class='add'>+	dev = &amp;wq-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map src sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	src_addr = sg_dma_address(req-&gt;src);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, src_addr %llx, nr_sgs %d, req-&gt;src %p,"</div><div class='add'>+		" req-&gt;slen %d, sg_dma_len(sg) %d\n", src_addr, nr_sgs,</div><div class='add'>+		req-&gt;src, req-&gt;slen, sg_dma_len(req-&gt;src));</div><div class='add'>+</div><div class='add'>+	req-&gt;dlen = 4 * req-&gt;slen; /* start with ~avg comp rato */</div><div class='add'>+alloc_dest:</div><div class='add'>+	order = order_base_2(round_up(req-&gt;dlen, PAGE_SIZE) / PAGE_SIZE);</div><div class='add'>+	req-&gt;dst = sgl_alloc_order(req-&gt;dlen, order, false, flags, NULL);</div><div class='add'>+	if (!req-&gt;dst) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		order = -1;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map dst sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto err_map_dst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dst_addr = sg_dma_address(req-&gt;dst);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, dst_addr %llx, nr_sgs %d, req-&gt;dst %p,"</div><div class='add'>+		" req-&gt;dlen %d, sg_dma_len(sg) %d\n", dst_addr, nr_sgs,</div><div class='add'>+		req-&gt;dst, req-&gt;dlen, sg_dma_len(req-&gt;dst));</div><div class='add'>+	ret = iaa_decompress(tfm, req, wq, src_addr, req-&gt;slen,</div><div class='add'>+			     dst_addr, &amp;req-&gt;dlen, true);</div><div class='add'>+	if (ret == -EOVERFLOW) {</div><div class='add'>+		dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+		req-&gt;dlen *= 2;</div><div class='add'>+		if (req-&gt;dlen &gt; CRYPTO_ACOMP_DST_MAX)</div><div class='add'>+			goto err_map_dst;</div><div class='add'>+		goto alloc_dest;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret != 0)</div><div class='add'>+		dev_dbg(dev, "asynchronous decompress failed ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+err_map_dst:</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+out:</div><div class='add'>+	iaa_wq_put(wq);</div><div class='add'>+</div><div class='add'>+	if (order &gt;= 0)</div><div class='add'>+		sgl_free_order(req-&gt;dst, order);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_comp_adecompress(struct acomp_req *req)</div><div class='add'>+{</div><div class='add'>+	struct crypto_tfm *tfm = req-&gt;base.tfm;</div><div class='add'>+	dma_addr_t src_addr, dst_addr;</div><div class='add'>+	int nr_sgs, cpu, ret = 0;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct idxd_wq *wq;</div><div class='add'>+</div><div class='add'>+	if (!iaa_crypto_enabled) {</div><div class='add'>+		pr_debug("iaa_crypto disabled, not decompressing\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;src || !req-&gt;slen) {</div><div class='add'>+		pr_debug("invalid src, not decompressing\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;dst)</div><div class='add'>+		return iaa_comp_adecompress_alloc_dest(req);</div><div class='add'>+</div><div class='add'>+	cpu = get_cpu();</div><div class='add'>+	wq = wq_table_next_wq(cpu);</div><div class='add'>+	put_cpu();</div><div class='add'>+	if (!wq) {</div><div class='add'>+		pr_debug("no wq configured for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = iaa_wq_get(wq);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("no wq available for cpu=%d\n", cpu);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+</div><div class='add'>+	dev = &amp;wq-&gt;idxd-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map src sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	src_addr = sg_dma_address(req-&gt;src);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, src_addr %llx, nr_sgs %d, req-&gt;src %p,"</div><div class='add'>+		" req-&gt;slen %d, sg_dma_len(sg) %d\n", src_addr, nr_sgs,</div><div class='add'>+		req-&gt;src, req-&gt;slen, sg_dma_len(req-&gt;src));</div><div class='add'>+</div><div class='add'>+	nr_sgs = dma_map_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+	if (nr_sgs &lt;= 0 || nr_sgs &gt; 1) {</div><div class='add'>+		dev_dbg(dev, "couldn't map dst sg for iaa device %d,"</div><div class='add'>+			" wq %d: ret=%d\n", iaa_wq-&gt;iaa_device-&gt;idxd-&gt;id,</div><div class='add'>+			iaa_wq-&gt;wq-&gt;id, ret);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto err_map_dst;</div><div class='add'>+	}</div><div class='add'>+	dst_addr = sg_dma_address(req-&gt;dst);</div><div class='add'>+	dev_dbg(dev, "dma_map_sg, dst_addr %llx, nr_sgs %d, req-&gt;dst %p,"</div><div class='add'>+		" req-&gt;dlen %d, sg_dma_len(sg) %d\n", dst_addr, nr_sgs,</div><div class='add'>+		req-&gt;dst, req-&gt;dlen, sg_dma_len(req-&gt;dst));</div><div class='add'>+</div><div class='add'>+	ret = iaa_decompress(tfm, req, wq, src_addr, req-&gt;slen,</div><div class='add'>+			     dst_addr, &amp;req-&gt;dlen, false);</div><div class='add'>+	if (ret == -EINPROGRESS)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (ret != 0)</div><div class='add'>+		dev_dbg(dev, "asynchronous decompress failed ret=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;dst, sg_nents(req-&gt;dst), DMA_FROM_DEVICE);</div><div class='add'>+err_map_dst:</div><div class='add'>+	dma_unmap_sg(dev, req-&gt;src, sg_nents(req-&gt;src), DMA_TO_DEVICE);</div><div class='add'>+out:</div><div class='add'>+	iaa_wq_put(wq);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void compression_ctx_init(struct iaa_compression_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	ctx-&gt;verify_compress = iaa_verify_compress;</div><div class='add'>+	ctx-&gt;async_mode = async_mode;</div><div class='add'>+	ctx-&gt;use_irq = use_irq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_comp_init_fixed(struct crypto_acomp *acomp_tfm)</div><div class='add'>+{</div><div class='add'>+	struct crypto_tfm *tfm = crypto_acomp_tfm(acomp_tfm);</div><div class='add'>+	struct iaa_compression_ctx *ctx = crypto_tfm_ctx(tfm);</div><div class='add'>+</div><div class='add'>+	compression_ctx_init(ctx);</div><div class='add'>+</div><div class='add'>+	ctx-&gt;mode = IAA_MODE_FIXED;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dst_free(struct scatterlist *sgl)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Called for req-&gt;dst = NULL cases but we free elsewhere</div><div class='add'>+	 * using sgl_free_order().</div><div class='add'>+	 */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct acomp_alg iaa_acomp_fixed_deflate = {</div><div class='add'>+	.init			= iaa_comp_init_fixed,</div><div class='add'>+	.compress		= iaa_comp_acompress,</div><div class='add'>+	.decompress		= iaa_comp_adecompress,</div><div class='add'>+	.dst_free               = dst_free,</div><div class='add'>+	.base			= {</div><div class='add'>+		.cra_name		= "deflate",</div><div class='add'>+		.cra_driver_name	= "deflate-iaa",</div><div class='add'>+		.cra_ctxsize		= sizeof(struct iaa_compression_ctx),</div><div class='add'>+		.cra_module		= THIS_MODULE,</div><div class='add'>+		.cra_priority		= IAA_ALG_PRIORITY,</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int iaa_register_compression_device(void)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = crypto_register_acomp(&amp;iaa_acomp_fixed_deflate);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_err("deflate algorithm acomp fixed registration failed (%d)\n", ret);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iaa_crypto_registered = true;</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_unregister_compression_device(void)</div><div class='add'>+{</div><div class='add'>+	if (iaa_crypto_registered)</div><div class='add'>+		crypto_unregister_acomp(&amp;iaa_acomp_fixed_deflate);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_crypto_probe(struct idxd_dev *idxd_dev)</div><div class='add'>+{</div><div class='add'>+	struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);</div><div class='add'>+	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='add'>+	struct idxd_driver_data *data = idxd-&gt;data;</div><div class='add'>+	struct device *dev = &amp;idxd_dev-&gt;conf_dev;</div><div class='add'>+	bool first_wq = false;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (idxd-&gt;state != IDXD_DEV_ENABLED)</div><div class='add'>+		return -ENXIO;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;type != IDXD_TYPE_IAX)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;wq-&gt;wq_lock);</div><div class='add'>+</div><div class='add'>+	if (idxd_wq_get_private(wq)) {</div><div class='add'>+		mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!idxd_wq_driver_name_match(wq, dev)) {</div><div class='add'>+		dev_dbg(dev, "wq %d.%d driver_name match failed: wq driver_name %s, dev driver name %s\n",</div><div class='add'>+			idxd-&gt;id, wq-&gt;id, wq-&gt;driver_name, dev-&gt;driver-&gt;name);</div><div class='add'>+		idxd-&gt;cmd_status = IDXD_SCMD_WQ_NO_DRV_NAME;</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wq-&gt;type = IDXD_WQT_KERNEL;</div><div class='add'>+</div><div class='add'>+	ret = idxd_drv_enable_wq(wq);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_dbg(dev, "enable wq %d.%d failed: %d\n",</div><div class='add'>+			idxd-&gt;id, wq-&gt;id, ret);</div><div class='add'>+		ret = -ENXIO;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	if (list_empty(&amp;iaa_devices)) {</div><div class='add'>+		ret = alloc_wq_table(wq-&gt;idxd-&gt;max_wqs);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_alloc;</div><div class='add'>+		first_wq = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = save_iaa_wq(wq);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_save;</div><div class='add'>+</div><div class='add'>+	rebalance_wq_table();</div><div class='add'>+</div><div class='add'>+	if (first_wq) {</div><div class='add'>+		iaa_crypto_enabled = true;</div><div class='add'>+		ret = iaa_register_compression_device();</div><div class='add'>+		if (ret != 0) {</div><div class='add'>+			iaa_crypto_enabled = false;</div><div class='add'>+			dev_dbg(dev, "IAA compression device registration failed\n");</div><div class='add'>+			goto err_register;</div><div class='add'>+		}</div><div class='add'>+		try_module_get(THIS_MODULE);</div><div class='add'>+</div><div class='add'>+		pr_info("iaa_crypto now ENABLED\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+err_register:</div><div class='add'>+	remove_iaa_wq(wq);</div><div class='add'>+	free_iaa_wq(idxd_wq_get_private(wq));</div><div class='add'>+err_save:</div><div class='add'>+	if (first_wq)</div><div class='add'>+		free_wq_table();</div><div class='add'>+err_alloc:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='add'>+err:</div><div class='add'>+	wq-&gt;type = IDXD_WQT_NONE;</div><div class='add'>+</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void iaa_crypto_remove(struct idxd_dev *idxd_dev)</div><div class='add'>+{</div><div class='add'>+	struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);</div><div class='add'>+	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+	bool free = false;</div><div class='add'>+</div><div class='add'>+	idxd_wq_quiesce(wq);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;wq-&gt;wq_lock);</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	remove_iaa_wq(wq);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+	iaa_wq = idxd_wq_get_private(wq);</div><div class='add'>+	if (!iaa_wq) {</div><div class='add'>+		spin_unlock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+		pr_err("%s: no iaa_wq available to remove\n", __func__);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (iaa_wq-&gt;ref) {</div><div class='add'>+		iaa_wq-&gt;remove = true;</div><div class='add'>+	} else {</div><div class='add'>+		wq = iaa_wq-&gt;wq;</div><div class='add'>+		idxd_wq_set_private(wq, NULL);</div><div class='add'>+		free = true;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;idxd-&gt;dev_lock);</div><div class='add'>+	if (free) {</div><div class='add'>+		__free_iaa_wq(iaa_wq);</div><div class='add'>+		kfree(iaa_wq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='add'>+	rebalance_wq_table();</div><div class='add'>+</div><div class='add'>+	if (nr_iaa == 0) {</div><div class='add'>+		iaa_crypto_enabled = false;</div><div class='add'>+		free_wq_table();</div><div class='add'>+		module_put(THIS_MODULE);</div><div class='add'>+</div><div class='add'>+		pr_info("iaa_crypto now DISABLED\n");</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+	mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum idxd_dev_type dev_types[] = {</div><div class='add'>+	IDXD_DEV_WQ,</div><div class='add'>+	IDXD_DEV_NONE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct idxd_device_driver iaa_crypto_driver = {</div><div class='add'>+	.probe = iaa_crypto_probe,</div><div class='add'>+	.remove = iaa_crypto_remove,</div><div class='add'>+	.name = IDXD_SUBDRIVER_NAME,</div><div class='add'>+	.type = dev_types,</div><div class='add'>+	.desc_complete = iaa_desc_complete,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init iaa_crypto_init_module(void)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	int node;</div><div class='add'>+</div><div class='add'>+	nr_cpus = num_online_cpus();</div><div class='add'>+	for_each_node_with_cpus(node)</div><div class='add'>+		nr_nodes++;</div><div class='add'>+	if (!nr_nodes) {</div><div class='add'>+		pr_err("IAA couldn't find any nodes with cpus\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	nr_cpus_per_node = nr_cpus / nr_nodes;</div><div class='add'>+</div><div class='add'>+	if (crypto_has_comp("deflate-generic", 0, 0))</div><div class='add'>+		deflate_generic_tfm = crypto_alloc_comp("deflate-generic", 0, 0);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR_OR_NULL(deflate_generic_tfm)) {</div><div class='add'>+		pr_err("IAA could not alloc %s tfm: errcode = %ld\n",</div><div class='add'>+		       "deflate-generic", PTR_ERR(deflate_generic_tfm));</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = iaa_aecs_init_fixed();</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		pr_debug("IAA fixed compression mode init failed\n");</div><div class='add'>+		goto err_aecs_init;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = idxd_driver_register(&amp;iaa_crypto_driver);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("IAA wq sub-driver registration failed\n");</div><div class='add'>+		goto err_driver_reg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = driver_create_file(&amp;iaa_crypto_driver.drv,</div><div class='add'>+				 &amp;driver_attr_verify_compress);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("IAA verify_compress attr creation failed\n");</div><div class='add'>+		goto err_verify_attr_create;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = driver_create_file(&amp;iaa_crypto_driver.drv,</div><div class='add'>+				 &amp;driver_attr_sync_mode);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("IAA sync mode attr creation failed\n");</div><div class='add'>+		goto err_sync_attr_create;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (iaa_crypto_debugfs_init())</div><div class='add'>+		pr_warn("debugfs init failed, stats not available\n");</div><div class='add'>+</div><div class='add'>+	pr_debug("initialized\n");</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+err_sync_attr_create:</div><div class='add'>+	driver_remove_file(&amp;iaa_crypto_driver.drv,</div><div class='add'>+			   &amp;driver_attr_verify_compress);</div><div class='add'>+err_verify_attr_create:</div><div class='add'>+	idxd_driver_unregister(&amp;iaa_crypto_driver);</div><div class='add'>+err_driver_reg:</div><div class='add'>+	iaa_aecs_cleanup_fixed();</div><div class='add'>+err_aecs_init:</div><div class='add'>+	crypto_free_comp(deflate_generic_tfm);</div><div class='add'>+</div><div class='add'>+	goto out;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit iaa_crypto_cleanup_module(void)</div><div class='add'>+{</div><div class='add'>+	if (iaa_unregister_compression_device())</div><div class='add'>+		pr_debug("IAA compression device unregister failed\n");</div><div class='add'>+</div><div class='add'>+	iaa_crypto_debugfs_cleanup();</div><div class='add'>+	driver_remove_file(&amp;iaa_crypto_driver.drv,</div><div class='add'>+			   &amp;driver_attr_sync_mode);</div><div class='add'>+	driver_remove_file(&amp;iaa_crypto_driver.drv,</div><div class='add'>+			   &amp;driver_attr_verify_compress);</div><div class='add'>+	idxd_driver_unregister(&amp;iaa_crypto_driver);</div><div class='add'>+	iaa_aecs_cleanup_fixed();</div><div class='add'>+	crypto_free_comp(deflate_generic_tfm);</div><div class='add'>+</div><div class='add'>+	pr_debug("cleaned up\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+MODULE_IMPORT_NS(IDXD);</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_ALIAS_IDXD_DEVICE(0);</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_DESCRIPTION("IAA Compression Accelerator Crypto Driver");</div><div class='add'>+</div><div class='add'>+module_init(iaa_crypto_init_module);</div><div class='add'>+module_exit(iaa_crypto_cleanup_module);</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/iaa_crypto_stats.c b/drivers/crypto/intel/iaa/iaa_crypto_stats.c<br/>new file mode 100644<br/>index 000000000000..2e3b7b73af20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/iaa_crypto_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_stats.c</a></div><div class='hunk'>@@ -0,0 +1,312 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright(c) 2021 Intel Corporation. All rights rsvd. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/highmem.h&gt;</div><div class='add'>+#include &lt;linux/mm.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/smp.h&gt;</div><div class='add'>+#include &lt;uapi/linux/idxd.h&gt;</div><div class='add'>+#include &lt;linux/idxd.h&gt;</div><div class='add'>+#include &lt;linux/dmaengine.h&gt;</div><div class='add'>+#include "../../dma/idxd/idxd.h"</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;crypto/internal/acompress.h&gt;</div><div class='add'>+#include "iaa_crypto.h"</div><div class='add'>+#include "iaa_crypto_stats.h"</div><div class='add'>+</div><div class='add'>+static u64 total_comp_calls;</div><div class='add'>+static u64 total_decomp_calls;</div><div class='add'>+static u64 total_sw_decomp_calls;</div><div class='add'>+static u64 max_comp_delay_ns;</div><div class='add'>+static u64 max_decomp_delay_ns;</div><div class='add'>+static u64 max_acomp_delay_ns;</div><div class='add'>+static u64 max_adecomp_delay_ns;</div><div class='add'>+static u64 total_comp_bytes_out;</div><div class='add'>+static u64 total_decomp_bytes_in;</div><div class='add'>+static u64 total_completion_einval_errors;</div><div class='add'>+static u64 total_completion_timeout_errors;</div><div class='add'>+static u64 total_completion_comp_buf_overflow_errors;</div><div class='add'>+</div><div class='add'>+static struct dentry *iaa_crypto_debugfs_root;</div><div class='add'>+</div><div class='add'>+void update_total_comp_calls(void)</div><div class='add'>+{</div><div class='add'>+	total_comp_calls++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_total_comp_bytes_out(int n)</div><div class='add'>+{</div><div class='add'>+	total_comp_bytes_out += n;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_total_decomp_calls(void)</div><div class='add'>+{</div><div class='add'>+	total_decomp_calls++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_total_sw_decomp_calls(void)</div><div class='add'>+{</div><div class='add'>+	total_sw_decomp_calls++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_total_decomp_bytes_in(int n)</div><div class='add'>+{</div><div class='add'>+	total_decomp_bytes_in += n;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_completion_einval_errs(void)</div><div class='add'>+{</div><div class='add'>+	total_completion_einval_errors++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_completion_timeout_errs(void)</div><div class='add'>+{</div><div class='add'>+	total_completion_timeout_errors++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_completion_comp_buf_overflow_errs(void)</div><div class='add'>+{</div><div class='add'>+	total_completion_comp_buf_overflow_errors++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_max_comp_delay_ns(u64 start_time_ns)</div><div class='add'>+{</div><div class='add'>+	u64 time_diff;</div><div class='add'>+</div><div class='add'>+	time_diff = ktime_get_ns() - start_time_ns;</div><div class='add'>+</div><div class='add'>+	if (time_diff &gt; max_comp_delay_ns)</div><div class='add'>+		max_comp_delay_ns = time_diff;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_max_decomp_delay_ns(u64 start_time_ns)</div><div class='add'>+{</div><div class='add'>+	u64 time_diff;</div><div class='add'>+</div><div class='add'>+	time_diff = ktime_get_ns() - start_time_ns;</div><div class='add'>+</div><div class='add'>+	if (time_diff &gt; max_decomp_delay_ns)</div><div class='add'>+		max_decomp_delay_ns = time_diff;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_max_acomp_delay_ns(u64 start_time_ns)</div><div class='add'>+{</div><div class='add'>+	u64 time_diff;</div><div class='add'>+</div><div class='add'>+	time_diff = ktime_get_ns() - start_time_ns;</div><div class='add'>+</div><div class='add'>+	if (time_diff &gt; max_acomp_delay_ns)</div><div class='add'>+		max_acomp_delay_ns = time_diff;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_max_adecomp_delay_ns(u64 start_time_ns)</div><div class='add'>+{</div><div class='add'>+	u64 time_diff;</div><div class='add'>+</div><div class='add'>+	time_diff = ktime_get_ns() - start_time_ns;</div><div class='add'>+</div><div class='add'>+	if (time_diff &gt; max_adecomp_delay_ns)</div><div class='add'>+		max_adecomp_delay_ns = time_diff;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_wq_comp_calls(struct idxd_wq *idxd_wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *wq = idxd_wq_get_private(idxd_wq);</div><div class='add'>+</div><div class='add'>+	wq-&gt;comp_calls++;</div><div class='add'>+	wq-&gt;iaa_device-&gt;comp_calls++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_wq_comp_bytes(struct idxd_wq *idxd_wq, int n)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *wq = idxd_wq_get_private(idxd_wq);</div><div class='add'>+</div><div class='add'>+	wq-&gt;comp_bytes += n;</div><div class='add'>+	wq-&gt;iaa_device-&gt;comp_bytes += n;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_wq_decomp_calls(struct idxd_wq *idxd_wq)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *wq = idxd_wq_get_private(idxd_wq);</div><div class='add'>+</div><div class='add'>+	wq-&gt;decomp_calls++;</div><div class='add'>+	wq-&gt;iaa_device-&gt;decomp_calls++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void update_wq_decomp_bytes(struct idxd_wq *idxd_wq, int n)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *wq = idxd_wq_get_private(idxd_wq);</div><div class='add'>+</div><div class='add'>+	wq-&gt;decomp_bytes += n;</div><div class='add'>+	wq-&gt;iaa_device-&gt;decomp_bytes += n;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_iaa_crypto_stats(void)</div><div class='add'>+{</div><div class='add'>+	total_comp_calls = 0;</div><div class='add'>+	total_decomp_calls = 0;</div><div class='add'>+	total_sw_decomp_calls = 0;</div><div class='add'>+	max_comp_delay_ns = 0;</div><div class='add'>+	max_decomp_delay_ns = 0;</div><div class='add'>+	max_acomp_delay_ns = 0;</div><div class='add'>+	max_adecomp_delay_ns = 0;</div><div class='add'>+	total_comp_bytes_out = 0;</div><div class='add'>+	total_decomp_bytes_in = 0;</div><div class='add'>+	total_completion_einval_errors = 0;</div><div class='add'>+	total_completion_timeout_errors = 0;</div><div class='add'>+	total_completion_comp_buf_overflow_errors = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_wq_stats(struct iaa_wq *wq)</div><div class='add'>+{</div><div class='add'>+	wq-&gt;comp_calls = 0;</div><div class='add'>+	wq-&gt;comp_bytes = 0;</div><div class='add'>+	wq-&gt;decomp_calls = 0;</div><div class='add'>+	wq-&gt;decomp_bytes = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_device_stats(struct iaa_device *iaa_device)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+</div><div class='add'>+	iaa_device-&gt;comp_calls = 0;</div><div class='add'>+	iaa_device-&gt;comp_bytes = 0;</div><div class='add'>+	iaa_device-&gt;decomp_calls = 0;</div><div class='add'>+	iaa_device-&gt;decomp_bytes = 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_wq, &amp;iaa_device-&gt;wqs, list)</div><div class='add'>+		reset_wq_stats(iaa_wq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wq_show(struct seq_file *m, struct iaa_wq *iaa_wq)</div><div class='add'>+{</div><div class='add'>+	seq_printf(m, "    name: %s\n", iaa_wq-&gt;wq-&gt;name);</div><div class='add'>+	seq_printf(m, "    comp_calls: %llu\n", iaa_wq-&gt;comp_calls);</div><div class='add'>+	seq_printf(m, "    comp_bytes: %llu\n", iaa_wq-&gt;comp_bytes);</div><div class='add'>+	seq_printf(m, "    decomp_calls: %llu\n", iaa_wq-&gt;decomp_calls);</div><div class='add'>+	seq_printf(m, "    decomp_bytes: %llu\n\n", iaa_wq-&gt;decomp_bytes);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void device_stats_show(struct seq_file *m, struct iaa_device *iaa_device)</div><div class='add'>+{</div><div class='add'>+	struct iaa_wq *iaa_wq;</div><div class='add'>+</div><div class='add'>+	seq_puts(m, "iaa device:\n");</div><div class='add'>+	seq_printf(m, "  id: %d\n", iaa_device-&gt;idxd-&gt;id);</div><div class='add'>+	seq_printf(m, "  n_wqs: %d\n", iaa_device-&gt;n_wq);</div><div class='add'>+	seq_printf(m, "  comp_calls: %llu\n", iaa_device-&gt;comp_calls);</div><div class='add'>+	seq_printf(m, "  comp_bytes: %llu\n", iaa_device-&gt;comp_bytes);</div><div class='add'>+	seq_printf(m, "  decomp_calls: %llu\n", iaa_device-&gt;decomp_calls);</div><div class='add'>+	seq_printf(m, "  decomp_bytes: %llu\n", iaa_device-&gt;decomp_bytes);</div><div class='add'>+	seq_puts(m, "  wqs:\n");</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_wq, &amp;iaa_device-&gt;wqs, list)</div><div class='add'>+		wq_show(m, iaa_wq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void global_stats_show(struct seq_file *m)</div><div class='add'>+{</div><div class='add'>+	seq_puts(m, "global stats:\n");</div><div class='add'>+	seq_printf(m, "  total_comp_calls: %llu\n", total_comp_calls);</div><div class='add'>+	seq_printf(m, "  total_decomp_calls: %llu\n", total_decomp_calls);</div><div class='add'>+	seq_printf(m, "  total_sw_decomp_calls: %llu\n", total_sw_decomp_calls);</div><div class='add'>+	seq_printf(m, "  total_comp_bytes_out: %llu\n", total_comp_bytes_out);</div><div class='add'>+	seq_printf(m, "  total_decomp_bytes_in: %llu\n", total_decomp_bytes_in);</div><div class='add'>+	seq_printf(m, "  total_completion_einval_errors: %llu\n",</div><div class='add'>+		   total_completion_einval_errors);</div><div class='add'>+	seq_printf(m, "  total_completion_timeout_errors: %llu\n",</div><div class='add'>+		   total_completion_timeout_errors);</div><div class='add'>+	seq_printf(m, "  total_completion_comp_buf_overflow_errors: %llu\n\n",</div><div class='add'>+		   total_completion_comp_buf_overflow_errors);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wq_stats_show(struct seq_file *m, void *v)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	global_stats_show(m);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_device, &amp;iaa_devices, list)</div><div class='add'>+		device_stats_show(m, iaa_device);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int iaa_crypto_stats_reset(void *data, u64 value)</div><div class='add'>+{</div><div class='add'>+	struct iaa_device *iaa_device;</div><div class='add'>+</div><div class='add'>+	reset_iaa_crypto_stats();</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iaa_device, &amp;iaa_devices, list)</div><div class='add'>+		reset_device_stats(iaa_device);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;iaa_devices_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wq_stats_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	return single_open(file, wq_stats_show, file);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations wq_stats_fops = {</div><div class='add'>+	.open = wq_stats_open,</div><div class='add'>+	.read = seq_read,</div><div class='add'>+	.llseek = seq_lseek,</div><div class='add'>+	.release = single_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(wq_stats_reset_fops, NULL, iaa_crypto_stats_reset, "%llu\n");</div><div class='add'>+</div><div class='add'>+int __init iaa_crypto_debugfs_init(void)</div><div class='add'>+{</div><div class='add'>+	if (!debugfs_initialized())</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	iaa_crypto_debugfs_root = debugfs_create_dir("iaa_crypto", NULL);</div><div class='add'>+	if (!iaa_crypto_debugfs_root)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	debugfs_create_u64("max_comp_delay_ns", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;max_comp_delay_ns);</div><div class='add'>+	debugfs_create_u64("max_decomp_delay_ns", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;max_decomp_delay_ns);</div><div class='add'>+	debugfs_create_u64("max_acomp_delay_ns", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;max_comp_delay_ns);</div><div class='add'>+	debugfs_create_u64("max_adecomp_delay_ns", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;max_decomp_delay_ns);</div><div class='add'>+	debugfs_create_u64("total_comp_calls", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;total_comp_calls);</div><div class='add'>+	debugfs_create_u64("total_decomp_calls", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;total_decomp_calls);</div><div class='add'>+	debugfs_create_u64("total_sw_decomp_calls", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;total_sw_decomp_calls);</div><div class='add'>+	debugfs_create_u64("total_comp_bytes_out", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;total_comp_bytes_out);</div><div class='add'>+	debugfs_create_u64("total_decomp_bytes_in", 0644,</div><div class='add'>+			   iaa_crypto_debugfs_root, &amp;total_decomp_bytes_in);</div><div class='add'>+	debugfs_create_file("wq_stats", 0644, iaa_crypto_debugfs_root, NULL,</div><div class='add'>+			    &amp;wq_stats_fops);</div><div class='add'>+	debugfs_create_file("stats_reset", 0644, iaa_crypto_debugfs_root, NULL,</div><div class='add'>+			    &amp;wq_stats_reset_fops);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void __exit iaa_crypto_debugfs_cleanup(void)</div><div class='add'>+{</div><div class='add'>+	debugfs_remove_recursive(iaa_crypto_debugfs_root);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/crypto/intel/iaa/iaa_crypto_stats.h b/drivers/crypto/intel/iaa/iaa_crypto_stats.h<br/>new file mode 100644<br/>index 000000000000..c10b87b86fa4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/iaa/iaa_crypto_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/iaa/iaa_crypto_stats.h</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Copyright(c) 2021 Intel Corporation. All rights rsvd. */</div><div class='add'>+</div><div class='add'>+#ifndef __CRYPTO_DEV_IAA_CRYPTO_STATS_H__</div><div class='add'>+#define __CRYPTO_DEV_IAA_CRYPTO_STATS_H__</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS)</div><div class='add'>+int	iaa_crypto_debugfs_init(void);</div><div class='add'>+void	iaa_crypto_debugfs_cleanup(void);</div><div class='add'>+</div><div class='add'>+void	update_total_comp_calls(void);</div><div class='add'>+void	update_total_comp_bytes_out(int n);</div><div class='add'>+void	update_total_decomp_calls(void);</div><div class='add'>+void	update_total_sw_decomp_calls(void);</div><div class='add'>+void	update_total_decomp_bytes_in(int n);</div><div class='add'>+void	update_max_comp_delay_ns(u64 start_time_ns);</div><div class='add'>+void	update_max_decomp_delay_ns(u64 start_time_ns);</div><div class='add'>+void	update_max_acomp_delay_ns(u64 start_time_ns);</div><div class='add'>+void	update_max_adecomp_delay_ns(u64 start_time_ns);</div><div class='add'>+void	update_completion_einval_errs(void);</div><div class='add'>+void	update_completion_timeout_errs(void);</div><div class='add'>+void	update_completion_comp_buf_overflow_errs(void);</div><div class='add'>+</div><div class='add'>+void	update_wq_comp_calls(struct idxd_wq *idxd_wq);</div><div class='add'>+void	update_wq_comp_bytes(struct idxd_wq *idxd_wq, int n);</div><div class='add'>+void	update_wq_decomp_calls(struct idxd_wq *idxd_wq);</div><div class='add'>+void	update_wq_decomp_bytes(struct idxd_wq *idxd_wq, int n);</div><div class='add'>+</div><div class='add'>+#else</div><div class='add'>+static inline int	iaa_crypto_debugfs_init(void) { return 0; }</div><div class='add'>+static inline void	iaa_crypto_debugfs_cleanup(void) {}</div><div class='add'>+</div><div class='add'>+static inline void	update_total_comp_calls(void) {}</div><div class='add'>+static inline void	update_total_comp_bytes_out(int n) {}</div><div class='add'>+static inline void	update_total_decomp_calls(void) {}</div><div class='add'>+static inline void	update_total_sw_decomp_calls(void) {}</div><div class='add'>+static inline void	update_total_decomp_bytes_in(int n) {}</div><div class='add'>+static inline void	update_max_comp_delay_ns(u64 start_time_ns) {}</div><div class='add'>+static inline void	update_max_decomp_delay_ns(u64 start_time_ns) {}</div><div class='add'>+static inline void	update_max_acomp_delay_ns(u64 start_time_ns) {}</div><div class='add'>+static inline void	update_max_adecomp_delay_ns(u64 start_time_ns) {}</div><div class='add'>+static inline void	update_completion_einval_errs(void) {}</div><div class='add'>+static inline void	update_completion_timeout_errs(void) {}</div><div class='add'>+static inline void	update_completion_comp_buf_overflow_errs(void) {}</div><div class='add'>+</div><div class='add'>+static inline void	update_wq_comp_calls(struct idxd_wq *idxd_wq) {}</div><div class='add'>+static inline void	update_wq_comp_bytes(struct idxd_wq *idxd_wq, int n) {}</div><div class='add'>+static inline void	update_wq_decomp_calls(struct idxd_wq *idxd_wq) {}</div><div class='add'>+static inline void	update_wq_decomp_bytes(struct idxd_wq *idxd_wq, int n) {}</div><div class='add'>+</div><div class='add'>+#endif // CONFIG_CRYPTO_DEV_IAA_CRYPTO_STATS</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/Kconfig b/drivers/crypto/intel/qat/Kconfig<br/>index 1220cc86f910..c120f6715a09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/Kconfig</a></div><div class='hunk'>@@ -59,6 +59,17 @@ config CRYPTO_DEV_QAT_4XXX</div><div class='ctx'> 	  To compile this as a module, choose M here: the module</div><div class='ctx'> 	  will be called qat_4xxx.</div><div class='ctx'> </div><div class='add'>+config CRYPTO_DEV_QAT_420XX</div><div class='add'>+	tristate "Support for Intel(R) QAT_420XX"</div><div class='add'>+	depends on PCI &amp;&amp; (!CPU_BIG_ENDIAN || COMPILE_TEST)</div><div class='add'>+	select CRYPTO_DEV_QAT</div><div class='add'>+	help</div><div class='add'>+	  Support for Intel(R) QuickAssist Technology QAT_420xx</div><div class='add'>+	  for accelerating crypto and compression workloads.</div><div class='add'>+</div><div class='add'>+	  To compile this as a module, choose M here: the module</div><div class='add'>+	  will be called qat_420xx.</div><div class='add'>+</div><div class='ctx'> config CRYPTO_DEV_QAT_DH895xCCVF</div><div class='ctx'> 	tristate "Support for Intel(R) DH895xCC Virtual Function"</div><div class='ctx'> 	depends on PCI &amp;&amp; (!CPU_BIG_ENDIAN || COMPILE_TEST)</div><div class='head'>diff --git a/drivers/crypto/intel/qat/Makefile b/drivers/crypto/intel/qat/Makefile<br/>index 258c8a626ce0..235b69f4f3f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/Makefile</a></div><div class='hunk'>@@ -4,6 +4,7 @@ obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCC) += qat_dh895xcc/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXX) += qat_c3xxx/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_C62X) += qat_c62x/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_4XXX) += qat_4xxx/</div><div class='add'>+obj-$(CONFIG_CRYPTO_DEV_QAT_420XX) += qat_420xx/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_DH895xCCVF) += qat_dh895xccvf/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_C3XXXVF) += qat_c3xxxvf/</div><div class='ctx'> obj-$(CONFIG_CRYPTO_DEV_QAT_C62XVF) += qat_c62xvf/</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_420xx/Makefile b/drivers/crypto/intel/qat/qat_420xx/Makefile<br/>new file mode 100644<br/>index 000000000000..a90fbe00b3c8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_420xx/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/Makefile</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+ccflags-y := -I $(srctree)/$(src)/../qat_common</div><div class='add'>+obj-$(CONFIG_CRYPTO_DEV_QAT_420XX) += qat_420xx.o</div><div class='add'>+qat_420xx-objs := adf_drv.o adf_420xx_hw_data.o</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c<br/>new file mode 100644<br/>index 000000000000..a87d29ae724f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c</a></div><div class='hunk'>@@ -0,0 +1,528 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;adf_accel_devices.h&gt;</div><div class='add'>+#include &lt;adf_admin.h&gt;</div><div class='add'>+#include &lt;adf_cfg.h&gt;</div><div class='add'>+#include &lt;adf_cfg_services.h&gt;</div><div class='add'>+#include &lt;adf_clock.h&gt;</div><div class='add'>+#include &lt;adf_common_drv.h&gt;</div><div class='add'>+#include &lt;adf_fw_config.h&gt;</div><div class='add'>+#include &lt;adf_gen4_config.h&gt;</div><div class='add'>+#include &lt;adf_gen4_dc.h&gt;</div><div class='add'>+#include &lt;adf_gen4_hw_data.h&gt;</div><div class='add'>+#include &lt;adf_gen4_pfvf.h&gt;</div><div class='add'>+#include &lt;adf_gen4_pm.h&gt;</div><div class='add'>+#include &lt;adf_gen4_ras.h&gt;</div><div class='add'>+#include &lt;adf_gen4_timer.h&gt;</div><div class='add'>+#include &lt;adf_gen4_tl.h&gt;</div><div class='add'>+#include "adf_420xx_hw_data.h"</div><div class='add'>+#include "icp_qat_hw.h"</div><div class='add'>+</div><div class='add'>+#define ADF_AE_GROUP_0		GENMASK(3, 0)</div><div class='add'>+#define ADF_AE_GROUP_1		GENMASK(7, 4)</div><div class='add'>+#define ADF_AE_GROUP_2		GENMASK(11, 8)</div><div class='add'>+#define ADF_AE_GROUP_3		GENMASK(15, 12)</div><div class='add'>+#define ADF_AE_GROUP_4		BIT(16)</div><div class='add'>+</div><div class='add'>+#define ENA_THD_MASK_ASYM	GENMASK(1, 0)</div><div class='add'>+#define ENA_THD_MASK_SYM	GENMASK(3, 0)</div><div class='add'>+#define ENA_THD_MASK_DC		GENMASK(1, 0)</div><div class='add'>+</div><div class='add'>+static const char * const adf_420xx_fw_objs[] = {</div><div class='add'>+	[ADF_FW_SYM_OBJ] =  ADF_420XX_SYM_OBJ,</div><div class='add'>+	[ADF_FW_ASYM_OBJ] =  ADF_420XX_ASYM_OBJ,</div><div class='add'>+	[ADF_FW_DC_OBJ] =  ADF_420XX_DC_OBJ,</div><div class='add'>+	[ADF_FW_ADMIN_OBJ] = ADF_420XX_ADMIN_OBJ,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_cy_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_dc_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_sym_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_3, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_asym_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_asym_dc_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_3, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_2, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_ASYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_sym_dc_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_2, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_DC_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config adf_fw_dcc_config[] = {</div><div class='add'>+	{ADF_AE_GROUP_1, ADF_FW_DC_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_0, ADF_FW_SYM_OBJ},</div><div class='add'>+	{ADF_AE_GROUP_4, ADF_FW_ADMIN_OBJ},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static struct adf_hw_device_class adf_420xx_class = {</div><div class='add'>+	.name = ADF_420XX_DEVICE_NAME,</div><div class='add'>+	.type = DEV_420XX,</div><div class='add'>+	.instances = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u32 get_ae_mask(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	u32 me_disable = self-&gt;fuses;</div><div class='add'>+</div><div class='add'>+	return ~me_disable &amp; ADF_420XX_ACCELENGINES_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	switch (adf_get_service_enabled(accel_dev)) {</div><div class='add'>+	case SVC_CY:</div><div class='add'>+	case SVC_CY2:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_cy_config);</div><div class='add'>+	case SVC_DC:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_dc_config);</div><div class='add'>+	case SVC_DCC:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_dcc_config);</div><div class='add'>+	case SVC_SYM:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_sym_config);</div><div class='add'>+	case SVC_ASYM:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_asym_config);</div><div class='add'>+	case SVC_ASYM_DC:</div><div class='add'>+	case SVC_DC_ASYM:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_asym_dc_config);</div><div class='add'>+	case SVC_SYM_DC:</div><div class='add'>+	case SVC_DC_SYM:</div><div class='add'>+		return ARRAY_SIZE(adf_fw_sym_dc_config);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	switch (adf_get_service_enabled(accel_dev)) {</div><div class='add'>+	case SVC_CY:</div><div class='add'>+	case SVC_CY2:</div><div class='add'>+		return adf_fw_cy_config;</div><div class='add'>+	case SVC_DC:</div><div class='add'>+		return adf_fw_dc_config;</div><div class='add'>+	case SVC_DCC:</div><div class='add'>+		return adf_fw_dcc_config;</div><div class='add'>+	case SVC_SYM:</div><div class='add'>+		return adf_fw_sym_config;</div><div class='add'>+	case SVC_ASYM:</div><div class='add'>+		return adf_fw_asym_config;</div><div class='add'>+	case SVC_ASYM_DC:</div><div class='add'>+	case SVC_DC_ASYM:</div><div class='add'>+		return adf_fw_asym_dc_config;</div><div class='add'>+	case SVC_SYM_DC:</div><div class='add'>+	case SVC_DC_SYM:</div><div class='add'>+		return adf_fw_sym_dc_config;</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void update_ae_mask(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+	u32 config_ae_mask = 0;</div><div class='add'>+	u32 ae_mask, num_objs;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	ae_mask = get_ae_mask(hw_data);</div><div class='add'>+</div><div class='add'>+	/* Modify the AE mask based on the firmware configuration loaded */</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	num_objs = uof_get_num_objs(accel_dev);</div><div class='add'>+</div><div class='add'>+	config_ae_mask |= ADF_420XX_ADMIN_AE_MASK;</div><div class='add'>+	for (i = 0; i &lt; num_objs; i++)</div><div class='add'>+		config_ae_mask |= fw_config[i].ae_mask;</div><div class='add'>+</div><div class='add'>+	hw_data-&gt;ae_mask = ae_mask &amp; config_ae_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	u32 capabilities_sym, capabilities_asym, capabilities_dc;</div><div class='add'>+	struct pci_dev *pdev = accel_dev-&gt;accel_pci_dev.pci_dev;</div><div class='add'>+	u32 capabilities_dcc;</div><div class='add'>+	u32 fusectl1;</div><div class='add'>+</div><div class='add'>+	/* As a side effect, update ae_mask based on configuration */</div><div class='add'>+	update_ae_mask(accel_dev);</div><div class='add'>+</div><div class='add'>+	/* Read accelerator capabilities mask */</div><div class='add'>+	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL1_OFFSET, &amp;fusectl1);</div><div class='add'>+</div><div class='add'>+	capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_CIPHER |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_AUTHENTICATION |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_SHA3 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_SHA3_EXT |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_HKDF |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_CHACHA_POLY |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_AESGCM_SPC |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_SM3 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_SM4 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_AES_V2 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_ZUC |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_ZUC_256 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN;</div><div class='add'>+</div><div class='add'>+	/* A set bit in fusectl1 means the feature is OFF in this SKU */</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_CIPHER_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_HKDF;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_UCS_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AES_V2;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_AUTH_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SHA3;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_SMX_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SM3;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SM4;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_ZUC;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_ZUC_256;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_EIA3_SLICE) {</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_ZUC;</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_ZUC_256;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE)</div><div class='add'>+		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_ZUC_256;</div><div class='add'>+</div><div class='add'>+	capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_SM2 |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_ECEDMONT;</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_PKE_SLICE) {</div><div class='add'>+		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;</div><div class='add'>+		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_SM2;</div><div class='add'>+		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |</div><div class='add'>+			  ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;</div><div class='add'>+</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE) {</div><div class='add'>+		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;</div><div class='add'>+		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;</div><div class='add'>+		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;</div><div class='add'>+		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (adf_get_service_enabled(accel_dev)) {</div><div class='add'>+	case SVC_CY:</div><div class='add'>+	case SVC_CY2:</div><div class='add'>+		return capabilities_sym | capabilities_asym;</div><div class='add'>+	case SVC_DC:</div><div class='add'>+		return capabilities_dc;</div><div class='add'>+	case SVC_DCC:</div><div class='add'>+		/*</div><div class='add'>+		 * Sym capabilities are available for chaining operations,</div><div class='add'>+		 * but sym crypto instances cannot be supported</div><div class='add'>+		 */</div><div class='add'>+		capabilities_dcc = capabilities_dc | capabilities_sym;</div><div class='add'>+		capabilities_dcc &amp;= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;</div><div class='add'>+		return capabilities_dcc;</div><div class='add'>+	case SVC_SYM:</div><div class='add'>+		return capabilities_sym;</div><div class='add'>+	case SVC_ASYM:</div><div class='add'>+		return capabilities_asym;</div><div class='add'>+	case SVC_ASYM_DC:</div><div class='add'>+	case SVC_DC_ASYM:</div><div class='add'>+		return capabilities_asym | capabilities_dc;</div><div class='add'>+	case SVC_SYM_DC:</div><div class='add'>+	case SVC_DC_SYM:</div><div class='add'>+		return capabilities_sym | capabilities_dc;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	if (adf_gen4_init_thd2arb_map(accel_dev))</div><div class='add'>+		dev_warn(&amp;GET_DEV(accel_dev),</div><div class='add'>+			 "Generate of the thread to arbiter map failed");</div><div class='add'>+</div><div class='add'>+	return GET_HW_DATA(accel_dev)-&gt;thd_to_arb_map;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)</div><div class='add'>+{</div><div class='add'>+	rl_data-&gt;pciout_tb_offset = ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET;</div><div class='add'>+	rl_data-&gt;pciin_tb_offset = ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET;</div><div class='add'>+	rl_data-&gt;r2l_offset = ADF_GEN4_RL_R2L_OFFSET;</div><div class='add'>+	rl_data-&gt;l2c_offset = ADF_GEN4_RL_L2C_OFFSET;</div><div class='add'>+	rl_data-&gt;c2s_offset = ADF_GEN4_RL_C2S_OFFSET;</div><div class='add'>+</div><div class='add'>+	rl_data-&gt;pcie_scale_div = ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV;</div><div class='add'>+	rl_data-&gt;pcie_scale_mul = ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL;</div><div class='add'>+	rl_data-&gt;dcpr_correction = ADF_420XX_RL_DCPR_CORRECTION;</div><div class='add'>+	rl_data-&gt;max_tp[ADF_SVC_ASYM] = ADF_420XX_RL_MAX_TP_ASYM;</div><div class='add'>+	rl_data-&gt;max_tp[ADF_SVC_SYM] = ADF_420XX_RL_MAX_TP_SYM;</div><div class='add'>+	rl_data-&gt;max_tp[ADF_SVC_DC] = ADF_420XX_RL_MAX_TP_DC;</div><div class='add'>+	rl_data-&gt;scan_interval = ADF_420XX_RL_SCANS_PER_SEC;</div><div class='add'>+	rl_data-&gt;scale_ref = ADF_420XX_RL_SLICE_REF;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)</div><div class='add'>+{</div><div class='add'>+	switch (ae_mask) {</div><div class='add'>+	case ADF_AE_GROUP_0:</div><div class='add'>+		return RP_GROUP_0;</div><div class='add'>+	case ADF_AE_GROUP_1:</div><div class='add'>+	case ADF_AE_GROUP_3:</div><div class='add'>+		return RP_GROUP_1;</div><div class='add'>+	case ADF_AE_GROUP_2:</div><div class='add'>+		if (get_fw_config(accel_dev) == adf_fw_cy_config)</div><div class='add'>+			return RP_GROUP_0;</div><div class='add'>+		else</div><div class='add'>+			return RP_GROUP_1;</div><div class='add'>+	default:</div><div class='add'>+		dev_dbg(&amp;GET_DEV(accel_dev), "ae_mask not recognized");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)</div><div class='add'>+{</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+</div><div class='add'>+	if (obj_num &gt;= uof_get_num_objs(accel_dev))</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (!fw_config)</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	switch (fw_config[obj_num].obj) {</div><div class='add'>+	case ADF_FW_ASYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_ASYM;</div><div class='add'>+	case ADF_FW_SYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_SYM;</div><div class='add'>+	case ADF_FW_DC_OBJ:</div><div class='add'>+		return ENA_THD_MASK_DC;</div><div class='add'>+	default:</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	enum adf_cfg_service_type rps[RP_GROUP_COUNT] = { };</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+	u16 ring_to_svc_map;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (!fw_config)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; RP_GROUP_COUNT; i++) {</div><div class='add'>+		switch (fw_config[i].ae_mask) {</div><div class='add'>+		case ADF_AE_GROUP_0:</div><div class='add'>+			j = RP_GROUP_0;</div><div class='add'>+			break;</div><div class='add'>+		case ADF_AE_GROUP_1:</div><div class='add'>+			j = RP_GROUP_1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		switch (fw_config[i].obj) {</div><div class='add'>+		case ADF_FW_SYM_OBJ:</div><div class='add'>+			rps[j] = SYM;</div><div class='add'>+			break;</div><div class='add'>+		case ADF_FW_ASYM_OBJ:</div><div class='add'>+			rps[j] = ASYM;</div><div class='add'>+			break;</div><div class='add'>+		case ADF_FW_DC_OBJ:</div><div class='add'>+			rps[j] = COMP;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			rps[j] = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ring_to_svc_map = rps[RP_GROUP_0] &lt;&lt; ADF_CFG_SERV_RING_PAIR_0_SHIFT |</div><div class='add'>+			  rps[RP_GROUP_1] &lt;&lt; ADF_CFG_SERV_RING_PAIR_1_SHIFT |</div><div class='add'>+			  rps[RP_GROUP_0] &lt;&lt; ADF_CFG_SERV_RING_PAIR_2_SHIFT |</div><div class='add'>+			  rps[RP_GROUP_1] &lt;&lt; ADF_CFG_SERV_RING_PAIR_3_SHIFT;</div><div class='add'>+</div><div class='add'>+	return ring_to_svc_map;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,</div><div class='add'>+				const char * const fw_objs[], int num_objs)</div><div class='add'>+{</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (fw_config)</div><div class='add'>+		id = fw_config[obj_num].obj;</div><div class='add'>+	else</div><div class='add'>+		id = -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (id &lt; 0 || id &gt; num_objs)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return fw_objs[id];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *uof_get_name_420xx(struct adf_accel_dev *accel_dev, u32 obj_num)</div><div class='add'>+{</div><div class='add'>+	int num_fw_objs = ARRAY_SIZE(adf_420xx_fw_objs);</div><div class='add'>+</div><div class='add'>+	return uof_get_name(accel_dev, obj_num, adf_420xx_fw_objs, num_fw_objs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)</div><div class='add'>+{</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (!fw_config)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return fw_config[obj_num].ae_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void adf_gen4_set_err_mask(struct adf_dev_err_mask *dev_err_mask)</div><div class='add'>+{</div><div class='add'>+	dev_err_mask-&gt;cppagentcmdpar_mask = ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK;</div><div class='add'>+	dev_err_mask-&gt;parerr_ath_cph_mask = ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK;</div><div class='add'>+	dev_err_mask-&gt;parerr_cpr_xlt_mask = ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK;</div><div class='add'>+	dev_err_mask-&gt;parerr_dcpr_ucs_mask = ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK;</div><div class='add'>+	dev_err_mask-&gt;parerr_pke_mask = ADF_420XX_PARITYERRORMASK_PKE_MASK;</div><div class='add'>+	dev_err_mask-&gt;ssmfeatren_mask = ADF_420XX_SSMFEATREN_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)</div><div class='add'>+{</div><div class='add'>+	hw_data-&gt;dev_class = &amp;adf_420xx_class;</div><div class='add'>+	hw_data-&gt;instance_id = adf_420xx_class.instances++;</div><div class='add'>+	hw_data-&gt;num_banks = ADF_GEN4_ETR_MAX_BANKS;</div><div class='add'>+	hw_data-&gt;num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;</div><div class='add'>+	hw_data-&gt;num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;</div><div class='add'>+	hw_data-&gt;num_accel = ADF_GEN4_MAX_ACCELERATORS;</div><div class='add'>+	hw_data-&gt;num_engines = ADF_420XX_MAX_ACCELENGINES;</div><div class='add'>+	hw_data-&gt;num_logical_accel = 1;</div><div class='add'>+	hw_data-&gt;tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;</div><div class='add'>+	hw_data-&gt;tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;</div><div class='add'>+	hw_data-&gt;ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;</div><div class='add'>+	hw_data-&gt;alloc_irq = adf_isr_resource_alloc;</div><div class='add'>+	hw_data-&gt;free_irq = adf_isr_resource_free;</div><div class='add'>+	hw_data-&gt;enable_error_correction = adf_gen4_enable_error_correction;</div><div class='add'>+	hw_data-&gt;get_accel_mask = adf_gen4_get_accel_mask;</div><div class='add'>+	hw_data-&gt;get_ae_mask = get_ae_mask;</div><div class='add'>+	hw_data-&gt;get_num_accels = adf_gen4_get_num_accels;</div><div class='add'>+	hw_data-&gt;get_num_aes = adf_gen4_get_num_aes;</div><div class='add'>+	hw_data-&gt;get_sram_bar_id = adf_gen4_get_sram_bar_id;</div><div class='add'>+	hw_data-&gt;get_etr_bar_id = adf_gen4_get_etr_bar_id;</div><div class='add'>+	hw_data-&gt;get_misc_bar_id = adf_gen4_get_misc_bar_id;</div><div class='add'>+	hw_data-&gt;get_arb_info = adf_gen4_get_arb_info;</div><div class='add'>+	hw_data-&gt;get_admin_info = adf_gen4_get_admin_info;</div><div class='add'>+	hw_data-&gt;get_accel_cap = get_accel_cap;</div><div class='add'>+	hw_data-&gt;get_sku = adf_gen4_get_sku;</div><div class='add'>+	hw_data-&gt;init_admin_comms = adf_init_admin_comms;</div><div class='add'>+	hw_data-&gt;exit_admin_comms = adf_exit_admin_comms;</div><div class='add'>+	hw_data-&gt;send_admin_init = adf_send_admin_init;</div><div class='add'>+	hw_data-&gt;init_arb = adf_init_arb;</div><div class='add'>+	hw_data-&gt;exit_arb = adf_exit_arb;</div><div class='add'>+	hw_data-&gt;get_arb_mapping = adf_get_arbiter_mapping;</div><div class='add'>+	hw_data-&gt;enable_ints = adf_gen4_enable_ints;</div><div class='add'>+	hw_data-&gt;init_device = adf_gen4_init_device;</div><div class='add'>+	hw_data-&gt;reset_device = adf_reset_flr;</div><div class='add'>+	hw_data-&gt;admin_ae_mask = ADF_420XX_ADMIN_AE_MASK;</div><div class='add'>+	hw_data-&gt;num_rps = ADF_GEN4_MAX_RPS;</div><div class='add'>+	hw_data-&gt;fw_name = ADF_420XX_FW;</div><div class='add'>+	hw_data-&gt;fw_mmp_name = ADF_420XX_MMP;</div><div class='add'>+	hw_data-&gt;uof_get_name = uof_get_name_420xx;</div><div class='add'>+	hw_data-&gt;uof_get_num_objs = uof_get_num_objs;</div><div class='add'>+	hw_data-&gt;uof_get_ae_mask = uof_get_ae_mask;</div><div class='add'>+	hw_data-&gt;get_rp_group = get_rp_group;</div><div class='add'>+	hw_data-&gt;get_ena_thd_mask = get_ena_thd_mask;</div><div class='add'>+	hw_data-&gt;set_msix_rttable = adf_gen4_set_msix_default_rttable;</div><div class='add'>+	hw_data-&gt;set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;</div><div class='add'>+	hw_data-&gt;get_ring_to_svc_map = get_ring_to_svc_map;</div><div class='add'>+	hw_data-&gt;disable_iov = adf_disable_sriov;</div><div class='add'>+	hw_data-&gt;ring_pair_reset = adf_gen4_ring_pair_reset;</div><div class='add'>+	hw_data-&gt;enable_pm = adf_gen4_enable_pm;</div><div class='add'>+	hw_data-&gt;handle_pm_interrupt = adf_gen4_handle_pm_interrupt;</div><div class='add'>+	hw_data-&gt;dev_config = adf_gen4_dev_config;</div><div class='add'>+	hw_data-&gt;start_timer = adf_gen4_timer_start;</div><div class='add'>+	hw_data-&gt;stop_timer = adf_gen4_timer_stop;</div><div class='add'>+	hw_data-&gt;get_hb_clock = adf_gen4_get_heartbeat_clock;</div><div class='add'>+	hw_data-&gt;num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;</div><div class='add'>+	hw_data-&gt;clock_frequency = ADF_420XX_AE_FREQ;</div><div class='add'>+</div><div class='add'>+	adf_gen4_set_err_mask(&amp;hw_data-&gt;dev_err_mask);</div><div class='add'>+	adf_gen4_init_hw_csr_ops(&amp;hw_data-&gt;csr_ops);</div><div class='add'>+	adf_gen4_init_pf_pfvf_ops(&amp;hw_data-&gt;pfvf_ops);</div><div class='add'>+	adf_gen4_init_dc_ops(&amp;hw_data-&gt;dc_ops);</div><div class='add'>+	adf_gen4_init_ras_ops(&amp;hw_data-&gt;ras_ops);</div><div class='add'>+	adf_gen4_init_tl_data(&amp;hw_data-&gt;tl_data);</div><div class='add'>+	adf_init_rl_data(&amp;hw_data-&gt;rl_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data)</div><div class='add'>+{</div><div class='add'>+	hw_data-&gt;dev_class-&gt;instances--;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h<br/>new file mode 100644<br/>index 000000000000..99abbfc14820<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#ifndef ADF_420XX_HW_DATA_H_</div><div class='add'>+#define ADF_420XX_HW_DATA_H_</div><div class='add'>+</div><div class='add'>+#include &lt;adf_accel_devices.h&gt;</div><div class='add'>+</div><div class='add'>+#define ADF_420XX_MAX_ACCELENGINES		17</div><div class='add'>+</div><div class='add'>+#define ADF_420XX_ACCELENGINES_MASK		0x1FFFF</div><div class='add'>+#define ADF_420XX_ADMIN_AE_MASK			0x10000</div><div class='add'>+</div><div class='add'>+#define ADF_420XX_HICPPAGENTCMDPARERRLOG_MASK	(0xFF)</div><div class='add'>+#define ADF_420XX_PARITYERRORMASK_ATH_CPH_MASK	(0xFF00FF)</div><div class='add'>+#define ADF_420XX_PARITYERRORMASK_CPR_XLT_MASK	(0x10001)</div><div class='add'>+#define ADF_420XX_PARITYERRORMASK_DCPR_UCS_MASK	(0xF0007)</div><div class='add'>+#define ADF_420XX_PARITYERRORMASK_PKE_MASK	(0xFFF)</div><div class='add'>+#define ADF_420XX_PARITYERRORMASK_WAT_WCP_MASK	(0x3FF03FF)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SSMFEATREN bit mask</div><div class='add'>+ * BIT(4) - enables parity detection on CPP</div><div class='add'>+ * BIT(12) - enables the logging of push/pull data errors</div><div class='add'>+ *	     in pperr register</div><div class='add'>+ * BIT(16) - BIT(27) - enable parity detection on SPPs</div><div class='add'>+ */</div><div class='add'>+#define ADF_420XX_SSMFEATREN_MASK \</div><div class='add'>+	(BIT(4) | BIT(12) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | \</div><div class='add'>+	 BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))</div><div class='add'>+</div><div class='add'>+/* Firmware Binaries */</div><div class='add'>+#define ADF_420XX_FW		"qat_420xx.bin"</div><div class='add'>+#define ADF_420XX_MMP		"qat_420xx_mmp.bin"</div><div class='add'>+#define ADF_420XX_SYM_OBJ	"qat_420xx_sym.bin"</div><div class='add'>+#define ADF_420XX_DC_OBJ	"qat_420xx_dc.bin"</div><div class='add'>+#define ADF_420XX_ASYM_OBJ	"qat_420xx_asym.bin"</div><div class='add'>+#define ADF_420XX_ADMIN_OBJ	"qat_420xx_admin.bin"</div><div class='add'>+</div><div class='add'>+/* RL constants */</div><div class='add'>+#define ADF_420XX_RL_PCIE_SCALE_FACTOR_DIV	100</div><div class='add'>+#define ADF_420XX_RL_PCIE_SCALE_FACTOR_MUL	102</div><div class='add'>+#define ADF_420XX_RL_DCPR_CORRECTION		1</div><div class='add'>+#define ADF_420XX_RL_SCANS_PER_SEC		954</div><div class='add'>+#define ADF_420XX_RL_MAX_TP_ASYM		173750UL</div><div class='add'>+#define ADF_420XX_RL_MAX_TP_SYM			95000UL</div><div class='add'>+#define ADF_420XX_RL_MAX_TP_DC			40000UL</div><div class='add'>+#define ADF_420XX_RL_SLICE_REF			1000UL</div><div class='add'>+</div><div class='add'>+/* Clocks frequency */</div><div class='add'>+#define ADF_420XX_AE_FREQ		(1000 * HZ_PER_MHZ)</div><div class='add'>+</div><div class='add'>+void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id);</div><div class='add'>+void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_drv.c b/drivers/crypto/intel/qat/qat_420xx/adf_drv.c<br/>new file mode 100644<br/>index 000000000000..2a3598409eeb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_420xx/adf_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_420xx/adf_drv.c</a></div><div class='hunk'>@@ -0,0 +1,202 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;adf_accel_devices.h&gt;</div><div class='add'>+#include &lt;adf_gen4_hw_data.h&gt;</div><div class='add'>+#include &lt;adf_gen4_config.h&gt;</div><div class='add'>+#include &lt;adf_cfg.h&gt;</div><div class='add'>+#include &lt;adf_common_drv.h&gt;</div><div class='add'>+#include &lt;adf_dbgfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include "adf_420xx_hw_data.h"</div><div class='add'>+</div><div class='add'>+static const struct pci_device_id adf_pci_tbl[] = {</div><div class='add'>+	{ PCI_VDEVICE(INTEL, ADF_420XX_PCI_DEVICE_ID), },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(pci, adf_pci_tbl);</div><div class='add'>+</div><div class='add'>+static void adf_cleanup_accel(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	if (accel_dev-&gt;hw_device) {</div><div class='add'>+		adf_clean_hw_data_420xx(accel_dev-&gt;hw_device);</div><div class='add'>+		accel_dev-&gt;hw_device = NULL;</div><div class='add'>+	}</div><div class='add'>+	adf_dbgfs_exit(accel_dev);</div><div class='add'>+	adf_cfg_dev_remove(accel_dev);</div><div class='add'>+	adf_devmgr_rm_dev(accel_dev, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='add'>+{</div><div class='add'>+	struct adf_accel_dev *accel_dev;</div><div class='add'>+	struct adf_accel_pci *accel_pci_dev;</div><div class='add'>+	struct adf_hw_device_data *hw_data;</div><div class='add'>+	unsigned int i, bar_nr;</div><div class='add'>+	unsigned long bar_mask;</div><div class='add'>+	struct adf_bar *bar;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (num_possible_nodes() &gt; 1 &amp;&amp; dev_to_node(&amp;pdev-&gt;dev) &lt; 0) {</div><div class='add'>+		/*</div><div class='add'>+		 * If the accelerator is connected to a node with no memory</div><div class='add'>+		 * there is no point in using the accelerator since the remote</div><div class='add'>+		 * memory transaction will be very slow.</div><div class='add'>+		 */</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Invalid NUMA configuration.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	accel_dev = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*accel_dev), GFP_KERNEL);</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;accel_dev-&gt;crypto_list);</div><div class='add'>+	accel_pci_dev = &amp;accel_dev-&gt;accel_pci_dev;</div><div class='add'>+	accel_pci_dev-&gt;pci_dev = pdev;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Add accel device to accel table</div><div class='add'>+	 * This should be called before adf_cleanup_accel is called</div><div class='add'>+	 */</div><div class='add'>+	if (adf_devmgr_add_dev(accel_dev, NULL)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to add new accelerator device.\n");</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	accel_dev-&gt;owner = THIS_MODULE;</div><div class='add'>+	/* Allocate and initialise device hardware meta-data structure */</div><div class='add'>+	hw_data = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*hw_data), GFP_KERNEL);</div><div class='add'>+	if (!hw_data) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	accel_dev-&gt;hw_device = hw_data;</div><div class='add'>+	adf_init_hw_data_420xx(accel_dev-&gt;hw_device, ent-&gt;device);</div><div class='add'>+</div><div class='add'>+	pci_read_config_byte(pdev, PCI_REVISION_ID, &amp;accel_pci_dev-&gt;revid);</div><div class='add'>+	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &amp;hw_data-&gt;fuses);</div><div class='add'>+</div><div class='add'>+	/* Get Accelerators and Accelerators Engines masks */</div><div class='add'>+	hw_data-&gt;accel_mask = hw_data-&gt;get_accel_mask(hw_data);</div><div class='add'>+	hw_data-&gt;ae_mask = hw_data-&gt;get_ae_mask(hw_data);</div><div class='add'>+	accel_pci_dev-&gt;sku = hw_data-&gt;get_sku(hw_data);</div><div class='add'>+	/* If the device has no acceleration engines then ignore it */</div><div class='add'>+	if (!hw_data-&gt;accel_mask || !hw_data-&gt;ae_mask ||</div><div class='add'>+	    (~hw_data-&gt;ae_mask &amp; 0x01)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "No acceleration units found.\n");</div><div class='add'>+		ret = -EFAULT;</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Create device configuration table */</div><div class='add'>+	ret = adf_cfg_dev_add(accel_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_err;</div><div class='add'>+</div><div class='add'>+	/* Enable PCI device */</div><div class='add'>+	ret = pcim_enable_device(pdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Can't enable PCI device.\n");</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set DMA identifier */</div><div class='add'>+	ret = dma_set_mask_and_coherent(&amp;pdev-&gt;dev, DMA_BIT_MASK(64));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "No usable DMA configuration.\n");</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = adf_gen4_cfg_dev_init(accel_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to initialize configuration.\n");</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get accelerator capabilities mask */</div><div class='add'>+	hw_data-&gt;accel_capabilities_mask = hw_data-&gt;get_accel_cap(accel_dev);</div><div class='add'>+	if (!hw_data-&gt;accel_capabilities_mask) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to get capabilities mask.\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Find and map all the device's BARS */</div><div class='add'>+	bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) &amp; ADF_GEN4_BAR_MASK;</div><div class='add'>+</div><div class='add'>+	ret = pcim_iomap_regions_request_all(pdev, bar_mask, pci_name(pdev));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to map pci regions.\n");</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	i = 0;</div><div class='add'>+	for_each_set_bit(bar_nr, &amp;bar_mask, PCI_STD_NUM_BARS) {</div><div class='add'>+		bar = &amp;accel_pci_dev-&gt;pci_bars[i++];</div><div class='add'>+		bar-&gt;virt_addr = pcim_iomap_table(pdev)[bar_nr];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pci_set_master(pdev);</div><div class='add'>+</div><div class='add'>+	if (pci_save_state(pdev)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to save pci state.\n");</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	accel_dev-&gt;ras_errors.enabled = true;</div><div class='add'>+	adf_dbgfs_init(accel_dev);</div><div class='add'>+</div><div class='add'>+	ret = adf_dev_up(accel_dev, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_err_dev_stop;</div><div class='add'>+</div><div class='add'>+	ret = adf_sysfs_init(accel_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_err_dev_stop;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+out_err_dev_stop:</div><div class='add'>+	adf_dev_down(accel_dev, false);</div><div class='add'>+out_err:</div><div class='add'>+	adf_cleanup_accel(accel_dev);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void adf_remove(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);</div><div class='add'>+</div><div class='add'>+	if (!accel_dev) {</div><div class='add'>+		pr_err("QAT: Driver removal failed\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	adf_dev_down(accel_dev, false);</div><div class='add'>+	adf_cleanup_accel(accel_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct pci_driver adf_driver = {</div><div class='add'>+	.id_table = adf_pci_tbl,</div><div class='add'>+	.name = ADF_420XX_DEVICE_NAME,</div><div class='add'>+	.probe = adf_probe,</div><div class='add'>+	.remove = adf_remove,</div><div class='add'>+	.sriov_configure = adf_sriov_configure,</div><div class='add'>+	.err_handler = &amp;adf_err_handler,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_pci_driver(adf_driver);</div><div class='add'>+</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Intel");</div><div class='add'>+MODULE_FIRMWARE(ADF_420XX_FW);</div><div class='add'>+MODULE_FIRMWARE(ADF_420XX_MMP);</div><div class='add'>+MODULE_DESCRIPTION("Intel(R) QuickAssist Technology");</div><div class='add'>+MODULE_VERSION(ADF_DRV_VERSION);</div><div class='add'>+MODULE_SOFTDEP("pre: crypto-intel_qat");</div><div class='add'>+MODULE_IMPORT_NS(CRYPTO_QAT);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c<br/>index 0faedb5b2eb5..479062aa5e6b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c</a></div><div class='hunk'>@@ -7,12 +7,15 @@</div><div class='ctx'> #include &lt;adf_cfg_services.h&gt;</div><div class='ctx'> #include &lt;adf_clock.h&gt;</div><div class='ctx'> #include &lt;adf_common_drv.h&gt;</div><div class='add'>+#include &lt;adf_fw_config.h&gt;</div><div class='add'>+#include &lt;adf_gen4_config.h&gt;</div><div class='ctx'> #include &lt;adf_gen4_dc.h&gt;</div><div class='ctx'> #include &lt;adf_gen4_hw_data.h&gt;</div><div class='ctx'> #include &lt;adf_gen4_pfvf.h&gt;</div><div class='ctx'> #include &lt;adf_gen4_pm.h&gt;</div><div class='ctx'> #include "adf_gen4_ras.h"</div><div class='ctx'> #include &lt;adf_gen4_timer.h&gt;</div><div class='add'>+#include &lt;adf_gen4_tl.h&gt;</div><div class='ctx'> #include "adf_4xxx_hw_data.h"</div><div class='ctx'> #include "icp_qat_hw.h"</div><div class='ctx'> </div><div class='hunk'>@@ -20,12 +23,10 @@</div><div class='ctx'> #define ADF_AE_GROUP_1		GENMASK(7, 4)</div><div class='ctx'> #define ADF_AE_GROUP_2		BIT(8)</div><div class='ctx'> </div><div class='del'>-enum adf_fw_objs {</div><div class='del'>-	ADF_FW_SYM_OBJ,</div><div class='del'>-	ADF_FW_ASYM_OBJ,</div><div class='del'>-	ADF_FW_DC_OBJ,</div><div class='del'>-	ADF_FW_ADMIN_OBJ,</div><div class='del'>-};</div><div class='add'>+#define ENA_THD_MASK_ASYM	GENMASK(1, 0)</div><div class='add'>+#define ENA_THD_MASK_ASYM_401XX	GENMASK(5, 0)</div><div class='add'>+#define ENA_THD_MASK_SYM	GENMASK(6, 0)</div><div class='add'>+#define ENA_THD_MASK_DC		GENMASK(1, 0)</div><div class='ctx'> </div><div class='ctx'> static const char * const adf_4xxx_fw_objs[] = {</div><div class='ctx'> 	[ADF_FW_SYM_OBJ] =  ADF_4XXX_SYM_OBJ,</div><div class='hunk'>@@ -41,11 +42,6 @@ static const char * const adf_402xx_fw_objs[] = {</div><div class='ctx'> 	[ADF_FW_ADMIN_OBJ] = ADF_402XX_ADMIN_OBJ,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct adf_fw_config {</div><div class='del'>-	u32 ae_mask;</div><div class='del'>-	enum adf_fw_objs obj;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct adf_fw_config adf_fw_cy_config[] = {</div><div class='ctx'> 	{ADF_AE_GROUP_1, ADF_FW_SYM_OBJ},</div><div class='ctx'> 	{ADF_AE_GROUP_0, ADF_FW_ASYM_OBJ},</div><div class='hunk'>@@ -95,59 +91,12 @@ static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_dc_config))</div><div class='ctx'> static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_dc_config));</div><div class='ctx'> static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_dcc_config));</div><div class='ctx'> </div><div class='del'>-/* Worker thread to service arbiter mappings */</div><div class='del'>-static const u32 default_thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {</div><div class='del'>-	0x5555555, 0x5555555, 0x5555555, 0x5555555,</div><div class='del'>-	0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,</div><div class='del'>-	0x0</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 thrd_to_arb_map_dc[ADF_4XXX_MAX_ACCELENGINES] = {</div><div class='del'>-	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,</div><div class='del'>-	0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,</div><div class='del'>-	0x0</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const u32 thrd_to_arb_map_dcc[ADF_4XXX_MAX_ACCELENGINES] = {</div><div class='del'>-	0x00000000, 0x00000000, 0x00000000, 0x00000000,</div><div class='del'>-	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,</div><div class='del'>-	0x0</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static struct adf_hw_device_class adf_4xxx_class = {</div><div class='ctx'> 	.name = ADF_4XXX_DEVICE_NAME,</div><div class='ctx'> 	.type = DEV_4XXX,</div><div class='ctx'> 	.instances = 0,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int get_service_enabled(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,</div><div class='del'>-				      ADF_SERVICES_ENABLED, services);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;GET_DEV(accel_dev),</div><div class='del'>-			ADF_SERVICES_ENABLED " param not found\n");</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = match_string(adf_cfg_services, ARRAY_SIZE(adf_cfg_services),</div><div class='del'>-			   services);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		dev_err(&amp;GET_DEV(accel_dev),</div><div class='del'>-			"Invalid value of " ADF_SERVICES_ENABLED " param: %s\n",</div><div class='del'>-			services);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_accel_mask(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return ADF_4XXX_ACCELERATORS_MASK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u32 get_ae_mask(struct adf_hw_device_data *self)</div><div class='ctx'> {</div><div class='ctx'> 	u32 me_disable = self-&gt;fuses;</div><div class='hunk'>@@ -155,55 +104,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)</div><div class='ctx'> 	return ~me_disable &amp; ADF_4XXX_ACCELENGINES_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 get_num_accels(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return ADF_4XXX_MAX_ACCELERATORS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_num_aes(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	if (!self || !self-&gt;ae_mask)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return hweight32(self-&gt;ae_mask);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_misc_bar_id(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return ADF_4XXX_PMISC_BAR;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_etr_bar_id(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return ADF_4XXX_ETR_BAR;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_sram_bar_id(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return ADF_4XXX_SRAM_BAR;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * The vector routing table is used to select the MSI-X entry to use for each</div><div class='del'>- * interrupt source.</div><div class='del'>- * The first ADF_4XXX_ETR_MAX_BANKS entries correspond to ring interrupts.</div><div class='del'>- * The final entry corresponds to VF2PF or error interrupts.</div><div class='del'>- * This vector table could be used to configure one MSI-X entry to be shared</div><div class='del'>- * between multiple interrupt sources.</div><div class='del'>- *</div><div class='del'>- * The default routing is set to have a one to one correspondence between the</div><div class='del'>- * interrupt source and the MSI-X entry used.</div><div class='del'>- */</div><div class='del'>-static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	void __iomem *csr;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	csr = (&amp;GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])-&gt;virt_addr;</div><div class='del'>-	for (i = 0; i &lt;= ADF_4XXX_ETR_MAX_BANKS; i++)</div><div class='del'>-		ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev = accel_dev-&gt;accel_pci_dev.pci_dev;</div><div class='hunk'>@@ -212,7 +112,7 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	u32 fusectl1;</div><div class='ctx'> </div><div class='ctx'> 	/* Read accelerator capabilities mask */</div><div class='del'>-	pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &amp;fusectl1);</div><div class='add'>+	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL1_OFFSET, &amp;fusectl1);</div><div class='ctx'> </div><div class='ctx'> 	capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_CIPHER |</div><div class='hunk'>@@ -227,27 +127,27 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_AES_V2;</div><div class='ctx'> </div><div class='ctx'> 	/* A set bit in fusectl1 means the feature is OFF in this SKU */</div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_CIPHER_SLICE) {</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_HKDF;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_UCS_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_UCS_SLICE) {</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AES_V2;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_AUTH_SLICE) {</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SHA3;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_CIPHER;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_SMX_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_SMX_SLICE) {</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SM3;</div><div class='ctx'> 		capabilities_sym &amp;= ~ICP_ACCEL_CAPABILITIES_SM4;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -257,7 +157,7 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_SM2 |</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_ECEDMONT;</div><div class='ctx'> </div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_PKE_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_PKE_SLICE) {</div><div class='ctx'> 		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;</div><div class='ctx'> 		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_SM2;</div><div class='ctx'> 		capabilities_asym &amp;= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;</div><div class='hunk'>@@ -268,14 +168,14 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |</div><div class='ctx'> 			  ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;</div><div class='ctx'> </div><div class='del'>-	if (fusectl1 &amp; ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {</div><div class='add'>+	if (fusectl1 &amp; ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE) {</div><div class='ctx'> 		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;</div><div class='ctx'> 		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;</div><div class='ctx'> 		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;</div><div class='ctx'> 		capabilities_dc &amp;= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	switch (get_service_enabled(accel_dev)) {</div><div class='add'>+	switch (adf_get_service_enabled(accel_dev)) {</div><div class='ctx'> 	case SVC_CY:</div><div class='ctx'> 	case SVC_CY2:</div><div class='ctx'> 		return capabilities_sym | capabilities_asym;</div><div class='hunk'>@@ -304,43 +204,13 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum dev_sku_info get_sku(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	return DEV_SKU_1;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='del'>-	switch (get_service_enabled(accel_dev)) {</div><div class='del'>-	case SVC_DC:</div><div class='del'>-		return thrd_to_arb_map_dc;</div><div class='del'>-	case SVC_DCC:</div><div class='del'>-		return thrd_to_arb_map_dcc;</div><div class='del'>-	default:</div><div class='del'>-		return default_thrd_to_arb_map;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void get_arb_info(struct arb_info *arb_info)</div><div class='del'>-{</div><div class='del'>-	arb_info-&gt;arb_cfg = ADF_4XXX_ARB_CONFIG;</div><div class='del'>-	arb_info-&gt;arb_offset = ADF_4XXX_ARB_OFFSET;</div><div class='del'>-	arb_info-&gt;wt2sam_offset = ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET;</div><div class='del'>-}</div><div class='add'>+	if (adf_gen4_init_thd2arb_map(accel_dev))</div><div class='add'>+		dev_warn(&amp;GET_DEV(accel_dev),</div><div class='add'>+			 "Generate of the thread to arbiter map failed");</div><div class='ctx'> </div><div class='del'>-static void get_admin_info(struct admin_info *admin_csrs_info)</div><div class='del'>-{</div><div class='del'>-	admin_csrs_info-&gt;mailbox_offset = ADF_4XXX_MAILBOX_BASE_OFFSET;</div><div class='del'>-	admin_csrs_info-&gt;admin_msg_ur = ADF_4XXX_ADMINMSGUR_OFFSET;</div><div class='del'>-	admin_csrs_info-&gt;admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 get_heartbeat_clock(struct adf_hw_device_data *self)</div><div class='del'>-{</div><div class='del'>-	/*</div><div class='del'>-	 * 4XXX uses KPT counter for HB</div><div class='del'>-	 */</div><div class='del'>-	return ADF_4XXX_KPT_COUNTER_FREQ;</div><div class='add'>+	return GET_HW_DATA(accel_dev)-&gt;thd_to_arb_map;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)</div><div class='hunk'>@@ -361,66 +231,14 @@ static void adf_init_rl_data(struct adf_rl_hw_data *rl_data)</div><div class='ctx'> 	rl_data-&gt;scale_ref = ADF_4XXX_RL_SLICE_REF;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	struct adf_bar *misc_bar = &amp;GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];</div><div class='del'>-	void __iomem *csr = misc_bar-&gt;virt_addr;</div><div class='del'>-</div><div class='del'>-	/* Enable all in errsou3 except VFLR notification on host */</div><div class='del'>-	ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void adf_enable_ints(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	void __iomem *addr;</div><div class='del'>-</div><div class='del'>-	addr = (&amp;GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])-&gt;virt_addr;</div><div class='del'>-</div><div class='del'>-	/* Enable bundle interrupts */</div><div class='del'>-	ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0);</div><div class='del'>-	ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0);</div><div class='del'>-</div><div class='del'>-	/* Enable misc interrupts */</div><div class='del'>-	ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int adf_init_device(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	void __iomem *addr;</div><div class='del'>-	u32 status;</div><div class='del'>-	u32 csr;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	addr = (&amp;GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])-&gt;virt_addr;</div><div class='del'>-</div><div class='del'>-	/* Temporarily mask PM interrupt */</div><div class='del'>-	csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2);</div><div class='del'>-	csr |= ADF_GEN4_PM_SOU;</div><div class='del'>-	ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr);</div><div class='del'>-</div><div class='del'>-	/* Set DRV_ACTIVE bit to power up the device */</div><div class='del'>-	ADF_CSR_WR(addr, ADF_GEN4_PM_INTERRUPT, ADF_GEN4_PM_DRV_ACTIVE);</div><div class='del'>-</div><div class='del'>-	/* Poll status register to make sure the device is powered up */</div><div class='del'>-	ret = read_poll_timeout(ADF_CSR_RD, status,</div><div class='del'>-				status &amp; ADF_GEN4_PM_INIT_STATE,</div><div class='del'>-				ADF_GEN4_PM_POLL_DELAY_US,</div><div class='del'>-				ADF_GEN4_PM_POLL_TIMEOUT_US, true, addr,</div><div class='del'>-				ADF_GEN4_PM_STATUS);</div><div class='del'>-	if (ret)</div><div class='del'>-		dev_err(&amp;GET_DEV(accel_dev), "Failed to power up the device\n");</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 uof_get_num_objs(void)</div><div class='add'>+static u32 uof_get_num_objs(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='ctx'> 	return ARRAY_SIZE(adf_fw_cy_config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='del'>-	switch (get_service_enabled(accel_dev)) {</div><div class='add'>+	switch (adf_get_service_enabled(accel_dev)) {</div><div class='ctx'> 	case SVC_CY:</div><div class='ctx'> 	case SVC_CY2:</div><div class='ctx'> 		return adf_fw_cy_config;</div><div class='hunk'>@@ -443,11 +261,64 @@ static const struct adf_fw_config *get_fw_config(struct adf_accel_dev *accel_dev</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum adf_rp_groups {</div><div class='del'>-	RP_GROUP_0 = 0,</div><div class='del'>-	RP_GROUP_1,</div><div class='del'>-	RP_GROUP_COUNT</div><div class='del'>-};</div><div class='add'>+static int get_rp_group(struct adf_accel_dev *accel_dev, u32 ae_mask)</div><div class='add'>+{</div><div class='add'>+	switch (ae_mask) {</div><div class='add'>+	case ADF_AE_GROUP_0:</div><div class='add'>+		return RP_GROUP_0;</div><div class='add'>+	case ADF_AE_GROUP_1:</div><div class='add'>+		return RP_GROUP_1;</div><div class='add'>+	default:</div><div class='add'>+		dev_dbg(&amp;GET_DEV(accel_dev), "ae_mask not recognized");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_ena_thd_mask(struct adf_accel_dev *accel_dev, u32 obj_num)</div><div class='add'>+{</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+</div><div class='add'>+	if (obj_num &gt;= uof_get_num_objs(accel_dev))</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (!fw_config)</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	switch (fw_config[obj_num].obj) {</div><div class='add'>+	case ADF_FW_ASYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_ASYM;</div><div class='add'>+	case ADF_FW_SYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_SYM;</div><div class='add'>+	case ADF_FW_DC_OBJ:</div><div class='add'>+		return ENA_THD_MASK_DC;</div><div class='add'>+	default:</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_ena_thd_mask_401xx(struct adf_accel_dev *accel_dev, u32 obj_num)</div><div class='add'>+{</div><div class='add'>+	const struct adf_fw_config *fw_config;</div><div class='add'>+</div><div class='add'>+	if (obj_num &gt;= uof_get_num_objs(accel_dev))</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	fw_config = get_fw_config(accel_dev);</div><div class='add'>+	if (!fw_config)</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+</div><div class='add'>+	switch (fw_config[obj_num].obj) {</div><div class='add'>+	case ADF_FW_ASYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_ASYM_401XX;</div><div class='add'>+	case ADF_FW_SYM_OBJ:</div><div class='add'>+		return ENA_THD_MASK_SYM;</div><div class='add'>+	case ADF_FW_DC_OBJ:</div><div class='add'>+		return ENA_THD_MASK_DC;</div><div class='add'>+	default:</div><div class='add'>+		return ADF_GEN4_ENA_THD_MASK_ERROR;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -553,54 +424,63 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	hw_data-&gt;dev_class = &amp;adf_4xxx_class;</div><div class='ctx'> 	hw_data-&gt;instance_id = adf_4xxx_class.instances++;</div><div class='del'>-	hw_data-&gt;num_banks = ADF_4XXX_ETR_MAX_BANKS;</div><div class='del'>-	hw_data-&gt;num_banks_per_vf = ADF_4XXX_NUM_BANKS_PER_VF;</div><div class='del'>-	hw_data-&gt;num_rings_per_bank = ADF_4XXX_NUM_RINGS_PER_BANK;</div><div class='del'>-	hw_data-&gt;num_accel = ADF_4XXX_MAX_ACCELERATORS;</div><div class='add'>+	hw_data-&gt;num_banks = ADF_GEN4_ETR_MAX_BANKS;</div><div class='add'>+	hw_data-&gt;num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;</div><div class='add'>+	hw_data-&gt;num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;</div><div class='add'>+	hw_data-&gt;num_accel = ADF_GEN4_MAX_ACCELERATORS;</div><div class='ctx'> 	hw_data-&gt;num_engines = ADF_4XXX_MAX_ACCELENGINES;</div><div class='ctx'> 	hw_data-&gt;num_logical_accel = 1;</div><div class='del'>-	hw_data-&gt;tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;</div><div class='del'>-	hw_data-&gt;tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;</div><div class='add'>+	hw_data-&gt;tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;</div><div class='add'>+	hw_data-&gt;tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;</div><div class='ctx'> 	hw_data-&gt;ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;</div><div class='ctx'> 	hw_data-&gt;alloc_irq = adf_isr_resource_alloc;</div><div class='ctx'> 	hw_data-&gt;free_irq = adf_isr_resource_free;</div><div class='del'>-	hw_data-&gt;enable_error_correction = adf_enable_error_correction;</div><div class='del'>-	hw_data-&gt;get_accel_mask = get_accel_mask;</div><div class='add'>+	hw_data-&gt;enable_error_correction = adf_gen4_enable_error_correction;</div><div class='add'>+	hw_data-&gt;get_accel_mask = adf_gen4_get_accel_mask;</div><div class='ctx'> 	hw_data-&gt;get_ae_mask = get_ae_mask;</div><div class='del'>-	hw_data-&gt;get_num_accels = get_num_accels;</div><div class='del'>-	hw_data-&gt;get_num_aes = get_num_aes;</div><div class='del'>-	hw_data-&gt;get_sram_bar_id = get_sram_bar_id;</div><div class='del'>-	hw_data-&gt;get_etr_bar_id = get_etr_bar_id;</div><div class='del'>-	hw_data-&gt;get_misc_bar_id = get_misc_bar_id;</div><div class='del'>-	hw_data-&gt;get_arb_info = get_arb_info;</div><div class='del'>-	hw_data-&gt;get_admin_info = get_admin_info;</div><div class='add'>+	hw_data-&gt;get_num_accels = adf_gen4_get_num_accels;</div><div class='add'>+	hw_data-&gt;get_num_aes = adf_gen4_get_num_aes;</div><div class='add'>+	hw_data-&gt;get_sram_bar_id = adf_gen4_get_sram_bar_id;</div><div class='add'>+	hw_data-&gt;get_etr_bar_id = adf_gen4_get_etr_bar_id;</div><div class='add'>+	hw_data-&gt;get_misc_bar_id = adf_gen4_get_misc_bar_id;</div><div class='add'>+	hw_data-&gt;get_arb_info = adf_gen4_get_arb_info;</div><div class='add'>+	hw_data-&gt;get_admin_info = adf_gen4_get_admin_info;</div><div class='ctx'> 	hw_data-&gt;get_accel_cap = get_accel_cap;</div><div class='del'>-	hw_data-&gt;get_sku = get_sku;</div><div class='add'>+	hw_data-&gt;get_sku = adf_gen4_get_sku;</div><div class='ctx'> 	hw_data-&gt;init_admin_comms = adf_init_admin_comms;</div><div class='ctx'> 	hw_data-&gt;exit_admin_comms = adf_exit_admin_comms;</div><div class='ctx'> 	hw_data-&gt;send_admin_init = adf_send_admin_init;</div><div class='ctx'> 	hw_data-&gt;init_arb = adf_init_arb;</div><div class='ctx'> 	hw_data-&gt;exit_arb = adf_exit_arb;</div><div class='ctx'> 	hw_data-&gt;get_arb_mapping = adf_get_arbiter_mapping;</div><div class='del'>-	hw_data-&gt;enable_ints = adf_enable_ints;</div><div class='del'>-	hw_data-&gt;init_device = adf_init_device;</div><div class='add'>+	hw_data-&gt;enable_ints = adf_gen4_enable_ints;</div><div class='add'>+	hw_data-&gt;init_device = adf_gen4_init_device;</div><div class='ctx'> 	hw_data-&gt;reset_device = adf_reset_flr;</div><div class='ctx'> 	hw_data-&gt;admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;</div><div class='add'>+	hw_data-&gt;num_rps = ADF_GEN4_MAX_RPS;</div><div class='ctx'> 	switch (dev_id) {</div><div class='ctx'> 	case ADF_402XX_PCI_DEVICE_ID:</div><div class='ctx'> 		hw_data-&gt;fw_name = ADF_402XX_FW;</div><div class='ctx'> 		hw_data-&gt;fw_mmp_name = ADF_402XX_MMP;</div><div class='ctx'> 		hw_data-&gt;uof_get_name = uof_get_name_402xx;</div><div class='ctx'> 		break;</div><div class='del'>-</div><div class='add'>+	case ADF_401XX_PCI_DEVICE_ID:</div><div class='add'>+		hw_data-&gt;fw_name = ADF_4XXX_FW;</div><div class='add'>+		hw_data-&gt;fw_mmp_name = ADF_4XXX_MMP;</div><div class='add'>+		hw_data-&gt;uof_get_name = uof_get_name_4xxx;</div><div class='add'>+		hw_data-&gt;get_ena_thd_mask = get_ena_thd_mask_401xx;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_data-&gt;fw_name = ADF_4XXX_FW;</div><div class='ctx'> 		hw_data-&gt;fw_mmp_name = ADF_4XXX_MMP;</div><div class='ctx'> 		hw_data-&gt;uof_get_name = uof_get_name_4xxx;</div><div class='add'>+		hw_data-&gt;get_ena_thd_mask = get_ena_thd_mask;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	hw_data-&gt;uof_get_num_objs = uof_get_num_objs;</div><div class='ctx'> 	hw_data-&gt;uof_get_ae_mask = uof_get_ae_mask;</div><div class='del'>-	hw_data-&gt;set_msix_rttable = set_msix_default_rttable;</div><div class='add'>+	hw_data-&gt;get_rp_group = get_rp_group;</div><div class='add'>+	hw_data-&gt;set_msix_rttable = adf_gen4_set_msix_default_rttable;</div><div class='ctx'> 	hw_data-&gt;set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;</div><div class='ctx'> 	hw_data-&gt;get_ring_to_svc_map = get_ring_to_svc_map;</div><div class='ctx'> 	hw_data-&gt;disable_iov = adf_disable_sriov;</div><div class='hunk'>@@ -610,7 +490,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)</div><div class='ctx'> 	hw_data-&gt;dev_config = adf_gen4_dev_config;</div><div class='ctx'> 	hw_data-&gt;start_timer = adf_gen4_timer_start;</div><div class='ctx'> 	hw_data-&gt;stop_timer = adf_gen4_timer_stop;</div><div class='del'>-	hw_data-&gt;get_hb_clock = get_heartbeat_clock;</div><div class='add'>+	hw_data-&gt;get_hb_clock = adf_gen4_get_heartbeat_clock;</div><div class='ctx'> 	hw_data-&gt;num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;</div><div class='ctx'> 	hw_data-&gt;clock_frequency = ADF_4XXX_AE_FREQ;</div><div class='ctx'> </div><div class='hunk'>@@ -619,6 +499,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)</div><div class='ctx'> 	adf_gen4_init_pf_pfvf_ops(&amp;hw_data-&gt;pfvf_ops);</div><div class='ctx'> 	adf_gen4_init_dc_ops(&amp;hw_data-&gt;dc_ops);</div><div class='ctx'> 	adf_gen4_init_ras_ops(&amp;hw_data-&gt;ras_ops);</div><div class='add'>+	adf_gen4_init_tl_data(&amp;hw_data-&gt;tl_data);</div><div class='ctx'> 	adf_init_rl_data(&amp;hw_data-&gt;rl_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h<br/>index 33423295e90f..76388363ea87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h</a></div><div class='hunk'>@@ -6,25 +6,8 @@</div><div class='ctx'> #include &lt;linux/units.h&gt;</div><div class='ctx'> #include &lt;adf_accel_devices.h&gt;</div><div class='ctx'> </div><div class='del'>-/* PCIe configuration space */</div><div class='del'>-#define ADF_4XXX_SRAM_BAR		0</div><div class='del'>-#define ADF_4XXX_PMISC_BAR		1</div><div class='del'>-#define ADF_4XXX_ETR_BAR		2</div><div class='del'>-#define ADF_4XXX_RX_RINGS_OFFSET	1</div><div class='del'>-#define ADF_4XXX_TX_RINGS_MASK		0x1</div><div class='del'>-#define ADF_4XXX_MAX_ACCELERATORS	1</div><div class='ctx'> #define ADF_4XXX_MAX_ACCELENGINES	9</div><div class='del'>-#define ADF_4XXX_BAR_MASK		(BIT(0) | BIT(2) | BIT(4))</div><div class='ctx'> </div><div class='del'>-/* Physical function fuses */</div><div class='del'>-#define ADF_4XXX_FUSECTL0_OFFSET	(0x2C8)</div><div class='del'>-#define ADF_4XXX_FUSECTL1_OFFSET	(0x2CC)</div><div class='del'>-#define ADF_4XXX_FUSECTL2_OFFSET	(0x2D0)</div><div class='del'>-#define ADF_4XXX_FUSECTL3_OFFSET	(0x2D4)</div><div class='del'>-#define ADF_4XXX_FUSECTL4_OFFSET	(0x2D8)</div><div class='del'>-#define ADF_4XXX_FUSECTL5_OFFSET	(0x2DC)</div><div class='del'>-</div><div class='del'>-#define ADF_4XXX_ACCELERATORS_MASK	(0x1)</div><div class='ctx'> #define ADF_4XXX_ACCELENGINES_MASK	(0x1FF)</div><div class='ctx'> #define ADF_4XXX_ADMIN_AE_MASK		(0x100)</div><div class='ctx'> </div><div class='hunk'>@@ -45,28 +28,6 @@</div><div class='ctx'> 	(BIT(4) | BIT(12) | BIT(16) | BIT(17) | BIT(18) | \</div><div class='ctx'> 	 BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))</div><div class='ctx'> </div><div class='del'>-#define ADF_4XXX_ETR_MAX_BANKS		64</div><div class='del'>-</div><div class='del'>-/* MSIX interrupt */</div><div class='del'>-#define ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET	(0x41A040)</div><div class='del'>-#define ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET	(0x41A044)</div><div class='del'>-#define ADF_4XXX_SMIAPF_MASK_OFFSET		(0x41A084)</div><div class='del'>-#define ADF_4XXX_MSIX_RTTABLE_OFFSET(i)		(0x409000 + ((i) * 0x04))</div><div class='del'>-</div><div class='del'>-/* Bank and ring configuration */</div><div class='del'>-#define ADF_4XXX_NUM_RINGS_PER_BANK	2</div><div class='del'>-#define ADF_4XXX_NUM_BANKS_PER_VF	4</div><div class='del'>-</div><div class='del'>-/* Arbiter configuration */</div><div class='del'>-#define ADF_4XXX_ARB_CONFIG			(BIT(31) | BIT(6) | BIT(0))</div><div class='del'>-#define ADF_4XXX_ARB_OFFSET			(0x0)</div><div class='del'>-#define ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET	(0x400)</div><div class='del'>-</div><div class='del'>-/* Admin Interface Reg Offset */</div><div class='del'>-#define ADF_4XXX_ADMINMSGUR_OFFSET	(0x500574)</div><div class='del'>-#define ADF_4XXX_ADMINMSGLR_OFFSET	(0x500578)</div><div class='del'>-#define ADF_4XXX_MAILBOX_BASE_OFFSET	(0x600970)</div><div class='del'>-</div><div class='ctx'> /* Firmware Binaries */</div><div class='ctx'> #define ADF_4XXX_FW		"qat_4xxx.bin"</div><div class='ctx'> #define ADF_4XXX_MMP		"qat_4xxx_mmp.bin"</div><div class='hunk'>@@ -93,22 +54,9 @@</div><div class='ctx'> #define ADF_4XXX_RL_SLICE_REF			1000UL</div><div class='ctx'> </div><div class='ctx'> /* Clocks frequency */</div><div class='del'>-#define ADF_4XXX_KPT_COUNTER_FREQ	(100 * HZ_PER_MHZ)</div><div class='ctx'> #define ADF_4XXX_AE_FREQ		(1000 * HZ_PER_MHZ)</div><div class='ctx'> </div><div class='del'>-/* qat_4xxx fuse bits are different from old GENs, redefine them */</div><div class='del'>-enum icp_qat_4xxx_slice_mask {</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),</div><div class='del'>-	ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(7),</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id);</div><div class='ctx'> void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);</div><div class='del'>-int adf_gen4_dev_config(struct adf_accel_dev *accel_dev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c b/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c<br/>index 8f483d1197dd..9762f2bf7727 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_4xxx/adf_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_4xxx/adf_drv.c</a></div><div class='hunk'>@@ -8,13 +8,10 @@</div><div class='ctx'> #include &lt;adf_cfg.h&gt;</div><div class='ctx'> #include &lt;adf_common_drv.h&gt;</div><div class='ctx'> #include &lt;adf_dbgfs.h&gt;</div><div class='del'>-#include &lt;adf_heartbeat.h&gt;</div><div class='add'>+#include &lt;adf_gen4_config.h&gt;</div><div class='add'>+#include &lt;adf_gen4_hw_data.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "adf_4xxx_hw_data.h"</div><div class='del'>-#include "adf_cfg_services.h"</div><div class='del'>-#include "qat_compression.h"</div><div class='del'>-#include "qat_crypto.h"</div><div class='del'>-#include "adf_transport_access_macros.h"</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id adf_pci_tbl[] = {</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, ADF_4XXX_PCI_DEVICE_ID), },</div><div class='hunk'>@@ -35,270 +32,6 @@ static void adf_cleanup_accel(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	adf_devmgr_rm_dev(accel_dev, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int adf_cfg_dev_init(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	const char *config;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	config = accel_dev-&gt;accel_id % 2 ? ADF_CFG_DC : ADF_CFG_CY;</div><div class='del'>-</div><div class='del'>-	ret = adf_cfg_section_add(accel_dev, ADF_GENERAL_SEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	/* Default configuration is crypto only for even devices</div><div class='del'>-	 * and compression for odd devices</div><div class='del'>-	 */</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC,</div><div class='del'>-					  ADF_SERVICES_ENABLED, config,</div><div class='del'>-					  ADF_STR);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	adf_heartbeat_save_cfg_param(accel_dev, ADF_CFG_HB_TIMER_MIN_MS);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];</div><div class='del'>-	int banks = GET_MAX_BANKS(accel_dev);</div><div class='del'>-	int cpus = num_online_cpus();</div><div class='del'>-	unsigned long bank, val;</div><div class='del'>-	int instances;</div><div class='del'>-	int ret;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (adf_hw_dev_has_crypto(accel_dev))</div><div class='del'>-		instances = min(cpus, banks / 2);</div><div class='del'>-	else</div><div class='del'>-		instances = 0;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; instances; i++) {</div><div class='del'>-		val = i;</div><div class='del'>-		bank = i * 2;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;bank, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		bank += 1;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_BANK_NUM, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;bank, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,</div><div class='del'>-			 i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);</div><div class='del'>-		val = 128;</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 512;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 0;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 0;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 1;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 1;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = ADF_COALESCING_DEF_TIME;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	val = i;</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	val = 0;</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-err:</div><div class='del'>-	dev_err(&amp;GET_DEV(accel_dev), "Failed to add configuration for crypto\n");</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int adf_comp_dev_config(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];</div><div class='del'>-	int banks = GET_MAX_BANKS(accel_dev);</div><div class='del'>-	int cpus = num_online_cpus();</div><div class='del'>-	unsigned long val;</div><div class='del'>-	int instances;</div><div class='del'>-	int ret;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (adf_hw_dev_has_compression(accel_dev))</div><div class='del'>-		instances = min(cpus, banks);</div><div class='del'>-	else</div><div class='del'>-		instances = 0;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; instances; i++) {</div><div class='del'>-		val = i;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 512;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_SIZE, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 0;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_TX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = 1;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_RX, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-</div><div class='del'>-		val = ADF_COALESCING_DEF_TIME;</div><div class='del'>-		snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);</div><div class='del'>-		ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",</div><div class='del'>-						  key, &amp;val, ADF_DEC);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	val = i;</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	val = 0;</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-err:</div><div class='del'>-	dev_err(&amp;GET_DEV(accel_dev), "Failed to add configuration for compression\n");</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int adf_no_dev_config(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	unsigned long val;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	val = 0;</div><div class='del'>-	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	return adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='del'>-					  &amp;val, ADF_DEC);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int adf_gen4_dev_config(struct adf_accel_dev *accel_dev)</div><div class='del'>-{</div><div class='del'>-	char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	ret = adf_cfg_section_add(accel_dev, "Accelerator0");</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,</div><div class='del'>-				      ADF_SERVICES_ENABLED, services);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	ret = sysfs_match_string(adf_cfg_services, services);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	switch (ret) {</div><div class='del'>-	case SVC_CY:</div><div class='del'>-	case SVC_CY2:</div><div class='del'>-		ret = adf_crypto_dev_config(accel_dev);</div><div class='del'>-		break;</div><div class='del'>-	case SVC_DC:</div><div class='del'>-	case SVC_DCC:</div><div class='del'>-		ret = adf_comp_dev_config(accel_dev);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		ret = adf_no_dev_config(accel_dev);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err;</div><div class='del'>-</div><div class='del'>-	set_bit(ADF_STATUS_CONFIGURED, &amp;accel_dev-&gt;status);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-</div><div class='del'>-err:</div><div class='del'>-	dev_err(&amp;GET_DEV(accel_dev), "Failed to configure QAT driver\n");</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> {</div><div class='ctx'> 	struct adf_accel_dev *accel_dev;</div><div class='hunk'>@@ -348,7 +81,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	adf_init_hw_data_4xxx(accel_dev-&gt;hw_device, ent-&gt;device);</div><div class='ctx'> </div><div class='ctx'> 	pci_read_config_byte(pdev, PCI_REVISION_ID, &amp;accel_pci_dev-&gt;revid);</div><div class='del'>-	pci_read_config_dword(pdev, ADF_4XXX_FUSECTL4_OFFSET, &amp;hw_data-&gt;fuses);</div><div class='add'>+	pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &amp;hw_data-&gt;fuses);</div><div class='ctx'> </div><div class='ctx'> 	/* Get Accelerators and Accelerators Engines masks */</div><div class='ctx'> 	hw_data-&gt;accel_mask = hw_data-&gt;get_accel_mask(hw_data);</div><div class='hunk'>@@ -381,7 +114,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		goto out_err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = adf_cfg_dev_init(accel_dev);</div><div class='add'>+	ret = adf_gen4_cfg_dev_init(accel_dev);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "Failed to initialize configuration.\n");</div><div class='ctx'> 		goto out_err;</div><div class='hunk'>@@ -396,7 +129,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Find and map all the device's BARS */</div><div class='del'>-	bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) &amp; ADF_4XXX_BAR_MASK;</div><div class='add'>+	bar_mask = pci_select_bars(pdev, IORESOURCE_MEM) &amp; ADF_GEN4_BAR_MASK;</div><div class='ctx'> </div><div class='ctx'> 	ret = pcim_iomap_regions_request_all(pdev, bar_mask, pci_name(pdev));</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/Makefile b/drivers/crypto/intel/qat/qat_common/Makefile<br/>index 779a8aa0b8d2..6908727bff3b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/Makefile</a></div><div class='hunk'>@@ -16,6 +16,7 @@ intel_qat-objs := adf_cfg.o \</div><div class='ctx'> 	adf_sysfs_ras_counters.o \</div><div class='ctx'> 	adf_gen2_hw_data.o \</div><div class='ctx'> 	adf_gen2_config.o \</div><div class='add'>+	adf_gen4_config.o \</div><div class='ctx'> 	adf_gen4_hw_data.o \</div><div class='ctx'> 	adf_gen4_pm.o \</div><div class='ctx'> 	adf_gen2_dc.o \</div><div class='hunk'>@@ -40,9 +41,12 @@ intel_qat-$(CONFIG_DEBUG_FS) += adf_transport_debug.o \</div><div class='ctx'> 				adf_fw_counters.o \</div><div class='ctx'> 				adf_cnv_dbgfs.o \</div><div class='ctx'> 				adf_gen4_pm_debugfs.o \</div><div class='add'>+				adf_gen4_tl.o \</div><div class='ctx'> 				adf_heartbeat.o \</div><div class='ctx'> 				adf_heartbeat_dbgfs.o \</div><div class='ctx'> 				adf_pm_dbgfs.o \</div><div class='add'>+				adf_telemetry.o \</div><div class='add'>+				adf_tl_debugfs.o \</div><div class='ctx'> 				adf_dbgfs.o</div><div class='ctx'> </div><div class='ctx'> intel_qat-$(CONFIG_PCI_IOV) += adf_sriov.o adf_vf_isr.o adf_pfvf_utils.o \</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h<br/>index 4ff5729a3496..a16c7e6edc65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_accel_devices.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_accel_devices.h</a></div><div class='hunk'>@@ -6,11 +6,14 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/ratelimit.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include "adf_cfg_common.h"</div><div class='ctx'> #include "adf_rl.h"</div><div class='add'>+#include "adf_telemetry.h"</div><div class='ctx'> #include "adf_pfvf_msg.h"</div><div class='add'>+#include "icp_qat_hw.h"</div><div class='ctx'> </div><div class='ctx'> #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"</div><div class='ctx'> #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"</div><div class='hunk'>@@ -19,12 +22,15 @@</div><div class='ctx'> #define ADF_C3XXX_DEVICE_NAME "c3xxx"</div><div class='ctx'> #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"</div><div class='ctx'> #define ADF_4XXX_DEVICE_NAME "4xxx"</div><div class='add'>+#define ADF_420XX_DEVICE_NAME "420xx"</div><div class='ctx'> #define ADF_4XXX_PCI_DEVICE_ID 0x4940</div><div class='ctx'> #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941</div><div class='ctx'> #define ADF_401XX_PCI_DEVICE_ID 0x4942</div><div class='ctx'> #define ADF_401XXIOV_PCI_DEVICE_ID 0x4943</div><div class='ctx'> #define ADF_402XX_PCI_DEVICE_ID 0x4944</div><div class='ctx'> #define ADF_402XXIOV_PCI_DEVICE_ID 0x4945</div><div class='add'>+#define ADF_420XX_PCI_DEVICE_ID 0x4946</div><div class='add'>+#define ADF_420XXIOV_PCI_DEVICE_ID 0x4947</div><div class='ctx'> #define ADF_DEVICE_FUSECTL_OFFSET 0x40</div><div class='ctx'> #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C</div><div class='ctx'> #define ADF_DEVICE_FUSECTL_MASK 0x80000000</div><div class='hunk'>@@ -92,6 +98,7 @@ enum ras_errors {</div><div class='ctx'> </div><div class='ctx'> struct adf_error_counters {</div><div class='ctx'> 	atomic_t counter[ADF_RAS_ERRORS];</div><div class='add'>+	bool sysfs_added;</div><div class='ctx'> 	bool enabled;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -240,8 +247,10 @@ struct adf_hw_device_data {</div><div class='ctx'> 	void (*reset_device)(struct adf_accel_dev *accel_dev);</div><div class='ctx'> 	void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);</div><div class='ctx'> 	const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);</div><div class='del'>-	u32 (*uof_get_num_objs)(void);</div><div class='add'>+	u32 (*uof_get_num_objs)(struct adf_accel_dev *accel_dev);</div><div class='ctx'> 	u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);</div><div class='add'>+	int (*get_rp_group)(struct adf_accel_dev *accel_dev, u32 ae_mask);</div><div class='add'>+	u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);</div><div class='ctx'> 	int (*dev_config)(struct adf_accel_dev *accel_dev);</div><div class='ctx'> 	struct adf_pfvf_ops pfvf_ops;</div><div class='ctx'> 	struct adf_hw_csr_ops csr_ops;</div><div class='hunk'>@@ -249,6 +258,7 @@ struct adf_hw_device_data {</div><div class='ctx'> 	struct adf_ras_ops ras_ops;</div><div class='ctx'> 	struct adf_dev_err_mask dev_err_mask;</div><div class='ctx'> 	struct adf_rl_hw_data rl_data;</div><div class='add'>+	struct adf_tl_hw_data tl_data;</div><div class='ctx'> 	const char *fw_name;</div><div class='ctx'> 	const char *fw_mmp_name;</div><div class='ctx'> 	u32 fuses;</div><div class='hunk'>@@ -263,6 +273,7 @@ struct adf_hw_device_data {</div><div class='ctx'> 	u32 admin_ae_mask;</div><div class='ctx'> 	u16 tx_rings_mask;</div><div class='ctx'> 	u16 ring_to_svc_map;</div><div class='add'>+	u32 thd_to_arb_map[ICP_QAT_HW_AE_DELIMITER];</div><div class='ctx'> 	u8 tx_rx_gap;</div><div class='ctx'> 	u8 num_banks;</div><div class='ctx'> 	u16 num_banks_per_vf;</div><div class='hunk'>@@ -271,6 +282,7 @@ struct adf_hw_device_data {</div><div class='ctx'> 	u8 num_logical_accel;</div><div class='ctx'> 	u8 num_engines;</div><div class='ctx'> 	u32 num_hb_ctrs;</div><div class='add'>+	u8 num_rps;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* CSR write macro */</div><div class='hunk'>@@ -303,6 +315,7 @@ struct adf_hw_device_data {</div><div class='ctx'> #define GET_CSR_OPS(accel_dev) (&amp;(accel_dev)-&gt;hw_device-&gt;csr_ops)</div><div class='ctx'> #define GET_PFVF_OPS(accel_dev) (&amp;(accel_dev)-&gt;hw_device-&gt;pfvf_ops)</div><div class='ctx'> #define GET_DC_OPS(accel_dev) (&amp;(accel_dev)-&gt;hw_device-&gt;dc_ops)</div><div class='add'>+#define GET_TL_DATA(accel_dev) GET_HW_DATA(accel_dev)-&gt;tl_data</div><div class='ctx'> #define accel_to_pci_dev(accel_ptr) accel_ptr-&gt;accel_pci_dev.pci_dev</div><div class='ctx'> </div><div class='ctx'> struct adf_admin_comms;</div><div class='hunk'>@@ -351,6 +364,7 @@ struct adf_accel_dev {</div><div class='ctx'> 	struct adf_cfg_device_data *cfg;</div><div class='ctx'> 	struct adf_fw_loader_data *fw_loader;</div><div class='ctx'> 	struct adf_admin_comms *admin;</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='ctx'> 	struct adf_dc_data *dc_data;</div><div class='ctx'> 	struct adf_pm power_management;</div><div class='ctx'> 	struct list_head crypto_list;</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_engine.c b/drivers/crypto/intel/qat/qat_common/adf_accel_engine.c<br/>index 6be064dc64c8..4b5d0350fc2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_accel_engine.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_accel_engine.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_accel_engine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_accel_engine.c</a></div><div class='hunk'>@@ -19,7 +19,7 @@ static int adf_ae_fw_load_images(struct adf_accel_dev *accel_dev, void *fw_addr,</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	loader = loader_data-&gt;fw_loader;</div><div class='del'>-	num_objs = hw_device-&gt;uof_get_num_objs();</div><div class='add'>+	num_objs = hw_device-&gt;uof_get_num_objs(accel_dev);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_objs; i++) {</div><div class='ctx'> 		obj_name = hw_device-&gt;uof_get_name(accel_dev, i);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_admin.c b/drivers/crypto/intel/qat/qat_common/adf_admin.c<br/>index 54b673ec2362..acad526eb741 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_admin.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_admin.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_admin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_admin.c</a></div><div class='hunk'>@@ -498,6 +498,43 @@ int adf_get_cnv_stats(struct adf_accel_dev *accel_dev, u16 ae, u16 *err_cnt,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int adf_send_admin_tl_start(struct adf_accel_dev *accel_dev,</div><div class='add'>+			    dma_addr_t tl_dma_addr, size_t layout_sz, u8 *rp_indexes,</div><div class='add'>+			    struct icp_qat_fw_init_admin_slice_cnt *slice_count)</div><div class='add'>+{</div><div class='add'>+	u32 ae_mask = GET_HW_DATA(accel_dev)-&gt;admin_ae_mask;</div><div class='add'>+	struct icp_qat_fw_init_admin_resp resp = { };</div><div class='add'>+	struct icp_qat_fw_init_admin_req req = { };</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	req.cmd_id = ICP_QAT_FW_TL_START;</div><div class='add'>+	req.init_cfg_ptr = tl_dma_addr;</div><div class='add'>+	req.init_cfg_sz = layout_sz;</div><div class='add'>+</div><div class='add'>+	if (rp_indexes)</div><div class='add'>+		memcpy(&amp;req.rp_indexes, rp_indexes, sizeof(req.rp_indexes));</div><div class='add'>+</div><div class='add'>+	ret = adf_send_admin(accel_dev, &amp;req, &amp;resp, ae_mask);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	memcpy(slice_count, &amp;resp.slices, sizeof(*slice_count));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_send_admin_tl_stop(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);</div><div class='add'>+	struct icp_qat_fw_init_admin_resp resp = { };</div><div class='add'>+	struct icp_qat_fw_init_admin_req req = { };</div><div class='add'>+	u32 ae_mask = hw_data-&gt;admin_ae_mask;</div><div class='add'>+</div><div class='add'>+	req.cmd_id = ICP_QAT_FW_TL_STOP;</div><div class='add'>+</div><div class='add'>+	return adf_send_admin(accel_dev, &amp;req, &amp;resp, ae_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int adf_init_admin_comms(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct adf_admin_comms *admin;</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_admin.h b/drivers/crypto/intel/qat/qat_common/adf_admin.h<br/>index 55cbcbc66c9f..647c8e196752 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_admin.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_admin.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_admin.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_admin.h</a></div><div class='hunk'>@@ -23,5 +23,9 @@ int adf_send_admin_rl_delete(struct adf_accel_dev *accel_dev, u16 node_id,</div><div class='ctx'> int adf_get_fw_timestamp(struct adf_accel_dev *accel_dev, u64 *timestamp);</div><div class='ctx'> int adf_get_pm_info(struct adf_accel_dev *accel_dev, dma_addr_t p_state_addr, size_t buff_size);</div><div class='ctx'> int adf_get_cnv_stats(struct adf_accel_dev *accel_dev, u16 ae, u16 *err_cnt, u16 *latest_err);</div><div class='add'>+int adf_send_admin_tl_start(struct adf_accel_dev *accel_dev,</div><div class='add'>+			    dma_addr_t tl_dma_addr, size_t layout_sz, u8 *rp_indexes,</div><div class='add'>+			    struct icp_qat_fw_init_admin_slice_cnt *slice_count);</div><div class='add'>+int adf_send_admin_tl_stop(struct adf_accel_dev *accel_dev);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h b/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h<br/>index 6e5de1dab97b..89df3888d7ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_cfg_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_common.h</a></div><div class='hunk'>@@ -47,6 +47,7 @@ enum adf_device_type {</div><div class='ctx'> 	DEV_C3XXX,</div><div class='ctx'> 	DEV_C3XXXVF,</div><div class='ctx'> 	DEV_4XXX,</div><div class='add'>+	DEV_420XX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct adf_dev_status_info {</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c<br/>index 8e13fe938959..268052294468 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_services.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.c</a></div><div class='hunk'>@@ -2,6 +2,9 @@</div><div class='ctx'> /* Copyright(c) 2023 Intel Corporation */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/export.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include "adf_cfg.h"</div><div class='ctx'> #include "adf_cfg_services.h"</div><div class='ctx'> #include "adf_cfg_strings.h"</div><div class='ctx'> </div><div class='hunk'>@@ -18,3 +21,27 @@ const char *const adf_cfg_services[] = {</div><div class='ctx'> 	[SVC_SYM_DC] = ADF_CFG_SYM_DC,</div><div class='ctx'> };</div><div class='ctx'> EXPORT_SYMBOL_GPL(adf_cfg_services);</div><div class='add'>+</div><div class='add'>+int adf_get_service_enabled(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,</div><div class='add'>+				      ADF_SERVICES_ENABLED, services);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;GET_DEV(accel_dev),</div><div class='add'>+			ADF_SERVICES_ENABLED " param not found\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = match_string(adf_cfg_services, ARRAY_SIZE(adf_cfg_services),</div><div class='add'>+			   services);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(&amp;GET_DEV(accel_dev),</div><div class='add'>+			"Invalid value of " ADF_SERVICES_ENABLED " param: %s\n",</div><div class='add'>+			services);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_get_service_enabled);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h b/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h<br/>index f78fd697b4be..c6b0328b0f5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_cfg_services.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_cfg_services.h</a></div><div class='hunk'>@@ -5,6 +5,8 @@</div><div class='ctx'> </div><div class='ctx'> #include "adf_cfg_strings.h"</div><div class='ctx'> </div><div class='add'>+struct adf_accel_dev;</div><div class='add'>+</div><div class='ctx'> enum adf_services {</div><div class='ctx'> 	SVC_CY = 0,</div><div class='ctx'> 	SVC_CY2,</div><div class='hunk'>@@ -21,4 +23,6 @@ enum adf_services {</div><div class='ctx'> </div><div class='ctx'> extern const char *const adf_cfg_services[SVC_COUNT];</div><div class='ctx'> </div><div class='add'>+int adf_get_service_enabled(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_dbgfs.c b/drivers/crypto/intel/qat/qat_common/adf_dbgfs.c<br/>index 477efcc81a16..c42f5c25aabd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_dbgfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_dbgfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_dbgfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_dbgfs.c</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> #include "adf_fw_counters.h"</div><div class='ctx'> #include "adf_heartbeat_dbgfs.h"</div><div class='ctx'> #include "adf_pm_dbgfs.h"</div><div class='add'>+#include "adf_tl_debugfs.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * adf_dbgfs_init() - add persistent debugfs entries</div><div class='hunk'>@@ -66,6 +67,7 @@ void adf_dbgfs_add(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 		adf_heartbeat_dbgfs_add(accel_dev);</div><div class='ctx'> 		adf_pm_dbgfs_add(accel_dev);</div><div class='ctx'> 		adf_cnv_dbgfs_add(accel_dev);</div><div class='add'>+		adf_tl_dbgfs_add(accel_dev);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -79,6 +81,7 @@ void adf_dbgfs_rm(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!accel_dev-&gt;is_vf) {</div><div class='add'>+		adf_tl_dbgfs_rm(accel_dev);</div><div class='ctx'> 		adf_cnv_dbgfs_rm(accel_dev);</div><div class='ctx'> 		adf_pm_dbgfs_rm(accel_dev);</div><div class='ctx'> 		adf_heartbeat_dbgfs_rm(accel_dev);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_fw_config.h b/drivers/crypto/intel/qat/qat_common/adf_fw_config.h<br/>new file mode 100644<br/>index 000000000000..4f86696800c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_fw_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_fw_config.h</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#ifndef ADF_FW_CONFIG_H_</div><div class='add'>+#define ADF_FW_CONFIG_H_</div><div class='add'>+</div><div class='add'>+enum adf_fw_objs {</div><div class='add'>+	ADF_FW_SYM_OBJ,</div><div class='add'>+	ADF_FW_ASYM_OBJ,</div><div class='add'>+	ADF_FW_DC_OBJ,</div><div class='add'>+	ADF_FW_ADMIN_OBJ,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct adf_fw_config {</div><div class='add'>+	u32 ae_mask;</div><div class='add'>+	enum adf_fw_objs obj;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_config.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_config.c<br/>new file mode 100644<br/>index 000000000000..fe1f3d727dc5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_config.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_config.c</a></div><div class='hunk'>@@ -0,0 +1,287 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#include "adf_accel_devices.h"</div><div class='add'>+#include "adf_cfg.h"</div><div class='add'>+#include "adf_cfg_services.h"</div><div class='add'>+#include "adf_cfg_strings.h"</div><div class='add'>+#include "adf_common_drv.h"</div><div class='add'>+#include "adf_gen4_config.h"</div><div class='add'>+#include "adf_heartbeat.h"</div><div class='add'>+#include "adf_transport_access_macros.h"</div><div class='add'>+#include "qat_compression.h"</div><div class='add'>+#include "qat_crypto.h"</div><div class='add'>+</div><div class='add'>+static int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];</div><div class='add'>+	int banks = GET_MAX_BANKS(accel_dev);</div><div class='add'>+	int cpus = num_online_cpus();</div><div class='add'>+	unsigned long bank, val;</div><div class='add'>+	int instances;</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (adf_hw_dev_has_crypto(accel_dev))</div><div class='add'>+		instances = min(cpus, banks / 2);</div><div class='add'>+	else</div><div class='add'>+		instances = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; instances; i++) {</div><div class='add'>+		val = i;</div><div class='add'>+		bank = i * 2;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;bank, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		bank += 1;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_BANK_NUM, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;bank, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_ETRMGR_CORE_AFFINITY,</div><div class='add'>+			 i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_SIZE, i);</div><div class='add'>+		val = 128;</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 512;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_SIZE, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 0;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_TX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 0;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_TX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 1;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_RX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 1;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_SYM_RX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = ADF_COALESCING_DEF_TIME;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = i;</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	val = 0;</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+err:</div><div class='add'>+	dev_err(&amp;GET_DEV(accel_dev), "Failed to add configuration for crypto\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adf_comp_dev_config(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];</div><div class='add'>+	int banks = GET_MAX_BANKS(accel_dev);</div><div class='add'>+	int cpus = num_online_cpus();</div><div class='add'>+	unsigned long val;</div><div class='add'>+	int instances;</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (adf_hw_dev_has_compression(accel_dev))</div><div class='add'>+		instances = min(cpus, banks);</div><div class='add'>+	else</div><div class='add'>+		instances = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; instances; i++) {</div><div class='add'>+		val = i;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 512;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_SIZE, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 0;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_TX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = 1;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_RX, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='add'>+		val = ADF_COALESCING_DEF_TIME;</div><div class='add'>+		snprintf(key, sizeof(key), ADF_ETRMGR_COALESCE_TIMER_FORMAT, i);</div><div class='add'>+		ret = adf_cfg_add_key_value_param(accel_dev, "Accelerator0",</div><div class='add'>+						  key, &amp;val, ADF_DEC);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = i;</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	val = 0;</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+err:</div><div class='add'>+	dev_err(&amp;GET_DEV(accel_dev), "Failed to add configuration for compression\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adf_no_dev_config(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	unsigned long val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	val = 0;</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY,</div><div class='add'>+					  &amp;val, ADF_DEC);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * adf_gen4_dev_config() - create dev config required to create instances</div><div class='add'>+ *</div><div class='add'>+ * @accel_dev: Pointer to acceleration device.</div><div class='add'>+ *</div><div class='add'>+ * Function creates device configuration required to create instances</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int adf_gen4_dev_config(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = adf_cfg_section_add(accel_dev, "Accelerator0");</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,</div><div class='add'>+				      ADF_SERVICES_ENABLED, services);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = sysfs_match_string(adf_cfg_services, services);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	switch (ret) {</div><div class='add'>+	case SVC_CY:</div><div class='add'>+	case SVC_CY2:</div><div class='add'>+		ret = adf_crypto_dev_config(accel_dev);</div><div class='add'>+		break;</div><div class='add'>+	case SVC_DC:</div><div class='add'>+	case SVC_DCC:</div><div class='add'>+		ret = adf_comp_dev_config(accel_dev);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = adf_no_dev_config(accel_dev);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	set_bit(ADF_STATUS_CONFIGURED, &amp;accel_dev-&gt;status);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	dev_err(&amp;GET_DEV(accel_dev), "Failed to configure QAT driver\n");</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_dev_config);</div><div class='add'>+</div><div class='add'>+int adf_gen4_cfg_dev_init(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	const char *config;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	config = accel_dev-&gt;accel_id % 2 ? ADF_CFG_DC : ADF_CFG_CY;</div><div class='add'>+</div><div class='add'>+	ret = adf_cfg_section_add(accel_dev, ADF_GENERAL_SEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Default configuration is crypto only for even devices</div><div class='add'>+	 * and compression for odd devices</div><div class='add'>+	 */</div><div class='add'>+	ret = adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC,</div><div class='add'>+					  ADF_SERVICES_ENABLED, config,</div><div class='add'>+					  ADF_STR);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	adf_heartbeat_save_cfg_param(accel_dev, ADF_CFG_HB_TIMER_MIN_MS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_cfg_dev_init);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_config.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_config.h<br/>new file mode 100644<br/>index 000000000000..bb87655f69a8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_config.h</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation */</div><div class='add'>+#ifndef ADF_GEN4_CONFIG_H_</div><div class='add'>+#define ADF_GEN4_CONFIG_H_</div><div class='add'>+</div><div class='add'>+#include "adf_accel_devices.h"</div><div class='add'>+</div><div class='add'>+int adf_gen4_dev_config(struct adf_accel_dev *accel_dev);</div><div class='add'>+int adf_gen4_cfg_dev_init(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c<br/>index 3148a62938fd..9985683056d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c</a></div><div class='hunk'>@@ -2,8 +2,10 @@</div><div class='ctx'> /* Copyright(c) 2020 Intel Corporation */</div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> #include "adf_accel_devices.h"</div><div class='add'>+#include "adf_cfg_services.h"</div><div class='ctx'> #include "adf_common_drv.h"</div><div class='ctx'> #include "adf_gen4_hw_data.h"</div><div class='add'>+#include "adf_gen4_pm.h"</div><div class='ctx'> </div><div class='ctx'> static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)</div><div class='ctx'> {</div><div class='hunk'>@@ -102,6 +104,131 @@ void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);</div><div class='ctx'> </div><div class='add'>+u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return ADF_GEN4_ACCELERATORS_MASK;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_accel_mask);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return ADF_GEN4_MAX_ACCELERATORS;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_num_accels);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	if (!self || !self-&gt;ae_mask)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return hweight32(self-&gt;ae_mask);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_num_aes);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return ADF_GEN4_PMISC_BAR;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_misc_bar_id);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return ADF_GEN4_ETR_BAR;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_etr_bar_id);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return ADF_GEN4_SRAM_BAR;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_sram_bar_id);</div><div class='add'>+</div><div class='add'>+enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	return DEV_SKU_1;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_sku);</div><div class='add'>+</div><div class='add'>+void adf_gen4_get_arb_info(struct arb_info *arb_info)</div><div class='add'>+{</div><div class='add'>+	arb_info-&gt;arb_cfg = ADF_GEN4_ARB_CONFIG;</div><div class='add'>+	arb_info-&gt;arb_offset = ADF_GEN4_ARB_OFFSET;</div><div class='add'>+	arb_info-&gt;wt2sam_offset = ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_arb_info);</div><div class='add'>+</div><div class='add'>+void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info)</div><div class='add'>+{</div><div class='add'>+	admin_csrs_info-&gt;mailbox_offset = ADF_GEN4_MAILBOX_BASE_OFFSET;</div><div class='add'>+	admin_csrs_info-&gt;admin_msg_ur = ADF_GEN4_ADMINMSGUR_OFFSET;</div><div class='add'>+	admin_csrs_info-&gt;admin_msg_lr = ADF_GEN4_ADMINMSGLR_OFFSET;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_admin_info);</div><div class='add'>+</div><div class='add'>+u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * GEN4 uses KPT counter for HB</div><div class='add'>+	 */</div><div class='add'>+	return ADF_GEN4_KPT_COUNTER_FREQ;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_get_heartbeat_clock);</div><div class='add'>+</div><div class='add'>+void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_bar *misc_bar = &amp;GET_BARS(accel_dev)[ADF_GEN4_PMISC_BAR];</div><div class='add'>+	void __iomem *csr = misc_bar-&gt;virt_addr;</div><div class='add'>+</div><div class='add'>+	/* Enable all in errsou3 except VFLR notification on host */</div><div class='add'>+	ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_enable_error_correction);</div><div class='add'>+</div><div class='add'>+void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+</div><div class='add'>+	addr = (&amp;GET_BARS(accel_dev)[ADF_GEN4_PMISC_BAR])-&gt;virt_addr;</div><div class='add'>+</div><div class='add'>+	/* Enable bundle interrupts */</div><div class='add'>+	ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET, 0);</div><div class='add'>+	ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET, 0);</div><div class='add'>+</div><div class='add'>+	/* Enable misc interrupts */</div><div class='add'>+	ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_MASK_OFFSET, 0);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_enable_ints);</div><div class='add'>+</div><div class='add'>+int adf_gen4_init_device(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+	u32 status;</div><div class='add'>+	u32 csr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	addr = (&amp;GET_BARS(accel_dev)[ADF_GEN4_PMISC_BAR])-&gt;virt_addr;</div><div class='add'>+</div><div class='add'>+	/* Temporarily mask PM interrupt */</div><div class='add'>+	csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2);</div><div class='add'>+	csr |= ADF_GEN4_PM_SOU;</div><div class='add'>+	ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr);</div><div class='add'>+</div><div class='add'>+	/* Set DRV_ACTIVE bit to power up the device */</div><div class='add'>+	ADF_CSR_WR(addr, ADF_GEN4_PM_INTERRUPT, ADF_GEN4_PM_DRV_ACTIVE);</div><div class='add'>+</div><div class='add'>+	/* Poll status register to make sure the device is powered up */</div><div class='add'>+	ret = read_poll_timeout(ADF_CSR_RD, status,</div><div class='add'>+				status &amp; ADF_GEN4_PM_INIT_STATE,</div><div class='add'>+				ADF_GEN4_PM_POLL_DELAY_US,</div><div class='add'>+				ADF_GEN4_PM_POLL_TIMEOUT_US, true, addr,</div><div class='add'>+				ADF_GEN4_PM_STATUS);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(&amp;GET_DEV(accel_dev), "Failed to power up the device\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_init_device);</div><div class='add'>+</div><div class='ctx'> static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper,</div><div class='ctx'> 					       u32 *lower)</div><div class='ctx'> {</div><div class='hunk'>@@ -135,6 +262,28 @@ void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * The vector routing table is used to select the MSI-X entry to use for each</div><div class='add'>+ * interrupt source.</div><div class='add'>+ * The first ADF_GEN4_ETR_MAX_BANKS entries correspond to ring interrupts.</div><div class='add'>+ * The final entry corresponds to VF2PF or error interrupts.</div><div class='add'>+ * This vector table could be used to configure one MSI-X entry to be shared</div><div class='add'>+ * between multiple interrupt sources.</div><div class='add'>+ *</div><div class='add'>+ * The default routing is set to have a one to one correspondence between the</div><div class='add'>+ * interrupt source and the MSI-X entry used.</div><div class='add'>+ */</div><div class='add'>+void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	void __iomem *csr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	csr = (&amp;GET_BARS(accel_dev)[ADF_GEN4_PMISC_BAR])-&gt;virt_addr;</div><div class='add'>+	for (i = 0; i &lt;= ADF_GEN4_ETR_MAX_BANKS; i++)</div><div class='add'>+		ADF_CSR_WR(csr, ADF_GEN4_MSIX_RTTABLE_OFFSET(i), i);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_set_msix_default_rttable);</div><div class='add'>+</div><div class='ctx'> int adf_pfvf_comms_disabled(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -192,3 +341,92 @@ int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(adf_gen4_ring_pair_reset);</div><div class='add'>+</div><div class='add'>+static const u32 thrd_to_arb_map_dcc[] = {</div><div class='add'>+	0x00000000, 0x00000000, 0x00000000, 0x00000000,</div><div class='add'>+	0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,</div><div class='add'>+	0x00000000, 0x00000000, 0x00000000, 0x00000000,</div><div class='add'>+	0x00000000, 0x00000000, 0x00000000, 0x00000000,</div><div class='add'>+	0x0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 rp_group_to_arb_mask[] = {</div><div class='add'>+	[RP_GROUP_0] = 0x5,</div><div class='add'>+	[RP_GROUP_1] = 0xA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool is_single_service(int service_id)</div><div class='add'>+{</div><div class='add'>+	switch (service_id) {</div><div class='add'>+	case SVC_DC:</div><div class='add'>+	case SVC_SYM:</div><div class='add'>+	case SVC_ASYM:</div><div class='add'>+		return true;</div><div class='add'>+	case SVC_CY:</div><div class='add'>+	case SVC_CY2:</div><div class='add'>+	case SVC_DCC:</div><div class='add'>+	case SVC_ASYM_DC:</div><div class='add'>+	case SVC_DC_ASYM:</div><div class='add'>+	case SVC_SYM_DC:</div><div class='add'>+	case SVC_DC_SYM:</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);</div><div class='add'>+	u32 *thd2arb_map = hw_data-&gt;thd_to_arb_map;</div><div class='add'>+	unsigned int ae_cnt, worker_obj_cnt, i, j;</div><div class='add'>+	unsigned long ae_mask, thds_mask;</div><div class='add'>+	int srv_id, rp_group;</div><div class='add'>+	u32 thd2arb_map_base;</div><div class='add'>+	u16 arb_mask;</div><div class='add'>+</div><div class='add'>+	if (!hw_data-&gt;get_rp_group || !hw_data-&gt;get_ena_thd_mask ||</div><div class='add'>+	    !hw_data-&gt;get_num_aes || !hw_data-&gt;uof_get_num_objs ||</div><div class='add'>+	    !hw_data-&gt;uof_get_ae_mask)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	srv_id = adf_get_service_enabled(accel_dev);</div><div class='add'>+	if (srv_id &lt; 0)</div><div class='add'>+		return srv_id;</div><div class='add'>+</div><div class='add'>+	ae_cnt = hw_data-&gt;get_num_aes(hw_data);</div><div class='add'>+	worker_obj_cnt = hw_data-&gt;uof_get_num_objs(accel_dev) -</div><div class='add'>+			 ADF_GEN4_ADMIN_ACCELENGINES;</div><div class='add'>+</div><div class='add'>+	if (srv_id == SVC_DCC) {</div><div class='add'>+		memcpy(thd2arb_map, thrd_to_arb_map_dcc,</div><div class='add'>+		       array_size(sizeof(*thd2arb_map), ae_cnt));</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; worker_obj_cnt; i++) {</div><div class='add'>+		ae_mask = hw_data-&gt;uof_get_ae_mask(accel_dev, i);</div><div class='add'>+		rp_group = hw_data-&gt;get_rp_group(accel_dev, ae_mask);</div><div class='add'>+		thds_mask = hw_data-&gt;get_ena_thd_mask(accel_dev, i);</div><div class='add'>+		thd2arb_map_base = 0;</div><div class='add'>+</div><div class='add'>+		if (rp_group &gt;= RP_GROUP_COUNT || rp_group &lt; RP_GROUP_0)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (thds_mask == ADF_GEN4_ENA_THD_MASK_ERROR)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (is_single_service(srv_id))</div><div class='add'>+			arb_mask = rp_group_to_arb_mask[RP_GROUP_0] |</div><div class='add'>+				   rp_group_to_arb_mask[RP_GROUP_1];</div><div class='add'>+		else</div><div class='add'>+			arb_mask = rp_group_to_arb_mask[rp_group];</div><div class='add'>+</div><div class='add'>+		for_each_set_bit(j, &amp;thds_mask, ADF_NUM_THREADS_PER_AE)</div><div class='add'>+			thd2arb_map_base |= arb_mask &lt;&lt; (j * 4);</div><div class='add'>+</div><div class='add'>+		for_each_set_bit(j, &amp;ae_mask, ae_cnt)</div><div class='add'>+			thd2arb_map[j] = thd2arb_map_base;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_init_thd2arb_map);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h<br/>index 1813fe1d5a06..7d8a774cadc8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h</a></div><div class='hunk'>@@ -3,9 +3,57 @@</div><div class='ctx'> #ifndef ADF_GEN4_HW_CSR_DATA_H_</div><div class='ctx'> #define ADF_GEN4_HW_CSR_DATA_H_</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "adf_accel_devices.h"</div><div class='ctx'> #include "adf_cfg_common.h"</div><div class='ctx'> </div><div class='add'>+/* PCIe configuration space */</div><div class='add'>+#define ADF_GEN4_BAR_MASK	(BIT(0) | BIT(2) | BIT(4))</div><div class='add'>+#define ADF_GEN4_SRAM_BAR	0</div><div class='add'>+#define ADF_GEN4_PMISC_BAR	1</div><div class='add'>+#define ADF_GEN4_ETR_BAR	2</div><div class='add'>+</div><div class='add'>+/* Clocks frequency */</div><div class='add'>+#define ADF_GEN4_KPT_COUNTER_FREQ	(100 * HZ_PER_MHZ)</div><div class='add'>+</div><div class='add'>+/* Physical function fuses */</div><div class='add'>+#define ADF_GEN4_FUSECTL0_OFFSET	0x2C8</div><div class='add'>+#define ADF_GEN4_FUSECTL1_OFFSET	0x2CC</div><div class='add'>+#define ADF_GEN4_FUSECTL2_OFFSET	0x2D0</div><div class='add'>+#define ADF_GEN4_FUSECTL3_OFFSET	0x2D4</div><div class='add'>+#define ADF_GEN4_FUSECTL4_OFFSET	0x2D8</div><div class='add'>+#define ADF_GEN4_FUSECTL5_OFFSET	0x2DC</div><div class='add'>+</div><div class='add'>+/* Accelerators */</div><div class='add'>+#define ADF_GEN4_ACCELERATORS_MASK	0x1</div><div class='add'>+#define ADF_GEN4_MAX_ACCELERATORS	1</div><div class='add'>+#define ADF_GEN4_ADMIN_ACCELENGINES	1</div><div class='add'>+</div><div class='add'>+/* MSIX interrupt */</div><div class='add'>+#define ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET	0x41A040</div><div class='add'>+#define ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET	0x41A044</div><div class='add'>+#define ADF_GEN4_SMIAPF_MASK_OFFSET		0x41A084</div><div class='add'>+#define ADF_GEN4_MSIX_RTTABLE_OFFSET(i)		(0x409000 + ((i) * 0x04))</div><div class='add'>+</div><div class='add'>+/* Bank and ring configuration */</div><div class='add'>+#define ADF_GEN4_MAX_RPS		64</div><div class='add'>+#define ADF_GEN4_NUM_RINGS_PER_BANK	2</div><div class='add'>+#define ADF_GEN4_NUM_BANKS_PER_VF	4</div><div class='add'>+#define ADF_GEN4_ETR_MAX_BANKS		64</div><div class='add'>+#define ADF_GEN4_RX_RINGS_OFFSET	1</div><div class='add'>+#define ADF_GEN4_TX_RINGS_MASK		0x1</div><div class='add'>+</div><div class='add'>+/* Arbiter configuration */</div><div class='add'>+#define ADF_GEN4_ARB_CONFIG			(BIT(31) | BIT(6) | BIT(0))</div><div class='add'>+#define ADF_GEN4_ARB_OFFSET			0x0</div><div class='add'>+#define ADF_GEN4_ARB_WRK_2_SER_MAP_OFFSET	0x400</div><div class='add'>+</div><div class='add'>+/* Admin Interface Reg Offset */</div><div class='add'>+#define ADF_GEN4_ADMINMSGUR_OFFSET	0x500574</div><div class='add'>+#define ADF_GEN4_ADMINMSGLR_OFFSET	0x500578</div><div class='add'>+#define ADF_GEN4_MAILBOX_BASE_OFFSET	0x600970</div><div class='add'>+</div><div class='ctx'> /* Transport access */</div><div class='ctx'> #define ADF_BANK_INT_SRC_SEL_MASK	0x44UL</div><div class='ctx'> #define ADF_RING_CSR_RING_CONFIG	0x1000</div><div class='hunk'>@@ -146,7 +194,46 @@ do { \</div><div class='ctx'> #define ADF_GEN4_RL_TOKEN_PCIEIN_BUCKET_OFFSET	0x508800</div><div class='ctx'> #define ADF_GEN4_RL_TOKEN_PCIEOUT_BUCKET_OFFSET	0x508804</div><div class='ctx'> </div><div class='add'>+/* Arbiter threads mask with error value */</div><div class='add'>+#define ADF_GEN4_ENA_THD_MASK_ERROR	GENMASK(ADF_NUM_THREADS_PER_AE, 0)</div><div class='add'>+</div><div class='ctx'> void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='add'>+enum icp_qat_gen4_slice_mask {</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_CIPHER_SLICE = BIT(0),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_AUTH_SLICE = BIT(1),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_PKE_SLICE = BIT(2),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_COMPRESS_SLICE = BIT(3),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_UCS_SLICE = BIT(4),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_EIA3_SLICE = BIT(5),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_SMX_SLICE = BIT(7),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_WCP_WAT_SLICE = BIT(8),</div><div class='add'>+	ICP_ACCEL_GEN4_MASK_ZUC_256_SLICE = BIT(9),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum adf_gen4_rp_groups {</div><div class='add'>+	RP_GROUP_0,</div><div class='add'>+	RP_GROUP_1,</div><div class='add'>+	RP_GROUP_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void adf_gen4_enable_error_correction(struct adf_accel_dev *accel_dev);</div><div class='add'>+void adf_gen4_enable_ints(struct adf_accel_dev *accel_dev);</div><div class='add'>+u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self);</div><div class='add'>+void adf_gen4_get_admin_info(struct admin_info *admin_csrs_info);</div><div class='add'>+void adf_gen4_get_arb_info(struct arb_info *arb_info);</div><div class='add'>+u32 adf_gen4_get_etr_bar_id(struct adf_hw_device_data *self);</div><div class='add'>+u32 adf_gen4_get_heartbeat_clock(struct adf_hw_device_data *self);</div><div class='add'>+u32 adf_gen4_get_misc_bar_id(struct adf_hw_device_data *self);</div><div class='add'>+u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self);</div><div class='add'>+u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self);</div><div class='add'>+enum dev_sku_info adf_gen4_get_sku(struct adf_hw_device_data *self);</div><div class='add'>+u32 adf_gen4_get_sram_bar_id(struct adf_hw_device_data *self);</div><div class='add'>+int adf_gen4_init_device(struct adf_accel_dev *accel_dev);</div><div class='ctx'> void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);</div><div class='ctx'> int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);</div><div class='add'>+void adf_gen4_set_msix_default_rttable(struct adf_accel_dev *accel_dev);</div><div class='add'>+void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);</div><div class='add'>+int adf_gen4_init_thd2arb_map(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c<br/>new file mode 100644<br/>index 000000000000..7fc7a77f6aed<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c</a></div><div class='hunk'>@@ -0,0 +1,153 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#include &lt;linux/export.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+</div><div class='add'>+#include "adf_gen4_tl.h"</div><div class='add'>+#include "adf_telemetry.h"</div><div class='add'>+#include "adf_tl_debugfs.h"</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen4)</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen4)</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_SL_UTIL_COUNTER(_name)	\</div><div class='add'>+	ADF_TL_COUNTER("util_" #_name,		\</div><div class='add'>+			ADF_TL_SIMPLE_COUNT,	\</div><div class='add'>+			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen4))</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_SL_EXEC_COUNTER(_name)	\</div><div class='add'>+	ADF_TL_COUNTER("exec_" #_name,		\</div><div class='add'>+			ADF_TL_SIMPLE_COUNT,	\</div><div class='add'>+			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen4))</div><div class='add'>+</div><div class='add'>+/* Device level counters. */</div><div class='add'>+static const struct adf_tl_dbg_counter dev_counters[] = {</div><div class='add'>+	/* PCIe partial transactions. */</div><div class='add'>+	ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_pci_trans_cnt)),</div><div class='add'>+	/* Max read latency[ns]. */</div><div class='add'>+	ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),</div><div class='add'>+	/* Read latency average[ns]. */</div><div class='add'>+	ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),</div><div class='add'>+	/* Max get to put latency[ns]. */</div><div class='add'>+	ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),</div><div class='add'>+	/* Get to put latency average[ns]. */</div><div class='add'>+	ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),</div><div class='add'>+	/* PCIe write bandwidth[Mbps]. */</div><div class='add'>+	ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_in)),</div><div class='add'>+	/* PCIe read bandwidth[Mbps]. */</div><div class='add'>+	ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_out)),</div><div class='add'>+	/* Page request latency average[ns]. */</div><div class='add'>+	ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),</div><div class='add'>+	/* Page translation latency average[ns]. */</div><div class='add'>+	ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),</div><div class='add'>+			       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),</div><div class='add'>+	/* Maximum uTLB used. */</div><div class='add'>+	ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_max_tlb_used)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Slice utilization counters. */</div><div class='add'>+static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {</div><div class='add'>+	/* Compression slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(cpr),</div><div class='add'>+	/* Translator slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(xlt),</div><div class='add'>+	/* Decompression slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(dcpr),</div><div class='add'>+	/* PKE utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(pke),</div><div class='add'>+	/* Wireless Authentication slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(wat),</div><div class='add'>+	/* Wireless Cipher slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(wcp),</div><div class='add'>+	/* UCS slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(ucs),</div><div class='add'>+	/* Cipher slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(cph),</div><div class='add'>+	/* Authentication slice utilization. */</div><div class='add'>+	ADF_GEN4_TL_SL_UTIL_COUNTER(ath),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Slice execution counters. */</div><div class='add'>+static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {</div><div class='add'>+	/* Compression slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(cpr),</div><div class='add'>+	/* Translator slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(xlt),</div><div class='add'>+	/* Decompression slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(dcpr),</div><div class='add'>+	/* PKE execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(pke),</div><div class='add'>+	/* Wireless Authentication slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(wat),</div><div class='add'>+	/* Wireless Cipher slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(wcp),</div><div class='add'>+	/* UCS slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(ucs),</div><div class='add'>+	/* Cipher slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(cph),</div><div class='add'>+	/* Authentication slice execution count. */</div><div class='add'>+	ADF_GEN4_TL_SL_EXEC_COUNTER(ath),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Ring pair counters. */</div><div class='add'>+static const struct adf_tl_dbg_counter rp_counters[] = {</div><div class='add'>+	/* PCIe partial transactions. */</div><div class='add'>+	ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_pci_trans_cnt)),</div><div class='add'>+	/* Get to put latency average[ns]. */</div><div class='add'>+	ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+			       ADF_GEN4_TL_RP_REG_OFF(reg_tl_gp_lat_acc),</div><div class='add'>+			       ADF_GEN4_TL_RP_REG_OFF(reg_tl_ae_put_cnt)),</div><div class='add'>+	/* PCIe write bandwidth[Mbps]. */</div><div class='add'>+	ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_in)),</div><div class='add'>+	/* PCIe read bandwidth[Mbps]. */</div><div class='add'>+	ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_out)),</div><div class='add'>+	/* Message descriptor DevTLB hit rate. */</div><div class='add'>+	ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)),</div><div class='add'>+	/* Message descriptor DevTLB miss rate. */</div><div class='add'>+	ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)),</div><div class='add'>+	/* Payload DevTLB hit rate. */</div><div class='add'>+	ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)),</div><div class='add'>+	/* Payload DevTLB miss rate. */</div><div class='add'>+	ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,</div><div class='add'>+		       ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)</div><div class='add'>+{</div><div class='add'>+	tl_data-&gt;layout_sz = ADF_GEN4_TL_LAYOUT_SZ;</div><div class='add'>+	tl_data-&gt;slice_reg_sz = ADF_GEN4_TL_SLICE_REG_SZ;</div><div class='add'>+	tl_data-&gt;rp_reg_sz = ADF_GEN4_TL_RP_REG_SZ;</div><div class='add'>+	tl_data-&gt;num_hbuff = ADF_GEN4_TL_NUM_HIST_BUFFS;</div><div class='add'>+	tl_data-&gt;max_rp = ADF_GEN4_TL_MAX_RP_NUM;</div><div class='add'>+	tl_data-&gt;msg_cnt_off = ADF_GEN4_TL_MSG_CNT_OFF;</div><div class='add'>+	tl_data-&gt;cpp_ns_per_cycle = ADF_GEN4_CPP_NS_PER_CYCLE;</div><div class='add'>+	tl_data-&gt;bw_units_to_bytes = ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES;</div><div class='add'>+</div><div class='add'>+	tl_data-&gt;dev_counters = dev_counters;</div><div class='add'>+	tl_data-&gt;num_dev_counters = ARRAY_SIZE(dev_counters);</div><div class='add'>+	tl_data-&gt;sl_util_counters = sl_util_counters;</div><div class='add'>+	tl_data-&gt;sl_exec_counters = sl_exec_counters;</div><div class='add'>+	tl_data-&gt;rp_counters = rp_counters;</div><div class='add'>+	tl_data-&gt;num_rp_counters = ARRAY_SIZE(rp_counters);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(adf_gen4_init_tl_data);</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h<br/>new file mode 100644<br/>index 000000000000..32df4163beb9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_gen4_tl.h</a></div><div class='hunk'>@@ -0,0 +1,158 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#ifndef ADF_GEN4_TL_H</div><div class='add'>+#define ADF_GEN4_TL_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/stddef.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct adf_tl_hw_data;</div><div class='add'>+</div><div class='add'>+/* Computation constants. */</div><div class='add'>+#define ADF_GEN4_CPP_NS_PER_CYCLE		2</div><div class='add'>+#define ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES	64</div><div class='add'>+</div><div class='add'>+/* Maximum aggregation time. Value in milliseconds. */</div><div class='add'>+#define ADF_GEN4_TL_MAX_AGGR_TIME_MS		4000</div><div class='add'>+/* Num of buffers to store historic values. */</div><div class='add'>+#define ADF_GEN4_TL_NUM_HIST_BUFFS \</div><div class='add'>+	(ADF_GEN4_TL_MAX_AGGR_TIME_MS / ADF_TL_DATA_WR_INTERVAL_MS)</div><div class='add'>+</div><div class='add'>+/* Max number of HW resources of one type. */</div><div class='add'>+#define ADF_GEN4_TL_MAX_SLICES_PER_TYPE		24</div><div class='add'>+</div><div class='add'>+/* Max number of simultaneously monitored ring pairs. */</div><div class='add'>+#define ADF_GEN4_TL_MAX_RP_NUM			4</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct adf_gen4_tl_slice_data_regs - HW slice data as populated by FW.</div><div class='add'>+ * @reg_tm_slice_exec_cnt: Slice execution count.</div><div class='add'>+ * @reg_tm_slice_util: Slice utilization.</div><div class='add'>+ */</div><div class='add'>+struct adf_gen4_tl_slice_data_regs {</div><div class='add'>+	__u32 reg_tm_slice_exec_cnt;</div><div class='add'>+	__u32 reg_tm_slice_util;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_SLICE_REG_SZ sizeof(struct adf_gen4_tl_slice_data_regs)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct adf_gen4_tl_device_data_regs - This structure stores device telemetry</div><div class='add'>+ * counter values as are being populated periodically by device.</div><div class='add'>+ * @reg_tl_rd_lat_acc: read latency accumulator</div><div class='add'>+ * @reg_tl_gp_lat_acc: get-put latency accumulator</div><div class='add'>+ * @reg_tl_at_page_req_lat_acc: AT/DevTLB page request latency accumulator</div><div class='add'>+ * @reg_tl_at_trans_lat_acc: DevTLB transaction latency accumulator</div><div class='add'>+ * @reg_tl_re_acc: accumulated ring empty time</div><div class='add'>+ * @reg_tl_pci_trans_cnt: PCIe partial transactions</div><div class='add'>+ * @reg_tl_rd_lat_max: maximum logged read latency</div><div class='add'>+ * @reg_tl_rd_cmpl_cnt: read requests completed count</div><div class='add'>+ * @reg_tl_gp_lat_max: maximum logged get to put latency</div><div class='add'>+ * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings</div><div class='add'>+ * @reg_tl_bw_in: PCIe write bandwidth</div><div class='add'>+ * @reg_tl_bw_out: PCIe read bandwidth</div><div class='add'>+ * @reg_tl_at_page_req_cnt: DevTLB page requests count</div><div class='add'>+ * @reg_tl_at_trans_lat_cnt: DevTLB transaction latency samples count</div><div class='add'>+ * @reg_tl_at_max_tlb_used: maximum uTLB used</div><div class='add'>+ * @reg_tl_re_cnt: ring empty time samples count</div><div class='add'>+ * @reserved: reserved</div><div class='add'>+ * @ath_slices: array of Authentication slices utilization registers</div><div class='add'>+ * @cph_slices: array of Cipher slices utilization registers</div><div class='add'>+ * @cpr_slices: array of Compression slices utilization registers</div><div class='add'>+ * @xlt_slices: array of Translator slices utilization registers</div><div class='add'>+ * @dcpr_slices: array of Decompression slices utilization registers</div><div class='add'>+ * @pke_slices: array of PKE slices utilization registers</div><div class='add'>+ * @ucs_slices: array of UCS slices utilization registers</div><div class='add'>+ * @wat_slices: array of Wireless Authentication slices utilization registers</div><div class='add'>+ * @wcp_slices: array of Wireless Cipher slices utilization registers</div><div class='add'>+ */</div><div class='add'>+struct adf_gen4_tl_device_data_regs {</div><div class='add'>+	__u64 reg_tl_rd_lat_acc;</div><div class='add'>+	__u64 reg_tl_gp_lat_acc;</div><div class='add'>+	__u64 reg_tl_at_page_req_lat_acc;</div><div class='add'>+	__u64 reg_tl_at_trans_lat_acc;</div><div class='add'>+	__u64 reg_tl_re_acc;</div><div class='add'>+	__u32 reg_tl_pci_trans_cnt;</div><div class='add'>+	__u32 reg_tl_rd_lat_max;</div><div class='add'>+	__u32 reg_tl_rd_cmpl_cnt;</div><div class='add'>+	__u32 reg_tl_gp_lat_max;</div><div class='add'>+	__u32 reg_tl_ae_put_cnt;</div><div class='add'>+	__u32 reg_tl_bw_in;</div><div class='add'>+	__u32 reg_tl_bw_out;</div><div class='add'>+	__u32 reg_tl_at_page_req_cnt;</div><div class='add'>+	__u32 reg_tl_at_trans_lat_cnt;</div><div class='add'>+	__u32 reg_tl_at_max_tlb_used;</div><div class='add'>+	__u32 reg_tl_re_cnt;</div><div class='add'>+	__u32 reserved;</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs ath_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs cph_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs cpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs xlt_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs dcpr_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs pke_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs ucs_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs wat_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+	struct adf_gen4_tl_slice_data_regs wcp_slices[ADF_GEN4_TL_MAX_SLICES_PER_TYPE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct adf_gen4_tl_ring_pair_data_regs - This structure stores Ring Pair</div><div class='add'>+ * telemetry counter values as are being populated periodically by device.</div><div class='add'>+ * @reg_tl_gp_lat_acc: get-put latency accumulator</div><div class='add'>+ * @reserved: reserved</div><div class='add'>+ * @reg_tl_pci_trans_cnt: PCIe partial transactions</div><div class='add'>+ * @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings</div><div class='add'>+ * @reg_tl_bw_in: PCIe write bandwidth</div><div class='add'>+ * @reg_tl_bw_out: PCIe read bandwidth</div><div class='add'>+ * @reg_tl_at_glob_devtlb_hit: Message descriptor DevTLB hit rate</div><div class='add'>+ * @reg_tl_at_glob_devtlb_miss: Message descriptor DevTLB miss rate</div><div class='add'>+ * @reg_tl_at_payld_devtlb_hit: Payload DevTLB hit rate</div><div class='add'>+ * @reg_tl_at_payld_devtlb_miss: Payload DevTLB miss rate</div><div class='add'>+ * @reg_tl_re_cnt: ring empty time samples count</div><div class='add'>+ * @reserved1: reserved</div><div class='add'>+ */</div><div class='add'>+struct adf_gen4_tl_ring_pair_data_regs {</div><div class='add'>+	__u64 reg_tl_gp_lat_acc;</div><div class='add'>+	__u64 reserved;</div><div class='add'>+	__u32 reg_tl_pci_trans_cnt;</div><div class='add'>+	__u32 reg_tl_ae_put_cnt;</div><div class='add'>+	__u32 reg_tl_bw_in;</div><div class='add'>+	__u32 reg_tl_bw_out;</div><div class='add'>+	__u32 reg_tl_at_glob_devtlb_hit;</div><div class='add'>+	__u32 reg_tl_at_glob_devtlb_miss;</div><div class='add'>+	__u32 reg_tl_at_payld_devtlb_hit;</div><div class='add'>+	__u32 reg_tl_at_payld_devtlb_miss;</div><div class='add'>+	__u32 reg_tl_re_cnt;</div><div class='add'>+	__u32 reserved1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_RP_REG_SZ sizeof(struct adf_gen4_tl_ring_pair_data_regs)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct adf_gen4_tl_layout - This structure represents entire telemetry</div><div class='add'>+ * counters data: Device + 4 Ring Pairs as are being populated periodically</div><div class='add'>+ * by device.</div><div class='add'>+ * @tl_device_data_regs: structure of device telemetry registers</div><div class='add'>+ * @tl_ring_pairs_data_regs: array of ring pairs telemetry registers</div><div class='add'>+ * @reg_tl_msg_cnt: telemetry messages counter</div><div class='add'>+ * @reserved: reserved</div><div class='add'>+ */</div><div class='add'>+struct adf_gen4_tl_layout {</div><div class='add'>+	struct adf_gen4_tl_device_data_regs tl_device_data_regs;</div><div class='add'>+	struct adf_gen4_tl_ring_pair_data_regs</div><div class='add'>+			tl_ring_pairs_data_regs[ADF_GEN4_TL_MAX_RP_NUM];</div><div class='add'>+	__u32 reg_tl_msg_cnt;</div><div class='add'>+	__u32 reserved;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ADF_GEN4_TL_LAYOUT_SZ	sizeof(struct adf_gen4_tl_layout)</div><div class='add'>+#define ADF_GEN4_TL_MSG_CNT_OFF	offsetof(struct adf_gen4_tl_layout, reg_tl_msg_cnt)</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DEBUG_FS</div><div class='add'>+void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data);</div><div class='add'>+#else</div><div class='add'>+static inline void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_DEBUG_FS */</div><div class='add'>+#endif /* ADF_GEN4_TL_H */</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_init.c b/drivers/crypto/intel/qat/qat_common/adf_init.c<br/>index 81c39f3d07e1..f43ae9111553 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_init.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include "adf_heartbeat.h"</div><div class='ctx'> #include "adf_rl.h"</div><div class='ctx'> #include "adf_sysfs_ras_counters.h"</div><div class='add'>+#include "adf_telemetry.h"</div><div class='ctx'> </div><div class='ctx'> static LIST_HEAD(service_table);</div><div class='ctx'> static DEFINE_MUTEX(service_lock);</div><div class='hunk'>@@ -142,6 +143,10 @@ static int adf_dev_init(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	ret = adf_tl_init(accel_dev);</div><div class='add'>+	if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Subservice initialisation is divided into two stages: init and start.</div><div class='ctx'> 	 * This is to facilitate any ordering dependencies between services</div><div class='hunk'>@@ -220,6 +225,10 @@ static int adf_dev_start(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	ret = adf_tl_start(accel_dev);</div><div class='add'>+	if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry(service, &amp;service_table, list) {</div><div class='ctx'> 		if (service-&gt;event_hld(accel_dev, ADF_EVENT_START)) {</div><div class='ctx'> 			dev_err(&amp;GET_DEV(accel_dev),</div><div class='hunk'>@@ -279,6 +288,7 @@ static void adf_dev_stop(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	    !test_bit(ADF_STATUS_STARTING, &amp;accel_dev-&gt;status))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	adf_tl_stop(accel_dev);</div><div class='ctx'> 	adf_rl_stop(accel_dev);</div><div class='ctx'> 	adf_dbgfs_rm(accel_dev);</div><div class='ctx'> 	adf_sysfs_stop_ras(accel_dev);</div><div class='hunk'>@@ -374,6 +384,8 @@ static void adf_dev_shutdown(struct adf_accel_dev *accel_dev)</div><div class='ctx'> </div><div class='ctx'> 	adf_heartbeat_shutdown(accel_dev);</div><div class='ctx'> </div><div class='add'>+	adf_tl_shutdown(accel_dev);</div><div class='add'>+</div><div class='ctx'> 	hw_data-&gt;disable_iov(accel_dev);</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(ADF_STATUS_IRQ_ALLOCATED, &amp;accel_dev-&gt;status)) {</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.c b/drivers/crypto/intel/qat/qat_common/adf_rl.c<br/>index 86e3e2152b1b..de1b214dba1f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_rl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_rl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_rl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_rl.c</a></div><div class='hunk'>@@ -812,17 +812,16 @@ static int add_update_sla(struct adf_accel_dev *accel_dev,</div><div class='ctx'> 	if (!sla_in) {</div><div class='ctx'> 		dev_warn(&amp;GET_DEV(accel_dev),</div><div class='ctx'> 			 "SLA input data pointer is missing\n");</div><div class='del'>-		ret = -EFAULT;</div><div class='del'>-		goto ret_err;</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;rl_data-&gt;rl_lock);</div><div class='add'>+</div><div class='ctx'> 	/* Input validation */</div><div class='ctx'> 	ret = validate_user_input(accel_dev, sla_in, is_update);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto ret_err;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;rl_data-&gt;rl_lock);</div><div class='del'>-</div><div class='ctx'> 	if (is_update) {</div><div class='ctx'> 		ret = validate_sla_id(accel_dev, sla_in-&gt;sla_id);</div><div class='ctx'> 		if (ret)</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_rl.h b/drivers/crypto/intel/qat/qat_common/adf_rl.h<br/>index eb5a330f8543..269c6656fb90 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_rl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_rl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_rl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_rl.h</a></div><div class='hunk'>@@ -79,6 +79,7 @@ struct adf_rl_interface_data {</div><div class='ctx'> 	struct adf_rl_sla_input_data input;</div><div class='ctx'> 	enum adf_base_services cap_rem_srv;</div><div class='ctx'> 	struct rw_semaphore lock;</div><div class='add'>+	bool sysfs_added;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct adf_rl_hw_data {</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs.c<br/>index ddffc98119c6..d450dad32c9e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs.c</a></div><div class='hunk'>@@ -215,6 +215,9 @@ static ssize_t rp2srv_show(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 	enum adf_cfg_service_type svc;</div><div class='ctx'> </div><div class='ctx'> 	accel_dev = adf_devmgr_pci_to_accel_dev(to_pci_dev(dev));</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	hw_data = GET_HW_DATA(accel_dev);</div><div class='ctx'> </div><div class='ctx'> 	if (accel_dev-&gt;sysfs.ring_num == UNSET_RING_NUM)</div><div class='hunk'>@@ -242,7 +245,8 @@ static ssize_t rp2srv_store(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 			    const char *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct adf_accel_dev *accel_dev;</div><div class='del'>-	int ring, num_rings, ret;</div><div class='add'>+	int num_rings, ret;</div><div class='add'>+	unsigned int ring;</div><div class='ctx'> </div><div class='ctx'> 	accel_dev = adf_devmgr_pci_to_accel_dev(to_pci_dev(dev));</div><div class='ctx'> 	if (!accel_dev)</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c<br/>index cffe2d722995..e97c67c87b3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs_ras_counters.c</a></div><div class='hunk'>@@ -99,6 +99,8 @@ void adf_sysfs_start_ras(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	if (device_add_group(&amp;GET_DEV(accel_dev), &amp;qat_ras_group))</div><div class='ctx'> 		dev_err(&amp;GET_DEV(accel_dev),</div><div class='ctx'> 			"Failed to create qat_ras attribute group.\n");</div><div class='add'>+</div><div class='add'>+	accel_dev-&gt;ras_errors.sysfs_added = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void adf_sysfs_stop_ras(struct adf_accel_dev *accel_dev)</div><div class='hunk'>@@ -106,7 +108,10 @@ void adf_sysfs_stop_ras(struct adf_accel_dev *accel_dev)</div><div class='ctx'> 	if (!accel_dev-&gt;ras_errors.enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	device_remove_group(&amp;GET_DEV(accel_dev), &amp;qat_ras_group);</div><div class='add'>+	if (accel_dev-&gt;ras_errors.sysfs_added) {</div><div class='add'>+		device_remove_group(&amp;GET_DEV(accel_dev), &amp;qat_ras_group);</div><div class='add'>+		accel_dev-&gt;ras_errors.sysfs_added = false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ADF_RAS_ERR_CTR_CLEAR(accel_dev-&gt;ras_errors);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c b/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c<br/>index abf9c52474ec..bedb514d4e30 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c</a></div><div class='hunk'>@@ -441,11 +441,19 @@ int adf_sysfs_rl_add(struct adf_accel_dev *accel_dev)</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;cap_rem_srv = ADF_SVC_NONE;</div><div class='ctx'> 	data-&gt;input.srv = ADF_SVC_NONE;</div><div class='add'>+	data-&gt;sysfs_added = true;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void adf_sysfs_rl_rm(struct adf_accel_dev *accel_dev)</div><div class='ctx'> {</div><div class='add'>+	struct adf_rl_interface_data *data;</div><div class='add'>+</div><div class='add'>+	data = &amp;GET_RL_STRUCT(accel_dev);</div><div class='add'>+	if (!data-&gt;sysfs_added)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	device_remove_group(&amp;GET_DEV(accel_dev), &amp;qat_rl_group);</div><div class='add'>+	data-&gt;sysfs_added = false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_telemetry.c b/drivers/crypto/intel/qat/qat_common/adf_telemetry.c<br/>new file mode 100644<br/>index 000000000000..2ff714d11bd2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_telemetry.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_telemetry.c</a></div><div class='hunk'>@@ -0,0 +1,288 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#define dev_fmt(fmt) "Telemetry: " fmt</div><div class='add'>+</div><div class='add'>+#include &lt;asm/errno.h&gt;</div><div class='add'>+#include &lt;linux/atomic.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/dev_printk.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/jiffies.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "adf_admin.h"</div><div class='add'>+#include "adf_accel_devices.h"</div><div class='add'>+#include "adf_common_drv.h"</div><div class='add'>+#include "adf_telemetry.h"</div><div class='add'>+</div><div class='add'>+#define TL_IS_ZERO(input)	((input) == 0)</div><div class='add'>+</div><div class='add'>+static bool is_tl_supported(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	u16 fw_caps =  GET_HW_DATA(accel_dev)-&gt;fw_capabilities;</div><div class='add'>+</div><div class='add'>+	return fw_caps &amp; TL_CAPABILITY_BIT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int validate_tl_data(struct adf_tl_hw_data *tl_data)</div><div class='add'>+{</div><div class='add'>+	if (!tl_data-&gt;dev_counters ||</div><div class='add'>+	    TL_IS_ZERO(tl_data-&gt;num_dev_counters) ||</div><div class='add'>+	    !tl_data-&gt;sl_util_counters ||</div><div class='add'>+	    !tl_data-&gt;sl_exec_counters ||</div><div class='add'>+	    !tl_data-&gt;rp_counters ||</div><div class='add'>+	    TL_IS_ZERO(tl_data-&gt;num_rp_counters))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adf_tl_alloc_mem(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	size_t regs_sz = tl_data-&gt;layout_sz;</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='add'>+	int node = dev_to_node(dev);</div><div class='add'>+	void *tl_data_regs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	telemetry = kzalloc_node(sizeof(*telemetry), GFP_KERNEL, node);</div><div class='add'>+	if (!telemetry)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	telemetry-&gt;rp_num_indexes = kmalloc_array(tl_data-&gt;max_rp,</div><div class='add'>+						  sizeof(*telemetry-&gt;rp_num_indexes),</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+	if (!telemetry-&gt;rp_num_indexes)</div><div class='add'>+		goto err_free_tl;</div><div class='add'>+</div><div class='add'>+	telemetry-&gt;regs_hist_buff = kmalloc_array(tl_data-&gt;num_hbuff,</div><div class='add'>+						  sizeof(*telemetry-&gt;regs_hist_buff),</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+	if (!telemetry-&gt;regs_hist_buff)</div><div class='add'>+		goto err_free_rp_indexes;</div><div class='add'>+</div><div class='add'>+	telemetry-&gt;regs_data = dma_alloc_coherent(dev, regs_sz,</div><div class='add'>+						  &amp;telemetry-&gt;regs_data_p,</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+	if (!telemetry-&gt;regs_data)</div><div class='add'>+		goto err_free_regs_hist_buff;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; tl_data-&gt;num_hbuff; i++) {</div><div class='add'>+		tl_data_regs = kzalloc_node(regs_sz, GFP_KERNEL, node);</div><div class='add'>+		if (!tl_data_regs)</div><div class='add'>+			goto err_free_dma;</div><div class='add'>+</div><div class='add'>+		telemetry-&gt;regs_hist_buff[i] = tl_data_regs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	accel_dev-&gt;telemetry = telemetry;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_free_dma:</div><div class='add'>+	dma_free_coherent(dev, regs_sz, telemetry-&gt;regs_data,</div><div class='add'>+			  telemetry-&gt;regs_data_p);</div><div class='add'>+</div><div class='add'>+	while (i--)</div><div class='add'>+		kfree(telemetry-&gt;regs_hist_buff[i]);</div><div class='add'>+</div><div class='add'>+err_free_regs_hist_buff:</div><div class='add'>+	kfree(telemetry-&gt;regs_hist_buff);</div><div class='add'>+err_free_rp_indexes:</div><div class='add'>+	kfree(telemetry-&gt;rp_num_indexes);</div><div class='add'>+err_free_tl:</div><div class='add'>+	kfree(telemetry);</div><div class='add'>+</div><div class='add'>+	return -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void adf_tl_free_mem(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	size_t regs_sz = tl_data-&gt;layout_sz;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; tl_data-&gt;num_hbuff; i++)</div><div class='add'>+		kfree(telemetry-&gt;regs_hist_buff[i]);</div><div class='add'>+</div><div class='add'>+	dma_free_coherent(dev, regs_sz, telemetry-&gt;regs_data,</div><div class='add'>+			  telemetry-&gt;regs_data_p);</div><div class='add'>+</div><div class='add'>+	kfree(telemetry-&gt;regs_hist_buff);</div><div class='add'>+	kfree(telemetry-&gt;rp_num_indexes);</div><div class='add'>+	kfree(telemetry);</div><div class='add'>+	accel_dev-&gt;telemetry = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long get_next_timeout(void)</div><div class='add'>+{</div><div class='add'>+	return msecs_to_jiffies(ADF_TL_TIMER_INT_MS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void snapshot_regs(struct adf_telemetry *telemetry, size_t size)</div><div class='add'>+{</div><div class='add'>+	void *dst = telemetry-&gt;regs_hist_buff[telemetry-&gt;hb_num];</div><div class='add'>+	void *src = telemetry-&gt;regs_data;</div><div class='add'>+</div><div class='add'>+	memcpy(dst, src, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tl_work_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct delayed_work *delayed_work;</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='add'>+	struct adf_tl_hw_data *tl_data;</div><div class='add'>+	u32 msg_cnt, old_msg_cnt;</div><div class='add'>+	size_t layout_sz;</div><div class='add'>+	u32 *regs_data;</div><div class='add'>+	size_t id;</div><div class='add'>+</div><div class='add'>+	delayed_work = to_delayed_work(work);</div><div class='add'>+	telemetry = container_of(delayed_work, struct adf_telemetry, work_ctx);</div><div class='add'>+	tl_data = &amp;GET_TL_DATA(telemetry-&gt;accel_dev);</div><div class='add'>+	regs_data = telemetry-&gt;regs_data;</div><div class='add'>+</div><div class='add'>+	id = tl_data-&gt;msg_cnt_off / sizeof(*regs_data);</div><div class='add'>+	layout_sz = tl_data-&gt;layout_sz;</div><div class='add'>+</div><div class='add'>+	if (!atomic_read(&amp;telemetry-&gt;state)) {</div><div class='add'>+		cancel_delayed_work_sync(&amp;telemetry-&gt;work_ctx);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	msg_cnt = regs_data[id];</div><div class='add'>+	old_msg_cnt = msg_cnt;</div><div class='add'>+	if (msg_cnt == telemetry-&gt;msg_cnt)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+	snapshot_regs(telemetry, layout_sz);</div><div class='add'>+</div><div class='add'>+	/* Check if data changed while updating it */</div><div class='add'>+	msg_cnt = regs_data[id];</div><div class='add'>+	if (old_msg_cnt != msg_cnt)</div><div class='add'>+		snapshot_regs(telemetry, layout_sz);</div><div class='add'>+</div><div class='add'>+	telemetry-&gt;msg_cnt = msg_cnt;</div><div class='add'>+	telemetry-&gt;hb_num++;</div><div class='add'>+	telemetry-&gt;hb_num %= telemetry-&gt;hbuffs;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	adf_misc_wq_queue_delayed_work(&amp;telemetry-&gt;work_ctx, get_next_timeout());</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_tl_halt(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;telemetry-&gt;work_ctx);</div><div class='add'>+	atomic_set(&amp;telemetry-&gt;state, 0);</div><div class='add'>+</div><div class='add'>+	ret = adf_send_admin_tl_stop(accel_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(dev, "failed to stop telemetry\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_tl_run(struct adf_accel_dev *accel_dev, int state)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	size_t layout_sz = tl_data-&gt;layout_sz;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = adf_send_admin_tl_start(accel_dev, telemetry-&gt;regs_data_p,</div><div class='add'>+				      layout_sz, telemetry-&gt;rp_num_indexes,</div><div class='add'>+				      &amp;telemetry-&gt;slice_cnt);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to start telemetry\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	telemetry-&gt;hbuffs = state;</div><div class='add'>+	atomic_set(&amp;telemetry-&gt;state, state);</div><div class='add'>+</div><div class='add'>+	adf_misc_wq_queue_delayed_work(&amp;telemetry-&gt;work_ctx, get_next_timeout());</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_tl_init(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	u8 max_rp = GET_TL_DATA(accel_dev).max_rp;</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = validate_tl_data(tl_data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = adf_tl_alloc_mem(accel_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to initialize: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	telemetry-&gt;accel_dev = accel_dev;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;telemetry-&gt;wr_lock);</div><div class='add'>+	mutex_init(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;telemetry-&gt;work_ctx, tl_work_handler);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; max_rp; i++)</div><div class='add'>+		telemetry-&gt;rp_num_indexes[i] = ADF_TL_RP_REGS_DISABLED;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int adf_tl_start(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+</div><div class='add'>+	if (!accel_dev-&gt;telemetry)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (!is_tl_supported(accel_dev)) {</div><div class='add'>+		dev_info(dev, "feature not supported by FW\n");</div><div class='add'>+		adf_tl_free_mem(accel_dev);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adf_tl_stop(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	if (!accel_dev-&gt;telemetry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (atomic_read(&amp;accel_dev-&gt;telemetry-&gt;state))</div><div class='add'>+		adf_tl_halt(accel_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adf_tl_shutdown(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	if (!accel_dev-&gt;telemetry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	adf_tl_free_mem(accel_dev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_telemetry.h b/drivers/crypto/intel/qat/qat_common/adf_telemetry.h<br/>new file mode 100644<br/>index 000000000000..9be81cd3b886<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_telemetry.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_telemetry.h</a></div><div class='hunk'>@@ -0,0 +1,99 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#ifndef ADF_TELEMETRY_H</div><div class='add'>+#define ADF_TELEMETRY_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "icp_qat_fw_init_admin.h"</div><div class='add'>+</div><div class='add'>+struct adf_accel_dev;</div><div class='add'>+struct adf_tl_dbg_counter;</div><div class='add'>+struct dentry;</div><div class='add'>+</div><div class='add'>+#define ADF_TL_SL_CNT_COUNT		\</div><div class='add'>+	(sizeof(struct icp_qat_fw_init_admin_slice_cnt) / sizeof(__u8))</div><div class='add'>+</div><div class='add'>+#define TL_CAPABILITY_BIT		BIT(1)</div><div class='add'>+/* Interval within device writes data to DMA region. Value in milliseconds. */</div><div class='add'>+#define ADF_TL_DATA_WR_INTERVAL_MS	1000</div><div class='add'>+/* Interval within timer interrupt should be handled. Value in milliseconds. */</div><div class='add'>+#define ADF_TL_TIMER_INT_MS		(ADF_TL_DATA_WR_INTERVAL_MS / 2)</div><div class='add'>+</div><div class='add'>+#define ADF_TL_RP_REGS_DISABLED		(0xff)</div><div class='add'>+</div><div class='add'>+struct adf_tl_hw_data {</div><div class='add'>+	size_t layout_sz;</div><div class='add'>+	size_t slice_reg_sz;</div><div class='add'>+	size_t rp_reg_sz;</div><div class='add'>+	size_t msg_cnt_off;</div><div class='add'>+	const struct adf_tl_dbg_counter *dev_counters;</div><div class='add'>+	const struct adf_tl_dbg_counter *sl_util_counters;</div><div class='add'>+	const struct adf_tl_dbg_counter *sl_exec_counters;</div><div class='add'>+	const struct adf_tl_dbg_counter *rp_counters;</div><div class='add'>+	u8 num_hbuff;</div><div class='add'>+	u8 cpp_ns_per_cycle;</div><div class='add'>+	u8 bw_units_to_bytes;</div><div class='add'>+	u8 num_dev_counters;</div><div class='add'>+	u8 num_rp_counters;</div><div class='add'>+	u8 max_rp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct adf_telemetry {</div><div class='add'>+	struct adf_accel_dev *accel_dev;</div><div class='add'>+	atomic_t state;</div><div class='add'>+	u32 hbuffs;</div><div class='add'>+	int hb_num;</div><div class='add'>+	u32 msg_cnt;</div><div class='add'>+	dma_addr_t regs_data_p; /* bus address for DMA mapping */</div><div class='add'>+	void *regs_data; /* virtual address for DMA mapping */</div><div class='add'>+	/**</div><div class='add'>+	 * @regs_hist_buff: array of pointers to copies of the last @hbuffs</div><div class='add'>+	 * values of @regs_data</div><div class='add'>+	 */</div><div class='add'>+	void **regs_hist_buff;</div><div class='add'>+	struct dentry *dbg_dir;</div><div class='add'>+	u8 *rp_num_indexes;</div><div class='add'>+	/**</div><div class='add'>+	 * @regs_hist_lock: protects from race conditions between write and read</div><div class='add'>+	 * to the copies referenced by @regs_hist_buff</div><div class='add'>+	 */</div><div class='add'>+	struct mutex regs_hist_lock;</div><div class='add'>+	/**</div><div class='add'>+	 * @wr_lock: protects from concurrent writes to debugfs telemetry files</div><div class='add'>+	 */</div><div class='add'>+	struct mutex wr_lock;</div><div class='add'>+	struct delayed_work work_ctx;</div><div class='add'>+	struct icp_qat_fw_init_admin_slice_cnt slice_cnt;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DEBUG_FS</div><div class='add'>+int adf_tl_init(struct adf_accel_dev *accel_dev);</div><div class='add'>+int adf_tl_start(struct adf_accel_dev *accel_dev);</div><div class='add'>+void adf_tl_stop(struct adf_accel_dev *accel_dev);</div><div class='add'>+void adf_tl_shutdown(struct adf_accel_dev *accel_dev);</div><div class='add'>+int adf_tl_run(struct adf_accel_dev *accel_dev, int state);</div><div class='add'>+int adf_tl_halt(struct adf_accel_dev *accel_dev);</div><div class='add'>+#else</div><div class='add'>+static inline int adf_tl_init(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int adf_tl_start(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void adf_tl_stop(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void adf_tl_shutdown(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_DEBUG_FS */</div><div class='add'>+#endif /* ADF_TELEMETRY_H */</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c b/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c<br/>new file mode 100644<br/>index 000000000000..c8241f5a0a26<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,710 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#define dev_fmt(fmt) "Telemetry debugfs: " fmt</div><div class='add'>+</div><div class='add'>+#include &lt;linux/atomic.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/dev_printk.h&gt;</div><div class='add'>+#include &lt;linux/dcache.h&gt;</div><div class='add'>+#include &lt;linux/file.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/math64.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/seq_file.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include "adf_accel_devices.h"</div><div class='add'>+#include "adf_cfg_strings.h"</div><div class='add'>+#include "adf_telemetry.h"</div><div class='add'>+#include "adf_tl_debugfs.h"</div><div class='add'>+</div><div class='add'>+#define TL_VALUE_MIN_PADDING	20</div><div class='add'>+#define TL_KEY_MIN_PADDING	23</div><div class='add'>+#define TL_RP_SRV_UNKNOWN	"Unknown"</div><div class='add'>+</div><div class='add'>+static int tl_collect_values_u32(struct adf_telemetry *telemetry,</div><div class='add'>+				 size_t counter_offset, u64 *arr)</div><div class='add'>+{</div><div class='add'>+	unsigned int samples, hb_idx, i;</div><div class='add'>+	u32 *regs_hist_buff;</div><div class='add'>+	u32 counter_val;</div><div class='add'>+</div><div class='add'>+	samples = min(telemetry-&gt;msg_cnt, telemetry-&gt;hbuffs);</div><div class='add'>+	hb_idx = telemetry-&gt;hb_num + telemetry-&gt;hbuffs - samples;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; samples; i++) {</div><div class='add'>+		regs_hist_buff = telemetry-&gt;regs_hist_buff[hb_idx % telemetry-&gt;hbuffs];</div><div class='add'>+		counter_val = regs_hist_buff[counter_offset / sizeof(counter_val)];</div><div class='add'>+		arr[i] = counter_val;</div><div class='add'>+		hb_idx++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+	return samples;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_collect_values_u64(struct adf_telemetry *telemetry,</div><div class='add'>+				 size_t counter_offset, u64 *arr)</div><div class='add'>+{</div><div class='add'>+	unsigned int samples, hb_idx, i;</div><div class='add'>+	u64 *regs_hist_buff;</div><div class='add'>+	u64 counter_val;</div><div class='add'>+</div><div class='add'>+	samples = min(telemetry-&gt;msg_cnt, telemetry-&gt;hbuffs);</div><div class='add'>+	hb_idx = telemetry-&gt;hb_num + telemetry-&gt;hbuffs - samples;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; samples; i++) {</div><div class='add'>+		regs_hist_buff = telemetry-&gt;regs_hist_buff[hb_idx % telemetry-&gt;hbuffs];</div><div class='add'>+		counter_val = regs_hist_buff[counter_offset / sizeof(counter_val)];</div><div class='add'>+		arr[i] = counter_val;</div><div class='add'>+		hb_idx++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;telemetry-&gt;regs_hist_lock);</div><div class='add'>+</div><div class='add'>+	return samples;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * avg_array() - Return average of values within an array.</div><div class='add'>+ * @array: Array of values.</div><div class='add'>+ * @len: Number of elements.</div><div class='add'>+ *</div><div class='add'>+ * This algorithm computes average of an array without running into overflow.</div><div class='add'>+ *</div><div class='add'>+ * Return: average of values.</div><div class='add'>+ */</div><div class='add'>+#define avg_array(array, len) (				\</div><div class='add'>+{							\</div><div class='add'>+	typeof(&amp;(array)[0]) _array = (array);		\</div><div class='add'>+	__unqual_scalar_typeof(_array[0]) _x = 0;	\</div><div class='add'>+	__unqual_scalar_typeof(_array[0]) _y = 0;	\</div><div class='add'>+	__unqual_scalar_typeof(_array[0]) _a, _b;	\</div><div class='add'>+	typeof(len) _len = (len);			\</div><div class='add'>+	size_t _i;					\</div><div class='add'>+							\</div><div class='add'>+	for (_i = 0; _i &lt; _len; _i++) {			\</div><div class='add'>+		_a = _array[_i];			\</div><div class='add'>+		_b = do_div(_a, _len);			\</div><div class='add'>+		_x += _a;				\</div><div class='add'>+		if (_y &gt;= _len - _b) {			\</div><div class='add'>+			_x++;				\</div><div class='add'>+			_y -= _len - _b;		\</div><div class='add'>+		} else {				\</div><div class='add'>+			_y += _b;			\</div><div class='add'>+		}					\</div><div class='add'>+	}						\</div><div class='add'>+	do_div(_y, _len);				\</div><div class='add'>+	(_x + _y);					\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+/* Calculation function for simple counter. */</div><div class='add'>+static int tl_calc_count(struct adf_telemetry *telemetry,</div><div class='add'>+			 const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+			 struct adf_tl_dbg_aggr_values *vals)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(telemetry-&gt;accel_dev);</div><div class='add'>+	u64 *hist_vals;</div><div class='add'>+	int sample_cnt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	hist_vals = kmalloc_array(tl_data-&gt;num_hbuff, sizeof(*hist_vals),</div><div class='add'>+				  GFP_KERNEL);</div><div class='add'>+	if (!hist_vals)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	memset(vals, 0, sizeof(*vals));</div><div class='add'>+	sample_cnt = tl_collect_values_u32(telemetry, ctr-&gt;offset1, hist_vals);</div><div class='add'>+	if (!sample_cnt)</div><div class='add'>+		goto out_free_hist_vals;</div><div class='add'>+</div><div class='add'>+	vals-&gt;curr = hist_vals[sample_cnt - 1];</div><div class='add'>+	vals-&gt;min = min_array(hist_vals, sample_cnt);</div><div class='add'>+	vals-&gt;max = max_array(hist_vals, sample_cnt);</div><div class='add'>+	vals-&gt;avg = avg_array(hist_vals, sample_cnt);</div><div class='add'>+</div><div class='add'>+out_free_hist_vals:</div><div class='add'>+	kfree(hist_vals);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Convert CPP bus cycles to ns. */</div><div class='add'>+static int tl_cycles_to_ns(struct adf_telemetry *telemetry,</div><div class='add'>+			   const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+			   struct adf_tl_dbg_aggr_values *vals)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(telemetry-&gt;accel_dev);</div><div class='add'>+	u8 cpp_ns_per_cycle = tl_data-&gt;cpp_ns_per_cycle;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = tl_calc_count(telemetry, ctr, vals);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	vals-&gt;curr *= cpp_ns_per_cycle;</div><div class='add'>+	vals-&gt;min *= cpp_ns_per_cycle;</div><div class='add'>+	vals-&gt;max *= cpp_ns_per_cycle;</div><div class='add'>+	vals-&gt;avg *= cpp_ns_per_cycle;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Compute latency cumulative average with division of accumulated value</div><div class='add'>+ * by sample count. Returned value is in ns.</div><div class='add'>+ */</div><div class='add'>+static int tl_lat_acc_avg(struct adf_telemetry *telemetry,</div><div class='add'>+			  const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+			  struct adf_tl_dbg_aggr_values *vals)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(telemetry-&gt;accel_dev);</div><div class='add'>+	u8 cpp_ns_per_cycle = tl_data-&gt;cpp_ns_per_cycle;</div><div class='add'>+	u8 num_hbuff = tl_data-&gt;num_hbuff;</div><div class='add'>+	int sample_cnt, i;</div><div class='add'>+	u64 *hist_vals;</div><div class='add'>+	u64 *hist_cnt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	hist_vals = kmalloc_array(num_hbuff, sizeof(*hist_vals), GFP_KERNEL);</div><div class='add'>+	if (!hist_vals)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	hist_cnt = kmalloc_array(num_hbuff, sizeof(*hist_cnt), GFP_KERNEL);</div><div class='add'>+	if (!hist_cnt) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto out_free_hist_vals;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(vals, 0, sizeof(*vals));</div><div class='add'>+	sample_cnt = tl_collect_values_u64(telemetry, ctr-&gt;offset1, hist_vals);</div><div class='add'>+	if (!sample_cnt)</div><div class='add'>+		goto out_free_hist_cnt;</div><div class='add'>+</div><div class='add'>+	tl_collect_values_u32(telemetry, ctr-&gt;offset2, hist_cnt);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; sample_cnt; i++) {</div><div class='add'>+		/* Avoid division by 0 if count is 0. */</div><div class='add'>+		if (hist_cnt[i])</div><div class='add'>+			hist_vals[i] = div_u64(hist_vals[i] * cpp_ns_per_cycle,</div><div class='add'>+					       hist_cnt[i]);</div><div class='add'>+		else</div><div class='add'>+			hist_vals[i] = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vals-&gt;curr = hist_vals[sample_cnt - 1];</div><div class='add'>+	vals-&gt;min = min_array(hist_vals, sample_cnt);</div><div class='add'>+	vals-&gt;max = max_array(hist_vals, sample_cnt);</div><div class='add'>+	vals-&gt;avg = avg_array(hist_vals, sample_cnt);</div><div class='add'>+</div><div class='add'>+out_free_hist_cnt:</div><div class='add'>+	kfree(hist_cnt);</div><div class='add'>+out_free_hist_vals:</div><div class='add'>+	kfree(hist_vals);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Convert HW raw bandwidth units to Mbps. */</div><div class='add'>+static int tl_bw_hw_units_to_mbps(struct adf_telemetry *telemetry,</div><div class='add'>+				  const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+				  struct adf_tl_dbg_aggr_values *vals)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(telemetry-&gt;accel_dev);</div><div class='add'>+	u16 bw_hw_2_bits = tl_data-&gt;bw_units_to_bytes * BITS_PER_BYTE;</div><div class='add'>+	u64 *hist_vals;</div><div class='add'>+	int sample_cnt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	hist_vals = kmalloc_array(tl_data-&gt;num_hbuff, sizeof(*hist_vals),</div><div class='add'>+				  GFP_KERNEL);</div><div class='add'>+	if (!hist_vals)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	memset(vals, 0, sizeof(*vals));</div><div class='add'>+	sample_cnt = tl_collect_values_u32(telemetry, ctr-&gt;offset1, hist_vals);</div><div class='add'>+	if (!sample_cnt)</div><div class='add'>+		goto out_free_hist_vals;</div><div class='add'>+</div><div class='add'>+	vals-&gt;curr = div_u64(hist_vals[sample_cnt - 1] * bw_hw_2_bits, MEGA);</div><div class='add'>+	vals-&gt;min = div_u64(min_array(hist_vals, sample_cnt) * bw_hw_2_bits, MEGA);</div><div class='add'>+	vals-&gt;max = div_u64(max_array(hist_vals, sample_cnt) * bw_hw_2_bits, MEGA);</div><div class='add'>+	vals-&gt;avg = div_u64(avg_array(hist_vals, sample_cnt) * bw_hw_2_bits, MEGA);</div><div class='add'>+</div><div class='add'>+out_free_hist_vals:</div><div class='add'>+	kfree(hist_vals);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tl_seq_printf_counter(struct adf_telemetry *telemetry,</div><div class='add'>+				  struct seq_file *s, const char *name,</div><div class='add'>+				  struct adf_tl_dbg_aggr_values *vals)</div><div class='add'>+{</div><div class='add'>+	seq_printf(s, "%-*s", TL_KEY_MIN_PADDING, name);</div><div class='add'>+	seq_printf(s, "%*llu", TL_VALUE_MIN_PADDING, vals-&gt;curr);</div><div class='add'>+	if (atomic_read(&amp;telemetry-&gt;state) &gt; 1) {</div><div class='add'>+		seq_printf(s, "%*llu", TL_VALUE_MIN_PADDING, vals-&gt;min);</div><div class='add'>+		seq_printf(s, "%*llu", TL_VALUE_MIN_PADDING, vals-&gt;max);</div><div class='add'>+		seq_printf(s, "%*llu", TL_VALUE_MIN_PADDING, vals-&gt;avg);</div><div class='add'>+	}</div><div class='add'>+	seq_puts(s, "\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_calc_and_print_counter(struct adf_telemetry *telemetry,</div><div class='add'>+				     struct seq_file *s,</div><div class='add'>+				     const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+				     const char *name)</div><div class='add'>+{</div><div class='add'>+	const char *counter_name = name ? name : ctr-&gt;name;</div><div class='add'>+	enum adf_tl_counter_type type = ctr-&gt;type;</div><div class='add'>+	struct adf_tl_dbg_aggr_values vals;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case ADF_TL_SIMPLE_COUNT:</div><div class='add'>+		ret = tl_calc_count(telemetry, ctr, &amp;vals);</div><div class='add'>+		break;</div><div class='add'>+	case ADF_TL_COUNTER_NS:</div><div class='add'>+		ret = tl_cycles_to_ns(telemetry, ctr, &amp;vals);</div><div class='add'>+		break;</div><div class='add'>+	case ADF_TL_COUNTER_NS_AVG:</div><div class='add'>+		ret = tl_lat_acc_avg(telemetry, ctr, &amp;vals);</div><div class='add'>+		break;</div><div class='add'>+	case ADF_TL_COUNTER_MBPS:</div><div class='add'>+		ret = tl_bw_hw_units_to_mbps(telemetry, ctr, &amp;vals);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	tl_seq_printf_counter(telemetry, s, counter_name, &amp;vals);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_print_sl_counter(struct adf_telemetry *telemetry,</div><div class='add'>+			       const struct adf_tl_dbg_counter *ctr,</div><div class='add'>+			       struct seq_file *s, u8 cnt_id)</div><div class='add'>+{</div><div class='add'>+	size_t sl_regs_sz = GET_TL_DATA(telemetry-&gt;accel_dev).slice_reg_sz;</div><div class='add'>+	struct adf_tl_dbg_counter slice_ctr;</div><div class='add'>+	size_t offset_inc = cnt_id * sl_regs_sz;</div><div class='add'>+	char cnt_name[MAX_COUNT_NAME_SIZE];</div><div class='add'>+</div><div class='add'>+	snprintf(cnt_name, MAX_COUNT_NAME_SIZE, "%s%d", ctr-&gt;name, cnt_id);</div><div class='add'>+	slice_ctr = *ctr;</div><div class='add'>+	slice_ctr.offset1 += offset_inc;</div><div class='add'>+</div><div class='add'>+	return tl_calc_and_print_counter(telemetry, s, &amp;slice_ctr, cnt_name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_calc_and_print_sl_counters(struct adf_accel_dev *accel_dev,</div><div class='add'>+					 struct seq_file *s, u8 cnt_type, u8 cnt_id)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	const struct adf_tl_dbg_counter *sl_tl_util_counters;</div><div class='add'>+	const struct adf_tl_dbg_counter *sl_tl_exec_counters;</div><div class='add'>+	const struct adf_tl_dbg_counter *ctr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	sl_tl_util_counters = tl_data-&gt;sl_util_counters;</div><div class='add'>+	sl_tl_exec_counters = tl_data-&gt;sl_exec_counters;</div><div class='add'>+</div><div class='add'>+	ctr = &amp;sl_tl_util_counters[cnt_type];</div><div class='add'>+</div><div class='add'>+	ret = tl_print_sl_counter(telemetry, ctr, s, cnt_id);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_notice(&amp;GET_DEV(accel_dev),</div><div class='add'>+			   "invalid slice utilization counter type\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ctr = &amp;sl_tl_exec_counters[cnt_type];</div><div class='add'>+</div><div class='add'>+	ret = tl_print_sl_counter(telemetry, ctr, s, cnt_id);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_notice(&amp;GET_DEV(accel_dev),</div><div class='add'>+			   "invalid slice execution counter type\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tl_print_msg_cnt(struct seq_file *s, u32 msg_cnt)</div><div class='add'>+{</div><div class='add'>+	seq_printf(s, "%-*s", TL_KEY_MIN_PADDING, SNAPSHOT_CNT_MSG);</div><div class='add'>+	seq_printf(s, "%*u\n", TL_VALUE_MIN_PADDING, msg_cnt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_print_dev_data(struct adf_accel_dev *accel_dev,</div><div class='add'>+			     struct seq_file *s)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	const struct adf_tl_dbg_counter *dev_tl_counters;</div><div class='add'>+	u8 num_dev_counters = tl_data-&gt;num_dev_counters;</div><div class='add'>+	u8 *sl_cnt = (u8 *)&amp;telemetry-&gt;slice_cnt;</div><div class='add'>+	const struct adf_tl_dbg_counter *ctr;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+	u8 j;</div><div class='add'>+</div><div class='add'>+	if (!atomic_read(&amp;telemetry-&gt;state)) {</div><div class='add'>+		dev_info(&amp;GET_DEV(accel_dev), "not enabled\n");</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_tl_counters = tl_data-&gt;dev_counters;</div><div class='add'>+</div><div class='add'>+	tl_print_msg_cnt(s, telemetry-&gt;msg_cnt);</div><div class='add'>+</div><div class='add'>+	/* Print device level telemetry. */</div><div class='add'>+	for (i = 0; i &lt; num_dev_counters; i++) {</div><div class='add'>+		ctr = &amp;dev_tl_counters[i];</div><div class='add'>+		ret = tl_calc_and_print_counter(telemetry, s, ctr, NULL);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_notice(&amp;GET_DEV(accel_dev),</div><div class='add'>+				   "invalid counter type\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Print per slice telemetry. */</div><div class='add'>+	for (i = 0; i &lt; ADF_TL_SL_CNT_COUNT; i++) {</div><div class='add'>+		for (j = 0; j &lt; sl_cnt[i]; j++) {</div><div class='add'>+			ret = tl_calc_and_print_sl_counters(accel_dev, s, i, j);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_dev_data_show(struct seq_file *s, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct adf_accel_dev *accel_dev = s-&gt;private;</div><div class='add'>+</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return tl_print_dev_data(accel_dev, s);</div><div class='add'>+}</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(tl_dev_data);</div><div class='add'>+</div><div class='add'>+static int tl_control_show(struct seq_file *s, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct adf_accel_dev *accel_dev = s-&gt;private;</div><div class='add'>+</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	seq_printf(s, "%d\n", atomic_read(&amp;accel_dev-&gt;telemetry-&gt;state));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t tl_control_write(struct file *file, const char __user *userbuf,</div><div class='add'>+				size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct seq_file *seq_f = file-&gt;private_data;</div><div class='add'>+	struct adf_accel_dev *accel_dev;</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='add'>+	struct adf_tl_hw_data *tl_data;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	u32 input;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	accel_dev = seq_f-&gt;private;</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;telemetry-&gt;wr_lock);</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32_from_user(userbuf, count, 10, &amp;input);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+</div><div class='add'>+	if (input &gt; tl_data-&gt;num_hbuff) {</div><div class='add'>+		dev_info(dev, "invalid control input\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If input is 0, just stop telemetry. */</div><div class='add'>+	if (!input) {</div><div class='add'>+		ret = adf_tl_halt(accel_dev);</div><div class='add'>+		if (!ret)</div><div class='add'>+			ret = count;</div><div class='add'>+</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If TL is already enabled, stop it. */</div><div class='add'>+	if (atomic_read(&amp;telemetry-&gt;state)) {</div><div class='add'>+		dev_info(dev, "already enabled, restarting.\n");</div><div class='add'>+		ret = adf_tl_halt(accel_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto unlock_and_exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = adf_tl_run(accel_dev, input);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+</div><div class='add'>+	ret = count;</div><div class='add'>+</div><div class='add'>+unlock_and_exit:</div><div class='add'>+	mutex_unlock(&amp;telemetry-&gt;wr_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+DEFINE_SHOW_STORE_ATTRIBUTE(tl_control);</div><div class='add'>+</div><div class='add'>+static int get_rp_index_from_file(const struct file *f, u8 *rp_id, u8 rp_num)</div><div class='add'>+{</div><div class='add'>+	char alpha;</div><div class='add'>+	u8 index;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = sscanf(f-&gt;f_path.dentry-&gt;d_name.name, ADF_TL_RP_REGS_FNAME, &amp;alpha);</div><div class='add'>+	if (ret != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	index = ADF_TL_DBG_RP_INDEX_ALPHA(alpha);</div><div class='add'>+	*rp_id = index;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adf_tl_dbg_change_rp_index(struct adf_accel_dev *accel_dev,</div><div class='add'>+				      unsigned int new_rp_num,</div><div class='add'>+				      unsigned int rp_regs_index)</div><div class='add'>+{</div><div class='add'>+	struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct device *dev = &amp;GET_DEV(accel_dev);</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u8 curr_state;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (new_rp_num &gt;= hw_data-&gt;num_rps) {</div><div class='add'>+		dev_info(dev, "invalid Ring Pair number selected\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; hw_data-&gt;tl_data.max_rp; i++) {</div><div class='add'>+		if (telemetry-&gt;rp_num_indexes[i] == new_rp_num) {</div><div class='add'>+			dev_info(dev, "RP nr: %d is already selected in slot rp_%c_data\n",</div><div class='add'>+				 new_rp_num, ADF_TL_DBG_RP_ALPHA_INDEX(i));</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "selecting RP nr %u into slot rp_%c_data\n",</div><div class='add'>+		new_rp_num, ADF_TL_DBG_RP_ALPHA_INDEX(rp_regs_index));</div><div class='add'>+</div><div class='add'>+	curr_state = atomic_read(&amp;telemetry-&gt;state);</div><div class='add'>+</div><div class='add'>+	if (curr_state) {</div><div class='add'>+		ret = adf_tl_halt(accel_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		telemetry-&gt;rp_num_indexes[rp_regs_index] = new_rp_num;</div><div class='add'>+</div><div class='add'>+		ret = adf_tl_run(accel_dev, curr_state);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	} else {</div><div class='add'>+		telemetry-&gt;rp_num_indexes[rp_regs_index] = new_rp_num;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tl_print_rp_srv(struct adf_accel_dev *accel_dev, struct seq_file *s,</div><div class='add'>+			    u8 rp_idx)</div><div class='add'>+{</div><div class='add'>+	u32 banks_per_vf = GET_HW_DATA(accel_dev)-&gt;num_banks_per_vf;</div><div class='add'>+	enum adf_cfg_service_type svc;</div><div class='add'>+</div><div class='add'>+	seq_printf(s, "%-*s", TL_KEY_MIN_PADDING, RP_SERVICE_TYPE);</div><div class='add'>+</div><div class='add'>+	svc = GET_SRV_TYPE(accel_dev, rp_idx % banks_per_vf);</div><div class='add'>+	switch (svc) {</div><div class='add'>+	case COMP:</div><div class='add'>+		seq_printf(s, "%*s\n", TL_VALUE_MIN_PADDING, ADF_CFG_DC);</div><div class='add'>+		break;</div><div class='add'>+	case SYM:</div><div class='add'>+		seq_printf(s, "%*s\n", TL_VALUE_MIN_PADDING, ADF_CFG_SYM);</div><div class='add'>+		break;</div><div class='add'>+	case ASYM:</div><div class='add'>+		seq_printf(s, "%*s\n", TL_VALUE_MIN_PADDING, ADF_CFG_ASYM);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		seq_printf(s, "%*s\n", TL_VALUE_MIN_PADDING, TL_RP_SRV_UNKNOWN);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_print_rp_data(struct adf_accel_dev *accel_dev, struct seq_file *s,</div><div class='add'>+			    u8 rp_regs_index)</div><div class='add'>+{</div><div class='add'>+	struct adf_tl_hw_data *tl_data = &amp;GET_TL_DATA(accel_dev);</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	const struct adf_tl_dbg_counter *rp_tl_counters;</div><div class='add'>+	u8 num_rp_counters = tl_data-&gt;num_rp_counters;</div><div class='add'>+	size_t rp_regs_sz = tl_data-&gt;rp_reg_sz;</div><div class='add'>+	struct adf_tl_dbg_counter ctr;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u8 rp_idx;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!atomic_read(&amp;telemetry-&gt;state)) {</div><div class='add'>+		dev_info(&amp;GET_DEV(accel_dev), "not enabled\n");</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rp_tl_counters = tl_data-&gt;rp_counters;</div><div class='add'>+	rp_idx = telemetry-&gt;rp_num_indexes[rp_regs_index];</div><div class='add'>+</div><div class='add'>+	if (rp_idx == ADF_TL_RP_REGS_DISABLED) {</div><div class='add'>+		dev_info(&amp;GET_DEV(accel_dev), "no RP number selected in rp_%c_data\n",</div><div class='add'>+			 ADF_TL_DBG_RP_ALPHA_INDEX(rp_regs_index));</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tl_print_msg_cnt(s, telemetry-&gt;msg_cnt);</div><div class='add'>+	seq_printf(s, "%-*s", TL_KEY_MIN_PADDING, RP_NUM_INDEX);</div><div class='add'>+	seq_printf(s, "%*d\n", TL_VALUE_MIN_PADDING, rp_idx);</div><div class='add'>+	tl_print_rp_srv(accel_dev, s, rp_idx);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_rp_counters; i++) {</div><div class='add'>+		ctr = rp_tl_counters[i];</div><div class='add'>+		ctr.offset1 += rp_regs_sz * rp_regs_index;</div><div class='add'>+		ctr.offset2 += rp_regs_sz * rp_regs_index;</div><div class='add'>+		ret = tl_calc_and_print_counter(telemetry, s, &amp;ctr, NULL);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(&amp;GET_DEV(accel_dev),</div><div class='add'>+				"invalid RP counter type\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tl_rp_data_show(struct seq_file *s, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct adf_accel_dev *accel_dev = s-&gt;private;</div><div class='add'>+	u8 rp_regs_index;</div><div class='add'>+	u8 max_rp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	max_rp = GET_TL_DATA(accel_dev).max_rp;</div><div class='add'>+	ret = get_rp_index_from_file(s-&gt;file, &amp;rp_regs_index, max_rp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(&amp;GET_DEV(accel_dev), "invalid RP data file name\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return tl_print_rp_data(accel_dev, s, rp_regs_index);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t tl_rp_data_write(struct file *file, const char __user *userbuf,</div><div class='add'>+				size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct seq_file *seq_f = file-&gt;private_data;</div><div class='add'>+	struct adf_accel_dev *accel_dev;</div><div class='add'>+	struct adf_telemetry *telemetry;</div><div class='add'>+	unsigned int new_rp_num;</div><div class='add'>+	u8 rp_regs_index;</div><div class='add'>+	u8 max_rp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	accel_dev = seq_f-&gt;private;</div><div class='add'>+	if (!accel_dev)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	max_rp = GET_TL_DATA(accel_dev).max_rp;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;telemetry-&gt;wr_lock);</div><div class='add'>+</div><div class='add'>+	ret = get_rp_index_from_file(file, &amp;rp_regs_index, max_rp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(&amp;GET_DEV(accel_dev), "invalid RP data file name\n");</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32_from_user(userbuf, count, 10, &amp;new_rp_num);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+</div><div class='add'>+	ret = adf_tl_dbg_change_rp_index(accel_dev, new_rp_num, rp_regs_index);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock_and_exit;</div><div class='add'>+</div><div class='add'>+	ret = count;</div><div class='add'>+</div><div class='add'>+unlock_and_exit:</div><div class='add'>+	mutex_unlock(&amp;telemetry-&gt;wr_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+DEFINE_SHOW_STORE_ATTRIBUTE(tl_rp_data);</div><div class='add'>+</div><div class='add'>+void adf_tl_dbgfs_add(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct dentry *parent = accel_dev-&gt;debugfs_dir;</div><div class='add'>+	u8 max_rp = GET_TL_DATA(accel_dev).max_rp;</div><div class='add'>+	char name[ADF_TL_RP_REGS_FNAME_SIZE];</div><div class='add'>+	struct dentry *dir;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (!telemetry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dir = debugfs_create_dir("telemetry", parent);</div><div class='add'>+	accel_dev-&gt;telemetry-&gt;dbg_dir = dir;</div><div class='add'>+	debugfs_create_file("device_data", 0444, dir, accel_dev, &amp;tl_dev_data_fops);</div><div class='add'>+	debugfs_create_file("control", 0644, dir, accel_dev, &amp;tl_control_fops);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; max_rp; i++) {</div><div class='add'>+		snprintf(name, sizeof(name), ADF_TL_RP_REGS_FNAME,</div><div class='add'>+			 ADF_TL_DBG_RP_ALPHA_INDEX(i));</div><div class='add'>+		debugfs_create_file(name, 0644, dir, accel_dev, &amp;tl_rp_data_fops);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void adf_tl_dbgfs_rm(struct adf_accel_dev *accel_dev)</div><div class='add'>+{</div><div class='add'>+	struct adf_telemetry *telemetry = accel_dev-&gt;telemetry;</div><div class='add'>+	struct dentry *dbg_dir;</div><div class='add'>+</div><div class='add'>+	if (!telemetry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dbg_dir = telemetry-&gt;dbg_dir;</div><div class='add'>+</div><div class='add'>+	debugfs_remove_recursive(dbg_dir);</div><div class='add'>+</div><div class='add'>+	if (atomic_read(&amp;telemetry-&gt;state))</div><div class='add'>+		adf_tl_halt(accel_dev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h b/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h<br/>new file mode 100644<br/>index 000000000000..11cc9eae19b3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,117 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Copyright (c) 2023 Intel Corporation. */</div><div class='add'>+#ifndef ADF_TL_DEBUGFS_H</div><div class='add'>+#define ADF_TL_DEBUGFS_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct adf_accel_dev;</div><div class='add'>+</div><div class='add'>+#define MAX_COUNT_NAME_SIZE	32</div><div class='add'>+#define SNAPSHOT_CNT_MSG	"sample_cnt"</div><div class='add'>+#define RP_NUM_INDEX		"rp_num"</div><div class='add'>+#define PCI_TRANS_CNT_NAME	"pci_trans_cnt"</div><div class='add'>+#define MAX_RD_LAT_NAME		"max_rd_lat"</div><div class='add'>+#define RD_LAT_ACC_NAME		"rd_lat_acc_avg"</div><div class='add'>+#define MAX_LAT_NAME		"max_gp_lat"</div><div class='add'>+#define LAT_ACC_NAME		"gp_lat_acc_avg"</div><div class='add'>+#define BW_IN_NAME		"bw_in"</div><div class='add'>+#define BW_OUT_NAME		"bw_out"</div><div class='add'>+#define PAGE_REQ_LAT_NAME	"at_page_req_lat_avg"</div><div class='add'>+#define AT_TRANS_LAT_NAME	"at_trans_lat_avg"</div><div class='add'>+#define AT_MAX_UTLB_USED_NAME	"at_max_tlb_used"</div><div class='add'>+#define AT_GLOB_DTLB_HIT_NAME	"at_glob_devtlb_hit"</div><div class='add'>+#define AT_GLOB_DTLB_MISS_NAME	"at_glob_devtlb_miss"</div><div class='add'>+#define AT_PAYLD_DTLB_HIT_NAME	"tl_at_payld_devtlb_hit"</div><div class='add'>+#define AT_PAYLD_DTLB_MISS_NAME	"tl_at_payld_devtlb_miss"</div><div class='add'>+#define RP_SERVICE_TYPE		"service_type"</div><div class='add'>+</div><div class='add'>+#define ADF_TL_DBG_RP_ALPHA_INDEX(index) ((index) + 'A')</div><div class='add'>+#define ADF_TL_DBG_RP_INDEX_ALPHA(alpha) ((alpha) - 'A')</div><div class='add'>+</div><div class='add'>+#define ADF_TL_RP_REGS_FNAME		"rp_%c_data"</div><div class='add'>+#define ADF_TL_RP_REGS_FNAME_SIZE		16</div><div class='add'>+</div><div class='add'>+#define ADF_TL_DATA_REG_OFF(reg, qat_gen)	\</div><div class='add'>+	offsetof(struct adf_##qat_gen##_tl_layout, reg)</div><div class='add'>+</div><div class='add'>+#define ADF_TL_DEV_REG_OFF(reg, qat_gen)			\</div><div class='add'>+	(ADF_TL_DATA_REG_OFF(tl_device_data_regs, qat_gen) +	\</div><div class='add'>+	offsetof(struct adf_##qat_gen##_tl_device_data_regs, reg))</div><div class='add'>+</div><div class='add'>+#define ADF_TL_SLICE_REG_OFF(slice, reg, qat_gen)		\</div><div class='add'>+	(ADF_TL_DEV_REG_OFF(slice##_slices[0], qat_gen) +	\</div><div class='add'>+	offsetof(struct adf_##qat_gen##_tl_slice_data_regs, reg))</div><div class='add'>+</div><div class='add'>+#define ADF_TL_RP_REG_OFF(reg, qat_gen)					\</div><div class='add'>+	(ADF_TL_DATA_REG_OFF(tl_ring_pairs_data_regs[0], qat_gen) +	\</div><div class='add'>+	offsetof(struct adf_##qat_gen##_tl_ring_pair_data_regs, reg))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum adf_tl_counter_type - telemetry counter types</div><div class='add'>+ * @ADF_TL_COUNTER_UNSUPPORTED: unsupported counter</div><div class='add'>+ * @ADF_TL_SIMPLE_COUNT: simple counter</div><div class='add'>+ * @ADF_TL_COUNTER_NS: latency counter, value in ns</div><div class='add'>+ * @ADF_TL_COUNTER_NS_AVG: accumulated average latency counter, value in ns</div><div class='add'>+ * @ADF_TL_COUNTER_MBPS: bandwidth, value in MBps</div><div class='add'>+ */</div><div class='add'>+enum adf_tl_counter_type {</div><div class='add'>+	ADF_TL_COUNTER_UNSUPPORTED,</div><div class='add'>+	ADF_TL_SIMPLE_COUNT,</div><div class='add'>+	ADF_TL_COUNTER_NS,</div><div class='add'>+	ADF_TL_COUNTER_NS_AVG,</div><div class='add'>+	ADF_TL_COUNTER_MBPS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct adf_tl_dbg_counter - telemetry counter definition</div><div class='add'>+ * @name: name of the counter as printed in the report</div><div class='add'>+ * @adf_tl_counter_type: type of the counter</div><div class='add'>+ * @offset1: offset of 1st register</div><div class='add'>+ * @offset2: offset of 2nd optional register</div><div class='add'>+ */</div><div class='add'>+struct adf_tl_dbg_counter {</div><div class='add'>+	const char *name;</div><div class='add'>+	enum adf_tl_counter_type type;</div><div class='add'>+	size_t offset1;</div><div class='add'>+	size_t offset2;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ADF_TL_COUNTER(_name, _type, _offset)	\</div><div class='add'>+{	.name =		_name,			\</div><div class='add'>+	.type =		_type,			\</div><div class='add'>+	.offset1 =	_offset			\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define ADF_TL_COUNTER_LATENCY(_name, _type, _offset1, _offset2)	\</div><div class='add'>+{	.name =		_name,						\</div><div class='add'>+	.type =		_type,						\</div><div class='add'>+	.offset1 =	_offset1,					\</div><div class='add'>+	.offset2 =	_offset2					\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Telemetry counter aggregated values. */</div><div class='add'>+struct adf_tl_dbg_aggr_values {</div><div class='add'>+	u64 curr;</div><div class='add'>+	u64 min;</div><div class='add'>+	u64 max;</div><div class='add'>+	u64 avg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * adf_tl_dbgfs_add() - Add telemetry's debug fs entries.</div><div class='add'>+ * @accel_dev: Pointer to acceleration device.</div><div class='add'>+ *</div><div class='add'>+ * Creates telemetry's debug fs folder and attributes in QAT debug fs root.</div><div class='add'>+ */</div><div class='add'>+void adf_tl_dbgfs_add(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * adf_tl_dbgfs_rm() - Remove telemetry's debug fs entries.</div><div class='add'>+ * @accel_dev: Pointer to acceleration device.</div><div class='add'>+ *</div><div class='add'>+ * Removes telemetry's debug fs folder and attributes from QAT debug fs root.</div><div class='add'>+ */</div><div class='add'>+void adf_tl_dbgfs_rm(struct adf_accel_dev *accel_dev);</div><div class='add'>+</div><div class='add'>+#endif /* ADF_TL_DEBUGFS_H */</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h b/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h<br/>index cd418b51d9f3..63cf18e2a4e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h</a></div><div class='hunk'>@@ -29,6 +29,8 @@ enum icp_qat_fw_init_admin_cmd_id {</div><div class='ctx'> 	ICP_QAT_FW_RL_ADD = 134,</div><div class='ctx'> 	ICP_QAT_FW_RL_UPDATE = 135,</div><div class='ctx'> 	ICP_QAT_FW_RL_REMOVE = 136,</div><div class='add'>+	ICP_QAT_FW_TL_START = 137,</div><div class='add'>+	ICP_QAT_FW_TL_STOP = 138,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum icp_qat_fw_init_admin_resp_status {</div><div class='hunk'>@@ -36,6 +38,13 @@ enum icp_qat_fw_init_admin_resp_status {</div><div class='ctx'> 	ICP_QAT_FW_INIT_RESP_STATUS_FAIL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct icp_qat_fw_init_admin_tl_rp_indexes {</div><div class='add'>+	__u8 rp_num_index_0;</div><div class='add'>+	__u8 rp_num_index_1;</div><div class='add'>+	__u8 rp_num_index_2;</div><div class='add'>+	__u8 rp_num_index_3;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct icp_qat_fw_init_admin_slice_cnt {</div><div class='ctx'> 	__u8 cpr_cnt;</div><div class='ctx'> 	__u8 xlt_cnt;</div><div class='hunk'>@@ -87,6 +96,7 @@ struct icp_qat_fw_init_admin_req {</div><div class='ctx'> 			__u8 rp_count;</div><div class='ctx'> 		};</div><div class='ctx'> 		__u32 idle_filter;</div><div class='add'>+		struct icp_qat_fw_init_admin_tl_rp_indexes rp_indexes;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	__u32 resrvd4;</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h b/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h<br/>index eb2ef225bcee..b8f1c4ffb8b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/icp_qat_hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_hw.h</a></div><div class='hunk'>@@ -18,7 +18,12 @@ enum icp_qat_hw_ae_id {</div><div class='ctx'> 	ICP_QAT_HW_AE_9 = 9,</div><div class='ctx'> 	ICP_QAT_HW_AE_10 = 10,</div><div class='ctx'> 	ICP_QAT_HW_AE_11 = 11,</div><div class='del'>-	ICP_QAT_HW_AE_DELIMITER = 12</div><div class='add'>+	ICP_QAT_HW_AE_12 = 12,</div><div class='add'>+	ICP_QAT_HW_AE_13 = 13,</div><div class='add'>+	ICP_QAT_HW_AE_14 = 14,</div><div class='add'>+	ICP_QAT_HW_AE_15 = 15,</div><div class='add'>+	ICP_QAT_HW_AE_16 = 16,</div><div class='add'>+	ICP_QAT_HW_AE_DELIMITER = 17</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum icp_qat_hw_qat_id {</div><div class='hunk'>@@ -95,7 +100,7 @@ enum icp_qat_capabilities_mask {</div><div class='ctx'> 	/* Bits 10-11 are currently reserved */</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_HKDF = BIT(12),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13),</div><div class='del'>-	/* Bit 14 is currently reserved */</div><div class='add'>+	ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = BIT(14),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),</div><div class='hunk'>@@ -107,7 +112,10 @@ enum icp_qat_capabilities_mask {</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24),</div><div class='ctx'> 	ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25),</div><div class='del'>-	ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26)</div><div class='add'>+	ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26),</div><div class='add'>+	/* Bits 27-28 are currently reserved */</div><div class='add'>+	ICP_ACCEL_CAPABILITIES_ZUC_256 = BIT(29),</div><div class='add'>+	ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT = BIT(30),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define QAT_AUTH_MODE_BITPOS 4</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h b/drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h<br/>index 69482abdb8b9..e28241bdd0f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/icp_qat_uclo.h</a></div><div class='hunk'>@@ -7,7 +7,7 @@</div><div class='ctx'> #define ICP_QAT_AC_C62X_DEV_TYPE   0x01000000</div><div class='ctx'> #define ICP_QAT_AC_C3XXX_DEV_TYPE  0x02000000</div><div class='ctx'> #define ICP_QAT_AC_4XXX_A_DEV_TYPE 0x08000000</div><div class='del'>-#define ICP_QAT_UCLO_MAX_AE       12</div><div class='add'>+#define ICP_QAT_UCLO_MAX_AE       17</div><div class='ctx'> #define ICP_QAT_UCLO_MAX_CTX      8</div><div class='ctx'> #define ICP_QAT_UCLO_MAX_UIMAGE   (ICP_QAT_UCLO_MAX_AE * ICP_QAT_UCLO_MAX_CTX)</div><div class='ctx'> #define ICP_QAT_UCLO_MAX_USTORE   0x4000</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/qat_hal.c b/drivers/crypto/intel/qat/qat_common/qat_hal.c<br/>index cbb946a80076..317cafa9d11f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/qat_hal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/qat_hal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/qat_hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/qat_hal.c</a></div><div class='hunk'>@@ -697,12 +697,16 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,</div><div class='ctx'> 	case ADF_4XXX_PCI_DEVICE_ID:</div><div class='ctx'> 	case ADF_401XX_PCI_DEVICE_ID:</div><div class='ctx'> 	case ADF_402XX_PCI_DEVICE_ID:</div><div class='add'>+	case ADF_420XX_PCI_DEVICE_ID:</div><div class='ctx'> 		handle-&gt;chip_info-&gt;mmp_sram_size = 0;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;nn = false;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;lm2lm3 = true;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;icp_rst_csr = ICP_RESET_CPP0;</div><div class='del'>-		handle-&gt;chip_info-&gt;icp_rst_mask = 0x100015;</div><div class='add'>+		if (handle-&gt;pci_dev-&gt;device == ADF_420XX_PCI_DEVICE_ID)</div><div class='add'>+			handle-&gt;chip_info-&gt;icp_rst_mask = 0x100155;</div><div class='add'>+		else</div><div class='add'>+			handle-&gt;chip_info-&gt;icp_rst_mask = 0x100015;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;misc_ctl_csr = MISC_CONTROL_C4XXX;</div><div class='ctx'> 		handle-&gt;chip_info-&gt;wakeup_event_val = 0x80000000;</div><div class='head'>diff --git a/drivers/crypto/intel/qat/qat_common/qat_uclo.c b/drivers/crypto/intel/qat/qat_common/qat_uclo.c<br/>index e27ea7e28c51..ad2c64af7427 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/qat_uclo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/intel/qat/qat_common/qat_uclo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/intel/qat/qat_common/qat_uclo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/intel/qat/qat_common/qat_uclo.c</a></div><div class='hunk'>@@ -733,6 +733,7 @@ qat_uclo_get_dev_type(struct icp_qat_fw_loader_handle *handle)</div><div class='ctx'> 	case ADF_4XXX_PCI_DEVICE_ID:</div><div class='ctx'> 	case ADF_401XX_PCI_DEVICE_ID:</div><div class='ctx'> 	case ADF_402XX_PCI_DEVICE_ID:</div><div class='add'>+	case ADF_420XX_PCI_DEVICE_ID:</div><div class='ctx'> 		return ICP_QAT_AC_4XXX_A_DEV_TYPE;</div><div class='ctx'> 	default:</div><div class='ctx'> 		pr_err("QAT: unsupported device 0x%x\n",</div><div class='head'>diff --git a/drivers/crypto/marvell/cesa/cesa.c b/drivers/crypto/marvell/cesa/cesa.c<br/>index 5744df30c838..5fd31ba715c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/cesa/cesa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/cesa/cesa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/cesa/cesa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/cesa/cesa.c</a></div><div class='hunk'>@@ -488,7 +488,7 @@ static int mv_cesa_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; caps-&gt;nengines; i++) {</div><div class='ctx'> 		struct mv_cesa_engine *engine = &amp;cesa-&gt;engines[i];</div><div class='del'>-		char res_name[7];</div><div class='add'>+		char res_name[16];</div><div class='ctx'> </div><div class='ctx'> 		engine-&gt;id = i;</div><div class='ctx'> 		spin_lock_init(&amp;engine-&gt;lock);</div><div class='hunk'>@@ -509,7 +509,7 @@ static int mv_cesa_probe(struct platform_device *pdev)</div><div class='ctx'> 		 * Not all platforms can gate the CESA clocks: do not complain</div><div class='ctx'> 		 * if the clock does not exist.</div><div class='ctx'> 		 */</div><div class='del'>-		snprintf(res_name, sizeof(res_name), "cesa%d", i);</div><div class='add'>+		snprintf(res_name, sizeof(res_name), "cesa%u", i);</div><div class='ctx'> 		engine-&gt;clk = devm_clk_get(dev, res_name);</div><div class='ctx'> 		if (IS_ERR(engine-&gt;clk)) {</div><div class='ctx'> 			engine-&gt;clk = devm_clk_get(dev, NULL);</div><div class='hunk'>@@ -517,7 +517,7 @@ static int mv_cesa_probe(struct platform_device *pdev)</div><div class='ctx'> 				engine-&gt;clk = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		snprintf(res_name, sizeof(res_name), "cesaz%d", i);</div><div class='add'>+		snprintf(res_name, sizeof(res_name), "cesaz%u", i);</div><div class='ctx'> 		engine-&gt;zclk = devm_clk_get(dev, res_name);</div><div class='ctx'> 		if (IS_ERR(engine-&gt;zclk))</div><div class='ctx'> 			engine-&gt;zclk = NULL;</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c<br/>index 1c2c870e887a..3c5d577d8f0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx/otx_cptvf_algs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx/otx_cptvf_algs.c</a></div><div class='hunk'>@@ -473,12 +473,6 @@ static int otx_cpt_skcipher_ecb_aes_setkey(struct crypto_skcipher *tfm,</div><div class='ctx'> 	return cpt_aes_setkey(tfm, key, keylen, OTX_CPT_AES_ECB);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int otx_cpt_skcipher_cfb_aes_setkey(struct crypto_skcipher *tfm,</div><div class='del'>-					   const u8 *key, u32 keylen)</div><div class='del'>-{</div><div class='del'>-	return cpt_aes_setkey(tfm, key, keylen, OTX_CPT_AES_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int otx_cpt_skcipher_cbc_des3_setkey(struct crypto_skcipher *tfm,</div><div class='ctx'> 					    const u8 *key, u32 keylen)</div><div class='ctx'> {</div><div class='hunk'>@@ -1352,23 +1346,6 @@ static struct skcipher_alg otx_cpt_skciphers[] = { {</div><div class='ctx'> 	.encrypt = otx_cpt_skcipher_encrypt,</div><div class='ctx'> 	.decrypt = otx_cpt_skcipher_decrypt,</div><div class='ctx'> }, {</div><div class='del'>-	.base.cra_name = "cfb(aes)",</div><div class='del'>-	.base.cra_driver_name = "cpt_cfb_aes",</div><div class='del'>-	.base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY,</div><div class='del'>-	.base.cra_blocksize = AES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize = sizeof(struct otx_cpt_enc_ctx),</div><div class='del'>-	.base.cra_alignmask = 7,</div><div class='del'>-	.base.cra_priority = 4001,</div><div class='del'>-	.base.cra_module = THIS_MODULE,</div><div class='del'>-</div><div class='del'>-	.init = otx_cpt_enc_dec_init,</div><div class='del'>-	.ivsize = AES_BLOCK_SIZE,</div><div class='del'>-	.min_keysize = AES_MIN_KEY_SIZE,</div><div class='del'>-	.max_keysize = AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey = otx_cpt_skcipher_cfb_aes_setkey,</div><div class='del'>-	.encrypt = otx_cpt_skcipher_encrypt,</div><div class='del'>-	.decrypt = otx_cpt_skcipher_decrypt,</div><div class='del'>-}, {</div><div class='ctx'> 	.base.cra_name = "cbc(des3_ede)",</div><div class='ctx'> 	.base.cra_driver_name = "cpt_cbc_des3_ede",</div><div class='ctx'> 	.base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY,</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c<br/>index 93d22b328991..79b4e74804f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/cn10k_cpt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/cn10k_cpt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/cn10k_cpt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/cn10k_cpt.c</a></div><div class='hunk'>@@ -14,12 +14,14 @@ static struct cpt_hw_ops otx2_hw_ops = {</div><div class='ctx'> 	.send_cmd = otx2_cpt_send_cmd,</div><div class='ctx'> 	.cpt_get_compcode = otx2_cpt_get_compcode,</div><div class='ctx'> 	.cpt_get_uc_compcode = otx2_cpt_get_uc_compcode,</div><div class='add'>+	.cpt_sg_info_create = otx2_sg_info_create,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct cpt_hw_ops cn10k_hw_ops = {</div><div class='ctx'> 	.send_cmd = cn10k_cpt_send_cmd,</div><div class='ctx'> 	.cpt_get_compcode = cn10k_cpt_get_compcode,</div><div class='ctx'> 	.cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode,</div><div class='add'>+	.cpt_sg_info_create = otx2_sg_info_create,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num,</div><div class='hunk'>@@ -78,12 +80,9 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> 	struct pci_dev *pdev = cptvf-&gt;pdev;</div><div class='ctx'> 	resource_size_t offset, size;</div><div class='ctx'> </div><div class='del'>-	if (!test_bit(CN10K_LMTST, &amp;cptvf-&gt;cap_flag)) {</div><div class='del'>-		cptvf-&gt;lfs.ops = &amp;otx2_hw_ops;</div><div class='add'>+	if (!test_bit(CN10K_LMTST, &amp;cptvf-&gt;cap_flag))</div><div class='ctx'> 		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	cptvf-&gt;lfs.ops = &amp;cn10k_hw_ops;</div><div class='ctx'> 	offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);</div><div class='ctx'> 	size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);</div><div class='ctx'> 	/* Map VF LMILINE region */</div><div class='hunk'>@@ -96,3 +95,82 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,</div><div class='add'>+			    struct cn10k_cpt_errata_ctx *er_ctx)</div><div class='add'>+{</div><div class='add'>+	u64 cptr_dma;</div><div class='add'>+</div><div class='add'>+	if (!is_dev_cn10ka_ax(pdev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cptr_dma = er_ctx-&gt;cptr_dma &amp; ~(BIT_ULL(60));</div><div class='add'>+	cn10k_cpt_ctx_flush(pdev, cptr_dma, true);</div><div class='add'>+	dma_unmap_single(&amp;pdev-&gt;dev, cptr_dma, CN10K_CPT_HW_CTX_SIZE,</div><div class='add'>+			 DMA_BIDIRECTIONAL);</div><div class='add'>+	kfree(er_ctx-&gt;hw_ctx);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_clear, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz)</div><div class='add'>+{</div><div class='add'>+	hctx-&gt;w0.aop_valid = 1;</div><div class='add'>+	hctx-&gt;w0.ctx_hdr_sz = 0;</div><div class='add'>+	hctx-&gt;w0.ctx_sz = ctx_sz;</div><div class='add'>+	hctx-&gt;w0.ctx_push_sz = 1;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_set, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,</div><div class='add'>+			  struct cn10k_cpt_errata_ctx *er_ctx)</div><div class='add'>+{</div><div class='add'>+	union cn10k_cpt_hw_ctx *hctx;</div><div class='add'>+	u64 cptr_dma;</div><div class='add'>+</div><div class='add'>+	er_ctx-&gt;cptr_dma = 0;</div><div class='add'>+	er_ctx-&gt;hw_ctx = NULL;</div><div class='add'>+</div><div class='add'>+	if (!is_dev_cn10ka_ax(pdev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	hctx = kmalloc(CN10K_CPT_HW_CTX_SIZE, GFP_KERNEL);</div><div class='add'>+	if (unlikely(!hctx))</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	cptr_dma = dma_map_single(&amp;pdev-&gt;dev, hctx, CN10K_CPT_HW_CTX_SIZE,</div><div class='add'>+				  DMA_BIDIRECTIONAL);</div><div class='add'>+</div><div class='add'>+	cn10k_cpt_hw_ctx_set(hctx, 1);</div><div class='add'>+	er_ctx-&gt;hw_ctx = hctx;</div><div class='add'>+	er_ctx-&gt;cptr_dma = cptr_dma | BIT_ULL(60);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cn10k_cpt_hw_ctx_init, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval)</div><div class='add'>+{</div><div class='add'>+	struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);</div><div class='add'>+	struct otx2_cptlfs_info *lfs = &amp;cptvf-&gt;lfs;</div><div class='add'>+	u64 reg;</div><div class='add'>+</div><div class='add'>+	reg = (uintptr_t)cptr &gt;&gt; 7;</div><div class='add'>+	if (inval)</div><div class='add'>+		reg = reg | BIT_ULL(46);</div><div class='add'>+</div><div class='add'>+	otx2_cpt_write64(lfs-&gt;reg_base, lfs-&gt;blkaddr, lfs-&gt;lf[0].slot,</div><div class='add'>+			 OTX2_CPT_LF_CTX_FLUSH, reg);</div><div class='add'>+	/* Make sure that the FLUSH operation is complete */</div><div class='add'>+	wmb();</div><div class='add'>+	otx2_cpt_read64(lfs-&gt;reg_base, lfs-&gt;blkaddr, lfs-&gt;lf[0].slot,</div><div class='add'>+			OTX2_CPT_LF_CTX_ERR);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cn10k_cpt_ctx_flush, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf)</div><div class='add'>+{</div><div class='add'>+	if (test_bit(CN10K_LMTST, &amp;cptvf-&gt;cap_flag))</div><div class='add'>+		cptvf-&gt;lfs.ops = &amp;cn10k_hw_ops;</div><div class='add'>+	else</div><div class='add'>+		cptvf-&gt;lfs.ops = &amp;otx2_hw_ops;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cptvf_hw_ops_get, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h<br/>index aaefc7e38e06..92be3ecf570f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/cn10k_cpt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/cn10k_cpt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/cn10k_cpt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/cn10k_cpt.h</a></div><div class='hunk'>@@ -8,6 +8,26 @@</div><div class='ctx'> #include "otx2_cptpf.h"</div><div class='ctx'> #include "otx2_cptvf.h"</div><div class='ctx'> </div><div class='add'>+#define CN10K_CPT_HW_CTX_SIZE  256</div><div class='add'>+</div><div class='add'>+union cn10k_cpt_hw_ctx {</div><div class='add'>+	u64 u;</div><div class='add'>+	struct {</div><div class='add'>+		u64 reserved_0_47:48;</div><div class='add'>+		u64 ctx_push_sz:7;</div><div class='add'>+		u64 reserved_55:1;</div><div class='add'>+		u64 ctx_hdr_sz:2;</div><div class='add'>+		u64 aop_valid:1;</div><div class='add'>+		u64 reserved_59:1;</div><div class='add'>+		u64 ctx_sz:4;</div><div class='add'>+	} w0;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct cn10k_cpt_errata_ctx {</div><div class='add'>+	union cn10k_cpt_hw_ctx *hw_ctx;</div><div class='add'>+	u64 cptr_dma;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static inline u8 cn10k_cpt_get_compcode(union otx2_cpt_res_s *result)</div><div class='ctx'> {</div><div class='ctx'> 	return ((struct cn10k_cpt_res_s *)result)-&gt;compcode;</div><div class='hunk'>@@ -30,5 +50,12 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)</div><div class='ctx'> </div><div class='ctx'> int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);</div><div class='ctx'> int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);</div><div class='add'>+void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);</div><div class='add'>+int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,</div><div class='add'>+			  struct cn10k_cpt_errata_ctx *er_ctx);</div><div class='add'>+void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,</div><div class='add'>+			    struct cn10k_cpt_errata_ctx *er_ctx);</div><div class='add'>+void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz);</div><div class='add'>+void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf);</div><div class='ctx'> </div><div class='ctx'> #endif /* __CN10K_CPTLF_H */</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h<br/>index 46b778bbbee4..c5b7c57574ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cpt_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_common.h</a></div><div class='hunk'>@@ -56,7 +56,11 @@ struct otx2_cpt_rx_inline_lf_cfg {</div><div class='ctx'> 	u16 param2;</div><div class='ctx'> 	u16 opcode;</div><div class='ctx'> 	u32 credit;</div><div class='add'>+	u32 credit_th;</div><div class='add'>+	u16 bpid;</div><div class='ctx'> 	u32 reserved;</div><div class='add'>+	u8 ctx_ilen_valid : 1;</div><div class='add'>+	u8 ctx_ilen : 7;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -102,7 +106,10 @@ union otx2_cpt_eng_caps {</div><div class='ctx'> 		u64 kasumi:1;</div><div class='ctx'> 		u64 des:1;</div><div class='ctx'> 		u64 crc:1;</div><div class='del'>-		u64 reserved_14_63:50;</div><div class='add'>+		u64 mmul:1;</div><div class='add'>+		u64 reserved_15_33:19;</div><div class='add'>+		u64 pdcp_chain:1;</div><div class='add'>+		u64 reserved_35_63:29;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -145,6 +152,35 @@ static inline bool is_dev_otx2(struct pci_dev *pdev)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool is_dev_cn10ka(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	return pdev-&gt;subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (pdev-&gt;subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &amp;&amp;</div><div class='add'>+	    ((pdev-&gt;revision &amp; 0xFF) == 4 || (pdev-&gt;revision &amp; 0xFF) == 0x50 ||</div><div class='add'>+	     (pdev-&gt;revision &amp; 0xff) == 0x51))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool is_dev_cn10kb(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	return pdev-&gt;subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_B;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (pdev-&gt;subsystem_device == CPT_PCI_SUBSYS_DEVID_CN10K_A &amp;&amp;</div><div class='add'>+	    (pdev-&gt;revision &amp; 0xFF) == 0x54)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,</div><div class='ctx'> 					unsigned long *cap_flag)</div><div class='ctx'> {</div><div class='hunk'>@@ -154,6 +190,21 @@ static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool cpt_is_errata_38550_exists(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (is_dev_otx2(pdev) || is_dev_cn10ka_ax(pdev))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool cpt_feature_sgv2(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (!is_dev_otx2(pdev) &amp;&amp; !is_dev_cn10ka_ax(pdev))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);</div><div class='ctx'> int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);</div><div class='hunk'>@@ -171,5 +222,6 @@ int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);</div><div class='add'>+int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);</div><div class='ctx'> </div><div class='ctx'> #endif /* __OTX2_CPT_COMMON_H */</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c<br/>index a2aba0b0d68a..d2b8d26db968 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_devlink.c</a></div><div class='hunk'>@@ -24,10 +24,45 @@ static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id,</div><div class='ctx'> static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id,</div><div class='ctx'> 			       struct devlink_param_gset_ctx *ctx)</div><div class='ctx'> {</div><div class='add'>+	ctx-&gt;val.vstr[0] = '\0';</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id,</div><div class='add'>+				     struct devlink_param_gset_ctx *ctx)</div><div class='add'>+{</div><div class='ctx'> 	struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);</div><div class='ctx'> 	struct otx2_cptpf_dev *cptpf = cpt_dl-&gt;cptpf;</div><div class='add'>+	struct pci_dev *pdev = cptpf-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_CTL, &amp;reg_val,</div><div class='add'>+			     BLKADDR_CPT0);</div><div class='add'>+	ctx-&gt;val.vu8 = (reg_val &gt;&gt; 18) &amp; 0x1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	otx2_cpt_print_uc_dbg_info(cptpf);</div><div class='add'>+static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id,</div><div class='add'>+				     struct devlink_param_gset_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl);</div><div class='add'>+	struct otx2_cptpf_dev *cptpf = cpt_dl-&gt;cptpf;</div><div class='add'>+	struct pci_dev *pdev = cptpf-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	if (cptpf-&gt;enabled_vfs != 0 || cptpf-&gt;eng_grps.is_grps_created)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	if (cpt_feature_sgv2(pdev)) {</div><div class='add'>+		otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_CTL,</div><div class='add'>+				     &amp;reg_val, BLKADDR_CPT0);</div><div class='add'>+		reg_val &amp;= ~(0x1ULL &lt;&lt; 18);</div><div class='add'>+		reg_val |= ((u64)ctx-&gt;val.vu8 &amp; 0x1) &lt;&lt; 18;</div><div class='add'>+		return otx2_cpt_write_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev,</div><div class='add'>+					     CPT_AF_CTL, reg_val, BLKADDR_CPT0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -36,6 +71,7 @@ enum otx2_cpt_dl_param_id {</div><div class='ctx'> 	OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,</div><div class='ctx'> 	OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE,</div><div class='ctx'> 	OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE,</div><div class='add'>+	OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct devlink_param otx2_cpt_dl_params[] = {</div><div class='hunk'>@@ -49,6 +85,11 @@ static const struct devlink_param otx2_cpt_dl_params[] = {</div><div class='ctx'> 			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),</div><div class='ctx'> 			     otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_delete,</div><div class='ctx'> 			     NULL),</div><div class='add'>+	DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE,</div><div class='add'>+			     "t106_mode", DEVLINK_PARAM_TYPE_U8,</div><div class='add'>+			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),</div><div class='add'>+			     otx2_cpt_dl_t106_mode_get, otx2_cpt_dl_t106_mode_set,</div><div class='add'>+			     NULL),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int otx2_cpt_dl_info_firmware_version_put(struct devlink_info_req *req,</div><div class='hunk'>@@ -120,7 +161,6 @@ int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf)</div><div class='ctx'> 		devlink_free(dl);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='ctx'> 	devlink_register(dl);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h<br/>index 6f947978e4e8..7e746a4def86 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h</a></div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2</div><div class='ctx'> #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3</div><div class='ctx'> </div><div class='add'>+#define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900</div><div class='add'>+#define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00</div><div class='add'>+</div><div class='ctx'> /* Mailbox interrupts offset */</div><div class='ctx'> #define OTX2_CPT_PF_MBOX_INT	6</div><div class='ctx'> #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))</div><div class='hunk'>@@ -99,6 +102,9 @@</div><div class='ctx'> #define OTX2_CPT_LF_Q_INST_PTR          (0x110)</div><div class='ctx'> #define OTX2_CPT_LF_Q_GRP_PTR           (0x120)</div><div class='ctx'> #define OTX2_CPT_LF_NQX(a)              (0x400 | (a) &lt;&lt; 3)</div><div class='add'>+#define OTX2_CPT_LF_CTX_CTL             (0x500)</div><div class='add'>+#define OTX2_CPT_LF_CTX_FLUSH           (0x510)</div><div class='add'>+#define OTX2_CPT_LF_CTX_ERR             (0x520)</div><div class='ctx'> #define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20</div><div class='ctx'> /* LMT LF registers */</div><div class='ctx'> #define OTX2_CPT_LMT_LFBASE             BIT_ULL(OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT)</div><div class='hunk'>@@ -467,7 +473,8 @@ union otx2_cptx_af_lf_ctrl {</div><div class='ctx'> 		u64 cont_err:1;</div><div class='ctx'> 		u64 reserved_11_15:5;</div><div class='ctx'> 		u64 nixtx_en:1;</div><div class='del'>-		u64 reserved_17_47:31;</div><div class='add'>+		u64 ctx_ilen:3;</div><div class='add'>+		u64 reserved_17_47:28;</div><div class='ctx'> 		u64 grp:8;</div><div class='ctx'> 		u64 reserved_56_63:8;</div><div class='ctx'> 	} s;</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c<br/>index 273ee5352a50..5be0103c1fb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c</a></div><div class='hunk'>@@ -229,3 +229,29 @@ int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox)</div><div class='ctx'> 	return otx2_mbox_check_rsp_msgs(mbox, 0);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(otx2_cpt_sync_mbox_msg, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)</div><div class='add'>+{</div><div class='add'>+	struct otx2_mbox *mbox = lfs-&gt;mbox;</div><div class='add'>+	struct pci_dev *pdev = lfs-&gt;pdev;</div><div class='add'>+	struct cpt_lf_rst_req *req;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	req = (struct cpt_lf_rst_req *)otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),</div><div class='add'>+							       sizeof(struct msg_rsp));</div><div class='add'>+	if (!req) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "RVU MBOX failed to get message.\n");</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	req-&gt;hdr.id = MBOX_MSG_CPT_LF_RESET;</div><div class='add'>+	req-&gt;hdr.sig = OTX2_MBOX_REQ_SIG;</div><div class='add'>+	req-&gt;hdr.pcifunc = 0;</div><div class='add'>+	req-&gt;slot = slot;</div><div class='add'>+	ret = otx2_cpt_send_mbox_msg(mbox, pdev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h<br/>index dbb1ee746f4c..e27e849b01df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h</a></div><div class='hunk'>@@ -27,6 +27,13 @@</div><div class='ctx'> </div><div class='ctx'> #define OTX2_CPT_MAX_REQ_SIZE 65535</div><div class='ctx'> </div><div class='add'>+#define SG_COMPS_MAX    4</div><div class='add'>+#define SGV2_COMPS_MAX  3</div><div class='add'>+</div><div class='add'>+#define SG_COMP_3    3</div><div class='add'>+#define SG_COMP_2    2</div><div class='add'>+#define SG_COMP_1    1</div><div class='add'>+</div><div class='ctx'> union otx2_cpt_opcode {</div><div class='ctx'> 	u16 flags;</div><div class='ctx'> 	struct {</div><div class='hunk'>@@ -40,6 +47,8 @@ struct otx2_cptvf_request {</div><div class='ctx'> 	u32 param2;</div><div class='ctx'> 	u16 dlen;</div><div class='ctx'> 	union otx2_cpt_opcode opcode;</div><div class='add'>+	dma_addr_t cptr_dma;</div><div class='add'>+	void *cptr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -143,6 +152,8 @@ struct otx2_cpt_inst_info {</div><div class='ctx'> 	unsigned long time_in;</div><div class='ctx'> 	u32 dlen;</div><div class='ctx'> 	u32 dma_len;</div><div class='add'>+	u64 gthr_sz;</div><div class='add'>+	u64 sctr_sz;</div><div class='ctx'> 	u8 extra_time;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -157,6 +168,16 @@ struct otx2_cpt_sglist_component {</div><div class='ctx'> 	__be64 ptr3;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct cn10kb_cpt_sglist_component {</div><div class='add'>+	u16 len0;</div><div class='add'>+	u16 len1;</div><div class='add'>+	u16 len2;</div><div class='add'>+	u16 valid_segs;</div><div class='add'>+	u64 ptr0;</div><div class='add'>+	u64 ptr1;</div><div class='add'>+	u64 ptr2;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,</div><div class='ctx'> 					 struct otx2_cpt_inst_info *info)</div><div class='ctx'> {</div><div class='hunk'>@@ -188,6 +209,283 @@ static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,</div><div class='ctx'> 	kfree(info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline int setup_sgio_components(struct pci_dev *pdev,</div><div class='add'>+					struct otx2_cpt_buf_ptr *list,</div><div class='add'>+					int buf_count, u8 *buffer)</div><div class='add'>+{</div><div class='add'>+	struct otx2_cpt_sglist_component *sg_ptr;</div><div class='add'>+	int components;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!list)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Input list pointer is NULL\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; buf_count; i++) {</div><div class='add'>+		if (unlikely(!list[i].vptr))</div><div class='add'>+			continue;</div><div class='add'>+		list[i].dma_addr = dma_map_single(&amp;pdev-&gt;dev, list[i].vptr,</div><div class='add'>+						  list[i].size,</div><div class='add'>+						  DMA_BIDIRECTIONAL);</div><div class='add'>+		if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, list[i].dma_addr))) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "Dma mapping failed\n");</div><div class='add'>+			goto sg_cleanup;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	components = buf_count / SG_COMPS_MAX;</div><div class='add'>+	sg_ptr = (struct otx2_cpt_sglist_component *)buffer;</div><div class='add'>+	for (i = 0; i &lt; components; i++) {</div><div class='add'>+		sg_ptr-&gt;len0 = cpu_to_be16(list[i * SG_COMPS_MAX + 0].size);</div><div class='add'>+		sg_ptr-&gt;len1 = cpu_to_be16(list[i * SG_COMPS_MAX + 1].size);</div><div class='add'>+		sg_ptr-&gt;len2 = cpu_to_be16(list[i * SG_COMPS_MAX + 2].size);</div><div class='add'>+		sg_ptr-&gt;len3 = cpu_to_be16(list[i * SG_COMPS_MAX + 3].size);</div><div class='add'>+		sg_ptr-&gt;ptr0 = cpu_to_be64(list[i * SG_COMPS_MAX + 0].dma_addr);</div><div class='add'>+		sg_ptr-&gt;ptr1 = cpu_to_be64(list[i * SG_COMPS_MAX + 1].dma_addr);</div><div class='add'>+		sg_ptr-&gt;ptr2 = cpu_to_be64(list[i * SG_COMPS_MAX + 2].dma_addr);</div><div class='add'>+		sg_ptr-&gt;ptr3 = cpu_to_be64(list[i * SG_COMPS_MAX + 3].dma_addr);</div><div class='add'>+		sg_ptr++;</div><div class='add'>+	}</div><div class='add'>+	components = buf_count % SG_COMPS_MAX;</div><div class='add'>+</div><div class='add'>+	switch (components) {</div><div class='add'>+	case SG_COMP_3:</div><div class='add'>+		sg_ptr-&gt;len2 = cpu_to_be16(list[i * SG_COMPS_MAX + 2].size);</div><div class='add'>+		sg_ptr-&gt;ptr2 = cpu_to_be64(list[i * SG_COMPS_MAX + 2].dma_addr);</div><div class='add'>+		fallthrough;</div><div class='add'>+	case SG_COMP_2:</div><div class='add'>+		sg_ptr-&gt;len1 = cpu_to_be16(list[i * SG_COMPS_MAX + 1].size);</div><div class='add'>+		sg_ptr-&gt;ptr1 = cpu_to_be64(list[i * SG_COMPS_MAX + 1].dma_addr);</div><div class='add'>+		fallthrough;</div><div class='add'>+	case SG_COMP_1:</div><div class='add'>+		sg_ptr-&gt;len0 = cpu_to_be16(list[i * SG_COMPS_MAX + 0].size);</div><div class='add'>+		sg_ptr-&gt;ptr0 = cpu_to_be64(list[i * SG_COMPS_MAX + 0].dma_addr);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+sg_cleanup:</div><div class='add'>+	for (j = 0; j &lt; i; j++) {</div><div class='add'>+		if (list[j].dma_addr) {</div><div class='add'>+			dma_unmap_single(&amp;pdev-&gt;dev, list[j].dma_addr,</div><div class='add'>+					 list[j].size, DMA_BIDIRECTIONAL);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		list[j].dma_addr = 0;</div><div class='add'>+	}</div><div class='add'>+	return -EIO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int sgv2io_components_setup(struct pci_dev *pdev,</div><div class='add'>+					  struct otx2_cpt_buf_ptr *list,</div><div class='add'>+					  int buf_count, u8 *buffer)</div><div class='add'>+{</div><div class='add'>+	struct cn10kb_cpt_sglist_component *sg_ptr;</div><div class='add'>+	int components;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!list)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Input list pointer is NULL\n");</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; buf_count; i++) {</div><div class='add'>+		if (unlikely(!list[i].vptr))</div><div class='add'>+			continue;</div><div class='add'>+		list[i].dma_addr = dma_map_single(&amp;pdev-&gt;dev, list[i].vptr,</div><div class='add'>+						  list[i].size,</div><div class='add'>+						  DMA_BIDIRECTIONAL);</div><div class='add'>+		if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, list[i].dma_addr))) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "Dma mapping failed\n");</div><div class='add'>+			goto sg_cleanup;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	components = buf_count / SGV2_COMPS_MAX;</div><div class='add'>+	sg_ptr = (struct cn10kb_cpt_sglist_component *)buffer;</div><div class='add'>+	for (i = 0; i &lt; components; i++) {</div><div class='add'>+		sg_ptr-&gt;len0 = list[i * SGV2_COMPS_MAX + 0].size;</div><div class='add'>+		sg_ptr-&gt;len1 = list[i * SGV2_COMPS_MAX + 1].size;</div><div class='add'>+		sg_ptr-&gt;len2 = list[i * SGV2_COMPS_MAX + 2].size;</div><div class='add'>+		sg_ptr-&gt;ptr0 = list[i * SGV2_COMPS_MAX + 0].dma_addr;</div><div class='add'>+		sg_ptr-&gt;ptr1 = list[i * SGV2_COMPS_MAX + 1].dma_addr;</div><div class='add'>+		sg_ptr-&gt;ptr2 = list[i * SGV2_COMPS_MAX + 2].dma_addr;</div><div class='add'>+		sg_ptr-&gt;valid_segs = SGV2_COMPS_MAX;</div><div class='add'>+		sg_ptr++;</div><div class='add'>+	}</div><div class='add'>+	components = buf_count % SGV2_COMPS_MAX;</div><div class='add'>+</div><div class='add'>+	sg_ptr-&gt;valid_segs = components;</div><div class='add'>+	switch (components) {</div><div class='add'>+	case SG_COMP_2:</div><div class='add'>+		sg_ptr-&gt;len1 = list[i * SGV2_COMPS_MAX + 1].size;</div><div class='add'>+		sg_ptr-&gt;ptr1 = list[i * SGV2_COMPS_MAX + 1].dma_addr;</div><div class='add'>+		fallthrough;</div><div class='add'>+	case SG_COMP_1:</div><div class='add'>+		sg_ptr-&gt;len0 = list[i * SGV2_COMPS_MAX + 0].size;</div><div class='add'>+		sg_ptr-&gt;ptr0 = list[i * SGV2_COMPS_MAX + 0].dma_addr;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+sg_cleanup:</div><div class='add'>+	for (j = 0; j &lt; i; j++) {</div><div class='add'>+		if (list[j].dma_addr) {</div><div class='add'>+			dma_unmap_single(&amp;pdev-&gt;dev, list[j].dma_addr,</div><div class='add'>+					 list[j].size, DMA_BIDIRECTIONAL);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		list[j].dma_addr = 0;</div><div class='add'>+	}</div><div class='add'>+	return -EIO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct otx2_cpt_inst_info *</div><div class='add'>+cn10k_sgv2_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='add'>+		       gfp_t gfp)</div><div class='add'>+{</div><div class='add'>+	u32 dlen = 0, g_len, sg_len, info_len;</div><div class='add'>+	int align = OTX2_CPT_DMA_MINALIGN;</div><div class='add'>+	struct otx2_cpt_inst_info *info;</div><div class='add'>+	u16 g_sz_bytes, s_sz_bytes;</div><div class='add'>+	u32 total_mem_len;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	g_sz_bytes = ((req-&gt;in_cnt + 2) / 3) *</div><div class='add'>+		      sizeof(struct cn10kb_cpt_sglist_component);</div><div class='add'>+	s_sz_bytes = ((req-&gt;out_cnt + 2) / 3) *</div><div class='add'>+		      sizeof(struct cn10kb_cpt_sglist_component);</div><div class='add'>+</div><div class='add'>+	g_len = ALIGN(g_sz_bytes, align);</div><div class='add'>+	sg_len = ALIGN(g_len + s_sz_bytes, align);</div><div class='add'>+	info_len = ALIGN(sizeof(*info), align);</div><div class='add'>+	total_mem_len = sg_len + info_len + sizeof(union otx2_cpt_res_s);</div><div class='add'>+</div><div class='add'>+	info = kzalloc(total_mem_len, gfp);</div><div class='add'>+	if (unlikely(!info))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; req-&gt;in_cnt; i++)</div><div class='add'>+		dlen += req-&gt;in[i].size;</div><div class='add'>+</div><div class='add'>+	info-&gt;dlen = dlen;</div><div class='add'>+	info-&gt;in_buffer = (u8 *)info + info_len;</div><div class='add'>+	info-&gt;gthr_sz = req-&gt;in_cnt;</div><div class='add'>+	info-&gt;sctr_sz = req-&gt;out_cnt;</div><div class='add'>+</div><div class='add'>+	/* Setup gather (input) components */</div><div class='add'>+	if (sgv2io_components_setup(pdev, req-&gt;in, req-&gt;in_cnt,</div><div class='add'>+				    info-&gt;in_buffer)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to setup gather list\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (sgv2io_components_setup(pdev, req-&gt;out, req-&gt;out_cnt,</div><div class='add'>+				    &amp;info-&gt;in_buffer[g_len])) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to setup scatter list\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	info-&gt;dma_len = total_mem_len - info_len;</div><div class='add'>+	info-&gt;dptr_baddr = dma_map_single(&amp;pdev-&gt;dev, info-&gt;in_buffer,</div><div class='add'>+					  info-&gt;dma_len, DMA_BIDIRECTIONAL);</div><div class='add'>+	if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, info-&gt;dptr_baddr))) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "DMA Mapping failed for cpt req\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+	info-&gt;rptr_baddr = info-&gt;dptr_baddr + g_len;</div><div class='add'>+	/*</div><div class='add'>+	 * Get buffer for union otx2_cpt_res_s response</div><div class='add'>+	 * structure and its physical address</div><div class='add'>+	 */</div><div class='add'>+	info-&gt;completion_addr = info-&gt;in_buffer + sg_len;</div><div class='add'>+	info-&gt;comp_baddr = info-&gt;dptr_baddr + sg_len;</div><div class='add'>+</div><div class='add'>+	return info;</div><div class='add'>+</div><div class='add'>+destroy_info:</div><div class='add'>+	otx2_cpt_info_destroy(pdev, info);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* SG list header size in bytes */</div><div class='add'>+#define SG_LIST_HDR_SIZE	8</div><div class='add'>+static inline struct otx2_cpt_inst_info *</div><div class='add'>+otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='add'>+		    gfp_t gfp)</div><div class='add'>+{</div><div class='add'>+	int align = OTX2_CPT_DMA_MINALIGN;</div><div class='add'>+	struct otx2_cpt_inst_info *info;</div><div class='add'>+	u32 dlen, align_dlen, info_len;</div><div class='add'>+	u16 g_sz_bytes, s_sz_bytes;</div><div class='add'>+	u32 total_mem_len;</div><div class='add'>+</div><div class='add'>+	if (unlikely(req-&gt;in_cnt &gt; OTX2_CPT_MAX_SG_IN_CNT ||</div><div class='add'>+		     req-&gt;out_cnt &gt; OTX2_CPT_MAX_SG_OUT_CNT)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Error too many sg components\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	g_sz_bytes = ((req-&gt;in_cnt + 3) / 4) *</div><div class='add'>+		      sizeof(struct otx2_cpt_sglist_component);</div><div class='add'>+	s_sz_bytes = ((req-&gt;out_cnt + 3) / 4) *</div><div class='add'>+		      sizeof(struct otx2_cpt_sglist_component);</div><div class='add'>+</div><div class='add'>+	dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;</div><div class='add'>+	align_dlen = ALIGN(dlen, align);</div><div class='add'>+	info_len = ALIGN(sizeof(*info), align);</div><div class='add'>+	total_mem_len = align_dlen + info_len + sizeof(union otx2_cpt_res_s);</div><div class='add'>+</div><div class='add'>+	info = kzalloc(total_mem_len, gfp);</div><div class='add'>+	if (unlikely(!info))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	info-&gt;dlen = dlen;</div><div class='add'>+	info-&gt;in_buffer = (u8 *)info + info_len;</div><div class='add'>+</div><div class='add'>+	((u16 *)info-&gt;in_buffer)[0] = req-&gt;out_cnt;</div><div class='add'>+	((u16 *)info-&gt;in_buffer)[1] = req-&gt;in_cnt;</div><div class='add'>+	((u16 *)info-&gt;in_buffer)[2] = 0;</div><div class='add'>+	((u16 *)info-&gt;in_buffer)[3] = 0;</div><div class='add'>+	cpu_to_be64s((u64 *)info-&gt;in_buffer);</div><div class='add'>+</div><div class='add'>+	/* Setup gather (input) components */</div><div class='add'>+	if (setup_sgio_components(pdev, req-&gt;in, req-&gt;in_cnt,</div><div class='add'>+				  &amp;info-&gt;in_buffer[8])) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to setup gather list\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (setup_sgio_components(pdev, req-&gt;out, req-&gt;out_cnt,</div><div class='add'>+				  &amp;info-&gt;in_buffer[8 + g_sz_bytes])) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to setup scatter list\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	info-&gt;dma_len = total_mem_len - info_len;</div><div class='add'>+	info-&gt;dptr_baddr = dma_map_single(&amp;pdev-&gt;dev, info-&gt;in_buffer,</div><div class='add'>+					  info-&gt;dma_len, DMA_BIDIRECTIONAL);</div><div class='add'>+	if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, info-&gt;dptr_baddr))) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "DMA Mapping failed for cpt req\n");</div><div class='add'>+		goto destroy_info;</div><div class='add'>+	}</div><div class='add'>+	/*</div><div class='add'>+	 * Get buffer for union otx2_cpt_res_s response</div><div class='add'>+	 * structure and its physical address</div><div class='add'>+	 */</div><div class='add'>+	info-&gt;completion_addr = info-&gt;in_buffer + align_dlen;</div><div class='add'>+	info-&gt;comp_baddr = info-&gt;dptr_baddr + align_dlen;</div><div class='add'>+</div><div class='add'>+	return info;</div><div class='add'>+</div><div class='add'>+destroy_info:</div><div class='add'>+	otx2_cpt_info_destroy(pdev, info);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct otx2_cptlf_wqe;</div><div class='ctx'> int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='ctx'> 			int cpu_num);</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.c b/drivers/crypto/marvell/octeontx2/otx2_cptlf.c<br/>index 6edd27ff8c4e..b52728e3c0d1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptlf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptlf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptlf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptlf.c</a></div><div class='hunk'>@@ -106,6 +106,32 @@ static int cptlf_set_grp_and_pri(struct otx2_cptlfs_info *lfs,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int cptlf_set_ctx_ilen(struct otx2_cptlfs_info *lfs, int ctx_ilen)</div><div class='add'>+{</div><div class='add'>+	union otx2_cptx_af_lf_ctrl lf_ctrl;</div><div class='add'>+	struct otx2_cptlf_info *lf;</div><div class='add'>+	int slot, ret = 0;</div><div class='add'>+</div><div class='add'>+	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++) {</div><div class='add'>+		lf = &amp;lfs-&gt;lf[slot];</div><div class='add'>+</div><div class='add'>+		ret = otx2_cpt_read_af_reg(lfs-&gt;mbox, lfs-&gt;pdev,</div><div class='add'>+					   CPT_AF_LFX_CTL(lf-&gt;slot),</div><div class='add'>+					   &amp;lf_ctrl.u, lfs-&gt;blkaddr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		lf_ctrl.s.ctx_ilen = ctx_ilen;</div><div class='add'>+</div><div class='add'>+		ret = otx2_cpt_write_af_reg(lfs-&gt;mbox, lfs-&gt;pdev,</div><div class='add'>+					    CPT_AF_LFX_CTL(lf-&gt;slot),</div><div class='add'>+					    lf_ctrl.u, lfs-&gt;blkaddr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void cptlf_hw_init(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='ctx'> 	/* Disable instruction queues */</div><div class='hunk'>@@ -151,26 +177,14 @@ static void cptlf_set_misc_intrs(struct otx2_cptlfs_info *lfs, u8 enable)</div><div class='ctx'> 				 irq_misc.u);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cptlf_enable_intrs(struct otx2_cptlfs_info *lfs)</div><div class='del'>-{</div><div class='del'>-	int slot;</div><div class='del'>-</div><div class='del'>-	/* Enable done interrupts */</div><div class='del'>-	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++)</div><div class='del'>-		otx2_cpt_write64(lfs-&gt;reg_base, lfs-&gt;blkaddr, slot,</div><div class='del'>-				 OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);</div><div class='del'>-	/* Enable Misc interrupts */</div><div class='del'>-	cptlf_set_misc_intrs(lfs, true);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void cptlf_disable_intrs(struct otx2_cptlfs_info *lfs)</div><div class='add'>+static void cptlf_set_done_intrs(struct otx2_cptlfs_info *lfs, u8 enable)</div><div class='ctx'> {</div><div class='add'>+	u64 reg = enable ? OTX2_CPT_LF_DONE_INT_ENA_W1S :</div><div class='add'>+			   OTX2_CPT_LF_DONE_INT_ENA_W1C;</div><div class='ctx'> 	int slot;</div><div class='ctx'> </div><div class='ctx'> 	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++)</div><div class='del'>-		otx2_cpt_write64(lfs-&gt;reg_base, lfs-&gt;blkaddr, slot,</div><div class='del'>-				 OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);</div><div class='del'>-	cptlf_set_misc_intrs(lfs, false);</div><div class='add'>+		otx2_cpt_write64(lfs-&gt;reg_base, lfs-&gt;blkaddr, slot, reg, 0x1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf)</div><div class='hunk'>@@ -257,24 +271,44 @@ static irqreturn_t cptlf_done_intr_handler(int irq, void *arg)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='add'>+void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='del'>-	int i, offs, vector;</div><div class='add'>+	int i, irq_offs, vector;</div><div class='ctx'> </div><div class='add'>+	irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;</div><div class='ctx'> 	for (i = 0; i &lt; lfs-&gt;lfs_num; i++) {</div><div class='del'>-		for (offs = 0; offs &lt; OTX2_CPT_LF_MSIX_VECTORS; offs++) {</div><div class='del'>-			if (!lfs-&gt;lf[i].is_irq_reg[offs])</div><div class='del'>-				continue;</div><div class='add'>+		if (!lfs-&gt;lf[i].is_irq_reg[irq_offs])</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-			vector = pci_irq_vector(lfs-&gt;pdev,</div><div class='del'>-						lfs-&gt;lf[i].msix_offset + offs);</div><div class='del'>-			free_irq(vector, &amp;lfs-&gt;lf[i]);</div><div class='del'>-			lfs-&gt;lf[i].is_irq_reg[offs] = false;</div><div class='del'>-		}</div><div class='add'>+		vector = pci_irq_vector(lfs-&gt;pdev,</div><div class='add'>+					lfs-&gt;lf[i].msix_offset + irq_offs);</div><div class='add'>+		free_irq(vector, &amp;lfs-&gt;lf[i]);</div><div class='add'>+		lfs-&gt;lf[i].is_irq_reg[irq_offs] = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cptlf_set_misc_intrs(lfs, false);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_misc_interrupts,</div><div class='add'>+		     CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='add'>+{</div><div class='add'>+	int i, irq_offs, vector;</div><div class='add'>+</div><div class='add'>+	irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;</div><div class='add'>+	for (i = 0; i &lt; lfs-&gt;lfs_num; i++) {</div><div class='add'>+		if (!lfs-&gt;lf[i].is_irq_reg[irq_offs])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vector = pci_irq_vector(lfs-&gt;pdev,</div><div class='add'>+					lfs-&gt;lf[i].msix_offset + irq_offs);</div><div class='add'>+		free_irq(vector, &amp;lfs-&gt;lf[i]);</div><div class='add'>+		lfs-&gt;lf[i].is_irq_reg[irq_offs] = false;</div><div class='ctx'> 	}</div><div class='del'>-	cptlf_disable_intrs(lfs);</div><div class='add'>+</div><div class='add'>+	cptlf_set_done_intrs(lfs, false);</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_interrupts,</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_done_interrupts,</div><div class='ctx'> 		     CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='ctx'> </div><div class='ctx'> static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs,</div><div class='hunk'>@@ -296,34 +330,53 @@ static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='add'>+int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='add'>+	bool is_cpt1 = (lfs-&gt;blkaddr == BLKADDR_CPT1);</div><div class='ctx'> 	int irq_offs, ret, i;</div><div class='ctx'> </div><div class='add'>+	irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;</div><div class='ctx'> 	for (i = 0; i &lt; lfs-&gt;lfs_num; i++) {</div><div class='del'>-		irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;</div><div class='del'>-		snprintf(lfs-&gt;lf[i].irq_name[irq_offs], 32, "CPTLF Misc%d", i);</div><div class='add'>+		snprintf(lfs-&gt;lf[i].irq_name[irq_offs], 32, "CPT%dLF Misc%d",</div><div class='add'>+			 is_cpt1, i);</div><div class='ctx'> 		ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,</div><div class='ctx'> 						    cptlf_misc_intr_handler);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto free_irq;</div><div class='add'>+	}</div><div class='add'>+	cptlf_set_misc_intrs(lfs, true);</div><div class='add'>+	return 0;</div><div class='ctx'> </div><div class='del'>-		irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;</div><div class='del'>-		snprintf(lfs-&gt;lf[i].irq_name[irq_offs], 32, "OTX2_CPTLF Done%d",</div><div class='del'>-			 i);</div><div class='add'>+free_irq:</div><div class='add'>+	otx2_cptlf_unregister_misc_interrupts(lfs);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_misc_interrupts,</div><div class='add'>+		     CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+</div><div class='add'>+int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs)</div><div class='add'>+{</div><div class='add'>+	bool is_cpt1 = (lfs-&gt;blkaddr == BLKADDR_CPT1);</div><div class='add'>+	int irq_offs, ret, i;</div><div class='add'>+</div><div class='add'>+	irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;</div><div class='add'>+	for (i = 0; i &lt; lfs-&gt;lfs_num; i++) {</div><div class='add'>+		snprintf(lfs-&gt;lf[i].irq_name[irq_offs], 32,</div><div class='add'>+			 "OTX2_CPT%dLF Done%d", is_cpt1, i);</div><div class='ctx'> 		ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,</div><div class='ctx'> 						    cptlf_done_intr_handler);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto free_irq;</div><div class='ctx'> 	}</div><div class='del'>-	cptlf_enable_intrs(lfs);</div><div class='add'>+	cptlf_set_done_intrs(lfs, true);</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> free_irq:</div><div class='del'>-	otx2_cptlf_unregister_interrupts(lfs);</div><div class='add'>+	otx2_cptlf_unregister_done_interrupts(lfs);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_interrupts, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_done_interrupts,</div><div class='add'>+		     CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='ctx'> </div><div class='ctx'> void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='hunk'>@@ -416,11 +469,17 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto free_iq;</div><div class='ctx'> </div><div class='add'>+	if (lfs-&gt;ctx_ilen_ovrd) {</div><div class='add'>+		ret = cptlf_set_ctx_ilen(lfs, lfs-&gt;ctx_ilen);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_iq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> free_iq:</div><div class='del'>-	otx2_cpt_free_instruction_queues(lfs);</div><div class='ctx'> 	cptlf_hw_cleanup(lfs);</div><div class='add'>+	otx2_cpt_free_instruction_queues(lfs);</div><div class='ctx'> detach_rsrcs:</div><div class='ctx'> 	otx2_cpt_detach_rsrcs_msg(lfs);</div><div class='ctx'> clear_lfs_num:</div><div class='hunk'>@@ -431,11 +490,13 @@ EXPORT_SYMBOL_NS_GPL(otx2_cptlf_init, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='ctx'> </div><div class='ctx'> void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='del'>-	lfs-&gt;lfs_num = 0;</div><div class='ctx'> 	/* Cleanup LFs hardware side */</div><div class='ctx'> 	cptlf_hw_cleanup(lfs);</div><div class='add'>+	/* Free instruction queues */</div><div class='add'>+	otx2_cpt_free_instruction_queues(lfs);</div><div class='ctx'> 	/* Send request to detach LFs */</div><div class='ctx'> 	otx2_cpt_detach_rsrcs_msg(lfs);</div><div class='add'>+	lfs-&gt;lfs_num = 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(otx2_cptlf_shutdown, CRYPTO_DEV_OCTEONTX2_CPT);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h<br/>index 5302fe3d0e6f..bd8604be2952 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptlf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptlf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptlf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptlf.h</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> #define __OTX2_CPTLF_H</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/soc/marvell/octeontx2/asm.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;mbox.h&gt;</div><div class='ctx'> #include &lt;rvu.h&gt;</div><div class='ctx'> #include "otx2_cpt_common.h"</div><div class='hunk'>@@ -99,6 +100,9 @@ struct cpt_hw_ops {</div><div class='ctx'> 			 struct otx2_cptlf_info *lf);</div><div class='ctx'> 	u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result);</div><div class='ctx'> 	u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result);</div><div class='add'>+	struct otx2_cpt_inst_info *</div><div class='add'>+	(*cpt_sg_info_create)(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='add'>+			      gfp_t gfp);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct otx2_cptlfs_info {</div><div class='hunk'>@@ -116,6 +120,9 @@ struct otx2_cptlfs_info {</div><div class='ctx'> 	u8 kvf_limits;          /* Kernel crypto limits */</div><div class='ctx'> 	atomic_t state;         /* LF's state. started/reset */</div><div class='ctx'> 	int blkaddr;            /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */</div><div class='add'>+	int global_slot;        /* Global slot across the blocks */</div><div class='add'>+	u8 ctx_ilen;</div><div class='add'>+	u8 ctx_ilen_ovrd;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline void otx2_cpt_free_instruction_queues(</div><div class='hunk'>@@ -203,48 +210,71 @@ static inline void otx2_cptlf_set_iqueues_size(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> 		otx2_cptlf_do_set_iqueue_size(&amp;lfs-&gt;lf[slot]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define INFLIGHT   GENMASK_ULL(8, 0)</div><div class='add'>+#define GRB_CNT    GENMASK_ULL(39, 32)</div><div class='add'>+#define GWB_CNT    GENMASK_ULL(47, 40)</div><div class='add'>+#define XQ_XOR     GENMASK_ULL(63, 63)</div><div class='add'>+#define DQPTR      GENMASK_ULL(19, 0)</div><div class='add'>+#define NQPTR      GENMASK_ULL(51, 32)</div><div class='add'>+</div><div class='ctx'> static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)</div><div class='ctx'> {</div><div class='del'>-	union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };</div><div class='del'>-	union otx2_cptx_lf_inprog lf_inprog;</div><div class='add'>+	void __iomem *reg_base = lf-&gt;lfs-&gt;reg_base;</div><div class='add'>+	struct pci_dev *pdev = lf-&gt;lfs-&gt;pdev;</div><div class='ctx'> 	u8 blkaddr = lf-&gt;lfs-&gt;blkaddr;</div><div class='del'>-	int timeout = 20;</div><div class='add'>+	int timeout = 1000000;</div><div class='add'>+	u64 inprog, inst_ptr;</div><div class='add'>+	u64 slot = lf-&gt;slot;</div><div class='add'>+	u64 qsize, pending;</div><div class='add'>+	int i = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable instructions enqueuing */</div><div class='del'>-	otx2_cpt_write64(lf-&gt;lfs-&gt;reg_base, blkaddr, lf-&gt;slot,</div><div class='del'>-			 OTX2_CPT_LF_CTL, lf_ctl.u);</div><div class='add'>+	otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_CTL, 0x0);</div><div class='add'>+</div><div class='add'>+	inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);</div><div class='add'>+	inprog |= BIT_ULL(16);</div><div class='add'>+	otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG, inprog);</div><div class='ctx'> </div><div class='del'>-	/* Wait for instruction queue to become empty */</div><div class='add'>+	qsize = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_SIZE) &amp; 0x7FFF;</div><div class='add'>+	do {</div><div class='add'>+		inst_ptr = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_INST_PTR);</div><div class='add'>+		pending = (FIELD_GET(XQ_XOR, inst_ptr) * qsize * 40) +</div><div class='add'>+			  FIELD_GET(NQPTR, inst_ptr) - FIELD_GET(DQPTR, inst_ptr);</div><div class='add'>+		udelay(1);</div><div class='add'>+		timeout--;</div><div class='add'>+	} while ((pending != 0) &amp;&amp; (timeout != 0));</div><div class='add'>+</div><div class='add'>+	if (timeout == 0)</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "TIMEOUT: CPT poll on pending instructions\n");</div><div class='add'>+</div><div class='add'>+	timeout = 1000000;</div><div class='add'>+	/* Wait for CPT queue to become execution-quiescent */</div><div class='ctx'> 	do {</div><div class='del'>-		lf_inprog.u = otx2_cpt_read64(lf-&gt;lfs-&gt;reg_base, blkaddr,</div><div class='del'>-					      lf-&gt;slot, OTX2_CPT_LF_INPROG);</div><div class='del'>-		if (!lf_inprog.s.inflight)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		usleep_range(10000, 20000);</div><div class='del'>-		if (timeout-- &lt; 0) {</div><div class='del'>-			dev_err(&amp;lf-&gt;lfs-&gt;pdev-&gt;dev,</div><div class='del'>-				"Error LF %d is still busy.\n", lf-&gt;slot);</div><div class='del'>-			break;</div><div class='add'>+		inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);</div><div class='add'>+</div><div class='add'>+		if ((FIELD_GET(INFLIGHT, inprog) == 0) &amp;&amp;</div><div class='add'>+		    (FIELD_GET(GRB_CNT, inprog) == 0)) {</div><div class='add'>+			i++;</div><div class='add'>+		} else {</div><div class='add'>+			i = 0;</div><div class='add'>+			timeout--;</div><div class='ctx'> 		}</div><div class='add'>+	} while ((timeout != 0) &amp;&amp; (i &lt; 10));</div><div class='ctx'> </div><div class='del'>-	} while (1);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Disable executions in the LF's queue,</div><div class='del'>-	 * the queue should be empty at this point</div><div class='del'>-	 */</div><div class='del'>-	lf_inprog.s.eena = 0x0;</div><div class='del'>-	otx2_cpt_write64(lf-&gt;lfs-&gt;reg_base, blkaddr, lf-&gt;slot,</div><div class='del'>-			 OTX2_CPT_LF_INPROG, lf_inprog.u);</div><div class='add'>+	if (timeout == 0)</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "TIMEOUT: CPT poll on inflight count\n");</div><div class='add'>+	/* Wait for 2 us to flush all queue writes to memory */</div><div class='add'>+	udelay(2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> {</div><div class='ctx'> 	int slot;</div><div class='ctx'> </div><div class='del'>-	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++)</div><div class='add'>+	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++) {</div><div class='ctx'> 		otx2_cptlf_do_disable_iqueue(&amp;lfs-&gt;lf[slot]);</div><div class='add'>+		otx2_cpt_lf_reset_msg(lfs, lfs-&gt;global_slot + slot);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,</div><div class='hunk'>@@ -282,6 +312,19 @@ static inline void otx2_cptlf_set_iqueue_exec(struct otx2_cptlf_info *lf,</div><div class='ctx'> 			 OTX2_CPT_LF_INPROG, lf_inprog.u);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void otx2_cptlf_set_ctx_flr_flush(struct otx2_cptlf_info *lf)</div><div class='add'>+{</div><div class='add'>+	u8 blkaddr = lf-&gt;lfs-&gt;blkaddr;</div><div class='add'>+	u64 val;</div><div class='add'>+</div><div class='add'>+	val = otx2_cpt_read64(lf-&gt;lfs-&gt;reg_base, blkaddr, lf-&gt;slot,</div><div class='add'>+			      OTX2_CPT_LF_CTX_CTL);</div><div class='add'>+	val |= BIT_ULL(0);</div><div class='add'>+</div><div class='add'>+	otx2_cpt_write64(lf-&gt;lfs-&gt;reg_base, blkaddr, lf-&gt;slot,</div><div class='add'>+			 OTX2_CPT_LF_CTX_CTL, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)</div><div class='ctx'> {</div><div class='ctx'> 	otx2_cptlf_set_iqueue_exec(lf, true);</div><div class='hunk'>@@ -297,6 +340,10 @@ static inline void otx2_cptlf_enable_iqueues(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> 	int slot;</div><div class='ctx'> </div><div class='ctx'> 	for (slot = 0; slot &lt; lfs-&gt;lfs_num; slot++) {</div><div class='add'>+		/* Enable flush on FLR for Errata */</div><div class='add'>+		if (is_dev_cn10kb(lfs-&gt;pdev))</div><div class='add'>+			otx2_cptlf_set_ctx_flr_flush(&amp;lfs-&gt;lf[slot]);</div><div class='add'>+</div><div class='ctx'> 		otx2_cptlf_enable_iqueue_exec(&amp;lfs-&gt;lf[slot]);</div><div class='ctx'> 		otx2_cptlf_enable_iqueue_enq(&amp;lfs-&gt;lf[slot]);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -382,8 +429,10 @@ static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,</div><div class='ctx'> int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,</div><div class='ctx'> 		    int lfs_num);</div><div class='ctx'> void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);</div><div class='del'>-int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='del'>-void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='add'>+int otx2_cptlf_register_misc_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='add'>+int otx2_cptlf_register_done_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='add'>+void otx2_cptlf_unregister_misc_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='add'>+void otx2_cptlf_unregister_done_interrupts(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf.h b/drivers/crypto/marvell/octeontx2/otx2_cptpf.h<br/>index a209ec5af381..e5859a1e1c60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptpf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf.h</a></div><div class='hunk'>@@ -71,4 +71,8 @@ void otx2_cptpf_afpf_mbox_up_handler(struct work_struct *work);</div><div class='ctx'> irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);</div><div class='ctx'> void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);</div><div class='ctx'> </div><div class='add'>+int otx2_inline_cptlf_setup(struct otx2_cptpf_dev *cptpf,</div><div class='add'>+			    struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs);</div><div class='add'>+void otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs);</div><div class='add'>+</div><div class='ctx'> #endif /* __OTX2_CPTPF_H */</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c<br/>index e34223daa327..400e36d9908f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c</a></div><div class='hunk'>@@ -14,6 +14,8 @@</div><div class='ctx'> #define OTX2_CPT_DRV_STRING  "Marvell RVU CPT Physical Function Driver"</div><div class='ctx'> </div><div class='ctx'> #define CPT_UC_RID_CN9K_B0   1</div><div class='add'>+#define CPT_UC_RID_CN10K_A   4</div><div class='add'>+#define CPT_UC_RID_CN10K_B   5</div><div class='ctx'> </div><div class='ctx'> static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 					int num_vfs)</div><div class='hunk'>@@ -587,43 +589,22 @@ static int cpt_is_pf_usable(struct otx2_cptpf_dev *cptpf)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cptx_device_reset(struct otx2_cptpf_dev *cptpf, int blkaddr)</div><div class='add'>+static void cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptpf)</div><div class='ctx'> {</div><div class='del'>-	int timeout = 10, ret;</div><div class='del'>-	u64 reg = 0;</div><div class='add'>+	struct otx2_cpt_eng_grps *eng_grps = &amp;cptpf-&gt;eng_grps;</div><div class='add'>+	u64 reg_val = 0x0;</div><div class='ctx'> </div><div class='del'>-	ret = otx2_cpt_write_af_reg(&amp;cptpf-&gt;afpf_mbox, cptpf-&gt;pdev,</div><div class='del'>-				    CPT_AF_BLK_RST, 0x1, blkaddr);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		ret = otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, cptpf-&gt;pdev,</div><div class='del'>-					   CPT_AF_BLK_RST, &amp;reg, blkaddr);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		if (!((reg &gt;&gt; 63) &amp; 0x1))</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		usleep_range(10000, 20000);</div><div class='del'>-		if (timeout-- &lt; 0)</div><div class='del'>-			return -EBUSY;</div><div class='del'>-	} while (1);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int cptpf_device_reset(struct otx2_cptpf_dev *cptpf)</div><div class='del'>-{</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	if (cptpf-&gt;has_cpt1) {</div><div class='del'>-		ret = cptx_device_reset(cptpf, BLKADDR_CPT1);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+	if (is_dev_otx2(pdev)) {</div><div class='add'>+		eng_grps-&gt;rid = pdev-&gt;revision;</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='del'>-	return cptx_device_reset(cptpf, BLKADDR_CPT0);</div><div class='add'>+	otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_CTL, &amp;reg_val,</div><div class='add'>+			     BLKADDR_CPT0);</div><div class='add'>+	if ((cpt_feature_sgv2(pdev) &amp;&amp; (reg_val &amp; BIT_ULL(18))) ||</div><div class='add'>+	    is_dev_cn10ka_ax(pdev))</div><div class='add'>+		eng_grps-&gt;rid = CPT_UC_RID_CN10K_A;</div><div class='add'>+	else if (cpt_feature_sgv2(pdev))</div><div class='add'>+		eng_grps-&gt;rid = CPT_UC_RID_CN10K_B;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptpf)</div><div class='hunk'>@@ -643,10 +624,6 @@ static int cptpf_device_init(struct otx2_cptpf_dev *cptpf)</div><div class='ctx'> </div><div class='ctx'> 	/* check if 'implemented' bit is set for block BLKADDR_CPT1 */</div><div class='ctx'> 	cptpf_check_block_implemented(cptpf);</div><div class='del'>-	/* Reset the CPT PF device */</div><div class='del'>-	ret = cptpf_device_reset(cptpf);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Get number of SE, IE and AE engines */</div><div class='ctx'> 	ret = otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, cptpf-&gt;pdev,</div><div class='hunk'>@@ -701,6 +678,7 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, int num_vfs)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto destroy_flr;</div><div class='ctx'> </div><div class='add'>+	cptpf_get_rid(pdev, cptpf);</div><div class='ctx'> 	/* Get CPT HW capabilities using LOAD_FVC operation. */</div><div class='ctx'> 	ret = otx2_cpt_discover_eng_capabilities(cptpf);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -744,7 +722,7 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct otx2_cptpf_dev *cptpf;</div><div class='del'>-	int err;</div><div class='add'>+	int err, num_vec;</div><div class='ctx'> </div><div class='ctx'> 	cptpf = devm_kzalloc(dev, sizeof(*cptpf), GFP_KERNEL);</div><div class='ctx'> 	if (!cptpf)</div><div class='hunk'>@@ -779,8 +757,13 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto clear_drvdata;</div><div class='ctx'> </div><div class='del'>-	err = pci_alloc_irq_vectors(pdev, RVU_PF_INT_VEC_CNT,</div><div class='del'>-				    RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);</div><div class='add'>+	num_vec = pci_msix_vec_count(cptpf-&gt;pdev);</div><div class='add'>+	if (num_vec &lt;= 0) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto clear_drvdata;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX);</div><div class='ctx'> 	if (err &lt; 0) {</div><div class='ctx'> 		dev_err(dev, "Request for %d msix vectors failed\n",</div><div class='ctx'> 			RVU_PF_INT_VEC_CNT);</div><div class='hunk'>@@ -797,6 +780,7 @@ static int otx2_cptpf_probe(struct pci_dev *pdev,</div><div class='ctx'> 		goto destroy_afpf_mbox;</div><div class='ctx'> </div><div class='ctx'> 	cptpf-&gt;max_vfs = pci_sriov_get_totalvfs(pdev);</div><div class='add'>+	cptpf-&gt;kvf_limits = 1;</div><div class='ctx'> </div><div class='ctx'> 	err = cn10k_cptpf_lmtst_init(cptpf);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -844,6 +828,14 @@ static void otx2_cptpf_remove(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	cptpf_sriov_disable(pdev);</div><div class='ctx'> 	otx2_cpt_unregister_dl(cptpf);</div><div class='add'>+</div><div class='add'>+	/* Cleanup Inline CPT LF's if attached */</div><div class='add'>+	if (cptpf-&gt;lfs.lfs_num)</div><div class='add'>+		otx2_inline_cptlf_cleanup(&amp;cptpf-&gt;lfs);</div><div class='add'>+</div><div class='add'>+	if (cptpf-&gt;cpt1_lfs.lfs_num)</div><div class='add'>+		otx2_inline_cptlf_cleanup(&amp;cptpf-&gt;cpt1_lfs);</div><div class='add'>+</div><div class='ctx'> 	/* Delete sysfs entry created for kernel VF limits */</div><div class='ctx'> 	sysfs_remove_group(&amp;pdev-&gt;dev.kobj, &amp;cptpf_sysfs_group);</div><div class='ctx'> 	/* Cleanup engine groups */</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c<br/>index 480b3720f15a..ec1ac7e836a3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@ static int handle_msg_get_caps(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	rsp-&gt;hdr.sig = OTX2_MBOX_RSP_SIG;</div><div class='ctx'> 	rsp-&gt;hdr.pcifunc = req-&gt;pcifunc;</div><div class='ctx'> 	rsp-&gt;cpt_pf_drv_version = OTX2_CPT_PF_DRV_VERSION;</div><div class='del'>-	rsp-&gt;cpt_revision = cptpf-&gt;pdev-&gt;revision;</div><div class='add'>+	rsp-&gt;cpt_revision = cptpf-&gt;eng_grps.rid;</div><div class='ctx'> 	memcpy(&amp;rsp-&gt;eng_caps, &amp;cptpf-&gt;eng_caps, sizeof(rsp-&gt;eng_caps));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -171,6 +171,8 @@ static int rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, u8 egrp,</div><div class='ctx'> 	nix_req-&gt;hdr.id = MBOX_MSG_NIX_INLINE_IPSEC_CFG;</div><div class='ctx'> 	nix_req-&gt;hdr.sig = OTX2_MBOX_REQ_SIG;</div><div class='ctx'> 	nix_req-&gt;enable = 1;</div><div class='add'>+	nix_req-&gt;credit_th = req-&gt;credit_th;</div><div class='add'>+	nix_req-&gt;bpid = req-&gt;bpid;</div><div class='ctx'> 	if (!req-&gt;credit || req-&gt;credit &gt; OTX2_CPT_INST_QLEN_MSGS)</div><div class='ctx'> 		nix_req-&gt;cpt_credit = OTX2_CPT_INST_QLEN_MSGS - 1;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -197,12 +199,53 @@ static int rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, u8 egrp,</div><div class='ctx'> 	return send_inline_ipsec_inbound_msg(cptpf, req-&gt;sso_pf_func, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int</div><div class='add'>+otx2_inline_cptlf_setup(struct otx2_cptpf_dev *cptpf,</div><div class='add'>+			struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = otx2_cptlf_init(lfs, 1 &lt;&lt; egrp, OTX2_CPT_QUEUE_HI_PRIO, 1);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;cptpf-&gt;pdev-&gt;dev,</div><div class='add'>+			"LF configuration failed for RX inline ipsec.\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get msix offsets for attached LFs */</div><div class='add'>+	ret = otx2_cpt_msix_offset_msg(lfs);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup_lf;</div><div class='add'>+</div><div class='add'>+	/* Register for CPT LF Misc interrupts */</div><div class='add'>+	ret = otx2_cptlf_register_misc_interrupts(lfs);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_irq;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+free_irq:</div><div class='add'>+	otx2_cptlf_unregister_misc_interrupts(lfs);</div><div class='add'>+cleanup_lf:</div><div class='add'>+	otx2_cptlf_shutdown(lfs);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs)</div><div class='add'>+{</div><div class='add'>+	/* Unregister misc interrupt */</div><div class='add'>+	otx2_cptlf_unregister_misc_interrupts(lfs);</div><div class='add'>+</div><div class='add'>+	/* Cleanup LFs */</div><div class='add'>+	otx2_cptlf_shutdown(lfs);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 					     struct mbox_msghdr *req)</div><div class='ctx'> {</div><div class='ctx'> 	struct otx2_cpt_rx_inline_lf_cfg *cfg_req;</div><div class='add'>+	int num_lfs = 1, ret;</div><div class='ctx'> 	u8 egrp;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='ctx'> 	cfg_req = (struct otx2_cpt_rx_inline_lf_cfg *)req;</div><div class='ctx'> 	if (cptpf-&gt;lfs.lfs_num) {</div><div class='hunk'>@@ -223,11 +266,13 @@ static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> </div><div class='ctx'> 	otx2_cptlf_set_dev_info(&amp;cptpf-&gt;lfs, cptpf-&gt;pdev, cptpf-&gt;reg_base,</div><div class='ctx'> 				&amp;cptpf-&gt;afpf_mbox, BLKADDR_CPT0);</div><div class='del'>-	ret = otx2_cptlf_init(&amp;cptpf-&gt;lfs, 1 &lt;&lt; egrp, OTX2_CPT_QUEUE_HI_PRIO,</div><div class='del'>-			      1);</div><div class='add'>+	cptpf-&gt;lfs.global_slot = 0;</div><div class='add'>+	cptpf-&gt;lfs.ctx_ilen_ovrd = cfg_req-&gt;ctx_ilen_valid;</div><div class='add'>+	cptpf-&gt;lfs.ctx_ilen = cfg_req-&gt;ctx_ilen;</div><div class='add'>+</div><div class='add'>+	ret = otx2_inline_cptlf_setup(cptpf, &amp;cptpf-&gt;lfs, egrp, num_lfs);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(&amp;cptpf-&gt;pdev-&gt;dev,</div><div class='del'>-			"LF configuration failed for RX inline ipsec.\n");</div><div class='add'>+		dev_err(&amp;cptpf-&gt;pdev-&gt;dev, "Inline-Ipsec CPT0 LF setup failed.\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -236,11 +281,13 @@ static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 		otx2_cptlf_set_dev_info(&amp;cptpf-&gt;cpt1_lfs, cptpf-&gt;pdev,</div><div class='ctx'> 					cptpf-&gt;reg_base, &amp;cptpf-&gt;afpf_mbox,</div><div class='ctx'> 					BLKADDR_CPT1);</div><div class='del'>-		ret = otx2_cptlf_init(&amp;cptpf-&gt;cpt1_lfs, 1 &lt;&lt; egrp,</div><div class='del'>-				      OTX2_CPT_QUEUE_HI_PRIO, 1);</div><div class='add'>+		cptpf-&gt;cpt1_lfs.global_slot = num_lfs;</div><div class='add'>+		cptpf-&gt;cpt1_lfs.ctx_ilen_ovrd = cfg_req-&gt;ctx_ilen_valid;</div><div class='add'>+		cptpf-&gt;cpt1_lfs.ctx_ilen = cfg_req-&gt;ctx_ilen;</div><div class='add'>+		ret = otx2_inline_cptlf_setup(cptpf, &amp;cptpf-&gt;cpt1_lfs, egrp,</div><div class='add'>+					      num_lfs);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			dev_err(&amp;cptpf-&gt;pdev-&gt;dev,</div><div class='del'>-				"LF configuration failed for RX inline ipsec.\n");</div><div class='add'>+			dev_err(&amp;cptpf-&gt;pdev-&gt;dev, "Inline CPT1 LF setup failed.\n");</div><div class='ctx'> 			goto lf_cleanup;</div><div class='ctx'> 		}</div><div class='ctx'> 		cptpf-&gt;rsrc_req_blkaddr = 0;</div><div class='hunk'>@@ -253,9 +300,9 @@ static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> lf1_cleanup:</div><div class='del'>-	otx2_cptlf_shutdown(&amp;cptpf-&gt;cpt1_lfs);</div><div class='add'>+	otx2_inline_cptlf_cleanup(&amp;cptpf-&gt;cpt1_lfs);</div><div class='ctx'> lf_cleanup:</div><div class='del'>-	otx2_cptlf_shutdown(&amp;cptpf-&gt;lfs);</div><div class='add'>+	otx2_inline_cptlf_cleanup(&amp;cptpf-&gt;lfs);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -410,6 +457,8 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	struct otx2_cptlfs_info *lfs = &amp;cptpf-&gt;lfs;</div><div class='ctx'> 	struct device *dev = &amp;cptpf-&gt;pdev-&gt;dev;</div><div class='ctx'> 	struct cpt_rd_wr_reg_msg *rsp_rd_wr;</div><div class='add'>+	struct msix_offset_rsp *rsp_msix;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (msg-&gt;id &gt;= MBOX_MSG_MAX) {</div><div class='ctx'> 		dev_err(dev, "MBOX msg with unknown ID %d\n", msg-&gt;id);</div><div class='hunk'>@@ -428,6 +477,14 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 		cptpf-&gt;pf_id = (msg-&gt;pcifunc &gt;&gt; RVU_PFVF_PF_SHIFT) &amp;</div><div class='ctx'> 				RVU_PFVF_PF_MASK;</div><div class='ctx'> 		break;</div><div class='add'>+	case MBOX_MSG_MSIX_OFFSET:</div><div class='add'>+		rsp_msix = (struct msix_offset_rsp *) msg;</div><div class='add'>+		for (i = 0; i &lt; rsp_msix-&gt;cptlfs; i++)</div><div class='add'>+			lfs-&gt;lf[i].msix_offset = rsp_msix-&gt;cptlf_msixoff[i];</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; rsp_msix-&gt;cpt1_lfs; i++)</div><div class='add'>+			lfs-&gt;lf[i].msix_offset = rsp_msix-&gt;cpt1_lf_msixoff[i];</div><div class='add'>+		break;</div><div class='ctx'> 	case MBOX_MSG_CPT_RD_WR_REGISTER:</div><div class='ctx'> 		rsp_rd_wr = (struct cpt_rd_wr_reg_msg *)msg;</div><div class='ctx'> 		if (msg-&gt;rc) {</div><div class='hunk'>@@ -449,6 +506,7 @@ static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case MBOX_MSG_CPT_INLINE_IPSEC_CFG:</div><div class='ctx'> 	case MBOX_MSG_NIX_INLINE_IPSEC_CFG:</div><div class='add'>+	case MBOX_MSG_CPT_LF_RESET:</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c<br/>index 1958b797a421..5c9484646172 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c</a></div><div class='hunk'>@@ -16,7 +16,11 @@</div><div class='ctx'> #define LOADFVC_MAJOR_OP 0x01</div><div class='ctx'> #define LOADFVC_MINOR_OP 0x08</div><div class='ctx'> </div><div class='del'>-#define CTX_FLUSH_TIMER_CNT 0xFFFFFF</div><div class='add'>+/*</div><div class='add'>+ * Interval to flush dirty data for next CTX entry. The interval is measured</div><div class='add'>+ * in increments of 10ns(interval time = CTX_FLUSH_TIMER_COUNT * 10ns).</div><div class='add'>+ */</div><div class='add'>+#define CTX_FLUSH_TIMER_CNT 0x2FAF0</div><div class='ctx'> </div><div class='ctx'> struct fw_info_t {</div><div class='ctx'> 	struct list_head ucodes;</div><div class='hunk'>@@ -117,12 +121,10 @@ static char *get_ucode_type_str(int ucode_type)</div><div class='ctx'> </div><div class='ctx'> static int get_ucode_type(struct device *dev,</div><div class='ctx'> 			  struct otx2_cpt_ucode_hdr *ucode_hdr,</div><div class='del'>-			  int *ucode_type)</div><div class='add'>+			  int *ucode_type, u16 rid)</div><div class='ctx'> {</div><div class='del'>-	struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);</div><div class='ctx'> 	char ver_str_prefix[OTX2_CPT_UCODE_VER_STR_SZ];</div><div class='ctx'> 	char tmp_ver_str[OTX2_CPT_UCODE_VER_STR_SZ];</div><div class='del'>-	struct pci_dev *pdev = cptpf-&gt;pdev;</div><div class='ctx'> 	int i, val = 0;</div><div class='ctx'> 	u8 nn;</div><div class='ctx'> </div><div class='hunk'>@@ -130,7 +132,7 @@ static int get_ucode_type(struct device *dev,</div><div class='ctx'> 	for (i = 0; i &lt; strlen(tmp_ver_str); i++)</div><div class='ctx'> 		tmp_ver_str[i] = tolower(tmp_ver_str[i]);</div><div class='ctx'> </div><div class='del'>-	sprintf(ver_str_prefix, "ocpt-%02d", pdev-&gt;revision);</div><div class='add'>+	sprintf(ver_str_prefix, "ocpt-%02d", rid);</div><div class='ctx'> 	if (!strnstr(tmp_ver_str, ver_str_prefix, OTX2_CPT_UCODE_VER_STR_SZ))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -359,7 +361,7 @@ static int cpt_attach_and_enable_cores(struct otx2_cpt_eng_grp_info *eng_grp,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int load_fw(struct device *dev, struct fw_info_t *fw_info,</div><div class='del'>-		   char *filename)</div><div class='add'>+		   char *filename, u16 rid)</div><div class='ctx'> {</div><div class='ctx'> 	struct otx2_cpt_ucode_hdr *ucode_hdr;</div><div class='ctx'> 	struct otx2_cpt_uc_info_t *uc_info;</div><div class='hunk'>@@ -375,7 +377,7 @@ static int load_fw(struct device *dev, struct fw_info_t *fw_info,</div><div class='ctx'> 		goto free_uc_info;</div><div class='ctx'> </div><div class='ctx'> 	ucode_hdr = (struct otx2_cpt_ucode_hdr *)uc_info-&gt;fw-&gt;data;</div><div class='del'>-	ret = get_ucode_type(dev, ucode_hdr, &amp;ucode_type);</div><div class='add'>+	ret = get_ucode_type(dev, ucode_hdr, &amp;ucode_type, rid);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto release_fw;</div><div class='ctx'> </div><div class='hunk'>@@ -389,6 +391,7 @@ static int load_fw(struct device *dev, struct fw_info_t *fw_info,</div><div class='ctx'> 	set_ucode_filename(&amp;uc_info-&gt;ucode, filename);</div><div class='ctx'> 	memcpy(uc_info-&gt;ucode.ver_str, ucode_hdr-&gt;ver_str,</div><div class='ctx'> 	       OTX2_CPT_UCODE_VER_STR_SZ);</div><div class='add'>+	uc_info-&gt;ucode.ver_str[OTX2_CPT_UCODE_VER_STR_SZ] = 0;</div><div class='ctx'> 	uc_info-&gt;ucode.ver_num = ucode_hdr-&gt;ver_num;</div><div class='ctx'> 	uc_info-&gt;ucode.type = ucode_type;</div><div class='ctx'> 	uc_info-&gt;ucode.size = ucode_size;</div><div class='hunk'>@@ -448,7 +451,8 @@ static void print_uc_info(struct fw_info_t *fw_info)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info)</div><div class='add'>+static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info,</div><div class='add'>+			     u16 rid)</div><div class='ctx'> {</div><div class='ctx'> 	char filename[OTX2_CPT_NAME_LENGTH];</div><div class='ctx'> 	char eng_type[8] = {0};</div><div class='hunk'>@@ -462,9 +466,9 @@ static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info)</div><div class='ctx'> 			eng_type[i] = tolower(eng_type[i]);</div><div class='ctx'> </div><div class='ctx'> 		snprintf(filename, sizeof(filename), "mrvl/cpt%02d/%s.out",</div><div class='del'>-			 pdev-&gt;revision, eng_type);</div><div class='add'>+			 rid, eng_type);</div><div class='ctx'> 		/* Request firmware for each engine type */</div><div class='del'>-		ret = load_fw(&amp;pdev-&gt;dev, fw_info, filename);</div><div class='add'>+		ret = load_fw(&amp;pdev-&gt;dev, fw_info, filename, rid);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto release_fw;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1155,7 +1159,7 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	if (eng_grps-&gt;is_grps_created)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='del'>-	ret = cpt_ucode_load_fw(pdev, &amp;fw_info);</div><div class='add'>+	ret = cpt_ucode_load_fw(pdev, &amp;fw_info, eng_grps-&gt;rid);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -1230,14 +1234,16 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	 */</div><div class='ctx'> 	rnm_to_cpt_errata_fixup(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_CTL, &amp;reg_val,</div><div class='add'>+			     BLKADDR_CPT0);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Configure engine group mask to allow context prefetching</div><div class='ctx'> 	 * for the groups and enable random number request, to enable</div><div class='ctx'> 	 * CPT to request random numbers from RNM.</div><div class='ctx'> 	 */</div><div class='add'>+	reg_val |= OTX2_CPT_ALL_ENG_GRPS_MASK &lt;&lt; 3 | BIT_ULL(16);</div><div class='ctx'> 	otx2_cpt_write_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_CTL,</div><div class='del'>-			      OTX2_CPT_ALL_ENG_GRPS_MASK &lt;&lt; 3 | BIT_ULL(16),</div><div class='del'>-			      BLKADDR_CPT0);</div><div class='add'>+			      reg_val, BLKADDR_CPT0);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Set interval to periodically flush dirty data for the next</div><div class='ctx'> 	 * CTX cache entry. Set the interval count to maximum supported</div><div class='hunk'>@@ -1252,10 +1258,12 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 	 * encounters a fault/poison, a rare case may result in</div><div class='ctx'> 	 * unpredictable data being delivered to a CPT engine.</div><div class='ctx'> 	 */</div><div class='del'>-	otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_DIAG, &amp;reg_val,</div><div class='del'>-			     BLKADDR_CPT0);</div><div class='del'>-	otx2_cpt_write_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_DIAG,</div><div class='del'>-			      reg_val | BIT_ULL(24), BLKADDR_CPT0);</div><div class='add'>+	if (cpt_is_errata_38550_exists(pdev)) {</div><div class='add'>+		otx2_cpt_read_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_DIAG,</div><div class='add'>+				     &amp;reg_val, BLKADDR_CPT0);</div><div class='add'>+		otx2_cpt_write_af_reg(&amp;cptpf-&gt;afpf_mbox, pdev, CPT_AF_DIAG,</div><div class='add'>+				      reg_val | BIT_ULL(24), BLKADDR_CPT0);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;eng_grps-&gt;lock);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1412,7 +1420,7 @@ static int create_eng_caps_discovery_grps(struct pci_dev *pdev,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;eng_grps-&gt;lock);</div><div class='del'>-	ret = cpt_ucode_load_fw(pdev, &amp;fw_info);</div><div class='add'>+	ret = cpt_ucode_load_fw(pdev, &amp;fw_info, eng_grps-&gt;rid);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		mutex_unlock(&amp;eng_grps-&gt;lock);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -1686,13 +1694,14 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;fw_info.ucodes);</div><div class='del'>-	ret = load_fw(dev, &amp;fw_info, ucode_filename[0]);</div><div class='add'>+</div><div class='add'>+	ret = load_fw(dev, &amp;fw_info, ucode_filename[0], eng_grps-&gt;rid);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Unable to load firmware %s\n", ucode_filename[0]);</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ucode_idx &gt; 1) {</div><div class='del'>-		ret = load_fw(dev, &amp;fw_info, ucode_filename[1]);</div><div class='add'>+		ret = load_fw(dev, &amp;fw_info, ucode_filename[1], eng_grps-&gt;rid);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "Unable to load firmware %s\n",</div><div class='ctx'> 				ucode_filename[1]);</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h<br/>index e69320a54b5d..365fe8943bd9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h</a></div><div class='hunk'>@@ -73,7 +73,7 @@ struct otx2_cpt_ucode_hdr {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct otx2_cpt_ucode {</div><div class='del'>-	u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/*</div><div class='add'>+	u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ + 1];/*</div><div class='ctx'> 					       * ucode version in readable</div><div class='ctx'> 					       * format</div><div class='ctx'> 					       */</div><div class='hunk'>@@ -150,6 +150,7 @@ struct otx2_cpt_eng_grps {</div><div class='ctx'> 	int engs_num;			/* total number of engines supported */</div><div class='ctx'> 	u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */</div><div class='ctx'> 	bool is_grps_created; /* Is the engine groups are already created */</div><div class='add'>+	u16 rid;</div><div class='ctx'> };</div><div class='ctx'> struct otx2_cptpf_dev;</div><div class='ctx'> int otx2_cpt_init_eng_grps(struct pci_dev *pdev,</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf.h b/drivers/crypto/marvell/octeontx2/otx2_cptvf.h<br/>index 994291e90da1..11ab9af1df15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf.h</a></div><div class='hunk'>@@ -22,6 +22,7 @@ struct otx2_cptvf_dev {</div><div class='ctx'> 	int blkaddr;</div><div class='ctx'> 	void *bbuf_base;</div><div class='ctx'> 	unsigned long cap_flag;</div><div class='add'>+	u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);</div><div class='hunk'>@@ -29,5 +30,6 @@ void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work);</div><div class='ctx'> int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);</div><div class='ctx'> int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);</div><div class='ctx'> int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);</div><div class='add'>+int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf);</div><div class='ctx'> </div><div class='ctx'> #endif /* __OTX2_CPTVF_H */</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c<br/>index e27ddd3c4e55..1604fc58dc13 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> #include "otx2_cptvf.h"</div><div class='ctx'> #include "otx2_cptvf_algs.h"</div><div class='ctx'> #include "otx2_cpt_reqmgr.h"</div><div class='add'>+#include "cn10k_cpt.h"</div><div class='ctx'> </div><div class='ctx'> /* Size of salt in AES GCM mode */</div><div class='ctx'> #define AES_GCM_SALT_SIZE 4</div><div class='hunk'>@@ -384,6 +385,9 @@ static inline int cpt_enc_dec(struct skcipher_request *req, u32 enc)</div><div class='ctx'> 	req_info-&gt;is_trunc_hmac = false;</div><div class='ctx'> 	req_info-&gt;ctrl.s.grp = otx2_cpt_get_kcrypto_eng_grp_num(pdev);</div><div class='ctx'> </div><div class='add'>+	req_info-&gt;req.cptr = ctx-&gt;er_ctx.hw_ctx;</div><div class='add'>+	req_info-&gt;req.cptr_dma = ctx-&gt;er_ctx.cptr_dma;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We perform an asynchronous send and once</div><div class='ctx'> 	 * the request is completed the driver would</div><div class='hunk'>@@ -530,6 +534,8 @@ static int otx2_cpt_enc_dec_init(struct crypto_skcipher *stfm)</div><div class='ctx'> 	struct otx2_cpt_enc_ctx *ctx = crypto_skcipher_ctx(stfm);</div><div class='ctx'> 	struct crypto_tfm *tfm = crypto_skcipher_tfm(stfm);</div><div class='ctx'> 	struct crypto_alg *alg = tfm-&gt;__crt_alg;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	int ret, cpu_num;</div><div class='ctx'> </div><div class='ctx'> 	memset(ctx, 0, sizeof(*ctx));</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -541,6 +547,15 @@ static int otx2_cpt_enc_dec_init(struct crypto_skcipher *stfm)</div><div class='ctx'> 		stfm, sizeof(struct otx2_cpt_req_ctx) +</div><div class='ctx'> 		      sizeof(struct skcipher_request));</div><div class='ctx'> </div><div class='add'>+	ret = get_se_device(&amp;pdev, &amp;cpu_num);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ctx-&gt;pdev = pdev;</div><div class='add'>+	ret = cn10k_cpt_hw_ctx_init(pdev, &amp;ctx-&gt;er_ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	return cpt_skcipher_fallback_init(ctx, alg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -552,6 +567,7 @@ static void otx2_cpt_skcipher_exit(struct crypto_skcipher *tfm)</div><div class='ctx'> 		crypto_free_skcipher(ctx-&gt;fbk_cipher);</div><div class='ctx'> 		ctx-&gt;fbk_cipher = NULL;</div><div class='ctx'> 	}</div><div class='add'>+	cn10k_cpt_hw_ctx_clear(ctx-&gt;pdev, &amp;ctx-&gt;er_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cpt_aead_fallback_init(struct otx2_cpt_aead_ctx *ctx,</div><div class='hunk'>@@ -576,6 +592,8 @@ static int cpt_aead_init(struct crypto_aead *atfm, u8 cipher_type, u8 mac_type)</div><div class='ctx'> 	struct otx2_cpt_aead_ctx *ctx = crypto_aead_ctx_dma(atfm);</div><div class='ctx'> 	struct crypto_tfm *tfm = crypto_aead_tfm(atfm);</div><div class='ctx'> 	struct crypto_alg *alg = tfm-&gt;__crt_alg;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	int ret, cpu_num;</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;cipher_type = cipher_type;</div><div class='ctx'> 	ctx-&gt;mac_type = mac_type;</div><div class='hunk'>@@ -632,6 +650,15 @@ static int cpt_aead_init(struct crypto_aead *atfm, u8 cipher_type, u8 mac_type)</div><div class='ctx'> 	}</div><div class='ctx'> 	crypto_aead_set_reqsize_dma(atfm, sizeof(struct otx2_cpt_req_ctx));</div><div class='ctx'> </div><div class='add'>+	ret = get_se_device(&amp;pdev, &amp;cpu_num);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ctx-&gt;pdev = pdev;</div><div class='add'>+	ret = cn10k_cpt_hw_ctx_init(pdev, &amp;ctx-&gt;er_ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	return cpt_aead_fallback_init(ctx, alg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -694,6 +721,7 @@ static void otx2_cpt_aead_exit(struct crypto_aead *tfm)</div><div class='ctx'> 		crypto_free_aead(ctx-&gt;fbk_cipher);</div><div class='ctx'> 		ctx-&gt;fbk_cipher = NULL;</div><div class='ctx'> 	}</div><div class='add'>+	cn10k_cpt_hw_ctx_clear(ctx-&gt;pdev, &amp;ctx-&gt;er_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int otx2_cpt_aead_gcm_set_authsize(struct crypto_aead *tfm,</div><div class='hunk'>@@ -1299,6 +1327,9 @@ static int cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc)</div><div class='ctx'> 	req_info-&gt;is_enc = enc;</div><div class='ctx'> 	req_info-&gt;is_trunc_hmac = false;</div><div class='ctx'> </div><div class='add'>+	req_info-&gt;req.cptr = ctx-&gt;er_ctx.hw_ctx;</div><div class='add'>+	req_info-&gt;req.cptr_dma = ctx-&gt;er_ctx.cptr_dma;</div><div class='add'>+</div><div class='ctx'> 	switch (reg_type) {</div><div class='ctx'> 	case OTX2_CPT_AEAD_ENC_DEC_REQ:</div><div class='ctx'> 		status = create_aead_input_list(req, enc);</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h b/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h<br/>index f04184bd1744..d29f84f01cee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.h</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> #include &lt;crypto/skcipher.h&gt;</div><div class='ctx'> #include &lt;crypto/aead.h&gt;</div><div class='ctx'> #include "otx2_cpt_common.h"</div><div class='add'>+#include "cn10k_cpt.h"</div><div class='ctx'> </div><div class='ctx'> #define OTX2_CPT_MAX_ENC_KEY_SIZE    32</div><div class='ctx'> #define OTX2_CPT_MAX_HASH_KEY_SIZE   64</div><div class='hunk'>@@ -123,6 +124,8 @@ struct otx2_cpt_enc_ctx {</div><div class='ctx'> 	u8 key_type;</div><div class='ctx'> 	u8 enc_align_len;</div><div class='ctx'> 	struct crypto_skcipher *fbk_cipher;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	struct cn10k_cpt_errata_ctx er_ctx;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> union otx2_cpt_offset_ctrl {</div><div class='hunk'>@@ -161,6 +164,8 @@ struct otx2_cpt_aead_ctx {</div><div class='ctx'> 	struct crypto_shash *hashalg;</div><div class='ctx'> 	struct otx2_cpt_sdesc *sdesc;</div><div class='ctx'> 	struct crypto_aead *fbk_cipher;</div><div class='add'>+	struct cn10k_cpt_errata_ctx er_ctx;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='ctx'> 	u8 *ipad;</div><div class='ctx'> 	u8 *opad;</div><div class='ctx'> 	u32 enc_key_len;</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c<br/>index bac729c885f9..527d34cc258b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c</a></div><div class='hunk'>@@ -246,11 +246,15 @@ static void cptvf_lf_shutdown(struct otx2_cptlfs_info *lfs)</div><div class='ctx'> 	/* Unregister crypto algorithms */</div><div class='ctx'> 	otx2_cpt_crypto_exit(lfs-&gt;pdev, THIS_MODULE);</div><div class='ctx'> 	/* Unregister LFs interrupts */</div><div class='del'>-	otx2_cptlf_unregister_interrupts(lfs);</div><div class='add'>+	otx2_cptlf_unregister_misc_interrupts(lfs);</div><div class='add'>+	otx2_cptlf_unregister_done_interrupts(lfs);</div><div class='ctx'> 	/* Cleanup LFs software side */</div><div class='ctx'> 	lf_sw_cleanup(lfs);</div><div class='add'>+	/* Free instruction queues */</div><div class='add'>+	otx2_cpt_free_instruction_queues(lfs);</div><div class='ctx'> 	/* Send request to detach LFs */</div><div class='ctx'> 	otx2_cpt_detach_rsrcs_msg(lfs);</div><div class='add'>+	lfs-&gt;lfs_num = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)</div><div class='hunk'>@@ -277,8 +281,7 @@ static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	lfs_num = cptvf-&gt;lfs.kvf_limits ? cptvf-&gt;lfs.kvf_limits :</div><div class='del'>-		  num_online_cpus();</div><div class='add'>+	lfs_num = cptvf-&gt;lfs.kvf_limits;</div><div class='ctx'> </div><div class='ctx'> 	otx2_cptlf_set_dev_info(lfs, cptvf-&gt;pdev, cptvf-&gt;reg_base,</div><div class='ctx'> 				&amp;cptvf-&gt;pfvf_mbox, cptvf-&gt;blkaddr);</div><div class='hunk'>@@ -298,7 +301,11 @@ static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> 		goto cleanup_lf;</div><div class='ctx'> </div><div class='ctx'> 	/* Register LFs interrupts */</div><div class='del'>-	ret = otx2_cptlf_register_interrupts(lfs);</div><div class='add'>+	ret = otx2_cptlf_register_misc_interrupts(lfs);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto cleanup_lf_sw;</div><div class='add'>+</div><div class='add'>+	ret = otx2_cptlf_register_done_interrupts(lfs);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto cleanup_lf_sw;</div><div class='ctx'> </div><div class='hunk'>@@ -319,7 +326,8 @@ static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> disable_irqs:</div><div class='ctx'> 	otx2_cptlf_free_irqs_affinity(lfs);</div><div class='ctx'> unregister_intr:</div><div class='del'>-	otx2_cptlf_unregister_interrupts(lfs);</div><div class='add'>+	otx2_cptlf_unregister_misc_interrupts(lfs);</div><div class='add'>+	otx2_cptlf_unregister_done_interrupts(lfs);</div><div class='ctx'> cleanup_lf_sw:</div><div class='ctx'> 	lf_sw_cleanup(lfs);</div><div class='ctx'> cleanup_lf:</div><div class='hunk'>@@ -380,6 +388,17 @@ static int otx2_cptvf_probe(struct pci_dev *pdev,</div><div class='ctx'> 		goto destroy_pfvf_mbox;</div><div class='ctx'> </div><div class='ctx'> 	cptvf-&gt;blkaddr = BLKADDR_CPT0;</div><div class='add'>+</div><div class='add'>+	cptvf_hw_ops_get(cptvf);</div><div class='add'>+</div><div class='add'>+	ret = otx2_cptvf_send_caps_msg(cptvf);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Couldn't get CPT engine capabilities.\n");</div><div class='add'>+		goto unregister_interrupts;</div><div class='add'>+	}</div><div class='add'>+	if (cptvf-&gt;eng_caps[OTX2_CPT_SE_TYPES] &amp; BIT_ULL(35))</div><div class='add'>+		cptvf-&gt;lfs.ops-&gt;cpt_sg_info_create = cn10k_sgv2_info_create;</div><div class='add'>+</div><div class='ctx'> 	/* Initialize CPT LFs */</div><div class='ctx'> 	ret = cptvf_lf_init(cptvf);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c<br/>index 75c403f2b1d9..d9fa5f6e204d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c</a></div><div class='hunk'>@@ -72,6 +72,7 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,</div><div class='ctx'> 	struct otx2_cptlfs_info *lfs = &amp;cptvf-&gt;lfs;</div><div class='ctx'> 	struct otx2_cpt_kvf_limits_rsp *rsp_limits;</div><div class='ctx'> 	struct otx2_cpt_egrp_num_rsp *rsp_grp;</div><div class='add'>+	struct otx2_cpt_caps_rsp *eng_caps;</div><div class='ctx'> 	struct cpt_rd_wr_reg_msg *rsp_reg;</div><div class='ctx'> 	struct msix_offset_rsp *rsp_msix;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -127,6 +128,13 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf,</div><div class='ctx'> 		rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;</div><div class='ctx'> 		cptvf-&gt;lfs.kvf_limits = rsp_limits-&gt;kvf_limits;</div><div class='ctx'> 		break;</div><div class='add'>+	case MBOX_MSG_GET_CAPS:</div><div class='add'>+		eng_caps = (struct otx2_cpt_caps_rsp *)msg;</div><div class='add'>+		memcpy(cptvf-&gt;eng_caps, eng_caps-&gt;eng_caps,</div><div class='add'>+		       sizeof(cptvf-&gt;eng_caps));</div><div class='add'>+		break;</div><div class='add'>+	case MBOX_MSG_CPT_LF_RESET:</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(&amp;cptvf-&gt;pdev-&gt;dev, "Unsupported msg %d received.\n",</div><div class='ctx'> 			msg-&gt;id);</div><div class='hunk'>@@ -205,3 +213,23 @@ int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf)</div><div class='ctx'> </div><div class='ctx'> 	return otx2_cpt_send_mbox_msg(mbox, pdev);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf)</div><div class='add'>+{</div><div class='add'>+	struct otx2_mbox *mbox = &amp;cptvf-&gt;pfvf_mbox;</div><div class='add'>+	struct pci_dev *pdev = cptvf-&gt;pdev;</div><div class='add'>+	struct mbox_msghdr *req;</div><div class='add'>+</div><div class='add'>+	req = (struct mbox_msghdr *)</div><div class='add'>+	      otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),</div><div class='add'>+				      sizeof(struct otx2_cpt_caps_rsp));</div><div class='add'>+	if (!req) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "RVU MBOX failed to get message.\n");</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+	req-&gt;id = MBOX_MSG_GET_CAPS;</div><div class='add'>+	req-&gt;sig = OTX2_MBOX_REQ_SIG;</div><div class='add'>+	req-&gt;pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf-&gt;vf_id, 0);</div><div class='add'>+</div><div class='add'>+	return otx2_cpt_send_mbox_msg(mbox, pdev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c<br/>index 811ded72ce5f..5387c68f3c9d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c</a></div><div class='hunk'>@@ -4,9 +4,6 @@</div><div class='ctx'> #include "otx2_cptvf.h"</div><div class='ctx'> #include "otx2_cpt_common.h"</div><div class='ctx'> </div><div class='del'>-/* SG list header size in bytes */</div><div class='del'>-#define SG_LIST_HDR_SIZE	8</div><div class='del'>-</div><div class='ctx'> /* Default timeout when waiting for free pending entry in us */</div><div class='ctx'> #define CPT_PENTRY_TIMEOUT	1000</div><div class='ctx'> #define CPT_PENTRY_STEP		50</div><div class='hunk'>@@ -26,9 +23,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("Gather list size %d\n", req-&gt;in_cnt);</div><div class='ctx'> 	for (i = 0; i &lt; req-&gt;in_cnt; i++) {</div><div class='del'>-		pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,</div><div class='add'>+		pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,</div><div class='ctx'> 			 req-&gt;in[i].size, req-&gt;in[i].vptr,</div><div class='del'>-			 (void *) req-&gt;in[i].dma_addr);</div><div class='add'>+			 req-&gt;in[i].dma_addr);</div><div class='ctx'> 		pr_debug("Buffer hexdump (%d bytes)\n",</div><div class='ctx'> 			 req-&gt;in[i].size);</div><div class='ctx'> 		print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1,</div><div class='hunk'>@@ -36,9 +33,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev,</div><div class='ctx'> 	}</div><div class='ctx'> 	pr_debug("Scatter list size %d\n", req-&gt;out_cnt);</div><div class='ctx'> 	for (i = 0; i &lt; req-&gt;out_cnt; i++) {</div><div class='del'>-		pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,</div><div class='add'>+		pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,</div><div class='ctx'> 			 req-&gt;out[i].size, req-&gt;out[i].vptr,</div><div class='del'>-			 (void *) req-&gt;out[i].dma_addr);</div><div class='add'>+			 req-&gt;out[i].dma_addr);</div><div class='ctx'> 		pr_debug("Buffer hexdump (%d bytes)\n", req-&gt;out[i].size);</div><div class='ctx'> 		print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1,</div><div class='ctx'> 				     req-&gt;out[i].vptr, req-&gt;out[i].size, false);</div><div class='hunk'>@@ -84,149 +81,6 @@ static inline void free_pentry(struct otx2_cpt_pending_entry *pentry)</div><div class='ctx'> 	pentry-&gt;busy = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int setup_sgio_components(struct pci_dev *pdev,</div><div class='del'>-					struct otx2_cpt_buf_ptr *list,</div><div class='del'>-					int buf_count, u8 *buffer)</div><div class='del'>-{</div><div class='del'>-	struct otx2_cpt_sglist_component *sg_ptr = NULL;</div><div class='del'>-	int ret = 0, i, j;</div><div class='del'>-	int components;</div><div class='del'>-</div><div class='del'>-	if (unlikely(!list)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Input list pointer is NULL\n");</div><div class='del'>-		return -EFAULT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; buf_count; i++) {</div><div class='del'>-		if (unlikely(!list[i].vptr))</div><div class='del'>-			continue;</div><div class='del'>-		list[i].dma_addr = dma_map_single(&amp;pdev-&gt;dev, list[i].vptr,</div><div class='del'>-						  list[i].size,</div><div class='del'>-						  DMA_BIDIRECTIONAL);</div><div class='del'>-		if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, list[i].dma_addr))) {</div><div class='del'>-			dev_err(&amp;pdev-&gt;dev, "Dma mapping failed\n");</div><div class='del'>-			ret = -EIO;</div><div class='del'>-			goto sg_cleanup;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	components = buf_count / 4;</div><div class='del'>-	sg_ptr = (struct otx2_cpt_sglist_component *)buffer;</div><div class='del'>-	for (i = 0; i &lt; components; i++) {</div><div class='del'>-		sg_ptr-&gt;len0 = cpu_to_be16(list[i * 4 + 0].size);</div><div class='del'>-		sg_ptr-&gt;len1 = cpu_to_be16(list[i * 4 + 1].size);</div><div class='del'>-		sg_ptr-&gt;len2 = cpu_to_be16(list[i * 4 + 2].size);</div><div class='del'>-		sg_ptr-&gt;len3 = cpu_to_be16(list[i * 4 + 3].size);</div><div class='del'>-		sg_ptr-&gt;ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);</div><div class='del'>-		sg_ptr-&gt;ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);</div><div class='del'>-		sg_ptr-&gt;ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);</div><div class='del'>-		sg_ptr-&gt;ptr3 = cpu_to_be64(list[i * 4 + 3].dma_addr);</div><div class='del'>-		sg_ptr++;</div><div class='del'>-	}</div><div class='del'>-	components = buf_count % 4;</div><div class='del'>-</div><div class='del'>-	switch (components) {</div><div class='del'>-	case 3:</div><div class='del'>-		sg_ptr-&gt;len2 = cpu_to_be16(list[i * 4 + 2].size);</div><div class='del'>-		sg_ptr-&gt;ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);</div><div class='del'>-		fallthrough;</div><div class='del'>-	case 2:</div><div class='del'>-		sg_ptr-&gt;len1 = cpu_to_be16(list[i * 4 + 1].size);</div><div class='del'>-		sg_ptr-&gt;ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);</div><div class='del'>-		fallthrough;</div><div class='del'>-	case 1:</div><div class='del'>-		sg_ptr-&gt;len0 = cpu_to_be16(list[i * 4 + 0].size);</div><div class='del'>-		sg_ptr-&gt;ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-	return ret;</div><div class='del'>-</div><div class='del'>-sg_cleanup:</div><div class='del'>-	for (j = 0; j &lt; i; j++) {</div><div class='del'>-		if (list[j].dma_addr) {</div><div class='del'>-			dma_unmap_single(&amp;pdev-&gt;dev, list[j].dma_addr,</div><div class='del'>-					 list[j].size, DMA_BIDIRECTIONAL);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		list[j].dma_addr = 0;</div><div class='del'>-	}</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline struct otx2_cpt_inst_info *info_create(struct pci_dev *pdev,</div><div class='del'>-					      struct otx2_cpt_req_info *req,</div><div class='del'>-					      gfp_t gfp)</div><div class='del'>-{</div><div class='del'>-	int align = OTX2_CPT_DMA_MINALIGN;</div><div class='del'>-	struct otx2_cpt_inst_info *info;</div><div class='del'>-	u32 dlen, align_dlen, info_len;</div><div class='del'>-	u16 g_sz_bytes, s_sz_bytes;</div><div class='del'>-	u32 total_mem_len;</div><div class='del'>-</div><div class='del'>-	if (unlikely(req-&gt;in_cnt &gt; OTX2_CPT_MAX_SG_IN_CNT ||</div><div class='del'>-		     req-&gt;out_cnt &gt; OTX2_CPT_MAX_SG_OUT_CNT)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Error too many sg components\n");</div><div class='del'>-		return NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	g_sz_bytes = ((req-&gt;in_cnt + 3) / 4) *</div><div class='del'>-		      sizeof(struct otx2_cpt_sglist_component);</div><div class='del'>-	s_sz_bytes = ((req-&gt;out_cnt + 3) / 4) *</div><div class='del'>-		      sizeof(struct otx2_cpt_sglist_component);</div><div class='del'>-</div><div class='del'>-	dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;</div><div class='del'>-	align_dlen = ALIGN(dlen, align);</div><div class='del'>-	info_len = ALIGN(sizeof(*info), align);</div><div class='del'>-	total_mem_len = align_dlen + info_len + sizeof(union otx2_cpt_res_s);</div><div class='del'>-</div><div class='del'>-	info = kzalloc(total_mem_len, gfp);</div><div class='del'>-	if (unlikely(!info))</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	info-&gt;dlen = dlen;</div><div class='del'>-	info-&gt;in_buffer = (u8 *)info + info_len;</div><div class='del'>-</div><div class='del'>-	((u16 *)info-&gt;in_buffer)[0] = req-&gt;out_cnt;</div><div class='del'>-	((u16 *)info-&gt;in_buffer)[1] = req-&gt;in_cnt;</div><div class='del'>-	((u16 *)info-&gt;in_buffer)[2] = 0;</div><div class='del'>-	((u16 *)info-&gt;in_buffer)[3] = 0;</div><div class='del'>-	cpu_to_be64s((u64 *)info-&gt;in_buffer);</div><div class='del'>-</div><div class='del'>-	/* Setup gather (input) components */</div><div class='del'>-	if (setup_sgio_components(pdev, req-&gt;in, req-&gt;in_cnt,</div><div class='del'>-				  &amp;info-&gt;in_buffer[8])) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to setup gather list\n");</div><div class='del'>-		goto destroy_info;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (setup_sgio_components(pdev, req-&gt;out, req-&gt;out_cnt,</div><div class='del'>-				  &amp;info-&gt;in_buffer[8 + g_sz_bytes])) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to setup scatter list\n");</div><div class='del'>-		goto destroy_info;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	info-&gt;dma_len = total_mem_len - info_len;</div><div class='del'>-	info-&gt;dptr_baddr = dma_map_single(&amp;pdev-&gt;dev, info-&gt;in_buffer,</div><div class='del'>-					  info-&gt;dma_len, DMA_BIDIRECTIONAL);</div><div class='del'>-	if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, info-&gt;dptr_baddr))) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "DMA Mapping failed for cpt req\n");</div><div class='del'>-		goto destroy_info;</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * Get buffer for union otx2_cpt_res_s response</div><div class='del'>-	 * structure and its physical address</div><div class='del'>-	 */</div><div class='del'>-	info-&gt;completion_addr = info-&gt;in_buffer + align_dlen;</div><div class='del'>-	info-&gt;comp_baddr = info-&gt;dptr_baddr + align_dlen;</div><div class='del'>-</div><div class='del'>-	return info;</div><div class='del'>-</div><div class='del'>-destroy_info:</div><div class='del'>-	otx2_cpt_info_destroy(pdev, info);</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='ctx'> 			   struct otx2_cpt_pending_queue *pqueue,</div><div class='ctx'> 			   struct otx2_cptlf_info *lf)</div><div class='hunk'>@@ -247,7 +101,7 @@ static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='ctx'> 	if (unlikely(!otx2_cptlf_started(lf-&gt;lfs)))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	info = info_create(pdev, req, gfp);</div><div class='add'>+	info = lf-&gt;lfs-&gt;ops-&gt;cpt_sg_info_create(pdev, req, gfp);</div><div class='ctx'> 	if (unlikely(!info)) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "Setting up cpt inst info failed");</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -303,9 +157,9 @@ static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_info *req,</div><div class='ctx'> </div><div class='ctx'> 	/* 64-bit swap for microcode data reads, not needed for addresses*/</div><div class='ctx'> 	cpu_to_be64s(&amp;iq_cmd.cmd.u);</div><div class='del'>-	iq_cmd.dptr = info-&gt;dptr_baddr;</div><div class='del'>-	iq_cmd.rptr = 0;</div><div class='del'>-	iq_cmd.cptr.u = 0;</div><div class='add'>+	iq_cmd.dptr = info-&gt;dptr_baddr | info-&gt;gthr_sz &lt;&lt; 60;</div><div class='add'>+	iq_cmd.rptr = info-&gt;rptr_baddr | info-&gt;sctr_sz &lt;&lt; 60;</div><div class='add'>+	iq_cmd.cptr.s.cptr = cpt_req-&gt;cptr_dma;</div><div class='ctx'> 	iq_cmd.cptr.s.grp = ctrl-&gt;s.grp;</div><div class='ctx'> </div><div class='ctx'> 	/* Fill in the CPT_INST_S type command for HW interpretation */</div><div class='head'>diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c<br/>index caea98622c33..7a3083debc2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/n2_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/n2_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/n2_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/n2_core.c</a></div><div class='hunk'>@@ -1121,19 +1121,6 @@ static const struct n2_skcipher_tmpl skcipher_tmpls[] = {</div><div class='ctx'> 			.decrypt	= n2_decrypt_chaining,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='del'>-	{	.name		= "cfb(des)",</div><div class='del'>-		.drv_name	= "cfb-des",</div><div class='del'>-		.block_size	= DES_BLOCK_SIZE,</div><div class='del'>-		.enc_type	= (ENC_TYPE_ALG_DES |</div><div class='del'>-				   ENC_TYPE_CHAINING_CFB),</div><div class='del'>-		.skcipher	= {</div><div class='del'>-			.min_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.max_keysize	= DES_KEY_SIZE,</div><div class='del'>-			.setkey		= n2_des_setkey,</div><div class='del'>-			.encrypt	= n2_encrypt_chaining,</div><div class='del'>-			.decrypt	= n2_decrypt_chaining,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='ctx'> </div><div class='ctx'> 	/* 3DES: ECB CBC and CFB are supported */</div><div class='ctx'> 	{	.name		= "ecb(des3_ede)",</div><div class='hunk'>@@ -1163,19 +1150,7 @@ static const struct n2_skcipher_tmpl skcipher_tmpls[] = {</div><div class='ctx'> 			.decrypt	= n2_decrypt_chaining,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='del'>-	{	.name		= "cfb(des3_ede)",</div><div class='del'>-		.drv_name	= "cfb-3des",</div><div class='del'>-		.block_size	= DES_BLOCK_SIZE,</div><div class='del'>-		.enc_type	= (ENC_TYPE_ALG_3DES |</div><div class='del'>-				   ENC_TYPE_CHAINING_CFB),</div><div class='del'>-		.skcipher	= {</div><div class='del'>-			.min_keysize	= 3 * DES_KEY_SIZE,</div><div class='del'>-			.max_keysize	= 3 * DES_KEY_SIZE,</div><div class='del'>-			.setkey		= n2_3des_setkey,</div><div class='del'>-			.encrypt	= n2_encrypt_chaining,</div><div class='del'>-			.decrypt	= n2_decrypt_chaining,</div><div class='del'>-		},</div><div class='del'>-	},</div><div class='add'>+</div><div class='ctx'> 	/* AES: ECB CBC and CTR are supported */</div><div class='ctx'> 	{	.name		= "ecb(aes)",</div><div class='ctx'> 		.drv_name	= "ecb-aes",</div><div class='hunk'>@@ -1382,8 +1357,12 @@ static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)</div><div class='ctx'> 	ahash-&gt;setkey = n2_hmac_async_setkey;</div><div class='ctx'> </div><div class='ctx'> 	base = &amp;ahash-&gt;halg.base;</div><div class='del'>-	snprintf(base-&gt;cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p-&gt;child_alg);</div><div class='del'>-	snprintf(base-&gt;cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p-&gt;child_alg);</div><div class='add'>+	if (snprintf(base-&gt;cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)",</div><div class='add'>+		     p-&gt;child_alg) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		goto out_free_p;</div><div class='add'>+	if (snprintf(base-&gt;cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2",</div><div class='add'>+		     p-&gt;child_alg) &gt;= CRYPTO_MAX_ALG_NAME)</div><div class='add'>+		goto out_free_p;</div><div class='ctx'> </div><div class='ctx'> 	base-&gt;cra_ctxsize = sizeof(struct n2_hmac_ctx);</div><div class='ctx'> 	base-&gt;cra_init = n2_hmac_cra_init;</div><div class='hunk'>@@ -1394,6 +1373,7 @@ static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		pr_err("%s alg registration failed\n", base-&gt;cra_name);</div><div class='ctx'> 		list_del(&amp;p-&gt;derived.entry);</div><div class='add'>+out_free_p:</div><div class='ctx'> 		kfree(p);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		pr_info("%s alg registered\n", base-&gt;cra_name);</div><div class='head'>diff --git a/drivers/crypto/rockchip/rk3288_crypto_skcipher.c b/drivers/crypto/rockchip/rk3288_crypto_skcipher.c<br/>index da95747d973f..9393e10671c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/rockchip/rk3288_crypto_skcipher.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/rockchip/rk3288_crypto_skcipher.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/rockchip/rk3288_crypto_skcipher.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/rockchip/rk3288_crypto_skcipher.c</a></div><div class='hunk'>@@ -445,8 +445,8 @@ static int rk_cipher_tfm_init(struct crypto_skcipher *tfm)</div><div class='ctx'> 		return PTR_ERR(ctx-&gt;fallback_tfm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct rk_cipher_rctx) +</div><div class='del'>-		crypto_skcipher_reqsize(ctx-&gt;fallback_tfm);</div><div class='add'>+	crypto_skcipher_set_reqsize(tfm, sizeof(struct rk_cipher_rctx) +</div><div class='add'>+				    crypto_skcipher_reqsize(ctx-&gt;fallback_tfm));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c<br/>index 6846a8429574..78a4930c6480 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/sa2ul.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/sa2ul.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/sa2ul.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/sa2ul.c</a></div><div class='hunk'>@@ -1869,9 +1869,8 @@ static int sa_aead_setkey(struct crypto_aead *authenc,</div><div class='ctx'> 	crypto_aead_set_flags(ctx-&gt;fallback.aead,</div><div class='ctx'> 			      crypto_aead_get_flags(authenc) &amp;</div><div class='ctx'> 			      CRYPTO_TFM_REQ_MASK);</div><div class='del'>-	crypto_aead_setkey(ctx-&gt;fallback.aead, key, keylen);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return crypto_aead_setkey(ctx-&gt;fallback.aead, key, keylen);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sa_aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)</div><div class='head'>diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c<br/>index 02065131c300..3423b5cde1c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/sahara.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/sahara.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/sahara.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/sahara.c</a></div><div class='hunk'>@@ -15,6 +15,7 @@</div><div class='ctx'> #include &lt;crypto/internal/hash.h&gt;</div><div class='ctx'> #include &lt;crypto/internal/skcipher.h&gt;</div><div class='ctx'> #include &lt;crypto/scatterwalk.h&gt;</div><div class='add'>+#include &lt;crypto/engine.h&gt;</div><div class='ctx'> #include &lt;crypto/sha1.h&gt;</div><div class='ctx'> #include &lt;crypto/sha2.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -24,106 +25,101 @@</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/kthread.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> </div><div class='del'>-#define SHA_BUFFER_LEN		PAGE_SIZE</div><div class='del'>-#define SAHARA_MAX_SHA_BLOCK_SIZE	SHA256_BLOCK_SIZE</div><div class='del'>-</div><div class='del'>-#define SAHARA_NAME "sahara"</div><div class='del'>-#define SAHARA_VERSION_3	3</div><div class='del'>-#define SAHARA_VERSION_4	4</div><div class='del'>-#define SAHARA_TIMEOUT_MS	1000</div><div class='del'>-#define SAHARA_MAX_HW_DESC	2</div><div class='del'>-#define SAHARA_MAX_HW_LINK	20</div><div class='del'>-</div><div class='del'>-#define FLAGS_MODE_MASK		0x000f</div><div class='del'>-#define FLAGS_ENCRYPT		BIT(0)</div><div class='del'>-#define FLAGS_CBC		BIT(1)</div><div class='del'>-#define FLAGS_NEW_KEY		BIT(3)</div><div class='del'>-</div><div class='del'>-#define SAHARA_HDR_BASE			0x00800000</div><div class='del'>-#define SAHARA_HDR_SKHA_ALG_AES	0</div><div class='del'>-#define SAHARA_HDR_SKHA_OP_ENC		(1 &lt;&lt; 2)</div><div class='del'>-#define SAHARA_HDR_SKHA_MODE_ECB	(0 &lt;&lt; 3)</div><div class='del'>-#define SAHARA_HDR_SKHA_MODE_CBC	(1 &lt;&lt; 3)</div><div class='del'>-#define SAHARA_HDR_FORM_DATA		(5 &lt;&lt; 16)</div><div class='del'>-#define SAHARA_HDR_FORM_KEY		(8 &lt;&lt; 16)</div><div class='del'>-#define SAHARA_HDR_LLO			(1 &lt;&lt; 24)</div><div class='del'>-#define SAHARA_HDR_CHA_SKHA		(1 &lt;&lt; 28)</div><div class='del'>-#define SAHARA_HDR_CHA_MDHA		(2 &lt;&lt; 28)</div><div class='del'>-#define SAHARA_HDR_PARITY_BIT		(1 &lt;&lt; 31)</div><div class='del'>-</div><div class='del'>-#define SAHARA_HDR_MDHA_SET_MODE_MD_KEY	0x20880000</div><div class='del'>-#define SAHARA_HDR_MDHA_SET_MODE_HASH	0x208D0000</div><div class='del'>-#define SAHARA_HDR_MDHA_HASH		0xA0850000</div><div class='del'>-#define SAHARA_HDR_MDHA_STORE_DIGEST	0x20820000</div><div class='del'>-#define SAHARA_HDR_MDHA_ALG_SHA1	0</div><div class='del'>-#define SAHARA_HDR_MDHA_ALG_MD5		1</div><div class='del'>-#define SAHARA_HDR_MDHA_ALG_SHA256	2</div><div class='del'>-#define SAHARA_HDR_MDHA_ALG_SHA224	3</div><div class='del'>-#define SAHARA_HDR_MDHA_PDATA		(1 &lt;&lt; 2)</div><div class='del'>-#define SAHARA_HDR_MDHA_HMAC		(1 &lt;&lt; 3)</div><div class='del'>-#define SAHARA_HDR_MDHA_INIT		(1 &lt;&lt; 5)</div><div class='del'>-#define SAHARA_HDR_MDHA_IPAD		(1 &lt;&lt; 6)</div><div class='del'>-#define SAHARA_HDR_MDHA_OPAD		(1 &lt;&lt; 7)</div><div class='del'>-#define SAHARA_HDR_MDHA_SWAP		(1 &lt;&lt; 8)</div><div class='del'>-#define SAHARA_HDR_MDHA_MAC_FULL	(1 &lt;&lt; 9)</div><div class='del'>-#define SAHARA_HDR_MDHA_SSL		(1 &lt;&lt; 10)</div><div class='del'>-</div><div class='del'>-/* SAHARA can only process one request at a time */</div><div class='del'>-#define SAHARA_QUEUE_LENGTH	1</div><div class='del'>-</div><div class='del'>-#define SAHARA_REG_VERSION	0x00</div><div class='del'>-#define SAHARA_REG_DAR		0x04</div><div class='del'>-#define SAHARA_REG_CONTROL	0x08</div><div class='del'>-#define		SAHARA_CONTROL_SET_THROTTLE(x)	(((x) &amp; 0xff) &lt;&lt; 24)</div><div class='del'>-#define		SAHARA_CONTROL_SET_MAXBURST(x)	(((x) &amp; 0xff) &lt;&lt; 16)</div><div class='del'>-#define		SAHARA_CONTROL_RNG_AUTORSD	(1 &lt;&lt; 7)</div><div class='del'>-#define		SAHARA_CONTROL_ENABLE_INT	(1 &lt;&lt; 4)</div><div class='del'>-#define SAHARA_REG_CMD		0x0C</div><div class='del'>-#define		SAHARA_CMD_RESET		(1 &lt;&lt; 0)</div><div class='del'>-#define		SAHARA_CMD_CLEAR_INT		(1 &lt;&lt; 8)</div><div class='del'>-#define		SAHARA_CMD_CLEAR_ERR		(1 &lt;&lt; 9)</div><div class='del'>-#define		SAHARA_CMD_SINGLE_STEP		(1 &lt;&lt; 10)</div><div class='del'>-#define		SAHARA_CMD_MODE_BATCH		(1 &lt;&lt; 16)</div><div class='del'>-#define		SAHARA_CMD_MODE_DEBUG		(1 &lt;&lt; 18)</div><div class='del'>-#define	SAHARA_REG_STATUS	0x10</div><div class='del'>-#define		SAHARA_STATUS_GET_STATE(x)	((x) &amp; 0x7)</div><div class='del'>-#define			SAHARA_STATE_IDLE	0</div><div class='del'>-#define			SAHARA_STATE_BUSY	1</div><div class='del'>-#define			SAHARA_STATE_ERR	2</div><div class='del'>-#define			SAHARA_STATE_FAULT	3</div><div class='del'>-#define			SAHARA_STATE_COMPLETE	4</div><div class='del'>-#define			SAHARA_STATE_COMP_FLAG	(1 &lt;&lt; 2)</div><div class='del'>-#define		SAHARA_STATUS_DAR_FULL		(1 &lt;&lt; 3)</div><div class='del'>-#define		SAHARA_STATUS_ERROR		(1 &lt;&lt; 4)</div><div class='del'>-#define		SAHARA_STATUS_SECURE		(1 &lt;&lt; 5)</div><div class='del'>-#define		SAHARA_STATUS_FAIL		(1 &lt;&lt; 6)</div><div class='del'>-#define		SAHARA_STATUS_INIT		(1 &lt;&lt; 7)</div><div class='del'>-#define		SAHARA_STATUS_RNG_RESEED	(1 &lt;&lt; 8)</div><div class='del'>-#define		SAHARA_STATUS_ACTIVE_RNG	(1 &lt;&lt; 9)</div><div class='del'>-#define		SAHARA_STATUS_ACTIVE_MDHA	(1 &lt;&lt; 10)</div><div class='del'>-#define		SAHARA_STATUS_ACTIVE_SKHA	(1 &lt;&lt; 11)</div><div class='del'>-#define		SAHARA_STATUS_MODE_BATCH	(1 &lt;&lt; 16)</div><div class='del'>-#define		SAHARA_STATUS_MODE_DEDICATED	(1 &lt;&lt; 17)</div><div class='del'>-#define		SAHARA_STATUS_MODE_DEBUG	(1 &lt;&lt; 18)</div><div class='del'>-#define		SAHARA_STATUS_GET_ISTATE(x)	(((x) &gt;&gt; 24) &amp; 0xff)</div><div class='del'>-#define SAHARA_REG_ERRSTATUS	0x14</div><div class='del'>-#define		SAHARA_ERRSTATUS_GET_SOURCE(x)	((x) &amp; 0xf)</div><div class='del'>-#define			SAHARA_ERRSOURCE_CHA	14</div><div class='del'>-#define			SAHARA_ERRSOURCE_DMA	15</div><div class='del'>-#define		SAHARA_ERRSTATUS_DMA_DIR	(1 &lt;&lt; 8)</div><div class='del'>-#define		SAHARA_ERRSTATUS_GET_DMASZ(x)(((x) &gt;&gt; 9) &amp; 0x3)</div><div class='del'>-#define		SAHARA_ERRSTATUS_GET_DMASRC(x) (((x) &gt;&gt; 13) &amp; 0x7)</div><div class='del'>-#define		SAHARA_ERRSTATUS_GET_CHASRC(x)	(((x) &gt;&gt; 16) &amp; 0xfff)</div><div class='del'>-#define		SAHARA_ERRSTATUS_GET_CHAERR(x)	(((x) &gt;&gt; 28) &amp; 0x3)</div><div class='del'>-#define SAHARA_REG_FADDR	0x18</div><div class='del'>-#define SAHARA_REG_CDAR		0x1C</div><div class='del'>-#define SAHARA_REG_IDAR		0x20</div><div class='add'>+#define SHA_BUFFER_LEN				PAGE_SIZE</div><div class='add'>+#define SAHARA_MAX_SHA_BLOCK_SIZE		SHA256_BLOCK_SIZE</div><div class='add'>+</div><div class='add'>+#define SAHARA_NAME				"sahara"</div><div class='add'>+#define SAHARA_VERSION_3			3</div><div class='add'>+#define SAHARA_VERSION_4			4</div><div class='add'>+#define SAHARA_TIMEOUT_MS			1000</div><div class='add'>+#define SAHARA_MAX_HW_DESC			2</div><div class='add'>+#define SAHARA_MAX_HW_LINK			20</div><div class='add'>+</div><div class='add'>+#define FLAGS_MODE_MASK				0x000f</div><div class='add'>+#define FLAGS_ENCRYPT				BIT(0)</div><div class='add'>+#define FLAGS_CBC				BIT(1)</div><div class='add'>+</div><div class='add'>+#define SAHARA_HDR_BASE				0x00800000</div><div class='add'>+#define SAHARA_HDR_SKHA_ALG_AES			0</div><div class='add'>+#define SAHARA_HDR_SKHA_MODE_ECB		0</div><div class='add'>+#define SAHARA_HDR_SKHA_OP_ENC			BIT(2)</div><div class='add'>+#define SAHARA_HDR_SKHA_MODE_CBC		BIT(3)</div><div class='add'>+#define SAHARA_HDR_FORM_DATA			(5 &lt;&lt; 16)</div><div class='add'>+#define SAHARA_HDR_FORM_KEY			BIT(19)</div><div class='add'>+#define SAHARA_HDR_LLO				BIT(24)</div><div class='add'>+#define SAHARA_HDR_CHA_SKHA			BIT(28)</div><div class='add'>+#define SAHARA_HDR_CHA_MDHA			BIT(29)</div><div class='add'>+#define SAHARA_HDR_PARITY_BIT			BIT(31)</div><div class='add'>+</div><div class='add'>+#define SAHARA_HDR_MDHA_SET_MODE_MD_KEY		0x20880000</div><div class='add'>+#define SAHARA_HDR_MDHA_SET_MODE_HASH		0x208D0000</div><div class='add'>+#define SAHARA_HDR_MDHA_HASH			0xA0850000</div><div class='add'>+#define SAHARA_HDR_MDHA_STORE_DIGEST		0x20820000</div><div class='add'>+#define SAHARA_HDR_MDHA_ALG_SHA1		0</div><div class='add'>+#define SAHARA_HDR_MDHA_ALG_MD5			1</div><div class='add'>+#define SAHARA_HDR_MDHA_ALG_SHA256		2</div><div class='add'>+#define SAHARA_HDR_MDHA_ALG_SHA224		3</div><div class='add'>+#define SAHARA_HDR_MDHA_PDATA			BIT(2)</div><div class='add'>+#define SAHARA_HDR_MDHA_HMAC			BIT(3)</div><div class='add'>+#define SAHARA_HDR_MDHA_INIT			BIT(5)</div><div class='add'>+#define SAHARA_HDR_MDHA_IPAD			BIT(6)</div><div class='add'>+#define SAHARA_HDR_MDHA_OPAD			BIT(7)</div><div class='add'>+#define SAHARA_HDR_MDHA_SWAP			BIT(8)</div><div class='add'>+#define SAHARA_HDR_MDHA_MAC_FULL		BIT(9)</div><div class='add'>+#define SAHARA_HDR_MDHA_SSL			BIT(10)</div><div class='add'>+</div><div class='add'>+#define SAHARA_REG_VERSION			0x00</div><div class='add'>+#define SAHARA_REG_DAR				0x04</div><div class='add'>+#define SAHARA_REG_CONTROL			0x08</div><div class='add'>+#define SAHARA_CONTROL_SET_THROTTLE(x)		(((x) &amp; 0xff) &lt;&lt; 24)</div><div class='add'>+#define SAHARA_CONTROL_SET_MAXBURST(x)		(((x) &amp; 0xff) &lt;&lt; 16)</div><div class='add'>+#define SAHARA_CONTROL_RNG_AUTORSD		BIT(7)</div><div class='add'>+#define SAHARA_CONTROL_ENABLE_INT		BIT(4)</div><div class='add'>+#define SAHARA_REG_CMD				0x0C</div><div class='add'>+#define SAHARA_CMD_RESET			BIT(0)</div><div class='add'>+#define SAHARA_CMD_CLEAR_INT			BIT(8)</div><div class='add'>+#define SAHARA_CMD_CLEAR_ERR			BIT(9)</div><div class='add'>+#define SAHARA_CMD_SINGLE_STEP			BIT(10)</div><div class='add'>+#define SAHARA_CMD_MODE_BATCH			BIT(16)</div><div class='add'>+#define SAHARA_CMD_MODE_DEBUG			BIT(18)</div><div class='add'>+#define SAHARA_REG_STATUS			0x10</div><div class='add'>+#define SAHARA_STATUS_GET_STATE(x)		((x) &amp; 0x7)</div><div class='add'>+#define SAHARA_STATE_IDLE			0</div><div class='add'>+#define SAHARA_STATE_BUSY			1</div><div class='add'>+#define SAHARA_STATE_ERR			2</div><div class='add'>+#define SAHARA_STATE_FAULT			3</div><div class='add'>+#define SAHARA_STATE_COMPLETE			4</div><div class='add'>+#define SAHARA_STATE_COMP_FLAG			BIT(2)</div><div class='add'>+#define SAHARA_STATUS_DAR_FULL			BIT(3)</div><div class='add'>+#define SAHARA_STATUS_ERROR			BIT(4)</div><div class='add'>+#define SAHARA_STATUS_SECURE			BIT(5)</div><div class='add'>+#define SAHARA_STATUS_FAIL			BIT(6)</div><div class='add'>+#define SAHARA_STATUS_INIT			BIT(7)</div><div class='add'>+#define SAHARA_STATUS_RNG_RESEED		BIT(8)</div><div class='add'>+#define SAHARA_STATUS_ACTIVE_RNG		BIT(9)</div><div class='add'>+#define SAHARA_STATUS_ACTIVE_MDHA		BIT(10)</div><div class='add'>+#define SAHARA_STATUS_ACTIVE_SKHA		BIT(11)</div><div class='add'>+#define SAHARA_STATUS_MODE_BATCH		BIT(16)</div><div class='add'>+#define SAHARA_STATUS_MODE_DEDICATED		BIT(17)</div><div class='add'>+#define SAHARA_STATUS_MODE_DEBUG		BIT(18)</div><div class='add'>+#define SAHARA_STATUS_GET_ISTATE(x)		(((x) &gt;&gt; 24) &amp; 0xff)</div><div class='add'>+#define SAHARA_REG_ERRSTATUS			0x14</div><div class='add'>+#define SAHARA_ERRSTATUS_GET_SOURCE(x)		((x) &amp; 0xf)</div><div class='add'>+#define SAHARA_ERRSOURCE_CHA			14</div><div class='add'>+#define SAHARA_ERRSOURCE_DMA			15</div><div class='add'>+#define SAHARA_ERRSTATUS_DMA_DIR		BIT(8)</div><div class='add'>+#define SAHARA_ERRSTATUS_GET_DMASZ(x)		(((x) &gt;&gt; 9) &amp; 0x3)</div><div class='add'>+#define SAHARA_ERRSTATUS_GET_DMASRC(x)		(((x) &gt;&gt; 13) &amp; 0x7)</div><div class='add'>+#define SAHARA_ERRSTATUS_GET_CHASRC(x)		(((x) &gt;&gt; 16) &amp; 0xfff)</div><div class='add'>+#define SAHARA_ERRSTATUS_GET_CHAERR(x)		(((x) &gt;&gt; 28) &amp; 0x3)</div><div class='add'>+#define SAHARA_REG_FADDR			0x18</div><div class='add'>+#define SAHARA_REG_CDAR				0x1C</div><div class='add'>+#define SAHARA_REG_IDAR				0x20</div><div class='ctx'> </div><div class='ctx'> struct sahara_hw_desc {</div><div class='ctx'> 	u32	hdr;</div><div class='hunk'>@@ -141,8 +137,6 @@ struct sahara_hw_link {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct sahara_ctx {</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='ctx'> 	/* AES-specific context */</div><div class='ctx'> 	int keylen;</div><div class='ctx'> 	u8 key[AES_KEYSIZE_128];</div><div class='hunk'>@@ -151,6 +145,7 @@ struct sahara_ctx {</div><div class='ctx'> </div><div class='ctx'> struct sahara_aes_reqctx {</div><div class='ctx'> 	unsigned long mode;</div><div class='add'>+	u8 iv_out[AES_BLOCK_SIZE];</div><div class='ctx'> 	struct skcipher_request fallback_req;	// keep at the end</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -170,7 +165,6 @@ struct sahara_aes_reqctx {</div><div class='ctx'>  * @total: total number of bytes for transfer</div><div class='ctx'>  * @last: is this the last block</div><div class='ctx'>  * @first: is this the first block</div><div class='del'>- * @active: inside a transfer</div><div class='ctx'>  */</div><div class='ctx'> struct sahara_sha_reqctx {</div><div class='ctx'> 	u8			buf[SAHARA_MAX_SHA_BLOCK_SIZE];</div><div class='hunk'>@@ -186,7 +180,6 @@ struct sahara_sha_reqctx {</div><div class='ctx'> 	size_t			total;</div><div class='ctx'> 	unsigned int		last;</div><div class='ctx'> 	unsigned int		first;</div><div class='del'>-	unsigned int		active;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct sahara_dev {</div><div class='hunk'>@@ -195,12 +188,9 @@ struct sahara_dev {</div><div class='ctx'> 	void __iomem		*regs_base;</div><div class='ctx'> 	struct clk		*clk_ipg;</div><div class='ctx'> 	struct clk		*clk_ahb;</div><div class='del'>-	spinlock_t		queue_spinlock;</div><div class='del'>-	struct task_struct	*kthread;</div><div class='ctx'> 	struct completion	dma_completion;</div><div class='ctx'> </div><div class='ctx'> 	struct sahara_ctx	*ctx;</div><div class='del'>-	struct crypto_queue	queue;</div><div class='ctx'> 	unsigned long		flags;</div><div class='ctx'> </div><div class='ctx'> 	struct sahara_hw_desc	*hw_desc[SAHARA_MAX_HW_DESC];</div><div class='hunk'>@@ -224,7 +214,7 @@ struct sahara_dev {</div><div class='ctx'> 	struct scatterlist	*out_sg;</div><div class='ctx'> 	int		nb_out_sg;</div><div class='ctx'> </div><div class='del'>-	u32			error;</div><div class='add'>+	struct crypto_engine *engine;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct sahara_dev *dev_ptr;</div><div class='hunk'>@@ -446,27 +436,24 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev)</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	int idx = 0;</div><div class='add'>+	u32 len;</div><div class='ctx'> </div><div class='del'>-	/* Copy new key if necessary */</div><div class='del'>-	if (ctx-&gt;flags &amp; FLAGS_NEW_KEY) {</div><div class='del'>-		memcpy(dev-&gt;key_base, ctx-&gt;key, ctx-&gt;keylen);</div><div class='del'>-		ctx-&gt;flags &amp;= ~FLAGS_NEW_KEY;</div><div class='add'>+	memcpy(dev-&gt;key_base, ctx-&gt;key, ctx-&gt;keylen);</div><div class='ctx'> </div><div class='del'>-		if (dev-&gt;flags &amp; FLAGS_CBC) {</div><div class='del'>-			dev-&gt;hw_desc[idx]-&gt;len1 = AES_BLOCK_SIZE;</div><div class='del'>-			dev-&gt;hw_desc[idx]-&gt;p1 = dev-&gt;iv_phys_base;</div><div class='del'>-		} else {</div><div class='del'>-			dev-&gt;hw_desc[idx]-&gt;len1 = 0;</div><div class='del'>-			dev-&gt;hw_desc[idx]-&gt;p1 = 0;</div><div class='del'>-		}</div><div class='del'>-		dev-&gt;hw_desc[idx]-&gt;len2 = ctx-&gt;keylen;</div><div class='del'>-		dev-&gt;hw_desc[idx]-&gt;p2 = dev-&gt;key_phys_base;</div><div class='del'>-		dev-&gt;hw_desc[idx]-&gt;next = dev-&gt;hw_phys_desc[1];</div><div class='add'>+	if (dev-&gt;flags &amp; FLAGS_CBC) {</div><div class='add'>+		dev-&gt;hw_desc[idx]-&gt;len1 = AES_BLOCK_SIZE;</div><div class='add'>+		dev-&gt;hw_desc[idx]-&gt;p1 = dev-&gt;iv_phys_base;</div><div class='add'>+	} else {</div><div class='add'>+		dev-&gt;hw_desc[idx]-&gt;len1 = 0;</div><div class='add'>+		dev-&gt;hw_desc[idx]-&gt;p1 = 0;</div><div class='add'>+	}</div><div class='add'>+	dev-&gt;hw_desc[idx]-&gt;len2 = ctx-&gt;keylen;</div><div class='add'>+	dev-&gt;hw_desc[idx]-&gt;p2 = dev-&gt;key_phys_base;</div><div class='add'>+	dev-&gt;hw_desc[idx]-&gt;next = dev-&gt;hw_phys_desc[1];</div><div class='add'>+	dev-&gt;hw_desc[idx]-&gt;hdr = sahara_aes_key_hdr(dev);</div><div class='ctx'> </div><div class='del'>-		dev-&gt;hw_desc[idx]-&gt;hdr = sahara_aes_key_hdr(dev);</div><div class='add'>+	idx++;</div><div class='ctx'> </div><div class='del'>-		idx++;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;nb_in_sg = sg_nents_for_len(dev-&gt;in_sg, dev-&gt;total);</div><div class='ctx'> 	if (dev-&gt;nb_in_sg &lt; 0) {</div><div class='hunk'>@@ -488,24 +475,27 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev)</div><div class='ctx'> 			 DMA_TO_DEVICE);</div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		dev_err(dev-&gt;device, "couldn't map in sg\n");</div><div class='del'>-		goto unmap_in;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	ret = dma_map_sg(dev-&gt;device, dev-&gt;out_sg, dev-&gt;nb_out_sg,</div><div class='ctx'> 			 DMA_FROM_DEVICE);</div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		dev_err(dev-&gt;device, "couldn't map out sg\n");</div><div class='del'>-		goto unmap_out;</div><div class='add'>+		goto unmap_in;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Create input links */</div><div class='ctx'> 	dev-&gt;hw_desc[idx]-&gt;p1 = dev-&gt;hw_phys_link[0];</div><div class='ctx'> 	sg = dev-&gt;in_sg;</div><div class='add'>+	len = dev-&gt;total;</div><div class='ctx'> 	for (i = 0; i &lt; dev-&gt;nb_in_sg; i++) {</div><div class='del'>-		dev-&gt;hw_link[i]-&gt;len = sg-&gt;length;</div><div class='add'>+		dev-&gt;hw_link[i]-&gt;len = min(len, sg-&gt;length);</div><div class='ctx'> 		dev-&gt;hw_link[i]-&gt;p = sg-&gt;dma_address;</div><div class='ctx'> 		if (i == (dev-&gt;nb_in_sg - 1)) {</div><div class='ctx'> 			dev-&gt;hw_link[i]-&gt;next = 0;</div><div class='ctx'> 		} else {</div><div class='add'>+			len -= min(len, sg-&gt;length);</div><div class='ctx'> 			dev-&gt;hw_link[i]-&gt;next = dev-&gt;hw_phys_link[i + 1];</div><div class='ctx'> 			sg = sg_next(sg);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -514,12 +504,14 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev)</div><div class='ctx'> 	/* Create output links */</div><div class='ctx'> 	dev-&gt;hw_desc[idx]-&gt;p2 = dev-&gt;hw_phys_link[i];</div><div class='ctx'> 	sg = dev-&gt;out_sg;</div><div class='add'>+	len = dev-&gt;total;</div><div class='ctx'> 	for (j = i; j &lt; dev-&gt;nb_out_sg + i; j++) {</div><div class='del'>-		dev-&gt;hw_link[j]-&gt;len = sg-&gt;length;</div><div class='add'>+		dev-&gt;hw_link[j]-&gt;len = min(len, sg-&gt;length);</div><div class='ctx'> 		dev-&gt;hw_link[j]-&gt;p = sg-&gt;dma_address;</div><div class='ctx'> 		if (j == (dev-&gt;nb_out_sg + i - 1)) {</div><div class='ctx'> 			dev-&gt;hw_link[j]-&gt;next = 0;</div><div class='ctx'> 		} else {</div><div class='add'>+			len -= min(len, sg-&gt;length);</div><div class='ctx'> 			dev-&gt;hw_link[j]-&gt;next = dev-&gt;hw_phys_link[j + 1];</div><div class='ctx'> 			sg = sg_next(sg);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -538,9 +530,6 @@ static int sahara_hw_descriptor_create(struct sahara_dev *dev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-unmap_out:</div><div class='del'>-	dma_unmap_sg(dev-&gt;device, dev-&gt;out_sg, dev-&gt;nb_out_sg,</div><div class='del'>-		DMA_FROM_DEVICE);</div><div class='ctx'> unmap_in:</div><div class='ctx'> 	dma_unmap_sg(dev-&gt;device, dev-&gt;in_sg, dev-&gt;nb_in_sg,</div><div class='ctx'> 		DMA_TO_DEVICE);</div><div class='hunk'>@@ -548,8 +537,24 @@ unmap_in:</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void sahara_aes_cbc_update_iv(struct skcipher_request *req)</div><div class='add'>+{</div><div class='add'>+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);</div><div class='add'>+	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='add'>+	unsigned int ivsize = crypto_skcipher_ivsize(skcipher);</div><div class='add'>+</div><div class='add'>+	/* Update IV buffer to contain the last ciphertext block */</div><div class='add'>+	if (rctx-&gt;mode &amp; FLAGS_ENCRYPT) {</div><div class='add'>+		sg_pcopy_to_buffer(req-&gt;dst, sg_nents(req-&gt;dst), req-&gt;iv,</div><div class='add'>+				   ivsize, req-&gt;cryptlen - ivsize);</div><div class='add'>+	} else {</div><div class='add'>+		memcpy(req-&gt;iv, rctx-&gt;iv_out, ivsize);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sahara_aes_process(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='add'>+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);</div><div class='ctx'> 	struct sahara_dev *dev = dev_ptr;</div><div class='ctx'> 	struct sahara_ctx *ctx;</div><div class='ctx'> 	struct sahara_aes_reqctx *rctx;</div><div class='hunk'>@@ -571,8 +576,17 @@ static int sahara_aes_process(struct skcipher_request *req)</div><div class='ctx'> 	rctx-&gt;mode &amp;= FLAGS_MODE_MASK;</div><div class='ctx'> 	dev-&gt;flags = (dev-&gt;flags &amp; ~FLAGS_MODE_MASK) | rctx-&gt;mode;</div><div class='ctx'> </div><div class='del'>-	if ((dev-&gt;flags &amp; FLAGS_CBC) &amp;&amp; req-&gt;iv)</div><div class='del'>-		memcpy(dev-&gt;iv_base, req-&gt;iv, AES_KEYSIZE_128);</div><div class='add'>+	if ((dev-&gt;flags &amp; FLAGS_CBC) &amp;&amp; req-&gt;iv) {</div><div class='add'>+		unsigned int ivsize = crypto_skcipher_ivsize(skcipher);</div><div class='add'>+</div><div class='add'>+		memcpy(dev-&gt;iv_base, req-&gt;iv, ivsize);</div><div class='add'>+</div><div class='add'>+		if (!(dev-&gt;flags &amp; FLAGS_ENCRYPT)) {</div><div class='add'>+			sg_pcopy_to_buffer(req-&gt;src, sg_nents(req-&gt;src),</div><div class='add'>+					   rctx-&gt;iv_out, ivsize,</div><div class='add'>+					   req-&gt;cryptlen - ivsize);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* assign new context to device */</div><div class='ctx'> 	dev-&gt;ctx = ctx;</div><div class='hunk'>@@ -585,16 +599,20 @@ static int sahara_aes_process(struct skcipher_request *req)</div><div class='ctx'> </div><div class='ctx'> 	timeout = wait_for_completion_timeout(&amp;dev-&gt;dma_completion,</div><div class='ctx'> 				msecs_to_jiffies(SAHARA_TIMEOUT_MS));</div><div class='del'>-	if (!timeout) {</div><div class='del'>-		dev_err(dev-&gt;device, "AES timeout\n");</div><div class='del'>-		return -ETIMEDOUT;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	dma_unmap_sg(dev-&gt;device, dev-&gt;out_sg, dev-&gt;nb_out_sg,</div><div class='ctx'> 		DMA_FROM_DEVICE);</div><div class='ctx'> 	dma_unmap_sg(dev-&gt;device, dev-&gt;in_sg, dev-&gt;nb_in_sg,</div><div class='ctx'> 		DMA_TO_DEVICE);</div><div class='ctx'> </div><div class='add'>+	if (!timeout) {</div><div class='add'>+		dev_err(dev-&gt;device, "AES timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((dev-&gt;flags &amp; FLAGS_CBC) &amp;&amp; req-&gt;iv)</div><div class='add'>+		sahara_aes_cbc_update_iv(req);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -608,7 +626,6 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,</div><div class='ctx'> 	/* SAHARA only supports 128bit keys */</div><div class='ctx'> 	if (keylen == AES_KEYSIZE_128) {</div><div class='ctx'> 		memcpy(ctx-&gt;key, key, keylen);</div><div class='del'>-		ctx-&gt;flags |= FLAGS_NEW_KEY;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -624,109 +641,67 @@ static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,</div><div class='ctx'> 	return crypto_skcipher_setkey(ctx-&gt;fallback, key, keylen);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int sahara_aes_fallback(struct skcipher_request *req, unsigned long mode)</div><div class='add'>+{</div><div class='add'>+	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='add'>+	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='add'>+		crypto_skcipher_reqtfm(req));</div><div class='add'>+</div><div class='add'>+	skcipher_request_set_tfm(&amp;rctx-&gt;fallback_req, ctx-&gt;fallback);</div><div class='add'>+	skcipher_request_set_callback(&amp;rctx-&gt;fallback_req,</div><div class='add'>+				      req-&gt;base.flags,</div><div class='add'>+				      req-&gt;base.complete,</div><div class='add'>+				      req-&gt;base.data);</div><div class='add'>+	skcipher_request_set_crypt(&amp;rctx-&gt;fallback_req, req-&gt;src,</div><div class='add'>+				   req-&gt;dst, req-&gt;cryptlen, req-&gt;iv);</div><div class='add'>+</div><div class='add'>+	if (mode &amp; FLAGS_ENCRYPT)</div><div class='add'>+		return crypto_skcipher_encrypt(&amp;rctx-&gt;fallback_req);</div><div class='add'>+</div><div class='add'>+	return crypto_skcipher_decrypt(&amp;rctx-&gt;fallback_req);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='add'>+	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='add'>+		crypto_skcipher_reqtfm(req));</div><div class='ctx'> 	struct sahara_dev *dev = dev_ptr;</div><div class='del'>-	int err = 0;</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;cryptlen)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (unlikely(ctx-&gt;keylen != AES_KEYSIZE_128))</div><div class='add'>+		return sahara_aes_fallback(req, mode);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(dev-&gt;device, "nbytes: %d, enc: %d, cbc: %d\n",</div><div class='ctx'> 		req-&gt;cryptlen, !!(mode &amp; FLAGS_ENCRYPT), !!(mode &amp; FLAGS_CBC));</div><div class='ctx'> </div><div class='del'>-	if (!IS_ALIGNED(req-&gt;cryptlen, AES_BLOCK_SIZE)) {</div><div class='del'>-		dev_err(dev-&gt;device,</div><div class='del'>-			"request size is not exact amount of AES blocks\n");</div><div class='add'>+	if (!IS_ALIGNED(req-&gt;cryptlen, AES_BLOCK_SIZE))</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	rctx-&gt;mode = mode;</div><div class='ctx'> </div><div class='del'>-	spin_lock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-	err = crypto_enqueue_request(&amp;dev-&gt;queue, &amp;req-&gt;base);</div><div class='del'>-	spin_unlock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-</div><div class='del'>-	wake_up_process(dev-&gt;kthread);</div><div class='del'>-</div><div class='del'>-	return err;</div><div class='add'>+	return crypto_transfer_skcipher_request_to_engine(dev-&gt;engine, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sahara_aes_ecb_encrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='del'>-	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='del'>-	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='del'>-		crypto_skcipher_reqtfm(req));</div><div class='del'>-</div><div class='del'>-	if (unlikely(ctx-&gt;keylen != AES_KEYSIZE_128)) {</div><div class='del'>-		skcipher_request_set_tfm(&amp;rctx-&gt;fallback_req, ctx-&gt;fallback);</div><div class='del'>-		skcipher_request_set_callback(&amp;rctx-&gt;fallback_req,</div><div class='del'>-					      req-&gt;base.flags,</div><div class='del'>-					      req-&gt;base.complete,</div><div class='del'>-					      req-&gt;base.data);</div><div class='del'>-		skcipher_request_set_crypt(&amp;rctx-&gt;fallback_req, req-&gt;src,</div><div class='del'>-					   req-&gt;dst, req-&gt;cryptlen, req-&gt;iv);</div><div class='del'>-		return crypto_skcipher_encrypt(&amp;rctx-&gt;fallback_req);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return sahara_aes_crypt(req, FLAGS_ENCRYPT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sahara_aes_ecb_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='del'>-	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='del'>-	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='del'>-		crypto_skcipher_reqtfm(req));</div><div class='del'>-</div><div class='del'>-	if (unlikely(ctx-&gt;keylen != AES_KEYSIZE_128)) {</div><div class='del'>-		skcipher_request_set_tfm(&amp;rctx-&gt;fallback_req, ctx-&gt;fallback);</div><div class='del'>-		skcipher_request_set_callback(&amp;rctx-&gt;fallback_req,</div><div class='del'>-					      req-&gt;base.flags,</div><div class='del'>-					      req-&gt;base.complete,</div><div class='del'>-					      req-&gt;base.data);</div><div class='del'>-		skcipher_request_set_crypt(&amp;rctx-&gt;fallback_req, req-&gt;src,</div><div class='del'>-					   req-&gt;dst, req-&gt;cryptlen, req-&gt;iv);</div><div class='del'>-		return crypto_skcipher_decrypt(&amp;rctx-&gt;fallback_req);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return sahara_aes_crypt(req, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sahara_aes_cbc_encrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='del'>-	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='del'>-	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='del'>-		crypto_skcipher_reqtfm(req));</div><div class='del'>-</div><div class='del'>-	if (unlikely(ctx-&gt;keylen != AES_KEYSIZE_128)) {</div><div class='del'>-		skcipher_request_set_tfm(&amp;rctx-&gt;fallback_req, ctx-&gt;fallback);</div><div class='del'>-		skcipher_request_set_callback(&amp;rctx-&gt;fallback_req,</div><div class='del'>-					      req-&gt;base.flags,</div><div class='del'>-					      req-&gt;base.complete,</div><div class='del'>-					      req-&gt;base.data);</div><div class='del'>-		skcipher_request_set_crypt(&amp;rctx-&gt;fallback_req, req-&gt;src,</div><div class='del'>-					   req-&gt;dst, req-&gt;cryptlen, req-&gt;iv);</div><div class='del'>-		return crypto_skcipher_encrypt(&amp;rctx-&gt;fallback_req);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return sahara_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sahara_aes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='del'>-	struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);</div><div class='del'>-	struct sahara_ctx *ctx = crypto_skcipher_ctx(</div><div class='del'>-		crypto_skcipher_reqtfm(req));</div><div class='del'>-</div><div class='del'>-	if (unlikely(ctx-&gt;keylen != AES_KEYSIZE_128)) {</div><div class='del'>-		skcipher_request_set_tfm(&amp;rctx-&gt;fallback_req, ctx-&gt;fallback);</div><div class='del'>-		skcipher_request_set_callback(&amp;rctx-&gt;fallback_req,</div><div class='del'>-					      req-&gt;base.flags,</div><div class='del'>-					      req-&gt;base.complete,</div><div class='del'>-					      req-&gt;base.data);</div><div class='del'>-		skcipher_request_set_crypt(&amp;rctx-&gt;fallback_req, req-&gt;src,</div><div class='del'>-					   req-&gt;dst, req-&gt;cryptlen, req-&gt;iv);</div><div class='del'>-		return crypto_skcipher_decrypt(&amp;rctx-&gt;fallback_req);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return sahara_aes_crypt(req, FLAGS_CBC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -783,6 +758,7 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev,</div><div class='ctx'> 				       int start)</div><div class='ctx'> {</div><div class='ctx'> 	struct scatterlist *sg;</div><div class='add'>+	unsigned int len;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -804,12 +780,14 @@ static int sahara_sha_hw_links_create(struct sahara_dev *dev,</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> </div><div class='add'>+	len = rctx-&gt;total;</div><div class='ctx'> 	for (i = start; i &lt; dev-&gt;nb_in_sg + start; i++) {</div><div class='del'>-		dev-&gt;hw_link[i]-&gt;len = sg-&gt;length;</div><div class='add'>+		dev-&gt;hw_link[i]-&gt;len = min(len, sg-&gt;length);</div><div class='ctx'> 		dev-&gt;hw_link[i]-&gt;p = sg-&gt;dma_address;</div><div class='ctx'> 		if (i == (dev-&gt;nb_in_sg + start - 1)) {</div><div class='ctx'> 			dev-&gt;hw_link[i]-&gt;next = 0;</div><div class='ctx'> 		} else {</div><div class='add'>+			len -= min(len, sg-&gt;length);</div><div class='ctx'> 			dev-&gt;hw_link[i]-&gt;next = dev-&gt;hw_phys_link[i + 1];</div><div class='ctx'> 			sg = sg_next(sg);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -890,24 +868,6 @@ static int sahara_sha_hw_context_descriptor_create(struct sahara_dev *dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sahara_walk_and_recalc(struct scatterlist *sg, unsigned int nbytes)</div><div class='del'>-{</div><div class='del'>-	if (!sg || !sg-&gt;length)</div><div class='del'>-		return nbytes;</div><div class='del'>-</div><div class='del'>-	while (nbytes &amp;&amp; sg) {</div><div class='del'>-		if (nbytes &lt;= sg-&gt;length) {</div><div class='del'>-			sg-&gt;length = nbytes;</div><div class='del'>-			sg_mark_end(sg);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-		nbytes -= sg-&gt;length;</div><div class='del'>-		sg = sg_next(sg);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return nbytes;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int sahara_sha_prepare_request(struct ahash_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);</div><div class='hunk'>@@ -944,36 +904,20 @@ static int sahara_sha_prepare_request(struct ahash_request *req)</div><div class='ctx'> 					hash_later, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* nbytes should now be multiple of blocksize */</div><div class='del'>-	req-&gt;nbytes = req-&gt;nbytes - hash_later;</div><div class='del'>-</div><div class='del'>-	sahara_walk_and_recalc(req-&gt;src, req-&gt;nbytes);</div><div class='del'>-</div><div class='add'>+	rctx-&gt;total = len - hash_later;</div><div class='ctx'> 	/* have data from previous operation and current */</div><div class='ctx'> 	if (rctx-&gt;buf_cnt &amp;&amp; req-&gt;nbytes) {</div><div class='ctx'> 		sg_init_table(rctx-&gt;in_sg_chain, 2);</div><div class='ctx'> 		sg_set_buf(rctx-&gt;in_sg_chain, rctx-&gt;rembuf, rctx-&gt;buf_cnt);</div><div class='del'>-</div><div class='ctx'> 		sg_chain(rctx-&gt;in_sg_chain, 2, req-&gt;src);</div><div class='del'>-</div><div class='del'>-		rctx-&gt;total = req-&gt;nbytes + rctx-&gt;buf_cnt;</div><div class='ctx'> 		rctx-&gt;in_sg = rctx-&gt;in_sg_chain;</div><div class='del'>-</div><div class='del'>-		req-&gt;src = rctx-&gt;in_sg_chain;</div><div class='ctx'> 	/* only data from previous operation */</div><div class='ctx'> 	} else if (rctx-&gt;buf_cnt) {</div><div class='del'>-		if (req-&gt;src)</div><div class='del'>-			rctx-&gt;in_sg = req-&gt;src;</div><div class='del'>-		else</div><div class='del'>-			rctx-&gt;in_sg = rctx-&gt;in_sg_chain;</div><div class='del'>-		/* buf was copied into rembuf above */</div><div class='add'>+		rctx-&gt;in_sg = rctx-&gt;in_sg_chain;</div><div class='ctx'> 		sg_init_one(rctx-&gt;in_sg, rctx-&gt;rembuf, rctx-&gt;buf_cnt);</div><div class='del'>-		rctx-&gt;total = rctx-&gt;buf_cnt;</div><div class='ctx'> 	/* no data from previous operation */</div><div class='ctx'> 	} else {</div><div class='ctx'> 		rctx-&gt;in_sg = req-&gt;src;</div><div class='del'>-		rctx-&gt;total = req-&gt;nbytes;</div><div class='del'>-		req-&gt;src = rctx-&gt;in_sg;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* on next call, we only have the remaining data in the buffer */</div><div class='hunk'>@@ -994,7 +938,10 @@ static int sahara_sha_process(struct ahash_request *req)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (rctx-&gt;first) {</div><div class='del'>-		sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0);</div><div class='add'>+		ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='ctx'> 		dev-&gt;hw_desc[0]-&gt;next = 0;</div><div class='ctx'> 		rctx-&gt;first = 0;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1002,7 +949,10 @@ static int sahara_sha_process(struct ahash_request *req)</div><div class='ctx'> </div><div class='ctx'> 		sahara_sha_hw_context_descriptor_create(dev, rctx, req, 0);</div><div class='ctx'> 		dev-&gt;hw_desc[0]-&gt;next = dev-&gt;hw_phys_desc[1];</div><div class='del'>-		sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1);</div><div class='add'>+		ret = sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='ctx'> 		dev-&gt;hw_desc[1]-&gt;next = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1015,62 +965,44 @@ static int sahara_sha_process(struct ahash_request *req)</div><div class='ctx'> </div><div class='ctx'> 	timeout = wait_for_completion_timeout(&amp;dev-&gt;dma_completion,</div><div class='ctx'> 				msecs_to_jiffies(SAHARA_TIMEOUT_MS));</div><div class='del'>-	if (!timeout) {</div><div class='del'>-		dev_err(dev-&gt;device, "SHA timeout\n");</div><div class='del'>-		return -ETIMEDOUT;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (rctx-&gt;sg_in_idx)</div><div class='ctx'> 		dma_unmap_sg(dev-&gt;device, dev-&gt;in_sg, dev-&gt;nb_in_sg,</div><div class='ctx'> 			     DMA_TO_DEVICE);</div><div class='ctx'> </div><div class='add'>+	if (!timeout) {</div><div class='add'>+		dev_err(dev-&gt;device, "SHA timeout\n");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	memcpy(rctx-&gt;context, dev-&gt;context_base, rctx-&gt;context_size);</div><div class='ctx'> </div><div class='del'>-	if (req-&gt;result)</div><div class='add'>+	if (req-&gt;result &amp;&amp; rctx-&gt;last)</div><div class='ctx'> 		memcpy(req-&gt;result, rctx-&gt;context, rctx-&gt;digest_size);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sahara_queue_manage(void *data)</div><div class='add'>+static int sahara_do_one_request(struct crypto_engine *engine, void *areq)</div><div class='ctx'> {</div><div class='del'>-	struct sahara_dev *dev = data;</div><div class='del'>-	struct crypto_async_request *async_req;</div><div class='del'>-	struct crypto_async_request *backlog;</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		__set_current_state(TASK_INTERRUPTIBLE);</div><div class='del'>-</div><div class='del'>-		spin_lock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-		backlog = crypto_get_backlog(&amp;dev-&gt;queue);</div><div class='del'>-		async_req = crypto_dequeue_request(&amp;dev-&gt;queue);</div><div class='del'>-		spin_unlock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-</div><div class='del'>-		if (backlog)</div><div class='del'>-			crypto_request_complete(backlog, -EINPROGRESS);</div><div class='del'>-</div><div class='del'>-		if (async_req) {</div><div class='del'>-			if (crypto_tfm_alg_type(async_req-&gt;tfm) ==</div><div class='del'>-			    CRYPTO_ALG_TYPE_AHASH) {</div><div class='del'>-				struct ahash_request *req =</div><div class='del'>-					ahash_request_cast(async_req);</div><div class='del'>-</div><div class='del'>-				ret = sahara_sha_process(req);</div><div class='del'>-			} else {</div><div class='del'>-				struct skcipher_request *req =</div><div class='del'>-					skcipher_request_cast(async_req);</div><div class='del'>-</div><div class='del'>-				ret = sahara_aes_process(req);</div><div class='del'>-			}</div><div class='add'>+	struct crypto_async_request *async_req = areq;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-			crypto_request_complete(async_req, ret);</div><div class='add'>+	if (crypto_tfm_alg_type(async_req-&gt;tfm) == CRYPTO_ALG_TYPE_AHASH) {</div><div class='add'>+		struct ahash_request *req = ahash_request_cast(async_req);</div><div class='ctx'> </div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='add'>+		err = sahara_sha_process(req);</div><div class='add'>+		local_bh_disable();</div><div class='add'>+		crypto_finalize_hash_request(engine, req, err);</div><div class='add'>+		local_bh_enable();</div><div class='add'>+	} else {</div><div class='add'>+		struct skcipher_request *req = skcipher_request_cast(async_req);</div><div class='ctx'> </div><div class='del'>-		schedule();</div><div class='del'>-	} while (!kthread_should_stop());</div><div class='add'>+		err = sahara_aes_process(skcipher_request_cast(async_req));</div><div class='add'>+		local_bh_disable();</div><div class='add'>+		crypto_finalize_skcipher_request(engine, req, err);</div><div class='add'>+		local_bh_enable();</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1079,25 +1011,13 @@ static int sahara_sha_enqueue(struct ahash_request *req, int last)</div><div class='ctx'> {</div><div class='ctx'> 	struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);</div><div class='ctx'> 	struct sahara_dev *dev = dev_ptr;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!req-&gt;nbytes &amp;&amp; !last)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	rctx-&gt;last = last;</div><div class='ctx'> </div><div class='del'>-	if (!rctx-&gt;active) {</div><div class='del'>-		rctx-&gt;active = 1;</div><div class='del'>-		rctx-&gt;first = 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	spin_lock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-	ret = crypto_enqueue_request(&amp;dev-&gt;queue, &amp;req-&gt;base);</div><div class='del'>-	spin_unlock_bh(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-</div><div class='del'>-	wake_up_process(dev-&gt;kthread);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='add'>+	return crypto_transfer_hash_request_to_engine(dev-&gt;engine, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sahara_sha_init(struct ahash_request *req)</div><div class='hunk'>@@ -1121,7 +1041,7 @@ static int sahara_sha_init(struct ahash_request *req)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rctx-&gt;context_size = rctx-&gt;digest_size + 4;</div><div class='del'>-	rctx-&gt;active = 0;</div><div class='add'>+	rctx-&gt;first = 1;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1170,100 +1090,119 @@ static int sahara_sha_import(struct ahash_request *req, const void *in)</div><div class='ctx'> static int sahara_sha_cra_init(struct crypto_tfm *tfm)</div><div class='ctx'> {</div><div class='ctx'> 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),</div><div class='del'>-				 sizeof(struct sahara_sha_reqctx) +</div><div class='del'>-				 SHA_BUFFER_LEN + SHA256_BLOCK_SIZE);</div><div class='add'>+				 sizeof(struct sahara_sha_reqctx));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct skcipher_alg aes_algs[] = {</div><div class='add'>+static struct skcipher_engine_alg aes_algs[] = {</div><div class='ctx'> {</div><div class='del'>-	.base.cra_name		= "ecb(aes)",</div><div class='del'>-	.base.cra_driver_name	= "sahara-ecb-aes",</div><div class='del'>-	.base.cra_priority	= 300,</div><div class='del'>-	.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-	.base.cra_blocksize	= AES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct sahara_ctx),</div><div class='del'>-	.base.cra_alignmask	= 0x0,</div><div class='del'>-	.base.cra_module	= THIS_MODULE,</div><div class='del'>-</div><div class='del'>-	.init			= sahara_aes_init_tfm,</div><div class='del'>-	.exit			= sahara_aes_exit_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE ,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.setkey			= sahara_aes_setkey,</div><div class='del'>-	.encrypt		= sahara_aes_ecb_encrypt,</div><div class='del'>-	.decrypt		= sahara_aes_ecb_decrypt,</div><div class='add'>+	.base = {</div><div class='add'>+		.base.cra_name		= "ecb(aes)",</div><div class='add'>+		.base.cra_driver_name	= "sahara-ecb-aes",</div><div class='add'>+		.base.cra_priority	= 300,</div><div class='add'>+		.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,</div><div class='add'>+		.base.cra_blocksize	= AES_BLOCK_SIZE,</div><div class='add'>+		.base.cra_ctxsize	= sizeof(struct sahara_ctx),</div><div class='add'>+		.base.cra_alignmask	= 0x0,</div><div class='add'>+		.base.cra_module	= THIS_MODULE,</div><div class='add'>+</div><div class='add'>+		.init			= sahara_aes_init_tfm,</div><div class='add'>+		.exit			= sahara_aes_exit_tfm,</div><div class='add'>+		.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='add'>+		.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='add'>+		.setkey			= sahara_aes_setkey,</div><div class='add'>+		.encrypt		= sahara_aes_ecb_encrypt,</div><div class='add'>+		.decrypt		= sahara_aes_ecb_decrypt,</div><div class='add'>+	},</div><div class='add'>+	.op = {</div><div class='add'>+		.do_one_request = sahara_do_one_request,</div><div class='add'>+	},</div><div class='ctx'> }, {</div><div class='del'>-	.base.cra_name		= "cbc(aes)",</div><div class='del'>-	.base.cra_driver_name	= "sahara-cbc-aes",</div><div class='del'>-	.base.cra_priority	= 300,</div><div class='del'>-	.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-	.base.cra_blocksize	= AES_BLOCK_SIZE,</div><div class='del'>-	.base.cra_ctxsize	= sizeof(struct sahara_ctx),</div><div class='del'>-	.base.cra_alignmask	= 0x0,</div><div class='del'>-	.base.cra_module	= THIS_MODULE,</div><div class='del'>-</div><div class='del'>-	.init			= sahara_aes_init_tfm,</div><div class='del'>-	.exit			= sahara_aes_exit_tfm,</div><div class='del'>-	.min_keysize		= AES_MIN_KEY_SIZE ,</div><div class='del'>-	.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-	.setkey			= sahara_aes_setkey,</div><div class='del'>-	.encrypt		= sahara_aes_cbc_encrypt,</div><div class='del'>-	.decrypt		= sahara_aes_cbc_decrypt,</div><div class='add'>+	.base = {</div><div class='add'>+		.base.cra_name		= "cbc(aes)",</div><div class='add'>+		.base.cra_driver_name	= "sahara-cbc-aes",</div><div class='add'>+		.base.cra_priority	= 300,</div><div class='add'>+		.base.cra_flags		= CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,</div><div class='add'>+		.base.cra_blocksize	= AES_BLOCK_SIZE,</div><div class='add'>+		.base.cra_ctxsize	= sizeof(struct sahara_ctx),</div><div class='add'>+		.base.cra_alignmask	= 0x0,</div><div class='add'>+		.base.cra_module	= THIS_MODULE,</div><div class='add'>+</div><div class='add'>+		.init			= sahara_aes_init_tfm,</div><div class='add'>+		.exit			= sahara_aes_exit_tfm,</div><div class='add'>+		.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='add'>+		.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='add'>+		.ivsize			= AES_BLOCK_SIZE,</div><div class='add'>+		.setkey			= sahara_aes_setkey,</div><div class='add'>+		.encrypt		= sahara_aes_cbc_encrypt,</div><div class='add'>+		.decrypt		= sahara_aes_cbc_decrypt,</div><div class='add'>+	},</div><div class='add'>+	.op = {</div><div class='add'>+		.do_one_request = sahara_do_one_request,</div><div class='add'>+	},</div><div class='ctx'> }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct ahash_alg sha_v3_algs[] = {</div><div class='add'>+static struct ahash_engine_alg sha_v3_algs[] = {</div><div class='ctx'> {</div><div class='del'>-	.init		= sahara_sha_init,</div><div class='del'>-	.update		= sahara_sha_update,</div><div class='del'>-	.final		= sahara_sha_final,</div><div class='del'>-	.finup		= sahara_sha_finup,</div><div class='del'>-	.digest		= sahara_sha_digest,</div><div class='del'>-	.export		= sahara_sha_export,</div><div class='del'>-	.import		= sahara_sha_import,</div><div class='del'>-	.halg.digestsize	= SHA1_DIGEST_SIZE,</div><div class='del'>-	.halg.statesize         = sizeof(struct sahara_sha_reqctx),</div><div class='del'>-	.halg.base	= {</div><div class='del'>-		.cra_name		= "sha1",</div><div class='del'>-		.cra_driver_name	= "sahara-sha1",</div><div class='del'>-		.cra_priority		= 300,</div><div class='del'>-		.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='del'>-						CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-		.cra_blocksize		= SHA1_BLOCK_SIZE,</div><div class='del'>-		.cra_ctxsize		= sizeof(struct sahara_ctx),</div><div class='del'>-		.cra_alignmask		= 0,</div><div class='del'>-		.cra_module		= THIS_MODULE,</div><div class='del'>-		.cra_init		= sahara_sha_cra_init,</div><div class='del'>-	}</div><div class='add'>+	.base = {</div><div class='add'>+		.init		= sahara_sha_init,</div><div class='add'>+		.update		= sahara_sha_update,</div><div class='add'>+		.final		= sahara_sha_final,</div><div class='add'>+		.finup		= sahara_sha_finup,</div><div class='add'>+		.digest		= sahara_sha_digest,</div><div class='add'>+		.export		= sahara_sha_export,</div><div class='add'>+		.import		= sahara_sha_import,</div><div class='add'>+		.halg.digestsize	= SHA1_DIGEST_SIZE,</div><div class='add'>+		.halg.statesize         = sizeof(struct sahara_sha_reqctx),</div><div class='add'>+		.halg.base	= {</div><div class='add'>+			.cra_name		= "sha1",</div><div class='add'>+			.cra_driver_name	= "sahara-sha1",</div><div class='add'>+			.cra_priority		= 300,</div><div class='add'>+			.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='add'>+							CRYPTO_ALG_NEED_FALLBACK,</div><div class='add'>+			.cra_blocksize		= SHA1_BLOCK_SIZE,</div><div class='add'>+			.cra_ctxsize		= sizeof(struct sahara_ctx),</div><div class='add'>+			.cra_alignmask		= 0,</div><div class='add'>+			.cra_module		= THIS_MODULE,</div><div class='add'>+			.cra_init		= sahara_sha_cra_init,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.op = {</div><div class='add'>+		.do_one_request = sahara_do_one_request,</div><div class='add'>+	},</div><div class='ctx'> },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct ahash_alg sha_v4_algs[] = {</div><div class='add'>+static struct ahash_engine_alg sha_v4_algs[] = {</div><div class='ctx'> {</div><div class='del'>-	.init		= sahara_sha_init,</div><div class='del'>-	.update		= sahara_sha_update,</div><div class='del'>-	.final		= sahara_sha_final,</div><div class='del'>-	.finup		= sahara_sha_finup,</div><div class='del'>-	.digest		= sahara_sha_digest,</div><div class='del'>-	.export		= sahara_sha_export,</div><div class='del'>-	.import		= sahara_sha_import,</div><div class='del'>-	.halg.digestsize	= SHA256_DIGEST_SIZE,</div><div class='del'>-	.halg.statesize         = sizeof(struct sahara_sha_reqctx),</div><div class='del'>-	.halg.base	= {</div><div class='del'>-		.cra_name		= "sha256",</div><div class='del'>-		.cra_driver_name	= "sahara-sha256",</div><div class='del'>-		.cra_priority		= 300,</div><div class='del'>-		.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='del'>-						CRYPTO_ALG_NEED_FALLBACK,</div><div class='del'>-		.cra_blocksize		= SHA256_BLOCK_SIZE,</div><div class='del'>-		.cra_ctxsize		= sizeof(struct sahara_ctx),</div><div class='del'>-		.cra_alignmask		= 0,</div><div class='del'>-		.cra_module		= THIS_MODULE,</div><div class='del'>-		.cra_init		= sahara_sha_cra_init,</div><div class='del'>-	}</div><div class='add'>+	.base = {</div><div class='add'>+		.init		= sahara_sha_init,</div><div class='add'>+		.update		= sahara_sha_update,</div><div class='add'>+		.final		= sahara_sha_final,</div><div class='add'>+		.finup		= sahara_sha_finup,</div><div class='add'>+		.digest		= sahara_sha_digest,</div><div class='add'>+		.export		= sahara_sha_export,</div><div class='add'>+		.import		= sahara_sha_import,</div><div class='add'>+		.halg.digestsize	= SHA256_DIGEST_SIZE,</div><div class='add'>+		.halg.statesize         = sizeof(struct sahara_sha_reqctx),</div><div class='add'>+		.halg.base	= {</div><div class='add'>+			.cra_name		= "sha256",</div><div class='add'>+			.cra_driver_name	= "sahara-sha256",</div><div class='add'>+			.cra_priority		= 300,</div><div class='add'>+			.cra_flags		= CRYPTO_ALG_ASYNC |</div><div class='add'>+							CRYPTO_ALG_NEED_FALLBACK,</div><div class='add'>+			.cra_blocksize		= SHA256_BLOCK_SIZE,</div><div class='add'>+			.cra_ctxsize		= sizeof(struct sahara_ctx),</div><div class='add'>+			.cra_alignmask		= 0,</div><div class='add'>+			.cra_module		= THIS_MODULE,</div><div class='add'>+			.cra_init		= sahara_sha_cra_init,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='add'>+	.op = {</div><div class='add'>+		.do_one_request = sahara_do_one_request,</div><div class='add'>+	},</div><div class='ctx'> },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1278,14 +1217,11 @@ static irqreturn_t sahara_irq_handler(int irq, void *data)</div><div class='ctx'> </div><div class='ctx'> 	sahara_decode_status(dev, stat);</div><div class='ctx'> </div><div class='del'>-	if (SAHARA_STATUS_GET_STATE(stat) == SAHARA_STATE_BUSY) {</div><div class='add'>+	if (SAHARA_STATUS_GET_STATE(stat) == SAHARA_STATE_BUSY)</div><div class='ctx'> 		return IRQ_NONE;</div><div class='del'>-	} else if (SAHARA_STATUS_GET_STATE(stat) == SAHARA_STATE_COMPLETE) {</div><div class='del'>-		dev-&gt;error = 0;</div><div class='del'>-	} else {</div><div class='add'>+</div><div class='add'>+	if (SAHARA_STATUS_GET_STATE(stat) != SAHARA_STATE_COMPLETE)</div><div class='ctx'> 		sahara_decode_error(dev, err);</div><div class='del'>-		dev-&gt;error = -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	complete(&amp;dev-&gt;dma_completion);</div><div class='ctx'> </div><div class='hunk'>@@ -1296,57 +1232,42 @@ static irqreturn_t sahara_irq_handler(int irq, void *data)</div><div class='ctx'> static int sahara_register_algs(struct sahara_dev *dev)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='del'>-	unsigned int i, j, k, l;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(aes_algs); i++) {</div><div class='del'>-		err = crypto_register_skcipher(&amp;aes_algs[i]);</div><div class='del'>-		if (err)</div><div class='del'>-			goto err_aes_algs;</div><div class='del'>-	}</div><div class='add'>+	err = crypto_engine_register_skciphers(aes_algs, ARRAY_SIZE(aes_algs));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = crypto_engine_register_ahashes(sha_v3_algs,</div><div class='add'>+					     ARRAY_SIZE(sha_v3_algs));</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_aes_algs;</div><div class='ctx'> </div><div class='del'>-	for (k = 0; k &lt; ARRAY_SIZE(sha_v3_algs); k++) {</div><div class='del'>-		err = crypto_register_ahash(&amp;sha_v3_algs[k]);</div><div class='add'>+	if (dev-&gt;version &gt; SAHARA_VERSION_3) {</div><div class='add'>+		err = crypto_engine_register_ahashes(sha_v4_algs,</div><div class='add'>+						     ARRAY_SIZE(sha_v4_algs));</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto err_sha_v3_algs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;version &gt; SAHARA_VERSION_3)</div><div class='del'>-		for (l = 0; l &lt; ARRAY_SIZE(sha_v4_algs); l++) {</div><div class='del'>-			err = crypto_register_ahash(&amp;sha_v4_algs[l]);</div><div class='del'>-			if (err)</div><div class='del'>-				goto err_sha_v4_algs;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err_sha_v4_algs:</div><div class='del'>-	for (j = 0; j &lt; l; j++)</div><div class='del'>-		crypto_unregister_ahash(&amp;sha_v4_algs[j]);</div><div class='del'>-</div><div class='ctx'> err_sha_v3_algs:</div><div class='del'>-	for (j = 0; j &lt; k; j++)</div><div class='del'>-		crypto_unregister_ahash(&amp;sha_v3_algs[j]);</div><div class='add'>+	crypto_engine_unregister_ahashes(sha_v3_algs, ARRAY_SIZE(sha_v3_algs));</div><div class='ctx'> </div><div class='ctx'> err_aes_algs:</div><div class='del'>-	for (j = 0; j &lt; i; j++)</div><div class='del'>-		crypto_unregister_skcipher(&amp;aes_algs[j]);</div><div class='add'>+	crypto_engine_unregister_skciphers(aes_algs, ARRAY_SIZE(aes_algs));</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sahara_unregister_algs(struct sahara_dev *dev)</div><div class='ctx'> {</div><div class='del'>-	unsigned int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(aes_algs); i++)</div><div class='del'>-		crypto_unregister_skcipher(&amp;aes_algs[i]);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(sha_v3_algs); i++)</div><div class='del'>-		crypto_unregister_ahash(&amp;sha_v3_algs[i]);</div><div class='add'>+	crypto_engine_unregister_skciphers(aes_algs, ARRAY_SIZE(aes_algs));</div><div class='add'>+	crypto_engine_unregister_ahashes(sha_v3_algs, ARRAY_SIZE(sha_v3_algs));</div><div class='ctx'> </div><div class='ctx'> 	if (dev-&gt;version &gt; SAHARA_VERSION_3)</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(sha_v4_algs); i++)</div><div class='del'>-			crypto_unregister_ahash(&amp;sha_v4_algs[i]);</div><div class='add'>+		crypto_engine_unregister_ahashes(sha_v4_algs,</div><div class='add'>+						 ARRAY_SIZE(sha_v4_algs));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id sahara_dt_ids[] = {</div><div class='hunk'>@@ -1383,32 +1304,27 @@ static int sahara_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	err = devm_request_irq(&amp;pdev-&gt;dev, irq, sahara_irq_handler,</div><div class='ctx'> 			       0, dev_name(&amp;pdev-&gt;dev), dev);</div><div class='del'>-	if (err) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "failed to request irq\n");</div><div class='del'>-		return err;</div><div class='del'>-	}</div><div class='add'>+	if (err)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, err,</div><div class='add'>+				     "failed to request irq\n");</div><div class='ctx'> </div><div class='ctx'> 	/* clocks */</div><div class='del'>-	dev-&gt;clk_ipg = devm_clk_get(&amp;pdev-&gt;dev, "ipg");</div><div class='del'>-	if (IS_ERR(dev-&gt;clk_ipg)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not get ipg clock\n");</div><div class='del'>-		return PTR_ERR(dev-&gt;clk_ipg);</div><div class='del'>-	}</div><div class='add'>+	dev-&gt;clk_ipg = devm_clk_get_enabled(&amp;pdev-&gt;dev, "ipg");</div><div class='add'>+	if (IS_ERR(dev-&gt;clk_ipg))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(dev-&gt;clk_ipg),</div><div class='add'>+				     "Could not get ipg clock\n");</div><div class='ctx'> </div><div class='del'>-	dev-&gt;clk_ahb = devm_clk_get(&amp;pdev-&gt;dev, "ahb");</div><div class='del'>-	if (IS_ERR(dev-&gt;clk_ahb)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not get ahb clock\n");</div><div class='del'>-		return PTR_ERR(dev-&gt;clk_ahb);</div><div class='del'>-	}</div><div class='add'>+	dev-&gt;clk_ahb = devm_clk_get_enabled(&amp;pdev-&gt;dev, "ahb");</div><div class='add'>+	if (IS_ERR(dev-&gt;clk_ahb))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(dev-&gt;clk_ahb),</div><div class='add'>+				     "Could not get ahb clock\n");</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate HW descriptors */</div><div class='ctx'> 	dev-&gt;hw_desc[0] = dmam_alloc_coherent(&amp;pdev-&gt;dev,</div><div class='ctx'> 			SAHARA_MAX_HW_DESC * sizeof(struct sahara_hw_desc),</div><div class='ctx'> 			&amp;dev-&gt;hw_phys_desc[0], GFP_KERNEL);</div><div class='del'>-	if (!dev-&gt;hw_desc[0]) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not allocate hw descriptors\n");</div><div class='add'>+	if (!dev-&gt;hw_desc[0])</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> 	dev-&gt;hw_desc[1] = dev-&gt;hw_desc[0] + 1;</div><div class='ctx'> 	dev-&gt;hw_phys_desc[1] = dev-&gt;hw_phys_desc[0] +</div><div class='ctx'> 				sizeof(struct sahara_hw_desc);</div><div class='hunk'>@@ -1416,10 +1332,8 @@ static int sahara_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* Allocate space for iv and key */</div><div class='ctx'> 	dev-&gt;key_base = dmam_alloc_coherent(&amp;pdev-&gt;dev, 2 * AES_KEYSIZE_128,</div><div class='ctx'> 				&amp;dev-&gt;key_phys_base, GFP_KERNEL);</div><div class='del'>-	if (!dev-&gt;key_base) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not allocate memory for key\n");</div><div class='add'>+	if (!dev-&gt;key_base)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> 	dev-&gt;iv_base = dev-&gt;key_base + AES_KEYSIZE_128;</div><div class='ctx'> 	dev-&gt;iv_phys_base = dev-&gt;key_phys_base + AES_KEYSIZE_128;</div><div class='ctx'> </div><div class='hunk'>@@ -1427,45 +1341,36 @@ static int sahara_probe(struct platform_device *pdev)</div><div class='ctx'> 	dev-&gt;context_base = dmam_alloc_coherent(&amp;pdev-&gt;dev,</div><div class='ctx'> 					SHA256_DIGEST_SIZE + 4,</div><div class='ctx'> 					&amp;dev-&gt;context_phys_base, GFP_KERNEL);</div><div class='del'>-	if (!dev-&gt;context_base) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not allocate memory for MDHA context\n");</div><div class='add'>+	if (!dev-&gt;context_base)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate space for HW links */</div><div class='ctx'> 	dev-&gt;hw_link[0] = dmam_alloc_coherent(&amp;pdev-&gt;dev,</div><div class='ctx'> 			SAHARA_MAX_HW_LINK * sizeof(struct sahara_hw_link),</div><div class='ctx'> 			&amp;dev-&gt;hw_phys_link[0], GFP_KERNEL);</div><div class='del'>-	if (!dev-&gt;hw_link[0]) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not allocate hw links\n");</div><div class='add'>+	if (!dev-&gt;hw_link[0])</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> 	for (i = 1; i &lt; SAHARA_MAX_HW_LINK; i++) {</div><div class='ctx'> 		dev-&gt;hw_phys_link[i] = dev-&gt;hw_phys_link[i - 1] +</div><div class='ctx'> 					sizeof(struct sahara_hw_link);</div><div class='ctx'> 		dev-&gt;hw_link[i] = dev-&gt;hw_link[i - 1] + 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	crypto_init_queue(&amp;dev-&gt;queue, SAHARA_QUEUE_LENGTH);</div><div class='del'>-</div><div class='del'>-	spin_lock_init(&amp;dev-&gt;queue_spinlock);</div><div class='del'>-</div><div class='ctx'> 	dev_ptr = dev;</div><div class='ctx'> </div><div class='del'>-	dev-&gt;kthread = kthread_run(sahara_queue_manage, dev, "sahara_crypto");</div><div class='del'>-	if (IS_ERR(dev-&gt;kthread)) {</div><div class='del'>-		return PTR_ERR(dev-&gt;kthread);</div><div class='add'>+	dev-&gt;engine = crypto_engine_alloc_init(&amp;pdev-&gt;dev, true);</div><div class='add'>+	if (!dev-&gt;engine)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	err = crypto_engine_start(dev-&gt;engine);</div><div class='add'>+	if (err) {</div><div class='add'>+		crypto_engine_exit(dev-&gt;engine);</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, err,</div><div class='add'>+				     "Could not start crypto engine\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	init_completion(&amp;dev-&gt;dma_completion);</div><div class='ctx'> </div><div class='del'>-	err = clk_prepare_enable(dev-&gt;clk_ipg);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='del'>-	err = clk_prepare_enable(dev-&gt;clk_ahb);</div><div class='del'>-	if (err)</div><div class='del'>-		goto clk_ipg_disable;</div><div class='del'>-</div><div class='ctx'> 	version = sahara_read(dev, SAHARA_REG_VERSION);</div><div class='ctx'> 	if (of_device_is_compatible(pdev-&gt;dev.of_node, "fsl,imx27-sahara")) {</div><div class='ctx'> 		if (version != SAHARA_VERSION_3)</div><div class='hunk'>@@ -1477,8 +1382,8 @@ static int sahara_probe(struct platform_device *pdev)</div><div class='ctx'> 		version = (version &gt;&gt; 8) &amp; 0xff;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err == -ENODEV) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "SAHARA version %d not supported\n",</div><div class='del'>-				version);</div><div class='add'>+		dev_err_probe(&amp;pdev-&gt;dev, err,</div><div class='add'>+			      "SAHARA version %d not supported\n", version);</div><div class='ctx'> 		goto err_algs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1501,11 +1406,7 @@ static int sahara_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_algs:</div><div class='del'>-	kthread_stop(dev-&gt;kthread);</div><div class='del'>-	dev_ptr = NULL;</div><div class='del'>-	clk_disable_unprepare(dev-&gt;clk_ahb);</div><div class='del'>-clk_ipg_disable:</div><div class='del'>-	clk_disable_unprepare(dev-&gt;clk_ipg);</div><div class='add'>+	crypto_engine_exit(dev-&gt;engine);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -1514,14 +1415,8 @@ static void sahara_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sahara_dev *dev = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	kthread_stop(dev-&gt;kthread);</div><div class='del'>-</div><div class='add'>+	crypto_engine_exit(dev-&gt;engine);</div><div class='ctx'> 	sahara_unregister_algs(dev);</div><div class='del'>-</div><div class='del'>-	clk_disable_unprepare(dev-&gt;clk_ipg);</div><div class='del'>-	clk_disable_unprepare(dev-&gt;clk_ahb);</div><div class='del'>-</div><div class='del'>-	dev_ptr = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sahara_driver = {</div><div class='head'>diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig<br/>index 2cb192502c1b..cb59357b58b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/starfive/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/Kconfig</a></div><div class='hunk'>@@ -4,7 +4,7 @@</div><div class='ctx'> </div><div class='ctx'> config CRYPTO_DEV_JH7110</div><div class='ctx'> 	tristate "StarFive JH7110 cryptographic engine driver"</div><div class='del'>-	depends on SOC_STARFIVE || AMBA_PL08X || COMPILE_TEST</div><div class='add'>+	depends on (SOC_STARFIVE &amp;&amp; AMBA_PL08X) || COMPILE_TEST</div><div class='ctx'> 	depends on HAS_DMA</div><div class='ctx'> 	select CRYPTO_ENGINE</div><div class='ctx'> 	select CRYPTO_HMAC</div><div class='head'>diff --git a/drivers/crypto/starfive/jh7110-aes.c b/drivers/crypto/starfive/jh7110-aes.c<br/>index 9378e6682f0e..1ac15cc4ef3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-aes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/starfive/jh7110-aes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-aes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-aes.c</a></div><div class='hunk'>@@ -262,12 +262,7 @@ static int starfive_aes_hw_init(struct starfive_cryp_ctx *ctx)</div><div class='ctx'> 	rctx-&gt;csr.aes.mode  = hw_mode;</div><div class='ctx'> 	rctx-&gt;csr.aes.cmode = !is_encrypt(cryp);</div><div class='ctx'> 	rctx-&gt;csr.aes.ie = 1;</div><div class='del'>-</div><div class='del'>-	if (hw_mode == STARFIVE_AES_MODE_CFB ||</div><div class='del'>-	    hw_mode == STARFIVE_AES_MODE_OFB)</div><div class='del'>-		rctx-&gt;csr.aes.stmode = STARFIVE_AES_MODE_XFB_128;</div><div class='del'>-	else</div><div class='del'>-		rctx-&gt;csr.aes.stmode = STARFIVE_AES_MODE_XFB_1;</div><div class='add'>+	rctx-&gt;csr.aes.stmode = STARFIVE_AES_MODE_XFB_1;</div><div class='ctx'> </div><div class='ctx'> 	if (cryp-&gt;side_chan) {</div><div class='ctx'> 		rctx-&gt;csr.aes.delay_aes = 1;</div><div class='hunk'>@@ -294,8 +289,6 @@ static int starfive_aes_hw_init(struct starfive_cryp_ctx *ctx)</div><div class='ctx'> 		starfive_aes_ccm_init(ctx);</div><div class='ctx'> 		starfive_aes_aead_hw_start(ctx, hw_mode);</div><div class='ctx'> 		break;</div><div class='del'>-	case STARFIVE_AES_MODE_OFB:</div><div class='del'>-	case STARFIVE_AES_MODE_CFB:</div><div class='ctx'> 	case STARFIVE_AES_MODE_CBC:</div><div class='ctx'> 	case STARFIVE_AES_MODE_CTR:</div><div class='ctx'> 		starfive_aes_write_iv(ctx, (void *)cryp-&gt;req.sreq-&gt;iv);</div><div class='hunk'>@@ -500,7 +493,7 @@ static int starfive_aes_prepare_req(struct skcipher_request *req,</div><div class='ctx'> 	scatterwalk_start(&amp;cryp-&gt;out_walk, rctx-&gt;out_sg);</div><div class='ctx'> </div><div class='ctx'> 	if (cryp-&gt;assoclen) {</div><div class='del'>-		rctx-&gt;adata = kzalloc(ALIGN(cryp-&gt;assoclen, AES_BLOCK_SIZE), GFP_KERNEL);</div><div class='add'>+		rctx-&gt;adata = kzalloc(cryp-&gt;assoclen + AES_BLOCK_SIZE, GFP_KERNEL);</div><div class='ctx'> 		if (!rctx-&gt;adata)</div><div class='ctx'> 			return dev_err_probe(cryp-&gt;dev, -ENOMEM,</div><div class='ctx'> 					     "Failed to alloc memory for adata");</div><div class='hunk'>@@ -569,7 +562,7 @@ static int starfive_aes_aead_do_one_req(struct crypto_engine *engine, void *areq</div><div class='ctx'> 	struct starfive_cryp_ctx *ctx =</div><div class='ctx'> 		crypto_aead_ctx(crypto_aead_reqtfm(req));</div><div class='ctx'> 	struct starfive_cryp_dev *cryp = ctx-&gt;cryp;</div><div class='del'>-	struct starfive_cryp_request_ctx *rctx = ctx-&gt;rctx;</div><div class='add'>+	struct starfive_cryp_request_ctx *rctx;</div><div class='ctx'> 	u32 block[AES_BLOCK_32];</div><div class='ctx'> 	u32 stat;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -579,6 +572,8 @@ static int starfive_aes_aead_do_one_req(struct crypto_engine *engine, void *areq</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='add'>+	rctx = ctx-&gt;rctx;</div><div class='add'>+</div><div class='ctx'> 	if (!cryp-&gt;assoclen)</div><div class='ctx'> 		goto write_text;</div><div class='ctx'> </div><div class='hunk'>@@ -783,26 +778,6 @@ static int starfive_aes_cbc_decrypt(struct skcipher_request *req)</div><div class='ctx'> 	return starfive_aes_crypt(req, STARFIVE_AES_MODE_CBC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int starfive_aes_cfb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return starfive_aes_crypt(req, STARFIVE_AES_MODE_CFB | FLG_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int starfive_aes_cfb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return starfive_aes_crypt(req, STARFIVE_AES_MODE_CFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int starfive_aes_ofb_encrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return starfive_aes_crypt(req, STARFIVE_AES_MODE_OFB | FLG_ENCRYPT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int starfive_aes_ofb_decrypt(struct skcipher_request *req)</div><div class='del'>-{</div><div class='del'>-	return starfive_aes_crypt(req, STARFIVE_AES_MODE_OFB);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int starfive_aes_ctr_encrypt(struct skcipher_request *req)</div><div class='ctx'> {</div><div class='ctx'> 	return starfive_aes_crypt(req, STARFIVE_AES_MODE_CTR | FLG_ENCRYPT);</div><div class='hunk'>@@ -908,48 +883,6 @@ static struct skcipher_engine_alg skcipher_algs[] = {</div><div class='ctx'> 	.op = {</div><div class='ctx'> 		.do_one_request = starfive_aes_do_one_req,</div><div class='ctx'> 	},</div><div class='del'>-}, {</div><div class='del'>-	.base.init			= starfive_aes_init_tfm,</div><div class='del'>-	.base.setkey			= starfive_aes_setkey,</div><div class='del'>-	.base.encrypt			= starfive_aes_cfb_encrypt,</div><div class='del'>-	.base.decrypt			= starfive_aes_cfb_decrypt,</div><div class='del'>-	.base.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.base.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.base.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-	.base.base = {</div><div class='del'>-		.cra_name		= "cfb(aes)",</div><div class='del'>-		.cra_driver_name	= "starfive-cfb-aes",</div><div class='del'>-		.cra_priority		= 200,</div><div class='del'>-		.cra_flags		= CRYPTO_ALG_ASYNC,</div><div class='del'>-		.cra_blocksize		= 1,</div><div class='del'>-		.cra_ctxsize		= sizeof(struct starfive_cryp_ctx),</div><div class='del'>-		.cra_alignmask		= 0xf,</div><div class='del'>-		.cra_module		= THIS_MODULE,</div><div class='del'>-	},</div><div class='del'>-	.op = {</div><div class='del'>-		.do_one_request = starfive_aes_do_one_req,</div><div class='del'>-	},</div><div class='del'>-}, {</div><div class='del'>-	.base.init			= starfive_aes_init_tfm,</div><div class='del'>-	.base.setkey			= starfive_aes_setkey,</div><div class='del'>-	.base.encrypt			= starfive_aes_ofb_encrypt,</div><div class='del'>-	.base.decrypt			= starfive_aes_ofb_decrypt,</div><div class='del'>-	.base.min_keysize		= AES_MIN_KEY_SIZE,</div><div class='del'>-	.base.max_keysize		= AES_MAX_KEY_SIZE,</div><div class='del'>-	.base.ivsize			= AES_BLOCK_SIZE,</div><div class='del'>-	.base.base = {</div><div class='del'>-		.cra_name		= "ofb(aes)",</div><div class='del'>-		.cra_driver_name	= "starfive-ofb-aes",</div><div class='del'>-		.cra_priority		= 200,</div><div class='del'>-		.cra_flags		= CRYPTO_ALG_ASYNC,</div><div class='del'>-		.cra_blocksize		= 1,</div><div class='del'>-		.cra_ctxsize		= sizeof(struct starfive_cryp_ctx),</div><div class='del'>-		.cra_alignmask		= 0xf,</div><div class='del'>-		.cra_module		= THIS_MODULE,</div><div class='del'>-	},</div><div class='del'>-	.op = {</div><div class='del'>-		.do_one_request = starfive_aes_do_one_req,</div><div class='del'>-	},</div><div class='ctx'> },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c<br/>index 08e974e0dd12..425fddf3a8ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-cryp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/starfive/jh7110-cryp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-cryp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-cryp.c</a></div><div class='hunk'>@@ -109,12 +109,6 @@ static irqreturn_t starfive_cryp_irq(int irq, void *priv)</div><div class='ctx'> 		tasklet_schedule(&amp;cryp-&gt;hash_done);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (status &amp; STARFIVE_IE_FLAG_PKA_DONE) {</div><div class='del'>-		mask |= STARFIVE_IE_MASK_PKA_DONE;</div><div class='del'>-		writel(mask, cryp-&gt;base + STARFIVE_IE_MASK_OFFSET);</div><div class='del'>-		complete(&amp;cryp-&gt;pka_done);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -159,8 +153,6 @@ static int starfive_cryp_probe(struct platform_device *pdev)</div><div class='ctx'> 		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(cryp-&gt;rst),</div><div class='ctx'> 				     "Error getting hardware reset line\n");</div><div class='ctx'> </div><div class='del'>-	init_completion(&amp;cryp-&gt;pka_done);</div><div class='del'>-</div><div class='ctx'> 	irq = platform_get_irq(pdev, 0);</div><div class='ctx'> 	if (irq &lt; 0)</div><div class='ctx'> 		return irq;</div><div class='hunk'>@@ -168,7 +160,7 @@ static int starfive_cryp_probe(struct platform_device *pdev)</div><div class='ctx'> 	ret = devm_request_irq(&amp;pdev-&gt;dev, irq, starfive_cryp_irq, 0, pdev-&gt;name,</div><div class='ctx'> 			       (void *)cryp);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(&amp;pdev-&gt;dev, irq,</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, ret,</div><div class='ctx'> 				     "Failed to register interrupt handler\n");</div><div class='ctx'> </div><div class='ctx'> 	clk_prepare_enable(cryp-&gt;hclk);</div><div class='hunk'>@@ -180,12 +172,8 @@ static int starfive_cryp_probe(struct platform_device *pdev)</div><div class='ctx'> 	spin_unlock(&amp;dev_list.lock);</div><div class='ctx'> </div><div class='ctx'> 	ret = starfive_dma_init(cryp);</div><div class='del'>-	if (ret) {</div><div class='del'>-		if (ret == -EPROBE_DEFER)</div><div class='del'>-			goto err_probe_defer;</div><div class='del'>-		else</div><div class='del'>-			goto err_dma_init;</div><div class='del'>-	}</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_dma_init;</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize crypto engine */</div><div class='ctx'> 	cryp-&gt;engine = crypto_engine_alloc_init(&amp;pdev-&gt;dev, 1);</div><div class='hunk'>@@ -233,7 +221,7 @@ err_dma_init:</div><div class='ctx'> </div><div class='ctx'> 	tasklet_kill(&amp;cryp-&gt;aes_done);</div><div class='ctx'> 	tasklet_kill(&amp;cryp-&gt;hash_done);</div><div class='del'>-err_probe_defer:</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfive/jh7110-cryp.h<br/>index fe011d50473d..6cdf6db5d904 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-cryp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/starfive/jh7110-cryp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-cryp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-cryp.h</a></div><div class='hunk'>@@ -50,8 +50,6 @@ union starfive_aes_csr {</div><div class='ctx'> 		u32 ccm_start			:1;</div><div class='ctx'> #define STARFIVE_AES_MODE_ECB			0x0</div><div class='ctx'> #define STARFIVE_AES_MODE_CBC			0x1</div><div class='del'>-#define STARFIVE_AES_MODE_CFB			0x2</div><div class='del'>-#define STARFIVE_AES_MODE_OFB			0x3</div><div class='ctx'> #define STARFIVE_AES_MODE_CTR			0x4</div><div class='ctx'> #define STARFIVE_AES_MODE_CCM			0x5</div><div class='ctx'> #define STARFIVE_AES_MODE_GCM			0x6</div><div class='hunk'>@@ -125,6 +123,15 @@ union starfive_pka_cacr {</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+union starfive_pka_casr {</div><div class='add'>+	u32 v;</div><div class='add'>+	struct {</div><div class='add'>+#define STARFIVE_PKA_DONE			BIT(0)</div><div class='add'>+		u32 done			:1;</div><div class='add'>+		u32 rsvd_0			:31;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct starfive_rsa_key {</div><div class='ctx'> 	u8	*n;</div><div class='ctx'> 	u8	*e;</div><div class='hunk'>@@ -183,7 +190,6 @@ struct starfive_cryp_dev {</div><div class='ctx'> 	struct crypto_engine			*engine;</div><div class='ctx'> 	struct tasklet_struct			aes_done;</div><div class='ctx'> 	struct tasklet_struct			hash_done;</div><div class='del'>-	struct completion			pka_done;</div><div class='ctx'> 	size_t					assoclen;</div><div class='ctx'> 	size_t					total_in;</div><div class='ctx'> 	size_t					total_out;</div><div class='head'>diff --git a/drivers/crypto/starfive/jh7110-rsa.c b/drivers/crypto/starfive/jh7110-rsa.c<br/>index f31bbd825f88..cf8bda7f0855 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-rsa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/starfive/jh7110-rsa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/starfive/jh7110-rsa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/starfive/jh7110-rsa.c</a></div><div class='hunk'>@@ -6,13 +6,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/crypto.h&gt;</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/dma-direct.h&gt;</div><div class='del'>-#include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='del'>-#include &lt;linux/io.h&gt;</div><div class='del'>-#include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;crypto/akcipher.h&gt;</div><div class='ctx'> #include &lt;crypto/algapi.h&gt;</div><div class='ctx'> #include &lt;crypto/internal/akcipher.h&gt;</div><div class='hunk'>@@ -28,13 +22,13 @@</div><div class='ctx'> #define STARFIVE_PKA_CAER_OFFSET	(STARFIVE_PKA_REGS_OFFSET + 0x108)</div><div class='ctx'> #define STARFIVE_PKA_CANR_OFFSET	(STARFIVE_PKA_REGS_OFFSET + 0x208)</div><div class='ctx'> </div><div class='del'>-// R^2 mod N and N0'</div><div class='add'>+/* R ^ 2 mod N and N0' */</div><div class='ctx'> #define CRYPTO_CMD_PRE			0x0</div><div class='del'>-// A * R mod N   ==&gt; A</div><div class='add'>+/* A * R mod N   ==&gt; A */</div><div class='ctx'> #define CRYPTO_CMD_ARN			0x5</div><div class='del'>-// A * E * R mod N ==&gt; A</div><div class='add'>+/* A * E * R mod N ==&gt; A */</div><div class='ctx'> #define CRYPTO_CMD_AERN			0x6</div><div class='del'>-// A * A * R mod N ==&gt; A</div><div class='add'>+/* A * A * R mod N ==&gt; A */</div><div class='ctx'> #define CRYPTO_CMD_AARN			0x7</div><div class='ctx'> </div><div class='ctx'> #define STARFIVE_RSA_MAX_KEYSZ		256</div><div class='hunk'>@@ -43,31 +37,17 @@</div><div class='ctx'> static inline int starfive_pka_wait_done(struct starfive_cryp_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct starfive_cryp_dev *cryp = ctx-&gt;cryp;</div><div class='add'>+	u32 status;</div><div class='ctx'> </div><div class='del'>-	return wait_for_completion_timeout(&amp;cryp-&gt;pka_done,</div><div class='del'>-					   usecs_to_jiffies(100000));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void starfive_pka_irq_mask_clear(struct starfive_cryp_ctx *ctx)</div><div class='del'>-{</div><div class='del'>-	struct starfive_cryp_dev *cryp = ctx-&gt;cryp;</div><div class='del'>-	u32 stat;</div><div class='del'>-</div><div class='del'>-	stat = readl(cryp-&gt;base + STARFIVE_IE_MASK_OFFSET);</div><div class='del'>-	stat &amp;= ~STARFIVE_IE_MASK_PKA_DONE;</div><div class='del'>-	writel(stat, cryp-&gt;base + STARFIVE_IE_MASK_OFFSET);</div><div class='del'>-</div><div class='del'>-	reinit_completion(&amp;cryp-&gt;pka_done);</div><div class='add'>+	return readl_relaxed_poll_timeout(cryp-&gt;base + STARFIVE_PKA_CASR_OFFSET, status,</div><div class='add'>+					  status &amp; STARFIVE_PKA_DONE, 10, 100000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void starfive_rsa_free_key(struct starfive_rsa_key *key)</div><div class='ctx'> {</div><div class='del'>-	if (key-&gt;d)</div><div class='del'>-		kfree_sensitive(key-&gt;d);</div><div class='del'>-	if (key-&gt;e)</div><div class='del'>-		kfree_sensitive(key-&gt;e);</div><div class='del'>-	if (key-&gt;n)</div><div class='del'>-		kfree_sensitive(key-&gt;n);</div><div class='add'>+	kfree_sensitive(key-&gt;d);</div><div class='add'>+	kfree_sensitive(key-&gt;e);</div><div class='add'>+	kfree_sensitive(key-&gt;n);</div><div class='ctx'> 	memset(key, 0, sizeof(*key));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -114,10 +94,9 @@ static int starfive_rsa_montgomery_form(struct starfive_cryp_ctx *ctx,</div><div class='ctx'> 		rctx-&gt;csr.pka.not_r2 = 1;</div><div class='ctx'> 		rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-		starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 		writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='del'>-		if (!starfive_pka_wait_done(ctx))</div><div class='add'>+		if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 			return -ETIMEDOUT;</div><div class='ctx'> </div><div class='ctx'> 		for (loop = 0; loop &lt;= opsize; loop++)</div><div class='hunk'>@@ -136,10 +115,9 @@ static int starfive_rsa_montgomery_form(struct starfive_cryp_ctx *ctx,</div><div class='ctx'> 		rctx-&gt;csr.pka.start = 1;</div><div class='ctx'> 		rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-		starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 		writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='del'>-		if (!starfive_pka_wait_done(ctx))</div><div class='add'>+		if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 			return -ETIMEDOUT;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		rctx-&gt;csr.pka.v = 0;</div><div class='hunk'>@@ -151,10 +129,9 @@ static int starfive_rsa_montgomery_form(struct starfive_cryp_ctx *ctx,</div><div class='ctx'> 		rctx-&gt;csr.pka.pre_expf = 1;</div><div class='ctx'> 		rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-		starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 		writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='del'>-		if (!starfive_pka_wait_done(ctx))</div><div class='add'>+		if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 			return -ETIMEDOUT;</div><div class='ctx'> </div><div class='ctx'> 		for (loop = 0; loop &lt;= count; loop++)</div><div class='hunk'>@@ -172,10 +149,9 @@ static int starfive_rsa_montgomery_form(struct starfive_cryp_ctx *ctx,</div><div class='ctx'> 		rctx-&gt;csr.pka.start = 1;</div><div class='ctx'> 		rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-		starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 		writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='del'>-		if (!starfive_pka_wait_done(ctx))</div><div class='add'>+		if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 			return -ETIMEDOUT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -226,11 +202,10 @@ static int starfive_rsa_cpu_start(struct starfive_cryp_ctx *ctx, u32 *result,</div><div class='ctx'> 		rctx-&gt;csr.pka.start = 1;</div><div class='ctx'> 		rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-		starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 		writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='ctx'> 		ret = -ETIMEDOUT;</div><div class='del'>-		if (!starfive_pka_wait_done(ctx))</div><div class='add'>+		if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 			goto rsa_err;</div><div class='ctx'> </div><div class='ctx'> 		if (mlen) {</div><div class='hunk'>@@ -242,10 +217,9 @@ static int starfive_rsa_cpu_start(struct starfive_cryp_ctx *ctx, u32 *result,</div><div class='ctx'> 			rctx-&gt;csr.pka.start = 1;</div><div class='ctx'> 			rctx-&gt;csr.pka.ie = 1;</div><div class='ctx'> </div><div class='del'>-			starfive_pka_irq_mask_clear(ctx);</div><div class='ctx'> 			writel(rctx-&gt;csr.pka.v, cryp-&gt;base + STARFIVE_PKA_CACR_OFFSET);</div><div class='ctx'> </div><div class='del'>-			if (!starfive_pka_wait_done(ctx))</div><div class='add'>+			if (starfive_pka_wait_done(ctx))</div><div class='ctx'> 				goto rsa_err;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/crypto/stm32/stm32-crc32.c b/drivers/crypto/stm32/stm32-crc32.c<br/>index b2d5c8921ab3..b0cf6d2fd352 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/stm32/stm32-crc32.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/stm32/stm32-crc32.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/stm32/stm32-crc32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/stm32/stm32-crc32.c</a></div><div class='hunk'>@@ -104,7 +104,7 @@ static struct stm32_crc *stm32_crc_get_next_crc(void)</div><div class='ctx'> 	struct stm32_crc *crc;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;crc_list.lock);</div><div class='del'>-	crc = list_first_entry(&amp;crc_list.dev_list, struct stm32_crc, list);</div><div class='add'>+	crc = list_first_entry_or_null(&amp;crc_list.dev_list, struct stm32_crc, list);</div><div class='ctx'> 	if (crc)</div><div class='ctx'> 		list_move_tail(&amp;crc-&gt;list, &amp;crc_list.dev_list);</div><div class='ctx'> 	spin_unlock_bh(&amp;crc_list.lock);</div><div class='head'>diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c<br/>index c3cbc2673338..11ad4ffdce0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/stm32/stm32-cryp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/stm32/stm32-cryp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/stm32/stm32-cryp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/stm32/stm32-cryp.c</a></div><div class='hunk'>@@ -838,7 +838,7 @@ static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq);</div><div class='ctx'> </div><div class='ctx'> static int stm32_cryp_aes_aead_init(struct crypto_aead *tfm)</div><div class='ctx'> {</div><div class='del'>-	tfm-&gt;reqsize = sizeof(struct stm32_cryp_reqctx);</div><div class='add'>+	crypto_aead_set_reqsize(tfm, sizeof(struct stm32_cryp_reqctx));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/crypto/virtio/virtio_crypto_common.h b/drivers/crypto/virtio/virtio_crypto_common.h<br/>index 154590e1f764..7059bbe5a2eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/virtio/virtio_crypto_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/virtio/virtio_crypto_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/virtio/virtio_crypto_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/virtio/virtio_crypto_common.h</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> #include &lt;linux/virtio.h&gt;</div><div class='ctx'> #include &lt;linux/crypto.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;crypto/aead.h&gt;</div><div class='ctx'> #include &lt;crypto/aes.h&gt;</div><div class='ctx'> #include &lt;crypto/engine.h&gt;</div><div class='hunk'>@@ -28,6 +29,7 @@ struct data_queue {</div><div class='ctx'> 	char name[32];</div><div class='ctx'> </div><div class='ctx'> 	struct crypto_engine *engine;</div><div class='add'>+	struct tasklet_struct done_task;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct virtio_crypto {</div><div class='head'>diff --git a/drivers/crypto/virtio/virtio_crypto_core.c b/drivers/crypto/virtio/virtio_crypto_core.c<br/>index 43a0838d31ff..b909c6a2bf1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/crypto/virtio/virtio_crypto_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/crypto/virtio/virtio_crypto_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/crypto/virtio/virtio_crypto_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/crypto/virtio/virtio_crypto_core.c</a></div><div class='hunk'>@@ -72,27 +72,28 @@ int virtio_crypto_ctrl_vq_request(struct virtio_crypto *vcrypto, struct scatterl</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void virtcrypto_dataq_callback(struct virtqueue *vq)</div><div class='add'>+static void virtcrypto_done_task(unsigned long data)</div><div class='ctx'> {</div><div class='del'>-	struct virtio_crypto *vcrypto = vq-&gt;vdev-&gt;priv;</div><div class='add'>+	struct data_queue *data_vq = (struct data_queue *)data;</div><div class='add'>+	struct virtqueue *vq = data_vq-&gt;vq;</div><div class='ctx'> 	struct virtio_crypto_request *vc_req;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	unsigned int len;</div><div class='del'>-	unsigned int qid = vq-&gt;index;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;vcrypto-&gt;data_vq[qid].lock, flags);</div><div class='ctx'> 	do {</div><div class='ctx'> 		virtqueue_disable_cb(vq);</div><div class='ctx'> 		while ((vc_req = virtqueue_get_buf(vq, &amp;len)) != NULL) {</div><div class='del'>-			spin_unlock_irqrestore(</div><div class='del'>-				&amp;vcrypto-&gt;data_vq[qid].lock, flags);</div><div class='ctx'> 			if (vc_req-&gt;alg_cb)</div><div class='ctx'> 				vc_req-&gt;alg_cb(vc_req, len);</div><div class='del'>-			spin_lock_irqsave(</div><div class='del'>-				&amp;vcrypto-&gt;data_vq[qid].lock, flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	} while (!virtqueue_enable_cb(vq));</div><div class='del'>-	spin_unlock_irqrestore(&amp;vcrypto-&gt;data_vq[qid].lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void virtcrypto_dataq_callback(struct virtqueue *vq)</div><div class='add'>+{</div><div class='add'>+	struct virtio_crypto *vcrypto = vq-&gt;vdev-&gt;priv;</div><div class='add'>+	struct data_queue *dq = &amp;vcrypto-&gt;data_vq[vq-&gt;index];</div><div class='add'>+</div><div class='add'>+	tasklet_schedule(&amp;dq-&gt;done_task);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int virtcrypto_find_vqs(struct virtio_crypto *vi)</div><div class='hunk'>@@ -150,6 +151,8 @@ static int virtcrypto_find_vqs(struct virtio_crypto *vi)</div><div class='ctx'> 			ret = -ENOMEM;</div><div class='ctx'> 			goto err_engine;</div><div class='ctx'> 		}</div><div class='add'>+		tasklet_init(&amp;vi-&gt;data_vq[i].done_task, virtcrypto_done_task,</div><div class='add'>+				(unsigned long)&amp;vi-&gt;data_vq[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	kfree(names);</div><div class='hunk'>@@ -497,12 +500,15 @@ static void virtcrypto_free_unused_reqs(struct virtio_crypto *vcrypto)</div><div class='ctx'> static void virtcrypto_remove(struct virtio_device *vdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct virtio_crypto *vcrypto = vdev-&gt;priv;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	dev_info(&amp;vdev-&gt;dev, "Start virtcrypto_remove.\n");</div><div class='ctx'> </div><div class='ctx'> 	flush_work(&amp;vcrypto-&gt;config_work);</div><div class='ctx'> 	if (virtcrypto_dev_started(vcrypto))</div><div class='ctx'> 		virtcrypto_dev_stop(vcrypto);</div><div class='add'>+	for (i = 0; i &lt; vcrypto-&gt;max_data_queues; i++)</div><div class='add'>+		tasklet_kill(&amp;vcrypto-&gt;data_vq[i].done_task);</div><div class='ctx'> 	virtio_reset_device(vdev);</div><div class='ctx'> 	virtcrypto_free_unused_reqs(vcrypto);</div><div class='ctx'> 	virtcrypto_clear_crypto_engines(vcrypto);</div><div class='head'>diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig<br/>index 8ea1d340e438..67998dbd1d46 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/Kconfig</a></div><div class='hunk'>@@ -5,6 +5,7 @@ menuconfig CXL_BUS</div><div class='ctx'> 	select FW_LOADER</div><div class='ctx'> 	select FW_UPLOAD</div><div class='ctx'> 	select PCI_DOE</div><div class='add'>+	select FIRMWARE_TABLE</div><div class='ctx'> 	help</div><div class='ctx'> 	  CXL is a bus that is electrically compatible with PCI Express, but</div><div class='ctx'> 	  layers three protocols on that signalling (CXL.io, CXL.cache, and</div><div class='hunk'>@@ -54,8 +55,10 @@ config CXL_MEM_RAW_COMMANDS</div><div class='ctx'> config CXL_ACPI</div><div class='ctx'> 	tristate "CXL ACPI: Platform Support"</div><div class='ctx'> 	depends on ACPI</div><div class='add'>+	depends on ACPI_NUMA</div><div class='ctx'> 	default CXL_BUS</div><div class='ctx'> 	select ACPI_TABLE_LIB</div><div class='add'>+	select ACPI_HMAT</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enable support for host managed device memory (HDM) resources</div><div class='ctx'> 	  published by a platform's ACPI CXL memory layout description.  See</div><div class='head'>diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c<br/>index 2034eb4ce83f..dcf2b39e1048 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/acpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/acpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/acpi.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/node.h&gt;</div><div class='ctx'> #include &lt;asm/div64.h&gt;</div><div class='ctx'> #include "cxlpci.h"</div><div class='ctx'> #include "cxl.h"</div><div class='hunk'>@@ -17,6 +18,10 @@ struct cxl_cxims_data {</div><div class='ctx'> 	u64 xormaps[] __counted_by(nr_maps);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const guid_t acpi_cxl_qtg_id_guid =</div><div class='add'>+	GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,</div><div class='add'>+		  0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Find a targets entry (n) in the host bridge interleave list.</div><div class='ctx'>  * CXL Specification 3.0 Table 9-22</div><div class='hunk'>@@ -194,6 +199,123 @@ struct cxl_cfmws_context {</div><div class='ctx'> 	int id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM</div><div class='add'>+ * @handle: ACPI handle</div><div class='add'>+ * @coord: performance access coordinates</div><div class='add'>+ * @entries: number of QTG IDs to return</div><div class='add'>+ * @qos_class: int array provided by caller to return QTG IDs</div><div class='add'>+ *</div><div class='add'>+ * Return: number of QTG IDs returned, or -errno for errors</div><div class='add'>+ *</div><div class='add'>+ * Issue QTG _DSM with accompanied bandwidth and latency data in order to get</div><div class='add'>+ * the QTG IDs that are suitable for the performance point in order of most</div><div class='add'>+ * suitable to least suitable. Write back array of QTG IDs and return the</div><div class='add'>+ * actual number of QTG IDs written back.</div><div class='add'>+ */</div><div class='add'>+static int</div><div class='add'>+cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,</div><div class='add'>+			  int entries, int *qos_class)</div><div class='add'>+{</div><div class='add'>+	union acpi_object *out_obj, *out_buf, *obj;</div><div class='add'>+	union acpi_object in_array[4] = {</div><div class='add'>+		[0].integer = { ACPI_TYPE_INTEGER, coord-&gt;read_latency },</div><div class='add'>+		[1].integer = { ACPI_TYPE_INTEGER, coord-&gt;write_latency },</div><div class='add'>+		[2].integer = { ACPI_TYPE_INTEGER, coord-&gt;read_bandwidth },</div><div class='add'>+		[3].integer = { ACPI_TYPE_INTEGER, coord-&gt;write_bandwidth },</div><div class='add'>+	};</div><div class='add'>+	union acpi_object in_obj = {</div><div class='add'>+		.package = {</div><div class='add'>+			.type = ACPI_TYPE_PACKAGE,</div><div class='add'>+			.count = 4,</div><div class='add'>+			.elements = in_array,</div><div class='add'>+		},</div><div class='add'>+	};</div><div class='add'>+	int count, pkg_entries, i;</div><div class='add'>+	u16 max_qtg;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (!entries)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	out_obj = acpi_evaluate_dsm(handle, &amp;acpi_cxl_qtg_id_guid, 1, 1, &amp;in_obj);</div><div class='add'>+	if (!out_obj)</div><div class='add'>+		return -ENXIO;</div><div class='add'>+</div><div class='add'>+	if (out_obj-&gt;type != ACPI_TYPE_PACKAGE) {</div><div class='add'>+		rc = -ENXIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check Max QTG ID */</div><div class='add'>+	obj = &amp;out_obj-&gt;package.elements[0];</div><div class='add'>+	if (obj-&gt;type != ACPI_TYPE_INTEGER) {</div><div class='add'>+		rc = -ENXIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	max_qtg = obj-&gt;integer.value;</div><div class='add'>+</div><div class='add'>+	/* It's legal to have 0 QTG entries */</div><div class='add'>+	pkg_entries = out_obj-&gt;package.count;</div><div class='add'>+	if (pkg_entries &lt;= 1) {</div><div class='add'>+		rc = 0;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Retrieve QTG IDs package */</div><div class='add'>+	obj = &amp;out_obj-&gt;package.elements[1];</div><div class='add'>+	if (obj-&gt;type != ACPI_TYPE_PACKAGE) {</div><div class='add'>+		rc = -ENXIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pkg_entries = obj-&gt;package.count;</div><div class='add'>+	count = min(entries, pkg_entries);</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		u16 qtg_id;</div><div class='add'>+</div><div class='add'>+		out_buf = &amp;obj-&gt;package.elements[i];</div><div class='add'>+		if (out_buf-&gt;type != ACPI_TYPE_INTEGER) {</div><div class='add'>+			rc = -ENXIO;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		qtg_id = out_buf-&gt;integer.value;</div><div class='add'>+		if (qtg_id &gt; max_qtg)</div><div class='add'>+			pr_warn("QTG ID %u greater than MAX %u\n",</div><div class='add'>+				qtg_id, max_qtg);</div><div class='add'>+</div><div class='add'>+		qos_class[i] = qtg_id;</div><div class='add'>+	}</div><div class='add'>+	rc = count;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	ACPI_FREE(out_obj);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cxl_acpi_qos_class(struct cxl_root *cxl_root,</div><div class='add'>+			      struct access_coordinate *coord, int entries,</div><div class='add'>+			      int *qos_class)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = cxl_root-&gt;port.uport_dev;</div><div class='add'>+	acpi_handle handle;</div><div class='add'>+</div><div class='add'>+	if (!dev_is_platform(dev))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	handle = ACPI_HANDLE(dev);</div><div class='add'>+	if (!handle)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	return cxl_acpi_evaluate_qtg_dsm(handle, coord, entries, qos_class);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct cxl_root_ops acpi_root_ops = {</div><div class='add'>+	.qos_class = cxl_acpi_qos_class,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,</div><div class='ctx'> 			   const unsigned long end)</div><div class='ctx'> {</div><div class='hunk'>@@ -389,8 +511,29 @@ static int cxl_get_chbs(struct device *dev, struct acpi_device *hb,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)</div><div class='add'>+{</div><div class='add'>+	struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);</div><div class='add'>+	u32 uid;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (kstrtou32(acpi_device_uid(hb), 0, &amp;uid))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	rc = acpi_get_genport_coordinates(uid, &amp;dport-&gt;hb_coord);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	/* Adjust back to picoseconds from nanoseconds */</div><div class='add'>+	dport-&gt;hb_coord.read_latency *= 1000;</div><div class='add'>+	dport-&gt;hb_coord.write_latency *= 1000;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int add_host_bridge_dport(struct device *match, void *arg)</div><div class='ctx'> {</div><div class='add'>+	int ret;</div><div class='ctx'> 	acpi_status rc;</div><div class='ctx'> 	struct device *bridge;</div><div class='ctx'> 	struct cxl_dport *dport;</div><div class='hunk'>@@ -440,6 +583,10 @@ static int add_host_bridge_dport(struct device *match, void *arg)</div><div class='ctx'> 	if (IS_ERR(dport))</div><div class='ctx'> 		return PTR_ERR(dport);</div><div class='ctx'> </div><div class='add'>+	ret = get_genport_coordinates(match, dport);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_dbg(match, "Failed to get generic port perf coordinates.\n");</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -656,6 +803,7 @@ static int cxl_acpi_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	struct resource *cxl_res;</div><div class='add'>+	struct cxl_root *cxl_root;</div><div class='ctx'> 	struct cxl_port *root_port;</div><div class='ctx'> 	struct device *host = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct acpi_device *adev = ACPI_COMPANION(host);</div><div class='hunk'>@@ -675,9 +823,10 @@ static int cxl_acpi_probe(struct platform_device *pdev)</div><div class='ctx'> 	cxl_res-&gt;end = -1;</div><div class='ctx'> 	cxl_res-&gt;flags = IORESOURCE_MEM;</div><div class='ctx'> </div><div class='del'>-	root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);</div><div class='del'>-	if (IS_ERR(root_port))</div><div class='del'>-		return PTR_ERR(root_port);</div><div class='add'>+	cxl_root = devm_cxl_add_root(host, &amp;acpi_root_ops);</div><div class='add'>+	if (IS_ERR(cxl_root))</div><div class='add'>+		return PTR_ERR(cxl_root);</div><div class='add'>+	root_port = &amp;cxl_root-&gt;port;</div><div class='ctx'> </div><div class='ctx'> 	rc = bus_for_each_dev(adev-&gt;dev.bus, NULL, root_port,</div><div class='ctx'> 			      add_host_bridge_dport);</div><div class='head'>diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile<br/>index 1f66b5d4d935..9259bcc6773c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/Makefile</a></div><div class='hunk'>@@ -13,5 +13,6 @@ cxl_core-y += mbox.o</div><div class='ctx'> cxl_core-y += pci.o</div><div class='ctx'> cxl_core-y += hdm.o</div><div class='ctx'> cxl_core-y += pmu.o</div><div class='add'>+cxl_core-y += cdat.o</div><div class='ctx'> cxl_core-$(CONFIG_TRACING) += trace.o</div><div class='ctx'> cxl_core-$(CONFIG_CXL_REGION) += region.o</div><div class='head'>diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c<br/>new file mode 100644<br/>index 000000000000..6fe11546889f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/cdat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/cdat.c</a></div><div class='hunk'>@@ -0,0 +1,521 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation. All rights reserved. */</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+#include &lt;linux/fw_table.h&gt;</div><div class='add'>+#include &lt;linux/node.h&gt;</div><div class='add'>+#include &lt;linux/overflow.h&gt;</div><div class='add'>+#include "cxlpci.h"</div><div class='add'>+#include "cxlmem.h"</div><div class='add'>+#include "core.h"</div><div class='add'>+#include "cxl.h"</div><div class='add'>+</div><div class='add'>+struct dsmas_entry {</div><div class='add'>+	struct range dpa_range;</div><div class='add'>+	u8 handle;</div><div class='add'>+	struct access_coordinate coord;</div><div class='add'>+</div><div class='add'>+	int entries;</div><div class='add'>+	int qos_class;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,</div><div class='add'>+			      const unsigned long end)</div><div class='add'>+{</div><div class='add'>+	struct acpi_cdat_header *hdr = &amp;header-&gt;cdat;</div><div class='add'>+	struct acpi_cdat_dsmas *dsmas;</div><div class='add'>+	int size = sizeof(*hdr) + sizeof(*dsmas);</div><div class='add'>+	struct xarray *dsmas_xa = arg;</div><div class='add'>+	struct dsmas_entry *dent;</div><div class='add'>+	u16 len;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	len = le16_to_cpu((__force __le16)hdr-&gt;length);</div><div class='add'>+	if (len != size || (unsigned long)hdr + len &gt; end) {</div><div class='add'>+		pr_warn("Malformed DSMAS table length: (%u:%u)\n", size, len);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Skip common header */</div><div class='add'>+	dsmas = (struct acpi_cdat_dsmas *)(hdr + 1);</div><div class='add'>+</div><div class='add'>+	dent = kzalloc(sizeof(*dent), GFP_KERNEL);</div><div class='add'>+	if (!dent)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	dent-&gt;handle = dsmas-&gt;dsmad_handle;</div><div class='add'>+	dent-&gt;dpa_range.start = le64_to_cpu((__force __le64)dsmas-&gt;dpa_base_address);</div><div class='add'>+	dent-&gt;dpa_range.end = le64_to_cpu((__force __le64)dsmas-&gt;dpa_base_address) +</div><div class='add'>+			      le64_to_cpu((__force __le64)dsmas-&gt;dpa_length) - 1;</div><div class='add'>+</div><div class='add'>+	rc = xa_insert(dsmas_xa, dent-&gt;handle, dent, GFP_KERNEL);</div><div class='add'>+	if (rc) {</div><div class='add'>+		kfree(dent);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void cxl_access_coordinate_set(struct access_coordinate *coord,</div><div class='add'>+				      int access, unsigned int val)</div><div class='add'>+{</div><div class='add'>+	switch (access) {</div><div class='add'>+	case ACPI_HMAT_ACCESS_LATENCY:</div><div class='add'>+		coord-&gt;read_latency = val;</div><div class='add'>+		coord-&gt;write_latency = val;</div><div class='add'>+		break;</div><div class='add'>+	case ACPI_HMAT_READ_LATENCY:</div><div class='add'>+		coord-&gt;read_latency = val;</div><div class='add'>+		break;</div><div class='add'>+	case ACPI_HMAT_WRITE_LATENCY:</div><div class='add'>+		coord-&gt;write_latency = val;</div><div class='add'>+		break;</div><div class='add'>+	case ACPI_HMAT_ACCESS_BANDWIDTH:</div><div class='add'>+		coord-&gt;read_bandwidth = val;</div><div class='add'>+		coord-&gt;write_bandwidth = val;</div><div class='add'>+		break;</div><div class='add'>+	case ACPI_HMAT_READ_BANDWIDTH:</div><div class='add'>+		coord-&gt;read_bandwidth = val;</div><div class='add'>+		break;</div><div class='add'>+	case ACPI_HMAT_WRITE_BANDWIDTH:</div><div class='add'>+		coord-&gt;write_bandwidth = val;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cdat_dslbis_handler(union acpi_subtable_headers *header, void *arg,</div><div class='add'>+			       const unsigned long end)</div><div class='add'>+{</div><div class='add'>+	struct acpi_cdat_header *hdr = &amp;header-&gt;cdat;</div><div class='add'>+	struct acpi_cdat_dslbis *dslbis;</div><div class='add'>+	int size = sizeof(*hdr) + sizeof(*dslbis);</div><div class='add'>+	struct xarray *dsmas_xa = arg;</div><div class='add'>+	struct dsmas_entry *dent;</div><div class='add'>+	__le64 le_base;</div><div class='add'>+	__le16 le_val;</div><div class='add'>+	u64 val;</div><div class='add'>+	u16 len;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	len = le16_to_cpu((__force __le16)hdr-&gt;length);</div><div class='add'>+	if (len != size || (unsigned long)hdr + len &gt; end) {</div><div class='add'>+		pr_warn("Malformed DSLBIS table length: (%u:%u)\n", size, len);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Skip common header */</div><div class='add'>+	dslbis = (struct acpi_cdat_dslbis *)(hdr + 1);</div><div class='add'>+</div><div class='add'>+	/* Skip unrecognized data type */</div><div class='add'>+	if (dslbis-&gt;data_type &gt; ACPI_HMAT_WRITE_BANDWIDTH)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Not a memory type, skip */</div><div class='add'>+	if ((dslbis-&gt;flags &amp; ACPI_HMAT_MEMORY_HIERARCHY) != ACPI_HMAT_MEMORY)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	dent = xa_load(dsmas_xa, dslbis-&gt;handle);</div><div class='add'>+	if (!dent) {</div><div class='add'>+		pr_warn("No matching DSMAS entry for DSLBIS entry.\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	le_base = (__force __le64)dslbis-&gt;entry_base_unit;</div><div class='add'>+	le_val = (__force __le16)dslbis-&gt;entry[0];</div><div class='add'>+	rc = check_mul_overflow(le64_to_cpu(le_base),</div><div class='add'>+				le16_to_cpu(le_val), &amp;val);</div><div class='add'>+	if (rc)</div><div class='add'>+		pr_warn("DSLBIS value overflowed.\n");</div><div class='add'>+</div><div class='add'>+	cxl_access_coordinate_set(&amp;dent-&gt;coord, dslbis-&gt;data_type, val);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cdat_table_parse_output(int rc)</div><div class='add'>+{</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return rc;</div><div class='add'>+	if (rc == 0)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cxl_cdat_endpoint_process(struct cxl_port *port,</div><div class='add'>+				     struct xarray *dsmas_xa)</div><div class='add'>+{</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	rc = cdat_table_parse(ACPI_CDAT_TYPE_DSMAS, cdat_dsmas_handler,</div><div class='add'>+			      dsmas_xa, port-&gt;cdat.table);</div><div class='add'>+	rc = cdat_table_parse_output(rc);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rc = cdat_table_parse(ACPI_CDAT_TYPE_DSLBIS, cdat_dslbis_handler,</div><div class='add'>+			      dsmas_xa, port-&gt;cdat.table);</div><div class='add'>+	return cdat_table_parse_output(rc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cxl_port_perf_data_calculate(struct cxl_port *port,</div><div class='add'>+					struct xarray *dsmas_xa)</div><div class='add'>+{</div><div class='add'>+	struct access_coordinate c;</div><div class='add'>+	struct dsmas_entry *dent;</div><div class='add'>+	int valid_entries = 0;</div><div class='add'>+	unsigned long index;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	rc = cxl_endpoint_get_perf_coordinates(port, &amp;c);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_dbg(&amp;port-&gt;dev, "Failed to retrieve perf coordinates.\n");</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);</div><div class='add'>+</div><div class='add'>+	if (!cxl_root)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (!cxl_root-&gt;ops || !cxl_root-&gt;ops-&gt;qos_class)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	xa_for_each(dsmas_xa, index, dent) {</div><div class='add'>+		int qos_class;</div><div class='add'>+</div><div class='add'>+		dent-&gt;coord.read_latency = dent-&gt;coord.read_latency +</div><div class='add'>+					   c.read_latency;</div><div class='add'>+		dent-&gt;coord.write_latency = dent-&gt;coord.write_latency +</div><div class='add'>+					    c.write_latency;</div><div class='add'>+		dent-&gt;coord.read_bandwidth = min_t(int, c.read_bandwidth,</div><div class='add'>+						   dent-&gt;coord.read_bandwidth);</div><div class='add'>+		dent-&gt;coord.write_bandwidth = min_t(int, c.write_bandwidth,</div><div class='add'>+						    dent-&gt;coord.write_bandwidth);</div><div class='add'>+</div><div class='add'>+		dent-&gt;entries = 1;</div><div class='add'>+		rc = cxl_root-&gt;ops-&gt;qos_class(cxl_root, &amp;dent-&gt;coord, 1,</div><div class='add'>+					      &amp;qos_class);</div><div class='add'>+		if (rc != 1)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		valid_entries++;</div><div class='add'>+		dent-&gt;qos_class = qos_class;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!valid_entries)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void add_perf_entry(struct device *dev, struct dsmas_entry *dent,</div><div class='add'>+			   struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf;</div><div class='add'>+</div><div class='add'>+	dpa_perf = kzalloc(sizeof(*dpa_perf), GFP_KERNEL);</div><div class='add'>+	if (!dpa_perf)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dpa_perf-&gt;dpa_range = dent-&gt;dpa_range;</div><div class='add'>+	dpa_perf-&gt;coord = dent-&gt;coord;</div><div class='add'>+	dpa_perf-&gt;qos_class = dent-&gt;qos_class;</div><div class='add'>+	list_add_tail(&amp;dpa_perf-&gt;list, list);</div><div class='add'>+	dev_dbg(dev,</div><div class='add'>+		"DSMAS: dpa: %#llx qos: %d read_bw: %d write_bw %d read_lat: %d write_lat: %d\n",</div><div class='add'>+		dent-&gt;dpa_range.start, dpa_perf-&gt;qos_class,</div><div class='add'>+		dent-&gt;coord.read_bandwidth, dent-&gt;coord.write_bandwidth,</div><div class='add'>+		dent-&gt;coord.read_latency, dent-&gt;coord.write_latency);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_perf_ents(void *data)</div><div class='add'>+{</div><div class='add'>+	struct cxl_memdev_state *mds = data;</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf, *n;</div><div class='add'>+	LIST_HEAD(discard);</div><div class='add'>+</div><div class='add'>+	list_splice_tail_init(&amp;mds-&gt;ram_perf_list, &amp;discard);</div><div class='add'>+	list_splice_tail_init(&amp;mds-&gt;pmem_perf_list, &amp;discard);</div><div class='add'>+	list_for_each_entry_safe(dpa_perf, n, &amp;discard, list) {</div><div class='add'>+		list_del(&amp;dpa_perf-&gt;list);</div><div class='add'>+		kfree(dpa_perf);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,</div><div class='add'>+				     struct xarray *dsmas_xa)</div><div class='add'>+{</div><div class='add'>+	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);</div><div class='add'>+	struct device *dev = cxlds-&gt;dev;</div><div class='add'>+	struct range pmem_range = {</div><div class='add'>+		.start = cxlds-&gt;pmem_res.start,</div><div class='add'>+		.end = cxlds-&gt;pmem_res.end,</div><div class='add'>+	};</div><div class='add'>+	struct range ram_range = {</div><div class='add'>+		.start = cxlds-&gt;ram_res.start,</div><div class='add'>+		.end = cxlds-&gt;ram_res.end,</div><div class='add'>+	};</div><div class='add'>+	struct dsmas_entry *dent;</div><div class='add'>+	unsigned long index;</div><div class='add'>+</div><div class='add'>+	xa_for_each(dsmas_xa, index, dent) {</div><div class='add'>+		if (resource_size(&amp;cxlds-&gt;ram_res) &amp;&amp;</div><div class='add'>+		    range_contains(&amp;ram_range, &amp;dent-&gt;dpa_range))</div><div class='add'>+			add_perf_entry(dev, dent, &amp;mds-&gt;ram_perf_list);</div><div class='add'>+		else if (resource_size(&amp;cxlds-&gt;pmem_res) &amp;&amp;</div><div class='add'>+			 range_contains(&amp;pmem_range, &amp;dent-&gt;dpa_range))</div><div class='add'>+			add_perf_entry(dev, dent, &amp;mds-&gt;pmem_perf_list);</div><div class='add'>+		else</div><div class='add'>+			dev_dbg(dev, "no partition for dsmas dpa: %#llx\n",</div><div class='add'>+				dent-&gt;dpa_range.start);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	devm_add_action_or_reset(&amp;cxlds-&gt;cxlmd-&gt;dev, free_perf_ents, mds);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int match_cxlrd_qos_class(struct device *dev, void *data)</div><div class='add'>+{</div><div class='add'>+	int dev_qos_class = *(int *)data;</div><div class='add'>+	struct cxl_root_decoder *cxlrd;</div><div class='add'>+</div><div class='add'>+	if (!is_root_decoder(dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	cxlrd = to_cxl_root_decoder(dev);</div><div class='add'>+	if (cxlrd-&gt;qos_class == CXL_QOS_CLASS_INVALID)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (cxlrd-&gt;qos_class == dev_qos_class)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void cxl_qos_match(struct cxl_port *root_port,</div><div class='add'>+			  struct list_head *work_list,</div><div class='add'>+			  struct list_head *discard_list)</div><div class='add'>+{</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf, *n;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(dpa_perf, n, work_list, list) {</div><div class='add'>+		int rc;</div><div class='add'>+</div><div class='add'>+		if (dpa_perf-&gt;qos_class == CXL_QOS_CLASS_INVALID)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		rc = device_for_each_child(&amp;root_port-&gt;dev,</div><div class='add'>+					   (void *)&amp;dpa_perf-&gt;qos_class,</div><div class='add'>+					   match_cxlrd_qos_class);</div><div class='add'>+		if (!rc)</div><div class='add'>+			list_move_tail(&amp;dpa_perf-&gt;list, discard_list);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int match_cxlrd_hb(struct device *dev, void *data)</div><div class='add'>+{</div><div class='add'>+	struct device *host_bridge = data;</div><div class='add'>+	struct cxl_switch_decoder *cxlsd;</div><div class='add'>+	struct cxl_root_decoder *cxlrd;</div><div class='add'>+</div><div class='add'>+	if (!is_root_decoder(dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	cxlrd = to_cxl_root_decoder(dev);</div><div class='add'>+	cxlsd = &amp;cxlrd-&gt;cxlsd;</div><div class='add'>+</div><div class='add'>+	guard(rwsem_read)(&amp;cxl_region_rwsem);</div><div class='add'>+	for (int i = 0; i &lt; cxlsd-&gt;nr_targets; i++) {</div><div class='add'>+		if (host_bridge == cxlsd-&gt;target[i]-&gt;dport_dev)</div><div class='add'>+			return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void discard_dpa_perf(struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf, *n;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(dpa_perf, n, list, list) {</div><div class='add'>+		list_del(&amp;dpa_perf-&gt;list);</div><div class='add'>+		kfree(dpa_perf);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+DEFINE_FREE(dpa_perf, struct list_head *, if (!list_empty(_T)) discard_dpa_perf(_T))</div><div class='add'>+</div><div class='add'>+static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)</div><div class='add'>+{</div><div class='add'>+	struct cxl_dev_state *cxlds = cxlmd-&gt;cxlds;</div><div class='add'>+	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);</div><div class='add'>+	LIST_HEAD(__discard);</div><div class='add'>+	struct list_head *discard __free(dpa_perf) = &amp;__discard;</div><div class='add'>+	struct cxl_port *root_port;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	struct cxl_root *cxl_root __free(put_cxl_root) =</div><div class='add'>+		find_cxl_root(cxlmd-&gt;endpoint);</div><div class='add'>+</div><div class='add'>+	if (!cxl_root)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	root_port = &amp;cxl_root-&gt;port;</div><div class='add'>+</div><div class='add'>+	/* Check that the QTG IDs are all sane between end device and root decoders */</div><div class='add'>+	cxl_qos_match(root_port, &amp;mds-&gt;ram_perf_list, discard);</div><div class='add'>+	cxl_qos_match(root_port, &amp;mds-&gt;pmem_perf_list, discard);</div><div class='add'>+</div><div class='add'>+	/* Check to make sure that the device's host bridge is under a root decoder */</div><div class='add'>+	rc = device_for_each_child(&amp;root_port-&gt;dev,</div><div class='add'>+				   (void *)cxlmd-&gt;endpoint-&gt;host_bridge,</div><div class='add'>+				   match_cxlrd_hb);</div><div class='add'>+	if (!rc) {</div><div class='add'>+		list_splice_tail_init(&amp;mds-&gt;ram_perf_list, discard);</div><div class='add'>+		list_splice_tail_init(&amp;mds-&gt;pmem_perf_list, discard);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void discard_dsmas(struct xarray *xa)</div><div class='add'>+{</div><div class='add'>+	unsigned long index;</div><div class='add'>+	void *ent;</div><div class='add'>+</div><div class='add'>+	xa_for_each(xa, index, ent) {</div><div class='add'>+		xa_erase(xa, index);</div><div class='add'>+		kfree(ent);</div><div class='add'>+	}</div><div class='add'>+	xa_destroy(xa);</div><div class='add'>+}</div><div class='add'>+DEFINE_FREE(dsmas, struct xarray *, if (_T) discard_dsmas(_T))</div><div class='add'>+</div><div class='add'>+void cxl_endpoint_parse_cdat(struct cxl_port *port)</div><div class='add'>+{</div><div class='add'>+	struct cxl_memdev *cxlmd = to_cxl_memdev(port-&gt;uport_dev);</div><div class='add'>+	struct cxl_dev_state *cxlds = cxlmd-&gt;cxlds;</div><div class='add'>+	struct xarray __dsmas_xa;</div><div class='add'>+	struct xarray *dsmas_xa __free(dsmas) = &amp;__dsmas_xa;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	xa_init(&amp;__dsmas_xa);</div><div class='add'>+	if (!port-&gt;cdat.table)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	rc = cxl_cdat_endpoint_process(port, dsmas_xa);</div><div class='add'>+	if (rc &lt; 0) {</div><div class='add'>+		dev_dbg(&amp;port-&gt;dev, "Failed to parse CDAT: %d\n", rc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = cxl_port_perf_data_calculate(port, dsmas_xa);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_dbg(&amp;port-&gt;dev, "Failed to do perf coord calculations.\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cxl_memdev_set_qos_class(cxlds, dsmas_xa);</div><div class='add'>+	cxl_qos_class_verify(cxlmd);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_endpoint_parse_cdat, CXL);</div><div class='add'>+</div><div class='add'>+static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,</div><div class='add'>+			       const unsigned long end)</div><div class='add'>+{</div><div class='add'>+	struct acpi_cdat_sslbis *sslbis;</div><div class='add'>+	int size = sizeof(header-&gt;cdat) + sizeof(*sslbis);</div><div class='add'>+	struct cxl_port *port = arg;</div><div class='add'>+	struct device *dev = &amp;port-&gt;dev;</div><div class='add'>+	struct acpi_cdat_sslbe *entry;</div><div class='add'>+	int remain, entries, i;</div><div class='add'>+	u16 len;</div><div class='add'>+</div><div class='add'>+	len = le16_to_cpu((__force __le16)header-&gt;cdat.length);</div><div class='add'>+	remain = len - size;</div><div class='add'>+	if (!remain || remain % sizeof(*entry) ||</div><div class='add'>+	    (unsigned long)header + len &gt; end) {</div><div class='add'>+		dev_warn(dev, "Malformed SSLBIS table length: (%u)\n", len);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Skip common header */</div><div class='add'>+	sslbis = (struct acpi_cdat_sslbis *)((unsigned long)header +</div><div class='add'>+					     sizeof(header-&gt;cdat));</div><div class='add'>+</div><div class='add'>+	/* Unrecognized data type, we can skip */</div><div class='add'>+	if (sslbis-&gt;data_type &gt; ACPI_HMAT_WRITE_BANDWIDTH)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	entries = remain / sizeof(*entry);</div><div class='add'>+	entry = (struct acpi_cdat_sslbe *)((unsigned long)header + sizeof(*sslbis));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; entries; i++) {</div><div class='add'>+		u16 x = le16_to_cpu((__force __le16)entry-&gt;portx_id);</div><div class='add'>+		u16 y = le16_to_cpu((__force __le16)entry-&gt;porty_id);</div><div class='add'>+		__le64 le_base;</div><div class='add'>+		__le16 le_val;</div><div class='add'>+		struct cxl_dport *dport;</div><div class='add'>+		unsigned long index;</div><div class='add'>+		u16 dsp_id;</div><div class='add'>+		u64 val;</div><div class='add'>+</div><div class='add'>+		switch (x) {</div><div class='add'>+		case ACPI_CDAT_SSLBIS_US_PORT:</div><div class='add'>+			dsp_id = y;</div><div class='add'>+			break;</div><div class='add'>+		case ACPI_CDAT_SSLBIS_ANY_PORT:</div><div class='add'>+			switch (y) {</div><div class='add'>+			case ACPI_CDAT_SSLBIS_US_PORT:</div><div class='add'>+				dsp_id = x;</div><div class='add'>+				break;</div><div class='add'>+			case ACPI_CDAT_SSLBIS_ANY_PORT:</div><div class='add'>+				dsp_id = ACPI_CDAT_SSLBIS_ANY_PORT;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				dsp_id = y;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			dsp_id = x;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		le_base = (__force __le64)sslbis-&gt;entry_base_unit;</div><div class='add'>+		le_val = (__force __le16)entry-&gt;latency_or_bandwidth;</div><div class='add'>+</div><div class='add'>+		if (check_mul_overflow(le64_to_cpu(le_base),</div><div class='add'>+				       le16_to_cpu(le_val), &amp;val))</div><div class='add'>+			dev_warn(dev, "SSLBIS value overflowed!\n");</div><div class='add'>+</div><div class='add'>+		xa_for_each(&amp;port-&gt;dports, index, dport) {</div><div class='add'>+			if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT ||</div><div class='add'>+			    dsp_id == dport-&gt;port_id)</div><div class='add'>+				cxl_access_coordinate_set(&amp;dport-&gt;sw_coord,</div><div class='add'>+							  sslbis-&gt;data_type,</div><div class='add'>+							  val);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		entry++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void cxl_switch_parse_cdat(struct cxl_port *port)</div><div class='add'>+{</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (!port-&gt;cdat.table)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	rc = cdat_table_parse(ACPI_CDAT_TYPE_SSLBIS, cdat_sslbis_handler,</div><div class='add'>+			      port, port-&gt;cdat.table);</div><div class='add'>+	rc = cdat_table_parse_output(rc);</div><div class='add'>+	if (rc)</div><div class='add'>+		dev_dbg(&amp;port-&gt;dev, "Failed to parse SSLBIS: %d\n", rc);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL);</div><div class='add'>+</div><div class='add'>+MODULE_IMPORT_NS(CXL);</div><div class='head'>diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h<br/>index 86d7ba23235e..3b64fb1b9ed0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/core.h</a></div><div class='hunk'>@@ -88,4 +88,6 @@ enum cxl_poison_trace_type {</div><div class='ctx'> 	CXL_POISON_TRACE_CLEAR,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+long cxl_pci_get_latency(struct pci_dev *pdev);</div><div class='add'>+</div><div class='ctx'> #endif /* __CXL_CORE_H__ */</div><div class='head'>diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c<br/>index 1cc9be85ba4c..7d97790b893d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/hdm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/hdm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/hdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/hdm.c</a></div><div class='hunk'>@@ -363,10 +363,9 @@ resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled)</div><div class='ctx'> {</div><div class='ctx'> 	resource_size_t base = -1;</div><div class='ctx'> </div><div class='del'>-	down_read(&amp;cxl_dpa_rwsem);</div><div class='add'>+	lockdep_assert_held(&amp;cxl_dpa_rwsem);</div><div class='ctx'> 	if (cxled-&gt;dpa_res)</div><div class='ctx'> 		base = cxled-&gt;dpa_res-&gt;start;</div><div class='del'>-	up_read(&amp;cxl_dpa_rwsem);</div><div class='ctx'> </div><div class='ctx'> 	return base;</div><div class='ctx'> }</div><div class='hunk'>@@ -839,6 +838,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,</div><div class='ctx'> 			cxld-&gt;target_type = CXL_DECODER_HOSTONLYMEM;</div><div class='ctx'> 		else</div><div class='ctx'> 			cxld-&gt;target_type = CXL_DECODER_DEVMEM;</div><div class='add'>+</div><div class='add'>+		guard(rwsem_write)(&amp;cxl_region_rwsem);</div><div class='ctx'> 		if (cxld-&gt;id != cxl_num_decoders_committed(port)) {</div><div class='ctx'> 			dev_warn(&amp;port-&gt;dev,</div><div class='ctx'> 				 "decoder%d.%d: Committed out of order\n",</div><div class='head'>diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c<br/>index 36270dcfb42e..27166a411705 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/mbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/mbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/mbox.c</a></div><div class='hunk'>@@ -63,6 +63,7 @@ static struct cxl_mem_command cxl_mem_commands[CXL_MEM_COMMAND_ID_MAX] = {</div><div class='ctx'> 	CXL_CMD(GET_SHUTDOWN_STATE, 0, 0x1, 0),</div><div class='ctx'> 	CXL_CMD(SET_SHUTDOWN_STATE, 0x1, 0, 0),</div><div class='ctx'> 	CXL_CMD(GET_SCAN_MEDIA_CAPS, 0x10, 0x4, 0),</div><div class='add'>+	CXL_CMD(GET_TIMESTAMP, 0, 0x8, 0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -836,54 +837,37 @@ out:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL);</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * General Media Event Record</div><div class='del'>- * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43</div><div class='del'>- */</div><div class='del'>-static const uuid_t gen_media_event_uuid =</div><div class='del'>-	UUID_INIT(0xfbcd0a77, 0xc260, 0x417f,</div><div class='del'>-		  0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6);</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * DRAM Event Record</div><div class='del'>- * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44</div><div class='del'>- */</div><div class='del'>-static const uuid_t dram_event_uuid =</div><div class='del'>-	UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab,</div><div class='del'>-		  0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24);</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Memory Module Event Record</div><div class='del'>- * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45</div><div class='del'>- */</div><div class='del'>-static const uuid_t mem_mod_event_uuid =</div><div class='del'>-	UUID_INIT(0xfe927475, 0xdd59, 0x4339,</div><div class='del'>-		  0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74);</div><div class='del'>-</div><div class='del'>-static void cxl_event_trace_record(const struct cxl_memdev *cxlmd,</div><div class='del'>-				   enum cxl_event_log_type type,</div><div class='del'>-				   struct cxl_event_record_raw *record)</div><div class='add'>+void cxl_event_trace_record(const struct cxl_memdev *cxlmd,</div><div class='add'>+			    enum cxl_event_log_type type,</div><div class='add'>+			    enum cxl_event_type event_type,</div><div class='add'>+			    const uuid_t *uuid, union cxl_event *evt)</div><div class='ctx'> {</div><div class='del'>-	uuid_t *id = &amp;record-&gt;hdr.id;</div><div class='del'>-</div><div class='del'>-	if (uuid_equal(id, &amp;gen_media_event_uuid)) {</div><div class='del'>-		struct cxl_event_gen_media *rec =</div><div class='del'>-				(struct cxl_event_gen_media *)record;</div><div class='add'>+	if (event_type == CXL_CPER_EVENT_GEN_MEDIA)</div><div class='add'>+		trace_cxl_general_media(cxlmd, type, &amp;evt-&gt;gen_media);</div><div class='add'>+	else if (event_type == CXL_CPER_EVENT_DRAM)</div><div class='add'>+		trace_cxl_dram(cxlmd, type, &amp;evt-&gt;dram);</div><div class='add'>+	else if (event_type == CXL_CPER_EVENT_MEM_MODULE)</div><div class='add'>+		trace_cxl_memory_module(cxlmd, type, &amp;evt-&gt;mem_module);</div><div class='add'>+	else</div><div class='add'>+		trace_cxl_generic_event(cxlmd, type, uuid, &amp;evt-&gt;generic);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_event_trace_record, CXL);</div><div class='ctx'> </div><div class='del'>-		trace_cxl_general_media(cxlmd, type, rec);</div><div class='del'>-	} else if (uuid_equal(id, &amp;dram_event_uuid)) {</div><div class='del'>-		struct cxl_event_dram *rec = (struct cxl_event_dram *)record;</div><div class='add'>+static void __cxl_event_trace_record(const struct cxl_memdev *cxlmd,</div><div class='add'>+				     enum cxl_event_log_type type,</div><div class='add'>+				     struct cxl_event_record_raw *record)</div><div class='add'>+{</div><div class='add'>+	enum cxl_event_type ev_type = CXL_CPER_EVENT_GENERIC;</div><div class='add'>+	const uuid_t *uuid = &amp;record-&gt;id;</div><div class='ctx'> </div><div class='del'>-		trace_cxl_dram(cxlmd, type, rec);</div><div class='del'>-	} else if (uuid_equal(id, &amp;mem_mod_event_uuid)) {</div><div class='del'>-		struct cxl_event_mem_module *rec =</div><div class='del'>-				(struct cxl_event_mem_module *)record;</div><div class='add'>+	if (uuid_equal(uuid, &amp;CXL_EVENT_GEN_MEDIA_UUID))</div><div class='add'>+		ev_type = CXL_CPER_EVENT_GEN_MEDIA;</div><div class='add'>+	else if (uuid_equal(uuid, &amp;CXL_EVENT_DRAM_UUID))</div><div class='add'>+		ev_type = CXL_CPER_EVENT_DRAM;</div><div class='add'>+	else if (uuid_equal(uuid, &amp;CXL_EVENT_MEM_MODULE_UUID))</div><div class='add'>+		ev_type = CXL_CPER_EVENT_MEM_MODULE;</div><div class='ctx'> </div><div class='del'>-		trace_cxl_memory_module(cxlmd, type, rec);</div><div class='del'>-	} else {</div><div class='del'>-		/* For unknown record types print just the header */</div><div class='del'>-		trace_cxl_generic_event(cxlmd, type, record);</div><div class='del'>-	}</div><div class='add'>+	cxl_event_trace_record(cxlmd, type, ev_type, uuid, &amp;record-&gt;event);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cxl_clear_event_record(struct cxl_memdev_state *mds,</div><div class='hunk'>@@ -926,7 +910,10 @@ static int cxl_clear_event_record(struct cxl_memdev_state *mds,</div><div class='ctx'> 	 */</div><div class='ctx'> 	i = 0;</div><div class='ctx'> 	for (cnt = 0; cnt &lt; total; cnt++) {</div><div class='del'>-		payload-&gt;handles[i++] = get_pl-&gt;records[cnt].hdr.handle;</div><div class='add'>+		struct cxl_event_record_raw *raw = &amp;get_pl-&gt;records[cnt];</div><div class='add'>+		struct cxl_event_generic *gen = &amp;raw-&gt;event.generic;</div><div class='add'>+</div><div class='add'>+		payload-&gt;handles[i++] = gen-&gt;hdr.handle;</div><div class='ctx'> 		dev_dbg(mds-&gt;cxlds.dev, "Event log '%d': Clearing %u\n", log,</div><div class='ctx'> 			le16_to_cpu(payload-&gt;handles[i]));</div><div class='ctx'> </div><div class='hunk'>@@ -991,8 +978,8 @@ static void cxl_mem_get_records_log(struct cxl_memdev_state *mds,</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; nr_rec; i++)</div><div class='del'>-			cxl_event_trace_record(cxlmd, type,</div><div class='del'>-					       &amp;payload-&gt;records[i]);</div><div class='add'>+			__cxl_event_trace_record(cxlmd, type,</div><div class='add'>+						 &amp;payload-&gt;records[i]);</div><div class='ctx'> </div><div class='ctx'> 		if (payload-&gt;flags &amp; CXL_GET_EVENT_FLAG_OVERFLOW)</div><div class='ctx'> 			trace_cxl_overflow(cxlmd, type, payload);</div><div class='hunk'>@@ -1404,6 +1391,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)</div><div class='ctx'> 	mds-&gt;cxlds.reg_map.host = dev;</div><div class='ctx'> 	mds-&gt;cxlds.reg_map.resource = CXL_RESOURCE_NONE;</div><div class='ctx'> 	mds-&gt;cxlds.type = CXL_DEVTYPE_CLASSMEM;</div><div class='add'>+	INIT_LIST_HEAD(&amp;mds-&gt;ram_perf_list);</div><div class='add'>+	INIT_LIST_HEAD(&amp;mds-&gt;pmem_perf_list);</div><div class='ctx'> </div><div class='ctx'> 	return mds;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c<br/>index fc5c2b414793..dae8802ecdb0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/memdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/memdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/memdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/memdev.c</a></div><div class='hunk'>@@ -114,7 +114,7 @@ static DEVICE_ATTR_RO(serial);</div><div class='ctx'> static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 			      char *buf)</div><div class='ctx'> {</div><div class='del'>-	return sprintf(buf, "%d\n", dev_to_node(dev));</div><div class='add'>+	return sysfs_emit(buf, "%d\n", dev_to_node(dev));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(numa_node);</div><div class='ctx'> </div><div class='hunk'>@@ -227,10 +227,16 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd)</div><div class='ctx'> 	if (!port || !is_cxl_endpoint(port))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_region_rwsem);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	if (rc) {</div><div class='add'>+		up_read(&amp;cxl_region_rwsem);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (cxl_num_decoders_committed(port) == 0) {</div><div class='ctx'> 		/* No regions mapped to this memdev */</div><div class='ctx'> 		rc = cxl_get_poison_by_memdev(cxlmd);</div><div class='hunk'>@@ -239,6 +245,7 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd)</div><div class='ctx'> 		rc =  cxl_get_poison_by_endpoint(port);</div><div class='ctx'> 	}</div><div class='ctx'> 	up_read(&amp;cxl_dpa_rwsem);</div><div class='add'>+	up_read(&amp;cxl_region_rwsem);</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='hunk'>@@ -324,10 +331,16 @@ int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa)</div><div class='ctx'> 	if (!IS_ENABLED(CONFIG_DEBUG_FS))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_region_rwsem);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	if (rc) {</div><div class='add'>+		up_read(&amp;cxl_region_rwsem);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rc = cxl_validate_poison_dpa(cxlmd, dpa);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -355,6 +368,7 @@ int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa)</div><div class='ctx'> 	trace_cxl_poison(cxlmd, cxlr, &amp;record, 0, 0, CXL_POISON_TRACE_INJECT);</div><div class='ctx'> out:</div><div class='ctx'> 	up_read(&amp;cxl_dpa_rwsem);</div><div class='add'>+	up_read(&amp;cxl_region_rwsem);</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='hunk'>@@ -372,10 +386,16 @@ int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa)</div><div class='ctx'> 	if (!IS_ENABLED(CONFIG_DEBUG_FS))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_region_rwsem);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='add'>+	rc = down_read_interruptible(&amp;cxl_dpa_rwsem);</div><div class='add'>+	if (rc) {</div><div class='add'>+		up_read(&amp;cxl_region_rwsem);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rc = cxl_validate_poison_dpa(cxlmd, dpa);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -412,6 +432,7 @@ int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa)</div><div class='ctx'> 	trace_cxl_poison(cxlmd, cxlr, &amp;record, 0, 0, CXL_POISON_TRACE_CLEAR);</div><div class='ctx'> out:</div><div class='ctx'> 	up_read(&amp;cxl_dpa_rwsem);</div><div class='add'>+	up_read(&amp;cxl_region_rwsem);</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c<br/>index eff20e83d0a6..6c9c8d92f8f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pci.c</a></div><div class='hunk'>@@ -1,5 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /* Copyright(c) 2021 Intel Corporation. All rights reserved. */</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='ctx'> #include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='hunk'>@@ -620,7 +621,7 @@ void read_cdat_data(struct cxl_port *port)</div><div class='ctx'> 	struct pci_dev *pdev = NULL;</div><div class='ctx'> 	struct cxl_memdev *cxlmd;</div><div class='ctx'> 	size_t cdat_length;</div><div class='del'>-	void *cdat_table;</div><div class='add'>+	void *cdat_table, *cdat_buf;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (is_cxl_memdev(uport)) {</div><div class='hunk'>@@ -651,16 +652,15 @@ void read_cdat_data(struct cxl_port *port)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	cdat_table = devm_kzalloc(dev, cdat_length + sizeof(__le32),</div><div class='del'>-				  GFP_KERNEL);</div><div class='del'>-	if (!cdat_table)</div><div class='add'>+	cdat_buf = devm_kzalloc(dev, cdat_length + sizeof(__le32), GFP_KERNEL);</div><div class='add'>+	if (!cdat_buf)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	rc = cxl_cdat_read_table(dev, cdat_doe, cdat_table, &amp;cdat_length);</div><div class='add'>+	rc = cxl_cdat_read_table(dev, cdat_doe, cdat_buf, &amp;cdat_length);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='del'>-	cdat_table = cdat_table + sizeof(__le32);</div><div class='add'>+	cdat_table = cdat_buf + sizeof(__le32);</div><div class='ctx'> 	if (cdat_checksum(cdat_table, cdat_length))</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -670,7 +670,7 @@ void read_cdat_data(struct cxl_port *port)</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='ctx'> 	/* Don't leave table data allocated on error */</div><div class='del'>-	devm_kfree(dev, cdat_table);</div><div class='add'>+	devm_kfree(dev, cdat_buf);</div><div class='ctx'> 	dev_err(dev, "Failed to read/validate CDAT.\n");</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);</div><div class='hunk'>@@ -980,3 +980,38 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,</div><div class='ctx'> 	return PCI_ERS_RESULT_NEED_RESET;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(cxl_error_detected, CXL);</div><div class='add'>+</div><div class='add'>+static int cxl_flit_size(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (cxl_pci_flit_256(pdev))</div><div class='add'>+		return 256;</div><div class='add'>+</div><div class='add'>+	return 68;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * cxl_pci_get_latency - calculate the link latency for the PCIe link</div><div class='add'>+ * @pdev: PCI device</div><div class='add'>+ *</div><div class='add'>+ * return: calculated latency or 0 for no latency</div><div class='add'>+ *</div><div class='add'>+ * CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation</div><div class='add'>+ * Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency</div><div class='add'>+ * LinkProgationLatency is negligible, so 0 will be used</div><div class='add'>+ * RetimerLatency is assumed to be negligible and 0 will be used</div><div class='add'>+ * FlitLatency = FlitSize / LinkBandwidth</div><div class='add'>+ * FlitSize is defined by spec. CXL rev3.0 4.2.1.</div><div class='add'>+ * 68B flit is used up to 32GT/s. &gt;32GT/s, 256B flit size is used.</div><div class='add'>+ * The FlitLatency is converted to picoseconds.</div><div class='add'>+ */</div><div class='add'>+long cxl_pci_get_latency(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	long bw;</div><div class='add'>+</div><div class='add'>+	bw = pcie_link_speed_mbps(pdev);</div><div class='add'>+	if (bw &lt; 0)</div><div class='add'>+		return 0;</div><div class='add'>+	bw /= BITS_PER_BYTE;</div><div class='add'>+</div><div class='add'>+	return cxl_flit_size(pdev) * MEGA / bw;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c<br/>index fc94f5240327..e69625a8d6a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/pmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/pmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/pmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pmem.c</a></div><div class='hunk'>@@ -64,14 +64,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data)</div><div class='ctx'> </div><div class='ctx'> struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)</div><div class='ctx'> {</div><div class='del'>-	struct cxl_port *port = find_cxl_root(cxlmd-&gt;endpoint);</div><div class='add'>+	struct cxl_root *cxl_root __free(put_cxl_root) =</div><div class='add'>+		find_cxl_root(cxlmd-&gt;endpoint);</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> </div><div class='del'>-	if (!port)</div><div class='add'>+	if (!cxl_root)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	dev = device_find_child(&amp;port-&gt;dev, NULL, match_nvdimm_bridge);</div><div class='del'>-	put_device(&amp;port-&gt;dev);</div><div class='add'>+	dev = device_find_child(&amp;cxl_root-&gt;port.dev, NULL, match_nvdimm_bridge);</div><div class='ctx'> </div><div class='ctx'> 	if (!dev)</div><div class='ctx'> 		return NULL;</div><div class='head'>diff --git a/drivers/cxl/core/pmu.c b/drivers/cxl/core/pmu.c<br/>index 7684c843e5a5..5d8e06b0ba6e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/pmu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/pmu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/pmu.c</a></div><div class='hunk'>@@ -23,7 +23,7 @@ const struct device_type cxl_pmu_type = {</div><div class='ctx'> </div><div class='ctx'> static void remove_dev(void *dev)</div><div class='ctx'> {</div><div class='del'>-	device_del(dev);</div><div class='add'>+	device_unregister(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs,</div><div class='head'>diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c<br/>index 38441634e4c6..e59d9d37aa65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/port.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/port.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/port.c</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/idr.h&gt;</div><div class='add'>+#include &lt;linux/node.h&gt;</div><div class='ctx'> #include &lt;cxlmem.h&gt;</div><div class='ctx'> #include &lt;cxlpci.h&gt;</div><div class='ctx'> #include &lt;cxl.h&gt;</div><div class='hunk'>@@ -172,14 +173,10 @@ static ssize_t target_list_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(dev);</div><div class='ctx'> 	ssize_t offset;</div><div class='del'>-	unsigned int seq;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	do {</div><div class='del'>-		seq = read_seqbegin(&amp;cxlsd-&gt;target_lock);</div><div class='del'>-		rc = emit_target_list(cxlsd, buf);</div><div class='del'>-	} while (read_seqretry(&amp;cxlsd-&gt;target_lock, seq));</div><div class='del'>-</div><div class='add'>+	guard(rwsem_read)(&amp;cxl_region_rwsem);</div><div class='add'>+	rc = emit_target_list(cxlsd, buf);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	offset = rc;</div><div class='hunk'>@@ -226,9 +223,9 @@ static ssize_t dpa_resource_show(struct device *dev, struct device_attribute *at</div><div class='ctx'> 			    char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct cxl_endpoint_decoder *cxled = to_cxl_endpoint_decoder(dev);</div><div class='del'>-	u64 base = cxl_dpa_resource_start(cxled);</div><div class='ctx'> </div><div class='del'>-	return sysfs_emit(buf, "%#llx\n", base);</div><div class='add'>+	guard(rwsem_read)(&amp;cxl_dpa_rwsem);</div><div class='add'>+	return sysfs_emit(buf, "%#llx\n", (u64)cxl_dpa_resource_start(cxled));</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(dpa_resource);</div><div class='ctx'> </div><div class='hunk'>@@ -541,7 +538,10 @@ static void cxl_port_release(struct device *dev)</div><div class='ctx'> 	xa_destroy(&amp;port-&gt;dports);</div><div class='ctx'> 	xa_destroy(&amp;port-&gt;regions);</div><div class='ctx'> 	ida_free(&amp;cxl_port_ida, port-&gt;id);</div><div class='del'>-	kfree(port);</div><div class='add'>+	if (is_cxl_root(port))</div><div class='add'>+		kfree(to_cxl_root(port));</div><div class='add'>+	else</div><div class='add'>+		kfree(port);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t decoders_committed_show(struct device *dev,</div><div class='hunk'>@@ -669,17 +669,31 @@ static struct lock_class_key cxl_port_key;</div><div class='ctx'> static struct cxl_port *cxl_port_alloc(struct device *uport_dev,</div><div class='ctx'> 				       struct cxl_dport *parent_dport)</div><div class='ctx'> {</div><div class='del'>-	struct cxl_port *port;</div><div class='add'>+	struct cxl_root *cxl_root __free(kfree) = NULL;</div><div class='add'>+	struct cxl_port *port, *_port __free(kfree) = NULL;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	port = kzalloc(sizeof(*port), GFP_KERNEL);</div><div class='del'>-	if (!port)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	/* No parent_dport, root cxl_port */</div><div class='add'>+	if (!parent_dport) {</div><div class='add'>+		cxl_root = kzalloc(sizeof(*cxl_root), GFP_KERNEL);</div><div class='add'>+		if (!cxl_root)</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+	} else {</div><div class='add'>+		_port = kzalloc(sizeof(*port), GFP_KERNEL);</div><div class='add'>+		if (!_port)</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	rc = ida_alloc(&amp;cxl_port_ida, GFP_KERNEL);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='del'>-		goto err;</div><div class='add'>+		return ERR_PTR(rc);</div><div class='add'>+</div><div class='add'>+	if (cxl_root)</div><div class='add'>+		port = &amp;no_free_ptr(cxl_root)-&gt;port;</div><div class='add'>+	else</div><div class='add'>+		port = no_free_ptr(_port);</div><div class='add'>+</div><div class='ctx'> 	port-&gt;id = rc;</div><div class='ctx'> 	port-&gt;uport_dev = uport_dev;</div><div class='ctx'> </div><div class='hunk'>@@ -731,10 +745,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,</div><div class='ctx'> 	dev-&gt;type = &amp;cxl_port_type;</div><div class='ctx'> </div><div class='ctx'> 	return port;</div><div class='del'>-</div><div class='del'>-err:</div><div class='del'>-	kfree(port);</div><div class='del'>-	return ERR_PTR(rc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,</div><div class='hunk'>@@ -841,6 +851,9 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return ERR_PTR(rc);</div><div class='ctx'> </div><div class='add'>+	if (parent_dport &amp;&amp; dev_is_pci(uport_dev))</div><div class='add'>+		port-&gt;pci_latency = cxl_pci_get_latency(to_pci_dev(uport_dev));</div><div class='add'>+</div><div class='ctx'> 	return port;</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='hunk'>@@ -884,6 +897,22 @@ struct cxl_port *devm_cxl_add_port(struct device *host,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);</div><div class='ctx'> </div><div class='add'>+struct cxl_root *devm_cxl_add_root(struct device *host,</div><div class='add'>+				   const struct cxl_root_ops *ops)</div><div class='add'>+{</div><div class='add'>+	struct cxl_root *cxl_root;</div><div class='add'>+	struct cxl_port *port;</div><div class='add'>+</div><div class='add'>+	port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);</div><div class='add'>+	if (IS_ERR(port))</div><div class='add'>+		return (struct cxl_root *)port;</div><div class='add'>+</div><div class='add'>+	cxl_root = to_cxl_root(port);</div><div class='add'>+	cxl_root-&gt;ops = ops;</div><div class='add'>+	return cxl_root;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, CXL);</div><div class='add'>+</div><div class='ctx'> struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port)</div><div class='ctx'> {</div><div class='ctx'> 	/* There is no pci_bus associated with a CXL platform-root port */</div><div class='hunk'>@@ -939,7 +968,7 @@ static bool dev_is_cxl_root_child(struct device *dev)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct cxl_port *find_cxl_root(struct cxl_port *port)</div><div class='add'>+struct cxl_root *find_cxl_root(struct cxl_port *port)</div><div class='ctx'> {</div><div class='ctx'> 	struct cxl_port *iter = port;</div><div class='ctx'> </div><div class='hunk'>@@ -949,10 +978,19 @@ struct cxl_port *find_cxl_root(struct cxl_port *port)</div><div class='ctx'> 	if (!iter)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	get_device(&amp;iter-&gt;dev);</div><div class='del'>-	return iter;</div><div class='add'>+	return to_cxl_root(iter);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);</div><div class='ctx'> </div><div class='add'>+void put_cxl_root(struct cxl_root *cxl_root)</div><div class='add'>+{</div><div class='add'>+	if (!cxl_root)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	put_device(&amp;cxl_root-&gt;port.dev);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(put_cxl_root, CXL);</div><div class='add'>+</div><div class='ctx'> static struct cxl_dport *find_dport(struct cxl_port *port, int id)</div><div class='ctx'> {</div><div class='ctx'> 	struct cxl_dport *dport;</div><div class='hunk'>@@ -1108,6 +1146,9 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return ERR_PTR(rc);</div><div class='ctx'> </div><div class='add'>+	if (dev_is_pci(dport_dev))</div><div class='add'>+		dport-&gt;link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev));</div><div class='add'>+</div><div class='ctx'> 	return dport;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1633,7 +1674,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);</div><div class='ctx'> static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,</div><div class='ctx'> 				    struct cxl_port *port, int *target_map)</div><div class='ctx'> {</div><div class='del'>-	int i, rc = 0;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!target_map)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1643,19 +1684,16 @@ static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,</div><div class='ctx'> 	if (xa_empty(&amp;port-&gt;dports))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	write_seqlock(&amp;cxlsd-&gt;target_lock);</div><div class='del'>-	for (i = 0; i &lt; cxlsd-&gt;nr_targets; i++) {</div><div class='add'>+	guard(rwsem_write)(&amp;cxl_region_rwsem);</div><div class='add'>+	for (i = 0; i &lt; cxlsd-&gt;cxld.interleave_ways; i++) {</div><div class='ctx'> 		struct cxl_dport *dport = find_dport(port, target_map[i]);</div><div class='ctx'> </div><div class='del'>-		if (!dport) {</div><div class='del'>-			rc = -ENXIO;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='add'>+		if (!dport)</div><div class='add'>+			return -ENXIO;</div><div class='ctx'> 		cxlsd-&gt;target[i] = dport;</div><div class='ctx'> 	}</div><div class='del'>-	write_sequnlock(&amp;cxlsd-&gt;target_lock);</div><div class='ctx'> </div><div class='del'>-	return rc;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos)</div><div class='hunk'>@@ -1725,7 +1763,6 @@ static int cxl_switch_decoder_init(struct cxl_port *port,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	cxlsd-&gt;nr_targets = nr_targets;</div><div class='del'>-	seqlock_init(&amp;cxlsd-&gt;target_lock);</div><div class='ctx'> 	return cxl_decoder_init(port, &amp;cxlsd-&gt;cxld);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2059,6 +2096,80 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);</div><div class='ctx'> </div><div class='add'>+static void combine_coordinates(struct access_coordinate *c1,</div><div class='add'>+				struct access_coordinate *c2)</div><div class='add'>+{</div><div class='add'>+		if (c2-&gt;write_bandwidth)</div><div class='add'>+			c1-&gt;write_bandwidth = min(c1-&gt;write_bandwidth,</div><div class='add'>+						  c2-&gt;write_bandwidth);</div><div class='add'>+		c1-&gt;write_latency += c2-&gt;write_latency;</div><div class='add'>+</div><div class='add'>+		if (c2-&gt;read_bandwidth)</div><div class='add'>+			c1-&gt;read_bandwidth = min(c1-&gt;read_bandwidth,</div><div class='add'>+						 c2-&gt;read_bandwidth);</div><div class='add'>+		c1-&gt;read_latency += c2-&gt;read_latency;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports</div><div class='add'>+ *				   of CXL path</div><div class='add'>+ * @port: endpoint cxl_port</div><div class='add'>+ * @coord: output performance data</div><div class='add'>+ *</div><div class='add'>+ * Return: errno on failure, 0 on success.</div><div class='add'>+ */</div><div class='add'>+int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,</div><div class='add'>+				      struct access_coordinate *coord)</div><div class='add'>+{</div><div class='add'>+	struct access_coordinate c = {</div><div class='add'>+		.read_bandwidth = UINT_MAX,</div><div class='add'>+		.write_bandwidth = UINT_MAX,</div><div class='add'>+	};</div><div class='add'>+	struct cxl_port *iter = port;</div><div class='add'>+	struct cxl_dport *dport;</div><div class='add'>+	struct pci_dev *pdev;</div><div class='add'>+	unsigned int bw;</div><div class='add'>+</div><div class='add'>+	if (!is_cxl_endpoint(port))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dport = iter-&gt;parent_dport;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Exit the loop when the parent port of the current port is cxl root.</div><div class='add'>+	 * The iterative loop starts at the endpoint and gathers the</div><div class='add'>+	 * latency of the CXL link from the current iter to the next downstream</div><div class='add'>+	 * port each iteration. If the parent is cxl root then there is</div><div class='add'>+	 * nothing to gather.</div><div class='add'>+	 */</div><div class='add'>+	while (iter &amp;&amp; !is_cxl_root(to_cxl_port(iter-&gt;dev.parent))) {</div><div class='add'>+		combine_coordinates(&amp;c, &amp;dport-&gt;sw_coord);</div><div class='add'>+		c.write_latency += dport-&gt;link_latency;</div><div class='add'>+		c.read_latency += dport-&gt;link_latency;</div><div class='add'>+</div><div class='add'>+		iter = to_cxl_port(iter-&gt;dev.parent);</div><div class='add'>+		dport = iter-&gt;parent_dport;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Augment with the generic port (host bridge) perf data */</div><div class='add'>+	combine_coordinates(&amp;c, &amp;dport-&gt;hb_coord);</div><div class='add'>+</div><div class='add'>+	/* Get the calculated PCI paths bandwidth */</div><div class='add'>+	pdev = to_pci_dev(port-&gt;uport_dev-&gt;parent);</div><div class='add'>+	bw = pcie_bandwidth_available(pdev, NULL, NULL, NULL);</div><div class='add'>+	if (bw == 0)</div><div class='add'>+		return -ENXIO;</div><div class='add'>+	bw /= BITS_PER_BYTE;</div><div class='add'>+</div><div class='add'>+	c.write_bandwidth = min(c.write_bandwidth, bw);</div><div class='add'>+	c.read_bandwidth = min(c.read_bandwidth, bw);</div><div class='add'>+</div><div class='add'>+	*coord = c;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(cxl_endpoint_get_perf_coordinates, CXL);</div><div class='add'>+</div><div class='ctx'> /* for user tooling to ensure port disable work has completed */</div><div class='ctx'> static ssize_t flush_store(const struct bus_type *bus, const char *buf, size_t count)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c<br/>index 56e575c79bb4..0f05692bfec3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/region.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/region.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/region.c</a></div><div class='hunk'>@@ -397,7 +397,7 @@ static ssize_t interleave_ways_store(struct device *dev,</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Even for x3, x9, and x12 interleaves the region interleave must be a</div><div class='add'>+	 * Even for x3, x6, and x12 interleaves the region interleave must be a</div><div class='ctx'> 	 * power of 2 multiple of the host bridge interleave.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!is_power_of_2(val / cxld-&gt;interleave_ways) ||</div><div class='hunk'>@@ -552,8 +552,9 @@ static int alloc_hpa(struct cxl_region *cxlr, resource_size_t size)</div><div class='ctx'> 	res = alloc_free_mem_region(cxlrd-&gt;res, size, SZ_256M,</div><div class='ctx'> 				    dev_name(&amp;cxlr-&gt;dev));</div><div class='ctx'> 	if (IS_ERR(res)) {</div><div class='del'>-		dev_dbg(&amp;cxlr-&gt;dev, "failed to allocate HPA: %ld\n",</div><div class='del'>-			PTR_ERR(res));</div><div class='add'>+		dev_dbg(&amp;cxlr-&gt;dev,</div><div class='add'>+			"HPA allocation error (%ld) for size:%pap in %s %pr\n",</div><div class='add'>+			PTR_ERR(res), &amp;size, cxlrd-&gt;res-&gt;name, cxlrd-&gt;res);</div><div class='ctx'> 		return PTR_ERR(res);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2083,13 +2084,13 @@ static struct cxl_region *to_cxl_region(struct device *dev)</div><div class='ctx'> 	return container_of(dev, struct cxl_region, dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void unregister_region(void *dev)</div><div class='add'>+static void unregister_region(void *_cxlr)</div><div class='ctx'> {</div><div class='del'>-	struct cxl_region *cxlr = to_cxl_region(dev);</div><div class='add'>+	struct cxl_region *cxlr = _cxlr;</div><div class='ctx'> 	struct cxl_region_params *p = &amp;cxlr-&gt;params;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	device_del(dev);</div><div class='add'>+	device_del(&amp;cxlr-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Now that region sysfs is shutdown, the parameter block is now</div><div class='hunk'>@@ -2100,7 +2101,7 @@ static void unregister_region(void *dev)</div><div class='ctx'> 		detach_target(cxlr, i);</div><div class='ctx'> </div><div class='ctx'> 	cxl_region_iomem_release(cxlr);</div><div class='del'>-	put_device(dev);</div><div class='add'>+	put_device(&amp;cxlr-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct lock_class_key cxl_region_key;</div><div class='hunk'>@@ -2467,10 +2468,6 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port)</div><div class='ctx'> 	struct cxl_poison_context ctx;</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> </div><div class='del'>-	rc = down_read_interruptible(&amp;cxl_region_rwsem);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='ctx'> 	ctx = (struct cxl_poison_context) {</div><div class='ctx'> 		.port = port</div><div class='ctx'> 	};</div><div class='hunk'>@@ -2480,7 +2477,6 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port)</div><div class='ctx'> 		rc = cxl_get_poison_unmapped(to_cxl_memdev(port-&gt;uport_dev),</div><div class='ctx'> 					     &amp;ctx);</div><div class='ctx'> </div><div class='del'>-	up_read(&amp;cxl_region_rwsem);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h<br/>index a0b5819bc70b..89445435303a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/core/trace.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/core/trace.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/core/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/core/trace.h</a></div><div class='hunk'>@@ -181,6 +181,7 @@ TRACE_EVENT(cxl_overflow,</div><div class='ctx'>  *	1) Add CXL_EVT_TP_entry to TP_STRUCT__entry</div><div class='ctx'>  *	2) Use CXL_EVT_TP_fast_assign within TP_fast_assign;</div><div class='ctx'>  *	   pass the dev, log, and CXL event header</div><div class='add'>+ *	   NOTE: The uuid must be assigned by the specific trace event</div><div class='ctx'>  *	3) Use CXL_EVT_TP_printk() instead of TP_printk()</div><div class='ctx'>  *</div><div class='ctx'>  * See the generic_event tracepoint as an example.</div><div class='hunk'>@@ -203,7 +204,6 @@ TRACE_EVENT(cxl_overflow,</div><div class='ctx'> 	__assign_str(host, dev_name((cxlmd)-&gt;dev.parent));			\</div><div class='ctx'> 	__entry-&gt;log = (l);							\</div><div class='ctx'> 	__entry-&gt;serial = (cxlmd)-&gt;cxlds-&gt;serial;				\</div><div class='del'>-	memcpy(&amp;__entry-&gt;hdr_uuid, &amp;(hdr).id, sizeof(uuid_t));			\</div><div class='ctx'> 	__entry-&gt;hdr_length = (hdr).length;					\</div><div class='ctx'> 	__entry-&gt;hdr_flags = get_unaligned_le24((hdr).flags);			\</div><div class='ctx'> 	__entry-&gt;hdr_handle = le16_to_cpu((hdr).handle);			\</div><div class='hunk'>@@ -225,9 +225,9 @@ TRACE_EVENT(cxl_overflow,</div><div class='ctx'> TRACE_EVENT(cxl_generic_event,</div><div class='ctx'> </div><div class='ctx'> 	TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,</div><div class='del'>-		 struct cxl_event_record_raw *rec),</div><div class='add'>+		 const uuid_t *uuid, struct cxl_event_generic *gen_rec),</div><div class='ctx'> </div><div class='del'>-	TP_ARGS(cxlmd, log, rec),</div><div class='add'>+	TP_ARGS(cxlmd, log, uuid, gen_rec),</div><div class='ctx'> </div><div class='ctx'> 	TP_STRUCT__entry(</div><div class='ctx'> 		CXL_EVT_TP_entry</div><div class='hunk'>@@ -235,8 +235,9 @@ TRACE_EVENT(cxl_generic_event,</div><div class='ctx'> 	),</div><div class='ctx'> </div><div class='ctx'> 	TP_fast_assign(</div><div class='del'>-		CXL_EVT_TP_fast_assign(cxlmd, log, rec-&gt;hdr);</div><div class='del'>-		memcpy(__entry-&gt;data, &amp;rec-&gt;data, CXL_EVENT_RECORD_DATA_LENGTH);</div><div class='add'>+		CXL_EVT_TP_fast_assign(cxlmd, log, gen_rec-&gt;hdr);</div><div class='add'>+		memcpy(&amp;__entry-&gt;hdr_uuid, uuid, sizeof(uuid_t));</div><div class='add'>+		memcpy(__entry-&gt;data, gen_rec-&gt;data, CXL_EVENT_RECORD_DATA_LENGTH);</div><div class='ctx'> 	),</div><div class='ctx'> </div><div class='ctx'> 	CXL_EVT_TP_printk("%s",</div><div class='hunk'>@@ -337,6 +338,7 @@ TRACE_EVENT(cxl_general_media,</div><div class='ctx'> </div><div class='ctx'> 	TP_fast_assign(</div><div class='ctx'> 		CXL_EVT_TP_fast_assign(cxlmd, log, rec-&gt;hdr);</div><div class='add'>+		memcpy(&amp;__entry-&gt;hdr_uuid, &amp;CXL_EVENT_GEN_MEDIA_UUID, sizeof(uuid_t));</div><div class='ctx'> </div><div class='ctx'> 		/* General Media */</div><div class='ctx'> 		__entry-&gt;dpa = le64_to_cpu(rec-&gt;phys_addr);</div><div class='hunk'>@@ -423,6 +425,7 @@ TRACE_EVENT(cxl_dram,</div><div class='ctx'> </div><div class='ctx'> 	TP_fast_assign(</div><div class='ctx'> 		CXL_EVT_TP_fast_assign(cxlmd, log, rec-&gt;hdr);</div><div class='add'>+		memcpy(&amp;__entry-&gt;hdr_uuid, &amp;CXL_EVENT_DRAM_UUID, sizeof(uuid_t));</div><div class='ctx'> </div><div class='ctx'> 		/* DRAM */</div><div class='ctx'> 		__entry-&gt;dpa = le64_to_cpu(rec-&gt;phys_addr);</div><div class='hunk'>@@ -570,6 +573,7 @@ TRACE_EVENT(cxl_memory_module,</div><div class='ctx'> </div><div class='ctx'> 	TP_fast_assign(</div><div class='ctx'> 		CXL_EVT_TP_fast_assign(cxlmd, log, rec-&gt;hdr);</div><div class='add'>+		memcpy(&amp;__entry-&gt;hdr_uuid, &amp;CXL_EVENT_MEM_MODULE_UUID, sizeof(uuid_t));</div><div class='ctx'> </div><div class='ctx'> 		/* Memory Module Event */</div><div class='ctx'> 		__entry-&gt;event_type = rec-&gt;event_type;</div><div class='head'>diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h<br/>index 687043ece101..b6017c0c57b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/cxl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/cxl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/cxl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxl.h</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/bitops.h&gt;</div><div class='ctx'> #include &lt;linux/log2.h&gt;</div><div class='add'>+#include &lt;linux/node.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -412,7 +413,6 @@ struct cxl_endpoint_decoder {</div><div class='ctx'> /**</div><div class='ctx'>  * struct cxl_switch_decoder - Switch specific CXL HDM Decoder</div><div class='ctx'>  * @cxld: base cxl_decoder object</div><div class='del'>- * @target_lock: coordinate coherent reads of the target list</div><div class='ctx'>  * @nr_targets: number of elements in @target</div><div class='ctx'>  * @target: active ordered target list in current decoder configuration</div><div class='ctx'>  *</div><div class='hunk'>@@ -424,7 +424,6 @@ struct cxl_endpoint_decoder {</div><div class='ctx'>  */</div><div class='ctx'> struct cxl_switch_decoder {</div><div class='ctx'> 	struct cxl_decoder cxld;</div><div class='del'>-	seqlock_t target_lock;</div><div class='ctx'> 	int nr_targets;</div><div class='ctx'> 	struct cxl_dport *target[];</div><div class='ctx'> };</div><div class='hunk'>@@ -590,6 +589,7 @@ struct cxl_dax_region {</div><div class='ctx'>  * @depth: How deep this port is relative to the root. depth 0 is the root.</div><div class='ctx'>  * @cdat: Cached CDAT data</div><div class='ctx'>  * @cdat_available: Should a CDAT attribute be available in sysfs</div><div class='add'>+ * @pci_latency: Upstream latency in picoseconds</div><div class='ctx'>  */</div><div class='ctx'> struct cxl_port {</div><div class='ctx'> 	struct device dev;</div><div class='hunk'>@@ -612,6 +612,30 @@ struct cxl_port {</div><div class='ctx'> 		size_t length;</div><div class='ctx'> 	} cdat;</div><div class='ctx'> 	bool cdat_available;</div><div class='add'>+	long pci_latency;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct cxl_root - logical collection of root cxl_port items</div><div class='add'>+ *</div><div class='add'>+ * @port: cxl_port member</div><div class='add'>+ * @ops: cxl root operations</div><div class='add'>+ */</div><div class='add'>+struct cxl_root {</div><div class='add'>+	struct cxl_port port;</div><div class='add'>+	const struct cxl_root_ops *ops;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct cxl_root *</div><div class='add'>+to_cxl_root(const struct cxl_port *port)</div><div class='add'>+{</div><div class='add'>+	return container_of(port, struct cxl_root, port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct cxl_root_ops {</div><div class='add'>+	int (*qos_class)(struct cxl_root *cxl_root,</div><div class='add'>+			 struct access_coordinate *coord, int entries,</div><div class='add'>+			 int *qos_class);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct cxl_dport *</div><div class='hunk'>@@ -634,6 +658,9 @@ struct cxl_rcrb_info {</div><div class='ctx'>  * @rch: Indicate whether this dport was enumerated in RCH or VH mode</div><div class='ctx'>  * @port: reference to cxl_port that contains this downstream port</div><div class='ctx'>  * @regs: Dport parsed register blocks</div><div class='add'>+ * @sw_coord: access coordinates (performance) for switch from CDAT</div><div class='add'>+ * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge)</div><div class='add'>+ * @link_latency: calculated PCIe downstream latency</div><div class='ctx'>  */</div><div class='ctx'> struct cxl_dport {</div><div class='ctx'> 	struct device *dport_dev;</div><div class='hunk'>@@ -643,6 +670,9 @@ struct cxl_dport {</div><div class='ctx'> 	bool rch;</div><div class='ctx'> 	struct cxl_port *port;</div><div class='ctx'> 	struct cxl_regs regs;</div><div class='add'>+	struct access_coordinate sw_coord;</div><div class='add'>+	struct access_coordinate hb_coord;</div><div class='add'>+	long link_latency;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -700,7 +730,12 @@ struct cxl_port *devm_cxl_add_port(struct device *host,</div><div class='ctx'> 				   struct device *uport_dev,</div><div class='ctx'> 				   resource_size_t component_reg_phys,</div><div class='ctx'> 				   struct cxl_dport *parent_dport);</div><div class='del'>-struct cxl_port *find_cxl_root(struct cxl_port *port);</div><div class='add'>+struct cxl_root *devm_cxl_add_root(struct device *host,</div><div class='add'>+				   const struct cxl_root_ops *ops);</div><div class='add'>+struct cxl_root *find_cxl_root(struct cxl_port *port);</div><div class='add'>+void put_cxl_root(struct cxl_root *cxl_root);</div><div class='add'>+DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))</div><div class='add'>+</div><div class='ctx'> int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);</div><div class='ctx'> void cxl_bus_rescan(void);</div><div class='ctx'> void cxl_bus_drain(void);</div><div class='hunk'>@@ -839,6 +874,12 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+void cxl_endpoint_parse_cdat(struct cxl_port *port);</div><div class='add'>+void cxl_switch_parse_cdat(struct cxl_port *port);</div><div class='add'>+</div><div class='add'>+int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,</div><div class='add'>+				      struct access_coordinate *coord);</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Unit test builds overrides this to __weak, find the 'strong' version</div><div class='ctx'>  * of these symbols in tools/testing/cxl/.</div><div class='head'>diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h<br/>index a2fcbca253f3..5303d6942b88 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/cxlmem.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/cxlmem.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/cxlmem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxlmem.h</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'> #include &lt;linux/cdev.h&gt;</div><div class='ctx'> #include &lt;linux/uuid.h&gt;</div><div class='ctx'> #include &lt;linux/rcuwait.h&gt;</div><div class='add'>+#include &lt;linux/cxl-event.h&gt;</div><div class='add'>+#include &lt;linux/node.h&gt;</div><div class='ctx'> #include "cxl.h"</div><div class='ctx'> </div><div class='ctx'> /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */</div><div class='hunk'>@@ -392,6 +394,20 @@ enum cxl_devtype {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct cxl_dpa_perf - DPA performance property entry</div><div class='add'>+ * @list - list entry</div><div class='add'>+ * @dpa_range - range for DPA address</div><div class='add'>+ * @coord - QoS performance data (i.e. latency, bandwidth)</div><div class='add'>+ * @qos_class - QoS Class cookies</div><div class='add'>+ */</div><div class='add'>+struct cxl_dpa_perf {</div><div class='add'>+	struct list_head list;</div><div class='add'>+	struct range dpa_range;</div><div class='add'>+	struct access_coordinate coord;</div><div class='add'>+	int qos_class;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * struct cxl_dev_state - The driver device state</div><div class='ctx'>  *</div><div class='ctx'>  * cxl_dev_state represents the CXL driver/device state.  It provides an</div><div class='hunk'>@@ -455,6 +471,8 @@ struct cxl_dev_state {</div><div class='ctx'>  * @security: security driver state info</div><div class='ctx'>  * @fw: firmware upload / activation state</div><div class='ctx'>  * @mbox_send: @dev specific transport for transmitting mailbox commands</div><div class='add'>+ * @ram_perf_list: performance data entries matched to RAM</div><div class='add'>+ * @pmem_perf_list: performance data entries matched to PMEM</div><div class='ctx'>  *</div><div class='ctx'>  * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for</div><div class='ctx'>  * details on capacity parameters.</div><div class='hunk'>@@ -475,6 +493,10 @@ struct cxl_memdev_state {</div><div class='ctx'> 	u64 active_persistent_bytes;</div><div class='ctx'> 	u64 next_volatile_bytes;</div><div class='ctx'> 	u64 next_persistent_bytes;</div><div class='add'>+</div><div class='add'>+	struct list_head ram_perf_list;</div><div class='add'>+	struct list_head pmem_perf_list;</div><div class='add'>+</div><div class='ctx'> 	struct cxl_event_state event;</div><div class='ctx'> 	struct cxl_poison_state poison;</div><div class='ctx'> 	struct cxl_security_state security;</div><div class='hunk'>@@ -503,6 +525,7 @@ enum cxl_opcode {</div><div class='ctx'> 	CXL_MBOX_OP_GET_FW_INFO		= 0x0200,</div><div class='ctx'> 	CXL_MBOX_OP_TRANSFER_FW		= 0x0201,</div><div class='ctx'> 	CXL_MBOX_OP_ACTIVATE_FW		= 0x0202,</div><div class='add'>+	CXL_MBOX_OP_GET_TIMESTAMP	= 0x0300,</div><div class='ctx'> 	CXL_MBOX_OP_SET_TIMESTAMP	= 0x0301,</div><div class='ctx'> 	CXL_MBOX_OP_GET_SUPPORTED_LOGS	= 0x0400,</div><div class='ctx'> 	CXL_MBOX_OP_GET_LOG		= 0x0401,</div><div class='hunk'>@@ -580,25 +603,28 @@ struct cxl_mbox_identify {</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Common Event Record Format</div><div class='del'>- * CXL rev 3.0 section 8.2.9.2.1; Table 8-42</div><div class='add'>+ * General Media Event Record UUID</div><div class='add'>+ * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43</div><div class='ctx'>  */</div><div class='del'>-struct cxl_event_record_hdr {</div><div class='del'>-	uuid_t id;</div><div class='del'>-	u8 length;</div><div class='del'>-	u8 flags[3];</div><div class='del'>-	__le16 handle;</div><div class='del'>-	__le16 related_handle;</div><div class='del'>-	__le64 timestamp;</div><div class='del'>-	u8 maint_op_class;</div><div class='del'>-	u8 reserved[15];</div><div class='del'>-} __packed;</div><div class='add'>+#define CXL_EVENT_GEN_MEDIA_UUID                                            \</div><div class='add'>+	UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \</div><div class='add'>+		  0x21, 0xeb, 0xa6)</div><div class='ctx'> </div><div class='del'>-#define CXL_EVENT_RECORD_DATA_LENGTH 0x50</div><div class='del'>-struct cxl_event_record_raw {</div><div class='del'>-	struct cxl_event_record_hdr hdr;</div><div class='del'>-	u8 data[CXL_EVENT_RECORD_DATA_LENGTH];</div><div class='del'>-} __packed;</div><div class='add'>+/*</div><div class='add'>+ * DRAM Event Record UUID</div><div class='add'>+ * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44</div><div class='add'>+ */</div><div class='add'>+#define CXL_EVENT_DRAM_UUID                                                 \</div><div class='add'>+	UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \</div><div class='add'>+		  0x5c, 0x96, 0x24)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Memory Module Event Record UUID</div><div class='add'>+ * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45</div><div class='add'>+ */</div><div class='add'>+#define CXL_EVENT_MEM_MODULE_UUID                                           \</div><div class='add'>+	UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \</div><div class='add'>+		  0x13, 0xb7, 0x74)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Get Event Records output payload</div><div class='hunk'>@@ -641,74 +667,6 @@ struct cxl_mbox_clear_event_payload {</div><div class='ctx'> } __packed;</div><div class='ctx'> #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * General Media Event Record</div><div class='del'>- * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43</div><div class='del'>- */</div><div class='del'>-#define CXL_EVENT_GEN_MED_COMP_ID_SIZE	0x10</div><div class='del'>-struct cxl_event_gen_media {</div><div class='del'>-	struct cxl_event_record_hdr hdr;</div><div class='del'>-	__le64 phys_addr;</div><div class='del'>-	u8 descriptor;</div><div class='del'>-	u8 type;</div><div class='del'>-	u8 transaction_type;</div><div class='del'>-	u8 validity_flags[2];</div><div class='del'>-	u8 channel;</div><div class='del'>-	u8 rank;</div><div class='del'>-	u8 device[3];</div><div class='del'>-	u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];</div><div class='del'>-	u8 reserved[46];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * DRAM Event Record - DER</div><div class='del'>- * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44</div><div class='del'>- */</div><div class='del'>-#define CXL_EVENT_DER_CORRECTION_MASK_SIZE	0x20</div><div class='del'>-struct cxl_event_dram {</div><div class='del'>-	struct cxl_event_record_hdr hdr;</div><div class='del'>-	__le64 phys_addr;</div><div class='del'>-	u8 descriptor;</div><div class='del'>-	u8 type;</div><div class='del'>-	u8 transaction_type;</div><div class='del'>-	u8 validity_flags[2];</div><div class='del'>-	u8 channel;</div><div class='del'>-	u8 rank;</div><div class='del'>-	u8 nibble_mask[3];</div><div class='del'>-	u8 bank_group;</div><div class='del'>-	u8 bank;</div><div class='del'>-	u8 row[3];</div><div class='del'>-	u8 column[2];</div><div class='del'>-	u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];</div><div class='del'>-	u8 reserved[0x17];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Get Health Info Record</div><div class='del'>- * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100</div><div class='del'>- */</div><div class='del'>-struct cxl_get_health_info {</div><div class='del'>-	u8 health_status;</div><div class='del'>-	u8 media_status;</div><div class='del'>-	u8 add_status;</div><div class='del'>-	u8 life_used;</div><div class='del'>-	u8 device_temp[2];</div><div class='del'>-	u8 dirty_shutdown_cnt[4];</div><div class='del'>-	u8 cor_vol_err_cnt[4];</div><div class='del'>-	u8 cor_per_err_cnt[4];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Memory Module Event Record</div><div class='del'>- * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45</div><div class='del'>- */</div><div class='del'>-struct cxl_event_mem_module {</div><div class='del'>-	struct cxl_event_record_hdr hdr;</div><div class='del'>-	u8 event_type;</div><div class='del'>-	struct cxl_get_health_info info;</div><div class='del'>-	u8 reserved[0x3d];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='ctx'> struct cxl_mbox_get_partition_info {</div><div class='ctx'> 	__le64 active_volatile_cap;</div><div class='ctx'> 	__le64 active_persistent_cap;</div><div class='hunk'>@@ -866,6 +824,10 @@ void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,</div><div class='ctx'> void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,</div><div class='ctx'> 				  unsigned long *cmds);</div><div class='ctx'> void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);</div><div class='add'>+void cxl_event_trace_record(const struct cxl_memdev *cxlmd,</div><div class='add'>+			    enum cxl_event_log_type type,</div><div class='add'>+			    enum cxl_event_type event_type,</div><div class='add'>+			    const uuid_t *uuid, union cxl_event *evt);</div><div class='ctx'> int cxl_set_timestamp(struct cxl_memdev_state *mds);</div><div class='ctx'> int cxl_poison_state_init(struct cxl_memdev_state *mds);</div><div class='ctx'> int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,</div><div class='head'>diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h<br/>index 0fa4799ea316..711b05d9a370 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/cxlpci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/cxlpci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/cxlpci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/cxlpci.h</a></div><div class='hunk'>@@ -85,6 +85,19 @@ struct cdat_entry_header {</div><div class='ctx'> 	__le16 length;</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * CXL v3.0 6.2.3 Table 6-4</div><div class='add'>+ * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits</div><div class='add'>+ * mode, otherwise it's 68B flits mode.</div><div class='add'>+ */</div><div class='add'>+static inline bool cxl_pci_flit_256(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	u16 lnksta2;</div><div class='add'>+</div><div class='add'>+	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &amp;lnksta2);</div><div class='add'>+	return lnksta2 &amp; PCI_EXP_LNKSTA2_FLIT;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int devm_cxl_port_enumerate_dports(struct cxl_port *port);</div><div class='ctx'> struct cxl_dev_state;</div><div class='ctx'> int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,</div><div class='head'>diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c<br/>index e087febf9af0..c5c9d8e0d88d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/mem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/mem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/mem.c</a></div><div class='hunk'>@@ -215,23 +215,78 @@ static ssize_t trigger_poison_list_store(struct device *dev,</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_WO(trigger_poison_list);</div><div class='ctx'> </div><div class='add'>+static ssize_t ram_qos_class_show(struct device *dev,</div><div class='add'>+				  struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);</div><div class='add'>+	struct cxl_dev_state *cxlds = cxlmd-&gt;cxlds;</div><div class='add'>+	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf;</div><div class='add'>+</div><div class='add'>+	if (!dev-&gt;driver)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (list_empty(&amp;mds-&gt;ram_perf_list))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	dpa_perf = list_first_entry(&amp;mds-&gt;ram_perf_list, struct cxl_dpa_perf,</div><div class='add'>+				    list);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", dpa_perf-&gt;qos_class);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct device_attribute dev_attr_ram_qos_class =</div><div class='add'>+	__ATTR(qos_class, 0444, ram_qos_class_show, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t pmem_qos_class_show(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);</div><div class='add'>+	struct cxl_dev_state *cxlds = cxlmd-&gt;cxlds;</div><div class='add'>+	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);</div><div class='add'>+	struct cxl_dpa_perf *dpa_perf;</div><div class='add'>+</div><div class='add'>+	if (!dev-&gt;driver)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (list_empty(&amp;mds-&gt;pmem_perf_list))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	dpa_perf = list_first_entry(&amp;mds-&gt;pmem_perf_list, struct cxl_dpa_perf,</div><div class='add'>+				    list);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", dpa_perf-&gt;qos_class);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct device_attribute dev_attr_pmem_qos_class =</div><div class='add'>+	__ATTR(qos_class, 0444, pmem_qos_class_show, NULL);</div><div class='add'>+</div><div class='ctx'> static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)</div><div class='ctx'> {</div><div class='del'>-	if (a == &amp;dev_attr_trigger_poison_list.attr) {</div><div class='del'>-		struct device *dev = kobj_to_dev(kobj);</div><div class='del'>-		struct cxl_memdev *cxlmd = to_cxl_memdev(dev);</div><div class='del'>-		struct cxl_memdev_state *mds =</div><div class='del'>-			to_cxl_memdev_state(cxlmd-&gt;cxlds);</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);</div><div class='add'>+	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd-&gt;cxlds);</div><div class='ctx'> </div><div class='add'>+	if (a == &amp;dev_attr_trigger_poison_list.attr)</div><div class='ctx'> 		if (!test_bit(CXL_POISON_ENABLED_LIST,</div><div class='ctx'> 			      mds-&gt;poison.enabled_cmds))</div><div class='ctx'> 			return 0;</div><div class='del'>-	}</div><div class='add'>+</div><div class='add'>+	if (a == &amp;dev_attr_pmem_qos_class.attr)</div><div class='add'>+		if (list_empty(&amp;mds-&gt;pmem_perf_list))</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+	if (a == &amp;dev_attr_ram_qos_class.attr)</div><div class='add'>+		if (list_empty(&amp;mds-&gt;ram_perf_list))</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='ctx'> 	return a-&gt;mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct attribute *cxl_mem_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_trigger_poison_list.attr,</div><div class='add'>+	&amp;dev_attr_ram_qos_class.attr,</div><div class='add'>+	&amp;dev_attr_pmem_qos_class.attr,</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c<br/>index 0155fb66b580..4fd1f207c84e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/pci.c</a></div><div class='hunk'>@@ -1,5 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /* Copyright(c) 2020 Intel Corporation. All rights reserved. */</div><div class='add'>+#include &lt;asm-generic/unaligned.h&gt;</div><div class='ctx'> #include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='ctx'> #include &lt;linux/moduleparam.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -969,6 +970,61 @@ static struct pci_driver cxl_pci_driver = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0)</div><div class='add'>+static void cxl_cper_event_call(enum cxl_event_type ev_type,</div><div class='add'>+				struct cxl_cper_event_rec *rec)</div><div class='add'>+{</div><div class='add'>+	struct cper_cxl_event_devid *device_id = &amp;rec-&gt;hdr.device_id;</div><div class='add'>+	struct pci_dev *pdev __free(pci_dev_put) = NULL;</div><div class='add'>+	enum cxl_event_log_type log_type;</div><div class='add'>+	struct cxl_dev_state *cxlds;</div><div class='add'>+	unsigned int devfn;</div><div class='add'>+	u32 hdr_flags;</div><div class='add'>+</div><div class='add'>+	devfn = PCI_DEVFN(device_id-&gt;device_num, device_id-&gt;func_num);</div><div class='add'>+	pdev = pci_get_domain_bus_and_slot(device_id-&gt;segment_num,</div><div class='add'>+					   device_id-&gt;bus_num, devfn);</div><div class='add'>+	if (!pdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	guard(pci_dev)(pdev);</div><div class='add'>+	if (pdev-&gt;driver != &amp;cxl_pci_driver)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cxlds = pci_get_drvdata(pdev);</div><div class='add'>+	if (!cxlds)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Fabricate a log type */</div><div class='add'>+	hdr_flags = get_unaligned_le24(rec-&gt;event.generic.hdr.flags);</div><div class='add'>+	log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags);</div><div class='add'>+</div><div class='add'>+	cxl_event_trace_record(cxlds-&gt;cxlmd, log_type, ev_type,</div><div class='add'>+			       &amp;uuid_null, &amp;rec-&gt;event);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __init cxl_pci_driver_init(void)</div><div class='add'>+{</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	rc = cxl_cper_register_callback(cxl_cper_event_call);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rc = pci_register_driver(&amp;cxl_pci_driver);</div><div class='add'>+	if (rc)</div><div class='add'>+		cxl_cper_unregister_callback(cxl_cper_event_call);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit cxl_pci_driver_exit(void)</div><div class='add'>+{</div><div class='add'>+	pci_unregister_driver(&amp;cxl_pci_driver);</div><div class='add'>+	cxl_cper_unregister_callback(cxl_cper_event_call);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+module_init(cxl_pci_driver_init);</div><div class='add'>+module_exit(cxl_pci_driver_exit);</div><div class='ctx'> MODULE_LICENSE("GPL v2");</div><div class='del'>-module_pci_driver(cxl_pci_driver);</div><div class='ctx'> MODULE_IMPORT_NS(CXL);</div><div class='head'>diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c<br/>index 47bc8e0b8590..97c21566677a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/cxl/port.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/cxl/port.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/cxl/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/cxl/port.c</a></div><div class='hunk'>@@ -69,6 +69,8 @@ static int cxl_switch_port_probe(struct cxl_port *port)</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='add'>+	cxl_switch_parse_cdat(port);</div><div class='add'>+</div><div class='ctx'> 	cxlhdm = devm_cxl_setup_hdm(port, NULL);</div><div class='ctx'> 	if (!IS_ERR(cxlhdm))</div><div class='ctx'> 		return devm_cxl_enumerate_decoders(cxlhdm, NULL);</div><div class='hunk'>@@ -109,6 +111,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)</div><div class='ctx'> </div><div class='ctx'> 	/* Cache the data early to ensure is_visible() works */</div><div class='ctx'> 	read_cdat_data(port);</div><div class='add'>+	cxl_endpoint_parse_cdat(port);</div><div class='ctx'> </div><div class='ctx'> 	get_device(&amp;cxlmd-&gt;dev);</div><div class='ctx'> 	rc = devm_add_action_or_reset(&amp;port-&gt;dev, schedule_detach, cxlmd);</div><div class='hunk'>@@ -127,14 +130,15 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)</div><div class='ctx'> 	 * This can't fail in practice as CXL root exit unregisters all</div><div class='ctx'> 	 * descendant ports and that in turn synchronizes with cxl_port_probe()</div><div class='ctx'> 	 */</div><div class='del'>-	root = find_cxl_root(port);</div><div class='add'>+	struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);</div><div class='add'>+</div><div class='add'>+	root = &amp;cxl_root-&gt;port;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Now that all endpoint decoders are successfully enumerated, try to</div><div class='ctx'> 	 * assemble regions from committed decoders</div><div class='ctx'> 	 */</div><div class='ctx'> 	device_for_each_child(&amp;port-&gt;dev, root, discover_region);</div><div class='del'>-	put_device(&amp;root-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/dax/bus.c b/drivers/dax/bus.c<br/>index 1659b787b65f..1ff1ab5fa105 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/bus.c</a></div><div class='hunk'>@@ -367,6 +367,7 @@ static ssize_t create_store(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 			.dax_region = dax_region,</div><div class='ctx'> 			.size = 0,</div><div class='ctx'> 			.id = -1,</div><div class='add'>+			.memmap_on_memory = false,</div><div class='ctx'> 		};</div><div class='ctx'> 		struct dev_dax *dev_dax = devm_create_dev_dax(&amp;data);</div><div class='ctx'> </div><div class='hunk'>@@ -1400,6 +1401,8 @@ struct dev_dax *devm_create_dev_dax(struct dev_dax_data *data)</div><div class='ctx'> 	dev_dax-&gt;align = dax_region-&gt;align;</div><div class='ctx'> 	ida_init(&amp;dev_dax-&gt;ida);</div><div class='ctx'> </div><div class='add'>+	dev_dax-&gt;memmap_on_memory = data-&gt;memmap_on_memory;</div><div class='add'>+</div><div class='ctx'> 	inode = dax_inode(dax_dev);</div><div class='ctx'> 	dev-&gt;devt = inode-&gt;i_rdev;</div><div class='ctx'> 	dev-&gt;bus = &amp;dax_bus_type;</div><div class='head'>diff --git a/drivers/dax/bus.h b/drivers/dax/bus.h<br/>index 1ccd23360124..cbbf64443098 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/bus.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/bus.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/bus.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/bus.h</a></div><div class='hunk'>@@ -23,6 +23,7 @@ struct dev_dax_data {</div><div class='ctx'> 	struct dev_pagemap *pgmap;</div><div class='ctx'> 	resource_size_t size;</div><div class='ctx'> 	int id;</div><div class='add'>+	bool memmap_on_memory;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dev_dax *devm_create_dev_dax(struct dev_dax_data *data);</div><div class='head'>diff --git a/drivers/dax/cxl.c b/drivers/dax/cxl.c<br/>index 8bc9d04034d6..c696837ab23c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/cxl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/cxl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/cxl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/cxl.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@ static int cxl_dax_region_probe(struct device *dev)</div><div class='ctx'> 		.dax_region = dax_region,</div><div class='ctx'> 		.id = -1,</div><div class='ctx'> 		.size = range_len(&amp;cxlr_dax-&gt;hpa_range),</div><div class='add'>+		.memmap_on_memory = true,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	return PTR_ERR_OR_ZERO(devm_create_dev_dax(&amp;data));</div><div class='head'>diff --git a/drivers/dax/dax-private.h b/drivers/dax/dax-private.h<br/>index 27cf2daaaa79..446617b73aea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/dax-private.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/dax-private.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/dax-private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/dax-private.h</a></div><div class='hunk'>@@ -70,6 +70,7 @@ struct dev_dax {</div><div class='ctx'> 	struct ida ida;</div><div class='ctx'> 	struct device dev;</div><div class='ctx'> 	struct dev_pagemap *pgmap;</div><div class='add'>+	bool memmap_on_memory;</div><div class='ctx'> 	int nr_range;</div><div class='ctx'> 	struct dev_dax_range {</div><div class='ctx'> 		unsigned long pgoff;</div><div class='head'>diff --git a/drivers/dax/hmem/hmem.c b/drivers/dax/hmem/hmem.c<br/>index 5d2ddef0f8f5..b9da69f92697 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/hmem/hmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/hmem/hmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/hmem/hmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/hmem/hmem.c</a></div><div class='hunk'>@@ -36,6 +36,7 @@ static int dax_hmem_probe(struct platform_device *pdev)</div><div class='ctx'> 		.dax_region = dax_region,</div><div class='ctx'> 		.id = -1,</div><div class='ctx'> 		.size = region_idle ? 0 : range_len(&amp;mri-&gt;range),</div><div class='add'>+		.memmap_on_memory = false,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	return PTR_ERR_OR_ZERO(devm_create_dev_dax(&amp;data));</div><div class='head'>diff --git a/drivers/dax/kmem.c b/drivers/dax/kmem.c<br/>index 369c698b7706..42ee360cf4e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/kmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/kmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/kmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/kmem.c</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> #include &lt;linux/mm.h&gt;</div><div class='ctx'> #include &lt;linux/mman.h&gt;</div><div class='ctx'> #include &lt;linux/memory-tiers.h&gt;</div><div class='add'>+#include &lt;linux/memory_hotplug.h&gt;</div><div class='ctx'> #include "dax-private.h"</div><div class='ctx'> #include "bus.h"</div><div class='ctx'> </div><div class='hunk'>@@ -93,6 +94,7 @@ static int dev_dax_kmem_probe(struct dev_dax *dev_dax)</div><div class='ctx'> 	struct dax_kmem_data *data;</div><div class='ctx'> 	struct memory_dev_type *mtype;</div><div class='ctx'> 	int i, rc, mapped = 0;</div><div class='add'>+	mhp_t mhp_flags;</div><div class='ctx'> 	int numa_node;</div><div class='ctx'> 	int adist = MEMTIER_DEFAULT_DAX_ADISTANCE;</div><div class='ctx'> </div><div class='hunk'>@@ -179,12 +181,16 @@ static int dev_dax_kmem_probe(struct dev_dax *dev_dax)</div><div class='ctx'> 		 */</div><div class='ctx'> 		res-&gt;flags = IORESOURCE_SYSTEM_RAM;</div><div class='ctx'> </div><div class='add'>+		mhp_flags = MHP_NID_IS_MGID;</div><div class='add'>+		if (dev_dax-&gt;memmap_on_memory)</div><div class='add'>+			mhp_flags |= MHP_MEMMAP_ON_MEMORY;</div><div class='add'>+</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Ensure that future kexec'd kernels will not treat</div><div class='ctx'> 		 * this as RAM automatically.</div><div class='ctx'> 		 */</div><div class='ctx'> 		rc = add_memory_driver_managed(data-&gt;mgid, range.start,</div><div class='del'>-				range_len(&amp;range), kmem_name, MHP_NID_IS_MGID);</div><div class='add'>+				range_len(&amp;range), kmem_name, mhp_flags);</div><div class='ctx'> </div><div class='ctx'> 		if (rc) {</div><div class='ctx'> 			dev_warn(dev, "mapping%d: %#llx-%#llx memory add failed\n",</div><div class='head'>diff --git a/drivers/dax/pmem.c b/drivers/dax/pmem.c<br/>index ae0cb113a5d3..f3c6c67b8412 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/pmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/pmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/pmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/pmem.c</a></div><div class='hunk'>@@ -63,6 +63,7 @@ static struct dev_dax *__dax_pmem_probe(struct device *dev)</div><div class='ctx'> 		.id = id,</div><div class='ctx'> 		.pgmap = &amp;pgmap,</div><div class='ctx'> 		.size = range_len(&amp;range),</div><div class='add'>+		.memmap_on_memory = false,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	return devm_create_dev_dax(&amp;data);</div><div class='head'>diff --git a/drivers/dax/super.c b/drivers/dax/super.c<br/>index 0da9232ea175..f4b635526345 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dax/super.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dax/super.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dax/super.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dax/super.c</a></div><div class='hunk'>@@ -326,7 +326,8 @@ void kill_dax(struct dax_device *dax_dev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (dax_dev-&gt;holder_data != NULL)</div><div class='del'>-		dax_holder_notify_failure(dax_dev, 0, U64_MAX, 0);</div><div class='add'>+		dax_holder_notify_failure(dax_dev, 0, U64_MAX,</div><div class='add'>+				MF_MEM_PRE_REMOVE);</div><div class='ctx'> </div><div class='ctx'> 	clear_bit(DAXDEV_ALIVE, &amp;dax_dev-&gt;flags);</div><div class='ctx'> 	synchronize_srcu(&amp;dax_srcu);</div><div class='head'>diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c<br/>index b3a68d5833bd..98657d3b9435 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/devfreq/devfreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/devfreq/devfreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/devfreq/devfreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/devfreq/devfreq.c</a></div><div class='hunk'>@@ -461,10 +461,14 @@ static void devfreq_monitor(struct work_struct *work)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		dev_err(&amp;devfreq-&gt;dev, "dvfs failed with (%d) error\n", err);</div><div class='ctx'> </div><div class='add'>+	if (devfreq-&gt;stop_polling)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	queue_delayed_work(devfreq_wq, &amp;devfreq-&gt;work,</div><div class='ctx'> 				msecs_to_jiffies(devfreq-&gt;profile-&gt;polling_ms));</div><div class='del'>-	mutex_unlock(&amp;devfreq-&gt;lock);</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;devfreq-&gt;lock);</div><div class='ctx'> 	trace_devfreq_monitor(devfreq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -483,6 +487,10 @@ void devfreq_monitor_start(struct devfreq *devfreq)</div><div class='ctx'> 	if (IS_SUPPORTED_FLAG(devfreq-&gt;governor-&gt;flags, IRQ_DRIVEN))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;devfreq-&gt;lock);</div><div class='add'>+	if (delayed_work_pending(&amp;devfreq-&gt;work))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	switch (devfreq-&gt;profile-&gt;timer) {</div><div class='ctx'> 	case DEVFREQ_TIMER_DEFERRABLE:</div><div class='ctx'> 		INIT_DEFERRABLE_WORK(&amp;devfreq-&gt;work, devfreq_monitor);</div><div class='hunk'>@@ -491,12 +499,16 @@ void devfreq_monitor_start(struct devfreq *devfreq)</div><div class='ctx'> 		INIT_DELAYED_WORK(&amp;devfreq-&gt;work, devfreq_monitor);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		return;</div><div class='add'>+		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (devfreq-&gt;profile-&gt;polling_ms)</div><div class='ctx'> 		queue_delayed_work(devfreq_wq, &amp;devfreq-&gt;work,</div><div class='ctx'> 			msecs_to_jiffies(devfreq-&gt;profile-&gt;polling_ms));</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	devfreq-&gt;stop_polling = false;</div><div class='add'>+	mutex_unlock(&amp;devfreq-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(devfreq_monitor_start);</div><div class='ctx'> </div><div class='hunk'>@@ -513,6 +525,14 @@ void devfreq_monitor_stop(struct devfreq *devfreq)</div><div class='ctx'> 	if (IS_SUPPORTED_FLAG(devfreq-&gt;governor-&gt;flags, IRQ_DRIVEN))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;devfreq-&gt;lock);</div><div class='add'>+	if (devfreq-&gt;stop_polling) {</div><div class='add'>+		mutex_unlock(&amp;devfreq-&gt;lock);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	devfreq-&gt;stop_polling = true;</div><div class='add'>+	mutex_unlock(&amp;devfreq-&gt;lock);</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;devfreq-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(devfreq_monitor_stop);</div><div class='hunk'>@@ -1688,7 +1708,7 @@ static ssize_t trans_stat_show(struct device *dev,</div><div class='ctx'> 			       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct devfreq *df = to_devfreq(dev);</div><div class='del'>-	ssize_t len;</div><div class='add'>+	ssize_t len = 0;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	unsigned int max_state;</div><div class='ctx'> </div><div class='hunk'>@@ -1697,7 +1717,7 @@ static ssize_t trans_stat_show(struct device *dev,</div><div class='ctx'> 	max_state = df-&gt;max_state;</div><div class='ctx'> </div><div class='ctx'> 	if (max_state == 0)</div><div class='del'>-		return sprintf(buf, "Not Supported.\n");</div><div class='add'>+		return sysfs_emit(buf, "Not Supported.\n");</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;df-&gt;lock);</div><div class='ctx'> 	if (!df-&gt;stop_polling &amp;&amp;</div><div class='hunk'>@@ -1707,31 +1727,49 @@ static ssize_t trans_stat_show(struct device *dev,</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;df-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	len = sprintf(buf, "     From  :   To\n");</div><div class='del'>-	len += sprintf(buf + len, "           :");</div><div class='del'>-	for (i = 0; i &lt; max_state; i++)</div><div class='del'>-		len += sprintf(buf + len, "%10lu",</div><div class='del'>-				df-&gt;freq_table[i]);</div><div class='add'>+	len += sysfs_emit_at(buf, len, "     From  :   To\n");</div><div class='add'>+	len += sysfs_emit_at(buf, len, "           :");</div><div class='add'>+	for (i = 0; i &lt; max_state; i++) {</div><div class='add'>+		if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+			break;</div><div class='add'>+		len += sysfs_emit_at(buf, len, "%10lu",</div><div class='add'>+				     df-&gt;freq_table[i]);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	len += sprintf(buf + len, "   time(ms)\n");</div><div class='add'>+	if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+		return PAGE_SIZE - 1;</div><div class='add'>+	len += sysfs_emit_at(buf, len, "   time(ms)\n");</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; max_state; i++) {</div><div class='del'>-		if (df-&gt;freq_table[i] == df-&gt;previous_freq)</div><div class='del'>-			len += sprintf(buf + len, "*");</div><div class='add'>+		if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+			break;</div><div class='add'>+		if (df-&gt;freq_table[2] == df-&gt;previous_freq)</div><div class='add'>+			len += sysfs_emit_at(buf, len, "*");</div><div class='ctx'> 		else</div><div class='del'>-			len += sprintf(buf + len, " ");</div><div class='del'>-</div><div class='del'>-		len += sprintf(buf + len, "%10lu:", df-&gt;freq_table[i]);</div><div class='del'>-		for (j = 0; j &lt; max_state; j++)</div><div class='del'>-			len += sprintf(buf + len, "%10u",</div><div class='add'>+			len += sysfs_emit_at(buf, len, " ");</div><div class='add'>+		if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+			break;</div><div class='add'>+		len += sysfs_emit_at(buf, len, "%10lu:", df-&gt;freq_table[i]);</div><div class='add'>+		for (j = 0; j &lt; max_state; j++) {</div><div class='add'>+			if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+				break;</div><div class='add'>+			len += sysfs_emit_at(buf, len, "%10u",</div><div class='ctx'> 				df-&gt;stats.trans_table[(i * max_state) + j]);</div><div class='add'>+		}</div><div class='add'>+		if (len &gt;= PAGE_SIZE - 1)</div><div class='add'>+			break;</div><div class='add'>+		len += sysfs_emit_at(buf, len, "%10llu\n", (u64)</div><div class='add'>+				     jiffies64_to_msecs(df-&gt;stats.time_in_state[i]));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		len += sprintf(buf + len, "%10llu\n", (u64)</div><div class='del'>-			jiffies64_to_msecs(df-&gt;stats.time_in_state[i]));</div><div class='add'>+	if (len &lt; PAGE_SIZE - 1)</div><div class='add'>+		len += sysfs_emit_at(buf, len, "Total transition : %u\n",</div><div class='add'>+				     df-&gt;stats.total_trans);</div><div class='add'>+	if (len &gt;= PAGE_SIZE - 1) {</div><div class='add'>+		pr_warn_once("devfreq transition table exceeds PAGE_SIZE. Disabling\n");</div><div class='add'>+		return -EFBIG;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	len += sprintf(buf + len, "Total transition : %u\n",</div><div class='del'>-					df-&gt;stats.total_trans);</div><div class='ctx'> 	return len;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c<br/>index cab4f41f0470..e2869fb31140 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma-buf/dma-resv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma-buf/dma-resv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma-buf/dma-resv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma-buf/dma-resv.c</a></div><div class='hunk'>@@ -301,7 +301,7 @@ void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence,</div><div class='ctx'> </div><div class='ctx'> 		dma_resv_list_entry(fobj, i, obj, &amp;old, &amp;old_usage);</div><div class='ctx'> 		if ((old-&gt;context == fence-&gt;context &amp;&amp; old_usage &gt;= usage &amp;&amp;</div><div class='del'>-		     dma_fence_is_later(fence, old)) ||</div><div class='add'>+		     dma_fence_is_later_or_same(fence, old)) ||</div><div class='ctx'> 		    dma_fence_is_signaled(old)) {</div><div class='ctx'> 			dma_resv_list_set(fobj, i, fence, usage);</div><div class='ctx'> 			dma_fence_put(old);</div><div class='head'>diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig<br/>index 70ba506dabab..e928f2ca0f1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/Kconfig</a></div><div class='hunk'>@@ -378,6 +378,20 @@ config LPC18XX_DMAMUX</div><div class='ctx'> 	  Enable support for DMA on NXP LPC18xx/43xx platforms</div><div class='ctx'> 	  with PL080 and multiplexed DMA request lines.</div><div class='ctx'> </div><div class='add'>+config LS2X_APB_DMA</div><div class='add'>+	tristate "Loongson LS2X APB DMA support"</div><div class='add'>+	depends on LOONGARCH || COMPILE_TEST</div><div class='add'>+	select DMA_ENGINE</div><div class='add'>+	select DMA_VIRTUAL_CHANNELS</div><div class='add'>+	help</div><div class='add'>+	  Support for the Loongson LS2X APB DMA controller driver. The</div><div class='add'>+	  DMA controller is having single DMA channel which can be</div><div class='add'>+	  configured for different peripherals like audio, nand, sdio</div><div class='add'>+	  etc which is in APB bus.</div><div class='add'>+</div><div class='add'>+	  This DMA controller transfers data from memory to peripheral fifo.</div><div class='add'>+	  It does not support memory to memory data transfer.</div><div class='add'>+</div><div class='ctx'> config MCF_EDMA</div><div class='ctx'> 	tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"</div><div class='ctx'> 	depends on M5441x || COMPILE_TEST</div><div class='head'>diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile<br/>index 83553a97a010..dfd40d14e408 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/Makefile</a></div><div class='hunk'>@@ -48,6 +48,7 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioat/</div><div class='ctx'> obj-y += idxd/</div><div class='ctx'> obj-$(CONFIG_K3_DMA) += k3dma.o</div><div class='ctx'> obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o</div><div class='add'>+obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o</div><div class='ctx'> obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o</div><div class='ctx'> obj-$(CONFIG_MILBEAUT_XDMAC) += milbeaut-xdmac.o</div><div class='ctx'> obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o</div><div class='head'>diff --git a/drivers/dma/apple-admac.c b/drivers/dma/apple-admac.c<br/>index 5b63996640d9..9588773dd2eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/apple-admac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/apple-admac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/apple-admac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/apple-admac.c</a></div><div class='hunk'>@@ -57,6 +57,8 @@</div><div class='ctx'> </div><div class='ctx'> #define REG_BUS_WIDTH(ch)	(0x8040 + (ch) * 0x200)</div><div class='ctx'> </div><div class='add'>+#define BUS_WIDTH_WORD_SIZE	GENMASK(3, 0)</div><div class='add'>+#define BUS_WIDTH_FRAME_SIZE	GENMASK(7, 4)</div><div class='ctx'> #define BUS_WIDTH_8BIT		0x00</div><div class='ctx'> #define BUS_WIDTH_16BIT		0x01</div><div class='ctx'> #define BUS_WIDTH_32BIT		0x02</div><div class='hunk'>@@ -740,7 +742,8 @@ static int admac_device_config(struct dma_chan *chan,</div><div class='ctx'> 	struct admac_data *ad = adchan-&gt;host;</div><div class='ctx'> 	bool is_tx = admac_chan_direction(adchan-&gt;no) == DMA_MEM_TO_DEV;</div><div class='ctx'> 	int wordsize = 0;</div><div class='del'>-	u32 bus_width = 0;</div><div class='add'>+	u32 bus_width = readl_relaxed(ad-&gt;base + REG_BUS_WIDTH(adchan-&gt;no)) &amp;</div><div class='add'>+		~(BUS_WIDTH_WORD_SIZE | BUS_WIDTH_FRAME_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	switch (is_tx ? config-&gt;dst_addr_width : config-&gt;src_addr_width) {</div><div class='ctx'> 	case DMA_SLAVE_BUSWIDTH_1_BYTE:</div><div class='head'>diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c<br/>index 2457a420c13d..4e339c04fc1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/dma-axi-dmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/dma-axi-dmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/dma-axi-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dma-axi-dmac.c</a></div><div class='hunk'>@@ -81,9 +81,13 @@</div><div class='ctx'> #define AXI_DMAC_REG_CURRENT_DEST_ADDR	0x438</div><div class='ctx'> #define AXI_DMAC_REG_PARTIAL_XFER_LEN	0x44c</div><div class='ctx'> #define AXI_DMAC_REG_PARTIAL_XFER_ID	0x450</div><div class='add'>+#define AXI_DMAC_REG_CURRENT_SG_ID	0x454</div><div class='add'>+#define AXI_DMAC_REG_SG_ADDRESS		0x47c</div><div class='add'>+#define AXI_DMAC_REG_SG_ADDRESS_HIGH	0x4bc</div><div class='ctx'> </div><div class='ctx'> #define AXI_DMAC_CTRL_ENABLE		BIT(0)</div><div class='ctx'> #define AXI_DMAC_CTRL_PAUSE		BIT(1)</div><div class='add'>+#define AXI_DMAC_CTRL_ENABLE_SG		BIT(2)</div><div class='ctx'> </div><div class='ctx'> #define AXI_DMAC_IRQ_SOT		BIT(0)</div><div class='ctx'> #define AXI_DMAC_IRQ_EOT		BIT(1)</div><div class='hunk'>@@ -97,20 +101,35 @@</div><div class='ctx'> /* The maximum ID allocated by the hardware is 31 */</div><div class='ctx'> #define AXI_DMAC_SG_UNUSED 32U</div><div class='ctx'> </div><div class='add'>+/* Flags for axi_dmac_hw_desc.flags */</div><div class='add'>+#define AXI_DMAC_HW_FLAG_LAST		BIT(0)</div><div class='add'>+#define AXI_DMAC_HW_FLAG_IRQ		BIT(1)</div><div class='add'>+</div><div class='add'>+struct axi_dmac_hw_desc {</div><div class='add'>+	u32 flags;</div><div class='add'>+	u32 id;</div><div class='add'>+	u64 dest_addr;</div><div class='add'>+	u64 src_addr;</div><div class='add'>+	u64 next_sg_addr;</div><div class='add'>+	u32 y_len;</div><div class='add'>+	u32 x_len;</div><div class='add'>+	u32 src_stride;</div><div class='add'>+	u32 dst_stride;</div><div class='add'>+	u64 __pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct axi_dmac_sg {</div><div class='del'>-	dma_addr_t src_addr;</div><div class='del'>-	dma_addr_t dest_addr;</div><div class='del'>-	unsigned int x_len;</div><div class='del'>-	unsigned int y_len;</div><div class='del'>-	unsigned int dest_stride;</div><div class='del'>-	unsigned int src_stride;</div><div class='del'>-	unsigned int id;</div><div class='ctx'> 	unsigned int partial_len;</div><div class='ctx'> 	bool schedule_when_free;</div><div class='add'>+</div><div class='add'>+	struct axi_dmac_hw_desc *hw;</div><div class='add'>+	dma_addr_t hw_phys;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct axi_dmac_desc {</div><div class='ctx'> 	struct virt_dma_desc vdesc;</div><div class='add'>+	struct axi_dmac_chan *chan;</div><div class='add'>+</div><div class='ctx'> 	bool cyclic;</div><div class='ctx'> 	bool have_partial_xfer;</div><div class='ctx'> </div><div class='hunk'>@@ -139,6 +158,7 @@ struct axi_dmac_chan {</div><div class='ctx'> 	bool hw_partial_xfer;</div><div class='ctx'> 	bool hw_cyclic;</div><div class='ctx'> 	bool hw_2d;</div><div class='add'>+	bool hw_sg;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct axi_dmac {</div><div class='hunk'>@@ -213,9 +233,11 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)</div><div class='ctx'> 	unsigned int flags = 0;</div><div class='ctx'> 	unsigned int val;</div><div class='ctx'> </div><div class='del'>-	val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);</div><div class='del'>-	if (val) /* Queue is full, wait for the next SOT IRQ */</div><div class='del'>-		return;</div><div class='add'>+	if (!chan-&gt;hw_sg) {</div><div class='add'>+		val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);</div><div class='add'>+		if (val) /* Queue is full, wait for the next SOT IRQ */</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	desc = chan-&gt;next_desc;</div><div class='ctx'> </div><div class='hunk'>@@ -229,14 +251,15 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)</div><div class='ctx'> 	sg = &amp;desc-&gt;sg[desc-&gt;num_submitted];</div><div class='ctx'> </div><div class='ctx'> 	/* Already queued in cyclic mode. Wait for it to finish */</div><div class='del'>-	if (sg-&gt;id != AXI_DMAC_SG_UNUSED) {</div><div class='add'>+	if (sg-&gt;hw-&gt;id != AXI_DMAC_SG_UNUSED) {</div><div class='ctx'> 		sg-&gt;schedule_when_free = true;</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	desc-&gt;num_submitted++;</div><div class='del'>-	if (desc-&gt;num_submitted == desc-&gt;num_sgs ||</div><div class='del'>-	    desc-&gt;have_partial_xfer) {</div><div class='add'>+	if (chan-&gt;hw_sg) {</div><div class='add'>+		chan-&gt;next_desc = NULL;</div><div class='add'>+	} else if (++desc-&gt;num_submitted == desc-&gt;num_sgs ||</div><div class='add'>+		   desc-&gt;have_partial_xfer) {</div><div class='ctx'> 		if (desc-&gt;cyclic)</div><div class='ctx'> 			desc-&gt;num_submitted = 0; /* Start again */</div><div class='ctx'> 		else</div><div class='hunk'>@@ -246,32 +269,42 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)</div><div class='ctx'> 		chan-&gt;next_desc = desc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sg-&gt;id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);</div><div class='add'>+	sg-&gt;hw-&gt;id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);</div><div class='ctx'> </div><div class='del'>-	if (axi_dmac_dest_is_mem(chan)) {</div><div class='del'>-		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg-&gt;dest_addr);</div><div class='del'>-		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg-&gt;dest_stride);</div><div class='del'>-	}</div><div class='add'>+	if (!chan-&gt;hw_sg) {</div><div class='add'>+		if (axi_dmac_dest_is_mem(chan)) {</div><div class='add'>+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg-&gt;hw-&gt;dest_addr);</div><div class='add'>+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg-&gt;hw-&gt;dst_stride);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (axi_dmac_src_is_mem(chan)) {</div><div class='del'>-		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg-&gt;src_addr);</div><div class='del'>-		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg-&gt;src_stride);</div><div class='add'>+		if (axi_dmac_src_is_mem(chan)) {</div><div class='add'>+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg-&gt;hw-&gt;src_addr);</div><div class='add'>+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg-&gt;hw-&gt;src_stride);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If the hardware supports cyclic transfers and there is no callback to</div><div class='del'>-	 * call and only a single segment, enable hw cyclic mode to avoid</div><div class='del'>-	 * unnecessary interrupts.</div><div class='add'>+	 * call, enable hw cyclic mode to avoid unnecessary interrupts.</div><div class='ctx'> 	 */</div><div class='del'>-	if (chan-&gt;hw_cyclic &amp;&amp; desc-&gt;cyclic &amp;&amp; !desc-&gt;vdesc.tx.callback &amp;&amp;</div><div class='del'>-		desc-&gt;num_sgs == 1)</div><div class='del'>-		flags |= AXI_DMAC_FLAG_CYCLIC;</div><div class='add'>+	if (chan-&gt;hw_cyclic &amp;&amp; desc-&gt;cyclic &amp;&amp; !desc-&gt;vdesc.tx.callback) {</div><div class='add'>+		if (chan-&gt;hw_sg)</div><div class='add'>+			desc-&gt;sg[desc-&gt;num_sgs - 1].hw-&gt;flags &amp;= ~AXI_DMAC_HW_FLAG_IRQ;</div><div class='add'>+		else if (desc-&gt;num_sgs == 1)</div><div class='add'>+			flags |= AXI_DMAC_FLAG_CYCLIC;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (chan-&gt;hw_partial_xfer)</div><div class='ctx'> 		flags |= AXI_DMAC_FLAG_PARTIAL_REPORT;</div><div class='ctx'> </div><div class='del'>-	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg-&gt;x_len - 1);</div><div class='del'>-	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg-&gt;y_len - 1);</div><div class='add'>+	if (chan-&gt;hw_sg) {</div><div class='add'>+		axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS, (u32)sg-&gt;hw_phys);</div><div class='add'>+		axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS_HIGH,</div><div class='add'>+			       (u64)sg-&gt;hw_phys &gt;&gt; 32);</div><div class='add'>+	} else {</div><div class='add'>+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg-&gt;hw-&gt;x_len);</div><div class='add'>+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg-&gt;hw-&gt;y_len);</div><div class='add'>+	}</div><div class='ctx'> 	axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);</div><div class='ctx'> 	axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);</div><div class='ctx'> }</div><div class='hunk'>@@ -286,9 +319,9 @@ static inline unsigned int axi_dmac_total_sg_bytes(struct axi_dmac_chan *chan,</div><div class='ctx'> 	struct axi_dmac_sg *sg)</div><div class='ctx'> {</div><div class='ctx'> 	if (chan-&gt;hw_2d)</div><div class='del'>-		return sg-&gt;x_len * sg-&gt;y_len;</div><div class='add'>+		return (sg-&gt;hw-&gt;x_len + 1) * (sg-&gt;hw-&gt;y_len + 1);</div><div class='ctx'> 	else</div><div class='del'>-		return sg-&gt;x_len;</div><div class='add'>+		return (sg-&gt;hw-&gt;x_len + 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void axi_dmac_dequeue_partial_xfers(struct axi_dmac_chan *chan)</div><div class='hunk'>@@ -307,9 +340,9 @@ static void axi_dmac_dequeue_partial_xfers(struct axi_dmac_chan *chan)</div><div class='ctx'> 		list_for_each_entry(desc, &amp;chan-&gt;active_descs, vdesc.node) {</div><div class='ctx'> 			for (i = 0; i &lt; desc-&gt;num_sgs; i++) {</div><div class='ctx'> 				sg = &amp;desc-&gt;sg[i];</div><div class='del'>-				if (sg-&gt;id == AXI_DMAC_SG_UNUSED)</div><div class='add'>+				if (sg-&gt;hw-&gt;id == AXI_DMAC_SG_UNUSED)</div><div class='ctx'> 					continue;</div><div class='del'>-				if (sg-&gt;id == id) {</div><div class='add'>+				if (sg-&gt;hw-&gt;id == id) {</div><div class='ctx'> 					desc-&gt;have_partial_xfer = true;</div><div class='ctx'> 					sg-&gt;partial_len = len;</div><div class='ctx'> 					found_sg = true;</div><div class='hunk'>@@ -348,6 +381,9 @@ static void axi_dmac_compute_residue(struct axi_dmac_chan *chan,</div><div class='ctx'> 	rslt-&gt;result = DMA_TRANS_NOERROR;</div><div class='ctx'> 	rslt-&gt;residue = 0;</div><div class='ctx'> </div><div class='add'>+	if (chan-&gt;hw_sg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We get here if the last completed segment is partial, which</div><div class='ctx'> 	 * means we can compute the residue from that segment onwards</div><div class='hunk'>@@ -374,36 +410,47 @@ static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan,</div><div class='ctx'> 	    (completed_transfers &amp; AXI_DMAC_FLAG_PARTIAL_XFER_DONE))</div><div class='ctx'> 		axi_dmac_dequeue_partial_xfers(chan);</div><div class='ctx'> </div><div class='del'>-	do {</div><div class='del'>-		sg = &amp;active-&gt;sg[active-&gt;num_completed];</div><div class='del'>-		if (sg-&gt;id == AXI_DMAC_SG_UNUSED) /* Not yet submitted */</div><div class='del'>-			break;</div><div class='del'>-		if (!(BIT(sg-&gt;id) &amp; completed_transfers))</div><div class='del'>-			break;</div><div class='del'>-		active-&gt;num_completed++;</div><div class='del'>-		sg-&gt;id = AXI_DMAC_SG_UNUSED;</div><div class='del'>-		if (sg-&gt;schedule_when_free) {</div><div class='del'>-			sg-&gt;schedule_when_free = false;</div><div class='del'>-			start_next = true;</div><div class='add'>+	if (chan-&gt;hw_sg) {</div><div class='add'>+		if (active-&gt;cyclic) {</div><div class='add'>+			vchan_cyclic_callback(&amp;active-&gt;vdesc);</div><div class='add'>+		} else {</div><div class='add'>+			list_del(&amp;active-&gt;vdesc.node);</div><div class='add'>+			vchan_cookie_complete(&amp;active-&gt;vdesc);</div><div class='add'>+			active = axi_dmac_active_desc(chan);</div><div class='add'>+			start_next = !!active;</div><div class='ctx'> 		}</div><div class='add'>+	} else {</div><div class='add'>+		do {</div><div class='add'>+			sg = &amp;active-&gt;sg[active-&gt;num_completed];</div><div class='add'>+			if (sg-&gt;hw-&gt;id == AXI_DMAC_SG_UNUSED) /* Not yet submitted */</div><div class='add'>+				break;</div><div class='add'>+			if (!(BIT(sg-&gt;hw-&gt;id) &amp; completed_transfers))</div><div class='add'>+				break;</div><div class='add'>+			active-&gt;num_completed++;</div><div class='add'>+			sg-&gt;hw-&gt;id = AXI_DMAC_SG_UNUSED;</div><div class='add'>+			if (sg-&gt;schedule_when_free) {</div><div class='add'>+				sg-&gt;schedule_when_free = false;</div><div class='add'>+				start_next = true;</div><div class='add'>+			}</div><div class='ctx'> </div><div class='del'>-		if (sg-&gt;partial_len)</div><div class='del'>-			axi_dmac_compute_residue(chan, active);</div><div class='add'>+			if (sg-&gt;partial_len)</div><div class='add'>+				axi_dmac_compute_residue(chan, active);</div><div class='ctx'> </div><div class='del'>-		if (active-&gt;cyclic)</div><div class='del'>-			vchan_cyclic_callback(&amp;active-&gt;vdesc);</div><div class='add'>+			if (active-&gt;cyclic)</div><div class='add'>+				vchan_cyclic_callback(&amp;active-&gt;vdesc);</div><div class='ctx'> </div><div class='del'>-		if (active-&gt;num_completed == active-&gt;num_sgs ||</div><div class='del'>-		    sg-&gt;partial_len) {</div><div class='del'>-			if (active-&gt;cyclic) {</div><div class='del'>-				active-&gt;num_completed = 0; /* wrap around */</div><div class='del'>-			} else {</div><div class='del'>-				list_del(&amp;active-&gt;vdesc.node);</div><div class='del'>-				vchan_cookie_complete(&amp;active-&gt;vdesc);</div><div class='del'>-				active = axi_dmac_active_desc(chan);</div><div class='add'>+			if (active-&gt;num_completed == active-&gt;num_sgs ||</div><div class='add'>+			    sg-&gt;partial_len) {</div><div class='add'>+				if (active-&gt;cyclic) {</div><div class='add'>+					active-&gt;num_completed = 0; /* wrap around */</div><div class='add'>+				} else {</div><div class='add'>+					list_del(&amp;active-&gt;vdesc.node);</div><div class='add'>+					vchan_cookie_complete(&amp;active-&gt;vdesc);</div><div class='add'>+					active = axi_dmac_active_desc(chan);</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='del'>-		}</div><div class='del'>-	} while (active);</div><div class='add'>+		} while (active);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return start_next;</div><div class='ctx'> }</div><div class='hunk'>@@ -467,8 +514,12 @@ static void axi_dmac_issue_pending(struct dma_chan *c)</div><div class='ctx'> 	struct axi_dmac_chan *chan = to_axi_dmac_chan(c);</div><div class='ctx'> 	struct axi_dmac *dmac = chan_to_axi_dmac(chan);</div><div class='ctx'> 	unsigned long flags;</div><div class='add'>+	u32 ctrl = AXI_DMAC_CTRL_ENABLE;</div><div class='ctx'> </div><div class='del'>-	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);</div><div class='add'>+	if (chan-&gt;hw_sg)</div><div class='add'>+		ctrl |= AXI_DMAC_CTRL_ENABLE_SG;</div><div class='add'>+</div><div class='add'>+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, ctrl);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;chan-&gt;vchan.lock, flags);</div><div class='ctx'> 	if (vchan_issue_pending(&amp;chan-&gt;vchan))</div><div class='hunk'>@@ -476,22 +527,58 @@ static void axi_dmac_issue_pending(struct dma_chan *c)</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;chan-&gt;vchan.lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)</div><div class='add'>+static struct axi_dmac_desc *</div><div class='add'>+axi_dmac_alloc_desc(struct axi_dmac_chan *chan, unsigned int num_sgs)</div><div class='ctx'> {</div><div class='add'>+	struct axi_dmac *dmac = chan_to_axi_dmac(chan);</div><div class='add'>+	struct device *dev = dmac-&gt;dma_dev.dev;</div><div class='add'>+	struct axi_dmac_hw_desc *hws;</div><div class='ctx'> 	struct axi_dmac_desc *desc;</div><div class='add'>+	dma_addr_t hw_phys;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	desc = kzalloc(struct_size(desc, sg, num_sgs), GFP_NOWAIT);</div><div class='ctx'> 	if (!desc)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	desc-&gt;num_sgs = num_sgs;</div><div class='add'>+	desc-&gt;chan = chan;</div><div class='add'>+</div><div class='add'>+	hws = dma_alloc_coherent(dev, PAGE_ALIGN(num_sgs * sizeof(*hws)),</div><div class='add'>+				&amp;hw_phys, GFP_ATOMIC);</div><div class='add'>+	if (!hws) {</div><div class='add'>+		kfree(desc);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; num_sgs; i++)</div><div class='del'>-		desc-&gt;sg[i].id = AXI_DMAC_SG_UNUSED;</div><div class='add'>+	for (i = 0; i &lt; num_sgs; i++) {</div><div class='add'>+		desc-&gt;sg[i].hw = &amp;hws[i];</div><div class='add'>+		desc-&gt;sg[i].hw_phys = hw_phys + i * sizeof(*hws);</div><div class='add'>+</div><div class='add'>+		hws[i].id = AXI_DMAC_SG_UNUSED;</div><div class='add'>+		hws[i].flags = 0;</div><div class='add'>+</div><div class='add'>+		/* Link hardware descriptors */</div><div class='add'>+		hws[i].next_sg_addr = hw_phys + (i + 1) * sizeof(*hws);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* The last hardware descriptor will trigger an interrupt */</div><div class='add'>+	desc-&gt;sg[num_sgs - 1].hw-&gt;flags = AXI_DMAC_HW_FLAG_LAST | AXI_DMAC_HW_FLAG_IRQ;</div><div class='ctx'> </div><div class='ctx'> 	return desc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void axi_dmac_free_desc(struct axi_dmac_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct axi_dmac *dmac = chan_to_axi_dmac(desc-&gt;chan);</div><div class='add'>+	struct device *dev = dmac-&gt;dma_dev.dev;</div><div class='add'>+	struct axi_dmac_hw_desc *hw = desc-&gt;sg[0].hw;</div><div class='add'>+	dma_addr_t hw_phys = desc-&gt;sg[0].hw_phys;</div><div class='add'>+</div><div class='add'>+	dma_free_coherent(dev, PAGE_ALIGN(desc-&gt;num_sgs * sizeof(*hw)),</div><div class='add'>+			  hw, hw_phys);</div><div class='add'>+	kfree(desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan,</div><div class='ctx'> 	enum dma_transfer_direction direction, dma_addr_t addr,</div><div class='ctx'> 	unsigned int num_periods, unsigned int period_len,</div><div class='hunk'>@@ -508,26 +595,24 @@ static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan,</div><div class='ctx'> 	segment_size = ((segment_size - 1) | chan-&gt;length_align_mask) + 1;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_periods; i++) {</div><div class='del'>-		len = period_len;</div><div class='del'>-</div><div class='del'>-		while (len &gt; segment_size) {</div><div class='add'>+		for (len = period_len; len &gt; segment_size; sg++) {</div><div class='ctx'> 			if (direction == DMA_DEV_TO_MEM)</div><div class='del'>-				sg-&gt;dest_addr = addr;</div><div class='add'>+				sg-&gt;hw-&gt;dest_addr = addr;</div><div class='ctx'> 			else</div><div class='del'>-				sg-&gt;src_addr = addr;</div><div class='del'>-			sg-&gt;x_len = segment_size;</div><div class='del'>-			sg-&gt;y_len = 1;</div><div class='del'>-			sg++;</div><div class='add'>+				sg-&gt;hw-&gt;src_addr = addr;</div><div class='add'>+			sg-&gt;hw-&gt;x_len = segment_size - 1;</div><div class='add'>+			sg-&gt;hw-&gt;y_len = 0;</div><div class='add'>+			sg-&gt;hw-&gt;flags = 0;</div><div class='ctx'> 			addr += segment_size;</div><div class='ctx'> 			len -= segment_size;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (direction == DMA_DEV_TO_MEM)</div><div class='del'>-			sg-&gt;dest_addr = addr;</div><div class='add'>+			sg-&gt;hw-&gt;dest_addr = addr;</div><div class='ctx'> 		else</div><div class='del'>-			sg-&gt;src_addr = addr;</div><div class='del'>-		sg-&gt;x_len = len;</div><div class='del'>-		sg-&gt;y_len = 1;</div><div class='add'>+			sg-&gt;hw-&gt;src_addr = addr;</div><div class='add'>+		sg-&gt;hw-&gt;x_len = len - 1;</div><div class='add'>+		sg-&gt;hw-&gt;y_len = 0;</div><div class='ctx'> 		sg++;</div><div class='ctx'> 		addr += len;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -554,7 +639,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(</div><div class='ctx'> 	for_each_sg(sgl, sg, sg_len, i)</div><div class='ctx'> 		num_sgs += DIV_ROUND_UP(sg_dma_len(sg), chan-&gt;max_length);</div><div class='ctx'> </div><div class='del'>-	desc = axi_dmac_alloc_desc(num_sgs);</div><div class='add'>+	desc = axi_dmac_alloc_desc(chan, num_sgs);</div><div class='ctx'> 	if (!desc)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -563,7 +648,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(</div><div class='ctx'> 	for_each_sg(sgl, sg, sg_len, i) {</div><div class='ctx'> 		if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) ||</div><div class='ctx'> 		    !axi_dmac_check_len(chan, sg_dma_len(sg))) {</div><div class='del'>-			kfree(desc);</div><div class='add'>+			axi_dmac_free_desc(desc);</div><div class='ctx'> 			return NULL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -583,7 +668,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic(</div><div class='ctx'> {</div><div class='ctx'> 	struct axi_dmac_chan *chan = to_axi_dmac_chan(c);</div><div class='ctx'> 	struct axi_dmac_desc *desc;</div><div class='del'>-	unsigned int num_periods, num_segments;</div><div class='add'>+	unsigned int num_periods, num_segments, num_sgs;</div><div class='ctx'> </div><div class='ctx'> 	if (direction != chan-&gt;direction)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -597,11 +682,16 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic(</div><div class='ctx'> </div><div class='ctx'> 	num_periods = buf_len / period_len;</div><div class='ctx'> 	num_segments = DIV_ROUND_UP(period_len, chan-&gt;max_length);</div><div class='add'>+	num_sgs = num_periods * num_segments;</div><div class='ctx'> </div><div class='del'>-	desc = axi_dmac_alloc_desc(num_periods * num_segments);</div><div class='add'>+	desc = axi_dmac_alloc_desc(chan, num_sgs);</div><div class='ctx'> 	if (!desc)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	/* Chain the last descriptor to the first, and remove its "last" flag */</div><div class='add'>+	desc-&gt;sg[num_sgs - 1].hw-&gt;next_sg_addr = desc-&gt;sg[0].hw_phys;</div><div class='add'>+	desc-&gt;sg[num_sgs - 1].hw-&gt;flags &amp;= ~AXI_DMAC_HW_FLAG_LAST;</div><div class='add'>+</div><div class='ctx'> 	axi_dmac_fill_linear_sg(chan, direction, buf_addr, num_periods,</div><div class='ctx'> 		period_len, desc-&gt;sg);</div><div class='ctx'> </div><div class='hunk'>@@ -653,26 +743,26 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(</div><div class='ctx'> 			return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	desc = axi_dmac_alloc_desc(1);</div><div class='add'>+	desc = axi_dmac_alloc_desc(chan, 1);</div><div class='ctx'> 	if (!desc)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (axi_dmac_src_is_mem(chan)) {</div><div class='del'>-		desc-&gt;sg[0].src_addr = xt-&gt;src_start;</div><div class='del'>-		desc-&gt;sg[0].src_stride = xt-&gt;sgl[0].size + src_icg;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;src_addr = xt-&gt;src_start;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;src_stride = xt-&gt;sgl[0].size + src_icg;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (axi_dmac_dest_is_mem(chan)) {</div><div class='del'>-		desc-&gt;sg[0].dest_addr = xt-&gt;dst_start;</div><div class='del'>-		desc-&gt;sg[0].dest_stride = xt-&gt;sgl[0].size + dst_icg;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;dest_addr = xt-&gt;dst_start;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;dst_stride = xt-&gt;sgl[0].size + dst_icg;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (chan-&gt;hw_2d) {</div><div class='del'>-		desc-&gt;sg[0].x_len = xt-&gt;sgl[0].size;</div><div class='del'>-		desc-&gt;sg[0].y_len = xt-&gt;numf;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;x_len = xt-&gt;sgl[0].size - 1;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;y_len = xt-&gt;numf - 1;</div><div class='ctx'> 	} else {</div><div class='del'>-		desc-&gt;sg[0].x_len = xt-&gt;sgl[0].size * xt-&gt;numf;</div><div class='del'>-		desc-&gt;sg[0].y_len = 1;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;x_len = xt-&gt;sgl[0].size * xt-&gt;numf - 1;</div><div class='add'>+		desc-&gt;sg[0].hw-&gt;y_len = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; DMA_CYCLIC)</div><div class='hunk'>@@ -688,7 +778,7 @@ static void axi_dmac_free_chan_resources(struct dma_chan *c)</div><div class='ctx'> </div><div class='ctx'> static void axi_dmac_desc_free(struct virt_dma_desc *vdesc)</div><div class='ctx'> {</div><div class='del'>-	kfree(container_of(vdesc, struct axi_dmac_desc, vdesc));</div><div class='add'>+	axi_dmac_free_desc(to_axi_dmac_desc(vdesc));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg)</div><div class='hunk'>@@ -714,6 +804,9 @@ static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg)</div><div class='ctx'> 	case AXI_DMAC_REG_CURRENT_DEST_ADDR:</div><div class='ctx'> 	case AXI_DMAC_REG_PARTIAL_XFER_LEN:</div><div class='ctx'> 	case AXI_DMAC_REG_PARTIAL_XFER_ID:</div><div class='add'>+	case AXI_DMAC_REG_CURRENT_SG_ID:</div><div class='add'>+	case AXI_DMAC_REG_SG_ADDRESS:</div><div class='add'>+	case AXI_DMAC_REG_SG_ADDRESS_HIGH:</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -866,6 +959,10 @@ static int axi_dmac_detect_caps(struct axi_dmac *dmac, unsigned int version)</div><div class='ctx'> 	if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)</div><div class='ctx'> 		chan-&gt;hw_cyclic = true;</div><div class='ctx'> </div><div class='add'>+	axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS, 0xffffffff);</div><div class='add'>+	if (axi_dmac_read(dmac, AXI_DMAC_REG_SG_ADDRESS))</div><div class='add'>+		chan-&gt;hw_sg = true;</div><div class='add'>+</div><div class='ctx'> 	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 1);</div><div class='ctx'> 	if (axi_dmac_read(dmac, AXI_DMAC_REG_Y_LENGTH) == 1)</div><div class='ctx'> 		chan-&gt;hw_2d = true;</div><div class='hunk'>@@ -911,6 +1008,7 @@ static int axi_dmac_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct axi_dmac *dmac;</div><div class='ctx'> 	struct regmap *regmap;</div><div class='ctx'> 	unsigned int version;</div><div class='add'>+	u32 irq_mask = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	dmac = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*dmac), GFP_KERNEL);</div><div class='hunk'>@@ -966,6 +1064,7 @@ static int axi_dmac_probe(struct platform_device *pdev)</div><div class='ctx'> 	dma_dev-&gt;dst_addr_widths = BIT(dmac-&gt;chan.dest_width);</div><div class='ctx'> 	dma_dev-&gt;directions = BIT(dmac-&gt;chan.direction);</div><div class='ctx'> 	dma_dev-&gt;residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;</div><div class='add'>+	dma_dev-&gt;max_sg_burst = 31; /* 31 SGs maximum in one burst */</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;dma_dev-&gt;channels);</div><div class='ctx'> </div><div class='ctx'> 	dmac-&gt;chan.vchan.desc_free = axi_dmac_desc_free;</div><div class='hunk'>@@ -977,7 +1076,10 @@ static int axi_dmac_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dma_dev-&gt;copy_align = (dmac-&gt;chan.address_align_mask + 1);</div><div class='ctx'> </div><div class='del'>-	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);</div><div class='add'>+	if (dmac-&gt;chan.hw_sg)</div><div class='add'>+		irq_mask |= AXI_DMAC_IRQ_SOT;</div><div class='add'>+</div><div class='add'>+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, irq_mask);</div><div class='ctx'> </div><div class='ctx'> 	if (of_dma_is_coherent(pdev-&gt;dev.of_node)) {</div><div class='ctx'> 		ret = axi_dmac_read(dmac, AXI_DMAC_REG_COHERENCY_DESC);</div><div class='head'>diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c<br/>index b7388ae62d7f..491b22240221 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/dmaengine.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/dmaengine.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/dmaengine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dmaengine.c</a></div><div class='hunk'>@@ -1103,6 +1103,9 @@ EXPORT_SYMBOL_GPL(dma_async_device_channel_register);</div><div class='ctx'> static void __dma_async_device_channel_unregister(struct dma_device *device,</div><div class='ctx'> 						  struct dma_chan *chan)</div><div class='ctx'> {</div><div class='add'>+	if (chan-&gt;local == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	WARN_ONCE(!device-&gt;device_release &amp;&amp; chan-&gt;client_count,</div><div class='ctx'> 		  "%s called while %d clients hold a reference\n",</div><div class='ctx'> 		  __func__, chan-&gt;client_count);</div><div class='head'>diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c<br/>index ffe621695e47..a4f608837849 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/dmatest.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/dmatest.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/dmatest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dmatest.c</a></div><div class='hunk'>@@ -21,6 +21,10 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/wait.h&gt;</div><div class='ctx'> </div><div class='add'>+static bool nobounce;</div><div class='add'>+module_param(nobounce, bool, 0644);</div><div class='add'>+MODULE_PARM_DESC(nobounce, "Prevent using swiotlb buffer (default: use swiotlb buffer)");</div><div class='add'>+</div><div class='ctx'> static unsigned int test_buf_size = 16384;</div><div class='ctx'> module_param(test_buf_size, uint, 0644);</div><div class='ctx'> MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");</div><div class='hunk'>@@ -90,6 +94,7 @@ MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct dmatest_params - test parameters.</div><div class='add'>+ * @nobounce:		prevent using swiotlb buffer</div><div class='ctx'>  * @buf_size:		size of the memcpy test buffer</div><div class='ctx'>  * @channel:		bus ID of the channel to test</div><div class='ctx'>  * @device:		bus ID of the DMA Engine to test</div><div class='hunk'>@@ -106,6 +111,7 @@ MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");</div><div class='ctx'>  * @polled:		use polling for completion instead of interrupts</div><div class='ctx'>  */</div><div class='ctx'> struct dmatest_params {</div><div class='add'>+	bool		nobounce;</div><div class='ctx'> 	unsigned int	buf_size;</div><div class='ctx'> 	char		channel[20];</div><div class='ctx'> 	char		device[32];</div><div class='hunk'>@@ -215,6 +221,7 @@ struct dmatest_done {</div><div class='ctx'> struct dmatest_data {</div><div class='ctx'> 	u8		**raw;</div><div class='ctx'> 	u8		**aligned;</div><div class='add'>+	gfp_t		gfp_flags;</div><div class='ctx'> 	unsigned int	cnt;</div><div class='ctx'> 	unsigned int	off;</div><div class='ctx'> };</div><div class='hunk'>@@ -533,7 +540,7 @@ static int dmatest_alloc_test_data(struct dmatest_data *d,</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; d-&gt;cnt; i++) {</div><div class='del'>-		d-&gt;raw[i] = kmalloc(buf_size + align, GFP_KERNEL);</div><div class='add'>+		d-&gt;raw[i] = kmalloc(buf_size + align, d-&gt;gfp_flags);</div><div class='ctx'> 		if (!d-&gt;raw[i])</div><div class='ctx'> 			goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -655,6 +662,13 @@ static int dmatest_func(void *data)</div><div class='ctx'> 		goto err_free_coefs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	src-&gt;gfp_flags = GFP_KERNEL;</div><div class='add'>+	dst-&gt;gfp_flags = GFP_KERNEL;</div><div class='add'>+	if (params-&gt;nobounce) {</div><div class='add'>+		src-&gt;gfp_flags = GFP_DMA;</div><div class='add'>+		dst-&gt;gfp_flags = GFP_DMA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dmatest_alloc_test_data(src, buf_size, align) &lt; 0)</div><div class='ctx'> 		goto err_free_coefs;</div><div class='ctx'> </div><div class='hunk'>@@ -1093,6 +1107,7 @@ static void add_threaded_test(struct dmatest_info *info)</div><div class='ctx'> 	struct dmatest_params *params = &amp;info-&gt;params;</div><div class='ctx'> </div><div class='ctx'> 	/* Copy test parameters */</div><div class='add'>+	params-&gt;nobounce = nobounce;</div><div class='ctx'> 	params-&gt;buf_size = test_buf_size;</div><div class='ctx'> 	strscpy(params-&gt;channel, strim(test_channel), sizeof(params-&gt;channel));</div><div class='ctx'> 	strscpy(params-&gt;device, strim(test_device), sizeof(params-&gt;device));</div><div class='head'>diff --git a/drivers/dma/dw-edma/dw-edma-v0-debugfs.c b/drivers/dma/dw-edma/dw-edma-v0-debugfs.c<br/>index 0745d9e7d259..406f169b09a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/dw-edma/dw-edma-v0-debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/dw-edma/dw-edma-v0-debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/dw-edma/dw-edma-v0-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dw-edma/dw-edma-v0-debugfs.c</a></div><div class='hunk'>@@ -176,7 +176,7 @@ dw_edma_debugfs_regs_wr(struct dw_edma *dw, struct dentry *dent)</div><div class='ctx'> 	};</div><div class='ctx'> 	struct dentry *regs_dent, *ch_dent;</div><div class='ctx'> 	int nr_entries, i;</div><div class='del'>-	char name[16];</div><div class='add'>+	char name[32];</div><div class='ctx'> </div><div class='ctx'> 	regs_dent = debugfs_create_dir(WRITE_STR, dent);</div><div class='ctx'> </div><div class='hunk'>@@ -239,7 +239,7 @@ static noinline_for_stack void dw_edma_debugfs_regs_rd(struct dw_edma *dw,</div><div class='ctx'> 	};</div><div class='ctx'> 	struct dentry *regs_dent, *ch_dent;</div><div class='ctx'> 	int nr_entries, i;</div><div class='del'>-	char name[16];</div><div class='add'>+	char name[32];</div><div class='ctx'> </div><div class='ctx'> 	regs_dent = debugfs_create_dir(READ_STR, dent);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c<br/>index 520c81978b08..dcdc57fe976c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/dw-edma/dw-hdma-v0-debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/dw-edma/dw-hdma-v0-debugfs.c</a></div><div class='hunk'>@@ -116,7 +116,7 @@ static void dw_hdma_debugfs_regs_ch(struct dw_edma *dw, enum dw_edma_dir dir,</div><div class='ctx'> static void dw_hdma_debugfs_regs_wr(struct dw_edma *dw, struct dentry *dent)</div><div class='ctx'> {</div><div class='ctx'> 	struct dentry *regs_dent, *ch_dent;</div><div class='del'>-	char name[16];</div><div class='add'>+	char name[32];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	regs_dent = debugfs_create_dir(WRITE_STR, dent);</div><div class='hunk'>@@ -133,7 +133,7 @@ static void dw_hdma_debugfs_regs_wr(struct dw_edma *dw, struct dentry *dent)</div><div class='ctx'> static void dw_hdma_debugfs_regs_rd(struct dw_edma *dw, struct dentry *dent)</div><div class='ctx'> {</div><div class='ctx'> 	struct dentry *regs_dent, *ch_dent;</div><div class='del'>-	char name[16];</div><div class='add'>+	char name[32];</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	regs_dent = debugfs_create_dir(READ_STR, dent);</div><div class='head'>diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c<br/>index 6a3abe5b1790..b53f46245c37 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/fsl-edma-common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/fsl-edma-common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/fsl-edma-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-edma-common.c</a></div><div class='hunk'>@@ -828,6 +828,7 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)</div><div class='ctx'> 	dma_pool_destroy(fsl_chan-&gt;tcd_pool);</div><div class='ctx'> 	fsl_chan-&gt;tcd_pool = NULL;</div><div class='ctx'> 	fsl_chan-&gt;is_sw = false;</div><div class='add'>+	fsl_chan-&gt;srcid = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void fsl_edma_cleanup_vchan(struct dma_device *dmadev)</div><div class='head'>diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c<br/>index 4635e16d7705..45cc419b1b4a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/fsl-edma-main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/fsl-edma-main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/fsl-edma-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-edma-main.c</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'>  * Vybrid and Layerscape SoCs.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;dt-bindings/dma/fsl-edma.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='hunk'>@@ -21,10 +22,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "fsl-edma-common.h"</div><div class='ctx'> </div><div class='del'>-#define ARGS_RX                         BIT(0)</div><div class='del'>-#define ARGS_REMOTE                     BIT(1)</div><div class='del'>-#define ARGS_MULTI_FIFO                 BIT(2)</div><div class='del'>-</div><div class='ctx'> static void fsl_edma_synchronize(struct dma_chan *chan)</div><div class='ctx'> {</div><div class='ctx'> 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);</div><div class='hunk'>@@ -153,9 +150,15 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,</div><div class='ctx'> 		i = fsl_chan - fsl_edma-&gt;chans;</div><div class='ctx'> </div><div class='ctx'> 		fsl_chan-&gt;priority = dma_spec-&gt;args[1];</div><div class='del'>-		fsl_chan-&gt;is_rxchan = dma_spec-&gt;args[2] &amp; ARGS_RX;</div><div class='del'>-		fsl_chan-&gt;is_remote = dma_spec-&gt;args[2] &amp; ARGS_REMOTE;</div><div class='del'>-		fsl_chan-&gt;is_multi_fifo = dma_spec-&gt;args[2] &amp; ARGS_MULTI_FIFO;</div><div class='add'>+		fsl_chan-&gt;is_rxchan = dma_spec-&gt;args[2] &amp; FSL_EDMA_RX;</div><div class='add'>+		fsl_chan-&gt;is_remote = dma_spec-&gt;args[2] &amp; FSL_EDMA_REMOTE;</div><div class='add'>+		fsl_chan-&gt;is_multi_fifo = dma_spec-&gt;args[2] &amp; FSL_EDMA_MULTI_FIFO;</div><div class='add'>+</div><div class='add'>+		if ((dma_spec-&gt;args[2] &amp; FSL_EDMA_EVEN_CH) &amp;&amp; (i &amp; 0x1))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if ((dma_spec-&gt;args[2] &amp; FSL_EDMA_ODD_CH) &amp;&amp; !(i &amp; 0x1))</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (!b_chmux &amp;&amp; i == dma_spec-&gt;args[0]) {</div><div class='ctx'> 			chan = dma_get_slave_channel(chan);</div><div class='hunk'>@@ -396,9 +399,8 @@ static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_eng</div><div class='ctx'> 		link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |</div><div class='ctx'> 					     DL_FLAG_PM_RUNTIME |</div><div class='ctx'> 					     DL_FLAG_RPM_ACTIVE);</div><div class='del'>-		if (IS_ERR(link)) {</div><div class='del'>-			dev_err(dev, "Failed to add device_link to %d: %ld\n", i,</div><div class='del'>-				PTR_ERR(link));</div><div class='add'>+		if (!link) {</div><div class='add'>+			dev_err(dev, "Failed to add device_link to %d\n", i);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -631,6 +633,8 @@ static int fsl_edma_suspend_late(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; fsl_edma-&gt;n_chans; i++) {</div><div class='ctx'> 		fsl_chan = &amp;fsl_edma-&gt;chans[i];</div><div class='add'>+		if (fsl_edma-&gt;chan_masked &amp; BIT(i))</div><div class='add'>+			continue;</div><div class='ctx'> 		spin_lock_irqsave(&amp;fsl_chan-&gt;vchan.lock, flags);</div><div class='ctx'> 		/* Make sure chan is idle or will force disable. */</div><div class='ctx'> 		if (unlikely(!fsl_chan-&gt;idle)) {</div><div class='hunk'>@@ -655,13 +659,16 @@ static int fsl_edma_resume_early(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; fsl_edma-&gt;n_chans; i++) {</div><div class='ctx'> 		fsl_chan = &amp;fsl_edma-&gt;chans[i];</div><div class='add'>+		if (fsl_edma-&gt;chan_masked &amp; BIT(i))</div><div class='add'>+			continue;</div><div class='ctx'> 		fsl_chan-&gt;pm_state = RUNNING;</div><div class='ctx'> 		edma_write_tcdreg(fsl_chan, 0, csr);</div><div class='ctx'> 		if (fsl_chan-&gt;slave_id != 0)</div><div class='ctx'> 			fsl_edma_chan_mux(fsl_chan, fsl_chan-&gt;slave_id, true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs-&gt;cr);</div><div class='add'>+	if (!(fsl_edma-&gt;drvdata-&gt;flags &amp; FSL_EDMA_DRV_SPLIT_REG))</div><div class='add'>+		edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs-&gt;cr);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c<br/>index 47cb28468049..a1d0aa63142a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/fsl-qdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/fsl-qdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/fsl-qdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/fsl-qdma.c</a></div><div class='hunk'>@@ -805,7 +805,7 @@ fsl_qdma_irq_init(struct platform_device *pdev,</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int cpu;</div><div class='ctx'> 	int ret;</div><div class='del'>-	char irq_name[20];</div><div class='add'>+	char irq_name[32];</div><div class='ctx'> </div><div class='ctx'> 	fsl_qdma-&gt;error_irq =</div><div class='ctx'> 		platform_get_irq_byname(pdev, "qdma-error");</div><div class='head'>diff --git a/drivers/dma/idxd/Makefile b/drivers/dma/idxd/Makefile<br/>index c5e679070e46..2b4a0d406e1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/Makefile</a></div><div class='hunk'>@@ -4,7 +4,7 @@ obj-$(CONFIG_INTEL_IDXD_BUS) += idxd_bus.o</div><div class='ctx'> idxd_bus-y := bus.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_INTEL_IDXD) += idxd.o</div><div class='del'>-idxd-y := init.o irq.o device.o sysfs.o submit.o dma.o cdev.o debugfs.o</div><div class='add'>+idxd-y := init.o irq.o device.o sysfs.o submit.o dma.o cdev.o debugfs.o defaults.o</div><div class='ctx'> </div><div class='ctx'> idxd-$(CONFIG_INTEL_IDXD_PERFMON) += perfmon.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/idxd/bus.c b/drivers/dma/idxd/bus.c<br/>index 6f84621053c6..0c9e689a2e77 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/bus.c</a></div><div class='hunk'>@@ -67,11 +67,17 @@ static void idxd_config_bus_remove(struct device *dev)</div><div class='ctx'> 	idxd_drv-&gt;remove(idxd_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int idxd_bus_uevent(const struct device *dev, struct kobj_uevent_env *env)</div><div class='add'>+{</div><div class='add'>+	return add_uevent_var(env, "MODALIAS=" IDXD_DEVICES_MODALIAS_FMT, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct bus_type dsa_bus_type = {</div><div class='ctx'> 	.name = "dsa",</div><div class='ctx'> 	.match = idxd_config_bus_match,</div><div class='ctx'> 	.probe = idxd_config_bus_probe,</div><div class='ctx'> 	.remove = idxd_config_bus_remove,</div><div class='add'>+	.uevent = idxd_bus_uevent,</div><div class='ctx'> };</div><div class='ctx'> EXPORT_SYMBOL_GPL(dsa_bus_type);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/idxd/cdev.c b/drivers/dma/idxd/cdev.c<br/>index 0423655f5a88..77f8885cf407 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/cdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/cdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/cdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/cdev.c</a></div><div class='hunk'>@@ -165,7 +165,7 @@ static void idxd_cdev_dev_release(struct device *dev)</div><div class='ctx'> 	struct idxd_wq *wq = idxd_cdev-&gt;wq;</div><div class='ctx'> </div><div class='ctx'> 	cdev_ctx = &amp;ictx[wq-&gt;idxd-&gt;data-&gt;type];</div><div class='del'>-	ida_simple_remove(&amp;cdev_ctx-&gt;minor_ida, idxd_cdev-&gt;minor);</div><div class='add'>+	ida_free(&amp;cdev_ctx-&gt;minor_ida, idxd_cdev-&gt;minor);</div><div class='ctx'> 	kfree(idxd_cdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -463,7 +463,7 @@ int idxd_wq_add_cdev(struct idxd_wq *wq)</div><div class='ctx'> 	cdev = &amp;idxd_cdev-&gt;cdev;</div><div class='ctx'> 	dev = cdev_dev(idxd_cdev);</div><div class='ctx'> 	cdev_ctx = &amp;ictx[wq-&gt;idxd-&gt;data-&gt;type];</div><div class='del'>-	minor = ida_simple_get(&amp;cdev_ctx-&gt;minor_ida, 0, MINORMASK, GFP_KERNEL);</div><div class='add'>+	minor = ida_alloc_max(&amp;cdev_ctx-&gt;minor_ida, MINORMASK, GFP_KERNEL);</div><div class='ctx'> 	if (minor &lt; 0) {</div><div class='ctx'> 		kfree(idxd_cdev);</div><div class='ctx'> 		return minor;</div><div class='hunk'>@@ -550,7 +550,7 @@ static int idxd_user_drv_probe(struct idxd_dev *idxd_dev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_USER;</div><div class='del'>-	rc = drv_enable_wq(wq);</div><div class='add'>+	rc = idxd_drv_enable_wq(wq);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		goto err;</div><div class='ctx'> </div><div class='hunk'>@@ -565,7 +565,7 @@ static int idxd_user_drv_probe(struct idxd_dev *idxd_dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_cdev:</div><div class='del'>-	drv_disable_wq(wq);</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='ctx'> err:</div><div class='ctx'> 	destroy_workqueue(wq-&gt;wq);</div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_NONE;</div><div class='hunk'>@@ -580,7 +580,7 @@ static void idxd_user_drv_remove(struct idxd_dev *idxd_dev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;wq-&gt;wq_lock);</div><div class='ctx'> 	idxd_wq_del_cdev(wq);</div><div class='del'>-	drv_disable_wq(wq);</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_NONE;</div><div class='ctx'> 	destroy_workqueue(wq-&gt;wq);</div><div class='ctx'> 	wq-&gt;wq = NULL;</div><div class='head'>diff --git a/drivers/dma/idxd/defaults.c b/drivers/dma/idxd/defaults.c<br/>new file mode 100644<br/>index 000000000000..c607ae8dd12c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/defaults.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/defaults.c</a></div><div class='hunk'>@@ -0,0 +1,53 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright(c) 2023 Intel Corporation. All rights rsvd. */</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include "idxd.h"</div><div class='add'>+</div><div class='add'>+int idxd_load_iaa_device_defaults(struct idxd_device *idxd)</div><div class='add'>+{</div><div class='add'>+	struct idxd_engine *engine;</div><div class='add'>+	struct idxd_group *group;</div><div class='add'>+	struct idxd_wq *wq;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(IDXD_FLAG_CONFIGURABLE, &amp;idxd-&gt;flags))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	wq = idxd-&gt;wqs[0];</div><div class='add'>+</div><div class='add'>+	if (wq-&gt;state != IDXD_WQ_DISABLED)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	/* set mode to "dedicated" */</div><div class='add'>+	set_bit(WQ_FLAG_DEDICATED, &amp;wq-&gt;flags);</div><div class='add'>+	wq-&gt;threshold = 0;</div><div class='add'>+</div><div class='add'>+	/* only setting up 1 wq, so give it all the wq space */</div><div class='add'>+	wq-&gt;size = idxd-&gt;max_wq_size;</div><div class='add'>+</div><div class='add'>+	/* set priority to 10 */</div><div class='add'>+	wq-&gt;priority = 10;</div><div class='add'>+</div><div class='add'>+	/* set type to "kernel" */</div><div class='add'>+	wq-&gt;type = IDXD_WQT_KERNEL;</div><div class='add'>+</div><div class='add'>+	/* set wq group to 0 */</div><div class='add'>+	group = idxd-&gt;groups[0];</div><div class='add'>+	wq-&gt;group = group;</div><div class='add'>+	group-&gt;num_wqs++;</div><div class='add'>+</div><div class='add'>+	/* set name to "iaa_crypto" */</div><div class='add'>+	memset(wq-&gt;name, 0, WQ_NAME_SIZE + 1);</div><div class='add'>+	strscpy(wq-&gt;name, "iaa_crypto", WQ_NAME_SIZE + 1);</div><div class='add'>+</div><div class='add'>+	/* set driver_name to "crypto" */</div><div class='add'>+	memset(wq-&gt;driver_name, 0, DRIVER_NAME_SIZE + 1);</div><div class='add'>+	strscpy(wq-&gt;driver_name, "crypto", DRIVER_NAME_SIZE + 1);</div><div class='add'>+</div><div class='add'>+	engine = idxd-&gt;engines[0];</div><div class='add'>+</div><div class='add'>+	/* set engine group to 0 */</div><div class='add'>+	engine-&gt;group = idxd-&gt;groups[0];</div><div class='add'>+	engine-&gt;group-&gt;num_engines++;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/dma/idxd/device.c b/drivers/dma/idxd/device.c<br/>index 8f754f922217..ecfdf4a8f1f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/device.c</a></div><div class='hunk'>@@ -161,6 +161,7 @@ int idxd_wq_alloc_resources(struct idxd_wq *wq)</div><div class='ctx'> 	free_hw_descs(wq);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_wq_alloc_resources, IDXD);</div><div class='ctx'> </div><div class='ctx'> void idxd_wq_free_resources(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='hunk'>@@ -174,6 +175,7 @@ void idxd_wq_free_resources(struct idxd_wq *wq)</div><div class='ctx'> 	dma_free_coherent(dev, wq-&gt;compls_size, wq-&gt;compls, wq-&gt;compls_addr);</div><div class='ctx'> 	sbitmap_queue_free(&amp;wq-&gt;sbq);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_wq_free_resources, IDXD);</div><div class='ctx'> </div><div class='ctx'> int idxd_wq_enable(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='hunk'>@@ -405,6 +407,7 @@ int idxd_wq_init_percpu_ref(struct idxd_wq *wq)</div><div class='ctx'> 	reinit_completion(&amp;wq-&gt;wq_resurrect);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_wq_init_percpu_ref, IDXD);</div><div class='ctx'> </div><div class='ctx'> void __idxd_wq_quiesce(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='hunk'>@@ -414,6 +417,7 @@ void __idxd_wq_quiesce(struct idxd_wq *wq)</div><div class='ctx'> 	complete_all(&amp;wq-&gt;wq_resurrect);</div><div class='ctx'> 	wait_for_completion(&amp;wq-&gt;wq_dead);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(__idxd_wq_quiesce, IDXD);</div><div class='ctx'> </div><div class='ctx'> void idxd_wq_quiesce(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='hunk'>@@ -421,6 +425,7 @@ void idxd_wq_quiesce(struct idxd_wq *wq)</div><div class='ctx'> 	__idxd_wq_quiesce(wq);</div><div class='ctx'> 	mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_wq_quiesce, IDXD);</div><div class='ctx'> </div><div class='ctx'> /* Device control bits */</div><div class='ctx'> static inline bool idxd_is_enabled(struct idxd_device *idxd)</div><div class='hunk'>@@ -802,6 +807,9 @@ err_bmap:</div><div class='ctx'> </div><div class='ctx'> static void idxd_device_evl_free(struct idxd_device *idxd)</div><div class='ctx'> {</div><div class='add'>+	void *evl_log;</div><div class='add'>+	unsigned int evl_log_size;</div><div class='add'>+	dma_addr_t evl_dma;</div><div class='ctx'> 	union gencfg_reg gencfg;</div><div class='ctx'> 	union genctrl_reg genctrl;</div><div class='ctx'> 	struct device *dev = &amp;idxd-&gt;pdev-&gt;dev;</div><div class='hunk'>@@ -822,11 +830,15 @@ static void idxd_device_evl_free(struct idxd_device *idxd)</div><div class='ctx'> 	iowrite64(0, idxd-&gt;reg_base + IDXD_EVLCFG_OFFSET);</div><div class='ctx'> 	iowrite64(0, idxd-&gt;reg_base + IDXD_EVLCFG_OFFSET + 8);</div><div class='ctx'> </div><div class='del'>-	dma_free_coherent(dev, evl-&gt;log_size, evl-&gt;log, evl-&gt;dma);</div><div class='ctx'> 	bitmap_free(evl-&gt;bmap);</div><div class='add'>+	evl_log = evl-&gt;log;</div><div class='add'>+	evl_log_size = evl-&gt;log_size;</div><div class='add'>+	evl_dma = evl-&gt;dma;</div><div class='ctx'> 	evl-&gt;log = NULL;</div><div class='ctx'> 	evl-&gt;size = IDXD_EVL_SIZE_MIN;</div><div class='ctx'> 	spin_unlock(&amp;evl-&gt;lock);</div><div class='add'>+</div><div class='add'>+	dma_free_coherent(dev, evl_log_size, evl_log, evl_dma);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void idxd_group_config_write(struct idxd_group *group)</div><div class='hunk'>@@ -1266,7 +1278,7 @@ static void idxd_flush_pending_descs(struct idxd_irq_entry *ie)</div><div class='ctx'> 		tx = &amp;desc-&gt;txd;</div><div class='ctx'> 		tx-&gt;callback = NULL;</div><div class='ctx'> 		tx-&gt;callback_result = NULL;</div><div class='del'>-		idxd_dma_complete_txd(desc, ctype, true);</div><div class='add'>+		idxd_dma_complete_txd(desc, ctype, true, NULL, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1350,7 +1362,7 @@ err_irq:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int drv_enable_wq(struct idxd_wq *wq)</div><div class='add'>+int idxd_drv_enable_wq(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='ctx'> 	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='ctx'> 	struct device *dev = &amp;idxd-&gt;pdev-&gt;dev;</div><div class='hunk'>@@ -1482,8 +1494,9 @@ err_map_portal:</div><div class='ctx'> err:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_drv_enable_wq, IDXD);</div><div class='ctx'> </div><div class='del'>-void drv_disable_wq(struct idxd_wq *wq)</div><div class='add'>+void idxd_drv_disable_wq(struct idxd_wq *wq)</div><div class='ctx'> {</div><div class='ctx'> 	struct idxd_device *idxd = wq-&gt;idxd;</div><div class='ctx'> 	struct device *dev = &amp;idxd-&gt;pdev-&gt;dev;</div><div class='hunk'>@@ -1503,6 +1516,7 @@ void drv_disable_wq(struct idxd_wq *wq)</div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_NONE;</div><div class='ctx'> 	wq-&gt;client_count = 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_drv_disable_wq, IDXD);</div><div class='ctx'> </div><div class='ctx'> int idxd_device_drv_probe(struct idxd_dev *idxd_dev)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/dma/idxd/dma.c b/drivers/dma/idxd/dma.c<br/>index 47a01893cfdb..cd835eabd31b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/dma.c</a></div><div class='hunk'>@@ -22,7 +22,7 @@ static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c)</div><div class='ctx'> </div><div class='ctx'> void idxd_dma_complete_txd(struct idxd_desc *desc,</div><div class='ctx'> 			   enum idxd_complete_type comp_type,</div><div class='del'>-			   bool free_desc)</div><div class='add'>+			   bool free_desc, void *ctx, u32 *status)</div><div class='ctx'> {</div><div class='ctx'> 	struct idxd_device *idxd = desc-&gt;wq-&gt;idxd;</div><div class='ctx'> 	struct dma_async_tx_descriptor *tx;</div><div class='hunk'>@@ -314,7 +314,7 @@ static int idxd_dmaengine_drv_probe(struct idxd_dev *idxd_dev)</div><div class='ctx'> </div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_KERNEL;</div><div class='ctx'> </div><div class='del'>-	rc = drv_enable_wq(wq);</div><div class='add'>+	rc = idxd_drv_enable_wq(wq);</div><div class='ctx'> 	if (rc &lt; 0) {</div><div class='ctx'> 		dev_dbg(dev, "Enable wq %d failed: %d\n", wq-&gt;id, rc);</div><div class='ctx'> 		rc = -ENXIO;</div><div class='hunk'>@@ -333,7 +333,7 @@ static int idxd_dmaengine_drv_probe(struct idxd_dev *idxd_dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_dma:</div><div class='del'>-	drv_disable_wq(wq);</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='ctx'> err:</div><div class='ctx'> 	wq-&gt;type = IDXD_WQT_NONE;</div><div class='ctx'> 	mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='hunk'>@@ -347,7 +347,7 @@ static void idxd_dmaengine_drv_remove(struct idxd_dev *idxd_dev)</div><div class='ctx'> 	mutex_lock(&amp;wq-&gt;wq_lock);</div><div class='ctx'> 	__idxd_wq_quiesce(wq);</div><div class='ctx'> 	idxd_unregister_dma_channel(wq);</div><div class='del'>-	drv_disable_wq(wq);</div><div class='add'>+	idxd_drv_disable_wq(wq);</div><div class='ctx'> 	mutex_unlock(&amp;wq-&gt;wq_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -359,6 +359,7 @@ static enum idxd_dev_type dev_types[] = {</div><div class='ctx'> struct idxd_device_driver idxd_dmaengine_drv = {</div><div class='ctx'> 	.probe = idxd_dmaengine_drv_probe,</div><div class='ctx'> 	.remove = idxd_dmaengine_drv_remove,</div><div class='add'>+	.desc_complete = idxd_dma_complete_txd,</div><div class='ctx'> 	.name = "dmaengine",</div><div class='ctx'> 	.type = dev_types,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h<br/>index 1e89c80a07fc..47de3f93ff1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/idxd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/idxd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/idxd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/idxd.h</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #include &lt;linux/bitmap.h&gt;</div><div class='ctx'> #include &lt;linux/perf_event.h&gt;</div><div class='ctx'> #include &lt;linux/iommu.h&gt;</div><div class='add'>+#include &lt;linux/crypto.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/idxd.h&gt;</div><div class='ctx'> #include "registers.h"</div><div class='ctx'> </div><div class='hunk'>@@ -57,11 +58,23 @@ enum idxd_type {</div><div class='ctx'> #define IDXD_ENQCMDS_RETRIES		32</div><div class='ctx'> #define IDXD_ENQCMDS_MAX_RETRIES	64</div><div class='ctx'> </div><div class='add'>+enum idxd_complete_type {</div><div class='add'>+	IDXD_COMPLETE_NORMAL = 0,</div><div class='add'>+	IDXD_COMPLETE_ABORT,</div><div class='add'>+	IDXD_COMPLETE_DEV_FAIL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct idxd_desc;</div><div class='add'>+</div><div class='ctx'> struct idxd_device_driver {</div><div class='ctx'> 	const char *name;</div><div class='ctx'> 	enum idxd_dev_type *type;</div><div class='ctx'> 	int (*probe)(struct idxd_dev *idxd_dev);</div><div class='ctx'> 	void (*remove)(struct idxd_dev *idxd_dev);</div><div class='add'>+	void (*desc_complete)(struct idxd_desc *desc,</div><div class='add'>+			      enum idxd_complete_type comp_type,</div><div class='add'>+			      bool free_desc,</div><div class='add'>+			      void *ctx, u32 *status);</div><div class='ctx'> 	struct device_driver drv;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -174,12 +187,6 @@ enum idxd_op_type {</div><div class='ctx'> 	IDXD_OP_NONBLOCK = 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum idxd_complete_type {</div><div class='del'>-	IDXD_COMPLETE_NORMAL = 0,</div><div class='del'>-	IDXD_COMPLETE_ABORT,</div><div class='del'>-	IDXD_COMPLETE_DEV_FAIL,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct idxd_dma_chan {</div><div class='ctx'> 	struct dma_chan chan;</div><div class='ctx'> 	struct idxd_wq *wq;</div><div class='hunk'>@@ -270,6 +277,8 @@ struct idxd_dma_dev {</div><div class='ctx'> 	struct dma_device dma;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+typedef int (*load_device_defaults_fn_t) (struct idxd_device *idxd);</div><div class='add'>+</div><div class='ctx'> struct idxd_driver_data {</div><div class='ctx'> 	const char *name_prefix;</div><div class='ctx'> 	enum idxd_type type;</div><div class='hunk'>@@ -279,6 +288,7 @@ struct idxd_driver_data {</div><div class='ctx'> 	int evl_cr_off;</div><div class='ctx'> 	int cr_status_off;</div><div class='ctx'> 	int cr_result_off;</div><div class='add'>+	load_device_defaults_fn_t load_device_defaults;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct idxd_evl {</div><div class='hunk'>@@ -378,6 +388,14 @@ static inline unsigned int evl_size(struct idxd_device *idxd)</div><div class='ctx'> 	return idxd-&gt;evl-&gt;size * evl_ent_size(idxd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct crypto_ctx {</div><div class='add'>+	struct acomp_req *req;</div><div class='add'>+	struct crypto_tfm *tfm;</div><div class='add'>+	dma_addr_t src_addr;</div><div class='add'>+	dma_addr_t dst_addr;</div><div class='add'>+	bool compress;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* IDXD software descriptor */</div><div class='ctx'> struct idxd_desc {</div><div class='ctx'> 	union {</div><div class='hunk'>@@ -390,7 +408,10 @@ struct idxd_desc {</div><div class='ctx'> 		struct iax_completion_record *iax_completion;</div><div class='ctx'> 	};</div><div class='ctx'> 	dma_addr_t compl_dma;</div><div class='del'>-	struct dma_async_tx_descriptor txd;</div><div class='add'>+	union {</div><div class='add'>+		struct dma_async_tx_descriptor txd;</div><div class='add'>+		struct crypto_ctx crypto;</div><div class='add'>+	};</div><div class='ctx'> 	struct llist_node llnode;</div><div class='ctx'> 	struct list_head list;</div><div class='ctx'> 	int id;</div><div class='hunk'>@@ -417,6 +438,15 @@ enum idxd_completion_status {</div><div class='ctx'> #define idxd_dev_to_idxd(idxd_dev) container_of(idxd_dev, struct idxd_device, idxd_dev)</div><div class='ctx'> #define idxd_dev_to_wq(idxd_dev) container_of(idxd_dev, struct idxd_wq, idxd_dev)</div><div class='ctx'> </div><div class='add'>+static inline struct idxd_device_driver *wq_to_idxd_drv(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = wq_confdev(wq);</div><div class='add'>+	struct idxd_device_driver *idxd_drv =</div><div class='add'>+		container_of(dev-&gt;driver, struct idxd_device_driver, drv);</div><div class='add'>+</div><div class='add'>+	return idxd_drv;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline struct idxd_device *confdev_to_idxd(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);</div><div class='hunk'>@@ -618,6 +648,16 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq)</div><div class='ctx'> 	return wq-&gt;client_count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static inline void idxd_wq_set_private(struct idxd_wq *wq, void *private)</div><div class='add'>+{</div><div class='add'>+	dev_set_drvdata(wq_confdev(wq), private);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void *idxd_wq_get_private(struct idxd_wq *wq)</div><div class='add'>+{</div><div class='add'>+	return dev_get_drvdata(wq_confdev(wq));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Intel IAA does not support batch processing.</div><div class='ctx'>  * The max batch size of device, max batch size of wq and</div><div class='hunk'>@@ -655,6 +695,9 @@ static inline int idxd_wq_driver_name_match(struct idxd_wq *wq, struct device *d</div><div class='ctx'> 	return (strncmp(wq-&gt;driver_name, dev-&gt;driver-&gt;name, strlen(dev-&gt;driver-&gt;name)) == 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define MODULE_ALIAS_IDXD_DEVICE(type) MODULE_ALIAS("idxd:t" __stringify(type) "*")</div><div class='add'>+#define IDXD_DEVICES_MODALIAS_FMT "idxd:t%d"</div><div class='add'>+</div><div class='ctx'> int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,</div><div class='ctx'> 					struct module *module, const char *mod_name);</div><div class='ctx'> #define idxd_driver_register(driver) \</div><div class='hunk'>@@ -665,6 +708,24 @@ void idxd_driver_unregister(struct idxd_device_driver *idxd_drv);</div><div class='ctx'> #define module_idxd_driver(__idxd_driver) \</div><div class='ctx'> 	module_driver(__idxd_driver, idxd_driver_register, idxd_driver_unregister)</div><div class='ctx'> </div><div class='add'>+void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc);</div><div class='add'>+void idxd_dma_complete_txd(struct idxd_desc *desc,</div><div class='add'>+			   enum idxd_complete_type comp_type,</div><div class='add'>+			   bool free_desc, void *ctx, u32 *status);</div><div class='add'>+</div><div class='add'>+static inline void idxd_desc_complete(struct idxd_desc *desc,</div><div class='add'>+				      enum idxd_complete_type comp_type,</div><div class='add'>+				      bool free_desc)</div><div class='add'>+{</div><div class='add'>+	struct idxd_device_driver *drv;</div><div class='add'>+	u32 status;</div><div class='add'>+</div><div class='add'>+	drv = wq_to_idxd_drv(desc-&gt;wq);</div><div class='add'>+	if (drv-&gt;desc_complete)</div><div class='add'>+		drv-&gt;desc_complete(desc, comp_type, free_desc,</div><div class='add'>+				   &amp;desc-&gt;txd, &amp;status);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int idxd_register_bus_type(void);</div><div class='ctx'> void idxd_unregister_bus_type(void);</div><div class='ctx'> int idxd_register_devices(struct idxd_device *idxd);</div><div class='hunk'>@@ -672,6 +733,7 @@ void idxd_unregister_devices(struct idxd_device *idxd);</div><div class='ctx'> void idxd_wqs_quiesce(struct idxd_device *idxd);</div><div class='ctx'> bool idxd_queue_int_handle_resubmit(struct idxd_desc *desc);</div><div class='ctx'> void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count);</div><div class='add'>+int idxd_load_iaa_device_defaults(struct idxd_device *idxd);</div><div class='ctx'> </div><div class='ctx'> /* device interrupt control */</div><div class='ctx'> irqreturn_t idxd_misc_thread(int vec, void *data);</div><div class='hunk'>@@ -682,8 +744,8 @@ void idxd_unmask_error_interrupts(struct idxd_device *idxd);</div><div class='ctx'> /* device control */</div><div class='ctx'> int idxd_device_drv_probe(struct idxd_dev *idxd_dev);</div><div class='ctx'> void idxd_device_drv_remove(struct idxd_dev *idxd_dev);</div><div class='del'>-int drv_enable_wq(struct idxd_wq *wq);</div><div class='del'>-void drv_disable_wq(struct idxd_wq *wq);</div><div class='add'>+int idxd_drv_enable_wq(struct idxd_wq *wq);</div><div class='add'>+void idxd_drv_disable_wq(struct idxd_wq *wq);</div><div class='ctx'> int idxd_device_init_reset(struct idxd_device *idxd);</div><div class='ctx'> int idxd_device_enable(struct idxd_device *idxd);</div><div class='ctx'> int idxd_device_disable(struct idxd_device *idxd);</div><div class='hunk'>@@ -718,14 +780,11 @@ int idxd_wq_request_irq(struct idxd_wq *wq);</div><div class='ctx'> /* submission */</div><div class='ctx'> int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc);</div><div class='ctx'> struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype);</div><div class='del'>-void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc);</div><div class='ctx'> int idxd_enqcmds(struct idxd_wq *wq, void __iomem *portal, const void *desc);</div><div class='ctx'> </div><div class='ctx'> /* dmaengine */</div><div class='ctx'> int idxd_register_dma_device(struct idxd_device *idxd);</div><div class='ctx'> void idxd_unregister_dma_device(struct idxd_device *idxd);</div><div class='del'>-void idxd_dma_complete_txd(struct idxd_desc *desc,</div><div class='del'>-			   enum idxd_complete_type comp_type, bool free_desc);</div><div class='ctx'> </div><div class='ctx'> /* cdev */</div><div class='ctx'> int idxd_cdev_register(void);</div><div class='head'>diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c<br/>index 0eb1c827a215..14df1f1347a8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/init.c</a></div><div class='hunk'>@@ -59,6 +59,7 @@ static struct idxd_driver_data idxd_driver_data[] = {</div><div class='ctx'> 		.evl_cr_off = offsetof(struct iax_evl_entry, cr),</div><div class='ctx'> 		.cr_status_off = offsetof(struct iax_completion_record, status),</div><div class='ctx'> 		.cr_result_off = offsetof(struct iax_completion_record, error_code),</div><div class='add'>+		.load_device_defaults = idxd_load_iaa_device_defaults,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -745,6 +746,12 @@ static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (data-&gt;load_device_defaults) {</div><div class='add'>+		rc = data-&gt;load_device_defaults(idxd);</div><div class='add'>+		if (rc)</div><div class='add'>+			dev_warn(dev, "IDXD loading device defaults failed\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rc = idxd_register_devices(idxd);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		dev_err(dev, "IDXD sysfs setup failed\n");</div><div class='head'>diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c<br/>index 2183d7f9cdbd..c8a0aa874b11 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/irq.c</a></div><div class='hunk'>@@ -123,7 +123,7 @@ static void idxd_abort_invalid_int_handle_descs(struct idxd_irq_entry *ie)</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(d, t, &amp;flist, list) {</div><div class='ctx'> 		list_del(&amp;d-&gt;list);</div><div class='del'>-		idxd_dma_complete_txd(d, IDXD_COMPLETE_ABORT, true);</div><div class='add'>+		idxd_desc_complete(d, IDXD_COMPLETE_ABORT, true);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -534,7 +534,7 @@ static void idxd_int_handle_resubmit_work(struct work_struct *work)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (rc != -EAGAIN) {</div><div class='ctx'> 			desc-&gt;completion-&gt;status = IDXD_COMP_DESC_ABORT;</div><div class='del'>-			idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT, false);</div><div class='add'>+			idxd_desc_complete(desc, IDXD_COMPLETE_ABORT, false);</div><div class='ctx'> 		}</div><div class='ctx'> 		idxd_free_desc(wq, desc);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -575,11 +575,11 @@ static void irq_process_pending_llist(struct idxd_irq_entry *irq_entry)</div><div class='ctx'> 			 * and 0xff, which DSA_COMP_STATUS_MASK can mask out.</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (unlikely(desc-&gt;completion-&gt;status == IDXD_COMP_DESC_ABORT)) {</div><div class='del'>-				idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT, true);</div><div class='add'>+				idxd_desc_complete(desc, IDXD_COMPLETE_ABORT, true);</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL, true);</div><div class='add'>+			idxd_desc_complete(desc, IDXD_COMPLETE_NORMAL, true);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			spin_lock(&amp;irq_entry-&gt;list_lock);</div><div class='ctx'> 			list_add_tail(&amp;desc-&gt;list,</div><div class='hunk'>@@ -618,11 +618,11 @@ static void irq_process_work_list(struct idxd_irq_entry *irq_entry)</div><div class='ctx'> 		 * and 0xff, which DSA_COMP_STATUS_MASK can mask out.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (unlikely(desc-&gt;completion-&gt;status == IDXD_COMP_DESC_ABORT)) {</div><div class='del'>-			idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT, true);</div><div class='add'>+			idxd_desc_complete(desc, IDXD_COMPLETE_ABORT, true);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		idxd_dma_complete_txd(desc, IDXD_COMPLETE_NORMAL, true);</div><div class='add'>+		idxd_desc_complete(desc, IDXD_COMPLETE_NORMAL, true);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h<br/>index 7b54a3939ea1..315c004f58e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/registers.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/registers.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/registers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/registers.h</a></div><div class='hunk'>@@ -440,12 +440,14 @@ union wqcfg {</div><div class='ctx'> /*</div><div class='ctx'>  * This macro calculates the offset into the GRPCFG register</div><div class='ctx'>  * idxd - struct idxd *</div><div class='del'>- * n - wq id</div><div class='del'>- * ofs - the index of the 32b dword for the config register</div><div class='add'>+ * n - group id</div><div class='add'>+ * ofs - the index of the 64b qword for the config register</div><div class='ctx'>  *</div><div class='del'>- * The WQCFG register block is divided into groups per each wq. The n index</div><div class='del'>- * allows us to move to the register group that's for that particular wq.</div><div class='del'>- * Each register is 32bits. The ofs gives us the number of register to access.</div><div class='add'>+ * The GRPCFG register block is divided into three sub-registers, which</div><div class='add'>+ * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move</div><div class='add'>+ * to the register block that contains the three sub-registers.</div><div class='add'>+ * Each register block is 64bits. And the ofs gives us the offset</div><div class='add'>+ * within the GRPWQCFG register to access.</div><div class='ctx'>  */</div><div class='ctx'> #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)-&gt;grpcfg_offset +\</div><div class='ctx'> 					   (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))</div><div class='head'>diff --git a/drivers/dma/idxd/submit.c b/drivers/dma/idxd/submit.c<br/>index c01db23e3333..817a564413b0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/idxd/submit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/idxd/submit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/idxd/submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/idxd/submit.c</a></div><div class='hunk'>@@ -61,6 +61,7 @@ struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)</div><div class='ctx'> </div><div class='ctx'> 	return __get_desc(wq, idx, cpu);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_alloc_desc, IDXD);</div><div class='ctx'> </div><div class='ctx'> void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc)</div><div class='ctx'> {</div><div class='hunk'>@@ -69,6 +70,7 @@ void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc)</div><div class='ctx'> 	desc-&gt;cpu = -1;</div><div class='ctx'> 	sbitmap_queue_clear(&amp;wq-&gt;sbq, desc-&gt;id, cpu);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_free_desc, IDXD);</div><div class='ctx'> </div><div class='ctx'> static struct idxd_desc *list_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie,</div><div class='ctx'> 					 struct idxd_desc *desc)</div><div class='hunk'>@@ -125,7 +127,8 @@ static void llist_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie,</div><div class='ctx'> 	spin_unlock(&amp;ie-&gt;list_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (found)</div><div class='del'>-		idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, false);</div><div class='add'>+		idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, false,</div><div class='add'>+				      NULL, NULL);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * completing the descriptor will return desc to allocator and</div><div class='hunk'>@@ -135,7 +138,8 @@ static void llist_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie,</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry_safe(d, t, &amp;flist, list) {</div><div class='ctx'> 		list_del_init(&amp;d-&gt;list);</div><div class='del'>-		idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, true);</div><div class='add'>+		idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, true,</div><div class='add'>+				      NULL, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -183,13 +187,6 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)</div><div class='ctx'> 	portal = idxd_wq_portal_addr(wq);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * The wmb() flushes writes to coherent DMA data before</div><div class='del'>-	 * possibly triggering a DMA read. The wmb() is necessary</div><div class='del'>-	 * even on UP because the recipient is a device.</div><div class='del'>-	 */</div><div class='del'>-	wmb();</div><div class='del'>-</div><div class='del'>-	/*</div><div class='ctx'> 	 * Pending the descriptor to the lockless list for the irq_entry</div><div class='ctx'> 	 * that we designated the descriptor to.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -199,6 +196,13 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)</div><div class='ctx'> 		llist_add(&amp;desc-&gt;llnode, &amp;ie-&gt;pending_llist);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * The wmb() flushes writes to coherent DMA data before</div><div class='add'>+	 * possibly triggering a DMA read. The wmb() is necessary</div><div class='add'>+	 * even on UP because the recipient is a device.</div><div class='add'>+	 */</div><div class='add'>+	wmb();</div><div class='add'>+</div><div class='ctx'> 	if (wq_dedicated(wq)) {</div><div class='ctx'> 		iosubmit_cmds512(portal, desc-&gt;hw, 1);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -215,3 +219,4 @@ int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)</div><div class='ctx'> 	percpu_ref_put(&amp;wq-&gt;wq_active);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(idxd_submit_desc, IDXD);</div><div class='head'>diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c<br/>index f81ecf5863e8..9b42f5e96b1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/imx-sdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/imx-sdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/imx-sdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/imx-sdma.c</a></div><div class='hunk'>@@ -421,9 +421,7 @@ struct sdma_desc {</div><div class='ctx'>  * @shp_addr:		value for gReg[6]</div><div class='ctx'>  * @per_addr:		value for gReg[2]</div><div class='ctx'>  * @status:		status of dma channel</div><div class='del'>- * @context_loaded:	ensure context is only loaded once</div><div class='ctx'>  * @data:		specific sdma interface structure</div><div class='del'>- * @bd_pool:		dma_pool for bd</div><div class='ctx'>  * @terminate_worker:	used to call back into terminate work function</div><div class='ctx'>  * @terminated:		terminated list</div><div class='ctx'>  * @is_ram_script:	flag for script in ram</div><div class='hunk'>@@ -486,8 +484,6 @@ struct sdma_channel {</div><div class='ctx'>  * @num_script_addrs:	Number of script addresses in this image</div><div class='ctx'>  * @ram_code_start:	offset of SDMA ram image in this firmware image</div><div class='ctx'>  * @ram_code_size:	size of SDMA ram image</div><div class='del'>- * @script_addrs:	Stores the start address of the SDMA scripts</div><div class='del'>- *			(in SDMA memory space)</div><div class='ctx'>  */</div><div class='ctx'> struct sdma_firmware_header {</div><div class='ctx'> 	u32	magic;</div><div class='head'>diff --git a/drivers/dma/ls2x-apb-dma.c b/drivers/dma/ls2x-apb-dma.c<br/>new file mode 100644<br/>index 000000000000..a49913f3ed3f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ls2x-apb-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ls2x-apb-dma.c</a></div><div class='hunk'>@@ -0,0 +1,705 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Driver for the Loongson LS2X APB DMA Controller</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2017-2023 Loongson Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/dmapool.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_dma.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dmaengine.h"</div><div class='add'>+#include "virt-dma.h"</div><div class='add'>+</div><div class='add'>+/* Global Configuration Register */</div><div class='add'>+#define LDMA_ORDER_ERG		0x0</div><div class='add'>+</div><div class='add'>+/* Bitfield definitions */</div><div class='add'>+</div><div class='add'>+/* Bitfields in Global Configuration Register */</div><div class='add'>+#define LDMA_64BIT_EN		BIT(0) /* 1: 64 bit support */</div><div class='add'>+#define LDMA_UNCOHERENT_EN	BIT(1) /* 0: cache, 1: uncache */</div><div class='add'>+#define LDMA_ASK_VALID		BIT(2)</div><div class='add'>+#define LDMA_START		BIT(3) /* DMA start operation */</div><div class='add'>+#define LDMA_STOP		BIT(4) /* DMA stop operation */</div><div class='add'>+#define LDMA_CONFIG_MASK	GENMASK(4, 0) /* DMA controller config bits mask */</div><div class='add'>+</div><div class='add'>+/* Bitfields in ndesc_addr field of HW decriptor */</div><div class='add'>+#define LDMA_DESC_EN		BIT(0) /*1: The next descriptor is valid */</div><div class='add'>+#define LDMA_DESC_ADDR_LOW	GENMASK(31, 1)</div><div class='add'>+</div><div class='add'>+/* Bitfields in cmd field of HW decriptor */</div><div class='add'>+#define LDMA_INT		BIT(1) /* Enable DMA interrupts */</div><div class='add'>+#define LDMA_DATA_DIRECTION	BIT(12) /* 1: write to device, 0: read from device */</div><div class='add'>+</div><div class='add'>+#define LDMA_SLAVE_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \</div><div class='add'>+				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))</div><div class='add'>+</div><div class='add'>+#define LDMA_MAX_TRANS_LEN	U32_MAX</div><div class='add'>+</div><div class='add'>+/*--  descriptors  -----------------------------------------------------*/</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * struct ls2x_dma_hw_desc - DMA HW descriptor</div><div class='add'>+ * @ndesc_addr: the next descriptor low address.</div><div class='add'>+ * @mem_addr: memory low address.</div><div class='add'>+ * @apb_addr: device buffer address.</div><div class='add'>+ * @len: length of a piece of carried content, in words.</div><div class='add'>+ * @step_len: length between two moved memory data blocks.</div><div class='add'>+ * @step_times: number of blocks to be carried in a single DMA operation.</div><div class='add'>+ * @cmd: descriptor command or state.</div><div class='add'>+ * @stats: DMA status.</div><div class='add'>+ * @high_ndesc_addr: the next descriptor high address.</div><div class='add'>+ * @high_mem_addr: memory high address.</div><div class='add'>+ * @reserved: reserved</div><div class='add'>+ */</div><div class='add'>+struct ls2x_dma_hw_desc {</div><div class='add'>+	u32 ndesc_addr;</div><div class='add'>+	u32 mem_addr;</div><div class='add'>+	u32 apb_addr;</div><div class='add'>+	u32 len;</div><div class='add'>+	u32 step_len;</div><div class='add'>+	u32 step_times;</div><div class='add'>+	u32 cmd;</div><div class='add'>+	u32 stats;</div><div class='add'>+	u32 high_ndesc_addr;</div><div class='add'>+	u32 high_mem_addr;</div><div class='add'>+	u32 reserved[2];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * struct ls2x_dma_sg - ls2x dma scatter gather entry</div><div class='add'>+ * @hw: the pointer to DMA HW descriptor.</div><div class='add'>+ * @llp: physical address of the DMA HW descriptor.</div><div class='add'>+ * @phys: destination or source address(mem).</div><div class='add'>+ * @len: number of Bytes to read.</div><div class='add'>+ */</div><div class='add'>+struct ls2x_dma_sg {</div><div class='add'>+	struct ls2x_dma_hw_desc	*hw;</div><div class='add'>+	dma_addr_t		llp;</div><div class='add'>+	dma_addr_t		phys;</div><div class='add'>+	u32			len;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * struct ls2x_dma_desc - software descriptor</div><div class='add'>+ * @vdesc: pointer to the virtual dma descriptor.</div><div class='add'>+ * @cyclic: flag to dma cyclic</div><div class='add'>+ * @burst_size: burst size of transaction, in words.</div><div class='add'>+ * @desc_num: number of sg entries.</div><div class='add'>+ * @direction: transfer direction, to or from device.</div><div class='add'>+ * @status: dma controller status.</div><div class='add'>+ * @sg: array of sgs.</div><div class='add'>+ */</div><div class='add'>+struct ls2x_dma_desc {</div><div class='add'>+	struct virt_dma_desc		vdesc;</div><div class='add'>+	bool				cyclic;</div><div class='add'>+	size_t				burst_size;</div><div class='add'>+	u32				desc_num;</div><div class='add'>+	enum dma_transfer_direction	direction;</div><div class='add'>+	enum dma_status			status;</div><div class='add'>+	struct ls2x_dma_sg		sg[] __counted_by(desc_num);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*--  Channels  --------------------------------------------------------*/</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * struct ls2x_dma_chan - internal representation of an LS2X APB DMA channel</div><div class='add'>+ * @vchan: virtual dma channel entry.</div><div class='add'>+ * @desc: pointer to the ls2x sw dma descriptor.</div><div class='add'>+ * @pool: hw desc table</div><div class='add'>+ * @irq: irq line</div><div class='add'>+ * @sconfig: configuration for slave transfers, passed via .device_config</div><div class='add'>+ */</div><div class='add'>+struct ls2x_dma_chan {</div><div class='add'>+	struct virt_dma_chan	vchan;</div><div class='add'>+	struct ls2x_dma_desc	*desc;</div><div class='add'>+	void			*pool;</div><div class='add'>+	int			irq;</div><div class='add'>+	struct dma_slave_config	sconfig;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*--  Controller  ------------------------------------------------------*/</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * struct ls2x_dma_priv - LS2X APB DMAC specific information</div><div class='add'>+ * @ddev: dmaengine dma_device object members</div><div class='add'>+ * @dma_clk: DMAC clock source</div><div class='add'>+ * @regs: memory mapped register base</div><div class='add'>+ * @lchan: channel to store ls2x_dma_chan structures</div><div class='add'>+ */</div><div class='add'>+struct ls2x_dma_priv {</div><div class='add'>+	struct dma_device	ddev;</div><div class='add'>+	struct clk		*dma_clk;</div><div class='add'>+	void __iomem		*regs;</div><div class='add'>+	struct ls2x_dma_chan	lchan;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*--  Helper functions  ------------------------------------------------*/</div><div class='add'>+</div><div class='add'>+static inline struct ls2x_dma_desc *to_ldma_desc(struct virt_dma_desc *vdesc)</div><div class='add'>+{</div><div class='add'>+	return container_of(vdesc, struct ls2x_dma_desc, vdesc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct ls2x_dma_chan *to_ldma_chan(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	return container_of(chan, struct ls2x_dma_chan, vchan.chan);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct ls2x_dma_priv *to_ldma_priv(struct dma_device *ddev)</div><div class='add'>+{</div><div class='add'>+	return container_of(ddev, struct ls2x_dma_priv, ddev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct device *chan2dev(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	return &amp;chan-&gt;dev-&gt;device;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ls2x_dma_desc_free(struct virt_dma_desc *vdesc)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(vdesc-&gt;tx.chan);</div><div class='add'>+	struct ls2x_dma_desc *desc = to_ldma_desc(vdesc);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; desc-&gt;desc_num; i++) {</div><div class='add'>+		if (desc-&gt;sg[i].hw)</div><div class='add'>+			dma_pool_free(lchan-&gt;pool, desc-&gt;sg[i].hw,</div><div class='add'>+				      desc-&gt;sg[i].llp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ls2x_dma_write_cmd(struct ls2x_dma_chan *lchan, bool cmd)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_priv *priv = to_ldma_priv(lchan-&gt;vchan.chan.device);</div><div class='add'>+	u64 val;</div><div class='add'>+</div><div class='add'>+	val = lo_hi_readq(priv-&gt;regs + LDMA_ORDER_ERG) &amp; ~LDMA_CONFIG_MASK;</div><div class='add'>+	val |= LDMA_64BIT_EN | cmd;</div><div class='add'>+	lo_hi_writeq(val, priv-&gt;regs + LDMA_ORDER_ERG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ls2x_dma_start_transfer(struct ls2x_dma_chan *lchan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_priv *priv = to_ldma_priv(lchan-&gt;vchan.chan.device);</div><div class='add'>+	struct ls2x_dma_sg *ldma_sg;</div><div class='add'>+	struct virt_dma_desc *vdesc;</div><div class='add'>+	u64 val;</div><div class='add'>+</div><div class='add'>+	/* Get the next descriptor */</div><div class='add'>+	vdesc = vchan_next_desc(&amp;lchan-&gt;vchan);</div><div class='add'>+	if (!vdesc) {</div><div class='add'>+		lchan-&gt;desc = NULL;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_del(&amp;vdesc-&gt;node);</div><div class='add'>+	lchan-&gt;desc = to_ldma_desc(vdesc);</div><div class='add'>+	ldma_sg = &amp;lchan-&gt;desc-&gt;sg[0];</div><div class='add'>+</div><div class='add'>+	/* Start DMA */</div><div class='add'>+	lo_hi_writeq(0, priv-&gt;regs + LDMA_ORDER_ERG);</div><div class='add'>+	val = (ldma_sg-&gt;llp &amp; ~LDMA_CONFIG_MASK) | LDMA_64BIT_EN | LDMA_START;</div><div class='add'>+	lo_hi_writeq(val, priv-&gt;regs + LDMA_ORDER_ERG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t ls2x_dmac_detect_burst(struct ls2x_dma_chan *lchan)</div><div class='add'>+{</div><div class='add'>+	u32 maxburst, buswidth;</div><div class='add'>+</div><div class='add'>+	/* Reject definitely invalid configurations */</div><div class='add'>+	if ((lchan-&gt;sconfig.src_addr_width &amp; LDMA_SLAVE_BUSWIDTHS) &amp;&amp;</div><div class='add'>+	    (lchan-&gt;sconfig.dst_addr_width &amp; LDMA_SLAVE_BUSWIDTHS))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (lchan-&gt;sconfig.direction == DMA_MEM_TO_DEV) {</div><div class='add'>+		maxburst = lchan-&gt;sconfig.dst_maxburst;</div><div class='add'>+		buswidth = lchan-&gt;sconfig.dst_addr_width;</div><div class='add'>+	} else {</div><div class='add'>+		maxburst = lchan-&gt;sconfig.src_maxburst;</div><div class='add'>+		buswidth = lchan-&gt;sconfig.src_addr_width;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If maxburst is zero, fallback to LDMA_MAX_TRANS_LEN */</div><div class='add'>+	return maxburst ? (maxburst * buswidth) &gt;&gt; 2 : LDMA_MAX_TRANS_LEN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ls2x_dma_fill_desc(struct ls2x_dma_chan *lchan, u32 sg_index,</div><div class='add'>+			       struct ls2x_dma_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_sg *ldma_sg = &amp;desc-&gt;sg[sg_index];</div><div class='add'>+	u32 num_segments, segment_size;</div><div class='add'>+</div><div class='add'>+	if (desc-&gt;direction == DMA_MEM_TO_DEV) {</div><div class='add'>+		ldma_sg-&gt;hw-&gt;cmd = LDMA_INT | LDMA_DATA_DIRECTION;</div><div class='add'>+		ldma_sg-&gt;hw-&gt;apb_addr = lchan-&gt;sconfig.dst_addr;</div><div class='add'>+	} else {</div><div class='add'>+		ldma_sg-&gt;hw-&gt;cmd = LDMA_INT;</div><div class='add'>+		ldma_sg-&gt;hw-&gt;apb_addr = lchan-&gt;sconfig.src_addr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ldma_sg-&gt;hw-&gt;mem_addr = lower_32_bits(ldma_sg-&gt;phys);</div><div class='add'>+	ldma_sg-&gt;hw-&gt;high_mem_addr = upper_32_bits(ldma_sg-&gt;phys);</div><div class='add'>+</div><div class='add'>+	/* Split into multiple equally sized segments if necessary */</div><div class='add'>+	num_segments = DIV_ROUND_UP((ldma_sg-&gt;len + 3) &gt;&gt; 2, desc-&gt;burst_size);</div><div class='add'>+	segment_size = DIV_ROUND_UP((ldma_sg-&gt;len + 3) &gt;&gt; 2, num_segments);</div><div class='add'>+</div><div class='add'>+	/* Word count register takes input in words */</div><div class='add'>+	ldma_sg-&gt;hw-&gt;len = segment_size;</div><div class='add'>+	ldma_sg-&gt;hw-&gt;step_times = num_segments;</div><div class='add'>+	ldma_sg-&gt;hw-&gt;step_len = 0;</div><div class='add'>+</div><div class='add'>+	/* lets make a link list */</div><div class='add'>+	if (sg_index) {</div><div class='add'>+		desc-&gt;sg[sg_index - 1].hw-&gt;ndesc_addr = ldma_sg-&gt;llp | LDMA_DESC_EN;</div><div class='add'>+		desc-&gt;sg[sg_index - 1].hw-&gt;high_ndesc_addr = upper_32_bits(ldma_sg-&gt;llp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*--  DMA Engine API  --------------------------------------------------*/</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_alloc_chan_resources - allocate resources for DMA channel</div><div class='add'>+ * @chan: allocate descriptor resources for this channel</div><div class='add'>+ *</div><div class='add'>+ * return - the number of allocated descriptors</div><div class='add'>+ */</div><div class='add'>+static int ls2x_dma_alloc_chan_resources(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+</div><div class='add'>+	/* Create a pool of consistent memory blocks for hardware descriptors */</div><div class='add'>+	lchan-&gt;pool = dma_pool_create(dev_name(chan2dev(chan)),</div><div class='add'>+				      chan-&gt;device-&gt;dev, PAGE_SIZE,</div><div class='add'>+				      __alignof__(struct ls2x_dma_hw_desc), 0);</div><div class='add'>+	if (!lchan-&gt;pool) {</div><div class='add'>+		dev_err(chan2dev(chan), "No memory for descriptors\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_free_chan_resources - free all channel resources</div><div class='add'>+ * @chan: DMA channel</div><div class='add'>+ */</div><div class='add'>+static void ls2x_dma_free_chan_resources(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+</div><div class='add'>+	vchan_free_chan_resources(to_virt_chan(chan));</div><div class='add'>+	dma_pool_destroy(lchan-&gt;pool);</div><div class='add'>+	lchan-&gt;pool = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction</div><div class='add'>+ * @chan: DMA channel</div><div class='add'>+ * @sgl: scatterlist to transfer to/from</div><div class='add'>+ * @sg_len: number of entries in @scatterlist</div><div class='add'>+ * @direction: DMA direction</div><div class='add'>+ * @flags: tx descriptor status flags</div><div class='add'>+ * @context: transaction context (ignored)</div><div class='add'>+ *</div><div class='add'>+ * Return: Async transaction descriptor on success and NULL on failure</div><div class='add'>+ */</div><div class='add'>+static struct dma_async_tx_descriptor *</div><div class='add'>+ls2x_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,</div><div class='add'>+		       u32 sg_len, enum dma_transfer_direction direction,</div><div class='add'>+		       unsigned long flags, void *context)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	struct ls2x_dma_desc *desc;</div><div class='add'>+	struct scatterlist *sg;</div><div class='add'>+	size_t burst_size;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!sg_len || !is_slave_direction(direction)))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	burst_size = ls2x_dmac_detect_burst(lchan);</div><div class='add'>+	if (!burst_size)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	desc = kzalloc(struct_size(desc, sg, sg_len), GFP_NOWAIT);</div><div class='add'>+	if (!desc)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	desc-&gt;desc_num = sg_len;</div><div class='add'>+	desc-&gt;direction = direction;</div><div class='add'>+	desc-&gt;burst_size = burst_size;</div><div class='add'>+</div><div class='add'>+	for_each_sg(sgl, sg, sg_len, i) {</div><div class='add'>+		struct ls2x_dma_sg *ldma_sg = &amp;desc-&gt;sg[i];</div><div class='add'>+</div><div class='add'>+		/* Allocate DMA capable memory for hardware descriptor */</div><div class='add'>+		ldma_sg-&gt;hw = dma_pool_alloc(lchan-&gt;pool, GFP_NOWAIT, &amp;ldma_sg-&gt;llp);</div><div class='add'>+		if (!ldma_sg-&gt;hw) {</div><div class='add'>+			desc-&gt;desc_num = i;</div><div class='add'>+			ls2x_dma_desc_free(&amp;desc-&gt;vdesc);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ldma_sg-&gt;phys = sg_dma_address(sg);</div><div class='add'>+		ldma_sg-&gt;len = sg_dma_len(sg);</div><div class='add'>+</div><div class='add'>+		ls2x_dma_fill_desc(lchan, i, desc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Setting the last descriptor enable bit */</div><div class='add'>+	desc-&gt;sg[sg_len - 1].hw-&gt;ndesc_addr &amp;= ~LDMA_DESC_EN;</div><div class='add'>+	desc-&gt;status = DMA_IN_PROGRESS;</div><div class='add'>+</div><div class='add'>+	return vchan_tx_prep(&amp;lchan-&gt;vchan, &amp;desc-&gt;vdesc, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_prep_dma_cyclic - prepare the cyclic DMA transfer</div><div class='add'>+ * @chan: the DMA channel to prepare</div><div class='add'>+ * @buf_addr: physical DMA address where the buffer starts</div><div class='add'>+ * @buf_len: total number of bytes for the entire buffer</div><div class='add'>+ * @period_len: number of bytes for each period</div><div class='add'>+ * @direction: transfer direction, to or from device</div><div class='add'>+ * @flags: tx descriptor status flags</div><div class='add'>+ *</div><div class='add'>+ * Return: Async transaction descriptor on success and NULL on failure</div><div class='add'>+ */</div><div class='add'>+static struct dma_async_tx_descriptor *</div><div class='add'>+ls2x_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,</div><div class='add'>+			 size_t period_len, enum dma_transfer_direction direction,</div><div class='add'>+			 unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	struct ls2x_dma_desc *desc;</div><div class='add'>+	size_t burst_size;</div><div class='add'>+	u32 num_periods;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!buf_len || !period_len))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!is_slave_direction(direction)))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	burst_size = ls2x_dmac_detect_burst(lchan);</div><div class='add'>+	if (!burst_size)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	num_periods = buf_len / period_len;</div><div class='add'>+	desc = kzalloc(struct_size(desc, sg, num_periods), GFP_NOWAIT);</div><div class='add'>+	if (!desc)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	desc-&gt;desc_num = num_periods;</div><div class='add'>+	desc-&gt;direction = direction;</div><div class='add'>+	desc-&gt;burst_size = burst_size;</div><div class='add'>+</div><div class='add'>+	/* Build cyclic linked list */</div><div class='add'>+	for (i = 0; i &lt; num_periods; i++) {</div><div class='add'>+		struct ls2x_dma_sg *ldma_sg = &amp;desc-&gt;sg[i];</div><div class='add'>+</div><div class='add'>+		/* Allocate DMA capable memory for hardware descriptor */</div><div class='add'>+		ldma_sg-&gt;hw = dma_pool_alloc(lchan-&gt;pool, GFP_NOWAIT, &amp;ldma_sg-&gt;llp);</div><div class='add'>+		if (!ldma_sg-&gt;hw) {</div><div class='add'>+			desc-&gt;desc_num = i;</div><div class='add'>+			ls2x_dma_desc_free(&amp;desc-&gt;vdesc);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ldma_sg-&gt;phys = buf_addr + period_len * i;</div><div class='add'>+		ldma_sg-&gt;len = period_len;</div><div class='add'>+</div><div class='add'>+		ls2x_dma_fill_desc(lchan, i, desc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Lets make a cyclic list */</div><div class='add'>+	desc-&gt;sg[num_periods - 1].hw-&gt;ndesc_addr = desc-&gt;sg[0].llp | LDMA_DESC_EN;</div><div class='add'>+	desc-&gt;sg[num_periods - 1].hw-&gt;high_ndesc_addr = upper_32_bits(desc-&gt;sg[0].llp);</div><div class='add'>+	desc-&gt;cyclic = true;</div><div class='add'>+	desc-&gt;status = DMA_IN_PROGRESS;</div><div class='add'>+</div><div class='add'>+	return vchan_tx_prep(&amp;lchan-&gt;vchan, &amp;desc-&gt;vdesc, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_slave_config - set slave configuration for channel</div><div class='add'>+ * @chan: dma channel</div><div class='add'>+ * @cfg: slave configuration</div><div class='add'>+ *</div><div class='add'>+ * Sets slave configuration for channel</div><div class='add'>+ */</div><div class='add'>+static int ls2x_dma_slave_config(struct dma_chan *chan,</div><div class='add'>+				 struct dma_slave_config *config)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;lchan-&gt;sconfig, config, sizeof(*config));</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_issue_pending - push pending transactions to the hardware</div><div class='add'>+ * @chan: channel</div><div class='add'>+ *</div><div class='add'>+ * When this function is called, all pending transactions are pushed to the</div><div class='add'>+ * hardware and executed.</div><div class='add'>+ */</div><div class='add'>+static void ls2x_dma_issue_pending(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+	if (vchan_issue_pending(&amp;lchan-&gt;vchan) &amp;&amp; !lchan-&gt;desc)</div><div class='add'>+		ls2x_dma_start_transfer(lchan);</div><div class='add'>+	spin_unlock_irqrestore(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_terminate_all - terminate all transactions</div><div class='add'>+ * @chan: channel</div><div class='add'>+ *</div><div class='add'>+ * Stops all DMA transactions.</div><div class='add'>+ */</div><div class='add'>+static int ls2x_dma_terminate_all(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	LIST_HEAD(head);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+	/* Setting stop cmd */</div><div class='add'>+	ls2x_dma_write_cmd(lchan, LDMA_STOP);</div><div class='add'>+	if (lchan-&gt;desc) {</div><div class='add'>+		vchan_terminate_vdesc(&amp;lchan-&gt;desc-&gt;vdesc);</div><div class='add'>+		lchan-&gt;desc = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vchan_get_all_descriptors(&amp;lchan-&gt;vchan, &amp;head);</div><div class='add'>+	spin_unlock_irqrestore(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+</div><div class='add'>+	vchan_dma_desc_free_list(&amp;lchan-&gt;vchan, &amp;head);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_synchronize - Synchronizes the termination of transfers to the</div><div class='add'>+ * current context.</div><div class='add'>+ * @chan: channel</div><div class='add'>+ */</div><div class='add'>+static void ls2x_dma_synchronize(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+</div><div class='add'>+	vchan_synchronize(&amp;lchan-&gt;vchan);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ls2x_dma_pause(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+	if (lchan-&gt;desc &amp;&amp; lchan-&gt;desc-&gt;status == DMA_IN_PROGRESS) {</div><div class='add'>+		ls2x_dma_write_cmd(lchan, LDMA_STOP);</div><div class='add'>+		lchan-&gt;desc-&gt;status = DMA_PAUSED;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ls2x_dma_resume(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = to_ldma_chan(chan);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+	if (lchan-&gt;desc &amp;&amp; lchan-&gt;desc-&gt;status == DMA_PAUSED) {</div><div class='add'>+		lchan-&gt;desc-&gt;status = DMA_IN_PROGRESS;</div><div class='add'>+		ls2x_dma_write_cmd(lchan, LDMA_START);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;lchan-&gt;vchan.lock, flags);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_isr - LS2X DMA Interrupt handler</div><div class='add'>+ * @irq: IRQ number</div><div class='add'>+ * @dev_id: Pointer to ls2x_dma_chan</div><div class='add'>+ *</div><div class='add'>+ * Return: IRQ_HANDLED/IRQ_NONE</div><div class='add'>+ */</div><div class='add'>+static irqreturn_t ls2x_dma_isr(int irq, void *dev_id)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = dev_id;</div><div class='add'>+	struct ls2x_dma_desc *desc;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;lchan-&gt;vchan.lock);</div><div class='add'>+	desc = lchan-&gt;desc;</div><div class='add'>+	if (desc) {</div><div class='add'>+		if (desc-&gt;cyclic) {</div><div class='add'>+			vchan_cyclic_callback(&amp;desc-&gt;vdesc);</div><div class='add'>+		} else {</div><div class='add'>+			desc-&gt;status = DMA_COMPLETE;</div><div class='add'>+			vchan_cookie_complete(&amp;desc-&gt;vdesc);</div><div class='add'>+			ls2x_dma_start_transfer(lchan);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* ls2x_dma_start_transfer() updates lchan-&gt;desc */</div><div class='add'>+		if (!lchan-&gt;desc)</div><div class='add'>+			ls2x_dma_write_cmd(lchan, LDMA_STOP);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;lchan-&gt;vchan.lock);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ls2x_dma_chan_init(struct platform_device *pdev,</div><div class='add'>+			      struct ls2x_dma_priv *priv)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_chan *lchan = &amp;priv-&gt;lchan;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lchan-&gt;irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (lchan-&gt;irq &lt; 0)</div><div class='add'>+		return lchan-&gt;irq;</div><div class='add'>+</div><div class='add'>+	ret = devm_request_irq(dev, lchan-&gt;irq, ls2x_dma_isr, IRQF_TRIGGER_RISING,</div><div class='add'>+			       dev_name(&amp;pdev-&gt;dev), lchan);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Initialize channels related values */</div><div class='add'>+	INIT_LIST_HEAD(&amp;priv-&gt;ddev.channels);</div><div class='add'>+	lchan-&gt;vchan.desc_free = ls2x_dma_desc_free;</div><div class='add'>+	vchan_init(&amp;lchan-&gt;vchan, &amp;priv-&gt;ddev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_probe - Driver probe function</div><div class='add'>+ * @pdev: Pointer to the platform_device structure</div><div class='add'>+ *</div><div class='add'>+ * Return: '0' on success and failure value on error</div><div class='add'>+ */</div><div class='add'>+static int ls2x_dma_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct ls2x_dma_priv *priv;</div><div class='add'>+	struct dma_device *ddev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(priv-&gt;regs))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(priv-&gt;regs),</div><div class='add'>+				     "devm_platform_ioremap_resource failed.\n");</div><div class='add'>+</div><div class='add'>+	priv-&gt;dma_clk = devm_clk_get(&amp;pdev-&gt;dev, NULL);</div><div class='add'>+	if (IS_ERR(priv-&gt;dma_clk))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(priv-&gt;dma_clk), "devm_clk_get failed.\n");</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(priv-&gt;dma_clk);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "clk_prepare_enable failed.\n");</div><div class='add'>+</div><div class='add'>+	ret = ls2x_dma_chan_init(pdev, priv);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto disable_clk;</div><div class='add'>+</div><div class='add'>+	ddev = &amp;priv-&gt;ddev;</div><div class='add'>+	ddev-&gt;dev = dev;</div><div class='add'>+	dma_cap_zero(ddev-&gt;cap_mask);</div><div class='add'>+	dma_cap_set(DMA_SLAVE, ddev-&gt;cap_mask);</div><div class='add'>+	dma_cap_set(DMA_CYCLIC, ddev-&gt;cap_mask);</div><div class='add'>+</div><div class='add'>+	ddev-&gt;device_alloc_chan_resources = ls2x_dma_alloc_chan_resources;</div><div class='add'>+	ddev-&gt;device_free_chan_resources = ls2x_dma_free_chan_resources;</div><div class='add'>+	ddev-&gt;device_tx_status = dma_cookie_status;</div><div class='add'>+	ddev-&gt;device_issue_pending = ls2x_dma_issue_pending;</div><div class='add'>+	ddev-&gt;device_prep_slave_sg = ls2x_dma_prep_slave_sg;</div><div class='add'>+	ddev-&gt;device_prep_dma_cyclic = ls2x_dma_prep_dma_cyclic;</div><div class='add'>+	ddev-&gt;device_config = ls2x_dma_slave_config;</div><div class='add'>+	ddev-&gt;device_terminate_all = ls2x_dma_terminate_all;</div><div class='add'>+	ddev-&gt;device_synchronize = ls2x_dma_synchronize;</div><div class='add'>+	ddev-&gt;device_pause = ls2x_dma_pause;</div><div class='add'>+	ddev-&gt;device_resume = ls2x_dma_resume;</div><div class='add'>+</div><div class='add'>+	ddev-&gt;src_addr_widths = LDMA_SLAVE_BUSWIDTHS;</div><div class='add'>+	ddev-&gt;dst_addr_widths = LDMA_SLAVE_BUSWIDTHS;</div><div class='add'>+	ddev-&gt;directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);</div><div class='add'>+</div><div class='add'>+	ret = dma_async_device_register(&amp;priv-&gt;ddev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto disable_clk;</div><div class='add'>+</div><div class='add'>+	ret = of_dma_controller_register(dev-&gt;of_node, of_dma_xlate_by_chan_id, priv);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto unregister_dmac;</div><div class='add'>+</div><div class='add'>+	platform_set_drvdata(pdev, priv);</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "Loongson LS2X APB DMA driver registered successfully.\n");</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+unregister_dmac:</div><div class='add'>+	dma_async_device_unregister(&amp;priv-&gt;ddev);</div><div class='add'>+disable_clk:</div><div class='add'>+	clk_disable_unprepare(priv-&gt;dma_clk);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * ls2x_dma_remove - Driver remove function</div><div class='add'>+ * @pdev: Pointer to the platform_device structure</div><div class='add'>+ */</div><div class='add'>+static void ls2x_dma_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct ls2x_dma_priv *priv = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='add'>+	dma_async_device_unregister(&amp;priv-&gt;ddev);</div><div class='add'>+	clk_disable_unprepare(priv-&gt;dma_clk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ls2x_dma_of_match_table[] = {</div><div class='add'>+	{ .compatible = "loongson,ls2k1000-apbdma" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ls2x_dma_of_match_table);</div><div class='add'>+</div><div class='add'>+static struct platform_driver ls2x_dmac_driver = {</div><div class='add'>+	.probe		= ls2x_dma_probe,</div><div class='add'>+	.remove_new	= ls2x_dma_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name	= "ls2x-apbdma",</div><div class='add'>+		.of_match_table	= ls2x_dma_of_match_table,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_platform_driver(ls2x_dmac_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Loongson LS2X APB DMA Controller driver");</div><div class='add'>+MODULE_AUTHOR("Loongson Technology Corporation Limited");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/dma/milbeaut-hdmac.c b/drivers/dma/milbeaut-hdmac.c<br/>index 1b0a95892627..7b41c670970a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/milbeaut-hdmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/milbeaut-hdmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/milbeaut-hdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/milbeaut-hdmac.c</a></div><div class='hunk'>@@ -531,7 +531,7 @@ disable_clk:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int milbeaut_hdmac_remove(struct platform_device *pdev)</div><div class='add'>+static void milbeaut_hdmac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct milbeaut_hdmac_device *mdev = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct dma_chan *chan;</div><div class='hunk'>@@ -546,16 +546,21 @@ static int milbeaut_hdmac_remove(struct platform_device *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(chan, &amp;mdev-&gt;ddev.channels, device_node) {</div><div class='ctx'> 		ret = dmaengine_terminate_sync(chan);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * This results in resource leakage and maybe also</div><div class='add'>+			 * use-after-free errors as e.g. *mdev is kfreed.</div><div class='add'>+			 */</div><div class='add'>+			dev_alert(&amp;pdev-&gt;dev, "Failed to terminate channel %d (%pe)\n",</div><div class='add'>+				  chan-&gt;chan_id, ERR_PTR(ret));</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 		milbeaut_hdmac_free_chan_resources(chan);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='ctx'> 	dma_async_device_unregister(&amp;mdev-&gt;ddev);</div><div class='ctx'> 	clk_disable_unprepare(mdev-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id milbeaut_hdmac_match[] = {</div><div class='hunk'>@@ -566,7 +571,7 @@ MODULE_DEVICE_TABLE(of, milbeaut_hdmac_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver milbeaut_hdmac_driver = {</div><div class='ctx'> 	.probe = milbeaut_hdmac_probe,</div><div class='del'>-	.remove = milbeaut_hdmac_remove,</div><div class='add'>+	.remove_new = milbeaut_hdmac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "milbeaut-m10v-hdmac",</div><div class='ctx'> 		.of_match_table = milbeaut_hdmac_match,</div><div class='head'>diff --git a/drivers/dma/milbeaut-xdmac.c b/drivers/dma/milbeaut-xdmac.c<br/>index d29d01e730aa..2cce529b448e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/milbeaut-xdmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/milbeaut-xdmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/milbeaut-xdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/milbeaut-xdmac.c</a></div><div class='hunk'>@@ -368,7 +368,7 @@ disable_xdmac:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int milbeaut_xdmac_remove(struct platform_device *pdev)</div><div class='add'>+static void milbeaut_xdmac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct milbeaut_xdmac_device *mdev = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct dma_chan *chan;</div><div class='hunk'>@@ -383,8 +383,15 @@ static int milbeaut_xdmac_remove(struct platform_device *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(chan, &amp;mdev-&gt;ddev.channels, device_node) {</div><div class='ctx'> 		ret = dmaengine_terminate_sync(chan);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * This results in resource leakage and maybe also</div><div class='add'>+			 * use-after-free errors as e.g. *mdev is kfreed.</div><div class='add'>+			 */</div><div class='add'>+			dev_alert(&amp;pdev-&gt;dev, "Failed to terminate channel %d (%pe)\n",</div><div class='add'>+				  chan-&gt;chan_id, ERR_PTR(ret));</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 		milbeaut_xdmac_free_chan_resources(chan);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -392,8 +399,6 @@ static int milbeaut_xdmac_remove(struct platform_device *pdev)</div><div class='ctx'> 	dma_async_device_unregister(&amp;mdev-&gt;ddev);</div><div class='ctx'> </div><div class='ctx'> 	disable_xdmac(mdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id milbeaut_xdmac_match[] = {</div><div class='hunk'>@@ -404,7 +409,7 @@ MODULE_DEVICE_TABLE(of, milbeaut_xdmac_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver milbeaut_xdmac_driver = {</div><div class='ctx'> 	.probe = milbeaut_xdmac_probe,</div><div class='del'>-	.remove = milbeaut_xdmac_remove,</div><div class='add'>+	.remove_new = milbeaut_xdmac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "milbeaut-m10v-xdmac",</div><div class='ctx'> 		.of_match_table = milbeaut_xdmac_match,</div><div class='head'>diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c<br/>index 3cf0b38387ae..c29744bfdf2c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/pl330.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/pl330.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/pl330.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/pl330.c</a></div><div class='hunk'>@@ -1053,6 +1053,9 @@ static bool _trigger(struct pl330_thread *thrd)</div><div class='ctx'> </div><div class='ctx'> 	thrd-&gt;req_running = idx;</div><div class='ctx'> </div><div class='add'>+	if (desc-&gt;rqtype == DMA_MEM_TO_DEV || desc-&gt;rqtype == DMA_DEV_TO_MEM)</div><div class='add'>+		UNTIL(thrd, PL330_STATE_WFP);</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c<br/>index 3125a2f162b4..428473611115 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/sf-pdma/sf-pdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/sf-pdma/sf-pdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/sf-pdma/sf-pdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sf-pdma/sf-pdma.c</a></div><div class='hunk'>@@ -20,10 +20,13 @@</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_dma.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "sf-pdma.h"</div><div class='ctx'> </div><div class='add'>+#define PDMA_QUIRK_NO_STRICT_ORDERING   BIT(0)</div><div class='add'>+</div><div class='ctx'> #ifndef readq</div><div class='ctx'> static inline unsigned long long readq(void __iomem *addr)</div><div class='ctx'> {</div><div class='hunk'>@@ -65,7 +68,7 @@ static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan)</div><div class='ctx'> static void sf_pdma_fill_desc(struct sf_pdma_desc *desc,</div><div class='ctx'> 			      u64 dst, u64 src, u64 size)</div><div class='ctx'> {</div><div class='del'>-	desc-&gt;xfer_type = PDMA_FULL_SPEED;</div><div class='add'>+	desc-&gt;xfer_type =  desc-&gt;chan-&gt;pdma-&gt;transfer_type;</div><div class='ctx'> 	desc-&gt;xfer_size = size;</div><div class='ctx'> 	desc-&gt;dst_addr = dst;</div><div class='ctx'> 	desc-&gt;src_addr = src;</div><div class='hunk'>@@ -492,6 +495,7 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma)</div><div class='ctx'> </div><div class='ctx'> static int sf_pdma_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='add'>+	const struct sf_pdma_driver_platdata *ddata;</div><div class='ctx'> 	struct sf_pdma *pdma;</div><div class='ctx'> 	int ret, n_chans;</div><div class='ctx'> 	const enum dma_slave_buswidth widths =</div><div class='hunk'>@@ -517,6 +521,14 @@ static int sf_pdma_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	pdma-&gt;n_chans = n_chans;</div><div class='ctx'> </div><div class='add'>+	pdma-&gt;transfer_type = PDMA_FULL_SPEED | PDMA_STRICT_ORDERING;</div><div class='add'>+</div><div class='add'>+	ddata  = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ddata) {</div><div class='add'>+		if (ddata-&gt;quirks &amp; PDMA_QUIRK_NO_STRICT_ORDERING)</div><div class='add'>+			pdma-&gt;transfer_type &amp;= ~PDMA_STRICT_ORDERING;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pdma-&gt;membase = devm_platform_ioremap_resource(pdev, 0);</div><div class='ctx'> 	if (IS_ERR(pdma-&gt;membase))</div><div class='ctx'> 		return PTR_ERR(pdma-&gt;membase);</div><div class='hunk'>@@ -563,7 +575,20 @@ static int sf_pdma_probe(struct platform_device *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = of_dma_controller_register(pdev-&gt;dev.of_node,</div><div class='add'>+					 of_dma_xlate_by_chan_id, pdma);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev,</div><div class='add'>+			"Can't register SiFive Platform OF_DMA. (%d)\n", ret);</div><div class='add'>+		goto err_unregister;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+err_unregister:</div><div class='add'>+	dma_async_device_unregister(&amp;pdma-&gt;dma_dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sf_pdma_remove(struct platform_device *pdev)</div><div class='hunk'>@@ -583,12 +608,25 @@ static void sf_pdma_remove(struct platform_device *pdev)</div><div class='ctx'> 		tasklet_kill(&amp;ch-&gt;err_tasklet);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pdev-&gt;dev.of_node)</div><div class='add'>+		of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='add'>+</div><div class='ctx'> 	dma_async_device_unregister(&amp;pdma-&gt;dma_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct sf_pdma_driver_platdata mpfs_pdma = {</div><div class='add'>+	.quirks = PDMA_QUIRK_NO_STRICT_ORDERING,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id sf_pdma_dt_ids[] = {</div><div class='del'>-	{ .compatible = "sifive,fu540-c000-pdma" },</div><div class='del'>-	{ .compatible = "sifive,pdma0" },</div><div class='add'>+	{</div><div class='add'>+		.compatible = "sifive,fu540-c000-pdma",</div><div class='add'>+	}, {</div><div class='add'>+		.compatible = "sifive,pdma0",</div><div class='add'>+	}, {</div><div class='add'>+		.compatible = "microchip,mpfs-pdma",</div><div class='add'>+		.data	    = &amp;mpfs_pdma,</div><div class='add'>+	},</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);</div><div class='head'>diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h<br/>index d05772b5d8d3..215e07183d7e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/sf-pdma/sf-pdma.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/sf-pdma/sf-pdma.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/sf-pdma/sf-pdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sf-pdma/sf-pdma.h</a></div><div class='hunk'>@@ -48,7 +48,8 @@</div><div class='ctx'> #define PDMA_ERR_STATUS_MASK				GENMASK(31, 31)</div><div class='ctx'> </div><div class='ctx'> /* Transfer Type */</div><div class='del'>-#define PDMA_FULL_SPEED					0xFF000008</div><div class='add'>+#define PDMA_FULL_SPEED					0xFF000000</div><div class='add'>+#define PDMA_STRICT_ORDERING				BIT(3)</div><div class='ctx'> </div><div class='ctx'> /* Error Recovery */</div><div class='ctx'> #define MAX_RETRY					1</div><div class='hunk'>@@ -112,8 +113,13 @@ struct sf_pdma {</div><div class='ctx'> 	struct dma_device       dma_dev;</div><div class='ctx'> 	void __iomem            *membase;</div><div class='ctx'> 	void __iomem            *mappedbase;</div><div class='add'>+	u32			transfer_type;</div><div class='ctx'> 	u32			n_chans;</div><div class='ctx'> 	struct sf_pdma_chan	chans[] __counted_by(n_chans);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct sf_pdma_driver_platdata {</div><div class='add'>+	u32 quirks;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #endif /* _SF_PDMA_H */</div><div class='head'>diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c<br/>index fea5bda34bc2..1f1e86ba5c66 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/sh/rz-dmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/sh/rz-dmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/sh/rz-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/rz-dmac.c</a></div><div class='hunk'>@@ -755,11 +755,11 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec,</div><div class='ctx'> </div><div class='ctx'> static int rz_dmac_chan_probe(struct rz_dmac *dmac,</div><div class='ctx'> 			      struct rz_dmac_chan *channel,</div><div class='del'>-			      unsigned int index)</div><div class='add'>+			      u8 index)</div><div class='ctx'> {</div><div class='ctx'> 	struct platform_device *pdev = to_platform_device(dmac-&gt;dev);</div><div class='ctx'> 	struct rz_lmdesc *lmdesc;</div><div class='del'>-	char pdev_irqname[5];</div><div class='add'>+	char pdev_irqname[6];</div><div class='ctx'> 	char *irqname;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -767,7 +767,7 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac,</div><div class='ctx'> 	channel-&gt;mid_rid = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Request the channel interrupt. */</div><div class='del'>-	sprintf(pdev_irqname, "ch%u", index);</div><div class='add'>+	scnprintf(pdev_irqname, sizeof(pdev_irqname), "ch%u", index);</div><div class='ctx'> 	channel-&gt;irq = platform_get_irq_byname(pdev, pdev_irqname);</div><div class='ctx'> 	if (channel-&gt;irq &lt; 0)</div><div class='ctx'> 		return channel-&gt;irq;</div><div class='hunk'>@@ -845,9 +845,9 @@ static int rz_dmac_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct dma_device *engine;</div><div class='ctx'> 	struct rz_dmac *dmac;</div><div class='ctx'> 	int channel_num;</div><div class='del'>-	unsigned int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int irq;</div><div class='add'>+	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	dmac = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*dmac), GFP_KERNEL);</div><div class='ctx'> 	if (!dmac)</div><div class='head'>diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h<br/>index 9c121a4b33ad..f97d80343aea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/sh/shdma.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/sh/shdma.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/sh/shdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/shdma.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@ struct sh_dmae_chan {</div><div class='ctx'> 	const struct sh_dmae_slave_config *config; /* Slave DMA configuration */</div><div class='ctx'> 	int xmit_shift;			/* log_2(bytes_per_xfer) */</div><div class='ctx'> 	void __iomem *base;</div><div class='del'>-	char dev_id[16];		/* unique name per DMAC of channel */</div><div class='add'>+	char dev_id[32];		/* unique name per DMAC of channel */</div><div class='ctx'> 	int pm_error;</div><div class='ctx'> 	dma_addr_t slave_addr;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/dma/sh/usb-dmac.c b/drivers/dma/sh/usb-dmac.c<br/>index a9b4302f6050..f7cd0cad056c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/sh/usb-dmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/sh/usb-dmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/sh/usb-dmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/sh/usb-dmac.c</a></div><div class='hunk'>@@ -706,10 +706,10 @@ static const struct dev_pm_ops usb_dmac_pm = {</div><div class='ctx'> </div><div class='ctx'> static int usb_dmac_chan_probe(struct usb_dmac *dmac,</div><div class='ctx'> 			       struct usb_dmac_chan *uchan,</div><div class='del'>-			       unsigned int index)</div><div class='add'>+			       u8 index)</div><div class='ctx'> {</div><div class='ctx'> 	struct platform_device *pdev = to_platform_device(dmac-&gt;dev);</div><div class='del'>-	char pdev_irqname[5];</div><div class='add'>+	char pdev_irqname[6];</div><div class='ctx'> 	char *irqname;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -717,7 +717,7 @@ static int usb_dmac_chan_probe(struct usb_dmac *dmac,</div><div class='ctx'> 	uchan-&gt;iomem = dmac-&gt;iomem + USB_DMAC_CHAN_OFFSET(index);</div><div class='ctx'> </div><div class='ctx'> 	/* Request the channel interrupt. */</div><div class='del'>-	sprintf(pdev_irqname, "ch%u", index);</div><div class='add'>+	scnprintf(pdev_irqname, sizeof(pdev_irqname), "ch%u", index);</div><div class='ctx'> 	uchan-&gt;irq = platform_get_irq_byname(pdev, pdev_irqname);</div><div class='ctx'> 	if (uchan-&gt;irq &lt; 0)</div><div class='ctx'> 		return -ENODEV;</div><div class='hunk'>@@ -768,8 +768,8 @@ static int usb_dmac_probe(struct platform_device *pdev)</div><div class='ctx'> 	const enum dma_slave_buswidth widths = USB_DMAC_SLAVE_BUSWIDTH;</div><div class='ctx'> 	struct dma_device *engine;</div><div class='ctx'> 	struct usb_dmac *dmac;</div><div class='del'>-	unsigned int i;</div><div class='ctx'> 	int ret;</div><div class='add'>+	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	dmac = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*dmac), GFP_KERNEL);</div><div class='ctx'> 	if (!dmac)</div><div class='hunk'>@@ -869,7 +869,7 @@ static void usb_dmac_chan_remove(struct usb_dmac *dmac,</div><div class='ctx'> static void usb_dmac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct usb_dmac *dmac = platform_get_drvdata(pdev);</div><div class='del'>-	int i;</div><div class='add'>+	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dmac-&gt;n_channels; ++i)</div><div class='ctx'> 		usb_dmac_chan_remove(dmac, &amp;dmac-&gt;channels[i]);</div><div class='head'>diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c<br/>index 002833fb1fa0..2c489299148e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ste_dma40.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ste_dma40.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ste_dma40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ste_dma40.c</a></div><div class='hunk'>@@ -31,13 +31,11 @@</div><div class='ctx'> /**</div><div class='ctx'>  * struct stedma40_platform_data - Configuration struct for the dma device.</div><div class='ctx'>  *</div><div class='del'>- * @dev_tx: mapping between destination event line and io address</div><div class='del'>- * @dev_rx: mapping between source event line and io address</div><div class='ctx'>  * @disabled_channels: A vector, ending with -1, that marks physical channels</div><div class='ctx'>  * that are for different reasons not available for the driver.</div><div class='ctx'>  * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW</div><div class='ctx'>  * which avoids HW bug that exists in some versions of the controller.</div><div class='del'>- * SoftLLI introduces relink overhead that could impact performace for</div><div class='add'>+ * SoftLLI introduces relink overhead that could impact performance for</div><div class='ctx'>  * certain use cases.</div><div class='ctx'>  * @num_of_soft_lli_chans: The number of channels that needs to be configured</div><div class='ctx'>  * to use SoftLLI.</div><div class='hunk'>@@ -184,7 +182,7 @@ static __maybe_unused u32 d40_backup_regs[] = {</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * since 9540 and 8540 has the same HW revision</div><div class='del'>- * use v4a for 9540 or ealier</div><div class='add'>+ * use v4a for 9540 or earlier</div><div class='ctx'>  * use v4b for 8540 or later</div><div class='ctx'>  * HW revision:</div><div class='ctx'>  * DB8500ed has revision 0</div><div class='hunk'>@@ -411,7 +409,7 @@ struct d40_desc {</div><div class='ctx'>  *</div><div class='ctx'>  * @base: The virtual address of LCLA. 18 bit aligned.</div><div class='ctx'>  * @dma_addr: DMA address, if mapped</div><div class='del'>- * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.</div><div class='add'>+ * @base_unaligned: The original kmalloc pointer, if kmalloc is used.</div><div class='ctx'>  * This pointer is only there for clean-up on error.</div><div class='ctx'>  * @pages: The number of pages needed for all physical channels.</div><div class='ctx'>  * Only used later for clean-up on error</div><div class='hunk'>@@ -1655,7 +1653,7 @@ static void dma_tasklet(struct tasklet_struct *t)</div><div class='ctx'> </div><div class='ctx'> 	return;</div><div class='ctx'>  check_pending_tx:</div><div class='del'>-	/* Rescue manouver if receiving double interrupts */</div><div class='add'>+	/* Rescue maneuver if receiving double interrupts */</div><div class='ctx'> 	if (d40c-&gt;pending_tx &gt; 0)</div><div class='ctx'> 		d40c-&gt;pending_tx--;</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;d40c-&gt;lock, flags);</div><div class='hunk'>@@ -3412,7 +3410,7 @@ static int __init d40_lcla_allocate(struct d40_base *base)</div><div class='ctx'> 		base-&gt;lcla_pool.base = (void *)page_list[i];</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/*</div><div class='del'>-		 * After many attempts and no succees with finding the correct</div><div class='add'>+		 * After many attempts and no success with finding the correct</div><div class='ctx'> 		 * alignment, try with allocating a big buffer.</div><div class='ctx'> 		 */</div><div class='ctx'> 		dev_warn(base-&gt;dev,</div><div class='head'>diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c<br/>index 72d83cd9ed6b..90857d08a1a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/stm32-dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/stm32-dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/stm32-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/stm32-dma.c</a></div><div class='hunk'>@@ -1246,8 +1246,8 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(</div><div class='ctx'> 	enum dma_slave_buswidth max_width;</div><div class='ctx'> 	struct stm32_dma_desc *desc;</div><div class='ctx'> 	size_t xfer_count, offset;</div><div class='del'>-	u32 num_sgs, best_burst, dma_burst, threshold;</div><div class='del'>-	int i;</div><div class='add'>+	u32 num_sgs, best_burst, threshold;</div><div class='add'>+	int dma_burst, i;</div><div class='ctx'> </div><div class='ctx'> 	num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);</div><div class='ctx'> 	desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);</div><div class='hunk'>@@ -1266,6 +1266,10 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(</div><div class='ctx'> 		best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,</div><div class='ctx'> 						      threshold, max_width);</div><div class='ctx'> 		dma_burst = stm32_dma_get_burst(chan, best_burst);</div><div class='add'>+		if (dma_burst &lt; 0) {</div><div class='add'>+			kfree(desc);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		stm32_dma_clear_reg(&amp;desc-&gt;sg_req[i].chan_reg);</div><div class='ctx'> 		desc-&gt;sg_req[i].chan_reg.dma_scr =</div><div class='head'>diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c<br/>index fa4d4142a68a..88547a23825b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/tegra186-gpc-dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/tegra186-gpc-dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/tegra186-gpc-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/tegra186-gpc-dma.c</a></div><div class='hunk'>@@ -1348,8 +1348,8 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)</div><div class='ctx'> static int tegra_dma_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	const struct tegra_dma_chip_data *cdata = NULL;</div><div class='del'>-	struct iommu_fwspec *iommu_spec;</div><div class='del'>-	unsigned int stream_id, i;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 stream_id;</div><div class='ctx'> 	struct tegra_dma *tdma;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1378,12 +1378,10 @@ static int tegra_dma_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	tdma-&gt;dma_dev.dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	iommu_spec = dev_iommu_fwspec_get(&amp;pdev-&gt;dev);</div><div class='del'>-	if (!iommu_spec) {</div><div class='add'>+	if (!tegra_dev_iommu_get_stream_id(&amp;pdev-&gt;dev, &amp;stream_id)) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "Missing iommu stream-id\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	stream_id = iommu_spec-&gt;ids[0] &amp; 0xffff;</div><div class='ctx'> </div><div class='ctx'> 	ret = device_property_read_u32(&amp;pdev-&gt;dev, "dma-channel-mask",</div><div class='ctx'> 				       &amp;tdma-&gt;chan_mask);</div><div class='head'>diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c<br/>index 7a0586633bf3..24ad7077c53b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/tegra210-adma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/tegra210-adma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/tegra210-adma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/tegra210-adma.c</a></div><div class='hunk'>@@ -153,6 +153,7 @@ struct tegra_adma {</div><div class='ctx'> 	void __iomem			*base_addr;</div><div class='ctx'> 	struct clk			*ahub_clk;</div><div class='ctx'> 	unsigned int			nr_channels;</div><div class='add'>+	unsigned long			*dma_chan_mask;</div><div class='ctx'> 	unsigned long			rx_requests_reserved;</div><div class='ctx'> 	unsigned long			tx_requests_reserved;</div><div class='ctx'> </div><div class='hunk'>@@ -741,6 +742,10 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; tdma-&gt;nr_channels; i++) {</div><div class='ctx'> 		tdc = &amp;tdma-&gt;channels[i];</div><div class='add'>+		/* skip for reserved channels */</div><div class='add'>+		if (!tdc-&gt;tdma)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		ch_reg = &amp;tdc-&gt;ch_regs;</div><div class='ctx'> 		ch_reg-&gt;cmd = tdma_ch_read(tdc, ADMA_CH_CMD);</div><div class='ctx'> 		/* skip if channel is not active */</div><div class='hunk'>@@ -779,6 +784,9 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; tdma-&gt;nr_channels; i++) {</div><div class='ctx'> 		tdc = &amp;tdma-&gt;channels[i];</div><div class='add'>+		/* skip for reserved channels */</div><div class='add'>+		if (!tdc-&gt;tdma)</div><div class='add'>+			continue;</div><div class='ctx'> 		ch_reg = &amp;tdc-&gt;ch_regs;</div><div class='ctx'> 		/* skip if channel was not active earlier */</div><div class='ctx'> 		if (!ch_reg-&gt;cmd)</div><div class='hunk'>@@ -867,10 +875,31 @@ static int tegra_adma_probe(struct platform_device *pdev)</div><div class='ctx'> 		return PTR_ERR(tdma-&gt;ahub_clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	tdma-&gt;dma_chan_mask = devm_kzalloc(&amp;pdev-&gt;dev,</div><div class='add'>+					   BITS_TO_LONGS(tdma-&gt;nr_channels) * sizeof(unsigned long),</div><div class='add'>+					   GFP_KERNEL);</div><div class='add'>+	if (!tdma-&gt;dma_chan_mask)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Enable all channels by default */</div><div class='add'>+	bitmap_fill(tdma-&gt;dma_chan_mask, tdma-&gt;nr_channels);</div><div class='add'>+</div><div class='add'>+	ret = of_property_read_u32_array(pdev-&gt;dev.of_node, "dma-channel-mask",</div><div class='add'>+					 (u32 *)tdma-&gt;dma_chan_mask,</div><div class='add'>+					 BITS_TO_U32(tdma-&gt;nr_channels));</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; (ret != -EINVAL)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "dma-channel-mask is not complete.\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;tdma-&gt;dma_dev.channels);</div><div class='ctx'> 	for (i = 0; i &lt; tdma-&gt;nr_channels; i++) {</div><div class='ctx'> 		struct tegra_adma_chan *tdc = &amp;tdma-&gt;channels[i];</div><div class='ctx'> </div><div class='add'>+		/* skip for reserved channels */</div><div class='add'>+		if (!test_bit(i, tdma-&gt;dma_chan_mask))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		tdc-&gt;chan_addr = tdma-&gt;base_addr + cdata-&gt;ch_base_offset</div><div class='ctx'> 				 + (cdata-&gt;ch_reg_size * i);</div><div class='ctx'> </div><div class='hunk'>@@ -957,8 +986,10 @@ static void tegra_adma_remove(struct platform_device *pdev)</div><div class='ctx'> 	of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='ctx'> 	dma_async_device_unregister(&amp;tdma-&gt;dma_dev);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; tdma-&gt;nr_channels; ++i)</div><div class='del'>-		irq_dispose_mapping(tdma-&gt;channels[i].irq);</div><div class='add'>+	for (i = 0; i &lt; tdma-&gt;nr_channels; ++i) {</div><div class='add'>+		if (tdma-&gt;channels[i].irq)</div><div class='add'>+			irq_dispose_mapping(tdma-&gt;channels[i].irq);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile<br/>index acc950bf609c..d376c117cecf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/Makefile</a></div><div class='hunk'>@@ -12,6 +12,7 @@ k3-psil-lib-objs := k3-psil.o \</div><div class='ctx'> 		    k3-psil-j721s2.o \</div><div class='ctx'> 		    k3-psil-am62.o \</div><div class='ctx'> 		    k3-psil-am62a.o \</div><div class='del'>-		    k3-psil-j784s4.o</div><div class='add'>+		    k3-psil-j784s4.o \</div><div class='add'>+		    k3-psil-am62p.o</div><div class='ctx'> obj-$(CONFIG_TI_K3_PSIL) += k3-psil-lib.o</div><div class='ctx'> obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o</div><div class='head'>diff --git a/drivers/dma/ti/k3-psil-am62.c b/drivers/dma/ti/k3-psil-am62.c<br/>index 2b6fd6e37c61..1272b1541f61 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-am62.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/k3-psil-am62.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-am62.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62.c</a></div><div class='hunk'>@@ -74,7 +74,9 @@ static struct psil_ep am62_src_ep_map[] = {</div><div class='ctx'> 	PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),</div><div class='ctx'> 	PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),</div><div class='ctx'> 	PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),</div><div class='del'>-	/* PDMA_MAIN0 - SPI0-3 */</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4301),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4302),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4303),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4304),</div><div class='hunk'>@@ -85,8 +87,6 @@ static struct psil_ep am62_src_ep_map[] = {</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4309),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x430a),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x430b),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0x430c),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0x430d),</div><div class='ctx'> 	/* PDMA_MAIN1 - UART0-6 */</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4400),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4401),</div><div class='hunk'>@@ -141,7 +141,9 @@ static struct psil_ep am62_dst_ep_map[] = {</div><div class='ctx'> 	/* SAUL */</div><div class='ctx'> 	PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),</div><div class='ctx'> 	PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),</div><div class='del'>-	/* PDMA_MAIN0 - SPI0-3 */</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc301),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc302),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc303),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc304),</div><div class='hunk'>@@ -152,8 +154,6 @@ static struct psil_ep am62_dst_ep_map[] = {</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc309),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc30a),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc30b),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0xc30c),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0xc30d),</div><div class='ctx'> 	/* PDMA_MAIN1 - UART0-6 */</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc400),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc401),</div><div class='head'>diff --git a/drivers/dma/ti/k3-psil-am62a.c b/drivers/dma/ti/k3-psil-am62a.c<br/>index ca9d71f91422..4cf9123b0e93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-am62a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/k3-psil-am62a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-am62a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62a.c</a></div><div class='hunk'>@@ -84,7 +84,9 @@ static struct psil_ep am62a_src_ep_map[] = {</div><div class='ctx'> 	PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),</div><div class='ctx'> 	PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),</div><div class='ctx'> 	PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),</div><div class='del'>-	/* PDMA_MAIN0 - SPI0-3 */</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4301),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4302),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4303),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4304),</div><div class='hunk'>@@ -95,8 +97,6 @@ static struct psil_ep am62a_src_ep_map[] = {</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4309),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x430a),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x430b),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0x430c),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0x430d),</div><div class='ctx'> 	/* PDMA_MAIN1 - UART0-6 */</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4400),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0x4401),</div><div class='hunk'>@@ -151,7 +151,9 @@ static struct psil_ep am62a_dst_ep_map[] = {</div><div class='ctx'> 	/* SAUL */</div><div class='ctx'> 	PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),</div><div class='ctx'> 	PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),</div><div class='del'>-	/* PDMA_MAIN0 - SPI0-3 */</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc301),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc302),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc303),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc304),</div><div class='hunk'>@@ -162,8 +164,6 @@ static struct psil_ep am62a_dst_ep_map[] = {</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc309),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc30a),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc30b),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0xc30c),</div><div class='del'>-	PSIL_PDMA_XY_PKT(0xc30d),</div><div class='ctx'> 	/* PDMA_MAIN1 - UART0-6 */</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc400),</div><div class='ctx'> 	PSIL_PDMA_XY_PKT(0xc401),</div><div class='head'>diff --git a/drivers/dma/ti/k3-psil-am62p.c b/drivers/dma/ti/k3-psil-am62p.c<br/>new file mode 100644<br/>index 000000000000..0f338e16d971<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-am62p.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-am62p.c</a></div><div class='hunk'>@@ -0,0 +1,325 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ *  Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+</div><div class='add'>+#include "k3-psil-priv.h"</div><div class='add'>+</div><div class='add'>+#define PSIL_PDMA_XY_TR(x)					\</div><div class='add'>+	{							\</div><div class='add'>+		.thread_id = x,					\</div><div class='add'>+		.ep_config = {					\</div><div class='add'>+			.ep_type = PSIL_EP_PDMA_XY,		\</div><div class='add'>+			.mapped_channel_id = -1,		\</div><div class='add'>+			.default_flow_id = -1,			\</div><div class='add'>+		},						\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define PSIL_PDMA_XY_PKT(x)					\</div><div class='add'>+	{							\</div><div class='add'>+		.thread_id = x,					\</div><div class='add'>+		.ep_config = {					\</div><div class='add'>+			.ep_type = PSIL_EP_PDMA_XY,		\</div><div class='add'>+			.mapped_channel_id = -1,		\</div><div class='add'>+			.default_flow_id = -1,			\</div><div class='add'>+			.pkt_mode = 1,				\</div><div class='add'>+		},						\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)		\</div><div class='add'>+	{							\</div><div class='add'>+		.thread_id = x,					\</div><div class='add'>+		.ep_config = {					\</div><div class='add'>+			.ep_type = PSIL_EP_NATIVE,		\</div><div class='add'>+			.pkt_mode = 1,				\</div><div class='add'>+			.needs_epib = 1,			\</div><div class='add'>+			.psd_size = 16,				\</div><div class='add'>+			.mapped_channel_id = ch,		\</div><div class='add'>+			.flow_start = flow_base,		\</div><div class='add'>+			.flow_num = flow_cnt,			\</div><div class='add'>+			.default_flow_id = flow_base,		\</div><div class='add'>+		},						\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)	\</div><div class='add'>+	{							\</div><div class='add'>+		.thread_id = x,					\</div><div class='add'>+		.ep_config = {					\</div><div class='add'>+			.ep_type = PSIL_EP_NATIVE,		\</div><div class='add'>+			.pkt_mode = 1,				\</div><div class='add'>+			.needs_epib = 1,			\</div><div class='add'>+			.psd_size = 64,				\</div><div class='add'>+			.mapped_channel_id = ch,		\</div><div class='add'>+			.flow_start = flow_base,		\</div><div class='add'>+			.flow_num = flow_cnt,			\</div><div class='add'>+			.default_flow_id = default_flow,	\</div><div class='add'>+			.notdpkt = tx,				\</div><div class='add'>+		},						\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define PSIL_PDMA_MCASP(x)				\</div><div class='add'>+	{						\</div><div class='add'>+		.thread_id = x,				\</div><div class='add'>+		.ep_config = {				\</div><div class='add'>+			.ep_type = PSIL_EP_PDMA_XY,	\</div><div class='add'>+			.pdma_acc32 = 1,		\</div><div class='add'>+			.pdma_burst = 1,		\</div><div class='add'>+		},					\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define PSIL_CSI2RX(x)					\</div><div class='add'>+	{						\</div><div class='add'>+		.thread_id = x,				\</div><div class='add'>+		.ep_config = {				\</div><div class='add'>+			.ep_type = PSIL_EP_NATIVE,	\</div><div class='add'>+		},					\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */</div><div class='add'>+static struct psil_ep am62p_src_ep_map[] = {</div><div class='add'>+	/* SAUL */</div><div class='add'>+	PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),</div><div class='add'>+	PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),</div><div class='add'>+	PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),</div><div class='add'>+	PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4301),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4302),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4303),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4304),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4305),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4306),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4307),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4308),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4309),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x430a),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x430b),</div><div class='add'>+	/* PDMA_MAIN1 - UART0-6 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4400),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4401),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4402),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4403),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4404),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4405),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0x4406),</div><div class='add'>+	/* PDMA_MAIN2 - MCASP0-2 */</div><div class='add'>+	PSIL_PDMA_MCASP(0x4500),</div><div class='add'>+	PSIL_PDMA_MCASP(0x4501),</div><div class='add'>+	PSIL_PDMA_MCASP(0x4502),</div><div class='add'>+	/* CPSW3G */</div><div class='add'>+	PSIL_ETHERNET(0x4600, 19, 19, 16),</div><div class='add'>+	/* CSI2RX */</div><div class='add'>+	PSIL_CSI2RX(0x5000),</div><div class='add'>+	PSIL_CSI2RX(0x5001),</div><div class='add'>+	PSIL_CSI2RX(0x5002),</div><div class='add'>+	PSIL_CSI2RX(0x5003),</div><div class='add'>+	PSIL_CSI2RX(0x5004),</div><div class='add'>+	PSIL_CSI2RX(0x5005),</div><div class='add'>+	PSIL_CSI2RX(0x5006),</div><div class='add'>+	PSIL_CSI2RX(0x5007),</div><div class='add'>+	PSIL_CSI2RX(0x5008),</div><div class='add'>+	PSIL_CSI2RX(0x5009),</div><div class='add'>+	PSIL_CSI2RX(0x500a),</div><div class='add'>+	PSIL_CSI2RX(0x500b),</div><div class='add'>+	PSIL_CSI2RX(0x500c),</div><div class='add'>+	PSIL_CSI2RX(0x500d),</div><div class='add'>+	PSIL_CSI2RX(0x500e),</div><div class='add'>+	PSIL_CSI2RX(0x500f),</div><div class='add'>+	PSIL_CSI2RX(0x5010),</div><div class='add'>+	PSIL_CSI2RX(0x5011),</div><div class='add'>+	PSIL_CSI2RX(0x5012),</div><div class='add'>+	PSIL_CSI2RX(0x5013),</div><div class='add'>+	PSIL_CSI2RX(0x5014),</div><div class='add'>+	PSIL_CSI2RX(0x5015),</div><div class='add'>+	PSIL_CSI2RX(0x5016),</div><div class='add'>+	PSIL_CSI2RX(0x5017),</div><div class='add'>+	PSIL_CSI2RX(0x5018),</div><div class='add'>+	PSIL_CSI2RX(0x5019),</div><div class='add'>+	PSIL_CSI2RX(0x501a),</div><div class='add'>+	PSIL_CSI2RX(0x501b),</div><div class='add'>+	PSIL_CSI2RX(0x501c),</div><div class='add'>+	PSIL_CSI2RX(0x501d),</div><div class='add'>+	PSIL_CSI2RX(0x501e),</div><div class='add'>+	PSIL_CSI2RX(0x501f),</div><div class='add'>+	PSIL_CSI2RX(0x5000),</div><div class='add'>+	PSIL_CSI2RX(0x5001),</div><div class='add'>+	PSIL_CSI2RX(0x5002),</div><div class='add'>+	PSIL_CSI2RX(0x5003),</div><div class='add'>+	PSIL_CSI2RX(0x5004),</div><div class='add'>+	PSIL_CSI2RX(0x5005),</div><div class='add'>+	PSIL_CSI2RX(0x5006),</div><div class='add'>+	PSIL_CSI2RX(0x5007),</div><div class='add'>+	PSIL_CSI2RX(0x5008),</div><div class='add'>+	PSIL_CSI2RX(0x5009),</div><div class='add'>+	PSIL_CSI2RX(0x500a),</div><div class='add'>+	PSIL_CSI2RX(0x500b),</div><div class='add'>+	PSIL_CSI2RX(0x500c),</div><div class='add'>+	PSIL_CSI2RX(0x500d),</div><div class='add'>+	PSIL_CSI2RX(0x500e),</div><div class='add'>+	PSIL_CSI2RX(0x500f),</div><div class='add'>+	PSIL_CSI2RX(0x5010),</div><div class='add'>+	PSIL_CSI2RX(0x5011),</div><div class='add'>+	PSIL_CSI2RX(0x5012),</div><div class='add'>+	PSIL_CSI2RX(0x5013),</div><div class='add'>+	PSIL_CSI2RX(0x5014),</div><div class='add'>+	PSIL_CSI2RX(0x5015),</div><div class='add'>+	PSIL_CSI2RX(0x5016),</div><div class='add'>+	PSIL_CSI2RX(0x5017),</div><div class='add'>+	PSIL_CSI2RX(0x5018),</div><div class='add'>+	PSIL_CSI2RX(0x5019),</div><div class='add'>+	PSIL_CSI2RX(0x501a),</div><div class='add'>+	PSIL_CSI2RX(0x501b),</div><div class='add'>+	PSIL_CSI2RX(0x501c),</div><div class='add'>+	PSIL_CSI2RX(0x501d),</div><div class='add'>+	PSIL_CSI2RX(0x501e),</div><div class='add'>+	PSIL_CSI2RX(0x501f),</div><div class='add'>+	/* CSIRX 1-3 (only for J722S) */</div><div class='add'>+	PSIL_CSI2RX(0x5100),</div><div class='add'>+	PSIL_CSI2RX(0x5101),</div><div class='add'>+	PSIL_CSI2RX(0x5102),</div><div class='add'>+	PSIL_CSI2RX(0x5103),</div><div class='add'>+	PSIL_CSI2RX(0x5104),</div><div class='add'>+	PSIL_CSI2RX(0x5105),</div><div class='add'>+	PSIL_CSI2RX(0x5106),</div><div class='add'>+	PSIL_CSI2RX(0x5107),</div><div class='add'>+	PSIL_CSI2RX(0x5108),</div><div class='add'>+	PSIL_CSI2RX(0x5109),</div><div class='add'>+	PSIL_CSI2RX(0x510a),</div><div class='add'>+	PSIL_CSI2RX(0x510b),</div><div class='add'>+	PSIL_CSI2RX(0x510c),</div><div class='add'>+	PSIL_CSI2RX(0x510d),</div><div class='add'>+	PSIL_CSI2RX(0x510e),</div><div class='add'>+	PSIL_CSI2RX(0x510f),</div><div class='add'>+	PSIL_CSI2RX(0x5110),</div><div class='add'>+	PSIL_CSI2RX(0x5111),</div><div class='add'>+	PSIL_CSI2RX(0x5112),</div><div class='add'>+	PSIL_CSI2RX(0x5113),</div><div class='add'>+	PSIL_CSI2RX(0x5114),</div><div class='add'>+	PSIL_CSI2RX(0x5115),</div><div class='add'>+	PSIL_CSI2RX(0x5116),</div><div class='add'>+	PSIL_CSI2RX(0x5117),</div><div class='add'>+	PSIL_CSI2RX(0x5118),</div><div class='add'>+	PSIL_CSI2RX(0x5119),</div><div class='add'>+	PSIL_CSI2RX(0x511a),</div><div class='add'>+	PSIL_CSI2RX(0x511b),</div><div class='add'>+	PSIL_CSI2RX(0x511c),</div><div class='add'>+	PSIL_CSI2RX(0x511d),</div><div class='add'>+	PSIL_CSI2RX(0x511e),</div><div class='add'>+	PSIL_CSI2RX(0x511f),</div><div class='add'>+	PSIL_CSI2RX(0x5200),</div><div class='add'>+	PSIL_CSI2RX(0x5201),</div><div class='add'>+	PSIL_CSI2RX(0x5202),</div><div class='add'>+	PSIL_CSI2RX(0x5203),</div><div class='add'>+	PSIL_CSI2RX(0x5204),</div><div class='add'>+	PSIL_CSI2RX(0x5205),</div><div class='add'>+	PSIL_CSI2RX(0x5206),</div><div class='add'>+	PSIL_CSI2RX(0x5207),</div><div class='add'>+	PSIL_CSI2RX(0x5208),</div><div class='add'>+	PSIL_CSI2RX(0x5209),</div><div class='add'>+	PSIL_CSI2RX(0x520a),</div><div class='add'>+	PSIL_CSI2RX(0x520b),</div><div class='add'>+	PSIL_CSI2RX(0x520c),</div><div class='add'>+	PSIL_CSI2RX(0x520d),</div><div class='add'>+	PSIL_CSI2RX(0x520e),</div><div class='add'>+	PSIL_CSI2RX(0x520f),</div><div class='add'>+	PSIL_CSI2RX(0x5210),</div><div class='add'>+	PSIL_CSI2RX(0x5211),</div><div class='add'>+	PSIL_CSI2RX(0x5212),</div><div class='add'>+	PSIL_CSI2RX(0x5213),</div><div class='add'>+	PSIL_CSI2RX(0x5214),</div><div class='add'>+	PSIL_CSI2RX(0x5215),</div><div class='add'>+	PSIL_CSI2RX(0x5216),</div><div class='add'>+	PSIL_CSI2RX(0x5217),</div><div class='add'>+	PSIL_CSI2RX(0x5218),</div><div class='add'>+	PSIL_CSI2RX(0x5219),</div><div class='add'>+	PSIL_CSI2RX(0x521a),</div><div class='add'>+	PSIL_CSI2RX(0x521b),</div><div class='add'>+	PSIL_CSI2RX(0x521c),</div><div class='add'>+	PSIL_CSI2RX(0x521d),</div><div class='add'>+	PSIL_CSI2RX(0x521e),</div><div class='add'>+	PSIL_CSI2RX(0x521f),</div><div class='add'>+	PSIL_CSI2RX(0x5300),</div><div class='add'>+	PSIL_CSI2RX(0x5301),</div><div class='add'>+	PSIL_CSI2RX(0x5302),</div><div class='add'>+	PSIL_CSI2RX(0x5303),</div><div class='add'>+	PSIL_CSI2RX(0x5304),</div><div class='add'>+	PSIL_CSI2RX(0x5305),</div><div class='add'>+	PSIL_CSI2RX(0x5306),</div><div class='add'>+	PSIL_CSI2RX(0x5307),</div><div class='add'>+	PSIL_CSI2RX(0x5308),</div><div class='add'>+	PSIL_CSI2RX(0x5309),</div><div class='add'>+	PSIL_CSI2RX(0x530a),</div><div class='add'>+	PSIL_CSI2RX(0x530b),</div><div class='add'>+	PSIL_CSI2RX(0x530c),</div><div class='add'>+	PSIL_CSI2RX(0x530d),</div><div class='add'>+	PSIL_CSI2RX(0x530e),</div><div class='add'>+	PSIL_CSI2RX(0x530f),</div><div class='add'>+	PSIL_CSI2RX(0x5310),</div><div class='add'>+	PSIL_CSI2RX(0x5311),</div><div class='add'>+	PSIL_CSI2RX(0x5312),</div><div class='add'>+	PSIL_CSI2RX(0x5313),</div><div class='add'>+	PSIL_CSI2RX(0x5314),</div><div class='add'>+	PSIL_CSI2RX(0x5315),</div><div class='add'>+	PSIL_CSI2RX(0x5316),</div><div class='add'>+	PSIL_CSI2RX(0x5317),</div><div class='add'>+	PSIL_CSI2RX(0x5318),</div><div class='add'>+	PSIL_CSI2RX(0x5319),</div><div class='add'>+	PSIL_CSI2RX(0x531a),</div><div class='add'>+	PSIL_CSI2RX(0x531b),</div><div class='add'>+	PSIL_CSI2RX(0x531c),</div><div class='add'>+	PSIL_CSI2RX(0x531d),</div><div class='add'>+	PSIL_CSI2RX(0x531e),</div><div class='add'>+	PSIL_CSI2RX(0x531f),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */</div><div class='add'>+static struct psil_ep am62p_dst_ep_map[] = {</div><div class='add'>+	/* SAUL */</div><div class='add'>+	PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),</div><div class='add'>+	PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),</div><div class='add'>+	/* PDMA_MAIN0 - SPI0-2 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc300),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc301),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc302),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc303),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc304),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc305),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc306),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc307),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc308),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc309),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc30a),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc30b),</div><div class='add'>+	/* PDMA_MAIN1 - UART0-6 */</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc400),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc401),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc402),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc403),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc404),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc405),</div><div class='add'>+	PSIL_PDMA_XY_PKT(0xc406),</div><div class='add'>+	/* PDMA_MAIN2 - MCASP0-2 */</div><div class='add'>+	PSIL_PDMA_MCASP(0xc500),</div><div class='add'>+	PSIL_PDMA_MCASP(0xc501),</div><div class='add'>+	PSIL_PDMA_MCASP(0xc502),</div><div class='add'>+	/* CPSW3G */</div><div class='add'>+	PSIL_ETHERNET(0xc600, 19, 19, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc601, 20, 27, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc602, 21, 35, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc603, 22, 43, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc604, 23, 51, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc605, 24, 59, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc606, 25, 67, 8),</div><div class='add'>+	PSIL_ETHERNET(0xc607, 26, 75, 8),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct psil_ep_map am62p_ep_map = {</div><div class='add'>+	.name = "am62p",</div><div class='add'>+	.src = am62p_src_ep_map,</div><div class='add'>+	.src_count = ARRAY_SIZE(am62p_src_ep_map),</div><div class='add'>+	.dst = am62p_dst_ep_map,</div><div class='add'>+	.dst_count = ARRAY_SIZE(am62p_dst_ep_map),</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h<br/>index c383723d1c8f..a577be97e344 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-priv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/k3-psil-priv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil-priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil-priv.h</a></div><div class='hunk'>@@ -45,5 +45,6 @@ extern struct psil_ep_map j721s2_ep_map;</div><div class='ctx'> extern struct psil_ep_map am62_ep_map;</div><div class='ctx'> extern struct psil_ep_map am62a_ep_map;</div><div class='ctx'> extern struct psil_ep_map j784s4_ep_map;</div><div class='add'>+extern struct psil_ep_map am62p_ep_map;</div><div class='ctx'> </div><div class='ctx'> #endif /* K3_PSIL_PRIV_H_ */</div><div class='head'>diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c<br/>index c11389d67a3f..25148d952472 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/k3-psil.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-psil.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-psil.c</a></div><div class='hunk'>@@ -26,6 +26,8 @@ static const struct soc_device_attribute k3_soc_devices[] = {</div><div class='ctx'> 	{ .family = "AM62X", .data = &amp;am62_ep_map },</div><div class='ctx'> 	{ .family = "AM62AX", .data = &amp;am62a_ep_map },</div><div class='ctx'> 	{ .family = "J784S4", .data = &amp;j784s4_ep_map },</div><div class='add'>+	{ .family = "AM62PX", .data = &amp;am62p_ep_map },</div><div class='add'>+	{ .family = "J722S", .data = &amp;am62p_ep_map },</div><div class='ctx'> 	{ /* sentinel */ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c<br/>index 30fd2f386f36..2841a539c264 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-udma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/ti/k3-udma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/ti/k3-udma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/ti/k3-udma.c</a></div><div class='hunk'>@@ -4441,6 +4441,8 @@ static const struct soc_device_attribute k3_soc_devices[] = {</div><div class='ctx'> 	{ .family = "AM62X", .data = &amp;am64_soc_data },</div><div class='ctx'> 	{ .family = "AM62AX", .data = &amp;am64_soc_data },</div><div class='ctx'> 	{ .family = "J784S4", .data = &amp;j721e_soc_data },</div><div class='add'>+	{ .family = "AM62PX", .data = &amp;am64_soc_data },</div><div class='add'>+	{ .family = "J722S", .data = &amp;am64_soc_data },</div><div class='ctx'> 	{ /* sentinel */ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dma/uniphier-mdmac.c b/drivers/dma/uniphier-mdmac.c<br/>index 618839df0748..ad7125f6e2ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/uniphier-mdmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/uniphier-mdmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/uniphier-mdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/uniphier-mdmac.c</a></div><div class='hunk'>@@ -453,7 +453,7 @@ disable_clk:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uniphier_mdmac_remove(struct platform_device *pdev)</div><div class='add'>+static void uniphier_mdmac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct uniphier_mdmac_device *mdev = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct dma_chan *chan;</div><div class='hunk'>@@ -468,16 +468,21 @@ static int uniphier_mdmac_remove(struct platform_device *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(chan, &amp;mdev-&gt;ddev.channels, device_node) {</div><div class='ctx'> 		ret = dmaengine_terminate_sync(chan);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * This results in resource leakage and maybe also</div><div class='add'>+			 * use-after-free errors as e.g. *mdev is kfreed.</div><div class='add'>+			 */</div><div class='add'>+			dev_alert(&amp;pdev-&gt;dev, "Failed to terminate channel %d (%pe)\n",</div><div class='add'>+				  chan-&gt;chan_id, ERR_PTR(ret));</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 		uniphier_mdmac_free_chan_resources(chan);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='ctx'> 	dma_async_device_unregister(&amp;mdev-&gt;ddev);</div><div class='ctx'> 	clk_disable_unprepare(mdev-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id uniphier_mdmac_match[] = {</div><div class='hunk'>@@ -488,7 +493,7 @@ MODULE_DEVICE_TABLE(of, uniphier_mdmac_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver uniphier_mdmac_driver = {</div><div class='ctx'> 	.probe = uniphier_mdmac_probe,</div><div class='del'>-	.remove = uniphier_mdmac_remove,</div><div class='add'>+	.remove_new = uniphier_mdmac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "uniphier-mio-dmac",</div><div class='ctx'> 		.of_match_table = uniphier_mdmac_match,</div><div class='head'>diff --git a/drivers/dma/uniphier-xdmac.c b/drivers/dma/uniphier-xdmac.c<br/>index 3a8ee2b173b5..3ce2dc2ad9de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/uniphier-xdmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/uniphier-xdmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/uniphier-xdmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/uniphier-xdmac.c</a></div><div class='hunk'>@@ -563,7 +563,7 @@ out_unregister_dmac:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int uniphier_xdmac_remove(struct platform_device *pdev)</div><div class='add'>+static void uniphier_xdmac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct uniphier_xdmac_device *xdev = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct dma_device *ddev = &amp;xdev-&gt;ddev;</div><div class='hunk'>@@ -579,15 +579,20 @@ static int uniphier_xdmac_remove(struct platform_device *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(chan, &amp;ddev-&gt;channels, device_node) {</div><div class='ctx'> 		ret = dmaengine_terminate_sync(chan);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * This results in resource leakage and maybe also</div><div class='add'>+			 * use-after-free errors as e.g. *xdev is kfreed.</div><div class='add'>+			 */</div><div class='add'>+			dev_alert(&amp;pdev-&gt;dev, "Failed to terminate channel %d (%pe)\n",</div><div class='add'>+				  chan-&gt;chan_id, ERR_PTR(ret));</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 		uniphier_xdmac_free_chan_resources(chan);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	of_dma_controller_free(pdev-&gt;dev.of_node);</div><div class='ctx'> 	dma_async_device_unregister(ddev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id uniphier_xdmac_match[] = {</div><div class='hunk'>@@ -598,7 +603,7 @@ MODULE_DEVICE_TABLE(of, uniphier_xdmac_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver uniphier_xdmac_driver = {</div><div class='ctx'> 	.probe = uniphier_xdmac_probe,</div><div class='del'>-	.remove = uniphier_xdmac_remove,</div><div class='add'>+	.remove_new = uniphier_xdmac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "uniphier-xdmac",</div><div class='ctx'> 		.of_match_table = uniphier_xdmac_match,</div><div class='head'>diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h<br/>index e641a5083e14..98f5f6fb9ff9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xdma-regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/xilinx/xdma-regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xdma-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xdma-regs.h</a></div><div class='hunk'>@@ -64,9 +64,10 @@ struct xdma_hw_desc {</div><div class='ctx'> 	__le64		next_desc;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define XDMA_DESC_SIZE		sizeof(struct xdma_hw_desc)</div><div class='del'>-#define XDMA_DESC_BLOCK_SIZE	(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)</div><div class='del'>-#define XDMA_DESC_BLOCK_ALIGN	4096</div><div class='add'>+#define XDMA_DESC_SIZE			sizeof(struct xdma_hw_desc)</div><div class='add'>+#define XDMA_DESC_BLOCK_SIZE		(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)</div><div class='add'>+#define XDMA_DESC_BLOCK_ALIGN		32</div><div class='add'>+#define XDMA_DESC_BLOCK_BOUNDARY	4096</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Channel registers</div><div class='hunk'>@@ -76,6 +77,7 @@ struct xdma_hw_desc {</div><div class='ctx'> #define XDMA_CHAN_CONTROL_W1S		0x8</div><div class='ctx'> #define XDMA_CHAN_CONTROL_W1C		0xc</div><div class='ctx'> #define XDMA_CHAN_STATUS		0x40</div><div class='add'>+#define XDMA_CHAN_STATUS_RC		0x44</div><div class='ctx'> #define XDMA_CHAN_COMPLETED_DESC	0x48</div><div class='ctx'> #define XDMA_CHAN_ALIGNMENTS		0x4c</div><div class='ctx'> #define XDMA_CHAN_INTR_ENABLE		0x90</div><div class='hunk'>@@ -101,6 +103,7 @@ struct xdma_hw_desc {</div><div class='ctx'> #define CHAN_CTRL_IE_MAGIC_STOPPED		BIT(4)</div><div class='ctx'> #define CHAN_CTRL_IE_IDLE_STOPPED		BIT(6)</div><div class='ctx'> #define CHAN_CTRL_IE_READ_ERROR			GENMASK(13, 9)</div><div class='add'>+#define CHAN_CTRL_IE_WRITE_ERROR		GENMASK(18, 14)</div><div class='ctx'> #define CHAN_CTRL_IE_DESC_ERROR			GENMASK(23, 19)</div><div class='ctx'> #define CHAN_CTRL_NON_INCR_ADDR			BIT(25)</div><div class='ctx'> #define CHAN_CTRL_POLL_MODE_WB			BIT(26)</div><div class='hunk'>@@ -111,8 +114,17 @@ struct xdma_hw_desc {</div><div class='ctx'> 			 CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |		\</div><div class='ctx'> 			 CHAN_CTRL_IE_MAGIC_STOPPED |			\</div><div class='ctx'> 			 CHAN_CTRL_IE_READ_ERROR |			\</div><div class='add'>+			 CHAN_CTRL_IE_WRITE_ERROR |			\</div><div class='ctx'> 			 CHAN_CTRL_IE_DESC_ERROR)</div><div class='ctx'> </div><div class='add'>+#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START</div><div class='add'>+</div><div class='add'>+#define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |	\</div><div class='add'>+			      CHAN_CTRL_IE_MAGIC_STOPPED |		\</div><div class='add'>+			      CHAN_CTRL_IE_READ_ERROR |			\</div><div class='add'>+			      CHAN_CTRL_IE_WRITE_ERROR |		\</div><div class='add'>+			      CHAN_CTRL_IE_DESC_ERROR)</div><div class='add'>+</div><div class='ctx'> /* bits of the channel interrupt enable mask */</div><div class='ctx'> #define CHAN_IM_DESC_ERROR			BIT(19)</div><div class='ctx'> #define CHAN_IM_READ_ERROR			BIT(9)</div><div class='hunk'>@@ -134,18 +146,6 @@ struct xdma_hw_desc {</div><div class='ctx'> #define XDMA_SGDMA_DESC_ADJ	0x4088</div><div class='ctx'> #define XDMA_SGDMA_DESC_CREDIT	0x408c</div><div class='ctx'> </div><div class='del'>-/* bits of the SG DMA control register */</div><div class='del'>-#define XDMA_CTRL_RUN_STOP			BIT(0)</div><div class='del'>-#define XDMA_CTRL_IE_DESC_STOPPED		BIT(1)</div><div class='del'>-#define XDMA_CTRL_IE_DESC_COMPLETED		BIT(2)</div><div class='del'>-#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH	BIT(3)</div><div class='del'>-#define XDMA_CTRL_IE_MAGIC_STOPPED		BIT(4)</div><div class='del'>-#define XDMA_CTRL_IE_IDLE_STOPPED		BIT(6)</div><div class='del'>-#define XDMA_CTRL_IE_READ_ERROR			GENMASK(13, 9)</div><div class='del'>-#define XDMA_CTRL_IE_DESC_ERROR			GENMASK(23, 19)</div><div class='del'>-#define XDMA_CTRL_NON_INCR_ADDR			BIT(25)</div><div class='del'>-#define XDMA_CTRL_POLL_MODE_WB			BIT(26)</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * interrupt registers</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c<br/>index 84a88029226f..170017ff2aad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/xilinx/xdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xdma.c</a></div><div class='hunk'>@@ -78,27 +78,31 @@ struct xdma_chan {</div><div class='ctx'>  * @vdesc: Virtual DMA descriptor</div><div class='ctx'>  * @chan: DMA channel pointer</div><div class='ctx'>  * @dir: Transferring direction of the request</div><div class='del'>- * @dev_addr: Physical address on DMA device side</div><div class='ctx'>  * @desc_blocks: Hardware descriptor blocks</div><div class='ctx'>  * @dblk_num: Number of hardware descriptor blocks</div><div class='ctx'>  * @desc_num: Number of hardware descriptors</div><div class='ctx'>  * @completed_desc_num: Completed hardware descriptors</div><div class='ctx'>  * @cyclic: Cyclic transfer vs. scatter-gather</div><div class='add'>+ * @interleaved_dma: Interleaved DMA transfer</div><div class='ctx'>  * @periods: Number of periods in the cyclic transfer</div><div class='ctx'>  * @period_size: Size of a period in bytes in cyclic transfers</div><div class='add'>+ * @frames_left: Number of frames left in interleaved DMA transfer</div><div class='add'>+ * @error: tx error flag</div><div class='ctx'>  */</div><div class='ctx'> struct xdma_desc {</div><div class='ctx'> 	struct virt_dma_desc		vdesc;</div><div class='ctx'> 	struct xdma_chan		*chan;</div><div class='ctx'> 	enum dma_transfer_direction	dir;</div><div class='del'>-	u64				dev_addr;</div><div class='ctx'> 	struct xdma_desc_block		*desc_blocks;</div><div class='ctx'> 	u32				dblk_num;</div><div class='ctx'> 	u32				desc_num;</div><div class='ctx'> 	u32				completed_desc_num;</div><div class='ctx'> 	bool				cyclic;</div><div class='add'>+	bool				interleaved_dma;</div><div class='ctx'> 	u32				periods;</div><div class='ctx'> 	u32				period_size;</div><div class='add'>+	u32				frames_left;</div><div class='add'>+	bool				error;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define XDMA_DEV_STATUS_REG_DMA		BIT(0)</div><div class='hunk'>@@ -276,6 +280,7 @@ xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num, bool cyclic)</div><div class='ctx'> 	sw_desc-&gt;chan = chan;</div><div class='ctx'> 	sw_desc-&gt;desc_num = desc_num;</div><div class='ctx'> 	sw_desc-&gt;cyclic = cyclic;</div><div class='add'>+	sw_desc-&gt;error = false;</div><div class='ctx'> 	dblk_num = DIV_ROUND_UP(desc_num, XDMA_DESC_ADJACENT);</div><div class='ctx'> 	sw_desc-&gt;desc_blocks = kcalloc(dblk_num, sizeof(*sw_desc-&gt;desc_blocks),</div><div class='ctx'> 				       GFP_NOWAIT);</div><div class='hunk'>@@ -371,6 +376,31 @@ static int xdma_xfer_start(struct xdma_chan *xchan)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	xchan-&gt;busy = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xdma_xfer_stop - Stop DMA transfer</div><div class='add'>+ * @xchan: DMA channel pointer</div><div class='add'>+ */</div><div class='add'>+static int xdma_xfer_stop(struct xdma_chan *xchan)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 val;</div><div class='add'>+	struct xdma_device *xdev = xchan-&gt;xdev_hdl;</div><div class='add'>+</div><div class='add'>+	/* clear run stop bit to prevent any further auto-triggering */</div><div class='add'>+	ret = regmap_write(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_CONTROL_W1C,</div><div class='add'>+			   CHAN_CTRL_RUN_STOP);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Clear the channel status register */</div><div class='add'>+	ret = regmap_read(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_STATUS_RC, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -476,6 +506,84 @@ static void xdma_issue_pending(struct dma_chan *chan)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * xdma_terminate_all - Terminate all transactions</div><div class='add'>+ * @chan: DMA channel pointer</div><div class='add'>+ */</div><div class='add'>+static int xdma_terminate_all(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct xdma_chan *xdma_chan = to_xdma_chan(chan);</div><div class='add'>+	struct virt_dma_desc *vd;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	LIST_HEAD(head);</div><div class='add'>+</div><div class='add'>+	xdma_xfer_stop(xdma_chan);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;xdma_chan-&gt;vchan.lock, flags);</div><div class='add'>+</div><div class='add'>+	xdma_chan-&gt;busy = false;</div><div class='add'>+	vd = vchan_next_desc(&amp;xdma_chan-&gt;vchan);</div><div class='add'>+	if (vd) {</div><div class='add'>+		list_del(&amp;vd-&gt;node);</div><div class='add'>+		dma_cookie_complete(&amp;vd-&gt;tx);</div><div class='add'>+		vchan_terminate_vdesc(vd);</div><div class='add'>+	}</div><div class='add'>+	vchan_get_all_descriptors(&amp;xdma_chan-&gt;vchan, &amp;head);</div><div class='add'>+	list_splice_tail(&amp;head, &amp;xdma_chan-&gt;vchan.desc_terminated);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;xdma_chan-&gt;vchan.lock, flags);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xdma_synchronize - Synchronize terminated transactions</div><div class='add'>+ * @chan: DMA channel pointer</div><div class='add'>+ */</div><div class='add'>+static void xdma_synchronize(struct dma_chan *chan)</div><div class='add'>+{</div><div class='add'>+	struct xdma_chan *xdma_chan = to_xdma_chan(chan);</div><div class='add'>+</div><div class='add'>+	vchan_synchronize(&amp;xdma_chan-&gt;vchan);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xdma_fill_descs - Fill hardware descriptors with contiguous memory block addresses</div><div class='add'>+ * @sw_desc: tx descriptor state container</div><div class='add'>+ * @src_addr: Value for a -&gt;src_addr field of a first descriptor</div><div class='add'>+ * @dst_addr: Value for a -&gt;dst_addr field of a first descriptor</div><div class='add'>+ * @size: Total size of a contiguous memory block</div><div class='add'>+ * @filled_descs_num: Number of filled hardware descriptors for corresponding sw_desc</div><div class='add'>+ */</div><div class='add'>+static inline u32 xdma_fill_descs(struct xdma_desc *sw_desc, u64 src_addr,</div><div class='add'>+				  u64 dst_addr, u32 size, u32 filled_descs_num)</div><div class='add'>+{</div><div class='add'>+	u32 left = size, len, desc_num = filled_descs_num;</div><div class='add'>+	struct xdma_desc_block *dblk;</div><div class='add'>+	struct xdma_hw_desc *desc;</div><div class='add'>+</div><div class='add'>+	dblk = sw_desc-&gt;desc_blocks + (desc_num / XDMA_DESC_ADJACENT);</div><div class='add'>+	desc = dblk-&gt;virt_addr;</div><div class='add'>+	desc += desc_num &amp; XDMA_DESC_ADJACENT_MASK;</div><div class='add'>+	do {</div><div class='add'>+		len = min_t(u32, left, XDMA_DESC_BLEN_MAX);</div><div class='add'>+		/* set hardware descriptor */</div><div class='add'>+		desc-&gt;bytes = cpu_to_le32(len);</div><div class='add'>+		desc-&gt;src_addr = cpu_to_le64(src_addr);</div><div class='add'>+		desc-&gt;dst_addr = cpu_to_le64(dst_addr);</div><div class='add'>+		if (!(++desc_num &amp; XDMA_DESC_ADJACENT_MASK))</div><div class='add'>+			desc = (++dblk)-&gt;virt_addr;</div><div class='add'>+		else</div><div class='add'>+			desc++;</div><div class='add'>+</div><div class='add'>+		src_addr += len;</div><div class='add'>+		dst_addr += len;</div><div class='add'>+		left -= len;</div><div class='add'>+	} while (left);</div><div class='add'>+</div><div class='add'>+	return desc_num - filled_descs_num;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * xdma_prep_device_sg - prepare a descriptor for a DMA transaction</div><div class='ctx'>  * @chan: DMA channel pointer</div><div class='ctx'>  * @sgl: Transfer scatter gather list</div><div class='hunk'>@@ -491,13 +599,10 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl,</div><div class='ctx'> {</div><div class='ctx'> 	struct xdma_chan *xdma_chan = to_xdma_chan(chan);</div><div class='ctx'> 	struct dma_async_tx_descriptor *tx_desc;</div><div class='del'>-	u32 desc_num = 0, i, len, rest;</div><div class='del'>-	struct xdma_desc_block *dblk;</div><div class='del'>-	struct xdma_hw_desc *desc;</div><div class='ctx'> 	struct xdma_desc *sw_desc;</div><div class='del'>-	u64 dev_addr, *src, *dst;</div><div class='add'>+	u32 desc_num = 0, i;</div><div class='add'>+	u64 addr, dev_addr, *src, *dst;</div><div class='ctx'> 	struct scatterlist *sg;</div><div class='del'>-	u64 addr;</div><div class='ctx'> </div><div class='ctx'> 	for_each_sg(sgl, sg, sg_len, i)</div><div class='ctx'> 		desc_num += DIV_ROUND_UP(sg_dma_len(sg), XDMA_DESC_BLEN_MAX);</div><div class='hunk'>@@ -506,6 +611,8 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl,</div><div class='ctx'> 	if (!sw_desc)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	sw_desc-&gt;dir = dir;</div><div class='add'>+	sw_desc-&gt;cyclic = false;</div><div class='add'>+	sw_desc-&gt;interleaved_dma = false;</div><div class='ctx'> </div><div class='ctx'> 	if (dir == DMA_MEM_TO_DEV) {</div><div class='ctx'> 		dev_addr = xdma_chan-&gt;cfg.dst_addr;</div><div class='hunk'>@@ -517,32 +624,11 @@ xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl,</div><div class='ctx'> 		dst = &amp;addr;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dblk = sw_desc-&gt;desc_blocks;</div><div class='del'>-	desc = dblk-&gt;virt_addr;</div><div class='del'>-	desc_num = 1;</div><div class='add'>+	desc_num = 0;</div><div class='ctx'> 	for_each_sg(sgl, sg, sg_len, i) {</div><div class='ctx'> 		addr = sg_dma_address(sg);</div><div class='del'>-		rest = sg_dma_len(sg);</div><div class='del'>-</div><div class='del'>-		do {</div><div class='del'>-			len = min_t(u32, rest, XDMA_DESC_BLEN_MAX);</div><div class='del'>-			/* set hardware descriptor */</div><div class='del'>-			desc-&gt;bytes = cpu_to_le32(len);</div><div class='del'>-			desc-&gt;src_addr = cpu_to_le64(*src);</div><div class='del'>-			desc-&gt;dst_addr = cpu_to_le64(*dst);</div><div class='del'>-</div><div class='del'>-			if (!(desc_num &amp; XDMA_DESC_ADJACENT_MASK)) {</div><div class='del'>-				dblk++;</div><div class='del'>-				desc = dblk-&gt;virt_addr;</div><div class='del'>-			} else {</div><div class='del'>-				desc++;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			desc_num++;</div><div class='del'>-			dev_addr += len;</div><div class='del'>-			addr += len;</div><div class='del'>-			rest -= len;</div><div class='del'>-		} while (rest);</div><div class='add'>+		desc_num += xdma_fill_descs(sw_desc, *src, *dst, sg_dma_len(sg), desc_num);</div><div class='add'>+		dev_addr += sg_dma_len(sg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	tx_desc = vchan_tx_prep(&amp;xdma_chan-&gt;vchan, &amp;sw_desc-&gt;vdesc, flags);</div><div class='hunk'>@@ -576,9 +662,9 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address,</div><div class='ctx'> 	struct xdma_device *xdev = xdma_chan-&gt;xdev_hdl;</div><div class='ctx'> 	unsigned int periods = size / period_size;</div><div class='ctx'> 	struct dma_async_tx_descriptor *tx_desc;</div><div class='del'>-	struct xdma_desc_block *dblk;</div><div class='del'>-	struct xdma_hw_desc *desc;</div><div class='ctx'> 	struct xdma_desc *sw_desc;</div><div class='add'>+	u64 addr, dev_addr, *src, *dst;</div><div class='add'>+	u32 desc_num;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -602,22 +688,23 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address,</div><div class='ctx'> 	sw_desc-&gt;periods = periods;</div><div class='ctx'> 	sw_desc-&gt;period_size = period_size;</div><div class='ctx'> 	sw_desc-&gt;dir = dir;</div><div class='add'>+	sw_desc-&gt;interleaved_dma = false;</div><div class='ctx'> </div><div class='del'>-	dblk = sw_desc-&gt;desc_blocks;</div><div class='del'>-	desc = dblk-&gt;virt_addr;</div><div class='add'>+	addr = address;</div><div class='add'>+	if (dir == DMA_MEM_TO_DEV) {</div><div class='add'>+		dev_addr = xdma_chan-&gt;cfg.dst_addr;</div><div class='add'>+		src = &amp;addr;</div><div class='add'>+		dst = &amp;dev_addr;</div><div class='add'>+	} else {</div><div class='add'>+		dev_addr = xdma_chan-&gt;cfg.src_addr;</div><div class='add'>+		src = &amp;dev_addr;</div><div class='add'>+		dst = &amp;addr;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* fill hardware descriptor */</div><div class='add'>+	desc_num = 0;</div><div class='ctx'> 	for (i = 0; i &lt; periods; i++) {</div><div class='del'>-		desc-&gt;bytes = cpu_to_le32(period_size);</div><div class='del'>-		if (dir == DMA_MEM_TO_DEV) {</div><div class='del'>-			desc-&gt;src_addr = cpu_to_le64(address + i * period_size);</div><div class='del'>-			desc-&gt;dst_addr = cpu_to_le64(xdma_chan-&gt;cfg.dst_addr);</div><div class='del'>-		} else {</div><div class='del'>-			desc-&gt;src_addr = cpu_to_le64(xdma_chan-&gt;cfg.src_addr);</div><div class='del'>-			desc-&gt;dst_addr = cpu_to_le64(address + i * period_size);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		desc++;</div><div class='add'>+		desc_num += xdma_fill_descs(sw_desc, *src, *dst, period_size, desc_num);</div><div class='add'>+		addr += i * period_size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	tx_desc = vchan_tx_prep(&amp;xdma_chan-&gt;vchan, &amp;sw_desc-&gt;vdesc, flags);</div><div class='hunk'>@@ -633,6 +720,57 @@ failed:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * xdma_prep_interleaved_dma - Prepare virtual descriptor for interleaved DMA transfers</div><div class='add'>+ * @chan: DMA channel</div><div class='add'>+ * @xt: DMA transfer template</div><div class='add'>+ * @flags: tx flags</div><div class='add'>+ */</div><div class='add'>+static struct dma_async_tx_descriptor *</div><div class='add'>+xdma_prep_interleaved_dma(struct dma_chan *chan,</div><div class='add'>+			  struct dma_interleaved_template *xt,</div><div class='add'>+			  unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	u32 desc_num = 0, period_size = 0;</div><div class='add'>+	struct dma_async_tx_descriptor *tx_desc;</div><div class='add'>+	struct xdma_chan *xchan = to_xdma_chan(chan);</div><div class='add'>+	struct xdma_desc *sw_desc;</div><div class='add'>+	u64 src_addr, dst_addr;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xt-&gt;frame_size; ++i)</div><div class='add'>+		desc_num += DIV_ROUND_UP(xt-&gt;sgl[i].size, XDMA_DESC_BLEN_MAX);</div><div class='add'>+</div><div class='add'>+	sw_desc = xdma_alloc_desc(xchan, desc_num, false);</div><div class='add'>+	if (!sw_desc)</div><div class='add'>+		return NULL;</div><div class='add'>+	sw_desc-&gt;dir = xt-&gt;dir;</div><div class='add'>+	sw_desc-&gt;interleaved_dma = true;</div><div class='add'>+	sw_desc-&gt;cyclic = flags &amp; DMA_PREP_REPEAT;</div><div class='add'>+	sw_desc-&gt;frames_left = xt-&gt;numf;</div><div class='add'>+	sw_desc-&gt;periods = xt-&gt;numf;</div><div class='add'>+</div><div class='add'>+	desc_num = 0;</div><div class='add'>+	src_addr = xt-&gt;src_start;</div><div class='add'>+	dst_addr = xt-&gt;dst_start;</div><div class='add'>+	for (i = 0; i &lt; xt-&gt;frame_size; ++i) {</div><div class='add'>+		desc_num += xdma_fill_descs(sw_desc, src_addr, dst_addr, xt-&gt;sgl[i].size, desc_num);</div><div class='add'>+		src_addr += dmaengine_get_src_icg(xt, &amp;xt-&gt;sgl[i]) + (xt-&gt;src_inc ?</div><div class='add'>+							      xt-&gt;sgl[i].size : 0);</div><div class='add'>+		dst_addr += dmaengine_get_dst_icg(xt, &amp;xt-&gt;sgl[i]) + (xt-&gt;dst_inc ?</div><div class='add'>+							      xt-&gt;sgl[i].size : 0);</div><div class='add'>+		period_size += xt-&gt;sgl[i].size;</div><div class='add'>+	}</div><div class='add'>+	sw_desc-&gt;period_size = period_size;</div><div class='add'>+</div><div class='add'>+	tx_desc = vchan_tx_prep(&amp;xchan-&gt;vchan, &amp;sw_desc-&gt;vdesc, flags);</div><div class='add'>+	if (tx_desc)</div><div class='add'>+		return tx_desc;</div><div class='add'>+</div><div class='add'>+	xdma_free_desc(&amp;sw_desc-&gt;vdesc);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * xdma_device_config - Configure the DMA channel</div><div class='ctx'>  * @chan: DMA channel</div><div class='ctx'>  * @cfg: channel configuration</div><div class='hunk'>@@ -677,9 +815,8 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	xdma_chan-&gt;desc_pool = dma_pool_create(dma_chan_name(chan),</div><div class='del'>-					       dev, XDMA_DESC_BLOCK_SIZE,</div><div class='del'>-					       XDMA_DESC_BLOCK_ALIGN, 0);</div><div class='add'>+	xdma_chan-&gt;desc_pool = dma_pool_create(dma_chan_name(chan), dev, XDMA_DESC_BLOCK_SIZE,</div><div class='add'>+					       XDMA_DESC_BLOCK_ALIGN, XDMA_DESC_BLOCK_BOUNDARY);</div><div class='ctx'> 	if (!xdma_chan-&gt;desc_pool) {</div><div class='ctx'> 		xdma_err(xdev, "unable to allocate descriptor pool");</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -706,20 +843,20 @@ static enum dma_status xdma_tx_status(struct dma_chan *chan, dma_cookie_t cookie</div><div class='ctx'> 	spin_lock_irqsave(&amp;xdma_chan-&gt;vchan.lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	vd = vchan_find_desc(&amp;xdma_chan-&gt;vchan, cookie);</div><div class='del'>-	if (vd)</div><div class='del'>-		desc = to_xdma_desc(vd);</div><div class='del'>-	if (!desc || !desc-&gt;cyclic) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;xdma_chan-&gt;vchan.lock, flags);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	period_idx = desc-&gt;completed_desc_num % desc-&gt;periods;</div><div class='del'>-	residue = (desc-&gt;periods - period_idx) * desc-&gt;period_size;</div><div class='add'>+	if (!vd)</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='add'>+	desc = to_xdma_desc(vd);</div><div class='add'>+	if (desc-&gt;error) {</div><div class='add'>+		ret = DMA_ERROR;</div><div class='add'>+	} else if (desc-&gt;cyclic) {</div><div class='add'>+		period_idx = desc-&gt;completed_desc_num % desc-&gt;periods;</div><div class='add'>+		residue = (desc-&gt;periods - period_idx) * desc-&gt;period_size;</div><div class='add'>+		dma_set_residue(state, residue);</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;xdma_chan-&gt;vchan.lock, flags);</div><div class='ctx'> </div><div class='del'>-	dma_set_residue(state, residue);</div><div class='del'>-</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -732,11 +869,12 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct xdma_chan *xchan = dev_id;</div><div class='ctx'> 	u32 complete_desc_num = 0;</div><div class='del'>-	struct xdma_device *xdev;</div><div class='del'>-	struct virt_dma_desc *vd;</div><div class='add'>+	struct xdma_device *xdev = xchan-&gt;xdev_hdl;</div><div class='add'>+	struct virt_dma_desc *vd, *next_vd;</div><div class='ctx'> 	struct xdma_desc *desc;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u32 st;</div><div class='add'>+	bool repeat_tx;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;xchan-&gt;vchan.lock);</div><div class='ctx'> </div><div class='hunk'>@@ -745,45 +883,76 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id)</div><div class='ctx'> 	if (!vd)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	xchan-&gt;busy = false;</div><div class='add'>+	/* Clear-on-read the status register */</div><div class='add'>+	ret = regmap_read(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_STATUS_RC, &amp;st);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	desc = to_xdma_desc(vd);</div><div class='del'>-	xdev = xchan-&gt;xdev_hdl;</div><div class='add'>+</div><div class='add'>+	st &amp;= XDMA_CHAN_STATUS_MASK;</div><div class='add'>+	if ((st &amp; XDMA_CHAN_ERROR_MASK) ||</div><div class='add'>+	    !(st &amp; (CHAN_CTRL_IE_DESC_COMPLETED | CHAN_CTRL_IE_DESC_STOPPED))) {</div><div class='add'>+		desc-&gt;error = true;</div><div class='add'>+		xdma_err(xdev, "channel error, status register value: 0x%x", st);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_read(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_COMPLETED_DESC,</div><div class='ctx'> 			  &amp;complete_desc_num);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	desc-&gt;completed_desc_num += complete_desc_num;</div><div class='add'>+	if (desc-&gt;interleaved_dma) {</div><div class='add'>+		xchan-&gt;busy = false;</div><div class='add'>+		desc-&gt;completed_desc_num += complete_desc_num;</div><div class='add'>+		if (complete_desc_num == XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT) {</div><div class='add'>+			xdma_xfer_start(xchan);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (desc-&gt;cyclic) {</div><div class='del'>-		ret = regmap_read(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_STATUS,</div><div class='del'>-				  &amp;st);</div><div class='del'>-		if (ret)</div><div class='add'>+		/* last desc of any frame */</div><div class='add'>+		desc-&gt;frames_left--;</div><div class='add'>+		if (desc-&gt;frames_left)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		/* last desc of the last frame  */</div><div class='add'>+		repeat_tx = vd-&gt;tx.flags &amp; DMA_PREP_REPEAT;</div><div class='add'>+		next_vd = list_first_entry_or_null(&amp;vd-&gt;node, struct virt_dma_desc, node);</div><div class='add'>+		if (next_vd)</div><div class='add'>+			repeat_tx = repeat_tx &amp;&amp; !(next_vd-&gt;tx.flags &amp; DMA_PREP_LOAD_EOT);</div><div class='add'>+		if (repeat_tx) {</div><div class='add'>+			desc-&gt;frames_left = desc-&gt;periods;</div><div class='add'>+			desc-&gt;completed_desc_num = 0;</div><div class='add'>+			vchan_cyclic_callback(vd);</div><div class='add'>+		} else {</div><div class='add'>+			list_del(&amp;vd-&gt;node);</div><div class='add'>+			vchan_cookie_complete(vd);</div><div class='add'>+		}</div><div class='add'>+		/* start (or continue) the tx of a first desc on the vc.desc_issued list, if any */</div><div class='add'>+		xdma_xfer_start(xchan);</div><div class='add'>+	} else if (!desc-&gt;cyclic) {</div><div class='add'>+		xchan-&gt;busy = false;</div><div class='add'>+		desc-&gt;completed_desc_num += complete_desc_num;</div><div class='add'>+</div><div class='add'>+		/* if all data blocks are transferred, remove and complete the request */</div><div class='add'>+		if (desc-&gt;completed_desc_num == desc-&gt;desc_num) {</div><div class='add'>+			list_del(&amp;vd-&gt;node);</div><div class='add'>+			vchan_cookie_complete(vd);</div><div class='ctx'> 			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		regmap_write(xdev-&gt;rmap, xchan-&gt;base + XDMA_CHAN_STATUS, st);</div><div class='add'>+		if (desc-&gt;completed_desc_num &gt; desc-&gt;desc_num ||</div><div class='add'>+		    complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT)</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='add'>+		/* transfer the rest of data */</div><div class='add'>+		xdma_xfer_start(xchan);</div><div class='add'>+	} else {</div><div class='add'>+		desc-&gt;completed_desc_num = complete_desc_num;</div><div class='ctx'> 		vchan_cyclic_callback(vd);</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * if all data blocks are transferred, remove and complete the request</div><div class='del'>-	 */</div><div class='del'>-	if (desc-&gt;completed_desc_num == desc-&gt;desc_num) {</div><div class='del'>-		list_del(&amp;vd-&gt;node);</div><div class='del'>-		vchan_cookie_complete(vd);</div><div class='del'>-		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (desc-&gt;completed_desc_num &gt; desc-&gt;desc_num ||</div><div class='del'>-	    complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT)</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	/* transfer the rest of data (SG only) */</div><div class='del'>-	xdma_xfer_start(xchan);</div><div class='del'>-</div><div class='ctx'> out:</div><div class='ctx'> 	spin_unlock(&amp;xchan-&gt;vchan.lock);</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='hunk'>@@ -1080,6 +1249,9 @@ static int xdma_probe(struct platform_device *pdev)</div><div class='ctx'> 	dma_cap_set(DMA_SLAVE, xdev-&gt;dma_dev.cap_mask);</div><div class='ctx'> 	dma_cap_set(DMA_PRIVATE, xdev-&gt;dma_dev.cap_mask);</div><div class='ctx'> 	dma_cap_set(DMA_CYCLIC, xdev-&gt;dma_dev.cap_mask);</div><div class='add'>+	dma_cap_set(DMA_INTERLEAVE, xdev-&gt;dma_dev.cap_mask);</div><div class='add'>+	dma_cap_set(DMA_REPEAT, xdev-&gt;dma_dev.cap_mask);</div><div class='add'>+	dma_cap_set(DMA_LOAD_EOT, xdev-&gt;dma_dev.cap_mask);</div><div class='ctx'> </div><div class='ctx'> 	xdev-&gt;dma_dev.dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	xdev-&gt;dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;</div><div class='hunk'>@@ -1089,10 +1261,13 @@ static int xdma_probe(struct platform_device *pdev)</div><div class='ctx'> 	xdev-&gt;dma_dev.device_prep_slave_sg = xdma_prep_device_sg;</div><div class='ctx'> 	xdev-&gt;dma_dev.device_config = xdma_device_config;</div><div class='ctx'> 	xdev-&gt;dma_dev.device_issue_pending = xdma_issue_pending;</div><div class='add'>+	xdev-&gt;dma_dev.device_terminate_all = xdma_terminate_all;</div><div class='add'>+	xdev-&gt;dma_dev.device_synchronize = xdma_synchronize;</div><div class='ctx'> 	xdev-&gt;dma_dev.filter.map = pdata-&gt;device_map;</div><div class='ctx'> 	xdev-&gt;dma_dev.filter.mapcnt = pdata-&gt;device_map_cnt;</div><div class='ctx'> 	xdev-&gt;dma_dev.filter.fn = xdma_filter_fn;</div><div class='ctx'> 	xdev-&gt;dma_dev.device_prep_dma_cyclic = xdma_prep_dma_cyclic;</div><div class='add'>+	xdev-&gt;dma_dev.device_prep_interleaved_dma = xdma_prep_interleaved_dma;</div><div class='ctx'> </div><div class='ctx'> 	ret = dma_async_device_register(&amp;xdev-&gt;dma_dev);</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c<br/>index 69587d85a7cd..b82815e64d24 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xilinx_dpdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dma/xilinx/xilinx_dpdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dma/xilinx/xilinx_dpdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dma/xilinx/xilinx_dpdma.c</a></div><div class='hunk'>@@ -309,7 +309,7 @@ static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)</div><div class='ctx'> </div><div class='ctx'> 	out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR);</div><div class='ctx'> 	out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE,</div><div class='del'>-			    out_str_len);</div><div class='add'>+			    out_str_len + 1);</div><div class='ctx'> 	snprintf(buf, out_str_len, "%d",</div><div class='ctx'> 		 dpdma_debugfs.xilinx_dpdma_irq_done_count);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c<br/>index 3568149b9562..1eca8cc271f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dpll/dpll_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dpll/dpll_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dpll/dpll_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dpll/dpll_core.c</a></div><div class='hunk'>@@ -22,7 +22,8 @@ DEFINE_MUTEX(dpll_lock);</div><div class='ctx'> DEFINE_XARRAY_FLAGS(dpll_device_xa, XA_FLAGS_ALLOC);</div><div class='ctx'> DEFINE_XARRAY_FLAGS(dpll_pin_xa, XA_FLAGS_ALLOC);</div><div class='ctx'> </div><div class='del'>-static u32 dpll_xa_id;</div><div class='add'>+static u32 dpll_device_xa_id;</div><div class='add'>+static u32 dpll_pin_xa_id;</div><div class='ctx'> </div><div class='ctx'> #define ASSERT_DPLL_REGISTERED(d)	\</div><div class='ctx'> 	WARN_ON_ONCE(!xa_get_mark(&amp;dpll_device_xa, (d)-&gt;id, DPLL_REGISTERED))</div><div class='hunk'>@@ -246,7 +247,7 @@ dpll_device_alloc(const u64 clock_id, u32 device_idx, struct module *module)</div><div class='ctx'> 	dpll-&gt;clock_id = clock_id;</div><div class='ctx'> 	dpll-&gt;module = module;</div><div class='ctx'> 	ret = xa_alloc_cyclic(&amp;dpll_device_xa, &amp;dpll-&gt;id, dpll, xa_limit_32b,</div><div class='del'>-			      &amp;dpll_xa_id, GFP_KERNEL);</div><div class='add'>+			      &amp;dpll_device_xa_id, GFP_KERNEL);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		kfree(dpll);</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='hunk'>@@ -446,7 +447,8 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,</div><div class='ctx'> 	refcount_set(&amp;pin-&gt;refcount, 1);</div><div class='ctx'> 	xa_init_flags(&amp;pin-&gt;dpll_refs, XA_FLAGS_ALLOC);</div><div class='ctx'> 	xa_init_flags(&amp;pin-&gt;parent_refs, XA_FLAGS_ALLOC);</div><div class='del'>-	ret = xa_alloc(&amp;dpll_pin_xa, &amp;pin-&gt;id, pin, xa_limit_16b, GFP_KERNEL);</div><div class='add'>+	ret = xa_alloc_cyclic(&amp;dpll_pin_xa, &amp;pin-&gt;id, pin, xa_limit_32b,</div><div class='add'>+			      &amp;dpll_pin_xa_id, GFP_KERNEL);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	return pin;</div><div class='head'>diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c<br/>index 442a0ebeb953..3370dbddb86b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/dpll/dpll_netlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/dpll/dpll_netlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/dpll/dpll_netlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/dpll/dpll_netlink.c</a></div><div class='hunk'>@@ -101,13 +101,17 @@ dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll,</div><div class='ctx'> {</div><div class='ctx'> 	const struct dpll_device_ops *ops = dpll_device_ops(dpll);</div><div class='ctx'> 	enum dpll_mode mode;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!ops-&gt;mode_supported)</div><div class='del'>-		return 0;</div><div class='del'>-	for (mode = DPLL_MODE_MANUAL; mode &lt;= DPLL_MODE_MAX; mode++)</div><div class='del'>-		if (ops-&gt;mode_supported(dpll, dpll_priv(dpll), mode, extack))</div><div class='del'>-			if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode))</div><div class='del'>-				return -EMSGSIZE;</div><div class='add'>+	/* No mode change is supported now, so the only supported mode is the</div><div class='add'>+	 * one obtained by mode_get().</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	ret = ops-&gt;mode_get(dpll, dpll_priv(dpll), &amp;mode, extack);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode))</div><div class='add'>+		return -EMSGSIZE;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -259,6 +263,27 @@ dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin,</div><div class='add'>+			    struct dpll_pin_ref *ref,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	const struct dpll_pin_ops *ops = dpll_pin_ops(ref);</div><div class='add'>+	struct dpll_device *dpll = ref-&gt;dpll;</div><div class='add'>+	s64 ffo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!ops-&gt;ffo_get)</div><div class='add'>+		return 0;</div><div class='add'>+	ret = ops-&gt;ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin),</div><div class='add'>+			   dpll, dpll_priv(dpll), &amp;ffo, extack);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (ret == -ENODATA)</div><div class='add'>+			return 0;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, ffo);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int</div><div class='ctx'> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,</div><div class='ctx'> 		      struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)</div><div class='hunk'>@@ -438,6 +463,9 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,</div><div class='ctx'> 	ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='add'>+	ret = dpll_msg_add_ffo(msg, pin, ref, extack);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> 	if (xa_empty(&amp;pin-&gt;parent_refs))</div><div class='ctx'> 		ret = dpll_msg_add_pin_dplls(msg, pin, extack);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -925,7 +953,6 @@ dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest,</div><div class='ctx'> 			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct nlattr *tb[DPLL_A_PIN_MAX + 1];</div><div class='del'>-	enum dpll_pin_state state;</div><div class='ctx'> 	u32 ppin_idx;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -936,10 +963,14 @@ dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> 	ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]);</div><div class='del'>-	state = nla_get_u32(tb[DPLL_A_PIN_STATE]);</div><div class='del'>-	ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+</div><div class='add'>+	if (tb[DPLL_A_PIN_STATE]) {</div><div class='add'>+		enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]);</div><div class='add'>+</div><div class='add'>+		ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c<br/>index 8b31cd54bdb6..ae17ce4d9722 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/altera_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/altera_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/altera_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/altera_edac.c</a></div><div class='hunk'>@@ -22,6 +22,7 @@</div><div class='ctx'> #include &lt;linux/of_platform.h&gt;</div><div class='ctx'> #include &lt;linux/panic_notifier.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='hunk'>@@ -279,7 +280,6 @@ release:</div><div class='ctx'> </div><div class='ctx'> static int altr_sdram_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *id;</div><div class='ctx'> 	struct edac_mc_layer layers[2];</div><div class='ctx'> 	struct mem_ctl_info *mci;</div><div class='ctx'> 	struct altr_sdram_mc_data *drvdata;</div><div class='hunk'>@@ -290,10 +290,6 @@ static int altr_sdram_probe(struct platform_device *pdev)</div><div class='ctx'> 	int irq, irq2, res = 0;</div><div class='ctx'> 	unsigned long mem_size, irqflags = 0;</div><div class='ctx'> </div><div class='del'>-	id = of_match_device(altr_sdram_ctrl_of_match, &amp;pdev-&gt;dev);</div><div class='del'>-	if (!id)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='ctx'> 	/* Grab the register range from the sdr controller in device tree */</div><div class='ctx'> 	mc_vbase = syscon_regmap_lookup_by_phandle(pdev-&gt;dev.of_node,</div><div class='ctx'> 						   "altr,sdr-syscon");</div><div class='hunk'>@@ -304,8 +300,7 @@ static int altr_sdram_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check specific dependencies for the module */</div><div class='del'>-	priv = of_match_node(altr_sdram_ctrl_of_match,</div><div class='del'>-			     pdev-&gt;dev.of_node)-&gt;data;</div><div class='add'>+	priv = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	/* Validate the SDRAM controller has ECC enabled */</div><div class='ctx'> 	if (regmap_read(mc_vbase, priv-&gt;ecc_ctrl_offset, &amp;read_reg) ||</div><div class='hunk'>@@ -459,15 +454,13 @@ free:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int altr_sdram_remove(struct platform_device *pdev)</div><div class='add'>+static void altr_sdram_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='ctx'> 	platform_set_drvdata(pdev, NULL);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -489,7 +482,7 @@ static const struct dev_pm_ops altr_sdram_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver altr_sdram_edac_driver = {</div><div class='ctx'> 	.probe = altr_sdram_probe,</div><div class='del'>-	.remove = altr_sdram_remove,</div><div class='add'>+	.remove_new = altr_sdram_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "altr_sdram_edac",</div><div class='ctx'> #ifdef CONFIG_PM</div><div class='hunk'>@@ -812,7 +805,7 @@ fail:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int altr_edac_device_remove(struct platform_device *pdev)</div><div class='add'>+static void altr_edac_device_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct altr_edac_device_dev *drvdata = dci-&gt;pvt_info;</div><div class='hunk'>@@ -820,13 +813,11 @@ static int altr_edac_device_remove(struct platform_device *pdev)</div><div class='ctx'> 	debugfs_remove_recursive(drvdata-&gt;debugfs_dir);</div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(dci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver altr_edac_device_driver = {</div><div class='ctx'> 	.probe =  altr_edac_device_probe,</div><div class='del'>-	.remove = altr_edac_device_remove,</div><div class='add'>+	.remove_new = altr_edac_device_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "altr_edac_device",</div><div class='ctx'> 		.of_match_table = altr_edac_device_of_match,</div><div class='head'>diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c<br/>index 9b6642d00871..537b9987a431 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/amd64_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/amd64_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/amd64_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/amd64_edac.c</a></div><div class='hunk'>@@ -996,15 +996,23 @@ static struct local_node_map {</div><div class='ctx'> #define LNTM_NODE_COUNT				GENMASK(27, 16)</div><div class='ctx'> #define LNTM_BASE_NODE_ID			GENMASK(11, 0)</div><div class='ctx'> </div><div class='del'>-static int gpu_get_node_map(void)</div><div class='add'>+static int gpu_get_node_map(struct amd64_pvt *pvt)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u32 tmp;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Node ID 0 is reserved for CPUs.</div><div class='del'>-	 * Therefore, a non-zero Node ID means we've already cached the values.</div><div class='add'>+	 * Mapping of nodes from hardware-provided AMD Node ID to a</div><div class='add'>+	 * Linux logical one is applicable for MI200 models. Therefore,</div><div class='add'>+	 * return early for other heterogeneous systems.</div><div class='add'>+	 */</div><div class='add'>+	if (pvt-&gt;F3-&gt;device != PCI_DEVICE_ID_AMD_MI200_DF_F3)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID</div><div class='add'>+	 * means the values have been already cached.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (gpu_node_map.base_node_id)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -3851,7 +3859,7 @@ static void gpu_init_csrows(struct mem_ctl_info *mci)</div><div class='ctx'> </div><div class='ctx'> 			dimm-&gt;nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs);</div><div class='ctx'> 			dimm-&gt;edac_mode = EDAC_SECDED;</div><div class='del'>-			dimm-&gt;mtype = MEM_HBM2;</div><div class='add'>+			dimm-&gt;mtype = pvt-&gt;dram_type;</div><div class='ctx'> 			dimm-&gt;dtype = DEV_X16;</div><div class='ctx'> 			dimm-&gt;grain = 64;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3880,7 +3888,7 @@ static bool gpu_ecc_enabled(struct amd64_pvt *pvt)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline u32 gpu_get_umc_base(u8 umc, u8 channel)</div><div class='add'>+static inline u32 gpu_get_umc_base(struct amd64_pvt *pvt, u8 umc, u8 channel)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * On CPUs, there is one channel per UMC, so UMC numbering equals</div><div class='hunk'>@@ -3893,13 +3901,16 @@ static inline u32 gpu_get_umc_base(u8 umc, u8 channel)</div><div class='ctx'> 	 * On GPU nodes channels are selected in 3rd nibble</div><div class='ctx'> 	 * HBM chX[3:0]= [Y  ]5X[3:0]000;</div><div class='ctx'> 	 * HBM chX[7:4]= [Y+1]5X[3:0]000</div><div class='add'>+	 *</div><div class='add'>+	 * On MI300 APU nodes, same as GPU nodes but channels are selected</div><div class='add'>+	 * in the base address of 0x90000</div><div class='ctx'> 	 */</div><div class='ctx'> 	umc *= 2;</div><div class='ctx'> </div><div class='ctx'> 	if (channel &gt;= 4)</div><div class='ctx'> 		umc++;</div><div class='ctx'> </div><div class='del'>-	return 0x50000 + (umc &lt;&lt; 20) + ((channel % 4) &lt;&lt; 12);</div><div class='add'>+	return pvt-&gt;gpu_umc_base + (umc &lt;&lt; 20) + ((channel % 4) &lt;&lt; 12);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gpu_read_mc_regs(struct amd64_pvt *pvt)</div><div class='hunk'>@@ -3910,7 +3921,7 @@ static void gpu_read_mc_regs(struct amd64_pvt *pvt)</div><div class='ctx'> </div><div class='ctx'> 	/* Read registers from each UMC */</div><div class='ctx'> 	for_each_umc(i) {</div><div class='del'>-		umc_base = gpu_get_umc_base(i, 0);</div><div class='add'>+		umc_base = gpu_get_umc_base(pvt, i, 0);</div><div class='ctx'> 		umc = &amp;pvt-&gt;umc[i];</div><div class='ctx'> </div><div class='ctx'> 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &amp;umc-&gt;umc_cfg);</div><div class='hunk'>@@ -3927,7 +3938,7 @@ static void gpu_read_base_mask(struct amd64_pvt *pvt)</div><div class='ctx'> </div><div class='ctx'> 	for_each_umc(umc) {</div><div class='ctx'> 		for_each_chip_select(cs, umc, pvt) {</div><div class='del'>-			base_reg = gpu_get_umc_base(umc, cs) + UMCCH_BASE_ADDR;</div><div class='add'>+			base_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_BASE_ADDR;</div><div class='ctx'> 			base = &amp;pvt-&gt;csels[umc].csbases[cs];</div><div class='ctx'> </div><div class='ctx'> 			if (!amd_smn_read(pvt-&gt;mc_node_id, base_reg, base)) {</div><div class='hunk'>@@ -3935,7 +3946,7 @@ static void gpu_read_base_mask(struct amd64_pvt *pvt)</div><div class='ctx'> 					 umc, cs, *base, base_reg);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			mask_reg = gpu_get_umc_base(umc, cs) + UMCCH_ADDR_MASK;</div><div class='add'>+			mask_reg = gpu_get_umc_base(pvt, umc, cs) + UMCCH_ADDR_MASK;</div><div class='ctx'> 			mask = &amp;pvt-&gt;csels[umc].csmasks[cs];</div><div class='ctx'> </div><div class='ctx'> 			if (!amd_smn_read(pvt-&gt;mc_node_id, mask_reg, mask)) {</div><div class='hunk'>@@ -3960,7 +3971,7 @@ static int gpu_hw_info_get(struct amd64_pvt *pvt)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = gpu_get_node_map();</div><div class='add'>+	ret = gpu_get_node_map(pvt);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -4125,6 +4136,8 @@ static int per_family_init(struct amd64_pvt *pvt)</div><div class='ctx'> 			if (pvt-&gt;F3-&gt;device == PCI_DEVICE_ID_AMD_MI200_DF_F3) {</div><div class='ctx'> 				pvt-&gt;ctl_name		= "MI200";</div><div class='ctx'> 				pvt-&gt;max_mcs		= 4;</div><div class='add'>+				pvt-&gt;dram_type		= MEM_HBM2;</div><div class='add'>+				pvt-&gt;gpu_umc_base	= 0x50000;</div><div class='ctx'> 				pvt-&gt;ops		= &amp;gpu_ops;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				pvt-&gt;ctl_name		= "F19h_M30h";</div><div class='hunk'>@@ -4142,6 +4155,13 @@ static int per_family_init(struct amd64_pvt *pvt)</div><div class='ctx'> 			pvt-&gt;ctl_name			= "F19h_M70h";</div><div class='ctx'> 			pvt-&gt;flags.zn_regs_v2		= 1;</div><div class='ctx'> 			break;</div><div class='add'>+		case 0x90 ... 0x9f:</div><div class='add'>+			pvt-&gt;ctl_name			= "F19h_M90h";</div><div class='add'>+			pvt-&gt;max_mcs			= 4;</div><div class='add'>+			pvt-&gt;dram_type			= MEM_HBM3;</div><div class='add'>+			pvt-&gt;gpu_umc_base		= 0x90000;</div><div class='add'>+			pvt-&gt;ops			= &amp;gpu_ops;</div><div class='add'>+			break;</div><div class='ctx'> 		case 0xa0 ... 0xaf:</div><div class='ctx'> 			pvt-&gt;ctl_name			= "F19h_MA0h";</div><div class='ctx'> 			pvt-&gt;max_mcs			= 12;</div><div class='hunk'>@@ -4180,23 +4200,33 @@ static const struct attribute_group *amd64_edac_attr_groups[] = {</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * For heterogeneous and APU models EDAC CHIP_SELECT and CHANNEL layers</div><div class='add'>+ * should be swapped to fit into the layers.</div><div class='add'>+ */</div><div class='add'>+static unsigned int get_layer_size(struct amd64_pvt *pvt, u8 layer)</div><div class='add'>+{</div><div class='add'>+	bool is_gpu = (pvt-&gt;ops == &amp;gpu_ops);</div><div class='add'>+</div><div class='add'>+	if (!layer)</div><div class='add'>+		return is_gpu ? pvt-&gt;max_mcs</div><div class='add'>+			      : pvt-&gt;csels[0].b_cnt;</div><div class='add'>+	else</div><div class='add'>+		return is_gpu ? pvt-&gt;csels[0].b_cnt</div><div class='add'>+			      : pvt-&gt;max_mcs;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int init_one_instance(struct amd64_pvt *pvt)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = NULL;</div><div class='ctx'> 	struct edac_mc_layer layers[2];</div><div class='ctx'> 	int ret = -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * For Heterogeneous family EDAC CHIP_SELECT and CHANNEL layers should</div><div class='del'>-	 * be swapped to fit into the layers.</div><div class='del'>-	 */</div><div class='ctx'> 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;</div><div class='del'>-	layers[0].size = (pvt-&gt;F3-&gt;device == PCI_DEVICE_ID_AMD_MI200_DF_F3) ?</div><div class='del'>-			 pvt-&gt;max_mcs : pvt-&gt;csels[0].b_cnt;</div><div class='add'>+	layers[0].size = get_layer_size(pvt, 0);</div><div class='ctx'> 	layers[0].is_virt_csrow = true;</div><div class='ctx'> 	layers[1].type = EDAC_MC_LAYER_CHANNEL;</div><div class='del'>-	layers[1].size = (pvt-&gt;F3-&gt;device == PCI_DEVICE_ID_AMD_MI200_DF_F3) ?</div><div class='del'>-			 pvt-&gt;csels[0].b_cnt : pvt-&gt;max_mcs;</div><div class='add'>+	layers[1].size = get_layer_size(pvt, 1);</div><div class='ctx'> 	layers[1].is_virt_csrow = false;</div><div class='ctx'> </div><div class='ctx'> 	mci = edac_mc_alloc(pvt-&gt;mc_node_id, ARRAY_SIZE(layers), layers, 0);</div><div class='head'>diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h<br/>index 5a4e4a59682b..1665f7932bac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/amd64_edac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/amd64_edac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/amd64_edac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/amd64_edac.h</a></div><div class='hunk'>@@ -362,6 +362,7 @@ struct amd64_pvt {</div><div class='ctx'> 	u32 dct_sel_lo;		/* DRAM Controller Select Low */</div><div class='ctx'> 	u32 dct_sel_hi;		/* DRAM Controller Select High */</div><div class='ctx'> 	u32 online_spare;	/* On-Line spare Reg */</div><div class='add'>+	u32 gpu_umc_base;	/* Base address used for channel selection on GPUs */</div><div class='ctx'> </div><div class='ctx'> 	/* x4, x8, or x16 syndromes in use */</div><div class='ctx'> 	u8 ecc_sym_sz;</div><div class='head'>diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c<br/>index c4bd2fb9c46b..25517c99b3ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/armada_xp_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/armada_xp_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/armada_xp_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/armada_xp_edac.c</a></div><div class='hunk'>@@ -5,7 +5,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/edac.h&gt;</div><div class='del'>-#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/hardware/cache-l2x0.h&gt;</div><div class='ctx'> #include &lt;asm/hardware/cache-aurora-l2.h&gt;</div><div class='hunk'>@@ -351,20 +353,18 @@ static int axp_mc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int axp_mc_remove(struct platform_device *pdev)</div><div class='add'>+static void axp_mc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='ctx'> 	platform_set_drvdata(pdev, NULL);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver axp_mc_driver = {</div><div class='ctx'> 	.probe = axp_mc_probe,</div><div class='del'>-	.remove = axp_mc_remove,</div><div class='add'>+	.remove_new = axp_mc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "armada_xp_mc_edac",</div><div class='ctx'> 		.of_match_table = of_match_ptr(axp_mc_of_match),</div><div class='hunk'>@@ -564,7 +564,7 @@ static int aurora_l2_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aurora_l2_remove(struct platform_device *pdev)</div><div class='add'>+static void aurora_l2_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);</div><div class='ctx'> #ifdef CONFIG_EDAC_DEBUG</div><div class='hunk'>@@ -575,13 +575,11 @@ static int aurora_l2_remove(struct platform_device *pdev)</div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(dci);</div><div class='ctx'> 	platform_set_drvdata(pdev, NULL);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver aurora_l2_driver = {</div><div class='ctx'> 	.probe = aurora_l2_probe,</div><div class='del'>-	.remove = aurora_l2_remove,</div><div class='add'>+	.remove_new = aurora_l2_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "aurora_l2_edac",</div><div class='ctx'> 		.of_match_table = of_match_ptr(aurora_l2_of_match),</div><div class='head'>diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c<br/>index 6bd5f8815919..157a480eb761 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/aspeed_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/aspeed_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/aspeed_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/aspeed_edac.c</a></div><div class='hunk'>@@ -357,7 +357,7 @@ probe_exit02:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-static int aspeed_remove(struct platform_device *pdev)</div><div class='add'>+static void aspeed_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci;</div><div class='ctx'> </div><div class='hunk'>@@ -369,8 +369,6 @@ static int aspeed_remove(struct platform_device *pdev)</div><div class='ctx'> 	mci = edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	if (mci)</div><div class='ctx'> 		edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -389,7 +387,7 @@ static struct platform_driver aspeed_driver = {</div><div class='ctx'> 		.of_match_table = aspeed_of_match</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= aspeed_probe,</div><div class='del'>-	.remove		= aspeed_remove</div><div class='add'>+	.remove_new	= aspeed_remove</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(aspeed_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/edac/bluefield_edac.c b/drivers/edac/bluefield_edac.c<br/>index e4736eb37bfb..5b3164560648 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/bluefield_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/bluefield_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/bluefield_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/bluefield_edac.c</a></div><div class='hunk'>@@ -323,14 +323,12 @@ err:</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bluefield_edac_mc_remove(struct platform_device *pdev)</div><div class='add'>+static void bluefield_edac_mc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct acpi_device_id bluefield_mc_acpi_ids[] = {</div><div class='hunk'>@@ -346,7 +344,7 @@ static struct platform_driver bluefield_edac_mc_driver = {</div><div class='ctx'> 		.acpi_match_table = bluefield_mc_acpi_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = bluefield_edac_mc_probe,</div><div class='del'>-	.remove = bluefield_edac_mc_remove,</div><div class='add'>+	.remove_new = bluefield_edac_mc_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(bluefield_edac_mc_driver);</div><div class='head'>diff --git a/drivers/edac/cell_edac.c b/drivers/edac/cell_edac.c<br/>index bc1f3416400e..2000f66fbf5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/cell_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/cell_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/cell_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/cell_edac.c</a></div><div class='hunk'>@@ -234,12 +234,11 @@ static int cell_edac_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cell_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void cell_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	if (mci)</div><div class='ctx'> 		edac_mc_free(mci);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver cell_edac_driver = {</div><div class='hunk'>@@ -247,7 +246,7 @@ static struct platform_driver cell_edac_driver = {</div><div class='ctx'> 		.name	= "cbe-mic",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= cell_edac_probe,</div><div class='del'>-	.remove		= cell_edac_remove,</div><div class='add'>+	.remove_new	= cell_edac_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init cell_edac_init(void)</div><div class='head'>diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c<br/>index 9797e6d60dde..5075dc7526e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/cpc925_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/cpc925_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/cpc925_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/cpc925_edac.c</a></div><div class='hunk'>@@ -1010,7 +1010,7 @@ out:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cpc925_remove(struct platform_device *pdev)</div><div class='add'>+static void cpc925_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1023,13 +1023,11 @@ static int cpc925_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver cpc925_edac_driver = {</div><div class='ctx'> 	.probe = cpc925_probe,</div><div class='del'>-	.remove = cpc925_remove,</div><div class='add'>+	.remove_new = cpc925_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "cpc925_edac",</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/edac/dmc520_edac.c b/drivers/edac/dmc520_edac.c<br/>index 1fa5ca57e9ec..4e30b989a1a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/dmc520_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/dmc520_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/dmc520_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/dmc520_edac.c</a></div><div class='hunk'>@@ -602,7 +602,7 @@ err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dmc520_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void dmc520_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 reg_val, idx, irq_mask_all = 0;</div><div class='ctx'> 	struct mem_ctl_info *mci;</div><div class='hunk'>@@ -626,8 +626,6 @@ static int dmc520_edac_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id dmc520_edac_driver_id[] = {</div><div class='hunk'>@@ -644,7 +642,7 @@ static struct platform_driver dmc520_edac_driver = {</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='ctx'> 	.probe = dmc520_edac_probe,</div><div class='del'>-	.remove = dmc520_edac_remove</div><div class='add'>+	.remove_new = dmc520_edac_remove</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(dmc520_edac_driver);</div><div class='head'>diff --git a/drivers/edac/edac_device.h b/drivers/edac/edac_device.h<br/>index 3f44e6b9d387..7db22a4c83ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/edac_device.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/edac_device.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/edac_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_device.h</a></div><div class='hunk'>@@ -176,7 +176,7 @@ struct edac_device_ctl_info {</div><div class='ctx'> 	struct edac_dev_sysfs_attribute *sysfs_attributes;</div><div class='ctx'> </div><div class='ctx'> 	/* pointer to main 'edac' subsys in sysfs */</div><div class='del'>-	struct bus_type *edac_subsys;</div><div class='add'>+	const struct bus_type *edac_subsys;</div><div class='ctx'> </div><div class='ctx'> 	/* the internal state of this controller instance */</div><div class='ctx'> 	int op_state;</div><div class='head'>diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c<br/>index 010c26be5846..237a542e045a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/edac_device_sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/edac_device_sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/edac_device_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_device_sysfs.c</a></div><div class='hunk'>@@ -229,7 +229,7 @@ static struct kobj_type ktype_device_ctrl = {</div><div class='ctx'> int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev_root;</div><div class='del'>-	struct bus_type *edac_subsys;</div><div class='add'>+	const struct bus_type *edac_subsys;</div><div class='ctx'> 	int err = -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	edac_dbg(1, "\n");</div><div class='head'>diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c<br/>index 6faeb2ab3960..d6eed727b0cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/edac_mc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/edac_mc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/edac_mc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_mc.c</a></div><div class='hunk'>@@ -166,6 +166,7 @@ const char * const edac_mem_types[] = {</div><div class='ctx'> 	[MEM_NVDIMM]	= "Non-volatile-RAM",</div><div class='ctx'> 	[MEM_WIO2]	= "Wide-IO-2",</div><div class='ctx'> 	[MEM_HBM2]	= "High-bandwidth-memory-Gen2",</div><div class='add'>+	[MEM_HBM3]	= "High-bandwidth-memory-Gen3",</div><div class='ctx'> };</div><div class='ctx'> EXPORT_SYMBOL_GPL(edac_mem_types);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/edac/edac_module.c b/drivers/edac/edac_module.c<br/>index 32a931d0cb71..1c9f62382666 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/edac_module.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/edac_module.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/edac_module.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_module.c</a></div><div class='hunk'>@@ -67,7 +67,7 @@ char *edac_op_state_to_string(int opstate)</div><div class='ctx'>  * sysfs object: /sys/devices/system/edac</div><div class='ctx'>  *	need to export to other files</div><div class='ctx'>  */</div><div class='del'>-static struct bus_type edac_subsys = {</div><div class='add'>+static const struct bus_type edac_subsys = {</div><div class='ctx'> 	.name = "edac",</div><div class='ctx'> 	.dev_name = "edac",</div><div class='ctx'> };</div><div class='hunk'>@@ -90,7 +90,7 @@ static void edac_subsys_exit(void)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* return pointer to the 'edac' node in sysfs */</div><div class='del'>-struct bus_type *edac_get_sysfs_subsys(void)</div><div class='add'>+const struct bus_type *edac_get_sysfs_subsys(void)</div><div class='ctx'> {</div><div class='ctx'> 	return &amp;edac_subsys;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c<br/>index 287cc51dbc86..7b44afcf48db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/edac_pci_sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/edac_pci_sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/edac_pci_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/edac_pci_sysfs.c</a></div><div class='hunk'>@@ -338,7 +338,7 @@ static struct kobj_type ktype_edac_pci_main_kobj = {</div><div class='ctx'> static int edac_pci_main_kobj_setup(void)</div><div class='ctx'> {</div><div class='ctx'> 	int err = -ENODEV;</div><div class='del'>-	struct bus_type *edac_subsys;</div><div class='add'>+	const struct bus_type *edac_subsys;</div><div class='ctx'> 	struct device *dev_root;</div><div class='ctx'> </div><div class='ctx'> 	edac_dbg(0, "\n");</div><div class='hunk'>@@ -521,7 +521,7 @@ static void edac_pci_dev_parity_clear(struct pci_dev *dev)</div><div class='ctx'> 	/* read the device TYPE, looking for bridges */</div><div class='ctx'> 	pci_read_config_byte(dev, PCI_HEADER_TYPE, &amp;header_type);</div><div class='ctx'> </div><div class='del'>-	if ((header_type &amp; 0x7F) == PCI_HEADER_TYPE_BRIDGE)</div><div class='add'>+	if ((header_type &amp; PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE)</div><div class='ctx'> 		get_pci_parity_status(dev, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -583,7 +583,7 @@ static void edac_pci_dev_parity_test(struct pci_dev *dev)</div><div class='ctx'> 	edac_dbg(4, "PCI HEADER TYPE= 0x%02x %s\n",</div><div class='ctx'> 		 header_type, dev_name(&amp;dev-&gt;dev));</div><div class='ctx'> </div><div class='del'>-	if ((header_type &amp; 0x7F) == PCI_HEADER_TYPE_BRIDGE) {</div><div class='add'>+	if ((header_type &amp; PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) {</div><div class='ctx'> 		/* On bridges, need to examine secondary status register  */</div><div class='ctx'> 		status = get_pci_parity_status(dev, 1);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c<br/>index b81757555a8a..d148d262d0d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/fsl_ddr_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/fsl_ddr_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/fsl_ddr_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/fsl_ddr_edac.c</a></div><div class='hunk'>@@ -612,7 +612,7 @@ err:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int fsl_mc_err_remove(struct platform_device *op)</div><div class='add'>+void fsl_mc_err_remove(struct platform_device *op)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = dev_get_drvdata(&amp;op-&gt;dev);</div><div class='ctx'> 	struct fsl_mc_pdata *pdata = mci-&gt;pvt_info;</div><div class='hunk'>@@ -629,5 +629,4 @@ int fsl_mc_err_remove(struct platform_device *op)</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;op-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h<br/>index 332439d7b2d9..c0994a2a003c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/fsl_ddr_edac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/fsl_ddr_edac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/fsl_ddr_edac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/fsl_ddr_edac.h</a></div><div class='hunk'>@@ -72,5 +72,5 @@ struct fsl_mc_pdata {</div><div class='ctx'> 	int irq;</div><div class='ctx'> };</div><div class='ctx'> int fsl_mc_err_probe(struct platform_device *op);</div><div class='del'>-int fsl_mc_err_remove(struct platform_device *op);</div><div class='add'>+void fsl_mc_err_remove(struct platform_device *op);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/edac/highbank_l2_edac.c b/drivers/edac/highbank_l2_edac.c<br/>index 140d4431bd0d..5646c049a934 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/highbank_l2_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/highbank_l2_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/highbank_l2_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/highbank_l2_edac.c</a></div><div class='hunk'>@@ -118,18 +118,17 @@ err:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int highbank_l2_err_remove(struct platform_device *pdev)</div><div class='add'>+static void highbank_l2_err_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(dci);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver highbank_l2_edac_driver = {</div><div class='ctx'> 	.probe = highbank_l2_err_probe,</div><div class='del'>-	.remove = highbank_l2_err_remove,</div><div class='add'>+	.remove_new = highbank_l2_err_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "hb_l2_edac",</div><div class='ctx'> 		.of_match_table = hb_l2_err_of_match,</div><div class='head'>diff --git a/drivers/edac/highbank_mc_edac.c b/drivers/edac/highbank_mc_edac.c<br/>index a0c04a7f95e9..1c5b888ab11d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/highbank_mc_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/highbank_mc_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/highbank_mc_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/highbank_mc_edac.c</a></div><div class='hunk'>@@ -251,18 +251,17 @@ free:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int highbank_mc_remove(struct platform_device *pdev)</div><div class='add'>+static void highbank_mc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver highbank_mc_edac_driver = {</div><div class='ctx'> 	.probe = highbank_mc_probe,</div><div class='del'>-	.remove = highbank_mc_remove,</div><div class='add'>+	.remove_new = highbank_mc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "hb_mc_edac",</div><div class='ctx'> 		.of_match_table = hb_ddr_ctrl_of_match,</div><div class='head'>diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c<br/>index 23d25724bae4..91e0a88ef904 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/i7core_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/i7core_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/i7core_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/i7core_edac.c</a></div><div class='hunk'>@@ -376,7 +376,7 @@ static const struct pci_id_table pci_dev_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -385,7 +385,7 @@ static const struct pci_id_table pci_dev_table[] = {</div><div class='ctx'> static const struct pci_device_id i7core_pci_tbl[] = {</div><div class='ctx'> 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},</div><div class='ctx'> 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ 0, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /****************************************************************************</div><div class='head'>diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c<br/>index 1a18693294db..2b0ecdeba5cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/igen6_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/igen6_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/igen6_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/igen6_edac.c</a></div><div class='hunk'>@@ -58,6 +58,7 @@</div><div class='ctx'> /* Capability register E */</div><div class='ctx'> #define CAPID_E_OFFSET			0xf0</div><div class='ctx'> #define CAPID_E_IBECC			BIT(12)</div><div class='add'>+#define CAPID_E_IBECC_BIT18		BIT(18)</div><div class='ctx'> </div><div class='ctx'> /* Error Status */</div><div class='ctx'> #define ERRSTS_OFFSET			0xc8</div><div class='hunk'>@@ -80,6 +81,7 @@</div><div class='ctx'> #define ECC_ERROR_LOG_UE		BIT_ULL(63)</div><div class='ctx'> #define ECC_ERROR_LOG_ADDR_SHIFT	5</div><div class='ctx'> #define ECC_ERROR_LOG_ADDR(v)		GET_BITFIELD(v, 5, 38)</div><div class='add'>+#define ECC_ERROR_LOG_ADDR45(v)		GET_BITFIELD(v, 5, 45)</div><div class='ctx'> #define ECC_ERROR_LOG_SYND(v)		GET_BITFIELD(v, 46, 61)</div><div class='ctx'> </div><div class='ctx'> /* Host MMIO base address */</div><div class='hunk'>@@ -133,6 +135,8 @@ static struct res_config {</div><div class='ctx'> 	u32 ibecc_base;</div><div class='ctx'> 	u32 ibecc_error_log_offset;</div><div class='ctx'> 	bool (*ibecc_available)(struct pci_dev *pdev);</div><div class='add'>+	/* Extract error address logged in IBECC */</div><div class='add'>+	u64 (*err_addr)(u64 ecclog);</div><div class='ctx'> 	/* Convert error address logged in IBECC to system physical address */</div><div class='ctx'> 	u64 (*err_addr_to_sys_addr)(u64 eaddr, int mc);</div><div class='ctx'> 	/* Convert error address logged in IBECC to integrated memory controller address */</div><div class='hunk'>@@ -222,6 +226,67 @@ static struct work_struct ecclog_work;</div><div class='ctx'> #define DID_ADL_SKU3	0x4621</div><div class='ctx'> #define DID_ADL_SKU4	0x4641</div><div class='ctx'> </div><div class='add'>+/* Compute die IDs for Alder Lake-N with IBECC */</div><div class='add'>+#define DID_ADL_N_SKU1	0x4614</div><div class='add'>+#define DID_ADL_N_SKU2	0x4617</div><div class='add'>+#define DID_ADL_N_SKU3	0x461b</div><div class='add'>+#define DID_ADL_N_SKU4	0x461c</div><div class='add'>+#define DID_ADL_N_SKU5	0x4673</div><div class='add'>+#define DID_ADL_N_SKU6	0x4674</div><div class='add'>+#define DID_ADL_N_SKU7	0x4675</div><div class='add'>+#define DID_ADL_N_SKU8	0x4677</div><div class='add'>+#define DID_ADL_N_SKU9	0x4678</div><div class='add'>+#define DID_ADL_N_SKU10	0x4679</div><div class='add'>+#define DID_ADL_N_SKU11	0x467c</div><div class='add'>+</div><div class='add'>+/* Compute die IDs for Raptor Lake-P with IBECC */</div><div class='add'>+#define DID_RPL_P_SKU1	0xa706</div><div class='add'>+#define DID_RPL_P_SKU2	0xa707</div><div class='add'>+#define DID_RPL_P_SKU3	0xa708</div><div class='add'>+#define DID_RPL_P_SKU4	0xa716</div><div class='add'>+#define DID_RPL_P_SKU5	0xa718</div><div class='add'>+</div><div class='add'>+/* Compute die IDs for Meteor Lake-PS with IBECC */</div><div class='add'>+#define DID_MTL_PS_SKU1	0x7d21</div><div class='add'>+#define DID_MTL_PS_SKU2	0x7d22</div><div class='add'>+#define DID_MTL_PS_SKU3	0x7d23</div><div class='add'>+#define DID_MTL_PS_SKU4	0x7d24</div><div class='add'>+</div><div class='add'>+/* Compute die IDs for Meteor Lake-P with IBECC */</div><div class='add'>+#define DID_MTL_P_SKU1	0x7d01</div><div class='add'>+#define DID_MTL_P_SKU2	0x7d02</div><div class='add'>+#define DID_MTL_P_SKU3	0x7d14</div><div class='add'>+</div><div class='add'>+static int get_mchbar(struct pci_dev *pdev, u64 *mchbar)</div><div class='add'>+{</div><div class='add'>+	union  {</div><div class='add'>+		u64 v;</div><div class='add'>+		struct {</div><div class='add'>+			u32 v_lo;</div><div class='add'>+			u32 v_hi;</div><div class='add'>+		};</div><div class='add'>+	} u;</div><div class='add'>+</div><div class='add'>+	if (pci_read_config_dword(pdev, MCHBAR_OFFSET, &amp;u.v_lo)) {</div><div class='add'>+		igen6_printk(KERN_ERR, "Failed to read lower MCHBAR\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pci_read_config_dword(pdev, MCHBAR_OFFSET + 4, &amp;u.v_hi)) {</div><div class='add'>+		igen6_printk(KERN_ERR, "Failed to read upper MCHBAR\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(u.v &amp; MCHBAR_EN)) {</div><div class='add'>+		igen6_printk(KERN_ERR, "MCHBAR is disabled\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*mchbar = MCHBAR_BASE(u.v);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool ehl_ibecc_available(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 v;</div><div class='hunk'>@@ -272,6 +337,39 @@ static bool tgl_ibecc_available(struct pci_dev *pdev)</div><div class='ctx'> 	return !(CAPID_E_IBECC &amp; v);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool mtl_p_ibecc_available(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	u32 v;</div><div class='add'>+</div><div class='add'>+	if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &amp;v))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return !(CAPID_E_IBECC_BIT18 &amp; v);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mtl_ps_ibecc_available(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+#define MCHBAR_MEMSS_IBECCDIS	0x13c00</div><div class='add'>+	void __iomem *window;</div><div class='add'>+	u64 mchbar;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	if (get_mchbar(pdev, &amp;mchbar))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	window = ioremap(mchbar, MCHBAR_SIZE * 2);</div><div class='add'>+	if (!window) {</div><div class='add'>+		igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = readl(window + MCHBAR_MEMSS_IBECCDIS);</div><div class='add'>+	iounmap(window);</div><div class='add'>+</div><div class='add'>+	/* Bit6: 1 - IBECC is disabled, 0 - IBECC isn't disabled */</div><div class='add'>+	return !GET_BITFIELD(val, 6, 6);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u64 mem_addr_to_sys_addr(u64 maddr)</div><div class='ctx'> {</div><div class='ctx'> 	if (maddr &lt; igen6_tolud)</div><div class='hunk'>@@ -358,6 +456,11 @@ static u64 adl_err_addr_to_imc_addr(u64 eaddr, int mc)</div><div class='ctx'> 	return imc_addr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u64 rpl_p_err_addr(u64 ecclog)</div><div class='add'>+{</div><div class='add'>+	return ECC_ERROR_LOG_ADDR45(ecclog);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct res_config ehl_cfg = {</div><div class='ctx'> 	.num_imc		= 1,</div><div class='ctx'> 	.imc_base		= 0x5000,</div><div class='hunk'>@@ -403,6 +506,51 @@ static struct res_config adl_cfg = {</div><div class='ctx'> 	.err_addr_to_imc_addr	= adl_err_addr_to_imc_addr,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct res_config adl_n_cfg = {</div><div class='add'>+	.machine_check		= true,</div><div class='add'>+	.num_imc		= 1,</div><div class='add'>+	.imc_base		= 0xd800,</div><div class='add'>+	.ibecc_base		= 0xd400,</div><div class='add'>+	.ibecc_error_log_offset	= 0x68,</div><div class='add'>+	.ibecc_available	= tgl_ibecc_available,</div><div class='add'>+	.err_addr_to_sys_addr	= adl_err_addr_to_sys_addr,</div><div class='add'>+	.err_addr_to_imc_addr	= adl_err_addr_to_imc_addr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct res_config rpl_p_cfg = {</div><div class='add'>+	.machine_check		= true,</div><div class='add'>+	.num_imc		= 2,</div><div class='add'>+	.imc_base		= 0xd800,</div><div class='add'>+	.ibecc_base		= 0xd400,</div><div class='add'>+	.ibecc_error_log_offset	= 0x68,</div><div class='add'>+	.ibecc_available	= tgl_ibecc_available,</div><div class='add'>+	.err_addr		= rpl_p_err_addr,</div><div class='add'>+	.err_addr_to_sys_addr	= adl_err_addr_to_sys_addr,</div><div class='add'>+	.err_addr_to_imc_addr	= adl_err_addr_to_imc_addr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct res_config mtl_ps_cfg = {</div><div class='add'>+	.machine_check		= true,</div><div class='add'>+	.num_imc		= 2,</div><div class='add'>+	.imc_base		= 0xd800,</div><div class='add'>+	.ibecc_base		= 0xd400,</div><div class='add'>+	.ibecc_error_log_offset	= 0x170,</div><div class='add'>+	.ibecc_available	= mtl_ps_ibecc_available,</div><div class='add'>+	.err_addr_to_sys_addr	= adl_err_addr_to_sys_addr,</div><div class='add'>+	.err_addr_to_imc_addr	= adl_err_addr_to_imc_addr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct res_config mtl_p_cfg = {</div><div class='add'>+	.machine_check		= true,</div><div class='add'>+	.num_imc		= 2,</div><div class='add'>+	.imc_base		= 0xd800,</div><div class='add'>+	.ibecc_base		= 0xd400,</div><div class='add'>+	.ibecc_error_log_offset	= 0x170,</div><div class='add'>+	.ibecc_available	= mtl_p_ibecc_available,</div><div class='add'>+	.err_addr_to_sys_addr	= adl_err_addr_to_sys_addr,</div><div class='add'>+	.err_addr_to_imc_addr	= adl_err_addr_to_imc_addr,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct pci_device_id igen6_pci_tbl[] = {</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&amp;ehl_cfg },</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&amp;ehl_cfg },</div><div class='hunk'>@@ -424,6 +572,29 @@ static const struct pci_device_id igen6_pci_tbl[] = {</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, DID_ADL_SKU2), (kernel_ulong_t)&amp;adl_cfg },</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, DID_ADL_SKU3), (kernel_ulong_t)&amp;adl_cfg },</div><div class='ctx'> 	{ PCI_VDEVICE(INTEL, DID_ADL_SKU4), (kernel_ulong_t)&amp;adl_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU1), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU2), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU3), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU4), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU5), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU6), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU7), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU8), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU9), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU10), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_ADL_N_SKU11), (kernel_ulong_t)&amp;adl_n_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&amp;rpl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&amp;rpl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&amp;rpl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU4), (kernel_ulong_t)&amp;rpl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU5), (kernel_ulong_t)&amp;rpl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU1), (kernel_ulong_t)&amp;mtl_ps_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU2), (kernel_ulong_t)&amp;mtl_ps_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU3), (kernel_ulong_t)&amp;mtl_ps_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU4), (kernel_ulong_t)&amp;mtl_ps_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_P_SKU1), (kernel_ulong_t)&amp;mtl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_P_SKU2), (kernel_ulong_t)&amp;mtl_p_cfg },</div><div class='add'>+	{ PCI_VDEVICE(INTEL, DID_MTL_P_SKU3), (kernel_ulong_t)&amp;mtl_p_cfg },</div><div class='ctx'> 	{ },</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);</div><div class='hunk'>@@ -679,8 +850,11 @@ static void ecclog_work_cb(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	llist_for_each_entry_safe(node, tmp, head, llnode) {</div><div class='ctx'> 		memset(&amp;res, 0, sizeof(res));</div><div class='del'>-		eaddr = ECC_ERROR_LOG_ADDR(node-&gt;ecclog) &lt;&lt;</div><div class='del'>-			ECC_ERROR_LOG_ADDR_SHIFT;</div><div class='add'>+		if (res_cfg-&gt;err_addr)</div><div class='add'>+			eaddr = res_cfg-&gt;err_addr(node-&gt;ecclog);</div><div class='add'>+		else</div><div class='add'>+			eaddr = ECC_ERROR_LOG_ADDR(node-&gt;ecclog) &lt;&lt;</div><div class='add'>+				ECC_ERROR_LOG_ADDR_SHIFT;</div><div class='ctx'> 		res.mc	     = node-&gt;mc;</div><div class='ctx'> 		res.sys_addr = res_cfg-&gt;err_addr_to_sys_addr(eaddr, res.mc);</div><div class='ctx'> 		res.imc_addr = res_cfg-&gt;err_addr_to_imc_addr(eaddr, res.mc);</div><div class='hunk'>@@ -969,22 +1143,8 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)</div><div class='ctx'> </div><div class='ctx'> 	igen6_tom = u.v &amp; GENMASK_ULL(38, 20);</div><div class='ctx'> </div><div class='del'>-	if (pci_read_config_dword(pdev, MCHBAR_OFFSET, &amp;u.v_lo)) {</div><div class='del'>-		igen6_printk(KERN_ERR, "Failed to read lower MCHBAR\n");</div><div class='add'>+	if (get_mchbar(pdev, mchbar))</div><div class='ctx'> 		goto fail;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (pci_read_config_dword(pdev, MCHBAR_OFFSET + 4, &amp;u.v_hi)) {</div><div class='del'>-		igen6_printk(KERN_ERR, "Failed to read upper MCHBAR\n");</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!(u.v &amp; MCHBAR_EN)) {</div><div class='del'>-		igen6_printk(KERN_ERR, "MCHBAR is disabled\n");</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	*mchbar = MCHBAR_BASE(u.v);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_EDAC_DEBUG</div><div class='ctx'> 	if (pci_read_config_dword(pdev, TOUUD_OFFSET, &amp;u.v_lo))</div><div class='head'>diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c<br/>index 7c5e2b3c0daa..d2f895033280 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/layerscape_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/layerscape_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/layerscape_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/layerscape_edac.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@ MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver fsl_ddr_mc_err_driver = {</div><div class='ctx'> 	.probe = fsl_mc_err_probe,</div><div class='del'>-	.remove = fsl_mc_err_remove,</div><div class='add'>+	.remove_new = fsl_mc_err_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "fsl_ddr_mc_err",</div><div class='ctx'> 		.of_match_table = fsl_ddr_mc_err_of_match,</div><div class='head'>diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c<br/>index 9215c06783df..ec8b6c9fedfd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/mce_amd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/mce_amd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/mce_amd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/mce_amd.c</a></div><div class='hunk'>@@ -143,482 +143,6 @@ static const char * const mc6_mce_desc[] = {</div><div class='ctx'> 	"Status Register File",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* Scalable MCA error strings */</div><div class='del'>-static const char * const smca_ls_mce_desc[] = {</div><div class='del'>-	"Load queue parity error",</div><div class='del'>-	"Store queue parity error",</div><div class='del'>-	"Miss address buffer payload parity error",</div><div class='del'>-	"Level 1 TLB parity error",</div><div class='del'>-	"DC Tag error type 5",</div><div class='del'>-	"DC Tag error type 6",</div><div class='del'>-	"DC Tag error type 1",</div><div class='del'>-	"Internal error type 1",</div><div class='del'>-	"Internal error type 2",</div><div class='del'>-	"System Read Data Error Thread 0",</div><div class='del'>-	"System Read Data Error Thread 1",</div><div class='del'>-	"DC Tag error type 2",</div><div class='del'>-	"DC Data error type 1 and poison consumption",</div><div class='del'>-	"DC Data error type 2",</div><div class='del'>-	"DC Data error type 3",</div><div class='del'>-	"DC Tag error type 4",</div><div class='del'>-	"Level 2 TLB parity error",</div><div class='del'>-	"PDC parity error",</div><div class='del'>-	"DC Tag error type 3",</div><div class='del'>-	"DC Tag error type 5",</div><div class='del'>-	"L2 Fill Data error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_ls2_mce_desc[] = {</div><div class='del'>-	"An ECC error was detected on a data cache read by a probe or victimization",</div><div class='del'>-	"An ECC error or L2 poison was detected on a data cache read by a load",</div><div class='del'>-	"An ECC error was detected on a data cache read-modify-write by a store",</div><div class='del'>-	"An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization",</div><div class='del'>-	"An ECC error or poison bit mismatch was detected on a tag read by a load",</div><div class='del'>-	"An ECC error or poison bit mismatch was detected on a tag read by a store",</div><div class='del'>-	"An ECC error was detected on an EMEM read by a load",</div><div class='del'>-	"An ECC error was detected on an EMEM read-modify-write by a store",</div><div class='del'>-	"A parity error was detected in an L1 TLB entry by any access",</div><div class='del'>-	"A parity error was detected in an L2 TLB entry by any access",</div><div class='del'>-	"A parity error was detected in a PWC entry by any access",</div><div class='del'>-	"A parity error was detected in an STQ entry by any access",</div><div class='del'>-	"A parity error was detected in an LDQ entry by any access",</div><div class='del'>-	"A parity error was detected in a MAB entry by any access",</div><div class='del'>-	"A parity error was detected in an SCB entry state field by any access",</div><div class='del'>-	"A parity error was detected in an SCB entry address field by any access",</div><div class='del'>-	"A parity error was detected in an SCB entry data field by any access",</div><div class='del'>-	"A parity error was detected in a WCB entry by any access",</div><div class='del'>-	"A poisoned line was detected in an SCB entry by any access",</div><div class='del'>-	"A SystemReadDataError error was reported on read data returned from L2 for a load",</div><div class='del'>-	"A SystemReadDataError error was reported on read data returned from L2 for an SCB store",</div><div class='del'>-	"A SystemReadDataError error was reported on read data returned from L2 for a WCB store",</div><div class='del'>-	"A hardware assertion error was reported",</div><div class='del'>-	"A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_if_mce_desc[] = {</div><div class='del'>-	"Op Cache Microtag Probe Port Parity Error",</div><div class='del'>-	"IC Microtag or Full Tag Multi-hit Error",</div><div class='del'>-	"IC Full Tag Parity Error",</div><div class='del'>-	"IC Data Array Parity Error",</div><div class='del'>-	"Decoupling Queue PhysAddr Parity Error",</div><div class='del'>-	"L0 ITLB Parity Error",</div><div class='del'>-	"L1 ITLB Parity Error",</div><div class='del'>-	"L2 ITLB Parity Error",</div><div class='del'>-	"BPQ Thread 0 Snoop Parity Error",</div><div class='del'>-	"BPQ Thread 1 Snoop Parity Error",</div><div class='del'>-	"L1 BTB Multi-Match Error",</div><div class='del'>-	"L2 BTB Multi-Match Error",</div><div class='del'>-	"L2 Cache Response Poison Error",</div><div class='del'>-	"System Read Data Error",</div><div class='del'>-	"Hardware Assertion Error",</div><div class='del'>-	"L1-TLB Multi-Hit",</div><div class='del'>-	"L2-TLB Multi-Hit",</div><div class='del'>-	"BSR Parity Error",</div><div class='del'>-	"CT MCE",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_l2_mce_desc[] = {</div><div class='del'>-	"L2M Tag Multiple-Way-Hit error",</div><div class='del'>-	"L2M Tag or State Array ECC Error",</div><div class='del'>-	"L2M Data Array ECC Error",</div><div class='del'>-	"Hardware Assert Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_de_mce_desc[] = {</div><div class='del'>-	"Micro-op cache tag parity error",</div><div class='del'>-	"Micro-op cache data parity error",</div><div class='del'>-	"Instruction buffer parity error",</div><div class='del'>-	"Micro-op queue parity error",</div><div class='del'>-	"Instruction dispatch queue parity error",</div><div class='del'>-	"Fetch address FIFO parity error",</div><div class='del'>-	"Patch RAM data parity error",</div><div class='del'>-	"Patch RAM sequencer parity error",</div><div class='del'>-	"Micro-op buffer parity error",</div><div class='del'>-	"Hardware Assertion MCA Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_ex_mce_desc[] = {</div><div class='del'>-	"Watchdog Timeout error",</div><div class='del'>-	"Physical register file parity error",</div><div class='del'>-	"Flag register file parity error",</div><div class='del'>-	"Immediate displacement register file parity error",</div><div class='del'>-	"Address generator payload parity error",</div><div class='del'>-	"EX payload parity error",</div><div class='del'>-	"Checkpoint queue parity error",</div><div class='del'>-	"Retire dispatch queue parity error",</div><div class='del'>-	"Retire status queue parity error",</div><div class='del'>-	"Scheduling queue parity error",</div><div class='del'>-	"Branch buffer queue parity error",</div><div class='del'>-	"Hardware Assertion error",</div><div class='del'>-	"Spec Map parity error",</div><div class='del'>-	"Retire Map parity error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_fp_mce_desc[] = {</div><div class='del'>-	"Physical register file (PRF) parity error",</div><div class='del'>-	"Freelist (FL) parity error",</div><div class='del'>-	"Schedule queue parity error",</div><div class='del'>-	"NSQ parity error",</div><div class='del'>-	"Retire queue (RQ) parity error",</div><div class='del'>-	"Status register file (SRF) parity error",</div><div class='del'>-	"Hardware assertion",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_l3_mce_desc[] = {</div><div class='del'>-	"Shadow Tag Macro ECC Error",</div><div class='del'>-	"Shadow Tag Macro Multi-way-hit Error",</div><div class='del'>-	"L3M Tag ECC Error",</div><div class='del'>-	"L3M Tag Multi-way-hit Error",</div><div class='del'>-	"L3M Data ECC Error",</div><div class='del'>-	"SDP Parity Error or SystemReadDataError from XI",</div><div class='del'>-	"L3 Victim Queue Parity Error",</div><div class='del'>-	"L3 Hardware Assertion",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_cs_mce_desc[] = {</div><div class='del'>-	"Illegal Request",</div><div class='del'>-	"Address Violation",</div><div class='del'>-	"Security Violation",</div><div class='del'>-	"Illegal Response",</div><div class='del'>-	"Unexpected Response",</div><div class='del'>-	"Request or Probe Parity Error",</div><div class='del'>-	"Read Response Parity Error",</div><div class='del'>-	"Atomic Request Parity Error",</div><div class='del'>-	"Probe Filter ECC Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_cs2_mce_desc[] = {</div><div class='del'>-	"Illegal Request",</div><div class='del'>-	"Address Violation",</div><div class='del'>-	"Security Violation",</div><div class='del'>-	"Illegal Response",</div><div class='del'>-	"Unexpected Response",</div><div class='del'>-	"Request or Probe Parity Error",</div><div class='del'>-	"Read Response Parity Error",</div><div class='del'>-	"Atomic Request Parity Error",</div><div class='del'>-	"SDP read response had no match in the CS queue",</div><div class='del'>-	"Probe Filter Protocol Error",</div><div class='del'>-	"Probe Filter ECC Error",</div><div class='del'>-	"SDP read response had an unexpected RETRY error",</div><div class='del'>-	"Counter overflow error",</div><div class='del'>-	"Counter underflow error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_pie_mce_desc[] = {</div><div class='del'>-	"Hardware Assert",</div><div class='del'>-	"Register security violation",</div><div class='del'>-	"Link Error",</div><div class='del'>-	"Poison data consumption",</div><div class='del'>-	"A deferred error was detected in the DF"</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_umc_mce_desc[] = {</div><div class='del'>-	"DRAM ECC error",</div><div class='del'>-	"Data poison error",</div><div class='del'>-	"SDP parity error",</div><div class='del'>-	"Advanced peripheral bus error",</div><div class='del'>-	"Address/Command parity error",</div><div class='del'>-	"Write data CRC error",</div><div class='del'>-	"DCQ SRAM ECC error",</div><div class='del'>-	"AES SRAM ECC error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_umc2_mce_desc[] = {</div><div class='del'>-	"DRAM ECC error",</div><div class='del'>-	"Data poison error",</div><div class='del'>-	"SDP parity error",</div><div class='del'>-	"Reserved",</div><div class='del'>-	"Address/Command parity error",</div><div class='del'>-	"Write data parity error",</div><div class='del'>-	"DCQ SRAM ECC error",</div><div class='del'>-	"Reserved",</div><div class='del'>-	"Read data parity error",</div><div class='del'>-	"Rdb SRAM ECC error",</div><div class='del'>-	"RdRsp SRAM ECC error",</div><div class='del'>-	"LM32 MP errors",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_pb_mce_desc[] = {</div><div class='del'>-	"An ECC error in the Parameter Block RAM array",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_psp_mce_desc[] = {</div><div class='del'>-	"An ECC or parity error in a PSP RAM instance",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_psp2_mce_desc[] = {</div><div class='del'>-	"High SRAM ECC or parity error",</div><div class='del'>-	"Low SRAM ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank 0 ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank 1 ECC or parity error",</div><div class='del'>-	"Instruction Tag Ram 0 parity error",</div><div class='del'>-	"Instruction Tag Ram 1 parity error",</div><div class='del'>-	"Data Cache Bank 0 ECC or parity error",</div><div class='del'>-	"Data Cache Bank 1 ECC or parity error",</div><div class='del'>-	"Data Cache Bank 2 ECC or parity error",</div><div class='del'>-	"Data Cache Bank 3 ECC or parity error",</div><div class='del'>-	"Data Tag Bank 0 parity error",</div><div class='del'>-	"Data Tag Bank 1 parity error",</div><div class='del'>-	"Data Tag Bank 2 parity error",</div><div class='del'>-	"Data Tag Bank 3 parity error",</div><div class='del'>-	"Dirty Data Ram parity error",</div><div class='del'>-	"TLB Bank 0 parity error",</div><div class='del'>-	"TLB Bank 1 parity error",</div><div class='del'>-	"System Hub Read Buffer ECC or parity error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_smu_mce_desc[] = {</div><div class='del'>-	"An ECC or parity error in an SMU RAM instance",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_smu2_mce_desc[] = {</div><div class='del'>-	"High SRAM ECC or parity error",</div><div class='del'>-	"Low SRAM ECC or parity error",</div><div class='del'>-	"Data Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"System Hub Read Buffer ECC or parity error",</div><div class='del'>-	"PHY RAM ECC error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_mp5_mce_desc[] = {</div><div class='del'>-	"High SRAM ECC or parity error",</div><div class='del'>-	"Low SRAM ECC or parity error",</div><div class='del'>-	"Data Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank B ECC or parity error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_mpdma_mce_desc[] = {</div><div class='del'>-	"Main SRAM [31:0] bank ECC or parity error",</div><div class='del'>-	"Main SRAM [63:32] bank ECC or parity error",</div><div class='del'>-	"Main SRAM [95:64] bank ECC or parity error",</div><div class='del'>-	"Main SRAM [127:96] bank ECC or parity error",</div><div class='del'>-	"Data Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Cache Bank B ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Data Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Cache Bank B ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank A ECC or parity error",</div><div class='del'>-	"Instruction Tag Cache Bank B ECC or parity error",</div><div class='del'>-	"System Hub Read Buffer ECC or parity error",</div><div class='del'>-	"MPDMA TVF DVSEC Memory ECC or parity error",</div><div class='del'>-	"MPDMA TVF MMIO Mailbox0 ECC or parity error",</div><div class='del'>-	"MPDMA TVF MMIO Mailbox1 ECC or parity error",</div><div class='del'>-	"MPDMA TVF Doorbell Memory ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Slave Memory 0 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Slave Memory 1 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Slave Memory 2 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 0 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 1 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 2 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 3 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 4 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 5 ECC or parity error",</div><div class='del'>-	"MPDMA TVF SDP Master Memory 6 ECC or parity error",</div><div class='del'>-	"MPDMA PTE Command FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE Hub Data FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE Internal Data FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE Command Memory DMA ECC or parity error",</div><div class='del'>-	"MPDMA PTE Command Memory Internal ECC or parity error",</div><div class='del'>-	"MPDMA PTE DMA Completion FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE Tablewalk Completion FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE Descriptor Completion FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE ReadOnly Completion FIFO ECC or parity error",</div><div class='del'>-	"MPDMA PTE DirectWrite Completion FIFO ECC or parity error",</div><div class='del'>-	"SDP Watchdog Timer expired",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_nbio_mce_desc[] = {</div><div class='del'>-	"ECC or Parity error",</div><div class='del'>-	"PCIE error",</div><div class='del'>-	"SDP ErrEvent error",</div><div class='del'>-	"SDP Egress Poison Error",</div><div class='del'>-	"IOHC Internal Poison Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_pcie_mce_desc[] = {</div><div class='del'>-	"CCIX PER Message logging",</div><div class='del'>-	"CCIX Read Response with Status: Non-Data Error",</div><div class='del'>-	"CCIX Write Response with Status: Non-Data Error",</div><div class='del'>-	"CCIX Read Response with Status: Data Error",</div><div class='del'>-	"CCIX Non-okay write response with data error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_pcie2_mce_desc[] = {</div><div class='del'>-	"SDP Parity Error logging",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_xgmipcs_mce_desc[] = {</div><div class='del'>-	"Data Loss Error",</div><div class='del'>-	"Training Error",</div><div class='del'>-	"Flow Control Acknowledge Error",</div><div class='del'>-	"Rx Fifo Underflow Error",</div><div class='del'>-	"Rx Fifo Overflow Error",</div><div class='del'>-	"CRC Error",</div><div class='del'>-	"BER Exceeded Error",</div><div class='del'>-	"Tx Vcid Data Error",</div><div class='del'>-	"Replay Buffer Parity Error",</div><div class='del'>-	"Data Parity Error",</div><div class='del'>-	"Replay Fifo Overflow Error",</div><div class='del'>-	"Replay Fifo Underflow Error",</div><div class='del'>-	"Elastic Fifo Overflow Error",</div><div class='del'>-	"Deskew Error",</div><div class='del'>-	"Flow Control CRC Error",</div><div class='del'>-	"Data Startup Limit Error",</div><div class='del'>-	"FC Init Timeout Error",</div><div class='del'>-	"Recovery Timeout Error",</div><div class='del'>-	"Ready Serial Timeout Error",</div><div class='del'>-	"Ready Serial Attempt Error",</div><div class='del'>-	"Recovery Attempt Error",</div><div class='del'>-	"Recovery Relock Attempt Error",</div><div class='del'>-	"Replay Attempt Error",</div><div class='del'>-	"Sync Header Error",</div><div class='del'>-	"Tx Replay Timeout Error",</div><div class='del'>-	"Rx Replay Timeout Error",</div><div class='del'>-	"LinkSub Tx Timeout Error",</div><div class='del'>-	"LinkSub Rx Timeout Error",</div><div class='del'>-	"Rx CMD Packet Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_xgmiphy_mce_desc[] = {</div><div class='del'>-	"RAM ECC Error",</div><div class='del'>-	"ARC instruction buffer parity error",</div><div class='del'>-	"ARC data buffer parity error",</div><div class='del'>-	"PHY APB error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_nbif_mce_desc[] = {</div><div class='del'>-	"Timeout error from GMI",</div><div class='del'>-	"SRAM ECC error",</div><div class='del'>-	"NTB Error Event",</div><div class='del'>-	"SDP Parity error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_sata_mce_desc[] = {</div><div class='del'>-	"Parity error for port 0",</div><div class='del'>-	"Parity error for port 1",</div><div class='del'>-	"Parity error for port 2",</div><div class='del'>-	"Parity error for port 3",</div><div class='del'>-	"Parity error for port 4",</div><div class='del'>-	"Parity error for port 5",</div><div class='del'>-	"Parity error for port 6",</div><div class='del'>-	"Parity error for port 7",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_usb_mce_desc[] = {</div><div class='del'>-	"Parity error or ECC error for S0 RAM0",</div><div class='del'>-	"Parity error or ECC error for S0 RAM1",</div><div class='del'>-	"Parity error or ECC error for S0 RAM2",</div><div class='del'>-	"Parity error for PHY RAM0",</div><div class='del'>-	"Parity error for PHY RAM1",</div><div class='del'>-	"AXI Slave Response error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const char * const smca_gmipcs_mce_desc[] = {</div><div class='del'>-	"Data Loss Error",</div><div class='del'>-	"Training Error",</div><div class='del'>-	"Replay Parity Error",</div><div class='del'>-	"Rx Fifo Underflow Error",</div><div class='del'>-	"Rx Fifo Overflow Error",</div><div class='del'>-	"CRC Error",</div><div class='del'>-	"BER Exceeded Error",</div><div class='del'>-	"Tx Fifo Underflow Error",</div><div class='del'>-	"Replay Buffer Parity Error",</div><div class='del'>-	"Tx Overflow Error",</div><div class='del'>-	"Replay Fifo Overflow Error",</div><div class='del'>-	"Replay Fifo Underflow Error",</div><div class='del'>-	"Elastic Fifo Overflow Error",</div><div class='del'>-	"Deskew Error",</div><div class='del'>-	"Offline Error",</div><div class='del'>-	"Data Startup Limit Error",</div><div class='del'>-	"FC Init Timeout Error",</div><div class='del'>-	"Recovery Timeout Error",</div><div class='del'>-	"Ready Serial Timeout Error",</div><div class='del'>-	"Ready Serial Attempt Error",</div><div class='del'>-	"Recovery Attempt Error",</div><div class='del'>-	"Recovery Relock Attempt Error",</div><div class='del'>-	"Deskew Abort Error",</div><div class='del'>-	"Rx Buffer Error",</div><div class='del'>-	"Rx LFDS Fifo Overflow Error",</div><div class='del'>-	"Rx LFDS Fifo Underflow Error",</div><div class='del'>-	"LinkSub Tx Timeout Error",</div><div class='del'>-	"LinkSub Rx Timeout Error",</div><div class='del'>-	"Rx CMD Packet Error",</div><div class='del'>-	"LFDS Training Timeout Error",</div><div class='del'>-	"LFDS FC Init Timeout Error",</div><div class='del'>-	"Data Loss Error",</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct smca_mce_desc {</div><div class='del'>-	const char * const *descs;</div><div class='del'>-	unsigned int num_descs;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct smca_mce_desc smca_mce_descs[] = {</div><div class='del'>-	[SMCA_LS]	= { smca_ls_mce_desc,	ARRAY_SIZE(smca_ls_mce_desc)	},</div><div class='del'>-	[SMCA_LS_V2]	= { smca_ls2_mce_desc,	ARRAY_SIZE(smca_ls2_mce_desc)	},</div><div class='del'>-	[SMCA_IF]	= { smca_if_mce_desc,	ARRAY_SIZE(smca_if_mce_desc)	},</div><div class='del'>-	[SMCA_L2_CACHE]	= { smca_l2_mce_desc,	ARRAY_SIZE(smca_l2_mce_desc)	},</div><div class='del'>-	[SMCA_DE]	= { smca_de_mce_desc,	ARRAY_SIZE(smca_de_mce_desc)	},</div><div class='del'>-	[SMCA_EX]	= { smca_ex_mce_desc,	ARRAY_SIZE(smca_ex_mce_desc)	},</div><div class='del'>-	[SMCA_FP]	= { smca_fp_mce_desc,	ARRAY_SIZE(smca_fp_mce_desc)	},</div><div class='del'>-	[SMCA_L3_CACHE]	= { smca_l3_mce_desc,	ARRAY_SIZE(smca_l3_mce_desc)	},</div><div class='del'>-	[SMCA_CS]	= { smca_cs_mce_desc,	ARRAY_SIZE(smca_cs_mce_desc)	},</div><div class='del'>-	[SMCA_CS_V2]	= { smca_cs2_mce_desc,	ARRAY_SIZE(smca_cs2_mce_desc)	},</div><div class='del'>-	[SMCA_PIE]	= { smca_pie_mce_desc,	ARRAY_SIZE(smca_pie_mce_desc)	},</div><div class='del'>-	[SMCA_UMC]	= { smca_umc_mce_desc,	ARRAY_SIZE(smca_umc_mce_desc)	},</div><div class='del'>-	[SMCA_UMC_V2]	= { smca_umc2_mce_desc,	ARRAY_SIZE(smca_umc2_mce_desc)	},</div><div class='del'>-	[SMCA_PB]	= { smca_pb_mce_desc,	ARRAY_SIZE(smca_pb_mce_desc)	},</div><div class='del'>-	[SMCA_PSP]	= { smca_psp_mce_desc,	ARRAY_SIZE(smca_psp_mce_desc)	},</div><div class='del'>-	[SMCA_PSP_V2]	= { smca_psp2_mce_desc,	ARRAY_SIZE(smca_psp2_mce_desc)	},</div><div class='del'>-	[SMCA_SMU]	= { smca_smu_mce_desc,	ARRAY_SIZE(smca_smu_mce_desc)	},</div><div class='del'>-	[SMCA_SMU_V2]	= { smca_smu2_mce_desc,	ARRAY_SIZE(smca_smu2_mce_desc)	},</div><div class='del'>-	[SMCA_MP5]	= { smca_mp5_mce_desc,	ARRAY_SIZE(smca_mp5_mce_desc)	},</div><div class='del'>-	[SMCA_MPDMA]	= { smca_mpdma_mce_desc,	ARRAY_SIZE(smca_mpdma_mce_desc)	},</div><div class='del'>-	[SMCA_NBIO]	= { smca_nbio_mce_desc,	ARRAY_SIZE(smca_nbio_mce_desc)	},</div><div class='del'>-	[SMCA_PCIE]	= { smca_pcie_mce_desc,	ARRAY_SIZE(smca_pcie_mce_desc)	},</div><div class='del'>-	[SMCA_PCIE_V2]	= { smca_pcie2_mce_desc,   ARRAY_SIZE(smca_pcie2_mce_desc)	},</div><div class='del'>-	[SMCA_XGMI_PCS]	= { smca_xgmipcs_mce_desc, ARRAY_SIZE(smca_xgmipcs_mce_desc)	},</div><div class='del'>-	/* NBIF and SHUB have the same error descriptions, for now. */</div><div class='del'>-	[SMCA_NBIF]	= { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc)	},</div><div class='del'>-	[SMCA_SHUB]	= { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc)	},</div><div class='del'>-	[SMCA_SATA]	= { smca_sata_mce_desc, ARRAY_SIZE(smca_sata_mce_desc)	},</div><div class='del'>-	[SMCA_USB]	= { smca_usb_mce_desc,	ARRAY_SIZE(smca_usb_mce_desc)	},</div><div class='del'>-	[SMCA_GMI_PCS]	= { smca_gmipcs_mce_desc,  ARRAY_SIZE(smca_gmipcs_mce_desc)	},</div><div class='del'>-	/* All the PHY bank types have the same error descriptions, for now. */</div><div class='del'>-	[SMCA_XGMI_PHY]	= { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)	},</div><div class='del'>-	[SMCA_WAFL_PHY]	= { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)	},</div><div class='del'>-	[SMCA_GMI_PHY]	= { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)	},</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static bool f12h_mc0_mce(u16 ec, u8 xec)</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = false;</div><div class='hunk'>@@ -1163,11 +687,51 @@ static void decode_mc6_mce(struct mce *m)</div><div class='ctx'> 	pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char * const smca_long_names[] = {</div><div class='add'>+	[SMCA_LS ... SMCA_LS_V2]	= "Load Store Unit",</div><div class='add'>+	[SMCA_IF]			= "Instruction Fetch Unit",</div><div class='add'>+	[SMCA_L2_CACHE]			= "L2 Cache",</div><div class='add'>+	[SMCA_DE]			= "Decode Unit",</div><div class='add'>+	[SMCA_RESERVED]			= "Reserved",</div><div class='add'>+	[SMCA_EX]			= "Execution Unit",</div><div class='add'>+	[SMCA_FP]			= "Floating Point Unit",</div><div class='add'>+	[SMCA_L3_CACHE]			= "L3 Cache",</div><div class='add'>+	[SMCA_CS ... SMCA_CS_V2]	= "Coherent Slave",</div><div class='add'>+	[SMCA_PIE]			= "Power, Interrupts, etc.",</div><div class='add'>+</div><div class='add'>+	/* UMC v2 is separate because both of them can exist in a single system. */</div><div class='add'>+	[SMCA_UMC]			= "Unified Memory Controller",</div><div class='add'>+	[SMCA_UMC_V2]			= "Unified Memory Controller v2",</div><div class='add'>+	[SMCA_PB]			= "Parameter Block",</div><div class='add'>+	[SMCA_PSP ... SMCA_PSP_V2]	= "Platform Security Processor",</div><div class='add'>+	[SMCA_SMU ... SMCA_SMU_V2]	= "System Management Unit",</div><div class='add'>+	[SMCA_MP5]			= "Microprocessor 5 Unit",</div><div class='add'>+	[SMCA_MPDMA]			= "MPDMA Unit",</div><div class='add'>+	[SMCA_NBIO]			= "Northbridge IO Unit",</div><div class='add'>+	[SMCA_PCIE ... SMCA_PCIE_V2]	= "PCI Express Unit",</div><div class='add'>+	[SMCA_XGMI_PCS]			= "Ext Global Memory Interconnect PCS Unit",</div><div class='add'>+	[SMCA_NBIF]			= "NBIF Unit",</div><div class='add'>+	[SMCA_SHUB]			= "System Hub Unit",</div><div class='add'>+	[SMCA_SATA]			= "SATA Unit",</div><div class='add'>+	[SMCA_USB]			= "USB Unit",</div><div class='add'>+	[SMCA_GMI_PCS]			= "Global Memory Interconnect PCS Unit",</div><div class='add'>+	[SMCA_XGMI_PHY]			= "Ext Global Memory Interconnect PHY Unit",</div><div class='add'>+	[SMCA_WAFL_PHY]			= "WAFL PHY Unit",</div><div class='add'>+	[SMCA_GMI_PHY]			= "Global Memory Interconnect PHY Unit",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *smca_get_long_name(enum smca_bank_types t)</div><div class='add'>+{</div><div class='add'>+	if (t &gt;= N_SMCA_BANK_TYPES)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return smca_long_names[t];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Decode errors according to Scalable MCA specification */</div><div class='ctx'> static void decode_smca_error(struct mce *m)</div><div class='ctx'> {</div><div class='ctx'> 	enum smca_bank_types bank_type = smca_get_bank_type(m-&gt;extcpu, m-&gt;bank);</div><div class='del'>-	const char *ip_name;</div><div class='ctx'> 	u8 xec = XEC(m-&gt;status, xec_mask);</div><div class='ctx'> </div><div class='ctx'> 	if (bank_type &gt;= N_SMCA_BANK_TYPES)</div><div class='hunk'>@@ -1178,13 +742,7 @@ static void decode_smca_error(struct mce *m)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ip_name = smca_get_long_name(bank_type);</div><div class='del'>-</div><div class='del'>-	pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);</div><div class='del'>-</div><div class='del'>-	/* Only print the decode of valid error codes */</div><div class='del'>-	if (xec &lt; smca_mce_descs[bank_type].num_descs)</div><div class='del'>-		pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);</div><div class='add'>+	pr_emerg(HW_ERR "%s Ext. Error Code: %d", smca_get_long_name(bank_type), xec);</div><div class='ctx'> </div><div class='ctx'> 	if ((bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) &amp;&amp;</div><div class='ctx'> 	    xec == 0 &amp;&amp; decode_dram_ecc)</div><div class='head'>diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c<br/>index 2b5703e5066e..c1bc53f4e184 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/mpc85xx_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/mpc85xx_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/mpc85xx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/mpc85xx_edac.c</a></div><div class='hunk'>@@ -300,7 +300,7 @@ err:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mpc85xx_pci_err_remove(struct platform_device *op)</div><div class='add'>+static void mpc85xx_pci_err_remove(struct platform_device *op)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_pci_ctl_info *pci = dev_get_drvdata(&amp;op-&gt;dev);</div><div class='ctx'> 	struct mpc85xx_pci_pdata *pdata = pci-&gt;pvt_info;</div><div class='hunk'>@@ -312,8 +312,6 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)</div><div class='ctx'> </div><div class='ctx'> 	edac_pci_del_device(&amp;op-&gt;dev);</div><div class='ctx'> 	edac_pci_free_ctl_info(pci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct platform_device_id mpc85xx_pci_err_match[] = {</div><div class='hunk'>@@ -325,7 +323,7 @@ static const struct platform_device_id mpc85xx_pci_err_match[] = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mpc85xx_pci_err_driver = {</div><div class='ctx'> 	.probe = mpc85xx_pci_err_probe,</div><div class='del'>-	.remove = mpc85xx_pci_err_remove,</div><div class='add'>+	.remove_new = mpc85xx_pci_err_remove,</div><div class='ctx'> 	.id_table = mpc85xx_pci_err_match,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "mpc85xx_pci_err",</div><div class='hunk'>@@ -591,7 +589,7 @@ err:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mpc85xx_l2_err_remove(struct platform_device *op)</div><div class='add'>+static void mpc85xx_l2_err_remove(struct platform_device *op)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&amp;op-&gt;dev);</div><div class='ctx'> 	struct mpc85xx_l2_pdata *pdata = edac_dev-&gt;pvt_info;</div><div class='hunk'>@@ -606,7 +604,6 @@ static int mpc85xx_l2_err_remove(struct platform_device *op)</div><div class='ctx'> 	out_be32(pdata-&gt;l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);</div><div class='ctx'> 	edac_device_del_device(&amp;op-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(edac_dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mpc85xx_l2_err_of_match[] = {</div><div class='hunk'>@@ -630,7 +627,7 @@ MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mpc85xx_l2_err_driver = {</div><div class='ctx'> 	.probe = mpc85xx_l2_err_probe,</div><div class='del'>-	.remove = mpc85xx_l2_err_remove,</div><div class='add'>+	.remove_new = mpc85xx_l2_err_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "mpc85xx_l2_err",</div><div class='ctx'> 		.of_match_table = mpc85xx_l2_err_of_match,</div><div class='hunk'>@@ -659,7 +656,7 @@ MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mpc85xx_mc_err_driver = {</div><div class='ctx'> 	.probe = fsl_mc_err_probe,</div><div class='del'>-	.remove = fsl_mc_err_remove,</div><div class='add'>+	.remove_new = fsl_mc_err_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "mpc85xx_mc_err",</div><div class='ctx'> 		.of_match_table = mpc85xx_mc_err_of_match,</div><div class='head'>diff --git a/drivers/edac/npcm_edac.c b/drivers/edac/npcm_edac.c<br/>index 6d15c1550263..2e2133b784e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/npcm_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/npcm_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/npcm_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/npcm_edac.c</a></div><div class='hunk'>@@ -410,7 +410,7 @@ free_edac_mc:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int edac_remove(struct platform_device *pdev)</div><div class='add'>+static void edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct priv_data *priv = mci-&gt;pvt_info;</div><div class='hunk'>@@ -426,8 +426,6 @@ static int edac_remove(struct platform_device *pdev)</div><div class='ctx'> 	regmap_write(npcm_regmap, pdata-&gt;ctl_int_mask_master,</div><div class='ctx'> 		     pdata-&gt;int_mask_master_global_mask);</div><div class='ctx'> 	regmap_update_bits(npcm_regmap, pdata-&gt;ctl_ecc_en, pdata-&gt;ecc_en_mask, 0);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct npcm_platform_data npcm750_edac = {</div><div class='hunk'>@@ -533,7 +531,7 @@ static struct platform_driver npcm_edac_driver = {</div><div class='ctx'> 		.of_match_table = npcm_edac_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = edac_probe,</div><div class='del'>-	.remove = edac_remove,</div><div class='add'>+	.remove_new = edac_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(npcm_edac_driver);</div><div class='head'>diff --git a/drivers/edac/octeon_edac-l2c.c b/drivers/edac/octeon_edac-l2c.c<br/>index c33059e9b0be..4015eb9af6fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-l2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/octeon_edac-l2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-l2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-l2c.c</a></div><div class='hunk'>@@ -184,19 +184,17 @@ err:</div><div class='ctx'> 	return -ENXIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int octeon_l2c_remove(struct platform_device *pdev)</div><div class='add'>+static void octeon_l2c_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *l2c = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(l2c);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver octeon_l2c_driver = {</div><div class='ctx'> 	.probe = octeon_l2c_probe,</div><div class='del'>-	.remove = octeon_l2c_remove,</div><div class='add'>+	.remove_new = octeon_l2c_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "octeon_l2c_edac",</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/edac/octeon_edac-lmc.c b/drivers/edac/octeon_edac-lmc.c<br/>index aeb222ca3ed1..18615cbcd9ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-lmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/octeon_edac-lmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-lmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-lmc.c</a></div><div class='hunk'>@@ -302,18 +302,17 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int octeon_lmc_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void octeon_lmc_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver octeon_lmc_edac_driver = {</div><div class='ctx'> 	.probe = octeon_lmc_edac_probe,</div><div class='del'>-	.remove = octeon_lmc_edac_remove,</div><div class='add'>+	.remove_new = octeon_lmc_edac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "octeon_lmc_edac",</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/edac/octeon_edac-pc.c b/drivers/edac/octeon_edac-pc.c<br/>index 754eced59c32..ea8a8e337b1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-pc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/octeon_edac-pc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-pc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-pc.c</a></div><div class='hunk'>@@ -119,19 +119,18 @@ err:</div><div class='ctx'> 	return -ENXIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int co_cache_error_remove(struct platform_device *pdev)</div><div class='add'>+static void co_cache_error_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct co_cache_error *p = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	unregister_co_cache_error_notifier(&amp;p-&gt;notifier);</div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(p-&gt;ed);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver co_cache_error_driver = {</div><div class='ctx'> 	.probe = co_cache_error_probe,</div><div class='del'>-	.remove = co_cache_error_remove,</div><div class='add'>+	.remove_new = co_cache_error_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "octeon_pc_edac",</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/edac/octeon_edac-pci.c b/drivers/edac/octeon_edac-pci.c<br/>index 28b238eecefc..108ad9493cfb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/octeon_edac-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/octeon_edac-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/octeon_edac-pci.c</a></div><div class='hunk'>@@ -87,19 +87,17 @@ err:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int octeon_pci_remove(struct platform_device *pdev)</div><div class='add'>+static void octeon_pci_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_pci_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_pci_free_ctl_info(pci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver octeon_pci_driver = {</div><div class='ctx'> 	.probe = octeon_pci_probe,</div><div class='del'>-	.remove = octeon_pci_remove,</div><div class='add'>+	.remove_new = octeon_pci_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "octeon_pci_edac",</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c<br/>index 2b306f2cc605..2afcd148fcf8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/pnd2_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/pnd2_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/pnd2_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/pnd2_edac.c</a></div><div class='hunk'>@@ -16,18 +16,20 @@</div><div class='ctx'>  * rank, bank, row and column using the appropriate "dunit_ops" functions/parameters.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/bitmap.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/edac.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/math64.h&gt;</div><div class='add'>+#include &lt;linux/mmzone.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/pci_ids.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/edac.h&gt;</div><div class='del'>-#include &lt;linux/mmzone.h&gt;</div><div class='ctx'> #include &lt;linux/smp.h&gt;</div><div class='del'>-#include &lt;linux/bitmap.h&gt;</div><div class='del'>-#include &lt;linux/math64.h&gt;</div><div class='del'>-#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/platform_data/x86/p2sb.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/cpu_device_id.h&gt;</div><div class='hunk'>@@ -109,7 +111,6 @@ static struct mem_ctl_info *pnd2_mci;</div><div class='ctx'> #define MOT_CHAN_INTLV_BIT_1SLC_2CH 12</div><div class='ctx'> #define MOT_CHAN_INTLV_BIT_2SLC_2CH 13</div><div class='ctx'> #define SELECTOR_DISABLED (-1)</div><div class='del'>-#define _4GB (1ul &lt;&lt; 32)</div><div class='ctx'> </div><div class='ctx'> #define PMI_ADDRESS_WIDTH	31</div><div class='ctx'> #define PND_MAX_PHYS_BIT	39</div><div class='hunk'>@@ -183,7 +184,7 @@ static int _apl_rd_reg(int port, int off, int op, u32 *data)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	P2SB_READ(dword, P2SB_DATA_OFF, data);</div><div class='del'>-	ret = (status &gt;&gt; 1) &amp; 0x3;</div><div class='add'>+	ret = (status &gt;&gt; 1) &amp; GENMASK(1, 0);</div><div class='ctx'> out:</div><div class='ctx'> 	/* Hide the P2SB device, if it was hidden before */</div><div class='ctx'> 	if (hidden)</div><div class='hunk'>@@ -307,7 +308,7 @@ static bool two_channels; /* Both PMI channels in one slice enabled */</div><div class='ctx'> </div><div class='ctx'> static u8 sym_chan_mask;</div><div class='ctx'> static u8 asym_chan_mask;</div><div class='del'>-static u8 chan_mask;</div><div class='add'>+static unsigned long chan_mask;</div><div class='ctx'> </div><div class='ctx'> static int slice_selector = -1;</div><div class='ctx'> static int chan_selector = -1;</div><div class='hunk'>@@ -329,7 +330,7 @@ static void mk_region_mask(char *name, struct region *rp, u64 base, u64 mask)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) {</div><div class='del'>-		pr_info(FW_BUG "MOT mask not power of two\n");</div><div class='add'>+		pr_info(FW_BUG "MOT mask is invalid\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (base &amp; ~mask) {</div><div class='hunk'>@@ -587,7 +588,7 @@ static int get_registers(void)</div><div class='ctx'> /* Get a contiguous memory address (remove the MMIO gap) */</div><div class='ctx'> static u64 remove_mmio_gap(u64 sys)</div><div class='ctx'> {</div><div class='del'>-	return (sys &lt; _4GB) ? sys : sys - (_4GB - top_lm);</div><div class='add'>+	return (sys &lt; SZ_4G) ? sys : sys - (SZ_4G - top_lm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Squeeze out one address bit, shift upper part down to fill gap */</div><div class='hunk'>@@ -598,7 +599,7 @@ static void remove_addr_bit(u64 *addr, int bitidx)</div><div class='ctx'> 	if (bitidx == -1)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	mask = (1ull &lt;&lt; bitidx) - 1;</div><div class='add'>+	mask = BIT_ULL(bitidx) - 1;</div><div class='ctx'> 	*addr = ((*addr &gt;&gt; 1) &amp; ~mask) | (*addr &amp; mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -642,8 +643,8 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg)</div><div class='ctx'> 	int sym_chan_shift = sym_channels &gt;&gt; 1;</div><div class='ctx'> </div><div class='ctx'> 	/* Give up if address is out of range, or in MMIO gap */</div><div class='del'>-	if (addr &gt;= (1ul &lt;&lt; PND_MAX_PHYS_BIT) ||</div><div class='del'>-	   (addr &gt;= top_lm &amp;&amp; addr &lt; _4GB) || addr &gt;= top_hm) {</div><div class='add'>+	if (addr &gt;= BIT(PND_MAX_PHYS_BIT) ||</div><div class='add'>+	   (addr &gt;= top_lm &amp;&amp; addr &lt; SZ_4G) || addr &gt;= top_hm) {</div><div class='ctx'> 		snprintf(msg, PND2_MSG_SIZE, "Error address 0x%llx is not DRAM", addr);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -727,10 +728,10 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Translate PMI address to memory (rank, row, bank, column) */</div><div class='del'>-#define C(n) (0x10 | (n))	/* column */</div><div class='del'>-#define B(n) (0x20 | (n))	/* bank */</div><div class='del'>-#define R(n) (0x40 | (n))	/* row */</div><div class='del'>-#define RS   (0x80)			/* rank */</div><div class='add'>+#define C(n) (BIT(4) | (n))	/* column */</div><div class='add'>+#define B(n) (BIT(5) | (n))	/* bank */</div><div class='add'>+#define R(n) (BIT(6) | (n))	/* row */</div><div class='add'>+#define RS   (BIT(7))		/* rank */</div><div class='ctx'> </div><div class='ctx'> /* addrdec values */</div><div class='ctx'> #define AMAP_1KB	0</div><div class='hunk'>@@ -1064,9 +1065,9 @@ static int apl_check_ecc_active(void)</div><div class='ctx'> 	int	i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Check dramtype and ECC mode for each present DIMM */</div><div class='del'>-	for (i = 0; i &lt; APL_NUM_CHANNELS; i++)</div><div class='del'>-		if (chan_mask &amp; BIT(i))</div><div class='del'>-			ret += check_channel(i);</div><div class='add'>+	for_each_set_bit(i, &amp;chan_mask, APL_NUM_CHANNELS)</div><div class='add'>+		ret += check_channel(i);</div><div class='add'>+</div><div class='ctx'> 	return ret ? -EINVAL : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1205,10 +1206,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci)</div><div class='ctx'> 	u64	capacity;</div><div class='ctx'> 	int	i, g;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; APL_NUM_CHANNELS; i++) {</div><div class='del'>-		if (!(chan_mask &amp; BIT(i)))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='add'>+	for_each_set_bit(i, &amp;chan_mask, APL_NUM_CHANNELS) {</div><div class='ctx'> 		dimm = edac_get_dimm(mci, i, 0, 0);</div><div class='ctx'> 		if (!dimm) {</div><div class='ctx'> 			edac_dbg(0, "No allocated DIMM for channel %d\n", i);</div><div class='hunk'>@@ -1228,8 +1226,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		pvt-&gt;dimm_geom[i] = g;</div><div class='del'>-		capacity = (d-&gt;rken0 + d-&gt;rken1) * 8 * (1ul &lt;&lt; dimms[g].rowbits) *</div><div class='del'>-				   (1ul &lt;&lt; dimms[g].colbits);</div><div class='add'>+		capacity = (d-&gt;rken0 + d-&gt;rken1) * 8 * BIT(dimms[g].rowbits + dimms[g].colbits);</div><div class='ctx'> 		edac_dbg(0, "Channel %d: %lld MByte DIMM\n", i, capacity &gt;&gt; (20 - 3));</div><div class='ctx'> 		dimm-&gt;nr_pages = MiB_TO_PAGES(capacity &gt;&gt; (20 - 3));</div><div class='ctx'> 		dimm-&gt;grain = 32;</div><div class='hunk'>@@ -1295,7 +1292,7 @@ static void dnv_get_dimm_config(struct mem_ctl_info *mci)</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			capacity = ranks_of_dimm[j] * banks * (1ul &lt;&lt; rowbits) * (1ul &lt;&lt; colbits);</div><div class='add'>+			capacity = ranks_of_dimm[j] * banks * BIT(rowbits + colbits);</div><div class='ctx'> 			edac_dbg(0, "Channel %d DIMM %d: %lld MByte DIMM\n", i, j, capacity &gt;&gt; (20 - 3));</div><div class='ctx'> 			dimm-&gt;nr_pages = MiB_TO_PAGES(capacity &gt;&gt; (20 - 3));</div><div class='ctx'> 			dimm-&gt;grain = 32;</div><div class='head'>diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c<br/>index 046969b4e82e..1eea3341a916 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/ppc4xx_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/ppc4xx_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/ppc4xx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/ppc4xx_edac.c</a></div><div class='hunk'>@@ -1329,8 +1329,7 @@ static int ppc4xx_edac_probe(struct platform_device *op)</div><div class='ctx'>  *</div><div class='ctx'>  * Unconditionally returns 0.</div><div class='ctx'>  */</div><div class='del'>-static int</div><div class='del'>-ppc4xx_edac_remove(struct platform_device *op)</div><div class='add'>+static void ppc4xx_edac_remove(struct platform_device *op)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = dev_get_drvdata(&amp;op-&gt;dev);</div><div class='ctx'> 	struct ppc4xx_edac_pdata *pdata = mci-&gt;pvt_info;</div><div class='hunk'>@@ -1344,8 +1343,6 @@ ppc4xx_edac_remove(struct platform_device *op)</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(mci-&gt;pdev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1379,7 +1376,7 @@ ppc4xx_edac_opstate_init(void)</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ppc4xx_edac_driver = {</div><div class='ctx'> 	.probe			= ppc4xx_edac_probe,</div><div class='del'>-	.remove			= ppc4xx_edac_remove,</div><div class='add'>+	.remove_new		= ppc4xx_edac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = PPC4XX_EDAC_MODULE_NAME,</div><div class='ctx'> 		.of_match_table = ppc4xx_edac_match,</div><div class='head'>diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c<br/>index b2db545c6810..5539917c01dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/qcom_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/qcom_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/qcom_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/qcom_edac.c</a></div><div class='hunk'>@@ -390,14 +390,12 @@ irq_done:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qcom_llcc_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_llcc_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	edac_device_del_device(edev_ctl-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(edev_ctl);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct platform_device_id qcom_llcc_edac_id_table[] = {</div><div class='hunk'>@@ -408,7 +406,7 @@ MODULE_DEVICE_TABLE(platform, qcom_llcc_edac_id_table);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcom_llcc_edac_driver = {</div><div class='ctx'> 	.probe = qcom_llcc_edac_probe,</div><div class='del'>-	.remove = qcom_llcc_edac_remove,</div><div class='add'>+	.remove_new = qcom_llcc_edac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom_llcc_edac",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c<br/>index 0c779a0326b6..26cca5a9322d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/sb_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/sb_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/sb_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/sb_edac.c</a></div><div class='hunk'>@@ -439,7 +439,7 @@ static const struct pci_id_descr pci_dev_descr_sbridge[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct pci_id_table pci_dev_descr_sbridge_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* This changes depending if 1HA or 2HA:</div><div class='hunk'>@@ -505,7 +505,7 @@ static const struct pci_id_descr pci_dev_descr_ibridge[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct pci_id_table pci_dev_descr_ibridge_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Haswell support */</div><div class='hunk'>@@ -576,7 +576,7 @@ static const struct pci_id_descr pci_dev_descr_haswell[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct pci_id_table pci_dev_descr_haswell_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Knight's Landing Support */</div><div class='hunk'>@@ -620,7 +620,7 @@ static const struct pci_id_descr pci_dev_descr_knl[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct pci_id_table pci_dev_descr_knl_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),</div><div class='del'>-	{0,}</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -686,7 +686,7 @@ static const struct pci_id_descr pci_dev_descr_broadwell[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct pci_id_table pci_dev_descr_broadwell_table[] = {</div><div class='ctx'> 	PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),</div><div class='del'>-	{0,}			/* 0 terminated list. */</div><div class='add'>+	{ NULL, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c<br/>index ce3e0069e028..9c5b6f8bd8bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/skx_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/skx_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/skx_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/skx_common.c</a></div><div class='hunk'>@@ -648,6 +648,10 @@ int skx_mce_check_error(struct notifier_block *nb, unsigned long val,</div><div class='ctx'> 	memset(&amp;res, 0, sizeof(res));</div><div class='ctx'> 	res.mce  = mce;</div><div class='ctx'> 	res.addr = mce-&gt;addr &amp; MCI_ADDR_PHYSADDR;</div><div class='add'>+	if (!pfn_to_online_page(res.addr &gt;&gt; PAGE_SHIFT)) {</div><div class='add'>+		pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce-&gt;addr, mce-&gt;bank);</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Try driver decoder first */</div><div class='ctx'> 	if (!(driver_decode &amp;&amp; driver_decode(&amp;res))) {</div><div class='head'>diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c<br/>index c4fc64cbecd0..709babce43ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/synopsys_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/synopsys_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/synopsys_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/synopsys_edac.c</a></div><div class='hunk'>@@ -1410,7 +1410,7 @@ free_edac_mc:</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Unconditionally 0</div><div class='ctx'>  */</div><div class='del'>-static int mc_remove(struct platform_device *pdev)</div><div class='add'>+static void mc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct synps_edac_priv *priv = mci-&gt;pvt_info;</div><div class='hunk'>@@ -1425,8 +1425,6 @@ static int mc_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver synps_edac_mc_driver = {</div><div class='hunk'>@@ -1435,7 +1433,7 @@ static struct platform_driver synps_edac_mc_driver = {</div><div class='ctx'> 		   .of_match_table = synps_edac_match,</div><div class='ctx'> 		   },</div><div class='ctx'> 	.probe = mc_probe,</div><div class='del'>-	.remove = mc_remove,</div><div class='add'>+	.remove_new = mc_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(synps_edac_mc_driver);</div><div class='head'>diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c<br/>index b9c5772da959..90d46e5c4ff0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/thunderx_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/thunderx_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/thunderx_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/thunderx_edac.c</a></div><div class='hunk'>@@ -1133,7 +1133,7 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id)</div><div class='ctx'> 		decode_register(other, OCX_OTHER_SIZE,</div><div class='ctx'> 				ocx_com_errors, ctx-&gt;reg_com_int);</div><div class='ctx'> </div><div class='del'>-		strncat(msg, other, OCX_MESSAGE_SIZE);</div><div class='add'>+		strlcat(msg, other, OCX_MESSAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 		for (lane = 0; lane &lt; OCX_RX_LANES; lane++)</div><div class='ctx'> 			if (ctx-&gt;reg_com_int &amp; BIT(lane)) {</div><div class='hunk'>@@ -1142,12 +1142,12 @@ static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id)</div><div class='ctx'> 					 lane, ctx-&gt;reg_lane_int[lane],</div><div class='ctx'> 					 lane, ctx-&gt;reg_lane_stat11[lane]);</div><div class='ctx'> </div><div class='del'>-				strncat(msg, other, OCX_MESSAGE_SIZE);</div><div class='add'>+				strlcat(msg, other, OCX_MESSAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 				decode_register(other, OCX_OTHER_SIZE,</div><div class='ctx'> 						ocx_lane_errors,</div><div class='ctx'> 						ctx-&gt;reg_lane_int[lane]);</div><div class='del'>-				strncat(msg, other, OCX_MESSAGE_SIZE);</div><div class='add'>+				strlcat(msg, other, OCX_MESSAGE_SIZE);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 		if (ctx-&gt;reg_com_int &amp; OCX_COM_INT_CE)</div><div class='hunk'>@@ -1217,7 +1217,7 @@ static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id)</div><div class='ctx'> 		decode_register(other, OCX_OTHER_SIZE,</div><div class='ctx'> 				ocx_com_link_errors, ctx-&gt;reg_com_link_int);</div><div class='ctx'> </div><div class='del'>-		strncat(msg, other, OCX_MESSAGE_SIZE);</div><div class='add'>+		strlcat(msg, other, OCX_MESSAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 		if (ctx-&gt;reg_com_link_int &amp; OCX_COM_LINK_INT_UE)</div><div class='ctx'> 			edac_device_handle_ue(ocx-&gt;edac_dev, 0, 0, msg);</div><div class='hunk'>@@ -1896,7 +1896,7 @@ static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id)</div><div class='ctx'> </div><div class='ctx'> 		decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx-&gt;reg_int);</div><div class='ctx'> </div><div class='del'>-		strncat(msg, other, L2C_MESSAGE_SIZE);</div><div class='add'>+		strlcat(msg, other, L2C_MESSAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 		if (ctx-&gt;reg_int &amp; mask_ue)</div><div class='ctx'> 			edac_device_handle_ue(l2c-&gt;edac_dev, 0, 0, msg);</div><div class='head'>diff --git a/drivers/edac/ti_edac.c b/drivers/edac/ti_edac.c<br/>index 6971ded598de..29723c9592f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/ti_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/ti_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/ti_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/ti_edac.c</a></div><div class='hunk'>@@ -312,19 +312,17 @@ err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ti_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void ti_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	edac_mc_del_mc(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_mc_free(mci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ti_edac_driver = {</div><div class='ctx'> 	.probe = ti_edac_probe,</div><div class='del'>-	.remove = ti_edac_remove,</div><div class='add'>+	.remove_new = ti_edac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = EDAC_MOD_NAME,</div><div class='ctx'> 		   .of_match_table = ti_edac_of_match,</div><div class='head'>diff --git a/drivers/edac/versal_edac.c b/drivers/edac/versal_edac.c<br/>index 87e730dfefa0..62caf454b567 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/versal_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/versal_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/versal_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/versal_edac.c</a></div><div class='hunk'>@@ -966,10 +966,10 @@ static int mc_probe(struct platform_device *pdev)</div><div class='ctx'> 	edac_mc_id = emif_get_id(pdev-&gt;dev.of_node);</div><div class='ctx'> </div><div class='ctx'> 	regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);</div><div class='del'>-	num_chans = FIELD_PREP(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);</div><div class='add'>+	num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval);</div><div class='ctx'> 	num_chans++;</div><div class='ctx'> </div><div class='del'>-	num_csrows = FIELD_PREP(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);</div><div class='add'>+	num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval);</div><div class='ctx'> 	num_csrows *= 2;</div><div class='ctx'> 	if (!num_csrows)</div><div class='ctx'> 		num_csrows = 1;</div><div class='hunk'>@@ -1005,7 +1005,7 @@ static int mc_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto free_edac_mc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = xlnx_register_event(PM_NOTIFY_CB, EVENT_ERROR_PMC_ERR1,</div><div class='add'>+	rc = xlnx_register_event(PM_NOTIFY_CB, VERSAL_EVENT_ERROR_PMC_ERR1,</div><div class='ctx'> 				 XPM_EVENT_ERROR_MASK_DDRMC_CR | XPM_EVENT_ERROR_MASK_DDRMC_NCR |</div><div class='ctx'> 				 XPM_EVENT_ERROR_MASK_NOC_CR | XPM_EVENT_ERROR_MASK_NOC_NCR,</div><div class='ctx'> 				 false, err_callback, mci);</div><div class='hunk'>@@ -1042,7 +1042,7 @@ static int mc_remove(struct platform_device *pdev)</div><div class='ctx'> 	debugfs_remove_recursive(priv-&gt;debugfs);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-	xlnx_unregister_event(PM_NOTIFY_CB, EVENT_ERROR_PMC_ERR1,</div><div class='add'>+	xlnx_unregister_event(PM_NOTIFY_CB, VERSAL_EVENT_ERROR_PMC_ERR1,</div><div class='ctx'> 			      XPM_EVENT_ERROR_MASK_DDRMC_CR |</div><div class='ctx'> 			      XPM_EVENT_ERROR_MASK_NOC_CR |</div><div class='ctx'> 			      XPM_EVENT_ERROR_MASK_NOC_NCR |</div><div class='head'>diff --git a/drivers/edac/xgene_edac.c b/drivers/edac/xgene_edac.c<br/>index c52b9dd9154c..1b50f8160013 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/xgene_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/xgene_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/xgene_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/xgene_edac.c</a></div><div class='hunk'>@@ -1960,7 +1960,7 @@ out_err:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xgene_edac_remove(struct platform_device *pdev)</div><div class='add'>+static void xgene_edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct xgene_edac *edac = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct xgene_edac_mc_ctx *mcu;</div><div class='hunk'>@@ -1981,8 +1981,6 @@ static int xgene_edac_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(node, temp_node, &amp;edac-&gt;socs, next)</div><div class='ctx'> 		xgene_edac_soc_remove(node);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id xgene_edac_of_match[] = {</div><div class='hunk'>@@ -1993,7 +1991,7 @@ MODULE_DEVICE_TABLE(of, xgene_edac_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver xgene_edac_driver = {</div><div class='ctx'> 	.probe = xgene_edac_probe,</div><div class='del'>-	.remove = xgene_edac_remove,</div><div class='add'>+	.remove_new = xgene_edac_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "xgene-edac",</div><div class='ctx'> 		.of_match_table = xgene_edac_of_match,</div><div class='head'>diff --git a/drivers/edac/zynqmp_edac.c b/drivers/edac/zynqmp_edac.c<br/>index ac7d1e0b324c..2d9a5cfd8931 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/edac/zynqmp_edac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/edac/zynqmp_edac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/edac/zynqmp_edac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/edac/zynqmp_edac.c</a></div><div class='hunk'>@@ -426,7 +426,7 @@ free_dev_ctl:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int edac_remove(struct platform_device *pdev)</div><div class='add'>+static void edac_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct edac_priv *priv = dci-&gt;pvt_info;</div><div class='hunk'>@@ -440,8 +440,6 @@ static int edac_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	edac_device_del_device(&amp;pdev-&gt;dev);</div><div class='ctx'> 	edac_device_free_ctl_info(dci);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id zynqmp_ocm_edac_match[] = {</div><div class='hunk'>@@ -457,7 +455,7 @@ static struct platform_driver zynqmp_ocm_edac_driver = {</div><div class='ctx'> 		   .of_match_table = zynqmp_ocm_edac_match,</div><div class='ctx'> 		   },</div><div class='ctx'> 	.probe = edac_probe,</div><div class='del'>-	.remove = edac_remove,</div><div class='add'>+	.remove_new = edac_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(zynqmp_ocm_edac_driver);</div><div class='head'>diff --git a/drivers/extcon/extcon-qcom-spmi-misc.c b/drivers/extcon/extcon-qcom-spmi-misc.c<br/>index f72e90ceca53..53de581a393a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/extcon/extcon-qcom-spmi-misc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/extcon/extcon-qcom-spmi-misc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/extcon/extcon-qcom-spmi-misc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon-qcom-spmi-misc.c</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-/**</div><div class='add'>+/*</div><div class='ctx'>  * extcon-qcom-spmi-misc.c - Qualcomm USB extcon driver to support USB ID</div><div class='ctx'>  *			and VBUS detection based on extcon-usb-gpio.c.</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/extcon/extcon-usbc-tusb320.c b/drivers/extcon/extcon-usbc-tusb320.c<br/>index 4d08c2123e59..2eab341de6b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/extcon/extcon-usbc-tusb320.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/extcon/extcon-usbc-tusb320.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/extcon/extcon-usbc-tusb320.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon-usbc-tusb320.c</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> #include &lt;linux/usb/typec.h&gt;</div><div class='ctx'> #include &lt;linux/usb/typec_altmode.h&gt;</div><div class='ctx'> #include &lt;linux/usb/role.h&gt;</div><div class='add'>+#include &lt;linux/irq.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define TUSB320_REG8				0x8</div><div class='ctx'> #define TUSB320_REG8_CURRENT_MODE_ADVERTISE	GENMASK(7, 6)</div><div class='hunk'>@@ -515,6 +516,8 @@ static int tusb320_probe(struct i2c_client *client)</div><div class='ctx'> 	const void *match_data;</div><div class='ctx'> 	unsigned int revision;</div><div class='ctx'> 	int ret;</div><div class='add'>+	u32 irq_trigger_type = IRQF_TRIGGER_FALLING;</div><div class='add'>+	struct irq_data *irq_d;</div><div class='ctx'> </div><div class='ctx'> 	priv = devm_kzalloc(&amp;client-&gt;dev, sizeof(*priv), GFP_KERNEL);</div><div class='ctx'> 	if (!priv)</div><div class='hunk'>@@ -568,9 +571,13 @@ static int tusb320_probe(struct i2c_client *client)</div><div class='ctx'> 		 */</div><div class='ctx'> 		tusb320_state_update_handler(priv, true);</div><div class='ctx'> </div><div class='add'>+	irq_d = irq_get_irq_data(client-&gt;irq);</div><div class='add'>+	if (irq_d)</div><div class='add'>+		irq_trigger_type = irqd_get_trigger_type(irq_d);</div><div class='add'>+</div><div class='ctx'> 	ret = devm_request_threaded_irq(priv-&gt;dev, client-&gt;irq, NULL,</div><div class='ctx'> 					tusb320_irq_handler,</div><div class='del'>-					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,</div><div class='add'>+					IRQF_ONESHOT | irq_trigger_type,</div><div class='ctx'> 					client-&gt;name, priv);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		tusb320_typec_remove(priv);</div><div class='head'>diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c<br/>index 6f7a60d2ed91..e7f55c021e56 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/extcon/extcon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/extcon/extcon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/extcon/extcon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/extcon/extcon.c</a></div><div class='hunk'>@@ -1280,8 +1280,6 @@ int extcon_dev_register(struct extcon_dev *edev)</div><div class='ctx'> </div><div class='ctx'> 	edev-&gt;id = ret;</div><div class='ctx'> </div><div class='del'>-	dev_set_name(&amp;edev-&gt;dev, "extcon%d", edev-&gt;id);</div><div class='del'>-</div><div class='ctx'> 	ret = extcon_alloc_cables(edev);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto err_alloc_cables;</div><div class='hunk'>@@ -1310,6 +1308,7 @@ int extcon_dev_register(struct extcon_dev *edev)</div><div class='ctx'> 	RAW_INIT_NOTIFIER_HEAD(&amp;edev-&gt;nh_all);</div><div class='ctx'> </div><div class='ctx'> 	dev_set_drvdata(&amp;edev-&gt;dev, edev);</div><div class='add'>+	dev_set_name(&amp;edev-&gt;dev, "extcon%d", edev-&gt;id);</div><div class='ctx'> 	edev-&gt;state = 0;</div><div class='ctx'> </div><div class='ctx'> 	ret = device_register(&amp;edev-&gt;dev);</div><div class='head'>diff --git a/drivers/firewire/.kunitconfig b/drivers/firewire/.kunitconfig<br/>index 1599e069395f..76444a2d5e12 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firewire/.kunitconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firewire/.kunitconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/.kunitconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/.kunitconfig</a></div><div class='hunk'>@@ -2,3 +2,4 @@ CONFIG_KUNIT=y</div><div class='ctx'> CONFIG_PCI=y</div><div class='ctx'> CONFIG_FIREWIRE=y</div><div class='ctx'> CONFIG_FIREWIRE_KUNIT_UAPI_TEST=y</div><div class='add'>+CONFIG_FIREWIRE_KUNIT_DEVICE_ATTRIBUTE_TEST=y</div><div class='head'>diff --git a/drivers/firewire/Kconfig b/drivers/firewire/Kconfig<br/>index 0a6596b027db..552a39df8cbd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firewire/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firewire/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/Kconfig</a></div><div class='hunk'>@@ -34,6 +34,22 @@ config FIREWIRE_KUNIT_UAPI_TEST</div><div class='ctx'> 	  For more information on KUnit and unit tests in general, refer</div><div class='ctx'> 	  to the KUnit documentation in Documentation/dev-tools/kunit/.</div><div class='ctx'> </div><div class='add'>+config FIREWIRE_KUNIT_DEVICE_ATTRIBUTE_TEST</div><div class='add'>+	tristate "KUnit tests for device attributes" if !KUNIT_ALL_TESTS</div><div class='add'>+	depends on FIREWIRE &amp;&amp; KUNIT</div><div class='add'>+	default KUNIT_ALL_TESTS</div><div class='add'>+	help</div><div class='add'>+	  This builds the KUnit tests for device attribute for node and</div><div class='add'>+	  unit.</div><div class='add'>+</div><div class='add'>+	  KUnit tests run during boot and output the results to the debug</div><div class='add'>+	  log in TAP format (https://testanything.org/). Only useful for</div><div class='add'>+	  kernel devs running KUnit test harness and are not for inclusion</div><div class='add'>+	  into a production build.</div><div class='add'>+</div><div class='add'>+	  For more information on KUnit and unit tests in general, refer</div><div class='add'>+	  to the KUnit documentation in Documentation/dev-tools/kunit/.</div><div class='add'>+</div><div class='ctx'> config FIREWIRE_OHCI</div><div class='ctx'> 	tristate "OHCI-1394 controllers"</div><div class='ctx'> 	depends on PCI &amp;&amp; FIREWIRE &amp;&amp; MMU</div><div class='head'>diff --git a/drivers/firewire/core-device.c b/drivers/firewire/core-device.c<br/>index aa597cda0d88..0547253d16fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firewire/core-device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firewire/core-device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/core-device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/core-device.c</a></div><div class='hunk'>@@ -31,6 +31,8 @@</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='ctx'> </div><div class='add'>+#define ROOT_DIR_OFFSET	5</div><div class='add'>+</div><div class='ctx'> void fw_csr_iterator_init(struct fw_csr_iterator *ci, const u32 *p)</div><div class='ctx'> {</div><div class='ctx'> 	ci-&gt;p = p + 1;</div><div class='hunk'>@@ -47,6 +49,22 @@ int fw_csr_iterator_next(struct fw_csr_iterator *ci, int *key, int *value)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(fw_csr_iterator_next);</div><div class='ctx'> </div><div class='add'>+static const u32 *search_directory(const u32 *directory, int search_key)</div><div class='add'>+{</div><div class='add'>+	struct fw_csr_iterator ci;</div><div class='add'>+	int key, value;</div><div class='add'>+</div><div class='add'>+	search_key |= CSR_DIRECTORY;</div><div class='add'>+</div><div class='add'>+	fw_csr_iterator_init(&amp;ci, directory);</div><div class='add'>+	while (fw_csr_iterator_next(&amp;ci, &amp;key, &amp;value)) {</div><div class='add'>+		if (key == search_key)</div><div class='add'>+			return ci.p - 1 + value;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const u32 *search_leaf(const u32 *directory, int search_key)</div><div class='ctx'> {</div><div class='ctx'> 	struct fw_csr_iterator ci;</div><div class='hunk'>@@ -135,8 +153,25 @@ static void get_ids(const u32 *directory, int *id)</div><div class='ctx'> </div><div class='ctx'> static void get_modalias_ids(const struct fw_unit *unit, int *id)</div><div class='ctx'> {</div><div class='del'>-	get_ids(&amp;fw_parent_device(unit)-&gt;config_rom[5], id);</div><div class='del'>-	get_ids(unit-&gt;directory, id);</div><div class='add'>+	const u32 *root_directory = &amp;fw_parent_device(unit)-&gt;config_rom[ROOT_DIR_OFFSET];</div><div class='add'>+	const u32 *directories[] = {NULL, NULL, NULL};</div><div class='add'>+	const u32 *vendor_directory;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	directories[0] = root_directory;</div><div class='add'>+</div><div class='add'>+	// Legacy layout of configuration ROM described in Annex 1 of 'Configuration ROM for AV/C</div><div class='add'>+	// Devices 1.0 (December 12, 2000, 1394 Trading Association, TA Document 1999027)'.</div><div class='add'>+	vendor_directory = search_directory(root_directory, CSR_VENDOR);</div><div class='add'>+	if (!vendor_directory) {</div><div class='add'>+		directories[1] = unit-&gt;directory;</div><div class='add'>+	} else {</div><div class='add'>+		directories[1] = vendor_directory;</div><div class='add'>+		directories[2] = unit-&gt;directory;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(directories) &amp;&amp; !!directories[i]; ++i)</div><div class='add'>+		get_ids(directories[i], id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool match_ids(const struct ieee1394_device_id *id_table, int *id)</div><div class='hunk'>@@ -171,7 +206,7 @@ static const struct ieee1394_device_id *unit_match(struct device *dev,</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool is_fw_unit(struct device *dev);</div><div class='add'>+static bool is_fw_unit(const struct device *dev);</div><div class='ctx'> </div><div class='ctx'> static int fw_unit_match(struct device *dev, struct device_driver *drv)</div><div class='ctx'> {</div><div class='hunk'>@@ -219,7 +254,7 @@ static int fw_unit_uevent(const struct device *dev, struct kobj_uevent_env *env)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct bus_type fw_bus_type = {</div><div class='add'>+const struct bus_type fw_bus_type = {</div><div class='ctx'> 	.name = "firewire",</div><div class='ctx'> 	.match = fw_unit_match,</div><div class='ctx'> 	.probe = fw_unit_probe,</div><div class='hunk'>@@ -251,27 +286,44 @@ static ssize_t show_immediate(struct device *dev,</div><div class='ctx'> 	struct config_rom_attribute *attr =</div><div class='ctx'> 		container_of(dattr, struct config_rom_attribute, attr);</div><div class='ctx'> 	struct fw_csr_iterator ci;</div><div class='del'>-	const u32 *dir;</div><div class='del'>-	int key, value, ret = -ENOENT;</div><div class='add'>+	const u32 *directories[] = {NULL, NULL};</div><div class='add'>+	int i, value = -1;</div><div class='ctx'> </div><div class='ctx'> 	down_read(&amp;fw_device_rwsem);</div><div class='ctx'> </div><div class='del'>-	if (is_fw_unit(dev))</div><div class='del'>-		dir = fw_unit(dev)-&gt;directory;</div><div class='del'>-	else</div><div class='del'>-		dir = fw_device(dev)-&gt;config_rom + 5;</div><div class='add'>+	if (is_fw_unit(dev)) {</div><div class='add'>+		directories[0] = fw_unit(dev)-&gt;directory;</div><div class='add'>+	} else {</div><div class='add'>+		const u32 *root_directory = fw_device(dev)-&gt;config_rom + ROOT_DIR_OFFSET;</div><div class='add'>+		const u32 *vendor_directory = search_directory(root_directory, CSR_VENDOR);</div><div class='ctx'> </div><div class='del'>-	fw_csr_iterator_init(&amp;ci, dir);</div><div class='del'>-	while (fw_csr_iterator_next(&amp;ci, &amp;key, &amp;value))</div><div class='del'>-		if (attr-&gt;key == key) {</div><div class='del'>-			ret = snprintf(buf, buf ? PAGE_SIZE : 0,</div><div class='del'>-				       "0x%06x\n", value);</div><div class='del'>-			break;</div><div class='add'>+		if (!vendor_directory) {</div><div class='add'>+			directories[0] = root_directory;</div><div class='add'>+		} else {</div><div class='add'>+			// Legacy layout of configuration ROM described in Annex 1 of</div><div class='add'>+			// 'Configuration ROM for AV/C Devices 1.0 (December 12, 2000, 1394 Trading</div><div class='add'>+			// Association, TA Document 1999027)'.</div><div class='add'>+			directories[0] = vendor_directory;</div><div class='add'>+			directories[1] = root_directory;</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(directories) &amp;&amp; !!directories[i]; ++i) {</div><div class='add'>+		int key, val;</div><div class='add'>+</div><div class='add'>+		fw_csr_iterator_init(&amp;ci, directories[i]);</div><div class='add'>+		while (fw_csr_iterator_next(&amp;ci, &amp;key, &amp;val)) {</div><div class='add'>+			if (attr-&gt;key == key)</div><div class='add'>+				value = val;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	up_read(&amp;fw_device_rwsem);</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	if (value &lt; 0)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	return snprintf(buf, buf ? PAGE_SIZE : 0, "0x%06x\n", value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define IMMEDIATE_ATTR(name, key)				\</div><div class='hunk'>@@ -282,17 +334,29 @@ static ssize_t show_text_leaf(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct config_rom_attribute *attr =</div><div class='ctx'> 		container_of(dattr, struct config_rom_attribute, attr);</div><div class='del'>-	const u32 *dir;</div><div class='add'>+	const u32 *directories[] = {NULL, NULL};</div><div class='ctx'> 	size_t bufsize;</div><div class='ctx'> 	char dummy_buf[2];</div><div class='del'>-	int ret;</div><div class='add'>+	int i, ret = -ENOENT;</div><div class='ctx'> </div><div class='ctx'> 	down_read(&amp;fw_device_rwsem);</div><div class='ctx'> </div><div class='del'>-	if (is_fw_unit(dev))</div><div class='del'>-		dir = fw_unit(dev)-&gt;directory;</div><div class='del'>-	else</div><div class='del'>-		dir = fw_device(dev)-&gt;config_rom + 5;</div><div class='add'>+	if (is_fw_unit(dev)) {</div><div class='add'>+		directories[0] = fw_unit(dev)-&gt;directory;</div><div class='add'>+	} else {</div><div class='add'>+		const u32 *root_directory = fw_device(dev)-&gt;config_rom + ROOT_DIR_OFFSET;</div><div class='add'>+		const u32 *vendor_directory = search_directory(root_directory, CSR_VENDOR);</div><div class='add'>+</div><div class='add'>+		if (!vendor_directory) {</div><div class='add'>+			directories[0] = root_directory;</div><div class='add'>+		} else {</div><div class='add'>+			// Legacy layout of configuration ROM described in Annex 1 of</div><div class='add'>+			// 'Configuration ROM for AV/C Devices 1.0 (December 12, 2000, 1394</div><div class='add'>+			// Trading Association, TA Document 1999027)'.</div><div class='add'>+			directories[0] = root_directory;</div><div class='add'>+			directories[1] = vendor_directory;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (buf) {</div><div class='ctx'> 		bufsize = PAGE_SIZE - 1;</div><div class='hunk'>@@ -301,7 +365,12 @@ static ssize_t show_text_leaf(struct device *dev,</div><div class='ctx'> 		bufsize = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = fw_csr_string(dir, attr-&gt;key, buf, bufsize);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(directories) &amp;&amp; !!directories[i]; ++i) {</div><div class='add'>+		int result = fw_csr_string(directories[i], attr-&gt;key, buf, bufsize);</div><div class='add'>+		// Detected.</div><div class='add'>+		if (result &gt;= 0)</div><div class='add'>+			ret = result;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (ret &gt;= 0) {</div><div class='ctx'> 		/* Strip trailing whitespace and add newline. */</div><div class='hunk'>@@ -446,7 +515,7 @@ static ssize_t units_show(struct device *dev,</div><div class='ctx'> 	int key, value, i = 0;</div><div class='ctx'> </div><div class='ctx'> 	down_read(&amp;fw_device_rwsem);</div><div class='del'>-	fw_csr_iterator_init(&amp;ci, &amp;device-&gt;config_rom[5]);</div><div class='add'>+	fw_csr_iterator_init(&amp;ci, &amp;device-&gt;config_rom[ROOT_DIR_OFFSET]);</div><div class='ctx'> 	while (fw_csr_iterator_next(&amp;ci, &amp;key, &amp;value)) {</div><div class='ctx'> 		if (key != (CSR_UNIT | CSR_DIRECTORY))</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -679,7 +748,7 @@ static struct device_type fw_unit_type = {</div><div class='ctx'> 	.release	= fw_unit_release,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static bool is_fw_unit(struct device *dev)</div><div class='add'>+static bool is_fw_unit(const struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	return dev-&gt;type == &amp;fw_unit_type;</div><div class='ctx'> }</div><div class='hunk'>@@ -691,7 +760,7 @@ static void create_units(struct fw_device *device)</div><div class='ctx'> 	int key, value, i;</div><div class='ctx'> </div><div class='ctx'> 	i = 0;</div><div class='del'>-	fw_csr_iterator_init(&amp;ci, &amp;device-&gt;config_rom[5]);</div><div class='add'>+	fw_csr_iterator_init(&amp;ci, &amp;device-&gt;config_rom[ROOT_DIR_OFFSET]);</div><div class='ctx'> 	while (fw_csr_iterator_next(&amp;ci, &amp;key, &amp;value)) {</div><div class='ctx'> 		if (key != (CSR_UNIT | CSR_DIRECTORY))</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -717,14 +786,11 @@ static void create_units(struct fw_device *device)</div><div class='ctx'> 					fw_unit_attributes,</div><div class='ctx'> 					&amp;unit-&gt;attribute_group);</div><div class='ctx'> </div><div class='del'>-		if (device_register(&amp;unit-&gt;device) &lt; 0)</div><div class='del'>-			goto skip_unit;</div><div class='del'>-</div><div class='ctx'> 		fw_device_get(device);</div><div class='del'>-		continue;</div><div class='del'>-</div><div class='del'>-	skip_unit:</div><div class='del'>-		kfree(unit);</div><div class='add'>+		if (device_register(&amp;unit-&gt;device) &lt; 0) {</div><div class='add'>+			put_device(&amp;unit-&gt;device);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -838,7 +904,7 @@ static struct device_type fw_device_type = {</div><div class='ctx'> 	.release = fw_device_release,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static bool is_fw_device(struct device *dev)</div><div class='add'>+static bool is_fw_device(const struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	return dev-&gt;type == &amp;fw_device_type;</div><div class='ctx'> }</div><div class='hunk'>@@ -1311,3 +1377,7 @@ void fw_node_event(struct fw_card *card, struct fw_node *node, int event)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_FIREWIRE_KUNIT_DEVICE_ATTRIBUTE_TEST</div><div class='add'>+#include "device-attribute-test.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/firewire/device-attribute-test.c b/drivers/firewire/device-attribute-test.c<br/>new file mode 100644<br/>index 000000000000..2f123c6b0a16<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/device-attribute-test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/device-attribute-test.c</a></div><div class='hunk'>@@ -0,0 +1,251 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+//</div><div class='add'>+// device-attribute-test.c - An application of Kunit to test implementation for device attributes.</div><div class='add'>+//</div><div class='add'>+// Copyright (c) 2023 Takashi Sakamoto</div><div class='add'>+//</div><div class='add'>+// This file can not be built independently since it is intentionally included in core-device.c.</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+// Configuration ROM for AV/C Devices 1.0 (Dec. 12, 2000, 1394 Trading Association)</div><div class='add'>+// Annex C:Configuration ROM example(informative)</div><div class='add'>+// C.1 Simple AV/C device</div><div class='add'>+//</div><div class='add'>+// Copied from the documentation.</div><div class='add'>+static const u32 simple_avc_config_rom[] = {</div><div class='add'>+	0x0404eabf,</div><div class='add'>+	0x31333934,</div><div class='add'>+	0xe0646102,</div><div class='add'>+	0xffffffff,</div><div class='add'>+	0xffffffff,</div><div class='add'>+	0x00063287, // root directory.</div><div class='add'>+	0x03ffffff,</div><div class='add'>+	0x8100000a,</div><div class='add'>+	0x17ffffff,</div><div class='add'>+	0x8100000e,</div><div class='add'>+	0x0c0083c0,</div><div class='add'>+	0xd1000001,</div><div class='add'>+	0x0004442d, // unit 0 directory.</div><div class='add'>+	0x1200a02d,</div><div class='add'>+	0x13010001,</div><div class='add'>+	0x17ffffff,</div><div class='add'>+	0x81000007,</div><div class='add'>+	0x0005c915, // leaf for textual descriptor.</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x56656e64,</div><div class='add'>+	0x6f72204e,</div><div class='add'>+	0x616d6500,</div><div class='add'>+	0x00057f16, // leaf for textual descriptor.</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x4d6f6465,</div><div class='add'>+	0x6c204e61,</div><div class='add'>+	0x6d650000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+// Ibid.</div><div class='add'>+// Annex A:Consideration for configuration ROM reader design (informative)</div><div class='add'>+// A.1 Vendor directory</div><div class='add'>+//</div><div class='add'>+// Written by hand.</div><div class='add'>+static const u32 legacy_avc_config_rom[] = {</div><div class='add'>+	0x04199fe7,</div><div class='add'>+	0x31333934,</div><div class='add'>+	0xe0644000,</div><div class='add'>+	0x00112233,</div><div class='add'>+	0x44556677,</div><div class='add'>+	0x0005dace, // root directory.</div><div class='add'>+	0x03012345,</div><div class='add'>+	0x0c0083c0,</div><div class='add'>+	0x8d000009,</div><div class='add'>+	0xd1000002,</div><div class='add'>+	0xc3000004,</div><div class='add'>+	0x0002e107, // unit 0 directory.</div><div class='add'>+	0x12abcdef,</div><div class='add'>+	0x13543210,</div><div class='add'>+	0x0002cb73, // vendor directory.</div><div class='add'>+	0x17fedcba,</div><div class='add'>+	0x81000004,</div><div class='add'>+	0x00026dc1, // leaf for EUI-64.</div><div class='add'>+	0x00112233,</div><div class='add'>+	0x44556677,</div><div class='add'>+	0x00050e84, // leaf for textual descriptor.</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x00000000,</div><div class='add'>+	0x41424344,</div><div class='add'>+	0x45464748,</div><div class='add'>+	0x494a0000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void device_attr_simple_avc(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	static const struct fw_device node = {</div><div class='add'>+		.device = {</div><div class='add'>+			.type = &amp;fw_device_type,</div><div class='add'>+		},</div><div class='add'>+		.config_rom = simple_avc_config_rom,</div><div class='add'>+		.config_rom_length = sizeof(simple_avc_config_rom),</div><div class='add'>+	};</div><div class='add'>+	static const struct fw_unit unit0 = {</div><div class='add'>+		.device = {</div><div class='add'>+			.type = &amp;fw_unit_type,</div><div class='add'>+			.parent = (struct device *)&amp;node.device,</div><div class='add'>+		},</div><div class='add'>+		.directory = &amp;simple_avc_config_rom[12],</div><div class='add'>+	};</div><div class='add'>+	struct device *node_dev = (struct device *)&amp;node.device;</div><div class='add'>+	struct device *unit0_dev = (struct device *)&amp;unit0.device;</div><div class='add'>+	static const int unit0_expected_ids[] = {0x00ffffff, 0x00ffffff, 0x0000a02d, 0x00010001};</div><div class='add'>+	char *buf = kunit_kzalloc(test, PAGE_SIZE, GFP_KERNEL);</div><div class='add'>+	int ids[4] = {0, 0, 0, 0};</div><div class='add'>+</div><div class='add'>+	// Ensure associations for node and unit devices.</div><div class='add'>+</div><div class='add'>+	KUNIT_ASSERT_TRUE(test, is_fw_device(node_dev));</div><div class='add'>+	KUNIT_ASSERT_FALSE(test, is_fw_unit(node_dev));</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_device(node_dev), &amp;node);</div><div class='add'>+</div><div class='add'>+	KUNIT_ASSERT_FALSE(test, is_fw_device(unit0_dev));</div><div class='add'>+	KUNIT_ASSERT_TRUE(test, is_fw_unit(unit0_dev));</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_parent_device((&amp;unit0)), &amp;node);</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_unit(unit0_dev), &amp;unit0);</div><div class='add'>+</div><div class='add'>+	// For entries in root directory.</div><div class='add'>+</div><div class='add'>+	// Vendor immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(node_dev, &amp;config_rom_attributes[0].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0xffffff\n");</div><div class='add'>+</div><div class='add'>+	// Model immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(node_dev, &amp;config_rom_attributes[4].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0xffffff\n");</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for vendor is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_text_leaf(node_dev, &amp;config_rom_attributes[5].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "Vendor Name\n");</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for model is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_text_leaf(node_dev, &amp;config_rom_attributes[6].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "Model Name\n");</div><div class='add'>+</div><div class='add'>+	// For entries in unit 0 directory.</div><div class='add'>+</div><div class='add'>+	// Vendor immediate entry is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[0].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Model immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[4].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0xffffff\n");</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for vendor is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_text_leaf(unit0_dev, &amp;config_rom_attributes[5].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for model is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_text_leaf(unit0_dev, &amp;config_rom_attributes[6].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "Model Name\n");</div><div class='add'>+</div><div class='add'>+	// Specifier_ID immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[2].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0x00a02d\n");</div><div class='add'>+</div><div class='add'>+	// Version immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[3].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0x010001\n");</div><div class='add'>+</div><div class='add'>+	kunit_kfree(test, buf);</div><div class='add'>+</div><div class='add'>+	get_modalias_ids(&amp;unit0, ids);</div><div class='add'>+	KUNIT_EXPECT_MEMEQ(test, ids, unit0_expected_ids, sizeof(ids));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void device_attr_legacy_avc(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	static const struct fw_device node = {</div><div class='add'>+		.device = {</div><div class='add'>+			.type = &amp;fw_device_type,</div><div class='add'>+		},</div><div class='add'>+		.config_rom = legacy_avc_config_rom,</div><div class='add'>+		.config_rom_length = sizeof(legacy_avc_config_rom),</div><div class='add'>+	};</div><div class='add'>+	static const struct fw_unit unit0 = {</div><div class='add'>+		.device = {</div><div class='add'>+			.type = &amp;fw_unit_type,</div><div class='add'>+			.parent = (struct device *)&amp;node.device,</div><div class='add'>+		},</div><div class='add'>+		.directory = &amp;legacy_avc_config_rom[11],</div><div class='add'>+	};</div><div class='add'>+	struct device *node_dev = (struct device *)&amp;node.device;</div><div class='add'>+	struct device *unit0_dev = (struct device *)&amp;unit0.device;</div><div class='add'>+	static const int unit0_expected_ids[] = {0x00012345, 0x00fedcba, 0x00abcdef, 0x00543210};</div><div class='add'>+	char *buf = kunit_kzalloc(test, PAGE_SIZE, GFP_KERNEL);</div><div class='add'>+	int ids[4] = {0, 0, 0, 0};</div><div class='add'>+</div><div class='add'>+	// Ensure associations for node and unit devices.</div><div class='add'>+</div><div class='add'>+	KUNIT_ASSERT_TRUE(test, is_fw_device(node_dev));</div><div class='add'>+	KUNIT_ASSERT_FALSE(test, is_fw_unit(node_dev));</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_device((node_dev)), &amp;node);</div><div class='add'>+</div><div class='add'>+	KUNIT_ASSERT_FALSE(test, is_fw_device(unit0_dev));</div><div class='add'>+	KUNIT_ASSERT_TRUE(test, is_fw_unit(unit0_dev));</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_parent_device((&amp;unit0)), &amp;node);</div><div class='add'>+	KUNIT_ASSERT_PTR_EQ(test, fw_unit(unit0_dev), &amp;unit0);</div><div class='add'>+</div><div class='add'>+	// For entries in root directory.</div><div class='add'>+</div><div class='add'>+	// Vendor immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(node_dev, &amp;config_rom_attributes[0].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0x012345\n");</div><div class='add'>+</div><div class='add'>+	// Model immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(node_dev, &amp;config_rom_attributes[4].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0xfedcba\n");</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for vendor is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_text_leaf(node_dev, &amp;config_rom_attributes[5].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for model is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_text_leaf(node_dev, &amp;config_rom_attributes[6].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "ABCDEFGHIJ\n");</div><div class='add'>+</div><div class='add'>+	// For entries in unit 0 directory.</div><div class='add'>+</div><div class='add'>+	// Vendor immediate entry is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[0].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Model immediate entry is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[4].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for vendor is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_text_leaf(unit0_dev, &amp;config_rom_attributes[5].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Descriptor leaf entry for model is not found.</div><div class='add'>+	KUNIT_EXPECT_LT(test, show_text_leaf(unit0_dev, &amp;config_rom_attributes[6].attr, buf), 0);</div><div class='add'>+</div><div class='add'>+	// Specifier_ID immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[2].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0xabcdef\n");</div><div class='add'>+</div><div class='add'>+	// Version immediate entry is found.</div><div class='add'>+	KUNIT_EXPECT_GT(test, show_immediate(unit0_dev, &amp;config_rom_attributes[3].attr, buf), 0);</div><div class='add'>+	KUNIT_EXPECT_STREQ(test, buf, "0x543210\n");</div><div class='add'>+</div><div class='add'>+	kunit_kfree(test, buf);</div><div class='add'>+</div><div class='add'>+	get_modalias_ids(&amp;unit0, ids);</div><div class='add'>+	KUNIT_EXPECT_MEMEQ(test, ids, unit0_expected_ids, sizeof(ids));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kunit_case device_attr_test_cases[] = {</div><div class='add'>+	KUNIT_CASE(device_attr_simple_avc),</div><div class='add'>+	KUNIT_CASE(device_attr_legacy_avc),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite device_attr_test_suite = {</div><div class='add'>+	.name = "firewire-device-attribute",</div><div class='add'>+	.test_cases = device_attr_test_cases,</div><div class='add'>+};</div><div class='add'>+kunit_test_suite(device_attr_test_suite);</div><div class='head'>diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c<br/>index 7e88fd489741..9db9290c3269 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firewire/ohci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firewire/ohci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/ohci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/ohci.c</a></div><div class='hunk'>@@ -279,6 +279,51 @@ static char ohci_driver_name[] = KBUILD_MODNAME;</div><div class='ctx'> #define QUIRK_TI_SLLZ059		0x20</div><div class='ctx'> #define QUIRK_IR_WAKE			0x40</div><div class='ctx'> </div><div class='add'>+// On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia</div><div class='add'>+// ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register</div><div class='add'>+// (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not</div><div class='add'>+// clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register,</div><div class='add'>+// while it is probable due to detection of any type of PCIe error.</div><div class='add'>+#define QUIRK_REBOOT_BY_CYCLE_TIMER_READ	0x80000000</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_X86)</div><div class='add'>+</div><div class='add'>+static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci)</div><div class='add'>+{</div><div class='add'>+	return !!(ohci-&gt;quirks &amp; QUIRK_REBOOT_BY_CYCLE_TIMER_READ);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define PCI_DEVICE_ID_ASMEDIA_ASM108X	0x1080</div><div class='add'>+</div><div class='add'>+static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	const struct pci_dev *pcie_to_pci_bridge;</div><div class='add'>+</div><div class='add'>+	// Detect any type of AMD Ryzen machine.</div><div class='add'>+	if (!static_cpu_has(X86_FEATURE_ZEN))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	// Detect VIA VT6306/6307/6308.</div><div class='add'>+	if (pdev-&gt;vendor != PCI_VENDOR_ID_VIA)</div><div class='add'>+		return false;</div><div class='add'>+	if (pdev-&gt;device != PCI_DEVICE_ID_VIA_VT630X)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	// Detect Asmedia ASM1083/1085.</div><div class='add'>+	pcie_to_pci_bridge = pdev-&gt;bus-&gt;self;</div><div class='add'>+	if (pcie_to_pci_bridge-&gt;vendor != PCI_VENDOR_ID_ASMEDIA)</div><div class='add'>+		return false;</div><div class='add'>+	if (pcie_to_pci_bridge-&gt;device != PCI_DEVICE_ID_ASMEDIA_ASM108X)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#else</div><div class='add'>+#define has_reboot_by_cycle_timer_read_quirk(ohci) false</div><div class='add'>+#define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev)	false</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /* In case of multiple matches in ohci_quirks[], only the first one is used. */</div><div class='ctx'> static const struct {</div><div class='ctx'> 	unsigned short vendor, device, revision, flags;</div><div class='hunk'>@@ -1724,6 +1769,9 @@ static u32 get_cycle_time(struct fw_ohci *ohci)</div><div class='ctx'> 	s32 diff01, diff12;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (has_reboot_by_cycle_timer_read_quirk(ohci))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);</div><div class='ctx'> </div><div class='ctx'> 	if (ohci-&gt;quirks &amp; QUIRK_CYCLE_TIMER) {</div><div class='hunk'>@@ -3630,6 +3678,9 @@ static int pci_probe(struct pci_dev *dev,</div><div class='ctx'> 	if (param_quirks)</div><div class='ctx'> 		ohci-&gt;quirks = param_quirks;</div><div class='ctx'> </div><div class='add'>+	if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev))</div><div class='add'>+		ohci-&gt;quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Because dma_alloc_coherent() allocates at least one page,</div><div class='ctx'> 	 * we save space by using a common buffer for the AR request/</div><div class='head'>diff --git a/drivers/firewire/sbp2.c b/drivers/firewire/sbp2.c<br/>index 7edf2c95282f..e779d866022b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firewire/sbp2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firewire/sbp2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firewire/sbp2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firewire/sbp2.c</a></div><div class='hunk'>@@ -1519,9 +1519,9 @@ static int sbp2_scsi_slave_configure(struct scsi_device *sdev)</div><div class='ctx'> 	sdev-&gt;use_10_for_rw = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (sbp2_param_exclusive_login) {</div><div class='del'>-		sdev-&gt;manage_system_start_stop = true;</div><div class='del'>-		sdev-&gt;manage_runtime_start_stop = true;</div><div class='del'>-		sdev-&gt;manage_shutdown = true;</div><div class='add'>+		sdev-&gt;manage_system_start_stop = 1;</div><div class='add'>+		sdev-&gt;manage_runtime_start_stop = 1;</div><div class='add'>+		sdev-&gt;manage_shutdown = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (sdev-&gt;type == TYPE_ROM)</div><div class='head'>diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig<br/>index 4a98a859d44d..afd38539b92e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/Kconfig</a></div><div class='hunk'>@@ -28,15 +28,6 @@ config ARM_SCPI_PROTOCOL</div><div class='ctx'> 	  This protocol library provides interface for all the client drivers</div><div class='ctx'> 	  making use of the features offered by the SCP.</div><div class='ctx'> </div><div class='del'>-config ARM_SCPI_POWER_DOMAIN</div><div class='del'>-	tristate "SCPI power domain driver"</div><div class='del'>-	depends on ARM_SCPI_PROTOCOL || (COMPILE_TEST &amp;&amp; OF)</div><div class='del'>-	default y</div><div class='del'>-	select PM_GENERIC_DOMAINS if PM</div><div class='del'>-	help</div><div class='del'>-	  This enables support for the SCPI power domains which can be</div><div class='del'>-	  enabled or disabled via the SCP firmware</div><div class='del'>-</div><div class='ctx'> config ARM_SDE_INTERFACE</div><div class='ctx'> 	bool "ARM Software Delegated Exception Interface (SDEI)"</div><div class='ctx'> 	depends on ARM64</div><div class='hunk'>@@ -272,6 +263,7 @@ source "drivers/firmware/google/Kconfig"</div><div class='ctx'> source "drivers/firmware/efi/Kconfig"</div><div class='ctx'> source "drivers/firmware/imx/Kconfig"</div><div class='ctx'> source "drivers/firmware/meson/Kconfig"</div><div class='add'>+source "drivers/firmware/microchip/Kconfig"</div><div class='ctx'> source "drivers/firmware/psci/Kconfig"</div><div class='ctx'> source "drivers/firmware/qcom/Kconfig"</div><div class='ctx'> source "drivers/firmware/smccc/Kconfig"</div><div class='head'>diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile<br/>index 5f9dab82e1a0..7a8d486e718f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/Makefile</a></div><div class='hunk'>@@ -3,7 +3,6 @@</div><div class='ctx'> # Makefile for the linux kernel.</div><div class='ctx'> #</div><div class='ctx'> obj-$(CONFIG_ARM_SCPI_PROTOCOL)	+= arm_scpi.o</div><div class='del'>-obj-$(CONFIG_ARM_SCPI_POWER_DOMAIN) += scpi_pm_domain.o</div><div class='ctx'> obj-$(CONFIG_ARM_SDE_INTERFACE)	+= arm_sdei.o</div><div class='ctx'> obj-$(CONFIG_DMI)		+= dmi_scan.o</div><div class='ctx'> obj-$(CONFIG_DMI_SYSFS)		+= dmi-sysfs.o</div><div class='hunk'>@@ -28,6 +27,7 @@ obj-y				+= arm_scmi/</div><div class='ctx'> obj-y				+= broadcom/</div><div class='ctx'> obj-y				+= cirrus/</div><div class='ctx'> obj-y				+= meson/</div><div class='add'>+obj-y				+= microchip/</div><div class='ctx'> obj-$(CONFIG_GOOGLE_FIRMWARE)	+= google/</div><div class='ctx'> obj-y				+= efi/</div><div class='ctx'> obj-y				+= imx/</div><div class='head'>diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c<br/>index 07b72c679247..6146b2927d5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_ffa/driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_ffa/driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_ffa/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_ffa/driver.c</a></div><div class='hunk'>@@ -99,6 +99,7 @@ struct ffa_drv_info {</div><div class='ctx'> 	void *tx_buffer;</div><div class='ctx'> 	bool mem_ops_native;</div><div class='ctx'> 	bool bitmap_created;</div><div class='add'>+	bool notif_enabled;</div><div class='ctx'> 	unsigned int sched_recv_irq;</div><div class='ctx'> 	unsigned int cpuhp_state;</div><div class='ctx'> 	struct ffa_pcpu_irq __percpu *irq_pcpu;</div><div class='hunk'>@@ -782,7 +783,7 @@ static void ffa_notification_info_get(void)</div><div class='ctx'> 			if (ids_processed &gt;= max_ids - 1)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='del'>-			part_id = packed_id_list[++ids_processed];</div><div class='add'>+			part_id = packed_id_list[ids_processed++];</div><div class='ctx'> </div><div class='ctx'> 			if (!ids_count[list]) { /* Global Notification */</div><div class='ctx'> 				__do_sched_recv_cb(part_id, 0, false);</div><div class='hunk'>@@ -794,7 +795,7 @@ static void ffa_notification_info_get(void)</div><div class='ctx'> 				if (ids_processed &gt;= max_ids - 1)</div><div class='ctx'> 					break;</div><div class='ctx'> </div><div class='del'>-				vcpu_id = packed_id_list[++ids_processed];</div><div class='add'>+				vcpu_id = packed_id_list[ids_processed++];</div><div class='ctx'> </div><div class='ctx'> 				__do_sched_recv_cb(part_id, vcpu_id, true);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -889,6 +890,8 @@ static int ffa_memory_lend(struct ffa_mem_ops_args *args)</div><div class='ctx'> </div><div class='ctx'> #define FFA_SECURE_PARTITION_ID_FLAG	BIT(15)</div><div class='ctx'> </div><div class='add'>+#define ffa_notifications_disabled()	(!drv_info-&gt;notif_enabled)</div><div class='add'>+</div><div class='ctx'> enum notify_type {</div><div class='ctx'> 	NON_SECURE_VM,</div><div class='ctx'> 	SECURE_PARTITION,</div><div class='hunk'>@@ -908,6 +911,9 @@ static int ffa_sched_recv_cb_update(u16 part_id, ffa_sched_recv_cb callback,</div><div class='ctx'> 	struct ffa_dev_part_info *partition;</div><div class='ctx'> 	bool cb_valid;</div><div class='ctx'> </div><div class='add'>+	if (ffa_notifications_disabled())</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	partition = xa_load(&amp;drv_info-&gt;partition_info, part_id);</div><div class='ctx'> 	write_lock(&amp;partition-&gt;rw_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -1001,6 +1007,9 @@ static int ffa_notify_relinquish(struct ffa_device *dev, int notify_id)</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	enum notify_type type = ffa_notify_type_get(dev-&gt;vm_id);</div><div class='ctx'> </div><div class='add'>+	if (ffa_notifications_disabled())</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (notify_id &gt;= FFA_MAX_NOTIFICATIONS)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1027,6 +1036,9 @@ static int ffa_notify_request(struct ffa_device *dev, bool is_per_vcpu,</div><div class='ctx'> 	u32 flags = 0;</div><div class='ctx'> 	enum notify_type type = ffa_notify_type_get(dev-&gt;vm_id);</div><div class='ctx'> </div><div class='add'>+	if (ffa_notifications_disabled())</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (notify_id &gt;= FFA_MAX_NOTIFICATIONS)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1057,6 +1069,9 @@ static int ffa_notify_send(struct ffa_device *dev, int notify_id,</div><div class='ctx'> {</div><div class='ctx'> 	u32 flags = 0;</div><div class='ctx'> </div><div class='add'>+	if (ffa_notifications_disabled())</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (is_per_vcpu)</div><div class='ctx'> 		flags |= (PER_VCPU_NOTIFICATION_FLAG | vcpu &lt;&lt; 16);</div><div class='ctx'> </div><div class='hunk'>@@ -1233,7 +1248,7 @@ static void ffa_partitions_cleanup(void)</div><div class='ctx'> 	if (!count)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	info = kcalloc(count, sizeof(**info), GFP_KERNEL);</div><div class='add'>+	info = kcalloc(count, sizeof(*info), GFP_KERNEL);</div><div class='ctx'> 	if (!info)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -1311,8 +1326,10 @@ static int ffa_sched_recv_irq_map(void)</div><div class='ctx'> </div><div class='ctx'> static void ffa_sched_recv_irq_unmap(void)</div><div class='ctx'> {</div><div class='del'>-	if (drv_info-&gt;sched_recv_irq)</div><div class='add'>+	if (drv_info-&gt;sched_recv_irq) {</div><div class='ctx'> 		irq_dispose_mapping(drv_info-&gt;sched_recv_irq);</div><div class='add'>+		drv_info-&gt;sched_recv_irq = 0;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ffa_cpuhp_pcpu_irq_enable(unsigned int cpu)</div><div class='hunk'>@@ -1329,17 +1346,23 @@ static int ffa_cpuhp_pcpu_irq_disable(unsigned int cpu)</div><div class='ctx'> </div><div class='ctx'> static void ffa_uninit_pcpu_irq(void)</div><div class='ctx'> {</div><div class='del'>-	if (drv_info-&gt;cpuhp_state)</div><div class='add'>+	if (drv_info-&gt;cpuhp_state) {</div><div class='ctx'> 		cpuhp_remove_state(drv_info-&gt;cpuhp_state);</div><div class='add'>+		drv_info-&gt;cpuhp_state = 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (drv_info-&gt;notif_pcpu_wq)</div><div class='add'>+	if (drv_info-&gt;notif_pcpu_wq) {</div><div class='ctx'> 		destroy_workqueue(drv_info-&gt;notif_pcpu_wq);</div><div class='add'>+		drv_info-&gt;notif_pcpu_wq = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (drv_info-&gt;sched_recv_irq)</div><div class='ctx'> 		free_percpu_irq(drv_info-&gt;sched_recv_irq, drv_info-&gt;irq_pcpu);</div><div class='ctx'> </div><div class='del'>-	if (drv_info-&gt;irq_pcpu)</div><div class='add'>+	if (drv_info-&gt;irq_pcpu) {</div><div class='ctx'> 		free_percpu(drv_info-&gt;irq_pcpu);</div><div class='add'>+		drv_info-&gt;irq_pcpu = NULL;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ffa_init_pcpu_irq(unsigned int irq)</div><div class='hunk'>@@ -1388,22 +1411,23 @@ static void ffa_notifications_cleanup(void)</div><div class='ctx'> 		ffa_notification_bitmap_destroy();</div><div class='ctx'> 		drv_info-&gt;bitmap_created = false;</div><div class='ctx'> 	}</div><div class='add'>+	drv_info-&gt;notif_enabled = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ffa_notifications_setup(void)</div><div class='add'>+static void ffa_notifications_setup(void)</div><div class='ctx'> {</div><div class='ctx'> 	int ret, irq;</div><div class='ctx'> </div><div class='ctx'> 	ret = ffa_features(FFA_NOTIFICATION_BITMAP_CREATE, 0, NULL, NULL);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pr_err("Notifications not supported, continuing with it ..\n");</div><div class='del'>-		return 0;</div><div class='add'>+		pr_info("Notifications not supported, continuing with it ..\n");</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = ffa_notification_bitmap_create();</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pr_err("notification_bitmap_create error %d\n", ret);</div><div class='del'>-		return ret;</div><div class='add'>+		pr_info("Notification bitmap create error %d\n", ret);</div><div class='add'>+		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	drv_info-&gt;bitmap_created = true;</div><div class='ctx'> </div><div class='hunk'>@@ -1422,14 +1446,11 @@ static int ffa_notifications_setup(void)</div><div class='ctx'> 	hash_init(drv_info-&gt;notifier_hash);</div><div class='ctx'> 	mutex_init(&amp;drv_info-&gt;notify_lock);</div><div class='ctx'> </div><div class='del'>-	/* Register internal scheduling callback */</div><div class='del'>-	ret = ffa_sched_recv_cb_update(drv_info-&gt;vm_id, ffa_self_notif_handle,</div><div class='del'>-				       drv_info, true);</div><div class='del'>-	if (!ret)</div><div class='del'>-		return ret;</div><div class='add'>+	drv_info-&gt;notif_enabled = true;</div><div class='add'>+	return;</div><div class='ctx'> cleanup:</div><div class='add'>+	pr_info("Notification setup failed %d, not enabled\n", ret);</div><div class='ctx'> 	ffa_notifications_cleanup();</div><div class='del'>-	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __init ffa_init(void)</div><div class='hunk'>@@ -1483,17 +1504,18 @@ static int __init ffa_init(void)</div><div class='ctx'> 	mutex_init(&amp;drv_info-&gt;rx_lock);</div><div class='ctx'> 	mutex_init(&amp;drv_info-&gt;tx_lock);</div><div class='ctx'> </div><div class='del'>-	ffa_setup_partitions();</div><div class='del'>-</div><div class='ctx'> 	ffa_set_up_mem_ops_native_flag();</div><div class='ctx'> </div><div class='del'>-	ret = ffa_notifications_setup();</div><div class='add'>+	ffa_notifications_setup();</div><div class='add'>+</div><div class='add'>+	ffa_setup_partitions();</div><div class='add'>+</div><div class='add'>+	ret = ffa_sched_recv_cb_update(drv_info-&gt;vm_id, ffa_self_notif_handle,</div><div class='add'>+				       drv_info, true);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto partitions_cleanup;</div><div class='add'>+		pr_info("Failed to register driver sched callback %d\n", ret);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-partitions_cleanup:</div><div class='del'>-	ffa_partitions_cleanup();</div><div class='ctx'> free_pages:</div><div class='ctx'> 	if (drv_info-&gt;tx_buffer)</div><div class='ctx'> 		free_pages_exact(drv_info-&gt;tx_buffer, RXTX_BUFFER_SIZE);</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig<br/>index 706d1264d038..aa5842be19b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/Kconfig</a></div><div class='hunk'>@@ -168,31 +168,6 @@ config ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE</div><div class='ctx'> </div><div class='ctx'> endif #ARM_SCMI_PROTOCOL</div><div class='ctx'> </div><div class='del'>-config ARM_SCMI_POWER_DOMAIN</div><div class='del'>-	tristate "SCMI power domain driver"</div><div class='del'>-	depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST &amp;&amp; OF)</div><div class='del'>-	default y</div><div class='del'>-	select PM_GENERIC_DOMAINS if PM</div><div class='del'>-	help</div><div class='del'>-	  This enables support for the SCMI power domains which can be</div><div class='del'>-	  enabled or disabled via the SCP firmware</div><div class='del'>-</div><div class='del'>-	  This driver can also be built as a module.  If so, the module</div><div class='del'>-	  will be called scmi_pm_domain. Note this may needed early in boot</div><div class='del'>-	  before rootfs may be available.</div><div class='del'>-</div><div class='del'>-config ARM_SCMI_PERF_DOMAIN</div><div class='del'>-	tristate "SCMI performance domain driver"</div><div class='del'>-	depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST &amp;&amp; OF)</div><div class='del'>-	default y</div><div class='del'>-	select PM_GENERIC_DOMAINS if PM</div><div class='del'>-	help</div><div class='del'>-	  This enables support for the SCMI performance domains which can be</div><div class='del'>-	  enabled or disabled via the SCP firmware.</div><div class='del'>-</div><div class='del'>-	  This driver can also be built as a module. If so, the module will be</div><div class='del'>-	  called scmi_perf_domain.</div><div class='del'>-</div><div class='ctx'> config ARM_SCMI_POWER_CONTROL</div><div class='ctx'> 	tristate "SCMI system power control driver"</div><div class='ctx'> 	depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST &amp;&amp; OF)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c<br/>index a52f084a6a87..97254de35ab0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/base.c</a></div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #include "common.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x20000</div><div class='add'>+</div><div class='ctx'> #define SCMI_BASE_NUM_SOURCES		1</div><div class='ctx'> #define SCMI_BASE_MAX_CMD_ERR_COUNT	1024</div><div class='ctx'> </div><div class='hunk'>@@ -385,7 +388,7 @@ static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> </div><div class='ctx'> 	rev-&gt;major_ver = PROTOCOL_REV_MAJOR(version),</div><div class='ctx'> 	rev-&gt;minor_ver = PROTOCOL_REV_MINOR(version);</div><div class='del'>-	ph-&gt;set_priv(ph, rev);</div><div class='add'>+	ph-&gt;set_priv(ph, rev, version);</div><div class='ctx'> </div><div class='ctx'> 	ret = scmi_base_attributes_get(ph);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -423,6 +426,7 @@ static const struct scmi_protocol scmi_base = {</div><div class='ctx'> 	.instance_init = &amp;scmi_base_protocol_init,</div><div class='ctx'> 	.ops = NULL,</div><div class='ctx'> 	.events = &amp;base_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(base, scmi_base)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c<br/>index 42b81c181d68..c0644558042a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/clock.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/clock.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/clock.c</a></div><div class='hunk'>@@ -12,6 +12,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x20001</div><div class='add'>+</div><div class='ctx'> enum scmi_clock_protocol_cmd {</div><div class='ctx'> 	CLOCK_ATTRIBUTES = 0x3,</div><div class='ctx'> 	CLOCK_DESCRIBE_RATES = 0x4,</div><div class='hunk'>@@ -318,7 +321,7 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (!ret &amp;&amp; PROTOCOL_REV_MAJOR(version) &gt;= 0x2) {</div><div class='ctx'> 		if (SUPPORTS_EXTENDED_NAMES(attributes))</div><div class='ctx'> 			ph-&gt;hops-&gt;extended_name_get(ph, CLOCK_NAME_GET, clk_id,</div><div class='del'>-						    clk-&gt;name,</div><div class='add'>+						    NULL, clk-&gt;name,</div><div class='ctx'> 						    SCMI_MAX_STR_SIZE);</div><div class='ctx'> </div><div class='ctx'> 		if (SUPPORTS_RATE_CHANGED_NOTIF(attributes))</div><div class='hunk'>@@ -961,7 +964,7 @@ static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cinfo-&gt;version = version;</div><div class='del'>-	return ph-&gt;set_priv(ph, cinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, cinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_clock = {</div><div class='hunk'>@@ -970,6 +973,7 @@ static const struct scmi_protocol scmi_clock = {</div><div class='ctx'> 	.instance_init = &amp;scmi_clock_protocol_init,</div><div class='ctx'> 	.ops = &amp;clk_proto_ops,</div><div class='ctx'> 	.events = &amp;clk_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(clock, scmi_clock)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c<br/>index 09371f40d61f..3ea64b22cf0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/driver.c</a></div><div class='hunk'>@@ -85,6 +85,7 @@ struct scmi_xfers_info {</div><div class='ctx'>  * @gid: A reference for per-protocol devres management.</div><div class='ctx'>  * @users: A refcount to track effective users of this protocol.</div><div class='ctx'>  * @priv: Reference for optional protocol private data.</div><div class='add'>+ * @version: Protocol version supported by the platform as detected at runtime.</div><div class='ctx'>  * @ph: An embedded protocol handle that will be passed down to protocol</div><div class='ctx'>  *	initialization code to identify this instance.</div><div class='ctx'>  *</div><div class='hunk'>@@ -97,6 +98,7 @@ struct scmi_protocol_instance {</div><div class='ctx'> 	void				*gid;</div><div class='ctx'> 	refcount_t			users;</div><div class='ctx'> 	void				*priv;</div><div class='add'>+	unsigned int			version;</div><div class='ctx'> 	struct scmi_protocol_handle	ph;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1392,15 +1394,17 @@ static int version_get(const struct scmi_protocol_handle *ph, u32 *version)</div><div class='ctx'>  *</div><div class='ctx'>  * @ph: A reference to the protocol handle.</div><div class='ctx'>  * @priv: The private data to set.</div><div class='add'>+ * @version: The detected protocol version for the core to register.</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 on Success</div><div class='ctx'>  */</div><div class='ctx'> static int scmi_set_protocol_priv(const struct scmi_protocol_handle *ph,</div><div class='del'>-				  void *priv)</div><div class='add'>+				  void *priv, u32 version)</div><div class='ctx'> {</div><div class='ctx'> 	struct scmi_protocol_instance *pi = ph_to_pi(ph);</div><div class='ctx'> </div><div class='ctx'> 	pi-&gt;priv = priv;</div><div class='add'>+	pi-&gt;version = version;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1438,6 +1442,7 @@ struct scmi_msg_resp_domain_name_get {</div><div class='ctx'>  * @ph: A protocol handle reference.</div><div class='ctx'>  * @cmd_id: The specific command ID to use.</div><div class='ctx'>  * @res_id: The specific resource ID to use.</div><div class='add'>+ * @flags: A pointer to specific flags to use, if any.</div><div class='ctx'>  * @name: A pointer to the preallocated area where the retrieved name will be</div><div class='ctx'>  *	  stored as a NULL terminated string.</div><div class='ctx'>  * @len: The len in bytes of the @name char array.</div><div class='hunk'>@@ -1445,19 +1450,22 @@ struct scmi_msg_resp_domain_name_get {</div><div class='ctx'>  * Return: 0 on Succcess</div><div class='ctx'>  */</div><div class='ctx'> static int scmi_common_extended_name_get(const struct scmi_protocol_handle *ph,</div><div class='del'>-					 u8 cmd_id, u32 res_id, char *name,</div><div class='del'>-					 size_t len)</div><div class='add'>+					 u8 cmd_id, u32 res_id, u32 *flags,</div><div class='add'>+					 char *name, size_t len)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='add'>+	size_t txlen;</div><div class='ctx'> 	struct scmi_xfer *t;</div><div class='ctx'> 	struct scmi_msg_resp_domain_name_get *resp;</div><div class='ctx'> </div><div class='del'>-	ret = ph-&gt;xops-&gt;xfer_get_init(ph, cmd_id, sizeof(res_id),</div><div class='del'>-				      sizeof(*resp), &amp;t);</div><div class='add'>+	txlen = !flags ? sizeof(res_id) : sizeof(res_id) + sizeof(*flags);</div><div class='add'>+	ret = ph-&gt;xops-&gt;xfer_get_init(ph, cmd_id, txlen, sizeof(*resp), &amp;t);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	put_unaligned_le32(res_id, t-&gt;tx.buf);</div><div class='add'>+	if (flags)</div><div class='add'>+		put_unaligned_le32(*flags, t-&gt;tx.buf + sizeof(res_id));</div><div class='ctx'> 	resp = t-&gt;rx.buf;</div><div class='ctx'> </div><div class='ctx'> 	ret = ph-&gt;xops-&gt;do_xfer(ph, t);</div><div class='hunk'>@@ -1845,6 +1853,12 @@ scmi_alloc_init_protocol_instance(struct scmi_info *info,</div><div class='ctx'> 	devres_close_group(handle-&gt;dev, pi-&gt;gid);</div><div class='ctx'> 	dev_dbg(handle-&gt;dev, "Initialized protocol: 0x%X\n", pi-&gt;proto-&gt;id);</div><div class='ctx'> </div><div class='add'>+	if (pi-&gt;version &gt; proto-&gt;supported_version)</div><div class='add'>+		dev_warn(handle-&gt;dev,</div><div class='add'>+			 "Detected UNSUPPORTED higher version 0x%X for protocol 0x%X."</div><div class='add'>+			 "Backward compatibility is NOT assured.\n",</div><div class='add'>+			 pi-&gt;version, pi-&gt;proto-&gt;id);</div><div class='add'>+</div><div class='ctx'> 	return pi;</div><div class='ctx'> </div><div class='ctx'> clean:</div><div class='hunk'>@@ -2820,7 +2834,7 @@ clear_ida:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int scmi_remove(struct platform_device *pdev)</div><div class='add'>+static void scmi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int id;</div><div class='ctx'> 	struct scmi_info *info = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -2854,8 +2868,6 @@ static int scmi_remove(struct platform_device *pdev)</div><div class='ctx'> 	scmi_cleanup_txrx_channels(info);</div><div class='ctx'> </div><div class='ctx'> 	ida_free(&amp;scmi_id, info-&gt;id);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t protocol_version_show(struct device *dev,</div><div class='hunk'>@@ -2933,7 +2945,7 @@ static struct platform_driver scmi_driver = {</div><div class='ctx'> 		   .dev_groups = versions_groups,</div><div class='ctx'> 		   },</div><div class='ctx'> 	.probe = scmi_probe,</div><div class='del'>-	.remove = scmi_remove,</div><div class='add'>+	.remove_new = scmi_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/optee.c b/drivers/firmware/arm_scmi/optee.c<br/>index e123de6e8c67..25bfb465484d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/optee.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/optee.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/optee.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/optee.c</a></div><div class='hunk'>@@ -440,6 +440,10 @@ static int scmi_optee_chan_setup(struct scmi_chan_info *cinfo, struct device *de</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_free_shm;</div><div class='ctx'> </div><div class='add'>+	ret = tee_client_system_session(scmi_optee_private-&gt;tee_ctx, channel-&gt;tee_session);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_warn(dev, "Could not switch to system session, do best effort\n");</div><div class='add'>+</div><div class='ctx'> 	ret = get_channel(channel);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_close_sess;</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c<br/>index c2435be0ae1b..8ea2a7b3d35d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/perf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/perf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/perf.c</a></div><div class='hunk'>@@ -24,7 +24,10 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='del'>-#define MAX_OPPS		16</div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x40000</div><div class='add'>+</div><div class='add'>+#define MAX_OPPS		32</div><div class='ctx'> </div><div class='ctx'> enum scmi_performance_protocol_cmd {</div><div class='ctx'> 	PERF_DOMAIN_ATTRIBUTES = 0x3,</div><div class='hunk'>@@ -152,7 +155,7 @@ struct perf_dom_info {</div><div class='ctx'> 	u32 opp_count;</div><div class='ctx'> 	u32 sustained_freq_khz;</div><div class='ctx'> 	u32 sustained_perf_level;</div><div class='del'>-	u32 mult_factor;</div><div class='add'>+	unsigned long mult_factor;</div><div class='ctx'> 	struct scmi_perf_domain_info info;</div><div class='ctx'> 	struct scmi_opp opp[MAX_OPPS];</div><div class='ctx'> 	struct scmi_fc_info *fc_info;</div><div class='hunk'>@@ -268,13 +271,14 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 		dom_info-&gt;sustained_perf_level =</div><div class='ctx'> 					le32_to_cpu(attr-&gt;sustained_perf_level);</div><div class='ctx'> 		if (!dom_info-&gt;sustained_freq_khz ||</div><div class='del'>-		    !dom_info-&gt;sustained_perf_level)</div><div class='add'>+		    !dom_info-&gt;sustained_perf_level ||</div><div class='add'>+		    dom_info-&gt;level_indexing_mode)</div><div class='ctx'> 			/* CPUFreq converts to kHz, hence default 1000 */</div><div class='ctx'> 			dom_info-&gt;mult_factor =	1000;</div><div class='ctx'> 		else</div><div class='ctx'> 			dom_info-&gt;mult_factor =</div><div class='del'>-					(dom_info-&gt;sustained_freq_khz * 1000) /</div><div class='del'>-					dom_info-&gt;sustained_perf_level;</div><div class='add'>+					(dom_info-&gt;sustained_freq_khz * 1000UL)</div><div class='add'>+					/ dom_info-&gt;sustained_perf_level;</div><div class='ctx'> 		strscpy(dom_info-&gt;info.name, attr-&gt;name,</div><div class='ctx'> 			SCMI_SHORT_NAME_MAX_SIZE);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -288,7 +292,7 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (!ret &amp;&amp; PROTOCOL_REV_MAJOR(version) &gt;= 0x3 &amp;&amp;</div><div class='ctx'> 	    SUPPORTS_EXTENDED_NAMES(flags))</div><div class='ctx'> 		ph-&gt;hops-&gt;extended_name_get(ph, PERF_DOMAIN_NAME_GET,</div><div class='del'>-					    dom_info-&gt;id, dom_info-&gt;info.name,</div><div class='add'>+					    dom_info-&gt;id, NULL, dom_info-&gt;info.name,</div><div class='ctx'> 					    SCMI_MAX_STR_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	if (dom_info-&gt;level_indexing_mode) {</div><div class='hunk'>@@ -504,6 +508,9 @@ static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (IS_ERR(dom))</div><div class='ctx'> 		return PTR_ERR(dom);</div><div class='ctx'> </div><div class='add'>+	if (!dom-&gt;set_limits)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (PROTOCOL_REV_MAJOR(pi-&gt;version) &gt;= 0x3 &amp;&amp; !max_perf &amp;&amp; !min_perf)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -654,6 +661,9 @@ static int scmi_perf_level_set(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (IS_ERR(dom))</div><div class='ctx'> 		return PTR_ERR(dom);</div><div class='ctx'> </div><div class='add'>+	if (!dom-&gt;info.set_perf)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (dom-&gt;level_indexing_mode) {</div><div class='ctx'> 		struct scmi_opp *opp;</div><div class='ctx'> </div><div class='hunk'>@@ -753,7 +763,7 @@ static int scmi_perf_level_limits_notify(const struct scmi_protocol_handle *ph,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void scmi_perf_domain_init_fc(const struct scmi_protocol_handle *ph,</div><div class='del'>-				     u32 domain, struct scmi_fc_info **p_fc)</div><div class='add'>+				     struct perf_dom_info *dom)</div><div class='ctx'> {</div><div class='ctx'> 	struct scmi_fc_info *fc;</div><div class='ctx'> </div><div class='hunk'>@@ -762,24 +772,26 @@ static void scmi_perf_domain_init_fc(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='del'>-				   PERF_LEVEL_SET, 4, domain,</div><div class='del'>-				   &amp;fc[PERF_FC_LEVEL].set_addr,</div><div class='del'>-				   &amp;fc[PERF_FC_LEVEL].set_db);</div><div class='del'>-</div><div class='del'>-	ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='del'>-				   PERF_LEVEL_GET, 4, domain,</div><div class='add'>+				   PERF_LEVEL_GET, 4, dom-&gt;id,</div><div class='ctx'> 				   &amp;fc[PERF_FC_LEVEL].get_addr, NULL);</div><div class='ctx'> </div><div class='ctx'> 	ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='del'>-				   PERF_LIMITS_SET, 8, domain,</div><div class='del'>-				   &amp;fc[PERF_FC_LIMIT].set_addr,</div><div class='del'>-				   &amp;fc[PERF_FC_LIMIT].set_db);</div><div class='del'>-</div><div class='del'>-	ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='del'>-				   PERF_LIMITS_GET, 8, domain,</div><div class='add'>+				   PERF_LIMITS_GET, 8, dom-&gt;id,</div><div class='ctx'> 				   &amp;fc[PERF_FC_LIMIT].get_addr, NULL);</div><div class='ctx'> </div><div class='del'>-	*p_fc = fc;</div><div class='add'>+	if (dom-&gt;info.set_perf)</div><div class='add'>+		ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='add'>+					   PERF_LEVEL_SET, 4, dom-&gt;id,</div><div class='add'>+					   &amp;fc[PERF_FC_LEVEL].set_addr,</div><div class='add'>+					   &amp;fc[PERF_FC_LEVEL].set_db);</div><div class='add'>+</div><div class='add'>+	if (dom-&gt;set_limits)</div><div class='add'>+		ph-&gt;hops-&gt;fastchannel_init(ph, PERF_DESCRIBE_FASTCHANNEL,</div><div class='add'>+					   PERF_LIMITS_SET, 8, dom-&gt;id,</div><div class='add'>+					   &amp;fc[PERF_FC_LIMIT].set_addr,</div><div class='add'>+					   &amp;fc[PERF_FC_LIMIT].set_db);</div><div class='add'>+</div><div class='add'>+	dom-&gt;fc_info = fc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph,</div><div class='hunk'>@@ -798,7 +810,7 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 		if (!dom-&gt;level_indexing_mode)</div><div class='ctx'> 			freq = dom-&gt;opp[idx].perf * dom-&gt;mult_factor;</div><div class='ctx'> 		else</div><div class='del'>-			freq = dom-&gt;opp[idx].indicative_freq * 1000;</div><div class='add'>+			freq = dom-&gt;opp[idx].indicative_freq * dom-&gt;mult_factor;</div><div class='ctx'> </div><div class='ctx'> 		data.level = dom-&gt;opp[idx].perf;</div><div class='ctx'> 		data.freq = freq;</div><div class='hunk'>@@ -845,7 +857,8 @@ static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		struct scmi_opp *opp;</div><div class='ctx'> </div><div class='del'>-		opp = LOOKUP_BY_FREQ(dom-&gt;opps_by_freq, freq / 1000);</div><div class='add'>+		opp = LOOKUP_BY_FREQ(dom-&gt;opps_by_freq,</div><div class='add'>+				     freq / dom-&gt;mult_factor);</div><div class='ctx'> 		if (!opp)</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> </div><div class='hunk'>@@ -879,7 +892,7 @@ static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain,</div><div class='ctx'> 		if (!opp)</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> </div><div class='del'>-		*freq = opp-&gt;indicative_freq * 1000;</div><div class='add'>+		*freq = opp-&gt;indicative_freq * dom-&gt;mult_factor;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -902,7 +915,7 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 		if (!dom-&gt;level_indexing_mode)</div><div class='ctx'> 			opp_freq = opp-&gt;perf * dom-&gt;mult_factor;</div><div class='ctx'> 		else</div><div class='del'>-			opp_freq = opp-&gt;indicative_freq * 1000;</div><div class='add'>+			opp_freq = opp-&gt;indicative_freq * dom-&gt;mult_factor;</div><div class='ctx'> </div><div class='ctx'> 		if (opp_freq &lt; *freq)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -1089,14 +1102,14 @@ static int scmi_perf_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 		scmi_perf_describe_levels_get(ph, dom, version);</div><div class='ctx'> </div><div class='ctx'> 		if (dom-&gt;perf_fastchannels)</div><div class='del'>-			scmi_perf_domain_init_fc(ph, dom-&gt;id, &amp;dom-&gt;fc_info);</div><div class='add'>+			scmi_perf_domain_init_fc(ph, dom);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = devm_add_action_or_reset(ph-&gt;dev, scmi_perf_xa_destroy, pinfo);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	return ph-&gt;set_priv(ph, pinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, pinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_perf = {</div><div class='hunk'>@@ -1105,6 +1118,7 @@ static const struct scmi_protocol scmi_perf = {</div><div class='ctx'> 	.instance_init = &amp;scmi_perf_protocol_init,</div><div class='ctx'> 	.ops = &amp;perf_proto_ops,</div><div class='ctx'> 	.events = &amp;perf_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(perf, scmi_perf)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/power.c<br/>index 356e83631664..c2e6b9b4d941 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/power.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/power.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/power.c</a></div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x30000</div><div class='add'>+</div><div class='ctx'> enum scmi_power_protocol_cmd {</div><div class='ctx'> 	POWER_DOMAIN_ATTRIBUTES = 0x3,</div><div class='ctx'> 	POWER_STATE_SET = 0x4,</div><div class='hunk'>@@ -133,7 +136,7 @@ scmi_power_domain_attributes_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (!ret &amp;&amp; PROTOCOL_REV_MAJOR(version) &gt;= 0x3 &amp;&amp;</div><div class='ctx'> 	    SUPPORTS_EXTENDED_NAMES(flags)) {</div><div class='ctx'> 		ph-&gt;hops-&gt;extended_name_get(ph, POWER_DOMAIN_NAME_GET,</div><div class='del'>-					    domain, dom_info-&gt;name,</div><div class='add'>+					    domain, NULL, dom_info-&gt;name,</div><div class='ctx'> 					    SCMI_MAX_STR_SIZE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -328,7 +331,7 @@ static int scmi_power_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> </div><div class='ctx'> 	pinfo-&gt;version = version;</div><div class='ctx'> </div><div class='del'>-	return ph-&gt;set_priv(ph, pinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, pinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_power = {</div><div class='hunk'>@@ -337,6 +340,7 @@ static const struct scmi_protocol scmi_power = {</div><div class='ctx'> 	.instance_init = &amp;scmi_power_protocol_init,</div><div class='ctx'> 	.ops = &amp;power_proto_ops,</div><div class='ctx'> 	.events = &amp;power_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(power, scmi_power)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/powercap.c b/drivers/firmware/arm_scmi/powercap.c<br/>index cb5617443a14..a4c6cd4716fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/powercap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/powercap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/powercap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/powercap.c</a></div><div class='hunk'>@@ -17,6 +17,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x20000</div><div class='add'>+</div><div class='ctx'> enum scmi_powercap_protocol_cmd {</div><div class='ctx'> 	POWERCAP_DOMAIN_ATTRIBUTES = 0x3,</div><div class='ctx'> 	POWERCAP_CAP_GET = 0x4,</div><div class='hunk'>@@ -270,7 +273,7 @@ clean:</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!ret &amp;&amp; SUPPORTS_EXTENDED_NAMES(flags))</div><div class='ctx'> 		ph-&gt;hops-&gt;extended_name_get(ph, POWERCAP_DOMAIN_NAME_GET,</div><div class='del'>-					    domain, dom_info-&gt;name,</div><div class='add'>+					    domain, NULL, dom_info-&gt;name,</div><div class='ctx'> 					    SCMI_MAX_STR_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -975,7 +978,7 @@ scmi_powercap_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pinfo-&gt;version = version;</div><div class='del'>-	return ph-&gt;set_priv(ph, pinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, pinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_powercap = {</div><div class='hunk'>@@ -984,6 +987,7 @@ static const struct scmi_protocol scmi_powercap = {</div><div class='ctx'> 	.instance_init = &amp;scmi_powercap_protocol_init,</div><div class='ctx'> 	.ops = &amp;powercap_proto_ops,</div><div class='ctx'> 	.events = &amp;powercap_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(powercap, scmi_powercap)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h<br/>index 78e1a01eb656..e683c26f24eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/protocols.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/protocols.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/protocols.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/protocols.h</a></div><div class='hunk'>@@ -174,7 +174,8 @@ struct scmi_protocol_handle {</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	const struct scmi_xfer_ops *xops;</div><div class='ctx'> 	const struct scmi_proto_helpers_ops *hops;</div><div class='del'>-	int (*set_priv)(const struct scmi_protocol_handle *ph, void *priv);</div><div class='add'>+	int (*set_priv)(const struct scmi_protocol_handle *ph, void *priv,</div><div class='add'>+			u32 version);</div><div class='ctx'> 	void *(*get_priv)(const struct scmi_protocol_handle *ph);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -256,7 +257,8 @@ struct scmi_fc_info {</div><div class='ctx'>  */</div><div class='ctx'> struct scmi_proto_helpers_ops {</div><div class='ctx'> 	int (*extended_name_get)(const struct scmi_protocol_handle *ph,</div><div class='del'>-				 u8 cmd_id, u32 res_id, char *name, size_t len);</div><div class='add'>+				 u8 cmd_id, u32 res_id, u32 *flags, char *name,</div><div class='add'>+				 size_t len);</div><div class='ctx'> 	void *(*iter_response_init)(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 				    struct scmi_iterator_ops *ops,</div><div class='ctx'> 				    unsigned int max_resources, u8 msg_id,</div><div class='hunk'>@@ -310,6 +312,10 @@ typedef int (*scmi_prot_init_ph_fn_t)(const struct scmi_protocol_handle *);</div><div class='ctx'>  * @ops: Optional reference to the operations provided by the protocol and</div><div class='ctx'>  *	 exposed in scmi_protocol.h.</div><div class='ctx'>  * @events: An optional reference to the events supported by this protocol.</div><div class='add'>+ * @supported_version: The highest version currently supported for this</div><div class='add'>+ *		       protocol by the agent. Each protocol implementation</div><div class='add'>+ *		       in the agent is supposed to downgrade to match the</div><div class='add'>+ *		       protocol version supported by the platform.</div><div class='ctx'>  */</div><div class='ctx'> struct scmi_protocol {</div><div class='ctx'> 	const u8				id;</div><div class='hunk'>@@ -318,6 +324,7 @@ struct scmi_protocol {</div><div class='ctx'> 	const scmi_prot_init_ph_fn_t		instance_deinit;</div><div class='ctx'> 	const void				*ops;</div><div class='ctx'> 	const struct scmi_protocol_events	*events;</div><div class='add'>+	unsigned int				supported_version;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(name, proto)	\</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/reset.c b/drivers/firmware/arm_scmi/reset.c<br/>index e9afa8cab730..19970d9f9e36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/reset.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/reset.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/reset.c</a></div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x30000</div><div class='add'>+</div><div class='ctx'> enum scmi_reset_protocol_cmd {</div><div class='ctx'> 	RESET_DOMAIN_ATTRIBUTES = 0x3,</div><div class='ctx'> 	RESET = 0x4,</div><div class='hunk'>@@ -128,7 +131,8 @@ scmi_reset_domain_attributes_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (!ret &amp;&amp; PROTOCOL_REV_MAJOR(version) &gt;= 0x3 &amp;&amp;</div><div class='ctx'> 	    SUPPORTS_EXTENDED_NAMES(attributes))</div><div class='ctx'> 		ph-&gt;hops-&gt;extended_name_get(ph, RESET_DOMAIN_NAME_GET, domain,</div><div class='del'>-					    dom_info-&gt;name, SCMI_MAX_STR_SIZE);</div><div class='add'>+					    NULL, dom_info-&gt;name,</div><div class='add'>+					    SCMI_MAX_STR_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -342,7 +346,7 @@ static int scmi_reset_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pinfo-&gt;version = version;</div><div class='del'>-	return ph-&gt;set_priv(ph, pinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, pinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_reset = {</div><div class='hunk'>@@ -351,6 +355,7 @@ static const struct scmi_protocol scmi_reset = {</div><div class='ctx'> 	.instance_init = &amp;scmi_reset_protocol_init,</div><div class='ctx'> 	.ops = &amp;reset_proto_ops,</div><div class='ctx'> 	.events = &amp;reset_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(reset, scmi_reset)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c<br/>index 0b5853fa9d87..311149965370 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/sensors.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/sensors.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/sensors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/sensors.c</a></div><div class='hunk'>@@ -14,6 +14,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x30000</div><div class='add'>+</div><div class='ctx'> #define SCMI_MAX_NUM_SENSOR_AXIS	63</div><div class='ctx'> #define	SCMIv2_SENSOR_PROTOCOL		0x10000</div><div class='ctx'> </div><div class='hunk'>@@ -644,7 +647,7 @@ iter_sens_descr_process_response(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 	if (PROTOCOL_REV_MAJOR(si-&gt;version) &gt;= 0x3 &amp;&amp;</div><div class='ctx'> 	    SUPPORTS_EXTENDED_NAMES(attrl))</div><div class='ctx'> 		ph-&gt;hops-&gt;extended_name_get(ph, SENSOR_NAME_GET, s-&gt;id,</div><div class='del'>-					    s-&gt;name, SCMI_MAX_STR_SIZE);</div><div class='add'>+					    NULL, s-&gt;name, SCMI_MAX_STR_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	if (s-&gt;extended_scalar_attrs) {</div><div class='ctx'> 		s-&gt;sensor_power = le32_to_cpu(sdesc-&gt;power);</div><div class='hunk'>@@ -1138,7 +1141,7 @@ static int scmi_sensors_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	return ph-&gt;set_priv(ph, sinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, sinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_sensors = {</div><div class='hunk'>@@ -1147,6 +1150,7 @@ static const struct scmi_protocol scmi_sensors = {</div><div class='ctx'> 	.instance_init = &amp;scmi_sensors_protocol_init,</div><div class='ctx'> 	.ops = &amp;sensor_proto_ops,</div><div class='ctx'> 	.events = &amp;sensor_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(sensors, scmi_sensors)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/system.c b/drivers/firmware/arm_scmi/system.c<br/>index 9383d7584539..1621da97bcbb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/system.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/system.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/system.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/system.c</a></div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> #include "notify.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x20000</div><div class='add'>+</div><div class='ctx'> #define SCMI_SYSTEM_NUM_SOURCES		1</div><div class='ctx'> </div><div class='ctx'> enum scmi_system_protocol_cmd {</div><div class='hunk'>@@ -144,7 +147,7 @@ static int scmi_system_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 	if (PROTOCOL_REV_MAJOR(pinfo-&gt;version) &gt;= 0x2)</div><div class='ctx'> 		pinfo-&gt;graceful_timeout_supported = true;</div><div class='ctx'> </div><div class='del'>-	return ph-&gt;set_priv(ph, pinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, pinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_system = {</div><div class='hunk'>@@ -153,6 +156,7 @@ static const struct scmi_protocol scmi_system = {</div><div class='ctx'> 	.instance_init = &amp;scmi_system_protocol_init,</div><div class='ctx'> 	.ops = NULL,</div><div class='ctx'> 	.events = &amp;system_protocol_events,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(system, scmi_system)</div><div class='head'>diff --git a/drivers/firmware/arm_scmi/voltage.c b/drivers/firmware/arm_scmi/voltage.c<br/>index eaa8d944926a..2175ffd6cef5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/voltage.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scmi/voltage.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scmi/voltage.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scmi/voltage.c</a></div><div class='hunk'>@@ -10,6 +10,9 @@</div><div class='ctx'> </div><div class='ctx'> #include "protocols.h"</div><div class='ctx'> </div><div class='add'>+/* Updated only after ALL the mandatory features for that version are merged */</div><div class='add'>+#define SCMI_PROTOCOL_SUPPORTED_VERSION		0x20000</div><div class='add'>+</div><div class='ctx'> #define VOLTAGE_DOMS_NUM_MASK		GENMASK(15, 0)</div><div class='ctx'> #define REMAINING_LEVELS_MASK		GENMASK(31, 16)</div><div class='ctx'> #define RETURNED_LEVELS_MASK		GENMASK(11, 0)</div><div class='hunk'>@@ -242,7 +245,7 @@ static int scmi_voltage_descriptors_get(const struct scmi_protocol_handle *ph,</div><div class='ctx'> 			if (SUPPORTS_EXTENDED_NAMES(attributes))</div><div class='ctx'> 				ph-&gt;hops-&gt;extended_name_get(ph,</div><div class='ctx'> 							VOLTAGE_DOMAIN_NAME_GET,</div><div class='del'>-							v-&gt;id, v-&gt;name,</div><div class='add'>+							v-&gt;id, NULL, v-&gt;name,</div><div class='ctx'> 							SCMI_MAX_STR_SIZE);</div><div class='ctx'> 			if (SUPPORTS_ASYNC_LEVEL_SET(attributes))</div><div class='ctx'> 				v-&gt;async_level_set = true;</div><div class='hunk'>@@ -432,7 +435,7 @@ static int scmi_voltage_protocol_init(const struct scmi_protocol_handle *ph)</div><div class='ctx'> 		dev_warn(ph-&gt;dev, "No Voltage domains found.\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ph-&gt;set_priv(ph, vinfo);</div><div class='add'>+	return ph-&gt;set_priv(ph, vinfo, version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct scmi_protocol scmi_voltage = {</div><div class='hunk'>@@ -440,6 +443,7 @@ static const struct scmi_protocol scmi_voltage = {</div><div class='ctx'> 	.owner = THIS_MODULE,</div><div class='ctx'> 	.instance_init = &amp;scmi_voltage_protocol_init,</div><div class='ctx'> 	.ops = &amp;voltage_proto_ops,</div><div class='add'>+	.supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(voltage, scmi_voltage)</div><div class='head'>diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c<br/>index 3f123f592cb4..94a6b4e667de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/arm_scpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/arm_scpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/arm_scpi.c</a></div><div class='hunk'>@@ -863,7 +863,7 @@ static void scpi_free_channels(void *data)</div><div class='ctx'> 		mbox_free_channel(info-&gt;channels[i].chan);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int scpi_remove(struct platform_device *pdev)</div><div class='add'>+static void scpi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct scpi_drvinfo *info = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -874,8 +874,6 @@ static int scpi_remove(struct platform_device *pdev)</div><div class='ctx'> 		kfree(info-&gt;dvfs[i]-&gt;opps);</div><div class='ctx'> 		kfree(info-&gt;dvfs[i]);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define MAX_SCPI_XFERS		10</div><div class='hunk'>@@ -1048,7 +1046,7 @@ static struct platform_driver scpi_driver = {</div><div class='ctx'> 		.dev_groups = versions_groups,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = scpi_probe,</div><div class='del'>-	.remove = scpi_remove,</div><div class='add'>+	.remove_new = scpi_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(scpi_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/firmware/efi/Kconfig b/drivers/firmware/efi/Kconfig<br/>index cb374b2da9b7..72f2537d90ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/Kconfig</a></div><div class='hunk'>@@ -301,3 +301,18 @@ config UEFI_CPER_X86</div><div class='ctx'> 	bool</div><div class='ctx'> 	depends on UEFI_CPER &amp;&amp; X86</div><div class='ctx'> 	default y</div><div class='add'>+</div><div class='add'>+config TEE_STMM_EFI</div><div class='add'>+	tristate "TEE-based EFI runtime variable service driver"</div><div class='add'>+	depends on EFI &amp;&amp; OPTEE</div><div class='add'>+	help</div><div class='add'>+	  Select this config option if TEE is compiled to include StandAloneMM</div><div class='add'>+	  as a separate secure partition. It has the ability to check and store</div><div class='add'>+	  EFI variables on an RPMB or any other non-volatile medium used by</div><div class='add'>+	  StandAloneMM.</div><div class='add'>+</div><div class='add'>+	  Enabling this will change the EFI runtime services from the firmware</div><div class='add'>+	  provided functions to TEE calls.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module</div><div class='add'>+	  will be called tee_stmm_efi.</div><div class='head'>diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile<br/>index e489fefd23da..a2d0009560d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/Makefile</a></div><div class='hunk'>@@ -42,3 +42,4 @@ obj-$(CONFIG_EFI_EARLYCON)		+= earlycon.o</div><div class='ctx'> obj-$(CONFIG_UEFI_CPER_ARM)		+= cper-arm.o</div><div class='ctx'> obj-$(CONFIG_UEFI_CPER_X86)		+= cper-x86.o</div><div class='ctx'> obj-$(CONFIG_UNACCEPTED_MEMORY)		+= unaccepted_memory.o</div><div class='add'>+obj-$(CONFIG_TEE_STMM_EFI)		+= stmm/tee_stmm_efi.o</div><div class='head'>diff --git a/drivers/firmware/efi/dev-path-parser.c b/drivers/firmware/efi/dev-path-parser.c<br/>index f80d87c199c3..937be269fee8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/dev-path-parser.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/dev-path-parser.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/dev-path-parser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/dev-path-parser.c</a></div><div class='hunk'>@@ -18,8 +18,6 @@ static long __init parse_acpi_path(const struct efi_dev_path *node,</div><div class='ctx'> 	struct acpi_device *adev;</div><div class='ctx'> 	struct device *phys_dev;</div><div class='ctx'> 	char hid[ACPI_ID_LEN];</div><div class='del'>-	u64 uid;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (node-&gt;header.length != 12)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -31,10 +29,9 @@ static long __init parse_acpi_path(const struct efi_dev_path *node,</div><div class='ctx'> 			node-&gt;acpi.hid &gt;&gt; 16);</div><div class='ctx'> </div><div class='ctx'> 	for_each_acpi_dev_match(adev, hid, NULL, -1) {</div><div class='del'>-		ret = acpi_dev_uid_to_integer(adev, &amp;uid);</div><div class='del'>-		if (ret == 0 &amp;&amp; node-&gt;acpi.uid == uid)</div><div class='add'>+		if (acpi_dev_uid_match(adev, node-&gt;acpi.uid))</div><div class='ctx'> 			break;</div><div class='del'>-		if (ret == -ENODATA &amp;&amp; node-&gt;acpi.uid == 0)</div><div class='add'>+		if (!acpi_device_uid(adev) &amp;&amp; node-&gt;acpi.uid == 0)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!adev)</div><div class='head'>diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c<br/>index 9d3910d1abe1..4fcda50acfa4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/efi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/efi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/efi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/efi.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include &lt;linux/ucs2_string.h&gt;</div><div class='ctx'> #include &lt;linux/memblock.h&gt;</div><div class='ctx'> #include &lt;linux/security.h&gt;</div><div class='add'>+#include &lt;linux/notifier.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/early_ioremap.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -187,6 +188,9 @@ static const struct attribute_group efi_subsys_attr_group = {</div><div class='ctx'> 	.is_visible = efi_attr_is_visible,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct blocking_notifier_head efivar_ops_nh;</div><div class='add'>+EXPORT_SYMBOL_GPL(efivar_ops_nh);</div><div class='add'>+</div><div class='ctx'> static struct efivars generic_efivars;</div><div class='ctx'> static struct efivar_operations generic_ops;</div><div class='ctx'> </div><div class='hunk'>@@ -231,6 +235,18 @@ static void generic_ops_unregister(void)</div><div class='ctx'> 	efivars_unregister(&amp;generic_efivars);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void efivars_generic_ops_register(void)</div><div class='add'>+{</div><div class='add'>+	generic_ops_register();</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(efivars_generic_ops_register);</div><div class='add'>+</div><div class='add'>+void efivars_generic_ops_unregister(void)</div><div class='add'>+{</div><div class='add'>+	generic_ops_unregister();</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(efivars_generic_ops_unregister);</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_EFI_CUSTOM_SSDT_OVERLAYS</div><div class='ctx'> #define EFIVAR_SSDT_NAME_MAX	16UL</div><div class='ctx'> static char efivar_ssdt[EFIVAR_SSDT_NAME_MAX] __initdata;</div><div class='hunk'>@@ -419,6 +435,8 @@ static int __init efisubsys_init(void)</div><div class='ctx'> 		platform_device_register_simple("efivars", 0, NULL, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	BLOCKING_INIT_NOTIFIER_HEAD(&amp;efivar_ops_nh);</div><div class='add'>+</div><div class='ctx'> 	error = sysfs_create_group(efi_kobj, &amp;efi_subsys_attr_group);</div><div class='ctx'> 	if (error) {</div><div class='ctx'> 		pr_err("efi: Sysfs attribute export failed with error %d.\n",</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/Makefile.zboot b/drivers/firmware/efi/libstub/Makefile.zboot<br/>index 2c489627a807..65ffd0b760b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/Makefile.zboot?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/libstub/Makefile.zboot</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/Makefile.zboot?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/Makefile.zboot</a></div><div class='hunk'>@@ -5,8 +5,8 @@</div><div class='ctx'> # EFI_ZBOOT_FORWARD_CFI</div><div class='ctx'> </div><div class='ctx'> quiet_cmd_copy_and_pad = PAD     $@</div><div class='del'>-      cmd_copy_and_pad = cp $&lt; $@ &amp;&amp; \</div><div class='del'>-			 truncate -s $(shell hexdump -s16 -n4 -e '"%u"' $&lt;) $@</div><div class='add'>+      cmd_copy_and_pad = cp $&lt; $@; \</div><div class='add'>+			 truncate -s $$(hexdump -s16 -n4 -e '"%u"' $&lt;) $@</div><div class='ctx'> </div><div class='ctx'> # Pad the file to the size of the uncompressed image in memory, including BSS</div><div class='ctx'> $(obj)/vmlinux.bin: $(obj)/$(EFI_ZBOOT_PAYLOAD) FORCE</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/loongarch-stub.c b/drivers/firmware/efi/libstub/loongarch-stub.c<br/>index 72c71ae201f0..736b6aae323d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/loongarch-stub.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/libstub/loongarch-stub.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/loongarch-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch-stub.c</a></div><div class='hunk'>@@ -8,10 +8,10 @@</div><div class='ctx'> #include &lt;asm/efi.h&gt;</div><div class='ctx'> #include &lt;asm/addrspace.h&gt;</div><div class='ctx'> #include "efistub.h"</div><div class='add'>+#include "loongarch-stub.h"</div><div class='ctx'> </div><div class='ctx'> extern int kernel_asize;</div><div class='ctx'> extern int kernel_fsize;</div><div class='del'>-extern int kernel_offset;</div><div class='ctx'> extern int kernel_entry;</div><div class='ctx'> </div><div class='ctx'> efi_status_t handle_kernel_image(unsigned long *image_addr,</div><div class='hunk'>@@ -24,7 +24,7 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,</div><div class='ctx'> 	efi_status_t status;</div><div class='ctx'> 	unsigned long kernel_addr = 0;</div><div class='ctx'> </div><div class='del'>-	kernel_addr = (unsigned long)&amp;kernel_offset - kernel_offset;</div><div class='add'>+	kernel_addr = (unsigned long)image-&gt;image_base;</div><div class='ctx'> </div><div class='ctx'> 	status = efi_relocate_kernel(&amp;kernel_addr, kernel_fsize, kernel_asize,</div><div class='ctx'> 		     EFI_KIMG_PREFERRED_ADDRESS, efi_get_kimg_min_align(), 0x0);</div><div class='hunk'>@@ -35,9 +35,10 @@ efi_status_t handle_kernel_image(unsigned long *image_addr,</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-unsigned long kernel_entry_address(void)</div><div class='add'>+unsigned long kernel_entry_address(unsigned long kernel_addr,</div><div class='add'>+		efi_loaded_image_t *image)</div><div class='ctx'> {</div><div class='del'>-	unsigned long base = (unsigned long)&amp;kernel_offset - kernel_offset;</div><div class='add'>+	unsigned long base = (unsigned long)image-&gt;image_base;</div><div class='ctx'> </div><div class='del'>-	return (unsigned long)&amp;kernel_entry - base + VMLINUX_LOAD_ADDRESS;</div><div class='add'>+	return (unsigned long)&amp;kernel_entry - base + kernel_addr;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/loongarch-stub.h b/drivers/firmware/efi/libstub/loongarch-stub.h<br/>new file mode 100644<br/>index 000000000000..cd015955a015<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/loongarch-stub.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch-stub.h</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+</div><div class='add'>+unsigned long kernel_entry_address(unsigned long kernel_addr,</div><div class='add'>+		efi_loaded_image_t *image);</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/loongarch.c b/drivers/firmware/efi/libstub/loongarch.c<br/>index 807cba2693fc..684c9354637c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/loongarch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/libstub/loongarch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/loongarch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/loongarch.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include &lt;asm/efi.h&gt;</div><div class='ctx'> #include &lt;asm/addrspace.h&gt;</div><div class='ctx'> #include "efistub.h"</div><div class='add'>+#include "loongarch-stub.h"</div><div class='ctx'> </div><div class='ctx'> typedef void __noreturn (*kernel_entry_t)(bool efi, unsigned long cmdline,</div><div class='ctx'> 					  unsigned long systab);</div><div class='hunk'>@@ -37,9 +38,10 @@ static efi_status_t exit_boot_func(struct efi_boot_memmap *map, void *priv)</div><div class='ctx'> 	return EFI_SUCCESS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-unsigned long __weak kernel_entry_address(void)</div><div class='add'>+unsigned long __weak kernel_entry_address(unsigned long kernel_addr,</div><div class='add'>+		efi_loaded_image_t *image)</div><div class='ctx'> {</div><div class='del'>-	return *(unsigned long *)(PHYSADDR(VMLINUX_LOAD_ADDRESS) + 8);</div><div class='add'>+	return *(unsigned long *)(kernel_addr + 8) - VMLINUX_LOAD_ADDRESS + kernel_addr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> efi_status_t efi_boot_kernel(void *handle, efi_loaded_image_t *image,</div><div class='hunk'>@@ -73,7 +75,7 @@ efi_status_t efi_boot_kernel(void *handle, efi_loaded_image_t *image,</div><div class='ctx'> 	csr_write64(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0);</div><div class='ctx'> 	csr_write64(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1);</div><div class='ctx'> </div><div class='del'>-	real_kernel_entry = (void *)kernel_entry_address();</div><div class='add'>+	real_kernel_entry = (void *)kernel_entry_address(kernel_addr, image);</div><div class='ctx'> </div><div class='ctx'> 	real_kernel_entry(true, (unsigned long)cmdline_ptr,</div><div class='ctx'> 			  (unsigned long)efi_system_table);</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c<br/>index 479dd445acdc..77359e802181 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/x86-5lvl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/libstub/x86-5lvl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/x86-5lvl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/x86-5lvl.c</a></div><div class='hunk'>@@ -13,8 +13,8 @@ bool efi_no5lvl;</div><div class='ctx'> static void (*la57_toggle)(void *cr3);</div><div class='ctx'> </div><div class='ctx'> static const struct desc_struct gdt[] = {</div><div class='del'>-	[GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),</div><div class='del'>-	[GDT_ENTRY_KERNEL_CS]   = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),</div><div class='add'>+	[GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),</div><div class='add'>+	[GDT_ENTRY_KERNEL_CS]   = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/firmware/efi/libstub/x86-stub.c b/drivers/firmware/efi/libstub/x86-stub.c<br/>index 1bfdae34df39..0d510c9a06a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/x86-stub.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/libstub/x86-stub.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/libstub/x86-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/libstub/x86-stub.c</a></div><div class='hunk'>@@ -307,17 +307,20 @@ static void setup_unaccepted_memory(void)</div><div class='ctx'> 		efi_err("Memory acceptance protocol failed\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static efi_char16_t *efistub_fw_vendor(void)</div><div class='add'>+{</div><div class='add'>+	unsigned long vendor = efi_table_attr(efi_system_table, fw_vendor);</div><div class='add'>+</div><div class='add'>+	return (efi_char16_t *)vendor;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const efi_char16_t apple[] = L"Apple";</div><div class='ctx'> </div><div class='ctx'> static void setup_quirks(struct boot_params *boot_params)</div><div class='ctx'> {</div><div class='del'>-	efi_char16_t *fw_vendor = (efi_char16_t *)(unsigned long)</div><div class='del'>-		efi_table_attr(efi_system_table, fw_vendor);</div><div class='del'>-</div><div class='del'>-	if (!memcmp(fw_vendor, apple, sizeof(apple))) {</div><div class='del'>-		if (IS_ENABLED(CONFIG_APPLE_PROPERTIES))</div><div class='del'>-			retrieve_apple_device_properties(boot_params);</div><div class='del'>-	}</div><div class='add'>+	if (IS_ENABLED(CONFIG_APPLE_PROPERTIES) &amp;&amp;</div><div class='add'>+	    !memcmp(efistub_fw_vendor(), apple, sizeof(apple)))</div><div class='add'>+		retrieve_apple_device_properties(boot_params);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -765,11 +768,27 @@ static efi_status_t efi_decompress_kernel(unsigned long *kernel_entry)</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) &amp;&amp; !efi_nokaslr) {</div><div class='ctx'> 		u64 range = KERNEL_IMAGE_SIZE - LOAD_PHYSICAL_ADDR - kernel_total_size;</div><div class='add'>+		static const efi_char16_t ami[] = L"American Megatrends";</div><div class='ctx'> </div><div class='ctx'> 		efi_get_seed(seed, sizeof(seed));</div><div class='ctx'> </div><div class='ctx'> 		virt_addr += (range * seed[1]) &gt;&gt; 32;</div><div class='ctx'> 		virt_addr &amp;= ~(CONFIG_PHYSICAL_ALIGN - 1);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Older Dell systems with AMI UEFI firmware v2.0 may hang</div><div class='add'>+		 * while decompressing the kernel if physical address</div><div class='add'>+		 * randomization is enabled.</div><div class='add'>+		 *</div><div class='add'>+		 * https://bugzilla.kernel.org/show_bug.cgi?id=218173</div><div class='add'>+		 */</div><div class='add'>+		if (efi_system_table-&gt;hdr.revision &lt;= EFI_2_00_SYSTEM_TABLE_REVISION &amp;&amp;</div><div class='add'>+		    !memcmp(efistub_fw_vendor(), ami, sizeof(ami))) {</div><div class='add'>+			efi_debug("AMI firmware v2.0 or older detected - disabling physical KASLR\n");</div><div class='add'>+			seed[0] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		boot_params_ptr-&gt;hdr.loadflags |= KASLR_FLAG;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = efi_random_alloc(alloc_size, CONFIG_PHYSICAL_ALIGN, &amp;addr,</div><div class='head'>diff --git a/drivers/firmware/efi/memmap.c b/drivers/firmware/efi/memmap.c<br/>index a1180461a445..3365944f7965 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/memmap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/memmap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/memmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/memmap.c</a></div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'>  * space isn't setup.  Once the kernel is fully booted we can fallback</div><div class='ctx'>  * to the more robust memremap*() API.</div><div class='ctx'>  *</div><div class='del'>- * Returns zero on success, a negative error code on failure.</div><div class='add'>+ * Returns: zero on success, a negative error code on failure.</div><div class='ctx'>  */</div><div class='ctx'> int __init __efi_memmap_init(struct efi_memory_map_data *data)</div><div class='ctx'> {</div><div class='hunk'>@@ -77,6 +77,8 @@ int __init __efi_memmap_init(struct efi_memory_map_data *data)</div><div class='ctx'>  *</div><div class='ctx'>  * Use early_memremap() to map the passed in EFI memory map and assign</div><div class='ctx'>  * it to efi.memmap.</div><div class='add'>+ *</div><div class='add'>+ * Returns: zero on success, a negative error code on failure.</div><div class='ctx'>  */</div><div class='ctx'> int __init efi_memmap_init_early(struct efi_memory_map_data *data)</div><div class='ctx'> {</div><div class='hunk'>@@ -107,7 +109,7 @@ void __init efi_memmap_unmap(void)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * efi_memmap_init_late - Map efi.memmap with memremap()</div><div class='del'>- * @phys_addr: Physical address of the new EFI memory map</div><div class='add'>+ * @addr: Physical address of the new EFI memory map</div><div class='ctx'>  * @size: Size in bytes of the new EFI memory map</div><div class='ctx'>  *</div><div class='ctx'>  * Setup a mapping of the EFI memory map using ioremap_cache(). This</div><div class='hunk'>@@ -126,7 +128,7 @@ void __init efi_memmap_unmap(void)</div><div class='ctx'>  * runtime so that things like efi_mem_desc_lookup() and</div><div class='ctx'>  * efi_mem_attributes() always work.</div><div class='ctx'>  *</div><div class='del'>- * Returns zero on success, a negative error code on failure.</div><div class='add'>+ * Returns: zero on success, a negative error code on failure.</div><div class='ctx'>  */</div><div class='ctx'> int __init efi_memmap_init_late(phys_addr_t addr, unsigned long size)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/firmware/efi/stmm/mm_communication.h b/drivers/firmware/efi/stmm/mm_communication.h<br/>new file mode 100644<br/>index 000000000000..52a1f32cd1eb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/stmm/mm_communication.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/stmm/mm_communication.h</a></div><div class='hunk'>@@ -0,0 +1,236 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0+ */</div><div class='add'>+/*</div><div class='add'>+ *  Headers for EFI variable service via StandAloneMM, EDK2 application running</div><div class='add'>+ *  in OP-TEE. Most of the structs and defines resemble the EDK2 naming.</div><div class='add'>+ *</div><div class='add'>+ *  Copyright (c) 2017, Intel Corporation. All rights reserved.</div><div class='add'>+ *  Copyright (C) 2020 Linaro Ltd.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _MM_COMMUNICATION_H_</div><div class='add'>+#define _MM_COMMUNICATION_H_</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Interface to the pseudo Trusted Application (TA), which provides a</div><div class='add'>+ * communication channel with the Standalone MM (Management Mode)</div><div class='add'>+ * Secure Partition running at Secure-EL0</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define PTA_STMM_CMD_COMMUNICATE 0</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Defined in OP-TEE, this UUID is used to identify the pseudo-TA.</div><div class='add'>+ * OP-TEE is using big endian GUIDs while UEFI uses little endian ones</div><div class='add'>+ */</div><div class='add'>+#define PTA_STMM_UUID \</div><div class='add'>+	UUID_INIT(0xed32d533, 0x99e6, 0x4209, \</div><div class='add'>+		  0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7)</div><div class='add'>+</div><div class='add'>+#define EFI_MM_VARIABLE_GUID \</div><div class='add'>+	EFI_GUID(0xed32d533, 0x99e6, 0x4209, \</div><div class='add'>+		 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct efi_mm_communicate_header - Header used for SMM variable communication</div><div class='add'>+</div><div class='add'>+ * @header_guid:  header use for disambiguation of content</div><div class='add'>+ * @message_len:  length of the message. Does not include the size of the</div><div class='add'>+ *                header</div><div class='add'>+ * @data:         payload of the message</div><div class='add'>+ *</div><div class='add'>+ * Defined in the PI spec as EFI_MM_COMMUNICATE_HEADER.</div><div class='add'>+ * To avoid confusion in interpreting frames, the communication buffer should</div><div class='add'>+ * always begin with efi_mm_communicate_header.</div><div class='add'>+ */</div><div class='add'>+struct efi_mm_communicate_header {</div><div class='add'>+	efi_guid_t header_guid;</div><div class='add'>+	size_t     message_len;</div><div class='add'>+	u8         data[];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#define MM_COMMUNICATE_HEADER_SIZE \</div><div class='add'>+	(sizeof(struct efi_mm_communicate_header))</div><div class='add'>+</div><div class='add'>+/* SPM return error codes */</div><div class='add'>+#define ARM_SVC_SPM_RET_SUCCESS               0</div><div class='add'>+#define ARM_SVC_SPM_RET_NOT_SUPPORTED        -1</div><div class='add'>+#define ARM_SVC_SPM_RET_INVALID_PARAMS       -2</div><div class='add'>+#define ARM_SVC_SPM_RET_DENIED               -3</div><div class='add'>+#define ARM_SVC_SPM_RET_NO_MEMORY            -5</div><div class='add'>+</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_GET_VARIABLE  1</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is</div><div class='add'>+ * SMM_VARIABLE_COMMUNICATE_GET_NEXT_VARIABLE_NAME.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_GET_NEXT_VARIABLE_NAME  2</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is SMM_VARIABLE_COMMUNICATE_ACCESS_VARIABLE.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_SET_VARIABLE  3</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is</div><div class='add'>+ * SMM_VARIABLE_COMMUNICATE_QUERY_VARIABLE_INFO.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_QUERY_VARIABLE_INFO  4</div><div class='add'>+/*</div><div class='add'>+ * It is a notify event, no extra payload for this function.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_READY_TO_BOOT  5</div><div class='add'>+/*</div><div class='add'>+ * It is a notify event, no extra payload for this function.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_EXIT_BOOT_SERVICE  6</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is VARIABLE_INFO_ENTRY.</div><div class='add'>+ * The GUID in EFI_SMM_COMMUNICATE_HEADER is gEfiSmmVariableProtocolGuid.</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_GET_STATISTICS  7</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is SMM_VARIABLE_COMMUNICATE_LOCK_VARIABLE</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_LOCK_VARIABLE   8</div><div class='add'>+</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_SET  9</div><div class='add'>+</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET  10</div><div class='add'>+</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_GET_PAYLOAD_SIZE  11</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is</div><div class='add'>+ * SMM_VARIABLE_COMMUNICATE_RUNTIME_VARIABLE_CACHE_CONTEXT</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_INIT_RUNTIME_VARIABLE_CACHE_CONTEXT 12</div><div class='add'>+</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_SYNC_RUNTIME_CACHE  13</div><div class='add'>+/*</div><div class='add'>+ * The payload for this function is</div><div class='add'>+ * SMM_VARIABLE_COMMUNICATE_GET_RUNTIME_CACHE_INFO</div><div class='add'>+ */</div><div class='add'>+#define SMM_VARIABLE_FUNCTION_GET_RUNTIME_CACHE_INFO  14</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_communicate_header - Used for SMM variable communication</div><div class='add'>+</div><div class='add'>+ * @function:     function to call in Smm.</div><div class='add'>+ * @ret_status:   return status</div><div class='add'>+ * @data:         payload</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_communicate_header {</div><div class='add'>+	size_t  function;</div><div class='add'>+	efi_status_t ret_status;</div><div class='add'>+	u8 data[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MM_VARIABLE_COMMUNICATE_SIZE \</div><div class='add'>+	(sizeof(struct smm_variable_communicate_header))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_access - Used to communicate with StMM by</div><div class='add'>+ *                              SetVariable and GetVariable.</div><div class='add'>+</div><div class='add'>+ * @guid:         vendor GUID</div><div class='add'>+ * @data_size:    size of EFI variable data</div><div class='add'>+ * @name_size:    size of EFI name</div><div class='add'>+ * @attr:         attributes</div><div class='add'>+ * @name:         variable name</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_access {</div><div class='add'>+	efi_guid_t  guid;</div><div class='add'>+	size_t data_size;</div><div class='add'>+	size_t name_size;</div><div class='add'>+	u32 attr;</div><div class='add'>+	u16 name[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MM_VARIABLE_ACCESS_HEADER_SIZE \</div><div class='add'>+	(sizeof(struct smm_variable_access))</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_payload_size - Used to get the max allowed</div><div class='add'>+ *                                    payload used in StMM.</div><div class='add'>+ *</div><div class='add'>+ * @size:  size to fill in</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_payload_size {</div><div class='add'>+	size_t size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_getnext - Used to communicate with StMM for</div><div class='add'>+ *                               GetNextVariableName.</div><div class='add'>+ *</div><div class='add'>+ * @guid:       vendor GUID</div><div class='add'>+ * @name_size:  size of the name of the variable</div><div class='add'>+ * @name:       variable name</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_getnext {</div><div class='add'>+	efi_guid_t  guid;</div><div class='add'>+	size_t name_size;</div><div class='add'>+	u16         name[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MM_VARIABLE_GET_NEXT_HEADER_SIZE \</div><div class='add'>+	(sizeof(struct smm_variable_getnext))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_query_info - Used to communicate with StMM for</div><div class='add'>+ *                                  QueryVariableInfo.</div><div class='add'>+ *</div><div class='add'>+ * @max_variable_storage:        max available storage</div><div class='add'>+ * @remaining_variable_storage:  remaining available storage</div><div class='add'>+ * @max_variable_size:           max variable supported size</div><div class='add'>+ * @attr:                        attributes to query storage for</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_query_info {</div><div class='add'>+	u64 max_variable_storage;</div><div class='add'>+	u64 remaining_variable_storage;</div><div class='add'>+	u64 max_variable_size;</div><div class='add'>+	u32 attr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define VAR_CHECK_VARIABLE_PROPERTY_REVISION 0x0001</div><div class='add'>+#define VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY BIT(0)</div><div class='add'>+/**</div><div class='add'>+ * struct var_check_property - Used to store variable properties in StMM</div><div class='add'>+ *</div><div class='add'>+ * @revision:   magic revision number for variable property checking</div><div class='add'>+ * @property:   properties mask for the variable used in StMM.</div><div class='add'>+ *              Currently RO flag is supported</div><div class='add'>+ * @attributes: variable attributes used in StMM checking when properties</div><div class='add'>+ *              for a variable are enabled</div><div class='add'>+ * @minsize:    minimum allowed size for variable payload checked against</div><div class='add'>+ *              smm_variable_access-&gt;datasize in StMM</div><div class='add'>+ * @maxsize:    maximum allowed size for variable payload checked against</div><div class='add'>+ *              smm_variable_access-&gt;datasize in StMM</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct var_check_property {</div><div class='add'>+	u16 revision;</div><div class='add'>+	u16 property;</div><div class='add'>+	u32 attributes;</div><div class='add'>+	size_t minsize;</div><div class='add'>+	size_t maxsize;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct smm_variable_var_check_property - Used to communicate variable</div><div class='add'>+ *                                          properties with StMM</div><div class='add'>+ *</div><div class='add'>+ * @guid:       vendor GUID</div><div class='add'>+ * @name_size:  size of EFI name</div><div class='add'>+ * @property:   variable properties struct</div><div class='add'>+ * @name:       variable name</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct smm_variable_var_check_property {</div><div class='add'>+	efi_guid_t guid;</div><div class='add'>+	size_t name_size;</div><div class='add'>+	struct var_check_property property;</div><div class='add'>+	u16 name[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif /* _MM_COMMUNICATION_H_ */</div><div class='head'>diff --git a/drivers/firmware/efi/stmm/tee_stmm_efi.c b/drivers/firmware/efi/stmm/tee_stmm_efi.c<br/>new file mode 100644<br/>index 000000000000..f741ca279052<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/stmm/tee_stmm_efi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/stmm/tee_stmm_efi.c</a></div><div class='hunk'>@@ -0,0 +1,616 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ *  EFI variable service via TEE</div><div class='add'>+ *</div><div class='add'>+ *  Copyright (C) 2022 Linaro</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/efi.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/tee.h&gt;</div><div class='add'>+#include &lt;linux/tee_drv.h&gt;</div><div class='add'>+#include &lt;linux/ucs2_string.h&gt;</div><div class='add'>+#include "mm_communication.h"</div><div class='add'>+</div><div class='add'>+static struct efivars tee_efivars;</div><div class='add'>+static struct efivar_operations tee_efivar_ops;</div><div class='add'>+</div><div class='add'>+static size_t max_buffer_size; /* comm + var + func + data */</div><div class='add'>+static size_t max_payload_size; /* func + data */</div><div class='add'>+</div><div class='add'>+struct tee_stmm_efi_private {</div><div class='add'>+	struct tee_context *ctx;</div><div class='add'>+	u32 session;</div><div class='add'>+	struct device *dev;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct tee_stmm_efi_private pvt_data;</div><div class='add'>+</div><div class='add'>+/* UUID of the stmm PTA */</div><div class='add'>+static const struct tee_client_device_id tee_stmm_efi_id_table[] = {</div><div class='add'>+	{PTA_STMM_UUID},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int tee_ctx_match(struct tee_ioctl_version_data *ver, const void *data)</div><div class='add'>+{</div><div class='add'>+	/* currently only OP-TEE is supported as a communication path */</div><div class='add'>+	if (ver-&gt;impl_id == TEE_IMPL_ID_OPTEE)</div><div class='add'>+		return 1;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * tee_mm_communicate() - Pass a buffer to StandaloneMM running in TEE</div><div class='add'>+ *</div><div class='add'>+ * @comm_buf:		locally allocated communication buffer</div><div class='add'>+ * @dsize:		buffer size</div><div class='add'>+ * Return:		status code</div><div class='add'>+ */</div><div class='add'>+static efi_status_t tee_mm_communicate(void *comm_buf, size_t dsize)</div><div class='add'>+{</div><div class='add'>+	size_t buf_size;</div><div class='add'>+	struct efi_mm_communicate_header *mm_hdr;</div><div class='add'>+	struct tee_ioctl_invoke_arg arg;</div><div class='add'>+	struct tee_param param[4];</div><div class='add'>+	struct tee_shm *shm = NULL;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (!comm_buf)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;</div><div class='add'>+	buf_size = mm_hdr-&gt;message_len + sizeof(efi_guid_t) + sizeof(size_t);</div><div class='add'>+</div><div class='add'>+	if (dsize != buf_size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	shm = tee_shm_register_kernel_buf(pvt_data.ctx, comm_buf, buf_size);</div><div class='add'>+	if (IS_ERR(shm)) {</div><div class='add'>+		dev_err(pvt_data.dev, "Unable to register shared memory\n");</div><div class='add'>+		return EFI_UNSUPPORTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(&amp;arg, 0, sizeof(arg));</div><div class='add'>+	arg.func = PTA_STMM_CMD_COMMUNICATE;</div><div class='add'>+	arg.session = pvt_data.session;</div><div class='add'>+	arg.num_params = 4;</div><div class='add'>+</div><div class='add'>+	memset(param, 0, sizeof(param));</div><div class='add'>+	param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT;</div><div class='add'>+	param[0].u.memref.size = buf_size;</div><div class='add'>+	param[0].u.memref.shm = shm;</div><div class='add'>+	param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT;</div><div class='add'>+	param[2].attr = TEE_IOCTL_PARAM_ATTR_TYPE_NONE;</div><div class='add'>+	param[3].attr = TEE_IOCTL_PARAM_ATTR_TYPE_NONE;</div><div class='add'>+</div><div class='add'>+	rc = tee_client_invoke_func(pvt_data.ctx, &amp;arg, param);</div><div class='add'>+	tee_shm_free(shm);</div><div class='add'>+</div><div class='add'>+	if (rc &lt; 0 || arg.ret != 0) {</div><div class='add'>+		dev_err(pvt_data.dev,</div><div class='add'>+			"PTA_STMM_CMD_COMMUNICATE invoke error: 0x%x\n", arg.ret);</div><div class='add'>+		return EFI_DEVICE_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (param[1].u.value.a) {</div><div class='add'>+	case ARM_SVC_SPM_RET_SUCCESS:</div><div class='add'>+		return EFI_SUCCESS;</div><div class='add'>+</div><div class='add'>+	case ARM_SVC_SPM_RET_INVALID_PARAMS:</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	case ARM_SVC_SPM_RET_DENIED:</div><div class='add'>+		return EFI_ACCESS_DENIED;</div><div class='add'>+</div><div class='add'>+	case ARM_SVC_SPM_RET_NO_MEMORY:</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return EFI_ACCESS_DENIED;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * mm_communicate() - Adjust the communication buffer to StandAlonneMM and send</div><div class='add'>+ * it to TEE</div><div class='add'>+ *</div><div class='add'>+ * @comm_buf:		locally allocated communication buffer, buffer should</div><div class='add'>+ *			be enough big to have some headers and payload</div><div class='add'>+ * @payload_size:	payload size</div><div class='add'>+ * Return:		status code</div><div class='add'>+ */</div><div class='add'>+static efi_status_t mm_communicate(u8 *comm_buf, size_t payload_size)</div><div class='add'>+{</div><div class='add'>+	size_t dsize;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+	struct efi_mm_communicate_header *mm_hdr;</div><div class='add'>+	struct smm_variable_communicate_header *var_hdr;</div><div class='add'>+</div><div class='add'>+	dsize = payload_size + MM_COMMUNICATE_HEADER_SIZE +</div><div class='add'>+		MM_VARIABLE_COMMUNICATE_SIZE;</div><div class='add'>+	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;</div><div class='add'>+	var_hdr = (struct smm_variable_communicate_header *)mm_hdr-&gt;data;</div><div class='add'>+</div><div class='add'>+	ret = tee_mm_communicate(comm_buf, dsize);</div><div class='add'>+	if (ret != EFI_SUCCESS) {</div><div class='add'>+		dev_err(pvt_data.dev, "%s failed!\n", __func__);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return var_hdr-&gt;ret_status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * setup_mm_hdr() -	Allocate a buffer for StandAloneMM and initialize the</div><div class='add'>+ *			header data.</div><div class='add'>+ *</div><div class='add'>+ * @dptr:		pointer address to store allocated buffer</div><div class='add'>+ * @payload_size:	payload size</div><div class='add'>+ * @func:		standAloneMM function number</div><div class='add'>+ * @ret:		EFI return code</div><div class='add'>+ * Return:		pointer to corresponding StandAloneMM function buffer or NULL</div><div class='add'>+ */</div><div class='add'>+static void *setup_mm_hdr(u8 **dptr, size_t payload_size, size_t func,</div><div class='add'>+			  efi_status_t *ret)</div><div class='add'>+{</div><div class='add'>+	const efi_guid_t mm_var_guid = EFI_MM_VARIABLE_GUID;</div><div class='add'>+	struct efi_mm_communicate_header *mm_hdr;</div><div class='add'>+	struct smm_variable_communicate_header *var_hdr;</div><div class='add'>+	u8 *comm_buf;</div><div class='add'>+</div><div class='add'>+	/* In the init function we initialize max_buffer_size with</div><div class='add'>+	 * get_max_payload(). So skip the test if max_buffer_size is initialized</div><div class='add'>+	 * StandAloneMM will perform similar checks and drop the buffer if it's</div><div class='add'>+	 * too long</div><div class='add'>+	 */</div><div class='add'>+	if (max_buffer_size &amp;&amp;</div><div class='add'>+	    max_buffer_size &lt; (MM_COMMUNICATE_HEADER_SIZE +</div><div class='add'>+			       MM_VARIABLE_COMMUNICATE_SIZE + payload_size)) {</div><div class='add'>+		*ret = EFI_INVALID_PARAMETER;</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	comm_buf = kzalloc(MM_COMMUNICATE_HEADER_SIZE +</div><div class='add'>+				   MM_VARIABLE_COMMUNICATE_SIZE + payload_size,</div><div class='add'>+			   GFP_KERNEL);</div><div class='add'>+	if (!comm_buf) {</div><div class='add'>+		*ret = EFI_OUT_OF_RESOURCES;</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;</div><div class='add'>+	memcpy(&amp;mm_hdr-&gt;header_guid, &amp;mm_var_guid, sizeof(mm_hdr-&gt;header_guid));</div><div class='add'>+	mm_hdr-&gt;message_len = MM_VARIABLE_COMMUNICATE_SIZE + payload_size;</div><div class='add'>+</div><div class='add'>+	var_hdr = (struct smm_variable_communicate_header *)mm_hdr-&gt;data;</div><div class='add'>+	var_hdr-&gt;function = func;</div><div class='add'>+	if (dptr)</div><div class='add'>+		*dptr = comm_buf;</div><div class='add'>+	*ret = EFI_SUCCESS;</div><div class='add'>+</div><div class='add'>+	return var_hdr-&gt;data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * get_max_payload() - Get variable payload size from StandAloneMM.</div><div class='add'>+ *</div><div class='add'>+ * @size:    size of the variable in storage</div><div class='add'>+ * Return:   status code</div><div class='add'>+ */</div><div class='add'>+static efi_status_t get_max_payload(size_t *size)</div><div class='add'>+{</div><div class='add'>+	struct smm_variable_payload_size *var_payload = NULL;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	u8 *comm_buf = NULL;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+</div><div class='add'>+	if (!size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	payload_size = sizeof(*var_payload);</div><div class='add'>+	var_payload = setup_mm_hdr(&amp;comm_buf, payload_size,</div><div class='add'>+				   SMM_VARIABLE_FUNCTION_GET_PAYLOAD_SIZE,</div><div class='add'>+				   &amp;ret);</div><div class='add'>+	if (!var_payload)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* Make sure the buffer is big enough for storing variables */</div><div class='add'>+	if (var_payload-&gt;size &lt; MM_VARIABLE_ACCESS_HEADER_SIZE + 0x20) {</div><div class='add'>+		ret = EFI_DEVICE_ERROR;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	*size = var_payload-&gt;size;</div><div class='add'>+	/*</div><div class='add'>+	 * There seems to be a bug in EDK2 miscalculating the boundaries and</div><div class='add'>+	 * size checks, so deduct 2 more bytes to fulfill this requirement. Fix</div><div class='add'>+	 * it up here to ensure backwards compatibility with older versions</div><div class='add'>+	 * (cf. StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c.</div><div class='add'>+	 * sizeof (EFI_MM_COMMUNICATE_HEADER) instead the size minus the</div><div class='add'>+	 * flexible array member).</div><div class='add'>+	 *</div><div class='add'>+	 * size is guaranteed to be &gt; 2 due to checks on the beginning.</div><div class='add'>+	 */</div><div class='add'>+	*size -= 2;</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t get_property_int(u16 *name, size_t name_size,</div><div class='add'>+				     const efi_guid_t *vendor,</div><div class='add'>+				     struct var_check_property *var_property)</div><div class='add'>+{</div><div class='add'>+	struct smm_variable_var_check_property *smm_property;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	u8 *comm_buf = NULL;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+</div><div class='add'>+	memset(var_property, 0, sizeof(*var_property));</div><div class='add'>+	payload_size = sizeof(*smm_property) + name_size;</div><div class='add'>+	if (payload_size &gt; max_payload_size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	smm_property = setup_mm_hdr(</div><div class='add'>+		&amp;comm_buf, payload_size,</div><div class='add'>+		SMM_VARIABLE_FUNCTION_VAR_CHECK_VARIABLE_PROPERTY_GET, &amp;ret);</div><div class='add'>+	if (!smm_property)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;smm_property-&gt;guid, vendor, sizeof(smm_property-&gt;guid));</div><div class='add'>+	smm_property-&gt;name_size = name_size;</div><div class='add'>+	memcpy(smm_property-&gt;name, name, name_size);</div><div class='add'>+</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	/*</div><div class='add'>+	 * Currently only R/O property is supported in StMM.</div><div class='add'>+	 * Variables that are not set to R/O will not set the property in StMM</div><div class='add'>+	 * and the call will return EFI_NOT_FOUND. We are setting the</div><div class='add'>+	 * properties to 0x0 so checking against that is enough for the</div><div class='add'>+	 * EFI_NOT_FOUND case.</div><div class='add'>+	 */</div><div class='add'>+	if (ret == EFI_NOT_FOUND)</div><div class='add'>+		ret = EFI_SUCCESS;</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+	memcpy(var_property, &amp;smm_property-&gt;property, sizeof(*var_property));</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t tee_get_variable(u16 *name, efi_guid_t *vendor,</div><div class='add'>+				     u32 *attributes, unsigned long *data_size,</div><div class='add'>+				     void *data)</div><div class='add'>+{</div><div class='add'>+	struct var_check_property var_property;</div><div class='add'>+	struct smm_variable_access *var_acc;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	size_t name_size;</div><div class='add'>+	size_t tmp_dsize;</div><div class='add'>+	u8 *comm_buf = NULL;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+</div><div class='add'>+	if (!name || !vendor || !data_size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	name_size = (ucs2_strnlen(name, EFI_VAR_NAME_LEN) + 1) * sizeof(u16);</div><div class='add'>+	if (name_size &gt; max_payload_size - MM_VARIABLE_ACCESS_HEADER_SIZE)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	/* Trim output buffer size */</div><div class='add'>+	tmp_dsize = *data_size;</div><div class='add'>+	if (name_size + tmp_dsize &gt;</div><div class='add'>+	    max_payload_size - MM_VARIABLE_ACCESS_HEADER_SIZE) {</div><div class='add'>+		tmp_dsize = max_payload_size - MM_VARIABLE_ACCESS_HEADER_SIZE -</div><div class='add'>+			    name_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	payload_size = MM_VARIABLE_ACCESS_HEADER_SIZE + name_size + tmp_dsize;</div><div class='add'>+	var_acc = setup_mm_hdr(&amp;comm_buf, payload_size,</div><div class='add'>+			       SMM_VARIABLE_FUNCTION_GET_VARIABLE, &amp;ret);</div><div class='add'>+	if (!var_acc)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	/* Fill in contents */</div><div class='add'>+	memcpy(&amp;var_acc-&gt;guid, vendor, sizeof(var_acc-&gt;guid));</div><div class='add'>+	var_acc-&gt;data_size = tmp_dsize;</div><div class='add'>+	var_acc-&gt;name_size = name_size;</div><div class='add'>+	var_acc-&gt;attr = attributes ? *attributes : 0;</div><div class='add'>+	memcpy(var_acc-&gt;name, name, name_size);</div><div class='add'>+</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL)</div><div class='add'>+		/* Update with reported data size for trimmed case */</div><div class='add'>+		*data_size = var_acc-&gt;data_size;</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = get_property_int(name, name_size, vendor, &amp;var_property);</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (attributes)</div><div class='add'>+		*attributes = var_acc-&gt;attr;</div><div class='add'>+</div><div class='add'>+	if (!data) {</div><div class='add'>+		ret = EFI_INVALID_PARAMETER;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	memcpy(data, (u8 *)var_acc-&gt;name + var_acc-&gt;name_size,</div><div class='add'>+	       var_acc-&gt;data_size);</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t tee_get_next_variable(unsigned long *name_size,</div><div class='add'>+					  efi_char16_t *name, efi_guid_t *guid)</div><div class='add'>+{</div><div class='add'>+	struct smm_variable_getnext *var_getnext;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	size_t out_name_size;</div><div class='add'>+	size_t in_name_size;</div><div class='add'>+	u8 *comm_buf = NULL;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+</div><div class='add'>+	if (!name_size || !name || !guid)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	out_name_size = *name_size;</div><div class='add'>+	in_name_size = (ucs2_strnlen(name, EFI_VAR_NAME_LEN) + 1) * sizeof(u16);</div><div class='add'>+</div><div class='add'>+	if (out_name_size &lt; in_name_size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	if (in_name_size &gt; max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	/* Trim output buffer size */</div><div class='add'>+	if (out_name_size &gt; max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE)</div><div class='add'>+		out_name_size =</div><div class='add'>+			max_payload_size - MM_VARIABLE_GET_NEXT_HEADER_SIZE;</div><div class='add'>+</div><div class='add'>+	payload_size = MM_VARIABLE_GET_NEXT_HEADER_SIZE + out_name_size;</div><div class='add'>+	var_getnext = setup_mm_hdr(&amp;comm_buf, payload_size,</div><div class='add'>+				   SMM_VARIABLE_FUNCTION_GET_NEXT_VARIABLE_NAME,</div><div class='add'>+				   &amp;ret);</div><div class='add'>+	if (!var_getnext)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	/* Fill in contents */</div><div class='add'>+	memcpy(&amp;var_getnext-&gt;guid, guid, sizeof(var_getnext-&gt;guid));</div><div class='add'>+	var_getnext-&gt;name_size = out_name_size;</div><div class='add'>+	memcpy(var_getnext-&gt;name, name, in_name_size);</div><div class='add'>+	memset((u8 *)var_getnext-&gt;name + in_name_size, 0x0,</div><div class='add'>+	       out_name_size - in_name_size);</div><div class='add'>+</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	if (ret == EFI_SUCCESS || ret == EFI_BUFFER_TOO_SMALL) {</div><div class='add'>+		/* Update with reported data size for trimmed case */</div><div class='add'>+		*name_size = var_getnext-&gt;name_size;</div><div class='add'>+	}</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	memcpy(guid, &amp;var_getnext-&gt;guid, sizeof(*guid));</div><div class='add'>+	memcpy(name, var_getnext-&gt;name, var_getnext-&gt;name_size);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t tee_set_variable(efi_char16_t *name, efi_guid_t *vendor,</div><div class='add'>+				     u32 attributes, unsigned long data_size,</div><div class='add'>+				     void *data)</div><div class='add'>+{</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+	struct var_check_property var_property;</div><div class='add'>+	struct smm_variable_access *var_acc;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	size_t name_size;</div><div class='add'>+	u8 *comm_buf = NULL;</div><div class='add'>+</div><div class='add'>+	if (!name || name[0] == 0 || !vendor)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	if (data_size &gt; 0 &amp;&amp; !data)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	/* Check payload size */</div><div class='add'>+	name_size = (ucs2_strnlen(name, EFI_VAR_NAME_LEN) + 1) * sizeof(u16);</div><div class='add'>+	payload_size = MM_VARIABLE_ACCESS_HEADER_SIZE + name_size + data_size;</div><div class='add'>+	if (payload_size &gt; max_payload_size)</div><div class='add'>+		return EFI_INVALID_PARAMETER;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Allocate the buffer early, before switching to RW (if needed)</div><div class='add'>+	 * so we won't need to account for any failures in reading/setting</div><div class='add'>+	 * the properties, if the allocation fails</div><div class='add'>+	 */</div><div class='add'>+	var_acc = setup_mm_hdr(&amp;comm_buf, payload_size,</div><div class='add'>+			       SMM_VARIABLE_FUNCTION_SET_VARIABLE, &amp;ret);</div><div class='add'>+	if (!var_acc)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The API has the ability to override RO flags. If no RO check was</div><div class='add'>+	 * requested switch the variable to RW for the duration of this call</div><div class='add'>+	 */</div><div class='add'>+	ret = get_property_int(name, name_size, vendor, &amp;var_property);</div><div class='add'>+	if (ret != EFI_SUCCESS) {</div><div class='add'>+		dev_err(pvt_data.dev, "Getting variable property failed\n");</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (var_property.property &amp; VAR_CHECK_VARIABLE_PROPERTY_READ_ONLY) {</div><div class='add'>+		ret = EFI_WRITE_PROTECTED;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Fill in contents */</div><div class='add'>+	memcpy(&amp;var_acc-&gt;guid, vendor, sizeof(var_acc-&gt;guid));</div><div class='add'>+	var_acc-&gt;data_size = data_size;</div><div class='add'>+	var_acc-&gt;name_size = name_size;</div><div class='add'>+	var_acc-&gt;attr = attributes;</div><div class='add'>+	memcpy(var_acc-&gt;name, name, name_size);</div><div class='add'>+	memcpy((u8 *)var_acc-&gt;name + name_size, data, data_size);</div><div class='add'>+</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	dev_dbg(pvt_data.dev, "Set Variable %s %d %lx\n", __FILE__, __LINE__, ret);</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t tee_set_variable_nonblocking(efi_char16_t *name,</div><div class='add'>+						 efi_guid_t *vendor,</div><div class='add'>+						 u32 attributes,</div><div class='add'>+						 unsigned long data_size,</div><div class='add'>+						 void *data)</div><div class='add'>+{</div><div class='add'>+	return EFI_UNSUPPORTED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static efi_status_t tee_query_variable_info(u32 attributes,</div><div class='add'>+					    u64 *max_variable_storage_size,</div><div class='add'>+					    u64 *remain_variable_storage_size,</div><div class='add'>+					    u64 *max_variable_size)</div><div class='add'>+{</div><div class='add'>+	struct smm_variable_query_info *mm_query_info;</div><div class='add'>+	size_t payload_size;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+	u8 *comm_buf;</div><div class='add'>+</div><div class='add'>+	payload_size = sizeof(*mm_query_info);</div><div class='add'>+	mm_query_info = setup_mm_hdr(&amp;comm_buf, payload_size,</div><div class='add'>+				SMM_VARIABLE_FUNCTION_QUERY_VARIABLE_INFO,</div><div class='add'>+				&amp;ret);</div><div class='add'>+	if (!mm_query_info)</div><div class='add'>+		return EFI_OUT_OF_RESOURCES;</div><div class='add'>+</div><div class='add'>+	mm_query_info-&gt;attr = attributes;</div><div class='add'>+	ret = mm_communicate(comm_buf, payload_size);</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		goto out;</div><div class='add'>+	*max_variable_storage_size = mm_query_info-&gt;max_variable_storage;</div><div class='add'>+	*remain_variable_storage_size =</div><div class='add'>+		mm_query_info-&gt;remaining_variable_storage;</div><div class='add'>+	*max_variable_size = mm_query_info-&gt;max_variable_size;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(comm_buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tee_stmm_efi_close_context(void *data)</div><div class='add'>+{</div><div class='add'>+	tee_client_close_context(pvt_data.ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tee_stmm_efi_close_session(void *data)</div><div class='add'>+{</div><div class='add'>+	tee_client_close_session(pvt_data.ctx, pvt_data.session);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tee_stmm_restore_efivars_generic_ops(void)</div><div class='add'>+{</div><div class='add'>+	efivars_unregister(&amp;tee_efivars);</div><div class='add'>+	efivars_generic_ops_register();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tee_stmm_efi_probe(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct tee_ioctl_open_session_arg sess_arg;</div><div class='add'>+	efi_status_t ret;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	pvt_data.ctx = tee_client_open_context(NULL, tee_ctx_match, NULL, NULL);</div><div class='add'>+	if (IS_ERR(pvt_data.ctx))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	rc = devm_add_action_or_reset(dev, tee_stmm_efi_close_context, NULL);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	/* Open session with StMM PTA */</div><div class='add'>+	memset(&amp;sess_arg, 0, sizeof(sess_arg));</div><div class='add'>+	export_uuid(sess_arg.uuid, &amp;tee_stmm_efi_id_table[0].uuid);</div><div class='add'>+	rc = tee_client_open_session(pvt_data.ctx, &amp;sess_arg, NULL);</div><div class='add'>+	if ((rc &lt; 0) || (sess_arg.ret != 0)) {</div><div class='add'>+		dev_err(dev, "tee_client_open_session failed, err: %x\n",</div><div class='add'>+			sess_arg.ret);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	pvt_data.session = sess_arg.session;</div><div class='add'>+	pvt_data.dev = dev;</div><div class='add'>+	rc = devm_add_action_or_reset(dev, tee_stmm_efi_close_session, NULL);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	ret = get_max_payload(&amp;max_payload_size);</div><div class='add'>+	if (ret != EFI_SUCCESS)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	max_buffer_size = MM_COMMUNICATE_HEADER_SIZE +</div><div class='add'>+			  MM_VARIABLE_COMMUNICATE_SIZE +</div><div class='add'>+			  max_payload_size;</div><div class='add'>+</div><div class='add'>+	tee_efivar_ops.get_variable		= tee_get_variable;</div><div class='add'>+	tee_efivar_ops.get_next_variable	= tee_get_next_variable;</div><div class='add'>+	tee_efivar_ops.set_variable		= tee_set_variable;</div><div class='add'>+	tee_efivar_ops.set_variable_nonblocking	= tee_set_variable_nonblocking;</div><div class='add'>+	tee_efivar_ops.query_variable_store	= efi_query_variable_store;</div><div class='add'>+	tee_efivar_ops.query_variable_info	= tee_query_variable_info;</div><div class='add'>+</div><div class='add'>+	efivars_generic_ops_unregister();</div><div class='add'>+	pr_info("Using TEE-based EFI runtime variable services\n");</div><div class='add'>+	efivars_register(&amp;tee_efivars, &amp;tee_efivar_ops);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tee_stmm_efi_remove(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	tee_stmm_restore_efivars_generic_ops();</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+MODULE_DEVICE_TABLE(tee, tee_stmm_efi_id_table);</div><div class='add'>+</div><div class='add'>+static struct tee_client_driver tee_stmm_efi_driver = {</div><div class='add'>+	.id_table	= tee_stmm_efi_id_table,</div><div class='add'>+	.driver		= {</div><div class='add'>+		.name		= "tee-stmm-efi",</div><div class='add'>+		.bus		= &amp;tee_bus_type,</div><div class='add'>+		.probe		= tee_stmm_efi_probe,</div><div class='add'>+		.remove		= tee_stmm_efi_remove,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init tee_stmm_efi_mod_init(void)</div><div class='add'>+{</div><div class='add'>+	return driver_register(&amp;tee_stmm_efi_driver.driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit tee_stmm_efi_mod_exit(void)</div><div class='add'>+{</div><div class='add'>+	driver_unregister(&amp;tee_stmm_efi_driver.driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+module_init(tee_stmm_efi_mod_init);</div><div class='add'>+module_exit(tee_stmm_efi_mod_exit);</div><div class='add'>+</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;");</div><div class='add'>+MODULE_AUTHOR("Masahisa Kojima &lt;masahisa.kojima@linaro.org&gt;");</div><div class='add'>+MODULE_DESCRIPTION("TEE based EFI runtime variable service driver");</div><div class='head'>diff --git a/drivers/firmware/efi/unaccepted_memory.c b/drivers/firmware/efi/unaccepted_memory.c<br/>index 3f2f7bf6e335..5b439d04079c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/unaccepted_memory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/unaccepted_memory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/unaccepted_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/unaccepted_memory.c</a></div><div class='hunk'>@@ -101,7 +101,7 @@ retry:</div><div class='ctx'> 	 * overlap on physical address level.</div><div class='ctx'> 	 */</div><div class='ctx'> 	list_for_each_entry(entry, &amp;accepting_list, list) {</div><div class='del'>-		if (entry-&gt;end &lt; range.start)</div><div class='add'>+		if (entry-&gt;end &lt;= range.start)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (entry-&gt;start &gt;= range.end)</div><div class='ctx'> 			continue;</div><div class='head'>diff --git a/drivers/firmware/efi/vars.c b/drivers/firmware/efi/vars.c<br/>index e9dc7116daf1..f654e6f6af87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/efi/vars.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/efi/vars.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/efi/vars.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/efi/vars.c</a></div><div class='hunk'>@@ -63,6 +63,7 @@ int efivars_register(struct efivars *efivars,</div><div class='ctx'> 		     const struct efivar_operations *ops)</div><div class='ctx'> {</div><div class='ctx'> 	int rv;</div><div class='add'>+	int event;</div><div class='ctx'> </div><div class='ctx'> 	if (down_interruptible(&amp;efivars_lock))</div><div class='ctx'> 		return -EINTR;</div><div class='hunk'>@@ -77,6 +78,13 @@ int efivars_register(struct efivars *efivars,</div><div class='ctx'> </div><div class='ctx'> 	__efivars = efivars;</div><div class='ctx'> </div><div class='add'>+	if (efivar_supports_writes())</div><div class='add'>+		event = EFIVAR_OPS_RDWR;</div><div class='add'>+	else</div><div class='add'>+		event = EFIVAR_OPS_RDONLY;</div><div class='add'>+</div><div class='add'>+	blocking_notifier_call_chain(&amp;efivar_ops_nh, event, NULL);</div><div class='add'>+</div><div class='ctx'> 	pr_info("Registered efivars operations\n");</div><div class='ctx'> 	rv = 0;</div><div class='ctx'> out:</div><div class='head'>diff --git a/drivers/firmware/google/coreboot_table.c b/drivers/firmware/google/coreboot_table.c<br/>index 33ae94745aef..2a4469bf1b81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/google/coreboot_table.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/google/coreboot_table.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/google/coreboot_table.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/google/coreboot_table.c</a></div><div class='hunk'>@@ -176,10 +176,9 @@ static int __cb_dev_unregister(struct device *dev, void *dummy)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int coreboot_table_remove(struct platform_device *pdev)</div><div class='add'>+static void coreboot_table_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	bus_for_each_dev(&amp;coreboot_bus_type, NULL, NULL, __cb_dev_unregister);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_ACPI</div><div class='hunk'>@@ -201,7 +200,7 @@ MODULE_DEVICE_TABLE(of, coreboot_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver coreboot_table_driver = {</div><div class='ctx'> 	.probe = coreboot_table_probe,</div><div class='del'>-	.remove = coreboot_table_remove,</div><div class='add'>+	.remove_new = coreboot_table_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "coreboot_table",</div><div class='ctx'> 		.acpi_match_table = ACPI_PTR(cros_coreboot_acpi_match),</div><div class='head'>diff --git a/drivers/firmware/google/framebuffer-coreboot.c b/drivers/firmware/google/framebuffer-coreboot.c<br/>index c323a818805c..5c84bbebfef8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/google/framebuffer-coreboot.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/google/framebuffer-coreboot.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/google/framebuffer-coreboot.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/google/framebuffer-coreboot.c</a></div><div class='hunk'>@@ -36,6 +36,9 @@ static int framebuffer_probe(struct coreboot_device *dev)</div><div class='ctx'> 		.format = NULL,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='add'>+	if (!fb-&gt;physical_address)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(formats); ++i) {</div><div class='ctx'> 		if (fb-&gt;bits_per_pixel     == formats[i].bits_per_pixel &amp;&amp;</div><div class='ctx'> 		    fb-&gt;red_mask_pos       == formats[i].red.offset &amp;&amp;</div><div class='head'>diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c<br/>index a48a58e0c61f..01c8ef14eaec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/imx/imx-dsp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/imx/imx-dsp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/imx/imx-dsp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/imx/imx-dsp.c</a></div><div class='hunk'>@@ -160,7 +160,7 @@ static int imx_dsp_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx_dsp_remove(struct platform_device *pdev)</div><div class='add'>+static void imx_dsp_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx_dsp_chan *dsp_chan;</div><div class='ctx'> 	struct imx_dsp_ipc *dsp_ipc;</div><div class='hunk'>@@ -173,8 +173,6 @@ static int imx_dsp_remove(struct platform_device *pdev)</div><div class='ctx'> 		mbox_free_channel(dsp_chan-&gt;ch);</div><div class='ctx'> 		kfree(dsp_chan-&gt;name);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver imx_dsp_driver = {</div><div class='hunk'>@@ -182,7 +180,7 @@ static struct platform_driver imx_dsp_driver = {</div><div class='ctx'> 		.name = "imx-dsp",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = imx_dsp_probe,</div><div class='del'>-	.remove = imx_dsp_remove,</div><div class='add'>+	.remove_new = imx_dsp_remove,</div><div class='ctx'> };</div><div class='ctx'> builtin_platform_driver(imx_dsp_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c<br/>index ed60f1103053..5d7f62fe1d5f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/meson/meson_sm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/meson/meson_sm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/meson/meson_sm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/meson/meson_sm.c</a></div><div class='hunk'>@@ -274,14 +274,11 @@ static ssize_t serial_show(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR_RO(serial);</div><div class='ctx'> </div><div class='del'>-static struct attribute *meson_sm_sysfs_attributes[] = {</div><div class='add'>+static struct attribute *meson_sm_sysfs_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_serial.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-static const struct attribute_group meson_sm_sysfs_attr_group = {</div><div class='del'>-	.attrs = meson_sm_sysfs_attributes,</div><div class='del'>-};</div><div class='add'>+ATTRIBUTE_GROUPS(meson_sm_sysfs);</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id meson_sm_ids[] = {</div><div class='ctx'> 	{ .compatible = "amlogic,meson-gxbb-sm", .data = &amp;gxbb_chip },</div><div class='hunk'>@@ -313,7 +310,7 @@ static int __init meson_sm_probe(struct platform_device *pdev)</div><div class='ctx'> 		fw-&gt;sm_shmem_out_base = meson_sm_map_shmem(chip-&gt;cmd_shmem_out_base,</div><div class='ctx'> 							   chip-&gt;shmem_size);</div><div class='ctx'> 		if (WARN_ON(!fw-&gt;sm_shmem_out_base))</div><div class='del'>-			goto out_in_base;</div><div class='add'>+			goto unmap_in_base;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	fw-&gt;chip = chip;</div><div class='hunk'>@@ -321,16 +318,15 @@ static int __init meson_sm_probe(struct platform_device *pdev)</div><div class='ctx'> 	platform_set_drvdata(pdev, fw);</div><div class='ctx'> </div><div class='ctx'> 	if (devm_of_platform_populate(dev))</div><div class='del'>-		goto out_in_base;</div><div class='del'>-</div><div class='del'>-	if (sysfs_create_group(&amp;pdev-&gt;dev.kobj, &amp;meson_sm_sysfs_attr_group))</div><div class='del'>-		goto out_in_base;</div><div class='add'>+		goto unmap_out_base;</div><div class='ctx'> </div><div class='ctx'> 	pr_info("secure-monitor enabled\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-out_in_base:</div><div class='add'>+unmap_out_base:</div><div class='add'>+	iounmap(fw-&gt;sm_shmem_out_base);</div><div class='add'>+unmap_in_base:</div><div class='ctx'> 	iounmap(fw-&gt;sm_shmem_in_base);</div><div class='ctx'> out:</div><div class='ctx'> 	return -EINVAL;</div><div class='hunk'>@@ -340,6 +336,7 @@ static struct platform_driver meson_sm_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "meson-sm",</div><div class='ctx'> 		.of_match_table = of_match_ptr(meson_sm_ids),</div><div class='add'>+		.dev_groups = meson_sm_sysfs_groups,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver_probe(meson_sm_driver, meson_sm_probe);</div><div class='head'>diff --git a/drivers/firmware/microchip/Kconfig b/drivers/firmware/microchip/Kconfig<br/>new file mode 100644<br/>index 000000000000..434b923e08c2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/microchip/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+config POLARFIRE_SOC_AUTO_UPDATE</div><div class='add'>+	tristate "Microchip PolarFire SoC AUTO UPDATE"</div><div class='add'>+	depends on POLARFIRE_SOC_SYS_CTRL</div><div class='add'>+	select FW_LOADER</div><div class='add'>+	select FW_UPLOAD</div><div class='add'>+	help</div><div class='add'>+	  Support for reprogramming PolarFire SoC from within Linux, using the</div><div class='add'>+	  Auto Upgrade feature of the system controller.</div><div class='add'>+</div><div class='add'>+	  If built as a module, it will be called mpfs-auto-update.</div><div class='head'>diff --git a/drivers/firmware/microchip/Makefile b/drivers/firmware/microchip/Makefile<br/>new file mode 100644<br/>index 000000000000..38796fd82893<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/microchip/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/Makefile</a></div><div class='hunk'>@@ -0,0 +1,3 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_POLARFIRE_SOC_AUTO_UPDATE) += mpfs-auto-update.o</div><div class='head'>diff --git a/drivers/firmware/microchip/mpfs-auto-update.c b/drivers/firmware/microchip/mpfs-auto-update.c<br/>new file mode 100644<br/>index 000000000000..81f5f62e34fc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/microchip/mpfs-auto-update.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/microchip/mpfs-auto-update.c</a></div><div class='hunk'>@@ -0,0 +1,494 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Microchip Polarfire SoC "Auto Update" FPGA reprogramming.</div><div class='add'>+ *</div><div class='add'>+ * Documentation of this functionality is available in the "PolarFire® FPGA and</div><div class='add'>+ * PolarFire SoC FPGA Programming" User Guide.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Author: Conor Dooley &lt;conor.dooley@microchip.com&gt;</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/math.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mtd/mtd.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;soc/microchip/mpfs.h&gt;</div><div class='add'>+</div><div class='add'>+#define AUTO_UPDATE_DEFAULT_MBOX_OFFSET		0u</div><div class='add'>+#define AUTO_UPDATE_DEFAULT_RESP_OFFSET		0u</div><div class='add'>+</div><div class='add'>+#define AUTO_UPDATE_FEATURE_CMD_OPCODE		0x05u</div><div class='add'>+#define AUTO_UPDATE_FEATURE_CMD_DATA_SIZE	0u</div><div class='add'>+#define AUTO_UPDATE_FEATURE_RESP_SIZE		33u</div><div class='add'>+#define AUTO_UPDATE_FEATURE_CMD_DATA		NULL</div><div class='add'>+#define AUTO_UPDATE_FEATURE_ENABLED		BIT(5)</div><div class='add'>+</div><div class='add'>+#define AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE	0x22u</div><div class='add'>+#define AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE	0u</div><div class='add'>+#define AUTO_UPDATE_AUTHENTICATE_RESP_SIZE	1u</div><div class='add'>+#define AUTO_UPDATE_AUTHENTICATE_CMD_DATA	NULL</div><div class='add'>+</div><div class='add'>+#define AUTO_UPDATE_PROGRAM_CMD_OPCODE		0x46u</div><div class='add'>+#define AUTO_UPDATE_PROGRAM_CMD_DATA_SIZE	0u</div><div class='add'>+#define AUTO_UPDATE_PROGRAM_RESP_SIZE		1u</div><div class='add'>+#define AUTO_UPDATE_PROGRAM_CMD_DATA		NULL</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SPI Flash layout example:</div><div class='add'>+ * |------------------------------| 0x0000000</div><div class='add'>+ * | 1 KiB                        |</div><div class='add'>+ * | SPI "directories"            |</div><div class='add'>+ * |------------------------------| 0x0000400</div><div class='add'>+ * | 1 MiB                        |</div><div class='add'>+ * | Reserved area                |</div><div class='add'>+ * | Used for bitstream info      |</div><div class='add'>+ * |------------------------------| 0x0100400</div><div class='add'>+ * | 20 MiB                       |</div><div class='add'>+ * | Golden Image                 |</div><div class='add'>+ * |------------------------------| 0x1500400</div><div class='add'>+ * | 20 MiB                       |</div><div class='add'>+ * | Auto Upgrade Image           |</div><div class='add'>+ * |------------------------------| 0x2900400</div><div class='add'>+ * | 20 MiB                       |</div><div class='add'>+ * | Reserved for multi-image IAP |</div><div class='add'>+ * | Unused for Auto Upgrade      |</div><div class='add'>+ * |------------------------------| 0x3D00400</div><div class='add'>+ * | ? B                          |</div><div class='add'>+ * | Unused                       |</div><div class='add'>+ * |------------------------------| 0x?</div><div class='add'>+ */</div><div class='add'>+#define AUTO_UPDATE_DIRECTORY_BASE	0u</div><div class='add'>+#define AUTO_UPDATE_DIRECTORY_WIDTH	4u</div><div class='add'>+#define AUTO_UPDATE_GOLDEN_INDEX	0u</div><div class='add'>+#define AUTO_UPDATE_UPGRADE_INDEX	1u</div><div class='add'>+#define AUTO_UPDATE_BLANK_INDEX		2u</div><div class='add'>+#define AUTO_UPDATE_GOLDEN_DIRECTORY	(AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_GOLDEN_INDEX)</div><div class='add'>+#define AUTO_UPDATE_UPGRADE_DIRECTORY	(AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_UPGRADE_INDEX)</div><div class='add'>+#define AUTO_UPDATE_BLANK_DIRECTORY	(AUTO_UPDATE_DIRECTORY_WIDTH * AUTO_UPDATE_BLANK_INDEX)</div><div class='add'>+#define AUTO_UPDATE_DIRECTORY_SIZE	SZ_1K</div><div class='add'>+#define AUTO_UPDATE_RESERVED_SIZE	SZ_1M</div><div class='add'>+#define AUTO_UPDATE_BITSTREAM_BASE	(AUTO_UPDATE_DIRECTORY_SIZE + AUTO_UPDATE_RESERVED_SIZE)</div><div class='add'>+</div><div class='add'>+#define AUTO_UPDATE_TIMEOUT_MS		60000</div><div class='add'>+</div><div class='add'>+struct mpfs_auto_update_priv {</div><div class='add'>+	struct mpfs_sys_controller *sys_controller;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct mtd_info *flash;</div><div class='add'>+	struct fw_upload *fw_uploader;</div><div class='add'>+	struct completion programming_complete;</div><div class='add'>+	size_t size_per_bitstream;</div><div class='add'>+	bool cancel_request;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err mpfs_auto_update_prepare(struct fw_upload *fw_uploader, const u8 *data,</div><div class='add'>+						   u32 size)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+	size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Verifying the Golden Image is idealistic. It will be evaluated</div><div class='add'>+	 * against the currently programmed image and thus may fail - due to</div><div class='add'>+	 * either rollback protection (if its an older version than that in use)</div><div class='add'>+	 * or if the version is the same as that of the in-use image.</div><div class='add'>+	 * Extracting the information as to why a failure occurred is not</div><div class='add'>+	 * currently possible due to limitations of the system controller</div><div class='add'>+	 * driver. If those are fixed, verification of the Golden Image should</div><div class='add'>+	 * be added here.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	priv-&gt;flash = mpfs_sys_controller_get_flash(priv-&gt;sys_controller);</div><div class='add'>+	if (!priv-&gt;flash)</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+</div><div class='add'>+	erase_size = round_up(erase_size, (u64)priv-&gt;flash-&gt;erasesize);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We need to calculate if we have enough space in the flash for the</div><div class='add'>+	 * new image.</div><div class='add'>+	 * First, chop off the first 1 KiB as it's reserved for the directory.</div><div class='add'>+	 * The 1 MiB reserved for design info needs to be ignored also.</div><div class='add'>+	 * All that remains is carved into 3 &amp; rounded down to the erasesize.</div><div class='add'>+	 * If this is smaller than the image size, we abort.</div><div class='add'>+	 * There's also no need to consume more than 20 MiB per image.</div><div class='add'>+	 */</div><div class='add'>+	priv-&gt;size_per_bitstream = priv-&gt;flash-&gt;size - SZ_1K - SZ_1M;</div><div class='add'>+	priv-&gt;size_per_bitstream = round_down(priv-&gt;size_per_bitstream / 3, erase_size);</div><div class='add'>+	if (priv-&gt;size_per_bitstream &gt; 20 * SZ_1M)</div><div class='add'>+		priv-&gt;size_per_bitstream = 20 * SZ_1M;</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;size_per_bitstream &lt; size) {</div><div class='add'>+		dev_err(priv-&gt;dev,</div><div class='add'>+			"flash device has insufficient capacity to store this bitstream\n");</div><div class='add'>+		return FW_UPLOAD_ERR_INVALID_SIZE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	priv-&gt;cancel_request = false;</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mpfs_auto_update_cancel(struct fw_upload *fw_uploader)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+</div><div class='add'>+	priv-&gt;cancel_request = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err mpfs_auto_update_poll_complete(struct fw_upload *fw_uploader)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * There is no meaningful way to get the status of the programming while</div><div class='add'>+	 * it is in progress, so attempting anything other than waiting for it</div><div class='add'>+	 * to complete would be misplaced.</div><div class='add'>+	 */</div><div class='add'>+	ret = wait_for_completion_timeout(&amp;priv-&gt;programming_complete,</div><div class='add'>+					  msecs_to_jiffies(AUTO_UPDATE_TIMEOUT_MS));</div><div class='add'>+	if (ret)</div><div class='add'>+		return FW_UPLOAD_ERR_TIMEOUT;</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mpfs_auto_update_verify_image(struct fw_upload *fw_uploader)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+	struct mpfs_mss_response *response;</div><div class='add'>+	struct mpfs_mss_msg *message;</div><div class='add'>+	u32 *response_msg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	response_msg = devm_kzalloc(priv-&gt;dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg),</div><div class='add'>+				    GFP_KERNEL);</div><div class='add'>+	if (!response_msg)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	response = devm_kzalloc(priv-&gt;dev, sizeof(struct mpfs_mss_response), GFP_KERNEL);</div><div class='add'>+	if (!response) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto free_response_msg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	message = devm_kzalloc(priv-&gt;dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL);</div><div class='add'>+	if (!message) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto free_response;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The system controller can verify that an image in the flash is valid.</div><div class='add'>+	 * Rather than duplicate the check in this driver, call the relevant</div><div class='add'>+	 * service from the system controller instead.</div><div class='add'>+	 * This service has no command data and no response data. It overloads</div><div class='add'>+	 * mbox_offset with the image index in the flash's SPI directory where</div><div class='add'>+	 * the bitstream is located.</div><div class='add'>+	 */</div><div class='add'>+	response-&gt;resp_msg = response_msg;</div><div class='add'>+	response-&gt;resp_size = AUTO_UPDATE_AUTHENTICATE_RESP_SIZE;</div><div class='add'>+	message-&gt;cmd_opcode = AUTO_UPDATE_AUTHENTICATE_CMD_OPCODE;</div><div class='add'>+	message-&gt;cmd_data_size = AUTO_UPDATE_AUTHENTICATE_CMD_DATA_SIZE;</div><div class='add'>+	message-&gt;response = response;</div><div class='add'>+	message-&gt;cmd_data = AUTO_UPDATE_AUTHENTICATE_CMD_DATA;</div><div class='add'>+	message-&gt;mbox_offset = AUTO_UPDATE_UPGRADE_INDEX;</div><div class='add'>+	message-&gt;resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET;</div><div class='add'>+</div><div class='add'>+	dev_info(priv-&gt;dev, "Running verification of Upgrade Image\n");</div><div class='add'>+	ret = mpfs_blocking_transaction(priv-&gt;sys_controller, message);</div><div class='add'>+	if (ret | response-&gt;resp_status) {</div><div class='add'>+		dev_warn(priv-&gt;dev, "Verification of Upgrade Image failed!\n");</div><div class='add'>+		ret = ret ? ret : -EBADMSG;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(priv-&gt;dev, "Verification of Upgrade Image passed!\n");</div><div class='add'>+</div><div class='add'>+	devm_kfree(priv-&gt;dev, message);</div><div class='add'>+free_response:</div><div class='add'>+	devm_kfree(priv-&gt;dev, response);</div><div class='add'>+free_response_msg:</div><div class='add'>+	devm_kfree(priv-&gt;dev, response_msg);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mpfs_auto_update_set_image_address(struct mpfs_auto_update_priv *priv, char *buffer,</div><div class='add'>+					      u32 image_address, loff_t directory_address)</div><div class='add'>+{</div><div class='add'>+	struct erase_info erase;</div><div class='add'>+	size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE;</div><div class='add'>+	size_t bytes_written = 0, bytes_read = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	erase_size = round_up(erase_size, (u64)priv-&gt;flash-&gt;erasesize);</div><div class='add'>+</div><div class='add'>+	erase.addr = AUTO_UPDATE_DIRECTORY_BASE;</div><div class='add'>+	erase.len = erase_size;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We need to write the "SPI DIRECTORY" to the first 1 KiB, telling</div><div class='add'>+	 * the system controller where to find the actual bitstream. Since</div><div class='add'>+	 * this is spi-nor, we have to read the first eraseblock, erase that</div><div class='add'>+	 * portion of the flash, modify the data and then write it back.</div><div class='add'>+	 * There's no need to do this though if things are already the way they</div><div class='add'>+	 * should be, so check and save the write in that case.</div><div class='add'>+	 */</div><div class='add'>+	ret = mtd_read(priv-&gt;flash, AUTO_UPDATE_DIRECTORY_BASE, erase_size, &amp;bytes_read,</div><div class='add'>+		       (u_char *)buffer);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (bytes_read != erase_size)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	if ((*(u32 *)(buffer + AUTO_UPDATE_UPGRADE_DIRECTORY) == image_address) &amp;&amp;</div><div class='add'>+	    !(*(u32 *)(buffer + AUTO_UPDATE_BLANK_DIRECTORY)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = mtd_erase(priv-&gt;flash, &amp;erase);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Populate the image address and then zero out the next directory so</div><div class='add'>+	 * that the system controller doesn't complain if in "Single Image"</div><div class='add'>+	 * mode.</div><div class='add'>+	 */</div><div class='add'>+	memcpy(buffer + AUTO_UPDATE_UPGRADE_DIRECTORY, &amp;image_address,</div><div class='add'>+	       AUTO_UPDATE_DIRECTORY_WIDTH);</div><div class='add'>+	memset(buffer + AUTO_UPDATE_BLANK_DIRECTORY, 0x0, AUTO_UPDATE_DIRECTORY_WIDTH);</div><div class='add'>+</div><div class='add'>+	dev_info(priv-&gt;dev, "Writing the image address (%x) to the flash directory (%llx)\n",</div><div class='add'>+		 image_address, directory_address);</div><div class='add'>+</div><div class='add'>+	ret = mtd_write(priv-&gt;flash, 0x0, erase_size, &amp;bytes_written, (u_char *)buffer);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (bytes_written != erase_size)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mpfs_auto_update_write_bitstream(struct fw_upload *fw_uploader, const u8 *data,</div><div class='add'>+					    u32 offset, u32 size, u32 *written)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+	struct erase_info erase;</div><div class='add'>+	char *buffer;</div><div class='add'>+	loff_t directory_address = AUTO_UPDATE_UPGRADE_DIRECTORY;</div><div class='add'>+	size_t erase_size = AUTO_UPDATE_DIRECTORY_SIZE;</div><div class='add'>+	size_t bytes_written = 0;</div><div class='add'>+	u32 image_address;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	erase_size = round_up(erase_size, (u64)priv-&gt;flash-&gt;erasesize);</div><div class='add'>+</div><div class='add'>+	image_address = AUTO_UPDATE_BITSTREAM_BASE +</div><div class='add'>+		AUTO_UPDATE_UPGRADE_INDEX * priv-&gt;size_per_bitstream;</div><div class='add'>+</div><div class='add'>+	buffer = devm_kzalloc(priv-&gt;dev, erase_size, GFP_KERNEL);</div><div class='add'>+	if (!buffer)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = mpfs_auto_update_set_image_address(priv, buffer, image_address, directory_address);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(priv-&gt;dev, "failed to set image address in the SPI directory: %d\n", ret);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Now the .spi image itself can be written to the flash. Preservation</div><div class='add'>+	 * of contents here is not important here, unlike the spi "directory"</div><div class='add'>+	 * which must be RMWed.</div><div class='add'>+	 */</div><div class='add'>+	erase.len = round_up(size, (size_t)priv-&gt;flash-&gt;erasesize);</div><div class='add'>+	erase.addr = image_address;</div><div class='add'>+</div><div class='add'>+	dev_info(priv-&gt;dev, "Erasing the flash at address (%x)\n", image_address);</div><div class='add'>+	ret = mtd_erase(priv-&gt;flash, &amp;erase);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * No parsing etc of the bitstream is required. The system controller</div><div class='add'>+	 * will do all of that itself - including verifying that the bitstream</div><div class='add'>+	 * is valid.</div><div class='add'>+	 */</div><div class='add'>+	dev_info(priv-&gt;dev, "Writing the image to the flash at address (%x)\n", image_address);</div><div class='add'>+	ret = mtd_write(priv-&gt;flash, (loff_t)image_address, size, &amp;bytes_written, data);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (bytes_written != size) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*written = bytes_written;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	devm_kfree(priv-&gt;dev, buffer);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err mpfs_auto_update_write(struct fw_upload *fw_uploader, const u8 *data,</div><div class='add'>+						 u32 offset, u32 size, u32 *written)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = fw_uploader-&gt;dd_handle;</div><div class='add'>+	enum fw_upload_err err = FW_UPLOAD_ERR_NONE;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	reinit_completion(&amp;priv-&gt;programming_complete);</div><div class='add'>+</div><div class='add'>+	ret = mpfs_auto_update_write_bitstream(fw_uploader, data, offset, size, written);</div><div class='add'>+	if (ret) {</div><div class='add'>+		err = FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;cancel_request) {</div><div class='add'>+		err = FW_UPLOAD_ERR_CANCELED;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mpfs_auto_update_verify_image(fw_uploader);</div><div class='add'>+	if (ret)</div><div class='add'>+		err = FW_UPLOAD_ERR_FW_INVALID;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	complete(&amp;priv-&gt;programming_complete);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct fw_upload_ops mpfs_auto_update_ops = {</div><div class='add'>+	.prepare = mpfs_auto_update_prepare,</div><div class='add'>+	.write = mpfs_auto_update_write,</div><div class='add'>+	.poll_complete = mpfs_auto_update_poll_complete,</div><div class='add'>+	.cancel = mpfs_auto_update_cancel,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mpfs_auto_update_available(struct mpfs_auto_update_priv *priv)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_mss_response *response;</div><div class='add'>+	struct mpfs_mss_msg *message;</div><div class='add'>+	u32 *response_msg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	response_msg = devm_kzalloc(priv-&gt;dev, AUTO_UPDATE_FEATURE_RESP_SIZE * sizeof(response_msg),</div><div class='add'>+				    GFP_KERNEL);</div><div class='add'>+	if (!response_msg)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	response = devm_kzalloc(priv-&gt;dev, sizeof(struct mpfs_mss_response), GFP_KERNEL);</div><div class='add'>+	if (!response)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	message = devm_kzalloc(priv-&gt;dev, sizeof(struct mpfs_mss_msg), GFP_KERNEL);</div><div class='add'>+	if (!message)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * To verify that Auto Update is possible, the "Query Security Service</div><div class='add'>+	 * Request" is performed.</div><div class='add'>+	 * This service has no command data &amp; does not overload mbox_offset.</div><div class='add'>+	 */</div><div class='add'>+	response-&gt;resp_msg = response_msg;</div><div class='add'>+	response-&gt;resp_size = AUTO_UPDATE_FEATURE_RESP_SIZE;</div><div class='add'>+	message-&gt;cmd_opcode = AUTO_UPDATE_FEATURE_CMD_OPCODE;</div><div class='add'>+	message-&gt;cmd_data_size = AUTO_UPDATE_FEATURE_CMD_DATA_SIZE;</div><div class='add'>+	message-&gt;response = response;</div><div class='add'>+	message-&gt;cmd_data = AUTO_UPDATE_FEATURE_CMD_DATA;</div><div class='add'>+	message-&gt;mbox_offset = AUTO_UPDATE_DEFAULT_MBOX_OFFSET;</div><div class='add'>+	message-&gt;resp_offset = AUTO_UPDATE_DEFAULT_RESP_OFFSET;</div><div class='add'>+</div><div class='add'>+	ret = mpfs_blocking_transaction(priv-&gt;sys_controller, message);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Currently, the system controller's firmware does not generate any</div><div class='add'>+	 * interrupts for failed services, so mpfs_blocking_transaction() should</div><div class='add'>+	 * time out &amp; therefore return an error.</div><div class='add'>+	 * Hitting this check is highly unlikely at present, but if the system</div><div class='add'>+	 * controller's behaviour changes so that it does generate interrupts</div><div class='add'>+	 * for failed services, it will be required.</div><div class='add'>+	 */</div><div class='add'>+	if (response-&gt;resp_status)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Bit 5 of byte 1 is "UL_Auto Update" &amp; if it is set, Auto Update is</div><div class='add'>+	 * not possible.</div><div class='add'>+	 */</div><div class='add'>+	if (response_msg[1] &amp; AUTO_UPDATE_FEATURE_ENABLED)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mpfs_auto_update_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct mpfs_auto_update_priv *priv;</div><div class='add'>+	struct fw_upload *fw_uploader;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;sys_controller = mpfs_sys_controller_get(dev);</div><div class='add'>+	if (IS_ERR(priv-&gt;sys_controller))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(priv-&gt;sys_controller),</div><div class='add'>+				     "Could not register as a sub device of the system controller\n");</div><div class='add'>+</div><div class='add'>+	priv-&gt;dev = dev;</div><div class='add'>+	platform_set_drvdata(pdev, priv);</div><div class='add'>+</div><div class='add'>+	ret = mpfs_auto_update_available(priv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+				     "The current bitstream does not support auto-update\n");</div><div class='add'>+</div><div class='add'>+	init_completion(&amp;priv-&gt;programming_complete);</div><div class='add'>+</div><div class='add'>+	fw_uploader = firmware_upload_register(THIS_MODULE, dev, "mpfs-auto-update",</div><div class='add'>+					       &amp;mpfs_auto_update_ops, priv);</div><div class='add'>+	if (IS_ERR(fw_uploader))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(fw_uploader),</div><div class='add'>+				     "Failed to register the bitstream uploader\n");</div><div class='add'>+</div><div class='add'>+	priv-&gt;fw_uploader = fw_uploader;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mpfs_auto_update_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct mpfs_auto_update_priv *priv = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	firmware_upload_unregister(priv-&gt;fw_uploader);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver mpfs_auto_update_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "mpfs-auto-update",</div><div class='add'>+	},</div><div class='add'>+	.probe = mpfs_auto_update_probe,</div><div class='add'>+	.remove_new = mpfs_auto_update_remove,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(mpfs_auto_update_driver);</div><div class='add'>+</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Conor Dooley &lt;conor.dooley@microchip.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");</div><div class='head'>diff --git a/drivers/firmware/mtk-adsp-ipc.c b/drivers/firmware/mtk-adsp-ipc.c<br/>index 85e94ddc7204..a762302978de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/mtk-adsp-ipc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/mtk-adsp-ipc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/mtk-adsp-ipc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/mtk-adsp-ipc.c</a></div><div class='hunk'>@@ -116,7 +116,7 @@ static int mtk_adsp_ipc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mtk_adsp_ipc_remove(struct platform_device *pdev)</div><div class='add'>+static void mtk_adsp_ipc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_adsp_ipc *adsp_ipc = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct mtk_adsp_chan *adsp_chan;</div><div class='hunk'>@@ -126,8 +126,6 @@ static int mtk_adsp_ipc_remove(struct platform_device *pdev)</div><div class='ctx'> 		adsp_chan = &amp;adsp_ipc-&gt;chans[i];</div><div class='ctx'> 		mbox_free_channel(adsp_chan-&gt;ch);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mtk_adsp_ipc_driver = {</div><div class='hunk'>@@ -135,7 +133,7 @@ static struct platform_driver mtk_adsp_ipc_driver = {</div><div class='ctx'> 		.name = "mtk-adsp-ipc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = mtk_adsp_ipc_probe,</div><div class='del'>-	.remove = mtk_adsp_ipc_remove,</div><div class='add'>+	.remove_new = mtk_adsp_ipc_remove,</div><div class='ctx'> };</div><div class='ctx'> builtin_platform_driver(mtk_adsp_ipc_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c b/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c<br/>index a33acdaf7b78..32188f098ef3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/qcom/qcom_qseecom_uefisecapp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/qcom/qcom_qseecom_uefisecapp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/qcom/qcom_qseecom_uefisecapp.c</a></div><div class='hunk'>@@ -325,8 +325,10 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e</div><div class='ctx'> 	req_data-&gt;length = req_size;</div><div class='ctx'> </div><div class='ctx'> 	status = ucs2_strscpy(((void *)req_data) + req_data-&gt;name_offset, name, name_length);</div><div class='del'>-	if (status &lt; 0)</div><div class='del'>-		return EFI_INVALID_PARAMETER;</div><div class='add'>+	if (status &lt; 0) {</div><div class='add'>+		efi_status = EFI_INVALID_PARAMETER;</div><div class='add'>+		goto out_free;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(((void *)req_data) + req_data-&gt;guid_offset, guid, req_data-&gt;guid_size);</div><div class='ctx'> </div><div class='hunk'>@@ -471,8 +473,10 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e</div><div class='ctx'> 	req_data-&gt;length = req_size;</div><div class='ctx'> </div><div class='ctx'> 	status = ucs2_strscpy(((void *)req_data) + req_data-&gt;name_offset, name, name_length);</div><div class='del'>-	if (status &lt; 0)</div><div class='del'>-		return EFI_INVALID_PARAMETER;</div><div class='add'>+	if (status &lt; 0) {</div><div class='add'>+		efi_status = EFI_INVALID_PARAMETER;</div><div class='add'>+		goto out_free;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(((void *)req_data) + req_data-&gt;guid_offset, guid, req_data-&gt;guid_size);</div><div class='ctx'> </div><div class='hunk'>@@ -563,8 +567,10 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,</div><div class='ctx'> 	memcpy(((void *)req_data) + req_data-&gt;guid_offset, guid, req_data-&gt;guid_size);</div><div class='ctx'> 	status = ucs2_strscpy(((void *)req_data) + req_data-&gt;name_offset, name,</div><div class='ctx'> 			      *name_size / sizeof(*name));</div><div class='del'>-	if (status &lt; 0)</div><div class='del'>-		return EFI_INVALID_PARAMETER;</div><div class='add'>+	if (status &lt; 0) {</div><div class='add'>+		efi_status = EFI_INVALID_PARAMETER;</div><div class='add'>+		goto out_free;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	status = qcom_qseecom_app_send(qcuefi-&gt;client, req_data, req_size, rsp_data, rsp_size);</div><div class='ctx'> 	if (status) {</div><div class='hunk'>@@ -635,7 +641,7 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,</div><div class='ctx'> 		 * have already been validated above, causing this function to</div><div class='ctx'> 		 * bail with EFI_BUFFER_TOO_SMALL.</div><div class='ctx'> 		 */</div><div class='del'>-		return EFI_DEVICE_ERROR;</div><div class='add'>+		efi_status = EFI_DEVICE_ERROR;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out_free:</div><div class='head'>diff --git a/drivers/firmware/qemu_fw_cfg.c b/drivers/firmware/qemu_fw_cfg.c<br/>index 1448f61173b3..03da9a4354f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/qemu_fw_cfg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/qemu_fw_cfg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/qemu_fw_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/qemu_fw_cfg.c</a></div><div class='hunk'>@@ -731,7 +731,7 @@ err_sel:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fw_cfg_sysfs_remove(struct platform_device *pdev)</div><div class='add'>+static void fw_cfg_sysfs_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pr_debug("fw_cfg: unloading.\n");</div><div class='ctx'> 	fw_cfg_sysfs_cache_cleanup();</div><div class='hunk'>@@ -739,7 +739,6 @@ static int fw_cfg_sysfs_remove(struct platform_device *pdev)</div><div class='ctx'> 	fw_cfg_io_cleanup();</div><div class='ctx'> 	fw_cfg_kset_unregister_recursive(fw_cfg_fname_kset);</div><div class='ctx'> 	fw_cfg_kobj_cleanup(fw_cfg_sel_ko);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id fw_cfg_sysfs_mmio_match[] = {</div><div class='hunk'>@@ -758,7 +757,7 @@ MODULE_DEVICE_TABLE(acpi, fw_cfg_sysfs_acpi_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver fw_cfg_sysfs_driver = {</div><div class='ctx'> 	.probe = fw_cfg_sysfs_probe,</div><div class='del'>-	.remove = fw_cfg_sysfs_remove,</div><div class='add'>+	.remove_new = fw_cfg_sysfs_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "fw_cfg",</div><div class='ctx'> 		.of_match_table = fw_cfg_sysfs_mmio_match,</div><div class='head'>diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c<br/>index 4cd290a60fba..322aada20f74 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/raspberrypi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/raspberrypi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/raspberrypi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/raspberrypi.c</a></div><div class='hunk'>@@ -317,7 +317,7 @@ static void rpi_firmware_shutdown(struct platform_device *pdev)</div><div class='ctx'> 	rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT, NULL, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rpi_firmware_remove(struct platform_device *pdev)</div><div class='add'>+static void rpi_firmware_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct rpi_firmware *fw = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -327,8 +327,6 @@ static int rpi_firmware_remove(struct platform_device *pdev)</div><div class='ctx'> 	rpi_clk = NULL;</div><div class='ctx'> </div><div class='ctx'> 	rpi_firmware_put(fw);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id rpi_firmware_of_match[] = {</div><div class='hunk'>@@ -406,7 +404,7 @@ static struct platform_driver rpi_firmware_driver = {</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= rpi_firmware_probe,</div><div class='ctx'> 	.shutdown	= rpi_firmware_shutdown,</div><div class='del'>-	.remove		= rpi_firmware_remove,</div><div class='add'>+	.remove_new	= rpi_firmware_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(rpi_firmware_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c<br/>index 4f7a7abada48..e20cee9c2d32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/stratix10-rsu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/stratix10-rsu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/stratix10-rsu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/stratix10-rsu.c</a></div><div class='hunk'>@@ -793,17 +793,16 @@ static int stratix10_rsu_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stratix10_rsu_remove(struct platform_device *pdev)</div><div class='add'>+static void stratix10_rsu_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct stratix10_rsu_priv *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	stratix10_svc_free_channel(priv-&gt;chan);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver stratix10_rsu_driver = {</div><div class='ctx'> 	.probe = stratix10_rsu_probe,</div><div class='del'>-	.remove = stratix10_rsu_remove,</div><div class='add'>+	.remove_new = stratix10_rsu_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "stratix10-rsu",</div><div class='ctx'> 		.dev_groups = rsu_groups,</div><div class='head'>diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c<br/>index c693da60e9a9..528f37417aea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/stratix10-svc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/stratix10-svc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/stratix10-svc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/stratix10-svc.c</a></div><div class='hunk'>@@ -1251,7 +1251,7 @@ err_destroy_pool:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stratix10_svc_drv_remove(struct platform_device *pdev)</div><div class='add'>+static void stratix10_svc_drv_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct stratix10_svc *svc = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct stratix10_svc_controller *ctrl = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -1267,13 +1267,11 @@ static int stratix10_svc_drv_remove(struct platform_device *pdev)</div><div class='ctx'> 	if (ctrl-&gt;genpool)</div><div class='ctx'> 		gen_pool_destroy(ctrl-&gt;genpool);</div><div class='ctx'> 	list_del(&amp;ctrl-&gt;node);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver stratix10_svc_driver = {</div><div class='ctx'> 	.probe = stratix10_svc_drv_probe,</div><div class='del'>-	.remove = stratix10_svc_drv_remove,</div><div class='add'>+	.remove_new = stratix10_svc_drv_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "stratix10-svc",</div><div class='ctx'> 		.of_match_table = stratix10_svc_drv_match,</div><div class='head'>diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c<br/>index 7041befc756a..8b9a2556de16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/ti_sci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/ti_sci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/ti_sci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/ti_sci.c</a></div><div class='hunk'>@@ -164,7 +164,7 @@ static int ti_sci_debugfs_create(struct platform_device *pdev,</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct resource *res;</div><div class='del'>-	char debug_name[50] = "ti_sci_debug@";</div><div class='add'>+	char debug_name[50];</div><div class='ctx'> </div><div class='ctx'> 	/* Debug region is optional */</div><div class='ctx'> 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,</div><div class='hunk'>@@ -181,10 +181,10 @@ static int ti_sci_debugfs_create(struct platform_device *pdev,</div><div class='ctx'> 	/* Setup NULL termination */</div><div class='ctx'> 	info-&gt;debug_buffer[info-&gt;debug_region_size] = 0;</div><div class='ctx'> </div><div class='del'>-	info-&gt;d = debugfs_create_file(strncat(debug_name, dev_name(dev),</div><div class='del'>-					      sizeof(debug_name) -</div><div class='del'>-					      sizeof("ti_sci_debug@")),</div><div class='del'>-				      0444, NULL, info, &amp;ti_sci_debug_fops);</div><div class='add'>+	snprintf(debug_name, sizeof(debug_name), "ti_sci_debug@%s",</div><div class='add'>+		 dev_name(dev));</div><div class='add'>+	info-&gt;d = debugfs_create_file(debug_name, 0444, NULL, info,</div><div class='add'>+				      &amp;ti_sci_debug_fops);</div><div class='ctx'> 	if (IS_ERR(info-&gt;d))</div><div class='ctx'> 		return PTR_ERR(info-&gt;d);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/firmware/turris-mox-rwtm.c b/drivers/firmware/turris-mox-rwtm.c<br/>index 2de0fb139ce1..31d962cdd6eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/turris-mox-rwtm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/turris-mox-rwtm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/turris-mox-rwtm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/turris-mox-rwtm.c</a></div><div class='hunk'>@@ -554,7 +554,7 @@ put_kobj:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int turris_mox_rwtm_remove(struct platform_device *pdev)</div><div class='add'>+static void turris_mox_rwtm_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mox_rwtm *rwtm = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -562,8 +562,6 @@ static int turris_mox_rwtm_remove(struct platform_device *pdev)</div><div class='ctx'> 	sysfs_remove_files(rwtm_to_kobj(rwtm), mox_rwtm_attrs);</div><div class='ctx'> 	kobject_put(rwtm_to_kobj(rwtm));</div><div class='ctx'> 	mbox_free_channel(rwtm-&gt;mbox);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id turris_mox_rwtm_match[] = {</div><div class='hunk'>@@ -576,7 +574,7 @@ MODULE_DEVICE_TABLE(of, turris_mox_rwtm_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver turris_mox_rwtm_driver = {</div><div class='ctx'> 	.probe	= turris_mox_rwtm_probe,</div><div class='del'>-	.remove	= turris_mox_rwtm_remove,</div><div class='add'>+	.remove_new = turris_mox_rwtm_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name		= DRIVER_NAME,</div><div class='ctx'> 		.of_match_table	= turris_mox_rwtm_match,</div><div class='head'>diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c<br/>index b0d22d4455d9..79789f0563f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/firmware/xilinx/zynqmp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/firmware/xilinx/zynqmp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/firmware/xilinx/zynqmp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/firmware/xilinx/zynqmp.c</a></div><div class='hunk'>@@ -92,6 +92,8 @@ static int zynqmp_pm_ret_code(u32 ret_status)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	case XST_PM_NO_FEATURE:</div><div class='ctx'> 		return -ENOTSUPP;</div><div class='add'>+	case XST_PM_INVALID_VERSION:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	case XST_PM_NO_ACCESS:</div><div class='ctx'> 		return -EACCES;</div><div class='ctx'> 	case XST_PM_ABORT_SUSPEND:</div><div class='hunk'>@@ -101,13 +103,13 @@ static int zynqmp_pm_ret_code(u32 ret_status)</div><div class='ctx'> 	case XST_PM_INTERNAL:</div><div class='ctx'> 	case XST_PM_CONFLICT:</div><div class='ctx'> 	case XST_PM_INVALID_NODE:</div><div class='add'>+	case XST_PM_INVALID_CRC:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static noinline int do_fw_call_fail(u64 arg0, u64 arg1, u64 arg2,</div><div class='del'>-				    u32 *ret_payload)</div><div class='add'>+static noinline int do_fw_call_fail(u32 *ret_payload, u32 num_args, ...)</div><div class='ctx'> {</div><div class='ctx'> 	return -ENODEV;</div><div class='ctx'> }</div><div class='hunk'>@@ -116,25 +118,35 @@ static noinline int do_fw_call_fail(u64 arg0, u64 arg1, u64 arg2,</div><div class='ctx'>  * PM function call wrapper</div><div class='ctx'>  * Invoke do_fw_call_smc or do_fw_call_hvc, depending on the configuration</div><div class='ctx'>  */</div><div class='del'>-static int (*do_fw_call)(u64, u64, u64, u32 *ret_payload) = do_fw_call_fail;</div><div class='add'>+static int (*do_fw_call)(u32 *ret_payload, u32, ...) = do_fw_call_fail;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * do_fw_call_smc() - Call system-level platform management layer (SMC)</div><div class='del'>- * @arg0:		Argument 0 to SMC call</div><div class='del'>- * @arg1:		Argument 1 to SMC call</div><div class='del'>- * @arg2:		Argument 2 to SMC call</div><div class='add'>+ * @num_args:		Number of variable arguments should be &lt;= 8</div><div class='ctx'>  * @ret_payload:	Returned value array</div><div class='ctx'>  *</div><div class='ctx'>  * Invoke platform management function via SMC call (no hypervisor present).</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Returns status, either success or error+reason</div><div class='ctx'>  */</div><div class='del'>-static noinline int do_fw_call_smc(u64 arg0, u64 arg1, u64 arg2,</div><div class='del'>-				   u32 *ret_payload)</div><div class='add'>+static noinline int do_fw_call_smc(u32 *ret_payload, u32 num_args, ...)</div><div class='ctx'> {</div><div class='ctx'> 	struct arm_smccc_res res;</div><div class='add'>+	u64 args[8] = {0};</div><div class='add'>+	va_list arg_list;</div><div class='add'>+	u8 i;</div><div class='ctx'> </div><div class='del'>-	arm_smccc_smc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &amp;res);</div><div class='add'>+	if (num_args &gt; 8)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	va_start(arg_list, num_args);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_args; i++)</div><div class='add'>+		args[i] = va_arg(arg_list, u64);</div><div class='add'>+</div><div class='add'>+	va_end(arg_list);</div><div class='add'>+</div><div class='add'>+	arm_smccc_smc(args[0], args[1], args[2], args[3], args[4], args[5], args[6], args[7], &amp;res);</div><div class='ctx'> </div><div class='ctx'> 	if (ret_payload) {</div><div class='ctx'> 		ret_payload[0] = lower_32_bits(res.a0);</div><div class='hunk'>@@ -148,9 +160,7 @@ static noinline int do_fw_call_smc(u64 arg0, u64 arg1, u64 arg2,</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * do_fw_call_hvc() - Call system-level platform management layer (HVC)</div><div class='del'>- * @arg0:		Argument 0 to HVC call</div><div class='del'>- * @arg1:		Argument 1 to HVC call</div><div class='del'>- * @arg2:		Argument 2 to HVC call</div><div class='add'>+ * @num_args:		Number of variable arguments should be &lt;= 8</div><div class='ctx'>  * @ret_payload:	Returned value array</div><div class='ctx'>  *</div><div class='ctx'>  * Invoke platform management function via HVC</div><div class='hunk'>@@ -159,12 +169,24 @@ static noinline int do_fw_call_smc(u64 arg0, u64 arg1, u64 arg2,</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Returns status, either success or error+reason</div><div class='ctx'>  */</div><div class='del'>-static noinline int do_fw_call_hvc(u64 arg0, u64 arg1, u64 arg2,</div><div class='del'>-				   u32 *ret_payload)</div><div class='add'>+static noinline int do_fw_call_hvc(u32 *ret_payload, u32 num_args, ...)</div><div class='ctx'> {</div><div class='ctx'> 	struct arm_smccc_res res;</div><div class='add'>+	u64 args[8] = {0};</div><div class='add'>+	va_list arg_list;</div><div class='add'>+	u8 i;</div><div class='add'>+</div><div class='add'>+	if (num_args &gt; 8)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	va_start(arg_list, num_args);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_args; i++)</div><div class='add'>+		args[i] = va_arg(arg_list, u64);</div><div class='add'>+</div><div class='add'>+	va_end(arg_list);</div><div class='ctx'> </div><div class='del'>-	arm_smccc_hvc(arg0, arg1, arg2, 0, 0, 0, 0, 0, &amp;res);</div><div class='add'>+	arm_smccc_hvc(args[0], args[1], args[2], args[3], args[4], args[5], args[6], args[7], &amp;res);</div><div class='ctx'> </div><div class='ctx'> 	if (ret_payload) {</div><div class='ctx'> 		ret_payload[0] = lower_32_bits(res.a0);</div><div class='hunk'>@@ -180,11 +202,31 @@ static int __do_feature_check_call(const u32 api_id, u32 *ret_payload)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u64 smc_arg[2];</div><div class='add'>+	u32 module_id;</div><div class='add'>+	u32 feature_check_api_id;</div><div class='ctx'> </div><div class='del'>-	smc_arg[0] = PM_SIP_SVC | PM_FEATURE_CHECK;</div><div class='del'>-	smc_arg[1] = api_id;</div><div class='add'>+	module_id = FIELD_GET(MODULE_ID_MASK, api_id);</div><div class='ctx'> </div><div class='del'>-	ret = do_fw_call(smc_arg[0], smc_arg[1], 0, ret_payload);</div><div class='add'>+	/*</div><div class='add'>+	 * Feature check of APIs belonging to PM, XSEM, and TF-A are handled by calling</div><div class='add'>+	 * PM_FEATURE_CHECK API. For other modules, call PM_API_FEATURES API.</div><div class='add'>+	 */</div><div class='add'>+	if (module_id == PM_MODULE_ID || module_id == XSEM_MODULE_ID || module_id == TF_A_MODULE_ID)</div><div class='add'>+		feature_check_api_id = PM_FEATURE_CHECK;</div><div class='add'>+	else</div><div class='add'>+		feature_check_api_id = PM_API_FEATURES;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Feature check of TF-A APIs is done in the TF-A layer and it expects for</div><div class='add'>+	 * MODULE_ID_MASK bits of SMC's arg[0] to be the same as PM_MODULE_ID.</div><div class='add'>+	 */</div><div class='add'>+	if (module_id == TF_A_MODULE_ID)</div><div class='add'>+		module_id = PM_MODULE_ID;</div><div class='add'>+</div><div class='add'>+	smc_arg[0] = PM_SIP_SVC | FIELD_PREP(MODULE_ID_MASK, module_id) | feature_check_api_id;</div><div class='add'>+	smc_arg[1] = (api_id &amp; API_ID_MASK);</div><div class='add'>+</div><div class='add'>+	ret = do_fw_call(ret_payload, 2, smc_arg[0], smc_arg[1]);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		ret = -EOPNOTSUPP;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -295,11 +337,8 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_is_function_supported);</div><div class='ctx'>  * zynqmp_pm_invoke_fn() - Invoke the system-level platform management layer</div><div class='ctx'>  *			   caller function depending on the configuration</div><div class='ctx'>  * @pm_api_id:		Requested PM-API call</div><div class='del'>- * @arg0:		Argument 0 to requested PM-API call</div><div class='del'>- * @arg1:		Argument 1 to requested PM-API call</div><div class='del'>- * @arg2:		Argument 2 to requested PM-API call</div><div class='del'>- * @arg3:		Argument 3 to requested PM-API call</div><div class='ctx'>  * @ret_payload:	Returned value array</div><div class='add'>+ * @num_args:		Number of arguments to requested PM-API call</div><div class='ctx'>  *</div><div class='ctx'>  * Invoke platform management function for SMC or HVC call, depending on</div><div class='ctx'>  * configuration.</div><div class='hunk'>@@ -316,26 +355,38 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_is_function_supported);</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Returns status, either success or error+reason</div><div class='ctx'>  */</div><div class='del'>-int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,</div><div class='del'>-			u32 arg2, u32 arg3, u32 *ret_payload)</div><div class='add'>+int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Added SIP service call Function Identifier</div><div class='ctx'> 	 * Make sure to stay in x0 register</div><div class='ctx'> 	 */</div><div class='del'>-	u64 smc_arg[4];</div><div class='del'>-	int ret;</div><div class='add'>+	u64 smc_arg[8];</div><div class='add'>+	int ret, i;</div><div class='add'>+	va_list arg_list;</div><div class='add'>+	u32 args[14] = {0};</div><div class='add'>+</div><div class='add'>+	if (num_args &gt; 14)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	va_start(arg_list, num_args);</div><div class='ctx'> </div><div class='ctx'> 	/* Check if feature is supported or not */</div><div class='ctx'> 	ret = zynqmp_pm_feature(pm_api_id);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; num_args; i++)</div><div class='add'>+		args[i] = va_arg(arg_list, u32);</div><div class='add'>+</div><div class='add'>+	va_end(arg_list);</div><div class='add'>+</div><div class='ctx'> 	smc_arg[0] = PM_SIP_SVC | pm_api_id;</div><div class='del'>-	smc_arg[1] = ((u64)arg1 &lt;&lt; 32) | arg0;</div><div class='del'>-	smc_arg[2] = ((u64)arg3 &lt;&lt; 32) | arg2;</div><div class='add'>+	for (i = 0; i &lt; 7; i++)</div><div class='add'>+		smc_arg[i + 1] = ((u64)args[(i * 2) + 1] &lt;&lt; 32) | args[i * 2];</div><div class='ctx'> </div><div class='del'>-	return do_fw_call(smc_arg[0], smc_arg[1], smc_arg[2], ret_payload);</div><div class='add'>+	return do_fw_call(ret_payload, 8, smc_arg[0], smc_arg[1], smc_arg[2], smc_arg[3],</div><div class='add'>+			  smc_arg[4], smc_arg[5], smc_arg[6], smc_arg[7]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 pm_api_version;</div><div class='hunk'>@@ -347,14 +398,12 @@ int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(TF_A_PM_REGISTER_SGI, sgi_num, reset, 0, 0,</div><div class='del'>-				  NULL);</div><div class='del'>-	if (!ret)</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(TF_A_PM_REGISTER_SGI, NULL, 2, sgi_num, reset);</div><div class='add'>+	if (ret != -EOPNOTSUPP &amp;&amp; !ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* try old implementation as fallback strategy if above fails */</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_REGISTER_SGI, sgi_num,</div><div class='del'>-				   reset, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, IOCTL_REGISTER_SGI, sgi_num, reset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -376,7 +425,7 @@ int zynqmp_pm_get_api_version(u32 *version)</div><div class='ctx'> 		*version = pm_api_version;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_GET_API_VERSION, 0, 0, 0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_GET_API_VERSION, ret_payload, 0);</div><div class='ctx'> 	*version = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -399,7 +448,7 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)</div><div class='ctx'> 	if (!idcode || !version)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, ret_payload, 0);</div><div class='ctx'> 	*idcode = ret_payload[1];</div><div class='ctx'> 	*version = ret_payload[2];</div><div class='ctx'> </div><div class='hunk'>@@ -414,7 +463,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid);</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Returns status, either success or error+reason</div><div class='ctx'>  */</div><div class='del'>-static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)</div><div class='add'>+int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)</div><div class='ctx'> {</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	u32 idcode;</div><div class='hunk'>@@ -427,7 +476,7 @@ static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, ret_payload, 0);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -439,6 +488,7 @@ static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(zynqmp_pm_get_family_info);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version</div><div class='hunk'>@@ -459,8 +509,7 @@ static int zynqmp_pm_get_trustzone_version(u32 *version)</div><div class='ctx'> 		*version = pm_tz_version;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_GET_TRUSTZONE_VERSION, 0, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_GET_TRUSTZONE_VERSION, ret_payload, 0);</div><div class='ctx'> 	*version = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -507,8 +556,8 @@ int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_QUERY_DATA, qdata.qid, qdata.arg1,</div><div class='del'>-				  qdata.arg2, qdata.arg3, out);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_QUERY_DATA, out, 4, qdata.qid, qdata.arg1, qdata.arg2,</div><div class='add'>+				  qdata.arg3);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * For clock name query, all bytes in SMC response are clock name</div><div class='hunk'>@@ -530,7 +579,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_query_data);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_clock_enable(u32 clock_id)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, NULL, 1, clock_id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_clock_enable);</div><div class='ctx'> </div><div class='hunk'>@@ -545,7 +594,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_enable);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_clock_disable(u32 clock_id)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, NULL, 1, clock_id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_clock_disable);</div><div class='ctx'> </div><div class='hunk'>@@ -564,8 +613,7 @@ int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETSTATE, clock_id, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETSTATE, ret_payload, 1, clock_id);</div><div class='ctx'> 	*state = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -584,8 +632,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider,</div><div class='del'>-				   0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, NULL, 2, clock_id, divider);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider);</div><div class='ctx'> </div><div class='hunk'>@@ -604,8 +651,7 @@ int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, clock_id, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, ret_payload, 1, clock_id);</div><div class='ctx'> 	*divider = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -613,47 +659,6 @@ int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getdivider);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * zynqmp_pm_clock_setrate() - Set the clock rate for given id</div><div class='del'>- * @clock_id:	ID of the clock</div><div class='del'>- * @rate:	rate value in hz</div><div class='del'>- *</div><div class='del'>- * This function is used by master to set rate for any clock.</div><div class='del'>- *</div><div class='del'>- * Return: Returns status, either success or error+reason</div><div class='del'>- */</div><div class='del'>-int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)</div><div class='del'>-{</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_CLOCK_SETRATE, clock_id,</div><div class='del'>-				   lower_32_bits(rate),</div><div class='del'>-				   upper_32_bits(rate),</div><div class='del'>-				   0, NULL);</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setrate);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * zynqmp_pm_clock_getrate() - Get the clock rate for given id</div><div class='del'>- * @clock_id:	ID of the clock</div><div class='del'>- * @rate:	rate value in hz</div><div class='del'>- *</div><div class='del'>- * This function is used by master to get rate</div><div class='del'>- * for any clock.</div><div class='del'>- *</div><div class='del'>- * Return: Returns status, either success or error+reason</div><div class='del'>- */</div><div class='del'>-int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)</div><div class='del'>-{</div><div class='del'>-	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETRATE, clock_id, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='del'>-	*rate = ((u64)ret_payload[2] &lt;&lt; 32) | ret_payload[1];</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getrate);</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * zynqmp_pm_clock_setparent() - Set the clock parent for given id</div><div class='ctx'>  * @clock_id:	ID of the clock</div><div class='ctx'>  * @parent_id:	parent id</div><div class='hunk'>@@ -664,8 +669,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getrate);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, clock_id,</div><div class='del'>-				   parent_id, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, NULL, 2, clock_id, parent_id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setparent);</div><div class='ctx'> </div><div class='hunk'>@@ -684,8 +688,7 @@ int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETPARENT, clock_id, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETPARENT, ret_payload, 1, clock_id);</div><div class='ctx'> 	*parent_id = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -704,8 +707,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getparent);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_MODE,</div><div class='del'>-				   clk_id, mode, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -721,8 +723,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_mode);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_MODE,</div><div class='del'>-				   clk_id, 0, mode);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, mode, 3, 0, IOCTL_GET_PLL_FRAC_MODE, clk_id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -739,8 +740,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_mode);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_DATA,</div><div class='del'>-				   clk_id, data, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_SET_PLL_FRAC_DATA, clk_id, data);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_data);</div><div class='ctx'> </div><div class='hunk'>@@ -756,8 +756,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_data);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_DATA,</div><div class='del'>-				   clk_id, 0, data);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, data, 3, 0, IOCTL_GET_PLL_FRAC_DATA, clk_id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data);</div><div class='ctx'> </div><div class='hunk'>@@ -778,9 +777,8 @@ int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)</div><div class='ctx'> 	u32 mask = (node_id == NODE_SD_0) ? GENMASK(15, 0) : GENMASK(31, 16);</div><div class='ctx'> </div><div class='ctx'> 	if (value) {</div><div class='del'>-		return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,</div><div class='del'>-					   IOCTL_SET_SD_TAPDELAY,</div><div class='del'>-					   type, value, NULL);</div><div class='add'>+		return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, node_id, IOCTL_SET_SD_TAPDELAY, type,</div><div class='add'>+					   value);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -798,7 +796,7 @@ int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)</div><div class='ctx'> 	 * Use PM_MMIO_READ/PM_MMIO_WRITE to re-implement the missing counter</div><div class='ctx'> 	 * part of IOCTL_SET_SD_TAPDELAY which clears SDx_ITAPDLYENA bits.</div><div class='ctx'> 	 */</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, reg, mask, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, NULL, 2, reg, mask);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay);</div><div class='ctx'> </div><div class='hunk'>@@ -814,8 +812,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SD_DLL_RESET,</div><div class='del'>-				   type, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, node_id, IOCTL_SD_DLL_RESET, type);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);</div><div class='ctx'> </div><div class='hunk'>@@ -831,8 +828,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, dev_id, IOCTL_OSPI_MUX_SELECT,</div><div class='del'>-				   select, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, dev_id, IOCTL_OSPI_MUX_SELECT, select);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);</div><div class='ctx'> </div><div class='hunk'>@@ -847,8 +843,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_ospi_mux_select);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_write_ggs(u32 index, u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_GGS,</div><div class='del'>-				   index, value, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_WRITE_GGS, index, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs);</div><div class='ctx'> </div><div class='hunk'>@@ -863,8 +858,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_read_ggs(u32 index, u32 *value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_GGS,</div><div class='del'>-				   index, 0, value);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, value, 3, 0, IOCTL_READ_GGS, index);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs);</div><div class='ctx'> </div><div class='hunk'>@@ -880,8 +874,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_write_pggs(u32 index, u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_PGGS, index, value,</div><div class='del'>-				   NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_WRITE_PGGS, index, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs);</div><div class='ctx'> </div><div class='hunk'>@@ -897,15 +890,13 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_read_pggs(u32 index, u32 *value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_PGGS, index, 0,</div><div class='del'>-				   value);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, value, 3, 0, IOCTL_READ_PGGS, index);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);</div><div class='ctx'> </div><div class='ctx'> int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,</div><div class='del'>-				   index, value, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_SET_TAPDELAY_BYPASS, index, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);</div><div class='ctx'> </div><div class='hunk'>@@ -920,8 +911,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_boot_health_status(u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_BOOT_HEALTH_STATUS,</div><div class='del'>-				   value, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, 0, IOCTL_SET_BOOT_HEALTH_STATUS, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -935,8 +925,7 @@ int zynqmp_pm_set_boot_health_status(u32 value)</div><div class='ctx'> int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,</div><div class='ctx'> 			   const enum zynqmp_pm_reset_action assert_flag)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_RESET_ASSERT, reset, assert_flag,</div><div class='del'>-				   0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_RESET_ASSERT, NULL, 2, reset, assert_flag);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_reset_assert);</div><div class='ctx'> </div><div class='hunk'>@@ -955,8 +944,7 @@ int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status)</div><div class='ctx'> 	if (!status)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_RESET_GET_STATUS, reset, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_RESET_GET_STATUS, ret_payload, 1, reset);</div><div class='ctx'> 	*status = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -981,9 +969,8 @@ int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags)</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),</div><div class='del'>-				  upper_32_bits(address), size, flags,</div><div class='del'>-				  ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_FPGA_LOAD, ret_payload, 4, lower_32_bits(address),</div><div class='add'>+				  upper_32_bits(address), size, flags);</div><div class='ctx'> 	if (ret_payload[0])</div><div class='ctx'> 		return -ret_payload[0];</div><div class='ctx'> </div><div class='hunk'>@@ -1008,7 +995,7 @@ int zynqmp_pm_fpga_get_status(u32 *value)</div><div class='ctx'> 	if (!value)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, ret_payload, 0);</div><div class='ctx'> 	*value = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1036,11 +1023,9 @@ int zynqmp_pm_fpga_get_config_status(u32 *value)</div><div class='ctx'> 	lower_addr = lower_32_bits((u64)&amp;buf);</div><div class='ctx'> 	upper_addr = upper_32_bits((u64)&amp;buf);</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,</div><div class='del'>-				  XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,</div><div class='del'>-				  lower_addr, upper_addr,</div><div class='del'>-				  XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,</div><div class='del'>-				  ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_FPGA_READ, ret_payload, 4,</div><div class='add'>+				  XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET, lower_addr, upper_addr,</div><div class='add'>+				  XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG);</div><div class='ctx'> </div><div class='ctx'> 	*value = ret_payload[1];</div><div class='ctx'> </div><div class='hunk'>@@ -1058,7 +1043,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_pinctrl_request(const u32 pin)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_PINCTRL_REQUEST, NULL, 1, pin);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_request);</div><div class='ctx'> </div><div class='hunk'>@@ -1072,36 +1057,11 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_request);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_pinctrl_release(const u32 pin)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_PINCTRL_RELEASE, pin, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_PINCTRL_RELEASE, NULL, 1, pin);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_release);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * zynqmp_pm_pinctrl_get_function - Read function id set for the given pin</div><div class='del'>- * @pin: Pin number</div><div class='del'>- * @id: Buffer to store function ID</div><div class='del'>- *</div><div class='del'>- * This function provides the function currently set for the given pin.</div><div class='del'>- *</div><div class='del'>- * Return: Returns status, either success or error+reason</div><div class='del'>- */</div><div class='del'>-int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)</div><div class='del'>-{</div><div class='del'>-	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (!id)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_PINCTRL_GET_FUNCTION, pin, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='del'>-	*id = ret_payload[1];</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_function);</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * zynqmp_pm_pinctrl_set_function - Set requested function for the pin</div><div class='ctx'>  * @pin: Pin number</div><div class='ctx'>  * @id: Function ID to set</div><div class='hunk'>@@ -1112,8 +1072,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_function);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_PINCTRL_SET_FUNCTION, pin, id,</div><div class='del'>-				   0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_PINCTRL_SET_FUNCTION, NULL, 2, pin, id);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_function);</div><div class='ctx'> </div><div class='hunk'>@@ -1136,8 +1095,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,</div><div class='ctx'> 	if (!value)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_GET, pin, param,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_GET, ret_payload, 2, pin, param);</div><div class='ctx'> 	*value = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1166,8 +1124,7 @@ int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,</div><div class='ctx'> 			return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin,</div><div class='del'>-				   param, value, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, NULL, 3, pin, param, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);</div><div class='ctx'> </div><div class='hunk'>@@ -1185,8 +1142,7 @@ unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)</div><div class='ctx'> 	unsigned int ret;</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, CRL_APB_BOOT_PIN_CTRL, 0,</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, ret_payload, 1, CRL_APB_BOOT_PIN_CTRL);</div><div class='ctx'> </div><div class='ctx'> 	*ps_mode = ret_payload[1];</div><div class='ctx'> </div><div class='hunk'>@@ -1205,8 +1161,8 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_read);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_bootmode_write(u32 ps_mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, CRL_APB_BOOT_PIN_CTRL,</div><div class='del'>-				   CRL_APB_BOOTPIN_CTRL_MASK, ps_mode, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, NULL, 3, CRL_APB_BOOT_PIN_CTRL,</div><div class='add'>+				   CRL_APB_BOOTPIN_CTRL_MASK, ps_mode);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write);</div><div class='ctx'> </div><div class='hunk'>@@ -1221,7 +1177,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_init_finalize(void)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_PM_INIT_FINALIZE, 0, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_PM_INIT_FINALIZE, NULL, 0);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_init_finalize);</div><div class='ctx'> </div><div class='hunk'>@@ -1235,7 +1191,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_init_finalize);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_suspend_mode(u32 mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_SET_SUSPEND_MODE, mode, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_SET_SUSPEND_MODE, NULL, 1, mode);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_suspend_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -1254,8 +1210,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_suspend_mode);</div><div class='ctx'> int zynqmp_pm_request_node(const u32 node, const u32 capabilities,</div><div class='ctx'> 			   const u32 qos, const enum zynqmp_pm_request_ack ack)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, node, capabilities,</div><div class='del'>-				   qos, ack, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, NULL, 4, node, capabilities, qos, ack);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_request_node);</div><div class='ctx'> </div><div class='hunk'>@@ -1271,7 +1226,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_request_node);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_release_node(const u32 node)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, NULL, 1, node);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_release_node);</div><div class='ctx'> </div><div class='hunk'>@@ -1290,8 +1245,7 @@ int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)</div><div class='ctx'> 	u32 ret_payload[PAYLOAD_ARG_CNT];</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_IOCTL, node_id,</div><div class='del'>-				  IOCTL_GET_RPU_OPER_MODE, 0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_IOCTL, ret_payload, 2, node_id, IOCTL_GET_RPU_OPER_MODE);</div><div class='ctx'> </div><div class='ctx'> 	/* only set rpu_mode if no error */</div><div class='ctx'> 	if (ret == XST_PM_SUCCESS)</div><div class='hunk'>@@ -1313,9 +1267,8 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_rpu_mode);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,</div><div class='del'>-				   IOCTL_SET_RPU_OPER_MODE, (u32)rpu_mode,</div><div class='del'>-				   0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, node_id, IOCTL_SET_RPU_OPER_MODE,</div><div class='add'>+				   (u32)rpu_mode);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -1331,9 +1284,8 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_rpu_mode);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, node_id,</div><div class='del'>-				   IOCTL_TCM_COMB_CONFIG, (u32)tcm_mode, 0,</div><div class='del'>-				   NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 3, node_id, IOCTL_TCM_COMB_CONFIG,</div><div class='add'>+				   (u32)tcm_mode);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config);</div><div class='ctx'> </div><div class='hunk'>@@ -1348,7 +1300,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_tcm_config);</div><div class='ctx'> int zynqmp_pm_force_pwrdwn(const u32 node,</div><div class='ctx'> 			   const enum zynqmp_pm_request_ack ack)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, node, ack, 0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, NULL, 2, node, ack);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_force_pwrdwn);</div><div class='ctx'> </div><div class='hunk'>@@ -1367,8 +1319,8 @@ int zynqmp_pm_request_wake(const u32 node,</div><div class='ctx'> 			   const enum zynqmp_pm_request_ack ack)</div><div class='ctx'> {</div><div class='ctx'> 	/* set_addr flag is encoded into 1st bit of address */</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr,</div><div class='del'>-				   address &gt;&gt; 32, ack, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, NULL, 4, node, address | set_addr,</div><div class='add'>+				   address &gt;&gt; 32, ack);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake);</div><div class='ctx'> </div><div class='hunk'>@@ -1388,15 +1340,14 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,</div><div class='ctx'> 			      const u32 qos,</div><div class='ctx'> 			      const enum zynqmp_pm_request_ack ack)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_SET_REQUIREMENT, node, capabilities,</div><div class='del'>-				   qos, ack, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_SET_REQUIREMENT, NULL, 4, node, capabilities, qos, ack);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * zynqmp_pm_load_pdi - Load and process PDI</div><div class='del'>- * @src:       Source device where PDI is located</div><div class='del'>- * @address:   PDI src address</div><div class='add'>+ * @src:	Source device where PDI is located</div><div class='add'>+ * @address:	PDI src address</div><div class='ctx'>  *</div><div class='ctx'>  * This function provides support to load PDI from linux</div><div class='ctx'>  *</div><div class='hunk'>@@ -1404,9 +1355,8 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_load_pdi(const u32 src, const u64 address)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,</div><div class='del'>-				   lower_32_bits(address),</div><div class='del'>-				   upper_32_bits(address), 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, NULL, 3, src, lower_32_bits(address),</div><div class='add'>+				   upper_32_bits(address));</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);</div><div class='ctx'> </div><div class='hunk'>@@ -1426,9 +1376,8 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)</div><div class='ctx'> 	if (!out)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),</div><div class='del'>-				  lower_32_bits(address),</div><div class='del'>-				  0, 0, ret_payload);</div><div class='add'>+	ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, ret_payload, 2, upper_32_bits(address),</div><div class='add'>+				  lower_32_bits(address));</div><div class='ctx'> 	*out = ret_payload[1];</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1456,8 +1405,7 @@ int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)</div><div class='ctx'> 	u32 lower_addr = lower_32_bits(address);</div><div class='ctx'> 	u32 upper_addr = upper_32_bits(address);</div><div class='ctx'> </div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,</div><div class='del'>-				   size, flags, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_SECURE_SHA, NULL, 4, upper_addr, lower_addr, size, flags);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);</div><div class='ctx'> </div><div class='hunk'>@@ -1479,8 +1427,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);</div><div class='ctx'> int zynqmp_pm_register_notifier(const u32 node, const u32 event,</div><div class='ctx'> 				const u32 wake, const u32 enable)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_REGISTER_NOTIFIER, node, event,</div><div class='del'>-				   wake, enable, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_REGISTER_NOTIFIER, NULL, 4, node, event, wake, enable);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_register_notifier);</div><div class='ctx'> </div><div class='hunk'>@@ -1493,8 +1440,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_register_notifier);</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_SYSTEM_SHUTDOWN, type, subtype,</div><div class='del'>-				   0, 0, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_SYSTEM_SHUTDOWN, NULL, 2, type, subtype);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1506,8 +1452,7 @@ int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_FEATURE_CONFIG,</div><div class='del'>-				   id, value, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, 0, IOCTL_SET_FEATURE_CONFIG, id, value);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1520,8 +1465,7 @@ int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value)</div><div class='ctx'> int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,</div><div class='ctx'> 				 u32 *payload)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_FEATURE_CONFIG,</div><div class='del'>-				   id, 0, payload);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, payload, 3, 0, IOCTL_GET_FEATURE_CONFIG, id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1534,8 +1478,7 @@ int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,</div><div class='ctx'>  */</div><div class='ctx'> int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_SET_SD_CONFIG,</div><div class='del'>-				   config, value, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, node, IOCTL_SET_SD_CONFIG, config, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_config);</div><div class='ctx'> </div><div class='hunk'>@@ -1550,8 +1493,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_config);</div><div class='ctx'> int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,</div><div class='ctx'> 			     u32 value)</div><div class='ctx'> {</div><div class='del'>-	return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_SET_GEM_CONFIG,</div><div class='del'>-				   config, value, NULL);</div><div class='add'>+	return zynqmp_pm_invoke_fn(PM_IOCTL, NULL, 4, node, IOCTL_SET_GEM_CONFIG, config, value);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(zynqmp_pm_set_gem_config);</div><div class='ctx'> </div><div class='hunk'>@@ -1916,7 +1858,6 @@ ATTRIBUTE_GROUPS(zynqmp_firmware);</div><div class='ctx'> static int zynqmp_firmware_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='del'>-	struct device_node *np;</div><div class='ctx'> 	struct zynqmp_devinfo *devinfo;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1924,22 +1865,9 @@ static int zynqmp_firmware_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	np = of_find_compatible_node(NULL, NULL, "xlnx,zynqmp");</div><div class='del'>-	if (!np) {</div><div class='del'>-		np = of_find_compatible_node(NULL, NULL, "xlnx,versal");</div><div class='del'>-		if (!np)</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='add'>+	ret = do_feature_check_call(PM_FEATURE_CHECK);</div><div class='add'>+	if (ret &gt;= 0 &amp;&amp; ((ret &amp; FIRMWARE_VERSION_MASK) &gt;= PM_API_VERSION_1))</div><div class='ctx'> 		feature_check_enabled = true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!feature_check_enabled) {</div><div class='del'>-		ret = do_feature_check_call(PM_FEATURE_CHECK);</div><div class='del'>-		if (ret &gt;= 0)</div><div class='del'>-			feature_check_enabled = true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	of_node_put(np);</div><div class='ctx'> </div><div class='ctx'> 	devinfo = devm_kzalloc(dev, sizeof(*devinfo), GFP_KERNEL);</div><div class='ctx'> 	if (!devinfo)</div><div class='hunk'>@@ -1992,19 +1920,17 @@ static int zynqmp_firmware_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	zynqmp_pm_api_debugfs_init();</div><div class='ctx'> </div><div class='del'>-	np = of_find_compatible_node(NULL, NULL, "xlnx,versal");</div><div class='del'>-	if (np) {</div><div class='add'>+	if (pm_family_code == VERSAL_FAMILY_CODE) {</div><div class='ctx'> 		em_dev = platform_device_register_data(&amp;pdev-&gt;dev, "xlnx_event_manager",</div><div class='ctx'> 						       -1, NULL, 0);</div><div class='ctx'> 		if (IS_ERR(em_dev))</div><div class='ctx'> 			dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(em_dev), "EM register fail with error\n");</div><div class='ctx'> 	}</div><div class='del'>-	of_node_put(np);</div><div class='ctx'> </div><div class='ctx'> 	return of_platform_populate(dev-&gt;of_node, NULL, NULL, dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int zynqmp_firmware_remove(struct platform_device *pdev)</div><div class='add'>+static void zynqmp_firmware_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pm_api_feature_data *feature_data;</div><div class='ctx'> 	struct hlist_node *tmp;</div><div class='hunk'>@@ -2019,8 +1945,6 @@ static int zynqmp_firmware_remove(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	platform_device_unregister(em_dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id zynqmp_firmware_of_match[] = {</div><div class='hunk'>@@ -2037,6 +1961,6 @@ static struct platform_driver zynqmp_firmware_driver = {</div><div class='ctx'> 		.dev_groups = zynqmp_firmware_groups,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = zynqmp_firmware_probe,</div><div class='del'>-	.remove = zynqmp_firmware_remove,</div><div class='add'>+	.remove_new = zynqmp_firmware_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(zynqmp_firmware_driver);</div><div class='head'>diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c<br/>index 1fa2ccc321ab..6b60ca004345 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/altera-fpga2sdram.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/altera-fpga2sdram.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/altera-fpga2sdram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-fpga2sdram.c</a></div><div class='hunk'>@@ -147,20 +147,18 @@ static int alt_fpga_bridge_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int alt_fpga_bridge_remove(struct platform_device *pdev)</div><div class='add'>+static void alt_fpga_bridge_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_bridge *br = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	fpga_bridge_unregister(br);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> MODULE_DEVICE_TABLE(of, altera_fpga_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver altera_fpga_driver = {</div><div class='ctx'> 	.probe = alt_fpga_bridge_probe,</div><div class='del'>-	.remove = alt_fpga_bridge_remove,</div><div class='add'>+	.remove_new = alt_fpga_bridge_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "altera_fpga2sdram_bridge",</div><div class='ctx'> 		.of_match_table = of_match_ptr(altera_fpga_of_match),</div><div class='head'>diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera-freeze-bridge.c<br/>index 0c3fb8226908..44061cb16f87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/altera-freeze-bridge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/altera-freeze-bridge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/altera-freeze-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-freeze-bridge.c</a></div><div class='hunk'>@@ -253,18 +253,16 @@ static int altera_freeze_br_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int altera_freeze_br_remove(struct platform_device *pdev)</div><div class='add'>+static void altera_freeze_br_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_bridge *br = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	fpga_bridge_unregister(br);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver altera_freeze_br_driver = {</div><div class='ctx'> 	.probe = altera_freeze_br_probe,</div><div class='del'>-	.remove = altera_freeze_br_remove,</div><div class='add'>+	.remove_new = altera_freeze_br_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "altera_freeze_br",</div><div class='ctx'> 		.of_match_table = altera_freeze_br_of_match,</div><div class='head'>diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera-hps2fpga.c<br/>index 578663503297..6f8e24be19c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/altera-hps2fpga.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/altera-hps2fpga.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/altera-hps2fpga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/altera-hps2fpga.c</a></div><div class='hunk'>@@ -191,7 +191,7 @@ err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int alt_fpga_bridge_remove(struct platform_device *pdev)</div><div class='add'>+static void alt_fpga_bridge_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_bridge *bridge = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct altera_hps2fpga_data *priv = bridge-&gt;priv;</div><div class='hunk'>@@ -199,15 +199,13 @@ static int alt_fpga_bridge_remove(struct platform_device *pdev)</div><div class='ctx'> 	fpga_bridge_unregister(bridge);</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(priv-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> MODULE_DEVICE_TABLE(of, altera_fpga_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver alt_fpga_bridge_driver = {</div><div class='ctx'> 	.probe = alt_fpga_bridge_probe,</div><div class='del'>-	.remove = alt_fpga_bridge_remove,</div><div class='add'>+	.remove_new = alt_fpga_bridge_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "altera_hps2fpga_bridge",</div><div class='ctx'> 		.of_match_table = of_match_ptr(altera_fpga_of_match),</div><div class='head'>diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c<br/>index 7f621e96d3b8..c0a75ca360d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-afu-main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/dfl-afu-main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-afu-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-afu-main.c</a></div><div class='hunk'>@@ -932,15 +932,13 @@ exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int afu_remove(struct platform_device *pdev)</div><div class='add'>+static void afu_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "%s\n", __func__);</div><div class='ctx'> </div><div class='ctx'> 	dfl_fpga_dev_ops_unregister(pdev);</div><div class='ctx'> 	dfl_fpga_dev_feature_uinit(pdev);</div><div class='ctx'> 	afu_dev_destroy(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct attribute_group *afu_dev_groups[] = {</div><div class='hunk'>@@ -956,7 +954,7 @@ static struct platform_driver afu_driver = {</div><div class='ctx'> 		.dev_groups = afu_dev_groups,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe   = afu_probe,</div><div class='del'>-	.remove  = afu_remove,</div><div class='add'>+	.remove_new = afu_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init afu_init(void)</div><div class='head'>diff --git a/drivers/fpga/dfl-fme-br.c b/drivers/fpga/dfl-fme-br.c<br/>index 808d1f4d76df..0b01b3895277 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-br.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/dfl-fme-br.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-br.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-br.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@ static int fme_br_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fme_br_remove(struct platform_device *pdev)</div><div class='add'>+static void fme_br_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_bridge *br = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct fme_br_priv *priv = br-&gt;priv;</div><div class='hunk'>@@ -89,8 +89,6 @@ static int fme_br_remove(struct platform_device *pdev)</div><div class='ctx'> 		put_device(&amp;priv-&gt;port_pdev-&gt;dev);</div><div class='ctx'> 	if (priv-&gt;port_ops)</div><div class='ctx'> 		dfl_fpga_port_ops_put(priv-&gt;port_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver fme_br_driver = {</div><div class='hunk'>@@ -98,7 +96,7 @@ static struct platform_driver fme_br_driver = {</div><div class='ctx'> 		.name    = DFL_FPGA_FME_BRIDGE,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe   = fme_br_probe,</div><div class='del'>-	.remove  = fme_br_remove,</div><div class='add'>+	.remove_new = fme_br_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(fme_br_driver);</div><div class='head'>diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c<br/>index 3dcf990bd261..a2b5da0093da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/dfl-fme-main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-main.c</a></div><div class='hunk'>@@ -730,13 +730,11 @@ exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fme_remove(struct platform_device *pdev)</div><div class='add'>+static void fme_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	dfl_fpga_dev_ops_unregister(pdev);</div><div class='ctx'> 	dfl_fpga_dev_feature_uinit(pdev);</div><div class='ctx'> 	fme_dev_destroy(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct attribute_group *fme_dev_groups[] = {</div><div class='hunk'>@@ -751,7 +749,7 @@ static struct platform_driver fme_driver = {</div><div class='ctx'> 		.dev_groups = fme_dev_groups,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe   = fme_probe,</div><div class='del'>-	.remove  = fme_remove,</div><div class='add'>+	.remove_new = fme_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(fme_driver);</div><div class='head'>diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl-fme-region.c<br/>index 4aebde0a7f1c..71616f8b4982 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-region.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/dfl-fme-region.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/dfl-fme-region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl-fme-region.c</a></div><div class='hunk'>@@ -61,15 +61,13 @@ eprobe_mgr_put:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fme_region_remove(struct platform_device *pdev)</div><div class='add'>+static void fme_region_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_region *region = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct fpga_manager *mgr = region-&gt;mgr;</div><div class='ctx'> </div><div class='ctx'> 	fpga_region_unregister(region);</div><div class='ctx'> 	fpga_mgr_put(mgr);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver fme_region_driver = {</div><div class='hunk'>@@ -77,7 +75,7 @@ static struct platform_driver fme_region_driver = {</div><div class='ctx'> 		.name    = DFL_FPGA_FME_REGION,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe   = fme_region_probe,</div><div class='del'>-	.remove  = fme_region_remove,</div><div class='add'>+	.remove_new = fme_region_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(fme_region_driver);</div><div class='head'>diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c<br/>index dd7a783d53b5..e6d12fbab653 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/dfl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/dfl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/dfl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/dfl.c</a></div><div class='hunk'>@@ -1872,7 +1872,7 @@ static irqreturn_t dfl_irq_handler(int irq, void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct eventfd_ctx *trigger = arg;</div><div class='ctx'> </div><div class='del'>-	eventfd_signal(trigger, 1);</div><div class='add'>+	eventfd_signal(trigger);</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2008,8 +2008,8 @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev,</div><div class='ctx'> 	    (hdr.start + hdr.count &lt; hdr.start))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	fds = memdup_user((void __user *)(arg + sizeof(hdr)),</div><div class='del'>-			  array_size(hdr.count, sizeof(s32)));</div><div class='add'>+	fds = memdup_array_user((void __user *)(arg + sizeof(hdr)),</div><div class='add'>+				hdr.count, sizeof(s32));</div><div class='ctx'> 	if (IS_ERR(fds))</div><div class='ctx'> 		return PTR_ERR(fds);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c<br/>index 31af2e08c825..89851b133709 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/intel-m10-bmc-sec-update.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/intel-m10-bmc-sec-update.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/intel-m10-bmc-sec-update.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/intel-m10-bmc-sec-update.c</a></div><div class='hunk'>@@ -730,15 +730,13 @@ fw_name_fail:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int m10bmc_sec_remove(struct platform_device *pdev)</div><div class='add'>+static void m10bmc_sec_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct m10bmc_sec *sec = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	firmware_upload_unregister(sec-&gt;fwl);</div><div class='ctx'> 	kfree(sec-&gt;fw_name);</div><div class='ctx'> 	xa_erase(&amp;fw_upload_xa, sec-&gt;fw_name_id);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct platform_device_id intel_m10bmc_sec_ids[] = {</div><div class='hunk'>@@ -760,7 +758,7 @@ MODULE_DEVICE_TABLE(platform, intel_m10bmc_sec_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver intel_m10bmc_sec_driver = {</div><div class='ctx'> 	.probe = m10bmc_sec_probe,</div><div class='del'>-	.remove = m10bmc_sec_remove,</div><div class='add'>+	.remove_new = m10bmc_sec_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "intel-m10bmc-sec-update",</div><div class='ctx'> 		.dev_groups = m10bmc_sec_attr_groups,</div><div class='head'>diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c<br/>index a6affd83f275..8526a5a86f0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/of-fpga-region.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/of-fpga-region.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/of-fpga-region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/of-fpga-region.c</a></div><div class='hunk'>@@ -425,20 +425,18 @@ eprobe_mgr_put:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int of_fpga_region_remove(struct platform_device *pdev)</div><div class='add'>+static void of_fpga_region_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_region *region = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct fpga_manager *mgr = region-&gt;mgr;</div><div class='ctx'> </div><div class='ctx'> 	fpga_region_unregister(region);</div><div class='ctx'> 	fpga_mgr_put(mgr);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver of_fpga_region_driver = {</div><div class='ctx'> 	.probe = of_fpga_region_probe,</div><div class='del'>-	.remove = of_fpga_region_remove,</div><div class='add'>+	.remove_new = of_fpga_region_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "of-fpga-region",</div><div class='ctx'> 		.of_match_table = of_match_ptr(fpga_region_of_match),</div><div class='head'>diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c<br/>index cc4861e345c9..4c03513b8f03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/socfpga-a10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/socfpga-a10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/socfpga-a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/socfpga-a10.c</a></div><div class='hunk'>@@ -517,15 +517,13 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int socfpga_a10_fpga_remove(struct platform_device *pdev)</div><div class='add'>+static void socfpga_a10_fpga_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_manager *mgr = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct a10_fpga_priv *priv = mgr-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	fpga_mgr_unregister(mgr);</div><div class='ctx'> 	clk_disable_unprepare(priv-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id socfpga_a10_fpga_of_match[] = {</div><div class='hunk'>@@ -537,7 +535,7 @@ MODULE_DEVICE_TABLE(of, socfpga_a10_fpga_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver socfpga_a10_fpga_driver = {</div><div class='ctx'> 	.probe = socfpga_a10_fpga_probe,</div><div class='del'>-	.remove = socfpga_a10_fpga_remove,</div><div class='add'>+	.remove_new = socfpga_a10_fpga_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "socfpga_a10_fpga_manager",</div><div class='ctx'> 		.of_match_table = socfpga_a10_fpga_of_match,</div><div class='head'>diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c<br/>index cacb9cc5757e..2c0def7d7cbb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/stratix10-soc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/stratix10-soc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/stratix10-soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/stratix10-soc.c</a></div><div class='hunk'>@@ -436,15 +436,13 @@ probe_err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int s10_remove(struct platform_device *pdev)</div><div class='add'>+static void s10_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_manager *mgr = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct s10_priv *priv = mgr-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	fpga_mgr_unregister(mgr);</div><div class='ctx'> 	stratix10_svc_free_channel(priv-&gt;chan);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id s10_of_match[] = {</div><div class='hunk'>@@ -457,7 +455,7 @@ MODULE_DEVICE_TABLE(of, s10_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver s10_driver = {</div><div class='ctx'> 	.probe = s10_probe,</div><div class='del'>-	.remove = s10_remove,</div><div class='add'>+	.remove_new = s10_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "Stratix10 SoC FPGA manager",</div><div class='ctx'> 		.of_match_table = of_match_ptr(s10_of_match),</div><div class='head'>diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c<br/>index 68835896f180..788dd2f63a65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/xilinx-pr-decoupler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/xilinx-pr-decoupler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/xilinx-pr-decoupler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/xilinx-pr-decoupler.c</a></div><div class='hunk'>@@ -150,7 +150,7 @@ err_clk:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xlnx_pr_decoupler_remove(struct platform_device *pdev)</div><div class='add'>+static void xlnx_pr_decoupler_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fpga_bridge *bridge = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct xlnx_pr_decoupler_data *p = bridge-&gt;priv;</div><div class='hunk'>@@ -158,13 +158,11 @@ static int xlnx_pr_decoupler_remove(struct platform_device *pdev)</div><div class='ctx'> 	fpga_bridge_unregister(bridge);</div><div class='ctx'> </div><div class='ctx'> 	clk_unprepare(p-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver xlnx_pr_decoupler_driver = {</div><div class='ctx'> 	.probe = xlnx_pr_decoupler_probe,</div><div class='del'>-	.remove = xlnx_pr_decoupler_remove,</div><div class='add'>+	.remove_new = xlnx_pr_decoupler_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "xlnx_pr_decoupler",</div><div class='ctx'> 		.of_match_table = xlnx_pr_decoupler_of_match,</div><div class='head'>diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c<br/>index 96611d424a10..0ac93183d201 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/fpga/zynq-fpga.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/fpga/zynq-fpga.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/fpga/zynq-fpga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/fpga/zynq-fpga.c</a></div><div class='hunk'>@@ -618,7 +618,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int zynq_fpga_remove(struct platform_device *pdev)</div><div class='add'>+static void zynq_fpga_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct zynq_fpga_priv *priv;</div><div class='ctx'> 	struct fpga_manager *mgr;</div><div class='hunk'>@@ -629,8 +629,6 @@ static int zynq_fpga_remove(struct platform_device *pdev)</div><div class='ctx'> 	fpga_mgr_unregister(mgr);</div><div class='ctx'> </div><div class='ctx'> 	clk_unprepare(priv-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_OF</div><div class='hunk'>@@ -644,7 +642,7 @@ MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver zynq_fpga_driver = {</div><div class='ctx'> 	.probe = zynq_fpga_probe,</div><div class='del'>-	.remove = zynq_fpga_remove,</div><div class='add'>+	.remove_new = zynq_fpga_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "zynq_fpga_manager",</div><div class='ctx'> 		.of_match_table = of_match_ptr(zynq_fpga_of_match),</div><div class='head'>diff --git a/drivers/gnss/serial.c b/drivers/gnss/serial.c<br/>index 5d8e9bfb24d0..baa956494e79 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gnss/serial.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gnss/serial.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gnss/serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/serial.c</a></div><div class='hunk'>@@ -80,8 +80,8 @@ static const struct gnss_operations gnss_serial_gnss_ops = {</div><div class='ctx'> 	.write_raw	= gnss_serial_write_raw,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int gnss_serial_receive_buf(struct serdev_device *serdev,</div><div class='del'>-					const unsigned char *buf, size_t count)</div><div class='add'>+static ssize_t gnss_serial_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				       const u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct gnss_serial *gserial = serdev_device_get_drvdata(serdev);</div><div class='ctx'> 	struct gnss_device *gdev = gserial-&gt;gdev;</div><div class='head'>diff --git a/drivers/gnss/sirf.c b/drivers/gnss/sirf.c<br/>index bcb53ccfee4d..6801a8fb2040 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gnss/sirf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gnss/sirf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gnss/sirf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/sirf.c</a></div><div class='hunk'>@@ -160,8 +160,8 @@ static const struct gnss_operations sirf_gnss_ops = {</div><div class='ctx'> 	.write_raw	= sirf_write_raw,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int sirf_receive_buf(struct serdev_device *serdev,</div><div class='del'>-				const unsigned char *buf, size_t count)</div><div class='add'>+static ssize_t sirf_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				const u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct sirf_data *data = serdev_device_get_drvdata(serdev);</div><div class='ctx'> 	struct gnss_device *gdev = data-&gt;gdev;</div><div class='head'>diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c<br/>index c951be202ca2..92402f6082c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gnss/ubx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gnss/ubx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gnss/ubx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gnss/ubx.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/gnss.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -17,7 +18,6 @@</div><div class='ctx'> #include "serial.h"</div><div class='ctx'> </div><div class='ctx'> struct ubx_data {</div><div class='del'>-	struct regulator *v_bckp;</div><div class='ctx'> 	struct regulator *vcc;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -66,6 +66,7 @@ static const struct gnss_serial_ops ubx_gserial_ops = {</div><div class='ctx'> static int ubx_probe(struct serdev_device *serdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct gnss_serial *gserial;</div><div class='add'>+	struct gpio_desc *reset;</div><div class='ctx'> 	struct ubx_data *data;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -87,30 +88,23 @@ static int ubx_probe(struct serdev_device *serdev)</div><div class='ctx'> 		goto err_free_gserial;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	data-&gt;v_bckp = devm_regulator_get_optional(&amp;serdev-&gt;dev, "v-bckp");</div><div class='del'>-	if (IS_ERR(data-&gt;v_bckp)) {</div><div class='del'>-		ret = PTR_ERR(data-&gt;v_bckp);</div><div class='del'>-		if (ret == -ENODEV)</div><div class='del'>-			data-&gt;v_bckp = NULL;</div><div class='del'>-		else</div><div class='del'>-			goto err_free_gserial;</div><div class='del'>-	}</div><div class='add'>+	ret = devm_regulator_get_enable_optional(&amp;serdev-&gt;dev, "v-bckp");</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -ENODEV)</div><div class='add'>+		goto err_free_gserial;</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;v_bckp) {</div><div class='del'>-		ret = regulator_enable(data-&gt;v_bckp);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err_free_gserial;</div><div class='add'>+	/* Deassert reset */</div><div class='add'>+	reset = devm_gpiod_get_optional(&amp;serdev-&gt;dev, "reset", GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(reset)) {</div><div class='add'>+		ret = PTR_ERR(reset);</div><div class='add'>+		goto err_free_gserial;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = gnss_serial_register(gserial);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto err_disable_v_bckp;</div><div class='add'>+		goto err_free_gserial;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err_disable_v_bckp:</div><div class='del'>-	if (data-&gt;v_bckp)</div><div class='del'>-		regulator_disable(data-&gt;v_bckp);</div><div class='ctx'> err_free_gserial:</div><div class='ctx'> 	gnss_serial_free(gserial);</div><div class='ctx'> </div><div class='hunk'>@@ -120,11 +114,8 @@ err_free_gserial:</div><div class='ctx'> static void ubx_remove(struct serdev_device *serdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct gnss_serial *gserial = serdev_device_get_drvdata(serdev);</div><div class='del'>-	struct ubx_data *data = gnss_serial_get_drvdata(gserial);</div><div class='ctx'> </div><div class='ctx'> 	gnss_serial_deregister(gserial);</div><div class='del'>-	if (data-&gt;v_bckp)</div><div class='del'>-		regulator_disable(data-&gt;v_bckp);</div><div class='ctx'> 	gnss_serial_free(gserial);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig<br/>index b3a133ed31ee..1301cec94f12 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/Kconfig</a></div><div class='hunk'>@@ -478,6 +478,13 @@ config GPIO_MXS</div><div class='ctx'> 	select GPIO_GENERIC</div><div class='ctx'> 	select GENERIC_IRQ_CHIP</div><div class='ctx'> </div><div class='add'>+config GPIO_NPCM_SGPIO</div><div class='add'>+	bool "Nuvoton SGPIO support"</div><div class='add'>+	depends on ARCH_NPCM || COMPILE_TEST</div><div class='add'>+	select GPIOLIB_IRQCHIP</div><div class='add'>+	help</div><div class='add'>+	  Say Y here to support Nuvoton NPCM7XX/NPCM8XX SGPIO functionality.</div><div class='add'>+</div><div class='ctx'> config GPIO_OCTEON</div><div class='ctx'> 	tristate "Cavium OCTEON GPIO"</div><div class='ctx'> 	depends on CAVIUM_OCTEON_SOC</div><div class='hunk'>@@ -553,6 +560,19 @@ config GPIO_ROCKCHIP</div><div class='ctx'> 	help</div><div class='ctx'> 	  Say yes here to support GPIO on Rockchip SoCs.</div><div class='ctx'> </div><div class='add'>+config GPIO_RTD</div><div class='add'>+	tristate "Realtek DHC GPIO support"</div><div class='add'>+	depends on ARCH_REALTEK</div><div class='add'>+	default y</div><div class='add'>+	select GPIOLIB_IRQCHIP</div><div class='add'>+	help</div><div class='add'>+	  This option enables support for GPIOs found on Realtek DHC(Digital</div><div class='add'>+	  Home Center) SoCs family, including RTD1295, RTD1315E, RTD1319,</div><div class='add'>+	  RTD1319D, RTD1395, RTD1619 and RTD1619B.</div><div class='add'>+</div><div class='add'>+	  Say yes here to support GPIO functionality and GPIO interrupt on</div><div class='add'>+	  Realtek DHC SoCs.</div><div class='add'>+</div><div class='ctx'> config GPIO_SAMA5D2_PIOBU</div><div class='ctx'> 	tristate "SAMA5D2 PIOBU GPIO support"</div><div class='ctx'> 	depends on MFD_SYSCON</div><div class='head'>diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile<br/>index eb73b5d633eb..9e40af196aae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/Makefile</a></div><div class='hunk'>@@ -116,6 +116,7 @@ obj-$(CONFIG_GPIO_MT7621)		+= gpio-mt7621.o</div><div class='ctx'> obj-$(CONFIG_GPIO_MVEBU)		+= gpio-mvebu.o</div><div class='ctx'> obj-$(CONFIG_GPIO_MXC)			+= gpio-mxc.o</div><div class='ctx'> obj-$(CONFIG_GPIO_MXS)			+= gpio-mxs.o</div><div class='add'>+obj-$(CONFIG_GPIO_NPCM_SGPIO)		+= gpio-npcm-sgpio.o</div><div class='ctx'> obj-$(CONFIG_GPIO_OCTEON)		+= gpio-octeon.o</div><div class='ctx'> obj-$(CONFIG_GPIO_OMAP)			+= gpio-omap.o</div><div class='ctx'> obj-$(CONFIG_GPIO_PALMAS)		+= gpio-palmas.o</div><div class='hunk'>@@ -137,6 +138,7 @@ obj-$(CONFIG_GPIO_RDC321X)		+= gpio-rdc321x.o</div><div class='ctx'> obj-$(CONFIG_GPIO_REALTEK_OTTO)		+= gpio-realtek-otto.o</div><div class='ctx'> obj-$(CONFIG_GPIO_REG)			+= gpio-reg.o</div><div class='ctx'> obj-$(CONFIG_GPIO_ROCKCHIP)	+= gpio-rockchip.o</div><div class='add'>+obj-$(CONFIG_GPIO_RTD)			+= gpio-rtd.o</div><div class='ctx'> obj-$(CONFIG_ARCH_SA1100)		+= gpio-sa1100.o</div><div class='ctx'> obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)	+= gpio-sama5d2-piobu.o</div><div class='ctx'> obj-$(CONFIG_GPIO_SCH311X)		+= gpio-sch311x.o</div><div class='head'>diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c<br/>index 4a4f61bf6c58..798235791f70 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-dwapb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-dwapb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-dwapb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-dwapb.c</a></div><div class='hunk'>@@ -282,13 +282,15 @@ static void dwapb_irq_enable(struct irq_data *d)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);</div><div class='ctx'> 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);</div><div class='add'>+	irq_hw_number_t hwirq = irqd_to_hwirq(d);</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	raw_spin_lock_irqsave(&amp;gc-&gt;bgpio_lock, flags);</div><div class='del'>-	val = dwapb_read(gpio, GPIO_INTEN);</div><div class='del'>-	val |= BIT(irqd_to_hwirq(d));</div><div class='add'>+	val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);</div><div class='ctx'> 	dwapb_write(gpio, GPIO_INTEN, val);</div><div class='add'>+	val = dwapb_read(gpio, GPIO_INTMASK) &amp; ~BIT(hwirq);</div><div class='add'>+	dwapb_write(gpio, GPIO_INTMASK, val);</div><div class='ctx'> 	raw_spin_unlock_irqrestore(&amp;gc-&gt;bgpio_lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -296,12 +298,14 @@ static void dwapb_irq_disable(struct irq_data *d)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);</div><div class='ctx'> 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);</div><div class='add'>+	irq_hw_number_t hwirq = irqd_to_hwirq(d);</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	raw_spin_lock_irqsave(&amp;gc-&gt;bgpio_lock, flags);</div><div class='del'>-	val = dwapb_read(gpio, GPIO_INTEN);</div><div class='del'>-	val &amp;= ~BIT(irqd_to_hwirq(d));</div><div class='add'>+	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);</div><div class='add'>+	dwapb_write(gpio, GPIO_INTMASK, val);</div><div class='add'>+	val = dwapb_read(gpio, GPIO_INTEN) &amp; ~BIT(hwirq);</div><div class='ctx'> 	dwapb_write(gpio, GPIO_INTEN, val);</div><div class='ctx'> 	raw_spin_unlock_irqrestore(&amp;gc-&gt;bgpio_lock, flags);</div><div class='ctx'> }</div><div class='hunk'>@@ -412,11 +416,12 @@ static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,</div><div class='ctx'> {</div><div class='ctx'> 	u32 debounce;</div><div class='ctx'> </div><div class='del'>-	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)</div><div class='del'>-		return -ENOTSUPP;</div><div class='add'>+	if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {</div><div class='add'>+		debounce = pinconf_to_config_argument(config);</div><div class='add'>+		return dwapb_gpio_set_debounce(gc, offset, debounce);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	debounce = pinconf_to_config_argument(config);</div><div class='del'>-	return dwapb_gpio_set_debounce(gc, offset, debounce);</div><div class='add'>+	return gpiochip_generic_config(gc, offset, config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,</div><div class='hunk'>@@ -526,10 +531,14 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,</div><div class='ctx'> 	port-&gt;gc.fwnode = pp-&gt;fwnode;</div><div class='ctx'> 	port-&gt;gc.ngpio = pp-&gt;ngpio;</div><div class='ctx'> 	port-&gt;gc.base = pp-&gt;gpio_base;</div><div class='add'>+	port-&gt;gc.request = gpiochip_generic_request;</div><div class='add'>+	port-&gt;gc.free = gpiochip_generic_free;</div><div class='ctx'> </div><div class='ctx'> 	/* Only port A support debounce */</div><div class='ctx'> 	if (pp-&gt;idx == 0)</div><div class='ctx'> 		port-&gt;gc.set_config = dwapb_gpio_set_config;</div><div class='add'>+	else</div><div class='add'>+		port-&gt;gc.set_config = gpiochip_generic_config;</div><div class='ctx'> </div><div class='ctx'> 	/* Only port A can provide interrupts in all configurations of the IP */</div><div class='ctx'> 	if (pp-&gt;idx == 0)</div><div class='head'>diff --git a/drivers/gpio/gpio-elkhartlake.c b/drivers/gpio/gpio-elkhartlake.c<br/>index a9c8b16215be..887c0fe99d39 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-elkhartlake.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-elkhartlake.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-elkhartlake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-elkhartlake.c</a></div><div class='hunk'>@@ -55,18 +55,6 @@ static int ehl_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ehl_gpio_suspend(struct device *dev)</div><div class='del'>-{</div><div class='del'>-	return tng_gpio_suspend(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ehl_gpio_resume(struct device *dev)</div><div class='del'>-{</div><div class='del'>-	return tng_gpio_resume(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static DEFINE_SIMPLE_DEV_PM_OPS(ehl_gpio_pm_ops, ehl_gpio_suspend, ehl_gpio_resume);</div><div class='del'>-</div><div class='ctx'> static const struct platform_device_id ehl_gpio_ids[] = {</div><div class='ctx'> 	{ "gpio-elkhartlake" },</div><div class='ctx'> 	{ }</div><div class='hunk'>@@ -76,7 +64,7 @@ MODULE_DEVICE_TABLE(platform, ehl_gpio_ids);</div><div class='ctx'> static struct platform_driver ehl_gpio_driver = {</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name	= "gpio-elkhartlake",</div><div class='del'>-		.pm	= pm_sleep_ptr(&amp;ehl_gpio_pm_ops),</div><div class='add'>+		.pm	= pm_sleep_ptr(&amp;tng_gpio_pm_ops),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= ehl_gpio_probe,</div><div class='ctx'> 	.id_table	= ehl_gpio_ids,</div><div class='head'>diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c<br/>index f836a8db4c1d..69834db2c1cf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-en7523.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-en7523.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-en7523.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-en7523.c</a></div><div class='hunk'>@@ -12,11 +12,11 @@</div><div class='ctx'> #define AIROHA_GPIO_MAX		32</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * airoha_gpio_ctrl - Airoha GPIO driver data</div><div class='add'>+ * struct airoha_gpio_ctrl - Airoha GPIO driver data</div><div class='ctx'>  * @gc: Associated gpio_chip instance.</div><div class='ctx'>  * @data: The data register.</div><div class='del'>- * @dir0: The direction register for the lower 16 pins.</div><div class='del'>- * @dir1: The direction register for the higher 16 pins.</div><div class='add'>+ * @dir: [0] The direction register for the lower 16 pins.</div><div class='add'>+ * [1]: The direction register for the higher 16 pins.</div><div class='ctx'>  * @output: The output enable register.</div><div class='ctx'>  */</div><div class='ctx'> struct airoha_gpio_ctrl {</div><div class='head'>diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c<br/>index dde6cf3a5779..c5a9fa640566 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-ixp4xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-ixp4xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-ixp4xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-ixp4xx.c</a></div><div class='hunk'>@@ -38,6 +38,18 @@</div><div class='ctx'> #define IXP4XX_GPIO_STYLE_MASK		GENMASK(2, 0)</div><div class='ctx'> #define IXP4XX_GPIO_STYLE_SIZE		3</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Clock output control register defines.</div><div class='add'>+ */</div><div class='add'>+#define IXP4XX_GPCLK_CLK0DC_SHIFT	0</div><div class='add'>+#define IXP4XX_GPCLK_CLK0TC_SHIFT	4</div><div class='add'>+#define IXP4XX_GPCLK_CLK0_MASK		GENMASK(7, 0)</div><div class='add'>+#define IXP4XX_GPCLK_MUX14		BIT(8)</div><div class='add'>+#define IXP4XX_GPCLK_CLK1DC_SHIFT	16</div><div class='add'>+#define IXP4XX_GPCLK_CLK1TC_SHIFT	20</div><div class='add'>+#define IXP4XX_GPCLK_CLK1_MASK		GENMASK(23, 16)</div><div class='add'>+#define IXP4XX_GPCLK_MUX15		BIT(24)</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct ixp4xx_gpio - IXP4 GPIO state container</div><div class='ctx'>  * @dev: containing device for this instance</div><div class='hunk'>@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct ixp4xx_gpio *g;</div><div class='ctx'> 	struct gpio_irq_chip *girq;</div><div class='ctx'> 	struct device_node *irq_parent;</div><div class='add'>+	bool clk_14, clk_15;</div><div class='add'>+	u32 val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);</div><div class='hunk'>@@ -226,12 +240,47 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 	g-&gt;fwnode = of_node_to_fwnode(np);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * If either clock output is enabled explicitly in the device tree</div><div class='add'>+	 * we take full control of the clock by masking off all bits for</div><div class='add'>+	 * the clock control and selectively enabling them. Otherwise</div><div class='add'>+	 * we leave the hardware default settings.</div><div class='add'>+	 *</div><div class='add'>+	 * Enable clock outputs with default timings of requested clock.</div><div class='add'>+	 * If you need control over TC and DC, add these to the device</div><div class='add'>+	 * tree bindings and use them here.</div><div class='add'>+	 */</div><div class='add'>+	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");</div><div class='add'>+	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on</div><div class='ctx'> 	 * specific machines.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||</div><div class='ctx'> 	    of_machine_is_compatible("iom,nas-100d"))</div><div class='del'>-		__raw_writel(0x0, g-&gt;base + IXP4XX_REG_GPCLK);</div><div class='add'>+		val = 0;</div><div class='add'>+	else {</div><div class='add'>+		val = __raw_readl(g-&gt;base + IXP4XX_REG_GPCLK);</div><div class='add'>+</div><div class='add'>+		if (clk_14 || clk_15) {</div><div class='add'>+			val &amp;= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);</div><div class='add'>+			val &amp;= ~IXP4XX_GPCLK_CLK0_MASK;</div><div class='add'>+			val &amp;= ~IXP4XX_GPCLK_CLK1_MASK;</div><div class='add'>+			if (clk_14) {</div><div class='add'>+				/* IXP4XX_GPCLK_CLK0DC implicit low */</div><div class='add'>+				val |= (1 &lt;&lt; IXP4XX_GPCLK_CLK0TC_SHIFT);</div><div class='add'>+				val |= IXP4XX_GPCLK_MUX14;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (clk_15) {</div><div class='add'>+				/* IXP4XX_GPCLK_CLK1DC implicit low */</div><div class='add'>+				val |= (1 &lt;&lt; IXP4XX_GPCLK_CLK1TC_SHIFT);</div><div class='add'>+				val |= IXP4XX_GPCLK_MUX15;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	__raw_writel(val, g-&gt;base + IXP4XX_REG_GPCLK);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * This is a very special big-endian ARM issue: when the IXP4xx is</div><div class='head'>diff --git a/drivers/gpio/gpio-max730x.c b/drivers/gpio/gpio-max730x.c<br/>index bb5cf14ae4c8..701795b9d329 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-max730x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-max730x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-max730x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-max730x.c</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-/**</div><div class='add'>+/*</div><div class='ctx'>  * Copyright (C) 2006 Juergen Beisert, Pengutronix</div><div class='ctx'>  * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix</div><div class='ctx'>  * Copyright (C) 2009 Wolfram Sang, Pengutronix</div><div class='head'>diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c<br/>index 7a3e1760fc5b..d5906d419b0a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mlxbf3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-mlxbf3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mlxbf3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mlxbf3.c</a></div><div class='hunk'>@@ -215,6 +215,8 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 			gs-&gt;gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,</div><div class='ctx'> 			gs-&gt;gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,</div><div class='ctx'> 			gs-&gt;gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__);</div><div class='ctx'> </div><div class='ctx'> 	gc-&gt;request = gpiochip_generic_request;</div><div class='ctx'> 	gc-&gt;free = gpiochip_generic_free;</div><div class='head'>diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c<br/>index 3ff0ea1e351c..71e1af7c2184 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mmio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-mmio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mmio.c</a></div><div class='hunk'>@@ -40,25 +40,22 @@ o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`</div><div class='ctx'>  *               `.......````.```</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/compiler.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='del'>-#include &lt;linux/bug.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/ioport.h&gt;</div><div class='add'>+#include &lt;linux/log2.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='del'>-#include &lt;linux/compiler.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/errno.h&gt;</div><div class='del'>-#include &lt;linux/log2.h&gt;</div><div class='del'>-#include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/io.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/gpio/driver.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/bitops.h&gt;</div><div class='del'>-#include &lt;linux/platform_device.h&gt;</div><div class='del'>-#include &lt;linux/property.h&gt;</div><div class='del'>-#include &lt;linux/mod_devicetable.h&gt;</div><div class='del'>-#include &lt;linux/of.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "gpiolib.h"</div><div class='ctx'> </div><div class='hunk'>@@ -688,7 +685,6 @@ static void __iomem *bgpio_map(struct platform_device *pdev,</div><div class='ctx'> 	return devm_ioremap_resource(&amp;pdev-&gt;dev, r);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_OF</div><div class='ctx'> static const struct of_device_id bgpio_of_match[] = {</div><div class='ctx'> 	{ .compatible = "brcm,bcm6345-gpio" },</div><div class='ctx'> 	{ .compatible = "wd,mbl-gpio" },</div><div class='hunk'>@@ -697,36 +693,27 @@ static const struct of_device_id bgpio_of_match[] = {</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, bgpio_of_match);</div><div class='ctx'> </div><div class='del'>-static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,</div><div class='del'>-					  unsigned long *flags)</div><div class='add'>+static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct bgpio_pdata *pdata;</div><div class='ctx'> </div><div class='del'>-	if (!pdev-&gt;dev.of_node)</div><div class='add'>+	if (!dev_fwnode(dev))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	pdata = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(struct bgpio_pdata),</div><div class='del'>-			     GFP_KERNEL);</div><div class='add'>+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);</div><div class='ctx'> 	if (!pdata)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='ctx'> 	pdata-&gt;base = -1;</div><div class='ctx'> </div><div class='del'>-	if (of_device_is_big_endian(pdev-&gt;dev.of_node))</div><div class='add'>+	if (device_is_big_endian(dev))</div><div class='ctx'> 		*flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;</div><div class='ctx'> </div><div class='del'>-	if (of_property_read_bool(pdev-&gt;dev.of_node, "no-output"))</div><div class='add'>+	if (device_property_read_bool(dev, "no-output"))</div><div class='ctx'> 		*flags |= BGPIOF_NO_OUTPUT;</div><div class='ctx'> </div><div class='ctx'> 	return pdata;</div><div class='ctx'> }</div><div class='del'>-#else</div><div class='del'>-static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,</div><div class='del'>-					  unsigned long *flags)</div><div class='del'>-{</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-#endif /* CONFIG_OF */</div><div class='ctx'> </div><div class='ctx'> static int bgpio_pdev_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='hunk'>@@ -743,7 +730,7 @@ static int bgpio_pdev_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct gpio_chip *gc;</div><div class='ctx'> 	struct bgpio_pdata *pdata;</div><div class='ctx'> </div><div class='del'>-	pdata = bgpio_parse_dt(pdev, &amp;flags);</div><div class='add'>+	pdata = bgpio_parse_fw(dev, &amp;flags);</div><div class='ctx'> 	if (IS_ERR(pdata))</div><div class='ctx'> 		return PTR_ERR(pdata);</div><div class='ctx'> </div><div class='hunk'>@@ -814,7 +801,7 @@ MODULE_DEVICE_TABLE(platform, bgpio_id_table);</div><div class='ctx'> static struct platform_driver bgpio_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "basic-mmio-gpio",</div><div class='del'>-		.of_match_table = of_match_ptr(bgpio_of_match),</div><div class='add'>+		.of_match_table = bgpio_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.id_table = bgpio_id_table,</div><div class='ctx'> 	.probe = bgpio_pdev_probe,</div><div class='head'>diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c<br/>index 4870e267a402..455eecf6380e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mockup.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-mockup.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-mockup.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-mockup.c</a></div><div class='hunk'>@@ -354,7 +354,6 @@ static const struct file_operations gpio_mockup_debugfs_ops = {</div><div class='ctx'> static void gpio_mockup_debugfs_setup(struct device *dev,</div><div class='ctx'> 				      struct gpio_mockup_chip *chip)</div><div class='ctx'> {</div><div class='del'>-	struct device *child __free(put_device) = NULL;</div><div class='ctx'> 	struct gpio_mockup_dbgfs_private *priv;</div><div class='ctx'> 	struct gpio_chip *gc;</div><div class='ctx'> 	const char *devname;</div><div class='hunk'>@@ -367,7 +366,7 @@ static void gpio_mockup_debugfs_setup(struct device *dev,</div><div class='ctx'> 	 * There can only be a single GPIO device per platform device in</div><div class='ctx'> 	 * gpio-mockup so using device_find_any_child() is OK.</div><div class='ctx'> 	 */</div><div class='del'>-	child = device_find_any_child(dev);</div><div class='add'>+	struct device *child __free(put_device) = device_find_any_child(dev);</div><div class='ctx'> 	if (!child)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpio/gpio-npcm-sgpio.c b/drivers/gpio/gpio-npcm-sgpio.c<br/>new file mode 100644<br/>index 000000000000..d31788b43abc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-npcm-sgpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-npcm-sgpio.c</a></div><div class='hunk'>@@ -0,0 +1,619 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Nuvoton NPCM Serial GPIO Driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021 Nuvoton Technologies</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/gpio/driver.h&gt;</div><div class='add'>+#include &lt;linux/hashtable.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#define MAX_NR_HW_SGPIO		64</div><div class='add'>+</div><div class='add'>+#define  NPCM_IOXCFG1		0x2A</div><div class='add'>+#define  NPCM_IOXCFG1_SFT_CLK	GENMASK(3, 0)</div><div class='add'>+#define  NPCM_IOXCFG1_SCLK_POL	BIT(4)</div><div class='add'>+#define  NPCM_IOXCFG1_LDSH_POL	BIT(5)</div><div class='add'>+</div><div class='add'>+#define  NPCM_IOXCTS			0x28</div><div class='add'>+#define  NPCM_IOXCTS_IOXIF_EN		BIT(7)</div><div class='add'>+#define  NPCM_IOXCTS_RD_MODE		GENMASK(2, 1)</div><div class='add'>+#define  NPCM_IOXCTS_RD_MODE_PERIODIC	BIT(2)</div><div class='add'>+</div><div class='add'>+#define  NPCM_IOXCFG2		0x2B</div><div class='add'>+#define  NPCM_IOXCFG2_PORT	GENMASK(3, 0)</div><div class='add'>+</div><div class='add'>+#define  NPCM_IXOEVCFG_MASK	GENMASK(1, 0)</div><div class='add'>+#define  NPCM_IXOEVCFG_FALLING	BIT(1)</div><div class='add'>+#define  NPCM_IXOEVCFG_RISING	BIT(0)</div><div class='add'>+#define  NPCM_IXOEVCFG_BOTH	(NPCM_IXOEVCFG_FALLING | NPCM_IXOEVCFG_RISING)</div><div class='add'>+</div><div class='add'>+#define NPCM_CLK_MHZ	(8 * HZ_PER_MHZ)</div><div class='add'>+#define NPCM_750_OPT	6</div><div class='add'>+#define NPCM_845_OPT	5</div><div class='add'>+</div><div class='add'>+#define GPIO_BANK(x)    ((x) / 8)</div><div class='add'>+#define GPIO_BIT(x)     ((x) % 8)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Select the frequency of shift clock.</div><div class='add'>+ * The shift clock is a division of the APB clock.</div><div class='add'>+ */</div><div class='add'>+struct npcm_clk_cfg {</div><div class='add'>+	unsigned int	*sft_clk;</div><div class='add'>+	unsigned int	*clk_sel;</div><div class='add'>+	unsigned int	cfg_opt;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct npcm_sgpio {</div><div class='add'>+	struct gpio_chip chip;</div><div class='add'>+	struct clk *pclk;</div><div class='add'>+	struct irq_chip intc;</div><div class='add'>+	raw_spinlock_t lock;</div><div class='add'>+</div><div class='add'>+	void __iomem *base;</div><div class='add'>+	int irq;</div><div class='add'>+	u8 nin_sgpio;</div><div class='add'>+	u8 nout_sgpio;</div><div class='add'>+	u8 in_port;</div><div class='add'>+	u8 out_port;</div><div class='add'>+	u8 int_type[MAX_NR_HW_SGPIO];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct npcm_sgpio_bank {</div><div class='add'>+	u8 rdata_reg;</div><div class='add'>+	u8 wdata_reg;</div><div class='add'>+	u8 event_config;</div><div class='add'>+	u8 event_status;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum npcm_sgpio_reg {</div><div class='add'>+	READ_DATA,</div><div class='add'>+	WRITE_DATA,</div><div class='add'>+	EVENT_CFG,</div><div class='add'>+	EVENT_STS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct npcm_sgpio_bank npcm_sgpio_banks[] = {</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x00,</div><div class='add'>+		.rdata_reg = 0x08,</div><div class='add'>+		.event_config = 0x10,</div><div class='add'>+		.event_status = 0x20,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x01,</div><div class='add'>+		.rdata_reg = 0x09,</div><div class='add'>+		.event_config = 0x12,</div><div class='add'>+		.event_status = 0x21,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x02,</div><div class='add'>+		.rdata_reg = 0x0a,</div><div class='add'>+		.event_config = 0x14,</div><div class='add'>+		.event_status = 0x22,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x03,</div><div class='add'>+		.rdata_reg = 0x0b,</div><div class='add'>+		.event_config = 0x16,</div><div class='add'>+		.event_status = 0x23,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x04,</div><div class='add'>+		.rdata_reg = 0x0c,</div><div class='add'>+		.event_config = 0x18,</div><div class='add'>+		.event_status = 0x24,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x05,</div><div class='add'>+		.rdata_reg = 0x0d,</div><div class='add'>+		.event_config = 0x1a,</div><div class='add'>+		.event_status = 0x25,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x06,</div><div class='add'>+		.rdata_reg = 0x0e,</div><div class='add'>+		.event_config = 0x1c,</div><div class='add'>+		.event_status = 0x26,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.wdata_reg = 0x07,</div><div class='add'>+		.rdata_reg = 0x0f,</div><div class='add'>+		.event_config = 0x1e,</div><div class='add'>+		.event_status = 0x27,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void __iomem *bank_reg(struct npcm_sgpio *gpio,</div><div class='add'>+			      const struct npcm_sgpio_bank *bank,</div><div class='add'>+			      const enum npcm_sgpio_reg reg)</div><div class='add'>+{</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case READ_DATA:</div><div class='add'>+		return gpio-&gt;base + bank-&gt;rdata_reg;</div><div class='add'>+	case WRITE_DATA:</div><div class='add'>+		return gpio-&gt;base + bank-&gt;wdata_reg;</div><div class='add'>+	case EVENT_CFG:</div><div class='add'>+		return gpio-&gt;base + bank-&gt;event_config;</div><div class='add'>+	case EVENT_STS:</div><div class='add'>+		return gpio-&gt;base + bank-&gt;event_status;</div><div class='add'>+	default:</div><div class='add'>+		/* actually if code runs to here, it's an error case */</div><div class='add'>+		dev_WARN(gpio-&gt;chip.parent, "Getting here is an error condition");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	unsigned int bank = GPIO_BANK(offset);</div><div class='add'>+</div><div class='add'>+	return &amp;npcm_sgpio_banks[bank];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irqd_to_data(struct irq_data *d,</div><div class='add'>+				    struct npcm_sgpio **gpio,</div><div class='add'>+				    const struct npcm_sgpio_bank **bank,</div><div class='add'>+				    u8 *bit, unsigned int *offset)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *internal;</div><div class='add'>+</div><div class='add'>+	*offset = irqd_to_hwirq(d);</div><div class='add'>+	internal = irq_data_get_irq_chip_data(d);</div><div class='add'>+</div><div class='add'>+	*gpio = internal;</div><div class='add'>+	*offset -= internal-&gt;nout_sgpio;</div><div class='add'>+	*bank = offset_to_bank(*offset);</div><div class='add'>+	*bit = GPIO_BIT(*offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_init_port(struct npcm_sgpio *gpio)</div><div class='add'>+{</div><div class='add'>+	u8 in_port, out_port, set_port, reg;</div><div class='add'>+</div><div class='add'>+	in_port = GPIO_BANK(gpio-&gt;nin_sgpio);</div><div class='add'>+	if (GPIO_BIT(gpio-&gt;nin_sgpio) &gt; 0)</div><div class='add'>+		in_port += 1;</div><div class='add'>+</div><div class='add'>+	out_port = GPIO_BANK(gpio-&gt;nout_sgpio);</div><div class='add'>+	if (GPIO_BIT(gpio-&gt;nout_sgpio) &gt; 0)</div><div class='add'>+		out_port += 1;</div><div class='add'>+</div><div class='add'>+	gpio-&gt;in_port = in_port;</div><div class='add'>+	gpio-&gt;out_port = out_port;</div><div class='add'>+	set_port = (out_port &amp; NPCM_IOXCFG2_PORT) &lt;&lt; 4 |</div><div class='add'>+		   (in_port &amp; NPCM_IOXCFG2_PORT);</div><div class='add'>+	iowrite8(set_port, gpio-&gt;base + NPCM_IOXCFG2);</div><div class='add'>+</div><div class='add'>+	reg = ioread8(gpio-&gt;base + NPCM_IOXCFG2);</div><div class='add'>+</div><div class='add'>+	return reg == set_port ? 0 : -EINVAL;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+</div><div class='add'>+	return offset &lt;	gpio-&gt;nout_sgpio ? -EINVAL : 0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)</div><div class='add'>+{</div><div class='add'>+	gc-&gt;set(gc, offset, val);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+</div><div class='add'>+	if (offset &lt; gpio-&gt;nout_sgpio)</div><div class='add'>+		return GPIO_LINE_DIRECTION_OUT;</div><div class='add'>+</div><div class='add'>+	return GPIO_LINE_DIRECTION_IN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+	const struct  npcm_sgpio_bank *bank = offset_to_bank(offset);</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+	u8 reg = 0;</div><div class='add'>+</div><div class='add'>+	addr = bank_reg(gpio, bank, WRITE_DATA);</div><div class='add'>+	reg = ioread8(addr);</div><div class='add'>+</div><div class='add'>+	if (val)</div><div class='add'>+		reg |= BIT(GPIO_BIT(offset));</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~BIT(GPIO_BIT(offset));</div><div class='add'>+</div><div class='add'>+	iowrite8(reg, addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_get(struct gpio_chip *gc, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+	const struct  npcm_sgpio_bank *bank;</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+	u8 reg;</div><div class='add'>+</div><div class='add'>+	if (offset &lt; gpio-&gt;nout_sgpio) {</div><div class='add'>+		bank = offset_to_bank(offset);</div><div class='add'>+		addr = bank_reg(gpio, bank, WRITE_DATA);</div><div class='add'>+	} else {</div><div class='add'>+		offset -= gpio-&gt;nout_sgpio;</div><div class='add'>+		bank = offset_to_bank(offset);</div><div class='add'>+		addr = bank_reg(gpio, bank, READ_DATA);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg = ioread8(addr);</div><div class='add'>+</div><div class='add'>+	return !!(reg &amp; BIT(GPIO_BIT(offset)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_setup_enable(struct npcm_sgpio *gpio, bool enable)</div><div class='add'>+{</div><div class='add'>+	u8 reg;</div><div class='add'>+</div><div class='add'>+	reg = ioread8(gpio-&gt;base + NPCM_IOXCTS);</div><div class='add'>+	reg = (reg &amp; ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC;</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		reg |= NPCM_IOXCTS_IOXIF_EN;</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~NPCM_IOXCTS_IOXIF_EN;</div><div class='add'>+</div><div class='add'>+	iowrite8(reg, gpio-&gt;base + NPCM_IOXCTS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_setup_clk(struct npcm_sgpio *gpio,</div><div class='add'>+				const struct npcm_clk_cfg *clk_cfg)</div><div class='add'>+{</div><div class='add'>+	unsigned long apb_freq;</div><div class='add'>+	u32 val;</div><div class='add'>+	u8 tmp;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	apb_freq = clk_get_rate(gpio-&gt;pclk);</div><div class='add'>+	tmp = ioread8(gpio-&gt;base + NPCM_IOXCFG1) &amp; ~NPCM_IOXCFG1_SFT_CLK;</div><div class='add'>+</div><div class='add'>+	for (i = clk_cfg-&gt;cfg_opt-1; i &gt; 0; i--) {</div><div class='add'>+		val = apb_freq / clk_cfg-&gt;sft_clk[i];</div><div class='add'>+		if (NPCM_CLK_MHZ &gt; val) {</div><div class='add'>+			iowrite8(clk_cfg-&gt;clk_sel[i] | tmp,</div><div class='add'>+				 gpio-&gt;base + NPCM_IOXCFG1);</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_init_valid_mask(struct gpio_chip *gc,</div><div class='add'>+					   unsigned long *valid_mask,</div><div class='add'>+					   unsigned int ngpios)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+</div><div class='add'>+	/* input GPIOs in the high range */</div><div class='add'>+	bitmap_set(valid_mask, gpio-&gt;nout_sgpio, gpio-&gt;nin_sgpio);</div><div class='add'>+	bitmap_clear(valid_mask, 0, gpio-&gt;nout_sgpio);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_set_mask(struct irq_data *d, bool set)</div><div class='add'>+{</div><div class='add'>+	const struct npcm_sgpio_bank *bank;</div><div class='add'>+	struct npcm_sgpio *gpio;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+	unsigned int offset;</div><div class='add'>+	u16 reg, type;</div><div class='add'>+	u8 bit;</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_irqd_to_data(d, &amp;gpio, &amp;bank, &amp;bit, &amp;offset);</div><div class='add'>+	addr = bank_reg(gpio, bank, EVENT_CFG);</div><div class='add'>+</div><div class='add'>+	reg = ioread16(addr);</div><div class='add'>+	if (set) {</div><div class='add'>+		reg &amp;= ~(NPCM_IXOEVCFG_MASK &lt;&lt; (bit * 2));</div><div class='add'>+	} else {</div><div class='add'>+		type = gpio-&gt;int_type[offset];</div><div class='add'>+		reg |= (type &lt;&lt; (bit * 2));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	raw_spin_lock_irqsave(&amp;gpio-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, false);</div><div class='add'>+</div><div class='add'>+	iowrite16(reg, addr);</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, true);</div><div class='add'>+</div><div class='add'>+	addr = bank_reg(gpio, bank, EVENT_STS);</div><div class='add'>+	reg = ioread8(addr);</div><div class='add'>+	reg |= BIT(bit);</div><div class='add'>+	iowrite8(reg, addr);</div><div class='add'>+</div><div class='add'>+	raw_spin_unlock_irqrestore(&amp;gpio-&gt;lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_ack(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	const struct npcm_sgpio_bank *bank;</div><div class='add'>+	struct npcm_sgpio *gpio;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	void __iomem *status_addr;</div><div class='add'>+	unsigned int offset;</div><div class='add'>+	u8 bit;</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_irqd_to_data(d, &amp;gpio, &amp;bank, &amp;bit, &amp;offset);</div><div class='add'>+	status_addr = bank_reg(gpio, bank, EVENT_STS);</div><div class='add'>+	raw_spin_lock_irqsave(&amp;gpio-&gt;lock, flags);</div><div class='add'>+	iowrite8(BIT(bit), status_addr);</div><div class='add'>+	raw_spin_unlock_irqrestore(&amp;gpio-&gt;lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_mask(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	npcm_sgpio_irq_set_mask(d, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_unmask(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	npcm_sgpio_irq_set_mask(d, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_set_type(struct irq_data *d, unsigned int type)</div><div class='add'>+{</div><div class='add'>+	const struct npcm_sgpio_bank *bank;</div><div class='add'>+	irq_flow_handler_t handler;</div><div class='add'>+	struct npcm_sgpio *gpio;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	void __iomem *addr;</div><div class='add'>+	unsigned int offset;</div><div class='add'>+	u16 reg, val;</div><div class='add'>+	u8 bit;</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_irqd_to_data(d, &amp;gpio, &amp;bank, &amp;bit, &amp;offset);</div><div class='add'>+</div><div class='add'>+	switch (type &amp; IRQ_TYPE_SENSE_MASK) {</div><div class='add'>+	case IRQ_TYPE_EDGE_BOTH:</div><div class='add'>+		val = NPCM_IXOEVCFG_BOTH;</div><div class='add'>+		break;</div><div class='add'>+	case IRQ_TYPE_EDGE_RISING:</div><div class='add'>+	case IRQ_TYPE_LEVEL_HIGH:</div><div class='add'>+		val = NPCM_IXOEVCFG_RISING;</div><div class='add'>+		break;</div><div class='add'>+	case IRQ_TYPE_EDGE_FALLING:</div><div class='add'>+	case IRQ_TYPE_LEVEL_LOW:</div><div class='add'>+		val = NPCM_IXOEVCFG_FALLING;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (type &amp; IRQ_TYPE_LEVEL_MASK)</div><div class='add'>+		handler = handle_level_irq;</div><div class='add'>+	else</div><div class='add'>+		handler = handle_edge_irq;</div><div class='add'>+</div><div class='add'>+	gpio-&gt;int_type[offset] = val;</div><div class='add'>+</div><div class='add'>+	raw_spin_lock_irqsave(&amp;gpio-&gt;lock, flags);</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, false);</div><div class='add'>+	addr = bank_reg(gpio, bank, EVENT_CFG);</div><div class='add'>+	reg = ioread16(addr);</div><div class='add'>+</div><div class='add'>+	reg |= (val &lt;&lt; (bit * 2));</div><div class='add'>+</div><div class='add'>+	iowrite16(reg, addr);</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, true);</div><div class='add'>+	raw_spin_unlock_irqrestore(&amp;gpio-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	irq_set_handler_locked(d, handler);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void npcm_sgpio_irq_handler(struct irq_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct gpio_chip *gc = irq_desc_get_handler_data(desc);</div><div class='add'>+	struct irq_chip *ic = irq_desc_get_chip(desc);</div><div class='add'>+	struct npcm_sgpio *gpio = gpiochip_get_data(gc);</div><div class='add'>+	unsigned int i, j, girq;</div><div class='add'>+	unsigned long reg;</div><div class='add'>+</div><div class='add'>+	chained_irq_enter(ic, desc);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(npcm_sgpio_banks); i++) {</div><div class='add'>+		const struct npcm_sgpio_bank *bank = &amp;npcm_sgpio_banks[i];</div><div class='add'>+</div><div class='add'>+		reg = ioread8(bank_reg(gpio, bank, EVENT_STS));</div><div class='add'>+		for_each_set_bit(j, &amp;reg, 8) {</div><div class='add'>+			girq = irq_find_mapping(gc-&gt;irq.domain,</div><div class='add'>+						i * 8 + gpio-&gt;nout_sgpio + j);</div><div class='add'>+			generic_handle_domain_irq(gc-&gt;irq.domain, girq);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	chained_irq_exit(ic, desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct irq_chip sgpio_irq_chip = {</div><div class='add'>+	.name = "sgpio-irq",</div><div class='add'>+	.irq_ack = npcm_sgpio_irq_ack,</div><div class='add'>+	.irq_mask = npcm_sgpio_irq_mask,</div><div class='add'>+	.irq_unmask = npcm_sgpio_irq_unmask,</div><div class='add'>+	.irq_set_type = npcm_sgpio_set_type,</div><div class='add'>+	.flags	= IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,</div><div class='add'>+	GPIOCHIP_IRQ_RESOURCE_HELPERS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_setup_irqs(struct npcm_sgpio *gpio,</div><div class='add'>+				 struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	int rc, i;</div><div class='add'>+	struct gpio_irq_chip *irq;</div><div class='add'>+</div><div class='add'>+	rc = platform_get_irq(pdev, 0);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	gpio-&gt;irq = rc;</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, false);</div><div class='add'>+</div><div class='add'>+	/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(npcm_sgpio_banks); i++) {</div><div class='add'>+		const struct npcm_sgpio_bank *bank = &amp;npcm_sgpio_banks[i];</div><div class='add'>+</div><div class='add'>+		iowrite16(0, bank_reg(gpio, bank, EVENT_CFG));</div><div class='add'>+		iowrite8(0xff, bank_reg(gpio, bank, EVENT_STS));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	irq = &amp;gpio-&gt;chip.irq;</div><div class='add'>+	gpio_irq_chip_set_chip(irq, &amp;sgpio_irq_chip);</div><div class='add'>+	irq-&gt;init_valid_mask = npcm_sgpio_irq_init_valid_mask;</div><div class='add'>+	irq-&gt;handler = handle_bad_irq;</div><div class='add'>+	irq-&gt;default_type = IRQ_TYPE_NONE;</div><div class='add'>+	irq-&gt;parent_handler = npcm_sgpio_irq_handler;</div><div class='add'>+	irq-&gt;parent_handler_data = gpio;</div><div class='add'>+	irq-&gt;parents = &amp;gpio-&gt;irq;</div><div class='add'>+	irq-&gt;num_parents = 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npcm_sgpio_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct npcm_sgpio *gpio;</div><div class='add'>+	const struct npcm_clk_cfg *clk_cfg;</div><div class='add'>+	int rc;</div><div class='add'>+	u32 nin_gpios, nout_gpios;</div><div class='add'>+</div><div class='add'>+	gpio = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*gpio), GFP_KERNEL);</div><div class='add'>+	if (!gpio)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	gpio-&gt;base = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(gpio-&gt;base))</div><div class='add'>+		return PTR_ERR(gpio-&gt;base);</div><div class='add'>+</div><div class='add'>+	clk_cfg = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (!clk_cfg)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	rc = device_property_read_u32(&amp;pdev-&gt;dev, "nuvoton,input-ngpios",</div><div class='add'>+				      &amp;nin_gpios);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, rc, "Could not read ngpios property\n");</div><div class='add'>+</div><div class='add'>+	rc = device_property_read_u32(&amp;pdev-&gt;dev, "nuvoton,output-ngpios",</div><div class='add'>+				      &amp;nout_gpios);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, rc, "Could not read ngpios property\n");</div><div class='add'>+</div><div class='add'>+	gpio-&gt;nin_sgpio = nin_gpios;</div><div class='add'>+	gpio-&gt;nout_sgpio = nout_gpios;</div><div class='add'>+	if (gpio-&gt;nin_sgpio &gt; MAX_NR_HW_SGPIO ||</div><div class='add'>+	    gpio-&gt;nout_sgpio &gt; MAX_NR_HW_SGPIO)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, -EINVAL, "Number of GPIOs exceeds the maximum of %d: input: %d output: %d\n", MAX_NR_HW_SGPIO, nin_gpios, nout_gpios);</div><div class='add'>+</div><div class='add'>+	gpio-&gt;pclk = devm_clk_get(&amp;pdev-&gt;dev, NULL);</div><div class='add'>+	if (IS_ERR(gpio-&gt;pclk))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(gpio-&gt;pclk), "Could not get pclk\n");</div><div class='add'>+</div><div class='add'>+	rc = npcm_sgpio_setup_clk(gpio, clk_cfg);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, rc, "Failed to setup clock\n");</div><div class='add'>+</div><div class='add'>+	raw_spin_lock_init(&amp;gpio-&gt;lock);</div><div class='add'>+	gpio-&gt;chip.parent = &amp;pdev-&gt;dev;</div><div class='add'>+	gpio-&gt;chip.ngpio = gpio-&gt;nin_sgpio + gpio-&gt;nout_sgpio;</div><div class='add'>+	gpio-&gt;chip.direction_input = npcm_sgpio_dir_in;</div><div class='add'>+	gpio-&gt;chip.direction_output = npcm_sgpio_dir_out;</div><div class='add'>+	gpio-&gt;chip.get_direction = npcm_sgpio_get_direction;</div><div class='add'>+	gpio-&gt;chip.get = npcm_sgpio_get;</div><div class='add'>+	gpio-&gt;chip.set = npcm_sgpio_set;</div><div class='add'>+	gpio-&gt;chip.label = dev_name(&amp;pdev-&gt;dev);</div><div class='add'>+	gpio-&gt;chip.base = -1;</div><div class='add'>+</div><div class='add'>+	rc = npcm_sgpio_init_port(gpio);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rc = npcm_sgpio_setup_irqs(gpio, pdev);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rc = devm_gpiochip_add_data(&amp;pdev-&gt;dev, &amp;gpio-&gt;chip, gpio);</div><div class='add'>+	if (rc)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, rc, "GPIO registering failed\n");</div><div class='add'>+</div><div class='add'>+	npcm_sgpio_setup_enable(gpio, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int npcm750_SFT_CLK[NPCM_750_OPT] = {</div><div class='add'>+	1024, 32, 8, 4, 3, 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static unsigned int npcm750_CLK_SEL[NPCM_750_OPT] = {</div><div class='add'>+	0x00, 0x05, 0x07, 0x0C, 0x0D, 0x0E,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static unsigned int npcm845_SFT_CLK[NPCM_845_OPT] = {</div><div class='add'>+	1024, 32, 16, 8, 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static unsigned int npcm845_CLK_SEL[NPCM_845_OPT] = {</div><div class='add'>+	0x00, 0x05, 0x06, 0x07, 0x0C,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct npcm_clk_cfg npcm750_sgpio_pdata = {</div><div class='add'>+	.sft_clk = npcm750_SFT_CLK,</div><div class='add'>+	.clk_sel = npcm750_CLK_SEL,</div><div class='add'>+	.cfg_opt = NPCM_750_OPT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct npcm_clk_cfg npcm845_sgpio_pdata = {</div><div class='add'>+	.sft_clk = npcm845_SFT_CLK,</div><div class='add'>+	.clk_sel = npcm845_CLK_SEL,</div><div class='add'>+	.cfg_opt = NPCM_845_OPT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id npcm_sgpio_of_table[] = {</div><div class='add'>+	{ .compatible = "nuvoton,npcm750-sgpio", .data = &amp;npcm750_sgpio_pdata, },</div><div class='add'>+	{ .compatible = "nuvoton,npcm845-sgpio", .data = &amp;npcm845_sgpio_pdata, },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, npcm_sgpio_of_table);</div><div class='add'>+</div><div class='add'>+static struct platform_driver npcm_sgpio_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = KBUILD_MODNAME,</div><div class='add'>+		.of_match_table = npcm_sgpio_of_table,</div><div class='add'>+	},</div><div class='add'>+	.probe	= npcm_sgpio_probe,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(npcm_sgpio_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Jim Liu &lt;jjliu0@nuvoton.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Joseph Liu &lt;kwliu@nuvoton.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Nuvoton NPCM Serial GPIO Driver");</div><div class='add'>+MODULE_LICENSE("GPL v2");</div><div class='head'>diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c<br/>index 01c0fd0a9d8c..d9b228bea42e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-pmic-eic-sprd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-pmic-eic-sprd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-pmic-eic-sprd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-pmic-eic-sprd.c</a></div><div class='hunk'>@@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)</div><div class='ctx'> 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);</div><div class='ctx'> 	u32 offset = irqd_to_hwirq(data);</div><div class='ctx'> </div><div class='del'>-	pmic_eic-&gt;reg[REG_IE] = 0;</div><div class='del'>-	pmic_eic-&gt;reg[REG_TRIG] = 0;</div><div class='add'>+	pmic_eic-&gt;reg[REG_IE] &amp;= ~BIT(offset);</div><div class='add'>+	pmic_eic-&gt;reg[REG_TRIG] &amp;= ~BIT(offset);</div><div class='ctx'> </div><div class='ctx'> 	gpiochip_disable_irq(chip, offset);</div><div class='ctx'> }</div><div class='hunk'>@@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)</div><div class='ctx'> </div><div class='ctx'> 	gpiochip_enable_irq(chip, offset);</div><div class='ctx'> </div><div class='del'>-	pmic_eic-&gt;reg[REG_IE] = 1;</div><div class='del'>-	pmic_eic-&gt;reg[REG_TRIG] = 1;</div><div class='add'>+	pmic_eic-&gt;reg[REG_IE] |= BIT(offset);</div><div class='add'>+	pmic_eic-&gt;reg[REG_TRIG] |= BIT(offset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sprd_pmic_eic_irq_set_type(struct irq_data *data,</div><div class='hunk'>@@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);</div><div class='ctx'> 	struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);</div><div class='add'>+	u32 offset = irqd_to_hwirq(data);</div><div class='ctx'> </div><div class='ctx'> 	switch (flow_type) {</div><div class='ctx'> 	case IRQ_TYPE_LEVEL_HIGH:</div><div class='del'>-		pmic_eic-&gt;reg[REG_IEV] = 1;</div><div class='add'>+		pmic_eic-&gt;reg[REG_IEV] |= BIT(offset);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IRQ_TYPE_LEVEL_LOW:</div><div class='del'>-		pmic_eic-&gt;reg[REG_IEV] = 0;</div><div class='add'>+		pmic_eic-&gt;reg[REG_IEV] &amp;= ~BIT(offset);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IRQ_TYPE_EDGE_RISING:</div><div class='ctx'> 	case IRQ_TYPE_EDGE_FALLING:</div><div class='hunk'>@@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)</div><div class='ctx'> 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,</div><div class='del'>-				     pmic_eic-&gt;reg[REG_IEV]);</div><div class='add'>+				     !!(pmic_eic-&gt;reg[REG_IEV] &amp; BIT(offset)));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set irq unmask */</div><div class='ctx'> 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,</div><div class='del'>-			     pmic_eic-&gt;reg[REG_IE]);</div><div class='add'>+			     !!(pmic_eic-&gt;reg[REG_IE] &amp; BIT(offset)));</div><div class='ctx'> 	/* Generate trigger start pulse for debounce EIC */</div><div class='ctx'> 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,</div><div class='del'>-			     pmic_eic-&gt;reg[REG_TRIG]);</div><div class='add'>+			     !!(pmic_eic-&gt;reg[REG_TRIG] &amp; BIT(offset)));</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;pmic_eic-&gt;buslock);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpio/gpio-rtd.c b/drivers/gpio/gpio-rtd.c<br/>new file mode 100644<br/>index 000000000000..bf7f008f58d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-rtd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-rtd.c</a></div><div class='hunk'>@@ -0,0 +1,607 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Realtek DHC gpio driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Realtek Semiconductor Corp.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/gpio/driver.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/irqchip.h&gt;</div><div class='add'>+#include &lt;linux/irqchip/chained_irq.h&gt;</div><div class='add'>+#include &lt;linux/irqdomain.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_1US 0</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_10US 1</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_100US 2</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_1MS 3</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_10MS 4</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_20MS 5</div><div class='add'>+#define RTD_GPIO_DEBOUNCE_30MS 6</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct rtd_gpio_info - Specific GPIO register information</div><div class='add'>+ * @name: GPIO device name</div><div class='add'>+ * @gpio_base: GPIO base number</div><div class='add'>+ * @num_gpios: The number of GPIOs</div><div class='add'>+ * @dir_offset: Offset for GPIO direction registers</div><div class='add'>+ * @dato_offset: Offset for GPIO data output registers</div><div class='add'>+ * @dati_offset: Offset for GPIO data input registers</div><div class='add'>+ * @ie_offset: Offset for GPIO interrupt enable registers</div><div class='add'>+ * @dp_offset: Offset for GPIO detection polarity registers</div><div class='add'>+ * @gpa_offset: Offset for GPIO assert interrupt status registers</div><div class='add'>+ * @gpda_offset: Offset for GPIO deassert interrupt status registers</div><div class='add'>+ * @deb_offset: Offset for GPIO debounce registers</div><div class='add'>+ * @deb_val: Register values representing the GPIO debounce time</div><div class='add'>+ * @get_deb_setval: Used to get the corresponding value for setting the debounce register</div><div class='add'>+ */</div><div class='add'>+struct rtd_gpio_info {</div><div class='add'>+	const char	*name;</div><div class='add'>+	unsigned int	gpio_base;</div><div class='add'>+	unsigned int	num_gpios;</div><div class='add'>+	u8		*dir_offset;</div><div class='add'>+	u8		*dato_offset;</div><div class='add'>+	u8		*dati_offset;</div><div class='add'>+	u8		*ie_offset;</div><div class='add'>+	u8		*dp_offset;</div><div class='add'>+	u8		*gpa_offset;</div><div class='add'>+	u8		*gpda_offset;</div><div class='add'>+	u8		*deb_offset;</div><div class='add'>+	u8		*deb_val;</div><div class='add'>+	u8		(*get_deb_setval)(const struct rtd_gpio_info *info,</div><div class='add'>+					  unsigned int offset, u8 deb_index,</div><div class='add'>+					  u8 *reg_offset, u8 *shift);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct rtd_gpio {</div><div class='add'>+	struct gpio_chip		gpio_chip;</div><div class='add'>+	const struct rtd_gpio_info	*info;</div><div class='add'>+	void __iomem			*base;</div><div class='add'>+	void __iomem			*irq_base;</div><div class='add'>+	unsigned int			irqs[2];</div><div class='add'>+	raw_spinlock_t			lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u8 rtd_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset,</div><div class='add'>+				  u8 deb_index, u8 *reg_offset, u8 *shift)</div><div class='add'>+{</div><div class='add'>+	*reg_offset = info-&gt;deb_offset[offset / 8];</div><div class='add'>+	*shift = (offset % 8) * 4;</div><div class='add'>+	return info-&gt;deb_val[deb_index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u8 rtd1295_misc_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset,</div><div class='add'>+					   u8 deb_index, u8 *reg_offset, u8 *shift)</div><div class='add'>+{</div><div class='add'>+	*reg_offset = info-&gt;deb_offset[0];</div><div class='add'>+	*shift = (offset % 8) * 4;</div><div class='add'>+	return info-&gt;deb_val[deb_index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u8 rtd1295_iso_gpio_get_deb_setval(const struct rtd_gpio_info *info, unsigned int offset,</div><div class='add'>+					  u8 deb_index, u8 *reg_offset, u8 *shift)</div><div class='add'>+{</div><div class='add'>+	*reg_offset = info-&gt;deb_offset[0];</div><div class='add'>+	*shift = 0;</div><div class='add'>+	return info-&gt;deb_val[deb_index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct rtd_gpio_info rtd_iso_gpio_info = {</div><div class='add'>+	.name			= "rtd_iso_gpio",</div><div class='add'>+	.gpio_base		= 0,</div><div class='add'>+	.num_gpios		= 82,</div><div class='add'>+	.dir_offset		= (u8 []){ 0x0, 0x18, 0x2c },</div><div class='add'>+	.dato_offset		= (u8 []){ 0x4, 0x1c, 0x30 },</div><div class='add'>+	.dati_offset		= (u8 []){ 0x8, 0x20, 0x34 },</div><div class='add'>+	.ie_offset		= (u8 []){ 0xc, 0x24, 0x38 },</div><div class='add'>+	.dp_offset		= (u8 []){ 0x10, 0x28, 0x3c },</div><div class='add'>+	.gpa_offset		= (u8 []){ 0x8, 0xe0, 0x90 },</div><div class='add'>+	.gpda_offset		= (u8 []){ 0xc, 0xe4, 0x94 },</div><div class='add'>+	.deb_offset		= (u8 []){ 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c,</div><div class='add'>+					   0x60, 0x64, 0x68, 0x6c },</div><div class='add'>+	.deb_val		= (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 },</div><div class='add'>+	.get_deb_setval		= rtd_gpio_get_deb_setval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct rtd_gpio_info rtd1619_iso_gpio_info = {</div><div class='add'>+	.name			= "rtd1619_iso_gpio",</div><div class='add'>+	.gpio_base		= 0,</div><div class='add'>+	.num_gpios		= 86,</div><div class='add'>+	.dir_offset		= (u8 []){ 0x0, 0x18, 0x2c },</div><div class='add'>+	.dato_offset		= (u8 []){ 0x4, 0x1c, 0x30 },</div><div class='add'>+	.dati_offset		= (u8 []){ 0x8, 0x20, 0x34 },</div><div class='add'>+	.ie_offset		= (u8 []){ 0xc, 0x24, 0x38 },</div><div class='add'>+	.dp_offset		= (u8 []){ 0x10, 0x28, 0x3c },</div><div class='add'>+	.gpa_offset		= (u8 []){ 0x8, 0xe0, 0x90 },</div><div class='add'>+	.gpda_offset		= (u8 []){ 0xc, 0xe4, 0x94 },</div><div class='add'>+	.deb_offset		= (u8 []){ 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c,</div><div class='add'>+					   0x60, 0x64, 0x68, 0x6c },</div><div class='add'>+	.deb_val		= (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 },</div><div class='add'>+	.get_deb_setval		= rtd_gpio_get_deb_setval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct rtd_gpio_info rtd1395_iso_gpio_info = {</div><div class='add'>+	.name			= "rtd1395_iso_gpio",</div><div class='add'>+	.gpio_base		= 0,</div><div class='add'>+	.num_gpios		= 57,</div><div class='add'>+	.dir_offset		= (u8 []){ 0x0, 0x18 },</div><div class='add'>+	.dato_offset		= (u8 []){ 0x4, 0x1c },</div><div class='add'>+	.dati_offset		= (u8 []){ 0x8, 0x20 },</div><div class='add'>+	.ie_offset		= (u8 []){ 0xc, 0x24 },</div><div class='add'>+	.dp_offset		= (u8 []){ 0x10, 0x28 },</div><div class='add'>+	.gpa_offset		= (u8 []){ 0x8, 0xe0 },</div><div class='add'>+	.gpda_offset		= (u8 []){ 0xc, 0xe4 },</div><div class='add'>+	.deb_offset		= (u8 []){ 0x30, 0x34, 0x38, 0x3c, 0x40, 0x44, 0x48, 0x4c },</div><div class='add'>+	.deb_val		= (u8 []){ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6 },</div><div class='add'>+	.get_deb_setval		= rtd_gpio_get_deb_setval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct rtd_gpio_info rtd1295_misc_gpio_info = {</div><div class='add'>+	.name			= "rtd1295_misc_gpio",</div><div class='add'>+	.gpio_base		= 0,</div><div class='add'>+	.num_gpios		= 101,</div><div class='add'>+	.dir_offset		= (u8 []){ 0x0, 0x4, 0x8, 0xc },</div><div class='add'>+	.dato_offset		= (u8 []){ 0x10, 0x14, 0x18, 0x1c },</div><div class='add'>+	.dati_offset		= (u8 []){ 0x20, 0x24, 0x28, 0x2c },</div><div class='add'>+	.ie_offset		= (u8 []){ 0x30, 0x34, 0x38, 0x3c },</div><div class='add'>+	.dp_offset		= (u8 []){ 0x40, 0x44, 0x48, 0x4c },</div><div class='add'>+	.gpa_offset		= (u8 []){ 0x40, 0x44, 0xa4, 0xb8 },</div><div class='add'>+	.gpda_offset		= (u8 []){ 0x54, 0x58, 0xa8, 0xbc},</div><div class='add'>+	.deb_offset		= (u8 []){ 0x50 },</div><div class='add'>+	.deb_val		= (u8 []){ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 },</div><div class='add'>+	.get_deb_setval		= rtd1295_misc_gpio_get_deb_setval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct rtd_gpio_info rtd1295_iso_gpio_info = {</div><div class='add'>+	.name			= "rtd1295_iso_gpio",</div><div class='add'>+	.gpio_base		= 101,</div><div class='add'>+	.num_gpios		= 35,</div><div class='add'>+	.dir_offset		= (u8 []){ 0x0, 0x18 },</div><div class='add'>+	.dato_offset		= (u8 []){ 0x4, 0x1c },</div><div class='add'>+	.dati_offset		= (u8 []){ 0x8, 0x20 },</div><div class='add'>+	.ie_offset		= (u8 []){ 0xc, 0x24 },</div><div class='add'>+	.dp_offset		= (u8 []){ 0x10, 0x28 },</div><div class='add'>+	.gpa_offset		= (u8 []){ 0x8, 0xe0 },</div><div class='add'>+	.gpda_offset		= (u8 []){ 0xc, 0xe4 },</div><div class='add'>+	.deb_offset		= (u8 []){ 0x14 },</div><div class='add'>+	.deb_val		= (u8 []){ 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 },</div><div class='add'>+	.get_deb_setval		= rtd1295_iso_gpio_get_deb_setval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_dir_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return data-&gt;info-&gt;dir_offset[offset / 32];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_dato_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return data-&gt;info-&gt;dato_offset[offset / 32];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_dati_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return data-&gt;info-&gt;dati_offset[offset / 32];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_ie_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return data-&gt;info-&gt;ie_offset[offset / 32];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_dp_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return data-&gt;info-&gt;dp_offset[offset / 32];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_gpa_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	/* Each GPIO assert interrupt status register contains 31 GPIOs. */</div><div class='add'>+	return data-&gt;info-&gt;gpa_offset[offset / 31];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_gpda_offset(struct rtd_gpio *data, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	/* Each GPIO deassert interrupt status register contains 31 GPIOs. */</div><div class='add'>+	return data-&gt;info-&gt;gpda_offset[offset / 31];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,</div><div class='add'>+				   unsigned int debounce)</div><div class='add'>+{</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(chip);</div><div class='add'>+	u8 deb_val, deb_index, reg_offset, shift;</div><div class='add'>+	unsigned int write_en;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	switch (debounce) {</div><div class='add'>+	case 1:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_1US;</div><div class='add'>+		break;</div><div class='add'>+	case 10:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_10US;</div><div class='add'>+		break;</div><div class='add'>+	case 100:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_100US;</div><div class='add'>+		break;</div><div class='add'>+	case 1000:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_1MS;</div><div class='add'>+		break;</div><div class='add'>+	case 10000:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_10MS;</div><div class='add'>+		break;</div><div class='add'>+	case 20000:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_20MS;</div><div class='add'>+		break;</div><div class='add'>+	case 30000:</div><div class='add'>+		deb_index = RTD_GPIO_DEBOUNCE_30MS;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -ENOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	deb_val = data-&gt;info-&gt;get_deb_setval(data-&gt;info, offset, deb_index, &amp;reg_offset, &amp;shift);</div><div class='add'>+	write_en = BIT(shift + 3);</div><div class='add'>+	val = (deb_val &lt;&lt; shift) | write_en;</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;data-&gt;lock);</div><div class='add'>+	writel_relaxed(val, data-&gt;base + reg_offset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_set_config(struct gpio_chip *chip, unsigned int offset,</div><div class='add'>+				 unsigned long config)</div><div class='add'>+{</div><div class='add'>+	int debounce;</div><div class='add'>+</div><div class='add'>+	switch (pinconf_to_config_param(config)) {</div><div class='add'>+	case PIN_CONFIG_BIAS_DISABLE:</div><div class='add'>+	case PIN_CONFIG_BIAS_PULL_UP:</div><div class='add'>+	case PIN_CONFIG_BIAS_PULL_DOWN:</div><div class='add'>+		return gpiochip_generic_config(chip, offset, config);</div><div class='add'>+	case PIN_CONFIG_INPUT_DEBOUNCE:</div><div class='add'>+		debounce = pinconf_to_config_argument(config);</div><div class='add'>+		return rtd_gpio_set_debounce(chip, offset, debounce);</div><div class='add'>+	default:</div><div class='add'>+		return -ENOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)</div><div class='add'>+{</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(chip);</div><div class='add'>+	u32 mask = BIT(offset % 32);</div><div class='add'>+	int dato_reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	dato_reg_offset = rtd_gpio_dato_offset(data, offset);</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	val = readl_relaxed(data-&gt;base + dato_reg_offset);</div><div class='add'>+	if (value)</div><div class='add'>+		val |= mask;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~mask;</div><div class='add'>+	writel_relaxed(val, data-&gt;base + dato_reg_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_get(struct gpio_chip *chip, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(chip);</div><div class='add'>+	int dato_reg_offset = rtd_gpio_dato_offset(data, offset);</div><div class='add'>+	int dati_reg_offset = rtd_gpio_dati_offset(data, offset);</div><div class='add'>+	int dir_reg_offset = rtd_gpio_dir_offset(data, offset);</div><div class='add'>+	int dat_reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	val = readl_relaxed(data-&gt;base + dir_reg_offset);</div><div class='add'>+	dat_reg_offset = (val &amp; BIT(offset % 32)) ? dato_reg_offset : dati_reg_offset;</div><div class='add'>+	val = readl_relaxed(data-&gt;base + dat_reg_offset);</div><div class='add'>+</div><div class='add'>+	return !!(val &amp; BIT(offset % 32));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(chip);</div><div class='add'>+	int reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	reg_offset = rtd_gpio_dir_offset(data, offset);</div><div class='add'>+	val = readl_relaxed(data-&gt;base + reg_offset);</div><div class='add'>+	if (val &amp; BIT(offset % 32))</div><div class='add'>+		return GPIO_LINE_DIRECTION_OUT;</div><div class='add'>+</div><div class='add'>+	return GPIO_LINE_DIRECTION_IN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_set_direction(struct gpio_chip *chip, unsigned int offset, bool out)</div><div class='add'>+{</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(chip);</div><div class='add'>+	u32 mask = BIT(offset % 32);</div><div class='add'>+	int reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	reg_offset = rtd_gpio_dir_offset(data, offset);</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	val = readl_relaxed(data-&gt;base + reg_offset);</div><div class='add'>+	if (out)</div><div class='add'>+		val |= mask;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~mask;</div><div class='add'>+	writel_relaxed(val, data-&gt;base + reg_offset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)</div><div class='add'>+{</div><div class='add'>+	return rtd_gpio_set_direction(chip, offset, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)</div><div class='add'>+{</div><div class='add'>+	rtd_gpio_set(chip, offset, value);</div><div class='add'>+</div><div class='add'>+	return rtd_gpio_set_direction(chip, offset, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool rtd_gpio_check_ie(struct rtd_gpio *data, int irq)</div><div class='add'>+{</div><div class='add'>+	int mask = BIT(irq % 32);</div><div class='add'>+	int ie_reg_offset;</div><div class='add'>+	u32 enable;</div><div class='add'>+</div><div class='add'>+	ie_reg_offset = rtd_gpio_ie_offset(data, irq);</div><div class='add'>+	enable = readl_relaxed(data-&gt;base + ie_reg_offset);</div><div class='add'>+</div><div class='add'>+	return enable &amp; mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtd_gpio_irq_handle(struct irq_desc *desc)</div><div class='add'>+{</div><div class='add'>+	int (*get_reg_offset)(struct rtd_gpio *gpio, unsigned int offset);</div><div class='add'>+	struct rtd_gpio *data = irq_desc_get_handler_data(desc);</div><div class='add'>+	struct irq_domain *domain = data-&gt;gpio_chip.irq.domain;</div><div class='add'>+	struct irq_chip *chip = irq_desc_get_chip(desc);</div><div class='add'>+	unsigned int irq = irq_desc_get_irq(desc);</div><div class='add'>+	unsigned long status;</div><div class='add'>+	int reg_offset, i, j;</div><div class='add'>+	unsigned int hwirq;</div><div class='add'>+</div><div class='add'>+	if (irq == data-&gt;irqs[0])</div><div class='add'>+		get_reg_offset = &amp;rtd_gpio_gpa_offset;</div><div class='add'>+	else if (irq == data-&gt;irqs[1])</div><div class='add'>+		get_reg_offset = &amp;rtd_gpio_gpda_offset;</div><div class='add'>+</div><div class='add'>+	chained_irq_enter(chip, desc);</div><div class='add'>+</div><div class='add'>+	/* Each GPIO interrupt status register contains 31 GPIOs. */</div><div class='add'>+	for (i = 0; i &lt; data-&gt;info-&gt;num_gpios; i += 31) {</div><div class='add'>+		reg_offset = get_reg_offset(data, i);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Bit 0 is the write_en bit, bit 0 to 31 corresponds to 31 GPIOs.</div><div class='add'>+		 * When bit 0 is set to 0, write 1 to the other bits to clear the status.</div><div class='add'>+		 * When bit 0 is set to 1, write 1 to the other bits to set the status.</div><div class='add'>+		 */</div><div class='add'>+		status = readl_relaxed(data-&gt;irq_base + reg_offset);</div><div class='add'>+		status &amp;= ~BIT(0);</div><div class='add'>+		writel_relaxed(status, data-&gt;irq_base + reg_offset);</div><div class='add'>+</div><div class='add'>+		for_each_set_bit(j, &amp;status, 32) {</div><div class='add'>+			hwirq = i + j - 1;</div><div class='add'>+			if (rtd_gpio_check_ie(data, hwirq)) {</div><div class='add'>+				int girq = irq_find_mapping(domain, hwirq);</div><div class='add'>+				u32 irq_type = irq_get_trigger_type(girq);</div><div class='add'>+</div><div class='add'>+				if ((irq == data-&gt;irqs[1]) &amp;&amp; (irq_type != IRQ_TYPE_EDGE_BOTH))</div><div class='add'>+					break;</div><div class='add'>+				generic_handle_domain_irq(domain, hwirq);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	chained_irq_exit(chip, desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtd_gpio_enable_irq(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(gc);</div><div class='add'>+	irq_hw_number_t hwirq = irqd_to_hwirq(d);</div><div class='add'>+</div><div class='add'>+	/* Bit 0 is write_en and bit 1 to 31 is correspond to 31 GPIOs. */</div><div class='add'>+	u32 clr_mask = BIT(hwirq % 31) &lt;&lt; 1;</div><div class='add'>+</div><div class='add'>+	u32 ie_mask = BIT(hwirq % 32);</div><div class='add'>+	int gpda_reg_offset;</div><div class='add'>+	int gpa_reg_offset;</div><div class='add'>+	int ie_reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	ie_reg_offset = rtd_gpio_ie_offset(data, hwirq);</div><div class='add'>+	gpa_reg_offset = rtd_gpio_gpa_offset(data, hwirq);</div><div class='add'>+	gpda_reg_offset = rtd_gpio_gpda_offset(data, hwirq);</div><div class='add'>+</div><div class='add'>+	gpiochip_enable_irq(gc, hwirq);</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	writel_relaxed(clr_mask, data-&gt;irq_base + gpa_reg_offset);</div><div class='add'>+	writel_relaxed(clr_mask, data-&gt;irq_base + gpda_reg_offset);</div><div class='add'>+</div><div class='add'>+	val = readl_relaxed(data-&gt;base + ie_reg_offset);</div><div class='add'>+	val |= ie_mask;</div><div class='add'>+	writel_relaxed(val, data-&gt;base + ie_reg_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtd_gpio_disable_irq(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(gc);</div><div class='add'>+	irq_hw_number_t hwirq = irqd_to_hwirq(d);</div><div class='add'>+	u32 ie_mask = BIT(hwirq % 32);</div><div class='add'>+	int ie_reg_offset;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	ie_reg_offset = rtd_gpio_ie_offset(data, hwirq);</div><div class='add'>+</div><div class='add'>+	scoped_guard(raw_spinlock_irqsave, &amp;data-&gt;lock) {</div><div class='add'>+		val = readl_relaxed(data-&gt;base + ie_reg_offset);</div><div class='add'>+		val &amp;= ~ie_mask;</div><div class='add'>+		writel_relaxed(val, data-&gt;base + ie_reg_offset);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpiochip_disable_irq(gc, hwirq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_irq_set_type(struct irq_data *d, unsigned int type)</div><div class='add'>+{</div><div class='add'>+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);</div><div class='add'>+	struct rtd_gpio *data = gpiochip_get_data(gc);</div><div class='add'>+	irq_hw_number_t hwirq = irqd_to_hwirq(d);</div><div class='add'>+	u32 mask = BIT(hwirq % 32);</div><div class='add'>+	int dp_reg_offset;</div><div class='add'>+	bool polarity;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	dp_reg_offset = rtd_gpio_dp_offset(data, hwirq);</div><div class='add'>+</div><div class='add'>+	switch (type &amp; IRQ_TYPE_SENSE_MASK) {</div><div class='add'>+	case IRQ_TYPE_EDGE_RISING:</div><div class='add'>+		polarity = 1;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case IRQ_TYPE_EDGE_FALLING:</div><div class='add'>+		polarity = 0;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case IRQ_TYPE_EDGE_BOTH:</div><div class='add'>+		polarity = 1;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	scoped_guard(raw_spinlock_irqsave, &amp;data-&gt;lock) {</div><div class='add'>+		val = readl_relaxed(data-&gt;base + dp_reg_offset);</div><div class='add'>+		if (polarity)</div><div class='add'>+			val |= mask;</div><div class='add'>+		else</div><div class='add'>+			val &amp;= ~mask;</div><div class='add'>+		writel_relaxed(val, data-&gt;base + dp_reg_offset);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	irq_set_handler_locked(d, handle_simple_irq);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct irq_chip rtd_gpio_irq_chip = {</div><div class='add'>+	.name = "rtd-gpio",</div><div class='add'>+	.irq_enable = rtd_gpio_enable_irq,</div><div class='add'>+	.irq_disable = rtd_gpio_disable_irq,</div><div class='add'>+	.irq_set_type = rtd_gpio_irq_set_type,</div><div class='add'>+	.flags = IRQCHIP_IMMUTABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int rtd_gpio_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct gpio_irq_chip *irq_chip;</div><div class='add'>+	struct rtd_gpio *data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);</div><div class='add'>+	if (!data)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = platform_get_irq(pdev, 0);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	data-&gt;irqs[0] = ret;</div><div class='add'>+</div><div class='add'>+	ret = platform_get_irq(pdev, 1);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	data-&gt;irqs[1] = ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;info = device_get_match_data(dev);</div><div class='add'>+	if (!data-&gt;info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	raw_spin_lock_init(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	data-&gt;base = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(data-&gt;base))</div><div class='add'>+		return PTR_ERR(data-&gt;base);</div><div class='add'>+</div><div class='add'>+	data-&gt;irq_base = devm_platform_ioremap_resource(pdev, 1);</div><div class='add'>+	if (IS_ERR(data-&gt;irq_base))</div><div class='add'>+		return PTR_ERR(data-&gt;irq_base);</div><div class='add'>+</div><div class='add'>+	data-&gt;gpio_chip.label = dev_name(dev);</div><div class='add'>+	data-&gt;gpio_chip.base = -1;</div><div class='add'>+	data-&gt;gpio_chip.ngpio = data-&gt;info-&gt;num_gpios;</div><div class='add'>+	data-&gt;gpio_chip.request = gpiochip_generic_request;</div><div class='add'>+	data-&gt;gpio_chip.free = gpiochip_generic_free;</div><div class='add'>+	data-&gt;gpio_chip.get_direction = rtd_gpio_get_direction;</div><div class='add'>+	data-&gt;gpio_chip.direction_input = rtd_gpio_direction_input;</div><div class='add'>+	data-&gt;gpio_chip.direction_output = rtd_gpio_direction_output;</div><div class='add'>+	data-&gt;gpio_chip.set = rtd_gpio_set;</div><div class='add'>+	data-&gt;gpio_chip.get = rtd_gpio_get;</div><div class='add'>+	data-&gt;gpio_chip.set_config = rtd_gpio_set_config;</div><div class='add'>+	data-&gt;gpio_chip.parent = dev;</div><div class='add'>+</div><div class='add'>+	irq_chip = &amp;data-&gt;gpio_chip.irq;</div><div class='add'>+	irq_chip-&gt;handler = handle_bad_irq;</div><div class='add'>+	irq_chip-&gt;default_type = IRQ_TYPE_NONE;</div><div class='add'>+	irq_chip-&gt;parent_handler = rtd_gpio_irq_handle;</div><div class='add'>+	irq_chip-&gt;parent_handler_data = data;</div><div class='add'>+	irq_chip-&gt;num_parents = 2;</div><div class='add'>+	irq_chip-&gt;parents = data-&gt;irqs;</div><div class='add'>+</div><div class='add'>+	gpio_irq_chip_set_chip(irq_chip, &amp;rtd_gpio_irq_chip);</div><div class='add'>+</div><div class='add'>+	return devm_gpiochip_add_data(dev, &amp;data-&gt;gpio_chip, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id rtd_gpio_of_matches[] = {</div><div class='add'>+	{ .compatible = "realtek,rtd1295-misc-gpio", .data = &amp;rtd1295_misc_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1295-iso-gpio", .data = &amp;rtd1295_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1395-iso-gpio", .data = &amp;rtd1395_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1619-iso-gpio", .data = &amp;rtd1619_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1319-iso-gpio", .data = &amp;rtd_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1619b-iso-gpio", .data = &amp;rtd_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1319d-iso-gpio", .data = &amp;rtd_iso_gpio_info },</div><div class='add'>+	{ .compatible = "realtek,rtd1315e-iso-gpio", .data = &amp;rtd_iso_gpio_info },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, rtd_gpio_of_matches);</div><div class='add'>+</div><div class='add'>+static struct platform_driver rtd_gpio_platform_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "gpio-rtd",</div><div class='add'>+		.of_match_table = rtd_gpio_of_matches,</div><div class='add'>+	},</div><div class='add'>+	.probe = rtd_gpio_probe,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(rtd_gpio_platform_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Realtek DHC SoC gpio driver");</div><div class='add'>+MODULE_LICENSE("GPL v2");</div><div class='head'>diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c<br/>index 8decd9b5d229..067c8edb62e2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-sifive.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-sifive.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-sifive.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-sifive.c</a></div><div class='hunk'>@@ -250,7 +250,6 @@ static int sifive_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 	girq-&gt;handler = handle_bad_irq;</div><div class='ctx'> 	girq-&gt;default_type = IRQ_TYPE_NONE;</div><div class='ctx'> </div><div class='del'>-	platform_set_drvdata(pdev, chip);</div><div class='ctx'> 	return gpiochip_add_data(&amp;chip-&gt;gc, chip);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpio/gpio-sim.c b/drivers/gpio/gpio-sim.c<br/>index 1928209491e1..c4106e37e6db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-sim.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-sim.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-sim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-sim.c</a></div><div class='hunk'>@@ -20,6 +20,7 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='ctx'> #include &lt;linux/irq_sim.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/minmax.h&gt;</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='hunk'>@@ -28,6 +29,7 @@</div><div class='ctx'> #include &lt;linux/notifier.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/seq_file.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/string.h&gt;</div><div class='ctx'> #include &lt;linux/string_helpers.h&gt;</div><div class='hunk'>@@ -224,6 +226,25 @@ static void gpio_sim_free(struct gpio_chip *gc, unsigned int offset)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gpio_sim_dbg_show(struct seq_file *seq, struct gpio_chip *gc)</div><div class='add'>+{</div><div class='add'>+	struct gpio_sim_chip *chip = gpiochip_get_data(gc);</div><div class='add'>+	const char *label;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;chip-&gt;lock);</div><div class='add'>+</div><div class='add'>+	for_each_requested_gpio(gc, i, label)</div><div class='add'>+		seq_printf(seq, " gpio-%-3d (%s) %s,%s\n",</div><div class='add'>+			   gc-&gt;base + i,</div><div class='add'>+			   label,</div><div class='add'>+			   test_bit(i, chip-&gt;direction_map) ? "input" :</div><div class='add'>+				test_bit(i, chip-&gt;value_map) ? "output-high" :</div><div class='add'>+							       "output-low",</div><div class='add'>+			   test_bit(i, chip-&gt;pull_map) ? "pull-up" :</div><div class='add'>+							 "pull-down");</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t gpio_sim_sysfs_val_show(struct device *dev,</div><div class='ctx'> 				       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='hunk'>@@ -460,6 +481,7 @@ static int gpio_sim_add_bank(struct fwnode_handle *swnode, struct device *dev)</div><div class='ctx'> 	gc-&gt;to_irq = gpio_sim_to_irq;</div><div class='ctx'> 	gc-&gt;request = gpio_sim_request;</div><div class='ctx'> 	gc-&gt;free = gpio_sim_free;</div><div class='add'>+	gc-&gt;dbg_show = PTR_IF(IS_ENABLED(CONFIG_DEBUG_FS), gpio_sim_dbg_show);</div><div class='ctx'> 	gc-&gt;can_sleep = true;</div><div class='ctx'> </div><div class='ctx'> 	ret = devm_gpiochip_add_data(dev, gc, chip);</div><div class='hunk'>@@ -1546,6 +1568,6 @@ static void __exit gpio_sim_exit(void)</div><div class='ctx'> }</div><div class='ctx'> module_exit(gpio_sim_exit);</div><div class='ctx'> </div><div class='del'>-MODULE_AUTHOR("Bartosz Golaszewski &lt;brgl@bgdev.pl");</div><div class='add'>+MODULE_AUTHOR("Bartosz Golaszewski &lt;brgl@bgdev.pl&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("GPIO Simulator Module");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c<br/>index 27cc4da53565..6c5ee81d71b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-stmpe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-stmpe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-stmpe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-stmpe.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'>  * Author: Rabin Vincent &lt;rabin.vincent@stericsson.com&gt; for ST-Ericsson</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='hunk'>@@ -255,7 +256,6 @@ static void stmpe_dbg_show_one(struct seq_file *s,</div><div class='ctx'> {</div><div class='ctx'> 	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);</div><div class='ctx'> 	struct stmpe *stmpe = stmpe_gpio-&gt;stmpe;</div><div class='del'>-	const char *label = gpiochip_is_requested(gc, offset);</div><div class='ctx'> 	bool val = !!stmpe_gpio_get(gc, offset);</div><div class='ctx'> 	u8 bank = offset / 8;</div><div class='ctx'> 	u8 dir_reg = stmpe-&gt;regs[STMPE_IDX_GPDR_LSB + bank];</div><div class='hunk'>@@ -263,6 +263,10 @@ static void stmpe_dbg_show_one(struct seq_file *s,</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u8 dir;</div><div class='ctx'> </div><div class='add'>+	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);</div><div class='add'>+	if (IS_ERR(label))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	ret = stmpe_reg_read(stmpe, dir_reg);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/gpio/gpio-tangier.c b/drivers/gpio/gpio-tangier.c<br/>index 7ce3eddaed25..b75e0b12087a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tangier.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-tangier.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tangier.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tangier.c</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/export.h&gt;</div><div class='hunk'>@@ -19,6 +20,7 @@</div><div class='ctx'> #include &lt;linux/math.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pinctrl/pinconf-generic.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/string_helpers.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='hunk'>@@ -91,37 +93,31 @@ static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)</div><div class='ctx'> static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = gpiochip_get_data(chip);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *reg;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &amp;shift);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	writel(BIT(shift), reg);</div><div class='del'>-</div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = gpiochip_get_data(chip);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *gpdr;</div><div class='ctx'> 	u32 value;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &amp;shift);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	value = readl(gpdr);</div><div class='ctx'> 	value &amp;= ~BIT(shift);</div><div class='ctx'> 	writel(value, gpdr);</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -129,21 +125,18 @@ static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset</div><div class='ctx'> 				     int value)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = gpiochip_get_data(chip);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *gpdr;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	gpdr = gpio_reg_and_bit(chip, offset, GPDR, &amp;shift);</div><div class='ctx'> 	tng_gpio_set(chip, offset, value);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	value = readl(gpdr);</div><div class='ctx'> 	value |= BIT(shift);</div><div class='ctx'> 	writel(value, gpdr);</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -164,14 +157,13 @@ static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,</div><div class='ctx'> 				 unsigned int debounce)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = gpiochip_get_data(chip);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *gfbr;</div><div class='ctx'> 	u32 value;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	gfbr = gpio_reg_and_bit(chip, offset, GFBR, &amp;shift);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	value = readl(gfbr);</div><div class='ctx'> 	if (debounce)</div><div class='hunk'>@@ -180,8 +172,6 @@ static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,</div><div class='ctx'> 		value |= BIT(shift);</div><div class='ctx'> 	writel(value, gfbr);</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -207,27 +197,25 @@ static void tng_irq_ack(struct irq_data *d)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = irq_data_get_irq_chip_data(d);</div><div class='ctx'> 	irq_hw_number_t gpio = irqd_to_hwirq(d);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *gisr;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	gisr = gpio_reg_and_bit(&amp;priv-&gt;chip, gpio, GISR, &amp;shift);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	writel(BIT(shift), gisr);</div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)</div><div class='ctx'> {</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	void __iomem *gimr;</div><div class='ctx'> 	u32 value;</div><div class='ctx'> 	u8 shift;</div><div class='ctx'> </div><div class='ctx'> 	gimr = gpio_reg_and_bit(&amp;priv-&gt;chip, gpio, GIMR, &amp;shift);</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	value = readl(gimr);</div><div class='ctx'> 	if (unmask)</div><div class='hunk'>@@ -235,8 +223,6 @@ static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)</div><div class='ctx'> 	else</div><div class='ctx'> 		value &amp;= ~BIT(shift);</div><div class='ctx'> 	writel(value, gimr);</div><div class='del'>-</div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void tng_irq_mask(struct irq_data *d)</div><div class='hunk'>@@ -267,10 +253,9 @@ static int tng_irq_set_type(struct irq_data *d, unsigned int type)</div><div class='ctx'> 	void __iomem *gitr = gpio_reg(&amp;priv-&gt;chip, gpio, GITR);</div><div class='ctx'> 	void __iomem *glpr = gpio_reg(&amp;priv-&gt;chip, gpio, GLPR);</div><div class='ctx'> 	u8 shift = gpio % 32;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	u32 value;</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	value = readl(grer);</div><div class='ctx'> 	if (type &amp; IRQ_TYPE_EDGE_RISING)</div><div class='hunk'>@@ -311,8 +296,6 @@ static int tng_irq_set_type(struct irq_data *d, unsigned int type)</div><div class='ctx'> 		irq_set_handler_locked(d, handle_edge_irq);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -324,10 +307,11 @@ static int tng_irq_set_wake(struct irq_data *d, unsigned int on)</div><div class='ctx'> 	void __iomem *gwmr = gpio_reg(&amp;priv-&gt;chip, gpio, priv-&gt;wake_regs.gwmr);</div><div class='ctx'> 	void __iomem *gwsr = gpio_reg(&amp;priv-&gt;chip, gpio, priv-&gt;wake_regs.gwsr);</div><div class='ctx'> 	u8 shift = gpio % 32;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	u32 value;</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	dev_dbg(priv-&gt;dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);</div><div class='add'>+</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	/* Clear the existing wake status */</div><div class='ctx'> 	writel(BIT(shift), gwsr);</div><div class='hunk'>@@ -339,9 +323,6 @@ static int tng_irq_set_wake(struct irq_data *d, unsigned int on)</div><div class='ctx'> 		value &amp;= ~BIT(shift);</div><div class='ctx'> 	writel(value, gwmr);</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='del'>-	dev_dbg(priv-&gt;dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -477,14 +458,13 @@ int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER);</div><div class='ctx'> </div><div class='del'>-int tng_gpio_suspend(struct device *dev)</div><div class='add'>+static int tng_gpio_suspend(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = dev_get_drvdata(dev);</div><div class='ctx'> 	struct tng_gpio_context *ctx = priv-&gt;ctx;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	unsigned int base;</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	for (base = 0; base &lt; priv-&gt;chip.ngpio; base += 32, ctx++) {</div><div class='ctx'> 		/* GPLR is RO, values read will be restored using GPSR */</div><div class='hunk'>@@ -498,20 +478,16 @@ int tng_gpio_suspend(struct device *dev)</div><div class='ctx'> 		ctx-&gt;gwmr = readl(gpio_reg(&amp;priv-&gt;chip, base, priv-&gt;wake_regs.gwmr));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER);</div><div class='ctx'> </div><div class='del'>-int tng_gpio_resume(struct device *dev)</div><div class='add'>+static int tng_gpio_resume(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tng_gpio *priv = dev_get_drvdata(dev);</div><div class='ctx'> 	struct tng_gpio_context *ctx = priv-&gt;ctx;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	unsigned int base;</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+	guard(raw_spinlock_irqsave)(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	for (base = 0; base &lt; priv-&gt;chip.ngpio; base += 32, ctx++) {</div><div class='ctx'> 		/* GPLR is RO, values read will be restored using GPSR */</div><div class='hunk'>@@ -525,11 +501,10 @@ int tng_gpio_resume(struct device *dev)</div><div class='ctx'> 		writel(ctx-&gt;gwmr, gpio_reg(&amp;priv-&gt;chip, base, priv-&gt;wake_regs.gwmr));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER);</div><div class='add'>+</div><div class='add'>+EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(tng_gpio_pm_ops, tng_gpio_suspend, tng_gpio_resume, GPIO_TANGIER);</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;");</div><div class='ctx'> MODULE_AUTHOR("Pandith N &lt;pandith.n@intel.com&gt;");</div><div class='head'>diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h<br/>index 16c4f22908fb..ca7ab6cf6fa5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tangier.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-tangier.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tangier.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tangier.h</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #define _GPIO_TANGIER_H_</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/gpio/driver.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock_types.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -111,7 +112,6 @@ struct tng_gpio {</div><div class='ctx'> </div><div class='ctx'> int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio);</div><div class='ctx'> </div><div class='del'>-int tng_gpio_suspend(struct device *dev);</div><div class='del'>-int tng_gpio_resume(struct device *dev);</div><div class='add'>+extern const struct dev_pm_ops tng_gpio_pm_ops;</div><div class='ctx'> </div><div class='ctx'> #endif /* _GPIO_TANGIER_H_ */</div><div class='head'>diff --git a/drivers/gpio/gpio-tps65219.c b/drivers/gpio/gpio-tps65219.c<br/>index 7b38aa360112..cd1f17041f8c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tps65219.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-tps65219.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-tps65219.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-tps65219.c</a></div><div class='hunk'>@@ -96,16 +96,16 @@ static int tps65219_gpio_change_direction(struct gpio_chip *gc, unsigned int off</div><div class='ctx'> 	 * Below can be used for test purpose only.</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	if (IS_ENABLED(CONFIG_DEBUG_GPIO)) {</div><div class='del'>-		int ret = regmap_update_bits(gpio-&gt;tps-&gt;regmap, TPS65219_REG_MFP_1_CONFIG,</div><div class='del'>-					     TPS65219_GPIO0_DIR_MASK, direction);</div><div class='del'>-		if (ret) {</div><div class='del'>-			dev_err(dev,</div><div class='del'>-				"GPIO DEBUG enabled: Fail to change direction to %u for GPIO%d.\n",</div><div class='del'>-				direction, offset);</div><div class='del'>-			return ret;</div><div class='del'>-		}</div><div class='add'>+#if 0</div><div class='add'>+	int ret = regmap_update_bits(gpio-&gt;tps-&gt;regmap, TPS65219_REG_MFP_1_CONFIG,</div><div class='add'>+				     TPS65219_GPIO0_DIR_MASK, direction);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev,</div><div class='add'>+			"GPIO DEBUG enabled: Fail to change direction to %u for GPIO%d.\n",</div><div class='add'>+			direction, offset);</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 	dev_err(dev,</div><div class='ctx'> 		"GPIO%d direction set by NVM, change to %u failed, not allowed by specification\n",</div><div class='head'>diff --git a/drivers/gpio/gpio-wm831x.c b/drivers/gpio/gpio-wm831x.c<br/>index 7eaf8a28638c..f7d5120ff8f1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-wm831x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-wm831x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-wm831x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-wm831x.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -160,18 +161,21 @@ static void wm831x_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)</div><div class='ctx'> 	for (i = 0; i &lt; chip-&gt;ngpio; i++) {</div><div class='ctx'> 		int gpio = i + chip-&gt;base;</div><div class='ctx'> 		int reg;</div><div class='del'>-		const char *label, *pull, *powerdomain;</div><div class='add'>+		const char *pull, *powerdomain;</div><div class='ctx'> </div><div class='ctx'> 		/* We report the GPIO even if it's not requested since</div><div class='ctx'> 		 * we're also reporting things like alternate</div><div class='ctx'> 		 * functions which apply even when the GPIO is not in</div><div class='ctx'> 		 * use as a GPIO.</div><div class='ctx'> 		 */</div><div class='del'>-		label = gpiochip_is_requested(chip, i);</div><div class='del'>-		if (!label)</div><div class='del'>-			label = "Unrequested";</div><div class='add'>+		char *label __free(kfree) = gpiochip_dup_line_label(chip, i);</div><div class='add'>+		if (IS_ERR(label)) {</div><div class='add'>+			dev_err(wm831x-&gt;dev, "Failed to duplicate label\n");</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label);</div><div class='add'>+		seq_printf(s, " gpio-%-3d (%-20.20s) ",</div><div class='add'>+			   gpio, label ?: "Unrequested");</div><div class='ctx'> </div><div class='ctx'> 		reg = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i);</div><div class='ctx'> 		if (reg &lt; 0) {</div><div class='head'>diff --git a/drivers/gpio/gpio-wm8994.c b/drivers/gpio/gpio-wm8994.c<br/>index f4a474cef32d..bf05c9b5882b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-wm8994.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-wm8994.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-wm8994.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-wm8994.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -193,18 +194,20 @@ static void wm8994_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)</div><div class='ctx'> 	for (i = 0; i &lt; chip-&gt;ngpio; i++) {</div><div class='ctx'> 		int gpio = i + chip-&gt;base;</div><div class='ctx'> 		int reg;</div><div class='del'>-		const char *label;</div><div class='ctx'> </div><div class='ctx'> 		/* We report the GPIO even if it's not requested since</div><div class='ctx'> 		 * we're also reporting things like alternate</div><div class='ctx'> 		 * functions which apply even when the GPIO is not in</div><div class='ctx'> 		 * use as a GPIO.</div><div class='ctx'> 		 */</div><div class='del'>-		label = gpiochip_is_requested(chip, i);</div><div class='del'>-		if (!label)</div><div class='del'>-			label = "Unrequested";</div><div class='add'>+		char *label __free(kfree) = gpiochip_dup_line_label(chip, i);</div><div class='add'>+		if (IS_ERR(label)) {</div><div class='add'>+			dev_err(wm8994-&gt;dev, "Failed to duplicate label\n");</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio, label);</div><div class='add'>+		seq_printf(s, " gpio-%-3d (%-20.20s) ", gpio,</div><div class='add'>+			   label ?: "Unrequested");</div><div class='ctx'> </div><div class='ctx'> 		reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i);</div><div class='ctx'> 		if (reg &lt; 0) {</div><div class='head'>diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c<br/>index 823198368250..7348df385198 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-xilinx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpio-xilinx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpio-xilinx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpio-xilinx.c</a></div><div class='hunk'>@@ -52,7 +52,6 @@</div><div class='ctx'>  * @dir: GPIO direction shadow register</div><div class='ctx'>  * @gpio_lock: Lock used for synchronization</div><div class='ctx'>  * @irq: IRQ used by GPIO device</div><div class='del'>- * @irqchip: IRQ chip</div><div class='ctx'>  * @enable: GPIO IRQ enable/disable bitfield</div><div class='ctx'>  * @rising_edge: GPIO IRQ rising edge enable/disable bitfield</div><div class='ctx'>  * @falling_edge: GPIO IRQ falling edge enable/disable bitfield</div><div class='head'>diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c<br/>index 02ffda6c1e51..2a88736629ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-cdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib-cdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-cdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-cdev.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> #include &lt;linux/bitmap.h&gt;</div><div class='ctx'> #include &lt;linux/build_bug.h&gt;</div><div class='ctx'> #include &lt;linux/cdev.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/compat.h&gt;</div><div class='ctx'> #include &lt;linux/compiler.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='hunk'>@@ -19,8 +20,11 @@</div><div class='ctx'> #include &lt;linux/kfifo.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/overflow.h&gt;</div><div class='ctx'> #include &lt;linux/pinctrl/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/poll.h&gt;</div><div class='add'>+#include &lt;linux/rbtree.h&gt;</div><div class='add'>+#include &lt;linux/rwsem.h&gt;</div><div class='ctx'> #include &lt;linux/seq_file.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/timekeeping.h&gt;</div><div class='hunk'>@@ -62,45 +66,6 @@ typedef long (*ioctl_fn)(struct file *, unsigned int, unsigned long);</div><div class='ctx'> typedef ssize_t (*read_fn)(struct file *, char __user *,</div><div class='ctx'> 			   size_t count, loff_t *);</div><div class='ctx'> </div><div class='del'>-static __poll_t call_poll_locked(struct file *file,</div><div class='del'>-				 struct poll_table_struct *wait,</div><div class='del'>-				 struct gpio_device *gdev, poll_fn func)</div><div class='del'>-{</div><div class='del'>-	__poll_t ret;</div><div class='del'>-</div><div class='del'>-	down_read(&amp;gdev-&gt;sem);</div><div class='del'>-	ret = func(file, wait);</div><div class='del'>-	up_read(&amp;gdev-&gt;sem);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static long call_ioctl_locked(struct file *file, unsigned int cmd,</div><div class='del'>-			      unsigned long arg, struct gpio_device *gdev,</div><div class='del'>-			      ioctl_fn func)</div><div class='del'>-{</div><div class='del'>-	long ret;</div><div class='del'>-</div><div class='del'>-	down_read(&amp;gdev-&gt;sem);</div><div class='del'>-	ret = func(file, cmd, arg);</div><div class='del'>-	up_read(&amp;gdev-&gt;sem);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static ssize_t call_read_locked(struct file *file, char __user *buf,</div><div class='del'>-				size_t count, loff_t *f_ps,</div><div class='del'>-				struct gpio_device *gdev, read_fn func)</div><div class='del'>-{</div><div class='del'>-	ssize_t ret;</div><div class='del'>-</div><div class='del'>-	down_read(&amp;gdev-&gt;sem);</div><div class='del'>-	ret = func(file, buf, count, f_ps);</div><div class='del'>-	up_read(&amp;gdev-&gt;sem);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * GPIO line handle management</div><div class='ctx'>  */</div><div class='hunk'>@@ -235,8 +200,8 @@ static long linehandle_set_config(struct linehandle_state *lh,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linehandle_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='del'>-				      unsigned long arg)</div><div class='add'>+static long linehandle_ioctl(struct file *file, unsigned int cmd,</div><div class='add'>+			     unsigned long arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct linehandle_state *lh = file-&gt;private_data;</div><div class='ctx'> 	void __user *ip = (void __user *)arg;</div><div class='hunk'>@@ -245,6 +210,8 @@ static long linehandle_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;lh-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!lh-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -294,15 +261,6 @@ static long linehandle_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linehandle_ioctl(struct file *file, unsigned int cmd,</div><div class='del'>-			     unsigned long arg)</div><div class='del'>-{</div><div class='del'>-	struct linehandle_state *lh = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_ioctl_locked(file, cmd, arg, lh-&gt;gdev,</div><div class='del'>-				 linehandle_ioctl_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #ifdef CONFIG_COMPAT</div><div class='ctx'> static long linehandle_ioctl_compat(struct file *file, unsigned int cmd,</div><div class='ctx'> 				    unsigned long arg)</div><div class='hunk'>@@ -461,6 +419,7 @@ out_free_lh:</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct line - contains the state of a requested line</div><div class='add'>+ * @node: to store the object in supinfo_tree if supplemental</div><div class='ctx'>  * @desc: the GPIO descriptor for this line.</div><div class='ctx'>  * @req: the corresponding line request</div><div class='ctx'>  * @irq: the interrupt triggered in response to events on this GPIO</div><div class='hunk'>@@ -473,6 +432,7 @@ out_free_lh:</div><div class='ctx'>  * @line_seqno: the seqno for the current edge event in the sequence of</div><div class='ctx'>  * events for this line.</div><div class='ctx'>  * @work: the worker that implements software debouncing</div><div class='add'>+ * @debounce_period_us: the debounce period in microseconds</div><div class='ctx'>  * @sw_debounced: flag indicating if the software debouncer is active</div><div class='ctx'>  * @level: the current debounced physical level of the line</div><div class='ctx'>  * @hdesc: the Hardware Timestamp Engine (HTE) descriptor</div><div class='hunk'>@@ -481,6 +441,7 @@ out_free_lh:</div><div class='ctx'>  * @last_seqno: the last sequence number before debounce period expires</div><div class='ctx'>  */</div><div class='ctx'> struct line {</div><div class='add'>+	struct rb_node node;</div><div class='ctx'> 	struct gpio_desc *desc;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * -- edge detector specific fields --</div><div class='hunk'>@@ -515,6 +476,15 @@ struct line {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct delayed_work work;</div><div class='ctx'> 	/*</div><div class='add'>+	 * debounce_period_us is accessed by debounce_irq_handler() and</div><div class='add'>+	 * process_hw_ts() which are disabled when modified by</div><div class='add'>+	 * debounce_setup(), edge_detector_setup() or edge_detector_stop()</div><div class='add'>+	 * or can live with a stale version when updated by</div><div class='add'>+	 * edge_detector_update().</div><div class='add'>+	 * The modifying functions are themselves mutually exclusive.</div><div class='add'>+	 */</div><div class='add'>+	unsigned int debounce_period_us;</div><div class='add'>+	/*</div><div class='ctx'> 	 * sw_debounce is accessed by linereq_set_config(), which is the</div><div class='ctx'> 	 * only setter, and linereq_get_values(), which can live with a</div><div class='ctx'> 	 * slightly stale value.</div><div class='hunk'>@@ -546,6 +516,17 @@ struct line {</div><div class='ctx'> #endif /* CONFIG_HTE */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * a rbtree of the struct lines containing supplemental info.</div><div class='add'>+ * Used to populate gpio_v2_line_info with cdev specific fields not contained</div><div class='add'>+ * in the struct gpio_desc.</div><div class='add'>+ * A line is determined to contain supplemental information by</div><div class='add'>+ * line_has_supinfo().</div><div class='add'>+ */</div><div class='add'>+static struct rb_root supinfo_tree = RB_ROOT;</div><div class='add'>+/* covers supinfo_tree */</div><div class='add'>+static DEFINE_SPINLOCK(supinfo_lock);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct linereq - contains the state of a userspace line request</div><div class='ctx'>  * @gdev: the GPIO device the line request pertains to</div><div class='hunk'>@@ -559,7 +540,8 @@ struct line {</div><div class='ctx'>  * this line request.  Note that this is not used when @num_lines is 1, as</div><div class='ctx'>  * the line_seqno is then the same and is cheaper to calculate.</div><div class='ctx'>  * @config_mutex: mutex for serializing ioctl() calls to ensure consistency</div><div class='del'>- * of configuration, particularly multi-step accesses to desc flags.</div><div class='add'>+ * of configuration, particularly multi-step accesses to desc flags and</div><div class='add'>+ * changes to supinfo status.</div><div class='ctx'>  * @lines: the lines held by this line request, with @num_lines elements.</div><div class='ctx'>  */</div><div class='ctx'> struct linereq {</div><div class='hunk'>@@ -575,6 +557,103 @@ struct linereq {</div><div class='ctx'> 	struct line lines[] __counted_by(num_lines);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void supinfo_insert(struct line *line)</div><div class='add'>+{</div><div class='add'>+	struct rb_node **new = &amp;(supinfo_tree.rb_node), *parent = NULL;</div><div class='add'>+	struct line *entry;</div><div class='add'>+</div><div class='add'>+	guard(spinlock)(&amp;supinfo_lock);</div><div class='add'>+</div><div class='add'>+	while (*new) {</div><div class='add'>+		entry = container_of(*new, struct line, node);</div><div class='add'>+</div><div class='add'>+		parent = *new;</div><div class='add'>+		if (line-&gt;desc &lt; entry-&gt;desc) {</div><div class='add'>+			new = &amp;((*new)-&gt;rb_left);</div><div class='add'>+		} else if (line-&gt;desc &gt; entry-&gt;desc) {</div><div class='add'>+			new = &amp;((*new)-&gt;rb_right);</div><div class='add'>+		} else {</div><div class='add'>+			/* this should never happen */</div><div class='add'>+			WARN(1, "duplicate line inserted");</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rb_link_node(&amp;line-&gt;node, parent, new);</div><div class='add'>+	rb_insert_color(&amp;line-&gt;node, &amp;supinfo_tree);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void supinfo_erase(struct line *line)</div><div class='add'>+{</div><div class='add'>+	guard(spinlock)(&amp;supinfo_lock);</div><div class='add'>+</div><div class='add'>+	rb_erase(&amp;line-&gt;node, &amp;supinfo_tree);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct line *supinfo_find(struct gpio_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct rb_node *node = supinfo_tree.rb_node;</div><div class='add'>+	struct line *line;</div><div class='add'>+</div><div class='add'>+	while (node) {</div><div class='add'>+		line = container_of(node, struct line, node);</div><div class='add'>+		if (desc &lt; line-&gt;desc)</div><div class='add'>+			node = node-&gt;rb_left;</div><div class='add'>+		else if (desc &gt; line-&gt;desc)</div><div class='add'>+			node = node-&gt;rb_right;</div><div class='add'>+		else</div><div class='add'>+			return line;</div><div class='add'>+	}</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void supinfo_to_lineinfo(struct gpio_desc *desc,</div><div class='add'>+				struct gpio_v2_line_info *info)</div><div class='add'>+{</div><div class='add'>+	struct gpio_v2_line_attribute *attr;</div><div class='add'>+	struct line *line;</div><div class='add'>+</div><div class='add'>+	guard(spinlock)(&amp;supinfo_lock);</div><div class='add'>+</div><div class='add'>+	line = supinfo_find(desc);</div><div class='add'>+	if (!line)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	attr = &amp;info-&gt;attrs[info-&gt;num_attrs];</div><div class='add'>+	attr-&gt;id = GPIO_V2_LINE_ATTR_ID_DEBOUNCE;</div><div class='add'>+	attr-&gt;debounce_period_us = READ_ONCE(line-&gt;debounce_period_us);</div><div class='add'>+	info-&gt;num_attrs++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool line_has_supinfo(struct line *line)</div><div class='add'>+{</div><div class='add'>+	return READ_ONCE(line-&gt;debounce_period_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Checks line_has_supinfo() before and after the change to avoid unnecessary</div><div class='add'>+ * supinfo_tree access.</div><div class='add'>+ * Called indirectly by linereq_create() or linereq_set_config() so line</div><div class='add'>+ * is already protected from concurrent changes.</div><div class='add'>+ */</div><div class='add'>+static void line_set_debounce_period(struct line *line,</div><div class='add'>+				     unsigned int debounce_period_us)</div><div class='add'>+{</div><div class='add'>+	bool was_suppl = line_has_supinfo(line);</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(line-&gt;debounce_period_us, debounce_period_us);</div><div class='add'>+</div><div class='add'>+	/* if supinfo status is unchanged then we're done */</div><div class='add'>+	if (line_has_supinfo(line) == was_suppl)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* supinfo status has changed, so update the tree */</div><div class='add'>+	if (was_suppl)</div><div class='add'>+		supinfo_erase(line);</div><div class='add'>+	else</div><div class='add'>+		supinfo_insert(line);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define GPIO_V2_LINE_BIAS_FLAGS \</div><div class='ctx'> 	(GPIO_V2_LINE_FLAG_BIAS_PULL_UP | \</div><div class='ctx'> 	 GPIO_V2_LINE_FLAG_BIAS_PULL_DOWN | \</div><div class='hunk'>@@ -625,13 +704,13 @@ static void linereq_put_event(struct linereq *lr,</div><div class='ctx'> {</div><div class='ctx'> 	bool overflow = false;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;lr-&gt;wait.lock);</div><div class='del'>-	if (kfifo_is_full(&amp;lr-&gt;events)) {</div><div class='del'>-		overflow = true;</div><div class='del'>-		kfifo_skip(&amp;lr-&gt;events);</div><div class='add'>+	scoped_guard(spinlock, &amp;lr-&gt;wait.lock) {</div><div class='add'>+		if (kfifo_is_full(&amp;lr-&gt;events)) {</div><div class='add'>+			overflow = true;</div><div class='add'>+			kfifo_skip(&amp;lr-&gt;events);</div><div class='add'>+		}</div><div class='add'>+		kfifo_in(&amp;lr-&gt;events, le, 1);</div><div class='ctx'> 	}</div><div class='del'>-	kfifo_in(&amp;lr-&gt;events, le, 1);</div><div class='del'>-	spin_unlock(&amp;lr-&gt;wait.lock);</div><div class='ctx'> 	if (!overflow)</div><div class='ctx'> 		wake_up_poll(&amp;lr-&gt;wait, EPOLLIN);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -723,7 +802,7 @@ static enum hte_return process_hw_ts(struct hte_ts_data *ts, void *p)</div><div class='ctx'> 		line-&gt;total_discard_seq++;</div><div class='ctx'> 		line-&gt;last_seqno = ts-&gt;seq;</div><div class='ctx'> 		mod_delayed_work(system_wq, &amp;line-&gt;work,</div><div class='del'>-		  usecs_to_jiffies(READ_ONCE(line-&gt;desc-&gt;debounce_period_us)));</div><div class='add'>+		  usecs_to_jiffies(READ_ONCE(line-&gt;debounce_period_us)));</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (unlikely(ts-&gt;seq &lt; line-&gt;line_seqno))</div><div class='ctx'> 			return HTE_CB_HANDLED;</div><div class='hunk'>@@ -864,7 +943,7 @@ static irqreturn_t debounce_irq_handler(int irq, void *p)</div><div class='ctx'> 	struct line *line = p;</div><div class='ctx'> </div><div class='ctx'> 	mod_delayed_work(system_wq, &amp;line-&gt;work,</div><div class='del'>-		usecs_to_jiffies(READ_ONCE(line-&gt;desc-&gt;debounce_period_us)));</div><div class='add'>+		usecs_to_jiffies(READ_ONCE(line-&gt;debounce_period_us)));</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='hunk'>@@ -946,7 +1025,7 @@ static int debounce_setup(struct line *line, unsigned int debounce_period_us)</div><div class='ctx'> 	/* try hardware */</div><div class='ctx'> 	ret = gpiod_set_debounce(line-&gt;desc, debounce_period_us);</div><div class='ctx'> 	if (!ret) {</div><div class='del'>-		WRITE_ONCE(line-&gt;desc-&gt;debounce_period_us, debounce_period_us);</div><div class='add'>+		line_set_debounce_period(line, debounce_period_us);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ret != -ENOTSUPP)</div><div class='hunk'>@@ -1025,8 +1104,7 @@ static void edge_detector_stop(struct line *line)</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;line-&gt;work);</div><div class='ctx'> 	WRITE_ONCE(line-&gt;sw_debounced, 0);</div><div class='ctx'> 	WRITE_ONCE(line-&gt;edflags, 0);</div><div class='del'>-	if (line-&gt;desc)</div><div class='del'>-		WRITE_ONCE(line-&gt;desc-&gt;debounce_period_us, 0);</div><div class='add'>+	line_set_debounce_period(line, 0);</div><div class='ctx'> 	/* do not change line-&gt;level - see comment in debounced_value() */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1051,7 +1129,7 @@ static int edge_detector_setup(struct line *line,</div><div class='ctx'> 		ret = debounce_setup(line, debounce_period_us);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='del'>-		WRITE_ONCE(line-&gt;desc-&gt;debounce_period_us, debounce_period_us);</div><div class='add'>+		line_set_debounce_period(line, debounce_period_us);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* detection disabled or sw debouncer will provide edge detection */</div><div class='hunk'>@@ -1093,12 +1171,12 @@ static int edge_detector_update(struct line *line,</div><div class='ctx'> 			gpio_v2_line_config_debounce_period(lc, line_idx);</div><div class='ctx'> </div><div class='ctx'> 	if ((active_edflags == edflags) &amp;&amp;</div><div class='del'>-	    (READ_ONCE(line-&gt;desc-&gt;debounce_period_us) == debounce_period_us))</div><div class='add'>+	    (READ_ONCE(line-&gt;debounce_period_us) == debounce_period_us))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* sw debounced and still will be...*/</div><div class='ctx'> 	if (debounce_period_us &amp;&amp; READ_ONCE(line-&gt;sw_debounced)) {</div><div class='del'>-		WRITE_ONCE(line-&gt;desc-&gt;debounce_period_us, debounce_period_us);</div><div class='add'>+		line_set_debounce_period(line, debounce_period_us);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1272,9 +1350,18 @@ static long linereq_get_values(struct linereq *lr, void __user *ip)</div><div class='ctx'> 	if (copy_from_user(&amp;lv, ip, sizeof(lv)))</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * gpiod_get_array_value_complex() requires compacted desc and val</div><div class='add'>+	 * arrays, rather than the sparse ones in lv.</div><div class='add'>+	 * Calculation of num_get and construction of the desc array is</div><div class='add'>+	 * optimized to avoid allocation for the desc array for the common</div><div class='add'>+	 * num_get == 1 case.</div><div class='add'>+	 */</div><div class='add'>+	/* scan requested lines to calculate the subset to get */</div><div class='ctx'> 	for (num_get = 0, i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='ctx'> 		if (lv.mask &amp; BIT_ULL(i)) {</div><div class='ctx'> 			num_get++;</div><div class='add'>+			/* capture desc for the num_get == 1 case */</div><div class='ctx'> 			descs = &amp;lr-&gt;lines[i].desc;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1283,6 +1370,7 @@ static long linereq_get_values(struct linereq *lr, void __user *ip)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (num_get != 1) {</div><div class='add'>+		/* build compacted desc array */</div><div class='ctx'> 		descs = kmalloc_array(num_get, sizeof(*descs), GFP_KERNEL);</div><div class='ctx'> 		if (!descs)</div><div class='ctx'> 			return -ENOMEM;</div><div class='hunk'>@@ -1303,6 +1391,7 @@ static long linereq_get_values(struct linereq *lr, void __user *ip)</div><div class='ctx'> </div><div class='ctx'> 	lv.bits = 0;</div><div class='ctx'> 	for (didx = 0, i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='add'>+		/* unpack compacted vals for the response */</div><div class='ctx'> 		if (lv.mask &amp; BIT_ULL(i)) {</div><div class='ctx'> 			if (lr-&gt;lines[i].sw_debounced)</div><div class='ctx'> 				val = debounced_value(&amp;lr-&gt;lines[i]);</div><div class='hunk'>@@ -1320,22 +1409,38 @@ static long linereq_get_values(struct linereq *lr, void __user *ip)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linereq_set_values_unlocked(struct linereq *lr,</div><div class='del'>-					struct gpio_v2_line_values *lv)</div><div class='add'>+static long linereq_set_values(struct linereq *lr, void __user *ip)</div><div class='ctx'> {</div><div class='ctx'> 	DECLARE_BITMAP(vals, GPIO_V2_LINES_MAX);</div><div class='add'>+	struct gpio_v2_line_values lv;</div><div class='ctx'> 	struct gpio_desc **descs;</div><div class='ctx'> 	unsigned int i, didx, num_set;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (copy_from_user(&amp;lv, ip, sizeof(lv)))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;lr-&gt;config_mutex);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * gpiod_set_array_value_complex() requires compacted desc and val</div><div class='add'>+	 * arrays, rather than the sparse ones in lv.</div><div class='add'>+	 * Calculation of num_set and construction of the descs and vals arrays</div><div class='add'>+	 * is optimized to minimize scanning the lv-&gt;mask, and to avoid</div><div class='add'>+	 * allocation for the desc array for the common num_set == 1 case.</div><div class='add'>+	 */</div><div class='ctx'> 	bitmap_zero(vals, GPIO_V2_LINES_MAX);</div><div class='add'>+	/* scan requested lines to determine the subset to be set */</div><div class='ctx'> 	for (num_set = 0, i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='del'>-		if (lv-&gt;mask &amp; BIT_ULL(i)) {</div><div class='add'>+		if (lv.mask &amp; BIT_ULL(i)) {</div><div class='add'>+			/* setting inputs is not allowed */</div><div class='ctx'> 			if (!test_bit(FLAG_IS_OUT, &amp;lr-&gt;lines[i].desc-&gt;flags))</div><div class='ctx'> 				return -EPERM;</div><div class='del'>-			if (lv-&gt;bits &amp; BIT_ULL(i))</div><div class='add'>+			/* add to compacted values */</div><div class='add'>+			if (lv.bits &amp; BIT_ULL(i))</div><div class='ctx'> 				__set_bit(num_set, vals);</div><div class='ctx'> 			num_set++;</div><div class='add'>+			/* capture desc for the num_set == 1 case */</div><div class='ctx'> 			descs = &amp;lr-&gt;lines[i].desc;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1343,12 +1448,12 @@ static long linereq_set_values_unlocked(struct linereq *lr,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (num_set != 1) {</div><div class='del'>-		/* build compacted desc array and values */</div><div class='add'>+		/* build compacted desc array */</div><div class='ctx'> 		descs = kmalloc_array(num_set, sizeof(*descs), GFP_KERNEL);</div><div class='ctx'> 		if (!descs)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		for (didx = 0, i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='del'>-			if (lv-&gt;mask &amp; BIT_ULL(i)) {</div><div class='add'>+			if (lv.mask &amp; BIT_ULL(i)) {</div><div class='ctx'> 				descs[didx] = lr-&gt;lines[i].desc;</div><div class='ctx'> 				didx++;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1362,36 +1467,28 @@ static long linereq_set_values_unlocked(struct linereq *lr,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linereq_set_values(struct linereq *lr, void __user *ip)</div><div class='del'>-{</div><div class='del'>-	struct gpio_v2_line_values lv;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (copy_from_user(&amp;lv, ip, sizeof(lv)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;lr-&gt;config_mutex);</div><div class='del'>-</div><div class='del'>-	ret = linereq_set_values_unlocked(lr, &amp;lv);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;lr-&gt;config_mutex);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static long linereq_set_config_unlocked(struct linereq *lr,</div><div class='del'>-					struct gpio_v2_line_config *lc)</div><div class='add'>+static long linereq_set_config(struct linereq *lr, void __user *ip)</div><div class='ctx'> {</div><div class='add'>+	struct gpio_v2_line_config lc;</div><div class='ctx'> 	struct gpio_desc *desc;</div><div class='ctx'> 	struct line *line;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	u64 flags, edflags;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (copy_from_user(&amp;lc, ip, sizeof(lc)))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	ret = gpio_v2_line_config_validate(&amp;lc, lr-&gt;num_lines);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;lr-&gt;config_mutex);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='ctx'> 		line = &amp;lr-&gt;lines[i];</div><div class='ctx'> 		desc = lr-&gt;lines[i].desc;</div><div class='del'>-		flags = gpio_v2_line_config_flags(lc, i);</div><div class='add'>+		flags = gpio_v2_line_config_flags(&amp;lc, i);</div><div class='ctx'> 		gpio_v2_line_config_flags_to_desc_flags(flags, &amp;desc-&gt;flags);</div><div class='ctx'> 		edflags = flags &amp; GPIO_V2_LINE_EDGE_DETECTOR_FLAGS;</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -1399,7 +1496,7 @@ static long linereq_set_config_unlocked(struct linereq *lr,</div><div class='ctx'> 		 * or output, else the line will be treated "as is".</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (flags &amp; GPIO_V2_LINE_FLAG_OUTPUT) {</div><div class='del'>-			int val = gpio_v2_line_config_output_value(lc, i);</div><div class='add'>+			int val = gpio_v2_line_config_output_value(&amp;lc, i);</div><div class='ctx'> </div><div class='ctx'> 			edge_detector_stop(line);</div><div class='ctx'> 			ret = gpiod_direction_output(desc, val);</div><div class='hunk'>@@ -1410,7 +1507,7 @@ static long linereq_set_config_unlocked(struct linereq *lr,</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='del'>-			ret = edge_detector_update(line, lc, i, edflags);</div><div class='add'>+			ret = edge_detector_update(line, &amp;lc, i, edflags);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1422,33 +1519,14 @@ static long linereq_set_config_unlocked(struct linereq *lr,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linereq_set_config(struct linereq *lr, void __user *ip)</div><div class='del'>-{</div><div class='del'>-	struct gpio_v2_line_config lc;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (copy_from_user(&amp;lc, ip, sizeof(lc)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	ret = gpio_v2_line_config_validate(&amp;lc, lr-&gt;num_lines);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;lr-&gt;config_mutex);</div><div class='del'>-</div><div class='del'>-	ret = linereq_set_config_unlocked(lr, &amp;lc);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;lr-&gt;config_mutex);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static long linereq_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='del'>-				   unsigned long arg)</div><div class='add'>+static long linereq_ioctl(struct file *file, unsigned int cmd,</div><div class='add'>+			  unsigned long arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct linereq *lr = file-&gt;private_data;</div><div class='ctx'> 	void __user *ip = (void __user *)arg;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;lr-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!lr-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -1464,15 +1542,6 @@ static long linereq_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long linereq_ioctl(struct file *file, unsigned int cmd,</div><div class='del'>-			  unsigned long arg)</div><div class='del'>-{</div><div class='del'>-	struct linereq *lr = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_ioctl_locked(file, cmd, arg, lr-&gt;gdev,</div><div class='del'>-				 linereq_ioctl_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #ifdef CONFIG_COMPAT</div><div class='ctx'> static long linereq_ioctl_compat(struct file *file, unsigned int cmd,</div><div class='ctx'> 				 unsigned long arg)</div><div class='hunk'>@@ -1481,12 +1550,14 @@ static long linereq_ioctl_compat(struct file *file, unsigned int cmd,</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-static __poll_t linereq_poll_unlocked(struct file *file,</div><div class='del'>-				      struct poll_table_struct *wait)</div><div class='add'>+static __poll_t linereq_poll(struct file *file,</div><div class='add'>+			     struct poll_table_struct *wait)</div><div class='ctx'> {</div><div class='ctx'> 	struct linereq *lr = file-&gt;private_data;</div><div class='ctx'> 	__poll_t events = 0;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;lr-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!lr-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return EPOLLHUP | EPOLLERR;</div><div class='ctx'> </div><div class='hunk'>@@ -1499,22 +1570,16 @@ static __poll_t linereq_poll_unlocked(struct file *file,</div><div class='ctx'> 	return events;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __poll_t linereq_poll(struct file *file,</div><div class='del'>-			     struct poll_table_struct *wait)</div><div class='del'>-{</div><div class='del'>-	struct linereq *lr = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_poll_locked(file, wait, lr-&gt;gdev, linereq_poll_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static ssize_t linereq_read_unlocked(struct file *file, char __user *buf,</div><div class='del'>-				     size_t count, loff_t *f_ps)</div><div class='add'>+static ssize_t linereq_read(struct file *file, char __user *buf,</div><div class='add'>+			    size_t count, loff_t *f_ps)</div><div class='ctx'> {</div><div class='ctx'> 	struct linereq *lr = file-&gt;private_data;</div><div class='ctx'> 	struct gpio_v2_line_event le;</div><div class='ctx'> 	ssize_t bytes_read = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;lr-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!lr-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -1522,28 +1587,22 @@ static ssize_t linereq_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		spin_lock(&amp;lr-&gt;wait.lock);</div><div class='del'>-		if (kfifo_is_empty(&amp;lr-&gt;events)) {</div><div class='del'>-			if (bytes_read) {</div><div class='del'>-				spin_unlock(&amp;lr-&gt;wait.lock);</div><div class='del'>-				return bytes_read;</div><div class='add'>+		scoped_guard(spinlock, &amp;lr-&gt;wait.lock) {</div><div class='add'>+			if (kfifo_is_empty(&amp;lr-&gt;events)) {</div><div class='add'>+				if (bytes_read)</div><div class='add'>+					return bytes_read;</div><div class='add'>+</div><div class='add'>+				if (file-&gt;f_flags &amp; O_NONBLOCK)</div><div class='add'>+					return -EAGAIN;</div><div class='add'>+</div><div class='add'>+				ret = wait_event_interruptible_locked(lr-&gt;wait,</div><div class='add'>+						!kfifo_is_empty(&amp;lr-&gt;events));</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			if (file-&gt;f_flags &amp; O_NONBLOCK) {</div><div class='del'>-				spin_unlock(&amp;lr-&gt;wait.lock);</div><div class='del'>-				return -EAGAIN;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			ret = wait_event_interruptible_locked(lr-&gt;wait,</div><div class='del'>-					!kfifo_is_empty(&amp;lr-&gt;events));</div><div class='del'>-			if (ret) {</div><div class='del'>-				spin_unlock(&amp;lr-&gt;wait.lock);</div><div class='del'>-				return ret;</div><div class='del'>-			}</div><div class='add'>+			ret = kfifo_out(&amp;lr-&gt;events, &amp;le, 1);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		ret = kfifo_out(&amp;lr-&gt;events, &amp;le, 1);</div><div class='del'>-		spin_unlock(&amp;lr-&gt;wait.lock);</div><div class='ctx'> 		if (ret != 1) {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * This should never happen - we were holding the</div><div class='hunk'>@@ -1562,17 +1621,9 @@ static ssize_t linereq_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 	return bytes_read;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static ssize_t linereq_read(struct file *file, char __user *buf,</div><div class='del'>-			    size_t count, loff_t *f_ps)</div><div class='del'>-{</div><div class='del'>-	struct linereq *lr = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_read_locked(file, buf, count, f_ps, lr-&gt;gdev,</div><div class='del'>-				linereq_read_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void linereq_free(struct linereq *lr)</div><div class='ctx'> {</div><div class='add'>+	struct line *line;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	if (lr-&gt;device_unregistered_nb.notifier_call)</div><div class='hunk'>@@ -1580,15 +1631,19 @@ static void linereq_free(struct linereq *lr)</div><div class='ctx'> 						   &amp;lr-&gt;device_unregistered_nb);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; lr-&gt;num_lines; i++) {</div><div class='del'>-		if (lr-&gt;lines[i].desc) {</div><div class='del'>-			edge_detector_stop(&amp;lr-&gt;lines[i]);</div><div class='del'>-			gpiod_free(lr-&gt;lines[i].desc);</div><div class='del'>-		}</div><div class='add'>+		line = &amp;lr-&gt;lines[i];</div><div class='add'>+		if (!line-&gt;desc)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		edge_detector_stop(line);</div><div class='add'>+		if (line_has_supinfo(line))</div><div class='add'>+			supinfo_erase(line);</div><div class='add'>+		gpiod_free(line-&gt;desc);</div><div class='ctx'> 	}</div><div class='ctx'> 	kfifo_free(&amp;lr-&gt;events);</div><div class='ctx'> 	kfree(lr-&gt;label);</div><div class='ctx'> 	gpio_device_put(lr-&gt;gdev);</div><div class='del'>-	kfree(lr);</div><div class='add'>+	kvfree(lr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int linereq_release(struct inode *inode, struct file *file)</div><div class='hunk'>@@ -1653,7 +1708,7 @@ static int linereq_create(struct gpio_device *gdev, void __user *ip)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	lr = kzalloc(struct_size(lr, lines, ulr.num_lines), GFP_KERNEL);</div><div class='add'>+	lr = kvzalloc(struct_size(lr, lines, ulr.num_lines), GFP_KERNEL);</div><div class='ctx'> 	if (!lr)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	lr-&gt;num_lines = ulr.num_lines;</div><div class='hunk'>@@ -1818,12 +1873,14 @@ struct lineevent_state {</div><div class='ctx'> 	(GPIOEVENT_REQUEST_RISING_EDGE | \</div><div class='ctx'> 	GPIOEVENT_REQUEST_FALLING_EDGE)</div><div class='ctx'> </div><div class='del'>-static __poll_t lineevent_poll_unlocked(struct file *file,</div><div class='del'>-					struct poll_table_struct *wait)</div><div class='add'>+static __poll_t lineevent_poll(struct file *file,</div><div class='add'>+			       struct poll_table_struct *wait)</div><div class='ctx'> {</div><div class='ctx'> 	struct lineevent_state *le = file-&gt;private_data;</div><div class='ctx'> 	__poll_t events = 0;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;le-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!le-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return EPOLLHUP | EPOLLERR;</div><div class='ctx'> </div><div class='hunk'>@@ -1835,14 +1892,6 @@ static __poll_t lineevent_poll_unlocked(struct file *file,</div><div class='ctx'> 	return events;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __poll_t lineevent_poll(struct file *file,</div><div class='del'>-			       struct poll_table_struct *wait)</div><div class='del'>-{</div><div class='del'>-	struct lineevent_state *le = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_poll_locked(file, wait, le-&gt;gdev, lineevent_poll_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int lineevent_unregistered_notify(struct notifier_block *nb,</div><div class='ctx'> 					 unsigned long action, void *data)</div><div class='ctx'> {</div><div class='hunk'>@@ -1859,8 +1908,8 @@ struct compat_gpioeevent_data {</div><div class='ctx'> 	u32		id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static ssize_t lineevent_read_unlocked(struct file *file, char __user *buf,</div><div class='del'>-				       size_t count, loff_t *f_ps)</div><div class='add'>+static ssize_t lineevent_read(struct file *file, char __user *buf,</div><div class='add'>+			      size_t count, loff_t *f_ps)</div><div class='ctx'> {</div><div class='ctx'> 	struct lineevent_state *le = file-&gt;private_data;</div><div class='ctx'> 	struct gpioevent_data ge;</div><div class='hunk'>@@ -1868,6 +1917,8 @@ static ssize_t lineevent_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 	ssize_t ge_size;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;le-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!le-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -1888,28 +1939,22 @@ static ssize_t lineevent_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		spin_lock(&amp;le-&gt;wait.lock);</div><div class='del'>-		if (kfifo_is_empty(&amp;le-&gt;events)) {</div><div class='del'>-			if (bytes_read) {</div><div class='del'>-				spin_unlock(&amp;le-&gt;wait.lock);</div><div class='del'>-				return bytes_read;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (file-&gt;f_flags &amp; O_NONBLOCK) {</div><div class='del'>-				spin_unlock(&amp;le-&gt;wait.lock);</div><div class='del'>-				return -EAGAIN;</div><div class='add'>+		scoped_guard(spinlock, &amp;le-&gt;wait.lock) {</div><div class='add'>+			if (kfifo_is_empty(&amp;le-&gt;events)) {</div><div class='add'>+				if (bytes_read)</div><div class='add'>+					return bytes_read;</div><div class='add'>+</div><div class='add'>+				if (file-&gt;f_flags &amp; O_NONBLOCK)</div><div class='add'>+					return -EAGAIN;</div><div class='add'>+</div><div class='add'>+				ret = wait_event_interruptible_locked(le-&gt;wait,</div><div class='add'>+						!kfifo_is_empty(&amp;le-&gt;events));</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			ret = wait_event_interruptible_locked(le-&gt;wait,</div><div class='del'>-					!kfifo_is_empty(&amp;le-&gt;events));</div><div class='del'>-			if (ret) {</div><div class='del'>-				spin_unlock(&amp;le-&gt;wait.lock);</div><div class='del'>-				return ret;</div><div class='del'>-			}</div><div class='add'>+			ret = kfifo_out(&amp;le-&gt;events, &amp;ge, 1);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		ret = kfifo_out(&amp;le-&gt;events, &amp;ge, 1);</div><div class='del'>-		spin_unlock(&amp;le-&gt;wait.lock);</div><div class='ctx'> 		if (ret != 1) {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * This should never happen - we were holding the lock</div><div class='hunk'>@@ -1928,15 +1973,6 @@ static ssize_t lineevent_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 	return bytes_read;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static ssize_t lineevent_read(struct file *file, char __user *buf,</div><div class='del'>-			      size_t count, loff_t *f_ps)</div><div class='del'>-{</div><div class='del'>-	struct lineevent_state *le = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_read_locked(file, buf, count, f_ps, le-&gt;gdev,</div><div class='del'>-				lineevent_read_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void lineevent_free(struct lineevent_state *le)</div><div class='ctx'> {</div><div class='ctx'> 	if (le-&gt;device_unregistered_nb.notifier_call)</div><div class='hunk'>@@ -1957,13 +1993,15 @@ static int lineevent_release(struct inode *inode, struct file *file)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long lineevent_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='del'>-				     unsigned long arg)</div><div class='add'>+static long lineevent_ioctl(struct file *file, unsigned int cmd,</div><div class='add'>+			    unsigned long arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct lineevent_state *le = file-&gt;private_data;</div><div class='ctx'> 	void __user *ip = (void __user *)arg;</div><div class='ctx'> 	struct gpiohandle_data ghd;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;le-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!le-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -1989,15 +2027,6 @@ static long lineevent_ioctl_unlocked(struct file *file, unsigned int cmd,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static long lineevent_ioctl(struct file *file, unsigned int cmd,</div><div class='del'>-			    unsigned long arg)</div><div class='del'>-{</div><div class='del'>-	struct lineevent_state *le = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_ioctl_locked(file, cmd, arg, le-&gt;gdev,</div><div class='del'>-				 lineevent_ioctl_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #ifdef CONFIG_COMPAT</div><div class='ctx'> static long lineevent_ioctl_compat(struct file *file, unsigned int cmd,</div><div class='ctx'> 				   unsigned long arg)</div><div class='hunk'>@@ -2272,84 +2301,72 @@ static void gpio_desc_to_lineinfo(struct gpio_desc *desc,</div><div class='ctx'> 				  struct gpio_v2_line_info *info)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chip *gc = desc-&gt;gdev-&gt;chip;</div><div class='del'>-	bool ok_for_pinctrl;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	u32 debounce_period_us;</div><div class='del'>-	unsigned int num_attrs = 0;</div><div class='add'>+	unsigned long dflags;</div><div class='ctx'> </div><div class='ctx'> 	memset(info, 0, sizeof(*info));</div><div class='ctx'> 	info-&gt;offset = gpio_chip_hwgpio(desc);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * This function takes a mutex so we must check this before taking</div><div class='del'>-	 * the spinlock.</div><div class='del'>-	 *</div><div class='del'>-	 * FIXME: find a non-racy way to retrieve this information. Maybe a</div><div class='del'>-	 * lock common to both frameworks?</div><div class='del'>-	 */</div><div class='del'>-	ok_for_pinctrl = pinctrl_gpio_can_use_line(gc, info-&gt;offset);</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;gpio_lock, flags);</div><div class='add'>+	scoped_guard(spinlock_irqsave, &amp;gpio_lock) {</div><div class='add'>+		if (desc-&gt;name)</div><div class='add'>+			strscpy(info-&gt;name, desc-&gt;name, sizeof(info-&gt;name));</div><div class='ctx'> </div><div class='del'>-	if (desc-&gt;name)</div><div class='del'>-		strscpy(info-&gt;name, desc-&gt;name, sizeof(info-&gt;name));</div><div class='add'>+		if (desc-&gt;label)</div><div class='add'>+			strscpy(info-&gt;consumer, desc-&gt;label,</div><div class='add'>+				sizeof(info-&gt;consumer));</div><div class='ctx'> </div><div class='del'>-	if (desc-&gt;label)</div><div class='del'>-		strscpy(info-&gt;consumer, desc-&gt;label, sizeof(info-&gt;consumer));</div><div class='add'>+		dflags = READ_ONCE(desc-&gt;flags);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Userspace only need to know that the kernel is using this GPIO so</div><div class='del'>-	 * it can't use it.</div><div class='add'>+	 * Userspace only need know that the kernel is using this GPIO so it</div><div class='add'>+	 * can't use it.</div><div class='add'>+	 * The calculation of the used flag is slightly racy, as it may read</div><div class='add'>+	 * desc, gc and pinctrl state without a lock covering all three at</div><div class='add'>+	 * once.  Worst case if the line is in transition and the calculation</div><div class='add'>+	 * is inconsistent then it looks to the user like they performed the</div><div class='add'>+	 * read on the other side of the transition - but that can always</div><div class='add'>+	 * happen.</div><div class='add'>+	 * The definitive test that a line is available to userspace is to</div><div class='add'>+	 * request it.</div><div class='ctx'> 	 */</div><div class='del'>-	info-&gt;flags = 0;</div><div class='del'>-	if (test_bit(FLAG_REQUESTED, &amp;desc-&gt;flags) ||</div><div class='del'>-	    test_bit(FLAG_IS_HOGGED, &amp;desc-&gt;flags) ||</div><div class='del'>-	    test_bit(FLAG_USED_AS_IRQ, &amp;desc-&gt;flags) ||</div><div class='del'>-	    test_bit(FLAG_EXPORT, &amp;desc-&gt;flags) ||</div><div class='del'>-	    test_bit(FLAG_SYSFS, &amp;desc-&gt;flags) ||</div><div class='add'>+	if (test_bit(FLAG_REQUESTED, &amp;dflags) ||</div><div class='add'>+	    test_bit(FLAG_IS_HOGGED, &amp;dflags) ||</div><div class='add'>+	    test_bit(FLAG_USED_AS_IRQ, &amp;dflags) ||</div><div class='add'>+	    test_bit(FLAG_EXPORT, &amp;dflags) ||</div><div class='add'>+	    test_bit(FLAG_SYSFS, &amp;dflags) ||</div><div class='ctx'> 	    !gpiochip_line_is_valid(gc, info-&gt;offset) ||</div><div class='del'>-	    !ok_for_pinctrl)</div><div class='add'>+	    !pinctrl_gpio_can_use_line(gc, info-&gt;offset))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_USED;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_IS_OUT, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_IS_OUT, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_OUTPUT;</div><div class='ctx'> 	else</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_INPUT;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_ACTIVE_LOW, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_ACTIVE_LOW, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_ACTIVE_LOW;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_OPEN_DRAIN, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_OPEN_DRAIN, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_OPEN_DRAIN;</div><div class='del'>-	if (test_bit(FLAG_OPEN_SOURCE, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_OPEN_SOURCE, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_OPEN_SOURCE;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_BIAS_DISABLE, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_BIAS_DISABLE, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_BIAS_DISABLED;</div><div class='del'>-	if (test_bit(FLAG_PULL_DOWN, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_PULL_DOWN, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_BIAS_PULL_DOWN;</div><div class='del'>-	if (test_bit(FLAG_PULL_UP, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_PULL_UP, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_BIAS_PULL_UP;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_EDGE_RISING, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_EDGE_RISING, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_EDGE_RISING;</div><div class='del'>-	if (test_bit(FLAG_EDGE_FALLING, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_EDGE_FALLING, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_EDGE_FALLING;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_EVENT_CLOCK_REALTIME, &amp;desc-&gt;flags))</div><div class='add'>+	if (test_bit(FLAG_EVENT_CLOCK_REALTIME, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME;</div><div class='del'>-	else if (test_bit(FLAG_EVENT_CLOCK_HTE, &amp;desc-&gt;flags))</div><div class='add'>+	else if (test_bit(FLAG_EVENT_CLOCK_HTE, &amp;dflags))</div><div class='ctx'> 		info-&gt;flags |= GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE;</div><div class='del'>-</div><div class='del'>-	debounce_period_us = READ_ONCE(desc-&gt;debounce_period_us);</div><div class='del'>-	if (debounce_period_us) {</div><div class='del'>-		info-&gt;attrs[num_attrs].id = GPIO_V2_LINE_ATTR_ID_DEBOUNCE;</div><div class='del'>-		info-&gt;attrs[num_attrs].debounce_period_us = debounce_period_us;</div><div class='del'>-		num_attrs++;</div><div class='del'>-	}</div><div class='del'>-	info-&gt;num_attrs = num_attrs;</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;gpio_lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct gpio_chardev_data {</div><div class='hunk'>@@ -2455,6 +2472,7 @@ static int lineinfo_get(struct gpio_chardev_data *cdev, void __user *ip,</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> 	gpio_desc_to_lineinfo(desc, &amp;lineinfo);</div><div class='add'>+	supinfo_to_lineinfo(desc, &amp;lineinfo);</div><div class='ctx'> </div><div class='ctx'> 	if (copy_to_user(ip, &amp;lineinfo, sizeof(lineinfo))) {</div><div class='ctx'> 		if (watch)</div><div class='hunk'>@@ -2490,6 +2508,8 @@ static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)</div><div class='ctx'> 	struct gpio_device *gdev = cdev-&gt;gdev;</div><div class='ctx'> 	void __user *ip = (void __user *)arg;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	/* We fail any subsequent ioctl():s when the chip is gone */</div><div class='ctx'> 	if (!gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='hunk'>@@ -2545,6 +2565,7 @@ static int lineinfo_changed_notify(struct notifier_block *nb,</div><div class='ctx'> 	chg.event_type = action;</div><div class='ctx'> 	chg.timestamp_ns = ktime_get_ns();</div><div class='ctx'> 	gpio_desc_to_lineinfo(desc, &amp;chg.info);</div><div class='add'>+	supinfo_to_lineinfo(desc, &amp;chg.info);</div><div class='ctx'> </div><div class='ctx'> 	ret = kfifo_in_spinlocked(&amp;cdev-&gt;events, &amp;chg, 1, &amp;cdev-&gt;wait.lock);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -2567,12 +2588,14 @@ static int gpio_device_unregistered_notify(struct notifier_block *nb,</div><div class='ctx'> 	return NOTIFY_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __poll_t lineinfo_watch_poll_unlocked(struct file *file,</div><div class='del'>-					     struct poll_table_struct *pollt)</div><div class='add'>+static __poll_t lineinfo_watch_poll(struct file *file,</div><div class='add'>+				    struct poll_table_struct *pollt)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chardev_data *cdev = file-&gt;private_data;</div><div class='ctx'> 	__poll_t events = 0;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;cdev-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!cdev-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return EPOLLHUP | EPOLLERR;</div><div class='ctx'> </div><div class='hunk'>@@ -2585,17 +2608,8 @@ static __poll_t lineinfo_watch_poll_unlocked(struct file *file,</div><div class='ctx'> 	return events;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __poll_t lineinfo_watch_poll(struct file *file,</div><div class='del'>-				    struct poll_table_struct *pollt)</div><div class='del'>-{</div><div class='del'>-	struct gpio_chardev_data *cdev = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_poll_locked(file, pollt, cdev-&gt;gdev,</div><div class='del'>-				lineinfo_watch_poll_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static ssize_t lineinfo_watch_read_unlocked(struct file *file, char __user *buf,</div><div class='del'>-					    size_t count, loff_t *off)</div><div class='add'>+static ssize_t lineinfo_watch_read(struct file *file, char __user *buf,</div><div class='add'>+				   size_t count, loff_t *off)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_chardev_data *cdev = file-&gt;private_data;</div><div class='ctx'> 	struct gpio_v2_line_info_changed event;</div><div class='hunk'>@@ -2603,6 +2617,8 @@ static ssize_t lineinfo_watch_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	size_t event_size;</div><div class='ctx'> </div><div class='add'>+	guard(rwsem_read)(&amp;cdev-&gt;gdev-&gt;sem);</div><div class='add'>+</div><div class='ctx'> 	if (!cdev-&gt;gdev-&gt;chip)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -2613,38 +2629,30 @@ static ssize_t lineinfo_watch_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		spin_lock(&amp;cdev-&gt;wait.lock);</div><div class='del'>-		if (kfifo_is_empty(&amp;cdev-&gt;events)) {</div><div class='del'>-			if (bytes_read) {</div><div class='del'>-				spin_unlock(&amp;cdev-&gt;wait.lock);</div><div class='del'>-				return bytes_read;</div><div class='add'>+		scoped_guard(spinlock, &amp;cdev-&gt;wait.lock) {</div><div class='add'>+			if (kfifo_is_empty(&amp;cdev-&gt;events)) {</div><div class='add'>+				if (bytes_read)</div><div class='add'>+					return bytes_read;</div><div class='add'>+</div><div class='add'>+				if (file-&gt;f_flags &amp; O_NONBLOCK)</div><div class='add'>+					return -EAGAIN;</div><div class='add'>+</div><div class='add'>+				ret = wait_event_interruptible_locked(cdev-&gt;wait,</div><div class='add'>+						!kfifo_is_empty(&amp;cdev-&gt;events));</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='del'>-			if (file-&gt;f_flags &amp; O_NONBLOCK) {</div><div class='del'>-				spin_unlock(&amp;cdev-&gt;wait.lock);</div><div class='del'>-				return -EAGAIN;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			ret = wait_event_interruptible_locked(cdev-&gt;wait,</div><div class='del'>-					!kfifo_is_empty(&amp;cdev-&gt;events));</div><div class='del'>-			if (ret) {</div><div class='del'>-				spin_unlock(&amp;cdev-&gt;wait.lock);</div><div class='del'>-				return ret;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='ctx'> #ifdef CONFIG_GPIO_CDEV_V1</div><div class='del'>-		/* must be after kfifo check so watch_abi_version is set */</div><div class='del'>-		if (atomic_read(&amp;cdev-&gt;watch_abi_version) == 2)</div><div class='del'>-			event_size = sizeof(struct gpio_v2_line_info_changed);</div><div class='del'>-		else</div><div class='del'>-			event_size = sizeof(struct gpioline_info_changed);</div><div class='del'>-		if (count &lt; event_size) {</div><div class='del'>-			spin_unlock(&amp;cdev-&gt;wait.lock);</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+			/* must be after kfifo check so watch_abi_version is set */</div><div class='add'>+			if (atomic_read(&amp;cdev-&gt;watch_abi_version) == 2)</div><div class='add'>+				event_size = sizeof(struct gpio_v2_line_info_changed);</div><div class='add'>+			else</div><div class='add'>+				event_size = sizeof(struct gpioline_info_changed);</div><div class='add'>+			if (count &lt; event_size)</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> #endif</div><div class='del'>-		ret = kfifo_out(&amp;cdev-&gt;events, &amp;event, 1);</div><div class='del'>-		spin_unlock(&amp;cdev-&gt;wait.lock);</div><div class='add'>+			ret = kfifo_out(&amp;cdev-&gt;events, &amp;event, 1);</div><div class='add'>+		}</div><div class='ctx'> 		if (ret != 1) {</div><div class='ctx'> 			ret = -EIO;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -2673,15 +2681,6 @@ static ssize_t lineinfo_watch_read_unlocked(struct file *file, char __user *buf,</div><div class='ctx'> 	return bytes_read;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static ssize_t lineinfo_watch_read(struct file *file, char __user *buf,</div><div class='del'>-				   size_t count, loff_t *off)</div><div class='del'>-{</div><div class='del'>-	struct gpio_chardev_data *cdev = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	return call_read_locked(file, buf, count, off, cdev-&gt;gdev,</div><div class='del'>-				lineinfo_watch_read_unlocked);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * gpio_chrdev_open() - open the chardev for ioctl operations</div><div class='ctx'>  * @inode: inode for this chardev</div><div class='hunk'>@@ -2695,17 +2694,15 @@ static int gpio_chrdev_open(struct inode *inode, struct file *file)</div><div class='ctx'> 	struct gpio_chardev_data *cdev;</div><div class='ctx'> 	int ret = -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	down_read(&amp;gdev-&gt;sem);</div><div class='add'>+	guard(rwsem_read)(&amp;gdev-&gt;sem);</div><div class='ctx'> </div><div class='ctx'> 	/* Fail on open if the backing gpiochip is gone */</div><div class='del'>-	if (!gdev-&gt;chip) {</div><div class='del'>-		ret = -ENODEV;</div><div class='del'>-		goto out_unlock;</div><div class='del'>-	}</div><div class='add'>+	if (!gdev-&gt;chip)</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);</div><div class='ctx'> 	if (!cdev)</div><div class='del'>-		goto out_unlock;</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	cdev-&gt;watched_lines = bitmap_zalloc(gdev-&gt;chip-&gt;ngpio, GFP_KERNEL);</div><div class='ctx'> 	if (!cdev-&gt;watched_lines)</div><div class='hunk'>@@ -2734,8 +2731,6 @@ static int gpio_chrdev_open(struct inode *inode, struct file *file)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_unregister_device_notifier;</div><div class='ctx'> </div><div class='del'>-	up_read(&amp;gdev-&gt;sem);</div><div class='del'>-</div><div class='ctx'> 	return ret;</div><div class='ctx'> </div><div class='ctx'> out_unregister_device_notifier:</div><div class='hunk'>@@ -2749,8 +2744,6 @@ out_free_bitmap:</div><div class='ctx'> 	bitmap_free(cdev-&gt;watched_lines);</div><div class='ctx'> out_free_cdev:</div><div class='ctx'> 	kfree(cdev);</div><div class='del'>-out_unlock:</div><div class='del'>-	up_read(&amp;gdev-&gt;sem);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c<br/>index 402f7d99b0c1..e7770eedd146 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-of.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib-of.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-of.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-of.c</a></div><div class='hunk'>@@ -184,7 +184,7 @@ static void of_gpio_try_fixup_polarity(const struct device_node *np,</div><div class='ctx'> 		const char *propname;</div><div class='ctx'> 		bool active_high;</div><div class='ctx'> 	} gpios[] = {</div><div class='del'>-#if !IS_ENABLED(CONFIG_LCD_HX8357)</div><div class='add'>+#if IS_ENABLED(CONFIG_LCD_HX8357)</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Himax LCD controllers used incorrectly named</div><div class='ctx'> 		 * "gpios-reset" property and also specified wrong</div><div class='hunk'>@@ -478,7 +478,7 @@ static struct gpio_desc *of_find_gpio_rename(struct device_node *np,</div><div class='ctx'> 		 */</div><div class='ctx'> 		const char *compatible;</div><div class='ctx'> 	} gpios[] = {</div><div class='del'>-#if !IS_ENABLED(CONFIG_LCD_HX8357)</div><div class='add'>+#if IS_ENABLED(CONFIG_LCD_HX8357)</div><div class='ctx'> 		/* Himax LCD controllers used "gpios-reset" */</div><div class='ctx'> 		{ "reset",	"gpios-reset",	"himax,hx8357" },</div><div class='ctx'> 		{ "reset",	"gpios-reset",	"himax,hx8369" },</div><div class='head'>diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c<br/>index 6f309a3b2d9a..6bf5332136e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib-sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-sysfs.c</a></div><div class='hunk'>@@ -165,10 +165,10 @@ static irqreturn_t gpio_sysfs_irq(int irq, void *priv)</div><div class='ctx'> /* Caller holds gpiod-data mutex. */</div><div class='ctx'> static int gpio_sysfs_request_irq(struct device *dev, unsigned char flags)</div><div class='ctx'> {</div><div class='del'>-	struct gpiod_data	*data = dev_get_drvdata(dev);</div><div class='del'>-	struct gpio_desc	*desc = data-&gt;desc;</div><div class='del'>-	unsigned long		irq_flags;</div><div class='del'>-	int			ret;</div><div class='add'>+	struct gpiod_data *data = dev_get_drvdata(dev);</div><div class='add'>+	struct gpio_desc *desc = data-&gt;desc;</div><div class='add'>+	unsigned long irq_flags;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;irq = gpiod_to_irq(desc);</div><div class='ctx'> 	if (data-&gt;irq &lt; 0)</div><div class='hunk'>@@ -259,7 +259,7 @@ static ssize_t edge_store(struct device *dev,</div><div class='ctx'> 		struct device_attribute *attr, const char *buf, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpiod_data *data = dev_get_drvdata(dev);</div><div class='del'>-	ssize_t	status = size;</div><div class='add'>+	ssize_t status = size;</div><div class='ctx'> 	int flags;</div><div class='ctx'> </div><div class='ctx'> 	flags = sysfs_match_string(trigger_names, buf);</div><div class='hunk'>@@ -292,10 +292,11 @@ static DEVICE_ATTR_RW(edge);</div><div class='ctx'> /* Caller holds gpiod-data mutex. */</div><div class='ctx'> static int gpio_sysfs_set_active_low(struct device *dev, int value)</div><div class='ctx'> {</div><div class='del'>-	struct gpiod_data	*data = dev_get_drvdata(dev);</div><div class='del'>-	struct gpio_desc	*desc = data-&gt;desc;</div><div class='del'>-	int			status = 0;</div><div class='del'>-	unsigned int		flags = data-&gt;irq_flags;</div><div class='add'>+	struct gpiod_data *data = dev_get_drvdata(dev);</div><div class='add'>+	unsigned int flags = data-&gt;irq_flags;</div><div class='add'>+	struct gpio_desc *desc = data-&gt;desc;</div><div class='add'>+	int status = 0;</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	if (!!test_bit(FLAG_ACTIVE_LOW, &amp;desc-&gt;flags) == !!value)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -331,9 +332,9 @@ static ssize_t active_low_show(struct device *dev,</div><div class='ctx'> static ssize_t active_low_store(struct device *dev,</div><div class='ctx'> 		struct device_attribute *attr, const char *buf, size_t size)</div><div class='ctx'> {</div><div class='del'>-	struct gpiod_data	*data = dev_get_drvdata(dev);</div><div class='del'>-	ssize_t			status;</div><div class='del'>-	long			value;</div><div class='add'>+	struct gpiod_data *data = dev_get_drvdata(dev);</div><div class='add'>+	ssize_t status;</div><div class='add'>+	long value;</div><div class='ctx'> </div><div class='ctx'> 	status = kstrtol(buf, 0, &amp;value);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -399,7 +400,7 @@ static const struct attribute_group *gpio_groups[] = {</div><div class='ctx'> static ssize_t base_show(struct device *dev,</div><div class='ctx'> 			       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='del'>-	const struct gpio_chip	*chip = dev_get_drvdata(dev);</div><div class='add'>+	const struct gpio_chip *chip = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='ctx'> 	return sysfs_emit(buf, "%d\n", chip-&gt;base);</div><div class='ctx'> }</div><div class='hunk'>@@ -408,7 +409,7 @@ static DEVICE_ATTR_RO(base);</div><div class='ctx'> static ssize_t label_show(struct device *dev,</div><div class='ctx'> 			       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='del'>-	const struct gpio_chip	*chip = dev_get_drvdata(dev);</div><div class='add'>+	const struct gpio_chip *chip = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='ctx'> 	return sysfs_emit(buf, "%s\n", chip-&gt;label ?: "");</div><div class='ctx'> }</div><div class='hunk'>@@ -417,7 +418,7 @@ static DEVICE_ATTR_RO(label);</div><div class='ctx'> static ssize_t ngpio_show(struct device *dev,</div><div class='ctx'> 			       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='del'>-	const struct gpio_chip	*chip = dev_get_drvdata(dev);</div><div class='add'>+	const struct gpio_chip *chip = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='ctx'> 	return sysfs_emit(buf, "%u\n", chip-&gt;ngpio);</div><div class='ctx'> }</div><div class='hunk'>@@ -441,11 +442,10 @@ static ssize_t export_store(const struct class *class,</div><div class='ctx'> 				const struct class_attribute *attr,</div><div class='ctx'> 				const char *buf, size_t len)</div><div class='ctx'> {</div><div class='del'>-	long			gpio;</div><div class='del'>-	struct gpio_desc	*desc;</div><div class='del'>-	int			status;</div><div class='del'>-	struct gpio_chip	*gc;</div><div class='del'>-	int			offset;</div><div class='add'>+	struct gpio_desc *desc;</div><div class='add'>+	struct gpio_chip *gc;</div><div class='add'>+	int status, offset;</div><div class='add'>+	long gpio;</div><div class='ctx'> </div><div class='ctx'> 	status = kstrtol(buf, 0, &amp;gpio);</div><div class='ctx'> 	if (status &lt; 0)</div><div class='hunk'>@@ -474,14 +474,17 @@ static ssize_t export_store(const struct class *class,</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='ctx'> 	status = gpiod_set_transitory(desc, false);</div><div class='del'>-	if (!status) {</div><div class='del'>-		status = gpiod_export(desc, true);</div><div class='del'>-		if (status &lt; 0)</div><div class='del'>-			gpiod_free(desc);</div><div class='del'>-		else</div><div class='del'>-			set_bit(FLAG_SYSFS, &amp;desc-&gt;flags);</div><div class='add'>+	if (status) {</div><div class='add'>+		gpiod_free(desc);</div><div class='add'>+		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	status = gpiod_export(desc, true);</div><div class='add'>+	if (status &lt; 0)</div><div class='add'>+		gpiod_free(desc);</div><div class='add'>+	else</div><div class='add'>+		set_bit(FLAG_SYSFS, &amp;desc-&gt;flags);</div><div class='add'>+</div><div class='ctx'> done:</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		pr_debug("%s: status %d\n", __func__, status);</div><div class='hunk'>@@ -493,9 +496,9 @@ static ssize_t unexport_store(const struct class *class,</div><div class='ctx'> 				const struct class_attribute *attr,</div><div class='ctx'> 				const char *buf, size_t len)</div><div class='ctx'> {</div><div class='del'>-	long			gpio;</div><div class='del'>-	struct gpio_desc	*desc;</div><div class='del'>-	int			status;</div><div class='add'>+	struct gpio_desc *desc;</div><div class='add'>+	int status;</div><div class='add'>+	long gpio;</div><div class='ctx'> </div><div class='ctx'> 	status = kstrtol(buf, 0, &amp;gpio);</div><div class='ctx'> 	if (status &lt; 0)</div><div class='hunk'>@@ -556,14 +559,13 @@ static struct class gpio_class = {</div><div class='ctx'>  */</div><div class='ctx'> int gpiod_export(struct gpio_desc *desc, bool direction_may_change)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*chip;</div><div class='del'>-	struct gpio_device	*gdev;</div><div class='del'>-	struct gpiod_data	*data;</div><div class='del'>-	unsigned long		flags;</div><div class='del'>-	int			status;</div><div class='del'>-	const char		*ioname = NULL;</div><div class='del'>-	struct device		*dev;</div><div class='del'>-	int			offset;</div><div class='add'>+	const char *ioname = NULL;</div><div class='add'>+	struct gpio_device *gdev;</div><div class='add'>+	struct gpiod_data *data;</div><div class='add'>+	struct gpio_chip *chip;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int status, offset;</div><div class='ctx'> </div><div class='ctx'> 	/* can't export until sysfs is available ... */</div><div class='ctx'> 	if (!class_is_registered(&amp;gpio_class)) {</div><div class='hunk'>@@ -730,9 +732,9 @@ EXPORT_SYMBOL_GPL(gpiod_unexport);</div><div class='ctx'> </div><div class='ctx'> int gpiochip_sysfs_register(struct gpio_device *gdev)</div><div class='ctx'> {</div><div class='del'>-	struct device	*dev;</div><div class='del'>-	struct device	*parent;</div><div class='ctx'> 	struct gpio_chip *chip = gdev-&gt;chip;</div><div class='add'>+	struct device *parent;</div><div class='add'>+	struct device *dev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Many systems add gpio chips for SOC support very early,</div><div class='head'>diff --git a/drivers/gpio/gpiolib-sysfs.h b/drivers/gpio/gpiolib-sysfs.h<br/>index 0f213bdb4732..b794b396d6a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-sysfs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib-sysfs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib-sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib-sysfs.h</a></div><div class='hunk'>@@ -3,10 +3,10 @@</div><div class='ctx'> #ifndef GPIOLIB_SYSFS_H</div><div class='ctx'> #define GPIOLIB_SYSFS_H</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_GPIO_SYSFS</div><div class='del'>-</div><div class='ctx'> struct gpio_device;</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_GPIO_SYSFS</div><div class='add'>+</div><div class='ctx'> int gpiochip_sysfs_register(struct gpio_device *gdev);</div><div class='ctx'> void gpiochip_sysfs_unregister(struct gpio_device *gdev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c<br/>index 95d2a7b2ea3e..44c8f5743a24 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib.c</a></div><div class='hunk'>@@ -45,19 +45,6 @@</div><div class='ctx'>  * GPIOs can sometimes cost only an instruction or two per bit.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-/* When debugging, extend minimal trust to callers and platform code.</div><div class='del'>- * Also emit diagnostic messages that may help initial bringup, when</div><div class='del'>- * board setup or driver bugs are most common.</div><div class='del'>- *</div><div class='del'>- * Otherwise, minimize overhead in what may be bitbanging codepaths.</div><div class='del'>- */</div><div class='del'>-#ifdef	DEBUG</div><div class='del'>-#define	extra_checks	1</div><div class='del'>-#else</div><div class='del'>-#define	extra_checks	0</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> /* Device and char device-related information */</div><div class='ctx'> static DEFINE_IDA(gpio_ida);</div><div class='ctx'> static dev_t gpio_devt;</div><div class='hunk'>@@ -255,6 +242,20 @@ int gpio_device_get_base(struct gpio_device *gdev)</div><div class='ctx'> EXPORT_SYMBOL_GPL(gpio_device_get_base);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * gpio_device_get_label() - Get the label of this GPIO device</div><div class='add'>+ * @gdev: GPIO device</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * Pointer to the string containing the GPIO device label. The string's</div><div class='add'>+ * lifetime is tied to that of the underlying GPIO device.</div><div class='add'>+ */</div><div class='add'>+const char *gpio_device_get_label(struct gpio_device *gdev)</div><div class='add'>+{</div><div class='add'>+	return gdev-&gt;label;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(gpio_device_get_label);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * gpio_device_get_chip() - Get the gpio_chip implementation of this GPIO device</div><div class='ctx'>  * @gdev: GPIO device</div><div class='ctx'>  *</div><div class='hunk'>@@ -276,7 +277,7 @@ struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev)</div><div class='ctx'> EXPORT_SYMBOL_GPL(gpio_device_get_chip);</div><div class='ctx'> </div><div class='ctx'> /* dynamic allocation of GPIOs, e.g. on a hotplugged device */</div><div class='del'>-static int gpiochip_find_base(int ngpio)</div><div class='add'>+static int gpiochip_find_base_unlocked(int ngpio)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_device *gdev;</div><div class='ctx'> 	int base = GPIO_DYNAMIC_BASE;</div><div class='hunk'>@@ -349,7 +350,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_direction);</div><div class='ctx'>  * Return -EBUSY if the new chip overlaps with some other chip's integer</div><div class='ctx'>  * space.</div><div class='ctx'>  */</div><div class='del'>-static int gpiodev_add_to_list(struct gpio_device *gdev)</div><div class='add'>+static int gpiodev_add_to_list_unlocked(struct gpio_device *gdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_device *prev, *next;</div><div class='ctx'> </div><div class='hunk'>@@ -655,11 +656,6 @@ EXPORT_SYMBOL_GPL(gpiochip_line_is_valid);</div><div class='ctx'> static void gpiodev_release(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_device *gdev = to_gpio_device(dev);</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;gpio_lock, flags);</div><div class='del'>-	list_del(&amp;gdev-&gt;list);</div><div class='del'>-	spin_unlock_irqrestore(&amp;gpio_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	ida_free(&amp;gpio_ida, gdev-&gt;id);</div><div class='ctx'> 	kfree_const(gdev-&gt;label);</div><div class='hunk'>@@ -893,7 +889,7 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,</div><div class='ctx'> 	 */</div><div class='ctx'> 	base = gc-&gt;base;</div><div class='ctx'> 	if (base &lt; 0) {</div><div class='del'>-		base = gpiochip_find_base(gc-&gt;ngpio);</div><div class='add'>+		base = gpiochip_find_base_unlocked(gc-&gt;ngpio);</div><div class='ctx'> 		if (base &lt; 0) {</div><div class='ctx'> 			spin_unlock_irqrestore(&amp;gpio_lock, flags);</div><div class='ctx'> 			ret = base;</div><div class='hunk'>@@ -913,7 +909,7 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,</div><div class='ctx'> 	}</div><div class='ctx'> 	gdev-&gt;base = base;</div><div class='ctx'> </div><div class='del'>-	ret = gpiodev_add_to_list(gdev);</div><div class='add'>+	ret = gpiodev_add_to_list_unlocked(gdev);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;gpio_lock, flags);</div><div class='ctx'> 		chip_err(gc, "GPIO integer space overlap, cannot add chip\n");</div><div class='hunk'>@@ -1048,8 +1044,8 @@ EXPORT_SYMBOL_GPL(gpiochip_add_data_with_key);</div><div class='ctx'> void gpiochip_remove(struct gpio_chip *gc)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_device *gdev = gc-&gt;gpiodev;</div><div class='del'>-	unsigned long	flags;</div><div class='del'>-	unsigned int	i;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	down_write(&amp;gdev-&gt;sem);</div><div class='ctx'> </div><div class='hunk'>@@ -1071,7 +1067,7 @@ void gpiochip_remove(struct gpio_chip *gc)</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;gpio_lock, flags);</div><div class='ctx'> 	for (i = 0; i &lt; gdev-&gt;ngpio; i++) {</div><div class='del'>-		if (gpiochip_is_requested(gc, i))</div><div class='add'>+		if (test_bit(FLAG_REQUESTED, &amp;gdev-&gt;descs[i].flags))</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;gpio_lock, flags);</div><div class='hunk'>@@ -1080,6 +1076,9 @@ void gpiochip_remove(struct gpio_chip *gc)</div><div class='ctx'> 		dev_crit(&amp;gdev-&gt;dev,</div><div class='ctx'> 			 "REMOVING GPIOCHIP WITH GPIOS STILL REQUESTED\n");</div><div class='ctx'> </div><div class='add'>+	scoped_guard(spinlock_irqsave, &amp;gpio_lock)</div><div class='add'>+		list_del(&amp;gdev-&gt;list);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The gpiochip side puts its use of the device to rest here:</div><div class='ctx'> 	 * if there are no userspace clients, the chardev and device will</div><div class='hunk'>@@ -2185,10 +2184,10 @@ EXPORT_SYMBOL_GPL(gpiochip_remove_pin_ranges);</div><div class='ctx'>  */</div><div class='ctx'> static int gpiod_request_commit(struct gpio_desc *desc, const char *label)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*gc = desc-&gt;gdev-&gt;chip;</div><div class='del'>-	int			ret;</div><div class='del'>-	unsigned long		flags;</div><div class='del'>-	unsigned		offset;</div><div class='add'>+	struct gpio_chip *gc = desc-&gt;gdev-&gt;chip;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	unsigned int offset;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (label) {</div><div class='ctx'> 		label = kstrdup_const(label, GFP_KERNEL);</div><div class='hunk'>@@ -2300,9 +2299,9 @@ int gpiod_request(struct gpio_desc *desc, const char *label)</div><div class='ctx'> </div><div class='ctx'> static bool gpiod_free_commit(struct gpio_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	bool			ret = false;</div><div class='del'>-	unsigned long		flags;</div><div class='del'>-	struct gpio_chip	*gc;</div><div class='add'>+	struct gpio_chip *gc;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool ret = false;</div><div class='ctx'> </div><div class='ctx'> 	might_sleep();</div><div class='ctx'> </div><div class='hunk'>@@ -2331,9 +2330,6 @@ static bool gpiod_free_commit(struct gpio_desc *desc)</div><div class='ctx'> #ifdef CONFIG_OF_DYNAMIC</div><div class='ctx'> 		desc-&gt;hog = NULL;</div><div class='ctx'> #endif</div><div class='del'>-#ifdef CONFIG_GPIO_CDEV</div><div class='del'>-		WRITE_ONCE(desc-&gt;debounce_period_us, 0);</div><div class='del'>-#endif</div><div class='ctx'> 		ret = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2353,38 +2349,53 @@ void gpiod_free(struct gpio_desc *desc)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (!gpiod_free_commit(desc))</div><div class='del'>-		WARN_ON(extra_checks);</div><div class='add'>+		WARN_ON(1);</div><div class='ctx'> </div><div class='ctx'> 	module_put(desc-&gt;gdev-&gt;owner);</div><div class='ctx'> 	gpio_device_put(desc-&gt;gdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * gpiochip_is_requested - return string iff signal was requested</div><div class='del'>- * @gc: controller managing the signal</div><div class='del'>- * @offset: of signal within controller's 0..(ngpio - 1) range</div><div class='add'>+ * gpiochip_dup_line_label - Get a copy of the consumer label.</div><div class='add'>+ * @gc: GPIO chip controlling this line.</div><div class='add'>+ * @offset: Hardware offset of the line.</div><div class='ctx'>  *</div><div class='del'>- * Returns NULL if the GPIO is not currently requested, else a string.</div><div class='del'>- * The string returned is the label passed to gpio_request(); if none has been</div><div class='del'>- * passed it is a meaningless, non-NULL constant.</div><div class='add'>+ * Returns:</div><div class='add'>+ * Pointer to a copy of the consumer label if the line is requested or NULL</div><div class='add'>+ * if it's not. If a valid pointer was returned, it must be freed using</div><div class='add'>+ * kfree(). In case of a memory allocation error, the function returns %ENOMEM.</div><div class='ctx'>  *</div><div class='del'>- * This function is for use by GPIO controller drivers.  The label can</div><div class='del'>- * help with diagnostics, and knowing that the signal is used as a GPIO</div><div class='del'>- * can help avoid accidentally multiplexing it to another controller.</div><div class='add'>+ * Must not be called from atomic context.</div><div class='ctx'>  */</div><div class='del'>-const char *gpiochip_is_requested(struct gpio_chip *gc, unsigned int offset)</div><div class='add'>+char *gpiochip_dup_line_label(struct gpio_chip *gc, unsigned int offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_desc *desc;</div><div class='add'>+	char *label;</div><div class='ctx'> </div><div class='ctx'> 	desc = gpiochip_get_desc(gc, offset);</div><div class='ctx'> 	if (IS_ERR(desc))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(FLAG_REQUESTED, &amp;desc-&gt;flags) == 0)</div><div class='add'>+	guard(spinlock_irqsave)(&amp;gpio_lock);</div><div class='add'>+</div><div class='add'>+	if (!test_bit(FLAG_REQUESTED, &amp;desc-&gt;flags))</div><div class='ctx'> 		return NULL;</div><div class='del'>-	return desc-&gt;label;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Once we mark gpiod_direction_input/output() and</div><div class='add'>+	 * gpiod_get_direction() with might_sleep(), we'll be able to protect</div><div class='add'>+	 * the GPIO descriptors with mutex (while value setting operations will</div><div class='add'>+	 * become lockless).</div><div class='add'>+	 *</div><div class='add'>+	 * Until this happens, this allocation needs to be atomic.</div><div class='add'>+	 */</div><div class='add'>+	label = kstrdup(desc-&gt;label, GFP_ATOMIC);</div><div class='add'>+	if (!label)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	return label;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(gpiochip_is_requested);</div><div class='add'>+EXPORT_SYMBOL_GPL(gpiochip_dup_line_label);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor</div><div class='hunk'>@@ -2564,8 +2575,8 @@ int gpio_set_debounce_timeout(struct gpio_desc *desc, unsigned int debounce)</div><div class='ctx'>  */</div><div class='ctx'> int gpiod_direction_input(struct gpio_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*gc;</div><div class='del'>-	int			ret = 0;</div><div class='add'>+	struct gpio_chip *gc;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	VALIDATE_DESC(desc);</div><div class='ctx'> 	gc = desc-&gt;gdev-&gt;chip;</div><div class='hunk'>@@ -2914,7 +2925,7 @@ static int gpio_chip_get_value(struct gpio_chip *gc, const struct gpio_desc *des</div><div class='ctx'> </div><div class='ctx'> static int gpiod_get_raw_value_commit(const struct gpio_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*gc;</div><div class='add'>+	struct gpio_chip *gc;</div><div class='ctx'> 	int value;</div><div class='ctx'> </div><div class='ctx'> 	gc = desc-&gt;gdev-&gt;chip;</div><div class='hunk'>@@ -3209,7 +3220,7 @@ static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value</div><div class='ctx'> </div><div class='ctx'> static void gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*gc;</div><div class='add'>+	struct gpio_chip *gc;</div><div class='ctx'> </div><div class='ctx'> 	gc = desc-&gt;gdev-&gt;chip;</div><div class='ctx'> 	trace_gpio_value(desc_to_gpio(desc), 0, value);</div><div class='hunk'>@@ -3716,7 +3727,7 @@ EXPORT_SYMBOL_GPL(gpiochip_line_is_persistent);</div><div class='ctx'>  */</div><div class='ctx'> int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	VALIDATE_DESC(desc);</div><div class='ctx'> 	return gpiod_get_raw_value_commit(desc);</div><div class='ctx'> }</div><div class='hunk'>@@ -3735,7 +3746,7 @@ int gpiod_get_value_cansleep(const struct gpio_desc *desc)</div><div class='ctx'> {</div><div class='ctx'> 	int value;</div><div class='ctx'> </div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	VALIDATE_DESC(desc);</div><div class='ctx'> 	value = gpiod_get_raw_value_commit(desc);</div><div class='ctx'> 	if (value &lt; 0)</div><div class='hunk'>@@ -3766,7 +3777,7 @@ int gpiod_get_raw_array_value_cansleep(unsigned int array_size,</div><div class='ctx'> 				       struct gpio_array *array_info,</div><div class='ctx'> 				       unsigned long *value_bitmap)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	if (!desc_array)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	return gpiod_get_array_value_complex(true, true, array_size,</div><div class='hunk'>@@ -3792,7 +3803,7 @@ int gpiod_get_array_value_cansleep(unsigned int array_size,</div><div class='ctx'> 				   struct gpio_array *array_info,</div><div class='ctx'> 				   unsigned long *value_bitmap)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	if (!desc_array)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	return gpiod_get_array_value_complex(false, true, array_size,</div><div class='hunk'>@@ -3813,7 +3824,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_array_value_cansleep);</div><div class='ctx'>  */</div><div class='ctx'> void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	VALIDATE_DESC_VOID(desc);</div><div class='ctx'> 	gpiod_set_raw_value_commit(desc, value);</div><div class='ctx'> }</div><div class='hunk'>@@ -3831,7 +3842,7 @@ EXPORT_SYMBOL_GPL(gpiod_set_raw_value_cansleep);</div><div class='ctx'>  */</div><div class='ctx'> void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	VALIDATE_DESC_VOID(desc);</div><div class='ctx'> 	gpiod_set_value_nocheck(desc, value);</div><div class='ctx'> }</div><div class='hunk'>@@ -3854,7 +3865,7 @@ int gpiod_set_raw_array_value_cansleep(unsigned int array_size,</div><div class='ctx'> 				       struct gpio_array *array_info,</div><div class='ctx'> 				       unsigned long *value_bitmap)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	if (!desc_array)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	return gpiod_set_array_value_complex(true, true, array_size, desc_array,</div><div class='hunk'>@@ -3896,7 +3907,7 @@ int gpiod_set_array_value_cansleep(unsigned int array_size,</div><div class='ctx'> 				   struct gpio_array *array_info,</div><div class='ctx'> 				   unsigned long *value_bitmap)</div><div class='ctx'> {</div><div class='del'>-	might_sleep_if(extra_checks);</div><div class='add'>+	might_sleep();</div><div class='ctx'> 	if (!desc_array)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	return gpiod_set_array_value_complex(false, true, array_size,</div><div class='hunk'>@@ -4696,13 +4707,11 @@ core_initcall(gpiolib_dev_init);</div><div class='ctx'> </div><div class='ctx'> static void gpiolib_dbg_show(struct seq_file *s, struct gpio_device *gdev)</div><div class='ctx'> {</div><div class='del'>-	struct gpio_chip	*gc = gdev-&gt;chip;</div><div class='del'>-	struct gpio_desc	*desc;</div><div class='del'>-	unsigned		gpio = gdev-&gt;base;</div><div class='del'>-	int			value;</div><div class='del'>-	bool			is_out;</div><div class='del'>-	bool			is_irq;</div><div class='del'>-	bool			active_low;</div><div class='add'>+	struct gpio_chip *gc = gdev-&gt;chip;</div><div class='add'>+	bool active_low, is_irq, is_out;</div><div class='add'>+	unsigned int gpio = gdev-&gt;base;</div><div class='add'>+	struct gpio_desc *desc;</div><div class='add'>+	int value;</div><div class='ctx'> </div><div class='ctx'> 	for_each_gpio_desc(gc, desc) {</div><div class='ctx'> 		if (test_bit(FLAG_REQUESTED, &amp;desc-&gt;flags)) {</div><div class='head'>diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h<br/>index 3ccacf3c1288..a4a2520b5f31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpio/gpiolib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpio/gpiolib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpio/gpiolib.h</a></div><div class='hunk'>@@ -147,7 +147,6 @@ void gpiod_line_state_notify(struct gpio_desc *desc, unsigned long action);</div><div class='ctx'>  * @label:		Name of the consumer</div><div class='ctx'>  * @name:		Line name</div><div class='ctx'>  * @hog:		Pointer to the device node that hogs this line (if any)</div><div class='del'>- * @debounce_period_us:	Debounce period in microseconds</div><div class='ctx'>  *</div><div class='ctx'>  * These are obtained using gpiod_get() and are preferable to the old</div><div class='ctx'>  * integer-based handles.</div><div class='hunk'>@@ -185,10 +184,6 @@ struct gpio_desc {</div><div class='ctx'> #ifdef CONFIG_OF_DYNAMIC</div><div class='ctx'> 	struct device_node	*hog;</div><div class='ctx'> #endif</div><div class='del'>-#ifdef CONFIG_GPIO_CDEV</div><div class='del'>-	/* debounce period in microseconds */</div><div class='del'>-	unsigned int		debounce_period_us;</div><div class='del'>-#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define gpiod_not_found(desc)		(IS_ERR(desc) &amp;&amp; PTR_ERR(desc) == -ENOENT)</div><div class='head'>diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig<br/>index 23764316efcf..872edb47bb53 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/Kconfig</a></div><div class='hunk'>@@ -275,6 +275,8 @@ source "drivers/gpu/drm/nouveau/Kconfig"</div><div class='ctx'> </div><div class='ctx'> source "drivers/gpu/drm/i915/Kconfig"</div><div class='ctx'> </div><div class='add'>+source "drivers/gpu/drm/xe/Kconfig"</div><div class='add'>+</div><div class='ctx'> source "drivers/gpu/drm/kmb/Kconfig"</div><div class='ctx'> </div><div class='ctx'> config DRM_VGEM</div><div class='head'>diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile<br/>index 8ac6f4b9546e..104b42df2e95 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/Makefile</a></div><div class='hunk'>@@ -134,6 +134,7 @@ obj-$(CONFIG_DRM_RADEON)+= radeon/</div><div class='ctx'> obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/</div><div class='ctx'> obj-$(CONFIG_DRM_AMDGPU)+= amd/amdxcp/</div><div class='ctx'> obj-$(CONFIG_DRM_I915)	+= i915/</div><div class='add'>+obj-$(CONFIG_DRM_XE)	+= xe/</div><div class='ctx'> obj-$(CONFIG_DRM_KMB_DISPLAY)  += kmb/</div><div class='ctx'> obj-$(CONFIG_DRM_MGAG200) += mgag200/</div><div class='ctx'> obj-$(CONFIG_DRM_V3D)  += v3d/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile<br/>index 2afecc55090f..260e32ef7bae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/Makefile</a></div><div class='hunk'>@@ -80,7 +80,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \</div><div class='ctx'> 	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \</div><div class='ctx'> 	amdgpu_fw_attestation.o amdgpu_securedisplay.o \</div><div class='ctx'> 	amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \</div><div class='del'>-	amdgpu_ring_mux.o amdgpu_xcp.o</div><div class='add'>+	amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o</div><div class='ctx'> </div><div class='ctx'> amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c<br/>index 02f4c6f9d4f6..576067d66bb9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/aldebaran.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/aldebaran.c</a></div><div class='hunk'>@@ -330,6 +330,7 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> {</div><div class='ctx'> 	struct list_head *reset_device_list = reset_context-&gt;reset_device_list;</div><div class='ctx'> 	struct amdgpu_device *tmp_adev = NULL;</div><div class='add'>+	struct amdgpu_ras *con;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (reset_device_list == NULL)</div><div class='hunk'>@@ -355,7 +356,30 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,</div><div class='ctx'> 		 */</div><div class='ctx'> 		amdgpu_register_gpu_instance(tmp_adev);</div><div class='ctx'> </div><div class='del'>-		/* Resume RAS */</div><div class='add'>+		/* Resume RAS, ecc_irq */</div><div class='add'>+		con = amdgpu_ras_get_context(tmp_adev);</div><div class='add'>+		if (!amdgpu_sriov_vf(tmp_adev) &amp;&amp; con) {</div><div class='add'>+			if (tmp_adev-&gt;sdma.ras &amp;&amp;</div><div class='add'>+				tmp_adev-&gt;sdma.ras-&gt;ras_block.ras_late_init) {</div><div class='add'>+				r = tmp_adev-&gt;sdma.ras-&gt;ras_block.ras_late_init(tmp_adev,</div><div class='add'>+						&amp;tmp_adev-&gt;sdma.ras-&gt;ras_block.ras_comm);</div><div class='add'>+				if (r) {</div><div class='add'>+					dev_err(tmp_adev-&gt;dev, "SDMA failed to execute ras_late_init! ret:%d\n", r);</div><div class='add'>+					goto end;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (tmp_adev-&gt;gfx.ras &amp;&amp;</div><div class='add'>+				tmp_adev-&gt;gfx.ras-&gt;ras_block.ras_late_init) {</div><div class='add'>+				r = tmp_adev-&gt;gfx.ras-&gt;ras_block.ras_late_init(tmp_adev,</div><div class='add'>+						&amp;tmp_adev-&gt;gfx.ras-&gt;ras_block.ras_comm);</div><div class='add'>+				if (r) {</div><div class='add'>+					dev_err(tmp_adev-&gt;dev, "GFX failed to execute ras_late_init! ret:%d\n", r);</div><div class='add'>+					goto end;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		amdgpu_ras_resume(tmp_adev);</div><div class='ctx'> </div><div class='ctx'> 		/* Update PSP FW topology after reset */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br/>index 9d92ca157677..3d8a48f46b01 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu.h</a></div><div class='hunk'>@@ -109,6 +109,8 @@</div><div class='ctx'> #include "amdgpu_mca.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='add'>+#include "amdgpu_seq64.h"</div><div class='add'>+#include "amdgpu_reg_state.h"</div><div class='ctx'> </div><div class='ctx'> #define MAX_GPU_INSTANCE		64</div><div class='ctx'> </div><div class='hunk'>@@ -250,6 +252,8 @@ extern int amdgpu_seamless;</div><div class='ctx'> extern int amdgpu_user_partt_mode;</div><div class='ctx'> extern int amdgpu_agp;</div><div class='ctx'> </div><div class='add'>+extern int amdgpu_wbrf;</div><div class='add'>+</div><div class='ctx'> #define AMDGPU_VM_MAX_NUM_CTX			4096</div><div class='ctx'> #define AMDGPU_SG_THRESHOLD			(256*1024*1024)</div><div class='ctx'> #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000</div><div class='hunk'>@@ -468,6 +472,7 @@ struct amdgpu_fpriv {</div><div class='ctx'> 	struct amdgpu_vm	vm;</div><div class='ctx'> 	struct amdgpu_bo_va	*prt_va;</div><div class='ctx'> 	struct amdgpu_bo_va	*csa_va;</div><div class='add'>+	struct amdgpu_bo_va	*seq64_va;</div><div class='ctx'> 	struct mutex		bo_list_lock;</div><div class='ctx'> 	struct idr		bo_list_handles;</div><div class='ctx'> 	struct amdgpu_ctx_mgr	ctx_mgr;</div><div class='hunk'>@@ -506,6 +511,31 @@ struct amdgpu_allowed_register_entry {</div><div class='ctx'> 	bool grbm_indexed;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * enum amd_reset_method - Methods for resetting AMD GPU devices</div><div class='add'>+ *</div><div class='add'>+ * @AMD_RESET_METHOD_NONE: The device will not be reset.</div><div class='add'>+ * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.</div><div class='add'>+ * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the</div><div class='add'>+ *                   any device.</div><div class='add'>+ * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)</div><div class='add'>+ *                   individually. Suitable only for some discrete GPU, not</div><div class='add'>+ *                   available for all ASICs.</div><div class='add'>+ * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs</div><div class='add'>+ *                   are reset depends on the ASIC. Notably doesn't reset IPs</div><div class='add'>+ *                   shared with the CPU on APUs or the memory controllers (so</div><div class='add'>+ *                   VRAM is not lost). Not available on all ASICs.</div><div class='add'>+ * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card</div><div class='add'>+ *                  but without powering off the PCI bus. Suitable only for</div><div class='add'>+ *                  discrete GPUs.</div><div class='add'>+ * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset</div><div class='add'>+ *                 and does a secondary bus reset or FLR, depending on what the</div><div class='add'>+ *                 underlying hardware supports.</div><div class='add'>+ *</div><div class='add'>+ * Methods available for AMD GPU driver for resetting the device. Not all</div><div class='add'>+ * methods are suitable for every device. User can override the method using</div><div class='add'>+ * module parameter `reset_method`.</div><div class='add'>+ */</div><div class='ctx'> enum amd_reset_method {</div><div class='ctx'> 	AMD_RESET_METHOD_NONE = -1,</div><div class='ctx'> 	AMD_RESET_METHOD_LEGACY = 0,</div><div class='hunk'>@@ -585,6 +615,10 @@ struct amdgpu_asic_funcs {</div><div class='ctx'> 				  const struct amdgpu_video_codecs **codecs);</div><div class='ctx'> 	/* encode "&gt; 32bits" smn addressing */</div><div class='ctx'> 	u64 (*encode_ext_smn_addressing)(int ext_id);</div><div class='add'>+</div><div class='add'>+	ssize_t (*get_reg_state)(struct amdgpu_device *adev,</div><div class='add'>+				 enum amdgpu_reg_state reg_state, void *buf,</div><div class='add'>+				 size_t max_size);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -757,6 +791,7 @@ struct amdgpu_mqd_prop {</div><div class='ctx'> 	uint64_t eop_gpu_addr;</div><div class='ctx'> 	uint32_t hqd_pipe_priority;</div><div class='ctx'> 	uint32_t hqd_queue_priority;</div><div class='add'>+	bool allow_tunneling;</div><div class='ctx'> 	bool hqd_active;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -986,6 +1021,9 @@ struct amdgpu_device {</div><div class='ctx'> 	/* GDS */</div><div class='ctx'> 	struct amdgpu_gds		gds;</div><div class='ctx'> </div><div class='add'>+	/* for userq and VM fences */</div><div class='add'>+	struct amdgpu_seq64		seq64;</div><div class='add'>+</div><div class='ctx'> 	/* KFD */</div><div class='ctx'> 	struct amdgpu_kfd_dev		kfd;</div><div class='ctx'> </div><div class='hunk'>@@ -1106,6 +1144,7 @@ struct amdgpu_device {</div><div class='ctx'> 	bool                            debug_vm;</div><div class='ctx'> 	bool                            debug_largebar;</div><div class='ctx'> 	bool                            debug_disable_soft_recovery;</div><div class='add'>+	bool                            debug_use_vram_fw_buf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c<br/>index b8412202a1b0..77e263660288 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c</a></div><div class='hunk'>@@ -138,10 +138,14 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work)</div><div class='ctx'> 	amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct drm_client_funcs kfd_client_funcs = {</div><div class='add'>+	.unregister	= drm_client_release,</div><div class='add'>+};</div><div class='ctx'> void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int last_valid_bit;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_amdkfd_gpuvm_init_mem_limits();</div><div class='ctx'> </div><div class='hunk'>@@ -160,6 +164,12 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)</div><div class='ctx'> 			.enable_mes = adev-&gt;enable_mes,</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='add'>+		ret = drm_client_init(&amp;adev-&gt;ddev, &amp;adev-&gt;kfd.client, "kfd", &amp;kfd_client_funcs);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to init DRM client: %d\n", ret);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		/* this is going to have a few of the MSBs set that we need to</div><div class='ctx'> 		 * clear</div><div class='ctx'> 		 */</div><div class='hunk'>@@ -198,6 +208,10 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 		adev-&gt;kfd.init_complete = kgd2kfd_device_init(adev-&gt;kfd.dev,</div><div class='ctx'> 							&amp;gpu_resources);</div><div class='add'>+		if (adev-&gt;kfd.init_complete)</div><div class='add'>+			drm_client_register(&amp;adev-&gt;kfd.client);</div><div class='add'>+		else</div><div class='add'>+			drm_client_release(&amp;adev-&gt;kfd.client);</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_amdkfd_total_mem_size += adev-&gt;gmc.real_vram_size;</div><div class='ctx'> </div><div class='hunk'>@@ -547,7 +561,7 @@ int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,</div><div class='ctx'> 	struct amdgpu_device *adev = dst, *peer_adev;</div><div class='ctx'> 	int num_links;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;asic_type != CHIP_ALDEBARAN)</div><div class='add'>+	if (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(9, 4, 2))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (src)</div><div class='hunk'>@@ -684,10 +698,8 @@ err:</div><div class='ctx'> void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)</div><div class='ctx'> {</div><div class='ctx'> 	enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;</div><div class='del'>-	/* Temporary workaround to fix issues observed in some</div><div class='del'>-	 * compute applications when GFXOFF is enabled on GFX11.</div><div class='del'>-	 */</div><div class='del'>-	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11) {</div><div class='add'>+	if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &amp;&amp;</div><div class='add'>+	    ((adev-&gt;mes.kiq_version &amp; AMDGPU_MES_VERSION_MASK) &lt;= 64)) {</div><div class='ctx'> 		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");</div><div class='ctx'> 		amdgpu_gfx_off_ctrl(adev, idle);</div><div class='ctx'> 	} else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &amp;&amp;</div><div class='hunk'>@@ -710,35 +722,6 @@ bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,</div><div class='del'>-				     uint16_t vmid)</div><div class='del'>-{</div><div class='del'>-	if (adev-&gt;family == AMDGPU_FAMILY_AI) {</div><div class='del'>-		int i;</div><div class='del'>-</div><div class='del'>-		for_each_set_bit(i, adev-&gt;vmhubs_mask, AMDGPU_MAX_VMHUBS)</div><div class='del'>-			amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);</div><div class='del'>-	} else {</div><div class='del'>-		amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,</div><div class='del'>-				      uint16_t pasid,</div><div class='del'>-				      enum TLB_FLUSH_TYPE flush_type,</div><div class='del'>-				      uint32_t inst)</div><div class='del'>-{</div><div class='del'>-	bool all_hub = false;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;family == AMDGPU_FAMILY_AI ||</div><div class='del'>-	    adev-&gt;family == AMDGPU_FAMILY_RV)</div><div class='del'>-		all_hub = true;</div><div class='del'>-</div><div class='del'>-	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	return adev-&gt;have_atomics_support;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h<br/>index dac983da961d..f262b9d89541 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #include &lt;linux/mmu_notifier.h&gt;</div><div class='ctx'> #include &lt;linux/memremap.h&gt;</div><div class='ctx'> #include &lt;kgd_kfd_interface.h&gt;</div><div class='add'>+#include &lt;drm/drm_client.h&gt;</div><div class='ctx'> #include "amdgpu_sync.h"</div><div class='ctx'> #include "amdgpu_vm.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='hunk'>@@ -83,6 +84,7 @@ struct kgd_mem {</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_sync sync;</div><div class='ctx'> </div><div class='add'>+	uint32_t gem_handle;</div><div class='ctx'> 	bool aql_queue;</div><div class='ctx'> 	bool is_imported;</div><div class='ctx'> };</div><div class='hunk'>@@ -105,6 +107,9 @@ struct amdgpu_kfd_dev {</div><div class='ctx'> </div><div class='ctx'> 	/* HMM page migration MEMORY_DEVICE_PRIVATE mapping */</div><div class='ctx'> 	struct dev_pagemap pgmap;</div><div class='add'>+</div><div class='add'>+	/* Client for KFD BO GEM handle allocations */</div><div class='add'>+	struct drm_client_dev client;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum kgd_engine_type {</div><div class='hunk'>@@ -162,11 +167,6 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,</div><div class='ctx'> 				uint32_t *ib_cmd, uint32_t ib_len);</div><div class='ctx'> void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);</div><div class='ctx'> bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);</div><div class='del'>-int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,</div><div class='del'>-				uint16_t vmid);</div><div class='del'>-int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,</div><div class='del'>-				uint16_t pasid, enum TLB_FLUSH_TYPE flush_type,</div><div class='del'>-				uint32_t inst);</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);</div><div class='ctx'> </div><div class='hunk'>@@ -311,14 +311,13 @@ void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);</div><div class='ctx'> int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,</div><div class='del'>-					    struct dma_fence **ef);</div><div class='add'>+					    struct dma_fence __rcu **ef);</div><div class='ctx'> int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,</div><div class='ctx'> 					      struct kfd_vm_fault_info *info);</div><div class='del'>-int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,</div><div class='del'>-				      struct dma_buf *dmabuf,</div><div class='del'>-				      uint64_t va, void *drm_priv,</div><div class='del'>-				      struct kgd_mem **mem, uint64_t *size,</div><div class='del'>-				      uint64_t *mmap_offset);</div><div class='add'>+int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,</div><div class='add'>+					 uint64_t va, void *drm_priv,</div><div class='add'>+					 struct kgd_mem **mem, uint64_t *size,</div><div class='add'>+					 uint64_t *mmap_offset);</div><div class='ctx'> int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,</div><div class='ctx'> 				      struct dma_buf **dmabuf);</div><div class='ctx'> void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c<br/>index 10d56979fe3b..899e31e3a5e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c</a></div><div class='hunk'>@@ -200,7 +200,7 @@ int kgd_arcturus_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+6+7+10)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c<br/>index 469785d33791..1ef758ac5076 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c</a></div><div class='hunk'>@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	fence = container_of(f, struct amdgpu_amdkfd_fence, base);</div><div class='del'>-	if (fence &amp;&amp; f-&gt;ops == &amp;amdkfd_fence_ops)</div><div class='add'>+	if (f-&gt;ops == &amp;amdkfd_fence_ops)</div><div class='ctx'> 		return fence;</div><div class='ctx'> </div><div class='ctx'> 	return NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c<br/>index f6598b9e4faa..a5c7259cf2a3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c</a></div><div class='hunk'>@@ -141,7 +141,7 @@ static int kgd_gfx_v9_4_3_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32(addr);         \</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c<br/>index 6bf448ab3dff..ca4a6b82817f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c</a></div><div class='hunk'>@@ -214,7 +214,7 @@ static int kgd_hqd_dump(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32(addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -301,7 +301,7 @@ static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+4)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c<br/>index cd06e4a6d1da..0f3e2944edd7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c</a></div><div class='hunk'>@@ -238,7 +238,7 @@ static int kgd_hqd_dump(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32(addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -324,7 +324,7 @@ static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+4+2+3+7)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br/>index 00fbc0f44c92..5a35a8ca8922 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c</a></div><div class='hunk'>@@ -363,7 +363,7 @@ int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev,</div><div class='ctx'> 		(*dump)[i++][1] = RREG32(addr);		\</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -460,7 +460,7 @@ static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,</div><div class='ctx'> #undef HQD_N_REGS</div><div class='ctx'> #define HQD_N_REGS (19+6+7+10)</div><div class='ctx'> </div><div class='del'>-	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);</div><div class='add'>+	*dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);</div><div class='ctx'> 	if (*dump == NULL)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c<br/>index 41fbc4fd0fac..f183d7faeeec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c</a></div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> #include &lt;linux/pagemap.h&gt;</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='ctx'> #include &lt;linux/sched/task.h&gt;</div><div class='add'>+#include &lt;linux/fdtable.h&gt;</div><div class='ctx'> #include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_exec.h&gt;</div><div class='hunk'>@@ -806,13 +807,22 @@ kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,</div><div class='ctx'> static int kfd_mem_export_dmabuf(struct kgd_mem *mem)</div><div class='ctx'> {</div><div class='ctx'> 	if (!mem-&gt;dmabuf) {</div><div class='del'>-		struct dma_buf *ret = amdgpu_gem_prime_export(</div><div class='del'>-			&amp;mem-&gt;bo-&gt;tbo.base,</div><div class='add'>+		struct amdgpu_device *bo_adev;</div><div class='add'>+		struct dma_buf *dmabuf;</div><div class='add'>+		int r, fd;</div><div class='add'>+</div><div class='add'>+		bo_adev = amdgpu_ttm_adev(mem-&gt;bo-&gt;tbo.bdev);</div><div class='add'>+		r = drm_gem_prime_handle_to_fd(&amp;bo_adev-&gt;ddev, bo_adev-&gt;kfd.client.file,</div><div class='add'>+					       mem-&gt;gem_handle,</div><div class='ctx'> 			mem-&gt;alloc_flags &amp; KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?</div><div class='del'>-				DRM_RDWR : 0);</div><div class='del'>-		if (IS_ERR(ret))</div><div class='del'>-			return PTR_ERR(ret);</div><div class='del'>-		mem-&gt;dmabuf = ret;</div><div class='add'>+					       DRM_RDWR : 0, &amp;fd);</div><div class='add'>+		if (r)</div><div class='add'>+			return r;</div><div class='add'>+		dmabuf = dma_buf_get(fd);</div><div class='add'>+		close_fd(fd);</div><div class='add'>+		if (WARN_ON_ONCE(IS_ERR(dmabuf)))</div><div class='add'>+			return PTR_ERR(dmabuf);</div><div class='add'>+		mem-&gt;dmabuf = dmabuf;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1137,7 +1147,7 @@ static int reserve_bo_and_vm(struct kgd_mem *mem,</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;n_vms = 1;</div><div class='ctx'> 	ctx-&gt;sync = &amp;mem-&gt;sync;</div><div class='del'>-	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;ctx-&gt;exec) {</div><div class='ctx'> 		ret = amdgpu_vm_lock_pd(vm, &amp;ctx-&gt;exec, 2);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;ctx-&gt;exec);</div><div class='hunk'>@@ -1176,7 +1186,7 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ctx-&gt;sync = &amp;mem-&gt;sync;</div><div class='del'>-	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;ctx-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;ctx-&gt;exec) {</div><div class='ctx'> 		ctx-&gt;n_vms = 0;</div><div class='ctx'> 		list_for_each_entry(entry, &amp;mem-&gt;attachments, list) {</div><div class='hunk'>@@ -1384,7 +1394,6 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,</div><div class='ctx'> 				  amdgpu_amdkfd_restore_userptr_worker);</div><div class='ctx'> </div><div class='ctx'> 		*process_info = info;</div><div class='del'>-		*ef = dma_fence_get(&amp;info-&gt;eviction_fence-&gt;base);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vm-&gt;process_info = *process_info;</div><div class='hunk'>@@ -1415,6 +1424,8 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,</div><div class='ctx'> 	list_add_tail(&amp;vm-&gt;vm_list_node,</div><div class='ctx'> 			&amp;(vm-&gt;process_info-&gt;vm_list_head));</div><div class='ctx'> 	vm-&gt;process_info-&gt;n_vms++;</div><div class='add'>+</div><div class='add'>+	*ef = dma_fence_get(&amp;vm-&gt;process_info-&gt;eviction_fence-&gt;base);</div><div class='ctx'> 	mutex_unlock(&amp;vm-&gt;process_info-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1426,10 +1437,7 @@ validate_pd_fail:</div><div class='ctx'> reserve_pd_fail:</div><div class='ctx'> 	vm-&gt;process_info = NULL;</div><div class='ctx'> 	if (info) {</div><div class='del'>-		/* Two fence references: one in info and one in *ef */</div><div class='ctx'> 		dma_fence_put(&amp;info-&gt;eviction_fence-&gt;base);</div><div class='del'>-		dma_fence_put(*ef);</div><div class='del'>-		*ef = NULL;</div><div class='ctx'> 		*process_info = NULL;</div><div class='ctx'> 		put_pid(info-&gt;pid);</div><div class='ctx'> create_evict_fence_fail:</div><div class='hunk'>@@ -1623,7 +1631,8 @@ int amdgpu_amdkfd_criu_resume(void *p)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	WRITE_ONCE(pinfo-&gt;block_mmu_notifications, false);</div><div class='del'>-	schedule_delayed_work(&amp;pinfo-&gt;restore_userptr_work, 0);</div><div class='add'>+	queue_delayed_work(system_freezable_wq,</div><div class='add'>+			   &amp;pinfo-&gt;restore_userptr_work, 0);</div><div class='ctx'> </div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;pinfo-&gt;lock);</div><div class='hunk'>@@ -1779,6 +1788,9 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(</div><div class='ctx'> 		pr_debug("Failed to allow vma node access. ret %d\n", ret);</div><div class='ctx'> 		goto err_node_allow;</div><div class='ctx'> 	}</div><div class='add'>+	ret = drm_gem_handle_create(adev-&gt;kfd.client.file, gobj, &amp;(*mem)-&gt;gem_handle);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_gem_handle_create;</div><div class='ctx'> 	bo = gem_to_amdgpu_bo(gobj);</div><div class='ctx'> 	if (bo_type == ttm_bo_type_sg) {</div><div class='ctx'> 		bo-&gt;tbo.sg = sg;</div><div class='hunk'>@@ -1830,6 +1842,8 @@ allocate_init_user_pages_failed:</div><div class='ctx'> err_pin_bo:</div><div class='ctx'> err_validate_bo:</div><div class='ctx'> 	remove_kgd_mem_from_kfd_bo_list(*mem, avm-&gt;process_info);</div><div class='add'>+	drm_gem_handle_delete(adev-&gt;kfd.client.file, (*mem)-&gt;gem_handle);</div><div class='add'>+err_gem_handle_create:</div><div class='ctx'> 	drm_vma_node_revoke(&amp;gobj-&gt;vma_node, drm_priv);</div><div class='ctx'> err_node_allow:</div><div class='ctx'> 	/* Don't unreserve system mem limit twice */</div><div class='hunk'>@@ -1942,8 +1956,11 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(</div><div class='ctx'> </div><div class='ctx'> 	/* Free the BO*/</div><div class='ctx'> 	drm_vma_node_revoke(&amp;mem-&gt;bo-&gt;tbo.base.vma_node, drm_priv);</div><div class='del'>-	if (mem-&gt;dmabuf)</div><div class='add'>+	drm_gem_handle_delete(adev-&gt;kfd.client.file, mem-&gt;gem_handle);</div><div class='add'>+	if (mem-&gt;dmabuf) {</div><div class='ctx'> 		dma_buf_put(mem-&gt;dmabuf);</div><div class='add'>+		mem-&gt;dmabuf = NULL;</div><div class='add'>+	}</div><div class='ctx'> 	mutex_destroy(&amp;mem-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	/* If this releases the last reference, it will end up calling</div><div class='hunk'>@@ -2295,34 +2312,26 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,</div><div class='del'>-				      struct dma_buf *dma_buf,</div><div class='del'>-				      uint64_t va, void *drm_priv,</div><div class='del'>-				      struct kgd_mem **mem, uint64_t *size,</div><div class='del'>-				      uint64_t *mmap_offset)</div><div class='add'>+static int import_obj_create(struct amdgpu_device *adev,</div><div class='add'>+			     struct dma_buf *dma_buf,</div><div class='add'>+			     struct drm_gem_object *obj,</div><div class='add'>+			     uint64_t va, void *drm_priv,</div><div class='add'>+			     struct kgd_mem **mem, uint64_t *size,</div><div class='add'>+			     uint64_t *mmap_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);</div><div class='del'>-	struct drm_gem_object *obj;</div><div class='ctx'> 	struct amdgpu_bo *bo;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);</div><div class='del'>-	if (IS_ERR(obj))</div><div class='del'>-		return PTR_ERR(obj);</div><div class='del'>-</div><div class='ctx'> 	bo = gem_to_amdgpu_bo(obj);</div><div class='ctx'> 	if (!(bo-&gt;preferred_domains &amp; (AMDGPU_GEM_DOMAIN_VRAM |</div><div class='del'>-				    AMDGPU_GEM_DOMAIN_GTT))) {</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_GTT)))</div><div class='ctx'> 		/* Only VRAM and GTT BOs are supported */</div><div class='del'>-		ret = -EINVAL;</div><div class='del'>-		goto err_put_obj;</div><div class='del'>-	}</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	*mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);</div><div class='del'>-	if (!*mem) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto err_put_obj;</div><div class='del'>-	}</div><div class='add'>+	if (!*mem)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_vma_node_allow(&amp;obj-&gt;vma_node, drm_priv);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -2372,8 +2381,41 @@ err_remove_mem:</div><div class='ctx'> 	drm_vma_node_revoke(&amp;obj-&gt;vma_node, drm_priv);</div><div class='ctx'> err_free_mem:</div><div class='ctx'> 	kfree(*mem);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,</div><div class='add'>+					 uint64_t va, void *drm_priv,</div><div class='add'>+					 struct kgd_mem **mem, uint64_t *size,</div><div class='add'>+					 uint64_t *mmap_offset)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='add'>+	uint32_t handle;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = drm_gem_prime_fd_to_handle(&amp;adev-&gt;ddev, adev-&gt;kfd.client.file, fd,</div><div class='add'>+					 &amp;handle);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	obj = drm_gem_object_lookup(adev-&gt;kfd.client.file, handle);</div><div class='add'>+	if (!obj) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_handle;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = import_obj_create(adev, obj-&gt;dma_buf, obj, va, drm_priv, mem, size,</div><div class='add'>+				mmap_offset);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_put_obj;</div><div class='add'>+</div><div class='add'>+	(*mem)-&gt;gem_handle = handle;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='ctx'> err_put_obj:</div><div class='ctx'> 	drm_gem_object_put(obj);</div><div class='add'>+err_release_handle:</div><div class='add'>+	drm_gem_handle_delete(adev-&gt;kfd.client.file, handle);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2426,7 +2468,8 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,</div><div class='ctx'> 				       KFD_QUEUE_EVICTION_TRIGGER_USERPTR);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			pr_err("Failed to quiesce KFD\n");</div><div class='del'>-		schedule_delayed_work(&amp;process_info-&gt;restore_userptr_work,</div><div class='add'>+		queue_delayed_work(system_freezable_wq,</div><div class='add'>+			&amp;process_info-&gt;restore_userptr_work,</div><div class='ctx'> 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;process_info-&gt;notifier_lock);</div><div class='hunk'>@@ -2552,7 +2595,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;sync);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	/* Reserve all BOs and page tables for validation */</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		/* Reserve all the page directories */</div><div class='hunk'>@@ -2749,7 +2792,8 @@ unlock_out:</div><div class='ctx'> </div><div class='ctx'> 	/* If validation failed, reschedule another attempt */</div><div class='ctx'> 	if (evicted_bos) {</div><div class='del'>-		schedule_delayed_work(&amp;process_info-&gt;restore_userptr_work,</div><div class='add'>+		queue_delayed_work(system_freezable_wq,</div><div class='add'>+			&amp;process_info-&gt;restore_userptr_work,</div><div class='ctx'> 			msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_queue_restore_rescheduled(mm);</div><div class='hunk'>@@ -2758,6 +2802,23 @@ unlock_out:</div><div class='ctx'> 	put_task_struct(usertask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void replace_eviction_fence(struct dma_fence __rcu **ef,</div><div class='add'>+				   struct dma_fence *new_ef)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true</div><div class='add'>+		/* protected by process_info-&gt;lock */);</div><div class='add'>+</div><div class='add'>+	/* If we're replacing an unsignaled eviction fence, that fence will</div><div class='add'>+	 * never be signaled, and if anyone is still waiting on that fence,</div><div class='add'>+	 * they will hang forever. This should never happen. We should only</div><div class='add'>+	 * replace the fence in restore_work that only gets scheduled after</div><div class='add'>+	 * eviction work signaled the fence.</div><div class='add'>+	 */</div><div class='add'>+	WARN_ONCE(!dma_fence_is_signaled(old_ef),</div><div class='add'>+		  "Replacing unsignaled eviction fence");</div><div class='add'>+	dma_fence_put(old_ef);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given</div><div class='ctx'>  *   KFD process identified by process_info</div><div class='ctx'>  *</div><div class='hunk'>@@ -2776,12 +2837,11 @@ unlock_out:</div><div class='ctx'>  * 7.  Add fence to all PD and PT BOs.</div><div class='ctx'>  * 8.  Unreserve all BOs</div><div class='ctx'>  */</div><div class='del'>-int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)</div><div class='add'>+int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdkfd_process_info *process_info = info;</div><div class='ctx'> 	struct amdgpu_vm *peer_vm;</div><div class='ctx'> 	struct kgd_mem *mem;</div><div class='del'>-	struct amdgpu_amdkfd_fence *new_fence;</div><div class='ctx'> 	struct list_head duplicate_save;</div><div class='ctx'> 	struct amdgpu_sync sync_obj;</div><div class='ctx'> 	unsigned long failed_size = 0;</div><div class='hunk'>@@ -2793,7 +2853,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;process_info-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		list_for_each_entry(peer_vm, &amp;process_info-&gt;vm_list_head,</div><div class='ctx'> 				    vm_list_node) {</div><div class='hunk'>@@ -2825,12 +2885,6 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto validate_map_fail;</div><div class='ctx'> </div><div class='del'>-	ret = process_sync_pds_resv(process_info, &amp;sync_obj);</div><div class='del'>-	if (ret) {</div><div class='del'>-		pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");</div><div class='del'>-		goto validate_map_fail;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Validate BOs and map them to GPUVM (update VM page tables). */</div><div class='ctx'> 	list_for_each_entry(mem, &amp;process_info-&gt;kfd_bo_list,</div><div class='ctx'> 			    validate_list) {</div><div class='hunk'>@@ -2881,6 +2935,19 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)</div><div class='ctx'> 	if (failed_size)</div><div class='ctx'> 		pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);</div><div class='ctx'> </div><div class='add'>+	/* Update mappings not managed by KFD */</div><div class='add'>+	list_for_each_entry(peer_vm, &amp;process_info-&gt;vm_list_head,</div><div class='add'>+			vm_list_node) {</div><div class='add'>+		struct amdgpu_device *adev = amdgpu_ttm_adev(</div><div class='add'>+			peer_vm-&gt;root.bo-&gt;tbo.bdev);</div><div class='add'>+</div><div class='add'>+		ret = amdgpu_vm_handle_moved(adev, peer_vm, &amp;exec.ticket);</div><div class='add'>+		if (ret) {</div><div class='add'>+			pr_debug("Memory eviction: handle moved failed. Try again\n");</div><div class='add'>+			goto validate_map_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Update page directories */</div><div class='ctx'> 	ret = process_update_pds(process_info, &amp;sync_obj);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2888,25 +2955,47 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)</div><div class='ctx'> 		goto validate_map_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Sync with fences on all the page tables. They implicitly depend on any</div><div class='add'>+	 * move fences from amdgpu_vm_handle_moved above.</div><div class='add'>+	 */</div><div class='add'>+	ret = process_sync_pds_resv(process_info, &amp;sync_obj);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");</div><div class='add'>+		goto validate_map_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Wait for validate and PT updates to finish */</div><div class='ctx'> 	amdgpu_sync_wait(&amp;sync_obj, false);</div><div class='ctx'> </div><div class='del'>-	/* Release old eviction fence and create new one, because fence only</div><div class='del'>-	 * goes from unsignaled to signaled, fence cannot be reused.</div><div class='del'>-	 * Use context and mm from the old fence.</div><div class='add'>+	/* The old eviction fence may be unsignaled if restore happens</div><div class='add'>+	 * after a GPU reset or suspend/resume. Keep the old fence in that</div><div class='add'>+	 * case. Otherwise release the old eviction fence and create new</div><div class='add'>+	 * one, because fence only goes from unsignaled to signaled once</div><div class='add'>+	 * and cannot be reused. Use context and mm from the old fence.</div><div class='add'>+	 *</div><div class='add'>+	 * If an old eviction fence signals after this check, that's OK.</div><div class='add'>+	 * Anyone signaling an eviction fence must stop the queues first</div><div class='add'>+	 * and schedule another restore worker.</div><div class='ctx'> 	 */</div><div class='del'>-	new_fence = amdgpu_amdkfd_fence_create(</div><div class='add'>+	if (dma_fence_is_signaled(&amp;process_info-&gt;eviction_fence-&gt;base)) {</div><div class='add'>+		struct amdgpu_amdkfd_fence *new_fence =</div><div class='add'>+			amdgpu_amdkfd_fence_create(</div><div class='ctx'> 				process_info-&gt;eviction_fence-&gt;base.context,</div><div class='ctx'> 				process_info-&gt;eviction_fence-&gt;mm,</div><div class='ctx'> 				NULL);</div><div class='del'>-	if (!new_fence) {</div><div class='del'>-		pr_err("Failed to create eviction fence\n");</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto validate_map_fail;</div><div class='add'>+</div><div class='add'>+		if (!new_fence) {</div><div class='add'>+			pr_err("Failed to create eviction fence\n");</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto validate_map_fail;</div><div class='add'>+		}</div><div class='add'>+		dma_fence_put(&amp;process_info-&gt;eviction_fence-&gt;base);</div><div class='add'>+		process_info-&gt;eviction_fence = new_fence;</div><div class='add'>+		replace_eviction_fence(ef, dma_fence_get(&amp;new_fence-&gt;base));</div><div class='add'>+	} else {</div><div class='add'>+		WARN_ONCE(*ef != &amp;process_info-&gt;eviction_fence-&gt;base,</div><div class='add'>+			  "KFD eviction fence doesn't match KGD process_info");</div><div class='ctx'> 	}</div><div class='del'>-	dma_fence_put(&amp;process_info-&gt;eviction_fence-&gt;base);</div><div class='del'>-	process_info-&gt;eviction_fence = new_fence;</div><div class='del'>-	*ef = dma_fence_get(&amp;new_fence-&gt;base);</div><div class='ctx'> </div><div class='ctx'> 	/* Attach new eviction fence to all BOs except pinned ones */</div><div class='ctx'> 	list_for_each_entry(mem, &amp;process_info-&gt;kfd_bo_list, validate_list) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c<br/>index 7473a42f7d45..9caba10315a8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c</a></div><div class='hunk'>@@ -103,7 +103,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='ctx'> 	struct amdgpu_connector_atom_dig *dig_connector;</div><div class='ctx'> 	int bpc = 8;</div><div class='del'>-	unsigned mode_clock, max_tmds_clock;</div><div class='add'>+	unsigned int mode_clock, max_tmds_clock;</div><div class='ctx'> </div><div class='ctx'> 	switch (connector-&gt;connector_type) {</div><div class='ctx'> 	case DRM_MODE_CONNECTOR_DVII:</div><div class='hunk'>@@ -255,6 +255,7 @@ struct edid *amdgpu_connector_edid(struct drm_connector *connector)</div><div class='ctx'> 		return amdgpu_connector-&gt;edid;</div><div class='ctx'> 	} else if (edid_blob) {</div><div class='ctx'> 		struct edid *edid = kmemdup(edid_blob-&gt;data, edid_blob-&gt;length, GFP_KERNEL);</div><div class='add'>+</div><div class='ctx'> 		if (edid)</div><div class='ctx'> 			amdgpu_connector-&gt;edid = edid;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -581,6 +582,7 @@ static int amdgpu_connector_set_property(struct drm_connector *connector,</div><div class='ctx'> 			amdgpu_encoder = to_amdgpu_encoder(connector-&gt;encoder);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			const struct drm_connector_helper_funcs *connector_funcs = connector-&gt;helper_private;</div><div class='add'>+</div><div class='ctx'> 			amdgpu_encoder = to_amdgpu_encoder(connector_funcs-&gt;best_encoder(connector));</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -797,6 +799,7 @@ static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,</div><div class='ctx'> 		amdgpu_encoder = to_amdgpu_encoder(connector-&gt;encoder);</div><div class='ctx'> 	else {</div><div class='ctx'> 		const struct drm_connector_helper_funcs *connector_funcs = connector-&gt;helper_private;</div><div class='add'>+</div><div class='ctx'> 		amdgpu_encoder = to_amdgpu_encoder(connector_funcs-&gt;best_encoder(connector));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -979,6 +982,41 @@ amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_connector_shared_ddc(enum drm_connector_status *status,</div><div class='add'>+					struct drm_connector *connector,</div><div class='add'>+					struct amdgpu_connector *amdgpu_connector)</div><div class='add'>+{</div><div class='add'>+	struct drm_connector *list_connector;</div><div class='add'>+	struct drm_connector_list_iter iter;</div><div class='add'>+	struct amdgpu_connector *list_amdgpu_connector;</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+</div><div class='add'>+	if (amdgpu_connector-&gt;shared_ddc &amp;&amp; *status == connector_status_connected) {</div><div class='add'>+		drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='add'>+		drm_for_each_connector_iter(list_connector,</div><div class='add'>+					    &amp;iter) {</div><div class='add'>+			if (connector == list_connector)</div><div class='add'>+				continue;</div><div class='add'>+			list_amdgpu_connector = to_amdgpu_connector(list_connector);</div><div class='add'>+			if (list_amdgpu_connector-&gt;shared_ddc &amp;&amp;</div><div class='add'>+			    list_amdgpu_connector-&gt;ddc_bus-&gt;rec.i2c_id ==</div><div class='add'>+			     amdgpu_connector-&gt;ddc_bus-&gt;rec.i2c_id) {</div><div class='add'>+				/* cases where both connectors are digital */</div><div class='add'>+				if (list_connector-&gt;connector_type != DRM_MODE_CONNECTOR_VGA) {</div><div class='add'>+					/* hpd is our only option in this case */</div><div class='add'>+					if (!amdgpu_display_hpd_sense(adev,</div><div class='add'>+								      amdgpu_connector-&gt;hpd.hpd)) {</div><div class='add'>+						amdgpu_connector_free_edid(connector);</div><div class='add'>+						*status = connector_status_disconnected;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		drm_connector_list_iter_end(&amp;iter);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * DVI is complicated</div><div class='ctx'>  * Do a DDC probe, if DDC probe passes, get the full EDID so</div><div class='hunk'>@@ -1065,32 +1103,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)</div><div class='ctx'> 			 * DDC line.  The latter is more complex because with DVI&lt;-&gt;HDMI adapters</div><div class='ctx'> 			 * you don't really know what's connected to which port as both are digital.</div><div class='ctx'> 			 */</div><div class='del'>-			if (amdgpu_connector-&gt;shared_ddc &amp;&amp; (ret == connector_status_connected)) {</div><div class='del'>-				struct drm_connector *list_connector;</div><div class='del'>-				struct drm_connector_list_iter iter;</div><div class='del'>-				struct amdgpu_connector *list_amdgpu_connector;</div><div class='del'>-</div><div class='del'>-				drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='del'>-				drm_for_each_connector_iter(list_connector,</div><div class='del'>-							    &amp;iter) {</div><div class='del'>-					if (connector == list_connector)</div><div class='del'>-						continue;</div><div class='del'>-					list_amdgpu_connector = to_amdgpu_connector(list_connector);</div><div class='del'>-					if (list_amdgpu_connector-&gt;shared_ddc &amp;&amp;</div><div class='del'>-					    (list_amdgpu_connector-&gt;ddc_bus-&gt;rec.i2c_id ==</div><div class='del'>-					     amdgpu_connector-&gt;ddc_bus-&gt;rec.i2c_id)) {</div><div class='del'>-						/* cases where both connectors are digital */</div><div class='del'>-						if (list_connector-&gt;connector_type != DRM_MODE_CONNECTOR_VGA) {</div><div class='del'>-							/* hpd is our only option in this case */</div><div class='del'>-							if (!amdgpu_display_hpd_sense(adev, amdgpu_connector-&gt;hpd.hpd)) {</div><div class='del'>-								amdgpu_connector_free_edid(connector);</div><div class='del'>-								ret = connector_status_disconnected;</div><div class='del'>-							}</div><div class='del'>-						}</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-				drm_connector_list_iter_end(&amp;iter);</div><div class='del'>-			}</div><div class='add'>+			amdgpu_connector_shared_ddc(&amp;ret, connector, amdgpu_connector);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1192,6 +1205,7 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector)</div><div class='ctx'> static void amdgpu_connector_dvi_force(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);</div><div class='add'>+</div><div class='ctx'> 	if (connector-&gt;force == DRM_FORCE_ON)</div><div class='ctx'> 		amdgpu_connector-&gt;use_digital = false;</div><div class='ctx'> 	if (connector-&gt;force == DRM_FORCE_ON_DIGITAL)</div><div class='hunk'>@@ -1426,6 +1440,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)</div><div class='ctx'> 				ret = connector_status_connected;</div><div class='ctx'> 			else if (amdgpu_connector-&gt;dac_load_detect) { /* try load detection */</div><div class='ctx'> 				const struct drm_encoder_helper_funcs *encoder_funcs = encoder-&gt;helper_private;</div><div class='add'>+</div><div class='ctx'> 				ret = encoder_funcs-&gt;detect(encoder, connector);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c<br/>index e50be6500030..6adeddfb3d56 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c</a></div><div class='hunk'>@@ -66,7 +66,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;p-&gt;sync);</div><div class='ctx'> 	drm_exec_init(&amp;p-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT |</div><div class='del'>-		      DRM_EXEC_IGNORE_DUPLICATES);</div><div class='add'>+		      DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -870,9 +870,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,</div><div class='ctx'> 		struct amdgpu_bo *bo = e-&gt;bo;</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='del'>-		e-&gt;user_pages = kvmalloc_array(bo-&gt;tbo.ttm-&gt;num_pages,</div><div class='del'>-					sizeof(struct page *),</div><div class='del'>-					GFP_KERNEL | __GFP_ZERO);</div><div class='add'>+		e-&gt;user_pages = kvcalloc(bo-&gt;tbo.ttm-&gt;num_pages,</div><div class='add'>+					 sizeof(struct page *),</div><div class='add'>+					 GFP_KERNEL);</div><div class='ctx'> 		if (!e-&gt;user_pages) {</div><div class='ctx'> 			DRM_ERROR("kvmalloc_array failure\n");</div><div class='ctx'> 			r = -ENOMEM;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c<br/>index 720011019741..796fa6f1420b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c</a></div><div class='hunk'>@@ -70,7 +70,7 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='ctx'> 		if (likely(!r))</div><div class='hunk'>@@ -110,7 +110,7 @@ int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='ctx'> 		if (likely(!r))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c<br/>index c1efa13bccbb..e485dd3357c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c</a></div><div class='hunk'>@@ -540,7 +540,11 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,</div><div class='ctx'> 	while (size) {</div><div class='ctx'> 		uint32_t value;</div><div class='ctx'> </div><div class='del'>-		value = RREG32_PCIE(*pos);</div><div class='add'>+		if (upper_32_bits(*pos))</div><div class='add'>+			value = RREG32_PCIE_EXT(*pos);</div><div class='add'>+		else</div><div class='add'>+			value = RREG32_PCIE(*pos);</div><div class='add'>+</div><div class='ctx'> 		r = put_user(value, (uint32_t *)buf);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -600,7 +604,10 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			goto out;</div><div class='ctx'> </div><div class='del'>-		WREG32_PCIE(*pos, value);</div><div class='add'>+		if (upper_32_bits(*pos))</div><div class='add'>+			WREG32_PCIE_EXT(*pos, value);</div><div class='add'>+		else</div><div class='add'>+			WREG32_PCIE(*pos, value);</div><div class='ctx'> </div><div class='ctx'> 		result += 4;</div><div class='ctx'> 		buf += 4;</div><div class='hunk'>@@ -638,6 +645,9 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,</div><div class='ctx'> 	if (size &amp; 0x3 || *pos &amp; 0x3)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!adev-&gt;didt_rreg)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	if (r &lt; 0) {</div><div class='ctx'> 		pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='hunk'>@@ -694,6 +704,9 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user</div><div class='ctx'> 	if (size &amp; 0x3 || *pos &amp; 0x3)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (!adev-&gt;didt_wreg)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	if (r &lt; 0) {</div><div class='ctx'> 		pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='hunk'>@@ -749,7 +762,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;smc_rreg)</div><div class='del'>-		return -EPERM;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (size &amp; 0x3 || *pos &amp; 0x3)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -808,7 +821,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;smc_wreg)</div><div class='del'>-		return -EPERM;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (size &amp; 0x3 || *pos &amp; 0x3)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2141,6 +2154,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_debugfs_firmware_init(adev);</div><div class='ctx'> 	amdgpu_ta_if_debugfs_init(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_debugfs_mes_event_log_init(adev);</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC)</div><div class='ctx'> 	if (adev-&gt;dc_enabled)</div><div class='ctx'> 		dtn_debugfs_init(adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h<br/>index 371a6f0deb29..0425432d8659 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h</a></div><div class='hunk'>@@ -32,3 +32,5 @@ void amdgpu_debugfs_fini(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_fence_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_debugfs_gem_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br/>index 2a6684a38714..b158d27d0a71 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c</a></div><div class='hunk'>@@ -162,6 +162,65 @@ static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,</div><div class='ctx'> static DEVICE_ATTR(pcie_replay_count, 0444,</div><div class='ctx'> 		amdgpu_device_get_pcie_replay_count, NULL);</div><div class='ctx'> </div><div class='add'>+static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,</div><div class='add'>+					  struct bin_attribute *attr, char *buf,</div><div class='add'>+					  loff_t ppos, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	ssize_t bytes_read;</div><div class='add'>+</div><div class='add'>+	switch (ppos) {</div><div class='add'>+	case AMDGPU_SYS_REG_STATE_XGMI:</div><div class='add'>+		bytes_read = amdgpu_asic_get_reg_state(</div><div class='add'>+			adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_SYS_REG_STATE_WAFL:</div><div class='add'>+		bytes_read = amdgpu_asic_get_reg_state(</div><div class='add'>+			adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_SYS_REG_STATE_PCIE:</div><div class='add'>+		bytes_read = amdgpu_asic_get_reg_state(</div><div class='add'>+			adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_SYS_REG_STATE_USR:</div><div class='add'>+		bytes_read = amdgpu_asic_get_reg_state(</div><div class='add'>+			adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_SYS_REG_STATE_USR_1:</div><div class='add'>+		bytes_read = amdgpu_asic_get_reg_state(</div><div class='add'>+			adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return bytes_read;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,</div><div class='add'>+	 AMDGPU_SYS_REG_STATE_END);</div><div class='add'>+</div><div class='add'>+int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!amdgpu_asic_get_reg_state_supported(adev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = sysfs_create_bin_file(&amp;adev-&gt;dev-&gt;kobj, &amp;bin_attr_reg_state);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	if (!amdgpu_asic_get_reg_state_supported(adev))</div><div class='add'>+		return;</div><div class='add'>+	sysfs_remove_bin_file(&amp;adev-&gt;dev-&gt;kobj, &amp;bin_attr_reg_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: board_info</div><div class='ctx'>  *</div><div class='hunk'>@@ -1485,6 +1544,7 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)</div><div class='ctx'> 				return true;</div><div class='ctx'> </div><div class='ctx'> 			fw_ver = *((uint32_t *)adev-&gt;pm.fw-&gt;data + 69);</div><div class='add'>+			release_firmware(adev-&gt;pm.fw);</div><div class='ctx'> 			if (fw_ver &lt; 0x00160e00)</div><div class='ctx'> 				return true;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1540,7 +1600,7 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;mman.keep_stolen_vga_memory)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	return adev-&gt;ip_versions[DCE_HWIP][0] &gt;= IP_VERSION(3, 0, 0);</div><div class='add'>+	return amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(3, 0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1551,11 +1611,15 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)</div><div class='ctx'>  * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/</div><div class='ctx'>  * https://gitlab.freedesktop.org/drm/amd/-/issues/2663</div><div class='ctx'>  */</div><div class='del'>-static bool amdgpu_device_pcie_dynamic_switching_supported(void)</div><div class='add'>+static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> #if IS_ENABLED(CONFIG_X86)</div><div class='ctx'> 	struct cpuinfo_x86 *c = &amp;cpu_data(0);</div><div class='ctx'> </div><div class='add'>+	/* eGPU change speeds based on USB4 fabric conditions */</div><div class='add'>+	if (dev_is_removable(adev-&gt;dev))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	if (c-&gt;x86_vendor == X86_VENDOR_INTEL)</div><div class='ctx'> 		return false;</div><div class='ctx'> #endif</div><div class='hunk'>@@ -2188,15 +2252,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	adev-&gt;firmware.gpu_info_fw = NULL;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;mman.discovery_bin) {</div><div class='del'>-		/*</div><div class='del'>-		 * FIXME: The bounding box is still needed by Navi12, so</div><div class='del'>-		 * temporarily read it from gpu_info firmware. Should be dropped</div><div class='del'>-		 * when DAL no longer needs it.</div><div class='del'>-		 */</div><div class='del'>-		if (adev-&gt;asic_type != CHIP_NAVI12)</div><div class='del'>-			return 0;</div><div class='del'>-	}</div><div class='add'>+	if (adev-&gt;mman.discovery_bin)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (adev-&gt;asic_type) {</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -2395,7 +2452,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;pm.pp_feature &amp;= ~PP_GFXOFF_MASK;</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;asic_type == CHIP_SIENNA_CICHLID)</div><div class='ctx'> 		adev-&gt;pm.pp_feature &amp;= ~PP_OVERDRIVE_MASK;</div><div class='del'>-	if (!amdgpu_device_pcie_dynamic_switching_supported())</div><div class='add'>+	if (!amdgpu_device_pcie_dynamic_switching_supported(adev))</div><div class='ctx'> 		adev-&gt;pm.pp_feature &amp;= ~PP_PCIE_DPM_MASK;</div><div class='ctx'> </div><div class='ctx'> 	total = true;</div><div class='hunk'>@@ -2676,6 +2733,12 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)</div><div class='ctx'> 					goto init_failed;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			r = amdgpu_seq64_init(adev);</div><div class='add'>+			if (r) {</div><div class='add'>+				DRM_ERROR("allocate seq64 failed %d\n", r);</div><div class='add'>+				goto init_failed;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3138,6 +3201,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)</div><div class='ctx'> 			amdgpu_device_wb_fini(adev);</div><div class='ctx'> 			amdgpu_device_mem_scratch_fini(adev);</div><div class='ctx'> 			amdgpu_ib_pool_fini(adev);</div><div class='add'>+			amdgpu_seq64_fini(adev);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		r = adev-&gt;ip_blocks[i].version-&gt;funcs-&gt;sw_fini((void *)adev);</div><div class='hunk'>@@ -3791,10 +3855,6 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)</div><div class='ctx'> 		adev-&gt;gfx.mcbp = true;</div><div class='ctx'> 	else if (amdgpu_mcbp == 0)</div><div class='ctx'> 		adev-&gt;gfx.mcbp = false;</div><div class='del'>-	else if ((amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(9, 0, 0)) &amp;&amp;</div><div class='del'>-		 (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(10, 0, 0)) &amp;&amp;</div><div class='del'>-		 adev-&gt;gfx.num_gfx_rings)</div><div class='del'>-		adev-&gt;gfx.mcbp = true;</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		adev-&gt;gfx.mcbp = true;</div><div class='hunk'>@@ -4222,6 +4282,7 @@ fence_driver_init:</div><div class='ctx'> 			"Could not create amdgpu board attributes\n");</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_fru_sysfs_init(adev);</div><div class='add'>+	amdgpu_reg_state_sysfs_init(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ENABLED(CONFIG_PERF_EVENTS))</div><div class='ctx'> 		r = amdgpu_pmu_init(adev);</div><div class='hunk'>@@ -4344,6 +4405,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)</div><div class='ctx'> 	sysfs_remove_files(&amp;adev-&gt;dev-&gt;kobj, amdgpu_dev_attributes);</div><div class='ctx'> 	amdgpu_fru_sysfs_fini(adev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_reg_state_sysfs_fini(adev);</div><div class='add'>+</div><div class='ctx'> 	/* disable ras feature must before hw fini */</div><div class='ctx'> 	amdgpu_ras_pre_fini(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -4520,8 +4583,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_suspend(adev);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ttm_set_buffer_funcs_status(adev, false);</div><div class='del'>-</div><div class='ctx'> 	amdgpu_device_ip_suspend_phase1(adev);</div><div class='ctx'> </div><div class='ctx'> 	if (!adev-&gt;in_s0ix)</div><div class='hunk'>@@ -4531,6 +4592,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='add'>+	amdgpu_ttm_set_buffer_funcs_status(adev, false);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_fence_driver_hw_fini(adev);</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_device_ip_suspend_phase2(adev);</div><div class='hunk'>@@ -4538,6 +4601,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		amdgpu_virt_release_full_gpu(adev, false);</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_dpm_notify_rlc_state(adev, false);</div><div class='add'>+	if (r)</div><div class='add'>+		return r;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5179,7 +5246,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 	struct amdgpu_device *tmp_adev = NULL;</div><div class='ctx'> 	bool need_full_reset, skip_hw_reset, vram_lost = false;</div><div class='ctx'> 	int r = 0;</div><div class='del'>-	bool gpu_reset_for_dev_remove = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Try reset handler method first */</div><div class='ctx'> 	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='hunk'>@@ -5199,10 +5265,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 		test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> 	skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> </div><div class='del'>-	gpu_reset_for_dev_remove =</div><div class='del'>-		test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &amp;reset_context-&gt;flags) &amp;&amp;</div><div class='del'>-			test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * ASIC reset has to be done on all XGMI hive nodes ASAP</div><div class='ctx'> 	 * to allow proper links negotiation in FW (within 1 sec)</div><div class='hunk'>@@ -5245,18 +5307,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,</div><div class='ctx'> 		amdgpu_ras_intr_cleared();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Since the mode1 reset affects base ip blocks, the</div><div class='del'>-	 * phase1 ip blocks need to be resumed. Otherwise there</div><div class='del'>-	 * will be a BIOS signature error and the psp bootloader</div><div class='del'>-	 * can't load kdb on the next amdgpu install.</div><div class='del'>-	 */</div><div class='del'>-	if (gpu_reset_for_dev_remove) {</div><div class='del'>-		list_for_each_entry(tmp_adev, device_list_handle, reset_list)</div><div class='del'>-			amdgpu_device_ip_resume_phase1(tmp_adev);</div><div class='del'>-</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='ctx'> 		if (need_full_reset) {</div><div class='ctx'> 			/* post card */</div><div class='hunk'>@@ -5493,11 +5543,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='ctx'> 	int i, r = 0;</div><div class='ctx'> 	bool need_emergency_restart = false;</div><div class='ctx'> 	bool audio_suspended = false;</div><div class='del'>-	bool gpu_reset_for_dev_remove = false;</div><div class='del'>-</div><div class='del'>-	gpu_reset_for_dev_remove =</div><div class='del'>-			test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &amp;reset_context-&gt;flags) &amp;&amp;</div><div class='del'>-				test_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Special case: RAS triggered and full reset isn't supported</div><div class='hunk'>@@ -5535,7 +5580,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev) &amp;&amp; (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1)) {</div><div class='ctx'> 		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='ctx'> 			list_add_tail(&amp;tmp_adev-&gt;reset_list, &amp;device_list);</div><div class='del'>-			if (gpu_reset_for_dev_remove &amp;&amp; adev-&gt;shutdown)</div><div class='add'>+			if (adev-&gt;shutdown)</div><div class='ctx'> 				tmp_adev-&gt;shutdown = true;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (!list_is_first(&amp;adev-&gt;reset_list, &amp;device_list))</div><div class='hunk'>@@ -5620,10 +5665,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> retry:	/* Rest of adevs pre asic reset from XGMI hive. */</div><div class='ctx'> 	list_for_each_entry(tmp_adev, device_list_handle, reset_list) {</div><div class='del'>-		if (gpu_reset_for_dev_remove) {</div><div class='del'>-			/* Workaroud for ASICs need to disable SMC first */</div><div class='del'>-			amdgpu_device_smu_fini_early(tmp_adev);</div><div class='del'>-		}</div><div class='ctx'> 		r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);</div><div class='ctx'> 		/*TODO Should we stop ?*/</div><div class='ctx'> 		if (r) {</div><div class='hunk'>@@ -5655,9 +5696,6 @@ retry:	/* Rest of adevs pre asic reset from XGMI hive. */</div><div class='ctx'> 		r = amdgpu_do_asic_reset(device_list_handle, reset_context);</div><div class='ctx'> 		if (r &amp;&amp; r == -EAGAIN)</div><div class='ctx'> 			goto retry;</div><div class='del'>-</div><div class='del'>-		if (!r &amp;&amp; gpu_reset_for_dev_remove)</div><div class='del'>-			goto recover_end;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> skip_hw_reset:</div><div class='hunk'>@@ -5713,7 +5751,6 @@ skip_sched_resume:</div><div class='ctx'> 		amdgpu_ras_set_error_query_ready(tmp_adev, true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-recover_end:</div><div class='ctx'> 	tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,</div><div class='ctx'> 					    reset_list);</div><div class='ctx'> 	amdgpu_device_unlock_reset_domain(tmp_adev-&gt;reset_domain);</div><div class='hunk'>@@ -5731,6 +5768,39 @@ recover_end:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @speed: pointer to the speed of the link</div><div class='add'>+ * @width: pointer to the width of the link</div><div class='add'>+ *</div><div class='add'>+ * Evaluate the hierarchy to find the speed and bandwidth capabilities of the</div><div class='add'>+ * first physical partner to an AMD dGPU.</div><div class='add'>+ * This will exclude any virtual switches and links.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,</div><div class='add'>+					    enum pci_bus_speed *speed,</div><div class='add'>+					    enum pcie_link_width *width)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *parent = adev-&gt;pdev;</div><div class='add'>+</div><div class='add'>+	if (!speed || !width)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	*speed = PCI_SPEED_UNKNOWN;</div><div class='add'>+	*width = PCIE_LNK_WIDTH_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	while ((parent = pci_upstream_bridge(parent))) {</div><div class='add'>+		/* skip upstream/downstream switches internal to dGPU*/</div><div class='add'>+		if (parent-&gt;vendor == PCI_VENDOR_ID_ATI)</div><div class='add'>+			continue;</div><div class='add'>+		*speed = pcie_get_speed_cap(parent);</div><div class='add'>+		*width = pcie_get_width_cap(parent);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='hunk'>@@ -5763,8 +5833,8 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;pm.pcie_gen_mask &amp;&amp; adev-&gt;pm.pcie_mlw_mask)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	pcie_bandwidth_available(adev-&gt;pdev, NULL,</div><div class='del'>-				 &amp;platform_speed_cap, &amp;platform_link_width);</div><div class='add'>+	amdgpu_device_partner_bandwidth(adev, &amp;platform_speed_cap,</div><div class='add'>+					&amp;platform_link_width);</div><div class='ctx'> </div><div class='ctx'> 	if (adev-&gt;pm.pcie_gen_mask == 0) {</div><div class='ctx'> 		/* asic caps */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c<br/>index 0431eafa86b5..c7d60dd0fb97 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c</a></div><div class='hunk'>@@ -1963,8 +1963,6 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gfx_v9_0_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(9, 4, 3):</div><div class='del'>-		if (!amdgpu_exp_hw_support)</div><div class='del'>-			return -EINVAL;</div><div class='ctx'> 		amdgpu_device_ip_block_add(adev, &amp;gfx_v9_4_3_ip_block);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IP_VERSION(10, 1, 10):</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c<br/>index 0cacd0b9f8be..b8fbe97efe1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_display.c</a></div><div class='hunk'>@@ -340,14 +340,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set,</div><div class='ctx'> 		adev-&gt;have_disp_power_ref = true;</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='del'>-	/* if we have no active crtcs, then drop the power ref</div><div class='del'>-	 * we got before</div><div class='add'>+	/* if we have no active crtcs, then go to</div><div class='add'>+	 * drop the power ref we got before</div><div class='ctx'> 	 */</div><div class='del'>-	if (!active &amp;&amp; adev-&gt;have_disp_power_ref) {</div><div class='del'>-		pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='add'>+	if (!active &amp;&amp; adev-&gt;have_disp_power_ref)</div><div class='ctx'> 		adev-&gt;have_disp_power_ref = false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> out:</div><div class='ctx'> 	/* drop the power reference we got coming in here */</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c<br/>index e7e87a3b2601..decbbe3d4f06 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c</a></div><div class='hunk'>@@ -42,6 +42,7 @@</div><div class='ctx'> #include &lt;linux/dma-fence-array.h&gt;</div><div class='ctx'> #include &lt;linux/pci-p2pdma.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include "amdgpu_trace.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dma_buf_attach - &amp;dma_buf_ops.attach implementation</div><div class='hunk'>@@ -63,6 +64,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,</div><div class='ctx'> 		attach-&gt;peer2peer = false;</div><div class='ctx'> </div><div class='ctx'> 	r = pm_runtime_get_sync(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+	trace_amdgpu_runpm_reference_dumps(1, __func__);</div><div class='ctx'> 	if (r &lt; 0)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -70,6 +72,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+	trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -90,6 +93,7 @@ static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+	trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c<br/>index 8f24cabe2155..cc69005f5b46 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</a></div><div class='hunk'>@@ -115,9 +115,10 @@</div><div class='ctx'>  *   3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support</div><div class='ctx'>  * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query</div><div class='ctx'>  * - 3.56.0 - Update IB start address and size alignment for decode and encode</div><div class='add'>+ * - 3.57.0 - Compute tunneling on GFX10+</div><div class='ctx'>  */</div><div class='ctx'> #define KMS_DRIVER_MAJOR	3</div><div class='del'>-#define KMS_DRIVER_MINOR	56</div><div class='add'>+#define KMS_DRIVER_MINOR	57</div><div class='ctx'> #define KMS_DRIVER_PATCHLEVEL	0</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -127,6 +128,7 @@ enum AMDGPU_DEBUG_MASK {</div><div class='ctx'> 	AMDGPU_DEBUG_VM = BIT(0),</div><div class='ctx'> 	AMDGPU_DEBUG_LARGEBAR = BIT(1),</div><div class='ctx'> 	AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),</div><div class='add'>+	AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> unsigned int amdgpu_vram_limit = UINT_MAX;</div><div class='hunk'>@@ -208,6 +210,7 @@ int amdgpu_umsch_mm;</div><div class='ctx'> int amdgpu_seamless = -1; /* auto */</div><div class='ctx'> uint amdgpu_debug_mask;</div><div class='ctx'> int amdgpu_agp = -1; /* auto */</div><div class='add'>+int amdgpu_wbrf = -1;</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);</div><div class='ctx'> </div><div class='hunk'>@@ -971,6 +974,22 @@ module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);</div><div class='ctx'> MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");</div><div class='ctx'> module_param_named(agp, amdgpu_agp, int, 0444);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * DOC: wbrf (int)</div><div class='add'>+ * Enable Wifi RFI interference mitigation feature.</div><div class='add'>+ * Due to electrical and mechanical constraints there may be likely interference of</div><div class='add'>+ * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio</div><div class='add'>+ * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,</div><div class='add'>+ * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based</div><div class='add'>+ * on active list of frequencies in-use (to be avoided) as part of initial setting or</div><div class='add'>+ * P-state transition. However, there may be potential performance impact with this</div><div class='add'>+ * feature enabled.</div><div class='add'>+ * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))</div><div class='add'>+ */</div><div class='add'>+MODULE_PARM_DESC(wbrf,</div><div class='add'>+	"Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");</div><div class='add'>+module_param_named(wbrf, amdgpu_wbrf, int, 0444);</div><div class='add'>+</div><div class='ctx'> /* These devices are not supported by amdgpu.</div><div class='ctx'>  * They are supported by the mach64, r128, radeon drivers</div><div class='ctx'>  */</div><div class='hunk'>@@ -2099,6 +2118,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev)</div><div class='ctx'> 		pr_info("debug: soft reset for GPU recovery disabled\n");</div><div class='ctx'> 		adev-&gt;debug_disable_soft_recovery = true;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_debug_mask &amp; AMDGPU_DEBUG_USE_VRAM_FW_BUF) {</div><div class='add'>+		pr_info("debug: place fw in vram for frontdoor loading\n");</div><div class='add'>+		adev-&gt;debug_use_vram_fw_buf = true;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)</div><div class='hunk'>@@ -2210,6 +2234,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	pci_set_drvdata(pdev, ddev);</div><div class='ctx'> </div><div class='add'>+	amdgpu_init_debug_options(adev);</div><div class='add'>+</div><div class='ctx'> 	ret = amdgpu_driver_load_kms(adev, flags);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_pci;</div><div class='hunk'>@@ -2263,6 +2289,8 @@ retry_init:</div><div class='ctx'> 		pm_runtime_mark_last_busy(ddev-&gt;dev);</div><div class='ctx'> 		pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='ctx'> </div><div class='add'>+		pci_wake_from_d3(pdev, TRUE);</div><div class='add'>+</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * For runpm implemented via BACO, PMFW will handle the</div><div class='ctx'> 		 * timing for BACO in and out:</div><div class='hunk'>@@ -2288,8 +2316,6 @@ retry_init:</div><div class='ctx'> 			amdgpu_get_secondary_funcs(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	amdgpu_init_debug_options(adev);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_pci:</div><div class='hunk'>@@ -2311,38 +2337,6 @@ amdgpu_pci_remove(struct pci_dev *pdev)</div><div class='ctx'> 		pm_runtime_forbid(dev-&gt;dev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &amp;&amp;</div><div class='del'>-	    !amdgpu_sriov_vf(adev)) {</div><div class='del'>-		bool need_to_reset_gpu = false;</div><div class='del'>-</div><div class='del'>-		if (adev-&gt;gmc.xgmi.num_physical_nodes &gt; 1) {</div><div class='del'>-			struct amdgpu_hive_info *hive;</div><div class='del'>-</div><div class='del'>-			hive = amdgpu_get_xgmi_hive(adev);</div><div class='del'>-			if (hive-&gt;device_remove_count == 0)</div><div class='del'>-				need_to_reset_gpu = true;</div><div class='del'>-			hive-&gt;device_remove_count++;</div><div class='del'>-			amdgpu_put_xgmi_hive(hive);</div><div class='del'>-		} else {</div><div class='del'>-			need_to_reset_gpu = true;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Workaround for ASICs need to reset SMU.</div><div class='del'>-		 * Called only when the first device is removed.</div><div class='del'>-		 */</div><div class='del'>-		if (need_to_reset_gpu) {</div><div class='del'>-			struct amdgpu_reset_context reset_context;</div><div class='del'>-</div><div class='del'>-			adev-&gt;shutdown = true;</div><div class='del'>-			memset(&amp;reset_context, 0, sizeof(reset_context));</div><div class='del'>-			reset_context.method = AMD_RESET_METHOD_NONE;</div><div class='del'>-			reset_context.reset_req_dev = adev;</div><div class='del'>-			set_bit(AMDGPU_NEED_FULL_RESET, &amp;reset_context.flags);</div><div class='del'>-			set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &amp;reset_context.flags);</div><div class='del'>-			amdgpu_device_gpu_recover(adev, NULL, &amp;reset_context);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	amdgpu_driver_unload_kms(dev);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c<br/>index dc230212746a..70bff8cecfda 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c</a></div><div class='hunk'>@@ -183,6 +183,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd</div><div class='ctx'> 	amdgpu_ring_emit_fence(ring, ring-&gt;fence_drv.gpu_addr,</div><div class='ctx'> 			       seq, flags | AMDGPU_FENCE_FLAG_INT);</div><div class='ctx'> 	pm_runtime_get_noresume(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+	trace_amdgpu_runpm_reference_dumps(1, __func__);</div><div class='ctx'> 	ptr = &amp;ring-&gt;fence_drv.fences[seq &amp; ring-&gt;fence_drv.num_fences_mask];</div><div class='ctx'> 	if (unlikely(rcu_dereference_protected(*ptr, 1))) {</div><div class='ctx'> 		struct dma_fence *old;</div><div class='hunk'>@@ -310,6 +311,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)</div><div class='ctx'> 		dma_fence_put(fence);</div><div class='ctx'> 		pm_runtime_mark_last_busy(adev_to_drm(adev)-&gt;dev);</div><div class='ctx'> 		pm_runtime_put_autosuspend(adev_to_drm(adev)-&gt;dev);</div><div class='add'>+		trace_amdgpu_runpm_reference_dumps(0, __func__);</div><div class='ctx'> 	} while (last_seq != seq);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c<br/>index 84beeaa4d21c..49a5f1c73b3e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c</a></div><div class='hunk'>@@ -203,7 +203,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_IGNORE_DUPLICATES);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = drm_exec_prepare_obj(&amp;exec, &amp;bo-&gt;tbo.base, 1);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -739,7 +739,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT |</div><div class='del'>-		      DRM_EXEC_IGNORE_DUPLICATES);</div><div class='add'>+		      DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		if (gobj) {</div><div class='ctx'> 			r = drm_exec_lock_obj(&amp;exec, gobj);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c<br/>index 5f71414190e9..55784a9f26c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c</a></div><div class='hunk'>@@ -181,6 +181,9 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;bdev);</div><div class='ctx'> </div><div class='add'>+	if (!bo-&gt;ttm)</div><div class='add'>+		return AMDGPU_BO_INVALID_OFFSET;</div><div class='add'>+</div><div class='ctx'> 	if (bo-&gt;ttm-&gt;num_pages != 1 || bo-&gt;ttm-&gt;caching == ttm_cached)</div><div class='ctx'> 		return AMDGPU_BO_INVALID_OFFSET;</div><div class='ctx'> </div><div class='hunk'>@@ -1042,21 +1045,28 @@ int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)</div><div class='ctx'> 	 * seconds, so here, we just pick up three parts for emulation.</div><div class='ctx'> 	 */</div><div class='ctx'> 	ret = memcmp(vram_ptr, cptr, 10);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto release_buffer;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = memcmp(vram_ptr + (size / 2), cptr, 10);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto release_buffer;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = memcmp(vram_ptr + size - 10, cptr, 10);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto release_buffer;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+release_buffer:</div><div class='ctx'> 	amdgpu_bo_free_kernel(&amp;vram_bo, &amp;vram_gpu,</div><div class='ctx'> 			&amp;vram_ptr);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t current_memory_partition_show(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c<br/>index 081267161d40..55b65fc04b65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c</a></div><div class='hunk'>@@ -190,8 +190,8 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier,</div><div class='ctx'> 		pr_debug("hmm range: start = 0x%lx, end = 0x%lx",</div><div class='ctx'> 			hmm_range-&gt;start, hmm_range-&gt;end);</div><div class='ctx'> </div><div class='del'>-		/* Assuming 128MB takes maximum 1 second to fault page address */</div><div class='del'>-		timeout = max((hmm_range-&gt;end - hmm_range-&gt;start) &gt;&gt; 27, 1UL);</div><div class='add'>+		/* Assuming 64MB takes maximum 1 second to fault page address */</div><div class='add'>+		timeout = max((hmm_range-&gt;end - hmm_range-&gt;start) &gt;&gt; 26, 1UL);</div><div class='ctx'> 		timeout *= HMM_RANGE_DEFAULT_TIMEOUT;</div><div class='ctx'> 		timeout = jiffies + msecs_to_jiffies(timeout);</div><div class='ctx'> </div><div class='hunk'>@@ -199,6 +199,7 @@ retry:</div><div class='ctx'> 		hmm_range-&gt;notifier_seq = mmu_interval_read_begin(notifier);</div><div class='ctx'> 		r = hmm_range_fault(hmm_range);</div><div class='ctx'> 		if (unlikely(r)) {</div><div class='add'>+			schedule();</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * FIXME: This timeout should encompass the retry from</div><div class='ctx'> 			 * mmu_interval_read_retry() as well.</div><div class='hunk'>@@ -212,7 +213,6 @@ retry:</div><div class='ctx'> 			break;</div><div class='ctx'> 		hmm_range-&gt;hmm_pfns += MAX_WALK_BYTE &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 		hmm_range-&gt;start = hmm_range-&gt;end;</div><div class='del'>-		schedule();</div><div class='ctx'> 	} while (hmm_range-&gt;end &lt; end);</div><div class='ctx'> </div><div class='ctx'> 	hmm_range-&gt;start = start;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c<br/>index 82608df43396..d79cb13e1aa8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c</a></div><div class='hunk'>@@ -175,7 +175,6 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	i2c-&gt;rec = *rec;</div><div class='ctx'> 	i2c-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	i2c-&gt;adapter.dev.parent = dev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;dev = dev;</div><div class='ctx'> 	i2c_set_adapdata(&amp;i2c-&gt;adapter, i2c);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br/>index 583cf03950cd..bf4f48fe438d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c</a></div><div class='hunk'>@@ -1105,7 +1105,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)</div><div class='ctx'> 			if (amdgpu_dpm_read_sensor(adev,</div><div class='ctx'> 						   AMDGPU_PP_SENSOR_GPU_AVG_POWER,</div><div class='ctx'> 						   (void *)&amp;ui32, &amp;ui32_size)) {</div><div class='del'>-				return -EINVAL;</div><div class='add'>+				/* fall back to input power for backwards compat */</div><div class='add'>+				if (amdgpu_dpm_read_sensor(adev,</div><div class='add'>+							   AMDGPU_PP_SENSOR_GPU_INPUT_POWER,</div><div class='add'>+							   (void *)&amp;ui32, &amp;ui32_size)) {</div><div class='add'>+					return -EINVAL;</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 			ui32 &gt;&gt;= 8;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1428,6 +1433,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,</div><div class='ctx'> 		fpriv-&gt;csa_va = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	amdgpu_seq64_unmap(adev, fpriv);</div><div class='add'>+</div><div class='ctx'> 	pasid = fpriv-&gt;vm.pasid;</div><div class='ctx'> 	pd = amdgpu_bo_ref(fpriv-&gt;vm.root.bo);</div><div class='ctx'> 	if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c<br/>index cf33eb219e25..59fafb8392e0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c</a></div><div class='hunk'>@@ -218,6 +218,7 @@ static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, st</div><div class='ctx'> int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_smuio_mcm_config_info mcm_info;</div><div class='add'>+	struct ras_err_addr err_addr = {0};</div><div class='ctx'> 	struct mca_bank_set mca_set;</div><div class='ctx'> 	struct mca_bank_node *node;</div><div class='ctx'> 	struct mca_bank_entry *entry;</div><div class='hunk'>@@ -246,10 +247,18 @@ int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_blo</div><div class='ctx'> 		mcm_info.socket_id = entry-&gt;info.socket_id;</div><div class='ctx'> 		mcm_info.die_id = entry-&gt;info.aid;</div><div class='ctx'> </div><div class='add'>+		if (blk == AMDGPU_RAS_BLOCK__UMC) {</div><div class='add'>+			err_addr.err_status = entry-&gt;regs[MCA_REG_IDX_STATUS];</div><div class='add'>+			err_addr.err_ipid = entry-&gt;regs[MCA_REG_IDX_IPID];</div><div class='add'>+			err_addr.err_addr = entry-&gt;regs[MCA_REG_IDX_ADDR];</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (type == AMDGPU_MCA_ERROR_TYPE_UE)</div><div class='del'>-			amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, (uint64_t)count);</div><div class='add'>+			amdgpu_ras_error_statistic_ue_count(err_data,</div><div class='add'>+				&amp;mcm_info, &amp;err_addr, (uint64_t)count);</div><div class='ctx'> 		else</div><div class='del'>-			amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, (uint64_t)count);</div><div class='add'>+			amdgpu_ras_error_statistic_ce_count(err_data,</div><div class='add'>+				&amp;mcm_info, &amp;err_addr, (uint64_t)count);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out_mca_release:</div><div class='hunk'>@@ -351,6 +360,9 @@ int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_err</div><div class='ctx'> 	const struct amdgpu_mca_smu_funcs *mca_funcs = adev-&gt;mca.mca_funcs;</div><div class='ctx'> 	int count;</div><div class='ctx'> </div><div class='add'>+	if (!mca_funcs || !mca_funcs-&gt;mca_get_mca_entry)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	switch (type) {</div><div class='ctx'> 	case AMDGPU_MCA_ERROR_TYPE_UE:</div><div class='ctx'> 		count = mca_funcs-&gt;max_ue_count;</div><div class='hunk'>@@ -365,10 +377,7 @@ int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_err</div><div class='ctx'> 	if (idx &gt;= count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (mca_funcs &amp;&amp; mca_funcs-&gt;mca_get_mca_entry)</div><div class='del'>-		return mca_funcs-&gt;mca_get_mca_entry(adev, type, idx, entry);</div><div class='del'>-</div><div class='del'>-	return -EOPNOTSUPP;</div><div class='add'>+	return mca_funcs-&gt;mca_get_mca_entry(adev, type, idx, entry);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='hunk'>@@ -377,7 +386,7 @@ static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)data;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = amdgpu_mca_smu_set_debug_mode(adev, val ? true : false);</div><div class='add'>+	ret = amdgpu_ras_set_mca_debug_mode(adev, val ? true : false);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -485,7 +494,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_se</div><div class='ctx'> void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)</div><div class='ctx'> {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='del'>-	if (!root || adev-&gt;ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6))</div><div class='add'>+	if (!root || amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_file("mca_debug_mode", 0200, root, adev, &amp;mca_debug_mode_fops);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h<br/>index 2b488fcf2f95..b399f1b62887 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h</a></div><div class='hunk'>@@ -46,6 +46,10 @@</div><div class='ctx'> #define MCA_REG__STATUS__ERRORCODEEXT(x)	MCA_REG_FIELD(x, 21, 16)</div><div class='ctx'> #define MCA_REG__STATUS__ERRORCODE(x)		MCA_REG_FIELD(x, 15, 0)</div><div class='ctx'> </div><div class='add'>+#define MCA_REG__MISC0__ERRCNT(x)		MCA_REG_FIELD(x, 43, 32)</div><div class='add'>+</div><div class='add'>+#define MCA_REG__SYND__ERRORINFORMATION(x)	MCA_REG_FIELD(x, 17, 0)</div><div class='add'>+</div><div class='ctx'> enum amdgpu_mca_ip {</div><div class='ctx'> 	AMDGPU_MCA_IP_UNKNOW = -1,</div><div class='ctx'> 	AMDGPU_MCA_IP_PSP = 0,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c<br/>index 9ddbf1494326..da48b6da0107 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c</a></div><div class='hunk'>@@ -98,6 +98,26 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,</div><div class='add'>+				    AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				    &amp;adev-&gt;mes.event_log_gpu_obj,</div><div class='add'>+				    &amp;adev-&gt;mes.event_log_gpu_addr,</div><div class='add'>+				    &amp;adev-&gt;mes.event_log_cpu_addr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "failed to create MES event log buffer (%d)", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(adev-&gt;mes.event_log_cpu_addr, 0, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	return  0;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	bitmap_free(adev-&gt;mes.doorbell_bitmap);</div><div class='hunk'>@@ -182,8 +202,14 @@ int amdgpu_mes_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='add'>+	r = amdgpu_mes_event_log_init(adev);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_doorbell;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+error_doorbell:</div><div class='add'>+	amdgpu_mes_doorbell_free(adev);</div><div class='ctx'> error:</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='hunk'>@@ -199,6 +225,10 @@ error_ids:</div><div class='ctx'> </div><div class='ctx'> void amdgpu_mes_fini(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;mes.event_log_gpu_obj,</div><div class='add'>+			      &amp;adev-&gt;mes.event_log_gpu_addr,</div><div class='add'>+			      &amp;adev-&gt;mes.event_log_cpu_addr);</div><div class='add'>+</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;mes.sch_ctx_offs);</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;mes.query_status_fence_offs);</div><div class='ctx'> 	amdgpu_device_wb_free(adev, adev-&gt;mes.read_val_offs);</div><div class='hunk'>@@ -886,6 +916,11 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;</div><div class='ctx'> 	op_input.set_shader_debugger.process_context_addr = process_context_addr;</div><div class='ctx'> 	op_input.set_shader_debugger.flags.u32all = flags;</div><div class='add'>+</div><div class='add'>+	/* use amdgpu mes_flush_shader_debugger instead */</div><div class='add'>+	if (op_input.set_shader_debugger.flags.process_ctx_flush)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl;</div><div class='ctx'> 	memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,</div><div class='ctx'> 			sizeof(op_input.set_shader_debugger.tcp_watch_cntl));</div><div class='hunk'>@@ -905,6 +940,32 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,</div><div class='add'>+				     uint64_t process_context_addr)</div><div class='add'>+{</div><div class='add'>+	struct mes_misc_op_input op_input = {0};</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;mes.funcs-&gt;misc_op) {</div><div class='add'>+		DRM_ERROR("mes flush shader debugger is not supported!\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;</div><div class='add'>+	op_input.set_shader_debugger.process_context_addr = process_context_addr;</div><div class='add'>+	op_input.set_shader_debugger.flags.process_ctx_flush = true;</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_lock(&amp;adev-&gt;mes);</div><div class='add'>+</div><div class='add'>+	r = adev-&gt;mes.funcs-&gt;misc_op(&amp;adev-&gt;mes, &amp;op_input);</div><div class='add'>+	if (r)</div><div class='add'>+		DRM_ERROR("failed to set_shader_debugger\n");</div><div class='add'>+</div><div class='add'>+	amdgpu_mes_unlock(&amp;adev-&gt;mes);</div><div class='add'>+</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,</div><div class='ctx'> 			       struct amdgpu_ring *ring,</div><div class='hunk'>@@ -1122,7 +1183,7 @@ int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;sync);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = drm_exec_lock_obj(&amp;exec,</div><div class='ctx'> 				      &amp;ctx_data-&gt;meta_data_obj-&gt;tbo.base);</div><div class='hunk'>@@ -1193,7 +1254,7 @@ int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = drm_exec_lock_obj(&amp;exec,</div><div class='ctx'> 				      &amp;ctx_data-&gt;meta_data_obj-&gt;tbo.base);</div><div class='hunk'>@@ -1479,3 +1540,34 @@ out:</div><div class='ctx'> 	amdgpu_ucode_release(&amp;adev-&gt;mes.fw[pipe]);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+</div><div class='add'>+static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = m-&gt;private;</div><div class='add'>+	uint32_t *mem = (uint32_t *)(adev-&gt;mes.event_log_cpu_addr);</div><div class='add'>+</div><div class='add'>+	seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,</div><div class='add'>+		     mem, PAGE_SIZE, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_mes_event_log);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+#if defined(CONFIG_DEBUG_FS)</div><div class='add'>+	struct drm_minor *minor = adev_to_drm(adev)-&gt;primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("amdgpu_mes_event_log", 0444, root,</div><div class='add'>+			    adev, &amp;amdgpu_debugfs_mes_event_log_fops);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h<br/>index a27b424ffe00..7d4f93fea937 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h</a></div><div class='hunk'>@@ -133,6 +133,11 @@ struct amdgpu_mes {</div><div class='ctx'> 	uint32_t			num_mes_dbs;</div><div class='ctx'> 	unsigned long			*doorbell_bitmap;</div><div class='ctx'> </div><div class='add'>+	/* MES event log buffer */</div><div class='add'>+	struct amdgpu_bo		*event_log_gpu_obj;</div><div class='add'>+	uint64_t                        event_log_gpu_addr;</div><div class='add'>+	void				*event_log_cpu_addr;</div><div class='add'>+</div><div class='ctx'> 	/* ip specific functions */</div><div class='ctx'> 	const struct amdgpu_mes_funcs   *funcs;</div><div class='ctx'> };</div><div class='hunk'>@@ -291,9 +296,10 @@ struct mes_misc_op_input {</div><div class='ctx'> 			uint64_t process_context_addr;</div><div class='ctx'> 			union {</div><div class='ctx'> 				struct {</div><div class='del'>-					uint64_t single_memop : 1;</div><div class='del'>-					uint64_t single_alu_op : 1;</div><div class='del'>-					uint64_t reserved: 30;</div><div class='add'>+					uint32_t single_memop : 1;</div><div class='add'>+					uint32_t single_alu_op : 1;</div><div class='add'>+					uint32_t reserved: 29;</div><div class='add'>+					uint32_t process_ctx_flush: 1;</div><div class='ctx'> 				};</div><div class='ctx'> 				uint32_t u32all;</div><div class='ctx'> 			} flags;</div><div class='hunk'>@@ -369,7 +375,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,</div><div class='ctx'> 				const uint32_t *tcp_watch_cntl,</div><div class='ctx'> 				uint32_t flags,</div><div class='ctx'> 				bool trap_en);</div><div class='del'>-</div><div class='add'>+int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,</div><div class='add'>+				uint64_t process_context_addr);</div><div class='ctx'> int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,</div><div class='ctx'> 			int queue_type, int idx,</div><div class='ctx'> 			struct amdgpu_mes_ctx_data *ctx_data,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h<br/>index 32fe05c810c6..2e4911050cc5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h</a></div><div class='hunk'>@@ -32,7 +32,6 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/display/drm_dp_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='del'>-#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_encoder.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fixed.h&gt;</div><div class='ctx'> #include &lt;drm/drm_framebuffer.h&gt;</div><div class='hunk'>@@ -51,6 +50,7 @@ struct amdgpu_device;</div><div class='ctx'> struct amdgpu_encoder;</div><div class='ctx'> struct amdgpu_router;</div><div class='ctx'> struct amdgpu_hpd;</div><div class='add'>+struct edid;</div><div class='ctx'> </div><div class='ctx'> #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)</div><div class='ctx'> #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)</div><div class='hunk'>@@ -343,6 +343,97 @@ struct amdgpu_mode_info {</div><div class='ctx'> 	int			disp_priority;</div><div class='ctx'> 	const struct amdgpu_display_funcs *funcs;</div><div class='ctx'> 	const enum drm_plane_type *plane_type;</div><div class='add'>+</div><div class='add'>+	/* Driver-private color mgmt props */</div><div class='add'>+</div><div class='add'>+	/* @plane_degamma_lut_property: Plane property to set a degamma LUT to</div><div class='add'>+	 * convert encoded values to light linear values before sampling or</div><div class='add'>+	 * blending.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_degamma_lut_property;</div><div class='add'>+	/* @plane_degamma_lut_size_property: Plane property to define the max</div><div class='add'>+	 * size of degamma LUT as supported by the driver (read-only).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_degamma_lut_size_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_degamma_tf_property: Plane pre-defined transfer function to</div><div class='add'>+	 * to go from scanout/encoded values to linear values.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_degamma_tf_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_hdr_mult_property:</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_hdr_mult_property;</div><div class='add'>+</div><div class='add'>+	struct drm_property *plane_ctm_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @shaper_lut_property: Plane property to set pre-blending shaper LUT</div><div class='add'>+	 * that converts color content before 3D LUT. If</div><div class='add'>+	 * plane_shaper_tf_property != Identity TF, AMD color module will</div><div class='add'>+	 * combine the user LUT values with pre-defined TF into the LUT</div><div class='add'>+	 * parameters to be programmed.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_shaper_lut_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @shaper_lut_size_property: Plane property for the size of</div><div class='add'>+	 * pre-blending shaper LUT as supported by the driver (read-only).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_shaper_lut_size_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_shaper_tf_property: Plane property to set a predefined</div><div class='add'>+	 * transfer function for pre-blending shaper (before applying 3D LUT)</div><div class='add'>+	 * with or without LUT. There is no shaper ROM, but we can use AMD</div><div class='add'>+	 * color modules to program LUT parameters from predefined TF (or</div><div class='add'>+	 * from a combination of pre-defined TF and the custom 1D LUT).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_shaper_tf_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_lut3d_property: Plane property for color transformation using</div><div class='add'>+	 * a 3D LUT (pre-blending), a three-dimensional array where each</div><div class='add'>+	 * element is an RGB triplet. Each dimension has the size of</div><div class='add'>+	 * lut3d_size. The array contains samples from the approximated</div><div class='add'>+	 * function. On AMD, values between samples are estimated by</div><div class='add'>+	 * tetrahedral interpolation. The array is accessed with three indices,</div><div class='add'>+	 * one for each input dimension (color channel), blue being the</div><div class='add'>+	 * outermost dimension, red the innermost.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_lut3d_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_degamma_lut_size_property: Plane property to define the max</div><div class='add'>+	 * size of 3D LUT as supported by the driver (read-only). The max size</div><div class='add'>+	 * is the max size of one dimension and, therefore, the max number of</div><div class='add'>+	 * entries for 3D LUT array is the 3D LUT size cubed;</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_lut3d_size_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_blend_lut_property: Plane property for output gamma before</div><div class='add'>+	 * blending. Userspace set a blend LUT to convert colors after 3D LUT</div><div class='add'>+	 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they</div><div class='add'>+	 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property</div><div class='add'>+	 * != Identity TF, AMD color module will combine the user LUT values</div><div class='add'>+	 * with pre-defined TF into the LUT parameters to be programmed.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_blend_lut_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_blend_lut_size_property: Plane property to define the max</div><div class='add'>+	 * size of blend LUT as supported by the driver (read-only).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_blend_lut_size_property;</div><div class='add'>+	/**</div><div class='add'>+	 * @plane_blend_tf_property: Plane property to set a predefined</div><div class='add'>+	 * transfer function for pre-blending blend/out_gamma (after applying</div><div class='add'>+	 * 3D LUT) with or without LUT. There is no blend ROM, but we can use</div><div class='add'>+	 * AMD color modules to program LUT parameters from predefined TF (or</div><div class='add'>+	 * from a combination of pre-defined TF and the custom 1D LUT).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *plane_blend_tf_property;</div><div class='add'>+	/* @regamma_tf_property: Transfer function for CRTC regamma</div><div class='add'>+	 * (post-blending). Possible values are defined by `enum</div><div class='add'>+	 * amdgpu_transfer_function`. There is no regamma ROM, but we can use</div><div class='add'>+	 * AMD color modules to program LUT parameters from predefined TF (or</div><div class='add'>+	 * from a combination of pre-defined TF and the custom 1D LUT).</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property *regamma_tf_property;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define AMDGPU_MAX_BL_LEVEL 0xFF</div><div class='hunk'>@@ -416,6 +507,10 @@ struct amdgpu_crtc {</div><div class='ctx'> </div><div class='ctx'> 	int otg_inst;</div><div class='ctx'> 	struct drm_pending_vblank_event *event;</div><div class='add'>+</div><div class='add'>+	bool wb_pending;</div><div class='add'>+	bool wb_enabled;</div><div class='add'>+	struct drm_writeback_connector *wb_conn;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_encoder_atom_dig {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c<br/>index b2e9a2f81d82..b671b0665492 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.c</a></div><div class='hunk'>@@ -1242,19 +1242,15 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,</div><div class='ctx'>  * amdgpu_bo_move_notify - notification about a memory move</div><div class='ctx'>  * @bo: pointer to a buffer object</div><div class='ctx'>  * @evict: if this move is evicting the buffer from the graphics address space</div><div class='del'>- * @new_mem: new information of the bufer object</div><div class='ctx'>  *</div><div class='ctx'>  * Marks the corresponding &amp;amdgpu_bo buffer object as invalid, also performs</div><div class='ctx'>  * bookkeeping.</div><div class='ctx'>  * TTM driver callback which is called when ttm moves a buffer.</div><div class='ctx'>  */</div><div class='del'>-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,</div><div class='del'>-			   bool evict,</div><div class='del'>-			   struct ttm_resource *new_mem)</div><div class='add'>+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;bdev);</div><div class='ctx'> 	struct amdgpu_bo *abo;</div><div class='del'>-	struct ttm_resource *old_mem = bo-&gt;resource;</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_bo_is_amdgpu_bo(bo))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1271,13 +1267,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,</div><div class='ctx'> 	/* remember the eviction */</div><div class='ctx'> 	if (evict)</div><div class='ctx'> 		atomic64_inc(&amp;adev-&gt;num_evictions);</div><div class='del'>-</div><div class='del'>-	/* update statistics */</div><div class='del'>-	if (!new_mem)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* move_notify is called before move happens */</div><div class='del'>-	trace_amdgpu_bo_move(abo, new_mem-&gt;mem_type, old_mem-&gt;mem_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amdgpu_bo_get_memory(struct amdgpu_bo *bo,</div><div class='hunk'>@@ -1340,6 +1329,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> </div><div class='ctx'> 	abo = ttm_to_amdgpu_bo(bo);</div><div class='ctx'> </div><div class='add'>+	WARN_ON(abo-&gt;vm_bo);</div><div class='add'>+</div><div class='ctx'> 	if (abo-&gt;kfd_bo)</div><div class='ctx'> 		amdgpu_amdkfd_release_notify(abo);</div><div class='ctx'> </div><div class='hunk'>@@ -1523,10 +1514,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)</div><div class='ctx'> u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo-&gt;tbo.bdev);</div><div class='del'>-	uint64_t offset;</div><div class='add'>+	uint64_t offset = AMDGPU_BO_INVALID_OFFSET;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;tbo.resource-&gt;mem_type == TTM_PL_TT)</div><div class='add'>+		offset = amdgpu_gmc_agp_addr(&amp;bo-&gt;tbo);</div><div class='ctx'> </div><div class='del'>-	offset = (bo-&gt;tbo.resource-&gt;start &lt;&lt; PAGE_SHIFT) +</div><div class='del'>-		 amdgpu_ttm_domain_start(adev, bo-&gt;tbo.resource-&gt;mem_type);</div><div class='add'>+	if (offset == AMDGPU_BO_INVALID_OFFSET)</div><div class='add'>+		offset = (bo-&gt;tbo.resource-&gt;start &lt;&lt; PAGE_SHIFT) +</div><div class='add'>+			amdgpu_ttm_domain_start(adev, bo-&gt;tbo.resource-&gt;mem_type);</div><div class='ctx'> </div><div class='ctx'> 	return amdgpu_gmc_sign_extend(offset);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h<br/>index d28e21baef16..a3ea8a82db23 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_object.h</a></div><div class='hunk'>@@ -344,9 +344,7 @@ int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,</div><div class='ctx'> int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,</div><div class='ctx'> 			   size_t buffer_size, uint32_t *metadata_size,</div><div class='ctx'> 			   uint64_t *flags);</div><div class='del'>-void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,</div><div class='del'>-			   bool evict,</div><div class='del'>-			   struct ttm_resource *new_mem);</div><div class='add'>+void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict);</div><div class='ctx'> void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);</div><div class='ctx'> vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);</div><div class='ctx'> void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br/>index a21045d018f2..0328616473f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c</a></div><div class='hunk'>@@ -466,7 +466,7 @@ static int psp_sw_init(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,</div><div class='del'>-				      amdgpu_sriov_vf(adev) ?</div><div class='add'>+				      (amdgpu_sriov_vf(adev) || adev-&gt;debug_use_vram_fw_buf) ?</div><div class='ctx'> 				      AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,</div><div class='ctx'> 				      &amp;psp-&gt;fw_pri_bo,</div><div class='ctx'> 				      &amp;psp-&gt;fw_pri_mc_addr,</div><div class='hunk'>@@ -1433,8 +1433,8 @@ int psp_xgmi_get_topology_info(struct psp_context *psp,</div><div class='ctx'> 			 get_extended_data) ||</div><div class='ctx'> 			amdgpu_ip_version(psp-&gt;adev, MP0_HWIP, 0) ==</div><div class='ctx'> 				IP_VERSION(13, 0, 6);</div><div class='del'>-		bool ta_port_num_support = psp-&gt;xgmi_context.xgmi_ta_caps &amp;</div><div class='del'>-						EXTEND_PEER_LINK_INFO_CMD_FLAG;</div><div class='add'>+		bool ta_port_num_support = amdgpu_sriov_vf(psp-&gt;adev) ? 0 :</div><div class='add'>+				psp-&gt;xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG;</div><div class='ctx'> </div><div class='ctx'> 		/* popluate the shared output buffer rather than the cmd input buffer</div><div class='ctx'> 		 * with node_ids as the input for GET_PEER_LINKS command execution.</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br/>index a3dc68e98910..31823a30dea2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include &lt;linux/reboot.h&gt;</div><div class='ctx'> #include &lt;linux/syscalls.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/list_sort.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ras.h"</div><div class='hunk'>@@ -304,11 +305,13 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		data-&gt;head.block = block_id;</div><div class='del'>-		/* only ue and ce errors are supported */</div><div class='add'>+		/* only ue, ce and poison errors are supported */</div><div class='ctx'> 		if (!memcmp("ue", err, 2))</div><div class='ctx'> 			data-&gt;head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;</div><div class='ctx'> 		else if (!memcmp("ce", err, 2))</div><div class='ctx'> 			data-&gt;head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;</div><div class='add'>+		else if (!memcmp("poison", err, 6))</div><div class='add'>+			data-&gt;head.type = AMDGPU_RAS_ERROR__POISON;</div><div class='ctx'> 		else</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -430,9 +433,10 @@ static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,</div><div class='ctx'>  * The block is one of: umc, sdma, gfx, etc.</div><div class='ctx'>  *	see ras_block_string[] for details</div><div class='ctx'>  *</div><div class='del'>- * The error type is one of: ue, ce, where,</div><div class='add'>+ * The error type is one of: ue, ce and poison where,</div><div class='ctx'>  *	ue is multi-uncorrectable</div><div class='ctx'>  *	ce is single-correctable</div><div class='add'>+ *	poison is poison</div><div class='ctx'>  *</div><div class='ctx'>  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.</div><div class='ctx'>  * The address and value are hexadecimal numbers, leading 0x is optional.</div><div class='hunk'>@@ -1066,8 +1070,7 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,</div><div class='ctx'> 			mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='ctx'> 			if (err_info-&gt;ce_count) {</div><div class='ctx'> 				dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-					 "%lld new correctable hardware errors detected in %s block, "</div><div class='del'>-					 "no user action is needed\n",</div><div class='add'>+					 "%lld new correctable hardware errors detected in %s block\n",</div><div class='ctx'> 					 mcm_info-&gt;socket_id,</div><div class='ctx'> 					 mcm_info-&gt;die_id,</div><div class='ctx'> 					 err_info-&gt;ce_count,</div><div class='hunk'>@@ -1079,8 +1082,7 @@ static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,</div><div class='ctx'> 			err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> 			mcm_info = &amp;err_info-&gt;mcm_info;</div><div class='ctx'> 			dev_info(adev-&gt;dev, "socket: %d, die: %d, "</div><div class='del'>-				 "%lld correctable hardware errors detected in total in %s block, "</div><div class='del'>-				 "no user action is needed\n",</div><div class='add'>+				 "%lld correctable hardware errors detected in total in %s block\n",</div><div class='ctx'> 				 mcm_info-&gt;socket_id, mcm_info-&gt;die_id, err_info-&gt;ce_count, blk_name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1107,16 +1109,14 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,</div><div class='ctx'> 			   adev-&gt;smuio.funcs-&gt;get_die_id) {</div><div class='ctx'> 			dev_info(adev-&gt;dev, "socket: %d, die: %d "</div><div class='ctx'> 				 "%ld correctable hardware errors "</div><div class='del'>-				 "detected in %s block, no user "</div><div class='del'>-				 "action is needed.\n",</div><div class='add'>+				 "detected in %s block\n",</div><div class='ctx'> 				 adev-&gt;smuio.funcs-&gt;get_socket_id(adev),</div><div class='ctx'> 				 adev-&gt;smuio.funcs-&gt;get_die_id(adev),</div><div class='ctx'> 				 ras_mgr-&gt;err_data.ce_count,</div><div class='ctx'> 				 blk_name);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			dev_info(adev-&gt;dev, "%ld correctable hardware errors "</div><div class='del'>-				 "detected in %s block, no user "</div><div class='del'>-				 "action is needed.\n",</div><div class='add'>+				 "detected in %s block\n",</div><div class='ctx'> 				 ras_mgr-&gt;err_data.ce_count,</div><div class='ctx'> 				 blk_name);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1155,8 +1155,10 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s</div><div class='ctx'> 		for_each_ras_error(err_node, err_data) {</div><div class='ctx'> 			err_info = &amp;err_node-&gt;err_info;</div><div class='ctx'> </div><div class='del'>-			amdgpu_ras_error_statistic_ce_count(&amp;obj-&gt;err_data, &amp;err_info-&gt;mcm_info, err_info-&gt;ce_count);</div><div class='del'>-			amdgpu_ras_error_statistic_ue_count(&amp;obj-&gt;err_data, &amp;err_info-&gt;mcm_info, err_info-&gt;ue_count);</div><div class='add'>+			amdgpu_ras_error_statistic_ce_count(&amp;obj-&gt;err_data,</div><div class='add'>+					&amp;err_info-&gt;mcm_info, NULL, err_info-&gt;ce_count);</div><div class='add'>+			amdgpu_ras_error_statistic_ue_count(&amp;obj-&gt;err_data,</div><div class='add'>+					&amp;err_info-&gt;mcm_info, NULL, err_info-&gt;ue_count);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* for legacy asic path which doesn't has error source info */</div><div class='hunk'>@@ -1173,6 +1175,9 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> 	enum amdgpu_ras_block blk = info ? info-&gt;head.block : AMDGPU_RAS_BLOCK_COUNT;</div><div class='ctx'> 	struct amdgpu_ras_block_object *block_obj = NULL;</div><div class='ctx'> </div><div class='add'>+	if (blk == AMDGPU_RAS_BLOCK_COUNT)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1914,7 +1919,7 @@ static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj</div><div class='ctx'> 				struct amdgpu_iv_entry *entry)</div><div class='ctx'> {</div><div class='ctx'> 	dev_info(obj-&gt;adev-&gt;dev,</div><div class='del'>-		"Poison is created, no user action is needed.\n");</div><div class='add'>+		"Poison is created\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,</div><div class='hunk'>@@ -2537,7 +2542,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	data = &amp;con-&gt;eh_data;</div><div class='del'>-	*data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);</div><div class='add'>+	*data = kzalloc(sizeof(**data), GFP_KERNEL);</div><div class='ctx'> 	if (!*data) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -2824,10 +2829,10 @@ int amdgpu_ras_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (con)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	con = kmalloc(sizeof(struct amdgpu_ras) +</div><div class='add'>+	con = kzalloc(sizeof(*con) +</div><div class='ctx'> 			sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +</div><div class='ctx'> 			sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,</div><div class='del'>-			GFP_KERNEL|__GFP_ZERO);</div><div class='add'>+			GFP_KERNEL);</div><div class='ctx'> 	if (!con)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -2914,6 +2919,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_query_poison_mode(adev);</div><div class='ctx'> </div><div class='add'>+	/* Packed socket_id to ras feature mask bits[31:29] */</div><div class='add'>+	if (adev-&gt;smuio.funcs &amp;&amp;</div><div class='add'>+	    adev-&gt;smuio.funcs-&gt;get_socket_id)</div><div class='add'>+		con-&gt;features |= ((adev-&gt;smuio.funcs-&gt;get_socket_id(adev)) &lt;&lt; 29);</div><div class='add'>+</div><div class='ctx'> 	/* Get RAS schema for particular SOC */</div><div class='ctx'> 	con-&gt;schema = amdgpu_get_ras_schema(adev);</div><div class='ctx'> </div><div class='hunk'>@@ -3132,6 +3142,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	amdgpu_ras_set_mca_debug_mode(adev, false);</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(node, tmp, &amp;adev-&gt;ras_list, node) {</div><div class='ctx'> 		if (!node-&gt;ras_obj) {</div><div class='ctx'> 			dev_warn(adev-&gt;dev, "Warning: abnormal ras list node.\n");</div><div class='hunk'>@@ -3405,12 +3417,18 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)</div><div class='add'>+int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (con)</div><div class='del'>-		con-&gt;is_mca_debug_mode = enable;</div><div class='add'>+	if (con) {</div><div class='add'>+		ret = amdgpu_mca_smu_set_debug_mode(adev, enable);</div><div class='add'>+		if (!ret)</div><div class='add'>+			con-&gt;is_mca_debug_mode = enable;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)</div><div class='hunk'>@@ -3665,8 +3683,24 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void)</div><div class='ctx'> 	return err_node;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)</div><div class='add'>+{</div><div class='add'>+	struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);</div><div class='add'>+	struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);</div><div class='add'>+	struct amdgpu_smuio_mcm_config_info *infoa = &amp;nodea-&gt;err_info.mcm_info;</div><div class='add'>+	struct amdgpu_smuio_mcm_config_info *infob = &amp;nodeb-&gt;err_info.mcm_info;</div><div class='add'>+</div><div class='add'>+	if (unlikely(infoa-&gt;socket_id != infob-&gt;socket_id))</div><div class='add'>+		return infoa-&gt;socket_id - infob-&gt;socket_id;</div><div class='add'>+	else</div><div class='add'>+		return infoa-&gt;die_id - infob-&gt;die_id;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,</div><div class='del'>-						      struct amdgpu_smuio_mcm_config_info *mcm_info)</div><div class='add'>+				struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+				struct ras_err_addr *err_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_node *err_node;</div><div class='ctx'> </div><div class='hunk'>@@ -3680,14 +3714,19 @@ static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_d</div><div class='ctx'> </div><div class='ctx'> 	memcpy(&amp;err_node-&gt;err_info.mcm_info, mcm_info, sizeof(*mcm_info));</div><div class='ctx'> </div><div class='add'>+	if (err_addr)</div><div class='add'>+		memcpy(&amp;err_node-&gt;err_info.err_addr, err_addr, sizeof(*err_addr));</div><div class='add'>+</div><div class='ctx'> 	err_data-&gt;err_list_count++;</div><div class='ctx'> 	list_add_tail(&amp;err_node-&gt;node, &amp;err_data-&gt;err_node_list);</div><div class='add'>+	list_sort(NULL, &amp;err_data-&gt;err_node_list, ras_err_info_cmp);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;err_node-&gt;err_info;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='del'>-					struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)</div><div class='add'>+		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+		struct ras_err_addr *err_addr, u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='ctx'> </div><div class='hunk'>@@ -3697,7 +3736,7 @@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='ctx'> 	if (!count)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	err_info = amdgpu_ras_error_get_info(err_data, mcm_info);</div><div class='add'>+	err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);</div><div class='ctx'> 	if (!err_info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -3708,7 +3747,8 @@ int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='del'>-					struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count)</div><div class='add'>+		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+		struct ras_err_addr *err_addr, u64 count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ras_err_info *err_info;</div><div class='ctx'> </div><div class='hunk'>@@ -3718,7 +3758,7 @@ int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='ctx'> 	if (!count)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	err_info = amdgpu_ras_error_get_info(err_data, mcm_info);</div><div class='add'>+	err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);</div><div class='ctx'> 	if (!err_info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h<br/>index 19161916ac46..76fb85628716 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h</a></div><div class='hunk'>@@ -452,10 +452,17 @@ struct ras_fs_data {</div><div class='ctx'> 	char debugfs_name[32];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct ras_err_addr {</div><div class='add'>+	uint64_t err_status;</div><div class='add'>+	uint64_t err_ipid;</div><div class='add'>+	uint64_t err_addr;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct ras_err_info {</div><div class='ctx'> 	struct amdgpu_smuio_mcm_config_info mcm_info;</div><div class='ctx'> 	u64 ce_count;</div><div class='ctx'> 	u64 ue_count;</div><div class='add'>+	struct ras_err_addr err_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ras_err_node {</div><div class='hunk'>@@ -773,7 +780,7 @@ struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);</div><div class='ctx'> </div><div class='del'>-void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);</div><div class='add'>+int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev);</div><div class='ctx'> bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				     unsigned int *mode);</div><div class='hunk'>@@ -806,8 +813,10 @@ void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_ras_error_data_init(struct ras_err_data *err_data);</div><div class='ctx'> void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);</div><div class='ctx'> int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,</div><div class='del'>-					struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count);</div><div class='add'>+		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+		struct ras_err_addr *err_addr, u64 count);</div><div class='ctx'> int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,</div><div class='del'>-					struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count);</div><div class='add'>+		struct amdgpu_smuio_mcm_config_info *mcm_info,</div><div class='add'>+		struct ras_err_addr *err_addr, u64 count);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c<br/>index 65aa218380be..2fde93b00cab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c</a></div><div class='hunk'>@@ -214,6 +214,12 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,</div><div class='ctx'> 			control-&gt;i2c_address = EEPROM_I2C_MADDR_0;</div><div class='ctx'> 		return true;</div><div class='ctx'> 	case IP_VERSION(13, 0, 0):</div><div class='add'>+		if (strnstr(atom_ctx-&gt;vbios_pn, "D707",</div><div class='add'>+			    sizeof(atom_ctx-&gt;vbios_pn)))</div><div class='add'>+			control-&gt;i2c_address = EEPROM_I2C_MADDR_0;</div><div class='add'>+		else</div><div class='add'>+			control-&gt;i2c_address = EEPROM_I2C_MADDR_4;</div><div class='add'>+		return true;</div><div class='ctx'> 	case IP_VERSION(13, 0, 6):</div><div class='ctx'> 	case IP_VERSION(13, 0, 10):</div><div class='ctx'> 		control-&gt;i2c_address = EEPROM_I2C_MADDR_4;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h<br/>index b0335a1c5e90..19899f6b9b2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h</a></div><div class='hunk'>@@ -32,7 +32,6 @@ enum AMDGPU_RESET_FLAGS {</div><div class='ctx'> </div><div class='ctx'> 	AMDGPU_NEED_FULL_RESET = 0,</div><div class='ctx'> 	AMDGPU_SKIP_HW_RESET = 1,</div><div class='del'>-	AMDGPU_RESET_FOR_DEVICE_REMOVE = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_reset_context {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c<br/>index 6a80d3ec887e..45424ebf9681 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c</a></div><div class='hunk'>@@ -642,6 +642,10 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,</div><div class='ctx'> 				    struct amdgpu_mqd_prop *prop)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	bool is_high_prio_compute = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE &amp;&amp;</div><div class='add'>+				    amdgpu_gfx_is_high_priority_compute_queue(adev, ring);</div><div class='add'>+	bool is_high_prio_gfx = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX &amp;&amp;</div><div class='add'>+				amdgpu_gfx_is_high_priority_graphics_queue(adev, ring);</div><div class='ctx'> </div><div class='ctx'> 	memset(prop, 0, sizeof(*prop));</div><div class='ctx'> </div><div class='hunk'>@@ -659,10 +663,8 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,</div><div class='ctx'> 	 */</div><div class='ctx'> 	prop-&gt;hqd_active = ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_KIQ;</div><div class='ctx'> </div><div class='del'>-	if ((ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_COMPUTE &amp;&amp;</div><div class='del'>-	     amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) ||</div><div class='del'>-	    (ring-&gt;funcs-&gt;type == AMDGPU_RING_TYPE_GFX &amp;&amp;</div><div class='del'>-	     amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) {</div><div class='add'>+	prop-&gt;allow_tunneling = is_high_prio_compute;</div><div class='add'>+	if (is_high_prio_compute || is_high_prio_gfx) {</div><div class='ctx'> 		prop-&gt;hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;</div><div class='ctx'> 		prop-&gt;hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c<br/>index 35e0ae9acadc..2c3675d91614 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c</a></div><div class='hunk'>@@ -531,13 +531,12 @@ int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,</div><div class='ctx'> 	if (version_major == 2 &amp;&amp; version_minor == 1)</div><div class='ctx'> 		adev-&gt;gfx.rlc.is_rlc_v2_1 = true;</div><div class='ctx'> </div><div class='del'>-	if (version_minor &gt;= 0) {</div><div class='del'>-		err = amdgpu_gfx_rlc_init_microcode_v2_0(adev);</div><div class='del'>-		if (err) {</div><div class='del'>-			dev_err(adev-&gt;dev, "fail to init rlc v2_0 microcode\n");</div><div class='del'>-			return err;</div><div class='del'>-		}</div><div class='add'>+	err = amdgpu_gfx_rlc_init_microcode_v2_0(adev);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to init rlc v2_0 microcode\n");</div><div class='add'>+		return err;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	if (version_minor &gt;= 1)</div><div class='ctx'> 		amdgpu_gfx_rlc_init_microcode_v2_1(adev);</div><div class='ctx'> 	if (version_minor &gt;= 2)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c<br/>new file mode 100644<br/>index 000000000000..7a6a67275404<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c</a></div><div class='hunk'>@@ -0,0 +1,247 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_seq64.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: amdgpu_seq64</div><div class='add'>+ *</div><div class='add'>+ * amdgpu_seq64 allocates a 64bit memory on each request in sequence order.</div><div class='add'>+ * seq64 driver is required for user queue fence memory allocation, TLB</div><div class='add'>+ * counters and VM updates. It has maximum count of 32768 64 bit slots.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_map - Map the seq64 memory to VM</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @vm: vm pointer</div><div class='add'>+ * @bo_va: bo_va pointer</div><div class='add'>+ * @seq64_addr: seq64 vaddr start address</div><div class='add'>+ * @size: seq64 pool size</div><div class='add'>+ *</div><div class='add'>+ * Map the seq64 memory to the given VM.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success or a negative error code on failure</div><div class='add'>+ */</div><div class='add'>+int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+		     struct amdgpu_bo_va **bo_va, u64 seq64_addr,</div><div class='add'>+		     uint32_t size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	bo = adev-&gt;seq64.sbo;</div><div class='add'>+	if (!bo)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='add'>+		if (likely(!r))</div><div class='add'>+			r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (unlikely(r))</div><div class='add'>+			goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*bo_va = amdgpu_vm_bo_add(adev, vm, bo);</div><div class='add'>+	if (!*bo_va) {</div><div class='add'>+		r = -ENOMEM;</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, size,</div><div class='add'>+			     AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |</div><div class='add'>+			     AMDGPU_PTE_EXECUTABLE);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r);</div><div class='add'>+		amdgpu_vm_bo_del(adev, *bo_va);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_vm_bo_update(adev, *bo_va, false);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("failed to do vm_bo_update on userq sem\n");</div><div class='add'>+		amdgpu_vm_bo_del(adev, *bo_va);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_unmap - Unmap the seq64 memory</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @fpriv: DRM file private</div><div class='add'>+ *</div><div class='add'>+ * Unmap the seq64 memory from the given VM.</div><div class='add'>+ */</div><div class='add'>+void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_vm *vm;</div><div class='add'>+	struct amdgpu_bo *bo;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!fpriv-&gt;seq64_va)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	bo = adev-&gt;seq64.sbo;</div><div class='add'>+	if (!bo)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	vm = &amp;fpriv-&gt;vm;</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		r = amdgpu_vm_lock_pd(vm, &amp;exec, 0);</div><div class='add'>+		if (likely(!r))</div><div class='add'>+			r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (unlikely(r))</div><div class='add'>+			goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_vm_bo_del(adev, fpriv-&gt;seq64_va);</div><div class='add'>+</div><div class='add'>+	fpriv-&gt;seq64_va = NULL;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_alloc - Allocate a 64 bit memory</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @gpu_addr: allocated gpu VA start address</div><div class='add'>+ * @cpu_addr: allocated cpu VA start address</div><div class='add'>+ *</div><div class='add'>+ * Alloc a 64 bit memory from seq64 pool.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success or a negative error code on failure</div><div class='add'>+ */</div><div class='add'>+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr,</div><div class='add'>+		       u64 **cpu_addr)</div><div class='add'>+{</div><div class='add'>+	unsigned long bit_pos;</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	bit_pos = find_first_zero_bit(adev-&gt;seq64.used, adev-&gt;seq64.num_sem);</div><div class='add'>+</div><div class='add'>+	if (bit_pos &lt; adev-&gt;seq64.num_sem) {</div><div class='add'>+		__set_bit(bit_pos, adev-&gt;seq64.used);</div><div class='add'>+		offset = bit_pos &lt;&lt; 6; /* convert to qw offset */</div><div class='add'>+	} else {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*gpu_addr = offset + AMDGPU_SEQ64_VADDR_START;</div><div class='add'>+	*cpu_addr = offset + adev-&gt;seq64.cpu_base_addr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_free - Free the given 64 bit memory</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @gpu_addr: gpu start address to be freed</div><div class='add'>+ *</div><div class='add'>+ * Free the given 64 bit memory from seq64 pool.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr)</div><div class='add'>+{</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	offset = gpu_addr - AMDGPU_SEQ64_VADDR_START;</div><div class='add'>+</div><div class='add'>+	offset &gt;&gt;= 6;</div><div class='add'>+	if (offset &lt; adev-&gt;seq64.num_sem)</div><div class='add'>+		__clear_bit(offset, adev-&gt;seq64.used);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_fini - Cleanup seq64 driver</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Free the memory space allocated for seq64.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void amdgpu_seq64_fini(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	amdgpu_bo_free_kernel(&amp;adev-&gt;seq64.sbo,</div><div class='add'>+			      NULL,</div><div class='add'>+			      (void **)&amp;adev-&gt;seq64.cpu_base_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_seq64_init - Initialize seq64 driver</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ *</div><div class='add'>+ * Allocate the required memory space for seq64.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success or a negative error code on failure</div><div class='add'>+ */</div><div class='add'>+int amdgpu_seq64_init(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;seq64.sbo)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * AMDGPU_MAX_SEQ64_SLOTS * sizeof(u64) * 8 = AMDGPU_MAX_SEQ64_SLOTS</div><div class='add'>+	 * 64bit slots</div><div class='add'>+	 */</div><div class='add'>+	r = amdgpu_bo_create_kernel(adev, AMDGPU_SEQ64_SIZE,</div><div class='add'>+				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+				    &amp;adev-&gt;seq64.sbo, NULL,</div><div class='add'>+				    (void **)&amp;adev-&gt;seq64.cpu_base_addr);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_warn(adev-&gt;dev, "(%d) create seq64 failed\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(adev-&gt;seq64.cpu_base_addr, 0, AMDGPU_SEQ64_SIZE);</div><div class='add'>+</div><div class='add'>+	adev-&gt;seq64.num_sem = AMDGPU_MAX_SEQ64_SLOTS;</div><div class='add'>+	memset(&amp;adev-&gt;seq64.used, 0, sizeof(adev-&gt;seq64.used));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h<br/>new file mode 100644<br/>index 000000000000..2196e72be508<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_SEQ64_H__</div><div class='add'>+#define __AMDGPU_SEQ64_H__</div><div class='add'>+</div><div class='add'>+#define AMDGPU_SEQ64_SIZE		(2ULL &lt;&lt; 20)</div><div class='add'>+#define AMDGPU_MAX_SEQ64_SLOTS		(AMDGPU_SEQ64_SIZE / (sizeof(u64) * 8))</div><div class='add'>+#define AMDGPU_SEQ64_VADDR_OFFSET	0x50000</div><div class='add'>+#define AMDGPU_SEQ64_VADDR_START	(AMDGPU_VA_RESERVED_SIZE + AMDGPU_SEQ64_VADDR_OFFSET)</div><div class='add'>+</div><div class='add'>+struct amdgpu_seq64 {</div><div class='add'>+	struct amdgpu_bo *sbo;</div><div class='add'>+	u32 num_sem;</div><div class='add'>+	u64 *cpu_base_addr;</div><div class='add'>+	DECLARE_BITMAP(used, AMDGPU_MAX_SEQ64_SLOTS);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void amdgpu_seq64_fini(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_seq64_init(struct amdgpu_device *adev);</div><div class='add'>+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr);</div><div class='add'>+void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);</div><div class='add'>+int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='add'>+		     struct amdgpu_bo_va **bo_va, u64 seq64_addr, uint32_t size);</div><div class='add'>+void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c<br/>index dcd8c066bc1f..1b013a44ca99 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c</a></div><div class='hunk'>@@ -191,7 +191,8 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	/* Never sync to VM updates either. */</div><div class='ctx'> 	if (fence_owner == AMDGPU_FENCE_OWNER_VM &amp;&amp;</div><div class='del'>-	    owner != AMDGPU_FENCE_OWNER_UNDEFINED)</div><div class='add'>+	    owner != AMDGPU_FENCE_OWNER_UNDEFINED &amp;&amp;</div><div class='add'>+	    owner != AMDGPU_FENCE_OWNER_KFD)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* Ignore fences depending on the sync mode */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h<br/>index 2fd1bfb35916..f539b1d00234 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h</a></div><div class='hunk'>@@ -554,6 +554,21 @@ TRACE_EVENT(amdgpu_reset_reg_dumps,</div><div class='ctx'> 		      __entry-&gt;value)</div><div class='ctx'> );</div><div class='ctx'> </div><div class='add'>+TRACE_EVENT(amdgpu_runpm_reference_dumps,</div><div class='add'>+	    TP_PROTO(uint32_t index, const char *func),</div><div class='add'>+	    TP_ARGS(index, func),</div><div class='add'>+	    TP_STRUCT__entry(</div><div class='add'>+			     __field(uint32_t, index)</div><div class='add'>+			     __string(func, func)</div><div class='add'>+			     ),</div><div class='add'>+	    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;index = index;</div><div class='add'>+			   __assign_str(func, func);</div><div class='add'>+			   ),</div><div class='add'>+	    TP_printk("amdgpu runpm reference dump 0x%x: 0x%s\n",</div><div class='add'>+		      __entry-&gt;index,</div><div class='add'>+		      __get_str(func))</div><div class='add'>+);</div><div class='ctx'> #undef AMDGPU_JOB_GET_TIMELINE_NAME</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br/>index 46a24d2308aa..8722beba494e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c</a></div><div class='hunk'>@@ -540,10 +540,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	trace_amdgpu_bo_move(abo, new_mem-&gt;mem_type, old_mem-&gt;mem_type);</div><div class='ctx'> out:</div><div class='ctx'> 	/* update statistics */</div><div class='ctx'> 	atomic64_add(bo-&gt;base.size, &amp;adev-&gt;num_bytes_moved);</div><div class='del'>-	amdgpu_bo_move_notify(bo, evict, new_mem);</div><div class='add'>+	amdgpu_bo_move_notify(bo, evict);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -954,10 +955,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	addr = amdgpu_gmc_agp_addr(bo);</div><div class='del'>-	if (addr != AMDGPU_BO_INVALID_OFFSET) {</div><div class='del'>-		bo-&gt;resource-&gt;start = addr &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	if (addr != AMDGPU_BO_INVALID_OFFSET)</div><div class='ctx'> 		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* allocate GART space */</div><div class='ctx'> 	placement.num_placement = 1;</div><div class='hunk'>@@ -1548,7 +1547,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,</div><div class='ctx'> static void</div><div class='ctx'> amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)</div><div class='ctx'> {</div><div class='del'>-	amdgpu_bo_move_notify(bo, false, NULL);</div><div class='add'>+	amdgpu_bo_move_notify(bo, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct ttm_device_funcs amdgpu_bo_driver = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c<br/>index b14127429f30..3e12763e477a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c</a></div><div class='hunk'>@@ -1062,7 +1062,8 @@ int amdgpu_ucode_create_bo(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	if (adev-&gt;firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {</div><div class='ctx'> 		amdgpu_bo_create_kernel(adev, adev-&gt;firmware.fw_size, PAGE_SIZE,</div><div class='del'>-			amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,</div><div class='add'>+			(amdgpu_sriov_vf(adev) || adev-&gt;debug_use_vram_fw_buf) ?</div><div class='add'>+			AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,</div><div class='ctx'> 			&amp;adev-&gt;firmware.fw_buf,</div><div class='ctx'> 			&amp;adev-&gt;firmware.fw_buf_mc,</div><div class='ctx'> 			&amp;adev-&gt;firmware.fw_buf_ptr);</div><div class='hunk'>@@ -1397,9 +1398,13 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,</div><div class='ctx'> </div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return -ENODEV;</div><div class='add'>+</div><div class='ctx'> 	err = amdgpu_ucode_validate(*fw);</div><div class='del'>-	if (err)</div><div class='add'>+	if (err) {</div><div class='ctx'> 		dev_dbg(adev-&gt;dev, "\"%s\" failed to validate\n", fw_name);</div><div class='add'>+		release_firmware(*fw);</div><div class='add'>+		*fw = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c<br/>index ca45ba8ac171..bfbf59326ee1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c</a></div><div class='hunk'>@@ -86,7 +86,7 @@ static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_sync_create(&amp;sync);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -149,7 +149,7 @@ static int unmap_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> 	long r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, 0);</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		r = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;tbo.base);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br/>index 3a632c3b1a2c..0dcff2889e25 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c</a></div><div class='hunk'>@@ -1099,7 +1099,8 @@ bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	bool xnack_mode = true;</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))</div><div class='add'>+	if (amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))</div><div class='ctx'> 		xnack_mode = false;</div><div class='ctx'> </div><div class='ctx'> 	return xnack_mode;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c<br/>index db6fc0cb18eb..453a4b786cfc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0+</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_simple_kms_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c<br/>index d1b8afd105c9..b8fcb6c55698 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c</a></div><div class='hunk'>@@ -285,6 +285,7 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)</div><div class='ctx'> 	list_for_each_entry_safe(vm_bo, tmp, &amp;vm-&gt;idle, vm_status) {</div><div class='ctx'> 		struct amdgpu_bo *bo = vm_bo-&gt;bo;</div><div class='ctx'> </div><div class='add'>+		vm_bo-&gt;moved = true;</div><div class='ctx'> 		if (!bo || bo-&gt;tbo.type != ttm_bo_type_kernel)</div><div class='ctx'> 			list_move(&amp;vm_bo-&gt;vm_status, &amp;vm_bo-&gt;vm-&gt;moved);</div><div class='ctx'> 		else if (bo-&gt;parent)</div><div class='hunk'>@@ -1438,6 +1439,51 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM</div><div class='add'>+ *</div><div class='add'>+ * @adev: amdgpu_device pointer</div><div class='add'>+ * @vm: requested vm</div><div class='add'>+ * @flush_type: flush type</div><div class='add'>+ * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.</div><div class='add'>+ *</div><div class='add'>+ * Flush TLB if needed for a compute VM.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 for success.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				uint32_t flush_type,</div><div class='add'>+				uint32_t xcc_mask)</div><div class='add'>+{</div><div class='add'>+	uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);</div><div class='add'>+	bool all_hub = false;</div><div class='add'>+	int xcc = 0, r = 0;</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(!vm-&gt;is_compute_context);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * It can be that we race and lose here, but that is extremely unlikely</div><div class='add'>+	 * and the worst thing which could happen is that we flush the changes</div><div class='add'>+	 * into the TLB once more which is harmless.</div><div class='add'>+	 */</div><div class='add'>+	if (atomic64_xchg(&amp;vm-&gt;kfd_last_flushed_seq, tlb_seq) == tlb_seq)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;family == AMDGPU_FAMILY_AI ||</div><div class='add'>+	    adev-&gt;family == AMDGPU_FAMILY_RV)</div><div class='add'>+		all_hub = true;</div><div class='add'>+</div><div class='add'>+	for_each_inst(xcc, xcc_mask) {</div><div class='add'>+		r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm-&gt;pasid, flush_type,</div><div class='add'>+						   all_hub, xcc);</div><div class='add'>+		if (r)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * amdgpu_vm_bo_add - add a bo to a specific vm</div><div class='ctx'>  *</div><div class='ctx'>  * @adev: amdgpu_device pointer</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h<br/>index 2cd86d2bf73f..4740dd65b99d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h</a></div><div class='hunk'>@@ -116,7 +116,7 @@ struct amdgpu_mem_stats;</div><div class='ctx'> #define AMDGPU_VM_FAULT_STOP_FIRST	1</div><div class='ctx'> #define AMDGPU_VM_FAULT_STOP_ALWAYS	2</div><div class='ctx'> </div><div class='del'>-/* Reserve 4MB VRAM for page tables */</div><div class='add'>+/* How much VRAM be reserved for page tables */</div><div class='ctx'> #define AMDGPU_VM_RESERVED_VRAM		(8ULL &lt;&lt; 20)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -324,6 +324,7 @@ struct amdgpu_vm {</div><div class='ctx'> 	/* Last finished delayed update */</div><div class='ctx'> 	atomic64_t		tlb_seq;</div><div class='ctx'> 	struct dma_fence	*last_tlb_flush;</div><div class='add'>+	atomic64_t		kfd_last_flushed_seq;</div><div class='ctx'> </div><div class='ctx'> 	/* How many times we had to re-generate the page tables */</div><div class='ctx'> 	uint64_t		generation;</div><div class='hunk'>@@ -445,6 +446,10 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_vm_handle_moved(struct amdgpu_device *adev,</div><div class='ctx'> 			   struct amdgpu_vm *vm,</div><div class='ctx'> 			   struct ww_acquire_ctx *ticket);</div><div class='add'>+int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,</div><div class='add'>+				struct amdgpu_vm *vm,</div><div class='add'>+				uint32_t flush_type,</div><div class='add'>+				uint32_t xcc_mask);</div><div class='ctx'> void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,</div><div class='ctx'> 			    struct amdgpu_vm *vm, struct amdgpu_bo *bo);</div><div class='ctx'> int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c<br/>index a2287bb25223..a160265ddc07 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c</a></div><div class='hunk'>@@ -642,13 +642,14 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry)</div><div class='ctx'> </div><div class='ctx'> 	if (!entry-&gt;bo)</div><div class='ctx'> 		return;</div><div class='add'>+</div><div class='add'>+	entry-&gt;bo-&gt;vm_bo = NULL;</div><div class='ctx'> 	shadow = amdgpu_bo_shadowed(entry-&gt;bo);</div><div class='ctx'> 	if (shadow) {</div><div class='ctx'> 		ttm_bo_set_bulk_move(&amp;shadow-&gt;tbo, NULL);</div><div class='ctx'> 		amdgpu_bo_unref(&amp;shadow);</div><div class='ctx'> 	}</div><div class='ctx'> 	ttm_bo_set_bulk_move(&amp;entry-&gt;bo-&gt;tbo, NULL);</div><div class='del'>-	entry-&gt;bo-&gt;vm_bo = NULL;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;entry-&gt;vm-&gt;status_lock);</div><div class='ctx'> 	list_del(&amp;entry-&gt;vm_status);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c<br/>index e81579708e96..b9a15d51eb5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_ucode.h"</div><div class='ctx'> #include "amdgpu_vpe.h"</div><div class='add'>+#include "amdgpu_smu.h"</div><div class='ctx'> #include "soc15_common.h"</div><div class='ctx'> #include "vpe_v6_1.h"</div><div class='ctx'> </div><div class='hunk'>@@ -33,8 +34,180 @@</div><div class='ctx'> /* VPE CSA resides in the 4th page of CSA */</div><div class='ctx'> #define AMDGPU_CSA_VPE_OFFSET 	(4096 * 3)</div><div class='ctx'> </div><div class='add'>+/* 1 second timeout */</div><div class='add'>+#define VPE_IDLE_TIMEOUT	msecs_to_jiffies(1000)</div><div class='add'>+</div><div class='add'>+#define VPE_MAX_DPM_LEVEL			4</div><div class='add'>+#define FIXED1_8_BITS_PER_FRACTIONAL_PART	8</div><div class='add'>+#define GET_PRATIO_INTEGER_PART(x)		((x) &gt;&gt; FIXED1_8_BITS_PER_FRACTIONAL_PART)</div><div class='add'>+</div><div class='ctx'> static void vpe_set_ring_funcs(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='add'>+static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)</div><div class='add'>+{</div><div class='add'>+	*remainder = dividend % divisor;</div><div class='add'>+	return dividend / divisor;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline uint16_t complete_integer_division_u16(</div><div class='add'>+	uint16_t dividend,</div><div class='add'>+	uint16_t divisor,</div><div class='add'>+	uint16_t *remainder)</div><div class='add'>+{</div><div class='add'>+	return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)</div><div class='add'>+{</div><div class='add'>+	u16 arg1_value = numerator;</div><div class='add'>+	u16 arg2_value = denominator;</div><div class='add'>+</div><div class='add'>+	uint16_t remainder;</div><div class='add'>+</div><div class='add'>+	/* determine integer part */</div><div class='add'>+	uint16_t res_value = complete_integer_division_u16(</div><div class='add'>+		arg1_value, arg2_value, &amp;remainder);</div><div class='add'>+</div><div class='add'>+	if (res_value &gt; 127 /* CHAR_MAX */)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* determine fractional part */</div><div class='add'>+	{</div><div class='add'>+		unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			remainder &lt;&lt;= 1;</div><div class='add'>+</div><div class='add'>+			res_value &lt;&lt;= 1;</div><div class='add'>+</div><div class='add'>+			if (remainder &gt;= arg2_value) {</div><div class='add'>+				res_value |= 1;</div><div class='add'>+				remainder -= arg2_value;</div><div class='add'>+			}</div><div class='add'>+		} while (--i != 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* round up LSB */</div><div class='add'>+	{</div><div class='add'>+		uint16_t summand = (remainder &lt;&lt; 1) &gt;= arg2_value;</div><div class='add'>+</div><div class='add'>+		if ((res_value + summand) &gt; 32767 /* SHRT_MAX */)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		res_value += summand;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return res_value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)</div><div class='add'>+{</div><div class='add'>+	uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);</div><div class='add'>+</div><div class='add'>+	if (GET_PRATIO_INTEGER_PART(pratio) &gt; 1)</div><div class='add'>+		pratio = 0;</div><div class='add'>+</div><div class='add'>+	return pratio;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),</div><div class='add'>+ * VPE FW will dynamically decide which level should be used according to current loading.</div><div class='add'>+ *</div><div class='add'>+ * Get VPE and SOC clocks from PM, and select the appropriate four clock values,</div><div class='add'>+ * calculate the ratios of adjusting from one clock to another.</div><div class='add'>+ * The VPE FW can then request the appropriate frequency from the PMFW.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = vpe-&gt;ring.adev;</div><div class='add'>+	uint32_t dpm_ctl;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;pm.dpm_enabled) {</div><div class='add'>+		struct dpm_clocks clock_table = { 0 };</div><div class='add'>+		struct dpm_clock *VPEClks;</div><div class='add'>+		struct dpm_clock *SOCClks;</div><div class='add'>+		uint32_t idx;</div><div class='add'>+		uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;</div><div class='add'>+		uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;</div><div class='add'>+</div><div class='add'>+		dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_enable));</div><div class='add'>+		dpm_ctl |= 1; /* DPM enablement */</div><div class='add'>+		WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_enable), dpm_ctl);</div><div class='add'>+</div><div class='add'>+		/* Get VPECLK and SOCCLK */</div><div class='add'>+		if (amdgpu_dpm_get_dpm_clock_table(adev, &amp;clock_table)) {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "%s: get clock failed!\n", __func__);</div><div class='add'>+			goto disable_dpm;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		SOCClks = clock_table.SocClocks;</div><div class='add'>+		VPEClks = clock_table.VPEClocks;</div><div class='add'>+</div><div class='add'>+		/* vpe dpm only cares 4 levels. */</div><div class='add'>+		for (idx = 0; idx &lt; VPE_MAX_DPM_LEVEL; idx++) {</div><div class='add'>+			uint32_t soc_dpm_level;</div><div class='add'>+			uint32_t min_freq;</div><div class='add'>+</div><div class='add'>+			if (idx == 0)</div><div class='add'>+				soc_dpm_level = 0;</div><div class='add'>+			else</div><div class='add'>+				soc_dpm_level = (idx * 2) + 1;</div><div class='add'>+</div><div class='add'>+			/* clamp the max level */</div><div class='add'>+			if (soc_dpm_level &gt; PP_SMU_NUM_VPECLK_DPM_LEVELS - 1)</div><div class='add'>+				soc_dpm_level = PP_SMU_NUM_VPECLK_DPM_LEVELS - 1;</div><div class='add'>+</div><div class='add'>+			min_freq = (SOCClks[soc_dpm_level].Freq &lt; VPEClks[soc_dpm_level].Freq) ?</div><div class='add'>+				   SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;</div><div class='add'>+</div><div class='add'>+			switch (idx) {</div><div class='add'>+			case 0:</div><div class='add'>+				pratio_vmin_freq = min_freq;</div><div class='add'>+				break;</div><div class='add'>+			case 1:</div><div class='add'>+				pratio_vmid_freq = min_freq;</div><div class='add'>+				break;</div><div class='add'>+			case 2:</div><div class='add'>+				pratio_vnorm_freq = min_freq;</div><div class='add'>+				break;</div><div class='add'>+			case 3:</div><div class='add'>+				pratio_vmax_freq = min_freq;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (pratio_vmin_freq &amp;&amp; pratio_vmid_freq &amp;&amp; pratio_vnorm_freq &amp;&amp; pratio_vmax_freq) {</div><div class='add'>+			uint32_t pratio_ctl;</div><div class='add'>+</div><div class='add'>+			pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);</div><div class='add'>+			pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);</div><div class='add'>+			pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);</div><div class='add'>+</div><div class='add'>+			pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid &lt;&lt; 9) | (pratio_vmid_vmin &lt;&lt; 18);</div><div class='add'>+			WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_pratio), pratio_ctl);		/* PRatio */</div><div class='add'>+			WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_request_interval), 24000);	/* 1ms, unit=1/24MHz */</div><div class='add'>+			WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_decision_threshold), 1200000);	/* 50ms */</div><div class='add'>+			WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */</div><div class='add'>+			WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */</div><div class='add'>+			dev_dbg(adev-&gt;dev, "%s: configure vpe dpm pratio done!\n", __func__);</div><div class='add'>+		} else {</div><div class='add'>+			dev_dbg(adev-&gt;dev, "%s: invalid pratio parameters!\n", __func__);</div><div class='add'>+			goto disable_dpm;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+disable_dpm:</div><div class='add'>+	dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_enable));</div><div class='add'>+	dpm_ctl &amp;= 0xfffffffe; /* Disable DPM */</div><div class='add'>+	WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.dpm_enable), dpm_ctl);</div><div class='add'>+	dev_dbg(adev-&gt;dev, "%s: disable vpe dpm\n", __func__);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_firmware_info ucode = {</div><div class='hunk'>@@ -134,6 +307,19 @@ static int vpe_early_init(void *handle)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void vpe_idle_work_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev =</div><div class='add'>+		container_of(work, struct amdgpu_device, vpe.idle_work.work);</div><div class='add'>+	unsigned int fences = 0;</div><div class='add'>+</div><div class='add'>+	fences += amdgpu_fence_count_emitted(&amp;adev-&gt;vpe.ring);</div><div class='add'>+</div><div class='add'>+	if (fences == 0)</div><div class='add'>+		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);</div><div class='add'>+	else</div><div class='add'>+		schedule_delayed_work(&amp;adev-&gt;vpe.idle_work, VPE_IDLE_TIMEOUT);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static int vpe_common_init(struct amdgpu_vpe *vpe)</div><div class='ctx'> {</div><div class='hunk'>@@ -150,6 +336,9 @@ static int vpe_common_init(struct amdgpu_vpe *vpe)</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	vpe-&gt;context_started = false;</div><div class='add'>+	INIT_DELAYED_WORK(&amp;adev-&gt;vpe.idle_work, vpe_idle_work_handler);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -219,6 +408,9 @@ static int vpe_hw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	vpe_ring_stop(vpe);</div><div class='ctx'> </div><div class='add'>+	/* Power off VPE */</div><div class='add'>+	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -226,6 +418,8 @@ static int vpe_suspend(void *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;vpe.idle_work);</div><div class='add'>+</div><div class='ctx'> 	return vpe_hw_fini(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -430,6 +624,21 @@ static int vpe_set_clockgating_state(void *handle,</div><div class='ctx'> static int vpe_set_powergating_state(void *handle,</div><div class='ctx'> 				     enum amd_powergating_state state)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='add'>+	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='add'>+</div><div class='add'>+	if (!adev-&gt;pm.dpm_enabled)</div><div class='add'>+		dev_err(adev-&gt;dev, "Without PM, cannot support powergating\n");</div><div class='add'>+</div><div class='add'>+	dev_dbg(adev-&gt;dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");</div><div class='add'>+</div><div class='add'>+	if (state == AMD_PG_STATE_GATE) {</div><div class='add'>+		amdgpu_dpm_enable_vpe(adev, false);</div><div class='add'>+		vpe-&gt;context_started = false;</div><div class='add'>+	} else {</div><div class='add'>+		amdgpu_dpm_enable_vpe(adev, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -595,6 +804,38 @@ err0:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void vpe_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+	struct amdgpu_vpe *vpe = &amp;adev-&gt;vpe;</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;adev-&gt;vpe.idle_work);</div><div class='add'>+</div><div class='add'>+	/* Power on VPE and notify VPE of new context  */</div><div class='add'>+	if (!vpe-&gt;context_started) {</div><div class='add'>+		uint32_t context_notify;</div><div class='add'>+</div><div class='add'>+		/* Power on VPE */</div><div class='add'>+		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);</div><div class='add'>+</div><div class='add'>+		/* Indicates that a job from a new context has been submitted. */</div><div class='add'>+		context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.context_indicator));</div><div class='add'>+		if ((context_notify &amp; 0x1) == 0)</div><div class='add'>+			context_notify |= 0x1;</div><div class='add'>+		else</div><div class='add'>+			context_notify &amp;= ~(0x1);</div><div class='add'>+		WREG32(vpe_get_reg_offset(vpe, 0, vpe-&gt;regs.context_indicator), context_notify);</div><div class='add'>+		vpe-&gt;context_started = true;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vpe_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	schedule_delayed_work(&amp;adev-&gt;vpe.idle_work, VPE_IDLE_TIMEOUT);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct amdgpu_ring_funcs vpe_ring_funcs = {</div><div class='ctx'> 	.type = AMDGPU_RING_TYPE_VPE,</div><div class='ctx'> 	.align_mask = 0xf,</div><div class='hunk'>@@ -625,6 +866,8 @@ static const struct amdgpu_ring_funcs vpe_ring_funcs = {</div><div class='ctx'> 	.init_cond_exec = vpe_ring_init_cond_exec,</div><div class='ctx'> 	.patch_cond_exec = vpe_ring_patch_cond_exec,</div><div class='ctx'> 	.preempt_ib = vpe_ring_preempt_ib,</div><div class='add'>+	.begin_use = vpe_ring_begin_use,</div><div class='add'>+	.end_use = vpe_ring_end_use,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void vpe_set_ring_funcs(struct amdgpu_device *adev)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h<br/>index 29d56f7ae4a9..1153ddaea64d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h</a></div><div class='hunk'>@@ -47,6 +47,15 @@ struct vpe_regs {</div><div class='ctx'> 	uint32_t queue0_rb_wptr_lo;</div><div class='ctx'> 	uint32_t queue0_rb_wptr_hi;</div><div class='ctx'> 	uint32_t queue0_preempt;</div><div class='add'>+</div><div class='add'>+	uint32_t dpm_enable;</div><div class='add'>+	uint32_t dpm_pratio;</div><div class='add'>+	uint32_t dpm_request_interval;</div><div class='add'>+	uint32_t dpm_decision_threshold;</div><div class='add'>+	uint32_t dpm_busy_clamp_threshold;</div><div class='add'>+	uint32_t dpm_idle_clamp_threshold;</div><div class='add'>+	uint32_t dpm_request_lv;</div><div class='add'>+	uint32_t context_indicator;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_vpe {</div><div class='hunk'>@@ -63,12 +72,15 @@ struct amdgpu_vpe {</div><div class='ctx'> 	struct amdgpu_bo		*cmdbuf_obj;</div><div class='ctx'> 	uint64_t			cmdbuf_gpu_addr;</div><div class='ctx'> 	uint32_t			*cmdbuf_cpu_addr;</div><div class='add'>+	struct delayed_work		idle_work;</div><div class='add'>+	bool				context_started;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);</div><div class='ctx'> int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);</div><div class='ctx'> int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);</div><div class='add'>+int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);</div><div class='ctx'> </div><div class='ctx'> #define vpe_ring_init(vpe) ((vpe)-&gt;funcs-&gt;ring_init ? (vpe)-&gt;funcs-&gt;ring_init((vpe)) : 0)</div><div class='ctx'> #define vpe_ring_start(vpe) ((vpe)-&gt;funcs-&gt;ring_start ? (vpe)-&gt;funcs-&gt;ring_start((vpe)) : 0)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c<br/>index bd20cb3b9819..a6c88f2fe6e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c</a></div><div class='hunk'>@@ -413,6 +413,38 @@ static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,</div><div class='ctx'> 	return sysfs_emit(buf, "%s\n", buf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t amdgpu_xgmi_show_connected_port_num(struct device *dev,</div><div class='add'>+					struct device_attribute *attr,</div><div class='add'>+					char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	struct psp_xgmi_topology_info *top = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='add'>+	int i, j, size = 0;</div><div class='add'>+	int current_node;</div><div class='add'>+	/*</div><div class='add'>+	 * get the node id in the sysfs for the current socket and show</div><div class='add'>+	 * it in the port num info output in the sysfs for easy reading.</div><div class='add'>+	 * it is NOT the one retrieved from xgmi ta.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; top-&gt;num_nodes; i++) {</div><div class='add'>+		if (top-&gt;nodes[i].node_id == adev-&gt;gmc.xgmi.node_id) {</div><div class='add'>+			current_node = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; top-&gt;num_nodes; i++) {</div><div class='add'>+		for (j = 0; j &lt; top-&gt;nodes[i].num_links; j++)</div><div class='add'>+			/* node id in sysfs starts from 1 rather than 0 so +1 here */</div><div class='add'>+			size += sysfs_emit_at(buf, size, "%02x:%02x -&gt;  %02x:%02x\n", current_node + 1,</div><div class='add'>+					      top-&gt;nodes[i].port_num[j].src_xgmi_port_num, i + 1,</div><div class='add'>+					      top-&gt;nodes[i].port_num[j].dst_xgmi_port_num);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define AMDGPU_XGMI_SET_FICAA(o)	((o) | 0x456801)</div><div class='ctx'> static ssize_t amdgpu_xgmi_show_error(struct device *dev,</div><div class='ctx'> 				      struct device_attribute *attr,</div><div class='hunk'>@@ -452,6 +484,7 @@ static DEVICE_ATTR(xgmi_physical_id, 0444, amdgpu_xgmi_show_physical_id, NULL);</div><div class='ctx'> static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);</div><div class='ctx'> static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);</div><div class='ctx'> static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);</div><div class='add'>+static DEVICE_ATTR(xgmi_port_num, S_IRUGO, amdgpu_xgmi_show_connected_port_num, NULL);</div><div class='ctx'> </div><div class='ctx'> static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,</div><div class='ctx'> 					 struct amdgpu_hive_info *hive)</div><div class='hunk'>@@ -487,6 +520,13 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		pr_err("failed to create xgmi_num_links\n");</div><div class='ctx'> </div><div class='add'>+	/* Create xgmi port num file if supported */</div><div class='add'>+	if (adev-&gt;psp.xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG) {</div><div class='add'>+		ret = device_create_file(adev-&gt;dev, &amp;dev_attr_xgmi_port_num);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_err(adev-&gt;dev, "failed to create xgmi_port_num\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Create sysfs link to hive info folder on the first device */</div><div class='ctx'> 	if (hive-&gt;kobj.parent != (&amp;adev-&gt;dev-&gt;kobj)) {</div><div class='ctx'> 		ret = sysfs_create_link(&amp;adev-&gt;dev-&gt;kobj, &amp;hive-&gt;kobj,</div><div class='hunk'>@@ -517,6 +557,8 @@ remove_file:</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_error);</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_num_hops);</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_num_links);</div><div class='add'>+	if (adev-&gt;psp.xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_port_num);</div><div class='ctx'> </div><div class='ctx'> success:</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -533,6 +575,8 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_error);</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_num_hops);</div><div class='ctx'> 	device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_num_links);</div><div class='add'>+	if (adev-&gt;psp.xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG)</div><div class='add'>+		device_remove_file(adev-&gt;dev, &amp;dev_attr_xgmi_port_num);</div><div class='ctx'> </div><div class='ctx'> 	if (hive-&gt;kobj.parent != (&amp;adev-&gt;dev-&gt;kobj))</div><div class='ctx'> 		sysfs_remove_link(&amp;adev-&gt;dev-&gt;kobj,"xgmi_hive_info");</div><div class='hunk'>@@ -779,6 +823,28 @@ static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_inf</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void amdgpu_xgmi_fill_topology_info(struct amdgpu_device *adev,</div><div class='add'>+	struct amdgpu_device *peer_adev)</div><div class='add'>+{</div><div class='add'>+	struct psp_xgmi_topology_info *top_info = &amp;adev-&gt;psp.xgmi_context.top_info;</div><div class='add'>+	struct psp_xgmi_topology_info *peer_info = &amp;peer_adev-&gt;psp.xgmi_context.top_info;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; peer_info-&gt;num_nodes; i++) {</div><div class='add'>+		if (peer_info-&gt;nodes[i].node_id == adev-&gt;gmc.xgmi.node_id) {</div><div class='add'>+			for (int j = 0; j &lt; top_info-&gt;num_nodes; j++) {</div><div class='add'>+				if (top_info-&gt;nodes[j].node_id == peer_adev-&gt;gmc.xgmi.node_id) {</div><div class='add'>+					peer_info-&gt;nodes[i].num_hops = top_info-&gt;nodes[j].num_hops;</div><div class='add'>+					peer_info-&gt;nodes[i].is_sharing_enabled =</div><div class='add'>+							top_info-&gt;nodes[j].is_sharing_enabled;</div><div class='add'>+					peer_info-&gt;nodes[i].num_links =</div><div class='add'>+							top_info-&gt;nodes[j].num_links;</div><div class='add'>+					return;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct psp_xgmi_topology_info *top_info;</div><div class='hunk'>@@ -853,18 +919,38 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)</div><div class='ctx'> 				goto exit_unlock;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		/* get latest topology info for each device from psp */</div><div class='del'>-		list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='del'>-			ret = psp_xgmi_get_topology_info(&amp;tmp_adev-&gt;psp, count,</div><div class='del'>-					&amp;tmp_adev-&gt;psp.xgmi_context.top_info, false);</div><div class='add'>+		if (amdgpu_sriov_vf(adev) &amp;&amp;</div><div class='add'>+			adev-&gt;psp.xgmi_context.xgmi_ta_caps &amp; EXTEND_PEER_LINK_INFO_CMD_FLAG) {</div><div class='add'>+			/* only get topology for VF being init if it can support full duplex */</div><div class='add'>+			ret = psp_xgmi_get_topology_info(&amp;adev-&gt;psp, count,</div><div class='add'>+						&amp;adev-&gt;psp.xgmi_context.top_info, false);</div><div class='ctx'> 			if (ret) {</div><div class='del'>-				dev_err(tmp_adev-&gt;dev,</div><div class='add'>+				dev_err(adev-&gt;dev,</div><div class='ctx'> 					"XGMI: Get topology failure on device %llx, hive %llx, ret %d",</div><div class='del'>-					tmp_adev-&gt;gmc.xgmi.node_id,</div><div class='del'>-					tmp_adev-&gt;gmc.xgmi.hive_id, ret);</div><div class='del'>-				/* To do : continue with some node failed or disable the whole hive */</div><div class='add'>+					adev-&gt;gmc.xgmi.node_id,</div><div class='add'>+					adev-&gt;gmc.xgmi.hive_id, ret);</div><div class='add'>+				/* To do: continue with some node failed or disable the whole hive*/</div><div class='ctx'> 				goto exit_unlock;</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			/* fill the topology info for peers instead of getting from PSP */</div><div class='add'>+			list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+				amdgpu_xgmi_fill_topology_info(adev, tmp_adev);</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* get latest topology info for each device from psp */</div><div class='add'>+			list_for_each_entry(tmp_adev, &amp;hive-&gt;device_list, gmc.xgmi.head) {</div><div class='add'>+				ret = psp_xgmi_get_topology_info(&amp;tmp_adev-&gt;psp, count,</div><div class='add'>+					&amp;tmp_adev-&gt;psp.xgmi_context.top_info, false);</div><div class='add'>+				if (ret) {</div><div class='add'>+					dev_err(tmp_adev-&gt;dev,</div><div class='add'>+						"XGMI: Get topology failure on device %llx, hive %llx, ret %d",</div><div class='add'>+						tmp_adev-&gt;gmc.xgmi.node_id,</div><div class='add'>+						tmp_adev-&gt;gmc.xgmi.hive_id, ret);</div><div class='add'>+					/* To do : continue with some node failed or disable the whole hive */</div><div class='add'>+					goto exit_unlock;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* get topology again for hives that support extended data */</div><div class='hunk'>@@ -1227,10 +1313,10 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a</div><div class='ctx'> </div><div class='ctx'> 	switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) {</div><div class='ctx'> 	case AMDGPU_MCA_ERROR_TYPE_UE:</div><div class='del'>-		amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, 1ULL);</div><div class='add'>+		amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, NULL, 1ULL);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AMDGPU_MCA_ERROR_TYPE_CE:</div><div class='del'>-		amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, 1ULL);</div><div class='add'>+		amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, NULL, 1ULL);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h<br/>index 6cab882e8061..1592c63b3099 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h</a></div><div class='hunk'>@@ -43,7 +43,6 @@ struct amdgpu_hive_info {</div><div class='ctx'> 	} pstate;</div><div class='ctx'> </div><div class='ctx'> 	struct amdgpu_reset_domain *reset_domain;</div><div class='del'>-	uint32_t device_remove_count;</div><div class='ctx'> 	atomic_t ras_recovery;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c<br/>index 3f715e7fe1a9..d6f808acfb17 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'> #include "soc15.h"</div><div class='ctx'> </div><div class='ctx'> #include "soc15_common.h"</div><div class='add'>+#include "amdgpu_reg_state.h"</div><div class='ctx'> #include "amdgpu_xcp.h"</div><div class='ctx'> #include "gfx_v9_4_3.h"</div><div class='ctx'> #include "gfxhub_v1_2.h"</div><div class='hunk'>@@ -656,3 +657,416 @@ int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static void aqua_read_smn(struct amdgpu_device *adev,</div><div class='add'>+			  struct amdgpu_smn_reg_data *regdata,</div><div class='add'>+			  uint64_t smn_addr)</div><div class='add'>+{</div><div class='add'>+	regdata-&gt;addr = smn_addr;</div><div class='add'>+	regdata-&gt;value = RREG32_PCIE(smn_addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct aqua_reg_list {</div><div class='add'>+	uint64_t start_addr;</div><div class='add'>+	uint32_t num_regs;</div><div class='add'>+	uint32_t incrx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DW_ADDR_INCR	4</div><div class='add'>+</div><div class='add'>+static void aqua_read_smn_ext(struct amdgpu_device *adev,</div><div class='add'>+			      struct amdgpu_smn_reg_data *regdata,</div><div class='add'>+			      uint64_t smn_addr, int i)</div><div class='add'>+{</div><div class='add'>+	regdata-&gt;addr =</div><div class='add'>+		smn_addr + adev-&gt;asic_funcs-&gt;encode_ext_smn_addressing(i);</div><div class='add'>+	regdata-&gt;value = RREG32_PCIE_EXT(regdata-&gt;addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1A340218	0x1A340218</div><div class='add'>+#define smnreg_0x1A3402E4	0x1A3402E4</div><div class='add'>+#define smnreg_0x1A340294	0x1A340294</div><div class='add'>+#define smreg_0x1A380088	0x1A380088</div><div class='add'>+</div><div class='add'>+#define NUM_PCIE_SMN_REGS	14</div><div class='add'>+</div><div class='add'>+static struct aqua_reg_list pcie_reg_addrs[] = {</div><div class='add'>+	{ smnreg_0x1A340218, 1, 0 },</div><div class='add'>+	{ smnreg_0x1A3402E4, 1, 0 },</div><div class='add'>+	{ smnreg_0x1A340294, 6, DW_ADDR_INCR },</div><div class='add'>+	{ smreg_0x1A380088, 6, DW_ADDR_INCR },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t aqua_vanjaram_read_pcie_state(struct amdgpu_device *adev,</div><div class='add'>+					     void *buf, size_t max_size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_reg_state_pcie_v1_0 *pcie_reg_state;</div><div class='add'>+	uint32_t start_addr, incrx, num_regs, szbuf;</div><div class='add'>+	struct amdgpu_regs_pcie_v1_0 *pcie_regs;</div><div class='add'>+	struct amdgpu_smn_reg_data *reg_data;</div><div class='add'>+	struct pci_dev *us_pdev, *ds_pdev;</div><div class='add'>+	int aer_cap, r, n;</div><div class='add'>+</div><div class='add'>+	if (!buf || !max_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	pcie_reg_state = (struct amdgpu_reg_state_pcie_v1_0 *)buf;</div><div class='add'>+</div><div class='add'>+	szbuf = sizeof(*pcie_reg_state) +</div><div class='add'>+		amdgpu_reginst_size(1, sizeof(*pcie_regs), NUM_PCIE_SMN_REGS);</div><div class='add'>+	/* Only one instance of pcie regs */</div><div class='add'>+	if (max_size &lt; szbuf)</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+</div><div class='add'>+	pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf +</div><div class='add'>+						     sizeof(*pcie_reg_state));</div><div class='add'>+	pcie_regs-&gt;inst_header.instance = 0;</div><div class='add'>+	pcie_regs-&gt;inst_header.state = AMDGPU_INST_S_OK;</div><div class='add'>+	pcie_regs-&gt;inst_header.num_smn_regs = NUM_PCIE_SMN_REGS;</div><div class='add'>+</div><div class='add'>+	reg_data = pcie_regs-&gt;smn_reg_values;</div><div class='add'>+</div><div class='add'>+	for (r = 0; r &lt; ARRAY_SIZE(pcie_reg_addrs); r++) {</div><div class='add'>+		start_addr = pcie_reg_addrs[r].start_addr;</div><div class='add'>+		incrx = pcie_reg_addrs[r].incrx;</div><div class='add'>+		num_regs = pcie_reg_addrs[r].num_regs;</div><div class='add'>+		for (n = 0; n &lt; num_regs; n++) {</div><div class='add'>+			aqua_read_smn(adev, reg_data, start_addr + n * incrx);</div><div class='add'>+			++reg_data;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ds_pdev = pci_upstream_bridge(adev-&gt;pdev);</div><div class='add'>+	us_pdev = pci_upstream_bridge(ds_pdev);</div><div class='add'>+</div><div class='add'>+	pcie_capability_read_word(us_pdev, PCI_EXP_DEVSTA,</div><div class='add'>+				  &amp;pcie_regs-&gt;device_status);</div><div class='add'>+	pcie_capability_read_word(us_pdev, PCI_EXP_LNKSTA,</div><div class='add'>+				  &amp;pcie_regs-&gt;link_status);</div><div class='add'>+</div><div class='add'>+	aer_cap = pci_find_ext_capability(us_pdev, PCI_EXT_CAP_ID_ERR);</div><div class='add'>+	if (aer_cap) {</div><div class='add'>+		pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_COR_STATUS,</div><div class='add'>+				      &amp;pcie_regs-&gt;pcie_corr_err_status);</div><div class='add'>+		pci_read_config_dword(us_pdev, aer_cap + PCI_ERR_UNCOR_STATUS,</div><div class='add'>+				      &amp;pcie_regs-&gt;pcie_uncorr_err_status);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(us_pdev, PCI_PRIMARY_BUS,</div><div class='add'>+			      &amp;pcie_regs-&gt;sub_bus_number_latency);</div><div class='add'>+</div><div class='add'>+	pcie_reg_state-&gt;common_header.structure_size = szbuf;</div><div class='add'>+	pcie_reg_state-&gt;common_header.format_revision = 1;</div><div class='add'>+	pcie_reg_state-&gt;common_header.content_revision = 0;</div><div class='add'>+	pcie_reg_state-&gt;common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE;</div><div class='add'>+	pcie_reg_state-&gt;common_header.num_instances = 1;</div><div class='add'>+</div><div class='add'>+	return pcie_reg_state-&gt;common_header.structure_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define smnreg_0x11A00050	0x11A00050</div><div class='add'>+#define smnreg_0x11A00180	0x11A00180</div><div class='add'>+#define smnreg_0x11A00070	0x11A00070</div><div class='add'>+#define smnreg_0x11A00200	0x11A00200</div><div class='add'>+#define smnreg_0x11A0020C	0x11A0020C</div><div class='add'>+#define smnreg_0x11A00210	0x11A00210</div><div class='add'>+#define smnreg_0x11A00108	0x11A00108</div><div class='add'>+</div><div class='add'>+#define XGMI_LINK_REG(smnreg, l) ((smnreg) | (l &lt;&lt; 20))</div><div class='add'>+</div><div class='add'>+#define NUM_XGMI_SMN_REGS 25</div><div class='add'>+</div><div class='add'>+static struct aqua_reg_list xgmi_reg_addrs[] = {</div><div class='add'>+	{ smnreg_0x11A00050, 1, 0 },</div><div class='add'>+	{ smnreg_0x11A00180, 16, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x11A00070, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x11A00200, 1, 0 },</div><div class='add'>+	{ smnreg_0x11A0020C, 1, 0 },</div><div class='add'>+	{ smnreg_0x11A00210, 1, 0 },</div><div class='add'>+	{ smnreg_0x11A00108, 1, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev,</div><div class='add'>+					     void *buf, size_t max_size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_reg_state_xgmi_v1_0 *xgmi_reg_state;</div><div class='add'>+	uint32_t start_addr, incrx, num_regs, szbuf;</div><div class='add'>+	struct amdgpu_regs_xgmi_v1_0 *xgmi_regs;</div><div class='add'>+	struct amdgpu_smn_reg_data *reg_data;</div><div class='add'>+	const int max_xgmi_instances = 8;</div><div class='add'>+	int inst = 0, i, j, r, n;</div><div class='add'>+	const int xgmi_inst = 2;</div><div class='add'>+	void *p;</div><div class='add'>+</div><div class='add'>+	if (!buf || !max_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	xgmi_reg_state = (struct amdgpu_reg_state_xgmi_v1_0 *)buf;</div><div class='add'>+</div><div class='add'>+	szbuf = sizeof(*xgmi_reg_state) +</div><div class='add'>+		amdgpu_reginst_size(max_xgmi_instances, sizeof(*xgmi_regs),</div><div class='add'>+				    NUM_XGMI_SMN_REGS);</div><div class='add'>+	/* Only one instance of pcie regs */</div><div class='add'>+	if (max_size &lt; szbuf)</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+</div><div class='add'>+	p = &amp;xgmi_reg_state-&gt;xgmi_state_regs[0];</div><div class='add'>+	for_each_inst(i, adev-&gt;aid_mask) {</div><div class='add'>+		for (j = 0; j &lt; xgmi_inst; ++j) {</div><div class='add'>+			xgmi_regs = (struct amdgpu_regs_xgmi_v1_0 *)p;</div><div class='add'>+			xgmi_regs-&gt;inst_header.instance = inst++;</div><div class='add'>+</div><div class='add'>+			xgmi_regs-&gt;inst_header.state = AMDGPU_INST_S_OK;</div><div class='add'>+			xgmi_regs-&gt;inst_header.num_smn_regs = NUM_XGMI_SMN_REGS;</div><div class='add'>+</div><div class='add'>+			reg_data = xgmi_regs-&gt;smn_reg_values;</div><div class='add'>+</div><div class='add'>+			for (r = 0; r &lt; ARRAY_SIZE(xgmi_reg_addrs); r++) {</div><div class='add'>+				start_addr = xgmi_reg_addrs[r].start_addr;</div><div class='add'>+				incrx = xgmi_reg_addrs[r].incrx;</div><div class='add'>+				num_regs = xgmi_reg_addrs[r].num_regs;</div><div class='add'>+</div><div class='add'>+				for (n = 0; n &lt; num_regs; n++) {</div><div class='add'>+					aqua_read_smn_ext(</div><div class='add'>+						adev, reg_data,</div><div class='add'>+						XGMI_LINK_REG(start_addr, j) +</div><div class='add'>+							n * incrx,</div><div class='add'>+						i);</div><div class='add'>+					++reg_data;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			p = reg_data;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xgmi_reg_state-&gt;common_header.structure_size = szbuf;</div><div class='add'>+	xgmi_reg_state-&gt;common_header.format_revision = 1;</div><div class='add'>+	xgmi_reg_state-&gt;common_header.content_revision = 0;</div><div class='add'>+	xgmi_reg_state-&gt;common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI;</div><div class='add'>+	xgmi_reg_state-&gt;common_header.num_instances = max_xgmi_instances;</div><div class='add'>+</div><div class='add'>+	return xgmi_reg_state-&gt;common_header.structure_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define smnreg_0x11C00070	0x11C00070</div><div class='add'>+#define smnreg_0x11C00210	0x11C00210</div><div class='add'>+</div><div class='add'>+static struct aqua_reg_list wafl_reg_addrs[] = {</div><div class='add'>+	{ smnreg_0x11C00070, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x11C00210, 1, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define WAFL_LINK_REG(smnreg, l) ((smnreg) | (l &lt;&lt; 20))</div><div class='add'>+</div><div class='add'>+#define NUM_WAFL_SMN_REGS 5</div><div class='add'>+</div><div class='add'>+static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev,</div><div class='add'>+					     void *buf, size_t max_size)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_reg_state_wafl_v1_0 *wafl_reg_state;</div><div class='add'>+	uint32_t start_addr, incrx, num_regs, szbuf;</div><div class='add'>+	struct amdgpu_regs_wafl_v1_0 *wafl_regs;</div><div class='add'>+	struct amdgpu_smn_reg_data *reg_data;</div><div class='add'>+	const int max_wafl_instances = 8;</div><div class='add'>+	int inst = 0, i, j, r, n;</div><div class='add'>+	const int wafl_inst = 2;</div><div class='add'>+	void *p;</div><div class='add'>+</div><div class='add'>+	if (!buf || !max_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	wafl_reg_state = (struct amdgpu_reg_state_wafl_v1_0 *)buf;</div><div class='add'>+</div><div class='add'>+	szbuf = sizeof(*wafl_reg_state) +</div><div class='add'>+		amdgpu_reginst_size(max_wafl_instances, sizeof(*wafl_regs),</div><div class='add'>+				    NUM_WAFL_SMN_REGS);</div><div class='add'>+</div><div class='add'>+	if (max_size &lt; szbuf)</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+</div><div class='add'>+	p = &amp;wafl_reg_state-&gt;wafl_state_regs[0];</div><div class='add'>+	for_each_inst(i, adev-&gt;aid_mask) {</div><div class='add'>+		for (j = 0; j &lt; wafl_inst; ++j) {</div><div class='add'>+			wafl_regs = (struct amdgpu_regs_wafl_v1_0 *)p;</div><div class='add'>+			wafl_regs-&gt;inst_header.instance = inst++;</div><div class='add'>+</div><div class='add'>+			wafl_regs-&gt;inst_header.state = AMDGPU_INST_S_OK;</div><div class='add'>+			wafl_regs-&gt;inst_header.num_smn_regs = NUM_WAFL_SMN_REGS;</div><div class='add'>+</div><div class='add'>+			reg_data = wafl_regs-&gt;smn_reg_values;</div><div class='add'>+</div><div class='add'>+			for (r = 0; r &lt; ARRAY_SIZE(wafl_reg_addrs); r++) {</div><div class='add'>+				start_addr = wafl_reg_addrs[r].start_addr;</div><div class='add'>+				incrx = wafl_reg_addrs[r].incrx;</div><div class='add'>+				num_regs = wafl_reg_addrs[r].num_regs;</div><div class='add'>+				for (n = 0; n &lt; num_regs; n++) {</div><div class='add'>+					aqua_read_smn_ext(</div><div class='add'>+						adev, reg_data,</div><div class='add'>+						WAFL_LINK_REG(start_addr, j) +</div><div class='add'>+							n * incrx,</div><div class='add'>+						i);</div><div class='add'>+					++reg_data;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			p = reg_data;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wafl_reg_state-&gt;common_header.structure_size = szbuf;</div><div class='add'>+	wafl_reg_state-&gt;common_header.format_revision = 1;</div><div class='add'>+	wafl_reg_state-&gt;common_header.content_revision = 0;</div><div class='add'>+	wafl_reg_state-&gt;common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL;</div><div class='add'>+	wafl_reg_state-&gt;common_header.num_instances = max_wafl_instances;</div><div class='add'>+</div><div class='add'>+	return wafl_reg_state-&gt;common_header.structure_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1B311060 0x1B311060</div><div class='add'>+#define smnreg_0x1B411060 0x1B411060</div><div class='add'>+#define smnreg_0x1B511060 0x1B511060</div><div class='add'>+#define smnreg_0x1B611060 0x1B611060</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1C307120 0x1C307120</div><div class='add'>+#define smnreg_0x1C317120 0x1C317120</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1C320830 0x1C320830</div><div class='add'>+#define smnreg_0x1C380830 0x1C380830</div><div class='add'>+#define smnreg_0x1C3D0830 0x1C3D0830</div><div class='add'>+#define smnreg_0x1C420830 0x1C420830</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1C320100 0x1C320100</div><div class='add'>+#define smnreg_0x1C380100 0x1C380100</div><div class='add'>+#define smnreg_0x1C3D0100 0x1C3D0100</div><div class='add'>+#define smnreg_0x1C420100 0x1C420100</div><div class='add'>+</div><div class='add'>+#define smnreg_0x1B310500 0x1B310500</div><div class='add'>+#define smnreg_0x1C300400 0x1C300400</div><div class='add'>+</div><div class='add'>+#define USR_CAKE_INCR 0x11000</div><div class='add'>+#define USR_LINK_INCR 0x100000</div><div class='add'>+#define USR_CP_INCR 0x10000</div><div class='add'>+</div><div class='add'>+#define NUM_USR_SMN_REGS	20</div><div class='add'>+</div><div class='add'>+struct aqua_reg_list usr_reg_addrs[] = {</div><div class='add'>+	{ smnreg_0x1B311060, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x1B411060, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x1B511060, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x1B611060, 4, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x1C307120, 2, DW_ADDR_INCR },</div><div class='add'>+	{ smnreg_0x1C317120, 2, DW_ADDR_INCR },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define NUM_USR1_SMN_REGS	46</div><div class='add'>+struct aqua_reg_list usr1_reg_addrs[] = {</div><div class='add'>+	{ smnreg_0x1C320830, 6, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C380830, 5, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C3D0830, 5, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C420830, 4, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C320100, 6, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C380100, 5, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C3D0100, 5, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1C420100, 4, USR_CAKE_INCR },</div><div class='add'>+	{ smnreg_0x1B310500, 4, USR_LINK_INCR },</div><div class='add'>+	{ smnreg_0x1C300400, 2, USR_CP_INCR },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev,</div><div class='add'>+					    void *buf, size_t max_size,</div><div class='add'>+					    int reg_state)</div><div class='add'>+{</div><div class='add'>+	uint32_t start_addr, incrx, num_regs, szbuf, num_smn;</div><div class='add'>+	struct amdgpu_reg_state_usr_v1_0 *usr_reg_state;</div><div class='add'>+	struct amdgpu_regs_usr_v1_0 *usr_regs;</div><div class='add'>+	struct amdgpu_smn_reg_data *reg_data;</div><div class='add'>+	const int max_usr_instances = 4;</div><div class='add'>+	struct aqua_reg_list *reg_addrs;</div><div class='add'>+	int inst = 0, i, n, r, arr_size;</div><div class='add'>+	void *p;</div><div class='add'>+</div><div class='add'>+	if (!buf || !max_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (reg_state) {</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_USR:</div><div class='add'>+		arr_size = ARRAY_SIZE(usr_reg_addrs);</div><div class='add'>+		reg_addrs = usr_reg_addrs;</div><div class='add'>+		num_smn = NUM_USR_SMN_REGS;</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_USR_1:</div><div class='add'>+		arr_size = ARRAY_SIZE(usr1_reg_addrs);</div><div class='add'>+		reg_addrs = usr1_reg_addrs;</div><div class='add'>+		num_smn = NUM_USR1_SMN_REGS;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usr_reg_state = (struct amdgpu_reg_state_usr_v1_0 *)buf;</div><div class='add'>+</div><div class='add'>+	szbuf = sizeof(*usr_reg_state) + amdgpu_reginst_size(max_usr_instances,</div><div class='add'>+							     sizeof(*usr_regs),</div><div class='add'>+							     num_smn);</div><div class='add'>+	if (max_size &lt; szbuf)</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+</div><div class='add'>+	p = &amp;usr_reg_state-&gt;usr_state_regs[0];</div><div class='add'>+	for_each_inst(i, adev-&gt;aid_mask) {</div><div class='add'>+		usr_regs = (struct amdgpu_regs_usr_v1_0 *)p;</div><div class='add'>+		usr_regs-&gt;inst_header.instance = inst++;</div><div class='add'>+		usr_regs-&gt;inst_header.state = AMDGPU_INST_S_OK;</div><div class='add'>+		usr_regs-&gt;inst_header.num_smn_regs = num_smn;</div><div class='add'>+		reg_data = usr_regs-&gt;smn_reg_values;</div><div class='add'>+</div><div class='add'>+		for (r = 0; r &lt; arr_size; r++) {</div><div class='add'>+			start_addr = reg_addrs[r].start_addr;</div><div class='add'>+			incrx = reg_addrs[r].incrx;</div><div class='add'>+			num_regs = reg_addrs[r].num_regs;</div><div class='add'>+			for (n = 0; n &lt; num_regs; n++) {</div><div class='add'>+				aqua_read_smn_ext(adev, reg_data,</div><div class='add'>+						  start_addr + n * incrx, i);</div><div class='add'>+				reg_data++;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		p = reg_data;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usr_reg_state-&gt;common_header.structure_size = szbuf;</div><div class='add'>+	usr_reg_state-&gt;common_header.format_revision = 1;</div><div class='add'>+	usr_reg_state-&gt;common_header.content_revision = 0;</div><div class='add'>+	usr_reg_state-&gt;common_header.state_type = AMDGPU_REG_STATE_TYPE_USR;</div><div class='add'>+	usr_reg_state-&gt;common_header.num_instances = max_usr_instances;</div><div class='add'>+</div><div class='add'>+	return usr_reg_state-&gt;common_header.structure_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,</div><div class='add'>+				    enum amdgpu_reg_state reg_state, void *buf,</div><div class='add'>+				    size_t max_size)</div><div class='add'>+{</div><div class='add'>+	ssize_t size;</div><div class='add'>+</div><div class='add'>+	switch (reg_state) {</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_PCIE:</div><div class='add'>+		size = aqua_vanjaram_read_pcie_state(adev, buf, max_size);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_XGMI:</div><div class='add'>+		size = aqua_vanjaram_read_xgmi_state(adev, buf, max_size);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_WAFL:</div><div class='add'>+		size = aqua_vanjaram_read_wafl_state(adev, buf, max_size);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_USR:</div><div class='add'>+		size = aqua_vanjaram_read_usr_state(adev, buf, max_size,</div><div class='add'>+						    AMDGPU_REG_STATE_TYPE_USR);</div><div class='add'>+		break;</div><div class='add'>+	case AMDGPU_REG_STATE_TYPE_USR_1:</div><div class='add'>+		size = aqua_vanjaram_read_usr_state(</div><div class='add'>+			adev, buf, max_size, AMDGPU_REG_STATE_TYPE_USR_1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c<br/>index f0737fb3a999..d1bba9c64e16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/athub_v3_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/athub_v3_0.c</a></div><div class='hunk'>@@ -30,6 +30,8 @@</div><div class='ctx'> </div><div class='ctx'> #define regATHUB_MISC_CNTL_V3_0_1			0x00d7</div><div class='ctx'> #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX		0</div><div class='add'>+#define regATHUB_MISC_CNTL_V3_3_0			0x00d8</div><div class='add'>+#define regATHUB_MISC_CNTL_V3_3_0_BASE_IDX		0</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)</div><div class='hunk'>@@ -40,6 +42,9 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)</div><div class='ctx'> 	case IP_VERSION(3, 0, 1):</div><div class='ctx'> 		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(3, 3, 0):</div><div class='add'>+		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -53,6 +58,9 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)</div><div class='ctx'> 	case IP_VERSION(3, 0, 1):</div><div class='ctx'> 		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);</div><div class='ctx'> 		break;</div><div class='add'>+	case IP_VERSION(3, 3, 0):</div><div class='add'>+		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c<br/>index 2c221000782c..a33e890c70d9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/atom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/atom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/atom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/atom.c</a></div><div class='hunk'>@@ -395,7 +395,6 @@ static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)</div><div class='ctx'> 			(*ptr)++;</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='del'>-		return;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c<br/>index 3ee219aa2891..7672abe6c140 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/atombios_encoders.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;acpi/video.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/amdgpu_drm.h&gt;</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_connectors.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c<br/>index bb666cb7522e..587ee632a3b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v10_0.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c<br/>index 7af277f61cca..f22ec27365bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v11_0.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c<br/>index 143efc37a17f..4dbe9b3259b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v6_0.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c<br/>index adeddfb7ff12..05bcce23385e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/dce_v8_0.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br/>index c8a3bf01743f..d63cab294883 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c</a></div><div class='hunk'>@@ -3996,16 +3996,13 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='ctx'> 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='del'>-		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='del'>-		/* don't check this.  There are apparently firmwares in the wild with</div><div class='del'>-		 * incorrect size in the header</div><div class='del'>-		 */</div><div class='del'>-		if (err == -ENODEV)</div><div class='del'>-			goto out;</div><div class='add'>+		err = request_firmware(&amp;adev-&gt;gfx.rlc_fw, fw_name, adev-&gt;dev);</div><div class='ctx'> 		if (err)</div><div class='del'>-			dev_dbg(adev-&gt;dev,</div><div class='del'>-				"gfx10: amdgpu_ucode_request() failed \"%s\"\n",</div><div class='del'>-				fw_name);</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		/* don't validate this firmware. There are apparently firmwares</div><div class='add'>+		 * in the wild with incorrect size in the header</div><div class='add'>+		 */</div><div class='ctx'> 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev-&gt;gfx.rlc_fw-&gt;data;</div><div class='ctx'> 		version_major = le16_to_cpu(rlc_hdr-&gt;header.header_version_major);</div><div class='ctx'> 		version_minor = le16_to_cpu(rlc_hdr-&gt;header.header_version_minor);</div><div class='hunk'>@@ -6593,7 +6590,8 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);</div><div class='ctx'> #endif</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,</div><div class='add'>+			    prop-&gt;allow_tunneling);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br/>index 0c6133cc5e57..0ea0866c261f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c</a></div><div class='hunk'>@@ -67,6 +67,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");</div><div class='add'>+MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");</div><div class='hunk'>@@ -89,6 +90,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");</div><div class='ctx'> MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");</div><div class='ctx'> </div><div class='add'>+static const struct soc15_reg_golden golden_settings_gc_11_0[] = {</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =</div><div class='ctx'> {</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),</div><div class='hunk'>@@ -110,7 +115,7 @@ static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188),</div><div class='del'>-	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x8000b007),</div><div class='add'>+	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x80009007),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000),</div><div class='ctx'> 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),</div><div class='hunk'>@@ -289,6 +294,9 @@ static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='add'>+	if (amdgpu_sriov_vf(adev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(11, 0, 1):</div><div class='ctx'> 	case IP_VERSION(11, 0, 4):</div><div class='hunk'>@@ -304,6 +312,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+	soc15_program_register_sequence(adev,</div><div class='add'>+					golden_settings_gc_11_0,</div><div class='add'>+					(const u32)ARRAY_SIZE(golden_settings_gc_11_0));</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,</div><div class='hunk'>@@ -419,7 +431,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 		adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='ctx'> 		cpu_ptr = &amp;adev-&gt;wb.wb[index];</div><div class='ctx'> </div><div class='del'>-		r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+		r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);</div><div class='ctx'> 			goto err1;</div><div class='hunk'>@@ -556,7 +568,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!amdgpu_sriov_vf(adev)) {</div><div class='del'>-		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='add'>+		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &amp;&amp;</div><div class='add'>+		    adev-&gt;pdev-&gt;revision == 0xCE)</div><div class='add'>+			snprintf(fw_name, sizeof(fw_name), "amdgpu/gc_11_0_0_rlc_1.bin");</div><div class='add'>+		else</div><div class='add'>+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);</div><div class='ctx'> 		err = amdgpu_ucode_request(adev, &amp;adev-&gt;gfx.rlc_fw, fw_name);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -3831,7 +3847,8 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,</div><div class='ctx'> 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);</div><div class='del'>-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);</div><div class='add'>+	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,</div><div class='add'>+			    prop-&gt;allow_tunneling);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);</div><div class='ctx'> 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);</div><div class='ctx'> 	mqd-&gt;cp_hqd_pq_control = tmp;</div><div class='hunk'>@@ -4457,11 +4474,43 @@ static int gfx_v11_0_wait_for_idle(void *handle)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,</div><div class='add'>+					     int req)</div><div class='add'>+{</div><div class='add'>+	u32 i, tmp, val;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='add'>+		/* Request with MeId=2, PipeId=0 */</div><div class='add'>+		tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);</div><div class='add'>+		tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);</div><div class='add'>+		WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp);</div><div class='add'>+</div><div class='add'>+		val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);</div><div class='add'>+		if (req) {</div><div class='add'>+			if (val == tmp)</div><div class='add'>+				break;</div><div class='add'>+		} else {</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,</div><div class='add'>+					    REQUEST, 1);</div><div class='add'>+</div><div class='add'>+			/* unlocked or locked by firmware */</div><div class='add'>+			if (val != tmp)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+		udelay(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= adev-&gt;usec_timeout)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> {</div><div class='ctx'> 	u32 grbm_soft_reset = 0;</div><div class='ctx'> 	u32 tmp;</div><div class='del'>-	int i, j, k;</div><div class='add'>+	int r, i, j, k;</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> </div><div class='ctx'> 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);</div><div class='hunk'>@@ -4501,6 +4550,13 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Try to acquire the gfx mutex before access to CP_VMID_RESET */</div><div class='add'>+	r = gfx_v11_0_request_gfx_index_mutex(adev, 1);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);</div><div class='ctx'> </div><div class='ctx'> 	// Read CP_VMID_RESET register three times.</div><div class='hunk'>@@ -4509,6 +4565,13 @@ static int gfx_v11_0_soft_reset(void *handle)</div><div class='ctx'> 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);</div><div class='ctx'> 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);</div><div class='ctx'> </div><div class='add'>+	/* release the gfx mutex */</div><div class='add'>+	r = gfx_v11_0_request_gfx_index_mutex(adev, 0);</div><div class='add'>+	if (r) {</div><div class='add'>+		DRM_ERROR("Failed to release the gfx mutex during soft reset\n");</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;usec_timeout; i++) {</div><div class='ctx'> 		if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &amp;&amp;</div><div class='ctx'> 		    !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))</div><div class='hunk'>@@ -6320,6 +6383,9 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,</div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;gfx.config.max_shader_engines; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; adev-&gt;gfx.config.max_sh_per_se; j++) {</div><div class='add'>+			bitmap = i * adev-&gt;gfx.config.max_sh_per_se + j;</div><div class='add'>+			if (!((gfx_v11_0_get_sa_active_bitmap(adev) &gt;&gt; bitmap) &amp; 1))</div><div class='add'>+				continue;</div><div class='ctx'> 			mask = 1;</div><div class='ctx'> 			counter = 0;</div><div class='ctx'> 			gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br/>index 885ebd703260..1943beb135c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c</a></div><div class='hunk'>@@ -883,8 +883,8 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='ctx'> 	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='del'>-	r = amdgpu_ib_get(adev, NULL, 16,</div><div class='del'>-					AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br/>index e3ff6e46f3f7..69c500910746 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</a></div><div class='hunk'>@@ -1039,8 +1039,8 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='ctx'> 	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='del'>-	r = amdgpu_ib_get(adev, NULL, 16,</div><div class='del'>-					AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c<br/>index 40d06d32bb74..131cddbdda0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c</a></div><div class='hunk'>@@ -297,8 +297,8 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)</div><div class='ctx'> 	gpu_addr = adev-&gt;wb.gpu_addr + (index * 4);</div><div class='ctx'> 	adev-&gt;wb.wb[index] = cpu_to_le32(0xCAFEDEAD);</div><div class='ctx'> 	memset(&amp;ib, 0, sizeof(ib));</div><div class='del'>-	r = amdgpu_ib_get(adev, NULL, 16,</div><div class='del'>-			  AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &amp;ib);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err1;</div><div class='ctx'> </div><div class='hunk'>@@ -3828,8 +3828,8 @@ static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,</div><div class='ctx'> 	/* the caller should make sure initialize value of</div><div class='ctx'> 	 * err_data-&gt;ue_count and err_data-&gt;ce_count</div><div class='ctx'> 	 */</div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -3882,150 +3882,6 @@ static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,</div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,</div><div class='del'>-					int xcc_id)</div><div class='del'>-{</div><div class='del'>-	uint32_t data;</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS);</div><div class='del'>-	if (data) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS);</div><div class='del'>-	if (data) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),</div><div class='del'>-				regVML2_WALKER_MEM_ECC_STATUS);</div><div class='del'>-	if (data) {</div><div class='del'>-		dev_warn(adev-&gt;dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS,</div><div class='del'>-				0x3);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev,</div><div class='del'>-					uint32_t status, int xcc_id)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_cu_info *cu_info = &amp;adev-&gt;gfx.cu_info;</div><div class='del'>-	uint32_t i, simd, wave;</div><div class='del'>-	uint32_t wave_status;</div><div class='del'>-	uint32_t wave_pc_lo, wave_pc_hi;</div><div class='del'>-	uint32_t wave_exec_lo, wave_exec_hi;</div><div class='del'>-	uint32_t wave_inst_dw0, wave_inst_dw1;</div><div class='del'>-	uint32_t wave_ib_sts;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 32; i++) {</div><div class='del'>-		if (!((i &lt;&lt; 1) &amp; status))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		simd = i / cu_info-&gt;max_waves_per_simd;</div><div class='del'>-		wave = i % cu_info-&gt;max_waves_per_simd;</div><div class='del'>-</div><div class='del'>-		wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);</div><div class='del'>-		wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);</div><div class='del'>-		wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);</div><div class='del'>-		wave_exec_lo =</div><div class='del'>-			wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);</div><div class='del'>-		wave_exec_hi =</div><div class='del'>-			wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);</div><div class='del'>-		wave_inst_dw0 =</div><div class='del'>-			wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);</div><div class='del'>-		wave_inst_dw1 =</div><div class='del'>-			wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);</div><div class='del'>-		wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);</div><div class='del'>-</div><div class='del'>-		dev_info(</div><div class='del'>-			adev-&gt;dev,</div><div class='del'>-			"\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",</div><div class='del'>-			simd, wave, wave_status,</div><div class='del'>-			((uint64_t)wave_pc_hi &lt;&lt; 32 | wave_pc_lo),</div><div class='del'>-			((uint64_t)wave_exec_hi &lt;&lt; 32 | wave_exec_lo),</div><div class='del'>-			((uint64_t)wave_inst_dw1 &lt;&lt; 32 | wave_inst_dw0),</div><div class='del'>-			wave_ib_sts);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,</div><div class='del'>-					int xcc_id)</div><div class='del'>-{</div><div class='del'>-	uint32_t se_idx, sh_idx, cu_idx;</div><div class='del'>-	uint32_t status;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-	for (se_idx = 0; se_idx &lt; adev-&gt;gfx.config.max_shader_engines; se_idx++) {</div><div class='del'>-		for (sh_idx = 0; sh_idx &lt; adev-&gt;gfx.config.max_sh_per_se; sh_idx++) {</div><div class='del'>-			for (cu_idx = 0; cu_idx &lt; adev-&gt;gfx.config.max_cu_per_sh; cu_idx++) {</div><div class='del'>-				gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,</div><div class='del'>-							cu_idx, xcc_id);</div><div class='del'>-				status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),</div><div class='del'>-						      regSQ_TIMEOUT_STATUS);</div><div class='del'>-				if (status != 0) {</div><div class='del'>-					dev_info(</div><div class='del'>-						adev-&gt;dev,</div><div class='del'>-						"GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",</div><div class='del'>-						se_idx, sh_idx, cu_idx);</div><div class='del'>-					gfx_v9_4_3_log_cu_timeout_status(</div><div class='del'>-						adev, status, xcc_id);</div><div class='del'>-				}</div><div class='del'>-				/* clear old status */</div><div class='del'>-				WREG32_SOC15(GC, GET_INST(GC, xcc_id),</div><div class='del'>-						regSQ_TIMEOUT_STATUS, 0);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,</div><div class='del'>-			xcc_id);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,</div><div class='del'>-					void *ras_error_status, int xcc_id)</div><div class='del'>-{</div><div class='del'>-	gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);</div><div class='del'>-	gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,</div><div class='del'>-					int xcc_id)</div><div class='del'>-{</div><div class='del'>-	WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);</div><div class='del'>-	WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);</div><div class='del'>-	WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,</div><div class='del'>-					int xcc_id)</div><div class='del'>-{</div><div class='del'>-	uint32_t se_idx, sh_idx, cu_idx;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-	for (se_idx = 0; se_idx &lt; adev-&gt;gfx.config.max_shader_engines; se_idx++) {</div><div class='del'>-		for (sh_idx = 0; sh_idx &lt; adev-&gt;gfx.config.max_sh_per_se; sh_idx++) {</div><div class='del'>-			for (cu_idx = 0; cu_idx &lt; adev-&gt;gfx.config.max_cu_per_sh; cu_idx++) {</div><div class='del'>-				gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,</div><div class='del'>-							cu_idx, xcc_id);</div><div class='del'>-				WREG32_SOC15(GC, GET_INST(GC, xcc_id),</div><div class='del'>-						regSQ_TIMEOUT_STATUS, 0);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,</div><div class='del'>-			xcc_id);</div><div class='del'>-	mutex_unlock(&amp;adev-&gt;grbm_idx_mutex);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,</div><div class='del'>-					void *ras_error_status, int xcc_id)</div><div class='del'>-{</div><div class='del'>-	gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);</div><div class='del'>-	gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev,</div><div class='ctx'> 					void *ras_error_status, int xcc_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -4067,16 +3923,6 @@ static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)</div><div class='ctx'> 	amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev)</div><div class='del'>-{</div><div class='del'>-	amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);</div><div class='hunk'>@@ -4394,8 +4240,6 @@ struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {</div><div class='ctx'> struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {</div><div class='ctx'> 	.query_ras_error_count = &amp;gfx_v9_4_3_query_ras_error_count,</div><div class='ctx'> 	.reset_ras_error_count = &amp;gfx_v9_4_3_reset_ras_error_count,</div><div class='del'>-	.query_ras_error_status = &amp;gfx_v9_4_3_query_ras_error_status,</div><div class='del'>-	.reset_ras_error_status = &amp;gfx_v9_4_3_reset_ras_error_status,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amdgpu_gfx_ras gfx_v9_4_3_ras = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c<br/>index 53a2ba5fcf4b..22175da0e16a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c</a></div><div class='hunk'>@@ -102,7 +102,9 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='ctx'> 			min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='ctx'> </div><div class='del'>-		if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+		if (adev-&gt;apu_flags &amp; (AMD_APU_IS_RAVEN2 |</div><div class='add'>+				       AMD_APU_IS_RENOIR |</div><div class='add'>+				       AMD_APU_IS_GREEN_SARDINE))</div><div class='ctx'> 		       /*</div><div class='ctx'> 			* Raven2 has a HW issue that it is unable to use the</div><div class='ctx'> 			* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c<br/>index 55423ff1bb49..49aecdcee006 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c</a></div><div class='hunk'>@@ -139,7 +139,9 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev,</div><div class='ctx'> 			WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='ctx'> 				min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='ctx'> </div><div class='del'>-			if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+			if (adev-&gt;apu_flags &amp; (AMD_APU_IS_RAVEN2 |</div><div class='add'>+					       AMD_APU_IS_RENOIR |</div><div class='add'>+					       AMD_APU_IS_GREEN_SARDINE))</div><div class='ctx'> 			       /*</div><div class='ctx'> 				* Raven2 has a HW issue that it is unable to use the</div><div class='ctx'> 				* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.</div><div class='hunk'>@@ -454,10 +456,12 @@ static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev,</div><div class='ctx'> 		WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);</div><div class='ctx'> </div><div class='ctx'> 		/* Setup L2 cache */</div><div class='del'>-		tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);</div><div class='del'>-		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);</div><div class='del'>-		WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);</div><div class='add'>+		if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+			tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);</div><div class='add'>+			tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);</div><div class='add'>+			WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);</div><div class='add'>+			WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br/>index a5a05c16c10d..6c5185608854 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c</a></div><div class='hunk'>@@ -1041,6 +1041,10 @@ static int gmc_v10_0_hw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='add'>+		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c<br/>index 23d7b548d13f..c9c653cfc765 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c</a></div><div class='hunk'>@@ -941,6 +941,11 @@ static int gmc_v11_0_hw_fini(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='add'>+		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+</div><div class='ctx'> 	gmc_v11_0_gart_disable(adev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br/>index 2ac5820e9c92..f9039d64ff2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c</a></div><div class='hunk'>@@ -883,7 +883,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,</div><div class='ctx'> 	 * GRBM interface.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if ((vmhub == AMDGPU_GFXHUB(0)) &amp;&amp;</div><div class='del'>-	    (adev-&gt;ip_versions[GC_HWIP][0] &lt; IP_VERSION(9, 4, 2)))</div><div class='add'>+	    (amdgpu_ip_version(adev, GC_HWIP, 0) &lt; IP_VERSION(9, 4, 2)))</div><div class='ctx'> 		RREG32_NO_KIQ(req);</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adev-&gt;usec_timeout; j++) {</div><div class='hunk'>@@ -2380,6 +2380,10 @@ static int gmc_v9_0_hw_fini(void *handle)</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_irq_put(adev, &amp;adev-&gt;gmc.vm_fault, 0);</div><div class='ctx'> </div><div class='add'>+	if (adev-&gt;gmc.ecc_irq.funcs &amp;&amp;</div><div class='add'>+		amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))</div><div class='add'>+		amdgpu_irq_put(adev, &amp;adev-&gt;gmc.ecc_irq, 0);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br/>index 49e934975719..4db6bb73ead4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c</a></div><div class='hunk'>@@ -129,6 +129,11 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,</div><div class='ctx'> {</div><div class='ctx'> 	int data;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {</div><div class='add'>+		/* Default enabled */</div><div class='add'>+		*flags |= AMD_CG_SUPPORT_HDP_MGCG;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> 	/* AMD_CG_SUPPORT_HDP_LS */</div><div class='ctx'> 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));</div><div class='ctx'> 	if (data &amp; HDP_MEM_POWER_LS__LS_ENABLE_MASK)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c<br/>index 9df011323d4b..6ede85b28cc8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c</a></div><div class='hunk'>@@ -155,13 +155,6 @@ static int jpeg_v4_0_5_hw_init(void *handle)</div><div class='ctx'> 	struct amdgpu_ring *ring = adev-&gt;jpeg.inst-&gt;ring_dec;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='del'>-				(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1), 0);</div><div class='del'>-</div><div class='del'>-	WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,</div><div class='del'>-		ring-&gt;doorbell_index &lt;&lt; VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='del'>-		VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='del'>-</div><div class='ctx'> 	r = amdgpu_ring_test_helper(ring);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -336,6 +329,14 @@ static int jpeg_v4_0_5_start(struct amdgpu_device *adev)</div><div class='ctx'> 	if (adev-&gt;pm.dpm_enabled)</div><div class='ctx'> 		amdgpu_dpm_enable_jpeg(adev, true);</div><div class='ctx'> </div><div class='add'>+	/* doorbell programming is done for every playback */</div><div class='add'>+	adev-&gt;nbio.funcs-&gt;vcn_doorbell_range(adev, ring-&gt;use_doorbell,</div><div class='add'>+				(adev-&gt;doorbell_index.vcn.vcn_ring0_1 &lt;&lt; 1), 0);</div><div class='add'>+</div><div class='add'>+	WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,</div><div class='add'>+		ring-&gt;doorbell_index &lt;&lt; VCN_JPEG_DB_CTRL__OFFSET__SHIFT |</div><div class='add'>+		VCN_JPEG_DB_CTRL__EN_MASK);</div><div class='add'>+</div><div class='ctx'> 	/* disable power gating */</div><div class='ctx'> 	r = jpeg_v4_0_5_disable_static_power_gating(adev);</div><div class='ctx'> 	if (r)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c<br/>index 4dfec56e1b7f..26d71a22395d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mes_v11_0.c</a></div><div class='hunk'>@@ -408,6 +408,8 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)</div><div class='ctx'> 	mes_set_hw_res_pkt.enable_reg_active_poll = 1;</div><div class='ctx'> 	mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;</div><div class='ctx'> 	mes_set_hw_res_pkt.oversubscription_timer = 50;</div><div class='add'>+	mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;</div><div class='add'>+	mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes-&gt;event_log_gpu_addr;</div><div class='ctx'> </div><div class='ctx'> 	return mes_v11_0_submit_pkt_and_poll_completion(mes,</div><div class='ctx'> 			&amp;mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br/>index 843219a91736..e3ddd22aa172 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c</a></div><div class='hunk'>@@ -96,7 +96,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)</div><div class='ctx'> 	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,</div><div class='ctx'> 		     min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18);</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+	if (adev-&gt;apu_flags &amp; (AMD_APU_IS_RAVEN2 |</div><div class='add'>+			       AMD_APU_IS_RENOIR |</div><div class='add'>+			       AMD_APU_IS_GREEN_SARDINE))</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Raven2 has a HW issue that it is unable to use the vram which</div><div class='ctx'> 		 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c<br/>index 9b0146732e13..fb53aacdcba2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c</a></div><div class='hunk'>@@ -652,8 +652,8 @@ static void mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,</div><div class='ctx'> 					&amp;ue_count);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mmhub_v1_8_query_ras_error_count(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c<br/>index 676ab1d20d2f..1f52b4b1db03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c</a></div><div class='hunk'>@@ -259,17 +259,17 @@ const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = {</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_11_init_registers(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='del'>-/*	uint32_t def, data;</div><div class='add'>+	uint32_t def, data;</div><div class='add'>+</div><div class='add'>+	def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);</div><div class='add'>+	data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,</div><div class='add'>+				CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);</div><div class='add'>+	data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,</div><div class='add'>+				CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);</div><div class='ctx'> </div><div class='del'>-		def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);</div><div class='del'>-		data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,</div><div class='del'>-			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);</div><div class='del'>-		data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,</div><div class='del'>-			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);</div><div class='add'>+	if (def != data)</div><div class='add'>+		WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);</div><div class='ctx'> </div><div class='del'>-		if (def != data)</div><div class='del'>-			WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);</div><div class='del'>-*/</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c<br/>index 6d24c84924cb..19986ff6a48d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c</a></div><div class='hunk'>@@ -401,8 +401,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device</div><div class='ctx'> </div><div class='ctx'> 			if (err_data.ce_count)</div><div class='ctx'> 				dev_info(adev-&gt;dev, "%ld correctable hardware "</div><div class='del'>-						"errors detected in %s block, "</div><div class='del'>-						"no user action is needed.\n",</div><div class='add'>+						"errors detected in %s block\n",</div><div class='ctx'> 						obj-&gt;err_data.ce_count,</div><div class='ctx'> 						get_ras_block_str(adev-&gt;nbio.ras_if));</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c<br/>index 23f26f8caad4..e90f33780803 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c</a></div><div class='hunk'>@@ -597,8 +597,7 @@ static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device</div><div class='ctx'> </div><div class='ctx'> 			if (err_data.ce_count)</div><div class='ctx'> 				dev_info(adev-&gt;dev, "%ld correctable hardware "</div><div class='del'>-						"errors detected in %s block, "</div><div class='del'>-						"no user action is needed.\n",</div><div class='add'>+						"errors detected in %s block\n",</div><div class='ctx'> 						obj-&gt;err_data.ce_count,</div><div class='ctx'> 						get_ras_block_str(adev-&gt;nbio.ras_if));</div><div class='ctx'> </div><div class='hunk'>@@ -611,11 +610,6 @@ static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device</div><div class='ctx'> </div><div class='ctx'> 		dev_info(adev-&gt;dev, "RAS controller interrupt triggered "</div><div class='ctx'> 					"by NBIF error\n");</div><div class='del'>-</div><div class='del'>-		/* ras_controller_int is dedicated for nbif ras error,</div><div class='del'>-		 * not the global interrupt for sync flood</div><div class='del'>-		 */</div><div class='del'>-		amdgpu_ras_reset_gpu(adev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	amdgpu_ras_error_data_fini(&amp;err_data);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c<br/>index 3cf4684d0d3f..df1844d0800f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/psp_v13_0.c</a></div><div class='hunk'>@@ -60,7 +60,7 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");</div><div class='ctx'> #define GFX_CMD_USB_PD_USE_LFB 0x480</div><div class='ctx'> </div><div class='ctx'> /* Retry times for vmbx ready wait */</div><div class='del'>-#define PSP_VMBX_POLLING_LIMIT 20000</div><div class='add'>+#define PSP_VMBX_POLLING_LIMIT 3000</div><div class='ctx'> </div><div class='ctx'> /* VBIOS gfl defines */</div><div class='ctx'> #define MBOX_READY_MASK 0x80000000</div><div class='hunk'>@@ -161,14 +161,18 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)</div><div class='ctx'> static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = psp-&gt;adev;</div><div class='del'>-	int retry_loop, ret;</div><div class='add'>+	int retry_loop, retry_cnt, ret;</div><div class='ctx'> </div><div class='add'>+	retry_cnt =</div><div class='add'>+		(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?</div><div class='add'>+			PSP_VMBX_POLLING_LIMIT :</div><div class='add'>+			10;</div><div class='ctx'> 	/* Wait for bootloader to signify that it is ready having bit 31 of</div><div class='ctx'> 	 * C2PMSG_35 set to 1. All other bits are expected to be cleared.</div><div class='ctx'> 	 * If there is an error in processing command, bits[7:0] will be set.</div><div class='ctx'> 	 * This is applicable for PSP v13.0.6 and newer.</div><div class='ctx'> 	 */</div><div class='del'>-	for (retry_loop = 0; retry_loop &lt; PSP_VMBX_POLLING_LIMIT; retry_loop++) {</div><div class='add'>+	for (retry_loop = 0; retry_loop &lt; retry_cnt; retry_loop++) {</div><div class='ctx'> 		ret = psp_wait_for(</div><div class='ctx'> 			psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),</div><div class='ctx'> 			0x80000000, 0xffffffff, false);</div><div class='hunk'>@@ -821,7 +825,7 @@ static int psp_v13_0_query_boot_status(struct psp_context *psp)</div><div class='ctx'> 	if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) &lt; 0x00a10007)</div><div class='add'>+	if (RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_59) &lt; 0x00a10109)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for_each_inst(i, inst_mask) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c<br/>index 45377a175250..8d5d86675a7f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c</a></div><div class='hunk'>@@ -813,12 +813,12 @@ static int sdma_v2_4_early_init(void *handle)</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	adev-&gt;sdma.num_instances = SDMA_MAX_INSTANCE;</div><div class='add'>+</div><div class='ctx'> 	r = sdma_v2_4_init_microcode(adev);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;sdma.num_instances = SDMA_MAX_INSTANCE;</div><div class='del'>-</div><div class='ctx'> 	sdma_v2_4_set_ring_funcs(adev);</div><div class='ctx'> 	sdma_v2_4_set_buffer_funcs(adev);</div><div class='ctx'> 	sdma_v2_4_set_vm_pte_funcs(adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c<br/>index 0f24af6f2810..2d688dca26be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c</a></div><div class='hunk'>@@ -2156,7 +2156,7 @@ static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,</div><div class='ctx'> 					&amp;ue_count);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br/>index 83c240f741b5..0058f3f7cf6e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c</a></div><div class='hunk'>@@ -1643,6 +1643,32 @@ static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 		*flags |= AMD_CG_SUPPORT_SDMA_LS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* SDMA 5.2.3 (RMB) FW doesn't seem to properly</div><div class='add'>+	 * disallow GFXOFF in some cases leading to</div><div class='add'>+	 * hangs in SDMA.  Disallow GFXOFF while SDMA is active.</div><div class='add'>+	 * We can probably just limit this to 5.2.3,</div><div class='add'>+	 * but it shouldn't hurt for other parts since</div><div class='add'>+	 * this GFXOFF will be disallowed anyway when SDMA is</div><div class='add'>+	 * active, this just makes it explicit.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = ring-&gt;adev;</div><div class='add'>+</div><div class='add'>+	/* SDMA 5.2.3 (RMB) FW doesn't seem to properly</div><div class='add'>+	 * disallow GFXOFF in some cases leading to</div><div class='add'>+	 * hangs in SDMA.  Allow GFXOFF when SDMA is complete.</div><div class='add'>+	 */</div><div class='add'>+	amdgpu_gfx_off_ctrl(adev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct amd_ip_funcs sdma_v5_2_ip_funcs = {</div><div class='ctx'> 	.name = "sdma_v5_2",</div><div class='ctx'> 	.early_init = sdma_v5_2_early_init,</div><div class='hunk'>@@ -1690,6 +1716,8 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {</div><div class='ctx'> 	.test_ib = sdma_v5_2_ring_test_ib,</div><div class='ctx'> 	.insert_nop = sdma_v5_2_ring_insert_nop,</div><div class='ctx'> 	.pad_ib = sdma_v5_2_ring_pad_ib,</div><div class='add'>+	.begin_use = sdma_v5_2_ring_begin_use,</div><div class='add'>+	.end_use = sdma_v5_2_ring_end_use,</div><div class='ctx'> 	.emit_wreg = sdma_v5_2_ring_emit_wreg,</div><div class='ctx'> 	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,</div><div class='ctx'> 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c<br/>index d4b8d62f4294..15033efec2ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/soc15.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/soc15.c</a></div><div class='hunk'>@@ -902,6 +902,7 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =</div><div class='ctx'> 	.pre_asic_init = &amp;soc15_pre_asic_init,</div><div class='ctx'> 	.query_video_codecs = &amp;soc15_query_video_codecs,</div><div class='ctx'> 	.encode_ext_smn_addressing = &amp;aqua_vanjaram_encode_ext_smn_addressing,</div><div class='add'>+	.get_reg_state = &amp;aqua_vanjaram_get_reg_state,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int soc15_common_early_init(void *handle)</div><div class='hunk'>@@ -1161,6 +1162,11 @@ static int soc15_common_early_init(void *handle)</div><div class='ctx'> 			AMD_PG_SUPPORT_VCN_DPG |</div><div class='ctx'> 			AMD_PG_SUPPORT_JPEG;</div><div class='ctx'> 		adev-&gt;external_rev_id = adev-&gt;rev_id + 0x46;</div><div class='add'>+		/* GC 9.4.3 uses MMIO register region hole at a different offset */</div><div class='add'>+		if (!amdgpu_sriov_vf(adev)) {</div><div class='add'>+			adev-&gt;rmmio_remap.reg_offset = 0x1A000;</div><div class='add'>+			adev-&gt;rmmio_remap.bus_addr = adev-&gt;rmmio_base + 0x1A000;</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* FIXME: not supported yet */</div><div class='hunk'>@@ -1418,11 +1424,14 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 	if (amdgpu_sriov_vf(adev))</div><div class='ctx'> 		*flags = 0;</div><div class='ctx'> </div><div class='del'>-	adev-&gt;nbio.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='add'>+	if (adev-&gt;nbio.funcs &amp;&amp; adev-&gt;nbio.funcs-&gt;get_clockgating_state)</div><div class='add'>+		adev-&gt;nbio.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;hdp.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='add'>+	if (adev-&gt;hdp.funcs &amp;&amp; adev-&gt;hdp.funcs-&gt;get_clock_gating_state)</div><div class='add'>+		adev-&gt;hdp.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) {</div><div class='add'>+	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &amp;&amp;</div><div class='add'>+	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {</div><div class='ctx'> 		/* AMD_CG_SUPPORT_DRM_MGCG */</div><div class='ctx'> 		data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));</div><div class='ctx'> 		if (!(data &amp; 0x01000000))</div><div class='hunk'>@@ -1435,9 +1444,11 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* AMD_CG_SUPPORT_ROM_MGCG */</div><div class='del'>-	adev-&gt;smuio.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='add'>+	if (adev-&gt;smuio.funcs &amp;&amp; adev-&gt;smuio.funcs-&gt;get_clock_gating_state)</div><div class='add'>+		adev-&gt;smuio.funcs-&gt;get_clock_gating_state(adev, flags);</div><div class='ctx'> </div><div class='del'>-	adev-&gt;df.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='add'>+	if (adev-&gt;df.funcs &amp;&amp; adev-&gt;df.funcs-&gt;get_clockgating_state)</div><div class='add'>+		adev-&gt;df.funcs-&gt;get_clockgating_state(adev, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int soc15_common_set_powergating_state(void *handle,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h<br/>index eac54042c6c0..1444b7765e4b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/soc15.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/soc15.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/soc15.h</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #include "nbio_v6_1.h"</div><div class='ctx'> #include "nbio_v7_0.h"</div><div class='ctx'> #include "nbio_v7_4.h"</div><div class='add'>+#include "amdgpu_reg_state.h"</div><div class='ctx'> </div><div class='ctx'> extern const struct amdgpu_ip_block_version vega10_common_ip_block;</div><div class='ctx'> </div><div class='hunk'>@@ -114,6 +115,9 @@ int aldebaran_reg_base_init(struct amdgpu_device *adev);</div><div class='ctx'> void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);</div><div class='ctx'> u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);</div><div class='ctx'> int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);</div><div class='add'>+ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,</div><div class='add'>+				    enum amdgpu_reg_state reg_state, void *buf,</div><div class='add'>+				    size_t max_size);</div><div class='ctx'> </div><div class='ctx'> void vega10_doorbell_index_init(struct amdgpu_device *adev);</div><div class='ctx'> void vega20_doorbell_index_init(struct amdgpu_device *adev);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c<br/>index e9c2ff74f0bc..7458a218e89d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "umc/umc_12_0_0_offset.h"</div><div class='ctx'> #include "umc/umc_12_0_0_sh_mask.h"</div><div class='add'>+#include "mp/mp_13_0_6_sh_mask.h"</div><div class='ctx'> </div><div class='ctx'> const uint32_t</div><div class='ctx'> 	umc_v12_0_channel_idx_tbl[]</div><div class='hunk'>@@ -88,16 +89,26 @@ static void umc_v12_0_reset_error_count(struct amdgpu_device *adev)</div><div class='ctx'> 		umc_v12_0_reset_error_count_per_channel, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status)</div><div class='add'>+bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)</div><div class='ctx'> {</div><div class='add'>+	if (amdgpu_ras_is_poison_mode_supported(adev) &amp;&amp;</div><div class='add'>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &amp;&amp;</div><div class='add'>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &amp;&amp;</div><div class='ctx'> 		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||</div><div class='ctx'> 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||</div><div class='ctx'> 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status)</div><div class='add'>+bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)</div><div class='ctx'> {</div><div class='add'>+	if (amdgpu_ras_is_poison_mode_supported(adev) &amp;&amp;</div><div class='add'>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &amp;&amp;</div><div class='add'>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &amp;&amp;</div><div class='ctx'> 		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 ||</div><div class='ctx'> 		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 &amp;&amp;</div><div class='hunk'>@@ -105,7 +116,7 @@ bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status)</div><div class='ctx'> 		/* Identify data parity error in replay mode */</div><div class='ctx'> 		((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 ||</div><div class='ctx'> 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) &amp;&amp;</div><div class='del'>-		!(umc_v12_0_is_uncorrectable_error(mc_umc_status)))));</div><div class='add'>+		!(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)))));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev,</div><div class='hunk'>@@ -124,7 +135,7 @@ static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 	mc_umc_status =</div><div class='ctx'> 		RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);</div><div class='ctx'> </div><div class='del'>-	if (umc_v12_0_is_correctable_error(mc_umc_status))</div><div class='add'>+	if (umc_v12_0_is_correctable_error(adev, mc_umc_status))</div><div class='ctx'> 		*error_count += 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -142,7 +153,7 @@ static void umc_v12_0_query_uncorrectable_error_count(struct amdgpu_device *adev</div><div class='ctx'> 	mc_umc_status =</div><div class='ctx'> 		RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4);</div><div class='ctx'> </div><div class='del'>-	if (umc_v12_0_is_uncorrectable_error(mc_umc_status))</div><div class='add'>+	if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))</div><div class='ctx'> 		*error_count += 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -166,8 +177,8 @@ static int umc_v12_0_query_error_count(struct amdgpu_device *adev,</div><div class='ctx'> 	umc_v12_0_query_correctable_error_count(adev, umc_reg_offset, &amp;ce_count);</div><div class='ctx'> 	umc_v12_0_query_uncorrectable_error_count(adev, umc_reg_offset, &amp;ue_count);</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, ue_count);</div><div class='del'>-	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, ce_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ue_count(err_data, &amp;mcm_info, NULL, ue_count);</div><div class='add'>+	amdgpu_ras_error_statistic_ce_count(err_data, &amp;mcm_info, NULL, ce_count);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -360,6 +371,59 @@ static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void umc_v12_0_ecc_info_query_ras_error_count(struct amdgpu_device *adev,</div><div class='add'>+					void *ras_error_status)</div><div class='add'>+{</div><div class='add'>+	amdgpu_mca_smu_log_ras_error(adev,</div><div class='add'>+		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_CE, ras_error_status);</div><div class='add'>+	amdgpu_mca_smu_log_ras_error(adev,</div><div class='add'>+		AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_UE, ras_error_status);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *adev,</div><div class='add'>+					void *ras_error_status)</div><div class='add'>+{</div><div class='add'>+	struct ras_err_node *err_node;</div><div class='add'>+	uint64_t mc_umc_status;</div><div class='add'>+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;</div><div class='add'>+</div><div class='add'>+	for_each_ras_error(err_node, err_data) {</div><div class='add'>+		mc_umc_status = err_node-&gt;err_info.err_addr.err_status;</div><div class='add'>+		if (!mc_umc_status)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) {</div><div class='add'>+			uint64_t mca_addr, err_addr, mca_ipid;</div><div class='add'>+			uint32_t InstanceIdLo;</div><div class='add'>+			struct amdgpu_smuio_mcm_config_info *mcm_info;</div><div class='add'>+</div><div class='add'>+			mcm_info = &amp;err_node-&gt;err_info.mcm_info;</div><div class='add'>+			mca_addr = err_node-&gt;err_info.err_addr.err_addr;</div><div class='add'>+			mca_ipid = err_node-&gt;err_info.err_addr.err_ipid;</div><div class='add'>+</div><div class='add'>+			err_addr =  REG_GET_FIELD(mca_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);</div><div class='add'>+			InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo);</div><div class='add'>+</div><div class='add'>+			dev_info(adev-&gt;dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n",</div><div class='add'>+				mca_ipid,</div><div class='add'>+				mcm_info-&gt;die_id,</div><div class='add'>+				MCA_IPID_LO_2_UMC_INST(InstanceIdLo),</div><div class='add'>+				MCA_IPID_LO_2_UMC_CH(InstanceIdLo),</div><div class='add'>+				err_addr);</div><div class='add'>+</div><div class='add'>+			umc_v12_0_convert_error_address(adev,</div><div class='add'>+				err_data, err_addr,</div><div class='add'>+				MCA_IPID_LO_2_UMC_CH(InstanceIdLo),</div><div class='add'>+				MCA_IPID_LO_2_UMC_INST(InstanceIdLo),</div><div class='add'>+				mcm_info-&gt;die_id);</div><div class='add'>+</div><div class='add'>+			/* Clear umc error address content */</div><div class='add'>+			memset(&amp;err_node-&gt;err_info.err_addr,</div><div class='add'>+				0, sizeof(err_node-&gt;err_info.err_addr));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	amdgpu_umc_loop_channels(adev,</div><div class='hunk'>@@ -386,4 +450,6 @@ struct amdgpu_umc_ras umc_v12_0_ras = {</div><div class='ctx'> 	},</div><div class='ctx'> 	.err_cnt_init = umc_v12_0_err_cnt_init,</div><div class='ctx'> 	.query_ras_poison_mode = umc_v12_0_query_ras_poison_mode,</div><div class='add'>+	.ecc_info_query_ras_error_count = umc_v12_0_ecc_info_query_ras_error_count,</div><div class='add'>+	.ecc_info_query_ras_error_address = umc_v12_0_ecc_info_query_ras_error_address,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h<br/>index b34b1e358f8b..e8de3a92251a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v12_0.h</a></div><div class='hunk'>@@ -117,8 +117,12 @@</div><div class='ctx'> 		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) &lt;&lt; UMC_V12_0_PA_CH6_BIT); \</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='del'>-bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status);</div><div class='del'>-bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status);</div><div class='add'>+#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) &gt;&gt; 20) &amp; 0x1) * 4) + \</div><div class='add'>+			(((_ipid_lo) &gt;&gt; 12) &amp; 0xF))</div><div class='add'>+#define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) &gt;&gt; 21) &amp; 0x7)</div><div class='add'>+</div><div class='add'>+bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='add'>+bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);</div><div class='ctx'> </div><div class='ctx'> extern const uint32_t</div><div class='ctx'> 	umc_v12_0_channel_idx_tbl[]</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c<br/>index 530549314ce4..a3ee3c4c650f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/umc_v6_7.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/umc_v6_7.c</a></div><div class='hunk'>@@ -64,7 +64,7 @@ static void umc_v6_7_query_error_status_helper(struct amdgpu_device *adev,</div><div class='ctx'> 	uint64_t reg_value;</div><div class='ctx'> </div><div class='ctx'> 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)</div><div class='del'>-		dev_info(adev-&gt;dev, "Deferred error, no user action is needed.\n");</div><div class='add'>+		dev_info(adev-&gt;dev, "Deferred error\n");</div><div class='ctx'> </div><div class='ctx'> 	if (mc_umc_status)</div><div class='ctx'> 		dev_info(adev-&gt;dev, "MCA STATUS 0x%llx, umc_reg_offset 0x%x\n", mc_umc_status, umc_reg_offset);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c<br/>index 48bfcd0d558b..169ed400ee7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c</a></div><div class='hunk'>@@ -100,6 +100,31 @@ static int vcn_v4_0_early_init(void *handle)</div><div class='ctx'> 	return amdgpu_vcn_early_init(adev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)</div><div class='add'>+{</div><div class='add'>+	volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='add'>+</div><div class='add'>+	fw_shared = adev-&gt;vcn.inst[inst_idx].fw_shared.cpu_addr;</div><div class='add'>+	fw_shared-&gt;present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='add'>+	fw_shared-&gt;sq.is_enabled = 1;</div><div class='add'>+</div><div class='add'>+	fw_shared-&gt;present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);</div><div class='add'>+	fw_shared-&gt;smu_dpm_interface.smu_interface_type = (adev-&gt;flags &amp; AMD_IS_APU) ?</div><div class='add'>+		AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==</div><div class='add'>+	    IP_VERSION(4, 0, 2)) {</div><div class='add'>+		fw_shared-&gt;present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;</div><div class='add'>+		fw_shared-&gt;drm_key_wa.method =</div><div class='add'>+			AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (amdgpu_vcnfw_log)</div><div class='add'>+		amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[inst_idx]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * vcn_v4_0_sw_init - sw init for VCN block</div><div class='ctx'>  *</div><div class='hunk'>@@ -124,8 +149,6 @@ static int vcn_v4_0_sw_init(void *handle)</div><div class='ctx'> 		return r;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; i++) {</div><div class='del'>-		volatile struct amdgpu_vcn4_fw_shared *fw_shared;</div><div class='del'>-</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -161,23 +184,7 @@ static int vcn_v4_0_sw_init(void *handle)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> </div><div class='del'>-		fw_shared = adev-&gt;vcn.inst[i].fw_shared.cpu_addr;</div><div class='del'>-		fw_shared-&gt;present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);</div><div class='del'>-		fw_shared-&gt;sq.is_enabled = 1;</div><div class='del'>-</div><div class='del'>-		fw_shared-&gt;present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);</div><div class='del'>-		fw_shared-&gt;smu_dpm_interface.smu_interface_type = (adev-&gt;flags &amp; AMD_IS_APU) ?</div><div class='del'>-			AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;</div><div class='del'>-</div><div class='del'>-		if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==</div><div class='del'>-		    IP_VERSION(4, 0, 2)) {</div><div class='del'>-			fw_shared-&gt;present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT;</div><div class='del'>-			fw_shared-&gt;drm_key_wa.method =</div><div class='del'>-				AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (amdgpu_vcnfw_log)</div><div class='del'>-			amdgpu_vcn_fwlog_init(&amp;adev-&gt;vcn.inst[i]);</div><div class='add'>+		vcn_v4_0_fw_shared_init(adev, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_sriov_vf(adev)) {</div><div class='hunk'>@@ -1273,6 +1280,9 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)</div><div class='ctx'> 		if (adev-&gt;vcn.harvest_config &amp; (1 &lt;&lt; i))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		// Must re/init fw_shared at beginning</div><div class='add'>+		vcn_v4_0_fw_shared_init(adev, i);</div><div class='add'>+</div><div class='ctx'> 		table_size = 0;</div><div class='ctx'> </div><div class='ctx'> 		MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c b/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c<br/>index 174f13eff575..d20060a51e05 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c</a></div><div class='hunk'>@@ -96,6 +96,10 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> 		adev-&gt;vpe.cmdbuf_cpu_addr[1] = f32_cntl;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_vpe_psp_update_sram(adev);</div><div class='add'>+</div><div class='add'>+		/* Config DPM */</div><div class='add'>+		amdgpu_vpe_configure_dpm(vpe);</div><div class='add'>+</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -128,6 +132,8 @@ static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vpe_v6_1_halt(vpe, false);</div><div class='add'>+	/* Config DPM */</div><div class='add'>+	amdgpu_vpe_configure_dpm(vpe);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -264,6 +270,15 @@ static int vpe_v6_1_set_regs(struct amdgpu_vpe *vpe)</div><div class='ctx'> 	vpe-&gt;regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;</div><div class='ctx'> 	vpe-&gt;regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;</div><div class='ctx'> </div><div class='add'>+	vpe-&gt;regs.dpm_enable = regVPEC_PUB_DUMMY2;</div><div class='add'>+	vpe-&gt;regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;</div><div class='add'>+	vpe-&gt;regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;</div><div class='add'>+	vpe-&gt;regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;</div><div class='add'>+	vpe-&gt;regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;</div><div class='add'>+	vpe-&gt;regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;</div><div class='add'>+	vpe-&gt;regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;</div><div class='add'>+	vpe-&gt;regs.context_indicator = regVPEC_QUEUE6_DUMMY3;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h<br/>index d7cd5fa313ff..df75863393fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h</a></div><div class='hunk'>@@ -2069,7 +2069,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='del'>-	0xbf820001, 0xbf820220,</div><div class='add'>+	0xbf820001, 0xbf820221,</div><div class='ctx'> 	0xb0804004, 0xb978f802,</div><div class='ctx'> 	0x8a78ff78, 0x00020006,</div><div class='ctx'> 	0xb97bf803, 0x876eff78,</div><div class='hunk'>@@ -2118,391 +2118,391 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {</div><div class='ctx'> 	0xbf900004, 0xbf8cc07f,</div><div class='ctx'> 	0x877aff7f, 0x04000000,</div><div class='ctx'> 	0x8f7a857a, 0x886d7a6d,</div><div class='del'>-	0xbefa037e, 0x877bff7f,</div><div class='del'>-	0x0000ffff, 0xbefe03c1,</div><div class='del'>-	0xbeff03c1, 0xdc5f8000,</div><div class='del'>-	0x007a0000, 0x7e000280,</div><div class='del'>-	0xbefe037a, 0xbeff037b,</div><div class='del'>-	0xb97b02dc, 0x8f7b997b,</div><div class='del'>-	0xb97a3a05, 0x807a817a,</div><div class='del'>-	0xbf0d997b, 0xbf850002,</div><div class='del'>-	0x8f7a897a, 0xbf820001,</div><div class='del'>-	0x8f7a8a7a, 0xb97b1e06,</div><div class='del'>-	0x8f7b8a7b, 0x807a7b7a,</div><div class='add'>+	0x7e008200, 0xbefa037e,</div><div class='ctx'> 	0x877bff7f, 0x0000ffff,</div><div class='del'>-	0x807aff7a, 0x00000200,</div><div class='del'>-	0x807a7e7a, 0x827b807b,</div><div class='del'>-	0xd7610000, 0x00010870,</div><div class='del'>-	0xd7610000, 0x00010a71,</div><div class='del'>-	0xd7610000, 0x00010c72,</div><div class='del'>-	0xd7610000, 0x00010e73,</div><div class='del'>-	0xd7610000, 0x00011074,</div><div class='del'>-	0xd7610000, 0x00011275,</div><div class='del'>-	0xd7610000, 0x00011476,</div><div class='del'>-	0xd7610000, 0x00011677,</div><div class='del'>-	0xd7610000, 0x00011a79,</div><div class='del'>-	0xd7610000, 0x00011c7e,</div><div class='del'>-	0xd7610000, 0x00011e7f,</div><div class='del'>-	0xbefe03ff, 0x00003fff,</div><div class='del'>-	0xbeff0380, 0xdc5f8040,</div><div class='del'>-	0x007a0000, 0xd760007a,</div><div class='del'>-	0x00011d00, 0xd760007b,</div><div class='del'>-	0x00011f00, 0xbefe037a,</div><div class='del'>-	0xbeff037b, 0xbef4037e,</div><div class='del'>-	0x8775ff7f, 0x0000ffff,</div><div class='del'>-	0x8875ff75, 0x00040000,</div><div class='del'>-	0xbef60380, 0xbef703ff,</div><div class='del'>-	0x10807fac, 0xbef1037c,</div><div class='del'>-	0xbef00380, 0xb97302dc,</div><div class='del'>-	0x8f739973, 0xbefe03c1,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850002,</div><div class='del'>-	0xbeff0380, 0xbf820002,</div><div class='del'>-	0xbeff03c1, 0xbf820009,</div><div class='add'>+	0xbefe03c1, 0xbeff03c1,</div><div class='add'>+	0xdc5f8000, 0x007a0000,</div><div class='add'>+	0x7e000280, 0xbefe037a,</div><div class='add'>+	0xbeff037b, 0xb97b02dc,</div><div class='add'>+	0x8f7b997b, 0xb97a3a05,</div><div class='add'>+	0x807a817a, 0xbf0d997b,</div><div class='add'>+	0xbf850002, 0x8f7a897a,</div><div class='add'>+	0xbf820001, 0x8f7a8a7a,</div><div class='add'>+	0xb97b1e06, 0x8f7b8a7b,</div><div class='add'>+	0x807a7b7a, 0x877bff7f,</div><div class='add'>+	0x0000ffff, 0x807aff7a,</div><div class='add'>+	0x00000200, 0x807a7e7a,</div><div class='add'>+	0x827b807b, 0xd7610000,</div><div class='add'>+	0x00010870, 0xd7610000,</div><div class='add'>+	0x00010a71, 0xd7610000,</div><div class='add'>+	0x00010c72, 0xd7610000,</div><div class='add'>+	0x00010e73, 0xd7610000,</div><div class='add'>+	0x00011074, 0xd7610000,</div><div class='add'>+	0x00011275, 0xd7610000,</div><div class='add'>+	0x00011476, 0xd7610000,</div><div class='add'>+	0x00011677, 0xd7610000,</div><div class='add'>+	0x00011a79, 0xd7610000,</div><div class='add'>+	0x00011c7e, 0xd7610000,</div><div class='add'>+	0x00011e7f, 0xbefe03ff,</div><div class='add'>+	0x00003fff, 0xbeff0380,</div><div class='add'>+	0xdc5f8040, 0x007a0000,</div><div class='add'>+	0xd760007a, 0x00011d00,</div><div class='add'>+	0xd760007b, 0x00011f00,</div><div class='add'>+	0xbefe037a, 0xbeff037b,</div><div class='add'>+	0xbef4037e, 0x8775ff7f,</div><div class='add'>+	0x0000ffff, 0x8875ff75,</div><div class='add'>+	0x00040000, 0xbef60380,</div><div class='add'>+	0xbef703ff, 0x10807fac,</div><div class='add'>+	0xbef1037c, 0xbef00380,</div><div class='add'>+	0xb97302dc, 0x8f739973,</div><div class='add'>+	0xbefe03c1, 0x907c9973,</div><div class='add'>+	0x877c817c, 0xbf06817c,</div><div class='add'>+	0xbf850002, 0xbeff0380,</div><div class='add'>+	0xbf820002, 0xbeff03c1,</div><div class='add'>+	0xbf820009, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xe0704080,</div><div class='add'>+	0x705d0100, 0xe0704100,</div><div class='add'>+	0x705d0200, 0xe0704180,</div><div class='add'>+	0x705d0300, 0xbf820008,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='del'>-	0xe0704080, 0x705d0100,</div><div class='del'>-	0xe0704100, 0x705d0200,</div><div class='del'>-	0xe0704180, 0x705d0300,</div><div class='del'>-	0xbf820008, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xe0704100,</div><div class='del'>-	0x705d0100, 0xe0704200,</div><div class='del'>-	0x705d0200, 0xe0704300,</div><div class='del'>-	0x705d0300, 0xb9703a05,</div><div class='del'>-	0x80708170, 0xbf0d9973,</div><div class='del'>-	0xbf850002, 0x8f708970,</div><div class='del'>-	0xbf820001, 0x8f708a70,</div><div class='del'>-	0xb97a1e06, 0x8f7a8a7a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000200, 0xbef603ff,</div><div class='del'>-	0x01000000, 0x7e000280,</div><div class='del'>-	0x7e020280, 0x7e040280,</div><div class='del'>-	0xbefc0380, 0xd7610002,</div><div class='del'>-	0x0000f871, 0x807c817c,</div><div class='del'>-	0xd7610002, 0x0000f86c,</div><div class='del'>-	0x807c817c, 0x8a7aff6d,</div><div class='del'>-	0x80000000, 0xd7610002,</div><div class='del'>-	0x0000f87a, 0x807c817c,</div><div class='del'>-	0xd7610002, 0x0000f86e,</div><div class='del'>-	0x807c817c, 0xd7610002,</div><div class='del'>-	0x0000f86f, 0x807c817c,</div><div class='del'>-	0xd7610002, 0x0000f878,</div><div class='del'>-	0x807c817c, 0xb97af803,</div><div class='del'>-	0xd7610002, 0x0000f87a,</div><div class='del'>-	0x807c817c, 0xd7610002,</div><div class='del'>-	0x0000f87b, 0x807c817c,</div><div class='del'>-	0xb971f801, 0xd7610002,</div><div class='del'>-	0x0000f871, 0x807c817c,</div><div class='del'>-	0xb971f814, 0xd7610002,</div><div class='del'>-	0x0000f871, 0x807c817c,</div><div class='del'>-	0xb971f815, 0xd7610002,</div><div class='del'>-	0x0000f871, 0x807c817c,</div><div class='del'>-	0xbefe03ff, 0x0000ffff,</div><div class='del'>-	0xbeff0380, 0xe0704000,</div><div class='del'>-	0x705d0200, 0xbefe03c1,</div><div class='add'>+	0xe0704100, 0x705d0100,</div><div class='add'>+	0xe0704200, 0x705d0200,</div><div class='add'>+	0xe0704300, 0x705d0300,</div><div class='ctx'> 	0xb9703a05, 0x80708170,</div><div class='ctx'> 	0xbf0d9973, 0xbf850002,</div><div class='ctx'> 	0x8f708970, 0xbf820001,</div><div class='ctx'> 	0x8f708a70, 0xb97a1e06,</div><div class='ctx'> 	0x8f7a8a7a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000200,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='del'>-	0xbef90380, 0xbefc0380,</div><div class='del'>-	0xbf800000, 0xbe802f00,</div><div class='del'>-	0xbe822f02, 0xbe842f04,</div><div class='del'>-	0xbe862f06, 0xbe882f08,</div><div class='del'>-	0xbe8a2f0a, 0xbe8c2f0c,</div><div class='del'>-	0xbe8e2f0e, 0xd7610002,</div><div class='del'>-	0x0000f200, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f201,</div><div class='add'>+	0x7e000280, 0x7e020280,</div><div class='add'>+	0x7e040280, 0xbefc0380,</div><div class='add'>+	0xd7610002, 0x0000f871,</div><div class='add'>+	0x807c817c, 0xd7610002,</div><div class='add'>+	0x0000f86c, 0x807c817c,</div><div class='add'>+	0x8a7aff6d, 0x80000000,</div><div class='add'>+	0xd7610002, 0x0000f87a,</div><div class='add'>+	0x807c817c, 0xd7610002,</div><div class='add'>+	0x0000f86e, 0x807c817c,</div><div class='add'>+	0xd7610002, 0x0000f86f,</div><div class='add'>+	0x807c817c, 0xd7610002,</div><div class='add'>+	0x0000f878, 0x807c817c,</div><div class='add'>+	0xb97af803, 0xd7610002,</div><div class='add'>+	0x0000f87a, 0x807c817c,</div><div class='add'>+	0xd7610002, 0x0000f87b,</div><div class='add'>+	0x807c817c, 0xb971f801,</div><div class='add'>+	0xd7610002, 0x0000f871,</div><div class='add'>+	0x807c817c, 0xb971f814,</div><div class='add'>+	0xd7610002, 0x0000f871,</div><div class='add'>+	0x807c817c, 0xb971f815,</div><div class='add'>+	0xd7610002, 0x0000f871,</div><div class='add'>+	0x807c817c, 0xbefe03ff,</div><div class='add'>+	0x0000ffff, 0xbeff0380,</div><div class='add'>+	0xe0704000, 0x705d0200,</div><div class='add'>+	0xbefe03c1, 0xb9703a05,</div><div class='add'>+	0x80708170, 0xbf0d9973,</div><div class='add'>+	0xbf850002, 0x8f708970,</div><div class='add'>+	0xbf820001, 0x8f708a70,</div><div class='add'>+	0xb97a1e06, 0x8f7a8a7a,</div><div class='add'>+	0x80707a70, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xbef90380,</div><div class='add'>+	0xbefc0380, 0xbf800000,</div><div class='add'>+	0xbe802f00, 0xbe822f02,</div><div class='add'>+	0xbe842f04, 0xbe862f06,</div><div class='add'>+	0xbe882f08, 0xbe8a2f0a,</div><div class='add'>+	0xbe8c2f0c, 0xbe8e2f0e,</div><div class='add'>+	0xd7610002, 0x0000f200,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f202, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f203,</div><div class='add'>+	0x0000f201, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f202,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f204, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f205,</div><div class='add'>+	0x0000f203, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f204,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f206, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f207,</div><div class='add'>+	0x0000f205, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f206,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f208, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f209,</div><div class='add'>+	0x0000f207, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f208,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20a, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20b,</div><div class='add'>+	0x0000f209, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20a,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20c, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20d,</div><div class='add'>+	0x0000f20b, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20c,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20e, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20f,</div><div class='del'>-	0x80798179, 0xbf06a079,</div><div class='del'>-	0xbf840006, 0xe0704000,</div><div class='del'>-	0x705d0200, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef90380,</div><div class='del'>-	0x7e040280, 0x807c907c,</div><div class='del'>-	0xbf0aff7c, 0x00000060,</div><div class='del'>-	0xbf85ffbc, 0xbe802f00,</div><div class='del'>-	0xbe822f02, 0xbe842f04,</div><div class='del'>-	0xbe862f06, 0xbe882f08,</div><div class='del'>-	0xbe8a2f0a, 0xd7610002,</div><div class='del'>-	0x0000f200, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f201,</div><div class='add'>+	0x0000f20d, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20e,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f202, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f203,</div><div class='add'>+	0x0000f20f, 0x80798179,</div><div class='add'>+	0xbf06a079, 0xbf840006,</div><div class='add'>+	0xe0704000, 0x705d0200,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef90380, 0x7e040280,</div><div class='add'>+	0x807c907c, 0xbf0aff7c,</div><div class='add'>+	0x00000060, 0xbf85ffbc,</div><div class='add'>+	0xbe802f00, 0xbe822f02,</div><div class='add'>+	0xbe842f04, 0xbe862f06,</div><div class='add'>+	0xbe882f08, 0xbe8a2f0a,</div><div class='add'>+	0xd7610002, 0x0000f200,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f204, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f205,</div><div class='add'>+	0x0000f201, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f202,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f206, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f207,</div><div class='add'>+	0x0000f203, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f204,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f208, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f209,</div><div class='add'>+	0x0000f205, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f206,</div><div class='ctx'> 	0x80798179, 0xd7610002,</div><div class='del'>-	0x0000f20a, 0x80798179,</div><div class='del'>-	0xd7610002, 0x0000f20b,</div><div class='del'>-	0x80798179, 0xe0704000,</div><div class='del'>-	0x705d0200, 0xbefe03c1,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850002,</div><div class='del'>-	0xbeff0380, 0xbf820001,</div><div class='del'>-	0xbeff03c1, 0xb97b4306,</div><div class='del'>-	0x877bc17b, 0xbf840044,</div><div class='del'>-	0xbf8a0000, 0x877aff6d,</div><div class='del'>-	0x80000000, 0xbf840040,</div><div class='del'>-	0x8f7b867b, 0x8f7b827b,</div><div class='del'>-	0xbef6037b, 0xb9703a05,</div><div class='del'>-	0x80708170, 0xbf0d9973,</div><div class='del'>-	0xbf850002, 0x8f708970,</div><div class='del'>-	0xbf820001, 0x8f708a70,</div><div class='del'>-	0xb97a1e06, 0x8f7a8a7a,</div><div class='del'>-	0x80707a70, 0x8070ff70,</div><div class='del'>-	0x00000200, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xd7650000,</div><div class='del'>-	0x000100c1, 0xd7660000,</div><div class='del'>-	0x000200c1, 0x16000084,</div><div class='del'>-	0x907c9973, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbefc0380,</div><div class='del'>-	0xbf850012, 0xbe8303ff,</div><div class='del'>-	0x00000080, 0xbf800000,</div><div class='del'>-	0xbf800000, 0xbf800000,</div><div class='del'>-	0xd8d80000, 0x01000000,</div><div class='del'>-	0xbf8c0000, 0xe0704000,</div><div class='del'>-	0x705d0100, 0x807c037c,</div><div class='del'>-	0x80700370, 0xd5250000,</div><div class='del'>-	0x0001ff00, 0x00000080,</div><div class='del'>-	0xbf0a7b7c, 0xbf85fff4,</div><div class='del'>-	0xbf820011, 0xbe8303ff,</div><div class='del'>-	0x00000100, 0xbf800000,</div><div class='del'>-	0xbf800000, 0xbf800000,</div><div class='del'>-	0xd8d80000, 0x01000000,</div><div class='del'>-	0xbf8c0000, 0xe0704000,</div><div class='del'>-	0x705d0100, 0x807c037c,</div><div class='del'>-	0x80700370, 0xd5250000,</div><div class='del'>-	0x0001ff00, 0x00000100,</div><div class='del'>-	0xbf0a7b7c, 0xbf85fff4,</div><div class='add'>+	0x0000f207, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f208,</div><div class='add'>+	0x80798179, 0xd7610002,</div><div class='add'>+	0x0000f209, 0x80798179,</div><div class='add'>+	0xd7610002, 0x0000f20a,</div><div class='add'>+	0x80798179, 0xd7610002,</div><div class='add'>+	0x0000f20b, 0x80798179,</div><div class='add'>+	0xe0704000, 0x705d0200,</div><div class='ctx'> 	0xbefe03c1, 0x907c9973,</div><div class='ctx'> 	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbf850004, 0xbef003ff,</div><div class='del'>-	0x00000200, 0xbeff0380,</div><div class='del'>-	0xbf820003, 0xbef003ff,</div><div class='del'>-	0x00000400, 0xbeff03c1,</div><div class='del'>-	0xb97b3a05, 0x807b817b,</div><div class='del'>-	0x8f7b827b, 0x907c9973,</div><div class='add'>+	0xbf850002, 0xbeff0380,</div><div class='add'>+	0xbf820001, 0xbeff03c1,</div><div class='add'>+	0xb97b4306, 0x877bc17b,</div><div class='add'>+	0xbf840044, 0xbf8a0000,</div><div class='add'>+	0x877aff6d, 0x80000000,</div><div class='add'>+	0xbf840040, 0x8f7b867b,</div><div class='add'>+	0x8f7b827b, 0xbef6037b,</div><div class='add'>+	0xb9703a05, 0x80708170,</div><div class='add'>+	0xbf0d9973, 0xbf850002,</div><div class='add'>+	0x8f708970, 0xbf820001,</div><div class='add'>+	0x8f708a70, 0xb97a1e06,</div><div class='add'>+	0x8f7a8a7a, 0x80707a70,</div><div class='add'>+	0x8070ff70, 0x00000200,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbef603ff, 0x01000000,</div><div class='add'>+	0xd7650000, 0x000100c1,</div><div class='add'>+	0xd7660000, 0x000200c1,</div><div class='add'>+	0x16000084, 0x907c9973,</div><div class='ctx'> 	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbf850017, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbefc0384,</div><div class='del'>-	0xbf0a7b7c, 0xbf840037,</div><div class='del'>-	0x7e008700, 0x7e028701,</div><div class='del'>-	0x7e048702, 0x7e068703,</div><div class='del'>-	0xe0704000, 0x705d0000,</div><div class='del'>-	0xe0704080, 0x705d0100,</div><div class='del'>-	0xe0704100, 0x705d0200,</div><div class='del'>-	0xe0704180, 0x705d0300,</div><div class='del'>-	0x807c847c, 0x8070ff70,</div><div class='del'>-	0x00000200, 0xbf0a7b7c,</div><div class='del'>-	0xbf85ffef, 0xbf820025,</div><div class='add'>+	0xbefc0380, 0xbf850012,</div><div class='add'>+	0xbe8303ff, 0x00000080,</div><div class='add'>+	0xbf800000, 0xbf800000,</div><div class='add'>+	0xbf800000, 0xd8d80000,</div><div class='add'>+	0x01000000, 0xbf8c0000,</div><div class='add'>+	0xe0704000, 0x705d0100,</div><div class='add'>+	0x807c037c, 0x80700370,</div><div class='add'>+	0xd5250000, 0x0001ff00,</div><div class='add'>+	0x00000080, 0xbf0a7b7c,</div><div class='add'>+	0xbf85fff4, 0xbf820011,</div><div class='add'>+	0xbe8303ff, 0x00000100,</div><div class='add'>+	0xbf800000, 0xbf800000,</div><div class='add'>+	0xbf800000, 0xd8d80000,</div><div class='add'>+	0x01000000, 0xbf8c0000,</div><div class='add'>+	0xe0704000, 0x705d0100,</div><div class='add'>+	0x807c037c, 0x80700370,</div><div class='add'>+	0xd5250000, 0x0001ff00,</div><div class='add'>+	0x00000100, 0xbf0a7b7c,</div><div class='add'>+	0xbf85fff4, 0xbefe03c1,</div><div class='add'>+	0x907c9973, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbf850004,</div><div class='add'>+	0xbef003ff, 0x00000200,</div><div class='add'>+	0xbeff0380, 0xbf820003,</div><div class='add'>+	0xbef003ff, 0x00000400,</div><div class='add'>+	0xbeff03c1, 0xb97b3a05,</div><div class='add'>+	0x807b817b, 0x8f7b827b,</div><div class='add'>+	0x907c9973, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbf850017,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='ctx'> 	0xbefc0384, 0xbf0a7b7c,</div><div class='del'>-	0xbf840011, 0x7e008700,</div><div class='add'>+	0xbf840037, 0x7e008700,</div><div class='ctx'> 	0x7e028701, 0x7e048702,</div><div class='ctx'> 	0x7e068703, 0xe0704000,</div><div class='del'>-	0x705d0000, 0xe0704100,</div><div class='del'>-	0x705d0100, 0xe0704200,</div><div class='del'>-	0x705d0200, 0xe0704300,</div><div class='add'>+	0x705d0000, 0xe0704080,</div><div class='add'>+	0x705d0100, 0xe0704100,</div><div class='add'>+	0x705d0200, 0xe0704180,</div><div class='ctx'> 	0x705d0300, 0x807c847c,</div><div class='del'>-	0x8070ff70, 0x00000400,</div><div class='add'>+	0x8070ff70, 0x00000200,</div><div class='ctx'> 	0xbf0a7b7c, 0xbf85ffef,</div><div class='del'>-	0xb97b1e06, 0x877bc17b,</div><div class='del'>-	0xbf84000c, 0x8f7b837b,</div><div class='del'>-	0x807b7c7b, 0xbefe03c1,</div><div class='del'>-	0xbeff0380, 0x7e008700,</div><div class='add'>+	0xbf820025, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xbefc0384,</div><div class='add'>+	0xbf0a7b7c, 0xbf840011,</div><div class='add'>+	0x7e008700, 0x7e028701,</div><div class='add'>+	0x7e048702, 0x7e068703,</div><div class='ctx'> 	0xe0704000, 0x705d0000,</div><div class='del'>-	0x807c817c, 0x8070ff70,</div><div class='del'>-	0x00000080, 0xbf0a7b7c,</div><div class='del'>-	0xbf85fff8, 0xbf82013b,</div><div class='del'>-	0xbef4037e, 0x8775ff7f,</div><div class='del'>-	0x0000ffff, 0x8875ff75,</div><div class='del'>-	0x00040000, 0xbef60380,</div><div class='del'>-	0xbef703ff, 0x10807fac,</div><div class='del'>-	0xb97202dc, 0x8f729972,</div><div class='del'>-	0x876eff7f, 0x04000000,</div><div class='del'>-	0xbf840034, 0xbefe03c1,</div><div class='del'>-	0x907c9972, 0x877c817c,</div><div class='del'>-	0xbf06817c, 0xbf850002,</div><div class='del'>-	0xbeff0380, 0xbf820001,</div><div class='del'>-	0xbeff03c1, 0xb96f4306,</div><div class='del'>-	0x876fc16f, 0xbf840029,</div><div class='del'>-	0x8f6f866f, 0x8f6f826f,</div><div class='del'>-	0xbef6036f, 0xb9783a05,</div><div class='del'>-	0x80788178, 0xbf0d9972,</div><div class='del'>-	0xbf850002, 0x8f788978,</div><div class='del'>-	0xbf820001, 0x8f788a78,</div><div class='del'>-	0xb96e1e06, 0x8f6e8a6e,</div><div class='del'>-	0x80786e78, 0x8078ff78,</div><div class='del'>-	0x00000200, 0x8078ff78,</div><div class='del'>-	0x00000080, 0xbef603ff,</div><div class='del'>-	0x01000000, 0x907c9972,</div><div class='del'>-	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbefc0380, 0xbf850009,</div><div class='del'>-	0xe0310000, 0x781d0000,</div><div class='del'>-	0x807cff7c, 0x00000080,</div><div class='del'>-	0x8078ff78, 0x00000080,</div><div class='del'>-	0xbf0a6f7c, 0xbf85fff8,</div><div class='del'>-	0xbf820008, 0xe0310000,</div><div class='del'>-	0x781d0000, 0x807cff7c,</div><div class='del'>-	0x00000100, 0x8078ff78,</div><div class='del'>-	0x00000100, 0xbf0a6f7c,</div><div class='del'>-	0xbf85fff8, 0xbef80380,</div><div class='add'>+	0xe0704100, 0x705d0100,</div><div class='add'>+	0xe0704200, 0x705d0200,</div><div class='add'>+	0xe0704300, 0x705d0300,</div><div class='add'>+	0x807c847c, 0x8070ff70,</div><div class='add'>+	0x00000400, 0xbf0a7b7c,</div><div class='add'>+	0xbf85ffef, 0xb97b1e06,</div><div class='add'>+	0x877bc17b, 0xbf84000c,</div><div class='add'>+	0x8f7b837b, 0x807b7c7b,</div><div class='add'>+	0xbefe03c1, 0xbeff0380,</div><div class='add'>+	0x7e008700, 0xe0704000,</div><div class='add'>+	0x705d0000, 0x807c817c,</div><div class='add'>+	0x8070ff70, 0x00000080,</div><div class='add'>+	0xbf0a7b7c, 0xbf85fff8,</div><div class='add'>+	0xbf82013b, 0xbef4037e,</div><div class='add'>+	0x8775ff7f, 0x0000ffff,</div><div class='add'>+	0x8875ff75, 0x00040000,</div><div class='add'>+	0xbef60380, 0xbef703ff,</div><div class='add'>+	0x10807fac, 0xb97202dc,</div><div class='add'>+	0x8f729972, 0x876eff7f,</div><div class='add'>+	0x04000000, 0xbf840034,</div><div class='ctx'> 	0xbefe03c1, 0x907c9972,</div><div class='ctx'> 	0x877c817c, 0xbf06817c,</div><div class='ctx'> 	0xbf850002, 0xbeff0380,</div><div class='ctx'> 	0xbf820001, 0xbeff03c1,</div><div class='del'>-	0xb96f3a05, 0x806f816f,</div><div class='del'>-	0x8f6f826f, 0x907c9972,</div><div class='del'>-	0x877c817c, 0xbf06817c,</div><div class='del'>-	0xbf850024, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbeee0378,</div><div class='add'>+	0xb96f4306, 0x876fc16f,</div><div class='add'>+	0xbf840029, 0x8f6f866f,</div><div class='add'>+	0x8f6f826f, 0xbef6036f,</div><div class='add'>+	0xb9783a05, 0x80788178,</div><div class='add'>+	0xbf0d9972, 0xbf850002,</div><div class='add'>+	0x8f788978, 0xbf820001,</div><div class='add'>+	0x8f788a78, 0xb96e1e06,</div><div class='add'>+	0x8f6e8a6e, 0x80786e78,</div><div class='ctx'> 	0x8078ff78, 0x00000200,</div><div class='del'>-	0xbefc0384, 0xbf0a6f7c,</div><div class='del'>-	0xbf840050, 0xe0304000,</div><div class='del'>-	0x785d0000, 0xe0304080,</div><div class='del'>-	0x785d0100, 0xe0304100,</div><div class='del'>-	0x785d0200, 0xe0304180,</div><div class='del'>-	0x785d0300, 0xbf8c3f70,</div><div class='del'>-	0x7e008500, 0x7e028501,</div><div class='del'>-	0x7e048502, 0x7e068503,</div><div class='del'>-	0x807c847c, 0x8078ff78,</div><div class='del'>-	0x00000200, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffee, 0xe0304000,</div><div class='del'>-	0x6e5d0000, 0xe0304080,</div><div class='del'>-	0x6e5d0100, 0xe0304100,</div><div class='del'>-	0x6e5d0200, 0xe0304180,</div><div class='del'>-	0x6e5d0300, 0xbf8c3f70,</div><div class='del'>-	0xbf820034, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbeee0378,</div><div class='del'>-	0x8078ff78, 0x00000400,</div><div class='del'>-	0xbefc0384, 0xbf0a6f7c,</div><div class='del'>-	0xbf840012, 0xe0304000,</div><div class='del'>-	0x785d0000, 0xe0304100,</div><div class='del'>-	0x785d0100, 0xe0304200,</div><div class='del'>-	0x785d0200, 0xe0304300,</div><div class='del'>-	0x785d0300, 0xbf8c3f70,</div><div class='del'>-	0x7e008500, 0x7e028501,</div><div class='del'>-	0x7e048502, 0x7e068503,</div><div class='del'>-	0x807c847c, 0x8078ff78,</div><div class='del'>-	0x00000400, 0xbf0a6f7c,</div><div class='del'>-	0xbf85ffee, 0xb96f1e06,</div><div class='del'>-	0x876fc16f, 0xbf84000e,</div><div class='del'>-	0x8f6f836f, 0x806f7c6f,</div><div class='del'>-	0xbefe03c1, 0xbeff0380,</div><div class='add'>+	0x8078ff78, 0x00000080,</div><div class='add'>+	0xbef603ff, 0x01000000,</div><div class='add'>+	0x907c9972, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbefc0380,</div><div class='add'>+	0xbf850009, 0xe0310000,</div><div class='add'>+	0x781d0000, 0x807cff7c,</div><div class='add'>+	0x00000080, 0x8078ff78,</div><div class='add'>+	0x00000080, 0xbf0a6f7c,</div><div class='add'>+	0xbf85fff8, 0xbf820008,</div><div class='add'>+	0xe0310000, 0x781d0000,</div><div class='add'>+	0x807cff7c, 0x00000100,</div><div class='add'>+	0x8078ff78, 0x00000100,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff8,</div><div class='add'>+	0xbef80380, 0xbefe03c1,</div><div class='add'>+	0x907c9972, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbf850002,</div><div class='add'>+	0xbeff0380, 0xbf820001,</div><div class='add'>+	0xbeff03c1, 0xb96f3a05,</div><div class='add'>+	0x806f816f, 0x8f6f826f,</div><div class='add'>+	0x907c9972, 0x877c817c,</div><div class='add'>+	0xbf06817c, 0xbf850024,</div><div class='add'>+	0xbef603ff, 0x01000000,</div><div class='add'>+	0xbeee0378, 0x8078ff78,</div><div class='add'>+	0x00000200, 0xbefc0384,</div><div class='add'>+	0xbf0a6f7c, 0xbf840050,</div><div class='ctx'> 	0xe0304000, 0x785d0000,</div><div class='add'>+	0xe0304080, 0x785d0100,</div><div class='add'>+	0xe0304100, 0x785d0200,</div><div class='add'>+	0xe0304180, 0x785d0300,</div><div class='ctx'> 	0xbf8c3f70, 0x7e008500,</div><div class='del'>-	0x807c817c, 0x8078ff78,</div><div class='del'>-	0x00000080, 0xbf0a6f7c,</div><div class='del'>-	0xbf85fff7, 0xbeff03c1,</div><div class='add'>+	0x7e028501, 0x7e048502,</div><div class='add'>+	0x7e068503, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000200,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffee,</div><div class='ctx'> 	0xe0304000, 0x6e5d0000,</div><div class='del'>-	0xe0304100, 0x6e5d0100,</div><div class='del'>-	0xe0304200, 0x6e5d0200,</div><div class='del'>-	0xe0304300, 0x6e5d0300,</div><div class='del'>-	0xbf8c3f70, 0xb9783a05,</div><div class='del'>-	0x80788178, 0xbf0d9972,</div><div class='del'>-	0xbf850002, 0x8f788978,</div><div class='del'>-	0xbf820001, 0x8f788a78,</div><div class='del'>-	0xb96e1e06, 0x8f6e8a6e,</div><div class='del'>-	0x80786e78, 0x8078ff78,</div><div class='del'>-	0x00000200, 0x80f8ff78,</div><div class='del'>-	0x00000050, 0xbef603ff,</div><div class='del'>-	0x01000000, 0xbefc03ff,</div><div class='del'>-	0x0000006c, 0x80f89078,</div><div class='del'>-	0xf429003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc847c,</div><div class='del'>-	0xbf800000, 0xbe803100,</div><div class='del'>-	0xbe823102, 0x80f8a078,</div><div class='del'>-	0xf42d003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc887c,</div><div class='del'>-	0xbf800000, 0xbe803100,</div><div class='del'>-	0xbe823102, 0xbe843104,</div><div class='del'>-	0xbe863106, 0x80f8c078,</div><div class='del'>-	0xf431003a, 0xf0000000,</div><div class='del'>-	0xbf8cc07f, 0x80fc907c,</div><div class='del'>-	0xbf800000, 0xbe803100,</div><div class='del'>-	0xbe823102, 0xbe843104,</div><div class='del'>-	0xbe863106, 0xbe883108,</div><div class='del'>-	0xbe8a310a, 0xbe8c310c,</div><div class='del'>-	0xbe8e310e, 0xbf06807c,</div><div class='del'>-	0xbf84fff0, 0xba80f801,</div><div class='del'>-	0x00000000, 0xbf8a0000,</div><div class='add'>+	0xe0304080, 0x6e5d0100,</div><div class='add'>+	0xe0304100, 0x6e5d0200,</div><div class='add'>+	0xe0304180, 0x6e5d0300,</div><div class='add'>+	0xbf8c3f70, 0xbf820034,</div><div class='add'>+	0xbef603ff, 0x01000000,</div><div class='add'>+	0xbeee0378, 0x8078ff78,</div><div class='add'>+	0x00000400, 0xbefc0384,</div><div class='add'>+	0xbf0a6f7c, 0xbf840012,</div><div class='add'>+	0xe0304000, 0x785d0000,</div><div class='add'>+	0xe0304100, 0x785d0100,</div><div class='add'>+	0xe0304200, 0x785d0200,</div><div class='add'>+	0xe0304300, 0x785d0300,</div><div class='add'>+	0xbf8c3f70, 0x7e008500,</div><div class='add'>+	0x7e028501, 0x7e048502,</div><div class='add'>+	0x7e068503, 0x807c847c,</div><div class='add'>+	0x8078ff78, 0x00000400,</div><div class='add'>+	0xbf0a6f7c, 0xbf85ffee,</div><div class='add'>+	0xb96f1e06, 0x876fc16f,</div><div class='add'>+	0xbf84000e, 0x8f6f836f,</div><div class='add'>+	0x806f7c6f, 0xbefe03c1,</div><div class='add'>+	0xbeff0380, 0xe0304000,</div><div class='add'>+	0x785d0000, 0xbf8c3f70,</div><div class='add'>+	0x7e008500, 0x807c817c,</div><div class='add'>+	0x8078ff78, 0x00000080,</div><div class='add'>+	0xbf0a6f7c, 0xbf85fff7,</div><div class='add'>+	0xbeff03c1, 0xe0304000,</div><div class='add'>+	0x6e5d0000, 0xe0304100,</div><div class='add'>+	0x6e5d0100, 0xe0304200,</div><div class='add'>+	0x6e5d0200, 0xe0304300,</div><div class='add'>+	0x6e5d0300, 0xbf8c3f70,</div><div class='ctx'> 	0xb9783a05, 0x80788178,</div><div class='ctx'> 	0xbf0d9972, 0xbf850002,</div><div class='ctx'> 	0x8f788978, 0xbf820001,</div><div class='ctx'> 	0x8f788a78, 0xb96e1e06,</div><div class='ctx'> 	0x8f6e8a6e, 0x80786e78,</div><div class='ctx'> 	0x8078ff78, 0x00000200,</div><div class='add'>+	0x80f8ff78, 0x00000050,</div><div class='ctx'> 	0xbef603ff, 0x01000000,</div><div class='del'>-	0xf4211bfa, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4211b3a,</div><div class='add'>+	0xbefc03ff, 0x0000006c,</div><div class='add'>+	0x80f89078, 0xf429003a,</div><div class='add'>+	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0x80fc847c, 0xbf800000,</div><div class='add'>+	0xbe803100, 0xbe823102,</div><div class='add'>+	0x80f8a078, 0xf42d003a,</div><div class='add'>+	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0x80fc887c, 0xbf800000,</div><div class='add'>+	0xbe803100, 0xbe823102,</div><div class='add'>+	0xbe843104, 0xbe863106,</div><div class='add'>+	0x80f8c078, 0xf431003a,</div><div class='add'>+	0xf0000000, 0xbf8cc07f,</div><div class='add'>+	0x80fc907c, 0xbf800000,</div><div class='add'>+	0xbe803100, 0xbe823102,</div><div class='add'>+	0xbe843104, 0xbe863106,</div><div class='add'>+	0xbe883108, 0xbe8a310a,</div><div class='add'>+	0xbe8c310c, 0xbe8e310e,</div><div class='add'>+	0xbf06807c, 0xbf84fff0,</div><div class='add'>+	0xba80f801, 0x00000000,</div><div class='add'>+	0xbf8a0000, 0xb9783a05,</div><div class='add'>+	0x80788178, 0xbf0d9972,</div><div class='add'>+	0xbf850002, 0x8f788978,</div><div class='add'>+	0xbf820001, 0x8f788a78,</div><div class='add'>+	0xb96e1e06, 0x8f6e8a6e,</div><div class='add'>+	0x80786e78, 0x8078ff78,</div><div class='add'>+	0x00000200, 0xbef603ff,</div><div class='add'>+	0x01000000, 0xf4211bfa,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4211b7a, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4211c3a,</div><div class='add'>+	0xf4211b3a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4211b7a,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4211c7a, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4211eba,</div><div class='add'>+	0xf4211c3a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4211c7a,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4211efa, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4211e7a,</div><div class='add'>+	0xf4211eba, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4211efa,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xf4211cfa, 0xf0000000,</div><div class='del'>-	0x80788478, 0xf4211bba,</div><div class='add'>+	0xf4211e7a, 0xf0000000,</div><div class='add'>+	0x80788478, 0xf4211cfa,</div><div class='ctx'> 	0xf0000000, 0x80788478,</div><div class='del'>-	0xbf8cc07f, 0xb9eef814,</div><div class='ctx'> 	0xf4211bba, 0xf0000000,</div><div class='ctx'> 	0x80788478, 0xbf8cc07f,</div><div class='del'>-	0xb9eef815, 0xbefc036f,</div><div class='del'>-	0xbefe0370, 0xbeff0371,</div><div class='del'>-	0x876f7bff, 0x000003ff,</div><div class='del'>-	0xb9ef4803, 0x876f7bff,</div><div class='del'>-	0xfffff800, 0x906f8b6f,</div><div class='del'>-	0xb9efa2c3, 0xb9f3f801,</div><div class='del'>-	0xb96e3a05, 0x806e816e,</div><div class='del'>-	0xbf0d9972, 0xbf850002,</div><div class='del'>-	0x8f6e896e, 0xbf820001,</div><div class='del'>-	0x8f6e8a6e, 0xb96f1e06,</div><div class='del'>-	0x8f6f8a6f, 0x806e6f6e,</div><div class='del'>-	0x806eff6e, 0x00000200,</div><div class='del'>-	0x806e746e, 0x826f8075,</div><div class='del'>-	0x876fff6f, 0x0000ffff,</div><div class='del'>-	0xf4091c37, 0xfa000050,</div><div class='del'>-	0xf4091d37, 0xfa000060,</div><div class='del'>-	0xf4011e77, 0xfa000074,</div><div class='del'>-	0xbf8cc07f, 0x876dff6d,</div><div class='del'>-	0x0000ffff, 0x87fe7e7e,</div><div class='del'>-	0x87ea6a6a, 0xb9faf802,</div><div class='del'>-	0xbe80226c, 0xbf810000,</div><div class='add'>+	0xb9eef814, 0xf4211bba,</div><div class='add'>+	0xf0000000, 0x80788478,</div><div class='add'>+	0xbf8cc07f, 0xb9eef815,</div><div class='add'>+	0xbefc036f, 0xbefe0370,</div><div class='add'>+	0xbeff0371, 0x876f7bff,</div><div class='add'>+	0x000003ff, 0xb9ef4803,</div><div class='add'>+	0x876f7bff, 0xfffff800,</div><div class='add'>+	0x906f8b6f, 0xb9efa2c3,</div><div class='add'>+	0xb9f3f801, 0xb96e3a05,</div><div class='add'>+	0x806e816e, 0xbf0d9972,</div><div class='add'>+	0xbf850002, 0x8f6e896e,</div><div class='add'>+	0xbf820001, 0x8f6e8a6e,</div><div class='add'>+	0xb96f1e06, 0x8f6f8a6f,</div><div class='add'>+	0x806e6f6e, 0x806eff6e,</div><div class='add'>+	0x00000200, 0x806e746e,</div><div class='add'>+	0x826f8075, 0x876fff6f,</div><div class='add'>+	0x0000ffff, 0xf4091c37,</div><div class='add'>+	0xfa000050, 0xf4091d37,</div><div class='add'>+	0xfa000060, 0xf4011e77,</div><div class='add'>+	0xfa000074, 0xbf8cc07f,</div><div class='add'>+	0x876dff6d, 0x0000ffff,</div><div class='add'>+	0x87fe7e7e, 0x87ea6a6a,</div><div class='add'>+	0xb9faf802, 0xbe80226c,</div><div class='add'>+	0xbf810000, 0xbf9f0000,</div><div class='ctx'> 	0xbf9f0000, 0xbf9f0000,</div><div class='ctx'> 	0xbf9f0000, 0xbf9f0000,</div><div class='del'>-	0xbf9f0000, 0x00000000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const uint32_t cwsr_trap_gfx11_hex[] = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm<br/>index fdab64624422..e0140df0b0ec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm</a></div><div class='hunk'>@@ -369,6 +369,12 @@ L_SLEEP:</div><div class='ctx'> 	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp</div><div class='ctx'> </div><div class='ctx'> #if NO_SQC_STORE</div><div class='add'>+#if ASIC_FAMILY &lt;= CHIP_SIENNA_CICHLID</div><div class='add'>+	// gfx10: If there was a VALU exception, the exception state must be</div><div class='add'>+	// cleared before executing the VALU instructions below.</div><div class='add'>+	v_clrexcp</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	// Trap temporaries must be saved via VGPR but all VGPRs are in use.</div><div class='ctx'> 	// There is no ttmp space to hold the resource constant for VGPR save.</div><div class='ctx'> 	// Save v0 by itself since it requires only two SGPRs.</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c<br/>index f6d4748c1980..ce4c52ec34d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_chardev.c</a></div><div class='hunk'>@@ -1564,16 +1564,11 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_ioctl_import_dmabuf_args *args = data;</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='del'>-	struct dma_buf *dmabuf;</div><div class='ctx'> 	int idr_handle;</div><div class='ctx'> 	uint64_t size;</div><div class='ctx'> 	void *mem;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	dmabuf = dma_buf_get(args-&gt;dmabuf_fd);</div><div class='del'>-	if (IS_ERR(dmabuf))</div><div class='del'>-		return PTR_ERR(dmabuf);</div><div class='del'>-</div><div class='ctx'> 	mutex_lock(&amp;p-&gt;mutex);</div><div class='ctx'> 	pdd = kfd_process_device_data_by_id(p, args-&gt;gpu_id);</div><div class='ctx'> 	if (!pdd) {</div><div class='hunk'>@@ -1587,10 +1582,10 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd-&gt;dev-&gt;adev, dmabuf,</div><div class='del'>-					      args-&gt;va_addr, pdd-&gt;drm_priv,</div><div class='del'>-					      (struct kgd_mem **)&amp;mem, &amp;size,</div><div class='del'>-					      NULL);</div><div class='add'>+	r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd-&gt;dev-&gt;adev, args-&gt;dmabuf_fd,</div><div class='add'>+						 args-&gt;va_addr, pdd-&gt;drm_priv,</div><div class='add'>+						 (struct kgd_mem **)&amp;mem, &amp;size,</div><div class='add'>+						 NULL);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -1601,7 +1596,6 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;mutex);</div><div class='del'>-	dma_buf_put(dmabuf);</div><div class='ctx'> </div><div class='ctx'> 	args-&gt;handle = MAKE_HANDLE(args-&gt;gpu_id, idr_handle);</div><div class='ctx'> </div><div class='hunk'>@@ -1612,7 +1606,6 @@ err_free:</div><div class='ctx'> 					       pdd-&gt;drm_priv, NULL);</div><div class='ctx'> err_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;mutex);</div><div class='del'>-	dma_buf_put(dmabuf);</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1855,8 +1848,8 @@ static uint32_t get_process_num_bos(struct kfd_process *p)</div><div class='ctx'> 	return num_of_bos;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int criu_get_prime_handle(struct kgd_mem *mem, int flags,</div><div class='del'>-				      u32 *shared_fd)</div><div class='add'>+static int criu_get_prime_handle(struct kgd_mem *mem,</div><div class='add'>+				 int flags, u32 *shared_fd)</div><div class='ctx'> {</div><div class='ctx'> 	struct dma_buf *dmabuf;</div><div class='ctx'> 	int ret;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c<br/>index 0f58be65132f..739721254a5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_events.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_events.c</a></div><div class='hunk'>@@ -880,6 +880,10 @@ static int copy_signaled_event_data(uint32_t num_events,</div><div class='ctx'> 				dst = &amp;data[i].memory_exception_data;</div><div class='ctx'> 				src = &amp;event-&gt;memory_exception_data;</div><div class='ctx'> 				size = sizeof(struct kfd_hsa_memory_exception_data);</div><div class='add'>+			} else if (event-&gt;type == KFD_EVENT_TYPE_HW_EXCEPTION) {</div><div class='add'>+				dst = &amp;data[i].memory_exception_data;</div><div class='add'>+				src = &amp;event-&gt;hw_exception_data;</div><div class='add'>+				size = sizeof(struct kfd_hsa_hw_exception_data);</div><div class='ctx'> 			} else if (event-&gt;type == KFD_EVENT_TYPE_SIGNAL &amp;&amp;</div><div class='ctx'> 				waiter-&gt;event_age_enabled) {</div><div class='ctx'> 				dst = &amp;data[i].signal_event_data.last_event_age;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c<br/>index 62b205dac63a..6604a3f99c5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c</a></div><div class='hunk'>@@ -330,12 +330,6 @@ static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)</div><div class='ctx'> 	pdd-&gt;gpuvm_limit =</div><div class='ctx'> 		pdd-&gt;dev-&gt;kfd-&gt;shared_resources.gpuvm_size - 1;</div><div class='ctx'> </div><div class='del'>-	/* dGPUs: the reserved space for kernel</div><div class='del'>-	 * before SVM</div><div class='del'>-	 */</div><div class='del'>-	pdd-&gt;qpd.cwsr_base = SVM_CWSR_BASE;</div><div class='del'>-	pdd-&gt;qpd.ib_base = SVM_IB_BASE;</div><div class='del'>-</div><div class='ctx'> 	pdd-&gt;scratch_base = MAKE_SCRATCH_APP_BASE_VI();</div><div class='ctx'> 	pdd-&gt;scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd-&gt;scratch_base);</div><div class='ctx'> }</div><div class='hunk'>@@ -345,18 +339,18 @@ static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)</div><div class='ctx'> 	pdd-&gt;lds_base = MAKE_LDS_APP_BASE_V9();</div><div class='ctx'> 	pdd-&gt;lds_limit = MAKE_LDS_APP_LIMIT(pdd-&gt;lds_base);</div><div class='ctx'> </div><div class='del'>-	pdd-&gt;gpuvm_base = PAGE_SIZE;</div><div class='add'>+        /* Raven needs SVM to support graphic handle, etc. Leave the small</div><div class='add'>+         * reserved space before SVM on Raven as well, even though we don't</div><div class='add'>+         * have to.</div><div class='add'>+         * Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they</div><div class='add'>+         * are used in Thunk to reserve SVM.</div><div class='add'>+         */</div><div class='add'>+        pdd-&gt;gpuvm_base = SVM_USER_BASE;</div><div class='ctx'> 	pdd-&gt;gpuvm_limit =</div><div class='ctx'> 		pdd-&gt;dev-&gt;kfd-&gt;shared_resources.gpuvm_size - 1;</div><div class='ctx'> </div><div class='ctx'> 	pdd-&gt;scratch_base = MAKE_SCRATCH_APP_BASE_V9();</div><div class='ctx'> 	pdd-&gt;scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd-&gt;scratch_base);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Place TBA/TMA on opposite side of VM hole to prevent</div><div class='del'>-	 * stray faults from triggering SVM on these pages.</div><div class='del'>-	 */</div><div class='del'>-	pdd-&gt;qpd.cwsr_base = pdd-&gt;dev-&gt;kfd-&gt;shared_resources.gpuvm_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int kfd_init_apertures(struct kfd_process *process)</div><div class='hunk'>@@ -413,6 +407,12 @@ int kfd_init_apertures(struct kfd_process *process)</div><div class='ctx'> 					return -EINVAL;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+                        /* dGPUs: the reserved space for kernel</div><div class='add'>+                         * before SVM</div><div class='add'>+                         */</div><div class='add'>+                        pdd-&gt;qpd.cwsr_base = SVM_CWSR_BASE;</div><div class='add'>+                        pdd-&gt;qpd.ib_base = SVM_IB_BASE;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dev_dbg(kfd_device, "node id %u\n", id);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c<br/>index 6c25dab051d5..f856901055d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.c</a></div><div class='hunk'>@@ -260,19 +260,6 @@ static void svm_migrate_put_sys_page(unsigned long addr)</div><div class='ctx'> 	put_page(page);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned long svm_migrate_successful_pages(struct migrate_vma *migrate)</div><div class='del'>-{</div><div class='del'>-	unsigned long cpages = 0;</div><div class='del'>-	unsigned long i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; migrate-&gt;npages; i++) {</div><div class='del'>-		if (migrate-&gt;src[i] &amp; MIGRATE_PFN_VALID &amp;&amp;</div><div class='del'>-		    migrate-&gt;src[i] &amp; MIGRATE_PFN_MIGRATE)</div><div class='del'>-			cpages++;</div><div class='del'>-	}</div><div class='del'>-	return cpages;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long upages = 0;</div><div class='hunk'>@@ -402,6 +389,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	struct dma_fence *mfence = NULL;</div><div class='ctx'> 	struct migrate_vma migrate = { 0 };</div><div class='ctx'> 	unsigned long cpages = 0;</div><div class='add'>+	unsigned long mpages = 0;</div><div class='ctx'> 	dma_addr_t *scratch;</div><div class='ctx'> 	void *buf;</div><div class='ctx'> 	int r = -ENOMEM;</div><div class='hunk'>@@ -442,20 +430,21 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (cpages != npages)</div><div class='del'>-		pr_debug("partial migration, 0x%lx/0x%llx pages migrated\n",</div><div class='add'>+		pr_debug("partial migration, 0x%lx/0x%llx pages collected\n",</div><div class='ctx'> 			 cpages, npages);</div><div class='ctx'> 	else</div><div class='del'>-		pr_debug("0x%lx pages migrated\n", cpages);</div><div class='add'>+		pr_debug("0x%lx pages collected\n", cpages);</div><div class='ctx'> </div><div class='ctx'> 	r = svm_migrate_copy_to_vram(node, prange, &amp;migrate, &amp;mfence, scratch, ttm_res_offset);</div><div class='ctx'> 	migrate_vma_pages(&amp;migrate);</div><div class='ctx'> </div><div class='del'>-	pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n",</div><div class='del'>-		svm_migrate_successful_pages(&amp;migrate), cpages, migrate.npages);</div><div class='del'>-</div><div class='ctx'> 	svm_migrate_copy_done(adev, mfence);</div><div class='ctx'> 	migrate_vma_finalize(&amp;migrate);</div><div class='ctx'> </div><div class='add'>+	mpages = cpages - svm_migrate_unsuccessful_pages(&amp;migrate);</div><div class='add'>+	pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n",</div><div class='add'>+			 mpages, cpages, migrate.npages);</div><div class='add'>+</div><div class='ctx'> 	kfd_smi_event_migration_end(node, p-&gt;lead_thread-&gt;pid,</div><div class='ctx'> 				    start &gt;&gt; PAGE_SHIFT, end &gt;&gt; PAGE_SHIFT,</div><div class='ctx'> 				    0, node-&gt;id, trigger);</div><div class='hunk'>@@ -465,12 +454,12 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> out_free:</div><div class='ctx'> 	kvfree(buf);</div><div class='ctx'> out:</div><div class='del'>-	if (!r &amp;&amp; cpages) {</div><div class='add'>+	if (!r &amp;&amp; mpages) {</div><div class='ctx'> 		pdd = svm_range_get_pdd_by_node(prange, node);</div><div class='ctx'> 		if (pdd)</div><div class='del'>-			WRITE_ONCE(pdd-&gt;page_in, pdd-&gt;page_in + cpages);</div><div class='add'>+			WRITE_ONCE(pdd-&gt;page_in, pdd-&gt;page_in + mpages);</div><div class='ctx'> </div><div class='del'>-		return cpages;</div><div class='add'>+		return mpages;</div><div class='ctx'> 	}</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='hunk'>@@ -479,6 +468,8 @@ out:</div><div class='ctx'>  * svm_migrate_ram_to_vram - migrate svm range from system to device</div><div class='ctx'>  * @prange: range structure</div><div class='ctx'>  * @best_loc: the device to migrate to</div><div class='add'>+ * @start_mgr: start page to migrate</div><div class='add'>+ * @last_mgr: last page to migrate</div><div class='ctx'>  * @mm: the process mm structure</div><div class='ctx'>  * @trigger: reason of migration</div><div class='ctx'>  *</div><div class='hunk'>@@ -489,19 +480,20 @@ out:</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='ctx'> svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='add'>+			unsigned long start_mgr, unsigned long last_mgr,</div><div class='ctx'> 			struct mm_struct *mm, uint32_t trigger)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long addr, start, end;</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='ctx'> 	uint64_t ttm_res_offset;</div><div class='ctx'> 	struct kfd_node *node;</div><div class='del'>-	unsigned long cpages = 0;</div><div class='add'>+	unsigned long mpages = 0;</div><div class='ctx'> 	long r = 0;</div><div class='ctx'> </div><div class='del'>-	if (prange-&gt;actual_loc == best_loc) {</div><div class='del'>-		pr_debug("svms 0x%p [0x%lx 0x%lx] already on best_loc 0x%x\n",</div><div class='del'>-			 prange-&gt;svms, prange-&gt;start, prange-&gt;last, best_loc);</div><div class='del'>-		return 0;</div><div class='add'>+	if (start_mgr &lt; prange-&gt;start || last_mgr &gt; prange-&gt;last) {</div><div class='add'>+		pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",</div><div class='add'>+			 start_mgr, last_mgr, prange-&gt;start, prange-&gt;last);</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	node = svm_range_get_node_by_id(prange, best_loc);</div><div class='hunk'>@@ -510,18 +502,19 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pr_debug("svms 0x%p [0x%lx 0x%lx] to gpu 0x%x\n", prange-&gt;svms,</div><div class='del'>-		 prange-&gt;start, prange-&gt;last, best_loc);</div><div class='add'>+	pr_debug("svms 0x%p [0x%lx 0x%lx] in [0x%lx 0x%lx] to gpu 0x%x\n",</div><div class='add'>+		prange-&gt;svms, start_mgr, last_mgr, prange-&gt;start, prange-&gt;last,</div><div class='add'>+		best_loc);</div><div class='ctx'> </div><div class='del'>-	start = prange-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='del'>-	end = (prange-&gt;last + 1) &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	start = start_mgr &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	end = (last_mgr + 1) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	r = svm_range_vram_node_new(node, prange, true);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		dev_dbg(node-&gt;adev-&gt;dev, "fail %ld to alloc vram\n", r);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='del'>-	ttm_res_offset = prange-&gt;offset &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	ttm_res_offset = (start_mgr - prange-&gt;start + prange-&gt;offset) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	for (addr = start; addr &lt; end;) {</div><div class='ctx'> 		unsigned long next;</div><div class='hunk'>@@ -536,16 +529,19 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 			pr_debug("failed %ld to migrate\n", r);</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else {</div><div class='del'>-			cpages += r;</div><div class='add'>+			mpages += r;</div><div class='ctx'> 		}</div><div class='ctx'> 		ttm_res_offset += next - addr;</div><div class='ctx'> 		addr = next;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (cpages) {</div><div class='add'>+	if (mpages) {</div><div class='ctx'> 		prange-&gt;actual_loc = best_loc;</div><div class='del'>-		svm_range_dma_unmap(prange);</div><div class='del'>-	} else {</div><div class='add'>+		prange-&gt;vram_pages += mpages;</div><div class='add'>+	} else if (!prange-&gt;actual_loc) {</div><div class='add'>+		/* if no page migrated and all pages from prange are at</div><div class='add'>+		 * sys ram drop svm_bo got from svm_range_vram_node_new</div><div class='add'>+		 */</div><div class='ctx'> 		svm_range_vram_node_free(prange);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -663,9 +659,8 @@ out_oom:</div><div class='ctx'>  * Context: Process context, caller hold mmap read lock, prange-&gt;migrate_mutex</div><div class='ctx'>  *</div><div class='ctx'>  * Return:</div><div class='del'>- *   0 - success with all pages migrated</div><div class='ctx'>  *   negative values - indicate error</div><div class='del'>- *   positive values - partial migration, number of pages not migrated</div><div class='add'>+ *   positive values or zero - number of pages got migrated</div><div class='ctx'>  */</div><div class='ctx'> static long</div><div class='ctx'> svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='hunk'>@@ -676,6 +671,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 	uint64_t npages = (end - start) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 	unsigned long upages = npages;</div><div class='ctx'> 	unsigned long cpages = 0;</div><div class='add'>+	unsigned long mpages = 0;</div><div class='ctx'> 	struct amdgpu_device *adev = node-&gt;adev;</div><div class='ctx'> 	struct kfd_process_device *pdd;</div><div class='ctx'> 	struct dma_fence *mfence = NULL;</div><div class='hunk'>@@ -725,10 +721,10 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (cpages != npages)</div><div class='del'>-		pr_debug("partial migration, 0x%lx/0x%llx pages migrated\n",</div><div class='add'>+		pr_debug("partial migration, 0x%lx/0x%llx pages collected\n",</div><div class='ctx'> 			 cpages, npages);</div><div class='ctx'> 	else</div><div class='del'>-		pr_debug("0x%lx pages migrated\n", cpages);</div><div class='add'>+		pr_debug("0x%lx pages collected\n", cpages);</div><div class='ctx'> </div><div class='ctx'> 	r = svm_migrate_copy_to_ram(adev, prange, &amp;migrate, &amp;mfence,</div><div class='ctx'> 				    scratch, npages);</div><div class='hunk'>@@ -751,17 +747,21 @@ out_free:</div><div class='ctx'> 	kvfree(buf);</div><div class='ctx'> out:</div><div class='ctx'> 	if (!r &amp;&amp; cpages) {</div><div class='add'>+		mpages = cpages - upages;</div><div class='ctx'> 		pdd = svm_range_get_pdd_by_node(prange, node);</div><div class='ctx'> 		if (pdd)</div><div class='del'>-			WRITE_ONCE(pdd-&gt;page_out, pdd-&gt;page_out + cpages);</div><div class='add'>+			WRITE_ONCE(pdd-&gt;page_out, pdd-&gt;page_out + mpages);</div><div class='ctx'> 	}</div><div class='del'>-	return r ? r : upages;</div><div class='add'>+</div><div class='add'>+	return r ? r : mpages;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * svm_migrate_vram_to_ram - migrate svm range from device to system</div><div class='ctx'>  * @prange: range structure</div><div class='ctx'>  * @mm: process mm, use current-&gt;mm if NULL</div><div class='add'>+ * @start_mgr: start page need be migrated to sys ram</div><div class='add'>+ * @last_mgr: last page need be migrated to sys ram</div><div class='ctx'>  * @trigger: reason of migration</div><div class='ctx'>  * @fault_page: is from vmf-&gt;page, svm_migrate_to_ram(), this is CPU page fault callback</div><div class='ctx'>  *</div><div class='hunk'>@@ -771,6 +771,7 @@ out:</div><div class='ctx'>  * 0 - OK, otherwise error code</div><div class='ctx'>  */</div><div class='ctx'> int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='add'>+			    unsigned long start_mgr, unsigned long last_mgr,</div><div class='ctx'> 			    uint32_t trigger, struct page *fault_page)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_node *node;</div><div class='hunk'>@@ -778,26 +779,33 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'> 	unsigned long addr;</div><div class='ctx'> 	unsigned long start;</div><div class='ctx'> 	unsigned long end;</div><div class='del'>-	unsigned long upages = 0;</div><div class='add'>+	unsigned long mpages = 0;</div><div class='ctx'> 	long r = 0;</div><div class='ctx'> </div><div class='add'>+	/* this pragne has no any vram page to migrate to sys ram */</div><div class='ctx'> 	if (!prange-&gt;actual_loc) {</div><div class='ctx'> 		pr_debug("[0x%lx 0x%lx] already migrated to ram\n",</div><div class='ctx'> 			 prange-&gt;start, prange-&gt;last);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (start_mgr &lt; prange-&gt;start || last_mgr &gt; prange-&gt;last) {</div><div class='add'>+		pr_debug("range [0x%lx 0x%lx] out prange [0x%lx 0x%lx]\n",</div><div class='add'>+			 start_mgr, last_mgr, prange-&gt;start, prange-&gt;last);</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	node = svm_range_get_node_by_id(prange, prange-&gt;actual_loc);</div><div class='ctx'> 	if (!node) {</div><div class='ctx'> 		pr_debug("failed to get kfd node by id 0x%x\n", prange-&gt;actual_loc);</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> 	pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] from gpu 0x%x to ram\n",</div><div class='del'>-		 prange-&gt;svms, prange, prange-&gt;start, prange-&gt;last,</div><div class='add'>+		 prange-&gt;svms, prange, start_mgr, last_mgr,</div><div class='ctx'> 		 prange-&gt;actual_loc);</div><div class='ctx'> </div><div class='del'>-	start = prange-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='del'>-	end = (prange-&gt;last + 1) &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	start = start_mgr &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	end = (last_mgr + 1) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	for (addr = start; addr &lt; end;) {</div><div class='ctx'> 		unsigned long next;</div><div class='hunk'>@@ -816,14 +824,21 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'> 			pr_debug("failed %ld to migrate prange %p\n", r, prange);</div><div class='ctx'> 			break;</div><div class='ctx'> 		} else {</div><div class='del'>-			upages += r;</div><div class='add'>+			mpages += r;</div><div class='ctx'> 		}</div><div class='ctx'> 		addr = next;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (r &gt;= 0 &amp;&amp; !upages) {</div><div class='del'>-		svm_range_vram_node_free(prange);</div><div class='del'>-		prange-&gt;actual_loc = 0;</div><div class='add'>+	if (r &gt;= 0) {</div><div class='add'>+		prange-&gt;vram_pages -= mpages;</div><div class='add'>+</div><div class='add'>+		/* prange does not have vram page set its actual_loc to system</div><div class='add'>+		 * and drop its svm_bo ref</div><div class='add'>+		 */</div><div class='add'>+		if (prange-&gt;vram_pages == 0 &amp;&amp; prange-&gt;ttm_res) {</div><div class='add'>+			prange-&gt;actual_loc = 0;</div><div class='add'>+			svm_range_vram_node_free(prange);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return r &lt; 0 ? r : 0;</div><div class='hunk'>@@ -833,17 +848,23 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'>  * svm_migrate_vram_to_vram - migrate svm range from device to device</div><div class='ctx'>  * @prange: range structure</div><div class='ctx'>  * @best_loc: the device to migrate to</div><div class='add'>+ * @start: start page need be migrated to sys ram</div><div class='add'>+ * @last: last page need be migrated to sys ram</div><div class='ctx'>  * @mm: process mm, use current-&gt;mm if NULL</div><div class='ctx'>  * @trigger: reason of migration</div><div class='ctx'>  *</div><div class='ctx'>  * Context: Process context, caller hold mmap read lock, svms lock, prange lock</div><div class='ctx'>  *</div><div class='add'>+ * migrate all vram pages in prange to sys ram, then migrate</div><div class='add'>+ * [start, last] pages from sys ram to gpu node best_loc.</div><div class='add'>+ *</div><div class='ctx'>  * Return:</div><div class='ctx'>  * 0 - OK, otherwise error code</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='ctx'> svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='del'>-			 struct mm_struct *mm, uint32_t trigger)</div><div class='add'>+			unsigned long start, unsigned long last,</div><div class='add'>+			struct mm_struct *mm, uint32_t trigger)</div><div class='ctx'> {</div><div class='ctx'> 	int r, retries = 3;</div><div class='ctx'> </div><div class='hunk'>@@ -855,7 +876,8 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 	pr_debug("from gpu 0x%x to gpu 0x%x\n", prange-&gt;actual_loc, best_loc);</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		r = svm_migrate_vram_to_ram(prange, mm, trigger, NULL);</div><div class='add'>+		r = svm_migrate_vram_to_ram(prange, mm, prange-&gt;start, prange-&gt;last,</div><div class='add'>+					    trigger, NULL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	} while (prange-&gt;actual_loc &amp;&amp; --retries);</div><div class='hunk'>@@ -863,17 +885,21 @@ svm_migrate_vram_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'> 	if (prange-&gt;actual_loc)</div><div class='ctx'> 		return -EDEADLK;</div><div class='ctx'> </div><div class='del'>-	return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger);</div><div class='add'>+	return svm_migrate_ram_to_vram(prange, best_loc, start, last, mm, trigger);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int</div><div class='ctx'> svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='add'>+		    unsigned long start, unsigned long last,</div><div class='ctx'> 		    struct mm_struct *mm, uint32_t trigger)</div><div class='ctx'> {</div><div class='del'>-	if  (!prange-&gt;actual_loc)</div><div class='del'>-		return svm_migrate_ram_to_vram(prange, best_loc, mm, trigger);</div><div class='add'>+	if  (!prange-&gt;actual_loc || prange-&gt;actual_loc == best_loc)</div><div class='add'>+		return svm_migrate_ram_to_vram(prange, best_loc, start, last,</div><div class='add'>+					       mm, trigger);</div><div class='add'>+</div><div class='ctx'> 	else</div><div class='del'>-		return svm_migrate_vram_to_vram(prange, best_loc, mm, trigger);</div><div class='add'>+		return svm_migrate_vram_to_vram(prange, best_loc, start, last,</div><div class='add'>+						mm, trigger);</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -889,10 +915,9 @@ svm_migrate_to_vram(struct svm_range *prange, uint32_t best_loc,</div><div class='ctx'>  */</div><div class='ctx'> static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)</div><div class='ctx'> {</div><div class='add'>+	unsigned long start, last, size;</div><div class='ctx'> 	unsigned long addr = vmf-&gt;address;</div><div class='ctx'> 	struct svm_range_bo *svm_bo;</div><div class='del'>-	enum svm_work_list_ops op;</div><div class='del'>-	struct svm_range *parent;</div><div class='ctx'> 	struct svm_range *prange;</div><div class='ctx'> 	struct kfd_process *p;</div><div class='ctx'> 	struct mm_struct *mm;</div><div class='hunk'>@@ -929,51 +954,31 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;p-&gt;svms.lock);</div><div class='ctx'> </div><div class='del'>-	prange = svm_range_from_addr(&amp;p-&gt;svms, addr, &amp;parent);</div><div class='add'>+	prange = svm_range_from_addr(&amp;p-&gt;svms, addr, NULL);</div><div class='ctx'> 	if (!prange) {</div><div class='ctx'> 		pr_debug("failed get range svms 0x%p addr 0x%lx\n", &amp;p-&gt;svms, addr);</div><div class='ctx'> 		r = -EFAULT;</div><div class='ctx'> 		goto out_unlock_svms;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;parent-&gt;migrate_mutex);</div><div class='del'>-	if (prange != parent)</div><div class='del'>-		mutex_lock_nested(&amp;prange-&gt;migrate_mutex, 1);</div><div class='add'>+	mutex_lock(&amp;prange-&gt;migrate_mutex);</div><div class='ctx'> </div><div class='ctx'> 	if (!prange-&gt;actual_loc)</div><div class='ctx'> 		goto out_unlock_prange;</div><div class='ctx'> </div><div class='del'>-	svm_range_lock(parent);</div><div class='del'>-	if (prange != parent)</div><div class='del'>-		mutex_lock_nested(&amp;prange-&gt;lock, 1);</div><div class='del'>-	r = svm_range_split_by_granularity(p, mm, addr, parent, prange);</div><div class='del'>-	if (prange != parent)</div><div class='del'>-		mutex_unlock(&amp;prange-&gt;lock);</div><div class='del'>-	svm_range_unlock(parent);</div><div class='del'>-	if (r) {</div><div class='del'>-		pr_debug("failed %d to split range by granularity\n", r);</div><div class='del'>-		goto out_unlock_prange;</div><div class='del'>-	}</div><div class='add'>+	/* Align migration range start and size to granularity size */</div><div class='add'>+	size = 1UL &lt;&lt; prange-&gt;granularity;</div><div class='add'>+	start = max(ALIGN_DOWN(addr, size), prange-&gt;start);</div><div class='add'>+	last = min(ALIGN(addr + 1, size) - 1, prange-&gt;last);</div><div class='ctx'> </div><div class='del'>-	r = svm_migrate_vram_to_ram(prange, vmf-&gt;vma-&gt;vm_mm,</div><div class='del'>-				    KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU,</div><div class='del'>-				    vmf-&gt;page);</div><div class='add'>+	r = svm_migrate_vram_to_ram(prange, vmf-&gt;vma-&gt;vm_mm, start, last,</div><div class='add'>+				    KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, vmf-&gt;page);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		pr_debug("failed %d migrate svms 0x%p range 0x%p [0x%lx 0x%lx]\n",</div><div class='del'>-			 r, prange-&gt;svms, prange, prange-&gt;start, prange-&gt;last);</div><div class='del'>-</div><div class='del'>-	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */</div><div class='del'>-	if (p-&gt;xnack_enabled &amp;&amp; parent == prange)</div><div class='del'>-		op = SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP;</div><div class='del'>-	else</div><div class='del'>-		op = SVM_OP_UPDATE_RANGE_NOTIFIER;</div><div class='del'>-	svm_range_add_list_work(&amp;p-&gt;svms, parent, mm, op);</div><div class='del'>-	schedule_deferred_list_work(&amp;p-&gt;svms);</div><div class='add'>+			r, prange-&gt;svms, prange, start, last);</div><div class='ctx'> </div><div class='ctx'> out_unlock_prange:</div><div class='del'>-	if (prange != parent)</div><div class='del'>-		mutex_unlock(&amp;prange-&gt;migrate_mutex);</div><div class='del'>-	mutex_unlock(&amp;parent-&gt;migrate_mutex);</div><div class='add'>+	mutex_unlock(&amp;prange-&gt;migrate_mutex);</div><div class='ctx'> out_unlock_svms:</div><div class='ctx'> 	mutex_unlock(&amp;p-&gt;svms.lock);</div><div class='ctx'> out_unref_process:</div><div class='hunk'>@@ -1021,7 +1026,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)</div><div class='ctx'> 	} else {</div><div class='ctx'> 		res = devm_request_free_mem_region(adev-&gt;dev, &amp;iomem_resource, size);</div><div class='ctx'> 		if (IS_ERR(res))</div><div class='del'>-			return -ENOMEM;</div><div class='add'>+			return PTR_ERR(res);</div><div class='ctx'> 		pgmap-&gt;range.start = res-&gt;start;</div><div class='ctx'> 		pgmap-&gt;range.end = res-&gt;end;</div><div class='ctx'> 		pgmap-&gt;type = MEMORY_DEVICE_PRIVATE;</div><div class='hunk'>@@ -1037,10 +1042,10 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)</div><div class='ctx'> 	r = devm_memremap_pages(adev-&gt;dev, pgmap);</div><div class='ctx'> 	if (IS_ERR(r)) {</div><div class='ctx'> 		pr_err("failed to register HMM device memory\n");</div><div class='del'>-		/* Disable SVM support capability */</div><div class='del'>-		pgmap-&gt;type = 0;</div><div class='ctx'> 		if (pgmap-&gt;type == MEMORY_DEVICE_PRIVATE)</div><div class='ctx'> 			devm_release_mem_region(adev-&gt;dev, res-&gt;start, resource_size(res));</div><div class='add'>+		/* Disable SVM support capability */</div><div class='add'>+		pgmap-&gt;type = 0;</div><div class='ctx'> 		return PTR_ERR(r);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h<br/>index 487f26368164..2eebf67f9c2c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_migrate.h</a></div><div class='hunk'>@@ -41,9 +41,13 @@ enum MIGRATION_COPY_DIR {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int svm_migrate_to_vram(struct svm_range *prange,  uint32_t best_loc,</div><div class='add'>+			unsigned long start, unsigned long last,</div><div class='ctx'> 			struct mm_struct *mm, uint32_t trigger);</div><div class='add'>+</div><div class='ctx'> int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm,</div><div class='add'>+			    unsigned long start, unsigned long last,</div><div class='ctx'> 			    uint32_t trigger, struct page *fault_page);</div><div class='add'>+</div><div class='ctx'> unsigned long</div><div class='ctx'> svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h<br/>index 9cc32f577e38..17fbedbf3651 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_priv.h</a></div><div class='hunk'>@@ -748,7 +748,6 @@ struct kfd_process_device {</div><div class='ctx'> 	/* VM context for GPUVM allocations */</div><div class='ctx'> 	struct file *drm_file;</div><div class='ctx'> 	void *drm_priv;</div><div class='del'>-	atomic64_t tlb_seq;</div><div class='ctx'> </div><div class='ctx'> 	/* GPUVM allocations storage */</div><div class='ctx'> 	struct idr alloc_idr;</div><div class='hunk'>@@ -918,7 +917,7 @@ struct kfd_process {</div><div class='ctx'> 	 * fence will be triggered during eviction and new one will be created</div><div class='ctx'> 	 * during restore</div><div class='ctx'> 	 */</div><div class='del'>-	struct dma_fence *ef;</div><div class='add'>+	struct dma_fence __rcu *ef;</div><div class='ctx'> </div><div class='ctx'> 	/* Work items for evicting and restoring BOs */</div><div class='ctx'> 	struct delayed_work eviction_work;</div><div class='hunk'>@@ -971,7 +970,7 @@ struct kfd_process {</div><div class='ctx'> 	struct work_struct debug_event_workarea;</div><div class='ctx'> </div><div class='ctx'> 	/* Tracks debug per-vmid request for debug flags */</div><div class='del'>-	bool dbg_flags;</div><div class='add'>+	u32 dbg_flags;</div><div class='ctx'> </div><div class='ctx'> 	atomic_t poison;</div><div class='ctx'> 	/* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */</div><div class='hunk'>@@ -1128,7 +1127,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev,</div><div class='ctx'> 	struct kfd_dev *dev = adev-&gt;kfd.dev;</div><div class='ctx'> 	uint32_t i;</div><div class='ctx'> </div><div class='del'>-	if (adev-&gt;ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3))</div><div class='add'>+	if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3))</div><div class='ctx'> 		return dev-&gt;nodes[0];</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dev-&gt;num_nodes; i++)</div><div class='hunk'>@@ -1462,7 +1461,14 @@ void kfd_signal_reset_event(struct kfd_node *dev);</div><div class='ctx'> </div><div class='ctx'> void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid);</div><div class='ctx'> </div><div class='del'>-void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);</div><div class='add'>+static inline void kfd_flush_tlb(struct kfd_process_device *pdd,</div><div class='add'>+				 enum TLB_FLUSH_TYPE type)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = pdd-&gt;dev-&gt;adev;</div><div class='add'>+	struct amdgpu_vm *vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='add'>+</div><div class='add'>+	amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd-&gt;dev-&gt;xcc_mask);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c<br/>index 7a33e06f5c90..717a60d7a4ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_process.c</a></div><div class='hunk'>@@ -664,7 +664,8 @@ int kfd_process_create_wq(void)</div><div class='ctx'> 	if (!kfd_process_wq)</div><div class='ctx'> 		kfd_process_wq = alloc_workqueue("kfd_process_wq", 0, 0);</div><div class='ctx'> 	if (!kfd_restore_wq)</div><div class='del'>-		kfd_restore_wq = alloc_ordered_workqueue("kfd_restore_wq", 0);</div><div class='add'>+		kfd_restore_wq = alloc_ordered_workqueue("kfd_restore_wq",</div><div class='add'>+							 WQ_FREEZABLE);</div><div class='ctx'> </div><div class='ctx'> 	if (!kfd_process_wq || !kfd_restore_wq) {</div><div class='ctx'> 		kfd_process_destroy_wq();</div><div class='hunk'>@@ -1109,6 +1110,7 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct kfd_process *p = container_of(work, struct kfd_process,</div><div class='ctx'> 					     release_work);</div><div class='add'>+	struct dma_fence *ef;</div><div class='ctx'> </div><div class='ctx'> 	kfd_process_dequeue_from_all_devices(p);</div><div class='ctx'> 	pqm_uninit(&amp;p-&gt;pqm);</div><div class='hunk'>@@ -1117,7 +1119,9 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> 	 * destroyed. This allows any BOs to be freed without</div><div class='ctx'> 	 * triggering pointless evictions or waiting for fences.</div><div class='ctx'> 	 */</div><div class='del'>-	dma_fence_signal(p-&gt;ef);</div><div class='add'>+	synchronize_rcu();</div><div class='add'>+	ef = rcu_access_pointer(p-&gt;ef);</div><div class='add'>+	dma_fence_signal(ef);</div><div class='ctx'> </div><div class='ctx'> 	kfd_process_remove_sysfs(p);</div><div class='ctx'> </div><div class='hunk'>@@ -1126,7 +1130,7 @@ static void kfd_process_wq_release(struct work_struct *work)</div><div class='ctx'> 	svm_range_list_fini(p);</div><div class='ctx'> </div><div class='ctx'> 	kfd_process_destroy_pdds(p);</div><div class='del'>-	dma_fence_put(p-&gt;ef);</div><div class='add'>+	dma_fence_put(ef);</div><div class='ctx'> </div><div class='ctx'> 	kfd_event_free_process(p);</div><div class='ctx'> </div><div class='hunk'>@@ -1642,6 +1646,7 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,</div><div class='ctx'> 	struct amdgpu_fpriv *drv_priv;</div><div class='ctx'> 	struct amdgpu_vm *avm;</div><div class='ctx'> 	struct kfd_process *p;</div><div class='add'>+	struct dma_fence *ef;</div><div class='ctx'> 	struct kfd_node *dev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1661,13 +1666,13 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,</div><div class='ctx'> </div><div class='ctx'> 	ret = amdgpu_amdkfd_gpuvm_acquire_process_vm(dev-&gt;adev, avm,</div><div class='ctx'> 						     &amp;p-&gt;kgd_process_info,</div><div class='del'>-						     &amp;p-&gt;ef);</div><div class='add'>+						     &amp;ef);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pr_err("Failed to create process VM object\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='add'>+	RCU_INIT_POINTER(p-&gt;ef, ef);</div><div class='ctx'> 	pdd-&gt;drm_priv = drm_file-&gt;private_data;</div><div class='del'>-	atomic64_set(&amp;pdd-&gt;tlb_seq, 0);</div><div class='ctx'> </div><div class='ctx'> 	ret = kfd_process_device_reserve_ib_mem(pdd);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1909,6 +1914,21 @@ kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int signal_eviction_fence(struct kfd_process *p)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *ef;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	ef = dma_fence_get_rcu_safe(&amp;p-&gt;ef);</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+</div><div class='add'>+	ret = dma_fence_signal(ef);</div><div class='add'>+	dma_fence_put(ef);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void evict_process_worker(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1921,31 +1941,46 @@ static void evict_process_worker(struct work_struct *work)</div><div class='ctx'> 	 * lifetime of this thread, kfd_process p will be valid</div><div class='ctx'> 	 */</div><div class='ctx'> 	p = container_of(dwork, struct kfd_process, eviction_work);</div><div class='del'>-	WARN_ONCE(p-&gt;last_eviction_seqno != p-&gt;ef-&gt;seqno,</div><div class='del'>-		  "Eviction fence mismatch\n");</div><div class='del'>-</div><div class='del'>-	/* Narrow window of overlap between restore and evict work</div><div class='del'>-	 * item is possible. Once amdgpu_amdkfd_gpuvm_restore_process_bos</div><div class='del'>-	 * unreserves KFD BOs, it is possible to evicted again. But</div><div class='del'>-	 * restore has few more steps of finish. So lets wait for any</div><div class='del'>-	 * previous restore work to complete</div><div class='del'>-	 */</div><div class='del'>-	flush_delayed_work(&amp;p-&gt;restore_work);</div><div class='ctx'> </div><div class='ctx'> 	pr_debug("Started evicting pasid 0x%x\n", p-&gt;pasid);</div><div class='ctx'> 	ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM);</div><div class='ctx'> 	if (!ret) {</div><div class='del'>-		dma_fence_signal(p-&gt;ef);</div><div class='del'>-		dma_fence_put(p-&gt;ef);</div><div class='del'>-		p-&gt;ef = NULL;</div><div class='del'>-		queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='add'>+		/* If another thread already signaled the eviction fence,</div><div class='add'>+		 * they are responsible stopping the queues and scheduling</div><div class='add'>+		 * the restore work.</div><div class='add'>+		 */</div><div class='add'>+		if (!signal_eviction_fence(p))</div><div class='add'>+			queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='ctx'> 				msecs_to_jiffies(PROCESS_RESTORE_TIME_MS));</div><div class='add'>+		else</div><div class='add'>+			kfd_process_restore_queues(p);</div><div class='ctx'> </div><div class='ctx'> 		pr_debug("Finished evicting pasid 0x%x\n", p-&gt;pasid);</div><div class='ctx'> 	} else</div><div class='ctx'> 		pr_err("Failed to evict queues of pasid 0x%x\n", p-&gt;pasid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int restore_process_helper(struct kfd_process *p)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* VMs may not have been acquired yet during debugging. */</div><div class='add'>+	if (p-&gt;kgd_process_info) {</div><div class='add'>+		ret = amdgpu_amdkfd_gpuvm_restore_process_bos(</div><div class='add'>+			p-&gt;kgd_process_info, &amp;p-&gt;ef);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = kfd_process_restore_queues(p);</div><div class='add'>+	if (!ret)</div><div class='add'>+		pr_debug("Finished restoring pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+	else</div><div class='add'>+		pr_err("Failed to restore queues of pasid 0x%x\n", p-&gt;pasid);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void restore_process_worker(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct delayed_work *dwork;</div><div class='hunk'>@@ -1971,24 +2006,15 @@ static void restore_process_worker(struct work_struct *work)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	p-&gt;last_restore_timestamp = get_jiffies_64();</div><div class='del'>-	/* VMs may not have been acquired yet during debugging. */</div><div class='del'>-	if (p-&gt;kgd_process_info)</div><div class='del'>-		ret = amdgpu_amdkfd_gpuvm_restore_process_bos(p-&gt;kgd_process_info,</div><div class='del'>-							     &amp;p-&gt;ef);</div><div class='add'>+</div><div class='add'>+	ret = restore_process_helper(p);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pr_debug("Failed to restore BOs of pasid 0x%x, retry after %d ms\n",</div><div class='ctx'> 			 p-&gt;pasid, PROCESS_BACK_OFF_TIME_MS);</div><div class='ctx'> 		ret = queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work,</div><div class='ctx'> 				msecs_to_jiffies(PROCESS_BACK_OFF_TIME_MS));</div><div class='ctx'> 		WARN(!ret, "reschedule restore work failed\n");</div><div class='del'>-		return;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	ret = kfd_process_restore_queues(p);</div><div class='del'>-	if (!ret)</div><div class='del'>-		pr_debug("Finished restoring pasid 0x%x\n", p-&gt;pasid);</div><div class='del'>-	else</div><div class='del'>-		pr_err("Failed to restore queues of pasid 0x%x\n", p-&gt;pasid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void kfd_suspend_all_processes(void)</div><div class='hunk'>@@ -1999,14 +2025,9 @@ void kfd_suspend_all_processes(void)</div><div class='ctx'> </div><div class='ctx'> 	WARN(debug_evictions, "Evicting all processes");</div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='del'>-		cancel_delayed_work_sync(&amp;p-&gt;eviction_work);</div><div class='del'>-		flush_delayed_work(&amp;p-&gt;restore_work);</div><div class='del'>-</div><div class='ctx'> 		if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND))</div><div class='ctx'> 			pr_err("Failed to suspend process 0x%x\n", p-&gt;pasid);</div><div class='del'>-		dma_fence_signal(p-&gt;ef);</div><div class='del'>-		dma_fence_put(p-&gt;ef);</div><div class='del'>-		p-&gt;ef = NULL;</div><div class='add'>+		signal_eviction_fence(p);</div><div class='ctx'> 	}</div><div class='ctx'> 	srcu_read_unlock(&amp;kfd_processes_srcu, idx);</div><div class='ctx'> }</div><div class='hunk'>@@ -2018,7 +2039,7 @@ int kfd_resume_all_processes(void)</div><div class='ctx'> 	int ret = 0, idx = srcu_read_lock(&amp;kfd_processes_srcu);</div><div class='ctx'> </div><div class='ctx'> 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {</div><div class='del'>-		if (!queue_delayed_work(kfd_restore_wq, &amp;p-&gt;restore_work, 0)) {</div><div class='add'>+		if (restore_process_helper(p)) {</div><div class='ctx'> 			pr_err("Restore process %d failed during resume\n",</div><div class='ctx'> 			       p-&gt;pasid);</div><div class='ctx'> 			ret = -EFAULT;</div><div class='hunk'>@@ -2059,36 +2080,6 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process,</div><div class='ctx'> 			       KFD_CWSR_TBA_TMA_SIZE, vma-&gt;vm_page_prot);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_vm *vm = drm_priv_to_vm(pdd-&gt;drm_priv);</div><div class='del'>-	uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);</div><div class='del'>-	struct kfd_node *dev = pdd-&gt;dev;</div><div class='del'>-	uint32_t xcc_mask = dev-&gt;xcc_mask;</div><div class='del'>-	int xcc = 0;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * It can be that we race and lose here, but that is extremely unlikely</div><div class='del'>-	 * and the worst thing which could happen is that we flush the changes</div><div class='del'>-	 * into the TLB once more which is harmless.</div><div class='del'>-	 */</div><div class='del'>-	if (atomic64_xchg(&amp;pdd-&gt;tlb_seq, tlb_seq) == tlb_seq)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (dev-&gt;dqm-&gt;sched_policy == KFD_SCHED_POLICY_NO_HWS) {</div><div class='del'>-		/* Nothing to flush until a VMID is assigned, which</div><div class='del'>-		 * only happens when the first queue is created.</div><div class='del'>-		 */</div><div class='del'>-		if (pdd-&gt;qpd.vmid)</div><div class='del'>-			amdgpu_amdkfd_flush_gpu_tlb_vmid(dev-&gt;adev,</div><div class='del'>-							pdd-&gt;qpd.vmid);</div><div class='del'>-	} else {</div><div class='del'>-		for_each_inst(xcc, xcc_mask)</div><div class='del'>-			amdgpu_amdkfd_flush_gpu_tlb_pasid(</div><div class='del'>-				dev-&gt;adev, pdd-&gt;process-&gt;pasid, type, xcc);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* assumes caller holds process lock. */</div><div class='ctx'> int kfd_process_drain_interrupts(struct kfd_process_device *pdd)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c<br/>index 77649392e233..43eff221eae5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c</a></div><div class='hunk'>@@ -87,6 +87,8 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;dqm-&gt;ops.process_termination(dev-&gt;dqm, &amp;pdd-&gt;qpd);</div><div class='add'>+	if (dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+		amdgpu_mes_flush_shader_debugger(dev-&gt;adev, pdd-&gt;proc_ctx_gpu_addr);</div><div class='ctx'> 	pdd-&gt;already_dequeued = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -169,16 +171,43 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void pqm_clean_queue_resource(struct process_queue_manager *pqm,</div><div class='add'>+				     struct process_queue_node *pqn)</div><div class='add'>+{</div><div class='add'>+	struct kfd_node *dev;</div><div class='add'>+	struct kfd_process_device *pdd;</div><div class='add'>+</div><div class='add'>+	dev = pqn-&gt;q-&gt;device;</div><div class='add'>+</div><div class='add'>+	pdd = kfd_get_process_device_data(dev, pqm-&gt;process);</div><div class='add'>+	if (!pdd) {</div><div class='add'>+		pr_err("Process device data doesn't exist\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pqn-&gt;q-&gt;gws) {</div><div class='add'>+		if (KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='add'>+		    !dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='add'>+			amdgpu_amdkfd_remove_gws_from_process(</div><div class='add'>+				pqm-&gt;process-&gt;kgd_process_info, pqn-&gt;q-&gt;gws);</div><div class='add'>+		pdd-&gt;qpd.num_gws = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='add'>+		amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, pqn-&gt;q-&gt;gang_ctx_bo);</div><div class='add'>+		if (pqn-&gt;q-&gt;wptr_bo)</div><div class='add'>+			amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, pqn-&gt;q-&gt;wptr_bo);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void pqm_uninit(struct process_queue_manager *pqm)</div><div class='ctx'> {</div><div class='ctx'> 	struct process_queue_node *pqn, *next;</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(pqn, next, &amp;pqm-&gt;queues, process_queue_list) {</div><div class='del'>-		if (pqn-&gt;q &amp;&amp; pqn-&gt;q-&gt;gws &amp;&amp;</div><div class='del'>-		    KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='del'>-		    !pqn-&gt;q-&gt;device-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-			amdgpu_amdkfd_remove_gws_from_process(pqm-&gt;process-&gt;kgd_process_info,</div><div class='del'>-				pqn-&gt;q-&gt;gws);</div><div class='add'>+		if (pqn-&gt;q)</div><div class='add'>+			pqm_clean_queue_resource(pqm, pqn);</div><div class='add'>+</div><div class='ctx'> 		kfd_procfs_del_queue(pqn-&gt;q);</div><div class='ctx'> 		uninit_queue(pqn-&gt;q);</div><div class='ctx'> 		list_del(&amp;pqn-&gt;process_queue_list);</div><div class='hunk'>@@ -461,22 +490,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)</div><div class='ctx'> 				goto err_destroy_queue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (pqn-&gt;q-&gt;gws) {</div><div class='del'>-			if (KFD_GC_VERSION(pqn-&gt;q-&gt;device) != IP_VERSION(9, 4, 3) &amp;&amp;</div><div class='del'>-			    !dev-&gt;kfd-&gt;shared_resources.enable_mes)</div><div class='del'>-				amdgpu_amdkfd_remove_gws_from_process(</div><div class='del'>-						pqm-&gt;process-&gt;kgd_process_info,</div><div class='del'>-						pqn-&gt;q-&gt;gws);</div><div class='del'>-			pdd-&gt;qpd.num_gws = 0;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (dev-&gt;kfd-&gt;shared_resources.enable_mes) {</div><div class='del'>-			amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev,</div><div class='del'>-						   pqn-&gt;q-&gt;gang_ctx_bo);</div><div class='del'>-			if (pqn-&gt;q-&gt;wptr_bo)</div><div class='del'>-				amdgpu_amdkfd_free_gtt_mem(dev-&gt;adev, pqn-&gt;q-&gt;wptr_bo);</div><div class='del'>-</div><div class='del'>-		}</div><div class='add'>+		pqm_clean_queue_resource(pqm, pqn);</div><div class='ctx'> 		uninit_queue(pqn-&gt;q);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c<br/>index f2f3c338fd94..c50a0dc9c9c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_svm.c</a></div><div class='hunk'>@@ -198,6 +198,7 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange,</div><div class='ctx'> 		pr_debug_ratelimited("dma mapping 0x%llx for page addr 0x%lx\n",</div><div class='ctx'> 				     addr[i] &gt;&gt; PAGE_SHIFT, page_to_pfn(page));</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -349,6 +350,7 @@ svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start,</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;prange-&gt;child_list);</div><div class='ctx'> 	atomic_set(&amp;prange-&gt;invalid, 0);</div><div class='ctx'> 	prange-&gt;validate_timestamp = 0;</div><div class='add'>+	prange-&gt;vram_pages = 0;</div><div class='ctx'> 	mutex_init(&amp;prange-&gt;migrate_mutex);</div><div class='ctx'> 	mutex_init(&amp;prange-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -395,19 +397,16 @@ static void svm_range_bo_release(struct kref *kref)</div><div class='ctx'> 			 prange-&gt;start, prange-&gt;last);</div><div class='ctx'> 		mutex_lock(&amp;prange-&gt;lock);</div><div class='ctx'> 		prange-&gt;svm_bo = NULL;</div><div class='add'>+		/* prange should not hold vram page now */</div><div class='add'>+		WARN_ONCE(prange-&gt;actual_loc, "prange should not hold vram page");</div><div class='ctx'> 		mutex_unlock(&amp;prange-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		spin_lock(&amp;svm_bo-&gt;list_lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;svm_bo-&gt;list_lock);</div><div class='del'>-	if (!dma_fence_is_signaled(&amp;svm_bo-&gt;eviction_fence-&gt;base)) {</div><div class='del'>-		/* We're not in the eviction worker.</div><div class='del'>-		 * Signal the fence and synchronize with any</div><div class='del'>-		 * pending eviction work.</div><div class='del'>-		 */</div><div class='add'>+	if (!dma_fence_is_signaled(&amp;svm_bo-&gt;eviction_fence-&gt;base))</div><div class='add'>+		/* We're not in the eviction worker. Signal the fence. */</div><div class='ctx'> 		dma_fence_signal(&amp;svm_bo-&gt;eviction_fence-&gt;base);</div><div class='del'>-		cancel_work_sync(&amp;svm_bo-&gt;eviction_work);</div><div class='del'>-	}</div><div class='ctx'> 	dma_fence_put(&amp;svm_bo-&gt;eviction_fence-&gt;base);</div><div class='ctx'> 	amdgpu_bo_unref(&amp;svm_bo-&gt;bo);</div><div class='ctx'> 	kfree(svm_bo);</div><div class='hunk'>@@ -878,14 +877,29 @@ static void svm_range_debug_dump(struct svm_range_list *svms)</div><div class='ctx'> </div><div class='ctx'> static void *</div><div class='ctx'> svm_range_copy_array(void *psrc, size_t size, uint64_t num_elements,</div><div class='del'>-		     uint64_t offset)</div><div class='add'>+		     uint64_t offset, uint64_t *vram_pages)</div><div class='ctx'> {</div><div class='add'>+	unsigned char *src = (unsigned char *)psrc + offset;</div><div class='ctx'> 	unsigned char *dst;</div><div class='add'>+	uint64_t i;</div><div class='ctx'> </div><div class='ctx'> 	dst = kvmalloc_array(num_elements, size, GFP_KERNEL);</div><div class='ctx'> 	if (!dst)</div><div class='ctx'> 		return NULL;</div><div class='del'>-	memcpy(dst, (unsigned char *)psrc + offset, num_elements * size);</div><div class='add'>+</div><div class='add'>+	if (!vram_pages) {</div><div class='add'>+		memcpy(dst, src, num_elements * size);</div><div class='add'>+		return (void *)dst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*vram_pages = 0;</div><div class='add'>+	for (i = 0; i &lt; num_elements; i++) {</div><div class='add'>+		dma_addr_t *temp;</div><div class='add'>+		temp = (dma_addr_t *)dst + i;</div><div class='add'>+		*temp = *((dma_addr_t *)src + i);</div><div class='add'>+		if (*temp&amp;SVM_RANGE_VRAM_DOMAIN)</div><div class='add'>+			(*vram_pages)++;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return (void *)dst;</div><div class='ctx'> }</div><div class='hunk'>@@ -899,7 +913,7 @@ svm_range_copy_dma_addrs(struct svm_range *dst, struct svm_range *src)</div><div class='ctx'> 		if (!src-&gt;dma_addr[i])</div><div class='ctx'> 			continue;</div><div class='ctx'> 		dst-&gt;dma_addr[i] = svm_range_copy_array(src-&gt;dma_addr[i],</div><div class='del'>-					sizeof(*src-&gt;dma_addr[i]), src-&gt;npages, 0);</div><div class='add'>+					sizeof(*src-&gt;dma_addr[i]), src-&gt;npages, 0, NULL);</div><div class='ctx'> 		if (!dst-&gt;dma_addr[i])</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -910,7 +924,7 @@ svm_range_copy_dma_addrs(struct svm_range *dst, struct svm_range *src)</div><div class='ctx'> static int</div><div class='ctx'> svm_range_split_array(void *ppnew, void *ppold, size_t size,</div><div class='ctx'> 		      uint64_t old_start, uint64_t old_n,</div><div class='del'>-		      uint64_t new_start, uint64_t new_n)</div><div class='add'>+		      uint64_t new_start, uint64_t new_n, uint64_t *new_vram_pages)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned char *new, *old, *pold;</div><div class='ctx'> 	uint64_t d;</div><div class='hunk'>@@ -922,11 +936,12 @@ svm_range_split_array(void *ppnew, void *ppold, size_t size,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	d = (new_start - old_start) * size;</div><div class='del'>-	new = svm_range_copy_array(pold, size, new_n, d);</div><div class='add'>+	/* get dma addr array for new range and calculte its vram page number */</div><div class='add'>+	new = svm_range_copy_array(pold, size, new_n, d, new_vram_pages);</div><div class='ctx'> 	if (!new)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	d = (new_start == old_start) ? new_n * size : 0;</div><div class='del'>-	old = svm_range_copy_array(pold, size, old_n, d);</div><div class='add'>+	old = svm_range_copy_array(pold, size, old_n, d, NULL);</div><div class='ctx'> 	if (!old) {</div><div class='ctx'> 		kvfree(new);</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -948,10 +963,13 @@ svm_range_split_pages(struct svm_range *new, struct svm_range *old,</div><div class='ctx'> 	for (i = 0; i &lt; MAX_GPU_INSTANCE; i++) {</div><div class='ctx'> 		r = svm_range_split_array(&amp;new-&gt;dma_addr[i], &amp;old-&gt;dma_addr[i],</div><div class='ctx'> 					  sizeof(*old-&gt;dma_addr[i]), old-&gt;start,</div><div class='del'>-					  npages, new-&gt;start, new-&gt;npages);</div><div class='add'>+					  npages, new-&gt;start, new-&gt;npages,</div><div class='add'>+					  old-&gt;actual_loc ? &amp;new-&gt;vram_pages : NULL);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='ctx'> 	}</div><div class='add'>+	if (old-&gt;actual_loc)</div><div class='add'>+		old-&gt;vram_pages -= new-&gt;vram_pages;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1097,7 +1115,7 @@ static int</div><div class='ctx'> svm_range_split_tail(struct svm_range *prange, uint64_t new_last,</div><div class='ctx'> 		     struct list_head *insert_list, struct list_head *remap_list)</div><div class='ctx'> {</div><div class='del'>-	struct svm_range *tail;</div><div class='add'>+	struct svm_range *tail = NULL;</div><div class='ctx'> 	int r = svm_range_split(prange, prange-&gt;start, new_last, &amp;tail);</div><div class='ctx'> </div><div class='ctx'> 	if (!r) {</div><div class='hunk'>@@ -1112,7 +1130,7 @@ static int</div><div class='ctx'> svm_range_split_head(struct svm_range *prange, uint64_t new_start,</div><div class='ctx'> 		     struct list_head *insert_list, struct list_head *remap_list)</div><div class='ctx'> {</div><div class='del'>-	struct svm_range *head;</div><div class='add'>+	struct svm_range *head = NULL;</div><div class='ctx'> 	int r = svm_range_split(prange, new_start, prange-&gt;last, &amp;head);</div><div class='ctx'> </div><div class='ctx'> 	if (!r) {</div><div class='hunk'>@@ -1135,66 +1153,6 @@ svm_range_add_child(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'> 	list_add_tail(&amp;pchild-&gt;child_list, &amp;prange-&gt;child_list);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * svm_range_split_by_granularity - collect ranges within granularity boundary</div><div class='del'>- *</div><div class='del'>- * @p: the process with svms list</div><div class='del'>- * @mm: mm structure</div><div class='del'>- * @addr: the vm fault address in pages, to split the prange</div><div class='del'>- * @parent: parent range if prange is from child list</div><div class='del'>- * @prange: prange to split</div><div class='del'>- *</div><div class='del'>- * Trims @prange to be a single aligned block of prange-&gt;granularity if</div><div class='del'>- * possible. The head and tail are added to the child_list in @parent.</div><div class='del'>- *</div><div class='del'>- * Context: caller must hold mmap_read_lock and prange-&gt;lock</div><div class='del'>- *</div><div class='del'>- * Return:</div><div class='del'>- * 0 - OK, otherwise error code</div><div class='del'>- */</div><div class='del'>-int</div><div class='del'>-svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm,</div><div class='del'>-			       unsigned long addr, struct svm_range *parent,</div><div class='del'>-			       struct svm_range *prange)</div><div class='del'>-{</div><div class='del'>-	struct svm_range *head, *tail;</div><div class='del'>-	unsigned long start, last, size;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	/* Align splited range start and size to granularity size, then a single</div><div class='del'>-	 * PTE will be used for whole range, this reduces the number of PTE</div><div class='del'>-	 * updated and the L1 TLB space used for translation.</div><div class='del'>-	 */</div><div class='del'>-	size = 1UL &lt;&lt; prange-&gt;granularity;</div><div class='del'>-	start = ALIGN_DOWN(addr, size);</div><div class='del'>-	last = ALIGN(addr + 1, size) - 1;</div><div class='del'>-</div><div class='del'>-	pr_debug("svms 0x%p split [0x%lx 0x%lx] to [0x%lx 0x%lx] size 0x%lx\n",</div><div class='del'>-		 prange-&gt;svms, prange-&gt;start, prange-&gt;last, start, last, size);</div><div class='del'>-</div><div class='del'>-	if (start &gt; prange-&gt;start) {</div><div class='del'>-		r = svm_range_split(prange, start, prange-&gt;last, &amp;head);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-		svm_range_add_child(parent, mm, head, SVM_OP_ADD_RANGE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (last &lt; prange-&gt;last) {</div><div class='del'>-		r = svm_range_split(prange, prange-&gt;start, last, &amp;tail);</div><div class='del'>-		if (r)</div><div class='del'>-			return r;</div><div class='del'>-		svm_range_add_child(parent, mm, tail, SVM_OP_ADD_RANGE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* xnack on, update mapping on GPUs with ACCESS_IN_PLACE */</div><div class='del'>-	if (p-&gt;xnack_enabled &amp;&amp; prange-&gt;work_item.op == SVM_OP_ADD_RANGE) {</div><div class='del'>-		prange-&gt;work_item.op = SVM_OP_ADD_RANGE_AND_MAP;</div><div class='del'>-		pr_debug("change prange 0x%p [0x%lx 0x%lx] op %d\n",</div><div class='del'>-			 prange, prange-&gt;start, prange-&gt;last,</div><div class='del'>-			 SVM_OP_ADD_RANGE_AND_MAP);</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='ctx'> static bool</div><div class='ctx'> svm_nodes_in_same_hive(struct kfd_node *node_a, struct kfd_node *node_b)</div><div class='ctx'> {</div><div class='hunk'>@@ -1529,7 +1487,7 @@ static int svm_range_reserve_bos(struct svm_validate_context *ctx, bool intr)</div><div class='ctx'> 	uint32_t gpuidx;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;ctx-&gt;exec, intr ? DRM_EXEC_INTERRUPTIBLE_WAIT: 0);</div><div class='add'>+	drm_exec_init(&amp;ctx-&gt;exec, intr ? DRM_EXEC_INTERRUPTIBLE_WAIT: 0, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;ctx-&gt;exec) {</div><div class='ctx'> 		for_each_set_bit(gpuidx, ctx-&gt;bitmap, MAX_GPU_INSTANCE) {</div><div class='ctx'> 			pdd = kfd_process_device_from_gpuidx(ctx-&gt;process, gpuidx);</div><div class='hunk'>@@ -1614,6 +1572,7 @@ static void *kfd_svm_page_owner(struct kfd_process *p, int32_t gpuidx)</div><div class='ctx'>  * 5. Release page table (and SVM BO) reservation</div><div class='ctx'>  */</div><div class='ctx'> static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='add'>+				      unsigned long map_start, unsigned long map_last,</div><div class='ctx'> 				      struct svm_range *prange, int32_t gpuidx,</div><div class='ctx'> 				      bool intr, bool wait, bool flush_tlb)</div><div class='ctx'> {</div><div class='hunk'>@@ -1653,18 +1612,24 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 			if (test_bit(gpuidx, prange-&gt;bitmap_access))</div><div class='ctx'> 				bitmap_set(ctx-&gt;bitmap, gpuidx, 1);</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If prange is already mapped or with always mapped flag,</div><div class='add'>+		 * update mapping on GPUs with ACCESS attribute</div><div class='add'>+		 */</div><div class='add'>+		if (bitmap_empty(ctx-&gt;bitmap, MAX_GPU_INSTANCE)) {</div><div class='add'>+			if (prange-&gt;mapped_to_gpu ||</div><div class='add'>+			    prange-&gt;flags &amp; KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED)</div><div class='add'>+				bitmap_copy(ctx-&gt;bitmap, prange-&gt;bitmap_access, MAX_GPU_INSTANCE);</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		bitmap_or(ctx-&gt;bitmap, prange-&gt;bitmap_access,</div><div class='ctx'> 			  prange-&gt;bitmap_aip, MAX_GPU_INSTANCE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (bitmap_empty(ctx-&gt;bitmap, MAX_GPU_INSTANCE)) {</div><div class='del'>-		bitmap_copy(ctx-&gt;bitmap, prange-&gt;bitmap_access, MAX_GPU_INSTANCE);</div><div class='del'>-		if (!prange-&gt;mapped_to_gpu ||</div><div class='del'>-		    bitmap_empty(ctx-&gt;bitmap, MAX_GPU_INSTANCE)) {</div><div class='del'>-			r = 0;</div><div class='del'>-			goto free_ctx;</div><div class='del'>-		}</div><div class='add'>+		r = 0;</div><div class='add'>+		goto free_ctx;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (prange-&gt;actual_loc &amp;&amp; !prange-&gt;ttm_res) {</div><div class='hunk'>@@ -1688,10 +1653,12 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	start = prange-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='del'>-	end = (prange-&gt;last + 1) &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	start = map_start &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	end = (map_last + 1) &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	for (addr = start; !r &amp;&amp; addr &lt; end; ) {</div><div class='ctx'> 		struct hmm_range *hmm_range;</div><div class='add'>+		unsigned long map_start_vma;</div><div class='add'>+		unsigned long map_last_vma;</div><div class='ctx'> 		struct vm_area_struct *vma;</div><div class='ctx'> 		unsigned long next = 0;</div><div class='ctx'> 		unsigned long offset;</div><div class='hunk'>@@ -1719,7 +1686,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!r) {</div><div class='del'>-			offset = (addr - start) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+			offset = (addr &gt;&gt; PAGE_SHIFT) - prange-&gt;start;</div><div class='ctx'> 			r = svm_range_dma_map(prange, ctx-&gt;bitmap, offset, npages,</div><div class='ctx'> 					      hmm_range-&gt;hmm_pfns);</div><div class='ctx'> 			if (r)</div><div class='hunk'>@@ -1737,9 +1704,16 @@ static int svm_range_validate_and_map(struct mm_struct *mm,</div><div class='ctx'> 			r = -EAGAIN;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!r)</div><div class='del'>-			r = svm_range_map_to_gpus(prange, offset, npages, readonly,</div><div class='del'>-						  ctx-&gt;bitmap, wait, flush_tlb);</div><div class='add'>+		if (!r) {</div><div class='add'>+			map_start_vma = max(map_start, prange-&gt;start + offset);</div><div class='add'>+			map_last_vma = min(map_last, prange-&gt;start + offset + npages - 1);</div><div class='add'>+			if (map_start_vma &lt;= map_last_vma) {</div><div class='add'>+				offset = map_start_vma - prange-&gt;start;</div><div class='add'>+				npages = map_last_vma - map_start_vma + 1;</div><div class='add'>+				r = svm_range_map_to_gpus(prange, offset, npages, readonly,</div><div class='add'>+							  ctx-&gt;bitmap, wait, flush_tlb);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!r &amp;&amp; next == end)</div><div class='ctx'> 			prange-&gt;mapped_to_gpu = true;</div><div class='hunk'>@@ -1832,8 +1806,8 @@ static void svm_range_restore_work(struct work_struct *work)</div><div class='ctx'> 		 */</div><div class='ctx'> 		mutex_lock(&amp;prange-&gt;migrate_mutex);</div><div class='ctx'> </div><div class='del'>-		r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,</div><div class='del'>-					       false, true, false);</div><div class='add'>+		r = svm_range_validate_and_map(mm, prange-&gt;start, prange-&gt;last, prange,</div><div class='add'>+					       MAX_GPU_INSTANCE, false, true, false);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			pr_debug("failed %d to map 0x%lx to gpus\n", r,</div><div class='ctx'> 				 prange-&gt;start);</div><div class='hunk'>@@ -1870,7 +1844,7 @@ out_reschedule:</div><div class='ctx'> 	/* If validation failed, reschedule another attempt */</div><div class='ctx'> 	if (evicted_ranges) {</div><div class='ctx'> 		pr_debug("reschedule to restore svm range\n");</div><div class='del'>-		schedule_delayed_work(&amp;svms-&gt;restore_work,</div><div class='add'>+		queue_delayed_work(system_freezable_wq, &amp;svms-&gt;restore_work,</div><div class='ctx'> 			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));</div><div class='ctx'> </div><div class='ctx'> 		kfd_smi_event_queue_restore_rescheduled(mm);</div><div class='hunk'>@@ -1946,7 +1920,7 @@ svm_range_evict(struct svm_range *prange, struct mm_struct *mm,</div><div class='ctx'> 			pr_debug("failed to quiesce KFD\n");</div><div class='ctx'> </div><div class='ctx'> 		pr_debug("schedule to restore svm %p ranges\n", svms);</div><div class='del'>-		schedule_delayed_work(&amp;svms-&gt;restore_work,</div><div class='add'>+		queue_delayed_work(system_freezable_wq, &amp;svms-&gt;restore_work,</div><div class='ctx'> 			msecs_to_jiffies(AMDGPU_SVM_RANGE_RESTORE_DELAY_MS));</div><div class='ctx'> 	} else {</div><div class='ctx'> 		unsigned long s, l;</div><div class='hunk'>@@ -2001,6 +1975,7 @@ static struct svm_range *svm_range_clone(struct svm_range *old)</div><div class='ctx'> 	new-&gt;actual_loc = old-&gt;actual_loc;</div><div class='ctx'> 	new-&gt;granularity = old-&gt;granularity;</div><div class='ctx'> 	new-&gt;mapped_to_gpu = old-&gt;mapped_to_gpu;</div><div class='add'>+	new-&gt;vram_pages = old-&gt;vram_pages;</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_access, old-&gt;bitmap_access, MAX_GPU_INSTANCE);</div><div class='ctx'> 	bitmap_copy(new-&gt;bitmap_aip, old-&gt;bitmap_aip, MAX_GPU_INSTANCE);</div><div class='ctx'> </div><div class='hunk'>@@ -2365,8 +2340,10 @@ retry:</div><div class='ctx'> 		mutex_unlock(&amp;svms-&gt;lock);</div><div class='ctx'> 		mmap_write_unlock(mm);</div><div class='ctx'> </div><div class='del'>-		/* Pairs with mmget in svm_range_add_list_work */</div><div class='del'>-		mmput(mm);</div><div class='add'>+		/* Pairs with mmget in svm_range_add_list_work. If dropping the</div><div class='add'>+		 * last mm refcount, schedule release work to avoid circular locking</div><div class='add'>+		 */</div><div class='add'>+		mmput_async(mm);</div><div class='ctx'> </div><div class='ctx'> 		spin_lock(&amp;svms-&gt;deferred_list_lock);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2677,6 +2654,7 @@ svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr,</div><div class='ctx'> {</div><div class='ctx'> 	struct vm_area_struct *vma;</div><div class='ctx'> 	struct interval_tree_node *node;</div><div class='add'>+	struct rb_node *rb_node;</div><div class='ctx'> 	unsigned long start_limit, end_limit;</div><div class='ctx'> </div><div class='ctx'> 	vma = vma_lookup(p-&gt;mm, addr &lt;&lt; PAGE_SHIFT);</div><div class='hunk'>@@ -2696,16 +2674,15 @@ svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr,</div><div class='ctx'> 	if (node) {</div><div class='ctx'> 		end_limit = min(end_limit, node-&gt;start);</div><div class='ctx'> 		/* Last range that ends before the fault address */</div><div class='del'>-		node = container_of(rb_prev(&amp;node-&gt;rb),</div><div class='del'>-				    struct interval_tree_node, rb);</div><div class='add'>+		rb_node = rb_prev(&amp;node-&gt;rb);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Last range must end before addr because</div><div class='ctx'> 		 * there was no range after addr</div><div class='ctx'> 		 */</div><div class='del'>-		node = container_of(rb_last(&amp;p-&gt;svms.objects.rb_root),</div><div class='del'>-				    struct interval_tree_node, rb);</div><div class='add'>+		rb_node = rb_last(&amp;p-&gt;svms.objects.rb_root);</div><div class='ctx'> 	}</div><div class='del'>-	if (node) {</div><div class='add'>+	if (rb_node) {</div><div class='add'>+		node = container_of(rb_node, struct interval_tree_node, rb);</div><div class='ctx'> 		if (node-&gt;last &gt;= addr) {</div><div class='ctx'> 			WARN(1, "Overlap with prev node and page fault addr\n");</div><div class='ctx'> 			return -EFAULT;</div><div class='hunk'>@@ -2908,6 +2885,7 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 			uint32_t vmid, uint32_t node_id,</div><div class='ctx'> 			uint64_t addr, bool write_fault)</div><div class='ctx'> {</div><div class='add'>+	unsigned long start, last, size;</div><div class='ctx'> 	struct mm_struct *mm = NULL;</div><div class='ctx'> 	struct svm_range_list *svms;</div><div class='ctx'> 	struct svm_range *prange;</div><div class='hunk'>@@ -3043,40 +3021,44 @@ retry_write_locked:</div><div class='ctx'> 	kfd_smi_event_page_fault_start(node, p-&gt;lead_thread-&gt;pid, addr,</div><div class='ctx'> 				       write_fault, timestamp);</div><div class='ctx'> </div><div class='del'>-	if (prange-&gt;actual_loc != best_loc) {</div><div class='add'>+	/* Align migration range start and size to granularity size */</div><div class='add'>+	size = 1UL &lt;&lt; prange-&gt;granularity;</div><div class='add'>+	start = max_t(unsigned long, ALIGN_DOWN(addr, size), prange-&gt;start);</div><div class='add'>+	last = min_t(unsigned long, ALIGN(addr + 1, size) - 1, prange-&gt;last);</div><div class='add'>+	if (prange-&gt;actual_loc != 0 || best_loc != 0) {</div><div class='ctx'> 		migration = true;</div><div class='add'>+</div><div class='ctx'> 		if (best_loc) {</div><div class='del'>-			r = svm_migrate_to_vram(prange, best_loc, mm,</div><div class='del'>-					KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);</div><div class='add'>+			r = svm_migrate_to_vram(prange, best_loc, start, last,</div><div class='add'>+					mm, KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU);</div><div class='ctx'> 			if (r) {</div><div class='ctx'> 				pr_debug("svm_migrate_to_vram failed (%d) at %llx, falling back to system memory\n",</div><div class='ctx'> 					 r, addr);</div><div class='ctx'> 				/* Fallback to system memory if migration to</div><div class='ctx'> 				 * VRAM failed</div><div class='ctx'> 				 */</div><div class='del'>-				if (prange-&gt;actual_loc)</div><div class='del'>-					r = svm_migrate_vram_to_ram(prange, mm,</div><div class='del'>-					   KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU,</div><div class='del'>-					   NULL);</div><div class='add'>+				if (prange-&gt;actual_loc &amp;&amp; prange-&gt;actual_loc != best_loc)</div><div class='add'>+					r = svm_migrate_vram_to_ram(prange, mm, start, last,</div><div class='add'>+						KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, NULL);</div><div class='ctx'> 				else</div><div class='ctx'> 					r = 0;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			r = svm_migrate_vram_to_ram(prange, mm,</div><div class='del'>-					KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU,</div><div class='del'>-					NULL);</div><div class='add'>+			r = svm_migrate_vram_to_ram(prange, mm, start, last,</div><div class='add'>+					KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, NULL);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			pr_debug("failed %d to migrate svms %p [0x%lx 0x%lx]\n",</div><div class='del'>-				 r, svms, prange-&gt;start, prange-&gt;last);</div><div class='add'>+				 r, svms, start, last);</div><div class='ctx'> 			goto out_unlock_range;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = svm_range_validate_and_map(mm, prange, gpuidx, false, false, false);</div><div class='add'>+	r = svm_range_validate_and_map(mm, start, last, prange, gpuidx, false,</div><div class='add'>+				       false, false);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		pr_debug("failed %d to map svms 0x%p [0x%lx 0x%lx] to gpus\n",</div><div class='del'>-			 r, svms, prange-&gt;start, prange-&gt;last);</div><div class='add'>+			 r, svms, start, last);</div><div class='ctx'> </div><div class='ctx'> 	kfd_smi_event_page_fault_end(node, p-&gt;lead_thread-&gt;pid, addr,</div><div class='ctx'> 				     migration);</div><div class='hunk'>@@ -3422,18 +3404,24 @@ svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> 	*migrated = false;</div><div class='ctx'> 	best_loc = svm_range_best_prefetch_location(prange);</div><div class='ctx'> </div><div class='del'>-	if (best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED ||</div><div class='del'>-	    best_loc == prange-&gt;actual_loc)</div><div class='add'>+	/* when best_loc is a gpu node and same as prange-&gt;actual_loc</div><div class='add'>+	 * we still need do migration as prange-&gt;actual_loc !=0 does</div><div class='add'>+	 * not mean all pages in prange are vram. hmm migrate will pick</div><div class='add'>+	 * up right pages during migration.</div><div class='add'>+	 */</div><div class='add'>+	if ((best_loc == KFD_IOCTL_SVM_LOCATION_UNDEFINED) ||</div><div class='add'>+	    (best_loc == 0 &amp;&amp; prange-&gt;actual_loc == 0))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!best_loc) {</div><div class='del'>-		r = svm_migrate_vram_to_ram(prange, mm,</div><div class='add'>+		r = svm_migrate_vram_to_ram(prange, mm, prange-&gt;start, prange-&gt;last,</div><div class='ctx'> 					KFD_MIGRATE_TRIGGER_PREFETCH, NULL);</div><div class='ctx'> 		*migrated = !r;</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = svm_migrate_to_vram(prange, best_loc, mm, KFD_MIGRATE_TRIGGER_PREFETCH);</div><div class='add'>+	r = svm_migrate_to_vram(prange, best_loc, prange-&gt;start, prange-&gt;last,</div><div class='add'>+				mm, KFD_MIGRATE_TRIGGER_PREFETCH);</div><div class='ctx'> 	*migrated = !r;</div><div class='ctx'> </div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -3441,13 +3429,14 @@ svm_range_trigger_migration(struct mm_struct *mm, struct svm_range *prange,</div><div class='ctx'> </div><div class='ctx'> int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence)</div><div class='ctx'> {</div><div class='del'>-	if (!fence)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if (dma_fence_is_signaled(&amp;fence-&gt;base))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (fence-&gt;svm_bo) {</div><div class='add'>+	/* Dereferencing fence-&gt;svm_bo is safe here because the fence hasn't</div><div class='add'>+	 * signaled yet and we're under the protection of the fence-&gt;lock.</div><div class='add'>+	 * After the fence is signaled in svm_range_bo_release, we cannot get</div><div class='add'>+	 * here any more.</div><div class='add'>+	 *</div><div class='add'>+	 * Reference is dropped in svm_range_evict_svm_bo_worker.</div><div class='add'>+	 */</div><div class='add'>+	if (svm_bo_ref_unless_zero(fence-&gt;svm_bo)) {</div><div class='ctx'> 		WRITE_ONCE(fence-&gt;svm_bo-&gt;evicting, 1);</div><div class='ctx'> 		schedule_work(&amp;fence-&gt;svm_bo-&gt;eviction_work);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3462,8 +3451,6 @@ static void svm_range_evict_svm_bo_worker(struct work_struct *work)</div><div class='ctx'> 	int r = 0;</div><div class='ctx'> </div><div class='ctx'> 	svm_bo = container_of(work, struct svm_range_bo, eviction_work);</div><div class='del'>-	if (!svm_bo_ref_unless_zero(svm_bo))</div><div class='del'>-		return; /* svm_bo was freed while eviction was pending */</div><div class='ctx'> </div><div class='ctx'> 	if (mmget_not_zero(svm_bo-&gt;eviction_fence-&gt;mm)) {</div><div class='ctx'> 		mm = svm_bo-&gt;eviction_fence-&gt;mm;</div><div class='hunk'>@@ -3488,7 +3475,11 @@ static void svm_range_evict_svm_bo_worker(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;prange-&gt;migrate_mutex);</div><div class='ctx'> 		do {</div><div class='add'>+			/* migrate all vram pages in this prange to sys ram</div><div class='add'>+			 * after that prange-&gt;actual_loc should be zero</div><div class='add'>+			 */</div><div class='ctx'> 			r = svm_migrate_vram_to_ram(prange, mm,</div><div class='add'>+					prange-&gt;start, prange-&gt;last,</div><div class='ctx'> 					KFD_MIGRATE_TRIGGER_TTM_EVICTION, NULL);</div><div class='ctx'> 		} while (!r &amp;&amp; prange-&gt;actual_loc &amp;&amp; --retries);</div><div class='ctx'> </div><div class='hunk'>@@ -3612,8 +3603,8 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm,</div><div class='ctx'> </div><div class='ctx'> 		flush_tlb = !migrated &amp;&amp; update_mapping &amp;&amp; prange-&gt;mapped_to_gpu;</div><div class='ctx'> </div><div class='del'>-		r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,</div><div class='del'>-					       true, true, flush_tlb);</div><div class='add'>+		r = svm_range_validate_and_map(mm, prange-&gt;start, prange-&gt;last, prange,</div><div class='add'>+					       MAX_GPU_INSTANCE, true, true, flush_tlb);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			pr_debug("failed %d to map svm range\n", r);</div><div class='ctx'> </div><div class='hunk'>@@ -3627,8 +3618,8 @@ out_unlock_range:</div><div class='ctx'> 		pr_debug("Remapping prange 0x%p [0x%lx 0x%lx]\n",</div><div class='ctx'> 			 prange, prange-&gt;start, prange-&gt;last);</div><div class='ctx'> 		mutex_lock(&amp;prange-&gt;migrate_mutex);</div><div class='del'>-		r = svm_range_validate_and_map(mm, prange, MAX_GPU_INSTANCE,</div><div class='del'>-					       true, true, prange-&gt;mapped_to_gpu);</div><div class='add'>+		r = svm_range_validate_and_map(mm,  prange-&gt;start, prange-&gt;last, prange,</div><div class='add'>+					       MAX_GPU_INSTANCE, true, true, prange-&gt;mapped_to_gpu);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			pr_debug("failed %d on remap svm range\n", r);</div><div class='ctx'> 		mutex_unlock(&amp;prange-&gt;migrate_mutex);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h<br/>index c528df1d0ba2..026863a0abcd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_svm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_svm.h</a></div><div class='hunk'>@@ -78,6 +78,7 @@ struct svm_work_list_item {</div><div class='ctx'>  * @update_list:link list node used to add to update_list</div><div class='ctx'>  * @mapping:    bo_va mapping structure to create and update GPU page table</div><div class='ctx'>  * @npages:     number of pages</div><div class='add'>+ * @vram_pages: vram pages number in this svm_range</div><div class='ctx'>  * @dma_addr:   dma mapping address on each GPU for system memory physical page</div><div class='ctx'>  * @ttm_res:    vram ttm resource map</div><div class='ctx'>  * @offset:     range start offset within mm_nodes</div><div class='hunk'>@@ -88,7 +89,9 @@ struct svm_work_list_item {</div><div class='ctx'>  * @flags:      flags defined as KFD_IOCTL_SVM_FLAG_*</div><div class='ctx'>  * @perferred_loc: perferred location, 0 for CPU, or GPU id</div><div class='ctx'>  * @perfetch_loc: last prefetch location, 0 for CPU, or GPU id</div><div class='del'>- * @actual_loc: the actual location, 0 for CPU, or GPU id</div><div class='add'>+ * @actual_loc: this svm_range location. 0: all pages are from sys ram;</div><div class='add'>+ *              GPU id: this svm_range may include vram pages from GPU with</div><div class='add'>+ *              id actual_loc.</div><div class='ctx'>  * @granularity:migration granularity, log2 num pages</div><div class='ctx'>  * @invalid:    not 0 means cpu page table is invalidated</div><div class='ctx'>  * @validate_timestamp: system timestamp when range is validated</div><div class='hunk'>@@ -112,6 +115,7 @@ struct svm_range {</div><div class='ctx'> 	struct list_head		list;</div><div class='ctx'> 	struct list_head		update_list;</div><div class='ctx'> 	uint64_t			npages;</div><div class='add'>+	uint64_t			vram_pages;</div><div class='ctx'> 	dma_addr_t			*dma_addr[MAX_GPU_INSTANCE];</div><div class='ctx'> 	struct ttm_resource		*ttm_res;</div><div class='ctx'> 	uint64_t			offset;</div><div class='hunk'>@@ -168,9 +172,6 @@ struct kfd_node *svm_range_get_node_by_id(struct svm_range *prange,</div><div class='ctx'> int svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,</div><div class='ctx'> 			    bool clear);</div><div class='ctx'> void svm_range_vram_node_free(struct svm_range *prange);</div><div class='del'>-int svm_range_split_by_granularity(struct kfd_process *p, struct mm_struct *mm,</div><div class='del'>-			       unsigned long addr, struct svm_range *parent,</div><div class='del'>-			       struct svm_range *prange);</div><div class='ctx'> int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid,</div><div class='ctx'> 			    uint32_t vmid, uint32_t node_id, uint64_t addr,</div><div class='ctx'> 			    bool write_fault);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c<br/>index 057284bf50bb..e5f7c92eebcb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/amdkfd/kfd_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/amdkfd/kfd_topology.c</a></div><div class='hunk'>@@ -1342,10 +1342,11 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g</div><div class='ctx'> 		num_cpu++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (list_empty(&amp;kdev-&gt;io_link_props))</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='ctx'> 	gpu_link = list_first_entry(&amp;kdev-&gt;io_link_props,</div><div class='del'>-					struct kfd_iolink_properties, list);</div><div class='del'>-	if (!gpu_link)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+				    struct kfd_iolink_properties, list);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_cpu; i++) {</div><div class='ctx'> 		/* CPU &lt;--&gt; GPU */</div><div class='hunk'>@@ -1423,15 +1424,17 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev,</div><div class='ctx'> 				peer-&gt;gpu-&gt;adev))</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	if (list_empty(&amp;kdev-&gt;io_link_props))</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='ctx'> 	iolink1 = list_first_entry(&amp;kdev-&gt;io_link_props,</div><div class='del'>-							struct kfd_iolink_properties, list);</div><div class='del'>-	if (!iolink1)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+				   struct kfd_iolink_properties, list);</div><div class='add'>+</div><div class='add'>+	if (list_empty(&amp;peer-&gt;io_link_props))</div><div class='add'>+		return -ENODATA;</div><div class='ctx'> </div><div class='ctx'> 	iolink2 = list_first_entry(&amp;peer-&gt;io_link_props,</div><div class='del'>-							struct kfd_iolink_properties, list);</div><div class='del'>-	if (!iolink2)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+				   struct kfd_iolink_properties, list);</div><div class='ctx'> </div><div class='ctx'> 	props = kfd_alloc_struct(props);</div><div class='ctx'> 	if (!props)</div><div class='hunk'>@@ -1449,17 +1452,19 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev,</div><div class='ctx'> 		/* CPU-&gt;CPU  link*/</div><div class='ctx'> 		cpu_dev = kfd_topology_device_by_proximity_domain(iolink1-&gt;node_to);</div><div class='ctx'> 		if (cpu_dev) {</div><div class='del'>-			list_for_each_entry(iolink3, &amp;cpu_dev-&gt;io_link_props, list)</div><div class='del'>-				if (iolink3-&gt;node_to == iolink2-&gt;node_to)</div><div class='del'>-					break;</div><div class='del'>-</div><div class='del'>-			props-&gt;weight += iolink3-&gt;weight;</div><div class='del'>-			props-&gt;min_latency += iolink3-&gt;min_latency;</div><div class='del'>-			props-&gt;max_latency += iolink3-&gt;max_latency;</div><div class='del'>-			props-&gt;min_bandwidth = min(props-&gt;min_bandwidth,</div><div class='del'>-							iolink3-&gt;min_bandwidth);</div><div class='del'>-			props-&gt;max_bandwidth = min(props-&gt;max_bandwidth,</div><div class='del'>-							iolink3-&gt;max_bandwidth);</div><div class='add'>+			list_for_each_entry(iolink3, &amp;cpu_dev-&gt;io_link_props, list) {</div><div class='add'>+				if (iolink3-&gt;node_to != iolink2-&gt;node_to)</div><div class='add'>+					continue;</div><div class='add'>+</div><div class='add'>+				props-&gt;weight += iolink3-&gt;weight;</div><div class='add'>+				props-&gt;min_latency += iolink3-&gt;min_latency;</div><div class='add'>+				props-&gt;max_latency += iolink3-&gt;max_latency;</div><div class='add'>+				props-&gt;min_bandwidth = min(props-&gt;min_bandwidth,</div><div class='add'>+							   iolink3-&gt;min_bandwidth);</div><div class='add'>+				props-&gt;max_bandwidth = min(props-&gt;max_bandwidth,</div><div class='add'>+							   iolink3-&gt;max_bandwidth);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 		} else {</div><div class='ctx'> 			WARN(1, "CPU node not found");</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile<br/>index af17ab8027df..92a5c5efcf92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/Makefile</a></div><div class='hunk'>@@ -30,6 +30,9 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/hw</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/clk_mgr</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/hwss</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/resource</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dsc</div><div class='add'>+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/optc</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync</div><div class='ctx'> subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile<br/>index 8bf94920d23e..ab2a97e354da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/Makefile</a></div><div class='hunk'>@@ -25,22 +25,25 @@</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> </div><div class='add'>+ifneq ($(CONFIG_DRM_AMD_DC),)</div><div class='ctx'> AMDGPUDM = \</div><div class='ctx'> 	amdgpu_dm.o \</div><div class='ctx'> 	amdgpu_dm_plane.o \</div><div class='ctx'> 	amdgpu_dm_crtc.o \</div><div class='ctx'> 	amdgpu_dm_irq.o \</div><div class='ctx'> 	amdgpu_dm_mst_types.o \</div><div class='del'>-	amdgpu_dm_color.o</div><div class='add'>+	amdgpu_dm_color.o \</div><div class='add'>+	amdgpu_dm_services.o \</div><div class='add'>+	amdgpu_dm_helpers.o \</div><div class='add'>+	amdgpu_dm_pp_smu.o \</div><div class='add'>+	amdgpu_dm_psr.o \</div><div class='add'>+	amdgpu_dm_replay.o \</div><div class='add'>+	amdgpu_dm_wb.o</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> AMDGPUDM += dc_fpu.o</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='del'>-ifneq ($(CONFIG_DRM_AMD_DC),)</div><div class='del'>-AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o amdgpu_dm_psr.o amdgpu_dm_replay.o</div><div class='del'>-endif</div><div class='del'>-</div><div class='ctx'> AMDGPUDM += amdgpu_dm_hdcp.o</div><div class='ctx'> </div><div class='ctx'> ifneq ($(CONFIG_DEBUG_FS),)</div><div class='hunk'>@@ -52,3 +55,4 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc</div><div class='ctx'> AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMDGPU_DM)</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br/>index b8c3a9b104a4..d4f525b66a09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</a></div><div class='hunk'>@@ -37,6 +37,7 @@</div><div class='ctx'> #include "dc/dc_dmub_srv.h"</div><div class='ctx'> #include "dc/dc_edid_parser.h"</div><div class='ctx'> #include "dc/dc_stat.h"</div><div class='add'>+#include "dc/dc_state.h"</div><div class='ctx'> #include "amdgpu_dm_trace.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> #include "link/protocols/link_dpcd.h"</div><div class='hunk'>@@ -54,6 +55,7 @@</div><div class='ctx'> #include "amdgpu_dm_crtc.h"</div><div class='ctx'> #include "amdgpu_dm_hdcp.h"</div><div class='ctx'> #include &lt;drm/display/drm_hdcp_helper.h&gt;</div><div class='add'>+#include "amdgpu_dm_wb.h"</div><div class='ctx'> #include "amdgpu_pm.h"</div><div class='ctx'> #include "amdgpu_atombios.h"</div><div class='ctx'> </div><div class='hunk'>@@ -65,7 +67,6 @@</div><div class='ctx'> #include "amdgpu_dm_debugfs.h"</div><div class='ctx'> #endif</div><div class='ctx'> #include "amdgpu_dm_psr.h"</div><div class='del'>-#include "amdgpu_dm_replay.h"</div><div class='ctx'> </div><div class='ctx'> #include "ivsrcid/ivsrcid_vislands30.h"</div><div class='ctx'> </div><div class='hunk'>@@ -576,6 +577,7 @@ static void dm_crtc_high_irq(void *interrupt_params)</div><div class='ctx'> {</div><div class='ctx'> 	struct common_irq_params *irq_params = interrupt_params;</div><div class='ctx'> 	struct amdgpu_device *adev = irq_params-&gt;adev;</div><div class='add'>+	struct drm_writeback_job *job;</div><div class='ctx'> 	struct amdgpu_crtc *acrtc;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	int vrr_active;</div><div class='hunk'>@@ -584,6 +586,33 @@ static void dm_crtc_high_irq(void *interrupt_params)</div><div class='ctx'> 	if (!acrtc)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (acrtc-&gt;wb_pending) {</div><div class='add'>+		if (acrtc-&gt;wb_conn) {</div><div class='add'>+			spin_lock_irqsave(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='add'>+			job = list_first_entry_or_null(&amp;acrtc-&gt;wb_conn-&gt;job_queue,</div><div class='add'>+						       struct drm_writeback_job,</div><div class='add'>+						       list_entry);</div><div class='add'>+			spin_unlock_irqrestore(&amp;acrtc-&gt;wb_conn-&gt;job_lock, flags);</div><div class='add'>+</div><div class='add'>+			if (job) {</div><div class='add'>+				unsigned int v_total, refresh_hz;</div><div class='add'>+				struct dc_stream_state *stream = acrtc-&gt;dm_irq_params.stream;</div><div class='add'>+</div><div class='add'>+				v_total = stream-&gt;adjust.v_total_max ?</div><div class='add'>+					  stream-&gt;adjust.v_total_max : stream-&gt;timing.v_total;</div><div class='add'>+				refresh_hz = div_u64((uint64_t) stream-&gt;timing.pix_clk_100hz *</div><div class='add'>+					     100LL, (v_total * stream-&gt;timing.h_total));</div><div class='add'>+				mdelay(1000 / refresh_hz);</div><div class='add'>+</div><div class='add'>+				drm_writeback_signal_completion(acrtc-&gt;wb_conn, 0);</div><div class='add'>+				dc_stream_fc_disable_writeback(adev-&gt;dm.dc,</div><div class='add'>+							       acrtc-&gt;dm_irq_params.stream, 0);</div><div class='add'>+			}</div><div class='add'>+		} else</div><div class='add'>+			DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__);</div><div class='add'>+		acrtc-&gt;wb_pending = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg_vbl(adev_to_drm(adev),</div><div class='hunk'>@@ -726,6 +755,10 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (link &amp;&amp; aconnector-&gt;dc_link == link) {</div><div class='ctx'> 			if (notify-&gt;type == DMUB_NOTIFICATION_HPD)</div><div class='hunk'>@@ -895,8 +928,7 @@ static int dm_early_init(void *handle);</div><div class='ctx'> /* Allocate memory for FBC compressed data  */</div><div class='ctx'> static void amdgpu_dm_fbc_init(struct drm_connector *connector)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(connector-&gt;dev);</div><div class='ctx'> 	struct dm_compressor_info *compressor = &amp;adev-&gt;dm.compressor;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 	struct drm_display_mode *mode;</div><div class='hunk'>@@ -950,6 +982,10 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;conn_iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;conn_iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (aconnector-&gt;audio_inst != port)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -990,8 +1026,7 @@ static int amdgpu_dm_audio_component_bind(struct device *kdev,</div><div class='ctx'> static void amdgpu_dm_audio_component_unbind(struct device *kdev,</div><div class='ctx'> 					  struct device *hda_kdev, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = dev_get_drvdata(kdev);</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));</div><div class='ctx'> 	struct drm_audio_component *acomp = data;</div><div class='ctx'> </div><div class='ctx'> 	acomp-&gt;ops = NULL;</div><div class='hunk'>@@ -1259,7 +1294,9 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_</div><div class='ctx'> 	/* AGP aperture is disabled */</div><div class='ctx'> 	if (agp_bot &gt; agp_top) {</div><div class='ctx'> 		logical_addr_low = adev-&gt;gmc.fb_start &gt;&gt; 18;</div><div class='del'>-		if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+		if (adev-&gt;apu_flags &amp; (AMD_APU_IS_RAVEN2 |</div><div class='add'>+				       AMD_APU_IS_RENOIR |</div><div class='add'>+				       AMD_APU_IS_GREEN_SARDINE))</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Raven2 has a HW issue that it is unable to use the vram which</div><div class='ctx'> 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the</div><div class='hunk'>@@ -1271,7 +1308,9 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_</div><div class='ctx'> 			logical_addr_high = adev-&gt;gmc.fb_end &gt;&gt; 18;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		logical_addr_low = min(adev-&gt;gmc.fb_start, adev-&gt;gmc.agp_start) &gt;&gt; 18;</div><div class='del'>-		if (adev-&gt;apu_flags &amp; AMD_APU_IS_RAVEN2)</div><div class='add'>+		if (adev-&gt;apu_flags &amp; (AMD_APU_IS_RAVEN2 |</div><div class='add'>+				       AMD_APU_IS_RENOIR |</div><div class='add'>+				       AMD_APU_IS_GREEN_SARDINE))</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * Raven2 has a HW issue that it is unable to use the vram which</div><div class='ctx'> 			 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the</div><div class='hunk'>@@ -1676,6 +1715,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	init_data.nbio_reg_offsets = adev-&gt;reg_offset[NBIO_HWIP][0];</div><div class='ctx'> 	init_data.clk_reg_offsets = adev-&gt;reg_offset[CLK_HWIP][0];</div><div class='ctx'> </div><div class='add'>+	init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;</div><div class='add'>+</div><div class='add'>+	/* Enable DWB for tested platforms only */</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(3, 0, 0))</div><div class='add'>+		init_data.num_virtual_links = 1;</div><div class='add'>+</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;adev-&gt;dm.da_list);</div><div class='ctx'> </div><div class='ctx'> 	retrieve_dmi_info(&amp;adev-&gt;dm);</div><div class='hunk'>@@ -1718,23 +1763,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div><div class='ctx'> 	/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */</div><div class='ctx'> 	adev-&gt;dm.dc-&gt;debug.ignore_cable_id = true;</div><div class='ctx'> </div><div class='del'>-	/* TODO: There is a new drm mst change where the freedom of</div><div class='del'>-	 * vc_next_start_slot update is revoked/moved into drm, instead of in</div><div class='del'>-	 * driver. This forces us to make sure to get vc_next_start_slot updated</div><div class='del'>-	 * in drm function each time without considering if mst_state is active</div><div class='del'>-	 * or not. Otherwise, next time hotplug will give wrong start_slot</div><div class='del'>-	 * number. We are implementing a temporary solution to even notify drm</div><div class='del'>-	 * mst deallocation when link is no longer of MST type when uncommitting</div><div class='del'>-	 * the stream so we will have more time to work on a proper solution.</div><div class='del'>-	 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we</div><div class='del'>-	 * should notify drm to do a complete "reset" of its states and stop</div><div class='del'>-	 * calling further drm mst functions when link is no longer of an MST</div><div class='del'>-	 * type. This could happen when we unplug an MST hubs/displays. When</div><div class='del'>-	 * uncommit stream comes later after unplug, we should just reset</div><div class='del'>-	 * hardware states only.</div><div class='del'>-	 */</div><div class='del'>-	adev-&gt;dm.dc-&gt;debug.temp_mst_deallocation_sequence = true;</div><div class='del'>-</div><div class='ctx'> 	if (adev-&gt;dm.dc-&gt;caps.dp_hdmi21_pcon_support)</div><div class='ctx'> 		DRM_INFO("DP-HDMI FRL PCON supported\n");</div><div class='ctx'> </div><div class='hunk'>@@ -2270,6 +2298,10 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (aconnector-&gt;dc_link-&gt;type == dc_connection_mst_branch &amp;&amp;</div><div class='ctx'> 		    aconnector-&gt;mst_mgr.aux) {</div><div class='hunk'>@@ -2398,6 +2430,10 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (aconnector-&gt;dc_link-&gt;type != dc_connection_mst_branch ||</div><div class='ctx'> 		    aconnector-&gt;mst_root)</div><div class='hunk'>@@ -2577,12 +2613,10 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	memset(del_streams, 0, sizeof(del_streams));</div><div class='ctx'> </div><div class='del'>-	context = dc_create_state(dc);</div><div class='add'>+	context = dc_state_create_current_copy(dc);</div><div class='ctx'> 	if (context == NULL)</div><div class='ctx'> 		goto context_alloc_fail;</div><div class='ctx'> </div><div class='del'>-	dc_resource_state_copy_construct_current(dc, context);</div><div class='del'>-</div><div class='ctx'> 	/* First remove from context all streams */</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='hunk'>@@ -2592,12 +2626,12 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	/* Remove all planes for removed streams and then remove the streams */</div><div class='ctx'> 	for (i = 0; i &lt; del_streams_count; i++) {</div><div class='del'>-		if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {</div><div class='add'>+		if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {</div><div class='ctx'> 			res = DC_FAIL_DETACH_SURFACES;</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);</div><div class='add'>+		res = dc_state_remove_stream(dc, context, del_streams[i]);</div><div class='ctx'> 		if (res != DC_OK)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2605,7 +2639,7 @@ static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)</div><div class='ctx'> 	res = dc_commit_streams(dc, context-&gt;streams, context-&gt;stream_count);</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	dc_release_state(context);</div><div class='add'>+	dc_state_release(context);</div><div class='ctx'> </div><div class='ctx'> context_alloc_fail:</div><div class='ctx'> 	return res;</div><div class='hunk'>@@ -2632,7 +2666,7 @@ static int dm_suspend(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		dc_allow_idle_optimizations(adev-&gt;dm.dc, false);</div><div class='ctx'> </div><div class='del'>-		dm-&gt;cached_dc_state = dc_copy_state(dm-&gt;dc-&gt;current_state);</div><div class='add'>+		dm-&gt;cached_dc_state = dc_state_create_copy(dm-&gt;dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 		dm_gpureset_toggle_interrupts(adev, dm-&gt;cached_dc_state, false);</div><div class='ctx'> </div><div class='hunk'>@@ -2657,11 +2691,12 @@ static int dm_suspend(void *handle)</div><div class='ctx'> 	hpd_rx_irq_work_suspend(dm);</div><div class='ctx'> </div><div class='ctx'> 	dc_set_power_state(dm-&gt;dc, DC_ACPI_CM_POWER_STATE_D3);</div><div class='add'>+	dc_dmub_srv_set_power_state(dm-&gt;dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D3);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct amdgpu_dm_connector *</div><div class='add'>+struct drm_connector *</div><div class='ctx'> amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,</div><div class='ctx'> 					     struct drm_crtc *crtc)</div><div class='ctx'> {</div><div class='hunk'>@@ -2674,7 +2709,7 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,</div><div class='ctx'> 		crtc_from_state = new_con_state-&gt;crtc;</div><div class='ctx'> </div><div class='ctx'> 		if (crtc_from_state == crtc)</div><div class='del'>-			return to_amdgpu_dm_connector(connector);</div><div class='add'>+			return connector;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return NULL;</div><div class='hunk'>@@ -2825,7 +2860,7 @@ static int dm_resume(void *handle)</div><div class='ctx'> 	bool need_hotplug = false;</div><div class='ctx'> </div><div class='ctx'> 	if (dm-&gt;dc-&gt;caps.ips_support) {</div><div class='del'>-		dc_dmub_srv_exit_low_power_state(dm-&gt;dc);</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(dm-&gt;dc, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (amdgpu_in_reset(adev)) {</div><div class='hunk'>@@ -2852,6 +2887,7 @@ static int dm_resume(void *handle)</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);</div><div class='ctx'> </div><div class='add'>+		dc_dmub_srv_set_power_state(dm-&gt;dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> 		dc_set_power_state(dm-&gt;dc, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> </div><div class='ctx'> 		dc_resume(dm-&gt;dc);</div><div class='hunk'>@@ -2877,7 +2913,7 @@ static int dm_resume(void *handle)</div><div class='ctx'> </div><div class='ctx'> 		dm_gpureset_toggle_interrupts(adev, dm-&gt;cached_dc_state, true);</div><div class='ctx'> </div><div class='del'>-		dc_release_state(dm-&gt;cached_dc_state);</div><div class='add'>+		dc_state_release(dm-&gt;cached_dc_state);</div><div class='ctx'> 		dm-&gt;cached_dc_state = NULL;</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_irq_resume_late(adev);</div><div class='hunk'>@@ -2887,10 +2923,9 @@ static int dm_resume(void *handle)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Recreate dc_state - DC invalidates it when setting power state to S3. */</div><div class='del'>-	dc_release_state(dm_state-&gt;context);</div><div class='del'>-	dm_state-&gt;context = dc_create_state(dm-&gt;dc);</div><div class='add'>+	dc_state_release(dm_state-&gt;context);</div><div class='add'>+	dm_state-&gt;context = dc_state_create(dm-&gt;dc);</div><div class='ctx'> 	/* TODO: Remove dc_state-&gt;dccg, use dc-&gt;dccg directly. */</div><div class='del'>-	dc_resource_state_construct(dm-&gt;dc, dm_state-&gt;context);</div><div class='ctx'> </div><div class='ctx'> 	/* Before powering on DC we need to re-initialize DMUB. */</div><div class='ctx'> 	dm_dmub_hw_resume(adev);</div><div class='hunk'>@@ -2902,6 +2937,7 @@ static int dm_resume(void *handle)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* power on hardware */</div><div class='add'>+	dc_dmub_srv_set_power_state(dm-&gt;dc-&gt;ctx-&gt;dmub_srv, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> 	dc_set_power_state(dm-&gt;dc, DC_ACPI_CM_POWER_STATE_D0);</div><div class='ctx'> </div><div class='ctx'> 	/* program HPD filter */</div><div class='hunk'>@@ -2919,6 +2955,10 @@ static int dm_resume(void *handle)</div><div class='ctx'> 	/* Do detection*/</div><div class='ctx'> 	drm_connector_list_iter_begin(ddev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 		if (!aconnector-&gt;dc_link)</div><div class='hunk'>@@ -3492,6 +3532,9 @@ static void register_hpd_handlers(struct amdgpu_device *adev)</div><div class='ctx'> 	list_for_each_entry(connector,</div><div class='ctx'> 			&amp;dev-&gt;mode_config.connector_list, head)	{</div><div class='ctx'> </div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		dc_link = aconnector-&gt;dc_link;</div><div class='ctx'> </div><div class='hunk'>@@ -3958,7 +4001,7 @@ dm_atomic_duplicate_state(struct drm_private_obj *obj)</div><div class='ctx'> 	old_state = to_dm_atomic_state(obj-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 	if (old_state &amp;&amp; old_state-&gt;context)</div><div class='del'>-		new_state-&gt;context = dc_copy_state(old_state-&gt;context);</div><div class='add'>+		new_state-&gt;context = dc_state_create_copy(old_state-&gt;context);</div><div class='ctx'> </div><div class='ctx'> 	if (!new_state-&gt;context) {</div><div class='ctx'> 		kfree(new_state);</div><div class='hunk'>@@ -3974,7 +4017,7 @@ static void dm_atomic_destroy_state(struct drm_private_obj *obj,</div><div class='ctx'> 	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);</div><div class='ctx'> </div><div class='ctx'> 	if (dm_state &amp;&amp; dm_state-&gt;context)</div><div class='del'>-		dc_release_state(dm_state-&gt;context);</div><div class='add'>+		dc_state_release(dm_state-&gt;context);</div><div class='ctx'> </div><div class='ctx'> 	kfree(dm_state);</div><div class='ctx'> }</div><div class='hunk'>@@ -4010,14 +4053,12 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)</div><div class='ctx'> 	if (!state)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	state-&gt;context = dc_create_state(adev-&gt;dm.dc);</div><div class='add'>+	state-&gt;context = dc_state_create_current_copy(adev-&gt;dm.dc);</div><div class='ctx'> 	if (!state-&gt;context) {</div><div class='ctx'> 		kfree(state);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dc_resource_state_copy_construct_current(adev-&gt;dm.dc, state-&gt;context);</div><div class='del'>-</div><div class='ctx'> 	drm_atomic_private_obj_init(adev_to_drm(adev),</div><div class='ctx'> 				    &amp;adev-&gt;dm.atomic_obj,</div><div class='ctx'> 				    &amp;state-&gt;base,</div><div class='hunk'>@@ -4025,14 +4066,19 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	r = amdgpu_display_modeset_create_props(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dc_release_state(state-&gt;context);</div><div class='add'>+		dc_state_release(state-&gt;context);</div><div class='ctx'> 		kfree(state);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+	if (amdgpu_dm_create_color_properties(adev))</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_dm_audio_init(adev);</div><div class='ctx'> 	if (r) {</div><div class='del'>-		dc_release_state(state-&gt;context);</div><div class='add'>+		dc_state_release(state-&gt;context);</div><div class='ctx'> 		kfree(state);</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4346,7 +4392,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 	enum dc_connection_type new_connection_type = dc_connection_none;</div><div class='ctx'> 	const struct dc_plane_cap *plane;</div><div class='ctx'> 	bool psr_feature_enabled = false;</div><div class='del'>-	bool replay_feature_enabled = false;</div><div class='ctx'> 	int max_overlay = dm-&gt;dc-&gt;caps.max_slave_planes;</div><div class='ctx'> </div><div class='ctx'> 	dm-&gt;display_indexes_num = dm-&gt;dc-&gt;caps.max_streams;</div><div class='hunk'>@@ -4458,20 +4503,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!(amdgpu_dc_debug_mask &amp; DC_DISABLE_REPLAY)) {</div><div class='del'>-		switch (adev-&gt;ip_versions[DCE_HWIP][0]) {</div><div class='del'>-		case IP_VERSION(3, 1, 4):</div><div class='del'>-		case IP_VERSION(3, 1, 5):</div><div class='del'>-		case IP_VERSION(3, 1, 6):</div><div class='del'>-		case IP_VERSION(3, 2, 0):</div><div class='del'>-		case IP_VERSION(3, 2, 1):</div><div class='del'>-			replay_feature_enabled = true;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			replay_feature_enabled = amdgpu_dc_feature_mask &amp; DC_REPLAY_MASK;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='ctx'> 	/* loops over all connectors on the board */</div><div class='ctx'> 	for (i = 0; i &lt; link_cnt; i++) {</div><div class='ctx'> 		struct dc_link *link = NULL;</div><div class='hunk'>@@ -4483,6 +4514,28 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		link = dc_get_link_at_index(dm-&gt;dc, i);</div><div class='add'>+</div><div class='add'>+		if (link-&gt;connector_signal == SIGNAL_TYPE_VIRTUAL) {</div><div class='add'>+			struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+			if (!wbcon) {</div><div class='add'>+				DRM_ERROR("KMS: Failed to allocate writeback connector\n");</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) {</div><div class='add'>+				DRM_ERROR("KMS: Failed to initialize writeback connector\n");</div><div class='add'>+				kfree(wbcon);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			link-&gt;psr_settings.psr_feature_enabled = false;</div><div class='add'>+			link-&gt;psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;</div><div class='add'>+</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);</div><div class='ctx'> 		if (!aconnector)</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -4501,8 +4554,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		link = dc_get_link_at_index(dm-&gt;dc, i);</div><div class='del'>-</div><div class='ctx'> 		if (!dc_link_detect_connection_type(link, &amp;new_connection_type))</div><div class='ctx'> 			DRM_ERROR("KMS: Failed to detect connector\n");</div><div class='ctx'> </div><div class='hunk'>@@ -4520,12 +4571,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)</div><div class='ctx'> 				amdgpu_dm_update_connector_after_detect(aconnector);</div><div class='ctx'> 				setup_backlight_device(dm, aconnector);</div><div class='ctx'> </div><div class='del'>-				/*</div><div class='del'>-				 * Disable psr if replay can be enabled</div><div class='del'>-				 */</div><div class='del'>-				if (replay_feature_enabled &amp;&amp; amdgpu_dm_setup_replay(link, aconnector))</div><div class='del'>-					psr_feature_enabled = false;</div><div class='del'>-</div><div class='ctx'> 				if (psr_feature_enabled)</div><div class='ctx'> 					amdgpu_dm_set_psr_caps(link);</div><div class='ctx'> </div><div class='hunk'>@@ -5107,7 +5152,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,</div><div class='ctx'> 	 * Always set input transfer function, since plane state is refreshed</div><div class='ctx'> 	 * every time.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);</div><div class='add'>+	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state,</div><div class='add'>+						plane_state,</div><div class='add'>+						dc_plane_state);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -5183,6 +5230,9 @@ static void fill_dc_dirty_rects(struct drm_plane *plane,</div><div class='ctx'> 	if (plane-&gt;type == DRM_PLANE_TYPE_CURSOR)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (new_plane_state-&gt;rotation != DRM_MODE_ROTATE_0)</div><div class='add'>+		goto ffu;</div><div class='add'>+</div><div class='ctx'> 	num_clips = drm_plane_get_damage_clips_count(new_plane_state);</div><div class='ctx'> 	clips = drm_plane_get_damage_clips(new_plane_state);</div><div class='ctx'> </div><div class='hunk'>@@ -5509,10 +5559,13 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_crtc_timing *timing_out = &amp;stream-&gt;timing;</div><div class='ctx'> 	const struct drm_display_info *info = &amp;connector-&gt;display_info;</div><div class='del'>-	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct hdmi_vendor_infoframe hv_frame;</div><div class='ctx'> 	struct hdmi_avi_infoframe avi_frame;</div><div class='ctx'> </div><div class='add'>+	if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='ctx'> 	memset(&amp;hv_frame, 0, sizeof(hv_frame));</div><div class='ctx'> 	memset(&amp;avi_frame, 0, sizeof(avi_frame));</div><div class='ctx'> </div><div class='hunk'>@@ -5525,6 +5578,7 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> 			&amp;&amp; stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A)</div><div class='ctx'> 		timing_out-&gt;pixel_encoding = PIXEL_ENCODING_YCBCR420;</div><div class='ctx'> 	else if (drm_mode_is_420_also(info, mode_in)</div><div class='add'>+			&amp;&amp; aconnector</div><div class='ctx'> 			&amp;&amp; aconnector-&gt;force_yuv420_output)</div><div class='ctx'> 		timing_out-&gt;pixel_encoding = PIXEL_ENCODING_YCBCR420;</div><div class='ctx'> 	else if ((connector-&gt;display_info.color_formats &amp; DRM_COLOR_FORMAT_YCBCR444)</div><div class='hunk'>@@ -5560,7 +5614,7 @@ static void fill_stream_properties_from_drm_display_mode(</div><div class='ctx'> 		timing_out-&gt;hdmi_vic = hv_frame.vic;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (is_freesync_video_mode(mode_in, aconnector)) {</div><div class='add'>+	if (aconnector &amp;&amp; is_freesync_video_mode(mode_in, aconnector)) {</div><div class='ctx'> 		timing_out-&gt;h_addressable = mode_in-&gt;hdisplay;</div><div class='ctx'> 		timing_out-&gt;h_total = mode_in-&gt;htotal;</div><div class='ctx'> 		timing_out-&gt;h_sync_width = mode_in-&gt;hsync_end - mode_in-&gt;hsync_start;</div><div class='hunk'>@@ -5681,13 +5735,13 @@ decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct dc_sink *</div><div class='del'>-create_fake_sink(struct amdgpu_dm_connector *aconnector)</div><div class='add'>+create_fake_sink(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_sink_init_data sink_init_data = { 0 };</div><div class='ctx'> 	struct dc_sink *sink = NULL;</div><div class='ctx'> </div><div class='del'>-	sink_init_data.link = aconnector-&gt;dc_link;</div><div class='del'>-	sink_init_data.sink_signal = aconnector-&gt;dc_link-&gt;connector_signal;</div><div class='add'>+	sink_init_data.link = link;</div><div class='add'>+	sink_init_data.sink_signal = link-&gt;connector_signal;</div><div class='ctx'> </div><div class='ctx'> 	sink = dc_sink_create(&amp;sink_init_data);</div><div class='ctx'> 	if (!sink) {</div><div class='hunk'>@@ -6037,14 +6091,14 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct dc_stream_state *</div><div class='del'>-create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='add'>+create_stream_for_sink(struct drm_connector *connector,</div><div class='ctx'> 		       const struct drm_display_mode *drm_mode,</div><div class='ctx'> 		       const struct dm_connector_state *dm_state,</div><div class='ctx'> 		       const struct dc_stream_state *old_stream,</div><div class='ctx'> 		       int requested_bpc)</div><div class='ctx'> {</div><div class='add'>+	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct drm_display_mode *preferred_mode = NULL;</div><div class='del'>-	struct drm_connector *drm_connector;</div><div class='ctx'> 	const struct drm_connector_state *con_state = &amp;dm_state-&gt;base;</div><div class='ctx'> 	struct dc_stream_state *stream = NULL;</div><div class='ctx'> 	struct drm_display_mode mode;</div><div class='hunk'>@@ -6058,22 +6112,35 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;</div><div class='ctx'> 	struct dsc_dec_dpcd_caps dsc_caps;</div><div class='ctx'> </div><div class='add'>+	struct dc_link *link = NULL;</div><div class='ctx'> 	struct dc_sink *sink = NULL;</div><div class='ctx'> </div><div class='ctx'> 	drm_mode_init(&amp;mode, drm_mode);</div><div class='ctx'> 	memset(&amp;saved_mode, 0, sizeof(saved_mode));</div><div class='ctx'> </div><div class='del'>-	if (aconnector == NULL) {</div><div class='del'>-		DRM_ERROR("aconnector is NULL!\n");</div><div class='add'>+	if (connector == NULL) {</div><div class='add'>+		DRM_ERROR("connector is NULL!\n");</div><div class='ctx'> 		return stream;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_connector = &amp;aconnector-&gt;base;</div><div class='add'>+	if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK) {</div><div class='add'>+		aconnector = NULL;</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+		link = aconnector-&gt;dc_link;</div><div class='add'>+	} else {</div><div class='add'>+		struct drm_writeback_connector *wbcon = NULL;</div><div class='add'>+		struct amdgpu_dm_wb_connector *dm_wbcon = NULL;</div><div class='add'>+</div><div class='add'>+		wbcon = drm_connector_to_writeback(connector);</div><div class='add'>+		dm_wbcon = to_amdgpu_dm_wb_connector(wbcon);</div><div class='add'>+		link = dm_wbcon-&gt;link;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (!aconnector-&gt;dc_sink) {</div><div class='del'>-		sink = create_fake_sink(aconnector);</div><div class='add'>+	if (!aconnector || !aconnector-&gt;dc_sink) {</div><div class='add'>+		sink = create_fake_sink(link);</div><div class='ctx'> 		if (!sink)</div><div class='ctx'> 			return stream;</div><div class='add'>+</div><div class='ctx'> 	} else {</div><div class='ctx'> 		sink = aconnector-&gt;dc_sink;</div><div class='ctx'> 		dc_sink_retain(sink);</div><div class='hunk'>@@ -6086,12 +6153,13 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 		goto finish;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* We leave this NULL for writeback connectors */</div><div class='ctx'> 	stream-&gt;dm_stream_context = aconnector;</div><div class='ctx'> </div><div class='ctx'> 	stream-&gt;timing.flags.LTE_340MCSC_SCRAMBLE =</div><div class='del'>-		drm_connector-&gt;display_info.hdmi.scdc.scrambling.low_rates;</div><div class='add'>+		connector-&gt;display_info.hdmi.scdc.scrambling.low_rates;</div><div class='ctx'> </div><div class='del'>-	list_for_each_entry(preferred_mode, &amp;aconnector-&gt;base.modes, head) {</div><div class='add'>+	list_for_each_entry(preferred_mode, &amp;connector-&gt;modes, head) {</div><div class='ctx'> 		/* Search for preferred mode */</div><div class='ctx'> 		if (preferred_mode-&gt;type &amp; DRM_MODE_TYPE_PREFERRED) {</div><div class='ctx'> 			native_mode_found = true;</div><div class='hunk'>@@ -6100,7 +6168,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!native_mode_found)</div><div class='ctx'> 		preferred_mode = list_first_entry_or_null(</div><div class='del'>-				&amp;aconnector-&gt;base.modes,</div><div class='add'>+				&amp;connector-&gt;modes,</div><div class='ctx'> 				struct drm_display_mode,</div><div class='ctx'> 				head);</div><div class='ctx'> </div><div class='hunk'>@@ -6114,7 +6182,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 		 * and the modelist may not be filled in time.</div><div class='ctx'> 		 */</div><div class='ctx'> 		DRM_DEBUG_DRIVER("No preferred mode found\n");</div><div class='del'>-	} else {</div><div class='add'>+	} else if (aconnector) {</div><div class='ctx'> 		recalculate_timing = is_freesync_video_mode(&amp;mode, aconnector);</div><div class='ctx'> 		if (recalculate_timing) {</div><div class='ctx'> 			freesync_mode = get_highest_refresh_rate_mode(aconnector, false);</div><div class='hunk'>@@ -6137,13 +6205,17 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!scale || mode_refresh != preferred_refresh)</div><div class='ctx'> 		fill_stream_properties_from_drm_display_mode(</div><div class='del'>-			stream, &amp;mode, &amp;aconnector-&gt;base, con_state, NULL,</div><div class='add'>+			stream, &amp;mode, connector, con_state, NULL,</div><div class='ctx'> 			requested_bpc);</div><div class='ctx'> 	else</div><div class='ctx'> 		fill_stream_properties_from_drm_display_mode(</div><div class='del'>-			stream, &amp;mode, &amp;aconnector-&gt;base, con_state, old_stream,</div><div class='add'>+			stream, &amp;mode, connector, con_state, old_stream,</div><div class='ctx'> 			requested_bpc);</div><div class='ctx'> </div><div class='add'>+	/* The rest isn't needed for writeback connectors */</div><div class='add'>+	if (!aconnector)</div><div class='add'>+		goto finish;</div><div class='add'>+</div><div class='ctx'> 	if (aconnector-&gt;timing_changed) {</div><div class='ctx'> 		drm_dbg(aconnector-&gt;base.dev,</div><div class='ctx'> 			"overriding timing for automated test, bpc %d, changing to %d\n",</div><div class='hunk'>@@ -6161,15 +6233,16 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> </div><div class='ctx'> 	fill_audio_info(</div><div class='ctx'> 		&amp;stream-&gt;audio_info,</div><div class='del'>-		drm_connector,</div><div class='add'>+		connector,</div><div class='ctx'> 		sink);</div><div class='ctx'> </div><div class='ctx'> 	update_stream_signal(stream, sink);</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;signal == SIGNAL_TYPE_HDMI_TYPE_A)</div><div class='ctx'> 		mod_build_hf_vsif_infopacket(stream, &amp;stream-&gt;vsp_infopacket);</div><div class='del'>-</div><div class='del'>-	if (stream-&gt;link-&gt;psr_settings.psr_feature_enabled || stream-&gt;link-&gt;replay_settings.replay_feature_enabled) {</div><div class='add'>+	else if (stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='add'>+			 stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||</div><div class='add'>+			 stream-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='ctx'> 		//</div><div class='ctx'> 		// should decide stream support vsc sdp colorimetry capability</div><div class='ctx'> 		// before building vsc info packet</div><div class='hunk'>@@ -6185,8 +6258,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 		if (stream-&gt;out_transfer_func-&gt;tf == TRANSFER_FUNCTION_GAMMA22)</div><div class='ctx'> 			tf = TRANSFER_FUNC_GAMMA_22;</div><div class='ctx'> 		mod_build_vsc_infopacket(stream, &amp;stream-&gt;vsc_infopacket, stream-&gt;output_color_space, tf);</div><div class='del'>-		aconnector-&gt;psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;</div><div class='ctx'> </div><div class='add'>+		if (stream-&gt;link-&gt;psr_settings.psr_feature_enabled)</div><div class='add'>+			aconnector-&gt;psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;</div><div class='ctx'> 	}</div><div class='ctx'> finish:</div><div class='ctx'> 	dc_sink_release(sink);</div><div class='hunk'>@@ -6268,7 +6342,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,</div><div class='ctx'> 		dm_new_state-&gt;underscan_enable = val;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	} else if (property == adev-&gt;mode_info.abm_level_property) {</div><div class='del'>-		dm_new_state-&gt;abm_level = val;</div><div class='add'>+		dm_new_state-&gt;abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -6313,7 +6387,8 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,</div><div class='ctx'> 		*val = dm_state-&gt;underscan_enable;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	} else if (property == adev-&gt;mode_info.abm_level_property) {</div><div class='del'>-		*val = dm_state-&gt;abm_level;</div><div class='add'>+		*val = (dm_state-&gt;abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?</div><div class='add'>+			dm_state-&gt;abm_level : 0;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -6386,7 +6461,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)</div><div class='ctx'> 		state-&gt;pbn = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='del'>-			state-&gt;abm_level = amdgpu_dm_abm_level;</div><div class='add'>+			state-&gt;abm_level = amdgpu_dm_abm_level ?:</div><div class='add'>+				ABM_LEVEL_IMMEDIATE_DISABLE;</div><div class='ctx'> </div><div class='ctx'> 		__drm_atomic_helper_connector_reset(connector, &amp;state-&gt;base);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -6564,7 +6640,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,</div><div class='ctx'> 	if (!dc_plane_state)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> </div><div class='del'>-	dc_state = dc_create_state(dc);</div><div class='add'>+	dc_state = dc_state_create(dc);</div><div class='ctx'> 	if (!dc_state)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> </div><div class='hunk'>@@ -6591,9 +6667,9 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,</div><div class='ctx'> 		dc_result = dc_validate_plane(dc, dc_plane_state);</div><div class='ctx'> </div><div class='ctx'> 	if (dc_result == DC_OK)</div><div class='del'>-		dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);</div><div class='add'>+		dc_result = dc_state_add_stream(dc, dc_state, stream);</div><div class='ctx'> </div><div class='del'>-	if (dc_result == DC_OK &amp;&amp; !dc_add_plane_to_context(</div><div class='add'>+	if (dc_result == DC_OK &amp;&amp; !dc_state_add_plane(</div><div class='ctx'> 						dc,</div><div class='ctx'> 						stream,</div><div class='ctx'> 						dc_plane_state,</div><div class='hunk'>@@ -6605,7 +6681,7 @@ static enum dc_status dm_validate_stream_and_context(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> cleanup:</div><div class='ctx'> 	if (dc_state)</div><div class='del'>-		dc_release_state(dc_state);</div><div class='add'>+		dc_state_release(dc_state);</div><div class='ctx'> </div><div class='ctx'> 	if (dc_plane_state)</div><div class='ctx'> 		dc_plane_state_release(dc_plane_state);</div><div class='hunk'>@@ -6627,7 +6703,7 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 	enum dc_status dc_result = DC_OK;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		stream = create_stream_for_sink(aconnector, drm_mode,</div><div class='add'>+		stream = create_stream_for_sink(connector, drm_mode,</div><div class='ctx'> 						dm_state, old_stream,</div><div class='ctx'> 						requested_bpc);</div><div class='ctx'> 		if (stream == NULL) {</div><div class='hunk'>@@ -6635,6 +6711,9 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (aconnector-&gt;base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			return stream;</div><div class='add'>+</div><div class='ctx'> 		dc_result = dc_validate_stream(adev-&gt;dm.dc, stream);</div><div class='ctx'> 		if (dc_result == DC_OK &amp;&amp; stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 			dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);</div><div class='hunk'>@@ -6910,8 +6989,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,</div><div class='ctx'> 	if (IS_ERR(mst_state))</div><div class='ctx'> 		return PTR_ERR(mst_state);</div><div class='ctx'> </div><div class='del'>-	if (!mst_state-&gt;pbn_div.full)</div><div class='del'>-		mst_state-&gt;pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector-&gt;mst_root-&gt;dc_link));</div><div class='add'>+	mst_state-&gt;pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector-&gt;mst_root-&gt;dc_link));</div><div class='ctx'> </div><div class='ctx'> 	if (!state-&gt;duplicated) {</div><div class='ctx'> 		int max_bpc = conn_state-&gt;max_requested_bpc;</div><div class='hunk'>@@ -6955,6 +7033,9 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 	for_each_new_connector_in_state(state, connector, new_con_state, i) {</div><div class='ctx'> </div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 		if (!aconnector-&gt;mst_output_port)</div><div class='hunk'>@@ -7534,7 +7615,6 @@ create_i2c(struct ddc_service *ddc_service,</div><div class='ctx'> 	if (!i2c)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	i2c-&gt;base.owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;base.class = I2C_CLASS_DDC;</div><div class='ctx'> 	i2c-&gt;base.dev.parent = &amp;adev-&gt;pdev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;base.algo = &amp;amdgpu_dm_i2c_algo;</div><div class='ctx'> 	snprintf(i2c-&gt;base.name, sizeof(i2c-&gt;base.name), "AMDGPU DM i2c hw bus %d", link_index);</div><div class='hunk'>@@ -7560,6 +7640,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	struct dc_link *link = dc_get_link_at_index(dc, link_index);</div><div class='ctx'> 	struct amdgpu_i2c_adapter *i2c;</div><div class='ctx'> </div><div class='add'>+	/* Not needed for writeback connector */</div><div class='ctx'> 	link-&gt;priv = aconnector;</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -8170,6 +8251,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 			bundle-&gt;surface_updates[planes_count].gamma = dc_plane-&gt;gamma_correction;</div><div class='ctx'> 			bundle-&gt;surface_updates[planes_count].in_transfer_func = dc_plane-&gt;in_transfer_func;</div><div class='ctx'> 			bundle-&gt;surface_updates[planes_count].gamut_remap_matrix = &amp;dc_plane-&gt;gamut_remap_matrix;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].hdr_mult = dc_plane-&gt;hdr_mult;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].func_shaper = dc_plane-&gt;in_shaper_func;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].lut3d_func = dc_plane-&gt;lut3d_func;</div><div class='add'>+			bundle-&gt;surface_updates[planes_count].blend_tf = dc_plane-&gt;blend_tf;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		amdgpu_dm_plane_fill_dc_scaling_info(dm-&gt;adev, new_plane_state,</div><div class='hunk'>@@ -8381,6 +8466,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,</div><div class='ctx'> 				&amp;acrtc_state-&gt;stream-&gt;csc_color_matrix;</div><div class='ctx'> 			bundle-&gt;stream_update.out_transfer_func =</div><div class='ctx'> 				acrtc_state-&gt;stream-&gt;out_transfer_func;</div><div class='add'>+			bundle-&gt;stream_update.lut3d_func =</div><div class='add'>+				(struct dc_3dlut *) acrtc_state-&gt;stream-&gt;lut3d_func;</div><div class='add'>+			bundle-&gt;stream_update.func_shaper =</div><div class='add'>+				(struct dc_transfer_func *) acrtc_state-&gt;stream-&gt;func_shaper;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		acrtc_state-&gt;stream-&gt;abm_level = acrtc_state-&gt;abm_level;</div><div class='hunk'>@@ -8514,6 +8603,9 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev,</div><div class='ctx'> 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> notify:</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='hunk'>@@ -8547,6 +8639,9 @@ notify:</div><div class='ctx'> 		if (!status)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;adev-&gt;dm.audio_lock);</div><div class='hunk'>@@ -8572,6 +8667,12 @@ static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_stat</div><div class='ctx'> 	stream_state-&gt;mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dm_clear_writeback(struct amdgpu_display_manager *dm,</div><div class='add'>+			      struct dm_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	dc_stream_remove_writeback(dm-&gt;dc, crtc_state-&gt;stream, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 					struct dc_state *dc_state)</div><div class='ctx'> {</div><div class='hunk'>@@ -8581,9 +8682,38 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;</div><div class='ctx'> 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;</div><div class='add'>+	struct drm_connector_state *old_con_state;</div><div class='add'>+	struct drm_connector *connector;</div><div class='ctx'> 	bool mode_set_reset_required = false;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='add'>+	/* Disable writeback */</div><div class='add'>+	for_each_old_connector_in_state(state, connector, old_con_state, i) {</div><div class='add'>+		struct dm_connector_state *dm_old_con_state;</div><div class='add'>+		struct amdgpu_crtc *acrtc;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		old_crtc_state = NULL;</div><div class='add'>+</div><div class='add'>+		dm_old_con_state = to_dm_connector_state(old_con_state);</div><div class='add'>+		if (!dm_old_con_state-&gt;base.crtc)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		acrtc = to_amdgpu_crtc(dm_old_con_state-&gt;base.crtc);</div><div class='add'>+		if (acrtc)</div><div class='add'>+			old_crtc_state = drm_atomic_get_old_crtc_state(state, &amp;acrtc-&gt;base);</div><div class='add'>+</div><div class='add'>+		if (!acrtc-&gt;wb_enabled)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='add'>+</div><div class='add'>+		dm_clear_writeback(dm, dm_old_crtc_state);</div><div class='add'>+		acrtc-&gt;wb_enabled = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,</div><div class='ctx'> 				      new_crtc_state, i) {</div><div class='ctx'> 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);</div><div class='hunk'>@@ -8708,7 +8838,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 					dc_stream_get_status(dm_new_crtc_state-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 			if (!status)</div><div class='del'>-				status = dc_stream_get_status_from_state(dc_state,</div><div class='add'>+				status = dc_state_get_stream_status(dc_state,</div><div class='ctx'> 									 dm_new_crtc_state-&gt;stream);</div><div class='ctx'> 			if (!status)</div><div class='ctx'> 				drm_err(dev,</div><div class='hunk'>@@ -8720,6 +8850,105 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dm_set_writeback(struct amdgpu_display_manager *dm,</div><div class='add'>+			      struct dm_crtc_state *crtc_state,</div><div class='add'>+			      struct drm_connector *connector,</div><div class='add'>+			      struct drm_connector_state *new_con_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);</div><div class='add'>+	struct amdgpu_device *adev = dm-&gt;adev;</div><div class='add'>+	struct amdgpu_crtc *acrtc;</div><div class='add'>+	struct dc_writeback_info *wb_info;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+	struct amdgpu_framebuffer *afb;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL);</div><div class='add'>+	if (!wb_info) {</div><div class='add'>+		DRM_ERROR("Failed to allocate wb_info\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	acrtc = to_amdgpu_crtc(wb_conn-&gt;encoder.crtc);</div><div class='add'>+	if (!acrtc) {</div><div class='add'>+		DRM_ERROR("no amdgpu_crtc found\n");</div><div class='add'>+		kfree(wb_info);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	afb = to_amdgpu_framebuffer(new_con_state-&gt;writeback_job-&gt;fb);</div><div class='add'>+	if (!afb) {</div><div class='add'>+		DRM_ERROR("No amdgpu_framebuffer found\n");</div><div class='add'>+		kfree(wb_info);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		if (dm-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream == crtc_state-&gt;stream) {</div><div class='add'>+			pipe = &amp;dm-&gt;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* fill in wb_info */</div><div class='add'>+	wb_info-&gt;wb_enabled = true;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_pipe_inst = 0;</div><div class='add'>+	wb_info-&gt;dwb_params.dwbscl_black_color = 0;</div><div class='add'>+	wb_info-&gt;dwb_params.hdr_mult = 0x1F000;</div><div class='add'>+	wb_info-&gt;dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS;</div><div class='add'>+	wb_info-&gt;dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13;</div><div class='add'>+	wb_info-&gt;dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC;</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC;</div><div class='add'>+</div><div class='add'>+	/* width &amp; height from crtc */</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.src_width = acrtc-&gt;base.mode.crtc_hdisplay;</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.src_height = acrtc-&gt;base.mode.crtc_vdisplay;</div><div class='add'>+	wb_info-&gt;dwb_params.dest_width = acrtc-&gt;base.mode.crtc_hdisplay;</div><div class='add'>+	wb_info-&gt;dwb_params.dest_height = acrtc-&gt;base.mode.crtc_vdisplay;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.crop_en = false;</div><div class='add'>+	wb_info-&gt;dwb_params.stereo_params.stereo_enabled = false;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.out_max_pix_val = 0x3ff;	// 10 bits</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.out_min_pix_val = 0;</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB;</div><div class='add'>+	wb_info-&gt;dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_params.out_format = dwb_scaler_mode_bypass444;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_params.capture_rate = dwb_capture_rate_0;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;dwb_params.scaler_taps.h_taps = 4;</div><div class='add'>+	wb_info-&gt;dwb_params.scaler_taps.v_taps = 4;</div><div class='add'>+	wb_info-&gt;dwb_params.scaler_taps.h_taps_c = 2;</div><div class='add'>+	wb_info-&gt;dwb_params.scaler_taps.v_taps_c = 2;</div><div class='add'>+	wb_info-&gt;dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING;</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;mcif_buf_params.luma_pitch = afb-&gt;base.pitches[0];</div><div class='add'>+	wb_info-&gt;mcif_buf_params.chroma_pitch = afb-&gt;base.pitches[1];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; DWB_MCIF_BUF_COUNT; i++) {</div><div class='add'>+		wb_info-&gt;mcif_buf_params.luma_address[i] = afb-&gt;address;</div><div class='add'>+		wb_info-&gt;mcif_buf_params.chroma_address[i] = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wb_info-&gt;mcif_buf_params.p_vmid = 1;</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &gt;= IP_VERSION(3, 0, 0)) {</div><div class='add'>+		wb_info-&gt;mcif_warmup_params.start_address.quad_part = afb-&gt;address;</div><div class='add'>+		wb_info-&gt;mcif_warmup_params.region_size =</div><div class='add'>+			wb_info-&gt;mcif_buf_params.luma_pitch * wb_info-&gt;dwb_params.dest_height;</div><div class='add'>+	}</div><div class='add'>+	wb_info-&gt;mcif_warmup_params.p_vmid = 1;</div><div class='add'>+	wb_info-&gt;writeback_source_plane = pipe-&gt;plane_state;</div><div class='add'>+</div><div class='add'>+	dc_stream_add_writeback(dm-&gt;dc, crtc_state-&gt;stream, wb_info);</div><div class='add'>+</div><div class='add'>+	acrtc-&gt;wb_pending = true;</div><div class='add'>+	acrtc-&gt;wb_conn = wb_conn;</div><div class='add'>+	drm_writeback_queue_job(wb_conn, new_con_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.</div><div class='ctx'>  * @state: The atomic state to commit</div><div class='hunk'>@@ -8752,7 +8981,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 			if (new_con_state-&gt;crtc &amp;&amp;</div><div class='ctx'> 				new_con_state-&gt;crtc-&gt;state-&gt;active &amp;&amp;</div><div class='ctx'> 				drm_atomic_crtc_needs_modeset(new_con_state-&gt;crtc-&gt;state)) {</div><div class='del'>-				dc_dmub_srv_exit_low_power_state(dm-&gt;dc);</div><div class='add'>+				dc_dmub_srv_apply_idle_power_optimizations(dm-&gt;dc, false);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -8770,7 +8999,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {</div><div class='ctx'> 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);</div><div class='ctx'> 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state-&gt;base.crtc);</div><div class='del'>-		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+		struct amdgpu_dm_connector *aconnector;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 		if (!adev-&gt;dm.hdcp_workqueue)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -9047,6 +9281,31 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)</div><div class='ctx'> 			amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Enable writeback */</div><div class='add'>+	for_each_new_connector_in_state(state, connector, new_con_state, i) {</div><div class='add'>+		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);</div><div class='add'>+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state-&gt;base.crtc);</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type != DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!new_con_state-&gt;writeback_job)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		new_crtc_state = drm_atomic_get_new_crtc_state(state, &amp;acrtc-&gt;base);</div><div class='add'>+</div><div class='add'>+		if (!new_crtc_state)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (acrtc-&gt;wb_enabled)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='add'>+</div><div class='add'>+		dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);</div><div class='add'>+		acrtc-&gt;wb_enabled = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Update audio instances for each connector. */</div><div class='ctx'> 	amdgpu_dm_commit_audio(dev, state);</div><div class='ctx'> </div><div class='hunk'>@@ -9164,10 +9423,15 @@ out:</div><div class='ctx'> void dm_restore_drm_connector_state(struct drm_device *dev,</div><div class='ctx'> 				    struct drm_connector *connector)</div><div class='ctx'> {</div><div class='del'>-	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct amdgpu_crtc *disconnected_acrtc;</div><div class='ctx'> 	struct dm_crtc_state *acrtc_state;</div><div class='ctx'> </div><div class='add'>+	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	aconnector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='ctx'> 	if (!aconnector-&gt;dc_sink || !connector-&gt;state || !connector-&gt;encoder)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -9244,12 +9508,16 @@ static void get_freesync_config_for_crtc(</div><div class='ctx'> 	struct dm_connector_state *new_con_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct mod_freesync_config config = {0};</div><div class='del'>-	struct amdgpu_dm_connector *aconnector =</div><div class='del'>-			to_amdgpu_dm_connector(new_con_state-&gt;base.connector);</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct drm_display_mode *mode = &amp;new_crtc_state-&gt;base.mode;</div><div class='ctx'> 	int vrefresh = drm_mode_vrefresh(mode);</div><div class='ctx'> 	bool fs_vid_mode = false;</div><div class='ctx'> </div><div class='add'>+	if (new_con_state-&gt;base.connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	aconnector = to_amdgpu_dm_connector(new_con_state-&gt;base.connector);</div><div class='add'>+</div><div class='ctx'> 	new_crtc_state-&gt;vrr_supported = new_con_state-&gt;freesync_capable &amp;&amp;</div><div class='ctx'> 					vrefresh &gt;= aconnector-&gt;min_vfreq &amp;&amp;</div><div class='ctx'> 					vrefresh &lt;= aconnector-&gt;max_vfreq;</div><div class='hunk'>@@ -9349,6 +9617,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	 * update changed items</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = NULL;</div><div class='add'>+	struct drm_connector *connector = NULL;</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector = NULL;</div><div class='ctx'> 	struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;</div><div class='ctx'> 	struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;</div><div class='hunk'>@@ -9358,15 +9627,17 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);</div><div class='ctx'> 	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);</div><div class='ctx'> 	acrtc = to_amdgpu_crtc(crtc);</div><div class='del'>-	aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);</div><div class='add'>+	connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);</div><div class='add'>+	if (connector)</div><div class='add'>+		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> </div><div class='ctx'> 	/* TODO This hack should go away */</div><div class='del'>-	if (aconnector &amp;&amp; enable) {</div><div class='add'>+	if (connector &amp;&amp; enable) {</div><div class='ctx'> 		/* Make sure fake sink is created in plug-in scenario */</div><div class='ctx'> 		drm_new_conn_state = drm_atomic_get_new_connector_state(state,</div><div class='del'>-							    &amp;aconnector-&gt;base);</div><div class='add'>+									connector);</div><div class='ctx'> 		drm_old_conn_state = drm_atomic_get_old_connector_state(state,</div><div class='del'>-							    &amp;aconnector-&gt;base);</div><div class='add'>+									connector);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(drm_new_conn_state)) {</div><div class='ctx'> 			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);</div><div class='hunk'>@@ -9492,7 +9763,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 				crtc-&gt;base.id);</div><div class='ctx'> </div><div class='ctx'> 		/* i.e. reset mode */</div><div class='del'>-		if (dc_remove_stream_from_ctx(</div><div class='add'>+		if (dc_state_remove_stream(</div><div class='ctx'> 				dm-&gt;dc,</div><div class='ctx'> 				dm_state-&gt;context,</div><div class='ctx'> 				dm_old_crtc_state-&gt;stream) != DC_OK) {</div><div class='hunk'>@@ -9513,7 +9784,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 		 * added MST connectors not found in existing crtc_state in the chained mode</div><div class='ctx'> 		 * TODO: need to dig out the root cause of that</div><div class='ctx'> 		 */</div><div class='del'>-		if (!aconnector)</div><div class='add'>+		if (!connector)</div><div class='ctx'> 			goto skip_modeset;</div><div class='ctx'> </div><div class='ctx'> 		if (modereset_required(new_crtc_state))</div><div class='hunk'>@@ -9535,7 +9806,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,</div><div class='ctx'> 			DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",</div><div class='ctx'> 					 crtc-&gt;base.id);</div><div class='ctx'> </div><div class='del'>-			if (dc_add_stream_to_ctx(</div><div class='add'>+			if (dc_state_add_stream(</div><div class='ctx'> 					dm-&gt;dc,</div><div class='ctx'> 					dm_state-&gt;context,</div><div class='ctx'> 					dm_new_crtc_state-&gt;stream) != DC_OK) {</div><div class='hunk'>@@ -9556,7 +9827,7 @@ skip_modeset:</div><div class='ctx'> 	 * We want to do dc stream updates that do not require a</div><div class='ctx'> 	 * full modeset below.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!(enable &amp;&amp; aconnector &amp;&amp; new_crtc_state-&gt;active))</div><div class='add'>+	if (!(enable &amp;&amp; connector &amp;&amp; new_crtc_state-&gt;active))</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Given above conditions, the dc state cannot be NULL because:</div><div class='hunk'>@@ -9582,6 +9853,7 @@ skip_modeset:</div><div class='ctx'> 	 * when a modeset is needed, to ensure it gets reprogrammed.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (dm_new_crtc_state-&gt;base.color_mgmt_changed ||</div><div class='add'>+	    dm_old_crtc_state-&gt;regamma_tf != dm_new_crtc_state-&gt;regamma_tf ||</div><div class='ctx'> 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {</div><div class='ctx'> 		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -9615,7 +9887,8 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> 	 * TODO: Remove this hack for all asics once it proves that the</div><div class='ctx'> 	 * fast updates works fine on DCN3.2+.</div><div class='ctx'> 	 */</div><div class='del'>-	if (adev-&gt;ip_versions[DCE_HWIP][0] &lt; IP_VERSION(3, 2, 0) &amp;&amp; state-&gt;allow_modeset)</div><div class='add'>+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) &lt; IP_VERSION(3, 2, 0) &amp;&amp;</div><div class='add'>+	    state-&gt;allow_modeset)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* Exit early if we know that we're adding or removing the plane. */</div><div class='hunk'>@@ -9649,6 +9922,10 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> 	 */</div><div class='ctx'> 	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {</div><div class='ctx'> 		struct amdgpu_framebuffer *old_afb, *new_afb;</div><div class='add'>+		struct dm_plane_state *dm_new_other_state, *dm_old_other_state;</div><div class='add'>+</div><div class='add'>+		dm_new_other_state = to_dm_plane_state(new_other_state);</div><div class='add'>+		dm_old_other_state = to_dm_plane_state(old_other_state);</div><div class='ctx'> </div><div class='ctx'> 		if (other-&gt;type == DRM_PLANE_TYPE_CURSOR)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -9685,6 +9962,18 @@ static bool should_reset_plane(struct drm_atomic_state *state,</div><div class='ctx'> 		    old_other_state-&gt;color_encoding != new_other_state-&gt;color_encoding)</div><div class='ctx'> 			return true;</div><div class='ctx'> </div><div class='add'>+		/* HDR/Transfer Function changes. */</div><div class='add'>+		if (dm_old_other_state-&gt;degamma_tf != dm_new_other_state-&gt;degamma_tf ||</div><div class='add'>+		    dm_old_other_state-&gt;degamma_lut != dm_new_other_state-&gt;degamma_lut ||</div><div class='add'>+		    dm_old_other_state-&gt;hdr_mult != dm_new_other_state-&gt;hdr_mult ||</div><div class='add'>+		    dm_old_other_state-&gt;ctm != dm_new_other_state-&gt;ctm ||</div><div class='add'>+		    dm_old_other_state-&gt;shaper_lut != dm_new_other_state-&gt;shaper_lut ||</div><div class='add'>+		    dm_old_other_state-&gt;shaper_tf != dm_new_other_state-&gt;shaper_tf ||</div><div class='add'>+		    dm_old_other_state-&gt;lut3d != dm_new_other_state-&gt;lut3d ||</div><div class='add'>+		    dm_old_other_state-&gt;blend_lut != dm_new_other_state-&gt;blend_lut ||</div><div class='add'>+		    dm_old_other_state-&gt;blend_tf != dm_new_other_state-&gt;blend_tf)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='ctx'> 		/* Framebuffer checks fall at the end. */</div><div class='ctx'> 		if (!old_other_state-&gt;fb || !new_other_state-&gt;fb)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -9839,7 +10128,7 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> </div><div class='del'>-		if (!dc_remove_plane_from_context(</div><div class='add'>+		if (!dc_state_remove_plane(</div><div class='ctx'> 				dc,</div><div class='ctx'> 				dm_old_crtc_state-&gt;stream,</div><div class='ctx'> 				dm_old_plane_state-&gt;dc_state,</div><div class='hunk'>@@ -9917,7 +10206,7 @@ static int dm_update_plane_state(struct dc *dc,</div><div class='ctx'> 		 * state. It'll be released when the atomic state is</div><div class='ctx'> 		 * cleaned.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!dc_add_plane_to_context(</div><div class='add'>+		if (!dc_state_add_plane(</div><div class='ctx'> 				dc,</div><div class='ctx'> 				dm_new_crtc_state-&gt;stream,</div><div class='ctx'> 				dc_new_plane_state,</div><div class='hunk'>@@ -10079,6 +10368,9 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm</div><div class='ctx'> 		if (conn_state-&gt;crtc != crtc)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 		if (!aconnector-&gt;mst_output_port || !aconnector-&gt;mst_root)</div><div class='ctx'> 			aconnector = NULL;</div><div class='hunk'>@@ -10598,7 +10890,7 @@ static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,</div><div class='ctx'> 	input-&gt;cea_total_length = total_length;</div><div class='ctx'> 	memcpy(input-&gt;payload, data, length);</div><div class='ctx'> </div><div class='del'>-	res = dm_execute_dmub_cmd(dm-&gt;dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='add'>+	res = dc_wake_and_execute_dmub_cmd(dm-&gt;dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='ctx'> 	if (!res) {</div><div class='ctx'> 		DRM_ERROR("EDID CEA parser failed\n");</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -10789,8 +11081,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> 	struct dm_connector_state *dm_con_state = NULL;</div><div class='ctx'> 	struct dc_sink *sink;</div><div class='ctx'> </div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(connector-&gt;dev);</div><div class='ctx'> 	struct amdgpu_hdmi_vsdb_info vsdb_info = {0};</div><div class='ctx'> 	bool freesync_capable = false;</div><div class='ctx'> 	enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h<br/>index 3d480be802cb..9c1871b866cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_plane.h&gt;</div><div class='ctx'> #include "link_service_types.h"</div><div class='add'>+#include &lt;drm/drm_writeback.h&gt;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * This file contains the definition for amdgpu_display_manager</div><div class='hunk'>@@ -54,6 +55,9 @@</div><div class='ctx'> #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A</div><div class='ctx'> #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40</div><div class='ctx'> #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3</div><div class='add'>+</div><div class='add'>+#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'> #include "include/amdgpu_dal_power_if.h"</div><div class='ctx'> #include "amdgpu_dm_irq.h"</div><div class='hunk'>@@ -714,11 +718,107 @@ static inline void amdgpu_dm_set_mst_status(uint8_t *status,</div><div class='ctx'> </div><div class='ctx'> #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)</div><div class='ctx'> </div><div class='add'>+struct amdgpu_dm_wb_connector {</div><div class='add'>+	struct drm_writeback_connector base;</div><div class='add'>+	struct dc_link *link;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)</div><div class='add'>+</div><div class='ctx'> extern const struct amdgpu_ip_block_version dm_ip_block;</div><div class='ctx'> </div><div class='add'>+/* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.</div><div class='add'>+ *</div><div class='add'>+ * It includes standardized transfer functions and pure power functions. The</div><div class='add'>+ * transfer function coefficients are available at modules/color/color_gamma.c</div><div class='add'>+ */</div><div class='add'>+enum amdgpu_transfer_function {</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_DEFAULT,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_IDENTITY,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_BT709_OETF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,</div><div class='add'>+	AMDGPU_TRANSFER_FUNCTION_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dm_plane_state {</div><div class='ctx'> 	struct drm_plane_state base;</div><div class='ctx'> 	struct dc_plane_state *dc_state;</div><div class='add'>+</div><div class='add'>+	/* Plane color mgmt */</div><div class='add'>+	/**</div><div class='add'>+	 * @degamma_lut:</div><div class='add'>+	 *</div><div class='add'>+	 * 1D LUT for mapping framebuffer/plane pixel data before sampling or</div><div class='add'>+	 * blending operations. It's usually applied to linearize input space.</div><div class='add'>+	 * The blob (if not NULL) is an array of &amp;struct drm_color_lut.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property_blob *degamma_lut;</div><div class='add'>+	/**</div><div class='add'>+	 * @degamma_tf:</div><div class='add'>+	 *</div><div class='add'>+	 * Predefined transfer function to tell DC driver the input space to</div><div class='add'>+	 * linearize.</div><div class='add'>+	 */</div><div class='add'>+	enum amdgpu_transfer_function degamma_tf;</div><div class='add'>+	/**</div><div class='add'>+	 * @hdr_mult:</div><div class='add'>+	 *</div><div class='add'>+	 * Multiplier to 'gain' the plane.  When PQ is decoded using the fixed</div><div class='add'>+	 * func transfer function to the internal FP16 fb, 1.0 -&gt; 80 nits (on</div><div class='add'>+	 * AMD at least). When sRGB is decoded, 1.0 -&gt; 1.0, obviously.</div><div class='add'>+	 * Therefore, 1.0 multiplier = 80 nits for SDR content.  So if you</div><div class='add'>+	 * want, 203 nits for SDR content, pass in (203.0 / 80.0).  Format is</div><div class='add'>+	 * S31.32 sign-magnitude.</div><div class='add'>+	 *</div><div class='add'>+	 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ</div><div class='add'>+	 * TF is needed for any subsequent linear-to-non-linear transforms.</div><div class='add'>+	 */</div><div class='add'>+	__u64 hdr_mult;</div><div class='add'>+	/**</div><div class='add'>+	 * @ctm:</div><div class='add'>+	 *</div><div class='add'>+	 * Color transformation matrix. The blob (if not NULL) is a &amp;struct</div><div class='add'>+	 * drm_color_ctm_3x4.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property_blob *ctm;</div><div class='add'>+	/**</div><div class='add'>+	 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an</div><div class='add'>+	 * array of &amp;struct drm_color_lut.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property_blob *shaper_lut;</div><div class='add'>+	/**</div><div class='add'>+	 * @shaper_tf:</div><div class='add'>+	 *</div><div class='add'>+	 * Predefined transfer function to delinearize color space.</div><div class='add'>+	 */</div><div class='add'>+	enum amdgpu_transfer_function shaper_tf;</div><div class='add'>+	/**</div><div class='add'>+	 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of</div><div class='add'>+	 * &amp;struct drm_color_lut.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property_blob *lut3d;</div><div class='add'>+	/**</div><div class='add'>+	 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an</div><div class='add'>+	 * array of &amp;struct drm_color_lut.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_property_blob *blend_lut;</div><div class='add'>+	/**</div><div class='add'>+	 * @blend_tf:</div><div class='add'>+	 *</div><div class='add'>+	 * Pre-defined transfer function for converting plane pixel data before</div><div class='add'>+	 * applying blend LUT.</div><div class='add'>+	 */</div><div class='add'>+	enum amdgpu_transfer_function blend_tf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dm_crtc_state {</div><div class='hunk'>@@ -743,6 +843,14 @@ struct dm_crtc_state {</div><div class='ctx'> 	struct dc_info_packet vrr_infopacket;</div><div class='ctx'> </div><div class='ctx'> 	int abm_level;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @regamma_tf:</div><div class='add'>+	 *</div><div class='add'>+	 * Pre-defined transfer function for converting internal FB -&gt; wire</div><div class='add'>+	 * encoding.</div><div class='add'>+	 */</div><div class='add'>+	enum amdgpu_transfer_function regamma_tf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)</div><div class='hunk'>@@ -804,14 +912,22 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);</div><div class='ctx'> </div><div class='add'>+/* 3D LUT max size is 17x17x17 (4913 entries) */</div><div class='add'>+#define MAX_COLOR_3DLUT_SIZE 17</div><div class='add'>+#define MAX_COLOR_3DLUT_BITDEPTH 12</div><div class='add'>+int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,</div><div class='add'>+				struct drm_plane_state *plane_state);</div><div class='add'>+/* 1D LUT size */</div><div class='ctx'> #define MAX_COLOR_LUT_ENTRIES 4096</div><div class='ctx'> /* Legacy gamm LUT users such as X doesn't like large LUT sizes */</div><div class='ctx'> #define MAX_COLOR_LEGACY_LUT_ENTRIES 256</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_init_color_mod(void);</div><div class='add'>+int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);</div><div class='ctx'> int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);</div><div class='ctx'> int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='add'>+				      struct drm_plane_state *plane_state,</div><div class='ctx'> 				      struct dc_plane_state *dc_plane_state);</div><div class='ctx'> </div><div class='ctx'> void amdgpu_dm_update_connector_after_detect(</div><div class='hunk'>@@ -834,7 +950,7 @@ struct dc_stream_state *</div><div class='ctx'> int dm_atomic_get_state(struct drm_atomic_state *state,</div><div class='ctx'> 			struct dm_atomic_state **dm_state);</div><div class='ctx'> </div><div class='del'>-struct amdgpu_dm_connector *</div><div class='add'>+struct drm_connector *</div><div class='ctx'> amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,</div><div class='ctx'> 					     struct drm_crtc *crtc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c<br/>index a4cb23d059bd..c87b64e464ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c</a></div><div class='hunk'>@@ -72,6 +72,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #define MAX_DRM_LUT_VALUE 0xFFFF</div><div class='add'>+#define SDR_WHITE_LEVEL_INIT_VALUE 80</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dm_init_color_mod - Initialize the color module.</div><div class='hunk'>@@ -84,6 +85,247 @@ void amdgpu_dm_init_color_mod(void)</div><div class='ctx'> 	setup_x_points_distribution();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x)</div><div class='add'>+{</div><div class='add'>+	struct fixed31_32 val;</div><div class='add'>+</div><div class='add'>+	/* If negative, convert to 2's complement. */</div><div class='add'>+	if (x &amp; (1ULL &lt;&lt; 63))</div><div class='add'>+		x = -(x &amp; ~(1ULL &lt;&lt; 63));</div><div class='add'>+</div><div class='add'>+	val.value = x;</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+/* Pre-defined Transfer Functions (TF)</div><div class='add'>+ *</div><div class='add'>+ * AMD driver supports pre-defined mathematical functions for transferring</div><div class='add'>+ * between encoded values and optical/linear space. Depending on HW color caps,</div><div class='add'>+ * ROMs and curves built by the AMD color module support these transforms.</div><div class='add'>+ *</div><div class='add'>+ * The driver-specific color implementation exposes properties for pre-blending</div><div class='add'>+ * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and</div><div class='add'>+ * post-blending regamma (mpc.ogam) TF. However, only pre-blending degamma</div><div class='add'>+ * supports ROM curves. AMD color module uses pre-defined coefficients to build</div><div class='add'>+ * curves for the other blocks. What can be done by each color block is</div><div class='add'>+ * described by struct dpp_color_capsand struct mpc_color_caps.</div><div class='add'>+ *</div><div class='add'>+ * AMD driver-specific color API exposes the following pre-defined transfer</div><div class='add'>+ * functions:</div><div class='add'>+ *</div><div class='add'>+ * - Identity: linear/identity relationship between pixel value and</div><div class='add'>+ *   luminance value;</div><div class='add'>+ * - Gamma 2.2, Gamma 2.4, Gamma 2.6: pure power functions;</div><div class='add'>+ * - sRGB: 2.4: The piece-wise transfer function from IEC 61966-2-1:1999;</div><div class='add'>+ * - BT.709: has a linear segment in the bottom part and then a power function</div><div class='add'>+ *   with a 0.45 (~1/2.22) gamma for the rest of the range; standardized by</div><div class='add'>+ *   ITU-R BT.709-6;</div><div class='add'>+ * - PQ (Perceptual Quantizer): used for HDR display, allows luminance range</div><div class='add'>+ *   capability of 0 to 10,000 nits; standardized by SMPTE ST 2084.</div><div class='add'>+ *</div><div class='add'>+ * The AMD color model is designed with an assumption that SDR (sRGB, BT.709,</div><div class='add'>+ * Gamma 2.2, etc.) peak white maps (normalized to 1.0 FP) to 80 nits in the PQ</div><div class='add'>+ * system. This has the implication that PQ EOTF (non-linear to linear) maps to</div><div class='add'>+ * [0.0..125.0] where 125.0 = 10,000 nits / 80 nits.</div><div class='add'>+ *</div><div class='add'>+ * Non-linear and linear forms are described in the table below:</div><div class='add'>+ *</div><div class='add'>+ * ┌───────────┬─────────────────────┬──────────────────────┐</div><div class='add'>+ * │           │     Non-linear      │   Linear             │</div><div class='add'>+ * ├───────────┼─────────────────────┼──────────────────────┤</div><div class='add'>+ * │      sRGB │ UNORM or [0.0, 1.0] │ [0.0, 1.0]           │</div><div class='add'>+ * ├───────────┼─────────────────────┼──────────────────────┤</div><div class='add'>+ * │     BT709 │ UNORM or [0.0, 1.0] │ [0.0, 1.0]           │</div><div class='add'>+ * ├───────────┼─────────────────────┼──────────────────────┤</div><div class='add'>+ * │ Gamma 2.x │ UNORM or [0.0, 1.0] │ [0.0, 1.0]           │</div><div class='add'>+ * ├───────────┼─────────────────────┼──────────────────────┤</div><div class='add'>+ * │        PQ │ UNORM or FP16 CCCS* │ [0.0, 125.0]         │</div><div class='add'>+ * ├───────────┼─────────────────────┼──────────────────────┤</div><div class='add'>+ * │  Identity │ UNORM or FP16 CCCS* │ [0.0, 1.0] or CCCS** │</div><div class='add'>+ * └───────────┴─────────────────────┴──────────────────────┘</div><div class='add'>+ * * CCCS: Windows canonical composition color space</div><div class='add'>+ * ** Respectively</div><div class='add'>+ *</div><div class='add'>+ * In the driver-specific API, color block names attached to TF properties</div><div class='add'>+ * suggest the intention regarding non-linear encoding pixel's luminance</div><div class='add'>+ * values. As some newer encodings don't use gamma curve, we make encoding and</div><div class='add'>+ * decoding explicit by defining an enum list of transfer functions supported</div><div class='add'>+ * in terms of EOTF and inverse EOTF, where:</div><div class='add'>+ *</div><div class='add'>+ * - EOTF (electro-optical transfer function): is the transfer function to go</div><div class='add'>+ *   from the encoded value to an optical (linear) value. De-gamma functions</div><div class='add'>+ *   traditionally do this.</div><div class='add'>+ * - Inverse EOTF (simply the inverse of the EOTF): is usually intended to go</div><div class='add'>+ *   from an optical/linear space (which might have been used for blending)</div><div class='add'>+ *   back to the encoded values. Gamma functions traditionally do this.</div><div class='add'>+ */</div><div class='add'>+static const char * const</div><div class='add'>+amdgpu_transfer_function_names[] = {</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_DEFAULT]		= "Default",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_IDENTITY]		= "Identity",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF]		= "sRGB EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF]	= "BT.709 inv_OETF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_PQ_EOTF]		= "PQ EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF]		= "Gamma 2.2 EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF]		= "Gamma 2.4 EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF]		= "Gamma 2.6 EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF]	= "sRGB inv_EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_BT709_OETF]		= "BT.709 OETF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF]		= "PQ inv_EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF]	= "Gamma 2.2 inv_EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF]	= "Gamma 2.4 inv_EOTF",</div><div class='add'>+	[AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF]	= "Gamma 2.6 inv_EOTF",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 amdgpu_eotf =</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_PQ_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF);</div><div class='add'>+</div><div class='add'>+static const u32 amdgpu_inv_eotf =</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_BT709_OETF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF) |</div><div class='add'>+	BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF);</div><div class='add'>+</div><div class='add'>+static struct drm_property *</div><div class='add'>+amdgpu_create_tf_property(struct drm_device *dev,</div><div class='add'>+			  const char *name,</div><div class='add'>+			  u32 supported_tf)</div><div class='add'>+{</div><div class='add'>+	u32 transfer_functions = supported_tf |</div><div class='add'>+				 BIT(AMDGPU_TRANSFER_FUNCTION_DEFAULT) |</div><div class='add'>+				 BIT(AMDGPU_TRANSFER_FUNCTION_IDENTITY);</div><div class='add'>+	struct drm_prop_enum_list enum_list[AMDGPU_TRANSFER_FUNCTION_COUNT];</div><div class='add'>+	int i, len;</div><div class='add'>+</div><div class='add'>+	len = 0;</div><div class='add'>+	for (i = 0; i &lt; AMDGPU_TRANSFER_FUNCTION_COUNT; i++) {</div><div class='add'>+		if ((transfer_functions &amp; BIT(i)) == 0)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		enum_list[len].type = i;</div><div class='add'>+		enum_list[len].name = amdgpu_transfer_function_names[i];</div><div class='add'>+		len++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,</div><div class='add'>+					name, enum_list, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int</div><div class='add'>+amdgpu_dm_create_color_properties(struct amdgpu_device *adev)</div><div class='add'>+{</div><div class='add'>+	struct drm_property *prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev),</div><div class='add'>+				   DRM_MODE_PROP_BLOB,</div><div class='add'>+				   "AMD_PLANE_DEGAMMA_LUT", 0);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_degamma_lut_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create_range(adev_to_drm(adev),</div><div class='add'>+					 DRM_MODE_PROP_IMMUTABLE,</div><div class='add'>+					 "AMD_PLANE_DEGAMMA_LUT_SIZE",</div><div class='add'>+					 0, UINT_MAX);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_degamma_lut_size_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = amdgpu_create_tf_property(adev_to_drm(adev),</div><div class='add'>+					 "AMD_PLANE_DEGAMMA_TF",</div><div class='add'>+					 amdgpu_eotf);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_degamma_tf_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create_range(adev_to_drm(adev),</div><div class='add'>+					 0, "AMD_PLANE_HDR_MULT", 0, U64_MAX);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_hdr_mult_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev),</div><div class='add'>+				   DRM_MODE_PROP_BLOB,</div><div class='add'>+				   "AMD_PLANE_CTM", 0);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_ctm_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev),</div><div class='add'>+				   DRM_MODE_PROP_BLOB,</div><div class='add'>+				   "AMD_PLANE_SHAPER_LUT", 0);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_shaper_lut_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create_range(adev_to_drm(adev),</div><div class='add'>+					 DRM_MODE_PROP_IMMUTABLE,</div><div class='add'>+					 "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_shaper_lut_size_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = amdgpu_create_tf_property(adev_to_drm(adev),</div><div class='add'>+					 "AMD_PLANE_SHAPER_TF",</div><div class='add'>+					 amdgpu_inv_eotf);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_shaper_tf_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev),</div><div class='add'>+				   DRM_MODE_PROP_BLOB,</div><div class='add'>+				   "AMD_PLANE_LUT3D", 0);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_lut3d_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create_range(adev_to_drm(adev),</div><div class='add'>+					 DRM_MODE_PROP_IMMUTABLE,</div><div class='add'>+					 "AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_lut3d_size_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create(adev_to_drm(adev),</div><div class='add'>+				   DRM_MODE_PROP_BLOB,</div><div class='add'>+				   "AMD_PLANE_BLEND_LUT", 0);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_blend_lut_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = drm_property_create_range(adev_to_drm(adev),</div><div class='add'>+					 DRM_MODE_PROP_IMMUTABLE,</div><div class='add'>+					 "AMD_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_blend_lut_size_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = amdgpu_create_tf_property(adev_to_drm(adev),</div><div class='add'>+					 "AMD_PLANE_BLEND_TF",</div><div class='add'>+					 amdgpu_eotf);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.plane_blend_tf_property = prop;</div><div class='add'>+</div><div class='add'>+	prop = amdgpu_create_tf_property(adev_to_drm(adev),</div><div class='add'>+					 "AMD_CRTC_REGAMMA_TF",</div><div class='add'>+					 amdgpu_inv_eotf);</div><div class='add'>+	if (!prop)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;mode_info.regamma_tf_property = prop;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.</div><div class='ctx'>  * @blob: DRM color mgmt property blob</div><div class='hunk'>@@ -182,7 +424,6 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,</div><div class='ctx'> static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,</div><div class='ctx'> 				   struct fixed31_32 *matrix)</div><div class='ctx'> {</div><div class='del'>-	int64_t val;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -201,12 +442,29 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */</div><div class='del'>-		val = ctm-&gt;matrix[i - (i / 4)];</div><div class='del'>-		/* If negative, convert to 2's complement. */</div><div class='del'>-		if (val &amp; (1ULL &lt;&lt; 63))</div><div class='del'>-			val = -(val &amp; ~(1ULL &lt;&lt; 63));</div><div class='add'>+		matrix[i] = amdgpu_dm_fixpt_from_s3132(ctm-&gt;matrix[i - (i / 4)]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		matrix[i].value = val;</div><div class='add'>+/**</div><div class='add'>+ * __drm_ctm_3x4_to_dc_matrix - converts a DRM CTM 3x4 to a DC CSC float matrix</div><div class='add'>+ * @ctm: DRM color transformation matrix with 3x4 dimensions</div><div class='add'>+ * @matrix: DC CSC float matrix</div><div class='add'>+ *</div><div class='add'>+ * The matrix needs to be a 3x4 (12 entry) matrix.</div><div class='add'>+ */</div><div class='add'>+static void __drm_ctm_3x4_to_dc_matrix(const struct drm_color_ctm_3x4 *ctm,</div><div class='add'>+				       struct fixed31_32 *matrix)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* The format provided is S31.32, using signed-magnitude representation.</div><div class='add'>+	 * Our fixed31_32 is also S31.32, but is using 2's complement. We have</div><div class='add'>+	 * to convert from signed-magnitude to 2's complement.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; 12; i++) {</div><div class='add'>+		/* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */</div><div class='add'>+		matrix[i] = amdgpu_dm_fixpt_from_s3132(ctm-&gt;matrix[i]);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -268,16 +526,18 @@ static int __set_output_tf(struct dc_transfer_func *func,</div><div class='ctx'> 	struct calculate_buffer cal_buffer = {0};</div><div class='ctx'> 	bool res;</div><div class='ctx'> </div><div class='del'>-	ASSERT(lut &amp;&amp; lut_size == MAX_COLOR_LUT_ENTRIES);</div><div class='del'>-</div><div class='ctx'> 	cal_buffer.buffer_index = -1;</div><div class='ctx'> </div><div class='del'>-	gamma = dc_create_gamma();</div><div class='del'>-	if (!gamma)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	if (lut_size) {</div><div class='add'>+		ASSERT(lut &amp;&amp; lut_size == MAX_COLOR_LUT_ENTRIES);</div><div class='ctx'> </div><div class='del'>-	gamma-&gt;num_entries = lut_size;</div><div class='del'>-	__drm_lut_to_dc_gamma(lut, gamma, false);</div><div class='add'>+		gamma = dc_create_gamma();</div><div class='add'>+		if (!gamma)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		gamma-&gt;num_entries = lut_size;</div><div class='add'>+		__drm_lut_to_dc_gamma(lut, gamma, false);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (func-&gt;tf == TRANSFER_FUNCTION_LINEAR) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -285,27 +545,68 @@ static int __set_output_tf(struct dc_transfer_func *func,</div><div class='ctx'> 		 * on top of a linear input. But degamma params can be used</div><div class='ctx'> 		 * instead to simulate this.</div><div class='ctx'> 		 */</div><div class='del'>-		gamma-&gt;type = GAMMA_CUSTOM;</div><div class='add'>+		if (gamma)</div><div class='add'>+			gamma-&gt;type = GAMMA_CUSTOM;</div><div class='ctx'> 		res = mod_color_calculate_degamma_params(NULL, func,</div><div class='del'>-							gamma, true);</div><div class='add'>+							 gamma, gamma != NULL);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Assume sRGB. The actual mapping will depend on whether the</div><div class='ctx'> 		 * input was legacy or not.</div><div class='ctx'> 		 */</div><div class='del'>-		gamma-&gt;type = GAMMA_CS_TFM_1D;</div><div class='del'>-		res = mod_color_calculate_regamma_params(func, gamma, false,</div><div class='add'>+		if (gamma)</div><div class='add'>+			gamma-&gt;type = GAMMA_CS_TFM_1D;</div><div class='add'>+		res = mod_color_calculate_regamma_params(func, gamma, gamma != NULL,</div><div class='ctx'> 							 has_rom, NULL, &amp;cal_buffer);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dc_gamma_release(&amp;gamma);</div><div class='add'>+	if (gamma)</div><div class='add'>+		dc_gamma_release(&amp;gamma);</div><div class='ctx'> </div><div class='ctx'> 	return res ? 0 : -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream,</div><div class='add'>+					const struct drm_color_lut *regamma_lut,</div><div class='add'>+					uint32_t regamma_size, bool has_rom,</div><div class='add'>+					enum dc_transfer_func_predefined tf)</div><div class='add'>+{</div><div class='add'>+	struct dc_transfer_func *out_tf = stream-&gt;out_transfer_func;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) {</div><div class='add'>+		/*</div><div class='add'>+		 * CRTC RGM goes into RGM LUT.</div><div class='add'>+		 *</div><div class='add'>+		 * Note: there is no implicit sRGB regamma here. We are using</div><div class='add'>+		 * degamma calculation from color module to calculate the curve</div><div class='add'>+		 * from a linear base if gamma TF is not set. However, if gamma</div><div class='add'>+		 * TF (!= Linear) and LUT are set at the same time, we will use</div><div class='add'>+		 * regamma calculation, and the color module will combine the</div><div class='add'>+		 * pre-defined TF and the custom LUT values into the LUT that's</div><div class='add'>+		 * actually programmed.</div><div class='add'>+		 */</div><div class='add'>+		out_tf-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		out_tf-&gt;tf = tf;</div><div class='add'>+		out_tf-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+</div><div class='add'>+		ret = __set_output_tf(out_tf, regamma_lut, regamma_size, has_rom);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * No CRTC RGM means we can just put the block into bypass</div><div class='add'>+		 * since we don't have any plane level adjustments using it.</div><div class='add'>+		 */</div><div class='add'>+		out_tf-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+		out_tf-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * __set_input_tf - calculates the input transfer function based on expected</div><div class='ctx'>  * input space.</div><div class='add'>+ * @caps: dc color capabilities</div><div class='ctx'>  * @func: transfer function</div><div class='ctx'>  * @lut: lookup table that defines the color space</div><div class='ctx'>  * @lut_size: size of respective lut.</div><div class='hunk'>@@ -313,27 +614,240 @@ static int __set_output_tf(struct dc_transfer_func *func,</div><div class='ctx'>  * Returns:</div><div class='ctx'>  * 0 in case of success. -ENOMEM if fails.</div><div class='ctx'>  */</div><div class='del'>-static int __set_input_tf(struct dc_transfer_func *func,</div><div class='add'>+static int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_func *func,</div><div class='ctx'> 			  const struct drm_color_lut *lut, uint32_t lut_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_gamma *gamma = NULL;</div><div class='ctx'> 	bool res;</div><div class='ctx'> </div><div class='del'>-	gamma = dc_create_gamma();</div><div class='del'>-	if (!gamma)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	if (lut_size) {</div><div class='add'>+		gamma = dc_create_gamma();</div><div class='add'>+		if (!gamma)</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	gamma-&gt;type = GAMMA_CUSTOM;</div><div class='del'>-	gamma-&gt;num_entries = lut_size;</div><div class='add'>+		gamma-&gt;type = GAMMA_CUSTOM;</div><div class='add'>+		gamma-&gt;num_entries = lut_size;</div><div class='add'>+</div><div class='add'>+		__drm_lut_to_dc_gamma(lut, gamma, false);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	__drm_lut_to_dc_gamma(lut, gamma, false);</div><div class='add'>+	res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL);</div><div class='ctx'> </div><div class='del'>-	res = mod_color_calculate_degamma_params(NULL, func, gamma, true);</div><div class='del'>-	dc_gamma_release(&amp;gamma);</div><div class='add'>+	if (gamma)</div><div class='add'>+		dc_gamma_release(&amp;gamma);</div><div class='ctx'> </div><div class='ctx'> 	return res ? 0 : -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum dc_transfer_func_predefined</div><div class='add'>+amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf)</div><div class='add'>+{</div><div class='add'>+	switch (tf) {</div><div class='add'>+	default:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_DEFAULT:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_IDENTITY:</div><div class='add'>+		return TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_SRGB;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_BT709_OETF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF:</div><div class='add'>+		return TRANSFER_FUNCTION_BT709;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_PQ_EOTF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_PQ;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_GAMMA22;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_GAMMA24;</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF:</div><div class='add'>+	case AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF:</div><div class='add'>+		return TRANSFER_FUNCTION_GAMMA26;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __to_dc_lut3d_color(struct dc_rgb *rgb,</div><div class='add'>+				const struct drm_color_lut lut,</div><div class='add'>+				int bit_precision)</div><div class='add'>+{</div><div class='add'>+	rgb-&gt;red = drm_color_lut_extract(lut.red, bit_precision);</div><div class='add'>+	rgb-&gt;green = drm_color_lut_extract(lut.green, bit_precision);</div><div class='add'>+	rgb-&gt;blue  = drm_color_lut_extract(lut.blue, bit_precision);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut,</div><div class='add'>+				    uint32_t lut3d_size,</div><div class='add'>+				    struct tetrahedral_params *params,</div><div class='add'>+				    bool use_tetrahedral_9,</div><div class='add'>+				    int bit_depth)</div><div class='add'>+{</div><div class='add'>+	struct dc_rgb *lut0;</div><div class='add'>+	struct dc_rgb *lut1;</div><div class='add'>+	struct dc_rgb *lut2;</div><div class='add'>+	struct dc_rgb *lut3;</div><div class='add'>+	int lut_i, i;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	if (use_tetrahedral_9) {</div><div class='add'>+		lut0 = params-&gt;tetrahedral_9.lut0;</div><div class='add'>+		lut1 = params-&gt;tetrahedral_9.lut1;</div><div class='add'>+		lut2 = params-&gt;tetrahedral_9.lut2;</div><div class='add'>+		lut3 = params-&gt;tetrahedral_9.lut3;</div><div class='add'>+	} else {</div><div class='add'>+		lut0 = params-&gt;tetrahedral_17.lut0;</div><div class='add'>+		lut1 = params-&gt;tetrahedral_17.lut1;</div><div class='add'>+		lut2 = params-&gt;tetrahedral_17.lut2;</div><div class='add'>+		lut3 = params-&gt;tetrahedral_17.lut3;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (lut_i = 0, i = 0; i &lt; lut3d_size - 4; lut_i++, i += 4) {</div><div class='add'>+		/*</div><div class='add'>+		 * We should consider the 3D LUT RGB values are distributed</div><div class='add'>+		 * along four arrays lut0-3 where the first sizes 1229 and the</div><div class='add'>+		 * other 1228. The bit depth supported for 3dlut channel is</div><div class='add'>+		 * 12-bit, but DC also supports 10-bit.</div><div class='add'>+		 *</div><div class='add'>+		 * TODO: improve color pipeline API to enable the userspace set</div><div class='add'>+		 * bit depth and 3D LUT size/stride, as specified by VA-API.</div><div class='add'>+		 */</div><div class='add'>+		__to_dc_lut3d_color(&amp;lut0[lut_i], lut[i], bit_depth);</div><div class='add'>+		__to_dc_lut3d_color(&amp;lut1[lut_i], lut[i + 1], bit_depth);</div><div class='add'>+		__to_dc_lut3d_color(&amp;lut2[lut_i], lut[i + 2], bit_depth);</div><div class='add'>+		__to_dc_lut3d_color(&amp;lut3[lut_i], lut[i + 3], bit_depth);</div><div class='add'>+	}</div><div class='add'>+	/* lut0 has 1229 points (lut_size/4 + 1) */</div><div class='add'>+	__to_dc_lut3d_color(&amp;lut0[lut_i], lut[i], bit_depth);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream</div><div class='add'>+ * @drm_lut3d: user 3D LUT</div><div class='add'>+ * @drm_lut3d_size: size of 3D LUT</div><div class='add'>+ * @lut3d: DC 3D LUT</div><div class='add'>+ *</div><div class='add'>+ * Map user 3D LUT data to DC 3D LUT and all necessary bits to program it</div><div class='add'>+ * on DCN accordingly.</div><div class='add'>+ */</div><div class='add'>+static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut3d,</div><div class='add'>+				   uint32_t drm_lut3d_size,</div><div class='add'>+				   struct dc_3dlut *lut)</div><div class='add'>+{</div><div class='add'>+	if (!drm_lut3d_size) {</div><div class='add'>+		lut-&gt;state.bits.initialized = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/* Stride and bit depth are not programmable by API yet.</div><div class='add'>+		 * Therefore, only supports 17x17x17 3D LUT (12-bit).</div><div class='add'>+		 */</div><div class='add'>+		lut-&gt;lut_3d.use_tetrahedral_9 = false;</div><div class='add'>+		lut-&gt;lut_3d.use_12bits = true;</div><div class='add'>+		lut-&gt;state.bits.initialized = 1;</div><div class='add'>+		__drm_3dlut_to_dc_3dlut(drm_lut3d, drm_lut3d_size, &amp;lut-&gt;lut_3d,</div><div class='add'>+					lut-&gt;lut_3d.use_tetrahedral_9,</div><div class='add'>+					MAX_COLOR_3DLUT_BITDEPTH);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_lut,</div><div class='add'>+				       bool has_rom,</div><div class='add'>+				       enum dc_transfer_func_predefined tf,</div><div class='add'>+				       uint32_t shaper_size,</div><div class='add'>+				       struct dc_transfer_func *func_shaper)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (shaper_size || tf != TRANSFER_FUNCTION_LINEAR) {</div><div class='add'>+		/*</div><div class='add'>+		 * If user shaper LUT is set, we assume a linear color space</div><div class='add'>+		 * (linearized by degamma 1D LUT or not).</div><div class='add'>+		 */</div><div class='add'>+		func_shaper-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		func_shaper-&gt;tf = tf;</div><div class='add'>+		func_shaper-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+</div><div class='add'>+		ret = __set_output_tf(func_shaper, shaper_lut, shaper_size, has_rom);</div><div class='add'>+	} else {</div><div class='add'>+		func_shaper-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+		func_shaper-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_atomic_blend_lut(const struct drm_color_lut *blend_lut,</div><div class='add'>+				       bool has_rom,</div><div class='add'>+				       enum dc_transfer_func_predefined tf,</div><div class='add'>+				       uint32_t blend_size,</div><div class='add'>+				       struct dc_transfer_func *func_blend)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (blend_size || tf != TRANSFER_FUNCTION_LINEAR) {</div><div class='add'>+		/*</div><div class='add'>+		 * DRM plane gamma LUT or TF means we are linearizing color</div><div class='add'>+		 * space before blending (similar to degamma programming). As</div><div class='add'>+		 * we don't have hardcoded curve support, or we use AMD color</div><div class='add'>+		 * module to fill the parameters that will be translated to HW</div><div class='add'>+		 * points.</div><div class='add'>+		 */</div><div class='add'>+		func_blend-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		func_blend-&gt;tf = tf;</div><div class='add'>+		func_blend-&gt;sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;</div><div class='add'>+</div><div class='add'>+		ret = __set_input_tf(NULL, func_blend, blend_lut, blend_size);</div><div class='add'>+	} else {</div><div class='add'>+		func_blend-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+		func_blend-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_verify_lut3d_size - verifies if 3D LUT is supported and if user</div><div class='add'>+ * shaper and 3D LUTs match the hw supported size</div><div class='add'>+ * @adev: amdgpu device</div><div class='add'>+ * @plane_state: the DRM plane state</div><div class='add'>+ *</div><div class='add'>+ * Verifies if pre-blending (DPP) 3D LUT is supported by the HW (DCN 2.0 or</div><div class='add'>+ * newer) and if the user shaper and 3D LUTs match the supported size.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success. -EINVAL if lut size are invalid.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,</div><div class='add'>+				struct drm_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);</div><div class='add'>+	const struct drm_color_lut *shaper = NULL, *lut3d = NULL;</div><div class='add'>+	uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;</div><div class='add'>+	bool has_3dlut = adev-&gt;dm.dc-&gt;caps.color.dpp.hw_3d_lut;</div><div class='add'>+</div><div class='add'>+	/* shaper LUT is only available if 3D LUT color caps */</div><div class='add'>+	exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;</div><div class='add'>+	shaper = __extract_blob_lut(dm_plane_state-&gt;shaper_lut, &amp;size);</div><div class='add'>+</div><div class='add'>+	if (shaper &amp;&amp; size != exp_size) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev,</div><div class='add'>+			"Invalid Shaper LUT size. Should be %u but got %u.\n",</div><div class='add'>+			exp_size, size);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* The number of 3D LUT entries is the dimension size cubed */</div><div class='add'>+	exp_size = has_3dlut ? dim_size * dim_size * dim_size : 0;</div><div class='add'>+	lut3d = __extract_blob_lut(dm_plane_state-&gt;lut3d, &amp;size);</div><div class='add'>+</div><div class='add'>+	if (lut3d &amp;&amp; size != exp_size) {</div><div class='add'>+		drm_dbg(&amp;adev-&gt;ddev,</div><div class='add'>+			"Invalid 3D LUT size. Should be %u but got %u.\n",</div><div class='add'>+			exp_size, size);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes</div><div class='ctx'>  * @crtc_state: the DRM CRTC state</div><div class='hunk'>@@ -401,9 +915,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 	const struct drm_color_lut *degamma_lut, *regamma_lut;</div><div class='ctx'> 	uint32_t degamma_size, regamma_size;</div><div class='ctx'> 	bool has_regamma, has_degamma;</div><div class='add'>+	enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_LINEAR;</div><div class='ctx'> 	bool is_legacy;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='add'>+	tf = amdgpu_tf_to_dc_tf(crtc-&gt;regamma_tf);</div><div class='add'>+</div><div class='ctx'> 	r = amdgpu_dm_verify_lut_sizes(&amp;crtc-&gt;base);</div><div class='ctx'> 	if (r)</div><div class='ctx'> 		return r;</div><div class='hunk'>@@ -439,27 +956,23 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 		crtc-&gt;cm_is_degamma_srgb = true;</div><div class='ctx'> 		stream-&gt;out_transfer_func-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='ctx'> 		stream-&gt;out_transfer_func-&gt;tf = TRANSFER_FUNCTION_SRGB;</div><div class='del'>-</div><div class='add'>+		/*</div><div class='add'>+		 * Note: although we pass has_rom as parameter here, we never</div><div class='add'>+		 * actually use ROM because the color module only takes the ROM</div><div class='add'>+		 * path if transfer_func-&gt;type == PREDEFINED.</div><div class='add'>+		 *</div><div class='add'>+		 * See more in mod_color_calculate_regamma_params()</div><div class='add'>+		 */</div><div class='ctx'> 		r = __set_legacy_tf(stream-&gt;out_transfer_func, regamma_lut,</div><div class='ctx'> 				    regamma_size, has_rom);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-	} else if (has_regamma) {</div><div class='del'>-		/* If atomic regamma, CRTC RGM goes into RGM LUT. */</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='del'>-</div><div class='del'>-		r = __set_output_tf(stream-&gt;out_transfer_func, regamma_lut,</div><div class='del'>-				    regamma_size, has_rom);</div><div class='add'>+	} else {</div><div class='add'>+		regamma_size = has_regamma ? regamma_size : 0;</div><div class='add'>+		r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut,</div><div class='add'>+						 regamma_size, has_rom, tf);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-	} else {</div><div class='del'>-		/*</div><div class='del'>-		 * No CRTC RGM means we can just put the block into bypass</div><div class='del'>-		 * since we don't have any plane level adjustments using it.</div><div class='del'>-		 */</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-		stream-&gt;out_transfer_func-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -495,20 +1008,10 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.</div><div class='del'>- * @crtc: amdgpu_dm crtc state</div><div class='del'>- * @dc_plane_state: target DC surface</div><div class='del'>- *</div><div class='del'>- * Update the underlying dc_stream_state's input transfer function (ITF) in</div><div class='del'>- * preparation for hardware commit. The transfer function used depends on</div><div class='del'>- * the preparation done on the stream for color management.</div><div class='del'>- *</div><div class='del'>- * Returns:</div><div class='del'>- * 0 on success. -ENOMEM if mem allocation fails.</div><div class='del'>- */</div><div class='del'>-int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='del'>-				      struct dc_plane_state *dc_plane_state)</div><div class='add'>+static int</div><div class='add'>+map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc,</div><div class='add'>+			     struct dc_plane_state *dc_plane_state,</div><div class='add'>+			     struct dc_color_caps *caps)</div><div class='ctx'> {</div><div class='ctx'> 	const struct drm_color_lut *degamma_lut;</div><div class='ctx'> 	enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;</div><div class='hunk'>@@ -531,8 +1034,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 						 &amp;degamma_size);</div><div class='ctx'> 		ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);</div><div class='ctx'> </div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type =</div><div class='del'>-			TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_DISTRIBUTED_POINTS;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * This case isn't fully correct, but also fairly</div><div class='hunk'>@@ -564,11 +1066,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 			dc_plane_state-&gt;in_transfer_func-&gt;tf =</div><div class='ctx'> 				TRANSFER_FUNCTION_LINEAR;</div><div class='ctx'> </div><div class='del'>-		r = __set_input_tf(dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+		r = __set_input_tf(caps, dc_plane_state-&gt;in_transfer_func,</div><div class='ctx'> 				   degamma_lut, degamma_size);</div><div class='ctx'> 		if (r)</div><div class='ctx'> 			return r;</div><div class='del'>-	} else if (crtc-&gt;cm_is_degamma_srgb) {</div><div class='add'>+	} else {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * For legacy gamma support we need the regamma input</div><div class='ctx'> 		 * in linear space. Assume that the input is sRGB.</div><div class='hunk'>@@ -577,14 +1079,209 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='ctx'> 		dc_plane_state-&gt;in_transfer_func-&gt;tf = tf;</div><div class='ctx'> </div><div class='ctx'> 		if (tf != TRANSFER_FUNCTION_SRGB &amp;&amp;</div><div class='del'>-		    !mod_color_calculate_degamma_params(NULL,</div><div class='del'>-			    dc_plane_state-&gt;in_transfer_func, NULL, false))</div><div class='add'>+		    !mod_color_calculate_degamma_params(caps,</div><div class='add'>+							dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+							NULL, false))</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+__set_dm_plane_degamma(struct drm_plane_state *plane_state,</div><div class='add'>+		       struct dc_plane_state *dc_plane_state,</div><div class='add'>+		       struct dc_color_caps *color_caps)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);</div><div class='add'>+	const struct drm_color_lut *degamma_lut;</div><div class='add'>+	enum amdgpu_transfer_function tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='add'>+	uint32_t degamma_size;</div><div class='add'>+	bool has_degamma_lut;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	degamma_lut = __extract_blob_lut(dm_plane_state-&gt;degamma_lut,</div><div class='add'>+					 &amp;degamma_size);</div><div class='add'>+</div><div class='add'>+	has_degamma_lut = degamma_lut &amp;&amp;</div><div class='add'>+			  !__is_lut_linear(degamma_lut, degamma_size);</div><div class='add'>+</div><div class='add'>+	tf = dm_plane_state-&gt;degamma_tf;</div><div class='add'>+</div><div class='add'>+	/* If we don't have plane degamma LUT nor TF to set on DC, we have</div><div class='add'>+	 * nothing to do here, return.</div><div class='add'>+	 */</div><div class='add'>+	if (!has_degamma_lut &amp;&amp; tf == AMDGPU_TRANSFER_FUNCTION_DEFAULT)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func-&gt;tf = amdgpu_tf_to_dc_tf(tf);</div><div class='add'>+</div><div class='add'>+	if (has_degamma_lut) {</div><div class='add'>+		ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);</div><div class='add'>+</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func-&gt;type =</div><div class='add'>+			TF_TYPE_DISTRIBUTED_POINTS;</div><div class='add'>+</div><div class='add'>+		ret = __set_input_tf(color_caps, dc_plane_state-&gt;in_transfer_func,</div><div class='add'>+				     degamma_lut, degamma_size);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+       } else {</div><div class='add'>+		dc_plane_state-&gt;in_transfer_func-&gt;type =</div><div class='add'>+			TF_TYPE_PREDEFINED;</div><div class='add'>+</div><div class='add'>+		if (!mod_color_calculate_degamma_params(color_caps,</div><div class='add'>+		    dc_plane_state-&gt;in_transfer_func, NULL, false))</div><div class='ctx'> 			return -ENOMEM;</div><div class='del'>-	} else {</div><div class='del'>-		/* ...Otherwise we can just bypass the DGM block. */</div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='del'>-		dc_plane_state-&gt;in_transfer_func-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,</div><div class='add'>+				     struct dc_plane_state *dc_plane_state)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);</div><div class='add'>+	enum amdgpu_transfer_function shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='add'>+	enum amdgpu_transfer_function blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='add'>+	const struct drm_color_lut *shaper_lut, *lut3d, *blend_lut;</div><div class='add'>+	uint32_t shaper_size, lut3d_size, blend_size;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dc_plane_state-&gt;hdr_mult = amdgpu_dm_fixpt_from_s3132(dm_plane_state-&gt;hdr_mult);</div><div class='add'>+</div><div class='add'>+	shaper_lut = __extract_blob_lut(dm_plane_state-&gt;shaper_lut, &amp;shaper_size);</div><div class='add'>+	shaper_size = shaper_lut != NULL ? shaper_size : 0;</div><div class='add'>+	shaper_tf = dm_plane_state-&gt;shaper_tf;</div><div class='add'>+	lut3d = __extract_blob_lut(dm_plane_state-&gt;lut3d, &amp;lut3d_size);</div><div class='add'>+	lut3d_size = lut3d != NULL ? lut3d_size : 0;</div><div class='add'>+</div><div class='add'>+	amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, dc_plane_state-&gt;lut3d_func);</div><div class='add'>+	ret = amdgpu_dm_atomic_shaper_lut(shaper_lut, false,</div><div class='add'>+					  amdgpu_tf_to_dc_tf(shaper_tf),</div><div class='add'>+					  shaper_size,</div><div class='add'>+					  dc_plane_state-&gt;in_shaper_func);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_dbg_kms(plane_state-&gt;plane-&gt;dev,</div><div class='add'>+			    "setting plane %d shaper LUT failed.\n",</div><div class='add'>+			    plane_state-&gt;plane-&gt;index);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	blend_tf = dm_plane_state-&gt;blend_tf;</div><div class='add'>+	blend_lut = __extract_blob_lut(dm_plane_state-&gt;blend_lut, &amp;blend_size);</div><div class='add'>+	blend_size = blend_lut != NULL ? blend_size : 0;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dm_atomic_blend_lut(blend_lut, false,</div><div class='add'>+					 amdgpu_tf_to_dc_tf(blend_tf),</div><div class='add'>+					 blend_size, dc_plane_state-&gt;blend_tf);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_dbg_kms(plane_state-&gt;plane-&gt;dev,</div><div class='add'>+			    "setting plane %d gamma lut failed.\n",</div><div class='add'>+			    plane_state-&gt;plane-&gt;index);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.</div><div class='add'>+ * @crtc: amdgpu_dm crtc state</div><div class='add'>+ * @plane_state: DRM plane state</div><div class='add'>+ * @dc_plane_state: target DC surface</div><div class='add'>+ *</div><div class='add'>+ * Update the underlying dc_stream_state's input transfer function (ITF) in</div><div class='add'>+ * preparation for hardware commit. The transfer function used depends on</div><div class='add'>+ * the preparation done on the stream for color management.</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success. -ENOMEM if mem allocation fails.</div><div class='add'>+ */</div><div class='add'>+int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,</div><div class='add'>+				      struct drm_plane_state *plane_state,</div><div class='add'>+				      struct dc_plane_state *dc_plane_state)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;base.state-&gt;dev);</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);</div><div class='add'>+	struct drm_color_ctm_3x4 *ctm = NULL;</div><div class='add'>+	struct dc_color_caps *color_caps = NULL;</div><div class='add'>+	bool has_crtc_cm_degamma;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dm_verify_lut3d_size(adev, plane_state);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_dbg_driver(&amp;adev-&gt;ddev, "amdgpu_dm_verify_lut3d_size() failed\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dc_plane_state-&gt;ctx &amp;&amp; dc_plane_state-&gt;ctx-&gt;dc)</div><div class='add'>+		color_caps = &amp;dc_plane_state-&gt;ctx-&gt;dc-&gt;caps.color;</div><div class='add'>+</div><div class='add'>+	/* Initially, we can just bypass the DGM block. */</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='add'>+	dc_plane_state-&gt;in_transfer_func-&gt;tf = TRANSFER_FUNCTION_LINEAR;</div><div class='add'>+</div><div class='add'>+	/* After, we start to update values according to color props */</div><div class='add'>+	has_crtc_cm_degamma = (crtc-&gt;cm_has_degamma || crtc-&gt;cm_is_degamma_srgb);</div><div class='add'>+</div><div class='add'>+	ret = __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps);</div><div class='add'>+	if (ret == -ENOMEM)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* We only have one degamma block available (pre-blending) for the</div><div class='add'>+	 * whole color correction pipeline, so that we can't actually perform</div><div class='add'>+	 * plane and CRTC degamma at the same time. Explicitly reject atomic</div><div class='add'>+	 * updates when userspace sets both plane and CRTC degamma properties.</div><div class='add'>+	 */</div><div class='add'>+	if (has_crtc_cm_degamma &amp;&amp; ret != -EINVAL) {</div><div class='add'>+		drm_dbg_kms(crtc-&gt;base.crtc-&gt;dev,</div><div class='add'>+			    "doesn't support plane and CRTC degamma at the same time\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If we are here, it means we don't have plane degamma settings, check</div><div class='add'>+	 * if we have CRTC degamma waiting for mapping to pre-blending degamma</div><div class='add'>+	 * block</div><div class='add'>+	 */</div><div class='add'>+	if (has_crtc_cm_degamma) {</div><div class='add'>+		/*</div><div class='add'>+		 * AMD HW doesn't have post-blending degamma caps. When DRM</div><div class='add'>+		 * CRTC atomic degamma is set, we maps it to DPP degamma block</div><div class='add'>+		 * (pre-blending) or, on legacy gamma, we use DPP degamma to</div><div class='add'>+		 * linearize (implicit degamma) from sRGB/BT709 according to</div><div class='add'>+		 * the input space.</div><div class='add'>+		 */</div><div class='add'>+		ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, color_caps);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Setup CRTC CTM. */</div><div class='add'>+	if (dm_plane_state-&gt;ctm) {</div><div class='add'>+		ctm = (struct drm_color_ctm_3x4 *)dm_plane_state-&gt;ctm-&gt;data;</div><div class='add'>+		/*</div><div class='add'>+		 * DCN2 and older don't support both pre-blending and</div><div class='add'>+		 * post-blending gamut remap. For this HW family, if we have</div><div class='add'>+		 * the plane and CRTC CTMs simultaneously, CRTC CTM takes</div><div class='add'>+		 * priority, and we discard plane CTM, as implemented in</div><div class='add'>+		 * dcn10_program_gamut_remap(). However, DCN3+ has DPP</div><div class='add'>+		 * (pre-blending) and MPC (post-blending) `gamut remap` blocks;</div><div class='add'>+		 * therefore, we can program plane and CRTC CTMs together by</div><div class='add'>+		 * mapping CRTC CTM to MPC and keeping plane CTM setup at DPP,</div><div class='add'>+		 * as it's done by dcn30_program_gamut_remap().</div><div class='add'>+		 */</div><div class='add'>+		__drm_ctm_3x4_to_dc_matrix(ctm, dc_plane_state-&gt;gamut_remap_matrix.matrix);</div><div class='add'>+</div><div class='add'>+		dc_plane_state-&gt;gamut_remap_matrix.enable_remap = true;</div><div class='add'>+		dc_plane_state-&gt;input_csc_color_matrix.enable_adjustment = false;</div><div class='add'>+	} else {</div><div class='add'>+		/* Bypass CTM. */</div><div class='add'>+		dc_plane_state-&gt;gamut_remap_matrix.enable_remap = false;</div><div class='add'>+		dc_plane_state-&gt;input_csc_color_matrix.enable_adjustment = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c<br/>index 52ecfa746b54..f936a35fa9eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c</a></div><div class='hunk'>@@ -326,6 +326,9 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)</div><div class='ctx'> 			if (!connector-&gt;state || connector-&gt;state-&gt;crtc != crtc)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='add'>+			if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			aconn = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c<br/>index cb0b48bb2a7d..6e715ef3a556 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c</a></div><div class='hunk'>@@ -29,7 +29,6 @@</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_dm_psr.h"</div><div class='del'>-#include "amdgpu_dm_replay.h"</div><div class='ctx'> #include "amdgpu_dm_crtc.h"</div><div class='ctx'> #include "amdgpu_dm_plane.h"</div><div class='ctx'> #include "amdgpu_dm_trace.h"</div><div class='hunk'>@@ -124,12 +123,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='ctx'> 	 * fill_dc_dirty_rects().</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (vblank_work-&gt;stream &amp;&amp; vblank_work-&gt;stream-&gt;link) {</div><div class='del'>-		/*</div><div class='del'>-		 * Prioritize replay, instead of psr</div><div class='del'>-		 */</div><div class='del'>-		if (vblank_work-&gt;stream-&gt;link-&gt;replay_settings.replay_feature_enabled)</div><div class='del'>-			amdgpu_dm_replay_enable(vblank_work-&gt;stream, false);</div><div class='del'>-		else if (vblank_work-&gt;enable) {</div><div class='add'>+		if (vblank_work-&gt;enable) {</div><div class='ctx'> 			if (vblank_work-&gt;stream-&gt;link-&gt;psr_settings.psr_version &lt; DC_PSR_VERSION_SU_1 &amp;&amp;</div><div class='ctx'> 			    vblank_work-&gt;stream-&gt;link-&gt;psr_settings.psr_allow_active)</div><div class='ctx'> 				amdgpu_dm_psr_disable(vblank_work-&gt;stream);</div><div class='hunk'>@@ -138,7 +132,6 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)</div><div class='ctx'> #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY</div><div class='ctx'> 			   !amdgpu_dm_crc_window_is_activated(&amp;vblank_work-&gt;acrtc-&gt;base) &amp;&amp;</div><div class='ctx'> #endif</div><div class='del'>-			   vblank_work-&gt;stream-&gt;link-&gt;panel_config.psr.disallow_replay &amp;&amp;</div><div class='ctx'> 			   vblank_work-&gt;acrtc-&gt;dm_irq_params.allow_psr_entry) {</div><div class='ctx'> 			amdgpu_dm_psr_enable(vblank_work-&gt;stream);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -260,6 +253,7 @@ static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *cr</div><div class='ctx'> 	state-&gt;freesync_config = cur-&gt;freesync_config;</div><div class='ctx'> 	state-&gt;cm_has_degamma = cur-&gt;cm_has_degamma;</div><div class='ctx'> 	state-&gt;cm_is_degamma_srgb = cur-&gt;cm_is_degamma_srgb;</div><div class='add'>+	state-&gt;regamma_tf = cur-&gt;regamma_tf;</div><div class='ctx'> 	state-&gt;crc_skip_count = cur-&gt;crc_skip_count;</div><div class='ctx'> 	state-&gt;mpo_requested = cur-&gt;mpo_requested;</div><div class='ctx'> 	/* TODO Duplicate dc_stream after objects are stream object is flattened */</div><div class='hunk'>@@ -296,6 +290,70 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+/**</div><div class='add'>+ * dm_crtc_additional_color_mgmt - enable additional color properties</div><div class='add'>+ * @crtc: DRM CRTC</div><div class='add'>+ *</div><div class='add'>+ * This function lets the driver enable post-blending CRTC regamma transfer</div><div class='add'>+ * function property in addition to DRM CRTC gamma LUT. Default value means</div><div class='add'>+ * linear transfer function, which is the default CRTC gamma LUT behaviour</div><div class='add'>+ * without this property.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;dm.dc-&gt;caps.color.mpc.ogam_ram)</div><div class='add'>+		drm_object_attach_property(&amp;crtc-&gt;base,</div><div class='add'>+					   adev-&gt;mode_info.regamma_tf_property,</div><div class='add'>+					   AMDGPU_TRANSFER_FUNCTION_DEFAULT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,</div><div class='add'>+				   struct drm_crtc_state *state,</div><div class='add'>+				   struct drm_property *property,</div><div class='add'>+				   uint64_t val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='add'>+	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);</div><div class='add'>+</div><div class='add'>+	if (property == adev-&gt;mode_info.regamma_tf_property) {</div><div class='add'>+		if (acrtc_state-&gt;regamma_tf != val) {</div><div class='add'>+			acrtc_state-&gt;regamma_tf = val;</div><div class='add'>+			acrtc_state-&gt;base.color_mgmt_changed |= 1;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		drm_dbg_atomic(crtc-&gt;dev,</div><div class='add'>+			       "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",</div><div class='add'>+			       crtc-&gt;base.id, crtc-&gt;name,</div><div class='add'>+			       property-&gt;base.id, property-&gt;name);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,</div><div class='add'>+				   const struct drm_crtc_state *state,</div><div class='add'>+				   struct drm_property *property,</div><div class='add'>+				   uint64_t *val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(crtc-&gt;dev);</div><div class='add'>+	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);</div><div class='add'>+</div><div class='add'>+	if (property == adev-&gt;mode_info.regamma_tf_property)</div><div class='add'>+		*val = acrtc_state-&gt;regamma_tf;</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /* Implemented only the options currently available for the driver */</div><div class='ctx'> static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {</div><div class='ctx'> 	.reset = amdgpu_dm_crtc_reset_state,</div><div class='hunk'>@@ -314,6 +372,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {</div><div class='ctx'> #if defined(CONFIG_DEBUG_FS)</div><div class='ctx'> 	.late_register = amdgpu_dm_crtc_late_register,</div><div class='ctx'> #endif</div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+	.atomic_set_property = amdgpu_dm_atomic_crtc_set_property,</div><div class='add'>+	.atomic_get_property = amdgpu_dm_atomic_crtc_get_property,</div><div class='add'>+#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)</div><div class='hunk'>@@ -489,6 +551,9 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	drm_mode_crtc_set_gamma_size(&amp;acrtc-&gt;base, MAX_COLOR_LEGACY_LUT_ENTRIES);</div><div class='ctx'> </div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+	dm_crtc_additional_color_mgmt(&amp;acrtc-&gt;base);</div><div class='add'>+#endif</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c<br/>index 13a177d34376..68a846323912 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c</a></div><div class='hunk'>@@ -2971,6 +2971,85 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dmub_trace_mask_set(void *data, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = data;</div><div class='add'>+	struct dmub_srv *srv = adev-&gt;dm.dc-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='add'>+	enum dmub_gpint_command cmd;</div><div class='add'>+	u64 mask = 0xffff;</div><div class='add'>+	u8 shift = 0;</div><div class='add'>+	u32 res;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!srv-&gt;fw_version)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0;  i &lt; 4; i++) {</div><div class='add'>+		res = (val &amp; mask) &gt;&gt; shift;</div><div class='add'>+</div><div class='add'>+		switch (i) {</div><div class='add'>+		case 0:</div><div class='add'>+			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!dc_wake_and_execute_gpint(adev-&gt;dm.dc-&gt;ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))</div><div class='add'>+			return -EIO;</div><div class='add'>+</div><div class='add'>+		usleep_range(100, 1000);</div><div class='add'>+</div><div class='add'>+		mask &lt;&lt;= 16;</div><div class='add'>+		shift += 16;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dmub_trace_mask_show(void *data, u64 *val)</div><div class='add'>+{</div><div class='add'>+	enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;</div><div class='add'>+	struct amdgpu_device *adev = data;</div><div class='add'>+	struct dmub_srv *srv = adev-&gt;dm.dc-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='add'>+	u8 shift = 0;</div><div class='add'>+	u64 raw = 0;</div><div class='add'>+	u64 res = 0;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	if (!srv-&gt;fw_version)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	while (i &lt; 4) {</div><div class='add'>+		uint32_t response;</div><div class='add'>+</div><div class='add'>+		if (!dc_wake_and_execute_gpint(adev-&gt;dm.dc-&gt;ctx, cmd, 0, &amp;response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+			return -EIO;</div><div class='add'>+</div><div class='add'>+		raw = response;</div><div class='add'>+		usleep_range(100, 1000);</div><div class='add'>+</div><div class='add'>+		cmd++;</div><div class='add'>+		res |= (raw &lt;&lt; shift);</div><div class='add'>+		shift += 16;</div><div class='add'>+		i++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = res;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,</div><div class='add'>+			 dmub_trace_mask_set, "0x%llx\n");</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Set dmcub trace event IRQ enable or disable.</div><div class='ctx'>  * Usage to enable dmcub trace event IRQ: echo 1 &gt; /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en</div><div class='hunk'>@@ -3647,12 +3726,16 @@ static int capabilities_show(struct seq_file *m, void *unused)</div><div class='ctx'> 	bool mall_supported = dc-&gt;caps.mall_size_total;</div><div class='ctx'> 	bool subvp_supported = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='ctx'> 	unsigned int mall_in_use = false;</div><div class='del'>-	unsigned int subvp_in_use = dc-&gt;cap_funcs.get_subvp_en(dc, dc-&gt;current_state);</div><div class='add'>+	unsigned int subvp_in_use = false;</div><div class='add'>+</div><div class='ctx'> 	struct hubbub *hubbub = dc-&gt;res_pool-&gt;hubbub;</div><div class='ctx'> </div><div class='ctx'> 	if (hubbub-&gt;funcs-&gt;get_mall_en)</div><div class='ctx'> 		hubbub-&gt;funcs-&gt;get_mall_en(hubbub, &amp;mall_in_use);</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;cap_funcs.get_subvp_en)</div><div class='add'>+		subvp_in_use = dc-&gt;cap_funcs.get_subvp_en(dc, dc-&gt;current_state);</div><div class='add'>+</div><div class='ctx'> 	seq_printf(m, "mall supported: %s, enabled: %s\n",</div><div class='ctx'> 			   mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");</div><div class='ctx'> 	seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",</div><div class='hunk'>@@ -3880,6 +3963,9 @@ void dtn_debugfs_init(struct amdgpu_device *adev)</div><div class='ctx'> 	debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,</div><div class='ctx'> 				   adev, &amp;force_timing_sync_ops);</div><div class='ctx'> </div><div class='add'>+	debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,</div><div class='add'>+				   adev, &amp;dmub_trace_mask_fops);</div><div class='add'>+</div><div class='ctx'> 	debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,</div><div class='ctx'> 				   adev, &amp;dmcub_trace_event_state_fops);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c<br/>index eb6121ad92fd..85b7f58a7f35 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c</a></div><div class='hunk'>@@ -64,6 +64,12 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)</div><div class='ctx'> 		DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);</div><div class='ctx'> 		edid_caps-&gt;panel_patch.disable_fams = true;</div><div class='ctx'> 		break;</div><div class='add'>+	/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */</div><div class='add'>+	case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):</div><div class='add'>+	case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):</div><div class='add'>+		DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);</div><div class='add'>+		edid_caps-&gt;panel_patch.remove_sink_ext_caps = true;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -334,15 +340,14 @@ enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(</div><div class='ctx'> 	return ACT_SUCCESS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dm_helpers_dp_mst_send_payload_allocation(</div><div class='add'>+void dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='del'>-		bool enable)</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 	struct drm_dp_mst_topology_state *mst_state;</div><div class='ctx'> 	struct drm_dp_mst_topology_mgr *mst_mgr;</div><div class='del'>-	struct drm_dp_mst_atomic_payload *new_payload, old_payload;</div><div class='add'>+	struct drm_dp_mst_atomic_payload *new_payload;</div><div class='ctx'> 	enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;</div><div class='ctx'> 	enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -350,25 +355,13 @@ bool dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 	aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='ctx'> </div><div class='ctx'> 	if (!aconnector || !aconnector-&gt;mst_root)</div><div class='del'>-		return false;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	mst_mgr = &amp;aconnector-&gt;mst_root-&gt;mst_mgr;</div><div class='ctx'> 	mst_state = to_drm_dp_mst_topology_state(mst_mgr-&gt;base.state);</div><div class='del'>-</div><div class='ctx'> 	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector-&gt;mst_output_port);</div><div class='ctx'> </div><div class='del'>-	if (!enable) {</div><div class='del'>-		set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;</div><div class='del'>-		clr_flag = MST_ALLOCATE_NEW_PAYLOAD;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (enable) {</div><div class='del'>-		ret = drm_dp_add_payload_part2(mst_mgr, mst_state-&gt;base.state, new_payload);</div><div class='del'>-	} else {</div><div class='del'>-		dm_helpers_construct_old_payload(mst_mgr, mst_state,</div><div class='del'>-						 new_payload, &amp;old_payload);</div><div class='del'>-		drm_dp_remove_payload_part2(mst_mgr, mst_state, &amp;old_payload, new_payload);</div><div class='del'>-	}</div><div class='add'>+	ret = drm_dp_add_payload_part2(mst_mgr, mst_state-&gt;base.state, new_payload);</div><div class='ctx'> </div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='hunk'>@@ -379,10 +372,36 @@ bool dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 		amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status,</div><div class='ctx'> 			clr_flag, false);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_dm_connector *aconnector;</div><div class='add'>+	struct drm_dp_mst_topology_state *mst_state;</div><div class='add'>+	struct drm_dp_mst_topology_mgr *mst_mgr;</div><div class='add'>+	struct drm_dp_mst_atomic_payload *new_payload, old_payload;</div><div class='add'>+	enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;</div><div class='add'>+	enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;</div><div class='add'>+</div><div class='add'>+	aconnector = (struct amdgpu_dm_connector *)stream-&gt;dm_stream_context;</div><div class='add'>+</div><div class='add'>+	if (!aconnector || !aconnector-&gt;mst_root)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mst_mgr = &amp;aconnector-&gt;mst_root-&gt;mst_mgr;</div><div class='add'>+	mst_state = to_drm_dp_mst_topology_state(mst_mgr-&gt;base.state);</div><div class='add'>+	new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector-&gt;mst_output_port);</div><div class='add'>+	dm_helpers_construct_old_payload(mst_mgr, mst_state,</div><div class='add'>+					 new_payload, &amp;old_payload);</div><div class='add'>+</div><div class='add'>+	drm_dp_remove_payload_part2(mst_mgr, mst_state, &amp;old_payload, new_payload);</div><div class='add'>+</div><div class='add'>+	amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status, set_flag, true);</div><div class='add'>+	amdgpu_dm_set_mst_status(&amp;aconnector-&gt;mst_status, clr_flag, false);</div><div class='add'>+ }</div><div class='add'>+</div><div class='ctx'> void dm_dtn_log_begin(struct dc_context *ctx,</div><div class='ctx'> 	struct dc_log_buffer_ctx *log_ctx)</div><div class='ctx'> {</div><div class='hunk'>@@ -960,6 +979,11 @@ int dm_helper_dmub_aux_transfer_sync(</div><div class='ctx'> 		struct aux_payload *payload,</div><div class='ctx'> 		enum aux_return_code_type *operation_result)</div><div class='ctx'> {</div><div class='add'>+	if (!link-&gt;hpd_status) {</div><div class='add'>+		*operation_result = AUX_RET_ERROR_HPD_DISCON;</div><div class='add'>+		return -1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link-&gt;link_index, payload,</div><div class='ctx'> 			operation_result);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c<br/>index 51467f132c26..58b880acb087 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c</a></div><div class='hunk'>@@ -894,10 +894,15 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='del'>-				to_amdgpu_dm_connector(connector);</div><div class='add'>+		struct amdgpu_dm_connector *amdgpu_dm_connector;</div><div class='add'>+		const struct dc_link *dc_link;</div><div class='ctx'> </div><div class='del'>-		const struct dc_link *dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		amdgpu_dm_connector = to_amdgpu_dm_connector(connector);</div><div class='add'>+</div><div class='add'>+		dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd != DC_IRQ_SOURCE_INVALID) {</div><div class='ctx'> 			dc_interrupt_set(adev-&gt;dm.dc,</div><div class='hunk'>@@ -930,9 +935,14 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	drm_connector_list_iter_begin(dev, &amp;iter);</div><div class='ctx'> 	drm_for_each_connector_iter(connector, &amp;iter) {</div><div class='del'>-		struct amdgpu_dm_connector *amdgpu_dm_connector =</div><div class='del'>-				to_amdgpu_dm_connector(connector);</div><div class='del'>-		const struct dc_link *dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='add'>+		struct amdgpu_dm_connector *amdgpu_dm_connector;</div><div class='add'>+		const struct dc_link *dc_link;</div><div class='add'>+</div><div class='add'>+		if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_WRITEBACK)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		amdgpu_dm_connector = to_amdgpu_dm_connector(connector);</div><div class='add'>+		dc_link = amdgpu_dm_connector-&gt;dc_link;</div><div class='ctx'> </div><div class='ctx'> 		if (dc_link-&gt;irq_source_hpd != DC_IRQ_SOURCE_INVALID) {</div><div class='ctx'> 			dc_interrupt_set(adev-&gt;dm.dc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c<br/>index 3608d520b227..941e96f100f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include &lt;drm/drm_atomic.h&gt;</div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fixed.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "amdgpu_dm.h"</div><div class='hunk'>@@ -45,7 +46,7 @@</div><div class='ctx'> #include "amdgpu_dm_debugfs.h"</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-#include "dc/dcn20/dcn20_resource.h"</div><div class='add'>+#include "dc/resource/dcn20/dcn20_resource.h"</div><div class='ctx'> </div><div class='ctx'> #define PEAK_FACTOR_X1000 1006</div><div class='ctx'> </div><div class='hunk'>@@ -425,8 +426,7 @@ dm_mst_atomic_best_encoder(struct drm_connector *connector,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,</div><div class='ctx'> 											 connector);</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='del'>-	struct amdgpu_device *adev = drm_to_adev(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(connector-&gt;dev);</div><div class='ctx'> 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state-&gt;crtc);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;adev-&gt;dm.mst_encoders[acrtc-&gt;crtc_id].base;</div><div class='hunk'>@@ -1501,14 +1501,16 @@ int pre_validate_dsc(struct drm_atomic_state *state,</div><div class='ctx'> 		int ind = find_crtc_index_in_state_by_stream(state, stream);</div><div class='ctx'> </div><div class='ctx'> 		if (ind &gt;= 0) {</div><div class='add'>+			struct drm_connector *connector;</div><div class='ctx'> 			struct amdgpu_dm_connector *aconnector;</div><div class='ctx'> 			struct drm_connector_state *drm_new_conn_state;</div><div class='ctx'> 			struct dm_connector_state *dm_new_conn_state;</div><div class='ctx'> 			struct dm_crtc_state *dm_old_crtc_state;</div><div class='ctx'> </div><div class='del'>-			aconnector =</div><div class='add'>+			connector =</div><div class='ctx'> 				amdgpu_dm_find_first_crtc_matching_connector(state,</div><div class='ctx'> 									     state-&gt;crtcs[ind].ptr);</div><div class='add'>+			aconnector = to_amdgpu_dm_connector(connector);</div><div class='ctx'> 			drm_new_conn_state =</div><div class='ctx'> 				drm_atomic_get_new_connector_state(state,</div><div class='ctx'> 								   &amp;aconnector-&gt;base);</div><div class='hunk'>@@ -1603,9 +1605,8 @@ enum dc_status dm_dp_mst_is_port_support_mode(</div><div class='ctx'> 	struct dc_link_settings cur_link_settings;</div><div class='ctx'> 	unsigned int end_to_end_bw_in_kbps = 0;</div><div class='ctx'> 	unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;</div><div class='del'>-	unsigned int max_compressed_bw_in_kbps = 0;</div><div class='ctx'> 	struct dc_dsc_bw_range bw_range = {0};</div><div class='del'>-	uint16_t full_pbn = aconnector-&gt;mst_output_port-&gt;full_pbn;</div><div class='add'>+	struct dc_dsc_config_options dsc_options = {0};</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Consider the case with the depth of the mst topology tree is equal or less than 2</div><div class='hunk'>@@ -1621,30 +1622,39 @@ enum dc_status dm_dp_mst_is_port_support_mode(</div><div class='ctx'> 	   (aconnector-&gt;mst_output_port-&gt;passthrough_aux ||</div><div class='ctx'> 	    aconnector-&gt;dsc_aux == &amp;aconnector-&gt;mst_output_port-&gt;aux)) {</div><div class='ctx'> 		cur_link_settings = stream-&gt;link-&gt;verified_link_cap;</div><div class='add'>+		upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector-&gt;dc_link, &amp;cur_link_settings);</div><div class='add'>+		down_link_bw_in_kbps = kbps_from_pbn(aconnector-&gt;mst_output_port-&gt;full_pbn);</div><div class='ctx'> </div><div class='del'>-		upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector-&gt;dc_link,</div><div class='del'>-							       &amp;cur_link_settings);</div><div class='del'>-		down_link_bw_in_kbps = kbps_from_pbn(full_pbn);</div><div class='del'>-</div><div class='del'>-		/* pick the bottleneck */</div><div class='del'>-		end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,</div><div class='del'>-					    down_link_bw_in_kbps);</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * use the maximum dsc compression bandwidth as the required</div><div class='del'>-		 * bandwidth for the mode</div><div class='del'>-		 */</div><div class='del'>-		max_compressed_bw_in_kbps = bw_range.min_kbps;</div><div class='add'>+		/* pick the end to end bw bottleneck */</div><div class='add'>+		end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, down_link_bw_in_kbps);</div><div class='ctx'> </div><div class='del'>-		if (end_to_end_bw_in_kbps &lt; max_compressed_bw_in_kbps) {</div><div class='del'>-			DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");</div><div class='add'>+		if (end_to_end_bw_in_kbps &lt; bw_range.min_kbps) {</div><div class='add'>+			DRM_DEBUG_DRIVER("maximum dsc compression cannot fit into end-to-end bandwidth\n");</div><div class='ctx'> 			return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (end_to_end_bw_in_kbps &lt; bw_range.stream_kbps) {</div><div class='add'>+			dc_dsc_get_default_config_option(stream-&gt;link-&gt;dc, &amp;dsc_options);</div><div class='add'>+			dsc_options.max_target_bpp_limit_override_x16 = aconnector-&gt;base.display_info.max_dsc_bpp * 16;</div><div class='add'>+			if (dc_dsc_compute_config(stream-&gt;sink-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dscs[0],</div><div class='add'>+					&amp;stream-&gt;sink-&gt;dsc_caps.dsc_dec_caps,</div><div class='add'>+					&amp;dsc_options,</div><div class='add'>+					end_to_end_bw_in_kbps,</div><div class='add'>+					&amp;stream-&gt;timing,</div><div class='add'>+					dc_link_get_highest_encoding_format(stream-&gt;link),</div><div class='add'>+					&amp;stream-&gt;timing.dsc_cfg)) {</div><div class='add'>+				stream-&gt;timing.flags.DSC = 1;</div><div class='add'>+				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc and dsc config found\n");</div><div class='add'>+			} else {</div><div class='add'>+				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc but dsc config not found\n");</div><div class='add'>+				return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* check if mode could be supported within full_pbn */</div><div class='ctx'> 		bpp = convert_dc_color_depth_into_bpc(stream-&gt;timing.display_color_depth) * 3;</div><div class='ctx'> 		pbn = drm_dp_calc_pbn_mode(stream-&gt;timing.pix_clk_100hz / 10, bpp &lt;&lt; 4);</div><div class='del'>-		if (pbn &gt; full_pbn)</div><div class='add'>+		if (pbn &gt; aconnector-&gt;mst_output_port-&gt;full_pbn)</div><div class='ctx'> 			return DC_FAIL_BANDWIDTH_VALIDATE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c<br/>index 116121e647ca..8a4c40b4c27e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c</a></div><div class='hunk'>@@ -1337,8 +1337,14 @@ static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)</div><div class='ctx'> 	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);</div><div class='ctx'> 	WARN_ON(amdgpu_state == NULL);</div><div class='ctx'> </div><div class='del'>-	if (amdgpu_state)</div><div class='del'>-		__drm_atomic_helper_plane_reset(plane, &amp;amdgpu_state-&gt;base);</div><div class='add'>+	if (!amdgpu_state)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	__drm_atomic_helper_plane_reset(plane, &amp;amdgpu_state-&gt;base);</div><div class='add'>+	amdgpu_state-&gt;degamma_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='add'>+	amdgpu_state-&gt;hdr_mult = AMDGPU_HDR_MULT_DEFAULT;</div><div class='add'>+	amdgpu_state-&gt;shaper_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='add'>+	amdgpu_state-&gt;blend_tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane)</div><div class='hunk'>@@ -1357,6 +1363,27 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct</div><div class='ctx'> 		dc_plane_state_retain(dm_plane_state-&gt;dc_state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (old_dm_plane_state-&gt;degamma_lut)</div><div class='add'>+		dm_plane_state-&gt;degamma_lut =</div><div class='add'>+			drm_property_blob_get(old_dm_plane_state-&gt;degamma_lut);</div><div class='add'>+	if (old_dm_plane_state-&gt;ctm)</div><div class='add'>+		dm_plane_state-&gt;ctm =</div><div class='add'>+			drm_property_blob_get(old_dm_plane_state-&gt;ctm);</div><div class='add'>+	if (old_dm_plane_state-&gt;shaper_lut)</div><div class='add'>+		dm_plane_state-&gt;shaper_lut =</div><div class='add'>+			drm_property_blob_get(old_dm_plane_state-&gt;shaper_lut);</div><div class='add'>+	if (old_dm_plane_state-&gt;lut3d)</div><div class='add'>+		dm_plane_state-&gt;lut3d =</div><div class='add'>+			drm_property_blob_get(old_dm_plane_state-&gt;lut3d);</div><div class='add'>+	if (old_dm_plane_state-&gt;blend_lut)</div><div class='add'>+		dm_plane_state-&gt;blend_lut =</div><div class='add'>+			drm_property_blob_get(old_dm_plane_state-&gt;blend_lut);</div><div class='add'>+</div><div class='add'>+	dm_plane_state-&gt;degamma_tf = old_dm_plane_state-&gt;degamma_tf;</div><div class='add'>+	dm_plane_state-&gt;hdr_mult = old_dm_plane_state-&gt;hdr_mult;</div><div class='add'>+	dm_plane_state-&gt;shaper_tf = old_dm_plane_state-&gt;shaper_tf;</div><div class='add'>+	dm_plane_state-&gt;blend_tf = old_dm_plane_state-&gt;blend_tf;</div><div class='add'>+</div><div class='ctx'> 	return &amp;dm_plane_state-&gt;base;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1424,12 +1451,206 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,</div><div class='ctx'> {</div><div class='ctx'> 	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);</div><div class='ctx'> </div><div class='add'>+	if (dm_plane_state-&gt;degamma_lut)</div><div class='add'>+		drm_property_blob_put(dm_plane_state-&gt;degamma_lut);</div><div class='add'>+	if (dm_plane_state-&gt;ctm)</div><div class='add'>+		drm_property_blob_put(dm_plane_state-&gt;ctm);</div><div class='add'>+	if (dm_plane_state-&gt;lut3d)</div><div class='add'>+		drm_property_blob_put(dm_plane_state-&gt;lut3d);</div><div class='add'>+	if (dm_plane_state-&gt;shaper_lut)</div><div class='add'>+		drm_property_blob_put(dm_plane_state-&gt;shaper_lut);</div><div class='add'>+	if (dm_plane_state-&gt;blend_lut)</div><div class='add'>+		drm_property_blob_put(dm_plane_state-&gt;blend_lut);</div><div class='add'>+</div><div class='ctx'> 	if (dm_plane_state-&gt;dc_state)</div><div class='ctx'> 		dc_plane_state_release(dm_plane_state-&gt;dc_state);</div><div class='ctx'> </div><div class='ctx'> 	drm_atomic_helper_plane_destroy_state(plane, state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+static void</div><div class='add'>+dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,</div><div class='add'>+					     struct drm_plane *plane)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_mode_info mode_info = dm-&gt;adev-&gt;mode_info;</div><div class='add'>+	struct dpp_color_caps dpp_color_caps = dm-&gt;dc-&gt;caps.color.dpp;</div><div class='add'>+</div><div class='add'>+	/* Check HW color pipeline capabilities on DPP block (pre-blending)</div><div class='add'>+	 * before exposing related properties.</div><div class='add'>+	 */</div><div class='add'>+	if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) {</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_degamma_lut_property,</div><div class='add'>+					   0);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_degamma_lut_size_property,</div><div class='add'>+					   MAX_COLOR_LUT_ENTRIES);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   dm-&gt;adev-&gt;mode_info.plane_degamma_tf_property,</div><div class='add'>+					   AMDGPU_TRANSFER_FUNCTION_DEFAULT);</div><div class='add'>+	}</div><div class='add'>+	/* HDR MULT is always available */</div><div class='add'>+	drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+				   dm-&gt;adev-&gt;mode_info.plane_hdr_mult_property,</div><div class='add'>+				   AMDGPU_HDR_MULT_DEFAULT);</div><div class='add'>+</div><div class='add'>+	/* Only enable plane CTM if both DPP and MPC gamut remap is available. */</div><div class='add'>+	if (dm-&gt;dc-&gt;caps.color.mpc.gamut_remap)</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   dm-&gt;adev-&gt;mode_info.plane_ctm_property, 0);</div><div class='add'>+</div><div class='add'>+	if (dpp_color_caps.hw_3d_lut) {</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_shaper_lut_property, 0);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_shaper_lut_size_property,</div><div class='add'>+					   MAX_COLOR_LUT_ENTRIES);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_shaper_tf_property,</div><div class='add'>+					   AMDGPU_TRANSFER_FUNCTION_DEFAULT);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_lut3d_property, 0);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_lut3d_size_property,</div><div class='add'>+					   MAX_COLOR_3DLUT_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dpp_color_caps.ogam_ram) {</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_blend_lut_property, 0);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_blend_lut_size_property,</div><div class='add'>+					   MAX_COLOR_LUT_ENTRIES);</div><div class='add'>+		drm_object_attach_property(&amp;plane-&gt;base,</div><div class='add'>+					   mode_info.plane_blend_tf_property,</div><div class='add'>+					   AMDGPU_TRANSFER_FUNCTION_DEFAULT);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dm_atomic_plane_set_property(struct drm_plane *plane,</div><div class='add'>+			     struct drm_plane_state *state,</div><div class='add'>+			     struct drm_property *property,</div><div class='add'>+			     uint64_t val)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(plane-&gt;dev);</div><div class='add'>+	bool replaced = false;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (property == adev-&gt;mode_info.plane_degamma_lut_property) {</div><div class='add'>+		ret = drm_property_replace_blob_from_id(plane-&gt;dev,</div><div class='add'>+							&amp;dm_plane_state-&gt;degamma_lut,</div><div class='add'>+							val, -1,</div><div class='add'>+							sizeof(struct drm_color_lut),</div><div class='add'>+							&amp;replaced);</div><div class='add'>+		dm_plane_state-&gt;base.color_mgmt_changed |= replaced;</div><div class='add'>+		return ret;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_degamma_tf_property) {</div><div class='add'>+		if (dm_plane_state-&gt;degamma_tf != val) {</div><div class='add'>+			dm_plane_state-&gt;degamma_tf = val;</div><div class='add'>+			dm_plane_state-&gt;base.color_mgmt_changed = 1;</div><div class='add'>+		}</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_hdr_mult_property) {</div><div class='add'>+		if (dm_plane_state-&gt;hdr_mult != val) {</div><div class='add'>+			dm_plane_state-&gt;hdr_mult = val;</div><div class='add'>+			dm_plane_state-&gt;base.color_mgmt_changed = 1;</div><div class='add'>+		}</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_ctm_property) {</div><div class='add'>+		ret = drm_property_replace_blob_from_id(plane-&gt;dev,</div><div class='add'>+							&amp;dm_plane_state-&gt;ctm,</div><div class='add'>+							val,</div><div class='add'>+							sizeof(struct drm_color_ctm_3x4), -1,</div><div class='add'>+							&amp;replaced);</div><div class='add'>+		dm_plane_state-&gt;base.color_mgmt_changed |= replaced;</div><div class='add'>+		return ret;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_shaper_lut_property) {</div><div class='add'>+		ret = drm_property_replace_blob_from_id(plane-&gt;dev,</div><div class='add'>+							&amp;dm_plane_state-&gt;shaper_lut,</div><div class='add'>+							val, -1,</div><div class='add'>+							sizeof(struct drm_color_lut),</div><div class='add'>+							&amp;replaced);</div><div class='add'>+		dm_plane_state-&gt;base.color_mgmt_changed |= replaced;</div><div class='add'>+		return ret;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_shaper_tf_property) {</div><div class='add'>+		if (dm_plane_state-&gt;shaper_tf != val) {</div><div class='add'>+			dm_plane_state-&gt;shaper_tf = val;</div><div class='add'>+			dm_plane_state-&gt;base.color_mgmt_changed = 1;</div><div class='add'>+		}</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_lut3d_property) {</div><div class='add'>+		ret = drm_property_replace_blob_from_id(plane-&gt;dev,</div><div class='add'>+							&amp;dm_plane_state-&gt;lut3d,</div><div class='add'>+							val, -1,</div><div class='add'>+							sizeof(struct drm_color_lut),</div><div class='add'>+							&amp;replaced);</div><div class='add'>+		dm_plane_state-&gt;base.color_mgmt_changed |= replaced;</div><div class='add'>+		return ret;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_blend_lut_property) {</div><div class='add'>+		ret = drm_property_replace_blob_from_id(plane-&gt;dev,</div><div class='add'>+							&amp;dm_plane_state-&gt;blend_lut,</div><div class='add'>+							val, -1,</div><div class='add'>+							sizeof(struct drm_color_lut),</div><div class='add'>+							&amp;replaced);</div><div class='add'>+		dm_plane_state-&gt;base.color_mgmt_changed |= replaced;</div><div class='add'>+		return ret;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_blend_tf_property) {</div><div class='add'>+		if (dm_plane_state-&gt;blend_tf != val) {</div><div class='add'>+			dm_plane_state-&gt;blend_tf = val;</div><div class='add'>+			dm_plane_state-&gt;base.color_mgmt_changed = 1;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		drm_dbg_atomic(plane-&gt;dev,</div><div class='add'>+			       "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n",</div><div class='add'>+			       plane-&gt;base.id, plane-&gt;name,</div><div class='add'>+			       property-&gt;base.id, property-&gt;name);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dm_atomic_plane_get_property(struct drm_plane *plane,</div><div class='add'>+			     const struct drm_plane_state *state,</div><div class='add'>+			     struct drm_property *property,</div><div class='add'>+			     uint64_t *val)</div><div class='add'>+{</div><div class='add'>+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(plane-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (property == adev-&gt;mode_info.plane_degamma_lut_property) {</div><div class='add'>+		*val = (dm_plane_state-&gt;degamma_lut) ?</div><div class='add'>+			dm_plane_state-&gt;degamma_lut-&gt;base.id : 0;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_degamma_tf_property) {</div><div class='add'>+		*val = dm_plane_state-&gt;degamma_tf;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_hdr_mult_property) {</div><div class='add'>+		*val = dm_plane_state-&gt;hdr_mult;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_ctm_property) {</div><div class='add'>+		*val = (dm_plane_state-&gt;ctm) ?</div><div class='add'>+			dm_plane_state-&gt;ctm-&gt;base.id : 0;</div><div class='add'>+	} else 	if (property == adev-&gt;mode_info.plane_shaper_lut_property) {</div><div class='add'>+		*val = (dm_plane_state-&gt;shaper_lut) ?</div><div class='add'>+			dm_plane_state-&gt;shaper_lut-&gt;base.id : 0;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_shaper_tf_property) {</div><div class='add'>+		*val = dm_plane_state-&gt;shaper_tf;</div><div class='add'>+	} else 	if (property == adev-&gt;mode_info.plane_lut3d_property) {</div><div class='add'>+		*val = (dm_plane_state-&gt;lut3d) ?</div><div class='add'>+			dm_plane_state-&gt;lut3d-&gt;base.id : 0;</div><div class='add'>+	} else 	if (property == adev-&gt;mode_info.plane_blend_lut_property) {</div><div class='add'>+		*val = (dm_plane_state-&gt;blend_lut) ?</div><div class='add'>+			dm_plane_state-&gt;blend_lut-&gt;base.id : 0;</div><div class='add'>+	} else if (property == adev-&gt;mode_info.plane_blend_tf_property) {</div><div class='add'>+		*val = dm_plane_state-&gt;blend_tf;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> static const struct drm_plane_funcs dm_plane_funcs = {</div><div class='ctx'> 	.update_plane	= drm_atomic_helper_update_plane,</div><div class='ctx'> 	.disable_plane	= drm_atomic_helper_disable_plane,</div><div class='hunk'>@@ -1438,6 +1659,10 @@ static const struct drm_plane_funcs dm_plane_funcs = {</div><div class='ctx'> 	.atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,</div><div class='ctx'> 	.atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,</div><div class='ctx'> 	.format_mod_supported = amdgpu_dm_plane_format_mod_supported,</div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+	.atomic_set_property = dm_atomic_plane_set_property,</div><div class='add'>+	.atomic_get_property = dm_atomic_plane_get_property,</div><div class='add'>+#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='hunk'>@@ -1517,6 +1742,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,</div><div class='ctx'> </div><div class='ctx'> 	drm_plane_helper_add(plane, &amp;dm_plane_helper_funcs);</div><div class='ctx'> </div><div class='add'>+#ifdef AMD_PRIVATE_COLOR</div><div class='add'>+	dm_atomic_plane_attach_color_mgmt_properties(dm, plane);</div><div class='add'>+#endif</div><div class='ctx'> 	/* Create (reset) the plane state */</div><div class='ctx'> 	if (plane-&gt;funcs-&gt;reset)</div><div class='ctx'> 		plane-&gt;funcs-&gt;reset(plane);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c<br/>index 08ce3bb8f640..1f08c6564c3b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c</a></div><div class='hunk'>@@ -51,6 +51,9 @@ static bool link_supports_psrsu(struct dc_link *link)</div><div class='ctx'> 	    !link-&gt;dpcd_caps.psr_info.psr2_su_y_granularity_cap)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	if (amdgpu_dc_debug_mask &amp; DC_DISABLE_PSR_SU)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	return dc_dmub_check_min_version(dc-&gt;ctx-&gt;dmub_srv-&gt;dmub);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c<br/>new file mode 100644<br/>index 000000000000..16e72d623630<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c</a></div><div class='hunk'>@@ -0,0 +1,216 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dm_services_types.h"</div><div class='add'>+</div><div class='add'>+#include "amdgpu.h"</div><div class='add'>+#include "amdgpu_dm.h"</div><div class='add'>+#include "amdgpu_dm_wb.h"</div><div class='add'>+#include "amdgpu_display.h"</div><div class='add'>+#include "dc.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='add'>+#include &lt;drm/drm_atomic_state_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='add'>+</div><div class='add'>+static const u32 amdgpu_dm_wb_formats[] = {</div><div class='add'>+	DRM_FORMAT_XRGB2101010,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder,</div><div class='add'>+					struct drm_crtc_state *crtc_state,</div><div class='add'>+					struct drm_connector_state *conn_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	const struct drm_display_mode *mode = &amp;crtc_state-&gt;mode;</div><div class='add'>+	bool found = false;</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	if (!conn_state-&gt;writeback_job || !conn_state-&gt;writeback_job-&gt;fb)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	fb = conn_state-&gt;writeback_job-&gt;fb;</div><div class='add'>+	if (fb-&gt;width != mode-&gt;hdisplay || fb-&gt;height != mode-&gt;vdisplay) {</div><div class='add'>+		DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",</div><div class='add'>+			      fb-&gt;width, fb-&gt;height);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; sizeof(amdgpu_dm_wb_formats) / sizeof(u32); i++) {</div><div class='add'>+		if (fb-&gt;format-&gt;format == amdgpu_dm_wb_formats[i])</div><div class='add'>+			found = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!found) {</div><div class='add'>+		DRM_DEBUG_KMS("Invalid pixel format %p4cc\n",</div><div class='add'>+			      &amp;fb-&gt;format-&gt;format);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+</div><div class='add'>+	return drm_add_modes_noedid(connector, dev-&gt;mode_config.max_width,</div><div class='add'>+				    dev-&gt;mode_config.max_height);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector,</div><div class='add'>+			       struct drm_writeback_job *job)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_framebuffer *afb;</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='add'>+	struct amdgpu_device *adev;</div><div class='add'>+	struct amdgpu_bo *rbo;</div><div class='add'>+	uint32_t domain;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!job-&gt;fb) {</div><div class='add'>+		DRM_DEBUG_KMS("No FB bound\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	afb = to_amdgpu_framebuffer(job-&gt;fb);</div><div class='add'>+	obj = job-&gt;fb-&gt;obj[0];</div><div class='add'>+	rbo = gem_to_amdgpu_bo(obj);</div><div class='add'>+	adev = amdgpu_ttm_adev(rbo-&gt;tbo.bdev);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_reserve(rbo, true);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "fail to reserve bo (%d)\n", r);</div><div class='add'>+		return r;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = dma_resv_reserve_fences(rbo-&gt;tbo.base.resv, 1);</div><div class='add'>+	if (r) {</div><div class='add'>+		dev_err(adev-&gt;dev, "reserving fence slot failed (%d)\n", r);</div><div class='add'>+		goto error_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	domain = amdgpu_display_supported_domains(adev, rbo-&gt;flags);</div><div class='add'>+</div><div class='add'>+	r = amdgpu_bo_pin(rbo, domain);</div><div class='add'>+	if (unlikely(r != 0)) {</div><div class='add'>+		if (r != -ERESTARTSYS)</div><div class='add'>+			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);</div><div class='add'>+		goto error_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = amdgpu_ttm_alloc_gart(&amp;rbo-&gt;tbo);</div><div class='add'>+	if (unlikely(r != 0)) {</div><div class='add'>+		DRM_ERROR("%p bind failed\n", rbo);</div><div class='add'>+		goto error_unpin;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unreserve(rbo);</div><div class='add'>+</div><div class='add'>+	afb-&gt;address = amdgpu_bo_gpu_offset(rbo);</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_ref(rbo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_unpin:</div><div class='add'>+	amdgpu_bo_unpin(rbo);</div><div class='add'>+</div><div class='add'>+error_unlock:</div><div class='add'>+	amdgpu_bo_unreserve(rbo);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector,</div><div class='add'>+				struct drm_writeback_job *job)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_bo *rbo;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	if (!job-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	rbo = gem_to_amdgpu_bo(job-&gt;fb-&gt;obj[0]);</div><div class='add'>+	r = amdgpu_bo_reserve(rbo, false);</div><div class='add'>+	if (unlikely(r)) {</div><div class='add'>+		DRM_ERROR("failed to reserve rbo before unpin\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	amdgpu_bo_unpin(rbo);</div><div class='add'>+	amdgpu_bo_unreserve(rbo);</div><div class='add'>+	amdgpu_bo_unref(&amp;rbo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = {</div><div class='add'>+	.atomic_check = amdgpu_dm_wb_encoder_atomic_check,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = {</div><div class='add'>+	.fill_modes = drm_helper_probe_single_connector_modes,</div><div class='add'>+	.destroy = drm_connector_cleanup,</div><div class='add'>+	.reset = amdgpu_dm_connector_funcs_reset,</div><div class='add'>+	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,</div><div class='add'>+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = {</div><div class='add'>+	.get_modes = amdgpu_dm_wb_connector_get_modes,</div><div class='add'>+	.prepare_writeback_job = amdgpu_dm_wb_prepare_job,</div><div class='add'>+	.cleanup_writeback_job = amdgpu_dm_wb_cleanup_job,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm,</div><div class='add'>+				struct amdgpu_dm_wb_connector *wbcon,</div><div class='add'>+				uint32_t link_index)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = dm-&gt;dc;</div><div class='add'>+	struct dc_link *link = dc_get_link_at_index(dc, link_index);</div><div class='add'>+	int res = 0;</div><div class='add'>+</div><div class='add'>+	wbcon-&gt;link = link;</div><div class='add'>+</div><div class='add'>+	drm_connector_helper_add(&amp;wbcon-&gt;base.base, &amp;amdgpu_dm_wb_conn_helper_funcs);</div><div class='add'>+</div><div class='add'>+	res = drm_writeback_connector_init(&amp;dm-&gt;adev-&gt;ddev, &amp;wbcon-&gt;base,</div><div class='add'>+					    &amp;amdgpu_dm_wb_connector_funcs,</div><div class='add'>+					    &amp;amdgpu_dm_wb_encoder_helper_funcs,</div><div class='add'>+					    amdgpu_dm_wb_formats,</div><div class='add'>+					    ARRAY_SIZE(amdgpu_dm_wb_formats),</div><div class='add'>+					    amdgpu_dm_get_encoder_crtc_mask(dm-&gt;adev));</div><div class='add'>+</div><div class='add'>+	if (res)</div><div class='add'>+		return res;</div><div class='add'>+	/*</div><div class='add'>+	 * Some of the properties below require access to state, like bpc.</div><div class='add'>+	 * Allocate some default initial connector state with our reset helper.</div><div class='add'>+	 */</div><div class='add'>+	if (wbcon-&gt;base.base.funcs-&gt;reset)</div><div class='add'>+		wbcon-&gt;base.base.funcs-&gt;reset(&amp;wbcon-&gt;base.base);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h<br/>new file mode 100644<br/>index 000000000000..13d31c857dee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_DM_WB_H__</div><div class='add'>+#define __AMDGPU_DM_WB_H__</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_writeback.h&gt;</div><div class='add'>+</div><div class='add'>+int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm,</div><div class='add'>+				struct amdgpu_dm_wb_connector *dm_wbcon,</div><div class='add'>+				uint32_t link_index);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile<br/>index 3a169b78e7e4..7991ae468f75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/Makefile</a></div><div class='hunk'>@@ -22,7 +22,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for Display Core (dc) component.</div><div class='ctx'> </div><div class='del'>-DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc</div><div class='add'>+DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> </div><div class='hunk'>@@ -34,12 +34,8 @@ DC_LIBS += dcn21</div><div class='ctx'> DC_LIBS += dcn201</div><div class='ctx'> DC_LIBS += dcn30</div><div class='ctx'> DC_LIBS += dcn301</div><div class='del'>-DC_LIBS += dcn302</div><div class='del'>-DC_LIBS += dcn303</div><div class='ctx'> DC_LIBS += dcn31</div><div class='ctx'> DC_LIBS += dcn314</div><div class='del'>-DC_LIBS += dcn315</div><div class='del'>-DC_LIBS += dcn316</div><div class='ctx'> DC_LIBS += dcn32</div><div class='ctx'> DC_LIBS += dcn321</div><div class='ctx'> DC_LIBS += dcn35</div><div class='hunk'>@@ -51,7 +47,6 @@ DC_LIBS += dce120</div><div class='ctx'> </div><div class='ctx'> DC_LIBS += dce112</div><div class='ctx'> DC_LIBS += dce110</div><div class='del'>-DC_LIBS += dce100</div><div class='ctx'> DC_LIBS += dce80</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_DRM_AMD_DC_SI</div><div class='hunk'>@@ -65,7 +60,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI</div><div class='ctx'> include $(AMD_DC)</div><div class='ctx'> </div><div class='ctx'> DISPLAY_CORE = dc.o dc_stat.o dc_resource.o dc_hw_sequencer.o dc_sink.o \</div><div class='del'>-dc_surface.o dc_debug.o dc_stream.o dc_link_enc_cfg.o dc_link_exports.o</div><div class='add'>+dc_surface.o dc_debug.o dc_stream.o dc_link_enc_cfg.o dc_link_exports.o dc_state.o</div><div class='ctx'> </div><div class='ctx'> DISPLAY_CORE += dc_vm_helper.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c<br/>index e295a839ab47..1090d235086a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/basics/conversion.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/basics/conversion.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/basics/conversion.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/basics/conversion.c</a></div><div class='hunk'>@@ -103,7 +103,8 @@ void convert_float_matrix(</div><div class='ctx'> </div><div class='ctx'> static uint32_t find_gcd(uint32_t a, uint32_t b)</div><div class='ctx'> {</div><div class='del'>-	uint32_t remainder = 0;</div><div class='add'>+	uint32_t remainder;</div><div class='add'>+</div><div class='ctx'> 	while (b != 0) {</div><div class='ctx'> 		remainder = a % b;</div><div class='ctx'> 		a = b;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c<br/>index 7cdb1a8a0ba0..960c4b4f6ddf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c</a></div><div class='hunk'>@@ -1014,13 +1014,20 @@ static enum bp_result get_ss_info_v4_5(</div><div class='ctx'> 		DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info-&gt;spread_spectrum_percentage);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AS_SIGNAL_TYPE_DISPLAY_PORT:</div><div class='del'>-		ss_info-&gt;spread_spectrum_percentage =</div><div class='add'>+		if (bp-&gt;base.integrated_info) {</div><div class='add'>+			DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp-&gt;base.integrated_info-&gt;gpuclk_ss_percentage);</div><div class='add'>+			ss_info-&gt;spread_spectrum_percentage =</div><div class='add'>+					bp-&gt;base.integrated_info-&gt;gpuclk_ss_percentage;</div><div class='add'>+			ss_info-&gt;type.CENTER_MODE =</div><div class='add'>+					bp-&gt;base.integrated_info-&gt;gpuclk_ss_type;</div><div class='add'>+		} else {</div><div class='add'>+			ss_info-&gt;spread_spectrum_percentage =</div><div class='ctx'> 				disp_cntl_tbl-&gt;dp_ss_percentage;</div><div class='del'>-		ss_info-&gt;spread_spectrum_range =</div><div class='add'>+			ss_info-&gt;spread_spectrum_range =</div><div class='ctx'> 				disp_cntl_tbl-&gt;dp_ss_rate_10hz * 10;</div><div class='del'>-		if (disp_cntl_tbl-&gt;dp_ss_mode &amp; ATOM_SS_CENTRE_SPREAD_MODE)</div><div class='del'>-			ss_info-&gt;type.CENTER_MODE = true;</div><div class='del'>-</div><div class='add'>+			if (disp_cntl_tbl-&gt;dp_ss_mode &amp; ATOM_SS_CENTRE_SPREAD_MODE)</div><div class='add'>+				ss_info-&gt;type.CENTER_MODE = true;</div><div class='add'>+		}</div><div class='ctx'> 		DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info-&gt;spread_spectrum_percentage);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case AS_SIGNAL_TYPE_GPU_PLL:</div><div class='hunk'>@@ -1691,7 +1698,7 @@ static enum bp_result bios_parser_enable_disp_power_gating(</div><div class='ctx'> static enum bp_result bios_parser_enable_lvtma_control(</div><div class='ctx'> 	struct dc_bios *dcb,</div><div class='ctx'> 	uint8_t uc_pwr_on,</div><div class='del'>-	uint8_t panel_instance,</div><div class='add'>+	uint8_t pwrseq_instance,</div><div class='ctx'> 	uint8_t bypass_panel_control_wait)</div><div class='ctx'> {</div><div class='ctx'> 	struct bios_parser *bp = BP_FROM_DCB(dcb);</div><div class='hunk'>@@ -1699,7 +1706,7 @@ static enum bp_result bios_parser_enable_lvtma_control(</div><div class='ctx'> 	if (!bp-&gt;cmd_tbl.enable_lvtma_control)</div><div class='ctx'> 		return BP_RESULT_FAILURE;</div><div class='ctx'> </div><div class='del'>-	return bp-&gt;cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance, bypass_panel_control_wait);</div><div class='add'>+	return bp-&gt;cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool bios_parser_is_accelerated_mode(</div><div class='hunk'>@@ -2214,22 +2221,22 @@ static enum bp_result bios_parser_get_disp_connector_caps_info(</div><div class='ctx'> </div><div class='ctx'> 	switch (bp-&gt;object_info_tbl.revision.minor) {</div><div class='ctx'> 	case 4:</div><div class='del'>-	    default:</div><div class='del'>-		    object = get_bios_object(bp, object_id);</div><div class='del'>-</div><div class='del'>-		    if (!object)</div><div class='del'>-			    return BP_RESULT_BADINPUT;</div><div class='del'>-</div><div class='del'>-		    record = get_disp_connector_caps_record(bp, object);</div><div class='del'>-		    if (!record)</div><div class='del'>-			    return BP_RESULT_NORECORD;</div><div class='del'>-</div><div class='del'>-		    info-&gt;INTERNAL_DISPLAY =</div><div class='del'>-			    (record-&gt;connectcaps &amp; ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;</div><div class='del'>-		    info-&gt;INTERNAL_DISPLAY_BL =</div><div class='del'>-			    (record-&gt;connectcaps &amp; ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;</div><div class='del'>-		    break;</div><div class='del'>-	    case 5:</div><div class='add'>+		default:</div><div class='add'>+			object = get_bios_object(bp, object_id);</div><div class='add'>+</div><div class='add'>+			if (!object)</div><div class='add'>+				return BP_RESULT_BADINPUT;</div><div class='add'>+</div><div class='add'>+			record = get_disp_connector_caps_record(bp, object);</div><div class='add'>+			if (!record)</div><div class='add'>+				return BP_RESULT_NORECORD;</div><div class='add'>+</div><div class='add'>+			info-&gt;INTERNAL_DISPLAY =</div><div class='add'>+				(record-&gt;connectcaps &amp; ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;</div><div class='add'>+			info-&gt;INTERNAL_DISPLAY_BL =</div><div class='add'>+				(record-&gt;connectcaps &amp; ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;</div><div class='add'>+			break;</div><div class='add'>+	case 5:</div><div class='ctx'> 		object_path_v3 = get_bios_object_from_path_v3(bp, object_id);</div><div class='ctx'> </div><div class='ctx'> 		if (!object_path_v3)</div><div class='hunk'>@@ -2391,7 +2398,6 @@ static enum bp_result get_vram_info_v30(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * get_integrated_info_v11</div><div class='ctx'>  *</div><div class='hunk'>@@ -2814,6 +2820,8 @@ static enum bp_result get_integrated_info_v2_2(</div><div class='ctx'> 	info-&gt;ma_channel_number = info_v2_2-&gt;umachannelnumber;</div><div class='ctx'> 	info-&gt;dp_ss_control =</div><div class='ctx'> 		le16_to_cpu(info_v2_2-&gt;reserved1);</div><div class='add'>+	info-&gt;gpuclk_ss_percentage = info_v2_2-&gt;gpuclk_ss_percentage;</div><div class='add'>+	info-&gt;gpuclk_ss_type = info_v2_2-&gt;gpuclk_ss_type;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NUMBER_OF_UCHAR_FOR_GUID; ++i) {</div><div class='ctx'> 		info-&gt;ext_disp_conn_info.gu_id[i] =</div><div class='hunk'>@@ -3323,27 +3331,28 @@ static enum bp_result get_bracket_layout_record(</div><div class='ctx'> 		DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");</div><div class='ctx'> 		return BP_RESULT_BADINPUT;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	tbl = &amp;bp-&gt;object_info_tbl;</div><div class='ctx'> 	v1_4 = tbl-&gt;v1_4;</div><div class='ctx'> 	v1_5 = tbl-&gt;v1_5;</div><div class='ctx'> </div><div class='ctx'> 	result = BP_RESULT_NORECORD;</div><div class='ctx'> 	switch (bp-&gt;object_info_tbl.revision.minor) {</div><div class='del'>-		case 4:</div><div class='del'>-		default:</div><div class='del'>-			for (i = 0; i &lt; v1_4-&gt;number_of_path; ++i)	{</div><div class='del'>-				if (bracket_layout_id ==</div><div class='del'>-					v1_4-&gt;display_path[i].display_objid) {</div><div class='del'>-					result = update_slot_layout_info(dcb, i, slot_layout_info);</div><div class='del'>-					break;</div><div class='del'>-				}</div><div class='add'>+	case 4:</div><div class='add'>+	default:</div><div class='add'>+		for (i = 0; i &lt; v1_4-&gt;number_of_path; ++i) {</div><div class='add'>+			if (bracket_layout_id == v1_4-&gt;display_path[i].display_objid) {</div><div class='add'>+				result = update_slot_layout_info(dcb, i, slot_layout_info);</div><div class='add'>+				break;</div><div class='ctx'> 			}</div><div class='del'>-		    break;</div><div class='del'>-		case 5:</div><div class='del'>-			for (i = 0; i &lt; v1_5-&gt;number_of_path; ++i)</div><div class='del'>-				result = update_slot_layout_info_v2(dcb, i, slot_layout_info);</div><div class='del'>-			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 5:</div><div class='add'>+		for (i = 0; i &lt; v1_5-&gt;number_of_path; ++i)</div><div class='add'>+			result = update_slot_layout_info_v2(dcb, i, slot_layout_info);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3352,9 +3361,7 @@ static enum bp_result bios_get_board_layout_info(</div><div class='ctx'> 	struct board_layout_info *board_layout_info)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-</div><div class='ctx'> 	struct bios_parser *bp;</div><div class='del'>-</div><div class='ctx'> 	static enum bp_result record_result;</div><div class='ctx'> 	unsigned int max_slots;</div><div class='ctx'> </div><div class='hunk'>@@ -3364,7 +3371,6 @@ static enum bp_result bios_get_board_layout_info(</div><div class='ctx'> 		0, 0</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> 	bp = BP_FROM_DCB(dcb);</div><div class='ctx'> </div><div class='ctx'> 	if (board_layout_info == NULL) {</div><div class='hunk'>@@ -3545,7 +3551,6 @@ static const struct dc_vbios_funcs vbios_funcs = {</div><div class='ctx'> 	.bios_parser_destroy = firmware_parser_destroy,</div><div class='ctx'> </div><div class='ctx'> 	.get_board_layout_info = bios_get_board_layout_info,</div><div class='del'>-	/* TODO: use this fn in hw init?*/</div><div class='ctx'> 	.pack_data_tables = bios_parser_pack_data_tables,</div><div class='ctx'> </div><div class='ctx'> 	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c<br/>index 90a02d7bd3da..293a919d605d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/command_table2.c</a></div><div class='hunk'>@@ -123,7 +123,7 @@ static void encoder_control_dmcub(</div><div class='ctx'> 		sizeof(cmd.digx_encoder_control.header);</div><div class='ctx'> 	cmd.digx_encoder_control.encoder_control.dig.stream_param = *dig;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result encoder_control_digx_v1_5(</div><div class='hunk'>@@ -259,7 +259,7 @@ static void transmitter_control_dmcub(</div><div class='ctx'> 		sizeof(cmd.dig1_transmitter_control.header);</div><div class='ctx'> 	cmd.dig1_transmitter_control.transmitter_control.dig = *dig;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result transmitter_control_v1_6(</div><div class='hunk'>@@ -321,7 +321,7 @@ static void transmitter_control_dmcub_v1_7(</div><div class='ctx'> 		sizeof(cmd.dig1_transmitter_control.header);</div><div class='ctx'> 	cmd.dig1_transmitter_control.transmitter_control.dig_v1_7 = *dig;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result transmitter_control_v1_7(</div><div class='hunk'>@@ -429,7 +429,7 @@ static void set_pixel_clock_dmcub(</div><div class='ctx'> 		sizeof(cmd.set_pixel_clock.header);</div><div class='ctx'> 	cmd.set_pixel_clock.pixel_clock.clk = *clk;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result set_pixel_clock_v7(</div><div class='hunk'>@@ -796,7 +796,7 @@ static void enable_disp_power_gating_dmcub(</div><div class='ctx'> 		sizeof(cmd.enable_disp_power_gating.header);</div><div class='ctx'> 	cmd.enable_disp_power_gating.power_gating.pwr = *pwr;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result enable_disp_power_gating_v2_1(</div><div class='hunk'>@@ -976,7 +976,7 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)</div><div class='ctx'> static enum bp_result enable_lvtma_control(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	uint8_t uc_pwr_on,</div><div class='del'>-	uint8_t panel_instance,</div><div class='add'>+	uint8_t pwrseq_instance,</div><div class='ctx'> 	uint8_t bypass_panel_control_wait);</div><div class='ctx'> </div><div class='ctx'> static void init_enable_lvtma_control(struct bios_parser *bp)</div><div class='hunk'>@@ -989,7 +989,7 @@ static void init_enable_lvtma_control(struct bios_parser *bp)</div><div class='ctx'> static void enable_lvtma_control_dmcub(</div><div class='ctx'> 	struct dc_dmub_srv *dmcub,</div><div class='ctx'> 	uint8_t uc_pwr_on,</div><div class='del'>-	uint8_t panel_instance,</div><div class='add'>+	uint8_t pwrseq_instance,</div><div class='ctx'> 	uint8_t bypass_panel_control_wait)</div><div class='ctx'> {</div><div class='ctx'> </div><div class='hunk'>@@ -1002,17 +1002,17 @@ static void enable_lvtma_control_dmcub(</div><div class='ctx'> 			DMUB_CMD__VBIOS_LVTMA_CONTROL;</div><div class='ctx'> 	cmd.lvtma_control.data.uc_pwr_action =</div><div class='ctx'> 			uc_pwr_on;</div><div class='del'>-	cmd.lvtma_control.data.panel_inst =</div><div class='del'>-			panel_instance;</div><div class='add'>+	cmd.lvtma_control.data.pwrseq_inst =</div><div class='add'>+			pwrseq_instance;</div><div class='ctx'> 	cmd.lvtma_control.data.bypass_panel_control_wait =</div><div class='ctx'> 			bypass_panel_control_wait;</div><div class='del'>-	dm_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmcub-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum bp_result enable_lvtma_control(</div><div class='ctx'> 	struct bios_parser *bp,</div><div class='ctx'> 	uint8_t uc_pwr_on,</div><div class='del'>-	uint8_t panel_instance,</div><div class='add'>+	uint8_t pwrseq_instance,</div><div class='ctx'> 	uint8_t bypass_panel_control_wait)</div><div class='ctx'> {</div><div class='ctx'> 	enum bp_result result = BP_RESULT_FAILURE;</div><div class='hunk'>@@ -1021,7 +1021,7 @@ static enum bp_result enable_lvtma_control(</div><div class='ctx'> 	    bp-&gt;base.ctx-&gt;dc-&gt;debug.dmub_command_table) {</div><div class='ctx'> 		enable_lvtma_control_dmcub(bp-&gt;base.ctx-&gt;dmub_srv,</div><div class='ctx'> 				uc_pwr_on,</div><div class='del'>-				panel_instance,</div><div class='add'>+				pwrseq_instance,</div><div class='ctx'> 				bypass_panel_control_wait);</div><div class='ctx'> 		return BP_RESULT_OK;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h<br/>index b6d09bf6cf72..41c8c014397f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/bios/command_table2.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/bios/command_table2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/bios/command_table2.h</a></div><div class='hunk'>@@ -96,7 +96,7 @@ struct cmd_tbl {</div><div class='ctx'> 			struct bios_parser *bp, uint8_t id);</div><div class='ctx'> 	enum bp_result (*enable_lvtma_control)(struct bios_parser *bp,</div><div class='ctx'> 			uint8_t uc_pwr_on,</div><div class='del'>-			uint8_t panel_instance,</div><div class='add'>+			uint8_t pwrseq_instance,</div><div class='ctx'> 			uint8_t bypass_panel_control_wait);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c<br/>index 3e73c4e59d40..28a2a837d2f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include "dc_types.h"</div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> #include "link.h"</div><div class='ctx'> </div><div class='ctx'> #include "dce100/dce_clk_mgr.h"</div><div class='hunk'>@@ -63,7 +64,7 @@ int clk_mgr_helper_get_active_display_cnt(</div><div class='ctx'> 		/* Don't count SubVP phantom pipes as part of active</div><div class='ctx'> 		 * display count</div><div class='ctx'> 		 */</div><div class='del'>-		if (stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -368,7 +369,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p</div><div class='ctx'> 	}</div><div class='ctx'> 	break;</div><div class='ctx'> </div><div class='del'>-#endif /* CONFIG_DRM_AMD_DC_FP - Family RV */</div><div class='add'>+#endif	/* CONFIG_DRM_AMD_DC_FP */</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT(0); /* Unknown Asic */</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c<br/>index 3db4ef564b99..ce1386e22576 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c</a></div><div class='hunk'>@@ -253,7 +253,7 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c<br/>index 7326b7565846..a84f1e376dee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c</a></div><div class='hunk'>@@ -87,6 +87,20 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0,</div><div class='ctx'> #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L</div><div class='ctx'> #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L</div><div class='ctx'> </div><div class='add'>+#define regCLK1_CLK2_BYPASS_CNTL			0x029c</div><div class='add'>+#define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX	0</div><div class='add'>+</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT	0x0</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT	0x10</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK		0x00000007L</div><div class='add'>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK		0x000F0000L</div><div class='add'>+</div><div class='add'>+#define regCLK6_0_CLK6_spll_field_8				0x464b</div><div class='add'>+#define regCLK6_0_CLK6_spll_field_8_BASE_IDX	0</div><div class='add'>+</div><div class='add'>+#define CLK6_0_CLK6_spll_field_8__spll_ssc_en__SHIFT	0xd</div><div class='add'>+#define CLK6_0_CLK6_spll_field_8__spll_ssc_en_MASK		0x00002000L</div><div class='add'>+</div><div class='ctx'> #define REG(reg_name) \</div><div class='ctx'> 	(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)</div><div class='ctx'> </div><div class='hunk'>@@ -131,35 +145,63 @@ static int dcn314_get_active_display_cnt_wa(</div><div class='ctx'> 	return display_count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)</div><div class='add'>+static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,</div><div class='add'>+				  bool safe_to_lower, bool disable)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; ++i) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		struct pipe_ctx *pipe = safe_to_lower</div><div class='add'>+			? &amp;context-&gt;res_ctx.pipe_ctx[i]</div><div class='add'>+			: &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;top_pipe || pipe-&gt;prev_odm_pipe)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal))) {</div><div class='del'>-			struct stream_encoder *stream_enc = pipe-&gt;stream_res.stream_enc;</div><div class='del'>-</div><div class='ctx'> 			if (disable) {</div><div class='del'>-				if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;disable_fifo)</div><div class='del'>-					pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;disable_fifo(stream_enc);</div><div class='add'>+				if (pipe-&gt;stream_res.tg &amp;&amp; pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc)</div><div class='add'>+					pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> </div><div class='del'>-				pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> 				reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				pipe-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe-&gt;stream_res.tg);</div><div class='del'>-</div><div class='del'>-				if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;enable_fifo)</div><div class='del'>-					pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;enable_fifo(stream_enc);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='add'>+	uint32_t ssc_enable;</div><div class='add'>+</div><div class='add'>+	REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &amp;ssc_enable);</div><div class='add'>+</div><div class='add'>+	return ssc_enable == 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcn314_init_clocks(struct clk_mgr *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);</div><div class='add'>+	uint32_t ref_dtbclk = clk_mgr-&gt;clks.ref_dtbclk_khz;</div><div class='add'>+</div><div class='add'>+	memset(&amp;(clk_mgr-&gt;clks), 0, sizeof(struct dc_clocks));</div><div class='add'>+	// Assumption is that boot state always supports pstate</div><div class='add'>+	clk_mgr-&gt;clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk</div><div class='add'>+	clk_mgr-&gt;clks.p_state_change_support = true;</div><div class='add'>+	clk_mgr-&gt;clks.prev_p_state_change_support = true;</div><div class='add'>+	clk_mgr-&gt;clks.pwr_state = DCN_PWR_STATE_UNKNOWN;</div><div class='add'>+	clk_mgr-&gt;clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk</div><div class='add'>+	if (dcn314_is_spll_ssc_enabled(clk_mgr))</div><div class='add'>+		clk_mgr-&gt;dp_dto_source_clock_in_khz =</div><div class='add'>+			dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr-&gt;dprefclk_khz);</div><div class='add'>+	else</div><div class='add'>+		clk_mgr-&gt;dp_dto_source_clock_in_khz = clk_mgr-&gt;dprefclk_khz;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 			struct dc_state *context,</div><div class='ctx'> 			bool safe_to_lower)</div><div class='hunk'>@@ -252,11 +294,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (should_set_clock(safe_to_lower, new_clocks-&gt;dispclk_khz, clk_mgr_base-&gt;clks.dispclk_khz)) {</div><div class='del'>-		dcn314_disable_otg_wa(clk_mgr_base, context, true);</div><div class='add'>+		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);</div><div class='ctx'> </div><div class='ctx'> 		clk_mgr_base-&gt;clks.dispclk_khz = new_clocks-&gt;dispclk_khz;</div><div class='ctx'> 		dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base-&gt;clks.dispclk_khz);</div><div class='del'>-		dcn314_disable_otg_wa(clk_mgr_base, context, false);</div><div class='add'>+		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);</div><div class='ctx'> </div><div class='ctx'> 		update_dispclk = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -284,7 +326,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)</div><div class='hunk'>@@ -436,6 +478,11 @@ static DpmClocks314_t dummy_clocks;</div><div class='ctx'> </div><div class='ctx'> static struct dcn314_watermarks dummy_wms = { 0 };</div><div class='ctx'> </div><div class='add'>+static struct dcn314_ss_info_table ss_info_table = {</div><div class='add'>+	.ss_divider = 1000,</div><div class='add'>+	.ss_percentage = {0, 0, 375, 375, 375}</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)</div><div class='ctx'> {</div><div class='ctx'> 	int i, num_valid_sets;</div><div class='hunk'>@@ -708,13 +755,31 @@ static struct clk_mgr_funcs dcn314_funcs = {</div><div class='ctx'> 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,</div><div class='ctx'> 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,</div><div class='ctx'> 	.update_clocks = dcn314_update_clocks,</div><div class='del'>-	.init_clocks = dcn31_init_clocks,</div><div class='add'>+	.init_clocks = dcn314_init_clocks,</div><div class='ctx'> 	.enable_pme_wa = dcn314_enable_pme_wa,</div><div class='ctx'> 	.are_clock_states_equal = dcn314_are_clock_states_equal,</div><div class='ctx'> 	.notify_wm_ranges = dcn314_notify_wm_ranges</div><div class='ctx'> };</div><div class='ctx'> extern struct clk_mgr_funcs dcn3_fpga_funcs;</div><div class='ctx'> </div><div class='add'>+static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)</div><div class='add'>+{</div><div class='add'>+	uint32_t clock_source;</div><div class='add'>+	//uint32_t ssc_enable;</div><div class='add'>+</div><div class='add'>+	REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &amp;clock_source);</div><div class='add'>+	//REG_GET(CLK6_0_CLK6_spll_field_8, spll_ssc_en, &amp;ssc_enable);</div><div class='add'>+</div><div class='add'>+	if (dcn314_is_spll_ssc_enabled(&amp;clk_mgr-&gt;base) &amp;&amp; (clock_source &lt; ARRAY_SIZE(ss_info_table.ss_percentage))) {</div><div class='add'>+		clk_mgr-&gt;dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];</div><div class='add'>+</div><div class='add'>+		if (clk_mgr-&gt;dprefclk_ss_percentage != 0) {</div><div class='add'>+			clk_mgr-&gt;ss_on_dprefclk = true;</div><div class='add'>+			clk_mgr-&gt;dprefclk_ss_divider = ss_info_table.ss_divider;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dcn314_clk_mgr_construct(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct clk_mgr_dcn314 *clk_mgr,</div><div class='hunk'>@@ -782,6 +847,7 @@ void dcn314_clk_mgr_construct(</div><div class='ctx'> 	clk_mgr-&gt;base.base.dprefclk_khz = 600000;</div><div class='ctx'> 	clk_mgr-&gt;base.base.clks.ref_dtbclk_khz = 600000;</div><div class='ctx'> 	dce_clock_read_ss_info(&amp;clk_mgr-&gt;base);</div><div class='add'>+	dcn314_read_ss_info_from_lut(&amp;clk_mgr-&gt;base);</div><div class='ctx'> 	/*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.base.bw_params = &amp;dcn314_bw_params;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h<br/>index 171f84340eb2..002c28e80720 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h</a></div><div class='hunk'>@@ -28,6 +28,8 @@</div><div class='ctx'> #define __DCN314_CLK_MGR_H__</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='ctx'> </div><div class='add'>+#define DCN314_NUM_CLOCK_SOURCES   5</div><div class='add'>+</div><div class='ctx'> struct dcn314_watermarks;</div><div class='ctx'> </div><div class='ctx'> struct dcn314_smu_watermark_set {</div><div class='hunk'>@@ -40,9 +42,18 @@ struct clk_mgr_dcn314 {</div><div class='ctx'> 	struct dcn314_smu_watermark_set smu_wm_set;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn314_ss_info_table {</div><div class='add'>+	uint32_t ss_divider;</div><div class='add'>+	uint32_t ss_percentage[DCN314_NUM_CLOCK_SOURCES];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> bool dcn314_are_clock_states_equal(struct dc_clocks *a,</div><div class='ctx'> 		struct dc_clocks *b);</div><div class='ctx'> </div><div class='add'>+bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);</div><div class='add'>+</div><div class='add'>+void dcn314_init_clocks(struct clk_mgr *clk_mgr);</div><div class='add'>+</div><div class='ctx'> void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 			struct dc_state *context,</div><div class='ctx'> 			bool safe_to_lower);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c<br/>index b2c4f97afc8b..644da4637320 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c</a></div><div class='hunk'>@@ -232,7 +232,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='hunk'>@@ -334,7 +334,7 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_A,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='del'>-			.pstate_latency_us = 11.65333,</div><div class='add'>+			.pstate_latency_us = 129.0,</div><div class='ctx'> 			.sr_exit_time_us = 11.5,</div><div class='ctx'> 			.sr_enter_plus_exit_time_us = 14.5,</div><div class='ctx'> 			.valid = true,</div><div class='hunk'>@@ -342,7 +342,7 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_B,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='del'>-			.pstate_latency_us = 11.65333,</div><div class='add'>+			.pstate_latency_us = 129.0,</div><div class='ctx'> 			.sr_exit_time_us = 11.5,</div><div class='ctx'> 			.sr_enter_plus_exit_time_us = 14.5,</div><div class='ctx'> 			.valid = true,</div><div class='hunk'>@@ -350,7 +350,7 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_C,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='del'>-			.pstate_latency_us = 11.65333,</div><div class='add'>+			.pstate_latency_us = 129.0,</div><div class='ctx'> 			.sr_exit_time_us = 11.5,</div><div class='ctx'> 			.sr_enter_plus_exit_time_us = 14.5,</div><div class='ctx'> 			.valid = true,</div><div class='hunk'>@@ -358,7 +358,7 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_D,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='del'>-			.pstate_latency_us = 11.65333,</div><div class='add'>+			.pstate_latency_us = 129.0,</div><div class='ctx'> 			.sr_exit_time_us = 11.5,</div><div class='ctx'> 			.sr_enter_plus_exit_time_us = 14.5,</div><div class='ctx'> 			.valid = true,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c<br/>index 09151cc56ce4..12f3e8aa46d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c</a></div><div class='hunk'>@@ -239,7 +239,7 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c<br/>index a496930b1f9c..aadd07bc68c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c</a></div><div class='hunk'>@@ -25,7 +25,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "dccg.h"</div><div class='ctx'> #include "clk_mgr_internal.h"</div><div class='del'>-</div><div class='ctx'> #include "dcn32/dcn32_clk_mgr_smu_msg.h"</div><div class='ctx'> #include "dcn20/dcn20_clk_mgr.h"</div><div class='ctx'> #include "dce100/dce_clk_mgr.h"</div><div class='hunk'>@@ -34,7 +33,7 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dm_helpers.h"</div><div class='ctx'> #include "link.h"</div><div class='del'>-</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> #include "atomfirmware.h"</div><div class='ctx'> #include "smu13_driver_if.h"</div><div class='ctx'> </div><div class='hunk'>@@ -458,20 +457,56 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr_internal *clk_mgr)</div><div class='add'>+static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)</div><div class='ctx'> {</div><div class='del'>-    unsigned int dispclk_khz_reg    = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK</div><div class='del'>-    unsigned int dppclk_khz_reg     = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK</div><div class='del'>-    unsigned int dprefclk_khz_reg   = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK</div><div class='del'>-    unsigned int dcfclk_khz_reg     = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK</div><div class='del'>-    unsigned int dtbclk_khz_reg     = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK</div><div class='del'>-    unsigned int fclk_khz_reg       = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK</div><div class='add'>+	bool is_native_scaling = false;</div><div class='add'>+	int width = pipe-&gt;plane_state-&gt;src_rect.width;</div><div class='add'>+	int height = pipe-&gt;plane_state-&gt;src_rect.height;</div><div class='add'>+</div><div class='add'>+	if (pipe-&gt;stream-&gt;timing.h_addressable == width &amp;&amp;</div><div class='add'>+			pipe-&gt;stream-&gt;timing.v_addressable == height &amp;&amp;</div><div class='add'>+			pipe-&gt;plane_state-&gt;dst_rect.width == width &amp;&amp;</div><div class='add'>+			pipe-&gt;plane_state-&gt;dst_rect.height == height)</div><div class='add'>+		is_native_scaling = true;</div><div class='add'>+</div><div class='add'>+	return is_native_scaling;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcn32_auto_dpm_test_log(</div><div class='add'>+		struct dc_clocks *new_clocks,</div><div class='add'>+		struct clk_mgr_internal *clk_mgr,</div><div class='add'>+		struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	unsigned int dispclk_khz_reg, dppclk_khz_reg, dprefclk_khz_reg, dcfclk_khz_reg, dtbclk_khz_reg,</div><div class='add'>+				 fclk_khz_reg, mall_ss_size_bytes;</div><div class='add'>+	int dramclk_khz_override, fclk_khz_override, num_fclk_levels;</div><div class='add'>+</div><div class='add'>+	struct pipe_ctx *pipe_ctx_list[MAX_PIPES];</div><div class='add'>+	int active_pipe_count = 0;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='add'>+			pipe_ctx_list[active_pipe_count] = pipe_ctx;</div><div class='add'>+			active_pipe_count++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mall_ss_size_bytes = context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes;</div><div class='add'>+</div><div class='add'>+    dispclk_khz_reg    = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK</div><div class='add'>+    dppclk_khz_reg     = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK</div><div class='add'>+    dprefclk_khz_reg   = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK</div><div class='add'>+    dcfclk_khz_reg     = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK</div><div class='add'>+    dtbclk_khz_reg     = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK</div><div class='add'>+    fclk_khz_reg       = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK</div><div class='ctx'> </div><div class='ctx'>     // Overrides for these clocks in case there is no p_state change support</div><div class='del'>-    int dramclk_khz_override = new_clocks-&gt;dramclk_khz;</div><div class='del'>-    int fclk_khz_override = new_clocks-&gt;fclk_khz;</div><div class='add'>+    dramclk_khz_override = new_clocks-&gt;dramclk_khz;</div><div class='add'>+    fclk_khz_override = new_clocks-&gt;fclk_khz;</div><div class='ctx'> </div><div class='del'>-    int num_fclk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels - 1;</div><div class='add'>+    num_fclk_levels = clk_mgr-&gt;base.bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels - 1;</div><div class='ctx'> </div><div class='ctx'>     if (!new_clocks-&gt;p_state_change_support) {</div><div class='ctx'> 	    dramclk_khz_override = clk_mgr-&gt;base.bw_params-&gt;max_memclk_mhz * 1000;</div><div class='hunk'>@@ -488,16 +523,49 @@ static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr</div><div class='ctx'> 	//</div><div class='ctx'> 	//				AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"</div><div class='ctx'> 	////////////////////////////////////////////////////////////////////////////</div><div class='del'>-	if (new_clocks &amp;&amp;</div><div class='add'>+	if (new_clocks &amp;&amp; active_pipe_count &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;dramclk_khz &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;fclk_khz &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;dcfclk_khz &gt; 0 &amp;&amp;</div><div class='ctx'> 		new_clocks-&gt;dppclk_khz &gt; 0) {</div><div class='ctx'> </div><div class='add'>+		uint32_t pix_clk_list[MAX_PIPES] = {0};</div><div class='add'>+		int p_state_list[MAX_PIPES] = {0};</div><div class='add'>+		int disp_src_width_list[MAX_PIPES] = {0};</div><div class='add'>+		int disp_src_height_list[MAX_PIPES] = {0};</div><div class='add'>+		uint64_t disp_src_refresh_list[MAX_PIPES] = {0};</div><div class='add'>+		bool is_scaled_list[MAX_PIPES] = {0};</div><div class='add'>+</div><div class='add'>+		for (int i = 0; i &lt; active_pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];</div><div class='add'>+			uint64_t refresh_rate;</div><div class='add'>+</div><div class='add'>+			pix_clk_list[i] = curr_pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz;</div><div class='add'>+			p_state_list[i] = curr_pipe_ctx-&gt;p_state_type;</div><div class='add'>+</div><div class='add'>+			refresh_rate = (curr_pipe_ctx-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='add'>+				curr_pipe_ctx-&gt;stream-&gt;timing.v_total * curr_pipe_ctx-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.v_total);</div><div class='add'>+			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx-&gt;stream-&gt;timing.h_total);</div><div class='add'>+			disp_src_refresh_list[i] = refresh_rate;</div><div class='add'>+</div><div class='add'>+			if (curr_pipe_ctx-&gt;plane_state) {</div><div class='add'>+				is_scaled_list[i] = !(dcn32_check_native_scaling(curr_pipe_ctx));</div><div class='add'>+				disp_src_width_list[i] = curr_pipe_ctx-&gt;plane_state-&gt;src_rect.width;</div><div class='add'>+				disp_src_height_list[i] = curr_pipe_ctx-&gt;plane_state-&gt;src_rect.height;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "</div><div class='ctx'> 			"dcfclk:%d - dppclk:%d - dispclk_hw:%d - "</div><div class='ctx'> 			"dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "</div><div class='del'>-			"dtbclk_hw:%d - fclk_hw:%d\n",</div><div class='add'>+			"dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "</div><div class='add'>+			"pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "</div><div class='add'>+			"p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "</div><div class='add'>+			"pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "</div><div class='add'>+			"pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "</div><div class='add'>+			"pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "</div><div class='add'>+			"pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",</div><div class='ctx'> 			dramclk_khz_override,</div><div class='ctx'> 			fclk_khz_override,</div><div class='ctx'> 			new_clocks-&gt;dcfclk_khz,</div><div class='hunk'>@@ -507,7 +575,14 @@ static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct clk_mgr</div><div class='ctx'> 			dprefclk_khz_reg,</div><div class='ctx'> 			dcfclk_khz_reg,</div><div class='ctx'> 			dtbclk_khz_reg,</div><div class='del'>-			fclk_khz_reg);</div><div class='add'>+			fclk_khz_reg,</div><div class='add'>+			pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],</div><div class='add'>+			mall_ss_size_bytes,</div><div class='add'>+			p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],</div><div class='add'>+			disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],</div><div class='add'>+			disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],</div><div class='add'>+			disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],</div><div class='add'>+			disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -680,6 +755,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		/* DCCG requires KHz precision for DTBCLK */</div><div class='ctx'> 		clk_mgr_base-&gt;clks.ref_dtbclk_khz =</div><div class='ctx'> 				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks-&gt;ref_dtbclk_khz));</div><div class='add'>+</div><div class='ctx'> 		dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base-&gt;clks.ref_dtbclk_khz);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -708,7 +784,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 				clk_mgr_base-&gt;clks.dispclk_khz / 1000 / 7);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;config.enable_auto_dpm_test_logs) {</div><div class='del'>-	    dcn32_auto_dpm_test_log(new_clocks, clk_mgr);</div><div class='add'>+	    dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c<br/>index 507a7cf56711..9c660d1facc7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c</a></div><div class='hunk'>@@ -50,6 +50,7 @@</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='ctx'> #include "link.h"</div><div class='ctx'> #include "logger_types.h"</div><div class='add'>+</div><div class='ctx'> #undef DC_LOGGER</div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx-&gt;logger</div><div class='hunk'>@@ -80,12 +81,12 @@</div><div class='ctx'> </div><div class='ctx'> static int dcn35_get_active_display_cnt_wa(</div><div class='ctx'> 		struct dc *dc,</div><div class='del'>-		struct dc_state *context)</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		int *all_active_disps)</div><div class='ctx'> {</div><div class='del'>-	int i, display_count;</div><div class='add'>+	int i, display_count = 0;</div><div class='ctx'> 	bool tmds_present = false;</div><div class='ctx'> </div><div class='del'>-	display_count = 0;</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		const struct dc_stream_state *stream = context-&gt;streams[i];</div><div class='ctx'> </div><div class='hunk'>@@ -103,7 +104,8 @@ static int dcn35_get_active_display_cnt_wa(</div><div class='ctx'> 				link-&gt;link_enc-&gt;funcs-&gt;is_dig_enabled(link-&gt;link_enc))</div><div class='ctx'> 			display_count++;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	if (all_active_disps != NULL)</div><div class='add'>+		*all_active_disps = display_count;</div><div class='ctx'> 	/* WA for hang on HDMI after display off back on*/</div><div class='ctx'> 	if (display_count == 0 &amp;&amp; tmds_present)</div><div class='ctx'> 		display_count = 1;</div><div class='hunk'>@@ -126,21 +128,13 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *</div><div class='ctx'> 			continue;</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal) ||</div><div class='ctx'> 				     !pipe-&gt;stream-&gt;link_enc)) {</div><div class='del'>-			struct stream_encoder *stream_enc = pipe-&gt;stream_res.stream_enc;</div><div class='del'>-</div><div class='ctx'> 			if (disable) {</div><div class='del'>-				if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;disable_fifo)</div><div class='del'>-					pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;disable_fifo(stream_enc);</div><div class='del'>-</div><div class='ctx'> 				if (pipe-&gt;stream_res.tg &amp;&amp; pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc)</div><div class='ctx'> 					pipe-&gt;stream_res.tg-&gt;funcs-&gt;immediate_disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> </div><div class='ctx'> 				reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				pipe-&gt;stream_res.tg-&gt;funcs-&gt;enable_crtc(pipe-&gt;stream_res.tg);</div><div class='del'>-</div><div class='del'>-				if (stream_enc &amp;&amp; stream_enc-&gt;funcs-&gt;enable_fifo)</div><div class='del'>-					pipe-&gt;stream_res.stream_enc-&gt;funcs-&gt;enable_fifo(stream_enc);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -224,14 +218,19 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);</div><div class='ctx'> 	struct dc_clocks *new_clocks = &amp;context-&gt;bw_ctx.bw.dcn.clk;</div><div class='ctx'> 	struct dc *dc = clk_mgr_base-&gt;ctx-&gt;dc;</div><div class='del'>-	int display_count;</div><div class='add'>+	int display_count = 0;</div><div class='ctx'> 	bool update_dppclk = false;</div><div class='ctx'> 	bool update_dispclk = false;</div><div class='ctx'> 	bool dpp_clock_lowered = false;</div><div class='add'>+	int all_active_disps = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;work_arounds.skip_clock_update)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	display_count = dcn35_get_active_display_cnt_wa(dc, context, &amp;all_active_disps);</div><div class='add'>+	if (new_clocks-&gt;dtbclk_en &amp;&amp; !new_clocks-&gt;ref_dtbclk_khz)</div><div class='add'>+		new_clocks-&gt;ref_dtbclk_khz = 600000;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything</div><div class='ctx'> 	 * also if safe to lower is false, we just go in the higher state</div><div class='hunk'>@@ -250,7 +249,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		}</div><div class='ctx'> 		/* check that we're not already in lower */</div><div class='ctx'> 		if (clk_mgr_base-&gt;clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {</div><div class='del'>-			display_count = dcn35_get_active_display_cnt_wa(dc, context);</div><div class='ctx'> 			/* if we can go lower, go lower */</div><div class='ctx'> 			if (display_count == 0)</div><div class='ctx'> 				clk_mgr_base-&gt;clks.pwr_state = DCN_PWR_STATE_LOW_POWER;</div><div class='hunk'>@@ -265,8 +263,10 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> </div><div class='ctx'> 		if (!clk_mgr_base-&gt;clks.dtbclk_en &amp;&amp; new_clocks-&gt;dtbclk_en) {</div><div class='ctx'> 			dcn35_smu_set_dtbclk(clk_mgr, true);</div><div class='del'>-			dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base-&gt;clks.ref_dtbclk_khz);</div><div class='ctx'> 			clk_mgr_base-&gt;clks.dtbclk_en = new_clocks-&gt;dtbclk_en;</div><div class='add'>+</div><div class='add'>+			dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks-&gt;ref_dtbclk_khz);</div><div class='add'>+			clk_mgr_base-&gt;clks.ref_dtbclk_khz = new_clocks-&gt;ref_dtbclk_khz;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* check that we're not already in D0 */</div><div class='hunk'>@@ -314,17 +314,12 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 		update_dispclk = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!new_clocks-&gt;dtbclk_en) {</div><div class='del'>-		new_clocks-&gt;ref_dtbclk_khz = 600000;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */</div><div class='ctx'> 	if (!dc-&gt;debug.disable_dtb_ref_clk_switch &amp;&amp;</div><div class='del'>-			should_set_clock(safe_to_lower, new_clocks-&gt;ref_dtbclk_khz / 1000, clk_mgr_base-&gt;clks.ref_dtbclk_khz / 1000)) {</div><div class='del'>-		/* DCCG requires KHz precision for DTBCLK */</div><div class='del'>-		dcn35_smu_set_dtbclk(clk_mgr, true);</div><div class='del'>-</div><div class='del'>-		dcn35_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base-&gt;clks.ref_dtbclk_khz);</div><div class='add'>+	    should_set_clock(safe_to_lower, new_clocks-&gt;ref_dtbclk_khz / 1000,</div><div class='add'>+			     clk_mgr_base-&gt;clks.ref_dtbclk_khz / 1000)) {</div><div class='add'>+		dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks-&gt;ref_dtbclk_khz);</div><div class='add'>+		clk_mgr_base-&gt;clks.ref_dtbclk_khz = new_clocks-&gt;ref_dtbclk_khz;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dpp_clock_lowered) {</div><div class='hunk'>@@ -348,7 +343,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,</div><div class='ctx'> 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base-&gt;clks.dispclk_khz;</div><div class='ctx'> 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base-&gt;clks.dppclk_khz;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)</div><div class='hunk'>@@ -423,9 +418,8 @@ bool dcn35_are_clock_states_equal(struct dc_clocks *a,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,</div><div class='del'>-		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)</div><div class='add'>+		struct clk_mgr_dcn35 *clk_mgr)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct clk_bw_params dcn35_bw_params = {</div><div class='hunk'>@@ -443,32 +437,32 @@ static struct wm_table ddr5_wm_table = {</div><div class='ctx'> 			.wm_inst = WM_A,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.72,</div><div class='del'>-			.sr_exit_time_us = 9,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 11,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_B,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.72,</div><div class='del'>-			.sr_exit_time_us = 9,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 11,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_C,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.72,</div><div class='del'>-			.sr_exit_time_us = 9,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 11,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_D,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.72,</div><div class='del'>-			.sr_exit_time_us = 9,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 11,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 	}</div><div class='hunk'>@@ -480,32 +474,32 @@ static struct wm_table lpddr5_wm_table = {</div><div class='ctx'> 			.wm_inst = WM_A,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.65333,</div><div class='del'>-			.sr_exit_time_us = 11.5,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 14.5,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_B,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.65333,</div><div class='del'>-			.sr_exit_time_us = 11.5,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 14.5,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_C,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.65333,</div><div class='del'>-			.sr_exit_time_us = 11.5,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 14.5,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.wm_inst = WM_D,</div><div class='ctx'> 			.wm_type = WM_TYPE_PSTATE_CHG,</div><div class='ctx'> 			.pstate_latency_us = 11.65333,</div><div class='del'>-			.sr_exit_time_us = 11.5,</div><div class='del'>-			.sr_enter_plus_exit_time_us = 14.5,</div><div class='add'>+			.sr_exit_time_us = 14.0,</div><div class='add'>+			.sr_enter_plus_exit_time_us = 16.0,</div><div class='ctx'> 			.valid = true,</div><div class='ctx'> 		},</div><div class='ctx'> 	}</div><div class='hunk'>@@ -515,11 +509,6 @@ static DpmClocks_t_dcn35 dummy_clocks;</div><div class='ctx'> </div><div class='ctx'> static struct dcn35_watermarks dummy_wms = { 0 };</div><div class='ctx'> </div><div class='del'>-static struct dcn35_ss_info_table ss_info_table = {</div><div class='del'>-	.ss_divider = 1000,</div><div class='del'>-	.ss_percentage = {0, 0, 375, 375, 375}</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)</div><div class='ctx'> {</div><div class='ctx'> 	int i, num_valid_sets;</div><div class='hunk'>@@ -653,27 +642,47 @@ static unsigned int convert_wck_ratio(uint8_t wck_ratio)</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)</div><div class='add'>+{</div><div class='add'>+	return entry-&gt;UClk * convert_wck_ratio(entry-&gt;WckRatio) * 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,</div><div class='ctx'> 						    struct integrated_info *bios_info,</div><div class='ctx'> 						    DpmClocks_t_dcn35 *clock_table)</div><div class='ctx'> {</div><div class='ctx'> 	struct clk_bw_params *bw_params = clk_mgr-&gt;base.bw_params;</div><div class='ctx'> 	struct clk_limit_table_entry def_max = bw_params-&gt;clk_table.entries[bw_params-&gt;clk_table.num_entries - 1];</div><div class='del'>-	uint32_t max_pstate = 0,  max_uclk = 0, max_fclk = 0;</div><div class='del'>-	uint32_t min_pstate = 0, max_dispclk = 0, max_dppclk = 0;</div><div class='add'>+	uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;</div><div class='add'>+	uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/* Determine min/max p-state values. */</div><div class='ctx'> 	for (i = 0; i &lt; clock_table-&gt;NumMemPstatesEnabled; i++) {</div><div class='del'>-		if (is_valid_clock_value(clock_table-&gt;MemPstateTable[i].UClk) &amp;&amp;</div><div class='del'>-		    clock_table-&gt;MemPstateTable[i].UClk &gt; max_uclk) {</div><div class='del'>-			max_uclk = clock_table-&gt;MemPstateTable[i].UClk;</div><div class='add'>+		uint32_t dram_speed_mts = calc_dram_speed_mts(&amp;clock_table-&gt;MemPstateTable[i]);</div><div class='add'>+</div><div class='add'>+		if (is_valid_clock_value(dram_speed_mts) &amp;&amp; dram_speed_mts &gt; max_dram_speed_mts) {</div><div class='add'>+			max_dram_speed_mts = dram_speed_mts;</div><div class='ctx'> 			max_pstate = i;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* We expect the table to contain at least one valid Uclk entry. */</div><div class='del'>-	ASSERT(is_valid_clock_value(max_uclk));</div><div class='add'>+	min_dram_speed_mts = max_dram_speed_mts;</div><div class='add'>+	min_pstate = max_pstate;</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; clock_table-&gt;NumMemPstatesEnabled; i++) {</div><div class='add'>+		uint32_t dram_speed_mts = calc_dram_speed_mts(&amp;clock_table-&gt;MemPstateTable[i]);</div><div class='add'>+</div><div class='add'>+		if (is_valid_clock_value(dram_speed_mts) &amp;&amp; dram_speed_mts &lt; min_dram_speed_mts) {</div><div class='add'>+			min_dram_speed_mts = dram_speed_mts;</div><div class='add'>+			min_pstate = i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* We expect the table to contain at least one valid P-state entry. */</div><div class='add'>+	ASSERT(clock_table-&gt;NumMemPstatesEnabled &amp;&amp;</div><div class='add'>+	       is_valid_clock_value(max_dram_speed_mts) &amp;&amp;</div><div class='add'>+	       is_valid_clock_value(min_dram_speed_mts));</div><div class='ctx'> </div><div class='ctx'> 	/* dispclk and dppclk can be max at any voltage, same number of levels for both */</div><div class='ctx'> 	if (clock_table-&gt;NumDispClkLevelsEnabled &lt;= NUM_DISPCLK_DPM_LEVELS &amp;&amp;</div><div class='hunk'>@@ -683,47 +692,46 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk</div><div class='ctx'> 		max_dppclk = find_max_clk_value(clock_table-&gt;DppClocks,</div><div class='ctx'> 			clock_table-&gt;NumDispClkLevelsEnabled);</div><div class='ctx'> 	} else {</div><div class='add'>+		/* Invalid number of entries in the table from PMFW. */</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> 	}</div><div class='del'>-	if (clock_table-&gt;NumFclkLevelsEnabled &lt;= NUM_FCLK_DPM_LEVELS)</div><div class='del'>-		max_fclk = find_max_clk_value(clock_table-&gt;FclkClocks_Freq,</div><div class='del'>-			clock_table-&gt;NumFclkLevelsEnabled);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; clock_table-&gt;NumMemPstatesEnabled; i++) {</div><div class='del'>-		uint32_t min_uclk = clock_table-&gt;MemPstateTable[0].UClk;</div><div class='del'>-		int j;</div><div class='add'>+	/* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */</div><div class='add'>+	ASSERT(clock_table-&gt;NumDcfClkLevelsEnabled &gt; 0);</div><div class='ctx'> </div><div class='del'>-		for (j = 1; j &lt; clock_table-&gt;NumMemPstatesEnabled; j++) {</div><div class='del'>-			if (is_valid_clock_value(clock_table-&gt;MemPstateTable[j].UClk) &amp;&amp;</div><div class='del'>-			    clock_table-&gt;MemPstateTable[j].UClk &lt; min_uclk &amp;&amp;</div><div class='del'>-			    clock_table-&gt;MemPstateTable[j].Voltage &lt;= clock_table-&gt;SocVoltage[i]) {</div><div class='del'>-				min_uclk = clock_table-&gt;MemPstateTable[j].UClk;</div><div class='del'>-				min_pstate = j;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+	max_fclk = find_max_clk_value(clock_table-&gt;FclkClocks_Freq, clock_table-&gt;NumFclkLevelsEnabled);</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; clock_table-&gt;NumDcfClkLevelsEnabled; i++) {</div><div class='add'>+		int j;</div><div class='add'>+</div><div class='add'>+		/* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */</div><div class='ctx'> 		for (j = bw_params-&gt;clk_table.num_entries - 1; j &gt; 0; j--)</div><div class='ctx'> 			if (bw_params-&gt;clk_table.entries[j].dcfclk_mhz &lt;= clock_table-&gt;DcfClocks[i])</div><div class='del'>-			break;</div><div class='add'>+				break;</div><div class='ctx'> </div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].phyclk_mhz = bw_params-&gt;clk_table.entries[j].phyclk_mhz;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].phyclk_d18_mhz = bw_params-&gt;clk_table.entries[j].phyclk_d18_mhz;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].dtbclk_mhz = bw_params-&gt;clk_table.entries[j].dtbclk_mhz;</div><div class='del'>-		bw_params-&gt;clk_table.entries[i].fclk_mhz = max_fclk;</div><div class='add'>+</div><div class='add'>+		/* Now update clocks we do read */</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].memclk_mhz = clock_table-&gt;MemPstateTable[min_pstate].MemClk;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].voltage = clock_table-&gt;MemPstateTable[min_pstate].Voltage;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].dcfclk_mhz = clock_table-&gt;DcfClocks[i];</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].socclk_mhz = clock_table-&gt;SocClocks[i];</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].dispclk_mhz = max_dispclk;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].dppclk_mhz = max_dppclk;</div><div class='del'>-		bw_params-&gt;clk_table.entries[i].wck_ratio = convert_wck_ratio(</div><div class='del'>-			clock_table-&gt;MemPstateTable[min_pstate].WckRatio);</div><div class='del'>-		}</div><div class='add'>+		bw_params-&gt;clk_table.entries[i].wck_ratio =</div><div class='add'>+			convert_wck_ratio(clock_table-&gt;MemPstateTable[min_pstate].WckRatio);</div><div class='add'>+</div><div class='add'>+		/* Dcfclk and Fclk are tied, but at a different ratio */</div><div class='add'>+		bw_params-&gt;clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table-&gt;DcfClocks[i]);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Make sure to include at least one entry at highest pstate */</div><div class='ctx'> 	if (max_pstate != min_pstate || i == 0) {</div><div class='ctx'> 		if (i &gt; MAX_NUM_DPM_LVL - 1)</div><div class='ctx'> 			i = MAX_NUM_DPM_LVL - 1;</div><div class='add'>+</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].fclk_mhz = max_fclk;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].memclk_mhz = clock_table-&gt;MemPstateTable[max_pstate].MemClk;</div><div class='ctx'> 		bw_params-&gt;clk_table.entries[i].voltage = clock_table-&gt;MemPstateTable[max_pstate].Voltage;</div><div class='hunk'>@@ -739,6 +747,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk</div><div class='ctx'> 	}</div><div class='ctx'> 	bw_params-&gt;clk_table.num_entries = i--;</div><div class='ctx'> </div><div class='add'>+	/* Make sure all highest clocks are included*/</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].socclk_mhz =</div><div class='ctx'> 		find_max_clk_value(clock_table-&gt;SocClocks, NUM_SOCCLK_DPM_LEVELS);</div><div class='ctx'> 	bw_params-&gt;clk_table.entries[i].dispclk_mhz =</div><div class='hunk'>@@ -757,6 +766,11 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk</div><div class='ctx'> 	bw_params-&gt;clk_table.num_entries_per_clk.num_fclk_levels = clock_table-&gt;NumFclkLevelsEnabled;</div><div class='ctx'> 	bw_params-&gt;clk_table.num_entries_per_clk.num_memclk_levels = clock_table-&gt;NumMemPstatesEnabled;</div><div class='ctx'> 	bw_params-&gt;clk_table.num_entries_per_clk.num_socclk_levels = clock_table-&gt;NumSocClkLevelsEnabled;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set any 0 clocks to max default setting. Not an issue for</div><div class='add'>+	 * power since we aren't doing switching in such case anyway</div><div class='add'>+	 */</div><div class='ctx'> 	for (i = 0; i &lt; bw_params-&gt;clk_table.num_entries; i++) {</div><div class='ctx'> 		if (!bw_params-&gt;clk_table.entries[i].fclk_mhz) {</div><div class='ctx'> 			bw_params-&gt;clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;</div><div class='hunk'>@@ -805,7 +819,7 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)</div><div class='ctx'> 	struct dc_state *context = dc-&gt;current_state;</div><div class='ctx'> </div><div class='ctx'> 	if (clk_mgr_base-&gt;clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {</div><div class='del'>-		display_count = dcn35_get_active_display_cnt_wa(dc, context);</div><div class='add'>+		display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);</div><div class='ctx'> 		/* if we can go lower, go lower */</div><div class='ctx'> 		if (display_count == 0)</div><div class='ctx'> 			clk_mgr_base-&gt;clks.pwr_state = DCN_PWR_STATE_LOW_POWER;</div><div class='hunk'>@@ -965,21 +979,6 @@ struct clk_mgr_funcs dcn35_fpga_funcs = {</div><div class='ctx'> 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)</div><div class='del'>-{</div><div class='del'>-	uint32_t clock_source;</div><div class='del'>-	struct dc_context *ctx = clk_mgr-&gt;base.ctx;</div><div class='del'>-</div><div class='del'>-	REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &amp;clock_source);</div><div class='del'>-</div><div class='del'>-	clk_mgr-&gt;dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];</div><div class='del'>-</div><div class='del'>-	if (clk_mgr-&gt;dprefclk_ss_percentage != 0) {</div><div class='del'>-		clk_mgr-&gt;ss_on_dprefclk = true;</div><div class='del'>-		clk_mgr-&gt;dprefclk_ss_divider = ss_info_table.ss_divider;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dcn35_clk_mgr_construct(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='ctx'> 		struct clk_mgr_dcn35 *clk_mgr,</div><div class='hunk'>@@ -987,7 +986,6 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 		struct dccg *dccg)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };</div><div class='del'>-	struct clk_log_info log_info = {0};</div><div class='ctx'> 	clk_mgr-&gt;base.base.ctx = ctx;</div><div class='ctx'> 	clk_mgr-&gt;base.base.funcs = &amp;dcn35_funcs;</div><div class='ctx'> </div><div class='hunk'>@@ -1040,20 +1038,14 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 		dcn35_bw_params.wm_table = ddr5_wm_table;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Saved clocks configured at boot for debug purposes */</div><div class='del'>-	dcn35_dump_clk_registers(&amp;clk_mgr-&gt;base.base.boot_snapshot, &amp;clk_mgr-&gt;base.base, &amp;log_info);</div><div class='add'>+	dcn35_dump_clk_registers(&amp;clk_mgr-&gt;base.base.boot_snapshot, clk_mgr);</div><div class='ctx'> </div><div class='ctx'> 	clk_mgr-&gt;base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&amp;clk_mgr-&gt;base);</div><div class='del'>-	clk_mgr-&gt;base.base.clks.ref_dtbclk_khz = dcn35_smu_get_dtbclk(&amp;clk_mgr-&gt;base);</div><div class='del'>-</div><div class='del'>-	if (!clk_mgr-&gt;base.base.clks.ref_dtbclk_khz)</div><div class='del'>-		dcn35_smu_set_dtbclk(&amp;clk_mgr-&gt;base, true);</div><div class='add'>+	clk_mgr-&gt;base.base.clks.ref_dtbclk_khz = 600000;</div><div class='ctx'> </div><div class='del'>-	clk_mgr-&gt;base.base.clks.dtbclk_en = true;</div><div class='ctx'> 	dce_clock_read_ss_info(&amp;clk_mgr-&gt;base);</div><div class='ctx'> 	/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/</div><div class='ctx'> </div><div class='del'>-	dcn35_read_ss_info_from_lut(&amp;clk_mgr-&gt;base);</div><div class='del'>-</div><div class='ctx'> 	clk_mgr-&gt;base.base.bw_params = &amp;dcn35_bw_params;</div><div class='ctx'> </div><div class='ctx'> 	if (clk_mgr-&gt;base.base.ctx-&gt;dc-&gt;debug.pstate_enabled) {</div><div class='hunk'>@@ -1129,7 +1121,6 @@ void dcn35_clk_mgr_construct(</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_dpp_power_gate = false;</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_hubp_power_gate = false;</div><div class='ctx'> 			ctx-&gt;dc-&gt;debug.disable_dsc_power_gate = false;</div><div class='del'>-			ctx-&gt;dc-&gt;debug.disable_hpo_power_gate = false;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/*let's reset the config control flag*/</div><div class='ctx'> 			ctx-&gt;dc-&gt;config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c<br/>index b6b8c3ca1572..6d4a1ffab5ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c</a></div><div class='hunk'>@@ -116,6 +116,9 @@ static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un</div><div class='ctx'> 			msleep(delay_us/1000);</div><div class='ctx'> 		else if (delay_us &gt; 0)</div><div class='ctx'> 			udelay(delay_us);</div><div class='add'>+</div><div class='add'>+		if (clk_mgr-&gt;base.ctx-&gt;dc-&gt;debug.disable_timeout)</div><div class='add'>+			max_retries++;</div><div class='ctx'> 	} while (max_retries--);</div><div class='ctx'> </div><div class='ctx'> 	return res_val;</div><div class='hunk'>@@ -276,7 +279,7 @@ void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, u</div><div class='ctx'> 		clk_mgr,</div><div class='ctx'> 		VBIOSSMC_MSG_SetDisplayIdleOptimizations,</div><div class='ctx'> 		idle_info);</div><div class='del'>-	smu_print("VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info  = %d\n", idle_info);</div><div class='add'>+	smu_print("%s: VBIOSSMC_MSG_SetDisplayIdleOptimizations idle_info  = %x\n", __func__, idle_info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)</div><div class='hunk'>@@ -295,7 +298,7 @@ void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool e</div><div class='ctx'> 			clk_mgr,</div><div class='ctx'> 			VBIOSSMC_MSG_SetDisplayIdleOptimizations,</div><div class='ctx'> 			idle_info.data);</div><div class='del'>-	smu_print("dcn35_smu_enable_phy_refclk_pwrdwn  = %d\n", enable ? 1 : 0);</div><div class='add'>+	smu_print("%s smu_enable_phy_refclk_pwrdwn  = %d\n", __func__, enable ? 1 : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)</div><div class='hunk'>@@ -307,6 +310,7 @@ void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> 			clk_mgr,</div><div class='ctx'> 			VBIOSSMC_MSG_UpdatePmeRestore,</div><div class='ctx'> 			0);</div><div class='add'>+	smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)</div><div class='hunk'>@@ -347,7 +351,7 @@ void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> </div><div class='ctx'> void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)</div><div class='ctx'> {</div><div class='del'>-	unsigned int msg_id, param;</div><div class='add'>+	unsigned int msg_id, param, retv;</div><div class='ctx'> </div><div class='ctx'> 	if (!clk_mgr-&gt;smu_present)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -357,27 +361,32 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst</div><div class='ctx'> 	case DCN_ZSTATE_SUPPORT_ALLOW:</div><div class='ctx'> 		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;</div><div class='ctx'> 		param = (1 &lt;&lt; 10) | (1 &lt;&lt; 9) | (1 &lt;&lt; 8);</div><div class='add'>+		smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = %d\n", __func__, param);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case DCN_ZSTATE_SUPPORT_DISALLOW:</div><div class='ctx'> 		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;</div><div class='ctx'> 		param = 0;</div><div class='add'>+		smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = %d\n",  __func__, param);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:</div><div class='ctx'> 		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;</div><div class='ctx'> 		param = (1 &lt;&lt; 10);</div><div class='add'>+		smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = %d\n", __func__, param);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY:</div><div class='ctx'> 		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;</div><div class='ctx'> 		param = (1 &lt;&lt; 10) | (1 &lt;&lt; 8);</div><div class='add'>+		smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = %d\n", __func__, param);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY:</div><div class='ctx'> 		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;</div><div class='ctx'> 		param = (1 &lt;&lt; 8);</div><div class='add'>+		smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = %d\n", __func__, param);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default: //DCN_ZSTATE_SUPPORT_UNKNOWN</div><div class='hunk'>@@ -387,11 +396,11 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-	dcn35_smu_send_msg_with_param(</div><div class='add'>+	retv = dcn35_smu_send_msg_with_param(</div><div class='ctx'> 		clk_mgr,</div><div class='ctx'> 		msg_id,</div><div class='ctx'> 		param);</div><div class='del'>-	smu_print("dcn35_smu_set_zstate_support msg_id = %d, param = %d\n", msg_id, param);</div><div class='add'>+	smu_print("%s:  msg_id = %d, param = 0x%x, return = %d\n", __func__, msg_id, param, retv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)</div><div class='hunk'>@@ -405,7 +414,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> 						 VBIOSSMC_MSG_GetDprefclkFreq,</div><div class='ctx'> 						 0);</div><div class='ctx'> </div><div class='del'>-	smu_print("dcn35_smu_get_DPREF clk  = %d mhz\n", dprefclk);</div><div class='add'>+	smu_print("%s:  SMU DPREF clk  = %d mhz\n",  __func__, dprefclk);</div><div class='ctx'> 	return dprefclk * 1000;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -420,7 +429,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> 					       VBIOSSMC_MSG_GetDtbclkFreq,</div><div class='ctx'> 					       0);</div><div class='ctx'> </div><div class='del'>-	smu_print("dcn35_smu_get_dtbclk  = %d mhz\n", dtbclk);</div><div class='add'>+	smu_print("%s: get_dtbclk  = %dmhz\n", __func__, dtbclk);</div><div class='ctx'> 	return dtbclk * 1000;</div><div class='ctx'> }</div><div class='ctx'> /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */</div><div class='hunk'>@@ -433,7 +442,7 @@ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)</div><div class='ctx'> 			clk_mgr,</div><div class='ctx'> 			VBIOSSMC_MSG_SetDtbClk,</div><div class='ctx'> 			enable);</div><div class='del'>-	smu_print("dcn35_smu_set_dtbclk  = %d \n", enable ? 1 : 0);</div><div class='add'>+	smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)</div><div class='hunk'>@@ -442,30 +451,45 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl</div><div class='ctx'> 			clk_mgr,</div><div class='ctx'> 			VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,</div><div class='ctx'> 			enable);</div><div class='add'>+	smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> {</div><div class='del'>-	return dcn35_smu_send_msg_with_param(</div><div class='add'>+	int retv;</div><div class='add'>+</div><div class='add'>+	retv = dcn35_smu_send_msg_with_param(</div><div class='ctx'> 		clk_mgr,</div><div class='ctx'> 		VBIOSSMC_MSG_DispPsrExit,</div><div class='ctx'> 		0);</div><div class='add'>+	smu_print("%s: smu_exit_low_power_state return = %d\n", __func__, retv);</div><div class='add'>+	return retv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> {</div><div class='del'>-	return dcn35_smu_send_msg_with_param(</div><div class='add'>+	int retv;</div><div class='add'>+</div><div class='add'>+	retv = dcn35_smu_send_msg_with_param(</div><div class='ctx'> 			clk_mgr,</div><div class='ctx'> 			VBIOSSMC_MSG_QueryIPS2Support,</div><div class='ctx'> 			0);</div><div class='add'>+</div><div class='add'>+	//smu_print("%s: VBIOSSMC_MSG_QueryIPS2Support return = %x\n", __func__, retv);</div><div class='add'>+	return retv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)</div><div class='ctx'> {</div><div class='ctx'> 	REG_WRITE(MP1_SMN_C2PMSG_71, param);</div><div class='add'>+	//smu_print("%s: write_ips_scratch = %x\n", __func__, param);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)</div><div class='ctx'> {</div><div class='del'>-	return REG_READ(MP1_SMN_C2PMSG_71);</div><div class='add'>+	uint32_t retv;</div><div class='add'>+</div><div class='add'>+	retv = REG_READ(MP1_SMN_C2PMSG_71);</div><div class='add'>+	//smu_print("%s: dcn35_smu_read_ips_scratch = %x\n",  __func__, retv);</div><div class='add'>+	return retv;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c<br/>index 76b47f178127..aa7c02ba948e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc.c</a></div><div class='hunk'>@@ -34,6 +34,8 @@</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='add'>+#include "dc_state.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #include "gpio_service_interface.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='hunk'>@@ -519,7 +521,7 @@ dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,</div><div class='ctx'> 		cmd.secure_display.roi_info.y_end = rect-&gt;y + rect-&gt;height;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void</div><div class='hunk'>@@ -808,7 +810,7 @@ static void dc_destruct(struct dc *dc)</div><div class='ctx'> 		link_enc_cfg_init(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;current_state) {</div><div class='del'>-		dc_release_state(dc-&gt;current_state);</div><div class='add'>+		dc_state_release(dc-&gt;current_state);</div><div class='ctx'> 		dc-&gt;current_state = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1020,29 +1022,27 @@ static bool dc_construct(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+	if (!create_links(dc, init_params-&gt;num_virtual_links))</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	/* Create additional DIG link encoder objects if fewer than the platform</div><div class='add'>+	 * supports were created during link construction.</div><div class='add'>+	 */</div><div class='add'>+	if (!create_link_encoders(dc))</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='ctx'> 	/* Creation of current_state must occur after dc-&gt;dml</div><div class='ctx'> 	 * is initialized in dc_create_resource_pool because</div><div class='ctx'> 	 * on creation it copies the contents of dc-&gt;dml</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	dc-&gt;current_state = dc_create_state(dc);</div><div class='add'>+	dc-&gt;current_state = dc_state_create(dc);</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;current_state) {</div><div class='ctx'> 		dm_error("%s: failed to create validate ctx\n", __func__);</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!create_links(dc, init_params-&gt;num_virtual_links))</div><div class='del'>-		goto fail;</div><div class='del'>-</div><div class='del'>-	/* Create additional DIG link encoder objects if fewer than the platform</div><div class='del'>-	 * supports were created during link construction.</div><div class='del'>-	 */</div><div class='del'>-	if (!create_link_encoders(dc))</div><div class='del'>-		goto fail;</div><div class='del'>-</div><div class='del'>-	dc_resource_state_construct(dc, dc-&gt;current_state);</div><div class='del'>-</div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='hunk'>@@ -1085,7 +1085,7 @@ static void apply_ctx_interdependent_lock(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)</div><div class='add'>+static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dce_version &gt;= DCN_VERSION_1_0) {</div><div class='ctx'> 		memset(&amp;pipe_ctx-&gt;visual_confirm_color, 0, sizeof(struct tg_color));</div><div class='hunk'>@@ -1105,9 +1105,9 @@ static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *conte</div><div class='ctx'> 			if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)</div><div class='ctx'> 				get_mpctree_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 			else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_SUBVP)</div><div class='del'>-				get_subvp_visual_confirm_color(dc, context, pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+				get_subvp_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 			else if (dc-&gt;debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)</div><div class='del'>-				get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='add'>+				get_mclk_switch_visual_confirm_color(pipe_ctx, &amp;(pipe_ctx-&gt;visual_confirm_color));</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1115,7 +1115,7 @@ static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *conte</div><div class='ctx'> static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j;</div><div class='del'>-	struct dc_state *dangling_context = dc_create_state(dc);</div><div class='add'>+	struct dc_state *dangling_context = dc_state_create_current_copy(dc);</div><div class='ctx'> 	struct dc_state *current_ctx;</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='ctx'> 	struct timing_generator *tg;</div><div class='hunk'>@@ -1123,8 +1123,6 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	if (dangling_context == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dc_resource_state_copy_construct(dc-&gt;current_state, dangling_context);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct dc_stream_state *old_stream =</div><div class='ctx'> 				dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream;</div><div class='hunk'>@@ -1161,6 +1159,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (should_disable &amp;&amp; old_stream) {</div><div class='add'>+			bool is_phantom = dc_state_get_stream_subvp_type(dc-&gt;current_state, old_stream) == SUBVP_PHANTOM;</div><div class='ctx'> 			pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 			tg = pipe-&gt;stream_res.tg;</div><div class='ctx'> 			/* When disabling plane for a phantom pipe, we must turn on the</div><div class='hunk'>@@ -1169,22 +1168,29 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			 * state that can result in underflow or hang when enabling it</div><div class='ctx'> 			 * again for different use.</div><div class='ctx'> 			 */</div><div class='del'>-			if (old_stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+			if (is_phantom) {</div><div class='ctx'> 				if (tg-&gt;funcs-&gt;enable_crtc) {</div><div class='ctx'> 					int main_pipe_width, main_pipe_height;</div><div class='add'>+					struct dc_stream_state *old_paired_stream = dc_state_get_paired_subvp_stream(dc-&gt;current_state, old_stream);</div><div class='ctx'> </div><div class='del'>-					main_pipe_width = old_stream-&gt;mall_stream_config.paired_stream-&gt;dst.width;</div><div class='del'>-					main_pipe_height = old_stream-&gt;mall_stream_config.paired_stream-&gt;dst.height;</div><div class='add'>+					main_pipe_width = old_paired_stream-&gt;dst.width;</div><div class='add'>+					main_pipe_height = old_paired_stream-&gt;dst.height;</div><div class='ctx'> 					if (dc-&gt;hwss.blank_phantom)</div><div class='ctx'> 						dc-&gt;hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);</div><div class='ctx'> 					tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='del'>-			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);</div><div class='add'>+</div><div class='add'>+			if (is_phantom)</div><div class='add'>+				dc_state_rem_all_phantom_planes_for_stream(dc, old_stream, dangling_context, true);</div><div class='add'>+			else</div><div class='add'>+				dc_state_rem_all_planes_for_stream(dc, old_stream, dangling_context);</div><div class='ctx'> 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);</div><div class='ctx'> </div><div class='del'>-			if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state)</div><div class='del'>-				dc_update_viusal_confirm_color(dc, context, pipe);</div><div class='add'>+			if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='add'>+				set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			if (dc-&gt;hwss.apply_ctx_for_surface) {</div><div class='ctx'> 				apply_ctx_interdependent_lock(dc, dc-&gt;current_state, old_stream, true);</div><div class='hunk'>@@ -1203,7 +1209,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			 * The OTG is set to disable on falling edge of VUPDATE so the plane disable</div><div class='ctx'> 			 * will still get it's double buffer update.</div><div class='ctx'> 			 */</div><div class='del'>-			if (old_stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+			if (is_phantom) {</div><div class='ctx'> 				if (tg-&gt;funcs-&gt;disable_phantom_crtc)</div><div class='ctx'> 					tg-&gt;funcs-&gt;disable_phantom_crtc(tg);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1212,7 +1218,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)</div><div class='ctx'> </div><div class='ctx'> 	current_ctx = dc-&gt;current_state;</div><div class='ctx'> 	dc-&gt;current_state = dangling_context;</div><div class='del'>-	dc_release_state(current_ctx);</div><div class='add'>+	dc_state_release(current_ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void disable_vbios_mode_if_required(</div><div class='hunk'>@@ -1284,7 +1290,7 @@ static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		int count = 0;</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (!pipe-&gt;plane_state || pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (!pipe-&gt;plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* Timeout 100 ms */</div><div class='hunk'>@@ -1510,7 +1516,7 @@ static void program_timing_sync(</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for (k = 0; k &lt; group_size; k++) {</div><div class='del'>-			struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]-&gt;stream);</div><div class='add'>+			struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 			status-&gt;timing_sync_info.group_id = num_group;</div><div class='ctx'> 			status-&gt;timing_sync_info.group_size = group_size;</div><div class='hunk'>@@ -1521,7 +1527,7 @@ static void program_timing_sync(</div><div class='ctx'> </div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		/* remove any other pipes that are already been synced */</div><div class='add'>+		/* remove any other unblanked pipes as they have already been synced */</div><div class='ctx'> 		if (dc-&gt;config.use_pipe_ctx_sync_logic) {</div><div class='ctx'> 			/* check pipe's syncd to decide which pipe to be removed */</div><div class='ctx'> 			for (j = 1; j &lt; group_size; j++) {</div><div class='hunk'>@@ -1534,6 +1540,7 @@ static void program_timing_sync(</div><div class='ctx'> 					pipe_set[j]-&gt;pipe_idx_syncd = pipe_set[0]-&gt;pipe_idx_syncd;</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='add'>+			/* remove any other pipes by checking valid plane */</div><div class='ctx'> 			for (j = j + 1; j &lt; group_size; j++) {</div><div class='ctx'> 				bool is_blanked;</div><div class='ctx'> </div><div class='hunk'>@@ -1554,7 +1561,7 @@ static void program_timing_sync(</div><div class='ctx'> 		if (group_size &gt; 1) {</div><div class='ctx'> 			if (sync_type == TIMING_SYNCHRONIZABLE) {</div><div class='ctx'> 				dc-&gt;hwss.enable_timing_synchronization(</div><div class='del'>-					dc, group_index, group_size, pipe_set);</div><div class='add'>+					dc, ctx, group_index, group_size, pipe_set);</div><div class='ctx'> 			} else</div><div class='ctx'> 				if (sync_type == VBLANK_SYNCHRONIZABLE) {</div><div class='ctx'> 				dc-&gt;hwss.enable_vblanks_synchronization(</div><div class='hunk'>@@ -1836,7 +1843,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		/* Check old context for SubVP */</div><div class='del'>-		subvp_prev_use |= (old_pipe-&gt;stream &amp;&amp; old_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM);</div><div class='add'>+		subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc-&gt;current_state, old_pipe) == SUBVP_PHANTOM);</div><div class='ctx'> 		if (subvp_prev_use)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1964,6 +1971,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 		wait_for_no_pipes_pending(dc, context);</div><div class='ctx'> 		/* pplib is notified if disp_num changed */</div><div class='ctx'> 		dc-&gt;hwss.optimize_bandwidth(dc, context);</div><div class='add'>+		/* Need to do otg sync again as otg could be out of sync due to otg</div><div class='add'>+		 * workaround applied during clock update</div><div class='add'>+		 */</div><div class='add'>+		dc_trigger_sync(dc, context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.update_dsc_pg)</div><div class='hunk'>@@ -1990,9 +2001,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c</div><div class='ctx'> 	old_state = dc-&gt;current_state;</div><div class='ctx'> 	dc-&gt;current_state = context;</div><div class='ctx'> </div><div class='del'>-	dc_release_state(old_state);</div><div class='add'>+	dc_state_release(old_state);</div><div class='ctx'> </div><div class='del'>-	dc_retain_state(dc-&gt;current_state);</div><div class='add'>+	dc_state_retain(dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='hunk'>@@ -2063,12 +2074,10 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 	if (handle_exit_odm2to1)</div><div class='ctx'> 		res = commit_minimal_transition_state(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='del'>-	context = dc_create_state(dc);</div><div class='add'>+	context = dc_state_create_current_copy(dc);</div><div class='ctx'> 	if (!context)</div><div class='ctx'> 		goto context_alloc_fail;</div><div class='ctx'> </div><div class='del'>-	dc_resource_state_copy_construct_current(dc, context);</div><div class='del'>-</div><div class='ctx'> 	res = dc_validate_with_context(dc, set, stream_count, context, false);</div><div class='ctx'> 	if (res != DC_OK) {</div><div class='ctx'> 		BREAK_TO_DEBUGGER();</div><div class='hunk'>@@ -2083,7 +2092,7 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 				streams[i]-&gt;out.otg_offset = context-&gt;stream_status[j].primary_otg_inst;</div><div class='ctx'> </div><div class='ctx'> 			if (dc_is_embedded_signal(streams[i]-&gt;signal)) {</div><div class='del'>-				struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]);</div><div class='add'>+				struct dc_stream_status *status = dc_state_get_stream_status(context, streams[i]);</div><div class='ctx'> </div><div class='ctx'> 				if (dc-&gt;hwss.is_abm_supported)</div><div class='ctx'> 					status-&gt;is_abm_supported = dc-&gt;hwss.is_abm_supported(dc, context, streams[i]);</div><div class='hunk'>@@ -2094,7 +2103,7 @@ enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	dc_release_state(context);</div><div class='add'>+	dc_state_release(context);</div><div class='ctx'> </div><div class='ctx'> context_alloc_fail:</div><div class='ctx'> </div><div class='hunk'>@@ -2148,7 +2157,7 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		// Don't check flip pending on phantom pipes</div><div class='del'>-		if (!pipe-&gt;plane_state || (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM))</div><div class='add'>+		if (!pipe-&gt;plane_state || (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* Must set to false to start with, due to OR in update function */</div><div class='hunk'>@@ -2206,7 +2215,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)</div><div class='ctx'> 			if (context-&gt;res_ctx.pipe_ctx[i].stream == NULL ||</div><div class='ctx'> 					context-&gt;res_ctx.pipe_ctx[i].plane_state == NULL) {</div><div class='ctx'> 				context-&gt;res_ctx.pipe_ctx[i].pipe_idx = i;</div><div class='del'>-				dc-&gt;hwss.disable_plane(dc, &amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+				dc-&gt;hwss.disable_plane(dc, context, &amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 		process_deferred_updates(dc);</div><div class='hunk'>@@ -2221,110 +2230,6 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)</div><div class='ctx'> 	dc-&gt;wm_optimized_required = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void init_state(struct dc *dc, struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	/* Each context must have their own instance of VBA and in order to</div><div class='del'>-	 * initialize and obtain IP and SOC the base DML instance from DC is</div><div class='del'>-	 * initially copied into every context</div><div class='del'>-	 */</div><div class='del'>-	memcpy(&amp;context-&gt;bw_ctx.dml, &amp;dc-&gt;dml, sizeof(struct display_mode_lib));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct dc_state *dc_create_state(struct dc *dc)</div><div class='del'>-{</div><div class='del'>-	struct dc_state *context = kvzalloc(sizeof(struct dc_state),</div><div class='del'>-					    GFP_KERNEL);</div><div class='del'>-</div><div class='del'>-	if (!context)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	init_state(dc, context);</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	if (dc-&gt;debug.using_dml2) {</div><div class='del'>-		dml2_create(dc, &amp;dc-&gt;dml2_options, &amp;context-&gt;bw_ctx.dml2);</div><div class='del'>-	}</div><div class='del'>-#endif</div><div class='del'>-	kref_init(&amp;context-&gt;refcount);</div><div class='del'>-</div><div class='del'>-	return context;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct dc_state *dc_copy_state(struct dc_state *src_ctx)</div><div class='del'>-{</div><div class='del'>-	int i, j;</div><div class='del'>-	struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	struct dml2_context *dml2 =  NULL;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	if (!new_ctx)</div><div class='del'>-		return NULL;</div><div class='del'>-	memcpy(new_ctx, src_ctx, sizeof(struct dc_state));</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	if (new_ctx-&gt;bw_ctx.dml2) {</div><div class='del'>-		dml2 = kzalloc(sizeof(struct dml2_context), GFP_KERNEL);</div><div class='del'>-		if (!dml2)</div><div class='del'>-			return NULL;</div><div class='del'>-</div><div class='del'>-		memcpy(dml2, src_ctx-&gt;bw_ctx.dml2, sizeof(struct dml2_context));</div><div class='del'>-		new_ctx-&gt;bw_ctx.dml2 = dml2;</div><div class='del'>-	}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-			struct pipe_ctx *cur_pipe = &amp;new_ctx-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-			if (cur_pipe-&gt;top_pipe)</div><div class='del'>-				cur_pipe-&gt;top_pipe =  &amp;new_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;top_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-			if (cur_pipe-&gt;bottom_pipe)</div><div class='del'>-				cur_pipe-&gt;bottom_pipe = &amp;new_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;bottom_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-			if (cur_pipe-&gt;prev_odm_pipe)</div><div class='del'>-				cur_pipe-&gt;prev_odm_pipe =  &amp;new_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;prev_odm_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-			if (cur_pipe-&gt;next_odm_pipe)</div><div class='del'>-				cur_pipe-&gt;next_odm_pipe = &amp;new_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;next_odm_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; new_ctx-&gt;stream_count; i++) {</div><div class='del'>-			dc_stream_retain(new_ctx-&gt;streams[i]);</div><div class='del'>-			for (j = 0; j &lt; new_ctx-&gt;stream_status[i].plane_count; j++)</div><div class='del'>-				dc_plane_state_retain(</div><div class='del'>-					new_ctx-&gt;stream_status[i].plane_states[j]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kref_init(&amp;new_ctx-&gt;refcount);</div><div class='del'>-</div><div class='del'>-	return new_ctx;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dc_retain_state(struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	kref_get(&amp;context-&gt;refcount);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dc_state_free(struct kref *kref)</div><div class='del'>-{</div><div class='del'>-	struct dc_state *context = container_of(kref, struct dc_state, refcount);</div><div class='del'>-	dc_resource_state_destruct(context);</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	dml2_destroy(context-&gt;bw_ctx.dml2);</div><div class='del'>-	context-&gt;bw_ctx.dml2 = 0;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	kvfree(context);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dc_release_state(struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	kref_put(&amp;context-&gt;refcount, dc_state_free);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool dc_set_generic_gpio_for_stereo(bool enable,</div><div class='ctx'> 		struct gpio_service *gpio_service)</div><div class='ctx'> {</div><div class='hunk'>@@ -2997,11 +2902,9 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 				       update-&gt;dsc_config-&gt;num_slices_v != 0);</div><div class='ctx'> </div><div class='ctx'> 		/* Use temporarry context for validating new DSC config */</div><div class='del'>-		struct dc_state *dsc_validate_context = dc_create_state(dc);</div><div class='add'>+		struct dc_state *dsc_validate_context = dc_state_create_copy(dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 		if (dsc_validate_context) {</div><div class='del'>-			dc_resource_state_copy_construct(dc-&gt;current_state, dsc_validate_context);</div><div class='del'>-</div><div class='ctx'> 			stream-&gt;timing.dsc_cfg = *update-&gt;dsc_config;</div><div class='ctx'> 			stream-&gt;timing.flags.DSC = enable_dsc;</div><div class='ctx'> 			if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, dsc_validate_context, true)) {</div><div class='hunk'>@@ -3010,7 +2913,7 @@ static void copy_stream_update_to_stream(struct dc *dc,</div><div class='ctx'> 				update-&gt;dsc_config = NULL;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			dc_release_state(dsc_validate_context);</div><div class='add'>+			dc_state_release(dsc_validate_context);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			DC_ERROR("Failed to allocate new validate context for DSC change\n");</div><div class='ctx'> 			update-&gt;dsc_config = NULL;</div><div class='hunk'>@@ -3109,30 +3012,27 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 			new_planes[i] = srf_updates[i].surface;</div><div class='ctx'> </div><div class='ctx'> 		/* initialize scratch memory for building context */</div><div class='del'>-		context = dc_create_state(dc);</div><div class='add'>+		context = dc_state_create_copy(dc-&gt;current_state);</div><div class='ctx'> 		if (context == NULL) {</div><div class='ctx'> 			DC_ERROR("Failed to allocate new validate context!\n");</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		dc_resource_state_copy_construct(</div><div class='del'>-				dc-&gt;current_state, context);</div><div class='del'>-</div><div class='ctx'> 		/* For each full update, remove all existing phantom pipes first.</div><div class='ctx'> 		 * Ensures that we have enough pipes for newly added MPO planes</div><div class='ctx'> 		 */</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;remove_phantom_pipes)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;remove_phantom_pipes(dc, context, false);</div><div class='add'>+		dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='add'>+		dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='ctx'> </div><div class='ctx'> 		/*remove old surfaces from context */</div><div class='del'>-		if (!dc_rem_all_planes_for_stream(dc, stream, context)) {</div><div class='add'>+		if (!dc_state_rem_all_planes_for_stream(dc, stream, context)) {</div><div class='ctx'> </div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* add surface to context */</div><div class='del'>-		if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {</div><div class='add'>+		if (!dc_state_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {</div><div class='ctx'> </div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -3157,19 +3057,6 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	if (update_type == UPDATE_TYPE_FULL) {</div><div class='ctx'> 		if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, false)) {</div><div class='del'>-			/* For phantom pipes we remove and create a new set of phantom pipes</div><div class='del'>-			 * for each full update (because we don't know if we'll need phantom</div><div class='del'>-			 * pipes until after the first round of validation). However, if validation</div><div class='del'>-			 * fails we need to keep the existing phantom pipes (because we don't update</div><div class='del'>-			 * the dc-&gt;current_state).</div><div class='del'>-			 *</div><div class='del'>-			 * The phantom stream/plane refcount is decremented for validation because</div><div class='del'>-			 * we assume it'll be removed (the free comes when the dc_state is freed),</div><div class='del'>-			 * but if validation fails we have to increment back the refcount so it's</div><div class='del'>-			 * consistent.</div><div class='del'>-			 */</div><div class='del'>-			if (dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes)</div><div class='del'>-				dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes(dc, dc-&gt;current_state);</div><div class='ctx'> 			BREAK_TO_DEBUGGER();</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3190,7 +3077,7 @@ static bool update_planes_and_stream_state(struct dc *dc,</div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	dc_release_state(context);</div><div class='add'>+	dc_state_release(context);</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> </div><div class='hunk'>@@ -3386,7 +3273,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 			update_dirty_rect-&gt;panel_inst = panel_inst;</div><div class='ctx'> 			update_dirty_rect-&gt;pipe_idx = j;</div><div class='del'>-			dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+			dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -3488,18 +3375,24 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> {</div><div class='ctx'> 	int i, j;</div><div class='ctx'> 	struct pipe_ctx *top_pipe_to_program = NULL;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='ctx'> 	dc_z10_restore(dc);</div><div class='ctx'> </div><div class='ctx'> 	top_pipe_to_program = resource_get_otg_master_for_stream(</div><div class='ctx'> 			&amp;context-&gt;res_ctx,</div><div class='ctx'> 			stream);</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;debug.visual_confirm) {</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+	if (!top_pipe_to_program)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-			if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state)</div><div class='del'>-				dc_update_viusal_confirm_color(dc, context, pipe);</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='add'>+			set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;debug.visual_confirm)</div><div class='add'>+				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3523,6 +3416,8 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	stream_status = dc_state_get_stream_status(context, stream);</div><div class='add'>+</div><div class='ctx'> 	build_dmub_cmd_list(dc,</div><div class='ctx'> 			srf_updates,</div><div class='ctx'> 			surface_count,</div><div class='hunk'>@@ -3535,7 +3430,8 @@ static void commit_planes_for_stream_fast(struct dc *dc,</div><div class='ctx'> 			context-&gt;dmub_cmd_count,</div><div class='ctx'> 			context-&gt;block_sequence,</div><div class='ctx'> 			&amp;(context-&gt;block_sequence_steps),</div><div class='del'>-			top_pipe_to_program);</div><div class='add'>+			top_pipe_to_program,</div><div class='add'>+			stream_status);</div><div class='ctx'> 	hwss_execute_sequence(dc,</div><div class='ctx'> 			context-&gt;block_sequence,</div><div class='ctx'> 			context-&gt;block_sequence_steps);</div><div class='hunk'>@@ -3626,12 +3522,12 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	top_pipe_to_program = resource_get_otg_master_for_stream(</div><div class='ctx'> 				&amp;context-&gt;res_ctx,</div><div class='ctx'> 				stream);</div><div class='del'>-</div><div class='add'>+	ASSERT(top_pipe_to_program != NULL);</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		// Check old context for SubVP</div><div class='del'>-		subvp_prev_use |= (old_pipe-&gt;stream &amp;&amp; old_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM);</div><div class='add'>+		subvp_prev_use |= (dc_state_get_pipe_subvp_type(dc-&gt;current_state, old_pipe) == SUBVP_PHANTOM);</div><div class='ctx'> 		if (subvp_prev_use)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3639,19 +3535,22 @@ static void commit_planes_for_stream(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			subvp_curr_use = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;debug.visual_confirm)</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-			if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state)</div><div class='del'>-				dc_update_viusal_confirm_color(dc, context, pipe);</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='add'>+			set_p_state_switch_method(dc, context, pipe);</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;debug.visual_confirm)</div><div class='add'>+				dc_update_visual_confirm_color(dc, context, pipe);</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (stream-&gt;test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {</div><div class='ctx'> 		struct pipe_ctx *mpcc_pipe;</div><div class='hunk'>@@ -4024,7 +3923,7 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_NONE) {</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) != SUBVP_NONE) {</div><div class='ctx'> 			subvp_active = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4061,7 +3960,7 @@ struct pipe_split_policy_backup {</div><div class='ctx'> static void release_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context, struct pipe_split_policy_backup *policy)</div><div class='ctx'> {</div><div class='del'>-	dc_release_state(context);</div><div class='add'>+	dc_state_release(context);</div><div class='ctx'> 	/* restore previous pipe split and odm policy */</div><div class='ctx'> 	if (!dc-&gt;config.is_vmin_only_asic)</div><div class='ctx'> 		dc-&gt;debug.pipe_split_policy = policy-&gt;mpc_policy;</div><div class='hunk'>@@ -4072,7 +3971,7 @@ static void release_minimal_transition_state(struct dc *dc,</div><div class='ctx'> static struct dc_state *create_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 		struct dc_state *base_context, struct pipe_split_policy_backup *policy)</div><div class='ctx'> {</div><div class='del'>-	struct dc_state *minimal_transition_context = dc_create_state(dc);</div><div class='add'>+	struct dc_state *minimal_transition_context = NULL;</div><div class='ctx'> 	unsigned int i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc-&gt;config.is_vmin_only_asic) {</div><div class='hunk'>@@ -4084,7 +3983,9 @@ static struct dc_state *create_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 	policy-&gt;subvp_policy = dc-&gt;debug.force_disable_subvp;</div><div class='ctx'> 	dc-&gt;debug.force_disable_subvp = true;</div><div class='ctx'> </div><div class='del'>-	dc_resource_state_copy_construct(base_context, minimal_transition_context);</div><div class='add'>+	minimal_transition_context = dc_state_create_copy(base_context);</div><div class='add'>+	if (!minimal_transition_context)</div><div class='add'>+		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	/* commit minimal state */</div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, minimal_transition_context, false)) {</div><div class='hunk'>@@ -4116,7 +4017,6 @@ static bool commit_minimal_transition_state_for_windowed_mpo_odm(struct dc *dc,</div><div class='ctx'> 	bool success = false;</div><div class='ctx'> 	struct dc_state *minimal_transition_context;</div><div class='ctx'> 	struct pipe_split_policy_backup policy;</div><div class='del'>-	struct mall_temp_config mall_temp_config;</div><div class='ctx'> </div><div class='ctx'> 	/* commit based on new context */</div><div class='ctx'> 	/* Since all phantom pipes are removed in full validation,</div><div class='hunk'>@@ -4125,8 +4025,6 @@ static bool commit_minimal_transition_state_for_windowed_mpo_odm(struct dc *dc,</div><div class='ctx'> 	 * pipe as subvp/phantom will be cleared (dc copy constructor</div><div class='ctx'> 	 * creates a shallow copy).</div><div class='ctx'> 	 */</div><div class='del'>-	if (dc-&gt;res_pool-&gt;funcs-&gt;save_mall_state)</div><div class='del'>-		dc-&gt;res_pool-&gt;funcs-&gt;save_mall_state(dc, context, &amp;mall_temp_config);</div><div class='ctx'> 	minimal_transition_context = create_minimal_transition_state(dc,</div><div class='ctx'> 			context, &amp;policy);</div><div class='ctx'> 	if (minimal_transition_context) {</div><div class='hunk'>@@ -4139,16 +4037,6 @@ static bool commit_minimal_transition_state_for_windowed_mpo_odm(struct dc *dc,</div><div class='ctx'> 			success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK;</div><div class='ctx'> 		}</div><div class='ctx'> 		release_minimal_transition_state(dc, minimal_transition_context, &amp;policy);</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;restore_mall_state)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;restore_mall_state(dc, context, &amp;mall_temp_config);</div><div class='del'>-		/* If we do a minimal transition with plane removal and the context</div><div class='del'>-		 * has subvp we also have to retain back the phantom stream / planes</div><div class='del'>-		 * since the refcount is decremented as part of the min transition</div><div class='del'>-		 * (we commit a state with no subvp, so the phantom streams / planes</div><div class='del'>-		 * had to be removed).</div><div class='del'>-		 */</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes(dc, context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!success) {</div><div class='hunk'>@@ -4216,7 +4104,7 @@ static bool commit_minimal_transition_state(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			subvp_in_use = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4457,6 +4345,8 @@ static bool should_commit_minimal_transition_for_windowed_mpo_odm(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	cur_pipe = resource_get_otg_master_for_stream(&amp;dc-&gt;current_state-&gt;res_ctx, stream);</div><div class='ctx'> 	new_pipe = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='add'>+	if (!cur_pipe || !new_pipe)</div><div class='add'>+		return false;</div><div class='ctx'> 	cur_is_odm_in_use = resource_get_odm_slice_count(cur_pipe) &gt; 1;</div><div class='ctx'> 	new_is_odm_in_use = resource_get_odm_slice_count(new_pipe) &gt; 1;</div><div class='ctx'> 	if (cur_is_odm_in_use == new_is_odm_in_use)</div><div class='hunk'>@@ -4482,7 +4372,6 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> 	struct dc_state *context;</div><div class='ctx'> 	enum surface_update_type update_type;</div><div class='ctx'> 	int i;</div><div class='del'>-	struct mall_temp_config mall_temp_config;</div><div class='ctx'> 	struct dc_fast_update fast_update[MAX_SURFACES] = {0};</div><div class='ctx'> </div><div class='ctx'> 	/* In cases where MPO and split or ODM are used transitions can</div><div class='hunk'>@@ -4526,23 +4415,10 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> 		 * pipe as subvp/phantom will be cleared (dc copy constructor</div><div class='ctx'> 		 * creates a shallow copy).</div><div class='ctx'> 		 */</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;save_mall_state)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;save_mall_state(dc, context, &amp;mall_temp_config);</div><div class='ctx'> 		if (!commit_minimal_transition_state(dc, context)) {</div><div class='del'>-			dc_release_state(context);</div><div class='add'>+			dc_state_release(context);</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;restore_mall_state)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;restore_mall_state(dc, context, &amp;mall_temp_config);</div><div class='del'>-</div><div class='del'>-		/* If we do a minimal transition with plane removal and the context</div><div class='del'>-		 * has subvp we also have to retain back the phantom stream / planes</div><div class='del'>-		 * since the refcount is decremented as part of the min transition</div><div class='del'>-		 * (we commit a state with no subvp, so the phantom streams / planes</div><div class='del'>-		 * had to be removed).</div><div class='del'>-		 */</div><div class='del'>-		if (dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes)</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;retain_phantom_pipes(dc, context);</div><div class='ctx'> 		update_type = UPDATE_TYPE_FULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4599,7 +4475,7 @@ bool dc_update_planes_and_stream(struct dc *dc,</div><div class='ctx'> 		struct dc_state *old = dc-&gt;current_state;</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;current_state = context;</div><div class='del'>-		dc_release_state(old);</div><div class='add'>+		dc_state_release(old);</div><div class='ctx'> </div><div class='ctx'> 		// clear any forced full updates</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -4658,14 +4534,12 @@ void dc_commit_updates_for_stream(struct dc *dc,</div><div class='ctx'> 	if (update_type &gt;= UPDATE_TYPE_FULL) {</div><div class='ctx'> </div><div class='ctx'> 		/* initialize scratch memory for building context */</div><div class='del'>-		context = dc_create_state(dc);</div><div class='add'>+		context = dc_state_create_copy(state);</div><div class='ctx'> 		if (context == NULL) {</div><div class='ctx'> 			DC_ERROR("Failed to allocate new validate context!\n");</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		dc_resource_state_copy_construct(state, context);</div><div class='del'>-</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 			struct pipe_ctx *old_pipe = &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -4704,7 +4578,7 @@ void dc_commit_updates_for_stream(struct dc *dc,</div><div class='ctx'> 	if (update_type &gt;= UPDATE_TYPE_FULL) {</div><div class='ctx'> 		if (!dc-&gt;res_pool-&gt;funcs-&gt;validate_bandwidth(dc, context, false)) {</div><div class='ctx'> 			DC_ERROR("Mode validation failed for stream update!\n");</div><div class='del'>-			dc_release_state(context);</div><div class='add'>+			dc_state_release(context);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4737,7 +4611,7 @@ void dc_commit_updates_for_stream(struct dc *dc,</div><div class='ctx'> 		struct dc_state *old = dc-&gt;current_state;</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;current_state = context;</div><div class='del'>-		dc_release_state(old);</div><div class='add'>+		dc_state_release(old);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -4810,7 +4684,7 @@ void dc_set_power_state(</div><div class='ctx'> </div><div class='ctx'> 	switch (power_state) {</div><div class='ctx'> 	case DC_ACPI_CM_POWER_STATE_D0:</div><div class='del'>-		dc_resource_state_construct(dc, dc-&gt;current_state);</div><div class='add'>+		dc_state_construct(dc, dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 		dc_z10_restore(dc);</div><div class='ctx'> </div><div class='hunk'>@@ -4825,7 +4699,7 @@ void dc_set_power_state(</div><div class='ctx'> 	default:</div><div class='ctx'> 		ASSERT(dc-&gt;current_state-&gt;stream_count == 0);</div><div class='ctx'> </div><div class='del'>-		dc_resource_state_destruct(dc-&gt;current_state);</div><div class='add'>+		dc_state_destruct(dc-&gt;current_state);</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4902,6 +4776,38 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* enable/disable eDP Replay without specify stream for eDP */</div><div class='add'>+bool dc_set_replay_allow_active(struct dc *dc, bool active)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	bool allow_active;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;current_state-&gt;stream_count; i++) {</div><div class='add'>+		struct dc_link *link;</div><div class='add'>+		struct dc_stream_state *stream = dc-&gt;current_state-&gt;streams[i];</div><div class='add'>+</div><div class='add'>+		link = stream-&gt;link;</div><div class='add'>+		if (!link)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;replay_settings.replay_feature_enabled) {</div><div class='add'>+			if (active &amp;&amp; !link-&gt;replay_settings.replay_allow_active) {</div><div class='add'>+				allow_active = true;</div><div class='add'>+				if (!dc_link_set_replay_allow_active(link, &amp;allow_active,</div><div class='add'>+					false, false, NULL))</div><div class='add'>+					return false;</div><div class='add'>+			} else if (!active &amp;&amp; link-&gt;replay_settings.replay_allow_active) {</div><div class='add'>+				allow_active = false;</div><div class='add'>+				if (!dc_link_set_replay_allow_active(link, &amp;allow_active,</div><div class='add'>+					true, false, NULL))</div><div class='add'>+					return false;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dc_allow_idle_optimizations(struct dc *dc, bool allow)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;debug.disable_idle_power_optimizations)</div><div class='hunk'>@@ -5095,18 +5001,28 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)</div><div class='ctx'>  */</div><div class='ctx'> bool dc_is_dmub_outbox_supported(struct dc *dc)</div><div class='ctx'> {</div><div class='del'>-	/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */</div><div class='del'>-	if (dc-&gt;ctx-&gt;asic_id.chip_family == FAMILY_YELLOW_CARP &amp;&amp;</div><div class='del'>-	    dc-&gt;ctx-&gt;asic_id.hw_internal_rev == YELLOW_CARP_B0 &amp;&amp;</div><div class='del'>-	    !dc-&gt;debug.dpia_debug.bits.disable_dpia)</div><div class='del'>-		return true;</div><div class='add'>+	switch (dc-&gt;ctx-&gt;asic_id.chip_family) {</div><div class='ctx'> </div><div class='del'>-	if (dc-&gt;ctx-&gt;asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &amp;&amp;</div><div class='del'>-	    !dc-&gt;debug.dpia_debug.bits.disable_dpia)</div><div class='del'>-		return true;</div><div class='add'>+	case FAMILY_YELLOW_CARP:</div><div class='add'>+		/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */</div><div class='add'>+		if (dc-&gt;ctx-&gt;asic_id.hw_internal_rev == YELLOW_CARP_B0 &amp;&amp;</div><div class='add'>+		    !dc-&gt;debug.dpia_debug.bits.disable_dpia)</div><div class='add'>+			return true;</div><div class='add'>+	break;</div><div class='add'>+</div><div class='add'>+	case AMDGPU_FAMILY_GC_11_0_1:</div><div class='add'>+	case AMDGPU_FAMILY_GC_11_5_0:</div><div class='add'>+		if (!dc-&gt;debug.dpia_debug.bits.disable_dpia)</div><div class='add'>+			return true;</div><div class='add'>+	break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* dmub aux needs dmub notifications to be enabled */</div><div class='ctx'> 	return dc-&gt;debug.enable_dmub_aux_for_legacy_ddc;</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -5203,7 +5119,7 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,</div><div class='ctx'> 			);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -5257,7 +5173,7 @@ bool dc_process_dmub_set_config_async(struct dc *dc,</div><div class='ctx'> 	cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload-&gt;msg_type;</div><div class='ctx'> 	cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload-&gt;msg_data;</div><div class='ctx'> </div><div class='del'>-	if (!dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {</div><div class='ctx'> 		/* command is not processed by dmub */</div><div class='ctx'> 		notify-&gt;sc_status = SET_CONFIG_UNKNOWN_ERROR;</div><div class='ctx'> 		return is_cmd_complete;</div><div class='hunk'>@@ -5300,7 +5216,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,</div><div class='ctx'> 	cmd.set_mst_alloc_slots.mst_slots_control.instance = dc-&gt;links[link_index]-&gt;ddc_hw_inst;</div><div class='ctx'> 	cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;</div><div class='ctx'> </div><div class='del'>-	if (!dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='ctx'> 		/* command is not processed by dmub */</div><div class='ctx'> 		return DC_ERROR_UNEXPECTED;</div><div class='ctx'> </div><div class='hunk'>@@ -5338,7 +5254,7 @@ void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,</div><div class='ctx'> 	cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;</div><div class='ctx'> 	cmd.dpia_hpd_int_enable.enable = hpd_int_enable;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);</div><div class='ctx'> }</div><div class='hunk'>@@ -5437,6 +5353,8 @@ bool dc_abm_save_restore(</div><div class='ctx'> 	struct dc_link *link = stream-&gt;sink-&gt;link;</div><div class='ctx'> 	struct dc_link *edp_links[MAX_NUM_EDP];</div><div class='ctx'> </div><div class='add'>+	if (link-&gt;replay_settings.replay_feature_enabled)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	/*find primary pipe associated with stream*/</div><div class='ctx'> 	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c<br/>index fe07160932d6..9c05b1a07142 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #include "basics/dc_common.h"</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))</div><div class='ctx'> </div><div class='hunk'>@@ -425,45 +426,130 @@ void get_hdr_visual_confirm_color(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void get_subvp_visual_confirm_color(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='del'>-	bool enable_subvp = false;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !context)</div><div class='del'>-		return;</div><div class='add'>+	if (pipe_ctx) {</div><div class='add'>+		switch (pipe_ctx-&gt;p_state_type) {</div><div class='add'>+		case P_STATE_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = color_value;</div><div class='add'>+			color-&gt;color_g_y  = 0;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_DRR_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y  = color_value;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_V_BLANK_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y  = 0;</div><div class='add'>+			color-&gt;color_b_cb = color_value;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+void get_mclk_switch_visual_confirm_color(</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct tg_color *color)</div><div class='add'>+{</div><div class='add'>+	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.paired_stream &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='del'>-			/* SubVP enable - red */</div><div class='del'>-			color-&gt;color_g_y = 0;</div><div class='add'>+	if (pipe_ctx) {</div><div class='add'>+		switch (pipe_ctx-&gt;p_state_type) {</div><div class='add'>+		case P_STATE_V_BLANK:</div><div class='add'>+			color-&gt;color_r_cr = color_value;</div><div class='add'>+			color-&gt;color_g_y = color_value;</div><div class='ctx'> 			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_FPO:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y  = color_value;</div><div class='add'>+			color-&gt;color_b_cb = color_value;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_V_ACTIVE:</div><div class='ctx'> 			color-&gt;color_r_cr = color_value;</div><div class='del'>-			enable_subvp = true;</div><div class='del'>-</div><div class='del'>-			if (pipe_ctx-&gt;stream == pipe-&gt;stream)</div><div class='del'>-				return;</div><div class='add'>+			color-&gt;color_g_y  = 0;</div><div class='add'>+			color-&gt;color_b_cb = color_value;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = color_value;</div><div class='add'>+			color-&gt;color_g_y  = 0;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_DRR_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y  = color_value;</div><div class='add'>+			color-&gt;color_b_cb = 0;</div><div class='add'>+			break;</div><div class='add'>+		case P_STATE_V_BLANK_SUB_VP:</div><div class='add'>+			color-&gt;color_r_cr = 0;</div><div class='add'>+			color-&gt;color_g_y  = 0;</div><div class='add'>+			color-&gt;color_b_cb = color_value;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (enable_subvp &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='del'>-		color-&gt;color_r_cr = 0;</div><div class='del'>-		if (pipe_ctx-&gt;stream-&gt;allow_freesync == 1) {</div><div class='del'>-			/* SubVP enable and DRR on - green */</div><div class='del'>-			color-&gt;color_b_cb = 0;</div><div class='del'>-			color-&gt;color_g_y = color_value;</div><div class='add'>+void set_p_state_switch_method(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='add'>+	bool enable_subvp;</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !vba || !context)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (vba-&gt;DRAMClockChangeSupport[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb] !=</div><div class='add'>+			dm_dram_clock_change_unsupported) {</div><div class='add'>+		/* MCLK switching is supported */</div><div class='add'>+		if (!pipe_ctx-&gt;has_vactive_margin) {</div><div class='add'>+			/* In Vblank - yellow */</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_V_BLANK;</div><div class='add'>+</div><div class='add'>+			if (context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {</div><div class='add'>+				/* FPO + Vblank - cyan */</div><div class='add'>+				pipe_ctx-&gt;p_state_type = P_STATE_FPO;</div><div class='add'>+			}</div><div class='ctx'> 		} else {</div><div class='del'>-			/* SubVP enable and No DRR - blue */</div><div class='del'>-			color-&gt;color_g_y = 0;</div><div class='del'>-			color-&gt;color_b_cb = color_value;</div><div class='add'>+			/* In Vactive - pink */</div><div class='add'>+			pipe_ctx-&gt;p_state_type = P_STATE_V_ACTIVE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* SubVP */</div><div class='add'>+		enable_subvp = false;</div><div class='add'>+</div><div class='add'>+		for (int i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+			if (pipe-&gt;stream &amp;&amp; dc_state_get_paired_subvp_stream(context, pipe-&gt;stream) &amp;&amp;</div><div class='add'>+					dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='add'>+				/* SubVP enable - red */</div><div class='add'>+				pipe_ctx-&gt;p_state_type = P_STATE_SUB_VP;</div><div class='add'>+				enable_subvp = true;</div><div class='add'>+</div><div class='add'>+				if (pipe_ctx-&gt;stream == pipe-&gt;stream)</div><div class='add'>+					return;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (enable_subvp &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {</div><div class='add'>+			if (pipe_ctx-&gt;stream-&gt;allow_freesync == 1) {</div><div class='add'>+				/* SubVP enable and DRR on - green */</div><div class='add'>+				pipe_ctx-&gt;p_state_type = P_STATE_DRR_SUB_VP;</div><div class='add'>+			} else {</div><div class='add'>+				/* SubVP enable and No DRR - blue */</div><div class='add'>+				pipe_ctx-&gt;p_state_type = P_STATE_V_BLANK_SUB_VP;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -473,7 +559,8 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		unsigned int dmub_cmd_count,</div><div class='ctx'> 		struct block_sequence block_sequence[],</div><div class='ctx'> 		int *num_steps,</div><div class='del'>-		struct pipe_ctx *pipe_ctx)</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_status *stream_status)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_plane_state *plane = pipe_ctx-&gt;plane_state;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='hunk'>@@ -490,7 +577,8 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 	if (dc-&gt;hwss.subvp_pipe_control_lock_fast) {</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;</div><div class='del'>-		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =</div><div class='add'>+				plane-&gt;flip_immediate &amp;&amp; stream_status-&gt;mall_stream_config.type == SUBVP_MAIN;</div><div class='ctx'> 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;</div><div class='ctx'> 		(*num_steps)++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -529,7 +617,7 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 			}</div><div class='ctx'> 			if (dc-&gt;hwss.update_plane_addr &amp;&amp; current_mpc_pipe-&gt;plane_state-&gt;update_flags.bits.addr_update) {</div><div class='ctx'> 				if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &amp;&amp;</div><div class='del'>-						current_mpc_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+						stream_status-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='ctx'> 					block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='ctx'> 					block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &amp;current_mpc_pipe-&gt;plane_state-&gt;address;</div><div class='ctx'> 					block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe-&gt;subvp_index;</div><div class='hunk'>@@ -612,7 +700,8 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 	if (dc-&gt;hwss.subvp_pipe_control_lock_fast) {</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;</div><div class='ctx'> 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;</div><div class='del'>-		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.pipe_ctx = pipe_ctx;</div><div class='add'>+		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =</div><div class='add'>+				plane-&gt;flip_immediate &amp;&amp; stream_status-&gt;mall_stream_config.type == SUBVP_MAIN;</div><div class='ctx'> 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;</div><div class='ctx'> 		(*num_steps)++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -724,7 +813,7 @@ void hwss_send_dmcub_cmd(union block_sequence_params *params)</div><div class='ctx'> 	union dmub_rb_cmd *cmd = params-&gt;send_dmcub_cmd_params.cmd;</div><div class='ctx'> 	enum dm_dmub_wait_type wait_type = params-&gt;send_dmcub_cmd_params.wait_type;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(ctx, cmd, wait_type);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hwss_program_manual_trigger(union block_sequence_params *params)</div><div class='hunk'>@@ -812,42 +901,6 @@ void hwss_subvp_save_surf_addr(union block_sequence_params *params)</div><div class='ctx'> 	dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void get_mclk_switch_visual_confirm_color(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct pipe_ctx *pipe_ctx,</div><div class='del'>-		struct tg_color *color)</div><div class='del'>-{</div><div class='del'>-	uint32_t color_value = MAX_TG_COLOR_VALUE;</div><div class='del'>-	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='del'>-</div><div class='del'>-	if (!dc-&gt;ctx || !dc-&gt;ctx-&gt;dmub_srv || !pipe_ctx || !vba || !context)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (vba-&gt;DRAMClockChangeSupport[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb] !=</div><div class='del'>-			dm_dram_clock_change_unsupported) {</div><div class='del'>-		/* MCLK switching is supported */</div><div class='del'>-		if (!pipe_ctx-&gt;has_vactive_margin) {</div><div class='del'>-			/* In Vblank - yellow */</div><div class='del'>-			color-&gt;color_r_cr = color_value;</div><div class='del'>-			color-&gt;color_g_y = color_value;</div><div class='del'>-</div><div class='del'>-			if (context-&gt;bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {</div><div class='del'>-				/* FPO + Vblank - cyan */</div><div class='del'>-				color-&gt;color_r_cr = 0;</div><div class='del'>-				color-&gt;color_g_y  = color_value;</div><div class='del'>-				color-&gt;color_b_cb = color_value;</div><div class='del'>-			}</div><div class='del'>-		} else {</div><div class='del'>-			/* In Vactive - pink */</div><div class='del'>-			color-&gt;color_r_cr = color_value;</div><div class='del'>-			color-&gt;color_b_cb = color_value;</div><div class='del'>-		}</div><div class='del'>-		/* SubVP */</div><div class='del'>-		get_subvp_visual_confirm_color(dc, context, pipe_ctx, color);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void get_surface_tile_visual_confirm_color(</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c<br/>index ed94187c2afa..c6c35037bdb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c</a></div><div class='hunk'>@@ -467,6 +467,13 @@ bool dc_link_setup_psr(struct dc_link *link,</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;edp_setup_psr(link, stream, psr_config, psr_context);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool dc_link_set_replay_allow_active(struct dc_link *link, const bool *allow_active,</div><div class='add'>+		bool wait, bool force_static, const unsigned int *power_opts)</div><div class='add'>+{</div><div class='add'>+	return link-&gt;dc-&gt;link_srv-&gt;edp_set_replay_allow_active(link, allow_active, wait,</div><div class='add'>+			force_static, power_opts);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dc_link_get_replay_state(const struct dc_link *link, uint64_t *state)</div><div class='ctx'> {</div><div class='ctx'> 	return link-&gt;dc-&gt;link_srv-&gt;edp_get_replay_state(link, state);</div><div class='hunk'>@@ -497,7 +504,7 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)</div><div class='ctx'> 	link-&gt;dc-&gt;link_srv-&gt;enable_hpd_filter(link, enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count)</div><div class='add'>+bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count)</div><div class='ctx'> {</div><div class='ctx'> 	return dc-&gt;link_srv-&gt;validate_dpia_bandwidth(streams, count);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c<br/>index a1f1d1003992..9fbdb09697fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_resource.c</a></div><div class='hunk'>@@ -42,6 +42,7 @@</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #include "link.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> #include "virtual/virtual_link_hwss.h"</div><div class='ctx'> #include "link/hwss/link_hwss_dio.h"</div><div class='ctx'> #include "link/hwss/link_hwss_dpia.h"</div><div class='hunk'>@@ -69,8 +70,8 @@</div><div class='ctx'> #include "dcn314/dcn314_resource.h"</div><div class='ctx'> #include "dcn315/dcn315_resource.h"</div><div class='ctx'> #include "dcn316/dcn316_resource.h"</div><div class='del'>-#include "../dcn32/dcn32_resource.h"</div><div class='del'>-#include "../dcn321/dcn321_resource.h"</div><div class='add'>+#include "dcn32/dcn32_resource.h"</div><div class='add'>+#include "dcn321/dcn321_resource.h"</div><div class='ctx'> #include "dcn35/dcn35_resource.h"</div><div class='ctx'> </div><div class='ctx'> #define VISUAL_CONFIRM_BASE_DEFAULT 3</div><div class='hunk'>@@ -1764,6 +1765,29 @@ int recource_find_free_pipe_not_used_in_cur_res_ctx(</div><div class='ctx'> 	return free_pipe_idx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='add'>+		const struct resource_context *cur_res_ctx,</div><div class='add'>+		struct resource_context *new_res_ctx,</div><div class='add'>+		const struct resource_pool *pool)</div><div class='add'>+{</div><div class='add'>+	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;</div><div class='add'>+	const struct pipe_ctx *new_pipe, *cur_pipe;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pool-&gt;pipe_count; i++) {</div><div class='add'>+		cur_pipe = &amp;cur_res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+		new_pipe = &amp;new_res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (resource_is_pipe_type(cur_pipe, OTG_MASTER) &amp;&amp;</div><div class='add'>+				resource_is_pipe_type(new_pipe, FREE_PIPE)) {</div><div class='add'>+			free_pipe_idx = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return free_pipe_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(</div><div class='ctx'> 		const struct resource_context *cur_res_ctx,</div><div class='ctx'> 		struct resource_context *new_res_ctx,</div><div class='hunk'>@@ -2170,6 +2194,10 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)</div><div class='ctx'> 	for (stream_idx = 0; stream_idx &lt; state-&gt;stream_count; stream_idx++) {</div><div class='ctx'> 		otg_master = resource_get_otg_master_for_stream(</div><div class='ctx'> 				&amp;state-&gt;res_ctx, state-&gt;streams[stream_idx]);</div><div class='add'>+		if (!otg_master	|| otg_master-&gt;stream_res.tg == NULL) {</div><div class='add'>+			DC_LOG_DC("topology update: otg_master NULL stream_idx %d!\n", stream_idx);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 		slice_count = resource_get_opp_heads_for_otg_master(otg_master,</div><div class='ctx'> 				&amp;state-&gt;res_ctx, opp_heads);</div><div class='ctx'> 		for (slice_idx = 0; slice_idx &lt; slice_count; slice_idx++) {</div><div class='hunk'>@@ -2233,7 +2261,7 @@ static struct pipe_ctx *get_last_dpp_pipe_in_mpcc_combine(</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool update_pipe_params_after_odm_slice_count_change(</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='add'>+		struct pipe_ctx *otg_master,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		const struct resource_pool *pool)</div><div class='ctx'> {</div><div class='hunk'>@@ -2243,9 +2271,12 @@ static bool update_pipe_params_after_odm_slice_count_change(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;pipe_count &amp;&amp; result; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		if (pipe-&gt;stream == stream &amp;&amp; pipe-&gt;plane_state)</div><div class='add'>+		if (pipe-&gt;stream == otg_master-&gt;stream &amp;&amp; pipe-&gt;plane_state)</div><div class='ctx'> 			result = resource_build_scaling_params(pipe);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (pool-&gt;funcs-&gt;build_pipe_pix_clk_params)</div><div class='add'>+		pool-&gt;funcs-&gt;build_pipe_pix_clk_params(otg_master);</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2433,6 +2464,9 @@ void resource_remove_otg_master_for_stream_output(struct dc_state *context,</div><div class='ctx'> 	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(</div><div class='ctx'> 			&amp;context-&gt;res_ctx, stream);</div><div class='ctx'> </div><div class='add'>+	if (!otg_master)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	ASSERT(resource_get_odm_slice_count(otg_master) == 1);</div><div class='ctx'> 	ASSERT(otg_master-&gt;plane_state == NULL);</div><div class='ctx'> 	ASSERT(otg_master-&gt;stream_res.stream_enc);</div><div class='hunk'>@@ -2928,7 +2962,7 @@ bool resource_update_pipes_for_stream_with_slice_count(</div><div class='ctx'> 					otg_master, new_ctx, pool);</div><div class='ctx'> 	if (result)</div><div class='ctx'> 		result = update_pipe_params_after_odm_slice_count_change(</div><div class='del'>-				otg_master-&gt;stream, new_ctx, pool);</div><div class='add'>+				otg_master, new_ctx, pool);</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2967,189 +3001,6 @@ bool resource_update_pipes_for_plane_with_slice_count(</div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_add_plane_to_context(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state *plane_state,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='del'>-	struct pipe_ctx *otg_master_pipe;</div><div class='del'>-	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	bool added = false;</div><div class='del'>-</div><div class='del'>-	stream_status = dc_stream_get_status_from_state(context, stream);</div><div class='del'>-	if (stream_status == NULL) {</div><div class='del'>-		dm_error("Existing stream not found; failed to attach surface!\n");</div><div class='del'>-		goto out;</div><div class='del'>-	} else if (stream_status-&gt;plane_count == MAX_SURFACE_NUM) {</div><div class='del'>-		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",</div><div class='del'>-				plane_state, MAX_SURFACE_NUM);</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	otg_master_pipe = resource_get_otg_master_for_stream(</div><div class='del'>-			&amp;context-&gt;res_ctx, stream);</div><div class='del'>-	added = resource_append_dpp_pipes_for_plane_composition(context,</div><div class='del'>-			dc-&gt;current_state, pool, otg_master_pipe, plane_state);</div><div class='del'>-</div><div class='del'>-	if (added) {</div><div class='del'>-		stream_status-&gt;plane_states[stream_status-&gt;plane_count] =</div><div class='del'>-				plane_state;</div><div class='del'>-		stream_status-&gt;plane_count++;</div><div class='del'>-		dc_plane_state_retain(plane_state);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	return added;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool dc_remove_plane_from_context(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state *plane_state,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='del'>-</div><div class='del'>-	if (!plane_state)</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='del'>-		if (context-&gt;streams[i] == stream) {</div><div class='del'>-			stream_status = &amp;context-&gt;stream_status[i];</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	if (stream_status == NULL) {</div><div class='del'>-		dm_error("Existing stream not found; failed to remove plane.\n");</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	resource_remove_dpp_pipes_for_plane_composition(</div><div class='del'>-			context, pool, plane_state);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; stream_status-&gt;plane_count; i++) {</div><div class='del'>-		if (stream_status-&gt;plane_states[i] == plane_state) {</div><div class='del'>-			dc_plane_state_release(stream_status-&gt;plane_states[i]);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (i == stream_status-&gt;plane_count) {</div><div class='del'>-		dm_error("Existing plane_state not found; failed to detach it!\n");</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	stream_status-&gt;plane_count--;</div><div class='del'>-</div><div class='del'>-	/* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */</div><div class='del'>-	for (; i &lt; stream_status-&gt;plane_count; i++)</div><div class='del'>-		stream_status-&gt;plane_states[i] = stream_status-&gt;plane_states[i + 1];</div><div class='del'>-</div><div class='del'>-	stream_status-&gt;plane_states[stream_status-&gt;plane_count] = NULL;</div><div class='del'>-</div><div class='del'>-	if (stream_status-&gt;plane_count == 0 &amp;&amp; dc-&gt;config.enable_windowed_mpo_odm)</div><div class='del'>-		/* ODM combine could prevent us from supporting more planes</div><div class='del'>-		 * we will reset ODM slice count back to 1 when all planes have</div><div class='del'>-		 * been removed to maximize the amount of planes supported when</div><div class='del'>-		 * new planes are added.</div><div class='del'>-		 */</div><div class='del'>-		resource_update_pipes_for_stream_with_slice_count(</div><div class='del'>-				context, dc-&gt;current_state, dc-&gt;res_pool, stream, 1);</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dc_rem_all_planes_for_stream - Remove planes attached to the target stream.</div><div class='del'>- *</div><div class='del'>- * @dc: Current dc state.</div><div class='del'>- * @stream: Target stream, which we want to remove the attached plans.</div><div class='del'>- * @context: New context.</div><div class='del'>- *</div><div class='del'>- * Return:</div><div class='del'>- * Return true if DC was able to remove all planes from the target</div><div class='del'>- * stream, otherwise, return false.</div><div class='del'>- */</div><div class='del'>-bool dc_rem_all_planes_for_stream(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i, old_plane_count;</div><div class='del'>-	struct dc_stream_status *stream_status = NULL;</div><div class='del'>-	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; context-&gt;stream_count; i++)</div><div class='del'>-			if (context-&gt;streams[i] == stream) {</div><div class='del'>-				stream_status = &amp;context-&gt;stream_status[i];</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-	if (stream_status == NULL) {</div><div class='del'>-		dm_error("Existing stream %p not found!\n", stream);</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	old_plane_count = stream_status-&gt;plane_count;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; old_plane_count; i++)</div><div class='del'>-		del_planes[i] = stream_status-&gt;plane_states[i];</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; old_plane_count; i++)</div><div class='del'>-		if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool add_all_planes_for_stream(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		const struct dc_validation_set set[],</div><div class='del'>-		int set_count,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i, j;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; set_count; i++)</div><div class='del'>-		if (set[i].stream == stream)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-	if (i == set_count) {</div><div class='del'>-		dm_error("Stream %p not found in set!\n", stream);</div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (j = 0; j &lt; set[i].plane_count; j++)</div><div class='del'>-		if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))</div><div class='del'>-			return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-bool dc_add_all_planes_for_stream(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state * const *plane_states,</div><div class='del'>-		int plane_count,</div><div class='del'>-		struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	struct dc_validation_set set;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	set.stream = stream;</div><div class='del'>-	set.plane_count = plane_count;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; plane_count; i++)</div><div class='del'>-		set.plane_states[i] = plane_states[i];</div><div class='del'>-</div><div class='del'>-	return add_all_planes_for_stream(dc, stream, &amp;set, 1, context);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool dc_is_timing_changed(struct dc_stream_state *cur_stream,</div><div class='ctx'> 		       struct dc_stream_state *new_stream)</div><div class='ctx'> {</div><div class='hunk'>@@ -3301,84 +3152,6 @@ static struct audio *find_first_free_audio(</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.</div><div class='del'>- */</div><div class='del'>-enum dc_status dc_add_stream_to_ctx(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *new_ctx,</div><div class='del'>-		struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	enum dc_status res;</div><div class='del'>-	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='del'>-</div><div class='del'>-	if (new_ctx-&gt;stream_count &gt;= dc-&gt;res_pool-&gt;timing_generator_count) {</div><div class='del'>-		DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);</div><div class='del'>-		return DC_ERROR_UNEXPECTED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	new_ctx-&gt;streams[new_ctx-&gt;stream_count] = stream;</div><div class='del'>-	dc_stream_retain(stream);</div><div class='del'>-	new_ctx-&gt;stream_count++;</div><div class='del'>-</div><div class='del'>-	res = resource_add_otg_master_for_stream_output(</div><div class='del'>-			new_ctx, dc-&gt;res_pool, stream);</div><div class='del'>-	if (res != DC_OK)</div><div class='del'>-		DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);</div><div class='del'>-</div><div class='del'>-	return res;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.</div><div class='del'>- */</div><div class='del'>-enum dc_status dc_remove_stream_from_ctx(</div><div class='del'>-			struct dc *dc,</div><div class='del'>-			struct dc_state *new_ctx,</div><div class='del'>-			struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct dc_context *dc_ctx = dc-&gt;ctx;</div><div class='del'>-	struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(</div><div class='del'>-			&amp;new_ctx-&gt;res_ctx, stream);</div><div class='del'>-</div><div class='del'>-	if (!del_pipe) {</div><div class='del'>-		DC_ERROR("Pipe not found for stream %p !\n", stream);</div><div class='del'>-		return DC_ERROR_UNEXPECTED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	resource_update_pipes_for_stream_with_slice_count(new_ctx,</div><div class='del'>-			dc-&gt;current_state, dc-&gt;res_pool, stream, 1);</div><div class='del'>-	resource_remove_otg_master_for_stream_output(</div><div class='del'>-			new_ctx, dc-&gt;res_pool, stream);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; new_ctx-&gt;stream_count; i++)</div><div class='del'>-		if (new_ctx-&gt;streams[i] == stream)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-	if (new_ctx-&gt;streams[i] != stream) {</div><div class='del'>-		DC_ERROR("Context doesn't have stream %p !\n", stream);</div><div class='del'>-		return DC_ERROR_UNEXPECTED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dc_stream_release(new_ctx-&gt;streams[i]);</div><div class='del'>-	new_ctx-&gt;stream_count--;</div><div class='del'>-</div><div class='del'>-	/* Trim back arrays */</div><div class='del'>-	for (; i &lt; new_ctx-&gt;stream_count; i++) {</div><div class='del'>-		new_ctx-&gt;streams[i] = new_ctx-&gt;streams[i + 1];</div><div class='del'>-		new_ctx-&gt;stream_status[i] = new_ctx-&gt;stream_status[i + 1];</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	new_ctx-&gt;streams[new_ctx-&gt;stream_count] = NULL;</div><div class='del'>-	memset(</div><div class='del'>-			&amp;new_ctx-&gt;stream_status[new_ctx-&gt;stream_count],</div><div class='del'>-			0,</div><div class='del'>-			sizeof(new_ctx-&gt;stream_status[0]));</div><div class='del'>-</div><div class='del'>-	return DC_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct dc_stream_state *find_pll_sharable_stream(</div><div class='ctx'> 		struct dc_stream_state *stream_needs_pll,</div><div class='ctx'> 		struct dc_state *context)</div><div class='hunk'>@@ -3586,6 +3359,7 @@ static void mark_seamless_boot_stream(</div><div class='ctx'>  *       |________|_______________|___________|_____________|</div><div class='ctx'>  */</div><div class='ctx'> static bool acquire_otg_master_pipe_for_stream(</div><div class='add'>+		const struct dc_state *cur_ctx,</div><div class='ctx'> 		struct dc_state *new_ctx,</div><div class='ctx'> 		const struct resource_pool *pool,</div><div class='ctx'> 		struct dc_stream_state *stream)</div><div class='hunk'>@@ -3599,7 +3373,22 @@ static bool acquire_otg_master_pipe_for_stream(</div><div class='ctx'> 	int pipe_idx;</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx = NULL;</div><div class='ctx'> </div><div class='del'>-	pipe_idx = resource_find_any_free_pipe(&amp;new_ctx-&gt;res_ctx, pool);</div><div class='add'>+	/*</div><div class='add'>+	 * Upper level code is responsible to optimize unnecessary addition and</div><div class='add'>+	 * removal for unchanged streams. So unchanged stream will keep the same</div><div class='add'>+	 * OTG master instance allocated. When current stream is removed and a</div><div class='add'>+	 * new stream is added, we want to reuse the OTG instance made available</div><div class='add'>+	 * by the removed stream first. If not found, we try to avoid of using</div><div class='add'>+	 * any free pipes already used in current context as this could tear</div><div class='add'>+	 * down exiting ODM/MPC/MPO configuration unnecessarily.</div><div class='add'>+	 */</div><div class='add'>+	pipe_idx = recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='add'>+			&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx, pool);</div><div class='add'>+	if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)</div><div class='add'>+		pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(</div><div class='add'>+				&amp;cur_ctx-&gt;res_ctx, &amp;new_ctx-&gt;res_ctx, pool);</div><div class='add'>+	if (pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)</div><div class='add'>+		pipe_idx = resource_find_any_free_pipe(&amp;new_ctx-&gt;res_ctx, pool);</div><div class='ctx'> 	if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {</div><div class='ctx'> 		pipe_ctx = &amp;new_ctx-&gt;res_ctx.pipe_ctx[pipe_idx];</div><div class='ctx'> 		memset(pipe_ctx, 0, sizeof(*pipe_ctx));</div><div class='hunk'>@@ -3659,7 +3448,7 @@ enum dc_status resource_map_pool_resources(</div><div class='ctx'> </div><div class='ctx'> 	if (!acquired)</div><div class='ctx'> 		/* acquire new resources */</div><div class='del'>-		acquired = acquire_otg_master_pipe_for_stream(</div><div class='add'>+		acquired = acquire_otg_master_pipe_for_stream(dc-&gt;current_state,</div><div class='ctx'> 				context, pool, stream);</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx = resource_get_otg_master_for_stream(&amp;context-&gt;res_ctx, stream);</div><div class='hunk'>@@ -3742,34 +3531,6 @@ enum dc_status resource_map_pool_resources(</div><div class='ctx'> 	return DC_ERROR_UNEXPECTED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state</div><div class='del'>- *</div><div class='del'>- * @dc: copy out of dc-&gt;current_state</div><div class='del'>- * @dst_ctx: copy into this</div><div class='del'>- *</div><div class='del'>- * This function makes a shallow copy of the current DC state and increments</div><div class='del'>- * refcounts on existing streams and planes.</div><div class='del'>- */</div><div class='del'>-void dc_resource_state_copy_construct_current(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_state *dst_ctx)</div><div class='del'>-{</div><div class='del'>-	dc_resource_state_copy_construct(dc-&gt;current_state, dst_ctx);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-void dc_resource_state_construct(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_state *dst_ctx)</div><div class='del'>-{</div><div class='del'>-	dst_ctx-&gt;clk_mgr = dc-&gt;clk_mgr;</div><div class='del'>-</div><div class='del'>-	/* Initialise DIG link encoder resource tracking variables. */</div><div class='del'>-	link_enc_cfg_init(dc, dst_ctx);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	if (dc-&gt;res_pool == NULL)</div><div class='hunk'>@@ -3813,6 +3574,31 @@ static bool planes_changed_for_existing_stream(struct dc_state *context,</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool add_all_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		const struct dc_validation_set set[],</div><div class='add'>+		int set_count,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; set_count; i++)</div><div class='add'>+		if (set[i].stream == stream)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+	if (i == set_count) {</div><div class='add'>+		dm_error("Stream %p not found in set!\n", stream);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; set[i].plane_count; j++)</div><div class='add'>+		if (!dc_state_add_plane(dc, stream, set[i].plane_states[j], state))</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * dc_validate_with_context - Validate and update the potential new stream in the context object</div><div class='ctx'>  *</div><div class='hunk'>@@ -3918,7 +3704,8 @@ enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='ctx'> 						       unchanged_streams[i],</div><div class='ctx'> 						       set,</div><div class='ctx'> 						       set_count)) {</div><div class='del'>-			if (!dc_rem_all_planes_for_stream(dc,</div><div class='add'>+</div><div class='add'>+			if (!dc_state_rem_all_planes_for_stream(dc,</div><div class='ctx'> 							  unchanged_streams[i],</div><div class='ctx'> 							  context)) {</div><div class='ctx'> 				res = DC_FAIL_DETACH_SURFACES;</div><div class='hunk'>@@ -3940,12 +3727,24 @@ enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {</div><div class='del'>-			res = DC_FAIL_DETACH_SURFACES;</div><div class='del'>-			goto fail;</div><div class='add'>+		if (dc_state_get_stream_subvp_type(context, del_streams[i]) == SUBVP_PHANTOM) {</div><div class='add'>+			/* remove phantoms specifically */</div><div class='add'>+			if (!dc_state_rem_all_phantom_planes_for_stream(dc, del_streams[i], context, true)) {</div><div class='add'>+				res = DC_FAIL_DETACH_SURFACES;</div><div class='add'>+				goto fail;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			res = dc_state_remove_phantom_stream(dc, context, del_streams[i]);</div><div class='add'>+			dc_state_release_phantom_stream(dc, context, del_streams[i]);</div><div class='add'>+		} else {</div><div class='add'>+			if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) {</div><div class='add'>+				res = DC_FAIL_DETACH_SURFACES;</div><div class='add'>+				goto fail;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			res = dc_state_remove_stream(dc, context, del_streams[i]);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);</div><div class='ctx'> 		if (res != DC_OK)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3968,7 +3767,7 @@ enum dc_status dc_validate_with_context(struct dc *dc,</div><div class='ctx'> 	/* Add new streams and then add all planes for the new stream */</div><div class='ctx'> 	for (i = 0; i &lt; add_streams_count; i++) {</div><div class='ctx'> 		calculate_phy_pix_clks(add_streams[i]);</div><div class='del'>-		res = dc_add_stream_to_ctx(dc, context, add_streams[i]);</div><div class='add'>+		res = dc_state_add_stream(dc, context, add_streams[i]);</div><div class='ctx'> 		if (res != DC_OK)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> </div><div class='hunk'>@@ -4474,84 +4273,6 @@ static void set_vtem_info_packet(</div><div class='ctx'> 	*info_packet = stream-&gt;vtem_infopacket;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_resource_state_destruct(struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i, j;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-		for (j = 0; j &lt; context-&gt;stream_status[i].plane_count; j++)</div><div class='del'>-			dc_plane_state_release(</div><div class='del'>-				context-&gt;stream_status[i].plane_states[j]);</div><div class='del'>-</div><div class='del'>-		context-&gt;stream_status[i].plane_count = 0;</div><div class='del'>-		dc_stream_release(context-&gt;streams[i]);</div><div class='del'>-		context-&gt;streams[i] = NULL;</div><div class='del'>-	}</div><div class='del'>-	context-&gt;stream_count = 0;</div><div class='del'>-	context-&gt;stream_mask = 0;</div><div class='del'>-	memset(&amp;context-&gt;res_ctx, 0, sizeof(context-&gt;res_ctx));</div><div class='del'>-	memset(&amp;context-&gt;pp_display_cfg, 0, sizeof(context-&gt;pp_display_cfg));</div><div class='del'>-	memset(&amp;context-&gt;dcn_bw_vars, 0, sizeof(context-&gt;dcn_bw_vars));</div><div class='del'>-	context-&gt;clk_mgr = NULL;</div><div class='del'>-	memset(&amp;context-&gt;bw_ctx.bw, 0, sizeof(context-&gt;bw_ctx.bw));</div><div class='del'>-	memset(context-&gt;block_sequence, 0, sizeof(context-&gt;block_sequence));</div><div class='del'>-	context-&gt;block_sequence_steps = 0;</div><div class='del'>-	memset(context-&gt;dc_dmub_cmd, 0, sizeof(context-&gt;dc_dmub_cmd));</div><div class='del'>-	context-&gt;dmub_cmd_count = 0;</div><div class='del'>-	memset(&amp;context-&gt;perf_params, 0, sizeof(context-&gt;perf_params));</div><div class='del'>-	memset(&amp;context-&gt;scratch, 0, sizeof(context-&gt;scratch));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dc_resource_state_copy_construct(</div><div class='del'>-		const struct dc_state *src_ctx,</div><div class='del'>-		struct dc_state *dst_ctx)</div><div class='del'>-{</div><div class='del'>-	int i, j;</div><div class='del'>-	struct kref refcount = dst_ctx-&gt;refcount;</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	struct dml2_context *dml2 = NULL;</div><div class='del'>-</div><div class='del'>-	// Need to preserve allocated dml2 context</div><div class='del'>-	if (src_ctx-&gt;clk_mgr-&gt;ctx-&gt;dc-&gt;debug.using_dml2)</div><div class='del'>-		dml2 = dst_ctx-&gt;bw_ctx.dml2;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	*dst_ctx = *src_ctx;</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='del'>-	// Preserve allocated dml2 context</div><div class='del'>-	if (src_ctx-&gt;clk_mgr-&gt;ctx-&gt;dc-&gt;debug.using_dml2)</div><div class='del'>-		dst_ctx-&gt;bw_ctx.dml2 = dml2;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='del'>-		struct pipe_ctx *cur_pipe = &amp;dst_ctx-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (cur_pipe-&gt;top_pipe)</div><div class='del'>-			cur_pipe-&gt;top_pipe =  &amp;dst_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;top_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-		if (cur_pipe-&gt;bottom_pipe)</div><div class='del'>-			cur_pipe-&gt;bottom_pipe = &amp;dst_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;bottom_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-		if (cur_pipe-&gt;next_odm_pipe)</div><div class='del'>-			cur_pipe-&gt;next_odm_pipe =  &amp;dst_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;next_odm_pipe-&gt;pipe_idx];</div><div class='del'>-</div><div class='del'>-		if (cur_pipe-&gt;prev_odm_pipe)</div><div class='del'>-			cur_pipe-&gt;prev_odm_pipe = &amp;dst_ctx-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;prev_odm_pipe-&gt;pipe_idx];</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dst_ctx-&gt;stream_count; i++) {</div><div class='del'>-		dc_stream_retain(dst_ctx-&gt;streams[i]);</div><div class='del'>-		for (j = 0; j &lt; dst_ctx-&gt;stream_status[i].plane_count; j++)</div><div class='del'>-			dc_plane_state_retain(</div><div class='del'>-				dst_ctx-&gt;stream_status[i].plane_states[j]);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* context refcount should not be overridden */</div><div class='del'>-	dst_ctx-&gt;refcount = refcount;</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct clock_source *dc_resource_find_first_free_pll(</div><div class='ctx'> 		struct resource_context *res_ctx,</div><div class='ctx'> 		const struct resource_pool *pool)</div><div class='hunk'>@@ -4731,7 +4452,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,</div><div class='ctx'> 			option = DITHER_OPTION_SPATIAL8;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case COLOR_DEPTH_101010:</div><div class='del'>-			option = DITHER_OPTION_SPATIAL10;</div><div class='add'>+			option = DITHER_OPTION_TRUN10;</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			option = DITHER_OPTION_DISABLE;</div><div class='hunk'>@@ -4757,6 +4478,8 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,</div><div class='ctx'> 			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {</div><div class='ctx'> 		fmt_bit_depth-&gt;flags.TRUNCATE_ENABLED = 1;</div><div class='ctx'> 		fmt_bit_depth-&gt;flags.TRUNCATE_DEPTH = 2;</div><div class='add'>+		if (option == DITHER_OPTION_TRUN10)</div><div class='add'>+			fmt_bit_depth-&gt;flags.TRUNCATE_MODE = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* special case - Formatter can only reduce by 4 bits at most.</div><div class='hunk'>@@ -5274,7 +4997,7 @@ bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_st</div><div class='ctx'> 	if (dc-&gt;current_state-&gt;stream_count == 1 &amp;&amp; stream-&gt;timing.v_addressable &gt;= 2880 &amp;&amp;</div><div class='ctx'> 			((stream-&gt;timing.pix_clk_100hz * 100) / stream-&gt;timing.v_total / stream-&gt;timing.h_total) &lt; 120)</div><div class='ctx'> 		return true;</div><div class='del'>-	else if (dc-&gt;current_state-&gt;stream_count &gt; 1 &amp;&amp; stream-&gt;timing.v_addressable &gt;= 2160 &amp;&amp;</div><div class='add'>+	else if (dc-&gt;current_state-&gt;stream_count &gt; 1 &amp;&amp; stream-&gt;timing.v_addressable &gt;= 1080 &amp;&amp;</div><div class='ctx'> 			((stream-&gt;timing.pix_clk_100hz * 100) / stream-&gt;timing.v_total / stream-&gt;timing.h_total) &lt; 120)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c<br/>new file mode 100644<br/>index 000000000000..88c6436b28b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_state.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_state.c</a></div><div class='hunk'>@@ -0,0 +1,867 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+#include "core_types.h"</div><div class='add'>+#include "core_status.h"</div><div class='add'>+#include "dc_state.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+#include "dc_stream_priv.h"</div><div class='add'>+#include "dc_plane_priv.h"</div><div class='add'>+</div><div class='add'>+#include "dm_services.h"</div><div class='add'>+#include "resource.h"</div><div class='add'>+#include "link_enc_cfg.h"</div><div class='add'>+</div><div class='add'>+#include "dml2/dml2_wrapper.h"</div><div class='add'>+#include "dml2/dml2_internal_types.h"</div><div class='add'>+</div><div class='add'>+#define DC_LOGGER \</div><div class='add'>+	dc-&gt;ctx-&gt;logger</div><div class='add'>+#define DC_LOGGER_INIT(logger)</div><div class='add'>+</div><div class='add'>+/* Private dc_state helper functions */</div><div class='add'>+static bool dc_state_track_phantom_stream(struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream)</div><div class='add'>+{</div><div class='add'>+	if (state-&gt;phantom_stream_count &gt;= MAX_PHANTOM_PIPES)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	state-&gt;phantom_streams[state-&gt;phantom_stream_count++] = phantom_stream;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_state_untrack_phantom_stream(struct dc_state *state, struct dc_stream_state *phantom_stream)</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* first find phantom stream in the dc_state */</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_stream_count; i++) {</div><div class='add'>+		if (state-&gt;phantom_streams[i] == phantom_stream) {</div><div class='add'>+			state-&gt;phantom_streams[i] = NULL;</div><div class='add'>+			res = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* failed to find stream in state */</div><div class='add'>+	if (!res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	/* trim back phantom streams */</div><div class='add'>+	state-&gt;phantom_stream_count--;</div><div class='add'>+	for (; i &lt; state-&gt;phantom_stream_count; i++)</div><div class='add'>+		state-&gt;phantom_streams[i] = state-&gt;phantom_streams[i + 1];</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_state_is_phantom_stream_tracked(struct dc_state *state, struct dc_stream_state *phantom_stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_stream_count; i++) {</div><div class='add'>+		if (state-&gt;phantom_streams[i] == phantom_stream)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_state_track_phantom_plane(struct dc_state *state,</div><div class='add'>+		struct dc_plane_state *phantom_plane)</div><div class='add'>+{</div><div class='add'>+	if (state-&gt;phantom_plane_count &gt;= MAX_PHANTOM_PIPES)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	state-&gt;phantom_planes[state-&gt;phantom_plane_count++] = phantom_plane;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_state_untrack_phantom_plane(struct dc_state *state, struct dc_plane_state *phantom_plane)</div><div class='add'>+{</div><div class='add'>+	bool res = false;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* first find phantom plane in the dc_state */</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_plane_count; i++) {</div><div class='add'>+		if (state-&gt;phantom_planes[i] == phantom_plane) {</div><div class='add'>+			state-&gt;phantom_planes[i] = NULL;</div><div class='add'>+			res = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* failed to find plane in state */</div><div class='add'>+	if (!res)</div><div class='add'>+		return res;</div><div class='add'>+</div><div class='add'>+	/* trim back phantom planes */</div><div class='add'>+	state-&gt;phantom_plane_count--;</div><div class='add'>+	for (; i &lt; state-&gt;phantom_plane_count; i++)</div><div class='add'>+		state-&gt;phantom_planes[i] = state-&gt;phantom_planes[i + 1];</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_state_is_phantom_plane_tracked(struct dc_state *state, struct dc_plane_state *phantom_plane)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_plane_count; i++) {</div><div class='add'>+		if (state-&gt;phantom_planes[i] == phantom_plane)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dc_state_copy_internal(struct dc_state *dst_state, struct dc_state *src_state)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	memcpy(dst_state, src_state, sizeof(struct dc_state));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MAX_PIPES; i++) {</div><div class='add'>+		struct pipe_ctx *cur_pipe = &amp;dst_state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (cur_pipe-&gt;top_pipe)</div><div class='add'>+			cur_pipe-&gt;top_pipe =  &amp;dst_state-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;top_pipe-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+		if (cur_pipe-&gt;bottom_pipe)</div><div class='add'>+			cur_pipe-&gt;bottom_pipe = &amp;dst_state-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;bottom_pipe-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+		if (cur_pipe-&gt;prev_odm_pipe)</div><div class='add'>+			cur_pipe-&gt;prev_odm_pipe =  &amp;dst_state-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;prev_odm_pipe-&gt;pipe_idx];</div><div class='add'>+</div><div class='add'>+		if (cur_pipe-&gt;next_odm_pipe)</div><div class='add'>+			cur_pipe-&gt;next_odm_pipe = &amp;dst_state-&gt;res_ctx.pipe_ctx[cur_pipe-&gt;next_odm_pipe-&gt;pipe_idx];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* retain phantoms */</div><div class='add'>+	for (i = 0; i &lt; dst_state-&gt;phantom_stream_count; i++)</div><div class='add'>+		dc_stream_retain(dst_state-&gt;phantom_streams[i]);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dst_state-&gt;phantom_plane_count; i++)</div><div class='add'>+		dc_plane_state_retain(dst_state-&gt;phantom_planes[i]);</div><div class='add'>+</div><div class='add'>+	/* retain streams and planes */</div><div class='add'>+	for (i = 0; i &lt; dst_state-&gt;stream_count; i++) {</div><div class='add'>+		dc_stream_retain(dst_state-&gt;streams[i]);</div><div class='add'>+		for (j = 0; j &lt; dst_state-&gt;stream_status[i].plane_count; j++)</div><div class='add'>+			dc_plane_state_retain(</div><div class='add'>+					dst_state-&gt;stream_status[i].plane_states[j]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_state(struct dc *dc, struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	/* Each context must have their own instance of VBA and in order to</div><div class='add'>+	 * initialize and obtain IP and SOC the base DML instance from DC is</div><div class='add'>+	 * initially copied into every context</div><div class='add'>+	 */</div><div class='add'>+	memcpy(&amp;state-&gt;bw_ctx.dml, &amp;dc-&gt;dml, sizeof(struct display_mode_lib));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Public dc_state functions */</div><div class='add'>+struct dc_state *dc_state_create(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *state = kvzalloc(sizeof(struct dc_state),</div><div class='add'>+			GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!state)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	init_state(dc, state);</div><div class='add'>+	dc_state_construct(dc, state);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	if (dc-&gt;debug.using_dml2)</div><div class='add'>+		dml2_create(dc, &amp;dc-&gt;dml2_options, &amp;state-&gt;bw_ctx.dml2);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	kref_init(&amp;state-&gt;refcount);</div><div class='add'>+</div><div class='add'>+	return state;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state)</div><div class='add'>+{</div><div class='add'>+	struct kref refcount = dst_state-&gt;refcount;</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	struct dml2_context *dst_dml2 = dst_state-&gt;bw_ctx.dml2;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	dc_state_copy_internal(dst_state, src_state);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	dst_state-&gt;bw_ctx.dml2 = dst_dml2;</div><div class='add'>+	if (src_state-&gt;bw_ctx.dml2)</div><div class='add'>+		dml2_copy(dst_state-&gt;bw_ctx.dml2, src_state-&gt;bw_ctx.dml2);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	/* context refcount should not be overridden */</div><div class='add'>+	dst_state-&gt;refcount = refcount;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_state *dc_state_create_copy(struct dc_state *src_state)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *new_state;</div><div class='add'>+</div><div class='add'>+	new_state = kvmalloc(sizeof(struct dc_state),</div><div class='add'>+			GFP_KERNEL);</div><div class='add'>+	if (!new_state)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dc_state_copy_internal(new_state, src_state);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	if (src_state-&gt;bw_ctx.dml2 &amp;&amp;</div><div class='add'>+			!dml2_create_copy(&amp;new_state-&gt;bw_ctx.dml2, src_state-&gt;bw_ctx.dml2)) {</div><div class='add'>+		dc_state_release(new_state);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	kref_init(&amp;new_state-&gt;refcount);</div><div class='add'>+</div><div class='add'>+	return new_state;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state)</div><div class='add'>+{</div><div class='add'>+	dc_state_copy(dst_state, dc-&gt;current_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_state *dc_state_create_current_copy(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	return dc_state_create_copy(dc-&gt;current_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_construct(struct dc *dc, struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	state-&gt;clk_mgr = dc-&gt;clk_mgr;</div><div class='add'>+</div><div class='add'>+	/* Initialise DIG link encoder resource tracking variables. */</div><div class='add'>+	if (dc-&gt;res_pool)</div><div class='add'>+		link_enc_cfg_init(dc, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_destruct(struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		for (j = 0; j &lt; state-&gt;stream_status[i].plane_count; j++)</div><div class='add'>+			dc_plane_state_release(</div><div class='add'>+					state-&gt;stream_status[i].plane_states[j]);</div><div class='add'>+</div><div class='add'>+		state-&gt;stream_status[i].plane_count = 0;</div><div class='add'>+		dc_stream_release(state-&gt;streams[i]);</div><div class='add'>+		state-&gt;streams[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+	state-&gt;stream_count = 0;</div><div class='add'>+</div><div class='add'>+	/* release tracked phantoms */</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_stream_count; i++) {</div><div class='add'>+		dc_stream_release(state-&gt;phantom_streams[i]);</div><div class='add'>+		state-&gt;phantom_streams[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_plane_count; i++) {</div><div class='add'>+		dc_plane_state_release(state-&gt;phantom_planes[i]);</div><div class='add'>+		state-&gt;phantom_planes[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+	state-&gt;stream_mask = 0;</div><div class='add'>+	memset(&amp;state-&gt;res_ctx, 0, sizeof(state-&gt;res_ctx));</div><div class='add'>+	memset(&amp;state-&gt;pp_display_cfg, 0, sizeof(state-&gt;pp_display_cfg));</div><div class='add'>+	memset(&amp;state-&gt;dcn_bw_vars, 0, sizeof(state-&gt;dcn_bw_vars));</div><div class='add'>+	state-&gt;clk_mgr = NULL;</div><div class='add'>+	memset(&amp;state-&gt;bw_ctx.bw, 0, sizeof(state-&gt;bw_ctx.bw));</div><div class='add'>+	memset(state-&gt;block_sequence, 0, sizeof(state-&gt;block_sequence));</div><div class='add'>+	state-&gt;block_sequence_steps = 0;</div><div class='add'>+	memset(state-&gt;dc_dmub_cmd, 0, sizeof(state-&gt;dc_dmub_cmd));</div><div class='add'>+	state-&gt;dmub_cmd_count = 0;</div><div class='add'>+	memset(&amp;state-&gt;perf_params, 0, sizeof(state-&gt;perf_params));</div><div class='add'>+	memset(&amp;state-&gt;scratch, 0, sizeof(state-&gt;scratch));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_retain(struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;state-&gt;refcount);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dc_state_free(struct kref *kref)</div><div class='add'>+{</div><div class='add'>+	struct dc_state *state = container_of(kref, struct dc_state, refcount);</div><div class='add'>+</div><div class='add'>+	dc_state_destruct(state);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+	dml2_destroy(state-&gt;bw_ctx.dml2);</div><div class='add'>+	state-&gt;bw_ctx.dml2 = 0;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	kvfree(state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_release(struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;state-&gt;refcount, dc_state_free);</div><div class='add'>+}</div><div class='add'>+/*</div><div class='add'>+ * dc_state_add_stream() - Add a new dc_stream_state to a dc_state.</div><div class='add'>+ */</div><div class='add'>+enum dc_status dc_state_add_stream(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	enum dc_status res;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (state-&gt;stream_count &gt;= dc-&gt;res_pool-&gt;timing_generator_count) {</div><div class='add'>+		DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;streams[state-&gt;stream_count] = stream;</div><div class='add'>+	dc_stream_retain(stream);</div><div class='add'>+	state-&gt;stream_count++;</div><div class='add'>+</div><div class='add'>+	res = resource_add_otg_master_for_stream_output(</div><div class='add'>+			state, dc-&gt;res_pool, stream);</div><div class='add'>+	if (res != DC_OK)</div><div class='add'>+		DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * dc_state_remove_stream() - Remove a stream from a dc_state.</div><div class='add'>+ */</div><div class='add'>+enum dc_status dc_state_remove_stream(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(</div><div class='add'>+			&amp;state-&gt;res_ctx, stream);</div><div class='add'>+</div><div class='add'>+	if (!del_pipe) {</div><div class='add'>+		dm_error("Pipe not found for stream %p !\n", stream);</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	resource_update_pipes_for_stream_with_slice_count(state,</div><div class='add'>+			dc-&gt;current_state, dc-&gt;res_pool, stream, 1);</div><div class='add'>+	resource_remove_otg_master_for_stream_output(</div><div class='add'>+			state, dc-&gt;res_pool, stream);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] == stream)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+	if (state-&gt;streams[i] != stream) {</div><div class='add'>+		dm_error("Context doesn't have stream %p !\n", stream);</div><div class='add'>+		return DC_ERROR_UNEXPECTED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_stream_release(state-&gt;streams[i]);</div><div class='add'>+	state-&gt;stream_count--;</div><div class='add'>+</div><div class='add'>+	/* Trim back arrays */</div><div class='add'>+	for (; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		state-&gt;streams[i] = state-&gt;streams[i + 1];</div><div class='add'>+		state-&gt;stream_status[i] = state-&gt;stream_status[i + 1];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;streams[state-&gt;stream_count] = NULL;</div><div class='add'>+	memset(</div><div class='add'>+			&amp;state-&gt;stream_status[state-&gt;stream_count],</div><div class='add'>+			0,</div><div class='add'>+			sizeof(state-&gt;stream_status[0]));</div><div class='add'>+</div><div class='add'>+	return DC_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_add_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state *plane_state,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='add'>+	struct pipe_ctx *otg_master_pipe;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='add'>+	bool added = false;</div><div class='add'>+</div><div class='add'>+	stream_status = dc_state_get_stream_status(state, stream);</div><div class='add'>+	if (stream_status == NULL) {</div><div class='add'>+		dm_error("Existing stream not found; failed to attach surface!\n");</div><div class='add'>+		goto out;</div><div class='add'>+	} else if (stream_status-&gt;plane_count == MAX_SURFACE_NUM) {</div><div class='add'>+		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",</div><div class='add'>+				plane_state, MAX_SURFACE_NUM);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	otg_master_pipe = resource_get_otg_master_for_stream(</div><div class='add'>+			&amp;state-&gt;res_ctx, stream);</div><div class='add'>+	if (otg_master_pipe)</div><div class='add'>+		added = resource_append_dpp_pipes_for_plane_composition(state,</div><div class='add'>+				dc-&gt;current_state, pool, otg_master_pipe, plane_state);</div><div class='add'>+</div><div class='add'>+	if (added) {</div><div class='add'>+		stream_status-&gt;plane_states[stream_status-&gt;plane_count] =</div><div class='add'>+				plane_state;</div><div class='add'>+		stream_status-&gt;plane_count++;</div><div class='add'>+		dc_plane_state_retain(plane_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	return added;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state *plane_state,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='add'>+	struct resource_pool *pool = dc-&gt;res_pool;</div><div class='add'>+</div><div class='add'>+	if (!plane_state)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] == stream) {</div><div class='add'>+			stream_status = &amp;state-&gt;stream_status[i];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	if (stream_status == NULL) {</div><div class='add'>+		dm_error("Existing stream not found; failed to remove plane.\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	resource_remove_dpp_pipes_for_plane_composition(</div><div class='add'>+			state, pool, plane_state);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_status-&gt;plane_count; i++) {</div><div class='add'>+		if (stream_status-&gt;plane_states[i] == plane_state) {</div><div class='add'>+			dc_plane_state_release(stream_status-&gt;plane_states[i]);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i == stream_status-&gt;plane_count) {</div><div class='add'>+		dm_error("Existing plane_state not found; failed to detach it!\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	stream_status-&gt;plane_count--;</div><div class='add'>+</div><div class='add'>+	/* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */</div><div class='add'>+	for (; i &lt; stream_status-&gt;plane_count; i++)</div><div class='add'>+		stream_status-&gt;plane_states[i] = stream_status-&gt;plane_states[i + 1];</div><div class='add'>+</div><div class='add'>+	stream_status-&gt;plane_states[stream_status-&gt;plane_count] = NULL;</div><div class='add'>+</div><div class='add'>+	if (stream_status-&gt;plane_count == 0 &amp;&amp; dc-&gt;config.enable_windowed_mpo_odm)</div><div class='add'>+		/* ODM combine could prevent us from supporting more planes</div><div class='add'>+		 * we will reset ODM slice count back to 1 when all planes have</div><div class='add'>+		 * been removed to maximize the amount of planes supported when</div><div class='add'>+		 * new planes are added.</div><div class='add'>+		 */</div><div class='add'>+		resource_update_pipes_for_stream_with_slice_count(</div><div class='add'>+				state, dc-&gt;current_state, dc-&gt;res_pool, stream, 1);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_state_rem_all_planes_for_stream - Remove planes attached to the target stream.</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current dc state.</div><div class='add'>+ * @stream: Target stream, which we want to remove the attached plans.</div><div class='add'>+ * @state: context from which the planes are to be removed.</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * Return true if DC was able to remove all planes from the target</div><div class='add'>+ * stream, otherwise, return false.</div><div class='add'>+ */</div><div class='add'>+bool dc_state_rem_all_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i, old_plane_count;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='add'>+	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] == stream) {</div><div class='add'>+			stream_status = &amp;state-&gt;stream_status[i];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	if (stream_status == NULL) {</div><div class='add'>+		dm_error("Existing stream %p not found!\n", stream);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	old_plane_count = stream_status-&gt;plane_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; old_plane_count; i++)</div><div class='add'>+		del_planes[i] = stream_status-&gt;plane_states[i];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; old_plane_count; i++)</div><div class='add'>+		if (!dc_state_remove_plane(dc, stream, del_planes[i], state))</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_add_all_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state * const *plane_states,</div><div class='add'>+		int plane_count,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	bool result = true;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; plane_count; i++)</div><div class='add'>+		if (!dc_state_add_plane(dc, stream, plane_states[i], state)) {</div><div class='add'>+			result = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Private dc_state functions */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_state_get_stream_status - Get stream status from given dc state</div><div class='add'>+ * @state: DC state to find the stream status in</div><div class='add'>+ * @stream: The stream to get the stream status for</div><div class='add'>+ *</div><div class='add'>+ * The given stream is expected to exist in the given dc state. Otherwise, NULL</div><div class='add'>+ * will be returned.</div><div class='add'>+ */</div><div class='add'>+struct dc_stream_status *dc_state_get_stream_status(</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	uint8_t i;</div><div class='add'>+</div><div class='add'>+	if (state == NULL)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		if (stream == state-&gt;streams[i])</div><div class='add'>+			return &amp;state-&gt;stream_status[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum mall_stream_type dc_state_get_pipe_subvp_type(const struct dc_state *state,</div><div class='add'>+		const struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+	return dc_state_get_stream_subvp_type(state, pipe_ctx-&gt;stream);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum mall_stream_type dc_state_get_stream_subvp_type(const struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	enum mall_stream_type type = SUBVP_NONE;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		if (state-&gt;streams[i] == stream) {</div><div class='add'>+			type = state-&gt;stream_status[i].mall_stream_config.type;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return type;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_stream_state *dc_state_get_paired_subvp_stream(const struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	struct dc_stream_state *paired_stream = NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='add'>+		if (state-&gt;streams[i] == stream) {</div><div class='add'>+			paired_stream = state-&gt;stream_status[i].mall_stream_config.paired_stream;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return paired_stream;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *main_stream)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	phantom_stream = dc_create_stream_for_sink(main_stream-&gt;sink);</div><div class='add'>+</div><div class='add'>+	if (!phantom_stream) {</div><div class='add'>+		DC_LOG_ERROR("Failed to allocate phantom stream.\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* track phantom stream in dc_state */</div><div class='add'>+	dc_state_track_phantom_stream(state, phantom_stream);</div><div class='add'>+</div><div class='add'>+	phantom_stream-&gt;is_phantom = true;</div><div class='add'>+	phantom_stream-&gt;signal = SIGNAL_TYPE_VIRTUAL;</div><div class='add'>+	phantom_stream-&gt;dpms_off = true;</div><div class='add'>+</div><div class='add'>+	return phantom_stream;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_release_phantom_stream(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream)</div><div class='add'>+{</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (!dc_state_untrack_phantom_stream(state, phantom_stream)) {</div><div class='add'>+		DC_LOG_ERROR("Failed to free phantom stream %p in dc state %p.\n", phantom_stream, state);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_stream_release(phantom_stream);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dc_plane_state *dc_state_create_phantom_plane(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_plane_state *main_plane)</div><div class='add'>+{</div><div class='add'>+	struct dc_plane_state *phantom_plane = dc_create_plane_state(dc);</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (!phantom_plane) {</div><div class='add'>+		DC_LOG_ERROR("Failed to allocate phantom plane.\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* track phantom inside dc_state */</div><div class='add'>+	dc_state_track_phantom_plane(state, phantom_plane);</div><div class='add'>+</div><div class='add'>+	phantom_plane-&gt;is_phantom = true;</div><div class='add'>+</div><div class='add'>+	return phantom_plane;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_release_phantom_plane(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_plane_state *phantom_plane)</div><div class='add'>+{</div><div class='add'>+	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (!dc_state_untrack_phantom_plane(state, phantom_plane)) {</div><div class='add'>+		DC_LOG_ERROR("Failed to free phantom plane %p in dc state %p.\n", phantom_plane, state);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_plane_state_release(phantom_plane);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* add phantom streams to context and generate correct meta inside dc_state */</div><div class='add'>+enum dc_status dc_state_add_phantom_stream(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_stream_state *main_stream)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *main_stream_status;</div><div class='add'>+	struct dc_stream_status *phantom_stream_status;</div><div class='add'>+	enum dc_status res = dc_state_add_stream(dc, state, phantom_stream);</div><div class='add'>+</div><div class='add'>+	/* check if stream is tracked */</div><div class='add'>+	if (res == DC_OK &amp;&amp; !dc_state_is_phantom_stream_tracked(state, phantom_stream)) {</div><div class='add'>+		/* stream must be tracked if added to state */</div><div class='add'>+		dc_state_track_phantom_stream(state, phantom_stream);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* setup subvp meta */</div><div class='add'>+	main_stream_status = dc_state_get_stream_status(state, main_stream);</div><div class='add'>+	phantom_stream_status = dc_state_get_stream_status(state, phantom_stream);</div><div class='add'>+	phantom_stream_status-&gt;mall_stream_config.type = SUBVP_PHANTOM;</div><div class='add'>+	phantom_stream_status-&gt;mall_stream_config.paired_stream = main_stream;</div><div class='add'>+	main_stream_status-&gt;mall_stream_config.type = SUBVP_MAIN;</div><div class='add'>+	main_stream_status-&gt;mall_stream_config.paired_stream = phantom_stream;</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum dc_status dc_state_remove_phantom_stream(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream)</div><div class='add'>+{</div><div class='add'>+	struct dc_stream_status *main_stream_status;</div><div class='add'>+	struct dc_stream_status *phantom_stream_status;</div><div class='add'>+</div><div class='add'>+	/* reset subvp meta */</div><div class='add'>+	phantom_stream_status = dc_state_get_stream_status(state, phantom_stream);</div><div class='add'>+	main_stream_status = dc_state_get_stream_status(state, phantom_stream_status-&gt;mall_stream_config.paired_stream);</div><div class='add'>+	phantom_stream_status-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='add'>+	phantom_stream_status-&gt;mall_stream_config.paired_stream = NULL;</div><div class='add'>+	if (main_stream_status) {</div><div class='add'>+		main_stream_status-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='add'>+		main_stream_status-&gt;mall_stream_config.paired_stream = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* remove stream from state */</div><div class='add'>+	return dc_state_remove_stream(dc, state, phantom_stream);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_add_phantom_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state *phantom_plane,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	bool res = dc_state_add_plane(dc, phantom_stream, phantom_plane, state);</div><div class='add'>+</div><div class='add'>+	/* check if stream is tracked */</div><div class='add'>+	if (res &amp;&amp; !dc_state_is_phantom_plane_tracked(state, phantom_plane)) {</div><div class='add'>+		/* stream must be tracked if added to state */</div><div class='add'>+		dc_state_track_phantom_plane(state, phantom_plane);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return res;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_phantom_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state *phantom_plane,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	return dc_state_remove_plane(dc, phantom_stream, phantom_plane, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_rem_all_phantom_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool should_release_planes)</div><div class='add'>+{</div><div class='add'>+	int i, old_plane_count;</div><div class='add'>+	struct dc_stream_status *stream_status = NULL;</div><div class='add'>+	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;stream_count; i++)</div><div class='add'>+		if (state-&gt;streams[i] == phantom_stream) {</div><div class='add'>+			stream_status = &amp;state-&gt;stream_status[i];</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	if (stream_status == NULL) {</div><div class='add'>+		dm_error("Existing stream %p not found!\n", phantom_stream);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	old_plane_count = stream_status-&gt;plane_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; old_plane_count; i++)</div><div class='add'>+		del_planes[i] = stream_status-&gt;plane_states[i];</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; old_plane_count; i++) {</div><div class='add'>+		if (!dc_state_remove_plane(dc, phantom_stream, del_planes[i], state))</div><div class='add'>+			return false;</div><div class='add'>+		if (should_release_planes)</div><div class='add'>+			dc_state_release_phantom_plane(dc, state, del_planes[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_add_all_phantom_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state * const *phantom_planes,</div><div class='add'>+		int plane_count,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	return dc_state_add_all_planes_for_stream(dc, phantom_stream, phantom_planes, plane_count, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_phantom_streams_and_planes(</div><div class='add'>+	struct dc *dc,</div><div class='add'>+	struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+	bool removed_phantom = false;</div><div class='add'>+	struct dc_stream_state *phantom_stream = NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		struct pipe_ctx *pipe = &amp;state-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+			phantom_stream = pipe-&gt;stream;</div><div class='add'>+</div><div class='add'>+			dc_state_rem_all_phantom_planes_for_stream(dc, phantom_stream, state, false);</div><div class='add'>+			dc_state_remove_phantom_stream(dc, state, phantom_stream);</div><div class='add'>+			removed_phantom = true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return removed_phantom;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_state_release_phantom_streams_and_planes(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_stream_count; i++)</div><div class='add'>+		dc_state_release_phantom_stream(dc, state, state-&gt;phantom_streams[i]);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; state-&gt;phantom_plane_count; i++)</div><div class='add'>+		dc_state_release_phantom_plane(dc, state, state-&gt;phantom_planes[i]);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c<br/>index 4bdf105d1d71..54670e0b1518 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_stream.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_stream.c</a></div><div class='hunk'>@@ -31,6 +31,8 @@</div><div class='ctx'> #include "ipp.h"</div><div class='ctx'> #include "timing_generator.h"</div><div class='ctx'> #include "dc_dmub_srv.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+#include "dc_stream_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER dc-&gt;ctx-&gt;logger</div><div class='ctx'> </div><div class='hunk'>@@ -54,7 +56,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='add'>+bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='ctx'> 	struct dc_sink *dc_sink_data)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t i = 0;</div><div class='hunk'>@@ -121,13 +123,12 @@ static bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='ctx'> 	}</div><div class='ctx'> 	stream-&gt;out_transfer_func-&gt;type = TF_TYPE_BYPASS;</div><div class='ctx'> </div><div class='del'>-	stream-&gt;stream_id = stream-&gt;ctx-&gt;dc_stream_id_count;</div><div class='del'>-	stream-&gt;ctx-&gt;dc_stream_id_count++;</div><div class='add'>+	dc_stream_assign_stream_id(stream);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dc_stream_destruct(struct dc_stream_state *stream)</div><div class='add'>+void dc_stream_destruct(struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	dc_sink_release(stream-&gt;sink);</div><div class='ctx'> 	if (stream-&gt;out_transfer_func != NULL) {</div><div class='hunk'>@@ -136,6 +137,13 @@ static void dc_stream_destruct(struct dc_stream_state *stream)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_stream_assign_stream_id(struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	/* MSB is reserved to indicate phantoms */</div><div class='add'>+	stream-&gt;stream_id = stream-&gt;ctx-&gt;dc_stream_id_count;</div><div class='add'>+	stream-&gt;ctx-&gt;dc_stream_id_count++;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dc_stream_retain(struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	kref_get(&amp;stream-&gt;refcount);</div><div class='hunk'>@@ -196,8 +204,7 @@ struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)</div><div class='ctx'> 	if (new_stream-&gt;out_transfer_func)</div><div class='ctx'> 		dc_transfer_func_retain(new_stream-&gt;out_transfer_func);</div><div class='ctx'> </div><div class='del'>-	new_stream-&gt;stream_id = new_stream-&gt;ctx-&gt;dc_stream_id_count;</div><div class='del'>-	new_stream-&gt;ctx-&gt;dc_stream_id_count++;</div><div class='add'>+	dc_stream_assign_stream_id(new_stream);</div><div class='ctx'> </div><div class='ctx'> 	/* If using dynamic encoder assignment, wait till stream committed to assign encoder. */</div><div class='ctx'> 	if (new_stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;funcs-&gt;link_encs_assign)</div><div class='hunk'>@@ -209,31 +216,6 @@ struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dc_stream_get_status_from_state - Get stream status from given dc state</div><div class='del'>- * @state: DC state to find the stream status in</div><div class='del'>- * @stream: The stream to get the stream status for</div><div class='del'>- *</div><div class='del'>- * The given stream is expected to exist in the given dc state. Otherwise, NULL</div><div class='del'>- * will be returned.</div><div class='del'>- */</div><div class='del'>-struct dc_stream_status *dc_stream_get_status_from_state(</div><div class='del'>-	struct dc_state *state,</div><div class='del'>-	struct dc_stream_state *stream)</div><div class='del'>-{</div><div class='del'>-	uint8_t i;</div><div class='del'>-</div><div class='del'>-	if (state == NULL)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; state-&gt;stream_count; i++) {</div><div class='del'>-		if (stream == state-&gt;streams[i])</div><div class='del'>-			return &amp;state-&gt;stream_status[i];</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * dc_stream_get_status() - Get current stream status of the given stream state</div><div class='ctx'>  * @stream: The stream to get the stream status for.</div><div class='ctx'>  *</div><div class='hunk'>@@ -244,7 +226,7 @@ struct dc_stream_status *dc_stream_get_status(</div><div class='ctx'> 	struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = stream-&gt;ctx-&gt;dc;</div><div class='del'>-	return dc_stream_get_status_from_state(dc-&gt;current_state, stream);</div><div class='add'>+	return dc_state_get_stream_status(dc-&gt;current_state, stream);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void program_cursor_attributes(</div><div class='hunk'>@@ -465,16 +447,37 @@ bool dc_stream_add_writeback(struct dc *dc,</div><div class='ctx'> 	if (dc-&gt;hwss.enable_writeback) {</div><div class='ctx'> 		struct dc_stream_status *stream_status = dc_stream_get_status(stream);</div><div class='ctx'> 		struct dwbc *dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='del'>-		dwb-&gt;otg_inst = stream_status-&gt;primary_otg_inst;</div><div class='add'>+		if (stream_status)</div><div class='add'>+			dwb-&gt;otg_inst = stream_status-&gt;primary_otg_inst;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (!dc-&gt;hwss.update_bandwidth(dc, dc-&gt;current_state)) {</div><div class='add'>+		dm_error("DC: update_bandwidth failed!\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* enable writeback */</div><div class='add'>+	if (dc-&gt;hwss.enable_writeback) {</div><div class='add'>+		struct dwbc *dwb = dc-&gt;res_pool-&gt;dwbc[wb_info-&gt;dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+		if (dwb-&gt;funcs-&gt;is_enabled(dwb)) {</div><div class='add'>+			/* writeback pipe already enabled, only need to update */</div><div class='add'>+			dc-&gt;hwss.update_writeback(dc, wb_info, dc-&gt;current_state);</div><div class='add'>+		} else {</div><div class='add'>+			/* Enable writeback pipe from scratch*/</div><div class='add'>+			dc-&gt;hwss.enable_writeback(dc, wb_info, dc-&gt;current_state);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dc_stream_remove_writeback(struct dc *dc,</div><div class='add'>+bool dc_stream_fc_disable_writeback(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		uint32_t dwb_pipe_inst)</div><div class='ctx'> {</div><div class='del'>-	int i = 0, j = 0;</div><div class='add'>+	struct dwbc *dwb = dc-&gt;res_pool-&gt;dwbc[dwb_pipe_inst];</div><div class='add'>+</div><div class='ctx'> 	if (stream == NULL) {</div><div class='ctx'> 		dm_error("DC: dc_stream is NULL!\n");</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -490,27 +493,63 @@ bool dc_stream_remove_writeback(struct dc *dc,</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-//	stream-&gt;writeback_info[dwb_pipe_inst].wb_enabled = false;</div><div class='del'>-	for (i = 0; i &lt; stream-&gt;num_wb_info; i++) {</div><div class='del'>-		/*dynamic update*/</div><div class='del'>-		if (stream-&gt;writeback_info[i].wb_enabled &amp;&amp;</div><div class='del'>-			stream-&gt;writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {</div><div class='del'>-			stream-&gt;writeback_info[i].wb_enabled = false;</div><div class='del'>-		}</div><div class='add'>+	if (dwb-&gt;funcs-&gt;set_fc_enable)</div><div class='add'>+		dwb-&gt;funcs-&gt;set_fc_enable(dwb, DWB_FRAME_CAPTURE_DISABLE);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_stream_remove_writeback(struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		uint32_t dwb_pipe_inst)</div><div class='add'>+{</div><div class='add'>+	int i = 0, j = 0;</div><div class='add'>+	if (stream == NULL) {</div><div class='add'>+		dm_error("DC: dc_stream is NULL!\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dwb_pipe_inst &gt;= MAX_DWB_PIPES) {</div><div class='add'>+		dm_error("DC: writeback pipe is invalid!\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;num_wb_info &gt; MAX_DWB_PIPES) {</div><div class='add'>+		dm_error("DC: num_wb_info is invalid!\n");</div><div class='add'>+		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* remove writeback info for disabled writeback pipes from stream */</div><div class='ctx'> 	for (i = 0, j = 0; i &lt; stream-&gt;num_wb_info; i++) {</div><div class='ctx'> 		if (stream-&gt;writeback_info[i].wb_enabled) {</div><div class='del'>-			if (j &lt; i)</div><div class='del'>-				/* trim the array */</div><div class='add'>+</div><div class='add'>+			if (stream-&gt;writeback_info[i].dwb_pipe_inst == dwb_pipe_inst)</div><div class='add'>+				stream-&gt;writeback_info[i].wb_enabled = false;</div><div class='add'>+</div><div class='add'>+			/* trim the array */</div><div class='add'>+			if (j &lt; i) {</div><div class='ctx'> 				memcpy(&amp;stream-&gt;writeback_info[j], &amp;stream-&gt;writeback_info[i],</div><div class='ctx'> 						sizeof(struct dc_writeback_info));</div><div class='del'>-			j++;</div><div class='add'>+				j++;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	stream-&gt;num_wb_info = j;</div><div class='ctx'> </div><div class='add'>+	/* recalculate and apply DML parameters */</div><div class='add'>+	if (!dc-&gt;hwss.update_bandwidth(dc, dc-&gt;current_state)) {</div><div class='add'>+		dm_error("DC: update_bandwidth failed!\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* disable writeback */</div><div class='add'>+	if (dc-&gt;hwss.disable_writeback) {</div><div class='add'>+		struct dwbc *dwb = dc-&gt;res_pool-&gt;dwbc[dwb_pipe_inst];</div><div class='add'>+</div><div class='add'>+		if (dwb-&gt;funcs-&gt;is_enabled(dwb))</div><div class='add'>+			dc-&gt;hwss.disable_writeback(dc, dwb_pipe_inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c<br/>index a80e45300783..19a2c7140ae8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/core/dc_surface.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/core/dc_surface.c</a></div><div class='hunk'>@@ -32,10 +32,12 @@</div><div class='ctx'> #include "transform.h"</div><div class='ctx'> #include "dpp.h"</div><div class='ctx'> </div><div class='add'>+#include "dc_plane_priv.h"</div><div class='add'>+</div><div class='ctx'> /*******************************************************************************</div><div class='ctx'>  * Private functions</div><div class='ctx'>  ******************************************************************************/</div><div class='del'>-static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)</div><div class='add'>+void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='ctx'> 	plane_state-&gt;ctx = ctx;</div><div class='ctx'> </div><div class='hunk'>@@ -63,7 +65,7 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dc_plane_destruct(struct dc_plane_state *plane_state)</div><div class='add'>+void dc_plane_destruct(struct dc_plane_state *plane_state)</div><div class='ctx'> {</div><div class='ctx'> 	if (plane_state-&gt;gamma_correction != NULL) {</div><div class='ctx'> 		dc_gamma_release(&amp;plane_state-&gt;gamma_correction);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h<br/>index 9316b737a8ba..5d7aa882416b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc.h</a></div><div class='hunk'>@@ -27,6 +27,8 @@</div><div class='ctx'> #define DC_INTERFACE_H_</div><div class='ctx'> </div><div class='ctx'> #include "dc_types.h"</div><div class='add'>+#include "dc_state.h"</div><div class='add'>+#include "dc_plane.h"</div><div class='ctx'> #include "grph_object_defs.h"</div><div class='ctx'> #include "logger_types.h"</div><div class='ctx'> #include "hdcp_msg_types.h"</div><div class='hunk'>@@ -49,7 +51,7 @@ struct aux_payload;</div><div class='ctx'> struct set_config_cmd_payload;</div><div class='ctx'> struct dmub_notification;</div><div class='ctx'> </div><div class='del'>-#define DC_VER "3.2.259"</div><div class='add'>+#define DC_VER "3.2.266"</div><div class='ctx'> </div><div class='ctx'> #define MAX_SURFACES 3</div><div class='ctx'> #define MAX_PLANES 6</div><div class='hunk'>@@ -461,6 +463,12 @@ enum dml_hostvm_override_opts {</div><div class='ctx'> 	DML_HOSTVM_OVERRIDE_TRUE = 0x2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dc_replay_power_opts {</div><div class='add'>+	replay_power_opt_invalid		= 0x0,</div><div class='add'>+	replay_power_opt_smu_opt_static_screen	= 0x1,</div><div class='add'>+	replay_power_opt_z10_static_screen	= 0x10,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum dcc_option {</div><div class='ctx'> 	DCC_ENABLE = 0,</div><div class='ctx'> 	DCC_DISABLE = 1,</div><div class='hunk'>@@ -874,6 +882,7 @@ struct dc_debug_options {</div><div class='ctx'> 	unsigned int seamless_boot_odm_combine;</div><div class='ctx'> 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst</div><div class='ctx'> 	int minimum_z8_residency_time;</div><div class='add'>+	int minimum_z10_residency_time;</div><div class='ctx'> 	bool disable_z9_mpc;</div><div class='ctx'> 	unsigned int force_fclk_khz;</div><div class='ctx'> 	bool enable_tri_buf;</div><div class='hunk'>@@ -955,7 +964,6 @@ struct dc_debug_options {</div><div class='ctx'> 	unsigned int min_prefetch_in_strobe_ns;</div><div class='ctx'> 	bool disable_unbounded_requesting;</div><div class='ctx'> 	bool dig_fifo_off_in_blank;</div><div class='del'>-	bool temp_mst_deallocation_sequence;</div><div class='ctx'> 	bool override_dispclk_programming;</div><div class='ctx'> 	bool otg_crc_db;</div><div class='ctx'> 	bool disallow_dispclk_dppclk_ds;</div><div class='hunk'>@@ -978,6 +986,9 @@ struct dc_debug_options {</div><div class='ctx'> 	bool psp_disabled_wa;</div><div class='ctx'> 	unsigned int ips2_eval_delay_us;</div><div class='ctx'> 	unsigned int ips2_entry_delay_us;</div><div class='add'>+	bool disable_timeout;</div><div class='add'>+	bool disable_extblankadj;</div><div class='add'>+	unsigned int static_screen_wait_frames;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct gpu_info_soc_bounding_box_v1_0;</div><div class='hunk'>@@ -1388,13 +1399,6 @@ struct dc_surface_update {</div><div class='ctx'> /*</div><div class='ctx'>  * Create a new surface with default parameters;</div><div class='ctx'>  */</div><div class='del'>-struct dc_plane_state *dc_create_plane_state(struct dc *dc);</div><div class='del'>-const struct dc_plane_status *dc_plane_get_status(</div><div class='del'>-		const struct dc_plane_state *plane_state);</div><div class='del'>-</div><div class='del'>-void dc_plane_state_retain(struct dc_plane_state *plane_state);</div><div class='del'>-void dc_plane_state_release(struct dc_plane_state *plane_state);</div><div class='del'>-</div><div class='ctx'> void dc_gamma_retain(struct dc_gamma *dc_gamma);</div><div class='ctx'> void dc_gamma_release(struct dc_gamma **dc_gamma);</div><div class='ctx'> struct dc_gamma *dc_create_gamma(void);</div><div class='hunk'>@@ -1458,37 +1462,20 @@ enum dc_status dc_validate_global_state(</div><div class='ctx'> 		struct dc_state *new_ctx,</div><div class='ctx'> 		bool fast_validate);</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-void dc_resource_state_construct(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_state *dst_ctx);</div><div class='del'>-</div><div class='ctx'> bool dc_acquire_release_mpc_3dlut(</div><div class='ctx'> 		struct dc *dc, bool acquire,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_3dlut **lut,</div><div class='ctx'> 		struct dc_transfer_func **shaper);</div><div class='ctx'> </div><div class='del'>-void dc_resource_state_copy_construct(</div><div class='del'>-		const struct dc_state *src_ctx,</div><div class='del'>-		struct dc_state *dst_ctx);</div><div class='del'>-</div><div class='del'>-void dc_resource_state_copy_construct_current(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_state *dst_ctx);</div><div class='del'>-</div><div class='del'>-void dc_resource_state_destruct(struct dc_state *context);</div><div class='del'>-</div><div class='ctx'> bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);</div><div class='add'>+void get_audio_check(struct audio_info *aud_modes,</div><div class='add'>+	struct audio_check *aud_chk);</div><div class='ctx'> </div><div class='ctx'> enum dc_status dc_commit_streams(struct dc *dc,</div><div class='ctx'> 				 struct dc_stream_state *streams[],</div><div class='ctx'> 				 uint8_t stream_count);</div><div class='ctx'> </div><div class='del'>-struct dc_state *dc_create_state(struct dc *dc);</div><div class='del'>-struct dc_state *dc_copy_state(struct dc_state *src_ctx);</div><div class='del'>-void dc_retain_state(struct dc_state *context);</div><div class='del'>-void dc_release_state(struct dc_state *context);</div><div class='ctx'> </div><div class='ctx'> struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='hunk'>@@ -1540,7 +1527,13 @@ struct dc_link {</div><div class='ctx'> 	bool is_dig_mapping_flexible;</div><div class='ctx'> 	bool hpd_status; /* HPD status of link without physical HPD pin. */</div><div class='ctx'> 	bool is_hpd_pending; /* Indicates a new received hpd */</div><div class='del'>-	bool is_automated; /* Indicates automated testing */</div><div class='add'>+</div><div class='add'>+	/* USB4 DPIA links skip verifying link cap, instead performing the fallback method</div><div class='add'>+	 * for every link training. This is incompatible with DP LL compliance automation,</div><div class='add'>+	 * which expects the same link settings to be used every retry on a link loss.</div><div class='add'>+	 * This flag is used to skip the fallback when link loss occurs during automation.</div><div class='add'>+	 */</div><div class='add'>+	bool skip_fallback_on_link_loss;</div><div class='ctx'> </div><div class='ctx'> 	bool edp_sink_present;</div><div class='ctx'> </div><div class='hunk'>@@ -1608,7 +1601,6 @@ struct dc_link {</div><div class='ctx'> 	enum edp_revision edp_revision;</div><div class='ctx'> 	union dpcd_sink_ext_caps dpcd_sink_ext_caps;</div><div class='ctx'> </div><div class='del'>-	struct backlight_settings backlight_settings;</div><div class='ctx'> 	struct psr_settings psr_settings;</div><div class='ctx'> </div><div class='ctx'> 	struct replay_settings replay_settings;</div><div class='hunk'>@@ -2092,6 +2084,20 @@ bool dc_link_setup_psr(struct dc_link *dc_link,</div><div class='ctx'> 		const struct dc_stream_state *stream, struct psr_config *psr_config,</div><div class='ctx'> 		struct psr_context *psr_context);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Communicate with DMUB to allow or disallow Panel Replay on the specified link:</div><div class='add'>+ *</div><div class='add'>+ * @link: pointer to the dc_link struct instance</div><div class='add'>+ * @enable: enable(active) or disable(inactive) replay</div><div class='add'>+ * @wait: state transition need to wait the active set completed.</div><div class='add'>+ * @force_static: force disable(inactive) the replay</div><div class='add'>+ * @power_opts: set power optimazation parameters to DMUB.</div><div class='add'>+ *</div><div class='add'>+ * return: allow Replay active will return true, else will return false.</div><div class='add'>+ */</div><div class='add'>+bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,</div><div class='add'>+		bool wait, bool force_static, const unsigned int *power_opts);</div><div class='add'>+</div><div class='ctx'> bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);</div><div class='ctx'> </div><div class='ctx'> /* On eDP links this function call will stall until T12 has elapsed.</div><div class='hunk'>@@ -2187,11 +2193,11 @@ int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: pointer to dc struct</div><div class='ctx'>  * @stream: pointer to all possible streams</div><div class='del'>- * @num_streams: number of valid DPIA streams</div><div class='add'>+ * @count: number of valid DPIA streams</div><div class='ctx'>  *</div><div class='ctx'>  * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE</div><div class='ctx'>  */</div><div class='del'>-bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams,</div><div class='add'>+bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,</div><div class='ctx'> 		const unsigned int count);</div><div class='ctx'> </div><div class='ctx'> /* Sink Interfaces - A sink corresponds to a display output device */</div><div class='hunk'>@@ -2336,6 +2342,9 @@ void dc_hardware_release(struct dc *dc);</div><div class='ctx'> void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);</div><div class='ctx'> </div><div class='ctx'> bool dc_set_psr_allow_active(struct dc *dc, bool enable);</div><div class='add'>+</div><div class='add'>+bool dc_set_replay_allow_active(struct dc *dc, bool active);</div><div class='add'>+</div><div class='ctx'> void dc_z10_restore(const struct dc *dc);</div><div class='ctx'> void dc_z10_save_init(struct dc *dc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h<br/>index be9aa1a71847..26940d94d8fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_bios_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_bios_types.h</a></div><div class='hunk'>@@ -140,7 +140,7 @@ struct dc_vbios_funcs {</div><div class='ctx'> 	enum bp_result (*enable_lvtma_control)(</div><div class='ctx'> 		struct dc_bios *bios,</div><div class='ctx'> 		uint8_t uc_pwr_on,</div><div class='del'>-		uint8_t panel_instance,</div><div class='add'>+		uint8_t pwrseq_instance,</div><div class='ctx'> 		uint8_t bypass_panel_control_wait);</div><div class='ctx'> </div><div class='ctx'> 	enum bp_result (*get_soc_bb_info)(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c<br/>index 0e07699c1e83..2b79a0e5638e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #include "cursor_reg_cache.h"</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define CTX dc_dmub_srv-&gt;ctx</div><div class='ctx'> #define DC_LOGGER CTX-&gt;logger</div><div class='hunk'>@@ -140,7 +141,10 @@ bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> </div><div class='ctx'> 		if (status == DMUB_STATUS_QUEUE_FULL) {</div><div class='ctx'> 			/* Execute and wait for queue to become empty again. */</div><div class='del'>-			dmub_srv_cmd_execute(dmub);</div><div class='add'>+			status = dmub_srv_cmd_execute(dmub);</div><div class='add'>+			if (status == DMUB_STATUS_POWER_STATE_D3)</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='ctx'> 			dmub_srv_wait_for_idle(dmub, 100000);</div><div class='ctx'> </div><div class='ctx'> 			/* Requeue the command. */</div><div class='hunk'>@@ -148,16 +152,20 @@ bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='del'>-			DC_ERROR("Error queueing DMUB command: status=%d\n", status);</div><div class='del'>-			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+			if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='add'>+				DC_ERROR("Error queueing DMUB command: status=%d\n", status);</div><div class='add'>+				dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+			}</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = dmub_srv_cmd_execute(dmub);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='del'>-		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+		if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='add'>+			DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='add'>+			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+		}</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -218,7 +226,10 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int coun</div><div class='ctx'> </div><div class='ctx'> 		if (status == DMUB_STATUS_QUEUE_FULL) {</div><div class='ctx'> 			/* Execute and wait for queue to become empty again. */</div><div class='del'>-			dmub_srv_cmd_execute(dmub);</div><div class='add'>+			status = dmub_srv_cmd_execute(dmub);</div><div class='add'>+			if (status == DMUB_STATUS_POWER_STATE_D3)</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='ctx'> 			dmub_srv_wait_for_idle(dmub, 100000);</div><div class='ctx'> </div><div class='ctx'> 			/* Requeue the command. */</div><div class='hunk'>@@ -226,22 +237,31 @@ bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int coun</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='del'>-			DC_ERROR("Error queueing DMUB command: status=%d\n", status);</div><div class='del'>-			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+			if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='add'>+				DC_ERROR("Error queueing DMUB command: status=%d\n", status);</div><div class='add'>+				dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+			}</div><div class='ctx'> 			return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = dmub_srv_cmd_execute(dmub);</div><div class='ctx'> 	if (status != DMUB_STATUS_OK) {</div><div class='del'>-		DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='del'>-		dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+		if (status != DMUB_STATUS_POWER_STATE_D3) {</div><div class='add'>+			DC_ERROR("Error starting DMUB execution: status=%d\n", status);</div><div class='add'>+			dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);</div><div class='add'>+		}</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// Wait for DMUB to process command</div><div class='ctx'> 	if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) {</div><div class='del'>-		status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+		if (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout) {</div><div class='add'>+			do {</div><div class='add'>+				status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='add'>+			} while (status != DMUB_STATUS_OK);</div><div class='add'>+		} else</div><div class='add'>+			status = dmub_srv_wait_for_idle(dmub, 100000);</div><div class='ctx'> </div><div class='ctx'> 		if (status != DMUB_STATUS_OK) {</div><div class='ctx'> 			DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status);</div><div class='hunk'>@@ -282,17 +302,11 @@ bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,</div><div class='ctx'> 				    unsigned int stream_mask)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *dmub;</div><div class='del'>-	const uint32_t timeout = 30;</div><div class='del'>-</div><div class='ctx'> 	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	dmub = dc_dmub_srv-&gt;dmub;</div><div class='del'>-</div><div class='del'>-	return dmub_srv_send_gpint_command(</div><div class='del'>-		       dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,</div><div class='del'>-		       stream_mask, timeout) == DMUB_STATUS_OK;</div><div class='add'>+	return dc_wake_and_execute_gpint(dc_dmub_srv-&gt;ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,</div><div class='add'>+					 stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)</div><div class='hunk'>@@ -341,7 +355,7 @@ void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal</div><div class='ctx'> 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);</div><div class='ctx'> </div><div class='ctx'> 	// Send the command to the DMCUB.</div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)</div><div class='hunk'>@@ -355,7 +369,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)</div><div class='ctx'> 	cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header);</div><div class='ctx'> </div><div class='ctx'> 	// Send the command to the DMCUB.</div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)</div><div class='hunk'>@@ -448,7 +462,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru</div><div class='ctx'> 		sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header);</div><div class='ctx'> </div><div class='ctx'> 	// Send the command to the DMCUB.</div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -469,7 +483,7 @@ void dc_dmub_srv_query_caps_cmd(struct dc_dmub_srv *dc_dmub_srv)</div><div class='ctx'> 	cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data);</div><div class='ctx'> </div><div class='ctx'> 	/* If command was processed, copy feature caps to dmub srv */</div><div class='del'>-	if (dm_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='add'>+	if (dc_wake_and_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='ctx'> 	    cmd.query_feature_caps.header.ret_status == 0) {</div><div class='ctx'> 		memcpy(&amp;dc_dmub_srv-&gt;dmub-&gt;feature_caps,</div><div class='ctx'> 		       &amp;cmd.query_feature_caps.query_feature_caps_data,</div><div class='hunk'>@@ -494,7 +508,7 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi</div><div class='ctx'> 	cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;</div><div class='ctx'> </div><div class='ctx'> 	// If command was processed, copy feature caps to dmub srv</div><div class='del'>-	if (dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='add'>+	if (dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='ctx'> 		cmd.visual_confirm_color.header.ret_status == 0) {</div><div class='ctx'> 		memcpy(&amp;dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;visual_confirm_color,</div><div class='ctx'> 			&amp;cmd.visual_confirm_color.visual_confirm_color_data,</div><div class='hunk'>@@ -505,10 +519,11 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi</div><div class='ctx'> /**</div><div class='ctx'>  * populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command</div><div class='ctx'>  *</div><div class='del'>- * @dc: [in] current dc state</div><div class='add'>+ * @dc: [in] pointer to dc object</div><div class='ctx'>  * @subvp_pipe: [in] pipe_ctx for the SubVP pipe</div><div class='ctx'>  * @vblank_pipe: [in] pipe_ctx for the DRR pipe</div><div class='ctx'>  * @pipe_data: [in] Pipe data which stores the VBLANK/DRR info</div><div class='add'>+ * @context: [in] DC state for access to phantom stream</div><div class='ctx'>  *</div><div class='ctx'>  * Populate the DMCUB SubVP command with DRR pipe info. All the information</div><div class='ctx'>  * required for calculating the SubVP + DRR microschedule is populated here.</div><div class='hunk'>@@ -519,12 +534,14 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi</div><div class='ctx'>  * 3. Populate the drr_info with the min and max supported vtotal values</div><div class='ctx'>  */</div><div class='ctx'> static void populate_subvp_cmd_drr_info(struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *subvp_pipe,</div><div class='ctx'> 		struct pipe_ctx *vblank_pipe,</div><div class='ctx'> 		struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data)</div><div class='ctx'> {</div><div class='add'>+	struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing = &amp;subvp_pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 	struct dc_crtc_timing *drr_timing = &amp;vblank_pipe-&gt;stream-&gt;timing;</div><div class='ctx'> 	uint16_t drr_frame_us = 0;</div><div class='ctx'> 	uint16_t min_drr_supported_us = 0;</div><div class='hunk'>@@ -612,7 +629,7 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		// Find the SubVP pipe</div><div class='del'>-		if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -629,7 +646,7 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	if (vblank_pipe-&gt;stream-&gt;ignore_msa_timing_param &amp;&amp;</div><div class='ctx'> 		(vblank_pipe-&gt;stream-&gt;allow_freesync || vblank_pipe-&gt;stream-&gt;vrr_active_variable || vblank_pipe-&gt;stream-&gt;vrr_active_fixed))</div><div class='del'>-		populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);</div><div class='add'>+		populate_subvp_cmd_drr_info(dc, context, pipe, vblank_pipe, pipe_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -654,10 +671,17 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,</div><div class='ctx'> 	uint32_t subvp0_prefetch_us = 0;</div><div class='ctx'> 	uint32_t subvp1_prefetch_us = 0;</div><div class='ctx'> 	uint32_t prefetch_delta_us = 0;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing0 = &amp;subvp_pipes[0]-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing1 = &amp;subvp_pipes[1]-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+	struct dc_stream_state *phantom_stream0 = NULL;</div><div class='add'>+	struct dc_stream_state *phantom_stream1 = NULL;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing0 = NULL;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing1 = NULL;</div><div class='ctx'> 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;</div><div class='ctx'> </div><div class='add'>+	phantom_stream0 = dc_state_get_paired_subvp_stream(context, subvp_pipes[0]-&gt;stream);</div><div class='add'>+	phantom_stream1 = dc_state_get_paired_subvp_stream(context, subvp_pipes[1]-&gt;stream);</div><div class='add'>+	phantom_timing0 = &amp;phantom_stream0-&gt;timing;</div><div class='add'>+	phantom_timing1 = &amp;phantom_stream1-&gt;timing;</div><div class='add'>+</div><div class='ctx'> 	subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0-&gt;v_total - phantom_timing0-&gt;v_front_porch) *</div><div class='ctx'> 			(uint64_t)phantom_timing0-&gt;h_total * 1000000),</div><div class='ctx'> 			(((uint64_t)phantom_timing0-&gt;pix_clk_100hz * 100) + dc-&gt;caps.subvp_prefetch_end_to_mall_start_us));</div><div class='hunk'>@@ -707,8 +731,9 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,</div><div class='ctx'> 	uint32_t j;</div><div class='ctx'> 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data =</div><div class='ctx'> 			&amp;cmd-&gt;fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index];</div><div class='add'>+	struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-	struct dc_crtc_timing *phantom_timing = &amp;subvp_pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+	struct dc_crtc_timing *phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 	uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den;</div><div class='ctx'> </div><div class='ctx'> 	pipe_data-&gt;mode = SUBVP;</div><div class='hunk'>@@ -762,7 +787,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,</div><div class='ctx'> 	for (j = 0; j &lt; dc-&gt;res_pool-&gt;pipe_count; j++) {</div><div class='ctx'> 		struct pipe_ctx *phantom_pipe = &amp;context-&gt;res_ctx.pipe_ctx[j];</div><div class='ctx'> </div><div class='del'>-		if (phantom_pipe-&gt;stream == subvp_pipe-&gt;stream-&gt;mall_stream_config.paired_stream) {</div><div class='add'>+		if (phantom_pipe-&gt;stream == dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream)) {</div><div class='ctx'> 			pipe_data-&gt;pipe_config.subvp_data.phantom_pipe_index = phantom_pipe-&gt;stream_res.tg-&gt;inst;</div><div class='ctx'> 			if (phantom_pipe-&gt;bottom_pipe) {</div><div class='ctx'> 				pipe_data-&gt;pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe-&gt;bottom_pipe-&gt;plane_res.hubp-&gt;inst;</div><div class='hunk'>@@ -796,6 +821,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct pipe_ctx *subvp_pipes[2];</div><div class='ctx'> 	uint32_t wm_val_refclk = 0;</div><div class='add'>+	enum mall_stream_type pipe_mall_type;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	// FW command for SUBVP</div><div class='hunk'>@@ -811,7 +837,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='ctx'> 				resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)</div><div class='ctx'> 			subvp_pipes[subvp_count++] = pipe;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -819,6 +845,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 		// For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd</div><div class='ctx'> 		for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+			pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 			if (!pipe-&gt;stream)</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -829,12 +856,11 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='ctx'> 					resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='del'>-					pipe-&gt;stream-&gt;mall_stream_config.paired_stream &amp;&amp;</div><div class='del'>-					pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+					pipe_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 				populate_subvp_cmd_pipe_info(dc, context, &amp;cmd, pipe, cmd_pipe_index++);</div><div class='ctx'> 			} else if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='ctx'> 					resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='del'>-					pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+					pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 				// Don't need to check for ActiveDRAMClockChangeMargin &lt; 0, not valid in cases where</div><div class='ctx'> 				// we run through DML without calculating "natural" P-state support</div><div class='ctx'> 				populate_subvp_cmd_vblank_pipe_info(dc, context, &amp;cmd, pipe, cmd_pipe_index++);</div><div class='hunk'>@@ -856,7 +882,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,</div><div class='ctx'> 		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk &lt; 0xFFFF ? wm_val_refclk : 0xFFFF;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)</div><div class='hunk'>@@ -1093,7 +1119,7 @@ void dc_send_update_cursor_info_to_dmu(</div><div class='ctx'> 				pipe_idx, pCtx-&gt;plane_res.hubp, pCtx-&gt;plane_res.dpp);</div><div class='ctx'> </div><div class='ctx'> 		/* Combine 2nd cmds update_curosr_info to DMU */</div><div class='del'>-		dm_execute_dmub_cmd_list(pCtx-&gt;stream-&gt;ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+		dc_wake_and_execute_dmub_cmd_list(pCtx-&gt;stream-&gt;ctx, 2, cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1107,25 +1133,20 @@ bool dc_dmub_check_min_version(struct dmub_srv *srv)</div><div class='ctx'> void dc_dmub_srv_enable_dpia_trace(const struct dc *dc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_dmub_srv *dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='del'>-	struct dmub_srv *dmub;</div><div class='del'>-	enum dmub_status status;</div><div class='del'>-	static const uint32_t timeout_us = 30;</div><div class='ctx'> </div><div class='ctx'> 	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub) {</div><div class='ctx'> 		DC_LOG_ERROR("%s: invalid parameters.", __func__);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dmub = dc_dmub_srv-&gt;dmub;</div><div class='del'>-</div><div class='del'>-	status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1, 0x0010, timeout_us);</div><div class='del'>-	if (status != DMUB_STATUS_OK) {</div><div class='add'>+	if (!dc_wake_and_execute_gpint(dc-&gt;ctx, DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1,</div><div class='add'>+				       0x0010, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {</div><div class='ctx'> 		DC_LOG_ERROR("timeout updating trace buffer mask word\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = dmub_srv_send_gpint_command(dmub, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK, 0x0000, timeout_us);</div><div class='del'>-	if (status != DMUB_STATUS_OK) {</div><div class='add'>+	if (!dc_wake_and_execute_gpint(dc-&gt;ctx, DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK,</div><div class='add'>+				       0x0000, NULL, DM_DMUB_WAIT_TYPE_WAIT)) {</div><div class='ctx'> 		DC_LOG_ERROR("timeout updating trace buffer mask word\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1143,14 +1164,23 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)</div><div class='ctx'> 	struct dc_context *dc_ctx = dc_dmub_srv-&gt;ctx;</div><div class='ctx'> 	enum dmub_status status;</div><div class='ctx'> </div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='ctx'> 	if (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.dmcub_emulation)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	if (wait) {</div><div class='del'>-		status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv-&gt;dmub, 500000);</div><div class='del'>-		if (status != DMUB_STATUS_OK) {</div><div class='del'>-			DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);</div><div class='del'>-			return false;</div><div class='add'>+		if (dc_dmub_srv-&gt;ctx-&gt;dc-&gt;debug.disable_timeout) {</div><div class='add'>+			do {</div><div class='add'>+				status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv-&gt;dmub, 500000);</div><div class='add'>+			} while (status != DMUB_STATUS_OK);</div><div class='add'>+		} else {</div><div class='add'>+			status = dmub_srv_wait_for_hw_pwr_up(dc_dmub_srv-&gt;dmub, 500000);</div><div class='add'>+			if (status != DMUB_STATUS_OK) {</div><div class='add'>+				DC_ERROR("Error querying DMUB hw power up status: error=%d\n", status);</div><div class='add'>+				return false;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	} else</div><div class='ctx'> 		return dmub_srv_is_hw_pwr_up(dc_dmub_srv-&gt;dmub);</div><div class='hunk'>@@ -1158,7 +1188,7 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='add'>+static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd = {0};</div><div class='ctx'> </div><div class='hunk'>@@ -1179,20 +1209,20 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)</div><div class='ctx'> 			dc-&gt;hwss.set_idle_state(dc, true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	/* NOTE: This does not use the "wake" interface since this is part of the wake path. */</div><div class='add'>+	/* We also do not perform a wait since DMCUB could enter idle after the notification. */</div><div class='add'>+	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='add'>+static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> {</div><div class='del'>-	const uint32_t max_num_polls = 10000;</div><div class='ctx'> 	uint32_t allow_state = 0;</div><div class='ctx'> 	uint32_t commit_state = 0;</div><div class='del'>-	uint32_t i;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;debug.dmcub_emulation)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!dc-&gt;idle_optimizations_allowed)</div><div class='add'>+	if (!dc-&gt;ctx-&gt;dmub_srv || !dc-&gt;ctx-&gt;dmub_srv-&gt;dmub)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.get_idle_state &amp;&amp;</div><div class='hunk'>@@ -1204,8 +1234,16 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 		if (!(allow_state &amp; DMUB_IPS2_ALLOW_MASK)) {</div><div class='ctx'> 			// Wait for evaluation time</div><div class='del'>-			udelay(dc-&gt;debug.ips2_eval_delay_us);</div><div class='del'>-			commit_state = dc-&gt;hwss.get_idle_state(dc);</div><div class='add'>+			for (;;) {</div><div class='add'>+				udelay(dc-&gt;debug.ips2_eval_delay_us);</div><div class='add'>+				commit_state = dc-&gt;hwss.get_idle_state(dc);</div><div class='add'>+				if (commit_state &amp; DMUB_IPS2_ALLOW_MASK)</div><div class='add'>+					break;</div><div class='add'>+</div><div class='add'>+				/* allow was still set, retry eval delay */</div><div class='add'>+				dc-&gt;hwss.set_idle_state(dc, false);</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			if (!(commit_state &amp; DMUB_IPS2_COMMIT_MASK)) {</div><div class='ctx'> 				// Tell PMFW to exit low power state</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;funcs-&gt;exit_low_power_state(dc-&gt;clk_mgr);</div><div class='hunk'>@@ -1214,14 +1252,13 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> 				udelay(dc-&gt;debug.ips2_entry_delay_us);</div><div class='ctx'> 				dc-&gt;clk_mgr-&gt;funcs-&gt;exit_low_power_state(dc-&gt;clk_mgr);</div><div class='ctx'> </div><div class='del'>-				for (i = 0; i &lt; max_num_polls; ++i) {</div><div class='add'>+				for (;;) {</div><div class='ctx'> 					commit_state = dc-&gt;hwss.get_idle_state(dc);</div><div class='ctx'> 					if (commit_state &amp; DMUB_IPS2_COMMIT_MASK)</div><div class='ctx'> 						break;</div><div class='ctx'> </div><div class='ctx'> 					udelay(1);</div><div class='ctx'> 				}</div><div class='del'>-				ASSERT(i &lt; max_num_polls);</div><div class='ctx'> </div><div class='ctx'> 				if (!dc_dmub_srv_is_hw_pwr_up(dc-&gt;ctx-&gt;dmub_srv, true))</div><div class='ctx'> 					ASSERT(0);</div><div class='hunk'>@@ -1236,14 +1273,13 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 		dc_dmub_srv_notify_idle(dc, false);</div><div class='ctx'> 		if (!(allow_state &amp; DMUB_IPS1_ALLOW_MASK)) {</div><div class='del'>-			for (i = 0; i &lt; max_num_polls; ++i) {</div><div class='add'>+			for (;;) {</div><div class='ctx'> 				commit_state = dc-&gt;hwss.get_idle_state(dc);</div><div class='ctx'> 				if (commit_state &amp; DMUB_IPS1_COMMIT_MASK)</div><div class='ctx'> 					break;</div><div class='ctx'> </div><div class='ctx'> 				udelay(1);</div><div class='ctx'> 			}</div><div class='del'>-			ASSERT(i &lt; max_num_polls);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1251,3 +1287,131 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)</div><div class='ctx'> 		ASSERT(0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState)</div><div class='add'>+{</div><div class='add'>+	struct dmub_srv *dmub;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dmub = dc_dmub_srv-&gt;dmub;</div><div class='add'>+</div><div class='add'>+	if (powerState == DC_ACPI_CM_POWER_STATE_D0)</div><div class='add'>+		dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0);</div><div class='add'>+	else</div><div class='add'>+		dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (dc_dmub_srv-&gt;idle_allowed == allow_idle)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Entering a low power state requires a driver notification.</div><div class='add'>+	 * Powering up the hardware requires notifying PMFW and DMCUB.</div><div class='add'>+	 * Clearing the driver idle allow requires a DMCUB command.</div><div class='add'>+	 * DMCUB commands requires the DMCUB to be powered up and restored.</div><div class='add'>+	 *</div><div class='add'>+	 * Exit out early to prevent an infinite loop of DMCUB commands</div><div class='add'>+	 * triggering exit low power - use software state to track this.</div><div class='add'>+	 */</div><div class='add'>+	dc_dmub_srv-&gt;idle_allowed = allow_idle;</div><div class='add'>+</div><div class='add'>+	if (!allow_idle)</div><div class='add'>+		dc_dmub_srv_exit_low_power_state(dc);</div><div class='add'>+	else</div><div class='add'>+		dc_dmub_srv_notify_idle(dc, allow_idle);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,</div><div class='add'>+				  enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	return dc_wake_and_execute_dmub_cmd_list(ctx, 1, cmd, wait_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,</div><div class='add'>+				       union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = ctx-&gt;dmub_srv;</div><div class='add'>+	bool result = false, reallow_idle = false;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (count == 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (dc_dmub_srv-&gt;idle_allowed) {</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, false);</div><div class='add'>+		reallow_idle = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * These may have different implementations in DM, so ensure</div><div class='add'>+	 * that we guide it to the expected helper.</div><div class='add'>+	 */</div><div class='add'>+	if (count &gt; 1)</div><div class='add'>+		result = dm_execute_dmub_cmd_list(ctx, count, cmd, wait_type);</div><div class='add'>+	else</div><div class='add'>+		result = dm_execute_dmub_cmd(ctx, cmd, wait_type);</div><div class='add'>+</div><div class='add'>+	if (result &amp;&amp; reallow_idle)</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, true);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dc_dmub_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,</div><div class='add'>+				  uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = ctx-&gt;dmub_srv;</div><div class='add'>+	const uint32_t wait_us = wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT ? 0 : 30;</div><div class='add'>+	enum dmub_status status;</div><div class='add'>+</div><div class='add'>+	if (response)</div><div class='add'>+		*response = 0;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	status = dmub_srv_send_gpint_command(dc_dmub_srv-&gt;dmub, command_code, param, wait_us);</div><div class='add'>+	if (status != DMUB_STATUS_OK) {</div><div class='add'>+		if (status == DMUB_STATUS_TIMEOUT &amp;&amp; wait_type == DM_DMUB_WAIT_TYPE_NO_WAIT)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (response &amp;&amp; wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)</div><div class='add'>+		dmub_srv_get_gpint_response(dc_dmub_srv-&gt;dmub, response);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,</div><div class='add'>+			       uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type)</div><div class='add'>+{</div><div class='add'>+	struct dc_dmub_srv *dc_dmub_srv = ctx-&gt;dmub_srv;</div><div class='add'>+	bool result = false, reallow_idle = false;</div><div class='add'>+</div><div class='add'>+	if (!dc_dmub_srv || !dc_dmub_srv-&gt;dmub)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (dc_dmub_srv-&gt;idle_allowed) {</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, false);</div><div class='add'>+		reallow_idle = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	result = dc_dmub_execute_gpint(ctx, command_code, param, response, wait_type);</div><div class='add'>+</div><div class='add'>+	if (result &amp;&amp; reallow_idle)</div><div class='add'>+		dc_dmub_srv_apply_idle_power_optimizations(ctx-&gt;dc, true);</div><div class='add'>+</div><div class='add'>+	return result;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h<br/>index d4a60f53faab..952bfb368886 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h</a></div><div class='hunk'>@@ -50,6 +50,8 @@ struct dc_dmub_srv {</div><div class='ctx'> </div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	void *dm;</div><div class='add'>+</div><div class='add'>+	bool idle_allowed;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);</div><div class='hunk'>@@ -100,6 +102,59 @@ void dc_dmub_srv_enable_dpia_trace(const struct dc *dc);</div><div class='ctx'> void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, const struct dc_plane_address *addr, uint8_t subvp_index);</div><div class='ctx'> </div><div class='ctx'> bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait);</div><div class='del'>-void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle);</div><div class='del'>-void dc_dmub_srv_exit_low_power_state(const struct dc *dc);</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle);</div><div class='add'>+</div><div class='add'>+void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_wake_and_execute_dmub_cmd() - Wrapper for DMUB command execution.</div><div class='add'>+ *</div><div class='add'>+ * Refer to dc_wake_and_execute_dmub_cmd_list() for usage and limitations,</div><div class='add'>+ * This function is a convenience wrapper for a single command execution.</div><div class='add'>+ *</div><div class='add'>+ * @ctx: DC context</div><div class='add'>+ * @cmd: The command to send/receive</div><div class='add'>+ * @wait_type: The wait behavior for the execution</div><div class='add'>+ *</div><div class='add'>+ * Return: true on command submission success, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool dc_wake_and_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd,</div><div class='add'>+				  enum dm_dmub_wait_type wait_type);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_wake_and_execute_dmub_cmd_list() - Wrapper for DMUB command list execution.</div><div class='add'>+ *</div><div class='add'>+ * If the DMCUB hardware was asleep then it wakes the DMUB before</div><div class='add'>+ * executing the command and attempts to re-enter if the command</div><div class='add'>+ * submission was successful.</div><div class='add'>+ *</div><div class='add'>+ * This should be the preferred command submission interface provided</div><div class='add'>+ * the DC lock is acquired.</div><div class='add'>+ *</div><div class='add'>+ * Entry/exit out of idle power optimizations would need to be</div><div class='add'>+ * manually performed otherwise through dc_allow_idle_optimizations().</div><div class='add'>+ *</div><div class='add'>+ * @ctx: DC context</div><div class='add'>+ * @count: Number of commands to send/receive</div><div class='add'>+ * @cmd: Array of commands to send</div><div class='add'>+ * @wait_type: The wait behavior for the execution</div><div class='add'>+ *</div><div class='add'>+ * Return: true on command submission success, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool dc_wake_and_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count,</div><div class='add'>+				       union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dc_wake_and_execute_gpint()</div><div class='add'>+ *</div><div class='add'>+ * @ctx: DC context</div><div class='add'>+ * @command_code: The command ID to send to DMCUB</div><div class='add'>+ * @param: The parameter to message DMCUB</div><div class='add'>+ * @response: Optional response out value - may be NULL.</div><div class='add'>+ * @wait_type: The wait behavior for the execution</div><div class='add'>+ */</div><div class='add'>+bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_command command_code,</div><div class='add'>+			       uint16_t param, uint32_t *response, enum dm_dmub_wait_type wait_type);</div><div class='add'>+</div><div class='ctx'> #endif /* _DMUB_DC_SRV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h<br/>index eeeeeef4d717..1cb7765f593a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_dp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_dp_types.h</a></div><div class='hunk'>@@ -1377,6 +1377,12 @@ struct dp_trace {</div><div class='ctx'> #ifndef DP_TUNNELING_STATUS</div><div class='ctx'> #define DP_TUNNELING_STATUS				0xE0025 /* 1.4a */</div><div class='ctx'> #endif</div><div class='add'>+#ifndef DP_TUNNELING_MAX_LINK_RATE</div><div class='add'>+#define DP_TUNNELING_MAX_LINK_RATE			0xE0028 /* 1.4a */</div><div class='add'>+#endif</div><div class='add'>+#ifndef DP_TUNNELING_MAX_LANE_COUNT</div><div class='add'>+#define DP_TUNNELING_MAX_LANE_COUNT			0xE0029 /* 1.4a */</div><div class='add'>+#endif</div><div class='ctx'> #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL</div><div class='ctx'> #define DPTX_BW_ALLOCATION_MODE_CONTROL			0xE0030 /* 1.4a */</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c<br/>index cb6eaddab720..8f9a67825615 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_helper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_helper.c</a></div><div class='hunk'>@@ -50,7 +50,7 @@ static inline void submit_dmub_read_modify_write(</div><div class='ctx'> 	cmd_buf-&gt;header.payload_bytes =</div><div class='ctx'> 			sizeof(struct dmub_cmd_read_modify_write_sequence) * offload-&gt;reg_seq_count;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	memset(cmd_buf, 0, sizeof(*cmd_buf));</div><div class='ctx'> </div><div class='hunk'>@@ -67,7 +67,7 @@ static inline void submit_dmub_burst_write(</div><div class='ctx'> 	cmd_buf-&gt;header.payload_bytes =</div><div class='ctx'> 			sizeof(uint32_t) * offload-&gt;reg_seq_count;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	memset(cmd_buf, 0, sizeof(*cmd_buf));</div><div class='ctx'> </div><div class='hunk'>@@ -80,7 +80,7 @@ static inline void submit_dmub_reg_wait(</div><div class='ctx'> {</div><div class='ctx'> 	struct dmub_rb_cmd_reg_wait *cmd_buf = &amp;offload-&gt;cmd_data.reg_wait;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(ctx, &amp;offload-&gt;cmd_data, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	memset(cmd_buf, 0, sizeof(*cmd_buf));</div><div class='ctx'> 	offload-&gt;reg_seq_count = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h<br/>index 9649934ea186..811474f4419b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_hw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_hw_types.h</a></div><div class='hunk'>@@ -244,7 +244,7 @@ enum pixel_format {</div><div class='ctx'> #define DC_MAX_DIRTY_RECTS 3</div><div class='ctx'> struct dc_flip_addrs {</div><div class='ctx'> 	struct dc_plane_address address;</div><div class='del'>-	unsigned int flip_timestamp_in_us;</div><div class='add'>+	unsigned long long flip_timestamp_in_us;</div><div class='ctx'> 	bool flip_immediate;</div><div class='ctx'> 	/* TODO: add flip duration for FreeSync */</div><div class='ctx'> 	bool triplebuffer_flips;</div><div class='hunk'>@@ -465,6 +465,7 @@ struct dc_cursor_mi_param {</div><div class='ctx'> 	struct fixed31_32 v_scale_ratio;</div><div class='ctx'> 	enum dc_rotation_angle rotation;</div><div class='ctx'> 	bool mirror;</div><div class='add'>+	struct dc_stream_state *stream;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* IPP related types */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/dc_plane.h<br/>new file mode 100644<br/>index 000000000000..ef380cae816a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_plane.h</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DC_PLANE_H_</div><div class='add'>+#define _DC_PLANE_H_</div><div class='add'>+</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "dc_hw_types.h"</div><div class='add'>+</div><div class='add'>+struct dc_plane_state *dc_create_plane_state(struct dc *dc);</div><div class='add'>+const struct dc_plane_status *dc_plane_get_status(</div><div class='add'>+		const struct dc_plane_state *plane_state);</div><div class='add'>+void dc_plane_state_retain(struct dc_plane_state *plane_state);</div><div class='add'>+void dc_plane_state_release(struct dc_plane_state *plane_state);</div><div class='add'>+</div><div class='add'>+#endif /* _DC_PLANE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h b/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h<br/>new file mode 100644<br/>index 000000000000..9ee184c1df00<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_plane_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_plane_priv.h</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DC_PLANE_PRIV_H_</div><div class='add'>+#define _DC_PLANE_PRIV_H_</div><div class='add'>+</div><div class='add'>+#include "dc_plane.h"</div><div class='add'>+</div><div class='add'>+void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state);</div><div class='add'>+void dc_plane_destruct(struct dc_plane_state *plane_state);</div><div class='add'>+</div><div class='add'>+#endif /* _DC_PLANE_PRIV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_state.h b/drivers/gpu/drm/amd/display/dc/dc_state.h<br/>new file mode 100644<br/>index 000000000000..d167fdbfa8a9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_state.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_state.h</a></div><div class='hunk'>@@ -0,0 +1,78 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DC_STATE_H_</div><div class='add'>+#define _DC_STATE_H_</div><div class='add'>+</div><div class='add'>+#include "dc.h"</div><div class='add'>+#include "inc/core_status.h"</div><div class='add'>+</div><div class='add'>+struct dc_state *dc_state_create(struct dc *dc);</div><div class='add'>+void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state);</div><div class='add'>+struct dc_state *dc_state_create_copy(struct dc_state *src_state);</div><div class='add'>+void dc_state_copy_current(struct dc *dc, struct dc_state *dst_state);</div><div class='add'>+struct dc_state *dc_state_create_current_copy(struct dc *dc);</div><div class='add'>+void dc_state_construct(struct dc *dc, struct dc_state *state);</div><div class='add'>+void dc_state_destruct(struct dc_state *state);</div><div class='add'>+void dc_state_retain(struct dc_state *state);</div><div class='add'>+void dc_state_release(struct dc_state *state);</div><div class='add'>+</div><div class='add'>+enum dc_status dc_state_add_stream(struct dc *dc,</div><div class='add'>+				    struct dc_state *state,</div><div class='add'>+				    struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+enum dc_status dc_state_remove_stream(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+bool dc_state_add_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state *plane_state,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state *plane_state,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_rem_all_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_add_all_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		struct dc_plane_state * const *plane_states,</div><div class='add'>+		int plane_count,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+struct dc_stream_status *dc_state_get_stream_status(</div><div class='add'>+	struct dc_state *state,</div><div class='add'>+	struct dc_stream_state *stream);</div><div class='add'>+#endif /* _DC_STATE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_state_priv.h b/drivers/gpu/drm/amd/display/dc/dc_state_priv.h<br/>new file mode 100644<br/>index 000000000000..c1f44e09a6c1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_state_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_state_priv.h</a></div><div class='hunk'>@@ -0,0 +1,102 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DC_STATE_PRIV_H_</div><div class='add'>+#define _DC_STATE_PRIV_H_</div><div class='add'>+</div><div class='add'>+#include "dc_state.h"</div><div class='add'>+#include "dc_stream.h"</div><div class='add'>+</div><div class='add'>+/* Get the type of the provided resource (none, phantom, main) based on the provided</div><div class='add'>+ * context. If the context is unavailable, determine only if phantom or not.</div><div class='add'>+ */</div><div class='add'>+enum mall_stream_type dc_state_get_pipe_subvp_type(const struct dc_state *state,</div><div class='add'>+		const struct pipe_ctx *pipe_ctx);</div><div class='add'>+enum mall_stream_type dc_state_get_stream_subvp_type(const struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+/* Gets the phantom stream if main is provided, gets the main if phantom is provided.*/</div><div class='add'>+struct dc_stream_state *dc_state_get_paired_subvp_stream(const struct dc_state *state,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+/* allocate's phantom stream or plane and returns pointer to the object */</div><div class='add'>+struct dc_stream_state *dc_state_create_phantom_stream(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *main_stream);</div><div class='add'>+struct dc_plane_state *dc_state_create_phantom_plane(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_plane_state *main_plane);</div><div class='add'>+</div><div class='add'>+/* deallocate's phantom stream or plane */</div><div class='add'>+void dc_state_release_phantom_stream(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream);</div><div class='add'>+void dc_state_release_phantom_plane(const struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_plane_state *phantom_plane);</div><div class='add'>+</div><div class='add'>+/* add/remove phantom stream to context and generate subvp meta data */</div><div class='add'>+enum dc_status dc_state_add_phantom_stream(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_stream_state *main_stream);</div><div class='add'>+enum dc_status dc_state_remove_phantom_stream(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct dc_stream_state *phantom_stream);</div><div class='add'>+</div><div class='add'>+bool dc_state_add_phantom_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state *phantom_plane,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_phantom_plane(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state *phantom_plane,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_rem_all_phantom_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		bool should_release_planes);</div><div class='add'>+</div><div class='add'>+bool dc_state_add_all_phantom_planes_for_stream(</div><div class='add'>+		const struct dc *dc,</div><div class='add'>+		struct dc_stream_state *phantom_stream,</div><div class='add'>+		struct dc_plane_state * const *phantom_planes,</div><div class='add'>+		int plane_count,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+bool dc_state_remove_phantom_streams_and_planes(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+void dc_state_release_phantom_streams_and_planes(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *state);</div><div class='add'>+</div><div class='add'>+#endif /* _DC_STATE_PRIV_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h<br/>index e61eea6db29c..ee10941caa59 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_stream.h</a></div><div class='hunk'>@@ -38,6 +38,14 @@ struct timing_sync_info {</div><div class='ctx'> 	bool master;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mall_stream_config {</div><div class='add'>+	/* MALL stream config to indicate if the stream is phantom or not.</div><div class='add'>+	 * We will use a phantom stream to indicate that the pipe is phantom.</div><div class='add'>+	 */</div><div class='add'>+	enum mall_stream_type type;</div><div class='add'>+	struct dc_stream_state *paired_stream;	// master / slave stream</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dc_stream_status {</div><div class='ctx'> 	int primary_otg_inst;</div><div class='ctx'> 	int stream_enc_inst;</div><div class='hunk'>@@ -50,6 +58,7 @@ struct dc_stream_status {</div><div class='ctx'> 	struct timing_sync_info timing_sync_info;</div><div class='ctx'> 	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];</div><div class='ctx'> 	bool is_abm_supported;</div><div class='add'>+	struct mall_stream_config mall_stream_config;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum hubp_dmdata_mode {</div><div class='hunk'>@@ -147,31 +156,6 @@ struct test_pattern {</div><div class='ctx'> </div><div class='ctx'> #define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR)</div><div class='ctx'> </div><div class='del'>-enum mall_stream_type {</div><div class='del'>-	SUBVP_NONE, // subvp not in use</div><div class='del'>-	SUBVP_MAIN, // subvp in use, this stream is main stream</div><div class='del'>-	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct mall_stream_config {</div><div class='del'>-	/* MALL stream config to indicate if the stream is phantom or not.</div><div class='del'>-	 * We will use a phantom stream to indicate that the pipe is phantom.</div><div class='del'>-	 */</div><div class='del'>-	enum mall_stream_type type;</div><div class='del'>-	struct dc_stream_state *paired_stream;	// master / slave stream</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Temp struct used to save and restore MALL config</div><div class='del'>- * during validation.</div><div class='del'>- *</div><div class='del'>- * TODO: Move MALL config into dc_state instead of stream struct</div><div class='del'>- * to avoid needing to save/restore.</div><div class='del'>- */</div><div class='del'>-struct mall_temp_config {</div><div class='del'>-	struct mall_stream_config mall_stream_config[MAX_PIPES];</div><div class='del'>-	bool is_phantom_plane[MAX_PIPES];</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct dc_stream_debug_options {</div><div class='ctx'> 	char force_odm_combine_segments;</div><div class='ctx'> };</div><div class='hunk'>@@ -301,7 +285,7 @@ struct dc_stream_state {</div><div class='ctx'> 	bool has_non_synchronizable_pclk;</div><div class='ctx'> 	bool vblank_synchronized;</div><div class='ctx'> 	bool fpo_in_use;</div><div class='del'>-	struct mall_stream_config mall_stream_config;</div><div class='add'>+	bool is_phantom;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define ABM_LEVEL_IMMEDIATE_DISABLE 255</div><div class='hunk'>@@ -415,45 +399,14 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,</div><div class='ctx'> 				  uint32_t *h_position,</div><div class='ctx'> 				  uint32_t *v_position);</div><div class='ctx'> </div><div class='del'>-enum dc_status dc_add_stream_to_ctx(</div><div class='del'>-			struct dc *dc,</div><div class='del'>-		struct dc_state *new_ctx,</div><div class='del'>-		struct dc_stream_state *stream);</div><div class='del'>-</div><div class='del'>-enum dc_status dc_remove_stream_from_ctx(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-			struct dc_state *new_ctx,</div><div class='del'>-			struct dc_stream_state *stream);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-bool dc_add_plane_to_context(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state *plane_state,</div><div class='del'>-		struct dc_state *context);</div><div class='del'>-</div><div class='del'>-bool dc_remove_plane_from_context(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state *plane_state,</div><div class='del'>-		struct dc_state *context);</div><div class='del'>-</div><div class='del'>-bool dc_rem_all_planes_for_stream(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_state *context);</div><div class='del'>-</div><div class='del'>-bool dc_add_all_planes_for_stream(</div><div class='del'>-		const struct dc *dc,</div><div class='del'>-		struct dc_stream_state *stream,</div><div class='del'>-		struct dc_plane_state * const *plane_states,</div><div class='del'>-		int plane_count,</div><div class='del'>-		struct dc_state *context);</div><div class='del'>-</div><div class='ctx'> bool dc_stream_add_writeback(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_writeback_info *wb_info);</div><div class='ctx'> </div><div class='add'>+bool dc_stream_fc_disable_writeback(struct dc *dc,</div><div class='add'>+		struct dc_stream_state *stream,</div><div class='add'>+		uint32_t dwb_pipe_inst);</div><div class='add'>+</div><div class='ctx'> bool dc_stream_remove_writeback(struct dc *dc,</div><div class='ctx'> 		struct dc_stream_state *stream,</div><div class='ctx'> 		uint32_t dwb_pipe_inst);</div><div class='hunk'>@@ -514,9 +467,6 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);</div><div class='ctx'> void dc_stream_retain(struct dc_stream_state *dc_stream);</div><div class='ctx'> void dc_stream_release(struct dc_stream_state *dc_stream);</div><div class='ctx'> </div><div class='del'>-struct dc_stream_status *dc_stream_get_status_from_state(</div><div class='del'>-	struct dc_state *state,</div><div class='del'>-	struct dc_stream_state *stream);</div><div class='ctx'> struct dc_stream_status *dc_stream_get_status(</div><div class='ctx'> 	struct dc_stream_state *dc_stream);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h b/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h<br/>new file mode 100644<br/>index 000000000000..7476fd52ce2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_stream_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_stream_priv.h</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DC_STREAM_PRIV_H_</div><div class='add'>+#define _DC_STREAM_PRIV_H_</div><div class='add'>+</div><div class='add'>+#include "dc_stream.h"</div><div class='add'>+</div><div class='add'>+bool dc_stream_construct(struct dc_stream_state *stream,</div><div class='add'>+	struct dc_sink *dc_sink_data);</div><div class='add'>+void dc_stream_destruct(struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+void dc_stream_assign_stream_id(struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+#endif // _DC_STREAM_PRIV_H_</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h<br/>index fcb825e4f1bb..b08ccb8c68bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dc_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dc_types.h</a></div><div class='hunk'>@@ -991,10 +991,6 @@ struct link_mst_stream_allocation_table {</div><div class='ctx'> 	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct backlight_settings {</div><div class='del'>-	uint32_t backlight_millinits;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* PSR feature flags */</div><div class='ctx'> struct psr_settings {</div><div class='ctx'> 	bool psr_feature_enabled;		// PSR is supported by sink</div><div class='hunk'>@@ -1022,6 +1018,24 @@ enum replay_coasting_vtotal_type {</div><div class='ctx'> 	PR_COASTING_TYPE_NUM,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum replay_link_off_frame_count_level {</div><div class='add'>+	PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0,</div><div class='add'>+	PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2,</div><div class='add'>+	PR_LINK_OFF_FRAME_COUNT_BEST = 0x6,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This is general Interface for Replay to</div><div class='add'>+ * set an 32 bit variable to dmub</div><div class='add'>+ * The Message_type indicates which variable</div><div class='add'>+ * passed to DMUB.</div><div class='add'>+ */</div><div class='add'>+enum replay_FW_Message_type {</div><div class='add'>+	Replay_Msg_Not_Support = -1,</div><div class='add'>+	Replay_Set_Timing_Sync_Supported,</div><div class='add'>+	Replay_Set_Residency_Frameupdate_Timer,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> union replay_error_status {</div><div class='ctx'> 	struct {</div><div class='ctx'> 		unsigned char STATE_TRANSITION_ERROR    :1;</div><div class='hunk'>@@ -1033,26 +1047,48 @@ union replay_error_status {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct replay_config {</div><div class='del'>-	bool replay_supported;                          // Replay feature is supported</div><div class='del'>-	unsigned int replay_power_opt_supported;        // Power opt flags that are supported</div><div class='del'>-	bool replay_smu_opt_supported;                  // SMU optimization is supported</div><div class='del'>-	unsigned int replay_enable_option;              // Replay enablement option</div><div class='del'>-	uint32_t debug_flags;                           // Replay debug flags</div><div class='del'>-	bool replay_timing_sync_supported; // Replay desync is supported</div><div class='del'>-	bool force_disable_desync_error_check;             // Replay desync is supported</div><div class='del'>-	bool received_desync_error_hpd; //Replay Received Desync Error HPD.</div><div class='del'>-	union replay_error_status replay_error_status; // Replay error status</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Replay feature flags */</div><div class='add'>+	/* Replay feature is supported */</div><div class='add'>+	bool replay_supported;</div><div class='add'>+	/* Power opt flags that are supported */</div><div class='add'>+	unsigned int replay_power_opt_supported;</div><div class='add'>+	/* SMU optimization is supported */</div><div class='add'>+	bool replay_smu_opt_supported;</div><div class='add'>+	/* Replay enablement option */</div><div class='add'>+	unsigned int replay_enable_option;</div><div class='add'>+	/* Replay debug flags */</div><div class='add'>+	uint32_t debug_flags;</div><div class='add'>+	/* Replay sync is supported */</div><div class='add'>+	bool replay_timing_sync_supported;</div><div class='add'>+	/* Replay Disable desync error check. */</div><div class='add'>+	bool force_disable_desync_error_check;</div><div class='add'>+	/* Replay Received Desync Error HPD. */</div><div class='add'>+	bool received_desync_error_hpd;</div><div class='add'>+	/* Replay feature is supported long vblank */</div><div class='add'>+	bool replay_support_fast_resync_in_ultra_sleep_mode;</div><div class='add'>+	/* Replay error status */</div><div class='add'>+	union replay_error_status replay_error_status;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Replay feature flags*/</div><div class='ctx'> struct replay_settings {</div><div class='del'>-	struct replay_config config;            // Replay configuration</div><div class='del'>-	bool replay_feature_enabled;            // Replay feature is ready for activating</div><div class='del'>-	bool replay_allow_active;               // Replay is currently active</div><div class='del'>-	unsigned int replay_power_opt_active;   // Power opt flags that are activated currently</div><div class='del'>-	bool replay_smu_opt_enable;             // SMU optimization is enabled</div><div class='del'>-	uint16_t coasting_vtotal;               // Current Coasting vtotal</div><div class='del'>-	uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; // Coasting vtotal table</div><div class='add'>+	/* Replay configuration */</div><div class='add'>+	struct replay_config config;</div><div class='add'>+	/* Replay feature is ready for activating */</div><div class='add'>+	bool replay_feature_enabled;</div><div class='add'>+	/* Replay is currently active */</div><div class='add'>+	bool replay_allow_active;</div><div class='add'>+	/* Replay is currently active */</div><div class='add'>+	bool replay_allow_long_vblank;</div><div class='add'>+	/* Power opt flags that are activated currently */</div><div class='add'>+	unsigned int replay_power_opt_active;</div><div class='add'>+	/* SMU optimization is enabled */</div><div class='add'>+	bool replay_smu_opt_enable;</div><div class='add'>+	/* Current Coasting vtotal */</div><div class='add'>+	uint16_t coasting_vtotal;</div><div class='add'>+	/* Coasting vtotal table */</div><div class='add'>+	uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];</div><div class='add'>+	/* Maximum link off frame count */</div><div class='add'>+	enum replay_link_off_frame_count_level link_off_frame_count_level;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* To split out "global" and "per-panel" config settings.</div><div class='hunk'>@@ -1104,25 +1140,34 @@ struct dc_panel_config {</div><div class='ctx'> 	} ilr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define MAX_SINKS_PER_LINK 4</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  *  USB4 DPIA BW ALLOCATION STRUCTS</div><div class='ctx'>  */</div><div class='ctx'> struct dc_dpia_bw_alloc {</div><div class='del'>-	int sink_verified_bw;  // The Verified BW that sink can allocated and use that has been verified already</div><div class='del'>-	int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated</div><div class='del'>-	int sink_max_bw;       // The Max BW that sink can require/support</div><div class='add'>+	int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks</div><div class='add'>+	int link_verified_bw;  // The Verified BW that link can allocated and use that has been verified already</div><div class='add'>+	int link_max_bw;       // The Max BW that link can require/support</div><div class='add'>+	int allocated_bw;      // The Actual Allocated BW for this DPIA</div><div class='ctx'> 	int estimated_bw;      // The estimated available BW for this DPIA</div><div class='ctx'> 	int bw_granularity;    // BW Granularity</div><div class='add'>+	int dp_overhead;       // DP overhead in dp tunneling</div><div class='ctx'> 	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx &amp; Dpia &amp; CM</div><div class='ctx'> 	bool response_ready;   // Response ready from the CM side</div><div class='add'>+	uint8_t nrd_max_lane_count; // Non-reduced max lane count</div><div class='add'>+	uint8_t nrd_max_link_rate; // Non-reduced max link rate</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define MAX_SINKS_PER_LINK 4</div><div class='del'>-</div><div class='ctx'> enum dc_hpd_enable_select {</div><div class='ctx'> 	HPD_EN_FOR_ALL_EDP = 0,</div><div class='ctx'> 	HPD_EN_FOR_PRIMARY_EDP_ONLY,</div><div class='ctx'> 	HPD_EN_FOR_SECONDARY_EDP_ONLY,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum mall_stream_type {</div><div class='add'>+	SUBVP_NONE, // subvp not in use</div><div class='add'>+	SUBVP_MAIN, // subvp in use, this stream is main stream</div><div class='add'>+	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream</div><div class='add'>+};</div><div class='ctx'> #endif /* DC_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c<br/>index 874b132fe1d7..a6006776333d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_abm.c</a></div><div class='hunk'>@@ -135,7 +135,7 @@ static void dmcu_set_backlight_level(</div><div class='ctx'> 			0, 1, 80000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dce_abm_init(struct abm *abm, uint32_t backlight)</div><div class='add'>+static void dce_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);</div><div class='ctx'> </div><div class='hunk'>@@ -162,7 +162,7 @@ static void dce_abm_init(struct abm *abm, uint32_t backlight)</div><div class='ctx'> 			BL1_PWM_TARGET_ABM_LEVEL, backlight);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(BL1_PWM_USER_LEVEL,</div><div class='del'>-			BL1_PWM_USER_LEVEL, backlight);</div><div class='add'>+			BL1_PWM_USER_LEVEL, user_level);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,</div><div class='ctx'> 			ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c<br/>index 140598f18bbd..f0458b8f00af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_audio.c</a></div><div class='hunk'>@@ -782,7 +782,7 @@ static void get_azalia_clock_info_dp(</div><div class='ctx'> 	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;</div><div class='ctx'> 	 *  [khz] -&gt;[100Hz] */</div><div class='ctx'> 	azalia_clock_info-&gt;audio_dto_module =</div><div class='del'>-		pll_info-&gt;dp_dto_source_clock_in_khz * 10;</div><div class='add'>+		pll_info-&gt;audio_dto_source_clock_in_khz * 10;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dce_aud_wall_dto_setup(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c<br/>index 5d3f6fa1011e..970644b695cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c</a></div><div class='hunk'>@@ -975,6 +975,9 @@ static bool dcn31_program_pix_clk(</div><div class='ctx'> 			look_up_in_video_optimized_rate_tlb(pix_clk_params-&gt;requested_pix_clk_100hz / 10);</div><div class='ctx'> 	struct bp_pixel_clock_parameters bp_pc_params = {0};</div><div class='ctx'> 	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;</div><div class='add'>+</div><div class='add'>+	if (clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz != 0)</div><div class='add'>+		dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz;</div><div class='ctx'> 	// For these signal types Driver to program DP_DTO without calling VBIOS Command table</div><div class='ctx'> 	if (dc_is_dp_signal(pix_clk_params-&gt;signal_type) || dc_is_virtual_signal(pix_clk_params-&gt;signal_type)) {</div><div class='ctx'> 		if (e) {</div><div class='hunk'>@@ -1088,6 +1091,10 @@ static bool get_pixel_clk_frequency_100hz(</div><div class='ctx'> 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);</div><div class='ctx'> 	unsigned int clock_hz = 0;</div><div class='ctx'> 	unsigned int modulo_hz = 0;</div><div class='add'>+	unsigned int dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz;</div><div class='add'>+</div><div class='add'>+	if (clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz != 0)</div><div class='add'>+		dp_dto_ref_khz = clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dp_dto_source_clock_in_khz;</div><div class='ctx'> </div><div class='ctx'> 	if (clock_source-&gt;id == CLOCK_SOURCE_ID_DP_DTO) {</div><div class='ctx'> 		clock_hz = REG_READ(PHASE[inst]);</div><div class='hunk'>@@ -1100,7 +1107,7 @@ static bool get_pixel_clk_frequency_100hz(</div><div class='ctx'> 			modulo_hz = REG_READ(MODULO[inst]);</div><div class='ctx'> 			if (modulo_hz)</div><div class='ctx'> 				*pixel_clk_khz = div_u64((uint64_t)clock_hz*</div><div class='del'>-					clock_source-&gt;ctx-&gt;dc-&gt;clk_mgr-&gt;dprefclk_khz*10,</div><div class='add'>+					dp_dto_ref_khz*10,</div><div class='ctx'> 					modulo_hz);</div><div class='ctx'> 			else</div><div class='ctx'> 				*pixel_clk_khz = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c<br/>index d3e6544022b7..ccc154b0281c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c</a></div><div class='hunk'>@@ -57,18 +57,22 @@ static unsigned int abm_feature_support(struct abm *abm, unsigned int panel_inst</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dmub_abm_init_ex(struct abm *abm, uint32_t backlight)</div><div class='add'>+static void dmub_abm_init_ex(struct abm *abm, uint32_t backlight, uint32_t user_level)</div><div class='ctx'> {</div><div class='del'>-	dmub_abm_init(abm, backlight);</div><div class='add'>+	dmub_abm_init(abm, backlight, user_level);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned int dmub_abm_get_current_backlight_ex(struct abm *abm)</div><div class='ctx'> {</div><div class='add'>+	dc_allow_idle_optimizations(abm-&gt;ctx-&gt;dc, false);</div><div class='add'>+</div><div class='ctx'> 	return dmub_abm_get_current_backlight(abm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned int dmub_abm_get_target_backlight_ex(struct abm *abm)</div><div class='ctx'> {</div><div class='add'>+	dc_allow_idle_optimizations(abm-&gt;ctx-&gt;dc, false);</div><div class='add'>+</div><div class='ctx'> 	return dmub_abm_get_target_backlight(abm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -145,7 +149,11 @@ static bool dmub_abm_save_restore_ex(</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dmub_abm_set_pipe_ex(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst)</div><div class='add'>+static bool dmub_abm_set_pipe_ex(struct abm *abm,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		uint32_t option,</div><div class='add'>+		uint32_t panel_inst,</div><div class='add'>+		uint32_t pwrseq_inst)</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = false;</div><div class='ctx'> 	unsigned int feature_support;</div><div class='hunk'>@@ -153,7 +161,7 @@ static bool dmub_abm_set_pipe_ex(struct abm *abm, uint32_t otg_inst, uint32_t op</div><div class='ctx'> 	feature_support = abm_feature_support(abm, panel_inst);</div><div class='ctx'> </div><div class='ctx'> 	if (feature_support == ABM_LCD_SUPPORT)</div><div class='del'>-		ret = dmub_abm_set_pipe(abm, otg_inst, option, panel_inst);</div><div class='add'>+		ret = dmub_abm_set_pipe(abm, otg_inst, option, panel_inst, pwrseq_inst);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c<br/>index 592a8f7a1c6d..f9d6a181164a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c</a></div><div class='hunk'>@@ -76,10 +76,10 @@ static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)</div><div class='ctx'> 	cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask;</div><div class='ctx'> 	cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pwm_frac_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dmub_abm_init(struct abm *abm, uint32_t backlight)</div><div class='add'>+void dmub_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_abm *dce_abm = TO_DMUB_ABM(abm);</div><div class='ctx'> </div><div class='hunk'>@@ -106,7 +106,7 @@ void dmub_abm_init(struct abm *abm, uint32_t backlight)</div><div class='ctx'> 			BL1_PWM_TARGET_ABM_LEVEL, backlight);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE(BL1_PWM_USER_LEVEL,</div><div class='del'>-			BL1_PWM_USER_LEVEL, backlight);</div><div class='add'>+			BL1_PWM_USER_LEVEL, user_level);</div><div class='ctx'> </div><div class='ctx'> 	REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,</div><div class='ctx'> 			ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,</div><div class='hunk'>@@ -155,7 +155,7 @@ bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask)</div><div class='ctx'> 	cmd.abm_set_level.abm_set_level_data.panel_mask = panel_mask;</div><div class='ctx'> 	cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_level_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -186,7 +186,7 @@ void dmub_abm_init_config(struct abm *abm,</div><div class='ctx'> </div><div class='ctx'> 	cmd.abm_init_config.header.payload_bytes = sizeof(struct dmub_cmd_abm_init_config_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -203,7 +203,7 @@ bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, un</div><div class='ctx'> 	cmd.abm_pause.abm_pause_data.panel_mask = panel_mask;</div><div class='ctx'> 	cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_pause_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -246,7 +246,7 @@ bool dmub_abm_save_restore(</div><div class='ctx'> </div><div class='ctx'> 	cmd.abm_save_restore.header.payload_bytes = sizeof(struct dmub_rb_cmd_abm_save_restore);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	// Copy iramtable data into local structure</div><div class='ctx'> 	memcpy((void *)pData, dc-&gt;dmub_srv-&gt;dmub-&gt;scratch_mem_fb.cpu_addr, bytes);</div><div class='hunk'>@@ -254,7 +254,11 @@ bool dmub_abm_save_restore(</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst)</div><div class='add'>+bool dmub_abm_set_pipe(struct abm *abm,</div><div class='add'>+		uint32_t otg_inst,</div><div class='add'>+		uint32_t option,</div><div class='add'>+		uint32_t panel_inst,</div><div class='add'>+		uint32_t pwrseq_inst)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = abm-&gt;ctx;</div><div class='hunk'>@@ -264,12 +268,13 @@ bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint</div><div class='ctx'> 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;</div><div class='ctx'> 	cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;</div><div class='add'>+	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;</div><div class='ctx'> 	cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -291,7 +296,7 @@ bool dmub_abm_set_backlight_level(struct abm *abm,</div><div class='ctx'> 	cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 &lt;&lt; panel_inst);</div><div class='ctx'> 	cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h<br/>index 853564d7f471..761685e5b8c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.h</a></div><div class='hunk'>@@ -30,7 +30,7 @@</div><div class='ctx'> </div><div class='ctx'> struct abm_save_restore;</div><div class='ctx'> </div><div class='del'>-void dmub_abm_init(struct abm *abm, uint32_t backlight);</div><div class='add'>+void dmub_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level);</div><div class='ctx'> bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask);</div><div class='ctx'> unsigned int dmub_abm_get_current_backlight(struct abm *abm);</div><div class='ctx'> unsigned int dmub_abm_get_target_backlight(struct abm *abm);</div><div class='hunk'>@@ -44,7 +44,7 @@ bool dmub_abm_save_restore(</div><div class='ctx'> 		struct dc_context *dc,</div><div class='ctx'> 		unsigned int panel_inst,</div><div class='ctx'> 		struct abm_save_restore *pData);</div><div class='del'>-bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst);</div><div class='add'>+bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst);</div><div class='ctx'> bool dmub_abm_set_backlight_level(struct abm *abm,</div><div class='ctx'> 		unsigned int backlight_pwm_u16_16,</div><div class='ctx'> 		unsigned int frame_ramp,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c<br/>index 2aa0e01a6891..ba1fec3016d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c</a></div><div class='hunk'>@@ -47,7 +47,7 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,</div><div class='ctx'> 	if (!lock)</div><div class='ctx'> 		cmd.lock_hw.lock_hw_data.should_release = 1;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c<br/>index d8009b2dc56a..98a778996e1a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c</a></div><div class='hunk'>@@ -48,5 +48,5 @@ void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)</div><div class='ctx'> 		sizeof(cmd.outbox1_enable.header);</div><div class='ctx'> 	cmd.outbox1_enable.enable = true;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c<br/>index 9d4170a356a2..3e243e407bb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c</a></div><div class='hunk'>@@ -105,23 +105,18 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *srv = dmub-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='ctx'> 	uint32_t raw_state = 0;</div><div class='ctx'> 	uint32_t retry_count = 0;</div><div class='del'>-	enum dmub_status status;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		// Send gpint command and wait for ack</div><div class='del'>-		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);</div><div class='del'>-</div><div class='del'>-		if (status == DMUB_STATUS_OK) {</div><div class='del'>-			// GPINT was executed, get response</div><div class='del'>-			dmub_srv_get_gpint_response(srv, &amp;raw_state);</div><div class='add'>+		if (dc_wake_and_execute_gpint(dmub-&gt;ctx, DMUB_GPINT__GET_PSR_STATE, panel_inst, &amp;raw_state,</div><div class='add'>+					      DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {</div><div class='ctx'> 			*state = convert_psr_state(raw_state);</div><div class='del'>-		} else</div><div class='add'>+		} else {</div><div class='ctx'> 			// Return invalid state when GPINT times out</div><div class='ctx'> 			*state = PSR_STATE_INVALID;</div><div class='del'>-</div><div class='add'>+		}</div><div class='ctx'> 	} while (++retry_count &lt;= 1000 &amp;&amp; *state == PSR_STATE_INVALID);</div><div class='ctx'> </div><div class='ctx'> 	// Assert if max retry hit</div><div class='hunk'>@@ -171,7 +166,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *</div><div class='ctx'> 	cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;</div><div class='ctx'> 	cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -199,7 +194,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8</div><div class='ctx'> </div><div class='ctx'> 	cmd.psr_enable.header.payload_bytes = 0; // Send header only</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	/* Below loops 1000 x 500us = 500 ms.</div><div class='ctx'> 	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at</div><div class='hunk'>@@ -248,7 +243,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_</div><div class='ctx'> 	cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;</div><div class='ctx'> 	cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;</div><div class='ctx'> 	cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;</div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -267,7 +262,7 @@ static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,</div><div class='ctx'> 	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;</div><div class='ctx'> 	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -286,7 +281,7 @@ static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt</div><div class='ctx'> 	cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;</div><div class='ctx'> 	cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -423,7 +418,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,</div><div class='ctx'> 		copy_settings_data-&gt;relock_delay_frame_cnt = 2;</div><div class='ctx'> 	copy_settings_data-&gt;dsc_slice_height = psr_context-&gt;dsc_slice_height;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -444,7 +439,7 @@ static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)</div><div class='ctx'> 	cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;</div><div class='ctx'> 	cmd.psr_enable.header.payload_bytes = 0;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -452,13 +447,11 @@ static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)</div><div class='ctx'>  */</div><div class='ctx'> static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)</div><div class='ctx'> {</div><div class='del'>-	struct dmub_srv *srv = dmub-&gt;ctx-&gt;dmub_srv-&gt;dmub;</div><div class='ctx'> 	uint16_t param = (uint16_t)(panel_inst &lt;&lt; 8);</div><div class='ctx'> </div><div class='ctx'> 	/* Send gpint command and wait for ack */</div><div class='del'>-	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);</div><div class='del'>-</div><div class='del'>-	dmub_srv_get_gpint_response(srv, residency);</div><div class='add'>+	dc_wake_and_execute_gpint(dmub-&gt;ctx, DMUB_GPINT__PSR_RESIDENCY, param, residency,</div><div class='add'>+				  DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dmub_psr_funcs psr_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c<br/>index 28149e53c2a6..38e4797e9476 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c</a></div><div class='hunk'>@@ -258,13 +258,97 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,</div><div class='ctx'> 		*residency = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * Set REPLAY power optimization flags and coasting vtotal.</div><div class='add'>+ */</div><div class='add'>+static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub,</div><div class='add'>+		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	struct dc_context *dc = dmub-&gt;ctx;</div><div class='add'>+</div><div class='add'>+	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.header.type = DMUB_CMD__REPLAY;</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.header.sub_type =</div><div class='add'>+		DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.header.payload_bytes =</div><div class='add'>+		sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.power_opt = power_opt;</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.panel_inst = panel_inst;</div><div class='add'>+	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * send Replay general cmd to DMUB.</div><div class='add'>+ */</div><div class='add'>+static void dmub_replay_send_cmd(struct dmub_replay *dmub,</div><div class='add'>+		enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element)</div><div class='add'>+{</div><div class='add'>+	union dmub_rb_cmd cmd;</div><div class='add'>+	struct dc_context *ctx = NULL;</div><div class='add'>+</div><div class='add'>+	if (dmub == NULL || cmd_element == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ctx = dmub-&gt;ctx;</div><div class='add'>+	if (ctx != NULL) {</div><div class='add'>+</div><div class='add'>+		if (msg != Replay_Msg_Not_Support) {</div><div class='add'>+			memset(&amp;cmd, 0, sizeof(cmd));</div><div class='add'>+			//Header</div><div class='add'>+			cmd.replay_set_timing_sync.header.type = DMUB_CMD__REPLAY;</div><div class='add'>+		} else</div><div class='add'>+			return;</div><div class='add'>+	} else</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (msg) {</div><div class='add'>+	case Replay_Set_Timing_Sync_Supported:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_set_timing_sync.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED;</div><div class='add'>+		cmd.replay_set_timing_sync.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_timing_sync);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_set_timing_sync.replay_set_timing_sync_data.panel_inst =</div><div class='add'>+						cmd_element-&gt;sync_data.panel_inst;</div><div class='add'>+		cmd.replay_set_timing_sync.replay_set_timing_sync_data.timing_sync_supported =</div><div class='add'>+						cmd_element-&gt;sync_data.timing_sync_supported;</div><div class='add'>+		break;</div><div class='add'>+	case Replay_Set_Residency_Frameupdate_Timer:</div><div class='add'>+		//Header</div><div class='add'>+		cmd.replay_set_frameupdate_timer.header.sub_type =</div><div class='add'>+			DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER;</div><div class='add'>+		cmd.replay_set_frameupdate_timer.header.payload_bytes =</div><div class='add'>+			sizeof(struct dmub_rb_cmd_replay_set_frameupdate_timer);</div><div class='add'>+		//Cmd Body</div><div class='add'>+		cmd.replay_set_frameupdate_timer.data.panel_inst =</div><div class='add'>+						cmd_element-&gt;panel_inst;</div><div class='add'>+		cmd.replay_set_frameupdate_timer.data.enable =</div><div class='add'>+						cmd_element-&gt;timer_data.enable;</div><div class='add'>+		cmd.replay_set_frameupdate_timer.data.frameupdate_count =</div><div class='add'>+						cmd_element-&gt;timer_data.frameupdate_count;</div><div class='add'>+		break;</div><div class='add'>+	case Replay_Msg_Not_Support:</div><div class='add'>+	default:</div><div class='add'>+		return;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dmub_replay_funcs replay_funcs = {</div><div class='del'>-	.replay_copy_settings		= dmub_replay_copy_settings,</div><div class='del'>-	.replay_enable			= dmub_replay_enable,</div><div class='del'>-	.replay_get_state		= dmub_replay_get_state,</div><div class='del'>-	.replay_set_power_opt		= dmub_replay_set_power_opt,</div><div class='del'>-	.replay_set_coasting_vtotal	= dmub_replay_set_coasting_vtotal,</div><div class='del'>-	.replay_residency		= dmub_replay_residency,</div><div class='add'>+	.replay_copy_settings				= dmub_replay_copy_settings,</div><div class='add'>+	.replay_enable					= dmub_replay_enable,</div><div class='add'>+	.replay_get_state				= dmub_replay_get_state,</div><div class='add'>+	.replay_set_power_opt				= dmub_replay_set_power_opt,</div><div class='add'>+	.replay_set_coasting_vtotal			= dmub_replay_set_coasting_vtotal,</div><div class='add'>+	.replay_residency				= dmub_replay_residency,</div><div class='add'>+	.replay_set_power_opt_and_coasting_vtotal	= dmub_replay_set_power_opt_and_coasting_vtotal,</div><div class='add'>+	.replay_send_cmd				= dmub_replay_send_cmd,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h<br/>index e8385bbf51fc..3613aff994d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h</a></div><div class='hunk'>@@ -45,10 +45,14 @@ struct dmub_replay_funcs {</div><div class='ctx'> 		struct replay_context *replay_context, uint8_t panel_inst);</div><div class='ctx'> 	void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt,</div><div class='ctx'> 		uint8_t panel_inst);</div><div class='add'>+	void (*replay_send_cmd)(struct dmub_replay *dmub,</div><div class='add'>+		enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);</div><div class='ctx'> 	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal,</div><div class='ctx'> 		uint8_t panel_inst);</div><div class='ctx'> 	void (*replay_residency)(struct dmub_replay *dmub,</div><div class='ctx'> 		uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm);</div><div class='add'>+	void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,</div><div class='add'>+		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dmub_replay *dmub_replay_create(struct dc_context *ctx);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce100/Makefile b/drivers/gpu/drm/amd/display/dc/dce100/Makefile<br/>deleted file mode 100644<br/>index 0d2f6bbf7558..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce100/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce100/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,46 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# Copyright 2017 Advanced Micro Devices, Inc.</div><div class='del'>-#</div><div class='del'>-# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>-# copy of this software and associated documentation files (the "Software"),</div><div class='del'>-# to deal in the Software without restriction, including without limitation</div><div class='del'>-# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>-# and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>-# Software is furnished to do so, subject to the following conditions:</div><div class='del'>-#</div><div class='del'>-# The above copyright notice and this permission notice shall be included in</div><div class='del'>-# all copies or substantial portions of the Software.</div><div class='del'>-#</div><div class='del'>-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>-# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>-# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>-# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>-# OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>-#</div><div class='del'>-#</div><div class='del'>-# Makefile for the 'controller' sub-component of DAL.</div><div class='del'>-# It provides the control and status of HW CRTC block.</div><div class='del'>-</div><div class='del'>-CFLAGS_$(AMDDALPATH)/dc/dce100/dce100_resource.o = $(call cc-disable-warning, override-init)</div><div class='del'>-</div><div class='del'>-DCE100 = dce100_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCE100)</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-###############################################################################</div><div class='del'>-# DCE 10x</div><div class='del'>-###############################################################################</div><div class='del'>-ifdef 0#CONFIG_DRM_AMD_DC_DCE11_0</div><div class='del'>-TG_DCE100 = dce100_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_TG_DCE100 = $(addprefix \</div><div class='del'>-	$(AMDDALPATH)/dc/dce100/,$(TG_DCE100))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_TG_DCE100)</div><div class='del'>-endif</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile<br/>index 695a50ed5ad2..f0777d61c2cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce110/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce110/Makefile</a></div><div class='hunk'>@@ -26,8 +26,8 @@</div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dce110/dce110_resource.o = $(call cc-disable-warning, override-init)</div><div class='ctx'> </div><div class='ctx'> DCE110 = dce110_timing_generator.o \</div><div class='del'>-dce110_compressor.o dce110_resource.o \</div><div class='del'>-dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \</div><div class='add'>+dce110_compressor.o dce110_opp_regamma_v.o \</div><div class='add'>+dce110_opp_csc_v.o dce110_timing_generator_v.o \</div><div class='ctx'> dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce112/Makefile b/drivers/gpu/drm/amd/display/dc/dce112/Makefile<br/>index e846ef58cab3..7e92effec894 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce112/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce112/Makefile</a></div><div class='hunk'>@@ -25,8 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dce112/dce112_resource.o = $(call cc-disable-warning, override-init)</div><div class='ctx'> </div><div class='del'>-DCE112 = dce112_compressor.o \</div><div class='del'>-dce112_resource.o</div><div class='add'>+DCE112 = dce112_compressor.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile<br/>index 097cf407a15d..1e3ef68a452a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce120/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce120/Makefile</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dce120/dce120_resource.o = $(call cc-disable-warning, override-init)</div><div class='ctx'> </div><div class='del'>-DCE120 = dce120_resource.o dce120_timing_generator.o \</div><div class='add'>+DCE120 = dce120_timing_generator.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile<br/>index 93dd68c31275..7eefffbdc925 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce80/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dce80/Makefile</a></div><div class='hunk'>@@ -25,8 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dce80/dce80_resource.o = $(call cc-disable-warning, override-init)</div><div class='ctx'> </div><div class='del'>-DCE80 = dce80_timing_generator.o \</div><div class='del'>-	dce80_resource.o</div><div class='add'>+DCE80 = dce80_timing_generator.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile<br/>index 2d2007c3e2b6..ae6a131be71b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn10/Makefile</a></div><div class='hunk'>@@ -22,9 +22,9 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN.</div><div class='ctx'> </div><div class='del'>-DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o \</div><div class='add'>+DCN10 = dcn10_ipp.o \</div><div class='ctx'> 		dcn10_hw_sequencer_debug.o \</div><div class='del'>-		dcn10_dpp.o dcn10_opp.o dcn10_optc.o \</div><div class='add'>+		dcn10_dpp.o dcn10_opp.o \</div><div class='ctx'> 		dcn10_hubp.o dcn10_mpc.o \</div><div class='ctx'> 		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \</div><div class='ctx'> 		dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c<br/>index 92fdab731f4a..9033b39e0e0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c</a></div><div class='hunk'>@@ -32,7 +32,7 @@</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> #include "abm.h"</div><div class='ctx'> #include "dmcu.h"</div><div class='del'>-#include "dcn10_optc.h"</div><div class='add'>+#include "dcn10/dcn10_optc.h"</div><div class='ctx'> #include "dcn10/dcn10_dpp.h"</div><div class='ctx'> #include "dcn10/dcn10_mpc.h"</div><div class='ctx'> #include "timing_generator.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile<br/>index d7dc9696a8c8..3dae3943b056 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/Makefile</a></div><div class='hunk'>@@ -2,13 +2,11 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN.</div><div class='ctx'> </div><div class='del'>-DCN20 = dcn20_resource.o dcn20_init.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \</div><div class='del'>-		dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_optc.o dcn20_mmhubbub.o \</div><div class='add'>+DCN20 = dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \</div><div class='add'>+		dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_mmhubbub.o \</div><div class='ctx'> 		dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \</div><div class='ctx'> 		dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o</div><div class='ctx'> </div><div class='del'>-DCN20 += dcn20_dsc.o</div><div class='del'>-</div><div class='ctx'> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h<br/>index ab6d09c6fe34..ef5c22f41563 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h</a></div><div class='hunk'>@@ -291,7 +291,43 @@</div><div class='ctx'> 	type SYMCLKB_FE_SRC_SEL;\</div><div class='ctx'> 	type SYMCLKC_FE_SRC_SEL;\</div><div class='ctx'> 	type SYMCLKD_FE_SRC_SEL;\</div><div class='del'>-	type SYMCLKE_FE_SRC_SEL;</div><div class='add'>+	type SYMCLKE_FE_SRC_SEL;\</div><div class='add'>+	type DTBCLK_P0_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P1_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P2_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P3_GATE_DISABLE;\</div><div class='add'>+	type DSCCLK0_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DSCCLK1_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DSCCLK2_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DSCCLK3_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKA_FE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKB_FE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKC_FE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKD_FE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKE_FE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPPCLK0_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPPCLK1_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPPCLK2_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPPCLK3_ROOT_GATE_DISABLE;\</div><div class='add'>+	type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKA_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKB_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKC_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKD_ROOT_GATE_DISABLE;\</div><div class='add'>+	type SYMCLKE_ROOT_GATE_DISABLE;\</div><div class='add'>+	type PHYA_REFCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type PHYB_REFCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type PHYC_REFCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type PHYD_REFCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type PHYE_REFCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK0_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK1_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK2_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK3_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK0_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK1_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK2_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK3_GATE_DISABLE;\</div><div class='ctx'> </div><div class='ctx'> struct dccg_shift {</div><div class='ctx'> 	DCCG_REG_FIELD_LIST(uint8_t)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c<br/>index 139cf31d2e45..89c3bf0fe0c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c</a></div><div class='hunk'>@@ -1077,8 +1077,16 @@ void hubp2_cursor_set_position(</div><div class='ctx'> 	if (src_y_offset &lt; 0)</div><div class='ctx'> 		src_y_offset = 0;</div><div class='ctx'> 	/* Save necessary cursor info x, y position. w, h is saved in attribute func. */</div><div class='del'>-	hubp-&gt;cur_rect.x = src_x_offset + param-&gt;viewport.x;</div><div class='del'>-	hubp-&gt;cur_rect.y = src_y_offset + param-&gt;viewport.y;</div><div class='add'>+	if (param-&gt;stream-&gt;link-&gt;psr_settings.psr_version &gt;= DC_PSR_VERSION_SU_1 &amp;&amp;</div><div class='add'>+	    param-&gt;rotation != ROTATION_ANGLE_0) {</div><div class='add'>+		hubp-&gt;cur_rect.x = 0;</div><div class='add'>+		hubp-&gt;cur_rect.y = 0;</div><div class='add'>+		hubp-&gt;cur_rect.w = param-&gt;stream-&gt;timing.h_addressable;</div><div class='add'>+		hubp-&gt;cur_rect.h = param-&gt;stream-&gt;timing.v_addressable;</div><div class='add'>+	} else {</div><div class='add'>+		hubp-&gt;cur_rect.x = src_x_offset + param-&gt;viewport.x;</div><div class='add'>+		hubp-&gt;cur_rect.y = src_y_offset + param-&gt;viewport.y;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hubp2_clk_cntl(struct hubp *hubp, bool enable)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/Makefile b/drivers/gpu/drm/amd/display/dc/dcn201/Makefile<br/>index 3a41a97b0729..2b0b4f32e13b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn201/Makefile</a></div><div class='hunk'>@@ -1,9 +1,8 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN.</div><div class='del'>-DCN201 = dcn201_init.o dcn201_resource.o \</div><div class='del'>-	dcn201_hubbub.o\</div><div class='del'>-	dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_optc.o dcn201_dpp.o \</div><div class='add'>+DCN201 = dcn201_hubbub.o\</div><div class='add'>+	dcn201_mpc.o dcn201_hubp.o dcn201_opp.o dcn201_dpp.o \</div><div class='ctx'> 	dcn201_dccg.o dcn201_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN201 = $(addprefix $(AMDDALPATH)/dc/dcn201/,$(DCN201))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile<br/>index ce1be0afae4a..ca92f5c8e7fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn21/Makefile</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN21.</div><div class='ctx'> </div><div class='del'>-DCN21 = dcn21_init.o dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o \</div><div class='add'>+DCN21 = dcn21_hubp.o dcn21_hubbub.o \</div><div class='ctx'> 	 dcn21_link_encoder.o dcn21_dccg.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c<br/>index 68cad55c72ab..e13d69a22c1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c</a></div><div class='hunk'>@@ -691,7 +691,7 @@ static void dmcub_PLAT_54186_wa(struct hubp *hubp,</div><div class='ctx'> 	cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs-&gt;vmid;</div><div class='ctx'> </div><div class='ctx'> 	PERF_TRACE();  // TODO: remove after performance is stable.</div><div class='del'>-	dm_execute_dmub_cmd(hubp-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(hubp-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> 	PERF_TRACE();  // TODO: remove after performance is stable.</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile<br/>index af4d2065d2c1..b5b2aa3b3783 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/Makefile</a></div><div class='hunk'>@@ -23,12 +23,9 @@</div><div class='ctx'> #</div><div class='ctx'> #</div><div class='ctx'> </div><div class='del'>-DCN30 := \</div><div class='del'>-	dcn30_init.o \</div><div class='del'>-	dcn30_hubbub.o \</div><div class='add'>+DCN30 := dcn30_hubbub.o \</div><div class='ctx'> 	dcn30_hubp.o \</div><div class='ctx'> 	dcn30_dpp.o \</div><div class='del'>-	dcn30_optc.o \</div><div class='ctx'> 	dcn30_dccg.o \</div><div class='ctx'> 	dcn30_mpc.o dcn30_vpg.o \</div><div class='ctx'> 	dcn30_afmt.o \</div><div class='hunk'>@@ -38,7 +35,6 @@ DCN30 := \</div><div class='ctx'> 	dcn30_dwb_cm.o \</div><div class='ctx'> 	dcn30_cm_common.o \</div><div class='ctx'> 	dcn30_mmhubbub.o \</div><div class='del'>-	dcn30_resource.o \</div><div class='ctx'> 	dcn30_dio_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c<br/>index 0d98918bf0fc..1b9d9495f76d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c</a></div><div class='hunk'>@@ -130,6 +130,28 @@ bool dwb3_disable(struct dwbc *dwbc)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable)</div><div class='add'>+{</div><div class='add'>+	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);</div><div class='add'>+	unsigned int pre_locked;</div><div class='add'>+</div><div class='add'>+	REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &amp;pre_locked);</div><div class='add'>+</div><div class='add'>+	/* Lock DWB registers */</div><div class='add'>+	if (pre_locked == 0)</div><div class='add'>+		REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1);</div><div class='add'>+</div><div class='add'>+	/* Disable FC */</div><div class='add'>+	REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, enable);</div><div class='add'>+</div><div class='add'>+	/* Unlock DWB registers */</div><div class='add'>+	if (pre_locked == 0)</div><div class='add'>+		REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc-&gt;inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);</div><div class='hunk'>@@ -226,6 +248,7 @@ static const struct dwbc_funcs dcn30_dwbc_funcs = {</div><div class='ctx'> 	.disable		= dwb3_disable,</div><div class='ctx'> 	.update			= dwb3_update,</div><div class='ctx'> 	.is_enabled		= dwb3_is_enabled,</div><div class='add'>+	.set_fc_enable		= dwb3_set_fc_enable,</div><div class='ctx'> 	.set_stereo		= dwb3_set_stereo,</div><div class='ctx'> 	.set_new_content	= dwb3_set_new_content,</div><div class='ctx'> 	.dwb_program_output_csc	= NULL,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h<br/>index a5d1b81e768d..332634b76aac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h</a></div><div class='hunk'>@@ -877,6 +877,8 @@ bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);</div><div class='ctx'> </div><div class='ctx'> bool dwb3_is_enabled(struct dwbc *dwbc);</div><div class='ctx'> </div><div class='add'>+void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);</div><div class='add'>+</div><div class='ctx'> void dwb3_set_stereo(struct dwbc *dwbc,</div><div class='ctx'> 	struct dwb_stereo_params *stereo_params);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c<br/>index 701c7d8bc038..03a50c32fcfe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c</a></div><div class='hunk'>@@ -243,6 +243,9 @@ static bool dwb3_program_ogam_lut(</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (params-&gt;hw_points_num == 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);</div><div class='ctx'> </div><div class='ctx'> 	current_mode = dwb3_get_ogam_current(dwbc30);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile<br/>index 30fbc5e06dca..d241f665e40a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn301/Makefile</a></div><div class='hunk'>@@ -10,9 +10,8 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn30.</div><div class='ctx'> </div><div class='del'>-DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \</div><div class='del'>-		dcn301_dio_link_encoder.o dcn301_panel_cntl.o dcn301_hubbub.o \</div><div class='del'>-		dcn301_optc.o</div><div class='add'>+DCN301 = dcn301_dccg.o \</div><div class='add'>+		dcn301_dio_link_encoder.o dcn301_panel_cntl.o dcn301_hubbub.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile<br/>deleted file mode 100644<br/>index 95b66baf39e9..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn302/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,12 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved</div><div class='del'>-#</div><div class='del'>-#  Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn302.</div><div class='del'>-</div><div class='del'>-DCN3_02 = dcn302_init.o dcn302_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/dcn302/,$(DCN3_02))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_02)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/Makefile b/drivers/gpu/drm/amd/display/dc/dcn303/Makefile<br/>index d7b3ad780e5d..a954e316aca2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn303/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn303/Makefile</a></div><div class='hunk'>@@ -6,7 +6,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn303.</div><div class='ctx'> </div><div class='del'>-DCN3_03 = dcn303_init.o dcn303_resource.o</div><div class='add'>+DCN3_03 = dcn303_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/dcn303/,$(DCN3_03))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile<br/>index 96e45c9efb46..5d93ac16c03a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/Makefile</a></div><div class='hunk'>@@ -10,8 +10,8 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn31.</div><div class='ctx'> </div><div class='del'>-DCN31 = dcn31_resource.o dcn31_hubbub.o dcn31_init.o dcn31_hubp.o \</div><div class='del'>-	dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \</div><div class='add'>+DCN31 = dcn31_hubbub.o dcn31_hubp.o \</div><div class='add'>+	dcn31_dccg.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \</div><div class='ctx'> 	dcn31_apg.o dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o \</div><div class='ctx'> 	dcn31_afmt.o dcn31_vpg.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c<br/>index 4596f3bac1b4..26be5fee7411 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c</a></div><div class='hunk'>@@ -125,7 +125,7 @@ static bool query_dp_alt_from_dmub(struct link_encoder *enc,</div><div class='ctx'> 	cmd-&gt;query_dp_alt.header.payload_bytes = sizeof(cmd-&gt;query_dp_alt.data);</div><div class='ctx'> 	cmd-&gt;query_dp_alt.data.phy_id = phy_id_from_transmitter(enc10-&gt;base.transmitter);</div><div class='ctx'> </div><div class='del'>-	if (!dm_execute_dmub_cmd(enc-&gt;ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(enc-&gt;ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -436,7 +436,7 @@ static bool link_dpia_control(struct dc_context *dc_ctx,</div><div class='ctx'> </div><div class='ctx'> 	cmd.dig1_dpia_control.dpia_control = *dpia_control;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc_ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc_ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c<br/>index 217acd4e292a..03248422d6ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c</a></div><div class='hunk'>@@ -50,9 +50,9 @@ static bool dcn31_query_backlight_info(struct panel_cntl *panel_cntl, union dmub</div><div class='ctx'> 	cmd-&gt;panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;</div><div class='ctx'> 	cmd-&gt;panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO;</div><div class='ctx'> 	cmd-&gt;panel_cntl.header.payload_bytes = sizeof(cmd-&gt;panel_cntl.data);</div><div class='del'>-	cmd-&gt;panel_cntl.data.inst = dcn31_panel_cntl-&gt;base.inst;</div><div class='add'>+	cmd-&gt;panel_cntl.data.pwrseq_inst = dcn31_panel_cntl-&gt;base.pwrseq_inst;</div><div class='ctx'> </div><div class='del'>-	return dm_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='add'>+	return dc_wake_and_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static uint32_t dcn31_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)</div><div class='hunk'>@@ -78,14 +78,14 @@ static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)</div><div class='ctx'> 	cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;</div><div class='ctx'> 	cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_HW_INIT;</div><div class='ctx'> 	cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data);</div><div class='del'>-	cmd.panel_cntl.data.inst = dcn31_panel_cntl-&gt;base.inst;</div><div class='add'>+	cmd.panel_cntl.data.pwrseq_inst = dcn31_panel_cntl-&gt;base.pwrseq_inst;</div><div class='ctx'> 	cmd.panel_cntl.data.bl_pwm_cntl = panel_cntl-&gt;stored_backlight_registers.BL_PWM_CNTL;</div><div class='ctx'> 	cmd.panel_cntl.data.bl_pwm_period_cntl = panel_cntl-&gt;stored_backlight_registers.BL_PWM_PERIOD_CNTL;</div><div class='ctx'> 	cmd.panel_cntl.data.bl_pwm_ref_div1 =</div><div class='ctx'> 		panel_cntl-&gt;stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;</div><div class='ctx'> 	cmd.panel_cntl.data.bl_pwm_ref_div2 =</div><div class='ctx'> 		panel_cntl-&gt;stored_backlight_registers.PANEL_PWRSEQ_REF_DIV2;</div><div class='del'>-	if (!dm_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='add'>+	if (!dc_wake_and_execute_dmub_cmd(dc_dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	panel_cntl-&gt;stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl;</div><div class='hunk'>@@ -157,4 +157,5 @@ void dcn31_panel_cntl_construct(</div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.funcs = &amp;dcn31_link_panel_cntl_funcs;</div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.ctx = init_data-&gt;ctx;</div><div class='ctx'> 	dcn31_panel_cntl-&gt;base.inst = init_data-&gt;inst;</div><div class='add'>+	dcn31_panel_cntl-&gt;base.pwrseq_inst = init_data-&gt;pwrseq_inst;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/Makefile b/drivers/gpu/drm/amd/display/dc/dcn314/Makefile<br/>index 72456debb99f..b134ab05aa71 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn314/Makefile</a></div><div class='hunk'>@@ -10,8 +10,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn314.</div><div class='ctx'> </div><div class='del'>-DCN314 = dcn314_resource.o dcn314_init.o \</div><div class='del'>-		dcn314_dio_stream_encoder.o dcn314_dccg.o dcn314_optc.o</div><div class='add'>+DCN314 = dcn314_dio_stream_encoder.o dcn314_dccg.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN314 = $(addprefix $(AMDDALPATH)/dc/dcn314/,$(DCN314))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/Makefile b/drivers/gpu/drm/amd/display/dc/dcn315/Makefile<br/>deleted file mode 100644<br/>index 59381d24800b..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn315/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn315/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,30 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# Copyright © 2021 Advanced Micro Devices, Inc.</div><div class='del'>-#</div><div class='del'>-# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>-# copy of this software and associated documentation files (the "Software"),</div><div class='del'>-# to deal in the Software without restriction, including without limitation</div><div class='del'>-# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>-# and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>-# Software is furnished to do so, subject to the following conditions:</div><div class='del'>-#</div><div class='del'>-# The above copyright notice and this permission notice shall be included in</div><div class='del'>-# all copies or substantial portions of the Software.</div><div class='del'>-#</div><div class='del'>-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>-# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>-# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>-# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>-# OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>-#</div><div class='del'>-# Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn315.</div><div class='del'>-</div><div class='del'>-DCN315 = dcn315_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN315 = $(addprefix $(AMDDALPATH)/dc/dcn315/,$(DCN315))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN315)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/Makefile b/drivers/gpu/drm/amd/display/dc/dcn316/Makefile<br/>deleted file mode 100644<br/>index 819d44a9439b..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn316/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn316/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,30 +0,0 @@</div><div class='del'>-#</div><div class='del'>-# Copyright 2021 Advanced Micro Devices, Inc.</div><div class='del'>-#</div><div class='del'>-# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>-# copy of this software and associated documentation files (the "Software"),</div><div class='del'>-# to deal in the Software without restriction, including without limitation</div><div class='del'>-# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>-# and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>-# Software is furnished to do so, subject to the following conditions:</div><div class='del'>-#</div><div class='del'>-# The above copyright notice and this permission notice shall be included in</div><div class='del'>-# all copies or substantial portions of the Software.</div><div class='del'>-#</div><div class='del'>-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>-# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>-# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>-# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>-# OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>-#</div><div class='del'>-# Authors: AMD</div><div class='del'>-#</div><div class='del'>-# Makefile for dcn316.</div><div class='del'>-</div><div class='del'>-DCN316 = dcn316_resource.o</div><div class='del'>-</div><div class='del'>-AMD_DAL_DCN316 = $(addprefix $(AMDDALPATH)/dc/dcn316/,$(DCN316))</div><div class='del'>-</div><div class='del'>-AMD_DISPLAY_FILES += $(AMD_DAL_DCN316)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/Makefile b/drivers/gpu/drm/amd/display/dc/dcn32/Makefile<br/>index 8bb251307247..5314770fff1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/Makefile</a></div><div class='hunk'>@@ -10,10 +10,10 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn32.</div><div class='ctx'> </div><div class='del'>-DCN32 = dcn32_resource.o dcn32_hubbub.o dcn32_init.o dcn32_dccg.o \</div><div class='del'>-		dcn32_dccg.o dcn32_optc.o dcn32_mmhubbub.o dcn32_hubp.o dcn32_dpp.o \</div><div class='del'>-		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_hpo_dp_link_encoder.o \</div><div class='del'>-		dcn32_resource_helpers.o dcn32_mpc.o</div><div class='add'>+DCN32 = dcn32_hubbub.o dcn32_dccg.o \</div><div class='add'>+		dcn32_mmhubbub.o dcn32_dpp.o dcn32_hubp.o dcn32_mpc.o \</div><div class='add'>+		dcn32_dio_stream_encoder.o dcn32_dio_link_encoder.o dcn32_resource_helpers.o \</div><div class='add'>+		dcn32_hpo_dp_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c<br/>index 994b21ed272f..e789e654c387 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c</a></div><div class='hunk'>@@ -71,12 +71,13 @@ void mpc32_power_on_blnd_lut(</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);</div><div class='ctx'> </div><div class='add'>+	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);</div><div class='add'>+</div><div class='ctx'> 	if (mpc-&gt;ctx-&gt;dc-&gt;debug.enable_mem_low_power.bits.cm) {</div><div class='ctx'> 		if (power_on) {</div><div class='ctx'> 			REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);</div><div class='ctx'> 			REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);</div><div class='ctx'> 		} else if (!mpc-&gt;ctx-&gt;dc-&gt;debug.disable_mem_low_power) {</div><div class='del'>-			ASSERT(false);</div><div class='ctx'> 			/* TODO: change to mpc</div><div class='ctx'> 			 *  dpp_base-&gt;ctx-&gt;dc-&gt;optimized_required = true;</div><div class='ctx'> 			 *  dpp_base-&gt;deferred_reg_writes.bits.disable_blnd_lut = true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c<br/>index bc5f0db23d0c..87760600e154 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c</a></div><div class='hunk'>@@ -24,10 +24,11 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> // header file of functions being implemented</div><div class='del'>-#include "dcn32_resource.h"</div><div class='add'>+#include "dcn32/dcn32_resource.h"</div><div class='ctx'> #include "dcn20/dcn20_resource.h"</div><div class='ctx'> #include "dml/dcn32/display_mode_vba_util_32.h"</div><div class='ctx'> #include "dml/dcn32/dcn32_fpu.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> static bool is_dual_plane(enum surface_pixel_format format)</div><div class='ctx'> {</div><div class='hunk'>@@ -190,7 +191,7 @@ bool dcn32_subvp_in_use(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_NONE)</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE)</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -264,18 +265,17 @@ static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint</div><div class='ctx'> </div><div class='ctx'> 	// Do not override if a stream has multiple planes</div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-		if (context-&gt;stream_status[i].plane_count &gt; 1) {</div><div class='add'>+		if (context-&gt;stream_status[i].plane_count &gt; 1)</div><div class='ctx'> 			return;</div><div class='del'>-		}</div><div class='del'>-		if (context-&gt;streams[i]-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+</div><div class='add'>+		if (dc_state_get_stream_subvp_type(context, context-&gt;streams[i]) != SUBVP_PHANTOM)</div><div class='ctx'> 			stream_count++;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_state &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='ctx'> 			if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {</div><div class='ctx'> </div><div class='ctx'> 				if (pipe_ctx-&gt;stream-&gt;timing.v_addressable == 1080 &amp;&amp; pipe_ctx-&gt;stream-&gt;timing.h_addressable == 1920) {</div><div class='hunk'>@@ -290,7 +290,7 @@ static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-			if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+			if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_state &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='ctx'> 				if (pipe_ctx-&gt;stream-&gt;timing.v_addressable == 1080 &amp;&amp; pipe_ctx-&gt;stream-&gt;timing.h_addressable == 1920) {</div><div class='ctx'> 					if (pipe_segments[i] &gt; 4)</div><div class='ctx'> 						pipe_segments[i] = 4;</div><div class='hunk'>@@ -337,14 +337,14 @@ void dcn32_determine_det_override(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='ctx'> 		/* Don't count SubVP streams for DET allocation */</div><div class='del'>-		if (context-&gt;streams[i]-&gt;mall_stream_config.type != SUBVP_PHANTOM)</div><div class='add'>+		if (dc_state_get_stream_subvp_type(context, context-&gt;streams[i]) != SUBVP_PHANTOM)</div><div class='ctx'> 			stream_count++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (stream_count &gt; 0) {</div><div class='ctx'> 		stream_segments = 18 / stream_count;</div><div class='ctx'> 		for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='del'>-			if (context-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+			if (dc_state_get_stream_subvp_type(context, context-&gt;streams[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			if (context-&gt;stream_status[i].plane_count &gt; 0)</div><div class='hunk'>@@ -430,71 +430,6 @@ void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		dcn32_determine_det_override(dc, context, pipes);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * dcn32_save_mall_state(): Save MALL (SubVP) state for fast validation cases</div><div class='del'>- *</div><div class='del'>- * This function saves the MALL (SubVP) case for fast validation cases. For fast validation,</div><div class='del'>- * there are situations where a shallow copy of the dc-&gt;current_state is created for the</div><div class='del'>- * validation. In this case we want to save and restore the mall config because we always</div><div class='del'>- * teardown subvp at the beginning of validation (and don't attempt to add it back if it's</div><div class='del'>- * fast validation). If we don't restore the subvp config in cases of fast validation +</div><div class='del'>- * shallow copy of the dc-&gt;current_state, the dc-&gt;current_state will have a partially</div><div class='del'>- * removed subvp state when we did not intend to remove it.</div><div class='del'>- *</div><div class='del'>- * NOTE: This function ONLY works if the streams are not moved to a different pipe in the</div><div class='del'>- *       validation. We don't expect this to happen in fast_validation=1 cases.</div><div class='del'>- *</div><div class='del'>- * @dc: Current DC state</div><div class='del'>- * @context: New DC state to be programmed</div><div class='del'>- * @temp_config: struct used to cache the existing MALL state</div><div class='del'>- *</div><div class='del'>- * Return: void</div><div class='del'>- */</div><div class='del'>-void dcn32_save_mall_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct mall_temp_config *temp_config)</div><div class='del'>-{</div><div class='del'>-	uint32_t i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (pipe-&gt;stream)</div><div class='del'>-			temp_config-&gt;mall_stream_config[i] = pipe-&gt;stream-&gt;mall_stream_config;</div><div class='del'>-</div><div class='del'>-		if (pipe-&gt;plane_state)</div><div class='del'>-			temp_config-&gt;is_phantom_plane[i] = pipe-&gt;plane_state-&gt;is_phantom;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dcn32_restore_mall_state(): Restore MALL (SubVP) state for fast validation cases</div><div class='del'>- *</div><div class='del'>- * Restore the MALL state based on the previously saved state from dcn32_save_mall_state</div><div class='del'>- *</div><div class='del'>- * @dc: Current DC state</div><div class='del'>- * @context: New DC state to be programmed, restore MALL state into here</div><div class='del'>- * @temp_config: struct that has the cached MALL state</div><div class='del'>- *</div><div class='del'>- * Return: void</div><div class='del'>- */</div><div class='del'>-void dcn32_restore_mall_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct mall_temp_config *temp_config)</div><div class='del'>-{</div><div class='del'>-	uint32_t i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (pipe-&gt;stream)</div><div class='del'>-			pipe-&gt;stream-&gt;mall_stream_config = temp_config-&gt;mall_stream_config[i];</div><div class='del'>-</div><div class='del'>-		if (pipe-&gt;plane_state)</div><div class='del'>-			pipe-&gt;plane_state-&gt;is_phantom = temp_config-&gt;is_phantom_plane[i];</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #define MAX_STRETCHED_V_BLANK 1000 // in micro-seconds (must ensure to match value in FW)</div><div class='ctx'> /*</div><div class='ctx'>  * Scaling factor for v_blank stretch calculations considering timing in</div><div class='hunk'>@@ -589,13 +524,14 @@ static int get_refresh_rate(struct dc_stream_state *fpo_candidate_stream)</div><div class='ctx'>  *</div><div class='ctx'>  * Return: Pointer to FPO stream candidate if config can support FPO, otherwise NULL</div><div class='ctx'>  */</div><div class='del'>-struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, const struct dc_state *context)</div><div class='add'>+struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	int refresh_rate = 0;</div><div class='ctx'> 	const int minimum_refreshrate_supported = 120;</div><div class='ctx'> 	struct dc_stream_state *fpo_candidate_stream = NULL;</div><div class='ctx'> 	bool is_fpo_vactive = false;</div><div class='ctx'> 	uint32_t fpo_vactive_margin_us = 0;</div><div class='add'>+	struct dc_stream_status *fpo_stream_status = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (context == NULL)</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -618,16 +554,28 @@ struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stre</div><div class='ctx'> 		DC_FP_START();</div><div class='ctx'> 		dcn32_assign_fpo_vactive_candidate(dc, context, &amp;fpo_candidate_stream);</div><div class='ctx'> 		DC_FP_END();</div><div class='del'>-</div><div class='add'>+		if (fpo_candidate_stream)</div><div class='add'>+			fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);</div><div class='ctx'> 		DC_FP_START();</div><div class='ctx'> 		is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, dc-&gt;debug.fpo_vactive_min_active_margin_us);</div><div class='ctx'> 		DC_FP_END();</div><div class='ctx'> 		if (!is_fpo_vactive || dc-&gt;debug.disable_fpo_vactive)</div><div class='ctx'> 			return NULL;</div><div class='del'>-	} else</div><div class='add'>+	} else {</div><div class='ctx'> 		fpo_candidate_stream = context-&gt;streams[0];</div><div class='add'>+		if (fpo_candidate_stream)</div><div class='add'>+			fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (!fpo_candidate_stream)</div><div class='add'>+	/* In DCN32/321, FPO uses per-pipe P-State force.</div><div class='add'>+	 * If there's no planes, HUBP is power gated and</div><div class='add'>+	 * therefore programming UCLK_PSTATE_FORCE does</div><div class='add'>+	 * nothing (P-State will always be asserted naturally</div><div class='add'>+	 * on a pipe that has HUBP power gated. Therefore we</div><div class='add'>+	 * only want to enable FPO if the FPO pipe has both</div><div class='add'>+	 * a stream and a plane.</div><div class='add'>+	 */</div><div class='add'>+	if (!fpo_candidate_stream || !fpo_stream_status || fpo_stream_status-&gt;plane_count == 0)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (fpo_candidate_stream-&gt;sink-&gt;edid_caps.panel_patch.disable_fams)</div><div class='hunk'>@@ -666,6 +614,30 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int widt</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * disallow_subvp_in_active_plus_blank() - Function to determine disallowed subvp + drr/vblank configs</div><div class='add'>+ *</div><div class='add'>+ * @pipe: subvp pipe to be used for the subvp + drr/vblank config</div><div class='add'>+ *</div><div class='add'>+ * Since subvp is being enabled on more configs (such as 1080p60), we want</div><div class='add'>+ * to explicitly block any configs that we don't want to enable. We do not</div><div class='add'>+ * want to enable any 1080p60 (SubVP) + drr / vblank configs since these</div><div class='add'>+ * are already convered by FPO.</div><div class='add'>+ *</div><div class='add'>+ * Return: True if disallowed, false otherwise</div><div class='add'>+ */</div><div class='add'>+static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)</div><div class='add'>+{</div><div class='add'>+	bool disallow = false;</div><div class='add'>+</div><div class='add'>+	if (resource_is_pipe_type(pipe, OPP_HEAD) &amp;&amp;</div><div class='add'>+			resource_is_pipe_type(pipe, DPP_PIPE)) {</div><div class='add'>+		if (pipe-&gt;stream-&gt;timing.v_addressable == 1080 &amp;&amp; pipe-&gt;stream-&gt;timing.h_addressable == 1920)</div><div class='add'>+			disallow = true;</div><div class='add'>+	}</div><div class='add'>+	return disallow;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible</div><div class='ctx'>  *</div><div class='ctx'>  * @dc: Current DC state</div><div class='hunk'>@@ -688,21 +660,24 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	bool drr_pipe_found = false;</div><div class='ctx'> 	bool drr_psr_capable = false;</div><div class='ctx'> 	uint64_t refresh_rate = 0;</div><div class='add'>+	bool subvp_disallow = false;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		if (resource_is_pipe_type(pipe, OPP_HEAD) &amp;&amp;</div><div class='ctx'> 				resource_is_pipe_type(pipe, DPP_PIPE)) {</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+			if (pipe_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 				subvp_count++;</div><div class='ctx'> </div><div class='add'>+				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);</div><div class='ctx'> 				refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='ctx'> 					pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> 			}</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+			if (pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 				non_subvp_pipes++;</div><div class='ctx'> 				drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));</div><div class='ctx'> 				if (pipe-&gt;stream-&gt;ignore_msa_timing_param &amp;&amp;</div><div class='hunk'>@@ -713,7 +688,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (subvp_count == 1 &amp;&amp; non_subvp_pipes == 1 &amp;&amp; drr_pipe_found &amp;&amp; !drr_psr_capable &amp;&amp;</div><div class='add'>+	if (subvp_count == 1 &amp;&amp; !subvp_disallow &amp;&amp; non_subvp_pipes == 1 &amp;&amp; drr_pipe_found &amp;&amp; !drr_psr_capable &amp;&amp;</div><div class='ctx'> 		((uint32_t)refresh_rate &lt; 120))</div><div class='ctx'> 		result = true;</div><div class='ctx'> </div><div class='hunk'>@@ -746,21 +721,24 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int</div><div class='ctx'> 	struct vba_vars_st *vba = &amp;context-&gt;bw_ctx.dml.vba;</div><div class='ctx'> 	bool vblank_psr_capable = false;</div><div class='ctx'> 	uint64_t refresh_rate = 0;</div><div class='add'>+	bool subvp_disallow = false;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		if (resource_is_pipe_type(pipe, OPP_HEAD) &amp;&amp;</div><div class='ctx'> 				resource_is_pipe_type(pipe, DPP_PIPE)) {</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+			if (pipe_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 				subvp_count++;</div><div class='ctx'> </div><div class='add'>+				subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);</div><div class='ctx'> 				refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='ctx'> 					pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='ctx'> 				refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='ctx'> 			}</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+			if (pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 				non_subvp_pipes++;</div><div class='ctx'> 				vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));</div><div class='ctx'> 				if (pipe-&gt;stream-&gt;ignore_msa_timing_param &amp;&amp;</div><div class='hunk'>@@ -772,9 +750,35 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (subvp_count == 1 &amp;&amp; non_subvp_pipes == 1 &amp;&amp; !drr_pipe_found &amp;&amp; !vblank_psr_capable &amp;&amp;</div><div class='del'>-		((uint32_t)refresh_rate &lt; 120) &amp;&amp;</div><div class='add'>+		((uint32_t)refresh_rate &lt; 120) &amp;&amp; !subvp_disallow &amp;&amp;</div><div class='ctx'> 		vba-&gt;DRAMClockChangeSupport[vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)</div><div class='ctx'> 		result = true;</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,</div><div class='add'>+		display_e2e_pipe_params_st *pipes)</div><div class='add'>+{</div><div class='add'>+	int i, pipe_cnt;</div><div class='add'>+	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='add'>+	struct pipe_ctx *pipe = NULL;</div><div class='add'>+</div><div class='add'>+	for (i = 0, pipe_cnt = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		int odm_slice_count = 0;</div><div class='add'>+</div><div class='add'>+		if (!res_ctx-&gt;pipe_ctx[i].stream)</div><div class='add'>+			continue;</div><div class='add'>+		pipe = &amp;res_ctx-&gt;pipe_ctx[i];</div><div class='add'>+		odm_slice_count = resource_get_odm_slice_count(pipe);</div><div class='add'>+</div><div class='add'>+		if (odm_slice_count == 1)</div><div class='add'>+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;</div><div class='add'>+		else if (odm_slice_count == 2)</div><div class='add'>+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;</div><div class='add'>+		else if (odm_slice_count == 4)</div><div class='add'>+			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;</div><div class='add'>+</div><div class='add'>+		pipe_cnt++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/Makefile b/drivers/gpu/drm/amd/display/dc/dcn321/Makefile<br/>index 0a199c83bb5b..c195c47f58b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn321/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn321/Makefile</a></div><div class='hunk'>@@ -10,7 +10,7 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for dcn321.</div><div class='ctx'> </div><div class='del'>-DCN321 = dcn321_resource.o dcn321_dio_link_encoder.o</div><div class='add'>+DCN321 = dcn321_dio_link_encoder.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN321 = $(addprefix $(AMDDALPATH)/dc/dcn321/,$(DCN321))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/Makefile b/drivers/gpu/drm/amd/display/dc/dcn35/Makefile<br/>index 20d0eef1a13b..0e317e0c36a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/Makefile</a></div><div class='hunk'>@@ -10,9 +10,9 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for DCN35.</div><div class='ctx'> </div><div class='del'>-DCN35 = dcn35_resource.o dcn35_init.o dcn35_dio_stream_encoder.o \</div><div class='del'>-	dcn35_dio_link_encoder.o dcn35_dccg.o dcn35_optc.o \</div><div class='del'>-	dcn35_dsc.o dcn35_hubp.o dcn35_hubbub.o \</div><div class='add'>+DCN35 = dcn35_dio_stream_encoder.o \</div><div class='add'>+	dcn35_dio_link_encoder.o dcn35_dccg.o \</div><div class='add'>+	dcn35_hubp.o dcn35_hubbub.o \</div><div class='ctx'> 	dcn35_mmhubbub.o dcn35_opp.o dcn35_dpp.o dcn35_pg_cntl.o dcn35_dwb.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DCN35 = $(addprefix $(AMDDALPATH)/dc/dcn35/,$(DCN35))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c<br/>index 479f3683c0b7..f1ba7bb792ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c</a></div><div class='hunk'>@@ -256,6 +256,21 @@ static void dccg35_set_dtbclk_dto(</div><div class='ctx'> 	if (params-&gt;ref_dtbclk_khz &amp;&amp; req_dtbclk_khz) {</div><div class='ctx'> 		uint32_t modulo, phase;</div><div class='ctx'> </div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		// phase / modulo = dtbclk / dtbclk ref</div><div class='ctx'> 		modulo = params-&gt;ref_dtbclk_khz * 1000;</div><div class='ctx'> 		phase = req_dtbclk_khz * 1000;</div><div class='hunk'>@@ -280,6 +295,21 @@ static void dccg35_set_dtbclk_dto(</div><div class='ctx'> 		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='ctx'> 				PIPE_DTO_SRC_SEL[params-&gt;otg_inst], 2);</div><div class='ctx'> 	} else {</div><div class='add'>+		switch (params-&gt;otg_inst) {</div><div class='add'>+		case 0:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		case 3:</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params-&gt;otg_inst],</div><div class='ctx'> 				DTBCLK_DTO_ENABLE[params-&gt;otg_inst], 0,</div><div class='ctx'> 				PIPE_DTO_SRC_SEL[params-&gt;otg_inst], params-&gt;is_hdmi ? 0 : 1);</div><div class='hunk'>@@ -476,6 +506,64 @@ static void dccg35_dpp_root_clock_control(</div><div class='ctx'> 	dccg-&gt;dpp_clock_gated[dpp_inst] = !clock_on;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dccg35_disable_symclk32_se(</div><div class='add'>+		struct dccg *dccg,</div><div class='add'>+		int hpo_se_inst)</div><div class='add'>+{</div><div class='add'>+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);</div><div class='add'>+</div><div class='add'>+	/* set refclk as the source for symclk32_se */</div><div class='add'>+	switch (hpo_se_inst) {</div><div class='add'>+	case 0:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE0_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE0_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE0_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 1:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE1_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE1_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE1_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE2_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE2_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE2_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+		REG_UPDATE_2(SYMCLK32_SE_CNTL,</div><div class='add'>+				SYMCLK32_SE3_SRC_SEL, 0,</div><div class='add'>+				SYMCLK32_SE3_EN, 0);</div><div class='add'>+		if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_se) {</div><div class='add'>+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+					SYMCLK32_SE3_GATE_DISABLE, 0);</div><div class='add'>+//			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,</div><div class='add'>+//					SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void dccg35_init(struct dccg *dccg)</div><div class='ctx'> {</div><div class='ctx'> 	int otg_inst;</div><div class='hunk'>@@ -484,7 +572,7 @@ void dccg35_init(struct dccg *dccg)</div><div class='ctx'> 	 * will cause DCN to hang.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (otg_inst = 0; otg_inst &lt; 4; otg_inst++)</div><div class='del'>-		dccg31_disable_symclk32_se(dccg, otg_inst);</div><div class='add'>+		dccg35_disable_symclk32_se(dccg, otg_inst);</div><div class='ctx'> </div><div class='ctx'> 	if (dccg-&gt;ctx-&gt;dc-&gt;debug.root_clock_optimization.bits.symclk32_le)</div><div class='ctx'> 		for (otg_inst = 0; otg_inst &lt; 2; otg_inst++)</div><div class='hunk'>@@ -758,7 +846,7 @@ static const struct dccg_funcs dccg35_funcs = {</div><div class='ctx'> 	.dccg_init = dccg35_init,</div><div class='ctx'> 	.set_dpstreamclk = dccg35_set_dpstreamclk,</div><div class='ctx'> 	.enable_symclk32_se = dccg31_enable_symclk32_se,</div><div class='del'>-	.disable_symclk32_se = dccg31_disable_symclk32_se,</div><div class='add'>+	.disable_symclk32_se = dccg35_disable_symclk32_se,</div><div class='ctx'> 	.enable_symclk32_le = dccg31_enable_symclk32_le,</div><div class='ctx'> 	.disable_symclk32_le = dccg31_disable_symclk32_le,</div><div class='ctx'> 	.set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h<br/>index 423feb4c2f3f..1586a45ca3bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h</a></div><div class='hunk'>@@ -34,6 +34,8 @@</div><div class='ctx'> #define DCCG_REG_LIST_DCN35() \</div><div class='ctx'> 	DCCG_REG_LIST_DCN314(),\</div><div class='ctx'> 	SR(DPPCLK_CTRL),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL4),\</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL5),\</div><div class='ctx'> 	SR(DCCG_GATE_DISABLE_CNTL6),\</div><div class='ctx'> 	SR(DCCG_GLOBAL_FGCG_REP_CNTL),\</div><div class='ctx'> 	SR(SYMCLKA_CLOCK_ENABLE),\</div><div class='hunk'>@@ -174,7 +176,61 @@</div><div class='ctx'> 	DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\</div><div class='ctx'> 	DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\</div><div class='del'>-	DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh)</div><div class='add'>+	DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\</div><div class='add'>+	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\</div><div class='ctx'> </div><div class='ctx'> struct dccg *dccg35_create(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c<br/>index f91e08895275..da94e5309fba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c</a></div><div class='hunk'>@@ -256,6 +256,10 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;</div><div class='add'>+		if (bp_cap_info.DP_IS_USB_C) {</div><div class='add'>+			/*BIOS not switch to use CONNECTOR_ID_USBC = 24 yet*/</div><div class='add'>+			enc10-&gt;base.features.flags.bits.DP_IS_USB_C = 1;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",</div><div class='hunk'>@@ -264,4 +268,5 @@ void dcn35_link_encoder_construct(</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enc10-&gt;base.ctx-&gt;dc-&gt;debug.hdmi20_disable)</div><div class='ctx'> 		enc10-&gt;base.features.flags.bits.HDMI_6GB_EN = 0;</div><div class='add'>+</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c<br/>index 46f71ff08fd1..53bd0ae4bab5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c</a></div><div class='hunk'>@@ -261,6 +261,7 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)</div><div class='ctx'> 	uint32_t power_gate = power_on ? 0 : 1;</div><div class='ctx'> 	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='ctx'> 	uint32_t org_ip_request_cntl;</div><div class='add'>+	uint32_t power_forceon;</div><div class='ctx'> 	bool block_enabled;</div><div class='ctx'> </div><div class='ctx'> 	if (pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='hunk'>@@ -277,6 +278,10 @@ void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on)</div><div class='ctx'> 			return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &amp;power_forceon);</div><div class='add'>+	if (power_forceon)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='ctx'> 	if (org_ip_request_cntl == 0)</div><div class='ctx'> 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);</div><div class='hunk'>@@ -304,6 +309,7 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)</div><div class='ctx'> 	uint32_t power_gate = power_on ? 0 : 1;</div><div class='ctx'> 	uint32_t pwr_status = power_on ? 0 : 2;</div><div class='ctx'> 	uint32_t org_ip_request_cntl;</div><div class='add'>+	uint32_t power_forceon;</div><div class='ctx'> 	bool block_enabled;</div><div class='ctx'> </div><div class='ctx'> 	if (pg_cntl-&gt;ctx-&gt;dc-&gt;debug.ignore_pg ||</div><div class='hunk'>@@ -319,6 +325,10 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)</div><div class='ctx'> 			return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &amp;power_forceon);</div><div class='add'>+	if (power_forceon)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &amp;org_ip_request_cntl);</div><div class='ctx'> 	if (org_ip_request_cntl == 0)</div><div class='ctx'> 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);</div><div class='hunk'>@@ -332,13 +342,6 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)</div><div class='ctx'> 	pg_cntl-&gt;pg_res_enable[PG_DCIO] = power_on;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on)</div><div class='del'>-{</div><div class='del'>-	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);</div><div class='del'>-</div><div class='del'>-	REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, power_on ? 1 : 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)</div><div class='ctx'> {</div><div class='ctx'> 	struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);</div><div class='hunk'>@@ -508,8 +511,7 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = {</div><div class='ctx'> 	.mpcc_pg_control = pg_cntl35_mpcc_pg_control,</div><div class='ctx'> 	.opp_pg_control = pg_cntl35_opp_pg_control,</div><div class='ctx'> 	.optc_pg_control = pg_cntl35_optc_pg_control,</div><div class='del'>-	.dwb_pg_control = pg_cntl35_dwb_pg_control,</div><div class='del'>-	.set_force_poweron_domain22 = pg_cntl35_set_force_poweron_domain22</div><div class='add'>+	.dwb_pg_control = pg_cntl35_dwb_pg_control</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct pg_cntl *pg_cntl35_create(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h<br/>index 069dae08e222..3de240884d22 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h</a></div><div class='hunk'>@@ -183,7 +183,6 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,</div><div class='ctx'> 	unsigned int optc_inst, bool power_on);</div><div class='ctx'> void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);</div><div class='ctx'> void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);</div><div class='del'>-void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on);</div><div class='ctx'> </div><div class='ctx'> struct pg_cntl *pg_cntl35_create(</div><div class='ctx'> 	struct dc_context *ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h<br/>index 7ce9a5b6c33b..6d7a15dcf8a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dm_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dm_helpers.h</a></div><div class='hunk'>@@ -103,10 +103,16 @@ enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(</div><div class='ctx'> /*</div><div class='ctx'>  * Sends ALLOCATE_PAYLOAD message.</div><div class='ctx'>  */</div><div class='del'>-bool dm_helpers_dp_mst_send_payload_allocation(</div><div class='add'>+void dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='del'>-		const struct dc_stream_state *stream,</div><div class='del'>-		bool enable);</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Update mst manager relevant variables</div><div class='add'>+ */</div><div class='add'>+void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(</div><div class='add'>+		struct dc_context *ctx,</div><div class='add'>+		const struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> bool dm_helpers_dp_mst_start_top_mgr(</div><div class='ctx'> 		struct dc_context *ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h<br/>index 4440d08743aa..bd7ba0a25198 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dm_pp_smu.h</a></div><div class='hunk'>@@ -247,6 +247,7 @@ struct pp_smu_funcs_nv {</div><div class='ctx'> #define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4</div><div class='ctx'> #define PP_SMU_NUM_DCLK_DPM_LEVELS    8</div><div class='ctx'> #define PP_SMU_NUM_VCLK_DPM_LEVELS    8</div><div class='add'>+#define PP_SMU_NUM_VPECLK_DPM_LEVELS  8</div><div class='ctx'> </div><div class='ctx'> struct dpm_clock {</div><div class='ctx'>   uint32_t  Freq;    // In MHz</div><div class='hunk'>@@ -262,6 +263,7 @@ struct dpm_clocks {</div><div class='ctx'> 	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];</div><div class='ctx'> 	struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS];</div><div class='ctx'> 	struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS];</div><div class='add'>+	struct dpm_clock VPEClocks[PP_SMU_NUM_VPECLK_DPM_LEVELS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile<br/>index ea7d60f9a9b4..6042a5a6a44f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/Makefile</a></div><div class='hunk'>@@ -61,8 +61,12 @@ endif</div><div class='ctx'> endif</div><div class='ctx'> </div><div class='ctx'> ifneq ($(CONFIG_FRAME_WARN),0)</div><div class='add'>+ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)</div><div class='add'>+frame_warn_flag := -Wframe-larger-than=3072</div><div class='add'>+else</div><div class='ctx'> frame_warn_flag := -Wframe-larger-than=2048</div><div class='ctx'> endif</div><div class='add'>+endif</div><div class='ctx'> </div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)</div><div class='ctx'> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c<br/>index 50b0434354f8..0c4a8fe8e5ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c</a></div><div class='hunk'>@@ -30,7 +30,7 @@</div><div class='ctx'> #include "dcn_calc_auto.h"</div><div class='ctx'> #include "dal_asic_id.h"</div><div class='ctx'> #include "resource.h"</div><div class='del'>-#include "dcn10/dcn10_resource.h"</div><div class='add'>+#include "resource/dcn10/dcn10_resource.h"</div><div class='ctx'> #include "dcn10/dcn10_hubbub.h"</div><div class='ctx'> #include "dml/dml1_display_rq_dlg_calc.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h<br/>index 2cbdd75429ff..6e669a2c5b2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dc_features.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dc_features.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dc_features.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dc_features.h</a></div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'>  * Define the maximum amount of states supported by the ASIC. Every ASIC has a</div><div class='ctx'>  * specific number of states; this macro defines the maximum number of states.</div><div class='ctx'>  */</div><div class='del'>-#define DC__VOLTAGE_STATES 20</div><div class='add'>+#define DC__VOLTAGE_STATES 40</div><div class='ctx'> #define DC__NUM_DPP__4 1</div><div class='ctx'> #define DC__NUM_DPP__0_PRESENT 1</div><div class='ctx'> #define DC__NUM_DPP__1_PRESENT 1</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c<br/>index 7fc8b18096ba..38ab9ad60ef8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "link.h"</div><div class='ctx'> #include "dcn20_fpu.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc-&gt;ctx-&gt;logger</div><div class='hunk'>@@ -440,7 +441,115 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {</div><div class='ctx'> 	.use_urgent_burst_bw = 0</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };</div><div class='add'>+struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = {</div><div class='add'>+	.clock_limits = {</div><div class='add'>+		{</div><div class='add'>+			.state = 0,</div><div class='add'>+			.dcfclk_mhz = 560.0,</div><div class='add'>+			.fabricclk_mhz = 560.0,</div><div class='add'>+			.dispclk_mhz = 513.0,</div><div class='add'>+			.dppclk_mhz = 513.0,</div><div class='add'>+			.phyclk_mhz = 540.0,</div><div class='add'>+			.socclk_mhz = 560.0,</div><div class='add'>+			.dscclk_mhz = 171.0,</div><div class='add'>+			.dram_speed_mts = 1069.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 1,</div><div class='add'>+			.dcfclk_mhz = 694.0,</div><div class='add'>+			.fabricclk_mhz = 694.0,</div><div class='add'>+			.dispclk_mhz = 642.0,</div><div class='add'>+			.dppclk_mhz = 642.0,</div><div class='add'>+			.phyclk_mhz = 600.0,</div><div class='add'>+			.socclk_mhz = 694.0,</div><div class='add'>+			.dscclk_mhz = 214.0,</div><div class='add'>+			.dram_speed_mts = 1324.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 2,</div><div class='add'>+			.dcfclk_mhz = 875.0,</div><div class='add'>+			.fabricclk_mhz = 875.0,</div><div class='add'>+			.dispclk_mhz = 734.0,</div><div class='add'>+			.dppclk_mhz = 734.0,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.socclk_mhz = 875.0,</div><div class='add'>+			.dscclk_mhz = 245.0,</div><div class='add'>+			.dram_speed_mts = 1670.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 3,</div><div class='add'>+			.dcfclk_mhz = 1000.0,</div><div class='add'>+			.fabricclk_mhz = 1000.0,</div><div class='add'>+			.dispclk_mhz = 1100.0,</div><div class='add'>+			.dppclk_mhz = 1100.0,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.socclk_mhz = 1000.0,</div><div class='add'>+			.dscclk_mhz = 367.0,</div><div class='add'>+			.dram_speed_mts = 2000.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 4,</div><div class='add'>+			.dcfclk_mhz = 1200.0,</div><div class='add'>+			.fabricclk_mhz = 1200.0,</div><div class='add'>+			.dispclk_mhz = 1284.0,</div><div class='add'>+			.dppclk_mhz = 1284.0,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.socclk_mhz = 1200.0,</div><div class='add'>+			.dscclk_mhz = 428.0,</div><div class='add'>+			.dram_speed_mts = 2000.0,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.state = 5,</div><div class='add'>+			.dcfclk_mhz = 1200.0,</div><div class='add'>+			.fabricclk_mhz = 1200.0,</div><div class='add'>+			.dispclk_mhz = 1284.0,</div><div class='add'>+			.dppclk_mhz = 1284.0,</div><div class='add'>+			.phyclk_mhz = 810.0,</div><div class='add'>+			.socclk_mhz = 1200.0,</div><div class='add'>+			.dscclk_mhz = 428.0,</div><div class='add'>+			.dram_speed_mts = 2000.0,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	.num_states = 5,</div><div class='add'>+	.sr_exit_time_us = 1.9,</div><div class='add'>+	.sr_enter_plus_exit_time_us = 4.4,</div><div class='add'>+	.urgent_latency_us = 3.0,</div><div class='add'>+	.urgent_latency_pixel_data_only_us = 4.0,</div><div class='add'>+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,</div><div class='add'>+	.urgent_latency_vm_data_only_us = 4.0,</div><div class='add'>+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,</div><div class='add'>+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,</div><div class='add'>+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,</div><div class='add'>+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,</div><div class='add'>+	.max_avg_sdp_bw_use_normal_percent = 40.0,</div><div class='add'>+	.max_avg_dram_bw_use_normal_percent = 40.0,</div><div class='add'>+	.writeback_latency_us = 12.0,</div><div class='add'>+	.ideal_dram_bw_after_urgent_percent = 40.0,</div><div class='add'>+	.max_request_size_bytes = 256,</div><div class='add'>+	.dram_channel_width_bytes = 16,</div><div class='add'>+	.fabric_datapath_to_dcn_data_return_bytes = 64,</div><div class='add'>+	.dcn_downspread_percent = 0.5,</div><div class='add'>+	.downspread_percent = 0.5,</div><div class='add'>+	.dram_page_open_time_ns = 50.0,</div><div class='add'>+	.dram_rw_turnaround_time_ns = 17.5,</div><div class='add'>+	.dram_return_buffer_per_channel_bytes = 8192,</div><div class='add'>+	.round_trip_ping_latency_dcfclk_cycles = 131,</div><div class='add'>+	.urgent_out_of_order_return_per_channel_bytes = 4096,</div><div class='add'>+	.channel_interleave_bytes = 256,</div><div class='add'>+	.num_banks = 8,</div><div class='add'>+	.num_chans = 16,</div><div class='add'>+	.vmm_page_size_bytes = 4096,</div><div class='add'>+	.dram_clock_change_latency_us = 45.0,</div><div class='add'>+	.writeback_dram_clock_change_latency_us = 23.0,</div><div class='add'>+	.return_bus_width_bytes = 64,</div><div class='add'>+	.dispclk_dppclk_vco_speed_mhz = 3850,</div><div class='add'>+	.xfc_bus_transport_time_us = 20,</div><div class='add'>+	.xfc_xbuf_latency_tolerance_us = 50,</div><div class='add'>+	.use_urgent_burst_bw = 0,</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct _vcs_dpi_ip_params_st dcn2_1_ip = {</div><div class='ctx'> 	.odm_capable = 1,</div><div class='hunk'>@@ -950,10 +1059,8 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc</div><div class='ctx'> {</div><div class='ctx'> 	int plane_count;</div><div class='ctx'> 	int i;</div><div class='del'>-	unsigned int min_dst_y_next_start_us;</div><div class='ctx'> </div><div class='ctx'> 	plane_count = 0;</div><div class='del'>-	min_dst_y_next_start_us = 0;</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='ctx'> 			plane_count++;</div><div class='hunk'>@@ -975,26 +1082,15 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc</div><div class='ctx'> 	else if (context-&gt;stream_count == 1 &amp;&amp;  context-&gt;streams[0]-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='ctx'> 		struct dc_link *link = context-&gt;streams[0]-&gt;sink-&gt;link;</div><div class='ctx'> 		struct dc_stream_status *stream_status = &amp;context-&gt;stream_status[0];</div><div class='del'>-		struct dc_stream_state *current_stream = context-&gt;streams[0];</div><div class='ctx'> 		int minmum_z8_residency = dc-&gt;debug.minimum_z8_residency_time &gt; 0 ? dc-&gt;debug.minimum_z8_residency_time : 1000;</div><div class='ctx'> 		bool allow_z8 = context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; (double)minmum_z8_residency;</div><div class='ctx'> 		bool is_pwrseq0 = link-&gt;link_index == 0;</div><div class='del'>-		bool isFreesyncVideo;</div><div class='del'>-</div><div class='del'>-		isFreesyncVideo = current_stream-&gt;adjust.v_total_min == current_stream-&gt;adjust.v_total_max;</div><div class='del'>-		isFreesyncVideo = isFreesyncVideo &amp;&amp; current_stream-&gt;timing.v_total &lt; current_stream-&gt;adjust.v_total_min;</div><div class='del'>-		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-			if (context-&gt;res_ctx.pipe_ctx[i].stream == current_stream &amp;&amp; isFreesyncVideo) {</div><div class='del'>-				min_dst_y_next_start_us = context-&gt;res_ctx.pipe_ctx[i].dlg_regs.min_dst_y_next_start_us;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		/* Don't support multi-plane configurations */</div><div class='ctx'> 		if (stream_status-&gt;plane_count &gt; 1)</div><div class='ctx'> 			return DCN_ZSTATE_SUPPORT_DISALLOW;</div><div class='ctx'> </div><div class='del'>-		if (is_pwrseq0 &amp;&amp; (context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; 5000.0 || min_dst_y_next_start_us &gt; 5000))</div><div class='add'>+		if (is_pwrseq0 &amp;&amp; context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; 5000.0)</div><div class='ctx'> 			return DCN_ZSTATE_SUPPORT_ALLOW;</div><div class='ctx'> 		else if (is_pwrseq0 &amp;&amp; link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1 &amp;&amp; !link-&gt;panel_config.psr.disable_psr)</div><div class='ctx'> 			return allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;</div><div class='hunk'>@@ -1087,7 +1183,7 @@ void dcn20_calculate_dlg_params(struct dc *dc,</div><div class='ctx'> 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt, pipe_idx);</div><div class='ctx'> 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt, pipe_idx);</div><div class='ctx'> </div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {</div><div class='ctx'> 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[i].unbounded_req = false;</div><div class='hunk'>@@ -1437,7 +1533,7 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc,</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (res_ctx-&gt;pipe_ctx[i].plane_state &amp;&amp;</div><div class='ctx'> 				(res_ctx-&gt;pipe_ctx[i].plane_state-&gt;address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||</div><div class='del'>-				 res_ctx-&gt;pipe_ctx[i].stream-&gt;mall_stream_config.type == SUBVP_PHANTOM))</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, &amp;res_ctx-&gt;pipe_ctx[i]) == SUBVP_PHANTOM))</div><div class='ctx'> 			pipes[pipe_cnt].pipe.src.num_cursors = 0;</div><div class='ctx'> 		else</div><div class='ctx'> 			pipes[pipe_cnt].pipe.src.num_cursors = dc-&gt;dml.ip.number_of_cursors;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c<br/>index 3686f1e7de3a..63c48c29ba49 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c</a></div><div class='hunk'>@@ -3542,7 +3542,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> {</div><div class='ctx'> 	struct vba_vars_st *v = &amp;mode_lib-&gt;vba;</div><div class='ctx'> 	int MinPrefetchMode, MaxPrefetchMode;</div><div class='del'>-	int i;</div><div class='add'>+	int i, start_state;</div><div class='ctx'> 	unsigned int j, k, m;</div><div class='ctx'> 	bool   EnoughWritebackUnits = true;</div><div class='ctx'> 	bool   WritebackModeSupport = true;</div><div class='hunk'>@@ -3553,6 +3553,11 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> </div><div class='ctx'> 	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/</div><div class='ctx'> </div><div class='add'>+	if (mode_lib-&gt;validate_max_state)</div><div class='add'>+		start_state = v-&gt;soc.num_states - 1;</div><div class='add'>+	else</div><div class='add'>+		start_state = 0;</div><div class='add'>+</div><div class='ctx'> 	CalculateMinAndMaxPrefetchMode(</div><div class='ctx'> 		mode_lib-&gt;vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,</div><div class='ctx'> 		&amp;MinPrefetchMode, &amp;MaxPrefetchMode);</div><div class='hunk'>@@ -3851,7 +3856,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 			v-&gt;SingleDPPViewportSizeSupportPerPlane,</div><div class='ctx'> 			&amp;v-&gt;ViewportSizeSupport[0][0]);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; 2; j++) {</div><div class='ctx'> 			v-&gt;MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v-&gt;MaxDispclk[i], v-&gt;DISPCLKDPPCLKVCOSpeed);</div><div class='ctx'> 			v-&gt;MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v-&gt;MaxDppclk[i], v-&gt;DISPCLKDPPCLKVCOSpeed);</div><div class='hunk'>@@ -4007,7 +4012,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> </div><div class='ctx'> 	/*Total Available Pipes Support Check*/</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; 2; j++) {</div><div class='ctx'> 			if (v-&gt;TotalNumberOfActiveDPP[i][j] &lt;= v-&gt;MaxNumDPP) {</div><div class='ctx'> 				v-&gt;TotalAvailablePipesSupport[i][j] = true;</div><div class='hunk'>@@ -4046,7 +4051,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='ctx'> 			v-&gt;RequiresDSC[i][k] = false;</div><div class='ctx'> 			v-&gt;RequiresFEC[i][k] = false;</div><div class='hunk'>@@ -4174,7 +4179,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		v-&gt;DIOSupport[i] = true;</div><div class='ctx'> 		for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='ctx'> 			if (!v-&gt;skip_dio_check[k] &amp;&amp; v-&gt;BlendingAndTiming[k] == k &amp;&amp; (v-&gt;Output[k] == dm_dp || v-&gt;Output[k] == dm_edp || v-&gt;Output[k] == dm_hdmi)</div><div class='hunk'>@@ -4185,7 +4190,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; ++i) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; ++i) {</div><div class='ctx'> 		v-&gt;ODMCombine4To1SupportCheckOK[i] = true;</div><div class='ctx'> 		for (k = 0; k &lt; v-&gt;NumberOfActivePlanes; ++k) {</div><div class='ctx'> 			if (v-&gt;BlendingAndTiming[k] == k &amp;&amp; v-&gt;ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1</div><div class='hunk'>@@ -4197,7 +4202,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> </div><div class='ctx'> 	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		v-&gt;NotEnoughDSCUnits[i] = false;</div><div class='ctx'> 		v-&gt;TotalDSCUnitsRequired = 0.0;</div><div class='ctx'> 		for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='hunk'>@@ -4217,7 +4222,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 	}</div><div class='ctx'> 	/*DSC Delay per state*/</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='ctx'> 			if (v-&gt;OutputBppPerState[i][k] == BPP_INVALID) {</div><div class='ctx'> 				v-&gt;BPP = 0.0;</div><div class='hunk'>@@ -4333,7 +4338,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 		v-&gt;cursor_bw[k] = v-&gt;NumberOfCursors[k] * v-&gt;CursorWidth[k][0] * v-&gt;CursorBPP[k][0] / 8.0 / (v-&gt;HTotal[k] / v-&gt;PixelClock[k]) * v-&gt;VRatio[k];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; 2; j++) {</div><div class='ctx'> 			for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='ctx'> 				v-&gt;swath_width_luma_ub_this_state[k] = v-&gt;swath_width_luma_ub_all_states[i][j][k];</div><div class='hunk'>@@ -5075,7 +5080,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> </div><div class='ctx'> 	/*PTE Buffer Size Check*/</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; v-&gt;soc.num_states; i++) {</div><div class='add'>+	for (i = start_state; i &lt; v-&gt;soc.num_states; i++) {</div><div class='ctx'> 		for (j = 0; j &lt; 2; j++) {</div><div class='ctx'> 			v-&gt;PTEBufferSizeNotExceeded[i][j] = true;</div><div class='ctx'> 			for (k = 0; k &lt;= v-&gt;NumberOfActivePlanes - 1; k++) {</div><div class='hunk'>@@ -5136,7 +5141,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 	}</div><div class='ctx'> 	/*Mode Support, Voltage State and SOC Configuration*/</div><div class='ctx'> </div><div class='del'>-	for (i = v-&gt;soc.num_states - 1; i &gt;= 0; i--) {</div><div class='add'>+	for (i = v-&gt;soc.num_states - 1; i &gt;= start_state; i--) {</div><div class='ctx'> 		for (j = 0; j &lt; 2; j++) {</div><div class='ctx'> 			if (v-&gt;ScaleRatioAndTapsSupport == 1 &amp;&amp; v-&gt;SourceFormatPixelAndScanSupport == 1 &amp;&amp; v-&gt;ViewportSizeSupport[i][j] == 1</div><div class='ctx'> 					&amp;&amp; v-&gt;DIOSupport[i] == 1 &amp;&amp; v-&gt;ODMCombine4To1SupportCheckOK[i] == 1</div><div class='hunk'>@@ -5158,7 +5163,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 	}</div><div class='ctx'> 	{</div><div class='ctx'> 		unsigned int MaximumMPCCombine = 0;</div><div class='del'>-		for (i = v-&gt;soc.num_states; i &gt;= 0; i--) {</div><div class='add'>+		for (i = v-&gt;soc.num_states; i &gt;= start_state; i--) {</div><div class='ctx'> 			if (i == v-&gt;soc.num_states || v-&gt;ModeSupport[i][0] == true || v-&gt;ModeSupport[i][1] == true) {</div><div class='ctx'> 				v-&gt;VoltageLevel = i;</div><div class='ctx'> 				v-&gt;ModeIsSupported = v-&gt;ModeSupport[i][0] == true || v-&gt;ModeSupport[i][1] == true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c<br/>index 9ec4172d1c2d..9f37f717a1f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@</div><div class='ctx'> #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"</div><div class='ctx'> #include "dcn30/dcn30_resource.h"</div><div class='ctx'> #include "link.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -45,6 +46,14 @@ static const struct subvp_high_refresh_list subvp_high_refresh_list = {</div><div class='ctx'> 				{.width = 1920, .height = 1080, }},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct subvp_active_margin_list subvp_active_margin_list = {</div><div class='add'>+			.min_refresh = 55,</div><div class='add'>+			.max_refresh = 65,</div><div class='add'>+			.res = {</div><div class='add'>+				{.width = 2560, .height = 1440, },</div><div class='add'>+				{.width = 1920, .height = 1080, }},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct _vcs_dpi_ip_params_st dcn3_2_ip = {</div><div class='ctx'> 	.gpuvm_enable = 0,</div><div class='ctx'> 	.gpuvm_max_page_table_levels = 4,</div><div class='hunk'>@@ -333,7 +342,7 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,</div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			pipes[pipe_idx].pipe.dest.vstartup_start =</div><div class='ctx'> 				get_vstartup(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt, pipe_idx);</div><div class='ctx'> 			pipes[pipe_idx].pipe.dest.vupdate_offset =</div><div class='hunk'>@@ -616,7 +625,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !dcn32_is_center_timing(pipe) &amp;&amp;</div><div class='ctx'> 				!(pipe-&gt;stream-&gt;timing.pix_clk_100hz / 10000 &gt; DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &amp;&amp;</div><div class='ctx'> 				(!dcn32_is_psr_capable(pipe) || (context-&gt;stream_count == 1 &amp;&amp; dc-&gt;caps.dmub_caps.subvp_psr)) &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE &amp;&amp;</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &amp;&amp;</div><div class='ctx'> 				(refresh_rate &lt; 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &amp;&amp;</div><div class='ctx'> 				!pipe-&gt;plane_state-&gt;address.tmz_surface &amp;&amp;</div><div class='ctx'> 				(vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &lt;= 0 ||</div><div class='hunk'>@@ -674,7 +683,7 @@ static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context</div><div class='ctx'> </div><div class='ctx'> 		// Find the minimum pipe split count for non SubVP pipes</div><div class='ctx'> 		if (resource_is_pipe_type(pipe, OPP_HEAD) &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE) {</div><div class='ctx'> 			split_cnt = 0;</div><div class='ctx'> 			while (pipe) {</div><div class='ctx'> 				split_cnt++;</div><div class='hunk'>@@ -727,8 +736,8 @@ static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='del'>-			phantom = pipe-&gt;stream-&gt;mall_stream_config.paired_stream;</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='add'>+			phantom = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='ctx'> 			microschedule_lines = (phantom-&gt;timing.v_total - phantom-&gt;timing.v_front_porch) +</div><div class='ctx'> 					phantom-&gt;timing.v_addressable;</div><div class='ctx'> </div><div class='hunk'>@@ -796,6 +805,9 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	int16_t stretched_drr_us = 0;</div><div class='ctx'> 	int16_t drr_stretched_vblank_us = 0;</div><div class='ctx'> 	int16_t max_vblank_mallregion = 0;</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+	bool subvp_found = false;</div><div class='add'>+	bool drr_found = false;</div><div class='ctx'> </div><div class='ctx'> 	// Find SubVP pipe</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -808,8 +820,10 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		// Find the SubVP pipe</div><div class='del'>-		if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='add'>+			subvp_found = true;</div><div class='ctx'> 			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// Find the DRR pipe</div><div class='hunk'>@@ -817,32 +831,37 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		drr_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		// We check for master pipe only</div><div class='del'>-		if (!resource_is_pipe_type(pipe, OTG_MASTER) ||</div><div class='del'>-				!resource_is_pipe_type(pipe, DPP_PIPE))</div><div class='add'>+		if (!resource_is_pipe_type(drr_pipe, OTG_MASTER) ||</div><div class='add'>+				!resource_is_pipe_type(drr_pipe, DPP_PIPE))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (drr_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE &amp;&amp; drr_pipe-&gt;stream-&gt;ignore_msa_timing_param &amp;&amp;</div><div class='del'>-				(drr_pipe-&gt;stream-&gt;allow_freesync || drr_pipe-&gt;stream-&gt;vrr_active_variable || drr_pipe-&gt;stream-&gt;vrr_active_fixed))</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, drr_pipe) == SUBVP_NONE &amp;&amp; drr_pipe-&gt;stream-&gt;ignore_msa_timing_param &amp;&amp;</div><div class='add'>+				(drr_pipe-&gt;stream-&gt;allow_freesync || drr_pipe-&gt;stream-&gt;vrr_active_variable || drr_pipe-&gt;stream-&gt;vrr_active_fixed)) {</div><div class='add'>+			drr_found = true;</div><div class='ctx'> 			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	main_timing = &amp;pipe-&gt;stream-&gt;timing;</div><div class='del'>-	phantom_timing = &amp;pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='del'>-	drr_timing = &amp;drr_pipe-&gt;stream-&gt;timing;</div><div class='del'>-	prefetch_us = (phantom_timing-&gt;v_total - phantom_timing-&gt;v_front_porch) * phantom_timing-&gt;h_total /</div><div class='del'>-			(double)(phantom_timing-&gt;pix_clk_100hz * 100) * 1000000 +</div><div class='del'>-			dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='del'>-	subvp_active_us = main_timing-&gt;v_addressable * main_timing-&gt;h_total /</div><div class='del'>-			(double)(main_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='del'>-	drr_frame_us = drr_timing-&gt;v_total * drr_timing-&gt;h_total /</div><div class='del'>-			(double)(drr_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='del'>-	// P-State allow width and FW delays already included phantom_timing-&gt;v_addressable</div><div class='del'>-	mall_region_us = phantom_timing-&gt;v_addressable * phantom_timing-&gt;h_total /</div><div class='del'>-			(double)(phantom_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='del'>-	stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;</div><div class='del'>-	drr_stretched_vblank_us = (drr_timing-&gt;v_total - drr_timing-&gt;v_addressable) * drr_timing-&gt;h_total /</div><div class='del'>-			(double)(drr_timing-&gt;pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);</div><div class='del'>-	max_vblank_mallregion = drr_stretched_vblank_us &gt; mall_region_us ? drr_stretched_vblank_us : mall_region_us;</div><div class='add'>+	if (subvp_found &amp;&amp; drr_found) {</div><div class='add'>+		phantom_stream = dc_state_get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='add'>+		main_timing = &amp;pipe-&gt;stream-&gt;timing;</div><div class='add'>+		phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='add'>+		drr_timing = &amp;drr_pipe-&gt;stream-&gt;timing;</div><div class='add'>+		prefetch_us = (phantom_timing-&gt;v_total - phantom_timing-&gt;v_front_porch) * phantom_timing-&gt;h_total /</div><div class='add'>+				(double)(phantom_timing-&gt;pix_clk_100hz * 100) * 1000000 +</div><div class='add'>+				dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='add'>+		subvp_active_us = main_timing-&gt;v_addressable * main_timing-&gt;h_total /</div><div class='add'>+				(double)(main_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='add'>+		drr_frame_us = drr_timing-&gt;v_total * drr_timing-&gt;h_total /</div><div class='add'>+				(double)(drr_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='add'>+		// P-State allow width and FW delays already included phantom_timing-&gt;v_addressable</div><div class='add'>+		mall_region_us = phantom_timing-&gt;v_addressable * phantom_timing-&gt;h_total /</div><div class='add'>+				(double)(phantom_timing-&gt;pix_clk_100hz * 100) * 1000000;</div><div class='add'>+		stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;</div><div class='add'>+		drr_stretched_vblank_us = (drr_timing-&gt;v_total - drr_timing-&gt;v_addressable) * drr_timing-&gt;h_total /</div><div class='add'>+				(double)(drr_timing-&gt;pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);</div><div class='add'>+		max_vblank_mallregion = drr_stretched_vblank_us &gt; mall_region_us ? drr_stretched_vblank_us : mall_region_us;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the</div><div class='ctx'> 	 * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis</div><div class='hunk'>@@ -887,6 +906,8 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *phantom_timing = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *vblank_timing = NULL;</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+	enum mall_stream_type pipe_mall_type;</div><div class='ctx'> </div><div class='ctx'> 	/* For SubVP + VBLANK/DRR cases, we assume there can only be</div><div class='ctx'> 	 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK</div><div class='hunk'>@@ -896,6 +917,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		// We check for master pipe, but it shouldn't matter since we only need</div><div class='ctx'> 		// the pipe for timing info (stream should be same for any pipe splits)</div><div class='hunk'>@@ -903,18 +925,19 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 				!resource_is_pipe_type(pipe, DPP_PIPE))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (!found &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+		if (!found &amp;&amp; pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 			// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).</div><div class='ctx'> 			vblank_index = i;</div><div class='ctx'> 			found = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!subvp_pipe &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+		if (!subvp_pipe &amp;&amp; pipe_mall_type == SUBVP_MAIN)</div><div class='ctx'> 			subvp_pipe = pipe;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (found) {</div><div class='add'>+		phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 		main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-		phantom_timing = &amp;subvp_pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+		phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 		vblank_timing = &amp;context-&gt;res_ctx.pipe_ctx[vblank_index].stream-&gt;timing;</div><div class='ctx'> 		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe</div><div class='ctx'> 		// Also include the prefetch end to mallstart delay time</div><div class='hunk'>@@ -969,7 +992,7 @@ static bool subvp_subvp_admissable(struct dc *dc,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='ctx'> 			refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='ctx'> 				pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='ctx'> 			refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='hunk'>@@ -1018,23 +1041,23 @@ static bool subvp_validate_static_schedulability(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe) {</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+			if (pipe_mall_type == SUBVP_MAIN)</div><div class='ctx'> 				subvp_count++;</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+			if (pipe_mall_type == SUBVP_NONE)</div><div class='ctx'> 				non_subvp_pipes++;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		// Count how many planes that aren't SubVP/phantom are capable of VACTIVE</div><div class='ctx'> 		// switching (SubVP + VACTIVE unsupported). In situations where we force</div><div class='ctx'> 		// SubVP for a VACTIVE plane, we don't want to increment the vactive_count.</div><div class='ctx'> 		if (vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &gt; 0 &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+				pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 			vactive_count++;</div><div class='ctx'> 		}</div><div class='ctx'> 		pipe_idx++;</div><div class='hunk'>@@ -1070,7 +1093,7 @@ static void assign_subvp_index(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &amp;&amp;</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {</div><div class='ctx'> 			pipe_ctx-&gt;subvp_index = index++;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			pipe_ctx-&gt;subvp_index = 0;</div><div class='hunk'>@@ -1192,13 +1215,16 @@ static bool update_pipe_slice_table_with_split_flags(</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='ctx'> 	bool odm;</div><div class='del'>-	int i;</div><div class='add'>+	int dc_pipe_idx, dml_pipe_idx = 0;</div><div class='ctx'> 	bool updated = false;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+	for (dc_pipe_idx = 0;</div><div class='add'>+			dc_pipe_idx &lt; dc-&gt;res_pool-&gt;pipe_count; dc_pipe_idx++) {</div><div class='add'>+		pipe = &amp;context-&gt;res_ctx.pipe_ctx[dc_pipe_idx];</div><div class='add'>+		if (resource_is_pipe_type(pipe, FREE_PIPE))</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-		if (merge[i]) {</div><div class='add'>+		if (merge[dc_pipe_idx]) {</div><div class='ctx'> 			if (resource_is_pipe_type(pipe, OPP_HEAD))</div><div class='ctx'> 				/* merging OPP head means reducing ODM slice</div><div class='ctx'> 				 * count by 1</div><div class='hunk'>@@ -1213,17 +1239,18 @@ static bool update_pipe_slice_table_with_split_flags(</div><div class='ctx'> 			updated = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (split[i]) {</div><div class='del'>-			odm = vba-&gt;ODMCombineEnabled[vba-&gt;pipe_plane[i]] !=</div><div class='add'>+		if (split[dc_pipe_idx]) {</div><div class='add'>+			odm = vba-&gt;ODMCombineEnabled[vba-&gt;pipe_plane[dml_pipe_idx]] !=</div><div class='ctx'> 					dm_odm_combine_mode_disabled;</div><div class='ctx'> 			if (odm &amp;&amp; resource_is_pipe_type(pipe, OPP_HEAD))</div><div class='ctx'> 				update_slice_table_for_stream(</div><div class='del'>-						table, pipe-&gt;stream, split[i] - 1);</div><div class='add'>+						table, pipe-&gt;stream, split[dc_pipe_idx] - 1);</div><div class='ctx'> 			else if (!odm &amp;&amp; resource_is_pipe_type(pipe, DPP_PIPE))</div><div class='ctx'> 				update_slice_table_for_plane(table, pipe,</div><div class='del'>-						pipe-&gt;plane_state, split[i] - 1);</div><div class='add'>+						pipe-&gt;plane_state, split[dc_pipe_idx] - 1);</div><div class='ctx'> 			updated = true;</div><div class='ctx'> 		}</div><div class='add'>+		dml_pipe_idx++;</div><div class='ctx'> 	}</div><div class='ctx'> 	return updated;</div><div class='ctx'> }</div><div class='hunk'>@@ -1233,15 +1260,11 @@ static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *contex</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; table-&gt;odm_combine_count; i++) {</div><div class='add'>+	for (i = 0; i &lt; table-&gt;odm_combine_count; i++)</div><div class='ctx'> 		resource_update_pipes_for_stream_with_slice_count(context,</div><div class='ctx'> 				dc-&gt;current_state, dc-&gt;res_pool,</div><div class='ctx'> 				table-&gt;odm_combines[i].stream,</div><div class='ctx'> 				table-&gt;odm_combines[i].slice_count);</div><div class='del'>-		/* TODO: move this into the function above */</div><div class='del'>-		dcn20_build_mapped_resource(dc, context,</div><div class='del'>-				table-&gt;odm_combines[i].stream);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; table-&gt;mpc_combine_count; i++)</div><div class='ctx'> 		resource_update_pipes_for_plane_with_slice_count(context,</div><div class='hunk'>@@ -1408,6 +1431,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 	unsigned int dc_pipe_idx = 0;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	bool found_supported_config = false;</div><div class='add'>+	int vlevel_temp = 0;</div><div class='ctx'> </div><div class='ctx'> 	dc_assert_fp_enabled();</div><div class='ctx'> </div><div class='hunk'>@@ -1440,13 +1464,15 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!dc-&gt;debug.force_disable_subvp &amp;&amp; !dc-&gt;caps.dmub_caps.gecc_enable &amp;&amp; dcn32_all_pipes_have_stream_and_plane(dc, context) &amp;&amp;</div><div class='ctx'> 	    !dcn32_mpo_in_use(context) &amp;&amp; !dcn32_any_surfaces_rotated(dc, context) &amp;&amp; !is_test_pattern_enabled(context) &amp;&amp;</div><div class='del'>-		(*vlevel == context-&gt;bw_ctx.dml.soc.num_states ||</div><div class='add'>+		(*vlevel == context-&gt;bw_ctx.dml.soc.num_states || (vba-&gt;DRAMSpeedPerState[*vlevel] != vba-&gt;DRAMSpeedPerState[0] &amp;&amp;</div><div class='add'>+				vba-&gt;DRAMClockChangeSupport[*vlevel][vba-&gt;maxMpcComb] != dm_dram_clock_change_unsupported) ||</div><div class='ctx'> 	    vba-&gt;DRAMClockChangeSupport[*vlevel][vba-&gt;maxMpcComb] == dm_dram_clock_change_unsupported ||</div><div class='ctx'> 	    dc-&gt;debug.force_subvp_mclk_switch)) {</div><div class='ctx'> </div><div class='ctx'> 		dcn32_merge_pipes_for_subvp(dc, context);</div><div class='ctx'> 		memset(merge, 0, MAX_PIPES * sizeof(bool));</div><div class='ctx'> </div><div class='add'>+		vlevel_temp = *vlevel;</div><div class='ctx'> 		/* to re-initialize viewport after the pipe merge */</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='hunk'>@@ -1515,10 +1541,14 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (vba-&gt;DRAMSpeedPerState[*vlevel] &gt;= vba-&gt;DRAMSpeedPerState[vlevel_temp])</div><div class='add'>+			found_supported_config = false;</div><div class='add'>+</div><div class='ctx'> 		// If SubVP pipe config is unsupported (or cannot be used for UCLK switching)</div><div class='ctx'> 		// remove phantom pipes and repopulate dml pipes</div><div class='ctx'> 		if (!found_supported_config) {</div><div class='del'>-			dc-&gt;res_pool-&gt;funcs-&gt;remove_phantom_pipes(dc, context, false);</div><div class='add'>+			dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='add'>+			dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='ctx'> 			vba-&gt;DRAMClockChangeSupport[*vlevel][vba-&gt;maxMpcComb] = dm_dram_clock_change_unsupported;</div><div class='ctx'> 			*pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, false);</div><div class='ctx'> </div><div class='hunk'>@@ -1670,7 +1700,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt,</div><div class='ctx'> 				pipe_idx);</div><div class='ctx'> </div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {</div><div class='ctx'> 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[i].unbounded_req = false;</div><div class='hunk'>@@ -1702,7 +1732,7 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 				context-&gt;res_ctx.pipe_ctx[i].plane_state != context-&gt;res_ctx.pipe_ctx[i].top_pipe-&gt;plane_state) &amp;&amp;</div><div class='ctx'> 				context-&gt;res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {</div><div class='ctx'> 			/* SS: all active surfaces stored in MALL */</div><div class='del'>-			if (context-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+			if (dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {</div><div class='ctx'> 				context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes += context-&gt;res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;</div><div class='ctx'> </div><div class='ctx'> 				if (context-&gt;res_ctx.pipe_ctx[i].stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {</div><div class='hunk'>@@ -1916,7 +1946,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	// For each full update, remove all existing phantom pipes first</div><div class='del'>-	dc-&gt;res_pool-&gt;funcs-&gt;remove_phantom_pipes(dc, context, fast_validate);</div><div class='add'>+	dc_state_remove_phantom_streams_and_planes(dc, context);</div><div class='add'>+	dc_state_release_phantom_streams_and_planes(dc, context);</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;res_pool-&gt;funcs-&gt;update_soc_for_wm_a(dc, context);</div><div class='ctx'> </div><div class='hunk'>@@ -2178,6 +2209,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='ctx'> 		pipe_cnt = dc-&gt;res_pool-&gt;funcs-&gt;populate_dml_pipes(dc, context, pipes, fast_validate);</div><div class='add'>+		dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);</div><div class='ctx'> </div><div class='ctx'> 		/* repopulate_pipes = 1 means the pipes were either split or merged. In this case</div><div class='ctx'> 		 * we have to re-calculate the DET allocation and run through DML once more to</div><div class='hunk'>@@ -2186,7 +2218,9 @@ bool dcn32_internal_validate_bw(struct dc *dc,</div><div class='ctx'> 		 * */</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =</div><div class='ctx'> 					dm_prefetch_support_uclk_fclk_and_stutter_if_possible;</div><div class='add'>+</div><div class='ctx'> 		vlevel = dml_get_voltage_level(&amp;context-&gt;bw_ctx.dml, pipes, pipe_cnt);</div><div class='add'>+</div><div class='ctx'> 		if (vlevel == context-&gt;bw_ctx.dml.soc.num_states) {</div><div class='ctx'> 			/* failed after DET size changes */</div><div class='ctx'> 			goto validate_fail;</div><div class='hunk'>@@ -2231,6 +2265,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	int i, pipe_idx, vlevel_temp = 0;</div><div class='ctx'> 	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;</div><div class='ctx'> 	double dcfclk_from_validation = context-&gt;bw_ctx.dml.vba.DCFCLKState[vlevel][context-&gt;bw_ctx.dml.vba.maxMpcComb];</div><div class='add'>+	double dram_speed_from_validation = context-&gt;bw_ctx.dml.vba.DRAMSpeed;</div><div class='ctx'> 	double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;</div><div class='ctx'> 	bool pstate_en = context-&gt;bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context-&gt;bw_ctx.dml.vba.maxMpcComb] !=</div><div class='ctx'> 			dm_dram_clock_change_unsupported;</div><div class='hunk'>@@ -2418,7 +2453,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr-&gt;bw_params-&gt;wm_table.nv_entries[WM_C].valid) {</div><div class='del'>-		min_dram_speed_mts = context-&gt;bw_ctx.dml.vba.DRAMSpeed;</div><div class='add'>+		min_dram_speed_mts = dram_speed_from_validation;</div><div class='ctx'> 		min_dram_speed_mts_margin = 160;</div><div class='ctx'> </div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.dram_clock_change_latency_us =</div><div class='hunk'>@@ -3294,25 +3329,24 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)</div><div class='ctx'> {</div><div class='ctx'> 	bool allow = false;</div><div class='ctx'> 	uint32_t refresh_rate = 0;</div><div class='add'>+	uint32_t min_refresh = subvp_active_margin_list.min_refresh;</div><div class='add'>+	uint32_t max_refresh = subvp_active_margin_list.max_refresh;</div><div class='add'>+	uint32_t i;</div><div class='ctx'> </div><div class='del'>-	/* Allow subvp on displays that have active margin for 2560x1440@60hz displays</div><div class='del'>-	 * only for now. There must be no scaling as well.</div><div class='del'>-	 *</div><div class='del'>-	 * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs</div><div class='del'>-	 * for p-state switching.</div><div class='del'>-	 */</div><div class='del'>-	if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state) {</div><div class='del'>-		refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * 100 +</div><div class='del'>-						pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - 1)</div><div class='del'>-						/ (double)(pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total);</div><div class='del'>-		if (pipe-&gt;stream-&gt;timing.v_addressable == 1440 &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;timing.h_addressable == 2560 &amp;&amp;</div><div class='del'>-				refresh_rate &gt;= 55 &amp;&amp; refresh_rate &lt;= 65 &amp;&amp;</div><div class='del'>-				pipe-&gt;plane_state-&gt;src_rect.height == 1440 &amp;&amp;</div><div class='del'>-				pipe-&gt;plane_state-&gt;src_rect.width == 2560 &amp;&amp;</div><div class='del'>-				pipe-&gt;plane_state-&gt;dst_rect.height == 1440 &amp;&amp;</div><div class='del'>-				pipe-&gt;plane_state-&gt;dst_rect.width == 2560)</div><div class='add'>+	for (i = 0; i &lt; SUBVP_ACTIVE_MARGIN_LIST_LEN; i++) {</div><div class='add'>+		uint32_t width = subvp_active_margin_list.res[i].width;</div><div class='add'>+		uint32_t height = subvp_active_margin_list.res[i].height;</div><div class='add'>+</div><div class='add'>+		refresh_rate = (pipe-&gt;stream-&gt;timing.pix_clk_100hz * (uint64_t)100 +</div><div class='add'>+			pipe-&gt;stream-&gt;timing.v_total * pipe-&gt;stream-&gt;timing.h_total - (uint64_t)1);</div><div class='add'>+		refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.v_total);</div><div class='add'>+		refresh_rate = div_u64(refresh_rate, pipe-&gt;stream-&gt;timing.h_total);</div><div class='add'>+</div><div class='add'>+		if (refresh_rate &gt;= min_refresh &amp;&amp; refresh_rate &lt;= max_refresh &amp;&amp;</div><div class='add'>+				dcn32_check_native_scaling_for_res(pipe, width, height)) {</div><div class='ctx'> 			allow = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return allow;</div><div class='ctx'> }</div><div class='hunk'>@@ -3431,7 +3465,15 @@ void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *co</div><div class='ctx'> 	for (i = 0, pipe_idx = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		const struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (!pipe-&gt;stream)</div><div class='add'>+		/* In DCN32/321, FPO uses per-pipe P-State force.</div><div class='add'>+		 * If there's no planes, HUBP is power gated and</div><div class='add'>+		 * therefore programming UCLK_PSTATE_FORCE does</div><div class='add'>+		 * nothing (P-State will always be asserted naturally</div><div class='add'>+		 * on a pipe that has HUBP power gated. Therefore we</div><div class='add'>+		 * only want to enable FPO if the FPO pipe has both</div><div class='add'>+		 * a stream and a plane.</div><div class='add'>+		 */</div><div class='add'>+		if (!pipe-&gt;stream || !pipe-&gt;plane_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &lt;= 0) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c<br/>index cbdfb762c10c..6c84b0fa40f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c</a></div><div class='hunk'>@@ -813,6 +813,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman</div><div class='ctx'> 					(v-&gt;DRAMSpeedPerState[mode_lib-&gt;vba.VoltageLevel] &lt;= MEM_STROBE_FREQ_MHZ ||</div><div class='ctx'> 						v-&gt;DCFCLKPerState[mode_lib-&gt;vba.VoltageLevel] &lt;= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?</div><div class='ctx'> 							mode_lib-&gt;vba.ip.min_prefetch_in_strobe_us : 0,</div><div class='add'>+					mode_lib-&gt;vba.PrefetchModePerState[mode_lib-&gt;vba.VoltageLevel][mode_lib-&gt;vba.maxMpcComb] &gt; 0 || mode_lib-&gt;vba.DRAMClockChangeRequirementFinal == false,</div><div class='add'>+</div><div class='ctx'> 					/* Output */</div><div class='ctx'> 					&amp;v-&gt;DSTXAfterScaler[k],</div><div class='ctx'> 					&amp;v-&gt;DSTYAfterScaler[k],</div><div class='hunk'>@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l</div><div class='ctx'> 							v-&gt;SwathHeightCThisState[k], v-&gt;TWait,</div><div class='ctx'> 							(v-&gt;DRAMSpeedPerState[i] &lt;= MEM_STROBE_FREQ_MHZ || v-&gt;DCFCLKState[i][j] &lt;= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?</div><div class='ctx'> 									mode_lib-&gt;vba.ip.min_prefetch_in_strobe_us : 0,</div><div class='add'>+							mode_lib-&gt;vba.PrefetchModePerState[i][j] &gt; 0 || mode_lib-&gt;vba.DRAMClockChangeRequirementFinal == false,</div><div class='ctx'> </div><div class='ctx'> 							/* Output */</div><div class='ctx'> 							&amp;v-&gt;dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c<br/>index d940dfa5ae43..80fccd4999a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c</a></div><div class='hunk'>@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule(</div><div class='ctx'> 		unsigned int SwathHeightC,</div><div class='ctx'> 		double TWait,</div><div class='ctx'> 		double TPreReq,</div><div class='add'>+		bool ExtendPrefetchIfPossible,</div><div class='ctx'> 		/* Output */</div><div class='ctx'> 		double   *DSTXAfterScaler,</div><div class='ctx'> 		double   *DSTYAfterScaler,</div><div class='hunk'>@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule(</div><div class='ctx'> 			/* Clamp to oto for bandwidth calculation */</div><div class='ctx'> 			LinesForPrefetchBandwidth = dst_y_prefetch_oto;</div><div class='ctx'> 		} else {</div><div class='del'>-			*DestinationLinesForPrefetch = dst_y_prefetch_equ;</div><div class='del'>-			TimeForFetchingMetaPTE = Tvm_equ;</div><div class='del'>-			TimeForFetchingRowInVBlank = Tr0_equ;</div><div class='del'>-			*PrefetchBandwidth = prefetch_bw_equ;</div><div class='del'>-			/* Clamp to equ for bandwidth calculation */</div><div class='del'>-			LinesForPrefetchBandwidth = dst_y_prefetch_equ;</div><div class='add'>+			/* For mode programming we want to extend the prefetch as much as possible</div><div class='add'>+			 * (up to oto, or as long as we can for equ) if we're not already applying</div><div class='add'>+			 * the 60us prefetch requirement. This is to avoid intermittent underflow</div><div class='add'>+			 * issues during prefetch.</div><div class='add'>+			 *</div><div class='add'>+			 * The prefetch extension is applied under the following scenarios:</div><div class='add'>+			 * 1. We're in prefetch mode &gt; 0 (i.e. we don't support MCLK switch in blank)</div><div class='add'>+			 * 2. We're using subvp or drr methods of p-state switch, in which case we</div><div class='add'>+			 *    we don't care if prefetch takes up more of the blanking time</div><div class='add'>+			 *</div><div class='add'>+			 * Mode programming typically chooses the smallest prefetch time possible</div><div class='add'>+			 * (i.e. highest bandwidth during prefetch) presumably to create margin between</div><div class='add'>+			 * p-states / c-states that happen in vblank and prefetch. Therefore we only</div><div class='add'>+			 * apply this prefetch extension when p-state in vblank is not required (UCLK</div><div class='add'>+			 * p-states take up the most vblank time).</div><div class='add'>+			 */</div><div class='add'>+			if (ExtendPrefetchIfPossible &amp;&amp; TPreReq == 0 &amp;&amp; VStartup &lt; MaxVStartup) {</div><div class='add'>+				MyError = true;</div><div class='add'>+			} else {</div><div class='add'>+				*DestinationLinesForPrefetch = dst_y_prefetch_equ;</div><div class='add'>+				TimeForFetchingMetaPTE = Tvm_equ;</div><div class='add'>+				TimeForFetchingRowInVBlank = Tr0_equ;</div><div class='add'>+				*PrefetchBandwidth = prefetch_bw_equ;</div><div class='add'>+				/* Clamp to equ for bandwidth calculation */</div><div class='add'>+				LinesForPrefetchBandwidth = dst_y_prefetch_equ;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h<br/>index 592d174df6c6..5d34735df83d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h</a></div><div class='hunk'>@@ -747,6 +747,7 @@ bool dml32_CalculatePrefetchSchedule(</div><div class='ctx'> 		unsigned int SwathHeightC,</div><div class='ctx'> 		double TWait,</div><div class='ctx'> 		double TPreReq,</div><div class='add'>+		bool ExtendPrefetchIfPossible,</div><div class='ctx'> 		/* Output */</div><div class='ctx'> 		double   *DSTXAfterScaler,</div><div class='ctx'> 		double   *DSTYAfterScaler,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c<br/>index a5fe523668e9..475c4ec43c01 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c</a></div><div class='hunk'>@@ -124,7 +124,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.phyclk_mhz = 600.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='ctx'> 			.dscclk_mhz = 186.0,</div><div class='del'>-			.dtbclk_mhz = 625.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 1,</div><div class='hunk'>@@ -133,7 +133,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='ctx'> 			.dscclk_mhz = 209.0,</div><div class='del'>-			.dtbclk_mhz = 625.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 2,</div><div class='hunk'>@@ -142,7 +142,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='ctx'> 			.dscclk_mhz = 209.0,</div><div class='del'>-			.dtbclk_mhz = 625.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 3,</div><div class='hunk'>@@ -151,7 +151,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='ctx'> 			.dscclk_mhz = 371.0,</div><div class='del'>-			.dtbclk_mhz = 625.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 		{</div><div class='ctx'> 			.state = 4,</div><div class='hunk'>@@ -160,15 +160,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {</div><div class='ctx'> 			.phyclk_mhz = 810.0,</div><div class='ctx'> 			.phyclk_d18_mhz = 667.0,</div><div class='ctx'> 			.dscclk_mhz = 417.0,</div><div class='del'>-			.dtbclk_mhz = 625.0,</div><div class='add'>+			.dtbclk_mhz = 600.0,</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	.num_states = 5,</div><div class='del'>-	.sr_exit_time_us = 9.0,</div><div class='del'>-	.sr_enter_plus_exit_time_us = 11.0,</div><div class='del'>-	.sr_exit_z8_time_us = 50.0, /*changed from 442.0*/</div><div class='del'>-	.sr_enter_plus_exit_z8_time_us = 50.0,/*changed from 560.0*/</div><div class='del'>-	.fclk_change_latency_us = 20.0,</div><div class='add'>+	.sr_exit_time_us = 14.0,</div><div class='add'>+	.sr_enter_plus_exit_time_us = 16.0,</div><div class='add'>+	.sr_exit_z8_time_us = 210.0,</div><div class='add'>+	.sr_enter_plus_exit_z8_time_us = 320.0,</div><div class='add'>+	.fclk_change_latency_us = 24.0,</div><div class='ctx'> 	.usr_retraining_latency_us = 2,</div><div class='ctx'> 	.writeback_latency_us = 12.0,</div><div class='ctx'> </div><div class='hunk'>@@ -326,9 +326,74 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,</div><div class='ctx'> 		dcn3_5_soc.dram_clock_change_latency_us =</div><div class='ctx'> 			dc-&gt;debug.dram_clock_change_latency_ns / 1000.0;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.dram_clock_change_latency_ns &gt; 0)</div><div class='add'>+		dcn3_5_soc.dram_clock_change_latency_us =</div><div class='add'>+			dc-&gt;bb_overrides.dram_clock_change_latency_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_exit_time_ns &gt; 0)</div><div class='add'>+		dcn3_5_soc.sr_exit_time_us = dc-&gt;bb_overrides.sr_exit_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_enter_plus_exit_time_ns &gt; 0)</div><div class='add'>+		dcn3_5_soc.sr_enter_plus_exit_time_us =</div><div class='add'>+			dc-&gt;bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_exit_z8_time_ns &gt; 0)</div><div class='add'>+		dcn3_5_soc.sr_exit_z8_time_us = dc-&gt;bb_overrides.sr_exit_z8_time_ns / 1000.0;</div><div class='add'>+</div><div class='add'>+	if (dc-&gt;bb_overrides.sr_enter_plus_exit_z8_time_ns &gt; 0)</div><div class='add'>+		dcn3_5_soc.sr_enter_plus_exit_z8_time_us =</div><div class='add'>+			dc-&gt;bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0;</div><div class='add'>+</div><div class='ctx'> 	/*temp till dml2 fully work without dml1*/</div><div class='ctx'> 	dml_init_instance(&amp;dc-&gt;dml, &amp;dcn3_5_soc, &amp;dcn3_5_ip,</div><div class='ctx'> 				DML_PROJECT_DCN31);</div><div class='add'>+</div><div class='add'>+	/*copy to dml2, before dml2_create*/</div><div class='add'>+	if (clk_table-&gt;num_entries &gt; 2) {</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; clk_table-&gt;num_entries; i++) {</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_states =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =</div><div class='add'>+				clock_limits[i].dcfclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =</div><div class='add'>+				clock_limits[i].fabricclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =</div><div class='add'>+				clock_limits[i].dispclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =</div><div class='add'>+				clock_limits[i].dppclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =</div><div class='add'>+				clock_limits[i].socclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =</div><div class='add'>+				clk_table-&gt;entries[i].memclk_mhz * clk_table-&gt;entries[i].wck_ratio;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =</div><div class='add'>+				clock_limits[i].dtbclk_mhz;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+			dc-&gt;dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =</div><div class='add'>+				clk_table-&gt;num_entries;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update latency values */</div><div class='add'>+	dc-&gt;dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us;</div><div class='add'>+	dc-&gt;dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us;</div><div class='add'>+</div><div class='add'>+	dc-&gt;dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us;</div><div class='add'>+	dc-&gt;dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool is_dual_plane(enum surface_pixel_format format)</div><div class='hunk'>@@ -507,3 +572,37 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	return pipe_cnt;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)</div><div class='add'>+{</div><div class='add'>+	enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW;</div><div class='add'>+	unsigned int i, plane_count = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='add'>+			plane_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (plane_count == 0) {</div><div class='add'>+		support = DCN_ZSTATE_SUPPORT_ALLOW;</div><div class='add'>+	} else if (plane_count == 1 &amp;&amp; context-&gt;stream_count == 1 &amp;&amp; context-&gt;streams[0]-&gt;signal == SIGNAL_TYPE_EDP) {</div><div class='add'>+		struct dc_link *link = context-&gt;streams[0]-&gt;sink-&gt;link;</div><div class='add'>+		bool is_pwrseq0 = link &amp;&amp; link-&gt;link_index == 0;</div><div class='add'>+		bool is_psr1 = link &amp;&amp; link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1 &amp;&amp; !link-&gt;panel_config.psr.disable_psr;</div><div class='add'>+		int minmum_z8_residency =</div><div class='add'>+			dc-&gt;debug.minimum_z8_residency_time &gt; 0 ? dc-&gt;debug.minimum_z8_residency_time : 1000;</div><div class='add'>+		bool allow_z8 = context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; (double)minmum_z8_residency;</div><div class='add'>+		int minmum_z10_residency =</div><div class='add'>+			dc-&gt;debug.minimum_z10_residency_time &gt; 0 ? dc-&gt;debug.minimum_z10_residency_time : 5000;</div><div class='add'>+		bool allow_z10 = context-&gt;bw_ctx.dml.vba.StutterPeriod &gt; (double)minmum_z10_residency;</div><div class='add'>+</div><div class='add'>+		if (is_pwrseq0 &amp;&amp; allow_z10)</div><div class='add'>+			support = DCN_ZSTATE_SUPPORT_ALLOW;</div><div class='add'>+		else if (is_pwrseq0 &amp;&amp; is_psr1)</div><div class='add'>+			support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;</div><div class='add'>+		else if (allow_z8)</div><div class='add'>+			support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	context-&gt;bw_ctx.bw.dcn.clk.zstate_support = support;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h<br/>index e8d5a170893e..067480fc3691 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h</a></div><div class='hunk'>@@ -39,4 +39,6 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,</div><div class='ctx'> 					      display_e2e_pipe_params_st *pipes,</div><div class='ctx'> 					      bool fast_validate);</div><div class='ctx'> </div><div class='add'>+void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c<br/>index 510be909cd75..9be5ebf3a8c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c</a></div><div class='hunk'>@@ -5420,7 +5420,7 @@ static void CalculateOutputLink(</div><div class='ctx'> 					*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='ctx'> 												OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);</div><div class='ctx'> </div><div class='del'>-					if (OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 20000 / 32 &amp;&amp; DSCEnable == dml_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='add'>+					if (*OutBpp == 0 &amp;&amp; PHYCLKD32PerState &lt; 20000 / 32 &amp;&amp; DSCEnable == dml_dsc_enable_if_necessary &amp;&amp; ForcedOutputLinkBPP == 0) {</div><div class='ctx'> 						*RequiresDSC = true;</div><div class='ctx'> 						LinkDSCEnable = true;</div><div class='ctx'> 						*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,</div><div class='hunk'>@@ -6229,7 +6229,7 @@ static void set_calculate_prefetch_schedule_params(struct display_mode_lib_st *m</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;GPUVMEnable = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMEnable;</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;HostVMEnable = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMEnable;</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;HostVMMaxNonCachedPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;</div><div class='del'>-				CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes;</div><div class='add'>+				CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024;</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;DynamicMetadataEnable = mode_lib-&gt;ms.cache_display_cfg.plane.DynamicMetadataEnable[k];</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;DynamicMetadataVMEnabled = mode_lib-&gt;ms.ip.dynamic_metadata_vm_enabled;</div><div class='ctx'> 				CalculatePrefetchSchedule_params-&gt;DynamicMetadataLinesBeforeActiveRequired = mode_lib-&gt;ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];</div><div class='hunk'>@@ -6329,7 +6329,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 				mode_lib-&gt;ms.NoOfDPPThisState,</div><div class='ctx'> 				mode_lib-&gt;ms.dpte_group_bytes,</div><div class='ctx'> 				s-&gt;HostVMInefficiencyFactor,</div><div class='del'>-				mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes,</div><div class='add'>+				mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024,</div><div class='ctx'> 				mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);</div><div class='ctx'> </div><div class='ctx'> 		s-&gt;NextMaxVStartup = s-&gt;MaxVStartupAllPlanes[j];</div><div class='hunk'>@@ -6542,7 +6542,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.HostVMEnable,</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMEnable,</div><div class='del'>-						mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes,</div><div class='add'>+						mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024,</div><div class='ctx'> 						mode_lib-&gt;ms.PDEAndMetaPTEBytesPerFrame[j][k],</div><div class='ctx'> 						mode_lib-&gt;ms.MetaRowBytes[j][k],</div><div class='ctx'> 						mode_lib-&gt;ms.DPTEBytesPerRow[j][k],</div><div class='hunk'>@@ -7687,7 +7687,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;HostVMMaxNonCachedPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;GPUVMMaxPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;GPUVMMinPageSizeKBytes = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;</div><div class='del'>-		CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes;</div><div class='add'>+		CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024;</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;PTEBufferModeOverrideEn = mode_lib-&gt;ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;PTEBufferModeOverrideVal = mode_lib-&gt;ms.cache_display_cfg.plane.PTEBufferMode;</div><div class='ctx'> 		CalculateVMRowAndSwath_params-&gt;PTEBufferSizeNotExceeded = mode_lib-&gt;ms.PTEBufferSizeNotExceededPerState;</div><div class='hunk'>@@ -7957,7 +7957,7 @@ dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib)</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;GPUVMMaxPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;HostVMEnable = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMEnable;</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;NumberOfActiveSurfaces = mode_lib-&gt;ms.num_active_planes;</div><div class='del'>-		UseMinimumDCFCLK_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes;</div><div class='add'>+		UseMinimumDCFCLK_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024;</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;HostVMMaxNonCachedPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;DynamicMetadataVMEnabled = mode_lib-&gt;ms.ip.dynamic_metadata_vm_enabled;</div><div class='ctx'> 		UseMinimumDCFCLK_params-&gt;ImmediateFlipRequirement = s-&gt;ImmediateFlipRequiredFinal;</div><div class='hunk'>@@ -8699,7 +8699,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;HostVMMaxNonCachedPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;GPUVMMaxPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMMaxPageTableLevels;</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;GPUVMMinPageSizeKBytes = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMMinPageSizeKBytes;</div><div class='del'>-	CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes;</div><div class='add'>+	CalculateVMRowAndSwath_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024;</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;PTEBufferModeOverrideEn = mode_lib-&gt;ms.cache_display_cfg.plane.PTEBufferModeOverrideEn;</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;PTEBufferModeOverrideVal = mode_lib-&gt;ms.cache_display_cfg.plane.PTEBufferMode;</div><div class='ctx'> 	CalculateVMRowAndSwath_params-&gt;PTEBufferSizeNotExceeded = s-&gt;dummy_boolean_array[0];</div><div class='hunk'>@@ -8805,7 +8805,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 			mode_lib-&gt;ms.cache_display_cfg.hw.DPPPerSurface,</div><div class='ctx'> 			locals-&gt;dpte_group_bytes,</div><div class='ctx'> 			s-&gt;HostVMInefficiencyFactor,</div><div class='del'>-			mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes,</div><div class='add'>+			mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024,</div><div class='ctx'> 			mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels);</div><div class='ctx'> </div><div class='ctx'> 	locals-&gt;TCalc = 24.0 / locals-&gt;DCFCLKDeepSleep;</div><div class='hunk'>@@ -8995,7 +8995,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;GPUVMEnable = mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMEnable;</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;HostVMEnable = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMEnable;</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;HostVMMaxNonCachedPageTableLevels = mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels;</div><div class='del'>-			CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes;</div><div class='add'>+			CalculatePrefetchSchedule_params-&gt;HostVMMinPageSize = mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024;</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;DynamicMetadataEnable = mode_lib-&gt;ms.cache_display_cfg.plane.DynamicMetadataEnable[k];</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;DynamicMetadataVMEnabled = mode_lib-&gt;ms.ip.dynamic_metadata_vm_enabled;</div><div class='ctx'> 			CalculatePrefetchSchedule_params-&gt;DynamicMetadataLinesBeforeActiveRequired = mode_lib-&gt;ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];</div><div class='hunk'>@@ -9240,7 +9240,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.HostVMEnable,</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.HostVMMaxPageTableLevels,</div><div class='ctx'> 						mode_lib-&gt;ms.cache_display_cfg.plane.GPUVMEnable,</div><div class='del'>-						mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes,</div><div class='add'>+						mode_lib-&gt;ms.soc.hostvm_min_page_size_kbytes * 1024,</div><div class='ctx'> 						locals-&gt;PDEAndMetaPTEBytesFrame[k],</div><div class='ctx'> 						locals-&gt;MetaRowByte[k],</div><div class='ctx'> 						locals-&gt;PixelPTEBytesPerRow[k],</div><div class='hunk'>@@ -9446,13 +9446,13 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc</div><div class='ctx'> 		CalculateWatermarks_params-&gt;CompressedBufferSizeInkByte = locals-&gt;CompressedBufferSizeInkByte;</div><div class='ctx'> </div><div class='ctx'> 		// Output</div><div class='del'>-		CalculateWatermarks_params-&gt;Watermark = &amp;s-&gt;dummy_watermark; // Watermarks *Watermark</div><div class='del'>-		CalculateWatermarks_params-&gt;DRAMClockChangeSupport = &amp;mode_lib-&gt;ms.support.DRAMClockChangeSupport[j];</div><div class='del'>-		CalculateWatermarks_params-&gt;MaxActiveDRAMClockChangeLatencySupported = &amp;s-&gt;dummy_single_array[0][0]; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[]</div><div class='del'>-		CalculateWatermarks_params-&gt;SubViewportLinesNeededInMALL = &amp;mode_lib-&gt;ms.SubViewportLinesNeededInMALL[j]; // dml_uint_t SubViewportLinesNeededInMALL[]</div><div class='del'>-		CalculateWatermarks_params-&gt;FCLKChangeSupport = &amp;mode_lib-&gt;ms.support.FCLKChangeSupport[j];</div><div class='del'>-		CalculateWatermarks_params-&gt;MaxActiveFCLKChangeLatencySupported = &amp;s-&gt;dummy_single[0]; // dml_float_t *MaxActiveFCLKChangeLatencySupported</div><div class='del'>-		CalculateWatermarks_params-&gt;USRRetrainingSupport = &amp;mode_lib-&gt;ms.support.USRRetrainingSupport[j];</div><div class='add'>+		CalculateWatermarks_params-&gt;Watermark = &amp;locals-&gt;Watermark; // Watermarks *Watermark</div><div class='add'>+		CalculateWatermarks_params-&gt;DRAMClockChangeSupport = &amp;locals-&gt;DRAMClockChangeSupport;</div><div class='add'>+		CalculateWatermarks_params-&gt;MaxActiveDRAMClockChangeLatencySupported = locals-&gt;MaxActiveDRAMClockChangeLatencySupported; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[]</div><div class='add'>+		CalculateWatermarks_params-&gt;SubViewportLinesNeededInMALL = locals-&gt;SubViewportLinesNeededInMALL; // dml_uint_t SubViewportLinesNeededInMALL[]</div><div class='add'>+		CalculateWatermarks_params-&gt;FCLKChangeSupport = &amp;locals-&gt;FCLKChangeSupport;</div><div class='add'>+		CalculateWatermarks_params-&gt;MaxActiveFCLKChangeLatencySupported = &amp;locals-&gt;MaxActiveFCLKChangeLatencySupported; // dml_float_t *MaxActiveFCLKChangeLatencySupported</div><div class='add'>+		CalculateWatermarks_params-&gt;USRRetrainingSupport = &amp;locals-&gt;USRRetrainingSupport;</div><div class='ctx'> </div><div class='ctx'> 		CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(</div><div class='ctx'> 			&amp;mode_lib-&gt;scratch,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c<br/>index 1a2b24cc6b61..0baf39d64a2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c</a></div><div class='hunk'>@@ -772,18 +772,29 @@ static unsigned int get_mpc_factor(struct dml2_context *ctx,</div><div class='ctx'> 		const struct dc_state *state,</div><div class='ctx'> 		const struct dml_display_cfg_st *disp_cfg,</div><div class='ctx'> 		struct dml2_dml_to_dc_pipe_mapping *mapping,</div><div class='del'>-		const struct dc_stream_status *status, unsigned int stream_id,</div><div class='add'>+		const struct dc_stream_status *status,</div><div class='add'>+		const struct dc_stream_state *stream,</div><div class='ctx'> 		int plane_idx)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int plane_id;</div><div class='ctx'> 	unsigned int cfg_idx;</div><div class='add'>+	unsigned int mpc_factor;</div><div class='ctx'> </div><div class='del'>-	get_plane_id(ctx, state, status-&gt;plane_states[plane_idx], stream_id, plane_idx, &amp;plane_id);</div><div class='add'>+	get_plane_id(ctx, state, status-&gt;plane_states[plane_idx],</div><div class='add'>+			stream-&gt;stream_id, plane_idx, &amp;plane_id);</div><div class='ctx'> 	cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id);</div><div class='del'>-	if (ctx-&gt;architecture == dml2_architecture_20)</div><div class='del'>-		return (unsigned int)disp_cfg-&gt;hw.DPPPerSurface[cfg_idx];</div><div class='del'>-	ASSERT(false);</div><div class='del'>-	return 1;</div><div class='add'>+	if (ctx-&gt;architecture == dml2_architecture_20) {</div><div class='add'>+		mpc_factor = (unsigned int)disp_cfg-&gt;hw.DPPPerSurface[cfg_idx];</div><div class='add'>+	} else {</div><div class='add'>+		mpc_factor = 1;</div><div class='add'>+		ASSERT(false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* For stereo timings, we need to pipe split */</div><div class='add'>+	if (dml2_is_stereo_timing(stream))</div><div class='add'>+		mpc_factor = 2;</div><div class='add'>+</div><div class='add'>+	return mpc_factor;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static unsigned int get_odm_factor(</div><div class='hunk'>@@ -820,14 +831,13 @@ static void populate_mpc_factors_for_stream(</div><div class='ctx'> 		unsigned int mpc_factors[MAX_PIPES])</div><div class='ctx'> {</div><div class='ctx'> 	const struct dc_stream_status *status = &amp;state-&gt;stream_status[stream_idx];</div><div class='del'>-	unsigned int stream_id = state-&gt;streams[stream_idx]-&gt;stream_id;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; status-&gt;plane_count; i++)</div><div class='ctx'> 		if (odm_factor == 1)</div><div class='ctx'> 			mpc_factors[i] = get_mpc_factor(</div><div class='ctx'> 					ctx, state, disp_cfg, mapping, status,</div><div class='del'>-					stream_id, i);</div><div class='add'>+					state-&gt;streams[stream_idx], i);</div><div class='ctx'> 		else</div><div class='ctx'> 			mpc_factors[i] = 1;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h<br/>index e85866db80ff..7ca7f2a743c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h</a></div><div class='hunk'>@@ -38,5 +38,6 @@</div><div class='ctx'> #include "core_types.h"</div><div class='ctx'> #include "dsc.h"</div><div class='ctx'> #include "clk_mgr.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #endif //__DML2_DC_TYPES_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c<br/>index 32f8a43af3d6..282d70e2b18a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c</a></div><div class='hunk'>@@ -51,7 +51,7 @@ unsigned int dml2_helper_calculate_num_ways_for_subvp(struct dml2_context *ctx,</div><div class='ctx'> </div><div class='ctx'> 		// Find the phantom pipes</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; !pipe-&gt;prev_odm_pipe &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			bytes_per_pixel = pipe-&gt;plane_state-&gt;format &gt;= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4;</div><div class='ctx'> 			mblk_width = ctx-&gt;config.mall_cfg.mblk_width_pixels;</div><div class='ctx'> 			mblk_height = bytes_per_pixel == 4 ? mblk_width = ctx-&gt;config.mall_cfg.mblk_height_4bpe_pixels : ctx-&gt;config.mall_cfg.mblk_height_8bpe_pixels;</div><div class='hunk'>@@ -253,7 +253,7 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context</div><div class='ctx'> 		 *   to combine this with SubVP can cause issues with the scheduling).</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE &amp;&amp; refresh_rate &lt; 120 &amp;&amp;</div><div class='add'>+				ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_NONE &amp;&amp; refresh_rate &lt; 120 &amp;&amp;</div><div class='ctx'> 				vba-&gt;ActiveDRAMClockChangeLatencyMarginPerState[vba-&gt;VoltageLevel][vba-&gt;maxMpcComb][vba-&gt;pipe_plane[pipe_idx]] &lt;= 0) {</div><div class='ctx'> 			while (pipe) {</div><div class='ctx'> 				num_pipes++;</div><div class='hunk'>@@ -317,7 +317,7 @@ static bool enough_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *st</div><div class='ctx'> </div><div class='ctx'> 		// Find the minimum pipe split count for non SubVP pipes</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+				ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_NONE) {</div><div class='ctx'> 			split_cnt = 0;</div><div class='ctx'> 			while (pipe) {</div><div class='ctx'> 				split_cnt++;</div><div class='hunk'>@@ -372,8 +372,8 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c</div><div class='ctx'> 		 * and also to store the two main SubVP pipe pointers in subvp_pipes[2].</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='del'>-			phantom = pipe-&gt;stream-&gt;mall_stream_config.paired_stream;</div><div class='add'>+				ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {</div><div class='add'>+			phantom = ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='ctx'> 			microschedule_lines = (phantom-&gt;timing.v_total - phantom-&gt;timing.v_front_porch) +</div><div class='ctx'> 					phantom-&gt;timing.v_addressable;</div><div class='ctx'> </div><div class='hunk'>@@ -435,6 +435,7 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context</div><div class='ctx'> 	struct pipe_ctx *pipe = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *phantom_timing = NULL;</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='ctx'> 	int16_t prefetch_us = 0;</div><div class='ctx'> 	int16_t mall_region_us = 0;</div><div class='ctx'> 	int16_t drr_frame_us = 0;	// nominal frame time</div><div class='hunk'>@@ -453,12 +454,13 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		// Find the SubVP pipe</div><div class='del'>-		if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+		if (ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	phantom_stream = ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe-&gt;stream);</div><div class='ctx'> 	main_timing = &amp;pipe-&gt;stream-&gt;timing;</div><div class='del'>-	phantom_timing = &amp;pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+	phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 	prefetch_us = (phantom_timing-&gt;v_total - phantom_timing-&gt;v_front_porch) * phantom_timing-&gt;h_total /</div><div class='ctx'> 			(double)(phantom_timing-&gt;pix_clk_100hz * 100) * 1000000 +</div><div class='ctx'> 			ctx-&gt;config.svp_pstate.subvp_prefetch_end_to_mall_start_us;</div><div class='hunk'>@@ -519,6 +521,8 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *</div><div class='ctx'> 	struct dc_crtc_timing *main_timing = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *phantom_timing = NULL;</div><div class='ctx'> 	struct dc_crtc_timing *vblank_timing = NULL;</div><div class='add'>+	struct dc_stream_state *phantom_stream;</div><div class='add'>+	enum mall_stream_type pipe_mall_type;</div><div class='ctx'> </div><div class='ctx'> 	/* For SubVP + VBLANK/DRR cases, we assume there can only be</div><div class='ctx'> 	 * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK</div><div class='hunk'>@@ -528,19 +532,20 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		pipe_mall_type = ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		// We check for master pipe, but it shouldn't matter since we only need</div><div class='ctx'> 		// the pipe for timing info (stream should be same for any pipe splits)</div><div class='ctx'> 		if (!pipe-&gt;stream || !pipe-&gt;plane_state || pipe-&gt;top_pipe || pipe-&gt;prev_odm_pipe)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (!found &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+		if (!found &amp;&amp; pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 			// Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).</div><div class='ctx'> 			vblank_index = i;</div><div class='ctx'> 			found = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!subvp_pipe &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+		if (!subvp_pipe &amp;&amp; pipe_mall_type == SUBVP_MAIN)</div><div class='ctx'> 			subvp_pipe = pipe;</div><div class='ctx'> 	}</div><div class='ctx'> 	// Use ignore_msa_timing_param flag to identify as DRR</div><div class='hunk'>@@ -548,8 +553,9 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *</div><div class='ctx'> 		// SUBVP + DRR case</div><div class='ctx'> 		schedulable = dml2_svp_drr_schedulable(ctx, context, &amp;context-&gt;res_ctx.pipe_ctx[vblank_index].stream-&gt;timing);</div><div class='ctx'> 	} else if (found) {</div><div class='add'>+		phantom_stream = ctx-&gt;config.svp_pstate.callbacks.get_paired_subvp_stream(context, subvp_pipe-&gt;stream);</div><div class='ctx'> 		main_timing = &amp;subvp_pipe-&gt;stream-&gt;timing;</div><div class='del'>-		phantom_timing = &amp;subvp_pipe-&gt;stream-&gt;mall_stream_config.paired_stream-&gt;timing;</div><div class='add'>+		phantom_timing = &amp;phantom_stream-&gt;timing;</div><div class='ctx'> 		vblank_timing = &amp;context-&gt;res_ctx.pipe_ctx[vblank_index].stream-&gt;timing;</div><div class='ctx'> 		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe</div><div class='ctx'> 		// Also include the prefetch end to mallstart delay time</div><div class='hunk'>@@ -602,19 +608,20 @@ bool dml2_svp_validate_static_schedulability(struct dml2_context *ctx, struct dc</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, pipe_idx = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		enum mall_stream_type pipe_mall_type = ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+				pipe_mall_type == SUBVP_MAIN)</div><div class='ctx'> 			subvp_count++;</div><div class='ctx'> </div><div class='ctx'> 		// Count how many planes that aren't SubVP/phantom are capable of VACTIVE</div><div class='ctx'> 		// switching (SubVP + VACTIVE unsupported). In situations where we force</div><div class='ctx'> 		// SubVP for a VACTIVE plane, we don't want to increment the vactive_count.</div><div class='ctx'> 		if (vba-&gt;ActiveDRAMClockChangeLatencyMargin[vba-&gt;pipe_plane[pipe_idx]] &gt; 0 &amp;&amp;</div><div class='del'>-		    pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_NONE) {</div><div class='add'>+		    pipe_mall_type == SUBVP_NONE) {</div><div class='ctx'> 			vactive_count++;</div><div class='ctx'> 		}</div><div class='ctx'> 		pipe_idx++;</div><div class='hunk'>@@ -708,14 +715,10 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state</div><div class='ctx'> static struct dc_stream_state *enable_phantom_stream(struct dml2_context *ctx, struct dc_state *state, unsigned int dc_pipe_idx, unsigned int svp_height, unsigned int vstartup)</div><div class='ctx'> {</div><div class='ctx'> 	struct pipe_ctx *ref_pipe = &amp;state-&gt;res_ctx.pipe_ctx[dc_pipe_idx];</div><div class='del'>-	struct dc_stream_state *phantom_stream = ctx-&gt;config.svp_pstate.callbacks.create_stream_for_sink(ref_pipe-&gt;stream-&gt;sink);</div><div class='del'>-</div><div class='del'>-	phantom_stream-&gt;signal = SIGNAL_TYPE_VIRTUAL;</div><div class='del'>-	phantom_stream-&gt;dpms_off = true;</div><div class='del'>-	phantom_stream-&gt;mall_stream_config.type = SUBVP_PHANTOM;</div><div class='del'>-	phantom_stream-&gt;mall_stream_config.paired_stream = ref_pipe-&gt;stream;</div><div class='del'>-	ref_pipe-&gt;stream-&gt;mall_stream_config.type = SUBVP_MAIN;</div><div class='del'>-	ref_pipe-&gt;stream-&gt;mall_stream_config.paired_stream = phantom_stream;</div><div class='add'>+	struct dc_stream_state *phantom_stream = ctx-&gt;config.svp_pstate.callbacks.create_phantom_stream(</div><div class='add'>+			ctx-&gt;config.svp_pstate.callbacks.dc,</div><div class='add'>+			state,</div><div class='add'>+			ref_pipe-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 	/* stream has limited viewport and small timing */</div><div class='ctx'> 	memcpy(&amp;phantom_stream-&gt;timing, &amp;ref_pipe-&gt;stream-&gt;timing, sizeof(phantom_stream-&gt;timing));</div><div class='hunk'>@@ -723,7 +726,10 @@ static struct dc_stream_state *enable_phantom_stream(struct dml2_context *ctx, s</div><div class='ctx'> 	memcpy(&amp;phantom_stream-&gt;dst, &amp;ref_pipe-&gt;stream-&gt;dst, sizeof(phantom_stream-&gt;dst));</div><div class='ctx'> 	set_phantom_stream_timing(ctx, state, ref_pipe, phantom_stream, dc_pipe_idx, svp_height, vstartup);</div><div class='ctx'> </div><div class='del'>-	ctx-&gt;config.svp_pstate.callbacks.add_stream_to_ctx(ctx-&gt;config.svp_pstate.callbacks.dc, state, phantom_stream);</div><div class='add'>+	ctx-&gt;config.svp_pstate.callbacks.add_phantom_stream(ctx-&gt;config.svp_pstate.callbacks.dc,</div><div class='add'>+			state,</div><div class='add'>+			phantom_stream,</div><div class='add'>+			ref_pipe-&gt;stream);</div><div class='ctx'> 	return phantom_stream;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -740,7 +746,10 @@ static void enable_phantom_plane(struct dml2_context *ctx,</div><div class='ctx'> 		if (curr_pipe-&gt;top_pipe &amp;&amp; curr_pipe-&gt;top_pipe-&gt;plane_state == curr_pipe-&gt;plane_state) {</div><div class='ctx'> 			phantom_plane = prev_phantom_plane;</div><div class='ctx'> 		} else {</div><div class='del'>-			phantom_plane = ctx-&gt;config.svp_pstate.callbacks.create_plane(ctx-&gt;config.svp_pstate.callbacks.dc);</div><div class='add'>+			phantom_plane = ctx-&gt;config.svp_pstate.callbacks.create_phantom_plane(</div><div class='add'>+					ctx-&gt;config.svp_pstate.callbacks.dc,</div><div class='add'>+					state,</div><div class='add'>+					curr_pipe-&gt;plane_state);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;address, &amp;curr_pipe-&gt;plane_state-&gt;address, sizeof(phantom_plane-&gt;address));</div><div class='hunk'>@@ -763,9 +772,7 @@ static void enable_phantom_plane(struct dml2_context *ctx,</div><div class='ctx'> 		phantom_plane-&gt;clip_rect.y = 0;</div><div class='ctx'> 		phantom_plane-&gt;clip_rect.height = phantom_stream-&gt;timing.v_addressable;</div><div class='ctx'> </div><div class='del'>-		phantom_plane-&gt;is_phantom = true;</div><div class='del'>-</div><div class='del'>-		ctx-&gt;config.svp_pstate.callbacks.add_plane_to_context(ctx-&gt;config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);</div><div class='add'>+		ctx-&gt;config.svp_pstate.callbacks.add_phantom_plane(ctx-&gt;config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);</div><div class='ctx'> </div><div class='ctx'> 		curr_pipe = curr_pipe-&gt;bottom_pipe;</div><div class='ctx'> 		prev_phantom_plane = phantom_plane;</div><div class='hunk'>@@ -790,7 +797,7 @@ static void add_phantom_pipes_for_main_pipe(struct dml2_context *ctx, struct dc_</div><div class='ctx'> 		// We determine which phantom pipes were added by comparing with</div><div class='ctx'> 		// the phantom stream.</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream == phantom_stream &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			pipe-&gt;stream-&gt;use_dynamic_meta = false;</div><div class='ctx'> 			pipe-&gt;plane_state-&gt;flip_immediate = false;</div><div class='ctx'> 			if (!ctx-&gt;config.svp_pstate.callbacks.build_scaling_params(pipe)) {</div><div class='hunk'>@@ -800,7 +807,7 @@ static void add_phantom_pipes_for_main_pipe(struct dml2_context *ctx, struct dc_</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool remove_all_planes_for_stream(struct dml2_context *ctx, struct dc_stream_state *stream, struct dc_state *context)</div><div class='add'>+static bool remove_all_phantom_planes_for_stream(struct dml2_context *ctx, struct dc_stream_state *stream, struct dc_state *context)</div><div class='ctx'> {</div><div class='ctx'> 	int i, old_plane_count;</div><div class='ctx'> 	struct dc_stream_status *stream_status = NULL;</div><div class='hunk'>@@ -821,9 +828,11 @@ static bool remove_all_planes_for_stream(struct dml2_context *ctx, struct dc_str</div><div class='ctx'> 	for (i = 0; i &lt; old_plane_count; i++)</div><div class='ctx'> 		del_planes[i] = stream_status-&gt;plane_states[i];</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; old_plane_count; i++)</div><div class='del'>-		if (!ctx-&gt;config.svp_pstate.callbacks.remove_plane_from_context(ctx-&gt;config.svp_pstate.callbacks.dc, stream, del_planes[i], context))</div><div class='add'>+	for (i = 0; i &lt; old_plane_count; i++) {</div><div class='add'>+		if (!ctx-&gt;config.svp_pstate.callbacks.remove_phantom_plane(ctx-&gt;config.svp_pstate.callbacks.dc, stream, del_planes[i], context))</div><div class='ctx'> 			return false;</div><div class='add'>+		ctx-&gt;config.svp_pstate.callbacks.release_phantom_plane(ctx-&gt;config.svp_pstate.callbacks.dc, context, del_planes[i]);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -832,35 +841,21 @@ bool dml2_svp_remove_all_phantom_pipes(struct dml2_context *ctx, struct dc_state</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	bool removed_pipe = false;</div><div class='del'>-	struct dc_plane_state *phantom_plane = NULL;</div><div class='ctx'> 	struct dc_stream_state *phantom_stream = NULL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ctx-&gt;config.dcn_pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;state-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		// build scaling params for phantom pipes</div><div class='del'>-		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='del'>-			phantom_plane = pipe-&gt;plane_state;</div><div class='add'>+		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; ctx-&gt;config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			phantom_stream = pipe-&gt;stream;</div><div class='ctx'> </div><div class='del'>-			remove_all_planes_for_stream(ctx, pipe-&gt;stream, state);</div><div class='del'>-			ctx-&gt;config.svp_pstate.callbacks.remove_stream_from_ctx(ctx-&gt;config.svp_pstate.callbacks.dc, state, pipe-&gt;stream);</div><div class='del'>-</div><div class='del'>-			/* Ref count is incremented on allocation and also when added to the context.</div><div class='del'>-			 * Therefore we must call release for the the phantom plane and stream once</div><div class='del'>-			 * they are removed from the ctx to finally decrement the refcount to 0 to free.</div><div class='del'>-			 */</div><div class='del'>-			ctx-&gt;config.svp_pstate.callbacks.plane_state_release(phantom_plane);</div><div class='del'>-			ctx-&gt;config.svp_pstate.callbacks.stream_release(phantom_stream);</div><div class='add'>+			remove_all_phantom_planes_for_stream(ctx, phantom_stream, state);</div><div class='add'>+			ctx-&gt;config.svp_pstate.callbacks.remove_phantom_stream(ctx-&gt;config.svp_pstate.callbacks.dc, state, phantom_stream);</div><div class='add'>+			ctx-&gt;config.svp_pstate.callbacks.release_phantom_stream(ctx-&gt;config.svp_pstate.callbacks.dc, state, phantom_stream);</div><div class='ctx'> </div><div class='ctx'> 			removed_pipe = true;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		// Clear all phantom stream info</div><div class='del'>-		if (pipe-&gt;stream) {</div><div class='del'>-			pipe-&gt;stream-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='del'>-			pipe-&gt;stream-&gt;mall_stream_config.paired_stream = NULL;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		if (pipe-&gt;plane_state) {</div><div class='ctx'> 			pipe-&gt;plane_state-&gt;is_phantom = false;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c<br/>index 75171bee6f71..64d01a9cd68c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c</a></div><div class='hunk'>@@ -341,25 +341,45 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Override from passed values, mainly for debugging purposes, if available */</div><div class='del'>-	if (dml2-&gt;config.bbox_overrides.sr_exit_latency_us) {</div><div class='del'>-		p-&gt;in_states-&gt;state_array[0].sr_exit_time_us = dml2-&gt;config.bbox_overrides.sr_exit_latency_us;</div><div class='del'>-	}</div><div class='add'>+	if (dml2-&gt;config.bbox_overrides.clks_table.num_states)</div><div class='add'>+			p-&gt;in_states-&gt;num_states = dml2-&gt;config.bbox_overrides.clks_table.num_states;</div><div class='add'>+</div><div class='add'>+	/* Override from passed values, if available */</div><div class='add'>+	for (i = 0; i &lt; p-&gt;in_states-&gt;num_states; i++) {</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.sr_exit_latency_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].sr_exit_time_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.sr_exit_latency_us;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_latency_us) {</div><div class='del'>-		p-&gt;in_states-&gt;state_array[0].sr_enter_plus_exit_time_us = dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_latency_us;</div><div class='del'>-	}</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_latency_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].sr_enter_plus_exit_time_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_latency_us;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (dml2-&gt;config.bbox_overrides.urgent_latency_us) {</div><div class='del'>-		p-&gt;in_states-&gt;state_array[0].urgent_latency_pixel_data_only_us = dml2-&gt;config.bbox_overrides.urgent_latency_us;</div><div class='del'>-	}</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.sr_exit_z8_time_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].sr_exit_z8_time_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.sr_exit_z8_time_us;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (dml2-&gt;config.bbox_overrides.dram_clock_change_latency_us) {</div><div class='del'>-		p-&gt;in_states-&gt;state_array[0].dram_clock_change_latency_us = dml2-&gt;config.bbox_overrides.dram_clock_change_latency_us;</div><div class='del'>-	}</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].sr_enter_plus_exit_z8_time_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.sr_enter_plus_exit_z8_time_us;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-	if (dml2-&gt;config.bbox_overrides.fclk_change_latency_us) {</div><div class='del'>-		p-&gt;in_states-&gt;state_array[0].fclk_change_latency_us = dml2-&gt;config.bbox_overrides.fclk_change_latency_us;</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.urgent_latency_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].urgent_latency_pixel_data_only_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.urgent_latency_us;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.dram_clock_change_latency_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].dram_clock_change_latency_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.dram_clock_change_latency_us;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (dml2-&gt;config.bbox_overrides.fclk_change_latency_us) {</div><div class='add'>+			p-&gt;in_states-&gt;state_array[i].fclk_change_latency_us =</div><div class='add'>+				dml2-&gt;config.bbox_overrides.fclk_change_latency_us;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* DCFCLK stas values are project specific */</div><div class='hunk'>@@ -380,7 +400,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Copy clocks tables entries, if available */</div><div class='ctx'> 	if (dml2-&gt;config.bbox_overrides.clks_table.num_states) {</div><div class='del'>-		p-&gt;in_states-&gt;num_states = dml2-&gt;config.bbox_overrides.clks_table.num_states;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; dml2-&gt;config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {</div><div class='ctx'> 			p-&gt;in_states-&gt;state_array[i].dcfclk_mhz = dml2-&gt;config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;</div><div class='hunk'>@@ -406,8 +425,9 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; dml2-&gt;config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {</div><div class='del'>-			p-&gt;in_states-&gt;state_array[i].dtbclk_mhz =</div><div class='del'>-				dml2-&gt;config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;</div><div class='add'>+			if (dml2-&gt;config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz &gt; 0)</div><div class='add'>+				p-&gt;in_states-&gt;state_array[i].dtbclk_mhz =</div><div class='add'>+					dml2-&gt;config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; dml2-&gt;config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {</div><div class='hunk'>@@ -498,8 +518,8 @@ void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st</div><div class='ctx'> 	out-&gt;do_urgent_latency_adjustment = in_soc_params-&gt;do_urgent_latency_adjustment;</div><div class='ctx'> 	out-&gt;dram_channel_width_bytes = (dml_uint_t)in_soc_params-&gt;dram_channel_width_bytes;</div><div class='ctx'> 	out-&gt;fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params-&gt;fabric_datapath_to_dcn_data_return_bytes;</div><div class='del'>-	out-&gt;gpuvm_min_page_size_kbytes = in_soc_params-&gt;gpuvm_min_page_size_bytes * 1024;</div><div class='del'>-	out-&gt;hostvm_min_page_size_kbytes = in_soc_params-&gt;hostvm_min_page_size_bytes * 1024;</div><div class='add'>+	out-&gt;gpuvm_min_page_size_kbytes = in_soc_params-&gt;gpuvm_min_page_size_bytes / 1024;</div><div class='add'>+	out-&gt;hostvm_min_page_size_kbytes = in_soc_params-&gt;hostvm_min_page_size_bytes / 1024;</div><div class='ctx'> 	out-&gt;mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params-&gt;mall_allocated_for_dcn_mbytes;</div><div class='ctx'> 	out-&gt;max_avg_dram_bw_use_normal_percent = in_soc_params-&gt;max_avg_dram_bw_use_normal_percent;</div><div class='ctx'> 	out-&gt;max_avg_fabric_bw_use_normal_percent = in_soc_params-&gt;max_avg_fabric_bw_use_normal_percent;</div><div class='hunk'>@@ -606,8 +626,8 @@ static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *</div><div class='ctx'> 		if (is_dp2p0_output_encoder(pipe))</div><div class='ctx'> 			out-&gt;OutputEncoder[location] = dml_dp2p0;</div><div class='ctx'> 		break;</div><div class='del'>-		out-&gt;OutputEncoder[location] = dml_edp;</div><div class='ctx'> 	case SIGNAL_TYPE_EDP:</div><div class='add'>+		out-&gt;OutputEncoder[location] = dml_edp;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SIGNAL_TYPE_HDMI_TYPE_A:</div><div class='ctx'> 	case SIGNAL_TYPE_DVI_SINGLE_LINK:</div><div class='hunk'>@@ -1029,8 +1049,10 @@ static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2,</div><div class='ctx'> </div><div class='ctx'> void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)</div><div class='ctx'> {</div><div class='del'>-	int i = 0, j = 0;</div><div class='add'>+	int i = 0, j = 0, k = 0;</div><div class='ctx'> 	int disp_cfg_stream_location, disp_cfg_plane_location;</div><div class='add'>+	enum mall_stream_type stream_mall_type;</div><div class='add'>+	struct pipe_ctx *current_pipe_context;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {</div><div class='ctx'> 		dml2-&gt;v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;</div><div class='hunk'>@@ -1040,14 +1062,27 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	//Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file</div><div class='del'>-	dml_dispcfg-&gt;plane.GPUVMEnable = true;</div><div class='del'>-	dml_dispcfg-&gt;plane.GPUVMMaxPageTableLevels = 4;</div><div class='del'>-	dml_dispcfg-&gt;plane.HostVMEnable = false;</div><div class='add'>+	dml_dispcfg-&gt;plane.GPUVMEnable = dml2-&gt;v20.dml_core_ctx.ip.gpuvm_enable;</div><div class='add'>+	dml_dispcfg-&gt;plane.GPUVMMaxPageTableLevels = dml2-&gt;v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;</div><div class='add'>+	dml_dispcfg-&gt;plane.HostVMEnable = dml2-&gt;v20.dml_core_ctx.ip.hostvm_enable;</div><div class='add'>+	dml_dispcfg-&gt;plane.HostVMMaxPageTableLevels = dml2-&gt;v20.dml_core_ctx.ip.hostvm_max_page_table_levels;</div><div class='add'>+	if (dml2-&gt;v20.dml_core_ctx.ip.hostvm_enable)</div><div class='add'>+		dml2-&gt;v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;</div><div class='ctx'> </div><div class='ctx'> 	dml2_populate_pipe_to_plane_index_mapping(dml2, context);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; context-&gt;stream_count; i++) {</div><div class='add'>+		current_pipe_context = NULL;</div><div class='add'>+		for (k = 0; k &lt; MAX_PIPES; k++) {</div><div class='add'>+			/* find one pipe allocated to this stream for the purpose of getting</div><div class='add'>+			info about the link later */</div><div class='add'>+			if (context-&gt;streams[i] == context-&gt;res_ctx.pipe_ctx[k].stream) {</div><div class='add'>+				current_pipe_context = &amp;context-&gt;res_ctx.pipe_ctx[k];</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context-&gt;streams[i], dml_dispcfg);</div><div class='add'>+		stream_mall_type = dc_state_get_stream_subvp_type(context, context-&gt;streams[i]);</div><div class='ctx'> </div><div class='ctx'> 		if (disp_cfg_stream_location &lt; 0)</div><div class='ctx'> 			disp_cfg_stream_location = dml_dispcfg-&gt;num_timings++;</div><div class='hunk'>@@ -1055,7 +1090,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 		ASSERT(disp_cfg_stream_location &gt;= 0 &amp;&amp; disp_cfg_stream_location &lt;= __DML2_WRAPPER_MAX_STREAMS_PLANES__);</div><div class='ctx'> </div><div class='ctx'> 		populate_dml_timing_cfg_from_stream_state(&amp;dml_dispcfg-&gt;timing, disp_cfg_stream_location, context-&gt;streams[i]);</div><div class='del'>-		populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_stream_location, context-&gt;streams[i], &amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+		populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_stream_location, context-&gt;streams[i], current_pipe_context);</div><div class='ctx'> 		switch (context-&gt;streams[i]-&gt;debug.force_odm_combine_segments) {</div><div class='ctx'> 		case 2:</div><div class='ctx'> 			dml2-&gt;v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;</div><div class='hunk'>@@ -1092,10 +1127,10 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 				populate_dml_surface_cfg_from_plane_state(dml2-&gt;v20.dml_core_ctx.project, &amp;dml_dispcfg-&gt;surface, disp_cfg_plane_location, context-&gt;stream_status[i].plane_states[j]);</div><div class='ctx'> 				populate_dml_plane_cfg_from_plane_state(&amp;dml_dispcfg-&gt;plane, disp_cfg_plane_location, context-&gt;stream_status[i].plane_states[j], context);</div><div class='ctx'> </div><div class='del'>-				if (context-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+				if (stream_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 					dml_dispcfg-&gt;plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;</div><div class='ctx'> 					dml_dispcfg-&gt;plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;</div><div class='del'>-				} else if (context-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				} else if (stream_mall_type == SUBVP_PHANTOM) {</div><div class='ctx'> 					dml_dispcfg-&gt;plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;</div><div class='ctx'> 					dml_dispcfg-&gt;plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable;</div><div class='ctx'> 					dml2-&gt;v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required;</div><div class='hunk'>@@ -1112,7 +1147,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> </div><div class='ctx'> 				if (j &gt;= 1) {</div><div class='ctx'> 					populate_dml_timing_cfg_from_stream_state(&amp;dml_dispcfg-&gt;timing, disp_cfg_plane_location, context-&gt;streams[i]);</div><div class='del'>-					populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_plane_location, context-&gt;streams[i], &amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+					populate_dml_output_cfg_from_stream_state(&amp;dml_dispcfg-&gt;output, disp_cfg_plane_location, context-&gt;streams[i], current_pipe_context);</div><div class='ctx'> 					switch (context-&gt;streams[i]-&gt;debug.force_odm_combine_segments) {</div><div class='ctx'> 					case 2:</div><div class='ctx'> 						dml2-&gt;v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;</div><div class='hunk'>@@ -1124,9 +1159,9 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat</div><div class='ctx'> 						break;</div><div class='ctx'> 					}</div><div class='ctx'> </div><div class='del'>-					if (context-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_MAIN)</div><div class='add'>+					if (stream_mall_type == SUBVP_MAIN)</div><div class='ctx'> 						dml_dispcfg-&gt;plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;</div><div class='del'>-					else if (context-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+					else if (stream_mall_type == SUBVP_PHANTOM)</div><div class='ctx'> 						dml_dispcfg-&gt;plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;</div><div class='ctx'> </div><div class='ctx'> 					dml2-&gt;v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context-&gt;streams[i]-&gt;stream_id;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c<br/>index 2498b8341199..1068b962d1c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c</a></div><div class='hunk'>@@ -155,8 +155,20 @@ unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, e</div><div class='ctx'> </div><div class='ctx'> bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='add'>+	if (pipe_ctx == NULL || pipe_ctx-&gt;stream == NULL)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	/* If this assert is hit then we have a link encoder dynamic management issue */</div><div class='ctx'> 	ASSERT(pipe_ctx-&gt;stream_res.hpo_dp_stream_enc ? pipe_ctx-&gt;link_res.hpo_dp_link_enc != NULL : true);</div><div class='add'>+</div><div class='add'>+	/* Count MST hubs once by treating only 1st remote sink in topology as an encoder */</div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;link &amp;&amp; pipe_ctx-&gt;stream-&gt;link-&gt;remote_sinks[0]) {</div><div class='add'>+		return (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='add'>+			pipe_ctx-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='add'>+			dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal) &amp;&amp;</div><div class='add'>+			(pipe_ctx-&gt;stream-&gt;link-&gt;remote_sinks[0]-&gt;sink_id == pipe_ctx-&gt;stream-&gt;sink-&gt;sink_id));</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return (pipe_ctx-&gt;stream_res.hpo_dp_stream_enc &amp;&amp;</div><div class='ctx'> 		pipe_ctx-&gt;link_res.hpo_dp_link_enc &amp;&amp;</div><div class='ctx'> 		dc_is_dp_signal(pipe_ctx-&gt;stream-&gt;signal));</div><div class='hunk'>@@ -275,6 +287,7 @@ static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, str</div><div class='ctx'> void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id;</div><div class='add'>+	enum mall_stream_type pipe_mall_type;</div><div class='ctx'> 	bool unbounded_req_enabled = false;</div><div class='ctx'> 	struct dml2_calculate_rq_and_dlg_params_scratch *s = &amp;in_ctx-&gt;v20.scratch.calculate_rq_and_dlg_params_scratch;</div><div class='ctx'> </div><div class='hunk'>@@ -322,7 +335,8 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> 		 */</div><div class='ctx'> 		populate_pipe_ctx_dlg_params_from_dml(&amp;context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index], &amp;context-&gt;bw_ctx.dml2-&gt;v20.dml_core_ctx, dml_pipe_idx);</div><div class='ctx'> </div><div class='del'>-		if (context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		pipe_mall_type = dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index]);</div><div class='add'>+		if (pipe_mall_type == SUBVP_PHANTOM) {</div><div class='ctx'> 			// Phantom pipe requires that DET_SIZE = 0 and no unbounded requests</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0;</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false;</div><div class='hunk'>@@ -349,7 +363,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe-&gt;plane_state) &amp;&amp;</div><div class='ctx'> 			context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) {</div><div class='ctx'> 			/* SS: all active surfaces stored in MALL */</div><div class='del'>-			if (context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+			if (pipe_mall_type != SUBVP_PHANTOM) {</div><div class='ctx'> 				context-&gt;bw_ctx.bw.dcn.mall_ss_size_bytes += context-&gt;res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				/* SUBVP: phantom surfaces only stored in MALL */</div><div class='hunk'>@@ -468,7 +482,7 @@ bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc</div><div class='ctx'> 	return need_recalculation;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool dml2_is_stereo_timing(struct dc_stream_state *stream)</div><div class='add'>+bool dml2_is_stereo_timing(const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	bool is_stereo = false;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h<br/>index 23b9028337d4..5842d6d3c4b6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h</a></div><div class='hunk'>@@ -42,7 +42,7 @@ void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_st</div><div class='ctx'> void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);</div><div class='ctx'> int dml2_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id);</div><div class='ctx'> bool is_dtbclk_required(const struct dc *dc, struct dc_state *context);</div><div class='del'>-bool dml2_is_stereo_timing(struct dc_stream_state *stream);</div><div class='add'>+bool dml2_is_stereo_timing(const struct dc_stream_state *stream);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * dml2_dc_construct_pipes - This function will determine if we need additional pipes based</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c<br/>index 8f231418870f..26307e599614 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c</a></div><div class='hunk'>@@ -418,7 +418,7 @@ static int find_drr_eligible_stream(struct dc_state *display_state)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; display_state-&gt;stream_count; i++) {</div><div class='del'>-		if (display_state-&gt;streams[i]-&gt;mall_stream_config.type == SUBVP_NONE</div><div class='add'>+		if (dc_state_get_stream_subvp_type(display_state, display_state-&gt;streams[i]) == SUBVP_NONE</div><div class='ctx'> 			&amp;&amp; display_state-&gt;streams[i]-&gt;ignore_msa_timing_param) {</div><div class='ctx'> 			// Use ignore_msa_timing_param flag to identify as DRR</div><div class='ctx'> 			return i;</div><div class='hunk'>@@ -634,6 +634,8 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s</div><div class='ctx'> 		dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.b, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='ctx'> 		memcpy(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.c, &amp;dml2-&gt;v20.g6_temp_read_watermark_set, sizeof(context-&gt;bw_ctx.bw.dcn.watermarks.c));</div><div class='ctx'> 		dml2_extract_watermark_set(&amp;context-&gt;bw_ctx.bw.dcn.watermarks.d, &amp;dml2-&gt;v20.dml_core_ctx);</div><div class='add'>+		//copy for deciding zstate use</div><div class='add'>+		context-&gt;bw_ctx.dml.vba.StutterPeriod = context-&gt;bw_ctx.dml2-&gt;v20.dml_core_ctx.mp.StutterPeriod;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return result;</div><div class='hunk'>@@ -691,10 +693,15 @@ bool dml2_validate(const struct dc *in_dc, struct dc_state *context, bool fast_v</div><div class='ctx'> 	return out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline struct dml2_context *dml2_allocate_memory(void)</div><div class='add'>+{</div><div class='add'>+	return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)</div><div class='ctx'> {</div><div class='ctx'> 	// Allocate Mode Lib Ctx</div><div class='del'>-	*dml2 = (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL);</div><div class='add'>+	*dml2 = dml2_allocate_memory();</div><div class='ctx'> </div><div class='ctx'> 	if (!(*dml2))</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -745,3 +752,25 @@ void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2,</div><div class='ctx'> 	*fclk_change_support = (unsigned int) dml2-&gt;v20.dml_core_ctx.ms.support.FCLKChangeSupport[0];</div><div class='ctx'> 	*dram_clk_change_support = (unsigned int) dml2-&gt;v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dml2_copy(struct dml2_context *dst_dml2,</div><div class='add'>+	struct dml2_context *src_dml2)</div><div class='add'>+{</div><div class='add'>+	/* copy Mode Lib Ctx */</div><div class='add'>+	memcpy(dst_dml2, src_dml2, sizeof(struct dml2_context));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool dml2_create_copy(struct dml2_context **dst_dml2,</div><div class='add'>+	struct dml2_context *src_dml2)</div><div class='add'>+{</div><div class='add'>+	/* Allocate Mode Lib Ctx */</div><div class='add'>+	*dst_dml2 = dml2_allocate_memory();</div><div class='add'>+</div><div class='add'>+	if (!(*dst_dml2))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* copy Mode Lib Ctx */</div><div class='add'>+	dml2_copy(*dst_dml2, src_dml2);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h<br/>index 317f90776d97..ee0eb184eb6d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h</a></div><div class='hunk'>@@ -93,15 +93,34 @@ struct dml2_dc_callbacks {</div><div class='ctx'> struct dml2_dc_svp_callbacks {</div><div class='ctx'> 	struct dc *dc;</div><div class='ctx'> 	bool (*build_scaling_params)(struct pipe_ctx *pipe_ctx);</div><div class='del'>-	struct dc_stream_state* (*create_stream_for_sink)(struct dc_sink *dc_sink_data);</div><div class='del'>-	struct dc_plane_state* (*create_plane)(struct dc *dc);</div><div class='del'>-	enum dc_status (*add_stream_to_ctx)(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);</div><div class='del'>-	bool (*add_plane_to_context)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);</div><div class='del'>-	bool (*remove_plane_from_context)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);</div><div class='del'>-	enum dc_status (*remove_stream_from_ctx)(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream);</div><div class='del'>-	void (*plane_state_release)(struct dc_plane_state *plane_state);</div><div class='del'>-	void (*stream_release)(struct dc_stream_state *stream);</div><div class='add'>+	struct dc_stream_state* (*create_phantom_stream)(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_stream_state *main_stream);</div><div class='add'>+	struct dc_plane_state* (*create_phantom_plane)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_plane_state *main_plane);</div><div class='add'>+	enum dc_status (*add_phantom_stream)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_stream_state *phantom_stream,</div><div class='add'>+			struct dc_stream_state *main_stream);</div><div class='add'>+	bool (*add_phantom_plane)(const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, struct dc_state *context);</div><div class='add'>+	bool (*remove_phantom_plane)(const struct dc *dc,</div><div class='add'>+			struct dc_stream_state *stream,</div><div class='add'>+			struct dc_plane_state *plane_state,</div><div class='add'>+			struct dc_state *context);</div><div class='add'>+	enum dc_status (*remove_phantom_stream)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_stream_state *stream);</div><div class='add'>+	void (*release_phantom_plane)(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_plane_state *plane);</div><div class='add'>+	void (*release_phantom_stream)(const struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='add'>+			struct dc_stream_state *stream);</div><div class='ctx'> 	void (*release_dsc)(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc);</div><div class='add'>+	enum mall_stream_type (*get_pipe_subvp_type)(const struct dc_state *state, const struct pipe_ctx *pipe_ctx);</div><div class='add'>+	enum mall_stream_type (*get_stream_subvp_type)(const struct dc_state *state, const struct dc_stream_state *stream);</div><div class='add'>+	struct dc_stream_state *(*get_paired_subvp_stream)(const struct dc_state *state, const struct dc_stream_state *stream);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dml2_clks_table_entry {</div><div class='hunk'>@@ -139,6 +158,8 @@ struct dml2_soc_bbox_overrides {</div><div class='ctx'> 	double urgent_latency_us;</div><div class='ctx'> 	double sr_exit_latency_us;</div><div class='ctx'> 	double sr_enter_plus_exit_latency_us;</div><div class='add'>+	double sr_exit_z8_time_us;</div><div class='add'>+	double sr_enter_plus_exit_z8_time_us;</div><div class='ctx'> 	double dram_clock_change_latency_us;</div><div class='ctx'> 	double fclk_change_latency_us;</div><div class='ctx'> 	unsigned int dram_num_chan;</div><div class='hunk'>@@ -189,6 +210,10 @@ bool dml2_create(const struct dc *in_dc,</div><div class='ctx'> 				 struct dml2_context **dml2);</div><div class='ctx'> </div><div class='ctx'> void dml2_destroy(struct dml2_context *dml2);</div><div class='add'>+void dml2_copy(struct dml2_context *dst_dml2,</div><div class='add'>+	struct dml2_context *src_dml2);</div><div class='add'>+bool dml2_create_copy(struct dml2_context **dst_dml2,</div><div class='add'>+	struct dml2_context *src_dml2);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * dml2_validate - Determines if a display configuration is supported or not.</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile<br/>index a2537229ee88..b183ba5a692e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/Makefile</a></div><div class='hunk'>@@ -1,8 +1,34 @@</div><div class='ctx'> # SPDX-License-Identifier: MIT</div><div class='ctx'> #</div><div class='ctx'> # Makefile for the 'dsc' sub-component of DAL.</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN20</div><div class='add'>+###############################################################################</div><div class='add'>+DSC_DCN20 = dcn20_dsc.o</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN35</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+DSC_DCN35 = dcn35_dsc.o</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_DSC)</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c<br/>index e8b5f17beb96..0df6c55eb326 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c</a></div><div class='hunk'>@@ -331,8 +331,9 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,</div><div class='ctx'> 		int buff_block_size;</div><div class='ctx'> 		int buff_size;</div><div class='ctx'> </div><div class='del'>-		if (!dsc_buff_block_size_from_dpcd(dpcd_dsc_basic_data[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT],</div><div class='del'>-										   &amp;buff_block_size))</div><div class='add'>+		if (!dsc_buff_block_size_from_dpcd(</div><div class='add'>+				dpcd_dsc_basic_data[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT] &amp; 0x03,</div><div class='add'>+				&amp;buff_block_size))</div><div class='ctx'> 			return false;</div><div class='ctx'> </div><div class='ctx'> 		buff_size = dpcd_dsc_basic_data[DP_DSC_RC_BUF_SIZE - DP_DSC_SUPPORT] + 1;</div><div class='hunk'>@@ -357,10 +358,15 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	{</div><div class='ctx'> 		int dpcd_throughput = dpcd_dsc_basic_data[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];</div><div class='add'>+		int dsc_throughput_granular_delta;</div><div class='add'>+</div><div class='add'>+		dsc_throughput_granular_delta = dpcd_dsc_basic_data[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT] &gt;&gt; 3;</div><div class='add'>+		dsc_throughput_granular_delta *= 2;</div><div class='ctx'> </div><div class='ctx'> 		if (!dsc_throughput_from_dpcd(dpcd_throughput &amp; DP_DSC_THROUGHPUT_MODE_0_MASK,</div><div class='ctx'> 									  &amp;dsc_sink_caps-&gt;throughput_mode_0_mps))</div><div class='ctx'> 			return false;</div><div class='add'>+		dsc_sink_caps-&gt;throughput_mode_0_mps += dsc_throughput_granular_delta;</div><div class='ctx'> </div><div class='ctx'> 		dpcd_throughput = (dpcd_throughput &amp; DP_DSC_THROUGHPUT_MODE_1_MASK) &gt;&gt; DP_DSC_THROUGHPUT_MODE_1_SHIFT;</div><div class='ctx'> 		if (!dsc_throughput_from_dpcd(dpcd_throughput, &amp;dsc_sink_caps-&gt;throughput_mode_1_mps))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c<br/>index c9ae2d8f0096..c9ae2d8f0096 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h<br/>index ba869387c3c5..ba869387c3c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c<br/>index 71d2dff9986d..71d2dff9986d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h<br/>index 133ad38842cc..133ad38842cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h<br/>index 4b27f29d0d80..4b27f29d0d80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dsc/dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/dsc/dsc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile<br/>index bccd46bd1815..254136f8e3f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/Makefile</a></div><div class='hunk'>@@ -78,7 +78,7 @@ ifdef CONFIG_DRM_AMD_DC_FP</div><div class='ctx'> # DCN</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN10 = dcn10_hwseq.o</div><div class='add'>+HWSS_DCN10 = dcn10_hwseq.o dcn10_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN10 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn10/,$(HWSS_DCN10))</div><div class='ctx'> </div><div class='hunk'>@@ -86,7 +86,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN10)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN20 = dcn20_hwseq.o</div><div class='add'>+HWSS_DCN20 = dcn20_hwseq.o dcn20_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN20 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn20/,$(HWSS_DCN20))</div><div class='ctx'> </div><div class='hunk'>@@ -94,7 +94,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN20)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN201 = dcn201_hwseq.o</div><div class='add'>+HWSS_DCN201 = dcn201_hwseq.o dcn201_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN201 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn201/,$(HWSS_DCN201))</div><div class='ctx'> </div><div class='hunk'>@@ -102,7 +102,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN201)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN21 = dcn21_hwseq.o</div><div class='add'>+HWSS_DCN21 = dcn21_hwseq.o dcn21_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN21 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn21/,$(HWSS_DCN21))</div><div class='ctx'> </div><div class='hunk'>@@ -114,7 +114,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN21)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN30 = dcn30_hwseq.o</div><div class='add'>+HWSS_DCN30 = dcn30_hwseq.o dcn30_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN30 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn30/,$(HWSS_DCN30))</div><div class='ctx'> </div><div class='hunk'>@@ -122,7 +122,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN30)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN301 = dcn301_hwseq.o</div><div class='add'>+HWSS_DCN301 = dcn301_hwseq.o dcn301_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN301 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn301/,$(HWSS_DCN301))</div><div class='ctx'> </div><div class='hunk'>@@ -130,15 +130,17 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN301)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN302 = dcn302_hwseq.o</div><div class='add'>+HWSS_DCN302 = dcn302_hwseq.o dcn302_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN302 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn302/,$(HWSS_DCN302))</div><div class='ctx'> </div><div class='ctx'> AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN302)</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN303 = dcn303_hwseq.o</div><div class='add'>+HWSS_DCN303 = dcn303_hwseq.o dcn303_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN303 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn303/,$(HWSS_DCN303))</div><div class='ctx'> </div><div class='hunk'>@@ -146,7 +148,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN303)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN31 = dcn31_hwseq.o</div><div class='add'>+HWSS_DCN31 = dcn31_hwseq.o dcn31_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN31 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn31/,$(HWSS_DCN31))</div><div class='ctx'> </div><div class='hunk'>@@ -154,7 +156,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN31)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN314 = dcn314_hwseq.o</div><div class='add'>+HWSS_DCN314 = dcn314_hwseq.o dcn314_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN314 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn314/,$(HWSS_DCN314))</div><div class='ctx'> </div><div class='hunk'>@@ -162,7 +164,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN314)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN32 = dcn32_hwseq.o</div><div class='add'>+HWSS_DCN32 = dcn32_hwseq.o dcn32_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN32 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn32/,$(HWSS_DCN32))</div><div class='ctx'> </div><div class='hunk'>@@ -170,7 +172,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN32)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-HWSS_DCN35 = dcn35_hwseq.o</div><div class='add'>+HWSS_DCN35 = dcn35_hwseq.o dcn35_init.o</div><div class='ctx'> </div><div class='ctx'> AMD_DAL_HWSS_DCN35 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn35/,$(HWSS_DCN35))</div><div class='ctx'> </div><div class='hunk'>@@ -180,4 +182,4 @@ AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN35)</div><div class='ctx'> </div><div class='ctx'> ###############################################################################</div><div class='ctx'> </div><div class='del'>-endif
\ No newline at end of file</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h<br/>index 44b4df6469d1..52f045cfd52a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h</a></div><div class='hunk'>@@ -682,6 +682,7 @@ struct dce_hwseq_registers {</div><div class='ctx'> 	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;</div><div class='ctx'> 	uint32_t HPO_TOP_HW_CONTROL;</div><div class='ctx'> 	uint32_t DMU_CLK_CNTL;</div><div class='add'>+	uint32_t DCCG_GATE_DISABLE_CNTL4;</div><div class='ctx'> 	uint32_t DCCG_GATE_DISABLE_CNTL5;</div><div class='ctx'> };</div><div class='ctx'>  /* set field name */</div><div class='hunk'>@@ -1199,7 +1200,19 @@ struct dce_hwseq_registers {</div><div class='ctx'> 	type PHYBSYMCLK_ROOT_GATE_DISABLE;\</div><div class='ctx'> 	type PHYCSYMCLK_ROOT_GATE_DISABLE;\</div><div class='ctx'> 	type PHYDSYMCLK_ROOT_GATE_DISABLE;\</div><div class='del'>-	type PHYESYMCLK_ROOT_GATE_DISABLE;</div><div class='add'>+	type PHYESYMCLK_ROOT_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P0_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P1_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P2_GATE_DISABLE;\</div><div class='add'>+	type DTBCLK_P3_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK0_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK1_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK2_GATE_DISABLE;\</div><div class='add'>+	type DPSTREAMCLK3_GATE_DISABLE;\</div><div class='add'>+	type DPIASYMCLK0_GATE_DISABLE;\</div><div class='add'>+	type DPIASYMCLK1_GATE_DISABLE;\</div><div class='add'>+	type DPIASYMCLK2_GATE_DISABLE;\</div><div class='add'>+	type DPIASYMCLK3_GATE_DISABLE;</div><div class='ctx'> </div><div class='ctx'> struct dce_hwseq_shift {</div><div class='ctx'> 	HWSEQ_REG_FIELD_LIST(uint8_t)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c<br/>index 960a55e06375..5660f15da291 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c</a></div><div class='hunk'>@@ -55,6 +55,7 @@</div><div class='ctx'> #include "audio.h"</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "panel_cntl.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> #include "dpcd_defs.h"</div><div class='ctx'> /* include DCE11 register header files */</div><div class='ctx'> #include "dce/dce_11_0_d.h"</div><div class='hunk'>@@ -790,7 +791,7 @@ void dce110_edp_power_control(</div><div class='ctx'> 	struct dc_context *ctx = link-&gt;ctx;</div><div class='ctx'> 	struct bp_transmitter_control cntl = { 0 };</div><div class='ctx'> 	enum bp_result bp_result;</div><div class='del'>-	uint8_t panel_instance;</div><div class='add'>+	uint8_t pwrseq_instance;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	if (dal_graphics_object_id_get_connector_id(link-&gt;link_enc-&gt;connector)</div><div class='hunk'>@@ -873,7 +874,7 @@ void dce110_edp_power_control(</div><div class='ctx'> 		cntl.coherent = false;</div><div class='ctx'> 		cntl.lanes_number = LANE_COUNT_FOUR;</div><div class='ctx'> 		cntl.hpd_sel = link-&gt;link_enc-&gt;hpd_source;</div><div class='del'>-		panel_instance = link-&gt;panel_cntl-&gt;inst;</div><div class='add'>+		pwrseq_instance = link-&gt;panel_cntl-&gt;pwrseq_inst;</div><div class='ctx'> </div><div class='ctx'> 		if (ctx-&gt;dc-&gt;ctx-&gt;dmub_srv &amp;&amp;</div><div class='ctx'> 				ctx-&gt;dc-&gt;debug.dmub_command_table) {</div><div class='hunk'>@@ -881,11 +882,11 @@ void dce110_edp_power_control(</div><div class='ctx'> 			if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {</div><div class='ctx'> 				bp_result = ctx-&gt;dc_bios-&gt;funcs-&gt;enable_lvtma_control(ctx-&gt;dc_bios,</div><div class='ctx'> 						LVTMA_CONTROL_POWER_ON,</div><div class='del'>-						panel_instance, link-&gt;link_powered_externally);</div><div class='add'>+						pwrseq_instance, link-&gt;link_powered_externally);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				bp_result = ctx-&gt;dc_bios-&gt;funcs-&gt;enable_lvtma_control(ctx-&gt;dc_bios,</div><div class='ctx'> 						LVTMA_CONTROL_POWER_OFF,</div><div class='del'>-						panel_instance, link-&gt;link_powered_externally);</div><div class='add'>+						pwrseq_instance, link-&gt;link_powered_externally);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -956,7 +957,7 @@ void dce110_edp_backlight_control(</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_context *ctx = link-&gt;ctx;</div><div class='ctx'> 	struct bp_transmitter_control cntl = { 0 };</div><div class='del'>-	uint8_t panel_instance;</div><div class='add'>+	uint8_t pwrseq_instance;</div><div class='ctx'> 	unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;</div><div class='ctx'> 	unsigned int post_T7_delay = OLED_POST_T7_DELAY;</div><div class='ctx'> </div><div class='hunk'>@@ -1009,7 +1010,7 @@ void dce110_edp_backlight_control(</div><div class='ctx'> 	 */</div><div class='ctx'> 	/* dc_service_sleep_in_milliseconds(50); */</div><div class='ctx'> 		/*edp 1.2*/</div><div class='del'>-	panel_instance = link-&gt;panel_cntl-&gt;inst;</div><div class='add'>+	pwrseq_instance = link-&gt;panel_cntl-&gt;pwrseq_inst;</div><div class='ctx'> </div><div class='ctx'> 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {</div><div class='ctx'> 		if (!link-&gt;dc-&gt;config.edp_no_power_sequencing)</div><div class='hunk'>@@ -1034,11 +1035,11 @@ void dce110_edp_backlight_control(</div><div class='ctx'> 		if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)</div><div class='ctx'> 			ctx-&gt;dc_bios-&gt;funcs-&gt;enable_lvtma_control(ctx-&gt;dc_bios,</div><div class='ctx'> 					LVTMA_CONTROL_LCD_BLON,</div><div class='del'>-					panel_instance, link-&gt;link_powered_externally);</div><div class='add'>+					pwrseq_instance, link-&gt;link_powered_externally);</div><div class='ctx'> 		else</div><div class='ctx'> 			ctx-&gt;dc_bios-&gt;funcs-&gt;enable_lvtma_control(ctx-&gt;dc_bios,</div><div class='ctx'> 					LVTMA_CONTROL_LCD_BLOFF,</div><div class='del'>-					panel_instance, link-&gt;link_powered_externally);</div><div class='add'>+					pwrseq_instance, link-&gt;link_powered_externally);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	link_transmitter_control(ctx-&gt;dc_bios, &amp;cntl);</div><div class='hunk'>@@ -1353,7 +1354,7 @@ static void build_audio_output(</div><div class='ctx'> 	if (state-&gt;clk_mgr &amp;&amp;</div><div class='ctx'> 		(pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT ||</div><div class='ctx'> 			pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {</div><div class='del'>-		audio_output-&gt;pll_info.dp_dto_source_clock_in_khz =</div><div class='add'>+		audio_output-&gt;pll_info.audio_dto_source_clock_in_khz =</div><div class='ctx'> 				state-&gt;clk_mgr-&gt;funcs-&gt;get_dp_ref_clk_frequency(</div><div class='ctx'> 						state-&gt;clk_mgr);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1596,7 +1597,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(</div><div class='ctx'> 	 * is constructed with the same sink). Make sure not to override</div><div class='ctx'> 	 * and link programming on the main.</div><div class='ctx'> 	 */</div><div class='del'>-	if (pipe_ctx-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+	if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;link-&gt;psr_settings.psr_feature_enabled = false;</div><div class='ctx'> 		pipe_ctx-&gt;stream-&gt;link-&gt;replay_settings.replay_feature_enabled = false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1684,7 +1685,7 @@ static void disable_vga_and_power_gate_all_controllers(</div><div class='ctx'> 				true);</div><div class='ctx'> </div><div class='ctx'> 		dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].pipe_idx = i;</div><div class='del'>-		dc-&gt;hwss.disable_plane(dc,</div><div class='add'>+		dc-&gt;hwss.disable_plane(dc, dc-&gt;current_state,</div><div class='ctx'> 			&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2124,7 +2125,8 @@ static void dce110_reset_hw_ctx_wrap(</div><div class='ctx'> 				BREAK_TO_DEBUGGER();</div><div class='ctx'> 			}</div><div class='ctx'> 			pipe_ctx_old-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe_ctx_old-&gt;stream_res.tg);</div><div class='del'>-			pipe_ctx_old-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='add'>+			if (dc_is_hdmi_tmds_signal(pipe_ctx_old-&gt;stream-&gt;signal))</div><div class='add'>+				pipe_ctx_old-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> 			pipe_ctx_old-&gt;plane_res.mi-&gt;funcs-&gt;free_mem_input(</div><div class='ctx'> 					pipe_ctx_old-&gt;plane_res.mi, dc-&gt;current_state-&gt;stream_count);</div><div class='ctx'> </div><div class='hunk'>@@ -2133,7 +2135,7 @@ static void dce110_reset_hw_ctx_wrap(</div><div class='ctx'> 										old_clk))</div><div class='ctx'> 				old_clk-&gt;funcs-&gt;cs_power_down(old_clk);</div><div class='ctx'> </div><div class='del'>-			dc-&gt;hwss.disable_plane(dc, pipe_ctx_old);</div><div class='add'>+			dc-&gt;hwss.disable_plane(dc, dc-&gt;current_state, pipe_ctx_old);</div><div class='ctx'> </div><div class='ctx'> 			pipe_ctx_old-&gt;stream = NULL;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2497,6 +2499,7 @@ static bool wait_for_reset_trigger_to_occur(</div><div class='ctx'> /* Enable timing synchronization for a group of Timing Generators. */</div><div class='ctx'> static void dce110_enable_timing_synchronization(</div><div class='ctx'> 		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='ctx'> 		int group_index,</div><div class='ctx'> 		int group_size,</div><div class='ctx'> 		struct pipe_ctx *grouped_pipes[])</div><div class='hunk'>@@ -2590,6 +2593,7 @@ static void init_hw(struct dc *dc)</div><div class='ctx'> 	struct dmcu *dmcu;</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> </div><div class='ctx'> 	bp = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='hunk'>@@ -2639,13 +2643,15 @@ static void init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 		struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;panel_cntl)</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='ctx'> 			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	abm = dc-&gt;res_pool-&gt;abm;</div><div class='ctx'> 	if (abm != NULL)</div><div class='del'>-		abm-&gt;funcs-&gt;abm_init(abm, backlight);</div><div class='add'>+		abm-&gt;funcs-&gt;abm_init(abm, backlight, user_level);</div><div class='ctx'> </div><div class='ctx'> 	dmcu = dc-&gt;res_pool-&gt;dmcu;</div><div class='ctx'> 	if (dmcu != NULL &amp;&amp; abm != NULL)</div><div class='hunk'>@@ -2842,7 +2848,7 @@ static void dce110_post_unlock_program_front_end(</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	int fe_idx = pipe_ctx-&gt;plane_res.mi ?</div><div class='hunk'>@@ -3115,7 +3121,8 @@ void dce110_disable_link_output(struct dc_link *link,</div><div class='ctx'> 	struct dmcu *dmcu = dc-&gt;res_pool-&gt;dmcu;</div><div class='ctx'> </div><div class='ctx'> 	if (signal == SIGNAL_TYPE_EDP &amp;&amp;</div><div class='del'>-			link-&gt;dc-&gt;hwss.edp_backlight_control)</div><div class='add'>+			link-&gt;dc-&gt;hwss.edp_backlight_control &amp;&amp;</div><div class='add'>+			!link-&gt;skip_implict_edp_power_control)</div><div class='ctx'> 		link-&gt;dc-&gt;hwss.edp_backlight_control(link, false);</div><div class='ctx'> 	else if (dmcu != NULL &amp;&amp; dmcu-&gt;funcs-&gt;lock_phy)</div><div class='ctx'> 		dmcu-&gt;funcs-&gt;lock_phy(dmcu);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c<br/>index 2b8b8366538e..6dd479e8a348 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c</a></div><div class='hunk'>@@ -56,6 +56,7 @@</div><div class='ctx'> #include "dc_trace.h"</div><div class='ctx'> #include "dce/dmub_outbox.h"</div><div class='ctx'> #include "link.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc_logger</div><div class='hunk'>@@ -115,7 +116,7 @@ void dcn10_lock_all_pipes(struct dc *dc,</div><div class='ctx'> 		    !pipe_ctx-&gt;stream ||</div><div class='ctx'> 		    (!pipe_ctx-&gt;plane_state &amp;&amp; !old_pipe_ctx-&gt;plane_state) ||</div><div class='ctx'> 		    !tg-&gt;funcs-&gt;is_tg_enabled(tg) ||</div><div class='del'>-			pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+			dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (lock)</div><div class='hunk'>@@ -1057,7 +1058,8 @@ static void dcn10_reset_back_end_for_pipe(</div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='ctx'> 					pipe_ctx-&gt;stream_res.tg, NULL);</div><div class='del'>-		pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='add'>+		if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+			pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='hunk'>@@ -1180,7 +1182,9 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* trigger HW to start disconnect plane from stream on the next vsync */</div><div class='del'>-void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn10_plane_atomic_disconnect(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='hunk'>@@ -1200,7 +1204,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	mpc-&gt;funcs-&gt;remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);</div><div class='ctx'> 	// Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle,</div><div class='ctx'> 	// so don't wait for MPCC_IDLE in the programming sequence</div><div class='del'>-	if (opp != NULL &amp;&amp; !pipe_ctx-&gt;plane_state-&gt;is_phantom)</div><div class='add'>+	if (opp != NULL &amp;&amp; dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM)</div><div class='ctx'> 		opp-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;optimized_required = true;</div><div class='hunk'>@@ -1290,7 +1294,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;plane_state = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='hunk'>@@ -1416,12 +1420,12 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;opps[i]-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.opp = dc-&gt;res_pool-&gt;opps[i];</div><div class='ctx'> </div><div class='del'>-		hws-&gt;funcs.plane_atomic_disconnect(dc, pipe_ctx);</div><div class='add'>+		hws-&gt;funcs.plane_atomic_disconnect(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		if (tg-&gt;funcs-&gt;is_tg_enabled(tg))</div><div class='ctx'> 			tg-&gt;funcs-&gt;unlock(tg);</div><div class='ctx'> </div><div class='del'>-		dc-&gt;hwss.disable_plane(dc, pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.disable_plane(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = NULL;</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.hubp = NULL;</div><div class='hunk'>@@ -1486,6 +1490,7 @@ void dcn10_init_hw(struct dc *dc)</div><div class='ctx'> 	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	struct resource_pool *res_pool = dc-&gt;res_pool;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	bool   is_optimized_init_done = false;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='hunk'>@@ -1583,12 +1588,14 @@ void dcn10_init_hw(struct dc *dc)</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 			struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-			if (link-&gt;panel_cntl)</div><div class='add'>+			if (link-&gt;panel_cntl) {</div><div class='ctx'> 				backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+				user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (abm != NULL)</div><div class='del'>-			abm-&gt;funcs-&gt;abm_init(abm, backlight);</div><div class='add'>+			abm-&gt;funcs-&gt;abm_init(abm, backlight, user_level);</div><div class='ctx'> </div><div class='ctx'> 		if (dmcu != NULL &amp;&amp; !dmcu-&gt;auto_load_dmcu)</div><div class='ctx'> 			dmcu-&gt;funcs-&gt;dmcu_init(dmcu);</div><div class='hunk'>@@ -2262,6 +2269,7 @@ void dcn10_enable_vblanks_synchronization(</div><div class='ctx'> </div><div class='ctx'> void dcn10_enable_timing_synchronization(</div><div class='ctx'> 	struct dc *dc,</div><div class='add'>+	struct dc_state *state,</div><div class='ctx'> 	int group_index,</div><div class='ctx'> 	int group_size,</div><div class='ctx'> 	struct pipe_ctx *grouped_pipes[])</div><div class='hunk'>@@ -2276,7 +2284,7 @@ void dcn10_enable_timing_synchronization(</div><div class='ctx'> 	DC_SYNC_INFO("Setting up OTG reset trigger\n");</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; group_size; i++) {</div><div class='del'>-		if (grouped_pipes[i]-&gt;stream &amp;&amp; grouped_pipes[i]-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (grouped_pipes[i]-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, grouped_pipes[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		opp = grouped_pipes[i]-&gt;stream_res.opp;</div><div class='hunk'>@@ -2296,14 +2304,14 @@ void dcn10_enable_timing_synchronization(</div><div class='ctx'> 		if (grouped_pipes[i]-&gt;stream == NULL)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (grouped_pipes[i]-&gt;stream &amp;&amp; grouped_pipes[i]-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (grouped_pipes[i]-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, grouped_pipes[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		grouped_pipes[i]-&gt;stream-&gt;vblank_synchronized = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; group_size; i++) {</div><div class='del'>-		if (grouped_pipes[i]-&gt;stream &amp;&amp; grouped_pipes[i]-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (grouped_pipes[i]-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, grouped_pipes[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		grouped_pipes[i]-&gt;stream_res.tg-&gt;funcs-&gt;enable_reset_trigger(</div><div class='hunk'>@@ -2317,11 +2325,11 @@ void dcn10_enable_timing_synchronization(</div><div class='ctx'> 	 * synchronized. Look at last pipe programmed to reset.</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	if (grouped_pipes[1]-&gt;stream &amp;&amp; grouped_pipes[1]-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM)</div><div class='add'>+	if (grouped_pipes[1]-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, grouped_pipes[1]) != SUBVP_PHANTOM)</div><div class='ctx'> 		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]-&gt;stream_res.tg);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; group_size; i++) {</div><div class='del'>-		if (grouped_pipes[i]-&gt;stream &amp;&amp; grouped_pipes[i]-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (grouped_pipes[i]-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(state, grouped_pipes[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		grouped_pipes[i]-&gt;stream_res.tg-&gt;funcs-&gt;disable_reset_trigger(</div><div class='hunk'>@@ -2329,7 +2337,7 @@ void dcn10_enable_timing_synchronization(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; group_size; i++) {</div><div class='del'>-		if (grouped_pipes[i]-&gt;stream &amp;&amp; grouped_pipes[i]-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(state, grouped_pipes[i]) == SUBVP_PHANTOM)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		opp = grouped_pipes[i]-&gt;stream_res.opp;</div><div class='hunk'>@@ -3021,7 +3029,7 @@ void dcn10_post_unlock_program_front_end(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable)</div><div class='del'>-			dc-&gt;hwss.disable_plane(dc, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			dc-&gt;hwss.disable_plane(dc, dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable) {</div><div class='hunk'>@@ -3417,7 +3425,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 		.h_scale_ratio = pipe_ctx-&gt;plane_res.scl_data.ratios.horz,</div><div class='ctx'> 		.v_scale_ratio = pipe_ctx-&gt;plane_res.scl_data.ratios.vert,</div><div class='ctx'> 		.rotation = pipe_ctx-&gt;plane_state-&gt;rotation,</div><div class='del'>-		.mirror = pipe_ctx-&gt;plane_state-&gt;horizontal_mirror</div><div class='add'>+		.mirror = pipe_ctx-&gt;plane_state-&gt;horizontal_mirror,</div><div class='add'>+		.stream = pipe_ctx-&gt;stream,</div><div class='ctx'> 	};</div><div class='ctx'> 	bool pipe_split_on = false;</div><div class='ctx'> 	bool odm_combine_on = (pipe_ctx-&gt;next_odm_pipe != NULL) ||</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h<br/>index ef6d56da417c..bc5dd68a2408 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h</a></div><div class='hunk'>@@ -75,7 +75,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn10_reset_hw_ctx_wrap(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='del'>-void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn10_lock_all_pipes(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='hunk'>@@ -108,13 +108,16 @@ void dcn10_power_down_on_boot(struct dc *dc);</div><div class='ctx'> enum dc_status dce110_apply_ctx_to_hw(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct dc_state *context);</div><div class='del'>-void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn10_plane_atomic_disconnect(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);</div><div class='ctx'> void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dce110_power_down(struct dc *dc);</div><div class='ctx'> void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);</div><div class='ctx'> void dcn10_enable_timing_synchronization(</div><div class='ctx'> 		struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='ctx'> 		int group_index,</div><div class='ctx'> 		int group_size,</div><div class='ctx'> 		struct pipe_ctx *grouped_pipes[]);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c<br/>index a5bdac79a744..a5bdac79a744 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h<br/>index 8c6fd7b844a4..8c6fd7b844a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c<br/>index 608221b0dd5d..e931342fcf4c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c</a></div><div class='hunk'>@@ -55,6 +55,7 @@</div><div class='ctx'> #include "inc/link_enc_cfg.h"</div><div class='ctx'> #include "link_hwss.h"</div><div class='ctx'> #include "link.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER \</div><div class='ctx'> 	dc_logger</div><div class='hunk'>@@ -623,9 +624,9 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='del'>-	bool is_phantom = pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;is_phantom;</div><div class='add'>+	bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;</div><div class='ctx'> 	struct timing_generator *tg = is_phantom ? pipe_ctx-&gt;stream_res.tg : NULL;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='hunk'>@@ -847,7 +848,7 @@ enum dc_status dcn20_enable_stream_timing(</div><div class='ctx'> 	/* TODO enable stream if timing changed */</div><div class='ctx'> 	/* TODO unblank stream if DP */</div><div class='ctx'> </div><div class='del'>-	if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+	if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {</div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.tg &amp;&amp; pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;phantom_crtc_post_enable(pipe_ctx-&gt;stream_res.tg);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1368,8 +1369,14 @@ void dcn20_pipe_control_lock(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)</div><div class='add'>+static void dcn20_detect_pipe_changes(struct dc_state *old_state,</div><div class='add'>+		struct dc_state *new_state,</div><div class='add'>+		struct pipe_ctx *old_pipe,</div><div class='add'>+		struct pipe_ctx *new_pipe)</div><div class='ctx'> {</div><div class='add'>+	bool old_is_phantom = dc_state_get_pipe_subvp_type(old_state, old_pipe) == SUBVP_PHANTOM;</div><div class='add'>+	bool new_is_phantom = dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM;</div><div class='add'>+</div><div class='ctx'> 	new_pipe-&gt;update_flags.raw = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* If non-phantom pipe is being transitioned to a phantom pipe,</div><div class='hunk'>@@ -1379,8 +1386,8 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx</div><div class='ctx'> 	 * be different). The post_unlock sequence will set the correct</div><div class='ctx'> 	 * update flags to enable the phantom pipe.</div><div class='ctx'> 	 */</div><div class='del'>-	if (old_pipe-&gt;plane_state &amp;&amp; !old_pipe-&gt;plane_state-&gt;is_phantom &amp;&amp;</div><div class='del'>-			new_pipe-&gt;plane_state &amp;&amp; new_pipe-&gt;plane_state-&gt;is_phantom) {</div><div class='add'>+	if (old_pipe-&gt;plane_state &amp;&amp; !old_is_phantom &amp;&amp;</div><div class='add'>+			new_pipe-&gt;plane_state &amp;&amp; new_is_phantom) {</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.disable = 1;</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1400,6 +1407,10 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.scaler = 1;</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.viewport = 1;</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.det_size = 1;</div><div class='add'>+		if (new_pipe-&gt;stream-&gt;test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE &amp;&amp;</div><div class='add'>+				new_pipe-&gt;stream_res.test_pattern_params.width != 0 &amp;&amp;</div><div class='add'>+				new_pipe-&gt;stream_res.test_pattern_params.height != 0)</div><div class='add'>+			new_pipe-&gt;update_flags.bits.test_pattern_changed = 1;</div><div class='ctx'> 		if (!new_pipe-&gt;top_pipe &amp;&amp; !new_pipe-&gt;prev_odm_pipe) {</div><div class='ctx'> 			new_pipe-&gt;update_flags.bits.odm = 1;</div><div class='ctx'> 			new_pipe-&gt;update_flags.bits.global_sync = 1;</div><div class='hunk'>@@ -1412,14 +1423,14 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx</div><div class='ctx'> 	 * The remove-add sequence of the phantom pipe always results in the pipe</div><div class='ctx'> 	 * being blanked in enable_stream_timing (DPG).</div><div class='ctx'> 	 */</div><div class='del'>-	if (new_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM)</div><div class='add'>+	if (new_pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(new_state, new_pipe) == SUBVP_PHANTOM)</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.enable = 1;</div><div class='ctx'> </div><div class='ctx'> 	/* Phantom pipes are effectively disabled, if the pipe was previously phantom</div><div class='ctx'> 	 * we have to enable</div><div class='ctx'> 	 */</div><div class='del'>-	if (old_pipe-&gt;plane_state &amp;&amp; old_pipe-&gt;plane_state-&gt;is_phantom &amp;&amp;</div><div class='del'>-			new_pipe-&gt;plane_state &amp;&amp; !new_pipe-&gt;plane_state-&gt;is_phantom)</div><div class='add'>+	if (old_pipe-&gt;plane_state &amp;&amp; old_is_phantom &amp;&amp;</div><div class='add'>+			new_pipe-&gt;plane_state &amp;&amp; !new_is_phantom)</div><div class='ctx'> 		new_pipe-&gt;update_flags.bits.enable = 1;</div><div class='ctx'> </div><div class='ctx'> 	if (old_pipe-&gt;plane_state &amp;&amp; !new_pipe-&gt;plane_state) {</div><div class='hunk'>@@ -1556,6 +1567,7 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	struct dc_plane_state *plane_state = pipe_ctx-&gt;plane_state;</div><div class='ctx'> 	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='ctx'> 	bool viewport_changed = false;</div><div class='add'>+	enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.dppclk)</div><div class='ctx'> 		dpp-&gt;funcs-&gt;dpp_dppclk_control(dpp, false, true);</div><div class='hunk'>@@ -1701,7 +1713,7 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 		pipe_ctx-&gt;update_flags.bits.plane_changed ||</div><div class='ctx'> 		plane_state-&gt;update_flags.bits.addr_update) {</div><div class='ctx'> 		if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &amp;&amp;</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+				pipe_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 			union block_sequence_params params;</div><div class='ctx'> </div><div class='ctx'> 			params.subvp_save_surf_addr.dc_dmub_srv = dc-&gt;ctx-&gt;dmub_srv;</div><div class='hunk'>@@ -1715,7 +1727,7 @@ static void dcn20_update_dchubp_dpp(</div><div class='ctx'> 	if (pipe_ctx-&gt;update_flags.bits.enable)</div><div class='ctx'> 		hubp-&gt;funcs-&gt;set_blank(hubp, false);</div><div class='ctx'> 	/* If the stream paired with this plane is phantom, the plane is also phantom */</div><div class='del'>-	if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM</div><div class='add'>+	if (pipe_ctx-&gt;stream &amp;&amp; pipe_mall_type == SUBVP_PHANTOM</div><div class='ctx'> 			&amp;&amp; hubp-&gt;funcs-&gt;phantom_hubp_post_enable)</div><div class='ctx'> 		hubp-&gt;funcs-&gt;phantom_hubp_post_enable(hubp);</div><div class='ctx'> }</div><div class='hunk'>@@ -1773,7 +1785,7 @@ static void dcn20_program_pipe(</div><div class='ctx'> 				pipe_ctx-&gt;pipe_dlg_param.vupdate_offset,</div><div class='ctx'> 				pipe_ctx-&gt;pipe_dlg_param.vupdate_width);</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM)</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)</div><div class='ctx'> 			pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe_ctx-&gt;stream_res.tg, CRTC_STATE_VACTIVE);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_vtg_params(</div><div class='hunk'>@@ -1877,6 +1889,8 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='add'>+	unsigned int prev_hubp_count = 0;</div><div class='add'>+	unsigned int hubp_count = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (resource_is_pipe_topology_changed(dc-&gt;current_state, context))</div><div class='ctx'> 		resource_log_pipe_topology_update(dc, context);</div><div class='hunk'>@@ -1894,9 +1908,23 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+		if (dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='add'>+			prev_hubp_count++;</div><div class='add'>+		if (context-&gt;res_ctx.pipe_ctx[i].plane_state)</div><div class='add'>+			hubp_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (prev_hubp_count == 0 &amp;&amp; hubp_count &gt; 0) {</div><div class='add'>+		if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+			dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+					dc-&gt;res_pool-&gt;hubbub, true, false);</div><div class='add'>+		udelay(500);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Set pipe update flags and lock pipes */</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='del'>-		dcn20_detect_pipe_changes(&amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i],</div><div class='add'>+		dcn20_detect_pipe_changes(dc-&gt;current_state, context, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i],</div><div class='ctx'> 				&amp;context-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> </div><div class='ctx'> 	/* When disabling phantom pipes, turn on phantom OTG first (so we can get double</div><div class='hunk'>@@ -1906,15 +1934,16 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 		struct dc_stream_state *stream = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream;</div><div class='ctx'> </div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable &amp;&amp; stream &amp;&amp;</div><div class='del'>-			dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				dc_state_get_pipe_subvp_type(dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {</div><div class='ctx'> 			struct timing_generator *tg = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream_res.tg;</div><div class='ctx'> </div><div class='ctx'> 			if (tg-&gt;funcs-&gt;enable_crtc) {</div><div class='ctx'> 				if (dc-&gt;hwss.blank_phantom) {</div><div class='ctx'> 					int main_pipe_width, main_pipe_height;</div><div class='add'>+					struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(dc-&gt;current_state, dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream);</div><div class='ctx'> </div><div class='del'>-					main_pipe_width = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.paired_stream-&gt;dst.width;</div><div class='del'>-					main_pipe_height = dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].stream-&gt;mall_stream_config.paired_stream-&gt;dst.height;</div><div class='add'>+					main_pipe_width = phantom_stream-&gt;dst.width;</div><div class='add'>+					main_pipe_height = phantom_stream-&gt;dst.height;</div><div class='ctx'> 					dc-&gt;hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);</div><div class='ctx'> 				}</div><div class='ctx'> 				tg-&gt;funcs-&gt;enable_crtc(tg);</div><div class='hunk'>@@ -1943,9 +1972,9 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 			 * DET allocation.</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (hubbub-&gt;funcs-&gt;program_det_size &amp;&amp; (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable ||</div><div class='del'>-					(context-&gt;res_ctx.pipe_ctx[i].plane_state &amp;&amp; context-&gt;res_ctx.pipe_ctx[i].plane_state-&gt;is_phantom)))</div><div class='add'>+					(context-&gt;res_ctx.pipe_ctx[i].plane_state &amp;&amp; dc_state_get_pipe_subvp_type(context, &amp;context-&gt;res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM)))</div><div class='ctx'> 				hubbub-&gt;funcs-&gt;program_det_size(hubbub, dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].plane_res.hubp-&gt;inst, 0);</div><div class='del'>-			hws-&gt;funcs.plane_atomic_disconnect(dc, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			hws-&gt;funcs.plane_atomic_disconnect(dc, dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i].pipe_idx);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1968,7 +1997,7 @@ void dcn20_program_front_end_for_ctx(</div><div class='ctx'> 					 * but the MPO still exists until the double buffered update of the main pipe so we</div><div class='ctx'> 					 * will get a frame of underflow if the phantom pipe is programmed here.</div><div class='ctx'> 					 */</div><div class='del'>-					if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM)</div><div class='add'>+					if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM)</div><div class='ctx'> 						dcn20_program_pipe(dc, pipe, context);</div><div class='ctx'> 				}</div><div class='ctx'> </div><div class='hunk'>@@ -2018,7 +2047,7 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++)</div><div class='ctx'> 		if (context-&gt;res_ctx.pipe_ctx[i].update_flags.bits.disable)</div><div class='del'>-			dc-&gt;hwss.disable_plane(dc, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='add'>+			dc-&gt;hwss.disable_plane(dc, dc-&gt;current_state, &amp;dc-&gt;current_state-&gt;res_ctx.pipe_ctx[i]);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical</div><div class='hunk'>@@ -2030,7 +2059,7 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		// Don't check flip pending on phantom pipes</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; !pipe-&gt;top_pipe &amp;&amp; pipe-&gt;update_flags.bits.enable &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_PHANTOM) {</div><div class='ctx'> 			struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='ctx'> 			int j = 0;</div><div class='ctx'> 			for (j = 0; j &lt; TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us</div><div class='hunk'>@@ -2039,6 +2068,10 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control)</div><div class='add'>+		dc-&gt;res_pool-&gt;hubbub-&gt;funcs-&gt;force_pstate_change_control(</div><div class='add'>+				dc-&gt;res_pool-&gt;hubbub, false, false);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='hunk'>@@ -2049,7 +2082,7 @@ void dcn20_post_unlock_program_front_end(</div><div class='ctx'> 			 * programming sequence).</div><div class='ctx'> 			 */</div><div class='ctx'> 			while (pipe) {</div><div class='del'>-				if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 					/* When turning on the phantom pipe we want to run through the</div><div class='ctx'> 					 * entire enable sequence, so apply all the "enable" flags.</div><div class='ctx'> 					 */</div><div class='hunk'>@@ -2119,7 +2152,7 @@ void dcn20_prepare_bandwidth(</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		// At optimize don't restore the original watermark value</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_NONE) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2163,7 +2196,7 @@ void dcn20_optimize_bandwidth(</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='ctx'> 		// At optimize don't need  to restore the original watermark value</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_NONE) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) != SUBVP_NONE) {</div><div class='ctx'> 			context-&gt;bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2197,7 +2230,8 @@ void dcn20_optimize_bandwidth(</div><div class='ctx'> 			dc-&gt;clk_mgr,</div><div class='ctx'> 			context,</div><div class='ctx'> 			true);</div><div class='del'>-	if (context-&gt;bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) {</div><div class='add'>+	if (context-&gt;bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &amp;&amp;</div><div class='add'>+		!dc-&gt;debug.disable_extblankadj) {</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; ++i) {</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='hunk'>@@ -2590,7 +2624,8 @@ static void dcn20_reset_back_end_for_pipe(</div><div class='ctx'> 		 * the case where the same symclk is shared across multiple otg</div><div class='ctx'> 		 * instances</div><div class='ctx'> 		 */</div><div class='del'>-		link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='add'>+		if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+			link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> 		if (link-&gt;phy_state.symclk_state == SYMCLK_ON_TX_OFF) {</div><div class='ctx'> 			link_hwss-&gt;disable_link_output(link,</div><div class='ctx'> 					&amp;pipe_ctx-&gt;link_res, pipe_ctx-&gt;stream-&gt;signal);</div><div class='hunk'>@@ -2923,7 +2958,7 @@ void dcn20_fpga_init_hw(struct dc *dc)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;opps[i]-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.opp = dc-&gt;res_pool-&gt;opps[i];</div><div class='ctx'> 		/*to do*/</div><div class='del'>-		hws-&gt;funcs.plane_atomic_disconnect(dc, pipe_ctx);</div><div class='add'>+		hws-&gt;funcs.plane_atomic_disconnect(dc, context, pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize DWB pointer to MCIF_WB */</div><div class='hunk'>@@ -2940,7 +2975,7 @@ void dcn20_fpga_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		dc-&gt;hwss.disable_plane(dc, pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.disable_plane(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = NULL;</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.hubp = NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h<br/>index ab02e4e9c8c2..b94c85340abf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h</a></div><div class='hunk'>@@ -52,7 +52,7 @@ void dcn20_program_output_csc(struct dc *dc,</div><div class='ctx'> void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct dc_link_settings *link_settings);</div><div class='del'>-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn20_disable_pixel_data(</div><div class='ctx'> 		struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c<br/>index 884e3e323338..884e3e323338 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h<br/>index 12277797cd71..12277797cd71 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c<br/>index d3fe6092f50e..d5769f38874f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c</a></div><div class='hunk'>@@ -320,7 +320,7 @@ void dcn201_init_hw(struct dc *dc)</div><div class='ctx'> 		res_pool-&gt;opps[i]-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.opp = res_pool-&gt;opps[i];</div><div class='ctx'> 		/*To do: number of MPCC != number of opp*/</div><div class='del'>-		hws-&gt;funcs.plane_atomic_disconnect(dc, pipe_ctx);</div><div class='add'>+		hws-&gt;funcs.plane_atomic_disconnect(dc, context, pipe_ctx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize DWB pointer to MCIF_WB */</div><div class='hunk'>@@ -337,7 +337,7 @@ void dcn201_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		dc-&gt;hwss.disable_plane(dc, pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.disable_plane(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = NULL;</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.hubp = NULL;</div><div class='hunk'>@@ -369,7 +369,9 @@ void dcn201_init_hw(struct dc *dc)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* trigger HW to start disconnect plane from stream on the next vsync */</div><div class='del'>-void dcn201_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn201_plane_atomic_disconnect(struct dc *dc,</div><div class='add'>+		struct dc_state *state,</div><div class='add'>+		struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='ctx'> 	struct hubp *hubp = pipe_ctx-&gt;plane_res.hubp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h<br/>index 26cd62be6418..6a50a9894be6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h</a></div><div class='hunk'>@@ -33,7 +33,7 @@ void dcn201_init_hw(struct dc *dc);</div><div class='ctx'> void dcn201_unblank_stream(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct dc_link_settings *link_settings);</div><div class='ctx'> void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='del'>-void dcn201_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn201_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn201_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn201_set_cursor_attribute(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn201_pipe_control_lock(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c<br/>index a13bf6c9386e..a13bf6c9386e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h<br/>index 1168887b033d..1168887b033d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c<br/>index 467812cf3368..8e88dcaf88f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c</a></div><div class='hunk'>@@ -137,7 +137,8 @@ void dcn21_PLAT_58856_wa(struct dc_state *context, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;dpms_off = true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst)</div><div class='add'>+static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,</div><div class='add'>+		uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd;</div><div class='ctx'> 	struct dc_context *dc = abm-&gt;ctx;</div><div class='hunk'>@@ -147,12 +148,13 @@ static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t optio</div><div class='ctx'> 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;</div><div class='ctx'> 	cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;</div><div class='add'>+	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;</div><div class='ctx'> 	cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;</div><div class='ctx'> 	cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -171,7 +173,7 @@ static void dmub_abm_set_backlight(struct dc_context *dc, uint32_t backlight_pwm</div><div class='ctx'> 	cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 &lt;&lt; panel_inst);</div><div class='ctx'> 	cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)</div><div class='hunk'>@@ -179,7 +181,6 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	struct abm *abm = pipe_ctx-&gt;stream_res.abm;</div><div class='ctx'> 	uint32_t otg_inst = pipe_ctx-&gt;stream_res.tg-&gt;inst;</div><div class='ctx'> 	struct panel_cntl *panel_cntl = pipe_ctx-&gt;stream-&gt;link-&gt;panel_cntl;</div><div class='del'>-</div><div class='ctx'> 	struct dmcu *dmcu = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc-&gt;res_pool-&gt;dmcu;</div><div class='ctx'> </div><div class='ctx'> 	if (dmcu) {</div><div class='hunk'>@@ -190,9 +191,13 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	if (abm &amp;&amp; panel_cntl) {</div><div class='ctx'> 		if (abm-&gt;funcs &amp;&amp; abm-&gt;funcs-&gt;set_pipe_ex) {</div><div class='ctx'> 			abm-&gt;funcs-&gt;set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE,</div><div class='del'>-			panel_cntl-&gt;inst);</div><div class='add'>+					panel_cntl-&gt;inst, panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 		} else {</div><div class='del'>-			dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, panel_cntl-&gt;inst);</div><div class='add'>+				dmub_abm_set_pipe(abm,</div><div class='add'>+						otg_inst,</div><div class='add'>+						SET_ABM_PIPE_IMMEDIATELY_DISABLE,</div><div class='add'>+						panel_cntl-&gt;inst,</div><div class='add'>+						panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 		}</div><div class='ctx'> 		panel_cntl-&gt;funcs-&gt;store_backlight_level(panel_cntl);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -212,9 +217,16 @@ void dcn21_set_pipe(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> </div><div class='ctx'> 	if (abm &amp;&amp; panel_cntl) {</div><div class='ctx'> 		if (abm-&gt;funcs &amp;&amp; abm-&gt;funcs-&gt;set_pipe_ex) {</div><div class='del'>-			abm-&gt;funcs-&gt;set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl-&gt;inst);</div><div class='add'>+			abm-&gt;funcs-&gt;set_pipe_ex(abm,</div><div class='add'>+					otg_inst,</div><div class='add'>+					SET_ABM_PIPE_NORMAL,</div><div class='add'>+					panel_cntl-&gt;inst,</div><div class='add'>+					panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 		} else {</div><div class='del'>-			dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl-&gt;inst);</div><div class='add'>+				dmub_abm_set_pipe(abm, otg_inst,</div><div class='add'>+						SET_ABM_PIPE_NORMAL,</div><div class='add'>+						panel_cntl-&gt;inst,</div><div class='add'>+						panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -237,9 +249,17 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,</div><div class='ctx'> </div><div class='ctx'> 		if (abm &amp;&amp; panel_cntl) {</div><div class='ctx'> 			if (abm-&gt;funcs &amp;&amp; abm-&gt;funcs-&gt;set_pipe_ex) {</div><div class='del'>-				abm-&gt;funcs-&gt;set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl-&gt;inst);</div><div class='add'>+				abm-&gt;funcs-&gt;set_pipe_ex(abm,</div><div class='add'>+						otg_inst,</div><div class='add'>+						SET_ABM_PIPE_NORMAL,</div><div class='add'>+						panel_cntl-&gt;inst,</div><div class='add'>+						panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 			} else {</div><div class='del'>-				dmub_abm_set_pipe(abm, otg_inst, SET_ABM_PIPE_NORMAL, panel_cntl-&gt;inst);</div><div class='add'>+					dmub_abm_set_pipe(abm,</div><div class='add'>+							otg_inst,</div><div class='add'>+							SET_ABM_PIPE_NORMAL,</div><div class='add'>+							panel_cntl-&gt;inst,</div><div class='add'>+							panel_cntl-&gt;pwrseq_inst);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c<br/>index 18249c6b6d81..18249c6b6d81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h<br/>index 3ed24292648a..3ed24292648a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c<br/>index d71faf2ecd41..c34c13e1e0a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c</a></div><div class='hunk'>@@ -51,7 +51,7 @@</div><div class='ctx'> #include "dcn20/dcn20_hwseq.h"</div><div class='ctx'> #include "dcn30/dcn30_resource.h"</div><div class='ctx'> #include "link.h"</div><div class='del'>-</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -367,6 +367,10 @@ void dcn30_enable_writeback(</div><div class='ctx'> 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\</div><div class='ctx'> 		__func__, wb_info-&gt;dwb_pipe_inst,\</div><div class='ctx'> 		wb_info-&gt;mpcc_inst);</div><div class='add'>+</div><div class='add'>+	/* Warmup interface */</div><div class='add'>+	dcn30_mmhubbub_warmup(dc, 1, wb_info);</div><div class='add'>+</div><div class='ctx'> 	/* Update writeback pipe */</div><div class='ctx'> 	dcn30_set_writeback(dc, wb_info, context);</div><div class='ctx'> </div><div class='hunk'>@@ -472,6 +476,7 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int edp_num;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='hunk'>@@ -608,13 +613,15 @@ void dcn30_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 		struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;panel_cntl)</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='ctx'> 			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (abms[i] != NULL)</div><div class='del'>-			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight);</div><div class='add'>+			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight, user_level);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/</div><div class='hunk'>@@ -750,7 +757,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;</div><div class='ctx'> 				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);</div><div class='ctx'> </div><div class='del'>-				dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 				return true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -872,7 +879,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 					cmd.mall.cursor_height = cursor_attr.height;</div><div class='ctx'> 					cmd.mall.cursor_pitch = cursor_attr.pitch;</div><div class='ctx'> </div><div class='del'>-					dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+					dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 					/* Use copied cursor, and it's okay to not switch back */</div><div class='ctx'> 					cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;</div><div class='hunk'>@@ -888,7 +895,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 				cmd.mall.tmr_scale = tmr_scale;</div><div class='ctx'> 				cmd.mall.debug_bits = dc-&gt;debug.mall_error_as_fatal;</div><div class='ctx'> </div><div class='del'>-				dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 				return true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -905,7 +912,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 	cmd.mall.header.payload_bytes =</div><div class='ctx'> 		sizeof(cmd.mall) - sizeof(cmd.mall.header);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -962,7 +969,7 @@ void dcn30_hardware_release(struct dc *dc)</div><div class='ctx'> 		if (!pipe-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) == SUBVP_MAIN) {</div><div class='ctx'> 			subvp_in_use = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c<br/>index 9894caedffed..9894caedffed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h<br/>index c280ff90bfa3..c280ff90bfa3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c<br/>index 6477009ce065..6477009ce065 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h<br/>index 0bca48ccbfa2..0bca48ccbfa2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c<br/>index 637f9514d37b..637f9514d37b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h<br/>index 899587b93aa1..899587b93aa1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c<br/>index edb4d68b8187..edb4d68b8187 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h<br/>index 4949981126d7..4949981126d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c<br/>index 97798cee876e..7423880fabb6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c</a></div><div class='hunk'>@@ -96,7 +96,8 @@ static void enable_memory_low_power(struct dc *dc)</div><div class='ctx'> 	if (dc-&gt;debug.enable_mem_low_power.bits.vpg &amp;&amp; dc-&gt;res_pool-&gt;stream_enc[0]-&gt;vpg-&gt;funcs-&gt;vpg_powerdown) {</div><div class='ctx'> 		// Power down VPGs</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;stream_enc_count; i++)</div><div class='del'>-			dc-&gt;res_pool-&gt;stream_enc[i]-&gt;vpg-&gt;funcs-&gt;vpg_powerdown(dc-&gt;res_pool-&gt;stream_enc[i]-&gt;vpg);</div><div class='add'>+			if (dc-&gt;res_pool-&gt;stream_enc[i]-&gt;vpg)</div><div class='add'>+				dc-&gt;res_pool-&gt;stream_enc[i]-&gt;vpg-&gt;funcs-&gt;vpg_powerdown(dc-&gt;res_pool-&gt;stream_enc[i]-&gt;vpg);</div><div class='ctx'> #if defined(CONFIG_DRM_AMD_DC_FP)</div><div class='ctx'> 		for (i = 0; i &lt; dc-&gt;res_pool-&gt;hpo_dp_stream_enc_count; i++)</div><div class='ctx'> 			dc-&gt;res_pool-&gt;hpo_dp_stream_enc[i]-&gt;vpg-&gt;funcs-&gt;vpg_powerdown(dc-&gt;res_pool-&gt;hpo_dp_stream_enc[i]-&gt;vpg);</div><div class='hunk'>@@ -112,6 +113,7 @@ void dcn31_init_hw(struct dc *dc)</div><div class='ctx'> 	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	struct resource_pool *res_pool = dc-&gt;res_pool;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='hunk'>@@ -223,13 +225,15 @@ void dcn31_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 		struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;panel_cntl)</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='ctx'> 			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (abms[i] != NULL)</div><div class='del'>-			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight);</div><div class='add'>+			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight, user_level);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/</div><div class='hunk'>@@ -415,7 +419,7 @@ void dcn31_z10_save_init(struct dc *dc)</div><div class='ctx'> 	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;</div><div class='ctx'> 	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn31_z10_restore(const struct dc *dc)</div><div class='hunk'>@@ -433,7 +437,7 @@ void dcn31_z10_restore(const struct dc *dc)</div><div class='ctx'> 	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;</div><div class='ctx'> 	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)</div><div class='hunk'>@@ -523,7 +527,8 @@ static void dcn31_reset_back_end_for_pipe(</div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_odm_bypass(</div><div class='ctx'> 				pipe_ctx-&gt;stream_res.tg, &amp;pipe_ctx-&gt;stream-&gt;timing);</div><div class='del'>-	pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='add'>+	if (dc_is_hdmi_tmds_signal(pipe_ctx-&gt;stream-&gt;signal))</div><div class='add'>+		pipe_ctx-&gt;stream-&gt;link-&gt;phy_state.symclk_ref_cnts.otg = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c<br/>index 669f524bd064..669f524bd064 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h<br/>index a3db08c8bd35..a3db08c8bd35 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c<br/>index ccb7e317e86a..ccb7e317e86a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h<br/>index 8f92e66577cf..8f92e66577cf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c<br/>index 6a65af8c36b9..6c9299c7683d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c</a></div><div class='hunk'>@@ -51,6 +51,7 @@</div><div class='ctx'> #include "dcn32/dcn32_resource.h"</div><div class='ctx'> #include "link.h"</div><div class='ctx'> #include "../dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -277,7 +278,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 				cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;</div><div class='ctx'> 				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='ctx'> </div><div class='del'>-				dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 				return true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -311,7 +312,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 				cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='ctx'> 				cmd.cab.cab_alloc_ways = (uint8_t)ways;</div><div class='ctx'> </div><div class='del'>-				dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='add'>+				dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);</div><div class='ctx'> </div><div class='ctx'> 				return true;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -327,7 +328,7 @@ bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 	cmd.cab.header.payload_bytes =</div><div class='ctx'> 			sizeof(cmd.cab) - sizeof(cmd.cab.header);</div><div class='ctx'> </div><div class='del'>-	dm_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='add'>+	dc_wake_and_execute_dmub_cmd(dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -348,8 +349,7 @@ void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;stream-&gt;mall_stream_config.paired_stream &amp;&amp;</div><div class='del'>-				pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+		if (pipe_ctx-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {</div><div class='ctx'> 			// There is at least 1 SubVP pipe, so enable SubVP</div><div class='ctx'> 			enable_subvp = true;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -375,18 +375,20 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc,</div><div class='ctx'> 	bool subvp_immediate_flip = false;</div><div class='ctx'> 	bool subvp_in_use = false;</div><div class='ctx'> 	struct pipe_ctx *pipe;</div><div class='add'>+	enum mall_stream_type pipe_mall_type = SUBVP_NONE;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='add'>+		pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; pipe_mall_type == SUBVP_MAIN) {</div><div class='ctx'> 			subvp_in_use = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (top_pipe_to_program &amp;&amp; top_pipe_to_program-&gt;stream &amp;&amp; top_pipe_to_program-&gt;plane_state) {</div><div class='del'>-		if (top_pipe_to_program-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN &amp;&amp;</div><div class='add'>+		if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &amp;&amp;</div><div class='ctx'> 				top_pipe_to_program-&gt;plane_state-&gt;flip_immediate)</div><div class='ctx'> 			subvp_immediate_flip = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -398,7 +400,7 @@ void dcn32_subvp_pipe_control_lock(struct dc *dc,</div><div class='ctx'> 		if (!lock) {</div><div class='ctx'> 			for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 				pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-				if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN &amp;&amp;</div><div class='add'>+				if (pipe-&gt;stream &amp;&amp; pipe-&gt;plane_state &amp;&amp; pipe_mall_type == SUBVP_MAIN &amp;&amp;</div><div class='ctx'> 						should_lock_all_pipes)</div><div class='ctx'> 					pipe-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(pipe-&gt;stream_res.tg, CRTC_STATE_VBLANK);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -416,14 +418,7 @@ void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = params-&gt;subvp_pipe_control_lock_fast_params.dc;</div><div class='ctx'> 	bool lock = params-&gt;subvp_pipe_control_lock_fast_params.lock;</div><div class='del'>-	struct pipe_ctx *pipe_ctx = params-&gt;subvp_pipe_control_lock_fast_params.pipe_ctx;</div><div class='del'>-	bool subvp_immediate_flip = false;</div><div class='del'>-</div><div class='del'>-	if (pipe_ctx &amp;&amp; pipe_ctx-&gt;stream &amp;&amp; pipe_ctx-&gt;plane_state) {</div><div class='del'>-		if (pipe_ctx-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN &amp;&amp;</div><div class='del'>-				pipe_ctx-&gt;plane_state-&gt;flip_immediate)</div><div class='del'>-			subvp_immediate_flip = true;</div><div class='del'>-	}</div><div class='add'>+	bool subvp_immediate_flip = params-&gt;subvp_pipe_control_lock_fast_params.subvp_immediate_flip;</div><div class='ctx'> </div><div class='ctx'> 	// Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.</div><div class='ctx'> 	if (subvp_immediate_flip) {</div><div class='hunk'>@@ -487,8 +482,7 @@ bool dcn32_set_mcm_luts(</div><div class='ctx'> 		if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_HWPWL)</div><div class='ctx'> 			lut_params = &amp;plane_state-&gt;blend_tf-&gt;pwl;</div><div class='ctx'> 		else if (plane_state-&gt;blend_tf-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='del'>-			cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='del'>-					plane_state-&gt;blend_tf,</div><div class='add'>+			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;blend_tf,</div><div class='ctx'> 					&amp;dpp_base-&gt;regamma_params, false);</div><div class='ctx'> 			lut_params = &amp;dpp_base-&gt;regamma_params;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -503,8 +497,7 @@ bool dcn32_set_mcm_luts(</div><div class='ctx'> 		else if (plane_state-&gt;in_shaper_func-&gt;type == TF_TYPE_DISTRIBUTED_POINTS) {</div><div class='ctx'> 			// TODO: dpp_base replace</div><div class='ctx'> 			ASSERT(false);</div><div class='del'>-			cm_helper_translate_curve_to_hw_format(plane_state-&gt;ctx,</div><div class='del'>-					plane_state-&gt;in_shaper_func,</div><div class='add'>+			cm3_helper_translate_curve_to_hw_format(plane_state-&gt;in_shaper_func,</div><div class='ctx'> 					&amp;dpp_base-&gt;shaper_params, true);</div><div class='ctx'> 			lut_params = &amp;dpp_base-&gt;shaper_params;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -611,7 +604,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='ctx'> </div><div class='del'>-		if (!pipe-&gt;stream || !(pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN ||</div><div class='add'>+		if (!pipe-&gt;stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||</div><div class='ctx'> 		    pipe-&gt;stream-&gt;fpo_in_use)) {</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow)</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow(hubp, false);</div><div class='hunk'>@@ -626,7 +619,7 @@ void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> 		struct hubp *hubp = pipe-&gt;plane_res.hubp;</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN ||</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||</div><div class='ctx'> 				pipe-&gt;stream-&gt;fpo_in_use)) {</div><div class='ctx'> 			if (hubp &amp;&amp; hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow)</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_update_force_pstate_disallow(hubp, true);</div><div class='hunk'>@@ -673,8 +666,8 @@ void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			if (cursor_size &gt; 16384)</div><div class='ctx'> 				cache_cursor = true;</div><div class='ctx'> </div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='del'>-					hubp-&gt;funcs-&gt;hubp_update_mall_sel(hubp, 1, false);</div><div class='add'>+			if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='add'>+				hubp-&gt;funcs-&gt;hubp_update_mall_sel(hubp, 1, false);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				// MALL not supported with Stereo3D</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_update_mall_sel(hubp,</div><div class='hunk'>@@ -716,9 +709,8 @@ void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 			 *        see if CURSOR_REQ_MODE will be back to 1 for SubVP</div><div class='ctx'> 			 *        when it should be 0 for MPO</div><div class='ctx'> 			 */</div><div class='del'>-			if (pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN) {</div><div class='add'>+			if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)</div><div class='ctx'> 				hubp-&gt;funcs-&gt;hubp_prepare_subvp_buffering(hubp, true);</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -761,6 +753,7 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int edp_num;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='ctx'> 		dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks(dc-&gt;clk_mgr);</div><div class='hunk'>@@ -915,13 +908,15 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 		struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;panel_cntl)</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='ctx'> 			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (abms[i] != NULL &amp;&amp; abms[i]-&gt;funcs != NULL)</div><div class='del'>-			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight);</div><div class='add'>+			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight, user_level);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/</div><div class='hunk'>@@ -962,6 +957,12 @@ void dcn32_init_hw(struct dc *dc)</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.subvp_psr = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.subvp_psr_support;</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.gecc_enable = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.gecc_enable;</div><div class='ctx'> 		dc-&gt;caps.dmub_caps.mclk_sw = dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;feature_caps.fw_assisted_mclk_switch;</div><div class='add'>+</div><div class='add'>+		if (dc-&gt;ctx-&gt;dmub_srv-&gt;dmub-&gt;fw_version &lt;</div><div class='add'>+		    DMUB_FW_VERSION(7, 0, 35)) {</div><div class='add'>+			dc-&gt;debug.force_disable_subvp = true;</div><div class='add'>+			dc-&gt;debug.disable_fpo_optimizations = true;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -991,9 +992,22 @@ static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,</div><div class='ctx'> static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 1;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	/* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN</div><div class='add'>+	 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a</div><div class='add'>+	 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is</div><div class='add'>+	 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings</div><div class='add'>+	 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger</div><div class='add'>+	 * this problem. We are implementing a workaround here to keep using dscclk</div><div class='add'>+	 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e</div><div class='add'>+	 * 48Mhz) pixel clock to avoid hitting this problem.</div><div class='add'>+	 */</div><div class='add'>+	bool should_use_dto_dscclk = (dccg-&gt;funcs-&gt;set_dto_dscclk != NULL) &amp;&amp;</div><div class='add'>+			stream-&gt;timing.pix_clk_100hz &gt; 480000;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT(dsc);</div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='hunk'>@@ -1016,12 +1030,16 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+		if (should_use_dto_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			struct display_stream_compressor *odm_dsc = odm_pipe-&gt;stream_res.dsc;</div><div class='ctx'> </div><div class='ctx'> 			ASSERT(odm_dsc);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_set_config(odm_dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_enable(odm_dsc, odm_pipe-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+			if (should_use_dto_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst);</div><div class='ctx'> 		}</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_width *= opp_cnt;</div><div class='hunk'>@@ -1041,9 +1059,13 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 				OPTC_DSC_DISABLED, 0, 0);</div><div class='ctx'> </div><div class='ctx'> 		/* disable DSC block */</div><div class='add'>+		if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, pipe_ctx-&gt;stream_res.dsc-&gt;inst);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_disable(pipe_ctx-&gt;stream_res.dsc);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			ASSERT(odm_pipe-&gt;stream_res.dsc);</div><div class='add'>+			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, odm_pipe-&gt;stream_res.dsc-&gt;inst);</div><div class='ctx'> 			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(odm_pipe-&gt;stream_res.dsc);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1126,6 +1148,10 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *</div><div class='ctx'> 		if (!pipe_ctx-&gt;next_odm_pipe &amp;&amp; current_pipe_ctx-&gt;next_odm_pipe &amp;&amp;</div><div class='ctx'> 				current_pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.dsc) {</div><div class='ctx'> 			struct display_stream_compressor *dsc = current_pipe_ctx-&gt;next_odm_pipe-&gt;stream_res.dsc;</div><div class='add'>+			struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+</div><div class='add'>+			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 			/* disconnect DSC block from stream */</div><div class='ctx'> 			dsc-&gt;funcs-&gt;dsc_disconnect(dsc);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1199,7 +1225,7 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if ((pipe-&gt;stream-&gt;dpms_off || dc_is_virtual_signal(pipe-&gt;stream-&gt;signal))</div><div class='del'>-			&amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+			&amp;&amp; dc_state_get_pipe_subvp_type(dc-&gt;current_state, pipe) != SUBVP_PHANTOM) {</div><div class='ctx'> 			pipe-&gt;stream_res.tg-&gt;funcs-&gt;disable_crtc(pipe-&gt;stream_res.tg);</div><div class='ctx'> 			reset_sync_context_for_pipe(dc, context, i);</div><div class='ctx'> 			otg_disabled[i] = true;</div><div class='hunk'>@@ -1350,8 +1376,8 @@ void dcn32_update_phantom_vp_position(struct dc *dc,</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_MAIN &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.paired_stream == phantom_pipe-&gt;stream) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &amp;&amp;</div><div class='add'>+				dc_state_get_paired_subvp_stream(context, pipe-&gt;stream) == phantom_pipe-&gt;stream) {</div><div class='ctx'> 			if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;plane_state-&gt;update_flags.bits.position_change) {</div><div class='ctx'> </div><div class='ctx'> 				phantom_plane-&gt;src_rect.x = pipe-&gt;plane_state-&gt;src_rect.x;</div><div class='hunk'>@@ -1376,21 +1402,19 @@ void dcn32_update_phantom_vp_position(struct dc *dc,</div><div class='ctx'> void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)</div><div class='ctx'> {</div><div class='ctx'> 	phantom_pipe-&gt;update_flags.raw = 0;</div><div class='del'>-	if (phantom_pipe-&gt;stream &amp;&amp; phantom_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='del'>-		if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.enable = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.mpcc = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.dppclk = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.hubp_interdependent = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.hubp_rq_dlg_ttu = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.gamut_remap = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.scaler = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.viewport = 1;</div><div class='del'>-			phantom_pipe-&gt;update_flags.bits.det_size = 1;</div><div class='del'>-			if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {</div><div class='del'>-				phantom_pipe-&gt;update_flags.bits.odm = 1;</div><div class='del'>-				phantom_pipe-&gt;update_flags.bits.global_sync = 1;</div><div class='del'>-			}</div><div class='add'>+	if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.enable = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.mpcc = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.dppclk = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.hubp_interdependent = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.hubp_rq_dlg_ttu = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.gamut_remap = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.scaler = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.viewport = 1;</div><div class='add'>+		phantom_pipe-&gt;update_flags.bits.det_size = 1;</div><div class='add'>+		if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {</div><div class='add'>+			phantom_pipe-&gt;update_flags.bits.odm = 1;</div><div class='add'>+			phantom_pipe-&gt;update_flags.bits.global_sync = 1;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1462,8 +1486,8 @@ void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		 * pipe, wait for the double buffer update to complete first before we do</div><div class='ctx'> 		 * ANY phantom pipe programming.</div><div class='ctx'> 		 */</div><div class='del'>-		if (pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM &amp;&amp;</div><div class='del'>-				old_pipe-&gt;stream &amp;&amp; old_pipe-&gt;stream-&gt;mall_stream_config.type != SUBVP_PHANTOM) {</div><div class='add'>+		if (pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &amp;&amp;</div><div class='add'>+				old_pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(dc-&gt;current_state, old_pipe) != SUBVP_PHANTOM) {</div><div class='ctx'> 			old_pipe-&gt;stream_res.tg-&gt;funcs-&gt;wait_for_state(</div><div class='ctx'> 					old_pipe-&gt;stream_res.tg,</div><div class='ctx'> 					CRTC_STATE_VBLANK);</div><div class='hunk'>@@ -1475,7 +1499,7 @@ void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		struct pipe_ctx *new_pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='ctx'> </div><div class='del'>-		if (new_pipe-&gt;stream &amp;&amp; new_pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+		if (new_pipe-&gt;stream &amp;&amp; dc_state_get_pipe_subvp_type(context, new_pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			// If old context or new context has phantom pipes, apply</div><div class='ctx'> 			// the phantom timings now. We can't change the phantom</div><div class='ctx'> 			// pipe configuration safely without driver acquiring</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c<br/>index 427cfc8c24a4..427cfc8c24a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h<br/>index 89a591eb2c23..89a591eb2c23 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c<br/>index 5a8258287438..9c806385ecbd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c</a></div><div class='hunk'>@@ -56,6 +56,7 @@</div><div class='ctx'> #include "dcn30/dcn30_cm_common.h"</div><div class='ctx'> #include "dcn31/dcn31_hwseq.h"</div><div class='ctx'> #include "dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dc_state_priv.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger) \</div><div class='ctx'> 	struct dal_logger *dc_logger = logger</div><div class='hunk'>@@ -133,6 +134,7 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	struct dc_bios *dcb = dc-&gt;ctx-&gt;dc_bios;</div><div class='ctx'> 	struct resource_pool *res_pool = dc-&gt;res_pool;</div><div class='ctx'> 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;</div><div class='add'>+	uint32_t user_level = MAX_BACKLIGHT_LEVEL;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;clk_mgr &amp;&amp; dc-&gt;clk_mgr-&gt;funcs-&gt;init_clocks)</div><div class='hunk'>@@ -145,17 +147,36 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 		hws-&gt;funcs.bios_golden_init(dc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);</div><div class='del'>-	REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);</div><div class='del'>-</div><div class='del'>-	/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */</div><div class='del'>-	REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-			PHYBSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-			PHYCSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-			PHYDSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='del'>-			PHYESYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+	if (!dc-&gt;debug.disable_clock_gate) {</div><div class='add'>+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);</div><div class='add'>+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);</div><div class='add'>+</div><div class='add'>+		/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */</div><div class='add'>+		REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='add'>+				PHYBSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='add'>+				PHYCSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='add'>+				PHYDSYMCLK_ROOT_GATE_DISABLE, 1,</div><div class='add'>+				PHYESYMCLK_ROOT_GATE_DISABLE, 1);</div><div class='add'>+</div><div class='add'>+		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL4,</div><div class='add'>+				DPIASYMCLK0_GATE_DISABLE, 0,</div><div class='add'>+				DPIASYMCLK1_GATE_DISABLE, 0,</div><div class='add'>+				DPIASYMCLK2_GATE_DISABLE, 0,</div><div class='add'>+				DPIASYMCLK3_GATE_DISABLE, 0);</div><div class='add'>+</div><div class='add'>+		REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0xFFFFFFFF);</div><div class='add'>+		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				DTBCLK_P0_GATE_DISABLE, 0,</div><div class='add'>+				DTBCLK_P1_GATE_DISABLE, 0,</div><div class='add'>+				DTBCLK_P2_GATE_DISABLE, 0,</div><div class='add'>+				DTBCLK_P3_GATE_DISABLE, 0);</div><div class='add'>+		REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,</div><div class='add'>+				DPSTREAMCLK0_GATE_DISABLE, 0,</div><div class='add'>+				DPSTREAMCLK1_GATE_DISABLE, 0,</div><div class='add'>+				DPSTREAMCLK2_GATE_DISABLE, 0,</div><div class='add'>+				DPSTREAMCLK3_GATE_DISABLE, 0);</div><div class='ctx'> </div><div class='del'>-	REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	// Initialize the dccg</div><div class='ctx'> 	if (res_pool-&gt;dccg-&gt;funcs-&gt;dccg_init)</div><div class='hunk'>@@ -260,13 +281,15 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;link_count; i++) {</div><div class='ctx'> 		struct dc_link *link = dc-&gt;links[i];</div><div class='ctx'> </div><div class='del'>-		if (link-&gt;panel_cntl)</div><div class='add'>+		if (link-&gt;panel_cntl) {</div><div class='ctx'> 			backlight = link-&gt;panel_cntl-&gt;funcs-&gt;hw_init(link-&gt;panel_cntl);</div><div class='add'>+			user_level = link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (dc-&gt;ctx-&gt;dmub_srv) {</div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (abms[i] != NULL &amp;&amp; abms[i]-&gt;funcs != NULL)</div><div class='del'>-			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight);</div><div class='add'>+			abms[i]-&gt;funcs-&gt;abm_init(abms[i], backlight, user_level);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -332,9 +355,6 @@ void dcn35_init_hw(struct dc *dc)</div><div class='ctx'> 	if (dc-&gt;res_pool-&gt;pg_cntl) {</div><div class='ctx'> 		if (dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;init_pg_status)</div><div class='ctx'> 			dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;init_pg_status(dc-&gt;res_pool-&gt;pg_cntl);</div><div class='del'>-</div><div class='del'>-		if (dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;set_force_poweron_domain22)</div><div class='del'>-			dc-&gt;res_pool-&gt;pg_cntl-&gt;funcs-&gt;set_force_poweron_domain22(dc-&gt;res_pool-&gt;pg_cntl, false);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -671,11 +691,7 @@ bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	// TODO: review other cases when idle optimization is allowed</div><div class='del'>-</div><div class='del'>-	if (!enable)</div><div class='del'>-		dc_dmub_srv_exit_low_power_state(dc);</div><div class='del'>-	else</div><div class='del'>-		dc_dmub_srv_notify_idle(dc, enable);</div><div class='add'>+	dc_dmub_srv_apply_idle_power_optimizations(dc, enable);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -685,7 +701,7 @@ void dcn35_z10_restore(const struct dc *dc)</div><div class='ctx'> 	if (dc-&gt;debug.disable_z10)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dc_dmub_srv_exit_low_power_state(dc);</div><div class='add'>+	dc_dmub_srv_apply_idle_power_optimizations(dc, false);</div><div class='ctx'> </div><div class='ctx'> 	dcn31_z10_restore(dc);</div><div class='ctx'> }</div><div class='hunk'>@@ -801,12 +817,12 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 		dc-&gt;res_pool-&gt;opps[i]-&gt;mpcc_disconnect_pending[pipe_ctx-&gt;plane_res.mpcc_inst] = true;</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.opp = dc-&gt;res_pool-&gt;opps[i];</div><div class='ctx'> </div><div class='del'>-		hws-&gt;funcs.plane_atomic_disconnect(dc, pipe_ctx);</div><div class='add'>+		hws-&gt;funcs.plane_atomic_disconnect(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		if (tg-&gt;funcs-&gt;is_tg_enabled(tg))</div><div class='ctx'> 			tg-&gt;funcs-&gt;unlock(tg);</div><div class='ctx'> </div><div class='del'>-		dc-&gt;hwss.disable_plane(dc, pipe_ctx);</div><div class='add'>+		dc-&gt;hwss.disable_plane(dc, context, pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 		pipe_ctx-&gt;stream_res.tg = NULL;</div><div class='ctx'> 		pipe_ctx-&gt;plane_res.hubp = NULL;</div><div class='hunk'>@@ -933,10 +949,10 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	pipe_ctx-&gt;plane_state = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dce_hwseq *hws = dc-&gt;hwseq;</div><div class='del'>-	bool is_phantom = pipe_ctx-&gt;plane_state &amp;&amp; pipe_ctx-&gt;plane_state-&gt;is_phantom;</div><div class='add'>+	bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM;</div><div class='ctx'> 	struct timing_generator *tg = is_phantom ? pipe_ctx-&gt;stream_res.tg : NULL;</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='hunk'>@@ -963,6 +979,8 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	bool hpo_frl_stream_enc_acquired = false;</div><div class='ctx'> 	bool hpo_dp_stream_enc_acquired = false;</div><div class='ctx'> 	int i = 0, j = 0;</div><div class='add'>+	int edp_num = 0;</div><div class='add'>+	struct dc_link *edp_links[MAX_NUM_EDP] = { NULL };</div><div class='ctx'> </div><div class='ctx'> 	memset(update_state, 0, sizeof(struct pg_block_update));</div><div class='ctx'> </div><div class='hunk'>@@ -1003,10 +1021,24 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> </div><div class='ctx'> 		if (pipe_ctx-&gt;stream_res.opp)</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_OPP][pipe_ctx-&gt;stream_res.opp-&gt;inst] = false;</div><div class='add'>+	}</div><div class='add'>+	/*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;timing_generator_count; i++) {</div><div class='add'>+		struct timing_generator *tg = dc-&gt;res_pool-&gt;timing_generators[i];</div><div class='add'>+		if (tg &amp;&amp; tg-&gt;funcs-&gt;is_tg_enabled(tg)) {</div><div class='add'>+			update_state-&gt;pg_pipe_res_update[PG_OPTC][i] = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-		if (pipe_ctx-&gt;stream_res.tg)</div><div class='del'>-			update_state-&gt;pg_pipe_res_update[PG_OPTC][pipe_ctx-&gt;stream_res.tg-&gt;inst] = false;</div><div class='add'>+	dc_get_edp_links(dc, edp_links, &amp;edp_num);</div><div class='add'>+	if (edp_num == 0 ||</div><div class='add'>+		((!edp_links[0] || !edp_links[0]-&gt;edp_sink_present) &amp;&amp;</div><div class='add'>+			(!edp_links[1] || !edp_links[1]-&gt;edp_sink_present))) {</div><div class='add'>+		/*eDP not exist on this config, keep Domain24 power on, for S0i3, this will be handled in dmubfw*/</div><div class='add'>+		update_state-&gt;pg_pipe_res_update[PG_OPTC][0] = false;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='hunk'>@@ -1092,8 +1124,29 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_block_power_control(struct dc *dc,</div><div class='del'>-	struct pg_block_update *update_state, bool power_on)</div><div class='add'>+/**</div><div class='add'>+ * dcn35_hw_block_power_down() - power down sequence</div><div class='add'>+ *</div><div class='add'>+ * The following sequence describes the ON-OFF (ONO) for power down:</div><div class='add'>+ *</div><div class='add'>+ *	ONO Region 3, DCPG 25: hpo - SKIPPED</div><div class='add'>+ *	ONO Region 4, DCPG 0: dchubp0, dpp0</div><div class='add'>+ *	ONO Region 6, DCPG 1: dchubp1, dpp1</div><div class='add'>+ *	ONO Region 8, DCPG 2: dchubp2, dpp2</div><div class='add'>+ *	ONO Region 10, DCPG 3: dchubp3, dpp3</div><div class='add'>+ *	ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will pwr dwn at IPS2 entry</div><div class='add'>+ *	ONO Region 5, DCPG 16: dsc0</div><div class='add'>+ *	ONO Region 7, DCPG 17: dsc1</div><div class='add'>+ *	ONO Region 9, DCPG 18: dsc2</div><div class='add'>+ *	ONO Region 11, DCPG 19: dsc3</div><div class='add'>+ *	ONO Region 2, DCPG 24: mpc opp optc dwb</div><div class='add'>+ *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @update_state: update PG sequence states for HW block</div><div class='add'>+ */</div><div class='add'>+void dcn35_hw_block_power_down(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='ctx'> {</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='hunk'>@@ -1102,64 +1155,106 @@ void dcn35_block_power_control(struct dc *dc,</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (dc-&gt;debug.ignore_pg)</div><div class='ctx'> 		return;</div><div class='add'>+</div><div class='ctx'> 	if (update_state-&gt;pg_res_update[PG_HPO]) {</div><div class='ctx'> 		if (pg_cntl-&gt;funcs-&gt;hpo_pg_control)</div><div class='del'>-			pg_cntl-&gt;funcs-&gt;hpo_pg_control(pg_cntl, power_on);</div><div class='add'>+			pg_cntl-&gt;funcs-&gt;hpo_pg_control(pg_cntl, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='ctx'> 			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, power_on);</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, false);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++)</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='ctx'> 			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, power_on);</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, false);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_MPCC][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;mpcc_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;mpcc_pg_control(pg_cntl, i, power_on);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_OPP][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;opp_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;opp_pg_control(pg_cntl, i, power_on);</div><div class='del'>-		}</div><div class='ctx'> </div><div class='del'>-		if (update_state-&gt;pg_pipe_res_update[PG_OPTC][i]) {</div><div class='del'>-			if (pg_cntl-&gt;funcs-&gt;optc_pg_control)</div><div class='del'>-				pg_cntl-&gt;funcs-&gt;optc_pg_control(pg_cntl, i, power_on);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	/*this will need all the clients to unregister optc interruts let dmubfw handle this*/</div><div class='add'>+	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='add'>+		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, false);</div><div class='ctx'> </div><div class='del'>-	if (update_state-&gt;pg_res_update[PG_DWB]) {</div><div class='del'>-		if (pg_cntl-&gt;funcs-&gt;dwb_pg_control)</div><div class='del'>-			pg_cntl-&gt;funcs-&gt;dwb_pg_control(pg_cntl, power_on);</div><div class='del'>-	}</div><div class='add'>+	//domain22, 23, 25 currently always on.</div><div class='ctx'> </div><div class='del'>-	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='del'>-		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, power_on);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn35_root_clock_control(struct dc *dc,</div><div class='del'>-	struct pg_block_update *update_state, bool power_on)</div><div class='add'>+/**</div><div class='add'>+ * dcn35_hw_block_power_up() - power up sequence</div><div class='add'>+ *</div><div class='add'>+ * The following sequence describes the ON-OFF (ONO) for power up:</div><div class='add'>+ *</div><div class='add'>+ *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED</div><div class='add'>+ *	ONO Region 2, DCPG 24: mpc opp optc dwb</div><div class='add'>+ *	ONO Region 5, DCPG 16: dsc0</div><div class='add'>+ *	ONO Region 7, DCPG 17: dsc1</div><div class='add'>+ *	ONO Region 9, DCPG 18: dsc2</div><div class='add'>+ *	ONO Region 11, DCPG 19: dsc3</div><div class='add'>+ *	ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will power up at IPS2 exit</div><div class='add'>+ *	ONO Region 4, DCPG 0: dchubp0, dpp0</div><div class='add'>+ *	ONO Region 6, DCPG 1: dchubp1, dpp1</div><div class='add'>+ *	ONO Region 8, DCPG 2: dchubp2, dpp2</div><div class='add'>+ *	ONO Region 10, DCPG 3: dchubp3, dpp3</div><div class='add'>+ *	ONO Region 3, DCPG 25: hpo - SKIPPED</div><div class='add'>+ *</div><div class='add'>+ * @dc: Current DC state</div><div class='add'>+ * @update_state: update PG sequence states for HW block</div><div class='add'>+ */</div><div class='add'>+void dcn35_hw_block_power_up(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state)</div><div class='ctx'> {</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='ctx'> </div><div class='ctx'> 	if (!pg_cntl)</div><div class='ctx'> 		return;</div><div class='add'>+	if (dc-&gt;debug.ignore_pg)</div><div class='add'>+		return;</div><div class='add'>+	//domain22, 23, 25 currently always on.</div><div class='add'>+	/*this will need all the clients to unregister optc interruts let dmubfw handle this*/</div><div class='add'>+	if (pg_cntl-&gt;funcs-&gt;plane_otg_pg_control)</div><div class='add'>+		pg_cntl-&gt;funcs-&gt;plane_otg_pg_control(pg_cntl, true);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++)</div><div class='add'>+		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;dsc_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;dsc_pg_control(pg_cntl, i, true);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='ctx'> 			update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='del'>-			if (dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control)</div><div class='del'>-				dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='add'>+			if (pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control)</div><div class='add'>+				pg_cntl-&gt;funcs-&gt;hubp_dpp_pg_control(pg_cntl, i, true);</div><div class='ctx'> 		}</div><div class='add'>+	}</div><div class='add'>+	if (update_state-&gt;pg_res_update[PG_HPO]) {</div><div class='add'>+		if (pg_cntl-&gt;funcs-&gt;hpo_pg_control)</div><div class='add'>+			pg_cntl-&gt;funcs-&gt;hpo_pg_control(pg_cntl, true);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+void dcn35_root_clock_control(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state, bool power_on)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct pg_cntl *pg_cntl = dc-&gt;res_pool-&gt;pg_cntl;</div><div class='ctx'> </div><div class='add'>+	if (!pg_cntl)</div><div class='add'>+		return;</div><div class='add'>+	/*enable root clock first when power up*/</div><div class='add'>+	if (power_on)</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	for (i = 0; i &lt; dc-&gt;res_pool-&gt;res_cap-&gt;num_dsc; i++) {</div><div class='ctx'> 		if (update_state-&gt;pg_pipe_res_update[PG_DSC][i]) {</div><div class='ctx'> 			if (power_on) {</div><div class='ctx'> 				if (dc-&gt;res_pool-&gt;dccg-&gt;funcs-&gt;enable_dsc)</div><div class='hunk'>@@ -1170,6 +1265,15 @@ void dcn35_root_clock_control(struct dc *dc,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	/*disable root clock first when power down*/</div><div class='add'>+	if (!power_on)</div><div class='add'>+		for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='add'>+			if (update_state-&gt;pg_pipe_res_update[PG_HUBP][i] &amp;&amp;</div><div class='add'>+				update_state-&gt;pg_pipe_res_update[PG_DPP][i]) {</div><div class='add'>+				if (dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control)</div><div class='add'>+					dc-&gt;hwseq-&gt;funcs.dpp_root_clock_control(dc-&gt;hwseq, i, power_on);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void dcn35_prepare_bandwidth(</div><div class='hunk'>@@ -1183,9 +1287,9 @@ void dcn35_prepare_bandwidth(</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;hwss.root_clock_control)</div><div class='ctx'> 			dc-&gt;hwss.root_clock_control(dc, &amp;pg_update_state, true);</div><div class='del'>-</div><div class='del'>-		if (dc-&gt;hwss.block_power_control)</div><div class='del'>-			dc-&gt;hwss.block_power_control(dc, &amp;pg_update_state, true);</div><div class='add'>+		/*power up required HW block*/</div><div class='add'>+		if (dc-&gt;hwss.hw_block_power_up)</div><div class='add'>+			dc-&gt;hwss.hw_block_power_up(dc, &amp;pg_update_state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dcn20_prepare_bandwidth(dc, context);</div><div class='hunk'>@@ -1201,9 +1305,9 @@ void dcn35_optimize_bandwidth(</div><div class='ctx'> </div><div class='ctx'> 	if (dc-&gt;hwss.calc_blocks_to_gate) {</div><div class='ctx'> 		dc-&gt;hwss.calc_blocks_to_gate(dc, context, &amp;pg_update_state);</div><div class='del'>-</div><div class='del'>-		if (dc-&gt;hwss.block_power_control)</div><div class='del'>-			dc-&gt;hwss.block_power_control(dc, &amp;pg_update_state, false);</div><div class='add'>+		/*try to power down unused block*/</div><div class='add'>+		if (dc-&gt;hwss.hw_block_power_down)</div><div class='add'>+			dc-&gt;hwss.hw_block_power_down(dc, &amp;pg_update_state);</div><div class='ctx'> </div><div class='ctx'> 		if (dc-&gt;hwss.root_clock_control)</div><div class='ctx'> 			dc-&gt;hwss.root_clock_control(dc, &amp;pg_update_state, false);</div><div class='hunk'>@@ -1225,3 +1329,44 @@ uint32_t dcn35_get_idle_state(const struct dc *dc)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='add'>+		int num_pipes, struct dc_crtc_timing_adjust adjust)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+	struct drr_params params = {0};</div><div class='add'>+	// DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow</div><div class='add'>+	unsigned int event_triggers = 0x800;</div><div class='add'>+	// Note DRR trigger events are generated regardless of whether num frames met.</div><div class='add'>+	unsigned int num_frames = 2;</div><div class='add'>+</div><div class='add'>+	params.vertical_total_max = adjust.v_total_max;</div><div class='add'>+	params.vertical_total_min = adjust.v_total_min;</div><div class='add'>+	params.vertical_total_mid = adjust.v_total_mid;</div><div class='add'>+	params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_pipes; i++) {</div><div class='add'>+		if ((pipe_ctx[i]-&gt;stream_res.tg != NULL) &amp;&amp; pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs) {</div><div class='add'>+			struct dc_crtc_timing *timing = &amp;pipe_ctx[i]-&gt;stream-&gt;timing;</div><div class='add'>+			struct dc *dc = pipe_ctx[i]-&gt;stream-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+			if (dc-&gt;debug.static_screen_wait_frames) {</div><div class='add'>+				unsigned int frame_rate = timing-&gt;pix_clk_100hz / (timing-&gt;h_total * timing-&gt;v_total);</div><div class='add'>+</div><div class='add'>+				if (frame_rate &gt;= 120 &amp;&amp; dc-&gt;caps.ips_support &amp;&amp;</div><div class='add'>+					dc-&gt;config.disable_ips != DMUB_IPS_DISABLE_ALL) {</div><div class='add'>+					/*ips enable case*/</div><div class='add'>+					num_frames = 2 * (frame_rate % 60);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr)</div><div class='add'>+				pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_drr(</div><div class='add'>+					pipe_ctx[i]-&gt;stream_res.tg, &amp;params);</div><div class='add'>+			if (adjust.v_total_max != 0 &amp;&amp; adjust.v_total_min != 0)</div><div class='add'>+				if (pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control)</div><div class='add'>+					pipe_ctx[i]-&gt;stream_res.tg-&gt;funcs-&gt;set_static_screen_control(</div><div class='add'>+						pipe_ctx[i]-&gt;stream_res.tg,</div><div class='add'>+						event_triggers, num_frames);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h<br/>index 0dff10d179b8..fd66316e33de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h</a></div><div class='hunk'>@@ -57,14 +57,16 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context);</div><div class='ctx'> void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 			       struct dc_state *context);</div><div class='del'>-void dcn35_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	struct pg_block_update *update_state);</div><div class='ctx'> void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	struct pg_block_update *update_state);</div><div class='del'>-void dcn35_block_power_control(struct dc *dc,</div><div class='del'>-	struct pg_block_update *update_state, bool power_on);</div><div class='add'>+void dcn35_hw_block_power_up(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='add'>+void dcn35_hw_block_power_down(struct dc *dc,</div><div class='add'>+	struct pg_block_update *update_state);</div><div class='ctx'> void dcn35_root_clock_control(struct dc *dc,</div><div class='ctx'> 	struct pg_block_update *update_state, bool power_on);</div><div class='ctx'> </div><div class='hunk'>@@ -84,4 +86,8 @@ void dcn35_dsc_pg_control(</div><div class='ctx'> </div><div class='ctx'> void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);</div><div class='ctx'> uint32_t dcn35_get_idle_state(const struct dc *dc);</div><div class='add'>+</div><div class='add'>+void dcn35_set_drr(struct pipe_ctx **pipe_ctx,</div><div class='add'>+		int num_pipes, struct dc_crtc_timing_adjust adjust);</div><div class='add'>+</div><div class='ctx'> #endif /* __DC_HWSS_DCN35_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c<br/>index 296bf3a38cb9..a630aa77dcec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c</a></div><div class='hunk'>@@ -68,7 +68,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.prepare_bandwidth = dcn35_prepare_bandwidth,</div><div class='ctx'> 	.optimize_bandwidth = dcn35_optimize_bandwidth,</div><div class='ctx'> 	.update_bandwidth = dcn20_update_bandwidth,</div><div class='del'>-	.set_drr = dcn10_set_drr,</div><div class='add'>+	.set_drr = dcn35_set_drr,</div><div class='ctx'> 	.get_position = dcn10_get_position,</div><div class='ctx'> 	.set_static_screen_control = dcn30_set_static_screen_control,</div><div class='ctx'> 	.setup_stereo = dcn10_setup_stereo,</div><div class='hunk'>@@ -118,7 +118,8 @@ static const struct hw_sequencer_funcs dcn35_funcs = {</div><div class='ctx'> 	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='ctx'> 	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,</div><div class='ctx'> 	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,</div><div class='del'>-	.block_power_control = dcn35_block_power_control,</div><div class='add'>+	.hw_block_power_up = dcn35_hw_block_power_up,</div><div class='add'>+	.hw_block_power_down = dcn35_hw_block_power_down,</div><div class='ctx'> 	.root_clock_control = dcn35_root_clock_control,</div><div class='ctx'> 	.set_idle_state = dcn35_set_idle_state,</div><div class='ctx'> 	.get_idle_state = dcn35_get_idle_state</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h<br/>index b67015032c35..b67015032c35 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt<br/>new file mode 100644<br/>index 000000000000..951ca2da4486<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/CMakeLists.txt</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+dal3_subdirectory_sources(</div><div class='add'>+  dcn351_init.c</div><div class='add'>+  dcn351_init.h</div><div class='add'>+)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile<br/>new file mode 100644<br/>index 000000000000..b24ad27fe6ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/Makefile</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+#</div><div class='add'>+# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved</div><div class='add'>+#</div><div class='add'>+#  All rights reserved.  This notice is intended as a precaution against</div><div class='add'>+#  inadvertent publication and does not imply publication or any waiver</div><div class='add'>+#  of confidentiality.  The year included in the foregoing notice is the</div><div class='add'>+#  year of creation of the work.</div><div class='add'>+#</div><div class='add'>+#  Authors: AMD</div><div class='add'>+#</div><div class='add'>+# Makefile for DCN351.</div><div class='add'>+</div><div class='add'>+DCN351 = dcn351_init.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_DCN351 = $(addprefix $(AMDDALPATH)/dc/dcn351/,$(DCN351))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_DCN351)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c<br/>new file mode 100644<br/>index 000000000000..143d3fc0221c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c</a></div><div class='hunk'>@@ -0,0 +1,171 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "dce110/dce110_hwseq.h"</div><div class='add'>+#include "dcn10/dcn10_hwseq.h"</div><div class='add'>+#include "dcn20/dcn20_hwseq.h"</div><div class='add'>+#include "dcn21/dcn21_hwseq.h"</div><div class='add'>+#include "dcn30/dcn30_hwseq.h"</div><div class='add'>+#include "dcn301/dcn301_hwseq.h"</div><div class='add'>+#include "dcn31/dcn31_hwseq.h"</div><div class='add'>+#include "dcn32/dcn32_hwseq.h"</div><div class='add'>+#include "dcn35/dcn35_hwseq.h"</div><div class='add'>+</div><div class='add'>+#include "dcn351_init.h"</div><div class='add'>+</div><div class='add'>+static const struct hw_sequencer_funcs dcn351_funcs = {</div><div class='add'>+	.program_gamut_remap = dcn30_program_gamut_remap,</div><div class='add'>+	.init_hw = dcn35_init_hw,</div><div class='add'>+	.power_down_on_boot = dcn35_power_down_on_boot,</div><div class='add'>+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,</div><div class='add'>+	.apply_ctx_for_surface = NULL,</div><div class='add'>+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,</div><div class='add'>+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,</div><div class='add'>+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,</div><div class='add'>+	.update_plane_addr = dcn20_update_plane_addr,</div><div class='add'>+	.update_dchub = dcn10_update_dchub,</div><div class='add'>+	.update_pending_status = dcn10_update_pending_status,</div><div class='add'>+	.program_output_csc = dcn20_program_output_csc,</div><div class='add'>+	.enable_accelerated_mode = dce110_enable_accelerated_mode,</div><div class='add'>+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,</div><div class='add'>+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,</div><div class='add'>+	.update_info_frame = dcn31_update_info_frame,</div><div class='add'>+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,</div><div class='add'>+	.enable_stream = dcn20_enable_stream,</div><div class='add'>+	.disable_stream = dce110_disable_stream,</div><div class='add'>+	.unblank_stream = dcn32_unblank_stream,</div><div class='add'>+	.blank_stream = dce110_blank_stream,</div><div class='add'>+	.enable_audio_stream = dce110_enable_audio_stream,</div><div class='add'>+	.disable_audio_stream = dce110_disable_audio_stream,</div><div class='add'>+	.disable_plane = dcn35_disable_plane,</div><div class='add'>+	.disable_pixel_data = dcn20_disable_pixel_data,</div><div class='add'>+	.pipe_control_lock = dcn20_pipe_control_lock,</div><div class='add'>+	.interdependent_update_lock = dcn10_lock_all_pipes,</div><div class='add'>+	.cursor_lock = dcn10_cursor_lock,</div><div class='add'>+	.prepare_bandwidth = dcn35_prepare_bandwidth,</div><div class='add'>+	.optimize_bandwidth = dcn35_optimize_bandwidth,</div><div class='add'>+	.update_bandwidth = dcn20_update_bandwidth,</div><div class='add'>+	.set_drr = dcn10_set_drr,</div><div class='add'>+	.get_position = dcn10_get_position,</div><div class='add'>+	.set_static_screen_control = dcn30_set_static_screen_control,</div><div class='add'>+	.setup_stereo = dcn10_setup_stereo,</div><div class='add'>+	.set_avmute = dcn30_set_avmute,</div><div class='add'>+	.log_hw_state = dcn10_log_hw_state,</div><div class='add'>+	.get_hw_state = dcn10_get_hw_state,</div><div class='add'>+	.clear_status_bits = dcn10_clear_status_bits,</div><div class='add'>+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,</div><div class='add'>+	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='add'>+	.edp_power_control = dce110_edp_power_control,</div><div class='add'>+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,</div><div class='add'>+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,</div><div class='add'>+	.set_cursor_position = dcn10_set_cursor_position,</div><div class='add'>+	.set_cursor_attribute = dcn10_set_cursor_attribute,</div><div class='add'>+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,</div><div class='add'>+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,</div><div class='add'>+	.set_clock = dcn10_set_clock,</div><div class='add'>+	.get_clock = dcn10_get_clock,</div><div class='add'>+	.program_triplebuffer = dcn20_program_triple_buffer,</div><div class='add'>+	.enable_writeback = dcn30_enable_writeback,</div><div class='add'>+	.disable_writeback = dcn30_disable_writeback,</div><div class='add'>+	.update_writeback = dcn30_update_writeback,</div><div class='add'>+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,</div><div class='add'>+	.dmdata_status_done = dcn20_dmdata_status_done,</div><div class='add'>+	.program_dmdata_engine = dcn30_program_dmdata_engine,</div><div class='add'>+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,</div><div class='add'>+	.init_sys_ctx = dcn31_init_sys_ctx,</div><div class='add'>+	.init_vm_ctx = dcn20_init_vm_ctx,</div><div class='add'>+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,</div><div class='add'>+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,</div><div class='add'>+	.calc_vupdate_position = dcn10_calc_vupdate_position,</div><div class='add'>+	.power_down = dce110_power_down,</div><div class='add'>+	.set_backlight_level = dcn21_set_backlight_level,</div><div class='add'>+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,</div><div class='add'>+	.set_pipe = dcn21_set_pipe,</div><div class='add'>+	.enable_lvds_link_output = dce110_enable_lvds_link_output,</div><div class='add'>+	.enable_tmds_link_output = dce110_enable_tmds_link_output,</div><div class='add'>+	.enable_dp_link_output = dce110_enable_dp_link_output,</div><div class='add'>+	.disable_link_output = dcn32_disable_link_output,</div><div class='add'>+	.z10_restore = dcn35_z10_restore,</div><div class='add'>+	.z10_save_init = dcn31_z10_save_init,</div><div class='add'>+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,</div><div class='add'>+	.optimize_pwr_state = dcn21_optimize_pwr_state,</div><div class='add'>+	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,</div><div class='add'>+	.update_visual_confirm_color = dcn10_update_visual_confirm_color,</div><div class='add'>+	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,</div><div class='add'>+	.update_dsc_pg = dcn32_update_dsc_pg,</div><div class='add'>+	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,</div><div class='add'>+	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,</div><div class='add'>+	.hw_block_power_up = dcn35_hw_block_power_up,</div><div class='add'>+	.hw_block_power_down = dcn35_hw_block_power_down,</div><div class='add'>+	.root_clock_control = dcn35_root_clock_control,</div><div class='add'>+	.set_idle_state = dcn35_set_idle_state,</div><div class='add'>+	.get_idle_state = dcn35_get_idle_state</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwseq_private_funcs dcn351_private_funcs = {</div><div class='add'>+	.init_pipes = dcn35_init_pipes,</div><div class='add'>+	.update_plane_addr = dcn20_update_plane_addr,</div><div class='add'>+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,</div><div class='add'>+	.update_mpcc = dcn20_update_mpcc,</div><div class='add'>+	.set_input_transfer_func = dcn32_set_input_transfer_func,</div><div class='add'>+	.set_output_transfer_func = dcn32_set_output_transfer_func,</div><div class='add'>+	.power_down = dce110_power_down,</div><div class='add'>+	.enable_display_power_gating = dcn10_dummy_display_power_gating,</div><div class='add'>+	.blank_pixel_data = dcn20_blank_pixel_data,</div><div class='add'>+	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,</div><div class='add'>+	.enable_stream_timing = dcn20_enable_stream_timing,</div><div class='add'>+	.edp_backlight_control = dce110_edp_backlight_control,</div><div class='add'>+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,</div><div class='add'>+	.did_underflow_occur = dcn10_did_underflow_occur,</div><div class='add'>+	.init_blank = dcn20_init_blank,</div><div class='add'>+	.disable_vga = NULL,</div><div class='add'>+	.bios_golden_init = dcn10_bios_golden_init,</div><div class='add'>+	.plane_atomic_disable = dcn35_plane_atomic_disable,</div><div class='add'>+	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/</div><div class='add'>+	//.hubp_pg_control = dcn35_hubp_pg_control,</div><div class='add'>+	.enable_power_gating_plane = dcn35_enable_power_gating_plane,</div><div class='add'>+	.dpp_root_clock_control = dcn35_dpp_root_clock_control,</div><div class='add'>+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,</div><div class='add'>+	.update_odm = dcn35_update_odm,</div><div class='add'>+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,</div><div class='add'>+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,</div><div class='add'>+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,</div><div class='add'>+	.dccg_init = dcn20_dccg_init,</div><div class='add'>+	.set_mcm_luts = dcn32_set_mcm_luts,</div><div class='add'>+	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,</div><div class='add'>+	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,</div><div class='add'>+	.set_pixels_per_cycle = dcn32_set_pixels_per_cycle,</div><div class='add'>+	.is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,</div><div class='add'>+	.dsc_pg_control = dcn35_dsc_pg_control,</div><div class='add'>+	.dsc_pg_status = dcn32_dsc_pg_status,</div><div class='add'>+	.enable_plane = dcn35_enable_plane,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcn351_hw_sequencer_construct(struct dc *dc)</div><div class='add'>+{</div><div class='add'>+	dc-&gt;hwss = dcn351_funcs;</div><div class='add'>+	dc-&gt;hwseq-&gt;funcs = dcn351_private_funcs;</div><div class='add'>+</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h<br/>new file mode 100644<br/>index 000000000000..970b01008b23<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ * Authors: AMD</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DC_DCN351_INIT_H__</div><div class='add'>+#define __DC_DCN351_INIT_H__</div><div class='add'>+</div><div class='add'>+struct dc;</div><div class='add'>+</div><div class='add'>+void dcn351_hw_sequencer_construct(struct dc *dc);</div><div class='add'>+</div><div class='add'>+#endif /* __DC_DCN351_INIT_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h<br/>index 452680fe9aab..a54399383318 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h</a></div><div class='hunk'>@@ -50,7 +50,7 @@ struct pg_block_update;</div><div class='ctx'> struct subvp_pipe_control_lock_fast_params {</div><div class='ctx'> 	struct dc *dc;</div><div class='ctx'> 	bool lock;</div><div class='del'>-	struct pipe_ctx *pipe_ctx;</div><div class='add'>+	bool subvp_immediate_flip;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct pipe_control_lock_params {</div><div class='hunk'>@@ -200,7 +200,7 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 			struct dc_state *context);</div><div class='ctx'> 	enum dc_status (*apply_ctx_to_hw)(struct dc *dc,</div><div class='ctx'> 			struct dc_state *context);</div><div class='del'>-	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='add'>+	void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank);</div><div class='ctx'> 	void (*apply_ctx_for_surface)(struct dc *dc,</div><div class='ctx'> 			const struct dc_stream_state *stream,</div><div class='hunk'>@@ -248,6 +248,7 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 	void (*enable_per_frame_crtc_position_reset)(struct dc *dc,</div><div class='ctx'> 			int group_size, struct pipe_ctx *grouped_pipes[]);</div><div class='ctx'> 	void (*enable_timing_synchronization)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='ctx'> 			int group_index, int group_size,</div><div class='ctx'> 			struct pipe_ctx *grouped_pipes[]);</div><div class='ctx'> 	void (*enable_vblanks_synchronization)(struct dc *dc,</div><div class='hunk'>@@ -414,8 +415,10 @@ struct hw_sequencer_funcs {</div><div class='ctx'> 		struct pg_block_update *update_state);</div><div class='ctx'> 	void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		struct pg_block_update *update_state);</div><div class='del'>-	void (*block_power_control)(struct dc *dc,</div><div class='del'>-		struct pg_block_update *update_state, bool power_on);</div><div class='add'>+	void (*hw_block_power_up)(struct dc *dc,</div><div class='add'>+		struct pg_block_update *update_state);</div><div class='add'>+	void (*hw_block_power_down)(struct dc *dc,</div><div class='add'>+		struct pg_block_update *update_state);</div><div class='ctx'> 	void (*root_clock_control)(struct dc *dc,</div><div class='ctx'> 		struct pg_block_update *update_state, bool power_on);</div><div class='ctx'> 	void (*set_idle_state)(const struct dc *dc, bool allow_idle);</div><div class='hunk'>@@ -452,17 +455,18 @@ void get_mpctree_visual_confirm_color(</div><div class='ctx'> 		struct tg_color *color);</div><div class='ctx'> </div><div class='ctx'> void get_subvp_visual_confirm_color(</div><div class='del'>-	struct dc *dc,</div><div class='del'>-	struct dc_state *context,</div><div class='ctx'> 	struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 	struct tg_color *color);</div><div class='ctx'> </div><div class='ctx'> void get_mclk_switch_visual_confirm_color(</div><div class='del'>-		struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx,</div><div class='ctx'> 		struct tg_color *color);</div><div class='ctx'> </div><div class='add'>+void set_p_state_switch_method(</div><div class='add'>+		struct dc *dc,</div><div class='add'>+		struct dc_state *context,</div><div class='add'>+		struct pipe_ctx *pipe_ctx);</div><div class='add'>+</div><div class='ctx'> void hwss_execute_sequence(struct dc *dc,</div><div class='ctx'> 		struct block_sequence block_sequence[],</div><div class='ctx'> 		int num_steps);</div><div class='hunk'>@@ -472,7 +476,8 @@ void hwss_build_fast_sequence(struct dc *dc,</div><div class='ctx'> 		unsigned int dmub_cmd_count,</div><div class='ctx'> 		struct block_sequence block_sequence[],</div><div class='ctx'> 		int *num_steps,</div><div class='del'>-		struct pipe_ctx *pipe_ctx);</div><div class='add'>+		struct pipe_ctx *pipe_ctx,</div><div class='add'>+		struct dc_stream_status *stream_status);</div><div class='ctx'> </div><div class='ctx'> void hwss_send_dmcub_cmd(union block_sequence_params *params);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h<br/>index 82c592166875..6137cf09aa54 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h</a></div><div class='hunk'>@@ -79,6 +79,7 @@ struct hwseq_private_funcs {</div><div class='ctx'> 	void (*update_plane_addr)(const struct dc *dc,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*plane_atomic_disconnect)(struct dc *dc,</div><div class='add'>+			struct dc_state *state,</div><div class='ctx'> 			struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);</div><div class='ctx'> 	bool (*set_input_transfer_func)(struct dc *dc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h<br/>index bac1420b1de8..f74ae0d41d3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/core_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/core_types.h</a></div><div class='hunk'>@@ -200,11 +200,8 @@ struct resource_funcs {</div><div class='ctx'> 			unsigned int pipe_cnt,</div><div class='ctx'>             unsigned int index);</div><div class='ctx'> </div><div class='del'>-	bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update);</div><div class='del'>-	void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context);</div><div class='ctx'> 	void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);</div><div class='del'>-	void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);</div><div class='del'>-	void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config);</div><div class='add'>+	void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct audio_support{</div><div class='hunk'>@@ -384,6 +381,16 @@ union pipe_update_flags {</div><div class='ctx'> 	uint32_t raw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum p_state_switch_method {</div><div class='add'>+	P_STATE_UNKNOWN						= 0,</div><div class='add'>+	P_STATE_V_BLANK						= 1,</div><div class='add'>+	P_STATE_FPO,</div><div class='add'>+	P_STATE_V_ACTIVE,</div><div class='add'>+	P_STATE_SUB_VP,</div><div class='add'>+	P_STATE_DRR_SUB_VP,</div><div class='add'>+	P_STATE_V_BLANK_SUB_VP</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct pipe_ctx {</div><div class='ctx'> 	struct dc_plane_state *plane_state;</div><div class='ctx'> 	struct dc_stream_state *stream;</div><div class='hunk'>@@ -432,6 +439,7 @@ struct pipe_ctx {</div><div class='ctx'> 	struct dwbc *dwbc;</div><div class='ctx'> 	struct mcif_wb *mcif_wb;</div><div class='ctx'> 	union pipe_update_flags update_flags;</div><div class='add'>+	enum p_state_switch_method p_state_type;</div><div class='ctx'> 	struct tg_color visual_confirm_color;</div><div class='ctx'> 	bool has_vactive_margin;</div><div class='ctx'> 	/* subvp_index: only valid if the pipe is a SUBVP_MAIN*/</div><div class='hunk'>@@ -525,6 +533,14 @@ struct dc_state {</div><div class='ctx'> 	 * @stream_status: Planes status on a given stream</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dc_stream_status stream_status[MAX_PIPES];</div><div class='add'>+	/**</div><div class='add'>+	 * @phantom_streams: Stream state properties for phantoms</div><div class='add'>+	 */</div><div class='add'>+	struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES];</div><div class='add'>+	/**</div><div class='add'>+	 * @phantom_planes: Planes state properties for phantoms</div><div class='add'>+	 */</div><div class='add'>+	struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES];</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @stream_count: Total of streams in use</div><div class='hunk'>@@ -533,6 +549,14 @@ struct dc_state {</div><div class='ctx'> 	uint8_t stream_mask;</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * @stream_count: Total phantom streams in use</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phantom_stream_count;</div><div class='add'>+	/**</div><div class='add'>+	 * @stream_count: Total phantom planes in use</div><div class='add'>+	 */</div><div class='add'>+	uint8_t phantom_plane_count;</div><div class='add'>+	/**</div><div class='ctx'> 	 * @res_ctx: Persistent state of resources</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct resource_context res_ctx;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h<br/>index 33db15d69f23..3f0161d64675 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/abm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/abm.h</a></div><div class='hunk'>@@ -36,7 +36,7 @@ struct abm {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct abm_funcs {</div><div class='del'>-	void (*abm_init)(struct abm *abm, uint32_t back_light);</div><div class='add'>+	void (*abm_init)(struct abm *abm, uint32_t back_light, uint32_t user_level);</div><div class='ctx'> 	bool (*set_abm_level)(struct abm *abm, unsigned int abm_level);</div><div class='ctx'> 	bool (*set_abm_immediate_disable)(struct abm *abm, unsigned int panel_inst);</div><div class='ctx'> 	bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);</div><div class='hunk'>@@ -64,7 +64,8 @@ struct abm_funcs {</div><div class='ctx'> 	bool (*set_pipe_ex)(struct abm *abm,</div><div class='ctx'> 			unsigned int otg_inst,</div><div class='ctx'> 			unsigned int option,</div><div class='del'>-			unsigned int panel_inst);</div><div class='add'>+			unsigned int panel_inst,</div><div class='add'>+			unsigned int pwrseq_inst);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h<br/>index fa9614bcb160..17e014d3bdc8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h</a></div><div class='hunk'>@@ -62,6 +62,25 @@ struct dcn3_clk_internal {</div><div class='ctx'> 	uint32_t CLK4_CLK0_CURRENT_CNT; //fclk</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dcn35_clk_internal {</div><div class='add'>+	int dummy;</div><div class='add'>+	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk</div><div class='add'>+	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk</div><div class='add'>+	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk</div><div class='add'>+	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk</div><div class='add'>+	uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk</div><div class='add'>+	//uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk</div><div class='add'>+	//uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk</div><div class='add'>+	uint32_t CLK1_CLK3_DS_CNTL;	    //dcf_deep_sleep_divider</div><div class='add'>+	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow</div><div class='add'>+</div><div class='add'>+	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass</div><div class='add'>+	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass</div><div class='add'>+	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass</div><div class='add'>+	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass</div><div class='add'>+	uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dcn301_clk_internal {</div><div class='ctx'> 	int dummy;</div><div class='ctx'> 	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk</div><div class='hunk'>@@ -314,6 +333,7 @@ struct clk_mgr {</div><div class='ctx'> 	bool force_smu_not_present;</div><div class='ctx'> 	bool dc_mode_softmax_enabled;</div><div class='ctx'> 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes</div><div class='add'>+	int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314</div><div class='ctx'> 	int dentist_vco_freq_khz;</div><div class='ctx'> 	struct clk_state_registers_and_bypass boot_snapshot;</div><div class='ctx'> 	struct clk_bw_params *bw_params;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h<br/>index ce2f0c0e82bd..b9a06bf84cc9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h</a></div><div class='hunk'>@@ -59,8 +59,8 @@ enum dentist_dispclk_change_mode {</div><div class='ctx'> struct dp_dto_params {</div><div class='ctx'> 	int otg_inst;</div><div class='ctx'> 	enum signal_type signal;</div><div class='del'>-	long long pixclk_hz;</div><div class='del'>-	long long refclk_hz;</div><div class='add'>+	uint64_t pixclk_hz;</div><div class='add'>+	uint64_t refclk_hz;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum pixel_rate_div {</div><div class='hunk'>@@ -201,6 +201,10 @@ struct dccg_funcs {</div><div class='ctx'> 			struct dccg *dccg,</div><div class='ctx'> 			enum streamclk_source src,</div><div class='ctx'> 			uint32_t otg_inst);</div><div class='add'>+	void (*set_dto_dscclk)(</div><div class='add'>+			struct dccg *dccg,</div><div class='add'>+			uint32_t dsc_inst);</div><div class='add'>+	void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif //__DAL_DCCG_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h<br/>index 86b711dcc785..729ca0064e94 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h</a></div><div class='hunk'>@@ -188,6 +188,10 @@ struct dwbc_funcs {</div><div class='ctx'> 	bool (*is_enabled)(</div><div class='ctx'> 		struct dwbc *dwbc);</div><div class='ctx'> </div><div class='add'>+	void (*set_fc_enable)(</div><div class='add'>+		struct dwbc *dwbc,</div><div class='add'>+		enum dwb_frame_capture_enable enable);</div><div class='add'>+</div><div class='ctx'> 	void (*set_stereo)(</div><div class='ctx'> 		struct dwbc *dwbc,</div><div class='ctx'> 		struct dwb_stereo_params *stereo_params);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h<br/>index b95ae9596c3b..dcae23faeee3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h</a></div><div class='hunk'>@@ -43,6 +43,7 @@</div><div class='ctx'>  * to be used inside loops and for determining array sizes.</div><div class='ctx'>  */</div><div class='ctx'> #define MAX_PIPES 6</div><div class='add'>+#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)</div><div class='ctx'> #define MAX_DIG_LINK_ENCODERS 7</div><div class='ctx'> #define MAX_DWB_PIPES	1</div><div class='ctx'> #define MAX_HPO_DP2_ENCODERS	4</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h<br/>index 24af9d80b937..5dcbaa2db964 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h</a></div><div class='hunk'>@@ -40,6 +40,7 @@ struct panel_cntl_backlight_registers {</div><div class='ctx'> 	unsigned int BL_PWM_PERIOD_CNTL;</div><div class='ctx'> 	unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;</div><div class='ctx'> 	unsigned int PANEL_PWRSEQ_REF_DIV2;</div><div class='add'>+	unsigned int USER_LEVEL;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct panel_cntl_funcs {</div><div class='hunk'>@@ -56,12 +57,14 @@ struct panel_cntl_funcs {</div><div class='ctx'> struct panel_cntl_init_data {</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	uint32_t inst;</div><div class='add'>+	uint32_t pwrseq_inst;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct panel_cntl {</div><div class='ctx'> 	const struct panel_cntl_funcs *funcs;</div><div class='ctx'> 	struct dc_context *ctx;</div><div class='ctx'> 	uint32_t inst;</div><div class='add'>+	uint32_t pwrseq_inst;</div><div class='ctx'> 	/* registers setting needs to be saved and restored at InitBacklight */</div><div class='ctx'> 	struct panel_cntl_backlight_registers stored_backlight_registers;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h<br/>index b9812afb886b..00ea3864dd4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h</a></div><div class='hunk'>@@ -47,8 +47,6 @@ struct pg_cntl_funcs {</div><div class='ctx'> 	void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);</div><div class='ctx'> 	void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);</div><div class='ctx'> 	void (*init_pg_status)(struct pg_cntl *pg_cntl);</div><div class='del'>-</div><div class='del'>-	void (*set_force_poweron_domain22)(struct pg_cntl *pg_cntl, bool power_on);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif //__DC_PG_CNTL_H__</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h<br/>index d7685368140a..26fe81f213da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/link.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/link.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/link.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/link.h</a></div><div class='hunk'>@@ -281,11 +281,16 @@ struct link_service {</div><div class='ctx'> 			const unsigned int *power_opts);</div><div class='ctx'> 	bool (*edp_setup_replay)(struct dc_link *link,</div><div class='ctx'> 			const struct dc_stream_state *stream);</div><div class='add'>+	bool (*edp_send_replay_cmd)(struct dc_link *link,</div><div class='add'>+			enum replay_FW_Message_type msg,</div><div class='add'>+			union dmub_replay_cmd_set *cmd_data);</div><div class='ctx'> 	bool (*edp_set_coasting_vtotal)(</div><div class='ctx'> 			struct dc_link *link, uint16_t coasting_vtotal);</div><div class='ctx'> 	bool (*edp_replay_residency)(const struct dc_link *link,</div><div class='ctx'> 			unsigned int *residency, const bool is_start,</div><div class='ctx'> 			const bool is_alpm);</div><div class='add'>+	bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link,</div><div class='add'>+			const unsigned int *power_opts, uint16_t coasting_vtotal);</div><div class='ctx'> </div><div class='ctx'> 	bool (*edp_wait_for_t12)(struct dc_link *link);</div><div class='ctx'> 	bool (*edp_is_ilr_optimization_required)(struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h<br/>index 06ca8bfb91e7..c958ef37b78a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/inc/resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/inc/resource.h</a></div><div class='hunk'>@@ -501,6 +501,18 @@ int recource_find_free_pipe_not_used_in_cur_res_ctx(</div><div class='ctx'> 		const struct resource_pool *pool);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * Look for a free pipe in new resource context that is used in current resource</div><div class='add'>+ * context as an OTG master pipe.</div><div class='add'>+ *</div><div class='add'>+ * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise</div><div class='add'>+ * pipe idx of the free pipe</div><div class='add'>+ */</div><div class='add'>+int recource_find_free_pipe_used_as_otg_master_in_cur_res_ctx(</div><div class='add'>+		const struct resource_context *cur_res_ctx,</div><div class='add'>+		struct resource_context *new_res_ctx,</div><div class='add'>+		const struct resource_pool *pool);</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * Look for a free pipe in new resource context that is used as a secondary DPP</div><div class='ctx'>  * pipe in any MPCC combine in current resource context.</div><div class='ctx'>  * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise</div><div class='hunk'>@@ -561,9 +573,6 @@ void update_audio_usage(</div><div class='ctx'> </div><div class='ctx'> unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);</div><div class='ctx'> </div><div class='del'>-void get_audio_check(struct audio_info *aud_modes,</div><div class='del'>-	struct audio_check *aud_chk);</div><div class='del'>-</div><div class='ctx'> bool get_temp_dp_link_res(struct dc_link *link,</div><div class='ctx'> 		struct link_resource *link_res,</div><div class='ctx'> 		struct dc_link_settings *link_settings);</div><div class='hunk'>@@ -610,5 +619,4 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream);</div><div class='del'>-</div><div class='ctx'> #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c<br/>index f2fe523f914f..24153b0df503 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_detection.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_detection.c</a></div><div class='hunk'>@@ -879,7 +879,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,</div><div class='ctx'> 			(link-&gt;dpcd_sink_ext_caps.bits.oled == 1)) {</div><div class='ctx'> 			dpcd_set_source_specific_data(link);</div><div class='ctx'> 			msleep(post_oui_delay);</div><div class='del'>-			set_cached_brightness_aux(link);</div><div class='add'>+			set_default_brightness_aux(link);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		return true;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c<br/>index 34a4a8c0e18c..3cbfbf8d107e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_dpms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_dpms.c</a></div><div class='hunk'>@@ -776,10 +776,26 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'>  */</div><div class='ctx'> void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> {</div><div class='add'>+	/* TODO: Move this to HWSS as this is hardware programming sequence not a</div><div class='add'>+	 * link layer sequence</div><div class='add'>+	 */</div><div class='ctx'> 	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='add'>+	struct dc *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='ctx'> 	struct pipe_ctx *odm_pipe;</div><div class='ctx'> 	int opp_cnt = 1;</div><div class='add'>+	struct dccg *dccg = dc-&gt;res_pool-&gt;dccg;</div><div class='add'>+	/* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN</div><div class='add'>+	 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a</div><div class='add'>+	 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is</div><div class='add'>+	 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings</div><div class='add'>+	 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger</div><div class='add'>+	 * this problem. We are implementing a workaround here to keep using dscclk</div><div class='add'>+	 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e</div><div class='add'>+	 * 48Mhz) pixel clock to avoid hitting this problem.</div><div class='add'>+	 */</div><div class='add'>+	bool should_use_dto_dscclk = (dccg-&gt;funcs-&gt;set_dto_dscclk != NULL) &amp;&amp;</div><div class='add'>+			stream-&gt;timing.pix_clk_100hz &gt; 480000;</div><div class='ctx'> 	DC_LOGGER_INIT(dsc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='ctx'> 	for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='hunk'>@@ -802,11 +818,15 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> </div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_set_config(dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 		dsc-&gt;funcs-&gt;dsc_enable(dsc, pipe_ctx-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+		if (should_use_dto_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, dsc-&gt;inst);</div><div class='ctx'> 		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='ctx'> 			struct display_stream_compressor *odm_dsc = odm_pipe-&gt;stream_res.dsc;</div><div class='ctx'> </div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_set_config(odm_dsc, &amp;dsc_cfg, &amp;dsc_optc_cfg);</div><div class='ctx'> 			odm_dsc-&gt;funcs-&gt;dsc_enable(odm_dsc, odm_pipe-&gt;stream_res.opp-&gt;inst);</div><div class='add'>+			if (should_use_dto_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_dto_dscclk(dccg, odm_dsc-&gt;inst);</div><div class='ctx'> 		}</div><div class='ctx'> 		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;</div><div class='ctx'> 		dsc_cfg.pic_width *= opp_cnt;</div><div class='hunk'>@@ -856,9 +876,14 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* disable DSC block */</div><div class='add'>+		if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+			dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, pipe_ctx-&gt;stream_res.dsc-&gt;inst);</div><div class='ctx'> 		pipe_ctx-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(pipe_ctx-&gt;stream_res.dsc);</div><div class='del'>-		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe)</div><div class='add'>+		for (odm_pipe = pipe_ctx-&gt;next_odm_pipe; odm_pipe; odm_pipe = odm_pipe-&gt;next_odm_pipe) {</div><div class='add'>+			if (dccg-&gt;funcs-&gt;set_ref_dscclk)</div><div class='add'>+				dccg-&gt;funcs-&gt;set_ref_dscclk(dccg, odm_pipe-&gt;stream_res.dsc-&gt;inst);</div><div class='ctx'> 			odm_pipe-&gt;stream_res.dsc-&gt;funcs-&gt;dsc_disable(odm_pipe-&gt;stream_res.dsc);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -875,11 +900,15 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi</div><div class='ctx'> {</div><div class='ctx'> 	struct display_stream_compressor *dsc = pipe_ctx-&gt;stream_res.dsc;</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='del'>-	DC_LOGGER_INIT(dsc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='del'>-	if (!pipe_ctx-&gt;stream-&gt;timing.flags.DSC || !dsc)</div><div class='add'>+	if (!pipe_ctx-&gt;stream-&gt;timing.flags.DSC)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!dsc)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	DC_LOGGER_INIT(dsc-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		struct dsc_config dsc_cfg;</div><div class='ctx'> 		uint8_t dsc_packed_pps[128];</div><div class='hunk'>@@ -1057,18 +1086,21 @@ static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)</div><div class='ctx'> 	uint32_t denominator = 1;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006</div><div class='add'>+	 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not</div><div class='add'>+	 * required when determining PBN/time slot utilization on the link between</div><div class='add'>+	 * us and the branch, since that overhead is already accounted for in</div><div class='add'>+	 * the get_pbn_per_slot function.</div><div class='add'>+	 *</div><div class='ctx'> 	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on</div><div class='ctx'> 	 * common multiplier to render an integer PBN for all link rate/lane</div><div class='ctx'> 	 * counts combinations</div><div class='ctx'> 	 * calculate</div><div class='del'>-	 * peak_kbps *= (1006/1000)</div><div class='ctx'> 	 * peak_kbps *= (64/54)</div><div class='del'>-	 * peak_kbps *= 8    convert to bytes</div><div class='add'>+	 * peak_kbps /= (8 * 1000) convert to bytes</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	numerator = 64 * PEAK_FACTOR_X1000;</div><div class='del'>-	denominator = 54 * 8 * 1000 * 1000;</div><div class='add'>+	numerator = 64;</div><div class='add'>+	denominator = 54 * 8 * 1000;</div><div class='ctx'> 	kbps *= numerator;</div><div class='ctx'> 	peak_kbps = dc_fixpt_from_fraction(kbps, denominator);</div><div class='ctx'> </div><div class='hunk'>@@ -1247,86 +1279,6 @@ static void remove_stream_from_alloc_table(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum dc_status deallocate_mst_payload_with_temp_drm_wa(</div><div class='del'>-		struct pipe_ctx *pipe_ctx)</div><div class='del'>-{</div><div class='del'>-	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='del'>-	struct dc_link *link = stream-&gt;link;</div><div class='del'>-	struct dc_dp_mst_stream_allocation_table proposed_table = {0};</div><div class='del'>-	struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);</div><div class='del'>-	int i;</div><div class='del'>-	bool mst_mode = (link-&gt;type == dc_connection_mst_branch);</div><div class='del'>-	/* adjust for drm changes*/</div><div class='del'>-	const struct link_hwss *link_hwss = get_link_hwss(link, &amp;pipe_ctx-&gt;link_res);</div><div class='del'>-	const struct dc_link_settings empty_link_settings = {0};</div><div class='del'>-	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='del'>-</div><div class='del'>-	if (link_hwss-&gt;ext.set_throttled_vcp_size)</div><div class='del'>-		link_hwss-&gt;ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);</div><div class='del'>-	if (link_hwss-&gt;ext.set_hblank_min_symbol_width)</div><div class='del'>-		link_hwss-&gt;ext.set_hblank_min_symbol_width(pipe_ctx,</div><div class='del'>-				&amp;empty_link_settings,</div><div class='del'>-				avg_time_slots_per_mtp);</div><div class='del'>-</div><div class='del'>-	if (dm_helpers_dp_mst_write_payload_allocation_table(</div><div class='del'>-			stream-&gt;ctx,</div><div class='del'>-			stream,</div><div class='del'>-			&amp;proposed_table,</div><div class='del'>-			false))</div><div class='del'>-		update_mst_stream_alloc_table(</div><div class='del'>-				link,</div><div class='del'>-				pipe_ctx-&gt;stream_res.stream_enc,</div><div class='del'>-				pipe_ctx-&gt;stream_res.hpo_dp_stream_enc,</div><div class='del'>-				&amp;proposed_table);</div><div class='del'>-	else</div><div class='del'>-		DC_LOG_WARNING("Failed to update"</div><div class='del'>-				"MST allocation table for"</div><div class='del'>-				"pipe idx:%d\n",</div><div class='del'>-				pipe_ctx-&gt;pipe_idx);</div><div class='del'>-</div><div class='del'>-	DC_LOG_MST("%s"</div><div class='del'>-			"stream_count: %d: ",</div><div class='del'>-			__func__,</div><div class='del'>-			link-&gt;mst_stream_alloc_table.stream_count);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_CONTROLLER_NUM; i++) {</div><div class='del'>-		DC_LOG_MST("stream_enc[%d]: %p      "</div><div class='del'>-		"stream[%d].hpo_dp_stream_enc: %p      "</div><div class='del'>-		"stream[%d].vcp_id: %d      "</div><div class='del'>-		"stream[%d].slot_count: %d\n",</div><div class='del'>-		i,</div><div class='del'>-		(void *) link-&gt;mst_stream_alloc_table.stream_allocations[i].stream_enc,</div><div class='del'>-		i,</div><div class='del'>-		(void *) link-&gt;mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,</div><div class='del'>-		i,</div><div class='del'>-		link-&gt;mst_stream_alloc_table.stream_allocations[i].vcp_id,</div><div class='del'>-		i,</div><div class='del'>-		link-&gt;mst_stream_alloc_table.stream_allocations[i].slot_count);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (link_hwss-&gt;ext.update_stream_allocation_table == NULL ||</div><div class='del'>-			link_dp_get_encoding_format(&amp;link-&gt;cur_link_settings) == DP_UNKNOWN_ENCODING) {</div><div class='del'>-		DC_LOG_DEBUG("Unknown encoding format\n");</div><div class='del'>-		return DC_ERROR_UNEXPECTED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	link_hwss-&gt;ext.update_stream_allocation_table(link, &amp;pipe_ctx-&gt;link_res,</div><div class='del'>-			&amp;link-&gt;mst_stream_alloc_table);</div><div class='del'>-</div><div class='del'>-	if (mst_mode) {</div><div class='del'>-		dm_helpers_dp_mst_poll_for_allocation_change_trigger(</div><div class='del'>-			stream-&gt;ctx,</div><div class='del'>-			stream);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dm_helpers_dp_mst_send_payload_allocation(</div><div class='del'>-			stream-&gt;ctx,</div><div class='del'>-			stream,</div><div class='del'>-			false);</div><div class='del'>-</div><div class='del'>-	return DC_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc_stream_state *stream = pipe_ctx-&gt;stream;</div><div class='hunk'>@@ -1339,9 +1291,6 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	const struct dc_link_settings empty_link_settings = {0};</div><div class='ctx'> 	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;dc-&gt;debug.temp_mst_deallocation_sequence)</div><div class='del'>-		return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx);</div><div class='del'>-</div><div class='ctx'> 	/* deallocate_mst_payload is called before disable link. When mode or</div><div class='ctx'> 	 * disable/enable monitor, new stream is created which is not in link</div><div class='ctx'> 	 * stream[] yet. For this, payload is not allocated yet, so de-alloc</div><div class='hunk'>@@ -1414,16 +1363,14 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	link_hwss-&gt;ext.update_stream_allocation_table(link, &amp;pipe_ctx-&gt;link_res,</div><div class='ctx'> 			&amp;link-&gt;mst_stream_alloc_table);</div><div class='ctx'> </div><div class='del'>-	if (mst_mode) {</div><div class='add'>+	if (mst_mode)</div><div class='ctx'> 		dm_helpers_dp_mst_poll_for_allocation_change_trigger(</div><div class='ctx'> 			stream-&gt;ctx,</div><div class='ctx'> 			stream);</div><div class='ctx'> </div><div class='del'>-		dm_helpers_dp_mst_send_payload_allocation(</div><div class='del'>-				stream-&gt;ctx,</div><div class='del'>-				stream,</div><div class='del'>-				false);</div><div class='del'>-	}</div><div class='add'>+	dm_helpers_dp_mst_update_mst_mgr_for_deallocation(</div><div class='add'>+			stream-&gt;ctx,</div><div class='add'>+			stream);</div><div class='ctx'> </div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='hunk'>@@ -1504,12 +1451,10 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 			stream-&gt;ctx,</div><div class='ctx'> 			stream);</div><div class='ctx'> </div><div class='del'>-	if (ret != ACT_LINK_LOST) {</div><div class='add'>+	if (ret != ACT_LINK_LOST)</div><div class='ctx'> 		dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 				stream-&gt;ctx,</div><div class='del'>-				stream,</div><div class='del'>-				true);</div><div class='del'>-	}</div><div class='add'>+				stream);</div><div class='ctx'> </div><div class='ctx'> 	/* slot X.Y for only current stream */</div><div class='ctx'> 	pbn_per_slot = get_pbn_per_slot(stream);</div><div class='hunk'>@@ -1769,8 +1714,7 @@ enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in</div><div class='ctx'> 	/* send ALLOCATE_PAYLOAD sideband message with updated pbn */</div><div class='ctx'> 	dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 			stream-&gt;ctx,</div><div class='del'>-			stream,</div><div class='del'>-			true);</div><div class='add'>+			stream);</div><div class='ctx'> </div><div class='ctx'> 	/* notify immediate branch device table update */</div><div class='ctx'> 	if (dm_helpers_dp_mst_write_payload_allocation_table(</div><div class='hunk'>@@ -1899,8 +1843,7 @@ enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_</div><div class='ctx'> 		/* send ALLOCATE_PAYLOAD sideband message with updated pbn */</div><div class='ctx'> 		dm_helpers_dp_mst_send_payload_allocation(</div><div class='ctx'> 				stream-&gt;ctx,</div><div class='del'>-				stream,</div><div class='del'>-				true);</div><div class='add'>+				stream);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* increase throttled vcp size */</div><div class='hunk'>@@ -2066,17 +2009,11 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * If the link is DP-over-USB4 do the following:</div><div class='del'>-	 * - Train with fallback when enabling DPIA link. Conventional links are</div><div class='add'>+	/* Train with fallback when enabling DPIA link. Conventional links are</div><div class='ctx'> 	 * trained with fallback during sink detection.</div><div class='del'>-	 * - Allocate only what the stream needs for bw in Gbps. Inform the CM</div><div class='del'>-	 * in case stream needs more or less bw from what has been allocated</div><div class='del'>-	 * earlier at plug time.</div><div class='ctx'> 	 */</div><div class='del'>-	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {</div><div class='add'>+	if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='ctx'> 		do_fallback = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Temporary w/a to get DP2.0 link rates to work with SST.</div><div class='hunk'>@@ -2142,8 +2079,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,</div><div class='ctx'> 	if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1 ||</div><div class='ctx'> 		link-&gt;dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||</div><div class='ctx'> 		link-&gt;dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {</div><div class='del'>-		set_cached_brightness_aux(link);</div><div class='del'>-</div><div class='add'>+		set_default_brightness_aux(link);</div><div class='ctx'> 		if (link-&gt;dpcd_sink_ext_caps.bits.oled == 1)</div><div class='ctx'> 			msleep(bl_oled_enable_delay);</div><div class='ctx'> 		edp_backlight_enable_aux(link, true);</div><div class='hunk'>@@ -2259,6 +2195,32 @@ static enum dc_status enable_link(</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool allocate_usb4_bandwidth(struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	int bw = dc_bandwidth_in_kbps_from_timing(&amp;stream-&gt;timing,</div><div class='add'>+			dc_link_get_highest_encoding_format(stream-&gt;sink-&gt;link));</div><div class='add'>+</div><div class='add'>+	ret = allocate_usb4_bandwidth_for_stream(stream, bw);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream)</div><div class='add'>+{</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	ret = allocate_usb4_bandwidth_for_stream(stream, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc  *dc = pipe_ctx-&gt;stream-&gt;ctx-&gt;dc;</div><div class='hunk'>@@ -2294,6 +2256,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> 	update_psp_stream_config(pipe_ctx, true);</div><div class='ctx'> 	dc-&gt;hwss.blank_stream(pipe_ctx);</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		deallocate_usb4_bandwidth(pipe_ctx-&gt;stream);</div><div class='add'>+</div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 		deallocate_mst_payload(pipe_ctx);</div><div class='ctx'> 	else if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT &amp;&amp;</div><div class='hunk'>@@ -2536,6 +2501,9 @@ void link_set_dpms_on(</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pipe_ctx-&gt;stream-&gt;link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+		allocate_usb4_bandwidth(pipe_ctx-&gt;stream);</div><div class='add'>+</div><div class='ctx'> 	if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT_MST)</div><div class='ctx'> 		allocate_mst_payload(pipe_ctx);</div><div class='ctx'> 	else if (pipe_ctx-&gt;stream-&gt;signal == SIGNAL_TYPE_DISPLAY_PORT &amp;&amp;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c<br/>index 7abfc67d10a6..37d3027c32dc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_factory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_factory.c</a></div><div class='hunk'>@@ -213,8 +213,10 @@ static void construct_link_service_edp_panel_control(struct link_service *link_s</div><div class='ctx'> 	link_srv-&gt;edp_get_replay_state = edp_get_replay_state;</div><div class='ctx'> 	link_srv-&gt;edp_set_replay_allow_active = edp_set_replay_allow_active;</div><div class='ctx'> 	link_srv-&gt;edp_setup_replay = edp_setup_replay;</div><div class='add'>+	link_srv-&gt;edp_send_replay_cmd = edp_send_replay_cmd;</div><div class='ctx'> 	link_srv-&gt;edp_set_coasting_vtotal = edp_set_coasting_vtotal;</div><div class='ctx'> 	link_srv-&gt;edp_replay_residency = edp_replay_residency;</div><div class='add'>+	link_srv-&gt;edp_set_replay_power_opt_and_coasting_vtotal = edp_set_replay_power_opt_and_coasting_vtotal;</div><div class='ctx'> </div><div class='ctx'> 	link_srv-&gt;edp_wait_for_t12 = edp_wait_for_t12;</div><div class='ctx'> 	link_srv-&gt;edp_is_ilr_optimization_required =</div><div class='hunk'>@@ -368,6 +370,30 @@ static enum transmitter translate_encoder_to_transmitter(</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	uint8_t pwrseq_inst = 0xF;</div><div class='add'>+	struct dc_context *dc_ctx = link-&gt;dc-&gt;ctx;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(dc_ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	switch (link-&gt;eng_id) {</div><div class='add'>+	case ENGINE_ID_DIGA:</div><div class='add'>+		pwrseq_inst = 0;</div><div class='add'>+		break;</div><div class='add'>+	case ENGINE_ID_DIGB:</div><div class='add'>+		pwrseq_inst = 1;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", link-&gt;eng_id);</div><div class='add'>+		ASSERT(false);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return pwrseq_inst;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='ctx'> static void link_destruct(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -595,24 +621,6 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	link-&gt;ddc_hw_inst =</div><div class='ctx'> 		dal_ddc_get_line(get_ddc_pin(link-&gt;ddc));</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-	if (link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;panel_cntl_create &amp;&amp;</div><div class='del'>-		(link-&gt;link_id.id == CONNECTOR_ID_EDP ||</div><div class='del'>-			link-&gt;link_id.id == CONNECTOR_ID_LVDS)) {</div><div class='del'>-		panel_cntl_init_data.ctx = dc_ctx;</div><div class='del'>-		panel_cntl_init_data.inst =</div><div class='del'>-			panel_cntl_init_data.ctx-&gt;dc_edp_id_count;</div><div class='del'>-		link-&gt;panel_cntl =</div><div class='del'>-			link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;panel_cntl_create(</div><div class='del'>-								&amp;panel_cntl_init_data);</div><div class='del'>-		panel_cntl_init_data.ctx-&gt;dc_edp_id_count++;</div><div class='del'>-</div><div class='del'>-		if (link-&gt;panel_cntl == NULL) {</div><div class='del'>-			DC_ERROR("Failed to create link panel_cntl!\n");</div><div class='del'>-			goto panel_cntl_create_fail;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	enc_init_data.ctx = dc_ctx;</div><div class='ctx'> 	bp_funcs-&gt;get_src_obj(dc_ctx-&gt;dc_bios, link-&gt;link_id, 0,</div><div class='ctx'> 			      &amp;enc_init_data.encoder);</div><div class='hunk'>@@ -643,6 +651,23 @@ static bool construct_phy(struct dc_link *link,</div><div class='ctx'> 	link-&gt;dc-&gt;res_pool-&gt;dig_link_enc_count++;</div><div class='ctx'> </div><div class='ctx'> 	link-&gt;link_enc_hw_inst = link-&gt;link_enc-&gt;transmitter;</div><div class='add'>+</div><div class='add'>+	if (link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;panel_cntl_create &amp;&amp;</div><div class='add'>+		(link-&gt;link_id.id == CONNECTOR_ID_EDP ||</div><div class='add'>+			link-&gt;link_id.id == CONNECTOR_ID_LVDS)) {</div><div class='add'>+		panel_cntl_init_data.ctx = dc_ctx;</div><div class='add'>+		panel_cntl_init_data.inst = panel_cntl_init_data.ctx-&gt;dc_edp_id_count;</div><div class='add'>+		panel_cntl_init_data.pwrseq_inst = translate_dig_inst_to_pwrseq_inst(link);</div><div class='add'>+		link-&gt;panel_cntl =</div><div class='add'>+			link-&gt;dc-&gt;res_pool-&gt;funcs-&gt;panel_cntl_create(</div><div class='add'>+								&amp;panel_cntl_init_data);</div><div class='add'>+		panel_cntl_init_data.ctx-&gt;dc_edp_id_count++;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;panel_cntl == NULL) {</div><div class='add'>+			DC_ERROR("Failed to create link panel_cntl!\n");</div><div class='add'>+			goto panel_cntl_create_fail;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='ctx'> 		if (bp_funcs-&gt;get_device_tag(dc_ctx-&gt;dc_bios,</div><div class='ctx'> 					     link-&gt;link_id, i,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c<br/>index b45fda96eaf6..8fe66c367850 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_validation.c</a></div><div class='hunk'>@@ -346,23 +346,61 @@ enum dc_status link_validate_mode_timing(</div><div class='ctx'> 	return DC_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * This function calculates the bandwidth required for the stream timing</div><div class='add'>+ * and aggregates the stream bandwidth for the respective dpia link</div><div class='add'>+ *</div><div class='add'>+ * @stream: pointer to the dc_stream_state struct instance</div><div class='add'>+ * @num_streams: number of streams to be validated</div><div class='add'>+ *</div><div class='add'>+ * return: true if validation is succeeded</div><div class='add'>+ */</div><div class='ctx'> bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)</div><div class='ctx'> {</div><div class='del'>-	bool ret = true;</div><div class='del'>-	int bw_needed[MAX_DPIA_NUM];</div><div class='del'>-	struct dc_link *link[MAX_DPIA_NUM];</div><div class='del'>-</div><div class='del'>-	if (!num_streams || num_streams &gt; MAX_DPIA_NUM)</div><div class='del'>-		return ret;</div><div class='add'>+	int bw_needed[MAX_DPIA_NUM] = {0};</div><div class='add'>+	struct dc_link *dpia_link[MAX_DPIA_NUM] = {0};</div><div class='add'>+	int num_dpias = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (uint8_t i = 0; i &lt; num_streams; ++i) {</div><div class='add'>+		if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT) {</div><div class='add'>+			/* new dpia sst stream, check whether it exceeds max dpia */</div><div class='add'>+			if (num_dpias &gt;= MAX_DPIA_NUM)</div><div class='add'>+				return false;</div><div class='ctx'> </div><div class='del'>-		link[i] = stream[i].link;</div><div class='del'>-		bw_needed[i] = dc_bandwidth_in_kbps_from_timing(&amp;stream[i].timing,</div><div class='del'>-				dc_link_get_highest_encoding_format(link[i]));</div><div class='add'>+			dpia_link[num_dpias] = stream[i].link;</div><div class='add'>+			bw_needed[num_dpias] = dc_bandwidth_in_kbps_from_timing(&amp;stream[i].timing,</div><div class='add'>+					dc_link_get_highest_encoding_format(dpia_link[num_dpias]));</div><div class='add'>+			num_dpias++;</div><div class='add'>+		} else if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {</div><div class='add'>+			uint8_t j = 0;</div><div class='add'>+			/* check whether its a known dpia link */</div><div class='add'>+			for (; j &lt; num_dpias; ++j) {</div><div class='add'>+				if (dpia_link[j] == stream[i].link)</div><div class='add'>+					break;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (j == num_dpias) {</div><div class='add'>+				/* new dpia mst stream, check whether it exceeds max dpia */</div><div class='add'>+				if (num_dpias &gt;= MAX_DPIA_NUM)</div><div class='add'>+					return false;</div><div class='add'>+				else {</div><div class='add'>+					dpia_link[j] = stream[i].link;</div><div class='add'>+					num_dpias++;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			bw_needed[j] += dc_bandwidth_in_kbps_from_timing(&amp;stream[i].timing,</div><div class='add'>+				dc_link_get_highest_encoding_format(dpia_link[j]));</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = dpia_validate_usb4_bw(link, bw_needed, num_streams);</div><div class='add'>+	/* Include dp overheads */</div><div class='add'>+	for (uint8_t i = 0; i &lt; num_dpias; ++i) {</div><div class='add'>+		int dp_overhead = 0;</div><div class='add'>+</div><div class='add'>+		dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(dpia_link[i]);</div><div class='add'>+		bw_needed[i] += dp_overhead;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return dpia_validate_usb4_bw(dpia_link, bw_needed, num_dpias);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.h b/drivers/gpu/drm/amd/display/dc/link/link_validation.h<br/>index 4a954317d0da..595fb05946e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/link_validation.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/link_validation.h</a></div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> #ifndef __LINK_VALIDATION_H__</div><div class='ctx'> #define __LINK_VALIDATION_H__</div><div class='ctx'> #include "link.h"</div><div class='add'>+</div><div class='ctx'> enum dc_status link_validate_mode_timing(</div><div class='ctx'> 		const struct dc_stream_state *stream,</div><div class='ctx'> 		struct dc_link *link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c<br/>index db87aa7b5c90..289f5d133342 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c</a></div><div class='hunk'>@@ -412,12 +412,18 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY &amp; DP_UHBR20)</div><div class='add'>+	if (link-&gt;dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY &amp; DP_UHBR20) {</div><div class='ctx'> 		cable_max_link_rate = LINK_RATE_UHBR20;</div><div class='del'>-	else if (link-&gt;dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)</div><div class='add'>+	} else if (link-&gt;dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {</div><div class='ctx'> 		cable_max_link_rate = LINK_RATE_UHBR13_5;</div><div class='del'>-	else if (link-&gt;dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY &amp; DP_UHBR10)</div><div class='del'>-		cable_max_link_rate = LINK_RATE_UHBR10;</div><div class='add'>+	} else if (link-&gt;dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY &amp; DP_UHBR10) {</div><div class='add'>+		// allow DP40 cables to do UHBR13.5 for passive or unknown cable type</div><div class='add'>+		if (link-&gt;dpcd_caps.cable_id.bits.CABLE_TYPE &lt; 2) {</div><div class='add'>+			cable_max_link_rate = LINK_RATE_UHBR13_5;</div><div class='add'>+		} else {</div><div class='add'>+			cable_max_link_rate = LINK_RATE_UHBR10;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return cable_max_link_rate;</div><div class='ctx'> }</div><div class='hunk'>@@ -1392,7 +1398,7 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)</div><div class='ctx'> 	cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);</div><div class='ctx'> 	cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(</div><div class='ctx'> 			link-&gt;dc, link-&gt;link_enc-&gt;transmitter);</div><div class='del'>-	if (dm_execute_dmub_cmd(link-&gt;dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='add'>+	if (dc_wake_and_execute_dmub_cmd(link-&gt;dc-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='ctx'> 			cmd.cable_id.header.ret_status == 1) {</div><div class='ctx'> 		cable_id-&gt;raw = cmd.cable_id.data.output_raw;</div><div class='ctx'> 		DC_LOG_DC("usbc_cable_id = %d.\n", cable_id-&gt;raw);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c<br/>index 0bb749133909..6af42ba9885c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c</a></div><div class='hunk'>@@ -82,24 +82,33 @@ bool dpia_query_hpd_status(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	union dmub_rb_cmd cmd = {0};</div><div class='ctx'> 	struct dc_dmub_srv *dmub_srv = link-&gt;ctx-&gt;dmub_srv;</div><div class='del'>-	bool is_hpd_high = false;</div><div class='ctx'> </div><div class='ctx'> 	/* prepare QUERY_HPD command */</div><div class='ctx'> 	cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE;</div><div class='ctx'> 	cmd.query_hpd.data.instance = link-&gt;link_id.enum_id - ENUM_ID_1;</div><div class='ctx'> 	cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA;</div><div class='ctx'> </div><div class='del'>-	/* Return HPD status reported by DMUB if query successfully executed. */</div><div class='del'>-	if (dm_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp; cmd.query_hpd.data.status == AUX_RET_SUCCESS)</div><div class='del'>-		is_hpd_high = cmd.query_hpd.data.result;</div><div class='del'>-</div><div class='del'>-	DC_LOG_DEBUG("%s: link(%d) dpia(%d) cmd_status(%d) result(%d)\n",</div><div class='del'>-		__func__,</div><div class='del'>-		link-&gt;link_index,</div><div class='del'>-		link-&gt;link_id.enum_id - ENUM_ID_1,</div><div class='del'>-		cmd.query_hpd.data.status,</div><div class='del'>-		cmd.query_hpd.data.result);</div><div class='del'>-</div><div class='del'>-	return is_hpd_high;</div><div class='add'>+	/* Query dpia hpd status from dmub */</div><div class='add'>+	if (dc_wake_and_execute_dmub_cmd(dmub_srv-&gt;ctx, &amp;cmd,</div><div class='add'>+		DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &amp;&amp;</div><div class='add'>+	    cmd.query_hpd.data.status == AUX_RET_SUCCESS) {</div><div class='add'>+		DC_LOG_DEBUG("%s: for link(%d) dpia(%d) success, current_hpd_status(%d) new_hpd_status(%d)\n",</div><div class='add'>+			__func__,</div><div class='add'>+			link-&gt;link_index,</div><div class='add'>+			link-&gt;link_id.enum_id - ENUM_ID_1,</div><div class='add'>+			link-&gt;hpd_status,</div><div class='add'>+			cmd.query_hpd.data.result);</div><div class='add'>+		link-&gt;hpd_status = cmd.query_hpd.data.result;</div><div class='add'>+	} else {</div><div class='add'>+		DC_LOG_ERROR("%s: for link(%d) dpia(%d) failed with status(%d), current_hpd_status(%d) new_hpd_status(0)\n",</div><div class='add'>+			__func__,</div><div class='add'>+			link-&gt;link_index,</div><div class='add'>+			link-&gt;link_id.enum_id - ENUM_ID_1,</div><div class='add'>+			cmd.query_hpd.data.status,</div><div class='add'>+			link-&gt;hpd_status);</div><div class='add'>+		link-&gt;hpd_status = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return link-&gt;hpd_status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c<br/>index 7581023daa47..dd0d2b206462 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c</a></div><div class='hunk'>@@ -50,15 +50,28 @@ static bool get_bw_alloc_proceed_flag(struct dc_link *tmp)</div><div class='ctx'> 			&amp;&amp; tmp-&gt;hpd_status</div><div class='ctx'> 			&amp;&amp; tmp-&gt;dpia_bw_alloc_config.bw_alloc_enabled);</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static void reset_bw_alloc_struct(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = false;</div><div class='del'>-	link-&gt;dpia_bw_alloc_config.sink_verified_bw = 0;</div><div class='del'>-	link-&gt;dpia_bw_alloc_config.sink_max_bw = 0;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.link_verified_bw = 0;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.link_max_bw = 0;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.allocated_bw = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.estimated_bw = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.bw_granularity = 0;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.dp_overhead = 0;</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.response_ready = false;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.nrd_max_lane_count = 0;</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.nrd_max_link_rate = 0;</div><div class='add'>+	for (int i = 0; i &lt; MAX_SINKS_PER_LINK; i++)</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.remote_sink_req_bw[i] = 0;</div><div class='add'>+	DC_LOG_DEBUG("reset usb4 bw alloc of link(%d)\n", link-&gt;link_index);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+#define BW_GRANULARITY_0 4 // 0.25 Gbps</div><div class='add'>+#define BW_GRANULARITY_1 2 // 0.5 Gbps</div><div class='add'>+#define BW_GRANULARITY_2 1 // 1 Gbps</div><div class='add'>+</div><div class='ctx'> static uint8_t get_bw_granularity(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t bw_granularity = 0;</div><div class='hunk'>@@ -71,16 +84,20 @@ static uint8_t get_bw_granularity(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	switch (bw_granularity &amp; 0x3) {</div><div class='ctx'> 	case 0:</div><div class='del'>-		bw_granularity = 4;</div><div class='add'>+		bw_granularity = BW_GRANULARITY_0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 1:</div><div class='add'>+		bw_granularity = BW_GRANULARITY_1;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='ctx'> 	default:</div><div class='del'>-		bw_granularity = 2;</div><div class='add'>+		bw_granularity = BW_GRANULARITY_2;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return bw_granularity;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static int get_estimated_bw(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t bw_estimated_bw = 0;</div><div class='hunk'>@@ -93,31 +110,33 @@ static int get_estimated_bw(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	return bw_estimated_bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='ctx'> }</div><div class='del'>-static bool allocate_usb4_bw(int *stream_allocated_bw, int bw_needed, struct dc_link *link)</div><div class='add'>+</div><div class='add'>+static int get_non_reduced_max_link_rate(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	if (bw_needed &gt; 0)</div><div class='del'>-		*stream_allocated_bw += bw_needed;</div><div class='add'>+	uint8_t nrd_max_link_rate = 0;</div><div class='ctx'> </div><div class='del'>-	return true;</div><div class='add'>+	core_link_read_dpcd(</div><div class='add'>+			link,</div><div class='add'>+			DP_TUNNELING_MAX_LINK_RATE,</div><div class='add'>+			&amp;nrd_max_link_rate,</div><div class='add'>+			sizeof(uint8_t));</div><div class='add'>+</div><div class='add'>+	return nrd_max_link_rate;</div><div class='ctx'> }</div><div class='del'>-static bool deallocate_usb4_bw(int *stream_allocated_bw, int bw_to_dealloc, struct dc_link *link)</div><div class='del'>-{</div><div class='del'>-	bool ret = false;</div><div class='ctx'> </div><div class='del'>-	if (*stream_allocated_bw &gt; 0) {</div><div class='del'>-		*stream_allocated_bw -= bw_to_dealloc;</div><div class='del'>-		ret = true;</div><div class='del'>-	} else {</div><div class='del'>-		//Do nothing for now</div><div class='del'>-		ret = true;</div><div class='del'>-	}</div><div class='add'>+static int get_non_reduced_max_lane_count(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	uint8_t nrd_max_lane_count = 0;</div><div class='ctx'> </div><div class='del'>-	// Unplug so reset values</div><div class='del'>-	if (!link-&gt;hpd_status)</div><div class='del'>-		reset_bw_alloc_struct(link);</div><div class='add'>+	core_link_read_dpcd(</div><div class='add'>+			link,</div><div class='add'>+			DP_TUNNELING_MAX_LANE_COUNT,</div><div class='add'>+			&amp;nrd_max_lane_count,</div><div class='add'>+			sizeof(uint8_t));</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return nrd_max_lane_count;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Read all New BW alloc configuration ex: estimated_bw, allocated_bw,</div><div class='ctx'>  * granuality, Driver_ID, CM_Group, &amp; populate the BW allocation structs</div><div class='hunk'>@@ -125,10 +144,22 @@ static bool deallocate_usb4_bw(int *stream_allocated_bw, int bw_to_dealloc, stru</div><div class='ctx'>  */</div><div class='ctx'> static void init_usb4_bw_struct(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	// Init the known values</div><div class='add'>+	reset_bw_alloc_struct(link);</div><div class='add'>+</div><div class='add'>+	/* init the known values */</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link);</div><div class='ctx'> 	link-&gt;dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.nrd_max_link_rate = get_non_reduced_max_link_rate(link);</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.nrd_max_lane_count = get_non_reduced_max_lane_count(link);</div><div class='add'>+</div><div class='add'>+	DC_LOG_DEBUG("%s: bw_granularity(%d), estimated_bw(%d)\n",</div><div class='add'>+		__func__, link-&gt;dpia_bw_alloc_config.bw_granularity,</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='add'>+	DC_LOG_DEBUG("%s: nrd_max_link_rate(%d), nrd_max_lane_count(%d)\n",</div><div class='add'>+		__func__, link-&gt;dpia_bw_alloc_config.nrd_max_link_rate,</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.nrd_max_lane_count);</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static uint8_t get_lowest_dpia_index(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	const struct dc *dc_struct = link-&gt;dc;</div><div class='hunk'>@@ -141,51 +172,66 @@ static uint8_t get_lowest_dpia_index(struct dc_link *link)</div><div class='ctx'> 				dc_struct-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (idx &gt; dc_struct-&gt;links[i]-&gt;link_index)</div><div class='add'>+		if (idx &gt; dc_struct-&gt;links[i]-&gt;link_index) {</div><div class='ctx'> 			idx = dc_struct-&gt;links[i]-&gt;link_index;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return idx;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /*</div><div class='del'>- * Get the Max Available BW or Max Estimated BW for each Host Router</div><div class='add'>+ * Get the maximum dp tunnel banwidth of host router</div><div class='ctx'>  *</div><div class='del'>- * @link: pointer to the dc_link struct instance</div><div class='del'>- * @type: ESTIMATD BW or MAX AVAILABLE BW</div><div class='add'>+ * @dc: pointer to the dc struct instance</div><div class='add'>+ * @hr_index: host router index</div><div class='ctx'>  *</div><div class='del'>- * return: response_ready flag from dc_link struct</div><div class='add'>+ * return: host router maximum dp tunnel bandwidth</div><div class='ctx'>  */</div><div class='del'>-static int get_host_router_total_bw(struct dc_link *link, uint8_t type)</div><div class='add'>+static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_index)</div><div class='ctx'> {</div><div class='del'>-	const struct dc *dc_struct = link-&gt;dc;</div><div class='del'>-	uint8_t lowest_dpia_index = get_lowest_dpia_index(link);</div><div class='del'>-	uint8_t idx = (link-&gt;link_index - lowest_dpia_index) / 2, idx_temp = 0;</div><div class='del'>-	struct dc_link *link_temp;</div><div class='add'>+	uint8_t lowest_dpia_index = get_lowest_dpia_index(dc-&gt;links[0]);</div><div class='add'>+	uint8_t hr_index_temp = 0;</div><div class='add'>+	struct dc_link *link_dpia_primary, *link_dpia_secondary;</div><div class='ctx'> 	int total_bw = 0;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_PIPES * 2; ++i) {</div><div class='ctx'> </div><div class='del'>-		if (!dc_struct-&gt;links[i] || dc_struct-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='del'>-			continue;</div><div class='add'>+	for (uint8_t i = 0; i &lt; MAX_PIPES * 2; ++i) {</div><div class='ctx'> </div><div class='del'>-		link_temp = dc_struct-&gt;links[i];</div><div class='del'>-		if (!link_temp || !link_temp-&gt;hpd_status)</div><div class='add'>+		if (!dc-&gt;links[i] || dc-&gt;links[i]-&gt;ep_type != DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		idx_temp = (link_temp-&gt;link_index - lowest_dpia_index) / 2;</div><div class='del'>-</div><div class='del'>-		if (idx_temp == idx) {</div><div class='del'>-</div><div class='del'>-			if (type == HOST_ROUTER_BW_ESTIMATED)</div><div class='del'>-				total_bw += link_temp-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='del'>-			else if (type == HOST_ROUTER_BW_ALLOCATED)</div><div class='del'>-				total_bw += link_temp-&gt;dpia_bw_alloc_config.sink_allocated_bw;</div><div class='add'>+		hr_index_temp = (dc-&gt;links[i]-&gt;link_index - lowest_dpia_index) / 2;</div><div class='add'>+</div><div class='add'>+		if (hr_index_temp == hr_index) {</div><div class='add'>+			link_dpia_primary = dc-&gt;links[i];</div><div class='add'>+			link_dpia_secondary = dc-&gt;links[i + 1];</div><div class='add'>+</div><div class='add'>+			/**</div><div class='add'>+			 * If BW allocation enabled on both DPIAs, then</div><div class='add'>+			 * HR BW = Estimated(dpia_primary) + Allocated(dpia_secondary)</div><div class='add'>+			 * otherwise HR BW = Estimated(bw alloc enabled dpia)</div><div class='add'>+			 */</div><div class='add'>+			if ((link_dpia_primary-&gt;hpd_status &amp;&amp;</div><div class='add'>+				link_dpia_primary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) &amp;&amp;</div><div class='add'>+				(link_dpia_secondary-&gt;hpd_status &amp;&amp;</div><div class='add'>+				link_dpia_secondary-&gt;dpia_bw_alloc_config.bw_alloc_enabled)) {</div><div class='add'>+					total_bw += link_dpia_primary-&gt;dpia_bw_alloc_config.estimated_bw +</div><div class='add'>+						link_dpia_secondary-&gt;dpia_bw_alloc_config.allocated_bw;</div><div class='add'>+			} else if (link_dpia_primary-&gt;hpd_status &amp;&amp;</div><div class='add'>+					link_dpia_primary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) {</div><div class='add'>+				total_bw = link_dpia_primary-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+			} else if (link_dpia_secondary-&gt;hpd_status &amp;&amp;</div><div class='add'>+				link_dpia_secondary-&gt;dpia_bw_alloc_config.bw_alloc_enabled) {</div><div class='add'>+				total_bw += link_dpia_secondary-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return total_bw;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Cleanup function for when the dpia is unplugged to reset struct</div><div class='ctx'>  * and perform any required clean up</div><div class='hunk'>@@ -194,42 +240,49 @@ static int get_host_router_total_bw(struct dc_link *link, uint8_t type)</div><div class='ctx'>  *</div><div class='ctx'>  * return: none</div><div class='ctx'>  */</div><div class='del'>-static bool dpia_bw_alloc_unplug(struct dc_link *link)</div><div class='add'>+static void dpia_bw_alloc_unplug(struct dc_link *link)</div><div class='ctx'> {</div><div class='del'>-	if (!link)</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	return deallocate_usb4_bw(&amp;link-&gt;dpia_bw_alloc_config.sink_allocated_bw,</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.sink_allocated_bw, link);</div><div class='add'>+	if (link) {</div><div class='add'>+		DC_LOG_DEBUG("%s: resetting bw alloc config for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='add'>+		reset_bw_alloc_struct(link);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> static void set_usb4_req_bw_req(struct dc_link *link, int req_bw)</div><div class='ctx'> {</div><div class='ctx'> 	uint8_t requested_bw;</div><div class='ctx'> 	uint32_t temp;</div><div class='ctx'> </div><div class='del'>-	// 1. Add check for this corner case #1</div><div class='del'>-	if (req_bw &gt; link-&gt;dpia_bw_alloc_config.estimated_bw)</div><div class='add'>+	/* Error check whether request bw greater than allocated */</div><div class='add'>+	if (req_bw &gt; link-&gt;dpia_bw_alloc_config.estimated_bw) {</div><div class='add'>+		DC_LOG_ERROR("%s: Request bw greater than estimated bw for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='ctx'> 		req_bw = link-&gt;dpia_bw_alloc_config.estimated_bw;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	temp = req_bw * link-&gt;dpia_bw_alloc_config.bw_granularity;</div><div class='ctx'> 	requested_bw = temp / Kbps_TO_Gbps;</div><div class='ctx'> </div><div class='del'>-	// Always make sure to add more to account for floating points</div><div class='add'>+	/* Always make sure to add more to account for floating points */</div><div class='ctx'> 	if (temp % Kbps_TO_Gbps)</div><div class='ctx'> 		++requested_bw;</div><div class='ctx'> </div><div class='del'>-	// 2. Add check for this corner case #2</div><div class='add'>+	/* Error check whether requested and allocated are equal */</div><div class='ctx'> 	req_bw = requested_bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-	if (req_bw == link-&gt;dpia_bw_alloc_config.sink_allocated_bw)</div><div class='del'>-		return;</div><div class='add'>+	if (req_bw == link-&gt;dpia_bw_alloc_config.allocated_bw) {</div><div class='add'>+		DC_LOG_ERROR("%s: Request bw equals to allocated bw for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (core_link_write_dpcd(</div><div class='add'>+	link-&gt;dpia_bw_alloc_config.response_ready = false; // Reset flag</div><div class='add'>+	core_link_write_dpcd(</div><div class='ctx'> 		link,</div><div class='ctx'> 		REQUESTED_BW,</div><div class='ctx'> 		&amp;requested_bw,</div><div class='del'>-		sizeof(uint8_t)) == DC_OK)</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.response_ready = false; // Reset flag</div><div class='add'>+		sizeof(uint8_t));</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Return the response_ready flag from dc_link struct</div><div class='ctx'>  *</div><div class='hunk'>@@ -241,6 +294,7 @@ static bool get_cm_response_ready_flag(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	return link-&gt;dpia_bw_alloc_config.response_ready;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> // ------------------------------------------------------------------</div><div class='ctx'> //					PUBLIC FUNCTIONS</div><div class='ctx'> // ------------------------------------------------------------------</div><div class='hunk'>@@ -277,27 +331,27 @@ bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link)</div><div class='ctx'> 				DPTX_BW_ALLOCATION_MODE_CONTROL,</div><div class='ctx'> 				&amp;response,</div><div class='ctx'> 				sizeof(uint8_t)) != DC_OK) {</div><div class='del'>-			DC_LOG_DEBUG("%s: **** FAILURE Enabling DPtx BW Allocation Mode Support ***\n",</div><div class='del'>-					__func__);</div><div class='add'>+			DC_LOG_DEBUG("%s: FAILURE Enabling DPtx BW Allocation Mode Support for link(%d)\n",</div><div class='add'>+				__func__, link-&gt;link_index);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			// SUCCESS Enabled DPtx BW Allocation Mode Support</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = true;</div><div class='del'>-			DC_LOG_DEBUG("%s: **** SUCCESS Enabling DPtx BW Allocation Mode Support ***\n",</div><div class='del'>-					__func__);</div><div class='add'>+			DC_LOG_DEBUG("%s: SUCCESS Enabling DPtx BW Allocation Mode Support for link(%d)\n",</div><div class='add'>+				__func__, link-&gt;link_index);</div><div class='ctx'> </div><div class='ctx'> 			ret = true;</div><div class='ctx'> 			init_usb4_bw_struct(link);</div><div class='add'>+			link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result)</div><div class='ctx'> {</div><div class='ctx'> 	int bw_needed = 0;</div><div class='ctx'> 	int estimated = 0;</div><div class='del'>-	int host_router_total_estimated_bw = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!get_bw_alloc_proceed_flag((link)))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -306,14 +360,22 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res</div><div class='ctx'> </div><div class='ctx'> 	case DPIA_BW_REQ_FAILED:</div><div class='ctx'> </div><div class='del'>-		DC_LOG_DEBUG("%s: *** *** BW REQ FAILURE for DP-TX Request *** ***\n", __func__);</div><div class='add'>+		/*</div><div class='add'>+		 * Ideally, we shouldn't run into this case as we always validate available</div><div class='add'>+		 * bandwidth and request within that limit</div><div class='add'>+		 */</div><div class='add'>+		estimated = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='add'>+</div><div class='add'>+		DC_LOG_ERROR("%s: BW REQ FAILURE for DP-TX Request for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='add'>+		DC_LOG_ERROR("%s: current estimated_bw(%d), new estimated_bw(%d)\n",</div><div class='add'>+			__func__, link-&gt;dpia_bw_alloc_config.estimated_bw, estimated);</div><div class='ctx'> </div><div class='del'>-		// Update the new Estimated BW value updated by CM</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.estimated_bw =</div><div class='del'>-				bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='add'>+		/* Update the new Estimated BW value updated by CM */</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='ctx'> </div><div class='add'>+		/* Allocate the previously requested bandwidth */</div><div class='ctx'> 		set_usb4_req_bw_req(link, link-&gt;dpia_bw_alloc_config.estimated_bw);</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.response_ready = false;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If FAIL then it is either:</div><div class='hunk'>@@ -326,68 +388,34 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res</div><div class='ctx'> </div><div class='ctx'> 	case DPIA_BW_REQ_SUCCESS:</div><div class='ctx'> </div><div class='del'>-		DC_LOG_DEBUG("%s: *** BW REQ SUCCESS for DP-TX Request ***\n", __func__);</div><div class='del'>-</div><div class='del'>-		// 1. SUCCESS 1st time before any Pruning is done</div><div class='del'>-		// 2. SUCCESS after prev. FAIL before any Pruning is done</div><div class='del'>-		// 3. SUCCESS after Pruning is done but before enabling link</div><div class='del'>-</div><div class='ctx'> 		bw_needed = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='ctx'> </div><div class='del'>-		// 1.</div><div class='del'>-		if (!link-&gt;dpia_bw_alloc_config.sink_allocated_bw) {</div><div class='del'>-</div><div class='del'>-			allocate_usb4_bw(&amp;link-&gt;dpia_bw_alloc_config.sink_allocated_bw, bw_needed, link);</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.sink_verified_bw =</div><div class='del'>-					link-&gt;dpia_bw_alloc_config.sink_allocated_bw;</div><div class='del'>-</div><div class='del'>-			// SUCCESS from first attempt</div><div class='del'>-			if (link-&gt;dpia_bw_alloc_config.sink_allocated_bw &gt;</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.sink_max_bw)</div><div class='del'>-				link-&gt;dpia_bw_alloc_config.sink_verified_bw =</div><div class='del'>-						link-&gt;dpia_bw_alloc_config.sink_max_bw;</div><div class='del'>-		}</div><div class='del'>-		// 3.</div><div class='del'>-		else if (link-&gt;dpia_bw_alloc_config.sink_allocated_bw) {</div><div class='del'>-</div><div class='del'>-			// Find out how much do we need to de-alloc</div><div class='del'>-			if (link-&gt;dpia_bw_alloc_config.sink_allocated_bw &gt; bw_needed)</div><div class='del'>-				deallocate_usb4_bw(&amp;link-&gt;dpia_bw_alloc_config.sink_allocated_bw,</div><div class='del'>-						link-&gt;dpia_bw_alloc_config.sink_allocated_bw - bw_needed, link);</div><div class='del'>-			else</div><div class='del'>-				allocate_usb4_bw(&amp;link-&gt;dpia_bw_alloc_config.sink_allocated_bw,</div><div class='del'>-						bw_needed - link-&gt;dpia_bw_alloc_config.sink_allocated_bw, link);</div><div class='del'>-		}</div><div class='add'>+		DC_LOG_DEBUG("%s: BW REQ SUCCESS for DP-TX Request for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='add'>+		DC_LOG_DEBUG("%s: current allocated_bw(%d), new allocated_bw(%d)\n",</div><div class='add'>+			__func__, link-&gt;dpia_bw_alloc_config.allocated_bw, bw_needed);</div><div class='ctx'> </div><div class='del'>-		// 4. If this is the 2nd sink then any unused bw will be reallocated to master DPIA</div><div class='del'>-		// =&gt; check if estimated_bw changed</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.allocated_bw = bw_needed;</div><div class='ctx'> </div><div class='ctx'> 		link-&gt;dpia_bw_alloc_config.response_ready = true;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case DPIA_EST_BW_CHANGED:</div><div class='ctx'> </div><div class='del'>-		DC_LOG_DEBUG("%s: *** ESTIMATED BW CHANGED for DP-TX Request ***\n", __func__);</div><div class='del'>-</div><div class='ctx'> 		estimated = bw * (Kbps_TO_Gbps / link-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='del'>-		host_router_total_estimated_bw = get_host_router_total_bw(link, HOST_ROUTER_BW_ESTIMATED);</div><div class='ctx'> </div><div class='del'>-		// 1. If due to unplug of other sink</div><div class='del'>-		if (estimated == host_router_total_estimated_bw) {</div><div class='del'>-			// First update the estimated &amp; max_bw fields</div><div class='del'>-			if (link-&gt;dpia_bw_alloc_config.estimated_bw &lt; estimated)</div><div class='del'>-				link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='del'>-		}</div><div class='del'>-		// 2. If due to realloc bw btw 2 dpia due to plug OR realloc unused Bw</div><div class='del'>-		else {</div><div class='del'>-			// We lost estimated bw usually due to plug event of other dpia</div><div class='del'>-			link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='del'>-		}</div><div class='add'>+		DC_LOG_DEBUG("%s: ESTIMATED BW CHANGED for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='add'>+		DC_LOG_DEBUG("%s: current estimated_bw(%d), new estimated_bw(%d)\n",</div><div class='add'>+			__func__, link-&gt;dpia_bw_alloc_config.estimated_bw, estimated);</div><div class='add'>+</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.estimated_bw = estimated;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case DPIA_BW_ALLOC_CAPS_CHANGED:</div><div class='ctx'> </div><div class='del'>-		DC_LOG_DEBUG("%s: *** BW ALLOC CAPABILITY CHANGED for DP-TX Request ***\n", __func__);</div><div class='add'>+		DC_LOG_ERROR("%s: BW ALLOC CAPABILITY CHANGED to Disabled for link(%d)\n",</div><div class='add'>+			__func__, link-&gt;link_index);</div><div class='ctx'> 		link-&gt;dpia_bw_alloc_config.bw_alloc_enabled = false;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -405,21 +433,21 @@ int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pea</div><div class='ctx'> 	if (link-&gt;hpd_status &amp;&amp; peak_bw &gt; 0) {</div><div class='ctx'> </div><div class='ctx'> 		// If DP over USB4 then we need to check BW allocation</div><div class='del'>-		link-&gt;dpia_bw_alloc_config.sink_max_bw = peak_bw;</div><div class='del'>-		set_usb4_req_bw_req(link, link-&gt;dpia_bw_alloc_config.sink_max_bw);</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.link_max_bw = peak_bw;</div><div class='add'>+		set_usb4_req_bw_req(link, link-&gt;dpia_bw_alloc_config.link_max_bw);</div><div class='ctx'> </div><div class='ctx'> 		do {</div><div class='del'>-			if (!(timeout &gt; 0))</div><div class='add'>+			if (timeout &gt; 0)</div><div class='ctx'> 				timeout--;</div><div class='ctx'> 			else</div><div class='ctx'> 				break;</div><div class='del'>-			fsleep(10 * 1000);</div><div class='add'>+			msleep(10);</div><div class='ctx'> 		} while (!get_cm_response_ready_flag(link));</div><div class='ctx'> </div><div class='ctx'> 		if (!timeout)</div><div class='ctx'> 			ret = 0;// ERROR TIMEOUT waiting for response for allocating bw</div><div class='del'>-		else if (link-&gt;dpia_bw_alloc_config.sink_allocated_bw &gt; 0)</div><div class='del'>-			ret = get_host_router_total_bw(link, HOST_ROUTER_BW_ALLOCATED);</div><div class='add'>+		else if (link-&gt;dpia_bw_alloc_config.allocated_bw &gt; 0)</div><div class='add'>+			ret = link-&gt;dpia_bw_alloc_config.allocated_bw;</div><div class='ctx'> 	}</div><div class='ctx'> 	//2. Cold Unplug</div><div class='ctx'> 	else if (!link-&gt;hpd_status)</div><div class='hunk'>@@ -428,65 +456,102 @@ int dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pea</div><div class='ctx'> out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='del'>-int link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)</div><div class='add'>+bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)</div><div class='ctx'> {</div><div class='del'>-	int ret = 0;</div><div class='add'>+	bool ret = false;</div><div class='ctx'> 	uint8_t timeout = 10;</div><div class='ctx'> </div><div class='add'>+	DC_LOG_DEBUG("%s: ENTER: link(%d), hpd_status(%d), current allocated_bw(%d), req_bw(%d)\n",</div><div class='add'>+		__func__, link-&gt;link_index, link-&gt;hpd_status,</div><div class='add'>+		link-&gt;dpia_bw_alloc_config.allocated_bw, req_bw);</div><div class='add'>+</div><div class='ctx'> 	if (!get_bw_alloc_proceed_flag(link))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Sometimes stream uses same timing parameters as the already</div><div class='del'>-	 * allocated max sink bw so no need to re-alloc</div><div class='del'>-	 */</div><div class='del'>-	if (req_bw != link-&gt;dpia_bw_alloc_config.sink_allocated_bw) {</div><div class='del'>-		set_usb4_req_bw_req(link, req_bw);</div><div class='del'>-		do {</div><div class='del'>-			if (!(timeout &gt; 0))</div><div class='del'>-				timeout--;</div><div class='del'>-			else</div><div class='del'>-				break;</div><div class='del'>-			udelay(10 * 1000);</div><div class='del'>-		} while (!get_cm_response_ready_flag(link));</div><div class='add'>+	set_usb4_req_bw_req(link, req_bw);</div><div class='add'>+	do {</div><div class='add'>+		if (timeout &gt; 0)</div><div class='add'>+			timeout--;</div><div class='add'>+		else</div><div class='add'>+			break;</div><div class='add'>+		msleep(10);</div><div class='add'>+	} while (!get_cm_response_ready_flag(link));</div><div class='ctx'> </div><div class='del'>-		if (!timeout)</div><div class='del'>-			ret = 0;// ERROR TIMEOUT waiting for response for allocating bw</div><div class='del'>-		else if (link-&gt;dpia_bw_alloc_config.sink_allocated_bw &gt; 0)</div><div class='del'>-			ret = get_host_router_total_bw(link, HOST_ROUTER_BW_ALLOCATED);</div><div class='del'>-	}</div><div class='add'>+	if (timeout)</div><div class='add'>+		ret = true;</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='add'>+	DC_LOG_DEBUG("%s: EXIT: timeout(%d), ret(%d)\n", __func__, timeout, ret);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const unsigned int num_dpias)</div><div class='ctx'> {</div><div class='ctx'> 	bool ret = true;</div><div class='del'>-	int bw_needed_per_hr[MAX_HR_NUM] = { 0, 0 };</div><div class='del'>-	uint8_t lowest_dpia_index = 0, dpia_index = 0;</div><div class='del'>-	uint8_t i;</div><div class='add'>+	int bw_needed_per_hr[MAX_HR_NUM] = { 0, 0 }, host_router_total_dp_bw = 0;</div><div class='add'>+	uint8_t lowest_dpia_index, i, hr_index;</div><div class='ctx'> </div><div class='ctx'> 	if (!num_dpias || num_dpias &gt; MAX_DPIA_NUM)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	//Get total Host Router BW &amp; Validate against each Host Router max BW</div><div class='add'>+	lowest_dpia_index = get_lowest_dpia_index(link[0]);</div><div class='add'>+</div><div class='add'>+	/* get total Host Router BW with granularity for the given modes */</div><div class='ctx'> 	for (i = 0; i &lt; num_dpias; ++i) {</div><div class='add'>+		int granularity_Gbps = 0;</div><div class='add'>+		int bw_granularity = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (!link[i]-&gt;dpia_bw_alloc_config.bw_alloc_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		lowest_dpia_index = get_lowest_dpia_index(link[i]);</div><div class='ctx'> 		if (link[i]-&gt;link_index &lt; lowest_dpia_index)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		dpia_index = (link[i]-&gt;link_index - lowest_dpia_index) / 2;</div><div class='del'>-		bw_needed_per_hr[dpia_index] += bw_needed_per_dpia[i];</div><div class='del'>-		if (bw_needed_per_hr[dpia_index] &gt; get_host_router_total_bw(link[i], HOST_ROUTER_BW_ALLOCATED)) {</div><div class='add'>+		granularity_Gbps = (Kbps_TO_Gbps / link[i]-&gt;dpia_bw_alloc_config.bw_granularity);</div><div class='add'>+		bw_granularity = (bw_needed_per_dpia[i] / granularity_Gbps) * granularity_Gbps +</div><div class='add'>+				((bw_needed_per_dpia[i] % granularity_Gbps) ? granularity_Gbps : 0);</div><div class='ctx'> </div><div class='del'>-			ret = false;</div><div class='del'>-			break;</div><div class='add'>+		hr_index = (link[i]-&gt;link_index - lowest_dpia_index) / 2;</div><div class='add'>+		bw_needed_per_hr[hr_index] += bw_granularity;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* validate against each Host Router max BW */</div><div class='add'>+	for (hr_index = 0; hr_index &lt; MAX_HR_NUM; ++hr_index) {</div><div class='add'>+		if (bw_needed_per_hr[hr_index]) {</div><div class='add'>+			host_router_total_dp_bw = get_host_router_total_dp_tunnel_bw(link[0]-&gt;dc, hr_index);</div><div class='add'>+			if (bw_needed_per_hr[hr_index] &gt; host_router_total_dp_bw) {</div><div class='add'>+				ret = false;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link)</div><div class='add'>+{</div><div class='add'>+	int dp_overhead = 0, link_mst_overhead = 0;</div><div class='add'>+</div><div class='add'>+	if (!get_bw_alloc_proceed_flag((link)))</div><div class='add'>+		return dp_overhead;</div><div class='add'>+</div><div class='add'>+	/* if its mst link, add MTPH overhead */</div><div class='add'>+	if ((link-&gt;type == dc_connection_mst_branch) &amp;&amp;</div><div class='add'>+		!link-&gt;dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {</div><div class='add'>+		/* For 8b/10b encoding: MTP is 64 time slots long, slot 0 is used for MTPH</div><div class='add'>+		 * MST overhead is 1/64 of link bandwidth (excluding any overhead)</div><div class='add'>+		 */</div><div class='add'>+		const struct dc_link_settings *link_cap =</div><div class='add'>+			dc_link_get_link_cap(link);</div><div class='add'>+		uint32_t link_bw_in_kbps = (uint32_t)link_cap-&gt;link_rate *</div><div class='add'>+					   (uint32_t)link_cap-&gt;lane_count *</div><div class='add'>+					   LINK_RATE_REF_FREQ_IN_KHZ * 8;</div><div class='add'>+		link_mst_overhead = (link_bw_in_kbps / 64) + ((link_bw_in_kbps % 64) ? 1 : 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* add all the overheads */</div><div class='add'>+	dp_overhead = link_mst_overhead;</div><div class='add'>+</div><div class='add'>+	return dp_overhead;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h<br/>index 7292690383ae..3b6d8494f9d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h</a></div><div class='hunk'>@@ -59,9 +59,9 @@ bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link);</div><div class='ctx'>  * @link: pointer to the dc_link struct instance</div><div class='ctx'>  * @req_bw: Bw requested by the stream</div><div class='ctx'>  *</div><div class='del'>- * return: allocated bw else return 0</div><div class='add'>+ * return: true if allocated successfully</div><div class='ctx'>  */</div><div class='del'>-int link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw);</div><div class='add'>+bool link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Handle the USB4 BW Allocation related functionality here:</div><div class='hunk'>@@ -99,4 +99,13 @@ void dpia_handle_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t res</div><div class='ctx'>  */</div><div class='ctx'> bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, const unsigned int num_dpias);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Obtain all the DP overheads in dp tunneling for the dpia link</div><div class='add'>+ *</div><div class='add'>+ * @link: pointer to the dc_link struct instance</div><div class='add'>+ *</div><div class='add'>+ * return: DP overheads in DP tunneling</div><div class='add'>+ */</div><div class='add'>+int link_dp_dpia_get_dp_overhead_in_dp_tunneling(struct dc_link *link);</div><div class='add'>+</div><div class='ctx'> #endif /* DC_INC_LINK_DP_DPIA_BW_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c<br/>index 0c00e94e90b1..ba69874be5a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c</a></div><div class='hunk'>@@ -190,9 +190,6 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)</div><div class='ctx'> 	/*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/</div><div class='ctx'> 	union psr_error_status replay_error_status;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;replay_settings.config.force_disable_desync_error_check)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (!link-&gt;replay_settings.replay_feature_enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -210,9 +207,6 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)</div><div class='ctx'> 		&amp;replay_error_status.raw,</div><div class='ctx'> 		sizeof(replay_error_status.raw));</div><div class='ctx'> </div><div class='del'>-	if (replay_configuration.bits.DESYNC_ERROR_STATUS)</div><div class='del'>-		link-&gt;replay_settings.config.received_desync_error_hpd = 1;</div><div class='del'>-</div><div class='ctx'> 	link-&gt;replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR =</div><div class='ctx'> 		replay_error_status.bits.LINK_CRC_ERROR;</div><div class='ctx'> 	link-&gt;replay_settings.config.replay_error_status.bits.DESYNC_ERROR =</div><div class='hunk'>@@ -225,6 +219,12 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)</div><div class='ctx'> 		link-&gt;replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR) {</div><div class='ctx'> 		bool allow_active;</div><div class='ctx'> </div><div class='add'>+		if (link-&gt;replay_settings.config.replay_error_status.bits.DESYNC_ERROR)</div><div class='add'>+			link-&gt;replay_settings.config.received_desync_error_hpd = 1;</div><div class='add'>+</div><div class='add'>+		if (link-&gt;replay_settings.config.force_disable_desync_error_check)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='ctx'> 		/* Acknowledge and clear configuration bits */</div><div class='ctx'> 		dm_helpers_dp_write_dpcd(</div><div class='ctx'> 			link-&gt;ctx,</div><div class='hunk'>@@ -265,7 +265,7 @@ void dp_handle_link_loss(struct dc_link *link)</div><div class='ctx'> </div><div class='ctx'> 	for (i = count - 1; i &gt;= 0; i--) {</div><div class='ctx'> 		// Always use max settings here for DP 1.4a LL Compliance CTS</div><div class='del'>-		if (link-&gt;is_automated) {</div><div class='add'>+		if (link-&gt;skip_fallback_on_link_loss) {</div><div class='ctx'> 			pipes[i]-&gt;link_config.dp_link_settings.lane_count =</div><div class='ctx'> 					link-&gt;verified_link_cap.lane_count;</div><div class='ctx'> 			pipes[i]-&gt;link_config.dp_link_settings.link_rate =</div><div class='hunk'>@@ -404,7 +404,9 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,</div><div class='ctx'> </div><div class='ctx'> 	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {</div><div class='ctx'> 		// Workaround for DP 1.4a LL Compliance CTS as USB4 has to share encoders unlike DP and USBC</div><div class='del'>-		link-&gt;is_automated = true;</div><div class='add'>+		if (link-&gt;ep_type == DISPLAY_ENDPOINT_USB4_DPIA)</div><div class='add'>+			link-&gt;skip_fallback_on_link_loss = true;</div><div class='add'>+</div><div class='ctx'> 		device_service_clear.bits.AUTOMATED_TEST = 1;</div><div class='ctx'> 		core_link_write_dpcd(</div><div class='ctx'> 			link,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c<br/>index 90339c2dfd84..5a0b04518956 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c</a></div><div class='hunk'>@@ -807,7 +807,7 @@ void dp_decide_lane_settings(</div><div class='ctx'> 		const struct link_training_settings *lt_settings,</div><div class='ctx'> 		const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],</div><div class='ctx'> 		struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],</div><div class='del'>-		union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])</div><div class='add'>+		union dpcd_training_lane *dpcd_lane_settings)</div><div class='ctx'> {</div><div class='ctx'> 	uint32_t lane;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h<br/>index 7d027bac8255..851bd17317a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h</a></div><div class='hunk'>@@ -111,7 +111,7 @@ void dp_decide_lane_settings(</div><div class='ctx'> 	const struct link_training_settings *lt_settings,</div><div class='ctx'> 	const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],</div><div class='ctx'> 	struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],</div><div class='del'>-	union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);</div><div class='add'>+	union dpcd_training_lane *dpcd_lane_settings);</div><div class='ctx'> </div><div class='ctx'> enum dc_dp_training_pattern decide_cr_training_pattern(</div><div class='ctx'> 		const struct dc_link_settings *link_settings);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c<br/>index 4f4e899e5c46..e8dda44b23cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c</a></div><div class='hunk'>@@ -811,7 +811,7 @@ static enum link_training_result dpia_training_eq_transparent(</div><div class='ctx'> 			/* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4</div><div class='ctx'> 			 * has to share encoders unlike DP and USBC</div><div class='ctx'> 			 */</div><div class='del'>-			if (dp_is_interlane_aligned(dpcd_lane_status_updated) || (link-&gt;is_automated &amp;&amp; retries_eq)) {</div><div class='add'>+			if (dp_is_interlane_aligned(dpcd_lane_status_updated) || (link-&gt;skip_fallback_on_link_loss &amp;&amp; retries_eq)) {</div><div class='ctx'> 				result =  LINK_TRAINING_SUCCESS;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1037,7 +1037,7 @@ enum link_training_result dpia_perform_link_training(</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (result == LINK_TRAINING_SUCCESS) {</div><div class='ctx'> 		fsleep(5000);</div><div class='del'>-		if (!link-&gt;is_automated)</div><div class='add'>+		if (!link-&gt;skip_fallback_on_link_loss)</div><div class='ctx'> 			result = dp_check_link_loss_status(link, &amp;lt_settings);</div><div class='ctx'> 	} else if (result == LINK_TRAINING_ABORT)</div><div class='ctx'> 		dpia_training_abort(link, &amp;lt_settings, repeater_id);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c<br/>index fd8f6f198146..7087cdc9e977 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c</a></div><div class='hunk'>@@ -115,7 +115,7 @@ static enum link_training_result perform_fixed_vs_pe_nontransparent_training_seq</div><div class='ctx'> 		lt_settings-&gt;cr_pattern_time = 16000;</div><div class='ctx'> </div><div class='ctx'> 	/* Fixed VS/PE specific: Toggle link rate */</div><div class='del'>-	apply_toggle_rate_wa = (link-&gt;vendor_specific_lttpr_link_rate_wa == target_rate);</div><div class='add'>+	apply_toggle_rate_wa = ((link-&gt;vendor_specific_lttpr_link_rate_wa == target_rate) || (link-&gt;vendor_specific_lttpr_link_rate_wa == 0));</div><div class='ctx'> 	target_rate = get_dpcd_link_rate(&amp;lt_settings-&gt;link_settings);</div><div class='ctx'> 	toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;</div><div class='ctx'> </div><div class='hunk'>@@ -205,6 +205,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};</div><div class='add'>+	const uint8_t vendor_lttpr_write_data_dpmf[4] = {0x1, 0x6, 0x70, 0x87};</div><div class='ctx'> 	enum link_training_result status = LINK_TRAINING_SUCCESS;</div><div class='ctx'> 	uint8_t lane = 0;</div><div class='ctx'> 	union down_spread_ctrl downspread = {0};</div><div class='hunk'>@@ -271,7 +272,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(</div><div class='ctx'> 	/* Vendor specific: Toggle link rate */</div><div class='ctx'> 	toggle_rate = (rate == 0x6) ? 0xA : 0x6;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;vendor_specific_lttpr_link_rate_wa == rate) {</div><div class='add'>+	if (link-&gt;vendor_specific_lttpr_link_rate_wa == rate || link-&gt;vendor_specific_lttpr_link_rate_wa == 0) {</div><div class='ctx'> 		core_link_write_dpcd(</div><div class='ctx'> 				link,</div><div class='ctx'> 				DP_LINK_BW_SET,</div><div class='hunk'>@@ -293,6 +294,10 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(</div><div class='ctx'> 		DP_DOWNSPREAD_CTRL,</div><div class='ctx'> 		lt_settings-&gt;link_settings.link_spread);</div><div class='ctx'> </div><div class='add'>+	link_configure_fixed_vs_pe_retimer(link-&gt;ddc,</div><div class='add'>+			&amp;vendor_lttpr_write_data_dpmf[0],</div><div class='add'>+			sizeof(vendor_lttpr_write_data_dpmf));</div><div class='add'>+</div><div class='ctx'> 	if (lt_settings-&gt;link_settings.lane_count == LANE_COUNT_FOUR) {</div><div class='ctx'> 		link_configure_fixed_vs_pe_retimer(link-&gt;ddc,</div><div class='ctx'> 				&amp;vendor_lttpr_write_data_4lane_1[0], sizeof(vendor_lttpr_write_data_4lane_1));</div><div class='hunk'>@@ -552,6 +557,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};</div><div class='ctx'> 	const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};</div><div class='add'>+	const uint8_t vendor_lttpr_write_data_dpmf[4] = {0x1, 0x6, 0x70, 0x87};</div><div class='ctx'> 	enum link_training_result status = LINK_TRAINING_SUCCESS;</div><div class='ctx'> 	uint8_t lane = 0;</div><div class='ctx'> 	union down_spread_ctrl downspread = {0};</div><div class='hunk'>@@ -617,7 +623,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(</div><div class='ctx'> 	/* Vendor specific: Toggle link rate */</div><div class='ctx'> 	toggle_rate = (rate == 0x6) ? 0xA : 0x6;</div><div class='ctx'> </div><div class='del'>-	if (link-&gt;vendor_specific_lttpr_link_rate_wa == rate) {</div><div class='add'>+	if (link-&gt;vendor_specific_lttpr_link_rate_wa == rate || link-&gt;vendor_specific_lttpr_link_rate_wa == 0) {</div><div class='ctx'> 		core_link_write_dpcd(</div><div class='ctx'> 				link,</div><div class='ctx'> 				DP_LINK_BW_SET,</div><div class='hunk'>@@ -639,6 +645,10 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(</div><div class='ctx'> 		DP_DOWNSPREAD_CTRL,</div><div class='ctx'> 		lt_settings-&gt;link_settings.link_spread);</div><div class='ctx'> </div><div class='add'>+	link_configure_fixed_vs_pe_retimer(link-&gt;ddc,</div><div class='add'>+			&amp;vendor_lttpr_write_data_dpmf[0],</div><div class='add'>+			sizeof(vendor_lttpr_write_data_dpmf));</div><div class='add'>+</div><div class='ctx'> 	if (lt_settings-&gt;link_settings.lane_count == LANE_COUNT_FOUR) {</div><div class='ctx'> 		link_configure_fixed_vs_pe_retimer(link-&gt;ddc,</div><div class='ctx'> 				&amp;vendor_lttpr_write_data_4lane_1[0], sizeof(vendor_lttpr_write_data_4lane_1));</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c<br/>index e32a7974a4bc..046d3e205415 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c</a></div><div class='hunk'>@@ -170,7 +170,6 @@ bool edp_set_backlight_level_nits(struct dc_link *link,</div><div class='ctx'> 	*(uint32_t *)&amp;dpcd_backlight_set.backlight_level_millinits = backlight_millinits;</div><div class='ctx'> 	*(uint16_t *)&amp;dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;</div><div class='ctx'> </div><div class='del'>-	link-&gt;backlight_settings.backlight_millinits = backlight_millinits;</div><div class='ctx'> </div><div class='ctx'> 	if (!link-&gt;dpcd_caps.panel_luminance_control) {</div><div class='ctx'> 		if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,</div><div class='hunk'>@@ -290,7 +289,7 @@ bool set_default_brightness_aux(struct dc_link *link)</div><div class='ctx'> 			default_backlight = 150000;</div><div class='ctx'> 		// if &lt; 1 nits or &gt; 5000, it might be wrong readback</div><div class='ctx'> 		if (default_backlight &lt; 1000 || default_backlight &gt; 5000000)</div><div class='del'>-			default_backlight = 150000; //</div><div class='add'>+			default_backlight = 150000;</div><div class='ctx'> </div><div class='ctx'> 		return edp_set_backlight_level_nits(link, true,</div><div class='ctx'> 				default_backlight, 0);</div><div class='hunk'>@@ -298,15 +297,6 @@ bool set_default_brightness_aux(struct dc_link *link)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool set_cached_brightness_aux(struct dc_link *link)</div><div class='del'>-{</div><div class='del'>-	if (link-&gt;backlight_settings.backlight_millinits)</div><div class='del'>-		return edp_set_backlight_level_nits(link, true,</div><div class='del'>-						    link-&gt;backlight_settings.backlight_millinits, 0);</div><div class='del'>-	else</div><div class='del'>-		return set_default_brightness_aux(link);</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='ctx'> bool edp_is_ilr_optimization_enabled(struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	if (link-&gt;dpcd_caps.edp_supported_link_rates_count == 0 || !link-&gt;panel_config.ilr.optimize_edp_link_rate)</div><div class='hunk'>@@ -539,6 +529,9 @@ bool edp_set_backlight_level(const struct dc_link *link,</div><div class='ctx'> 	if (dc_is_embedded_signal(link-&gt;connector_signal)) {</div><div class='ctx'> 		struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);</div><div class='ctx'> </div><div class='add'>+		if (link-&gt;panel_cntl)</div><div class='add'>+			link-&gt;panel_cntl-&gt;stored_backlight_registers.USER_LEVEL = backlight_pwm_u16_16;</div><div class='add'>+</div><div class='ctx'> 		if (pipe_ctx) {</div><div class='ctx'> 			/* Disable brightness ramping when the display is blanked</div><div class='ctx'> 			 * as it can hang the DMCU</div><div class='hunk'>@@ -937,8 +930,8 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)</div><div class='ctx'> bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)</div><div class='ctx'> {</div><div class='ctx'> 	/* To-do: Setup Replay */</div><div class='del'>-	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='del'>-	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='add'>+	struct dc *dc;</div><div class='add'>+	struct dmub_replay *replay;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	unsigned int panel_inst;</div><div class='ctx'> 	struct replay_context replay_context = { 0 };</div><div class='hunk'>@@ -954,6 +947,10 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 	if (!link)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='add'>+	dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+</div><div class='add'>+	replay = dc-&gt;res_pool-&gt;replay;</div><div class='add'>+</div><div class='ctx'> 	if (!replay)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -982,8 +979,7 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> </div><div class='ctx'> 	replay_context.line_time_in_ns = lineTimeInNs;</div><div class='ctx'> </div><div class='del'>-	if (replay)</div><div class='del'>-		link-&gt;replay_settings.replay_feature_enabled =</div><div class='add'>+	link-&gt;replay_settings.replay_feature_enabled =</div><div class='ctx'> 			replay-&gt;funcs-&gt;replay_copy_settings(replay, link, &amp;replay_context, panel_inst);</div><div class='ctx'> 	if (link-&gt;replay_settings.replay_feature_enabled) {</div><div class='ctx'> </div><div class='hunk'>@@ -1007,6 +1003,36 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * This is general Interface for Replay to set an 32 bit variable to dmub</div><div class='add'>+ * replay_FW_Message_type: Indicates which instruction or variable pass to DMUB</div><div class='add'>+ * cmd_data: Value of the config.</div><div class='add'>+ */</div><div class='add'>+bool edp_send_replay_cmd(struct dc_link *link,</div><div class='add'>+			enum replay_FW_Message_type msg,</div><div class='add'>+			union dmub_replay_cmd_set *cmd_data)</div><div class='add'>+{</div><div class='add'>+	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='add'>+	unsigned int panel_inst;</div><div class='add'>+</div><div class='add'>+	if (!replay)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	DC_LOGGER_INIT(link-&gt;ctx-&gt;logger);</div><div class='add'>+</div><div class='add'>+	if (dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='add'>+		cmd_data-&gt;panel_inst = panel_inst;</div><div class='add'>+	else {</div><div class='add'>+		DC_LOG_DC("%s(): get edp panel inst fail ", __func__);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	replay-&gt;funcs-&gt;replay_send_cmd(replay, msg, cmd_data);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)</div><div class='ctx'> {</div><div class='ctx'> 	struct dc *dc = link-&gt;ctx-&gt;dc;</div><div class='hunk'>@@ -1045,6 +1071,33 @@ bool edp_replay_residency(const struct dc_link *link,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	const unsigned int *power_opts, uint16_t coasting_vtotal)</div><div class='add'>+{</div><div class='add'>+	struct dc  *dc = link-&gt;ctx-&gt;dc;</div><div class='add'>+	struct dmub_replay *replay = dc-&gt;res_pool-&gt;replay;</div><div class='add'>+	unsigned int panel_inst;</div><div class='add'>+</div><div class='add'>+	if (!dc_get_edp_link_panel_inst(dc, link, &amp;panel_inst))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Only both power and coasting vtotal changed, this func could return true */</div><div class='add'>+	if (power_opts &amp;&amp; link-&gt;replay_settings.replay_power_opt_active != *power_opts &amp;&amp;</div><div class='add'>+		coasting_vtotal &amp;&amp; link-&gt;replay_settings.coasting_vtotal != coasting_vtotal) {</div><div class='add'>+		if (link-&gt;replay_settings.replay_feature_enabled &amp;&amp;</div><div class='add'>+			replay-&gt;funcs-&gt;replay_set_power_opt_and_coasting_vtotal) {</div><div class='add'>+			replay-&gt;funcs-&gt;replay_set_power_opt_and_coasting_vtotal(replay,</div><div class='add'>+				*power_opts, panel_inst, coasting_vtotal);</div><div class='add'>+			link-&gt;replay_settings.replay_power_opt_active = *power_opts;</div><div class='add'>+			link-&gt;replay_settings.coasting_vtotal = coasting_vtotal;</div><div class='add'>+		} else</div><div class='add'>+			return false;</div><div class='add'>+	} else</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct abm *get_abm_from_stream_res(const struct dc_link *link)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h<br/>index ebf7deb63d13..34e521af7bb4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h</a></div><div class='hunk'>@@ -30,7 +30,6 @@</div><div class='ctx'> enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);</div><div class='ctx'> void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);</div><div class='ctx'> bool set_default_brightness_aux(struct dc_link *link);</div><div class='del'>-bool set_cached_brightness_aux(struct dc_link *link);</div><div class='ctx'> void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);</div><div class='ctx'> int edp_get_backlight_level(const struct dc_link *link);</div><div class='ctx'> bool edp_get_backlight_level_nits(struct dc_link *link,</div><div class='hunk'>@@ -57,10 +56,15 @@ bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,</div><div class='ctx'> 	bool wait, bool force_static, const unsigned int *power_opts);</div><div class='ctx'> bool edp_setup_replay(struct dc_link *link,</div><div class='ctx'> 		const struct dc_stream_state *stream);</div><div class='add'>+bool edp_send_replay_cmd(struct dc_link *link,</div><div class='add'>+			enum replay_FW_Message_type msg,</div><div class='add'>+			union dmub_replay_cmd_set *cmd_data);</div><div class='ctx'> bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal);</div><div class='ctx'> bool edp_replay_residency(const struct dc_link *link,</div><div class='ctx'> 	unsigned int *residency, const bool is_start, const bool is_alpm);</div><div class='ctx'> bool edp_get_replay_state(const struct dc_link *link, uint64_t *state);</div><div class='add'>+bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	const unsigned int *power_opts, uint16_t coasting_vtotal);</div><div class='ctx'> bool edp_wait_for_t12(struct dc_link *link);</div><div class='ctx'> bool edp_is_ilr_optimization_required(struct dc_link *link,</div><div class='ctx'>        struct dc_crtc_timing *crtc_timing);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile<br/>new file mode 100644<br/>index 000000000000..bb213335fb9f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/Makefile</a></div><div class='hunk'>@@ -0,0 +1,108 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'optc' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN10 = dcn10_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN10 = $(addprefix $(AMDDALPATH)/dc/optc/dcn10/,$(OPTC_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN20 = dcn20_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN20 = $(addprefix $(AMDDALPATH)/dc/optc/dcn20/,$(OPTC_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN201 = dcn201_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN201 = $(addprefix $(AMDDALPATH)/dc/optc/dcn201/,$(OPTC_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN30 = dcn30_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN30 = $(addprefix $(AMDDALPATH)/dc/optc/dcn30/,$(OPTC_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN301 = dcn301_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN301 = $(addprefix $(AMDDALPATH)/dc/optc/dcn301/,$(OPTC_DCN301))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN301)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN31 = dcn31_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN31 = $(addprefix $(AMDDALPATH)/dc/optc/dcn31/,$(OPTC_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN314 = dcn314_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN314 = $(addprefix $(AMDDALPATH)/dc/optc/dcn314/,$(OPTC_DCN314))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN314)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN32 = dcn32_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN32 = $(addprefix $(AMDDALPATH)/dc/optc/dcn32/,$(OPTC_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+OPTC_DCN35 = dcn35_optc.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_OPTC_DCN35 = $(addprefix $(AMDDALPATH)/dc/optc/dcn35/,$(OPTC_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c<br/>index 0e8f4f36c87c..0e8f4f36c87c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h<br/>index ab81594a7fad..ab81594a7fad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c<br/>index 58bdbd859bf9..58bdbd859bf9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h<br/>index f7968b9ca16e..c2e03ced392e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #ifndef __DC_OPTC_DCN20_H__</div><div class='ctx'> #define __DC_OPTC_DCN20_H__</div><div class='ctx'> </div><div class='del'>-#include "../dcn10/dcn10_optc.h"</div><div class='add'>+#include "dcn10/dcn10_optc.h"</div><div class='ctx'> </div><div class='ctx'> #define TG_COMMON_REG_LIST_DCN2_0(inst) \</div><div class='ctx'> 	TG_COMMON_REG_LIST_DCN(inst),\</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c<br/>index 70fcbec03fb6..70fcbec03fb6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h<br/>index e9545b73513a..e9545b73513a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c<br/>index b97bdb868a0e..b97bdb868a0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h<br/>index d3a056c12b0d..d3a056c12b0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c<br/>index b3cfcb887905..b3cfcb887905 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h<br/>index b49585682a15..b49585682a15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c<br/>index 63a677c8ee27..63a677c8ee27 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h<br/>index 30b81a448ce2..30b81a448ce2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c<br/>index 0086cafb0f7a..0086cafb0f7a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h<br/>index 99c098e76116..99c098e76116 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c<br/>index a2c4db2cebdd..823493543325 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c</a></div><div class='hunk'>@@ -166,6 +166,16 @@ static bool optc32_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> </div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OPTC_MEMORY_CONFIG,</div><div class='add'>+			OPTC_MEM_SEL, 0);</div><div class='add'>+</div><div class='ctx'> 	/* disable otg request until end of the first line</div><div class='ctx'> 	 * in the vertical blank region</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -198,6 +208,13 @@ static void optc32_disable_phantom_otg(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> </div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='ctx'> 	REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h<br/>index 8ce3b178cab0..8ce3b178cab0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c<br/>index a4a39f1638cf..5b1547508850 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c</a></div><div class='hunk'>@@ -138,6 +138,16 @@ static bool optc35_disable_crtc(struct timing_generator *optc)</div><div class='ctx'> {</div><div class='ctx'> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);</div><div class='ctx'> </div><div class='add'>+	REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,</div><div class='add'>+			OPTC_SEG0_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG1_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG2_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_SEG3_SRC_SEL, 0xf,</div><div class='add'>+			OPTC_NUM_OF_INPUT_SEGMENT, 0);</div><div class='add'>+</div><div class='add'>+	REG_UPDATE(OPTC_MEMORY_CONFIG,</div><div class='add'>+			OPTC_MEM_SEL, 0);</div><div class='add'>+</div><div class='ctx'> 	/* disable otg request until end of the first line</div><div class='ctx'> 	 * in the vertical blank region</div><div class='ctx'> 	 */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h<br/>index 1f422e4c468f..1f422e4c468f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile b/drivers/gpu/drm/amd/display/dc/resource/Makefile<br/>new file mode 100644<br/>index 000000000000..0a75ed8962a5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/Makefile</a></div><div class='hunk'>@@ -0,0 +1,199 @@</div><div class='add'>+</div><div class='add'>+# Copyright 2022 Advanced Micro Devices, Inc.</div><div class='add'>+#</div><div class='add'>+# Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+# copy of this software and associated documentation files (the "Software"),</div><div class='add'>+# to deal in the Software without restriction, including without limitation</div><div class='add'>+# the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+# and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+# Software is furnished to do so, subject to the following conditions:</div><div class='add'>+#</div><div class='add'>+# The above copyright notice and this permission notice shall be included in</div><div class='add'>+# all copies or substantial portions of the Software.</div><div class='add'>+#</div><div class='add'>+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+# OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+#</div><div class='add'>+# Makefile for the 'resource' sub-component of DAL.</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+#  DCE</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE100 = dce100_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE100 = $(addprefix $(AMDDALPATH)/dc/resource/dce100/,$(RESOURCE_DCE100))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE100)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE110 = dce110_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE110 = $(addprefix $(AMDDALPATH)/dc/resource/dce110/,$(RESOURCE_DCE110))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE110)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE112 = dce112_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE112 = $(addprefix $(AMDDALPATH)/dc/resource/dce112/,$(RESOURCE_DCE112))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE112)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE120 = dce120_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE120 = $(addprefix $(AMDDALPATH)/dc/resource/dce120/,$(RESOURCE_DCE120))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE120)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCE80 = dce80_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCE80 = $(addprefix $(AMDDALPATH)/dc/resource/dce80/,$(RESOURCE_DCE80))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCE80)</div><div class='add'>+</div><div class='add'>+ifdef CONFIG_DRM_AMD_DC_FP</div><div class='add'>+###############################################################################</div><div class='add'>+# DCN</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN10 = dcn10_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN10 = $(addprefix $(AMDDALPATH)/dc/resource/dcn10/,$(RESOURCE_DCN10))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN10)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN20 = dcn20_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN20 = $(addprefix $(AMDDALPATH)/dc/resource/dcn20/,$(RESOURCE_DCN20))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN20)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN201 = dcn201_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN201 = $(addprefix $(AMDDALPATH)/dc/resource/dcn201/,$(RESOURCE_DCN201))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN201)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN21 = dcn21_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN21 = $(addprefix $(AMDDALPATH)/dc/resource/dcn21/,$(RESOURCE_DCN21))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN21)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN30 = dcn30_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN30 = $(addprefix $(AMDDALPATH)/dc/resource/dcn30/,$(RESOURCE_DCN30))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN30)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN301 = dcn301_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN301 = $(addprefix $(AMDDALPATH)/dc/resource/dcn301/,$(RESOURCE_DCN301))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN301)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN302 = dcn302_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN302 = $(addprefix $(AMDDALPATH)/dc/resource/dcn302/,$(RESOURCE_DCN302))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN302)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN303 = dcn303_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN303 = $(addprefix $(AMDDALPATH)/dc/resource/dcn303/,$(RESOURCE_DCN303))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN303)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN31 = dcn31_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN31 = $(addprefix $(AMDDALPATH)/dc/resource/dcn31/,$(RESOURCE_DCN31))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN31)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN314 = dcn314_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN314 = $(addprefix $(AMDDALPATH)/dc/resource/dcn314/,$(RESOURCE_DCN314))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN314)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN315 = dcn315_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN315 = $(addprefix $(AMDDALPATH)/dc/resource/dcn315/,$(RESOURCE_DCN315))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN315)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN316 = dcn316_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN316 = $(addprefix $(AMDDALPATH)/dc/resource/dcn316/,$(RESOURCE_DCN316))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN316)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN32 = dcn32_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN32 = $(addprefix $(AMDDALPATH)/dc/resource/dcn32/,$(RESOURCE_DCN32))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN32)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN321 = dcn321_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN321 = $(addprefix $(AMDDALPATH)/dc/resource/dcn321/,$(RESOURCE_DCN321))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN321)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+RESOURCE_DCN35 = dcn35_resource.o</div><div class='add'>+</div><div class='add'>+AMD_DAL_RESOURCE_DCN35 = $(addprefix $(AMDDALPATH)/dc/resource/dcn35/,$(RESOURCE_DCN35))</div><div class='add'>+</div><div class='add'>+AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN35)</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+###############################################################################</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c<br/>index 53a5f4cb648c..53a5f4cb648c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h<br/>index fecab7c560f5..fecab7c560f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c<br/>index fe518fd27b08..fe518fd27b08 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h<br/>index aa4531e0800e..aa4531e0800e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c<br/>index d1edac46c9a0..d1edac46c9a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h<br/>index 1f57ebc6f9b4..1f57ebc6f9b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c<br/>index 962de79be169..20662edd0ae4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c</a></div><div class='hunk'>@@ -36,7 +36,7 @@</div><div class='ctx'> </div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='ctx'> #include "virtual/virtual_stream_encoder.h"</div><div class='del'>-#include "dce120_timing_generator.h"</div><div class='add'>+#include "dce120/dce120_timing_generator.h"</div><div class='ctx'> #include "irq/dce120/irq_service_dce120.h"</div><div class='ctx'> #include "dce/dce_opp.h"</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h<br/>index 3d1f3cf012f4..3d1f3cf012f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt b/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt<br/>new file mode 100644<br/>index 000000000000..19dd73bc9ab0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/CMakeLists.txt</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+dal3_subdirectory_sources(</div><div class='add'>+  dce80_resource.c</div><div class='add'>+  dce80_resource.h</div><div class='add'>+  )
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c<br/>index 35a2cce0c2b8..35a2cce0c2b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h<br/>index eff31ab83a39..eff31ab83a39 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c<br/>index b94c5c97eee7..d08d10969251 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c</a></div><div class='hunk'>@@ -26,29 +26,32 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn10_init.h"</div><div class='add'>+#include "dcn10/dcn10_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='del'>-#include "dcn10_resource.h"</div><div class='del'>-#include "dcn10_ipp.h"</div><div class='del'>-#include "dcn10_mpc.h"</div><div class='add'>+#include "dcn10/dcn10_resource.h"</div><div class='add'>+#include "dcn10/dcn10_ipp.h"</div><div class='add'>+#include "dcn10/dcn10_mpc.h"</div><div class='add'>+</div><div class='add'>+#include "dcn10/dcn10_dwb.h"</div><div class='add'>+</div><div class='ctx'> #include "irq/dcn10/irq_service_dcn10.h"</div><div class='del'>-#include "dcn10_dpp.h"</div><div class='del'>-#include "dcn10_optc.h"</div><div class='add'>+#include "dcn10/dcn10_dpp.h"</div><div class='add'>+#include "dcn10/dcn10_optc.h"</div><div class='ctx'> #include "dcn10/dcn10_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_hwseq.h"</div><div class='del'>-#include "dcn10_opp.h"</div><div class='del'>-#include "dcn10_link_encoder.h"</div><div class='del'>-#include "dcn10_stream_encoder.h"</div><div class='add'>+#include "dcn10/dcn10_opp.h"</div><div class='add'>+#include "dcn10/dcn10_link_encoder.h"</div><div class='add'>+#include "dcn10/dcn10_stream_encoder.h"</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> #include "virtual/virtual_stream_encoder.h"</div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='ctx'> #include "dce112/dce112_resource.h"</div><div class='del'>-#include "dcn10_hubp.h"</div><div class='del'>-#include "dcn10_hubbub.h"</div><div class='add'>+#include "dcn10/dcn10_hubp.h"</div><div class='add'>+#include "dcn10/dcn10_hubbub.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "soc15_hw_ip.h"</div><div class='hunk'>@@ -1247,7 +1250,10 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(</div><div class='ctx'> 			/* Store first available for MST second display</div><div class='ctx'> 			 * in daisy chain use case</div><div class='ctx'> 			 */</div><div class='del'>-			j = i;</div><div class='add'>+</div><div class='add'>+			if (pool-&gt;stream_enc[i]-&gt;id != ENGINE_ID_VIRTUAL)</div><div class='add'>+				j = i;</div><div class='add'>+</div><div class='ctx'> 			if (link-&gt;ep_type == DISPLAY_ENDPOINT_PHY &amp;&amp; pool-&gt;stream_enc[i]-&gt;id ==</div><div class='ctx'> 					link-&gt;link_enc-&gt;preferred_engine)</div><div class='ctx'> 				return pool-&gt;stream_enc[i];</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h<br/>index bf8e33cd8147..bf8e33cd8147 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c<br/>index 0a422fbb14bc..f9c5bc624be3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c</a></div><div class='hunk'>@@ -29,7 +29,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn20_init.h"</div><div class='add'>+#include "dcn20/dcn20_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -39,29 +39,29 @@</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_hubp.h"</div><div class='ctx'> #include "dcn10/dcn10_ipp.h"</div><div class='del'>-#include "dcn20_hubbub.h"</div><div class='del'>-#include "dcn20_mpc.h"</div><div class='del'>-#include "dcn20_hubp.h"</div><div class='add'>+#include "dcn20/dcn20_hubbub.h"</div><div class='add'>+#include "dcn20/dcn20_mpc.h"</div><div class='add'>+#include "dcn20/dcn20_hubp.h"</div><div class='ctx'> #include "irq/dcn20/irq_service_dcn20.h"</div><div class='del'>-#include "dcn20_dpp.h"</div><div class='del'>-#include "dcn20_optc.h"</div><div class='add'>+#include "dcn20/dcn20_dpp.h"</div><div class='add'>+#include "dcn20/dcn20_optc.h"</div><div class='ctx'> #include "dcn20/dcn20_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_hwseq.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='del'>-#include "dcn20_opp.h"</div><div class='add'>+#include "dcn20/dcn20_opp.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn20_dsc.h"</div><div class='add'>+#include "dcn20/dcn20_dsc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn20_link_encoder.h"</div><div class='del'>-#include "dcn20_stream_encoder.h"</div><div class='add'>+#include "dcn20/dcn20_link_encoder.h"</div><div class='add'>+#include "dcn20/dcn20_stream_encoder.h"</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='ctx'> #include "virtual/virtual_stream_encoder.h"</div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='ctx'> #include "dml/display_mode_vba.h"</div><div class='del'>-#include "dcn20_dccg.h"</div><div class='del'>-#include "dcn20_vmid.h"</div><div class='add'>+#include "dcn20/dcn20_dccg.h"</div><div class='add'>+#include "dcn20/dcn20_vmid.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "navi10_ip_offset.h"</div><div class='hunk'>@@ -1273,15 +1273,19 @@ static void build_clamping_params(struct dc_stream_state *stream)</div><div class='ctx'> 	stream-&gt;clamping.pixel_encoding = stream-&gt;timing.pixel_encoding;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)</div><div class='add'>+void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)</div><div class='ctx'> {</div><div class='del'>-</div><div class='ctx'> 	get_pixel_clock_parameters(pipe_ctx, &amp;pipe_ctx-&gt;stream_res.pix_clk_params);</div><div class='del'>-</div><div class='ctx'> 	pipe_ctx-&gt;clock_source-&gt;funcs-&gt;get_pix_clk_dividers(</div><div class='del'>-		pipe_ctx-&gt;clock_source,</div><div class='del'>-		&amp;pipe_ctx-&gt;stream_res.pix_clk_params,</div><div class='del'>-		&amp;pipe_ctx-&gt;pll_settings);</div><div class='add'>+			pipe_ctx-&gt;clock_source,</div><div class='add'>+			&amp;pipe_ctx-&gt;stream_res.pix_clk_params,</div><div class='add'>+			&amp;pipe_ctx-&gt;pll_settings);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	dcn20_build_pipe_pix_clk_params(pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> 	pipe_ctx-&gt;stream-&gt;clamping.pixel_encoding = pipe_ctx-&gt;stream-&gt;timing.pixel_encoding;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h<br/>index 37ecaccc5d12..4cee3fa11a7f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h</a></div><div class='hunk'>@@ -165,6 +165,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,</div><div class='ctx'> enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);</div><div class='ctx'> enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);</div><div class='ctx'> enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);</div><div class='add'>+void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx);</div><div class='ctx'> </div><div class='ctx'> #endif /* __DC_RESOURCE_DCN20_H__ */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c<br/>index bca22d867696..914b234d7f6b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn201_init.h"</div><div class='add'>+#include "dcn201/dcn201_init.h"</div><div class='ctx'> #include "dml/dcn20/dcn20_fpu.h"</div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -36,16 +36,16 @@</div><div class='ctx'> </div><div class='ctx'> #include "dcn10/dcn10_hubp.h"</div><div class='ctx'> #include "dcn10/dcn10_ipp.h"</div><div class='del'>-#include "dcn201_mpc.h"</div><div class='del'>-#include "dcn201_hubp.h"</div><div class='add'>+#include "dcn201/dcn201_mpc.h"</div><div class='add'>+#include "dcn201/dcn201_hubp.h"</div><div class='ctx'> #include "irq/dcn201/irq_service_dcn201.h"</div><div class='ctx'> #include "dcn201/dcn201_dpp.h"</div><div class='ctx'> #include "dcn201/dcn201_hubbub.h"</div><div class='del'>-#include "dcn201_dccg.h"</div><div class='del'>-#include "dcn201_optc.h"</div><div class='add'>+#include "dcn201/dcn201_dccg.h"</div><div class='add'>+#include "dcn201/dcn201_optc.h"</div><div class='ctx'> #include "dcn201/dcn201_hwseq.h"</div><div class='ctx'> #include "dce110/dce110_hwseq.h"</div><div class='del'>-#include "dcn201_opp.h"</div><div class='add'>+#include "dcn201/dcn201_opp.h"</div><div class='ctx'> #include "dcn201/dcn201_link_encoder.h"</div><div class='ctx'> #include "dcn20/dcn20_stream_encoder.h"</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='hunk'>@@ -55,7 +55,7 @@</div><div class='ctx'> #include "dce110/dce110_resource.h"</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='del'>-#include "dcn201_hubbub.h"</div><div class='add'>+#include "dcn201/dcn201_hubbub.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> </div><div class='ctx'> #include "cyan_skillfish_ip_offset.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h<br/>index e0467d17d4ae..e0467d17d4ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c<br/>index 42277b280586..65d337731f56 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c</a></div><div class='hunk'>@@ -29,7 +29,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn21_init.h"</div><div class='add'>+#include "dcn21/dcn21_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -44,7 +44,7 @@</div><div class='ctx'> #include "dcn20/dcn20_hubbub.h"</div><div class='ctx'> #include "dcn20/dcn20_mpc.h"</div><div class='ctx'> #include "dcn20/dcn20_hubp.h"</div><div class='del'>-#include "dcn21_hubp.h"</div><div class='add'>+#include "dcn21/dcn21_hubp.h"</div><div class='ctx'> #include "irq/dcn21/irq_service_dcn21.h"</div><div class='ctx'> #include "dcn20/dcn20_dpp.h"</div><div class='ctx'> #include "dcn20/dcn20_optc.h"</div><div class='hunk'>@@ -61,7 +61,7 @@</div><div class='ctx'> #include "dml/display_mode_vba.h"</div><div class='ctx'> #include "dcn20/dcn20_dccg.h"</div><div class='ctx'> #include "dcn21/dcn21_dccg.h"</div><div class='del'>-#include "dcn21_hubbub.h"</div><div class='add'>+#include "dcn21/dcn21_hubbub.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> #include "dce/dce_panel_cntl.h"</div><div class='ctx'> </div><div class='hunk'>@@ -713,9 +713,8 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)</div><div class='ctx'> 			pool-&gt;base.hubps[i] = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (pool-&gt;base.irqs != NULL) {</div><div class='add'>+		if (pool-&gt;base.irqs != NULL)</div><div class='ctx'> 			dal_irq_service_destroy(&amp;pool-&gt;base.irqs);</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_ddc; i++) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h<br/>index f7ecc002c2f7..f7ecc002c2f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c<br/>index 7b259cb5f418..37a64186f324 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn30_init.h"</div><div class='add'>+#include "dcn30/dcn30_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -1682,6 +1682,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 		 * We don't actually support prefetch mode 2, so require that we</div><div class='ctx'> 		 * at least support prefetch mode 1.</div><div class='ctx'> 		 */</div><div class='add'>+		context-&gt;bw_ctx.dml.validate_max_state = fast_validate;</div><div class='ctx'> 		context-&gt;bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =</div><div class='ctx'> 			dm_allow_self_refresh;</div><div class='ctx'> </div><div class='hunk'>@@ -1691,6 +1692,7 @@ noinline bool dcn30_internal_validate_bw(</div><div class='ctx'> 			memset(merge, 0, sizeof(merge));</div><div class='ctx'> 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);</div><div class='ctx'> 		}</div><div class='add'>+		context-&gt;bw_ctx.dml.validate_max_state = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dml_log_mode_support_params(&amp;context-&gt;bw_ctx.dml);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h<br/>index 8e6b8b7368fd..8e6b8b7368fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c<br/>index f3b75f283aa2..511ff6b5b985 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn301_init.h"</div><div class='add'>+#include "dcn301/dcn301_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -61,7 +61,7 @@</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> #include "dcn30/dcn30_dio_stream_encoder.h"</div><div class='ctx'> #include "dcn301/dcn301_dio_link_encoder.h"</div><div class='del'>-#include "dcn301_panel_cntl.h"</div><div class='add'>+#include "dcn301/dcn301_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "vangogh_ip_offset.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h<br/>index ae8672680cdd..ae8672680cdd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c<br/>index 63ac984a04f7..5791b5cc2875 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c</a></div><div class='hunk'>@@ -23,9 +23,9 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "dcn302_init.h"</div><div class='add'>+#include "dcn302/dcn302_init.h"</div><div class='ctx'> #include "dcn302_resource.h"</div><div class='del'>-#include "dcn302_dccg.h"</div><div class='add'>+#include "dcn302/dcn302_dccg.h"</div><div class='ctx'> #include "irq/dcn302/irq_service_dcn302.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dio_link_encoder.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h<br/>index 9f24e73b92b3..9f24e73b92b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c<br/>index 49cb7fde416a..25cd6236b054 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c</a></div><div class='hunk'>@@ -23,9 +23,9 @@</div><div class='ctx'>  * Authors: AMD</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include "dcn303_init.h"</div><div class='add'>+#include "dcn303/dcn303_init.h"</div><div class='ctx'> #include "dcn303_resource.h"</div><div class='del'>-#include "dcn303_dccg.h"</div><div class='add'>+#include "dcn303/dcn303_dccg.h"</div><div class='ctx'> #include "irq/dcn303/irq_service_dcn303.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dio_link_encoder.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h<br/>index 37cf1525820b..37cf1525820b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c<br/>index 79416cfb22f0..31035fc3d868 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c</a></div><div class='hunk'>@@ -70,7 +70,7 @@</div><div class='ctx'> #include "dml/dcn31/dcn31_fpu.h"</div><div class='ctx'> #include "dcn31/dcn31_dccg.h"</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='del'>-#include "dcn31_panel_cntl.h"</div><div class='add'>+#include "dcn31/dcn31_panel_cntl.h"</div><div class='ctx'> </div><div class='ctx'> #include "dcn30/dcn30_dwb.h"</div><div class='ctx'> #include "dcn30/dcn30_mmhubbub.h"</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h<br/>index 901436591ed4..901436591ed4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c<br/>index 677361d74a4e..c97391edb5ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c</a></div><div class='hunk'>@@ -871,7 +871,7 @@ static const struct dc_plane_cap plane_cap = {</div><div class='ctx'> static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_z10 = false,</div><div class='ctx'> 	.enable_z9_disable_interface = true,</div><div class='del'>-	.minimum_z8_residency_time = 2000,</div><div class='add'>+	.minimum_z8_residency_time = 2100,</div><div class='ctx'> 	.psr_skip_crtc_disable = true,</div><div class='ctx'> 	.replay_skip_crtc_disabled = true,</div><div class='ctx'> 	.disable_dmcu = true,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h<br/>index 49ffe71018df..49ffe71018df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c<br/>index cb8024eee8e4..515ba435f759 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c</a></div><div class='hunk'>@@ -1631,8 +1631,10 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct resource_context *res_ctx = &amp;context-&gt;res_ctx;</div><div class='ctx'> </div><div class='del'>-	/*Don't apply for single stream*/</div><div class='del'>-	if (context-&gt;stream_count &lt; 2)</div><div class='add'>+	/* Only apply for dual stream scenarios with edp*/</div><div class='add'>+	if (context-&gt;stream_count != 2)</div><div class='add'>+		return false;</div><div class='add'>+	if (context-&gt;streams[0]-&gt;signal != SIGNAL_TYPE_EDP &amp;&amp; context-&gt;streams[1]-&gt;signal != SIGNAL_TYPE_EDP)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h<br/>index 22849eaa6f24..22849eaa6f24 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c<br/>index b9753d4606f8..b9753d4606f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h<br/>index aba6d634131b..aba6d634131b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c<br/>index 89b072447dba..c4d71e7f18af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> #include "dm_services.h"</div><div class='ctx'> #include "dc.h"</div><div class='ctx'> </div><div class='del'>-#include "dcn32_init.h"</div><div class='add'>+#include "dcn32/dcn32_init.h"</div><div class='ctx'> </div><div class='ctx'> #include "resource.h"</div><div class='ctx'> #include "include/irq_service_interface.h"</div><div class='hunk'>@@ -41,7 +41,7 @@</div><div class='ctx'> #include "dcn31/dcn31_hubbub.h"</div><div class='ctx'> #include "dcn32/dcn32_hubbub.h"</div><div class='ctx'> #include "dcn32/dcn32_mpc.h"</div><div class='del'>-#include "dcn32_hubp.h"</div><div class='add'>+#include "dcn32/dcn32_hubp.h"</div><div class='ctx'> #include "irq/dcn32/irq_service_dcn32.h"</div><div class='ctx'> #include "dcn32/dcn32_dpp.h"</div><div class='ctx'> #include "dcn32/dcn32_optc.h"</div><div class='hunk'>@@ -89,6 +89,8 @@</div><div class='ctx'> #include "dcn20/dcn20_vmid.h"</div><div class='ctx'> #include "dml/dcn32/dcn32_fpu.h"</div><div class='ctx'> </div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+</div><div class='ctx'> #include "dml2/dml2_wrapper.h"</div><div class='ctx'> </div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='hunk'>@@ -1644,7 +1646,7 @@ static void dcn32_enable_phantom_plane(struct dc *dc,</div><div class='ctx'> 		if (curr_pipe-&gt;top_pipe &amp;&amp; curr_pipe-&gt;top_pipe-&gt;plane_state == curr_pipe-&gt;plane_state)</div><div class='ctx'> 			phantom_plane = prev_phantom_plane;</div><div class='ctx'> 		else</div><div class='del'>-			phantom_plane = dc_create_plane_state(dc);</div><div class='add'>+			phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe-&gt;plane_state);</div><div class='ctx'> </div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;address, &amp;curr_pipe-&gt;plane_state-&gt;address, sizeof(phantom_plane-&gt;address));</div><div class='ctx'> 		memcpy(&amp;phantom_plane-&gt;scaling_quality, &amp;curr_pipe-&gt;plane_state-&gt;scaling_quality,</div><div class='hunk'>@@ -1665,9 +1667,7 @@ static void dcn32_enable_phantom_plane(struct dc *dc,</div><div class='ctx'> 		phantom_plane-&gt;clip_rect.y = 0;</div><div class='ctx'> 		phantom_plane-&gt;clip_rect.height = phantom_stream-&gt;src.height;</div><div class='ctx'> </div><div class='del'>-		phantom_plane-&gt;is_phantom = true;</div><div class='del'>-</div><div class='del'>-		dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);</div><div class='add'>+		dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);</div><div class='ctx'> </div><div class='ctx'> 		curr_pipe = curr_pipe-&gt;bottom_pipe;</div><div class='ctx'> 		prev_phantom_plane = phantom_plane;</div><div class='hunk'>@@ -1683,13 +1683,7 @@ static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,</div><div class='ctx'> 	struct dc_stream_state *phantom_stream = NULL;</div><div class='ctx'> 	struct pipe_ctx *ref_pipe = &amp;context-&gt;res_ctx.pipe_ctx[dc_pipe_idx];</div><div class='ctx'> </div><div class='del'>-	phantom_stream = dc_create_stream_for_sink(ref_pipe-&gt;stream-&gt;sink);</div><div class='del'>-	phantom_stream-&gt;signal = SIGNAL_TYPE_VIRTUAL;</div><div class='del'>-	phantom_stream-&gt;dpms_off = true;</div><div class='del'>-	phantom_stream-&gt;mall_stream_config.type = SUBVP_PHANTOM;</div><div class='del'>-	phantom_stream-&gt;mall_stream_config.paired_stream = ref_pipe-&gt;stream;</div><div class='del'>-	ref_pipe-&gt;stream-&gt;mall_stream_config.type = SUBVP_MAIN;</div><div class='del'>-	ref_pipe-&gt;stream-&gt;mall_stream_config.paired_stream = phantom_stream;</div><div class='add'>+	phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe-&gt;stream);</div><div class='ctx'> </div><div class='ctx'> 	/* stream has limited viewport and small timing */</div><div class='ctx'> 	memcpy(&amp;phantom_stream-&gt;timing, &amp;ref_pipe-&gt;stream-&gt;timing, sizeof(phantom_stream-&gt;timing));</div><div class='hunk'>@@ -1699,81 +1693,10 @@ static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,</div><div class='ctx'> 	dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	dc_add_stream_to_ctx(dc, context, phantom_stream);</div><div class='add'>+	dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe-&gt;stream);</div><div class='ctx'> 	return phantom_stream;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct dc_plane_state *phantom_plane = NULL;</div><div class='del'>-	struct dc_stream_state *phantom_stream = NULL;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-</div><div class='del'>-		if (resource_is_pipe_type(pipe, OTG_MASTER) &amp;&amp;</div><div class='del'>-				resource_is_pipe_type(pipe, DPP_PIPE) &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='del'>-			phantom_plane = pipe-&gt;plane_state;</div><div class='del'>-			phantom_stream = pipe-&gt;stream;</div><div class='del'>-</div><div class='del'>-			dc_plane_state_retain(phantom_plane);</div><div class='del'>-			dc_stream_retain(phantom_stream);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-// return true if removed piped from ctx, false otherwise</div><div class='del'>-bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context, bool fast_update)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	bool removed_pipe = false;</div><div class='del'>-	struct dc_plane_state *phantom_plane = NULL;</div><div class='del'>-	struct dc_stream_state *phantom_stream = NULL;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dc-&gt;res_pool-&gt;pipe_count; i++) {</div><div class='del'>-		struct pipe_ctx *pipe = &amp;context-&gt;res_ctx.pipe_ctx[i];</div><div class='del'>-		// build scaling params for phantom pipes</div><div class='del'>-		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='del'>-			phantom_plane = pipe-&gt;plane_state;</div><div class='del'>-			phantom_stream = pipe-&gt;stream;</div><div class='del'>-</div><div class='del'>-			dc_rem_all_planes_for_stream(dc, pipe-&gt;stream, context);</div><div class='del'>-			dc_remove_stream_from_ctx(dc, context, pipe-&gt;stream);</div><div class='del'>-</div><div class='del'>-			/* Ref count is incremented on allocation and also when added to the context.</div><div class='del'>-			 * Therefore we must call release for the the phantom plane and stream once</div><div class='del'>-			 * they are removed from the ctx to finally decrement the refcount to 0 to free.</div><div class='del'>-			 */</div><div class='del'>-			dc_plane_state_release(phantom_plane);</div><div class='del'>-			dc_stream_release(phantom_stream);</div><div class='del'>-</div><div class='del'>-			removed_pipe = true;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* For non-full updates, a shallow copy of the current state</div><div class='del'>-		 * is created. In this case we don't want to erase the current</div><div class='del'>-		 * state (there can be 2 HIRQL threads, one in flip, and one in</div><div class='del'>-		 * checkMPO) that can cause a race condition.</div><div class='del'>-		 *</div><div class='del'>-		 * This is just a workaround, needs a proper fix.</div><div class='del'>-		 */</div><div class='del'>-		if (!fast_update) {</div><div class='del'>-			// Clear all phantom stream info</div><div class='del'>-			if (pipe-&gt;stream) {</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type = SUBVP_NONE;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.paired_stream = NULL;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (pipe-&gt;plane_state) {</div><div class='del'>-				pipe-&gt;plane_state-&gt;is_phantom = false;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return removed_pipe;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* TODO: Input to this function should indicate which pipe indexes (or streams)</div><div class='ctx'>  * require a phantom pipe / stream</div><div class='ctx'>  */</div><div class='hunk'>@@ -1798,7 +1721,7 @@ void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 		// We determine which phantom pipes were added by comparing with</div><div class='ctx'> 		// the phantom stream.</div><div class='ctx'> 		if (pipe-&gt;plane_state &amp;&amp; pipe-&gt;stream &amp;&amp; pipe-&gt;stream == phantom_stream &amp;&amp;</div><div class='del'>-				pipe-&gt;stream-&gt;mall_stream_config.type == SUBVP_PHANTOM) {</div><div class='add'>+				dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {</div><div class='ctx'> 			pipe-&gt;stream-&gt;use_dynamic_meta = false;</div><div class='ctx'> 			pipe-&gt;plane_state-&gt;flip_immediate = false;</div><div class='ctx'> 			if (!resource_build_scaling_params(pipe)) {</div><div class='hunk'>@@ -1817,7 +1740,6 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_val</div><div class='ctx'> 	int vlevel = 0;</div><div class='ctx'> 	int pipe_cnt = 0;</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes = kzalloc(dc-&gt;res_pool-&gt;pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);</div><div class='del'>-	struct mall_temp_config mall_temp_config;</div><div class='ctx'> </div><div class='ctx'> 	/* To handle Freesync properly, setting FreeSync DML parameters</div><div class='ctx'> 	 * to its default state for the first stage of validation</div><div class='hunk'>@@ -1827,29 +1749,12 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_val</div><div class='ctx'> </div><div class='ctx'> 	DC_LOGGER_INIT(dc-&gt;ctx-&gt;logger);</div><div class='ctx'> </div><div class='del'>-	/* For fast validation, there are situations where a shallow copy of</div><div class='del'>-	 * of the dc-&gt;current_state is created for the validation. In this case</div><div class='del'>-	 * we want to save and restore the mall config because we always</div><div class='del'>-	 * teardown subvp at the beginning of validation (and don't attempt</div><div class='del'>-	 * to add it back if it's fast validation). If we don't restore the</div><div class='del'>-	 * subvp config in cases of fast validation + shallow copy of the</div><div class='del'>-	 * dc-&gt;current_state, the dc-&gt;current_state will have a partially</div><div class='del'>-	 * removed subvp state when we did not intend to remove it.</div><div class='del'>-	 */</div><div class='del'>-	if (fast_validate) {</div><div class='del'>-		memset(&amp;mall_temp_config, 0, sizeof(mall_temp_config));</div><div class='del'>-		dcn32_save_mall_state(dc, context, &amp;mall_temp_config);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	BW_VAL_TRACE_COUNT();</div><div class='ctx'> </div><div class='ctx'> 	DC_FP_START();</div><div class='ctx'> 	out = dcn32_internal_validate_bw(dc, context, pipes, &amp;pipe_cnt, &amp;vlevel, fast_validate);</div><div class='ctx'> 	DC_FP_END();</div><div class='ctx'> </div><div class='del'>-	if (fast_validate)</div><div class='del'>-		dcn32_restore_mall_state(dc, context, &amp;mall_temp_config);</div><div class='del'>-</div><div class='ctx'> 	if (pipe_cnt == 0)</div><div class='ctx'> 		goto validate_out;</div><div class='ctx'> </div><div class='hunk'>@@ -1933,7 +1838,7 @@ int dcn32_populate_dml_pipes_from_context(</div><div class='ctx'> 		 * This is just a workaround -- needs a proper fix.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (!fast_validate) {</div><div class='del'>-			switch (pipe-&gt;stream-&gt;mall_stream_config.type) {</div><div class='add'>+			switch (dc_state_get_pipe_subvp_type(context, pipe)) {</div><div class='ctx'> 			case SUBVP_MAIN:</div><div class='ctx'> 				pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;</div><div class='ctx'> 				subvp_in_use = true;</div><div class='hunk'>@@ -2037,10 +1942,7 @@ static struct resource_funcs dcn32_res_pool_funcs = {</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,</div><div class='ctx'> 	.add_phantom_pipes = dcn32_add_phantom_pipes,</div><div class='del'>-	.remove_phantom_pipes = dcn32_remove_phantom_pipes,</div><div class='del'>-	.retain_phantom_pipes = dcn32_retain_phantom_pipes,</div><div class='del'>-	.save_mall_state = dcn32_save_mall_state,</div><div class='del'>-	.restore_mall_state = dcn32_restore_mall_state,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='hunk'>@@ -2453,16 +2355,19 @@ static bool dcn32_resource_construct(</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_plane_to_context = &amp;dc_add_plane_to_context;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_stream_to_ctx = &amp;dc_add_stream_to_ctx;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_plane = &amp;dc_state_add_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_stream = &amp;dc_state_add_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_plane = &amp;dc_create_plane_state;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_plane_from_context = &amp;dc_remove_plane_from_context;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_stream_from_ctx = &amp;dc_remove_stream_from_ctx;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_stream_for_sink = &amp;dc_create_stream_for_sink;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.plane_state_release = &amp;dc_plane_state_release;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.stream_release = &amp;dc_stream_release;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_plane = &amp;dc_state_create_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_plane = &amp;dc_state_remove_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_stream = &amp;dc_state_remove_phantom_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_stream = &amp;dc_state_create_phantom_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_plane = &amp;dc_state_release_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_stream = &amp;dc_state_release_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.release_dsc = &amp;dcn20_release_dsc;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_pipe_subvp_type = &amp;dc_state_get_pipe_subvp_type;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_stream_subvp_type = &amp;dc_state_get_stream_subvp_type;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_paired_subvp_stream = &amp;dc_state_get_paired_subvp_stream;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h<br/>index b931008114c9..0c87b0fabba7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h</a></div><div class='hunk'>@@ -39,6 +39,7 @@</div><div class='ctx'> #define DCN3_2_MBLK_HEIGHT_8BPE 64</div><div class='ctx'> #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq</div><div class='ctx'> #define SUBVP_HIGH_REFRESH_LIST_LEN 4</div><div class='add'>+#define SUBVP_ACTIVE_MARGIN_LIST_LEN 2</div><div class='ctx'> #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800</div><div class='ctx'> #define DCN3_2_VMIN_DISPCLK_HZ 717000000</div><div class='ctx'> </div><div class='hunk'>@@ -57,6 +58,15 @@ struct subvp_high_refresh_list {</div><div class='ctx'> 	} res[SUBVP_HIGH_REFRESH_LIST_LEN];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct subvp_active_margin_list {</div><div class='add'>+	int min_refresh;</div><div class='add'>+	int max_refresh;</div><div class='add'>+	struct {</div><div class='add'>+		int width;</div><div class='add'>+		int height;</div><div class='add'>+	} res[SUBVP_ACTIVE_MARGIN_LIST_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dcn32_resource_pool {</div><div class='ctx'> 	struct resource_pool base;</div><div class='ctx'> };</div><div class='hunk'>@@ -81,12 +91,6 @@ bool dcn32_release_post_bldn_3dlut(</div><div class='ctx'> 		struct dc_3dlut **lut,</div><div class='ctx'> 		struct dc_transfer_func **shaper);</div><div class='ctx'> </div><div class='del'>-bool dcn32_remove_phantom_pipes(struct dc *dc,</div><div class='del'>-		struct dc_state *context, bool fast_update);</div><div class='del'>-</div><div class='del'>-void dcn32_retain_phantom_pipes(struct dc *dc,</div><div class='del'>-		struct dc_state *context);</div><div class='del'>-</div><div class='ctx'> void dcn32_add_phantom_pipes(struct dc *dc,</div><div class='ctx'> 		struct dc_state *context,</div><div class='ctx'> 		display_e2e_pipe_params_st *pipes,</div><div class='hunk'>@@ -159,15 +163,7 @@ void dcn32_determine_det_override(struct dc *dc,</div><div class='ctx'> void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,</div><div class='ctx'> 	display_e2e_pipe_params_st *pipes);</div><div class='ctx'> </div><div class='del'>-void dcn32_save_mall_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct mall_temp_config *temp_config);</div><div class='del'>-</div><div class='del'>-void dcn32_restore_mall_state(struct dc *dc,</div><div class='del'>-		struct dc_state *context,</div><div class='del'>-		struct mall_temp_config *temp_config);</div><div class='del'>-</div><div class='del'>-struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, const struct dc_state *context);</div><div class='add'>+struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='ctx'> bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);</div><div class='ctx'> </div><div class='hunk'>@@ -183,6 +179,8 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);</div><div class='ctx'> </div><div class='ctx'> bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel);</div><div class='ctx'> </div><div class='add'>+void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);</div><div class='add'>+</div><div class='ctx'> /* definitions for run time init of reg offsets */</div><div class='ctx'> </div><div class='ctx'> /* CLK SRC */</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c<br/>index f7de3eca1225..74412e5f03fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c</a></div><div class='hunk'>@@ -63,7 +63,7 @@</div><div class='ctx'> #include "dcn31/dcn31_apg.h"</div><div class='ctx'> #include "dcn31/dcn31_dio_link_encoder.h"</div><div class='ctx'> #include "dcn32/dcn32_dio_link_encoder.h"</div><div class='del'>-#include "dcn321_dio_link_encoder.h"</div><div class='add'>+#include "dcn321/dcn321_dio_link_encoder.h"</div><div class='ctx'> #include "dce/dce_clock_source.h"</div><div class='ctx'> #include "dce/dce_audio.h"</div><div class='ctx'> #include "dce/dce_hwseq.h"</div><div class='hunk'>@@ -92,6 +92,8 @@</div><div class='ctx'> #include "vm_helper.h"</div><div class='ctx'> #include "dcn20/dcn20_vmid.h"</div><div class='ctx'> </div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='ctx'> enum dcn321_clk_src_array_id {</div><div class='hunk'>@@ -1605,10 +1607,7 @@ static struct resource_funcs dcn321_res_pool_funcs = {</div><div class='ctx'> 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,</div><div class='ctx'> 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,</div><div class='ctx'> 	.add_phantom_pipes = dcn32_add_phantom_pipes,</div><div class='del'>-	.remove_phantom_pipes = dcn32_remove_phantom_pipes,</div><div class='del'>-	.retain_phantom_pipes = dcn32_retain_phantom_pipes,</div><div class='del'>-	.save_mall_state = dcn32_save_mall_state,</div><div class='del'>-	.restore_mall_state = dcn32_restore_mall_state,</div><div class='add'>+	.build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint32_t read_pipe_fuses(struct dc_context *ctx)</div><div class='hunk'>@@ -2007,16 +2006,19 @@ static bool dcn321_resource_construct(</div><div class='ctx'> 	dc-&gt;dml2_options.callbacks.get_opp_head = &amp;resource_get_opp_head;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.dc = dc;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_plane_to_context = &amp;dc_add_plane_to_context;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.add_stream_to_ctx = &amp;dc_add_stream_to_ctx;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_plane = &amp;dc_state_add_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.add_phantom_stream = &amp;dc_state_add_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.build_scaling_params = &amp;resource_build_scaling_params;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_plane = &amp;dc_create_plane_state;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_plane_from_context = &amp;dc_remove_plane_from_context;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.remove_stream_from_ctx = &amp;dc_remove_stream_from_ctx;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.create_stream_for_sink = &amp;dc_create_stream_for_sink;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.plane_state_release = &amp;dc_plane_state_release;</div><div class='del'>-	dc-&gt;dml2_options.svp_pstate.callbacks.stream_release = &amp;dc_stream_release;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_plane = &amp;dc_state_create_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_plane = &amp;dc_state_remove_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.remove_phantom_stream = &amp;dc_state_remove_phantom_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.create_phantom_stream = &amp;dc_state_create_phantom_stream;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_plane = &amp;dc_state_release_phantom_plane;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.release_phantom_stream = &amp;dc_state_release_phantom_stream;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.callbacks.release_dsc = &amp;dcn20_release_dsc;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_pipe_subvp_type = &amp;dc_state_get_pipe_subvp_type;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_stream_subvp_type = &amp;dc_state_get_stream_subvp_type;</div><div class='add'>+	dc-&gt;dml2_options.svp_pstate.callbacks.get_paired_subvp_stream = &amp;dc_state_get_paired_subvp_stream;</div><div class='ctx'> </div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc-&gt;caps.subvp_fw_processing_delay_us;</div><div class='ctx'> 	dc-&gt;dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc-&gt;caps.subvp_prefetch_end_to_mall_start_us;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h<br/>index 82cbf009f2d3..82cbf009f2d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.h</a></div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c<br/>index c7e011d26d41..761ec9891875 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@</div><div class='ctx'> #include "dcn10/dcn10_resource.h"</div><div class='ctx'> #include "dcn31/dcn31_panel_cntl.h"</div><div class='ctx'> #include "dcn35/dcn35_hwseq.h"</div><div class='del'>-#include "dcn35_dio_link_encoder.h"</div><div class='add'>+#include "dcn35/dcn35_dio_link_encoder.h"</div><div class='ctx'> #include "dml/dcn31/dcn31_fpu.h" /*todo*/</div><div class='ctx'> #include "dml/dcn35/dcn35_fpu.h"</div><div class='ctx'> #include "dcn35/dcn35_dwb.h"</div><div class='hunk'>@@ -96,12 +96,15 @@</div><div class='ctx'> #include "reg_helper.h"</div><div class='ctx'> #include "dce/dmub_abm.h"</div><div class='ctx'> #include "dce/dmub_psr.h"</div><div class='add'>+#include "dce/dmub_replay.h"</div><div class='ctx'> #include "dce/dce_aux.h"</div><div class='ctx'> #include "dce/dce_i2c.h"</div><div class='ctx'> #include "dml/dcn31/display_mode_vba_31.h" /*temp*/</div><div class='ctx'> #include "vm_helper.h"</div><div class='ctx'> #include "dcn20/dcn20_vmid.h"</div><div class='ctx'> </div><div class='add'>+#include "dc_state_priv.h"</div><div class='add'>+</div><div class='ctx'> #include "link_enc_cfg.h"</div><div class='ctx'> #define DC_LOGGER_INIT(logger)</div><div class='ctx'> </div><div class='hunk'>@@ -626,7 +629,19 @@ static struct dce_hwseq_registers hwseq_reg;</div><div class='ctx'> 	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='ctx'> 	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='ctx'> 	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \</div><div class='del'>-	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh)</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\</div><div class='add'>+	HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)</div><div class='ctx'> </div><div class='ctx'> static const struct dce_hwseq_shift hwseq_shift = {</div><div class='ctx'> 		HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)</div><div class='hunk'>@@ -705,7 +720,9 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.disable_dcc = DCC_ENABLE,</div><div class='ctx'> 	.disable_dpp_power_gate = true,</div><div class='ctx'> 	.disable_hubp_power_gate = true,</div><div class='del'>-	.disable_clock_gate = true,</div><div class='add'>+	.disable_optc_power_gate = true, /*should the same as above two*/</div><div class='add'>+	.disable_hpo_power_gate = true, /*dmubfw force domain25 on*/</div><div class='add'>+	.disable_clock_gate = false,</div><div class='ctx'> 	.disable_dsc_power_gate = true,</div><div class='ctx'> 	.vsr_support = true,</div><div class='ctx'> 	.performance_trace = false,</div><div class='hunk'>@@ -724,7 +741,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 			.i2c = true,</div><div class='ctx'> 			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled</div><div class='ctx'> 			.dscl = true,</div><div class='del'>-			.cm = false,</div><div class='add'>+			.cm = true,</div><div class='ctx'> 			.mpc = true,</div><div class='ctx'> 			.optc = true,</div><div class='ctx'> 			.vpg = true,</div><div class='hunk'>@@ -752,7 +769,7 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.enable_hpo_pg_support = false,</div><div class='ctx'> 	.enable_legacy_fast_update = true,</div><div class='ctx'> 	.enable_single_display_2to1_odm_policy = false,</div><div class='del'>-	.disable_idle_power_optimizations = true,</div><div class='add'>+	.disable_idle_power_optimizations = false,</div><div class='ctx'> 	.dmcub_emulation = false,</div><div class='ctx'> 	.disable_boot_optimizations = false,</div><div class='ctx'> 	.disable_unbounded_requesting = false,</div><div class='hunk'>@@ -764,13 +781,15 @@ static const struct dc_debug_options debug_defaults_drv = {</div><div class='ctx'> 	.ignore_pg = true,</div><div class='ctx'> 	.psp_disabled_wa = true,</div><div class='ctx'> 	.ips2_eval_delay_us = 200,</div><div class='del'>-	.ips2_entry_delay_us = 400</div><div class='add'>+	.ips2_entry_delay_us = 400,</div><div class='add'>+	.static_screen_wait_frames = 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dc_panel_config panel_config_defaults = {</div><div class='ctx'> 	.psr = {</div><div class='ctx'> 		.disable_psr = false,</div><div class='ctx'> 		.disallow_psrsu = false,</div><div class='add'>+		.disallow_replay = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	.ilr = {</div><div class='ctx'> 		.optimize_edp_link_rate = true,</div><div class='hunk'>@@ -1529,6 +1548,9 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)</div><div class='ctx'> 	if (pool-&gt;base.psr != NULL)</div><div class='ctx'> 		dmub_psr_destroy(&amp;pool-&gt;base.psr);</div><div class='ctx'> </div><div class='add'>+	if (pool-&gt;base.replay != NULL)</div><div class='add'>+		dmub_replay_destroy(&amp;pool-&gt;base.replay);</div><div class='add'>+</div><div class='ctx'> 	if (pool-&gt;base.pg_cntl != NULL)</div><div class='ctx'> 		dcn_pg_cntl_destroy(&amp;pool-&gt;base.pg_cntl);</div><div class='ctx'> </div><div class='hunk'>@@ -1712,6 +1734,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc,</div><div class='ctx'> </div><div class='ctx'> 	out = dml2_validate(dc, context, fast_validate);</div><div class='ctx'> </div><div class='add'>+	if (fast_validate)</div><div class='add'>+		return out;</div><div class='add'>+</div><div class='add'>+	DC_FP_START();</div><div class='add'>+	dcn35_decide_zstate_support(dc, context);</div><div class='add'>+	DC_FP_END();</div><div class='add'>+</div><div class='ctx'> 	return out;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1857,7 +1886,7 @@ static bool dcn35_resource_construct(</div><div class='ctx'> </div><div class='ctx'> 	/* Use pipe context based otg sync logic */</div><div class='ctx'> 	dc-&gt;config.use_pipe_ctx_sync_logic = true;</div><div class='del'>-	dc-&gt;config.use_default_clock_table = false;</div><div class='add'>+</div><div class='ctx'> 	/* read VBIOS LTTPR caps */</div><div class='ctx'> 	{</div><div class='ctx'> 		if (ctx-&gt;dc_bios-&gt;funcs-&gt;get_lttpr_caps) {</div><div class='hunk'>@@ -2006,6 +2035,14 @@ static bool dcn35_resource_construct(</div><div class='ctx'> 		goto create_fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Replay */</div><div class='add'>+	pool-&gt;base.replay = dmub_replay_create(ctx);</div><div class='add'>+	if (pool-&gt;base.replay == NULL) {</div><div class='add'>+		dm_error("DC: failed to create replay obj!\n");</div><div class='add'>+		BREAK_TO_DEBUGGER();</div><div class='add'>+		goto create_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* ABM */</div><div class='ctx'> 	for (i = 0; i &lt; pool-&gt;base.res_cap-&gt;num_timing_generator; i++) {</div><div class='ctx'> 		pool-&gt;base.multiple_abms[i] = dmub_abm_create(ctx,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h<br/>index 99aea102e3f7..a51c4a9eaafe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h</a></div><div class='hunk'>@@ -166,6 +166,7 @@ struct resource_pool *dcn35_create_resource_pool(</div><div class='ctx'> 	SR(MMHUBBUB_MEM_PWR_CNTL), \</div><div class='ctx'> 	SR(DCCG_GATE_DISABLE_CNTL), \</div><div class='ctx'> 	SR(DCCG_GATE_DISABLE_CNTL2), \</div><div class='add'>+	SR(DCCG_GATE_DISABLE_CNTL4), \</div><div class='ctx'> 	SR(DCCG_GATE_DISABLE_CNTL5), \</div><div class='ctx'> 	SR(DCFCLK_CNTL),\</div><div class='ctx'> 	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h<br/>index df63aa8f01e9..c78c9224ab60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/dmub_srv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/dmub_srv.h</a></div><div class='hunk'>@@ -86,6 +86,7 @@ enum dmub_status {</div><div class='ctx'> 	DMUB_STATUS_TIMEOUT,</div><div class='ctx'> 	DMUB_STATUS_INVALID,</div><div class='ctx'> 	DMUB_STATUS_HW_FAILURE,</div><div class='add'>+	DMUB_STATUS_POWER_STATE_D3</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* enum dmub_asic - dmub asic identifier */</div><div class='hunk'>@@ -150,6 +151,13 @@ enum dmub_memory_access_type {</div><div class='ctx'> 	DMUB_MEMORY_ACCESS_DMA</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* enum dmub_power_state type - to track DC power state in dmub_srv */</div><div class='add'>+enum dmub_srv_power_state_type {</div><div class='add'>+	DMUB_POWER_STATE_UNDEFINED = 0,</div><div class='add'>+	DMUB_POWER_STATE_D0 = 1,</div><div class='add'>+	DMUB_POWER_STATE_D3 = 8</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct dmub_region - dmub hw memory region</div><div class='ctx'>  * @base: base address for region, must be 256 byte aligned</div><div class='hunk'>@@ -485,6 +493,8 @@ struct dmub_srv {</div><div class='ctx'> 	/* Feature capabilities reported by fw */</div><div class='ctx'> 	struct dmub_feature_caps feature_caps;</div><div class='ctx'> 	struct dmub_visual_confirm_color visual_confirm_color;</div><div class='add'>+</div><div class='add'>+	enum dmub_srv_power_state_type power_state;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -889,6 +899,18 @@ enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub);</div><div class='ctx'>  */</div><div class='ctx'> void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * dmub_srv_set_power_state() - Track DC power state in dmub_srv</div><div class='add'>+ * @dmub: The dmub service</div><div class='add'>+ * @power_state: DC power state setting</div><div class='add'>+ *</div><div class='add'>+ * Store DC power state in dmub_srv.  If dmub_srv is in D3, then don't send messages to DMUB</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ *   void</div><div class='add'>+ */</div><div class='add'>+void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);</div><div class='add'>+</div><div class='ctx'> #if defined(__cplusplus)</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h<br/>index ed4379c04715..c64b6c848ef7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h</a></div><div class='hunk'>@@ -185,8 +185,7 @@ union abm_flags {</div><div class='ctx'> 		unsigned int disable_abm_requested : 1;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled</div><div class='del'>-		 * immediately.</div><div class='add'>+		 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned int disable_abm_immediately : 1;</div><div class='ctx'> </div><div class='hunk'>@@ -654,7 +653,7 @@ union dmub_fw_boot_options {</div><div class='ctx'> 		uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/</div><div class='ctx'> 		uint32_t usb4_cm_version: 1; /**&lt; 1 CM support */</div><div class='ctx'> 		uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */</div><div class='del'>-		uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */</div><div class='add'>+		uint32_t reserved0: 1;</div><div class='ctx'> 		uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/</div><div class='ctx'> 		uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */</div><div class='ctx'> 		uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/</div><div class='hunk'>@@ -818,18 +817,61 @@ enum dmub_gpint_command {</div><div class='ctx'> 	 * RETURN: Lower 32-bit mask.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='del'>-	 * DESC: Updates the trace buffer lower 32-bit mask.</div><div class='add'>+	 * DESC: Updates the trace buffer mask bit0~bit15.</div><div class='ctx'> 	 * ARGS: The new mask</div><div class='ctx'> 	 * RETURN: Lower 32-bit mask.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='del'>-	 * DESC: Updates the trace buffer mask bi0~bit15.</div><div class='add'>+	 * DESC: Updates the trace buffer mask bit16~bit31.</div><div class='ctx'> 	 * ARGS: The new mask</div><div class='ctx'> 	 * RETURN: Lower 32-bit mask.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the trace buffer mask bit32~bit47.</div><div class='add'>+	 * ARGS: The new mask</div><div class='add'>+	 * RETURN: Lower 32-bit mask.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the trace buffer mask bit48~bit63.</div><div class='add'>+	 * ARGS: The new mask</div><div class='add'>+	 * RETURN: Lower 32-bit mask.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Read the trace buffer mask bi0~bit15.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Read the trace buffer mask bit16~bit31.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Read the trace buffer mask bi32~bit47.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Updates the trace buffer mask bit32~bit63.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * DESC: Enable measurements for various task duration</div><div class='add'>+	 * ARGS: 0 - Disable measurement</div><div class='add'>+	 *       1 - Enable measurement</div><div class='add'>+	 */</div><div class='add'>+	DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1303,6 +1345,10 @@ enum dmub_cmd_cab_type {</div><div class='ctx'> 	 * Fit surfaces in CAB (i.e. CAB enable)</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,</div><div class='add'>+	/**</div><div class='add'>+	 * Do not fit surfaces in CAB (i.e. no CAB)</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2840,6 +2886,14 @@ enum dmub_cmd_replay_type {</div><div class='ctx'> 	 * Set power opt and coasting vtotal.</div><div class='ctx'> 	 */</div><div class='ctx'> 	DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL	= 4,</div><div class='add'>+	/**</div><div class='add'>+	 * Set disabled iiming sync.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED	= 5,</div><div class='add'>+	/**</div><div class='add'>+	 * Set Residency Frameupdate Timer.</div><div class='add'>+	 */</div><div class='add'>+	DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3003,6 +3057,26 @@ struct dmub_cmd_replay_set_power_opt_data {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_replay_set_timing_sync_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * REPLAY set_timing_sync</div><div class='add'>+	 */</div><div class='add'>+	uint8_t timing_sync_supported;</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_rb_cmd_replay_set_power_opt {</div><div class='hunk'>@@ -3069,6 +3143,73 @@ struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_replay_set_timing_sync {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Data passed from driver to FW in  DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.</div><div class='add'>+ */</div><div class='add'>+struct dmub_cmd_replay_frameupdate_timer_data {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Replay Frameupdate Timer Enable or not</div><div class='add'>+	 */</div><div class='add'>+	uint8_t enable;</div><div class='add'>+	/**</div><div class='add'>+	 * REPLAY force reflash frame update number</div><div class='add'>+	 */</div><div class='add'>+	uint16_t frameupdate_count;</div><div class='add'>+};</div><div class='add'>+/**</div><div class='add'>+ * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER</div><div class='add'>+ */</div><div class='add'>+struct dmub_rb_cmd_replay_set_frameupdate_timer {</div><div class='add'>+	/**</div><div class='add'>+	 * Command header.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_header header;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_frameupdate_timer_data data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * Definition union of replay command set</div><div class='add'>+ */</div><div class='add'>+union dmub_replay_cmd_set {</div><div class='add'>+	/**</div><div class='add'>+	 * Panel Instance.</div><div class='add'>+	 * Panel isntance to identify which replay_state to use</div><div class='add'>+	 * Currently the support is only for 0 or 1</div><div class='add'>+	 */</div><div class='add'>+	uint8_t panel_inst;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_set_timing_sync_data sync_data;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_cmd_replay_frameupdate_timer_data timer_data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Set of HW components that can be locked.</div><div class='ctx'>  *</div><div class='ctx'>  * Note: If updating with more HW components, fields</div><div class='hunk'>@@ -3357,6 +3498,16 @@ struct dmub_cmd_abm_set_pipe_data {</div><div class='ctx'> 	 * TODO: Remove.</div><div class='ctx'> 	 */</div><div class='ctx'> 	uint8_t ramping_boundary;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * PwrSeq HW Instance.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pwrseq_inst;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Explicit padding to 4 byte boundary.</div><div class='add'>+	 */</div><div class='add'>+	uint8_t pad[3];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3737,7 +3888,7 @@ enum dmub_cmd_panel_cntl_type {</div><div class='ctx'>  * struct dmub_cmd_panel_cntl_data - Panel control data.</div><div class='ctx'>  */</div><div class='ctx'> struct dmub_cmd_panel_cntl_data {</div><div class='del'>-	uint32_t inst; /**&lt; panel instance */</div><div class='add'>+	uint32_t pwrseq_inst; /**&lt; pwrseq instance */</div><div class='ctx'> 	uint32_t current_backlight; /* in/out */</div><div class='ctx'> 	uint32_t bl_pwm_cntl; /* in/out */</div><div class='ctx'> 	uint32_t bl_pwm_period_cntl; /* in/out */</div><div class='hunk'>@@ -3796,7 +3947,7 @@ struct dmub_cmd_lvtma_control_data {</div><div class='ctx'> 	uint8_t uc_pwr_action; /**&lt; LVTMA_ACTION */</div><div class='ctx'> 	uint8_t bypass_panel_control_wait;</div><div class='ctx'> 	uint8_t reserved_0[2]; /**&lt; For future use */</div><div class='del'>-	uint8_t panel_inst; /**&lt; LVTMA control instance */</div><div class='add'>+	uint8_t pwrseq_inst; /**&lt; LVTMA control instance */</div><div class='ctx'> 	uint8_t reserved_1[3]; /**&lt; For future use */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -4201,6 +4352,12 @@ union dmub_rb_cmd {</div><div class='ctx'> 	 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;</div><div class='add'>+</div><div class='add'>+	struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;</div><div class='add'>+	/**</div><div class='add'>+	 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.</div><div class='add'>+	 */</div><div class='add'>+	struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c<br/>index 22fc4ba96def..9ad738805320 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c</a></div><div class='hunk'>@@ -64,7 +64,7 @@</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> /* Default scratch mem size. */</div><div class='del'>-#define DMUB_SCRATCH_MEM_SIZE (256)</div><div class='add'>+#define DMUB_SCRATCH_MEM_SIZE (1024)</div><div class='ctx'> </div><div class='ctx'> /* Number of windows in use. */</div><div class='ctx'> #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)</div><div class='hunk'>@@ -713,6 +713,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,</div><div class='ctx'> 		dmub-&gt;hw_funcs.reset_release(dmub);</div><div class='ctx'> </div><div class='ctx'> 	dmub-&gt;hw_init = true;</div><div class='add'>+	dmub-&gt;power_state = DMUB_POWER_STATE_D0;</div><div class='ctx'> </div><div class='ctx'> 	return DMUB_STATUS_OK;</div><div class='ctx'> }</div><div class='hunk'>@@ -766,6 +767,9 @@ enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,</div><div class='ctx'> 	if (!dmub-&gt;hw_init)</div><div class='ctx'> 		return DMUB_STATUS_INVALID;</div><div class='ctx'> </div><div class='add'>+	if (dmub-&gt;power_state != DMUB_POWER_STATE_D0)</div><div class='add'>+		return DMUB_STATUS_POWER_STATE_D3;</div><div class='add'>+</div><div class='ctx'> 	if (dmub-&gt;inbox1_rb.rptr &gt; dmub-&gt;inbox1_rb.capacity ||</div><div class='ctx'> 	    dmub-&gt;inbox1_rb.wrpt &gt; dmub-&gt;inbox1_rb.capacity) {</div><div class='ctx'> 		return DMUB_STATUS_HW_FAILURE;</div><div class='hunk'>@@ -784,6 +788,9 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)</div><div class='ctx'> 	if (!dmub-&gt;hw_init)</div><div class='ctx'> 		return DMUB_STATUS_INVALID;</div><div class='ctx'> </div><div class='add'>+	if (dmub-&gt;power_state != DMUB_POWER_STATE_D0)</div><div class='add'>+		return DMUB_STATUS_POWER_STATE_D3;</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * Read back all the queued commands to ensure that they've</div><div class='ctx'> 	 * been flushed to framebuffer memory. Otherwise DMCUB might</div><div class='hunk'>@@ -1077,6 +1084,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti</div><div class='ctx'> 		ack = dmub-&gt;hw_funcs.read_inbox0_ack_register(dmub);</div><div class='ctx'> 		if (ack)</div><div class='ctx'> 			return DMUB_STATUS_OK;</div><div class='add'>+		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	return DMUB_STATUS_TIMEOUT;</div><div class='ctx'> }</div><div class='hunk'>@@ -1099,3 +1107,11 @@ void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_</div><div class='ctx'> 				subvp_index);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state)</div><div class='add'>+{</div><div class='add'>+	if (!dmub || !dmub-&gt;hw_init)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dmub-&gt;power_state = dmub_srv_power_state;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/audio_types.h b/drivers/gpu/drm/amd/display/include/audio_types.h<br/>index 66a54da0641c..915a031a43cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/audio_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/include/audio_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/audio_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/audio_types.h</a></div><div class='hunk'>@@ -64,7 +64,7 @@ enum audio_dto_source {</div><div class='ctx'> /* PLL information required for AZALIA DTO calculation */</div><div class='ctx'> </div><div class='ctx'> struct audio_pll_info {</div><div class='del'>-	uint32_t dp_dto_source_clock_in_khz;</div><div class='add'>+	uint32_t audio_dto_source_clock_in_khz;</div><div class='ctx'> 	uint32_t feed_back_divider;</div><div class='ctx'> 	enum audio_dto_source dto_source;</div><div class='ctx'> 	bool ss_enabled;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h<br/>index bc96d0211360..813463ffe15c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h</a></div><div class='hunk'>@@ -417,6 +417,8 @@ struct integrated_info {</div><div class='ctx'> 	/* V2.1 */</div><div class='ctx'> 	struct edp_info edp1_info;</div><div class='ctx'> 	struct edp_info edp2_info;</div><div class='add'>+	uint32_t gpuclk_ss_percentage;</div><div class='add'>+	uint32_t gpuclk_ss_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h b/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h<br/>index 42229b4effdc..eced9ad91f1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/include/hdcp_msg_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/include/hdcp_msg_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/include/hdcp_msg_types.h</a></div><div class='hunk'>@@ -69,6 +69,11 @@ enum hdcp_message_id {</div><div class='ctx'> 	HDCP_MESSAGE_ID_READ_RXSTATUS,</div><div class='ctx'> 	HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,</div><div class='ctx'> </div><div class='add'>+	/* PS175 chip */</div><div class='add'>+</div><div class='add'>+	HDCP_MESSAGE_ID_WRITE_PS175_CMD,</div><div class='add'>+	HDCP_MESSAGE_ID_READ_PS175_RSP,</div><div class='add'>+</div><div class='ctx'> 	HDCP_MESSAGE_ID_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c<br/>index ccecddafeb05..3955b7e4b2e2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/freesync/freesync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/freesync/freesync.c</a></div><div class='hunk'>@@ -81,6 +81,7 @@ fail_alloc_context:</div><div class='ctx'> void mod_freesync_destroy(struct mod_freesync *mod_freesync)</div><div class='ctx'> {</div><div class='ctx'> 	struct core_freesync *core_freesync = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (mod_freesync == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);</div><div class='hunk'>@@ -278,9 +279,8 @@ static void apply_below_the_range(struct core_freesync *core_freesync,</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (last_render_time_in_us &gt; (max_render_time_in_us + in_out_vrr-&gt;btr.margin_in_us / 2)) {</div><div class='ctx'> 		/* Enter Below the Range */</div><div class='del'>-		if (!in_out_vrr-&gt;btr.btr_active) {</div><div class='add'>+		if (!in_out_vrr-&gt;btr.btr_active)</div><div class='ctx'> 			in_out_vrr-&gt;btr.btr_active = true;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* BTR set to "not active" so disengage */</div><div class='hunk'>@@ -693,10 +693,12 @@ static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,</div><div class='ctx'> 	if (app_tf != TRANSFER_FUNC_UNKNOWN) {</div><div class='ctx'> 		infopacket-&gt;valid = true;</div><div class='ctx'> </div><div class='del'>-		if (app_tf != TRANSFER_FUNC_PQ2084) {</div><div class='add'>+		if (app_tf == TRANSFER_FUNC_PQ2084)</div><div class='add'>+			infopacket-&gt;sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]</div><div class='add'>+		else {</div><div class='ctx'> 			infopacket-&gt;sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]</div><div class='ctx'> 			if (app_tf == TRANSFER_FUNC_GAMMA_22)</div><div class='del'>-				infopacket-&gt;sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]</div><div class='add'>+				infopacket-&gt;sb[9] |= 0x04;  // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c<br/>index 1ddb4f5eac8e..182e7532dda8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c</a></div><div class='hunk'>@@ -63,6 +63,7 @@ static inline enum mod_hdcp_status check_hdcp_capable_dp(struct mod_hdcp *hdcp)</div><div class='ctx'> static inline enum mod_hdcp_status check_r0p_available_dp(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	enum mod_hdcp_status status;</div><div class='add'>+</div><div class='ctx'> 	if (is_dp_hdcp(hdcp)) {</div><div class='ctx'> 		status = (hdcp-&gt;auth.msg.hdcp1.bstatus &amp;</div><div class='ctx'> 				DP_BSTATUS_R0_PRIME_READY) ?</div><div class='hunk'>@@ -131,9 +132,8 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	/* Avoid device count == 0 to do authentication */</div><div class='del'>-	if (0 == get_device_count(hdcp)) {</div><div class='add'>+	if (get_device_count(hdcp) == 0)</div><div class='ctx'> 		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* Some MST display may choose to report the internal panel as an HDCP RX.</div><div class='ctx'> 	 * To update this condition with 1(because the immediate repeater's internal</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c<br/>index 91c22b96ebde..733f22bed021 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c</a></div><div class='hunk'>@@ -208,9 +208,8 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)</div><div class='ctx'> {</div><div class='ctx'> 	/* Avoid device count == 0 to do authentication */</div><div class='del'>-	if (0 == get_device_count(hdcp)) {</div><div class='add'>+	if (get_device_count(hdcp) == 0)</div><div class='ctx'> 		return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/* Some MST display may choose to report the internal panel as an HDCP RX.   */</div><div class='ctx'> 	/* To update this condition with 1(because the immediate repeater's internal */</div><div class='hunk'>@@ -689,9 +688,8 @@ static enum mod_hdcp_status validate_stream_ready(struct mod_hdcp *hdcp,</div><div class='ctx'> 	if (is_hdmi_dvi_sl_hdcp(hdcp)) {</div><div class='ctx'> 		if (!process_rxstatus(hdcp, event_ctx, input, &amp;status))</div><div class='ctx'> 			goto out;</div><div class='del'>-		if (event_ctx-&gt;rx_id_list_ready) {</div><div class='add'>+		if (event_ctx-&gt;rx_id_list_ready)</div><div class='ctx'> 			goto out;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (is_hdmi_dvi_sl_hdcp(hdcp))</div><div class='ctx'> 		if (!mod_hdcp_execute_and_set(check_stream_ready_available,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h<br/>index c62df3bcc7cb..1d83c1b9da10 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h</a></div><div class='hunk'>@@ -86,10 +86,12 @@</div><div class='ctx'> #define HDCP_CPIRQ_TRACE(hdcp) \</div><div class='ctx'> 		HDCP_LOG_FSM(hdcp, "[Link %d] --&gt; CPIRQ", hdcp-&gt;config.index)</div><div class='ctx'> #define HDCP_EVENT_TRACE(hdcp, event) \</div><div class='del'>-		if (event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) \</div><div class='del'>-			HDCP_TIMEOUT_TRACE(hdcp); \</div><div class='del'>-		else if (event == MOD_HDCP_EVENT_CPIRQ) \</div><div class='del'>-			HDCP_CPIRQ_TRACE(hdcp)</div><div class='add'>+		do { \</div><div class='add'>+			if (event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) \</div><div class='add'>+				HDCP_TIMEOUT_TRACE(hdcp); \</div><div class='add'>+			else if (event == MOD_HDCP_EVENT_CPIRQ) \</div><div class='add'>+				HDCP_CPIRQ_TRACE(hdcp);	\</div><div class='add'>+		} while (0)</div><div class='ctx'> /* TODO: find some way to tell if logging is off to save time */</div><div class='ctx'> #define HDCP_DDC_READ_TRACE(hdcp, msg_name, msg, msg_size) do { \</div><div class='ctx'> 		mod_hdcp_dump_binary_message(msg, msg_size, hdcp-&gt;buf, \</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c<br/>index ee67a35c2a8e..8c137d7c032e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c</a></div><div class='hunk'>@@ -443,7 +443,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(struct mod_hdcp</div><div class='ctx'> 	for (i = 0; i &lt; MAX_NUM_OF_DISPLAYS; i++) {</div><div class='ctx'> </div><div class='ctx'> 		if (hdcp-&gt;displays[i].adjust.disable || hdcp-&gt;displays[i].state != MOD_HDCP_DISPLAY_ACTIVE)</div><div class='del'>-				continue;</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));</div><div class='ctx'> </div><div class='hunk'>@@ -926,7 +926,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_NUM_OF_DISPLAYS; i++) {</div><div class='ctx'> 		if (hdcp-&gt;displays[i].adjust.disable || hdcp-&gt;displays[i].state != MOD_HDCP_DISPLAY_ACTIVE)</div><div class='del'>-				continue;</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		hdcp_cmd-&gt;in_msg.hdcp2_enable_dp_stream_encryption.display_handle = hdcp-&gt;displays[i].index;</div><div class='ctx'> 		hdcp_cmd-&gt;in_msg.hdcp2_enable_dp_stream_encryption.session_handle = hdcp-&gt;auth.id;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h<br/>index 5b71bc96b98c..7844ea91650b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h</a></div><div class='hunk'>@@ -98,9 +98,9 @@ enum ta_dtm_encoder_type {</div><div class='ctx'>  * This enum defines software value for dio_output_type</div><div class='ctx'>  */</div><div class='ctx'> typedef enum {</div><div class='del'>-    TA_DTM_DIO_OUTPUT_TYPE__INVALID,</div><div class='del'>-    TA_DTM_DIO_OUTPUT_TYPE__DIRECT,</div><div class='del'>-    TA_DTM_DIO_OUTPUT_TYPE__DPIA</div><div class='add'>+	TA_DTM_DIO_OUTPUT_TYPE__INVALID,</div><div class='add'>+	TA_DTM_DIO_OUTPUT_TYPE__DIRECT,</div><div class='add'>+	TA_DTM_DIO_OUTPUT_TYPE__DPIA</div><div class='ctx'> } ta_dtm_dio_output_type;</div><div class='ctx'> </div><div class='ctx'> struct ta_dtm_topology_update_input_v3 {</div><div class='hunk'>@@ -237,11 +237,11 @@ enum ta_hdcp2_hdcp2_msg_id_max_size {</div><div class='ctx'> #define TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES 127</div><div class='ctx'> #define TA_HDCP__HDCP1_V_PRIME_SIZE 20</div><div class='ctx'> #define TA_HDCP__HDCP2_TX_BUF_MAX_SIZE                                                                                 \</div><div class='del'>-	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM + 6</div><div class='add'>+	(TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM + 6)</div><div class='ctx'> </div><div class='ctx'> // 64 bits boundaries</div><div class='ctx'> #define TA_HDCP__HDCP2_RX_BUF_MAX_SIZE                                                                                 \</div><div class='del'>-	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO + 4</div><div class='add'>+	(TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO + 4)</div><div class='ctx'> </div><div class='ctx'> enum ta_hdcp_status {</div><div class='ctx'> 	TA_HDCP_STATUS__SUCCESS = 0x00,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h<br/>index afe1f6cce528..cc3dc9b589f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h</a></div><div class='hunk'>@@ -23,34 +23,6 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Copyright 2016 Advanced Micro Devices, Inc.</div><div class='del'>- *</div><div class='del'>- * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='del'>- * copy of this software and associated documentation files (the "Software"),</div><div class='del'>- * to deal in the Software without restriction, including without limitation</div><div class='del'>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='del'>- * and/or sell copies of the Software, and to permit persons to whom the</div><div class='del'>- * Software is furnished to do so, subject to the following conditions:</div><div class='del'>- *</div><div class='del'>- * The above copyright notice and this permission notice shall be included in</div><div class='del'>- * all copies or substantial portions of the Software.</div><div class='del'>- *</div><div class='del'>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='del'>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='del'>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='del'>- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='del'>- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='del'>- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='del'>- * OTHER DEALINGS IN THE SOFTWARE.</div><div class='del'>- *</div><div class='del'>- * Authors: AMD</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='ctx'> #ifndef MOD_FREESYNC_H_</div><div class='ctx'> #define MOD_FREESYNC_H_</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c<br/>index 84f9b412a4f1..738ee763f24a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c</a></div><div class='hunk'>@@ -147,12 +147,15 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */</div><div class='del'>-	if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1)</div><div class='del'>-		vsc_packet_revision = vsc_packet_rev4;</div><div class='del'>-	else if (stream-&gt;link-&gt;replay_settings.config.replay_supported)</div><div class='add'>+	if (stream-&gt;link-&gt;psr_settings.psr_feature_enabled) {</div><div class='add'>+		if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_SU_1)</div><div class='add'>+			vsc_packet_revision = vsc_packet_rev4;</div><div class='add'>+		else if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1)</div><div class='add'>+			vsc_packet_revision = vsc_packet_rev2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (stream-&gt;link-&gt;replay_settings.config.replay_supported)</div><div class='ctx'> 		vsc_packet_revision = vsc_packet_rev4;</div><div class='del'>-	else if (stream-&gt;link-&gt;psr_settings.psr_version == DC_PSR_VERSION_1)</div><div class='del'>-		vsc_packet_revision = vsc_packet_rev2;</div><div class='ctx'> </div><div class='ctx'> 	/* Update to revision 5 for extended colorimetry support */</div><div class='ctx'> 	if (stream-&gt;use_vsc_sdp_for_colorimetry)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c<br/>index a522a7c02911..ad98e504c00d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/power/power_helpers.c</a></div><div class='hunk'>@@ -31,7 +31,7 @@</div><div class='ctx'> </div><div class='ctx'> #define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))</div><div class='ctx'> #define bswap16_based_on_endian(big_endian, value) \</div><div class='del'>-	(big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)</div><div class='add'>+	((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))</div><div class='ctx'> </div><div class='ctx'> /* Possible Min Reduction config from least aggressive to most aggressive</div><div class='ctx'>  *  0    1     2     3     4     5     6     7     8     9     10    11   12</div><div class='hunk'>@@ -839,6 +839,8 @@ bool is_psr_su_specific_panel(struct dc_link *link)</div><div class='ctx'> 				((dpcd_caps-&gt;sink_dev_id_str[1] == 0x08 &amp;&amp; dpcd_caps-&gt;sink_dev_id_str[0] == 0x08) ||</div><div class='ctx'> 				(dpcd_caps-&gt;sink_dev_id_str[1] == 0x08 &amp;&amp; dpcd_caps-&gt;sink_dev_id_str[0] == 0x07)))</div><div class='ctx'> 				isPSRSUSupported = false;</div><div class='add'>+			else if (dpcd_caps-&gt;sink_dev_id_str[1] == 0x08 &amp;&amp; dpcd_caps-&gt;sink_dev_id_str[0] == 0x03)</div><div class='add'>+				isPSRSUSupported = false;</div><div class='ctx'> 			else if (dpcd_caps-&gt;psr_info.force_psrsu_cap == 0x1)</div><div class='ctx'> 				isPSRSUSupported = true;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -971,6 +973,34 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void set_replay_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint16_t vtotal)</div><div class='add'>+{</div><div class='add'>+	link-&gt;replay_settings.coasting_vtotal_table[type] = vtotal;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void calculate_replay_link_off_frame_count(struct dc_link *link,</div><div class='add'>+	uint16_t vtotal, uint16_t htotal)</div><div class='add'>+{</div><div class='add'>+	uint8_t max_link_off_frame_count = 0;</div><div class='add'>+	uint16_t max_deviation_line = 0,  pixel_deviation_per_line = 0;</div><div class='add'>+</div><div class='add'>+	max_deviation_line = link-&gt;dpcd_caps.pr_info.max_deviation_line;</div><div class='add'>+	pixel_deviation_per_line = link-&gt;dpcd_caps.pr_info.pixel_deviation_per_line;</div><div class='add'>+</div><div class='add'>+	if (htotal != 0 &amp;&amp; vtotal != 0)</div><div class='add'>+		max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal);</div><div class='add'>+	else</div><div class='add'>+		ASSERT(0);</div><div class='add'>+</div><div class='add'>+	link-&gt;replay_settings.link_off_frame_count_level =</div><div class='add'>+		max_link_off_frame_count &gt;= PR_LINK_OFF_FRAME_COUNT_BEST ? PR_LINK_OFF_FRAME_COUNT_BEST :</div><div class='add'>+		max_link_off_frame_count &gt;= PR_LINK_OFF_FRAME_COUNT_GOOD ? PR_LINK_OFF_FRAME_COUNT_GOOD :</div><div class='add'>+		PR_LINK_OFF_FRAME_COUNT_FAIL;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int data_points_size;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h<br/>index d9e0d67d67f7..c17bbc6fb38c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/display/modules/power/power_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/display/modules/power/power_helpers.h</a></div><div class='hunk'>@@ -54,6 +54,11 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,</div><div class='ctx'> 		unsigned int inst);</div><div class='ctx'> </div><div class='ctx'> void init_replay_config(struct dc_link *link, struct replay_config *pr_config);</div><div class='add'>+void set_replay_coasting_vtotal(struct dc_link *link,</div><div class='add'>+	enum replay_coasting_vtotal_type type,</div><div class='add'>+	uint16_t vtotal);</div><div class='add'>+void calculate_replay_link_off_frame_count(struct dc_link *link,</div><div class='add'>+	uint16_t vtotal, uint16_t htotal);</div><div class='ctx'> </div><div class='ctx'> bool is_psr_su_specific_panel(struct dc_link *link);</div><div class='ctx'> void mod_power_calc_psr_configs(struct psr_config *psr_config,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h<br/>index 7f98394338c2..1dc5dd9b7bf7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/amd_shared.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/amd_shared.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/amd_shared.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/amd_shared.h</a></div><div class='hunk'>@@ -244,7 +244,6 @@ enum DC_FEATURE_MASK {</div><div class='ctx'> 	DC_DISABLE_LTTPR_DP2_0 = (1 &lt;&lt; 6), //0x40, disabled by default</div><div class='ctx'> 	DC_PSR_ALLOW_SMU_OPT = (1 &lt;&lt; 7), //0x80, disabled by default</div><div class='ctx'> 	DC_PSR_ALLOW_MULTI_DISP_OPT = (1 &lt;&lt; 8), //0x100, disabled by default</div><div class='del'>-	DC_REPLAY_MASK = (1 &lt;&lt; 9), //0x200, disabled by default for dcn &lt; 3.1.4</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum DC_DEBUG_MASK {</div><div class='hunk'>@@ -255,8 +254,10 @@ enum DC_DEBUG_MASK {</div><div class='ctx'> 	DC_DISABLE_PSR = 0x10,</div><div class='ctx'> 	DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,</div><div class='ctx'> 	DC_DISABLE_MPO = 0x40,</div><div class='del'>-	DC_DISABLE_REPLAY = 0x50,</div><div class='ctx'> 	DC_ENABLE_DPIA_TRACE = 0x80,</div><div class='add'>+	DC_ENABLE_DML2 = 0x100,</div><div class='add'>+	DC_DISABLE_PSR_SU = 0x200,</div><div class='add'>+	DC_DISABLE_REPLAY = 0x400,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum amd_dpm_forced_level;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/amdgpu_reg_state.h b/drivers/gpu/drm/amd/include/amdgpu_reg_state.h<br/>new file mode 100644<br/>index 000000000000..be519c8edf49<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/amdgpu_reg_state.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/amdgpu_reg_state.h</a></div><div class='hunk'>@@ -0,0 +1,153 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __AMDGPU_REG_STATE_H__</div><div class='add'>+#define __AMDGPU_REG_STATE_H__</div><div class='add'>+</div><div class='add'>+enum amdgpu_reg_state {</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_INVALID	= 0,</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_XGMI	= 1,</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_WAFL	= 2,</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_PCIE	= 3,</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_USR	= 4,</div><div class='add'>+	AMDGPU_REG_STATE_TYPE_USR_1	= 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum amdgpu_sysfs_reg_offset {</div><div class='add'>+	AMDGPU_SYS_REG_STATE_XGMI	= 0x0000,</div><div class='add'>+	AMDGPU_SYS_REG_STATE_WAFL	= 0x1000,</div><div class='add'>+	AMDGPU_SYS_REG_STATE_PCIE	= 0x2000,</div><div class='add'>+	AMDGPU_SYS_REG_STATE_USR	= 0x3000,</div><div class='add'>+	AMDGPU_SYS_REG_STATE_USR_1	= 0x4000,</div><div class='add'>+	AMDGPU_SYS_REG_STATE_END	= 0x5000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_state_header {</div><div class='add'>+	uint16_t		structure_size;</div><div class='add'>+	uint8_t			format_revision;</div><div class='add'>+	uint8_t			content_revision;</div><div class='add'>+	uint8_t			state_type;</div><div class='add'>+	uint8_t			num_instances;</div><div class='add'>+	uint16_t		pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum amdgpu_reg_inst_state {</div><div class='add'>+	AMDGPU_INST_S_OK,</div><div class='add'>+	AMDGPU_INST_S_EDISABLED,</div><div class='add'>+	AMDGPU_INST_S_EACCESS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_smn_reg_data {</div><div class='add'>+	uint64_t addr;</div><div class='add'>+	uint32_t value;</div><div class='add'>+	uint32_t pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_inst_header {</div><div class='add'>+	uint16_t	instance;</div><div class='add'>+	uint16_t	state;</div><div class='add'>+	uint16_t	num_smn_regs;</div><div class='add'>+	uint16_t	pad;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+struct amdgpu_regs_xgmi_v1_0 {</div><div class='add'>+	struct amdgpu_reg_inst_header	inst_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_smn_reg_data	smn_reg_values[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_state_xgmi_v1_0 {</div><div class='add'>+	/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_XGMI */</div><div class='add'>+	struct amdgpu_reg_state_header	common_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_regs_xgmi_v1_0	xgmi_state_regs[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_regs_wafl_v1_0 {</div><div class='add'>+	struct amdgpu_reg_inst_header	inst_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_smn_reg_data	smn_reg_values[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_state_wafl_v1_0 {</div><div class='add'>+	/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_WAFL */</div><div class='add'>+	struct amdgpu_reg_state_header	common_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_regs_wafl_v1_0	wafl_state_regs[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_regs_pcie_v1_0 {</div><div class='add'>+	struct amdgpu_reg_inst_header	inst_header;</div><div class='add'>+</div><div class='add'>+	uint16_t			device_status;</div><div class='add'>+	uint16_t			link_status;</div><div class='add'>+	uint32_t			sub_bus_number_latency;</div><div class='add'>+	uint32_t			pcie_corr_err_status;</div><div class='add'>+	uint32_t			pcie_uncorr_err_status;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_smn_reg_data	smn_reg_values[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_state_pcie_v1_0 {</div><div class='add'>+	/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_PCIE */</div><div class='add'>+	struct amdgpu_reg_state_header	common_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_regs_pcie_v1_0	pci_state_regs[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_regs_usr_v1_0 {</div><div class='add'>+	struct amdgpu_reg_inst_header	inst_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_smn_reg_data	smn_reg_values[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_reg_state_usr_v1_0 {</div><div class='add'>+	/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_USR */</div><div class='add'>+	struct amdgpu_reg_state_header	common_header;</div><div class='add'>+</div><div class='add'>+	struct amdgpu_regs_usr_v1_0	usr_state_regs[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline size_t amdgpu_reginst_size(uint16_t num_inst, size_t inst_size,</div><div class='add'>+					 uint16_t num_regs)</div><div class='add'>+{</div><div class='add'>+	return num_inst *</div><div class='add'>+	       (inst_size + num_regs * sizeof(struct amdgpu_smn_reg_data));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define amdgpu_asic_get_reg_state_supported(adev) \</div><div class='add'>+	((adev)-&gt;asic_funcs-&gt;get_reg_state ? 1 : 0)</div><div class='add'>+</div><div class='add'>+#define amdgpu_asic_get_reg_state(adev, state, buf, size)                  \</div><div class='add'>+	((adev)-&gt;asic_funcs-&gt;get_reg_state ?                               \</div><div class='add'>+		 (adev)-&gt;asic_funcs-&gt;get_reg_state((adev), (state), (buf), \</div><div class='add'>+						   (size)) :               \</div><div class='add'>+		 0)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev);</div><div class='add'>+void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h<br/>index b64664879211..fca72e2ec929 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h</a></div><div class='hunk'>@@ -6220,12 +6220,20 @@</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE__SHIFT                                              0x17</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE__SHIFT                                              0x18</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE__SHIFT                                              0x19</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE__SHIFT                                              0x1a</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L</div><div class='ctx'> #define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE_MASK                                                0x00800000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE_MASK                                                0x01000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE_MASK                                                0x02000000L</div><div class='add'>+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE_MASK                                                0x04000000L</div><div class='ctx'> #define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0</div><div class='ctx'> #define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3</div><div class='ctx'> #define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h<br/>index c92c4b83253f..4bff1ef8a9a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h</a></div><div class='hunk'>@@ -6369,6 +6369,8 @@</div><div class='ctx'> #define regTCP_INVALIDATE_BASE_IDX                                                                      1</div><div class='ctx'> #define regTCP_STATUS                                                                                   0x19a1</div><div class='ctx'> #define regTCP_STATUS_BASE_IDX                                                                          1</div><div class='add'>+#define regTCP_CNTL                                                                                     0x19a2</div><div class='add'>+#define regTCP_CNTL_BASE_IDX                                                                            1</div><div class='ctx'> #define regTCP_CNTL2                                                                                    0x19a3</div><div class='ctx'> #define regTCP_CNTL2_BASE_IDX                                                                           1</div><div class='ctx'> #define regTCP_DEBUG_INDEX                                                                              0x19a5</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h<br/>index ff30f04be591..6f80bfa7e41a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h</a></div><div class='hunk'>@@ -781,6 +781,8 @@</div><div class='ctx'> #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2_BASE_IDX                                              5</div><div class='ctx'> #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1                                             0x420187</div><div class='ctx'> #define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1_BASE_IDX                                    5</div><div class='add'>+#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3                                                  0x4201c6</div><div class='add'>+#define regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3_BASE_IDX                                         5</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp</div><div class='hunk'>@@ -8705,10 +8707,10 @@</div><div class='ctx'> #define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX                                                             2</div><div class='ctx'> #define regBIF_BX1_BX_RESET_CNTL                                                                        0x00f0</div><div class='ctx'> #define regBIF_BX1_BX_RESET_CNTL_BASE_IDX                                                               2</div><div class='del'>-#define regBIF_BX1_INTERRUPT_CNTL                                                                       0x8e11</div><div class='del'>-#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX                                                              5</div><div class='del'>-#define regBIF_BX1_INTERRUPT_CNTL2                                                                      0x8e12</div><div class='del'>-#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX                                                             5</div><div class='add'>+#define regBIF_BX1_INTERRUPT_CNTL                                                                       0x00f1</div><div class='add'>+#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX                                                              2</div><div class='add'>+#define regBIF_BX1_INTERRUPT_CNTL2                                                                      0x00f2</div><div class='add'>+#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX                                                             2</div><div class='ctx'> #define regBIF_BX1_CLKREQB_PAD_CNTL                                                                     0x00f8</div><div class='ctx'> #define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX                                                            2</div><div class='ctx'> #define regBIF_BX1_BIF_FEATURES_CONTROL_MISC                                                            0x00fb</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h<br/>index 7f131999a263..eb8c556d9c93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h</a></div><div class='hunk'>@@ -24646,6 +24646,35 @@</div><div class='ctx'> //BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1</div><div class='ctx'> #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK                                  0x00000001L</div><div class='ctx'> #define BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK                               0x00000008L</div><div class='add'>+//BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT                     0x8</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT                     0x9</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE__SHIFT                          0xb</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT                     0xd</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN__SHIFT                            0xf</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT                          0x10</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT                          0x11</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT                     0x14</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT                     0x15</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE__SHIFT                             0x18</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                       0x19</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT                0x1b</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT                0x1c</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT                  0x1e</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK                       0x00000100L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK                       0x00000600L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_10BIT_TAG_EN_OVERRIDE_MASK                            0x00001800L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK                       0x00006000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__MST_DROP_SYNC_FLOOD_EN_MASK                              0x00008000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_PAYLOAD_SIZE_MODE_MASK                            0x00010000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_PAYLOAD_SIZE_MASK                            0x000E0000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_REQUEST_SIZE_MODE_MASK                       0x00100000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK                       0x00E00000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_MAX_READ_SAFE_MODE_MASK                               0x01000000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                         0x06000000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK                  0x08000000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK                  0x30000000L</div><div class='add'>+#define BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK                    0xC0000000L</div><div class='ctx'> </div><div class='ctx'> // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp</div><div class='ctx'> //BIF_CFG_DEV0_RC0_VENDOR_ID</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h<br/>new file mode 100644<br/>index 000000000000..a4dd372c0541<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h</a></div><div class='hunk'>@@ -0,0 +1,102 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023  Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included</div><div class='add'>+ * in all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS</div><div class='add'>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN</div><div class='add'>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN</div><div class='add'>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+#ifndef _smuio_10_0_2_OFFSET_HEADER</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_misc_SmuSmuioDec</div><div class='add'>+// base address: 0x5a000</div><div class='add'>+#define mmSMUIO_MCM_CONFIG                                                                             0x0023</div><div class='add'>+#define mmSMUIO_MCM_CONFIG_BASE_IDX                                                                    0</div><div class='add'>+#define mmIP_DISCOVERY_VERSION                                                                         0x0000</div><div class='add'>+#define mmIP_DISCOVERY_VERSION_BASE_IDX                                                                1</div><div class='add'>+#define mmIO_SMUIO_PINSTRAP                                                                            0x01b1</div><div class='add'>+#define mmIO_SMUIO_PINSTRAP_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER0                                                                            0x01b2</div><div class='add'>+#define mmSCRATCH_REGISTER0_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER1                                                                            0x01b3</div><div class='add'>+#define mmSCRATCH_REGISTER1_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER2                                                                            0x01b4</div><div class='add'>+#define mmSCRATCH_REGISTER2_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER3                                                                            0x01b5</div><div class='add'>+#define mmSCRATCH_REGISTER3_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER4                                                                            0x01b6</div><div class='add'>+#define mmSCRATCH_REGISTER4_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER5                                                                            0x01b7</div><div class='add'>+#define mmSCRATCH_REGISTER5_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER6                                                                            0x01b8</div><div class='add'>+#define mmSCRATCH_REGISTER6_BASE_IDX                                                                   1</div><div class='add'>+#define mmSCRATCH_REGISTER7                                                                            0x01b9</div><div class='add'>+#define mmSCRATCH_REGISTER7_BASE_IDX                                                                   1</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_reset_SmuSmuioDec</div><div class='add'>+// base address: 0x5a300</div><div class='add'>+#define mmSMUIO_MP_RESET_INTR                                                                          0x00c1</div><div class='add'>+#define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0</div><div class='add'>+#define mmSMUIO_SOC_HALT                                                                               0x00c2</div><div class='add'>+#define mmSMUIO_SOC_HALT_BASE_IDX                                                                      0</div><div class='add'>+#define mmSMUIO_GFX_MISC_CNTL                                                                          0x00c8</div><div class='add'>+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                                                                 0</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec</div><div class='add'>+// base address: 0x5a000</div><div class='add'>+#define mmPWROK_REFCLK_GAP_CYCLES                                                                      0x0001</div><div class='add'>+#define mmPWROK_REFCLK_GAP_CYCLES_BASE_IDX                                                             1</div><div class='add'>+#define mmGOLDEN_TSC_INCREMENT_UPPER                                                                   0x0004</div><div class='add'>+#define mmGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX                                                          1</div><div class='add'>+#define mmGOLDEN_TSC_INCREMENT_LOWER                                                                   0x0005</div><div class='add'>+#define mmGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX                                                          1</div><div class='add'>+#define mmGOLDEN_TSC_COUNT_UPPER                                                                       0x0025</div><div class='add'>+#define mmGOLDEN_TSC_COUNT_UPPER_BASE_IDX                                                              1</div><div class='add'>+#define mmGOLDEN_TSC_COUNT_LOWER                                                                       0x0026</div><div class='add'>+#define mmGOLDEN_TSC_COUNT_LOWER_BASE_IDX                                                              1</div><div class='add'>+#define mmGFX_GOLDEN_TSC_SHADOW_UPPER                                                                  0x0029</div><div class='add'>+#define mmGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX                                                         1</div><div class='add'>+#define mmGFX_GOLDEN_TSC_SHADOW_LOWER                                                                  0x002a</div><div class='add'>+#define mmGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX                                                         1</div><div class='add'>+#define mmSOC_GOLDEN_TSC_SHADOW_UPPER                                                                  0x002b</div><div class='add'>+#define mmSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX                                                         1</div><div class='add'>+#define mmSOC_GOLDEN_TSC_SHADOW_LOWER                                                                  0x002c</div><div class='add'>+#define mmSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX                                                         1</div><div class='add'>+#define mmSOC_GAP_PWROK                                                                                0x002d</div><div class='add'>+#define mmSOC_GAP_PWROK_BASE_IDX                                                                       1</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_swtimer_SmuSmuioDec</div><div class='add'>+// base address: 0x5ac40</div><div class='add'>+#define mmPWR_VIRT_RESET_REQ                                                                           0x0110</div><div class='add'>+#define mmPWR_VIRT_RESET_REQ_BASE_IDX                                                                  1</div><div class='add'>+#define mmPWR_DISP_TIMER_CONTROL                                                                       0x0111</div><div class='add'>+#define mmPWR_DISP_TIMER_CONTROL_BASE_IDX                                                              1</div><div class='add'>+#define mmPWR_DISP_TIMER2_CONTROL                                                                      0x0113</div><div class='add'>+#define mmPWR_DISP_TIMER2_CONTROL_BASE_IDX                                                             1</div><div class='add'>+#define mmPWR_DISP_TIMER_GLOBAL_CONTROL                                                                0x0115</div><div class='add'>+#define mmPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX                                                       1</div><div class='add'>+#define mmPWR_IH_CONTROL                                                                               0x0116</div><div class='add'>+#define mmPWR_IH_CONTROL_BASE_IDX                                                                      1</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_svi0_SmuSmuioDec</div><div class='add'>+// base address: 0x6f000</div><div class='add'>+#define mmSMUSVI0_TEL_PLANE0                                                                           0x520e</div><div class='add'>+#define mmSMUSVI0_TEL_PLANE0_BASE_IDX                                                                  1</div><div class='add'>+#define mmSMUSVI0_PLANE0_CURRENTVID                                                                    0x5217</div><div class='add'>+#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX                                                           1</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h<br/>new file mode 100644<br/>index 000000000000..d10ae61c346b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h</a></div><div class='hunk'>@@ -0,0 +1,184 @@</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023  Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included</div><div class='add'>+ * in all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS</div><div class='add'>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN</div><div class='add'>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN</div><div class='add'>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+#ifndef _smuio_10_0_2_SH_MASK_HEADER</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_misc_SmuSmuioDec</div><div class='add'>+//SMUIO_MCM_CONFIG</div><div class='add'>+#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT                                                                       0x0</div><div class='add'>+#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT                                                                     0x2</div><div class='add'>+#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT                                                                    0x5</div><div class='add'>+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT                                                                  0x6</div><div class='add'>+#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT                                                                    0x10</div><div class='add'>+#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT                                                                    0x11</div><div class='add'>+#define SMUIO_MCM_CONFIG__DIE_ID_MASK                                                                         0x00000003L</div><div class='add'>+#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK                                                                       0x0000001CL</div><div class='add'>+#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK                                                                      0x00000020L</div><div class='add'>+#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK                                                                    0x000000C0L</div><div class='add'>+#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK                                                                      0x00010000L</div><div class='add'>+#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK                                                                      0x00020000L</div><div class='add'>+//IP_DISCOVERY_VERSION</div><div class='add'>+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT                                                     0x0</div><div class='add'>+#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK                                                       0xFFFFFFFFL</div><div class='add'>+//IO_SMUIO_PINSTRAP</div><div class='add'>+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT                                                               0x0</div><div class='add'>+#define IO_SMUIO_PINSTRAP__AUD__SHIFT                                                                         0x3</div><div class='add'>+#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK                                                                 0x00000007L</div><div class='add'>+#define IO_SMUIO_PINSTRAP__AUD_MASK                                                                           0x00000018L</div><div class='add'>+//SCRATCH_REGISTER0</div><div class='add'>+#define SCRATCH_REGISTER0__ScratchPad0__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER0__ScratchPad0_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER1</div><div class='add'>+#define SCRATCH_REGISTER1__ScratchPad1__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER1__ScratchPad1_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER2</div><div class='add'>+#define SCRATCH_REGISTER2__ScratchPad2__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER2__ScratchPad2_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER3</div><div class='add'>+#define SCRATCH_REGISTER3__ScratchPad3__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER3__ScratchPad3_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER4</div><div class='add'>+#define SCRATCH_REGISTER4__ScratchPad4__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER4__ScratchPad4_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER5</div><div class='add'>+#define SCRATCH_REGISTER5__ScratchPad5__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER5__ScratchPad5_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER6</div><div class='add'>+#define SCRATCH_REGISTER6__ScratchPad6__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER6__ScratchPad6_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+//SCRATCH_REGISTER7</div><div class='add'>+#define SCRATCH_REGISTER7__ScratchPad7__SHIFT                                                                 0x0</div><div class='add'>+#define SCRATCH_REGISTER7__ScratchPad7_MASK                                                                   0xFFFFFFFFL</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_reset_SmuSmuioDec</div><div class='add'>+//SMUIO_MP_RESET_INTR</div><div class='add'>+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT                                                       0x0</div><div class='add'>+#define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK                                                         0x00000001L</div><div class='add'>+//SMUIO_SOC_HALT</div><div class='add'>+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT                                                             0x2</div><div class='add'>+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT                                                            0x3</div><div class='add'>+#define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK                                                               0x00000004L</div><div class='add'>+#define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK                                                              0x00000008L</div><div class='add'>+//SMUIO_GFX_MISC_CNTL</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT                                                    0x0</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT                                                         0x1</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH__SHIFT                                                   0x3</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN__SHIFT                                                       0x4</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK                                                      0x00000001L</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK                                                           0x00000006L</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFX_DLDO_CLK_SWITCH_MASK                                                     0x00000008L</div><div class='add'>+#define SMUIO_GFX_MISC_CNTL__PWR_GFX_RLC_CGPG_EN_MASK                                                         0x00000010L</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_ccxctrl_SmuSmuioDec</div><div class='add'>+//PWROK_REFCLK_GAP_CYCLES</div><div class='add'>+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT                                      0x0</div><div class='add'>+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT                                     0x8</div><div class='add'>+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK                                        0x000000FFL</div><div class='add'>+#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK                                       0x0000FF00L</div><div class='add'>+//GOLDEN_TSC_INCREMENT_UPPER</div><div class='add'>+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT                                            0x0</div><div class='add'>+#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK                                              0x00FFFFFFL</div><div class='add'>+//GOLDEN_TSC_INCREMENT_LOWER</div><div class='add'>+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT                                            0x0</div><div class='add'>+#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK                                              0xFFFFFFFFL</div><div class='add'>+//GOLDEN_TSC_COUNT_UPPER</div><div class='add'>+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT                                                    0x0</div><div class='add'>+#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK                                                      0x00FFFFFFL</div><div class='add'>+//GOLDEN_TSC_COUNT_LOWER</div><div class='add'>+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT                                                    0x0</div><div class='add'>+#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK                                                      0xFFFFFFFFL</div><div class='add'>+//GFX_GOLDEN_TSC_SHADOW_UPPER</div><div class='add'>+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper__SHIFT                                           0x0</div><div class='add'>+#define GFX_GOLDEN_TSC_SHADOW_UPPER__GfxGoldenTscShadowUpper_MASK                                             0x00FFFFFFL</div><div class='add'>+//GFX_GOLDEN_TSC_SHADOW_LOWER</div><div class='add'>+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower__SHIFT                                           0x0</div><div class='add'>+#define GFX_GOLDEN_TSC_SHADOW_LOWER__GfxGoldenTscShadowLower_MASK                                             0xFFFFFFFFL</div><div class='add'>+//SOC_GOLDEN_TSC_SHADOW_UPPER</div><div class='add'>+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT                                           0x0</div><div class='add'>+#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK                                             0x00FFFFFFL</div><div class='add'>+//SOC_GOLDEN_TSC_SHADOW_LOWER</div><div class='add'>+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT                                           0x0</div><div class='add'>+#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK                                             0xFFFFFFFFL</div><div class='add'>+//SOC_GAP_PWROK</div><div class='add'>+#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT                                                                   0x0</div><div class='add'>+#define SOC_GAP_PWROK__soc_gap_pwrok_MASK                                                                     0x00000001L</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_swtimer_SmuSmuioDec</div><div class='add'>+//PWR_VIRT_RESET_REQ</div><div class='add'>+#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT                                                                     0x0</div><div class='add'>+#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT                                                                     0x1f</div><div class='add'>+#define PWR_VIRT_RESET_REQ__VF_FLR_MASK                                                                       0x7FFFFFFFL</div><div class='add'>+#define PWR_VIRT_RESET_REQ__PF_FLR_MASK                                                                       0x80000000L</div><div class='add'>+//PWR_DISP_TIMER_CONTROL</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT                                                   0x0</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT                                                  0x19</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT                                                 0x1a</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT                                                    0x1b</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT                                                 0x1c</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT                                                    0x1d</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT                                                    0x1e</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK                                                     0x01FFFFFFL</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK                                                    0x02000000L</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK                                                   0x04000000L</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK                                                      0x08000000L</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK                                                   0x10000000L</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK                                                      0x20000000L</div><div class='add'>+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK                                                      0x40000000L</div><div class='add'>+//PWR_DISP_TIMER2_CONTROL</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT                                                  0x0</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT                                                 0x19</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT                                                0x1a</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT                                                   0x1b</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT                                                0x1c</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT                                                   0x1d</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT                                                   0x1e</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK                                                    0x01FFFFFFL</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK                                                   0x02000000L</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK                                                  0x04000000L</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK                                                     0x08000000L</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK                                                  0x10000000L</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK                                                     0x20000000L</div><div class='add'>+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK                                                     0x40000000L</div><div class='add'>+//PWR_DISP_TIMER_GLOBAL_CONTROL</div><div class='add'>+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT                                          0x0</div><div class='add'>+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT                                             0xa</div><div class='add'>+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK                                            0x000003FFL</div><div class='add'>+#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK                                               0x00000400L</div><div class='add'>+//PWR_IH_CONTROL</div><div class='add'>+#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT                                                                     0x0</div><div class='add'>+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT                                                        0x5</div><div class='add'>+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT                                                       0x6</div><div class='add'>+#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT                                                             0x1f</div><div class='add'>+#define PWR_IH_CONTROL__MAX_CREDIT_MASK                                                                       0x0000001FL</div><div class='add'>+#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK                                                          0x00000020L</div><div class='add'>+#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK                                                         0x00000040L</div><div class='add'>+#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK                                                               0x80000000L</div><div class='add'>+</div><div class='add'>+// addressBlock: smuio_smuio_svi0_SmuSmuioDec</div><div class='add'>+//SMUSVI0_TEL_PLANE0</div><div class='add'>+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT                                                         0x0</div><div class='add'>+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT                                                         0x10</div><div class='add'>+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK                                                           0x000000FFL</div><div class='add'>+#define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK                                                           0x01FF0000L</div><div class='add'>+//SMUSVI0_PLANE0_CURRENTVID</div><div class='add'>+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT                                             0x18</div><div class='add'>+#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK                                               0xFF000000L</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br/>index cd3c40a86029..edcb85560ced 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/kgd_pp_interface.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/kgd_pp_interface.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/kgd_pp_interface.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/kgd_pp_interface.h</a></div><div class='hunk'>@@ -318,6 +318,7 @@ enum pp_xgmi_plpd_mode {</div><div class='ctx'> #define MAX_GFX_CLKS 8</div><div class='ctx'> #define MAX_CLKS 4</div><div class='ctx'> #define NUM_VCN 4</div><div class='add'>+#define NUM_JPEG_ENG 32</div><div class='ctx'> </div><div class='ctx'> struct seq_file;</div><div class='ctx'> enum amd_pp_clock_type;</div><div class='hunk'>@@ -421,7 +422,7 @@ struct amd_pm_funcs {</div><div class='ctx'> 	int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);</div><div class='ctx'> 	int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);</div><div class='ctx'> 	int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);</div><div class='del'>-	int (*get_asic_baco_capability)(void *handle, bool *cap);</div><div class='add'>+	bool (*get_asic_baco_capability)(void *handle);</div><div class='ctx'> 	int (*get_asic_baco_state)(void *handle, int *state);</div><div class='ctx'> 	int (*set_asic_baco_state)(void *handle, int state);</div><div class='ctx'> 	int (*get_ppfeature_status)(void *handle, char *buf);</div><div class='hunk'>@@ -431,6 +432,7 @@ struct amd_pm_funcs {</div><div class='ctx'> 	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);</div><div class='ctx'> 	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);</div><div class='ctx'> 	ssize_t (*get_gpu_metrics)(void *handle, void **table);</div><div class='add'>+	ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);</div><div class='ctx'> 	int (*set_watermarks_for_clock_ranges)(void *handle,</div><div class='ctx'> 					       struct pp_smu_wm_range_sets *ranges);</div><div class='ctx'> 	int (*display_disable_memory_clock_switch)(void *handle,</div><div class='hunk'>@@ -444,6 +446,7 @@ struct amd_pm_funcs {</div><div class='ctx'> 				   struct dpm_clocks *clock_table);</div><div class='ctx'> 	int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);</div><div class='ctx'> 	void (*pm_compute_clocks)(void *handle);</div><div class='add'>+	int (*notify_rlc_state)(void *handle, bool en);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct metrics_table_header {</div><div class='hunk'>@@ -773,6 +776,85 @@ struct gpu_metrics_v1_4 {</div><div class='ctx'> 	uint16_t			padding;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct gpu_metrics_v1_5 {</div><div class='add'>+	struct metrics_table_header	common_header;</div><div class='add'>+</div><div class='add'>+	/* Temperature (Celsius) */</div><div class='add'>+	uint16_t			temperature_hotspot;</div><div class='add'>+	uint16_t			temperature_mem;</div><div class='add'>+	uint16_t			temperature_vrsoc;</div><div class='add'>+</div><div class='add'>+	/* Power (Watts) */</div><div class='add'>+	uint16_t			curr_socket_power;</div><div class='add'>+</div><div class='add'>+	/* Utilization (%) */</div><div class='add'>+	uint16_t			average_gfx_activity;</div><div class='add'>+	uint16_t			average_umc_activity; // memory controller</div><div class='add'>+	uint16_t			vcn_activity[NUM_VCN];</div><div class='add'>+	uint16_t			jpeg_activity[NUM_JPEG_ENG];</div><div class='add'>+</div><div class='add'>+	/* Energy (15.259uJ (2^-16) units) */</div><div class='add'>+	uint64_t			energy_accumulator;</div><div class='add'>+</div><div class='add'>+	/* Driver attached timestamp (in ns) */</div><div class='add'>+	uint64_t			system_clock_counter;</div><div class='add'>+</div><div class='add'>+	/* Throttle status */</div><div class='add'>+	uint32_t			throttle_status;</div><div class='add'>+</div><div class='add'>+	/* Clock Lock Status. Each bit corresponds to clock instance */</div><div class='add'>+	uint32_t			gfxclk_lock_status;</div><div class='add'>+</div><div class='add'>+	/* Link width (number of lanes) and speed (in 0.1 GT/s) */</div><div class='add'>+	uint16_t			pcie_link_width;</div><div class='add'>+	uint16_t			pcie_link_speed;</div><div class='add'>+</div><div class='add'>+	/* XGMI bus width and bitrate (in Gbps) */</div><div class='add'>+	uint16_t			xgmi_link_width;</div><div class='add'>+	uint16_t			xgmi_link_speed;</div><div class='add'>+</div><div class='add'>+	/* Utilization Accumulated (%) */</div><div class='add'>+	uint32_t			gfx_activity_acc;</div><div class='add'>+	uint32_t			mem_activity_acc;</div><div class='add'>+</div><div class='add'>+	/*PCIE accumulated bandwidth (GB/sec) */</div><div class='add'>+	uint64_t			pcie_bandwidth_acc;</div><div class='add'>+</div><div class='add'>+	/*PCIE instantaneous bandwidth (GB/sec) */</div><div class='add'>+	uint64_t			pcie_bandwidth_inst;</div><div class='add'>+</div><div class='add'>+	/* PCIE L0 to recovery state transition accumulated count */</div><div class='add'>+	uint64_t			pcie_l0_to_recov_count_acc;</div><div class='add'>+</div><div class='add'>+	/* PCIE replay accumulated count */</div><div class='add'>+	uint64_t			pcie_replay_count_acc;</div><div class='add'>+</div><div class='add'>+	/* PCIE replay rollover accumulated count */</div><div class='add'>+	uint64_t			pcie_replay_rover_count_acc;</div><div class='add'>+</div><div class='add'>+	/* PCIE NAK sent  accumulated count */</div><div class='add'>+	uint32_t			pcie_nak_sent_count_acc;</div><div class='add'>+</div><div class='add'>+	/* PCIE NAK received accumulated count */</div><div class='add'>+	uint32_t			pcie_nak_rcvd_count_acc;</div><div class='add'>+</div><div class='add'>+	/* XGMI accumulated data transfer size(KiloBytes) */</div><div class='add'>+	uint64_t			xgmi_read_data_acc[NUM_XGMI_LINKS];</div><div class='add'>+	uint64_t			xgmi_write_data_acc[NUM_XGMI_LINKS];</div><div class='add'>+</div><div class='add'>+	/* PMFW attached timestamp (10ns resolution) */</div><div class='add'>+	uint64_t			firmware_timestamp;</div><div class='add'>+</div><div class='add'>+	/* Current clocks (Mhz) */</div><div class='add'>+	uint16_t			current_gfxclk[MAX_GFX_CLKS];</div><div class='add'>+	uint16_t			current_socclk[MAX_CLKS];</div><div class='add'>+	uint16_t			current_vclk0[MAX_CLKS];</div><div class='add'>+	uint16_t			current_dclk0[MAX_CLKS];</div><div class='add'>+	uint16_t			current_uclk;</div><div class='add'>+</div><div class='add'>+	uint16_t			padding;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.</div><div class='ctx'>  * Use gpu_metrics_v2_1 or later instead.</div><div class='hunk'>@@ -1084,6 +1166,10 @@ struct gpu_metrics_v3_0 {</div><div class='ctx'> 	uint16_t			average_dram_reads;</div><div class='ctx'> 	/* time filtered DRAM write bandwidth [MB/sec] */</div><div class='ctx'> 	uint16_t			average_dram_writes;</div><div class='add'>+	/* time filtered IPU read bandwidth [MB/sec] */</div><div class='add'>+	uint16_t			average_ipu_reads;</div><div class='add'>+	/* time filtered IPU write bandwidth [MB/sec] */</div><div class='add'>+	uint16_t			average_ipu_writes;</div><div class='ctx'> </div><div class='ctx'> 	/* Driver attached timestamp (in ns) */</div><div class='ctx'> 	uint64_t			system_clock_counter;</div><div class='hunk'>@@ -1103,6 +1189,8 @@ struct gpu_metrics_v3_0 {</div><div class='ctx'> 	uint32_t			average_all_core_power;</div><div class='ctx'> 	/* calculated core power [mW] */</div><div class='ctx'> 	uint16_t			average_core_power[16];</div><div class='add'>+	/* time filtered total system power [mW] */</div><div class='add'>+	uint16_t			average_sys_power;</div><div class='ctx'> 	/* maximum IRM defined STAPM power limit [mW] */</div><div class='ctx'> 	uint16_t			stapm_power_limit;</div><div class='ctx'> 	/* time filtered STAPM power limit [mW] */</div><div class='hunk'>@@ -1115,6 +1203,8 @@ struct gpu_metrics_v3_0 {</div><div class='ctx'> 	uint16_t			average_ipuclk_frequency;</div><div class='ctx'> 	uint16_t			average_fclk_frequency;</div><div class='ctx'> 	uint16_t			average_vclk_frequency;</div><div class='add'>+	uint16_t			average_uclk_frequency;</div><div class='add'>+	uint16_t			average_mpipu_frequency;</div><div class='ctx'> </div><div class='ctx'> 	/* Current clocks */</div><div class='ctx'> 	/* target core frequency [MHz] */</div><div class='hunk'>@@ -1124,7 +1214,31 @@ struct gpu_metrics_v3_0 {</div><div class='ctx'> 	/* GFXCLK frequency limit enforced on GFX [MHz] */</div><div class='ctx'> 	uint16_t			current_gfx_maxfreq;</div><div class='ctx'> </div><div class='add'>+	/* Throttle Residency (ASIC dependent) */</div><div class='add'>+	uint32_t			throttle_residency_prochot;</div><div class='add'>+	uint32_t			throttle_residency_spl;</div><div class='add'>+	uint32_t			throttle_residency_fppt;</div><div class='add'>+	uint32_t			throttle_residency_sppt;</div><div class='add'>+	uint32_t			throttle_residency_thm_core;</div><div class='add'>+	uint32_t			throttle_residency_thm_gfx;</div><div class='add'>+	uint32_t			throttle_residency_thm_soc;</div><div class='add'>+</div><div class='ctx'> 	/* Metrics table alpha filter time constant [us] */</div><div class='ctx'> 	uint32_t			time_filter_alphavalue;</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+struct amdgpu_pmmetrics_header {</div><div class='add'>+	uint16_t structure_size;</div><div class='add'>+	uint16_t pad;</div><div class='add'>+	uint32_t mp1_ip_discovery_version;</div><div class='add'>+	uint32_t pmfw_version;</div><div class='add'>+	uint32_t pmmetrics_version;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct amdgpu_pm_metrics {</div><div class='add'>+	struct amdgpu_pmmetrics_header common_header;</div><div class='add'>+</div><div class='add'>+	uint8_t data[];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h<br/>index b1db2b190187..ec5b9ab67c5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/mes_v11_api_def.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/include/mes_v11_api_def.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/include/mes_v11_api_def.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/include/mes_v11_api_def.h</a></div><div class='hunk'>@@ -232,6 +232,7 @@ union MESAPI_SET_HW_RESOURCES {</div><div class='ctx'> 		};</div><div class='ctx'> 		uint32_t	oversubscription_timer;</div><div class='ctx'> 		uint64_t        doorbell_info;</div><div class='add'>+		uint64_t        event_intr_history_gpu_mc_ptr;</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	uint32_t	max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];</div><div class='hunk'>@@ -571,7 +572,8 @@ struct SET_SHADER_DEBUGGER {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			uint32_t single_memop : 1;  /* SQ_DEBUG.single_memop */</div><div class='ctx'> 			uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */</div><div class='del'>-			uint32_t reserved : 30;</div><div class='add'>+			uint32_t reserved : 29;</div><div class='add'>+			uint32_t process_ctx_flush : 1;</div><div class='ctx'> 		};</div><div class='ctx'> 		uint32_t u32all;</div><div class='ctx'> 	} flags;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c<br/>index 08cb79401410..6627ee07d52d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/amdgpu_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/amdgpu_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/amdgpu_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/amdgpu_dpm.c</a></div><div class='hunk'>@@ -181,12 +181,29 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	const struct amd_pm_funcs *pp_funcs = adev-&gt;powerplay.pp_funcs;</div><div class='add'>+</div><div class='add'>+	if (pp_funcs &amp;&amp; pp_funcs-&gt;notify_rlc_state) {</div><div class='add'>+		mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='add'>+</div><div class='add'>+		ret = pp_funcs-&gt;notify_rlc_state(</div><div class='add'>+				adev-&gt;powerplay.pp_handle,</div><div class='add'>+				en);</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;adev-&gt;pm.mutex);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	const struct amd_pm_funcs *pp_funcs = adev-&gt;powerplay.pp_funcs;</div><div class='ctx'> 	void *pp_handle = adev-&gt;powerplay.pp_handle;</div><div class='del'>-	bool baco_cap;</div><div class='del'>-	int ret = 0;</div><div class='add'>+	bool ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!pp_funcs || !pp_funcs-&gt;get_asic_baco_capability)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -204,12 +221,11 @@ bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='ctx'> </div><div class='del'>-	ret = pp_funcs-&gt;get_asic_baco_capability(pp_handle,</div><div class='del'>-						 &amp;baco_cap);</div><div class='add'>+	ret = pp_funcs-&gt;get_asic_baco_capability(pp_handle);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;adev-&gt;pm.mutex);</div><div class='ctx'> </div><div class='del'>-	return ret ? false : baco_cap;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)</div><div class='hunk'>@@ -600,6 +616,16 @@ void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> 			  enable ? "enable" : "disable", ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable);</div><div class='add'>+	if (ret)</div><div class='add'>+		DRM_ERROR("Dpm %s vpe failed, ret = %d.\n",</div><div class='add'>+			  enable ? "enable" : "disable", ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)</div><div class='ctx'> {</div><div class='ctx'> 	const struct amd_pm_funcs *pp_funcs = adev-&gt;powerplay.pp_funcs;</div><div class='hunk'>@@ -1301,6 +1327,23 @@ int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics,</div><div class='add'>+				  size_t size)</div><div class='add'>+{</div><div class='add'>+	const struct amd_pm_funcs *pp_funcs = adev-&gt;powerplay.pp_funcs;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!pp_funcs-&gt;get_pm_metrics)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;adev-&gt;pm.mutex);</div><div class='add'>+	ret = pp_funcs-&gt;get_pm_metrics(adev-&gt;powerplay.pp_handle, pm_metrics,</div><div class='add'>+				       size);</div><div class='add'>+	mutex_unlock(&amp;adev-&gt;pm.mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				    uint32_t *fan_mode)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br/>index ca2ece24e1e0..087d57850304 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/amdgpu_pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/amdgpu_pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/amdgpu_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/amdgpu_pm.c</a></div><div class='hunk'>@@ -1799,6 +1799,44 @@ static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev,</div><div class='add'>+					 struct amdgpu_device_attr *attr,</div><div class='add'>+					 uint32_t mask,</div><div class='add'>+					 enum amdgpu_device_attr_states *states)</div><div class='add'>+{</div><div class='add'>+	if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP)</div><div class='add'>+		*states = ATTR_STATE_UNSUPPORTED;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t amdgpu_get_pm_metrics(struct device *dev,</div><div class='add'>+				     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *ddev = dev_get_drvdata(dev);</div><div class='add'>+	struct amdgpu_device *adev = drm_to_adev(ddev);</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (amdgpu_in_reset(adev))</div><div class='add'>+		return -EPERM;</div><div class='add'>+	if (adev-&gt;in_suspend &amp;&amp; !adev-&gt;in_runpm)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_get_sync(ddev-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(ddev-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(ddev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * DOC: gpu_metrics</div><div class='ctx'>  *</div><div class='hunk'>@@ -2096,6 +2134,8 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {</div><div class='ctx'> 	AMDGPU_DEVICE_ATTR_RW(smartshift_bias,				ATTR_FLAG_BASIC,</div><div class='ctx'> 			      .attr_update = ss_bias_attr_update),</div><div class='ctx'> 	AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy,				ATTR_FLAG_BASIC),</div><div class='add'>+	AMDGPU_DEVICE_ATTR_RO(pm_metrics,				ATTR_FLAG_BASIC,</div><div class='add'>+			      .attr_update = amdgpu_pm_metrics_attr_update),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,</div><div class='hunk'>@@ -2128,7 +2168,9 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_</div><div class='ctx'> 		if (amdgpu_dpm_is_overdrive_supported(adev))</div><div class='ctx'> 			*states = ATTR_STATE_SUPPORTED;</div><div class='ctx'> 	} else if (DEVICE_ATTR_IS(mem_busy_percent)) {</div><div class='del'>-		if (adev-&gt;flags &amp; AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))</div><div class='add'>+		if ((adev-&gt;flags &amp; AMD_IS_APU &amp;&amp;</div><div class='add'>+		     gc_ver != IP_VERSION(9, 4, 3)) ||</div><div class='add'>+		    gc_ver == IP_VERSION(9, 0, 1))</div><div class='ctx'> 			*states = ATTR_STATE_UNSUPPORTED;</div><div class='ctx'> 	} else if (DEVICE_ATTR_IS(pcie_bw)) {</div><div class='ctx'> 		/* PCIe Perf counters won't work on APU nodes */</div><div class='hunk'>@@ -2198,10 +2240,10 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_</div><div class='ctx'> 	} else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {</div><div class='ctx'> 		if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE)</div><div class='ctx'> 			*states = ATTR_STATE_UNSUPPORTED;</div><div class='del'>-	} else if (DEVICE_ATTR_IS(pp_dpm_mclk_od)) {</div><div class='add'>+	} else if (DEVICE_ATTR_IS(pp_mclk_od)) {</div><div class='ctx'> 		if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)</div><div class='ctx'> 			*states = ATTR_STATE_UNSUPPORTED;</div><div class='del'>-	} else if (DEVICE_ATTR_IS(pp_dpm_sclk_od)) {</div><div class='add'>+	} else if (DEVICE_ATTR_IS(pp_sclk_od)) {</div><div class='ctx'> 		if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)</div><div class='ctx'> 			*states = ATTR_STATE_UNSUPPORTED;</div><div class='ctx'> 	} else if (DEVICE_ATTR_IS(apu_thermal_cap)) {</div><div class='hunk'>@@ -4307,11 +4349,19 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a</div><div class='ctx'> 	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&amp;value, &amp;size))</div><div class='ctx'> 		seq_printf(m, "\t%u mV (VDDNB)\n", value);</div><div class='ctx'> 	size = sizeof(uint32_t);</div><div class='del'>-	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&amp;query, &amp;size))</div><div class='del'>-		seq_printf(m, "\t%u.%02u W (average GPU)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&amp;query, &amp;size)) {</div><div class='add'>+		if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+			seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+		else</div><div class='add'>+			seq_printf(m, "\t%u.%02u W (average SoC)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+	}</div><div class='ctx'> 	size = sizeof(uint32_t);</div><div class='del'>-	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&amp;query, &amp;size))</div><div class='del'>-		seq_printf(m, "\t%u.%02u W (current GPU)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&amp;query, &amp;size)) {</div><div class='add'>+		if (adev-&gt;flags &amp; AMD_IS_APU)</div><div class='add'>+			seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+		else</div><div class='add'>+			seq_printf(m, "\t%u.%02u W (current SoC)\n", query &gt;&gt; 8, query &amp; 0xff);</div><div class='add'>+	}</div><div class='ctx'> 	size = sizeof(value);</div><div class='ctx'> 	seq_printf(m, "\n");</div><div class='ctx'> </div><div class='hunk'>@@ -4337,9 +4387,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a</div><div class='ctx'> 		/* VCN clocks */</div><div class='ctx'> 		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&amp;value, &amp;size)) {</div><div class='ctx'> 			if (!value) {</div><div class='del'>-				seq_printf(m, "VCN: Disabled\n");</div><div class='add'>+				seq_printf(m, "VCN: Powered down\n");</div><div class='ctx'> 			} else {</div><div class='del'>-				seq_printf(m, "VCN: Enabled\n");</div><div class='add'>+				seq_printf(m, "VCN: Powered up\n");</div><div class='ctx'> 				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&amp;value, &amp;size))</div><div class='ctx'> 					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);</div><div class='ctx'> 				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&amp;value, &amp;size))</div><div class='hunk'>@@ -4351,9 +4401,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a</div><div class='ctx'> 		/* UVD clocks */</div><div class='ctx'> 		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&amp;value, &amp;size)) {</div><div class='ctx'> 			if (!value) {</div><div class='del'>-				seq_printf(m, "UVD: Disabled\n");</div><div class='add'>+				seq_printf(m, "UVD: Powered down\n");</div><div class='ctx'> 			} else {</div><div class='del'>-				seq_printf(m, "UVD: Enabled\n");</div><div class='add'>+				seq_printf(m, "UVD: Powered up\n");</div><div class='ctx'> 				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&amp;value, &amp;size))</div><div class='ctx'> 					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);</div><div class='ctx'> 				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&amp;value, &amp;size))</div><div class='hunk'>@@ -4365,9 +4415,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a</div><div class='ctx'> 		/* VCE clocks */</div><div class='ctx'> 		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&amp;value, &amp;size)) {</div><div class='ctx'> 			if (!value) {</div><div class='del'>-				seq_printf(m, "VCE: Disabled\n");</div><div class='add'>+				seq_printf(m, "VCE: Powered down\n");</div><div class='ctx'> 			} else {</div><div class='del'>-				seq_printf(m, "VCE: Enabled\n");</div><div class='add'>+				seq_printf(m, "VCE: Powered up\n");</div><div class='ctx'> 				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&amp;value, &amp;size))</div><div class='ctx'> 					seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h<br/>index feccd2a7120d..3047ffe7f244 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h</a></div><div class='hunk'>@@ -415,6 +415,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);</div><div class='ctx'> int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,</div><div class='ctx'> 			     enum pp_mp1_state mp1_state);</div><div class='ctx'> </div><div class='add'>+int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en);</div><div class='add'>+</div><div class='ctx'> int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);</div><div class='ctx'> </div><div class='ctx'> int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);</div><div class='hunk'>@@ -443,6 +445,7 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);</div><div class='ctx'> void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);</div><div class='add'>+void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);</div><div class='ctx'> int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);</div><div class='ctx'> int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);</div><div class='hunk'>@@ -511,6 +514,18 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,</div><div class='ctx'> int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				      long *input, uint32_t size);</div><div class='ctx'> int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * @get_pm_metrics: Get one snapshot of power management metrics from PMFW. The</div><div class='add'>+ * sample is copied to pm_metrics buffer. It's expected to be allocated by the</div><div class='add'>+ * caller and size of the allocated buffer is passed. Max size expected for a</div><div class='add'>+ * metrics sample is 4096 bytes.</div><div class='add'>+ *</div><div class='add'>+ * Return: Actual size of the metrics sample</div><div class='add'>+ */</div><div class='add'>+ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics,</div><div class='add'>+				  size_t size);</div><div class='add'>+</div><div class='ctx'> int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,</div><div class='ctx'> 				    uint32_t *fan_mode);</div><div class='ctx'> int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c<br/>index 5d28c951a319..5cb4725c773f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c</a></div><div class='hunk'>@@ -2735,10 +2735,8 @@ static int kv_parse_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)</div><div class='ctx'> 			&amp;non_clock_info_array-&gt;nonClockInfo[non_clock_array_index];</div><div class='ctx'> 		ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);</div><div class='del'>-		if (ps == NULL) {</div><div class='del'>-			kfree(adev-&gt;pm.dpm.ps);</div><div class='add'>+		if (ps == NULL)</div><div class='ctx'> 			return -ENOMEM;</div><div class='del'>-		}</div><div class='ctx'> 		adev-&gt;pm.dpm.ps[i].ps_priv = ps;</div><div class='ctx'> 		k = 0;</div><div class='ctx'> 		idx = (u8 *)&amp;power_state-&gt;v2.clockInfoIndex[0];</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c<br/>index 81fb4e5dd804..60377747bab4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c</a></div><div class='hunk'>@@ -272,10 +272,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				 le16_to_cpu(power_info-&gt;pplib4.usVddcDependencyOnSCLKOffset));</div><div class='ctx'> 			ret = amdgpu_parse_clk_voltage_dep_table(&amp;adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_sclk,</div><div class='ctx'> 								 dep_table);</div><div class='del'>-			if (ret) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (ret)</div><div class='ctx'> 				return ret;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (power_info-&gt;pplib4.usVddciDependencyOnMCLKOffset) {</div><div class='ctx'> 			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)</div><div class='hunk'>@@ -283,10 +281,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				 le16_to_cpu(power_info-&gt;pplib4.usVddciDependencyOnMCLKOffset));</div><div class='ctx'> 			ret = amdgpu_parse_clk_voltage_dep_table(&amp;adev-&gt;pm.dpm.dyn_state.vddci_dependency_on_mclk,</div><div class='ctx'> 								 dep_table);</div><div class='del'>-			if (ret) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (ret)</div><div class='ctx'> 				return ret;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (power_info-&gt;pplib4.usVddcDependencyOnMCLKOffset) {</div><div class='ctx'> 			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)</div><div class='hunk'>@@ -294,10 +290,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				 le16_to_cpu(power_info-&gt;pplib4.usVddcDependencyOnMCLKOffset));</div><div class='ctx'> 			ret = amdgpu_parse_clk_voltage_dep_table(&amp;adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_mclk,</div><div class='ctx'> 								 dep_table);</div><div class='del'>-			if (ret) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (ret)</div><div class='ctx'> 				return ret;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (power_info-&gt;pplib4.usMvddDependencyOnMCLKOffset) {</div><div class='ctx'> 			dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)</div><div class='hunk'>@@ -305,10 +299,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				 le16_to_cpu(power_info-&gt;pplib4.usMvddDependencyOnMCLKOffset));</div><div class='ctx'> 			ret = amdgpu_parse_clk_voltage_dep_table(&amp;adev-&gt;pm.dpm.dyn_state.mvdd_dependency_on_mclk,</div><div class='ctx'> 								 dep_table);</div><div class='del'>-			if (ret) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (ret)</div><div class='ctx'> 				return ret;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (power_info-&gt;pplib4.usMaxClockVoltageOnDCOffset) {</div><div class='ctx'> 			ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =</div><div class='hunk'>@@ -339,10 +331,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				kcalloc(psl-&gt;ucNumEntries,</div><div class='ctx'> 					sizeof(struct amdgpu_phase_shedding_limits_entry),</div><div class='ctx'> 					GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.phase_shedding_limits_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.phase_shedding_limits_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> </div><div class='ctx'> 			entry = &amp;psl-&gt;entries[0];</div><div class='ctx'> 			for (i = 0; i &lt; psl-&gt;ucNumEntries; i++) {</div><div class='hunk'>@@ -383,10 +373,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 			ATOM_PPLIB_CAC_Leakage_Record *entry;</div><div class='ctx'> 			u32 size = cac_table-&gt;ucNumEntries * sizeof(struct amdgpu_cac_leakage_table);</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.cac_leakage_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.cac_leakage_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			entry = &amp;cac_table-&gt;entries[0];</div><div class='ctx'> 			for (i = 0; i &lt; cac_table-&gt;ucNumEntries; i++) {</div><div class='ctx'> 				if (adev-&gt;pm.dpm.platform_caps &amp; ATOM_PP_PLATFORM_CAP_EVV) {</div><div class='hunk'>@@ -438,10 +426,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				sizeof(struct amdgpu_vce_clock_voltage_dependency_entry);</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =</div><div class='ctx'> 				kzalloc(size, GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =</div><div class='ctx'> 				limits-&gt;numEntries;</div><div class='ctx'> 			entry = &amp;limits-&gt;entries[0];</div><div class='hunk'>@@ -493,10 +479,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry);</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =</div><div class='ctx'> 				kzalloc(size, GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =</div><div class='ctx'> 				limits-&gt;numEntries;</div><div class='ctx'> 			entry = &amp;limits-&gt;entries[0];</div><div class='hunk'>@@ -525,10 +509,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				sizeof(struct amdgpu_clock_voltage_dependency_entry);</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =</div><div class='ctx'> 				kzalloc(size, GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =</div><div class='ctx'> 				limits-&gt;numEntries;</div><div class='ctx'> 			entry = &amp;limits-&gt;entries[0];</div><div class='hunk'>@@ -548,10 +530,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				 le16_to_cpu(ext_hdr-&gt;usPPMTableOffset));</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.ppm_table =</div><div class='ctx'> 				kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.ppm_table) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.ppm_table)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.ppm_table-&gt;ppm_design = ppm-&gt;ucPpmDesign;</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.ppm_table-&gt;cpu_core_number =</div><div class='ctx'> 				le16_to_cpu(ppm-&gt;usCpuCoreNumber);</div><div class='hunk'>@@ -583,10 +563,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 				sizeof(struct amdgpu_clock_voltage_dependency_entry);</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =</div><div class='ctx'> 				kzalloc(size, GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =</div><div class='ctx'> 				limits-&gt;numEntries;</div><div class='ctx'> 			entry = &amp;limits-&gt;entries[0];</div><div class='hunk'>@@ -606,10 +584,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 			ATOM_PowerTune_Table *pt;</div><div class='ctx'> 			adev-&gt;pm.dpm.dyn_state.cac_tdp_table =</div><div class='ctx'> 				kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL);</div><div class='del'>-			if (!adev-&gt;pm.dpm.dyn_state.cac_tdp_table) {</div><div class='del'>-				amdgpu_free_extended_power_table(adev);</div><div class='add'>+			if (!adev-&gt;pm.dpm.dyn_state.cac_tdp_table)</div><div class='ctx'> 				return -ENOMEM;</div><div class='del'>-			}</div><div class='ctx'> 			if (rev &gt; 0) {</div><div class='ctx'> 				ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)</div><div class='ctx'> 					(mode_info-&gt;atom_context-&gt;bios + data_offset +</div><div class='hunk'>@@ -645,10 +621,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)</div><div class='ctx'> 			ret = amdgpu_parse_clk_voltage_dep_table(</div><div class='ctx'> 					&amp;adev-&gt;pm.dpm.dyn_state.vddgfx_dependency_on_sclk,</div><div class='ctx'> 					dep_table);</div><div class='del'>-			if (ret) {</div><div class='del'>-				kfree(adev-&gt;pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries);</div><div class='add'>+			if (ret)</div><div class='ctx'> 				return ret;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c<br/>index fc8e4ac6c8e7..df4f20293c16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c</a></div><div class='hunk'>@@ -7379,10 +7379,9 @@ static int si_dpm_init(struct amdgpu_device *adev)</div><div class='ctx'> 		kcalloc(4,</div><div class='ctx'> 			sizeof(struct amdgpu_clock_voltage_dependency_entry),</div><div class='ctx'> 			GFP_KERNEL);</div><div class='del'>-	if (!adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {</div><div class='del'>-		amdgpu_free_extended_power_table(adev);</div><div class='add'>+	if (!adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='add'>+</div><div class='ctx'> 	adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;</div><div class='ctx'> 	adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;</div><div class='ctx'> 	adev-&gt;pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c<br/>index 914c15387157..aed0e2cefbf9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c</a></div><div class='hunk'>@@ -1371,21 +1371,18 @@ static int pp_set_active_display_count(void *handle, uint32_t count)</div><div class='ctx'> 	return phm_set_active_display_count(hwmgr, count);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pp_get_asic_baco_capability(void *handle, bool *cap)</div><div class='add'>+static bool pp_get_asic_baco_capability(void *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct pp_hwmgr *hwmgr = handle;</div><div class='ctx'> </div><div class='del'>-	*cap = false;</div><div class='ctx'> 	if (!hwmgr)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (!(hwmgr-&gt;not_vf &amp;&amp; amdgpu_dpm) ||</div><div class='ctx'> 		!hwmgr-&gt;hwmgr_func-&gt;get_asic_baco_capability)</div><div class='del'>-		return 0;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	hwmgr-&gt;hwmgr_func-&gt;get_asic_baco_capability(hwmgr, cap);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return hwmgr-&gt;hwmgr_func-&gt;get_asic_baco_capability(hwmgr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int pp_get_asic_baco_state(void *handle, int *state)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c<br/>index f2a55c1413f5..17882f8dfdd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c</a></div><div class='hunk'>@@ -200,7 +200,7 @@ static int get_platform_power_management_table(</div><div class='ctx'> 		struct pp_hwmgr *hwmgr,</div><div class='ctx'> 		ATOM_Tonga_PPM_Table *atom_ppm_table)</div><div class='ctx'> {</div><div class='del'>-	struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_Tonga_PPM_Table), GFP_KERNEL);</div><div class='add'>+	struct phm_ppm_table *ptr = kzalloc(sizeof(*ptr), GFP_KERNEL);</div><div class='ctx'> 	struct phm_ppt_v1_information *pp_table_information =</div><div class='ctx'> 		(struct phm_ppt_v1_information *)(hwmgr-&gt;pptable);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c<br/>index 044cda005aed..e8a9471c1898 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c</a></div><div class='hunk'>@@ -33,21 +33,20 @@</div><div class='ctx'> #include "smu/smu_7_1_2_d.h"</div><div class='ctx'> #include "smu/smu_7_1_2_sh_mask.h"</div><div class='ctx'> </div><div class='del'>-int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)</div><div class='add'>+bool smu7_baco_get_capability(struct pp_hwmgr *hwmgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr-&gt;adev);</div><div class='ctx'> 	uint32_t reg;</div><div class='ctx'> </div><div class='del'>-	*cap = false;</div><div class='ctx'> 	if (!phm_cap_enabled(hwmgr-&gt;platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);</div><div class='ctx'> </div><div class='ctx'> 	if (reg &amp; CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)</div><div class='del'>-		*cap = true;</div><div class='add'>+		return true;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h<br/>index be0d98abb536..73a773f4ce2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #include "hwmgr.h"</div><div class='ctx'> #include "common_baco.h"</div><div class='ctx'> </div><div class='del'>-extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);</div><div class='add'>+extern bool smu7_baco_get_capability(struct pp_hwmgr *hwmgr);</div><div class='ctx'> extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);</div><div class='ctx'> extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br/>index 11372fcc59c8..aa91730e4eaf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c</a></div><div class='hunk'>@@ -2974,6 +2974,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)</div><div class='ctx'> 		result = smu7_get_evv_voltages(hwmgr);</div><div class='ctx'> 		if (result) {</div><div class='ctx'> 			pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");</div><div class='add'>+			kfree(hwmgr-&gt;backend);</div><div class='add'>+			hwmgr-&gt;backend = NULL;</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -3019,8 +3021,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	result = smu7_update_edc_leakage_table(hwmgr);</div><div class='del'>-	if (result)</div><div class='add'>+	if (result) {</div><div class='add'>+		smu7_hwmgr_backend_fini(hwmgr);</div><div class='ctx'> 		return result;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3995,6 +3999,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,</div><div class='ctx'> 	uint32_t sclk, mclk, activity_percent;</div><div class='ctx'> 	uint32_t offset, val_vid;</div><div class='ctx'> 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr-&gt;backend);</div><div class='add'>+	struct amdgpu_device *adev = hwmgr-&gt;adev;</div><div class='ctx'> </div><div class='ctx'> 	/* size must be at least 4 bytes for all sensors */</div><div class='ctx'> 	if (*size &lt; 4)</div><div class='hunk'>@@ -4038,7 +4043,21 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,</div><div class='ctx'> 		*size = 4;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:</div><div class='del'>-		return smu7_get_gpu_power(hwmgr, (uint32_t *)value);</div><div class='add'>+		if ((adev-&gt;asic_type != CHIP_HAWAII) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_BONAIRE) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_FIJI) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_TONGA))</div><div class='add'>+			return smu7_get_gpu_power(hwmgr, (uint32_t *)value);</div><div class='add'>+		else</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:</div><div class='add'>+		if ((adev-&gt;asic_type != CHIP_HAWAII) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_BONAIRE) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_FIJI) &amp;&amp;</div><div class='add'>+		    (adev-&gt;asic_type != CHIP_TONGA))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		else</div><div class='add'>+			return smu7_get_gpu_power(hwmgr, (uint32_t *)value);</div><div class='ctx'> 	case AMDGPU_PP_SENSOR_VDDGFX:</div><div class='ctx'> 		if ((data-&gt;vr_config &amp; VRCONF_VDDGFX_MASK) ==</div><div class='ctx'> 		    (VR_SVI2_PLANE_2 &lt;&lt; VRCONF_VDDGFX_SHIFT))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c<br/>index de0a37f7c632..c66ef9741535 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c</a></div><div class='hunk'>@@ -28,14 +28,13 @@</div><div class='ctx'> #include "vega10_inc.h"</div><div class='ctx'> #include "smu9_baco.h"</div><div class='ctx'> </div><div class='del'>-int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)</div><div class='add'>+bool smu9_baco_get_capability(struct pp_hwmgr *hwmgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr-&gt;adev);</div><div class='ctx'> 	uint32_t reg, data;</div><div class='ctx'> </div><div class='del'>-	*cap = false;</div><div class='ctx'> 	if (!phm_cap_enabled(hwmgr-&gt;platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))</div><div class='del'>-		return 0;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	WREG32(0x12074, 0xFFF0003B);</div><div class='ctx'> 	data = RREG32(0x12075);</div><div class='hunk'>@@ -44,10 +43,10 @@ int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)</div><div class='ctx'> 		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);</div><div class='ctx'> </div><div class='ctx'> 		if (reg &amp; RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)</div><div class='del'>-			*cap = true;</div><div class='add'>+			return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h<br/>index 84e90f801ac3..9ff7c2ea1b58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #include "hwmgr.h"</div><div class='ctx'> #include "common_baco.h"</div><div class='ctx'> </div><div class='del'>-extern int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);</div><div class='add'>+extern bool smu9_baco_get_capability(struct pp_hwmgr *hwmgr);</div><div class='ctx'> extern int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c<br/>index 994c0d374bfa..dad4c80aee58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c</a></div><div class='hunk'>@@ -36,23 +36,22 @@ static const struct soc15_baco_cmd_entry clean_baco_tbl[] = {</div><div class='ctx'> 	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)</div><div class='add'>+bool vega20_baco_get_capability(struct pp_hwmgr *hwmgr)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr-&gt;adev);</div><div class='ctx'> 	uint32_t reg;</div><div class='ctx'> </div><div class='del'>-	*cap = false;</div><div class='ctx'> 	if (!phm_cap_enabled(hwmgr-&gt;platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))</div><div class='del'>-		return 0;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (((RREG32(0x17569) &amp; 0x20000000) &gt;&gt; 29) == 0x1) {</div><div class='ctx'> 		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);</div><div class='ctx'> </div><div class='ctx'> 		if (reg &amp; RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)</div><div class='del'>-			*cap = true;</div><div class='add'>+			return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h<br/>index f06471e712dc..bdad9c915631 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #include "hwmgr.h"</div><div class='ctx'> #include "common_baco.h"</div><div class='ctx'> </div><div class='del'>-extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);</div><div class='add'>+extern bool vega20_baco_get_capability(struct pp_hwmgr *hwmgr);</div><div class='ctx'> extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);</div><div class='ctx'> extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);</div><div class='ctx'> extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h<br/>index 81650727a5de..6f536159df4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h</a></div><div class='hunk'>@@ -351,7 +351,7 @@ struct pp_hwmgr_func {</div><div class='ctx'> 	int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);</div><div class='ctx'> 	int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);</div><div class='ctx'> 	int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);</div><div class='del'>-	int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);</div><div class='add'>+	bool (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr);</div><div class='ctx'> 	int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);</div><div class='ctx'> 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);</div><div class='ctx'> 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c<br/>index 9e4228232f02..ad1fd3150d03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c</a></div><div class='hunk'>@@ -2298,6 +2298,7 @@ static uint32_t ci_get_mac_definition(uint32_t value)</div><div class='ctx'> 	case SMU_MAX_ENTRIES_SMIO:</div><div class='ctx'> 		return SMU7_MAX_ENTRIES_SMIO;</div><div class='ctx'> 	case SMU_MAX_LEVELS_VDDC:</div><div class='add'>+	case SMU_MAX_LEVELS_VDDGFX:</div><div class='ctx'> 		return SMU7_MAX_LEVELS_VDDC;</div><div class='ctx'> 	case SMU_MAX_LEVELS_VDDCI:</div><div class='ctx'> 		return SMU7_MAX_LEVELS_VDDCI;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c<br/>index 97d9802fe673..17d2f5bff4a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c</a></div><div class='hunk'>@@ -2263,6 +2263,7 @@ static uint32_t iceland_get_mac_definition(uint32_t value)</div><div class='ctx'> 	case SMU_MAX_ENTRIES_SMIO:</div><div class='ctx'> 		return SMU71_MAX_ENTRIES_SMIO;</div><div class='ctx'> 	case SMU_MAX_LEVELS_VDDC:</div><div class='add'>+	case SMU_MAX_LEVELS_VDDGFX:</div><div class='ctx'> 		return SMU71_MAX_LEVELS_VDDC;</div><div class='ctx'> 	case SMU_MAX_LEVELS_VDDCI:</div><div class='ctx'> 		return SMU71_MAX_LEVELS_VDDCI;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br/>index 1ead323f1c78..c16703868e5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c</a></div><div class='hunk'>@@ -1322,6 +1322,187 @@ static int smu_get_thermal_temperature_range(struct smu_context *smu)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges</div><div class='add'>+ *</div><div class='add'>+ * @smu: smu_context pointer</div><div class='add'>+ *</div><div class='add'>+ * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling.</div><div class='add'>+ * Returns 0 on success, error on failure.</div><div class='add'>+ */</div><div class='add'>+static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	struct wbrf_ranges_in_out wbrf_exclusion = {0};</div><div class='add'>+	struct freq_band_range *wifi_bands = wbrf_exclusion.band_list;</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='add'>+	uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES;</div><div class='add'>+	uint64_t start, end;</div><div class='add'>+	int ret, i, j;</div><div class='add'>+</div><div class='add'>+	ret = amd_wbrf_retrieve_freq_band(adev-&gt;dev, &amp;wbrf_exclusion);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Failed to retrieve exclusion ranges!\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The exclusion ranges array we got might be filled with holes and duplicate</div><div class='add'>+	 * entries. For example:</div><div class='add'>+	 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...}</div><div class='add'>+	 * We need to do some sortups to eliminate those holes and duplicate entries.</div><div class='add'>+	 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...}</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; num_of_wbrf_ranges; i++) {</div><div class='add'>+		start = wifi_bands[i].start;</div><div class='add'>+		end = wifi_bands[i].end;</div><div class='add'>+</div><div class='add'>+		/* get the last valid entry to fill the intermediate hole */</div><div class='add'>+		if (!start &amp;&amp; !end) {</div><div class='add'>+			for (j = num_of_wbrf_ranges - 1; j &gt; i; j--)</div><div class='add'>+				if (wifi_bands[j].start &amp;&amp; wifi_bands[j].end)</div><div class='add'>+					break;</div><div class='add'>+</div><div class='add'>+			/* no valid entry left */</div><div class='add'>+			if (j &lt;= i)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			start = wifi_bands[i].start = wifi_bands[j].start;</div><div class='add'>+			end = wifi_bands[i].end = wifi_bands[j].end;</div><div class='add'>+			wifi_bands[j].start = 0;</div><div class='add'>+			wifi_bands[j].end = 0;</div><div class='add'>+			num_of_wbrf_ranges = j;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* eliminate duplicate entries */</div><div class='add'>+		for (j = i + 1; j &lt; num_of_wbrf_ranges; j++) {</div><div class='add'>+			if ((wifi_bands[j].start == start) &amp;&amp; (wifi_bands[j].end == end)) {</div><div class='add'>+				wifi_bands[j].start = 0;</div><div class='add'>+				wifi_bands[j].end = 0;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Send the sorted wifi_bands to PMFW */</div><div class='add'>+	ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);</div><div class='add'>+	/* Try to set the wifi_bands again */</div><div class='add'>+	if (unlikely(ret == -EBUSY)) {</div><div class='add'>+		mdelay(5);</div><div class='add'>+		ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_event_handler - handle notify events</div><div class='add'>+ *</div><div class='add'>+ * @nb: notifier block</div><div class='add'>+ * @action: event type</div><div class='add'>+ * @_arg: event data</div><div class='add'>+ *</div><div class='add'>+ * Calls relevant amdgpu function in response to wbrf event</div><div class='add'>+ * notification from kernel.</div><div class='add'>+ */</div><div class='add'>+static int smu_wbrf_event_handler(struct notifier_block *nb,</div><div class='add'>+				  unsigned long action, void *_arg)</div><div class='add'>+{</div><div class='add'>+	struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier);</div><div class='add'>+</div><div class='add'>+	switch (action) {</div><div class='add'>+	case WBRF_CHANGED:</div><div class='add'>+		schedule_delayed_work(&amp;smu-&gt;wbrf_delayed_work,</div><div class='add'>+				      msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NOTIFY_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_delayed_work_handler - callback on delayed work timer expired</div><div class='add'>+ *</div><div class='add'>+ * @work: struct work_struct pointer</div><div class='add'>+ *</div><div class='add'>+ * Flood is over and driver will consume the latest exclusion ranges.</div><div class='add'>+ */</div><div class='add'>+static void smu_wbrf_delayed_work_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work);</div><div class='add'>+</div><div class='add'>+	smu_wbrf_handle_exclusion_ranges(smu);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_support_check - check wbrf support</div><div class='add'>+ *</div><div class='add'>+ * @smu: smu_context pointer</div><div class='add'>+ *</div><div class='add'>+ * Verifies the ACPI interface whether wbrf is supported.</div><div class='add'>+ */</div><div class='add'>+static void smu_wbrf_support_check(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='add'>+</div><div class='add'>+	smu-&gt;wbrf_supported = smu_is_asic_wbrf_supported(smu) &amp;&amp; amdgpu_wbrf &amp;&amp;</div><div class='add'>+							acpi_amd_wbrf_supported_consumer(adev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (smu-&gt;wbrf_supported)</div><div class='add'>+		dev_info(adev-&gt;dev, "RF interference mitigation is supported\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_init - init driver wbrf support</div><div class='add'>+ *</div><div class='add'>+ * @smu: smu_context pointer</div><div class='add'>+ *</div><div class='add'>+ * Verifies the AMD ACPI interfaces and registers with the wbrf</div><div class='add'>+ * notifier chain if wbrf feature is supported.</div><div class='add'>+ * Returns 0 on success, error on failure.</div><div class='add'>+ */</div><div class='add'>+static int smu_wbrf_init(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!smu-&gt;wbrf_supported)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	INIT_DELAYED_WORK(&amp;smu-&gt;wbrf_delayed_work, smu_wbrf_delayed_work_handler);</div><div class='add'>+</div><div class='add'>+	smu-&gt;wbrf_notifier.notifier_call = smu_wbrf_event_handler;</div><div class='add'>+	ret = amd_wbrf_register_notifier(&amp;smu-&gt;wbrf_notifier);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Some wifiband exclusion ranges may be already there</div><div class='add'>+	 * before our driver loaded. To make sure our driver</div><div class='add'>+	 * is awared of those exclusion ranges.</div><div class='add'>+	 */</div><div class='add'>+	schedule_delayed_work(&amp;smu-&gt;wbrf_delayed_work,</div><div class='add'>+			      msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * smu_wbrf_fini - tear down driver wbrf support</div><div class='add'>+ *</div><div class='add'>+ * @smu: smu_context pointer</div><div class='add'>+ *</div><div class='add'>+ * Unregisters with the wbrf notifier chain.</div><div class='add'>+ */</div><div class='add'>+static void smu_wbrf_fini(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	if (!smu-&gt;wbrf_supported)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	amd_wbrf_unregister_notifier(&amp;smu-&gt;wbrf_notifier);</div><div class='add'>+</div><div class='add'>+	cancel_delayed_work_sync(&amp;smu-&gt;wbrf_delayed_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int smu_smc_hw_setup(struct smu_context *smu)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_feature *feature = &amp;smu-&gt;smu_feature;</div><div class='hunk'>@@ -1414,6 +1595,15 @@ static int smu_smc_hw_setup(struct smu_context *smu)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	/* Enable UclkShadow on wbrf supported */</div><div class='add'>+	if (smu-&gt;wbrf_supported) {</div><div class='add'>+		ret = smu_enable_uclk_shadow(smu, true);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(adev-&gt;dev, "Failed to enable UclkShadow feature to support wbrf!\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * With SCPM enabled, these actions(and relevant messages) are</div><div class='ctx'> 	 * not needed and permitted.</div><div class='hunk'>@@ -1512,6 +1702,15 @@ static int smu_smc_hw_setup(struct smu_context *smu)</div><div class='ctx'> 	 */</div><div class='ctx'> 	ret = smu_set_min_dcef_deep_sleep(smu,</div><div class='ctx'> 					  smu-&gt;smu_table.boot_values.dcefclk / 100);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Error setting min deepsleep dcefclk\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Init wbrf support. Properly setup the notifier */</div><div class='add'>+	ret = smu_wbrf_init(smu);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(adev-&gt;dev, "Error during wbrf init call\n");</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1567,6 +1766,13 @@ static int smu_hw_init(void *handle)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Check whether wbrf is supported. This needs to be done</div><div class='add'>+	 * before SMU setup starts since part of SMU configuration</div><div class='add'>+	 * relies on this.</div><div class='add'>+	 */</div><div class='add'>+	smu_wbrf_support_check(smu);</div><div class='add'>+</div><div class='ctx'> 	if (smu-&gt;is_apu) {</div><div class='ctx'> 		ret = smu_set_gfx_imu_enable(smu);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -1710,6 +1916,16 @@ static int smu_disable_dpms(struct smu_context *smu)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Notify SMU RLC is going to be off, stop RLC and SMU interaction.</div><div class='add'>+	 * otherwise SMU will hang while interacting with RLC if RLC is halted</div><div class='add'>+	 * this is a WA for Vangogh asic which fix the SMU hang issue.</div><div class='add'>+	 */</div><div class='add'>+	ret = smu_notify_rlc_state(smu, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(adev-&gt;dev, "Fail to notify rlc status!\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (amdgpu_ip_version(adev, GC_HWIP, 0) &gt;= IP_VERSION(9, 4, 2) &amp;&amp;</div><div class='ctx'> 	    !((adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; adev-&gt;gfx.imu.funcs) &amp;&amp;</div><div class='ctx'> 	    !amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;gfx.rlc.funcs-&gt;stop)</div><div class='hunk'>@@ -1723,6 +1939,8 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	smu_wbrf_fini(smu);</div><div class='add'>+</div><div class='ctx'> 	cancel_work_sync(&amp;smu-&gt;throttling_logging_work);</div><div class='ctx'> 	cancel_work_sync(&amp;smu-&gt;interrupt_work);</div><div class='ctx'> </div><div class='hunk'>@@ -3005,19 +3223,17 @@ static int smu_set_xgmi_pstate(void *handle,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int smu_get_baco_capability(void *handle, bool *cap)</div><div class='add'>+static bool smu_get_baco_capability(void *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_context *smu = handle;</div><div class='ctx'> </div><div class='del'>-	*cap = false;</div><div class='del'>-</div><div class='ctx'> 	if (!smu-&gt;pm_enabled)</div><div class='del'>-		return 0;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	if (smu-&gt;ppt_funcs &amp;&amp; smu-&gt;ppt_funcs-&gt;baco_is_support)</div><div class='del'>-		*cap = smu-&gt;ppt_funcs-&gt;baco_is_support(smu);</div><div class='add'>+	if (!smu-&gt;ppt_funcs || !smu-&gt;ppt_funcs-&gt;baco_is_support)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return smu-&gt;ppt_funcs-&gt;baco_is_support(smu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int smu_baco_set_state(void *handle, int state)</div><div class='hunk'>@@ -3191,6 +3407,20 @@ static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)</div><div class='ctx'> 	return smu-&gt;ppt_funcs-&gt;get_gpu_metrics(smu, table);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics,</div><div class='add'>+				      size_t size)</div><div class='add'>+{</div><div class='add'>+	struct smu_context *smu = handle;</div><div class='add'>+</div><div class='add'>+	if (!smu-&gt;pm_enabled || !smu-&gt;adev-&gt;pm.dpm_enabled)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (!smu-&gt;ppt_funcs-&gt;get_pm_metrics)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return smu-&gt;ppt_funcs-&gt;get_pm_metrics(smu, pm_metrics, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int smu_enable_mgpu_fan_boost(void *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_context *smu = handle;</div><div class='hunk'>@@ -3332,6 +3562,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {</div><div class='ctx'> 	.set_df_cstate                    = smu_set_df_cstate,</div><div class='ctx'> 	.set_xgmi_pstate                  = smu_set_xgmi_pstate,</div><div class='ctx'> 	.get_gpu_metrics                  = smu_sys_get_gpu_metrics,</div><div class='add'>+	.get_pm_metrics                   = smu_sys_get_pm_metrics,</div><div class='ctx'> 	.set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,</div><div class='ctx'> 	.display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,</div><div class='ctx'> 	.get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h<br/>index 8def291b18bc..2aa4fea87314 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h</a></div><div class='hunk'>@@ -22,6 +22,9 @@</div><div class='ctx'> #ifndef __AMDGPU_SMU_H__</div><div class='ctx'> #define __AMDGPU_SMU_H__</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/acpi_amd_wbrf.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "amdgpu.h"</div><div class='ctx'> #include "kgd_pp_interface.h"</div><div class='ctx'> #include "dm_pp_interface.h"</div><div class='hunk'>@@ -253,6 +256,7 @@ struct smu_table {</div><div class='ctx'> 	uint64_t mc_address;</div><div class='ctx'> 	void *cpu_addr;</div><div class='ctx'> 	struct amdgpu_bo *bo;</div><div class='add'>+	uint32_t version;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum smu_perf_level_designation {</div><div class='hunk'>@@ -317,6 +321,7 @@ enum smu_table_id {</div><div class='ctx'> 	SMU_TABLE_PACE,</div><div class='ctx'> 	SMU_TABLE_ECCINFO,</div><div class='ctx'> 	SMU_TABLE_COMBO_PPTABLE,</div><div class='add'>+	SMU_TABLE_WIFIBAND,</div><div class='ctx'> 	SMU_TABLE_COUNT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -470,6 +475,12 @@ struct stb_context {</div><div class='ctx'> </div><div class='ctx'> #define WORKLOAD_POLICY_MAX 7</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Configure wbrf event handling pace as there can be only one</div><div class='add'>+ * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms.</div><div class='add'>+ */</div><div class='add'>+#define SMU_WBRF_EVENT_HANDLING_PACE	10</div><div class='add'>+</div><div class='ctx'> struct smu_context {</div><div class='ctx'> 	struct amdgpu_device            *adev;</div><div class='ctx'> 	struct amdgpu_irq_src		irq_source;</div><div class='hunk'>@@ -569,6 +580,11 @@ struct smu_context {</div><div class='ctx'> 	struct delayed_work		swctf_delayed_work;</div><div class='ctx'> </div><div class='ctx'> 	enum pp_xgmi_plpd_mode plpd_mode;</div><div class='add'>+</div><div class='add'>+	/* data structures for wbrf feature support */</div><div class='add'>+	bool				wbrf_supported;</div><div class='add'>+	struct notifier_block		wbrf_notifier;</div><div class='add'>+	struct delayed_work		wbrf_delayed_work;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct i2c_adapter;</div><div class='hunk'>@@ -1253,6 +1269,15 @@ struct pptable_funcs {</div><div class='ctx'> 	ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * @get_pm_metrics: Get one snapshot of power management metrics from</div><div class='add'>+	 * PMFW.</div><div class='add'>+	 *</div><div class='add'>+	 * Return: Size of the metrics sample</div><div class='add'>+	 */</div><div class='add'>+	ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics,</div><div class='add'>+				  size_t size);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.</div><div class='ctx'> 	 */</div><div class='ctx'> 	int (*enable_mgpu_fan_boost)(struct smu_context *smu);</div><div class='hunk'>@@ -1360,6 +1385,27 @@ struct pptable_funcs {</div><div class='ctx'> 	 *                       management.</div><div class='ctx'> 	 */</div><div class='ctx'> 	int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @notify_rlc_state: Notify RLC power state to SMU.</div><div class='add'>+	 */</div><div class='add'>+	int (*notify_rlc_state)(struct smu_context *smu, bool en);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature</div><div class='add'>+	 */</div><div class='add'>+	bool (*is_asic_wbrf_supported)(struct smu_context *smu);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported</div><div class='add'>+	 */</div><div class='add'>+	int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied</div><div class='add'>+	 */</div><div class='add'>+	int (*set_wbrf_exclusion_ranges)(struct smu_context *smu,</div><div class='add'>+					struct freq_band_range *exclusion_ranges);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> typedef enum {</div><div class='hunk'>@@ -1403,6 +1449,16 @@ typedef enum {</div><div class='ctx'> 	METRICS_PCIE_WIDTH,</div><div class='ctx'> 	METRICS_CURR_FANPWM,</div><div class='ctx'> 	METRICS_CURR_SOCKETPOWER,</div><div class='add'>+	METRICS_AVERAGE_VPECLK,</div><div class='add'>+	METRICS_AVERAGE_IPUCLK,</div><div class='add'>+	METRICS_AVERAGE_MPIPUCLK,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_PROCHOT,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_SPL,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_FPPT,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_SPPT,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_THM_CORE,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_THM_GFX,</div><div class='add'>+	METRICS_THROTTLER_RESIDENCY_THM_SOC,</div><div class='ctx'> } MetricsMember_t;</div><div class='ctx'> </div><div class='ctx'> enum smu_cmn2asic_mapping_type {</div><div class='hunk'>@@ -1476,6 +1532,17 @@ enum smu_baco_seq {</div><div class='ctx'> 			 __dst_size);					   \</div><div class='ctx'> })</div><div class='ctx'> </div><div class='add'>+typedef struct {</div><div class='add'>+	uint16_t     LowFreq;</div><div class='add'>+	uint16_t     HighFreq;</div><div class='add'>+} WifiOneBand_t;</div><div class='add'>+</div><div class='add'>+typedef struct {</div><div class='add'>+	uint32_t		WifiBandEntryNum;</div><div class='add'>+	WifiOneBand_t	WifiBandEntry[11];</div><div class='add'>+	uint32_t		MmHubPadding[8];</div><div class='add'>+} WifiBandEntryTable_t;</div><div class='add'>+</div><div class='ctx'> #if !defined(SWSMU_CODE_LAYER_L2) &amp;&amp; !defined(SWSMU_CODE_LAYER_L3) &amp;&amp; !defined(SWSMU_CODE_LAYER_L4)</div><div class='ctx'> int smu_get_power_limit(void *handle,</div><div class='ctx'> 			uint32_t *limit,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h<br/>index 9dd1ed5b8940..b114d14fc053 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h</a></div><div class='hunk'>@@ -1615,7 +1615,8 @@ typedef struct {</div><div class='ctx'> #define TABLE_I2C_COMMANDS            9</div><div class='ctx'> #define TABLE_DRIVER_INFO             10</div><div class='ctx'> #define TABLE_ECCINFO                 11</div><div class='del'>-#define TABLE_COUNT                   12</div><div class='add'>+#define TABLE_WIFIBAND                12</div><div class='add'>+#define TABLE_COUNT                   13</div><div class='ctx'> </div><div class='ctx'> //IH Interupt ID</div><div class='ctx'> #define IH_INTERRUPT_ID_TO_DRIVER                   0xFE</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h<br/>index 62b7c0daff68..8b1496f8ce58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h</a></div><div class='hunk'>@@ -1605,7 +1605,8 @@ typedef struct {</div><div class='ctx'> #define TABLE_I2C_COMMANDS            9</div><div class='ctx'> #define TABLE_DRIVER_INFO             10</div><div class='ctx'> #define TABLE_ECCINFO                 11</div><div class='del'>-#define TABLE_COUNT                   12</div><div class='add'>+#define TABLE_WIFIBAND                12</div><div class='add'>+#define TABLE_COUNT                   13</div><div class='ctx'> </div><div class='ctx'> //IH Interupt ID</div><div class='ctx'> #define IH_INTERRUPT_ID_TO_DRIVER                   0xFE</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h<br/>index 22f88842a7fd..5bb7a63c0602 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h</a></div><div class='hunk'>@@ -24,11 +24,6 @@</div><div class='ctx'> #ifndef SMU14_DRIVER_IF_V14_0_0_H</div><div class='ctx'> #define SMU14_DRIVER_IF_V14_0_0_H</div><div class='ctx'> </div><div class='del'>-// *** IMPORTANT ***</div><div class='del'>-// SMU TEAM: Always increment the interface version if</div><div class='del'>-// any structure is changed in this file</div><div class='del'>-#define PMFW_DRIVER_IF_VERSION 6</div><div class='del'>-</div><div class='ctx'> typedef struct {</div><div class='ctx'>   int32_t value;</div><div class='ctx'>   uint32_t numFractionalBits;</div><div class='hunk'>@@ -150,37 +145,50 @@ typedef struct {</div><div class='ctx'> } DpmClocks_t;</div><div class='ctx'> </div><div class='ctx'> typedef struct {</div><div class='del'>-  uint16_t CoreFrequency[16];        //Target core frequency [MHz]</div><div class='del'>-  uint16_t CorePower[16];            //CAC calculated core power [mW]</div><div class='del'>-  uint16_t CoreTemperature[16];      //TSEN measured core temperature [centi-C]</div><div class='del'>-  uint16_t GfxTemperature;           //TSEN measured GFX temperature [centi-C]</div><div class='del'>-  uint16_t SocTemperature;           //TSEN measured SOC temperature [centi-C]</div><div class='del'>-  uint16_t StapmOpnLimit;            //Maximum IRM defined STAPM power limit [mW]</div><div class='del'>-  uint16_t StapmCurrentLimit;        //Time filtered STAPM power limit [mW]</div><div class='del'>-  uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]</div><div class='del'>-  uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]</div><div class='del'>-  uint16_t SkinTemp;                 //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]</div><div class='del'>-  uint16_t GfxclkFrequency;          //Time filtered target GFXCLK frequency [MHz]</div><div class='del'>-  uint16_t FclkFrequency;            //Time filtered target FCLK frequency [MHz]</div><div class='del'>-  uint16_t GfxActivity;              //Time filtered GFX busy % [0-100]</div><div class='del'>-  uint16_t SocclkFrequency;          //Time filtered target SOCCLK frequency [MHz]</div><div class='del'>-  uint16_t VclkFrequency;            //Time filtered target VCLK frequency [MHz]</div><div class='del'>-  uint16_t VcnActivity;              //Time filtered VCN busy % [0-100]</div><div class='del'>-  uint16_t VpeclkFrequency;          //Time filtered target VPECLK frequency [MHz]</div><div class='del'>-  uint16_t IpuclkFrequency;          //Time filtered target IPUCLK frequency [MHz]</div><div class='del'>-  uint16_t IpuBusy[8];               //Time filtered IPU per-column busy % [0-100]</div><div class='del'>-  uint16_t DRAMReads;                //Time filtered DRAM read bandwidth [MB/sec]</div><div class='del'>-  uint16_t DRAMWrites;               //Time filtered DRAM write bandwidth [MB/sec]</div><div class='del'>-  uint16_t CoreC0Residency[16];      //Time filtered per-core C0 residency % [0-100]</div><div class='del'>-  uint16_t IpuPower;                 //Time filtered IPU power [mW]</div><div class='del'>-  uint32_t ApuPower;                 //Time filtered APU power [mW]</div><div class='del'>-  uint32_t GfxPower;                 //Time filtered GFX power [mW]</div><div class='del'>-  uint32_t dGpuPower;                //Time filtered dGPU power [mW]</div><div class='del'>-  uint32_t SocketPower;              //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]</div><div class='del'>-  uint32_t AllCorePower;             //Time filtered sum of core power across all cores in the socket [mW]</div><div class='del'>-  uint32_t FilterAlphaValue;         //Metrics table alpha filter time constant [us]</div><div class='del'>-  uint32_t MetricsCounter;           //Counter that is incremented on every metrics table update [PM_TIMER cycles]</div><div class='del'>-  uint32_t spare[16];</div><div class='add'>+  uint16_t CoreFrequency[16];          //Target core frequency [MHz]</div><div class='add'>+  uint16_t CorePower[16];              //CAC calculated core power [mW]</div><div class='add'>+  uint16_t CoreTemperature[16];        //TSEN measured core temperature [centi-C]</div><div class='add'>+  uint16_t GfxTemperature;             //TSEN measured GFX temperature [centi-C]</div><div class='add'>+  uint16_t SocTemperature;             //TSEN measured SOC temperature [centi-C]</div><div class='add'>+  uint16_t StapmOpnLimit;              //Maximum IRM defined STAPM power limit [mW]</div><div class='add'>+  uint16_t StapmCurrentLimit;          //Time filtered STAPM power limit [mW]</div><div class='add'>+  uint16_t InfrastructureCpuMaxFreq;   //CCLK frequency limit enforced on classic cores [MHz]</div><div class='add'>+  uint16_t InfrastructureGfxMaxFreq;   //GFXCLK frequency limit enforced on GFX [MHz]</div><div class='add'>+  uint16_t SkinTemp;                   //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C]</div><div class='add'>+  uint16_t GfxclkFrequency;            //Time filtered target GFXCLK frequency [MHz]</div><div class='add'>+  uint16_t FclkFrequency;              //Time filtered target FCLK frequency [MHz]</div><div class='add'>+  uint16_t GfxActivity;                //Time filtered GFX busy % [0-100]</div><div class='add'>+  uint16_t SocclkFrequency;            //Time filtered target SOCCLK frequency [MHz]</div><div class='add'>+  uint16_t VclkFrequency;              //Time filtered target VCLK frequency [MHz]</div><div class='add'>+  uint16_t VcnActivity;                //Time filtered VCN busy % [0-100]</div><div class='add'>+  uint16_t VpeclkFrequency;            //Time filtered target VPECLK frequency [MHz]</div><div class='add'>+  uint16_t IpuclkFrequency;            //Time filtered target IPUCLK frequency [MHz]</div><div class='add'>+  uint16_t IpuBusy[8];                 //Time filtered IPU per-column busy % [0-100]</div><div class='add'>+  uint16_t DRAMReads;                  //Time filtered DRAM read bandwidth [MB/sec]</div><div class='add'>+  uint16_t DRAMWrites;                 //Time filtered DRAM write bandwidth [MB/sec]</div><div class='add'>+  uint16_t CoreC0Residency[16];        //Time filtered per-core C0 residency % [0-100]</div><div class='add'>+  uint16_t IpuPower;                   //Time filtered IPU power [mW]</div><div class='add'>+  uint32_t ApuPower;                   //Time filtered APU power [mW]</div><div class='add'>+  uint32_t GfxPower;                   //Time filtered GFX power [mW]</div><div class='add'>+  uint32_t dGpuPower;                  //Time filtered dGPU power [mW]</div><div class='add'>+  uint32_t SocketPower;                //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]</div><div class='add'>+  uint32_t AllCorePower;               //Time filtered sum of core power across all cores in the socket [mW]</div><div class='add'>+  uint32_t FilterAlphaValue;           //Metrics table alpha filter time constant [us]</div><div class='add'>+  uint32_t MetricsCounter;             //Counter that is incremented on every metrics table update [PM_TIMER cycles]</div><div class='add'>+  uint16_t MemclkFrequency;            //Time filtered target MEMCLK frequency [MHz]</div><div class='add'>+  uint16_t MpipuclkFrequency;          //Time filtered target MPIPUCLK frequency [MHz]</div><div class='add'>+  uint16_t IpuReads;                   //Time filtered IPU read bandwidth [MB/sec]</div><div class='add'>+  uint16_t IpuWrites;                  //Time filtered IPU write bandwidth [MB/sec]</div><div class='add'>+  uint32_t ThrottleResidency_PROCHOT;  //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_SPL;      //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_FPPT;     //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_SPPT;     //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_THM_CORE; //Counter that is incremented on every metrics table update when CORE thermal throttling was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_THM_GFX;  //Counter that is incremented on every metrics table update when GFX thermal throttling was engaged [PM_TIMER cycles]</div><div class='add'>+  uint32_t ThrottleResidency_THM_SOC;  //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles]</div><div class='add'>+  uint16_t Psys;                       //Time filtered Psys power [mW]</div><div class='add'>+  uint16_t spare1;</div><div class='add'>+  uint32_t spare[6];</div><div class='ctx'> } SmuMetrics_t;</div><div class='ctx'> </div><div class='ctx'> //ISP tile definitions</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h<br/>index e2ee855c7748..e862d323caab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h</a></div><div class='hunk'>@@ -138,10 +138,9 @@</div><div class='ctx'> #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A</div><div class='ctx'> #define PPSMC_MSG_SetPriorityDeltaGain           0x4B</div><div class='ctx'> #define PPSMC_MSG_AllowIHHostInterrupt           0x4C</div><div class='del'>-</div><div class='ctx'> #define PPSMC_MSG_DALNotPresent                  0x4E</div><div class='del'>-</div><div class='del'>-#define PPSMC_Message_Count                      0x4F</div><div class='add'>+#define PPSMC_MSG_EnableUCLKShadow               0x51</div><div class='add'>+#define PPSMC_Message_Count                      0x52</div><div class='ctx'> </div><div class='ctx'> //Debug Dump Message</div><div class='ctx'> #define DEBUGSMC_MSG_TestMessage                    0x1</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h<br/>index fef2d290f3f2..7b812b9994d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h</a></div><div class='hunk'>@@ -123,7 +123,7 @@ typedef enum {</div><div class='ctx'>   VOLTAGE_GUARDBAND_COUNT</div><div class='ctx'> } GFX_GUARDBAND_e;</div><div class='ctx'> </div><div class='del'>-#define SMU_METRICS_TABLE_VERSION 0x9</div><div class='add'>+#define SMU_METRICS_TABLE_VERSION 0xB</div><div class='ctx'> </div><div class='ctx'> typedef struct __attribute__((packed, aligned(4))) {</div><div class='ctx'>   uint32_t AccumulationCounter;</div><div class='hunk'>@@ -219,7 +219,103 @@ typedef struct __attribute__((packed, aligned(4))) {</div><div class='ctx'>   uint32_t PCIenReplayARolloverCountAcc;  // The Pcie counter itself is accumulated</div><div class='ctx'>   uint32_t PCIeNAKSentCountAcc;           // The Pcie counter itself is accumulated</div><div class='ctx'>   uint32_t PCIeNAKReceivedCountAcc;       // The Pcie counter itself is accumulated</div><div class='del'>-} MetricsTable_t;</div><div class='add'>+</div><div class='add'>+  // VCN/JPEG ACTIVITY</div><div class='add'>+  uint32_t VcnBusy[4];</div><div class='add'>+  uint32_t JpegBusy[32];</div><div class='add'>+} MetricsTableX_t;</div><div class='add'>+</div><div class='add'>+typedef struct __attribute__((packed, aligned(4))) {</div><div class='add'>+  uint32_t AccumulationCounter;</div><div class='add'>+</div><div class='add'>+  //TEMPERATURE</div><div class='add'>+  uint32_t MaxSocketTemperature;</div><div class='add'>+  uint32_t MaxVrTemperature;</div><div class='add'>+  uint32_t MaxHbmTemperature;</div><div class='add'>+  uint64_t MaxSocketTemperatureAcc;</div><div class='add'>+  uint64_t MaxVrTemperatureAcc;</div><div class='add'>+  uint64_t MaxHbmTemperatureAcc;</div><div class='add'>+</div><div class='add'>+  //POWER</div><div class='add'>+  uint32_t SocketPowerLimit;</div><div class='add'>+  uint32_t MaxSocketPowerLimit;</div><div class='add'>+  uint32_t SocketPower;</div><div class='add'>+</div><div class='add'>+  //ENERGY</div><div class='add'>+  uint64_t Timestamp;</div><div class='add'>+  uint64_t SocketEnergyAcc;</div><div class='add'>+  uint64_t CcdEnergyAcc;</div><div class='add'>+  uint64_t XcdEnergyAcc;</div><div class='add'>+  uint64_t AidEnergyAcc;</div><div class='add'>+  uint64_t HbmEnergyAcc;</div><div class='add'>+</div><div class='add'>+  //FREQUENCY</div><div class='add'>+  uint32_t CclkFrequencyLimit;</div><div class='add'>+  uint32_t GfxclkFrequencyLimit;</div><div class='add'>+  uint32_t FclkFrequency;</div><div class='add'>+  uint32_t UclkFrequency;</div><div class='add'>+  uint32_t SocclkFrequency[4];</div><div class='add'>+  uint32_t VclkFrequency[4];</div><div class='add'>+  uint32_t DclkFrequency[4];</div><div class='add'>+  uint32_t LclkFrequency[4];</div><div class='add'>+  uint64_t GfxclkFrequencyAcc[8];</div><div class='add'>+  uint64_t CclkFrequencyAcc[96];</div><div class='add'>+</div><div class='add'>+  //FREQUENCY RANGE</div><div class='add'>+  uint32_t MaxCclkFrequency;</div><div class='add'>+  uint32_t MinCclkFrequency;</div><div class='add'>+  uint32_t MaxGfxclkFrequency;</div><div class='add'>+  uint32_t MinGfxclkFrequency;</div><div class='add'>+  uint32_t FclkFrequencyTable[4];</div><div class='add'>+  uint32_t UclkFrequencyTable[4];</div><div class='add'>+  uint32_t SocclkFrequencyTable[4];</div><div class='add'>+  uint32_t VclkFrequencyTable[4];</div><div class='add'>+  uint32_t DclkFrequencyTable[4];</div><div class='add'>+  uint32_t LclkFrequencyTable[4];</div><div class='add'>+  uint32_t MaxLclkDpmRange;</div><div class='add'>+  uint32_t MinLclkDpmRange;</div><div class='add'>+</div><div class='add'>+  //XGMI</div><div class='add'>+  uint32_t XgmiWidth;</div><div class='add'>+  uint32_t XgmiBitrate;</div><div class='add'>+  uint64_t XgmiReadBandwidthAcc[8];</div><div class='add'>+  uint64_t XgmiWriteBandwidthAcc[8];</div><div class='add'>+</div><div class='add'>+  //ACTIVITY</div><div class='add'>+  uint32_t SocketC0Residency;</div><div class='add'>+  uint32_t SocketGfxBusy;</div><div class='add'>+  uint32_t DramBandwidthUtilization;</div><div class='add'>+  uint64_t SocketC0ResidencyAcc;</div><div class='add'>+  uint64_t SocketGfxBusyAcc;</div><div class='add'>+  uint64_t DramBandwidthAcc;</div><div class='add'>+  uint32_t MaxDramBandwidth;</div><div class='add'>+  uint64_t DramBandwidthUtilizationAcc;</div><div class='add'>+  uint64_t PcieBandwidthAcc[4];</div><div class='add'>+</div><div class='add'>+  //THROTTLERS</div><div class='add'>+  uint32_t ProchotResidencyAcc;</div><div class='add'>+  uint32_t PptResidencyAcc;</div><div class='add'>+  uint32_t SocketThmResidencyAcc;</div><div class='add'>+  uint32_t VrThmResidencyAcc;</div><div class='add'>+  uint32_t HbmThmResidencyAcc;</div><div class='add'>+  uint32_t GfxLockXCDMak;</div><div class='add'>+</div><div class='add'>+  // New Items at end to maintain driver compatibility</div><div class='add'>+  uint32_t GfxclkFrequency[8];</div><div class='add'>+</div><div class='add'>+  //PSNs</div><div class='add'>+  uint64_t PublicSerialNumber_AID[4];</div><div class='add'>+  uint64_t PublicSerialNumber_XCD[8];</div><div class='add'>+  uint64_t PublicSerialNumber_CCD[12];</div><div class='add'>+</div><div class='add'>+  //XGMI Data tranfser size</div><div class='add'>+  uint64_t XgmiReadDataSizeAcc[8];//in KByte</div><div class='add'>+  uint64_t XgmiWriteDataSizeAcc[8];//in KByte</div><div class='add'>+</div><div class='add'>+  // VCN/JPEG ACTIVITY</div><div class='add'>+  uint32_t VcnBusy[4];</div><div class='add'>+  uint32_t JpegBusy[32];</div><div class='add'>+} MetricsTableA_t;</div><div class='ctx'> </div><div class='ctx'> #define SMU_VF_METRICS_TABLE_VERSION 0x3</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h<br/>index 6aaefca9b595..a6bf9cdd130e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_7_ppsmc.h</a></div><div class='hunk'>@@ -134,6 +134,7 @@</div><div class='ctx'> #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A</div><div class='ctx'> #define PPSMC_MSG_SetPriorityDeltaGain           0x4B</div><div class='ctx'> #define PPSMC_MSG_AllowIHHostInterrupt           0x4C</div><div class='del'>-#define PPSMC_Message_Count                      0x4D</div><div class='add'>+#define PPSMC_MSG_EnableUCLKShadow               0x51</div><div class='add'>+#define PPSMC_Message_Count                      0x52</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h<br/>index 9dd47d91093e..953a767613b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h</a></div><div class='hunk'>@@ -259,7 +259,9 @@</div><div class='ctx'> 	__SMU_DUMMY_MAP(PowerUpUmsch),	\</div><div class='ctx'> 	__SMU_DUMMY_MAP(PowerDownUmsch),	\</div><div class='ctx'> 	__SMU_DUMMY_MAP(SetSoftMaxVpe),	\</div><div class='del'>-	__SMU_DUMMY_MAP(SetSoftMinVpe),</div><div class='add'>+	__SMU_DUMMY_MAP(SetSoftMinVpe), \</div><div class='add'>+	__SMU_DUMMY_MAP(GetMetricsVersion), \</div><div class='add'>+	__SMU_DUMMY_MAP(EnableUCLKShadow),</div><div class='ctx'> </div><div class='ctx'> #undef __SMU_DUMMY_MAP</div><div class='ctx'> #define __SMU_DUMMY_MAP(type)	SMU_MSG_##type</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h<br/>index 95cb919718ae..fbd57fa1a004 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h</a></div><div class='hunk'>@@ -210,15 +210,8 @@ int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);</div><div class='ctx'> int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,</div><div class='ctx'> 					       struct pp_smu_nv_clock_table *max_clocks);</div><div class='ctx'> </div><div class='del'>-int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,</div><div class='del'>-				      enum smu_baco_seq baco_seq);</div><div class='del'>-</div><div class='ctx'> bool smu_v13_0_baco_is_support(struct smu_context *smu);</div><div class='ctx'> </div><div class='del'>-enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);</div><div class='del'>-</div><div class='del'>-int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);</div><div class='del'>-</div><div class='ctx'> int smu_v13_0_baco_enter(struct smu_context *smu);</div><div class='ctx'> int smu_v13_0_baco_exit(struct smu_context *smu);</div><div class='ctx'> </div><div class='hunk'>@@ -301,5 +294,9 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu,</div><div class='ctx'> </div><div class='ctx'> int smu_v13_0_disable_pmfw_state(struct smu_context *smu);</div><div class='ctx'> </div><div class='add'>+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);</div><div class='add'>+</div><div class='add'>+int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,</div><div class='add'>+						 struct freq_band_range *exclusion_ranges);</div><div class='ctx'> #endif</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h<br/>index a5b569976f19..3f7463c1c1a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h</a></div><div class='hunk'>@@ -26,8 +26,8 @@</div><div class='ctx'> #include "amdgpu_smu.h"</div><div class='ctx'> </div><div class='ctx'> #define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF</div><div class='add'>+#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7</div><div class='ctx'> #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1</div><div class='del'>-#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x6</div><div class='ctx'> </div><div class='ctx'> #define FEATURE_MASK(feature) (1ULL &lt;&lt; feature)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c<br/>index 2cb6b68222ba..4cd43bbec910 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c</a></div><div class='hunk'>@@ -2407,8 +2407,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {</div><div class='ctx'> 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,</div><div class='ctx'> 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,</div><div class='ctx'> 	.baco_is_support = smu_v11_0_baco_is_support,</div><div class='del'>-	.baco_get_state = smu_v11_0_baco_get_state,</div><div class='del'>-	.baco_set_state = smu_v11_0_baco_set_state,</div><div class='ctx'> 	.baco_enter = smu_v11_0_baco_enter,</div><div class='ctx'> 	.baco_exit = smu_v11_0_baco_exit,</div><div class='ctx'> 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c<br/>index a38233cc5b7f..8d1d29ffb0f1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c</a></div><div class='hunk'>@@ -3537,8 +3537,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {</div><div class='ctx'> 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,</div><div class='ctx'> 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,</div><div class='ctx'> 	.baco_is_support = smu_v11_0_baco_is_support,</div><div class='del'>-	.baco_get_state = smu_v11_0_baco_get_state,</div><div class='del'>-	.baco_set_state = smu_v11_0_baco_set_state,</div><div class='ctx'> 	.baco_enter = navi10_baco_enter,</div><div class='ctx'> 	.baco_exit = navi10_baco_exit,</div><div class='ctx'> 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br/>index 1de9f8b5cc5f..21fc033528fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c</a></div><div class='hunk'>@@ -4428,8 +4428,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {</div><div class='ctx'> 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,</div><div class='ctx'> 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,</div><div class='ctx'> 	.baco_is_support = smu_v11_0_baco_is_support,</div><div class='del'>-	.baco_get_state = smu_v11_0_baco_get_state,</div><div class='del'>-	.baco_set_state = smu_v11_0_baco_set_state,</div><div class='ctx'> 	.baco_enter = sienna_cichlid_baco_enter,</div><div class='ctx'> 	.baco_exit = sienna_cichlid_baco_exit,</div><div class='ctx'> 	.mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c<br/>index 762b31455a0b..2ff6deedef95 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c</a></div><div class='hunk'>@@ -2193,8 +2193,7 @@ static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clock</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-static int vangogh_system_features_control(struct smu_context *smu, bool en)</div><div class='add'>+static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -2523,7 +2522,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {</div><div class='ctx'> 	.print_clk_levels = vangogh_common_print_clk_levels,</div><div class='ctx'> 	.set_default_dpm_table = vangogh_set_default_dpm_tables,</div><div class='ctx'> 	.set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,</div><div class='del'>-	.system_features_control = vangogh_system_features_control,</div><div class='add'>+	.notify_rlc_state = vangogh_notify_rlc_state,</div><div class='ctx'> 	.feature_is_enabled = smu_cmn_feature_is_enabled,</div><div class='ctx'> 	.set_power_profile_mode = vangogh_set_power_profile_mode,</div><div class='ctx'> 	.get_power_profile_mode = vangogh_get_power_profile_mode,</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c<br/>index 1a6675d70a4b..dd9bcbd630a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c</a></div><div class='hunk'>@@ -257,8 +257,11 @@ static int aldebaran_tables_init(struct smu_context *smu)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	smu_table-&gt;ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);</div><div class='del'>-	if (!smu_table-&gt;ecc_table)</div><div class='add'>+	if (!smu_table-&gt;ecc_table) {</div><div class='add'>+		kfree(smu_table-&gt;metrics_table);</div><div class='add'>+		kfree(smu_table-&gt;gpu_metrics_table);</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1527,7 +1530,6 @@ static int aldebaran_i2c_control_init(struct smu_context *smu)</div><div class='ctx'> 	smu_i2c-&gt;port = 0;</div><div class='ctx'> 	mutex_init(&amp;smu_i2c-&gt;mutex);</div><div class='ctx'> 	control-&gt;owner = THIS_MODULE;</div><div class='del'>-	control-&gt;class = I2C_CLASS_SPD;</div><div class='ctx'> 	control-&gt;dev.parent = &amp;adev-&gt;pdev-&gt;dev;</div><div class='ctx'> 	control-&gt;algo = &amp;aldebaran_i2c_algo;</div><div class='ctx'> 	snprintf(control-&gt;name, sizeof(control-&gt;name), "AMDGPU SMU 0");</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c<br/>index cf1b84060bc3..771a3d457c33 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c</a></div><div class='hunk'>@@ -2199,7 +2199,7 @@ int smu_v13_0_gfx_ulv_control(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,</div><div class='add'>+static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,</div><div class='ctx'> 				      enum smu_baco_seq baco_seq)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='hunk'>@@ -2221,33 +2221,14 @@ int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-bool smu_v13_0_baco_is_support(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='del'>-</div><div class='del'>-	if (amdgpu_sriov_vf(smu-&gt;adev) ||</div><div class='del'>-	    !smu_baco-&gt;platform_support)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	/* return true if ASIC is in BACO state already */</div><div class='del'>-	if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &amp;&amp;</div><div class='del'>-	    !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)</div><div class='add'>+static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='ctx'> </div><div class='ctx'> 	return smu_baco-&gt;state;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int smu_v13_0_baco_set_state(struct smu_context *smu,</div><div class='add'>+static int smu_v13_0_baco_set_state(struct smu_context *smu,</div><div class='ctx'> 			     enum smu_baco_state state)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='hunk'>@@ -2281,24 +2262,60 @@ int smu_v13_0_baco_set_state(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int smu_v13_0_baco_enter(struct smu_context *smu)</div><div class='add'>+bool smu_v13_0_baco_is_support(struct smu_context *smu)</div><div class='ctx'> {</div><div class='del'>-	int ret = 0;</div><div class='add'>+	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='ctx'> </div><div class='del'>-	ret = smu_v13_0_baco_set_state(smu,</div><div class='del'>-				       SMU_BACO_STATE_ENTER);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	if (amdgpu_sriov_vf(smu-&gt;adev) || !smu_baco-&gt;platform_support)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* return true if ASIC is in BACO state already */</div><div class='add'>+	if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)</div><div class='add'>+		return true;</div><div class='ctx'> </div><div class='del'>-	msleep(10);</div><div class='add'>+	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &amp;&amp;</div><div class='add'>+	    !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int smu_v13_0_baco_enter(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev)) {</div><div class='add'>+		return smu_v13_0_baco_set_armd3_sequence(smu,</div><div class='add'>+				(smu_baco-&gt;maco_support &amp;&amp; amdgpu_runtime_pm != 1) ?</div><div class='add'>+					BACO_SEQ_BAMACO : BACO_SEQ_BACO);</div><div class='add'>+	} else {</div><div class='add'>+		ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);</div><div class='add'>+		if (!ret)</div><div class='add'>+			usleep_range(10000, 11000);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int smu_v13_0_baco_exit(struct smu_context *smu)</div><div class='ctx'> {</div><div class='del'>-	return smu_v13_0_baco_set_state(smu,</div><div class='del'>-					SMU_BACO_STATE_EXIT);</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev)) {</div><div class='add'>+		/* Wait for PMFW handling for the Dstate change */</div><div class='add'>+		usleep_range(10000, 11000);</div><div class='add'>+		ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);</div><div class='add'>+	} else {</div><div class='add'>+		ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!ret)</div><div class='add'>+		adev-&gt;gfx.is_poweron = false;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)</div><div class='hunk'>@@ -2490,3 +2507,51 @@ int smu_v13_0_disable_pmfw_state(struct smu_context *smu)</div><div class='ctx'> </div><div class='ctx'> 	return ret == 0 ? 0 : -EINVAL;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)</div><div class='add'>+{</div><div class='add'>+	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,</div><div class='add'>+						 struct freq_band_range *exclusion_ranges)</div><div class='add'>+{</div><div class='add'>+	WifiBandEntryTable_t wifi_bands;</div><div class='add'>+	int valid_entries = 0;</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	memset(&amp;wifi_bands, 0, sizeof(wifi_bands));</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {</div><div class='add'>+		if (!exclusion_ranges[i].start &amp;&amp; !exclusion_ranges[i].end)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		/* PMFW expects the inputs to be in Mhz unit */</div><div class='add'>+		wifi_bands.WifiBandEntry[valid_entries].LowFreq =</div><div class='add'>+			DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);</div><div class='add'>+		wifi_bands.WifiBandEntry[valid_entries++].HighFreq =</div><div class='add'>+			DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);</div><div class='add'>+	}</div><div class='add'>+	wifi_bands.WifiBandEntryNum = valid_entries;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Per confirm with PMFW team, WifiBandEntryNum = 0</div><div class='add'>+	 * is a valid setting.</div><div class='add'>+	 *</div><div class='add'>+	 * Considering the scenarios below:</div><div class='add'>+	 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to</div><div class='add'>+	 *   BIOS and our driver gets notified. We will set WifiBandEntryNum = 1</div><div class='add'>+	 *   and pass the WifiBandEntry (2400, 2500) to PMFW.</div><div class='add'>+	 *</div><div class='add'>+	 * - Later the wifi device removes the wifiband list added above and</div><div class='add'>+	 *   our driver gets notified again. At this time, driver will set</div><div class='add'>+	 *   WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.</div><div class='add'>+	 *</div><div class='add'>+	 * - PMFW may still need to do some uclk shadow update(e.g. switching</div><div class='add'>+	 *   from shadow clock back to primary clock) on receiving this.</div><div class='add'>+	 */</div><div class='add'>+	ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &amp;wifi_bands, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_warn(smu-&gt;adev-&gt;dev, "Failed to set wifiband!");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br/>index 82c4e1f1c6f0..a9b25faa63e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c</a></div><div class='hunk'>@@ -169,6 +169,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =</div><div class='ctx'> 	MSG_MAP(AllowIHHostInterrupt,		PPSMC_MSG_AllowIHHostInterrupt,       0),</div><div class='ctx'> 	MSG_MAP(ReenableAcDcInterrupt,		PPSMC_MSG_ReenableAcDcInterrupt,       0),</div><div class='ctx'> 	MSG_MAP(DALNotPresent,		PPSMC_MSG_DALNotPresent,       0),</div><div class='add'>+	MSG_MAP(EnableUCLKShadow,		PPSMC_MSG_EnableUCLKShadow,            0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {</div><div class='hunk'>@@ -253,6 +254,7 @@ static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {</div><div class='ctx'> 	TAB_MAP(I2C_COMMANDS),</div><div class='ctx'> 	TAB_MAP(ECCINFO),</div><div class='ctx'> 	TAB_MAP(OVERDRIVE),</div><div class='add'>+	TAB_MAP(WIFIBAND),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {</div><div class='hunk'>@@ -498,6 +500,9 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu)</div><div class='ctx'> 			PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 	SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),</div><div class='ctx'> 			PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='add'>+	SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,</div><div class='add'>+		       sizeof(WifiBandEntryTable_t), PAGE_SIZE,</div><div class='add'>+		       AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> </div><div class='ctx'> 	smu_table-&gt;metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);</div><div class='ctx'> 	if (!smu_table-&gt;metrics_table)</div><div class='hunk'>@@ -2540,16 +2545,19 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,</div><div class='ctx'> </div><div class='ctx'> 	workload_mask = 1 &lt;&lt; workload_type;</div><div class='ctx'> </div><div class='del'>-	/* Add optimizations for SMU13.0.0.  Reuse the power saving profile */</div><div class='del'>-	if (smu-&gt;power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &amp;&amp;</div><div class='del'>-	    (amdgpu_ip_version(smu-&gt;adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) &amp;&amp;</div><div class='del'>-	    ((smu-&gt;adev-&gt;pm.fw_version == 0x004e6601) ||</div><div class='del'>-	     (smu-&gt;adev-&gt;pm.fw_version &gt;= 0x004e7400))) {</div><div class='del'>-		workload_type = smu_cmn_to_asic_specific_index(smu,</div><div class='del'>-							       CMN2ASIC_MAPPING_WORKLOAD,</div><div class='del'>-							       PP_SMC_POWER_PROFILE_POWERSAVING);</div><div class='del'>-		if (workload_type &gt;= 0)</div><div class='del'>-			workload_mask |= 1 &lt;&lt; workload_type;</div><div class='add'>+	/* Add optimizations for SMU13.0.0/10.  Reuse the power saving profile */</div><div class='add'>+	if (smu-&gt;power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {</div><div class='add'>+		if ((amdgpu_ip_version(smu-&gt;adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &amp;&amp;</div><div class='add'>+			((smu-&gt;adev-&gt;pm.fw_version == 0x004e6601) ||</div><div class='add'>+			(smu-&gt;adev-&gt;pm.fw_version &gt;= 0x004e7300))) ||</div><div class='add'>+			(amdgpu_ip_version(smu-&gt;adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &amp;&amp;</div><div class='add'>+			 smu-&gt;adev-&gt;pm.fw_version &gt;= 0x00504500)) {</div><div class='add'>+			workload_type = smu_cmn_to_asic_specific_index(smu,</div><div class='add'>+														   CMN2ASIC_MAPPING_WORKLOAD,</div><div class='add'>+														   PP_SMC_POWER_PROFILE_POWERSAVING);</div><div class='add'>+			if (workload_type &gt;= 0)</div><div class='add'>+				workload_mask |= 1 &lt;&lt; workload_type;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return smu_cmn_send_smc_msg_with_param(smu,</div><div class='hunk'>@@ -2558,38 +2566,6 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,</div><div class='ctx'> 					       NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int smu_v13_0_0_baco_enter(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='del'>-	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev))</div><div class='del'>-		return smu_v13_0_baco_set_armd3_sequence(smu,</div><div class='del'>-				(smu_baco-&gt;maco_support &amp;&amp; amdgpu_runtime_pm != 1) ?</div><div class='del'>-					BACO_SEQ_BAMACO : BACO_SEQ_BACO);</div><div class='del'>-	else</div><div class='del'>-		return smu_v13_0_baco_enter(smu);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int smu_v13_0_0_baco_exit(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev)) {</div><div class='del'>-		/* Wait for PMFW handling for the Dstate change */</div><div class='del'>-		usleep_range(10000, 11000);</div><div class='del'>-		ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);</div><div class='del'>-	} else {</div><div class='del'>-		ret = smu_v13_0_baco_exit(smu);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!ret)</div><div class='del'>-		adev-&gt;gfx.is_poweron = false;</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='hunk'>@@ -2720,7 +2696,6 @@ static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)</div><div class='ctx'> 		smu_i2c-&gt;port = i;</div><div class='ctx'> 		mutex_init(&amp;smu_i2c-&gt;mutex);</div><div class='ctx'> 		control-&gt;owner = THIS_MODULE;</div><div class='del'>-		control-&gt;class = I2C_CLASS_SPD;</div><div class='ctx'> 		control-&gt;dev.parent = &amp;adev-&gt;pdev-&gt;dev;</div><div class='ctx'> 		control-&gt;algo = &amp;smu_v13_0_0_i2c_algo;</div><div class='ctx'> 		snprintf(control-&gt;name, sizeof(control-&gt;name), "AMDGPU SMU %d", i);</div><div class='hunk'>@@ -2970,6 +2945,20 @@ static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='add'>+</div><div class='add'>+	switch (adev-&gt;ip_versions[MP1_HWIP][0]) {</div><div class='add'>+	case IP_VERSION(13, 0, 0):</div><div class='add'>+		return smu-&gt;smc_fw_version &gt;= 0x004e6300;</div><div class='add'>+	case IP_VERSION(13, 0, 10):</div><div class='add'>+		return smu-&gt;smc_fw_version &gt;= 0x00503300;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {</div><div class='ctx'> 	.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,</div><div class='ctx'> 	.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,</div><div class='hunk'>@@ -3035,10 +3024,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {</div><div class='ctx'> 	.deep_sleep_control = smu_v13_0_deep_sleep_control,</div><div class='ctx'> 	.gfx_ulv_control = smu_v13_0_gfx_ulv_control,</div><div class='ctx'> 	.baco_is_support = smu_v13_0_baco_is_support,</div><div class='del'>-	.baco_get_state = smu_v13_0_baco_get_state,</div><div class='del'>-	.baco_set_state = smu_v13_0_baco_set_state,</div><div class='del'>-	.baco_enter = smu_v13_0_0_baco_enter,</div><div class='del'>-	.baco_exit = smu_v13_0_0_baco_exit,</div><div class='add'>+	.baco_enter = smu_v13_0_baco_enter,</div><div class='add'>+	.baco_exit = smu_v13_0_baco_exit,</div><div class='ctx'> 	.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,</div><div class='ctx'> 	.mode1_reset = smu_v13_0_0_mode1_reset,</div><div class='ctx'> 	.mode2_reset = smu_v13_0_0_mode2_reset,</div><div class='hunk'>@@ -3050,6 +3037,9 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {</div><div class='ctx'> 	.gpo_control = smu_v13_0_gpo_control,</div><div class='ctx'> 	.get_ecc_info = smu_v13_0_0_get_ecc_info,</div><div class='ctx'> 	.notify_display_change = smu_v13_0_notify_display_change,</div><div class='add'>+	.is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check,</div><div class='add'>+	.enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,</div><div class='add'>+	.set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c<br/>index 0e5a77c3c2e2..3c98a8a0386a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c</a></div><div class='hunk'>@@ -120,6 +120,7 @@ struct mca_ras_info {</div><div class='ctx'> #define P2S_TABLE_ID_A 0x50325341</div><div class='ctx'> #define P2S_TABLE_ID_X 0x50325358</div><div class='ctx'> </div><div class='add'>+// clang-format off</div><div class='ctx'> static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {</div><div class='ctx'> 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),</div><div class='ctx'> 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),</div><div class='hunk'>@@ -128,6 +129,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU</div><div class='ctx'> 	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures,		0),</div><div class='ctx'> 	MSG_MAP(RequestI2cTransaction,		     PPSMC_MSG_RequestI2cTransaction,		0),</div><div class='ctx'> 	MSG_MAP(GetMetricsTable,		     PPSMC_MSG_GetMetricsTable,			1),</div><div class='add'>+	MSG_MAP(GetMetricsVersion,		     PPSMC_MSG_GetMetricsVersion,		1),</div><div class='ctx'> 	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh,	1),</div><div class='ctx'> 	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow,	1),</div><div class='ctx'> 	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh,		1),</div><div class='hunk'>@@ -171,6 +173,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU</div><div class='ctx'> 	MSG_MAP(SelectPLPDMode,                      PPSMC_MSG_SelectPLPDMode,                  0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+// clang-format on</div><div class='ctx'> static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {</div><div class='ctx'> 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),</div><div class='ctx'> 	CLK_MAP(FCLK, PPCLK_FCLK),</div><div class='hunk'>@@ -245,6 +248,8 @@ struct PPTable_t {</div><div class='ctx'> #define SMUQ10_TO_UINT(x) ((x) &gt;&gt; 10)</div><div class='ctx'> #define SMUQ10_FRAC(x) ((x) &amp; 0x3ff)</div><div class='ctx'> #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) &gt;= 0x200))</div><div class='add'>+#define GET_METRIC_FIELD(field) ((adev-&gt;flags &amp; AMD_IS_APU) ?\</div><div class='add'>+		(metrics_a-&gt;field) : (metrics_x-&gt;field))</div><div class='ctx'> </div><div class='ctx'> struct smu_v13_0_6_dpm_map {</div><div class='ctx'> 	enum smu_clk_type clk_type;</div><div class='hunk'>@@ -327,7 +332,8 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)</div><div class='ctx'> 		SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,</div><div class='ctx'> 			       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> </div><div class='del'>-	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(MetricsTable_t),</div><div class='add'>+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,</div><div class='add'>+		       max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),</div><div class='ctx'> 		       PAGE_SIZE,</div><div class='ctx'> 		       AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);</div><div class='ctx'> </div><div class='hunk'>@@ -335,12 +341,13 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)</div><div class='ctx'> 		       PAGE_SIZE,</div><div class='ctx'> 		       AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);</div><div class='ctx'> </div><div class='del'>-	smu_table-&gt;metrics_table = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL);</div><div class='add'>+	smu_table-&gt;metrics_table = kzalloc(max(sizeof(MetricsTableX_t),</div><div class='add'>+		       sizeof(MetricsTableA_t)), GFP_KERNEL);</div><div class='ctx'> 	if (!smu_table-&gt;metrics_table)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	smu_table-&gt;metrics_time = 0;</div><div class='ctx'> </div><div class='del'>-	smu_table-&gt;gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_4);</div><div class='add'>+	smu_table-&gt;gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5);</div><div class='ctx'> 	smu_table-&gt;gpu_metrics_table =</div><div class='ctx'> 		kzalloc(smu_table-&gt;gpu_metrics_table_size, GFP_KERNEL);</div><div class='ctx'> 	if (!smu_table-&gt;gpu_metrics_table) {</div><div class='hunk'>@@ -428,13 +435,51 @@ static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,</div><div class='add'>+					  void *metrics, size_t max_size)</div><div class='add'>+{</div><div class='add'>+	struct smu_table_context *smu_tbl_ctxt = &amp;smu-&gt;smu_table;</div><div class='add'>+	uint32_t table_version = smu_tbl_ctxt-&gt;tables[SMU_TABLE_SMU_METRICS].version;</div><div class='add'>+	uint32_t table_size = smu_tbl_ctxt-&gt;tables[SMU_TABLE_SMU_METRICS].size;</div><div class='add'>+	struct amdgpu_pm_metrics *pm_metrics = metrics;</div><div class='add'>+	uint32_t pmfw_version;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pm_metrics || !max_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (max_size &lt; (table_size + sizeof(pm_metrics-&gt;common_header)))</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+</div><div class='add'>+	/* Don't use cached metrics data */</div><div class='add'>+	ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics-&gt;data, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	smu_cmn_get_smc_version(smu, NULL, &amp;pmfw_version);</div><div class='add'>+</div><div class='add'>+	memset(&amp;pm_metrics-&gt;common_header, 0,</div><div class='add'>+	       sizeof(pm_metrics-&gt;common_header));</div><div class='add'>+	pm_metrics-&gt;common_header.mp1_ip_discovery_version =</div><div class='add'>+		IP_VERSION(13, 0, 6);</div><div class='add'>+	pm_metrics-&gt;common_header.pmfw_version = pmfw_version;</div><div class='add'>+	pm_metrics-&gt;common_header.pmmetrics_version = table_version;</div><div class='add'>+	pm_metrics-&gt;common_header.structure_size =</div><div class='add'>+		sizeof(pm_metrics-&gt;common_header) + table_size;</div><div class='add'>+</div><div class='add'>+	return pm_metrics-&gt;common_header.structure_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_table_context *smu_table = &amp;smu-&gt;smu_table;</div><div class='del'>-	MetricsTable_t *metrics = (MetricsTable_t *)smu_table-&gt;metrics_table;</div><div class='add'>+	MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table-&gt;metrics_table;</div><div class='add'>+	MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table-&gt;metrics_table;</div><div class='ctx'> 	struct PPTable_t *pptable =</div><div class='ctx'> 		(struct PPTable_t *)smu_table-&gt;driver_pptable;</div><div class='add'>+	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='ctx'> 	int ret, i, retry = 100;</div><div class='add'>+	uint32_t table_version;</div><div class='ctx'> </div><div class='ctx'> 	/* Store one-time values in driver PPTable */</div><div class='ctx'> 	if (!pptable-&gt;Init) {</div><div class='hunk'>@@ -444,7 +489,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='ctx'> 			/* Ensure that metrics have been updated */</div><div class='del'>-			if (metrics-&gt;AccumulationCounter)</div><div class='add'>+			if (GET_METRIC_FIELD(AccumulationCounter))</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='ctx'> 			usleep_range(1000, 1100);</div><div class='hunk'>@@ -453,30 +498,37 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)</div><div class='ctx'> 		if (!retry)</div><div class='ctx'> 			return -ETIME;</div><div class='ctx'> </div><div class='add'>+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,</div><div class='add'>+					   &amp;table_version);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		smu_table-&gt;tables[SMU_TABLE_SMU_METRICS].version =</div><div class='add'>+			table_version;</div><div class='add'>+</div><div class='ctx'> 		pptable-&gt;MaxSocketPowerLimit =</div><div class='del'>-			SMUQ10_ROUND(metrics-&gt;MaxSocketPowerLimit);</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit));</div><div class='ctx'> 		pptable-&gt;MaxGfxclkFrequency =</div><div class='del'>-			SMUQ10_ROUND(metrics-&gt;MaxGfxclkFrequency);</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency));</div><div class='ctx'> 		pptable-&gt;MinGfxclkFrequency =</div><div class='del'>-			SMUQ10_ROUND(metrics-&gt;MinGfxclkFrequency);</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency));</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; 4; ++i) {</div><div class='ctx'> 			pptable-&gt;FclkFrequencyTable[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;FclkFrequencyTable[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]);</div><div class='ctx'> 			pptable-&gt;UclkFrequencyTable[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;UclkFrequencyTable[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]);</div><div class='ctx'> 			pptable-&gt;SocclkFrequencyTable[i] = SMUQ10_ROUND(</div><div class='del'>-				metrics-&gt;SocclkFrequencyTable[i]);</div><div class='add'>+				GET_METRIC_FIELD(SocclkFrequencyTable)[i]);</div><div class='ctx'> 			pptable-&gt;VclkFrequencyTable[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;VclkFrequencyTable[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]);</div><div class='ctx'> 			pptable-&gt;DclkFrequencyTable[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;DclkFrequencyTable[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]);</div><div class='ctx'> 			pptable-&gt;LclkFrequencyTable[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;LclkFrequencyTable[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* use AID0 serial number by default */</div><div class='del'>-		pptable-&gt;PublicSerialNumber_AID = metrics-&gt;PublicSerialNumber_AID[0];</div><div class='add'>+		pptable-&gt;PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0];</div><div class='ctx'> </div><div class='ctx'> 		pptable-&gt;Init = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -778,7 +830,8 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,</div><div class='ctx'> 					    uint32_t *value)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_table_context *smu_table = &amp;smu-&gt;smu_table;</div><div class='del'>-	MetricsTable_t *metrics = (MetricsTable_t *)smu_table-&gt;metrics_table;</div><div class='add'>+	MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table-&gt;metrics_table;</div><div class='add'>+	MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table-&gt;metrics_table;</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	int xcc_id;</div><div class='hunk'>@@ -793,50 +846,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,</div><div class='ctx'> 	case METRICS_AVERAGE_GFXCLK:</div><div class='ctx'> 		if (smu-&gt;smc_fw_version &gt;= 0x552F00) {</div><div class='ctx'> 			xcc_id = GET_INST(GC, 0);</div><div class='del'>-			*value = SMUQ10_ROUND(metrics-&gt;GfxclkFrequency[xcc_id]);</div><div class='add'>+			*value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			*value = 0;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_SOCCLK:</div><div class='ctx'> 	case METRICS_AVERAGE_SOCCLK:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;SocclkFrequency[0]);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_UCLK:</div><div class='ctx'> 	case METRICS_AVERAGE_UCLK:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;UclkFrequency);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_VCLK:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;VclkFrequency[0]);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_DCLK:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;DclkFrequency[0]);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_FCLK:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;FclkFrequency);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_AVERAGE_GFXACTIVITY:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;SocketGfxBusy);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_AVERAGE_MEMACTIVITY:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;DramBandwidthUtilization);</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_CURR_SOCKETPOWER:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;SocketPower) &lt;&lt; 8;</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) &lt;&lt; 8;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_TEMPERATURE_HOTSPOT:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;MaxSocketTemperature) *</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) *</div><div class='ctx'> 			 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_TEMPERATURE_MEM:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;MaxHbmTemperature) *</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) *</div><div class='ctx'> 			 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;</div><div class='ctx'> 		break;</div><div class='ctx'> 	/* This is the max of all VRs and not just SOC VR.</div><div class='ctx'> 	 * No need to define another data type for the same.</div><div class='ctx'> 	 */</div><div class='ctx'> 	case METRICS_TEMPERATURE_VRSOC:</div><div class='del'>-		*value = SMUQ10_ROUND(metrics-&gt;MaxVrTemperature) *</div><div class='add'>+		*value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) *</div><div class='ctx'> 			 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -917,7 +970,9 @@ static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,</div><div class='ctx'> 			if (i &lt; (clocks.num_levels - 1))</div><div class='ctx'> 				clk2 = clocks.data[i + 1].clocks_in_khz / 1000;</div><div class='ctx'> </div><div class='del'>-			if (curr_clk &gt;= clk1 &amp;&amp; curr_clk &lt; clk2) {</div><div class='add'>+			if (curr_clk == clk1) {</div><div class='add'>+				level = i;</div><div class='add'>+			} else if (curr_clk &gt;= clk1 &amp;&amp; curr_clk &lt; clk2) {</div><div class='ctx'> 				level = (curr_clk - clk1) &lt;= (clk2 - curr_clk) ?</div><div class='ctx'> 						i :</div><div class='ctx'> 						i + 1;</div><div class='hunk'>@@ -1470,7 +1525,6 @@ static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)</div><div class='ctx'> 	if (smu-&gt;smc_fw_version &lt; 0x554800)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	amdgpu_ras_set_mca_debug_mode(smu-&gt;adev, enable);</div><div class='ctx'> 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,</div><div class='ctx'> 					       enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,</div><div class='ctx'> 					       NULL);</div><div class='hunk'>@@ -1884,7 +1938,6 @@ static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)</div><div class='ctx'> 		smu_i2c-&gt;port = i;</div><div class='ctx'> 		mutex_init(&amp;smu_i2c-&gt;mutex);</div><div class='ctx'> 		control-&gt;owner = THIS_MODULE;</div><div class='del'>-		control-&gt;class = I2C_CLASS_SPD;</div><div class='ctx'> 		control-&gt;dev.parent = &amp;adev-&gt;pdev-&gt;dev;</div><div class='ctx'> 		control-&gt;algo = &amp;smu_v13_0_6_i2c_algo;</div><div class='ctx'> 		snprintf(control-&gt;name, sizeof(control-&gt;name), "AMDGPU SMU %d", i);</div><div class='hunk'>@@ -2022,67 +2075,70 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)</div><div class='ctx'> static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_table_context *smu_table = &amp;smu-&gt;smu_table;</div><div class='del'>-	struct gpu_metrics_v1_4 *gpu_metrics =</div><div class='del'>-		(struct gpu_metrics_v1_4 *)smu_table-&gt;gpu_metrics_table;</div><div class='add'>+	struct gpu_metrics_v1_5 *gpu_metrics =</div><div class='add'>+		(struct gpu_metrics_v1_5 *)smu_table-&gt;gpu_metrics_table;</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-	int ret = 0, xcc_id, inst, i;</div><div class='del'>-	MetricsTable_t *metrics;</div><div class='add'>+	int ret = 0, xcc_id, inst, i, j;</div><div class='add'>+	MetricsTableX_t *metrics_x;</div><div class='add'>+	MetricsTableA_t *metrics_a;</div><div class='ctx'> 	u16 link_width_level;</div><div class='ctx'> </div><div class='del'>-	metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL);</div><div class='del'>-	ret = smu_v13_0_6_get_metrics_table(smu, metrics, true);</div><div class='add'>+	metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);</div><div class='add'>+	ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		kfree(metrics);</div><div class='add'>+		kfree(metrics_x);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 4);</div><div class='add'>+	metrics_a = (MetricsTableA_t *)metrics_x;</div><div class='add'>+</div><div class='add'>+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5);</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;temperature_hotspot =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;MaxSocketTemperature);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature));</div><div class='ctx'> 	/* Individual HBM stack temperature is not reported */</div><div class='ctx'> 	gpu_metrics-&gt;temperature_mem =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;MaxHbmTemperature);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature));</div><div class='ctx'> 	/* Reports max temperature of all voltage rails */</div><div class='ctx'> 	gpu_metrics-&gt;temperature_vrsoc =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;MaxVrTemperature);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature));</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;average_gfx_activity =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;SocketGfxBusy);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy));</div><div class='ctx'> 	gpu_metrics-&gt;average_umc_activity =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;DramBandwidthUtilization);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization));</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;curr_socket_power =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;SocketPower);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower));</div><div class='ctx'> 	/* Energy counter reported in 15.259uJ (2^-16) units */</div><div class='del'>-	gpu_metrics-&gt;energy_accumulator = metrics-&gt;SocketEnergyAcc;</div><div class='add'>+	gpu_metrics-&gt;energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX_GFX_CLKS; i++) {</div><div class='ctx'> 		xcc_id = GET_INST(GC, i);</div><div class='ctx'> 		if (xcc_id &gt;= 0)</div><div class='ctx'> 			gpu_metrics-&gt;current_gfxclk[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;GfxclkFrequency[xcc_id]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]);</div><div class='ctx'> </div><div class='ctx'> 		if (i &lt; MAX_CLKS) {</div><div class='ctx'> 			gpu_metrics-&gt;current_socclk[i] =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;SocclkFrequency[i]);</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]);</div><div class='ctx'> 			inst = GET_INST(VCN, i);</div><div class='ctx'> 			if (inst &gt;= 0) {</div><div class='ctx'> 				gpu_metrics-&gt;current_vclk0[i] =</div><div class='del'>-					SMUQ10_ROUND(metrics-&gt;VclkFrequency[inst]);</div><div class='add'>+					SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]);</div><div class='ctx'> 				gpu_metrics-&gt;current_dclk0[i] =</div><div class='del'>-					SMUQ10_ROUND(metrics-&gt;DclkFrequency[inst]);</div><div class='add'>+					SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	gpu_metrics-&gt;current_uclk = SMUQ10_ROUND(metrics-&gt;UclkFrequency);</div><div class='add'>+	gpu_metrics-&gt;current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency));</div><div class='ctx'> </div><div class='ctx'> 	/* Throttle status is not reported through metrics now */</div><div class='ctx'> 	gpu_metrics-&gt;throttle_status = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Clock Lock Status. Each bit corresponds to each GFXCLK instance */</div><div class='del'>-	gpu_metrics-&gt;gfxclk_lock_status = metrics-&gt;GfxLockXCDMak &gt;&gt; GET_INST(GC, 0);</div><div class='add'>+	gpu_metrics-&gt;gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) &gt;&gt; GET_INST(GC, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (!(adev-&gt;flags &amp; AMD_IS_APU)) {</div><div class='ctx'> 		link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);</div><div class='hunk'>@@ -2094,38 +2150,57 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table</div><div class='ctx'> 		gpu_metrics-&gt;pcie_link_speed =</div><div class='ctx'> 			smu_v13_0_6_get_current_pcie_link_speed(smu);</div><div class='ctx'> 		gpu_metrics-&gt;pcie_bandwidth_acc =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;PcieBandwidthAcc[0]);</div><div class='add'>+				SMUQ10_ROUND(metrics_x-&gt;PcieBandwidthAcc[0]);</div><div class='ctx'> 		gpu_metrics-&gt;pcie_bandwidth_inst =</div><div class='del'>-				SMUQ10_ROUND(metrics-&gt;PcieBandwidth[0]);</div><div class='add'>+				SMUQ10_ROUND(metrics_x-&gt;PcieBandwidth[0]);</div><div class='ctx'> 		gpu_metrics-&gt;pcie_l0_to_recov_count_acc =</div><div class='del'>-				metrics-&gt;PCIeL0ToRecoveryCountAcc;</div><div class='add'>+				metrics_x-&gt;PCIeL0ToRecoveryCountAcc;</div><div class='ctx'> 		gpu_metrics-&gt;pcie_replay_count_acc =</div><div class='del'>-				metrics-&gt;PCIenReplayAAcc;</div><div class='add'>+				metrics_x-&gt;PCIenReplayAAcc;</div><div class='ctx'> 		gpu_metrics-&gt;pcie_replay_rover_count_acc =</div><div class='del'>-				metrics-&gt;PCIenReplayARolloverCountAcc;</div><div class='add'>+				metrics_x-&gt;PCIenReplayARolloverCountAcc;</div><div class='add'>+		gpu_metrics-&gt;pcie_nak_sent_count_acc =</div><div class='add'>+				metrics_x-&gt;PCIeNAKSentCountAcc;</div><div class='add'>+		gpu_metrics-&gt;pcie_nak_rcvd_count_acc =</div><div class='add'>+				metrics_x-&gt;PCIeNAKReceivedCountAcc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;system_clock_counter = ktime_get_boottime_ns();</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;gfx_activity_acc =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;SocketGfxBusyAcc);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc));</div><div class='ctx'> 	gpu_metrics-&gt;mem_activity_acc =</div><div class='del'>-		SMUQ10_ROUND(metrics-&gt;DramBandwidthUtilizationAcc);</div><div class='add'>+		SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc));</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NUM_XGMI_LINKS; i++) {</div><div class='ctx'> 		gpu_metrics-&gt;xgmi_read_data_acc[i] =</div><div class='del'>-			SMUQ10_ROUND(metrics-&gt;XgmiReadDataSizeAcc[i]);</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]);</div><div class='ctx'> 		gpu_metrics-&gt;xgmi_write_data_acc[i] =</div><div class='del'>-			SMUQ10_ROUND(metrics-&gt;XgmiWriteDataSizeAcc[i]);</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	gpu_metrics-&gt;xgmi_link_width = SMUQ10_ROUND(metrics-&gt;XgmiWidth);</div><div class='del'>-	gpu_metrics-&gt;xgmi_link_speed = SMUQ10_ROUND(metrics-&gt;XgmiBitrate);</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;jpeg.num_jpeg_inst; ++i) {</div><div class='add'>+		inst = GET_INST(JPEG, i);</div><div class='add'>+		for (j = 0; j &lt; adev-&gt;jpeg.num_jpeg_rings; ++j) {</div><div class='add'>+			gpu_metrics-&gt;jpeg_activity[(i * adev-&gt;jpeg.num_jpeg_rings) + j] =</div><div class='add'>+				SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy)</div><div class='add'>+				[(inst * adev-&gt;jpeg.num_jpeg_rings) + j]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; adev-&gt;vcn.num_vcn_inst; ++i) {</div><div class='add'>+		inst = GET_INST(VCN, i);</div><div class='add'>+		gpu_metrics-&gt;vcn_activity[i] =</div><div class='add'>+			SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpu_metrics-&gt;xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth));</div><div class='add'>+	gpu_metrics-&gt;xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate));</div><div class='ctx'> </div><div class='del'>-	gpu_metrics-&gt;firmware_timestamp = metrics-&gt;Timestamp;</div><div class='add'>+	gpu_metrics-&gt;firmware_timestamp = GET_METRIC_FIELD(Timestamp);</div><div class='ctx'> </div><div class='ctx'> 	*table = (void *)gpu_metrics;</div><div class='del'>-	kfree(metrics);</div><div class='add'>+	kfree(metrics_x);</div><div class='ctx'> </div><div class='ctx'> 	return sizeof(*gpu_metrics);</div><div class='ctx'> }</div><div class='hunk'>@@ -2161,17 +2236,18 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (ret) {</div><div class='del'>-			dev_err(adev-&gt;dev,</div><div class='del'>-				"failed to send mode2 message \tparam: 0x%08x error code %d\n",</div><div class='del'>-				SMU_RESET_MODE_2, ret);</div><div class='add'>+		if (ret)</div><div class='ctx'> 			goto out;</div><div class='del'>-		}</div><div class='add'>+</div><div class='ctx'> 	} while (ret == -ETIME &amp;&amp; timeout);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;smu-&gt;message_lock);</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(adev-&gt;dev, "failed to send mode2 reset, error code %d",</div><div class='add'>+			ret);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2300,16 +2376,6 @@ static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int smu_v13_0_6_post_init(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-</div><div class='del'>-	if (!amdgpu_sriov_vf(adev) &amp;&amp; adev-&gt;ras_enabled)</div><div class='del'>-		return smu_v13_0_6_mca_set_debug_mode(smu, false);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct smu_context *smu = adev-&gt;powerplay.pp_handle;</div><div class='hunk'>@@ -2392,8 +2458,8 @@ static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT</div><div class='ctx'> </div><div class='ctx'> static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)</div><div class='ctx'> {</div><div class='del'>-	uint64_t ipid = entry-&gt;regs[MCA_REG_IDX_IPID];</div><div class='del'>-	uint32_t insthi;</div><div class='add'>+	u64 ipid = entry-&gt;regs[MCA_REG_IDX_IPID];</div><div class='add'>+	u32 instidhi, instid;</div><div class='ctx'> </div><div class='ctx'> 	/* NOTE: All MCA IPID register share the same format,</div><div class='ctx'> 	 * so the driver can share the MCMP1 register header file.</div><div class='hunk'>@@ -2402,9 +2468,15 @@ static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_</div><div class='ctx'> 	info-&gt;hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);</div><div class='ctx'> 	info-&gt;mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);</div><div class='ctx'> </div><div class='del'>-	insthi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);</div><div class='del'>-	info-&gt;aid = ((insthi &gt;&gt; 2) &amp; 0x03);</div><div class='del'>-	info-&gt;socket_id = insthi &amp; 0x03;</div><div class='add'>+	/*</div><div class='add'>+	 * Unfied DieID Format: SAASS. A:AID, S:Socket.</div><div class='add'>+	 * Unfied DieID[4] = InstanceId[0]</div><div class='add'>+	 * Unfied DieID[0:3] = InstanceIdHi[0:3]</div><div class='add'>+	 */</div><div class='add'>+	instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);</div><div class='add'>+	instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);</div><div class='add'>+	info-&gt;aid = ((instidhi &gt;&gt; 2) &amp; 0x03);</div><div class='add'>+	info-&gt;socket_id = ((instid &amp; 0x1) &lt;&lt; 2) | (instidhi &amp; 0x03);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,</div><div class='hunk'>@@ -2483,9 +2555,9 @@ static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (type == AMDGPU_MCA_ERROR_TYPE_UE &amp;&amp; umc_v12_0_is_uncorrectable_error(status0))</div><div class='add'>+	if (type == AMDGPU_MCA_ERROR_TYPE_UE &amp;&amp; umc_v12_0_is_uncorrectable_error(adev, status0))</div><div class='ctx'> 		*count = 1;</div><div class='del'>-	else if (type == AMDGPU_MCA_ERROR_TYPE_CE &amp;&amp; umc_v12_0_is_correctable_error(status0))</div><div class='add'>+	else if (type == AMDGPU_MCA_ERROR_TYPE_CE &amp;&amp; umc_v12_0_is_correctable_error(adev, status0))</div><div class='ctx'> 		*count = 1;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2496,13 +2568,15 @@ static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, st</div><div class='ctx'> 					  uint32_t *count)</div><div class='ctx'> {</div><div class='ctx'> 	u32 ext_error_code;</div><div class='add'>+	u32 err_cnt;</div><div class='ctx'> </div><div class='ctx'> 	ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry-&gt;regs[MCA_REG_IDX_STATUS]);</div><div class='add'>+	err_cnt = MCA_REG__MISC0__ERRCNT(entry-&gt;regs[MCA_REG_IDX_MISC0]);</div><div class='ctx'> </div><div class='ctx'> 	if (type == AMDGPU_MCA_ERROR_TYPE_UE &amp;&amp; ext_error_code == 0)</div><div class='del'>-		*count = 1;</div><div class='add'>+		*count = err_cnt;</div><div class='ctx'> 	else if (type == AMDGPU_MCA_ERROR_TYPE_CE &amp;&amp; ext_error_code == 6)</div><div class='del'>-		*count = 1;</div><div class='add'>+		*count = err_cnt;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2578,6 +2652,7 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct</div><div class='ctx'> 	uint32_t instlo;</div><div class='ctx'> </div><div class='ctx'> 	instlo = REG_GET_FIELD(entry-&gt;regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='ctx'> 	switch (instlo) {</div><div class='ctx'> 	case 0x36430400: /* SMNAID XCD 0 */</div><div class='ctx'> 	case 0x38430400: /* SMNAID XCD 1 */</div><div class='hunk'>@@ -2593,13 +2668,21 @@ static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct</div><div class='ctx'> static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,</div><div class='ctx'> 				  enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)</div><div class='ctx'> {</div><div class='add'>+	struct smu_context *smu = adev-&gt;powerplay.pp_handle;</div><div class='ctx'> 	uint32_t errcode, instlo;</div><div class='ctx'> </div><div class='ctx'> 	instlo = REG_GET_FIELD(entry-&gt;regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);</div><div class='add'>+	instlo &amp;= GENMASK(31, 1);</div><div class='ctx'> 	if (instlo != 0x03b30400)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	errcode = REG_GET_FIELD(entry-&gt;regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);</div><div class='add'>+	if (!(adev-&gt;flags &amp; AMD_IS_APU) &amp;&amp; smu-&gt;smc_fw_version &gt;= 0x00555600) {</div><div class='add'>+		errcode = MCA_REG__SYND__ERRORINFORMATION(entry-&gt;regs[MCA_REG_IDX_SYND]);</div><div class='add'>+		errcode &amp;= 0xff;</div><div class='add'>+	} else {</div><div class='add'>+		errcode = REG_GET_FIELD(entry-&gt;regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return mca_smu_check_error_code(adev, mca_ras, errcode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2812,6 +2895,13 @@ static int smu_v13_0_6_select_xgmi_plpd_policy(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ssize_t smu_v13_0_6_get_ecc_info(struct smu_context *smu,</div><div class='add'>+			void *table)</div><div class='add'>+{</div><div class='add'>+	/* Support ecc info by default */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {</div><div class='ctx'> 	/* init dpm */</div><div class='ctx'> 	.get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,</div><div class='hunk'>@@ -2856,6 +2946,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {</div><div class='ctx'> 	.log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,</div><div class='ctx'> 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,</div><div class='ctx'> 	.get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,</div><div class='add'>+	.get_pm_metrics = smu_v13_0_6_get_pm_metrics,</div><div class='ctx'> 	.get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,</div><div class='ctx'> 	.mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,</div><div class='ctx'> 	.mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported,</div><div class='hunk'>@@ -2865,7 +2956,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {</div><div class='ctx'> 	.i2c_init = smu_v13_0_6_i2c_control_init,</div><div class='ctx'> 	.i2c_fini = smu_v13_0_6_i2c_control_fini,</div><div class='ctx'> 	.send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,</div><div class='del'>-	.post_init = smu_v13_0_6_post_init,</div><div class='add'>+	.get_ecc_info = smu_v13_0_6_get_ecc_info,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c<br/>index 81eafed76045..59606a19e3d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c</a></div><div class='hunk'>@@ -140,6 +140,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =</div><div class='ctx'> 	MSG_MAP(AllowGpo,			PPSMC_MSG_SetGpoAllow,           0),</div><div class='ctx'> 	MSG_MAP(GetPptLimit,			PPSMC_MSG_GetPptLimit,                 0),</div><div class='ctx'> 	MSG_MAP(NotifyPowerSource,		PPSMC_MSG_NotifyPowerSource,           0),</div><div class='add'>+	MSG_MAP(EnableUCLKShadow,		PPSMC_MSG_EnableUCLKShadow,            0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {</div><div class='hunk'>@@ -222,6 +223,7 @@ static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {</div><div class='ctx'> 	TAB_MAP(ACTIVITY_MONITOR_COEFF),</div><div class='ctx'> 	[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},</div><div class='ctx'> 	TAB_MAP(OVERDRIVE),</div><div class='add'>+	TAB_MAP(WIFIBAND),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {</div><div class='hunk'>@@ -512,6 +514,9 @@ static int smu_v13_0_7_tables_init(struct smu_context *smu)</div><div class='ctx'> 		       AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> 	SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,</div><div class='ctx'> 			PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);</div><div class='add'>+	SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,</div><div class='add'>+		       sizeof(WifiBandEntryTable_t), PAGE_SIZE,</div><div class='add'>+		       AMDGPU_GEM_DOMAIN_VRAM);</div><div class='ctx'> </div><div class='ctx'> 	smu_table-&gt;metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);</div><div class='ctx'> 	if (!smu_table-&gt;metrics_table)</div><div class='hunk'>@@ -2515,38 +2520,6 @@ static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int smu_v13_0_7_baco_enter(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct smu_baco_context *smu_baco = &amp;smu-&gt;smu_baco;</div><div class='del'>-	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev))</div><div class='del'>-		return smu_v13_0_baco_set_armd3_sequence(smu,</div><div class='del'>-				(smu_baco-&gt;maco_support &amp;&amp; amdgpu_runtime_pm != 1) ?</div><div class='del'>-					BACO_SEQ_BAMACO : BACO_SEQ_BACO);</div><div class='del'>-	else</div><div class='del'>-		return smu_v13_0_baco_enter(smu);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int smu_v13_0_7_baco_exit(struct smu_context *smu)</div><div class='del'>-{</div><div class='del'>-	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (adev-&gt;in_runpm &amp;&amp; smu_cmn_is_audio_func_enabled(adev)) {</div><div class='del'>-		/* Wait for PMFW handling for the Dstate change */</div><div class='del'>-		usleep_range(10000, 11000);</div><div class='del'>-		ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);</div><div class='del'>-	} else {</div><div class='del'>-		ret = smu_v13_0_baco_exit(smu);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!ret)</div><div class='del'>-		adev-&gt;gfx.is_poweron = false;</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)</div><div class='ctx'> {</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='hunk'>@@ -2567,6 +2540,11 @@ static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,</div><div class='ctx'> 					       NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)</div><div class='add'>+{</div><div class='add'>+	return smu-&gt;smc_fw_version &gt; 0x00524600;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {</div><div class='ctx'> 	.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,</div><div class='ctx'> 	.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,</div><div class='hunk'>@@ -2626,15 +2604,16 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {</div><div class='ctx'> 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,</div><div class='ctx'> 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,</div><div class='ctx'> 	.baco_is_support = smu_v13_0_baco_is_support,</div><div class='del'>-	.baco_get_state = smu_v13_0_baco_get_state,</div><div class='del'>-	.baco_set_state = smu_v13_0_baco_set_state,</div><div class='del'>-	.baco_enter = smu_v13_0_7_baco_enter,</div><div class='del'>-	.baco_exit = smu_v13_0_7_baco_exit,</div><div class='add'>+	.baco_enter = smu_v13_0_baco_enter,</div><div class='add'>+	.baco_exit = smu_v13_0_baco_exit,</div><div class='ctx'> 	.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,</div><div class='ctx'> 	.mode1_reset = smu_v13_0_mode1_reset,</div><div class='ctx'> 	.set_mp1_state = smu_v13_0_7_set_mp1_state,</div><div class='ctx'> 	.set_df_cstate = smu_v13_0_7_set_df_cstate,</div><div class='ctx'> 	.gpo_control = smu_v13_0_gpo_control,</div><div class='add'>+	.is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,</div><div class='add'>+	.enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,</div><div class='add'>+	.set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c<br/>index d8f8ad0e7137..4894f7ee737b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c</a></div><div class='hunk'>@@ -224,7 +224,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)</div><div class='ctx'> 	if (smu-&gt;is_apu)</div><div class='ctx'> 		adev-&gt;pm.fw_version = smu_version;</div><div class='ctx'> </div><div class='del'>-	switch (adev-&gt;ip_versions[MP1_HWIP][0]) {</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(14, 0, 2):</div><div class='ctx'> 		smu-&gt;smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -235,7 +235,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(adev-&gt;dev, "smu unsupported IP version: 0x%x.\n",</div><div class='del'>-			adev-&gt;ip_versions[MP1_HWIP][0]);</div><div class='add'>+			amdgpu_ip_version(adev, MP1_HWIP, 0));</div><div class='ctx'> 		smu-&gt;smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -733,7 +733,7 @@ int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	struct amdgpu_device *adev = smu-&gt;adev;</div><div class='ctx'> </div><div class='del'>-	switch (adev-&gt;ip_versions[MP1_HWIP][0]) {</div><div class='add'>+	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {</div><div class='ctx'> 	case IP_VERSION(14, 0, 2):</div><div class='ctx'> 	case IP_VERSION(14, 0, 0):</div><div class='ctx'> 		if (!(adev-&gt;pm.pp_feature &amp; PP_GFXOFF_MASK))</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c<br/>index 03b38c3a9968..47fdbae4adfc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c</a></div><div class='hunk'>@@ -246,11 +246,20 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,</div><div class='ctx'> 		*value = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_AVERAGE_UCLK:</div><div class='del'>-		*value = 0;</div><div class='add'>+		*value = metrics-&gt;MemclkFrequency;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_AVERAGE_FCLK:</div><div class='ctx'> 		*value = metrics-&gt;FclkFrequency;</div><div class='ctx'> 		break;</div><div class='add'>+	case METRICS_AVERAGE_VPECLK:</div><div class='add'>+		*value = metrics-&gt;VpeclkFrequency;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_AVERAGE_IPUCLK:</div><div class='add'>+		*value = metrics-&gt;IpuclkFrequency;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_AVERAGE_MPIPUCLK:</div><div class='add'>+		*value = metrics-&gt;MpipuclkFrequency;</div><div class='add'>+		break;</div><div class='ctx'> 	case METRICS_AVERAGE_GFXACTIVITY:</div><div class='ctx'> 		*value = metrics-&gt;GfxActivity / 100;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -270,8 +279,26 @@ static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,</div><div class='ctx'> 		*value = metrics-&gt;SocTemperature / 100 *</div><div class='ctx'> 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;</div><div class='ctx'> 		break;</div><div class='del'>-	case METRICS_THROTTLER_STATUS:</div><div class='del'>-		*value = 0;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_PROCHOT:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_PROCHOT;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_SPL:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_SPL;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_FPPT:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_FPPT;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_SPPT:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_SPPT;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_THM_CORE:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_THM_CORE;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_THM_GFX:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_THM_GFX;</div><div class='add'>+		break;</div><div class='add'>+	case METRICS_THROTTLER_RESIDENCY_THM_SOC:</div><div class='add'>+		*value = metrics-&gt;ThrottleResidency_THM_SOC;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case METRICS_VOLTAGE_VDDGFX:</div><div class='ctx'> 		*value = 0;</div><div class='hunk'>@@ -498,6 +525,8 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,</div><div class='ctx'> 		sizeof(uint16_t) * 16);</div><div class='ctx'> 	gpu_metrics-&gt;average_dram_reads = metrics.DRAMReads;</div><div class='ctx'> 	gpu_metrics-&gt;average_dram_writes = metrics.DRAMWrites;</div><div class='add'>+	gpu_metrics-&gt;average_ipu_reads = metrics.IpuReads;</div><div class='add'>+	gpu_metrics-&gt;average_ipu_writes = metrics.IpuWrites;</div><div class='ctx'> </div><div class='ctx'> 	gpu_metrics-&gt;average_socket_power = metrics.SocketPower;</div><div class='ctx'> 	gpu_metrics-&gt;average_ipu_power = metrics.IpuPower;</div><div class='hunk'>@@ -505,6 +534,7 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,</div><div class='ctx'> 	gpu_metrics-&gt;average_gfx_power = metrics.GfxPower;</div><div class='ctx'> 	gpu_metrics-&gt;average_dgpu_power = metrics.dGpuPower;</div><div class='ctx'> 	gpu_metrics-&gt;average_all_core_power = metrics.AllCorePower;</div><div class='add'>+	gpu_metrics-&gt;average_sys_power = metrics.Psys;</div><div class='ctx'> 	memcpy(&amp;gpu_metrics-&gt;average_core_power[0],</div><div class='ctx'> 		&amp;metrics.CorePower[0],</div><div class='ctx'> 		sizeof(uint16_t) * 16);</div><div class='hunk'>@@ -515,6 +545,8 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,</div><div class='ctx'> 	gpu_metrics-&gt;average_fclk_frequency = metrics.FclkFrequency;</div><div class='ctx'> 	gpu_metrics-&gt;average_vclk_frequency = metrics.VclkFrequency;</div><div class='ctx'> 	gpu_metrics-&gt;average_ipuclk_frequency = metrics.IpuclkFrequency;</div><div class='add'>+	gpu_metrics-&gt;average_uclk_frequency = metrics.MemclkFrequency;</div><div class='add'>+	gpu_metrics-&gt;average_mpipu_frequency = metrics.MpipuclkFrequency;</div><div class='ctx'> </div><div class='ctx'> 	memcpy(&amp;gpu_metrics-&gt;current_coreclk[0],</div><div class='ctx'> 		&amp;metrics.CoreFrequency[0],</div><div class='hunk'>@@ -522,6 +554,14 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,</div><div class='ctx'> 	gpu_metrics-&gt;current_core_maxfreq = metrics.InfrastructureCpuMaxFreq;</div><div class='ctx'> 	gpu_metrics-&gt;current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq;</div><div class='ctx'> </div><div class='add'>+	gpu_metrics-&gt;throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_spl = metrics.ThrottleResidency_SPL;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_fppt = metrics.ThrottleResidency_FPPT;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_sppt = metrics.ThrottleResidency_SPPT;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_thm_core = metrics.ThrottleResidency_THM_CORE;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_thm_gfx = metrics.ThrottleResidency_THM_GFX;</div><div class='add'>+	gpu_metrics-&gt;throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC;</div><div class='add'>+</div><div class='ctx'> 	gpu_metrics-&gt;time_filter_alphavalue = metrics.FilterAlphaValue;</div><div class='ctx'> 	gpu_metrics-&gt;system_clock_counter = ktime_get_boottime_ns();</div><div class='ctx'> </div><div class='hunk'>@@ -1045,6 +1085,25 @@ static int smu_v14_0_0_set_umsch_mm_enable(struct smu_context *smu,</div><div class='ctx'> 					       0, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)</div><div class='add'>+{</div><div class='add'>+	DpmClocks_t *clk_table = smu-&gt;smu_table.clocks_table;</div><div class='add'>+	uint8_t idx;</div><div class='add'>+</div><div class='add'>+	/* Only the Clock information of SOC and VPE is copied to provide VPE DPM settings for use. */</div><div class='add'>+	for (idx = 0; idx &lt; NUM_SOCCLK_DPM_LEVELS; idx++) {</div><div class='add'>+		clock_table-&gt;SocClocks[idx].Freq = (idx &lt; clk_table-&gt;NumSocClkLevelsEnabled) ? clk_table-&gt;SocClocks[idx]:0;</div><div class='add'>+		clock_table-&gt;SocClocks[idx].Vol = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (idx = 0; idx &lt; NUM_VPE_DPM_LEVELS; idx++) {</div><div class='add'>+		clock_table-&gt;VPEClocks[idx].Freq = (idx &lt; clk_table-&gt;VpeClkLevelsEnabled) ? clk_table-&gt;VPEClocks[idx]:0;</div><div class='add'>+		clock_table-&gt;VPEClocks[idx].Vol = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {</div><div class='ctx'> 	.check_fw_status = smu_v14_0_check_fw_status,</div><div class='ctx'> 	.check_fw_version = smu_v14_0_check_fw_version,</div><div class='hunk'>@@ -1075,6 +1134,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {</div><div class='ctx'> 	.set_gfx_power_up_by_imu = smu_v14_0_set_gfx_power_up_by_imu,</div><div class='ctx'> 	.dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable,</div><div class='ctx'> 	.dpm_set_umsch_mm_enable = smu_v14_0_0_set_umsch_mm_enable,</div><div class='add'>+	.get_dpm_clock_table = smu_14_0_0_get_dpm_table,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br/>index 001a5cf09657..00cd615bbcdc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c</a></div><div class='hunk'>@@ -989,6 +989,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)</div><div class='ctx'> 	case METRICS_VERSION(1, 4):</div><div class='ctx'> 		structure_size = sizeof(struct gpu_metrics_v1_4);</div><div class='ctx'> 		break;</div><div class='add'>+	case METRICS_VERSION(1, 5):</div><div class='add'>+		structure_size = sizeof(struct gpu_metrics_v1_5);</div><div class='add'>+		break;</div><div class='ctx'> 	case METRICS_VERSION(2, 0):</div><div class='ctx'> 		structure_size = sizeof(struct gpu_metrics_v2_0);</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h<br/>index 80b3c3efc006..6f4d212607d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/amd/pm/swsmu/smu_internal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/amd/pm/swsmu/smu_internal.h</a></div><div class='hunk'>@@ -97,6 +97,10 @@</div><div class='ctx'> #define smu_get_default_config_table_settings(smu, config_table)	smu_ppt_funcs(get_default_config_table_settings, -EOPNOTSUPP, smu, config_table)</div><div class='ctx'> #define smu_set_config_table(smu, config_table)				smu_ppt_funcs(set_config_table, -EOPNOTSUPP, smu, config_table)</div><div class='ctx'> #define smu_init_pptable_microcode(smu)					smu_ppt_funcs(init_pptable_microcode, 0, smu)</div><div class='add'>+#define smu_notify_rlc_state(smu, en)					smu_ppt_funcs(notify_rlc_state, 0, smu, en)</div><div class='add'>+#define smu_is_asic_wbrf_supported(smu)			smu_ppt_funcs(is_asic_wbrf_supported, false, smu)</div><div class='add'>+#define smu_enable_uclk_shadow(smu, enable)		smu_ppt_funcs(enable_uclk_shadow, 0, smu, enable)</div><div class='add'>+#define smu_set_wbrf_exclusion_ranges(smu, freq_band_range)		smu_ppt_funcs(set_wbrf_exclusion_ranges, -EOPNOTSUPP, smu, freq_band_range)</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c<br/>index dc01c43f6193..d72c22dcf685 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/arm/malidp_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/arm/malidp_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/arm/malidp_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/arm/malidp_crtc.c</a></div><div class='hunk'>@@ -221,7 +221,7 @@ static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The size of the ctm is checked in</div><div class='del'>-	 * drm_atomic_replace_property_blob_from_id.</div><div class='add'>+	 * drm_property_replace_blob_from_id.</div><div class='ctx'> 	 */</div><div class='ctx'> 	ctm = (struct drm_color_ctm *)state-&gt;ctm-&gt;data;</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(ctm-&gt;matrix); ++i) {</div><div class='head'>diff --git a/drivers/gpu/drm/ast/ast_i2c.c b/drivers/gpu/drm/ast/ast_i2c.c<br/>index 0e845e7acd9b..e5d3f7121de4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ast/ast_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/ast/ast_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ast/ast_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ast/ast_i2c.c</a></div><div class='hunk'>@@ -120,7 +120,6 @@ struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	i2c-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	i2c-&gt;adapter.dev.parent = dev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;dev = dev;</div><div class='ctx'> 	i2c_set_adapdata(&amp;i2c-&gt;adapter, i2c);</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig<br/>index 19d2dc05c397..efd996f6c138 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/Kconfig</a></div><div class='hunk'>@@ -330,6 +330,7 @@ config DRM_TOSHIBA_TC358768</div><div class='ctx'> 	select REGMAP_I2C</div><div class='ctx'> 	select DRM_PANEL</div><div class='ctx'> 	select DRM_MIPI_DSI</div><div class='add'>+	select VIDEOMODE_HELPERS</div><div class='ctx'> 	help</div><div class='ctx'> 	  Toshiba TC358768AXBG/TC358778XBG DSI bridge chip driver.</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/bridge/aux-bridge.c b/drivers/gpu/drm/bridge/aux-bridge.c<br/>index 49d7c2ab1ecc..b29980f95379 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/aux-bridge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/aux-bridge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/aux-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/aux-bridge.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/auxiliary_bus.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_bridge.h&gt;</div><div class='ctx'> #include &lt;drm/bridge/aux-bridge.h&gt;</div><div class='hunk'>@@ -57,7 +58,7 @@ int drm_aux_bridge_register(struct device *parent)</div><div class='ctx'> 	adev-&gt;id = ret;</div><div class='ctx'> 	adev-&gt;name = "aux_bridge";</div><div class='ctx'> 	adev-&gt;dev.parent = parent;</div><div class='del'>-	adev-&gt;dev.of_node = parent-&gt;of_node;</div><div class='add'>+	adev-&gt;dev.of_node = of_node_get(parent-&gt;of_node);</div><div class='ctx'> 	adev-&gt;dev.release = drm_aux_bridge_release;</div><div class='ctx'> </div><div class='ctx'> 	ret = auxiliary_device_init(adev);</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/aux-hpd-bridge.c b/drivers/gpu/drm/bridge/aux-hpd-bridge.c<br/>index 1999a053d59b..bb55f697a181 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/aux-hpd-bridge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/aux-hpd-bridge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/aux-hpd-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/aux-hpd-bridge.c</a></div><div class='hunk'>@@ -68,9 +68,9 @@ struct device *drm_dp_hpd_bridge_register(struct device *parent,</div><div class='ctx'> 	adev-&gt;id = ret;</div><div class='ctx'> 	adev-&gt;name = "dp_hpd_bridge";</div><div class='ctx'> 	adev-&gt;dev.parent = parent;</div><div class='del'>-	adev-&gt;dev.of_node = parent-&gt;of_node;</div><div class='add'>+	adev-&gt;dev.of_node = of_node_get(parent-&gt;of_node);</div><div class='ctx'> 	adev-&gt;dev.release = drm_aux_hpd_bridge_release;</div><div class='del'>-	adev-&gt;dev.platform_data = np;</div><div class='add'>+	adev-&gt;dev.platform_data = of_node_get(np);</div><div class='ctx'> </div><div class='ctx'> 	ret = auxiliary_device_init(adev);</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c<br/>index e48823a4f1ed..7f41525f7a6e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/panel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/panel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/panel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/panel.c</a></div><div class='hunk'>@@ -4,8 +4,6 @@</div><div class='ctx'>  * Copyright (C) 2017 Broadcom</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-</div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_bridge.h&gt;</div><div class='ctx'> #include &lt;drm/drm_connector.h&gt;</div><div class='hunk'>@@ -21,7 +19,6 @@ struct panel_bridge {</div><div class='ctx'> 	struct drm_bridge bridge;</div><div class='ctx'> 	struct drm_connector connector;</div><div class='ctx'> 	struct drm_panel *panel;</div><div class='del'>-	struct device_link *link;</div><div class='ctx'> 	u32 connector_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -63,24 +60,13 @@ static int panel_bridge_attach(struct drm_bridge *bridge,</div><div class='ctx'> {</div><div class='ctx'> 	struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);</div><div class='ctx'> 	struct drm_connector *connector = &amp;panel_bridge-&gt;connector;</div><div class='del'>-	struct drm_panel *panel = panel_bridge-&gt;panel;</div><div class='del'>-	struct drm_device *drm_dev = bridge-&gt;dev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	panel_bridge-&gt;link = device_link_add(drm_dev-&gt;dev, panel-&gt;dev,</div><div class='del'>-					     DL_FLAG_STATELESS);</div><div class='del'>-	if (!panel_bridge-&gt;link) {</div><div class='del'>-		DRM_ERROR("Failed to add device link between %s and %s\n",</div><div class='del'>-			  dev_name(drm_dev-&gt;dev), dev_name(panel-&gt;dev));</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (flags &amp; DRM_BRIDGE_ATTACH_NO_CONNECTOR)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!bridge-&gt;encoder) {</div><div class='ctx'> 		DRM_ERROR("Missing encoder\n");</div><div class='del'>-		device_link_del(panel_bridge-&gt;link);</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -92,7 +78,6 @@ static int panel_bridge_attach(struct drm_bridge *bridge,</div><div class='ctx'> 				 panel_bridge-&gt;connector_type);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_ERROR("Failed to initialize connector\n");</div><div class='del'>-		device_link_del(panel_bridge-&gt;link);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -115,8 +100,6 @@ static void panel_bridge_detach(struct drm_bridge *bridge)</div><div class='ctx'> 	struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);</div><div class='ctx'> 	struct drm_connector *connector = &amp;panel_bridge-&gt;connector;</div><div class='ctx'> </div><div class='del'>-	device_link_del(panel_bridge-&gt;link);</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Cleanup the connector if we know it was initialized.</div><div class='ctx'> 	 *</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c<br/>index 8161b1a1a4b1..541e4f5afc4c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/parade-ps8640.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/parade-ps8640.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/parade-ps8640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/parade-ps8640.c</a></div><div class='hunk'>@@ -210,7 +210,7 @@ static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,</div><div class='ctx'> 	struct ps8640 *ps_bridge = aux_to_ps8640(aux);</div><div class='ctx'> 	struct regmap *map = ps_bridge-&gt;regmap[PAGE0_DP_CNTL];</div><div class='ctx'> 	struct device *dev = &amp;ps_bridge-&gt;page[PAGE0_DP_CNTL]-&gt;dev;</div><div class='del'>-	unsigned int len = msg-&gt;size;</div><div class='add'>+	size_t len = msg-&gt;size;</div><div class='ctx'> 	unsigned int data;</div><div class='ctx'> 	unsigned int base;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -330,11 +330,12 @@ static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,</div><div class='ctx'> 				return ret;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			buf[i] = data;</div><div class='add'>+			if (i &lt; msg-&gt;size)</div><div class='add'>+				buf[i] = data;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return len;</div><div class='add'>+	return min(len, msg-&gt;size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c<br/>index fa63a21bdd1c..ca74a20015b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/synopsys/dw-hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/synopsys/dw-hdmi.c</a></div><div class='hunk'>@@ -516,7 +516,6 @@ static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)</div><div class='ctx'> 	init_completion(&amp;i2c-&gt;cmp);</div><div class='ctx'> </div><div class='ctx'> 	adap = &amp;i2c-&gt;adap;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	adap-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	adap-&gt;dev.parent = hdmi-&gt;dev;</div><div class='ctx'> 	adap-&gt;algo = &amp;dw_hdmi_algorithm;</div><div class='head'>diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c<br/>index 9095d1453710..62cc3893dca5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/ti-sn65dsi86.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/bridge/ti-sn65dsi86.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/bridge/ti-sn65dsi86.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/bridge/ti-sn65dsi86.c</a></div><div class='hunk'>@@ -527,6 +527,7 @@ static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 	u32 request_val = AUX_CMD_REQ(msg-&gt;request);</div><div class='ctx'> 	u8 *buf = msg-&gt;buffer;</div><div class='ctx'> 	unsigned int len = msg-&gt;size;</div><div class='add'>+	unsigned int short_len;</div><div class='ctx'> 	unsigned int val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];</div><div class='hunk'>@@ -600,7 +601,8 @@ static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (val &amp; AUX_IRQ_STATUS_AUX_SHORT) {</div><div class='del'>-		ret = regmap_read(pdata-&gt;regmap, SN_AUX_LENGTH_REG, &amp;len);</div><div class='add'>+		ret = regmap_read(pdata-&gt;regmap, SN_AUX_LENGTH_REG, &amp;short_len);</div><div class='add'>+		len = min(len, short_len);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto exit;</div><div class='ctx'> 	} else if (val &amp; AUX_IRQ_STATUS_NAT_I2C_FAIL) {</div><div class='head'>diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh<br/>index 331a61e0d25a..106f2d40d222 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ci/build.sh?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/ci/build.sh</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ci/build.sh?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ci/build.sh</a></div><div class='hunk'>@@ -59,6 +59,9 @@ git config --global user.email "fdo@example.com"</div><div class='ctx'> git config --global user.name "freedesktop.org CI"</div><div class='ctx'> git config --global pull.rebase true</div><div class='ctx'> </div><div class='add'>+# cleanup git state on the worker</div><div class='add'>+rm -rf .git/rebase-merge</div><div class='add'>+</div><div class='ctx'> # Try to merge fixes from target repo</div><div class='ctx'> if [ "$(git ls-remote --exit-code --heads ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes)" ]; then</div><div class='ctx'>     git pull ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes</div><div class='head'>diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c<br/>index d72b6f9a352c..b1ca3a1100da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/display/drm_dp_helper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/display/drm_dp_helper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/display/drm_dp_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/display/drm_dp_helper.c</a></div><div class='hunk'>@@ -2102,7 +2102,6 @@ int drm_dp_aux_register(struct drm_dp_aux *aux)</div><div class='ctx'> 	if (!aux-&gt;ddc.algo)</div><div class='ctx'> 		drm_dp_aux_init(aux);</div><div class='ctx'> </div><div class='del'>-	aux-&gt;ddc.class = I2C_CLASS_DDC;</div><div class='ctx'> 	aux-&gt;ddc.owner = THIS_MODULE;</div><div class='ctx'> 	aux-&gt;ddc.dev.parent = aux-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c<br/>index 8ca01a6bf645..bd6c24d4213c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/display/drm_dp_mst_topology.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/display/drm_dp_mst_topology.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/display/drm_dp_mst_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/display/drm_dp_mst_topology.c</a></div><div class='hunk'>@@ -5926,7 +5926,6 @@ static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port)</div><div class='ctx'> 	aux-&gt;ddc.algo_data = aux;</div><div class='ctx'> 	aux-&gt;ddc.retries = 3;</div><div class='ctx'> </div><div class='del'>-	aux-&gt;ddc.class = I2C_CLASS_DDC;</div><div class='ctx'> 	aux-&gt;ddc.owner = THIS_MODULE;</div><div class='ctx'> 	/* FIXME: set the kdev of the port's connector as parent */</div><div class='ctx'> 	aux-&gt;ddc.dev.parent = parent_dev;</div><div class='head'>diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c<br/>index c31fc0b48c31..a91737adf8e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_atomic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic.c</a></div><div class='hunk'>@@ -733,6 +733,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p,</div><div class='ctx'> 		   drm_get_color_encoding_name(state-&gt;color_encoding));</div><div class='ctx'> 	drm_printf(p, "\tcolor-range=%s\n",</div><div class='ctx'> 		   drm_get_color_range_name(state-&gt;color_range));</div><div class='add'>+	drm_printf(p, "\tcolor_mgmt_changed=%d\n", state-&gt;color_mgmt_changed);</div><div class='ctx'> </div><div class='ctx'> 	if (plane-&gt;funcs-&gt;atomic_print_state)</div><div class='ctx'> 		plane-&gt;funcs-&gt;atomic_print_state(p, state);</div><div class='head'>diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c<br/>index c98a766ca3bd..39ef0a6addeb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_helper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_atomic_helper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_helper.c</a></div><div class='hunk'>@@ -2014,7 +2014,7 @@ int drm_atomic_helper_commit(struct drm_device *dev,</div><div class='ctx'> 			return ret;</div><div class='ctx'> </div><div class='ctx'> 		drm_atomic_helper_async_commit(dev, state);</div><div class='del'>-		drm_atomic_helper_cleanup_planes(dev, state);</div><div class='add'>+		drm_atomic_helper_unprepare_planes(dev, state);</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2074,7 +2074,7 @@ int drm_atomic_helper_commit(struct drm_device *dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='del'>-	drm_atomic_helper_cleanup_planes(dev, state);</div><div class='add'>+	drm_atomic_helper_unprepare_planes(dev, state);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_atomic_helper_commit);</div><div class='hunk'>@@ -2652,6 +2652,39 @@ fail_prepare_fb:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_atomic_helper_prepare_planes);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * drm_atomic_helper_unprepare_planes - release plane resources on aborts</div><div class='add'>+ * @dev: DRM device</div><div class='add'>+ * @state: atomic state object with old state structures</div><div class='add'>+ *</div><div class='add'>+ * This function cleans up plane state, specifically framebuffers, from the</div><div class='add'>+ * atomic state. It undoes the effects of drm_atomic_helper_prepare_planes()</div><div class='add'>+ * when aborting an atomic commit. For cleaning up after a successful commit</div><div class='add'>+ * use drm_atomic_helper_cleanup_planes().</div><div class='add'>+ */</div><div class='add'>+void drm_atomic_helper_unprepare_planes(struct drm_device *dev,</div><div class='add'>+					struct drm_atomic_state *state)</div><div class='add'>+{</div><div class='add'>+	struct drm_plane *plane;</div><div class='add'>+	struct drm_plane_state *new_plane_state;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for_each_new_plane_in_state(state, plane, new_plane_state, i) {</div><div class='add'>+		const struct drm_plane_helper_funcs *funcs = plane-&gt;helper_private;</div><div class='add'>+</div><div class='add'>+		if (funcs-&gt;end_fb_access)</div><div class='add'>+			funcs-&gt;end_fb_access(plane, new_plane_state);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_new_plane_in_state(state, plane, new_plane_state, i) {</div><div class='add'>+		const struct drm_plane_helper_funcs *funcs = plane-&gt;helper_private;</div><div class='add'>+</div><div class='add'>+		if (funcs-&gt;cleanup_fb)</div><div class='add'>+			funcs-&gt;cleanup_fb(plane, new_plane_state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(drm_atomic_helper_unprepare_planes);</div><div class='add'>+</div><div class='ctx'> static bool plane_crtc_active(const struct drm_plane_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	return state-&gt;crtc &amp;&amp; state-&gt;crtc-&gt;state-&gt;active;</div><div class='hunk'>@@ -2786,6 +2819,17 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 		funcs-&gt;atomic_flush(crtc, old_state);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Signal end of framebuffer access here before hw_done. After hw_done,</div><div class='add'>+	 * a later commit might have already released the plane state.</div><div class='add'>+	 */</div><div class='add'>+	for_each_old_plane_in_state(old_state, plane, old_plane_state, i) {</div><div class='add'>+		const struct drm_plane_helper_funcs *funcs = plane-&gt;helper_private;</div><div class='add'>+</div><div class='add'>+		if (funcs-&gt;end_fb_access)</div><div class='add'>+			funcs-&gt;end_fb_access(plane, old_plane_state);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_atomic_helper_commit_planes);</div><div class='ctx'> </div><div class='hunk'>@@ -2913,40 +2957,22 @@ EXPORT_SYMBOL(drm_atomic_helper_disable_planes_on_crtc);</div><div class='ctx'>  * configuration. Hence the old configuration must be perserved in @old_state to</div><div class='ctx'>  * be able to call this function.</div><div class='ctx'>  *</div><div class='del'>- * This function must also be called on the new state when the atomic update</div><div class='del'>- * fails at any point after calling drm_atomic_helper_prepare_planes().</div><div class='add'>+ * This function may not be called on the new state when the atomic update</div><div class='add'>+ * fails at any point after calling drm_atomic_helper_prepare_planes(). Use</div><div class='add'>+ * drm_atomic_helper_unprepare_planes() in this case.</div><div class='ctx'>  */</div><div class='ctx'> void drm_atomic_helper_cleanup_planes(struct drm_device *dev,</div><div class='ctx'> 				      struct drm_atomic_state *old_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_plane *plane;</div><div class='del'>-	struct drm_plane_state *old_plane_state, *new_plane_state;</div><div class='add'>+	struct drm_plane_state *old_plane_state;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) {</div><div class='add'>+	for_each_old_plane_in_state(old_state, plane, old_plane_state, i) {</div><div class='ctx'> 		const struct drm_plane_helper_funcs *funcs = plane-&gt;helper_private;</div><div class='ctx'> </div><div class='del'>-		if (funcs-&gt;end_fb_access)</div><div class='del'>-			funcs-&gt;end_fb_access(plane, new_plane_state);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) {</div><div class='del'>-		const struct drm_plane_helper_funcs *funcs;</div><div class='del'>-		struct drm_plane_state *plane_state;</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * This might be called before swapping when commit is aborted,</div><div class='del'>-		 * in which case we have to cleanup the new state.</div><div class='del'>-		 */</div><div class='del'>-		if (old_plane_state == plane-&gt;state)</div><div class='del'>-			plane_state = new_plane_state;</div><div class='del'>-		else</div><div class='del'>-			plane_state = old_plane_state;</div><div class='del'>-</div><div class='del'>-		funcs = plane-&gt;helper_private;</div><div class='del'>-</div><div class='ctx'> 		if (funcs-&gt;cleanup_fb)</div><div class='del'>-			funcs-&gt;cleanup_fb(plane, plane_state);</div><div class='add'>+			funcs-&gt;cleanup_fb(plane, old_plane_state);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes);</div><div class='head'>diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c<br/>index 54975de44a0e..519228eb1095 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_state_helper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_atomic_state_helper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_state_helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_state_helper.c</a></div><div class='hunk'>@@ -352,6 +352,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,</div><div class='ctx'> 	state-&gt;fence = NULL;</div><div class='ctx'> 	state-&gt;commit = NULL;</div><div class='ctx'> 	state-&gt;fb_damage_clips = NULL;</div><div class='add'>+	state-&gt;color_mgmt_changed = false;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c<br/>index aee4a65d4959..29d4940188d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_uapi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_atomic_uapi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_atomic_uapi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_atomic_uapi.c</a></div><div class='hunk'>@@ -362,48 +362,6 @@ static s32 __user *get_out_fence_for_connector(struct drm_atomic_state *state,</div><div class='ctx'> 	return fence_ptr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int</div><div class='del'>-drm_atomic_replace_property_blob_from_id(struct drm_device *dev,</div><div class='del'>-					 struct drm_property_blob **blob,</div><div class='del'>-					 uint64_t blob_id,</div><div class='del'>-					 ssize_t expected_size,</div><div class='del'>-					 ssize_t expected_elem_size,</div><div class='del'>-					 bool *replaced)</div><div class='del'>-{</div><div class='del'>-	struct drm_property_blob *new_blob = NULL;</div><div class='del'>-</div><div class='del'>-	if (blob_id != 0) {</div><div class='del'>-		new_blob = drm_property_lookup_blob(dev, blob_id);</div><div class='del'>-		if (new_blob == NULL) {</div><div class='del'>-			drm_dbg_atomic(dev,</div><div class='del'>-				       "cannot find blob ID %llu\n", blob_id);</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (expected_size &gt; 0 &amp;&amp;</div><div class='del'>-		    new_blob-&gt;length != expected_size) {</div><div class='del'>-			drm_dbg_atomic(dev,</div><div class='del'>-				       "[BLOB:%d] length %zu different from expected %zu\n",</div><div class='del'>-				       new_blob-&gt;base.id, new_blob-&gt;length, expected_size);</div><div class='del'>-			drm_property_blob_put(new_blob);</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		if (expected_elem_size &gt; 0 &amp;&amp;</div><div class='del'>-		    new_blob-&gt;length % expected_elem_size != 0) {</div><div class='del'>-			drm_dbg_atomic(dev,</div><div class='del'>-				       "[BLOB:%d] length %zu not divisible by element size %zu\n",</div><div class='del'>-				       new_blob-&gt;base.id, new_blob-&gt;length, expected_elem_size);</div><div class='del'>-			drm_property_blob_put(new_blob);</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	*replaced |= drm_property_replace_blob(blob, new_blob);</div><div class='del'>-	drm_property_blob_put(new_blob);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,</div><div class='ctx'> 		struct drm_crtc_state *state, struct drm_property *property,</div><div class='ctx'> 		uint64_t val)</div><div class='hunk'>@@ -424,7 +382,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,</div><div class='ctx'> 	} else if (property == config-&gt;prop_vrr_enabled) {</div><div class='ctx'> 		state-&gt;vrr_enabled = val;</div><div class='ctx'> 	} else if (property == config-&gt;degamma_lut_property) {</div><div class='del'>-		ret = drm_atomic_replace_property_blob_from_id(dev,</div><div class='add'>+		ret = drm_property_replace_blob_from_id(dev,</div><div class='ctx'> 					&amp;state-&gt;degamma_lut,</div><div class='ctx'> 					val,</div><div class='ctx'> 					-1, sizeof(struct drm_color_lut),</div><div class='hunk'>@@ -432,7 +390,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,</div><div class='ctx'> 		state-&gt;color_mgmt_changed |= replaced;</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	} else if (property == config-&gt;ctm_property) {</div><div class='del'>-		ret = drm_atomic_replace_property_blob_from_id(dev,</div><div class='add'>+		ret = drm_property_replace_blob_from_id(dev,</div><div class='ctx'> 					&amp;state-&gt;ctm,</div><div class='ctx'> 					val,</div><div class='ctx'> 					sizeof(struct drm_color_ctm), -1,</div><div class='hunk'>@@ -440,7 +398,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,</div><div class='ctx'> 		state-&gt;color_mgmt_changed |= replaced;</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	} else if (property == config-&gt;gamma_lut_property) {</div><div class='del'>-		ret = drm_atomic_replace_property_blob_from_id(dev,</div><div class='add'>+		ret = drm_property_replace_blob_from_id(dev,</div><div class='ctx'> 					&amp;state-&gt;gamma_lut,</div><div class='ctx'> 					val,</div><div class='ctx'> 					-1, sizeof(struct drm_color_lut),</div><div class='hunk'>@@ -581,7 +539,7 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,</div><div class='ctx'> 	} else if (property == plane-&gt;color_range_property) {</div><div class='ctx'> 		state-&gt;color_range = val;</div><div class='ctx'> 	} else if (property == config-&gt;prop_fb_damage_clips) {</div><div class='del'>-		ret = drm_atomic_replace_property_blob_from_id(dev,</div><div class='add'>+		ret = drm_property_replace_blob_from_id(dev,</div><div class='ctx'> 					&amp;state-&gt;fb_damage_clips,</div><div class='ctx'> 					val,</div><div class='ctx'> 					-1,</div><div class='hunk'>@@ -778,7 +736,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector,</div><div class='ctx'> 		if (state-&gt;link_status != DRM_LINK_STATUS_GOOD)</div><div class='ctx'> 			state-&gt;link_status = val;</div><div class='ctx'> 	} else if (property == config-&gt;hdr_output_metadata_property) {</div><div class='del'>-		ret = drm_atomic_replace_property_blob_from_id(dev,</div><div class='add'>+		ret = drm_property_replace_blob_from_id(dev,</div><div class='ctx'> 				&amp;state-&gt;hdr_output_metadata,</div><div class='ctx'> 				val,</div><div class='ctx'> 				sizeof(struct hdr_output_metadata), -1,</div><div class='head'>diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c<br/>index 252c105d614f..22aa015df387 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_auth.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_auth.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_auth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_auth.c</a></div><div class='hunk'>@@ -234,7 +234,7 @@ static int</div><div class='ctx'> drm_master_check_perm(struct drm_device *dev, struct drm_file *file_priv)</div><div class='ctx'> {</div><div class='ctx'> 	if (file_priv-&gt;was_master &amp;&amp;</div><div class='del'>-	    rcu_access_pointer(file_priv-&gt;pid) == task_pid(current))</div><div class='add'>+	    rcu_access_pointer(file_priv-&gt;pid) == task_tgid(current))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!capable(CAP_SYS_ADMIN))</div><div class='head'>diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c<br/>index df9bf3c9206e..cb90e70d85e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_crtc.c</a></div><div class='hunk'>@@ -715,8 +715,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,</div><div class='ctx'> 	struct drm_mode_set set;</div><div class='ctx'> 	uint32_t __user *set_connectors_ptr;</div><div class='ctx'> 	struct drm_modeset_acquire_ctx ctx;</div><div class='del'>-	int ret;</div><div class='del'>-	int i;</div><div class='add'>+	int ret, i, num_connectors = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!drm_core_check_feature(dev, DRIVER_MODESET))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='hunk'>@@ -871,6 +870,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,</div><div class='ctx'> 					connector-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 			connector_set[i] = connector;</div><div class='add'>+			num_connectors++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -879,7 +879,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,</div><div class='ctx'> 	set.y = crtc_req-&gt;y;</div><div class='ctx'> 	set.mode = mode;</div><div class='ctx'> 	set.connectors = connector_set;</div><div class='del'>-	set.num_connectors = crtc_req-&gt;count_connectors;</div><div class='add'>+	set.num_connectors = num_connectors;</div><div class='ctx'> 	set.fb = fb;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_drv_uses_atomic_modeset(dev))</div><div class='hunk'>@@ -892,7 +892,7 @@ out:</div><div class='ctx'> 		drm_framebuffer_put(fb);</div><div class='ctx'> </div><div class='ctx'> 	if (connector_set) {</div><div class='del'>-		for (i = 0; i &lt; crtc_req-&gt;count_connectors; i++) {</div><div class='add'>+		for (i = 0; i &lt; num_connectors; i++) {</div><div class='ctx'> 			if (connector_set[i])</div><div class='ctx'> 				drm_connector_put(connector_set[i]);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c<br/>index d45f86413402..923c4423151c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_edid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_edid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_edid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_edid.c</a></div><div class='hunk'>@@ -2311,7 +2311,8 @@ int drm_edid_override_connector_update(struct drm_connector *connector)</div><div class='ctx'> </div><div class='ctx'> 	override = drm_edid_override_get(connector);</div><div class='ctx'> 	if (override) {</div><div class='del'>-		num_modes = drm_edid_connector_update(connector, override);</div><div class='add'>+		if (drm_edid_connector_update(connector, override) == 0)</div><div class='add'>+			num_modes = drm_edid_connector_add_modes(connector);</div><div class='ctx'> </div><div class='ctx'> 		drm_edid_free(override);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c<br/>index 20e59d88218d..2da094bdf8a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_exec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_exec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_exec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_exec.c</a></div><div class='hunk'>@@ -69,16 +69,23 @@ static void drm_exec_unlock_all(struct drm_exec *exec)</div><div class='ctx'>  * drm_exec_init - initialize a drm_exec object</div><div class='ctx'>  * @exec: the drm_exec object to initialize</div><div class='ctx'>  * @flags: controls locking behavior, see DRM_EXEC_* defines</div><div class='add'>+ * @nr: the initial # of objects</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the object and make sure that we can track locked objects.</div><div class='add'>+ *</div><div class='add'>+ * If nr is non-zero then it is used as the initial objects table size.</div><div class='add'>+ * In either case, the table will grow (be re-allocated) on demand.</div><div class='ctx'>  */</div><div class='del'>-void drm_exec_init(struct drm_exec *exec, u32 flags)</div><div class='add'>+void drm_exec_init(struct drm_exec *exec, u32 flags, unsigned nr)</div><div class='ctx'> {</div><div class='add'>+	if (!nr)</div><div class='add'>+		nr = PAGE_SIZE / sizeof(void *);</div><div class='add'>+</div><div class='ctx'> 	exec-&gt;flags = flags;</div><div class='del'>-	exec-&gt;objects = kmalloc(PAGE_SIZE, GFP_KERNEL);</div><div class='add'>+	exec-&gt;objects = kvmalloc_array(nr, sizeof(void *), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	/* If allocation here fails, just delay that till the first use */</div><div class='del'>-	exec-&gt;max_objects = exec-&gt;objects ? PAGE_SIZE / sizeof(void *) : 0;</div><div class='add'>+	exec-&gt;max_objects = exec-&gt;objects ? nr : 0;</div><div class='ctx'> 	exec-&gt;num_objects = 0;</div><div class='ctx'> 	exec-&gt;contended = DRM_EXEC_DUMMY;</div><div class='ctx'> 	exec-&gt;prelocked = NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c<br/>index 3cc0ffc28e86..888aadb6a4ac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_framebuffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_framebuffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_framebuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_framebuffer.c</a></div><div class='hunk'>@@ -461,6 +461,7 @@ int drm_mode_rmfb(struct drm_device *dev, u32 fb_id,</div><div class='ctx'> </div><div class='ctx'> 		INIT_WORK_ONSTACK(&amp;arg.work, drm_mode_rmfb_work_fn);</div><div class='ctx'> 		INIT_LIST_HEAD(&amp;arg.fbs);</div><div class='add'>+		drm_WARN_ON(dev, !list_empty(&amp;fb-&gt;filp_head));</div><div class='ctx'> 		list_add_tail(&amp;fb-&gt;filp_head, &amp;arg.fbs);</div><div class='ctx'> </div><div class='ctx'> 		schedule_work(&amp;arg.work);</div><div class='hunk'>@@ -827,6 +828,8 @@ void drm_framebuffer_free(struct kref *kref)</div><div class='ctx'> 			container_of(kref, struct drm_framebuffer, base.refcount);</div><div class='ctx'> 	struct drm_device *dev = fb-&gt;dev;</div><div class='ctx'> </div><div class='add'>+	drm_WARN_ON(dev, !list_empty(&amp;fb-&gt;filp_head));</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The lookup idr holds a weak reference, which has not necessarily been</div><div class='ctx'> 	 * removed at this point. Check for that.</div><div class='hunk'>@@ -1119,7 +1122,7 @@ void drm_framebuffer_remove(struct drm_framebuffer *fb)</div><div class='ctx'> </div><div class='ctx'> 	dev = fb-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	WARN_ON(!list_empty(&amp;fb-&gt;filp_head));</div><div class='add'>+	drm_WARN_ON(dev, !list_empty(&amp;fb-&gt;filp_head));</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * drm ABI mandates that we remove any deleted framebuffers from active</div><div class='head'>diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c<br/>index 9c0922c1a5a2..f9eb56f24bef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_gpuvm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_gpuvm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_gpuvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_gpuvm.c</a></div><div class='hunk'>@@ -1,4 +1,4 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2022 Red Hat.</div><div class='ctx'>  *</div><div class='hunk'>@@ -1250,7 +1250,7 @@ drm_gpuvm_exec_lock(struct drm_gpuvm_exec *vm_exec)</div><div class='ctx'> 	unsigned int num_fences = vm_exec-&gt;num_fences;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(exec, vm_exec-&gt;flags);</div><div class='add'>+	drm_exec_init(exec, vm_exec-&gt;flags, 0);</div><div class='ctx'> </div><div class='ctx'> 	drm_exec_until_all_locked(exec) {</div><div class='ctx'> 		ret = drm_gpuvm_prepare_vm(gpuvm, exec, num_fences);</div><div class='hunk'>@@ -1341,7 +1341,7 @@ drm_gpuvm_exec_lock_range(struct drm_gpuvm_exec *vm_exec,</div><div class='ctx'> 	struct drm_exec *exec = &amp;vm_exec-&gt;exec;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(exec, vm_exec-&gt;flags);</div><div class='add'>+	drm_exec_init(exec, vm_exec-&gt;flags, 0);</div><div class='ctx'> </div><div class='ctx'> 	drm_exec_until_all_locked(exec) {</div><div class='ctx'> 		ret = drm_gpuvm_prepare_range(gpuvm, exec, addr, range,</div><div class='head'>diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c<br/>index 45238ec5df1b..c4f88c3a93b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_modes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_modes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_modes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_modes.c</a></div><div class='hunk'>@@ -2617,8 +2617,7 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	strncpy(out-&gt;name, in-&gt;name, DRM_DISPLAY_MODE_LEN);</div><div class='del'>-	out-&gt;name[DRM_DISPLAY_MODE_LEN-1] = 0;</div><div class='add'>+	strscpy_pad(out-&gt;name, in-&gt;name, sizeof(out-&gt;name));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2659,8 +2658,7 @@ int drm_mode_convert_umode(struct drm_device *dev,</div><div class='ctx'> 	 * useful for the kernel-&gt;userspace direction anyway.</div><div class='ctx'> 	 */</div><div class='ctx'> 	out-&gt;type = in-&gt;type &amp; DRM_MODE_TYPE_ALL;</div><div class='del'>-	strncpy(out-&gt;name, in-&gt;name, DRM_DISPLAY_MODE_LEN);</div><div class='del'>-	out-&gt;name[DRM_DISPLAY_MODE_LEN-1] = 0;</div><div class='add'>+	strscpy_pad(out-&gt;name, in-&gt;name, sizeof(out-&gt;name));</div><div class='ctx'> </div><div class='ctx'> 	/* Clearing picture aspect ratio bits from out flags,</div><div class='ctx'> 	 * as the aspect-ratio information is not stored in</div><div class='head'>diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c<br/>index 9e8e4c60983d..672c655c7a8e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_plane.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_plane.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_plane.c</a></div><div class='hunk'>@@ -1503,6 +1503,7 @@ retry:</div><div class='ctx'> out:</div><div class='ctx'> 	if (fb)</div><div class='ctx'> 		drm_framebuffer_put(fb);</div><div class='add'>+	fb = NULL;</div><div class='ctx'> 	if (plane-&gt;old_fb)</div><div class='ctx'> 		drm_framebuffer_put(plane-&gt;old_fb);</div><div class='ctx'> 	plane-&gt;old_fb = NULL;</div><div class='head'>diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c<br/>index 63b709a67471..834a5e28abbe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_prime.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_prime.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_prime.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_prime.c</a></div><div class='hunk'>@@ -278,7 +278,7 @@ void drm_gem_dmabuf_release(struct dma_buf *dma_buf)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_gem_dmabuf_release);</div><div class='ctx'> </div><div class='del'>-/*</div><div class='add'>+/**</div><div class='ctx'>  * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers</div><div class='ctx'>  * @dev: drm_device to import into</div><div class='ctx'>  * @file_priv: drm file-private structure</div><div class='hunk'>@@ -292,9 +292,9 @@ EXPORT_SYMBOL(drm_gem_dmabuf_release);</div><div class='ctx'>  *</div><div class='ctx'>  * Returns 0 on success or a negative error code on failure.</div><div class='ctx'>  */</div><div class='del'>-static int drm_gem_prime_fd_to_handle(struct drm_device *dev,</div><div class='del'>-				      struct drm_file *file_priv, int prime_fd,</div><div class='del'>-				      uint32_t *handle)</div><div class='add'>+int drm_gem_prime_fd_to_handle(struct drm_device *dev,</div><div class='add'>+			       struct drm_file *file_priv, int prime_fd,</div><div class='add'>+			       uint32_t *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct dma_buf *dma_buf;</div><div class='ctx'> 	struct drm_gem_object *obj;</div><div class='hunk'>@@ -360,6 +360,7 @@ out_put:</div><div class='ctx'> 	dma_buf_put(dma_buf);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);</div><div class='ctx'> </div><div class='ctx'> int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 				 struct drm_file *file_priv)</div><div class='hunk'>@@ -408,7 +409,7 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev,</div><div class='ctx'> 	return dmabuf;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='add'>+/**</div><div class='ctx'>  * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers</div><div class='ctx'>  * @dev: dev to export the buffer from</div><div class='ctx'>  * @file_priv: drm file-private structure</div><div class='hunk'>@@ -421,10 +422,10 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev,</div><div class='ctx'>  * The actual exporting from GEM object to a dma-buf is done through the</div><div class='ctx'>  * &amp;drm_gem_object_funcs.export callback.</div><div class='ctx'>  */</div><div class='del'>-static int drm_gem_prime_handle_to_fd(struct drm_device *dev,</div><div class='del'>-				      struct drm_file *file_priv, uint32_t handle,</div><div class='del'>-				      uint32_t flags,</div><div class='del'>-				      int *prime_fd)</div><div class='add'>+int drm_gem_prime_handle_to_fd(struct drm_device *dev,</div><div class='add'>+			       struct drm_file *file_priv, uint32_t handle,</div><div class='add'>+			       uint32_t flags,</div><div class='add'>+			       int *prime_fd)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_gem_object *obj;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -506,6 +507,7 @@ out_unlock:</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);</div><div class='ctx'> </div><div class='ctx'> int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 				 struct drm_file *file_priv)</div><div class='hunk'>@@ -864,9 +866,9 @@ EXPORT_SYMBOL(drm_prime_get_contiguous_size);</div><div class='ctx'>  * @obj: GEM object to export</div><div class='ctx'>  * @flags: flags like DRM_CLOEXEC and DRM_RDWR</div><div class='ctx'>  *</div><div class='del'>- * This is the implementation of the &amp;drm_gem_object_funcs.export functions</div><div class='del'>- * for GEM drivers using the PRIME helpers. It is used as the default for</div><div class='del'>- * drivers that do not set their own.</div><div class='add'>+ * This is the implementation of the &amp;drm_gem_object_funcs.export functions for GEM drivers</div><div class='add'>+ * using the PRIME helpers. It is used as the default in</div><div class='add'>+ * drm_gem_prime_handle_to_fd().</div><div class='ctx'>  */</div><div class='ctx'> struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,</div><div class='ctx'> 				     int flags)</div><div class='hunk'>@@ -962,9 +964,10 @@ EXPORT_SYMBOL(drm_gem_prime_import_dev);</div><div class='ctx'>  * @dev: drm_device to import into</div><div class='ctx'>  * @dma_buf: dma-buf object to import</div><div class='ctx'>  *</div><div class='del'>- * This is the implementation of the gem_prime_import functions for GEM</div><div class='del'>- * drivers using the PRIME helpers. It is the default for drivers that do</div><div class='del'>- * not set their own &amp;drm_driver.gem_prime_import.</div><div class='add'>+ * This is the implementation of the gem_prime_import functions for GEM drivers</div><div class='add'>+ * using the PRIME helpers. Drivers can use this as their</div><div class='add'>+ * &amp;drm_driver.gem_prime_import implementation. It is used as the default</div><div class='add'>+ * implementation in drm_gem_prime_fd_to_handle().</div><div class='ctx'>  *</div><div class='ctx'>  * Drivers must arrange to call drm_prime_gem_destroy() from their</div><div class='ctx'>  * &amp;drm_gem_object_funcs.free hook when using this function.</div><div class='head'>diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c<br/>index dfec479830e4..596272149a35 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_property.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_property.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_property.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_property.c</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #include &lt;drm/drm_drv.h&gt;</div><div class='ctx'> #include &lt;drm/drm_file.h&gt;</div><div class='ctx'> #include &lt;drm/drm_framebuffer.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='ctx'> #include &lt;drm/drm_property.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "drm_crtc_internal.h"</div><div class='hunk'>@@ -751,6 +752,64 @@ bool drm_property_replace_blob(struct drm_property_blob **blob,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(drm_property_replace_blob);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * drm_property_replace_blob_from_id - replace a blob property taking a reference</div><div class='add'>+ * @dev: DRM device</div><div class='add'>+ * @blob: a pointer to the member blob to be replaced</div><div class='add'>+ * @blob_id: the id of the new blob to replace with</div><div class='add'>+ * @expected_size: expected size of the blob property</div><div class='add'>+ * @expected_elem_size: expected size of an element in the blob property</div><div class='add'>+ * @replaced: if the blob was in fact replaced</div><div class='add'>+ *</div><div class='add'>+ * Look up the new blob from id, take its reference, check expected sizes of</div><div class='add'>+ * the blob and its element and replace the old blob by the new one. Advertise</div><div class='add'>+ * if the replacement operation was successful.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the blob was in fact replaced. -EINVAL if the new blob was</div><div class='add'>+ * not found or sizes don't match.</div><div class='add'>+ */</div><div class='add'>+int drm_property_replace_blob_from_id(struct drm_device *dev,</div><div class='add'>+					 struct drm_property_blob **blob,</div><div class='add'>+					 uint64_t blob_id,</div><div class='add'>+					 ssize_t expected_size,</div><div class='add'>+					 ssize_t expected_elem_size,</div><div class='add'>+					 bool *replaced)</div><div class='add'>+{</div><div class='add'>+	struct drm_property_blob *new_blob = NULL;</div><div class='add'>+</div><div class='add'>+	if (blob_id != 0) {</div><div class='add'>+		new_blob = drm_property_lookup_blob(dev, blob_id);</div><div class='add'>+		if (new_blob == NULL) {</div><div class='add'>+			drm_dbg_atomic(dev,</div><div class='add'>+				       "cannot find blob ID %llu\n", blob_id);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (expected_size &gt; 0 &amp;&amp;</div><div class='add'>+		    new_blob-&gt;length != expected_size) {</div><div class='add'>+			drm_dbg_atomic(dev,</div><div class='add'>+				       "[BLOB:%d] length %zu different from expected %zu\n",</div><div class='add'>+				       new_blob-&gt;base.id, new_blob-&gt;length, expected_size);</div><div class='add'>+			drm_property_blob_put(new_blob);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		if (expected_elem_size &gt; 0 &amp;&amp;</div><div class='add'>+		    new_blob-&gt;length % expected_elem_size != 0) {</div><div class='add'>+			drm_dbg_atomic(dev,</div><div class='add'>+				       "[BLOB:%d] length %zu not divisible by element size %zu\n",</div><div class='add'>+				       new_blob-&gt;base.id, new_blob-&gt;length, expected_elem_size);</div><div class='add'>+			drm_property_blob_put(new_blob);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*replaced |= drm_property_replace_blob(blob, new_blob);</div><div class='add'>+	drm_property_blob_put(new_blob);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(drm_property_replace_blob_from_id);</div><div class='add'>+</div><div class='ctx'> int drm_mode_getblob_ioctl(struct drm_device *dev,</div><div class='ctx'> 			   void *data, struct drm_file *file_priv)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c<br/>index cbb65b7ba425..84101baeecc6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_syncobj.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/drm_syncobj.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/drm_syncobj.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/drm_syncobj.c</a></div><div class='hunk'>@@ -1403,7 +1403,7 @@ static void syncobj_eventfd_entry_fence_func(struct dma_fence *fence,</div><div class='ctx'> 	struct syncobj_eventfd_entry *entry =</div><div class='ctx'> 		container_of(cb, struct syncobj_eventfd_entry, fence_cb);</div><div class='ctx'> </div><div class='del'>-	eventfd_signal(entry-&gt;ev_fd_ctx, 1);</div><div class='add'>+	eventfd_signal(entry-&gt;ev_fd_ctx);</div><div class='ctx'> 	syncobj_eventfd_entry_free(entry);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1426,13 +1426,13 @@ syncobj_eventfd_entry_func(struct drm_syncobj *syncobj,</div><div class='ctx'> 	entry-&gt;fence = fence;</div><div class='ctx'> </div><div class='ctx'> 	if (entry-&gt;flags &amp; DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE) {</div><div class='del'>-		eventfd_signal(entry-&gt;ev_fd_ctx, 1);</div><div class='add'>+		eventfd_signal(entry-&gt;ev_fd_ctx);</div><div class='ctx'> 		syncobj_eventfd_entry_free(entry);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = dma_fence_add_callback(fence, &amp;entry-&gt;fence_cb,</div><div class='ctx'> 					     syncobj_eventfd_entry_fence_func);</div><div class='ctx'> 		if (ret == -ENOENT) {</div><div class='del'>-			eventfd_signal(entry-&gt;ev_fd_ctx, 1);</div><div class='add'>+			eventfd_signal(entry-&gt;ev_fd_ctx);</div><div class='ctx'> 			syncobj_eventfd_entry_free(entry);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c<br/>index 4d986077738b..776f2f0b602d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos5433_drm_decon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos5433_drm_decon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos5433_drm_decon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos5433_drm_decon.c</a></div><div class='hunk'>@@ -862,18 +862,16 @@ err_disable_pm_runtime:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos5433_decon_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos5433_decon_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;decon_component_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct platform_driver exynos5433_decon_driver = {</div><div class='ctx'> 	.probe		= exynos5433_decon_probe,</div><div class='del'>-	.remove		= exynos5433_decon_remove,</div><div class='add'>+	.remove_new	= exynos5433_decon_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos5433-decon",</div><div class='ctx'> 		.pm	= pm_ptr(&amp;exynos5433_decon_pm_ops),</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c<br/>index 0156a5e94435..0d185c0564b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos7_drm_decon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos7_drm_decon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos7_drm_decon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos7_drm_decon.c</a></div><div class='hunk'>@@ -765,7 +765,7 @@ err_iounmap:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int decon_remove(struct platform_device *pdev)</div><div class='add'>+static void decon_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct decon_context *ctx = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -774,8 +774,6 @@ static int decon_remove(struct platform_device *pdev)</div><div class='ctx'> 	iounmap(ctx-&gt;regs);</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;decon_component_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int exynos7_decon_suspend(struct device *dev)</div><div class='hunk'>@@ -840,7 +838,7 @@ static DEFINE_RUNTIME_DEV_PM_OPS(exynos7_decon_pm_ops, exynos7_decon_suspend,</div><div class='ctx'> </div><div class='ctx'> struct platform_driver decon_driver = {</div><div class='ctx'> 	.probe		= decon_probe,</div><div class='del'>-	.remove		= decon_remove,</div><div class='add'>+	.remove_new	= decon_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-decon",</div><div class='ctx'> 		.pm	= pm_ptr(&amp;exynos7_decon_pm_ops),</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c<br/>index 3404ec1367fb..ca31bad6c576 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_dp.c</a></div><div class='hunk'>@@ -250,14 +250,12 @@ out:</div><div class='ctx'> 	return component_add(&amp;pdev-&gt;dev, &amp;exynos_dp_ops);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_dp_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_dp_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos_dp_device *dp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;exynos_dp_ops);</div><div class='ctx'> 	analogix_dp_remove(dp-&gt;adp);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int exynos_dp_suspend(struct device *dev)</div><div class='hunk'>@@ -285,7 +283,7 @@ MODULE_DEVICE_TABLE(of, exynos_dp_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver dp_driver = {</div><div class='ctx'> 	.probe		= exynos_dp_probe,</div><div class='del'>-	.remove		= exynos_dp_remove,</div><div class='add'>+	.remove_new	= exynos_dp_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-dp",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_dma.c b/drivers/gpu/drm/exynos/exynos_drm_dma.c<br/>index a971590b8132..e2c7373f20c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_dma.c</a></div><div class='hunk'>@@ -107,18 +107,16 @@ int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!priv-&gt;mapping) {</div><div class='del'>-		void *mapping;</div><div class='add'>+		void *mapping = NULL;</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))</div><div class='ctx'> 			mapping = arm_iommu_create_mapping(&amp;platform_bus_type,</div><div class='ctx'> 				EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE);</div><div class='ctx'> 		else if (IS_ENABLED(CONFIG_IOMMU_DMA))</div><div class='ctx'> 			mapping = iommu_get_domain_for_dev(priv-&gt;dma_dev);</div><div class='del'>-		else</div><div class='del'>-			mapping = ERR_PTR(-ENODEV);</div><div class='ctx'> </div><div class='del'>-		if (IS_ERR(mapping))</div><div class='del'>-			return PTR_ERR(mapping);</div><div class='add'>+		if (!mapping)</div><div class='add'>+			return -ENODEV;</div><div class='ctx'> 		priv-&gt;mapping = mapping;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_dpi.c b/drivers/gpu/drm/exynos/exynos_drm_dpi.c<br/>index 378e5381978f..0dc36df6ada3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_dpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_dpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_dpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_dpi.c</a></div><div class='hunk'>@@ -101,7 +101,7 @@ static int exynos_dpi_create_connector(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_connector_init(encoder-&gt;dev, connector,</div><div class='ctx'> 				 &amp;exynos_dpi_connector_funcs,</div><div class='del'>-				 DRM_MODE_CONNECTOR_VGA);</div><div class='add'>+				 DRM_MODE_CONNECTOR_DPI);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_DEV_ERROR(ctx-&gt;dev,</div><div class='ctx'> 			      "failed to initialize connector with drm\n");</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c<br/>index 8399256cb5c9..7c59e1164a48 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_drv.c</a></div><div class='hunk'>@@ -300,6 +300,7 @@ err_mode_config_cleanup:</div><div class='ctx'> 	drm_mode_config_cleanup(drm);</div><div class='ctx'> 	exynos_drm_cleanup_dma(drm);</div><div class='ctx'> 	kfree(private);</div><div class='add'>+	dev_set_drvdata(dev, NULL);</div><div class='ctx'> err_free_drm:</div><div class='ctx'> 	drm_dev_put(drm);</div><div class='ctx'> </div><div class='hunk'>@@ -313,6 +314,7 @@ static void exynos_drm_unbind(struct device *dev)</div><div class='ctx'> 	drm_dev_unregister(drm);</div><div class='ctx'> </div><div class='ctx'> 	drm_kms_helper_poll_fini(drm);</div><div class='add'>+	drm_atomic_helper_shutdown(drm);</div><div class='ctx'> </div><div class='ctx'> 	component_unbind_all(drm-&gt;dev, drm);</div><div class='ctx'> 	drm_mode_config_cleanup(drm);</div><div class='hunk'>@@ -344,15 +346,23 @@ static int exynos_drm_platform_probe(struct platform_device *pdev)</div><div class='ctx'> 					       match);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_drm_platform_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_drm_platform_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	component_master_del(&amp;pdev-&gt;dev, &amp;exynos_drm_ops);</div><div class='del'>-	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void exynos_drm_platform_shutdown(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *drm = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	if (drm)</div><div class='add'>+		drm_atomic_helper_shutdown(drm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver exynos_drm_platform_driver = {</div><div class='ctx'> 	.probe	= exynos_drm_platform_probe,</div><div class='del'>-	.remove	= exynos_drm_platform_remove,</div><div class='add'>+	.remove_new	= exynos_drm_platform_remove,</div><div class='add'>+	.shutdown = exynos_drm_platform_shutdown,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name	= "exynos-drm",</div><div class='ctx'> 		.pm	= &amp;exynos_drm_pm_ops,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c<br/>index 8de2714599fc..e81a576de398 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_fimc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_fimc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_fimc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_fimc.c</a></div><div class='hunk'>@@ -1367,7 +1367,7 @@ err_pm_dis:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fimc_remove(struct platform_device *pdev)</div><div class='add'>+static void fimc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct fimc_context *ctx = get_fimc_context(dev);</div><div class='hunk'>@@ -1377,8 +1377,6 @@ static int fimc_remove(struct platform_device *pdev)</div><div class='ctx'> 	pm_runtime_disable(dev);</div><div class='ctx'> </div><div class='ctx'> 	fimc_put_clocks(ctx);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int fimc_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -1410,7 +1408,7 @@ MODULE_DEVICE_TABLE(of, fimc_of_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver fimc_driver = {</div><div class='ctx'> 	.probe		= fimc_probe,</div><div class='del'>-	.remove		= fimc_remove,</div><div class='add'>+	.remove_new	= fimc_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.of_match_table = fimc_of_match,</div><div class='ctx'> 		.name	= "exynos-drm-fimc",</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c<br/>index 8dde7b1e9b35..a9f1c5c05894 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_fimd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_fimd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_fimd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_fimd.c</a></div><div class='hunk'>@@ -1277,13 +1277,11 @@ err_disable_pm_runtime:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fimd_remove(struct platform_device *pdev)</div><div class='add'>+static void fimd_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;fimd_component_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int exynos_fimd_suspend(struct device *dev)</div><div class='hunk'>@@ -1325,7 +1323,7 @@ static DEFINE_RUNTIME_DEV_PM_OPS(exynos_fimd_pm_ops, exynos_fimd_suspend,</div><div class='ctx'> </div><div class='ctx'> struct platform_driver fimd_driver = {</div><div class='ctx'> 	.probe		= fimd_probe,</div><div class='del'>-	.remove		= fimd_remove,</div><div class='add'>+	.remove_new	= fimd_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos4-fb",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c<br/>index 414e585ec7dd..f3138423612e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_g2d.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_g2d.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_g2d.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_g2d.c</a></div><div class='hunk'>@@ -1530,7 +1530,7 @@ err_destroy_slab:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int g2d_remove(struct platform_device *pdev)</div><div class='add'>+static void g2d_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct g2d_data *g2d = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1545,8 +1545,6 @@ static int g2d_remove(struct platform_device *pdev)</div><div class='ctx'> 	g2d_fini_cmdlist(g2d);</div><div class='ctx'> 	destroy_workqueue(g2d-&gt;g2d_workq);</div><div class='ctx'> 	kmem_cache_destroy(g2d-&gt;runqueue_slab);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int g2d_suspend(struct device *dev)</div><div class='hunk'>@@ -1609,7 +1607,7 @@ MODULE_DEVICE_TABLE(of, exynos_g2d_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver g2d_driver = {</div><div class='ctx'> 	.probe		= g2d_probe,</div><div class='del'>-	.remove		= g2d_remove,</div><div class='add'>+	.remove_new	= g2d_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-drm-g2d",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c<br/>index 35771fb4e85d..e9a769590415 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_gsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_gsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_gsc.c</a></div><div class='hunk'>@@ -1309,15 +1309,13 @@ err_pm_dis:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gsc_remove(struct platform_device *pdev)</div><div class='add'>+static void gsc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	component_del(dev, &amp;gsc_component_ops);</div><div class='ctx'> 	pm_runtime_dont_use_autosuspend(dev);</div><div class='ctx'> 	pm_runtime_disable(dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused gsc_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -1422,7 +1420,7 @@ MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver gsc_driver = {</div><div class='ctx'> 	.probe		= gsc_probe,</div><div class='del'>-	.remove		= gsc_remove,</div><div class='add'>+	.remove_new	= gsc_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-drm-gsc",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_mic.c b/drivers/gpu/drm/exynos/exynos_drm_mic.c<br/>index 17bab5b1663f..e2920960180f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_mic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_mic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_mic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_mic.c</a></div><div class='hunk'>@@ -442,7 +442,7 @@ err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_mic_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_mic_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos_mic *mic = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -450,8 +450,6 @@ static int exynos_mic_remove(struct platform_device *pdev)</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	drm_bridge_remove(&amp;mic-&gt;bridge);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id exynos_mic_of_match[] = {</div><div class='hunk'>@@ -462,7 +460,7 @@ MODULE_DEVICE_TABLE(of, exynos_mic_of_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver mic_driver = {</div><div class='ctx'> 	.probe		= exynos_mic_probe,</div><div class='del'>-	.remove		= exynos_mic_remove,</div><div class='add'>+	.remove_new	= exynos_mic_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-mic",</div><div class='ctx'> 		.pm	= pm_ptr(&amp;exynos_mic_pm_ops),</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c<br/>index ffb327c5139e..5f7516655b08 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_rotator.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_rotator.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_rotator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_rotator.c</a></div><div class='hunk'>@@ -329,15 +329,13 @@ err_component:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rotator_remove(struct platform_device *pdev)</div><div class='add'>+static void rotator_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	component_del(dev, &amp;rotator_component_ops);</div><div class='ctx'> 	pm_runtime_dont_use_autosuspend(dev);</div><div class='ctx'> 	pm_runtime_disable(dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rotator_runtime_suspend(struct device *dev)</div><div class='hunk'>@@ -453,7 +451,7 @@ static DEFINE_RUNTIME_DEV_PM_OPS(rotator_pm_ops, rotator_runtime_suspend,</div><div class='ctx'> </div><div class='ctx'> struct platform_driver rotator_driver = {</div><div class='ctx'> 	.probe		= rotator_probe,</div><div class='del'>-	.remove		= rotator_remove,</div><div class='add'>+	.remove_new	= rotator_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-rotator",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c b/drivers/gpu/drm/exynos/exynos_drm_scaler.c<br/>index f2b8b09a6b4e..392f721f13ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_scaler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_scaler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_scaler.c</a></div><div class='hunk'>@@ -539,15 +539,13 @@ err_ippdrv_register:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int scaler_remove(struct platform_device *pdev)</div><div class='add'>+static void scaler_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	component_del(dev, &amp;scaler_component_ops);</div><div class='ctx'> 	pm_runtime_dont_use_autosuspend(dev);</div><div class='ctx'> 	pm_runtime_disable(dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int clk_disable_unprepare_wrapper(struct clk *clk)</div><div class='hunk'>@@ -721,7 +719,7 @@ MODULE_DEVICE_TABLE(of, exynos_scaler_match);</div><div class='ctx'> </div><div class='ctx'> struct platform_driver scaler_driver = {</div><div class='ctx'> 	.probe		= scaler_probe,</div><div class='del'>-	.remove		= scaler_remove,</div><div class='add'>+	.remove_new	= scaler_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-scaler",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c<br/>index f5e1adfcaa51..00382f28748a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_vidi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_drm_vidi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_drm_vidi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_drm_vidi.c</a></div><div class='hunk'>@@ -462,7 +462,7 @@ static int vidi_probe(struct platform_device *pdev)</div><div class='ctx'> 	return component_add(dev, &amp;vidi_component_ops);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vidi_remove(struct platform_device *pdev)</div><div class='add'>+static void vidi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct vidi_context *ctx = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -472,13 +472,11 @@ static int vidi_remove(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;vidi_component_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct platform_driver vidi_driver = {</div><div class='ctx'> 	.probe		= vidi_probe,</div><div class='del'>-	.remove		= vidi_remove,</div><div class='add'>+	.remove_new	= vidi_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-drm-vidi",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c<br/>index f3aaa4ea3e68..43bed6cbaaea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_hdmi.c</a></div><div class='hunk'>@@ -1861,6 +1861,8 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI);</div><div class='add'>+	if (IS_ERR(crtc))</div><div class='add'>+		return PTR_ERR(crtc);</div><div class='ctx'> 	crtc-&gt;pipe_clk = &amp;hdata-&gt;phy_clk;</div><div class='ctx'> </div><div class='ctx'> 	ret = hdmi_create_connector(encoder);</div><div class='hunk'>@@ -2067,7 +2069,7 @@ err_ddc:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hdmi_remove(struct platform_device *pdev)</div><div class='add'>+static void hdmi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct hdmi_context *hdata = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -2090,8 +2092,6 @@ static int hdmi_remove(struct platform_device *pdev)</div><div class='ctx'> 	put_device(&amp;hdata-&gt;ddc_adpt-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	mutex_destroy(&amp;hdata-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused exynos_hdmi_suspend(struct device *dev)</div><div class='hunk'>@@ -2123,7 +2123,7 @@ static const struct dev_pm_ops exynos_hdmi_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> struct platform_driver hdmi_driver = {</div><div class='ctx'> 	.probe		= hdmi_probe,</div><div class='del'>-	.remove		= hdmi_remove,</div><div class='add'>+	.remove_new	= hdmi_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "exynos-hdmi",</div><div class='ctx'> 		.owner	= THIS_MODULE,</div><div class='head'>diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c<br/>index b302392ff0d7..6822333fd0e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_mixer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/exynos/exynos_mixer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/exynos/exynos_mixer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/exynos/exynos_mixer.c</a></div><div class='hunk'>@@ -1258,13 +1258,11 @@ static int mixer_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mixer_remove(struct platform_device *pdev)</div><div class='add'>+static void mixer_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;mixer_component_ops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused exynos_mixer_suspend(struct device *dev)</div><div class='hunk'>@@ -1338,5 +1336,5 @@ struct platform_driver mixer_driver = {</div><div class='ctx'> 		.of_match_table = mixer_match_types,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = mixer_probe,</div><div class='del'>-	.remove = mixer_remove,</div><div class='add'>+	.remove_new = mixer_remove,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c<br/>index 8992a95076f2..dd1eb7e9877d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/cdv_intel_dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/gma500/cdv_intel_dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/cdv_intel_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/cdv_intel_dp.c</a></div><div class='hunk'>@@ -855,7 +855,6 @@ cdv_intel_dp_i2c_init(struct gma_connector *connector,</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;intel_dp-&gt;adapter, '\0', sizeof (intel_dp-&gt;adapter));</div><div class='ctx'> 	intel_dp-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	intel_dp-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	strncpy (intel_dp-&gt;adapter.name, name, sizeof(intel_dp-&gt;adapter.name) - 1);</div><div class='ctx'> 	intel_dp-&gt;adapter.name[sizeof(intel_dp-&gt;adapter.name) - 1] = '\0';</div><div class='ctx'> 	intel_dp-&gt;adapter.algo_data = &amp;intel_dp-&gt;algo;</div><div class='head'>diff --git a/drivers/gpu/drm/gma500/intel_gmbus.c b/drivers/gpu/drm/gma500/intel_gmbus.c<br/>index 09cedabf4776..aa45509859f2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/intel_gmbus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/gma500/intel_gmbus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/intel_gmbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/intel_gmbus.c</a></div><div class='hunk'>@@ -411,7 +411,6 @@ int gma_intel_setup_gmbus(struct drm_device *dev)</div><div class='ctx'> 		struct intel_gmbus *bus = &amp;dev_priv-&gt;gmbus[i];</div><div class='ctx'> </div><div class='ctx'> 		bus-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-		bus-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 		snprintf(bus-&gt;adapter.name,</div><div class='ctx'> 			 sizeof(bus-&gt;adapter.name),</div><div class='ctx'> 			 "gma500 gmbus %s",</div><div class='head'>diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c b/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c<br/>index fc9a34ed58bd..6daa6669ed23 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c</a></div><div class='hunk'>@@ -168,7 +168,6 @@ static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {</div><div class='ctx'> 	.name		= "oaktrail_hdmi_i2c",</div><div class='ctx'> 	.nr		= 3,</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_DDC,</div><div class='ctx'> 	.algo		= &amp;oaktrail_hdmi_i2c_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c<br/>index d6fd5d726216..e4f914deceba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/psb_intel_sdvo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/gma500/psb_intel_sdvo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/gma500/psb_intel_sdvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/gma500/psb_intel_sdvo.c</a></div><div class='hunk'>@@ -2426,7 +2426,6 @@ psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,</div><div class='ctx'> 			  struct drm_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	sdvo-&gt;ddc.owner = THIS_MODULE;</div><div class='del'>-	sdvo-&gt;ddc.class = I2C_CLASS_DDC;</div><div class='ctx'> 	snprintf(sdvo-&gt;ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");</div><div class='ctx'> 	sdvo-&gt;ddc.dev.parent = dev-&gt;dev;</div><div class='ctx'> 	sdvo-&gt;ddc.algo_data = sdvo;</div><div class='head'>diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c<br/>index 410bd019bb35..e6e48651c15c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c</a></div><div class='hunk'>@@ -81,7 +81,6 @@ int hibmc_ddc_create(struct drm_device *drm_dev,</div><div class='ctx'> 		     struct hibmc_connector *connector)</div><div class='ctx'> {</div><div class='ctx'> 	connector-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	connector-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	snprintf(connector-&gt;adapter.name, I2C_NAME_SIZE, "HIS i2c bit bus");</div><div class='ctx'> 	connector-&gt;adapter.dev.parent = drm_dev-&gt;dev;</div><div class='ctx'> 	i2c_set_adapdata(&amp;connector-&gt;adapter, connector);</div><div class='head'>diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c<br/>index d511d17c5bdf..cff85086f2d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/hyperv/hyperv_drm_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/hyperv/hyperv_drm_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/hyperv/hyperv_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/hyperv/hyperv_drm_drv.c</a></div><div class='hunk'>@@ -7,7 +7,6 @@</div><div class='ctx'> #include &lt;linux/hyperv.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='del'>-#include &lt;linux/screen_info.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_aperture.h&gt;</div><div class='ctx'> #include &lt;drm/drm_atomic_helper.h&gt;</div><div class='hunk'>@@ -73,11 +72,6 @@ static int hyperv_setup_vram(struct hyperv_drm_device *hv,</div><div class='ctx'> 	struct drm_device *dev = &amp;hv-&gt;dev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (IS_ENABLED(CONFIG_SYSFB))</div><div class='del'>-		drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,</div><div class='del'>-							     screen_info.lfb_size,</div><div class='del'>-							     &amp;hyperv_driver);</div><div class='del'>-</div><div class='ctx'> 	hv-&gt;fb_size = (unsigned long)hv-&gt;mmio_megabytes * 1024 * 1024;</div><div class='ctx'> </div><div class='ctx'> 	ret = vmbus_allocate_mmio(&amp;hv-&gt;mem, hdev, 0, -1, hv-&gt;fb_size, 0x100000,</div><div class='hunk'>@@ -130,6 +124,8 @@ static int hyperv_vmbus_probe(struct hv_device *hdev,</div><div class='ctx'> 		goto err_hv_set_drv_data;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	drm_aperture_remove_framebuffers(&amp;hyperv_driver);</div><div class='add'>+</div><div class='ctx'> 	ret = hyperv_setup_vram(hv, hdev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_vmbus_close;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug<br/>index 2d21930d5501..5b7162076850 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/Kconfig.debug?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/Kconfig.debug</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/Kconfig.debug?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/Kconfig.debug</a></div><div class='hunk'>@@ -24,7 +24,9 @@ config DRM_I915_DEBUG</div><div class='ctx'> 	select DEBUG_FS</div><div class='ctx'> 	select PREEMPT_COUNT</div><div class='ctx'> 	select I2C_CHARDEV</div><div class='add'>+	select REF_TRACKER</div><div class='ctx'> 	select STACKDEPOT</div><div class='add'>+	select STACKTRACE</div><div class='ctx'> 	select DRM_DP_AUX_CHARDEV</div><div class='ctx'> 	select X86_MSR # used by igt/pm_rpm</div><div class='ctx'> 	select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)</div><div class='hunk'>@@ -38,6 +40,7 @@ config DRM_I915_DEBUG</div><div class='ctx'> 	select DRM_I915_DEBUG_GEM_ONCE</div><div class='ctx'> 	select DRM_I915_DEBUG_MMIO</div><div class='ctx'> 	select DRM_I915_DEBUG_RUNTIME_PM</div><div class='add'>+	select DRM_I915_DEBUG_WAKEREF</div><div class='ctx'> 	select DRM_I915_SW_FENCE_DEBUG_OBJECTS</div><div class='ctx'> 	select DRM_I915_SELFTEST</div><div class='ctx'> 	default n</div><div class='hunk'>@@ -231,7 +234,9 @@ config DRM_I915_DEBUG_RUNTIME_PM</div><div class='ctx'> 	bool "Enable extra state checking for runtime PM"</div><div class='ctx'> 	depends on DRM_I915</div><div class='ctx'> 	default n</div><div class='add'>+	select REF_TRACKER</div><div class='ctx'> 	select STACKDEPOT</div><div class='add'>+	select STACKTRACE</div><div class='ctx'> 	help</div><div class='ctx'> 	  Choose this option to turn on extra state checking for the</div><div class='ctx'> 	  runtime PM functionality. This may introduce overhead during</div><div class='hunk'>@@ -240,3 +245,16 @@ config DRM_I915_DEBUG_RUNTIME_PM</div><div class='ctx'> 	  Recommended for driver developers only.</div><div class='ctx'> </div><div class='ctx'> 	  If in doubt, say "N"</div><div class='add'>+</div><div class='add'>+config DRM_I915_DEBUG_WAKEREF</div><div class='add'>+	bool "Enable extra tracking for wakerefs"</div><div class='add'>+	depends on DRM_I915</div><div class='add'>+	select REF_TRACKER</div><div class='add'>+	select STACKDEPOT</div><div class='add'>+	select STACKTRACE</div><div class='add'>+	help</div><div class='add'>+	  Choose this option to turn on extra state checking and usage</div><div class='add'>+	  tracking for the wakerefPM functionality. This may introduce</div><div class='add'>+	  overhead during driver runtime.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N"</div><div class='head'>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile<br/>index 65e984242089..e777686190ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/Makefile</a></div><div class='hunk'>@@ -280,6 +280,7 @@ i915-y += \</div><div class='ctx'> 	display/intel_dsb.o \</div><div class='ctx'> 	display/intel_dsb_buffer.o \</div><div class='ctx'> 	display/intel_fb.o \</div><div class='add'>+	display/intel_fb_bo.o \</div><div class='ctx'> 	display/intel_fb_pin.o \</div><div class='ctx'> 	display/intel_fbc.o \</div><div class='ctx'> 	display/intel_fdi.o \</div><div class='hunk'>@@ -318,7 +319,8 @@ i915-$(CONFIG_ACPI) += \</div><div class='ctx'> 	display/intel_acpi.o \</div><div class='ctx'> 	display/intel_opregion.o</div><div class='ctx'> i915-$(CONFIG_DRM_FBDEV_EMULATION) += \</div><div class='del'>-	display/intel_fbdev.o</div><div class='add'>+	display/intel_fbdev.o \</div><div class='add'>+	display/intel_fbdev_fb.o</div><div class='ctx'> i915-$(CONFIG_DEBUG_FS) += \</div><div class='ctx'> 	display/intel_display_debugfs.o \</div><div class='ctx'> 	display/intel_display_debugfs_params.o \</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c<br/>index b37c0d02d500..11ca9572e8b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/i9xx_wm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/i9xx_wm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/i9xx_wm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/i9xx_wm.c</a></div><div class='hunk'>@@ -608,7 +608,7 @@ static bool intel_crtc_active(struct intel_crtc *crtc)</div><div class='ctx'> 	 * crtc-&gt;state-&gt;active once we have proper CRTC states wired up</div><div class='ctx'> 	 * for atomic.</div><div class='ctx'> 	 */</div><div class='del'>-	return crtc &amp;&amp; crtc-&gt;active &amp;&amp; crtc-&gt;base.primary-&gt;state-&gt;fb &amp;&amp;</div><div class='add'>+	return crtc-&gt;active &amp;&amp; crtc-&gt;base.primary-&gt;state-&gt;fb &amp;&amp;</div><div class='ctx'> 		crtc-&gt;config-&gt;hw.adjusted_mode.crtc_clock;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2477,7 +2477,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,</div><div class='ctx'> 		 * FIFO size is only half of the self</div><div class='ctx'> 		 * refresh FIFO size on ILK/SNB.</div><div class='ctx'> 		 */</div><div class='del'>-		if (DISPLAY_VER(dev_priv) &lt;= 6)</div><div class='add'>+		if (DISPLAY_VER(dev_priv) &lt; 7)</div><div class='ctx'> 			fifo_size /= 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2818,7 +2818,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,</div><div class='ctx'> 	usable_level = dev_priv-&gt;display.wm.num_levels - 1;</div><div class='ctx'> </div><div class='ctx'> 	/* ILK/SNB: LP2+ watermarks only w/o sprites */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt;= 6 &amp;&amp; pipe_wm-&gt;sprites_enabled)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 7 &amp;&amp; pipe_wm-&gt;sprites_enabled)</div><div class='ctx'> 		usable_level = 1;</div><div class='ctx'> </div><div class='ctx'> 	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */</div><div class='hunk'>@@ -2961,7 +2961,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,</div><div class='ctx'> 	int last_enabled_level = num_levels - 1;</div><div class='ctx'> </div><div class='ctx'> 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */</div><div class='del'>-	if ((DISPLAY_VER(dev_priv) &lt;= 6 || IS_IVYBRIDGE(dev_priv)) &amp;&amp;</div><div class='add'>+	if ((DISPLAY_VER(dev_priv) &lt; 7 || IS_IVYBRIDGE(dev_priv)) &amp;&amp;</div><div class='ctx'> 	    config-&gt;num_pipes_active &gt; 1)</div><div class='ctx'> 		last_enabled_level = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -3060,7 +3060,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,</div><div class='ctx'> 		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the</div><div class='ctx'> 		 * level is disabled. Doing otherwise could cause underruns.</div><div class='ctx'> 		 */</div><div class='del'>-		if (DISPLAY_VER(dev_priv) &lt;= 6 &amp;&amp; r-&gt;spr_val) {</div><div class='add'>+		if (DISPLAY_VER(dev_priv) &lt; 7 &amp;&amp; r-&gt;spr_val) {</div><div class='ctx'> 			drm_WARN_ON(&amp;dev_priv-&gt;drm, wm_lp != 1);</div><div class='ctx'> 			results-&gt;wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c<br/>index 481fcb650850..ac456a2275db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/icl_dsi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/icl_dsi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/icl_dsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/icl_dsi.c</a></div><div class='hunk'>@@ -1440,6 +1440,13 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state,</div><div class='ctx'> static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,</div><div class='ctx'> 						 struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='add'>+	enum drm_mode_status status;</div><div class='add'>+</div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	/* FIXME: DSC? */</div><div class='ctx'> 	return intel_dsi_mode_valid(connector, mode);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c<br/>index 612d4cd9dacb..3f3cd944a1c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_backlight.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_backlight.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_backlight.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_backlight.c</a></div><div class='hunk'>@@ -275,7 +275,7 @@ static void ext_pwm_set_backlight(const struct drm_connector_state *conn_state,</div><div class='ctx'> 	struct intel_panel *panel = &amp;to_intel_connector(conn_state-&gt;connector)-&gt;panel;</div><div class='ctx'> </div><div class='ctx'> 	pwm_set_relative_duty_cycle(&amp;panel-&gt;backlight.pwm_state, level, 100);</div><div class='del'>-	pwm_apply_state(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='add'>+	pwm_apply_might_sleep(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -428,7 +428,7 @@ static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn</div><div class='ctx'> 	intel_backlight_set_pwm_level(old_conn_state, level);</div><div class='ctx'> </div><div class='ctx'> 	panel-&gt;backlight.pwm_state.enabled = false;</div><div class='del'>-	pwm_apply_state(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='add'>+	pwm_apply_might_sleep(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void intel_backlight_disable(const struct drm_connector_state *old_conn_state)</div><div class='hunk'>@@ -750,7 +750,7 @@ static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,</div><div class='ctx'> </div><div class='ctx'> 	pwm_set_relative_duty_cycle(&amp;panel-&gt;backlight.pwm_state, level, 100);</div><div class='ctx'> 	panel-&gt;backlight.pwm_state.enabled = true;</div><div class='del'>-	pwm_apply_state(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='add'>+	pwm_apply_might_sleep(panel-&gt;backlight.pwm, &amp;panel-&gt;backlight.pwm_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __intel_backlight_enable(const struct intel_crtc_state *crtc_state,</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c<br/>index 2fd72b2fd109..aa169b0055e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_bios.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_bios.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_bios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_bios.c</a></div><div class='hunk'>@@ -2201,6 +2201,9 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)</div><div class='ctx'> 	const u8 *ddc_pin_map;</div><div class='ctx'> 	int i, n_entries;</div><div class='ctx'> </div><div class='add'>+	if (IS_DGFX(i915))</div><div class='add'>+		return vbt_pin;</div><div class='add'>+</div><div class='ctx'> 	if (INTEL_PCH_TYPE(i915) &gt;= PCH_LNL || HAS_PCH_MTP(i915) ||</div><div class='ctx'> 	    IS_ALDERLAKE_P(i915)) {</div><div class='ctx'> 		ddc_pin_map = adlp_ddc_pin_map;</div><div class='hunk'>@@ -2208,8 +2211,6 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)</div><div class='ctx'> 	} else if (IS_ALDERLAKE_S(i915)) {</div><div class='ctx'> 		ddc_pin_map = adls_ddc_pin_map;</div><div class='ctx'> 		n_entries = ARRAY_SIZE(adls_ddc_pin_map);</div><div class='del'>-	} else if (INTEL_PCH_TYPE(i915) &gt;= PCH_DG1) {</div><div class='del'>-		return vbt_pin;</div><div class='ctx'> 	} else if (IS_ROCKETLAKE(i915) &amp;&amp; INTEL_PCH_TYPE(i915) == PCH_TGP) {</div><div class='ctx'> 		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;</div><div class='ctx'> 		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);</div><div class='hunk'>@@ -3474,8 +3475,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,</div><div class='ctx'> 			if (!devdata-&gt;dsc)</div><div class='ctx'> 				return false;</div><div class='ctx'> </div><div class='del'>-			if (crtc_state)</div><div class='del'>-				fill_dsc(crtc_state, devdata-&gt;dsc, dsc_max_bpc);</div><div class='add'>+			fill_dsc(crtc_state, devdata-&gt;dsc, dsc_max_bpc);</div><div class='ctx'> </div><div class='ctx'> 			return true;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c<br/>index bef96db62c80..7f2a50b4f494 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_bw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_bw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_bw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_bw.c</a></div><div class='hunk'>@@ -87,7 +87,8 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	dclk = val &amp; 0xffff;</div><div class='del'>-	sp-&gt;dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) &gt; 11 ? 500 : 0), 1000);</div><div class='add'>+	sp-&gt;dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) &gt;= 12 ? 500 : 0),</div><div class='add'>+				1000);</div><div class='ctx'> 	sp-&gt;t_rp = (val &amp; 0xff0000) &gt;&gt; 16;</div><div class='ctx'> 	sp-&gt;t_rcd = (val &amp; 0xff000000) &gt;&gt; 24;</div><div class='ctx'> </div><div class='hunk'>@@ -480,7 +481,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel</div><div class='ctx'> 	if (num_channels &lt; qi.max_numchannels &amp;&amp; DISPLAY_VER(dev_priv) &gt;= 12)</div><div class='ctx'> 		qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt; 11 &amp;&amp; num_channels &gt; qi.max_numchannels)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &gt;= 12 &amp;&amp; num_channels &gt; qi.max_numchannels)</div><div class='ctx'> 		drm_warn(&amp;dev_priv-&gt;drm, "Number of channels exceeds max number of channels.");</div><div class='ctx'> 	if (qi.max_numchannels != 0)</div><div class='ctx'> 		num_channels = min_t(u8, num_channels, qi.max_numchannels);</div><div class='hunk'>@@ -897,7 +898,7 @@ static int icl_find_qgv_points(struct drm_i915_private *i915,</div><div class='ctx'> 		unsigned int idx;</div><div class='ctx'> 		unsigned int max_data_rate;</div><div class='ctx'> </div><div class='del'>-		if (DISPLAY_VER(i915) &gt; 11)</div><div class='add'>+		if (DISPLAY_VER(i915) &gt;= 12)</div><div class='ctx'> 			idx = tgl_max_bw_index(i915, num_active_planes, i);</div><div class='ctx'> 		else</div><div class='ctx'> 			idx = icl_max_bw_index(i915, num_active_planes, i);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c<br/>index b93d1ad7936d..c985ebb6831a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cdclk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_cdclk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cdclk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cdclk.c</a></div><div class='hunk'>@@ -1180,7 +1180,7 @@ sanitize:</div><div class='ctx'> 	/* force cdclk programming */</div><div class='ctx'> 	dev_priv-&gt;display.cdclk.hw.cdclk = 0;</div><div class='ctx'> 	/* force full PLL disable + enable */</div><div class='del'>-	dev_priv-&gt;display.cdclk.hw.vco = -1;</div><div class='add'>+	dev_priv-&gt;display.cdclk.hw.vco = ~0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)</div><div class='hunk'>@@ -1446,50 +1446,77 @@ static u8 bxt_calc_voltage_level(int cdclk)</div><div class='ctx'> 	return DIV_ROUND_UP(cdclk, 25000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u8 calc_voltage_level(int cdclk, int num_voltage_levels,</div><div class='add'>+			     const int voltage_level_max_cdclk[])</div><div class='add'>+{</div><div class='add'>+	int voltage_level;</div><div class='add'>+</div><div class='add'>+	for (voltage_level = 0; voltage_level &lt; num_voltage_levels; voltage_level++) {</div><div class='add'>+		if (cdclk &lt;= voltage_level_max_cdclk[voltage_level])</div><div class='add'>+			return voltage_level;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	MISSING_CASE(cdclk);</div><div class='add'>+	return num_voltage_levels - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u8 icl_calc_voltage_level(int cdclk)</div><div class='ctx'> {</div><div class='del'>-	if (cdclk &gt; 556800)</div><div class='del'>-		return 2;</div><div class='del'>-	else if (cdclk &gt; 312000)</div><div class='del'>-		return 1;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	static const int icl_voltage_level_max_cdclk[] = {</div><div class='add'>+		[0] = 312000,</div><div class='add'>+		[1] = 556800,</div><div class='add'>+		[2] = 652800,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return calc_voltage_level(cdclk,</div><div class='add'>+				  ARRAY_SIZE(icl_voltage_level_max_cdclk),</div><div class='add'>+				  icl_voltage_level_max_cdclk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u8 ehl_calc_voltage_level(int cdclk)</div><div class='ctx'> {</div><div class='del'>-	if (cdclk &gt; 326400)</div><div class='del'>-		return 3;</div><div class='del'>-	else if (cdclk &gt; 312000)</div><div class='del'>-		return 2;</div><div class='del'>-	else if (cdclk &gt; 180000)</div><div class='del'>-		return 1;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	static const int ehl_voltage_level_max_cdclk[] = {</div><div class='add'>+		[0] = 180000,</div><div class='add'>+		[1] = 312000,</div><div class='add'>+		[2] = 326400,</div><div class='add'>+		/*</div><div class='add'>+		 * Bspec lists the limit as 556.8 MHz, but some JSL</div><div class='add'>+		 * development boards (at least) boot with 652.8 MHz</div><div class='add'>+		 */</div><div class='add'>+		[3] = 652800,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return calc_voltage_level(cdclk,</div><div class='add'>+				  ARRAY_SIZE(ehl_voltage_level_max_cdclk),</div><div class='add'>+				  ehl_voltage_level_max_cdclk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u8 tgl_calc_voltage_level(int cdclk)</div><div class='ctx'> {</div><div class='del'>-	if (cdclk &gt; 556800)</div><div class='del'>-		return 3;</div><div class='del'>-	else if (cdclk &gt; 326400)</div><div class='del'>-		return 2;</div><div class='del'>-	else if (cdclk &gt; 312000)</div><div class='del'>-		return 1;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	static const int tgl_voltage_level_max_cdclk[] = {</div><div class='add'>+		[0] = 312000,</div><div class='add'>+		[1] = 326400,</div><div class='add'>+		[2] = 556800,</div><div class='add'>+		[3] = 652800,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return calc_voltage_level(cdclk,</div><div class='add'>+				  ARRAY_SIZE(tgl_voltage_level_max_cdclk),</div><div class='add'>+				  tgl_voltage_level_max_cdclk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u8 rplu_calc_voltage_level(int cdclk)</div><div class='ctx'> {</div><div class='del'>-	if (cdclk &gt; 556800)</div><div class='del'>-		return 3;</div><div class='del'>-	else if (cdclk &gt; 480000)</div><div class='del'>-		return 2;</div><div class='del'>-	else if (cdclk &gt; 312000)</div><div class='del'>-		return 1;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	static const int rplu_voltage_level_max_cdclk[] = {</div><div class='add'>+		[0] = 312000,</div><div class='add'>+		[1] = 480000,</div><div class='add'>+		[2] = 556800,</div><div class='add'>+		[3] = 652800,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return calc_voltage_level(cdclk,</div><div class='add'>+				  ARRAY_SIZE(rplu_voltage_level_max_cdclk),</div><div class='add'>+				  rplu_voltage_level_max_cdclk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void icl_readout_refclk(struct drm_i915_private *dev_priv,</div><div class='hunk'>@@ -1800,6 +1827,8 @@ static bool cdclk_pll_is_unknown(unsigned int vco)</div><div class='ctx'> 	return vco == ~0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const int cdclk_squash_len = 16;</div><div class='add'>+</div><div class='ctx'> static int cdclk_squash_divider(u16 waveform)</div><div class='ctx'> {</div><div class='ctx'> 	return hweight16(waveform ?: 0xffff);</div><div class='hunk'>@@ -1811,7 +1840,6 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91</div><div class='ctx'> 						    struct intel_cdclk_config *mid_cdclk_config)</div><div class='ctx'> {</div><div class='ctx'> 	u16 old_waveform, new_waveform, mid_waveform;</div><div class='del'>-	int size = 16;</div><div class='ctx'> 	int div = 2;</div><div class='ctx'> </div><div class='ctx'> 	/* Return if PLL is in an unknown state, force a complete disable and re-enable. */</div><div class='hunk'>@@ -1850,7 +1878,8 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mid_cdclk_config-&gt;cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *</div><div class='del'>-						    mid_cdclk_config-&gt;vco, size * div);</div><div class='add'>+						    mid_cdclk_config-&gt;vco,</div><div class='add'>+						    cdclk_squash_len * div);</div><div class='ctx'> </div><div class='ctx'> 	/* make sure the mid clock came out sane */</div><div class='ctx'> </div><div class='hunk'>@@ -1878,9 +1907,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,</div><div class='ctx'> {</div><div class='ctx'> 	int cdclk = cdclk_config-&gt;cdclk;</div><div class='ctx'> 	int vco = cdclk_config-&gt;vco;</div><div class='del'>-	u32 val;</div><div class='add'>+	int unsquashed_cdclk;</div><div class='ctx'> 	u16 waveform;</div><div class='del'>-	int clock;</div><div class='add'>+	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	if (HAS_CDCLK_CRAWL(dev_priv) &amp;&amp; dev_priv-&gt;display.cdclk.hw.vco &gt; 0 &amp;&amp; vco &gt; 0 &amp;&amp;</div><div class='ctx'> 	    !cdclk_pll_is_unknown(dev_priv-&gt;display.cdclk.hw.vco)) {</div><div class='hunk'>@@ -1897,15 +1926,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,</div><div class='ctx'> </div><div class='ctx'> 	waveform = cdclk_squash_waveform(dev_priv, cdclk);</div><div class='ctx'> </div><div class='del'>-	if (waveform)</div><div class='del'>-		clock = vco / 2;</div><div class='del'>-	else</div><div class='del'>-		clock = cdclk;</div><div class='add'>+	unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,</div><div class='add'>+					     cdclk_squash_divider(waveform));</div><div class='ctx'> </div><div class='ctx'> 	if (HAS_CDCLK_SQUASH(dev_priv))</div><div class='ctx'> 		dg2_cdclk_squash_program(dev_priv, waveform);</div><div class='ctx'> </div><div class='del'>-	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |</div><div class='add'>+	val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) |</div><div class='ctx'> 		bxt_cdclk_cd2x_pipe(dev_priv, pipe);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2075,7 +2102,7 @@ sanitize:</div><div class='ctx'> 	dev_priv-&gt;display.cdclk.hw.cdclk = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* force full PLL disable + enable */</div><div class='del'>-	dev_priv-&gt;display.cdclk.hw.vco = -1;</div><div class='add'>+	dev_priv-&gt;display.cdclk.hw.vco = ~0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)</div><div class='hunk'>@@ -2597,7 +2624,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> 		 * Since PPC = 2 with bigjoiner</div><div class='ctx'> 		 * =&gt; CDCLK &gt;= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits</div><div class='ctx'> 		 */</div><div class='del'>-		int bigjoiner_interface_bits = DISPLAY_VER(i915) &gt; 13 ? 36 : 24;</div><div class='add'>+		int bigjoiner_interface_bits = DISPLAY_VER(i915) &gt;= 14 ? 36 : 24;</div><div class='ctx'> 		int min_cdclk_bj =</div><div class='ctx'> 			(to_bpp_int_roundup(crtc_state-&gt;dsc.compressed_bpp_x16) *</div><div class='ctx'> 			 pixel_clock) / (2 * bigjoiner_interface_bits);</div><div class='hunk'>@@ -3489,7 +3516,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = {</div><div class='ctx'> 	.get_cdclk = bxt_get_cdclk,</div><div class='ctx'> 	.set_cdclk = bxt_set_cdclk,</div><div class='ctx'> 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,</div><div class='del'>-	.calc_voltage_level = tgl_calc_voltage_level,</div><div class='add'>+	.calc_voltage_level = rplu_calc_voltage_level,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_cdclk_funcs rplu_cdclk_funcs = {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c<br/>index 0e33a0523a75..abaacea5c2cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_crt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crt.c</a></div><div class='hunk'>@@ -348,8 +348,13 @@ intel_crt_mode_valid(struct drm_connector *connector,</div><div class='ctx'> 	struct drm_device *dev = connector-&gt;dev;</div><div class='ctx'> 	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='ctx'> 	int max_dotclk = dev_priv-&gt;max_dotclk_freq;</div><div class='add'>+	enum drm_mode_status status;</div><div class='ctx'> 	int max_clock;</div><div class='ctx'> </div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN)</div><div class='ctx'> 		return MODE_NO_DBLESCAN;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c<br/>index 1fd068e6e26c..8a84a31c7b48 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crtc.c</a></div><div class='hunk'>@@ -553,8 +553,15 @@ void intel_pipe_update_start(struct intel_atomic_state *state,</div><div class='ctx'> </div><div class='ctx'> 	intel_psr_lock(new_crtc_state);</div><div class='ctx'> </div><div class='del'>-	if (new_crtc_state-&gt;do_async_flip)</div><div class='add'>+	if (new_crtc_state-&gt;do_async_flip) {</div><div class='add'>+		spin_lock_irq(&amp;crtc-&gt;base.dev-&gt;event_lock);</div><div class='add'>+		/* arm the event for the flip done irq handler */</div><div class='add'>+		crtc-&gt;flip_done_event = new_crtc_state-&gt;uapi.event;</div><div class='add'>+		spin_unlock_irq(&amp;crtc-&gt;base.dev-&gt;event_lock);</div><div class='add'>+</div><div class='add'>+		new_crtc_state-&gt;uapi.event = NULL;</div><div class='ctx'> 		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (intel_crtc_needs_vblank_work(new_crtc_state))</div><div class='ctx'> 		intel_crtc_vblank_work_init(new_crtc_state);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c<br/>index 2d15e82c0b3d..49fd100ec98a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_crtc_state_dump.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_crtc_state_dump.c</a></div><div class='hunk'>@@ -262,6 +262,15 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,</div><div class='ctx'> 		drm_dbg_kms(&amp;i915-&gt;drm, "fec: %s, enhanced framing: %s\n",</div><div class='ctx'> 			    str_enabled_disabled(pipe_config-&gt;fec_enable),</div><div class='ctx'> 			    str_enabled_disabled(pipe_config-&gt;enhanced_framing));</div><div class='add'>+</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm, "sdp split: %s\n",</div><div class='add'>+			    str_enabled_disabled(pipe_config-&gt;sdp_split_enable));</div><div class='add'>+</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",</div><div class='add'>+			    str_enabled_disabled(pipe_config-&gt;has_psr),</div><div class='add'>+			    str_enabled_disabled(pipe_config-&gt;has_psr2),</div><div class='add'>+			    str_enabled_disabled(pipe_config-&gt;has_panel_replay),</div><div class='add'>+			    str_enabled_disabled(pipe_config-&gt;enable_psr2_sel_fetch));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg_kms(&amp;i915-&gt;drm, "framestart delay: %d, MSA timing delay: %d\n",</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c<br/>index b342fad180ca..926e2de00eb5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cursor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_cursor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cursor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cursor.c</a></div><div class='hunk'>@@ -21,8 +21,11 @@</div><div class='ctx'> #include "intel_fb_pin.h"</div><div class='ctx'> #include "intel_frontbuffer.h"</div><div class='ctx'> #include "intel_psr.h"</div><div class='add'>+#include "intel_psr_regs.h"</div><div class='ctx'> #include "skl_watermark.h"</div><div class='ctx'> </div><div class='add'>+#include "gem/i915_gem_object.h"</div><div class='add'>+</div><div class='ctx'> /* Cursor formats */</div><div class='ctx'> static const u32 intel_cursor_formats[] = {</div><div class='ctx'> 	DRM_FORMAT_ARGB8888,</div><div class='hunk'>@@ -33,11 +36,11 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)</div><div class='ctx'> 	struct drm_i915_private *dev_priv =</div><div class='ctx'> 		to_i915(plane_state-&gt;uapi.plane-&gt;dev);</div><div class='ctx'> 	const struct drm_framebuffer *fb = plane_state-&gt;hw.fb;</div><div class='del'>-	const struct drm_i915_gem_object *obj = intel_fb_obj(fb);</div><div class='add'>+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);</div><div class='ctx'> 	u32 base;</div><div class='ctx'> </div><div class='ctx'> 	if (DISPLAY_INFO(dev_priv)-&gt;cursor_needs_physical)</div><div class='del'>-		base = sg_dma_address(obj-&gt;mm.pages-&gt;sgl);</div><div class='add'>+		base = i915_gem_object_get_dma_address(obj, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		base = intel_plane_ggtt_offset(plane_state);</div><div class='ctx'> </div><div class='hunk'>@@ -484,6 +487,35 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,</div><div class='add'>+					      const struct intel_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(plane-&gt;base.dev);</div><div class='add'>+	enum pipe pipe = plane-&gt;pipe;</div><div class='add'>+</div><div class='add'>+	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id), 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,</div><div class='add'>+					     const struct intel_crtc_state *crtc_state,</div><div class='add'>+					     const struct intel_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(plane-&gt;base.dev);</div><div class='add'>+	enum pipe pipe = plane-&gt;pipe;</div><div class='add'>+</div><div class='add'>+	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (drm_rect_height(&amp;plane_state-&gt;psr2_sel_fetch_area) &gt; 0)</div><div class='add'>+		intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id),</div><div class='add'>+				  plane_state-&gt;ctl);</div><div class='add'>+	else</div><div class='add'>+		i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* TODO: split into noarm+arm pair */</div><div class='ctx'> static void i9xx_cursor_update_arm(struct intel_plane *plane,</div><div class='ctx'> 				   const struct intel_crtc_state *crtc_state,</div><div class='hunk'>@@ -531,10 +563,10 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,</div><div class='ctx'> 		skl_write_cursor_wm(plane, crtc_state);</div><div class='ctx'> </div><div class='ctx'> 	if (plane_state)</div><div class='del'>-		intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state,</div><div class='del'>-						       plane_state);</div><div class='add'>+		i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,</div><div class='add'>+						 plane_state);</div><div class='ctx'> 	else</div><div class='del'>-		intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);</div><div class='add'>+		i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);</div><div class='ctx'> </div><div class='ctx'> 	if (plane-&gt;cursor.base != base ||</div><div class='ctx'> 	    plane-&gt;cursor.size != fbc_ctl ||</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c<br/>index a8fa76580802..6b25e195232f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cx0_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_cx0_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_cx0_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_cx0_phy.c</a></div><div class='hunk'>@@ -415,9 +415,15 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(encoder-&gt;base.dev);</div><div class='ctx'> 	const struct intel_ddi_buf_trans *trans;</div><div class='ctx'> 	enum phy phy = intel_port_to_phy(i915, encoder-&gt;port);</div><div class='del'>-	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);</div><div class='add'>+	u8 owned_lane_mask;</div><div class='ctx'> 	intel_wakeref_t wakeref;</div><div class='ctx'> 	int n_entries, ln;</div><div class='add'>+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);</div><div class='add'>+</div><div class='add'>+	if (intel_tc_port_in_tbt_alt_mode(dig_port))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);</div><div class='ctx'> </div><div class='ctx'> 	wakeref = intel_cx0_phy_transaction_begin(encoder);</div><div class='ctx'> </div><div class='hunk'>@@ -739,7 +745,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {</div><div class='ctx'> </div><div class='ctx'> /* C20 basic DP 1.4 tables */</div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_rbr = {</div><div class='del'>-	.link_bit_rate = 162000,</div><div class='ctx'> 	.clock = 162000,</div><div class='ctx'> 	.tx = {	0xbe88, /* tx cfg0 */</div><div class='ctx'> 		0x5800, /* tx cfg1 */</div><div class='hunk'>@@ -765,7 +770,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {</div><div class='del'>-	.link_bit_rate = 270000,</div><div class='ctx'> 	.clock = 270000,</div><div class='ctx'> 	.tx = {	0xbe88, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='hunk'>@@ -791,7 +795,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {</div><div class='del'>-	.link_bit_rate = 540000,</div><div class='ctx'> 	.clock = 540000,</div><div class='ctx'> 	.tx = {	0xbe88, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='hunk'>@@ -817,7 +820,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {</div><div class='del'>-	.link_bit_rate = 810000,</div><div class='ctx'> 	.clock = 810000,</div><div class='ctx'> 	.tx = {	0xbe88, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='hunk'>@@ -844,8 +846,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {</div><div class='ctx'> </div><div class='ctx'> /* C20 basic DP 2.0 tables */</div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {</div><div class='del'>-	.link_bit_rate = 1000000, /* 10 Gbps */</div><div class='del'>-	.clock = 312500,</div><div class='add'>+	.clock = 1000000, /* 10 Gbps */</div><div class='ctx'> 	.tx = {	0xbe21, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='ctx'> 		0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -869,8 +870,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {</div><div class='del'>-	.link_bit_rate = 1350000, /* 13.5 Gbps */</div><div class='del'>-	.clock = 421875,</div><div class='add'>+	.clock = 1350000, /* 13.5 Gbps */</div><div class='ctx'> 	.tx = {	0xbea0, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='ctx'> 		0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -895,8 +895,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {</div><div class='del'>-	.link_bit_rate = 2000000, /* 20 Gbps */</div><div class='del'>-	.clock = 625000,</div><div class='add'>+	.clock = 2000000, /* 20 Gbps */</div><div class='ctx'> 	.tx = {	0xbe20, /* tx cfg0 */</div><div class='ctx'> 		0x4800, /* tx cfg1 */</div><div class='ctx'> 		0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1515,7 +1514,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {</div><div class='del'>-	.link_bit_rate = 25175,</div><div class='ctx'> 	.clock = 25175,</div><div class='ctx'> 	.tx = {  0xbe88, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='hunk'>@@ -1541,7 +1539,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {</div><div class='del'>-	.link_bit_rate = 27000,</div><div class='ctx'> 	.clock = 27000,</div><div class='ctx'> 	.tx = {  0xbe88, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='hunk'>@@ -1567,7 +1564,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {</div><div class='del'>-	.link_bit_rate = 74250,</div><div class='ctx'> 	.clock = 74250,</div><div class='ctx'> 	.tx = {  0xbe88, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='hunk'>@@ -1593,7 +1589,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {</div><div class='del'>-	.link_bit_rate = 148500,</div><div class='ctx'> 	.clock = 148500,</div><div class='ctx'> 	.tx = {  0xbe88, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='hunk'>@@ -1619,7 +1614,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_594 = {</div><div class='del'>-	.link_bit_rate = 594000,</div><div class='ctx'> 	.clock = 594000,</div><div class='ctx'> 	.tx = {  0xbe88, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='hunk'>@@ -1645,8 +1639,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_300 = {</div><div class='del'>-	.link_bit_rate = 3000000,</div><div class='del'>-	.clock = 166670,</div><div class='add'>+	.clock = 3000000,</div><div class='ctx'> 	.tx = {  0xbe98, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='ctx'> 		  0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1671,8 +1664,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_600 = {</div><div class='del'>-	.link_bit_rate = 6000000,</div><div class='del'>-	.clock = 333330,</div><div class='add'>+	.clock = 6000000,</div><div class='ctx'> 	.tx = {  0xbe98, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='ctx'> 		  0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1697,8 +1689,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_800 = {</div><div class='del'>-	.link_bit_rate = 8000000,</div><div class='del'>-	.clock = 444440,</div><div class='add'>+	.clock = 8000000,</div><div class='ctx'> 	.tx = {  0xbe98, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='ctx'> 		  0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1723,8 +1714,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {</div><div class='del'>-	.link_bit_rate = 10000000,</div><div class='del'>-	.clock = 555560,</div><div class='add'>+	.clock = 10000000,</div><div class='ctx'> 	.tx = {  0xbe98, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='ctx'> 		  0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1749,8 +1739,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {</div><div class='del'>-	.link_bit_rate = 12000000,</div><div class='del'>-	.clock = 666670,</div><div class='add'>+	.clock = 12000000,</div><div class='ctx'> 	.tx = {  0xbe98, /* tx cfg0 */</div><div class='ctx'> 		  0x9800, /* tx cfg1 */</div><div class='ctx'> 		  0x0000, /* tx cfg2 */</div><div class='hunk'>@@ -1999,7 +1988,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_</div><div class='ctx'> 	else</div><div class='ctx'> 		mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;</div><div class='ctx'> </div><div class='del'>-	pll_state-&gt;link_bit_rate	= pixel_clock;</div><div class='ctx'> 	pll_state-&gt;clock	= pixel_clock;</div><div class='ctx'> 	pll_state-&gt;tx[0]	= 0xbe88;</div><div class='ctx'> 	pll_state-&gt;tx[1]	= 0x9800;</div><div class='hunk'>@@ -2036,7 +2024,7 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; tables[i]; i++) {</div><div class='del'>-		if (clock == tables[i]-&gt;link_bit_rate)</div><div class='add'>+		if (clock == tables[i]-&gt;clock)</div><div class='ctx'> 			return MODE_OK;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2088,7 +2076,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; tables[i]; i++) {</div><div class='del'>-		if (crtc_state-&gt;port_clock == tables[i]-&gt;link_bit_rate) {</div><div class='add'>+		if (crtc_state-&gt;port_clock == tables[i]-&gt;clock) {</div><div class='ctx'> 			crtc_state-&gt;cx0pll_state.c20 = *tables[i];</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2111,7 +2099,7 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,</div><div class='ctx'> static bool intel_c20_use_mplla(u32 clock)</div><div class='ctx'> {</div><div class='ctx'> 	/* 10G and 20G rates use MPLLA */</div><div class='del'>-	if (clock == 312500 || clock == 625000)</div><div class='add'>+	if (clock == 1000000 || clock == 2000000)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -2214,11 +2202,11 @@ static u8 intel_c20_get_dp_rate(u32 clock)</div><div class='ctx'> 		return 6;</div><div class='ctx'> 	case 432000: /* 4.32 Gbps eDP */</div><div class='ctx'> 		return 7;</div><div class='del'>-	case 312500: /* 10 Gbps DP2.0 */</div><div class='add'>+	case 1000000: /* 10 Gbps DP2.0 */</div><div class='ctx'> 		return 8;</div><div class='del'>-	case 421875: /* 13.5 Gbps DP2.0 */</div><div class='add'>+	case 1350000: /* 13.5 Gbps DP2.0 */</div><div class='ctx'> 		return 9;</div><div class='del'>-	case 625000: /* 20 Gbps DP2.0*/</div><div class='add'>+	case 2000000: /* 20 Gbps DP2.0 */</div><div class='ctx'> 		return 10;</div><div class='ctx'> 	case 648000: /* 6.48 Gbps eDP*/</div><div class='ctx'> 		return 11;</div><div class='hunk'>@@ -2236,13 +2224,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (clock) {</div><div class='del'>-	case 166670: /* 3 Gbps */</div><div class='del'>-	case 333330: /* 6 Gbps */</div><div class='del'>-	case 666670: /* 12 Gbps */</div><div class='add'>+	case 300000: /* 3 Gbps */</div><div class='add'>+	case 600000: /* 6 Gbps */</div><div class='add'>+	case 1200000: /* 12 Gbps */</div><div class='ctx'> 		return 1;</div><div class='del'>-	case 444440: /* 8 Gbps */</div><div class='add'>+	case 800000: /* 8 Gbps */</div><div class='ctx'> 		return 2;</div><div class='del'>-	case 555560: /* 10 Gbps */</div><div class='add'>+	case 1000000: /* 10 Gbps */</div><div class='ctx'> 		return 3;</div><div class='ctx'> 	default:</div><div class='ctx'> 		MISSING_CASE(clock);</div><div class='hunk'>@@ -2253,7 +2241,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)</div><div class='ctx'> static bool is_dp2(u32 clock)</div><div class='ctx'> {</div><div class='ctx'> 	/* DP2.0 clock rates */</div><div class='del'>-	if (clock == 312500 || clock == 421875 || clock  == 625000)</div><div class='add'>+	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -2262,11 +2250,11 @@ static bool is_dp2(u32 clock)</div><div class='ctx'> static bool is_hdmi_frl(u32 clock)</div><div class='ctx'> {</div><div class='ctx'> 	switch (clock) {</div><div class='del'>-	case 166670: /* 3 Gbps */</div><div class='del'>-	case 333330: /* 6 Gbps */</div><div class='del'>-	case 444440: /* 8 Gbps */</div><div class='del'>-	case 555560: /* 10 Gbps */</div><div class='del'>-	case 666670: /* 12 Gbps */</div><div class='add'>+	case 300000: /* 3 Gbps */</div><div class='add'>+	case 600000: /* 6 Gbps */</div><div class='add'>+	case 800000: /* 8 Gbps */</div><div class='add'>+	case 1000000: /* 10 Gbps */</div><div class='add'>+	case 1200000: /* 12 Gbps */</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -2299,6 +2287,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,</div><div class='ctx'> 	const struct intel_c20pll_state *pll_state = &amp;crtc_state-&gt;cx0pll_state.c20;</div><div class='ctx'> 	bool dp = false;</div><div class='ctx'> 	int lane = crtc_state-&gt;lane_count &gt; 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;</div><div class='add'>+	u32 clock = crtc_state-&gt;port_clock;</div><div class='ctx'> 	bool cntx;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -2337,7 +2326,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* 3.3 mpllb or mplla configuration */</div><div class='del'>-	if (intel_c20_use_mplla(pll_state-&gt;clock)) {</div><div class='add'>+	if (intel_c20_use_mplla(clock)) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(pll_state-&gt;mplla); i++) {</div><div class='ctx'> 			if (cntx)</div><div class='ctx'> 				intel_c20_sram_write(i915, encoder-&gt;port, INTEL_CX0_LANE0,</div><div class='hunk'>@@ -2364,23 +2353,23 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,</div><div class='ctx'> 	/* 4. Program custom width to match the link protocol */</div><div class='ctx'> 	intel_cx0_rmw(i915, encoder-&gt;port, lane, PHY_C20_VDR_CUSTOM_WIDTH,</div><div class='ctx'> 		      PHY_C20_CUSTOM_WIDTH_MASK,</div><div class='del'>-		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state-&gt;clock, dp)),</div><div class='add'>+		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)),</div><div class='ctx'> 		      MB_WRITE_COMMITTED);</div><div class='ctx'> </div><div class='ctx'> 	/* 5. For DP or 6. For HDMI */</div><div class='ctx'> 	if (dp) {</div><div class='ctx'> 		intel_cx0_rmw(i915, encoder-&gt;port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,</div><div class='ctx'> 			      BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,</div><div class='del'>-			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state-&gt;clock)),</div><div class='add'>+			      BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),</div><div class='ctx'> 			      MB_WRITE_COMMITTED);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		intel_cx0_rmw(i915, encoder-&gt;port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,</div><div class='ctx'> 			      BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,</div><div class='del'>-			      is_hdmi_frl(pll_state-&gt;clock) ? BIT(7) : 0,</div><div class='add'>+			      is_hdmi_frl(clock) ? BIT(7) : 0,</div><div class='ctx'> 			      MB_WRITE_COMMITTED);</div><div class='ctx'> </div><div class='ctx'> 		intel_cx0_write(i915, encoder-&gt;port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,</div><div class='del'>-				intel_c20_get_hdmi_rate(pll_state-&gt;clock),</div><div class='add'>+				intel_c20_get_hdmi_rate(clock),</div><div class='ctx'> 				MB_WRITE_COMMITTED);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2479,7 +2468,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> 	val |= XELPDP_FORWARD_CLOCK_UNGATE;</div><div class='ctx'> </div><div class='del'>-	if (is_hdmi_frl(crtc_state-&gt;port_clock))</div><div class='add'>+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &amp;&amp;</div><div class='add'>+	    is_hdmi_frl(crtc_state-&gt;port_clock))</div><div class='ctx'> 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);</div><div class='ctx'> 	else</div><div class='ctx'> 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);</div><div class='hunk'>@@ -3077,24 +3067,29 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(crtc-&gt;base.dev);</div><div class='ctx'> 	const struct intel_c20pll_state *mpll_sw_state = &amp;state-&gt;cx0pll_state.c20;</div><div class='del'>-	bool use_mplla;</div><div class='add'>+	bool sw_use_mpllb = mpll_sw_state-&gt;tx[0] &amp; C20_PHY_USE_MPLLB;</div><div class='add'>+	bool hw_use_mpllb = mpll_hw_state-&gt;tx[0] &amp; C20_PHY_USE_MPLLB;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	use_mplla = intel_c20_use_mplla(mpll_hw_state-&gt;clock);</div><div class='del'>-	if (use_mplla) {</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(mpll_sw_state-&gt;mplla); i++) {</div><div class='del'>-			I915_STATE_WARN(i915, mpll_hw_state-&gt;mplla[i] != mpll_sw_state-&gt;mplla[i],</div><div class='del'>-					"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",</div><div class='del'>-					crtc-&gt;base.base.id, crtc-&gt;base.name, i,</div><div class='del'>-					mpll_sw_state-&gt;mplla[i], mpll_hw_state-&gt;mplla[i]);</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='add'>+	I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,</div><div class='add'>+			"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",</div><div class='add'>+			crtc-&gt;base.base.id, crtc-&gt;base.name,</div><div class='add'>+			sw_use_mpllb, hw_use_mpllb);</div><div class='add'>+</div><div class='add'>+	if (hw_use_mpllb) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(mpll_sw_state-&gt;mpllb); i++) {</div><div class='ctx'> 			I915_STATE_WARN(i915, mpll_hw_state-&gt;mpllb[i] != mpll_sw_state-&gt;mpllb[i],</div><div class='ctx'> 					"[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",</div><div class='ctx'> 					crtc-&gt;base.base.id, crtc-&gt;base.name, i,</div><div class='ctx'> 					mpll_sw_state-&gt;mpllb[i], mpll_hw_state-&gt;mpllb[i]);</div><div class='ctx'> 		}</div><div class='add'>+	} else {</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(mpll_sw_state-&gt;mplla); i++) {</div><div class='add'>+			I915_STATE_WARN(i915, mpll_hw_state-&gt;mplla[i] != mpll_sw_state-&gt;mplla[i],</div><div class='add'>+					"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",</div><div class='add'>+					crtc-&gt;base.base.id, crtc-&gt;base.name, i,</div><div class='add'>+					mpll_sw_state-&gt;mplla[i], mpll_hw_state-&gt;mplla[i]);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(mpll_sw_state-&gt;tx); i++) {</div><div class='hunk'>@@ -3136,6 +3131,9 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state,</div><div class='ctx'> 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);</div><div class='ctx'> 	phy = intel_port_to_phy(i915, encoder-&gt;port);</div><div class='ctx'> </div><div class='add'>+	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	intel_cx0pll_readout_hw_state(encoder, &amp;mpll_hw_state);</div><div class='ctx'> </div><div class='ctx'> 	if (intel_is_c10phy(i915, phy))</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c<br/>index 38f28c480b38..12a29363e5df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_ddi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_ddi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_ddi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_ddi.c</a></div><div class='hunk'>@@ -3672,16 +3672,42 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,</div><div class='ctx'> 		AUDIO_OUTPUT_ENABLE(cpu_transcoder);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,</div><div class='del'>-					 struct intel_crtc_state *crtc_state)</div><div class='add'>+static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> {</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt;= 12 &amp;&amp; crtc_state-&gt;port_clock &gt; 594000)</div><div class='del'>-		crtc_state-&gt;min_voltage_level = 2;</div><div class='del'>-	else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &amp;&amp;</div><div class='del'>-		 crtc_state-&gt;port_clock &gt; 594000)</div><div class='del'>-		crtc_state-&gt;min_voltage_level = 3;</div><div class='del'>-	else if (DISPLAY_VER(dev_priv) &gt;= 11 &amp;&amp; crtc_state-&gt;port_clock &gt; 594000)</div><div class='del'>-		crtc_state-&gt;min_voltage_level = 1;</div><div class='add'>+	if (crtc_state-&gt;port_clock &gt; 594000)</div><div class='add'>+		return 2;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	if (crtc_state-&gt;port_clock &gt; 594000)</div><div class='add'>+		return 3;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	if (crtc_state-&gt;port_clock &gt; 594000)</div><div class='add'>+		return 1;</div><div class='add'>+	else</div><div class='add'>+		return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(crtc_state-&gt;uapi.crtc-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &gt;= 14)</div><div class='add'>+		crtc_state-&gt;min_voltage_level = icl_ddi_min_voltage_level(crtc_state);</div><div class='add'>+	else if (DISPLAY_VER(dev_priv) &gt;= 12)</div><div class='add'>+		crtc_state-&gt;min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);</div><div class='add'>+	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))</div><div class='add'>+		crtc_state-&gt;min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);</div><div class='add'>+	else if (DISPLAY_VER(dev_priv) &gt;= 11)</div><div class='add'>+		crtc_state-&gt;min_voltage_level = icl_ddi_min_voltage_level(crtc_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,</div><div class='hunk'>@@ -3895,7 +3921,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,</div><div class='ctx'> 		pipe_config-&gt;lane_lat_optim_mask =</div><div class='ctx'> 			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);</div><div class='ctx'> </div><div class='del'>-	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);</div><div class='add'>+	intel_ddi_compute_min_voltage_level(pipe_config);</div><div class='ctx'> </div><div class='ctx'> 	intel_hdmi_read_gcp_infoframe(encoder, pipe_config);</div><div class='ctx'> </div><div class='hunk'>@@ -4175,7 +4201,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,</div><div class='ctx'> 		pipe_config-&gt;lane_lat_optim_mask =</div><div class='ctx'> 			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config-&gt;lane_count);</div><div class='ctx'> </div><div class='del'>-	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);</div><div class='add'>+	intel_ddi_compute_min_voltage_level(pipe_config);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h<br/>index 63853a1f6582..434de7196875 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_ddi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_ddi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_ddi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_ddi.h</a></div><div class='hunk'>@@ -70,8 +70,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,</div><div class='ctx'> bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);</div><div class='ctx'> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,</div><div class='ctx'> 				    bool state);</div><div class='del'>-void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,</div><div class='del'>-					 struct intel_crtc_state *crtc_state);</div><div class='add'>+void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state);</div><div class='ctx'> int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,</div><div class='ctx'> 			       enum transcoder cpu_transcoder,</div><div class='ctx'> 			       bool enable, u32 hdcp_mask);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c<br/>index 5cf162628b95..b10aad15a63d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display.c</a></div><div class='hunk'>@@ -2627,7 +2627,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta</div><div class='ctx'> 		crtc_vblank_start = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt; 3)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &gt;= 4)</div><div class='ctx'> 		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),</div><div class='ctx'> 			       vsyncshift);</div><div class='ctx'> </div><div class='hunk'>@@ -3167,7 +3167,7 @@ static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 36:</div><div class='ctx'> 		/* Port output 12BPC defined for ADLP+ */</div><div class='del'>-		if (DISPLAY_VER(dev_priv) &gt; 12)</div><div class='add'>+		if (DISPLAY_VER(dev_priv) &gt;= 13)</div><div class='ctx'> 			val |= PIPE_MISC_BPC_12_ADLP;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -3224,7 +3224,7 @@ int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)</div><div class='ctx'> 	 * MIPI DSI HW readout.</div><div class='ctx'> 	 */</div><div class='ctx'> 	case PIPE_MISC_BPC_12_ADLP:</div><div class='del'>-		if (DISPLAY_VER(dev_priv) &gt; 12)</div><div class='add'>+		if (DISPLAY_VER(dev_priv) &gt;= 13)</div><div class='ctx'> 			return 36;</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -3746,8 +3746,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,</div><div class='ctx'> 	if (!active)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	intel_dsc_get_config(pipe_config);</div><div class='ctx'> 	intel_bigjoiner_get_config(pipe_config);</div><div class='add'>+	intel_dsc_get_config(pipe_config);</div><div class='ctx'> </div><div class='ctx'> 	if (!transcoder_is_dsi(pipe_config-&gt;cpu_transcoder) ||</div><div class='ctx'> 	    DISPLAY_VER(dev_priv) &gt;= 11)</div><div class='hunk'>@@ -4923,6 +4923,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> </div><div class='ctx'> #define PIPE_CONF_CHECK_X(name) do { \</div><div class='ctx'> 	if (current_config-&gt;name != pipe_config-&gt;name) { \</div><div class='add'>+		BUILD_BUG_ON_MSG(__same_type(current_config-&gt;name, bool), \</div><div class='add'>+				 __stringify(name) " is bool");	\</div><div class='ctx'> 		pipe_config_mismatch(fastset, crtc, __stringify(name), \</div><div class='ctx'> 				     "(expected 0x%08x, found 0x%08x)", \</div><div class='ctx'> 				     current_config-&gt;name, \</div><div class='hunk'>@@ -4933,6 +4935,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> </div><div class='ctx'> #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \</div><div class='ctx'> 	if ((current_config-&gt;name &amp; (mask)) != (pipe_config-&gt;name &amp; (mask))) { \</div><div class='add'>+		BUILD_BUG_ON_MSG(__same_type(current_config-&gt;name, bool), \</div><div class='add'>+				 __stringify(name) " is bool");	\</div><div class='ctx'> 		pipe_config_mismatch(fastset, crtc, __stringify(name), \</div><div class='ctx'> 				     "(expected 0x%08x, found 0x%08x)", \</div><div class='ctx'> 				     current_config-&gt;name &amp; (mask), \</div><div class='hunk'>@@ -4943,6 +4947,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> </div><div class='ctx'> #define PIPE_CONF_CHECK_I(name) do { \</div><div class='ctx'> 	if (current_config-&gt;name != pipe_config-&gt;name) { \</div><div class='add'>+		BUILD_BUG_ON_MSG(__same_type(current_config-&gt;name, bool), \</div><div class='add'>+				 __stringify(name) " is bool");	\</div><div class='ctx'> 		pipe_config_mismatch(fastset, crtc, __stringify(name), \</div><div class='ctx'> 				     "(expected %i, found %i)", \</div><div class='ctx'> 				     current_config-&gt;name, \</div><div class='hunk'>@@ -4953,6 +4959,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> </div><div class='ctx'> #define PIPE_CONF_CHECK_BOOL(name) do { \</div><div class='ctx'> 	if (current_config-&gt;name != pipe_config-&gt;name) { \</div><div class='add'>+		BUILD_BUG_ON_MSG(!__same_type(current_config-&gt;name, bool), \</div><div class='add'>+				 __stringify(name) " is not bool");	\</div><div class='ctx'> 		pipe_config_mismatch(fastset, crtc,  __stringify(name), \</div><div class='ctx'> 				     "(expected %s, found %s)", \</div><div class='ctx'> 				     str_yes_no(current_config-&gt;name), \</div><div class='hunk'>@@ -5091,8 +5099,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> #define PIPE_CONF_QUIRK(quirk) \</div><div class='ctx'> 	((current_config-&gt;quirks | pipe_config-&gt;quirks) &amp; (quirk))</div><div class='ctx'> </div><div class='del'>-	PIPE_CONF_CHECK_I(hw.enable);</div><div class='del'>-	PIPE_CONF_CHECK_I(hw.active);</div><div class='add'>+	PIPE_CONF_CHECK_BOOL(hw.enable);</div><div class='add'>+	PIPE_CONF_CHECK_BOOL(hw.active);</div><div class='ctx'> </div><div class='ctx'> 	PIPE_CONF_CHECK_I(cpu_transcoder);</div><div class='ctx'> 	PIPE_CONF_CHECK_I(mst_master_transcoder);</div><div class='hunk'>@@ -5301,8 +5309,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,</div><div class='ctx'> 	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);</div><div class='ctx'> 	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);</div><div class='ctx'> </div><div class='del'>-	PIPE_CONF_CHECK_I(dsc.compression_enable);</div><div class='del'>-	PIPE_CONF_CHECK_I(dsc.dsc_split);</div><div class='add'>+	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);</div><div class='add'>+	PIPE_CONF_CHECK_BOOL(dsc.dsc_split);</div><div class='ctx'> 	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);</div><div class='ctx'> </div><div class='ctx'> 	PIPE_CONF_CHECK_BOOL(splitter.enable);</div><div class='hunk'>@@ -5918,6 +5926,17 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Bigjoiner+async flip is busted currently.</div><div class='add'>+	 * Remove this check once the issues are fixed.</div><div class='add'>+	 */</div><div class='add'>+	if (new_crtc_state-&gt;bigjoiner_pipes) {</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='add'>+			    "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",</div><div class='add'>+			    crtc-&gt;base.base.id, crtc-&gt;base.name);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,</div><div class='ctx'> 					     new_plane_state, i) {</div><div class='ctx'> 		if (plane-&gt;pipe != crtc-&gt;pipe)</div><div class='hunk'>@@ -6955,24 +6974,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)</div><div class='ctx'> 	drm_WARN_ON(&amp;dev_priv-&gt;drm, update_pipes);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)</div><div class='del'>-{</div><div class='del'>-	struct intel_atomic_state *state, *next;</div><div class='del'>-	struct llist_node *freed;</div><div class='del'>-</div><div class='del'>-	freed = llist_del_all(&amp;dev_priv-&gt;display.atomic_helper.free_list);</div><div class='del'>-	llist_for_each_entry_safe(state, next, freed, freed)</div><div class='del'>-		drm_atomic_state_put(&amp;state-&gt;base);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void intel_atomic_helper_free_state_worker(struct work_struct *work)</div><div class='del'>-{</div><div class='del'>-	struct drm_i915_private *dev_priv =</div><div class='del'>-		container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);</div><div class='del'>-</div><div class='del'>-	intel_atomic_helper_free_state(dev_priv);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(intel_state-&gt;base.dev);</div><div class='hunk'>@@ -7008,8 +7009,6 @@ static void intel_atomic_cleanup_work(struct work_struct *work)</div><div class='ctx'> 	drm_atomic_helper_cleanup_planes(&amp;i915-&gt;drm, &amp;state-&gt;base);</div><div class='ctx'> 	drm_atomic_helper_commit_cleanup_done(&amp;state-&gt;base);</div><div class='ctx'> 	drm_atomic_state_put(&amp;state-&gt;base);</div><div class='del'>-</div><div class='del'>-	intel_atomic_helper_free_state(i915);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)</div><div class='hunk'>@@ -7354,7 +7353,7 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,</div><div class='ctx'> 		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)</div><div class='ctx'> 			intel_color_cleanup_commit(new_crtc_state);</div><div class='ctx'> </div><div class='del'>-		drm_atomic_helper_cleanup_planes(dev, &amp;state-&gt;base);</div><div class='add'>+		drm_atomic_helper_unprepare_planes(dev, &amp;state-&gt;base);</div><div class='ctx'> 		intel_runtime_pm_put(&amp;dev_priv-&gt;runtime_pm, state-&gt;wakeref);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7734,6 +7733,16 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,</div><div class='ctx'> 	    mode-&gt;vtotal &gt; vtotal_max)</div><div class='ctx'> 		return MODE_V_ILLEGAL;</div><div class='ctx'> </div><div class='add'>+	return MODE_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,</div><div class='add'>+						     const struct drm_display_mode *mode)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Additional transcoder timing limits,</div><div class='add'>+	 * excluding BXT/GLK DSI transcoders.</div><div class='add'>+	 */</div><div class='ctx'> 	if (DISPLAY_VER(dev_priv) &gt;= 5) {</div><div class='ctx'> 		if (mode-&gt;hdisplay &lt; 64 ||</div><div class='ctx'> 		    mode-&gt;htotal - mode-&gt;hdisplay &lt; 32)</div><div class='hunk'>@@ -7753,7 +7762,7 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev,</div><div class='ctx'> 	 * Cantiga+ cannot handle modes with a hsync front porch of 0.</div><div class='ctx'> 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.</div><div class='ctx'> 	 */</div><div class='del'>-	if ((DISPLAY_VER(dev_priv) &gt; 4 || IS_G4X(dev_priv)) &amp;&amp;</div><div class='add'>+	if ((DISPLAY_VER(dev_priv) &gt;= 5 || IS_G4X(dev_priv)) &amp;&amp;</div><div class='ctx'> 	    mode-&gt;hsync_start == mode-&gt;hdisplay)</div><div class='ctx'> 		return MODE_H_ILLEGAL;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h<br/>index 8548f49e3972..f4a0773f0fca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display.h</a></div><div class='hunk'>@@ -402,6 +402,9 @@ enum drm_mode_status</div><div class='ctx'> intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,</div><div class='ctx'> 				const struct drm_display_mode *mode,</div><div class='ctx'> 				bool bigjoiner);</div><div class='add'>+enum drm_mode_status</div><div class='add'>+intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915,</div><div class='add'>+				const struct drm_display_mode *mode);</div><div class='ctx'> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);</div><div class='ctx'> bool is_trans_port_sync_mode(const struct intel_crtc_state *state);</div><div class='ctx'> bool is_trans_port_sync_master(const struct intel_crtc_state *state);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h<br/>index 7e82b87e9cde..47297ed85822 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_core.h</a></div><div class='hunk'>@@ -298,12 +298,6 @@ struct intel_display {</div><div class='ctx'> 		const struct intel_audio_funcs *audio;</div><div class='ctx'> 	} funcs;</div><div class='ctx'> </div><div class='del'>-	/* Grouping using anonymous structs. Keep sorted. */</div><div class='del'>-	struct intel_atomic_helper {</div><div class='del'>-		struct llist_head free_list;</div><div class='del'>-		struct work_struct free_work;</div><div class='del'>-	} atomic_helper;</div><div class='del'>-</div><div class='ctx'> 	struct {</div><div class='ctx'> 		/* backlight registers and fields in struct intel_panel */</div><div class='ctx'> 		struct mutex lock;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c<br/>index 915420d0cef8..d951edb36687 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_debugfs.c</a></div><div class='hunk'>@@ -1095,7 +1095,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(intel_display_debugfs_files); i++) {</div><div class='ctx'> 		debugfs_create_file(intel_display_debugfs_files[i].name,</div><div class='del'>-				    S_IRUGO | S_IWUSR,</div><div class='add'>+				    0644,</div><div class='ctx'> 				    minor-&gt;debugfs_root,</div><div class='ctx'> 				    to_i915(minor-&gt;dev),</div><div class='ctx'> 				    intel_display_debugfs_files[i].fops);</div><div class='hunk'>@@ -1116,11 +1116,10 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)</div><div class='ctx'> </div><div class='ctx'> static int i915_panel_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct intel_dp *intel_dp =</div><div class='del'>-		intel_attached_dp(to_intel_connector(connector));</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct intel_dp *intel_dp = intel_attached_dp(connector);</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;status != connector_status_connected)</div><div class='add'>+	if (connector-&gt;base.status != connector_status_connected)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	seq_printf(m, "Panel power up delay: %d\n",</div><div class='hunk'>@@ -1138,23 +1137,23 @@ DEFINE_SHOW_ATTRIBUTE(i915_panel);</div><div class='ctx'> </div><div class='ctx'> static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='del'>-	struct intel_connector *intel_connector = to_intel_connector(connector);</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = drm_modeset_lock_single_interruptible(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (!connector-&gt;encoder || connector-&gt;status != connector_status_connected) {</div><div class='add'>+	if (!connector-&gt;base.encoder ||</div><div class='add'>+	    connector-&gt;base.status != connector_status_connected) {</div><div class='ctx'> 		ret = -ENODEV;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	seq_printf(m, "%s:%d HDCP version: ", connector-&gt;name,</div><div class='del'>-		   connector-&gt;base.id);</div><div class='del'>-	intel_hdcp_info(m, intel_connector);</div><div class='add'>+	seq_printf(m, "%s:%d HDCP version: ", connector-&gt;base.name,</div><div class='add'>+		   connector-&gt;base.base.id);</div><div class='add'>+	intel_hdcp_info(m, connector);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	drm_modeset_unlock(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='hunk'>@@ -1165,16 +1164,16 @@ DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);</div><div class='ctx'> </div><div class='ctx'> static int i915_lpsp_capability_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='del'>-	struct intel_encoder *encoder;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='add'>+	int connector_type = connector-&gt;base.connector_type;</div><div class='ctx'> 	bool lpsp_capable = false;</div><div class='ctx'> </div><div class='del'>-	encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='ctx'> 	if (!encoder)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;status != connector_status_connected)</div><div class='add'>+	if (connector-&gt;base.status != connector_status_connected)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	if (DISPLAY_VER(i915) &gt;= 13)</div><div class='hunk'>@@ -1187,15 +1186,15 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)</div><div class='ctx'> 		 */</div><div class='ctx'> 		lpsp_capable = encoder-&gt;port &lt;= PORT_B;</div><div class='ctx'> 	else if (DISPLAY_VER(i915) == 11)</div><div class='del'>-		lpsp_capable = (connector-&gt;connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='del'>-				connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP);</div><div class='add'>+		lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='add'>+				connector_type == DRM_MODE_CONNECTOR_eDP);</div><div class='ctx'> 	else if (IS_DISPLAY_VER(i915, 9, 10))</div><div class='ctx'> 		lpsp_capable = (encoder-&gt;port == PORT_A &amp;&amp;</div><div class='del'>-				(connector-&gt;connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='del'>-				 connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP ||</div><div class='del'>-				 connector-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort));</div><div class='add'>+				(connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='add'>+				 connector_type == DRM_MODE_CONNECTOR_eDP ||</div><div class='add'>+				 connector_type == DRM_MODE_CONNECTOR_DisplayPort));</div><div class='ctx'> 	else if (IS_HASWELL(i915) || IS_BROADWELL(i915))</div><div class='del'>-		lpsp_capable = connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP;</div><div class='add'>+		lpsp_capable = connector_type == DRM_MODE_CONNECTOR_eDP;</div><div class='ctx'> </div><div class='ctx'> 	seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable");</div><div class='ctx'> </div><div class='hunk'>@@ -1205,7 +1204,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);</div><div class='ctx'> </div><div class='ctx'> static int i915_dsc_fec_support_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct intel_connector *connector = to_intel_connector(m-&gt;private);</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct intel_dp *intel_dp;</div><div class='hunk'>@@ -1275,13 +1274,13 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,</div><div class='ctx'> 					  const char __user *ubuf,</div><div class='ctx'> 					  size_t len, loff_t *offp)</div><div class='ctx'> {</div><div class='add'>+	struct seq_file *m = file-&gt;private_data;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='add'>+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);</div><div class='ctx'> 	bool dsc_enable = false;</div><div class='ctx'> 	int ret;</div><div class='del'>-	struct drm_connector *connector =</div><div class='del'>-		((struct seq_file *)file-&gt;private_data)-&gt;private;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(encoder-&gt;base.dev);</div><div class='del'>-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);</div><div class='ctx'> </div><div class='ctx'> 	if (len == 0)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1319,22 +1318,22 @@ static const struct file_operations i915_dsc_fec_support_fops = {</div><div class='ctx'> </div><div class='ctx'> static int i915_dsc_bpc_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct intel_crtc_state *crtc_state;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!encoder)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	ret = drm_modeset_lock_single_interruptible(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+	ret = drm_modeset_lock_single_interruptible(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	crtc = connector-&gt;state-&gt;crtc;</div><div class='del'>-	if (connector-&gt;status != connector_status_connected || !crtc) {</div><div class='add'>+	crtc = connector-&gt;base.state-&gt;crtc;</div><div class='add'>+	if (connector-&gt;base.status != connector_status_connected || !crtc) {</div><div class='ctx'> 		ret = -ENODEV;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1342,7 +1341,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)</div><div class='ctx'> 	crtc_state = to_intel_crtc_state(crtc-&gt;state);</div><div class='ctx'> 	seq_printf(m, "Input_BPC: %d\n", crtc_state-&gt;dsc.config.bits_per_component);</div><div class='ctx'> </div><div class='del'>-out:	drm_modeset_unlock(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+out:	drm_modeset_unlock(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1351,9 +1350,9 @@ static ssize_t i915_dsc_bpc_write(struct file *file,</div><div class='ctx'> 				  const char __user *ubuf,</div><div class='ctx'> 				  size_t len, loff_t *offp)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector =</div><div class='del'>-		((struct seq_file *)file-&gt;private_data)-&gt;private;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='add'>+	struct seq_file *m = file-&gt;private_data;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='ctx'> 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);</div><div class='ctx'> 	int dsc_bpc = 0;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1385,22 +1384,22 @@ static const struct file_operations i915_dsc_bpc_fops = {</div><div class='ctx'> </div><div class='ctx'> static int i915_dsc_output_format_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct intel_crtc_state *crtc_state;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!encoder)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	ret = drm_modeset_lock_single_interruptible(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+	ret = drm_modeset_lock_single_interruptible(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	crtc = connector-&gt;state-&gt;crtc;</div><div class='del'>-	if (connector-&gt;status != connector_status_connected || !crtc) {</div><div class='add'>+	crtc = connector-&gt;base.state-&gt;crtc;</div><div class='add'>+	if (connector-&gt;base.status != connector_status_connected || !crtc) {</div><div class='ctx'> 		ret = -ENODEV;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1409,7 +1408,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)</div><div class='ctx'> 	seq_printf(m, "DSC_Output_Format: %s\n",</div><div class='ctx'> 		   intel_output_format_name(crtc_state-&gt;output_format));</div><div class='ctx'> </div><div class='del'>-out:	drm_modeset_unlock(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+out:	drm_modeset_unlock(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1418,9 +1417,9 @@ static ssize_t i915_dsc_output_format_write(struct file *file,</div><div class='ctx'> 					    const char __user *ubuf,</div><div class='ctx'> 					    size_t len, loff_t *offp)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector =</div><div class='del'>-		((struct seq_file *)file-&gt;private_data)-&gt;private;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='add'>+	struct seq_file *m = file-&gt;private_data;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='ctx'> 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);</div><div class='ctx'> 	int dsc_output_format = 0;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1452,33 +1451,32 @@ static const struct file_operations i915_dsc_output_format_fops = {</div><div class='ctx'> </div><div class='ctx'> static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = m-&gt;private;</div><div class='del'>-	struct drm_device *dev = connector-&gt;dev;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct intel_dp *intel_dp;</div><div class='del'>-	struct intel_connector *intel_connector = to_intel_connector(connector);</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!encoder)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	ret = drm_modeset_lock_single_interruptible(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+	ret = drm_modeset_lock_single_interruptible(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	crtc = connector-&gt;state-&gt;crtc;</div><div class='del'>-	if (connector-&gt;status != connector_status_connected || !crtc) {</div><div class='add'>+	crtc = connector-&gt;base.state-&gt;crtc;</div><div class='add'>+	if (connector-&gt;base.status != connector_status_connected || !crtc) {</div><div class='ctx'> 		ret = -ENODEV;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	intel_dp = intel_attached_dp(intel_connector);</div><div class='add'>+	intel_dp = intel_attached_dp(connector);</div><div class='ctx'> 	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",</div><div class='ctx'> 		   str_yes_no(intel_dp-&gt;force_dsc_fractional_bpp_en));</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	drm_modeset_unlock(&amp;dev-&gt;mode_config.connection_mutex);</div><div class='add'>+	drm_modeset_unlock(&amp;i915-&gt;drm.mode_config.connection_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1487,10 +1485,10 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,</div><div class='ctx'> 					     const char __user *ubuf,</div><div class='ctx'> 					     size_t len, loff_t *offp)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector =</div><div class='del'>-		((struct seq_file *)file-&gt;private_data)-&gt;private;</div><div class='del'>-	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(encoder-&gt;base.dev);</div><div class='add'>+	struct seq_file *m = file-&gt;private_data;</div><div class='add'>+	struct intel_connector *connector = m-&gt;private;</div><div class='add'>+	struct intel_encoder *encoder = intel_attached_encoder(connector);</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);</div><div class='ctx'> 	bool dsc_fractional_bpp_enable = false;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1565,39 +1563,38 @@ DEFINE_SHOW_ATTRIBUTE(intel_crtc_pipe);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * intel_connector_debugfs_add - add i915 specific connector debugfs files</div><div class='del'>- * @intel_connector: pointer to a registered drm_connector</div><div class='add'>+ * @connector: pointer to a registered intel_connector</div><div class='ctx'>  *</div><div class='ctx'>  * Cleanup will be done by drm_connector_unregister() through a call to</div><div class='ctx'>  * drm_debugfs_connector_remove().</div><div class='ctx'>  */</div><div class='del'>-void intel_connector_debugfs_add(struct intel_connector *intel_connector)</div><div class='add'>+void intel_connector_debugfs_add(struct intel_connector *connector)</div><div class='ctx'> {</div><div class='del'>-	struct drm_connector *connector = &amp;intel_connector-&gt;base;</div><div class='del'>-	struct dentry *root = connector-&gt;debugfs_entry;</div><div class='del'>-	struct drm_i915_private *dev_priv = to_i915(connector-&gt;dev);</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='add'>+	struct dentry *root = connector-&gt;base.debugfs_entry;</div><div class='add'>+	int connector_type = connector-&gt;base.connector_type;</div><div class='ctx'> </div><div class='ctx'> 	/* The connector must have been registered beforehands. */</div><div class='ctx'> 	if (!root)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	intel_drrs_connector_debugfs_add(intel_connector);</div><div class='del'>-	intel_psr_connector_debugfs_add(intel_connector);</div><div class='add'>+	intel_drrs_connector_debugfs_add(connector);</div><div class='add'>+	intel_psr_connector_debugfs_add(connector);</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='del'>-		debugfs_create_file("i915_panel_timings", S_IRUGO, root,</div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_eDP)</div><div class='add'>+		debugfs_create_file("i915_panel_timings", 0444, root,</div><div class='ctx'> 				    connector, &amp;i915_panel_fops);</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_HDMIA ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_HDMIB) {</div><div class='del'>-		debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,</div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_HDMIA ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_HDMIB) {</div><div class='add'>+		debugfs_create_file("i915_hdcp_sink_capability", 0444, root,</div><div class='ctx'> 				    connector, &amp;i915_hdcp_sink_capability_fops);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt;= 11 &amp;&amp;</div><div class='del'>-	    ((connector-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort &amp;&amp;</div><div class='del'>-	    !to_intel_connector(connector)-&gt;mst_port) ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP)) {</div><div class='add'>+	if (DISPLAY_VER(i915) &gt;= 11 &amp;&amp;</div><div class='add'>+	    ((connector_type == DRM_MODE_CONNECTOR_DisplayPort &amp;&amp; !connector-&gt;mst_port) ||</div><div class='add'>+	     connector_type == DRM_MODE_CONNECTOR_eDP)) {</div><div class='ctx'> 		debugfs_create_file("i915_dsc_fec_support", 0644, root,</div><div class='ctx'> 				    connector, &amp;i915_dsc_fec_support_fops);</div><div class='ctx'> </div><div class='hunk'>@@ -1611,11 +1608,11 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)</div><div class='ctx'> 				    connector, &amp;i915_dsc_fractional_bpp_fops);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_eDP ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_DisplayPort ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_HDMIA ||</div><div class='del'>-	    connector-&gt;connector_type == DRM_MODE_CONNECTOR_HDMIB)</div><div class='add'>+	if (connector_type == DRM_MODE_CONNECTOR_DSI ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_eDP ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_HDMIA ||</div><div class='add'>+	    connector_type == DRM_MODE_CONNECTOR_HDMIB)</div><div class='ctx'> 		debugfs_create_file("i915_lpsp_capability", 0444, root,</div><div class='ctx'> 				    connector, &amp;i915_lpsp_capability_fops);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h<br/>index 4299cc452e05..fe4268813786 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_device.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_device.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_device.h</a></div><div class='hunk'>@@ -36,7 +36,7 @@ struct drm_printer;</div><div class='ctx'> #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) &gt;= 5)</div><div class='ctx'> #define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)-&gt;has_cdclk_crawl)</div><div class='ctx'> #define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)-&gt;has_cdclk_squash)</div><div class='del'>-#define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) &amp;&amp; DISPLAY_VER(i915) &gt;= 7)</div><div class='add'>+#define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) &amp;&amp; IS_DISPLAY_VER(i915, 7, 13))</div><div class='ctx'> #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))</div><div class='ctx'> #define HAS_DDI(i915)			(DISPLAY_INFO(i915)-&gt;has_ddi)</div><div class='ctx'> #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)-&gt;pipe_mask != 0)</div><div class='hunk'>@@ -49,7 +49,7 @@ struct drm_printer;</div><div class='ctx'> #define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)-&gt;has_dsc)</div><div class='ctx'> #define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)-&gt;fbc_mask != 0)</div><div class='ctx'> #define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)-&gt;has_fpga_dbg)</div><div class='del'>-#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) &gt; 2)</div><div class='add'>+#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) &gt;= 3)</div><div class='ctx'> #define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) &gt;= 4)</div><div class='ctx'> #define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) &gt;= 10 || IS_KABYLAKE(i915))</div><div class='ctx'> #define HAS_GMCH(i915)			(DISPLAY_INFO(i915)-&gt;has_gmch)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c<br/>index 62f7b10484be..9df9097a0255 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_driver.c</a></div><div class='hunk'>@@ -259,10 +259,6 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto cleanup_vga_client_pw_domain_dmc;</div><div class='ctx'> </div><div class='del'>-	init_llist_head(&amp;i915-&gt;display.atomic_helper.free_list);</div><div class='del'>-	INIT_WORK(&amp;i915-&gt;display.atomic_helper.free_work,</div><div class='del'>-		  intel_atomic_helper_free_state_worker);</div><div class='del'>-</div><div class='ctx'> 	intel_init_quirks(i915);</div><div class='ctx'> </div><div class='ctx'> 	intel_fbc_init(i915);</div><div class='hunk'>@@ -430,9 +426,6 @@ void intel_display_driver_remove(struct drm_i915_private *i915)</div><div class='ctx'> 	flush_workqueue(i915-&gt;display.wq.flip);</div><div class='ctx'> 	flush_workqueue(i915-&gt;display.wq.modeset);</div><div class='ctx'> </div><div class='del'>-	flush_work(&amp;i915-&gt;display.atomic_helper.free_work);</div><div class='del'>-	drm_WARN_ON(&amp;i915-&gt;drm, !llist_empty(&amp;i915-&gt;display.atomic_helper.free_list));</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * MST topology needs to be suspended so we don't have any calls to</div><div class='ctx'> 	 * fbdev after it's finalized. MST will be destroyed later as part of</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c<br/>index bff4a76310c0..a7d8f3fc98de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_irq.c</a></div><div class='hunk'>@@ -340,18 +340,15 @@ static void flip_done_handler(struct drm_i915_private *i915,</div><div class='ctx'> 			      enum pipe pipe)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);</div><div class='del'>-	struct drm_crtc_state *crtc_state = crtc-&gt;base.state;</div><div class='del'>-	struct drm_pending_vblank_event *e = crtc_state-&gt;event;</div><div class='del'>-	struct drm_device *dev = &amp;i915-&gt;drm;</div><div class='del'>-	unsigned long irqflags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;dev-&gt;event_lock, irqflags);</div><div class='ctx'> </div><div class='del'>-	crtc_state-&gt;event = NULL;</div><div class='add'>+	spin_lock(&amp;i915-&gt;drm.event_lock);</div><div class='ctx'> </div><div class='del'>-	drm_crtc_send_vblank_event(&amp;crtc-&gt;base, e);</div><div class='add'>+	if (crtc-&gt;flip_done_event) {</div><div class='add'>+		drm_crtc_send_vblank_event(&amp;crtc-&gt;base, crtc-&gt;flip_done_event);</div><div class='add'>+		crtc-&gt;flip_done_event = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irqrestore(&amp;dev-&gt;event_lock, irqflags);</div><div class='add'>+	spin_unlock(&amp;i915-&gt;drm.event_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,</div><div class='hunk'>@@ -896,7 +893,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!found)</div><div class='del'>-		drm_err(&amp;dev_priv-&gt;drm, "Unexpected DE Misc interrupt\n");</div><div class='add'>+		drm_err(&amp;dev_priv-&gt;drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,</div><div class='hunk'>@@ -1653,7 +1650,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)</div><div class='ctx'> 	else if (HAS_PCH_SPLIT(dev_priv))</div><div class='ctx'> 		ibx_irq_postinstall(dev_priv);</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt;= 10)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 11)</div><div class='ctx'> 		de_misc_masked |= GEN8_DE_MISC_GSE;</div><div class='ctx'> </div><div class='ctx'> 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c<br/>index e390595d7341..6fd4fa52253a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_power.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_power.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_power.c</a></div><div class='hunk'>@@ -405,8 +405,8 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)</div><div class='ctx'> 						     struct drm_i915_private,</div><div class='ctx'> 						     display.power.domains);</div><div class='ctx'> </div><div class='del'>-	drm_dbg(&amp;i915-&gt;drm, "async_put_wakeref %u\n",</div><div class='del'>-		power_domains-&gt;async_put_wakeref);</div><div class='add'>+	drm_dbg(&amp;i915-&gt;drm, "async_put_wakeref: %s\n",</div><div class='add'>+		str_yes_no(power_domains-&gt;async_put_wakeref));</div><div class='ctx'> </div><div class='ctx'> 	print_power_domains(power_domains, "async_put_domains[0]",</div><div class='ctx'> 			    &amp;power_domains-&gt;async_put_domains[0]);</div><div class='hunk'>@@ -1697,14 +1697,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,</div><div class='ctx'> 	if (resume)</div><div class='ctx'> 		intel_dmc_load_program(dev_priv);</div><div class='ctx'> </div><div class='del'>-	/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt;= 12)</div><div class='add'>+	/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */</div><div class='add'>+	if (IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))</div><div class='ctx'> 		intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,</div><div class='ctx'> 			     DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |</div><div class='ctx'> 			     DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);</div><div class='ctx'> </div><div class='ctx'> 	/* Wa_14011503030:xelpd */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt;= 13)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) == 13)</div><div class='ctx'> 		intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h<br/>index b3e942f2eeb0..3fdd8a517983 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_display_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_display_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_display_types.h</a></div><div class='hunk'>@@ -684,8 +684,6 @@ struct intel_atomic_state {</div><div class='ctx'> 	bool skip_intermediate_wm;</div><div class='ctx'> </div><div class='ctx'> 	bool rps_interactive;</div><div class='del'>-</div><div class='del'>-	struct llist_node freed;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct intel_plane_state {</div><div class='hunk'>@@ -1022,7 +1020,6 @@ struct intel_c10pll_state {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct intel_c20pll_state {</div><div class='del'>-	u32 link_bit_rate;</div><div class='ctx'> 	u32 clock; /* in kHz */</div><div class='ctx'> 	u16 tx[3];</div><div class='ctx'> 	u16 cmn[4];</div><div class='hunk'>@@ -1476,6 +1473,9 @@ struct intel_crtc {</div><div class='ctx'> </div><div class='ctx'> 	struct intel_crtc_state *config;</div><div class='ctx'> </div><div class='add'>+	/* armed event for async flip */</div><div class='add'>+	struct drm_pending_vblank_event *flip_done_event;</div><div class='add'>+</div><div class='ctx'> 	/* Access to these should be protected by dev_priv-&gt;irq_lock. */</div><div class='ctx'> 	bool cpu_fifo_underrun_disabled;</div><div class='ctx'> 	bool pch_fifo_underrun_disabled;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c<br/>index 63e080e07023..b70502586ab9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dmc.c</a></div><div class='hunk'>@@ -335,77 +335,6 @@ static void disable_event_handler(struct drm_i915_private *i915,</div><div class='ctx'> 	intel_de_write(i915, htp_reg, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void</div><div class='del'>-disable_flip_queue_event(struct drm_i915_private *i915,</div><div class='del'>-			 i915_reg_t ctl_reg, i915_reg_t htp_reg)</div><div class='del'>-{</div><div class='del'>-	u32 event_ctl;</div><div class='del'>-	u32 event_htp;</div><div class='del'>-</div><div class='del'>-	event_ctl = intel_de_read(i915, ctl_reg);</div><div class='del'>-	event_htp = intel_de_read(i915, htp_reg);</div><div class='del'>-	if (event_ctl != (DMC_EVT_CTL_ENABLE |</div><div class='del'>-			  DMC_EVT_CTL_RECURRING |</div><div class='del'>-			  REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,</div><div class='del'>-					 DMC_EVT_CTL_TYPE_EDGE_0_1) |</div><div class='del'>-			  REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,</div><div class='del'>-					 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||</div><div class='del'>-	    !event_htp) {</div><div class='del'>-		drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='del'>-			    "Unexpected DMC event configuration (control %08x htp %08x)\n",</div><div class='del'>-			    event_ctl, event_htp);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	disable_event_handler(i915, ctl_reg, htp_reg);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool</div><div class='del'>-get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id,</div><div class='del'>-			  i915_reg_t *ctl_reg, i915_reg_t *htp_reg)</div><div class='del'>-{</div><div class='del'>-	if (dmc_id == DMC_FW_MAIN) {</div><div class='del'>-		if (DISPLAY_VER(i915) == 12) {</div><div class='del'>-			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);</div><div class='del'>-			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);</div><div class='del'>-</div><div class='del'>-			return true;</div><div class='del'>-		}</div><div class='del'>-	} else if (dmc_id &gt;= DMC_FW_PIPEA &amp;&amp; dmc_id &lt;= DMC_FW_PIPED) {</div><div class='del'>-		if (IS_DG2(i915)) {</div><div class='del'>-			*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);</div><div class='del'>-			*htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);</div><div class='del'>-</div><div class='del'>-			return true;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-disable_all_flip_queue_events(struct drm_i915_private *i915)</div><div class='del'>-{</div><div class='del'>-	enum intel_dmc_id dmc_id;</div><div class='del'>-</div><div class='del'>-	/* TODO: check if the following applies to all D13+ platforms. */</div><div class='del'>-	if (!IS_DG2(i915) &amp;&amp; !IS_TIGERLAKE(i915))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	for_each_dmc_id(dmc_id) {</div><div class='del'>-		i915_reg_t ctl_reg;</div><div class='del'>-		i915_reg_t htp_reg;</div><div class='del'>-</div><div class='del'>-		if (!has_dmc_id_fw(i915, dmc_id))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (!get_flip_queue_event_regs(i915, dmc_id, &amp;ctl_reg, &amp;htp_reg))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		disable_flip_queue_event(i915, ctl_reg, htp_reg);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void disable_all_event_handlers(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> 	enum intel_dmc_id dmc_id;</div><div class='hunk'>@@ -493,6 +422,65 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)</div><div class='ctx'> 		intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,</div><div class='add'>+			       enum intel_dmc_id dmc_id, i915_reg_t reg)</div><div class='add'>+{</div><div class='add'>+	u32 offset = i915_mmio_reg_offset(reg);</div><div class='add'>+	u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));</div><div class='add'>+	u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));</div><div class='add'>+</div><div class='add'>+	return offset &gt;= start &amp;&amp; offset &lt; end;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915,</div><div class='add'>+			       enum intel_dmc_id dmc_id, i915_reg_t reg)</div><div class='add'>+{</div><div class='add'>+	u32 offset = i915_mmio_reg_offset(reg);</div><div class='add'>+	u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0));</div><div class='add'>+	u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));</div><div class='add'>+</div><div class='add'>+	return offset &gt;= start &amp;&amp; offset &lt; end;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool disable_dmc_evt(struct drm_i915_private *i915,</div><div class='add'>+			    enum intel_dmc_id dmc_id,</div><div class='add'>+			    i915_reg_t reg, u32 data)</div><div class='add'>+{</div><div class='add'>+	if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* keep all pipe DMC events disabled by default */</div><div class='add'>+	if (dmc_id != DMC_FW_MAIN)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* also disable the flip queue event on the main DMC on TGL */</div><div class='add'>+	if (IS_TIGERLAKE(i915) &amp;&amp;</div><div class='add'>+	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* also disable the HRR event on the main DMC on TGL/ADLS */</div><div class='add'>+	if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) &amp;&amp;</div><div class='add'>+	    REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 dmc_mmiodata(struct drm_i915_private *i915,</div><div class='add'>+			struct intel_dmc *dmc,</div><div class='add'>+			enum intel_dmc_id dmc_id, int i)</div><div class='add'>+{</div><div class='add'>+	if (disable_dmc_evt(i915, dmc_id,</div><div class='add'>+			    dmc-&gt;dmc_info[dmc_id].mmioaddr[i],</div><div class='add'>+			    dmc-&gt;dmc_info[dmc_id].mmiodata[i]))</div><div class='add'>+		return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,</div><div class='add'>+				      DMC_EVT_CTL_TYPE_EDGE_0_1) |</div><div class='add'>+			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,</div><div class='add'>+				       DMC_EVT_CTL_EVENT_ID_FALSE);</div><div class='add'>+	else</div><div class='add'>+		return dmc-&gt;dmc_info[dmc_id].mmiodata[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * intel_dmc_load_program() - write the firmware from memory to register.</div><div class='ctx'>  * @i915: i915 drm device.</div><div class='hunk'>@@ -532,7 +520,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915)</div><div class='ctx'> 	for_each_dmc_id(dmc_id) {</div><div class='ctx'> 		for (i = 0; i &lt; dmc-&gt;dmc_info[dmc_id].mmio_count; i++) {</div><div class='ctx'> 			intel_de_write(i915, dmc-&gt;dmc_info[dmc_id].mmioaddr[i],</div><div class='del'>-				       dmc-&gt;dmc_info[dmc_id].mmiodata[i]);</div><div class='add'>+				       dmc_mmiodata(i915, dmc, dmc_id, i));</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -540,13 +528,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915)</div><div class='ctx'> </div><div class='ctx'> 	gen9_set_dc_state_debugmask(i915);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Flip queue events need to be disabled before enabling DC5/6.</div><div class='del'>-	 * i915 doesn't use the flip queue feature, so disable it already</div><div class='del'>-	 * here.</div><div class='del'>-	 */</div><div class='del'>-	disable_all_flip_queue_events(i915);</div><div class='del'>-</div><div class='ctx'> 	pipedmc_clock_gating_wa(i915, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -742,9 +723,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	drm_dbg_kms(&amp;i915-&gt;drm, "DMC %d:\n", dmc_id);</div><div class='ctx'> 	for (i = 0; i &lt; mmio_count; i++) {</div><div class='ctx'> 		dmc_info-&gt;mmioaddr[i] = _MMIO(mmioaddr[i]);</div><div class='ctx'> 		dmc_info-&gt;mmiodata[i] = mmiodata[i];</div><div class='add'>+</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",</div><div class='add'>+			    i, mmioaddr[i], mmiodata[i],</div><div class='add'>+			    is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info-&gt;mmioaddr[i]) ? " (EVT_CTL)" :</div><div class='add'>+			    is_dmc_evt_htp_reg(i915, dmc_id, dmc_info-&gt;mmioaddr[i]) ? " (EVT_HTP)" : "",</div><div class='add'>+			    disable_dmc_evt(i915, dmc_id, dmc_info-&gt;mmioaddr[i],</div><div class='add'>+					    dmc_info-&gt;mmiodata[i]) ? " (disabling)" : "");</div><div class='ctx'> 	}</div><div class='ctx'> 	dmc_info-&gt;mmio_count = mmio_count;</div><div class='ctx'> 	dmc_info-&gt;start_mmioaddr = start_mmioaddr;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h<br/>index cf10094acae3..90d0dbb41cfe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dmc_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dmc_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dmc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dmc_regs.h</a></div><div class='hunk'>@@ -60,6 +60,7 @@</div><div class='ctx'> </div><div class='ctx'> #define DMC_EVT_CTL_EVENT_ID_MASK	REG_GENMASK(15, 8)</div><div class='ctx'> #define DMC_EVT_CTL_EVENT_ID_FALSE	0x01</div><div class='add'>+#define DMC_EVT_CTL_EVENT_ID_VBLANK_A	0x32 /* main DMC */</div><div class='ctx'> /* An event handler scheduled to run at a 1 kHz frequency. */</div><div class='ctx'> #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c<br/>index 1422c2370269..f5ef95da5534 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp.c</a></div><div class='hunk'>@@ -1227,6 +1227,10 @@ intel_dp_mode_valid(struct drm_connector *_connector,</div><div class='ctx'> 	enum drm_mode_status status;</div><div class='ctx'> 	bool dsc = false, bigjoiner = false;</div><div class='ctx'> </div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLCLK)</div><div class='ctx'> 		return MODE_H_ILLEGAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1886,7 +1890,7 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)</div><div class='ctx'> 	 * Max Compressed bpp for Gen 13+ is 27bpp.</div><div class='ctx'> 	 * For earlier platform is 23bpp. (Bspec:49259).</div><div class='ctx'> 	 */</div><div class='del'>-	if (DISPLAY_VER(i915) &lt;= 12)</div><div class='add'>+	if (DISPLAY_VER(i915) &lt; 13)</div><div class='ctx'> 		return 23;</div><div class='ctx'> 	else</div><div class='ctx'> 		return 27;</div><div class='hunk'>@@ -2097,7 +2101,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);</div><div class='add'>+	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);</div><div class='ctx'> 	if (!dsc_max_bpc)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -2844,19 +2848,12 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder,</div><div class='ctx'> 			      struct intel_crtc_state *pipe_config,</div><div class='ctx'> 			      struct drm_connector_state *conn_state)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(encoder-&gt;base.dev);</div><div class='del'>-	struct drm_connector *connector = conn_state-&gt;connector;</div><div class='del'>-</div><div class='ctx'> 	pipe_config-&gt;has_audio =</div><div class='ctx'> 		intel_dp_has_audio(encoder, pipe_config, conn_state) &amp;&amp;</div><div class='ctx'> 		intel_audio_compute_config(encoder, pipe_config, conn_state);</div><div class='ctx'> </div><div class='ctx'> 	pipe_config-&gt;sdp_split_enable = pipe_config-&gt;has_audio &amp;&amp;</div><div class='ctx'> 					intel_dp_is_uhbr(pipe_config);</div><div class='del'>-</div><div class='del'>-	drm_dbg_kms(&amp;i915-&gt;drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",</div><div class='del'>-		    connector-&gt;base.id, connector-&gt;name,</div><div class='del'>-		    str_yes_no(pipe_config-&gt;sdp_split_enable));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int</div><div class='hunk'>@@ -4767,7 +4764,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,</div><div class='ctx'> 			  intel_dp-&gt;train_set, crtc_state-&gt;lane_count);</div><div class='ctx'> </div><div class='ctx'> 	drm_dp_set_phy_test_pattern(&amp;intel_dp-&gt;aux, data,</div><div class='del'>-				    link_status[DP_DPCD_REV]);</div><div class='add'>+				    intel_dp-&gt;dpcd[DP_DPCD_REV]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c<br/>index dbc1b66c8ee4..1abfafbbfa75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp_link_training.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dp_link_training.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp_link_training.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp_link_training.c</a></div><div class='hunk'>@@ -650,19 +650,30 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,</div><div class='ctx'> 			    const struct intel_crtc_state *crtc_state,</div><div class='ctx'> 			    u8 link_bw, u8 rate_select)</div><div class='ctx'> {</div><div class='del'>-	u8 link_config[2];</div><div class='add'>+	u8 lane_count = crtc_state-&gt;lane_count;</div><div class='ctx'> </div><div class='del'>-	/* Write the link configuration data */</div><div class='del'>-	link_config[0] = link_bw;</div><div class='del'>-	link_config[1] = crtc_state-&gt;lane_count;</div><div class='ctx'> 	if (crtc_state-&gt;enhanced_framing)</div><div class='del'>-		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;</div><div class='del'>-	drm_dp_dpcd_write(&amp;intel_dp-&gt;aux, DP_LINK_BW_SET, link_config, 2);</div><div class='add'>+		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;</div><div class='add'>+</div><div class='add'>+	if (link_bw) {</div><div class='add'>+		/* DP and eDP v1.3 and earlier link bw set method. */</div><div class='add'>+		u8 link_config[] = { link_bw, lane_count };</div><div class='ctx'> </div><div class='del'>-	/* eDP 1.4 rate select method. */</div><div class='del'>-	if (!link_bw)</div><div class='del'>-		drm_dp_dpcd_write(&amp;intel_dp-&gt;aux, DP_LINK_RATE_SET,</div><div class='del'>-				  &amp;rate_select, 1);</div><div class='add'>+		drm_dp_dpcd_write(&amp;intel_dp-&gt;aux, DP_LINK_BW_SET, link_config,</div><div class='add'>+				  ARRAY_SIZE(link_config));</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * eDP v1.4 and later link rate set method.</div><div class='add'>+		 *</div><div class='add'>+		 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if</div><div class='add'>+		 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET.</div><div class='add'>+		 *</div><div class='add'>+		 * eDP v1.5 sinks allow choosing either, and the last choice</div><div class='add'>+		 * shall be active.</div><div class='add'>+		 */</div><div class='add'>+		drm_dp_dpcd_writeb(&amp;intel_dp-&gt;aux, DP_LANE_COUNT_SET, lane_count);</div><div class='add'>+		drm_dp_dpcd_writeb(&amp;intel_dp-&gt;aux, DP_LINK_RATE_SET, rate_select);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c<br/>index 63364c9602ef..8a9432335030 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp_mst.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dp_mst.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dp_mst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dp_mst.c</a></div><div class='hunk'>@@ -54,7 +54,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp</div><div class='ctx'> 					  struct intel_crtc_state *crtc_state,</div><div class='ctx'> 					  bool dsc)</div><div class='ctx'> {</div><div class='del'>-	if (intel_dp_is_uhbr(crtc_state) &amp;&amp; DISPLAY_VER(i915) &lt;= 13 &amp;&amp; dsc) {</div><div class='add'>+	if (intel_dp_is_uhbr(crtc_state) &amp;&amp; DISPLAY_VER(i915) &lt; 14 &amp;&amp; dsc) {</div><div class='ctx'> 		int output_bpp = bpp;</div><div class='ctx'> 		/* DisplayPort 2 128b/132b, bits per lane is always 32 */</div><div class='ctx'> 		int symbol_clock = crtc_state-&gt;port_clock / 32;</div><div class='hunk'>@@ -614,7 +614,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);</div><div class='ctx'> </div><div class='del'>-	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);</div><div class='add'>+	intel_ddi_compute_min_voltage_level(pipe_config);</div><div class='ctx'> </div><div class='ctx'> 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);</div><div class='ctx'> </div><div class='hunk'>@@ -1282,6 +1282,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	*status = intel_cpu_transcoder_mode_valid(dev_priv, mode);</div><div class='add'>+	if (*status != MODE_OK)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN) {</div><div class='ctx'> 		*status = MODE_NO_DBLESCAN;</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1328,6 +1332,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,</div><div class='ctx'> 	if (intel_dp_need_bigjoiner(intel_dp, mode-&gt;hdisplay, target_clock)) {</div><div class='ctx'> 		bigjoiner = true;</div><div class='ctx'> 		max_dotclk *= 2;</div><div class='add'>+</div><div class='add'>+		/* TODO: add support for bigjoiner */</div><div class='add'>+		*status = MODE_CLOCK_HIGH;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (DISPLAY_VER(dev_priv) &gt;= 10 &amp;&amp;</div><div class='hunk'>@@ -1362,11 +1370,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,</div><div class='ctx'> 	 * Big joiner configuration needs DSC for TGL which is not true for</div><div class='ctx'> 	 * XE_LPD where uncompressed joiner is supported.</div><div class='ctx'> 	 */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt; 13 &amp;&amp; bigjoiner &amp;&amp; !dsc)</div><div class='del'>-		return MODE_CLOCK_HIGH;</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 13 &amp;&amp; bigjoiner &amp;&amp; !dsc) {</div><div class='add'>+		*status = MODE_CLOCK_HIGH;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (mode_rate &gt; max_rate &amp;&amp; !dsc)</div><div class='del'>-		return MODE_CLOCK_HIGH;</div><div class='add'>+	if (mode_rate &gt; max_rate &amp;&amp; !dsc) {</div><div class='add'>+		*status = MODE_CLOCK_HIGH;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	*status = intel_mode_valid_max_plane_size(dev_priv, mode, false);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c<br/>index 7958d0bd851e..ef57dad1a9cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dpll_mgr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dpll_mgr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dpll_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dpll_mgr.c</a></div><div class='hunk'>@@ -4537,7 +4537,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,</div><div class='ctx'> 				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",</div><div class='ctx'> 				pipe_name(crtc-&gt;pipe), pll-&gt;active_mask);</div><div class='ctx'> 		I915_STATE_WARN(i915, pll-&gt;state.pipe_mask &amp; pipe_mask,</div><div class='del'>-				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",</div><div class='add'>+				"pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",</div><div class='ctx'> 				pipe_name(crtc-&gt;pipe), pll-&gt;state.pipe_mask);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c<br/>index 9598d50f68f2..482c28b5c2de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dsb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsb.c</a></div><div class='hunk'>@@ -341,7 +341,7 @@ static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,</div><div class='del'>-			      unsigned int dewake_scanline)</div><div class='add'>+			      int dewake_scanline)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_crtc *crtc = dsb-&gt;crtc;</div><div class='ctx'> 	struct drm_i915_private *dev_priv = to_i915(crtc-&gt;base.dev);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c<br/>index 275d0218394c..a5d7fc8418c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsi_vbt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dsi_vbt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsi_vbt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsi_vbt.c</a></div><div class='hunk'>@@ -922,7 +922,7 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)</div><div class='ctx'> 		gpiod_add_lookup_table(gpiod_lookup_table);</div><div class='ctx'> </div><div class='ctx'> 	if (want_panel_gpio) {</div><div class='del'>-		intel_dsi-&gt;gpio_panel = gpiod_get(dev-&gt;dev, "panel", flags);</div><div class='add'>+		intel_dsi-&gt;gpio_panel = devm_gpiod_get(dev-&gt;dev, "panel", flags);</div><div class='ctx'> 		if (IS_ERR(intel_dsi-&gt;gpio_panel)) {</div><div class='ctx'> 			drm_err(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 				"Failed to own gpio for panel control\n");</div><div class='hunk'>@@ -932,7 +932,7 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)</div><div class='ctx'> </div><div class='ctx'> 	if (want_backlight_gpio) {</div><div class='ctx'> 		intel_dsi-&gt;gpio_backlight =</div><div class='del'>-			gpiod_get(dev-&gt;dev, "backlight", flags);</div><div class='add'>+			devm_gpiod_get(dev-&gt;dev, "backlight", flags);</div><div class='ctx'> 		if (IS_ERR(intel_dsi-&gt;gpio_backlight)) {</div><div class='ctx'> 			drm_err(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 				"Failed to own gpio for backlight control\n");</div><div class='hunk'>@@ -943,16 +943,3 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)</div><div class='ctx'> 	if (gpiod_lookup_table)</div><div class='ctx'> 		gpiod_remove_lookup_table(gpiod_lookup_table);</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)</div><div class='del'>-{</div><div class='del'>-	if (intel_dsi-&gt;gpio_panel) {</div><div class='del'>-		gpiod_put(intel_dsi-&gt;gpio_panel);</div><div class='del'>-		intel_dsi-&gt;gpio_panel = NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (intel_dsi-&gt;gpio_backlight) {</div><div class='del'>-		gpiod_put(intel_dsi-&gt;gpio_backlight);</div><div class='del'>-		intel_dsi-&gt;gpio_backlight = NULL;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.h b/drivers/gpu/drm/i915/display/intel_dsi_vbt.h<br/>index 468d873fab1a..3462fcc760e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsi_vbt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dsi_vbt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dsi_vbt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dsi_vbt.h</a></div><div class='hunk'>@@ -13,7 +13,6 @@ struct intel_dsi;</div><div class='ctx'> </div><div class='ctx'> bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);</div><div class='ctx'> void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);</div><div class='del'>-void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi);</div><div class='ctx'> void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,</div><div class='ctx'> 				 enum mipi_seq seq_id);</div><div class='ctx'> void intel_dsi_log_params(struct intel_dsi *intel_dsi);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c<br/>index 55d6743374bd..9111e9d46486 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dvo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_dvo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_dvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_dvo.c</a></div><div class='hunk'>@@ -217,11 +217,17 @@ intel_dvo_mode_valid(struct drm_connector *_connector,</div><div class='ctx'> 		     struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_connector *connector = to_intel_connector(_connector);</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);</div><div class='ctx'> 	const struct drm_display_mode *fixed_mode =</div><div class='ctx'> 		intel_panel_fixed_mode(connector, mode);</div><div class='ctx'> 	int max_dotclk = to_i915(connector-&gt;base.dev)-&gt;max_dotclk_freq;</div><div class='ctx'> 	int target_clock = mode-&gt;clock;</div><div class='add'>+	enum drm_mode_status status;</div><div class='add'>+</div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='ctx'> </div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN)</div><div class='ctx'> 		return MODE_NO_DBLESCAN;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c<br/>index 6d48aa3af95a..0c0144eaa8fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_fb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb.c</a></div><div class='hunk'>@@ -4,7 +4,6 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_blend.h&gt;</div><div class='del'>-#include &lt;drm/drm_framebuffer.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-fence.h&gt;</div><div class='hunk'>@@ -15,6 +14,7 @@</div><div class='ctx'> #include "intel_display_types.h"</div><div class='ctx'> #include "intel_dpt.h"</div><div class='ctx'> #include "intel_fb.h"</div><div class='add'>+#include "intel_fb_bo.h"</div><div class='ctx'> #include "intel_frontbuffer.h"</div><div class='ctx'> </div><div class='ctx'> #define check_array_bounds(i915, a, i) drm_WARN_ON(&amp;(i915)-&gt;drm, (i) &gt;= ARRAY_SIZE(a))</div><div class='hunk'>@@ -301,6 +301,33 @@ lookup_format_info(const struct drm_format_info formats[],</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)</div><div class='add'>+{</div><div class='add'>+	const struct intel_modifier_desc *md;</div><div class='add'>+	u8 tiling_caps;</div><div class='add'>+</div><div class='add'>+	md = lookup_modifier_or_null(fb_modifier);</div><div class='add'>+	if (!md)</div><div class='add'>+		return I915_TILING_NONE;</div><div class='add'>+</div><div class='add'>+	tiling_caps = lookup_modifier_or_null(fb_modifier)-&gt;plane_caps &amp;</div><div class='add'>+			 INTEL_PLANE_CAP_TILING_MASK;</div><div class='add'>+</div><div class='add'>+	switch (tiling_caps) {</div><div class='add'>+	case INTEL_PLANE_CAP_TILING_Y:</div><div class='add'>+		return I915_TILING_Y;</div><div class='add'>+	case INTEL_PLANE_CAP_TILING_X:</div><div class='add'>+		return I915_TILING_X;</div><div class='add'>+	case INTEL_PLANE_CAP_TILING_4:</div><div class='add'>+	case INTEL_PLANE_CAP_TILING_Yf:</div><div class='add'>+	case INTEL_PLANE_CAP_TILING_NONE:</div><div class='add'>+		return I915_TILING_NONE;</div><div class='add'>+	default:</div><div class='add'>+		MISSING_CASE(tiling_caps);</div><div class='add'>+		return I915_TILING_NONE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * intel_fb_get_format_info: Get a modifier specific format information</div><div class='ctx'>  * @cmd: FB add command structure</div><div class='hunk'>@@ -737,26 +764,6 @@ intel_fb_align_height(const struct drm_framebuffer *fb,</div><div class='ctx'> 	return ALIGN(height, tile_height);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)</div><div class='del'>-{</div><div class='del'>-	u8 tiling_caps = lookup_modifier(fb_modifier)-&gt;plane_caps &amp;</div><div class='del'>-			 INTEL_PLANE_CAP_TILING_MASK;</div><div class='del'>-</div><div class='del'>-	switch (tiling_caps) {</div><div class='del'>-	case INTEL_PLANE_CAP_TILING_Y:</div><div class='del'>-		return I915_TILING_Y;</div><div class='del'>-	case INTEL_PLANE_CAP_TILING_X:</div><div class='del'>-		return I915_TILING_X;</div><div class='del'>-	case INTEL_PLANE_CAP_TILING_4:</div><div class='del'>-	case INTEL_PLANE_CAP_TILING_Yf:</div><div class='del'>-	case INTEL_PLANE_CAP_TILING_NONE:</div><div class='del'>-		return I915_TILING_NONE;</div><div class='del'>-	default:</div><div class='del'>-		MISSING_CASE(tiling_caps);</div><div class='del'>-		return I915_TILING_NONE;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)</div><div class='ctx'> {</div><div class='ctx'> 	return HAS_DPT(i915) &amp;&amp; modifier != DRM_FORMAT_MOD_LINEAR;</div><div class='hunk'>@@ -764,7 +771,7 @@ bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)</div><div class='ctx'> </div><div class='ctx'> bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)</div><div class='ctx'> {</div><div class='del'>-	return fb &amp;&amp; to_i915(fb-&gt;dev)-&gt;display.params.enable_dpt &amp;&amp;</div><div class='add'>+	return to_i915(fb-&gt;dev)-&gt;display.params.enable_dpt &amp;&amp;</div><div class='ctx'> 		intel_fb_modifier_uses_dpt(to_i915(fb-&gt;dev), fb-&gt;modifier);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1374,7 +1381,8 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(fb-&gt;base.dev);</div><div class='ctx'> 	unsigned int stride_tiles;</div><div class='ctx'> </div><div class='del'>-	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) &gt;= 14)</div><div class='add'>+	if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) &gt;= 14) &amp;&amp;</div><div class='add'>+	    src_stride_tiles &lt; dst_stride_tiles)</div><div class='ctx'> 		stride_tiles = src_stride_tiles;</div><div class='ctx'> 	else</div><div class='ctx'> 		stride_tiles = dst_stride_tiles;</div><div class='hunk'>@@ -1501,8 +1509,20 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p</div><div class='ctx'> </div><div class='ctx'> 			size += remap_info-&gt;size;</div><div class='ctx'> 		} else {</div><div class='del'>-			unsigned int dst_stride = plane_view_dst_stride_tiles(fb, color_plane,</div><div class='del'>-									      remap_info-&gt;width);</div><div class='add'>+			unsigned int dst_stride;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * The hardware automagically calculates the CCS AUX surface</div><div class='add'>+			 * stride from the main surface stride so can't really remap a</div><div class='add'>+			 * smaller subset (unless we'd remap in whole AUX page units).</div><div class='add'>+			 */</div><div class='add'>+			if (intel_fb_needs_pot_stride_remap(fb) &amp;&amp;</div><div class='add'>+			    intel_fb_is_ccs_modifier(fb-&gt;base.modifier))</div><div class='add'>+				dst_stride = remap_info-&gt;src_stride;</div><div class='add'>+			else</div><div class='add'>+				dst_stride = remap_info-&gt;width;</div><div class='add'>+</div><div class='add'>+			dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride);</div><div class='ctx'> </div><div class='ctx'> 			assign_chk_ovf(i915, remap_info-&gt;dst_stride, dst_stride);</div><div class='ctx'> 			color_plane_info-&gt;mapping_stride = dst_stride *</div><div class='hunk'>@@ -1657,10 +1677,10 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *</div><div class='ctx'> 		max_size = max(max_size, offset + size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (mul_u32_u32(max_size, tile_size) &gt; obj-&gt;base.size) {</div><div class='add'>+	if (mul_u32_u32(max_size, tile_size) &gt; intel_bo_to_drm_bo(obj)-&gt;size) {</div><div class='ctx'> 		drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='ctx'> 			    "fb too big for bo (need %llu bytes, have %zu bytes)\n",</div><div class='del'>-			    mul_u32_u32(max_size, tile_size), obj-&gt;base.size);</div><div class='add'>+			    mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)-&gt;size);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1881,6 +1901,8 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)</div><div class='ctx'> </div><div class='ctx'> 	intel_frontbuffer_put(intel_fb-&gt;frontbuffer);</div><div class='ctx'> </div><div class='add'>+	intel_fb_bo_framebuffer_fini(intel_fb_obj(fb));</div><div class='add'>+</div><div class='ctx'> 	kfree(intel_fb);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1889,7 +1911,7 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,</div><div class='ctx'> 						unsigned int *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(obj-&gt;base.dev);</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(intel_bo_to_drm_bo(obj)-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (i915_gem_object_is_userptr(obj)) {</div><div class='ctx'> 		drm_dbg(&amp;i915-&gt;drm,</div><div class='hunk'>@@ -1897,7 +1919,7 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return drm_gem_handle_create(file, &amp;obj-&gt;base, handle);</div><div class='add'>+	return drm_gem_handle_create(file, intel_bo_to_drm_bo(obj), handle);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct frontbuffer_fence_cb {</div><div class='hunk'>@@ -1975,61 +1997,30 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 			   struct drm_i915_gem_object *obj,</div><div class='ctx'> 			   struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *dev_priv = to_i915(obj-&gt;base.dev);</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(intel_bo_to_drm_bo(obj)-&gt;dev);</div><div class='ctx'> 	struct drm_framebuffer *fb = &amp;intel_fb-&gt;base;</div><div class='ctx'> 	u32 max_stride;</div><div class='del'>-	unsigned int tiling, stride;</div><div class='ctx'> 	int ret = -EINVAL;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	intel_fb-&gt;frontbuffer = intel_frontbuffer_get(obj);</div><div class='del'>-	if (!intel_fb-&gt;frontbuffer)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	i915_gem_object_lock(obj, NULL);</div><div class='del'>-	tiling = i915_gem_object_get_tiling(obj);</div><div class='del'>-	stride = i915_gem_object_get_stride(obj);</div><div class='del'>-	i915_gem_object_unlock(obj);</div><div class='add'>+	ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-	if (mode_cmd-&gt;flags &amp; DRM_MODE_FB_MODIFIERS) {</div><div class='del'>-		/*</div><div class='del'>-		 * If there's a fence, enforce that</div><div class='del'>-		 * the fb modifier and tiling mode match.</div><div class='del'>-		 */</div><div class='del'>-		if (tiling != I915_TILING_NONE &amp;&amp;</div><div class='del'>-		    tiling != intel_fb_modifier_to_tiling(mode_cmd-&gt;modifier[0])) {</div><div class='del'>-			drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='del'>-				    "tiling_mode doesn't match fb modifier\n");</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		if (tiling == I915_TILING_X) {</div><div class='del'>-			mode_cmd-&gt;modifier[0] = I915_FORMAT_MOD_X_TILED;</div><div class='del'>-		} else if (tiling == I915_TILING_Y) {</div><div class='del'>-			drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='del'>-				    "No Y tiling for legacy addfb\n");</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='add'>+	intel_fb-&gt;frontbuffer = intel_frontbuffer_get(obj);</div><div class='add'>+	if (!intel_fb-&gt;frontbuffer) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = -EINVAL;</div><div class='ctx'> 	if (!drm_any_plane_has_format(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 				      mode_cmd-&gt;pixel_format,</div><div class='ctx'> 				      mode_cmd-&gt;modifier[0])) {</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",</div><div class='ctx'> 			    &amp;mode_cmd-&gt;pixel_format, mode_cmd-&gt;modifier[0]);</div><div class='del'>-		goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * gen2/3 display engine uses the fence if present,</div><div class='del'>-	 * so the tiling mode must match the fb modifier exactly.</div><div class='del'>-	 */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt; 4 &amp;&amp;</div><div class='del'>-	    tiling != intel_fb_modifier_to_tiling(mode_cmd-&gt;modifier[0])) {</div><div class='del'>-		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='del'>-			    "tiling_mode must match fb modifier exactly on gen2/3\n");</div><div class='del'>-		goto err;</div><div class='add'>+		goto err_frontbuffer_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	max_stride = intel_fb_max_stride(dev_priv, mode_cmd-&gt;pixel_format,</div><div class='hunk'>@@ -2040,18 +2031,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 			    mode_cmd-&gt;modifier[0] != DRM_FORMAT_MOD_LINEAR ?</div><div class='ctx'> 			    "tiled" : "linear",</div><div class='ctx'> 			    mode_cmd-&gt;pitches[0], max_stride);</div><div class='del'>-		goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * If there's a fence, enforce that</div><div class='del'>-	 * the fb pitch and fence stride match.</div><div class='del'>-	 */</div><div class='del'>-	if (tiling != I915_TILING_NONE &amp;&amp; mode_cmd-&gt;pitches[0] != stride) {</div><div class='del'>-		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='del'>-			    "pitch (%d) must match tiling stride (%d)\n",</div><div class='del'>-			    mode_cmd-&gt;pitches[0], stride);</div><div class='del'>-		goto err;</div><div class='add'>+		goto err_frontbuffer_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */</div><div class='hunk'>@@ -2059,7 +2039,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			    "plane 0 offset (0x%08x) must be 0\n",</div><div class='ctx'> 			    mode_cmd-&gt;offsets[0]);</div><div class='del'>-		goto err;</div><div class='add'>+		goto err_frontbuffer_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	drm_helper_mode_fill_fb_struct(&amp;dev_priv-&gt;drm, fb, mode_cmd);</div><div class='hunk'>@@ -2070,7 +2050,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 		if (mode_cmd-&gt;handles[i] != mode_cmd-&gt;handles[0]) {</div><div class='ctx'> 			drm_dbg_kms(&amp;dev_priv-&gt;drm, "bad plane %d handle\n",</div><div class='ctx'> 				    i);</div><div class='del'>-			goto err;</div><div class='add'>+			goto err_frontbuffer_put;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		stride_alignment = intel_fb_stride_alignment(fb, i);</div><div class='hunk'>@@ -2078,7 +2058,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 			drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 				    "plane %d pitch (%d) must be at least %u byte aligned\n",</div><div class='ctx'> 				    i, fb-&gt;pitches[i], stride_alignment);</div><div class='del'>-			goto err;</div><div class='add'>+			goto err_frontbuffer_put;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {</div><div class='hunk'>@@ -2089,7 +2069,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 					    "ccs aux plane %d pitch (%d) must be %d\n",</div><div class='ctx'> 					    i,</div><div class='ctx'> 					    fb-&gt;pitches[i], ccs_aux_stride);</div><div class='del'>-				goto err;</div><div class='add'>+				goto err_frontbuffer_put;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -2098,7 +2078,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> </div><div class='ctx'> 	ret = intel_fill_fb_info(dev_priv, intel_fb);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto err;</div><div class='add'>+		goto err_frontbuffer_put;</div><div class='ctx'> </div><div class='ctx'> 	if (intel_fb_uses_dpt(fb)) {</div><div class='ctx'> 		struct i915_address_space *vm;</div><div class='hunk'>@@ -2107,7 +2087,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> 		if (IS_ERR(vm)) {</div><div class='ctx'> 			drm_dbg_kms(&amp;dev_priv-&gt;drm, "failed to create DPT\n");</div><div class='ctx'> 			ret = PTR_ERR(vm);</div><div class='del'>-			goto err;</div><div class='add'>+			goto err_frontbuffer_put;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		intel_fb-&gt;dpt_vm = vm;</div><div class='hunk'>@@ -2124,8 +2104,10 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='ctx'> err_free_dpt:</div><div class='ctx'> 	if (intel_fb_uses_dpt(fb))</div><div class='ctx'> 		intel_dpt_destroy(intel_fb-&gt;dpt_vm);</div><div class='del'>-err:</div><div class='add'>+err_frontbuffer_put:</div><div class='ctx'> 	intel_frontbuffer_put(intel_fb-&gt;frontbuffer);</div><div class='add'>+err:</div><div class='add'>+	intel_fb_bo_framebuffer_fini(obj);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2137,23 +2119,14 @@ intel_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> 	struct drm_framebuffer *fb;</div><div class='ctx'> 	struct drm_i915_gem_object *obj;</div><div class='ctx'> 	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;</div><div class='del'>-	struct drm_i915_private *i915;</div><div class='del'>-</div><div class='del'>-	obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);</div><div class='del'>-	if (!obj)</div><div class='del'>-		return ERR_PTR(-ENOENT);</div><div class='del'>-</div><div class='del'>-	/* object is backed with LMEM for discrete */</div><div class='del'>-	i915 = to_i915(obj-&gt;base.dev);</div><div class='del'>-	if (HAS_LMEM(i915) &amp;&amp; !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {</div><div class='del'>-		/* object is "remote", not in local memory */</div><div class='del'>-		i915_gem_object_put(obj);</div><div class='del'>-		drm_dbg_kms(&amp;i915-&gt;drm, "framebuffer must reside in local memory\n");</div><div class='del'>-		return ERR_PTR(-EREMOTE);</div><div class='del'>-	}</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(dev);</div><div class='add'>+</div><div class='add'>+	obj = intel_fb_bo_lookup_valid_bo(i915, filp, &amp;mode_cmd);</div><div class='add'>+	if (IS_ERR(obj))</div><div class='add'>+		return ERR_CAST(obj);</div><div class='ctx'> </div><div class='ctx'> 	fb = intel_framebuffer_create(obj, &amp;mode_cmd);</div><div class='del'>-	i915_gem_object_put(obj);</div><div class='add'>+	drm_gem_object_put(intel_bo_to_drm_bo(obj));</div><div class='ctx'> </div><div class='ctx'> 	return fb;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h<br/>index e85167d6bc34..23db6628f53e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_fb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb.h</a></div><div class='hunk'>@@ -95,4 +95,6 @@ intel_user_framebuffer_create(struct drm_device *dev,</div><div class='ctx'> bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier);</div><div class='ctx'> bool intel_fb_uses_dpt(const struct drm_framebuffer *fb);</div><div class='ctx'> </div><div class='add'>+unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier);</div><div class='add'>+</div><div class='ctx'> #endif /* __INTEL_FB_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.c b/drivers/gpu/drm/i915/display/intel_fb_bo.c<br/>new file mode 100644<br/>index 000000000000..4be09541e509<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb_bo.c</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_framebuffer.h&gt;</div><div class='add'>+</div><div class='add'>+#include "gem/i915_gem_object.h"</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_fb.h"</div><div class='add'>+#include "intel_fb_bo.h"</div><div class='add'>+</div><div class='add'>+void intel_fb_bo_framebuffer_fini(struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	/* Nothing to do for i915 */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='add'>+				 struct drm_i915_gem_object *obj,</div><div class='add'>+				 struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(obj-&gt;base.dev);</div><div class='add'>+	unsigned int tiling, stride;</div><div class='add'>+</div><div class='add'>+	i915_gem_object_lock(obj, NULL);</div><div class='add'>+	tiling = i915_gem_object_get_tiling(obj);</div><div class='add'>+	stride = i915_gem_object_get_stride(obj);</div><div class='add'>+	i915_gem_object_unlock(obj);</div><div class='add'>+</div><div class='add'>+	if (mode_cmd-&gt;flags &amp; DRM_MODE_FB_MODIFIERS) {</div><div class='add'>+		/*</div><div class='add'>+		 * If there's a fence, enforce that</div><div class='add'>+		 * the fb modifier and tiling mode match.</div><div class='add'>+		 */</div><div class='add'>+		if (tiling != I915_TILING_NONE &amp;&amp;</div><div class='add'>+		    tiling != intel_fb_modifier_to_tiling(mode_cmd-&gt;modifier[0])) {</div><div class='add'>+			drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='add'>+				    "tiling_mode doesn't match fb modifier\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (tiling == I915_TILING_X) {</div><div class='add'>+			mode_cmd-&gt;modifier[0] = I915_FORMAT_MOD_X_TILED;</div><div class='add'>+		} else if (tiling == I915_TILING_Y) {</div><div class='add'>+			drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='add'>+				    "No Y tiling for legacy addfb\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * gen2/3 display engine uses the fence if present,</div><div class='add'>+	 * so the tiling mode must match the fb modifier exactly.</div><div class='add'>+	 */</div><div class='add'>+	if (DISPLAY_VER(i915) &lt; 4 &amp;&amp;</div><div class='add'>+	    tiling != intel_fb_modifier_to_tiling(mode_cmd-&gt;modifier[0])) {</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='add'>+			    "tiling_mode must match fb modifier exactly on gen2/3\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If there's a fence, enforce that</div><div class='add'>+	 * the fb pitch and fence stride match.</div><div class='add'>+	 */</div><div class='add'>+	if (tiling != I915_TILING_NONE &amp;&amp; mode_cmd-&gt;pitches[0] != stride) {</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='add'>+			    "pitch (%d) must match tiling stride (%d)\n",</div><div class='add'>+			    mode_cmd-&gt;pitches[0], stride);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct drm_i915_gem_object *</div><div class='add'>+intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,</div><div class='add'>+			    struct drm_file *filp,</div><div class='add'>+			    const struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+</div><div class='add'>+	obj = i915_gem_object_lookup(filp, mode_cmd-&gt;handles[0]);</div><div class='add'>+	if (!obj)</div><div class='add'>+		return ERR_PTR(-ENOENT);</div><div class='add'>+</div><div class='add'>+	/* object is backed with LMEM for discrete */</div><div class='add'>+	if (HAS_LMEM(i915) &amp;&amp; !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {</div><div class='add'>+		/* object is "remote", not in local memory */</div><div class='add'>+		i915_gem_object_put(obj);</div><div class='add'>+		drm_dbg_kms(&amp;i915-&gt;drm, "framebuffer must reside in local memory\n");</div><div class='add'>+		return ERR_PTR(-EREMOTE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return obj;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.h b/drivers/gpu/drm/i915/display/intel_fb_bo.h<br/>new file mode 100644<br/>index 000000000000..232bf898b013<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fb_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fb_bo.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_FB_BO_H__</div><div class='add'>+#define __INTEL_FB_BO_H__</div><div class='add'>+</div><div class='add'>+struct drm_file;</div><div class='add'>+struct drm_mode_fb_cmd2;</div><div class='add'>+struct drm_i915_gem_object;</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+struct intel_framebuffer;</div><div class='add'>+</div><div class='add'>+void intel_fb_bo_framebuffer_fini(struct drm_i915_gem_object *obj);</div><div class='add'>+</div><div class='add'>+int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='add'>+				 struct drm_i915_gem_object *obj,</div><div class='add'>+				 struct drm_mode_fb_cmd2 *mode_cmd);</div><div class='add'>+</div><div class='add'>+struct drm_i915_gem_object *</div><div class='add'>+intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,</div><div class='add'>+			    struct drm_file *filp,</div><div class='add'>+			    const struct drm_mode_fb_cmd2 *user_mode_cmd);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c<br/>index 63f389a1707d..f17a1afb4929 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_fbc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbc.c</a></div><div class='hunk'>@@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,</div><div class='ctx'> 	 * Recommendation is to keep this combination disabled</div><div class='ctx'> 	 * Bspec: 50422 HSD: 14010260002</div><div class='ctx'> 	 */</div><div class='del'>-	if (DISPLAY_VER(i915) &gt;= 12 &amp;&amp; crtc_state-&gt;has_psr2) {</div><div class='add'>+	if (IS_DISPLAY_VER(i915, 12, 14) &amp;&amp; crtc_state-&gt;has_psr2) {</div><div class='ctx'> 		plane_state-&gt;no_fbc_reason = "PSR2 enabled";</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c<br/>index 31d0d695d567..99894a855ef0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_fbdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev.c</a></div><div class='hunk'>@@ -43,7 +43,6 @@</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_gem_framebuffer_helper.h&gt;</div><div class='ctx'> </div><div class='del'>-#include "gem/i915_gem_lmem.h"</div><div class='ctx'> #include "gem/i915_gem_mman.h"</div><div class='ctx'> </div><div class='ctx'> #include "i915_drv.h"</div><div class='hunk'>@@ -51,6 +50,7 @@</div><div class='ctx'> #include "intel_fb.h"</div><div class='ctx'> #include "intel_fb_pin.h"</div><div class='ctx'> #include "intel_fbdev.h"</div><div class='add'>+#include "intel_fbdev_fb.h"</div><div class='ctx'> #include "intel_frontbuffer.h"</div><div class='ctx'> </div><div class='ctx'> struct intel_fbdev {</div><div class='hunk'>@@ -146,65 +146,6 @@ static const struct fb_ops intelfb_ops = {</div><div class='ctx'> 	.fb_mmap = intel_fbdev_mmap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int intelfb_alloc(struct drm_fb_helper *helper,</div><div class='del'>-			 struct drm_fb_helper_surface_size *sizes)</div><div class='del'>-{</div><div class='del'>-	struct intel_fbdev *ifbdev = to_intel_fbdev(helper);</div><div class='del'>-	struct drm_framebuffer *fb;</div><div class='del'>-	struct drm_device *dev = helper-&gt;dev;</div><div class='del'>-	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='del'>-	struct drm_mode_fb_cmd2 mode_cmd = {};</div><div class='del'>-	struct drm_i915_gem_object *obj;</div><div class='del'>-	int size;</div><div class='del'>-</div><div class='del'>-	/* we don't do packed 24bpp */</div><div class='del'>-	if (sizes-&gt;surface_bpp == 24)</div><div class='del'>-		sizes-&gt;surface_bpp = 32;</div><div class='del'>-</div><div class='del'>-	mode_cmd.width = sizes-&gt;surface_width;</div><div class='del'>-	mode_cmd.height = sizes-&gt;surface_height;</div><div class='del'>-</div><div class='del'>-	mode_cmd.pitches[0] = ALIGN(mode_cmd.width *</div><div class='del'>-				    DIV_ROUND_UP(sizes-&gt;surface_bpp, 8), 64);</div><div class='del'>-	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes-&gt;surface_bpp,</div><div class='del'>-							  sizes-&gt;surface_depth);</div><div class='del'>-</div><div class='del'>-	size = mode_cmd.pitches[0] * mode_cmd.height;</div><div class='del'>-	size = PAGE_ALIGN(size);</div><div class='del'>-</div><div class='del'>-	obj = ERR_PTR(-ENODEV);</div><div class='del'>-	if (HAS_LMEM(dev_priv)) {</div><div class='del'>-		obj = i915_gem_object_create_lmem(dev_priv, size,</div><div class='del'>-						  I915_BO_ALLOC_CONTIGUOUS |</div><div class='del'>-						  I915_BO_ALLOC_USER);</div><div class='del'>-	} else {</div><div class='del'>-		/*</div><div class='del'>-		 * If the FB is too big, just don't use it since fbdev is not very</div><div class='del'>-		 * important and we should probably use that space with FBC or other</div><div class='del'>-		 * features.</div><div class='del'>-		 *</div><div class='del'>-		 * Also skip stolen on MTL as Wa_22018444074 mitigation.</div><div class='del'>-		 */</div><div class='del'>-		if (!(IS_METEORLAKE(dev_priv)) &amp;&amp; size * 2 &lt; dev_priv-&gt;dsm.usable_size)</div><div class='del'>-			obj = i915_gem_object_create_stolen(dev_priv, size);</div><div class='del'>-		if (IS_ERR(obj))</div><div class='del'>-			obj = i915_gem_object_create_shmem(dev_priv, size);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (IS_ERR(obj)) {</div><div class='del'>-		drm_err(&amp;dev_priv-&gt;drm, "failed to allocate framebuffer (%pe)\n", obj);</div><div class='del'>-		return PTR_ERR(obj);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	fb = intel_framebuffer_create(obj, &amp;mode_cmd);</div><div class='del'>-	i915_gem_object_put(obj);</div><div class='del'>-	if (IS_ERR(fb))</div><div class='del'>-		return PTR_ERR(fb);</div><div class='del'>-</div><div class='del'>-	ifbdev-&gt;fb = to_intel_framebuffer(fb);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int intelfb_create(struct drm_fb_helper *helper,</div><div class='ctx'> 			  struct drm_fb_helper_surface_size *sizes)</div><div class='ctx'> {</div><div class='hunk'>@@ -213,7 +154,6 @@ static int intelfb_create(struct drm_fb_helper *helper,</div><div class='ctx'> 	struct drm_device *dev = helper-&gt;dev;</div><div class='ctx'> 	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='ctx'> 	struct pci_dev *pdev = to_pci_dev(dev_priv-&gt;drm.dev);</div><div class='del'>-	struct i915_ggtt *ggtt = to_gt(dev_priv)-&gt;ggtt;</div><div class='ctx'> 	const struct i915_gtt_view view = {</div><div class='ctx'> 		.type = I915_GTT_VIEW_NORMAL,</div><div class='ctx'> 	};</div><div class='hunk'>@@ -222,9 +162,7 @@ static int intelfb_create(struct drm_fb_helper *helper,</div><div class='ctx'> 	struct i915_vma *vma;</div><div class='ctx'> 	unsigned long flags = 0;</div><div class='ctx'> 	bool prealloc = false;</div><div class='del'>-	void __iomem *vaddr;</div><div class='ctx'> 	struct drm_i915_gem_object *obj;</div><div class='del'>-	struct i915_gem_ww_ctx ww;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ifbdev-&gt;hpd_lock);</div><div class='hunk'>@@ -245,12 +183,13 @@ static int intelfb_create(struct drm_fb_helper *helper,</div><div class='ctx'> 		intel_fb = ifbdev-&gt;fb = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(&amp;intel_fb-&gt;base))) {</div><div class='add'>+		struct drm_framebuffer *fb;</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			    "no BIOS fb, allocating a new one\n");</div><div class='del'>-		ret = intelfb_alloc(helper, sizes);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-		intel_fb = ifbdev-&gt;fb;</div><div class='add'>+		fb = intel_fbdev_fb_alloc(helper, sizes);</div><div class='add'>+		if (IS_ERR(fb))</div><div class='add'>+			return PTR_ERR(fb);</div><div class='add'>+		intel_fb = ifbdev-&gt;fb = to_intel_framebuffer(fb);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm, "re-using BIOS fb\n");</div><div class='ctx'> 		prealloc = true;</div><div class='hunk'>@@ -283,49 +222,18 @@ static int intelfb_create(struct drm_fb_helper *helper,</div><div class='ctx'> 	info-&gt;fbops = &amp;intelfb_ops;</div><div class='ctx'> </div><div class='ctx'> 	obj = intel_fb_obj(&amp;intel_fb-&gt;base);</div><div class='del'>-	if (i915_gem_object_is_lmem(obj)) {</div><div class='del'>-		struct intel_memory_region *mem = obj-&gt;mm.region;</div><div class='del'>-</div><div class='del'>-		/* Use fbdev's framebuffer from lmem for discrete */</div><div class='del'>-		info-&gt;fix.smem_start =</div><div class='del'>-			(unsigned long)(mem-&gt;io_start +</div><div class='del'>-					i915_gem_object_get_dma_address(obj, 0));</div><div class='del'>-		info-&gt;fix.smem_len = obj-&gt;base.size;</div><div class='del'>-	} else {</div><div class='del'>-		/* Our framebuffer is the entirety of fbdev's system memory */</div><div class='del'>-		info-&gt;fix.smem_start =</div><div class='del'>-			(unsigned long)(ggtt-&gt;gmadr.start + i915_ggtt_offset(vma));</div><div class='del'>-		info-&gt;fix.smem_len = vma-&gt;size;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for_i915_gem_ww(&amp;ww, ret, false) {</div><div class='del'>-		ret = i915_gem_object_lock(vma-&gt;obj, &amp;ww);</div><div class='del'>-</div><div class='del'>-		if (ret)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		vaddr = i915_vma_pin_iomap(vma);</div><div class='del'>-		if (IS_ERR(vaddr)) {</div><div class='del'>-			drm_err(&amp;dev_priv-&gt;drm,</div><div class='del'>-				"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);</div><div class='del'>-			ret = PTR_ERR(vaddr);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='ctx'> </div><div class='add'>+	ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_unpin;</div><div class='ctx'> </div><div class='del'>-	info-&gt;screen_base = vaddr;</div><div class='del'>-	info-&gt;screen_size = vma-&gt;size;</div><div class='del'>-</div><div class='ctx'> 	drm_fb_helper_fill_info(info, &amp;ifbdev-&gt;helper, sizes);</div><div class='ctx'> </div><div class='ctx'> 	/* If the object is shmemfs backed, it will have given us zeroed pages.</div><div class='ctx'> 	 * If the object is stolen however, it will be full of whatever</div><div class='ctx'> 	 * garbage was left in there.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!i915_gem_object_is_shmem(vma-&gt;obj) &amp;&amp; !prealloc)</div><div class='add'>+	if (!i915_gem_object_is_shmem(obj) &amp;&amp; !prealloc)</div><div class='ctx'> 		memset_io(info-&gt;screen_base, 0, info-&gt;screen_size);</div><div class='ctx'> </div><div class='ctx'> 	/* Use default scratch pixmap (info-&gt;pixmap.flags = FB_PIXMAP_SYSTEM) */</div><div class='hunk'>@@ -424,12 +332,12 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (obj-&gt;base.size &gt; max_size) {</div><div class='add'>+		if (intel_bo_to_drm_bo(obj)-&gt;size &gt; max_size) {</div><div class='ctx'> 			drm_dbg_kms(&amp;i915-&gt;drm,</div><div class='ctx'> 				    "found possible fb from [PLANE:%d:%s]\n",</div><div class='ctx'> 				    plane-&gt;base.base.id, plane-&gt;base.name);</div><div class='ctx'> 			fb = to_intel_framebuffer(plane_state-&gt;uapi.fb);</div><div class='del'>-			max_size = obj-&gt;base.size;</div><div class='add'>+			max_size = intel_bo_to_drm_bo(obj)-&gt;size;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c<br/>new file mode 100644<br/>index 000000000000..717c3a3237c4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbdev_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev_fb.c</a></div><div class='hunk'>@@ -0,0 +1,115 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_fb_helper.h&gt;</div><div class='add'>+</div><div class='add'>+#include "gem/i915_gem_lmem.h"</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_fbdev_fb.h"</div><div class='add'>+</div><div class='add'>+struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,</div><div class='add'>+					     struct drm_fb_helper_surface_size *sizes)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct drm_device *dev = helper-&gt;dev;</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='add'>+	struct drm_mode_fb_cmd2 mode_cmd = {};</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+	int size;</div><div class='add'>+</div><div class='add'>+	/* we don't do packed 24bpp */</div><div class='add'>+	if (sizes-&gt;surface_bpp == 24)</div><div class='add'>+		sizes-&gt;surface_bpp = 32;</div><div class='add'>+</div><div class='add'>+	mode_cmd.width = sizes-&gt;surface_width;</div><div class='add'>+	mode_cmd.height = sizes-&gt;surface_height;</div><div class='add'>+</div><div class='add'>+	mode_cmd.pitches[0] = ALIGN(mode_cmd.width *</div><div class='add'>+				    DIV_ROUND_UP(sizes-&gt;surface_bpp, 8), 64);</div><div class='add'>+	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes-&gt;surface_bpp,</div><div class='add'>+							  sizes-&gt;surface_depth);</div><div class='add'>+</div><div class='add'>+	size = mode_cmd.pitches[0] * mode_cmd.height;</div><div class='add'>+	size = PAGE_ALIGN(size);</div><div class='add'>+</div><div class='add'>+	obj = ERR_PTR(-ENODEV);</div><div class='add'>+	if (HAS_LMEM(dev_priv)) {</div><div class='add'>+		obj = i915_gem_object_create_lmem(dev_priv, size,</div><div class='add'>+						  I915_BO_ALLOC_CONTIGUOUS |</div><div class='add'>+						  I915_BO_ALLOC_USER);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * If the FB is too big, just don't use it since fbdev is not very</div><div class='add'>+		 * important and we should probably use that space with FBC or other</div><div class='add'>+		 * features.</div><div class='add'>+		 *</div><div class='add'>+		 * Also skip stolen on MTL as Wa_22018444074 mitigation.</div><div class='add'>+		 */</div><div class='add'>+		if (!(IS_METEORLAKE(dev_priv)) &amp;&amp; size * 2 &lt; dev_priv-&gt;dsm.usable_size)</div><div class='add'>+			obj = i915_gem_object_create_stolen(dev_priv, size);</div><div class='add'>+		if (IS_ERR(obj))</div><div class='add'>+			obj = i915_gem_object_create_shmem(dev_priv, size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(obj)) {</div><div class='add'>+		drm_err(&amp;dev_priv-&gt;drm, "failed to allocate framebuffer (%pe)\n", obj);</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fb = intel_framebuffer_create(obj, &amp;mode_cmd);</div><div class='add'>+	i915_gem_object_put(obj);</div><div class='add'>+</div><div class='add'>+	return fb;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,</div><div class='add'>+			     struct drm_i915_gem_object *obj, struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct i915_gem_ww_ctx ww;</div><div class='add'>+	void __iomem *vaddr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (i915_gem_object_is_lmem(obj)) {</div><div class='add'>+		struct intel_memory_region *mem = obj-&gt;mm.region;</div><div class='add'>+</div><div class='add'>+		/* Use fbdev's framebuffer from lmem for discrete */</div><div class='add'>+		info-&gt;fix.smem_start =</div><div class='add'>+			(unsigned long)(mem-&gt;io_start +</div><div class='add'>+					i915_gem_object_get_dma_address(obj, 0));</div><div class='add'>+		info-&gt;fix.smem_len = obj-&gt;base.size;</div><div class='add'>+	} else {</div><div class='add'>+		struct i915_ggtt *ggtt = to_gt(i915)-&gt;ggtt;</div><div class='add'>+</div><div class='add'>+		/* Our framebuffer is the entirety of fbdev's system memory */</div><div class='add'>+		info-&gt;fix.smem_start =</div><div class='add'>+			(unsigned long)(ggtt-&gt;gmadr.start + i915_ggtt_offset(vma));</div><div class='add'>+		info-&gt;fix.smem_len = vma-&gt;size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_i915_gem_ww(&amp;ww, ret, false) {</div><div class='add'>+		ret = i915_gem_object_lock(vma-&gt;obj, &amp;ww);</div><div class='add'>+</div><div class='add'>+		if (ret)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vaddr = i915_vma_pin_iomap(vma);</div><div class='add'>+		if (IS_ERR(vaddr)) {</div><div class='add'>+			drm_err(&amp;i915-&gt;drm,</div><div class='add'>+				"Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);</div><div class='add'>+			ret = PTR_ERR(vaddr);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	info-&gt;screen_base = vaddr;</div><div class='add'>+	info-&gt;screen_size = intel_bo_to_drm_bo(obj)-&gt;size;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h<br/>new file mode 100644<br/>index 000000000000..a395b2c65d33<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_fbdev_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_fbdev_fb.h</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_FBDEV_FB_H__</div><div class='add'>+#define __INTEL_FBDEV_FB_H__</div><div class='add'>+</div><div class='add'>+struct drm_fb_helper;</div><div class='add'>+struct drm_fb_helper_surface_size;</div><div class='add'>+struct drm_i915_gem_object;</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+struct fb_info;</div><div class='add'>+struct i915_vma;</div><div class='add'>+</div><div class='add'>+struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,</div><div class='add'>+					     struct drm_fb_helper_surface_size *sizes);</div><div class='add'>+int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,</div><div class='add'>+			     struct drm_i915_gem_object *obj, struct i915_vma *vma);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c<br/>index 40d7b6f3f489..e9e4dcf345f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_gmbus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_gmbus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_gmbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_gmbus.c</a></div><div class='hunk'>@@ -899,7 +899,6 @@ int intel_gmbus_setup(struct drm_i915_private *i915)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		bus-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-		bus-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 		snprintf(bus-&gt;adapter.name,</div><div class='ctx'> 			 sizeof(bus-&gt;adapter.name),</div><div class='ctx'> 			 "i915 gmbus %s", gmbus_pin-&gt;name);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c<br/>index ab18cfc19c0a..39e4f5f7c817 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_hdmi.c</a></div><div class='hunk'>@@ -1983,6 +1983,10 @@ intel_hdmi_mode_valid(struct drm_connector *connector,</div><div class='ctx'> 	bool ycbcr_420_only;</div><div class='ctx'> 	enum intel_output_format sink_format;</div><div class='ctx'> </div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	if ((mode-&gt;flags &amp; DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)</div><div class='ctx'> 		clock *= 2;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c<br/>index 4b114fde57b1..221f5c6c871b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_lvds.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_lvds.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_lvds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_lvds.c</a></div><div class='hunk'>@@ -185,7 +185,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,</div><div class='ctx'> 	/* Convert from 100ms to 100us units */</div><div class='ctx'> 	pps-&gt;t4 = val * 1000;</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt;= 4 &amp;&amp;</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 5 &amp;&amp;</div><div class='ctx'> 	    pps-&gt;t1_t2 == 0 &amp;&amp; pps-&gt;t5 == 0 &amp;&amp; pps-&gt;t3 == 0 &amp;&amp; pps-&gt;tx == 0) {</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			    "Panel power timings uninitialized, "</div><div class='hunk'>@@ -389,11 +389,16 @@ intel_lvds_mode_valid(struct drm_connector *_connector,</div><div class='ctx'> 		      struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_connector *connector = to_intel_connector(_connector);</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	const struct drm_display_mode *fixed_mode =</div><div class='ctx'> 		intel_panel_fixed_mode(connector, mode);</div><div class='ctx'> 	int max_pixclk = to_i915(connector-&gt;base.dev)-&gt;max_dotclk_freq;</div><div class='ctx'> 	enum drm_mode_status status;</div><div class='ctx'> </div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN)</div><div class='ctx'> 		return MODE_NO_DBLESCAN;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c<br/>index 15c1804dcd59..8f702c3fc62d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_psr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_psr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_psr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_psr.c</a></div><div class='hunk'>@@ -806,10 +806,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)</div><div class='ctx'> </div><div class='ctx'> 	val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt;= 13 &amp;&amp; !IS_ALDERLAKE_P(dev_priv))</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 14 &amp;&amp; !IS_ALDERLAKE_P(dev_priv))</div><div class='ctx'> 		val |= EDP_SU_TRACK_ENABLE;</div><div class='ctx'> </div><div class='del'>-	if (DISPLAY_VER(dev_priv) &gt;= 10 &amp;&amp; DISPLAY_VER(dev_priv) &lt;= 12)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &gt;= 10 &amp;&amp; DISPLAY_VER(dev_priv) &lt; 13)</div><div class='ctx'> 		val |= EDP_Y_COORDINATE_ENABLE;</div><div class='ctx'> </div><div class='ctx'> 	val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));</div><div class='hunk'>@@ -891,13 +891,13 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder cpu_trans</div><div class='ctx'> 		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)</div><div class='add'>+static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> {</div><div class='del'>-	if (!cstate || !cstate-&gt;hw.active)</div><div class='add'>+	if (!crtc_state-&gt;hw.active)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	return DIV_ROUND_UP(1000 * 1000,</div><div class='del'>-			    drm_mode_vrefresh(&amp;cstate-&gt;hw.adjusted_mode));</div><div class='add'>+			    drm_mode_vrefresh(&amp;crtc_state-&gt;hw.adjusted_mode));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void psr2_program_idle_frames(struct intel_dp *intel_dp,</div><div class='hunk'>@@ -1094,7 +1094,7 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	/* Not supported &lt;13 / Wa_22012279113:adl-p */</div><div class='del'>-	if (DISPLAY_VER(dev_priv) &lt;= 13 || intel_dp-&gt;edp_dpcd[0] &lt; DP_EDP_14b)</div><div class='add'>+	if (DISPLAY_VER(dev_priv) &lt; 14 || intel_dp-&gt;edp_dpcd[0] &lt; DP_EDP_14b)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	crtc_state-&gt;req_psr2_sdp_prior_scanline = true;</div><div class='hunk'>@@ -1221,7 +1221,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,</div><div class='ctx'> 	 * over PSR2.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (crtc_state-&gt;dsc.compression_enable &amp;&amp;</div><div class='del'>-	    (DISPLAY_VER(dev_priv) &lt;= 13 &amp;&amp; !IS_ALDERLAKE_P(dev_priv))) {</div><div class='add'>+	    (DISPLAY_VER(dev_priv) &lt; 14 &amp;&amp; !IS_ALDERLAKE_P(dev_priv))) {</div><div class='ctx'> 		drm_dbg_kms(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			    "PSR2 cannot be enabled since DSC is enabled\n");</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -1917,81 +1917,6 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)</div><div class='ctx'> 	intel_de_write(dev_priv, CURSURFLIVE(intel_dp-&gt;psr.pipe), 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void intel_psr2_disable_plane_sel_fetch_arm(struct intel_plane *plane,</div><div class='del'>-					    const struct intel_crtc_state *crtc_state)</div><div class='del'>-{</div><div class='del'>-	struct drm_i915_private *dev_priv = to_i915(plane-&gt;base.dev);</div><div class='del'>-	enum pipe pipe = plane-&gt;pipe;</div><div class='del'>-</div><div class='del'>-	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id), 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void intel_psr2_program_plane_sel_fetch_arm(struct intel_plane *plane,</div><div class='del'>-					    const struct intel_crtc_state *crtc_state,</div><div class='del'>-					    const struct intel_plane_state *plane_state)</div><div class='del'>-{</div><div class='del'>-	struct drm_i915_private *i915 = to_i915(plane-&gt;base.dev);</div><div class='del'>-	enum pipe pipe = plane-&gt;pipe;</div><div class='del'>-</div><div class='del'>-	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (plane-&gt;id == PLANE_CURSOR)</div><div class='del'>-		intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id),</div><div class='del'>-				  plane_state-&gt;ctl);</div><div class='del'>-	else</div><div class='del'>-		intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id),</div><div class='del'>-				  PLANE_SEL_FETCH_CTL_ENABLE);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,</div><div class='del'>-					      const struct intel_crtc_state *crtc_state,</div><div class='del'>-					      const struct intel_plane_state *plane_state,</div><div class='del'>-					      int color_plane)</div><div class='del'>-{</div><div class='del'>-	struct drm_i915_private *dev_priv = to_i915(plane-&gt;base.dev);</div><div class='del'>-	enum pipe pipe = plane-&gt;pipe;</div><div class='del'>-	const struct drm_rect *clip;</div><div class='del'>-	u32 val;</div><div class='del'>-	int x, y;</div><div class='del'>-</div><div class='del'>-	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (plane-&gt;id == PLANE_CURSOR)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	clip = &amp;plane_state-&gt;psr2_sel_fetch_area;</div><div class='del'>-</div><div class='del'>-	val = (clip-&gt;y1 + plane_state-&gt;uapi.dst.y1) &lt;&lt; 16;</div><div class='del'>-	val |= plane_state-&gt;uapi.dst.x1;</div><div class='del'>-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-&gt;id), val);</div><div class='del'>-</div><div class='del'>-	x = plane_state-&gt;view.color_plane[color_plane].x;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * From Bspec: UV surface Start Y Position = half of Y plane Y</div><div class='del'>-	 * start position.</div><div class='del'>-	 */</div><div class='del'>-	if (!color_plane)</div><div class='del'>-		y = plane_state-&gt;view.color_plane[color_plane].y + clip-&gt;y1;</div><div class='del'>-	else</div><div class='del'>-		y = plane_state-&gt;view.color_plane[color_plane].y + clip-&gt;y1 / 2;</div><div class='del'>-</div><div class='del'>-	val = y &lt;&lt; 16 | x;</div><div class='del'>-</div><div class='del'>-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-&gt;id),</div><div class='del'>-			  val);</div><div class='del'>-</div><div class='del'>-	/* Sizes are 0 based */</div><div class='del'>-	val = (drm_rect_height(clip) - 1) &lt;&lt; 16;</div><div class='del'>-	val |= (drm_rect_width(&amp;plane_state-&gt;uapi.src) &gt;&gt; 16) - 1;</div><div class='del'>-	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-&gt;id), val);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_i915_private *dev_priv = to_i915(crtc_state-&gt;uapi.crtc-&gt;dev);</div><div class='hunk'>@@ -2251,8 +2176,19 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		inter = pipe_clip;</div><div class='del'>-		if (!drm_rect_intersect(&amp;inter, &amp;new_plane_state-&gt;uapi.dst))</div><div class='add'>+		sel_fetch_area = &amp;new_plane_state-&gt;psr2_sel_fetch_area;</div><div class='add'>+		if (!drm_rect_intersect(&amp;inter, &amp;new_plane_state-&gt;uapi.dst)) {</div><div class='add'>+			sel_fetch_area-&gt;y1 = -1;</div><div class='add'>+			sel_fetch_area-&gt;y2 = -1;</div><div class='add'>+			/*</div><div class='add'>+			 * if plane sel fetch was previously enabled -&gt;</div><div class='add'>+			 * disable it</div><div class='add'>+			 */</div><div class='add'>+			if (drm_rect_height(&amp;old_plane_state-&gt;psr2_sel_fetch_area) &gt; 0)</div><div class='add'>+				crtc_state-&gt;update_planes |= BIT(plane-&gt;id);</div><div class='add'>+</div><div class='ctx'> 			continue;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {</div><div class='ctx'> 			full_update = true;</div><div class='hunk'>@@ -3383,11 +3319,11 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(connector-&gt;base.dev);</div><div class='ctx'> 	struct dentry *root = connector-&gt;base.debugfs_entry;</div><div class='ctx'> </div><div class='del'>-	if (connector-&gt;base.connector_type != DRM_MODE_CONNECTOR_eDP) {</div><div class='del'>-		if (!(HAS_DP20(i915) &amp;&amp;</div><div class='del'>-		      connector-&gt;base.connector_type == DRM_MODE_CONNECTOR_DisplayPort))</div><div class='del'>-			return;</div><div class='del'>-	}</div><div class='add'>+	/* TODO: Add support for MST connectors as well. */</div><div class='add'>+	if ((connector-&gt;base.connector_type != DRM_MODE_CONNECTOR_eDP &amp;&amp;</div><div class='add'>+	     connector-&gt;base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||</div><div class='add'>+	    connector-&gt;mst_port)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_file("i915_psr_sink_status", 0444, root,</div><div class='ctx'> 			    connector, &amp;i915_psr_sink_status_fops);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h<br/>index 6a1f4573852b..143e0595c097 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_psr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_psr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_psr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_psr.h</a></div><div class='hunk'>@@ -55,16 +55,6 @@ bool intel_psr_enabled(struct intel_dp *intel_dp);</div><div class='ctx'> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,</div><div class='ctx'> 				struct intel_crtc *crtc);</div><div class='ctx'> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);</div><div class='del'>-void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,</div><div class='del'>-					      const struct intel_crtc_state *crtc_state,</div><div class='del'>-					      const struct intel_plane_state *plane_state,</div><div class='del'>-					      int color_plane);</div><div class='del'>-void intel_psr2_program_plane_sel_fetch_arm(struct intel_plane *plane,</div><div class='del'>-					    const struct intel_crtc_state *crtc_state,</div><div class='del'>-					    const struct intel_plane_state *plane_state);</div><div class='del'>-</div><div class='del'>-void intel_psr2_disable_plane_sel_fetch_arm(struct intel_plane *plane,</div><div class='del'>-					    const struct intel_crtc_state *crtc_state);</div><div class='ctx'> void intel_psr_pause(struct intel_dp *intel_dp);</div><div class='ctx'> void intel_psr_resume(struct intel_dp *intel_dp);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c<br/>index bcb4959df70d..acc6b6804105 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_sdvo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_sdvo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_sdvo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_sdvo.c</a></div><div class='hunk'>@@ -1931,13 +1931,19 @@ static enum drm_mode_status</div><div class='ctx'> intel_sdvo_mode_valid(struct drm_connector *connector,</div><div class='ctx'> 		      struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='ctx'> 	struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));</div><div class='ctx'> 	struct intel_sdvo_connector *intel_sdvo_connector =</div><div class='ctx'> 		to_intel_sdvo_connector(connector);</div><div class='del'>-	int max_dotclk = to_i915(connector-&gt;dev)-&gt;max_dotclk_freq;</div><div class='ctx'> 	bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector-&gt;state);</div><div class='add'>+	int max_dotclk = i915-&gt;max_dotclk_freq;</div><div class='add'>+	enum drm_mode_status status;</div><div class='ctx'> 	int clock = mode-&gt;clock;</div><div class='ctx'> </div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN)</div><div class='ctx'> 		return MODE_NO_DBLESCAN;</div><div class='ctx'> </div><div class='hunk'>@@ -3321,7 +3327,6 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,</div><div class='ctx'> 	ddc-&gt;ddc_bus = ddc_bus;</div><div class='ctx'> </div><div class='ctx'> 	ddc-&gt;ddc.owner = THIS_MODULE;</div><div class='del'>-	ddc-&gt;ddc.class = I2C_CLASS_DDC;</div><div class='ctx'> 	snprintf(ddc-&gt;ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",</div><div class='ctx'> 		 port_name(sdvo-&gt;base.port), ddc_bus);</div><div class='ctx'> 	ddc-&gt;ddc.dev.parent = &amp;pdev-&gt;dev;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c<br/>index ce5a73a4cc89..bc61e736f9b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_snps_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_snps_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_snps_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_snps_phy.c</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'>  * Copyright © 2019 Intel Corporation</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/util_macros.h&gt;</div><div class='add'>+#include &lt;linux/math.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "i915_reg.h"</div><div class='ctx'> #include "intel_ddi.h"</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c<br/>index f64d348a969e..dcf05e00e505 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_tc.c</a></div><div class='hunk'>@@ -1030,18 +1030,25 @@ static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enabl</div><div class='ctx'> </div><div class='ctx'> 	__xelpdp_tc_phy_enable_tcss_power(tc, enable);</div><div class='ctx'> </div><div class='del'>-	if ((!tc_phy_wait_for_ready(tc) ||</div><div class='del'>-	     !xelpdp_tc_phy_wait_for_tcss_power(tc, enable)) &amp;&amp;</div><div class='del'>-	    !drm_WARN_ON(&amp;i915-&gt;drm, tc-&gt;mode == TC_PORT_LEGACY)) {</div><div class='del'>-		if (enable) {</div><div class='del'>-			__xelpdp_tc_phy_enable_tcss_power(tc, false);</div><div class='del'>-			xelpdp_tc_phy_wait_for_tcss_power(tc, false);</div><div class='del'>-		}</div><div class='add'>+	if (enable &amp;&amp; !tc_phy_wait_for_ready(tc))</div><div class='add'>+		goto out_disable;</div><div class='ctx'> </div><div class='del'>-		return false;</div><div class='del'>-	}</div><div class='add'>+	if (!xelpdp_tc_phy_wait_for_tcss_power(tc, enable))</div><div class='add'>+		goto out_disable;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='add'>+</div><div class='add'>+out_disable:</div><div class='add'>+	if (drm_WARN_ON(&amp;i915-&gt;drm, tc-&gt;mode == TC_PORT_LEGACY))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!enable)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	__xelpdp_tc_phy_enable_tcss_power(tc, false);</div><div class='add'>+	xelpdp_tc_phy_wait_for_tcss_power(tc, false);</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c<br/>index 31a79fdfc812..d4386cb3569e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_tv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_tv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_tv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_tv.c</a></div><div class='hunk'>@@ -958,8 +958,14 @@ static enum drm_mode_status</div><div class='ctx'> intel_tv_mode_valid(struct drm_connector *connector,</div><div class='ctx'> 		    struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='ctx'> 	const struct tv_mode *tv_mode = intel_tv_mode_find(connector-&gt;state);</div><div class='del'>-	int max_dotclk = to_i915(connector-&gt;dev)-&gt;max_dotclk_freq;</div><div class='add'>+	int max_dotclk = i915-&gt;max_dotclk_freq;</div><div class='add'>+	enum drm_mode_status status;</div><div class='add'>+</div><div class='add'>+	status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+	if (status != MODE_OK)</div><div class='add'>+		return status;</div><div class='ctx'> </div><div class='ctx'> 	if (mode-&gt;flags &amp; DRM_MODE_FLAG_DBLSCAN)</div><div class='ctx'> 		return MODE_NO_DBLESCAN;</div><div class='hunk'>@@ -1411,9 +1417,6 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,</div><div class='ctx'> static void set_color_conversion(struct drm_i915_private *dev_priv,</div><div class='ctx'> 				 const struct color_conversion *color_conversion)</div><div class='ctx'> {</div><div class='del'>-	if (!color_conversion)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	intel_de_write(dev_priv, TV_CSC_Y,</div><div class='ctx'> 		       (color_conversion-&gt;ry &lt;&lt; 16) | color_conversion-&gt;gy);</div><div class='ctx'> 	intel_de_write(dev_priv, TV_CSC_Y2,</div><div class='hunk'>@@ -1448,9 +1451,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,</div><div class='ctx'> 	int xpos, ypos;</div><div class='ctx'> 	unsigned int xsize, ysize;</div><div class='ctx'> </div><div class='del'>-	if (!tv_mode)</div><div class='del'>-		return;	/* can't happen (mode_prepare prevents this) */</div><div class='del'>-</div><div class='ctx'> 	tv_ctl = intel_de_read(dev_priv, TV_CTL);</div><div class='ctx'> 	tv_ctl &amp;= TV_CTL_SAVE;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c<br/>index 2cec2abf9746..fe256bf7b485 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_vblank.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_vblank.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_vblank.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_vblank.c</a></div><div class='hunk'>@@ -265,6 +265,32 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)</div><div class='ctx'> 	return (scanline + vtotal - crtc-&gt;scanline_offset) % vtotal;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * The uncore version of the spin lock functions is used to decide</div><div class='add'>+ * whether we need to lock the uncore lock or not.  This is only</div><div class='add'>+ * needed in i915, not in Xe.</div><div class='add'>+ *</div><div class='add'>+ * This lock in i915 is needed because some old platforms (at least</div><div class='add'>+ * IVB and possibly HSW as well), which are not supported in Xe, need</div><div class='add'>+ * all register accesses to the same cacheline to be serialized,</div><div class='add'>+ * otherwise they may hang.</div><div class='add'>+ */</div><div class='add'>+static void intel_vblank_section_enter(struct drm_i915_private *i915)</div><div class='add'>+	__acquires(i915-&gt;uncore.lock)</div><div class='add'>+{</div><div class='add'>+#ifdef I915</div><div class='add'>+	spin_lock(&amp;i915-&gt;uncore.lock);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void intel_vblank_section_exit(struct drm_i915_private *i915)</div><div class='add'>+	__releases(i915-&gt;uncore.lock)</div><div class='add'>+{</div><div class='add'>+#ifdef I915</div><div class='add'>+	spin_unlock(&amp;i915-&gt;uncore.lock);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,</div><div class='ctx'> 				     bool in_vblank_irq,</div><div class='ctx'> 				     int *vpos, int *hpos,</div><div class='hunk'>@@ -302,11 +328,12 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Lock uncore.lock, as we will do multiple timing critical raw</div><div class='del'>-	 * register reads, potentially with preemption disabled, so the</div><div class='del'>-	 * following code must not block on uncore.lock.</div><div class='add'>+	 * Enter vblank critical section, as we will do multiple</div><div class='add'>+	 * timing critical raw register reads, potentially with</div><div class='add'>+	 * preemption disabled, so the following code must not block.</div><div class='ctx'> 	 */</div><div class='del'>-	spin_lock_irqsave(&amp;dev_priv-&gt;uncore.lock, irqflags);</div><div class='add'>+	local_irq_save(irqflags);</div><div class='add'>+	intel_vblank_section_enter(dev_priv);</div><div class='ctx'> </div><div class='ctx'> 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */</div><div class='ctx'> </div><div class='hunk'>@@ -374,7 +401,8 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,</div><div class='ctx'> </div><div class='ctx'> 	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */</div><div class='ctx'> </div><div class='del'>-	spin_unlock_irqrestore(&amp;dev_priv-&gt;uncore.lock, irqflags);</div><div class='add'>+	intel_vblank_section_exit(dev_priv);</div><div class='add'>+	local_irq_restore(irqflags);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * While in vblank, position will be negative</div><div class='hunk'>@@ -412,9 +440,13 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)</div><div class='ctx'> 	unsigned long irqflags;</div><div class='ctx'> 	int position;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;dev_priv-&gt;uncore.lock, irqflags);</div><div class='add'>+	local_irq_save(irqflags);</div><div class='add'>+	intel_vblank_section_enter(dev_priv);</div><div class='add'>+</div><div class='ctx'> 	position = __intel_get_crtc_scanline(crtc);</div><div class='del'>-	spin_unlock_irqrestore(&amp;dev_priv-&gt;uncore.lock, irqflags);</div><div class='add'>+</div><div class='add'>+	intel_vblank_section_exit(dev_priv);</div><div class='add'>+	local_irq_restore(irqflags);</div><div class='ctx'> </div><div class='ctx'> 	return position;</div><div class='ctx'> }</div><div class='hunk'>@@ -537,7 +569,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,</div><div class='ctx'> 	 * Need to audit everything to make sure it's safe.</div><div class='ctx'> 	 */</div><div class='ctx'> 	spin_lock_irqsave(&amp;i915-&gt;drm.vblank_time_lock, irqflags);</div><div class='del'>-	spin_lock(&amp;i915-&gt;uncore.lock);</div><div class='add'>+	intel_vblank_section_enter(i915);</div><div class='ctx'> </div><div class='ctx'> 	drm_calc_timestamping_constants(&amp;crtc-&gt;base, &amp;adjusted_mode);</div><div class='ctx'> </div><div class='hunk'>@@ -546,7 +578,6 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,</div><div class='ctx'> 	crtc-&gt;mode_flags = mode_flags;</div><div class='ctx'> </div><div class='ctx'> 	crtc-&gt;scanline_offset = intel_crtc_scanline_offset(crtc_state);</div><div class='del'>-</div><div class='del'>-	spin_unlock(&amp;i915-&gt;uncore.lock);</div><div class='add'>+	intel_vblank_section_exit(i915);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;i915-&gt;drm.vblank_time_lock, irqflags);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c<br/>index 5f2fb702e367..17d6572f9d0a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_vdsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/intel_vdsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/intel_vdsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/intel_vdsc.c</a></div><div class='hunk'>@@ -812,13 +812,13 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,</div><div class='del'>-			      bool *check_equal)</div><div class='add'>+			      bool *all_equal)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state-&gt;uapi.crtc);</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(crtc-&gt;base.dev);</div><div class='ctx'> 	i915_reg_t dsc_reg[2];</div><div class='ctx'> 	int i, vdsc_per_pipe, dsc_reg_num;</div><div class='del'>-	u32 val = 0;</div><div class='add'>+	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);</div><div class='ctx'> 	dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);</div><div class='hunk'>@@ -827,20 +827,13 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,</div><div class='ctx'> </div><div class='ctx'> 	intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);</div><div class='ctx'> </div><div class='del'>-	if (check_equal)</div><div class='del'>-		*check_equal = true;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dsc_reg_num; i++) {</div><div class='del'>-		u32 tmp;</div><div class='add'>+	*all_equal = true;</div><div class='ctx'> </div><div class='del'>-		tmp = intel_de_read(i915, dsc_reg[i]);</div><div class='add'>+	val = intel_de_read(i915, dsc_reg[0]);</div><div class='ctx'> </div><div class='del'>-		if (i == 0) {</div><div class='del'>-			val = tmp;</div><div class='del'>-		} else if (check_equal &amp;&amp; tmp != val) {</div><div class='del'>-			*check_equal = false;</div><div class='del'>-			break;</div><div class='del'>-		} else if (!check_equal) {</div><div class='add'>+	for (i = 1; i &lt; dsc_reg_num; i++) {</div><div class='add'>+		if (intel_de_read(i915, dsc_reg[i]) != val) {</div><div class='add'>+			*all_equal = false;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c<br/>index 1e7c97243fcf..8a934bada624 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/skl_scaler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/skl_scaler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/skl_scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/skl_scaler.c</a></div><div class='hunk'>@@ -504,7 +504,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_plane *plane = NULL;</div><div class='ctx'> 	struct intel_plane *intel_plane;</div><div class='del'>-	struct intel_plane_state *plane_state = NULL;</div><div class='ctx'> 	struct intel_crtc_scaler_state *scaler_state =</div><div class='ctx'> 		&amp;crtc_state-&gt;scaler_state;</div><div class='ctx'> 	struct drm_atomic_state *drm_state = crtc_state-&gt;uapi.state;</div><div class='hunk'>@@ -536,6 +535,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,</div><div class='ctx'> </div><div class='ctx'> 	/* walkthrough scaler_users bits and start assigning scalers */</div><div class='ctx'> 	for (i = 0; i &lt; sizeof(scaler_state-&gt;scaler_users) * 8; i++) {</div><div class='add'>+		struct intel_plane_state *plane_state = NULL;</div><div class='ctx'> 		int *scaler_id;</div><div class='ctx'> 		const char *name;</div><div class='ctx'> 		int idx, ret;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c<br/>index f5c77a018e10..511dc1544854 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/skl_universal_plane.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/skl_universal_plane.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/skl_universal_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/skl_universal_plane.c</a></div><div class='hunk'>@@ -18,6 +18,7 @@</div><div class='ctx'> #include "intel_fbc.h"</div><div class='ctx'> #include "intel_frontbuffer.h"</div><div class='ctx'> #include "intel_psr.h"</div><div class='add'>+#include "intel_psr_regs.h"</div><div class='ctx'> #include "skl_scaler.h"</div><div class='ctx'> #include "skl_universal_plane.h"</div><div class='ctx'> #include "skl_watermark.h"</div><div class='hunk'>@@ -629,6 +630,18 @@ skl_plane_disable_arm(struct intel_plane *plane,</div><div class='ctx'> 	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,</div><div class='add'>+					    const struct intel_crtc_state *crtc_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(plane-&gt;base.dev);</div><div class='add'>+	enum pipe pipe = plane-&gt;pipe;</div><div class='add'>+</div><div class='add'>+	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id), 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> icl_plane_disable_arm(struct intel_plane *plane,</div><div class='ctx'> 		      const struct intel_crtc_state *crtc_state)</div><div class='hunk'>@@ -642,7 +655,7 @@ icl_plane_disable_arm(struct intel_plane *plane,</div><div class='ctx'> </div><div class='ctx'> 	skl_write_plane_wm(plane, crtc_state);</div><div class='ctx'> </div><div class='del'>-	intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);</div><div class='add'>+	icl_plane_disable_sel_fetch_arm(plane, crtc_state);</div><div class='ctx'> 	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);</div><div class='ctx'> 	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -1197,6 +1210,48 @@ skl_plane_update_arm(struct intel_plane *plane,</div><div class='ctx'> 			  skl_plane_surf(plane_state, 0));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,</div><div class='add'>+					     const struct intel_crtc_state *crtc_state,</div><div class='add'>+					     const struct intel_plane_state *plane_state,</div><div class='add'>+					     int color_plane)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(plane-&gt;base.dev);</div><div class='add'>+	enum pipe pipe = plane-&gt;pipe;</div><div class='add'>+	const struct drm_rect *clip;</div><div class='add'>+	u32 val;</div><div class='add'>+	int x, y;</div><div class='add'>+</div><div class='add'>+	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	clip = &amp;plane_state-&gt;psr2_sel_fetch_area;</div><div class='add'>+</div><div class='add'>+	val = (clip-&gt;y1 + plane_state-&gt;uapi.dst.y1) &lt;&lt; 16;</div><div class='add'>+	val |= plane_state-&gt;uapi.dst.x1;</div><div class='add'>+	intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane-&gt;id), val);</div><div class='add'>+</div><div class='add'>+	x = plane_state-&gt;view.color_plane[color_plane].x;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * From Bspec: UV surface Start Y Position = half of Y plane Y</div><div class='add'>+	 * start position.</div><div class='add'>+	 */</div><div class='add'>+	if (!color_plane)</div><div class='add'>+		y = plane_state-&gt;view.color_plane[color_plane].y + clip-&gt;y1;</div><div class='add'>+	else</div><div class='add'>+		y = plane_state-&gt;view.color_plane[color_plane].y + clip-&gt;y1 / 2;</div><div class='add'>+</div><div class='add'>+	val = y &lt;&lt; 16 | x;</div><div class='add'>+</div><div class='add'>+	intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane-&gt;id),</div><div class='add'>+			  val);</div><div class='add'>+</div><div class='add'>+	/* Sizes are 0 based */</div><div class='add'>+	val = (drm_rect_height(clip) - 1) &lt;&lt; 16;</div><div class='add'>+	val |= (drm_rect_width(&amp;plane_state-&gt;uapi.src) &gt;&gt; 16) - 1;</div><div class='add'>+	intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane-&gt;id), val);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> icl_plane_update_noarm(struct intel_plane *plane,</div><div class='ctx'> 		       const struct intel_crtc_state *crtc_state,</div><div class='hunk'>@@ -1269,7 +1324,24 @@ icl_plane_update_noarm(struct intel_plane *plane,</div><div class='ctx'> 	if (plane_state-&gt;force_black)</div><div class='ctx'> 		icl_plane_csc_load_black(plane);</div><div class='ctx'> </div><div class='del'>-	intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);</div><div class='add'>+	icl_plane_update_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,</div><div class='add'>+					   const struct intel_crtc_state *crtc_state,</div><div class='add'>+					   const struct intel_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(plane-&gt;base.dev);</div><div class='add'>+	enum pipe pipe = plane-&gt;pipe;</div><div class='add'>+</div><div class='add'>+	if (!crtc_state-&gt;enable_psr2_sel_fetch)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (drm_rect_height(&amp;plane_state-&gt;psr2_sel_fetch_area) &gt; 0)</div><div class='add'>+		intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane-&gt;id),</div><div class='add'>+				  PLANE_SEL_FETCH_CTL_ENABLE);</div><div class='add'>+	else</div><div class='add'>+		icl_plane_disable_sel_fetch_arm(plane, crtc_state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -1296,7 +1368,7 @@ icl_plane_update_arm(struct intel_plane *plane,</div><div class='ctx'> 	if (plane_state-&gt;scaler_id &gt;= 0)</div><div class='ctx'> 		skl_program_plane_scaler(plane, crtc_state, plane_state);</div><div class='ctx'> </div><div class='del'>-	intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state);</div><div class='add'>+	icl_plane_update_sel_fetch_arm(plane, crtc_state, plane_state);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The control register self-arms if the plane was previously</div><div class='head'>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c<br/>index bda49734ca33..9b33b8a74d64 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/vlv_dsi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/display/vlv_dsi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/display/vlv_dsi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/display/vlv_dsi.c</a></div><div class='hunk'>@@ -1532,21 +1532,29 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)</div><div class='add'>+static const struct drm_encoder_funcs intel_dsi_funcs = {</div><div class='add'>+	.destroy = intel_encoder_destroy,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,</div><div class='add'>+					       struct drm_display_mode *mode)</div><div class='ctx'> {</div><div class='del'>-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(connector-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	intel_dsi_vbt_gpio_cleanup(intel_dsi);</div><div class='del'>-	intel_encoder_destroy(encoder);</div><div class='del'>-}</div><div class='add'>+	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {</div><div class='add'>+		enum drm_mode_status status;</div><div class='ctx'> </div><div class='del'>-static const struct drm_encoder_funcs intel_dsi_funcs = {</div><div class='del'>-	.destroy = intel_dsi_encoder_destroy,</div><div class='del'>-};</div><div class='add'>+		status = intel_cpu_transcoder_mode_valid(i915, mode);</div><div class='add'>+		if (status != MODE_OK)</div><div class='add'>+			return status;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return intel_dsi_mode_valid(connector, mode);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {</div><div class='ctx'> 	.get_modes = intel_dsi_get_modes,</div><div class='del'>-	.mode_valid = intel_dsi_mode_valid,</div><div class='add'>+	.mode_valid = vlv_dsi_mode_valid,</div><div class='ctx'> 	.atomic_check = intel_digital_connector_atomic_check,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c<br/>index e38f06a6e56e..dcbfe32fd30c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_context.c</a></div><div class='hunk'>@@ -279,7 +279,8 @@ static int proto_context_set_protected(struct drm_i915_private *i915,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct i915_gem_proto_context *</div><div class='del'>-proto_context_create(struct drm_i915_private *i915, unsigned int flags)</div><div class='add'>+proto_context_create(struct drm_i915_file_private *fpriv,</div><div class='add'>+		     struct drm_i915_private *i915, unsigned int flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct i915_gem_proto_context *pc, *err;</div><div class='ctx'> </div><div class='hunk'>@@ -287,6 +288,7 @@ proto_context_create(struct drm_i915_private *i915, unsigned int flags)</div><div class='ctx'> 	if (!pc)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='add'>+	pc-&gt;fpriv = fpriv;</div><div class='ctx'> 	pc-&gt;num_user_engines = -1;</div><div class='ctx'> 	pc-&gt;user_engines = NULL;</div><div class='ctx'> 	pc-&gt;user_flags = BIT(UCONTEXT_BANNABLE) |</div><div class='hunk'>@@ -1622,6 +1624,7 @@ i915_gem_create_context(struct drm_i915_private *i915,</div><div class='ctx'> 			err = PTR_ERR(ppgtt);</div><div class='ctx'> 			goto err_ctx;</div><div class='ctx'> 		}</div><div class='add'>+		ppgtt-&gt;vm.fpriv = pc-&gt;fpriv;</div><div class='ctx'> 		vm = &amp;ppgtt-&gt;vm;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (vm)</div><div class='hunk'>@@ -1741,7 +1744,7 @@ int i915_gem_context_open(struct drm_i915_private *i915,</div><div class='ctx'> 	/* 0 reserved for invalid/unassigned ppgtt */</div><div class='ctx'> 	xa_init_flags(&amp;file_priv-&gt;vm_xa, XA_FLAGS_ALLOC1);</div><div class='ctx'> </div><div class='del'>-	pc = proto_context_create(i915, 0);</div><div class='add'>+	pc = proto_context_create(file_priv, i915, 0);</div><div class='ctx'> 	if (IS_ERR(pc)) {</div><div class='ctx'> 		err = PTR_ERR(pc);</div><div class='ctx'> 		goto err;</div><div class='hunk'>@@ -1823,6 +1826,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> </div><div class='ctx'> 	GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */</div><div class='ctx'> 	args-&gt;vm_id = id;</div><div class='add'>+	ppgtt-&gt;vm.fpriv = file_priv;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_put:</div><div class='hunk'>@@ -2285,7 +2289,8 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ext_data.pc = proto_context_create(i915, args-&gt;flags);</div><div class='add'>+	ext_data.pc = proto_context_create(file-&gt;driver_priv, i915,</div><div class='add'>+					   args-&gt;flags);</div><div class='ctx'> 	if (IS_ERR(ext_data.pc))</div><div class='ctx'> 		return PTR_ERR(ext_data.pc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h<br/>index cb78214a7dcd..03bc7f9d191b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_context_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_context_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_context_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_context_types.h</a></div><div class='hunk'>@@ -188,6 +188,9 @@ struct i915_gem_proto_engine {</div><div class='ctx'>  * CONTEXT_CREATE_SET_PARAM during GEM_CONTEXT_CREATE.</div><div class='ctx'>  */</div><div class='ctx'> struct i915_gem_proto_context {</div><div class='add'>+	/** @fpriv: Client which creates the context */</div><div class='add'>+	struct drm_i915_file_private *fpriv;</div><div class='add'>+</div><div class='ctx'> 	/** @vm: See &amp;i915_gem_context.vm */</div><div class='ctx'> 	struct i915_address_space *vm;</div><div class='ctx'> </div><div class='hunk'>@@ -409,9 +412,9 @@ struct i915_gem_context {</div><div class='ctx'> </div><div class='ctx'> 	/** @stale: tracks stale engines to be destroyed */</div><div class='ctx'> 	struct {</div><div class='del'>-		/** @lock: guards engines */</div><div class='add'>+		/** @stale.lock: guards engines */</div><div class='ctx'> 		spinlock_t lock;</div><div class='del'>-		/** @engines: list of stale engines */</div><div class='add'>+		/** @stale.engines: list of stale engines */</div><div class='ctx'> 		struct list_head engines;</div><div class='ctx'> 	} stale;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c<br/>index ccc077b74d2d..555022c0652c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c</a></div><div class='hunk'>@@ -254,6 +254,8 @@ struct i915_execbuffer {</div><div class='ctx'> 	struct intel_gt *gt; /* gt for the execbuf */</div><div class='ctx'> 	struct intel_context *context; /* logical state for the request */</div><div class='ctx'> 	struct i915_gem_context *gem_context; /** caller's context */</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='add'>+	intel_wakeref_t wakeref_gt0;</div><div class='ctx'> </div><div class='ctx'> 	/** our requests to build */</div><div class='ctx'> 	struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];</div><div class='hunk'>@@ -1157,7 +1159,7 @@ static void reloc_cache_unmap(struct reloc_cache *cache)</div><div class='ctx'> </div><div class='ctx'> 	vaddr = unmask_page(cache-&gt;vaddr);</div><div class='ctx'> 	if (cache-&gt;vaddr &amp; KMAP)</div><div class='del'>-		kunmap_atomic(vaddr);</div><div class='add'>+		kunmap_local(vaddr);</div><div class='ctx'> 	else</div><div class='ctx'> 		io_mapping_unmap_atomic((void __iomem *)vaddr);</div><div class='ctx'> }</div><div class='hunk'>@@ -1173,7 +1175,7 @@ static void reloc_cache_remap(struct reloc_cache *cache,</div><div class='ctx'> 	if (cache-&gt;vaddr &amp; KMAP) {</div><div class='ctx'> 		struct page *page = i915_gem_object_get_page(obj, cache-&gt;page);</div><div class='ctx'> </div><div class='del'>-		vaddr = kmap_atomic(page);</div><div class='add'>+		vaddr = kmap_local_page(page);</div><div class='ctx'> 		cache-&gt;vaddr = unmask_flags(cache-&gt;vaddr) |</div><div class='ctx'> 			(unsigned long)vaddr;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1203,7 +1205,7 @@ static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer</div><div class='ctx'> 		if (cache-&gt;vaddr &amp; CLFLUSH_AFTER)</div><div class='ctx'> 			mb();</div><div class='ctx'> </div><div class='del'>-		kunmap_atomic(vaddr);</div><div class='add'>+		kunmap_local(vaddr);</div><div class='ctx'> 		i915_gem_object_finish_access(obj);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		struct i915_ggtt *ggtt = cache_to_ggtt(cache);</div><div class='hunk'>@@ -1235,7 +1237,7 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,</div><div class='ctx'> 	struct page *page;</div><div class='ctx'> </div><div class='ctx'> 	if (cache-&gt;vaddr) {</div><div class='del'>-		kunmap_atomic(unmask_page(cache-&gt;vaddr));</div><div class='add'>+		kunmap_local(unmask_page(cache-&gt;vaddr));</div><div class='ctx'> 	} else {</div><div class='ctx'> 		unsigned int flushes;</div><div class='ctx'> 		int err;</div><div class='hunk'>@@ -1257,7 +1259,7 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,</div><div class='ctx'> 	if (!obj-&gt;mm.dirty)</div><div class='ctx'> 		set_page_dirty(page);</div><div class='ctx'> </div><div class='del'>-	vaddr = kmap_atomic(page);</div><div class='add'>+	vaddr = kmap_local_page(page);</div><div class='ctx'> 	cache-&gt;vaddr = unmask_flags(cache-&gt;vaddr) | (unsigned long)vaddr;</div><div class='ctx'> 	cache-&gt;page = pageno;</div><div class='ctx'> </div><div class='hunk'>@@ -1679,7 +1681,7 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb)</div><div class='ctx'> 		urelocs = u64_to_user_ptr(eb-&gt;exec[i].relocs_ptr);</div><div class='ctx'> 		size = nreloc * sizeof(*relocs);</div><div class='ctx'> </div><div class='del'>-		relocs = kvmalloc_array(size, 1, GFP_KERNEL);</div><div class='add'>+		relocs = kvmalloc_array(1, size, GFP_KERNEL);</div><div class='ctx'> 		if (!relocs) {</div><div class='ctx'> 			err = -ENOMEM;</div><div class='ctx'> 			goto err;</div><div class='hunk'>@@ -2720,13 +2722,13 @@ eb_select_engine(struct i915_execbuffer *eb)</div><div class='ctx'> </div><div class='ctx'> 	for_each_child(ce, child)</div><div class='ctx'> 		intel_context_get(child);</div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	eb-&gt;wakeref = intel_gt_pm_get(ce-&gt;engine-&gt;gt);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Keep GT0 active on MTL so that i915_vma_parked() doesn't</div><div class='ctx'> 	 * free VMAs while execbuf ioctl is validating VMAs.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (gt-&gt;info.id)</div><div class='del'>-		intel_gt_pm_get(to_gt(gt-&gt;i915));</div><div class='add'>+		eb-&gt;wakeref_gt0 = intel_gt_pm_get(to_gt(gt-&gt;i915));</div><div class='ctx'> </div><div class='ctx'> 	if (!test_bit(CONTEXT_ALLOC_BIT, &amp;ce-&gt;flags)) {</div><div class='ctx'> 		err = intel_context_alloc_state(ce);</div><div class='hunk'>@@ -2766,9 +2768,9 @@ eb_select_engine(struct i915_execbuffer *eb)</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='ctx'> 	if (gt-&gt;info.id)</div><div class='del'>-		intel_gt_pm_put(to_gt(gt-&gt;i915));</div><div class='add'>+		intel_gt_pm_put(to_gt(gt-&gt;i915), eb-&gt;wakeref_gt0);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(ce-&gt;engine-&gt;gt, eb-&gt;wakeref);</div><div class='ctx'> 	for_each_child(ce, child)</div><div class='ctx'> 		intel_context_put(child);</div><div class='ctx'> 	intel_context_put(ce);</div><div class='hunk'>@@ -2786,8 +2788,8 @@ eb_put_engine(struct i915_execbuffer *eb)</div><div class='ctx'> 	 * i915_vma_parked() from interfering while execbuf validates vmas.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (eb-&gt;gt-&gt;info.id)</div><div class='del'>-		intel_gt_pm_put(to_gt(eb-&gt;gt-&gt;i915));</div><div class='del'>-	intel_gt_pm_put(eb-&gt;gt);</div><div class='add'>+		intel_gt_pm_put(to_gt(eb-&gt;gt-&gt;i915), eb-&gt;wakeref_gt0);</div><div class='add'>+	intel_gt_pm_put(eb-&gt;context-&gt;engine-&gt;gt, eb-&gt;wakeref);</div><div class='ctx'> 	for_each_child(eb-&gt;context, child)</div><div class='ctx'> 		intel_context_put(child);</div><div class='ctx'> 	intel_context_put(eb-&gt;context);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c b/drivers/gpu/drm/i915/gem/i915_gem_internal.c<br/>index 6bc26b4b06b8..ea7561ae6e13 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_internal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_internal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_internal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_internal.c</a></div><div class='hunk'>@@ -36,7 +36,7 @@ static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	struct sg_table *st;</div><div class='ctx'> 	struct scatterlist *sg;</div><div class='ctx'> 	unsigned int npages; /* restricted by sg_alloc_table */</div><div class='del'>-	int max_order = MAX_ORDER;</div><div class='add'>+	int max_order = MAX_PAGE_ORDER;</div><div class='ctx'> 	unsigned int max_segment;</div><div class='ctx'> 	gfp_t gfp;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c<br/>index c26d87555825..58e6c680fe0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_object.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_object.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_object.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_object.c</a></div><div class='hunk'>@@ -106,6 +106,10 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;obj-&gt;mm.link);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	INIT_LIST_HEAD(&amp;obj-&gt;client_link);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;obj-&gt;lut_list);</div><div class='ctx'> 	spin_lock_init(&amp;obj-&gt;lut_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -293,6 +297,10 @@ void __i915_gem_free_object_rcu(struct rcu_head *head)</div><div class='ctx'> 		container_of(head, typeof(*obj), rcu);</div><div class='ctx'> 	struct drm_i915_private *i915 = to_i915(obj-&gt;base.dev);</div><div class='ctx'> </div><div class='add'>+	/* We need to keep this alive for RCU read access from fdinfo. */</div><div class='add'>+	if (obj-&gt;mm.n_placements &gt; 1)</div><div class='add'>+		kfree(obj-&gt;mm.placements);</div><div class='add'>+</div><div class='ctx'> 	i915_gem_object_free(obj);</div><div class='ctx'> </div><div class='ctx'> 	GEM_BUG_ON(!atomic_read(&amp;i915-&gt;mm.free_count));</div><div class='hunk'>@@ -389,9 +397,6 @@ void __i915_gem_free_object(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	if (obj-&gt;ops-&gt;release)</div><div class='ctx'> 		obj-&gt;ops-&gt;release(obj);</div><div class='ctx'> </div><div class='del'>-	if (obj-&gt;mm.n_placements &gt; 1)</div><div class='del'>-		kfree(obj-&gt;mm.placements);</div><div class='del'>-</div><div class='ctx'> 	if (obj-&gt;shares_resv_from)</div><div class='ctx'> 		i915_vm_resv_put(obj-&gt;shares_resv_from);</div><div class='ctx'> </div><div class='hunk'>@@ -442,6 +447,8 @@ static void i915_gem_free_object(struct drm_gem_object *gem_obj)</div><div class='ctx'> </div><div class='ctx'> 	GEM_BUG_ON(i915_gem_object_is_framebuffer(obj));</div><div class='ctx'> </div><div class='add'>+	i915_drm_client_remove_object(obj);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Before we free the object, make sure any pure RCU-only</div><div class='ctx'> 	 * read-side critical sections are complete, e.g.</div><div class='hunk'>@@ -493,17 +500,15 @@ static void</div><div class='ctx'> i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size)</div><div class='ctx'> {</div><div class='ctx'> 	pgoff_t idx = offset &gt;&gt; PAGE_SHIFT;</div><div class='del'>-	void *src_map;</div><div class='ctx'> 	void *src_ptr;</div><div class='ctx'> </div><div class='del'>-	src_map = kmap_atomic(i915_gem_object_get_page(obj, idx));</div><div class='del'>-</div><div class='del'>-	src_ptr = src_map + offset_in_page(offset);</div><div class='add'>+	src_ptr = kmap_local_page(i915_gem_object_get_page(obj, idx))</div><div class='add'>+	          + offset_in_page(offset);</div><div class='ctx'> 	if (!(obj-&gt;cache_coherent &amp; I915_BO_CACHE_COHERENT_FOR_READ))</div><div class='ctx'> 		drm_clflush_virt_range(src_ptr, size);</div><div class='ctx'> 	memcpy(dst, src_ptr, size);</div><div class='ctx'> </div><div class='del'>-	kunmap_atomic(src_map);</div><div class='add'>+	kunmap_local(src_ptr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h<br/>index 2292404007c8..0c5cdab278b6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_object_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_object_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_object_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_object_types.h</a></div><div class='hunk'>@@ -302,6 +302,18 @@ struct drm_i915_gem_object {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct i915_address_space *shares_resv_from;</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	/**</div><div class='add'>+	 * @client: @i915_drm_client which created the object</div><div class='add'>+	 */</div><div class='add'>+	struct i915_drm_client *client;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @client_link: Link into @i915_drm_client.objects_list</div><div class='add'>+	 */</div><div class='add'>+	struct list_head client_link;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct rcu_head rcu;</div><div class='ctx'> 		struct llist_node freed;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c<br/>index 5df128e2f4dc..ef85c6dc9fd5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_phys.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_phys.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_phys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_phys.c</a></div><div class='hunk'>@@ -65,16 +65,13 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	dst = vaddr;</div><div class='ctx'> 	for (i = 0; i &lt; obj-&gt;base.size / PAGE_SIZE; i++) {</div><div class='ctx'> 		struct page *page;</div><div class='del'>-		void *src;</div><div class='ctx'> </div><div class='ctx'> 		page = shmem_read_mapping_page(mapping, i);</div><div class='ctx'> 		if (IS_ERR(page))</div><div class='ctx'> 			goto err_st;</div><div class='ctx'> </div><div class='del'>-		src = kmap_atomic(page);</div><div class='del'>-		memcpy(dst, src, PAGE_SIZE);</div><div class='add'>+		memcpy_from_page(dst, page, 0, PAGE_SIZE);</div><div class='ctx'> 		drm_clflush_virt_range(dst, PAGE_SIZE);</div><div class='del'>-		kunmap_atomic(src);</div><div class='ctx'> </div><div class='ctx'> 		put_page(page);</div><div class='ctx'> 		dst += PAGE_SIZE;</div><div class='hunk'>@@ -113,16 +110,13 @@ i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; obj-&gt;base.size / PAGE_SIZE; i++) {</div><div class='ctx'> 			struct page *page;</div><div class='del'>-			char *dst;</div><div class='ctx'> </div><div class='ctx'> 			page = shmem_read_mapping_page(mapping, i);</div><div class='ctx'> 			if (IS_ERR(page))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			dst = kmap_atomic(page);</div><div class='ctx'> 			drm_clflush_virt_range(src, PAGE_SIZE);</div><div class='del'>-			memcpy(dst, src, PAGE_SIZE);</div><div class='del'>-			kunmap_atomic(dst);</div><div class='add'>+			memcpy_to_page(page, 0, src, PAGE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 			set_page_dirty(page);</div><div class='ctx'> 			if (obj-&gt;mm.madv == I915_MADV_WILLNEED)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c<br/>index 73a4a4eb29e0..38b72d86560f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_shmem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_shmem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_shmem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_shmem.c</a></div><div class='hunk'>@@ -485,11 +485,13 @@ shmem_pwrite(struct drm_i915_gem_object *obj,</div><div class='ctx'> 		if (err &lt; 0)</div><div class='ctx'> 			return err;</div><div class='ctx'> </div><div class='del'>-		vaddr = kmap_atomic(page);</div><div class='add'>+		vaddr = kmap_local_page(page);</div><div class='add'>+		pagefault_disable();</div><div class='ctx'> 		unwritten = __copy_from_user_inatomic(vaddr + pg,</div><div class='ctx'> 						      user_data,</div><div class='ctx'> 						      len);</div><div class='del'>-		kunmap_atomic(vaddr);</div><div class='add'>+		pagefault_enable();</div><div class='add'>+		kunmap_local(vaddr);</div><div class='ctx'> </div><div class='ctx'> 		err = aops-&gt;write_end(obj-&gt;base.filp, mapping, offset, len,</div><div class='ctx'> 				      len - unwritten, page, data);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c<br/>index 1a766d8e7cce..8c88075eeab2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_stolen.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/i915_gem_stolen.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/i915_gem_stolen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/i915_gem_stolen.c</a></div><div class='hunk'>@@ -386,6 +386,27 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg(&amp;i915-&gt;drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);</div><div class='ctx'> </div><div class='add'>+	/* Wa_14019821291 */</div><div class='add'>+	if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {</div><div class='add'>+		/*</div><div class='add'>+		 * This workaround is primarily implemented by the BIOS.  We</div><div class='add'>+		 * just need to figure out whether the BIOS has applied the</div><div class='add'>+		 * workaround (meaning the programmed address falls within</div><div class='add'>+		 * the DSM) and, if so, reserve that part of the DSM to</div><div class='add'>+		 * prevent accidental reuse.  The DSM location should be just</div><div class='add'>+		 * below the WOPCM.</div><div class='add'>+		 */</div><div class='add'>+		u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,</div><div class='add'>+							    MTL_GSCPSMI_BASEADDR_LSB,</div><div class='add'>+							    MTL_GSCPSMI_BASEADDR_MSB);</div><div class='add'>+		if (gscpsmi_base &gt;= i915-&gt;dsm.stolen.start &amp;&amp;</div><div class='add'>+		    gscpsmi_base &lt; i915-&gt;dsm.stolen.end) {</div><div class='add'>+			*base = gscpsmi_base;</div><div class='add'>+			*size = i915-&gt;dsm.stolen.end - gscpsmi_base;</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	switch (reg_val &amp; GEN8_STOLEN_RESERVED_SIZE_MASK) {</div><div class='ctx'> 	case GEN8_STOLEN_RESERVED_1M:</div><div class='ctx'> 		*size = 1024 * 1024;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c<br/>index 6b9f6cf50bf6..3ff3d8889c6c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/huge_pages.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/huge_pages.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/huge_pages.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/huge_pages.c</a></div><div class='hunk'>@@ -115,7 +115,7 @@ static int get_huge_pages(struct drm_i915_gem_object *obj)</div><div class='ctx'> 		do {</div><div class='ctx'> 			struct page *page;</div><div class='ctx'> </div><div class='del'>-			GEM_BUG_ON(order &gt; MAX_ORDER);</div><div class='add'>+			GEM_BUG_ON(order &gt; MAX_PAGE_ORDER);</div><div class='ctx'> 			page = alloc_pages(GFP | __GFP_ZERO, order);</div><div class='ctx'> 			if (!page)</div><div class='ctx'> 				goto err;</div><div class='hunk'>@@ -1082,7 +1082,7 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> </div><div class='ctx'> 	for (n = 0; n &lt; obj-&gt;base.size &gt;&gt; PAGE_SHIFT; ++n) {</div><div class='del'>-		u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n));</div><div class='add'>+		u32 *ptr = kmap_local_page(i915_gem_object_get_page(obj, n));</div><div class='ctx'> </div><div class='ctx'> 		if (needs_flush &amp; CLFLUSH_BEFORE)</div><div class='ctx'> 			drm_clflush_virt_range(ptr, PAGE_SIZE);</div><div class='hunk'>@@ -1090,12 +1090,12 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)</div><div class='ctx'> 		if (ptr[dword] != val) {</div><div class='ctx'> 			pr_err("n=%lu ptr[%u]=%u, val=%u\n",</div><div class='ctx'> 			       n, dword, ptr[dword], val);</div><div class='del'>-			kunmap_atomic(ptr);</div><div class='add'>+			kunmap_local(ptr);</div><div class='ctx'> 			err = -EINVAL;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		kunmap_atomic(ptr);</div><div class='add'>+		kunmap_local(ptr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	i915_gem_object_finish_access(obj);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c<br/>index 3bef1beec7cb..2a0c0634d446 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c</a></div><div class='hunk'>@@ -24,7 +24,6 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int needs_clflush;</div><div class='ctx'> 	struct page *page;</div><div class='del'>-	void *map;</div><div class='ctx'> 	u32 *cpu;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -34,8 +33,7 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	page = i915_gem_object_get_page(ctx-&gt;obj, offset &gt;&gt; PAGE_SHIFT);</div><div class='del'>-	map = kmap_atomic(page);</div><div class='del'>-	cpu = map + offset_in_page(offset);</div><div class='add'>+	cpu = kmap_local_page(page) + offset_in_page(offset);</div><div class='ctx'> </div><div class='ctx'> 	if (needs_clflush &amp; CLFLUSH_BEFORE)</div><div class='ctx'> 		drm_clflush_virt_range(cpu, sizeof(*cpu));</div><div class='hunk'>@@ -45,7 +43,7 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> 	if (needs_clflush &amp; CLFLUSH_AFTER)</div><div class='ctx'> 		drm_clflush_virt_range(cpu, sizeof(*cpu));</div><div class='ctx'> </div><div class='del'>-	kunmap_atomic(map);</div><div class='add'>+	kunmap_local(cpu);</div><div class='ctx'> 	i915_gem_object_finish_access(ctx-&gt;obj);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -57,7 +55,6 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int needs_clflush;</div><div class='ctx'> 	struct page *page;</div><div class='del'>-	void *map;</div><div class='ctx'> 	u32 *cpu;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -67,15 +64,14 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	page = i915_gem_object_get_page(ctx-&gt;obj, offset &gt;&gt; PAGE_SHIFT);</div><div class='del'>-	map = kmap_atomic(page);</div><div class='del'>-	cpu = map + offset_in_page(offset);</div><div class='add'>+	cpu = kmap_local_page(page) + offset_in_page(offset);</div><div class='ctx'> </div><div class='ctx'> 	if (needs_clflush &amp; CLFLUSH_BEFORE)</div><div class='ctx'> 		drm_clflush_virt_range(cpu, sizeof(*cpu));</div><div class='ctx'> </div><div class='ctx'> 	*v = *cpu;</div><div class='ctx'> </div><div class='del'>-	kunmap_atomic(map);</div><div class='add'>+	kunmap_local(cpu);</div><div class='ctx'> 	i915_gem_object_finish_access(ctx-&gt;obj);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -85,6 +81,7 @@ out:</div><div class='ctx'> </div><div class='ctx'> static int gtt_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	struct i915_vma *vma;</div><div class='ctx'> 	u32 __iomem *map;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -99,7 +96,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> 	if (IS_ERR(vma))</div><div class='ctx'> 		return PTR_ERR(vma);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='ctx'> </div><div class='ctx'> 	map = i915_vma_pin_iomap(vma);</div><div class='ctx'> 	i915_vma_unpin(vma);</div><div class='hunk'>@@ -112,12 +109,13 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v)</div><div class='ctx'> 	i915_vma_unpin_iomap(vma);</div><div class='ctx'> </div><div class='ctx'> out_rpm:</div><div class='del'>-	intel_gt_pm_put(vma-&gt;vm-&gt;gt);</div><div class='add'>+	intel_gt_pm_put(vma-&gt;vm-&gt;gt, wakeref);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	struct i915_vma *vma;</div><div class='ctx'> 	u32 __iomem *map;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -132,7 +130,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)</div><div class='ctx'> 	if (IS_ERR(vma))</div><div class='ctx'> 		return PTR_ERR(vma);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='ctx'> </div><div class='ctx'> 	map = i915_vma_pin_iomap(vma);</div><div class='ctx'> 	i915_vma_unpin(vma);</div><div class='hunk'>@@ -145,7 +143,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)</div><div class='ctx'> 	i915_vma_unpin_iomap(vma);</div><div class='ctx'> </div><div class='ctx'> out_rpm:</div><div class='del'>-	intel_gt_pm_put(vma-&gt;vm-&gt;gt);</div><div class='add'>+	intel_gt_pm_put(vma-&gt;vm-&gt;gt, wakeref);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c<br/>index 7021b6e9b219..89d4dc8b60c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c</a></div><div class='hunk'>@@ -489,12 +489,12 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value)</div><div class='ctx'> 	for (n = 0; n &lt; real_page_count(obj); n++) {</div><div class='ctx'> 		u32 *map;</div><div class='ctx'> </div><div class='del'>-		map = kmap_atomic(i915_gem_object_get_page(obj, n));</div><div class='add'>+		map = kmap_local_page(i915_gem_object_get_page(obj, n));</div><div class='ctx'> 		for (m = 0; m &lt; DW_PER_PAGE; m++)</div><div class='ctx'> 			map[m] = value;</div><div class='ctx'> 		if (!has_llc)</div><div class='ctx'> 			drm_clflush_virt_range(map, PAGE_SIZE);</div><div class='del'>-		kunmap_atomic(map);</div><div class='add'>+		kunmap_local(map);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	i915_gem_object_finish_access(obj);</div><div class='hunk'>@@ -520,7 +520,7 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj,</div><div class='ctx'> 	for (n = 0; n &lt; real_page_count(obj); n++) {</div><div class='ctx'> 		u32 *map, m;</div><div class='ctx'> </div><div class='del'>-		map = kmap_atomic(i915_gem_object_get_page(obj, n));</div><div class='add'>+		map = kmap_local_page(i915_gem_object_get_page(obj, n));</div><div class='ctx'> 		if (needs_flush &amp; CLFLUSH_BEFORE)</div><div class='ctx'> 			drm_clflush_virt_range(map, PAGE_SIZE);</div><div class='ctx'> </div><div class='hunk'>@@ -546,7 +546,7 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> out_unmap:</div><div class='del'>-		kunmap_atomic(map);</div><div class='add'>+		kunmap_local(map);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c<br/>index e57f9390076c..d684a70f2c04 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c</a></div><div class='hunk'>@@ -504,7 +504,7 @@ static int igt_dmabuf_export_vmap(void *arg)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (memchr_inv(ptr, 0, dmabuf-&gt;size)) {</div><div class='del'>-		pr_err("Exported object not initialiased to zero!\n");</div><div class='add'>+		pr_err("Exported object not initialised to zero!\n");</div><div class='ctx'> 		err = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c<br/>index 72957a36a36b..2c51a2c452fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c</a></div><div class='hunk'>@@ -630,14 +630,14 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,</div><div class='ctx'> static void disable_retire_worker(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> 	i915_gem_driver_unregister__shrinker(i915);</div><div class='del'>-	intel_gt_pm_get(to_gt(i915));</div><div class='add'>+	intel_gt_pm_get_untracked(to_gt(i915));</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;to_gt(i915)-&gt;requests.retire_work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void restore_retire_worker(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> 	igt_flush_test(i915);</div><div class='del'>-	intel_gt_pm_put(to_gt(i915));</div><div class='add'>+	intel_gt_pm_put_untracked(to_gt(i915));</div><div class='ctx'> 	i915_gem_driver_register__shrinker(i915);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -778,6 +778,7 @@ err_obj:</div><div class='ctx'> </div><div class='ctx'> static int gtt_set(struct drm_i915_gem_object *obj)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	struct i915_vma *vma;</div><div class='ctx'> 	void __iomem *map;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -786,7 +787,7 @@ static int gtt_set(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	if (IS_ERR(vma))</div><div class='ctx'> 		return PTR_ERR(vma);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='ctx'> 	map = i915_vma_pin_iomap(vma);</div><div class='ctx'> 	i915_vma_unpin(vma);</div><div class='ctx'> 	if (IS_ERR(map)) {</div><div class='hunk'>@@ -798,12 +799,13 @@ static int gtt_set(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	i915_vma_unpin_iomap(vma);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	intel_gt_pm_put(vma-&gt;vm-&gt;gt);</div><div class='add'>+	intel_gt_pm_put(vma-&gt;vm-&gt;gt, wakeref);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gtt_check(struct drm_i915_gem_object *obj)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	struct i915_vma *vma;</div><div class='ctx'> 	void __iomem *map;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -812,7 +814,7 @@ static int gtt_check(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	if (IS_ERR(vma))</div><div class='ctx'> 		return PTR_ERR(vma);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(vma-&gt;vm-&gt;gt);</div><div class='ctx'> 	map = i915_vma_pin_iomap(vma);</div><div class='ctx'> 	i915_vma_unpin(vma);</div><div class='ctx'> 	if (IS_ERR(map)) {</div><div class='hunk'>@@ -828,7 +830,7 @@ static int gtt_check(struct drm_i915_gem_object *obj)</div><div class='ctx'> 	i915_vma_unpin_iomap(vma);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	intel_gt_pm_put(vma-&gt;vm-&gt;gt);</div><div class='add'>+	intel_gt_pm_put(vma-&gt;vm-&gt;gt, wakeref);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c<br/>index e199d7dbb876..2b0327cc47c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/mock_context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gem/selftests/mock_context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gem/selftests/mock_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gem/selftests/mock_context.c</a></div><div class='hunk'>@@ -83,7 +83,7 @@ live_context(struct drm_i915_private *i915, struct file *file)</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 id;</div><div class='ctx'> </div><div class='del'>-	pc = proto_context_create(i915, 0);</div><div class='add'>+	pc = proto_context_create(fpriv, i915, 0);</div><div class='ctx'> 	if (IS_ERR(pc))</div><div class='ctx'> 		return ERR_CAST(pc);</div><div class='ctx'> </div><div class='hunk'>@@ -152,7 +152,7 @@ kernel_context(struct drm_i915_private *i915,</div><div class='ctx'> 	struct i915_gem_context *ctx;</div><div class='ctx'> 	struct i915_gem_proto_context *pc;</div><div class='ctx'> </div><div class='del'>-	pc = proto_context_create(i915, 0);</div><div class='add'>+	pc = proto_context_create(NULL, i915, 0);</div><div class='ctx'> 	if (IS_ERR(pc))</div><div class='ctx'> 		return ERR_CAST(pc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c<br/>index 9895e18df043..fa46d2308b0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/gen8_ppgtt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/gen8_ppgtt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/gen8_ppgtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/gen8_ppgtt.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/log2.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "gem/i915_gem_internal.h"</div><div class='ctx'> #include "gem/i915_gem_lmem.h"</div><div class='ctx'> </div><div class='ctx'> #include "gen8_ppgtt.h"</div><div class='hunk'>@@ -222,6 +223,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)</div><div class='ctx'> {</div><div class='ctx'> 	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);</div><div class='ctx'> </div><div class='add'>+	if (vm-&gt;rsvd.obj)</div><div class='add'>+		i915_gem_object_put(vm-&gt;rsvd.obj);</div><div class='add'>+</div><div class='ctx'> 	if (intel_vgpu_active(vm-&gt;i915))</div><div class='ctx'> 		gen8_ppgtt_notify_vgt(ppgtt, false);</div><div class='ctx'> </div><div class='hunk'>@@ -950,6 +954,41 @@ err_pd:</div><div class='ctx'> 	return ERR_PTR(err);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int gen8_init_rsvd(struct i915_address_space *vm)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = vm-&gt;i915;</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+	struct i915_vma *vma;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* The memory will be used only by GPU. */</div><div class='add'>+	obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,</div><div class='add'>+					  I915_BO_ALLOC_VOLATILE |</div><div class='add'>+					  I915_BO_ALLOC_GPU_ONLY);</div><div class='add'>+	if (IS_ERR(obj))</div><div class='add'>+		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);</div><div class='add'>+	if (IS_ERR(obj))</div><div class='add'>+		return PTR_ERR(obj);</div><div class='add'>+</div><div class='add'>+	vma = i915_vma_instance(obj, vm, NULL);</div><div class='add'>+	if (IS_ERR(vma)) {</div><div class='add'>+		ret = PTR_ERR(vma);</div><div class='add'>+		goto unref;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unref;</div><div class='add'>+</div><div class='add'>+	vm-&gt;rsvd.vma = i915_vma_make_unshrinkable(vma);</div><div class='add'>+	vm-&gt;rsvd.obj = obj;</div><div class='add'>+	vm-&gt;total -= vma-&gt;node.size;</div><div class='add'>+	return 0;</div><div class='add'>+unref:</div><div class='add'>+	i915_gem_object_put(obj);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers</div><div class='ctx'>  * with a net effect resembling a 2-level page table in normal x86 terms. Each</div><div class='hunk'>@@ -1031,6 +1070,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,</div><div class='ctx'> 	if (intel_vgpu_active(gt-&gt;i915))</div><div class='ctx'> 		gen8_ppgtt_notify_vgt(ppgtt, true);</div><div class='ctx'> </div><div class='add'>+	err = gen8_init_rsvd(&amp;ppgtt-&gt;vm);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_put;</div><div class='add'>+</div><div class='ctx'> 	return ppgtt;</div><div class='ctx'> </div><div class='ctx'> err_put:</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c<br/>index ecc990ec1b95..d650beb8ed22 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_breadcrumbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_breadcrumbs.c</a></div><div class='hunk'>@@ -28,11 +28,14 @@ static void irq_disable(struct intel_breadcrumbs *b)</div><div class='ctx'> </div><div class='ctx'> static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Since we are waiting on a request, the GPU should be busy</div><div class='ctx'> 	 * and should have its own rpm reference.</div><div class='ctx'> 	 */</div><div class='del'>-	if (GEM_WARN_ON(!intel_gt_pm_get_if_awake(b-&gt;irq_engine-&gt;gt)))</div><div class='add'>+	wakeref = intel_gt_pm_get_if_awake(b-&gt;irq_engine-&gt;gt);</div><div class='add'>+	if (GEM_WARN_ON(!wakeref))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -41,7 +44,7 @@ static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)</div><div class='ctx'> 	 * which we can add a new waiter and avoid the cost of re-enabling</div><div class='ctx'> 	 * the irq.</div><div class='ctx'> 	 */</div><div class='del'>-	WRITE_ONCE(b-&gt;irq_armed, true);</div><div class='add'>+	WRITE_ONCE(b-&gt;irq_armed, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	/* Requests may have completed before we could enable the interrupt. */</div><div class='ctx'> 	if (!b-&gt;irq_enabled++ &amp;&amp; b-&gt;irq_enable(b))</div><div class='hunk'>@@ -61,12 +64,14 @@ static void intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)</div><div class='ctx'> </div><div class='ctx'> static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)</div><div class='ctx'> {</div><div class='add'>+	intel_wakeref_t wakeref = b-&gt;irq_armed;</div><div class='add'>+</div><div class='ctx'> 	GEM_BUG_ON(!b-&gt;irq_enabled);</div><div class='ctx'> 	if (!--b-&gt;irq_enabled)</div><div class='ctx'> 		b-&gt;irq_disable(b);</div><div class='ctx'> </div><div class='del'>-	WRITE_ONCE(b-&gt;irq_armed, false);</div><div class='del'>-	intel_gt_pm_put_async(b-&gt;irq_engine-&gt;gt);</div><div class='add'>+	WRITE_ONCE(b-&gt;irq_armed, 0);</div><div class='add'>+	intel_gt_pm_put_async(b-&gt;irq_engine-&gt;gt, wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h<br/>index 72dfd3748c4c..bdf09fd67b6e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "intel_engine_types.h"</div><div class='add'>+#include "intel_wakeref.h"</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Rather than have every client wait upon all user interrupts,</div><div class='hunk'>@@ -43,7 +44,7 @@ struct intel_breadcrumbs {</div><div class='ctx'> 	spinlock_t irq_lock; /* protects the interrupt from hardirq context */</div><div class='ctx'> 	struct irq_work irq_work; /* for use from inside irq_lock */</div><div class='ctx'> 	unsigned int irq_enabled;</div><div class='del'>-	bool irq_armed;</div><div class='add'>+	intel_wakeref_t irq_armed;</div><div class='ctx'> </div><div class='ctx'> 	/* Not all breadcrumbs are attached to physical HW */</div><div class='ctx'> 	intel_engine_mask_t	engine_mask;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c<br/>index a53b26178f0a..a2f1245741bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> #include "gem/i915_gem_context.h"</div><div class='ctx'> #include "gem/i915_gem_pm.h"</div><div class='ctx'> </div><div class='add'>+#include "i915_drm_client.h"</div><div class='ctx'> #include "i915_drv.h"</div><div class='ctx'> #include "i915_trace.h"</div><div class='ctx'> </div><div class='hunk'>@@ -50,6 +51,7 @@ intel_context_create(struct intel_engine_cs *engine)</div><div class='ctx'> </div><div class='ctx'> int intel_context_alloc_state(struct intel_context *ce)</div><div class='ctx'> {</div><div class='add'>+	struct i915_gem_context *ctx;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (mutex_lock_interruptible(&amp;ce-&gt;pin_mutex))</div><div class='hunk'>@@ -66,6 +68,18 @@ int intel_context_alloc_state(struct intel_context *ce)</div><div class='ctx'> 			goto unlock;</div><div class='ctx'> </div><div class='ctx'> 		set_bit(CONTEXT_ALLOC_BIT, &amp;ce-&gt;flags);</div><div class='add'>+</div><div class='add'>+		rcu_read_lock();</div><div class='add'>+		ctx = rcu_dereference(ce-&gt;gem_context);</div><div class='add'>+		if (ctx &amp;&amp; !kref_get_unless_zero(&amp;ctx-&gt;ref))</div><div class='add'>+			ctx = NULL;</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+		if (ctx) {</div><div class='add'>+			if (ctx-&gt;client)</div><div class='add'>+				i915_drm_client_add_context_objects(ctx-&gt;client,</div><div class='add'>+								    ce);</div><div class='add'>+			i915_gem_context_put(ctx);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> unlock:</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h<br/>index a80e3b7c24ff..25564c01507e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_context.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context.h</a></div><div class='hunk'>@@ -212,7 +212,7 @@ static inline void intel_context_enter(struct intel_context *ce)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	ce-&gt;ops-&gt;enter(ce);</div><div class='del'>-	intel_gt_pm_get(ce-&gt;vm-&gt;gt);</div><div class='add'>+	ce-&gt;wakeref = intel_gt_pm_get(ce-&gt;vm-&gt;gt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void intel_context_mark_active(struct intel_context *ce)</div><div class='hunk'>@@ -229,7 +229,7 @@ static inline void intel_context_exit(struct intel_context *ce)</div><div class='ctx'> 	if (--ce-&gt;active_count)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_put_async(ce-&gt;vm-&gt;gt);</div><div class='add'>+	intel_gt_pm_put_async(ce-&gt;vm-&gt;gt, ce-&gt;wakeref);</div><div class='ctx'> 	ce-&gt;ops-&gt;exit(ce);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h<br/>index aceaac28a33e..7eccbd70d89f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_context_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_context_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_context_types.h</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> #include "i915_utils.h"</div><div class='ctx'> #include "intel_engine_types.h"</div><div class='ctx'> #include "intel_sseu.h"</div><div class='add'>+#include "intel_wakeref.h"</div><div class='ctx'> </div><div class='ctx'> #include "uc/intel_guc_fwif.h"</div><div class='ctx'> </div><div class='hunk'>@@ -112,6 +113,7 @@ struct intel_context {</div><div class='ctx'> 	u32 ring_size;</div><div class='ctx'> 	struct intel_ring *ring;</div><div class='ctx'> 	struct intel_timeline *timeline;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> #define CONTEXT_BARRIER_BIT		0</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c<br/>index 4a11219e560e..40687806d22a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_cs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_cs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_cs.c</a></div><div class='hunk'>@@ -47,7 +47,7 @@</div><div class='ctx'> #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)</div><div class='ctx'> #define GEN11_LR_CONTEXT_RENDER_SIZE	(14 * PAGE_SIZE)</div><div class='ctx'> </div><div class='del'>-#define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)</div><div class='add'>+#define GEN8_LR_CONTEXT_OTHER_SIZE	(2 * PAGE_SIZE)</div><div class='ctx'> </div><div class='ctx'> #define MAX_MMIO_BASES 3</div><div class='ctx'> struct engine_info {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c<br/>index 9a527e1f5be6..1a8e2b7db013 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c</a></div><div class='hunk'>@@ -188,7 +188,7 @@ static void heartbeat(struct work_struct *wrk)</div><div class='ctx'> 			 * low latency and no jitter] the chance to naturally</div><div class='ctx'> 			 * complete before being preempted.</div><div class='ctx'> 			 */</div><div class='del'>-			attr.priority = 0;</div><div class='add'>+			attr.priority = I915_PRIORITY_NORMAL;</div><div class='ctx'> 			if (rq-&gt;sched.attr.priority &gt;= attr.priority)</div><div class='ctx'> 				attr.priority = I915_PRIORITY_HEARTBEAT;</div><div class='ctx'> 			if (rq-&gt;sched.attr.priority &gt;= attr.priority)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c<br/>index e91fc881dbf1..96bdb93a948d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_pm.c</a></div><div class='hunk'>@@ -63,7 +63,7 @@ static int __engine_unpark(struct intel_wakeref *wf)</div><div class='ctx'> </div><div class='ctx'> 	ENGINE_TRACE(engine, "\n");</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(engine-&gt;gt);</div><div class='add'>+	engine-&gt;wakeref_track = intel_gt_pm_get(engine-&gt;gt);</div><div class='ctx'> </div><div class='ctx'> 	/* Discard stale context state from across idling */</div><div class='ctx'> 	ce = engine-&gt;kernel_context;</div><div class='hunk'>@@ -122,6 +122,7 @@ __queue_and_release_pm(struct i915_request *rq,</div><div class='ctx'> 	 */</div><div class='ctx'> 	GEM_BUG_ON(rq-&gt;context-&gt;active_count != 1);</div><div class='ctx'> 	__intel_gt_pm_get(engine-&gt;gt);</div><div class='add'>+	rq-&gt;context-&gt;wakeref = intel_wakeref_track(&amp;engine-&gt;gt-&gt;wakeref);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We have to serialise all potential retirement paths with our</div><div class='hunk'>@@ -285,7 +286,7 @@ static int __engine_park(struct intel_wakeref *wf)</div><div class='ctx'> 		engine-&gt;park(engine);</div><div class='ctx'> </div><div class='ctx'> 	/* While gt calls i915_vma_parked(), we have to break the lock cycle */</div><div class='del'>-	intel_gt_pm_put_async(engine-&gt;gt);</div><div class='add'>+	intel_gt_pm_put_async(engine-&gt;gt, engine-&gt;wakeref_track);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -296,7 +297,7 @@ static const struct intel_wakeref_ops wf_ops = {</div><div class='ctx'> </div><div class='ctx'> void intel_engine_init__pm(struct intel_engine_cs *engine)</div><div class='ctx'> {</div><div class='del'>-	intel_wakeref_init(&amp;engine-&gt;wakeref, engine-&gt;i915, &amp;wf_ops);</div><div class='add'>+	intel_wakeref_init(&amp;engine-&gt;wakeref, engine-&gt;i915, &amp;wf_ops, engine-&gt;name);</div><div class='ctx'> 	intel_engine_init_heartbeat(engine);</div><div class='ctx'> </div><div class='ctx'> 	intel_gsc_idle_msg_enable(engine);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h<br/>index fdd4ddd3a978..a8eac59e3779 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_regs.h</a></div><div class='hunk'>@@ -118,9 +118,15 @@</div><div class='ctx'> #define   CCID_EXTENDED_STATE_RESTORE		BIT(2)</div><div class='ctx'> #define   CCID_EXTENDED_STATE_SAVE		BIT(3)</div><div class='ctx'> #define RING_BB_PER_CTX_PTR(base)		_MMIO((base) + 0x1c0) /* gen8+ */</div><div class='add'>+#define   PER_CTX_BB_FORCE			BIT(2)</div><div class='add'>+#define   PER_CTX_BB_VALID			BIT(0)</div><div class='add'>+</div><div class='ctx'> #define RING_INDIRECT_CTX(base)			_MMIO((base) + 0x1c4) /* gen8+ */</div><div class='ctx'> #define RING_INDIRECT_CTX_OFFSET(base)		_MMIO((base) + 0x1c8) /* gen8+ */</div><div class='ctx'> #define ECOSKPD(base)				_MMIO((base) + 0x1d0)</div><div class='add'>+#define   XEHP_BLITTER_SCHEDULING_MODE_MASK	REG_GENMASK(12, 11)</div><div class='add'>+#define   XEHP_BLITTER_ROUND_ROBIN_MODE		\</div><div class='add'>+		REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)</div><div class='ctx'> #define   ECO_CONSTANT_BUFFER_SR_DISABLE	REG_BIT(4)</div><div class='ctx'> #define   ECO_GATING_CX_ONLY			REG_BIT(3)</div><div class='ctx'> #define   GEN6_BLITTER_FBC_NOTIFY		REG_BIT(3)</div><div class='hunk'>@@ -257,5 +263,7 @@</div><div class='ctx'> #define VDBOX_CGCTL3F18(base)			_MMIO((base) + 0x3f18)</div><div class='ctx'> #define   ALNUNIT_CLKGATE_DIS			REG_BIT(13)</div><div class='ctx'> </div><div class='add'>+#define VDBOX_CGCTL3F1C(base)			_MMIO((base) + 0x3f1c)</div><div class='add'>+#define   MFXPIPE_CLKGATE_DIS			REG_BIT(3)</div><div class='ctx'> </div><div class='ctx'> #endif /* __INTEL_ENGINE_REGS__ */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h<br/>index 8769760257fd..960e6be2042f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_types.h</a></div><div class='hunk'>@@ -446,7 +446,9 @@ struct intel_engine_cs {</div><div class='ctx'> 	unsigned long serial;</div><div class='ctx'> </div><div class='ctx'> 	unsigned long wakeref_serial;</div><div class='add'>+	intel_wakeref_t wakeref_track;</div><div class='ctx'> 	struct intel_wakeref wakeref;</div><div class='add'>+</div><div class='ctx'> 	struct file *default_state;</div><div class='ctx'> </div><div class='ctx'> 	struct {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c<br/>index 118164ddbb2e..833987015b8b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_user.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_engine_user.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_engine_user.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_engine_user.c</a></div><div class='hunk'>@@ -41,12 +41,15 @@ void intel_engine_add_user(struct intel_engine_cs *engine)</div><div class='ctx'> 	llist_add(&amp;engine-&gt;uabi_llist, &amp;engine-&gt;i915-&gt;uabi_engines_llist);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const u8 uabi_classes[] = {</div><div class='add'>+#define I915_NO_UABI_CLASS ((u16)(-1))</div><div class='add'>+</div><div class='add'>+static const u16 uabi_classes[] = {</div><div class='ctx'> 	[RENDER_CLASS] = I915_ENGINE_CLASS_RENDER,</div><div class='ctx'> 	[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,</div><div class='ctx'> 	[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,</div><div class='ctx'> 	[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='ctx'> 	[COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,</div><div class='add'>+	[OTHER_CLASS] = I915_NO_UABI_CLASS, /* Not exposed to users, no uabi class. */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int engine_cmp(void *priv, const struct list_head *A,</div><div class='hunk'>@@ -200,6 +203,7 @@ static void engine_rename(struct intel_engine_cs *engine, const char *name, u16</div><div class='ctx'> </div><div class='ctx'> void intel_engines_driver_register(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='add'>+	u16 name_instance, other_instance = 0;</div><div class='ctx'> 	struct legacy_ring ring = {};</div><div class='ctx'> 	struct list_head *it, *next;</div><div class='ctx'> 	struct rb_node **p, *prev;</div><div class='hunk'>@@ -216,27 +220,28 @@ void intel_engines_driver_register(struct drm_i915_private *i915)</div><div class='ctx'> 		if (intel_gt_has_unrecoverable_error(engine-&gt;gt))</div><div class='ctx'> 			continue; /* ignore incomplete engines */</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * We don't want to expose the GSC engine to the users, but we</div><div class='del'>-		 * still rename it so it is easier to identify in the debug logs</div><div class='del'>-		 */</div><div class='del'>-		if (engine-&gt;id == GSC0) {</div><div class='del'>-			engine_rename(engine, "gsc", 0);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='ctx'> 		GEM_BUG_ON(engine-&gt;class &gt;= ARRAY_SIZE(uabi_classes));</div><div class='ctx'> 		engine-&gt;uabi_class = uabi_classes[engine-&gt;class];</div><div class='add'>+		if (engine-&gt;uabi_class == I915_NO_UABI_CLASS) {</div><div class='add'>+			name_instance = other_instance++;</div><div class='add'>+		} else {</div><div class='add'>+			GEM_BUG_ON(engine-&gt;uabi_class &gt;=</div><div class='add'>+				   ARRAY_SIZE(i915-&gt;engine_uabi_class_count));</div><div class='add'>+			name_instance =</div><div class='add'>+				i915-&gt;engine_uabi_class_count[engine-&gt;uabi_class]++;</div><div class='add'>+		}</div><div class='add'>+		engine-&gt;uabi_instance = name_instance;</div><div class='ctx'> </div><div class='del'>-		GEM_BUG_ON(engine-&gt;uabi_class &gt;=</div><div class='del'>-			   ARRAY_SIZE(i915-&gt;engine_uabi_class_count));</div><div class='del'>-		engine-&gt;uabi_instance =</div><div class='del'>-			i915-&gt;engine_uabi_class_count[engine-&gt;uabi_class]++;</div><div class='del'>-</div><div class='del'>-		/* Replace the internal name with the final user facing name */</div><div class='add'>+		/*</div><div class='add'>+		 * Replace the internal name with the final user and log facing</div><div class='add'>+		 * name.</div><div class='add'>+		 */</div><div class='ctx'> 		engine_rename(engine,</div><div class='ctx'> 			      intel_engine_class_repr(engine-&gt;class),</div><div class='del'>-			      engine-&gt;uabi_instance);</div><div class='add'>+			      name_instance);</div><div class='add'>+</div><div class='add'>+		if (engine-&gt;uabi_class == I915_NO_UABI_CLASS)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		rb_link_node(&amp;engine-&gt;uabi_node, prev, p);</div><div class='ctx'> 		rb_insert_color(&amp;engine-&gt;uabi_node, &amp;i915-&gt;uabi_engines);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c<br/>index e8f42ec6b1b4..42aade0faf2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_execlists_submission.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_execlists_submission.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_execlists_submission.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_execlists_submission.c</a></div><div class='hunk'>@@ -630,7 +630,7 @@ static void __execlists_schedule_out(struct i915_request * const rq,</div><div class='ctx'> 	execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);</div><div class='ctx'> 	if (engine-&gt;fw_domain &amp;&amp; !--engine-&gt;fw_active)</div><div class='ctx'> 		intel_uncore_forcewake_put(engine-&gt;uncore, engine-&gt;fw_domain);</div><div class='del'>-	intel_gt_pm_put_async(engine-&gt;gt);</div><div class='add'>+	intel_gt_pm_put_async_untracked(engine-&gt;gt);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If this is part of a virtual engine, its next request may</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c<br/>index 15fc8e4703f4..21a7e3191c18 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_ggtt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_ggtt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_ggtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_ggtt.c</a></div><div class='hunk'>@@ -245,16 +245,15 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)</div><div class='ctx'> 	gen8_ggtt_invalidate(ggtt);</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(gt, &amp;ggtt-&gt;gt_list, ggtt_link) {</div><div class='del'>-		if (intel_guc_tlb_invalidation_is_available(&amp;gt-&gt;uc.guc)) {</div><div class='add'>+		if (intel_guc_tlb_invalidation_is_available(&amp;gt-&gt;uc.guc))</div><div class='ctx'> 			guc_ggtt_ct_invalidate(gt);</div><div class='del'>-		} else if (GRAPHICS_VER(i915) &gt;= 12) {</div><div class='add'>+		else if (GRAPHICS_VER(i915) &gt;= 12)</div><div class='ctx'> 			intel_uncore_write_fw(gt-&gt;uncore,</div><div class='ctx'> 					      GEN12_GUC_TLB_INV_CR,</div><div class='ctx'> 					      GEN12_GUC_TLB_INV_CR_INVALIDATE);</div><div class='del'>-		} else {</div><div class='add'>+		else</div><div class='ctx'> 			intel_uncore_write_fw(gt-&gt;uncore,</div><div class='ctx'> 					      GEN8_GTCR, GEN8_GTCR_INVALIDATE);</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -297,7 +296,7 @@ static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)</div><div class='ctx'> 	return intel_gt_is_bind_context_ready(gt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)</div><div class='add'>+static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt, intel_wakeref_t *wakeref)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_context *ce;</div><div class='ctx'> 	struct intel_gt *gt = ggtt-&gt;vm.gt;</div><div class='hunk'>@@ -314,7 +313,8 @@ static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)</div><div class='ctx'> 	 * would conflict with fs_reclaim trying to allocate memory while</div><div class='ctx'> 	 * doing rpm_resume().</div><div class='ctx'> 	 */</div><div class='del'>-	if (!intel_gt_pm_get_if_awake(gt))</div><div class='add'>+	*wakeref = intel_gt_pm_get_if_awake(gt);</div><div class='add'>+	if (!*wakeref)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	intel_engine_pm_get(ce-&gt;engine);</div><div class='hunk'>@@ -322,10 +322,10 @@ static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)</div><div class='ctx'> 	return ce;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void gen8_ggtt_bind_put_ce(struct intel_context *ce)</div><div class='add'>+static void gen8_ggtt_bind_put_ce(struct intel_context *ce, intel_wakeref_t wakeref)</div><div class='ctx'> {</div><div class='ctx'> 	intel_engine_pm_put(ce-&gt;engine);</div><div class='del'>-	intel_gt_pm_put(ce-&gt;engine-&gt;gt);</div><div class='add'>+	intel_gt_pm_put(ce-&gt;engine-&gt;gt, wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,</div><div class='hunk'>@@ -338,12 +338,13 @@ static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,</div><div class='ctx'> 	struct sgt_iter iter;</div><div class='ctx'> 	struct i915_request *rq;</div><div class='ctx'> 	struct intel_context *ce;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	u32 *cs;</div><div class='ctx'> </div><div class='ctx'> 	if (!num_entries)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='del'>-	ce = gen8_ggtt_bind_get_ce(ggtt);</div><div class='add'>+	ce = gen8_ggtt_bind_get_ce(ggtt, &amp;wakeref);</div><div class='ctx'> 	if (!ce)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='hunk'>@@ -419,13 +420,13 @@ queue_err_rq:</div><div class='ctx'> 		offset += n_ptes;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	gen8_ggtt_bind_put_ce(ce);</div><div class='add'>+	gen8_ggtt_bind_put_ce(ce, wakeref);</div><div class='ctx'> 	return true;</div><div class='ctx'> </div><div class='ctx'> err_rq:</div><div class='ctx'> 	i915_request_put(rq);</div><div class='ctx'> put_ce:</div><div class='del'>-	gen8_ggtt_bind_put_ce(ce);</div><div class='add'>+	gen8_ggtt_bind_put_ce(ce, wakeref);</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h<br/>index 7ab3ca0f9f26..013c64251448 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gsc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gsc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gsc.h</a></div><div class='hunk'>@@ -21,8 +21,11 @@ struct mei_aux_device;</div><div class='ctx'> /**</div><div class='ctx'>  * struct intel_gsc - graphics security controller</div><div class='ctx'>  *</div><div class='del'>- * @gem_obj: scratch memory GSC operations</div><div class='del'>- * @intf : gsc interface</div><div class='add'>+ * @intf: gsc interface</div><div class='add'>+ * @intf.adev: MEI aux. device for this @intf</div><div class='add'>+ * @intf.gem_obj: scratch memory GSC operations</div><div class='add'>+ * @intf.irq: IRQ for this device (%-1 for no IRQ)</div><div class='add'>+ * @intf.id: this interface's id number/index</div><div class='ctx'>  */</div><div class='ctx'> struct intel_gsc {</div><div class='ctx'> 	struct intel_gsc_intf {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c<br/>index ba1186fc524f..a425db5ed3a2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt.c</a></div><div class='hunk'>@@ -451,7 +451,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)</div><div class='ctx'> </div><div class='ctx'> 		spin_lock_irqsave(&amp;uncore-&gt;lock, flags);</div><div class='ctx'> 		intel_uncore_posting_read_fw(uncore,</div><div class='del'>-					     RING_HEAD(RENDER_RING_BASE));</div><div class='add'>+					     RING_TAIL(RENDER_RING_BASE));</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;uncore-&gt;lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h<br/>index e1f13735f530..608f5c872928 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt.h</a></div><div class='hunk'>@@ -82,6 +82,10 @@ struct drm_printer;</div><div class='ctx'> 		  ##__VA_ARGS__);					\</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='add'>+#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \</div><div class='add'>+	IS_GFX_GT_IP_RANGE(engine-&gt;gt, IP_VER(12, 55), IP_VER(12, 71)) &amp;&amp; \</div><div class='add'>+	engine-&gt;class == COPY_ENGINE_CLASS &amp;&amp; engine-&gt;instance == 0)</div><div class='add'>+</div><div class='ctx'> static inline bool gt_is_root(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	return !gt-&gt;info.id;</div><div class='hunk'>@@ -114,6 +118,11 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)</div><div class='ctx'> 	return container_of(gsc, struct intel_gt, gsc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return guc_to_gt(guc)-&gt;i915;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void intel_gt_common_init_early(struct intel_gt *gt);</div><div class='ctx'> int intel_root_gt_init_early(struct drm_i915_private *i915);</div><div class='ctx'> int intel_gt_assign_ggtt(struct intel_gt *gt);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c<br/>index 34913912d8ae..e253750a51c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_mcr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt_mcr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_mcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_mcr.c</a></div><div class='hunk'>@@ -388,8 +388,7 @@ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags)</div><div class='ctx'> 		 * registers.  This wakeref will be released in the unlock</div><div class='ctx'> 		 * routine.</div><div class='ctx'> 		 *</div><div class='del'>-		 * This is expected to become a formally documented/numbered</div><div class='del'>-		 * workaround soon.</div><div class='add'>+		 * Wa_22018931422</div><div class='ctx'> 		 */</div><div class='ctx'> 		intel_uncore_forcewake_get(gt-&gt;uncore, FORCEWAKE_GT);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c<br/>index f5899d503e23..220ac4f92edf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt_pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm.c</a></div><div class='hunk'>@@ -28,19 +28,20 @@</div><div class='ctx'> static void user_forcewake(struct intel_gt *gt, bool suspend)</div><div class='ctx'> {</div><div class='ctx'> 	int count = atomic_read(&amp;gt-&gt;user_wakeref);</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='ctx'> 	/* Inside suspend/resume so single threaded, no races to worry about. */</div><div class='ctx'> 	if (likely(!count))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	if (suspend) {</div><div class='ctx'> 		GEM_BUG_ON(count &gt; atomic_read(&amp;gt-&gt;wakeref.count));</div><div class='ctx'> 		atomic_sub(count, &amp;gt-&gt;wakeref.count);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		atomic_add(count, &amp;gt-&gt;wakeref.count);</div><div class='ctx'> 	}</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void runtime_begin(struct intel_gt *gt)</div><div class='hunk'>@@ -138,7 +139,7 @@ void intel_gt_pm_init_early(struct intel_gt *gt)</div><div class='ctx'> 	 * runtime_pm is per-device rather than per-tile, so this is still the</div><div class='ctx'> 	 * correct structure.</div><div class='ctx'> 	 */</div><div class='del'>-	intel_wakeref_init(&amp;gt-&gt;wakeref, gt-&gt;i915, &amp;wf_ops);</div><div class='add'>+	intel_wakeref_init(&amp;gt-&gt;wakeref, gt-&gt;i915, &amp;wf_ops, "GT");</div><div class='ctx'> 	seqcount_mutex_init(&amp;gt-&gt;stats.lock, &amp;gt-&gt;wakeref.mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -167,7 +168,7 @@ static void gt_sanitize(struct intel_gt *gt, bool force)</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='ctx'> 	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='del'>-	GT_TRACE(gt, "force:%s", str_yes_no(force));</div><div class='add'>+	GT_TRACE(gt, "force:%s\n", str_yes_no(force));</div><div class='ctx'> </div><div class='ctx'> 	/* Use a raw wakeref to avoid calling intel_display_power_get early */</div><div class='ctx'> 	wakeref = intel_runtime_pm_get(gt-&gt;uncore-&gt;rpm);</div><div class='hunk'>@@ -236,6 +237,7 @@ int intel_gt_resume(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = intel_gt_has_unrecoverable_error(gt);</div><div class='hunk'>@@ -252,7 +254,7 @@ int intel_gt_resume(struct intel_gt *gt)</div><div class='ctx'> 	 */</div><div class='ctx'> 	gt_sanitize(gt, true);</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> </div><div class='ctx'> 	intel_uncore_forcewake_get(gt-&gt;uncore, FORCEWAKE_ALL);</div><div class='ctx'> 	intel_rc6_sanitize(&amp;gt-&gt;rc6);</div><div class='hunk'>@@ -295,7 +297,7 @@ int intel_gt_resume(struct intel_gt *gt)</div><div class='ctx'> </div><div class='ctx'> out_fw:</div><div class='ctx'> 	intel_uncore_forcewake_put(gt-&gt;uncore, FORCEWAKE_ALL);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> 	intel_gt_bind_context_set_ready(gt);</div><div class='ctx'> 	return err;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h<br/>index b1eeb5b33918..911fd0160221 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt_pm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm.h</a></div><div class='hunk'>@@ -16,19 +16,28 @@ static inline bool intel_gt_pm_is_awake(const struct intel_gt *gt)</div><div class='ctx'> 	return intel_wakeref_is_active(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void intel_gt_pm_get(struct intel_gt *gt)</div><div class='add'>+static inline void intel_gt_pm_get_untracked(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	intel_wakeref_get(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline intel_wakeref_t intel_gt_pm_get(struct intel_gt *gt)</div><div class='add'>+{</div><div class='add'>+	intel_gt_pm_get_untracked(gt);</div><div class='add'>+	return intel_wakeref_track(&amp;gt-&gt;wakeref);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void __intel_gt_pm_get(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	__intel_wakeref_get(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)</div><div class='add'>+static inline intel_wakeref_t intel_gt_pm_get_if_awake(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='del'>-	return intel_wakeref_get_if_active(&amp;gt-&gt;wakeref);</div><div class='add'>+	if (!intel_wakeref_get_if_active(&amp;gt-&gt;wakeref))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return intel_wakeref_track(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void intel_gt_pm_might_get(struct intel_gt *gt)</div><div class='hunk'>@@ -36,12 +45,18 @@ static inline void intel_gt_pm_might_get(struct intel_gt *gt)</div><div class='ctx'> 	intel_wakeref_might_get(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void intel_gt_pm_put(struct intel_gt *gt)</div><div class='add'>+static inline void intel_gt_pm_put_untracked(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	intel_wakeref_put(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void intel_gt_pm_put_async(struct intel_gt *gt)</div><div class='add'>+static inline void intel_gt_pm_put(struct intel_gt *gt, intel_wakeref_t handle)</div><div class='add'>+{</div><div class='add'>+	intel_wakeref_untrack(&amp;gt-&gt;wakeref, handle);</div><div class='add'>+	intel_gt_pm_put_untracked(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_gt_pm_put_async_untracked(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	intel_wakeref_put_async(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='hunk'>@@ -51,9 +66,14 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)</div><div class='ctx'> 	intel_wakeref_might_put(&amp;gt-&gt;wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define with_intel_gt_pm(gt, tmp) \</div><div class='del'>-	for (tmp = 1, intel_gt_pm_get(gt); tmp; \</div><div class='del'>-	     intel_gt_pm_put(gt), tmp = 0)</div><div class='add'>+static inline void intel_gt_pm_put_async(struct intel_gt *gt, intel_wakeref_t handle)</div><div class='add'>+{</div><div class='add'>+	intel_wakeref_untrack(&amp;gt-&gt;wakeref, handle);</div><div class='add'>+	intel_gt_pm_put_async_untracked(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define with_intel_gt_pm(gt, wf) \</div><div class='add'>+	for (wf = intel_gt_pm_get(gt); wf; intel_gt_pm_put(gt, wf), wf = 0)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * with_intel_gt_pm_if_awake - if GT is PM awake, get a reference to prevent</div><div class='hunk'>@@ -64,7 +84,7 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)</div><div class='ctx'>  * @wf: pointer to a temporary wakeref.</div><div class='ctx'>  */</div><div class='ctx'> #define with_intel_gt_pm_if_awake(gt, wf) \</div><div class='del'>-	for (wf = intel_gt_pm_get_if_awake(gt); wf; intel_gt_pm_put_async(gt), wf = 0)</div><div class='add'>+	for (wf = intel_gt_pm_get_if_awake(gt); wf; intel_gt_pm_put_async(gt, wf), wf = 0)</div><div class='ctx'> </div><div class='ctx'> static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c<br/>index f900cc68d6d9..7114c116e928 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c</a></div><div class='hunk'>@@ -27,7 +27,7 @@</div><div class='ctx'> void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	atomic_inc(&amp;gt-&gt;user_wakeref);</div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	intel_gt_pm_get_untracked(gt);</div><div class='ctx'> 	if (GRAPHICS_VER(gt-&gt;i915) &gt;= 6)</div><div class='ctx'> 		intel_uncore_forcewake_user_get(gt-&gt;uncore);</div><div class='ctx'> }</div><div class='hunk'>@@ -36,7 +36,7 @@ void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='ctx'> 	if (GRAPHICS_VER(gt-&gt;i915) &gt;= 6)</div><div class='ctx'> 		intel_uncore_forcewake_user_put(gt-&gt;uncore);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put_untracked(gt);</div><div class='ctx'> 	atomic_dec(&amp;gt-&gt;user_wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br/>index eecd0a87a647..50962cfd1353 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gt_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gt_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gt_regs.h</a></div><div class='hunk'>@@ -469,6 +469,9 @@</div><div class='ctx'> #define XEHP_PSS_MODE2				MCR_REG(0x703c)</div><div class='ctx'> #define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)</div><div class='ctx'> </div><div class='add'>+#define XEHP_PSS_CHICKEN			MCR_REG(0x7044)</div><div class='add'>+#define   FD_END_COLLECT			REG_BIT(5)</div><div class='add'>+</div><div class='ctx'> #define GEN7_SC_INSTDONE			_MMIO(0x7100)</div><div class='ctx'> #define GEN12_SC_INSTDONE_EXTRA			_MMIO(0x7104)</div><div class='ctx'> #define GEN12_SC_INSTDONE_EXTRA2		_MMIO(0x7108)</div><div class='hunk'>@@ -537,6 +540,9 @@</div><div class='ctx'> #define XEHP_SQCM				MCR_REG(0x8724)</div><div class='ctx'> #define   EN_32B_ACCESS				REG_BIT(30)</div><div class='ctx'> </div><div class='add'>+#define MTL_GSCPSMI_BASEADDR_LSB		_MMIO(0x880c)</div><div class='add'>+#define MTL_GSCPSMI_BASEADDR_MSB		_MMIO(0x8810)</div><div class='add'>+</div><div class='ctx'> #define HSW_IDICR				_MMIO(0x9008)</div><div class='ctx'> #define   IDIHASHMSK(x)				(((x) &amp; 0x3f) &lt;&lt; 16)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c<br/>index 4fbed27ef0ec..86f73fe558ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gtt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gtt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gtt.c</a></div><div class='hunk'>@@ -63,6 +63,9 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)</div><div class='ctx'> 	if (!IS_ERR(obj)) {</div><div class='ctx'> 		obj-&gt;base.resv = i915_vm_resv_get(vm);</div><div class='ctx'> 		obj-&gt;shares_resv_from = vm;</div><div class='add'>+</div><div class='add'>+		if (vm-&gt;fpriv)</div><div class='add'>+			i915_drm_client_add_object(vm-&gt;fpriv-&gt;client, obj);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return obj;</div><div class='hunk'>@@ -84,6 +87,9 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)</div><div class='ctx'> 	if (!IS_ERR(obj)) {</div><div class='ctx'> 		obj-&gt;base.resv = i915_vm_resv_get(vm);</div><div class='ctx'> 		obj-&gt;shares_resv_from = vm;</div><div class='add'>+</div><div class='add'>+		if (vm-&gt;fpriv)</div><div class='add'>+			i915_drm_client_add_object(vm-&gt;fpriv-&gt;client, obj);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return obj;</div><div class='hunk'>@@ -95,6 +101,16 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)</div><div class='ctx'> 	void *vaddr;</div><div class='ctx'> </div><div class='ctx'> 	type = intel_gt_coherent_map_type(vm-&gt;gt, obj, true);</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: It is suspected that some Address Translation Service (ATS)</div><div class='add'>+	 * issue on IOMMU is causing CAT errors to occur on some MTL workloads.</div><div class='add'>+	 * Applying a write barrier to the ppgtt set entry functions appeared</div><div class='add'>+	 * to have no effect, so we must temporarily use I915_MAP_WC here on</div><div class='add'>+	 * MTL until a proper ATS solution is found.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_METEORLAKE(vm-&gt;i915))</div><div class='add'>+		type = I915_MAP_WC;</div><div class='add'>+</div><div class='ctx'> 	vaddr = i915_gem_object_pin_map_unlocked(obj, type);</div><div class='ctx'> 	if (IS_ERR(vaddr))</div><div class='ctx'> 		return PTR_ERR(vaddr);</div><div class='hunk'>@@ -109,6 +125,16 @@ int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object</div><div class='ctx'> 	void *vaddr;</div><div class='ctx'> </div><div class='ctx'> 	type = intel_gt_coherent_map_type(vm-&gt;gt, obj, true);</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: It is suspected that some Address Translation Service (ATS)</div><div class='add'>+	 * issue on IOMMU is causing CAT errors to occur on some MTL workloads.</div><div class='add'>+	 * Applying a write barrier to the ppgtt set entry functions appeared</div><div class='add'>+	 * to have no effect, so we must temporarily use I915_MAP_WC here on</div><div class='add'>+	 * MTL until a proper ATS solution is found.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_METEORLAKE(vm-&gt;i915))</div><div class='add'>+		type = I915_MAP_WC;</div><div class='add'>+</div><div class='ctx'> 	vaddr = i915_gem_object_pin_map(obj, type);</div><div class='ctx'> 	if (IS_ERR(vaddr))</div><div class='ctx'> 		return PTR_ERR(vaddr);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h<br/>index b471edac2699..6b85222ee3ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gtt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_gtt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_gtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_gtt.h</a></div><div class='hunk'>@@ -249,8 +249,13 @@ struct i915_address_space {</div><div class='ctx'> 	struct work_struct release_work;</div><div class='ctx'> </div><div class='ctx'> 	struct drm_mm mm;</div><div class='add'>+	struct {</div><div class='add'>+		struct drm_i915_gem_object *obj;</div><div class='add'>+		struct i915_vma *vma;</div><div class='add'>+	} rsvd;</div><div class='ctx'> 	struct intel_gt *gt;</div><div class='ctx'> 	struct drm_i915_private *i915;</div><div class='add'>+	struct drm_i915_file_private *fpriv;</div><div class='ctx'> 	struct device *dma;</div><div class='ctx'> 	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */</div><div class='ctx'> 	u64 reserved;		/* size addr space reserved */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c<br/>index eaf66d903166..7c367ba8d9dc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_lrc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_lrc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_lrc.c</a></div><div class='hunk'>@@ -829,6 +829,18 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='add'>+lrc_setup_bb_per_ctx(u32 *regs,</div><div class='add'>+		     const struct intel_engine_cs *engine,</div><div class='add'>+		     u32 ctx_bb_ggtt_addr)</div><div class='add'>+{</div><div class='add'>+	GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);</div><div class='add'>+	regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =</div><div class='add'>+		ctx_bb_ggtt_addr |</div><div class='add'>+		PER_CTX_BB_FORCE |</div><div class='add'>+		PER_CTX_BB_VALID;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='ctx'> lrc_setup_indirect_ctx(u32 *regs,</div><div class='ctx'> 		       const struct intel_engine_cs *engine,</div><div class='ctx'> 		       u32 ctx_bb_ggtt_addr,</div><div class='hunk'>@@ -1020,7 +1032,13 @@ static u32 context_wa_bb_offset(const struct intel_context *ce)</div><div class='ctx'> 	return PAGE_SIZE * ce-&gt;wa_bb_page;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 *context_indirect_bb(const struct intel_context *ce)</div><div class='add'>+/*</div><div class='add'>+ * per_ctx below determines which WABB section is used.</div><div class='add'>+ * When true, the function returns the location of the</div><div class='add'>+ * PER_CTX_BB.  When false, the function returns the</div><div class='add'>+ * location of the INDIRECT_CTX.</div><div class='add'>+ */</div><div class='add'>+static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	void *ptr;</div><div class='ctx'> </div><div class='hunk'>@@ -1029,6 +1047,7 @@ static u32 *context_indirect_bb(const struct intel_context *ce)</div><div class='ctx'> 	ptr = ce-&gt;lrc_reg_state;</div><div class='ctx'> 	ptr -= LRC_STATE_OFFSET; /* back to start of context image */</div><div class='ctx'> 	ptr += context_wa_bb_offset(ce);</div><div class='add'>+	ptr += per_ctx ? PAGE_SIZE : 0;</div><div class='ctx'> </div><div class='ctx'> 	return ptr;</div><div class='ctx'> }</div><div class='hunk'>@@ -1105,7 +1124,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)</div><div class='ctx'> </div><div class='ctx'> 	if (GRAPHICS_VER(engine-&gt;i915) &gt;= 12) {</div><div class='ctx'> 		ce-&gt;wa_bb_page = context_size / PAGE_SIZE;</div><div class='del'>-		context_size += PAGE_SIZE;</div><div class='add'>+		/* INDIRECT_CTX and PER_CTX_BB need separate pages. */</div><div class='add'>+		context_size += PAGE_SIZE * 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (intel_context_is_parent(ce) &amp;&amp; intel_engine_uses_guc(engine)) {</div><div class='hunk'>@@ -1407,12 +1427,85 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)</div><div class='ctx'> 	return gen12_emit_aux_table_inv(ce-&gt;engine, cs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)</div><div class='add'>+{</div><div class='add'>+	struct intel_gt *gt = ce-&gt;engine-&gt;gt;</div><div class='add'>+	int mocs = gt-&gt;mocs.uc_index &lt;&lt; 1;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Wa_16018031267 / Wa_16018063123 requires that SW forces the</div><div class='add'>+	 * main copy engine arbitration into round robin mode.  We</div><div class='add'>+	 * additionally need to submit the following WABB blt command</div><div class='add'>+	 * to produce 4 subblits with each subblit generating 0 byte</div><div class='add'>+	 * write requests as WABB:</div><div class='add'>+	 *</div><div class='add'>+	 * XY_FASTCOLOR_BLT</div><div class='add'>+	 *  BG0    -&gt; 5100000E</div><div class='add'>+	 *  BG1    -&gt; 0000003F (Dest pitch)</div><div class='add'>+	 *  BG2    -&gt; 00000000 (X1, Y1) = (0, 0)</div><div class='add'>+	 *  BG3    -&gt; 00040001 (X2, Y2) = (1, 4)</div><div class='add'>+	 *  BG4    -&gt; scratch</div><div class='add'>+	 *  BG5    -&gt; scratch</div><div class='add'>+	 *  BG6-12 -&gt; 00000000</div><div class='add'>+	 *  BG13   -&gt; 20004004 (Surf. Width= 2,Surf. Height = 5 )</div><div class='add'>+	 *  BG14   -&gt; 00000010 (Qpitch = 4)</div><div class='add'>+	 *  BG15   -&gt; 00000000</div><div class='add'>+	 */</div><div class='add'>+	*cs++ = XY_FAST_COLOR_BLT_CMD | (16 - 2);</div><div class='add'>+	*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) | 0x3f;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 4 &lt;&lt; 16 | 1;</div><div class='add'>+	*cs++ = lower_32_bits(i915_vma_offset(ce-&gt;vm-&gt;rsvd.vma));</div><div class='add'>+	*cs++ = upper_32_bits(i915_vma_offset(ce-&gt;vm-&gt;rsvd.vma));</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0x20004004;</div><div class='add'>+	*cs++ = 0x10;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+</div><div class='add'>+	return cs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 *</div><div class='add'>+xehp_emit_per_ctx_bb(const struct intel_context *ce, u32 *cs)</div><div class='add'>+{</div><div class='add'>+	/* Wa_16018031267, Wa_16018063123 */</div><div class='add'>+	if (NEEDS_FASTCOLOR_BLT_WABB(ce-&gt;engine))</div><div class='add'>+		cs = xehp_emit_fastcolor_blt_wabb(ce, cs);</div><div class='add'>+</div><div class='add'>+	return cs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+setup_per_ctx_bb(const struct intel_context *ce,</div><div class='add'>+		 const struct intel_engine_cs *engine,</div><div class='add'>+		 u32 *(*emit)(const struct intel_context *, u32 *))</div><div class='add'>+{</div><div class='add'>+	/* Place PER_CTX_BB on next page after INDIRECT_CTX */</div><div class='add'>+	u32 * const start = context_wabb(ce, true);</div><div class='add'>+	u32 *cs;</div><div class='add'>+</div><div class='add'>+	cs = emit(ce, start);</div><div class='add'>+</div><div class='add'>+	/* PER_CTX_BB must manually terminate */</div><div class='add'>+	*cs++ = MI_BATCH_BUFFER_END;</div><div class='add'>+</div><div class='add'>+	GEM_BUG_ON(cs - start &gt; I915_GTT_PAGE_SIZE / sizeof(*cs));</div><div class='add'>+	lrc_setup_bb_per_ctx(ce-&gt;lrc_reg_state, engine,</div><div class='add'>+			     lrc_indirect_bb(ce) + PAGE_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> setup_indirect_ctx_bb(const struct intel_context *ce,</div><div class='ctx'> 		      const struct intel_engine_cs *engine,</div><div class='ctx'> 		      u32 *(*emit)(const struct intel_context *, u32 *))</div><div class='ctx'> {</div><div class='del'>-	u32 * const start = context_indirect_bb(ce);</div><div class='add'>+	u32 * const start = context_wabb(ce, false);</div><div class='ctx'> 	u32 *cs;</div><div class='ctx'> </div><div class='ctx'> 	cs = emit(ce, start);</div><div class='hunk'>@@ -1511,6 +1604,7 @@ u32 lrc_update_regs(const struct intel_context *ce,</div><div class='ctx'> 		/* Mutually exclusive wrt to global indirect bb */</div><div class='ctx'> 		GEM_BUG_ON(engine-&gt;wa_ctx.indirect_ctx.size);</div><div class='ctx'> 		setup_indirect_ctx_bb(ce, engine, fn);</div><div class='add'>+		setup_per_ctx_bb(ce, engine, xehp_emit_per_ctx_bb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c<br/>index d5ed904f355d..6801f8b95c53 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_reset.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_reset.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_reset.c</a></div><div class='hunk'>@@ -1293,7 +1293,7 @@ int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)</div><div class='ctx'> 	if (msg)</div><div class='ctx'> 		drm_notice(&amp;engine-&gt;i915-&gt;drm,</div><div class='ctx'> 			   "Resetting %s for %s\n", engine-&gt;name, msg);</div><div class='del'>-	atomic_inc(&amp;engine-&gt;i915-&gt;gpu_error.reset_engine_count[engine-&gt;uabi_class]);</div><div class='add'>+	i915_increase_reset_engine_count(&amp;engine-&gt;i915-&gt;gpu_error, engine);</div><div class='ctx'> </div><div class='ctx'> 	ret = intel_gt_reset_engine(engine);</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c<br/>index f602895f6d0d..6a3246240e81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_sseu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_sseu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_sseu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_sseu.c</a></div><div class='hunk'>@@ -849,13 +849,12 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,</div><div class='ctx'> 			       const struct sseu_dev_info *sseu,</div><div class='ctx'> 			       struct drm_printer *p)</div><div class='ctx'> {</div><div class='del'>-	if (sseu-&gt;max_slices == 0) {</div><div class='add'>+	if (sseu-&gt;max_slices == 0)</div><div class='ctx'> 		drm_printf(p, "Unavailable\n");</div><div class='del'>-	} else if (GRAPHICS_VER_FULL(i915) &gt;= IP_VER(12, 50)) {</div><div class='add'>+	else if (GRAPHICS_VER_FULL(i915) &gt;= IP_VER(12, 50))</div><div class='ctx'> 		sseu_print_xehp_topology(sseu, p);</div><div class='del'>-	} else {</div><div class='add'>+	else</div><div class='ctx'> 		sseu_print_hsw_topology(sseu, p);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void intel_sseu_print_ss_info(const char *type,</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c<br/>index 192ac0e59afa..3eacbc50caf8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_workarounds.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/intel_workarounds.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/intel_workarounds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/intel_workarounds.c</a></div><div class='hunk'>@@ -777,6 +777,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,</div><div class='ctx'> </div><div class='ctx'> 	/* Wa_18019271663:dg2 */</div><div class='ctx'> 	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);</div><div class='add'>+</div><div class='add'>+	/* Wa_14019877138:dg2 */</div><div class='add'>+	wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,</div><div class='hunk'>@@ -1663,8 +1666,22 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='add'>+wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal)</div><div class='add'>+{</div><div class='add'>+	struct intel_engine_cs *engine;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	for_each_engine(engine, gt, id)</div><div class='add'>+		if (engine-&gt;class == VIDEO_DECODE_CLASS)</div><div class='add'>+			wa_write_or(wal, VDBOX_CGCTL3F1C(engine-&gt;mmio_base),</div><div class='add'>+				    MFXPIPE_CLKGATE_DIS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='ctx'> xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)</div><div class='ctx'> {</div><div class='add'>+	wa_16021867713(gt, wal);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Wa_14018778641</div><div class='ctx'> 	 * Wa_18018781329</div><div class='hunk'>@@ -1674,6 +1691,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)</div><div class='ctx'> 	 */</div><div class='ctx'> 	wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);</div><div class='ctx'> </div><div class='add'>+	/* Wa_22016670082 */</div><div class='add'>+	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);</div><div class='add'>+</div><div class='ctx'> 	debug_dump_steering(gt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2340,14 +2360,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)</div><div class='ctx'> 			   0, true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {</div><div class='del'>-		/* Wa_22014600077:dg2 */</div><div class='del'>-		wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,</div><div class='del'>-			   _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),</div><div class='del'>-			   0 /* Wa_14012342262 write-only reg, so skip verification */,</div><div class='del'>-			   true);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||</div><div class='ctx'> 	    IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -2782,6 +2794,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)</div><div class='ctx'> 			 RING_SEMA_WAIT_POLL(engine-&gt;mmio_base),</div><div class='ctx'> 			 1);</div><div class='ctx'> 	}</div><div class='add'>+	/* Wa_16018031267, Wa_16018063123 */</div><div class='add'>+	if (NEEDS_FASTCOLOR_BLT_WABB(engine))</div><div class='add'>+		wa_masked_field_set(wal, ECOSKPD(engine-&gt;mmio_base),</div><div class='add'>+				    XEHP_BLITTER_SCHEDULING_MODE_MASK,</div><div class='add'>+				    XEHP_BLITTER_ROUND_ROBIN_MODE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -2915,6 +2932,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li</div><div class='ctx'> 		 * Wa_22015475538:dg2</div><div class='ctx'> 		 */</div><div class='ctx'> 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);</div><div class='add'>+</div><div class='add'>+		/* Wa_18028616096 */</div><div class='add'>+		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (IS_DG2_G11(i915)) {</div><div class='hunk'>@@ -2943,11 +2963,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li</div><div class='ctx'> 			   true);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {</div><div class='del'>-		/* Wa_18028616096 */</div><div class='del'>-		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (IS_XEHPSDV(i915)) {</div><div class='ctx'> 		/* Wa_1409954639 */</div><div class='ctx'> 		wa_mcr_masked_en(wal,</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c<br/>index 86cecf7a1105..5ffa5e30f419 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_engine_cs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_engine_cs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_engine_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_engine_cs.c</a></div><div class='hunk'>@@ -21,20 +21,22 @@ static int cmp_u32(const void *A, const void *B)</div><div class='ctx'> 	return *a - *b;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void perf_begin(struct intel_gt *gt)</div><div class='add'>+static intel_wakeref_t perf_begin(struct intel_gt *gt)</div><div class='ctx'> {</div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	intel_wakeref_t wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> </div><div class='ctx'> 	/* Boost gpufreq to max [waitboost] and keep it fixed */</div><div class='ctx'> 	atomic_inc(&amp;gt-&gt;rps.num_waiters);</div><div class='ctx'> 	queue_work(gt-&gt;i915-&gt;unordered_wq, &amp;gt-&gt;rps.work);</div><div class='ctx'> 	flush_work(&amp;gt-&gt;rps.work);</div><div class='add'>+</div><div class='add'>+	return wakeref;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int perf_end(struct intel_gt *gt)</div><div class='add'>+static int perf_end(struct intel_gt *gt, intel_wakeref_t wakeref)</div><div class='ctx'> {</div><div class='ctx'> 	atomic_dec(&amp;gt-&gt;rps.num_waiters);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	return igt_flush_test(gt-&gt;i915);</div><div class='ctx'> }</div><div class='hunk'>@@ -133,12 +135,13 @@ static int perf_mi_bb_start(void *arg)</div><div class='ctx'> 	struct intel_gt *gt = arg;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (GRAPHICS_VER(gt-&gt;i915) &lt; 4) /* Any CS_TIMESTAMP? */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	perf_begin(gt);</div><div class='add'>+	wakeref = perf_begin(gt);</div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='ctx'> 		struct intel_context *ce = engine-&gt;kernel_context;</div><div class='ctx'> 		struct i915_vma *batch;</div><div class='hunk'>@@ -207,7 +210,7 @@ out:</div><div class='ctx'> 		pr_info("%s: MI_BB_START cycles: %u\n",</div><div class='ctx'> 			engine-&gt;name, trifilter(cycles));</div><div class='ctx'> 	}</div><div class='del'>-	if (perf_end(gt))</div><div class='add'>+	if (perf_end(gt, wakeref))</div><div class='ctx'> 		err = -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -260,12 +263,13 @@ static int perf_mi_noop(void *arg)</div><div class='ctx'> 	struct intel_gt *gt = arg;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (GRAPHICS_VER(gt-&gt;i915) &lt; 4) /* Any CS_TIMESTAMP? */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	perf_begin(gt);</div><div class='add'>+	wakeref = perf_begin(gt);</div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='ctx'> 		struct intel_context *ce = engine-&gt;kernel_context;</div><div class='ctx'> 		struct i915_vma *base, *nop;</div><div class='hunk'>@@ -364,7 +368,7 @@ out:</div><div class='ctx'> 		pr_info("%s: 16K MI_NOOP cycles: %u\n",</div><div class='ctx'> 			engine-&gt;name, trifilter(cycles));</div><div class='ctx'> 	}</div><div class='del'>-	if (perf_end(gt))</div><div class='add'>+	if (perf_end(gt, wakeref))</div><div class='ctx'> 		err = -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c<br/>index 273d440a53e3..bc441ce7b380 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c</a></div><div class='hunk'>@@ -84,7 +84,7 @@ static struct pulse *pulse_create(void)</div><div class='ctx'> </div><div class='ctx'> static void pulse_unlock_wait(struct pulse *p)</div><div class='ctx'> {</div><div class='del'>-	i915_active_unlock_wait(&amp;p-&gt;active);</div><div class='add'>+	wait_var_event_timeout(&amp;p-&gt;active, i915_active_is_idle(&amp;p-&gt;active), HZ);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __live_idle_pulse(struct intel_engine_cs *engine,</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c<br/>index 0971241707ce..33351deeea4f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_gt_pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_gt_pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_gt_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_gt_pm.c</a></div><div class='hunk'>@@ -81,6 +81,7 @@ static int live_gt_clocks(void *arg)</div><div class='ctx'> 	struct intel_gt *gt = arg;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!gt-&gt;clock_frequency) { /* unknown */</div><div class='hunk'>@@ -91,7 +92,7 @@ static int live_gt_clocks(void *arg)</div><div class='ctx'> 	if (GRAPHICS_VER(gt-&gt;i915) &lt; 4) /* Any CS_TIMESTAMP? */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	intel_uncore_forcewake_get(gt-&gt;uncore, FORCEWAKE_ALL);</div><div class='ctx'> </div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='hunk'>@@ -128,7 +129,7 @@ static int live_gt_clocks(void *arg)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	intel_uncore_forcewake_put(gt-&gt;uncore, FORCEWAKE_ALL);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c<br/>index 5f826b6dcf5d..e17b8777d21d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_lrc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_lrc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_lrc.c</a></div><div class='hunk'>@@ -1555,7 +1555,7 @@ static int live_lrc_isolation(void *arg)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int indirect_ctx_submit_req(struct intel_context *ce)</div><div class='add'>+static int wabb_ctx_submit_req(struct intel_context *ce)</div><div class='ctx'> {</div><div class='ctx'> 	struct i915_request *rq;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -1579,7 +1579,8 @@ static int indirect_ctx_submit_req(struct intel_context *ce)</div><div class='ctx'> #define CTX_BB_CANARY_INDEX  (CTX_BB_CANARY_OFFSET / sizeof(u32))</div><div class='ctx'> </div><div class='ctx'> static u32 *</div><div class='del'>-emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)</div><div class='add'>+emit_wabb_ctx_canary(const struct intel_context *ce,</div><div class='add'>+		     u32 *cs, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	*cs++ = MI_STORE_REGISTER_MEM_GEN8 |</div><div class='ctx'> 		MI_SRM_LRM_GLOBAL_GTT |</div><div class='hunk'>@@ -1587,26 +1588,43 @@ emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)</div><div class='ctx'> 	*cs++ = i915_mmio_reg_offset(RING_START(0));</div><div class='ctx'> 	*cs++ = i915_ggtt_offset(ce-&gt;state) +</div><div class='ctx'> 		context_wa_bb_offset(ce) +</div><div class='del'>-		CTX_BB_CANARY_OFFSET;</div><div class='add'>+		CTX_BB_CANARY_OFFSET +</div><div class='add'>+		(per_ctx ? PAGE_SIZE : 0);</div><div class='ctx'> 	*cs++ = 0;</div><div class='ctx'> </div><div class='ctx'> 	return cs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 *</div><div class='add'>+emit_indirect_ctx_bb_canary(const struct intel_context *ce, u32 *cs)</div><div class='add'>+{</div><div class='add'>+	return emit_wabb_ctx_canary(ce, cs, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 *</div><div class='add'>+emit_per_ctx_bb_canary(const struct intel_context *ce, u32 *cs)</div><div class='add'>+{</div><div class='add'>+	return emit_wabb_ctx_canary(ce, cs, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='del'>-indirect_ctx_bb_setup(struct intel_context *ce)</div><div class='add'>+wabb_ctx_setup(struct intel_context *ce, bool per_ctx)</div><div class='ctx'> {</div><div class='del'>-	u32 *cs = context_indirect_bb(ce);</div><div class='add'>+	u32 *cs = context_wabb(ce, per_ctx);</div><div class='ctx'> </div><div class='ctx'> 	cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d;</div><div class='ctx'> </div><div class='del'>-	setup_indirect_ctx_bb(ce, ce-&gt;engine, emit_indirect_ctx_bb_canary);</div><div class='add'>+	if (per_ctx)</div><div class='add'>+		setup_per_ctx_bb(ce, ce-&gt;engine, emit_per_ctx_bb_canary);</div><div class='add'>+	else</div><div class='add'>+		setup_indirect_ctx_bb(ce, ce-&gt;engine, emit_indirect_ctx_bb_canary);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool check_ring_start(struct intel_context *ce)</div><div class='add'>+static bool check_ring_start(struct intel_context *ce, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	const u32 * const ctx_bb = (void *)(ce-&gt;lrc_reg_state) -</div><div class='del'>-		LRC_STATE_OFFSET + context_wa_bb_offset(ce);</div><div class='add'>+		LRC_STATE_OFFSET + context_wa_bb_offset(ce) +</div><div class='add'>+		(per_ctx ? PAGE_SIZE : 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ctx_bb[CTX_BB_CANARY_INDEX] == ce-&gt;lrc_reg_state[CTX_RING_START])</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -1618,21 +1636,21 @@ static bool check_ring_start(struct intel_context *ce)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int indirect_ctx_bb_check(struct intel_context *ce)</div><div class='add'>+static int wabb_ctx_check(struct intel_context *ce, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = indirect_ctx_submit_req(ce);</div><div class='add'>+	err = wabb_ctx_submit_req(ce);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	if (!check_ring_start(ce))</div><div class='add'>+	if (!check_ring_start(ce, per_ctx))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)</div><div class='add'>+static int __lrc_wabb_ctx(struct intel_engine_cs *engine, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_context *a, *b;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -1667,14 +1685,14 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)</div><div class='ctx'> 	 * As ring start is restored apriori of starting the indirect ctx bb and</div><div class='ctx'> 	 * as it will be different for each context, it fits to this purpose.</div><div class='ctx'> 	 */</div><div class='del'>-	indirect_ctx_bb_setup(a);</div><div class='del'>-	indirect_ctx_bb_setup(b);</div><div class='add'>+	wabb_ctx_setup(a, per_ctx);</div><div class='add'>+	wabb_ctx_setup(b, per_ctx);</div><div class='ctx'> </div><div class='del'>-	err = indirect_ctx_bb_check(a);</div><div class='add'>+	err = wabb_ctx_check(a, per_ctx);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto unpin_b;</div><div class='ctx'> </div><div class='del'>-	err = indirect_ctx_bb_check(b);</div><div class='add'>+	err = wabb_ctx_check(b, per_ctx);</div><div class='ctx'> </div><div class='ctx'> unpin_b:</div><div class='ctx'> 	intel_context_unpin(b);</div><div class='hunk'>@@ -1688,7 +1706,7 @@ put_a:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int live_lrc_indirect_ctx_bb(void *arg)</div><div class='add'>+static int lrc_wabb_ctx(void *arg, bool per_ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_gt *gt = arg;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='hunk'>@@ -1697,7 +1715,7 @@ static int live_lrc_indirect_ctx_bb(void *arg)</div><div class='ctx'> </div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='ctx'> 		intel_engine_pm_get(engine);</div><div class='del'>-		err = __live_lrc_indirect_ctx_bb(engine);</div><div class='add'>+		err = __lrc_wabb_ctx(engine, per_ctx);</div><div class='ctx'> 		intel_engine_pm_put(engine);</div><div class='ctx'> </div><div class='ctx'> 		if (igt_flush_test(gt-&gt;i915))</div><div class='hunk'>@@ -1710,6 +1728,16 @@ static int live_lrc_indirect_ctx_bb(void *arg)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int live_lrc_indirect_ctx_bb(void *arg)</div><div class='add'>+{</div><div class='add'>+	return lrc_wabb_ctx(arg, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int live_lrc_per_ctx_bb(void *arg)</div><div class='add'>+{</div><div class='add'>+	return lrc_wabb_ctx(arg, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void garbage_reset(struct intel_engine_cs *engine,</div><div class='ctx'> 			  struct i915_request *rq)</div><div class='ctx'> {</div><div class='hunk'>@@ -1947,6 +1975,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)</div><div class='ctx'> 		SUBTEST(live_lrc_garbage),</div><div class='ctx'> 		SUBTEST(live_pphwsp_runtime),</div><div class='ctx'> 		SUBTEST(live_lrc_indirect_ctx_bb),</div><div class='add'>+		SUBTEST(live_lrc_per_ctx_bb),</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	if (!HAS_LOGICAL_RING_CONTEXTS(i915))</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c<br/>index 79aa6ac66ad2..f40de408cd3a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_reset.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_reset.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_reset.c</a></div><div class='hunk'>@@ -261,11 +261,12 @@ static int igt_atomic_reset(void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_gt *gt = arg;</div><div class='ctx'> 	const typeof(*igt_atomic_phases) *p;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Check that the resets are usable from atomic context */</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	igt_global_reset_lock(gt);</div><div class='ctx'> </div><div class='ctx'> 	/* Flush any requests before we get started and check basics */</div><div class='hunk'>@@ -296,7 +297,7 @@ static int igt_atomic_reset(void *arg)</div><div class='ctx'> </div><div class='ctx'> unlock:</div><div class='ctx'> 	igt_global_reset_unlock(gt);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -307,6 +308,7 @@ static int igt_atomic_engine_reset(void *arg)</div><div class='ctx'> 	const typeof(*igt_atomic_phases) *p;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Check that the resets are usable from atomic context */</div><div class='hunk'>@@ -317,7 +319,7 @@ static int igt_atomic_engine_reset(void *arg)</div><div class='ctx'> 	if (intel_uc_uses_guc_submission(&amp;gt-&gt;uc))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	igt_global_reset_lock(gt);</div><div class='ctx'> </div><div class='ctx'> 	/* Flush any requests before we get started and check basics */</div><div class='hunk'>@@ -365,7 +367,7 @@ static int igt_atomic_engine_reset(void *arg)</div><div class='ctx'> </div><div class='ctx'> out_unlock:</div><div class='ctx'> 	igt_global_reset_unlock(gt);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c<br/>index fb30f733b036..dcef8d498919 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_rps.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_rps.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_rps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_rps.c</a></div><div class='hunk'>@@ -224,6 +224,7 @@ int live_rps_clock_interval(void *arg)</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='ctx'> 	struct igt_spinner spin;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt-&gt;i915) &lt; 6)</div><div class='hunk'>@@ -236,7 +237,7 @@ int live_rps_clock_interval(void *arg)</div><div class='ctx'> 	saved_work = rps-&gt;work.func;</div><div class='ctx'> 	rps-&gt;work.func = dummy_rps_work;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	intel_rps_disable(&amp;gt-&gt;rps);</div><div class='ctx'> </div><div class='ctx'> 	intel_gt_check_clock_frequency(gt);</div><div class='hunk'>@@ -355,7 +356,7 @@ int live_rps_clock_interval(void *arg)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	intel_rps_enable(&amp;gt-&gt;rps);</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	igt_spinner_fini(&amp;spin);</div><div class='ctx'> </div><div class='hunk'>@@ -376,6 +377,7 @@ int live_rps_control(void *arg)</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='ctx'> 	struct igt_spinner spin;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -398,7 +400,7 @@ int live_rps_control(void *arg)</div><div class='ctx'> 	saved_work = rps-&gt;work.func;</div><div class='ctx'> 	rps-&gt;work.func = dummy_rps_work;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='ctx'> 		struct i915_request *rq;</div><div class='ctx'> 		ktime_t min_dt, max_dt;</div><div class='hunk'>@@ -488,7 +490,7 @@ int live_rps_control(void *arg)</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> </div><div class='ctx'> 	igt_spinner_fini(&amp;spin);</div><div class='ctx'> </div><div class='hunk'>@@ -1023,6 +1025,7 @@ int live_rps_interrupt(void *arg)</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='ctx'> 	struct igt_spinner spin;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	u32 pm_events;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1033,9 +1036,9 @@ int live_rps_interrupt(void *arg)</div><div class='ctx'> 	if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt-&gt;i915) &lt; 6)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='del'>-	pm_events = rps-&gt;pm_events;</div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	pm_events = 0;</div><div class='add'>+	with_intel_gt_pm(gt, wakeref)</div><div class='add'>+		pm_events = rps-&gt;pm_events;</div><div class='ctx'> 	if (!pm_events) {</div><div class='ctx'> 		pr_err("No RPS PM events registered, but RPS is enabled?\n");</div><div class='ctx'> 		return -ENODEV;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c<br/>index 952c8d52d68a..302d0540295d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_slpc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/selftest_slpc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/selftest_slpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/selftest_slpc.c</a></div><div class='hunk'>@@ -266,6 +266,7 @@ static int run_test(struct intel_gt *gt, int test_type)</div><div class='ctx'> 	struct intel_rps *rps = &amp;gt-&gt;rps;</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> 	enum intel_engine_id id;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	struct igt_spinner spin;</div><div class='ctx'> 	u32 slpc_min_freq, slpc_max_freq;</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -311,7 +312,7 @@ static int run_test(struct intel_gt *gt, int test_type)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	intel_gt_pm_wait_for_idle(gt);</div><div class='del'>-	intel_gt_pm_get(gt);</div><div class='add'>+	wakeref = intel_gt_pm_get(gt);</div><div class='ctx'> 	for_each_engine(engine, gt, id) {</div><div class='ctx'> 		struct i915_request *rq;</div><div class='ctx'> 		u32 max_act_freq;</div><div class='hunk'>@@ -397,7 +398,7 @@ static int run_test(struct intel_gt *gt, int test_type)</div><div class='ctx'> 	if (igt_flush_test(gt-&gt;i915))</div><div class='ctx'> 		err = -EIO;</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_put(gt);</div><div class='add'>+	intel_gt_pm_put(gt, wakeref);</div><div class='ctx'> 	igt_spinner_fini(&amp;spin);</div><div class='ctx'> 	intel_gt_pm_wait_for_idle(gt);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c<br/>index 5f138de3c14f..40817ebcca71 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c</a></div><div class='hunk'>@@ -322,6 +322,7 @@ static int i915_gsc_proxy_component_bind(struct device *i915_kdev,</div><div class='ctx'> 	gsc-&gt;proxy.component = data;</div><div class='ctx'> 	gsc-&gt;proxy.component-&gt;mei_dev = mei_kdev;</div><div class='ctx'> 	mutex_unlock(&amp;gsc-&gt;proxy.mutex);</div><div class='add'>+	gt_dbg(gt, "GSC proxy mei component bound\n");</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -342,6 +343,7 @@ static void i915_gsc_proxy_component_unbind(struct device *i915_kdev,</div><div class='ctx'> 	with_intel_runtime_pm(&amp;i915-&gt;runtime_pm, wakeref)</div><div class='ctx'> 		intel_uncore_rmw(gt-&gt;uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),</div><div class='ctx'> 				 HECI_H_CSR_IE | HECI_H_CSR_RST, 0);</div><div class='add'>+	gt_dbg(gt, "GSC proxy mei component unbound\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct component_ops i915_gsc_proxy_component_ops = {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c<br/>index 3f3df1166b86..2b450c43bbd7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc.c</a></div><div class='hunk'>@@ -330,7 +330,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)</div><div class='ctx'> </div><div class='ctx'> static u32 guc_ctl_devid(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> </div><div class='ctx'> 	return (INTEL_DEVID(i915) &lt;&lt; 16) | INTEL_REVID(i915);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h<br/>index 2b6dfe62c8f2..813cc888e6fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc.h</a></div><div class='hunk'>@@ -105,61 +105,67 @@ struct intel_guc {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct {</div><div class='ctx'> 		/**</div><div class='del'>-		 * @lock: protects everything in submission_state,</div><div class='del'>-		 * ce-&gt;guc_id.id, and ce-&gt;guc_id.ref when transitioning in and</div><div class='del'>-		 * out of zero</div><div class='add'>+		 * @submission_state.lock: protects everything in</div><div class='add'>+		 * submission_state, ce-&gt;guc_id.id, and ce-&gt;guc_id.ref</div><div class='add'>+		 * when transitioning in and out of zero</div><div class='ctx'> 		 */</div><div class='ctx'> 		spinlock_t lock;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @guc_ids: used to allocate new guc_ids, single-lrc</div><div class='add'>+		 * @submission_state.guc_ids: used to allocate new</div><div class='add'>+		 * guc_ids, single-lrc</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct ida guc_ids;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @num_guc_ids: Number of guc_ids, selftest feature to be able</div><div class='del'>-		 * to reduce this number while testing.</div><div class='add'>+		 * @submission_state.num_guc_ids: Number of guc_ids, selftest</div><div class='add'>+		 * feature to be able to reduce this number while testing.</div><div class='ctx'> 		 */</div><div class='ctx'> 		int num_guc_ids;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc</div><div class='add'>+		 * @submission_state.guc_ids_bitmap: used to allocate</div><div class='add'>+		 * new guc_ids, multi-lrc</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned long *guc_ids_bitmap;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @guc_id_list: list of intel_context with valid guc_ids but no</div><div class='del'>-		 * refs</div><div class='add'>+		 * @submission_state.guc_id_list: list of intel_context</div><div class='add'>+		 * with valid guc_ids but no refs</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct list_head guc_id_list;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @guc_ids_in_use: Number single-lrc guc_ids in use</div><div class='add'>+		 * @submission_state.guc_ids_in_use: Number single-lrc</div><div class='add'>+		 * guc_ids in use</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned int guc_ids_in_use;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @destroyed_contexts: list of contexts waiting to be destroyed</div><div class='del'>-		 * (deregistered with the GuC)</div><div class='add'>+		 * @submission_state.destroyed_contexts: list of contexts</div><div class='add'>+		 * waiting to be destroyed (deregistered with the GuC)</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct list_head destroyed_contexts;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @destroyed_worker: worker to deregister contexts, need as we</div><div class='del'>-		 * need to take a GT PM reference and can't from destroy</div><div class='del'>-		 * function as it might be in an atomic context (no sleeping)</div><div class='add'>+		 * @submission_state.destroyed_worker: worker to deregister</div><div class='add'>+		 * contexts, need as we need to take a GT PM reference and</div><div class='add'>+		 * can't from destroy function as it might be in an atomic</div><div class='add'>+		 * context (no sleeping)</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct work_struct destroyed_worker;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @reset_fail_worker: worker to trigger a GT reset after an</div><div class='del'>-		 * engine reset fails</div><div class='add'>+		 * @submission_state.reset_fail_worker: worker to trigger</div><div class='add'>+		 * a GT reset after an engine reset fails</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct work_struct reset_fail_worker;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @reset_fail_mask: mask of engines that failed to reset</div><div class='add'>+		 * @submission_state.reset_fail_mask: mask of engines that</div><div class='add'>+		 * failed to reset</div><div class='ctx'> 		 */</div><div class='ctx'> 		intel_engine_mask_t reset_fail_mask;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @sched_disable_delay_ms: schedule disable delay, in ms, for</div><div class='del'>-		 * contexts</div><div class='add'>+		 * @submission_state.sched_disable_delay_ms: schedule</div><div class='add'>+		 * disable delay, in ms, for contexts</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned int sched_disable_delay_ms;</div><div class='ctx'> 		/**</div><div class='del'>-		 * @sched_disable_gucid_threshold: threshold of min remaining available</div><div class='del'>-		 * guc_ids before we start bypassing the schedule disable delay</div><div class='add'>+		 * @submission_state.sched_disable_gucid_threshold:</div><div class='add'>+		 * threshold of min remaining available guc_ids before</div><div class='add'>+		 * we start bypassing the schedule disable delay</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned int sched_disable_gucid_threshold;</div><div class='ctx'> 	} submission_state;</div><div class='hunk'>@@ -243,37 +249,40 @@ struct intel_guc {</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct {</div><div class='ctx'> 		/**</div><div class='del'>-		 * @lock: Lock protecting the below fields and the engine stats.</div><div class='add'>+		 * @timestamp.lock: Lock protecting the below fields and</div><div class='add'>+		 * the engine stats.</div><div class='ctx'> 		 */</div><div class='ctx'> 		spinlock_t lock;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @gt_stamp: 64 bit extended value of the GT timestamp.</div><div class='add'>+		 * @timestamp.gt_stamp: 64-bit extended value of the GT</div><div class='add'>+		 * timestamp.</div><div class='ctx'> 		 */</div><div class='ctx'> 		u64 gt_stamp;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @ping_delay: Period for polling the GT timestamp for</div><div class='del'>-		 * overflow.</div><div class='add'>+		 * @timestamp.ping_delay: Period for polling the GT</div><div class='add'>+		 * timestamp for overflow.</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned long ping_delay;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @work: Periodic work to adjust GT timestamp, engine and</div><div class='del'>-		 * context usage for overflows.</div><div class='add'>+		 * @timestamp.work: Periodic work to adjust GT timestamp,</div><div class='add'>+		 * engine and context usage for overflows.</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct delayed_work work;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @shift: Right shift value for the gpm timestamp</div><div class='add'>+		 * @timestamp.shift: Right shift value for the gpm timestamp</div><div class='ctx'> 		 */</div><div class='ctx'> 		u32 shift;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @last_stat_jiffies: jiffies at last actual stats collection time</div><div class='del'>-		 * We use this timestamp to ensure we don't oversample the</div><div class='del'>-		 * stats because runtime power management events can trigger</div><div class='del'>-		 * stats collection at much higher rates than required.</div><div class='add'>+		 * @timestamp.last_stat_jiffies: jiffies at last actual</div><div class='add'>+		 * stats collection time. We use this timestamp to ensure</div><div class='add'>+		 * we don't oversample the stats because runtime power</div><div class='add'>+		 * management events can trigger stats collection at much</div><div class='add'>+		 * higher rates than required.</div><div class='ctx'> 		 */</div><div class='ctx'> 		unsigned long last_stat_jiffies;</div><div class='ctx'> 	} timestamp;</div><div class='hunk'>@@ -297,6 +306,10 @@ struct intel_guc {</div><div class='ctx'> 	 * @number_guc_id_stolen: The number of guc_ids that have been stolen</div><div class='ctx'> 	 */</div><div class='ctx'> 	int number_guc_id_stolen;</div><div class='add'>+	/**</div><div class='add'>+	 * @fast_response_selftest: Backdoor to CT handler for fast response selftest</div><div class='add'>+	 */</div><div class='add'>+	u32 fast_response_selftest;</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c<br/>index a4da0208c883..a1cd40d80517 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c</a></div><div class='hunk'>@@ -355,7 +355,7 @@ guc_capture_alloc_steered_lists(struct intel_guc *guc,</div><div class='ctx'> static const struct __guc_mmio_reg_descr_group *</div><div class='ctx'> guc_capture_get_device_reglist(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> 	const struct __guc_mmio_reg_descr_group *lists;</div><div class='ctx'> </div><div class='ctx'> 	if (GRAPHICS_VER(i915) &gt;= 12)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c<br/>index 89e314b3756b..0d5197c0824a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c</a></div><div class='hunk'>@@ -265,7 +265,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)</div><div class='ctx'> 	u32 *cmds;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = i915_inject_probe_error(guc_to_gt(guc)-&gt;i915, -ENXIO);</div><div class='add'>+	err = i915_inject_probe_error(guc_to_i915(guc), -ENXIO);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1076,6 +1076,15 @@ static int ct_handle_response(struct intel_guc_ct *ct, struct ct_incoming_msg *r</div><div class='ctx'> 		found = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_I915_SELFTEST</div><div class='add'>+	if (!found &amp;&amp; ct_to_guc(ct)-&gt;fast_response_selftest) {</div><div class='add'>+		CT_DEBUG(ct, "Assuming unsolicited response due to FAST_REQUEST selftest\n");</div><div class='add'>+		ct_to_guc(ct)-&gt;fast_response_selftest++;</div><div class='add'>+		found = true;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	if (!found) {</div><div class='ctx'> 		CT_ERROR(ct, "Unsolicited response message: len %u, data %#x (fence %u, last %u)\n",</div><div class='ctx'> 			 len, hxg[0], fence, ct-&gt;requests.last_fence);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c<br/>index 55bc8b55fbc0..bf16351c9349 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_log.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_log.c</a></div><div class='hunk'>@@ -520,7 +520,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)</div><div class='ctx'> static int guc_log_relay_create(struct intel_guc_log *log)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_guc *guc = log_to_guc(log);</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> 	struct rchan *guc_log_relay_chan;</div><div class='ctx'> 	size_t n_subbufs, subbuf_size;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -573,7 +573,7 @@ static void guc_log_relay_destroy(struct intel_guc_log *log)</div><div class='ctx'> static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_guc *guc = log_to_guc(log);</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> 	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='ctx'> 	_guc_log_copy_debuglogs_for_relay(log);</div><div class='hunk'>@@ -589,7 +589,7 @@ static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)</div><div class='ctx'> static u32 __get_default_log_level(struct intel_guc_log *log)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_guc *guc = log_to_guc(log);</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> </div><div class='ctx'> 	/* A negative value means "use platform/config default" */</div><div class='ctx'> 	if (i915-&gt;params.guc_log_level &lt; 0) {</div><div class='hunk'>@@ -664,7 +664,7 @@ void intel_guc_log_destroy(struct intel_guc_log *log)</div><div class='ctx'> int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_guc *guc = log_to_guc(log);</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> 	intel_wakeref_t wakeref;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -796,7 +796,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)</div><div class='ctx'> static void guc_log_relay_stop(struct intel_guc_log *log)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_guc *guc = log_to_guc(log);</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> </div><div class='ctx'> 	if (!log-&gt;relay.started)</div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c<br/>index 1adec6de223c..9df7927304ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c</a></div><div class='hunk'>@@ -14,7 +14,7 @@ static bool __guc_rc_supported(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='ctx'> 	/* GuC RC is unavailable for pre-Gen12 */</div><div class='ctx'> 	return guc-&gt;submission_supported &amp;&amp;</div><div class='del'>-		GRAPHICS_VER(guc_to_gt(guc)-&gt;i915) &gt;= 12;</div><div class='add'>+		GRAPHICS_VER(guc_to_i915(guc)) &gt;= 12;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool __guc_rc_selected(struct intel_guc *guc)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c<br/>index 2dfb07cc4b33..3e681ab6fbf9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c</a></div><div class='hunk'>@@ -34,7 +34,7 @@ static bool __detect_slpc_supported(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='ctx'> 	/* GuC SLPC is unavailable for pre-Gen12 */</div><div class='ctx'> 	return guc-&gt;submission_supported &amp;&amp;</div><div class='del'>-		GRAPHICS_VER(guc_to_gt(guc)-&gt;i915) &gt;= 12;</div><div class='add'>+		GRAPHICS_VER(guc_to_i915(guc)) &gt;= 12;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool __guc_slpc_selected(struct intel_guc *guc)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c<br/>index d37698bd6b91..a259f1118c5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c</a></div><div class='hunk'>@@ -1107,7 +1107,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc)</div><div class='ctx'> 			if (deregister)</div><div class='ctx'> 				guc_signal_context_fence(ce);</div><div class='ctx'> 			if (destroyed) {</div><div class='del'>-				intel_gt_pm_put_async(guc_to_gt(guc));</div><div class='add'>+				intel_gt_pm_put_async_untracked(guc_to_gt(guc));</div><div class='ctx'> 				release_guc_id(guc, ce);</div><div class='ctx'> 				__guc_context_destroy(ce);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1303,6 +1303,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs *engine, ktime_t *now)</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 reset_count;</div><div class='ctx'> 	bool in_reset;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;guc-&gt;timestamp.lock, flags);</div><div class='ctx'> </div><div class='hunk'>@@ -1325,7 +1326,8 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs *engine, ktime_t *now)</div><div class='ctx'> 	 * start_gt_clk is derived from GuC state. To get a consistent</div><div class='ctx'> 	 * view of activity, we query the GuC state only if gt is awake.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!in_reset &amp;&amp; intel_gt_pm_get_if_awake(gt)) {</div><div class='add'>+	wakeref = in_reset ? 0 : intel_gt_pm_get_if_awake(gt);</div><div class='add'>+	if (wakeref) {</div><div class='ctx'> 		stats_saved = *stats;</div><div class='ctx'> 		gt_stamp_saved = guc-&gt;timestamp.gt_stamp;</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -1334,7 +1336,7 @@ static ktime_t guc_engine_busyness(struct intel_engine_cs *engine, ktime_t *now)</div><div class='ctx'> 		 */</div><div class='ctx'> 		guc_update_engine_gt_clks(engine);</div><div class='ctx'> 		guc_update_pm_timestamp(guc, now);</div><div class='del'>-		intel_gt_pm_put_async(gt);</div><div class='add'>+		intel_gt_pm_put_async(gt, wakeref);</div><div class='ctx'> 		if (i915_reset_count(gpu_error) != reset_count) {</div><div class='ctx'> 			*stats = stats_saved;</div><div class='ctx'> 			guc-&gt;timestamp.gt_stamp = gt_stamp_saved;</div><div class='hunk'>@@ -3385,9 +3387,9 @@ static void destroyed_worker_func(struct work_struct *w)</div><div class='ctx'> 	struct intel_guc *guc = container_of(w, struct intel_guc,</div><div class='ctx'> 					     submission_state.destroyed_worker);</div><div class='ctx'> 	struct intel_gt *gt = guc_to_gt(guc);</div><div class='del'>-	int tmp;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='del'>-	with_intel_gt_pm(gt, tmp)</div><div class='add'>+	with_intel_gt_pm(gt, wakeref)</div><div class='ctx'> 		deregister_destroyed_contexts(guc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4624,12 +4626,12 @@ static bool __guc_submission_supported(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='ctx'> 	/* GuC submission is unavailable for pre-Gen11 */</div><div class='ctx'> 	return intel_guc_is_supported(guc) &amp;&amp;</div><div class='del'>-	       GRAPHICS_VER(guc_to_gt(guc)-&gt;i915) &gt;= 11;</div><div class='add'>+	       GRAPHICS_VER(guc_to_i915(guc)) &gt;= 11;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool __guc_submission_selected(struct intel_guc *guc)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = guc_to_gt(guc)-&gt;i915;</div><div class='add'>+	struct drm_i915_private *i915 = guc_to_i915(guc);</div><div class='ctx'> </div><div class='ctx'> 	if (!intel_guc_submission_is_supported(guc))</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -4894,7 +4896,7 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,</div><div class='ctx'> 		intel_context_put(ce);</div><div class='ctx'> 	} else if (context_destroyed(ce)) {</div><div class='ctx'> 		/* Context has been destroyed */</div><div class='del'>-		intel_gt_pm_put_async(guc_to_gt(guc));</div><div class='add'>+		intel_gt_pm_put_async_untracked(guc_to_gt(guc));</div><div class='ctx'> 		release_guc_id(guc, ce);</div><div class='ctx'> 		__guc_context_destroy(ce);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -5001,7 +5003,8 @@ static void capture_error_state(struct intel_guc *guc,</div><div class='ctx'> 			if (match) {</div><div class='ctx'> 				intel_engine_set_hung_context(e, ce);</div><div class='ctx'> 				engine_mask |= e-&gt;mask;</div><div class='del'>-				atomic_inc(&amp;i915-&gt;gpu_error.reset_engine_count[e-&gt;uabi_class]);</div><div class='add'>+				i915_increase_reset_engine_count(&amp;i915-&gt;gpu_error,</div><div class='add'>+								 e);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -5013,7 +5016,7 @@ static void capture_error_state(struct intel_guc *guc,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		intel_engine_set_hung_context(ce-&gt;engine, ce);</div><div class='ctx'> 		engine_mask = ce-&gt;engine-&gt;mask;</div><div class='del'>-		atomic_inc(&amp;i915-&gt;gpu_error.reset_engine_count[ce-&gt;engine-&gt;uabi_class]);</div><div class='add'>+		i915_increase_reset_engine_count(&amp;i915-&gt;gpu_error, ce-&gt;engine);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	with_intel_runtime_pm(&amp;i915-&gt;runtime_pm, wakeref)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c<br/>index 27f6561dd731..3872d309ed31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_uc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_uc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_uc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_uc.c</a></div><div class='hunk'>@@ -106,11 +106,6 @@ static void __confirm_options(struct intel_uc *uc)</div><div class='ctx'> 		gt_info(gt,  "Incompatible option enable_guc=%d - %s\n",</div><div class='ctx'> 			i915-&gt;params.enable_guc, "GuC is not supported!");</div><div class='ctx'> </div><div class='del'>-	if (i915-&gt;params.enable_guc &amp; ENABLE_GUC_LOAD_HUC &amp;&amp;</div><div class='del'>-	    !intel_uc_supports_huc(uc))</div><div class='del'>-		gt_info(gt, "Incompatible option enable_guc=%d - %s\n",</div><div class='del'>-			i915-&gt;params.enable_guc, "HuC is not supported!");</div><div class='del'>-</div><div class='ctx'> 	if (i915-&gt;params.enable_guc &amp; ENABLE_GUC_SUBMISSION &amp;&amp;</div><div class='ctx'> 	    !intel_uc_supports_guc_submission(uc))</div><div class='ctx'> 		gt_info(gt, "Incompatible option enable_guc=%d - %s\n",</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c<br/>index 362639162ed6..756093eaf2ad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c</a></div><div class='hunk'>@@ -1343,16 +1343,13 @@ size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)</div><div class='ctx'> </div><div class='ctx'> 		for_each_sgt_page(page, iter, uc_fw-&gt;obj-&gt;mm.pages) {</div><div class='ctx'> 			u32 len = min_t(u32, size, PAGE_SIZE - offset);</div><div class='del'>-			void *vaddr;</div><div class='ctx'> </div><div class='ctx'> 			if (idx &gt; 0) {</div><div class='ctx'> 				idx--;</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			vaddr = kmap_atomic(page);</div><div class='del'>-			memcpy(dst, vaddr + offset, len);</div><div class='del'>-			kunmap_atomic(vaddr);</div><div class='add'>+			memcpy_from_page(dst, page, offset, len);</div><div class='ctx'> </div><div class='ctx'> 			offset = 0;</div><div class='ctx'> 			dst += len;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c<br/>index bfb72143566f..c900aac85adb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/selftest_guc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/selftest_guc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/selftest_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/selftest_guc.c</a></div><div class='hunk'>@@ -286,11 +286,126 @@ err_wakeref:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Send a context schedule H2G message with an invalid context id.</div><div class='add'>+ * This should generate a GUC_RESULT_INVALID_CONTEXT response.</div><div class='add'>+ */</div><div class='add'>+static int bad_h2g(struct intel_guc *guc)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+	   INTEL_GUC_ACTION_SCHED_CONTEXT,</div><div class='add'>+	   0x12345678,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return intel_guc_send_nb(guc, action, ARRAY_SIZE(action), 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Set a spinner running to make sure the system is alive and active,</div><div class='add'>+ * then send a bad but asynchronous H2G command and wait to see if an</div><div class='add'>+ * error response is returned. If no response is received or if the</div><div class='add'>+ * spinner dies then the test will fail.</div><div class='add'>+ */</div><div class='add'>+#define FAST_RESPONSE_TIMEOUT_MS	1000</div><div class='add'>+static int intel_guc_fast_request(void *arg)</div><div class='add'>+{</div><div class='add'>+	struct intel_gt *gt = arg;</div><div class='add'>+	struct intel_context *ce;</div><div class='add'>+	struct igt_spinner spin;</div><div class='add'>+	struct i915_request *rq;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='add'>+	struct intel_engine_cs *engine = intel_selftest_find_any_engine(gt);</div><div class='add'>+	bool spinning = false;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!engine)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	wakeref = intel_runtime_pm_get(gt-&gt;uncore-&gt;rpm);</div><div class='add'>+</div><div class='add'>+	ce = intel_context_create(engine);</div><div class='add'>+	if (IS_ERR(ce)) {</div><div class='add'>+		ret = PTR_ERR(ce);</div><div class='add'>+		gt_err(gt, "Failed to create spinner request: %pe\n", ce);</div><div class='add'>+		goto err_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = igt_spinner_init(&amp;spin, engine-&gt;gt);</div><div class='add'>+	if (ret) {</div><div class='add'>+		gt_err(gt, "Failed to create spinner: %pe\n", ERR_PTR(ret));</div><div class='add'>+		goto err_pm;</div><div class='add'>+	}</div><div class='add'>+	spinning = true;</div><div class='add'>+</div><div class='add'>+	rq = igt_spinner_create_request(&amp;spin, ce, MI_ARB_CHECK);</div><div class='add'>+	intel_context_put(ce);</div><div class='add'>+	if (IS_ERR(rq)) {</div><div class='add'>+		ret = PTR_ERR(rq);</div><div class='add'>+		gt_err(gt, "Failed to create spinner request: %pe\n", rq);</div><div class='add'>+		goto err_spin;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = request_add_spin(rq, &amp;spin);</div><div class='add'>+	if (ret) {</div><div class='add'>+		gt_err(gt, "Failed to add Spinner request: %pe\n", ERR_PTR(ret));</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt-&gt;uc.guc.fast_response_selftest = 1;</div><div class='add'>+</div><div class='add'>+	ret = bad_h2g(&amp;gt-&gt;uc.guc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		gt_err(gt, "Failed to send H2G: %pe\n", ERR_PTR(ret));</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wait_for(gt-&gt;uc.guc.fast_response_selftest != 1 || i915_request_completed(rq),</div><div class='add'>+		       FAST_RESPONSE_TIMEOUT_MS);</div><div class='add'>+	if (ret) {</div><div class='add'>+		gt_err(gt, "Request wait failed: %pe\n", ERR_PTR(ret));</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i915_request_completed(rq)) {</div><div class='add'>+		gt_err(gt, "Spinner died waiting for fast request error!\n");</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;uc.guc.fast_response_selftest != 2) {</div><div class='add'>+		gt_err(gt, "Unexpected fast response count: %d\n",</div><div class='add'>+		       gt-&gt;uc.guc.fast_response_selftest);</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	igt_spinner_end(&amp;spin);</div><div class='add'>+	spinning = false;</div><div class='add'>+</div><div class='add'>+	ret = intel_selftest_wait_for_rq(rq);</div><div class='add'>+	if (ret) {</div><div class='add'>+		gt_err(gt, "Request failed to complete: %pe\n", ERR_PTR(ret));</div><div class='add'>+		goto err_rq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err_rq:</div><div class='add'>+	i915_request_put(rq);</div><div class='add'>+</div><div class='add'>+err_spin:</div><div class='add'>+	if (spinning)</div><div class='add'>+		igt_spinner_end(&amp;spin);</div><div class='add'>+	igt_spinner_fini(&amp;spin);</div><div class='add'>+</div><div class='add'>+err_pm:</div><div class='add'>+	intel_runtime_pm_put(gt-&gt;uncore-&gt;rpm, wakeref);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int intel_guc_live_selftests(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> 	static const struct i915_subtest tests[] = {</div><div class='ctx'> 		SUBTEST(intel_guc_scrub_ctbs),</div><div class='ctx'> 		SUBTEST(intel_guc_steal_guc_ids),</div><div class='add'>+		SUBTEST(intel_guc_fast_request),</div><div class='ctx'> 	};</div><div class='ctx'> 	struct intel_gt *gt = to_gt(i915);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c<br/>index 34b5d952e2bc..26fdc392fce6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c</a></div><div class='hunk'>@@ -74,7 +74,7 @@ static int intel_hang_guc(void *arg)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rq = igt_spinner_create_request(&amp;spin, ce, MI_NOOP);</div><div class='add'>+	rq = igt_spinner_create_request(&amp;spin, ce, MI_ARB_CHECK);</div><div class='ctx'> 	intel_context_put(ce);</div><div class='ctx'> 	if (IS_ERR(rq)) {</div><div class='ctx'> 		ret = PTR_ERR(rq);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c<br/>index de3f5903d1a7..c8e7dfc9f791 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gvt/interrupt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/gvt/interrupt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/gvt/interrupt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/gvt/interrupt.c</a></div><div class='hunk'>@@ -422,7 +422,7 @@ static void init_irq_map(struct intel_gvt_irq *irq)</div><div class='ctx'> #define MSI_CAP_DATA(offset) (offset + 8)</div><div class='ctx'> #define MSI_CAP_EN 0x1</div><div class='ctx'> </div><div class='del'>-static int inject_virtual_interrupt(struct intel_vgpu *vgpu)</div><div class='add'>+static void inject_virtual_interrupt(struct intel_vgpu *vgpu)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long offset = vgpu-&gt;gvt-&gt;device_info.msi_cap_offset;</div><div class='ctx'> 	u16 control, data;</div><div class='hunk'>@@ -434,10 +434,10 @@ static int inject_virtual_interrupt(struct intel_vgpu *vgpu)</div><div class='ctx'> </div><div class='ctx'> 	/* Do not generate MSI if MSIEN is disabled */</div><div class='ctx'> 	if (!(control &amp; MSI_CAP_EN))</div><div class='del'>-		return 0;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN(control &amp; GENMASK(15, 1), "only support one MSI format\n"))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	trace_inject_msi(vgpu-&gt;id, addr, data);</div><div class='ctx'> </div><div class='hunk'>@@ -451,10 +451,9 @@ static int inject_virtual_interrupt(struct intel_vgpu *vgpu)</div><div class='ctx'> 	 * returned and don't inject interrupt into guest.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu-&gt;status))</div><div class='del'>-		return -ESRCH;</div><div class='del'>-	if (vgpu-&gt;msi_trigger &amp;&amp; eventfd_signal(vgpu-&gt;msi_trigger, 1) != 1)</div><div class='del'>-		return -EFAULT;</div><div class='del'>-	return 0;</div><div class='add'>+		return;</div><div class='add'>+	if (vgpu-&gt;msi_trigger)</div><div class='add'>+		eventfd_signal(vgpu-&gt;msi_trigger);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void propagate_event(struct intel_gvt_irq *irq,</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c<br/>index ddf49c2dbb91..2905df83e180 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_cmd_parser.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_cmd_parser.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_cmd_parser.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_cmd_parser.c</a></div><div class='hunk'>@@ -1211,11 +1211,11 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,</div><div class='ctx'> 		for (n = offset &gt;&gt; PAGE_SHIFT; remain; n++) {</div><div class='ctx'> 			int len = min(remain, PAGE_SIZE - x);</div><div class='ctx'> </div><div class='del'>-			src = kmap_atomic(i915_gem_object_get_page(src_obj, n));</div><div class='add'>+			src = kmap_local_page(i915_gem_object_get_page(src_obj, n));</div><div class='ctx'> 			if (src_needs_clflush)</div><div class='ctx'> 				drm_clflush_virt_range(src + x, len);</div><div class='ctx'> 			memcpy(ptr, src + x, len);</div><div class='del'>-			kunmap_atomic(src);</div><div class='add'>+			kunmap_local(src);</div><div class='ctx'> </div><div class='ctx'> 			ptr += len;</div><div class='ctx'> 			remain -= len;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c<br/>index bfe92d2402ea..db99c2ef66db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_debugfs.c</a></div><div class='hunk'>@@ -51,6 +51,7 @@</div><div class='ctx'> #include "i915_debugfs.h"</div><div class='ctx'> #include "i915_debugfs_params.h"</div><div class='ctx'> #include "i915_driver.h"</div><div class='add'>+#include "i915_gpu_error.h"</div><div class='ctx'> #include "i915_irq.h"</div><div class='ctx'> #include "i915_reg.h"</div><div class='ctx'> #include "i915_scheduler.h"</div><div class='hunk'>@@ -299,107 +300,6 @@ static int i915_gem_object_info(struct seq_file *m, void *data)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)</div><div class='del'>-static ssize_t gpu_state_read(struct file *file, char __user *ubuf,</div><div class='del'>-			      size_t count, loff_t *pos)</div><div class='del'>-{</div><div class='del'>-	struct i915_gpu_coredump *error;</div><div class='del'>-	ssize_t ret;</div><div class='del'>-	void *buf;</div><div class='del'>-</div><div class='del'>-	error = file-&gt;private_data;</div><div class='del'>-	if (!error)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Bounce buffer required because of kernfs __user API convenience. */</div><div class='del'>-	buf = kmalloc(count, GFP_KERNEL);</div><div class='del'>-	if (!buf)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);</div><div class='del'>-	if (ret &lt;= 0)</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	if (!copy_to_user(ubuf, buf, ret))</div><div class='del'>-		*pos += ret;</div><div class='del'>-	else</div><div class='del'>-		ret = -EFAULT;</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	kfree(buf);</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int gpu_state_release(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	i915_gpu_coredump_put(file-&gt;private_data);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int i915_gpu_info_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct drm_i915_private *i915 = inode-&gt;i_private;</div><div class='del'>-	struct i915_gpu_coredump *gpu;</div><div class='del'>-	intel_wakeref_t wakeref;</div><div class='del'>-</div><div class='del'>-	gpu = NULL;</div><div class='del'>-	with_intel_runtime_pm(&amp;i915-&gt;runtime_pm, wakeref)</div><div class='del'>-		gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);</div><div class='del'>-</div><div class='del'>-	if (IS_ERR(gpu))</div><div class='del'>-		return PTR_ERR(gpu);</div><div class='del'>-</div><div class='del'>-	file-&gt;private_data = gpu;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct file_operations i915_gpu_info_fops = {</div><div class='del'>-	.owner = THIS_MODULE,</div><div class='del'>-	.open = i915_gpu_info_open,</div><div class='del'>-	.read = gpu_state_read,</div><div class='del'>-	.llseek = default_llseek,</div><div class='del'>-	.release = gpu_state_release,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static ssize_t</div><div class='del'>-i915_error_state_write(struct file *filp,</div><div class='del'>-		       const char __user *ubuf,</div><div class='del'>-		       size_t cnt,</div><div class='del'>-		       loff_t *ppos)</div><div class='del'>-{</div><div class='del'>-	struct i915_gpu_coredump *error = filp-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	if (!error)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	drm_dbg(&amp;error-&gt;i915-&gt;drm, "Resetting error state\n");</div><div class='del'>-	i915_reset_error_state(error-&gt;i915);</div><div class='del'>-</div><div class='del'>-	return cnt;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int i915_error_state_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct i915_gpu_coredump *error;</div><div class='del'>-</div><div class='del'>-	error = i915_first_error_state(inode-&gt;i_private);</div><div class='del'>-	if (IS_ERR(error))</div><div class='del'>-		return PTR_ERR(error);</div><div class='del'>-</div><div class='del'>-	file-&gt;private_data  = error;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct file_operations i915_error_state_fops = {</div><div class='del'>-	.owner = THIS_MODULE,</div><div class='del'>-	.open = i915_error_state_open,</div><div class='del'>-	.read = gpu_state_read,</div><div class='del'>-	.write = i915_error_state_write,</div><div class='del'>-	.llseek = default_llseek,</div><div class='del'>-	.release = gpu_state_release,</div><div class='del'>-};</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> static int i915_frequency_info(struct seq_file *m, void *unused)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_i915_private *i915 = node_to_i915(m-&gt;private);</div><div class='hunk'>@@ -839,10 +739,6 @@ static const struct i915_debugfs_files {</div><div class='ctx'> 	{"i915_perf_noa_delay", &amp;i915_perf_noa_delay_fops},</div><div class='ctx'> 	{"i915_wedged", &amp;i915_wedged_fops},</div><div class='ctx'> 	{"i915_gem_drop_caches", &amp;i915_drop_caches_fops},</div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)</div><div class='del'>-	{"i915_error_state", &amp;i915_error_state_fops},</div><div class='del'>-	{"i915_gpu_info", &amp;i915_gpu_info_fops},</div><div class='del'>-#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void i915_debugfs_register(struct drm_i915_private *dev_priv)</div><div class='hunk'>@@ -865,4 +761,6 @@ void i915_debugfs_register(struct drm_i915_private *dev_priv)</div><div class='ctx'> 	drm_debugfs_create_files(i915_debugfs_list,</div><div class='ctx'> 				 ARRAY_SIZE(i915_debugfs_list),</div><div class='ctx'> 				 minor-&gt;debugfs_root, minor);</div><div class='add'>+</div><div class='add'>+	i915_gpu_error_debugfs_register(dev_priv);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c<br/>index 2a1faf403965..c7d7c3b7ecc6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_driver.c</a></div><div class='hunk'>@@ -798,7 +798,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_cleanup_modeset2;</div><div class='ctx'> </div><div class='del'>-	intel_pxp_init(i915);</div><div class='add'>+	ret = intel_pxp_init(i915);</div><div class='add'>+	if (ret != -ENODEV)</div><div class='add'>+		drm_dbg(&amp;i915-&gt;drm, "pxp init failed with %d\n", ret);</div><div class='ctx'> </div><div class='ctx'> 	ret = intel_display_driver_probe(i915);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1033,7 +1035,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)</div><div class='ctx'> 	intel_power_domains_driver_remove(i915);</div><div class='ctx'> 	enable_rpm_wakeref_asserts(&amp;i915-&gt;runtime_pm);</div><div class='ctx'> </div><div class='del'>-	intel_runtime_pm_driver_release(&amp;i915-&gt;runtime_pm);</div><div class='add'>+	intel_runtime_pm_driver_last_release(&amp;i915-&gt;runtime_pm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool suspend_to_idle(struct drm_i915_private *dev_priv)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c<br/>index 2a44b3876cb5..fa6852713bee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_drm_client.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_drm_client.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_drm_client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_drm_client.c</a></div><div class='hunk'>@@ -28,6 +28,10 @@ struct i915_drm_client *i915_drm_client_alloc(void)</div><div class='ctx'> 	kref_init(&amp;client-&gt;kref);</div><div class='ctx'> 	spin_lock_init(&amp;client-&gt;ctx_lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;client-&gt;ctx_list);</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	spin_lock_init(&amp;client-&gt;objects_lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;client-&gt;objects_list);</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> 	return client;</div><div class='ctx'> }</div><div class='hunk'>@@ -41,6 +45,68 @@ void __i915_drm_client_free(struct kref *kref)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PROC_FS</div><div class='add'>+static void</div><div class='add'>+obj_meminfo(struct drm_i915_gem_object *obj,</div><div class='add'>+	    struct drm_memory_stats stats[INTEL_REGION_UNKNOWN])</div><div class='add'>+{</div><div class='add'>+	const enum intel_region_id id = obj-&gt;mm.region ?</div><div class='add'>+					obj-&gt;mm.region-&gt;id : INTEL_REGION_SMEM;</div><div class='add'>+	const u64 sz = obj-&gt;base.size;</div><div class='add'>+</div><div class='add'>+	if (obj-&gt;base.handle_count &gt; 1)</div><div class='add'>+		stats[id].shared += sz;</div><div class='add'>+	else</div><div class='add'>+		stats[id].private += sz;</div><div class='add'>+</div><div class='add'>+	if (i915_gem_object_has_pages(obj)) {</div><div class='add'>+		stats[id].resident += sz;</div><div class='add'>+</div><div class='add'>+		if (!dma_resv_test_signaled(obj-&gt;base.resv,</div><div class='add'>+					    DMA_RESV_USAGE_BOOKKEEP))</div><div class='add'>+			stats[id].active += sz;</div><div class='add'>+		else if (i915_gem_object_is_shrinkable(obj) &amp;&amp;</div><div class='add'>+			 obj-&gt;mm.madv == I915_MADV_DONTNEED)</div><div class='add'>+			stats[id].purgeable += sz;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void show_meminfo(struct drm_printer *p, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct drm_memory_stats stats[INTEL_REGION_UNKNOWN] = {};</div><div class='add'>+	struct drm_i915_file_private *fpriv = file-&gt;driver_priv;</div><div class='add'>+	struct i915_drm_client *client = fpriv-&gt;client;</div><div class='add'>+	struct drm_i915_private *i915 = fpriv-&gt;i915;</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+	struct intel_memory_region *mr;</div><div class='add'>+	struct list_head __rcu *pos;</div><div class='add'>+	unsigned int id;</div><div class='add'>+</div><div class='add'>+	/* Public objects. */</div><div class='add'>+	spin_lock(&amp;file-&gt;table_lock);</div><div class='add'>+	idr_for_each_entry(&amp;file-&gt;object_idr, obj, id)</div><div class='add'>+		obj_meminfo(obj, stats);</div><div class='add'>+	spin_unlock(&amp;file-&gt;table_lock);</div><div class='add'>+</div><div class='add'>+	/* Internal objects. */</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	list_for_each_rcu(pos, &amp;client-&gt;objects_list) {</div><div class='add'>+		obj = i915_gem_object_get_rcu(list_entry(pos, typeof(*obj),</div><div class='add'>+							 client_link));</div><div class='add'>+		if (!obj)</div><div class='add'>+			continue;</div><div class='add'>+		obj_meminfo(obj, stats);</div><div class='add'>+		i915_gem_object_put(obj);</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+</div><div class='add'>+	for_each_memory_region(mr, i915, id)</div><div class='add'>+		drm_print_memory_stats(p,</div><div class='add'>+				       &amp;stats[id],</div><div class='add'>+				       DRM_GEM_OBJECT_RESIDENT |</div><div class='add'>+				       DRM_GEM_OBJECT_PURGEABLE,</div><div class='add'>+				       mr-&gt;uabi_name);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const char * const uabi_class_names[] = {</div><div class='ctx'> 	[I915_ENGINE_CLASS_RENDER] = "render",</div><div class='ctx'> 	[I915_ENGINE_CLASS_COPY] = "copy",</div><div class='hunk'>@@ -102,10 +168,52 @@ void i915_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file)</div><div class='ctx'> 	 * ******************************************************************</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='add'>+	show_meminfo(p, file);</div><div class='add'>+</div><div class='ctx'> 	if (GRAPHICS_VER(i915) &lt; 8)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(uabi_class_names); i++)</div><div class='ctx'> 		show_client_class(p, i915, file_priv-&gt;client, i);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void i915_drm_client_add_object(struct i915_drm_client *client,</div><div class='add'>+				struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	GEM_WARN_ON(obj-&gt;client);</div><div class='add'>+	GEM_WARN_ON(!list_empty(&amp;obj-&gt;client_link));</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;client-&gt;objects_lock, flags);</div><div class='add'>+	obj-&gt;client = i915_drm_client_get(client);</div><div class='add'>+	list_add_tail_rcu(&amp;obj-&gt;client_link, &amp;client-&gt;objects_list);</div><div class='add'>+	spin_unlock_irqrestore(&amp;client-&gt;objects_lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void i915_drm_client_remove_object(struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	struct i915_drm_client *client = fetch_and_zero(&amp;obj-&gt;client);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	/* Object may not be associated with a client. */</div><div class='add'>+	if (!client)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;client-&gt;objects_lock, flags);</div><div class='add'>+	list_del_rcu(&amp;obj-&gt;client_link);</div><div class='add'>+	spin_unlock_irqrestore(&amp;client-&gt;objects_lock, flags);</div><div class='add'>+</div><div class='add'>+	i915_drm_client_put(client);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void i915_drm_client_add_context_objects(struct i915_drm_client *client,</div><div class='add'>+					 struct intel_context *ce)</div><div class='add'>+{</div><div class='add'>+	if (ce-&gt;state)</div><div class='add'>+		i915_drm_client_add_object(client, ce-&gt;state-&gt;obj);</div><div class='add'>+</div><div class='add'>+	if (ce-&gt;ring != ce-&gt;engine-&gt;legacy.ring &amp;&amp; ce-&gt;ring-&gt;vma)</div><div class='add'>+		i915_drm_client_add_object(client, ce-&gt;ring-&gt;vma-&gt;obj);</div><div class='add'>+}</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h<br/>index 67816c912bca..a439dd789936 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_drm_client.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_drm_client.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_drm_client.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_drm_client.h</a></div><div class='hunk'>@@ -12,6 +12,10 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;uapi/drm/i915_drm.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "i915_file_private.h"</div><div class='add'>+#include "gem/i915_gem_object_types.h"</div><div class='add'>+#include "gt/intel_context_types.h"</div><div class='add'>+</div><div class='ctx'> #define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE</div><div class='ctx'> </div><div class='ctx'> struct drm_file;</div><div class='hunk'>@@ -25,6 +29,20 @@ struct i915_drm_client {</div><div class='ctx'> 	spinlock_t ctx_lock; /* For add/remove from ctx_list. */</div><div class='ctx'> 	struct list_head ctx_list; /* List of contexts belonging to client. */</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	/**</div><div class='add'>+	 * @objects_lock: lock protecting @objects_list</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t objects_lock;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @objects_list: list of objects created by this client</div><div class='add'>+	 *</div><div class='add'>+	 * Protected by @objects_lock.</div><div class='add'>+	 */</div><div class='add'>+	struct list_head objects_list;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * @past_runtime: Accumulation of pphwsp runtimes from closed contexts.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -49,4 +67,28 @@ struct i915_drm_client *i915_drm_client_alloc(void);</div><div class='ctx'> </div><div class='ctx'> void i915_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+void i915_drm_client_add_object(struct i915_drm_client *client,</div><div class='add'>+				struct drm_i915_gem_object *obj);</div><div class='add'>+void i915_drm_client_remove_object(struct drm_i915_gem_object *obj);</div><div class='add'>+void i915_drm_client_add_context_objects(struct i915_drm_client *client,</div><div class='add'>+					 struct intel_context *ce);</div><div class='add'>+#else</div><div class='add'>+static inline void i915_drm_client_add_object(struct i915_drm_client *client,</div><div class='add'>+					      struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+i915_drm_client_remove_object(struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+i915_drm_client_add_context_objects(struct i915_drm_client *client,</div><div class='add'>+				    struct intel_context *ce)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> #endif /* !__I915_DRM_CLIENT_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c<br/>index 0971f4976324..d04660b60046 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_gpu_error.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_gpu_error.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_gpu_error.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_gpu_error.c</a></div><div class='hunk'>@@ -57,6 +57,7 @@</div><div class='ctx'> #include "i915_memcpy.h"</div><div class='ctx'> #include "i915_reg.h"</div><div class='ctx'> #include "i915_scatterlist.h"</div><div class='add'>+#include "i915_sysfs.h"</div><div class='ctx'> #include "i915_utils.h"</div><div class='ctx'> </div><div class='ctx'> #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)</div><div class='hunk'>@@ -520,7 +521,7 @@ __find_vma(struct i915_vma_coredump *vma, const char *name)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct i915_vma_coredump *</div><div class='add'>+static struct i915_vma_coredump *</div><div class='ctx'> intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)</div><div class='ctx'> {</div><div class='ctx'> 	return __find_vma(ee-&gt;vma, "batch");</div><div class='hunk'>@@ -609,9 +610,9 @@ void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)</div><div class='ctx'> 	va_end(args);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,</div><div class='del'>-			       const struct intel_engine_cs *engine,</div><div class='del'>-			       const struct i915_vma_coredump *vma)</div><div class='add'>+static void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,</div><div class='add'>+				      const struct intel_engine_cs *engine,</div><div class='add'>+				      const struct i915_vma_coredump *vma)</div><div class='ctx'> {</div><div class='ctx'> 	char out[ASCII85_BUFSZ];</div><div class='ctx'> 	struct page *page;</div><div class='hunk'>@@ -2140,7 +2141,7 @@ __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 du</div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct i915_gpu_coredump *</div><div class='add'>+static struct i915_gpu_coredump *</div><div class='ctx'> i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)</div><div class='ctx'> {</div><div class='ctx'> 	static DEFINE_MUTEX(capture_mutex);</div><div class='hunk'>@@ -2211,7 +2212,7 @@ void i915_capture_error_state(struct intel_gt *gt,</div><div class='ctx'> 	i915_gpu_coredump_put(error);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct i915_gpu_coredump *</div><div class='add'>+static struct i915_gpu_coredump *</div><div class='ctx'> i915_first_error_state(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> 	struct i915_gpu_coredump *error;</div><div class='hunk'>@@ -2378,3 +2379,184 @@ void intel_klog_error_capture(struct intel_gt *gt,</div><div class='ctx'> 	drm_info(&amp;i915-&gt;drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='add'>+</div><div class='add'>+static ssize_t gpu_state_read(struct file *file, char __user *ubuf,</div><div class='add'>+			      size_t count, loff_t *pos)</div><div class='add'>+{</div><div class='add'>+	struct i915_gpu_coredump *error;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+	void *buf;</div><div class='add'>+</div><div class='add'>+	error = file-&gt;private_data;</div><div class='add'>+	if (!error)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Bounce buffer required because of kernfs __user API convenience. */</div><div class='add'>+	buf = kmalloc(count, GFP_KERNEL);</div><div class='add'>+	if (!buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);</div><div class='add'>+	if (ret &lt;= 0)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (!copy_to_user(ubuf, buf, ret))</div><div class='add'>+		*pos += ret;</div><div class='add'>+	else</div><div class='add'>+		ret = -EFAULT;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(buf);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gpu_state_release(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	i915_gpu_coredump_put(file-&gt;private_data);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int i915_gpu_info_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = inode-&gt;i_private;</div><div class='add'>+	struct i915_gpu_coredump *gpu;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='add'>+</div><div class='add'>+	gpu = NULL;</div><div class='add'>+	with_intel_runtime_pm(&amp;i915-&gt;runtime_pm, wakeref)</div><div class='add'>+		gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(gpu))</div><div class='add'>+		return PTR_ERR(gpu);</div><div class='add'>+</div><div class='add'>+	file-&gt;private_data = gpu;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations i915_gpu_info_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = i915_gpu_info_open,</div><div class='add'>+	.read = gpu_state_read,</div><div class='add'>+	.llseek = default_llseek,</div><div class='add'>+	.release = gpu_state_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+i915_error_state_write(struct file *filp,</div><div class='add'>+		       const char __user *ubuf,</div><div class='add'>+		       size_t cnt,</div><div class='add'>+		       loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct i915_gpu_coredump *error = filp-&gt;private_data;</div><div class='add'>+</div><div class='add'>+	if (!error)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;error-&gt;i915-&gt;drm, "Resetting error state\n");</div><div class='add'>+	i915_reset_error_state(error-&gt;i915);</div><div class='add'>+</div><div class='add'>+	return cnt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int i915_error_state_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	struct i915_gpu_coredump *error;</div><div class='add'>+</div><div class='add'>+	error = i915_first_error_state(inode-&gt;i_private);</div><div class='add'>+	if (IS_ERR(error))</div><div class='add'>+		return PTR_ERR(error);</div><div class='add'>+</div><div class='add'>+	file-&gt;private_data  = error;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations i915_error_state_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = i915_error_state_open,</div><div class='add'>+	.read = gpu_state_read,</div><div class='add'>+	.write = i915_error_state_write,</div><div class='add'>+	.llseek = default_llseek,</div><div class='add'>+	.release = gpu_state_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	struct drm_minor *minor = i915-&gt;drm.primary;</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("i915_error_state", 0644, minor-&gt;debugfs_root, i915,</div><div class='add'>+			    &amp;i915_error_state_fops);</div><div class='add'>+	debugfs_create_file("i915_gpu_info", 0644, minor-&gt;debugfs_root, i915,</div><div class='add'>+			    &amp;i915_gpu_info_fops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t error_state_read(struct file *filp, struct kobject *kobj,</div><div class='add'>+				struct bin_attribute *attr, char *buf,</div><div class='add'>+				loff_t off, size_t count)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	struct device *kdev = kobj_to_dev(kobj);</div><div class='add'>+	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);</div><div class='add'>+	struct i915_gpu_coredump *gpu;</div><div class='add'>+	ssize_t ret = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Concurrent clients triggering resets and reading + clearing</div><div class='add'>+	 * dumps can cause inconsistent sysfs reads when a user calls in with a</div><div class='add'>+	 * non-zero offset to complete a prior partial read but the</div><div class='add'>+	 * gpu_coredump has been cleared or replaced.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	gpu = i915_first_error_state(i915);</div><div class='add'>+	if (IS_ERR(gpu)) {</div><div class='add'>+		ret = PTR_ERR(gpu);</div><div class='add'>+	} else if (gpu) {</div><div class='add'>+		ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);</div><div class='add'>+		i915_gpu_coredump_put(gpu);</div><div class='add'>+	} else {</div><div class='add'>+		const char *str = "No error state collected\n";</div><div class='add'>+		size_t len = strlen(str);</div><div class='add'>+</div><div class='add'>+		if (off &lt; len) {</div><div class='add'>+			ret = min_t(size_t, count, len - off);</div><div class='add'>+			memcpy(buf, str + off, ret);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t error_state_write(struct file *file, struct kobject *kobj,</div><div class='add'>+				 struct bin_attribute *attr, char *buf,</div><div class='add'>+				 loff_t off, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct device *kdev = kobj_to_dev(kobj);</div><div class='add'>+	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;dev_priv-&gt;drm, "Resetting error state\n");</div><div class='add'>+	i915_reset_error_state(dev_priv);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct bin_attribute error_state_attr = {</div><div class='add'>+	.attr.name = "error",</div><div class='add'>+	.attr.mode = S_IRUSR | S_IWUSR,</div><div class='add'>+	.size = 0,</div><div class='add'>+	.read = error_state_read,</div><div class='add'>+	.write = error_state_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	struct device *kdev = i915-&gt;drm.primary-&gt;kdev;</div><div class='add'>+</div><div class='add'>+	if (sysfs_create_bin_file(&amp;kdev-&gt;kobj, &amp;error_state_attr))</div><div class='add'>+		drm_err(&amp;i915-&gt;drm, "error_state sysfs setup failed\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	struct device *kdev = i915-&gt;drm.primary-&gt;kdev;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_bin_file(&amp;kdev-&gt;kobj, &amp;error_state_attr);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h<br/>index 4ce227f7e1e1..7c255bb1c319 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_gpu_error.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_gpu_error.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_gpu_error.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_gpu_error.h</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> #include "display/intel_display_device.h"</div><div class='ctx'> #include "display/intel_display_params.h"</div><div class='ctx'> #include "gt/intel_engine.h"</div><div class='add'>+#include "gt/intel_engine_types.h"</div><div class='ctx'> #include "gt/intel_gt_types.h"</div><div class='ctx'> #include "gt/uc/intel_uc_fw.h"</div><div class='ctx'> </div><div class='hunk'>@@ -234,7 +235,7 @@ struct i915_gpu_error {</div><div class='ctx'> 	atomic_t reset_count;</div><div class='ctx'> </div><div class='ctx'> 	/** Number of times an engine has been reset */</div><div class='del'>-	atomic_t reset_engine_count[I915_NUM_ENGINES];</div><div class='add'>+	atomic_t reset_engine_count[MAX_ENGINE_CLASS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct drm_i915_error_state_buf {</div><div class='hunk'>@@ -257,7 +258,14 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)</div><div class='ctx'> static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,</div><div class='ctx'> 					  const struct intel_engine_cs *engine)</div><div class='ctx'> {</div><div class='del'>-	return atomic_read(&amp;error-&gt;reset_engine_count[engine-&gt;uabi_class]);</div><div class='add'>+	return atomic_read(&amp;error-&gt;reset_engine_count[engine-&gt;class]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+i915_increase_reset_engine_count(struct i915_gpu_error *error,</div><div class='add'>+				 const struct intel_engine_cs *engine)</div><div class='add'>+{</div><div class='add'>+	atomic_inc(&amp;error-&gt;reset_engine_count[engine-&gt;class]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define CORE_DUMP_FLAG_NONE           0x0</div><div class='hunk'>@@ -277,14 +285,7 @@ static inline void intel_klog_error_capture(struct intel_gt *gt,</div><div class='ctx'> </div><div class='ctx'> __printf(2, 3)</div><div class='ctx'> void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);</div><div class='del'>-void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,</div><div class='del'>-			       const struct intel_engine_cs *engine,</div><div class='del'>-			       const struct i915_vma_coredump *vma);</div><div class='del'>-struct i915_vma_coredump *</div><div class='del'>-intel_gpu_error_find_batch(const struct intel_engine_coredump *ee);</div><div class='del'>-</div><div class='del'>-struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,</div><div class='del'>-					    intel_engine_mask_t engine_mask, u32 dump_flags);</div><div class='add'>+</div><div class='ctx'> void i915_capture_error_state(struct intel_gt *gt,</div><div class='ctx'> 			      intel_engine_mask_t engine_mask, u32 dump_flags);</div><div class='ctx'> </div><div class='hunk'>@@ -332,10 +333,13 @@ static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)</div><div class='ctx'> 		kref_put(&amp;gpu-&gt;ref, __i915_gpu_coredump_free);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);</div><div class='ctx'> void i915_reset_error_state(struct drm_i915_private *i915);</div><div class='ctx'> void i915_disable_error_state(struct drm_i915_private *i915, int err);</div><div class='ctx'> </div><div class='add'>+void i915_gpu_error_debugfs_register(struct drm_i915_private *i915);</div><div class='add'>+void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915);</div><div class='add'>+void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915);</div><div class='add'>+</div><div class='ctx'> #else</div><div class='ctx'> </div><div class='ctx'> __printf(2, 3)</div><div class='hunk'>@@ -403,12 +407,6 @@ static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline struct i915_gpu_coredump *</div><div class='del'>-i915_first_error_state(struct drm_i915_private *i915)</div><div class='del'>-{</div><div class='del'>-	return ERR_PTR(-ENODEV);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline void i915_reset_error_state(struct drm_i915_private *i915)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='hunk'>@@ -418,6 +416,18 @@ static inline void i915_disable_error_state(struct drm_i915_private *i915,</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void i915_gpu_error_debugfs_register(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void i915_gpu_error_sysfs_teardown(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */</div><div class='ctx'> </div><div class='ctx'> #endif /* _I915_GPU_ERROR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c<br/>index 975da8e7f2a9..8c3f443c8347 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_hwmon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_hwmon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_hwmon.c</a></div><div class='hunk'>@@ -175,7 +175,7 @@ hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr,</div><div class='ctx'> 	 *     tau4 = (4 | x) &lt;&lt; y</div><div class='ctx'> 	 * but add 2 when doing the final right shift to account for units</div><div class='ctx'> 	 */</div><div class='del'>-	tau4 = ((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='add'>+	tau4 = (u64)((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='ctx'> 	/* val in hwmon interface units (millisec) */</div><div class='ctx'> 	out = mul_u64_u32_shr(tau4, SF_TIME, hwmon-&gt;scl_shift_time + x_w);</div><div class='ctx'> </div><div class='hunk'>@@ -211,7 +211,7 @@ hwm_power1_max_interval_store(struct device *dev,</div><div class='ctx'> 	r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);</div><div class='ctx'> 	x = REG_FIELD_GET(PKG_MAX_WIN_X, r);</div><div class='ctx'> 	y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);</div><div class='del'>-	tau4 = ((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='add'>+	tau4 = (u64)((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='ctx'> 	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon-&gt;scl_shift_time + x_w);</div><div class='ctx'> </div><div class='ctx'> 	if (val &gt; max_win)</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_memcpy.c b/drivers/gpu/drm/i915/i915_memcpy.c<br/>index 1b021a4902de..ba82277254b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_memcpy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_memcpy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_memcpy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_memcpy.c</a></div><div class='hunk'>@@ -23,6 +23,8 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/cpufeature.h&gt;</div><div class='ctx'> #include &lt;asm/fpu/api.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "i915_memcpy.h"</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c<br/>index 7b1c8de2f9cb..2d695818f006 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_perf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_perf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_perf.c</a></div><div class='hunk'>@@ -772,10 +772,6 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,</div><div class='ctx'> 		 * The reason field includes flags identifying what</div><div class='ctx'> 		 * triggered this specific report (mostly timer</div><div class='ctx'> 		 * triggered or e.g. due to a context switch).</div><div class='del'>-		 *</div><div class='del'>-		 * In MMIO triggered reports, some platforms do not set the</div><div class='del'>-		 * reason bit in this field and it is valid to have a reason</div><div class='del'>-		 * field of zero.</div><div class='ctx'> 		 */</div><div class='ctx'> 		reason = oa_report_reason(stream, report);</div><div class='ctx'> 		ctx_id = oa_context_id(stream, report32);</div><div class='hunk'>@@ -787,8 +783,41 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * Note: that we don't clear the valid_ctx_bit so userspace can</div><div class='ctx'> 		 * understand that the ID has been squashed by the kernel.</div><div class='add'>+		 *</div><div class='add'>+		 * Update:</div><div class='add'>+		 *</div><div class='add'>+		 * On XEHP platforms the behavior of context id valid bit has</div><div class='add'>+		 * changed compared to prior platforms. To describe this, we</div><div class='add'>+		 * define a few terms:</div><div class='add'>+		 *</div><div class='add'>+		 * context-switch-report: This is a report with the reason type</div><div class='add'>+		 * being context-switch. It is generated when a context switches</div><div class='add'>+		 * out.</div><div class='add'>+		 *</div><div class='add'>+		 * context-valid-bit: A bit that is set in the report ID field</div><div class='add'>+		 * to indicate that a valid context has been loaded.</div><div class='add'>+		 *</div><div class='add'>+		 * gpu-idle: A condition characterized by a</div><div class='add'>+		 * context-switch-report with context-valid-bit set to 0.</div><div class='add'>+		 *</div><div class='add'>+		 * On prior platforms, context-id-valid bit is set to 0 only</div><div class='add'>+		 * when GPU goes idle. In all other reports, it is set to 1.</div><div class='add'>+		 *</div><div class='add'>+		 * On XEHP platforms, context-valid-bit is set to 1 in a context</div><div class='add'>+		 * switch report if a new context switched in. For all other</div><div class='add'>+		 * reports it is set to 0.</div><div class='add'>+		 *</div><div class='add'>+		 * This change in behavior causes an issue with MMIO triggered</div><div class='add'>+		 * reports. MMIO triggered reports have the markers in the</div><div class='add'>+		 * context ID field and the context-valid-bit is 0. The logic</div><div class='add'>+		 * below to squash the context ID would render the report</div><div class='add'>+		 * useless since the user will not be able to find it in the OA</div><div class='add'>+		 * buffer. Since MMIO triggered reports exist only on XEHP,</div><div class='add'>+		 * we should avoid squashing these for XEHP platforms.</div><div class='ctx'> 		 */</div><div class='del'>-		if (oa_report_ctx_invalid(stream, report)) {</div><div class='add'>+</div><div class='add'>+		if (oa_report_ctx_invalid(stream, report) &amp;&amp;</div><div class='add'>+		    GRAPHICS_VER_FULL(stream-&gt;engine-&gt;i915) &lt; IP_VER(12, 50)) {</div><div class='ctx'> 			ctx_id = INVALID_CTX_ID;</div><div class='ctx'> 			oa_context_id_squash(stream, report32);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h<br/>index 13b1ae9b96c7..46445248d193 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_perf_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_perf_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_perf_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_perf_types.h</a></div><div class='hunk'>@@ -291,7 +291,8 @@ struct i915_perf_stream {</div><div class='ctx'> 		int size_exponent;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @ptr_lock: Locks reads and writes to all head/tail state</div><div class='add'>+		 * @oa_buffer.ptr_lock: Locks reads and writes to all</div><div class='add'>+		 * head/tail state</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * Consider: the head and tail pointer state needs to be read</div><div class='ctx'> 		 * consistently from a hrtimer callback (atomic context) and</div><div class='hunk'>@@ -313,7 +314,8 @@ struct i915_perf_stream {</div><div class='ctx'> 		spinlock_t ptr_lock;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @head: Although we can always read back the head pointer register,</div><div class='add'>+		 * @oa_buffer.head: Although we can always read back</div><div class='add'>+		 * the head pointer register,</div><div class='ctx'> 		 * we prefer to avoid trusting the HW state, just to avoid any</div><div class='ctx'> 		 * risk that some hardware condition could * somehow bump the</div><div class='ctx'> 		 * head pointer unpredictably and cause us to forward the wrong</div><div class='hunk'>@@ -322,7 +324,8 @@ struct i915_perf_stream {</div><div class='ctx'> 		u32 head;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @tail: The last verified tail that can be read by userspace.</div><div class='add'>+		 * @oa_buffer.tail: The last verified tail that can be</div><div class='add'>+		 * read by userspace.</div><div class='ctx'> 		 */</div><div class='ctx'> 		u32 tail;</div><div class='ctx'> 	} oa_buffer;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c<br/>index f861863eb7c1..21eb0c5b320d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_pmu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_pmu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_pmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_pmu.c</a></div><div class='hunk'>@@ -31,6 +31,16 @@</div><div class='ctx'> static cpumask_t i915_pmu_cpumask;</div><div class='ctx'> static unsigned int i915_pmu_target_cpu = -1;</div><div class='ctx'> </div><div class='add'>+static struct i915_pmu *event_to_pmu(struct perf_event *event)</div><div class='add'>+{</div><div class='add'>+	return container_of(event-&gt;pmu, struct i915_pmu, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct drm_i915_private *pmu_to_i915(struct i915_pmu *pmu)</div><div class='add'>+{</div><div class='add'>+	return container_of(pmu, struct drm_i915_private, pmu);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u8 engine_config_sample(u64 config)</div><div class='ctx'> {</div><div class='ctx'> 	return config &amp; I915_PMU_SAMPLE_MASK;</div><div class='hunk'>@@ -141,7 +151,7 @@ static u32 frequency_enabled_mask(void)</div><div class='ctx'> </div><div class='ctx'> static bool pmu_needs_timer(struct i915_pmu *pmu)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	u32 enable;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -213,19 +223,19 @@ static u64 get_rc6(struct intel_gt *gt)</div><div class='ctx'> 	struct drm_i915_private *i915 = gt-&gt;i915;</div><div class='ctx'> 	const unsigned int gt_id = gt-&gt;info.id;</div><div class='ctx'> 	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	bool awake = false;</div><div class='ctx'> 	u64 val;</div><div class='ctx'> </div><div class='del'>-	if (intel_gt_pm_get_if_awake(gt)) {</div><div class='add'>+	wakeref = intel_gt_pm_get_if_awake(gt);</div><div class='add'>+	if (wakeref) {</div><div class='ctx'> 		val = __get_rc6(gt);</div><div class='del'>-		intel_gt_pm_put_async(gt);</div><div class='del'>-		awake = true;</div><div class='add'>+		intel_gt_pm_put_async(gt, wakeref);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;pmu-&gt;lock, flags);</div><div class='ctx'> </div><div class='del'>-	if (awake) {</div><div class='add'>+	if (wakeref) {</div><div class='ctx'> 		store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -251,7 +261,7 @@ static u64 get_rc6(struct intel_gt *gt)</div><div class='ctx'> </div><div class='ctx'> static void init_rc6(struct i915_pmu *pmu)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	struct intel_gt *gt;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='hunk'>@@ -429,12 +439,14 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)</div><div class='ctx'> 	const unsigned int gt_id = gt-&gt;info.id;</div><div class='ctx'> 	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='ctx'> 	struct intel_rps *rps = &amp;gt-&gt;rps;</div><div class='add'>+	intel_wakeref_t wakeref;</div><div class='ctx'> </div><div class='ctx'> 	if (!frequency_sampling_enabled(pmu, gt_id))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* Report 0/0 (actual/requested) frequency while parked. */</div><div class='del'>-	if (!intel_gt_pm_get_if_awake(gt))</div><div class='add'>+	wakeref = intel_gt_pm_get_if_awake(gt);</div><div class='add'>+	if (!wakeref)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (pmu-&gt;enable &amp; config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {</div><div class='hunk'>@@ -463,14 +475,13 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)</div><div class='ctx'> 				period_ns / 1000);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	intel_gt_pm_put_async(gt);</div><div class='add'>+	intel_gt_pm_put_async(gt, wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(hrtimer, struct drm_i915_private, pmu.timer);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	struct i915_pmu *pmu = container_of(hrtimer, struct i915_pmu, timer);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	unsigned int period_ns;</div><div class='ctx'> 	struct intel_gt *gt;</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -505,8 +516,8 @@ static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)</div><div class='ctx'> </div><div class='ctx'> static void i915_pmu_event_destroy(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> </div><div class='ctx'> 	drm_WARN_ON(&amp;i915-&gt;drm, event-&gt;parent);</div><div class='ctx'> </div><div class='hunk'>@@ -572,8 +583,8 @@ config_status(struct drm_i915_private *i915, u64 config)</div><div class='ctx'> </div><div class='ctx'> static int engine_event_init(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	struct intel_engine_cs *engine;</div><div class='ctx'> </div><div class='ctx'> 	engine = intel_engine_lookup_user(i915, engine_event_class(event),</div><div class='hunk'>@@ -586,9 +597,8 @@ static int engine_event_init(struct perf_event *event)</div><div class='ctx'> </div><div class='ctx'> static int i915_pmu_event_init(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (pmu-&gt;closed)</div><div class='hunk'>@@ -628,9 +638,8 @@ static int i915_pmu_event_init(struct perf_event *event)</div><div class='ctx'> </div><div class='ctx'> static u64 __i915_pmu_event_read(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	u64 val = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (is_engine_event(event)) {</div><div class='hunk'>@@ -686,10 +695,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event)</div><div class='ctx'> </div><div class='ctx'> static void i915_pmu_event_read(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='ctx'> 	struct hw_perf_event *hwc = &amp;event-&gt;hw;</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='ctx'> 	u64 prev, new;</div><div class='ctx'> </div><div class='ctx'> 	if (pmu-&gt;closed) {</div><div class='hunk'>@@ -707,10 +714,9 @@ static void i915_pmu_event_read(struct perf_event *event)</div><div class='ctx'> </div><div class='ctx'> static void i915_pmu_enable(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	const unsigned int bit = event_bit(event);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (bit == -1)</div><div class='hunk'>@@ -771,10 +777,9 @@ update:</div><div class='ctx'> </div><div class='ctx'> static void i915_pmu_disable(struct perf_event *event)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	const unsigned int bit = event_bit(event);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (bit == -1)</div><div class='hunk'>@@ -818,9 +823,7 @@ static void i915_pmu_disable(struct perf_event *event)</div><div class='ctx'> </div><div class='ctx'> static void i915_pmu_event_start(struct perf_event *event, int flags)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='ctx'> </div><div class='ctx'> 	if (pmu-&gt;closed)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -848,9 +851,7 @@ out:</div><div class='ctx'> </div><div class='ctx'> static int i915_pmu_event_add(struct perf_event *event, int flags)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-		container_of(event-&gt;pmu, typeof(*i915), pmu.base);</div><div class='del'>-	struct i915_pmu *pmu = &amp;i915-&gt;pmu;</div><div class='add'>+	struct i915_pmu *pmu = event_to_pmu(event);</div><div class='ctx'> </div><div class='ctx'> 	if (pmu-&gt;closed)</div><div class='ctx'> 		return -ENODEV;</div><div class='hunk'>@@ -982,7 +983,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,</div><div class='ctx'> static struct attribute **</div><div class='ctx'> create_event_attributes(struct i915_pmu *pmu)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);</div><div class='add'>+	struct drm_i915_private *i915 = pmu_to_i915(pmu);</div><div class='ctx'> 	static const struct {</div><div class='ctx'> 		unsigned int counter;</div><div class='ctx'> 		const char *name;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c<br/>index e88bb4f04305..613decd47760 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/i915_sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/i915_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/i915_sysfs.c</a></div><div class='hunk'>@@ -155,81 +155,6 @@ static const struct bin_attribute dpf_attrs_1 = {</div><div class='ctx'> 	.private = (void *)1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)</div><div class='del'>-</div><div class='del'>-static ssize_t error_state_read(struct file *filp, struct kobject *kobj,</div><div class='del'>-				struct bin_attribute *attr, char *buf,</div><div class='del'>-				loff_t off, size_t count)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-	struct device *kdev = kobj_to_dev(kobj);</div><div class='del'>-	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);</div><div class='del'>-	struct i915_gpu_coredump *gpu;</div><div class='del'>-	ssize_t ret = 0;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * FIXME: Concurrent clients triggering resets and reading + clearing</div><div class='del'>-	 * dumps can cause inconsistent sysfs reads when a user calls in with a</div><div class='del'>-	 * non-zero offset to complete a prior partial read but the</div><div class='del'>-	 * gpu_coredump has been cleared or replaced.</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	gpu = i915_first_error_state(i915);</div><div class='del'>-	if (IS_ERR(gpu)) {</div><div class='del'>-		ret = PTR_ERR(gpu);</div><div class='del'>-	} else if (gpu) {</div><div class='del'>-		ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);</div><div class='del'>-		i915_gpu_coredump_put(gpu);</div><div class='del'>-	} else {</div><div class='del'>-		const char *str = "No error state collected\n";</div><div class='del'>-		size_t len = strlen(str);</div><div class='del'>-</div><div class='del'>-		if (off &lt; len) {</div><div class='del'>-			ret = min_t(size_t, count, len - off);</div><div class='del'>-			memcpy(buf, str + off, ret);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static ssize_t error_state_write(struct file *file, struct kobject *kobj,</div><div class='del'>-				 struct bin_attribute *attr, char *buf,</div><div class='del'>-				 loff_t off, size_t count)</div><div class='del'>-{</div><div class='del'>-	struct device *kdev = kobj_to_dev(kobj);</div><div class='del'>-	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);</div><div class='del'>-</div><div class='del'>-	drm_dbg(&amp;dev_priv-&gt;drm, "Resetting error state\n");</div><div class='del'>-	i915_reset_error_state(dev_priv);</div><div class='del'>-</div><div class='del'>-	return count;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct bin_attribute error_state_attr = {</div><div class='del'>-	.attr.name = "error",</div><div class='del'>-	.attr.mode = S_IRUSR | S_IWUSR,</div><div class='del'>-	.size = 0,</div><div class='del'>-	.read = error_state_read,</div><div class='del'>-	.write = error_state_write,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void i915_setup_error_capture(struct device *kdev)</div><div class='del'>-{</div><div class='del'>-	if (sysfs_create_bin_file(&amp;kdev-&gt;kobj, &amp;error_state_attr))</div><div class='del'>-		drm_err(&amp;kdev_minor_to_i915(kdev)-&gt;drm,</div><div class='del'>-			"error_state sysfs setup failed\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void i915_teardown_error_capture(struct device *kdev)</div><div class='del'>-{</div><div class='del'>-	sysfs_remove_bin_file(&amp;kdev-&gt;kobj, &amp;error_state_attr);</div><div class='del'>-}</div><div class='del'>-#else</div><div class='del'>-static void i915_setup_error_capture(struct device *kdev) {}</div><div class='del'>-static void i915_teardown_error_capture(struct device *kdev) {}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> void i915_setup_sysfs(struct drm_i915_private *dev_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *kdev = dev_priv-&gt;drm.primary-&gt;kdev;</div><div class='hunk'>@@ -255,7 +180,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)</div><div class='ctx'> 		drm_warn(&amp;dev_priv-&gt;drm,</div><div class='ctx'> 			 "failed to register GT sysfs directory\n");</div><div class='ctx'> </div><div class='del'>-	i915_setup_error_capture(kdev);</div><div class='add'>+	i915_gpu_error_sysfs_setup(dev_priv);</div><div class='ctx'> </div><div class='ctx'> 	intel_engines_add_sysfs(dev_priv);</div><div class='ctx'> }</div><div class='hunk'>@@ -264,7 +189,7 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *kdev = dev_priv-&gt;drm.primary-&gt;kdev;</div><div class='ctx'> </div><div class='del'>-	i915_teardown_error_capture(kdev);</div><div class='add'>+	i915_gpu_error_sysfs_teardown(dev_priv);</div><div class='ctx'> </div><div class='ctx'> 	device_remove_bin_file(kdev,  &amp;dpf_attrs_1);</div><div class='ctx'> 	device_remove_bin_file(kdev,  &amp;dpf_attrs);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c<br/>index 3d1fdea9811d..60a03340bbd4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_memory_region.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_memory_region.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_memory_region.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_memory_region.c</a></div><div class='hunk'>@@ -216,6 +216,22 @@ static int intel_memory_region_memtest(struct intel_memory_region *mem,</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const char *region_type_str(u16 type)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case INTEL_MEMORY_SYSTEM:</div><div class='add'>+		return "system";</div><div class='add'>+	case INTEL_MEMORY_LOCAL:</div><div class='add'>+		return "local";</div><div class='add'>+	case INTEL_MEMORY_STOLEN_LOCAL:</div><div class='add'>+		return "stolen-local";</div><div class='add'>+	case INTEL_MEMORY_STOLEN_SYSTEM:</div><div class='add'>+		return "stolen-system";</div><div class='add'>+	default:</div><div class='add'>+		return "unknown";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct intel_memory_region *</div><div class='ctx'> intel_memory_region_create(struct drm_i915_private *i915,</div><div class='ctx'> 			   resource_size_t start,</div><div class='hunk'>@@ -244,6 +260,9 @@ intel_memory_region_create(struct drm_i915_private *i915,</div><div class='ctx'> 	mem-&gt;type = type;</div><div class='ctx'> 	mem-&gt;instance = instance;</div><div class='ctx'> </div><div class='add'>+	snprintf(mem-&gt;uabi_name, sizeof(mem-&gt;uabi_name), "%s%u",</div><div class='add'>+		 region_type_str(type), instance);</div><div class='add'>+</div><div class='ctx'> 	mutex_init(&amp;mem-&gt;objects.lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;mem-&gt;objects.list);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h<br/>index 2953ed5c3248..9ba36454e51b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_memory_region.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_memory_region.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_memory_region.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_memory_region.h</a></div><div class='hunk'>@@ -80,6 +80,7 @@ struct intel_memory_region {</div><div class='ctx'> 	u16 instance;</div><div class='ctx'> 	enum intel_region_id id;</div><div class='ctx'> 	char name[16];</div><div class='add'>+	char uabi_name[16];</div><div class='ctx'> 	bool private; /* not for userspace */</div><div class='ctx'> </div><div class='ctx'> 	struct {</div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c<br/>index 8743153fad87..860b51b56a92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_runtime_pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_runtime_pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_runtime_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_runtime_pm.c</a></div><div class='hunk'>@@ -50,184 +50,44 @@</div><div class='ctx'>  * present for a given platform.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)</div><div class='del'>-</div><div class='del'>-#include &lt;linux/sort.h&gt;</div><div class='del'>-</div><div class='del'>-#define STACKDEPTH 8</div><div class='del'>-</div><div class='del'>-static noinline depot_stack_handle_t __save_depot_stack(void)</div><div class='add'>+static struct drm_i915_private *rpm_to_i915(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	unsigned long entries[STACKDEPTH];</div><div class='del'>-	unsigned int n;</div><div class='del'>-</div><div class='del'>-	n = stack_trace_save(entries, ARRAY_SIZE(entries), 1);</div><div class='del'>-	return stack_depot_save(entries, n, GFP_NOWAIT | __GFP_NOWARN);</div><div class='add'>+	return container_of(rpm, struct drm_i915_private, runtime_pm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)</div><div class='add'>+</div><div class='ctx'> static void init_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	spin_lock_init(&amp;rpm-&gt;debug.lock);</div><div class='del'>-	stack_depot_init();</div><div class='add'>+	ref_tracker_dir_init(&amp;rpm-&gt;debug, INTEL_REFTRACK_DEAD_COUNT, dev_name(rpm-&gt;kdev));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static noinline depot_stack_handle_t</div><div class='add'>+static intel_wakeref_t</div><div class='ctx'> track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	depot_stack_handle_t stack, *stacks;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	if (rpm-&gt;no_wakeref_tracking)</div><div class='add'>+	if (!rpm-&gt;available || rpm-&gt;no_wakeref_tracking)</div><div class='ctx'> 		return -1;</div><div class='ctx'> </div><div class='del'>-	stack = __save_depot_stack();</div><div class='del'>-	if (!stack)</div><div class='del'>-		return -1;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-</div><div class='del'>-	if (!rpm-&gt;debug.count)</div><div class='del'>-		rpm-&gt;debug.last_acquire = stack;</div><div class='del'>-</div><div class='del'>-	stacks = krealloc(rpm-&gt;debug.owners,</div><div class='del'>-			  (rpm-&gt;debug.count + 1) * sizeof(*stacks),</div><div class='del'>-			  GFP_NOWAIT | __GFP_NOWARN);</div><div class='del'>-	if (stacks) {</div><div class='del'>-		stacks[rpm-&gt;debug.count++] = stack;</div><div class='del'>-		rpm-&gt;debug.owners = stacks;</div><div class='del'>-	} else {</div><div class='del'>-		stack = -1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-</div><div class='del'>-	return stack;</div><div class='add'>+	return intel_ref_tracker_alloc(&amp;rpm-&gt;debug);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void untrack_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm,</div><div class='del'>-					     depot_stack_handle_t stack)</div><div class='add'>+					     intel_wakeref_t wakeref)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(rpm,</div><div class='del'>-						     struct drm_i915_private,</div><div class='del'>-						     runtime_pm);</div><div class='del'>-	unsigned long flags, n;</div><div class='del'>-	bool found = false;</div><div class='del'>-</div><div class='del'>-	if (unlikely(stack == -1))</div><div class='add'>+	if (!rpm-&gt;available || rpm-&gt;no_wakeref_tracking)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-	for (n = rpm-&gt;debug.count; n--; ) {</div><div class='del'>-		if (rpm-&gt;debug.owners[n] == stack) {</div><div class='del'>-			memmove(rpm-&gt;debug.owners + n,</div><div class='del'>-				rpm-&gt;debug.owners + n + 1,</div><div class='del'>-				(--rpm-&gt;debug.count - n) * sizeof(stack));</div><div class='del'>-			found = true;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-</div><div class='del'>-	if (drm_WARN(&amp;i915-&gt;drm, !found,</div><div class='del'>-		     "Unmatched wakeref (tracking %lu), count %u\n",</div><div class='del'>-		     rpm-&gt;debug.count, atomic_read(&amp;rpm-&gt;wakeref_count))) {</div><div class='del'>-		char *buf;</div><div class='del'>-</div><div class='del'>-		buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);</div><div class='del'>-		if (!buf)</div><div class='del'>-			return;</div><div class='del'>-</div><div class='del'>-		stack_depot_snprint(stack, buf, PAGE_SIZE, 2);</div><div class='del'>-		DRM_DEBUG_DRIVER("wakeref %x from\n%s", stack, buf);</div><div class='del'>-</div><div class='del'>-		stack = READ_ONCE(rpm-&gt;debug.last_release);</div><div class='del'>-		if (stack) {</div><div class='del'>-			stack_depot_snprint(stack, buf, PAGE_SIZE, 2);</div><div class='del'>-			DRM_DEBUG_DRIVER("wakeref last released at\n%s", buf);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		kfree(buf);</div><div class='del'>-	}</div><div class='add'>+	intel_ref_tracker_free(&amp;rpm-&gt;debug, wakeref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cmphandle(const void *_a, const void *_b)</div><div class='add'>+static void untrack_all_intel_runtime_pm_wakerefs(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	const depot_stack_handle_t * const a = _a, * const b = _b;</div><div class='del'>-</div><div class='del'>-	if (*a &lt; *b)</div><div class='del'>-		return -1;</div><div class='del'>-	else if (*a &gt; *b)</div><div class='del'>-		return 1;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-__print_intel_runtime_pm_wakeref(struct drm_printer *p,</div><div class='del'>-				 const struct intel_runtime_pm_debug *dbg)</div><div class='del'>-{</div><div class='del'>-	unsigned long i;</div><div class='del'>-	char *buf;</div><div class='del'>-</div><div class='del'>-	buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);</div><div class='del'>-	if (!buf)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (dbg-&gt;last_acquire) {</div><div class='del'>-		stack_depot_snprint(dbg-&gt;last_acquire, buf, PAGE_SIZE, 2);</div><div class='del'>-		drm_printf(p, "Wakeref last acquired:\n%s", buf);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (dbg-&gt;last_release) {</div><div class='del'>-		stack_depot_snprint(dbg-&gt;last_release, buf, PAGE_SIZE, 2);</div><div class='del'>-		drm_printf(p, "Wakeref last released:\n%s", buf);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	drm_printf(p, "Wakeref count: %lu\n", dbg-&gt;count);</div><div class='del'>-</div><div class='del'>-	sort(dbg-&gt;owners, dbg-&gt;count, sizeof(*dbg-&gt;owners), cmphandle, NULL);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dbg-&gt;count; i++) {</div><div class='del'>-		depot_stack_handle_t stack = dbg-&gt;owners[i];</div><div class='del'>-		unsigned long rep;</div><div class='del'>-</div><div class='del'>-		rep = 1;</div><div class='del'>-		while (i + 1 &lt; dbg-&gt;count &amp;&amp; dbg-&gt;owners[i + 1] == stack)</div><div class='del'>-			rep++, i++;</div><div class='del'>-		stack_depot_snprint(stack, buf, PAGE_SIZE, 2);</div><div class='del'>-		drm_printf(p, "Wakeref x%lu taken at:\n%s", rep, buf);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kfree(buf);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static noinline void</div><div class='del'>-__untrack_all_wakerefs(struct intel_runtime_pm_debug *debug,</div><div class='del'>-		       struct intel_runtime_pm_debug *saved)</div><div class='del'>-{</div><div class='del'>-	*saved = *debug;</div><div class='del'>-</div><div class='del'>-	debug-&gt;owners = NULL;</div><div class='del'>-	debug-&gt;count = 0;</div><div class='del'>-	debug-&gt;last_release = __save_depot_stack();</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void</div><div class='del'>-dump_and_free_wakeref_tracking(struct intel_runtime_pm_debug *debug)</div><div class='del'>-{</div><div class='del'>-	if (debug-&gt;count) {</div><div class='del'>-		struct drm_printer p = drm_debug_printer("i915");</div><div class='del'>-</div><div class='del'>-		__print_intel_runtime_pm_wakeref(&amp;p, debug);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kfree(debug-&gt;owners);</div><div class='add'>+	ref_tracker_dir_exit(&amp;rpm-&gt;debug);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static noinline void</div><div class='ctx'> __intel_wakeref_dec_and_check_tracking(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	struct intel_runtime_pm_debug dbg = {};</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (!atomic_dec_and_lock_irqsave(&amp;rpm-&gt;wakeref_count,</div><div class='hunk'>@@ -235,60 +95,14 @@ __intel_wakeref_dec_and_check_tracking(struct intel_runtime_pm *rpm)</div><div class='ctx'> 					 flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	__untrack_all_wakerefs(&amp;rpm-&gt;debug, &amp;dbg);</div><div class='add'>+	ref_tracker_dir_print_locked(&amp;rpm-&gt;debug, INTEL_REFTRACK_PRINT_LIMIT);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-</div><div class='del'>-	dump_and_free_wakeref_tracking(&amp;dbg);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static noinline void</div><div class='del'>-untrack_all_intel_runtime_pm_wakerefs(struct intel_runtime_pm *rpm)</div><div class='del'>-{</div><div class='del'>-	struct intel_runtime_pm_debug dbg = {};</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-	__untrack_all_wakerefs(&amp;rpm-&gt;debug, &amp;dbg);</div><div class='del'>-	spin_unlock_irqrestore(&amp;rpm-&gt;debug.lock, flags);</div><div class='del'>-</div><div class='del'>-	dump_and_free_wakeref_tracking(&amp;dbg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void print_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm,</div><div class='ctx'> 				    struct drm_printer *p)</div><div class='ctx'> {</div><div class='del'>-	struct intel_runtime_pm_debug dbg = {};</div><div class='del'>-</div><div class='del'>-	do {</div><div class='del'>-		unsigned long alloc = dbg.count;</div><div class='del'>-		depot_stack_handle_t *s;</div><div class='del'>-</div><div class='del'>-		spin_lock_irq(&amp;rpm-&gt;debug.lock);</div><div class='del'>-		dbg.count = rpm-&gt;debug.count;</div><div class='del'>-		if (dbg.count &lt;= alloc) {</div><div class='del'>-			memcpy(dbg.owners,</div><div class='del'>-			       rpm-&gt;debug.owners,</div><div class='del'>-			       dbg.count * sizeof(*s));</div><div class='del'>-		}</div><div class='del'>-		dbg.last_acquire = rpm-&gt;debug.last_acquire;</div><div class='del'>-		dbg.last_release = rpm-&gt;debug.last_release;</div><div class='del'>-		spin_unlock_irq(&amp;rpm-&gt;debug.lock);</div><div class='del'>-		if (dbg.count &lt;= alloc)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		s = krealloc(dbg.owners,</div><div class='del'>-			     dbg.count * sizeof(*s),</div><div class='del'>-			     GFP_NOWAIT | __GFP_NOWARN);</div><div class='del'>-		if (!s)</div><div class='del'>-			goto out;</div><div class='del'>-</div><div class='del'>-		dbg.owners = s;</div><div class='del'>-	} while (1);</div><div class='del'>-</div><div class='del'>-	__print_intel_runtime_pm_wakeref(p, &amp;dbg);</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	kfree(dbg.owners);</div><div class='add'>+	intel_ref_tracker_show(&amp;rpm-&gt;debug, p);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #else</div><div class='hunk'>@@ -297,14 +111,14 @@ static void init_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static depot_stack_handle_t</div><div class='add'>+static intel_wakeref_t</div><div class='ctx'> track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='ctx'> 	return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void untrack_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm,</div><div class='del'>-					     intel_wakeref_t wref)</div><div class='add'>+					     intel_wakeref_t wakeref)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -349,9 +163,7 @@ intel_runtime_pm_release(struct intel_runtime_pm *rpm, int wakelock)</div><div class='ctx'> static intel_wakeref_t __intel_runtime_pm_get(struct intel_runtime_pm *rpm,</div><div class='ctx'> 					      bool wakelock)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(rpm,</div><div class='del'>-						     struct drm_i915_private,</div><div class='del'>-						     runtime_pm);</div><div class='add'>+	struct drm_i915_private *i915 = rpm_to_i915(rpm);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = pm_runtime_get_sync(rpm-&gt;kdev);</div><div class='hunk'>@@ -556,9 +368,7 @@ void intel_runtime_pm_put(struct intel_runtime_pm *rpm, intel_wakeref_t wref)</div><div class='ctx'>  */</div><div class='ctx'> void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(rpm,</div><div class='del'>-						     struct drm_i915_private,</div><div class='del'>-						     runtime_pm);</div><div class='add'>+	struct drm_i915_private *i915 = rpm_to_i915(rpm);</div><div class='ctx'> 	struct device *kdev = rpm-&gt;kdev;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -611,9 +421,7 @@ void intel_runtime_pm_enable(struct intel_runtime_pm *rpm)</div><div class='ctx'> </div><div class='ctx'> void intel_runtime_pm_disable(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(rpm,</div><div class='del'>-						     struct drm_i915_private,</div><div class='del'>-						     runtime_pm);</div><div class='add'>+	struct drm_i915_private *i915 = rpm_to_i915(rpm);</div><div class='ctx'> 	struct device *kdev = rpm-&gt;kdev;</div><div class='ctx'> </div><div class='ctx'> 	/* Transfer rpm ownership back to core */</div><div class='hunk'>@@ -628,9 +436,7 @@ void intel_runtime_pm_disable(struct intel_runtime_pm *rpm)</div><div class='ctx'> </div><div class='ctx'> void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 = container_of(rpm,</div><div class='del'>-						     struct drm_i915_private,</div><div class='del'>-						     runtime_pm);</div><div class='add'>+	struct drm_i915_private *i915 = rpm_to_i915(rpm);</div><div class='ctx'> 	int count = atomic_read(&amp;rpm-&gt;wakeref_count);</div><div class='ctx'> </div><div class='ctx'> 	intel_wakeref_auto_fini(&amp;rpm-&gt;userfault_wakeref);</div><div class='hunk'>@@ -639,14 +445,17 @@ void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm)</div><div class='ctx'> 		 "i915 raw-wakerefs=%d wakelocks=%d on cleanup\n",</div><div class='ctx'> 		 intel_rpm_raw_wakeref_count(count),</div><div class='ctx'> 		 intel_rpm_wakelock_count(count));</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+void intel_runtime_pm_driver_last_release(struct intel_runtime_pm *rpm)</div><div class='add'>+{</div><div class='add'>+	intel_runtime_pm_driver_release(rpm);</div><div class='ctx'> 	untrack_all_intel_runtime_pm_wakerefs(rpm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm)</div><div class='ctx'> {</div><div class='del'>-	struct drm_i915_private *i915 =</div><div class='del'>-			container_of(rpm, struct drm_i915_private, runtime_pm);</div><div class='add'>+	struct drm_i915_private *i915 = rpm_to_i915(rpm);</div><div class='ctx'> 	struct pci_dev *pdev = to_pci_dev(i915-&gt;drm.dev);</div><div class='ctx'> 	struct device *kdev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h<br/>index be43614c73fd..de3579d399e1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_runtime_pm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_runtime_pm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_runtime_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_runtime_pm.h</a></div><div class='hunk'>@@ -75,15 +75,7 @@ struct intel_runtime_pm {</div><div class='ctx'> 	 * paired rpm_put) we can remove corresponding pairs of and keep</div><div class='ctx'> 	 * the array trimmed to active wakerefs.</div><div class='ctx'> 	 */</div><div class='del'>-	struct intel_runtime_pm_debug {</div><div class='del'>-		spinlock_t lock;</div><div class='del'>-</div><div class='del'>-		depot_stack_handle_t last_acquire;</div><div class='del'>-		depot_stack_handle_t last_release;</div><div class='del'>-</div><div class='del'>-		depot_stack_handle_t *owners;</div><div class='del'>-		unsigned long count;</div><div class='del'>-	} debug;</div><div class='add'>+	struct ref_tracker_dir debug;</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -187,6 +179,7 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm);</div><div class='ctx'> void intel_runtime_pm_enable(struct intel_runtime_pm *rpm);</div><div class='ctx'> void intel_runtime_pm_disable(struct intel_runtime_pm *rpm);</div><div class='ctx'> void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm);</div><div class='add'>+void intel_runtime_pm_driver_last_release(struct intel_runtime_pm *rpm);</div><div class='ctx'> </div><div class='ctx'> intel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm);</div><div class='ctx'> intel_wakeref_t intel_runtime_pm_get_if_in_use(struct intel_runtime_pm *rpm);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_wakeref.c b/drivers/gpu/drm/i915/intel_wakeref.c<br/>index 623a69089386..dea2f63184f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_wakeref.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_wakeref.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_wakeref.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_wakeref.c</a></div><div class='hunk'>@@ -99,7 +99,8 @@ static void __intel_wakeref_put_work(struct work_struct *wrk)</div><div class='ctx'> void __intel_wakeref_init(struct intel_wakeref *wf,</div><div class='ctx'> 			  struct drm_i915_private *i915,</div><div class='ctx'> 			  const struct intel_wakeref_ops *ops,</div><div class='del'>-			  struct intel_wakeref_lockclass *key)</div><div class='add'>+			  struct intel_wakeref_lockclass *key,</div><div class='add'>+			  const char *name)</div><div class='ctx'> {</div><div class='ctx'> 	wf-&gt;i915 = i915;</div><div class='ctx'> 	wf-&gt;ops = ops;</div><div class='hunk'>@@ -111,6 +112,10 @@ void __intel_wakeref_init(struct intel_wakeref *wf,</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;wf-&gt;work, __intel_wakeref_put_work);</div><div class='ctx'> 	lockdep_init_map(&amp;wf-&gt;work.work.lockdep_map,</div><div class='ctx'> 			 "wakeref.work", &amp;key-&gt;work, 0);</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_WAKEREF)</div><div class='add'>+	ref_tracker_dir_init(&amp;wf-&gt;debug, INTEL_REFTRACK_DEAD_COUNT, name);</div><div class='add'>+#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int intel_wakeref_wait_for_idle(struct intel_wakeref *wf)</div><div class='hunk'>@@ -191,3 +196,31 @@ void intel_wakeref_auto_fini(struct intel_wakeref_auto *wf)</div><div class='ctx'> 	intel_wakeref_auto(wf, 0);</div><div class='ctx'> 	INTEL_WAKEREF_BUG_ON(wf-&gt;wakeref);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void intel_ref_tracker_show(struct ref_tracker_dir *dir,</div><div class='add'>+			    struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	const size_t buf_size = PAGE_SIZE;</div><div class='add'>+	char *buf, *sb, *se;</div><div class='add'>+	size_t count;</div><div class='add'>+</div><div class='add'>+	buf = kmalloc(buf_size, GFP_NOWAIT);</div><div class='add'>+	if (!buf)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	count = ref_tracker_dir_snprint(dir, buf, buf_size);</div><div class='add'>+	if (!count)</div><div class='add'>+		goto free;</div><div class='add'>+	/* printk does not like big buffers, so we split it */</div><div class='add'>+	for (sb = buf; *sb; sb = se + 1) {</div><div class='add'>+		se = strchrnul(sb, '\n');</div><div class='add'>+		drm_printf(p, "%.*s", (int)(se - sb + 1), sb);</div><div class='add'>+		if (!*se)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	if (count &gt;= buf_size)</div><div class='add'>+		drm_printf(p, "\n...dropped %zd extra bytes of leak report.\n",</div><div class='add'>+			   count + 1 - buf_size);</div><div class='add'>+free:</div><div class='add'>+	kfree(buf);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/intel_wakeref.h b/drivers/gpu/drm/i915/intel_wakeref.h<br/>index ec881b097368..68aa3be48251 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_wakeref.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/intel_wakeref.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/intel_wakeref.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/intel_wakeref.h</a></div><div class='hunk'>@@ -7,16 +7,25 @@</div><div class='ctx'> #ifndef INTEL_WAKEREF_H</div><div class='ctx'> #define INTEL_WAKEREF_H</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/atomic.h&gt;</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/bits.h&gt;</div><div class='ctx'> #include &lt;linux/lockdep.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/refcount.h&gt;</div><div class='add'>+#include &lt;linux/ref_tracker.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/stackdepot.h&gt;</div><div class='ctx'> #include &lt;linux/timer.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='ctx'> </div><div class='add'>+typedef unsigned long intel_wakeref_t;</div><div class='add'>+</div><div class='add'>+#define INTEL_REFTRACK_DEAD_COUNT 16</div><div class='add'>+#define INTEL_REFTRACK_PRINT_LIMIT 16</div><div class='add'>+</div><div class='ctx'> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)</div><div class='ctx'> #define INTEL_WAKEREF_BUG_ON(expr) BUG_ON(expr)</div><div class='ctx'> #else</div><div class='hunk'>@@ -26,8 +35,6 @@</div><div class='ctx'> struct intel_runtime_pm;</div><div class='ctx'> struct intel_wakeref;</div><div class='ctx'> </div><div class='del'>-typedef depot_stack_handle_t intel_wakeref_t;</div><div class='del'>-</div><div class='ctx'> struct intel_wakeref_ops {</div><div class='ctx'> 	int (*get)(struct intel_wakeref *wf);</div><div class='ctx'> 	int (*put)(struct intel_wakeref *wf);</div><div class='hunk'>@@ -43,6 +50,10 @@ struct intel_wakeref {</div><div class='ctx'> 	const struct intel_wakeref_ops *ops;</div><div class='ctx'> </div><div class='ctx'> 	struct delayed_work work;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_WAKEREF)</div><div class='add'>+	struct ref_tracker_dir debug;</div><div class='add'>+#endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct intel_wakeref_lockclass {</div><div class='hunk'>@@ -53,11 +64,12 @@ struct intel_wakeref_lockclass {</div><div class='ctx'> void __intel_wakeref_init(struct intel_wakeref *wf,</div><div class='ctx'> 			  struct drm_i915_private *i915,</div><div class='ctx'> 			  const struct intel_wakeref_ops *ops,</div><div class='del'>-			  struct intel_wakeref_lockclass *key);</div><div class='del'>-#define intel_wakeref_init(wf, i915, ops) do {				\</div><div class='add'>+			  struct intel_wakeref_lockclass *key,</div><div class='add'>+			  const char *name);</div><div class='add'>+#define intel_wakeref_init(wf, i915, ops, name) do {			\</div><div class='ctx'> 	static struct intel_wakeref_lockclass __key;			\</div><div class='ctx'> 									\</div><div class='del'>-	__intel_wakeref_init((wf), (i915), (ops), &amp;__key);		\</div><div class='add'>+	__intel_wakeref_init((wf), (i915), (ops), &amp;__key, name);	\</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='ctx'> int __intel_wakeref_get_first(struct intel_wakeref *wf);</div><div class='hunk'>@@ -261,6 +273,57 @@ __intel_wakeref_defer_park(struct intel_wakeref *wf)</div><div class='ctx'>  */</div><div class='ctx'> int intel_wakeref_wait_for_idle(struct intel_wakeref *wf);</div><div class='ctx'> </div><div class='add'>+#define INTEL_WAKEREF_DEF ((intel_wakeref_t)(-1))</div><div class='add'>+</div><div class='add'>+static inline intel_wakeref_t intel_ref_tracker_alloc(struct ref_tracker_dir *dir)</div><div class='add'>+{</div><div class='add'>+	struct ref_tracker *user = NULL;</div><div class='add'>+</div><div class='add'>+	ref_tracker_alloc(dir, &amp;user, GFP_NOWAIT);</div><div class='add'>+</div><div class='add'>+	return (intel_wakeref_t)user ?: INTEL_WAKEREF_DEF;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_ref_tracker_free(struct ref_tracker_dir *dir,</div><div class='add'>+					  intel_wakeref_t handle)</div><div class='add'>+{</div><div class='add'>+	struct ref_tracker *user;</div><div class='add'>+</div><div class='add'>+	user = (handle == INTEL_WAKEREF_DEF) ? NULL : (void *)handle;</div><div class='add'>+</div><div class='add'>+	ref_tracker_free(dir, &amp;user);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_ref_tracker_show(struct ref_tracker_dir *dir,</div><div class='add'>+			    struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_WAKEREF)</div><div class='add'>+</div><div class='add'>+static inline intel_wakeref_t intel_wakeref_track(struct intel_wakeref *wf)</div><div class='add'>+{</div><div class='add'>+	return intel_ref_tracker_alloc(&amp;wf-&gt;debug);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_wakeref_untrack(struct intel_wakeref *wf,</div><div class='add'>+					 intel_wakeref_t handle)</div><div class='add'>+{</div><div class='add'>+	intel_ref_tracker_free(&amp;wf-&gt;debug, handle);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+static inline intel_wakeref_t intel_wakeref_track(struct intel_wakeref *wf)</div><div class='add'>+{</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_wakeref_untrack(struct intel_wakeref *wf,</div><div class='add'>+					 intel_wakeref_t handle)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> struct intel_wakeref_auto {</div><div class='ctx'> 	struct drm_i915_private *i915;</div><div class='ctx'> 	struct timer_list timer;</div><div class='head'>diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c<br/>index dc327cf40b5a..75278e78ca90 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/pxp/intel_pxp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp.c</a></div><div class='hunk'>@@ -199,6 +199,9 @@ int intel_pxp_init(struct drm_i915_private *i915)</div><div class='ctx'> 	struct intel_gt *gt;</div><div class='ctx'> 	bool is_full_feature = false;</div><div class='ctx'> </div><div class='add'>+	if (intel_gt_is_wedged(to_gt(i915)))</div><div class='add'>+		return -ENOTCONN;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * NOTE: Get the ctrl_gt before checking intel_pxp_is_supported since</div><div class='ctx'> 	 * we still need it if PXP's backend tee transport is needed.</div><div class='hunk'>@@ -303,6 +306,8 @@ static int __pxp_global_teardown_final(struct intel_pxp *pxp)</div><div class='ctx'> </div><div class='ctx'> 	if (!pxp-&gt;arb_is_valid)</div><div class='ctx'> 		return 0;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;pxp-&gt;ctrl_gt-&gt;i915-&gt;drm, "PXP: teardown for suspend/fini");</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * To ensure synchronous and coherent session teardown completion</div><div class='ctx'> 	 * in response to suspend or shutdown triggers, don't use a worker.</div><div class='hunk'>@@ -324,6 +329,8 @@ static int __pxp_global_teardown_restart(struct intel_pxp *pxp)</div><div class='ctx'> </div><div class='ctx'> 	if (pxp-&gt;arb_is_valid)</div><div class='ctx'> 		return 0;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;pxp-&gt;ctrl_gt-&gt;i915-&gt;drm, "PXP: teardown for restart");</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The arb-session is currently inactive and we are doing a reset and restart</div><div class='ctx'> 	 * due to a runtime event. Use the worker that was designed for this.</div><div class='hunk'>@@ -332,8 +339,11 @@ static int __pxp_global_teardown_restart(struct intel_pxp *pxp)</div><div class='ctx'> </div><div class='ctx'> 	timeout = intel_pxp_get_backend_timeout_ms(pxp);</div><div class='ctx'> </div><div class='del'>-	if (!wait_for_completion_timeout(&amp;pxp-&gt;termination, msecs_to_jiffies(timeout)))</div><div class='add'>+	if (!wait_for_completion_timeout(&amp;pxp-&gt;termination, msecs_to_jiffies(timeout))) {</div><div class='add'>+		drm_dbg(&amp;pxp-&gt;ctrl_gt-&gt;i915-&gt;drm, "PXP: restart backend timed out (%d ms)",</div><div class='add'>+			timeout);</div><div class='ctx'> 		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -414,10 +424,12 @@ int intel_pxp_start(struct intel_pxp *pxp)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	ret = intel_pxp_get_readiness_status(pxp, PXP_READINESS_TIMEOUT);</div><div class='del'>-	if (ret &lt; 0)</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		drm_dbg(&amp;pxp-&gt;ctrl_gt-&gt;i915-&gt;drm, "PXP: tried but not-avail (%d)", ret);</div><div class='ctx'> 		return ret;</div><div class='del'>-	else if (ret &gt; 1)</div><div class='add'>+	} else if (ret &gt; 1) {</div><div class='ctx'> 		return -EIO; /* per UAPI spec, user may retry later */</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;pxp-&gt;arb_mutex);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c<br/>index 91e9622c07d0..d81750b9bdda 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/pxp/intel_pxp_irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_irq.c</a></div><div class='hunk'>@@ -40,11 +40,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)</div><div class='ctx'> 		   GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) {</div><div class='ctx'> 		/* immediately mark PXP as inactive on termination */</div><div class='ctx'> 		intel_pxp_mark_termination_in_progress(pxp);</div><div class='del'>-		pxp-&gt;session_events |= PXP_TERMINATION_REQUEST | PXP_INVAL_REQUIRED;</div><div class='add'>+		pxp-&gt;session_events |= PXP_TERMINATION_REQUEST | PXP_INVAL_REQUIRED |</div><div class='add'>+				       PXP_EVENT_TYPE_IRQ;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (iir &amp; GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)</div><div class='del'>-		pxp-&gt;session_events |= PXP_TERMINATION_COMPLETE;</div><div class='add'>+		pxp-&gt;session_events |= PXP_TERMINATION_COMPLETE | PXP_EVENT_TYPE_IRQ;</div><div class='ctx'> </div><div class='ctx'> 	if (pxp-&gt;session_events)</div><div class='ctx'> 		queue_work(system_unbound_wq, &amp;pxp-&gt;session_work);</div><div class='head'>diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c<br/>index 0a3e66b0265e..091c86e03d1a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_session.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/pxp/intel_pxp_session.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_session.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_session.c</a></div><div class='hunk'>@@ -137,8 +137,10 @@ void intel_pxp_terminate(struct intel_pxp *pxp, bool post_invalidation_needs_res</div><div class='ctx'> static void pxp_terminate_complete(struct intel_pxp *pxp)</div><div class='ctx'> {</div><div class='ctx'> 	/* Re-create the arb session after teardown handle complete */</div><div class='del'>-	if (fetch_and_zero(&amp;pxp-&gt;hw_state_invalidated))</div><div class='add'>+	if (fetch_and_zero(&amp;pxp-&gt;hw_state_invalidated)) {</div><div class='add'>+		drm_dbg(&amp;pxp-&gt;ctrl_gt-&gt;i915-&gt;drm, "PXP: creating arb_session after invalidation");</div><div class='ctx'> 		pxp_create_arb_session(pxp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	complete_all(&amp;pxp-&gt;termination);</div><div class='ctx'> }</div><div class='hunk'>@@ -157,6 +159,8 @@ static void pxp_session_work(struct work_struct *work)</div><div class='ctx'> 	if (!events)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	drm_dbg(&amp;gt-&gt;i915-&gt;drm, "PXP: processing event-flags 0x%08x", events);</div><div class='add'>+</div><div class='ctx'> 	if (events &amp; PXP_INVAL_REQUIRED)</div><div class='ctx'> 		intel_pxp_invalidate(pxp);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h<br/>index 7e11fa8034b2..07864b584cf4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/pxp/intel_pxp_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/pxp/intel_pxp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/pxp/intel_pxp_types.h</a></div><div class='hunk'>@@ -124,6 +124,7 @@ struct intel_pxp {</div><div class='ctx'> #define PXP_TERMINATION_REQUEST  BIT(0)</div><div class='ctx'> #define PXP_TERMINATION_COMPLETE BIT(1)</div><div class='ctx'> #define PXP_INVAL_REQUIRED       BIT(2)</div><div class='add'>+#define PXP_EVENT_TYPE_IRQ       BIT(3)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif /* __INTEL_PXP_TYPES_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/i915/selftests/i915_syncmap.c b/drivers/gpu/drm/i915/selftests/i915_syncmap.c<br/>index 47f4ae18a1ef..88fa845e9f4a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/i915_syncmap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/selftests/i915_syncmap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/i915_syncmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/i915_syncmap.c</a></div><div class='hunk'>@@ -77,7 +77,7 @@ __sync_print(struct i915_syncmap *p,</div><div class='ctx'> 		for_each_set_bit(i, (unsigned long *)&amp;p-&gt;bitmap, KSYNCMAP) {</div><div class='ctx'> 			buf = __sync_print(__sync_child(p)[i], buf, sz,</div><div class='ctx'> 					   depth + 1,</div><div class='del'>-					   last &lt;&lt; 1 | !!(p-&gt;bitmap &gt;&gt; (i + 1)),</div><div class='add'>+					   last &lt;&lt; 1 | ((p-&gt;bitmap &gt;&gt; (i + 1)) ? 1 : 0),</div><div class='ctx'> 					   i);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/selftests/igt_live_test.c b/drivers/gpu/drm/i915/selftests/igt_live_test.c<br/>index 4ddc6d902752..7d41874a49c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/igt_live_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/selftests/igt_live_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/igt_live_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/igt_live_test.c</a></div><div class='hunk'>@@ -37,8 +37,9 @@ int igt_live_test_begin(struct igt_live_test *t,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		for_each_engine(engine, gt, id)</div><div class='del'>-			t-&gt;reset_engine[id] =</div><div class='del'>-			i915_reset_engine_count(&amp;i915-&gt;gpu_error, engine);</div><div class='add'>+			t-&gt;reset_engine[i][id] =</div><div class='add'>+				i915_reset_engine_count(&amp;i915-&gt;gpu_error,</div><div class='add'>+							engine);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	t-&gt;reset_global = i915_reset_count(&amp;i915-&gt;gpu_error);</div><div class='hunk'>@@ -66,14 +67,14 @@ int igt_live_test_end(struct igt_live_test *t)</div><div class='ctx'> </div><div class='ctx'> 	for_each_gt(gt, i915, i) {</div><div class='ctx'> 		for_each_engine(engine, gt, id) {</div><div class='del'>-			if (t-&gt;reset_engine[id] ==</div><div class='add'>+			if (t-&gt;reset_engine[i][id] ==</div><div class='ctx'> 			    i915_reset_engine_count(&amp;i915-&gt;gpu_error, engine))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			gt_err(gt, "%s(%s): engine '%s' was reset %d times!\n",</div><div class='ctx'> 			       t-&gt;func, t-&gt;name, engine-&gt;name,</div><div class='ctx'> 			       i915_reset_engine_count(&amp;i915-&gt;gpu_error, engine) -</div><div class='del'>-			       t-&gt;reset_engine[id]);</div><div class='add'>+			       t-&gt;reset_engine[i][id]);</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/gpu/drm/i915/selftests/igt_live_test.h b/drivers/gpu/drm/i915/selftests/igt_live_test.h<br/>index 36ed42736c52..83e3ad430922 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/igt_live_test.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/i915/selftests/igt_live_test.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/i915/selftests/igt_live_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/i915/selftests/igt_live_test.h</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> #ifndef IGT_LIVE_TEST_H</div><div class='ctx'> #define IGT_LIVE_TEST_H</div><div class='ctx'> </div><div class='add'>+#include "gt/intel_gt_defines.h" /* for I915_MAX_GT */</div><div class='ctx'> #include "gt/intel_engine.h" /* for I915_NUM_ENGINES */</div><div class='ctx'> </div><div class='ctx'> struct drm_i915_private;</div><div class='hunk'>@@ -17,7 +18,7 @@ struct igt_live_test {</div><div class='ctx'> 	const char *name;</div><div class='ctx'> </div><div class='ctx'> 	unsigned int reset_global;</div><div class='del'>-	unsigned int reset_engine[I915_NUM_ENGINES];</div><div class='add'>+	unsigned int reset_engine[I915_MAX_GT][I915_NUM_ENGINES];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h<br/>index 2ca7e535799f..ecdd5767d8ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_device.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/imagination/pvr_device.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_device.h</a></div><div class='hunk'>@@ -193,13 +193,14 @@ struct pvr_device {</div><div class='ctx'> 	 * @queues: Queue-related fields.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct {</div><div class='del'>-		/** @active: Active queue list. */</div><div class='add'>+		/** @queues.active: Active queue list. */</div><div class='ctx'> 		struct list_head active;</div><div class='ctx'> </div><div class='del'>-		/** @idle: Idle queue list. */</div><div class='add'>+		/** @queues.idle: Idle queue list. */</div><div class='ctx'> 		struct list_head idle;</div><div class='ctx'> </div><div class='del'>-		/** @lock: Lock protecting access to the active/idle lists. */</div><div class='add'>+		/** @queues.lock: Lock protecting access to the active/idle</div><div class='add'>+		 *  lists. */</div><div class='ctx'> 		struct mutex lock;</div><div class='ctx'> 	} queues;</div><div class='ctx'> </div><div class='hunk'>@@ -207,18 +208,18 @@ struct pvr_device {</div><div class='ctx'> 	 * @watchdog: Watchdog for communications with firmware.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct {</div><div class='del'>-		/** @work: Work item for watchdog callback. */</div><div class='add'>+		/** @watchdog.work: Work item for watchdog callback. */</div><div class='ctx'> 		struct delayed_work work;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @old_kccb_cmds_executed: KCCB command execution count at last</div><div class='del'>-		 * watchdog poll.</div><div class='add'>+		 * @watchdog.old_kccb_cmds_executed: KCCB command execution</div><div class='add'>+		 * count at last watchdog poll.</div><div class='ctx'> 		 */</div><div class='ctx'> 		u32 old_kccb_cmds_executed;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @kccb_stall_count: Number of watchdog polls KCCB has been</div><div class='del'>-		 * stalled for.</div><div class='add'>+		 * @watchdog.kccb_stall_count: Number of watchdog polls</div><div class='add'>+		 * KCCB has been stalled for.</div><div class='ctx'> 		 */</div><div class='ctx'> 		u32 kccb_stall_count;</div><div class='ctx'> 	} watchdog;</div><div class='hunk'>@@ -227,43 +228,46 @@ struct pvr_device {</div><div class='ctx'> 	 * @kccb: Circular buffer for communications with firmware.</div><div class='ctx'> 	 */</div><div class='ctx'> 	struct {</div><div class='del'>-		/** @ccb: Kernel CCB. */</div><div class='add'>+		/** @kccb.ccb: Kernel CCB. */</div><div class='ctx'> 		struct pvr_ccb ccb;</div><div class='ctx'> </div><div class='del'>-		/** @rtn_q: Waitqueue for KCCB command return waiters. */</div><div class='add'>+		/** @kccb.rtn_q: Waitqueue for KCCB command return waiters. */</div><div class='ctx'> 		wait_queue_head_t rtn_q;</div><div class='ctx'> </div><div class='del'>-		/** @rtn_obj: Object representing KCCB return slots. */</div><div class='add'>+		/** @kccb.rtn_obj: Object representing KCCB return slots. */</div><div class='ctx'> 		struct pvr_fw_object *rtn_obj;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @rtn: Pointer to CPU mapping of KCCB return slots. Must be</div><div class='del'>-		 * accessed by READ_ONCE()/WRITE_ONCE().</div><div class='add'>+		 * @kccb.rtn: Pointer to CPU mapping of KCCB return slots.</div><div class='add'>+		 * Must be accessed by READ_ONCE()/WRITE_ONCE().</div><div class='ctx'> 		 */</div><div class='ctx'> 		u32 *rtn;</div><div class='ctx'> </div><div class='del'>-		/** @slot_count: Total number of KCCB slots available. */</div><div class='add'>+		/** @kccb.slot_count: Total number of KCCB slots available. */</div><div class='ctx'> 		u32 slot_count;</div><div class='ctx'> </div><div class='del'>-		/** @reserved_count: Number of KCCB slots reserved for future use. */</div><div class='add'>+		/** @kccb.reserved_count: Number of KCCB slots reserved for</div><div class='add'>+		 *  future use. */</div><div class='ctx'> 		u32 reserved_count;</div><div class='ctx'> </div><div class='ctx'> 		/**</div><div class='del'>-		 * @waiters: List of KCCB slot waiters.</div><div class='add'>+		 * @kccb.waiters: List of KCCB slot waiters.</div><div class='ctx'> 		 */</div><div class='ctx'> 		struct list_head waiters;</div><div class='ctx'> </div><div class='del'>-		/** @fence_ctx: KCCB fence context. */</div><div class='add'>+		/** @kccb.fence_ctx: KCCB fence context. */</div><div class='ctx'> 		struct {</div><div class='del'>-			/** @id: KCCB fence context ID allocated with dma_fence_context_alloc(). */</div><div class='add'>+			/** @kccb.fence_ctx.id: KCCB fence context ID</div><div class='add'>+			 *  allocated with dma_fence_context_alloc(). */</div><div class='ctx'> 			u64 id;</div><div class='ctx'> </div><div class='del'>-			/** @seqno: Sequence number incremented each time a fence is created. */</div><div class='add'>+			/** @kccb.fence_ctx.seqno: Sequence number incremented</div><div class='add'>+			 *  each time a fence is created. */</div><div class='ctx'> 			atomic_t seqno;</div><div class='ctx'> </div><div class='ctx'> 			/**</div><div class='del'>-			 * @lock: Lock used to synchronize access to fences allocated by this</div><div class='del'>-			 * context.</div><div class='add'>+			 * @kccb.fence_ctx.lock: Lock used to synchronize</div><div class='add'>+			 * access to fences allocated by this context.</div><div class='ctx'> 			 */</div><div class='ctx'> 			spinlock_t lock;</div><div class='ctx'> 		} fence_ctx;</div><div class='head'>diff --git a/drivers/gpu/drm/imagination/pvr_hwrt.c b/drivers/gpu/drm/imagination/pvr_hwrt.c<br/>index c4213c18489e..54f88d6c01e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_hwrt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/imagination/pvr_hwrt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_hwrt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_hwrt.c</a></div><div class='hunk'>@@ -458,7 +458,7 @@ pvr_hwrt_dataset_create(struct pvr_file *pvr_file,</div><div class='ctx'> 			struct drm_pvr_ioctl_create_hwrt_dataset_args *args)</div><div class='ctx'> {</div><div class='ctx'> 	struct pvr_hwrt_dataset *hwrt;</div><div class='del'>-	int err;</div><div class='add'>+	int err, i = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Create and fill out the kernel structure */</div><div class='ctx'> 	hwrt = kzalloc(sizeof(*hwrt), GFP_KERNEL);</div><div class='hunk'>@@ -466,35 +466,36 @@ pvr_hwrt_dataset_create(struct pvr_file *pvr_file,</div><div class='ctx'> 	if (!hwrt)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	kref_init(&amp;hwrt-&gt;ref_count);</div><div class='del'>-</div><div class='ctx'> 	err = hwrt_init_kernel_structure(pvr_file, args, hwrt);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> </div><div class='ctx'> 	err = hwrt_init_common_fw_structure(pvr_file, args, hwrt);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='del'>-		goto err_free;</div><div class='add'>+		goto err_fini_kernel_structure;</div><div class='ctx'> </div><div class='del'>-	for (int i = 0; i &lt; ARRAY_SIZE(hwrt-&gt;data); i++) {</div><div class='add'>+	for (; i &lt; ARRAY_SIZE(hwrt-&gt;data); i++) {</div><div class='ctx'> 		err = hwrt_data_init_fw_structure(pvr_file, hwrt, args,</div><div class='ctx'> 						  &amp;args-&gt;rt_data_args[i],</div><div class='ctx'> 						  &amp;hwrt-&gt;data[i]);</div><div class='del'>-		if (err &lt; 0) {</div><div class='del'>-			i--;</div><div class='del'>-			/* Destroy already created structures. */</div><div class='del'>-			for (; i &gt;= 0; i--)</div><div class='del'>-				hwrt_data_fini_fw_structure(hwrt, i);</div><div class='del'>-			goto err_free;</div><div class='del'>-		}</div><div class='add'>+		if (err &lt; 0)</div><div class='add'>+			goto err_fini_data_structures;</div><div class='ctx'> </div><div class='ctx'> 		hwrt-&gt;data[i].hwrt_dataset = hwrt;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kref_init(&amp;hwrt-&gt;ref_count);</div><div class='ctx'> 	return hwrt;</div><div class='ctx'> </div><div class='add'>+err_fini_data_structures:</div><div class='add'>+	while (--i &gt;= 0)</div><div class='add'>+		hwrt_data_fini_fw_structure(hwrt, i);</div><div class='add'>+</div><div class='add'>+err_fini_kernel_structure:</div><div class='add'>+	hwrt_fini_kernel_structure(hwrt);</div><div class='add'>+</div><div class='ctx'> err_free:</div><div class='del'>-	pvr_hwrt_dataset_put(hwrt);</div><div class='add'>+	kfree(hwrt);</div><div class='ctx'> </div><div class='ctx'> 	return ERR_PTR(err);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c<br/>index 04139da6c04d..78c2f3c6dce0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_job.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/imagination/pvr_job.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_job.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_job.c</a></div><div class='hunk'>@@ -746,7 +746,7 @@ pvr_submit_jobs(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out_job_data_cleanup;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT | DRM_EXEC_IGNORE_DUPLICATES);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT | DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> </div><div class='ctx'> 	xa_init_flags(&amp;signal_array, XA_FLAGS_ALLOC);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagination/pvr_vm.c<br/>index 82690cee978c..e59517ba039e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_vm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/imagination/pvr_vm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_vm.c</a></div><div class='hunk'>@@ -556,23 +556,12 @@ pvr_vm_create_context(struct pvr_device *pvr_dev, bool is_userspace_context)</div><div class='ctx'> 	if (!vm_ctx)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	drm_gem_private_object_init(&amp;pvr_dev-&gt;base, &amp;vm_ctx-&gt;dummy_gem, 0);</div><div class='del'>-</div><div class='ctx'> 	vm_ctx-&gt;pvr_dev = pvr_dev;</div><div class='del'>-	kref_init(&amp;vm_ctx-&gt;ref_count);</div><div class='del'>-	mutex_init(&amp;vm_ctx-&gt;lock);</div><div class='del'>-</div><div class='del'>-	drm_gpuvm_init(&amp;vm_ctx-&gt;gpuvm_mgr,</div><div class='del'>-		       is_userspace_context ? "PowerVR-user-VM" : "PowerVR-FW-VM",</div><div class='del'>-		       0, &amp;pvr_dev-&gt;base, &amp;vm_ctx-&gt;dummy_gem,</div><div class='del'>-		       0, 1ULL &lt;&lt; device_addr_bits, 0, 0, &amp;pvr_vm_gpuva_ops);</div><div class='ctx'> </div><div class='ctx'> 	vm_ctx-&gt;mmu_ctx = pvr_mmu_context_create(pvr_dev);</div><div class='del'>-	err = PTR_ERR_OR_ZERO(&amp;vm_ctx-&gt;mmu_ctx);</div><div class='del'>-	if (err) {</div><div class='del'>-		vm_ctx-&gt;mmu_ctx = NULL;</div><div class='del'>-		goto err_put_ctx;</div><div class='del'>-	}</div><div class='add'>+	err = PTR_ERR_OR_ZERO(vm_ctx-&gt;mmu_ctx);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_free;</div><div class='ctx'> </div><div class='ctx'> 	if (is_userspace_context) {</div><div class='ctx'> 		err = pvr_fw_object_create(pvr_dev, sizeof(struct rogue_fwif_fwmemcontext),</div><div class='hunk'>@@ -583,13 +572,22 @@ pvr_vm_create_context(struct pvr_device *pvr_dev, bool is_userspace_context)</div><div class='ctx'> 			goto err_page_table_destroy;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	drm_gem_private_object_init(&amp;pvr_dev-&gt;base, &amp;vm_ctx-&gt;dummy_gem, 0);</div><div class='add'>+	drm_gpuvm_init(&amp;vm_ctx-&gt;gpuvm_mgr,</div><div class='add'>+		       is_userspace_context ? "PowerVR-user-VM" : "PowerVR-FW-VM",</div><div class='add'>+		       0, &amp;pvr_dev-&gt;base, &amp;vm_ctx-&gt;dummy_gem,</div><div class='add'>+		       0, 1ULL &lt;&lt; device_addr_bits, 0, 0, &amp;pvr_vm_gpuva_ops);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;vm_ctx-&gt;lock);</div><div class='add'>+	kref_init(&amp;vm_ctx-&gt;ref_count);</div><div class='add'>+</div><div class='ctx'> 	return vm_ctx;</div><div class='ctx'> </div><div class='ctx'> err_page_table_destroy:</div><div class='ctx'> 	pvr_mmu_context_destroy(vm_ctx-&gt;mmu_ctx);</div><div class='ctx'> </div><div class='del'>-err_put_ctx:</div><div class='del'>-	pvr_vm_context_put(vm_ctx);</div><div class='add'>+err_free:</div><div class='add'>+	kfree(vm_ctx);</div><div class='ctx'> </div><div class='ctx'> 	return ERR_PTR(err);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/imagination/pvr_vm_mips.c b/drivers/gpu/drm/imagination/pvr_vm_mips.c<br/>index 2bc7181a4c3e..b7fef3c797e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_vm_mips.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/imagination/pvr_vm_mips.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/imagination/pvr_vm_mips.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/imagination/pvr_vm_mips.c</a></div><div class='hunk'>@@ -152,8 +152,8 @@ pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)</div><div class='ctx'> 	u64 end;</div><div class='ctx'> 	u32 cache_policy;</div><div class='ctx'> 	u32 pte_flags;</div><div class='del'>-	u32 start_pfn;</div><div class='del'>-	u32 end_pfn;</div><div class='add'>+	s32 start_pfn;</div><div class='add'>+	s32 end_pfn;</div><div class='ctx'> 	s32 pfn;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -201,7 +201,7 @@ pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_unmap_pages:</div><div class='del'>-	for (; pfn &gt;= start_pfn; pfn--)</div><div class='add'>+	while (--pfn &gt;= start_pfn)</div><div class='ctx'> 		WRITE_ONCE(mips_data-&gt;pt[pfn], 0);</div><div class='ctx'> </div><div class='ctx'> 	pvr_mmu_flush_request_all(pvr_dev);</div><div class='head'>diff --git a/drivers/gpu/drm/lima/lima_ctx.c b/drivers/gpu/drm/lima/lima_ctx.c<br/>index 891d5cd5019a..8389f2d7d021 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/lima/lima_ctx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/lima/lima_ctx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/lima/lima_ctx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/lima/lima_ctx.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0 OR MIT</div><div class='ctx'> /* Copyright 2018-2019 Qiang Yu &lt;yuq825@gmail.com&gt; */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/pid.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "lima_device.h"</div><div class='head'>diff --git a/drivers/gpu/drm/loongson/lsdc_i2c.c b/drivers/gpu/drm/loongson/lsdc_i2c.c<br/>index 9625d0b1d0b4..ce90c25536d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/loongson/lsdc_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/loongson/lsdc_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/loongson/lsdc_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/loongson/lsdc_i2c.c</a></div><div class='hunk'>@@ -154,7 +154,6 @@ int lsdc_create_i2c_chan(struct drm_device *ddev,</div><div class='ctx'> 	adapter = &amp;li2c-&gt;adapter;</div><div class='ctx'> 	adapter-&gt;algo_data = &amp;li2c-&gt;bit;</div><div class='ctx'> 	adapter-&gt;owner = THIS_MODULE;</div><div class='del'>-	adapter-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	adapter-&gt;dev.parent = ddev-&gt;dev;</div><div class='ctx'> 	adapter-&gt;nr = -1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile<br/>index d4d193f60271..5e4436403b8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/Makefile</a></div><div class='hunk'>@@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \</div><div class='ctx'> 		  mtk_dsi.o \</div><div class='ctx'> 		  mtk_dpi.o \</div><div class='ctx'> 		  mtk_ethdr.o \</div><div class='del'>-		  mtk_mdp_rdma.o</div><div class='add'>+		  mtk_mdp_rdma.o \</div><div class='add'>+		  mtk_padding.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c<br/>index f47f417d8ba6..8519e9bade36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_cec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_cec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_cec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_cec.c</a></div><div class='hunk'>@@ -185,7 +185,6 @@ static int mtk_cec_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct mtk_cec *cec;</div><div class='del'>-	struct resource *res;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);</div><div class='hunk'>@@ -195,8 +194,7 @@ static int mtk_cec_probe(struct platform_device *pdev)</div><div class='ctx'> 	platform_set_drvdata(pdev, cec);</div><div class='ctx'> 	spin_lock_init(&amp;cec-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);</div><div class='del'>-	cec-&gt;regs = devm_ioremap_resource(dev, res);</div><div class='add'>+	cec-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='ctx'> 	if (IS_ERR(cec-&gt;regs)) {</div><div class='ctx'> 		ret = PTR_ERR(cec-&gt;regs);</div><div class='ctx'> 		dev_err(dev, "Failed to ioremap cec: %d\n", ret);</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c<br/>index 2209159d8855..40fe403086c3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_aal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_aal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_aal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_aal.c</a></div><div class='hunk'>@@ -168,7 +168,6 @@ static int mtk_disp_aal_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct mtk_disp_aal *priv;</div><div class='del'>-	struct resource *res;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='hunk'>@@ -181,8 +180,7 @@ static int mtk_disp_aal_probe(struct platform_device *pdev)</div><div class='ctx'> 		return PTR_ERR(priv-&gt;clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);</div><div class='del'>-	priv-&gt;regs = devm_ioremap_resource(dev, res);</div><div class='add'>+	priv-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='ctx'> 	if (IS_ERR(priv-&gt;regs)) {</div><div class='ctx'> 		dev_err(dev, "failed to ioremap aal\n");</div><div class='ctx'> 		return PTR_ERR(priv-&gt;regs);</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c<br/>index 4234ff7485e8..465cddce0d32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_ccorr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_ccorr.c</a></div><div class='hunk'>@@ -153,7 +153,6 @@ static int mtk_disp_ccorr_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct mtk_disp_ccorr *priv;</div><div class='del'>-	struct resource *res;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='hunk'>@@ -166,8 +165,7 @@ static int mtk_disp_ccorr_probe(struct platform_device *pdev)</div><div class='ctx'> 		return PTR_ERR(priv-&gt;clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);</div><div class='del'>-	priv-&gt;regs = devm_ioremap_resource(dev, res);</div><div class='add'>+	priv-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='ctx'> 	if (IS_ERR(priv-&gt;regs)) {</div><div class='ctx'> 		dev_err(dev, "failed to ioremap ccorr\n");</div><div class='ctx'> 		return PTR_ERR(priv-&gt;regs);</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h<br/>index 1311562d25cc..74fa56339383 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_drv.h</a></div><div class='hunk'>@@ -110,6 +110,8 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,</div><div class='ctx'> 			     unsigned int next);</div><div class='ctx'> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev,</div><div class='ctx'> 				unsigned int next);</div><div class='add'>+int mtk_ovl_adaptor_power_on(struct device *dev);</div><div class='add'>+void mtk_ovl_adaptor_power_off(struct device *dev);</div><div class='ctx'> int mtk_ovl_adaptor_clk_enable(struct device *dev);</div><div class='ctx'> void mtk_ovl_adaptor_clk_disable(struct device *dev);</div><div class='ctx'> void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,</div><div class='hunk'>@@ -151,6 +153,8 @@ void mtk_rdma_disable_vblank(struct device *dev);</div><div class='ctx'> const u32 *mtk_rdma_get_formats(struct device *dev);</div><div class='ctx'> size_t mtk_rdma_get_num_formats(struct device *dev);</div><div class='ctx'> </div><div class='add'>+int mtk_mdp_rdma_power_on(struct device *dev);</div><div class='add'>+void mtk_mdp_rdma_power_off(struct device *dev);</div><div class='ctx'> int mtk_mdp_rdma_clk_enable(struct device *dev);</div><div class='ctx'> void mtk_mdp_rdma_clk_disable(struct device *dev);</div><div class='ctx'> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);</div><div class='hunk'>@@ -160,4 +164,8 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,</div><div class='ctx'> const u32 *mtk_mdp_rdma_get_formats(struct device *dev);</div><div class='ctx'> size_t mtk_mdp_rdma_get_num_formats(struct device *dev);</div><div class='ctx'> </div><div class='add'>+int mtk_padding_clk_enable(struct device *dev);</div><div class='add'>+void mtk_padding_clk_disable(struct device *dev);</div><div class='add'>+void mtk_padding_start(struct device *dev);</div><div class='add'>+void mtk_padding_stop(struct device *dev);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c<br/>index f81dc34c9c3e..c1bc8b00d938 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_gamma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_gamma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_gamma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_gamma.c</a></div><div class='hunk'>@@ -203,7 +203,7 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)</div><div class='ctx'> 	/* Disable RELAY mode to pass the processed image */</div><div class='ctx'> 	cfg_val &amp;= ~GAMMA_RELAY_MODE;</div><div class='ctx'> </div><div class='del'>-	cfg_val = readl(gamma-&gt;regs + DISP_GAMMA_CFG);</div><div class='add'>+	writel(cfg_val, gamma-&gt;regs + DISP_GAMMA_CFG);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_gamma_config(struct device *dev, unsigned int w,</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c<br/>index e525a6b9e5b0..22f768d923d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_merge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_merge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_merge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_merge.c</a></div><div class='hunk'>@@ -103,7 +103,7 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)</div><div class='ctx'> 	mtk_ddp_write(cmdq_pkt, 0, &amp;priv-&gt;cmdq_reg, priv-&gt;regs,</div><div class='ctx'> 		      DISP_REG_MERGE_CTRL);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;async_clk)</div><div class='add'>+	if (!cmdq_pkt &amp;&amp; priv-&gt;async_clk)</div><div class='ctx'> 		reset_control_reset(priv-&gt;reset_ctl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c<br/>index 3fdef3ad4ffd..12a37f740bf4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c</a></div><div class='hunk'>@@ -27,13 +27,14 @@</div><div class='ctx'> #define MTK_OVL_ADAPTOR_LAYER_NUM 4</div><div class='ctx'> </div><div class='ctx'> enum mtk_ovl_adaptor_comp_type {</div><div class='del'>-	OVL_ADAPTOR_TYPE_RDMA = 0,</div><div class='del'>-	OVL_ADAPTOR_TYPE_MERGE,</div><div class='ctx'> 	OVL_ADAPTOR_TYPE_ETHDR,</div><div class='add'>+	OVL_ADAPTOR_TYPE_MDP_RDMA,</div><div class='add'>+	OVL_ADAPTOR_TYPE_MERGE,</div><div class='ctx'> 	OVL_ADAPTOR_TYPE_NUM,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum mtk_ovl_adaptor_comp_id {</div><div class='add'>+	OVL_ADAPTOR_ETHDR0,</div><div class='ctx'> 	OVL_ADAPTOR_MDP_RDMA0,</div><div class='ctx'> 	OVL_ADAPTOR_MDP_RDMA1,</div><div class='ctx'> 	OVL_ADAPTOR_MDP_RDMA2,</div><div class='hunk'>@@ -46,13 +47,14 @@ enum mtk_ovl_adaptor_comp_id {</div><div class='ctx'> 	OVL_ADAPTOR_MERGE1,</div><div class='ctx'> 	OVL_ADAPTOR_MERGE2,</div><div class='ctx'> 	OVL_ADAPTOR_MERGE3,</div><div class='del'>-	OVL_ADAPTOR_ETHDR0,</div><div class='ctx'> 	OVL_ADAPTOR_ID_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ovl_adaptor_comp_match {</div><div class='ctx'> 	enum mtk_ovl_adaptor_comp_type type;</div><div class='add'>+	enum mtk_ddp_comp_id comp_id;</div><div class='ctx'> 	int alias_id;</div><div class='add'>+	const struct mtk_ddp_comp_funcs *funcs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mtk_disp_ovl_adaptor {</div><div class='hunk'>@@ -62,25 +64,44 @@ struct mtk_disp_ovl_adaptor {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {</div><div class='del'>-	[OVL_ADAPTOR_TYPE_RDMA]		= "vdo1-rdma",</div><div class='del'>-	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",</div><div class='ctx'> 	[OVL_ADAPTOR_TYPE_ETHDR]	= "ethdr",</div><div class='add'>+	[OVL_ADAPTOR_TYPE_MDP_RDMA]	= "vdo1-rdma",</div><div class='add'>+	[OVL_ADAPTOR_TYPE_MERGE]	= "merge",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_ddp_comp_funcs ethdr = {</div><div class='add'>+	.clk_enable = mtk_ethdr_clk_enable,</div><div class='add'>+	.clk_disable = mtk_ethdr_clk_disable,</div><div class='add'>+	.start = mtk_ethdr_start,</div><div class='add'>+	.stop = mtk_ethdr_stop,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_ddp_comp_funcs merge = {</div><div class='add'>+	.clk_enable = mtk_merge_clk_enable,</div><div class='add'>+	.clk_disable = mtk_merge_clk_disable,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mtk_ddp_comp_funcs rdma = {</div><div class='add'>+	.power_on = mtk_mdp_rdma_power_on,</div><div class='add'>+	.power_off = mtk_mdp_rdma_power_off,</div><div class='add'>+	.clk_enable = mtk_mdp_rdma_clk_enable,</div><div class='add'>+	.clk_disable = mtk_mdp_rdma_clk_disable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA0]	= { OVL_ADAPTOR_TYPE_RDMA, 0 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA1]	= { OVL_ADAPTOR_TYPE_RDMA, 1 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA2]	= { OVL_ADAPTOR_TYPE_RDMA, 2 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA3]	= { OVL_ADAPTOR_TYPE_RDMA, 3 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA4]	= { OVL_ADAPTOR_TYPE_RDMA, 4 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA5]	= { OVL_ADAPTOR_TYPE_RDMA, 5 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA6]	= { OVL_ADAPTOR_TYPE_RDMA, 6 },</div><div class='del'>-	[OVL_ADAPTOR_MDP_RDMA7]	= { OVL_ADAPTOR_TYPE_RDMA, 7 },</div><div class='del'>-	[OVL_ADAPTOR_MERGE0]	= { OVL_ADAPTOR_TYPE_MERGE, 1 },</div><div class='del'>-	[OVL_ADAPTOR_MERGE1]	= { OVL_ADAPTOR_TYPE_MERGE, 2 },</div><div class='del'>-	[OVL_ADAPTOR_MERGE2]	= { OVL_ADAPTOR_TYPE_MERGE, 3 },</div><div class='del'>-	[OVL_ADAPTOR_MERGE3]	= { OVL_ADAPTOR_TYPE_MERGE, 4 },</div><div class='del'>-	[OVL_ADAPTOR_ETHDR0]	= { OVL_ADAPTOR_TYPE_ETHDR, 0 },</div><div class='add'>+	[OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &amp;ethdr },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &amp;rdma },</div><div class='add'>+	[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &amp;merge },</div><div class='add'>+	[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &amp;merge },</div><div class='add'>+	[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &amp;merge },</div><div class='add'>+	[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &amp;merge },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,</div><div class='hunk'>@@ -172,68 +193,112 @@ void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_start(struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	int i;</div><div class='ctx'> 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	mtk_ethdr_start(ovl_adaptor-&gt;ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);</div><div class='add'>+	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i] ||</div><div class='add'>+		    !comp_matches[i].funcs-&gt;start)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		comp_matches[i].funcs-&gt;start(ovl_adaptor-&gt;ovl_adaptor_comp[i]);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_stop(struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	int i;</div><div class='ctx'> 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	mtk_ethdr_stop(ovl_adaptor-&gt;ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);</div><div class='add'>+	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i] ||</div><div class='add'>+		    !comp_matches[i].funcs-&gt;stop)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		comp_matches[i].funcs-&gt;stop(ovl_adaptor-&gt;ovl_adaptor_comp[i]);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mtk_ovl_adaptor_clk_enable(struct device *dev)</div><div class='add'>+/**</div><div class='add'>+ * power_off - Power off the devices in OVL adaptor</div><div class='add'>+ * @dev: Device to be powered off</div><div class='add'>+ * @num: Number of the devices to be powered off</div><div class='add'>+ *</div><div class='add'>+ * Calls the .power_off() ovl_adaptor component callback if it is present.</div><div class='add'>+ */</div><div class='add'>+static inline void power_off(struct device *dev, int num)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='del'>-	struct device *comp;</div><div class='del'>-	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; OVL_ADAPTOR_MERGE0; i++) {</div><div class='del'>-		comp = ovl_adaptor-&gt;ovl_adaptor_comp[i];</div><div class='del'>-		ret = pm_runtime_get_sync(comp);</div><div class='add'>+	if (num &gt; OVL_ADAPTOR_ID_MAX)</div><div class='add'>+		num = OVL_ADAPTOR_ID_MAX;</div><div class='add'>+</div><div class='add'>+	for (i = num - 1; i &gt;= 0; i--) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i] ||</div><div class='add'>+		    !comp_matches[i].funcs-&gt;power_off)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		comp_matches[i].funcs-&gt;power_off(ovl_adaptor-&gt;ovl_adaptor_comp[i]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * mtk_ovl_adaptor_power_on - Power on the devices in OVL adaptor</div><div class='add'>+ * @dev: Device to be powered on</div><div class='add'>+ *</div><div class='add'>+ * Different from OVL, OVL adaptor is a pseudo device so</div><div class='add'>+ * we didn't define it in the device tree, pm_runtime_resume_and_get()</div><div class='add'>+ * called by .atomic_enable() power on no device in OVL adaptor,</div><div class='add'>+ * we have to implement a function to do the job instead.</div><div class='add'>+ *</div><div class='add'>+ * Return: Zero for success or negative number for failure.</div><div class='add'>+ */</div><div class='add'>+int mtk_ovl_adaptor_power_on(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i] ||</div><div class='add'>+		    !comp_matches[i].funcs-&gt;power_on)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ret = comp_matches[i].funcs-&gt;power_on(ovl_adaptor-&gt;ovl_adaptor_comp[i]);</div><div class='ctx'> 		if (ret &lt; 0) {</div><div class='ctx'> 			dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);</div><div class='del'>-			goto pwr_err;</div><div class='add'>+			power_off(dev, i);</div><div class='add'>+			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mtk_ovl_adaptor_power_off(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	power_off(dev, OVL_ADAPTOR_ID_MAX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int mtk_ovl_adaptor_clk_enable(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='add'>+	struct device *comp;</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='ctx'> 		comp = ovl_adaptor-&gt;ovl_adaptor_comp[i];</div><div class='del'>-</div><div class='del'>-		if (i &lt; OVL_ADAPTOR_MERGE0)</div><div class='del'>-			ret = mtk_mdp_rdma_clk_enable(comp);</div><div class='del'>-		else if (i &lt; OVL_ADAPTOR_ETHDR0)</div><div class='del'>-			ret = mtk_merge_clk_enable(comp);</div><div class='del'>-		else</div><div class='del'>-			ret = mtk_ethdr_clk_enable(comp);</div><div class='add'>+		if (!comp || !comp_matches[i].funcs-&gt;clk_enable)</div><div class='add'>+			continue;</div><div class='add'>+		ret = comp_matches[i].funcs-&gt;clk_enable(comp);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);</div><div class='del'>-			goto clk_err;</div><div class='add'>+			while (--i &gt;= 0)</div><div class='add'>+				comp_matches[i].funcs-&gt;clk_disable(comp);</div><div class='add'>+			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-</div><div class='del'>-clk_err:</div><div class='del'>-	while (--i &gt;= 0) {</div><div class='del'>-		comp = ovl_adaptor-&gt;ovl_adaptor_comp[i];</div><div class='del'>-		if (i &lt; OVL_ADAPTOR_MERGE0)</div><div class='del'>-			mtk_mdp_rdma_clk_disable(comp);</div><div class='del'>-		else if (i &lt; OVL_ADAPTOR_ETHDR0)</div><div class='del'>-			mtk_merge_clk_disable(comp);</div><div class='del'>-		else</div><div class='del'>-			mtk_ethdr_clk_disable(comp);</div><div class='del'>-	}</div><div class='del'>-	i = OVL_ADAPTOR_MERGE0;</div><div class='del'>-</div><div class='del'>-pwr_err:</div><div class='del'>-	while (--i &gt;= 0)</div><div class='del'>-		pm_runtime_put(ovl_adaptor-&gt;ovl_adaptor_comp[i]);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_clk_disable(struct device *dev)</div><div class='hunk'>@@ -244,15 +309,11 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='ctx'> 		comp = ovl_adaptor-&gt;ovl_adaptor_comp[i];</div><div class='del'>-</div><div class='del'>-		if (i &lt; OVL_ADAPTOR_MERGE0) {</div><div class='del'>-			mtk_mdp_rdma_clk_disable(comp);</div><div class='add'>+		if (!comp || !comp_matches[i].funcs-&gt;clk_disable)</div><div class='add'>+			continue;</div><div class='add'>+		comp_matches[i].funcs-&gt;clk_disable(comp);</div><div class='add'>+		if (i &lt; OVL_ADAPTOR_MERGE0)</div><div class='ctx'> 			pm_runtime_put(comp);</div><div class='del'>-		} else if (i &lt; OVL_ADAPTOR_ETHDR0) {</div><div class='del'>-			mtk_merge_clk_disable(comp);</div><div class='del'>-		} else {</div><div class='del'>-			mtk_ethdr_clk_disable(comp);</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -314,40 +375,31 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)</div><div class='ctx'> {</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);</div><div class='del'>-	mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);</div><div class='add'>+	int i;</div><div class='add'>+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i])</div><div class='add'>+			continue;</div><div class='add'>+		mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)</div><div class='ctx'> {</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);</div><div class='del'>-	mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);</div><div class='add'>+	int i;</div><div class='add'>+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; OVL_ADAPTOR_ID_MAX; i++) {</div><div class='add'>+		if (!ovl_adaptor-&gt;ovl_adaptor_comp[i])</div><div class='add'>+			continue;</div><div class='add'>+		mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)</div><div class='ctx'> {</div><div class='add'>+	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);</div><div class='hunk'>@@ -355,11 +407,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsig</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);</div><div class='ctx'> 	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);</div><div class='del'>-	mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)</div><div class='ctx'> {</div><div class='add'>+	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);</div><div class='hunk'>@@ -367,7 +419,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, un</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);</div><div class='ctx'> 	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);</div><div class='del'>-	mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,</div><div class='hunk'>@@ -386,17 +437,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {</div><div class='del'>-	{</div><div class='del'>-		.compatible = "mediatek,mt8195-vdo1-rdma",</div><div class='del'>-		.data = (void *)OVL_ADAPTOR_TYPE_RDMA,</div><div class='del'>-	}, {</div><div class='del'>-		.compatible = "mediatek,mt8195-disp-merge",</div><div class='del'>-		.data = (void *)OVL_ADAPTOR_TYPE_MERGE,</div><div class='del'>-	}, {</div><div class='del'>-		.compatible = "mediatek,mt8195-disp-ethdr",</div><div class='del'>-		.data = (void *)OVL_ADAPTOR_TYPE_ETHDR,</div><div class='del'>-	},</div><div class='del'>-	{},</div><div class='add'>+	{ .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },</div><div class='add'>+	{ .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },</div><div class='add'>+	{ .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },</div><div class='add'>+	{ /* sentinel */ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int compare_of(struct device *dev, void *data)</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c<br/>index e4c16ba9902d..2136a596efa1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_dp.c</a></div><div class='hunk'>@@ -2818,3 +2818,4 @@ MODULE_AUTHOR("Markus Schneider-Pargmann &lt;msp@baylibre.com&gt;");</div><div class='ctx'> MODULE_AUTHOR("Bo-Chen Chen &lt;rex-bc.chen@mediatek.com&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("MediaTek DisplayPort Driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_SOFTDEP("pre: phy_mtk_dp");</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c<br/>index 4e3d9f7b4d8c..beb7d9d08e97 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_dpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_dpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_dpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_dpi.c</a></div><div class='hunk'>@@ -966,20 +966,6 @@ static const struct mtk_dpi_conf mt8186_conf = {</div><div class='ctx'> 	.csc_enable_bit = CSC_ENABLE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct mtk_dpi_conf mt8188_dpintf_conf = {</div><div class='del'>-	.cal_factor = mt8195_dpintf_calculate_factor,</div><div class='del'>-	.max_clock_khz = 600000,</div><div class='del'>-	.output_fmts = mt8195_output_fmts,</div><div class='del'>-	.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),</div><div class='del'>-	.pixels_per_iter = 4,</div><div class='del'>-	.input_2pixel = false,</div><div class='del'>-	.dimension_mask = DPINTF_HPW_MASK,</div><div class='del'>-	.hvsize_mask = DPINTF_HSIZE_MASK,</div><div class='del'>-	.channel_swap_shift = DPINTF_CH_SWAP,</div><div class='del'>-	.yuv422_en_bit = DPINTF_YUV422_EN,</div><div class='del'>-	.csc_enable_bit = DPINTF_CSC_ENABLE,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct mtk_dpi_conf mt8192_conf = {</div><div class='ctx'> 	.cal_factor = mt8183_calculate_factor,</div><div class='ctx'> 	.reg_h_fre_con = 0xe0,</div><div class='hunk'>@@ -1103,7 +1089,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {</div><div class='ctx'> 	{ .compatible = "mediatek,mt8173-dpi", .data = &amp;mt8173_conf },</div><div class='ctx'> 	{ .compatible = "mediatek,mt8183-dpi", .data = &amp;mt8183_conf },</div><div class='ctx'> 	{ .compatible = "mediatek,mt8186-dpi", .data = &amp;mt8186_conf },</div><div class='del'>-	{ .compatible = "mediatek,mt8188-dp-intf", .data = &amp;mt8188_dpintf_conf },</div><div class='add'>+	{ .compatible = "mediatek,mt8188-dp-intf", .data = &amp;mt8195_dpintf_conf },</div><div class='ctx'> 	{ .compatible = "mediatek,mt8192-dpi", .data = &amp;mt8192_conf },</div><div class='ctx'> 	{ .compatible = "mediatek,mt8195-dp-intf", .data = &amp;mt8195_dpintf_conf },</div><div class='ctx'> 	{ /* sentinel */ },</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c<br/>index c277b9fae950..c729af3b9822 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_drm_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_crtc.c</a></div><div class='hunk'>@@ -721,7 +721,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc-&gt;base.id);</div><div class='ctx'> </div><div class='del'>-	ret = pm_runtime_resume_and_get(comp-&gt;dev);</div><div class='add'>+	ret = mtk_ddp_comp_power_on(comp);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		DRM_DEV_ERROR(comp-&gt;dev, "Failed to enable power domain: %d\n", ret);</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -731,7 +731,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	ret = mtk_crtc_ddp_hw_init(mtk_crtc);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		pm_runtime_put(comp-&gt;dev);</div><div class='add'>+		mtk_ddp_comp_power_off(comp);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -744,7 +744,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);</div><div class='ctx'> 	struct mtk_ddp_comp *comp = mtk_crtc-&gt;ddp_comp[0];</div><div class='del'>-	int i, ret;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc-&gt;base.id);</div><div class='ctx'> 	if (!mtk_crtc-&gt;enabled)</div><div class='hunk'>@@ -774,9 +774,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	drm_crtc_vblank_off(crtc);</div><div class='ctx'> 	mtk_crtc_ddp_hw_fini(mtk_crtc);</div><div class='del'>-	ret = pm_runtime_put(comp-&gt;dev);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		DRM_DEV_ERROR(comp-&gt;dev, "Failed to disable power domain: %d\n", ret);</div><div class='add'>+	mtk_ddp_comp_power_off(comp);</div><div class='ctx'> </div><div class='ctx'> 	mtk_crtc-&gt;enabled = false;</div><div class='ctx'> }</div><div class='hunk'>@@ -788,6 +786,7 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,</div><div class='ctx'> 									  crtc);</div><div class='ctx'> 	struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);</div><div class='ctx'> 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (mtk_crtc-&gt;event &amp;&amp; mtk_crtc_state-&gt;base.event)</div><div class='ctx'> 		DRM_ERROR("new event while there is still a pending event\n");</div><div class='hunk'>@@ -795,7 +794,11 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,</div><div class='ctx'> 	if (mtk_crtc_state-&gt;base.event) {</div><div class='ctx'> 		mtk_crtc_state-&gt;base.event-&gt;pipe = drm_crtc_index(crtc);</div><div class='ctx'> 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);</div><div class='add'>+</div><div class='add'>+		spin_lock_irqsave(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='ctx'> 		mtk_crtc-&gt;event = mtk_crtc_state-&gt;base.event;</div><div class='add'>+		spin_unlock_irqrestore(&amp;crtc-&gt;dev-&gt;event_lock, flags);</div><div class='add'>+</div><div class='ctx'> 		mtk_crtc_state-&gt;base.event = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -921,7 +924,14 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,</div><div class='ctx'> </div><div class='ctx'> struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc)</div><div class='ctx'> {</div><div class='del'>-	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);</div><div class='add'>+	struct mtk_drm_crtc *mtk_crtc = NULL;</div><div class='add'>+</div><div class='add'>+	if (!crtc)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	mtk_crtc = to_mtk_crtc(crtc);</div><div class='add'>+	if (!mtk_crtc)</div><div class='add'>+		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	return mtk_crtc-&gt;dma_dev;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c<br/>index 3046c0409353..a9b5a21cde2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c</a></div><div class='hunk'>@@ -398,6 +398,8 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {</div><div class='add'>+	.power_on = mtk_ovl_adaptor_power_on,</div><div class='add'>+	.power_off = mtk_ovl_adaptor_power_off,</div><div class='ctx'> 	.clk_enable = mtk_ovl_adaptor_clk_enable,</div><div class='ctx'> 	.clk_disable = mtk_ovl_adaptor_clk_disable,</div><div class='ctx'> 	.config = mtk_ovl_adaptor_config,</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h<br/>index 4bae55bdb034..15b2eafff438 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> #define MTK_DRM_DDP_COMP_H</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/soc/mediatek/mtk-cmdq.h&gt;</div><div class='ctx'> #include &lt;linux/soc/mediatek/mtk-mmsys.h&gt;</div><div class='ctx'> #include &lt;linux/soc/mediatek/mtk-mutex.h&gt;</div><div class='hunk'>@@ -46,6 +47,8 @@ enum mtk_ddp_comp_type {</div><div class='ctx'> struct mtk_ddp_comp;</div><div class='ctx'> struct cmdq_pkt;</div><div class='ctx'> struct mtk_ddp_comp_funcs {</div><div class='add'>+	int (*power_on)(struct device *dev);</div><div class='add'>+	void (*power_off)(struct device *dev);</div><div class='ctx'> 	int (*clk_enable)(struct device *dev);</div><div class='ctx'> 	void (*clk_disable)(struct device *dev);</div><div class='ctx'> 	void (*config)(struct device *dev, unsigned int w,</div><div class='hunk'>@@ -92,6 +95,23 @@ struct mtk_ddp_comp {</div><div class='ctx'> 	const struct mtk_ddp_comp_funcs *funcs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static inline int mtk_ddp_comp_power_on(struct mtk_ddp_comp *comp)</div><div class='add'>+{</div><div class='add'>+	if (comp-&gt;funcs &amp;&amp; comp-&gt;funcs-&gt;power_on)</div><div class='add'>+		return comp-&gt;funcs-&gt;power_on(comp-&gt;dev);</div><div class='add'>+	else</div><div class='add'>+		return pm_runtime_resume_and_get(comp-&gt;dev);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void mtk_ddp_comp_power_off(struct mtk_ddp_comp *comp)</div><div class='add'>+{</div><div class='add'>+	if (comp-&gt;funcs &amp;&amp; comp-&gt;funcs-&gt;power_off)</div><div class='add'>+		comp-&gt;funcs-&gt;power_off(comp-&gt;dev);</div><div class='add'>+	else</div><div class='add'>+		pm_runtime_put(comp-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp)</div><div class='ctx'> {</div><div class='ctx'> 	if (comp-&gt;funcs &amp;&amp; comp-&gt;funcs-&gt;clk_enable)</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c<br/>index 2dfaa613276a..14a1e0157cc4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_drm_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_drv.c</a></div><div class='hunk'>@@ -5,7 +5,6 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/component.h&gt;</div><div class='del'>-#include &lt;linux/iommu.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/of_platform.h&gt;</div><div class='hunk'>@@ -443,6 +442,7 @@ static int mtk_drm_kms_init(struct drm_device *drm)</div><div class='ctx'> 	struct mtk_drm_private *private = drm-&gt;dev_private;</div><div class='ctx'> 	struct mtk_drm_private *priv_n;</div><div class='ctx'> 	struct device *dma_dev = NULL;</div><div class='add'>+	struct drm_crtc *crtc;</div><div class='ctx'> 	int ret, i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (drm_firmware_drivers_only())</div><div class='hunk'>@@ -519,7 +519,9 @@ static int mtk_drm_kms_init(struct drm_device *drm)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use OVL device for all DMA memory allocations */</div><div class='del'>-	dma_dev = mtk_drm_crtc_dma_dev_get(drm_crtc_from_index(drm, 0));</div><div class='add'>+	crtc = drm_crtc_from_index(drm, 0);</div><div class='add'>+	if (crtc)</div><div class='add'>+		dma_dev = mtk_drm_crtc_dma_dev_get(crtc);</div><div class='ctx'> 	if (!dma_dev) {</div><div class='ctx'> 		ret = -ENODEV;</div><div class='ctx'> 		dev_err(drm-&gt;dev, "Need at least one OVL device\n");</div><div class='hunk'>@@ -608,9 +610,6 @@ static int mtk_drm_bind(struct device *dev)</div><div class='ctx'> 	struct drm_device *drm;</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='del'>-	if (!iommu_present(&amp;platform_bus_type))</div><div class='del'>-		return -EPROBE_DEFER;</div><div class='del'>-</div><div class='ctx'> 	pdev = of_find_device_by_node(private-&gt;mutex_node);</div><div class='ctx'> 	if (!pdev) {</div><div class='ctx'> 		dev_err(dev, "Waiting for disp-mutex device %pOF\n",</div><div class='hunk'>@@ -1000,6 +999,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {</div><div class='ctx'> 	&amp;mtk_dsi_driver,</div><div class='ctx'> 	&amp;mtk_ethdr_driver,</div><div class='ctx'> 	&amp;mtk_mdp_rdma_driver,</div><div class='add'>+	&amp;mtk_padding_driver,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init mtk_drm_init(void)</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h<br/>index 6f98fff4f1a4..33fadb08dc1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_drm_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_drm_drv.h</a></div><div class='hunk'>@@ -77,5 +77,5 @@ extern struct platform_driver mtk_dpi_driver;</div><div class='ctx'> extern struct platform_driver mtk_dsi_driver;</div><div class='ctx'> extern struct platform_driver mtk_ethdr_driver;</div><div class='ctx'> extern struct platform_driver mtk_mdp_rdma_driver;</div><div class='del'>-</div><div class='add'>+extern struct platform_driver mtk_padding_driver;</div><div class='ctx'> #endif /* MTK_DRM_DRV_H */</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c<br/>index d675c954befe..54e46e440e0f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c</a></div><div class='hunk'>@@ -297,7 +297,6 @@ static int mtk_hdmi_ddc_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	strscpy(ddc-&gt;adap.name, "mediatek-hdmi-ddc", sizeof(ddc-&gt;adap.name));</div><div class='ctx'> 	ddc-&gt;adap.owner = THIS_MODULE;</div><div class='del'>-	ddc-&gt;adap.class = I2C_CLASS_DDC;</div><div class='ctx'> 	ddc-&gt;adap.algo = &amp;mtk_hdmi_ddc_algorithm;</div><div class='ctx'> 	ddc-&gt;adap.retries = 3;</div><div class='ctx'> 	ddc-&gt;adap.dev.of_node = dev-&gt;of_node;</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c<br/>index c3adaeefd551..ee9ce9b6d078 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mediatek/mtk_mdp_rdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_mdp_rdma.c</a></div><div class='hunk'>@@ -242,12 +242,27 @@ size_t mtk_mdp_rdma_get_num_formats(struct device *dev)</div><div class='ctx'> 	return ARRAY_SIZE(formats);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int mtk_mdp_rdma_power_on(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	int ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "Failed to power on: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mtk_mdp_rdma_power_off(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	pm_runtime_put(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int mtk_mdp_rdma_clk_enable(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	clk_prepare_enable(rdma-&gt;clk);</div><div class='del'>-	return 0;</div><div class='add'>+	return clk_prepare_enable(rdma-&gt;clk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mtk_mdp_rdma_clk_disable(struct device *dev)</div><div class='head'>diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c<br/>new file mode 100644<br/>index 000000000000..0d6451c149b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mediatek/mtk_padding.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mediatek/mtk_padding.c</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 MediaTek Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/component.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/soc/mediatek/mtk-cmdq.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mtk_disp_drv.h"</div><div class='add'>+#include "mtk_drm_crtc.h"</div><div class='add'>+#include "mtk_drm_ddp_comp.h"</div><div class='add'>+</div><div class='add'>+#define PADDING_CONTROL_REG	0x00</div><div class='add'>+#define PADDING_BYPASS			BIT(0)</div><div class='add'>+#define PADDING_ENABLE			BIT(1)</div><div class='add'>+#define PADDING_PIC_SIZE_REG	0x04</div><div class='add'>+#define PADDING_H_REG		0x08 /* horizontal */</div><div class='add'>+#define PADDING_V_REG		0x0c /* vertical */</div><div class='add'>+#define PADDING_COLOR_REG	0x10</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct mtk_padding - Basic information of the Padding</div><div class='add'>+ * @clk: Clock of the module</div><div class='add'>+ * @reg: Virtual address of the Padding for CPU to access</div><div class='add'>+ * @cmdq_reg: CMDQ setting of the Padding</div><div class='add'>+ *</div><div class='add'>+ * Every Padding should have different clock source, register base, and</div><div class='add'>+ * CMDQ settings, we stored these differences all together.</div><div class='add'>+ */</div><div class='add'>+struct mtk_padding {</div><div class='add'>+	struct clk		*clk;</div><div class='add'>+	void __iomem		*reg;</div><div class='add'>+	struct cmdq_client_reg	cmdq_reg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int mtk_padding_clk_enable(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_padding *padding = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	return clk_prepare_enable(padding-&gt;clk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mtk_padding_clk_disable(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_padding *padding = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	clk_disable_unprepare(padding-&gt;clk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mtk_padding_start(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_padding *padding = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	writel(PADDING_ENABLE | PADDING_BYPASS,</div><div class='add'>+	       padding-&gt;reg + PADDING_CONTROL_REG);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Notice that even the padding is in bypass mode,</div><div class='add'>+	 * all the settings must be cleared to 0 or</div><div class='add'>+	 * undefined behaviors could happen</div><div class='add'>+	 */</div><div class='add'>+	writel(0, padding-&gt;reg + PADDING_PIC_SIZE_REG);</div><div class='add'>+	writel(0, padding-&gt;reg + PADDING_H_REG);</div><div class='add'>+	writel(0, padding-&gt;reg + PADDING_V_REG);</div><div class='add'>+	writel(0, padding-&gt;reg + PADDING_COLOR_REG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mtk_padding_stop(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mtk_padding *padding = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	writel(0, padding-&gt;reg + PADDING_CONTROL_REG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mtk_padding_bind(struct device *dev, struct device *master, void *data)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_padding_unbind(struct device *dev, struct device *master, void *data)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct component_ops mtk_padding_component_ops = {</div><div class='add'>+	.bind	= mtk_padding_bind,</div><div class='add'>+	.unbind = mtk_padding_unbind,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mtk_padding_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct mtk_padding *priv;</div><div class='add'>+	struct resource *res;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;clk = devm_clk_get(dev, NULL);</div><div class='add'>+	if (IS_ERR(priv-&gt;clk)) {</div><div class='add'>+		dev_err(dev, "failed to get clk\n");</div><div class='add'>+		return PTR_ERR(priv-&gt;clk);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	priv-&gt;reg = devm_platform_get_and_ioremap_resource(pdev, 0, &amp;res);</div><div class='add'>+	if (IS_ERR(priv-&gt;reg)) {</div><div class='add'>+		dev_err(dev, "failed to do ioremap\n");</div><div class='add'>+		return PTR_ERR(priv-&gt;reg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#if IS_REACHABLE(CONFIG_MTK_CMDQ)</div><div class='add'>+	ret = cmdq_dev_get_client_reg(dev, &amp;priv-&gt;cmdq_reg, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to get gce client reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	platform_set_drvdata(pdev, priv);</div><div class='add'>+</div><div class='add'>+	ret = devm_pm_runtime_enable(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = component_add(dev, &amp;mtk_padding_component_ops);</div><div class='add'>+	if (ret) {</div><div class='add'>+		pm_runtime_disable(dev);</div><div class='add'>+		return dev_err_probe(dev, ret, "failed to add component\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mtk_padding_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	component_del(&amp;pdev-&gt;dev, &amp;mtk_padding_component_ops);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id mtk_padding_driver_dt_match[] = {</div><div class='add'>+	{ .compatible = "mediatek,mt8188-disp-padding" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);</div><div class='add'>+</div><div class='add'>+struct platform_driver mtk_padding_driver = {</div><div class='add'>+	.probe		= mtk_padding_probe,</div><div class='add'>+	.remove		= mtk_padding_remove,</div><div class='add'>+	.driver		= {</div><div class='add'>+		.name	= "mediatek-disp-padding",</div><div class='add'>+		.owner	= THIS_MODULE,</div><div class='add'>+		.of_match_table = mtk_padding_driver_dt_match,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h<br/>index 57c7edcab602..765e49fd8911 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_drv.h</a></div><div class='hunk'>@@ -392,6 +392,11 @@ void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,</div><div class='ctx'> 	.destroy = drm_plane_cleanup, \</div><div class='ctx'> 	DRM_GEM_SHADOW_PLANE_FUNCS</div><div class='ctx'> </div><div class='add'>+void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format);</div><div class='add'>+void mgag200_crtc_set_gamma(struct mga_device *mdev,</div><div class='add'>+			    const struct drm_format_info *format,</div><div class='add'>+			    struct drm_color_lut *lut);</div><div class='add'>+</div><div class='ctx'> enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,</div><div class='ctx'> 						    const struct drm_display_mode *mode);</div><div class='ctx'> int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c b/drivers/gpu/drm/mgag200/mgag200_g200er.c<br/>index bce267e0f7de..8d4538b71047 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200er.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_g200er.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200er.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200er.c</a></div><div class='hunk'>@@ -202,6 +202,11 @@ static void mgag200_g200er_crtc_helper_atomic_enable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	mgag200_g200er_reset_tagfifo(mdev);</div><div class='ctx'> </div><div class='add'>+	if (crtc_state-&gt;gamma_lut)</div><div class='add'>+		mgag200_crtc_set_gamma(mdev, format, crtc_state-&gt;gamma_lut-&gt;data);</div><div class='add'>+	else</div><div class='add'>+		mgag200_crtc_set_gamma_linear(mdev, format);</div><div class='add'>+</div><div class='ctx'> 	mgag200_enable_display(mdev);</div><div class='ctx'> </div><div class='ctx'> 	if (funcs-&gt;enable_vidrst)</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c b/drivers/gpu/drm/mgag200/mgag200_g200ev.c<br/>index ac957f42abe1..56e6f986bff3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200ev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_g200ev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200ev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200ev.c</a></div><div class='hunk'>@@ -203,6 +203,11 @@ static void mgag200_g200ev_crtc_helper_atomic_enable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	mgag200_g200ev_set_hiprilvl(mdev);</div><div class='ctx'> </div><div class='add'>+	if (crtc_state-&gt;gamma_lut)</div><div class='add'>+		mgag200_crtc_set_gamma(mdev, format, crtc_state-&gt;gamma_lut-&gt;data);</div><div class='add'>+	else</div><div class='add'>+		mgag200_crtc_set_gamma_linear(mdev, format);</div><div class='add'>+</div><div class='ctx'> 	mgag200_enable_display(mdev);</div><div class='ctx'> </div><div class='ctx'> 	if (funcs-&gt;enable_vidrst)</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c<br/>index bd6e573c9a1a..ff2b3c6622e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200se.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_g200se.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_g200se.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_g200se.c</a></div><div class='hunk'>@@ -334,6 +334,11 @@ static void mgag200_g200se_crtc_helper_atomic_enable(struct drm_crtc *crtc,</div><div class='ctx'> </div><div class='ctx'> 	mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, format);</div><div class='ctx'> </div><div class='add'>+	if (crtc_state-&gt;gamma_lut)</div><div class='add'>+		mgag200_crtc_set_gamma(mdev, format, crtc_state-&gt;gamma_lut-&gt;data);</div><div class='add'>+	else</div><div class='add'>+		mgag200_crtc_set_gamma_linear(mdev, format);</div><div class='add'>+</div><div class='ctx'> 	mgag200_enable_display(mdev);</div><div class='ctx'> </div><div class='ctx'> 	if (funcs-&gt;enable_vidrst)</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_i2c.c b/drivers/gpu/drm/mgag200/mgag200_i2c.c<br/>index 0c48bdf3e7f8..423eb302be7e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_i2c.c</a></div><div class='hunk'>@@ -106,7 +106,6 @@ int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c)</div><div class='ctx'> 	i2c-&gt;data = BIT(info-&gt;i2c.data_bit);</div><div class='ctx'> 	i2c-&gt;clock = BIT(info-&gt;i2c.clock_bit);</div><div class='ctx'> 	i2c-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	i2c-&gt;adapter.dev.parent = dev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;dev = dev;</div><div class='ctx'> 	i2c_set_adapdata(&amp;i2c-&gt;adapter, i2c);</div><div class='head'>diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c<br/>index 1596937bb5ad..0eb769dd76ce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_mode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/mgag200/mgag200_mode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/mgag200/mgag200_mode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/mgag200/mgag200_mode.c</a></div><div class='hunk'>@@ -28,8 +28,8 @@</div><div class='ctx'>  * This file contains setup code for the CRTC.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,</div><div class='del'>-					  const struct drm_format_info *format)</div><div class='add'>+void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,</div><div class='add'>+				   const struct drm_format_info *format)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -65,9 +65,9 @@ static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mgag200_crtc_set_gamma(struct mga_device *mdev,</div><div class='del'>-				   const struct drm_format_info *format,</div><div class='del'>-				   struct drm_color_lut *lut)</div><div class='add'>+void mgag200_crtc_set_gamma(struct mga_device *mdev,</div><div class='add'>+			    const struct drm_format_info *format,</div><div class='add'>+			    struct drm_color_lut *lut)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig<br/>index 6309a857ca31..f202f26adab2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/Kconfig</a></div><div class='hunk'>@@ -6,6 +6,7 @@ config DRM_MSM</div><div class='ctx'> 	depends on ARCH_QCOM || SOC_IMX5 || COMPILE_TEST</div><div class='ctx'> 	depends on COMMON_CLK</div><div class='ctx'> 	depends on IOMMU_SUPPORT</div><div class='add'>+	depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n</div><div class='ctx'> 	depends on QCOM_OCMEM || QCOM_OCMEM=n</div><div class='ctx'> 	depends on QCOM_LLCC || QCOM_LLCC=n</div><div class='ctx'> 	depends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=n</div><div class='hunk'>@@ -16,6 +17,7 @@ config DRM_MSM</div><div class='ctx'> 	select DRM_DP_AUX_BUS</div><div class='ctx'> 	select DRM_DISPLAY_DP_HELPER</div><div class='ctx'> 	select DRM_DISPLAY_HELPER</div><div class='add'>+	select DRM_EXEC</div><div class='ctx'> 	select DRM_KMS_HELPER</div><div class='ctx'> 	select DRM_PANEL</div><div class='ctx'> 	select DRM_BRIDGE</div><div class='head'>diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile<br/>index 49671364fdcf..b1173128b5b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/Makefile</a></div><div class='hunk'>@@ -63,6 +63,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \</div><div class='ctx'> 	disp/dpu1/dpu_encoder_phys_wb.o \</div><div class='ctx'> 	disp/dpu1/dpu_formats.o \</div><div class='ctx'> 	disp/dpu1/dpu_hw_catalog.o \</div><div class='add'>+	disp/dpu1/dpu_hw_cdm.o \</div><div class='ctx'> 	disp/dpu1/dpu_hw_ctl.o \</div><div class='ctx'> 	disp/dpu1/dpu_hw_dsc.o \</div><div class='ctx'> 	disp/dpu1/dpu_hw_dsc_1_2.o \</div><div class='head'>diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c<br/>index e5916c106796..c003f970189b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/a5xx_gpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/adreno/a5xx_gpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/a5xx_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/a5xx_gpu.c</a></div><div class='hunk'>@@ -684,7 +684,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)</div><div class='ctx'> {</div><div class='ctx'> 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);</div><div class='ctx'> 	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);</div><div class='del'>-	u32 regbit;</div><div class='add'>+	u32 hbb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);</div><div class='hunk'>@@ -820,18 +820,15 @@ static int a5xx_hw_init(struct msm_gpu *gpu)</div><div class='ctx'> </div><div class='ctx'> 	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);</div><div class='ctx'> </div><div class='del'>-	/* Set the highest bank bit */</div><div class='del'>-	if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))</div><div class='del'>-		regbit = 2;</div><div class='del'>-	else</div><div class='del'>-		regbit = 1;</div><div class='add'>+	BUG_ON(adreno_gpu-&gt;ubwc_config.highest_bank_bit &lt; 13);</div><div class='add'>+	hbb = adreno_gpu-&gt;ubwc_config.highest_bank_bit - 13;</div><div class='ctx'> </div><div class='del'>-	gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit &lt;&lt; 7);</div><div class='del'>-	gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit &lt;&lt; 1);</div><div class='add'>+	gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb &lt;&lt; 7);</div><div class='add'>+	gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb &lt;&lt; 1);</div><div class='ctx'> </div><div class='ctx'> 	if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||</div><div class='ctx'> 	    adreno_is_a540(adreno_gpu))</div><div class='del'>-		gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit);</div><div class='add'>+		gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, hbb);</div><div class='ctx'> </div><div class='ctx'> 	/* Disable All flat shading optimization (ALLFLATOPTDIS) */</div><div class='ctx'> 	gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 &lt;&lt; 10));</div><div class='hunk'>@@ -1785,5 +1782,11 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)</div><div class='ctx'> 	/* Set up the preemption specific bits and pieces for each ringbuffer */</div><div class='ctx'> 	a5xx_preempt_init(gpu);</div><div class='ctx'> </div><div class='add'>+	/* Set the highest bank bit */</div><div class='add'>+	if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))</div><div class='add'>+		adreno_gpu-&gt;ubwc_config.highest_bank_bit = 15;</div><div class='add'>+	else</div><div class='add'>+		adreno_gpu-&gt;ubwc_config.highest_bank_bit = 14;</div><div class='add'>+</div><div class='ctx'> 	return gpu;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c<br/>index 7a0220d29a23..c0bc924cd302 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/a6xx_gpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/adreno/a6xx_gpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/a6xx_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/a6xx_gpu.c</a></div><div class='hunk'>@@ -1270,87 +1270,92 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)</div><div class='ctx'> 	gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void a6xx_set_ubwc_config(struct msm_gpu *gpu)</div><div class='add'>+static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)</div><div class='ctx'> {</div><div class='del'>-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);</div><div class='ctx'> 	/* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */</div><div class='del'>-	u32 rgb565_predicator = 0;</div><div class='add'>+	gpu-&gt;ubwc_config.rgb565_predicator = 0;</div><div class='ctx'> 	/* Unknown, introduced with A650 family */</div><div class='del'>-	u32 uavflagprd_inv = 0;</div><div class='add'>+	gpu-&gt;ubwc_config.uavflagprd_inv = 0;</div><div class='ctx'> 	/* Whether the minimum access length is 64 bits */</div><div class='del'>-	u32 min_acc_len = 0;</div><div class='add'>+	gpu-&gt;ubwc_config.min_acc_len = 0;</div><div class='ctx'> 	/* Entirely magic, per-GPU-gen value */</div><div class='del'>-	u32 ubwc_mode = 0;</div><div class='add'>+	gpu-&gt;ubwc_config.ubwc_mode = 0;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The Highest Bank Bit value represents the bit of the highest DDR bank.</div><div class='del'>-	 * We then subtract 13 from it (13 is the minimum value allowed by hw) and</div><div class='del'>-	 * write the lowest two bits of the remaining value as hbb_lo and the</div><div class='del'>-	 * one above it as hbb_hi to the hardware. This should ideally use DRAM</div><div class='del'>-	 * type detection.</div><div class='add'>+	 * This should ideally use DRAM type detection.</div><div class='ctx'> 	 */</div><div class='del'>-	u32 hbb_hi = 0;</div><div class='del'>-	u32 hbb_lo = 2;</div><div class='del'>-	/* Unknown, introduced with A640/680 */</div><div class='del'>-	u32 amsbc = 0;</div><div class='add'>+	gpu-&gt;ubwc_config.highest_bank_bit = 15;</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_a610(adreno_gpu)) {</div><div class='del'>-		/* HBB = 14 */</div><div class='del'>-		hbb_lo = 1;</div><div class='del'>-		min_acc_len = 1;</div><div class='del'>-		ubwc_mode = 1;</div><div class='add'>+	if (adreno_is_a610(gpu)) {</div><div class='add'>+		gpu-&gt;ubwc_config.highest_bank_bit = 14;</div><div class='add'>+		gpu-&gt;ubwc_config.min_acc_len = 1;</div><div class='add'>+		gpu-&gt;ubwc_config.ubwc_mode = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* a618 is using the hw default values */</div><div class='del'>-	if (adreno_is_a618(adreno_gpu))</div><div class='add'>+	if (adreno_is_a618(gpu))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_a619_holi(adreno_gpu))</div><div class='del'>-		hbb_lo = 0;</div><div class='add'>+	if (adreno_is_a619_holi(gpu))</div><div class='add'>+		gpu-&gt;ubwc_config.highest_bank_bit = 13;</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_a640_family(adreno_gpu))</div><div class='del'>-		amsbc = 1;</div><div class='add'>+	if (adreno_is_a640_family(gpu))</div><div class='add'>+		gpu-&gt;ubwc_config.amsbc = 1;</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_a650(adreno_gpu) ||</div><div class='del'>-	    adreno_is_a660(adreno_gpu) ||</div><div class='del'>-	    adreno_is_a730(adreno_gpu) ||</div><div class='del'>-	    adreno_is_a740_family(adreno_gpu)) {</div><div class='add'>+	if (adreno_is_a650(gpu) ||</div><div class='add'>+	    adreno_is_a660(gpu) ||</div><div class='add'>+	    adreno_is_a690(gpu) ||</div><div class='add'>+	    adreno_is_a730(gpu) ||</div><div class='add'>+	    adreno_is_a740_family(gpu)) {</div><div class='ctx'> 		/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */</div><div class='del'>-		hbb_lo = 3;</div><div class='del'>-		amsbc = 1;</div><div class='del'>-		rgb565_predicator = 1;</div><div class='del'>-		uavflagprd_inv = 2;</div><div class='add'>+		gpu-&gt;ubwc_config.highest_bank_bit = 16;</div><div class='add'>+		gpu-&gt;ubwc_config.amsbc = 1;</div><div class='add'>+		gpu-&gt;ubwc_config.rgb565_predicator = 1;</div><div class='add'>+		gpu-&gt;ubwc_config.uavflagprd_inv = 2;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_a690(adreno_gpu)) {</div><div class='del'>-		hbb_lo = 2;</div><div class='del'>-		amsbc = 1;</div><div class='del'>-		rgb565_predicator = 1;</div><div class='del'>-		uavflagprd_inv = 2;</div><div class='add'>+	if (adreno_is_7c3(gpu)) {</div><div class='add'>+		gpu-&gt;ubwc_config.highest_bank_bit = 14;</div><div class='add'>+		gpu-&gt;ubwc_config.amsbc = 1;</div><div class='add'>+		gpu-&gt;ubwc_config.rgb565_predicator = 1;</div><div class='add'>+		gpu-&gt;ubwc_config.uavflagprd_inv = 2;</div><div class='ctx'> 	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (adreno_is_7c3(adreno_gpu)) {</div><div class='del'>-		hbb_lo = 1;</div><div class='del'>-		amsbc = 1;</div><div class='del'>-		rgb565_predicator = 1;</div><div class='del'>-		uavflagprd_inv = 2;</div><div class='del'>-	}</div><div class='add'>+static void a6xx_set_ubwc_config(struct msm_gpu *gpu)</div><div class='add'>+{</div><div class='add'>+	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);</div><div class='add'>+	/*</div><div class='add'>+	 * We subtract 13 from the highest bank bit (13 is the minimum value</div><div class='add'>+	 * allowed by hw) and write the lowest two bits of the remaining value</div><div class='add'>+	 * as hbb_lo and the one above it as hbb_hi to the hardware.</div><div class='add'>+	 */</div><div class='add'>+	BUG_ON(adreno_gpu-&gt;ubwc_config.highest_bank_bit &lt; 13);</div><div class='add'>+	u32 hbb = adreno_gpu-&gt;ubwc_config.highest_bank_bit - 13;</div><div class='add'>+	u32 hbb_hi = hbb &gt;&gt; 2;</div><div class='add'>+	u32 hbb_lo = hbb &amp; 3;</div><div class='ctx'> </div><div class='ctx'> 	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,</div><div class='del'>-		  rgb565_predicator &lt;&lt; 11 | hbb_hi &lt;&lt; 10 | amsbc &lt;&lt; 4 |</div><div class='del'>-		  min_acc_len &lt;&lt; 3 | hbb_lo &lt;&lt; 1 | ubwc_mode);</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.rgb565_predicator &lt;&lt; 11 |</div><div class='add'>+		  hbb_hi &lt;&lt; 10 | adreno_gpu-&gt;ubwc_config.amsbc &lt;&lt; 4 |</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.min_acc_len &lt;&lt; 3 |</div><div class='add'>+		  hbb_lo &lt;&lt; 1 | adreno_gpu-&gt;ubwc_config.ubwc_mode);</div><div class='ctx'> </div><div class='ctx'> 	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi &lt;&lt; 4 |</div><div class='del'>-		  min_acc_len &lt;&lt; 3 | hbb_lo &lt;&lt; 1 | ubwc_mode);</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.min_acc_len &lt;&lt; 3 |</div><div class='add'>+		  hbb_lo &lt;&lt; 1 | adreno_gpu-&gt;ubwc_config.ubwc_mode);</div><div class='ctx'> </div><div class='ctx'> 	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi &lt;&lt; 10 |</div><div class='del'>-		  uavflagprd_inv &lt;&lt; 4 | min_acc_len &lt;&lt; 3 |</div><div class='del'>-		  hbb_lo &lt;&lt; 1 | ubwc_mode);</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.uavflagprd_inv &lt;&lt; 4 |</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.min_acc_len &lt;&lt; 3 |</div><div class='add'>+		  hbb_lo &lt;&lt; 1 | adreno_gpu-&gt;ubwc_config.ubwc_mode);</div><div class='ctx'> </div><div class='ctx'> 	if (adreno_is_a7xx(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,</div><div class='ctx'> 			  FIELD_PREP(GENMASK(8, 5), hbb_lo));</div><div class='ctx'> </div><div class='del'>-	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len &lt;&lt; 23 | hbb_lo &lt;&lt; 21);</div><div class='add'>+	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,</div><div class='add'>+		  adreno_gpu-&gt;ubwc_config.min_acc_len &lt;&lt; 23 | hbb_lo &lt;&lt; 21);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int a6xx_cp_init(struct msm_gpu *gpu)</div><div class='hunk'>@@ -1741,7 +1746,9 @@ static int hw_init(struct msm_gpu *gpu)</div><div class='ctx'> 	/* Setting the primFifo thresholds default values,</div><div class='ctx'> 	 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer</div><div class='ctx'> 	*/</div><div class='del'>-	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu))</div><div class='add'>+	if (adreno_is_a690(adreno_gpu))</div><div class='add'>+		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);</div><div class='add'>+	else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);</div><div class='ctx'> 	else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);</div><div class='hunk'>@@ -1775,6 +1782,8 @@ static int hw_init(struct msm_gpu *gpu)</div><div class='ctx'> 	if (adreno_is_a730(adreno_gpu) ||</div><div class='ctx'> 	    adreno_is_a740_family(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 &lt;&lt; 30) | 0xcfffff);</div><div class='add'>+	else if (adreno_is_a690(adreno_gpu))</div><div class='add'>+		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 &lt;&lt; 30) | 0x4fffff);</div><div class='ctx'> 	else if (adreno_is_a619(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 &lt;&lt; 30) | 0x3fffff);</div><div class='ctx'> 	else if (adreno_is_a610(adreno_gpu))</div><div class='hunk'>@@ -1782,7 +1791,7 @@ static int hw_init(struct msm_gpu *gpu)</div><div class='ctx'> 	else</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 &lt;&lt; 30) | 0x1fffff);</div><div class='ctx'> </div><div class='del'>-	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);</div><div class='add'>+	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);</div><div class='ctx'> </div><div class='ctx'> 	/* Set weights for bicubic filtering */</div><div class='ctx'> 	if (adreno_is_a650_family(adreno_gpu)) {</div><div class='hunk'>@@ -1808,12 +1817,17 @@ static int hw_init(struct msm_gpu *gpu)</div><div class='ctx'> 	a6xx_set_cp_protect(gpu);</div><div class='ctx'> </div><div class='ctx'> 	if (adreno_is_a660_family(adreno_gpu)) {</div><div class='del'>-		gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);</div><div class='add'>+		if (adreno_is_a690(adreno_gpu))</div><div class='add'>+			gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801);</div><div class='add'>+		else</div><div class='add'>+			gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (adreno_is_a690(adreno_gpu))</div><div class='add'>+		gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90);</div><div class='ctx'> 	/* Set dualQ + disable afull for A660 GPU */</div><div class='del'>-	if (adreno_is_a660(adreno_gpu))</div><div class='add'>+	else if (adreno_is_a660(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);</div><div class='ctx'> 	else if (adreno_is_a7xx(adreno_gpu))</div><div class='ctx'> 		gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG,</div><div class='hunk'>@@ -2908,5 +2922,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)</div><div class='ctx'> 		msm_mmu_set_fault_handler(gpu-&gt;aspace-&gt;mmu, gpu,</div><div class='ctx'> 				a6xx_fault_handler);</div><div class='ctx'> </div><div class='add'>+	a6xx_calc_ubwc_config(adreno_gpu);</div><div class='add'>+</div><div class='ctx'> 	return gpu;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c<br/>index f62ab5257e66..2ce7d7b1690d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/adreno/adreno_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_device.c</a></div><div class='hunk'>@@ -464,7 +464,7 @@ static const struct adreno_info gpulist[] = {</div><div class='ctx'> 			{ 190, 1 },</div><div class='ctx'> 		),</div><div class='ctx'> 	}, {</div><div class='del'>-		.chip_ids = ADRENO_CHIP_IDS(0x06080000),</div><div class='add'>+		.chip_ids = ADRENO_CHIP_IDS(0x06080001),</div><div class='ctx'> 		.family = ADRENO_6XX_GEN2,</div><div class='ctx'> 		.revn = 680,</div><div class='ctx'> 		.fw = {</div><div class='head'>diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c<br/>index 3fe9fd240cc7..074fb498706f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_gpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/adreno/adreno_gpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_gpu.c</a></div><div class='hunk'>@@ -373,6 +373,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		*value = ctx-&gt;aspace-&gt;va_size;</div><div class='ctx'> 		return 0;</div><div class='add'>+	case MSM_PARAM_HIGHEST_BANK_BIT:</div><div class='add'>+		*value = adreno_gpu-&gt;ubwc_config.highest_bank_bit;</div><div class='add'>+		return 0;</div><div class='ctx'> 	default:</div><div class='ctx'> 		DBG("%s: invalid param: %u", gpu-&gt;name, param);</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h<br/>index 80b3f6312116..bc14df96feb0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_gpu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/adreno/adreno_gpu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/adreno/adreno_gpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/adreno/adreno_gpu.h</a></div><div class='hunk'>@@ -165,6 +165,15 @@ struct adreno_gpu {</div><div class='ctx'> 	/* firmware: */</div><div class='ctx'> 	const struct firmware *fw[ADRENO_FW_MAX];</div><div class='ctx'> </div><div class='add'>+	struct {</div><div class='add'>+		u32 rgb565_predicator;</div><div class='add'>+		u32 uavflagprd_inv;</div><div class='add'>+		u32 min_acc_len;</div><div class='add'>+		u32 ubwc_mode;</div><div class='add'>+		u32 highest_bank_bit;</div><div class='add'>+		u32 amsbc;</div><div class='add'>+	} ubwc_config;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Register offsets are different between some GPUs.</div><div class='ctx'> 	 * GPU specific offsets will be exported by GPU specific</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h<br/>new file mode 100644<br/>index 000000000000..eb5dfff2ec4f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h</a></div><div class='hunk'>@@ -0,0 +1,457 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DPU_10_0_SM8650_H</div><div class='add'>+#define _DPU_10_0_SM8650_H</div><div class='add'>+</div><div class='add'>+static const struct dpu_caps sm8650_dpu_caps = {</div><div class='add'>+	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='add'>+	.max_mixer_blendstages = 0xb,</div><div class='add'>+	.has_src_split = true,</div><div class='add'>+	.has_dim_layer = true,</div><div class='add'>+	.has_idle_pc = true,</div><div class='add'>+	.has_3d_merge = true,</div><div class='add'>+	.max_linewidth = 8192,</div><div class='add'>+	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_mdp_cfg sm8650_mdp = {</div><div class='add'>+	.name = "top_0",</div><div class='add'>+	.base = 0, .len = 0x494,</div><div class='add'>+	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),</div><div class='add'>+	.clk_ctrls = {</div><div class='add'>+		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */</div><div class='add'>+static const struct dpu_ctl_cfg sm8650_ctl[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "ctl_0", .id = CTL_0,</div><div class='add'>+		.base = 0x15000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "ctl_1", .id = CTL_1,</div><div class='add'>+		.base = 0x16000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "ctl_2", .id = CTL_2,</div><div class='add'>+		.base = 0x17000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK,</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "ctl_3", .id = CTL_3,</div><div class='add'>+		.base = 0x18000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK,</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "ctl_4", .id = CTL_4,</div><div class='add'>+		.base = 0x19000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK,</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "ctl_5", .id = CTL_5,</div><div class='add'>+		.base = 0x1a000, .len = 0x1000,</div><div class='add'>+		.features = CTL_SM8550_MASK,</div><div class='add'>+		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_cfg sm8650_sspp[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='add'>+		.base = 0x4000, .len = 0x344,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_3,</div><div class='add'>+		.xin_id = 0,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='add'>+		.base = 0x6000, .len = 0x344,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_3,</div><div class='add'>+		.xin_id = 4,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='add'>+		.base = 0x8000, .len = 0x344,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_3,</div><div class='add'>+		.xin_id = 8,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='add'>+		.base = 0xa000, .len = 0x344,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_3,</div><div class='add'>+		.xin_id = 12,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='add'>+		.base = 0x24000, .len = 0x344,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 1,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='add'>+		.base = 0x26000, .len = 0x344,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 5,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='add'>+		.base = 0x28000, .len = 0x344,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 9,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='add'>+		.base = 0x2a000, .len = 0x344,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 13,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_12", .id = SSPP_DMA4,</div><div class='add'>+		.base = 0x2c000, .len = 0x344,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 14,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_13", .id = SSPP_DMA5,</div><div class='add'>+		.base = 0x2e000, .len = 0x344,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 15,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_lm_cfg sm8650_lm[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "lm_0", .id = LM_0,</div><div class='add'>+		.base = 0x44000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_1,</div><div class='add'>+		.pingpong = PINGPONG_0,</div><div class='add'>+		.dspp = DSPP_0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "lm_1", .id = LM_1,</div><div class='add'>+		.base = 0x45000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_0,</div><div class='add'>+		.pingpong = PINGPONG_1,</div><div class='add'>+		.dspp = DSPP_1,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "lm_2", .id = LM_2,</div><div class='add'>+		.base = 0x46000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_3,</div><div class='add'>+		.pingpong = PINGPONG_2,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "lm_3", .id = LM_3,</div><div class='add'>+		.base = 0x47000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_2,</div><div class='add'>+		.pingpong = PINGPONG_3,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "lm_4", .id = LM_4,</div><div class='add'>+		.base = 0x48000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_5,</div><div class='add'>+		.pingpong = PINGPONG_4,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "lm_5", .id = LM_5,</div><div class='add'>+		.base = 0x49000, .len = 0x400,</div><div class='add'>+		.features = MIXER_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_lm_sblk,</div><div class='add'>+		.lm_pair = LM_4,</div><div class='add'>+		.pingpong = PINGPONG_5,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_dspp_cfg sm8650_dspp[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "dspp_0", .id = DSPP_0,</div><div class='add'>+		.base = 0x54000, .len = 0x1800,</div><div class='add'>+		.features = DSPP_SC7180_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_dspp_sblk,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dspp_1", .id = DSPP_1,</div><div class='add'>+		.base = 0x56000, .len = 0x1800,</div><div class='add'>+		.features = DSPP_SC7180_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_dspp_sblk,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dspp_2", .id = DSPP_2,</div><div class='add'>+		.base = 0x58000, .len = 0x1800,</div><div class='add'>+		.features = DSPP_SC7180_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_dspp_sblk,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dspp_3", .id = DSPP_3,</div><div class='add'>+		.base = 0x5a000, .len = 0x1800,</div><div class='add'>+		.features = DSPP_SC7180_MASK,</div><div class='add'>+		.sblk = &amp;sdm845_dspp_sblk,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_pingpong_cfg sm8650_pp[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "pingpong_0", .id = PINGPONG_0,</div><div class='add'>+		.base = 0x69000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_0,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_1", .id = PINGPONG_1,</div><div class='add'>+		.base = 0x6a000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_0,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_2", .id = PINGPONG_2,</div><div class='add'>+		.base = 0x6b000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_1,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_3", .id = PINGPONG_3,</div><div class='add'>+		.base = 0x6c000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_1,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_4", .id = PINGPONG_4,</div><div class='add'>+		.base = 0x6d000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_2,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_5", .id = PINGPONG_5,</div><div class='add'>+		.base = 0x6e000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_2,</div><div class='add'>+		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_6", .id = PINGPONG_6,</div><div class='add'>+		.base = 0x66000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_3,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_7", .id = PINGPONG_7,</div><div class='add'>+		.base = 0x66400, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_3,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_8", .id = PINGPONG_8,</div><div class='add'>+		.base = 0x7e000, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_4,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "pingpong_9", .id = PINGPONG_9,</div><div class='add'>+		.base = 0x7e400, .len = 0,</div><div class='add'>+		.features = BIT(DPU_PINGPONG_DITHER),</div><div class='add'>+		.sblk = &amp;sc7280_pp_sblk,</div><div class='add'>+		.merge_3d = MERGE_3D_4,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_merge_3d_cfg sm8650_merge_3d[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "merge_3d_0", .id = MERGE_3D_0,</div><div class='add'>+		.base = 0x4e000, .len = 0x8,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "merge_3d_1", .id = MERGE_3D_1,</div><div class='add'>+		.base = 0x4f000, .len = 0x8,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "merge_3d_2", .id = MERGE_3D_2,</div><div class='add'>+		.base = 0x50000, .len = 0x8,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "merge_3d_3", .id = MERGE_3D_3,</div><div class='add'>+		.base = 0x66700, .len = 0x8,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "merge_3d_4", .id = MERGE_3D_4,</div><div class='add'>+		.base = 0x7e700, .len = 0x8,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * NOTE: Each display compression engine (DCE) contains dual hard</div><div class='add'>+ * slice DSC encoders so both share same base address but with</div><div class='add'>+ * its own different sub block address.</div><div class='add'>+ */</div><div class='add'>+static const struct dpu_dsc_cfg sm8650_dsc[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "dce_0_0", .id = DSC_0,</div><div class='add'>+		.base = 0x80000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),</div><div class='add'>+		.sblk = &amp;dsc_sblk_0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dce_0_1", .id = DSC_1,</div><div class='add'>+		.base = 0x80000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),</div><div class='add'>+		.sblk = &amp;dsc_sblk_1,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dce_1_0", .id = DSC_2,</div><div class='add'>+		.base = 0x81000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),</div><div class='add'>+		.sblk = &amp;dsc_sblk_0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dce_1_1", .id = DSC_3,</div><div class='add'>+		.base = 0x81000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),</div><div class='add'>+		.sblk = &amp;dsc_sblk_1,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dce_2_0", .id = DSC_4,</div><div class='add'>+		.base = 0x82000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2),</div><div class='add'>+		.sblk = &amp;dsc_sblk_0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dce_2_1", .id = DSC_5,</div><div class='add'>+		.base = 0x82000, .len = 0x6,</div><div class='add'>+		.features = BIT(DPU_DSC_HW_REV_1_2),</div><div class='add'>+		.sblk = &amp;dsc_sblk_1,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_wb_cfg sm8650_wb[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "wb_2", .id = WB_2,</div><div class='add'>+		.base = 0x65000, .len = 0x2c8,</div><div class='add'>+		.features = WB_SM8250_MASK,</div><div class='add'>+		.format_list = wb2_formats_rgb,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),</div><div class='add'>+		.xin_id = 6,</div><div class='add'>+		.vbif_idx = VBIF_RT,</div><div class='add'>+		.maxlinewidth = 4096,</div><div class='add'>+		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_intf_cfg sm8650_intf[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "intf_0", .id = INTF_0,</div><div class='add'>+		.base = 0x34000, .len = 0x280,</div><div class='add'>+		.features = INTF_SC7280_MASK,</div><div class='add'>+		.type = INTF_DP,</div><div class='add'>+		.controller_id = MSM_DP_CONTROLLER_0,</div><div class='add'>+		.prog_fetch_lines_worst_case = 24,</div><div class='add'>+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),</div><div class='add'>+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "intf_1", .id = INTF_1,</div><div class='add'>+		.base = 0x35000, .len = 0x300,</div><div class='add'>+		.features = INTF_SC7280_MASK,</div><div class='add'>+		.type = INTF_DSI,</div><div class='add'>+		.controller_id = MSM_DSI_CONTROLLER_0,</div><div class='add'>+		.prog_fetch_lines_worst_case = 24,</div><div class='add'>+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),</div><div class='add'>+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),</div><div class='add'>+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "intf_2", .id = INTF_2,</div><div class='add'>+		.base = 0x36000, .len = 0x300,</div><div class='add'>+		.features = INTF_SC7280_MASK,</div><div class='add'>+		.type = INTF_DSI,</div><div class='add'>+		.controller_id = MSM_DSI_CONTROLLER_1,</div><div class='add'>+		.prog_fetch_lines_worst_case = 24,</div><div class='add'>+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),</div><div class='add'>+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),</div><div class='add'>+		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),</div><div class='add'>+	}, {</div><div class='add'>+		.name = "intf_3", .id = INTF_3,</div><div class='add'>+		.base = 0x37000, .len = 0x280,</div><div class='add'>+		.features = INTF_SC7280_MASK,</div><div class='add'>+		.type = INTF_DP,</div><div class='add'>+		.controller_id = MSM_DP_CONTROLLER_1,</div><div class='add'>+		.prog_fetch_lines_worst_case = 24,</div><div class='add'>+		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),</div><div class='add'>+		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_perf_cfg sm8650_perf_data = {</div><div class='add'>+	.max_bw_low = 17000000,</div><div class='add'>+	.max_bw_high = 27000000,</div><div class='add'>+	.min_core_ib = 2500000,</div><div class='add'>+	.min_llcc_ib = 0,</div><div class='add'>+	.min_dram_ib = 800000,</div><div class='add'>+	.min_prefill_lines = 35,</div><div class='add'>+	/* FIXME: lut tables */</div><div class='add'>+	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},</div><div class='add'>+	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},</div><div class='add'>+	.qos_lut_tbl = {</div><div class='add'>+		{.nentry = ARRAY_SIZE(sc7180_qos_linear),</div><div class='add'>+		.entries = sc7180_qos_linear</div><div class='add'>+		},</div><div class='add'>+		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),</div><div class='add'>+		.entries = sc7180_qos_macrotile</div><div class='add'>+		},</div><div class='add'>+		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),</div><div class='add'>+		.entries = sc7180_qos_nrt</div><div class='add'>+		},</div><div class='add'>+		/* TODO: macrotile-qseed is different from macrotile */</div><div class='add'>+	},</div><div class='add'>+	.cdp_cfg = {</div><div class='add'>+		{.rd_enable = 1, .wr_enable = 1},</div><div class='add'>+		{.rd_enable = 1, .wr_enable = 0}</div><div class='add'>+	},</div><div class='add'>+	.clk_inefficiency_factor = 105,</div><div class='add'>+	.bw_inefficiency_factor = 120,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_mdss_version sm8650_mdss_ver = {</div><div class='add'>+	.core_major_ver = 10,</div><div class='add'>+	.core_minor_ver = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct dpu_mdss_cfg dpu_sm8650_cfg = {</div><div class='add'>+	.mdss_ver = &amp;sm8650_mdss_ver,</div><div class='add'>+	.caps = &amp;sm8650_dpu_caps,</div><div class='add'>+	.mdp = &amp;sm8650_mdp,</div><div class='add'>+	.ctl_count = ARRAY_SIZE(sm8650_ctl),</div><div class='add'>+	.ctl = sm8650_ctl,</div><div class='add'>+	.sspp_count = ARRAY_SIZE(sm8650_sspp),</div><div class='add'>+	.sspp = sm8650_sspp,</div><div class='add'>+	.mixer_count = ARRAY_SIZE(sm8650_lm),</div><div class='add'>+	.mixer = sm8650_lm,</div><div class='add'>+	.dspp_count = ARRAY_SIZE(sm8650_dspp),</div><div class='add'>+	.dspp = sm8650_dspp,</div><div class='add'>+	.pingpong_count = ARRAY_SIZE(sm8650_pp),</div><div class='add'>+	.pingpong = sm8650_pp,</div><div class='add'>+	.dsc_count = ARRAY_SIZE(sm8650_dsc),</div><div class='add'>+	.dsc = sm8650_dsc,</div><div class='add'>+	.merge_3d_count = ARRAY_SIZE(sm8650_merge_3d),</div><div class='add'>+	.merge_3d = sm8650_merge_3d,</div><div class='add'>+	.wb_count = ARRAY_SIZE(sm8650_wb),</div><div class='add'>+	.wb = sm8650_wb,</div><div class='add'>+	.intf_count = ARRAY_SIZE(sm8650_intf),</div><div class='add'>+	.intf = sm8650_intf,</div><div class='add'>+	.vbif_count = ARRAY_SIZE(sm8650_vbif),</div><div class='add'>+	.vbif = sm8650_vbif,</div><div class='add'>+	.perf = &amp;sm8650_perf_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h<br/>index aa1867943c9f..1d3e9666c741 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps msm8998_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x7,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED3,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -70,7 +69,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1ac,</div><div class='ctx'> 		.features = VIG_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;msm8998_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_2,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -78,7 +77,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1ac,</div><div class='ctx'> 		.features = VIG_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;msm8998_vig_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_2,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='hunk'>@@ -86,7 +85,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1ac,</div><div class='ctx'> 		.features = VIG_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;msm8998_vig_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_2,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='hunk'>@@ -94,7 +93,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1ac,</div><div class='ctx'> 		.features = VIG_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;msm8998_vig_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_2,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -102,7 +101,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1ac,</div><div class='ctx'> 		.features = DMA_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -110,7 +109,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1ac,</div><div class='ctx'> 		.features = DMA_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -118,7 +117,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1ac,</div><div class='ctx'> 		.features = DMA_CURSOR_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -126,7 +125,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1ac,</div><div class='ctx'> 		.features = DMA_CURSOR_MSM8998_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h<br/>index 38ac0c1a134b..7a23389a5732 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sdm845_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED3,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -68,7 +67,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1c8,</div><div class='ctx'> 		.features = VIG_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -76,7 +75,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1c8,</div><div class='ctx'> 		.features = VIG_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='hunk'>@@ -84,7 +83,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1c8,</div><div class='ctx'> 		.features = VIG_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='hunk'>@@ -92,7 +91,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1c8,</div><div class='ctx'> 		.features = VIG_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -100,7 +99,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1c8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -108,7 +107,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1c8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -116,7 +115,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1c8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -124,7 +123,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1c8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h<br/>new file mode 100644<br/>index 000000000000..cbbdaebe357e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Richard Acayan. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DPU_4_1_SDM670_H</div><div class='add'>+#define _DPU_4_1_SDM670_H</div><div class='add'>+</div><div class='add'>+static const struct dpu_mdp_cfg sdm670_mdp = {</div><div class='add'>+	.name = "top_0",</div><div class='add'>+	.base = 0x0, .len = 0x45c,</div><div class='add'>+	.features = BIT(DPU_MDP_AUDIO_SELECT),</div><div class='add'>+	.clk_ctrls = {</div><div class='add'>+		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },</div><div class='add'>+		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },</div><div class='add'>+		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },</div><div class='add'>+		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },</div><div class='add'>+		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_cfg sdm670_sspp[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='add'>+		.base = 0x4000, .len = 0x1c8,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='add'>+		.xin_id = 0,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='add'>+		.base = 0x6000, .len = 0x1c8,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_3,</div><div class='add'>+		.xin_id = 4,</div><div class='add'>+		.type = SSPP_TYPE_VIG,</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='add'>+		.base = 0x24000, .len = 0x1c8,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 1,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='add'>+		.base = 0x26000, .len = 0x1c8,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 5,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='add'>+		.base = 0x28000, .len = 0x1c8,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='add'>+		.xin_id = 9,</div><div class='add'>+		.type = SSPP_TYPE_DMA,</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_dsc_cfg sdm670_dsc[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "dsc_0", .id = DSC_0,</div><div class='add'>+		.base = 0x80000, .len = 0x140,</div><div class='add'>+	}, {</div><div class='add'>+		.name = "dsc_1", .id = DSC_1,</div><div class='add'>+		.base = 0x80400, .len = 0x140,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dpu_mdss_version sdm670_mdss_ver = {</div><div class='add'>+	.core_major_ver = 4,</div><div class='add'>+	.core_minor_ver = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct dpu_mdss_cfg dpu_sdm670_cfg = {</div><div class='add'>+	.mdss_ver = &amp;sdm670_mdss_ver,</div><div class='add'>+	.caps = &amp;sdm845_dpu_caps,</div><div class='add'>+	.mdp = &amp;sdm670_mdp,</div><div class='add'>+	.ctl_count = ARRAY_SIZE(sdm845_ctl),</div><div class='add'>+	.ctl = sdm845_ctl,</div><div class='add'>+	.sspp_count = ARRAY_SIZE(sdm670_sspp),</div><div class='add'>+	.sspp = sdm670_sspp,</div><div class='add'>+	.mixer_count = ARRAY_SIZE(sdm845_lm),</div><div class='add'>+	.mixer = sdm845_lm,</div><div class='add'>+	.pingpong_count = ARRAY_SIZE(sdm845_pp),</div><div class='add'>+	.pingpong = sdm845_pp,</div><div class='add'>+	.dsc_count = ARRAY_SIZE(sdm670_dsc),</div><div class='add'>+	.dsc = sdm670_dsc,</div><div class='add'>+	.intf_count = ARRAY_SIZE(sdm845_intf),</div><div class='add'>+	.intf = sdm845_intf,</div><div class='add'>+	.vbif_count = ARRAY_SIZE(sdm845_vbif),</div><div class='add'>+	.vbif = sdm845_vbif,</div><div class='add'>+	.perf = &amp;sdm845_perf_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h<br/>index 9392ad2b4d3f..145f3d5953a3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm8150_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED3,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -77,7 +76,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -85,7 +84,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='hunk'>@@ -93,7 +92,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='hunk'>@@ -101,7 +100,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -109,7 +108,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -117,7 +116,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -125,7 +124,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -133,7 +132,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h<br/>index e07f4c8c25b9..9e3bec8bc121 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sc8180x_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED3,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -76,7 +75,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -84,7 +83,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='hunk'>@@ -92,7 +91,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='hunk'>@@ -100,7 +99,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1f0,</div><div class='ctx'> 		.features = VIG_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_vig_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_1_4,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -108,7 +107,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -116,7 +115,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -124,7 +123,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -132,7 +131,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='hunk'>@@ -367,6 +366,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {</div><div class='ctx'> 	.min_llcc_ib = 800000,</div><div class='ctx'> 	.min_dram_ib = 800000,</div><div class='ctx'> 	.danger_lut_tbl = {0xf, 0xffff, 0x0},</div><div class='add'>+	.safe_lut_tbl = {0xfff0, 0xf000, 0xffff},</div><div class='ctx'> 	.qos_lut_tbl = {</div><div class='ctx'> 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),</div><div class='ctx'> 		.entries = sc7180_qos_linear</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h<br/>index cec7af6667dc..76b2ec0d2489 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h</a></div><div class='hunk'>@@ -68,8 +68,8 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f0,</div><div class='del'>-		.features = VIG_SM6125_MASK,</div><div class='del'>-		.sblk = &amp;sm6125_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_2_4,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f0,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h<br/>index 94278a3e3483..a57d50b1f028 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm8250_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -32,7 +31,7 @@ static const struct dpu_mdp_cfg sm8250_mdp = {</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },</div><div class='del'>-		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },</div><div class='add'>+		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -75,32 +74,32 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_1,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_2,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_3,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -108,7 +107,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -116,7 +115,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -124,7 +123,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -132,7 +131,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='hunk'>@@ -337,8 +336,8 @@ static const struct dpu_wb_cfg sm8250_wb[] = {</div><div class='ctx'> 		.name = "wb_2", .id = WB_2,</div><div class='ctx'> 		.base = 0x65000, .len = 0x2c8,</div><div class='ctx'> 		.features = WB_SM8250_MASK,</div><div class='del'>-		.format_list = wb2_formats,</div><div class='del'>-		.num_formats = ARRAY_SIZE(wb2_formats),</div><div class='add'>+		.format_list = wb2_formats_rgb_yuv,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_WB2,</div><div class='ctx'> 		.xin_id = 6,</div><div class='ctx'> 		.vbif_idx = VBIF_RT,</div><div class='hunk'>@@ -385,6 +384,7 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {</div><div class='ctx'> 	.mdss_ver = &amp;sm8250_mdss_ver,</div><div class='ctx'> 	.caps = &amp;sm8250_dpu_caps,</div><div class='ctx'> 	.mdp = &amp;sm8250_mdp,</div><div class='add'>+	.cdm = &amp;sc7280_cdm,</div><div class='ctx'> 	.ctl_count = ARRAY_SIZE(sm8250_ctl),</div><div class='ctx'> 	.ctl = sm8250_ctl,</div><div class='ctx'> 	.sspp_count = ARRAY_SIZE(sm8250_sspp),</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h<br/>index c0d88ddccb28..7382ebb6e5b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sc7180_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x9,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='ctx'> 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='hunk'>@@ -25,7 +24,7 @@ static const struct dpu_mdp_cfg sc7180_mdp = {</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },</div><div class='del'>-		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },</div><div class='add'>+		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -52,8 +51,8 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sc7180_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -61,7 +60,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -69,7 +68,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -77,7 +76,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -158,8 +157,8 @@ static const struct dpu_wb_cfg sc7180_wb[] = {</div><div class='ctx'> 		.name = "wb_2", .id = WB_2,</div><div class='ctx'> 		.base = 0x65000, .len = 0x2c8,</div><div class='ctx'> 		.features = WB_SM8250_MASK,</div><div class='del'>-		.format_list = wb2_formats,</div><div class='del'>-		.num_formats = ARRAY_SIZE(wb2_formats),</div><div class='add'>+		.format_list = wb2_formats_rgb,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_WB2,</div><div class='ctx'> 		.xin_id = 6,</div><div class='ctx'> 		.vbif_idx = VBIF_RT,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h<br/>index 57ce14c18def..43f64a005f5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm6115_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x4,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='ctx'> 	.max_linewidth = 2160,</div><div class='hunk'>@@ -39,8 +38,8 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm6115_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -48,7 +47,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h<br/>index 62db84bd15f2..e17a30be7525 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h</a></div><div class='hunk'>@@ -11,7 +11,6 @@</div><div class='ctx'> static const struct dpu_caps sm6350_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x7,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -59,8 +58,8 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sc7180_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -68,7 +67,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -76,7 +75,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -84,7 +83,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h<br/>index fb36fba5171c..3cbb2fe8aba2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h</a></div><div class='hunk'>@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='ctx'> 		.features = VIG_QCM2290_MASK,</div><div class='del'>-		.sblk = &amp;qcm2290_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_noscale,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;qcm2290_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h<br/>index 5a3aad364c78..a06c8634d2d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h</a></div><div class='hunk'>@@ -11,7 +11,6 @@</div><div class='ctx'> static const struct dpu_caps sm6375_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x4,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='ctx'> 	.max_linewidth = 2160,</div><div class='hunk'>@@ -40,8 +39,8 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm6115_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -49,7 +48,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h<br/>index 1709ba57f384..aced16e350da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm8350_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -31,6 +30,7 @@ static const struct dpu_mdp_cfg sm8350_mdp = {</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },</div><div class='add'>+		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },</div><div class='ctx'> 		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -74,64 +74,64 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_1,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_2,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x1f8,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_3,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='del'>-		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f8,</div><div class='del'>-		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f8,</div><div class='del'>-		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x1f8,</div><div class='del'>-		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='hunk'>@@ -298,6 +298,21 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dpu_wb_cfg sm8350_wb[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "wb_2", .id = WB_2,</div><div class='add'>+		.base = 0x65000, .len = 0x2c8,</div><div class='add'>+		.features = WB_SM8250_MASK,</div><div class='add'>+		.format_list = wb2_formats_rgb,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_WB2,</div><div class='add'>+		.xin_id = 6,</div><div class='add'>+		.vbif_idx = VBIF_RT,</div><div class='add'>+		.maxlinewidth = 4096,</div><div class='add'>+		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dpu_intf_cfg sm8350_intf[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "intf_0", .id = INTF_0,</div><div class='hunk'>@@ -393,6 +408,8 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {</div><div class='ctx'> 	.dsc = sm8350_dsc,</div><div class='ctx'> 	.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),</div><div class='ctx'> 	.merge_3d = sm8350_merge_3d,</div><div class='add'>+	.wb_count = ARRAY_SIZE(sm8350_wb),</div><div class='add'>+	.wb = sm8350_wb,</div><div class='ctx'> 	.intf_count = ARRAY_SIZE(sm8350_intf),</div><div class='ctx'> 	.intf = sm8350_intf,</div><div class='ctx'> 	.vbif_count = ARRAY_SIZE(sdm845_vbif),</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h<br/>index 15942fa5a8e0..2f153e0b5c6a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sc7280_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0x7,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='ctx'> 	.max_linewidth = 2400,</div><div class='hunk'>@@ -25,7 +24,7 @@ static const struct dpu_mdp_cfg sc7280_mdp = {</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },</div><div class='del'>-		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },</div><div class='add'>+		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -58,7 +57,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x1f8,</div><div class='ctx'> 		.features = VIG_SC7280_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sc7280_vig_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0_rot_v2,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='hunk'>@@ -66,7 +65,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -74,7 +73,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -82,7 +81,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x1f8,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -170,8 +169,8 @@ static const struct dpu_wb_cfg sc7280_wb[] = {</div><div class='ctx'> 		.name = "wb_2", .id = WB_2,</div><div class='ctx'> 		.base = 0x65000, .len = 0x2c8,</div><div class='ctx'> 		.features = WB_SM8250_MASK,</div><div class='del'>-		.format_list = wb2_formats,</div><div class='del'>-		.num_formats = ARRAY_SIZE(wb2_formats),</div><div class='add'>+		.format_list = wb2_formats_rgb_yuv,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_WB2,</div><div class='ctx'> 		.xin_id = 6,</div><div class='ctx'> 		.vbif_idx = VBIF_RT,</div><div class='hunk'>@@ -249,6 +248,7 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {</div><div class='ctx'> 	.mdss_ver = &amp;sc7280_mdss_ver,</div><div class='ctx'> 	.caps = &amp;sc7280_dpu_caps,</div><div class='ctx'> 	.mdp = &amp;sc7280_mdp,</div><div class='add'>+	.cdm = &amp;sc7280_cdm,</div><div class='ctx'> 	.ctl_count = ARRAY_SIZE(sc7280_ctl),</div><div class='ctx'> 	.ctl = sc7280_ctl,</div><div class='ctx'> 	.sspp_count = ARRAY_SIZE(sc7280_sspp),</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h<br/>index 4c0528794e7a..0d143e390eca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sc8280xp_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 11,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -75,32 +74,32 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x2ac,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x2ac,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_1,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x2ac,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_2,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x2ac,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_3,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_0,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='hunk'>@@ -108,7 +107,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x2ac,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='hunk'>@@ -116,7 +115,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x2ac,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='hunk'>@@ -124,7 +123,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x2ac,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='hunk'>@@ -132,7 +131,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x2ac,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h<br/>index 7742f52be859..a1779c5597ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm8450_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -32,6 +31,7 @@ static const struct dpu_mdp_cfg sm8450_mdp = {</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },</div><div class='ctx'> 		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },</div><div class='add'>+		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },</div><div class='ctx'> 		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -75,64 +75,64 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x32c,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_1,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x32c,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_1,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_1,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x32c,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_2,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_1,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x32c,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8250_vig_sblk_3,</div><div class='add'>+		.features = VIG_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_1,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_VIG3,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x32c,</div><div class='del'>-		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA0,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x32c,</div><div class='del'>-		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.features = DMA_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA1,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x32c,</div><div class='del'>-		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA2,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x32c,</div><div class='del'>-		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.features = DMA_CURSOR_SDM845_MASK_SDMA,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 		.clk_ctrl = DPU_CLK_CTRL_DMA3,</div><div class='hunk'>@@ -316,6 +316,21 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dpu_wb_cfg sm8450_wb[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "wb_2", .id = WB_2,</div><div class='add'>+		.base = 0x65000, .len = 0x2c8,</div><div class='add'>+		.features = WB_SM8250_MASK,</div><div class='add'>+		.format_list = wb2_formats_rgb,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),</div><div class='add'>+		.clk_ctrl = DPU_CLK_CTRL_WB2,</div><div class='add'>+		.xin_id = 6,</div><div class='add'>+		.vbif_idx = VBIF_RT,</div><div class='add'>+		.maxlinewidth = 4096,</div><div class='add'>+		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct dpu_intf_cfg sm8450_intf[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "intf_0", .id = INTF_0,</div><div class='hunk'>@@ -411,6 +426,8 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {</div><div class='ctx'> 	.dsc = sm8450_dsc,</div><div class='ctx'> 	.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),</div><div class='ctx'> 	.merge_3d = sm8450_merge_3d,</div><div class='add'>+	.wb_count = ARRAY_SIZE(sm8450_wb),</div><div class='add'>+	.wb = sm8450_wb,</div><div class='ctx'> 	.intf_count = ARRAY_SIZE(sm8450_intf),</div><div class='ctx'> 	.intf = sm8450_intf,</div><div class='ctx'> 	.vbif_count = ARRAY_SIZE(sdm845_vbif),</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h<br/>index 69b80af6566a..ad48defa154f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h</a></div><div class='hunk'>@@ -10,7 +10,6 @@</div><div class='ctx'> static const struct dpu_caps sm8550_dpu_caps = {</div><div class='ctx'> 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,</div><div class='ctx'> 	.max_mixer_blendstages = 0xb,</div><div class='del'>-	.qseed_type = DPU_SSPP_SCALER_QSEED4,</div><div class='ctx'> 	.has_src_split = true,</div><div class='ctx'> 	.has_dim_layer = true,</div><div class='ctx'> 	.has_idle_pc = true,</div><div class='hunk'>@@ -67,71 +66,71 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "sspp_0", .id = SSPP_VIG0,</div><div class='ctx'> 		.base = 0x4000, .len = 0x344,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_vig_sblk_0,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_2,</div><div class='ctx'> 		.xin_id = 0,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_1", .id = SSPP_VIG1,</div><div class='ctx'> 		.base = 0x6000, .len = 0x344,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_vig_sblk_1,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_2,</div><div class='ctx'> 		.xin_id = 4,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_2", .id = SSPP_VIG2,</div><div class='ctx'> 		.base = 0x8000, .len = 0x344,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_vig_sblk_2,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_2,</div><div class='ctx'> 		.xin_id = 8,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_3", .id = SSPP_VIG3,</div><div class='ctx'> 		.base = 0xa000, .len = 0x344,</div><div class='del'>-		.features = VIG_SC7180_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_vig_sblk_3,</div><div class='add'>+		.features = VIG_SDM845_MASK,</div><div class='add'>+		.sblk = &amp;dpu_vig_sblk_qseed3_3_2,</div><div class='ctx'> 		.xin_id = 12,</div><div class='ctx'> 		.type = SSPP_TYPE_VIG,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_8", .id = SSPP_DMA0,</div><div class='ctx'> 		.base = 0x24000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_0,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 1,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_9", .id = SSPP_DMA1,</div><div class='ctx'> 		.base = 0x26000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_1,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 5,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_10", .id = SSPP_DMA2,</div><div class='ctx'> 		.base = 0x28000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_2,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 9,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_11", .id = SSPP_DMA3,</div><div class='ctx'> 		.base = 0x2a000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sdm845_dma_sblk_3,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 13,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_12", .id = SSPP_DMA4,</div><div class='ctx'> 		.base = 0x2c000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_dma_sblk_4,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 14,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.name = "sspp_13", .id = SSPP_DMA5,</div><div class='ctx'> 		.base = 0x2e000, .len = 0x344,</div><div class='ctx'> 		.features = DMA_CURSOR_SDM845_MASK,</div><div class='del'>-		.sblk = &amp;sm8550_dma_sblk_5,</div><div class='add'>+		.sblk = &amp;dpu_dma_sblk,</div><div class='ctx'> 		.xin_id = 15,</div><div class='ctx'> 		.type = SSPP_TYPE_DMA,</div><div class='ctx'> 	},</div><div class='hunk'>@@ -316,8 +315,8 @@ static const struct dpu_wb_cfg sm8550_wb[] = {</div><div class='ctx'> 		.name = "wb_2", .id = WB_2,</div><div class='ctx'> 		.base = 0x65000, .len = 0x2c8,</div><div class='ctx'> 		.features = WB_SM8250_MASK,</div><div class='del'>-		.format_list = wb2_formats,</div><div class='del'>-		.num_formats = ARRAY_SIZE(wb2_formats),</div><div class='add'>+		.format_list = wb2_formats_rgb,</div><div class='add'>+		.num_formats = ARRAY_SIZE(wb2_formats_rgb),</div><div class='ctx'> 		.xin_id = 6,</div><div class='ctx'> 		.vbif_idx = VBIF_RT,</div><div class='ctx'> 		.maxlinewidth = 4096,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c<br/>index 3c475f8042b0..88c2e51ab166 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.</div><div class='ctx'>  * Copyright (C) 2013 Red Hat</div><div class='ctx'>  * Author: Rob Clark &lt;robdclark@gmail.com&gt;</div><div class='hunk'>@@ -51,17 +51,6 @@ static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)</div><div class='ctx'> 	return to_dpu_kms(priv-&gt;kms);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_crtc_destroy(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);</div><div class='del'>-</div><div class='del'>-	if (!crtc)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	drm_crtc_cleanup(crtc);</div><div class='del'>-	kfree(dpu_crtc);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = crtc-&gt;dev;</div><div class='hunk'>@@ -125,7 +114,7 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* Calculate MISR over 1 frame */</div><div class='del'>-		m-&gt;hw_lm-&gt;ops.setup_misr(m-&gt;hw_lm, true, 1);</div><div class='add'>+		m-&gt;hw_lm-&gt;ops.setup_misr(m-&gt;hw_lm);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1435,7 +1424,6 @@ static int dpu_crtc_late_register(struct drm_crtc *crtc)</div><div class='ctx'> </div><div class='ctx'> static const struct drm_crtc_funcs dpu_crtc_funcs = {</div><div class='ctx'> 	.set_config = drm_atomic_helper_set_config,</div><div class='del'>-	.destroy = dpu_crtc_destroy,</div><div class='ctx'> 	.page_flip = drm_atomic_helper_page_flip,</div><div class='ctx'> 	.reset = dpu_crtc_reset,</div><div class='ctx'> 	.atomic_duplicate_state = dpu_crtc_duplicate_state,</div><div class='hunk'>@@ -1469,9 +1457,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,</div><div class='ctx'> 	struct dpu_crtc *dpu_crtc;</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> </div><div class='del'>-	dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);</div><div class='del'>-	if (!dpu_crtc)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	dpu_crtc = drmm_crtc_alloc_with_planes(dev, struct dpu_crtc, base,</div><div class='add'>+					       plane, cursor,</div><div class='add'>+					       &amp;dpu_crtc_funcs,</div><div class='add'>+					       NULL);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(dpu_crtc))</div><div class='add'>+		return ERR_CAST(dpu_crtc);</div><div class='ctx'> </div><div class='ctx'> 	crtc = &amp;dpu_crtc-&gt;base;</div><div class='ctx'> 	crtc-&gt;dev = dev;</div><div class='hunk'>@@ -1491,9 +1483,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,</div><div class='ctx'> 				dpu_crtc_frame_event_work);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_crtc_init_with_planes(dev, crtc, plane, cursor, &amp;dpu_crtc_funcs,</div><div class='del'>-				NULL);</div><div class='del'>-</div><div class='ctx'> 	drm_crtc_helper_add(crtc, &amp;dpu_crtc_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	if (dpu_kms-&gt;catalog-&gt;dspp_count)</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c<br/>index 1cf7ff6caff4..83380bc92a00 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (C) 2013 Red Hat</div><div class='ctx'>  * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  *</div><div class='ctx'>  * Author: Rob Clark &lt;robdclark@gmail.com&gt;</div><div class='ctx'>  */</div><div class='hunk'>@@ -16,6 +16,7 @@</div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_file.h&gt;</div><div class='ctx'> #include &lt;drm/drm_probe_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_framebuffer.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "msm_drv.h"</div><div class='ctx'> #include "dpu_kms.h"</div><div class='hunk'>@@ -26,6 +27,7 @@</div><div class='ctx'> #include "dpu_hw_dspp.h"</div><div class='ctx'> #include "dpu_hw_dsc.h"</div><div class='ctx'> #include "dpu_hw_merge3d.h"</div><div class='add'>+#include "dpu_hw_cdm.h"</div><div class='ctx'> #include "dpu_formats.h"</div><div class='ctx'> #include "dpu_encoder_phys.h"</div><div class='ctx'> #include "dpu_crtc.h"</div><div class='hunk'>@@ -39,6 +41,9 @@</div><div class='ctx'> #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\</div><div class='ctx'> 		(e) ? (e)-&gt;base.base.id : -1, ##__VA_ARGS__)</div><div class='ctx'> </div><div class='add'>+#define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\</div><div class='add'>+		(e) ? (e)-&gt;base.base.id : -1, ##__VA_ARGS__)</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Two to anticipate panels that can do cmd/vid dynamic switching</div><div class='ctx'>  * plan is to create all possible physical encoder types, and switch between</div><div class='hunk'>@@ -151,6 +156,8 @@ enum dpu_enc_rc_states {</div><div class='ctx'>  * @crtc_frame_event_cb:	callback handler for frame event</div><div class='ctx'>  * @crtc_frame_event_cb_data:	callback handler private data</div><div class='ctx'>  * @frame_done_timeout_ms:	frame done timeout in ms</div><div class='add'>+ * @frame_done_timeout_cnt:	atomic counter tracking the number of frame</div><div class='add'>+ * 				done timeouts</div><div class='ctx'>  * @frame_done_timer:		watchdog timer for frame done event</div><div class='ctx'>  * @disp_info:			local copy of msm_display_info struct</div><div class='ctx'>  * @idle_pc_supported:		indicate if idle power collaps is supported</div><div class='hunk'>@@ -184,13 +191,13 @@ struct dpu_encoder_virt {</div><div class='ctx'> 	struct drm_crtc *crtc;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> </div><div class='del'>-	struct dentry *debugfs_root;</div><div class='ctx'> 	struct mutex enc_lock;</div><div class='ctx'> 	DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);</div><div class='ctx'> 	void (*crtc_frame_event_cb)(void *, u32 event);</div><div class='ctx'> 	void *crtc_frame_event_cb_data;</div><div class='ctx'> </div><div class='ctx'> 	atomic_t frame_done_timeout_ms;</div><div class='add'>+	atomic_t frame_done_timeout_cnt;</div><div class='ctx'> 	struct timer_list frame_done_timer;</div><div class='ctx'> </div><div class='ctx'> 	struct msm_display_info disp_info;</div><div class='hunk'>@@ -255,7 +262,7 @@ void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)</div><div class='ctx'> 		if (!phys-&gt;hw_intf || !phys-&gt;hw_intf-&gt;ops.setup_misr)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		phys-&gt;hw_intf-&gt;ops.setup_misr(phys-&gt;hw_intf, true, 1);</div><div class='add'>+		phys-&gt;hw_intf-&gt;ops.setup_misr(phys-&gt;hw_intf);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -439,41 +446,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)</div><div class='ctx'> 	return linecount;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_encoder_destroy(struct drm_encoder *drm_enc)</div><div class='del'>-{</div><div class='del'>-	struct dpu_encoder_virt *dpu_enc = NULL;</div><div class='del'>-	int i = 0;</div><div class='del'>-</div><div class='del'>-	if (!drm_enc) {</div><div class='del'>-		DPU_ERROR("invalid encoder\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dpu_enc = to_dpu_encoder_virt(drm_enc);</div><div class='del'>-	DPU_DEBUG_ENC(dpu_enc, "\n");</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;dpu_enc-&gt;enc_lock);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; dpu_enc-&gt;num_phys_encs; i++) {</div><div class='del'>-		struct dpu_encoder_phys *phys = dpu_enc-&gt;phys_encs[i];</div><div class='del'>-</div><div class='del'>-		if (phys-&gt;ops.destroy) {</div><div class='del'>-			phys-&gt;ops.destroy(phys);</div><div class='del'>-			--dpu_enc-&gt;num_phys_encs;</div><div class='del'>-			dpu_enc-&gt;phys_encs[i] = NULL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (dpu_enc-&gt;num_phys_encs)</div><div class='del'>-		DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",</div><div class='del'>-				dpu_enc-&gt;num_phys_encs);</div><div class='del'>-	dpu_enc-&gt;num_phys_encs = 0;</div><div class='del'>-	mutex_unlock(&amp;dpu_enc-&gt;enc_lock);</div><div class='del'>-</div><div class='del'>-	drm_encoder_cleanup(drm_enc);</div><div class='del'>-	mutex_destroy(&amp;dpu_enc-&gt;enc_lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dpu_encoder_helper_split_config(</div><div class='ctx'> 		struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> 		enum dpu_intf interface)</div><div class='hunk'>@@ -614,6 +586,7 @@ static int dpu_encoder_virt_atomic_check(</div><div class='ctx'> 	struct drm_display_mode *adj_mode;</div><div class='ctx'> 	struct msm_display_topology topology;</div><div class='ctx'> 	struct dpu_global_state *global_state;</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='ctx'> 	struct drm_dsc_config *dsc;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -655,6 +628,22 @@ static int dpu_encoder_virt_atomic_check(</div><div class='ctx'> 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * Use CDM only for writeback at the moment as other interfaces cannot handle it.</div><div class='add'>+	 * if writeback itself cannot handle cdm for some reason it will fail in its atomic_check()</div><div class='add'>+	 * earlier.</div><div class='add'>+	 */</div><div class='add'>+	if (dpu_enc-&gt;disp_info.intf_type == INTF_WB &amp;&amp; conn_state-&gt;writeback_job) {</div><div class='add'>+		fb = conn_state-&gt;writeback_job-&gt;fb;</div><div class='add'>+</div><div class='add'>+		if (fb &amp;&amp; DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))</div><div class='add'>+			topology.needs_cdm = true;</div><div class='add'>+		if (topology.needs_cdm &amp;&amp; !dpu_enc-&gt;cur_master-&gt;hw_cdm)</div><div class='add'>+			crtc_state-&gt;mode_changed = true;</div><div class='add'>+		else if (!topology.needs_cdm &amp;&amp; dpu_enc-&gt;cur_master-&gt;hw_cdm)</div><div class='add'>+			crtc_state-&gt;mode_changed = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Release and Allocate resources on every modeset</div><div class='ctx'> 	 * Dont allocate when active is false.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -1094,6 +1083,15 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,</div><div class='ctx'> </div><div class='ctx'> 	dpu_enc-&gt;dsc_mask = dsc_mask;</div><div class='ctx'> </div><div class='add'>+	if (dpu_enc-&gt;disp_info.intf_type == INTF_WB &amp;&amp; conn_state-&gt;writeback_job) {</div><div class='add'>+		struct dpu_hw_blk *hw_cdm = NULL;</div><div class='add'>+</div><div class='add'>+		dpu_rm_get_assigned_resources(&amp;dpu_kms-&gt;rm, global_state,</div><div class='add'>+					      drm_enc-&gt;base.id, DPU_HW_BLK_CDM,</div><div class='add'>+					      &amp;hw_cdm, 1);</div><div class='add'>+		dpu_enc-&gt;cur_master-&gt;hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	cstate = to_dpu_crtc_state(crtc_state);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_lm; i++) {</div><div class='hunk'>@@ -1204,6 +1202,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,</div><div class='ctx'> </div><div class='ctx'> 	dpu_enc-&gt;dsc = dpu_encoder_get_dsc_config(drm_enc);</div><div class='ctx'> </div><div class='add'>+	atomic_set(&amp;dpu_enc-&gt;frame_done_timeout_cnt, 0);</div><div class='add'>+</div><div class='ctx'> 	if (disp_info-&gt;intf_type == INTF_DP)</div><div class='ctx'> 		dpu_enc-&gt;wide_bus_en = msm_dp_wide_bus_available(priv-&gt;dp[index]);</div><div class='ctx'> 	else if (disp_info-&gt;intf_type == INTF_DSI)</div><div class='hunk'>@@ -2080,6 +2080,15 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 					phys_enc-&gt;hw_pp-&gt;merge_3d-&gt;idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (phys_enc-&gt;hw_cdm) {</div><div class='add'>+		if (phys_enc-&gt;hw_cdm-&gt;ops.bind_pingpong_blk &amp;&amp; phys_enc-&gt;hw_pp)</div><div class='add'>+			phys_enc-&gt;hw_cdm-&gt;ops.bind_pingpong_blk(phys_enc-&gt;hw_cdm,</div><div class='add'>+								PINGPONG_NONE);</div><div class='add'>+		if (phys_enc-&gt;hw_ctl-&gt;ops.update_pending_flush_cdm)</div><div class='add'>+			phys_enc-&gt;hw_ctl-&gt;ops.update_pending_flush_cdm(phys_enc-&gt;hw_ctl,</div><div class='add'>+								       phys_enc-&gt;hw_cdm-&gt;idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dpu_enc-&gt;dsc) {</div><div class='ctx'> 		dpu_encoder_unprep_dsc(dpu_enc);</div><div class='ctx'> 		dpu_enc-&gt;dsc = NULL;</div><div class='hunk'>@@ -2108,18 +2117,20 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> #ifdef CONFIG_DEBUG_FS</div><div class='ctx'> static int _dpu_encoder_status_show(struct seq_file *s, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct dpu_encoder_virt *dpu_enc = s-&gt;private;</div><div class='add'>+	struct drm_encoder *drm_enc = s-&gt;private;</div><div class='add'>+	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dpu_enc-&gt;enc_lock);</div><div class='ctx'> 	for (i = 0; i &lt; dpu_enc-&gt;num_phys_encs; i++) {</div><div class='ctx'> 		struct dpu_encoder_phys *phys = dpu_enc-&gt;phys_encs[i];</div><div class='ctx'> </div><div class='del'>-		seq_printf(s, "intf:%d  wb:%d  vsync:%8d     underrun:%8d    ",</div><div class='add'>+		seq_printf(s, "intf:%d  wb:%d  vsync:%8d     underrun:%8d    frame_done_cnt:%d",</div><div class='ctx'> 				phys-&gt;hw_intf ? phys-&gt;hw_intf-&gt;idx - INTF_0 : -1,</div><div class='ctx'> 				phys-&gt;hw_wb ? phys-&gt;hw_wb-&gt;idx - WB_0 : -1,</div><div class='ctx'> 				atomic_read(&amp;phys-&gt;vsync_cnt),</div><div class='del'>-				atomic_read(&amp;phys-&gt;underrun_cnt));</div><div class='add'>+				atomic_read(&amp;phys-&gt;underrun_cnt),</div><div class='add'>+				atomic_read(&amp;dpu_enc-&gt;frame_done_timeout_cnt));</div><div class='ctx'> </div><div class='ctx'> 		seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys-&gt;intf_mode));</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2130,49 +2141,18 @@ static int _dpu_encoder_status_show(struct seq_file *s, void *data)</div><div class='ctx'> </div><div class='ctx'> DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);</div><div class='ctx'> </div><div class='del'>-static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)</div><div class='add'>+static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root)</div><div class='ctx'> {</div><div class='del'>-	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);</div><div class='del'>-</div><div class='del'>-	char name[12];</div><div class='del'>-</div><div class='del'>-	if (!drm_enc-&gt;dev) {</div><div class='del'>-		DPU_ERROR("invalid encoder or kms\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	snprintf(name, sizeof(name), "encoder%u", drm_enc-&gt;base.id);</div><div class='del'>-</div><div class='del'>-	/* create overall sub-directory for the encoder */</div><div class='del'>-	dpu_enc-&gt;debugfs_root = debugfs_create_dir(name,</div><div class='del'>-			drm_enc-&gt;dev-&gt;primary-&gt;debugfs_root);</div><div class='del'>-</div><div class='ctx'> 	/* don't error check these */</div><div class='ctx'> 	debugfs_create_file("status", 0600,</div><div class='del'>-		dpu_enc-&gt;debugfs_root, dpu_enc, &amp;_dpu_encoder_status_fops);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+			    root, drm_enc, &amp;_dpu_encoder_status_fops);</div><div class='ctx'> }</div><div class='ctx'> #else</div><div class='del'>-static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+#define dpu_encoder_debugfs_init NULL</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-static int dpu_encoder_late_register(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	return _dpu_encoder_init_debugfs(encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dpu_encoder_early_unregister(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);</div><div class='del'>-</div><div class='del'>-	debugfs_remove_recursive(dpu_enc-&gt;debugfs_root);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int dpu_encoder_virt_add_phys_encs(</div><div class='add'>+		struct drm_device *dev,</div><div class='ctx'> 		struct msm_display_info *disp_info,</div><div class='ctx'> 		struct dpu_encoder_virt *dpu_enc,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *params)</div><div class='hunk'>@@ -2194,7 +2174,7 @@ static int dpu_encoder_virt_add_phys_encs(</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	if (disp_info-&gt;intf_type == INTF_WB) {</div><div class='del'>-		enc = dpu_encoder_phys_wb_init(params);</div><div class='add'>+		enc = dpu_encoder_phys_wb_init(dev, params);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(enc)) {</div><div class='ctx'> 			DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",</div><div class='hunk'>@@ -2205,7 +2185,7 @@ static int dpu_encoder_virt_add_phys_encs(</div><div class='ctx'> 		dpu_enc-&gt;phys_encs[dpu_enc-&gt;num_phys_encs] = enc;</div><div class='ctx'> 		++dpu_enc-&gt;num_phys_encs;</div><div class='ctx'> 	} else if (disp_info-&gt;is_cmd_mode) {</div><div class='del'>-		enc = dpu_encoder_phys_cmd_init(params);</div><div class='add'>+		enc = dpu_encoder_phys_cmd_init(dev, params);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(enc)) {</div><div class='ctx'> 			DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",</div><div class='hunk'>@@ -2216,7 +2196,7 @@ static int dpu_encoder_virt_add_phys_encs(</div><div class='ctx'> 		dpu_enc-&gt;phys_encs[dpu_enc-&gt;num_phys_encs] = enc;</div><div class='ctx'> 		++dpu_enc-&gt;num_phys_encs;</div><div class='ctx'> 	} else {</div><div class='del'>-		enc = dpu_encoder_phys_vid_init(params);</div><div class='add'>+		enc = dpu_encoder_phys_vid_init(dev, params);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(enc)) {</div><div class='ctx'> 			DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",</div><div class='hunk'>@@ -2305,7 +2285,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ret = dpu_encoder_virt_add_phys_encs(disp_info,</div><div class='add'>+		ret = dpu_encoder_virt_add_phys_encs(dpu_kms-&gt;dev, disp_info,</div><div class='ctx'> 				dpu_enc, &amp;phys_params);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");</div><div class='hunk'>@@ -2339,7 +2319,10 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");</div><div class='add'>+	DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");</div><div class='add'>+</div><div class='add'>+	if (atomic_inc_return(&amp;dpu_enc-&gt;frame_done_timeout_cnt) == 1)</div><div class='add'>+		msm_disp_snapshot_state(drm_enc-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	event = DPU_ENCODER_FRAME_EVENT_ERROR;</div><div class='ctx'> 	trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);</div><div class='hunk'>@@ -2354,9 +2337,7 @@ static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct drm_encoder_funcs dpu_encoder_funcs = {</div><div class='del'>-		.destroy = dpu_encoder_destroy,</div><div class='del'>-		.late_register = dpu_encoder_late_register,</div><div class='del'>-		.early_unregister = dpu_encoder_early_unregister,</div><div class='add'>+	.debugfs_init = dpu_encoder_debugfs_init,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct drm_encoder *dpu_encoder_init(struct drm_device *dev,</div><div class='hunk'>@@ -2365,20 +2346,13 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct msm_drm_private *priv = dev-&gt;dev_private;</div><div class='ctx'> 	struct dpu_kms *dpu_kms = to_dpu_kms(priv-&gt;kms);</div><div class='del'>-	struct drm_encoder *drm_enc = NULL;</div><div class='del'>-	struct dpu_encoder_virt *dpu_enc = NULL;</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	dpu_enc = devm_kzalloc(dev-&gt;dev, sizeof(*dpu_enc), GFP_KERNEL);</div><div class='del'>-	if (!dpu_enc)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	struct dpu_encoder_virt *dpu_enc;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = drm_encoder_init(dev, &amp;dpu_enc-&gt;base, &amp;dpu_encoder_funcs,</div><div class='del'>-			       drm_enc_mode, NULL);</div><div class='del'>-	if (ret) {</div><div class='del'>-		devm_kfree(dev-&gt;dev, dpu_enc);</div><div class='del'>-		return ERR_PTR(ret);</div><div class='del'>-	}</div><div class='add'>+	dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,</div><div class='add'>+				     &amp;dpu_encoder_funcs, drm_enc_mode, NULL);</div><div class='add'>+	if (IS_ERR(dpu_enc))</div><div class='add'>+		return ERR_CAST(dpu_enc);</div><div class='ctx'> </div><div class='ctx'> 	drm_encoder_helper_add(&amp;dpu_enc-&gt;base, &amp;dpu_encoder_helper_funcs);</div><div class='ctx'> </div><div class='hunk'>@@ -2388,10 +2362,13 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,</div><div class='ctx'> 	mutex_init(&amp;dpu_enc-&gt;rc_lock);</div><div class='ctx'> </div><div class='ctx'> 	ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto fail;</div><div class='add'>+	if (ret) {</div><div class='add'>+		DPU_ERROR("failed to setup encoder\n");</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	atomic_set(&amp;dpu_enc-&gt;frame_done_timeout_ms, 0);</div><div class='add'>+	atomic_set(&amp;dpu_enc-&gt;frame_done_timeout_cnt, 0);</div><div class='ctx'> 	timer_setup(&amp;dpu_enc-&gt;frame_done_timer,</div><div class='ctx'> 			dpu_encoder_frame_done_timeout, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -2404,13 +2381,6 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev,</div><div class='ctx'> 	DPU_DEBUG_ENC(dpu_enc, "created\n");</div><div class='ctx'> </div><div class='ctx'> 	return &amp;dpu_enc-&gt;base;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	DPU_ERROR("failed to create encoder\n");</div><div class='del'>-	if (drm_enc)</div><div class='del'>-		dpu_encoder_destroy(drm_enc);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,</div><div class='hunk'>@@ -2437,9 +2407,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,</div><div class='ctx'> 		case MSM_ENC_TX_COMPLETE:</div><div class='ctx'> 			fn_wait = phys-&gt;ops.wait_for_tx_complete;</div><div class='ctx'> 			break;</div><div class='del'>-		case MSM_ENC_VBLANK:</div><div class='del'>-			fn_wait = phys-&gt;ops.wait_for_vblank;</div><div class='del'>-			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",</div><div class='ctx'> 					event);</div><div class='hunk'>@@ -2497,7 +2464,6 @@ void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> 	phys_enc-&gt;enc_spinlock = p-&gt;enc_spinlock;</div><div class='ctx'> 	phys_enc-&gt;enable_state = DPU_ENC_DISABLED;</div><div class='ctx'> </div><div class='del'>-	atomic_set(&amp;phys_enc-&gt;vblank_refcount, 0);</div><div class='ctx'> 	atomic_set(&amp;phys_enc-&gt;pending_kickoff_cnt, 0);</div><div class='ctx'> 	atomic_set(&amp;phys_enc-&gt;pending_ctlstart_cnt, 0);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h<br/>index 6f04c3d56e77..993f26343331 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h</a></div><div class='hunk'>@@ -14,8 +14,10 @@</div><div class='ctx'> #include "dpu_hw_intf.h"</div><div class='ctx'> #include "dpu_hw_wb.h"</div><div class='ctx'> #include "dpu_hw_pingpong.h"</div><div class='add'>+#include "dpu_hw_cdm.h"</div><div class='ctx'> #include "dpu_hw_ctl.h"</div><div class='ctx'> #include "dpu_hw_top.h"</div><div class='add'>+#include "dpu_hw_util.h"</div><div class='ctx'> #include "dpu_encoder.h"</div><div class='ctx'> #include "dpu_crtc.h"</div><div class='ctx'> </div><div class='hunk'>@@ -72,7 +74,6 @@ struct dpu_encoder_phys;</div><div class='ctx'>  * @enable:			DRM Call. Enable a DRM mode.</div><div class='ctx'>  * @disable:			DRM Call. Disable mode.</div><div class='ctx'>  * @atomic_check:		DRM Call. Atomic check new DRM state.</div><div class='del'>- * @destroy:			DRM Call. Destroy and release resources.</div><div class='ctx'>  * @control_vblank_irq		Register/Deregister for VBLANK IRQ</div><div class='ctx'>  * @wait_for_commit_done:	Wait for hardware to have flushed the</div><div class='ctx'>  *				current pending frames to hardware</div><div class='hunk'>@@ -102,11 +103,9 @@ struct dpu_encoder_phys_ops {</div><div class='ctx'> 	int (*atomic_check)(struct dpu_encoder_phys *encoder,</div><div class='ctx'> 			    struct drm_crtc_state *crtc_state,</div><div class='ctx'> 			    struct drm_connector_state *conn_state);</div><div class='del'>-	void (*destroy)(struct dpu_encoder_phys *encoder);</div><div class='ctx'> 	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);</div><div class='ctx'> 	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);</div><div class='ctx'> 	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);</div><div class='del'>-	int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);</div><div class='ctx'> 	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);</div><div class='ctx'> 	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);</div><div class='ctx'> 	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);</div><div class='hunk'>@@ -153,8 +152,10 @@ enum dpu_intr_idx {</div><div class='ctx'>  * @hw_pp:		Hardware interface to the ping pong registers</div><div class='ctx'>  * @hw_intf:		Hardware interface to the intf registers</div><div class='ctx'>  * @hw_wb:		Hardware interface to the wb registers</div><div class='add'>+ * @hw_cdm:		Hardware interface to the CDM registers</div><div class='ctx'>  * @dpu_kms:		Pointer to the dpu_kms top level</div><div class='ctx'>  * @cached_mode:	DRM mode cached at mode_set time, acted on in enable</div><div class='add'>+ * @vblank_ctl_lock:	Vblank ctl mutex lock to protect vblank_refcount</div><div class='ctx'>  * @enabled:		Whether the encoder has enabled and running a mode</div><div class='ctx'>  * @split_role:		Role to play in a split-panel configuration</div><div class='ctx'>  * @intf_mode:		Interface mode</div><div class='hunk'>@@ -181,13 +182,15 @@ struct dpu_encoder_phys {</div><div class='ctx'> 	struct dpu_hw_pingpong *hw_pp;</div><div class='ctx'> 	struct dpu_hw_intf *hw_intf;</div><div class='ctx'> 	struct dpu_hw_wb *hw_wb;</div><div class='add'>+	struct dpu_hw_cdm *hw_cdm;</div><div class='ctx'> 	struct dpu_kms *dpu_kms;</div><div class='ctx'> 	struct drm_display_mode cached_mode;</div><div class='add'>+	struct mutex vblank_ctl_lock;</div><div class='ctx'> 	enum dpu_enc_split_role split_role;</div><div class='ctx'> 	enum dpu_intf_mode intf_mode;</div><div class='ctx'> 	spinlock_t *enc_spinlock;</div><div class='ctx'> 	enum dpu_enc_enable_state enable_state;</div><div class='del'>-	atomic_t vblank_refcount;</div><div class='add'>+	int vblank_refcount;</div><div class='ctx'> 	atomic_t vsync_cnt;</div><div class='ctx'> 	atomic_t underrun_cnt;</div><div class='ctx'> 	atomic_t pending_ctlstart_cnt;</div><div class='hunk'>@@ -210,6 +213,7 @@ static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)</div><div class='ctx'>  * @wbirq_refcount:     Reference count of writeback interrupt</div><div class='ctx'>  * @wb_done_timeout_cnt: number of wb done irq timeout errors</div><div class='ctx'>  * @wb_cfg:  writeback block config to store fb related details</div><div class='add'>+ * @cdm_cfg: cdm block config needed to store writeback block's CDM configuration</div><div class='ctx'>  * @wb_conn: backpointer to writeback connector</div><div class='ctx'>  * @wb_job: backpointer to current writeback job</div><div class='ctx'>  * @dest:   dpu buffer layout for current writeback output buffer</div><div class='hunk'>@@ -219,6 +223,7 @@ struct dpu_encoder_phys_wb {</div><div class='ctx'> 	atomic_t wbirq_refcount;</div><div class='ctx'> 	int wb_done_timeout_cnt;</div><div class='ctx'> 	struct dpu_hw_wb_cfg wb_cfg;</div><div class='add'>+	struct dpu_hw_cdm_cfg cdm_cfg;</div><div class='ctx'> 	struct drm_writeback_connector *wb_conn;</div><div class='ctx'> 	struct drm_writeback_job *wb_job;</div><div class='ctx'> 	struct dpu_hw_fmt_layout dest;</div><div class='hunk'>@@ -281,22 +286,24 @@ struct dpu_encoder_wait_info {</div><div class='ctx'>  * @p:	Pointer to init params structure</div><div class='ctx'>  * Return: Error code or newly allocated encoder</div><div class='ctx'>  */</div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_vid_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @p:	Pointer to init params structure</div><div class='ctx'>  * Return: Error code or newly allocated encoder</div><div class='ctx'>  */</div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_encoder_phys_wb_init - initialize writeback encoder</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @init:	Pointer to init info structure with initialization params</div><div class='ctx'>  */</div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_wb_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c<br/>index be185fe69793..a301e2833177 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c</a></div><div class='hunk'>@@ -13,6 +13,8 @@</div><div class='ctx'> #include "dpu_trace.h"</div><div class='ctx'> #include "disp/msm_disp_snapshot.h"</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \</div><div class='ctx'> 		(e) &amp;&amp; (e)-&gt;base.parent ? \</div><div class='ctx'> 		(e)-&gt;base.parent-&gt;base.id : -1, \</div><div class='hunk'>@@ -244,7 +246,8 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	refcount = atomic_read(&amp;phys_enc-&gt;vblank_refcount);</div><div class='add'>+	mutex_lock(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='add'>+	refcount = phys_enc-&gt;vblank_refcount;</div><div class='ctx'> </div><div class='ctx'> 	/* Slave encoders don't report vblank */</div><div class='ctx'> 	if (!dpu_encoder_phys_cmd_is_master(phys_enc))</div><div class='hunk'>@@ -260,16 +263,24 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(</div><div class='ctx'> 		      phys_enc-&gt;hw_pp-&gt;idx - PINGPONG_0,</div><div class='ctx'> 		      enable ? "true" : "false", refcount);</div><div class='ctx'> </div><div class='del'>-	if (enable &amp;&amp; atomic_inc_return(&amp;phys_enc-&gt;vblank_refcount) == 1)</div><div class='del'>-		ret = dpu_core_irq_register_callback(phys_enc-&gt;dpu_kms,</div><div class='del'>-				phys_enc-&gt;irq[INTR_IDX_RDPTR],</div><div class='del'>-				dpu_encoder_phys_cmd_te_rd_ptr_irq,</div><div class='del'>-				phys_enc);</div><div class='del'>-	else if (!enable &amp;&amp; atomic_dec_return(&amp;phys_enc-&gt;vblank_refcount) == 0)</div><div class='del'>-		ret = dpu_core_irq_unregister_callback(phys_enc-&gt;dpu_kms,</div><div class='del'>-				phys_enc-&gt;irq[INTR_IDX_RDPTR]);</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (phys_enc-&gt;vblank_refcount == 0)</div><div class='add'>+			ret = dpu_core_irq_register_callback(phys_enc-&gt;dpu_kms,</div><div class='add'>+					phys_enc-&gt;irq[INTR_IDX_RDPTR],</div><div class='add'>+					dpu_encoder_phys_cmd_te_rd_ptr_irq,</div><div class='add'>+					phys_enc);</div><div class='add'>+		if (!ret)</div><div class='add'>+			phys_enc-&gt;vblank_refcount++;</div><div class='add'>+	} else if (!enable) {</div><div class='add'>+		if (phys_enc-&gt;vblank_refcount == 1)</div><div class='add'>+			ret = dpu_core_irq_unregister_callback(phys_enc-&gt;dpu_kms,</div><div class='add'>+					phys_enc-&gt;irq[INTR_IDX_RDPTR]);</div><div class='add'>+		if (!ret)</div><div class='add'>+			phys_enc-&gt;vblank_refcount--;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> end:</div><div class='add'>+	mutex_unlock(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",</div><div class='ctx'> 			  DRMID(phys_enc-&gt;parent),</div><div class='hunk'>@@ -285,7 +296,7 @@ static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> {</div><div class='ctx'> 	trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc-&gt;parent),</div><div class='ctx'> 			phys_enc-&gt;hw_pp-&gt;idx - PINGPONG_0,</div><div class='del'>-			enable, atomic_read(&amp;phys_enc-&gt;vblank_refcount));</div><div class='add'>+			enable, phys_enc-&gt;vblank_refcount);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		dpu_core_irq_register_callback(phys_enc-&gt;dpu_kms,</div><div class='hunk'>@@ -558,14 +569,6 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 	phys_enc-&gt;enable_state = DPU_ENC_DISABLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc)</div><div class='del'>-{</div><div class='del'>-	struct dpu_encoder_phys_cmd *cmd_enc =</div><div class='del'>-		to_dpu_encoder_phys_cmd(phys_enc);</div><div class='del'>-</div><div class='del'>-	kfree(cmd_enc);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dpu_encoder_phys_cmd_prepare_for_kickoff(</div><div class='ctx'> 		struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> {</div><div class='hunk'>@@ -681,33 +684,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done(</div><div class='ctx'> 	return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dpu_encoder_phys_cmd_wait_for_vblank(</div><div class='del'>-		struct dpu_encoder_phys *phys_enc)</div><div class='del'>-{</div><div class='del'>-	int rc = 0;</div><div class='del'>-	struct dpu_encoder_phys_cmd *cmd_enc;</div><div class='del'>-	struct dpu_encoder_wait_info wait_info;</div><div class='del'>-</div><div class='del'>-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);</div><div class='del'>-</div><div class='del'>-	/* only required for master controller */</div><div class='del'>-	if (!dpu_encoder_phys_cmd_is_master(phys_enc))</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	wait_info.wq = &amp;cmd_enc-&gt;pending_vblank_wq;</div><div class='del'>-	wait_info.atomic_cnt = &amp;cmd_enc-&gt;pending_vblank_cnt;</div><div class='del'>-	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;</div><div class='del'>-</div><div class='del'>-	atomic_inc(&amp;cmd_enc-&gt;pending_vblank_cnt);</div><div class='del'>-</div><div class='del'>-	rc = dpu_encoder_helper_wait_for_irq(phys_enc,</div><div class='del'>-			phys_enc-&gt;irq[INTR_IDX_RDPTR],</div><div class='del'>-			dpu_encoder_phys_cmd_te_rd_ptr_irq,</div><div class='del'>-			&amp;wait_info);</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dpu_encoder_phys_cmd_handle_post_kickoff(</div><div class='ctx'> 		struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> {</div><div class='hunk'>@@ -731,12 +707,10 @@ static void dpu_encoder_phys_cmd_init_ops(</div><div class='ctx'> 	ops-&gt;atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set;</div><div class='ctx'> 	ops-&gt;enable = dpu_encoder_phys_cmd_enable;</div><div class='ctx'> 	ops-&gt;disable = dpu_encoder_phys_cmd_disable;</div><div class='del'>-	ops-&gt;destroy = dpu_encoder_phys_cmd_destroy;</div><div class='ctx'> 	ops-&gt;control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;</div><div class='ctx'> 	ops-&gt;wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;</div><div class='ctx'> 	ops-&gt;prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;</div><div class='ctx'> 	ops-&gt;wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;</div><div class='del'>-	ops-&gt;wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;</div><div class='ctx'> 	ops-&gt;trigger_start = dpu_encoder_phys_cmd_trigger_start;</div><div class='ctx'> 	ops-&gt;needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;</div><div class='ctx'> 	ops-&gt;irq_control = dpu_encoder_phys_cmd_irq_control;</div><div class='hunk'>@@ -746,7 +720,7 @@ static void dpu_encoder_phys_cmd_init_ops(</div><div class='ctx'> 	ops-&gt;get_line_count = dpu_encoder_phys_cmd_get_line_count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_encoder_phys *phys_enc = NULL;</div><div class='hunk'>@@ -754,7 +728,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(</div><div class='ctx'> </div><div class='ctx'> 	DPU_DEBUG("intf\n");</div><div class='ctx'> </div><div class='del'>-	cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);</div><div class='add'>+	cmd_enc = drmm_kzalloc(dev, sizeof(*cmd_enc), GFP_KERNEL);</div><div class='ctx'> 	if (!cmd_enc) {</div><div class='ctx'> 		DPU_ERROR("failed to allocate\n");</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='hunk'>@@ -763,6 +737,9 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(</div><div class='ctx'> </div><div class='ctx'> 	dpu_encoder_phys_init(phys_enc, p);</div><div class='ctx'> </div><div class='add'>+	mutex_init(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='add'>+	phys_enc-&gt;vblank_refcount = 0;</div><div class='add'>+</div><div class='ctx'> 	dpu_encoder_phys_cmd_init_ops(&amp;phys_enc-&gt;ops);</div><div class='ctx'> 	phys_enc-&gt;intf_mode = INTF_MODE_CMD;</div><div class='ctx'> 	cmd_enc-&gt;stream_sel = 0;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c<br/>index a01fda711883..d0f56c5c4cce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c</a></div><div class='hunk'>@@ -11,6 +11,8 @@</div><div class='ctx'> #include "dpu_trace.h"</div><div class='ctx'> #include "disp/msm_disp_snapshot.h"</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \</div><div class='ctx'> 		(e) &amp;&amp; (e)-&gt;parent ? \</div><div class='ctx'> 		(e)-&gt;parent-&gt;base.id : -1, \</div><div class='hunk'>@@ -364,7 +366,8 @@ static int dpu_encoder_phys_vid_control_vblank_irq(</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	int refcount;</div><div class='ctx'> </div><div class='del'>-	refcount = atomic_read(&amp;phys_enc-&gt;vblank_refcount);</div><div class='add'>+	mutex_lock(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='add'>+	refcount = phys_enc-&gt;vblank_refcount;</div><div class='ctx'> </div><div class='ctx'> 	/* Slave encoders don't report vblank */</div><div class='ctx'> 	if (!dpu_encoder_phys_vid_is_master(phys_enc))</div><div class='hunk'>@@ -377,18 +380,26 @@ static int dpu_encoder_phys_vid_control_vblank_irq(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc-&gt;parent), enable,</div><div class='del'>-		      atomic_read(&amp;phys_enc-&gt;vblank_refcount));</div><div class='add'>+		      refcount);</div><div class='ctx'> </div><div class='del'>-	if (enable &amp;&amp; atomic_inc_return(&amp;phys_enc-&gt;vblank_refcount) == 1)</div><div class='del'>-		ret = dpu_core_irq_register_callback(phys_enc-&gt;dpu_kms,</div><div class='del'>-				phys_enc-&gt;irq[INTR_IDX_VSYNC],</div><div class='del'>-				dpu_encoder_phys_vid_vblank_irq,</div><div class='del'>-				phys_enc);</div><div class='del'>-	else if (!enable &amp;&amp; atomic_dec_return(&amp;phys_enc-&gt;vblank_refcount) == 0)</div><div class='del'>-		ret = dpu_core_irq_unregister_callback(phys_enc-&gt;dpu_kms,</div><div class='del'>-				phys_enc-&gt;irq[INTR_IDX_VSYNC]);</div><div class='add'>+	if (enable) {</div><div class='add'>+		if (phys_enc-&gt;vblank_refcount == 0)</div><div class='add'>+			ret = dpu_core_irq_register_callback(phys_enc-&gt;dpu_kms,</div><div class='add'>+					phys_enc-&gt;irq[INTR_IDX_VSYNC],</div><div class='add'>+					dpu_encoder_phys_vid_vblank_irq,</div><div class='add'>+					phys_enc);</div><div class='add'>+		if (!ret)</div><div class='add'>+			phys_enc-&gt;vblank_refcount++;</div><div class='add'>+	} else if (!enable) {</div><div class='add'>+		if (phys_enc-&gt;vblank_refcount == 1)</div><div class='add'>+			ret = dpu_core_irq_unregister_callback(phys_enc-&gt;dpu_kms,</div><div class='add'>+					phys_enc-&gt;irq[INTR_IDX_VSYNC]);</div><div class='add'>+		if (!ret)</div><div class='add'>+			phys_enc-&gt;vblank_refcount--;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> end:</div><div class='add'>+	mutex_unlock(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",</div><div class='ctx'> 			  DRMID(phys_enc-&gt;parent),</div><div class='hunk'>@@ -438,13 +449,7 @@ skip_flush:</div><div class='ctx'> 		phys_enc-&gt;enable_state = DPU_ENC_ENABLING;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc)</div><div class='del'>-{</div><div class='del'>-	DPU_DEBUG_VIDENC(phys_enc, "\n");</div><div class='del'>-	kfree(phys_enc);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dpu_encoder_phys_vid_wait_for_vblank(</div><div class='add'>+static int dpu_encoder_phys_vid_wait_for_tx_complete(</div><div class='ctx'> 		struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_encoder_wait_info wait_info;</div><div class='hunk'>@@ -558,7 +563,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 	 * scanout buffer) don't latch properly..</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (dpu_encoder_phys_vid_is_master(phys_enc)) {</div><div class='del'>-		ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);</div><div class='add'>+		ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			atomic_set(&amp;phys_enc-&gt;pending_kickoff_cnt, 0);</div><div class='ctx'> 			DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",</div><div class='hunk'>@@ -578,7 +583,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 		spin_lock_irqsave(phys_enc-&gt;enc_spinlock, lock_flags);</div><div class='ctx'> 		dpu_encoder_phys_inc_pending(phys_enc);</div><div class='ctx'> 		spin_unlock_irqrestore(phys_enc-&gt;enc_spinlock, lock_flags);</div><div class='del'>-		ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);</div><div class='add'>+		ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			atomic_set(&amp;phys_enc-&gt;pending_kickoff_cnt, 0);</div><div class='ctx'> 			DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",</div><div class='hunk'>@@ -618,7 +623,7 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> 	trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc-&gt;parent),</div><div class='ctx'> 			    phys_enc-&gt;hw_intf-&gt;idx - INTF_0,</div><div class='ctx'> 			    enable,</div><div class='del'>-			    atomic_read(&amp;phys_enc-&gt;vblank_refcount));</div><div class='add'>+			   phys_enc-&gt;vblank_refcount);</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);</div><div class='hunk'>@@ -681,11 +686,9 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)</div><div class='ctx'> 	ops-&gt;atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;</div><div class='ctx'> 	ops-&gt;enable = dpu_encoder_phys_vid_enable;</div><div class='ctx'> 	ops-&gt;disable = dpu_encoder_phys_vid_disable;</div><div class='del'>-	ops-&gt;destroy = dpu_encoder_phys_vid_destroy;</div><div class='ctx'> 	ops-&gt;control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;</div><div class='ctx'> 	ops-&gt;wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;</div><div class='del'>-	ops-&gt;wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;</div><div class='del'>-	ops-&gt;wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;</div><div class='add'>+	ops-&gt;wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;</div><div class='ctx'> 	ops-&gt;irq_control = dpu_encoder_phys_vid_irq_control;</div><div class='ctx'> 	ops-&gt;prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;</div><div class='ctx'> 	ops-&gt;handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;</div><div class='hunk'>@@ -694,7 +697,7 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)</div><div class='ctx'> 	ops-&gt;get_frame_count = dpu_encoder_phys_vid_get_frame_count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_vid_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_encoder_phys *phys_enc = NULL;</div><div class='hunk'>@@ -704,7 +707,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL);</div><div class='add'>+	phys_enc = drmm_kzalloc(dev, sizeof(*phys_enc), GFP_KERNEL);</div><div class='ctx'> 	if (!phys_enc) {</div><div class='ctx'> 		DPU_ERROR("failed to create encoder due to memory allocation error\n");</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='hunk'>@@ -713,6 +716,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(</div><div class='ctx'> 	DPU_DEBUG_VIDENC(phys_enc, "\n");</div><div class='ctx'> </div><div class='ctx'> 	dpu_encoder_phys_init(phys_enc, p);</div><div class='add'>+	mutex_init(&amp;phys_enc-&gt;vblank_ctl_lock);</div><div class='add'>+	phys_enc-&gt;vblank_refcount = 0;</div><div class='ctx'> </div><div class='ctx'> 	dpu_encoder_phys_vid_init_ops(&amp;phys_enc-&gt;ops);</div><div class='ctx'> 	phys_enc-&gt;intf_mode = INTF_MODE_VIDEO;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c<br/>index 0b6a761d68b7..4cd2d9e3131a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_framebuffer.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dpu_encoder_phys.h"</div><div class='ctx'> #include "dpu_formats.h"</div><div class='hunk'>@@ -206,13 +207,14 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dpu_encoder_phys_wb_setup_cdp - setup chroma down prefetch block</div><div class='add'>+ * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path</div><div class='ctx'>  * @phys_enc:Pointer to physical encoder</div><div class='ctx'>  */</div><div class='del'>-static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)</div><div class='add'>+static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_wb *hw_wb;</div><div class='ctx'> 	struct dpu_hw_ctl *ctl;</div><div class='add'>+	struct dpu_hw_cdm *hw_cdm;</div><div class='ctx'> </div><div class='ctx'> 	if (!phys_enc) {</div><div class='ctx'> 		DPU_ERROR("invalid encoder\n");</div><div class='hunk'>@@ -221,6 +223,7 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> </div><div class='ctx'> 	hw_wb = phys_enc-&gt;hw_wb;</div><div class='ctx'> 	ctl = phys_enc-&gt;hw_ctl;</div><div class='add'>+	hw_cdm = phys_enc-&gt;hw_cdm;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(DPU_CTL_ACTIVE_CFG, &amp;ctl-&gt;caps-&gt;features) &amp;&amp;</div><div class='ctx'> 		(phys_enc-&gt;hw_ctl &amp;&amp;</div><div class='hunk'>@@ -237,6 +240,9 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 		if (mode_3d &amp;&amp; hw_pp &amp;&amp; hw_pp-&gt;merge_3d)</div><div class='ctx'> 			intf_cfg.merge_3d = hw_pp-&gt;merge_3d-&gt;idx;</div><div class='ctx'> </div><div class='add'>+		if (hw_cdm)</div><div class='add'>+			intf_cfg.cdm = hw_cdm-&gt;idx;</div><div class='add'>+</div><div class='ctx'> 		if (phys_enc-&gt;hw_pp-&gt;merge_3d &amp;&amp; phys_enc-&gt;hw_pp-&gt;merge_3d-&gt;ops.setup_3d_mode)</div><div class='ctx'> 			phys_enc-&gt;hw_pp-&gt;merge_3d-&gt;ops.setup_3d_mode(phys_enc-&gt;hw_pp-&gt;merge_3d,</div><div class='ctx'> 					mode_3d);</div><div class='hunk'>@@ -259,6 +265,96 @@ static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block</div><div class='add'>+ *                                     This API does not handle DPU_CHROMA_H1V2.</div><div class='add'>+ * @phys_enc:Pointer to physical encoder</div><div class='add'>+ */</div><div class='add'>+static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc)</div><div class='add'>+{</div><div class='add'>+	struct dpu_hw_cdm *hw_cdm;</div><div class='add'>+	struct dpu_hw_cdm_cfg *cdm_cfg;</div><div class='add'>+	struct dpu_hw_pingpong *hw_pp;</div><div class='add'>+	struct dpu_encoder_phys_wb *wb_enc;</div><div class='add'>+	const struct msm_format *format;</div><div class='add'>+	const struct dpu_format *dpu_fmt;</div><div class='add'>+	struct drm_writeback_job *wb_job;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!phys_enc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	wb_enc = to_dpu_encoder_phys_wb(phys_enc);</div><div class='add'>+	cdm_cfg = &amp;wb_enc-&gt;cdm_cfg;</div><div class='add'>+	hw_pp = phys_enc-&gt;hw_pp;</div><div class='add'>+	hw_cdm = phys_enc-&gt;hw_cdm;</div><div class='add'>+	wb_job = wb_enc-&gt;wb_job;</div><div class='add'>+</div><div class='add'>+	format = msm_framebuffer_format(wb_enc-&gt;wb_job-&gt;fb);</div><div class='add'>+	dpu_fmt = dpu_get_dpu_format_ext(format-&gt;pixel_format, wb_job-&gt;fb-&gt;modifier);</div><div class='add'>+</div><div class='add'>+	if (!hw_cdm)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {</div><div class='add'>+		DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc-&gt;parent),</div><div class='add'>+			  dpu_fmt-&gt;base.pixel_format);</div><div class='add'>+		if (hw_cdm-&gt;ops.bind_pingpong_blk)</div><div class='add'>+			hw_cdm-&gt;ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);</div><div class='add'>+</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));</div><div class='add'>+</div><div class='add'>+	cdm_cfg-&gt;output_width = wb_job-&gt;fb-&gt;width;</div><div class='add'>+	cdm_cfg-&gt;output_height = wb_job-&gt;fb-&gt;height;</div><div class='add'>+	cdm_cfg-&gt;output_fmt = dpu_fmt;</div><div class='add'>+	cdm_cfg-&gt;output_type = CDM_CDWN_OUTPUT_WB;</div><div class='add'>+	cdm_cfg-&gt;output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?</div><div class='add'>+			CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;</div><div class='add'>+	cdm_cfg-&gt;csc_cfg = &amp;dpu_csc10_rgb2yuv_601l;</div><div class='add'>+</div><div class='add'>+	/* enable 10 bit logic */</div><div class='add'>+	switch (cdm_cfg-&gt;output_fmt-&gt;chroma_sample) {</div><div class='add'>+	case DPU_CHROMA_RGB:</div><div class='add'>+		cdm_cfg-&gt;h_cdwn_type = CDM_CDWN_DISABLE;</div><div class='add'>+		cdm_cfg-&gt;v_cdwn_type = CDM_CDWN_DISABLE;</div><div class='add'>+		break;</div><div class='add'>+	case DPU_CHROMA_H2V1:</div><div class='add'>+		cdm_cfg-&gt;h_cdwn_type = CDM_CDWN_COSITE;</div><div class='add'>+		cdm_cfg-&gt;v_cdwn_type = CDM_CDWN_DISABLE;</div><div class='add'>+		break;</div><div class='add'>+	case DPU_CHROMA_420:</div><div class='add'>+		cdm_cfg-&gt;h_cdwn_type = CDM_CDWN_COSITE;</div><div class='add'>+		cdm_cfg-&gt;v_cdwn_type = CDM_CDWN_OFFSITE;</div><div class='add'>+		break;</div><div class='add'>+	case DPU_CHROMA_H1V2:</div><div class='add'>+	default:</div><div class='add'>+		DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",</div><div class='add'>+			  DRMID(phys_enc-&gt;parent));</div><div class='add'>+		cdm_cfg-&gt;h_cdwn_type = CDM_CDWN_DISABLE;</div><div class='add'>+		cdm_cfg-&gt;v_cdwn_type = CDM_CDWN_DISABLE;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",</div><div class='add'>+		  DRMID(phys_enc-&gt;parent), cdm_cfg-&gt;output_width,</div><div class='add'>+		  cdm_cfg-&gt;output_height, cdm_cfg-&gt;output_fmt-&gt;base.pixel_format,</div><div class='add'>+		  cdm_cfg-&gt;output_type, cdm_cfg-&gt;output_bit_depth,</div><div class='add'>+		  cdm_cfg-&gt;h_cdwn_type, cdm_cfg-&gt;v_cdwn_type);</div><div class='add'>+</div><div class='add'>+	if (hw_cdm-&gt;ops.enable) {</div><div class='add'>+		cdm_cfg-&gt;pp_id = hw_pp-&gt;idx;</div><div class='add'>+		ret = hw_cdm-&gt;ops.enable(hw_cdm, cdm_cfg);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",</div><div class='add'>+				  DRMID(phys_enc-&gt;parent), ret);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states</div><div class='ctx'>  * @phys_enc:	Pointer to physical encoder</div><div class='ctx'>  * @crtc_state:	Pointer to CRTC atomic state</div><div class='hunk'>@@ -307,7 +403,7 @@ static int dpu_encoder_phys_wb_atomic_check(</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return drm_atomic_helper_check_wb_connector_state(conn_state-&gt;connector, conn_state-&gt;state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -320,6 +416,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 	struct dpu_hw_wb *hw_wb;</div><div class='ctx'> 	struct dpu_hw_ctl *hw_ctl;</div><div class='ctx'> 	struct dpu_hw_pingpong *hw_pp;</div><div class='add'>+	struct dpu_hw_cdm *hw_cdm;</div><div class='ctx'> 	u32 pending_flush = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!phys_enc)</div><div class='hunk'>@@ -328,6 +425,7 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 	hw_wb = phys_enc-&gt;hw_wb;</div><div class='ctx'> 	hw_pp = phys_enc-&gt;hw_pp;</div><div class='ctx'> 	hw_ctl = phys_enc-&gt;hw_ctl;</div><div class='add'>+	hw_cdm = phys_enc-&gt;hw_cdm;</div><div class='ctx'> </div><div class='ctx'> 	DPU_DEBUG("[wb:%d]\n", hw_wb-&gt;idx - WB_0);</div><div class='ctx'> </div><div class='hunk'>@@ -343,6 +441,9 @@ static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 		hw_ctl-&gt;ops.update_pending_flush_merge_3d(hw_ctl,</div><div class='ctx'> 				hw_pp-&gt;merge_3d-&gt;idx);</div><div class='ctx'> </div><div class='add'>+	if (hw_cdm &amp;&amp; hw_ctl-&gt;ops.update_pending_flush_cdm)</div><div class='add'>+		hw_ctl-&gt;ops.update_pending_flush_cdm(hw_ctl, hw_cdm-&gt;idx);</div><div class='add'>+</div><div class='ctx'> 	if (hw_ctl-&gt;ops.get_pending_flush)</div><div class='ctx'> 		pending_flush = hw_ctl-&gt;ops.get_pending_flush(hw_ctl);</div><div class='ctx'> </div><div class='hunk'>@@ -374,8 +475,9 @@ static void dpu_encoder_phys_wb_setup(</div><div class='ctx'> </div><div class='ctx'> 	dpu_encoder_phys_wb_setup_fb(phys_enc, fb);</div><div class='ctx'> </div><div class='del'>-	dpu_encoder_phys_wb_setup_cdp(phys_enc);</div><div class='add'>+	dpu_encoder_helper_phys_setup_cdm(phys_enc);</div><div class='ctx'> </div><div class='add'>+	dpu_encoder_phys_wb_setup_ctl(phys_enc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -580,20 +682,6 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)</div><div class='ctx'> 	phys_enc-&gt;enable_state = DPU_ENC_DISABLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * dpu_encoder_phys_wb_destroy - destroy writeback encoder</div><div class='del'>- * @phys_enc:	Pointer to physical encoder</div><div class='del'>- */</div><div class='del'>-static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc)</div><div class='del'>-{</div><div class='del'>-	if (!phys_enc)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	DPU_DEBUG("[wb:%d]\n", phys_enc-&gt;hw_wb-&gt;idx - WB_0);</div><div class='del'>-</div><div class='del'>-	kfree(phys_enc);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,</div><div class='ctx'> 		struct drm_writeback_job *job)</div><div class='ctx'> {</div><div class='hunk'>@@ -689,7 +777,6 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)</div><div class='ctx'> 	ops-&gt;atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;</div><div class='ctx'> 	ops-&gt;enable = dpu_encoder_phys_wb_enable;</div><div class='ctx'> 	ops-&gt;disable = dpu_encoder_phys_wb_disable;</div><div class='del'>-	ops-&gt;destroy = dpu_encoder_phys_wb_destroy;</div><div class='ctx'> 	ops-&gt;atomic_check = dpu_encoder_phys_wb_atomic_check;</div><div class='ctx'> 	ops-&gt;wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;</div><div class='ctx'> 	ops-&gt;prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;</div><div class='hunk'>@@ -705,9 +792,10 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_encoder_phys_wb_init - initialize writeback encoder</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @p:	Pointer to init info structure with initialization params</div><div class='ctx'>  */</div><div class='del'>-struct dpu_encoder_phys *dpu_encoder_phys_wb_init(</div><div class='add'>+struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,</div><div class='ctx'> 		struct dpu_enc_phys_init_params *p)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_encoder_phys *phys_enc = NULL;</div><div class='hunk'>@@ -720,7 +808,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init(</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	wb_enc = kzalloc(sizeof(*wb_enc), GFP_KERNEL);</div><div class='add'>+	wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);</div><div class='ctx'> 	if (!wb_enc) {</div><div class='ctx'> 		DPU_ERROR("failed to allocate wb phys_enc enc\n");</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c<br/>index a1aada630780..54e8717403a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c</a></div><div class='hunk'>@@ -22,23 +22,14 @@</div><div class='ctx'> 	BIT(DPU_SSPP_CSC_10BIT))</div><div class='ctx'> </div><div class='ctx'> #define VIG_MSM8998_MASK \</div><div class='del'>-	(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))</div><div class='add'>+	(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))</div><div class='ctx'> </div><div class='ctx'> #define VIG_SDM845_MASK \</div><div class='del'>-	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))</div><div class='add'>+	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))</div><div class='ctx'> </div><div class='ctx'> #define VIG_SDM845_MASK_SDMA \</div><div class='ctx'> 	(VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))</div><div class='ctx'> </div><div class='del'>-#define VIG_SC7180_MASK \</div><div class='del'>-	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))</div><div class='del'>-</div><div class='del'>-#define VIG_SM6125_MASK \</div><div class='del'>-	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))</div><div class='del'>-</div><div class='del'>-#define VIG_SC7180_MASK_SDMA \</div><div class='del'>-	(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))</div><div class='del'>-</div><div class='ctx'> #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))</div><div class='ctx'> </div><div class='ctx'> #define DMA_MSM8998_MASK \</div><div class='hunk'>@@ -47,7 +38,7 @@</div><div class='ctx'> 	BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))</div><div class='ctx'> </div><div class='ctx'> #define VIG_SC7280_MASK \</div><div class='del'>-	(VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))</div><div class='add'>+	(VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION))</div><div class='ctx'> </div><div class='ctx'> #define VIG_SC7280_MASK_SDMA \</div><div class='ctx'> 	(VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))</div><div class='hunk'>@@ -211,7 +202,7 @@ static const u32 rotation_v2_formats[] = {</div><div class='ctx'> 	/* TODO add formats after validation */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const uint32_t wb2_formats[] = {</div><div class='add'>+static const u32 wb2_formats_rgb[] = {</div><div class='ctx'> 	DRM_FORMAT_RGB565,</div><div class='ctx'> 	DRM_FORMAT_BGR565,</div><div class='ctx'> 	DRM_FORMAT_RGB888,</div><div class='hunk'>@@ -245,21 +236,56 @@ static const uint32_t wb2_formats[] = {</div><div class='ctx'> 	DRM_FORMAT_XBGR4444,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const u32 wb2_formats_rgb_yuv[] = {</div><div class='add'>+	DRM_FORMAT_RGB565,</div><div class='add'>+	DRM_FORMAT_BGR565,</div><div class='add'>+	DRM_FORMAT_RGB888,</div><div class='add'>+	DRM_FORMAT_ARGB8888,</div><div class='add'>+	DRM_FORMAT_RGBA8888,</div><div class='add'>+	DRM_FORMAT_ABGR8888,</div><div class='add'>+	DRM_FORMAT_XRGB8888,</div><div class='add'>+	DRM_FORMAT_RGBX8888,</div><div class='add'>+	DRM_FORMAT_XBGR8888,</div><div class='add'>+	DRM_FORMAT_ARGB1555,</div><div class='add'>+	DRM_FORMAT_RGBA5551,</div><div class='add'>+	DRM_FORMAT_XRGB1555,</div><div class='add'>+	DRM_FORMAT_RGBX5551,</div><div class='add'>+	DRM_FORMAT_ARGB4444,</div><div class='add'>+	DRM_FORMAT_RGBA4444,</div><div class='add'>+	DRM_FORMAT_RGBX4444,</div><div class='add'>+	DRM_FORMAT_XRGB4444,</div><div class='add'>+	DRM_FORMAT_BGR565,</div><div class='add'>+	DRM_FORMAT_BGR888,</div><div class='add'>+	DRM_FORMAT_ABGR8888,</div><div class='add'>+	DRM_FORMAT_BGRA8888,</div><div class='add'>+	DRM_FORMAT_BGRX8888,</div><div class='add'>+	DRM_FORMAT_XBGR8888,</div><div class='add'>+	DRM_FORMAT_ABGR1555,</div><div class='add'>+	DRM_FORMAT_BGRA5551,</div><div class='add'>+	DRM_FORMAT_XBGR1555,</div><div class='add'>+	DRM_FORMAT_BGRX5551,</div><div class='add'>+	DRM_FORMAT_ABGR4444,</div><div class='add'>+	DRM_FORMAT_BGRA4444,</div><div class='add'>+	DRM_FORMAT_BGRX4444,</div><div class='add'>+	DRM_FORMAT_XBGR4444,</div><div class='add'>+	DRM_FORMAT_NV12,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*************************************************************</div><div class='ctx'>  * SSPP sub blocks config</div><div class='ctx'>  *************************************************************/</div><div class='ctx'> </div><div class='add'>+#define SSPP_SCALER_VER(maj, min) (((maj) &lt;&lt; 16) | (min))</div><div class='add'>+</div><div class='ctx'> /* SSPP common configuration */</div><div class='del'>-#define _VIG_SBLK(sdma_pri, qseed_ver) \</div><div class='add'>+#define _VIG_SBLK(scaler_ver) \</div><div class='ctx'> 	{ \</div><div class='ctx'> 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \</div><div class='ctx'> 	.maxupscale = MAX_UPSCALE_RATIO, \</div><div class='del'>-	.smart_dma_priority = sdma_pri, \</div><div class='ctx'> 	.scaler_blk = {.name = "scaler", \</div><div class='del'>-		.id = qseed_ver, \</div><div class='add'>+		.version = scaler_ver, \</div><div class='ctx'> 		.base = 0xa00, .len = 0xa0,}, \</div><div class='ctx'> 	.csc_blk = {.name = "csc", \</div><div class='del'>-		.id = DPU_SSPP_CSC_10BIT, \</div><div class='ctx'> 		.base = 0x1a00, .len = 0x100,}, \</div><div class='ctx'> 	.format_list = plane_formats_yuv, \</div><div class='ctx'> 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \</div><div class='hunk'>@@ -268,16 +294,14 @@ static const uint32_t wb2_formats[] = {</div><div class='ctx'> 	.rotation_cfg = NULL, \</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \</div><div class='add'>+#define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \</div><div class='ctx'> 	{ \</div><div class='ctx'> 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \</div><div class='ctx'> 	.maxupscale = MAX_UPSCALE_RATIO, \</div><div class='del'>-	.smart_dma_priority = sdma_pri, \</div><div class='ctx'> 	.scaler_blk = {.name = "scaler", \</div><div class='del'>-		.id = qseed_ver, \</div><div class='add'>+		.version = scaler_ver, \</div><div class='ctx'> 		.base = 0xa00, .len = 0xa0,}, \</div><div class='ctx'> 	.csc_blk = {.name = "csc", \</div><div class='del'>-		.id = DPU_SSPP_CSC_10BIT, \</div><div class='ctx'> 		.base = 0x1a00, .len = 0x100,}, \</div><div class='ctx'> 	.format_list = plane_formats_yuv, \</div><div class='ctx'> 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \</div><div class='hunk'>@@ -286,91 +310,64 @@ static const uint32_t wb2_formats[] = {</div><div class='ctx'> 	.rotation_cfg = rot_cfg, \</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-#define _DMA_SBLK(sdma_pri) \</div><div class='add'>+#define _VIG_SBLK_NOSCALE() \</div><div class='add'>+	{ \</div><div class='add'>+	.maxdwnscale = SSPP_UNITY_SCALE, \</div><div class='add'>+	.maxupscale = SSPP_UNITY_SCALE, \</div><div class='add'>+	.format_list = plane_formats_yuv, \</div><div class='add'>+	.num_formats = ARRAY_SIZE(plane_formats_yuv), \</div><div class='add'>+	.virt_format_list = plane_formats, \</div><div class='add'>+	.virt_num_formats = ARRAY_SIZE(plane_formats), \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define _DMA_SBLK() \</div><div class='ctx'> 	{ \</div><div class='ctx'> 	.maxdwnscale = SSPP_UNITY_SCALE, \</div><div class='ctx'> 	.maxupscale = SSPP_UNITY_SCALE, \</div><div class='del'>-	.smart_dma_priority = sdma_pri, \</div><div class='ctx'> 	.format_list = plane_formats, \</div><div class='ctx'> 	.num_formats = ARRAY_SIZE(plane_formats), \</div><div class='ctx'> 	.virt_format_list = plane_formats, \</div><div class='ctx'> 	.virt_num_formats = ARRAY_SIZE(plane_formats), \</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =</div><div class='del'>-				_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =</div><div class='del'>-				_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =</div><div class='del'>-				_VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-</div><div class='ctx'> static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {</div><div class='ctx'> 	.rot_maxheight = 1088,</div><div class='ctx'> 	.rot_num_formats = ARRAY_SIZE(rotation_v2_formats),</div><div class='ctx'> 	.rot_format_list = rotation_v2_formats,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =</div><div class='del'>-				_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =</div><div class='del'>-				_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =</div><div class='del'>-				_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3);</div><div class='del'>-static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =</div><div class='del'>-			_VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &amp;dpu_rot_sc7280_cfg_v2);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =</div><div class='del'>-				_VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =</div><div class='del'>-				_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =</div><div class='del'>-				_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =</div><div class='del'>-				_VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =</div><div class='del'>-				_VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =</div><div class='del'>-				_VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =</div><div class='del'>-				_VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5);</div><div class='del'>-static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6);</div><div class='del'>-</div><div class='del'>-#define _VIG_SBLK_NOSCALE(sdma_pri) \</div><div class='del'>-	{ \</div><div class='del'>-	.maxdwnscale = SSPP_UNITY_SCALE, \</div><div class='del'>-	.maxupscale = SSPP_UNITY_SCALE, \</div><div class='del'>-	.smart_dma_priority = sdma_pri, \</div><div class='del'>-	.format_list = plane_formats_yuv, \</div><div class='del'>-	.num_formats = ARRAY_SIZE(plane_formats_yuv), \</div><div class='del'>-	.virt_format_list = plane_formats, \</div><div class='del'>-	.virt_num_formats = ARRAY_SIZE(plane_formats), \</div><div class='del'>-	}</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale =</div><div class='add'>+				_VIG_SBLK_NOSCALE();</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(1, 2));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(1, 3));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(1, 4));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(2, 4));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(3, 0));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 =</div><div class='add'>+			_VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0),</div><div class='add'>+				      &amp;dpu_rot_sc7280_cfg_v2);</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(3, 1));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(3, 2));</div><div class='add'>+</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =</div><div class='add'>+				_VIG_SBLK(SSPP_SCALER_VER(3, 3));</div><div class='ctx'> </div><div class='del'>-static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2);</div><div class='del'>-static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1);</div><div class='add'>+static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();</div><div class='ctx'> </div><div class='ctx'> /*************************************************************</div><div class='ctx'>  * MIXER sub blocks config</div><div class='hunk'>@@ -422,12 +419,12 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {</div><div class='ctx'>  * DSPP sub blocks config</div><div class='ctx'>  *************************************************************/</div><div class='ctx'> static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {</div><div class='del'>-	.pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700,</div><div class='add'>+	.pcc = {.name = "pcc", .base = 0x1700,</div><div class='ctx'> 		.len = 0x90, .version = 0x10007},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {</div><div class='del'>-	.pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700,</div><div class='add'>+	.pcc = {.name = "pcc", .base = 0x1700,</div><div class='ctx'> 		.len = 0x90, .version = 0x40000},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -435,19 +432,19 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {</div><div class='ctx'>  * PINGPONG sub blocks config</div><div class='ctx'>  *************************************************************/</div><div class='ctx'> static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {</div><div class='del'>-	.te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,</div><div class='add'>+	.te2 = {.name = "te2", .base = 0x2000, .len = 0x0,</div><div class='ctx'> 		.version = 0x1},</div><div class='del'>-	.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0,</div><div class='add'>+	.dither = {.name = "dither", .base = 0x30e0,</div><div class='ctx'> 		.len = 0x20, .version = 0x10000},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {</div><div class='del'>-	.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0,</div><div class='add'>+	.dither = {.name = "dither", .base = 0x30e0,</div><div class='ctx'> 		.len = 0x20, .version = 0x10000},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {</div><div class='del'>-	.dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0,</div><div class='add'>+	.dither = {.name = "dither", .base = 0xe0,</div><div class='ctx'> 	.len = 0x20, .version = 0x20000},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -465,6 +462,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*************************************************************</div><div class='add'>+ * CDM block config</div><div class='add'>+ *************************************************************/</div><div class='add'>+static const struct dpu_cdm_cfg sc7280_cdm = {</div><div class='add'>+	.name = "cdm_0",</div><div class='add'>+	.id = CDM_0,</div><div class='add'>+	.len = 0x228,</div><div class='add'>+	.base = 0x79200,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*************************************************************</div><div class='ctx'>  * VBIF sub blocks config</div><div class='ctx'>  *************************************************************/</div><div class='ctx'> /* VBIF QOS remap */</div><div class='hunk'>@@ -472,6 +479,7 @@ static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};</div><div class='ctx'> static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};</div><div class='ctx'> static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};</div><div class='ctx'> static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};</div><div class='add'>+static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6};</div><div class='ctx'> </div><div class='ctx'> static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {</div><div class='ctx'> 	{</div><div class='hunk'>@@ -558,6 +566,26 @@ static const struct dpu_vbif_cfg sm8550_vbif[] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct dpu_vbif_cfg sm8650_vbif[] = {</div><div class='add'>+	{</div><div class='add'>+	.name = "vbif_rt", .id = VBIF_RT,</div><div class='add'>+	.base = 0, .len = 0x1074,</div><div class='add'>+	.features = BIT(DPU_VBIF_QOS_REMAP),</div><div class='add'>+	.xin_halt_timeout = 0x4000,</div><div class='add'>+	.qos_rp_remap_size = 0x40,</div><div class='add'>+	.qos_rt_tbl = {</div><div class='add'>+		.npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),</div><div class='add'>+		.priority_lvl = sm8650_rt_pri_lvl,</div><div class='add'>+		},</div><div class='add'>+	.qos_nrt_tbl = {</div><div class='add'>+		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),</div><div class='add'>+		.priority_lvl = sdm845_nrt_pri_lvl,</div><div class='add'>+		},</div><div class='add'>+	.memtype_count = 16,</div><div class='add'>+	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*************************************************************</div><div class='ctx'>  * PERF data config</div><div class='ctx'>  *************************************************************/</div><div class='hunk'>@@ -654,6 +682,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {</div><div class='ctx'> #include "catalog/dpu_3_0_msm8998.h"</div><div class='ctx'> </div><div class='ctx'> #include "catalog/dpu_4_0_sdm845.h"</div><div class='add'>+#include "catalog/dpu_4_1_sdm670.h"</div><div class='ctx'> </div><div class='ctx'> #include "catalog/dpu_5_0_sm8150.h"</div><div class='ctx'> #include "catalog/dpu_5_1_sc8180x.h"</div><div class='hunk'>@@ -673,3 +702,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {</div><div class='ctx'> #include "catalog/dpu_8_1_sm8450.h"</div><div class='ctx'> </div><div class='ctx'> #include "catalog/dpu_9_0_sm8550.h"</div><div class='add'>+</div><div class='add'>+#include "catalog/dpu_10_0_sm8650.h"</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h<br/>index df024e10d3a3..ba82ef4560a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h</a></div><div class='hunk'>@@ -51,9 +51,7 @@ enum {</div><div class='ctx'> /**</div><div class='ctx'>  * SSPP sub-blocks/features</div><div class='ctx'>  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support</div><div class='del'>- * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support</div><div class='del'>- * @DPU_SSPP_SCALER_QSEED3LITE,  QSEED3 Lite alogorithm support</div><div class='del'>- * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support</div><div class='add'>+ * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE,  QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4)</div><div class='ctx'>  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes</div><div class='ctx'>  * @DPU_SSPP_CSC,            Support of Color space converion</div><div class='ctx'>  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion</div><div class='hunk'>@@ -71,9 +69,7 @@ enum {</div><div class='ctx'>  */</div><div class='ctx'> enum {</div><div class='ctx'> 	DPU_SSPP_SCALER_QSEED2 = 0x1,</div><div class='del'>-	DPU_SSPP_SCALER_QSEED3,</div><div class='del'>-	DPU_SSPP_SCALER_QSEED3LITE,</div><div class='del'>-	DPU_SSPP_SCALER_QSEED4,</div><div class='add'>+	DPU_SSPP_SCALER_QSEED3_COMPATIBLE,</div><div class='ctx'> 	DPU_SSPP_SCALER_RGB,</div><div class='ctx'> 	DPU_SSPP_CSC,</div><div class='ctx'> 	DPU_SSPP_CSC_10BIT,</div><div class='hunk'>@@ -249,49 +245,50 @@ enum {</div><div class='ctx'> 	unsigned long features</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU</div><div class='del'>- * @name:              string name for debug purposes</div><div class='del'>- * @id:                enum identifying this sub-block</div><div class='del'>- * @base:              offset of this sub-block relative to the block</div><div class='del'>- *                     offset</div><div class='del'>- * @len                register block length of this sub-block</div><div class='del'>- */</div><div class='del'>-#define DPU_HW_SUBBLK_INFO \</div><div class='del'>-	char name[DPU_HW_BLK_NAME_LEN]; \</div><div class='del'>-	u32 id; \</div><div class='del'>-	u32 base; \</div><div class='del'>-	u32 len</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * struct dpu_scaler_blk: Scaler information</div><div class='del'>- * @info:   HW register and features supported by this sub-blk</div><div class='del'>- * @version: qseed block revision</div><div class='add'>+ * @name: string name for debug purposes</div><div class='add'>+ * @base: offset of this sub-block relative to the block offset</div><div class='add'>+ * @len: register block length of this sub-block</div><div class='add'>+ * @version: qseed block revision, on QSEED3+ platforms this is the value of</div><div class='add'>+ *           scaler_blk.base + QSEED3_HW_VERSION registers.</div><div class='ctx'>  */</div><div class='ctx'> struct dpu_scaler_blk {</div><div class='del'>-	DPU_HW_SUBBLK_INFO;</div><div class='add'>+	char name[DPU_HW_BLK_NAME_LEN];</div><div class='add'>+	u32 base;</div><div class='add'>+	u32 len;</div><div class='ctx'> 	u32 version;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dpu_csc_blk {</div><div class='del'>-	DPU_HW_SUBBLK_INFO;</div><div class='add'>+	char name[DPU_HW_BLK_NAME_LEN];</div><div class='add'>+	u32 base;</div><div class='add'>+	u32 len;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct dpu_pp_blk : Pixel processing sub-blk information</div><div class='del'>- * @info:   HW register and features supported by this sub-blk</div><div class='add'>+ * @name: string name for debug purposes</div><div class='add'>+ * @base: offset of this sub-block relative to the block offset</div><div class='add'>+ * @len: register block length of this sub-block</div><div class='ctx'>  * @version: HW Algorithm version</div><div class='ctx'>  */</div><div class='ctx'> struct dpu_pp_blk {</div><div class='del'>-	DPU_HW_SUBBLK_INFO;</div><div class='add'>+	char name[DPU_HW_BLK_NAME_LEN];</div><div class='add'>+	u32 base;</div><div class='add'>+	u32 len;</div><div class='ctx'> 	u32 version;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct dpu_dsc_blk - DSC Encoder sub-blk information</div><div class='del'>- * @info:   HW register and features supported by this sub-blk</div><div class='add'>+ * @name: string name for debug purposes</div><div class='add'>+ * @base: offset of this sub-block relative to the block offset</div><div class='add'>+ * @len: register block length of this sub-block</div><div class='ctx'>  */</div><div class='ctx'> struct dpu_dsc_blk {</div><div class='del'>-	DPU_HW_SUBBLK_INFO;</div><div class='add'>+	char name[DPU_HW_BLK_NAME_LEN];</div><div class='add'>+	u32 base;</div><div class='add'>+	u32 len;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -341,7 +338,6 @@ struct dpu_rotation_cfg {</div><div class='ctx'>  * @max_mixer_width    max layer mixer line width support.</div><div class='ctx'>  * @max_mixer_blendstages max layer mixer blend stages or</div><div class='ctx'>  *                       supported z order</div><div class='del'>- * @qseed_type         qseed2 or qseed3 support.</div><div class='ctx'>  * @has_src_split      source split feature status</div><div class='ctx'>  * @has_dim_layer      dim layer feature status</div><div class='ctx'>  * @has_idle_pc        indicate if idle power collapse feature is supported</div><div class='hunk'>@@ -354,7 +350,6 @@ struct dpu_rotation_cfg {</div><div class='ctx'> struct dpu_caps {</div><div class='ctx'> 	u32 max_mixer_width;</div><div class='ctx'> 	u32 max_mixer_blendstages;</div><div class='del'>-	u32 qseed_type;</div><div class='ctx'> 	bool has_src_split;</div><div class='ctx'> 	bool has_dim_layer;</div><div class='ctx'> 	bool has_idle_pc;</div><div class='hunk'>@@ -371,7 +366,6 @@ struct dpu_caps {</div><div class='ctx'>  * common: Pointer to common configurations shared by sub blocks</div><div class='ctx'>  * @maxdwnscale: max downscale ratio supported(without DECIMATION)</div><div class='ctx'>  * @maxupscale:  maxupscale ratio supported</div><div class='del'>- * @smart_dma_priority: hw priority of rect1 of multirect pipe</div><div class='ctx'>  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps</div><div class='ctx'>  * @qseed_ver: qseed version</div><div class='ctx'>  * @scaler_blk:</div><div class='hunk'>@@ -385,7 +379,6 @@ struct dpu_caps {</div><div class='ctx'> struct dpu_sspp_sub_blks {</div><div class='ctx'> 	u32 maxdwnscale;</div><div class='ctx'> 	u32 maxupscale;</div><div class='del'>-	u32 smart_dma_priority;</div><div class='ctx'> 	u32 max_per_pipe_bw;</div><div class='ctx'> 	u32 qseed_ver;</div><div class='ctx'> 	struct dpu_scaler_blk scaler_blk;</div><div class='hunk'>@@ -690,6 +683,17 @@ struct dpu_vbif_cfg {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct dpu_cdm_cfg - information of chroma down blocks</div><div class='add'>+ * @name               string name for debug purposes</div><div class='add'>+ * @id                 enum identifying this block</div><div class='add'>+ * @base               register offset of this block</div><div class='add'>+ * @features           bit mask identifying sub-blocks/features</div><div class='add'>+ */</div><div class='add'>+struct dpu_cdm_cfg {</div><div class='add'>+	DPU_HW_BLK_INFO;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * Define CDP use cases</div><div class='ctx'>  * @DPU_PERF_CDP_UDAGE_RT: real-time use cases</div><div class='ctx'>  * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD</div><div class='hunk'>@@ -812,6 +816,8 @@ struct dpu_mdss_cfg {</div><div class='ctx'> 	u32 wb_count;</div><div class='ctx'> 	const struct dpu_wb_cfg *wb;</div><div class='ctx'> </div><div class='add'>+	const struct dpu_cdm_cfg *cdm;</div><div class='add'>+</div><div class='ctx'> 	u32 ad_count;</div><div class='ctx'> </div><div class='ctx'> 	u32 dspp_count;</div><div class='hunk'>@@ -827,6 +833,7 @@ struct dpu_mdss_cfg {</div><div class='ctx'> </div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_msm8998_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sdm845_cfg;</div><div class='add'>+extern const struct dpu_mdss_cfg dpu_sdm670_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sm8150_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sm8250_cfg;</div><div class='hunk'>@@ -841,5 +848,6 @@ extern const struct dpu_mdss_cfg dpu_sc7280_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sm8450_cfg;</div><div class='ctx'> extern const struct dpu_mdss_cfg dpu_sm8550_cfg;</div><div class='add'>+extern const struct dpu_mdss_cfg dpu_sm8650_cfg;</div><div class='ctx'> </div><div class='ctx'> #endif /* _DPU_HW_CATALOG_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c<br/>new file mode 100644<br/>index 000000000000..e9cdc7934a49<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c</a></div><div class='hunk'>@@ -0,0 +1,247 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dpu_hw_mdss.h"</div><div class='add'>+#include "dpu_hw_util.h"</div><div class='add'>+#include "dpu_hw_catalog.h"</div><div class='add'>+#include "dpu_hw_cdm.h"</div><div class='add'>+#include "dpu_kms.h"</div><div class='add'>+</div><div class='add'>+#define CDM_CSC_10_OPMODE                  0x000</div><div class='add'>+#define CDM_CSC_10_BASE                    0x004</div><div class='add'>+</div><div class='add'>+#define CDM_CDWN2_OP_MODE                  0x100</div><div class='add'>+#define CDM_CDWN2_CLAMP_OUT                0x104</div><div class='add'>+#define CDM_CDWN2_PARAMS_3D_0              0x108</div><div class='add'>+#define CDM_CDWN2_PARAMS_3D_1              0x10C</div><div class='add'>+#define CDM_CDWN2_COEFF_COSITE_H_0         0x110</div><div class='add'>+#define CDM_CDWN2_COEFF_COSITE_H_1         0x114</div><div class='add'>+#define CDM_CDWN2_COEFF_COSITE_H_2         0x118</div><div class='add'>+#define CDM_CDWN2_COEFF_OFFSITE_H_0        0x11C</div><div class='add'>+#define CDM_CDWN2_COEFF_OFFSITE_H_1        0x120</div><div class='add'>+#define CDM_CDWN2_COEFF_OFFSITE_H_2        0x124</div><div class='add'>+#define CDM_CDWN2_COEFF_COSITE_V           0x128</div><div class='add'>+#define CDM_CDWN2_COEFF_OFFSITE_V          0x12C</div><div class='add'>+#define CDM_CDWN2_OUT_SIZE                 0x130</div><div class='add'>+</div><div class='add'>+#define CDM_HDMI_PACK_OP_MODE              0x200</div><div class='add'>+#define CDM_CSC_10_MATRIX_COEFF_0          0x004</div><div class='add'>+</div><div class='add'>+#define CDM_MUX                            0x224</div><div class='add'>+</div><div class='add'>+/* CDM CDWN2 sub-block bit definitions */</div><div class='add'>+#define CDM_CDWN2_OP_MODE_EN                  BIT(0)</div><div class='add'>+#define CDM_CDWN2_OP_MODE_ENABLE_H            BIT(1)</div><div class='add'>+#define CDM_CDWN2_OP_MODE_ENABLE_V            BIT(2)</div><div class='add'>+#define CDM_CDWN2_OP_MODE_BITS_OUT_8BIT       BIT(7)</div><div class='add'>+#define CDM_CDWN2_V_PIXEL_METHOD_MASK         GENMASK(6, 5)</div><div class='add'>+#define CDM_CDWN2_H_PIXEL_METHOD_MASK         GENMASK(4, 3)</div><div class='add'>+</div><div class='add'>+/* CDM CSC10 sub-block bit definitions */</div><div class='add'>+#define CDM_CSC10_OP_MODE_EN               BIT(0)</div><div class='add'>+#define CDM_CSC10_OP_MODE_SRC_FMT_YUV      BIT(1)</div><div class='add'>+#define CDM_CSC10_OP_MODE_DST_FMT_YUV      BIT(2)</div><div class='add'>+</div><div class='add'>+/* CDM HDMI pack sub-block bit definitions */</div><div class='add'>+#define CDM_HDMI_PACK_OP_MODE_EN           BIT(0)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Horizontal coefficients for cosite chroma downscale</div><div class='add'>+ * s13 representation of coefficients</div><div class='add'>+ */</div><div class='add'>+static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Horizontal coefficients for offsite chroma downscale</div><div class='add'>+ */</div><div class='add'>+static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Vertical coefficients for cosite chroma downscale</div><div class='add'>+ */</div><div class='add'>+static u32 cosite_v_coeff[] = {0x00080004};</div><div class='add'>+/*</div><div class='add'>+ * Vertical coefficients for offsite chroma downscale</div><div class='add'>+ */</div><div class='add'>+static u32 offsite_v_coeff[] = {0x00060002};</div><div class='add'>+</div><div class='add'>+static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cfg)</div><div class='add'>+{</div><div class='add'>+	struct dpu_hw_blk_reg_map *c = &amp;ctx-&gt;hw;</div><div class='add'>+	u32 opmode;</div><div class='add'>+	u32 out_size;</div><div class='add'>+</div><div class='add'>+	switch (cfg-&gt;h_cdwn_type) {</div><div class='add'>+	case CDM_CDWN_DISABLE:</div><div class='add'>+		opmode = 0;</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_PIXEL_DROP:</div><div class='add'>+		opmode = CDM_CDWN2_OP_MODE_ENABLE_H |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_PIXEL_DROP);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_AVG:</div><div class='add'>+		opmode = CDM_CDWN2_OP_MODE_ENABLE_H |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_AVG);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_COSITE:</div><div class='add'>+		opmode = CDM_CDWN2_OP_MODE_ENABLE_H |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_COSITE);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,</div><div class='add'>+			      cosite_h_coeff[0]);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,</div><div class='add'>+			      cosite_h_coeff[1]);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,</div><div class='add'>+			      cosite_h_coeff[2]);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_OFFSITE:</div><div class='add'>+		opmode = CDM_CDWN2_OP_MODE_ENABLE_H |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_H_PIXEL_METHOD_MASK, CDM_CDWN2_METHOD_OFFSITE);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,</div><div class='add'>+			      offsite_h_coeff[0]);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,</div><div class='add'>+			      offsite_h_coeff[1]);</div><div class='add'>+		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,</div><div class='add'>+			      offsite_h_coeff[2]);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		DPU_ERROR("%s invalid horz down sampling type\n", __func__);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (cfg-&gt;v_cdwn_type) {</div><div class='add'>+	case CDM_CDWN_DISABLE:</div><div class='add'>+		/* if its only Horizontal downsample, we dont need to do anything here */</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_PIXEL_DROP:</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_PIXEL_DROP);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_AVG:</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_AVG);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_COSITE:</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_COSITE);</div><div class='add'>+		DPU_REG_WRITE(c,</div><div class='add'>+			      CDM_CDWN2_COEFF_COSITE_V,</div><div class='add'>+			      cosite_v_coeff[0]);</div><div class='add'>+		break;</div><div class='add'>+	case CDM_CDWN_OFFSITE:</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_ENABLE_V |</div><div class='add'>+				FIELD_PREP(CDM_CDWN2_V_PIXEL_METHOD_MASK,</div><div class='add'>+					   CDM_CDWN2_METHOD_OFFSITE);</div><div class='add'>+		DPU_REG_WRITE(c,</div><div class='add'>+			      CDM_CDWN2_COEFF_OFFSITE_V,</div><div class='add'>+			      offsite_v_coeff[0]);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;output_bit_depth != CDM_CDWN_OUTPUT_10BIT)</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_BITS_OUT_8BIT;</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;v_cdwn_type || cfg-&gt;h_cdwn_type)</div><div class='add'>+		opmode |= CDM_CDWN2_OP_MODE_EN; /* EN CDWN module */</div><div class='add'>+	else</div><div class='add'>+		opmode &amp;= ~CDM_CDWN2_OP_MODE_EN;</div><div class='add'>+</div><div class='add'>+	out_size = (cfg-&gt;output_width &amp; 0xFFFF) | ((cfg-&gt;output_height &amp; 0xFFFF) &lt;&lt; 16);</div><div class='add'>+	DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);</div><div class='add'>+	DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);</div><div class='add'>+	DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT, ((0x3FF &lt;&lt; 16) | 0x0));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)</div><div class='add'>+{</div><div class='add'>+	struct dpu_hw_blk_reg_map *c = &amp;ctx-&gt;hw;</div><div class='add'>+	const struct dpu_format *fmt;</div><div class='add'>+	u32 opmode = 0;</div><div class='add'>+	u32 csc = 0;</div><div class='add'>+</div><div class='add'>+	if (!ctx || !cdm)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fmt = cdm-&gt;output_fmt;</div><div class='add'>+</div><div class='add'>+	if (!DPU_FORMAT_IS_YUV(fmt))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dpu_hw_csc_setup(&amp;ctx-&gt;hw, CDM_CSC_10_MATRIX_COEFF_0, cdm-&gt;csc_cfg, true);</div><div class='add'>+	dpu_hw_cdm_setup_cdwn(ctx, cdm);</div><div class='add'>+</div><div class='add'>+	if (cdm-&gt;output_type == CDM_CDWN_OUTPUT_HDMI) {</div><div class='add'>+		if (fmt-&gt;chroma_sample != DPU_CHROMA_H1V2)</div><div class='add'>+			return -EINVAL; /*unsupported format */</div><div class='add'>+		opmode = CDM_HDMI_PACK_OP_MODE_EN;</div><div class='add'>+		opmode |= (fmt-&gt;chroma_sample &lt;&lt; 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	csc |= CDM_CSC10_OP_MODE_DST_FMT_YUV;</div><div class='add'>+	csc &amp;= ~CDM_CSC10_OP_MODE_SRC_FMT_YUV;</div><div class='add'>+	csc |= CDM_CSC10_OP_MODE_EN;</div><div class='add'>+</div><div class='add'>+	if (ctx &amp;&amp; ctx-&gt;ops.bind_pingpong_blk)</div><div class='add'>+		ctx-&gt;ops.bind_pingpong_blk(ctx, cdm-&gt;pp_id);</div><div class='add'>+</div><div class='add'>+	DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);</div><div class='add'>+	DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dpu_hw_cdm_bind_pingpong_blk(struct dpu_hw_cdm *ctx, const enum dpu_pingpong pp)</div><div class='add'>+{</div><div class='add'>+	struct dpu_hw_blk_reg_map *c;</div><div class='add'>+	int mux_cfg;</div><div class='add'>+</div><div class='add'>+	c = &amp;ctx-&gt;hw;</div><div class='add'>+</div><div class='add'>+	mux_cfg = DPU_REG_READ(c, CDM_MUX);</div><div class='add'>+	mux_cfg &amp;= ~0xf;</div><div class='add'>+</div><div class='add'>+	if (pp)</div><div class='add'>+		mux_cfg |= (pp - PINGPONG_0) &amp; 0x7;</div><div class='add'>+	else</div><div class='add'>+		mux_cfg |= 0xf;</div><div class='add'>+</div><div class='add'>+	DPU_REG_WRITE(c, CDM_MUX, mux_cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_cdm_cfg *cfg, void __iomem *addr,</div><div class='add'>+				   const struct dpu_mdss_version *mdss_rev)</div><div class='add'>+{</div><div class='add'>+	struct dpu_hw_cdm *c;</div><div class='add'>+</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='add'>+	if (!c)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	c-&gt;hw.blk_addr = addr + cfg-&gt;base;</div><div class='add'>+	c-&gt;hw.log_mask = DPU_DBG_MASK_CDM;</div><div class='add'>+</div><div class='add'>+	/* Assign ops */</div><div class='add'>+	c-&gt;idx = cfg-&gt;id;</div><div class='add'>+	c-&gt;caps = cfg;</div><div class='add'>+</div><div class='add'>+	c-&gt;ops.enable = dpu_hw_cdm_enable;</div><div class='add'>+	if (mdss_rev-&gt;core_major_ver &gt;= 5)</div><div class='add'>+		c-&gt;ops.bind_pingpong_blk = dpu_hw_cdm_bind_pingpong_blk;</div><div class='add'>+</div><div class='add'>+	return c;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h<br/>new file mode 100644<br/>index 000000000000..348424df87c6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h</a></div><div class='hunk'>@@ -0,0 +1,142 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DPU_HW_CDM_H</div><div class='add'>+#define _DPU_HW_CDM_H</div><div class='add'>+</div><div class='add'>+#include "dpu_hw_mdss.h"</div><div class='add'>+#include "dpu_hw_top.h"</div><div class='add'>+</div><div class='add'>+struct dpu_hw_cdm;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dpu_hw_cdm_cfg : current configuration of CDM block</div><div class='add'>+ *</div><div class='add'>+ *  @output_width:         output ROI width of CDM block</div><div class='add'>+ *  @output_height:        output ROI height of CDM block</div><div class='add'>+ *  @output_bit_depth:     output bit-depth of CDM block</div><div class='add'>+ *  @h_cdwn_type:          downsample type used for horizontal pixels</div><div class='add'>+ *  @v_cdwn_type:          downsample type used for vertical pixels</div><div class='add'>+ *  @output_fmt:           handle to dpu_format of CDM block</div><div class='add'>+ *  @csc_cfg:              handle to CSC matrix programmed for CDM block</div><div class='add'>+ *  @output_type:          interface to which CDM is paired (HDMI/WB)</div><div class='add'>+ *  @pp_id:                ping-pong block to which CDM is bound to</div><div class='add'>+ */</div><div class='add'>+struct dpu_hw_cdm_cfg {</div><div class='add'>+	u32 output_width;</div><div class='add'>+	u32 output_height;</div><div class='add'>+	u32 output_bit_depth;</div><div class='add'>+	u32 h_cdwn_type;</div><div class='add'>+	u32 v_cdwn_type;</div><div class='add'>+	const struct dpu_format *output_fmt;</div><div class='add'>+	const struct dpu_csc_cfg *csc_cfg;</div><div class='add'>+	u32 output_type;</div><div class='add'>+	int pp_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * These values are used indicate which type of downsample is used</div><div class='add'>+ * in the horizontal/vertical direction for the CDM block.</div><div class='add'>+ */</div><div class='add'>+enum dpu_hw_cdwn_type {</div><div class='add'>+	CDM_CDWN_DISABLE,</div><div class='add'>+	CDM_CDWN_PIXEL_DROP,</div><div class='add'>+	CDM_CDWN_AVG,</div><div class='add'>+	CDM_CDWN_COSITE,</div><div class='add'>+	CDM_CDWN_OFFSITE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * CDM block can be paired with WB or HDMI block. These values match</div><div class='add'>+ * the input with which the CDM block is paired.</div><div class='add'>+ */</div><div class='add'>+enum dpu_hw_cdwn_output_type {</div><div class='add'>+	CDM_CDWN_OUTPUT_HDMI,</div><div class='add'>+	CDM_CDWN_OUTPUT_WB,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * CDM block can give an 8-bit or 10-bit output. These values</div><div class='add'>+ * are used to indicate the output bit depth of CDM block</div><div class='add'>+ */</div><div class='add'>+enum dpu_hw_cdwn_output_bit_depth {</div><div class='add'>+	CDM_CDWN_OUTPUT_8BIT,</div><div class='add'>+	CDM_CDWN_OUTPUT_10BIT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * CDM block can downsample using different methods. These values</div><div class='add'>+ * are used to indicate the downsample method which can be used</div><div class='add'>+ * either in the horizontal or vertical direction.</div><div class='add'>+ */</div><div class='add'>+enum dpu_hw_cdwn_op_mode_method_h_v {</div><div class='add'>+	CDM_CDWN2_METHOD_PIXEL_DROP,</div><div class='add'>+	CDM_CDWN2_METHOD_AVG,</div><div class='add'>+	CDM_CDWN2_METHOD_COSITE,</div><div class='add'>+	CDM_CDWN2_METHOD_OFFSITE</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dpu_hw_cdm_ops : Interface to the chroma down Hw driver functions</div><div class='add'>+ *                         Assumption is these functions will be called after</div><div class='add'>+ *                         clocks are enabled</div><div class='add'>+ *  @enable:               Enables the output to interface and programs the</div><div class='add'>+ *                         output packer</div><div class='add'>+ *  @bind_pingpong_blk:    enable/disable the connection with pingpong which</div><div class='add'>+ *                         will feed pixels to this cdm</div><div class='add'>+ */</div><div class='add'>+struct dpu_hw_cdm_ops {</div><div class='add'>+	/**</div><div class='add'>+	 * Enable the CDM module</div><div class='add'>+	 * @cdm         Pointer to chroma down context</div><div class='add'>+	 */</div><div class='add'>+	int (*enable)(struct dpu_hw_cdm *cdm, struct dpu_hw_cdm_cfg *cfg);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * Enable/disable the connection with pingpong</div><div class='add'>+	 * @cdm         Pointer to chroma down context</div><div class='add'>+	 * @pp          pingpong block id.</div><div class='add'>+	 */</div><div class='add'>+	void (*bind_pingpong_blk)(struct dpu_hw_cdm *cdm, const enum dpu_pingpong pp);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dpu_hw_cdm - cdm description</div><div class='add'>+ * @base: Hardware block base structure</div><div class='add'>+ * @hw: Block hardware details</div><div class='add'>+ * @idx: CDM index</div><div class='add'>+ * @caps: Pointer to cdm_cfg</div><div class='add'>+ * @ops: handle to operations possible for this CDM</div><div class='add'>+ */</div><div class='add'>+struct dpu_hw_cdm {</div><div class='add'>+	struct dpu_hw_blk base;</div><div class='add'>+	struct dpu_hw_blk_reg_map hw;</div><div class='add'>+</div><div class='add'>+	/* chroma down */</div><div class='add'>+	const struct dpu_cdm_cfg *caps;</div><div class='add'>+	enum  dpu_cdm  idx;</div><div class='add'>+</div><div class='add'>+	/* ops */</div><div class='add'>+	struct dpu_hw_cdm_ops ops;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dpu_hw_cdm_init - initializes the cdm hw driver object.</div><div class='add'>+ * should be called once before accessing every cdm.</div><div class='add'>+ * @dev: DRM device handle</div><div class='add'>+ * @cdm: CDM catalog entry for which driver object is required</div><div class='add'>+ * @addr :   mapped register io address of MDSS</div><div class='add'>+ * @mdss_rev: mdss hw core revision</div><div class='add'>+ */</div><div class='add'>+struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_cdm_cfg *cdm, void __iomem *addr,</div><div class='add'>+				   const struct dpu_mdss_version *mdss_rev);</div><div class='add'>+</div><div class='add'>+static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)</div><div class='add'>+{</div><div class='add'>+	return container_of(hw, struct dpu_hw_cdm, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /*_DPU_HW_CDM_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c<br/>index 86182c734606..e76565c3e6a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c</a></div><div class='hunk'>@@ -4,6 +4,9 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_ctl.h"</div><div class='ctx'> #include "dpu_kms.h"</div><div class='hunk'>@@ -29,11 +32,13 @@</div><div class='ctx'> #define   CTL_DSC_ACTIVE                0x0E8</div><div class='ctx'> #define   CTL_WB_ACTIVE                 0x0EC</div><div class='ctx'> #define   CTL_INTF_ACTIVE               0x0F4</div><div class='add'>+#define   CTL_CDM_ACTIVE                0x0F8</div><div class='ctx'> #define   CTL_FETCH_PIPE_ACTIVE         0x0FC</div><div class='ctx'> #define   CTL_MERGE_3D_FLUSH            0x100</div><div class='ctx'> #define   CTL_DSC_FLUSH                0x104</div><div class='ctx'> #define   CTL_WB_FLUSH                  0x108</div><div class='ctx'> #define   CTL_INTF_FLUSH                0x110</div><div class='add'>+#define   CTL_CDM_FLUSH                0x114</div><div class='ctx'> #define   CTL_INTF_MASTER               0x134</div><div class='ctx'> #define   CTL_DSPP_n_FLUSH(n)           ((0x13C) + ((n) * 4))</div><div class='ctx'> </div><div class='hunk'>@@ -43,6 +48,7 @@</div><div class='ctx'> #define DPU_REG_RESET_TIMEOUT_US        2000</div><div class='ctx'> #define  MERGE_3D_IDX   23</div><div class='ctx'> #define  DSC_IDX        22</div><div class='add'>+#define CDM_IDX         26</div><div class='ctx'> #define  INTF_IDX       31</div><div class='ctx'> #define WB_IDX          16</div><div class='ctx'> #define  DSPP_IDX       29  /* From DPU hw rev 7.x.x */</div><div class='hunk'>@@ -104,6 +110,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)</div><div class='ctx'> 	ctx-&gt;pending_wb_flush_mask = 0;</div><div class='ctx'> 	ctx-&gt;pending_merge_3d_flush_mask = 0;</div><div class='ctx'> 	ctx-&gt;pending_dsc_flush_mask = 0;</div><div class='add'>+	ctx-&gt;pending_cdm_flush_mask = 0;</div><div class='ctx'> </div><div class='ctx'> 	memset(ctx-&gt;pending_dspp_flush_mask, 0,</div><div class='ctx'> 		sizeof(ctx-&gt;pending_dspp_flush_mask));</div><div class='hunk'>@@ -148,6 +155,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)</div><div class='ctx'> 		DPU_REG_WRITE(&amp;ctx-&gt;hw, CTL_DSC_FLUSH,</div><div class='ctx'> 			      ctx-&gt;pending_dsc_flush_mask);</div><div class='ctx'> </div><div class='add'>+	if (ctx-&gt;pending_flush_mask &amp; BIT(CDM_IDX))</div><div class='add'>+		DPU_REG_WRITE(&amp;ctx-&gt;hw, CTL_CDM_FLUSH,</div><div class='add'>+			      ctx-&gt;pending_cdm_flush_mask);</div><div class='add'>+</div><div class='ctx'> 	DPU_REG_WRITE(&amp;ctx-&gt;hw, CTL_FLUSH, ctx-&gt;pending_flush_mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -279,6 +290,13 @@ static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)</div><div class='add'>+{</div><div class='add'>+	/* update pending flush only if CDM_0 is flushed */</div><div class='add'>+	if (cdm_num == CDM_0)</div><div class='add'>+		ctx-&gt;pending_flush_mask |= BIT(CDM_IDX);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 		enum dpu_wb wb)</div><div class='ctx'> {</div><div class='hunk'>@@ -307,6 +325,12 @@ static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 	ctx-&gt;pending_flush_mask |= BIT(DSC_IDX);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)</div><div class='add'>+{</div><div class='add'>+	ctx-&gt;pending_cdm_flush_mask |= BIT(cdm_num - CDM_0);</div><div class='add'>+	ctx-&gt;pending_flush_mask |= BIT(CDM_IDX);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 	enum dpu_dspp dspp, u32 dspp_sub_blk)</div><div class='ctx'> {</div><div class='hunk'>@@ -540,6 +564,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,</div><div class='ctx'> </div><div class='ctx'> 	if (cfg-&gt;dsc)</div><div class='ctx'> 		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg-&gt;dsc);</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;cdm)</div><div class='add'>+		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg-&gt;cdm);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,</div><div class='hunk'>@@ -583,6 +610,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 	u32 wb_active = 0;</div><div class='ctx'> 	u32 merge3d_active = 0;</div><div class='ctx'> 	u32 dsc_active;</div><div class='add'>+	u32 cdm_active;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * This API resets each portion of the CTL path namely,</div><div class='hunk'>@@ -618,6 +646,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,</div><div class='ctx'> 		dsc_active &amp;= ~cfg-&gt;dsc;</div><div class='ctx'> 		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;cdm) {</div><div class='add'>+		cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE);</div><div class='add'>+		cdm_active &amp;= ~cfg-&gt;cdm;</div><div class='add'>+		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,</div><div class='hunk'>@@ -651,12 +685,14 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,</div><div class='ctx'> 		ops-&gt;update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;</div><div class='ctx'> 		ops-&gt;update_pending_flush_dsc =</div><div class='ctx'> 			dpu_hw_ctl_update_pending_flush_dsc_v1;</div><div class='add'>+		ops-&gt;update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ops-&gt;trigger_flush = dpu_hw_ctl_trigger_flush;</div><div class='ctx'> 		ops-&gt;setup_intf_cfg = dpu_hw_ctl_intf_cfg;</div><div class='ctx'> 		ops-&gt;update_pending_flush_intf =</div><div class='ctx'> 			dpu_hw_ctl_update_pending_flush_intf;</div><div class='ctx'> 		ops-&gt;update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;</div><div class='add'>+		ops-&gt;update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;</div><div class='ctx'> 	}</div><div class='ctx'> 	ops-&gt;clear_pending_flush = dpu_hw_ctl_clear_pending_flush;</div><div class='ctx'> 	ops-&gt;update_pending_flush = dpu_hw_ctl_update_pending_flush;</div><div class='hunk'>@@ -680,14 +716,15 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,</div><div class='ctx'> 		ops-&gt;set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_ctl *dpu_hw_ctl_init(const struct dpu_ctl_cfg *cfg,</div><div class='del'>-		void __iomem *addr,</div><div class='del'>-		u32 mixer_count,</div><div class='del'>-		const struct dpu_lm_cfg *mixer)</div><div class='add'>+struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_ctl_cfg *cfg,</div><div class='add'>+				   void __iomem *addr,</div><div class='add'>+				   u32 mixer_count,</div><div class='add'>+				   const struct dpu_lm_cfg *mixer)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_ctl *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -702,8 +739,3 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(const struct dpu_ctl_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)</div><div class='del'>-{</div><div class='del'>-	kfree(ctx);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h<br/>index 1c242298ff2e..ff85b5ee0acf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h</a></div><div class='hunk'>@@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg {</div><div class='ctx'>  * @mode_3d:               3d mux configuration</div><div class='ctx'>  * @merge_3d:              3d merge block used</div><div class='ctx'>  * @intf_mode_sel:         Interface mode, cmd / vid</div><div class='add'>+ * @cdm:                   CDM block used</div><div class='ctx'>  * @stream_sel:            Stream selection for multi-stream interfaces</div><div class='ctx'>  * @dsc:                   DSC BIT masks used</div><div class='ctx'>  */</div><div class='hunk'>@@ -48,6 +49,7 @@ struct dpu_hw_intf_cfg {</div><div class='ctx'> 	enum dpu_3d_blend_mode mode_3d;</div><div class='ctx'> 	enum dpu_merge_3d merge_3d;</div><div class='ctx'> 	enum dpu_ctl_mode_sel intf_mode_sel;</div><div class='add'>+	enum dpu_cdm cdm;</div><div class='ctx'> 	int stream_sel;</div><div class='ctx'> 	unsigned int dsc;</div><div class='ctx'> };</div><div class='hunk'>@@ -167,6 +169,14 @@ struct dpu_hw_ctl_ops {</div><div class='ctx'> 					 enum dpu_dsc blk);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='add'>+	 * OR in the given flushbits to the cached pending_(cdm_)flush_mask</div><div class='add'>+	 * No effect on hardware</div><div class='add'>+	 * @ctx: ctl path ctx pointer</div><div class='add'>+	 * @cdm_num: idx of cdm to be flushed</div><div class='add'>+	 */</div><div class='add'>+	void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='ctx'> 	 * Write the value of the pending_flush_mask to hardware</div><div class='ctx'> 	 * @ctx       : ctl path ctx pointer</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -239,6 +249,7 @@ struct dpu_hw_ctl_ops {</div><div class='ctx'>  * @pending_intf_flush_mask: pending INTF flush</div><div class='ctx'>  * @pending_wb_flush_mask: pending WB flush</div><div class='ctx'>  * @pending_dsc_flush_mask: pending DSC flush</div><div class='add'>+ * @pending_cdm_flush_mask: pending CDM flush</div><div class='ctx'>  * @ops: operation list</div><div class='ctx'>  */</div><div class='ctx'> struct dpu_hw_ctl {</div><div class='hunk'>@@ -256,6 +267,7 @@ struct dpu_hw_ctl {</div><div class='ctx'> 	u32 pending_merge_3d_flush_mask;</div><div class='ctx'> 	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];</div><div class='ctx'> 	u32 pending_dsc_flush_mask;</div><div class='add'>+	u32 pending_cdm_flush_mask;</div><div class='ctx'> </div><div class='ctx'> 	/* ops */</div><div class='ctx'> 	struct dpu_hw_ctl_ops ops;</div><div class='hunk'>@@ -274,20 +286,16 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.</div><div class='ctx'>  * Should be called before accessing any ctl_path register.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  ctl_path catalog entry for which driver object is required</div><div class='ctx'>  * @addr: mapped register io address of MDP</div><div class='ctx'>  * @mixer_count: Number of mixers in @mixer</div><div class='ctx'>  * @mixer: Pointer to an array of Layer Mixers defined in the catalog</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_ctl *dpu_hw_ctl_init(const struct dpu_ctl_cfg *cfg,</div><div class='del'>-		void __iomem *addr,</div><div class='del'>-		u32 mixer_count,</div><div class='del'>-		const struct dpu_lm_cfg *mixer);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_ctl_destroy(): Destroys ctl driver context</div><div class='del'>- * should be called to free the context</div><div class='del'>- */</div><div class='del'>-void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);</div><div class='add'>+struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_ctl_cfg *cfg,</div><div class='add'>+				   void __iomem *addr,</div><div class='add'>+				   u32 mixer_count,</div><div class='add'>+				   const struct dpu_lm_cfg *mixer);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_CTL_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c<br/>index 509dbaa51d87..5e9aad1b2aa2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c</a></div><div class='hunk'>@@ -3,6 +3,8 @@</div><div class='ctx'>  * Copyright (c) 2020-2022, Linaro Limited</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;drm/display/drm_dsc_helper.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dpu_kms.h"</div><div class='hunk'>@@ -188,12 +190,13 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,</div><div class='ctx'> 		ops-&gt;dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_dsc *dpu_hw_dsc_init(const struct dpu_dsc_cfg *cfg,</div><div class='add'>+struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_dsc_cfg *cfg,</div><div class='ctx'> 				   void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_dsc *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -206,8 +209,3 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(const struct dpu_dsc_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)</div><div class='del'>-{</div><div class='del'>-	kfree(dsc);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h<br/>index d5b597ab8c5c..989c88d2449b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h</a></div><div class='hunk'>@@ -64,20 +64,24 @@ struct dpu_hw_dsc {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_dsc_init() - Initializes the DSC hw driver object.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  DSC catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * Return: Error code or allocated dpu_hw_dsc context</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_dsc *dpu_hw_dsc_init(const struct dpu_dsc_cfg *cfg,</div><div class='del'>-		void __iomem *addr);</div><div class='add'>+struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,</div><div class='add'>+				   const struct dpu_dsc_cfg *cfg,</div><div class='add'>+				   void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  DSC catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * Returns: Error code or allocated dpu_hw_dsc context</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(const struct dpu_dsc_cfg *cfg,</div><div class='add'>+struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,</div><div class='add'>+				       const struct dpu_dsc_cfg *cfg,</div><div class='ctx'> 				       void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c<br/>index 24fe1d98eb86..ba193b0376fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c</a></div><div class='hunk'>@@ -4,6 +4,8 @@</div><div class='ctx'>  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;drm/display/drm_dsc_helper.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dpu_kms.h"</div><div class='hunk'>@@ -367,12 +369,13 @@ static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,</div><div class='ctx'> 	ops-&gt;dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk_1_2;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(const struct dpu_dsc_cfg *cfg,</div><div class='add'>+struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,</div><div class='add'>+				       const struct dpu_dsc_cfg *cfg,</div><div class='ctx'> 				       void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_dsc *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c<br/>index 9419b2209af8..b1da88e2935f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c</a></div><div class='hunk'>@@ -2,6 +2,8 @@</div><div class='ctx'> /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='ctx'> #include "dpu_hw_lm.h"</div><div class='hunk'>@@ -68,15 +70,16 @@ static void _setup_dspp_ops(struct dpu_hw_dspp *c,</div><div class='ctx'> 		c-&gt;ops.setup_pcc = dpu_setup_dspp_pcc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_dspp *dpu_hw_dspp_init(const struct dpu_dspp_cfg *cfg,</div><div class='del'>-			void __iomem *addr)</div><div class='add'>+struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_dspp_cfg *cfg,</div><div class='add'>+				     void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_dspp *c;</div><div class='ctx'> </div><div class='ctx'> 	if (!addr)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -90,10 +93,3 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(const struct dpu_dspp_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)</div><div class='del'>-{</div><div class='del'>-	kfree(dspp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h<br/>index bea965681330..3b435690b6cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h</a></div><div class='hunk'>@@ -81,18 +81,14 @@ static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_dspp_init() - Initializes the DSPP hw driver object.</div><div class='ctx'>  * should be called once before accessing every DSPP.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  DSPP catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * Return: pointer to structure or ERR_PTR</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_dspp *dpu_hw_dspp_init(const struct dpu_dspp_cfg *cfg,</div><div class='del'>-	void __iomem *addr);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_dspp_destroy(): Destroys DSPP driver context</div><div class='del'>- * @dspp: Pointer to DSPP driver context</div><div class='del'>- */</div><div class='del'>-void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp);</div><div class='add'>+struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_dspp_cfg *cfg,</div><div class='add'>+				     void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_DSPP_H */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c<br/>index 088807db2c83..946dd0135dff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_core_irq.h"</div><div class='ctx'> #include "dpu_kms.h"</div><div class='ctx'> #include "dpu_hw_interrupts.h"</div><div class='hunk'>@@ -472,8 +474,9 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms,</div><div class='ctx'> 	return intr_status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,</div><div class='del'>-		const struct dpu_mdss_cfg *m)</div><div class='add'>+struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct dpu_mdss_cfg *m)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_intr *intr;</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -481,7 +484,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,</div><div class='ctx'> 	if (!addr || !m)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='del'>-	intr = kzalloc(sizeof(*intr), GFP_KERNEL);</div><div class='add'>+	intr = drmm_kzalloc(dev, sizeof(*intr), GFP_KERNEL);</div><div class='ctx'> 	if (!intr)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -512,11 +515,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,</div><div class='ctx'> 	return intr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dpu_hw_intr_destroy(struct dpu_hw_intr *intr)</div><div class='del'>-{</div><div class='del'>-	kfree(intr);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms,</div><div class='ctx'> 				   unsigned int irq_idx,</div><div class='ctx'> 				   void (*irq_cb)(void *arg),</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h<br/>index 53a21ebc57e8..564b750a28fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h</a></div><div class='hunk'>@@ -70,15 +70,12 @@ struct dpu_hw_intr {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_intr_init(): Initializes the interrupts hw object</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @addr: mapped register io address of MDP</div><div class='ctx'>  * @m:    pointer to MDSS catalog data</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,</div><div class='del'>-		const struct dpu_mdss_cfg *m);</div><div class='add'>+struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct dpu_mdss_cfg *m);</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * dpu_hw_intr_destroy(): Cleanup interrutps hw object</div><div class='del'>- * @intr: pointer to interrupts hw object</div><div class='del'>- */</div><div class='del'>-void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c<br/>index e8b8908d3e12..6bba531d6dc4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -12,6 +12,8 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #define INTF_TIMING_ENGINE_EN           0x000</div><div class='ctx'> #define INTF_CONFIG                     0x004</div><div class='ctx'> #define INTF_HSYNC_CTL                  0x008</div><div class='hunk'>@@ -318,9 +320,9 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)</div><div class='ctx'> 	return DPU_REG_READ(c, INTF_LINE_COUNT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)</div><div class='add'>+static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)</div><div class='ctx'> {</div><div class='del'>-	dpu_hw_setup_misr(&amp;intf-&gt;hw, INTF_MISR_CTRL, enable, frame_count);</div><div class='add'>+	dpu_hw_setup_misr(&amp;intf-&gt;hw, INTF_MISR_CTRL, 0x1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)</div><div class='hunk'>@@ -527,8 +529,10 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,</div><div class='ctx'> 	DPU_REG_WRITE(&amp;ctx-&gt;hw, INTF_CONFIG2, intf_cfg2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev)</div><div class='add'>+struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_intf_cfg *cfg,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct dpu_mdss_version *mdss_rev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_intf *c;</div><div class='ctx'> </div><div class='hunk'>@@ -537,7 +541,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -581,9 +585,3 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)</div><div class='del'>-{</div><div class='del'>-	kfree(intf);</div><div class='del'>-}</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h<br/>index c539025c418b..0bd57a32144a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0-only */</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -95,7 +95,7 @@ struct dpu_hw_intf_ops {</div><div class='ctx'> </div><div class='ctx'> 	void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,</div><div class='ctx'> 			const enum dpu_pingpong pp);</div><div class='del'>-	void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count);</div><div class='add'>+	void (*setup_misr)(struct dpu_hw_intf *intf);</div><div class='ctx'> 	int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);</div><div class='ctx'> </div><div class='ctx'> 	// Tearcheck on INTF since DPU 5.0.0</div><div class='hunk'>@@ -131,17 +131,14 @@ struct dpu_hw_intf {</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_intf_init() - Initializes the INTF driver for the passed</div><div class='ctx'>  * interface catalog entry.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  interface catalog entry for which driver object is required</div><div class='ctx'>  * @addr: mapped register io address of MDP</div><div class='ctx'>  * @mdss_rev: dpu core's major and minor versions</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_intf_destroy(): Destroys INTF driver context</div><div class='del'>- * @intf:   Pointer to INTF driver context</div><div class='del'>- */</div><div class='del'>-void dpu_hw_intf_destroy(struct dpu_hw_intf *intf);</div><div class='add'>+struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_intf_cfg *cfg,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct dpu_mdss_version *mdss_rev);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_INTF_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c<br/>index d1c3bd8379ea..1d3ccf3228c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c</a></div><div class='hunk'>@@ -1,9 +1,11 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_kms.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='hunk'>@@ -81,9 +83,9 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)</div><div class='add'>+static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)</div><div class='ctx'> {</div><div class='del'>-	dpu_hw_setup_misr(&amp;ctx-&gt;hw, LM_MISR_CTRL, enable, frame_count);</div><div class='add'>+	dpu_hw_setup_misr(&amp;ctx-&gt;hw, LM_MISR_CTRL, 0x0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)</div><div class='hunk'>@@ -156,8 +158,9 @@ static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops,</div><div class='ctx'> 	ops-&gt;collect_misr = dpu_hw_lm_collect_misr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg,</div><div class='del'>-		void __iomem *addr)</div><div class='add'>+struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,</div><div class='add'>+				    const struct dpu_lm_cfg *cfg,</div><div class='add'>+				    void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_mixer *c;</div><div class='ctx'> </div><div class='hunk'>@@ -166,7 +169,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg,</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -180,8 +183,3 @@ struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)</div><div class='del'>-{</div><div class='del'>-	kfree(lm);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h<br/>index 36992d046a53..0a3381755249 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h</a></div><div class='hunk'>@@ -1,5 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0-only */</div><div class='ctx'> /*</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -57,7 +58,7 @@ struct dpu_hw_lm_ops {</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * setup_misr: Enable/disable MISR</div><div class='ctx'> 	 */</div><div class='del'>-	void (*setup_misr)(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count);</div><div class='add'>+	void (*setup_misr)(struct dpu_hw_mixer *ctx);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * collect_misr: Read MISR signature</div><div class='hunk'>@@ -95,16 +96,12 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_lm_init() - Initializes the mixer hw driver object.</div><div class='ctx'>  * should be called once before accessing every mixer.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  mixer catalog entry for which driver object is required</div><div class='ctx'>  * @addr: mapped register io address of MDP</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_mixer *dpu_hw_lm_init(const struct dpu_lm_cfg *cfg,</div><div class='del'>-		void __iomem *addr);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_lm_destroy(): Destroys layer mixer driver context</div><div class='del'>- * @lm:   Pointer to LM driver context</div><div class='del'>- */</div><div class='del'>-void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm);</div><div class='add'>+struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,</div><div class='add'>+				    const struct dpu_lm_cfg *cfg,</div><div class='add'>+				    void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_LM_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h<br/>index d85157acfbf8..5df545904057 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h</a></div><div class='hunk'>@@ -98,6 +98,7 @@ enum dpu_hw_blk_type {</div><div class='ctx'> 	DPU_HW_BLK_DSPP,</div><div class='ctx'> 	DPU_HW_BLK_MERGE_3D,</div><div class='ctx'> 	DPU_HW_BLK_DSC,</div><div class='add'>+	DPU_HW_BLK_CDM,</div><div class='ctx'> 	DPU_HW_BLK_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -185,6 +186,11 @@ enum dpu_dsc {</div><div class='ctx'> 	DSC_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum dpu_cdm {</div><div class='add'>+	CDM_0 = 1,</div><div class='add'>+	CDM_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum dpu_pingpong {</div><div class='ctx'> 	PINGPONG_NONE,</div><div class='ctx'> 	PINGPONG_0,</div><div class='hunk'>@@ -195,6 +201,8 @@ enum dpu_pingpong {</div><div class='ctx'> 	PINGPONG_5,</div><div class='ctx'> 	PINGPONG_6,</div><div class='ctx'> 	PINGPONG_7,</div><div class='add'>+	PINGPONG_8,</div><div class='add'>+	PINGPONG_9,</div><div class='ctx'> 	PINGPONG_S0,</div><div class='ctx'> 	PINGPONG_MAX</div><div class='ctx'> };</div><div class='hunk'>@@ -204,6 +212,7 @@ enum dpu_merge_3d {</div><div class='ctx'> 	MERGE_3D_1,</div><div class='ctx'> 	MERGE_3D_2,</div><div class='ctx'> 	MERGE_3D_3,</div><div class='add'>+	MERGE_3D_4,</div><div class='ctx'> 	MERGE_3D_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -458,6 +467,7 @@ struct dpu_mdss_color {</div><div class='ctx'> #define DPU_DBG_MASK_ROT      (1 &lt;&lt; 9)</div><div class='ctx'> #define DPU_DBG_MASK_DSPP     (1 &lt;&lt; 10)</div><div class='ctx'> #define DPU_DBG_MASK_DSC      (1 &lt;&lt; 11)</div><div class='add'>+#define DPU_DBG_MASK_CDM      (1 &lt;&lt; 12)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct dpu_hw_tear_check - Struct contains parameters to configure</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c<br/>index 90e0e05eff8d..ddfa40a959cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c</a></div><div class='hunk'>@@ -4,6 +4,8 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hw_mdss.h"</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='hunk'>@@ -37,12 +39,13 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,</div><div class='ctx'> 	c-&gt;ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(const struct dpu_merge_3d_cfg *cfg,</div><div class='del'>-		void __iomem *addr)</div><div class='add'>+struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev,</div><div class='add'>+					     const struct dpu_merge_3d_cfg *cfg,</div><div class='add'>+					     void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_merge_3d *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -55,8 +58,3 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(const struct dpu_merge_3d_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)</div><div class='del'>-{</div><div class='del'>-	kfree(hw);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h<br/>index 19cec5e88722..c192f02ec1ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h</a></div><div class='hunk'>@@ -48,18 +48,13 @@ static inline struct dpu_hw_merge_3d *to_dpu_hw_merge_3d(struct dpu_hw_blk *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_merge_3d_init() - Initializes the merge_3d driver for the passed</div><div class='ctx'>  * merge3d catalog entry.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  Pingpong catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * Return: Error code or allocated dpu_hw_merge_3d context</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(const struct dpu_merge_3d_cfg *cfg,</div><div class='del'>-		void __iomem *addr);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_merge_3d_destroy - destroys merge_3d driver context</div><div class='del'>- *	should be called to free the context</div><div class='del'>- * @pp:   Pointer to PP driver context returned by dpu_hw_merge_3d_init</div><div class='del'>- */</div><div class='del'>-void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *pp);</div><div class='add'>+struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev,</div><div class='add'>+					     const struct dpu_merge_3d_cfg *cfg,</div><div class='add'>+					     void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_MERGE3D_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c<br/>index 057cac7f5d93..2db4c6fba37a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c</a></div><div class='hunk'>@@ -4,6 +4,8 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hw_mdss.h"</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='hunk'>@@ -281,12 +283,14 @@ static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev)</div><div class='add'>+struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,</div><div class='add'>+					     const struct dpu_pingpong_cfg *cfg,</div><div class='add'>+					     void __iomem *addr,</div><div class='add'>+					     const struct dpu_mdss_version *mdss_rev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_pingpong *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -317,8 +321,3 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)</div><div class='del'>-{</div><div class='del'>-	kfree(pp);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h<br/>index 0d541ca5b056..a48b69fd79a3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h</a></div><div class='hunk'>@@ -121,19 +121,15 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_pingpong_init() - initializes the pingpong driver for the passed</div><div class='ctx'>  * pingpong catalog entry.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  Pingpong catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * @mdss_rev: dpu core's major and minor versions</div><div class='ctx'>  * Return: Error code or allocated dpu_hw_pingpong context</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_pingpong *dpu_hw_pingpong_init(const struct dpu_pingpong_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_pingpong_destroy - destroys pingpong driver context</div><div class='del'>- *	should be called to free the context</div><div class='del'>- * @pp:   Pointer to PP driver context returned by dpu_hw_pingpong_init</div><div class='del'>- */</div><div class='del'>-void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp);</div><div class='add'>+struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,</div><div class='add'>+					     const struct dpu_pingpong_cfg *cfg,</div><div class='add'>+					     void __iomem *addr,</div><div class='add'>+					     const struct dpu_mdss_version *mdss_rev);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_PINGPONG_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c<br/>index 8e3c65989c49..0bf8a83e8df3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include "msm_mdss.h"</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_file.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define DPU_FETCH_CONFIG_RESET_VALUE   0x00000087</div><div class='ctx'> </div><div class='hunk'>@@ -395,15 +396,6 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,</div><div class='ctx'> 			format);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)</div><div class='del'>-{</div><div class='del'>-	if (!ctx)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return dpu_hw_get_scaler3_ver(&amp;ctx-&gt;hw,</div><div class='del'>-				      ctx-&gt;cap-&gt;sblk-&gt;scaler_blk.base);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * dpu_hw_sspp_setup_rects()</div><div class='ctx'>  */</div><div class='hunk'>@@ -614,12 +606,8 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,</div><div class='ctx'> 		test_bit(DPU_SSPP_SMART_DMA_V2, &amp;c-&gt;cap-&gt;features))</div><div class='ctx'> 		c-&gt;ops.setup_multirect = dpu_hw_sspp_setup_multirect;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(DPU_SSPP_SCALER_QSEED3, &amp;features) ||</div><div class='del'>-			test_bit(DPU_SSPP_SCALER_QSEED3LITE, &amp;features) ||</div><div class='del'>-			test_bit(DPU_SSPP_SCALER_QSEED4, &amp;features)) {</div><div class='add'>+	if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &amp;features))</div><div class='ctx'> 		c-&gt;ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;</div><div class='del'>-		c-&gt;ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(DPU_SSPP_CDP, &amp;features))</div><div class='ctx'> 		c-&gt;ops.setup_cdp = dpu_hw_sspp_setup_cdp;</div><div class='hunk'>@@ -654,10 +642,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,</div><div class='ctx'> 			cfg-&gt;len,</div><div class='ctx'> 			kms);</div><div class='ctx'> </div><div class='del'>-	if (cfg-&gt;features &amp; BIT(DPU_SSPP_SCALER_QSEED3) ||</div><div class='del'>-			cfg-&gt;features &amp; BIT(DPU_SSPP_SCALER_QSEED3LITE) ||</div><div class='del'>-			cfg-&gt;features &amp; BIT(DPU_SSPP_SCALER_QSEED2) ||</div><div class='del'>-			cfg-&gt;features &amp; BIT(DPU_SSPP_SCALER_QSEED4))</div><div class='add'>+	if (sblk-&gt;scaler_blk.len)</div><div class='ctx'> 		dpu_debugfs_create_regset32("scaler_blk", 0400,</div><div class='ctx'> 				debugfs_root,</div><div class='ctx'> 				sblk-&gt;scaler_blk.base + cfg-&gt;base,</div><div class='hunk'>@@ -685,16 +670,18 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct msm_mdss_data *mdss_data,</div><div class='del'>-		const struct dpu_mdss_version *mdss_rev)</div><div class='add'>+struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_sspp_cfg *cfg,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct msm_mdss_data *mdss_data,</div><div class='add'>+				     const struct dpu_mdss_version *mdss_rev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_sspp *hw_pipe;</div><div class='ctx'> </div><div class='ctx'> 	if (!addr)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='del'>-	hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);</div><div class='add'>+	hw_pipe = drmm_kzalloc(dev, sizeof(*hw_pipe), GFP_KERNEL);</div><div class='ctx'> 	if (!hw_pipe)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -709,9 +696,3 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return hw_pipe;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx)</div><div class='del'>-{</div><div class='del'>-	kfree(ctx);</div><div class='del'>-}</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h<br/>index f93969fddb22..b7dc52312c39 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h</a></div><div class='hunk'>@@ -22,21 +22,6 @@ struct dpu_hw_sspp;</div><div class='ctx'> #define DPU_SSPP_SOLID_FILL		BIT(4)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * Define all scaler feature bits in catalog</div><div class='del'>- */</div><div class='del'>-#define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \</div><div class='del'>-			 BIT(DPU_SSPP_SCALER_QSEED2) | \</div><div class='del'>-			 BIT(DPU_SSPP_SCALER_QSEED3) | \</div><div class='del'>-			 BIT(DPU_SSPP_SCALER_QSEED3LITE) | \</div><div class='del'>-			 BIT(DPU_SSPP_SCALER_QSEED4))</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Define all CSC feature bits in catalog</div><div class='del'>- */</div><div class='del'>-#define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \</div><div class='del'>-			  BIT(DPU_SSPP_CSC_10BIT))</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * Component indices</div><div class='ctx'>  */</div><div class='ctx'> enum {</div><div class='hunk'>@@ -297,12 +282,6 @@ struct dpu_hw_sspp_ops {</div><div class='ctx'> 		const struct dpu_format *format);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='del'>-	 * get_scaler_ver - get scaler h/w version</div><div class='del'>-	 * @ctx: Pointer to pipe context</div><div class='del'>-	 */</div><div class='del'>-	u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx);</div><div class='del'>-</div><div class='del'>-	/**</div><div class='ctx'> 	 * setup_cdp - setup client driven prefetch</div><div class='ctx'> 	 * @pipe: Pointer to software pipe context</div><div class='ctx'> 	 * @fmt: format used by the sw pipe</div><div class='hunk'>@@ -339,21 +318,17 @@ struct dpu_kms;</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_sspp_init() - Initializes the sspp hw driver object.</div><div class='ctx'>  * Should be called once before accessing every pipe.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  Pipe catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * @mdss_data: UBWC / MDSS configuration data</div><div class='ctx'>  * @mdss_rev: dpu core's major and minor versions</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct msm_mdss_data *mdss_data,</div><div class='del'>-		const struct dpu_mdss_version *mdss_rev);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_sspp_destroy(): Destroys SSPP driver context</div><div class='del'>- * should be called during Hw pipe cleanup.</div><div class='del'>- * @ctx:  Pointer to SSPP driver context returned by dpu_hw_sspp_init</div><div class='del'>- */</div><div class='del'>-void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx);</div><div class='add'>+struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_sspp_cfg *cfg,</div><div class='add'>+				     void __iomem *addr,</div><div class='add'>+				     const struct msm_mdss_data *mdss_data,</div><div class='add'>+				     const struct dpu_mdss_version *mdss_rev);</div><div class='ctx'> </div><div class='ctx'> int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,</div><div class='ctx'> 			      struct dentry *entry);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c<br/>index 24e734768a72..05e48cf4ec1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c</a></div><div class='hunk'>@@ -2,6 +2,8 @@</div><div class='ctx'> /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='ctx'> #include "dpu_hw_top.h"</div><div class='hunk'>@@ -247,16 +249,17 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,</div><div class='ctx'> 		ops-&gt;intf_audio_select = dpu_hw_intf_audio_select;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,</div><div class='del'>-		void __iomem *addr,</div><div class='del'>-		const struct dpu_mdss_cfg *m)</div><div class='add'>+struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,</div><div class='add'>+				      const struct dpu_mdp_cfg *cfg,</div><div class='add'>+				      void __iomem *addr,</div><div class='add'>+				      const struct dpu_mdss_cfg *m)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_mdp *mdp;</div><div class='ctx'> </div><div class='ctx'> 	if (!addr)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='del'>-	mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);</div><div class='add'>+	mdp = drmm_kzalloc(dev, sizeof(*mdp), GFP_KERNEL);</div><div class='ctx'> 	if (!mdp)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -271,9 +274,3 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return mdp;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)</div><div class='del'>-{</div><div class='del'>-	kfree(mdp);</div><div class='del'>-}</div><div class='del'>-</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h<br/>index 8b1463d2b2f0..6f3dc98087df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h</a></div><div class='hunk'>@@ -145,13 +145,15 @@ struct dpu_hw_mdp {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_mdptop_init - initializes the top driver for the passed config</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  MDP TOP configuration from catalog</div><div class='ctx'>  * @addr: Mapped register io address of MDP</div><div class='ctx'>  * @m:    Pointer to mdss catalog data</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg,</div><div class='del'>-		void __iomem *addr,</div><div class='del'>-		const struct dpu_mdss_cfg *m);</div><div class='add'>+struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,</div><div class='add'>+				      const struct dpu_mdp_cfg *cfg,</div><div class='add'>+				      void __iomem *addr,</div><div class='add'>+				      const struct dpu_mdss_cfg *m);</div><div class='ctx'> </div><div class='ctx'> void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c<br/>index 18b16b2d2bf5..dd475827314e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__</div><div class='hunk'>@@ -381,12 +381,6 @@ end:</div><div class='ctx'> 	DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,</div><div class='del'>-			u32 scaler_offset)</div><div class='del'>-{</div><div class='del'>-	return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,</div><div class='ctx'> 		u32 csc_reg_off,</div><div class='ctx'> 		const struct dpu_csc_cfg *data, bool csc10)</div><div class='hunk'>@@ -481,9 +475,11 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,</div><div class='ctx'> 		      cfg-&gt;danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * note: Aside from encoders, input_sel should be set to 0x0 by default</div><div class='add'>+ */</div><div class='ctx'> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,</div><div class='del'>-		u32 misr_ctrl_offset,</div><div class='del'>-		bool enable, u32 frame_count)</div><div class='add'>+		u32 misr_ctrl_offset, u8 input_sel)</div><div class='ctx'> {</div><div class='ctx'> 	u32 config = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -492,15 +488,9 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,</div><div class='ctx'> 	/* Clear old MISR value (in case it's read before a new value is calculated)*/</div><div class='ctx'> 	wmb();</div><div class='ctx'> </div><div class='del'>-	if (enable) {</div><div class='del'>-		config = (frame_count &amp; MISR_FRAME_COUNT_MASK) |</div><div class='del'>-			MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;</div><div class='del'>-</div><div class='del'>-		DPU_REG_WRITE(c, misr_ctrl_offset, config);</div><div class='del'>-	} else {</div><div class='del'>-		DPU_REG_WRITE(c, misr_ctrl_offset, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |</div><div class='add'>+		((input_sel &amp; 0xF) &lt;&lt; 24);</div><div class='add'>+	DPU_REG_WRITE(c, misr_ctrl_offset, config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,</div><div class='hunk'>@@ -567,3 +557,47 @@ bool dpu_hw_clk_force_ctrl(struct dpu_hw_blk_reg_map *c,</div><div class='ctx'> </div><div class='ctx'> 	return clk_forced_on;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+#define TO_S15D16(_x_)((_x_) &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {</div><div class='add'>+	{</div><div class='add'>+		/* S15.16 format */</div><div class='add'>+		0x00012A00, 0x00000000, 0x00019880,</div><div class='add'>+		0x00012A00, 0xFFFF9B80, 0xFFFF3000,</div><div class='add'>+		0x00012A00, 0x00020480, 0x00000000,</div><div class='add'>+	},</div><div class='add'>+	/* signed bias */</div><div class='add'>+	{ 0xfff0, 0xff80, 0xff80,},</div><div class='add'>+	{ 0x0, 0x0, 0x0,},</div><div class='add'>+	/* unsigned clamp */</div><div class='add'>+	{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},</div><div class='add'>+	{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {</div><div class='add'>+	{</div><div class='add'>+		/* S15.16 format */</div><div class='add'>+		0x00012A00, 0x00000000, 0x00019880,</div><div class='add'>+		0x00012A00, 0xFFFF9B80, 0xFFFF3000,</div><div class='add'>+		0x00012A00, 0x00020480, 0x00000000,</div><div class='add'>+	},</div><div class='add'>+	/* signed bias */</div><div class='add'>+	{ 0xffc0, 0xfe00, 0xfe00,},</div><div class='add'>+	{ 0x0, 0x0, 0x0,},</div><div class='add'>+	/* unsigned clamp */</div><div class='add'>+	{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},</div><div class='add'>+	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l = {</div><div class='add'>+	{</div><div class='add'>+		TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032),</div><div class='add'>+		TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1),</div><div class='add'>+		TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc)</div><div class='add'>+	},</div><div class='add'>+	{ 0x00, 0x00, 0x00 },</div><div class='add'>+	{ 0x0040, 0x0200, 0x0200 },</div><div class='add'>+	{ 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },</div><div class='add'>+	{ 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h<br/>index 4bea139081bc..64ded69fa903 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0-only */</div><div class='ctx'> /*</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -13,12 +13,18 @@</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='ctx'> </div><div class='ctx'> #define REG_MASK(n)                     ((BIT(n)) - 1)</div><div class='del'>-#define MISR_FRAME_COUNT_MASK           0xFF</div><div class='add'>+#define MISR_FRAME_COUNT                0x1</div><div class='ctx'> #define MISR_CTRL_ENABLE                BIT(8)</div><div class='ctx'> #define MISR_CTRL_STATUS                BIT(9)</div><div class='ctx'> #define MISR_CTRL_STATUS_CLEAR          BIT(10)</div><div class='ctx'> #define MISR_CTRL_FREE_RUN_MASK         BIT(31)</div><div class='ctx'> </div><div class='add'>+#define TO_S15D16(_x_)((_x_) &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L;</div><div class='add'>+extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L;</div><div class='add'>+extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l;</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * This is the common struct maintained by each sub block</div><div class='ctx'>  * for mapping the register offsets in this block to the</div><div class='hunk'>@@ -340,9 +346,6 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,</div><div class='ctx'> 		u32 scaler_offset, u32 scaler_version,</div><div class='ctx'> 		const struct dpu_format *format);</div><div class='ctx'> </div><div class='del'>-u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,</div><div class='del'>-		u32 scaler_offset);</div><div class='del'>-</div><div class='ctx'> void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,</div><div class='ctx'> 		u32 csc_reg_off,</div><div class='ctx'> 		const struct dpu_csc_cfg *data, bool csc10);</div><div class='hunk'>@@ -358,9 +361,7 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,</div><div class='ctx'> 			   const struct dpu_hw_qos_cfg *cfg);</div><div class='ctx'> </div><div class='ctx'> void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,</div><div class='del'>-		u32 misr_ctrl_offset,</div><div class='del'>-		bool enable,</div><div class='del'>-		u32 frame_count);</div><div class='add'>+		u32 misr_ctrl_offset, u8 input_sel);</div><div class='ctx'> </div><div class='ctx'> int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,</div><div class='ctx'> 		u32 misr_ctrl_offset,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c<br/>index a5121a50b2bb..98e34afde2d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c</a></div><div class='hunk'>@@ -2,6 +2,8 @@</div><div class='ctx'> /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='ctx'> #include "dpu_hw_vbif.h"</div><div class='hunk'>@@ -211,12 +213,13 @@ static void _setup_vbif_ops(struct dpu_hw_vbif_ops *ops,</div><div class='ctx'> 	ops-&gt;set_write_gather_en = dpu_hw_set_write_gather_en;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_vbif *dpu_hw_vbif_init(const struct dpu_vbif_cfg *cfg,</div><div class='del'>-		void __iomem *addr)</div><div class='add'>+struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_vbif_cfg *cfg,</div><div class='add'>+				     void __iomem *addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_vbif *c;</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -234,8 +237,3 @@ struct dpu_hw_vbif *dpu_hw_vbif_init(const struct dpu_vbif_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_vbif_destroy(struct dpu_hw_vbif *vbif)</div><div class='del'>-{</div><div class='del'>-	kfree(vbif);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h<br/>index 7e10d2a172b4..e2b4307500e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h</a></div><div class='hunk'>@@ -108,12 +108,12 @@ struct dpu_hw_vbif {</div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_vbif_init() - Initializes the VBIF driver for the passed</div><div class='ctx'>  * VBIF catalog entry.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  VBIF catalog entry for which driver object is required</div><div class='ctx'>  * @addr: Mapped register io address of MDSS</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_vbif *dpu_hw_vbif_init(const struct dpu_vbif_cfg *cfg,</div><div class='del'>-		void __iomem *addr);</div><div class='del'>-</div><div class='del'>-void dpu_hw_vbif_destroy(struct dpu_hw_vbif *vbif);</div><div class='add'>+struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev,</div><div class='add'>+				     const struct dpu_vbif_cfg *cfg,</div><div class='add'>+				     void __iomem *addr);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_VBIF_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c<br/>index 9668fb97c047..e75995f7fcea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c</a></div><div class='hunk'>@@ -3,6 +3,8 @@</div><div class='ctx'>   * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved</div><div class='ctx'>   */</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "dpu_hw_mdss.h"</div><div class='ctx'> #include "dpu_hwio.h"</div><div class='ctx'> #include "dpu_hw_catalog.h"</div><div class='hunk'>@@ -87,6 +89,9 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,</div><div class='ctx'> 			dst_format |= BIT(14); /* DST_ALPHA_X */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (DPU_FORMAT_IS_YUV(fmt))</div><div class='add'>+		dst_format |= BIT(15);</div><div class='add'>+</div><div class='ctx'> 	pattern = (fmt-&gt;element[3] &lt;&lt; 24) |</div><div class='ctx'> 		(fmt-&gt;element[2] &lt;&lt; 16) |</div><div class='ctx'> 		(fmt-&gt;element[1] &lt;&lt; 8)  |</div><div class='hunk'>@@ -208,15 +213,17 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,</div><div class='ctx'> 		ops-&gt;setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev)</div><div class='add'>+struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev,</div><div class='add'>+				 const struct dpu_wb_cfg *cfg,</div><div class='add'>+				 void __iomem *addr,</div><div class='add'>+				 const struct dpu_mdss_version *mdss_rev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dpu_hw_wb *c;</div><div class='ctx'> </div><div class='ctx'> 	if (!addr)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='del'>-	c = kzalloc(sizeof(*c), GFP_KERNEL);</div><div class='add'>+	c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL);</div><div class='ctx'> 	if (!c)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -230,8 +237,3 @@ struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,</div><div class='ctx'> </div><div class='ctx'> 	return c;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb)</div><div class='del'>-{</div><div class='del'>-	kfree(hw_wb);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h<br/>index 88792f450a92..e671796ea379 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h</a></div><div class='hunk'>@@ -76,18 +76,15 @@ struct dpu_hw_wb {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_hw_wb_init() - Initializes the writeback hw driver object.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @cfg:  wb_path catalog entry for which driver object is required</div><div class='ctx'>  * @addr: mapped register io address of MDP</div><div class='ctx'>  * @mdss_rev: dpu core's major and minor versions</div><div class='ctx'>  * Return: Error code or allocated dpu_hw_wb context</div><div class='ctx'>  */</div><div class='del'>-struct dpu_hw_wb *dpu_hw_wb_init(const struct dpu_wb_cfg *cfg,</div><div class='del'>-		void __iomem *addr, const struct dpu_mdss_version *mdss_rev);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dpu_hw_wb_destroy(): Destroy writeback hw driver object.</div><div class='del'>- * @hw_wb:  Pointer to writeback hw driver object</div><div class='del'>- */</div><div class='del'>-void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb);</div><div class='add'>+struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev,</div><div class='add'>+				 const struct dpu_wb_cfg *cfg,</div><div class='add'>+				 void __iomem *addr,</div><div class='add'>+				 const struct dpu_mdss_version *mdss_rev);</div><div class='ctx'> </div><div class='ctx'> #endif /*_DPU_HW_WB_H */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c<br/>index fe7267b3bff5..723cc1d82143 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c</a></div><div class='hunk'>@@ -274,9 +274,6 @@ static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)</div><div class='ctx'> 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);</div><div class='ctx'> 	void *p = dpu_hw_util_get_log_mask_ptr();</div><div class='ctx'> 	struct dentry *entry;</div><div class='del'>-	struct drm_device *dev;</div><div class='del'>-	struct msm_drm_private *priv;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!p)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -285,9 +282,6 @@ static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)</div><div class='ctx'> 	if (minor-&gt;type != DRM_MINOR_PRIMARY)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	dev = dpu_kms-&gt;dev;</div><div class='del'>-	priv = dev-&gt;dev_private;</div><div class='del'>-</div><div class='ctx'> 	entry = debugfs_create_dir("debug", minor-&gt;debugfs_root);</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);</div><div class='hunk'>@@ -297,11 +291,6 @@ static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)</div><div class='ctx'> 	dpu_debugfs_core_irq_init(dpu_kms, entry);</div><div class='ctx'> 	dpu_debugfs_sspp_init(dpu_kms, entry);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(priv-&gt;dp); i++) {</div><div class='del'>-		if (priv-&gt;dp[i])</div><div class='del'>-			msm_dp_debugfs_init(priv-&gt;dp[i], minor);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return dpu_core_perf_debugfs_init(dpu_kms, entry);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='hunk'>@@ -597,7 +586,6 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev,</div><div class='ctx'> 		rc = msm_dp_modeset_init(priv-&gt;dp[i], dev, encoder);</div><div class='ctx'> 		if (rc) {</div><div class='ctx'> 			DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);</div><div class='del'>-			drm_encoder_cleanup(encoder);</div><div class='ctx'> 			return rc;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -630,7 +618,6 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *dev,</div><div class='ctx'> 	rc = msm_hdmi_modeset_init(priv-&gt;hdmi, dev, encoder);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);</div><div class='del'>-		drm_encoder_cleanup(encoder);</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -662,7 +649,6 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev,</div><div class='ctx'> 			n_formats);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);</div><div class='del'>-		drm_encoder_cleanup(encoder);</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -806,30 +792,17 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (dpu_kms-&gt;hw_intr)</div><div class='del'>-		dpu_hw_intr_destroy(dpu_kms-&gt;hw_intr);</div><div class='ctx'> 	dpu_kms-&gt;hw_intr = NULL;</div><div class='ctx'> </div><div class='ctx'> 	/* safe to call these more than once during shutdown */</div><div class='ctx'> 	_dpu_kms_mmu_destroy(dpu_kms);</div><div class='ctx'> </div><div class='del'>-	if (dpu_kms-&gt;catalog) {</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(dpu_kms-&gt;hw_vbif); i++) {</div><div class='del'>-			if (dpu_kms-&gt;hw_vbif[i]) {</div><div class='del'>-				dpu_hw_vbif_destroy(dpu_kms-&gt;hw_vbif[i]);</div><div class='del'>-				dpu_kms-&gt;hw_vbif[i] = NULL;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(dpu_kms-&gt;hw_vbif); i++) {</div><div class='add'>+		dpu_kms-&gt;hw_vbif[i] = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dpu_kms-&gt;rm_init)</div><div class='del'>-		dpu_rm_destroy(&amp;dpu_kms-&gt;rm);</div><div class='del'>-	dpu_kms-&gt;rm_init = false;</div><div class='del'>-</div><div class='ctx'> 	dpu_kms-&gt;catalog = NULL;</div><div class='ctx'> </div><div class='del'>-	if (dpu_kms-&gt;hw_mdp)</div><div class='del'>-		dpu_hw_mdp_destroy(dpu_kms-&gt;hw_mdp);</div><div class='ctx'> 	dpu_kms-&gt;hw_mdp = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -856,7 +829,6 @@ static int dpu_irq_postinstall(struct msm_kms *kms)</div><div class='ctx'> {</div><div class='ctx'> 	struct msm_drm_private *priv;</div><div class='ctx'> 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!dpu_kms || !dpu_kms-&gt;dev)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -865,9 +837,6 @@ static int dpu_irq_postinstall(struct msm_kms *kms)</div><div class='ctx'> 	if (!priv)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(priv-&gt;dp); i++)</div><div class='del'>-		msm_dp_irq_postinstall(priv-&gt;dp[i]);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -975,6 +944,10 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (cat-&gt;cdm)</div><div class='add'>+		msm_disp_snapshot_add_block(disp_state, cat-&gt;cdm-&gt;len,</div><div class='add'>+					    dpu_kms-&gt;mmio + cat-&gt;cdm-&gt;base, cat-&gt;cdm-&gt;name);</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_put_sync(&amp;dpu_kms-&gt;pdev-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1078,7 +1051,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)</div><div class='ctx'> 	if (!dpu_kms-&gt;catalog) {</div><div class='ctx'> 		DPU_ERROR("device config not known!\n");</div><div class='ctx'> 		rc = -EINVAL;</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1088,49 +1061,48 @@ static int dpu_kms_hw_init(struct msm_kms *kms)</div><div class='ctx'> 	rc = _dpu_kms_mmu_init(dpu_kms);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dpu_kms-&gt;mdss = msm_mdss_get_mdss_data(dpu_kms-&gt;pdev-&gt;dev.parent);</div><div class='ctx'> 	if (IS_ERR(dpu_kms-&gt;mdss)) {</div><div class='ctx'> 		rc = PTR_ERR(dpu_kms-&gt;mdss);</div><div class='ctx'> 		DPU_ERROR("failed to get MDSS data: %d\n", rc);</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!dpu_kms-&gt;mdss) {</div><div class='ctx'> 		rc = -EINVAL;</div><div class='ctx'> 		DPU_ERROR("NULL MDSS data\n");</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = dpu_rm_init(&amp;dpu_kms-&gt;rm, dpu_kms-&gt;catalog, dpu_kms-&gt;mdss, dpu_kms-&gt;mmio);</div><div class='add'>+	rc = dpu_rm_init(dev, &amp;dpu_kms-&gt;rm, dpu_kms-&gt;catalog, dpu_kms-&gt;mdss, dpu_kms-&gt;mmio);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("rm init failed: %d\n", rc);</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dpu_kms-&gt;rm_init = true;</div><div class='del'>-</div><div class='del'>-	dpu_kms-&gt;hw_mdp = dpu_hw_mdptop_init(dpu_kms-&gt;catalog-&gt;mdp,</div><div class='add'>+	dpu_kms-&gt;hw_mdp = dpu_hw_mdptop_init(dev,</div><div class='add'>+					     dpu_kms-&gt;catalog-&gt;mdp,</div><div class='ctx'> 					     dpu_kms-&gt;mmio,</div><div class='ctx'> 					     dpu_kms-&gt;catalog);</div><div class='ctx'> 	if (IS_ERR(dpu_kms-&gt;hw_mdp)) {</div><div class='ctx'> 		rc = PTR_ERR(dpu_kms-&gt;hw_mdp);</div><div class='ctx'> 		DPU_ERROR("failed to get hw_mdp: %d\n", rc);</div><div class='ctx'> 		dpu_kms-&gt;hw_mdp = NULL;</div><div class='del'>-		goto power_error;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dpu_kms-&gt;catalog-&gt;vbif_count; i++) {</div><div class='ctx'> 		struct dpu_hw_vbif *hw;</div><div class='ctx'> 		const struct dpu_vbif_cfg *vbif = &amp;dpu_kms-&gt;catalog-&gt;vbif[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_vbif_init(vbif, dpu_kms-&gt;vbif[vbif-&gt;id]);</div><div class='add'>+		hw = dpu_hw_vbif_init(dev, vbif, dpu_kms-&gt;vbif[vbif-&gt;id]);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed to init vbif %d: %d\n", vbif-&gt;id, rc);</div><div class='del'>-			goto power_error;</div><div class='add'>+			goto err_pm_put;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		dpu_kms-&gt;hw_vbif[vbif-&gt;id] = hw;</div><div class='hunk'>@@ -1146,15 +1118,15 @@ static int dpu_kms_hw_init(struct msm_kms *kms)</div><div class='ctx'> 	rc = dpu_core_perf_init(&amp;dpu_kms-&gt;perf, dpu_kms-&gt;catalog-&gt;perf, max_core_clk_rate);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("failed to init perf %d\n", rc);</div><div class='del'>-		goto perf_err;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dpu_kms-&gt;hw_intr = dpu_hw_intr_init(dpu_kms-&gt;mmio, dpu_kms-&gt;catalog);</div><div class='del'>-	if (IS_ERR_OR_NULL(dpu_kms-&gt;hw_intr)) {</div><div class='add'>+	dpu_kms-&gt;hw_intr = dpu_hw_intr_init(dev, dpu_kms-&gt;mmio, dpu_kms-&gt;catalog);</div><div class='add'>+	if (IS_ERR(dpu_kms-&gt;hw_intr)) {</div><div class='ctx'> 		rc = PTR_ERR(dpu_kms-&gt;hw_intr);</div><div class='ctx'> 		DPU_ERROR("hw_intr init failed: %d\n", rc);</div><div class='ctx'> 		dpu_kms-&gt;hw_intr = NULL;</div><div class='del'>-		goto hw_intr_init_err;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;mode_config.min_width = 0;</div><div class='hunk'>@@ -1179,7 +1151,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)</div><div class='ctx'> 	rc = _dpu_kms_drm_obj_init(dpu_kms);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		DPU_ERROR("modeset init failed: %d\n", rc);</div><div class='del'>-		goto drm_obj_init_err;</div><div class='add'>+		goto err_pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dpu_vbif_init_memtypes(dpu_kms);</div><div class='hunk'>@@ -1188,10 +1160,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-drm_obj_init_err:</div><div class='del'>-hw_intr_init_err:</div><div class='del'>-perf_err:</div><div class='del'>-power_error:</div><div class='add'>+err_pm_put:</div><div class='ctx'> 	pm_runtime_put_sync(&amp;dpu_kms-&gt;pdev-&gt;dev);</div><div class='ctx'> error:</div><div class='ctx'> 	_dpu_kms_hw_destroy(dpu_kms);</div><div class='hunk'>@@ -1349,6 +1318,7 @@ static const struct dev_pm_ops dpu_pm_ops = {</div><div class='ctx'> static const struct of_device_id dpu_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,msm8998-dpu", .data = &amp;dpu_msm8998_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,qcm2290-dpu", .data = &amp;dpu_qcm2290_cfg, },</div><div class='add'>+	{ .compatible = "qcom,sdm670-dpu", .data = &amp;dpu_sdm670_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,sdm845-dpu", .data = &amp;dpu_sdm845_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-dpu", .data = &amp;dpu_sc7180_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,sc7280-dpu", .data = &amp;dpu_sc7280_cfg, },</div><div class='hunk'>@@ -1363,6 +1333,7 @@ static const struct of_device_id dpu_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sm8350-dpu", .data = &amp;dpu_sm8350_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,sm8450-dpu", .data = &amp;dpu_sm8450_cfg, },</div><div class='ctx'> 	{ .compatible = "qcom,sm8550-dpu", .data = &amp;dpu_sm8550_cfg, },</div><div class='add'>+	{ .compatible = "qcom,sm8650-dpu", .data = &amp;dpu_sm8650_cfg, },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, dpu_dt_match);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h<br/>index b6f53ca6e962..d1207f4ec3ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h</a></div><div class='hunk'>@@ -51,6 +51,7 @@</div><div class='ctx'> 	} while (0)</div><div class='ctx'> </div><div class='ctx'> #define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__)</div><div class='add'>+#define DPU_ERROR_RATELIMITED(fmt, ...) pr_err_ratelimited("[dpu error]" fmt, ##__VA_ARGS__)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ktime_compare_safe - compare two ktime structures</div><div class='hunk'>@@ -88,7 +89,6 @@ struct dpu_kms {</div><div class='ctx'> 	struct drm_private_obj global_state;</div><div class='ctx'> </div><div class='ctx'> 	struct dpu_rm rm;</div><div class='del'>-	bool rm_init;</div><div class='ctx'> </div><div class='ctx'> 	struct dpu_hw_vbif *hw_vbif[VBIF_MAX];</div><div class='ctx'> 	struct dpu_hw_mdp *hw_mdp;</div><div class='hunk'>@@ -136,6 +136,7 @@ struct dpu_global_state {</div><div class='ctx'> 	uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];</div><div class='ctx'> 	uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];</div><div class='ctx'> 	uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];</div><div class='add'>+	uint32_t cdm_to_enc_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dpu_global_state</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c<br/>index 3eef5e025e12..ff975ad51145 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'> #include "dpu_kms.h"</div><div class='ctx'> #include "dpu_formats.h"</div><div class='ctx'> #include "dpu_hw_sspp.h"</div><div class='add'>+#include "dpu_hw_util.h"</div><div class='ctx'> #include "dpu_trace.h"</div><div class='ctx'> #include "dpu_crtc.h"</div><div class='ctx'> #include "dpu_vbif.h"</div><div class='hunk'>@@ -78,8 +79,6 @@ static const uint32_t qcom_compressed_supported_formats[] = {</div><div class='ctx'> struct dpu_plane {</div><div class='ctx'> 	struct drm_plane base;</div><div class='ctx'> </div><div class='del'>-	struct mutex lock;</div><div class='del'>-</div><div class='ctx'> 	enum dpu_sspp pipe;</div><div class='ctx'> </div><div class='ctx'> 	uint32_t color_fill;</div><div class='hunk'>@@ -470,8 +469,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,</div><div class='ctx'> 			scale_cfg-&gt;src_height[i] /= chroma_subsmpl_v;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (pipe_hw-&gt;cap-&gt;features &amp;</div><div class='del'>-			BIT(DPU_SSPP_SCALER_QSEED4)) {</div><div class='add'>+		if (pipe_hw-&gt;cap-&gt;sblk-&gt;scaler_blk.version &gt;= 0x3000) {</div><div class='ctx'> 			scale_cfg-&gt;preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;</div><div class='ctx'> 			scale_cfg-&gt;preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -511,36 +509,6 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = {</div><div class='del'>-	{</div><div class='del'>-		/* S15.16 format */</div><div class='del'>-		0x00012A00, 0x00000000, 0x00019880,</div><div class='del'>-		0x00012A00, 0xFFFF9B80, 0xFFFF3000,</div><div class='del'>-		0x00012A00, 0x00020480, 0x00000000,</div><div class='del'>-	},</div><div class='del'>-	/* signed bias */</div><div class='del'>-	{ 0xfff0, 0xff80, 0xff80,},</div><div class='del'>-	{ 0x0, 0x0, 0x0,},</div><div class='del'>-	/* unsigned clamp */</div><div class='del'>-	{ 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},</div><div class='del'>-	{ 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = {</div><div class='del'>-	{</div><div class='del'>-		/* S15.16 format */</div><div class='del'>-		0x00012A00, 0x00000000, 0x00019880,</div><div class='del'>-		0x00012A00, 0xFFFF9B80, 0xFFFF3000,</div><div class='del'>-		0x00012A00, 0x00020480, 0x00000000,</div><div class='del'>-		},</div><div class='del'>-	/* signed bias */</div><div class='del'>-	{ 0xffc0, 0xfe00, 0xfe00,},</div><div class='del'>-	{ 0x0, 0x0, 0x0,},</div><div class='del'>-	/* unsigned clamp */</div><div class='del'>-	{ 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},</div><div class='del'>-	{ 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,</div><div class='ctx'> 						    const struct dpu_format *fmt)</div><div class='ctx'> {</div><div class='hunk'>@@ -774,8 +742,8 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,</div><div class='ctx'> 	min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;</div><div class='ctx'> </div><div class='ctx'> 	if (DPU_FORMAT_IS_YUV(fmt) &amp;&amp;</div><div class='del'>-	    (!(pipe-&gt;sspp-&gt;cap-&gt;features &amp; DPU_SSPP_SCALER) ||</div><div class='del'>-	     !(pipe-&gt;sspp-&gt;cap-&gt;features &amp; DPU_SSPP_CSC_ANY))) {</div><div class='add'>+	    (!pipe-&gt;sspp-&gt;cap-&gt;sblk-&gt;scaler_blk.len ||</div><div class='add'>+	     !pipe-&gt;sspp-&gt;cap-&gt;sblk-&gt;csc_blk.len)) {</div><div class='ctx'> 		DPU_DEBUG_PLANE(pdpu,</div><div class='ctx'> 				"plane doesn't have scaler/csc for yuv\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -824,6 +792,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,</div><div class='ctx'> 										 plane);</div><div class='ctx'> 	int ret = 0, min_scale;</div><div class='ctx'> 	struct dpu_plane *pdpu = to_dpu_plane(plane);</div><div class='add'>+	struct dpu_kms *kms = _dpu_plane_get_kms(&amp;pdpu-&gt;base);</div><div class='add'>+	u64 max_mdp_clk_rate = kms-&gt;perf.max_core_clk_rate;</div><div class='ctx'> 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);</div><div class='ctx'> 	struct dpu_sw_pipe *pipe = &amp;pstate-&gt;pipe;</div><div class='ctx'> 	struct dpu_sw_pipe *r_pipe = &amp;pstate-&gt;r_pipe;</div><div class='hunk'>@@ -892,14 +862,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,</div><div class='ctx'> </div><div class='ctx'> 	max_linewidth = pdpu-&gt;catalog-&gt;caps-&gt;max_linewidth;</div><div class='ctx'> </div><div class='del'>-	if (drm_rect_width(&amp;pipe_cfg-&gt;src_rect) &gt; max_linewidth) {</div><div class='add'>+	if ((drm_rect_width(&amp;pipe_cfg-&gt;src_rect) &gt; max_linewidth) ||</div><div class='add'>+	     _dpu_plane_calc_clk(&amp;crtc_state-&gt;adjusted_mode, pipe_cfg) &gt; max_mdp_clk_rate) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * In parallel multirect case only the half of the usual width</div><div class='ctx'> 		 * is supported for tiled formats. If we are here, we know that</div><div class='ctx'> 		 * full width is more than max_linewidth, thus each rect is</div><div class='ctx'> 		 * wider than allowed.</div><div class='ctx'> 		 */</div><div class='del'>-		if (DPU_FORMAT_IS_UBWC(fmt)) {</div><div class='add'>+		if (DPU_FORMAT_IS_UBWC(fmt) &amp;&amp;</div><div class='add'>+		    drm_rect_width(&amp;pipe_cfg-&gt;src_rect) &gt; max_linewidth) {</div><div class='ctx'> 			DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",</div><div class='ctx'> 					DRM_RECT_ARG(&amp;pipe_cfg-&gt;src_rect), max_linewidth);</div><div class='ctx'> 			return -E2BIG;</div><div class='hunk'>@@ -1213,29 +1185,6 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dpu_plane_destroy(struct drm_plane *plane)</div><div class='del'>-{</div><div class='del'>-	struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL;</div><div class='del'>-	struct dpu_plane_state *pstate;</div><div class='del'>-</div><div class='del'>-	DPU_DEBUG_PLANE(pdpu, "\n");</div><div class='del'>-</div><div class='del'>-	if (pdpu) {</div><div class='del'>-		pstate = to_dpu_plane_state(plane-&gt;state);</div><div class='del'>-		_dpu_plane_set_qos_ctrl(plane, &amp;pstate-&gt;pipe, false);</div><div class='del'>-</div><div class='del'>-		if (pstate-&gt;r_pipe.sspp)</div><div class='del'>-			_dpu_plane_set_qos_ctrl(plane, &amp;pstate-&gt;r_pipe, false);</div><div class='del'>-</div><div class='del'>-		mutex_destroy(&amp;pdpu-&gt;lock);</div><div class='del'>-</div><div class='del'>-		/* this will destroy the states as well */</div><div class='del'>-		drm_plane_cleanup(plane);</div><div class='del'>-</div><div class='del'>-		kfree(pdpu);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void dpu_plane_destroy_state(struct drm_plane *plane,</div><div class='ctx'> 		struct drm_plane_state *state)</div><div class='ctx'> {</div><div class='hunk'>@@ -1405,7 +1354,6 @@ static bool dpu_plane_format_mod_supported(struct drm_plane *plane,</div><div class='ctx'> static const struct drm_plane_funcs dpu_plane_funcs = {</div><div class='ctx'> 		.update_plane = drm_atomic_helper_update_plane,</div><div class='ctx'> 		.disable_plane = drm_atomic_helper_disable_plane,</div><div class='del'>-		.destroy = dpu_plane_destroy,</div><div class='ctx'> 		.reset = dpu_plane_reset,</div><div class='ctx'> 		.atomic_duplicate_state = dpu_plane_duplicate_state,</div><div class='ctx'> 		.atomic_destroy_state = dpu_plane_destroy_state,</div><div class='hunk'>@@ -1433,35 +1381,28 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,</div><div class='ctx'> 	struct dpu_hw_sspp *pipe_hw;</div><div class='ctx'> 	uint32_t num_formats;</div><div class='ctx'> 	uint32_t supported_rotations;</div><div class='del'>-	int ret = -EINVAL;</div><div class='del'>-</div><div class='del'>-	/* create and zero local structure */</div><div class='del'>-	pdpu = kzalloc(sizeof(*pdpu), GFP_KERNEL);</div><div class='del'>-	if (!pdpu) {</div><div class='del'>-		DPU_ERROR("[%u]failed to allocate local plane struct\n", pipe);</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		return ERR_PTR(ret);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* cache local stuff for later */</div><div class='del'>-	plane = &amp;pdpu-&gt;base;</div><div class='del'>-	pdpu-&gt;pipe = pipe;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* initialize underlying h/w driver */</div><div class='ctx'> 	pipe_hw = dpu_rm_get_sspp(&amp;kms-&gt;rm, pipe);</div><div class='ctx'> 	if (!pipe_hw || !pipe_hw-&gt;cap || !pipe_hw-&gt;cap-&gt;sblk) {</div><div class='ctx'> 		DPU_ERROR("[%u]SSPP is invalid\n", pipe);</div><div class='del'>-		goto clean_plane;</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	format_list = pipe_hw-&gt;cap-&gt;sblk-&gt;format_list;</div><div class='ctx'> 	num_formats = pipe_hw-&gt;cap-&gt;sblk-&gt;num_formats;</div><div class='ctx'> </div><div class='del'>-	ret = drm_universal_plane_init(dev, plane, 0xff, &amp;dpu_plane_funcs,</div><div class='add'>+	pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base,</div><div class='add'>+				0xff, &amp;dpu_plane_funcs,</div><div class='ctx'> 				format_list, num_formats,</div><div class='ctx'> 				supported_format_modifiers, type, NULL);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto clean_plane;</div><div class='add'>+	if (IS_ERR(pdpu))</div><div class='add'>+		return ERR_CAST(pdpu);</div><div class='add'>+</div><div class='add'>+	/* cache local stuff for later */</div><div class='add'>+	plane = &amp;pdpu-&gt;base;</div><div class='add'>+	pdpu-&gt;pipe = pipe;</div><div class='ctx'> </div><div class='ctx'> 	pdpu-&gt;catalog = kms-&gt;catalog;</div><div class='ctx'> </div><div class='hunk'>@@ -1488,13 +1429,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,</div><div class='ctx'> 	/* success! finalize initialization */</div><div class='ctx'> 	drm_plane_helper_add(plane, &amp;dpu_plane_helper_funcs);</div><div class='ctx'> </div><div class='del'>-	mutex_init(&amp;pdpu-&gt;lock);</div><div class='del'>-</div><div class='ctx'> 	DPU_DEBUG("%s created for pipe:%u id:%u\n", plane-&gt;name,</div><div class='ctx'> 					pipe, plane-&gt;base.id);</div><div class='ctx'> 	return plane;</div><div class='del'>-</div><div class='del'>-clean_plane:</div><div class='del'>-	kfree(pdpu);</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c<br/>index 8759466e2f37..b58a9c2ae326 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include "dpu_kms.h"</div><div class='ctx'> #include "dpu_hw_lm.h"</div><div class='ctx'> #include "dpu_hw_ctl.h"</div><div class='add'>+#include "dpu_hw_cdm.h"</div><div class='ctx'> #include "dpu_hw_pingpong.h"</div><div class='ctx'> #include "dpu_hw_sspp.h"</div><div class='ctx'> #include "dpu_hw_intf.h"</div><div class='hunk'>@@ -34,72 +35,8 @@ struct dpu_rm_requirements {</div><div class='ctx'> 	struct msm_display_topology topology;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int dpu_rm_destroy(struct dpu_rm *rm)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;dspp_blks); i++) {</div><div class='del'>-		struct dpu_hw_dspp *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;dspp_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_dspp(rm-&gt;dspp_blks[i]);</div><div class='del'>-			dpu_hw_dspp_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;pingpong_blks); i++) {</div><div class='del'>-		struct dpu_hw_pingpong *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;pingpong_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_pingpong(rm-&gt;pingpong_blks[i]);</div><div class='del'>-			dpu_hw_pingpong_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;merge_3d_blks); i++) {</div><div class='del'>-		struct dpu_hw_merge_3d *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;merge_3d_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_merge_3d(rm-&gt;merge_3d_blks[i]);</div><div class='del'>-			dpu_hw_merge_3d_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;mixer_blks); i++) {</div><div class='del'>-		struct dpu_hw_mixer *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;mixer_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_mixer(rm-&gt;mixer_blks[i]);</div><div class='del'>-			dpu_hw_lm_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;ctl_blks); i++) {</div><div class='del'>-		struct dpu_hw_ctl *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;ctl_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_ctl(rm-&gt;ctl_blks[i]);</div><div class='del'>-			dpu_hw_ctl_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;hw_intf); i++)</div><div class='del'>-		dpu_hw_intf_destroy(rm-&gt;hw_intf[i]);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;dsc_blks); i++) {</div><div class='del'>-		struct dpu_hw_dsc *hw;</div><div class='del'>-</div><div class='del'>-		if (rm-&gt;dsc_blks[i]) {</div><div class='del'>-			hw = to_dpu_hw_dsc(rm-&gt;dsc_blks[i]);</div><div class='del'>-			dpu_hw_dsc_destroy(hw);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;hw_wb); i++)</div><div class='del'>-		dpu_hw_wb_destroy(rm-&gt;hw_wb[i]);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(rm-&gt;hw_sspp); i++)</div><div class='del'>-		dpu_hw_sspp_destroy(rm-&gt;hw_sspp[i]);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int dpu_rm_init(struct dpu_rm *rm,</div><div class='add'>+int dpu_rm_init(struct drm_device *dev,</div><div class='add'>+		struct dpu_rm *rm,</div><div class='ctx'> 		const struct dpu_mdss_cfg *cat,</div><div class='ctx'> 		const struct msm_mdss_data *mdss_data,</div><div class='ctx'> 		void __iomem *mmio)</div><div class='hunk'>@@ -119,7 +56,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_mixer *hw;</div><div class='ctx'> 		const struct dpu_lm_cfg *lm = &amp;cat-&gt;mixer[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_lm_init(lm, mmio);</div><div class='add'>+		hw = dpu_hw_lm_init(dev, lm, mmio);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed lm object creation: err %d\n", rc);</div><div class='hunk'>@@ -132,7 +69,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_merge_3d *hw;</div><div class='ctx'> 		const struct dpu_merge_3d_cfg *merge_3d = &amp;cat-&gt;merge_3d[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_merge_3d_init(merge_3d, mmio);</div><div class='add'>+		hw = dpu_hw_merge_3d_init(dev, merge_3d, mmio);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed merge_3d object creation: err %d\n",</div><div class='hunk'>@@ -146,7 +83,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_pingpong *hw;</div><div class='ctx'> 		const struct dpu_pingpong_cfg *pp = &amp;cat-&gt;pingpong[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_pingpong_init(pp, mmio, cat-&gt;mdss_ver);</div><div class='add'>+		hw = dpu_hw_pingpong_init(dev, pp, mmio, cat-&gt;mdss_ver);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed pingpong object creation: err %d\n",</div><div class='hunk'>@@ -162,7 +99,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_intf *hw;</div><div class='ctx'> 		const struct dpu_intf_cfg *intf = &amp;cat-&gt;intf[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_intf_init(intf, mmio, cat-&gt;mdss_ver);</div><div class='add'>+		hw = dpu_hw_intf_init(dev, intf, mmio, cat-&gt;mdss_ver);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed intf object creation: err %d\n", rc);</div><div class='hunk'>@@ -175,7 +112,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_wb *hw;</div><div class='ctx'> 		const struct dpu_wb_cfg *wb = &amp;cat-&gt;wb[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_wb_init(wb, mmio, cat-&gt;mdss_ver);</div><div class='add'>+		hw = dpu_hw_wb_init(dev, wb, mmio, cat-&gt;mdss_ver);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed wb object creation: err %d\n", rc);</div><div class='hunk'>@@ -188,7 +125,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_ctl *hw;</div><div class='ctx'> 		const struct dpu_ctl_cfg *ctl = &amp;cat-&gt;ctl[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_ctl_init(ctl, mmio, cat-&gt;mixer_count, cat-&gt;mixer);</div><div class='add'>+		hw = dpu_hw_ctl_init(dev, ctl, mmio, cat-&gt;mixer_count, cat-&gt;mixer);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed ctl object creation: err %d\n", rc);</div><div class='hunk'>@@ -201,7 +138,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_dspp *hw;</div><div class='ctx'> 		const struct dpu_dspp_cfg *dspp = &amp;cat-&gt;dspp[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_dspp_init(dspp, mmio);</div><div class='add'>+		hw = dpu_hw_dspp_init(dev, dspp, mmio);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed dspp object creation: err %d\n", rc);</div><div class='hunk'>@@ -215,9 +152,9 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		const struct dpu_dsc_cfg *dsc = &amp;cat-&gt;dsc[i];</div><div class='ctx'> </div><div class='ctx'> 		if (test_bit(DPU_DSC_HW_REV_1_2, &amp;dsc-&gt;features))</div><div class='del'>-			hw = dpu_hw_dsc_init_1_2(dsc, mmio);</div><div class='add'>+			hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);</div><div class='ctx'> 		else</div><div class='del'>-			hw = dpu_hw_dsc_init(dsc, mmio);</div><div class='add'>+			hw = dpu_hw_dsc_init(dev, dsc, mmio);</div><div class='ctx'> </div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='hunk'>@@ -231,7 +168,7 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_hw_sspp *hw;</div><div class='ctx'> 		const struct dpu_sspp_cfg *sspp = &amp;cat-&gt;sspp[i];</div><div class='ctx'> </div><div class='del'>-		hw = dpu_hw_sspp_init(sspp, mmio, mdss_data, cat-&gt;mdss_ver);</div><div class='add'>+		hw = dpu_hw_sspp_init(dev, sspp, mmio, mdss_data, cat-&gt;mdss_ver);</div><div class='ctx'> 		if (IS_ERR(hw)) {</div><div class='ctx'> 			rc = PTR_ERR(hw);</div><div class='ctx'> 			DPU_ERROR("failed sspp object creation: err %d\n", rc);</div><div class='hunk'>@@ -240,11 +177,21 @@ int dpu_rm_init(struct dpu_rm *rm,</div><div class='ctx'> 		rm-&gt;hw_sspp[sspp-&gt;id - SSPP_NONE] = hw;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (cat-&gt;cdm) {</div><div class='add'>+		struct dpu_hw_cdm *hw;</div><div class='add'>+</div><div class='add'>+		hw = dpu_hw_cdm_init(dev, cat-&gt;cdm, mmio, cat-&gt;mdss_ver);</div><div class='add'>+		if (IS_ERR(hw)) {</div><div class='add'>+			rc = PTR_ERR(hw);</div><div class='add'>+			DPU_ERROR("failed cdm object creation: err %d\n", rc);</div><div class='add'>+			goto fail;</div><div class='add'>+		}</div><div class='add'>+		rm-&gt;cdm_blk = &amp;hw-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='del'>-	dpu_rm_destroy(rm);</div><div class='del'>-</div><div class='ctx'> 	return rc ? rc : -EFAULT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -488,6 +435,26 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int _dpu_rm_reserve_cdm(struct dpu_rm *rm,</div><div class='add'>+			       struct dpu_global_state *global_state,</div><div class='add'>+			       struct drm_encoder *enc)</div><div class='add'>+{</div><div class='add'>+	/* try allocating only one CDM block */</div><div class='add'>+	if (!rm-&gt;cdm_blk) {</div><div class='add'>+		DPU_ERROR("CDM block does not exist\n");</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (global_state-&gt;cdm_to_enc_id) {</div><div class='add'>+		DPU_ERROR("CDM_0 is already allocated\n");</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	global_state-&gt;cdm_to_enc_id = enc-&gt;base.id;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int _dpu_rm_make_reservation(</div><div class='ctx'> 		struct dpu_rm *rm,</div><div class='ctx'> 		struct dpu_global_state *global_state,</div><div class='hunk'>@@ -513,6 +480,14 @@ static int _dpu_rm_make_reservation(</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	if (reqs-&gt;topology.needs_cdm) {</div><div class='add'>+		ret = _dpu_rm_reserve_cdm(rm, global_state, enc);</div><div class='add'>+		if (ret) {</div><div class='add'>+			DPU_ERROR("unable to find CDM blk\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -523,9 +498,9 @@ static int _dpu_rm_populate_requirements(</div><div class='ctx'> {</div><div class='ctx'> 	reqs-&gt;topology = req_topology;</div><div class='ctx'> </div><div class='del'>-	DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d\n",</div><div class='add'>+	DRM_DEBUG_KMS("num_lm: %d num_dsc: %d num_intf: %d cdm: %d\n",</div><div class='ctx'> 		      reqs-&gt;topology.num_lm, reqs-&gt;topology.num_dsc,</div><div class='del'>-		      reqs-&gt;topology.num_intf);</div><div class='add'>+		      reqs-&gt;topology.num_intf, reqs-&gt;topology.needs_cdm);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -554,6 +529,7 @@ void dpu_rm_release(struct dpu_global_state *global_state,</div><div class='ctx'> 		ARRAY_SIZE(global_state-&gt;dsc_to_enc_id), enc-&gt;base.id);</div><div class='ctx'> 	_dpu_rm_clear_mapping(global_state-&gt;dspp_to_enc_id,</div><div class='ctx'> 		ARRAY_SIZE(global_state-&gt;dspp_to_enc_id), enc-&gt;base.id);</div><div class='add'>+	_dpu_rm_clear_mapping(&amp;global_state-&gt;cdm_to_enc_id, 1, enc-&gt;base.id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dpu_rm_reserve(</div><div class='hunk'>@@ -627,6 +603,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,</div><div class='ctx'> 		hw_to_enc_id = global_state-&gt;dsc_to_enc_id;</div><div class='ctx'> 		max_blks = ARRAY_SIZE(rm-&gt;dsc_blks);</div><div class='ctx'> 		break;</div><div class='add'>+	case DPU_HW_BLK_CDM:</div><div class='add'>+		hw_blks = &amp;rm-&gt;cdm_blk;</div><div class='add'>+		hw_to_enc_id = &amp;global_state-&gt;cdm_to_enc_id;</div><div class='add'>+		max_blks = 1;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		DPU_ERROR("blk type %d not managed by rm\n", type);</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h<br/>index 2b551566cbf4..e3f83ebc656b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h</a></div><div class='hunk'>@@ -22,6 +22,7 @@ struct dpu_global_state;</div><div class='ctx'>  * @hw_wb: array of wb hardware resources</div><div class='ctx'>  * @dspp_blks: array of dspp hardware resources</div><div class='ctx'>  * @hw_sspp: array of sspp hardware resources</div><div class='add'>+ * @cdm_blk: cdm hardware resource</div><div class='ctx'>  */</div><div class='ctx'> struct dpu_rm {</div><div class='ctx'> 	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];</div><div class='hunk'>@@ -33,30 +34,26 @@ struct dpu_rm {</div><div class='ctx'> 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];</div><div class='ctx'> 	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];</div><div class='ctx'> 	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];</div><div class='add'>+	struct dpu_hw_blk *cdm_blk;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * dpu_rm_init - Read hardware catalog and create reservation tracking objects</div><div class='ctx'>  *	for all HW blocks.</div><div class='add'>+ * @dev:  Corresponding device for devres management</div><div class='ctx'>  * @rm: DPU Resource Manager handle</div><div class='ctx'>  * @cat: Pointer to hardware catalog</div><div class='ctx'>  * @mdss_data: Pointer to MDSS / UBWC configuration</div><div class='ctx'>  * @mmio: mapped register io address of MDP</div><div class='ctx'>  * @Return: 0 on Success otherwise -ERROR</div><div class='ctx'>  */</div><div class='del'>-int dpu_rm_init(struct dpu_rm *rm,</div><div class='add'>+int dpu_rm_init(struct drm_device *dev,</div><div class='add'>+		struct dpu_rm *rm,</div><div class='ctx'> 		const struct dpu_mdss_cfg *cat,</div><div class='ctx'> 		const struct msm_mdss_data *mdss_data,</div><div class='ctx'> 		void __iomem *mmio);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dpu_rm_destroy - Free all memory allocated by dpu_rm_init</div><div class='del'>- * @rm: DPU Resource Manager handle</div><div class='del'>- * @Return: 0 on Success otherwise -ERROR</div><div class='del'>- */</div><div class='del'>-int dpu_rm_destroy(struct dpu_rm *rm);</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * dpu_rm_reserve - Given a CRTC-&gt;Encoder-&gt;Connector display chain, analyze</div><div class='ctx'>  *	the use connections and user requirements, specified through related</div><div class='ctx'>  *	topology control properties, and reserve hardware blocks to that</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c<br/>index 169f9de4a12a..75f93e346282 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_flip_work.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> #include &lt;drm/drm_mode.h&gt;</div><div class='ctx'> #include &lt;drm/drm_probe_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='hunk'>@@ -123,16 +124,6 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val)</div><div class='ctx'> 	drm_gem_object_put(val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp4_crtc_destroy(struct drm_crtc *crtc)</div><div class='del'>-{</div><div class='del'>-	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);</div><div class='del'>-</div><div class='del'>-	drm_crtc_cleanup(crtc);</div><div class='del'>-	drm_flip_work_cleanup(&amp;mdp4_crtc-&gt;unref_cursor_work);</div><div class='del'>-</div><div class='del'>-	kfree(mdp4_crtc);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* statically (for now) map planes to mixer stage (z-order): */</div><div class='ctx'> static const int idxs[] = {</div><div class='ctx'> 		[VG1]  = 1,</div><div class='hunk'>@@ -269,6 +260,7 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,</div><div class='ctx'> {</div><div class='ctx'> 	struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);</div><div class='ctx'> 	struct mdp4_kms *mdp4_kms = get_kms(crtc);</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	DBG("%s", mdp4_crtc-&gt;name);</div><div class='ctx'> </div><div class='hunk'>@@ -281,6 +273,14 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,</div><div class='ctx'> 	mdp_irq_unregister(&amp;mdp4_kms-&gt;base, &amp;mdp4_crtc-&gt;err);</div><div class='ctx'> 	mdp4_disable(mdp4_kms);</div><div class='ctx'> </div><div class='add'>+	if (crtc-&gt;state-&gt;event &amp;&amp; !crtc-&gt;state-&gt;active) {</div><div class='add'>+		WARN_ON(mdp4_crtc-&gt;event);</div><div class='add'>+		spin_lock_irqsave(&amp;mdp4_kms-&gt;dev-&gt;event_lock, flags);</div><div class='add'>+		drm_crtc_send_vblank_event(crtc, crtc-&gt;state-&gt;event);</div><div class='add'>+		crtc-&gt;state-&gt;event = NULL;</div><div class='add'>+		spin_unlock_irqrestore(&amp;mdp4_kms-&gt;dev-&gt;event_lock, flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	mdp4_crtc-&gt;enabled = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -475,7 +475,6 @@ static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)</div><div class='ctx'> </div><div class='ctx'> static const struct drm_crtc_funcs mdp4_crtc_funcs = {</div><div class='ctx'> 	.set_config = drm_atomic_helper_set_config,</div><div class='del'>-	.destroy = mdp4_crtc_destroy,</div><div class='ctx'> 	.page_flip = drm_atomic_helper_page_flip,</div><div class='ctx'> 	.cursor_set = mdp4_crtc_cursor_set,</div><div class='ctx'> 	.cursor_move = mdp4_crtc_cursor_move,</div><div class='hunk'>@@ -616,6 +615,13 @@ static const char *dma_names[] = {</div><div class='ctx'> 		"DMA_P", "DMA_S", "DMA_E",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void mdp4_crtc_flip_cleanup(struct drm_device *dev, void *ptr)</div><div class='add'>+{</div><div class='add'>+	struct mdp4_crtc *mdp4_crtc = ptr;</div><div class='add'>+</div><div class='add'>+	drm_flip_work_cleanup(&amp;mdp4_crtc-&gt;unref_cursor_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* initialize crtc */</div><div class='ctx'> struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,</div><div class='ctx'> 		struct drm_plane *plane, int id, int ovlp_id,</div><div class='hunk'>@@ -623,10 +629,13 @@ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_crtc *crtc = NULL;</div><div class='ctx'> 	struct mdp4_crtc *mdp4_crtc;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);</div><div class='del'>-	if (!mdp4_crtc)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	mdp4_crtc = drmm_crtc_alloc_with_planes(dev, struct mdp4_crtc, base,</div><div class='add'>+						plane, NULL,</div><div class='add'>+						&amp;mdp4_crtc_funcs, NULL);</div><div class='add'>+	if (IS_ERR(mdp4_crtc))</div><div class='add'>+		return ERR_CAST(mdp4_crtc);</div><div class='ctx'> </div><div class='ctx'> 	crtc = &amp;mdp4_crtc-&gt;base;</div><div class='ctx'> </div><div class='hunk'>@@ -648,9 +657,10 @@ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	drm_flip_work_init(&amp;mdp4_crtc-&gt;unref_cursor_work,</div><div class='ctx'> 			"unref cursor", unref_cursor_worker);</div><div class='add'>+	ret = drmm_add_action_or_reset(dev, mdp4_crtc_flip_cleanup, mdp4_crtc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='ctx'> </div><div class='del'>-	drm_crtc_init_with_planes(dev, crtc, plane, NULL, &amp;mdp4_crtc_funcs,</div><div class='del'>-				  NULL);</div><div class='ctx'> 	drm_crtc_helper_add(crtc, &amp;mdp4_crtc_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return crtc;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c<br/>index 39b8fe53c29d..74dafe7106be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c</a></div><div class='hunk'>@@ -26,18 +26,6 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder)</div><div class='ctx'> 	return to_mdp4_kms(to_mdp_kms(priv-&gt;kms));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp4_dsi_encoder_destroy(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct mdp4_dsi_encoder *mdp4_dsi_encoder = to_mdp4_dsi_encoder(encoder);</div><div class='del'>-</div><div class='del'>-	drm_encoder_cleanup(encoder);</div><div class='del'>-	kfree(mdp4_dsi_encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_funcs mdp4_dsi_encoder_funcs = {</div><div class='del'>-	.destroy = mdp4_dsi_encoder_destroy,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static void mdp4_dsi_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> 				      struct drm_display_mode *mode,</div><div class='ctx'> 				      struct drm_display_mode *adjusted_mode)</div><div class='hunk'>@@ -148,28 +136,18 @@ static const struct drm_encoder_helper_funcs mdp4_dsi_encoder_helper_funcs = {</div><div class='ctx'> /* initialize encoder */</div><div class='ctx'> struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct drm_encoder *encoder = NULL;</div><div class='add'>+	struct drm_encoder *encoder;</div><div class='ctx'> 	struct mdp4_dsi_encoder *mdp4_dsi_encoder;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp4_dsi_encoder = kzalloc(sizeof(*mdp4_dsi_encoder), GFP_KERNEL);</div><div class='del'>-	if (!mdp4_dsi_encoder) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='add'>+	mdp4_dsi_encoder = drmm_encoder_alloc(dev, struct mdp4_dsi_encoder, base,</div><div class='add'>+					      NULL, DRM_MODE_ENCODER_DSI, NULL);</div><div class='add'>+	if (IS_ERR(mdp4_dsi_encoder))</div><div class='add'>+		return ERR_CAST(mdp4_dsi_encoder);</div><div class='ctx'> </div><div class='ctx'> 	encoder = &amp;mdp4_dsi_encoder-&gt;base;</div><div class='ctx'> </div><div class='del'>-	drm_encoder_init(dev, encoder, &amp;mdp4_dsi_encoder_funcs,</div><div class='del'>-			 DRM_MODE_ENCODER_DSI, NULL);</div><div class='ctx'> 	drm_encoder_helper_add(encoder, &amp;mdp4_dsi_encoder_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return encoder;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (encoder)</div><div class='del'>-		mdp4_dsi_encoder_destroy(encoder);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='ctx'> #endif /* CONFIG_DRM_MSM_DSI */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c<br/>index 88645dbc3785..3b70764b48c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c</a></div><div class='hunk'>@@ -25,17 +25,6 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder)</div><div class='ctx'> 	return to_mdp4_kms(to_mdp_kms(priv-&gt;kms));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);</div><div class='del'>-	drm_encoder_cleanup(encoder);</div><div class='del'>-	kfree(mdp4_dtv_encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = {</div><div class='del'>-	.destroy = mdp4_dtv_encoder_destroy,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> 		struct drm_display_mode *mode,</div><div class='ctx'> 		struct drm_display_mode *adjusted_mode)</div><div class='hunk'>@@ -173,41 +162,29 @@ long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate)</div><div class='ctx'> /* initialize encoder */</div><div class='ctx'> struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct drm_encoder *encoder = NULL;</div><div class='add'>+	struct drm_encoder *encoder;</div><div class='ctx'> 	struct mdp4_dtv_encoder *mdp4_dtv_encoder;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL);</div><div class='del'>-	if (!mdp4_dtv_encoder) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='add'>+	mdp4_dtv_encoder = drmm_encoder_alloc(dev, struct mdp4_dtv_encoder, base,</div><div class='add'>+					      NULL, DRM_MODE_ENCODER_TMDS, NULL);</div><div class='add'>+	if (IS_ERR(mdp4_dtv_encoder))</div><div class='add'>+		return ERR_CAST(mdp4_dtv_encoder);</div><div class='ctx'> </div><div class='ctx'> 	encoder = &amp;mdp4_dtv_encoder-&gt;base;</div><div class='ctx'> </div><div class='del'>-	drm_encoder_init(dev, encoder, &amp;mdp4_dtv_encoder_funcs,</div><div class='del'>-			 DRM_MODE_ENCODER_TMDS, NULL);</div><div class='ctx'> 	drm_encoder_helper_add(encoder, &amp;mdp4_dtv_encoder_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	mdp4_dtv_encoder-&gt;hdmi_clk = devm_clk_get(dev-&gt;dev, "hdmi_clk");</div><div class='ctx'> 	if (IS_ERR(mdp4_dtv_encoder-&gt;hdmi_clk)) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "failed to get hdmi_clk\n");</div><div class='del'>-		ret = PTR_ERR(mdp4_dtv_encoder-&gt;hdmi_clk);</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_CAST(mdp4_dtv_encoder-&gt;hdmi_clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mdp4_dtv_encoder-&gt;mdp_clk = devm_clk_get(dev-&gt;dev, "tv_clk");</div><div class='ctx'> 	if (IS_ERR(mdp4_dtv_encoder-&gt;mdp_clk)) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "failed to get tv_clk\n");</div><div class='del'>-		ret = PTR_ERR(mdp4_dtv_encoder-&gt;mdp_clk);</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_CAST(mdp4_dtv_encoder-&gt;mdp_clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return encoder;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (encoder)</div><div class='del'>-		mdp4_dtv_encoder_destroy(encoder);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c<br/>index 10eb3e5b218e..576995ddce37 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c</a></div><div class='hunk'>@@ -18,7 +18,7 @@ struct mdp4_lcdc_encoder {</div><div class='ctx'> 	struct drm_panel *panel;</div><div class='ctx'> 	struct clk *lcdc_clk;</div><div class='ctx'> 	unsigned long int pixclock;</div><div class='del'>-	struct regulator *regs[3];</div><div class='add'>+	struct regulator_bulk_data regs[3];</div><div class='ctx'> 	bool enabled;</div><div class='ctx'> 	uint32_t bsc;</div><div class='ctx'> };</div><div class='hunk'>@@ -30,18 +30,6 @@ static struct mdp4_kms *get_kms(struct drm_encoder *encoder)</div><div class='ctx'> 	return to_mdp4_kms(to_mdp_kms(priv-&gt;kms));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp4_lcdc_encoder_destroy(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =</div><div class='del'>-			to_mdp4_lcdc_encoder(encoder);</div><div class='del'>-	drm_encoder_cleanup(encoder);</div><div class='del'>-	kfree(mdp4_lcdc_encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_funcs mdp4_lcdc_encoder_funcs = {</div><div class='del'>-	.destroy = mdp4_lcdc_encoder_destroy,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* this should probably be a helper: */</div><div class='ctx'> static struct drm_connector *get_connector(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='hunk'>@@ -271,12 +259,10 @@ static void mdp4_lcdc_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> </div><div class='ctx'> static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)</div><div class='ctx'> {</div><div class='del'>-	struct drm_device *dev = encoder-&gt;dev;</div><div class='ctx'> 	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =</div><div class='ctx'> 			to_mdp4_lcdc_encoder(encoder);</div><div class='ctx'> 	struct mdp4_kms *mdp4_kms = get_kms(encoder);</div><div class='ctx'> 	struct drm_panel *panel;</div><div class='del'>-	int i, ret;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(!mdp4_lcdc_encoder-&gt;enabled))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -301,11 +287,8 @@ static void mdp4_lcdc_encoder_disable(struct drm_encoder *encoder)</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(mdp4_lcdc_encoder-&gt;lcdc_clk);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(mdp4_lcdc_encoder-&gt;regs); i++) {</div><div class='del'>-		ret = regulator_disable(mdp4_lcdc_encoder-&gt;regs[i]);</div><div class='del'>-		if (ret)</div><div class='del'>-			DRM_DEV_ERROR(dev-&gt;dev, "failed to disable regulator: %d\n", ret);</div><div class='del'>-	}</div><div class='add'>+	regulator_bulk_disable(ARRAY_SIZE(mdp4_lcdc_encoder-&gt;regs),</div><div class='add'>+			       mdp4_lcdc_encoder-&gt;regs);</div><div class='ctx'> </div><div class='ctx'> 	mdp4_lcdc_encoder-&gt;enabled = false;</div><div class='ctx'> }</div><div class='hunk'>@@ -319,7 +302,7 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)</div><div class='ctx'> 	struct mdp4_kms *mdp4_kms = get_kms(encoder);</div><div class='ctx'> 	struct drm_panel *panel;</div><div class='ctx'> 	uint32_t config;</div><div class='del'>-	int i, ret;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(mdp4_lcdc_encoder-&gt;enabled))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -339,11 +322,10 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)</div><div class='ctx'> 	mdp4_crtc_set_config(encoder-&gt;crtc, config);</div><div class='ctx'> 	mdp4_crtc_set_intf(encoder-&gt;crtc, INTF_LCDC_DTV, 0);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(mdp4_lcdc_encoder-&gt;regs); i++) {</div><div class='del'>-		ret = regulator_enable(mdp4_lcdc_encoder-&gt;regs[i]);</div><div class='del'>-		if (ret)</div><div class='del'>-			DRM_DEV_ERROR(dev-&gt;dev, "failed to enable regulator: %d\n", ret);</div><div class='del'>-	}</div><div class='add'>+	ret = regulator_bulk_enable(ARRAY_SIZE(mdp4_lcdc_encoder-&gt;regs),</div><div class='add'>+				    mdp4_lcdc_encoder-&gt;regs);</div><div class='add'>+	if (ret)</div><div class='add'>+		DRM_DEV_ERROR(dev-&gt;dev, "failed to enable regulators: %d\n", ret);</div><div class='ctx'> </div><div class='ctx'> 	DBG("setting lcdc_clk=%lu", pc);</div><div class='ctx'> 	ret = clk_set_rate(mdp4_lcdc_encoder-&gt;lcdc_clk, pc);</div><div class='hunk'>@@ -383,63 +365,38 @@ long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate)</div><div class='ctx'> struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,</div><div class='ctx'> 		struct device_node *panel_node)</div><div class='ctx'> {</div><div class='del'>-	struct drm_encoder *encoder = NULL;</div><div class='add'>+	struct drm_encoder *encoder;</div><div class='ctx'> 	struct mdp4_lcdc_encoder *mdp4_lcdc_encoder;</div><div class='del'>-	struct regulator *reg;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp4_lcdc_encoder = kzalloc(sizeof(*mdp4_lcdc_encoder), GFP_KERNEL);</div><div class='del'>-	if (!mdp4_lcdc_encoder) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='add'>+	mdp4_lcdc_encoder = drmm_encoder_alloc(dev, struct mdp4_lcdc_encoder, base,</div><div class='add'>+					       NULL, DRM_MODE_ENCODER_LVDS, NULL);</div><div class='add'>+	if (IS_ERR(mdp4_lcdc_encoder))</div><div class='add'>+		return ERR_CAST(mdp4_lcdc_encoder);</div><div class='ctx'> </div><div class='ctx'> 	mdp4_lcdc_encoder-&gt;panel_node = panel_node;</div><div class='ctx'> </div><div class='ctx'> 	encoder = &amp;mdp4_lcdc_encoder-&gt;base;</div><div class='ctx'> </div><div class='del'>-	drm_encoder_init(dev, encoder, &amp;mdp4_lcdc_encoder_funcs,</div><div class='del'>-			 DRM_MODE_ENCODER_LVDS, NULL);</div><div class='ctx'> 	drm_encoder_helper_add(encoder, &amp;mdp4_lcdc_encoder_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: do we need different pll in other cases? */</div><div class='ctx'> 	mdp4_lcdc_encoder-&gt;lcdc_clk = mpd4_lvds_pll_init(dev);</div><div class='ctx'> 	if (IS_ERR(mdp4_lcdc_encoder-&gt;lcdc_clk)) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "failed to get lvds_clk\n");</div><div class='del'>-		ret = PTR_ERR(mdp4_lcdc_encoder-&gt;lcdc_clk);</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_CAST(mdp4_lcdc_encoder-&gt;lcdc_clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: different regulators in other cases? */</div><div class='del'>-	reg = devm_regulator_get(dev-&gt;dev, "lvds-vccs-3p3v");</div><div class='del'>-	if (IS_ERR(reg)) {</div><div class='del'>-		ret = PTR_ERR(reg);</div><div class='del'>-		DRM_DEV_ERROR(dev-&gt;dev, "failed to get lvds-vccs-3p3v: %d\n", ret);</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='del'>-	mdp4_lcdc_encoder-&gt;regs[0] = reg;</div><div class='del'>-</div><div class='del'>-	reg = devm_regulator_get(dev-&gt;dev, "lvds-pll-vdda");</div><div class='del'>-	if (IS_ERR(reg)) {</div><div class='del'>-		ret = PTR_ERR(reg);</div><div class='del'>-		DRM_DEV_ERROR(dev-&gt;dev, "failed to get lvds-pll-vdda: %d\n", ret);</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='del'>-	mdp4_lcdc_encoder-&gt;regs[1] = reg;</div><div class='add'>+	mdp4_lcdc_encoder-&gt;regs[0].supply = "lvds-vccs-3p3v";</div><div class='add'>+	mdp4_lcdc_encoder-&gt;regs[1].supply = "lvds-vccs-3p3v";</div><div class='add'>+	mdp4_lcdc_encoder-&gt;regs[2].supply = "lvds-vdda";</div><div class='ctx'> </div><div class='del'>-	reg = devm_regulator_get(dev-&gt;dev, "lvds-vdda");</div><div class='del'>-	if (IS_ERR(reg)) {</div><div class='del'>-		ret = PTR_ERR(reg);</div><div class='del'>-		DRM_DEV_ERROR(dev-&gt;dev, "failed to get lvds-vdda: %d\n", ret);</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='del'>-	mdp4_lcdc_encoder-&gt;regs[2] = reg;</div><div class='add'>+	ret = devm_regulator_bulk_get(dev-&gt;dev,</div><div class='add'>+				      ARRAY_SIZE(mdp4_lcdc_encoder-&gt;regs),</div><div class='add'>+				      mdp4_lcdc_encoder-&gt;regs);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='ctx'> </div><div class='ctx'> 	return encoder;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (encoder)</div><div class='del'>-		mdp4_lcdc_encoder_destroy(encoder);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c<br/>index 694d54341337..c5179e4c393c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c</a></div><div class='hunk'>@@ -1350,23 +1350,17 @@ int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)</div><div class='ctx'> 	return cfg_handler-&gt;revision;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)</div><div class='del'>-{</div><div class='del'>-	kfree(cfg_handler);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 		uint32_t major, uint32_t minor)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = mdp5_kms-&gt;dev;</div><div class='ctx'> 	struct mdp5_cfg_handler *cfg_handler;</div><div class='ctx'> 	const struct mdp5_cfg_handler *cfg_handlers;</div><div class='del'>-	int i, ret = 0, num_handlers;</div><div class='add'>+	int i, num_handlers;</div><div class='ctx'> </div><div class='del'>-	cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);</div><div class='add'>+	cfg_handler = devm_kzalloc(dev-&gt;dev, sizeof(*cfg_handler), GFP_KERNEL);</div><div class='ctx'> 	if (unlikely(!cfg_handler)) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (major) {</div><div class='hunk'>@@ -1381,8 +1375,7 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 	default:</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "unexpected MDP major version: v%d.%d\n",</div><div class='ctx'> 				major, minor);</div><div class='del'>-		ret = -ENXIO;</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_PTR(-ENXIO);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* only after mdp5_cfg global pointer's init can we access the hw */</div><div class='hunk'>@@ -1396,8 +1389,7 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 	if (unlikely(!mdp5_cfg)) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "unexpected MDP minor revision: v%d.%d\n",</div><div class='ctx'> 				major, minor);</div><div class='del'>-		ret = -ENXIO;</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_PTR(-ENXIO);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cfg_handler-&gt;revision = minor;</div><div class='hunk'>@@ -1406,10 +1398,4 @@ struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 	DBG("MDP5: %s hw config selected", mdp5_cfg-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 	return cfg_handler;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (cfg_handler)</div><div class='del'>-		mdp5_cfg_destroy(cfg_handler);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h<br/>index c2502cc33864..26c5d8b4ab46 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h</a></div><div class='hunk'>@@ -121,6 +121,5 @@ int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);</div><div class='ctx'> </div><div class='ctx'> struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 		uint32_t major, uint32_t minor);</div><div class='del'>-void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);</div><div class='ctx'> </div><div class='ctx'> #endif /* __MDP5_CFG_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c<br/>index 86036dd4e1e8..4a3db2ea1689 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_flip_work.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> #include &lt;drm/drm_probe_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -172,14 +173,11 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val)</div><div class='ctx'> 	drm_gem_object_put(val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp5_crtc_destroy(struct drm_crtc *crtc)</div><div class='add'>+static void mdp5_crtc_flip_cleanup(struct drm_device *dev, void *ptr)</div><div class='ctx'> {</div><div class='del'>-	struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);</div><div class='add'>+	struct mdp5_crtc *mdp5_crtc = ptr;</div><div class='ctx'> </div><div class='del'>-	drm_crtc_cleanup(crtc);</div><div class='ctx'> 	drm_flip_work_cleanup(&amp;mdp5_crtc-&gt;unref_cursor_work);</div><div class='del'>-</div><div class='del'>-	kfree(mdp5_crtc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage)</div><div class='hunk'>@@ -1147,7 +1145,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc)</div><div class='ctx'> </div><div class='ctx'> static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {</div><div class='ctx'> 	.set_config = drm_atomic_helper_set_config,</div><div class='del'>-	.destroy = mdp5_crtc_destroy,</div><div class='ctx'> 	.page_flip = drm_atomic_helper_page_flip,</div><div class='ctx'> 	.reset = mdp5_crtc_reset,</div><div class='ctx'> 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,</div><div class='hunk'>@@ -1161,7 +1158,6 @@ static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {</div><div class='ctx'> </div><div class='ctx'> static const struct drm_crtc_funcs mdp5_crtc_funcs = {</div><div class='ctx'> 	.set_config = drm_atomic_helper_set_config,</div><div class='del'>-	.destroy = mdp5_crtc_destroy,</div><div class='ctx'> 	.page_flip = drm_atomic_helper_page_flip,</div><div class='ctx'> 	.reset = mdp5_crtc_reset,</div><div class='ctx'> 	.atomic_duplicate_state = mdp5_crtc_duplicate_state,</div><div class='hunk'>@@ -1327,10 +1323,16 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_crtc *crtc = NULL;</div><div class='ctx'> 	struct mdp5_crtc *mdp5_crtc;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);</div><div class='del'>-	if (!mdp5_crtc)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	mdp5_crtc = drmm_crtc_alloc_with_planes(dev, struct mdp5_crtc, base,</div><div class='add'>+						plane, cursor_plane,</div><div class='add'>+						cursor_plane ?</div><div class='add'>+						&amp;mdp5_crtc_no_lm_cursor_funcs :</div><div class='add'>+						&amp;mdp5_crtc_funcs,</div><div class='add'>+						NULL);</div><div class='add'>+	if (IS_ERR(mdp5_crtc))</div><div class='add'>+		return ERR_CAST(mdp5_crtc);</div><div class='ctx'> </div><div class='ctx'> 	crtc = &amp;mdp5_crtc-&gt;base;</div><div class='ctx'> </div><div class='hunk'>@@ -1346,13 +1348,11 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	mdp5_crtc-&gt;lm_cursor_enabled = cursor_plane ? false : true;</div><div class='ctx'> </div><div class='del'>-	drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane,</div><div class='del'>-				  cursor_plane ?</div><div class='del'>-				  &amp;mdp5_crtc_no_lm_cursor_funcs :</div><div class='del'>-				  &amp;mdp5_crtc_funcs, NULL);</div><div class='del'>-</div><div class='ctx'> 	drm_flip_work_init(&amp;mdp5_crtc-&gt;unref_cursor_work,</div><div class='ctx'> 			"unref cursor", unref_cursor_worker);</div><div class='add'>+	ret = drmm_add_action_or_reset(dev, mdp5_crtc_flip_cleanup, mdp5_crtc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='ctx'> </div><div class='ctx'> 	drm_crtc_helper_add(crtc, &amp;mdp5_crtc_helper_funcs);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c<br/>index 1220f2b20e05..666de99a46a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c</a></div><div class='hunk'>@@ -681,11 +681,6 @@ void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctl_mgr)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctl_mgr)</div><div class='del'>-{</div><div class='del'>-	kfree(ctl_mgr);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,</div><div class='ctx'> 		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd)</div><div class='ctx'> {</div><div class='hunk'>@@ -697,18 +692,16 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	int c, ret;</div><div class='ctx'> </div><div class='del'>-	ctl_mgr = kzalloc(sizeof(*ctl_mgr), GFP_KERNEL);</div><div class='add'>+	ctl_mgr = devm_kzalloc(dev-&gt;dev, sizeof(*ctl_mgr), GFP_KERNEL);</div><div class='ctx'> 	if (!ctl_mgr) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "failed to allocate CTL manager\n");</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(ctl_cfg-&gt;count &gt; MAX_CTL)) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev, "Increase static pool size to at least %d\n",</div><div class='ctx'> 				ctl_cfg-&gt;count);</div><div class='del'>-		ret = -ENOSPC;</div><div class='del'>-		goto fail;</div><div class='add'>+		return ERR_PTR(-ENOSPC);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* initialize the CTL manager: */</div><div class='hunk'>@@ -727,7 +720,7 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,</div><div class='ctx'> 			DRM_DEV_ERROR(dev-&gt;dev, "CTL_%d: base is null!\n", c);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			spin_unlock_irqrestore(&amp;ctl_mgr-&gt;pool_lock, flags);</div><div class='del'>-			goto fail;</div><div class='add'>+			return ERR_PTR(ret);</div><div class='ctx'> 		}</div><div class='ctx'> 		ctl-&gt;ctlm = ctl_mgr;</div><div class='ctx'> 		ctl-&gt;id = c;</div><div class='hunk'>@@ -755,10 +748,4 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,</div><div class='ctx'> 	DBG("Pool of %d CTLs created.", ctl_mgr-&gt;nctl);</div><div class='ctx'> </div><div class='ctx'> 	return ctl_mgr;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (ctl_mgr)</div><div class='del'>-		mdp5_ctlm_destroy(ctl_mgr);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h<br/>index c2af68aa77ae..9020e8efc4e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h</a></div><div class='hunk'>@@ -17,7 +17,6 @@ struct mdp5_ctl_manager;</div><div class='ctx'> struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,</div><div class='ctx'> 		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);</div><div class='ctx'> void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);</div><div class='del'>-void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * CTL prototypes:</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c<br/>index 79d67c495780..8db97083e14d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c</a></div><div class='hunk'>@@ -16,17 +16,6 @@ static struct mdp5_kms *get_kms(struct drm_encoder *encoder)</div><div class='ctx'> 	return to_mdp5_kms(to_mdp_kms(priv-&gt;kms));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mdp5_encoder_destroy(struct drm_encoder *encoder)</div><div class='del'>-{</div><div class='del'>-	struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);</div><div class='del'>-	drm_encoder_cleanup(encoder);</div><div class='del'>-	kfree(mdp5_encoder);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct drm_encoder_funcs mdp5_encoder_funcs = {</div><div class='del'>-	.destroy = mdp5_encoder_destroy,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder,</div><div class='ctx'> 				      struct drm_display_mode *mode,</div><div class='ctx'> 				      struct drm_display_mode *adjusted_mode)</div><div class='hunk'>@@ -342,13 +331,11 @@ struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,</div><div class='ctx'> 	struct mdp5_encoder *mdp5_encoder;</div><div class='ctx'> 	int enc_type = (intf-&gt;type == INTF_DSI) ?</div><div class='ctx'> 		DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='del'>-	mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);</div><div class='del'>-	if (!mdp5_encoder) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='add'>+	mdp5_encoder = drmm_encoder_alloc(dev, struct mdp5_encoder, base,</div><div class='add'>+					  NULL, enc_type, NULL);</div><div class='add'>+	if (IS_ERR(mdp5_encoder))</div><div class='add'>+		return ERR_CAST(mdp5_encoder);</div><div class='ctx'> </div><div class='ctx'> 	encoder = &amp;mdp5_encoder-&gt;base;</div><div class='ctx'> 	mdp5_encoder-&gt;ctl = ctl;</div><div class='hunk'>@@ -356,15 +343,7 @@ struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;mdp5_encoder-&gt;intf_lock);</div><div class='ctx'> </div><div class='del'>-	drm_encoder_init(dev, encoder, &amp;mdp5_encoder_funcs, enc_type, NULL);</div><div class='del'>-</div><div class='ctx'> 	drm_encoder_helper_add(encoder, &amp;mdp5_encoder_helper_funcs);</div><div class='ctx'> </div><div class='ctx'> 	return encoder;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	if (encoder)</div><div class='del'>-		mdp5_encoder_destroy(encoder);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c<br/>index ec933d597e20..0827634664ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c</a></div><div class='hunk'>@@ -209,13 +209,6 @@ static void mdp5_kms_destroy(struct msm_kms *kms)</div><div class='ctx'> {</div><div class='ctx'> 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));</div><div class='ctx'> 	struct msm_gem_address_space *aspace = kms-&gt;aspace;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mdp5_kms-&gt;num_hwmixers; i++)</div><div class='del'>-		mdp5_mixer_destroy(mdp5_kms-&gt;hwmixers[i]);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mdp5_kms-&gt;num_hwpipes; i++)</div><div class='del'>-		mdp5_pipe_destroy(mdp5_kms-&gt;hwpipes[i]);</div><div class='ctx'> </div><div class='ctx'> 	if (aspace) {</div><div class='ctx'> 		aspace-&gt;mmu-&gt;funcs-&gt;detach(aspace-&gt;mmu);</div><div class='hunk'>@@ -623,18 +616,6 @@ fail:</div><div class='ctx'> </div><div class='ctx'> static void mdp5_destroy(struct mdp5_kms *mdp5_kms)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (mdp5_kms-&gt;ctlm)</div><div class='del'>-		mdp5_ctlm_destroy(mdp5_kms-&gt;ctlm);</div><div class='del'>-	if (mdp5_kms-&gt;smp)</div><div class='del'>-		mdp5_smp_destroy(mdp5_kms-&gt;smp);</div><div class='del'>-	if (mdp5_kms-&gt;cfg)</div><div class='del'>-		mdp5_cfg_destroy(mdp5_kms-&gt;cfg);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mdp5_kms-&gt;num_intfs; i++)</div><div class='del'>-		kfree(mdp5_kms-&gt;intfs[i]);</div><div class='del'>-</div><div class='ctx'> 	if (mdp5_kms-&gt;rpm_enabled)</div><div class='ctx'> 		pm_runtime_disable(&amp;mdp5_kms-&gt;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -652,7 +633,7 @@ static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,</div><div class='ctx'> 	for (i = 0; i &lt; cnt; i++) {</div><div class='ctx'> 		struct mdp5_hw_pipe *hwpipe;</div><div class='ctx'> </div><div class='del'>-		hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps);</div><div class='add'>+		hwpipe = mdp5_pipe_init(dev, pipes[i], offsets[i], caps);</div><div class='ctx'> 		if (IS_ERR(hwpipe)) {</div><div class='ctx'> 			ret = PTR_ERR(hwpipe);</div><div class='ctx'> 			DRM_DEV_ERROR(dev-&gt;dev, "failed to construct pipe for %s (%d)\n",</div><div class='hunk'>@@ -724,7 +705,7 @@ static int hwmixer_init(struct mdp5_kms *mdp5_kms)</div><div class='ctx'> 	for (i = 0; i &lt; hw_cfg-&gt;lm.count; i++) {</div><div class='ctx'> 		struct mdp5_hw_mixer *mixer;</div><div class='ctx'> </div><div class='del'>-		mixer = mdp5_mixer_init(&amp;hw_cfg-&gt;lm.instances[i]);</div><div class='add'>+		mixer = mdp5_mixer_init(dev, &amp;hw_cfg-&gt;lm.instances[i]);</div><div class='ctx'> 		if (IS_ERR(mixer)) {</div><div class='ctx'> 			ret = PTR_ERR(mixer);</div><div class='ctx'> 			DRM_DEV_ERROR(dev-&gt;dev, "failed to construct LM%d (%d)\n",</div><div class='hunk'>@@ -755,7 +736,7 @@ static int interface_init(struct mdp5_kms *mdp5_kms)</div><div class='ctx'> 		if (intf_types[i] == INTF_DISABLED)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		intf = kzalloc(sizeof(*intf), GFP_KERNEL);</div><div class='add'>+		intf = devm_kzalloc(dev-&gt;dev, sizeof(*intf), GFP_KERNEL);</div><div class='ctx'> 		if (!intf) {</div><div class='ctx'> 			DRM_DEV_ERROR(dev-&gt;dev, "failed to construct INTF%d\n", i);</div><div class='ctx'> 			return -ENOMEM;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c<br/>index 2536def2a000..2822b533f807 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c</a></div><div class='hunk'>@@ -140,20 +140,16 @@ int mdp5_mixer_release(struct drm_atomic_state *s, struct mdp5_hw_mixer *mixer)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mdp5_mixer_destroy(struct mdp5_hw_mixer *mixer)</div><div class='del'>-{</div><div class='del'>-	kfree(mixer);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const char * const mixer_names[] = {</div><div class='ctx'> 	"LM0", "LM1", "LM2", "LM3", "LM4", "LM5",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct mdp5_hw_mixer *mdp5_mixer_init(const struct mdp5_lm_instance *lm)</div><div class='add'>+struct mdp5_hw_mixer *mdp5_mixer_init(struct drm_device *dev,</div><div class='add'>+				      const struct mdp5_lm_instance *lm)</div><div class='ctx'> {</div><div class='ctx'> 	struct mdp5_hw_mixer *mixer;</div><div class='ctx'> </div><div class='del'>-	mixer = kzalloc(sizeof(*mixer), GFP_KERNEL);</div><div class='add'>+	mixer = devm_kzalloc(dev-&gt;dev, sizeof(*mixer), GFP_KERNEL);</div><div class='ctx'> 	if (!mixer)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h<br/>index 545ee223b9d7..2bedd75835bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h</a></div><div class='hunk'>@@ -25,8 +25,8 @@ struct mdp5_hw_mixer_state {</div><div class='ctx'> 	struct drm_crtc *hwmixer_to_crtc[8];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct mdp5_hw_mixer *mdp5_mixer_init(const struct mdp5_lm_instance *lm);</div><div class='del'>-void mdp5_mixer_destroy(struct mdp5_hw_mixer *lm);</div><div class='add'>+struct mdp5_hw_mixer *mdp5_mixer_init(struct drm_device *dev,</div><div class='add'>+				      const struct mdp5_lm_instance *lm);</div><div class='ctx'> int mdp5_mixer_assign(struct drm_atomic_state *s, struct drm_crtc *crtc,</div><div class='ctx'> 		      uint32_t caps, struct mdp5_hw_mixer **mixer,</div><div class='ctx'> 		      struct mdp5_hw_mixer **r_mixer);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c<br/>index e4b8a789835a..99b2c30b1d48 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c</a></div><div class='hunk'>@@ -151,17 +151,13 @@ int mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mdp5_pipe_destroy(struct mdp5_hw_pipe *hwpipe)</div><div class='del'>-{</div><div class='del'>-	kfree(hwpipe);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe,</div><div class='add'>+struct mdp5_hw_pipe *mdp5_pipe_init(struct drm_device *dev,</div><div class='add'>+		enum mdp5_pipe pipe,</div><div class='ctx'> 		uint32_t reg_offset, uint32_t caps)</div><div class='ctx'> {</div><div class='ctx'> 	struct mdp5_hw_pipe *hwpipe;</div><div class='ctx'> </div><div class='del'>-	hwpipe = kzalloc(sizeof(*hwpipe), GFP_KERNEL);</div><div class='add'>+	hwpipe = devm_kzalloc(dev-&gt;dev, sizeof(*hwpipe), GFP_KERNEL);</div><div class='ctx'> 	if (!hwpipe)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h<br/>index cca67938cab2..452138821f60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h</a></div><div class='hunk'>@@ -39,8 +39,8 @@ int mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane,</div><div class='ctx'> 		     struct mdp5_hw_pipe **r_hwpipe);</div><div class='ctx'> int mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe);</div><div class='ctx'> </div><div class='del'>-struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe,</div><div class='add'>+struct mdp5_hw_pipe *mdp5_pipe_init(struct drm_device *dev,</div><div class='add'>+		enum mdp5_pipe pipe,</div><div class='ctx'> 		uint32_t reg_offset, uint32_t caps);</div><div class='del'>-void mdp5_pipe_destroy(struct mdp5_hw_pipe *hwpipe);</div><div class='ctx'> </div><div class='ctx'> #endif /* __MDP5_PIPE_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c<br/>index b68682c1b5bc..8b59562e29e2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c</a></div><div class='hunk'>@@ -370,23 +370,17 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p)</div><div class='ctx'> 		drm_modeset_unlock(&amp;mdp5_kms-&gt;glob_state_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mdp5_smp_destroy(struct mdp5_smp *smp)</div><div class='del'>-{</div><div class='del'>-	kfree(smp);</div><div class='del'>-}</div><div class='ctx'> </div><div class='ctx'> struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_block *cfg)</div><div class='ctx'> {</div><div class='add'>+	struct drm_device *dev = mdp5_kms-&gt;dev;</div><div class='ctx'> 	struct mdp5_smp_state *state;</div><div class='ctx'> 	struct mdp5_global_state *global_state;</div><div class='ctx'> 	struct mdp5_smp *smp;</div><div class='del'>-	int ret;</div><div class='ctx'> </div><div class='del'>-	smp = kzalloc(sizeof(*smp), GFP_KERNEL);</div><div class='del'>-	if (unlikely(!smp)) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto fail;</div><div class='del'>-	}</div><div class='add'>+	smp = devm_kzalloc(dev-&gt;dev, sizeof(*smp), GFP_KERNEL);</div><div class='add'>+	if (unlikely(!smp))</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='ctx'> 	smp-&gt;dev = mdp5_kms-&gt;dev;</div><div class='ctx'> 	smp-&gt;blk_cnt = cfg-&gt;mmb_count;</div><div class='hunk'>@@ -400,9 +394,4 @@ struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_</div><div class='ctx'> 	memcpy(smp-&gt;reserved, cfg-&gt;reserved, sizeof(smp-&gt;reserved));</div><div class='ctx'> </div><div class='ctx'> 	return smp;</div><div class='del'>-fail:</div><div class='del'>-	if (smp)</div><div class='del'>-		mdp5_smp_destroy(smp);</div><div class='del'>-</div><div class='del'>-	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h<br/>index ba5618e136c3..d8b6a11413d9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h</a></div><div class='hunk'>@@ -68,7 +68,6 @@ struct mdp5_smp;</div><div class='ctx'> </div><div class='ctx'> struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms,</div><div class='ctx'> 		const struct mdp5_smp_block *cfg);</div><div class='del'>-void  mdp5_smp_destroy(struct mdp5_smp *smp);</div><div class='ctx'> </div><div class='ctx'> void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c<br/>index 8e3b677f35e6..03f4951c49f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_aux.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_aux.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_aux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_aux.c</a></div><div class='hunk'>@@ -291,6 +291,10 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = pm_runtime_resume_and_get(dp_aux-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return  ret;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;aux-&gt;mutex);</div><div class='ctx'> 	if (!aux-&gt;initted) {</div><div class='ctx'> 		ret = -EIO;</div><div class='hunk'>@@ -364,6 +368,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,</div><div class='ctx'> </div><div class='ctx'> exit:</div><div class='ctx'> 	mutex_unlock(&amp;aux-&gt;mutex);</div><div class='add'>+	pm_runtime_put_sync(dp_aux-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -474,7 +479,6 @@ void dp_aux_deinit(struct drm_dp_aux *dp_aux)</div><div class='ctx'> </div><div class='ctx'> int dp_aux_register(struct drm_dp_aux *dp_aux)</div><div class='ctx'> {</div><div class='del'>-	struct dp_aux_private *aux;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!dp_aux) {</div><div class='hunk'>@@ -482,12 +486,7 @@ int dp_aux_register(struct drm_dp_aux *dp_aux)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);</div><div class='del'>-</div><div class='del'>-	aux-&gt;dp_aux.name = "dpu_dp_aux";</div><div class='del'>-	aux-&gt;dp_aux.dev = aux-&gt;dev;</div><div class='del'>-	aux-&gt;dp_aux.transfer = dp_aux_transfer;</div><div class='del'>-	ret = drm_dp_aux_register(&amp;aux-&gt;dp_aux);</div><div class='add'>+	ret = drm_dp_aux_register(dp_aux);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_ERROR("%s: failed to register drm aux: %d\n", __func__,</div><div class='ctx'> 				ret);</div><div class='hunk'>@@ -502,6 +501,21 @@ void dp_aux_unregister(struct drm_dp_aux *dp_aux)</div><div class='ctx'> 	drm_dp_aux_unregister(dp_aux);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dp_wait_hpd_asserted(struct drm_dp_aux *dp_aux,</div><div class='add'>+				 unsigned long wait_us)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct dp_aux_private *aux;</div><div class='add'>+</div><div class='add'>+	aux = container_of(dp_aux, struct dp_aux_private, dp_aux);</div><div class='add'>+</div><div class='add'>+	pm_runtime_get_sync(aux-&gt;dev);</div><div class='add'>+	ret = dp_catalog_aux_wait_for_hpd_connect_state(aux-&gt;catalog);</div><div class='add'>+	pm_runtime_put_sync(aux-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,</div><div class='ctx'> 			      bool is_edp)</div><div class='ctx'> {</div><div class='hunk'>@@ -525,6 +539,17 @@ struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog,</div><div class='ctx'> 	aux-&gt;catalog = catalog;</div><div class='ctx'> 	aux-&gt;retry_cnt = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Use the drm_dp_aux_init() to use the aux adapter</div><div class='add'>+	 * before registering AUX with the DRM device so that</div><div class='add'>+	 * msm eDP panel can be detected by generic_dep_panel_probe().</div><div class='add'>+	 */</div><div class='add'>+	aux-&gt;dp_aux.name = "dpu_dp_aux";</div><div class='add'>+	aux-&gt;dp_aux.dev = dev;</div><div class='add'>+	aux-&gt;dp_aux.transfer = dp_aux_transfer;</div><div class='add'>+	aux-&gt;dp_aux.wait_hpd_asserted = dp_wait_hpd_asserted;</div><div class='add'>+	drm_dp_aux_init(&amp;aux-&gt;dp_aux);</div><div class='add'>+</div><div class='ctx'> 	return &amp;aux-&gt;dp_aux;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c<br/>index 3bba901afe33..6c281dc095b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_debug.c</a></div><div class='hunk'>@@ -19,13 +19,9 @@</div><div class='ctx'> #define DEBUG_NAME "msm_dp"</div><div class='ctx'> </div><div class='ctx'> struct dp_debug_private {</div><div class='del'>-	struct dentry *root;</div><div class='del'>-</div><div class='ctx'> 	struct dp_link *link;</div><div class='ctx'> 	struct dp_panel *panel;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='del'>-	struct device *dev;</div><div class='del'>-	struct drm_device *drm_dev;</div><div class='ctx'> </div><div class='ctx'> 	struct dp_debug dp_debug;</div><div class='ctx'> };</div><div class='hunk'>@@ -204,35 +200,33 @@ static const struct file_operations test_active_fops = {</div><div class='ctx'> 	.write = dp_test_active_write</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void dp_debug_init(struct dp_debug *dp_debug, struct drm_minor *minor)</div><div class='add'>+static void dp_debug_init(struct dp_debug *dp_debug, struct dentry *root, bool is_edp)</div><div class='ctx'> {</div><div class='del'>-	char path[64];</div><div class='ctx'> 	struct dp_debug_private *debug = container_of(dp_debug,</div><div class='ctx'> 			struct dp_debug_private, dp_debug);</div><div class='ctx'> </div><div class='del'>-	snprintf(path, sizeof(path), "msm_dp-%s", debug-&gt;connector-&gt;name);</div><div class='del'>-</div><div class='del'>-	debug-&gt;root = debugfs_create_dir(path, minor-&gt;debugfs_root);</div><div class='del'>-</div><div class='del'>-	debugfs_create_file("dp_debug", 0444, debug-&gt;root,</div><div class='add'>+	debugfs_create_file("dp_debug", 0444, root,</div><div class='ctx'> 			debug, &amp;dp_debug_fops);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file("msm_dp_test_active", 0444,</div><div class='del'>-			debug-&gt;root,</div><div class='del'>-			debug, &amp;test_active_fops);</div><div class='add'>+	if (!is_edp) {</div><div class='add'>+		debugfs_create_file("msm_dp_test_active", 0444,</div><div class='add'>+				    root,</div><div class='add'>+				    debug, &amp;test_active_fops);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file("msm_dp_test_data", 0444,</div><div class='del'>-			debug-&gt;root,</div><div class='del'>-			debug, &amp;dp_test_data_fops);</div><div class='add'>+		debugfs_create_file("msm_dp_test_data", 0444,</div><div class='add'>+				    root,</div><div class='add'>+				    debug, &amp;dp_test_data_fops);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file("msm_dp_test_type", 0444,</div><div class='del'>-			debug-&gt;root,</div><div class='del'>-			debug, &amp;dp_test_type_fops);</div><div class='add'>+		debugfs_create_file("msm_dp_test_type", 0444,</div><div class='add'>+				    root,</div><div class='add'>+				    debug, &amp;dp_test_type_fops);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,</div><div class='ctx'> 		struct dp_link *link,</div><div class='del'>-		struct drm_connector *connector, struct drm_minor *minor)</div><div class='add'>+		struct drm_connector *connector,</div><div class='add'>+		struct dentry *root, bool is_edp)</div><div class='ctx'> {</div><div class='ctx'> 	struct dp_debug_private *debug;</div><div class='ctx'> 	struct dp_debug *dp_debug;</div><div class='hunk'>@@ -253,46 +247,15 @@ struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,</div><div class='ctx'> 	debug-&gt;dp_debug.debug_en = false;</div><div class='ctx'> 	debug-&gt;link = link;</div><div class='ctx'> 	debug-&gt;panel = panel;</div><div class='del'>-	debug-&gt;dev = dev;</div><div class='del'>-	debug-&gt;drm_dev = minor-&gt;dev;</div><div class='del'>-	debug-&gt;connector = connector;</div><div class='ctx'> </div><div class='ctx'> 	dp_debug = &amp;debug-&gt;dp_debug;</div><div class='ctx'> 	dp_debug-&gt;vdisplay = 0;</div><div class='ctx'> 	dp_debug-&gt;hdisplay = 0;</div><div class='ctx'> 	dp_debug-&gt;vrefresh = 0;</div><div class='ctx'> </div><div class='del'>-	dp_debug_init(dp_debug, minor);</div><div class='add'>+	dp_debug_init(dp_debug, root, is_edp);</div><div class='ctx'> </div><div class='ctx'> 	return dp_debug;</div><div class='ctx'>  error:</div><div class='ctx'> 	return ERR_PTR(rc);</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-static int dp_debug_deinit(struct dp_debug *dp_debug)</div><div class='del'>-{</div><div class='del'>-	struct dp_debug_private *debug;</div><div class='del'>-</div><div class='del'>-	if (!dp_debug)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	debug = container_of(dp_debug, struct dp_debug_private, dp_debug);</div><div class='del'>-</div><div class='del'>-	debugfs_remove_recursive(debug-&gt;root);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dp_debug_put(struct dp_debug *dp_debug)</div><div class='del'>-{</div><div class='del'>-	struct dp_debug_private *debug;</div><div class='del'>-</div><div class='del'>-	if (!dp_debug)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	debug = container_of(dp_debug, struct dp_debug_private, dp_debug);</div><div class='del'>-</div><div class='del'>-	dp_debug_deinit(dp_debug);</div><div class='del'>-</div><div class='del'>-	devm_kfree(debug-&gt;dev, debug);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_debug.h b/drivers/gpu/drm/msm/dp/dp_debug.h<br/>index 124227873d58..9b3b2e702f65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_debug.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_debug.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_debug.h</a></div><div class='hunk'>@@ -34,7 +34,8 @@ struct dp_debug {</div><div class='ctx'>  * @panel: instance of panel module</div><div class='ctx'>  * @link: instance of link module</div><div class='ctx'>  * @connector: double pointer to display connector</div><div class='del'>- * @minor: pointer to drm minor number after device registration</div><div class='add'>+ * @root: connector's debugfs root</div><div class='add'>+ * @is_edp: set for eDP connectors / panels</div><div class='ctx'>  * return: pointer to allocated debug module data</div><div class='ctx'>  *</div><div class='ctx'>  * This function sets up the debug module and provides a way</div><div class='hunk'>@@ -43,31 +44,21 @@ struct dp_debug {</div><div class='ctx'> struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,</div><div class='ctx'> 		struct dp_link *link,</div><div class='ctx'> 		struct drm_connector *connector,</div><div class='del'>-		struct drm_minor *minor);</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * dp_debug_put()</div><div class='del'>- *</div><div class='del'>- * Cleans up dp_debug instance</div><div class='del'>- *</div><div class='del'>- * @dp_debug: instance of dp_debug</div><div class='del'>- */</div><div class='del'>-void dp_debug_put(struct dp_debug *dp_debug);</div><div class='add'>+		struct dentry *root,</div><div class='add'>+		bool is_edp);</div><div class='ctx'> </div><div class='ctx'> #else</div><div class='ctx'> </div><div class='ctx'> static inline</div><div class='ctx'> struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,</div><div class='ctx'> 		struct dp_link *link,</div><div class='del'>-		struct drm_connector *connector, struct drm_minor *minor)</div><div class='add'>+		struct drm_connector *connector,</div><div class='add'>+		struct dentry *root,</div><div class='add'>+		bool is_edp)</div><div class='ctx'> {</div><div class='ctx'> 	return ERR_PTR(-EINVAL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void dp_debug_put(struct dp_debug *dp_debug)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #endif /* defined(CONFIG_DEBUG_FS) */</div><div class='ctx'> </div><div class='ctx'> #endif /* _DP_DEBUG_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c<br/>index 766c8d01e6b3..c8e1bbebdffe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_display.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_display.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_display.c</a></div><div class='hunk'>@@ -50,13 +50,11 @@ enum {</div><div class='ctx'> 	ST_CONNECTED,</div><div class='ctx'> 	ST_DISCONNECT_PENDING,</div><div class='ctx'> 	ST_DISPLAY_OFF,</div><div class='del'>-	ST_SUSPENDED,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum {</div><div class='ctx'> 	EV_NO_EVENT,</div><div class='ctx'> 	/* hpd events */</div><div class='del'>-	EV_HPD_INIT_SETUP,</div><div class='ctx'> 	EV_HPD_PLUG_INT,</div><div class='ctx'> 	EV_IRQ_HPD_INT,</div><div class='ctx'> 	EV_HPD_UNPLUG_INT,</div><div class='hunk'>@@ -171,6 +169,11 @@ static const struct msm_dp_desc sm8350_dp_descs[] = {</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct msm_dp_desc sm8650_dp_descs[] = {</div><div class='add'>+	{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id dp_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-dp", .data = &amp;sc7180_dp_descs },</div><div class='ctx'> 	{ .compatible = "qcom,sc7280-dp", .data = &amp;sc7280_dp_descs },</div><div class='hunk'>@@ -181,6 +184,7 @@ static const struct of_device_id dp_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sc8280xp-edp", .data = &amp;sc8280xp_edp_descs },</div><div class='ctx'> 	{ .compatible = "qcom,sdm845-dp", .data = &amp;sc7180_dp_descs },</div><div class='ctx'> 	{ .compatible = "qcom,sm8350-dp", .data = &amp;sm8350_dp_descs },</div><div class='add'>+	{ .compatible = "qcom,sm8650-dp", .data = &amp;sm8650_dp_descs },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -276,11 +280,6 @@ static int dp_display_bind(struct device *dev, struct device *master,</div><div class='ctx'> 	dp-&gt;dp_display.drm_dev = drm;</div><div class='ctx'> 	priv-&gt;dp[dp-&gt;id] = &amp;dp-&gt;dp_display;</div><div class='ctx'> </div><div class='del'>-	rc = dp-&gt;parser-&gt;parse(dp-&gt;parser);</div><div class='del'>-	if (rc) {</div><div class='del'>-		DRM_ERROR("device tree parsing failed\n");</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	dp-&gt;drm_dev = drm;</div><div class='hunk'>@@ -291,11 +290,6 @@ static int dp_display_bind(struct device *dev, struct device *master,</div><div class='ctx'> 		goto end;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = dp_power_client_init(dp-&gt;power);</div><div class='del'>-	if (rc) {</div><div class='del'>-		DRM_ERROR("Power client create failed\n");</div><div class='del'>-		goto end;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	rc = dp_register_audio_driver(dev, dp-&gt;audio);</div><div class='ctx'> 	if (rc) {</div><div class='hunk'>@@ -320,15 +314,10 @@ static void dp_display_unbind(struct device *dev, struct device *master,</div><div class='ctx'> 	struct dp_display_private *dp = dev_get_dp_display_private(dev);</div><div class='ctx'> 	struct msm_drm_private *priv = dev_get_drvdata(master);</div><div class='ctx'> </div><div class='del'>-	/* disable all HPD interrupts */</div><div class='del'>-	if (dp-&gt;core_initialized)</div><div class='del'>-		dp_catalog_hpd_config_intr(dp-&gt;catalog, DP_DP_HPD_INT_MASK, false);</div><div class='del'>-</div><div class='ctx'> 	kthread_stop(dp-&gt;ev_tsk);</div><div class='ctx'> </div><div class='ctx'> 	of_dp_aux_depopulate_bus(dp-&gt;aux);</div><div class='ctx'> </div><div class='del'>-	dp_power_client_deinit(dp-&gt;power);</div><div class='ctx'> 	dp_unregister_audio_driver(dev, dp-&gt;audio);</div><div class='ctx'> 	dp_aux_unregister(dp-&gt;aux);</div><div class='ctx'> 	dp-&gt;drm_dev = NULL;</div><div class='hunk'>@@ -341,27 +330,10 @@ static const struct component_ops dp_display_comp_ops = {</div><div class='ctx'> 	.unbind = dp_display_unbind,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void dp_display_send_hpd_event(struct msm_dp *dp_display)</div><div class='del'>-{</div><div class='del'>-	struct dp_display_private *dp;</div><div class='del'>-	struct drm_connector *connector;</div><div class='del'>-</div><div class='del'>-	dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='del'>-</div><div class='del'>-	connector = dp-&gt;dp_display.connector;</div><div class='del'>-	drm_helper_hpd_irq_event(connector-&gt;dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> static int dp_display_send_hpd_notification(struct dp_display_private *dp,</div><div class='ctx'> 					    bool hpd)</div><div class='ctx'> {</div><div class='del'>-	if ((hpd &amp;&amp; dp-&gt;dp_display.is_connected) ||</div><div class='del'>-			(!hpd &amp;&amp; !dp-&gt;dp_display.is_connected)) {</div><div class='del'>-		drm_dbg_dp(dp-&gt;drm_dev, "HPD already %s\n",</div><div class='del'>-				(hpd ? "on" : "off"));</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='add'>+	struct drm_bridge *bridge = dp-&gt;dp_display.bridge;</div><div class='ctx'> </div><div class='ctx'> 	/* reset video pattern flag on disconnect */</div><div class='ctx'> 	if (!hpd) {</div><div class='hunk'>@@ -373,11 +345,11 @@ static int dp_display_send_hpd_notification(struct dp_display_private *dp,</div><div class='ctx'> 							 dp-&gt;panel-&gt;downstream_ports);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dp-&gt;dp_display.is_connected = hpd;</div><div class='add'>+	dp-&gt;dp_display.link_ready = hpd;</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg_dp(dp-&gt;drm_dev, "type=%d hpd=%d\n",</div><div class='ctx'> 			dp-&gt;dp_display.connector_type, hpd);</div><div class='del'>-	dp_display_send_hpd_event(&amp;dp-&gt;dp_display);</div><div class='add'>+	drm_bridge_hpd_notify(bridge, dp-&gt;dp_display.link_ready);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -576,6 +548,7 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> {</div><div class='ctx'> 	u32 state;</div><div class='ctx'> 	int ret;</div><div class='add'>+	struct platform_device *pdev = dp-&gt;dp_display.pdev;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -583,7 +556,7 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> 	drm_dbg_dp(dp-&gt;drm_dev, "Before, type=%d hpd_state=%d\n",</div><div class='ctx'> 			dp-&gt;dp_display.connector_type, state);</div><div class='ctx'> </div><div class='del'>-	if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) {</div><div class='add'>+	if (state == ST_DISPLAY_OFF) {</div><div class='ctx'> 		mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -600,7 +573,14 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = dp_display_usbpd_configure_cb(&amp;dp-&gt;dp_display.pdev-&gt;dev);</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		DRM_ERROR("failed to pm_runtime_resume\n");</div><div class='add'>+		mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = dp_display_usbpd_configure_cb(&amp;pdev-&gt;dev);</div><div class='ctx'> 	if (ret) {	/* link train failed */</div><div class='ctx'> 		dp-&gt;hpd_state = ST_DISCONNECTED;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -632,6 +612,7 @@ static void dp_display_handle_plugged_change(struct msm_dp *dp_display,</div><div class='ctx'> static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> {</div><div class='ctx'> 	u32 state;</div><div class='add'>+	struct platform_device *pdev = dp-&gt;dp_display.pdev;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -682,6 +663,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> 			dp-&gt;dp_display.connector_type, state);</div><div class='ctx'> </div><div class='ctx'> 	/* uevent will complete disconnection part */</div><div class='add'>+	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -697,7 +679,7 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> 	drm_dbg_dp(dp-&gt;drm_dev, "Before, type=%d hpd_state=%d\n",</div><div class='ctx'> 			dp-&gt;dp_display.connector_type, state);</div><div class='ctx'> </div><div class='del'>-	if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) {</div><div class='add'>+	if (state == ST_DISPLAY_OFF) {</div><div class='ctx'> 		mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -721,7 +703,6 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data)</div><div class='ctx'> </div><div class='ctx'> static void dp_display_deinit_sub_modules(struct dp_display_private *dp)</div><div class='ctx'> {</div><div class='del'>-	dp_debug_put(dp-&gt;debug);</div><div class='ctx'> 	dp_audio_put(dp-&gt;audio);</div><div class='ctx'> 	dp_panel_put(dp-&gt;panel);</div><div class='ctx'> 	dp_aux_put(dp-&gt;aux);</div><div class='hunk'>@@ -919,7 +900,7 @@ int dp_display_set_plugged_cb(struct msm_dp *dp_display,</div><div class='ctx'> </div><div class='ctx'> 	dp_display-&gt;plugged_cb = fn;</div><div class='ctx'> 	dp_display-&gt;codec_dev = codec_dev;</div><div class='del'>-	plugged = dp_display-&gt;is_connected;</div><div class='add'>+	plugged = dp_display-&gt;link_ready;</div><div class='ctx'> 	dp_display_handle_plugged_change(dp_display, plugged);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1109,9 +1090,6 @@ static int hpd_event_thread(void *data)</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;dp_priv-&gt;event_lock, flag);</div><div class='ctx'> </div><div class='ctx'> 		switch (todo-&gt;event_id) {</div><div class='del'>-		case EV_HPD_INIT_SETUP:</div><div class='del'>-			dp_display_host_init(dp_priv);</div><div class='del'>-			break;</div><div class='ctx'> 		case EV_HPD_PLUG_INT:</div><div class='ctx'> 			dp_hpd_plug_handle(dp_priv, todo-&gt;data);</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1190,27 +1168,21 @@ static irqreturn_t dp_display_irq_handler(int irq, void *dev_id)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int dp_display_request_irq(struct msm_dp *dp_display)</div><div class='add'>+static int dp_display_request_irq(struct dp_display_private *dp)</div><div class='ctx'> {</div><div class='ctx'> 	int rc = 0;</div><div class='del'>-	struct dp_display_private *dp;</div><div class='del'>-</div><div class='del'>-	if (!dp_display) {</div><div class='del'>-		DRM_ERROR("invalid input\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='add'>+	struct platform_device *pdev = dp-&gt;dp_display.pdev;</div><div class='ctx'> </div><div class='del'>-	dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='del'>-</div><div class='del'>-	dp-&gt;irq = irq_of_parse_and_map(dp-&gt;dp_display.pdev-&gt;dev.of_node, 0);</div><div class='del'>-	if (!dp-&gt;irq) {</div><div class='add'>+	dp-&gt;irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (dp-&gt;irq &lt; 0) {</div><div class='ctx'> 		DRM_ERROR("failed to get irq\n");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return dp-&gt;irq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = devm_request_irq(dp_display-&gt;drm_dev-&gt;dev, dp-&gt;irq,</div><div class='del'>-			dp_display_irq_handler,</div><div class='del'>-			IRQF_TRIGGER_HIGH, "dp_display_isr", dp);</div><div class='add'>+	rc = devm_request_irq(&amp;pdev-&gt;dev, dp-&gt;irq, dp_display_irq_handler,</div><div class='add'>+			      IRQF_TRIGGER_HIGH|IRQF_NO_AUTOEN,</div><div class='add'>+			      "dp_display_isr", dp);</div><div class='add'>+</div><div class='ctx'> 	if (rc &lt; 0) {</div><div class='ctx'> 		DRM_ERROR("failed to request IRQ%u: %d\n",</div><div class='ctx'> 				dp-&gt;irq, rc);</div><div class='hunk'>@@ -1239,6 +1211,29 @@ static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pde</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int dp_display_get_next_bridge(struct msm_dp *dp);</div><div class='add'>+</div><div class='add'>+static int dp_display_probe_tail(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct msm_dp *dp = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = dp_display_get_next_bridge(dp);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = component_add(dev, &amp;dp_display_comp_ops);</div><div class='add'>+	if (ret)</div><div class='add'>+		DRM_ERROR("component add failed, rc=%d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp_auxbus_done_probe(struct drm_dp_aux *aux)</div><div class='add'>+{</div><div class='add'>+	return dp_display_probe_tail(aux-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int dp_display_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int rc = 0;</div><div class='hunk'>@@ -1272,6 +1267,18 @@ static int dp_display_probe(struct platform_device *pdev)</div><div class='ctx'> 		return -EPROBE_DEFER;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	rc = dp-&gt;parser-&gt;parse(dp-&gt;parser);</div><div class='add'>+	if (rc) {</div><div class='add'>+		DRM_ERROR("device tree parsing failed\n");</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = dp_power_client_init(dp-&gt;power);</div><div class='add'>+	if (rc) {</div><div class='add'>+		DRM_ERROR("Power client create failed\n");</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* setup event q */</div><div class='ctx'> 	mutex_init(&amp;dp-&gt;event_mutex);</div><div class='ctx'> 	init_waitqueue_head(&amp;dp-&gt;event_q);</div><div class='hunk'>@@ -1284,13 +1291,31 @@ static int dp_display_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	platform_set_drvdata(pdev, &amp;dp-&gt;dp_display);</div><div class='ctx'> </div><div class='del'>-	rc = component_add(&amp;pdev-&gt;dev, &amp;dp_display_comp_ops);</div><div class='del'>-	if (rc) {</div><div class='del'>-		DRM_ERROR("component add failed, rc=%d\n", rc);</div><div class='del'>-		dp_display_deinit_sub_modules(dp);</div><div class='add'>+	rc = devm_pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	rc = dp_display_request_irq(dp);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	if (dp-&gt;dp_display.is_edp) {</div><div class='add'>+		rc = devm_of_dp_aux_populate_bus(dp-&gt;aux, dp_auxbus_done_probe);</div><div class='add'>+		if (rc) {</div><div class='add'>+			DRM_ERROR("eDP auxbus population failed, rc=%d\n", rc);</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		rc = dp_display_probe_tail(&amp;pdev-&gt;dev);</div><div class='add'>+		if (rc)</div><div class='add'>+			goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	dp_display_deinit_sub_modules(dp);</div><div class='add'>+	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void dp_display_remove(struct platform_device *pdev)</div><div class='hunk'>@@ -1299,113 +1324,50 @@ static void dp_display_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;dp_display_comp_ops);</div><div class='ctx'> 	dp_display_deinit_sub_modules(dp);</div><div class='del'>-</div><div class='ctx'> 	platform_set_drvdata(pdev, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dp_pm_resume(struct device *dev)</div><div class='add'>+static int dp_pm_runtime_suspend(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct platform_device *pdev = to_platform_device(dev);</div><div class='del'>-	struct msm_dp *dp_display = platform_get_drvdata(pdev);</div><div class='del'>-	struct dp_display_private *dp;</div><div class='del'>-	int sink_count = 0;</div><div class='del'>-</div><div class='del'>-	dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;dp-&gt;event_mutex);</div><div class='del'>-</div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev,</div><div class='del'>-		"Before, type=%d core_inited=%d phy_inited=%d power_on=%d\n",</div><div class='del'>-		dp-&gt;dp_display.connector_type, dp-&gt;core_initialized,</div><div class='del'>-		dp-&gt;phy_initialized, dp_display-&gt;power_on);</div><div class='del'>-</div><div class='del'>-	/* start from disconnected state */</div><div class='del'>-	dp-&gt;hpd_state = ST_DISCONNECTED;</div><div class='del'>-</div><div class='del'>-	/* turn on dp ctrl/phy */</div><div class='del'>-	dp_display_host_init(dp);</div><div class='del'>-</div><div class='del'>-	if (dp_display-&gt;is_edp)</div><div class='del'>-		dp_catalog_ctrl_hpd_enable(dp-&gt;catalog);</div><div class='add'>+	struct dp_display_private *dp = dev_get_dp_display_private(dev);</div><div class='ctx'> </div><div class='del'>-	if (dp_catalog_link_is_connected(dp-&gt;catalog)) {</div><div class='del'>-		/*</div><div class='del'>-		 * set sink to normal operation mode -- D0</div><div class='del'>-		 * before dpcd read</div><div class='del'>-		 */</div><div class='del'>-		dp_display_host_phy_init(dp);</div><div class='del'>-		dp_link_psm_config(dp-&gt;link, &amp;dp-&gt;panel-&gt;link_info, false);</div><div class='del'>-		sink_count = drm_dp_read_sink_count(dp-&gt;aux);</div><div class='del'>-		if (sink_count &lt; 0)</div><div class='del'>-			sink_count = 0;</div><div class='add'>+	disable_irq(dp-&gt;irq);</div><div class='ctx'> </div><div class='add'>+	if (dp-&gt;dp_display.is_edp) {</div><div class='ctx'> 		dp_display_host_phy_exit(dp);</div><div class='add'>+		dp_catalog_ctrl_hpd_disable(dp-&gt;catalog);</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	dp-&gt;link-&gt;sink_count = sink_count;</div><div class='del'>-	/*</div><div class='del'>-	 * can not declared display is connected unless</div><div class='del'>-	 * HDMI cable is plugged in and sink_count of</div><div class='del'>-	 * dongle become 1</div><div class='del'>-	 * also only signal audio when disconnected</div><div class='del'>-	 */</div><div class='del'>-	if (dp-&gt;link-&gt;sink_count) {</div><div class='del'>-		dp-&gt;dp_display.is_connected = true;</div><div class='del'>-	} else {</div><div class='del'>-		dp-&gt;dp_display.is_connected = false;</div><div class='del'>-		dp_display_handle_plugged_change(dp_display, false);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev,</div><div class='del'>-		"After, type=%d sink=%d conn=%d core_init=%d phy_init=%d power=%d\n",</div><div class='del'>-		dp-&gt;dp_display.connector_type, dp-&gt;link-&gt;sink_count,</div><div class='del'>-		dp-&gt;dp_display.is_connected, dp-&gt;core_initialized,</div><div class='del'>-		dp-&gt;phy_initialized, dp_display-&gt;power_on);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='add'>+	dp_display_host_deinit(dp);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dp_pm_suspend(struct device *dev)</div><div class='add'>+static int dp_pm_runtime_resume(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct platform_device *pdev = to_platform_device(dev);</div><div class='del'>-	struct msm_dp *dp_display = platform_get_drvdata(pdev);</div><div class='del'>-	struct dp_display_private *dp;</div><div class='del'>-</div><div class='del'>-	dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;dp-&gt;event_mutex);</div><div class='del'>-</div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev,</div><div class='del'>-		"Before, type=%d core_inited=%d  phy_inited=%d power_on=%d\n",</div><div class='del'>-		dp-&gt;dp_display.connector_type, dp-&gt;core_initialized,</div><div class='del'>-		dp-&gt;phy_initialized, dp_display-&gt;power_on);</div><div class='del'>-</div><div class='del'>-	/* mainlink enabled */</div><div class='del'>-	if (dp_power_clk_status(dp-&gt;power, DP_CTRL_PM))</div><div class='del'>-		dp_ctrl_off_link_stream(dp-&gt;ctrl);</div><div class='del'>-</div><div class='del'>-	dp_display_host_phy_exit(dp);</div><div class='del'>-</div><div class='del'>-	/* host_init will be called at pm_resume */</div><div class='del'>-	dp_display_host_deinit(dp);</div><div class='del'>-</div><div class='del'>-	dp-&gt;hpd_state = ST_SUSPENDED;</div><div class='del'>-</div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev,</div><div class='del'>-		"After, type=%d core_inited=%d phy_inited=%d power_on=%d\n",</div><div class='del'>-		dp-&gt;dp_display.connector_type, dp-&gt;core_initialized,</div><div class='del'>-		dp-&gt;phy_initialized, dp_display-&gt;power_on);</div><div class='add'>+	struct dp_display_private *dp = dev_get_dp_display_private(dev);</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='add'>+	/*</div><div class='add'>+	 * for eDP, host cotroller, HPD block and PHY are enabled here</div><div class='add'>+	 * but with HPD irq disabled</div><div class='add'>+	 *</div><div class='add'>+	 * for DP, only host controller is enabled here.</div><div class='add'>+	 * HPD block is enabled at dp_bridge_hpd_enable()</div><div class='add'>+	 * PHY will be enabled at plugin handler later</div><div class='add'>+	 */</div><div class='add'>+	dp_display_host_init(dp);</div><div class='add'>+	if (dp-&gt;dp_display.is_edp) {</div><div class='add'>+		dp_catalog_ctrl_hpd_enable(dp-&gt;catalog);</div><div class='add'>+		dp_display_host_phy_init(dp);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	enable_irq(dp-&gt;irq);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pm_ops dp_pm_ops = {</div><div class='del'>-	.suspend = dp_pm_suspend,</div><div class='del'>-	.resume =  dp_pm_resume,</div><div class='add'>+	SET_RUNTIME_PM_OPS(dp_pm_runtime_suspend, dp_pm_runtime_resume, NULL)</div><div class='add'>+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,</div><div class='add'>+				pm_runtime_force_resume)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver dp_display_driver = {</div><div class='hunk'>@@ -1435,19 +1397,6 @@ void __exit msm_dp_unregister(void)</div><div class='ctx'> 	platform_driver_unregister(&amp;dp_display_driver);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void msm_dp_irq_postinstall(struct msm_dp *dp_display)</div><div class='del'>-{</div><div class='del'>-	struct dp_display_private *dp;</div><div class='del'>-</div><div class='del'>-	if (!dp_display)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='del'>-</div><div class='del'>-	if (!dp_display-&gt;is_edp)</div><div class='del'>-		dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)</div><div class='ctx'> {</div><div class='ctx'> 	struct dp_display_private *dp;</div><div class='hunk'>@@ -1457,7 +1406,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)</div><div class='ctx'> 	return dp-&gt;wide_bus_en;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)</div><div class='add'>+void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, bool is_edp)</div><div class='ctx'> {</div><div class='ctx'> 	struct dp_display_private *dp;</div><div class='ctx'> 	struct device *dev;</div><div class='hunk'>@@ -1468,7 +1417,7 @@ void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)</div><div class='ctx'> </div><div class='ctx'> 	dp-&gt;debug = dp_debug_get(dev, dp-&gt;panel,</div><div class='ctx'> 					dp-&gt;link, dp-&gt;dp_display.connector,</div><div class='del'>-					minor);</div><div class='add'>+					root, is_edp);</div><div class='ctx'> 	if (IS_ERR(dp-&gt;debug)) {</div><div class='ctx'> 		rc = PTR_ERR(dp-&gt;debug);</div><div class='ctx'> 		DRM_ERROR("failed to initialize debug, rc = %d\n", rc);</div><div class='hunk'>@@ -1480,33 +1429,8 @@ static int dp_display_get_next_bridge(struct msm_dp *dp)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	struct dp_display_private *dp_priv;</div><div class='del'>-	struct device_node *aux_bus;</div><div class='del'>-	struct device *dev;</div><div class='ctx'> </div><div class='ctx'> 	dp_priv = container_of(dp, struct dp_display_private, dp_display);</div><div class='del'>-	dev = &amp;dp_priv-&gt;dp_display.pdev-&gt;dev;</div><div class='del'>-	aux_bus = of_get_child_by_name(dev-&gt;of_node, "aux-bus");</div><div class='del'>-</div><div class='del'>-	if (aux_bus &amp;&amp; dp-&gt;is_edp) {</div><div class='del'>-		dp_display_host_init(dp_priv);</div><div class='del'>-		dp_catalog_ctrl_hpd_enable(dp_priv-&gt;catalog);</div><div class='del'>-		dp_display_host_phy_init(dp_priv);</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * The code below assumes that the panel will finish probing</div><div class='del'>-		 * by the time devm_of_dp_aux_populate_ep_devices() returns.</div><div class='del'>-		 * This isn't a great assumption since it will fail if the</div><div class='del'>-		 * panel driver is probed asynchronously but is the best we</div><div class='del'>-		 * can do without a bigger driver reorganization.</div><div class='del'>-		 */</div><div class='del'>-		rc = of_dp_aux_populate_bus(dp_priv-&gt;aux, NULL);</div><div class='del'>-		of_node_put(aux_bus);</div><div class='del'>-		if (rc)</div><div class='del'>-			goto error;</div><div class='del'>-	} else if (dp-&gt;is_edp) {</div><div class='del'>-		DRM_ERROR("eDP aux_bus not found\n");</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * External bridges are mandatory for eDP interfaces: one has to</div><div class='hunk'>@@ -1515,21 +1439,13 @@ static int dp_display_get_next_bridge(struct msm_dp *dp)</div><div class='ctx'> 	 * For DisplayPort interfaces external bridges are optional, so</div><div class='ctx'> 	 * silently ignore an error if one is not present (-ENODEV).</div><div class='ctx'> 	 */</div><div class='del'>-	rc = devm_dp_parser_find_next_bridge(dp-&gt;drm_dev-&gt;dev, dp_priv-&gt;parser);</div><div class='add'>+	rc = devm_dp_parser_find_next_bridge(&amp;dp-&gt;pdev-&gt;dev, dp_priv-&gt;parser);</div><div class='ctx'> 	if (!dp-&gt;is_edp &amp;&amp; rc == -ENODEV)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (!rc) {</div><div class='add'>+	if (!rc)</div><div class='ctx'> 		dp-&gt;next_bridge = dp_priv-&gt;parser-&gt;next_bridge;</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-error:</div><div class='del'>-	if (dp-&gt;is_edp) {</div><div class='del'>-		of_dp_aux_depopulate_bus(dp_priv-&gt;aux);</div><div class='del'>-		dp_display_host_phy_exit(dp_priv);</div><div class='del'>-		dp_display_host_deinit(dp_priv);</div><div class='del'>-	}</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1543,16 +1459,6 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	dp_priv = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='ctx'> </div><div class='del'>-	ret = dp_display_request_irq(dp_display);</div><div class='del'>-	if (ret) {</div><div class='del'>-		DRM_ERROR("request_irq failed, ret=%d\n", ret);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = dp_display_get_next_bridge(dp_display);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='ctx'> 	ret = dp_bridge_init(dp_display, dev, encoder);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		DRM_DEV_ERROR(dev-&gt;dev,</div><div class='hunk'>@@ -1594,6 +1500,11 @@ void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,</div><div class='ctx'> 		dp_hpd_plug_handle(dp_display, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;dp_display-&gt;event_mutex);</div><div class='add'>+	if (pm_runtime_resume_and_get(&amp;dp-&gt;pdev-&gt;dev)) {</div><div class='add'>+		DRM_ERROR("failed to pm_runtime_resume\n");</div><div class='add'>+		mutex_unlock(&amp;dp_display-&gt;event_mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	state = dp_display-&gt;hpd_state;</div><div class='ctx'> 	if (state != ST_DISPLAY_OFF &amp;&amp; state != ST_MAINLINK_READY) {</div><div class='hunk'>@@ -1658,10 +1569,9 @@ void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,</div><div class='ctx'> 	mutex_lock(&amp;dp_display-&gt;event_mutex);</div><div class='ctx'> </div><div class='ctx'> 	state = dp_display-&gt;hpd_state;</div><div class='del'>-	if (state != ST_DISCONNECT_PENDING &amp;&amp; state != ST_CONNECTED) {</div><div class='del'>-		mutex_unlock(&amp;dp_display-&gt;event_mutex);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='add'>+	if (state != ST_DISCONNECT_PENDING &amp;&amp; state != ST_CONNECTED)</div><div class='add'>+		drm_dbg_dp(dp-&gt;drm_dev, "type=%d wrong hpd_state=%d\n",</div><div class='add'>+			   dp-&gt;connector_type, state);</div><div class='ctx'> </div><div class='ctx'> 	dp_display_disable(dp_display);</div><div class='ctx'> </div><div class='hunk'>@@ -1674,6 +1584,8 @@ void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	drm_dbg_dp(dp-&gt;drm_dev, "type=%d Done\n", dp-&gt;connector_type);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_sync(&amp;dp-&gt;pdev-&gt;dev);</div><div class='ctx'> 	mutex_unlock(&amp;dp_display-&gt;event_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1712,7 +1624,21 @@ void dp_bridge_hpd_enable(struct drm_bridge *bridge)</div><div class='ctx'> 	struct msm_dp *dp_display = dp_bridge-&gt;dp_display;</div><div class='ctx'> 	struct dp_display_private *dp = container_of(dp_display, struct dp_display_private, dp_display);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * this is for external DP with hpd irq enabled case,</div><div class='add'>+	 * step-1: dp_pm_runtime_resume() enable dp host only</div><div class='add'>+	 * step-2: enable hdp block and have hpd irq enabled here</div><div class='add'>+	 * step-3: waiting for plugin irq while phy is not initialized</div><div class='add'>+	 * step-4: DP PHY is initialized at plugin handler before link training</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='ctx'> 	mutex_lock(&amp;dp-&gt;event_mutex);</div><div class='add'>+	if (pm_runtime_resume_and_get(&amp;dp_display-&gt;pdev-&gt;dev)) {</div><div class='add'>+		DRM_ERROR("failed to resume power\n");</div><div class='add'>+		mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dp_catalog_ctrl_hpd_enable(dp-&gt;catalog);</div><div class='ctx'> </div><div class='ctx'> 	/* enable HDP interrupts */</div><div class='hunk'>@@ -1734,6 +1660,8 @@ void dp_bridge_hpd_disable(struct drm_bridge *bridge)</div><div class='ctx'> 	dp_catalog_ctrl_hpd_disable(dp-&gt;catalog);</div><div class='ctx'> </div><div class='ctx'> 	dp_display-&gt;internal_hpd = false;</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_sync(&amp;dp_display-&gt;pdev-&gt;dev);</div><div class='ctx'> 	mutex_unlock(&amp;dp-&gt;event_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1748,13 +1676,8 @@ void dp_bridge_hpd_notify(struct drm_bridge *bridge,</div><div class='ctx'> 	if (dp_display-&gt;internal_hpd)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!dp-&gt;core_initialized) {</div><div class='del'>-		drm_dbg_dp(dp-&gt;drm_dev, "not initialized\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!dp_display-&gt;is_connected &amp;&amp; status == connector_status_connected)</div><div class='add'>+	if (!dp_display-&gt;link_ready &amp;&amp; status == connector_status_connected)</div><div class='ctx'> 		dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0);</div><div class='del'>-	else if (dp_display-&gt;is_connected &amp;&amp; status == connector_status_disconnected)</div><div class='add'>+	else if (dp_display-&gt;link_ready &amp;&amp; status == connector_status_disconnected)</div><div class='ctx'> 		dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h<br/>index f66cdbc35785..102f3507d824 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_display.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_display.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_display.h</a></div><div class='hunk'>@@ -17,7 +17,7 @@ struct msm_dp {</div><div class='ctx'> 	struct drm_bridge *bridge;</div><div class='ctx'> 	struct drm_connector *connector;</div><div class='ctx'> 	struct drm_bridge *next_bridge;</div><div class='del'>-	bool is_connected;</div><div class='add'>+	bool link_ready;</div><div class='ctx'> 	bool audio_enabled;</div><div class='ctx'> 	bool power_on;</div><div class='ctx'> 	unsigned int connector_type;</div><div class='hunk'>@@ -36,11 +36,11 @@ struct msm_dp {</div><div class='ctx'> int dp_display_set_plugged_cb(struct msm_dp *dp_display,</div><div class='ctx'> 		hdmi_codec_plugged_cb fn, struct device *codec_dev);</div><div class='ctx'> int dp_display_get_modes(struct msm_dp *dp_display);</div><div class='del'>-int dp_display_request_irq(struct msm_dp *dp_display);</div><div class='ctx'> bool dp_display_check_video_test(struct msm_dp *dp_display);</div><div class='ctx'> int dp_display_get_test_bpp(struct msm_dp *dp_display);</div><div class='ctx'> void dp_display_signal_audio_start(struct msm_dp *dp_display);</div><div class='ctx'> void dp_display_signal_audio_complete(struct msm_dp *dp_display);</div><div class='ctx'> void dp_display_set_psr(struct msm_dp *dp, bool enter);</div><div class='add'>+void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *dentry, bool is_edp);</div><div class='ctx'> </div><div class='ctx'> #endif /* _DP_DISPLAY_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c<br/>index e3bdd7dd4cdc..46e6889037e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_drm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_drm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_drm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_drm.c</a></div><div class='hunk'>@@ -24,10 +24,10 @@ static enum drm_connector_status dp_bridge_detect(struct drm_bridge *bridge)</div><div class='ctx'> </div><div class='ctx'> 	dp = to_dp_bridge(bridge)-&gt;dp_display;</div><div class='ctx'> </div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev, "is_connected = %s\n",</div><div class='del'>-		(dp-&gt;is_connected) ? "true" : "false");</div><div class='add'>+	drm_dbg_dp(dp-&gt;drm_dev, "link_ready = %s\n",</div><div class='add'>+		(dp-&gt;link_ready) ? "true" : "false");</div><div class='ctx'> </div><div class='del'>-	return (dp-&gt;is_connected) ? connector_status_connected :</div><div class='add'>+	return (dp-&gt;link_ready) ? connector_status_connected :</div><div class='ctx'> 					connector_status_disconnected;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -40,8 +40,8 @@ static int dp_bridge_atomic_check(struct drm_bridge *bridge,</div><div class='ctx'> </div><div class='ctx'> 	dp = to_dp_bridge(bridge)-&gt;dp_display;</div><div class='ctx'> </div><div class='del'>-	drm_dbg_dp(dp-&gt;drm_dev, "is_connected = %s\n",</div><div class='del'>-		(dp-&gt;is_connected) ? "true" : "false");</div><div class='add'>+	drm_dbg_dp(dp-&gt;drm_dev, "link_ready = %s\n",</div><div class='add'>+		(dp-&gt;link_ready) ? "true" : "false");</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * There is no protection in the DRM framework to check if the display</div><div class='hunk'>@@ -55,7 +55,7 @@ static int dp_bridge_atomic_check(struct drm_bridge *bridge,</div><div class='ctx'> 	 * After that this piece of code can be removed.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (bridge-&gt;ops &amp; DRM_BRIDGE_OP_HPD)</div><div class='del'>-		return (dp-&gt;is_connected) ? 0 : -ENOTCONN;</div><div class='add'>+		return (dp-&gt;link_ready) ? 0 : -ENOTCONN;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -78,7 +78,7 @@ static int dp_bridge_get_modes(struct drm_bridge *bridge, struct drm_connector *</div><div class='ctx'> 	dp = to_dp_bridge(bridge)-&gt;dp_display;</div><div class='ctx'> </div><div class='ctx'> 	/* pluggable case assumes EDID is read when HPD */</div><div class='del'>-	if (dp-&gt;is_connected) {</div><div class='add'>+	if (dp-&gt;link_ready) {</div><div class='ctx'> 		rc = dp_display_get_modes(dp);</div><div class='ctx'> 		if (rc &lt;= 0) {</div><div class='ctx'> 			DRM_ERROR("failed to get DP sink modes, rc=%d\n", rc);</div><div class='hunk'>@@ -90,6 +90,13 @@ static int dp_bridge_get_modes(struct drm_bridge *bridge, struct drm_connector *</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root)</div><div class='add'>+{</div><div class='add'>+	struct msm_dp *dp = to_dp_bridge(bridge)-&gt;dp_display;</div><div class='add'>+</div><div class='add'>+	dp_display_debugfs_init(dp, root, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct drm_bridge_funcs dp_bridge_ops = {</div><div class='ctx'> 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,</div><div class='ctx'> 	.atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,</div><div class='hunk'>@@ -105,6 +112,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = {</div><div class='ctx'> 	.hpd_enable   = dp_bridge_hpd_enable,</div><div class='ctx'> 	.hpd_disable  = dp_bridge_hpd_disable,</div><div class='ctx'> 	.hpd_notify   = dp_bridge_hpd_notify,</div><div class='add'>+	.debugfs_init = dp_bridge_debugfs_init,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int edp_bridge_atomic_check(struct drm_bridge *drm_bridge,</div><div class='hunk'>@@ -260,6 +268,13 @@ static enum drm_mode_status edp_bridge_mode_valid(struct drm_bridge *bridge,</div><div class='ctx'> 	return MODE_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void edp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root)</div><div class='add'>+{</div><div class='add'>+	struct msm_dp *dp = to_dp_bridge(bridge)-&gt;dp_display;</div><div class='add'>+</div><div class='add'>+	dp_display_debugfs_init(dp, root, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct drm_bridge_funcs edp_bridge_ops = {</div><div class='ctx'> 	.atomic_enable = edp_bridge_atomic_enable,</div><div class='ctx'> 	.atomic_disable = edp_bridge_atomic_disable,</div><div class='hunk'>@@ -270,6 +285,7 @@ static const struct drm_bridge_funcs edp_bridge_ops = {</div><div class='ctx'> 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,</div><div class='ctx'> 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,</div><div class='ctx'> 	.atomic_check = edp_bridge_atomic_check,</div><div class='add'>+	.debugfs_init = edp_bridge_debugfs_init,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c<br/>index 5cb84ca40e9e..c4843dd69f47 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_power.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_power.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_power.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_power.c</a></div><div class='hunk'>@@ -152,45 +152,17 @@ int dp_power_client_init(struct dp_power *dp_power)</div><div class='ctx'> </div><div class='ctx'> 	power = container_of(dp_power, struct dp_power_private, dp_power);</div><div class='ctx'> </div><div class='del'>-	pm_runtime_enable(power-&gt;dev);</div><div class='del'>-</div><div class='ctx'> 	return dp_power_clk_init(power);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dp_power_client_deinit(struct dp_power *dp_power)</div><div class='del'>-{</div><div class='del'>-	struct dp_power_private *power;</div><div class='del'>-</div><div class='del'>-	power = container_of(dp_power, struct dp_power_private, dp_power);</div><div class='del'>-</div><div class='del'>-	pm_runtime_disable(power-&gt;dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int dp_power_init(struct dp_power *dp_power)</div><div class='ctx'> {</div><div class='del'>-	int rc = 0;</div><div class='del'>-	struct dp_power_private *power = NULL;</div><div class='del'>-</div><div class='del'>-	power = container_of(dp_power, struct dp_power_private, dp_power);</div><div class='del'>-</div><div class='del'>-	pm_runtime_get_sync(power-&gt;dev);</div><div class='del'>-</div><div class='del'>-	rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);</div><div class='del'>-	if (rc)</div><div class='del'>-		pm_runtime_put_sync(power-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='add'>+	return dp_power_clk_enable(dp_power, DP_CORE_PM, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dp_power_deinit(struct dp_power *dp_power)</div><div class='ctx'> {</div><div class='del'>-	struct dp_power_private *power;</div><div class='del'>-</div><div class='del'>-	power = container_of(dp_power, struct dp_power_private, dp_power);</div><div class='del'>-</div><div class='del'>-	dp_power_clk_enable(dp_power, DP_CORE_PM, false);</div><div class='del'>-	pm_runtime_put_sync(power-&gt;dev);</div><div class='del'>-	return 0;</div><div class='add'>+	return dp_power_clk_enable(dp_power, DP_CORE_PM, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser)</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h<br/>index a3dec200785e..55ada51edb57 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_power.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dp/dp_power.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dp/dp_power.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dp/dp_power.h</a></div><div class='hunk'>@@ -81,17 +81,6 @@ int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type,</div><div class='ctx'> int dp_power_client_init(struct dp_power *power);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * dp_power_clinet_deinit() - de-initialize clock and regulator modules</div><div class='del'>- *</div><div class='del'>- * @power: instance of power module</div><div class='del'>- * return: 0 for success, error for failure.</div><div class='del'>- *</div><div class='del'>- * This API will de-initialize the DisplayPort's clocks and regulator</div><div class='del'>- * modules.</div><div class='del'>- */</div><div class='del'>-void dp_power_client_deinit(struct dp_power *power);</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * dp_power_get() - configure and get the DisplayPort power module data</div><div class='ctx'>  *</div><div class='ctx'>  * @parser: instance of parser module</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c<br/>index 1f98ff74ceb0..10ba7d153d1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/dsi_cfg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dsi/dsi_cfg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/dsi_cfg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/dsi_cfg.c</a></div><div class='hunk'>@@ -190,6 +190,21 @@ static const struct msm_dsi_config sm8550_dsi_cfg = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct regulator_bulk_data sm8650_dsi_regulators[] = {</div><div class='add'>+	{ .supply = "vdda", .init_load_uA = 16600 },	/* 1.2 V */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct msm_dsi_config sm8650_dsi_cfg = {</div><div class='add'>+	.io_offset = DSI_6G_REG_SHIFT,</div><div class='add'>+	.regulator_data = sm8650_dsi_regulators,</div><div class='add'>+	.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),</div><div class='add'>+	.bus_clk_names = dsi_v2_4_clk_names,</div><div class='add'>+	.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),</div><div class='add'>+	.io_start = {</div><div class='add'>+		{ 0xae94000, 0xae96000 },</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct regulator_bulk_data sc7280_dsi_regulators[] = {</div><div class='ctx'> 	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */</div><div class='ctx'> 	{ .supply = "refgen" },</div><div class='hunk'>@@ -281,6 +296,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {</div><div class='ctx'> 		&amp;sdm845_dsi_cfg, &amp;msm_dsi_6g_v2_host_ops},</div><div class='ctx'> 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,</div><div class='ctx'> 		&amp;sm8550_dsi_cfg, &amp;msm_dsi_6g_v2_host_ops},</div><div class='add'>+	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,</div><div class='add'>+		&amp;sm8650_dsi_cfg, &amp;msm_dsi_6g_v2_host_ops},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h<br/>index 43f0dd74edb6..4c9b4b37681b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/dsi_cfg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dsi/dsi_cfg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/dsi_cfg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/dsi_cfg.h</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #define MSM_DSI_6G_VER_MINOR_V2_5_0	0x20050000</div><div class='ctx'> #define MSM_DSI_6G_VER_MINOR_V2_6_0	0x20060000</div><div class='ctx'> #define MSM_DSI_6G_VER_MINOR_V2_7_0	0x20070000</div><div class='add'>+#define MSM_DSI_6G_VER_MINOR_V2_8_0	0x20080000</div><div class='ctx'> </div><div class='ctx'> #define MSM_DSI_V2_VER_MINOR_8064	0x0</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c<br/>index 05621e5e7d63..24a347fe2998 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.c</a></div><div class='hunk'>@@ -516,7 +516,9 @@ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)</div><div class='ctx'> 	struct device *dev = &amp;phy-&gt;pdev-&gt;dev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	pm_runtime_get_sync(dev);</div><div class='add'>+	ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = clk_prepare_enable(phy-&gt;ahb_clk);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -585,6 +587,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {</div><div class='ctx'> 	  .data = &amp;dsi_phy_5nm_8450_cfgs },</div><div class='ctx'> 	{ .compatible = "qcom,sm8550-dsi-phy-4nm",</div><div class='ctx'> 	  .data = &amp;dsi_phy_4nm_8550_cfgs },</div><div class='add'>+	{ .compatible = "qcom,sm8650-dsi-phy-4nm",</div><div class='add'>+	  .data = &amp;dsi_phy_4nm_8650_cfgs },</div><div class='ctx'> #endif</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='hunk'>@@ -689,6 +693,10 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)</div><div class='ctx'> 		return dev_err_probe(dev, PTR_ERR(phy-&gt;ahb_clk),</div><div class='ctx'> 				     "Unable to get ahb clk\n");</div><div class='ctx'> </div><div class='add'>+	ret = devm_pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	/* PLL init will call into clk_register which requires</div><div class='ctx'> 	 * register access, so we need to enable power and ahb clock.</div><div class='ctx'> 	 */</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h<br/>index 8b640d174785..e4275d3ad581 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy.h</a></div><div class='hunk'>@@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;</div><div class='ctx'> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;</div><div class='ctx'> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;</div><div class='ctx'> extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;</div><div class='add'>+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;</div><div class='ctx'> </div><div class='ctx'> struct msm_dsi_dphy_timing {</div><div class='ctx'> 	u32 clk_zero;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c<br/>index 89a6344bc865..82d015aa2d63 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c</a></div><div class='hunk'>@@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {</div><div class='ctx'> 	{ .supply = "vdds", .init_load_uA = 37550 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {</div><div class='add'>+	{ .supply = "vdds", .init_load_uA = 98000 },</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {</div><div class='ctx'> 	{ .supply = "vdds", .init_load_uA = 97800 },</div><div class='ctx'> };</div><div class='hunk'>@@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {</div><div class='ctx'> 	.num_dsi_phy = 2,</div><div class='ctx'> 	.quirks = DSI_PHY_7NM_QUIRK_V5_2,</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {</div><div class='add'>+	.has_phy_lane = true,</div><div class='add'>+	.regulator_data = dsi_phy_7nm_98000uA_regulators,</div><div class='add'>+	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),</div><div class='add'>+	.ops = {</div><div class='add'>+		.enable = dsi_7nm_phy_enable,</div><div class='add'>+		.disable = dsi_7nm_phy_disable,</div><div class='add'>+		.pll_init = dsi_pll_7nm_init,</div><div class='add'>+		.save_pll_state = dsi_7nm_pll_save_state,</div><div class='add'>+		.restore_pll_state = dsi_7nm_pll_restore_state,</div><div class='add'>+		.set_continuous_clock = dsi_7nm_set_continuous_clock,</div><div class='add'>+	},</div><div class='add'>+	.min_pll_rate = 600000000UL,</div><div class='add'>+#ifdef CONFIG_64BIT</div><div class='add'>+	.max_pll_rate = 5000000000UL,</div><div class='add'>+#else</div><div class='add'>+	.max_pll_rate = ULONG_MAX,</div><div class='add'>+#endif</div><div class='add'>+	.io_start = { 0xae95000, 0xae97000 },</div><div class='add'>+	.num_dsi_phy = 2,</div><div class='add'>+	.quirks = DSI_PHY_7NM_QUIRK_V5_2,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c b/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c<br/>index de182c004843..7aa500d24240 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/hdmi/hdmi_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/hdmi/hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/hdmi/hdmi_i2c.c</a></div><div class='hunk'>@@ -249,7 +249,6 @@ struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	i2c-&gt;owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	snprintf(i2c-&gt;name, sizeof(i2c-&gt;name), "msm hdmi i2c");</div><div class='ctx'> 	i2c-&gt;dev.parent = &amp;hdmi-&gt;pdev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;algo = &amp;msm_hdmi_i2c_algorithm;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c<br/>index 04d304eed223..4494f6d1c7cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_debugfs.c</a></div><div class='hunk'>@@ -304,36 +304,21 @@ int msm_debugfs_late_init(struct drm_device *dev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void msm_debugfs_init(struct drm_minor *minor)</div><div class='add'>+static void msm_debugfs_gpu_init(struct drm_minor *minor)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_device *dev = minor-&gt;dev;</div><div class='ctx'> 	struct msm_drm_private *priv = dev-&gt;dev_private;</div><div class='ctx'> 	struct dentry *gpu_devfreq;</div><div class='ctx'> </div><div class='del'>-	drm_debugfs_create_files(msm_debugfs_list,</div><div class='del'>-				 ARRAY_SIZE(msm_debugfs_list),</div><div class='del'>-				 minor-&gt;debugfs_root, minor);</div><div class='del'>-</div><div class='ctx'> 	debugfs_create_file("gpu", S_IRUSR, minor-&gt;debugfs_root,</div><div class='ctx'> 		dev, &amp;msm_gpu_fops);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;kms) {</div><div class='del'>-		drm_debugfs_create_files(msm_kms_debugfs_list,</div><div class='del'>-					 ARRAY_SIZE(msm_kms_debugfs_list),</div><div class='del'>-					 minor-&gt;debugfs_root, minor);</div><div class='del'>-		debugfs_create_file("kms", S_IRUSR, minor-&gt;debugfs_root,</div><div class='del'>-				    dev, &amp;msm_kms_fops);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	debugfs_create_u32("hangcheck_period_ms", 0600, minor-&gt;debugfs_root,</div><div class='ctx'> 		&amp;priv-&gt;hangcheck_period);</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_bool("disable_err_irq", 0600, minor-&gt;debugfs_root,</div><div class='ctx'> 		&amp;priv-&gt;disable_err_irq);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file("shrink", S_IRWXU, minor-&gt;debugfs_root,</div><div class='del'>-		dev, &amp;shrink_fops);</div><div class='del'>-</div><div class='ctx'> 	gpu_devfreq = debugfs_create_dir("devfreq", minor-&gt;debugfs_root);</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_bool("idle_clamp",0600, gpu_devfreq,</div><div class='hunk'>@@ -344,6 +329,30 @@ void msm_debugfs_init(struct drm_minor *minor)</div><div class='ctx'> </div><div class='ctx'> 	debugfs_create_u32("downdifferential",0600, gpu_devfreq,</div><div class='ctx'> 			   &amp;priv-&gt;gpu_devfreq_config.downdifferential);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void msm_debugfs_init(struct drm_minor *minor)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = minor-&gt;dev;</div><div class='add'>+	struct msm_drm_private *priv = dev-&gt;dev_private;</div><div class='add'>+</div><div class='add'>+	drm_debugfs_create_files(msm_debugfs_list,</div><div class='add'>+				 ARRAY_SIZE(msm_debugfs_list),</div><div class='add'>+				 minor-&gt;debugfs_root, minor);</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;gpu_pdev)</div><div class='add'>+		msm_debugfs_gpu_init(minor);</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;kms) {</div><div class='add'>+		drm_debugfs_create_files(msm_kms_debugfs_list,</div><div class='add'>+					 ARRAY_SIZE(msm_kms_debugfs_list),</div><div class='add'>+					 minor-&gt;debugfs_root, minor);</div><div class='add'>+		debugfs_create_file("kms", S_IRUSR, minor-&gt;debugfs_root,</div><div class='add'>+				    dev, &amp;msm_kms_fops);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("shrink", S_IRWXU, minor-&gt;debugfs_root,</div><div class='add'>+		dev, &amp;shrink_fops);</div><div class='ctx'> </div><div class='ctx'> 	if (priv-&gt;kms &amp;&amp; priv-&gt;kms-&gt;funcs-&gt;debugfs_init)</div><div class='ctx'> 		priv-&gt;kms-&gt;funcs-&gt;debugfs_init(priv-&gt;kms, minor);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c<br/>index 3f217b578293..50b65ffc24b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_drv.c</a></div><div class='hunk'>@@ -37,9 +37,10 @@</div><div class='ctx'>  * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN</div><div class='ctx'>  * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT</div><div class='ctx'>  * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)</div><div class='add'>+ * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA</div><div class='ctx'>  */</div><div class='ctx'> #define MSM_VERSION_MAJOR	1</div><div class='del'>-#define MSM_VERSION_MINOR	10</div><div class='add'>+#define MSM_VERSION_MINOR	12</div><div class='ctx'> #define MSM_VERSION_PATCHLEVEL	0</div><div class='ctx'> </div><div class='ctx'> static void msm_deinit_vram(struct drm_device *ddev);</div><div class='hunk'>@@ -544,6 +545,85 @@ static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,</div><div class='ctx'> 	return msm_gem_set_iova(obj, ctx-&gt;aspace, iova);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,</div><div class='add'>+					   __user void *metadata,</div><div class='add'>+					   u32 metadata_size)</div><div class='add'>+{</div><div class='add'>+	struct msm_gem_object *msm_obj = to_msm_bo(obj);</div><div class='add'>+	void *buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Impose a moderate upper bound on metadata size: */</div><div class='add'>+	if (metadata_size &gt; 128) {</div><div class='add'>+		return -EOVERFLOW;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */</div><div class='add'>+	buf = memdup_user(metadata, metadata_size);</div><div class='add'>+	if (IS_ERR(buf))</div><div class='add'>+		return PTR_ERR(buf);</div><div class='add'>+</div><div class='add'>+	ret = msm_gem_lock_interruptible(obj);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	msm_obj-&gt;metadata =</div><div class='add'>+		krealloc(msm_obj-&gt;metadata, metadata_size, GFP_KERNEL);</div><div class='add'>+	msm_obj-&gt;metadata_size = metadata_size;</div><div class='add'>+	memcpy(msm_obj-&gt;metadata, buf, metadata_size);</div><div class='add'>+</div><div class='add'>+	msm_gem_unlock(obj);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	kfree(buf);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,</div><div class='add'>+					   __user void *metadata,</div><div class='add'>+					   u32 *metadata_size)</div><div class='add'>+{</div><div class='add'>+	struct msm_gem_object *msm_obj = to_msm_bo(obj);</div><div class='add'>+	void *buf;</div><div class='add'>+	int ret, len;</div><div class='add'>+</div><div class='add'>+	if (!metadata) {</div><div class='add'>+		/*</div><div class='add'>+		 * Querying the size is inherently racey, but</div><div class='add'>+		 * EXT_external_objects expects the app to confirm</div><div class='add'>+		 * via device and driver UUIDs that the exporter and</div><div class='add'>+		 * importer versions match.  All we can do from the</div><div class='add'>+		 * kernel side is check the length under obj lock</div><div class='add'>+		 * when userspace tries to retrieve the metadata</div><div class='add'>+		 */</div><div class='add'>+		*metadata_size = msm_obj-&gt;metadata_size;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = msm_gem_lock_interruptible(obj);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Avoid copy_to_user() under gem obj lock: */</div><div class='add'>+	len = msm_obj-&gt;metadata_size;</div><div class='add'>+	buf = kmemdup(msm_obj-&gt;metadata, len, GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	msm_gem_unlock(obj);</div><div class='add'>+</div><div class='add'>+	if (*metadata_size &lt; len) {</div><div class='add'>+		ret = -ETOOSMALL;</div><div class='add'>+	} else if (copy_to_user(metadata, buf, len)) {</div><div class='add'>+		ret = -EFAULT;</div><div class='add'>+	} else {</div><div class='add'>+		*metadata_size = len;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int msm_ioctl_gem_info(struct drm_device *dev, void *data,</div><div class='ctx'> 		struct drm_file *file)</div><div class='ctx'> {</div><div class='hunk'>@@ -566,6 +646,8 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case MSM_INFO_SET_NAME:</div><div class='ctx'> 	case MSM_INFO_GET_NAME:</div><div class='add'>+	case MSM_INFO_SET_METADATA:</div><div class='add'>+	case MSM_INFO_GET_METADATA:</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -618,7 +700,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case MSM_INFO_GET_NAME:</div><div class='ctx'> 		if (args-&gt;value &amp;&amp; (args-&gt;len &lt; strlen(msm_obj-&gt;name))) {</div><div class='del'>-			ret = -EINVAL;</div><div class='add'>+			ret = -ETOOSMALL;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		args-&gt;len = strlen(msm_obj-&gt;name);</div><div class='hunk'>@@ -628,6 +710,14 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,</div><div class='ctx'> 				ret = -EFAULT;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='add'>+	case MSM_INFO_SET_METADATA:</div><div class='add'>+		ret = msm_ioctl_gem_info_set_metadata(</div><div class='add'>+			obj, u64_to_user_ptr(args-&gt;value), args-&gt;len);</div><div class='add'>+		break;</div><div class='add'>+	case MSM_INFO_GET_METADATA:</div><div class='add'>+		ret = msm_ioctl_gem_info_get_metadata(</div><div class='add'>+			obj, u64_to_user_ptr(args-&gt;value), &amp;args-&gt;len);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_object_put(obj);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h<br/>index cd5bf658df66..16a7cbc0b7dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_drv.h</a></div><div class='hunk'>@@ -78,12 +78,10 @@ enum msm_dsi_controller {</div><div class='ctx'>  * enum msm_event_wait - type of HW events to wait for</div><div class='ctx'>  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW</div><div class='ctx'>  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel</div><div class='del'>- * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)</div><div class='ctx'>  */</div><div class='ctx'> enum msm_event_wait {</div><div class='ctx'> 	MSM_ENC_COMMIT_DONE = 0,</div><div class='ctx'> 	MSM_ENC_TX_COMPLETE,</div><div class='del'>-	MSM_ENC_VBLANK,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -92,12 +90,14 @@ enum msm_event_wait {</div><div class='ctx'>  * @num_intf:     number of interfaces the panel is mounted on</div><div class='ctx'>  * @num_dspp:     number of dspp blocks used</div><div class='ctx'>  * @num_dsc:      number of Display Stream Compression (DSC) blocks used</div><div class='add'>+ * @needs_cdm:    indicates whether cdm block is needed for this display topology</div><div class='ctx'>  */</div><div class='ctx'> struct msm_display_topology {</div><div class='ctx'> 	u32 num_lm;</div><div class='ctx'> 	u32 num_intf;</div><div class='ctx'> 	u32 num_dspp;</div><div class='ctx'> 	u32 num_dsc;</div><div class='add'>+	bool needs_cdm;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Commit/Event thread specific structure */</div><div class='hunk'>@@ -386,10 +386,8 @@ int __init msm_dp_register(void);</div><div class='ctx'> void __exit msm_dp_unregister(void);</div><div class='ctx'> int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,</div><div class='ctx'> 			 struct drm_encoder *encoder);</div><div class='del'>-void msm_dp_irq_postinstall(struct msm_dp *dp_display);</div><div class='ctx'> void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);</div><div class='ctx'> </div><div class='del'>-void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);</div><div class='ctx'> bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);</div><div class='ctx'> </div><div class='ctx'> #else</div><div class='hunk'>@@ -407,19 +405,10 @@ static inline int msm_dp_modeset_init(struct msm_dp *dp_display,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,</div><div class='del'>-		struct drm_minor *minor)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)</div><div class='ctx'> {</div><div class='ctx'> 	return false;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c<br/>index db1e748daa75..175ee4ab8a6f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_gem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem.c</a></div><div class='hunk'>@@ -226,9 +226,9 @@ static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj,</div><div class='ctx'> </div><div class='ctx'> 	msm_gem_assert_locked(obj);</div><div class='ctx'> </div><div class='del'>-	if (GEM_WARN_ON(msm_obj-&gt;madv &gt; madv)) {</div><div class='del'>-		DRM_DEV_ERROR(obj-&gt;dev-&gt;dev, "Invalid madv state: %u vs %u\n",</div><div class='del'>-			msm_obj-&gt;madv, madv);</div><div class='add'>+	if (msm_obj-&gt;madv &gt; madv) {</div><div class='add'>+		DRM_DEV_DEBUG_DRIVER(obj-&gt;dev-&gt;dev, "Invalid madv state: %u vs %u\n",</div><div class='add'>+				     msm_obj-&gt;madv, madv);</div><div class='ctx'> 		return ERR_PTR(-EBUSY);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1058,6 +1058,7 @@ static void msm_gem_free_object(struct drm_gem_object *obj)</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_object_release(obj);</div><div class='ctx'> </div><div class='add'>+	kfree(msm_obj-&gt;metadata);</div><div class='ctx'> 	kfree(msm_obj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h<br/>index 8ddef5443140..8d414b072c29 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_gem.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem.h</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/kref.h&gt;</div><div class='ctx'> #include &lt;linux/dma-resv.h&gt;</div><div class='add'>+#include "drm/drm_exec.h"</div><div class='ctx'> #include "drm/gpu_scheduler.h"</div><div class='ctx'> #include "msm_drv.h"</div><div class='ctx'> </div><div class='hunk'>@@ -108,6 +109,10 @@ struct msm_gem_object {</div><div class='ctx'> </div><div class='ctx'> 	char name[32]; /* Identifier to print for the debugfs files */</div><div class='ctx'> </div><div class='add'>+	/* userspace metadata backchannel */</div><div class='add'>+	void *metadata;</div><div class='add'>+	u32 metadata_size;</div><div class='add'>+</div><div class='ctx'> 	/**</div><div class='ctx'> 	 * pin_count: Number of times the pages are pinned</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -254,7 +259,7 @@ struct msm_gem_submit {</div><div class='ctx'> 	struct msm_gpu *gpu;</div><div class='ctx'> 	struct msm_gem_address_space *aspace;</div><div class='ctx'> 	struct list_head node;   /* node in ring submit list */</div><div class='del'>-	struct ww_acquire_ctx ticket;</div><div class='add'>+	struct drm_exec exec;</div><div class='ctx'> 	uint32_t seqno;		/* Sequence number of the submit on the ring */</div><div class='ctx'> </div><div class='ctx'> 	/* Hw fence, which is created when the scheduler executes the job, and</div><div class='hunk'>@@ -270,9 +275,9 @@ struct msm_gem_submit {</div><div class='ctx'> 	int fence_id;       /* key into queue-&gt;fence_idr */</div><div class='ctx'> 	struct msm_gpu_submitqueue *queue;</div><div class='ctx'> 	struct pid *pid;    /* submitting process */</div><div class='del'>-	bool fault_dumped;  /* Limit devcoredump dumping to one per submit */</div><div class='del'>-	bool valid;         /* true if no cmdstream patching needed */</div><div class='del'>-	bool in_rb;         /* "sudo" mode, copy cmds into RB */</div><div class='add'>+	bool bos_pinned : 1;</div><div class='add'>+	bool fault_dumped:1;/* Limit devcoredump dumping to one per submit */</div><div class='add'>+	bool in_rb : 1;     /* "sudo" mode, copy cmds into RB */</div><div class='ctx'> 	struct msm_ringbuffer *ring;</div><div class='ctx'> 	unsigned int nr_cmds;</div><div class='ctx'> 	unsigned int nr_bos;</div><div class='hunk'>@@ -287,10 +292,6 @@ struct msm_gem_submit {</div><div class='ctx'> 		struct drm_msm_gem_submit_reloc *relocs;</div><div class='ctx'> 	} *cmd;  /* array of size nr_cmds */</div><div class='ctx'> 	struct {</div><div class='del'>-/* make sure these don't conflict w/ MSM_SUBMIT_BO_x */</div><div class='del'>-#define BO_VALID	0x8000	/* is current addr in cmdstream correct/valid? */</div><div class='del'>-#define BO_LOCKED	0x4000	/* obj lock is held */</div><div class='del'>-#define BO_PINNED	0x2000	/* obj (pages) is pinned and on active list */</div><div class='ctx'> 		uint32_t flags;</div><div class='ctx'> 		union {</div><div class='ctx'> 			struct drm_gem_object *obj;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c<br/>index 5a7d48c02c4b..07ca4ddfe4e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem_shrinker.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_gem_shrinker.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem_shrinker.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem_shrinker.c</a></div><div class='hunk'>@@ -75,7 +75,7 @@ static bool</div><div class='ctx'> wait_for_idle(struct drm_gem_object *obj)</div><div class='ctx'> {</div><div class='ctx'> 	enum dma_resv_usage usage = dma_resv_usage_rw(true);</div><div class='del'>-	return dma_resv_wait_timeout(obj-&gt;resv, usage, false, 1000) &gt; 0;</div><div class='add'>+	return dma_resv_wait_timeout(obj-&gt;resv, usage, false, 10) &gt; 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c<br/>index c002cabe7b9c..fba78193127d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem_submit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_gem_submit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gem_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gem_submit.c</a></div><div class='hunk'>@@ -17,6 +17,12 @@</div><div class='ctx'> #include "msm_gem.h"</div><div class='ctx'> #include "msm_gpu_trace.h"</div><div class='ctx'> </div><div class='add'>+/* For userspace errors, use DRM_UT_DRIVER.. so that userspace can enable</div><div class='add'>+ * error msgs for debugging, but we don't spam dmesg by default</div><div class='add'>+ */</div><div class='add'>+#define SUBMIT_ERROR(submit, fmt, ...) \</div><div class='add'>+	DRM_DEV_DEBUG_DRIVER((submit)-&gt;dev-&gt;dev, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Cmdstream submission:</div><div class='ctx'>  */</div><div class='hunk'>@@ -37,7 +43,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev,</div><div class='ctx'> 	if (sz &gt; SIZE_MAX)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	submit = kzalloc(sz, GFP_KERNEL);</div><div class='add'>+	submit = kzalloc(sz, GFP_KERNEL | __GFP_NOWARN);</div><div class='ctx'> 	if (!submit)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='hunk'>@@ -136,7 +142,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,</div><div class='ctx'> </div><div class='ctx'> 		if ((submit_bo.flags &amp; ~MSM_SUBMIT_BO_FLAGS) ||</div><div class='ctx'> 			!(submit_bo.flags &amp; MANDATORY_FLAGS)) {</div><div class='del'>-			DRM_ERROR("invalid flags: %x\n", submit_bo.flags);</div><div class='add'>+			SUBMIT_ERROR(submit, "invalid flags: %x\n", submit_bo.flags);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			i = 0;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -144,8 +150,6 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,</div><div class='ctx'> </div><div class='ctx'> 		submit-&gt;bos[i].handle = submit_bo.handle;</div><div class='ctx'> 		submit-&gt;bos[i].flags = submit_bo.flags;</div><div class='del'>-		/* in validate_objects() we figure out if this is true: */</div><div class='del'>-		submit-&gt;bos[i].iova  = submit_bo.presumed;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;file-&gt;table_lock);</div><div class='hunk'>@@ -158,7 +162,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit,</div><div class='ctx'> 		 */</div><div class='ctx'> 		obj = idr_find(&amp;file-&gt;object_idr, submit-&gt;bos[i].handle);</div><div class='ctx'> 		if (!obj) {</div><div class='del'>-			DRM_ERROR("invalid handle %u at index %u\n", submit-&gt;bos[i].handle, i);</div><div class='add'>+			SUBMIT_ERROR(submit, "invalid handle %u at index %u\n", submit-&gt;bos[i].handle, i);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto out_unlock;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -202,13 +206,13 @@ static int submit_lookup_cmds(struct msm_gem_submit *submit,</div><div class='ctx'> 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='del'>-			DRM_ERROR("invalid type: %08x\n", submit_cmd.type);</div><div class='add'>+			SUBMIT_ERROR(submit, "invalid type: %08x\n", submit_cmd.type);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (submit_cmd.size % 4) {</div><div class='del'>-			DRM_ERROR("non-aligned cmdstream buffer size: %u\n",</div><div class='del'>-					submit_cmd.size);</div><div class='add'>+			SUBMIT_ERROR(submit, "non-aligned cmdstream buffer size: %u\n",</div><div class='add'>+				     submit_cmd.size);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -228,7 +232,7 @@ static int submit_lookup_cmds(struct msm_gem_submit *submit,</div><div class='ctx'> 			ret = -ENOMEM;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='del'>-		submit-&gt;cmd[i].relocs = kmalloc(sz, GFP_KERNEL);</div><div class='add'>+		submit-&gt;cmd[i].relocs = kmalloc(sz, GFP_KERNEL | __GFP_NOWARN);</div><div class='ctx'> 		if (!submit-&gt;cmd[i].relocs) {</div><div class='ctx'> 			ret = -ENOMEM;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -244,101 +248,30 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* Unwind bo state, according to cleanup_flags.  In the success case, only</div><div class='del'>- * the lock is dropped at the end of the submit (and active/pin ref is dropped</div><div class='del'>- * later when the submit is retired).</div><div class='del'>- */</div><div class='del'>-static void submit_cleanup_bo(struct msm_gem_submit *submit, int i,</div><div class='del'>-		unsigned cleanup_flags)</div><div class='del'>-{</div><div class='del'>-	struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='del'>-	unsigned flags = submit-&gt;bos[i].flags &amp; cleanup_flags;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Clear flags bit before dropping lock, so that the msm_job_run()</div><div class='del'>-	 * path isn't racing with submit_cleanup() (ie. the read/modify/</div><div class='del'>-	 * write is protected by the obj lock in all paths)</div><div class='del'>-	 */</div><div class='del'>-	submit-&gt;bos[i].flags &amp;= ~cleanup_flags;</div><div class='del'>-</div><div class='del'>-	if (flags &amp; BO_PINNED)</div><div class='del'>-		msm_gem_unpin_locked(obj);</div><div class='del'>-</div><div class='del'>-	if (flags &amp; BO_LOCKED)</div><div class='del'>-		dma_resv_unlock(obj-&gt;resv);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i)</div><div class='del'>-{</div><div class='del'>-	unsigned cleanup_flags = BO_PINNED | BO_LOCKED;</div><div class='del'>-	submit_cleanup_bo(submit, i, cleanup_flags);</div><div class='del'>-</div><div class='del'>-	if (!(submit-&gt;bos[i].flags &amp; BO_VALID))</div><div class='del'>-		submit-&gt;bos[i].iova = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /* This is where we make sure all the bo's are reserved and pin'd: */</div><div class='ctx'> static int submit_lock_objects(struct msm_gem_submit *submit)</div><div class='ctx'> {</div><div class='del'>-	int contended, slow_locked = -1, i, ret = 0;</div><div class='del'>-</div><div class='del'>-retry:</div><div class='del'>-	for (i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='del'>-		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='del'>-</div><div class='del'>-		if (slow_locked == i)</div><div class='del'>-			slow_locked = -1;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-		contended = i;</div><div class='add'>+	drm_exec_init(&amp;submit-&gt;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, submit-&gt;nr_bos);</div><div class='ctx'> </div><div class='del'>-		if (!(submit-&gt;bos[i].flags &amp; BO_LOCKED)) {</div><div class='del'>-			ret = dma_resv_lock_interruptible(obj-&gt;resv,</div><div class='del'>-							  &amp;submit-&gt;ticket);</div><div class='add'>+	drm_exec_until_all_locked (&amp;submit-&gt;exec) {</div><div class='add'>+		for (unsigned i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='add'>+			struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='add'>+			ret = drm_exec_prepare_obj(&amp;submit-&gt;exec, obj, 1);</div><div class='add'>+			drm_exec_retry_on_contention(&amp;submit-&gt;exec);</div><div class='ctx'> 			if (ret)</div><div class='del'>-				goto fail;</div><div class='del'>-			submit-&gt;bos[i].flags |= BO_LOCKED;</div><div class='add'>+				goto error;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ww_acquire_done(&amp;submit-&gt;ticket);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-fail:</div><div class='del'>-	if (ret == -EALREADY) {</div><div class='del'>-		DRM_ERROR("handle %u at index %u already on submit list\n",</div><div class='del'>-				submit-&gt;bos[i].handle, i);</div><div class='del'>-		ret = -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (; i &gt;= 0; i--)</div><div class='del'>-		submit_unlock_unpin_bo(submit, i);</div><div class='del'>-</div><div class='del'>-	if (slow_locked &gt; 0)</div><div class='del'>-		submit_unlock_unpin_bo(submit, slow_locked);</div><div class='del'>-</div><div class='del'>-	if (ret == -EDEADLK) {</div><div class='del'>-		struct drm_gem_object *obj = submit-&gt;bos[contended].obj;</div><div class='del'>-		/* we lost out in a seqno race, lock and retry.. */</div><div class='del'>-		ret = dma_resv_lock_slow_interruptible(obj-&gt;resv,</div><div class='del'>-						       &amp;submit-&gt;ticket);</div><div class='del'>-		if (!ret) {</div><div class='del'>-			submit-&gt;bos[contended].flags |= BO_LOCKED;</div><div class='del'>-			slow_locked = contended;</div><div class='del'>-			goto retry;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Not expecting -EALREADY here, if the bo was already</div><div class='del'>-		 * locked, we should have gotten -EALREADY already from</div><div class='del'>-		 * the dma_resv_lock_interruptable() call.</div><div class='del'>-		 */</div><div class='del'>-		WARN_ON_ONCE(ret == -EALREADY);</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+error:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)</div><div class='add'>+static int submit_fence_sync(struct msm_gem_submit *submit)</div><div class='ctx'> {</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -346,22 +279,6 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)</div><div class='ctx'> 		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='ctx'> 		bool write = submit-&gt;bos[i].flags &amp; MSM_SUBMIT_BO_WRITE;</div><div class='ctx'> </div><div class='del'>-		/* NOTE: _reserve_shared() must happen before</div><div class='del'>-		 * _add_shared_fence(), which makes this a slightly</div><div class='del'>-		 * strange place to call it.  OTOH this is a</div><div class='del'>-		 * convenient can-fail point to hook it in.</div><div class='del'>-		 */</div><div class='del'>-		ret = dma_resv_reserve_fences(obj-&gt;resv, 1);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		/* If userspace has determined that explicit fencing is</div><div class='del'>-		 * used, it can disable implicit sync on the entire</div><div class='del'>-		 * submit:</div><div class='del'>-		 */</div><div class='del'>-		if (no_implicit)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='ctx'> 		/* Otherwise userspace can ask for implicit sync to be</div><div class='ctx'> 		 * disabled on specific buffers.  This is useful for internal</div><div class='ctx'> 		 * usermode driver managed buffers, suballocation, etc.</div><div class='hunk'>@@ -384,8 +301,6 @@ static int submit_pin_objects(struct msm_gem_submit *submit)</div><div class='ctx'> 	struct msm_drm_private *priv = submit-&gt;dev-&gt;dev_private;</div><div class='ctx'> 	int i, ret = 0;</div><div class='ctx'> </div><div class='del'>-	submit-&gt;valid = true;</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='ctx'> 		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='ctx'> 		struct msm_gem_vma *vma;</div><div class='hunk'>@@ -401,14 +316,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit)</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		if (vma-&gt;iova == submit-&gt;bos[i].iova) {</div><div class='del'>-			submit-&gt;bos[i].flags |= BO_VALID;</div><div class='del'>-		} else {</div><div class='del'>-			submit-&gt;bos[i].iova = vma-&gt;iova;</div><div class='del'>-			/* iova changed, so address in cmdstream is not valid: */</div><div class='del'>-			submit-&gt;bos[i].flags &amp;= ~BO_VALID;</div><div class='del'>-			submit-&gt;valid = false;</div><div class='del'>-		}</div><div class='add'>+		submit-&gt;bos[i].iova = vma-&gt;iova;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -421,13 +329,28 @@ static int submit_pin_objects(struct msm_gem_submit *submit)</div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;lru.lock);</div><div class='ctx'> 	for (i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='ctx'> 		msm_gem_pin_obj_locked(submit-&gt;bos[i].obj);</div><div class='del'>-		submit-&gt;bos[i].flags |= BO_PINNED;</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;lru.lock);</div><div class='ctx'> </div><div class='add'>+	submit-&gt;bos_pinned = true;</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void submit_unpin_objects(struct msm_gem_submit *submit)</div><div class='add'>+{</div><div class='add'>+	if (!submit-&gt;bos_pinned)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='add'>+		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='add'>+</div><div class='add'>+		msm_gem_unpin_locked(obj);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	submit-&gt;bos_pinned = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void submit_attach_object_fences(struct msm_gem_submit *submit)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -445,11 +368,11 @@ static void submit_attach_object_fences(struct msm_gem_submit *submit)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int submit_bo(struct msm_gem_submit *submit, uint32_t idx,</div><div class='del'>-		struct drm_gem_object **obj, uint64_t *iova, bool *valid)</div><div class='add'>+		struct drm_gem_object **obj, uint64_t *iova)</div><div class='ctx'> {</div><div class='ctx'> 	if (idx &gt;= submit-&gt;nr_bos) {</div><div class='del'>-		DRM_ERROR("invalid buffer index: %u (out of %u)\n",</div><div class='del'>-				idx, submit-&gt;nr_bos);</div><div class='add'>+		SUBMIT_ERROR(submit, "invalid buffer index: %u (out of %u)\n",</div><div class='add'>+			     idx, submit-&gt;nr_bos);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -457,8 +380,6 @@ static int submit_bo(struct msm_gem_submit *submit, uint32_t idx,</div><div class='ctx'> 		*obj = submit-&gt;bos[idx].obj;</div><div class='ctx'> 	if (iova)</div><div class='ctx'> 		*iova = submit-&gt;bos[idx].iova;</div><div class='del'>-	if (valid)</div><div class='del'>-		*valid = !!(submit-&gt;bos[idx].flags &amp; BO_VALID);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -471,11 +392,8 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob</div><div class='ctx'> 	uint32_t *ptr;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (!nr_relocs)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	if (offset % 4) {</div><div class='del'>-		DRM_ERROR("non-aligned cmdstream buffer: %u\n", offset);</div><div class='add'>+		SUBMIT_ERROR(submit, "non-aligned cmdstream buffer: %u\n", offset);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -494,11 +412,10 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob</div><div class='ctx'> 		struct drm_msm_gem_submit_reloc submit_reloc = relocs[i];</div><div class='ctx'> 		uint32_t off;</div><div class='ctx'> 		uint64_t iova;</div><div class='del'>-		bool valid;</div><div class='ctx'> </div><div class='ctx'> 		if (submit_reloc.submit_offset % 4) {</div><div class='del'>-			DRM_ERROR("non-aligned reloc offset: %u\n",</div><div class='del'>-					submit_reloc.submit_offset);</div><div class='add'>+			SUBMIT_ERROR(submit, "non-aligned reloc offset: %u\n",</div><div class='add'>+				     submit_reloc.submit_offset);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -508,18 +425,15 @@ static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *ob</div><div class='ctx'> </div><div class='ctx'> 		if ((off &gt;= (obj-&gt;size / 4)) ||</div><div class='ctx'> 				(off &lt; last_offset)) {</div><div class='del'>-			DRM_ERROR("invalid offset %u at reloc %u\n", off, i);</div><div class='add'>+			SUBMIT_ERROR(submit, "invalid offset %u at reloc %u\n", off, i);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ret = submit_bo(submit, submit_reloc.reloc_idx, NULL, &amp;iova, &amp;valid);</div><div class='add'>+		ret = submit_bo(submit, submit_reloc.reloc_idx, NULL, &amp;iova);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto out;</div><div class='ctx'> </div><div class='del'>-		if (valid)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='ctx'> 		iova += submit_reloc.reloc_offset;</div><div class='ctx'> </div><div class='ctx'> 		if (submit_reloc.shift &lt; 0)</div><div class='hunk'>@@ -544,18 +458,14 @@ out:</div><div class='ctx'>  */</div><div class='ctx'> static void submit_cleanup(struct msm_gem_submit *submit, bool error)</div><div class='ctx'> {</div><div class='del'>-	unsigned cleanup_flags = BO_LOCKED;</div><div class='del'>-	unsigned i;</div><div class='del'>-</div><div class='del'>-	if (error)</div><div class='del'>-		cleanup_flags |= BO_PINNED;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; submit-&gt;nr_bos; i++) {</div><div class='del'>-		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='del'>-		submit_cleanup_bo(submit, i, cleanup_flags);</div><div class='del'>-		if (error)</div><div class='del'>-			drm_gem_object_put(obj);</div><div class='add'>+	if (error) {</div><div class='add'>+		submit_unpin_objects(submit);</div><div class='add'>+		/* job wasn't enqueued to scheduler, so early retirement: */</div><div class='add'>+		msm_submit_retire(submit);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (submit-&gt;exec.objects)</div><div class='add'>+		drm_exec_fini(&amp;submit-&gt;exec);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void msm_submit_retire(struct msm_gem_submit *submit)</div><div class='hunk'>@@ -749,7 +659,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,</div><div class='ctx'> 	struct msm_submit_post_dep *post_deps = NULL;</div><div class='ctx'> 	struct drm_syncobj **syncobjs_to_reset = NULL;</div><div class='ctx'> 	int out_fence_fd = -1;</div><div class='del'>-	bool has_ww_ticket = false;</div><div class='ctx'> 	unsigned i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -855,15 +764,15 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	/* copy_*_user while holding a ww ticket upsets lockdep */</div><div class='del'>-	ww_acquire_init(&amp;submit-&gt;ticket, &amp;reservation_ww_class);</div><div class='del'>-	has_ww_ticket = true;</div><div class='ctx'> 	ret = submit_lock_objects(submit);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	ret = submit_fence_sync(submit, !!(args-&gt;flags &amp; MSM_SUBMIT_NO_IMPLICIT));</div><div class='del'>-	if (ret)</div><div class='del'>-		goto out;</div><div class='add'>+	if (!(args-&gt;flags &amp; MSM_SUBMIT_NO_IMPLICIT)) {</div><div class='add'>+		ret = submit_fence_sync(submit);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = submit_pin_objects(submit);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -873,32 +782,27 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,</div><div class='ctx'> 		struct drm_gem_object *obj;</div><div class='ctx'> 		uint64_t iova;</div><div class='ctx'> </div><div class='del'>-		ret = submit_bo(submit, submit-&gt;cmd[i].idx,</div><div class='del'>-				&amp;obj, &amp;iova, NULL);</div><div class='add'>+		ret = submit_bo(submit, submit-&gt;cmd[i].idx, &amp;obj, &amp;iova);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto out;</div><div class='ctx'> </div><div class='ctx'> 		if (!submit-&gt;cmd[i].size ||</div><div class='ctx'> 			((submit-&gt;cmd[i].size + submit-&gt;cmd[i].offset) &gt;</div><div class='ctx'> 				obj-&gt;size / 4)) {</div><div class='del'>-			DRM_ERROR("invalid cmdstream size: %u\n", submit-&gt;cmd[i].size * 4);</div><div class='add'>+			SUBMIT_ERROR(submit, "invalid cmdstream size: %u\n", submit-&gt;cmd[i].size * 4);</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		submit-&gt;cmd[i].iova = iova + (submit-&gt;cmd[i].offset * 4);</div><div class='ctx'> </div><div class='del'>-		if (submit-&gt;valid)</div><div class='add'>+		if (likely(!submit-&gt;cmd[i].nr_relocs))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (!gpu-&gt;allow_relocs) {</div><div class='del'>-			if (submit-&gt;cmd[i].nr_relocs) {</div><div class='del'>-				DRM_ERROR("relocs not allowed\n");</div><div class='del'>-				ret = -EINVAL;</div><div class='del'>-				goto out;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			continue;</div><div class='add'>+			SUBMIT_ERROR(submit, "relocs not allowed\n");</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = submit_reloc(submit, obj, submit-&gt;cmd[i].offset * 4,</div><div class='hunk'>@@ -974,6 +878,9 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	submit_attach_object_fences(submit);</div><div class='ctx'> </div><div class='ctx'> 	/* The scheduler owns a ref now: */</div><div class='hunk'>@@ -993,8 +900,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	submit_cleanup(submit, !!ret);</div><div class='del'>-	if (has_ww_ticket)</div><div class='del'>-		ww_acquire_fini(&amp;submit-&gt;ticket);</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;queue-&gt;lock);</div><div class='ctx'> out_post_unlock:</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c<br/>index 7f64c6667300..095390774f22 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gpu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_gpu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_gpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_gpu.c</a></div><div class='hunk'>@@ -292,8 +292,7 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,</div><div class='ctx'> 	/* Set the active crash state to be dumped on failure */</div><div class='ctx'> 	gpu-&gt;crashstate = state;</div><div class='ctx'> </div><div class='del'>-	/* FIXME: Release the crashstate if this errors out? */</div><div class='del'>-	dev_coredumpm(gpu-&gt;dev-&gt;dev, THIS_MODULE, gpu, 0, GFP_KERNEL,</div><div class='add'>+	dev_coredumpm(&amp;gpu-&gt;pdev-&gt;dev, THIS_MODULE, gpu, 0, GFP_KERNEL,</div><div class='ctx'> 		msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);</div><div class='ctx'> }</div><div class='ctx'> #else</div><div class='hunk'>@@ -366,29 +365,31 @@ static void recover_worker(struct kthread_work *work)</div><div class='ctx'> 	DRM_DEV_ERROR(dev-&gt;dev, "%s: hangcheck recover!\n", gpu-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 	submit = find_submit(cur_ring, cur_ring-&gt;memptrs-&gt;fence + 1);</div><div class='del'>-	if (submit) {</div><div class='del'>-		/* Increment the fault counts */</div><div class='del'>-		submit-&gt;queue-&gt;faults++;</div><div class='del'>-		if (submit-&gt;aspace)</div><div class='del'>-			submit-&gt;aspace-&gt;faults++;</div><div class='ctx'> </div><div class='del'>-		get_comm_cmdline(submit, &amp;comm, &amp;cmd);</div><div class='add'>+	/*</div><div class='add'>+	 * If the submit retired while we were waiting for the worker to run,</div><div class='add'>+	 * or waiting to acquire the gpu lock, then nothing more to do.</div><div class='add'>+	 */</div><div class='add'>+	if (!submit)</div><div class='add'>+		goto out_unlock;</div><div class='ctx'> </div><div class='del'>-		if (comm &amp;&amp; cmd) {</div><div class='del'>-			DRM_DEV_ERROR(dev-&gt;dev, "%s: offending task: %s (%s)\n",</div><div class='del'>-				gpu-&gt;name, comm, cmd);</div><div class='add'>+	/* Increment the fault counts */</div><div class='add'>+	submit-&gt;queue-&gt;faults++;</div><div class='add'>+	if (submit-&gt;aspace)</div><div class='add'>+		submit-&gt;aspace-&gt;faults++;</div><div class='ctx'> </div><div class='del'>-			msm_rd_dump_submit(priv-&gt;hangrd, submit,</div><div class='del'>-				"offending task: %s (%s)", comm, cmd);</div><div class='del'>-		} else {</div><div class='del'>-			msm_rd_dump_submit(priv-&gt;hangrd, submit, NULL);</div><div class='del'>-		}</div><div class='add'>+	get_comm_cmdline(submit, &amp;comm, &amp;cmd);</div><div class='add'>+</div><div class='add'>+	if (comm &amp;&amp; cmd) {</div><div class='add'>+		DRM_DEV_ERROR(dev-&gt;dev, "%s: offending task: %s (%s)\n",</div><div class='add'>+			      gpu-&gt;name, comm, cmd);</div><div class='add'>+</div><div class='add'>+		msm_rd_dump_submit(priv-&gt;hangrd, submit,</div><div class='add'>+				   "offending task: %s (%s)", comm, cmd);</div><div class='ctx'> 	} else {</div><div class='del'>-		/*</div><div class='del'>-		 * We couldn't attribute this fault to any particular context,</div><div class='del'>-		 * so increment the global fault count instead.</div><div class='del'>-		 */</div><div class='del'>-		gpu-&gt;global_faults++;</div><div class='add'>+		DRM_DEV_ERROR(dev-&gt;dev, "%s: offending task: unknown\n", gpu-&gt;name);</div><div class='add'>+</div><div class='add'>+		msm_rd_dump_submit(priv-&gt;hangrd, submit, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Record the crash state */</div><div class='hunk'>@@ -441,6 +442,7 @@ static void recover_worker(struct kthread_work *work)</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_put(&amp;gpu-&gt;pdev-&gt;dev);</div><div class='ctx'> </div><div class='add'>+out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;gpu-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	msm_gpu_retire(gpu);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c<br/>index 6865db1e3ce8..455b2e3a0cdd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_mdss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_mdss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_mdss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_mdss.c</a></div><div class='hunk'>@@ -28,6 +28,8 @@</div><div class='ctx'> </div><div class='ctx'> #define MIN_IB_BW	400000000UL /* Min ib vote 400MB */</div><div class='ctx'> </div><div class='add'>+#define DEFAULT_REG_BW	153600 /* Used in mdss fbdev driver */</div><div class='add'>+</div><div class='ctx'> struct msm_mdss {</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> </div><div class='hunk'>@@ -40,8 +42,9 @@ struct msm_mdss {</div><div class='ctx'> 		struct irq_domain *domain;</div><div class='ctx'> 	} irq_controller;</div><div class='ctx'> 	const struct msm_mdss_data *mdss_data;</div><div class='del'>-	struct icc_path *path[2];</div><div class='del'>-	u32 num_paths;</div><div class='add'>+	struct icc_path *mdp_path[2];</div><div class='add'>+	u32 num_mdp_paths;</div><div class='add'>+	struct icc_path *reg_bus_path;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int msm_mdss_parse_data_bus_icc_path(struct device *dev,</div><div class='hunk'>@@ -49,38 +52,26 @@ static int msm_mdss_parse_data_bus_icc_path(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct icc_path *path0;</div><div class='ctx'> 	struct icc_path *path1;</div><div class='add'>+	struct icc_path *reg_bus_path;</div><div class='ctx'> </div><div class='del'>-	path0 = of_icc_get(dev, "mdp0-mem");</div><div class='add'>+	path0 = devm_of_icc_get(dev, "mdp0-mem");</div><div class='ctx'> 	if (IS_ERR_OR_NULL(path0))</div><div class='ctx'> 		return PTR_ERR_OR_ZERO(path0);</div><div class='ctx'> </div><div class='del'>-	msm_mdss-&gt;path[0] = path0;</div><div class='del'>-	msm_mdss-&gt;num_paths = 1;</div><div class='add'>+	msm_mdss-&gt;mdp_path[0] = path0;</div><div class='add'>+	msm_mdss-&gt;num_mdp_paths = 1;</div><div class='ctx'> </div><div class='del'>-	path1 = of_icc_get(dev, "mdp1-mem");</div><div class='add'>+	path1 = devm_of_icc_get(dev, "mdp1-mem");</div><div class='ctx'> 	if (!IS_ERR_OR_NULL(path1)) {</div><div class='del'>-		msm_mdss-&gt;path[1] = path1;</div><div class='del'>-		msm_mdss-&gt;num_paths++;</div><div class='add'>+		msm_mdss-&gt;mdp_path[1] = path1;</div><div class='add'>+		msm_mdss-&gt;num_mdp_paths++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void msm_mdss_put_icc_path(void *data)</div><div class='del'>-{</div><div class='del'>-	struct msm_mdss *msm_mdss = data;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; msm_mdss-&gt;num_paths; i++)</div><div class='del'>-		icc_put(msm_mdss-&gt;path[i]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='add'>+	reg_bus_path = of_icc_get(dev, "cpu-cfg");</div><div class='add'>+	if (!IS_ERR_OR_NULL(reg_bus_path))</div><div class='add'>+		msm_mdss-&gt;reg_bus_path = reg_bus_path;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; msm_mdss-&gt;num_paths; i++)</div><div class='del'>-		icc_set_bw(msm_mdss-&gt;path[i], 0, Bps_to_icc(bw));</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void msm_mdss_irq(struct irq_desc *desc)</div><div class='hunk'>@@ -236,14 +227,22 @@ const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> static int msm_mdss_enable(struct msm_mdss *msm_mdss)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='add'>+	int ret, i;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Several components have AXI clocks that can only be turned on if</div><div class='ctx'> 	 * the interconnect is enabled (non-zero bandwidth). Let's make sure</div><div class='ctx'> 	 * that the interconnects are at least at a minimum amount.</div><div class='ctx'> 	 */</div><div class='del'>-	msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW);</div><div class='add'>+	for (i = 0; i &lt; msm_mdss-&gt;num_mdp_paths; i++)</div><div class='add'>+		icc_set_bw(msm_mdss-&gt;mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));</div><div class='add'>+</div><div class='add'>+	if (msm_mdss-&gt;mdss_data &amp;&amp; msm_mdss-&gt;mdss_data-&gt;reg_bus_bw)</div><div class='add'>+		icc_set_bw(msm_mdss-&gt;reg_bus_path, 0,</div><div class='add'>+			   msm_mdss-&gt;mdss_data-&gt;reg_bus_bw);</div><div class='add'>+	else</div><div class='add'>+		icc_set_bw(msm_mdss-&gt;reg_bus_path, 0,</div><div class='add'>+			   DEFAULT_REG_BW);</div><div class='ctx'> </div><div class='ctx'> 	ret = clk_bulk_prepare_enable(msm_mdss-&gt;num_clocks, msm_mdss-&gt;clocks);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -295,8 +294,15 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)</div><div class='ctx'> </div><div class='ctx'> static int msm_mdss_disable(struct msm_mdss *msm_mdss)</div><div class='ctx'> {</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='ctx'> 	clk_bulk_disable_unprepare(msm_mdss-&gt;num_clocks, msm_mdss-&gt;clocks);</div><div class='del'>-	msm_mdss_icc_request_bw(msm_mdss, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; msm_mdss-&gt;num_mdp_paths; i++)</div><div class='add'>+		icc_set_bw(msm_mdss-&gt;mdp_path[i], 0, 0);</div><div class='add'>+</div><div class='add'>+	if (msm_mdss-&gt;reg_bus_path)</div><div class='add'>+		icc_set_bw(msm_mdss-&gt;reg_bus_path, 0, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -384,6 +390,8 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5</div><div class='ctx'> 	if (!msm_mdss)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='add'>+	msm_mdss-&gt;mdss_data = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='ctx'> 	msm_mdss-&gt;mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");</div><div class='ctx'> 	if (IS_ERR(msm_mdss-&gt;mmio))</div><div class='ctx'> 		return ERR_CAST(msm_mdss-&gt;mmio);</div><div class='hunk'>@@ -393,9 +401,6 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5</div><div class='ctx'> 	ret = msm_mdss_parse_data_bus_icc_path(&amp;pdev-&gt;dev, msm_mdss);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='del'>-	ret = devm_add_action_or_reset(&amp;pdev-&gt;dev, msm_mdss_put_icc_path, msm_mdss);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ERR_PTR(ret);</div><div class='ctx'> </div><div class='ctx'> 	if (is_mdp5)</div><div class='ctx'> 		ret = mdp5_mdss_parse_clock(pdev, &amp;msm_mdss-&gt;clocks);</div><div class='hunk'>@@ -477,8 +482,6 @@ static int mdss_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (IS_ERR(mdss))</div><div class='ctx'> 		return PTR_ERR(mdss);</div><div class='ctx'> </div><div class='del'>-	mdss-&gt;mdss_data = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='ctx'> 	platform_set_drvdata(pdev, mdss);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -510,11 +513,13 @@ static const struct msm_mdss_data msm8998_data = {</div><div class='ctx'> 	.ubwc_enc_version = UBWC_1_0,</div><div class='ctx'> 	.ubwc_dec_version = UBWC_1_0,</div><div class='ctx'> 	.highest_bank_bit = 2,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data qcm2290_data = {</div><div class='ctx'> 	/* no UBWC */</div><div class='ctx'> 	.highest_bank_bit = 0x2,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sc7180_data = {</div><div class='hunk'>@@ -522,6 +527,7 @@ static const struct msm_mdss_data sc7180_data = {</div><div class='ctx'> 	.ubwc_dec_version = UBWC_2_0,</div><div class='ctx'> 	.ubwc_static = 0x1e,</div><div class='ctx'> 	.highest_bank_bit = 0x3,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sc7280_data = {</div><div class='hunk'>@@ -531,6 +537,7 @@ static const struct msm_mdss_data sc7280_data = {</div><div class='ctx'> 	.ubwc_static = 1,</div><div class='ctx'> 	.highest_bank_bit = 1,</div><div class='ctx'> 	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 74000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sc8180x_data = {</div><div class='hunk'>@@ -538,6 +545,7 @@ static const struct msm_mdss_data sc8180x_data = {</div><div class='ctx'> 	.ubwc_dec_version = UBWC_3_0,</div><div class='ctx'> 	.highest_bank_bit = 3,</div><div class='ctx'> 	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sc8280xp_data = {</div><div class='hunk'>@@ -545,14 +553,22 @@ static const struct msm_mdss_data sc8280xp_data = {</div><div class='ctx'> 	.ubwc_dec_version = UBWC_4_0,</div><div class='ctx'> 	.ubwc_swizzle = 6,</div><div class='ctx'> 	.ubwc_static = 1,</div><div class='del'>-	.highest_bank_bit = 2,</div><div class='add'>+	.highest_bank_bit = 3,</div><div class='ctx'> 	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct msm_mdss_data sdm670_data = {</div><div class='add'>+	.ubwc_enc_version = UBWC_2_0,</div><div class='add'>+	.ubwc_dec_version = UBWC_2_0,</div><div class='add'>+	.highest_bank_bit = 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sdm845_data = {</div><div class='ctx'> 	.ubwc_enc_version = UBWC_2_0,</div><div class='ctx'> 	.ubwc_dec_version = UBWC_2_0,</div><div class='ctx'> 	.highest_bank_bit = 2,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sm6350_data = {</div><div class='hunk'>@@ -561,12 +577,14 @@ static const struct msm_mdss_data sm6350_data = {</div><div class='ctx'> 	.ubwc_swizzle = 6,</div><div class='ctx'> 	.ubwc_static = 0x1e,</div><div class='ctx'> 	.highest_bank_bit = 1,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sm8150_data = {</div><div class='ctx'> 	.ubwc_enc_version = UBWC_3_0,</div><div class='ctx'> 	.ubwc_dec_version = UBWC_3_0,</div><div class='ctx'> 	.highest_bank_bit = 2,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sm6115_data = {</div><div class='hunk'>@@ -575,6 +593,7 @@ static const struct msm_mdss_data sm6115_data = {</div><div class='ctx'> 	.ubwc_swizzle = 7,</div><div class='ctx'> 	.ubwc_static = 0x11f,</div><div class='ctx'> 	.highest_bank_bit = 0x1,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sm6125_data = {</div><div class='hunk'>@@ -592,6 +611,18 @@ static const struct msm_mdss_data sm8250_data = {</div><div class='ctx'> 	/* TODO: highest_bank_bit = 2 for LP_DDR4 */</div><div class='ctx'> 	.highest_bank_bit = 3,</div><div class='ctx'> 	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 76800,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct msm_mdss_data sm8350_data = {</div><div class='add'>+	.ubwc_enc_version = UBWC_4_0,</div><div class='add'>+	.ubwc_dec_version = UBWC_4_0,</div><div class='add'>+	.ubwc_swizzle = 6,</div><div class='add'>+	.ubwc_static = 1,</div><div class='add'>+	/* TODO: highest_bank_bit = 2 for LP_DDR4 */</div><div class='add'>+	.highest_bank_bit = 3,</div><div class='add'>+	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 74000,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct msm_mdss_data sm8550_data = {</div><div class='hunk'>@@ -602,11 +633,13 @@ static const struct msm_mdss_data sm8550_data = {</div><div class='ctx'> 	/* TODO: highest_bank_bit = 2 for LP_DDR4 */</div><div class='ctx'> 	.highest_bank_bit = 3,</div><div class='ctx'> 	.macrotile_mode = 1,</div><div class='add'>+	.reg_bus_bw = 57000,</div><div class='ctx'> };</div><div class='ctx'> static const struct of_device_id mdss_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,mdss" },</div><div class='ctx'> 	{ .compatible = "qcom,msm8998-mdss", .data = &amp;msm8998_data },</div><div class='ctx'> 	{ .compatible = "qcom,qcm2290-mdss", .data = &amp;qcm2290_data },</div><div class='add'>+	{ .compatible = "qcom,sdm670-mdss", .data = &amp;sdm670_data },</div><div class='ctx'> 	{ .compatible = "qcom,sdm845-mdss", .data = &amp;sdm845_data },</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-mdss", .data = &amp;sc7180_data },</div><div class='ctx'> 	{ .compatible = "qcom,sc7280-mdss", .data = &amp;sc7280_data },</div><div class='hunk'>@@ -618,9 +651,10 @@ static const struct of_device_id mdss_dt_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sm6375-mdss", .data = &amp;sm6350_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm8150-mdss", .data = &amp;sm8150_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm8250-mdss", .data = &amp;sm8250_data },</div><div class='del'>-	{ .compatible = "qcom,sm8350-mdss", .data = &amp;sm8250_data },</div><div class='del'>-	{ .compatible = "qcom,sm8450-mdss", .data = &amp;sm8250_data },</div><div class='add'>+	{ .compatible = "qcom,sm8350-mdss", .data = &amp;sm8350_data },</div><div class='add'>+	{ .compatible = "qcom,sm8450-mdss", .data = &amp;sm8350_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm8550-mdss", .data = &amp;sm8550_data },</div><div class='add'>+	{ .compatible = "qcom,sm8650-mdss", .data = &amp;sm8550_data},</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, mdss_dt_match);</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h<br/>index 02bbab42adbc..3afef4b1786d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_mdss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_mdss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_mdss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_mdss.h</a></div><div class='hunk'>@@ -14,6 +14,7 @@ struct msm_mdss_data {</div><div class='ctx'> 	u32 ubwc_static;</div><div class='ctx'> 	u32 highest_bank_bit;</div><div class='ctx'> 	u32 macrotile_mode;</div><div class='add'>+	u32 reg_bus_bw;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define UBWC_1_0 0x10000000</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c<br/>index 5adc51f7ab59..ca44fd291c5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_rd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_rd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_rd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_rd.c</a></div><div class='hunk'>@@ -270,6 +270,9 @@ int msm_rd_debugfs_init(struct drm_minor *minor)</div><div class='ctx'> 	struct msm_rd_state *rd;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (!priv-&gt;gpu_pdev)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	/* only create on first minor: */</div><div class='ctx'> 	if (priv-&gt;rd)</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c<br/>index 4968568e3b54..4bc13f7d005a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_ringbuffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/msm/msm_ringbuffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/msm/msm_ringbuffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/msm/msm_ringbuffer.c</a></div><div class='hunk'>@@ -29,9 +29,10 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job)</div><div class='ctx'> 		struct drm_gem_object *obj = submit-&gt;bos[i].obj;</div><div class='ctx'> </div><div class='ctx'> 		msm_gem_unpin_active(obj);</div><div class='del'>-		submit-&gt;bos[i].flags &amp;= ~BO_PINNED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	submit-&gt;bos_pinned = false;</div><div class='add'>+</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;lru.lock);</div><div class='ctx'> </div><div class='ctx'> 	msm_gpu_submit(gpu, submit);</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c<br/>index 11fe75b68e95..8d37a694b772 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/dispnv50/disp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/dispnv50/disp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/dispnv50/disp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/dispnv50/disp.c</a></div><div class='hunk'>@@ -2476,7 +2476,7 @@ nv50_disp_atomic_commit(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> err_cleanup:</div><div class='ctx'> 	if (ret)</div><div class='del'>-		drm_atomic_helper_cleanup_planes(dev, state);</div><div class='add'>+		drm_atomic_helper_unprepare_planes(dev, state);</div><div class='ctx'> done:</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev-&gt;dev);</div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h<br/>index 2fa0445d8928..d1437c08645f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h</a></div><div class='hunk'>@@ -187,7 +187,7 @@ struct nvkm_gsp {</div><div class='ctx'> 		void (*rpc_done)(struct nvkm_gsp *gsp, void *repv);</div><div class='ctx'> </div><div class='ctx'> 		void *(*rm_ctrl_get)(struct nvkm_gsp_object *, u32 cmd, u32 argc);</div><div class='del'>-		void *(*rm_ctrl_push)(struct nvkm_gsp_object *, void *argv, u32 repc);</div><div class='add'>+		int (*rm_ctrl_push)(struct nvkm_gsp_object *, void **argv, u32 repc);</div><div class='ctx'> 		void (*rm_ctrl_done)(struct nvkm_gsp_object *, void *repv);</div><div class='ctx'> </div><div class='ctx'> 		void *(*rm_alloc_get)(struct nvkm_gsp_object *, u32 oclass, u32 argc);</div><div class='hunk'>@@ -265,7 +265,7 @@ nvkm_gsp_rm_ctrl_get(struct nvkm_gsp_object *object, u32 cmd, u32 argc)</div><div class='ctx'> 	return object-&gt;client-&gt;gsp-&gt;rm-&gt;rm_ctrl_get(object, cmd, argc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void *</div><div class='add'>+static inline int</div><div class='ctx'> nvkm_gsp_rm_ctrl_push(struct nvkm_gsp_object *object, void *argv, u32 repc)</div><div class='ctx'> {</div><div class='ctx'> 	return object-&gt;client-&gt;gsp-&gt;rm-&gt;rm_ctrl_push(object, argv, repc);</div><div class='hunk'>@@ -275,21 +275,24 @@ static inline void *</div><div class='ctx'> nvkm_gsp_rm_ctrl_rd(struct nvkm_gsp_object *object, u32 cmd, u32 repc)</div><div class='ctx'> {</div><div class='ctx'> 	void *argv = nvkm_gsp_rm_ctrl_get(object, cmd, repc);</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ERR(argv))</div><div class='ctx'> 		return argv;</div><div class='ctx'> </div><div class='del'>-	return nvkm_gsp_rm_ctrl_push(object, argv, repc);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(object, &amp;argv, repc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+	return argv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int</div><div class='ctx'> nvkm_gsp_rm_ctrl_wr(struct nvkm_gsp_object *object, void *argv)</div><div class='ctx'> {</div><div class='del'>-	void *repv = nvkm_gsp_rm_ctrl_push(object, argv, 0);</div><div class='del'>-</div><div class='del'>-	if (IS_ERR(repv))</div><div class='del'>-		return PTR_ERR(repv);</div><div class='add'>+	int ret = nvkm_gsp_rm_ctrl_push(object, &amp;argv, 0);</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h b/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h<br/>index 5a2f273d95c8..0e32e71e123f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/msgq_priv.h</a></div><div class='hunk'>@@ -26,6 +26,49 @@</div><div class='ctx'>  * DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * msgqTxHeader -- TX queue data structure</div><div class='add'>+ * @version: the version of this structure, must be 0</div><div class='add'>+ * @size: the size of the entire queue, including this header</div><div class='add'>+ * @msgSize: the padded size of queue element, 16 is minimum</div><div class='add'>+ * @msgCount: the number of elements in this queue</div><div class='add'>+ * @writePtr: head index of this queue</div><div class='add'>+ * @flags: 1 = swap the RX pointers</div><div class='add'>+ * @rxHdrOff: offset of readPtr in this structure</div><div class='add'>+ * @entryOff: offset of beginning of queue (msgqRxHeader), relative to</div><div class='add'>+ *          beginning of this structure</div><div class='add'>+ *</div><div class='add'>+ * The command queue is a queue of RPCs that are sent from the driver to the</div><div class='add'>+ * GSP.  The status queue is a queue of messages/responses from GSP-RM to the</div><div class='add'>+ * driver.  Although the driver allocates memory for both queues, the command</div><div class='add'>+ * queue is owned by the driver and the status queue is owned by GSP-RM.  In</div><div class='add'>+ * addition, the headers of the two queues must not share the same 4K page.</div><div class='add'>+ *</div><div class='add'>+ * Each queue is prefixed with this data structure.  The idea is that a queue</div><div class='add'>+ * and its header are written to only by their owner.  That is, only the</div><div class='add'>+ * driver writes to the command queue and command queue header, and only the</div><div class='add'>+ * GSP writes to the status (receive) queue and its header.</div><div class='add'>+ *</div><div class='add'>+ * This is enforced by the concept of "swapping" the RX pointers.  This is</div><div class='add'>+ * why the 'flags' field must be set to 1.  'rxHdrOff' is how the GSP knows</div><div class='add'>+ * where the where the tail pointer of its status queue.</div><div class='add'>+ *</div><div class='add'>+ * When the driver writes a new RPC to the command queue, it updates writePtr.</div><div class='add'>+ * When it reads a new message from the status queue, it updates readPtr.  In</div><div class='add'>+ * this way, the GSP knows when a new command is in the queue (it polls</div><div class='add'>+ * writePtr) and it knows how much free space is in the status queue (it</div><div class='add'>+ * checks readPtr).  The driver never cares about how much free space is in</div><div class='add'>+ * the status queue.</div><div class='add'>+ *</div><div class='add'>+ * As usual, producers write to the head pointer, and consumers read from the</div><div class='add'>+ * tail pointer.  When head == tail, the queue is empty.</div><div class='add'>+ *</div><div class='add'>+ * So to summarize:</div><div class='add'>+ * command.writePtr = head of command queue</div><div class='add'>+ * command.readPtr = tail of status queue</div><div class='add'>+ * status.writePtr = head of status queue</div><div class='add'>+ * status.readPtr = tail of command queue</div><div class='add'>+ */</div><div class='ctx'> typedef struct</div><div class='ctx'> {</div><div class='ctx'>     NvU32 version;   // queue version</div><div class='hunk'>@@ -38,6 +81,14 @@ typedef struct</div><div class='ctx'>     NvU32 entryOff;  // Offset of entries from start of backing store.</div><div class='ctx'> } msgqTxHeader;</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * msgqRxHeader - RX queue data structure</div><div class='add'>+ * @readPtr: tail index of the other queue</div><div class='add'>+ *</div><div class='add'>+ * Although this is a separate struct, it could easily be merged into</div><div class='add'>+ * msgqTxHeader.  msgqTxHeader.rxHdrOff is simply the offset of readPtr</div><div class='add'>+ * from the beginning of msgqTxHeader.</div><div class='add'>+ */</div><div class='ctx'> typedef struct</div><div class='ctx'> {</div><div class='ctx'>     NvU32 readPtr; // message id of last message read</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h b/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h<br/>index 754c6af42f30..10121218f4d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/g_os_nvoc.h</a></div><div class='hunk'>@@ -38,7 +38,7 @@ typedef struct PACKED_REGISTRY_TABLE</div><div class='ctx'> {</div><div class='ctx'>     NvU32                   size;</div><div class='ctx'>     NvU32                   numEntries;</div><div class='del'>-    PACKED_REGISTRY_ENTRY   entries[0];</div><div class='add'>+    PACKED_REGISTRY_ENTRY   entries[] __counted_by(numEntries);</div><div class='ctx'> } PACKED_REGISTRY_TABLE;</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c<br/>index 50ee9d730066..56dcd25db1ce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_bo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nouveau_bo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_bo.c</a></div><div class='hunk'>@@ -325,8 +325,9 @@ nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,</div><div class='ctx'> 			    (!vmm-&gt;page[i].host || vmm-&gt;page[i].shift &gt; PAGE_SHIFT))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='del'>-			if (pi &lt; 0)</div><div class='del'>-				pi = i;</div><div class='add'>+			/* pick the last one as it will be smallest. */</div><div class='add'>+			pi = i;</div><div class='add'>+</div><div class='ctx'> 			/* Stop once the buffer is larger than the current page size. */</div><div class='ctx'> 			if (*size &gt;= 1ULL &lt;&lt; vmm-&gt;page[i].shift)</div><div class='ctx'> 				break;</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c<br/>index ca762ea55413..5057d976fa57 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_fence.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nouveau_fence.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_fence.c</a></div><div class='hunk'>@@ -62,7 +62,7 @@ nouveau_fence_signal(struct nouveau_fence *fence)</div><div class='ctx'> 	if (test_bit(DMA_FENCE_FLAG_USER_BITS, &amp;fence-&gt;base.flags)) {</div><div class='ctx'> 		struct nouveau_fence_chan *fctx = nouveau_fctx(fence);</div><div class='ctx'> </div><div class='del'>-		if (!--fctx-&gt;notify_ref)</div><div class='add'>+		if (atomic_dec_and_test(&amp;fctx-&gt;notify_ref))</div><div class='ctx'> 			drop = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -103,6 +103,7 @@ nouveau_fence_context_kill(struct nouveau_fence_chan *fctx, int error)</div><div class='ctx'> void</div><div class='ctx'> nouveau_fence_context_del(struct nouveau_fence_chan *fctx)</div><div class='ctx'> {</div><div class='add'>+	cancel_work_sync(&amp;fctx-&gt;allow_block_work);</div><div class='ctx'> 	nouveau_fence_context_kill(fctx, 0);</div><div class='ctx'> 	nvif_event_dtor(&amp;fctx-&gt;event);</div><div class='ctx'> 	fctx-&gt;dead = 1;</div><div class='hunk'>@@ -167,6 +168,18 @@ nouveau_fence_wait_uevent_handler(struct nvif_event *event, void *repv, u32 repc</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void</div><div class='add'>+nouveau_fence_work_allow_block(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct nouveau_fence_chan *fctx = container_of(work, struct nouveau_fence_chan,</div><div class='add'>+						       allow_block_work);</div><div class='add'>+</div><div class='add'>+	if (atomic_read(&amp;fctx-&gt;notify_ref) == 0)</div><div class='add'>+		nvif_event_block(&amp;fctx-&gt;event);</div><div class='add'>+	else</div><div class='add'>+		nvif_event_allow(&amp;fctx-&gt;event);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void</div><div class='ctx'> nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx)</div><div class='ctx'> {</div><div class='hunk'>@@ -178,6 +191,7 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha</div><div class='ctx'> 	} args;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	INIT_WORK(&amp;fctx-&gt;allow_block_work, nouveau_fence_work_allow_block);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;fctx-&gt;flip);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;fctx-&gt;pending);</div><div class='ctx'> 	spin_lock_init(&amp;fctx-&gt;lock);</div><div class='hunk'>@@ -521,15 +535,19 @@ static bool nouveau_fence_enable_signaling(struct dma_fence *f)</div><div class='ctx'> 	struct nouveau_fence *fence = from_fence(f);</div><div class='ctx'> 	struct nouveau_fence_chan *fctx = nouveau_fctx(fence);</div><div class='ctx'> 	bool ret;</div><div class='add'>+	bool do_work;</div><div class='ctx'> </div><div class='del'>-	if (!fctx-&gt;notify_ref++)</div><div class='del'>-		nvif_event_allow(&amp;fctx-&gt;event);</div><div class='add'>+	if (atomic_inc_return(&amp;fctx-&gt;notify_ref) == 0)</div><div class='add'>+		do_work = true;</div><div class='ctx'> </div><div class='ctx'> 	ret = nouveau_fence_no_signaling(f);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		set_bit(DMA_FENCE_FLAG_USER_BITS, &amp;fence-&gt;base.flags);</div><div class='del'>-	else if (!--fctx-&gt;notify_ref)</div><div class='del'>-		nvif_event_block(&amp;fctx-&gt;event);</div><div class='add'>+	else if (atomic_dec_and_test(&amp;fctx-&gt;notify_ref))</div><div class='add'>+		do_work = true;</div><div class='add'>+</div><div class='add'>+	if (do_work)</div><div class='add'>+		schedule_work(&amp;fctx-&gt;allow_block_work);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h<br/>index 64d33ae7f356..28f5cf013b89 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_fence.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nouveau_fence.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_fence.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> #define __NOUVEAU_FENCE_H__</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='ctx'> #include &lt;nvif/event.h&gt;</div><div class='ctx'> </div><div class='ctx'> struct nouveau_drm;</div><div class='hunk'>@@ -45,7 +46,9 @@ struct nouveau_fence_chan {</div><div class='ctx'> 	char name[32];</div><div class='ctx'> </div><div class='ctx'> 	struct nvif_event event;</div><div class='del'>-	int notify_ref, dead, killed;</div><div class='add'>+	struct work_struct allow_block_work;</div><div class='add'>+	atomic_t notify_ref;</div><div class='add'>+	int dead, killed;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct nouveau_fence_priv {</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nouveau_uvmm.c b/drivers/gpu/drm/nouveau/nouveau_uvmm.c<br/>index dae3baf707a0..4f223c972c6a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_uvmm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nouveau_uvmm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_uvmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_uvmm.c</a></div><div class='hunk'>@@ -1347,7 +1347,7 @@ nouveau_uvmm_bind_job_submit(struct nouveau_job *job,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(exec, vme-&gt;flags);</div><div class='add'>+	drm_exec_init(exec, vme-&gt;flags, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(exec) {</div><div class='ctx'> 		ret = bind_lock_validate(job, exec, vme-&gt;num_fences);</div><div class='ctx'> 		drm_exec_retry_on_contention(exec);</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nouveau_vmm.c b/drivers/gpu/drm/nouveau/nouveau_vmm.c<br/>index a6602c012671..3dda885df5b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_vmm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nouveau_vmm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nouveau_vmm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nouveau_vmm.c</a></div><div class='hunk'>@@ -108,6 +108,9 @@ nouveau_vma_new(struct nouveau_bo *nvbo, struct nouveau_vmm *vmm,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = nvif_vmm_get(&amp;vmm-&gt;vmm, PTES, false, mem-&gt;mem.page, 0,</div><div class='ctx'> 				   mem-&gt;mem.size, &amp;tmp);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto done;</div><div class='add'>+</div><div class='ctx'> 		vma-&gt;addr = tmp.addr;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c<br/>index 457ec5db794d..b24eb1e560bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c</a></div><div class='hunk'>@@ -209,7 +209,7 @@ nvkm_disp_dtor(struct nvkm_engine *engine)</div><div class='ctx'> 		nvkm_head_del(&amp;head);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (disp-&gt;func-&gt;dtor)</div><div class='add'>+	if (disp-&gt;func &amp;&amp; disp-&gt;func-&gt;dtor)</div><div class='ctx'> 		disp-&gt;func-&gt;dtor(disp);</div><div class='ctx'> </div><div class='ctx'> 	return data;</div><div class='hunk'>@@ -243,8 +243,10 @@ nvkm_disp_new_(const struct nvkm_disp_func *func, struct nvkm_device *device,</div><div class='ctx'> 	spin_lock_init(&amp;disp-&gt;client.lock);</div><div class='ctx'> </div><div class='ctx'> 	ret = nvkm_engine_ctor(&amp;nvkm_disp, device, type, inst, true, &amp;disp-&gt;engine);</div><div class='del'>-	if (ret)</div><div class='add'>+	if (ret) {</div><div class='add'>+		disp-&gt;func = NULL;</div><div class='ctx'> 		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (func-&gt;super) {</div><div class='ctx'> 		disp-&gt;super.wq = create_singlethread_workqueue("nvkm-disp");</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c<br/>index 298035070b3a..6a0a4d3b8902 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/r535.c</a></div><div class='hunk'>@@ -282,7 +282,7 @@ r535_sor_bl_get(struct nvkm_ior *sor)</div><div class='ctx'> {</div><div class='ctx'> 	struct nvkm_disp *disp = sor-&gt;disp;</div><div class='ctx'> 	NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *ctrl;</div><div class='del'>-	int lvl;</div><div class='add'>+	int ret, lvl;</div><div class='ctx'> </div><div class='ctx'> 	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom,</div><div class='ctx'> 				    NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS,</div><div class='hunk'>@@ -292,9 +292,11 @@ r535_sor_bl_get(struct nvkm_ior *sor)</div><div class='ctx'> </div><div class='ctx'> 	ctrl-&gt;displayId = BIT(sor-&gt;asy.outp-&gt;index);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	lvl = ctrl-&gt;brightness;</div><div class='ctx'> 	nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='hunk'>@@ -649,9 +651,11 @@ r535_conn_new(struct nvkm_disp *disp, u32 id)</div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;displayId = BIT(id);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return (void *)ctrl;</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(conn, &amp;disp-&gt;conns, head) {</div><div class='ctx'> 		if (conn-&gt;index == ctrl-&gt;data[0].index) {</div><div class='hunk'>@@ -686,7 +690,7 @@ r535_outp_acquire(struct nvkm_outp *outp, bool hda)</div><div class='ctx'> 	struct nvkm_disp *disp = outp-&gt;disp;</div><div class='ctx'> 	struct nvkm_ior *ior;</div><div class='ctx'> 	NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS *ctrl;</div><div class='del'>-	int or;</div><div class='add'>+	int ret, or;</div><div class='ctx'> </div><div class='ctx'> 	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom,</div><div class='ctx'> 				    NV0073_CTRL_CMD_DFP_ASSIGN_SOR, sizeof(*ctrl));</div><div class='hunk'>@@ -699,9 +703,11 @@ r535_outp_acquire(struct nvkm_outp *outp, bool hda)</div><div class='ctx'> 	if (hda)</div><div class='ctx'> 		ctrl-&gt;flags |= NVDEF(NV0073_CTRL, DFP_ASSIGN_SOR_FLAGS, AUDIO, OPTIMAL);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (or = 0; or &lt; ARRAY_SIZE(ctrl-&gt;sorAssignListWithTag); or++) {</div><div class='ctx'> 		if (ctrl-&gt;sorAssignListWithTag[or].displayMask &amp; BIT(outp-&gt;index)) {</div><div class='hunk'>@@ -727,6 +733,7 @@ static int</div><div class='ctx'> r535_disp_head_displayid(struct nvkm_disp *disp, int head, u32 *displayid)</div><div class='ctx'> {</div><div class='ctx'> 	NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS *ctrl;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom,</div><div class='ctx'> 				    NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE, sizeof(*ctrl));</div><div class='hunk'>@@ -736,9 +743,11 @@ r535_disp_head_displayid(struct nvkm_disp *disp, int head, u32 *displayid)</div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;head = head;</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	*displayid = ctrl-&gt;displayId;</div><div class='ctx'> 	nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='hunk'>@@ -772,9 +781,11 @@ r535_outp_inherit(struct nvkm_outp *outp)</div><div class='ctx'> 			ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 			ctrl-&gt;displayId = displayid;</div><div class='ctx'> </div><div class='del'>-			ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-			if (IS_ERR(ctrl))</div><div class='add'>+			ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+			if (ret) {</div><div class='add'>+				nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='ctx'> 				return NULL;</div><div class='add'>+			}</div><div class='ctx'> </div><div class='ctx'> 			id = ctrl-&gt;index;</div><div class='ctx'> 			proto = ctrl-&gt;protocol;</div><div class='hunk'>@@ -825,6 +836,7 @@ r535_outp_dfp_get_info(struct nvkm_outp *outp)</div><div class='ctx'> {</div><div class='ctx'> 	NV0073_CTRL_DFP_GET_INFO_PARAMS *ctrl;</div><div class='ctx'> 	struct nvkm_disp *disp = outp-&gt;disp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom, NV0073_CTRL_CMD_DFP_GET_INFO, sizeof(*ctrl));</div><div class='ctx'> 	if (IS_ERR(ctrl))</div><div class='hunk'>@@ -832,9 +844,11 @@ r535_outp_dfp_get_info(struct nvkm_outp *outp)</div><div class='ctx'> </div><div class='ctx'> 	ctrl-&gt;displayId = BIT(outp-&gt;index);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	nvkm_debug(&amp;disp-&gt;engine.subdev, "DFP %08x: flags:%08x flags2:%08x\n",</div><div class='ctx'> 		   ctrl-&gt;displayId, ctrl-&gt;flags, ctrl-&gt;flags2);</div><div class='hunk'>@@ -858,9 +872,11 @@ r535_outp_detect(struct nvkm_outp *outp)</div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;displayMask = BIT(outp-&gt;index);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl-&gt;displayMask &amp; BIT(outp-&gt;index)) {</div><div class='ctx'> 		ret = r535_outp_dfp_get_info(outp);</div><div class='hunk'>@@ -895,6 +911,7 @@ r535_dp_mst_id_get(struct nvkm_outp *outp, u32 *pid)</div><div class='ctx'> {</div><div class='ctx'> 	NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS *ctrl;</div><div class='ctx'> 	struct nvkm_disp *disp = outp-&gt;disp;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom,</div><div class='ctx'> 				    NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID,</div><div class='hunk'>@@ -904,9 +921,11 @@ r535_dp_mst_id_get(struct nvkm_outp *outp, u32 *pid)</div><div class='ctx'> </div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;displayId = BIT(outp-&gt;index);</div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	*pid = ctrl-&gt;displayIdAssigned;</div><div class='ctx'> 	nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='hunk'>@@ -938,38 +957,60 @@ r535_dp_train_target(struct nvkm_outp *outp, u8 target, bool mst, u8 link_nr, u8</div><div class='ctx'> {</div><div class='ctx'> 	struct nvkm_disp *disp = outp-&gt;disp;</div><div class='ctx'> 	NV0073_CTRL_DP_CTRL_PARAMS *ctrl;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom, NV0073_CTRL_CMD_DP_CTRL, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	int ret, retries;</div><div class='add'>+	u32 cmd, data;</div><div class='ctx'> </div><div class='del'>-	ctrl-&gt;subDeviceInstance = 0;</div><div class='del'>-	ctrl-&gt;displayId = BIT(outp-&gt;index);</div><div class='del'>-	ctrl-&gt;cmd = NVDEF(NV0073_CTRL, DP_CMD, SET_LANE_COUNT, TRUE) |</div><div class='del'>-		    NVDEF(NV0073_CTRL, DP_CMD, SET_LINK_BW, TRUE) |</div><div class='del'>-		    NVDEF(NV0073_CTRL, DP_CMD, TRAIN_PHY_REPEATER, YES);</div><div class='del'>-	ctrl-&gt;data = NVVAL(NV0073_CTRL, DP_DATA, SET_LANE_COUNT, link_nr) |</div><div class='del'>-		     NVVAL(NV0073_CTRL, DP_DATA, SET_LINK_BW, link_bw) |</div><div class='del'>-		     NVVAL(NV0073_CTRL, DP_DATA, TARGET, target);</div><div class='add'>+	cmd = NVDEF(NV0073_CTRL, DP_CMD, SET_LANE_COUNT, TRUE) |</div><div class='add'>+	      NVDEF(NV0073_CTRL, DP_CMD, SET_LINK_BW, TRUE) |</div><div class='add'>+	      NVDEF(NV0073_CTRL, DP_CMD, TRAIN_PHY_REPEATER, YES);</div><div class='add'>+	data = NVVAL(NV0073_CTRL, DP_DATA, SET_LANE_COUNT, link_nr) |</div><div class='add'>+	       NVVAL(NV0073_CTRL, DP_DATA, SET_LINK_BW, link_bw) |</div><div class='add'>+	       NVVAL(NV0073_CTRL, DP_DATA, TARGET, target);</div><div class='ctx'> </div><div class='ctx'> 	if (mst)</div><div class='del'>-		ctrl-&gt;cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_FORMAT_MODE, MULTI_STREAM);</div><div class='add'>+		cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_FORMAT_MODE, MULTI_STREAM);</div><div class='ctx'> </div><div class='ctx'> 	if (outp-&gt;dp.dpcd[DPCD_RC02] &amp; DPCD_RC02_ENHANCED_FRAME_CAP)</div><div class='del'>-		ctrl-&gt;cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_ENHANCED_FRAMING, TRUE);</div><div class='add'>+		cmd |= NVDEF(NV0073_CTRL, DP_CMD, SET_ENHANCED_FRAMING, TRUE);</div><div class='ctx'> </div><div class='ctx'> 	if (target == 0 &amp;&amp;</div><div class='ctx'> 	     (outp-&gt;dp.dpcd[DPCD_RC02] &amp; 0x20) &amp;&amp;</div><div class='ctx'> 	    !(outp-&gt;dp.dpcd[DPCD_RC03] &amp; DPCD_RC03_TPS4_SUPPORTED))</div><div class='del'>-	    ctrl-&gt;cmd |= NVDEF(NV0073_CTRL, DP_CMD, POST_LT_ADJ_REQ_GRANTED, YES);</div><div class='add'>+		cmd |= NVDEF(NV0073_CTRL, DP_CMD, POST_LT_ADJ_REQ_GRANTED, YES);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	/* We should retry up to 3 times, but only if GSP asks politely */</div><div class='add'>+	for (retries = 0; retries &lt; 3; ++retries) {</div><div class='add'>+		ctrl = nvkm_gsp_rm_ctrl_get(&amp;disp-&gt;rm.objcom, NV0073_CTRL_CMD_DP_CTRL,</div><div class='add'>+					    sizeof(*ctrl));</div><div class='add'>+		if (IS_ERR(ctrl))</div><div class='add'>+			return PTR_ERR(ctrl);</div><div class='add'>+</div><div class='add'>+		ctrl-&gt;subDeviceInstance = 0;</div><div class='add'>+		ctrl-&gt;displayId = BIT(outp-&gt;index);</div><div class='add'>+		ctrl-&gt;retryTimeMs = 0;</div><div class='add'>+		ctrl-&gt;cmd = cmd;</div><div class='add'>+		ctrl-&gt;data = data;</div><div class='add'>+</div><div class='add'>+		ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+		if (ret == -EAGAIN &amp;&amp; ctrl-&gt;retryTimeMs) {</div><div class='add'>+			/*</div><div class='add'>+			 * Device (likely an eDP panel) isn't ready yet, wait for the time specified</div><div class='add'>+			 * by GSP before retrying again</div><div class='add'>+			 */</div><div class='add'>+			nvkm_debug(&amp;disp-&gt;engine.subdev,</div><div class='add'>+				   "Waiting %dms for GSP LT panel delay before retrying\n",</div><div class='add'>+				   ctrl-&gt;retryTimeMs);</div><div class='add'>+			msleep(ctrl-&gt;retryTimeMs);</div><div class='add'>+			nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		} else {</div><div class='add'>+			/* GSP didn't say to retry, or we were successful */</div><div class='add'>+			if (ctrl-&gt;err)</div><div class='add'>+				ret = -EIO;</div><div class='add'>+			nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ret = ctrl-&gt;err ? -EIO : 0;</div><div class='del'>-	nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1036,9 +1077,11 @@ r535_dp_aux_xfer(struct nvkm_outp *outp, u8 type, u32 addr, u8 *data, u8 *psize)</div><div class='ctx'> 	ctrl-&gt;size = !ctrl-&gt;bAddrOnly ? (size - 1) : 0;</div><div class='ctx'> 	memcpy(ctrl-&gt;data, data, size);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='ctx'> 		return PTR_ERR(ctrl);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	memcpy(data, ctrl-&gt;data, size);</div><div class='ctx'> 	*psize = ctrl-&gt;size;</div><div class='hunk'>@@ -1111,10 +1154,13 @@ r535_tmds_edid_get(struct nvkm_outp *outp, u8 *data, u16 *psize)</div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;displayId = BIT(outp-&gt;index);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	ret = -E2BIG;</div><div class='ctx'> 	if (ctrl-&gt;bufferSize &lt;= *psize) {</div><div class='ctx'> 		memcpy(data, ctrl-&gt;edidBuffer, ctrl-&gt;bufferSize);</div><div class='ctx'> 		*psize = ctrl-&gt;bufferSize;</div><div class='hunk'>@@ -1153,9 +1199,11 @@ r535_outp_new(struct nvkm_disp *disp, u32 id)</div><div class='ctx'> 	ctrl-&gt;subDeviceInstance = 0;</div><div class='ctx'> 	ctrl-&gt;displayId = BIT(id);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (IS_ERR(ctrl))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (ret) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	switch (ctrl-&gt;type) {</div><div class='ctx'> 	case NV0073_CTRL_SPECIFIC_OR_TYPE_NONE:</div><div class='hunk'>@@ -1229,9 +1277,11 @@ r535_outp_new(struct nvkm_disp *disp, u32 id)</div><div class='ctx'> </div><div class='ctx'> 		ctrl-&gt;sorIndex = ~0;</div><div class='ctx'> </div><div class='del'>-		ctrl = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, ctrl, sizeof(*ctrl));</div><div class='del'>-		if (IS_ERR(ctrl))</div><div class='del'>-			return PTR_ERR(ctrl);</div><div class='add'>+		ret = nvkm_gsp_rm_ctrl_push(&amp;disp-&gt;rm.objcom, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+		if (ret) {</div><div class='add'>+			nvkm_gsp_rm_ctrl_done(&amp;disp-&gt;rm.objcom, ctrl);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		switch (NVVAL_GET(ctrl-&gt;maxLinkRate, NV0073_CTRL_CMD, DP_GET_CAPS, MAX_LINK_RATE)) {</div><div class='ctx'> 		case NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62:</div><div class='hunk'>@@ -1465,8 +1515,6 @@ r535_disp_oneinit(struct nvkm_disp *disp)</div><div class='ctx'> 				bool nvhg = acpi_check_dsm(handle, &amp;NVHG_DSM_GUID, NVHG_DSM_REV,</div><div class='ctx'> 						           1ULL &lt;&lt; 0x00000014);</div><div class='ctx'> </div><div class='del'>-				printk(KERN_ERR "bl: nbci:%d nvhg:%d\n", nbci, nvhg);</div><div class='del'>-</div><div class='ctx'> 				if (nbci || nvhg) {</div><div class='ctx'> 					union acpi_object argv4 = {</div><div class='ctx'> 						.buffer.type    = ACPI_TYPE_BUFFER,</div><div class='hunk'>@@ -1479,9 +1527,6 @@ r535_disp_oneinit(struct nvkm_disp *disp)</div><div class='ctx'> 					if (!obj) {</div><div class='ctx'> 						acpi_handle_info(handle, "failed to evaluate _DSM\n");</div><div class='ctx'> 					} else {</div><div class='del'>-						printk(KERN_ERR "bl: obj type %d\n", obj-&gt;type);</div><div class='del'>-						printk(KERN_ERR "bl: obj len %d\n", obj-&gt;package.count);</div><div class='del'>-</div><div class='ctx'> 						for (int i = 0; i &lt; obj-&gt;package.count; i++) {</div><div class='ctx'> 							union acpi_object *elt = &amp;obj-&gt;package.elements[i];</div><div class='ctx'> 							u32 size;</div><div class='hunk'>@@ -1491,12 +1536,10 @@ r535_disp_oneinit(struct nvkm_disp *disp)</div><div class='ctx'> 							else</div><div class='ctx'> 								size = 4;</div><div class='ctx'> </div><div class='del'>-							printk(KERN_ERR "elt %03d: type %d size %d\n", i, elt-&gt;type, size);</div><div class='ctx'> 							memcpy(&amp;ctrl-&gt;backLightData[ctrl-&gt;backLightDataSize], &amp;elt-&gt;integer.value, size);</div><div class='ctx'> 							ctrl-&gt;backLightDataSize += size;</div><div class='ctx'> 						}</div><div class='ctx'> </div><div class='del'>-						printk(KERN_ERR "bl: data size %d\n", ctrl-&gt;backLightDataSize);</div><div class='ctx'> 						ctrl-&gt;status = 0;</div><div class='ctx'> 						ACPI_FREE(obj);</div><div class='ctx'> 					}</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c<br/>index e4279f1772a1..377d0e0cef84 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c</a></div><div class='hunk'>@@ -385,7 +385,7 @@ nvkm_uoutp_mthd_inherit(struct nvkm_outp *outp, void *argv, u32 argc)</div><div class='ctx'> </div><div class='ctx'> 	/* Ensure an ior is hooked up to this outp already */</div><div class='ctx'> 	ior = outp-&gt;func-&gt;inherit(outp);</div><div class='del'>-	if (!ior)</div><div class='add'>+	if (!ior || !ior-&gt;arm.head)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	/* With iors, there will be a separate output path for each type of connector - and all of</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c<br/>index c8ce7ff18713..e74493a4569e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c</a></div><div class='hunk'>@@ -550,6 +550,10 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)</div><div class='ctx'> 		struct nvkm_engn *engn = list_first_entry(&amp;runl-&gt;engns, typeof(*engn), head);</div><div class='ctx'> </div><div class='ctx'> 		runl-&gt;nonstall.vector = engn-&gt;func-&gt;nonstall(engn);</div><div class='add'>+</div><div class='add'>+		/* if no nonstall vector just keep going */</div><div class='add'>+		if (runl-&gt;nonstall.vector == -1)</div><div class='add'>+			continue;</div><div class='ctx'> 		if (runl-&gt;nonstall.vector &lt; 0) {</div><div class='ctx'> 			RUNL_ERROR(runl, "nonstall %d", runl-&gt;nonstall.vector);</div><div class='ctx'> 			return runl-&gt;nonstall.vector;</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c<br/>index d088e636edc3..3454c7d29502 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c</a></div><div class='hunk'>@@ -242,6 +242,7 @@ r535_chan_id_put(struct nvkm_chan *chan)</div><div class='ctx'> 				nvkm_memory_unref(&amp;userd-&gt;mem);</div><div class='ctx'> 				nvkm_chid_put(runl-&gt;chid, userd-&gt;chid, &amp;chan-&gt;cgrp-&gt;lock);</div><div class='ctx'> 				list_del(&amp;userd-&gt;head);</div><div class='add'>+				kfree(userd);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='hunk'>@@ -350,7 +351,7 @@ r535_engn_nonstall(struct nvkm_engn *engn)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = nvkm_gsp_intr_nonstall(subdev-&gt;device-&gt;gsp, subdev-&gt;type, subdev-&gt;inst);</div><div class='del'>-	WARN_ON(ret &lt; 0);</div><div class='add'>+	WARN_ON(ret == -ENOENT);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c<br/>index 04bceaa28a19..da1bebb896f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.c</a></div><div class='hunk'>@@ -25,12 +25,8 @@ int</div><div class='ctx'> nvkm_gsp_intr_nonstall(struct nvkm_gsp *gsp, enum nvkm_subdev_type type, int inst)</div><div class='ctx'> {</div><div class='ctx'> 	for (int i = 0; i &lt; gsp-&gt;intr_nr; i++) {</div><div class='del'>-		if (gsp-&gt;intr[i].type == type &amp;&amp; gsp-&gt;intr[i].inst == inst) {</div><div class='del'>-			if (gsp-&gt;intr[i].nonstall != ~0)</div><div class='del'>-				return gsp-&gt;intr[i].nonstall;</div><div class='del'>-</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+		if (gsp-&gt;intr[i].type == type &amp;&amp; gsp-&gt;intr[i].inst == inst)</div><div class='add'>+			return gsp-&gt;intr[i].nonstall;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return -ENOENT;</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c<br/>index dc44f5c7833f..9ee58e2a0eb2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c</a></div><div class='hunk'>@@ -70,6 +70,20 @@ struct r535_gsp_msg {</div><div class='ctx'> </div><div class='ctx'> #define GSP_MSG_HDR_SIZE offsetof(struct r535_gsp_msg, data)</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+r535_rpc_status_to_errno(uint32_t rpc_status)</div><div class='add'>+{</div><div class='add'>+	switch (rpc_status) {</div><div class='add'>+	case 0x55: /* NV_ERR_NOT_READY */</div><div class='add'>+	case 0x66: /* NV_ERR_TIMEOUT_RETRY */</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	case 0x51: /* NV_ERR_NO_MEMORY */</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void *</div><div class='ctx'> r535_gsp_msgq_wait(struct nvkm_gsp *gsp, u32 repc, u32 *prepc, int *ptime)</div><div class='ctx'> {</div><div class='hunk'>@@ -298,7 +312,8 @@ retry:</div><div class='ctx'> 		struct nvkm_gsp_msgq_ntfy *ntfy = &amp;gsp-&gt;msgq.ntfy[i];</div><div class='ctx'> </div><div class='ctx'> 		if (ntfy-&gt;fn == msg-&gt;function) {</div><div class='del'>-			ntfy-&gt;func(ntfy-&gt;priv, ntfy-&gt;fn, msg-&gt;data, msg-&gt;length - sizeof(*msg));</div><div class='add'>+			if (ntfy-&gt;func)</div><div class='add'>+				ntfy-&gt;func(ntfy-&gt;priv, ntfy-&gt;fn, msg-&gt;data, msg-&gt;length - sizeof(*msg));</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -365,10 +380,8 @@ r535_gsp_rpc_send(struct nvkm_gsp *gsp, void *argv, bool wait, u32 repc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = r535_gsp_cmdq_push(gsp, rpc);</div><div class='del'>-	if (ret) {</div><div class='del'>-		mutex_unlock(&amp;gsp-&gt;cmdq.mutex);</div><div class='add'>+	if (ret)</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (wait) {</div><div class='ctx'> 		msg = r535_gsp_msg_recv(gsp, fn, repc);</div><div class='hunk'>@@ -585,14 +598,14 @@ r535_gsp_rpc_rm_alloc_push(struct nvkm_gsp_object *object, void *argv, u32 repc)</div><div class='ctx'> 		return rpc;</div><div class='ctx'> </div><div class='ctx'> 	if (rpc-&gt;status) {</div><div class='del'>-		nvkm_error(&amp;gsp-&gt;subdev, "RM_ALLOC: 0x%x\n", rpc-&gt;status);</div><div class='del'>-		ret = ERR_PTR(-EINVAL);</div><div class='add'>+		ret = ERR_PTR(r535_rpc_status_to_errno(rpc-&gt;status));</div><div class='add'>+		if (PTR_ERR(ret) != -EAGAIN)</div><div class='add'>+			nvkm_error(&amp;gsp-&gt;subdev, "RM_ALLOC: 0x%x\n", rpc-&gt;status);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = repc ? rpc-&gt;params : NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (IS_ERR_OR_NULL(ret))</div><div class='del'>-		nvkm_gsp_rpc_done(gsp, rpc);</div><div class='add'>+	nvkm_gsp_rpc_done(gsp, rpc);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -625,29 +638,34 @@ r535_gsp_rpc_rm_ctrl_done(struct nvkm_gsp_object *object, void *repv)</div><div class='ctx'> {</div><div class='ctx'> 	rpc_gsp_rm_control_v03_00 *rpc = container_of(repv, typeof(*rpc), params);</div><div class='ctx'> </div><div class='add'>+	if (!repv)</div><div class='add'>+		return;</div><div class='ctx'> 	nvkm_gsp_rpc_done(object-&gt;client-&gt;gsp, rpc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void *</div><div class='del'>-r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void *argv, u32 repc)</div><div class='add'>+static int</div><div class='add'>+r535_gsp_rpc_rm_ctrl_push(struct nvkm_gsp_object *object, void **argv, u32 repc)</div><div class='ctx'> {</div><div class='del'>-	rpc_gsp_rm_control_v03_00 *rpc = container_of(argv, typeof(*rpc), params);</div><div class='add'>+	rpc_gsp_rm_control_v03_00 *rpc = container_of((*argv), typeof(*rpc), params);</div><div class='ctx'> 	struct nvkm_gsp *gsp = object-&gt;client-&gt;gsp;</div><div class='del'>-	void *ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	rpc = nvkm_gsp_rpc_push(gsp, rpc, true, repc);</div><div class='del'>-	if (IS_ERR_OR_NULL(rpc))</div><div class='del'>-		return rpc;</div><div class='add'>+	if (IS_ERR_OR_NULL(rpc)) {</div><div class='add'>+		*argv = NULL;</div><div class='add'>+		return PTR_ERR(rpc);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (rpc-&gt;status) {</div><div class='del'>-		nvkm_error(&amp;gsp-&gt;subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",</div><div class='del'>-			   object-&gt;client-&gt;object.handle, object-&gt;handle, rpc-&gt;cmd, rpc-&gt;status);</div><div class='del'>-		ret = ERR_PTR(-EINVAL);</div><div class='del'>-	} else {</div><div class='del'>-		ret = repc ? rpc-&gt;params : NULL;</div><div class='add'>+		ret = r535_rpc_status_to_errno(rpc-&gt;status);</div><div class='add'>+		if (ret != -EAGAIN)</div><div class='add'>+			nvkm_error(&amp;gsp-&gt;subdev, "cli:0x%08x obj:0x%08x ctrl cmd:0x%08x failed: 0x%08x\n",</div><div class='add'>+				   object-&gt;client-&gt;object.handle, object-&gt;handle, rpc-&gt;cmd, rpc-&gt;status);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (IS_ERR_OR_NULL(ret))</div><div class='add'>+	if (repc)</div><div class='add'>+		*argv = rpc-&gt;params;</div><div class='add'>+	else</div><div class='ctx'> 		nvkm_gsp_rpc_done(gsp, rpc);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -845,9 +863,11 @@ r535_gsp_intr_get_table(struct nvkm_gsp *gsp)</div><div class='ctx'> 	if (IS_ERR(ctrl))</div><div class='ctx'> 		return PTR_ERR(ctrl);</div><div class='ctx'> </div><div class='del'>-	ctrl = nvkm_gsp_rm_ctrl_push(&amp;gsp-&gt;internal.device.subdevice, ctrl, sizeof(*ctrl));</div><div class='del'>-	if (WARN_ON(IS_ERR(ctrl)))</div><div class='del'>-		return PTR_ERR(ctrl);</div><div class='add'>+	ret = nvkm_gsp_rm_ctrl_push(&amp;gsp-&gt;internal.device.subdevice, &amp;ctrl, sizeof(*ctrl));</div><div class='add'>+	if (WARN_ON(ret)) {</div><div class='add'>+		nvkm_gsp_rm_ctrl_done(&amp;gsp-&gt;internal.device.subdevice, ctrl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (unsigned i = 0; i &lt; ctrl-&gt;tableLen; i++) {</div><div class='ctx'> 		enum nvkm_subdev_type type;</div><div class='hunk'>@@ -1048,7 +1068,7 @@ r535_gsp_rpc_set_registry(struct nvkm_gsp *gsp)</div><div class='ctx'> 	char *strings;</div><div class='ctx'> 	int str_offset;</div><div class='ctx'> 	int i;</div><div class='del'>-	size_t rpc_size = sizeof(*rpc) + sizeof(rpc-&gt;entries[0]) * NV_GSP_REG_NUM_ENTRIES;</div><div class='add'>+	size_t rpc_size = struct_size(rpc, entries, NV_GSP_REG_NUM_ENTRIES);</div><div class='ctx'> </div><div class='ctx'> 	/* add strings + null terminator */</div><div class='ctx'> 	for (i = 0; i &lt; NV_GSP_REG_NUM_ENTRIES; i++)</div><div class='hunk'>@@ -1101,16 +1121,12 @@ r535_gsp_acpi_caps(acpi_handle handle, CAPS_METHOD_DATA *caps)</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	printk(KERN_ERR "nvop: obj type %d\n", obj-&gt;type);</div><div class='del'>-	printk(KERN_ERR "nvop: obj len %d\n", obj-&gt;buffer.length);</div><div class='del'>-</div><div class='ctx'> 	if (WARN_ON(obj-&gt;type != ACPI_TYPE_BUFFER) ||</div><div class='ctx'> 	    WARN_ON(obj-&gt;buffer.length != 4))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	caps-&gt;status = 0;</div><div class='ctx'> 	caps-&gt;optimusCaps = *(u32 *)obj-&gt;buffer.pointer;</div><div class='del'>-	printk(KERN_ERR "nvop: caps %08x\n", caps-&gt;optimusCaps);</div><div class='ctx'> </div><div class='ctx'> 	ACPI_FREE(obj);</div><div class='ctx'> </div><div class='hunk'>@@ -1137,9 +1153,6 @@ r535_gsp_acpi_jt(acpi_handle handle, JT_METHOD_DATA *jt)</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	printk(KERN_ERR "jt: obj type %d\n", obj-&gt;type);</div><div class='del'>-	printk(KERN_ERR "jt: obj len %d\n", obj-&gt;buffer.length);</div><div class='del'>-</div><div class='ctx'> 	if (WARN_ON(obj-&gt;type != ACPI_TYPE_BUFFER) ||</div><div class='ctx'> 	    WARN_ON(obj-&gt;buffer.length != 4))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1148,7 +1161,6 @@ r535_gsp_acpi_jt(acpi_handle handle, JT_METHOD_DATA *jt)</div><div class='ctx'> 	jt-&gt;jtCaps = *(u32 *)obj-&gt;buffer.pointer;</div><div class='ctx'> 	jt-&gt;jtRevId = (jt-&gt;jtCaps &amp; 0xfff00000) &gt;&gt; 20;</div><div class='ctx'> 	jt-&gt;bSBIOSCaps = 0;</div><div class='del'>-	printk(KERN_ERR "jt: caps %08x rev:%04x\n", jt-&gt;jtCaps, jt-&gt;jtRevId);</div><div class='ctx'> </div><div class='ctx'> 	ACPI_FREE(obj);</div><div class='ctx'> </div><div class='hunk'>@@ -1159,6 +1171,8 @@ static void</div><div class='ctx'> r535_gsp_acpi_mux_id(acpi_handle handle, u32 id, MUX_METHOD_DATA_ELEMENT *mode,</div><div class='ctx'> 						 MUX_METHOD_DATA_ELEMENT *part)</div><div class='ctx'> {</div><div class='add'>+	union acpi_object mux_arg = { ACPI_TYPE_INTEGER };</div><div class='add'>+	struct acpi_object_list input = { 1, &amp;mux_arg };</div><div class='ctx'> 	acpi_handle iter = NULL, handle_mux = NULL;</div><div class='ctx'> 	acpi_status status;</div><div class='ctx'> 	unsigned long long value;</div><div class='hunk'>@@ -1181,14 +1195,18 @@ r535_gsp_acpi_mux_id(acpi_handle handle, u32 id, MUX_METHOD_DATA_ELEMENT *mode,</div><div class='ctx'> 	if (!handle_mux)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(handle_mux, "MXDM", NULL, &amp;value);</div><div class='add'>+	/* I -think- 0 means "acquire" according to nvidia's driver source */</div><div class='add'>+	input.pointer-&gt;integer.type = ACPI_TYPE_INTEGER;</div><div class='add'>+	input.pointer-&gt;integer.value = 0;</div><div class='add'>+</div><div class='add'>+	status = acpi_evaluate_integer(handle_mux, "MXDM", &amp;input, &amp;value);</div><div class='ctx'> 	if (ACPI_SUCCESS(status)) {</div><div class='ctx'> 		mode-&gt;acpiId = id;</div><div class='ctx'> 		mode-&gt;mode   = value;</div><div class='ctx'> 		mode-&gt;status = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = acpi_evaluate_integer(handle_mux, "MXDS", NULL, &amp;value);</div><div class='add'>+	status = acpi_evaluate_integer(handle_mux, "MXDS", &amp;input, &amp;value);</div><div class='ctx'> 	if (ACPI_SUCCESS(status)) {</div><div class='ctx'> 		part-&gt;acpiId = id;</div><div class='ctx'> 		part-&gt;mode   = value;</div><div class='hunk'>@@ -1234,8 +1252,8 @@ r535_gsp_acpi_dod(acpi_handle handle, DOD_METHOD_DATA *dod)</div><div class='ctx'> 		dod-&gt;acpiIdListLen += sizeof(dod-&gt;acpiIdList[0]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	printk(KERN_ERR "_DOD: ok! len:%d\n", dod-&gt;acpiIdListLen);</div><div class='ctx'> 	dod-&gt;status = 0;</div><div class='add'>+	kfree(output.pointer);</div><div class='ctx'> }</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -1379,6 +1397,13 @@ r535_gsp_msg_post_event(void *priv, u32 fn, void *repv, u32 repc)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * r535_gsp_msg_run_cpu_sequencer() -- process I/O commands from the GSP</div><div class='add'>+ *</div><div class='add'>+ * The GSP sequencer is a list of I/O commands that the GSP can send to</div><div class='add'>+ * the driver to perform for various purposes.  The most common usage is to</div><div class='add'>+ * perform a special mid-initialization reset.</div><div class='add'>+ */</div><div class='ctx'> static int</div><div class='ctx'> r535_gsp_msg_run_cpu_sequencer(void *priv, u32 fn, void *repv, u32 repc)</div><div class='ctx'> {</div><div class='hunk'>@@ -1718,6 +1743,23 @@ r535_gsp_libos_id8(const char *name)</div><div class='ctx'> 	return id;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * create_pte_array() - creates a PTE array of a physically contiguous buffer</div><div class='add'>+ * @ptes: pointer to the array</div><div class='add'>+ * @addr: base address of physically contiguous buffer (GSP_PAGE_SIZE aligned)</div><div class='add'>+ * @size: size of the buffer</div><div class='add'>+ *</div><div class='add'>+ * GSP-RM sometimes expects physically-contiguous buffers to have an array of</div><div class='add'>+ * "PTEs" for each page in that buffer.  Although in theory that allows for</div><div class='add'>+ * the buffer to be physically discontiguous, GSP-RM does not currently</div><div class='add'>+ * support that.</div><div class='add'>+ *</div><div class='add'>+ * In this case, the PTEs are DMA addresses of each page of the buffer.  Since</div><div class='add'>+ * the buffer is physically contiguous, calculating all the PTEs is simple</div><div class='add'>+ * math.</div><div class='add'>+ *</div><div class='add'>+ * See memdescGetPhysAddrsForGpu()</div><div class='add'>+ */</div><div class='ctx'> static void create_pte_array(u64 *ptes, dma_addr_t addr, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int num_pages = DIV_ROUND_UP_ULL(size, GSP_PAGE_SIZE);</div><div class='hunk'>@@ -1727,6 +1769,35 @@ static void create_pte_array(u64 *ptes, dma_addr_t addr, size_t size)</div><div class='ctx'> 		ptes[i] = (u64)addr + (i &lt;&lt; GSP_PAGE_SHIFT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * r535_gsp_libos_init() -- create the libos arguments structure</div><div class='add'>+ *</div><div class='add'>+ * The logging buffers are byte queues that contain encoded printf-like</div><div class='add'>+ * messages from GSP-RM.  They need to be decoded by a special application</div><div class='add'>+ * that can parse the buffers.</div><div class='add'>+ *</div><div class='add'>+ * The 'loginit' buffer contains logs from early GSP-RM init and</div><div class='add'>+ * exception dumps.  The 'logrm' buffer contains the subsequent logs. Both are</div><div class='add'>+ * written to directly by GSP-RM and can be any multiple of GSP_PAGE_SIZE.</div><div class='add'>+ *</div><div class='add'>+ * The physical address map for the log buffer is stored in the buffer</div><div class='add'>+ * itself, starting with offset 1. Offset 0 contains the "put" pointer.</div><div class='add'>+ *</div><div class='add'>+ * The GSP only understands 4K pages (GSP_PAGE_SIZE), so even if the kernel is</div><div class='add'>+ * configured for a larger page size (e.g. 64K pages), we need to give</div><div class='add'>+ * the GSP an array of 4K pages. Fortunately, since the buffer is</div><div class='add'>+ * physically contiguous, it's simple math to calculate the addresses.</div><div class='add'>+ *</div><div class='add'>+ * The buffers must be a multiple of GSP_PAGE_SIZE.  GSP-RM also currently</div><div class='add'>+ * ignores the @kind field for LOGINIT, LOGINTR, and LOGRM, but expects the</div><div class='add'>+ * buffers to be physically contiguous anyway.</div><div class='add'>+ *</div><div class='add'>+ * The memory allocated for the arguments must remain until the GSP sends the</div><div class='add'>+ * init_done RPC.</div><div class='add'>+ *</div><div class='add'>+ * See _kgspInitLibosLoggingStructures (allocates memory for buffers)</div><div class='add'>+ * See kgspSetupLibosInitArgs_IMPL (creates pLibosInitArgs[] array)</div><div class='add'>+ */</div><div class='ctx'> static int</div><div class='ctx'> r535_gsp_libos_init(struct nvkm_gsp *gsp)</div><div class='ctx'> {</div><div class='hunk'>@@ -1837,6 +1908,35 @@ nvkm_gsp_radix3_dtor(struct nvkm_gsp *gsp, struct nvkm_gsp_radix3 *rx3)</div><div class='ctx'> 		nvkm_gsp_mem_dtor(gsp, &amp;rx3-&gt;mem[i]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * nvkm_gsp_radix3_sg - build a radix3 table from a S/G list</div><div class='add'>+ *</div><div class='add'>+ * The GSP uses a three-level page table, called radix3, to map the firmware.</div><div class='add'>+ * Each 64-bit "pointer" in the table is either the bus address of an entry in</div><div class='add'>+ * the next table (for levels 0 and 1) or the bus address of the next page in</div><div class='add'>+ * the GSP firmware image itself.</div><div class='add'>+ *</div><div class='add'>+ * Level 0 contains a single entry in one page that points to the first page</div><div class='add'>+ * of level 1.</div><div class='add'>+ *</div><div class='add'>+ * Level 1, since it's also only one page in size, contains up to 512 entries,</div><div class='add'>+ * one for each page in Level 2.</div><div class='add'>+ *</div><div class='add'>+ * Level 2 can be up to 512 pages in size, and each of those entries points to</div><div class='add'>+ * the next page of the firmware image.  Since there can be up to 512*512</div><div class='add'>+ * pages, that limits the size of the firmware to 512*512*GSP_PAGE_SIZE = 1GB.</div><div class='add'>+ *</div><div class='add'>+ * Internally, the GSP has its window into system memory, but the base</div><div class='add'>+ * physical address of the aperture is not 0.  In fact, it varies depending on</div><div class='add'>+ * the GPU architecture.  Since the GPU is a PCI device, this window is</div><div class='add'>+ * accessed via DMA and is therefore bound by IOMMU translation.  The end</div><div class='add'>+ * result is that GSP-RM must translate the bus addresses in the table to GSP</div><div class='add'>+ * physical addresses.  All this should happen transparently.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 on success, or negative error code</div><div class='add'>+ *</div><div class='add'>+ * See kgspCreateRadix3_IMPL</div><div class='add'>+ */</div><div class='ctx'> static int</div><div class='ctx'> nvkm_gsp_radix3_sg(struct nvkm_device *device, struct sg_table *sgt, u64 size,</div><div class='ctx'> 		   struct nvkm_gsp_radix3 *rx3)</div><div class='hunk'>@@ -2106,7 +2206,9 @@ r535_gsp_oneinit(struct nvkm_gsp *gsp)</div><div class='ctx'> 	r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_MMU_FAULT_QUEUED,</div><div class='ctx'> 			      r535_gsp_msg_mmu_fault_queued, gsp);</div><div class='ctx'> 	r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_OS_ERROR_LOG, r535_gsp_msg_os_error_log, gsp);</div><div class='del'>-</div><div class='add'>+	r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_PERF_BRIDGELESS_INFO_UPDATE, NULL, NULL);</div><div class='add'>+	r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT, NULL, NULL);</div><div class='add'>+	r535_gsp_msg_ntfy_add(gsp, NV_VGPU_MSG_EVENT_GSP_SEND_USER_SHARED_DATA, NULL, NULL);</div><div class='ctx'> 	ret = r535_gsp_rm_boot_ctor(gsp);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c<br/>index 1b811d6972a1..201022ae9214 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c</a></div><div class='hunk'>@@ -49,14 +49,14 @@</div><div class='ctx'> #include &lt;subdev/mmu.h&gt;</div><div class='ctx'> </div><div class='ctx'> struct gk20a_instobj {</div><div class='del'>-	struct nvkm_memory memory;</div><div class='add'>+	struct nvkm_instobj base;</div><div class='ctx'> 	struct nvkm_mm_node *mn;</div><div class='ctx'> 	struct gk20a_instmem *imem;</div><div class='ctx'> </div><div class='ctx'> 	/* CPU mapping */</div><div class='ctx'> 	u32 *vaddr;</div><div class='ctx'> };</div><div class='del'>-#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)</div><div class='add'>+#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, base.memory)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Used for objects allocated using the DMA API</div><div class='hunk'>@@ -148,7 +148,7 @@ gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj)</div><div class='ctx'> 	list_del(&amp;obj-&gt;vaddr_node);</div><div class='ctx'> 	vunmap(obj-&gt;base.vaddr);</div><div class='ctx'> 	obj-&gt;base.vaddr = NULL;</div><div class='del'>-	imem-&gt;vaddr_use -= nvkm_memory_size(&amp;obj-&gt;base.memory);</div><div class='add'>+	imem-&gt;vaddr_use -= nvkm_memory_size(&amp;obj-&gt;base.base.memory);</div><div class='ctx'> 	nvkm_debug(&amp;imem-&gt;base.subdev, "vaddr used: %x/%x\n", imem-&gt;vaddr_use,</div><div class='ctx'> 		   imem-&gt;vaddr_max);</div><div class='ctx'> }</div><div class='hunk'>@@ -283,7 +283,7 @@ gk20a_instobj_map(struct nvkm_memory *memory, u64 offset, struct nvkm_vmm *vmm,</div><div class='ctx'> {</div><div class='ctx'> 	struct gk20a_instobj *node = gk20a_instobj(memory);</div><div class='ctx'> 	struct nvkm_vmm_map map = {</div><div class='del'>-		.memory = &amp;node-&gt;memory,</div><div class='add'>+		.memory = &amp;node-&gt;base.memory,</div><div class='ctx'> 		.offset = offset,</div><div class='ctx'> 		.mem = node-&gt;mn,</div><div class='ctx'> 	};</div><div class='hunk'>@@ -391,8 +391,8 @@ gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align,</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	*_node = &amp;node-&gt;base;</div><div class='ctx'> </div><div class='del'>-	nvkm_memory_ctor(&amp;gk20a_instobj_func_dma, &amp;node-&gt;base.memory);</div><div class='del'>-	node-&gt;base.memory.ptrs = &amp;gk20a_instobj_ptrs;</div><div class='add'>+	nvkm_memory_ctor(&amp;gk20a_instobj_func_dma, &amp;node-&gt;base.base.memory);</div><div class='add'>+	node-&gt;base.base.memory.ptrs = &amp;gk20a_instobj_ptrs;</div><div class='ctx'> </div><div class='ctx'> 	node-&gt;base.vaddr = dma_alloc_attrs(dev, npages &lt;&lt; PAGE_SHIFT,</div><div class='ctx'> 					   &amp;node-&gt;handle, GFP_KERNEL,</div><div class='hunk'>@@ -438,8 +438,8 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align,</div><div class='ctx'> 	*_node = &amp;node-&gt;base;</div><div class='ctx'> 	node-&gt;dma_addrs = (void *)(node-&gt;pages + npages);</div><div class='ctx'> </div><div class='del'>-	nvkm_memory_ctor(&amp;gk20a_instobj_func_iommu, &amp;node-&gt;base.memory);</div><div class='del'>-	node-&gt;base.memory.ptrs = &amp;gk20a_instobj_ptrs;</div><div class='add'>+	nvkm_memory_ctor(&amp;gk20a_instobj_func_iommu, &amp;node-&gt;base.base.memory);</div><div class='add'>+	node-&gt;base.base.memory.ptrs = &amp;gk20a_instobj_ptrs;</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate backing memory */</div><div class='ctx'> 	for (i = 0; i &lt; npages; i++) {</div><div class='hunk'>@@ -533,7 +533,7 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,</div><div class='ctx'> 	else</div><div class='ctx'> 		ret = gk20a_instobj_ctor_dma(imem, size &gt;&gt; PAGE_SHIFT,</div><div class='ctx'> 					     align, &amp;node);</div><div class='del'>-	*pmemory = node ? &amp;node-&gt;memory : NULL;</div><div class='add'>+	*pmemory = node ? &amp;node-&gt;base.memory : NULL;</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c<br/>index e7e8fdf3adab..29682722b0b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c</a></div><div class='hunk'>@@ -28,19 +28,14 @@ static void</div><div class='ctx'> gp10b_ltc_init(struct nvkm_ltc *ltc)</div><div class='ctx'> {</div><div class='ctx'> 	struct nvkm_device *device = ltc-&gt;subdev.device;</div><div class='del'>-	struct iommu_fwspec *spec;</div><div class='add'>+	u32 sid;</div><div class='ctx'> </div><div class='ctx'> 	nvkm_wr32(device, 0x17e27c, ltc-&gt;ltc_nr);</div><div class='ctx'> 	nvkm_wr32(device, 0x17e000, ltc-&gt;ltc_nr);</div><div class='ctx'> 	nvkm_wr32(device, 0x100800, ltc-&gt;ltc_nr);</div><div class='ctx'> </div><div class='del'>-	spec = dev_iommu_fwspec_get(device-&gt;dev);</div><div class='del'>-	if (spec) {</div><div class='del'>-		u32 sid = spec-&gt;ids[0] &amp; 0xffff;</div><div class='del'>-</div><div class='del'>-		/* stream ID */</div><div class='add'>+	if (tegra_dev_iommu_get_stream_id(device-&gt;dev, &amp;sid))</div><div class='ctx'> 		nvkm_wr32(device, 0x160000, sid &lt;&lt; 2);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct nvkm_ltc_func</div><div class='head'>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c<br/>index e34bc6076401..8379e72d77ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c</a></div><div class='hunk'>@@ -31,7 +31,7 @@ tu102_vmm_flush(struct nvkm_vmm *vmm, int depth)</div><div class='ctx'> </div><div class='ctx'> 	type |= 0x00000001; /* PAGE_ALL */</div><div class='ctx'> 	if (atomic_read(&amp;vmm-&gt;engref[NVKM_SUBDEV_BAR]))</div><div class='del'>-		type |= 0x00000004; /* HUB_ONLY */</div><div class='add'>+		type |= 0x00000006; /* HUB_ONLY | ALL PDB (hack) */</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;vmm-&gt;mmu-&gt;mutex);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c<br/>index be8f48e3c1db..c4c0f08e9202 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c</a></div><div class='hunk'>@@ -1764,6 +1764,7 @@ static const struct panel_desc starry_qfh032011_53g_desc = {</div><div class='ctx'> 	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |</div><div class='ctx'> 		      MIPI_DSI_MODE_LPM,</div><div class='ctx'> 	.init_cmds = starry_qfh032011_53g_init_cmd,</div><div class='add'>+	.lp11_before_reset = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct drm_display_mode starry_himax83102_j02_default_mode = {</div><div class='head'>diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c b/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c<br/>index 32ebedadbcdc..9d87cc1a357e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c</a></div><div class='hunk'>@@ -326,7 +326,7 @@ static const struct drm_display_mode ltk050h3148w_mode = {</div><div class='ctx'> static const struct ltk050h3146w_desc ltk050h3148w_data = {</div><div class='ctx'> 	.mode = &amp;ltk050h3148w_mode,</div><div class='ctx'> 	.init = ltk050h3148w_init_sequence,</div><div class='del'>-	.mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE,</div><div class='add'>+	.mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_BURST,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int ltk050h3146w_init_sequence(struct ltk050h3146w *ctx)</div><div class='head'>diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36523.c b/drivers/gpu/drm/panel/panel-novatek-nt36523.c<br/>index 63242c45cd7e..d6fa76dbf948 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-novatek-nt36523.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/panel/panel-novatek-nt36523.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panel/panel-novatek-nt36523.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panel/panel-novatek-nt36523.c</a></div><div class='hunk'>@@ -1252,9 +1252,9 @@ static int nt36523_probe(struct mipi_dsi_device *dsi)</div><div class='ctx'> 			return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");</div><div class='ctx'> </div><div class='ctx'> 		pinfo-&gt;dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);</div><div class='del'>-		if (!pinfo-&gt;dsi[1]) {</div><div class='add'>+		if (IS_ERR(pinfo-&gt;dsi[1])) {</div><div class='ctx'> 			dev_err(dev, "cannot get secondary DSI device\n");</div><div class='del'>-			return -ENODEV;</div><div class='add'>+			return PTR_ERR(pinfo-&gt;dsi[1]);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c<br/>index f59c82ea8870..2d30da38c2c3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panfrost/panfrost_devfreq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/panfrost/panfrost_devfreq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panfrost/panfrost_devfreq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panfrost/panfrost_devfreq.c</a></div><div class='hunk'>@@ -29,14 +29,20 @@ static void panfrost_devfreq_update_utilization(struct panfrost_devfreq *pfdevfr</div><div class='ctx'> static int panfrost_devfreq_target(struct device *dev, unsigned long *freq,</div><div class='ctx'> 				   u32 flags)</div><div class='ctx'> {</div><div class='add'>+	struct panfrost_device *ptdev = dev_get_drvdata(dev);</div><div class='ctx'> 	struct dev_pm_opp *opp;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	opp = devfreq_recommended_opp(dev, freq, flags);</div><div class='ctx'> 	if (IS_ERR(opp))</div><div class='ctx'> 		return PTR_ERR(opp);</div><div class='ctx'> 	dev_pm_opp_put(opp);</div><div class='ctx'> </div><div class='del'>-	return dev_pm_opp_set_rate(dev, *freq);</div><div class='add'>+	err =  dev_pm_opp_set_rate(dev, *freq);</div><div class='add'>+	if (!err)</div><div class='add'>+		ptdev-&gt;pfdevfreq.current_frequency = *freq;</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq)</div><div class='hunk'>@@ -58,7 +64,6 @@ static int panfrost_devfreq_get_dev_status(struct device *dev,</div><div class='ctx'> 	spin_lock_irqsave(&amp;pfdevfreq-&gt;lock, irqflags);</div><div class='ctx'> </div><div class='ctx'> 	panfrost_devfreq_update_utilization(pfdevfreq);</div><div class='del'>-	pfdevfreq-&gt;current_frequency = status-&gt;current_frequency;</div><div class='ctx'> </div><div class='ctx'> 	status-&gt;total_time = ktime_to_ns(ktime_add(pfdevfreq-&gt;busy_time,</div><div class='ctx'> 						   pfdevfreq-&gt;idle_time));</div><div class='hunk'>@@ -165,6 +170,14 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)</div><div class='ctx'> 	panfrost_devfreq_profile.initial_freq = cur_freq;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * We could wait until panfrost_devfreq_target() to set this value, but</div><div class='add'>+	 * since the simple_ondemand governor works asynchronously, there's a</div><div class='add'>+	 * chance by the time someone opens the device's fdinfo file, current</div><div class='add'>+	 * frequency hasn't been updated yet, so let's just do an early set.</div><div class='add'>+	 */</div><div class='add'>+	pfdevfreq-&gt;current_frequency = cur_freq;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Set the recommend OPP this will enable and configure the regulator</div><div class='ctx'> 	 * if any and will avoid a switch off by regulator_late_cleanup()</div><div class='ctx'> 	 */</div><div class='head'>diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.c b/drivers/gpu/drm/panfrost/panfrost_gem.c<br/>index 0cf64456e29a..d47b40b82b0b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panfrost/panfrost_gem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/panfrost/panfrost_gem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/panfrost/panfrost_gem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/panfrost/panfrost_gem.c</a></div><div class='hunk'>@@ -200,7 +200,7 @@ static enum drm_gem_object_status panfrost_gem_status(struct drm_gem_object *obj</div><div class='ctx'> 	struct panfrost_gem_object *bo = to_panfrost_bo(obj);</div><div class='ctx'> 	enum drm_gem_object_status res = 0;</div><div class='ctx'> </div><div class='del'>-	if (bo-&gt;base.pages)</div><div class='add'>+	if (bo-&gt;base.base.import_attach || bo-&gt;base.pages)</div><div class='ctx'> 		res |= DRM_GEM_OBJECT_RESIDENT;</div><div class='ctx'> </div><div class='ctx'> 	if (bo-&gt;base.madv == PANFROST_MADV_DONTNEED)</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c<br/>index 4aca09cab4b8..6e537c5bd295 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/atombios_encoders.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/atombios_encoders.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/atombios_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/atombios_encoders.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_crtc_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_file.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/clearstate_evergreen.h b/drivers/gpu/drm/radeon/clearstate_evergreen.h<br/>index 63a1ffbb3ced..3b645558f133 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/clearstate_evergreen.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/clearstate_evergreen.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/clearstate_evergreen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/clearstate_evergreen.h</a></div><div class='hunk'>@@ -1049,7 +1049,7 @@ static const struct cs_extent_def SECT_CONTEXT_defs[] =</div><div class='ctx'>     {SECT_CONTEXT_def_5, 0x0000a29e, 5 },</div><div class='ctx'>     {SECT_CONTEXT_def_6, 0x0000a2a5, 56 },</div><div class='ctx'>     {SECT_CONTEXT_def_7, 0x0000a2de, 290 },</div><div class='del'>-    { 0, 0, 0 }</div><div class='add'>+    { NULL, 0, 0 }</div><div class='ctx'> };</div><div class='ctx'> static const u32 SECT_CLEAR_def_1[] =</div><div class='ctx'> {</div><div class='hunk'>@@ -1060,7 +1060,7 @@ static const u32 SECT_CLEAR_def_1[] =</div><div class='ctx'> static const struct cs_extent_def SECT_CLEAR_defs[] =</div><div class='ctx'> {</div><div class='ctx'>     {SECT_CLEAR_def_1, 0x0000ffc0, 3 },</div><div class='del'>-    { 0, 0, 0 }</div><div class='add'>+    { NULL, 0, 0 }</div><div class='ctx'> };</div><div class='ctx'> static const u32 SECT_CTRLCONST_def_1[] =</div><div class='ctx'> {</div><div class='hunk'>@@ -1070,11 +1070,11 @@ static const u32 SECT_CTRLCONST_def_1[] =</div><div class='ctx'> static const struct cs_extent_def SECT_CTRLCONST_defs[] =</div><div class='ctx'> {</div><div class='ctx'>     {SECT_CTRLCONST_def_1, 0x0000f3fc, 2 },</div><div class='del'>-    { 0, 0, 0 }</div><div class='add'>+    { NULL, 0, 0 }</div><div class='ctx'> };</div><div class='ctx'> static const struct cs_section_def evergreen_cs_data[] = {</div><div class='ctx'>     { SECT_CONTEXT_defs, SECT_CONTEXT },</div><div class='ctx'>     { SECT_CLEAR_defs, SECT_CLEAR },</div><div class='ctx'>     { SECT_CTRLCONST_defs, SECT_CTRLCONST },</div><div class='del'>-    { 0, SECT_NONE }</div><div class='add'>+    { NULL, SECT_NONE }</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c<br/>index e8fe239b9d79..324e9b765098 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/dce3_1_afmt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/dce3_1_afmt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/dce3_1_afmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/dce3_1_afmt.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  * OTHER DEALINGS IN THE SOFTWARE.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/hdmi.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "radeon.h"</div><div class='ctx'> #include "radeon_asic.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c<br/>index 4a1d5447eac1..4c06f47453fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/dce6_afmt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/dce6_afmt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/dce6_afmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/dce6_afmt.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/hdmi.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dce6_afmt.h"</div><div class='ctx'> #include "radeon.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c<br/>index f0ae087be914..a424b86008b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/evergreen.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/evergreen.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/evergreen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/evergreen.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_vblank.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fourcc.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c<br/>index 5f3078f8ab95..681119c91d94 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/evergreen_hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/evergreen_hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/evergreen_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/evergreen_hdmi.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/hdmi.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='ctx'> #include "evergreen_hdmi.h"</div><div class='ctx'> #include "radeon.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c<br/>index affa9e0309b2..cfeca2694d5f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/r100.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/r100.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/r100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/r100.c</a></div><div class='hunk'>@@ -2321,7 +2321,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)</div><div class='ctx'> 	switch (prim_walk) {</div><div class='ctx'> 	case 1:</div><div class='ctx'> 		for (i = 0; i &lt; track-&gt;num_arrays; i++) {</div><div class='del'>-			size = track-&gt;arrays[i].esize * track-&gt;max_indx * 4;</div><div class='add'>+			size = track-&gt;arrays[i].esize * track-&gt;max_indx * 4UL;</div><div class='ctx'> 			if (track-&gt;arrays[i].robj == NULL) {</div><div class='ctx'> 				DRM_ERROR("(PW %u) Vertex array %u no buffer "</div><div class='ctx'> 					  "bound\n", prim_walk, i);</div><div class='hunk'>@@ -2340,7 +2340,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='ctx'> 		for (i = 0; i &lt; track-&gt;num_arrays; i++) {</div><div class='del'>-			size = track-&gt;arrays[i].esize * (nverts - 1) * 4;</div><div class='add'>+			size = track-&gt;arrays[i].esize * (nverts - 1) * 4UL;</div><div class='ctx'> 			if (track-&gt;arrays[i].robj == NULL) {</div><div class='ctx'> 				DRM_ERROR("(PW %u) Vertex array %u no buffer "</div><div class='ctx'> 					  "bound\n", prim_walk, i);</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c<br/>index 638f861af80f..6cf54a747749 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/r600_cs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/r600_cs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/r600_cs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/r600_cs.c</a></div><div class='hunk'>@@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> 		tmp = (reg - CB_COLOR0_BASE) / 4;</div><div class='del'>-		track-&gt;cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) &lt;&lt; 8;</div><div class='add'>+		track-&gt;cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) &lt;&lt; 8;</div><div class='ctx'> 		ib[idx] += (u32)((reloc-&gt;gpu_offset &gt;&gt; 8) &amp; 0xffffffff);</div><div class='ctx'> 		track-&gt;cb_color_base_last[tmp] = ib[idx];</div><div class='ctx'> 		track-&gt;cb_color_bo[tmp] = reloc-&gt;robj;</div><div class='hunk'>@@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)</div><div class='ctx'> 					"0x%04X\n", reg);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='del'>-		track-&gt;htile_offset = radeon_get_ib_value(p, idx) &lt;&lt; 8;</div><div class='add'>+		track-&gt;htile_offset = (u64)radeon_get_ib_value(p, idx) &lt;&lt; 8;</div><div class='ctx'> 		ib[idx] += (u32)((reloc-&gt;gpu_offset &gt;&gt; 8) &amp; 0xffffffff);</div><div class='ctx'> 		track-&gt;htile_bo = reloc-&gt;robj;</div><div class='ctx'> 		track-&gt;db_dirty = true;</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c<br/>index 85c4bb186203..3596ea4a8b60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_atombios.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_atombios.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_atombios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_atombios.c</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "radeon.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c<br/>index 279bf130a18c..91b58fbc2be7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_audio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_audio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_audio.c</a></div><div class='hunk'>@@ -27,6 +27,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='ctx'> #include &lt;drm/drm_eld.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include "dce6_afmt.h"</div><div class='ctx'> #include "evergreen_hdmi.h"</div><div class='ctx'> #include "radeon.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_audio.h b/drivers/gpu/drm/radeon/radeon_audio.h<br/>index 05e67867469b..dacaaa007051 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_audio.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_audio.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_audio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_audio.h</a></div><div class='hunk'>@@ -27,7 +27,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='del'>-#define RREG32_ENDPOINT(block, reg)		\</div><div class='add'>+struct cea_sad;</div><div class='add'>+</div><div class='add'>+#define RREG32_ENDPOINT(block, reg)				\</div><div class='ctx'> 	radeon_audio_endpoint_rreg(rdev, (block), (reg))</div><div class='ctx'> #define WREG32_ENDPOINT(block, reg, v)	\</div><div class='ctx'> 	radeon_audio_endpoint_wreg(rdev, (block), (reg), (v))</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c<br/>index 2620efc7c675..6952b1273b0f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_combios.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_combios.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_combios.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_combios.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "radeon.h"</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c<br/>index 901e75ec70ff..efd18c8d84c8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_display.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_display.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_display.c</a></div><div class='hunk'>@@ -687,11 +687,16 @@ static void radeon_crtc_init(struct drm_device *dev, int index)</div><div class='ctx'> 	if (radeon_crtc == NULL)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	radeon_crtc-&gt;flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);</div><div class='add'>+	if (!radeon_crtc-&gt;flip_queue) {</div><div class='add'>+		kfree(radeon_crtc);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	drm_crtc_init(dev, &amp;radeon_crtc-&gt;base, &amp;radeon_crtc_funcs);</div><div class='ctx'> </div><div class='ctx'> 	drm_mode_crtc_set_gamma_size(&amp;radeon_crtc-&gt;base, 256);</div><div class='ctx'> 	radeon_crtc-&gt;crtc_id = index;</div><div class='del'>-	radeon_crtc-&gt;flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);</div><div class='ctx'> 	rdev-&gt;mode_info.crtcs[index] = radeon_crtc;</div><div class='ctx'> </div><div class='ctx'> 	if (rdev-&gt;family &gt;= CHIP_BONAIRE) {</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c<br/>index 9cb6401fe97e..3de3dce9e89d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_encoders.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_encoders.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_encoders.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_encoders.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_device.h&gt;</div><div class='ctx'> #include &lt;drm/radeon_drm.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c<br/>index 314d066e68e9..3d174390a8af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_i2c.c</a></div><div class='hunk'>@@ -918,7 +918,6 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,</div><div class='ctx'> </div><div class='ctx'> 	i2c-&gt;rec = *rec;</div><div class='ctx'> 	i2c-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	i2c-&gt;adapter.class = I2C_CLASS_DDC;</div><div class='ctx'> 	i2c-&gt;adapter.dev.parent = dev-&gt;dev;</div><div class='ctx'> 	i2c-&gt;dev = dev;</div><div class='ctx'> 	i2c_set_adapdata(&amp;i2c-&gt;adapter, i2c);</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h<br/>index 1decdcec0264..59c4db13d90a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_mode.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_mode.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_mode.h</a></div><div class='hunk'>@@ -32,13 +32,13 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;drm/display/drm_dp_helper.h&gt;</div><div class='ctx'> #include &lt;drm/drm_crtc.h&gt;</div><div class='del'>-#include &lt;drm/drm_edid.h&gt;</div><div class='ctx'> #include &lt;drm/drm_encoder.h&gt;</div><div class='ctx'> #include &lt;drm/drm_fixed.h&gt;</div><div class='ctx'> #include &lt;drm/drm_modeset_helper_vtables.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/i2c-algo-bit.h&gt;</div><div class='ctx'> </div><div class='add'>+struct edid;</div><div class='ctx'> struct radeon_bo;</div><div class='ctx'> struct radeon_device;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c<br/>index e6534fa9f1fb..38048593bb4a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_ring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_ring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_ring.c</a></div><div class='hunk'>@@ -413,6 +413,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig</div><div class='ctx'> 			dev_err(rdev-&gt;dev, "(%d) ring map failed\n", r);</div><div class='ctx'> 			return r;</div><div class='ctx'> 		}</div><div class='add'>+		radeon_debugfs_ring_init(rdev, ring);</div><div class='ctx'> 	}</div><div class='ctx'> 	ring-&gt;ptr_mask = (ring-&gt;ring_size / 4) - 1;</div><div class='ctx'> 	ring-&gt;ring_free_dw = ring-&gt;ring_size / 4;</div><div class='hunk'>@@ -421,7 +422,6 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig</div><div class='ctx'> 		ring-&gt;next_rptr_gpu_addr = rdev-&gt;wb.gpu_addr + index;</div><div class='ctx'> 		ring-&gt;next_rptr_cpu_addr = &amp;rdev-&gt;wb.wb[index/4];</div><div class='ctx'> 	}</div><div class='del'>-	radeon_debugfs_ring_init(rdev, ring);</div><div class='ctx'> 	radeon_ring_lockup_update(rdev, ring);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c<br/>index 987cabbf1318..c38b4d5d6a14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_vm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/radeon_vm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/radeon_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/radeon_vm.c</a></div><div class='hunk'>@@ -1204,13 +1204,17 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)</div><div class='ctx'> 	r = radeon_bo_create(rdev, pd_size, align, true,</div><div class='ctx'> 			     RADEON_GEM_DOMAIN_VRAM, 0, NULL,</div><div class='ctx'> 			     NULL, &amp;vm-&gt;page_directory);</div><div class='del'>-	if (r)</div><div class='add'>+	if (r) {</div><div class='add'>+		kfree(vm-&gt;page_tables);</div><div class='add'>+		vm-&gt;page_tables = NULL;</div><div class='ctx'> 		return r;</div><div class='del'>-</div><div class='add'>+	}</div><div class='ctx'> 	r = radeon_vm_clear_bo(rdev, vm-&gt;page_directory);</div><div class='ctx'> 	if (r) {</div><div class='ctx'> 		radeon_bo_unref(&amp;vm-&gt;page_directory);</div><div class='ctx'> 		vm-&gt;page_directory = NULL;</div><div class='add'>+		kfree(vm-&gt;page_tables);</div><div class='add'>+		vm-&gt;page_tables = NULL;</div><div class='ctx'> 		return r;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c<br/>index a91012447b56..85e9cba49cec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/si.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/si.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/si.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/si.c</a></div><div class='hunk'>@@ -3611,6 +3611,10 @@ static int si_cp_start(struct radeon_device *rdev)</div><div class='ctx'> 	for (i = RADEON_RING_TYPE_GFX_INDEX; i &lt;= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {</div><div class='ctx'> 		ring = &amp;rdev-&gt;ring[i];</div><div class='ctx'> 		r = radeon_ring_lock(rdev, ring, 2);</div><div class='add'>+		if (r) {</div><div class='add'>+			DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);</div><div class='add'>+			return r;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		/* clear the compute context state */</div><div class='ctx'> 		radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c<br/>index f74f381af05f..d49c145db437 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/sumo_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/sumo_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/sumo_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/sumo_dpm.c</a></div><div class='hunk'>@@ -1493,8 +1493,10 @@ static int sumo_parse_power_table(struct radeon_device *rdev)</div><div class='ctx'> 		non_clock_array_index = power_state-&gt;v2.nonClockInfoIndex;</div><div class='ctx'> 		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)</div><div class='ctx'> 			&amp;non_clock_info_array-&gt;nonClockInfo[non_clock_array_index];</div><div class='del'>-		if (!rdev-&gt;pm.power_state[i].clock_info)</div><div class='add'>+		if (!rdev-&gt;pm.power_state[i].clock_info) {</div><div class='add'>+			kfree(rdev-&gt;pm.dpm.ps);</div><div class='ctx'> 			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 		ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);</div><div class='ctx'> 		if (ps == NULL) {</div><div class='ctx'> 			kfree(rdev-&gt;pm.dpm.ps);</div><div class='head'>diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c<br/>index 08ea1c864cb2..ef1cc7bad20a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/trinity_dpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/radeon/trinity_dpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/radeon/trinity_dpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/radeon/trinity_dpm.c</a></div><div class='hunk'>@@ -1726,8 +1726,10 @@ static int trinity_parse_power_table(struct radeon_device *rdev)</div><div class='ctx'> 		non_clock_array_index = power_state-&gt;v2.nonClockInfoIndex;</div><div class='ctx'> 		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)</div><div class='ctx'> 			&amp;non_clock_info_array-&gt;nonClockInfo[non_clock_array_index];</div><div class='del'>-		if (!rdev-&gt;pm.power_state[i].clock_info)</div><div class='add'>+		if (!rdev-&gt;pm.power_state[i].clock_info) {</div><div class='add'>+			kfree(rdev-&gt;pm.dpm.ps);</div><div class='ctx'> 			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 		ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);</div><div class='ctx'> 		if (ps == NULL) {</div><div class='ctx'> 			kfree(rdev-&gt;pm.dpm.ps);</div><div class='head'>diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c<br/>index 3bb8f1382612..1d2261643743 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/inno_hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/rockchip/inno_hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/inno_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/inno_hdmi.c</a></div><div class='hunk'>@@ -887,7 +887,6 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)</div><div class='ctx'> 	init_completion(&amp;i2c-&gt;cmp);</div><div class='ctx'> </div><div class='ctx'> 	adap = &amp;i2c-&gt;adap;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	adap-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	adap-&gt;dev.parent = hdmi-&gt;dev;</div><div class='ctx'> 	adap-&gt;dev.of_node = hdmi-&gt;dev-&gt;of_node;</div><div class='head'>diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c<br/>index 62e6d8187de7..95cd1b49eda8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/rk3066_hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/rockchip/rk3066_hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/rk3066_hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/rk3066_hdmi.c</a></div><div class='hunk'>@@ -715,7 +715,6 @@ static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)</div><div class='ctx'> 	init_completion(&amp;i2c-&gt;cmpltn);</div><div class='ctx'> </div><div class='ctx'> 	adap = &amp;i2c-&gt;adap;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	adap-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	adap-&gt;dev.parent = hdmi-&gt;dev;</div><div class='ctx'> 	adap-&gt;dev.of_node = hdmi-&gt;dev-&gt;of_node;</div><div class='head'>diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c<br/>index 44508c2dd614..85b3b4871a1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/rockchip/rockchip_drm_vop2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/rockchip/rockchip_drm_vop2.c</a></div><div class='hunk'>@@ -35,7 +35,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "rockchip_drm_drv.h"</div><div class='ctx'> #include "rockchip_drm_gem.h"</div><div class='del'>-#include "rockchip_drm_fb.h"</div><div class='ctx'> #include "rockchip_drm_vop2.h"</div><div class='ctx'> #include "rockchip_rgb.h"</div><div class='ctx'> </div><div class='hunk'>@@ -959,12 +958,6 @@ static void vop2_enable(struct vop2 *vop2)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = regmap_reinit_cache(vop2-&gt;map, &amp;vop2_regmap_config);</div><div class='del'>-	if (ret) {</div><div class='del'>-		drm_err(vop2-&gt;drm, "failed to reinit cache: %d\n", ret);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (vop2-&gt;data-&gt;soc_id == 3566)</div><div class='ctx'> 		vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);</div><div class='ctx'> </div><div class='hunk'>@@ -996,6 +989,8 @@ static void vop2_disable(struct vop2 *vop2)</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_put_sync(vop2-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	regcache_drop_region(vop2-&gt;map, 0, vop2_regmap_config.max_register);</div><div class='add'>+</div><div class='ctx'> 	clk_disable_unprepare(vop2-&gt;pclk);</div><div class='ctx'> 	clk_disable_unprepare(vop2-&gt;aclk);</div><div class='ctx'> 	clk_disable_unprepare(vop2-&gt;hclk);</div><div class='hunk'>@@ -1685,7 +1680,6 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,</div><div class='ctx'> 	unsigned long dclk_core_rate = v_pixclk &gt;&gt; 2;</div><div class='ctx'> 	unsigned long dclk_rate = v_pixclk;</div><div class='ctx'> 	unsigned long dclk_out_rate;</div><div class='del'>-	unsigned long if_dclk_rate;</div><div class='ctx'> 	unsigned long if_pixclk_rate;</div><div class='ctx'> 	int K = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -1700,13 +1694,13 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if_pixclk_rate = (dclk_core_rate &lt;&lt; 1) / K;</div><div class='del'>-		if_dclk_rate = dclk_core_rate / K;</div><div class='ctx'> 		/*</div><div class='add'>+		 * if_dclk_rate = dclk_core_rate / K;</div><div class='ctx'> 		 * *if_pixclk_div = dclk_rate / if_pixclk_rate;</div><div class='ctx'> 		 * *if_dclk_div = dclk_rate / if_dclk_rate;</div><div class='ctx'> 		 */</div><div class='del'>-		 *if_pixclk_div = 2;</div><div class='del'>-		 *if_dclk_div = 4;</div><div class='add'>+		*if_pixclk_div = 2;</div><div class='add'>+		*if_dclk_div = 4;</div><div class='ctx'> 	} else if (vop2_output_if_is_edp(id)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * edp_pixclk = edp_dclk &gt; dclk_core</div><div class='head'>diff --git a/drivers/gpu/drm/solomon/ssd130x.c b/drivers/gpu/drm/solomon/ssd130x.c<br/>index 447d0c7c88c6..ebd943b9e357 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/solomon/ssd130x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/solomon/ssd130x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/solomon/ssd130x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/solomon/ssd130x.c</a></div><div class='hunk'>@@ -345,7 +345,7 @@ static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x)</div><div class='ctx'> </div><div class='ctx'> 	pwm_init_state(ssd130x-&gt;pwm, &amp;pwmstate);</div><div class='ctx'> 	pwm_set_relative_duty_cycle(&amp;pwmstate, 50, 100);</div><div class='del'>-	pwm_apply_state(ssd130x-&gt;pwm, &amp;pwmstate);</div><div class='add'>+	pwm_apply_might_sleep(ssd130x-&gt;pwm, &amp;pwmstate);</div><div class='ctx'> </div><div class='ctx'> 	/* Enable the PWM */</div><div class='ctx'> 	pwm_enable(ssd130x-&gt;pwm);</div><div class='head'>diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c<br/>index d1a65a921f5a..f5f62eb0eeca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c</a></div><div class='hunk'>@@ -302,7 +302,6 @@ int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	adap-&gt;owner = THIS_MODULE;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_DDC;</div><div class='ctx'> 	adap-&gt;algo = &amp;sun4i_hdmi_i2c_algorithm;</div><div class='ctx'> 	strscpy(adap-&gt;name, "sun4i_hdmi_i2c adapter", sizeof(adap-&gt;name));</div><div class='ctx'> 	i2c_set_adapdata(adap, hdmi);</div><div class='head'>diff --git a/drivers/gpu/drm/tests/drm_exec_test.c b/drivers/gpu/drm/tests/drm_exec_test.c<br/>index 563949d777dd..81f928a429ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/tests/drm_exec_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/tests/drm_exec_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/tests/drm_exec_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/tests/drm_exec_test.c</a></div><div class='hunk'>@@ -46,7 +46,7 @@ static void sanitycheck(struct kunit *test)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_fini(&amp;exec);</div><div class='ctx'> 	KUNIT_SUCCEED(test);</div><div class='ctx'> }</div><div class='hunk'>@@ -60,7 +60,7 @@ static void test_lock(struct kunit *test)</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj, PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		ret = drm_exec_lock_obj(&amp;exec, &amp;gobj);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -80,7 +80,7 @@ static void test_lock_unlock(struct kunit *test)</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj, PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		ret = drm_exec_lock_obj(&amp;exec, &amp;gobj);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -107,7 +107,7 @@ static void test_duplicates(struct kunit *test)</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj, PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_IGNORE_DUPLICATES);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_IGNORE_DUPLICATES, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		ret = drm_exec_lock_obj(&amp;exec, &amp;gobj);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -134,7 +134,7 @@ static void test_prepare(struct kunit *test)</div><div class='ctx'> </div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj, PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec) {</div><div class='ctx'> 		ret = drm_exec_prepare_obj(&amp;exec, &amp;gobj, 1);</div><div class='ctx'> 		drm_exec_retry_on_contention(&amp;exec);</div><div class='hunk'>@@ -159,7 +159,7 @@ static void test_prepare_array(struct kunit *test)</div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj1, PAGE_SIZE);</div><div class='ctx'> 	drm_gem_private_object_init(priv-&gt;drm, &amp;gobj2, PAGE_SIZE);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec)</div><div class='ctx'> 		ret = drm_exec_prepare_array(&amp;exec, array, ARRAY_SIZE(array),</div><div class='ctx'> 					     1);</div><div class='hunk'>@@ -174,14 +174,14 @@ static void test_multiple_loops(struct kunit *test)</div><div class='ctx'> {</div><div class='ctx'> 	struct drm_exec exec;</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec)</div><div class='ctx'> 	{</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	drm_exec_fini(&amp;exec);</div><div class='ctx'> </div><div class='del'>-	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT);</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='ctx'> 	drm_exec_until_all_locked(&amp;exec)</div><div class='ctx'> 	{</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.c b/drivers/gpu/drm/tests/drm_kunit_helpers.c<br/>index bccb33b900f3..ca4f8e4c5d5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/tests/drm_kunit_helpers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/tests/drm_kunit_helpers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/tests/drm_kunit_helpers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/tests/drm_kunit_helpers.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> #include &lt;drm/drm_kunit_helpers.h&gt;</div><div class='ctx'> #include &lt;drm/drm_managed.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;kunit/device.h&gt;</div><div class='ctx'> #include &lt;kunit/resource.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='hunk'>@@ -15,40 +16,6 @@</div><div class='ctx'> static const struct drm_mode_config_funcs drm_mode_config_funcs = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int fake_probe(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct platform_driver fake_platform_driver = {</div><div class='del'>-	.probe	= fake_probe,</div><div class='del'>-	.driver = {</div><div class='del'>-		.name	= KUNIT_DEVICE_NAME,</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void kunit_action_platform_driver_unregister(void *ptr)</div><div class='del'>-{</div><div class='del'>-	struct platform_driver *drv = ptr;</div><div class='del'>-</div><div class='del'>-	platform_driver_unregister(drv);</div><div class='del'>-</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void kunit_action_platform_device_put(void *ptr)</div><div class='del'>-{</div><div class='del'>-	struct platform_device *pdev = ptr;</div><div class='del'>-</div><div class='del'>-	platform_device_put(pdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void kunit_action_platform_device_del(void *ptr)</div><div class='del'>-{</div><div class='del'>-	struct platform_device *pdev = ptr;</div><div class='del'>-</div><div class='del'>-	platform_device_del(pdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * drm_kunit_helper_alloc_device - Allocate a mock device for a KUnit test</div><div class='ctx'>  * @test: The test context object</div><div class='hunk'>@@ -66,34 +33,7 @@ static void kunit_action_platform_device_del(void *ptr)</div><div class='ctx'>  */</div><div class='ctx'> struct device *drm_kunit_helper_alloc_device(struct kunit *test)</div><div class='ctx'> {</div><div class='del'>-	struct platform_device *pdev;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = platform_driver_register(&amp;fake_platform_driver);</div><div class='del'>-	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='del'>-</div><div class='del'>-	ret = kunit_add_action_or_reset(test,</div><div class='del'>-					kunit_action_platform_driver_unregister,</div><div class='del'>-					&amp;fake_platform_driver);</div><div class='del'>-	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='del'>-</div><div class='del'>-	pdev = platform_device_alloc(KUNIT_DEVICE_NAME, PLATFORM_DEVID_NONE);</div><div class='del'>-	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, pdev);</div><div class='del'>-</div><div class='del'>-	ret = kunit_add_action_or_reset(test,</div><div class='del'>-					kunit_action_platform_device_put,</div><div class='del'>-					pdev);</div><div class='del'>-	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='del'>-</div><div class='del'>-	ret = platform_device_add(pdev);</div><div class='del'>-	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='del'>-</div><div class='del'>-	ret = kunit_add_action_or_reset(test,</div><div class='del'>-					kunit_action_platform_device_del,</div><div class='del'>-					pdev);</div><div class='del'>-	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='del'>-</div><div class='del'>-	return &amp;pdev-&gt;dev;</div><div class='add'>+	return kunit_device_register(test, KUNIT_DEVICE_NAME);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(drm_kunit_helper_alloc_device);</div><div class='ctx'> </div><div class='hunk'>@@ -106,19 +46,7 @@ EXPORT_SYMBOL_GPL(drm_kunit_helper_alloc_device);</div><div class='ctx'>  */</div><div class='ctx'> void drm_kunit_helper_free_device(struct kunit *test, struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct platform_device *pdev = to_platform_device(dev);</div><div class='del'>-</div><div class='del'>-	kunit_release_action(test,</div><div class='del'>-			     kunit_action_platform_device_del,</div><div class='del'>-			     pdev);</div><div class='del'>-</div><div class='del'>-	kunit_release_action(test,</div><div class='del'>-			     kunit_action_platform_device_put,</div><div class='del'>-			     pdev);</div><div class='del'>-</div><div class='del'>-	kunit_release_action(test,</div><div class='del'>-			     kunit_action_platform_driver_unregister,</div><div class='del'>-			     &amp;fake_platform_driver);</div><div class='add'>+	kunit_device_unregister(test, dev);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(drm_kunit_helper_free_device);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/ttm/tests/ttm_device_test.c b/drivers/gpu/drm/ttm/tests/ttm_device_test.c<br/>index b1b423b68cdf..19eaff22e6ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/tests/ttm_device_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/ttm/tests/ttm_device_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/tests/ttm_device_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/tests/ttm_device_test.c</a></div><div class='hunk'>@@ -175,7 +175,7 @@ static void ttm_device_init_pools(struct kunit *test)</div><div class='ctx'> </div><div class='ctx'> 	if (params-&gt;pools_init_expected) {</div><div class='ctx'> 		for (int i = 0; i &lt; TTM_NUM_CACHING_TYPES; ++i) {</div><div class='del'>-			for (int j = 0; j &lt;= MAX_ORDER; ++j) {</div><div class='add'>+			for (int j = 0; j &lt; NR_PAGE_ORDERS; ++j) {</div><div class='ctx'> 				pt = pool-&gt;caching[i].orders[j];</div><div class='ctx'> 				KUNIT_EXPECT_PTR_EQ(test, pt.pool, pool);</div><div class='ctx'> 				KUNIT_EXPECT_EQ(test, pt.caching, i);</div><div class='head'>diff --git a/drivers/gpu/drm/ttm/tests/ttm_pool_test.c b/drivers/gpu/drm/ttm/tests/ttm_pool_test.c<br/>index b97f7b6daf5b..0a3fede84da9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/tests/ttm_pool_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/ttm/tests/ttm_pool_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/tests/ttm_pool_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/tests/ttm_pool_test.c</a></div><div class='hunk'>@@ -108,7 +108,7 @@ static const struct ttm_pool_test_case ttm_pool_basic_cases[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.description = "Above the allocation limit",</div><div class='del'>-		.order = MAX_ORDER + 1,</div><div class='add'>+		.order = MAX_PAGE_ORDER + 1,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.description = "One page, with coherent DMA mappings enabled",</div><div class='hunk'>@@ -117,7 +117,7 @@ static const struct ttm_pool_test_case ttm_pool_basic_cases[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.description = "Above the allocation limit, with coherent DMA mappings enabled",</div><div class='del'>-		.order = MAX_ORDER + 1,</div><div class='add'>+		.order = MAX_PAGE_ORDER + 1,</div><div class='ctx'> 		.use_dma_alloc = true,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -164,7 +164,7 @@ static void ttm_pool_alloc_basic(struct kunit *test)</div><div class='ctx'> 	fst_page = tt-&gt;pages[0];</div><div class='ctx'> 	last_page = tt-&gt;pages[tt-&gt;num_pages - 1];</div><div class='ctx'> </div><div class='del'>-	if (params-&gt;order &lt;= MAX_ORDER) {</div><div class='add'>+	if (params-&gt;order &lt;= MAX_PAGE_ORDER) {</div><div class='ctx'> 		if (params-&gt;use_dma_alloc) {</div><div class='ctx'> 			KUNIT_ASSERT_NOT_NULL(test, (void *)fst_page-&gt;private);</div><div class='ctx'> 			KUNIT_ASSERT_NOT_NULL(test, (void *)last_page-&gt;private);</div><div class='hunk'>@@ -181,7 +181,7 @@ static void ttm_pool_alloc_basic(struct kunit *test)</div><div class='ctx'> 			 * order 0 blocks</div><div class='ctx'> 			 */</div><div class='ctx'> 			KUNIT_ASSERT_EQ(test, fst_page-&gt;private,</div><div class='del'>-					min_t(unsigned int, MAX_ORDER,</div><div class='add'>+					min_t(unsigned int, MAX_PAGE_ORDER,</div><div class='ctx'> 					      params-&gt;order));</div><div class='ctx'> 			KUNIT_ASSERT_EQ(test, last_page-&gt;private, 0);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c<br/>index fe610a3cace0..b62f420a9f96 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/ttm_pool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/ttm/ttm_pool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/ttm/ttm_pool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/ttm/ttm_pool.c</a></div><div class='hunk'>@@ -65,11 +65,11 @@ module_param(page_pool_size, ulong, 0644);</div><div class='ctx'> </div><div class='ctx'> static atomic_long_t allocated_pages;</div><div class='ctx'> </div><div class='del'>-static struct ttm_pool_type global_write_combined[MAX_ORDER + 1];</div><div class='del'>-static struct ttm_pool_type global_uncached[MAX_ORDER + 1];</div><div class='add'>+static struct ttm_pool_type global_write_combined[NR_PAGE_ORDERS];</div><div class='add'>+static struct ttm_pool_type global_uncached[NR_PAGE_ORDERS];</div><div class='ctx'> </div><div class='del'>-static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER + 1];</div><div class='del'>-static struct ttm_pool_type global_dma32_uncached[MAX_ORDER + 1];</div><div class='add'>+static struct ttm_pool_type global_dma32_write_combined[NR_PAGE_ORDERS];</div><div class='add'>+static struct ttm_pool_type global_dma32_uncached[NR_PAGE_ORDERS];</div><div class='ctx'> </div><div class='ctx'> static spinlock_t shrinker_lock;</div><div class='ctx'> static struct list_head shrinker_list;</div><div class='hunk'>@@ -447,7 +447,7 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,</div><div class='ctx'> 	else</div><div class='ctx'> 		gfp_flags |= GFP_HIGHUSER;</div><div class='ctx'> </div><div class='del'>-	for (order = min_t(unsigned int, MAX_ORDER, __fls(num_pages));</div><div class='add'>+	for (order = min_t(unsigned int, MAX_PAGE_ORDER, __fls(num_pages));</div><div class='ctx'> 	     num_pages;</div><div class='ctx'> 	     order = min_t(unsigned int, order, __fls(num_pages))) {</div><div class='ctx'> 		struct ttm_pool_type *pt;</div><div class='hunk'>@@ -568,7 +568,7 @@ void ttm_pool_init(struct ttm_pool *pool, struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	if (use_dma_alloc || nid != NUMA_NO_NODE) {</div><div class='ctx'> 		for (i = 0; i &lt; TTM_NUM_CACHING_TYPES; ++i)</div><div class='del'>-			for (j = 0; j &lt;= MAX_ORDER; ++j)</div><div class='add'>+			for (j = 0; j &lt; NR_PAGE_ORDERS; ++j)</div><div class='ctx'> 				ttm_pool_type_init(&amp;pool-&gt;caching[i].orders[j],</div><div class='ctx'> 						   pool, i, j);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -601,7 +601,7 @@ void ttm_pool_fini(struct ttm_pool *pool)</div><div class='ctx'> </div><div class='ctx'> 	if (pool-&gt;use_dma_alloc || pool-&gt;nid != NUMA_NO_NODE) {</div><div class='ctx'> 		for (i = 0; i &lt; TTM_NUM_CACHING_TYPES; ++i)</div><div class='del'>-			for (j = 0; j &lt;= MAX_ORDER; ++j)</div><div class='add'>+			for (j = 0; j &lt; NR_PAGE_ORDERS; ++j)</div><div class='ctx'> 				ttm_pool_type_fini(&amp;pool-&gt;caching[i].orders[j]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -656,7 +656,7 @@ static void ttm_pool_debugfs_header(struct seq_file *m)</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	seq_puts(m, "\t ");</div><div class='del'>-	for (i = 0; i &lt;= MAX_ORDER; ++i)</div><div class='add'>+	for (i = 0; i &lt; NR_PAGE_ORDERS; ++i)</div><div class='ctx'> 		seq_printf(m, " ---%2u---", i);</div><div class='ctx'> 	seq_puts(m, "\n");</div><div class='ctx'> }</div><div class='hunk'>@@ -667,7 +667,7 @@ static void ttm_pool_debugfs_orders(struct ttm_pool_type *pt,</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt;= MAX_ORDER; ++i)</div><div class='add'>+	for (i = 0; i &lt; NR_PAGE_ORDERS; ++i)</div><div class='ctx'> 		seq_printf(m, " %8u", ttm_pool_type_count(&amp;pt[i]));</div><div class='ctx'> 	seq_puts(m, "\n");</div><div class='ctx'> }</div><div class='hunk'>@@ -776,7 +776,7 @@ int ttm_pool_mgr_init(unsigned long num_pages)</div><div class='ctx'> 	spin_lock_init(&amp;shrinker_lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;shrinker_list);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt;= MAX_ORDER; ++i) {</div><div class='add'>+	for (i = 0; i &lt; NR_PAGE_ORDERS; ++i) {</div><div class='ctx'> 		ttm_pool_type_init(&amp;global_write_combined[i], NULL,</div><div class='ctx'> 				   ttm_write_combined, i);</div><div class='ctx'> 		ttm_pool_type_init(&amp;global_uncached[i], NULL, ttm_uncached, i);</div><div class='hunk'>@@ -816,7 +816,7 @@ void ttm_pool_mgr_fini(void)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt;= MAX_ORDER; ++i) {</div><div class='add'>+	for (i = 0; i &lt; NR_PAGE_ORDERS; ++i) {</div><div class='ctx'> 		ttm_pool_type_fini(&amp;global_write_combined[i]);</div><div class='ctx'> 		ttm_pool_type_fini(&amp;global_uncached[i]);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c<br/>index cdfe1d3bf5ee..dc3cf708d02e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/v3d/v3d_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/v3d/v3d_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/v3d/v3d_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/v3d/v3d_debugfs.c</a></div><div class='hunk'>@@ -62,9 +62,9 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {</div><div class='ctx'> 	REGDEF(33, 71, V3D_PTB_BPCA),</div><div class='ctx'> 	REGDEF(33, 71, V3D_PTB_BPCS),</div><div class='ctx'> </div><div class='del'>-	REGDEF(33, 41, V3D_GMP_STATUS(33)),</div><div class='del'>-	REGDEF(33, 41, V3D_GMP_CFG(33)),</div><div class='del'>-	REGDEF(33, 41, V3D_GMP_VIO_ADDR(33)),</div><div class='add'>+	REGDEF(33, 42, V3D_GMP_STATUS(33)),</div><div class='add'>+	REGDEF(33, 42, V3D_GMP_CFG(33)),</div><div class='add'>+	REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),</div><div class='ctx'> </div><div class='ctx'> 	REGDEF(33, 71, V3D_ERR_FDBGO),</div><div class='ctx'> 	REGDEF(33, 71, V3D_ERR_FDBGB),</div><div class='hunk'>@@ -74,13 +74,13 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {</div><div class='ctx'> </div><div class='ctx'> static const struct v3d_reg_def v3d_csd_reg_defs[] = {</div><div class='ctx'> 	REGDEF(41, 71, V3D_CSD_STATUS),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG0(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG1(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG2(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG3(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG4(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG5(41)),</div><div class='del'>-	REGDEF(41, 41, V3D_CSD_CURRENT_CFG6(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),</div><div class='add'>+	REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),</div><div class='ctx'> 	REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),</div><div class='ctx'> 	REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),</div><div class='ctx'> 	REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),</div><div class='head'>diff --git a/drivers/gpu/drm/vc4/tests/vc4_mock.c b/drivers/gpu/drm/vc4/tests/vc4_mock.c<br/>index 63ca46f4cb35..becb3dbaa548 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/gpu/drm/vc4/tests/vc4_mock.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/gpu/drm/vc4/tests/vc4_mock.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/vc4/tests/vc4_mock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/vc4/tests/vc4_mock.c</a></div><div class='hunk'>@@ -153,12 +153,9 @@ static int __build_mock(struct kunit *test, struct drm_device *drm,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void kunit_action_drm_dev_unregister(void *ptr)</div><div class='del'>-{</div><div class='del'>-	struct drm_device *drm = ptr;</div><div class='del'>-</div><div class='del'>-	drm_dev_unregister(drm);</div><div class='del'>-}</div><div class='add'>+KUNIT_DEFINE_ACTION_WRAPPER(kunit_action_drm_dev_unregister,</div><div class='add'>+			    drm_dev_unregister,</div><div class='add'>+			    struct drm_device *);</div><div class='ctx'> </div><div class='ctx'> static struct vc4_dev *__mock_device(struct kunit *test, bool is_vc5)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/gpu/drm/xe/.gitignore b/drivers/gpu/drm/xe/.gitignore<br/>new file mode 100644<br/>index 000000000000..8778bf132674<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/.gitignore?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/.gitignore</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+*.hdrtest</div><div class='add'>+/generated</div><div class='add'>+/xe_gen_wa_oob</div><div class='head'>diff --git a/drivers/gpu/drm/xe/.kunitconfig b/drivers/gpu/drm/xe/.kunitconfig<br/>new file mode 100644<br/>index 000000000000..9590eac91af3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/.kunitconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/.kunitconfig</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+# xe dependencies</div><div class='add'>+CONFIG_KUNIT=y</div><div class='add'>+CONFIG_PCI=y</div><div class='add'>+CONFIG_PCI_IOV=y</div><div class='add'>+CONFIG_DEBUG_FS=y</div><div class='add'>+CONFIG_DRM=y</div><div class='add'>+CONFIG_DRM_FBDEV_EMULATION=y</div><div class='add'>+CONFIG_DRM_KMS_HELPER=y</div><div class='add'>+CONFIG_DRM_XE=y</div><div class='add'>+CONFIG_DRM_XE_DISPLAY=n</div><div class='add'>+CONFIG_EXPERT=y</div><div class='add'>+CONFIG_FB=y</div><div class='add'>+CONFIG_DRM_XE_KUNIT_TEST=y</div><div class='head'>diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig<br/>new file mode 100644<br/>index 000000000000..e36ae1f0d885<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+config DRM_XE</div><div class='add'>+	tristate "Intel Xe Graphics"</div><div class='add'>+	depends on DRM &amp;&amp; PCI &amp;&amp; MMU &amp;&amp; (m || (y &amp;&amp; KUNIT=y)) &amp;&amp; 64BIT</div><div class='add'>+	select INTERVAL_TREE</div><div class='add'>+	# we need shmfs for the swappable backing store, and in particular</div><div class='add'>+	# the shmem_readpage() which depends upon tmpfs</div><div class='add'>+	select SHMEM</div><div class='add'>+	select TMPFS</div><div class='add'>+	select DRM_BUDDY</div><div class='add'>+	select DRM_EXEC</div><div class='add'>+	select DRM_KMS_HELPER</div><div class='add'>+	select DRM_PANEL</div><div class='add'>+	select DRM_SUBALLOC_HELPER</div><div class='add'>+	select DRM_DISPLAY_DP_HELPER</div><div class='add'>+	select DRM_DISPLAY_HDCP_HELPER</div><div class='add'>+	select DRM_DISPLAY_HDMI_HELPER</div><div class='add'>+	select DRM_DISPLAY_HELPER</div><div class='add'>+	select DRM_MIPI_DSI</div><div class='add'>+	select RELAY</div><div class='add'>+	select IRQ_WORK</div><div class='add'>+	# xe depends on ACPI_VIDEO when ACPI is enabled</div><div class='add'>+	# but for select to work, need to select ACPI_VIDEO's dependencies, ick</div><div class='add'>+	select BACKLIGHT_CLASS_DEVICE if ACPI</div><div class='add'>+	select INPUT if ACPI</div><div class='add'>+	select ACPI_VIDEO if X86 &amp;&amp; ACPI</div><div class='add'>+	select ACPI_BUTTON if ACPI</div><div class='add'>+	select ACPI_WMI if X86 &amp;&amp; ACPI</div><div class='add'>+	select SYNC_FILE</div><div class='add'>+	select IOSF_MBI</div><div class='add'>+	select CRC32</div><div class='add'>+	select SND_HDA_I915 if SND_HDA_CORE</div><div class='add'>+	select CEC_CORE if CEC_NOTIFIER</div><div class='add'>+	select VMAP_PFN</div><div class='add'>+	select DRM_TTM</div><div class='add'>+	select DRM_TTM_HELPER</div><div class='add'>+	select DRM_EXEC</div><div class='add'>+	select DRM_GPUVM</div><div class='add'>+	select DRM_SCHED</div><div class='add'>+	select MMU_NOTIFIER</div><div class='add'>+	select WANT_DEV_COREDUMP</div><div class='add'>+	select AUXILIARY_BUS</div><div class='add'>+	help</div><div class='add'>+	  Experimental driver for Intel Xe series GPUs</div><div class='add'>+</div><div class='add'>+	  If "M" is selected, the module will be called xe.</div><div class='add'>+</div><div class='add'>+config DRM_XE_DISPLAY</div><div class='add'>+	bool "Enable display support"</div><div class='add'>+	depends on DRM_XE &amp;&amp; DRM_XE=m</div><div class='add'>+	select FB_IOMEM_HELPERS</div><div class='add'>+	select I2C</div><div class='add'>+	select I2C_ALGOBIT</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Disable this option only if you want to compile out display support.</div><div class='add'>+</div><div class='add'>+config DRM_XE_FORCE_PROBE</div><div class='add'>+	string "Force probe xe for selected Intel hardware IDs"</div><div class='add'>+	depends on DRM_XE</div><div class='add'>+	help</div><div class='add'>+	  This is the default value for the xe.force_probe module</div><div class='add'>+	  parameter. Using the module parameter overrides this option.</div><div class='add'>+</div><div class='add'>+	  Force probe the xe for Intel graphics devices that are</div><div class='add'>+	  recognized but not properly supported by this kernel version. It is</div><div class='add'>+	  recommended to upgrade to a kernel version with proper support as soon</div><div class='add'>+	  as it is available.</div><div class='add'>+</div><div class='add'>+	  It can also be used to block the probe of recognized and fully</div><div class='add'>+	  supported devices.</div><div class='add'>+</div><div class='add'>+	  Use "" to disable force probe. If in doubt, use this.</div><div class='add'>+</div><div class='add'>+	  Use "&lt;pci-id&gt;[,&lt;pci-id&gt;,...]" to force probe the xe for listed</div><div class='add'>+	  devices. For example, "4500" or "4500,4571".</div><div class='add'>+</div><div class='add'>+	  Use "*" to force probe the driver for all known devices.</div><div class='add'>+</div><div class='add'>+	  Use "!" right before the ID to block the probe of the device. For</div><div class='add'>+	  example, "4500,!4571" forces the probe of 4500 and blocks the probe of</div><div class='add'>+	  4571.</div><div class='add'>+</div><div class='add'>+	  Use "!*" to block the probe of the driver for all known devices.</div><div class='add'>+</div><div class='add'>+menu "drm/Xe Debugging"</div><div class='add'>+depends on DRM_XE</div><div class='add'>+depends on EXPERT</div><div class='add'>+source "drivers/gpu/drm/xe/Kconfig.debug"</div><div class='add'>+endmenu</div><div class='add'>+</div><div class='add'>+menu "drm/xe Profile Guided Optimisation"</div><div class='add'>+	visible if EXPERT</div><div class='add'>+	depends on DRM_XE</div><div class='add'>+	source "drivers/gpu/drm/xe/Kconfig.profile"</div><div class='add'>+endmenu</div><div class='head'>diff --git a/drivers/gpu/drm/xe/Kconfig.debug b/drivers/gpu/drm/xe/Kconfig.debug<br/>new file mode 100644<br/>index 000000000000..549065f57a78<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/Kconfig.debug?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig.debug</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+config DRM_XE_WERROR</div><div class='add'>+	bool "Force GCC to throw an error instead of a warning when compiling"</div><div class='add'>+	# As this may inadvertently break the build, only allow the user</div><div class='add'>+	# to shoot oneself in the foot iff they aim really hard</div><div class='add'>+	depends on EXPERT</div><div class='add'>+	# We use the dependency on !COMPILE_TEST to not be enabled in</div><div class='add'>+	# allmodconfig or allyesconfig configurations</div><div class='add'>+	depends on !COMPILE_TEST</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Add -Werror to the build flags for (and only for) xe.ko.</div><div class='add'>+	  Do not enable this unless you are writing code for the xe.ko module.</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_DEBUG</div><div class='add'>+	bool "Enable additional driver debugging"</div><div class='add'>+	depends on DRM_XE</div><div class='add'>+	depends on EXPERT</div><div class='add'>+	depends on !COMPILE_TEST</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Choose this option to turn on extra driver debugging that may affect</div><div class='add'>+	  performance but will catch some internal issues.</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_DEBUG_VM</div><div class='add'>+	bool "Enable extra VM debugging info"</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Enable extra VM debugging info</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_DEBUG_SRIOV</div><div class='add'>+	bool "Enable extra SR-IOV debugging"</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Enable extra SR-IOV debugging info.</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_DEBUG_MEM</div><div class='add'>+	bool "Enable passing SYS/VRAM addresses to user space"</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Pass object location trough uapi. Intended for extended</div><div class='add'>+	  testing and development only.</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_SIMPLE_ERROR_CAPTURE</div><div class='add'>+	bool "Enable simple error capture to dmesg on job timeout"</div><div class='add'>+	default n</div><div class='add'>+	help</div><div class='add'>+	  Choose this option when debugging an unexpected job timeout</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_KUNIT_TEST</div><div class='add'>+        tristate "KUnit tests for the drm xe driver" if !KUNIT_ALL_TESTS</div><div class='add'>+	depends on DRM_XE &amp;&amp; KUNIT &amp;&amp; DEBUG_FS</div><div class='add'>+	default KUNIT_ALL_TESTS</div><div class='add'>+	select DRM_EXPORT_FOR_TESTS if m</div><div class='add'>+	select DRM_KUNIT_TEST_HELPERS</div><div class='add'>+	help</div><div class='add'>+	  Choose this option to allow the driver to perform selftests under</div><div class='add'>+	  the kunit framework</div><div class='add'>+</div><div class='add'>+	  Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+	  If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_LARGE_GUC_BUFFER</div><div class='add'>+        bool "Enable larger guc log buffer"</div><div class='add'>+        default n</div><div class='add'>+        help</div><div class='add'>+          Choose this option when debugging guc issues.</div><div class='add'>+          Buffer should be large enough for complex issues.</div><div class='add'>+</div><div class='add'>+          Recommended for driver developers only.</div><div class='add'>+</div><div class='add'>+          If in doubt, say "N".</div><div class='add'>+</div><div class='add'>+config DRM_XE_USERPTR_INVAL_INJECT</div><div class='add'>+       bool "Inject userptr invalidation -EINVAL errors"</div><div class='add'>+       default n</div><div class='add'>+       help</div><div class='add'>+         Choose this option when debugging error paths that</div><div class='add'>+	 are hit during checks for userptr invalidations.</div><div class='add'>+</div><div class='add'>+	 Recomended for driver developers only.</div><div class='add'>+	 If in doubt, say "N".</div><div class='head'>diff --git a/drivers/gpu/drm/xe/Kconfig.profile b/drivers/gpu/drm/xe/Kconfig.profile<br/>new file mode 100644<br/>index 000000000000..ba17a25e8db3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/Kconfig.profile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Kconfig.profile</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+config DRM_XE_JOB_TIMEOUT_MAX</div><div class='add'>+	int "Default max job timeout (ms)"</div><div class='add'>+	default 10000 # milliseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default max job timeout after which job will</div><div class='add'>+	  be forcefully taken away from scheduler.</div><div class='add'>+config DRM_XE_JOB_TIMEOUT_MIN</div><div class='add'>+	int "Default min job timeout (ms)"</div><div class='add'>+	default 1 # milliseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default min job timeout after which job will</div><div class='add'>+	  be forcefully taken away from scheduler.</div><div class='add'>+config DRM_XE_TIMESLICE_MAX</div><div class='add'>+	int "Default max timeslice duration (us)"</div><div class='add'>+	default 10000000 # microseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default max timeslice duration between multiple</div><div class='add'>+	  contexts by guc scheduling.</div><div class='add'>+config DRM_XE_TIMESLICE_MIN</div><div class='add'>+	int "Default min timeslice duration (us)"</div><div class='add'>+	default 1 # microseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default min timeslice duration between multiple</div><div class='add'>+	  contexts by guc scheduling.</div><div class='add'>+config DRM_XE_PREEMPT_TIMEOUT</div><div class='add'>+	int "Preempt timeout (us, jiffy granularity)"</div><div class='add'>+	default 640000 # microseconds</div><div class='add'>+	help</div><div class='add'>+	  How long to wait (in microseconds) for a preemption event to occur</div><div class='add'>+	  when submitting a new context. If the current context does not hit</div><div class='add'>+	  an arbitration point and yield to HW before the timer expires, the</div><div class='add'>+	  HW will be reset to allow the more important context to execute.</div><div class='add'>+config DRM_XE_PREEMPT_TIMEOUT_MAX</div><div class='add'>+	int "Default max preempt timeout (us)"</div><div class='add'>+	default 10000000 # microseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default max preempt timeout after which context</div><div class='add'>+	  will be forcefully taken away and higher priority context will</div><div class='add'>+	  run.</div><div class='add'>+config DRM_XE_PREEMPT_TIMEOUT_MIN</div><div class='add'>+	int "Default min preempt timeout (us)"</div><div class='add'>+	default 1 # microseconds</div><div class='add'>+	help</div><div class='add'>+	  Configures the default min preempt timeout after which context</div><div class='add'>+	  will be forcefully taken away and higher priority context will</div><div class='add'>+	  run.</div><div class='add'>+config DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT</div><div class='add'>+	bool "Default configuration of limitation on scheduler timeout"</div><div class='add'>+	default y</div><div class='add'>+	help</div><div class='add'>+	  Configures the enablement of limitation on scheduler timeout</div><div class='add'>+	  to apply to applicable user. For elevated user, all above MIN</div><div class='add'>+	  and MAX values will apply when this configuration is enable to</div><div class='add'>+	  apply limitation. By default limitation is applied.</div><div class='head'>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile<br/>new file mode 100644<br/>index 000000000000..efcf0ab7a1a6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/Makefile</a></div><div class='hunk'>@@ -0,0 +1,304 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# Makefile for the drm device driver.  This driver provides support for the</div><div class='add'>+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.</div><div class='add'>+</div><div class='add'>+# Unconditionally enable W=1 warnings locally</div><div class='add'>+# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn</div><div class='add'>+subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter</div><div class='add'>+subdir-ccflags-y += -Wmissing-declarations</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wrestrict)</div><div class='add'>+subdir-ccflags-y += -Wmissing-format-attribute</div><div class='add'>+subdir-ccflags-y += -Wmissing-prototypes</div><div class='add'>+subdir-ccflags-y += -Wold-style-definition</div><div class='add'>+subdir-ccflags-y += -Wmissing-include-dirs</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wformat-overflow)</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wformat-truncation)</div><div class='add'>+subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)</div><div class='add'>+# The following turn off the warnings enabled by -Wextra</div><div class='add'>+ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)</div><div class='add'>+subdir-ccflags-y += -Wno-missing-field-initializers</div><div class='add'>+subdir-ccflags-y += -Wno-type-limits</div><div class='add'>+subdir-ccflags-y += -Wno-shift-negative-value</div><div class='add'>+endif</div><div class='add'>+ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)</div><div class='add'>+subdir-ccflags-y += -Wno-sign-compare</div><div class='add'>+endif</div><div class='add'>+# --- end copy-paste</div><div class='add'>+</div><div class='add'>+# Enable -Werror in CI and development</div><div class='add'>+subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror</div><div class='add'>+</div><div class='add'>+subdir-ccflags-y += -I$(obj) -I$(srctree)/$(src)</div><div class='add'>+</div><div class='add'>+# generated sources</div><div class='add'>+hostprogs := xe_gen_wa_oob</div><div class='add'>+</div><div class='add'>+generated_oob := $(obj)/generated/xe_wa_oob.c $(obj)/generated/xe_wa_oob.h</div><div class='add'>+</div><div class='add'>+quiet_cmd_wa_oob = GEN     $(notdir $(generated_oob))</div><div class='add'>+      cmd_wa_oob = mkdir -p $(@D); $^ $(generated_oob)</div><div class='add'>+</div><div class='add'>+$(generated_oob) &amp;: $(obj)/xe_gen_wa_oob $(srctree)/$(src)/xe_wa_oob.rules</div><div class='add'>+	$(call cmd,wa_oob)</div><div class='add'>+</div><div class='add'>+uses_generated_oob := \</div><div class='add'>+	$(obj)/xe_gsc.o \</div><div class='add'>+	$(obj)/xe_guc.o \</div><div class='add'>+	$(obj)/xe_migrate.o \</div><div class='add'>+	$(obj)/xe_ring_ops.o \</div><div class='add'>+	$(obj)/xe_vm.o \</div><div class='add'>+	$(obj)/xe_wa.o \</div><div class='add'>+	$(obj)/xe_ttm_stolen_mgr.o</div><div class='add'>+</div><div class='add'>+$(uses_generated_oob): $(generated_oob)</div><div class='add'>+</div><div class='add'>+# Please keep these build lists sorted!</div><div class='add'>+</div><div class='add'>+# core driver code</div><div class='add'>+</div><div class='add'>+xe-y += xe_bb.o \</div><div class='add'>+	xe_bo.o \</div><div class='add'>+	xe_bo_evict.o \</div><div class='add'>+	xe_debugfs.o \</div><div class='add'>+	xe_devcoredump.o \</div><div class='add'>+	xe_device.o \</div><div class='add'>+	xe_device_sysfs.o \</div><div class='add'>+	xe_dma_buf.o \</div><div class='add'>+	xe_drm_client.o \</div><div class='add'>+	xe_exec.o \</div><div class='add'>+	xe_execlist.o \</div><div class='add'>+	xe_exec_queue.o \</div><div class='add'>+	xe_force_wake.o \</div><div class='add'>+	xe_ggtt.o \</div><div class='add'>+	xe_gpu_scheduler.o \</div><div class='add'>+	xe_gsc.o \</div><div class='add'>+	xe_gsc_submit.o \</div><div class='add'>+	xe_gt.o \</div><div class='add'>+	xe_gt_ccs_mode.o \</div><div class='add'>+	xe_gt_clock.o \</div><div class='add'>+	xe_gt_debugfs.o \</div><div class='add'>+	xe_gt_freq.o \</div><div class='add'>+	xe_gt_idle.o \</div><div class='add'>+	xe_gt_mcr.o \</div><div class='add'>+	xe_gt_pagefault.o \</div><div class='add'>+	xe_gt_sysfs.o \</div><div class='add'>+	xe_gt_throttle_sysfs.o \</div><div class='add'>+	xe_gt_tlb_invalidation.o \</div><div class='add'>+	xe_gt_topology.o \</div><div class='add'>+	xe_guc.o \</div><div class='add'>+	xe_guc_ads.o \</div><div class='add'>+	xe_guc_ct.o \</div><div class='add'>+	xe_guc_debugfs.o \</div><div class='add'>+	xe_guc_hwconfig.o \</div><div class='add'>+	xe_guc_log.o \</div><div class='add'>+	xe_guc_pc.o \</div><div class='add'>+	xe_guc_submit.o \</div><div class='add'>+	xe_heci_gsc.o \</div><div class='add'>+	xe_hw_engine.o \</div><div class='add'>+	xe_hw_engine_class_sysfs.o \</div><div class='add'>+	xe_hw_fence.o \</div><div class='add'>+	xe_huc.o \</div><div class='add'>+	xe_huc_debugfs.o \</div><div class='add'>+	xe_irq.o \</div><div class='add'>+	xe_lrc.o \</div><div class='add'>+	xe_migrate.o \</div><div class='add'>+	xe_mmio.o \</div><div class='add'>+	xe_mocs.o \</div><div class='add'>+	xe_module.o \</div><div class='add'>+	xe_pat.o \</div><div class='add'>+	xe_pci.o \</div><div class='add'>+	xe_pcode.o \</div><div class='add'>+	xe_pm.o \</div><div class='add'>+	xe_preempt_fence.o \</div><div class='add'>+	xe_pt.o \</div><div class='add'>+	xe_pt_walk.o \</div><div class='add'>+	xe_query.o \</div><div class='add'>+	xe_range_fence.o \</div><div class='add'>+	xe_reg_sr.o \</div><div class='add'>+	xe_reg_whitelist.o \</div><div class='add'>+	xe_rtp.o \</div><div class='add'>+	xe_ring_ops.o \</div><div class='add'>+	xe_sa.o \</div><div class='add'>+	xe_sched_job.o \</div><div class='add'>+	xe_step.o \</div><div class='add'>+	xe_sync.o \</div><div class='add'>+	xe_tile.o \</div><div class='add'>+	xe_tile_sysfs.o \</div><div class='add'>+	xe_trace.o \</div><div class='add'>+	xe_ttm_sys_mgr.o \</div><div class='add'>+	xe_ttm_stolen_mgr.o \</div><div class='add'>+	xe_ttm_vram_mgr.o \</div><div class='add'>+	xe_tuning.o \</div><div class='add'>+	xe_uc.o \</div><div class='add'>+	xe_uc_debugfs.o \</div><div class='add'>+	xe_uc_fw.o \</div><div class='add'>+	xe_vm.o \</div><div class='add'>+	xe_wait_user_fence.o \</div><div class='add'>+	xe_wa.o \</div><div class='add'>+	xe_wopcm.o</div><div class='add'>+</div><div class='add'>+# graphics hardware monitoring (HWMON) support</div><div class='add'>+xe-$(CONFIG_HWMON) += xe_hwmon.o</div><div class='add'>+</div><div class='add'>+# graphics virtualization (SR-IOV) support</div><div class='add'>+xe-y += xe_sriov.o</div><div class='add'>+</div><div class='add'>+xe-$(CONFIG_PCI_IOV) += \</div><div class='add'>+	xe_lmtt.o \</div><div class='add'>+	xe_lmtt_2l.o \</div><div class='add'>+	xe_lmtt_ml.o</div><div class='add'>+</div><div class='add'>+# i915 Display compat #defines and #includes</div><div class='add'>+subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \</div><div class='add'>+	-I$(srctree)/$(src)/display/ext \</div><div class='add'>+	-I$(srctree)/$(src)/compat-i915-headers \</div><div class='add'>+	-I$(srctree)/drivers/gpu/drm/xe/display/ \</div><div class='add'>+	-I$(srctree)/drivers/gpu/drm/i915/display/ \</div><div class='add'>+	-Ddrm_i915_gem_object=xe_bo \</div><div class='add'>+	-Ddrm_i915_private=xe_device</div><div class='add'>+</div><div class='add'>+CFLAGS_i915-display/intel_fbdev.o = $(call cc-disable-warning, override-init)</div><div class='add'>+CFLAGS_i915-display/intel_display_device.o = $(call cc-disable-warning, override-init)</div><div class='add'>+</div><div class='add'>+# Rule to build SOC code shared with i915</div><div class='add'>+$(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE</div><div class='add'>+	$(call cmd,force_checksrc)</div><div class='add'>+	$(call if_changed_rule,cc_o_c)</div><div class='add'>+</div><div class='add'>+# Rule to build display code shared with i915</div><div class='add'>+$(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE</div><div class='add'>+	$(call cmd,force_checksrc)</div><div class='add'>+	$(call if_changed_rule,cc_o_c)</div><div class='add'>+</div><div class='add'>+# Display code specific to xe</div><div class='add'>+xe-$(CONFIG_DRM_XE_DISPLAY) += \</div><div class='add'>+	xe_display.o \</div><div class='add'>+	display/xe_fb_pin.o \</div><div class='add'>+	display/xe_hdcp_gsc.o \</div><div class='add'>+	display/xe_plane_initial.o \</div><div class='add'>+	display/xe_display_rps.o \</div><div class='add'>+	display/xe_display_misc.o \</div><div class='add'>+	display/xe_dsb_buffer.o \</div><div class='add'>+	display/intel_fbdev_fb.o \</div><div class='add'>+	display/intel_fb_bo.o \</div><div class='add'>+	display/ext/i915_irq.o \</div><div class='add'>+	display/ext/i915_utils.o</div><div class='add'>+</div><div class='add'>+# SOC code shared with i915</div><div class='add'>+xe-$(CONFIG_DRM_XE_DISPLAY) += \</div><div class='add'>+	i915-soc/intel_dram.o \</div><div class='add'>+	i915-soc/intel_pch.o</div><div class='add'>+</div><div class='add'>+# Display code shared with i915</div><div class='add'>+xe-$(CONFIG_DRM_XE_DISPLAY) += \</div><div class='add'>+	i915-display/icl_dsi.o \</div><div class='add'>+	i915-display/intel_atomic.o \</div><div class='add'>+	i915-display/intel_atomic_plane.o \</div><div class='add'>+	i915-display/intel_audio.o \</div><div class='add'>+	i915-display/intel_backlight.o \</div><div class='add'>+	i915-display/intel_bios.o \</div><div class='add'>+	i915-display/intel_bw.o \</div><div class='add'>+	i915-display/intel_cdclk.o \</div><div class='add'>+	i915-display/intel_color.o \</div><div class='add'>+	i915-display/intel_combo_phy.o \</div><div class='add'>+	i915-display/intel_connector.o \</div><div class='add'>+	i915-display/intel_crtc.o \</div><div class='add'>+	i915-display/intel_crtc_state_dump.o \</div><div class='add'>+	i915-display/intel_cursor.o \</div><div class='add'>+	i915-display/intel_cx0_phy.o \</div><div class='add'>+	i915-display/intel_ddi.o \</div><div class='add'>+	i915-display/intel_ddi_buf_trans.o \</div><div class='add'>+	i915-display/intel_display.o \</div><div class='add'>+	i915-display/intel_display_debugfs.o \</div><div class='add'>+	i915-display/intel_display_debugfs_params.o \</div><div class='add'>+	i915-display/intel_display_device.o \</div><div class='add'>+	i915-display/intel_display_driver.o \</div><div class='add'>+	i915-display/intel_display_irq.o \</div><div class='add'>+	i915-display/intel_display_params.o \</div><div class='add'>+	i915-display/intel_display_power.o \</div><div class='add'>+	i915-display/intel_display_power_map.o \</div><div class='add'>+	i915-display/intel_display_power_well.o \</div><div class='add'>+	i915-display/intel_display_trace.o \</div><div class='add'>+	i915-display/intel_display_wa.o \</div><div class='add'>+	i915-display/intel_dkl_phy.o \</div><div class='add'>+	i915-display/intel_dmc.o \</div><div class='add'>+	i915-display/intel_dp.o \</div><div class='add'>+	i915-display/intel_dp_aux.o \</div><div class='add'>+	i915-display/intel_dp_aux_backlight.o \</div><div class='add'>+	i915-display/intel_dp_hdcp.o \</div><div class='add'>+	i915-display/intel_dp_link_training.o \</div><div class='add'>+	i915-display/intel_dp_mst.o \</div><div class='add'>+	i915-display/intel_dpll.o \</div><div class='add'>+	i915-display/intel_dpll_mgr.o \</div><div class='add'>+	i915-display/intel_dpt_common.o \</div><div class='add'>+	i915-display/intel_drrs.o \</div><div class='add'>+	i915-display/intel_dsb.o \</div><div class='add'>+	i915-display/intel_dsi.o \</div><div class='add'>+	i915-display/intel_dsi_dcs_backlight.o \</div><div class='add'>+	i915-display/intel_dsi_vbt.o \</div><div class='add'>+	i915-display/intel_fb.o \</div><div class='add'>+	i915-display/intel_fbc.o \</div><div class='add'>+	i915-display/intel_fdi.o \</div><div class='add'>+	i915-display/intel_fifo_underrun.o \</div><div class='add'>+	i915-display/intel_frontbuffer.o \</div><div class='add'>+	i915-display/intel_global_state.o \</div><div class='add'>+	i915-display/intel_gmbus.o \</div><div class='add'>+	i915-display/intel_hdcp.o \</div><div class='add'>+	i915-display/intel_hdmi.o \</div><div class='add'>+	i915-display/intel_hotplug.o \</div><div class='add'>+	i915-display/intel_hotplug_irq.o \</div><div class='add'>+	i915-display/intel_hti.o \</div><div class='add'>+	i915-display/intel_link_bw.o \</div><div class='add'>+	i915-display/intel_lspcon.o \</div><div class='add'>+	i915-display/intel_modeset_lock.o \</div><div class='add'>+	i915-display/intel_modeset_setup.o \</div><div class='add'>+	i915-display/intel_modeset_verify.o \</div><div class='add'>+	i915-display/intel_panel.o \</div><div class='add'>+	i915-display/intel_pipe_crc.o \</div><div class='add'>+	i915-display/intel_pmdemand.o \</div><div class='add'>+	i915-display/intel_pps.o \</div><div class='add'>+	i915-display/intel_psr.o \</div><div class='add'>+	i915-display/intel_qp_tables.o \</div><div class='add'>+	i915-display/intel_quirks.o \</div><div class='add'>+	i915-display/intel_snps_phy.o \</div><div class='add'>+	i915-display/intel_tc.o \</div><div class='add'>+	i915-display/intel_vblank.o \</div><div class='add'>+	i915-display/intel_vdsc.o \</div><div class='add'>+	i915-display/intel_vga.o \</div><div class='add'>+	i915-display/intel_vrr.o \</div><div class='add'>+	i915-display/intel_wm.o \</div><div class='add'>+	i915-display/skl_scaler.o \</div><div class='add'>+	i915-display/skl_universal_plane.o \</div><div class='add'>+	i915-display/skl_watermark.o</div><div class='add'>+</div><div class='add'>+ifeq ($(CONFIG_ACPI),y)</div><div class='add'>+	xe-$(CONFIG_DRM_XE_DISPLAY) += \</div><div class='add'>+		i915-display/intel_acpi.o \</div><div class='add'>+		i915-display/intel_opregion.o</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+ifeq ($(CONFIG_DRM_FBDEV_EMULATION),y)</div><div class='add'>+	xe-$(CONFIG_DRM_XE_DISPLAY) += i915-display/intel_fbdev.o</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_DRM_XE) += xe.o</div><div class='add'>+obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/</div><div class='add'>+</div><div class='add'>+# header test</div><div class='add'>+hdrtest_find_args := -not -path xe_rtp_helpers.h</div><div class='add'>+ifneq ($(CONFIG_DRM_XE_DISPLAY),y)</div><div class='add'>+	hdrtest_find_args += -not -path display/\* -not -path compat-i915-headers/\* -not -path xe_display.h</div><div class='add'>+endif</div><div class='add'>+</div><div class='add'>+always-$(CONFIG_DRM_XE_WERROR) += \</div><div class='add'>+	$(patsubst %.h,%.hdrtest, $(shell cd $(srctree)/$(src) &amp;&amp; find * -name '*.h' $(hdrtest_find_args)))</div><div class='add'>+</div><div class='add'>+quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)</div><div class='add'>+      cmd_hdrtest = $(CC) -DHDRTEST $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $&lt;; touch $@</div><div class='add'>+</div><div class='add'>+$(obj)/%.hdrtest: $(src)/%.h FORCE</div><div class='add'>+	$(call if_changed_dep,hdrtest)</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/gsc_command_header_abi.h b/drivers/gpu/drm/xe/abi/gsc_command_header_abi.h<br/>new file mode 100644<br/>index 000000000000..a4c2646803b5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/gsc_command_header_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_command_header_abi.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GSC_COMMAND_HEADER_ABI_H</div><div class='add'>+#define _ABI_GSC_COMMAND_HEADER_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct intel_gsc_mtl_header {</div><div class='add'>+	u32 validity_marker;</div><div class='add'>+#define GSC_HECI_VALIDITY_MARKER 0xA578875A</div><div class='add'>+</div><div class='add'>+	u8 heci_client_id;</div><div class='add'>+</div><div class='add'>+	u8 reserved1;</div><div class='add'>+</div><div class='add'>+	u16 header_version;</div><div class='add'>+#define MTL_GSC_HEADER_VERSION 1</div><div class='add'>+</div><div class='add'>+	/* FW allows host to decide host_session handle as it sees fit. */</div><div class='add'>+	u64 host_session_handle;</div><div class='add'>+</div><div class='add'>+	/* handle generated by FW for messages that need to be re-submitted */</div><div class='add'>+	u64 gsc_message_handle;</div><div class='add'>+</div><div class='add'>+	u32 message_size; /* lower 20 bits only, upper 12 are reserved */</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Flags mask:</div><div class='add'>+	 * Bit 0: Pending</div><div class='add'>+	 * Bit 1: Session Cleanup;</div><div class='add'>+	 * Bits 2-15: Flags</div><div class='add'>+	 * Bits 16-31: Extension Size</div><div class='add'>+	 * According to internal spec flags are either input or output</div><div class='add'>+	 * we distinguish the flags using OUTFLAG or INFLAG</div><div class='add'>+	 */</div><div class='add'>+	u32 flags;</div><div class='add'>+#define GSC_OUTFLAG_MSG_PENDING	BIT(0)</div><div class='add'>+#define GSC_INFLAG_MSG_CLEANUP	BIT(1)</div><div class='add'>+</div><div class='add'>+	u32 status;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h b/drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h<br/>new file mode 100644<br/>index 000000000000..ad4d041873ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GSC_MKHI_COMMANDS_ABI_H</div><div class='add'>+#define _ABI_GSC_MKHI_COMMANDS_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/* Heci client ID for MKHI commands */</div><div class='add'>+#define HECI_MEADDRESS_MKHI 7</div><div class='add'>+</div><div class='add'>+/* Generic MKHI header */</div><div class='add'>+struct gsc_mkhi_header {</div><div class='add'>+	u8  group_id;</div><div class='add'>+	u8  command;</div><div class='add'>+	u8  reserved;</div><div class='add'>+	u8  result;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* GFX_SRV commands */</div><div class='add'>+#define MKHI_GROUP_ID_GFX_SRV 0x30</div><div class='add'>+</div><div class='add'>+#define MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION (0x42)</div><div class='add'>+</div><div class='add'>+struct gsc_get_compatibility_version_in {</div><div class='add'>+	struct gsc_mkhi_header header;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_get_compatibility_version_out {</div><div class='add'>+	struct gsc_mkhi_header header;</div><div class='add'>+	u16 proj_major;</div><div class='add'>+	u16 compat_major;</div><div class='add'>+	u16 compat_minor;</div><div class='add'>+	u16 reserved[5];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h b/drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h<br/>new file mode 100644<br/>index 000000000000..57520809e48d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/gsc_pxp_commands_abi.h</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GSC_PXP_COMMANDS_ABI_H</div><div class='add'>+#define _ABI_GSC_PXP_COMMANDS_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/* Heci client ID for PXP commands */</div><div class='add'>+#define HECI_MEADDRESS_PXP 17</div><div class='add'>+</div><div class='add'>+#define PXP_APIVER(x, y) (((x) &amp; 0xFFFF) &lt;&lt; 16 | ((y) &amp; 0xFFFF))</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * there are a lot of status codes for PXP, but we only define the cross-API</div><div class='add'>+ * common ones that we actually can handle in the kernel driver. Other failure</div><div class='add'>+ * codes should be printed to error msg for debug.</div><div class='add'>+ */</div><div class='add'>+enum pxp_status {</div><div class='add'>+	PXP_STATUS_SUCCESS = 0x0,</div><div class='add'>+	PXP_STATUS_ERROR_API_VERSION = 0x1002,</div><div class='add'>+	PXP_STATUS_NOT_READY = 0x100e,</div><div class='add'>+	PXP_STATUS_PLATFCONFIG_KF1_NOVERIF = 0x101a,</div><div class='add'>+	PXP_STATUS_PLATFCONFIG_KF1_BAD = 0x101f,</div><div class='add'>+	PXP_STATUS_OP_NOT_PERMITTED = 0x4013</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Common PXP FW message header */</div><div class='add'>+struct pxp_cmd_header {</div><div class='add'>+	u32 api_version;</div><div class='add'>+	u32 command_id;</div><div class='add'>+	union {</div><div class='add'>+		u32 status; /* out */</div><div class='add'>+		u32 stream_id; /* in */</div><div class='add'>+#define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)</div><div class='add'>+#define PXP_CMDHDR_EXTDATA_APP_TYPE GENMASK(1, 1)</div><div class='add'>+#define PXP_CMDHDR_EXTDATA_SESSION_ID GENMASK(17, 2)</div><div class='add'>+	};</div><div class='add'>+	/* Length of the message (excluding the header) */</div><div class='add'>+	u32 buffer_len;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */</div><div class='add'>+</div><div class='add'>+/* PXP-Input-Packet: HUC Auth-only */</div><div class='add'>+struct pxp43_new_huc_auth_in {</div><div class='add'>+	struct pxp_cmd_header header;</div><div class='add'>+	u64 huc_base_address;</div><div class='add'>+	u32 huc_size;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* PXP-Output-Packet: HUC Load and Authentication or Auth-only */</div><div class='add'>+struct pxp43_huc_auth_out {</div><div class='add'>+	struct pxp_cmd_header header;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h<br/>new file mode 100644<br/>index 000000000000..3062e0e0d467<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_actions_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_actions_abi.h</a></div><div class='hunk'>@@ -0,0 +1,219 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2014-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_ACTIONS_ABI_H</div><div class='add'>+#define _ABI_GUC_ACTIONS_ABI_H</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HOST2GUC_SELF_CFG</div><div class='add'>+ *</div><div class='add'>+ * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_.</div><div class='add'>+ *</div><div class='add'>+ * This message must be sent as `MMIO HXG Message`_.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | DATA0 = MBZ                                                  |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508            |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_           |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | **KLV_LEN** - KLV length                                     |</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  |   |       |   - 32 bit KLV = 1                                           |</div><div class='add'>+ *  |   |       |   - 64 bit KLV = 2                                           |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 2 |  31:0 | **VALUE32** - Bits 31-0 of the KLV value                     |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 3 |  31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2)  |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized   |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+#define GUC_ACTION_HOST2GUC_SELF_CFG			0x0508</div><div class='add'>+</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffff &lt;&lt; 16)</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffff &lt;&lt; 0)</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32		GUC_HXG_REQUEST_MSG_n_DATAn</div><div class='add'>+#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64		GUC_HXG_REQUEST_MSG_n_DATAn</div><div class='add'>+</div><div class='add'>+#define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN</div><div class='add'>+#define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM		GUC_HXG_RESPONSE_MSG_0_DATA0</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HOST2GUC_CONTROL_CTB</div><div class='add'>+ *</div><div class='add'>+ * This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_.</div><div class='add'>+ *</div><div class='add'>+ * This message must be sent as `MMIO HXG Message`_.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | DATA0 = MBZ                                                  |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509         |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 | **CONTROL** - control `CTB based communication`_             |</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_CONTROL_DISABLE` = 0                           |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_CONTROL_ENABLE` = 1                            |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | DATA0 = MBZ                                                  |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+#define GUC_ACTION_HOST2GUC_CONTROL_CTB			0x4509</div><div class='add'>+</div><div class='add'>+#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)</div><div class='add'>+#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0</div><div class='add'>+#define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL	GUC_HXG_REQUEST_MSG_n_DATAn</div><div class='add'>+#define   GUC_CTB_CONTROL_DISABLE			0u</div><div class='add'>+#define   GUC_CTB_CONTROL_ENABLE			1u</div><div class='add'>+</div><div class='add'>+#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN</div><div class='add'>+#define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ		GUC_HXG_RESPONSE_MSG_0_DATA0</div><div class='add'>+</div><div class='add'>+/* legacy definitions */</div><div class='add'>+</div><div class='add'>+enum xe_guc_action {</div><div class='add'>+	XE_GUC_ACTION_DEFAULT = 0x0,</div><div class='add'>+	XE_GUC_ACTION_REQUEST_PREEMPTION = 0x2,</div><div class='add'>+	XE_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,</div><div class='add'>+	XE_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,</div><div class='add'>+	XE_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,</div><div class='add'>+	XE_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,</div><div class='add'>+	XE_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,</div><div class='add'>+	XE_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,</div><div class='add'>+	XE_GUC_ACTION_ENTER_S_STATE = 0x501,</div><div class='add'>+	XE_GUC_ACTION_EXIT_S_STATE = 0x502,</div><div class='add'>+	XE_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,</div><div class='add'>+	XE_GUC_ACTION_SCHED_CONTEXT = 0x1000,</div><div class='add'>+	XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,</div><div class='add'>+	XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,</div><div class='add'>+	XE_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,</div><div class='add'>+	XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,</div><div class='add'>+	XE_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,</div><div class='add'>+	XE_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,</div><div class='add'>+	XE_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,</div><div class='add'>+	XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,</div><div class='add'>+	XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,</div><div class='add'>+	XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,</div><div class='add'>+	XE_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,</div><div class='add'>+	XE_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,</div><div class='add'>+	XE_GUC_ACTION_GET_HWCONFIG = 0x4100,</div><div class='add'>+	XE_GUC_ACTION_REGISTER_CONTEXT = 0x4502,</div><div class='add'>+	XE_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,</div><div class='add'>+	XE_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,</div><div class='add'>+	XE_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,</div><div class='add'>+	XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,</div><div class='add'>+	XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,</div><div class='add'>+	XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,</div><div class='add'>+	XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,</div><div class='add'>+	XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,</div><div class='add'>+	XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,</div><div class='add'>+	XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,</div><div class='add'>+	XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY = 0x6004,</div><div class='add'>+	XE_GUC_ACTION_TLB_INVALIDATION = 0x7000,</div><div class='add'>+	XE_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001,</div><div class='add'>+	XE_GUC_ACTION_TLB_INVALIDATION_ALL = 0x7002,</div><div class='add'>+	XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,</div><div class='add'>+	XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,</div><div class='add'>+	XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,</div><div class='add'>+	XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005,</div><div class='add'>+	XE_GUC_ACTION_LIMIT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_rc_options {</div><div class='add'>+	XE_GUCRC_HOST_CONTROL,</div><div class='add'>+	XE_GUCRC_FIRMWARE_CONTROL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_preempt_options {</div><div class='add'>+	XE_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,</div><div class='add'>+	XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_report_status {</div><div class='add'>+	XE_GUC_REPORT_STATUS_UNKNOWN = 0x0,</div><div class='add'>+	XE_GUC_REPORT_STATUS_ACKED = 0x1,</div><div class='add'>+	XE_GUC_REPORT_STATUS_ERROR = 0x2,</div><div class='add'>+	XE_GUC_REPORT_STATUS_COMPLETE = 0x4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_sleep_state_status {</div><div class='add'>+	XE_GUC_SLEEP_STATE_SUCCESS = 0x1,</div><div class='add'>+	XE_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,</div><div class='add'>+	XE_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3</div><div class='add'>+#define XE_GUC_SLEEP_STATE_INVALID_MASK 0x80000000</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GUC_LOG_CONTROL_LOGGING_ENABLED	(1 &lt;&lt; 0)</div><div class='add'>+#define GUC_LOG_CONTROL_VERBOSITY_SHIFT	4</div><div class='add'>+#define GUC_LOG_CONTROL_VERBOSITY_MASK	(0xF &lt;&lt; GUC_LOG_CONTROL_VERBOSITY_SHIFT)</div><div class='add'>+#define GUC_LOG_CONTROL_DEFAULT_LOGGING	(1 &lt;&lt; 8)</div><div class='add'>+</div><div class='add'>+#define XE_GUC_TLB_INVAL_TYPE_SHIFT 0</div><div class='add'>+#define XE_GUC_TLB_INVAL_MODE_SHIFT 8</div><div class='add'>+/* Flush PPC or SMRO caches along with TLB invalidation request */</div><div class='add'>+#define XE_GUC_TLB_INVAL_FLUSH_CACHE (1 &lt;&lt; 31)</div><div class='add'>+</div><div class='add'>+enum xe_guc_tlb_invalidation_type {</div><div class='add'>+	XE_GUC_TLB_INVAL_FULL = 0x0,</div><div class='add'>+	XE_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1,</div><div class='add'>+	XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2,</div><div class='add'>+	XE_GUC_TLB_INVAL_GUC = 0x3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * 0: Heavy mode of Invalidation:</div><div class='add'>+ * The pipeline of the engine(s) for which the invalidation is targeted to is</div><div class='add'>+ * blocked, and all the in-flight transactions are guaranteed to be Globally</div><div class='add'>+ * Observed before completing the TLB invalidation</div><div class='add'>+ * 1: Lite mode of Invalidation:</div><div class='add'>+ * TLBs of the targeted engine(s) are immediately invalidated.</div><div class='add'>+ * In-flight transactions are NOT guaranteed to be Globally Observed before</div><div class='add'>+ * completing TLB invalidation.</div><div class='add'>+ * Light Invalidation Mode is to be used only when</div><div class='add'>+ * it can be guaranteed (by SW) that the address translations remain invariant</div><div class='add'>+ * for the in-flight transactions across the TLB invalidation. In other words,</div><div class='add'>+ * this mode can be used when the TLB invalidation is intended to clear out the</div><div class='add'>+ * stale cached translations that are no longer in use. Light Invalidation Mode</div><div class='add'>+ * is much faster than the Heavy Invalidation Mode, as it does not wait for the</div><div class='add'>+ * in-flight transactions to be GOd.</div><div class='add'>+ */</div><div class='add'>+enum xe_guc_tlb_inval_mode {</div><div class='add'>+	XE_GUC_TLB_INVAL_MODE_HEAVY = 0x0,</div><div class='add'>+	XE_GUC_TLB_INVAL_MODE_LITE = 0x1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h<br/>new file mode 100644<br/>index 000000000000..811add10c30d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h</a></div><div class='hunk'>@@ -0,0 +1,249 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _GUC_ACTIONS_SLPC_ABI_H_</div><div class='add'>+#define _GUC_ACTIONS_SLPC_ABI_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: SLPC SHARED DATA STRUCTURE</div><div class='add'>+ *</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ *  | CL | Bytes| Description                                                  |</div><div class='add'>+ *  +====+======+==============================================================+</div><div class='add'>+ *  | 1  | 0-3  | SHARED DATA SIZE                                             |</div><div class='add'>+ *  |    +------+--------------------------------------------------------------+</div><div class='add'>+ *  |    | 4-7  | GLOBAL STATE                                                 |</div><div class='add'>+ *  |    +------+--------------------------------------------------------------+</div><div class='add'>+ *  |    | 8-11 | DISPLAY DATA ADDRESS                                         |</div><div class='add'>+ *  |    +------+--------------------------------------------------------------+</div><div class='add'>+ *  |    | 12:63| PADDING                                                      |</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ *  |    | 0:63 | PADDING(PLATFORM INFO)                                       |</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ *  | 3  | 0-3  | TASK STATE DATA                                              |</div><div class='add'>+ *  +    +------+--------------------------------------------------------------+</div><div class='add'>+ *  |    | 4:63 | PADDING                                                      |</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ *  |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS                               |</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ *  |    |      | PADDING + EXTRA RESERVED PAGE                                |</div><div class='add'>+ *  +----+------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SLPC exposes certain parameters for global configuration by the host.</div><div class='add'>+ * These are referred to as override parameters, because in most cases</div><div class='add'>+ * the host will not need to modify the default values used by SLPC.</div><div class='add'>+ * SLPC remembers the default values which allows the host to easily restore</div><div class='add'>+ * them by simply unsetting the override. The host can set or unset override</div><div class='add'>+ * parameters during SLPC (re-)initialization using the SLPC Reset event.</div><div class='add'>+ * The host can also set or unset override parameters on the fly using the</div><div class='add'>+ * Parameter Set and Parameter Unset events</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define SLPC_MAX_OVERRIDE_PARAMETERS		256</div><div class='add'>+#define SLPC_OVERRIDE_BITFIELD_SIZE \</div><div class='add'>+		(SLPC_MAX_OVERRIDE_PARAMETERS / 32)</div><div class='add'>+</div><div class='add'>+#define SLPC_PAGE_SIZE_BYTES			4096</div><div class='add'>+#define SLPC_CACHELINE_SIZE_BYTES		64</div><div class='add'>+#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER	SLPC_CACHELINE_SIZE_BYTES</div><div class='add'>+#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO	SLPC_CACHELINE_SIZE_BYTES</div><div class='add'>+#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE	SLPC_CACHELINE_SIZE_BYTES</div><div class='add'>+#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE	SLPC_PAGE_SIZE_BYTES</div><div class='add'>+#define SLPC_SHARED_DATA_SIZE_BYTE_MAX		(2 * SLPC_PAGE_SIZE_BYTES)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Cacheline size aligned (Total size needed for</div><div class='add'>+ * SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)</div><div class='add'>+ */</div><div class='add'>+#define SLPC_OVERRIDE_PARAMS_TOTAL_BYTES	(((((SLPC_MAX_OVERRIDE_PARAMETERS * 4) \</div><div class='add'>+						+ ((SLPC_MAX_OVERRIDE_PARAMETERS / 32) * 4)) \</div><div class='add'>+		+ (SLPC_CACHELINE_SIZE_BYTES - 1)) / SLPC_CACHELINE_SIZE_BYTES) * \</div><div class='add'>+					SLPC_CACHELINE_SIZE_BYTES)</div><div class='add'>+</div><div class='add'>+#define SLPC_SHARED_DATA_SIZE_BYTE_OTHER	(SLPC_SHARED_DATA_SIZE_BYTE_MAX - \</div><div class='add'>+					(SLPC_SHARED_DATA_SIZE_BYTE_HEADER \</div><div class='add'>+					+ SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO \</div><div class='add'>+					+ SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE \</div><div class='add'>+					+ SLPC_OVERRIDE_PARAMS_TOTAL_BYTES \</div><div class='add'>+					+ SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE))</div><div class='add'>+</div><div class='add'>+enum slpc_task_enable {</div><div class='add'>+	SLPC_PARAM_TASK_DEFAULT = 0,</div><div class='add'>+	SLPC_PARAM_TASK_ENABLED,</div><div class='add'>+	SLPC_PARAM_TASK_DISABLED,</div><div class='add'>+	SLPC_PARAM_TASK_UNKNOWN</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum slpc_global_state {</div><div class='add'>+	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,</div><div class='add'>+	SLPC_GLOBAL_STATE_INITIALIZING = 1,</div><div class='add'>+	SLPC_GLOBAL_STATE_RESETTING = 2,</div><div class='add'>+	SLPC_GLOBAL_STATE_RUNNING = 3,</div><div class='add'>+	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,</div><div class='add'>+	SLPC_GLOBAL_STATE_ERROR = 5</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum slpc_param_id {</div><div class='add'>+	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,</div><div class='add'>+	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,</div><div class='add'>+	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,</div><div class='add'>+	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,</div><div class='add'>+	SLPC_PARAM_TASK_ENABLE_DCC = 4,</div><div class='add'>+	SLPC_PARAM_TASK_DISABLE_DCC = 5,</div><div class='add'>+	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,</div><div class='add'>+	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,</div><div class='add'>+	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,</div><div class='add'>+	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,</div><div class='add'>+	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,</div><div class='add'>+	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,</div><div class='add'>+	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,</div><div class='add'>+	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,</div><div class='add'>+	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,</div><div class='add'>+	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,</div><div class='add'>+	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,</div><div class='add'>+	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,</div><div class='add'>+	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,</div><div class='add'>+	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,</div><div class='add'>+	SLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,</div><div class='add'>+	SLPC_PARAM_PWRGATE_RC_MODE = 21,</div><div class='add'>+	SLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,</div><div class='add'>+	SLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,</div><div class='add'>+	SLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,</div><div class='add'>+	SLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,</div><div class='add'>+	SLPC_PARAM_STRATEGIES = 26,</div><div class='add'>+	SLPC_PARAM_POWER_PROFILE = 27,</div><div class='add'>+	SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,</div><div class='add'>+	SLPC_MAX_PARAM = 32,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum slpc_media_ratio_mode {</div><div class='add'>+	SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,</div><div class='add'>+	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,</div><div class='add'>+	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum slpc_gucrc_mode {</div><div class='add'>+	SLPC_GUCRC_MODE_HW = 0,</div><div class='add'>+	SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,</div><div class='add'>+	SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,</div><div class='add'>+	SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,</div><div class='add'>+</div><div class='add'>+	SLPC_GUCRC_MODE_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum slpc_event_id {</div><div class='add'>+	SLPC_EVENT_RESET = 0,</div><div class='add'>+	SLPC_EVENT_SHUTDOWN = 1,</div><div class='add'>+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,</div><div class='add'>+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,</div><div class='add'>+	SLPC_EVENT_FLIP_COMPLETE = 4,</div><div class='add'>+	SLPC_EVENT_QUERY_TASK_STATE = 5,</div><div class='add'>+	SLPC_EVENT_PARAMETER_SET = 6,</div><div class='add'>+	SLPC_EVENT_PARAMETER_UNSET = 7,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct slpc_task_state_data {</div><div class='add'>+	union {</div><div class='add'>+		u32 task_status_padding;</div><div class='add'>+		struct {</div><div class='add'>+			u32 status;</div><div class='add'>+#define SLPC_GTPERF_TASK_ENABLED	REG_BIT(0)</div><div class='add'>+#define SLPC_DCC_TASK_ENABLED		REG_BIT(11)</div><div class='add'>+#define SLPC_IN_DCC			REG_BIT(12)</div><div class='add'>+#define SLPC_BALANCER_ENABLED		REG_BIT(15)</div><div class='add'>+#define SLPC_IBC_TASK_ENABLED		REG_BIT(16)</div><div class='add'>+#define SLPC_BALANCER_IA_LMT_ENABLED	REG_BIT(17)</div><div class='add'>+#define SLPC_BALANCER_IA_LMT_ACTIVE	REG_BIT(18)</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+	union {</div><div class='add'>+		u32 freq_padding;</div><div class='add'>+		struct {</div><div class='add'>+#define SLPC_MAX_UNSLICE_FREQ_MASK	REG_GENMASK(7, 0)</div><div class='add'>+#define SLPC_MIN_UNSLICE_FREQ_MASK	REG_GENMASK(15, 8)</div><div class='add'>+#define SLPC_MAX_SLICE_FREQ_MASK	REG_GENMASK(23, 16)</div><div class='add'>+#define SLPC_MIN_SLICE_FREQ_MASK	REG_GENMASK(31, 24)</div><div class='add'>+			u32 freq;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct slpc_shared_data_header {</div><div class='add'>+	/* Total size in bytes of this shared buffer. */</div><div class='add'>+	u32 size;</div><div class='add'>+	u32 global_state;</div><div class='add'>+	u32 display_data_addr;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct slpc_override_params {</div><div class='add'>+	u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];</div><div class='add'>+	u32 values[SLPC_MAX_OVERRIDE_PARAMETERS];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct slpc_shared_data {</div><div class='add'>+	struct slpc_shared_data_header header;</div><div class='add'>+	u8 shared_data_header_pad[SLPC_SHARED_DATA_SIZE_BYTE_HEADER -</div><div class='add'>+				sizeof(struct slpc_shared_data_header)];</div><div class='add'>+</div><div class='add'>+	u8 platform_info_pad[SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO];</div><div class='add'>+</div><div class='add'>+	struct slpc_task_state_data task_state_data;</div><div class='add'>+	u8 task_state_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE -</div><div class='add'>+				sizeof(struct slpc_task_state_data)];</div><div class='add'>+</div><div class='add'>+	struct slpc_override_params override_params;</div><div class='add'>+	u8 override_params_pad[SLPC_OVERRIDE_PARAMS_TOTAL_BYTES -</div><div class='add'>+				sizeof(struct slpc_override_params)];</div><div class='add'>+</div><div class='add'>+	u8 shared_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_OTHER];</div><div class='add'>+</div><div class='add'>+	/* PAGE 2 (4096 bytes), mode based parameter will be removed soon */</div><div class='add'>+	u8 reserved_mode_definition[4096];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: SLPC H2G MESSAGE FORMAT</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | DATA0 = MBZ                                                  |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_PC_SLPM_REQUEST` = 0x3003     |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:8 | **EVENT_ID**                                                 |</div><div class='add'>+ *  +   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |   7:0 | **EVENT_ARGC** - number of data arguments                    |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 2 |  31:0 | **EVENT_DATA1**                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |...|  31:0 | ...                                                          |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |2+n|  31:0 | **EVENT_DATAn**                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST		0x3003</div><div class='add'>+</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_MIN_LEN \</div><div class='add'>+				(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)</div><div class='add'>+#define HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS		9</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_MAX_LEN \</div><div class='add'>+		(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \</div><div class='add'>+			HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID		(0xff &lt;&lt; 8)</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC	(0xff &lt;&lt; 0)</div><div class='add'>+#define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N	GUC_HXG_REQUEST_MSG_n_DATAn</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h b/drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h<br/>new file mode 100644<br/>index 000000000000..3b83f907ece4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h</a></div><div class='hunk'>@@ -0,0 +1,127 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2014-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_COMMUNICATION_CTB_ABI_H</div><div class='add'>+#define _ABI_GUC_COMMUNICATION_CTB_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/build_bug.h&gt;</div><div class='add'>+</div><div class='add'>+#include "guc_messages_abi.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CT Buffer</div><div class='add'>+ *</div><div class='add'>+ * Circular buffer used to send `CTB Message`_</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CTB Descriptor</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |  31:0 | **HEAD** - offset (in dwords) to the last dword that was     |</div><div class='add'>+ *  |   |       | read from the `CT Buffer`_.                                  |</div><div class='add'>+ *  |   |       | It can only be updated by the receiver.                      |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 | **TAIL** - offset (in dwords) to the last dword that was     |</div><div class='add'>+ *  |   |       | written to the `CT Buffer`_.                                 |</div><div class='add'>+ *  |   |       | It can only be updated by the sender.                        |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 2 |  31:0 | **STATUS** - status of the CTB                               |</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)        |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)     |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)      |</div><div class='add'>+ *  |   |       |   - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)      |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |...|       | RESERVED = MBZ                                               |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 15|  31:0 | RESERVED = MBZ                                               |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct guc_ct_buffer_desc {</div><div class='add'>+	u32 head;</div><div class='add'>+	u32 tail;</div><div class='add'>+	u32 status;</div><div class='add'>+#define GUC_CTB_STATUS_NO_ERROR				0</div><div class='add'>+#define GUC_CTB_STATUS_OVERFLOW				(1 &lt;&lt; 0)</div><div class='add'>+#define GUC_CTB_STATUS_UNDERFLOW			(1 &lt;&lt; 1)</div><div class='add'>+#define GUC_CTB_STATUS_MISMATCH				(1 &lt;&lt; 2)</div><div class='add'>+	u32 reserved[13];</div><div class='add'>+} __packed;</div><div class='add'>+static_assert(sizeof(struct guc_ct_buffer_desc) == 64);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CTB Message</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 | 31:16 | **FENCE** - message identifier                               |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 15:12 | **FORMAT** - format of the CTB message                       |</div><div class='add'>+ *  |   |       |  - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  11:8 | **RESERVED**                                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |   7:0 | **NUM_DWORDS** - length of the CTB message (w/o header)      |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 | optional (depends on FORMAT)                                 |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_CTB_HDR_LEN				1u</div><div class='add'>+#define GUC_CTB_MSG_MIN_LEN			GUC_CTB_HDR_LEN</div><div class='add'>+#define GUC_CTB_MSG_MAX_LEN			256u</div><div class='add'>+#define GUC_CTB_MSG_0_FENCE			(0xffff &lt;&lt; 16)</div><div class='add'>+#define GUC_CTB_MSG_0_FORMAT			(0xf &lt;&lt; 12)</div><div class='add'>+#define   GUC_CTB_FORMAT_HXG			0u</div><div class='add'>+#define GUC_CTB_MSG_0_RESERVED			(0xf &lt;&lt; 8)</div><div class='add'>+#define GUC_CTB_MSG_0_NUM_DWORDS		(0xff &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CTB HXG Message</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 | 31:16 | FENCE                                                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  11:8 | RESERVED = MBZ                                               |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |   7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message  |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | [Embedded `HXG Message`_]                                    |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_CTB_HXG_MSG_MIN_LEN		(GUC_CTB_MSG_MIN_LEN + GUC_HXG_MSG_MIN_LEN)</div><div class='add'>+#define GUC_CTB_HXG_MSG_MAX_LEN		GUC_CTB_MSG_MAX_LEN</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CTB based communication</div><div class='add'>+ *</div><div class='add'>+ * The CTB (command transport buffer) communication between Host and GuC</div><div class='add'>+ * is based on u32 data stream written to the shared buffer. One buffer can</div><div class='add'>+ * be used to transmit data only in one direction (one-directional channel).</div><div class='add'>+ *</div><div class='add'>+ * Current status of the each buffer is maintained in the `CTB Descriptor`_.</div><div class='add'>+ * Each message in data stream is encoded as `CTB HXG Message`_.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h b/drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h<br/>new file mode 100644<br/>index 000000000000..ef538e34f894<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2014-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_COMMUNICATION_MMIO_ABI_H</div><div class='add'>+#define _ABI_GUC_COMMUNICATION_MMIO_ABI_H</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC MMIO based communication</div><div class='add'>+ *</div><div class='add'>+ * The MMIO based communication between Host and GuC relies on special</div><div class='add'>+ * hardware registers which format could be defined by the software</div><div class='add'>+ * (so called scratch registers).</div><div class='add'>+ *</div><div class='add'>+ * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)</div><div class='add'>+ * messages, which maximum length depends on number of available scratch</div><div class='add'>+ * registers, is directly written into those scratch registers.</div><div class='add'>+ *</div><div class='add'>+ * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,</div><div class='add'>+ * but no H2G command takes more than 4 parameters and the GuC firmware</div><div class='add'>+ * itself uses an 4-element array to store the H2G message.</div><div class='add'>+ *</div><div class='add'>+ * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which</div><div class='add'>+ * are, regardless on lower count, preferred over legacy ones.</div><div class='add'>+ *</div><div class='add'>+ * The MMIO based communication is mainly used during driver initialization</div><div class='add'>+ * phase to setup the `CTB based communication`_ that will be used afterwards.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_MAX_MMIO_MSG_LEN		4</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: MMIO HXG Message</div><div class='add'>+ *</div><div class='add'>+ * Format of the MMIO messages follows definitions of `HXG Message`_.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | [Embedded `HXG Message`_]                                    |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_errors_abi.h b/drivers/gpu/drm/xe/abi/guc_errors_abi.h<br/>new file mode 100644<br/>index 000000000000..ec83551bf9c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_errors_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_errors_abi.h</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2014-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_ERRORS_ABI_H</div><div class='add'>+#define _ABI_GUC_ERRORS_ABI_H</div><div class='add'>+</div><div class='add'>+enum xe_guc_response_status {</div><div class='add'>+	XE_GUC_RESPONSE_STATUS_SUCCESS = 0x0,</div><div class='add'>+	XE_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_load_status {</div><div class='add'>+	XE_GUC_LOAD_STATUS_DEFAULT                          = 0x00,</div><div class='add'>+	XE_GUC_LOAD_STATUS_START                            = 0x01,</div><div class='add'>+	XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH       = 0x02,</div><div class='add'>+	XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH       = 0x03,</div><div class='add'>+	XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE      = 0x04,</div><div class='add'>+	XE_GUC_LOAD_STATUS_GDT_DONE                         = 0x10,</div><div class='add'>+	XE_GUC_LOAD_STATUS_IDT_DONE                         = 0x20,</div><div class='add'>+	XE_GUC_LOAD_STATUS_LAPIC_DONE                       = 0x30,</div><div class='add'>+	XE_GUC_LOAD_STATUS_GUCINT_DONE                      = 0x40,</div><div class='add'>+	XE_GUC_LOAD_STATUS_DPC_READY                        = 0x50,</div><div class='add'>+	XE_GUC_LOAD_STATUS_DPC_ERROR                        = 0x60,</div><div class='add'>+	XE_GUC_LOAD_STATUS_EXCEPTION                        = 0x70,</div><div class='add'>+	XE_GUC_LOAD_STATUS_INIT_DATA_INVALID                = 0x71,</div><div class='add'>+	XE_GUC_LOAD_STATUS_PXP_TEARDOWN_CTRL_ENABLED        = 0x72,</div><div class='add'>+	XE_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_START,</div><div class='add'>+	XE_GUC_LOAD_STATUS_MPU_DATA_INVALID                 = 0x73,</div><div class='add'>+	XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID   = 0x74,</div><div class='add'>+	XE_GUC_LOAD_STATUS_INVALID_INIT_DATA_RANGE_END,</div><div class='add'>+</div><div class='add'>+	XE_GUC_LOAD_STATUS_READY                            = 0xF0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h<br/>new file mode 100644<br/>index 000000000000..47094b9b044c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_klvs_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_klvs_abi.h</a></div><div class='hunk'>@@ -0,0 +1,322 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_KLVS_ABI_H</div><div class='add'>+#define _ABI_GUC_KLVS_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC KLV</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 | 31:16 | **KEY** - KLV key identifier                                 |</div><div class='add'>+ *  |   |       |   - `GuC Self Config KLVs`_                                  |</div><div class='add'>+ *  |   |       |   - `GuC VGT Policy KLVs`_                                   |</div><div class='add'>+ *  |   |       |   - `GuC VF Configuration KLVs`_                             |</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | **LEN** - length of VALUE (in 32bit dwords)                  |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 | **VALUE** - actual value of the KLV (format depends on KEY)  |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_LEN_MIN				1u</div><div class='add'>+#define GUC_KLV_0_KEY				(0xffff &lt;&lt; 16)</div><div class='add'>+#define GUC_KLV_0_LEN				(0xffff &lt;&lt; 0)</div><div class='add'>+#define GUC_KLV_n_VALUE				(0xffffffff &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC Self Config KLVs</div><div class='add'>+ *</div><div class='add'>+ * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR` : 0x0900</div><div class='add'>+ *      Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts</div><div class='add'>+ *      status vector for use by the GuC.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR` : 0x0901</div><div class='add'>+ *      Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts</div><div class='add'>+ *      source vector for use by the GuC.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902</div><div class='add'>+ *      Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.</div><div class='add'>+ *      Should be above WOPCM address but below APIC base address for native mode.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903</div><div class='add'>+ *      Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.</div><div class='add'>+ *      Should be above WOPCM address but below APIC base address for native mode.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904</div><div class='add'>+ *      Refers to size of H2G `CT Buffer`_ in bytes.</div><div class='add'>+ *      Should be a multiple of 4K.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905</div><div class='add'>+ *      Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.</div><div class='add'>+ *      Should be above WOPCM address but below APIC base address for native mode.</div><div class='add'>+ *</div><div class='add'>+ * _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906</div><div class='add'>+ *      Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.</div><div class='add'>+ *      Should be above WOPCM address but below APIC base address for native mode.</div><div class='add'>+ *</div><div class='add'>+ * _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907</div><div class='add'>+ *      Refers to size of G2H `CT Buffer`_ in bytes.</div><div class='add'>+ *      Should be a multiple of 4K.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_KEY		0x0900</div><div class='add'>+#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_KEY		0x0901</div><div class='add'>+#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY		0x0902</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY	0x0903</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN	2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY		0x0904</div><div class='add'>+#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY		0x0905</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY	0x0906</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN	2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY		0x0907</div><div class='add'>+#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN		1u</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Per context scheduling policy update keys.</div><div class='add'>+ */</div><div class='add'>+enum  {</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM			= 0x2001,</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT			= 0x2002,</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY			= 0x2003,</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY	= 0x2004,</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY			= 0x2005,</div><div class='add'>+</div><div class='add'>+	GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC VGT Policy KLVs</div><div class='add'>+ *</div><div class='add'>+ * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001</div><div class='add'>+ *      This config sets whether strict scheduling is enabled whereby any VF</div><div class='add'>+ *      that doesn’t have work to submit is still allocated a fixed execution</div><div class='add'>+ *      time-slice to ensure active VFs execution is always consitent even</div><div class='add'>+ *      during other VF reprovisiong / rebooting events. Changing this KLV</div><div class='add'>+ *      impacts all VFs and takes effect on the next VF-Switch event.</div><div class='add'>+ *</div><div class='add'>+ *      :0: don't schedule idle (default)</div><div class='add'>+ *      :1: schedule if idle</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD` : 0x8002</div><div class='add'>+ *      This config sets the sample period for tracking adverse event counters.</div><div class='add'>+ *       A sample period is the period in millisecs during which events are counted.</div><div class='add'>+ *       This is applicable for all the VFs.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events are not counted (default)</div><div class='add'>+ *      :n: sample period in milliseconds</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH` : 0x8D00</div><div class='add'>+ *      This enum is to reset utilized HW engine after VF Switch (i.e to clean</div><div class='add'>+ *      up Stale HW register left behind by previous VF)</div><div class='add'>+ *</div><div class='add'>+ *      :0: don't reset (default)</div><div class='add'>+ *      :1: reset</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY		0x8001</div><div class='add'>+#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_KEY	0x8002</div><div class='add'>+#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_KEY	0x8D00</div><div class='add'>+#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_LEN	1u</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC VF Configuration KLVs</div><div class='add'>+ *</div><div class='add'>+ * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VF_CFG.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_GGTT_START` : 0x0001</div><div class='add'>+ *      A 4K aligned start GTT address/offset assigned to VF.</div><div class='add'>+ *      Value is 64 bits.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_GGTT_SIZE` : 0x0002</div><div class='add'>+ *      A 4K aligned size of GGTT assigned to VF.</div><div class='add'>+ *      Value is 64 bits.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_LMEM_SIZE` : 0x0003</div><div class='add'>+ *      A 2M aligned size of local memory assigned to VF.</div><div class='add'>+ *      Value is 64 bits.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_NUM_CONTEXTS` : 0x0004</div><div class='add'>+ *      Refers to the number of contexts allocated to this VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: no contexts (default)</div><div class='add'>+ *      :1-65535: number of contexts (Gen12)</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_TILE_MASK` : 0x0005</div><div class='add'>+ *      For multi-tiled products, this field contains the bitwise-OR of tiles</div><div class='add'>+ *      assigned to the VF. Bit-0-set means VF has access to Tile-0,</div><div class='add'>+ *      Bit-31-set means VF has access to Tile-31, and etc.</div><div class='add'>+ *      At least one tile will always be allocated.</div><div class='add'>+ *      If all bits are zero, VF KMD should treat this as a fatal error.</div><div class='add'>+ *      For, single-tile products this KLV config is ignored.</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_NUM_DOORBELLS` : 0x0006</div><div class='add'>+ *      Refers to the number of doorbells allocated to this VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: no doorbells (default)</div><div class='add'>+ *      :1-255: number of doorbells (Gen12)</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_EXEC_QUANTUM` : 0x8A01</div><div class='add'>+ *      This config sets the VFs-execution-quantum in milliseconds.</div><div class='add'>+ *      GUC will attempt to obey the maximum values as much as HW is capable</div><div class='add'>+ *      of and this will never be perfectly-exact (accumulated nano-second</div><div class='add'>+ *      granularity) since the GPUs clock time runs off a different crystal</div><div class='add'>+ *      from the CPUs clock. Changing this KLV on a VF that is currently</div><div class='add'>+ *      running a context wont take effect until a new context is scheduled in.</div><div class='add'>+ *      That said, when the PF is changing this value from 0xFFFFFFFF to</div><div class='add'>+ *      something else, it might never take effect if the VF is running an</div><div class='add'>+ *      inifinitely long compute or shader kernel. In such a scenario, the</div><div class='add'>+ *      PF would need to trigger a VM PAUSE and then change the KLV to force</div><div class='add'>+ *      it to take effect. Such cases might typically happen on a 1PF+1VF</div><div class='add'>+ *      Virtualization config enabled for heavier workloads like AI/ML.</div><div class='add'>+ *</div><div class='add'>+ *      :0: infinite exec quantum (default)</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_PREEMPT_TIMEOUT` : 0x8A02</div><div class='add'>+ *      This config sets the VF-preemption-timeout in microseconds.</div><div class='add'>+ *      GUC will attempt to obey the minimum and maximum values as much as</div><div class='add'>+ *      HW is capable and this will never be perfectly-exact (accumulated</div><div class='add'>+ *      nano-second granularity) since the GPUs clock time runs off a</div><div class='add'>+ *      different crystal from the CPUs clock. Changing this KLV on a VF</div><div class='add'>+ *      that is currently running a context wont take effect until a new</div><div class='add'>+ *      context is scheduled in.</div><div class='add'>+ *      That said, when the PF is changing this value from 0xFFFFFFFF to</div><div class='add'>+ *      something else, it might never take effect if the VF is running an</div><div class='add'>+ *      inifinitely long compute or shader kernel.</div><div class='add'>+ *      In this case, the PF would need to trigger a VM PAUSE and then change</div><div class='add'>+ *      the KLV to force it to take effect. Such cases might typically happen</div><div class='add'>+ *      on a 1PF+1VF Virtualization config enabled for heavier workloads like</div><div class='add'>+ *      AI/ML.</div><div class='add'>+ *</div><div class='add'>+ *      :0: no preemption timeout (default)</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR` : 0x8A03</div><div class='add'>+ *      This config sets threshold for CAT errors caused by the VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: event occurrence count per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET` : 0x8A04</div><div class='add'>+ *      This config sets threshold for engine reset caused by the VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: event occurrence count per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT` : 0x8A05</div><div class='add'>+ *      This config sets threshold for page fault errors caused by the VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: event occurrence count per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM` : 0x8A06</div><div class='add'>+ *      This config sets threshold for H2G interrupts triggered by the VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: time (us) per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM` : 0x8A07</div><div class='add'>+ *      This config sets threshold for GT interrupts triggered by the VF's</div><div class='add'>+ *      workloads.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: time (us) per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM` : 0x8A08</div><div class='add'>+ *      This config sets threshold for doorbell's ring triggered by the VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: adverse events or error will not be reported (default)</div><div class='add'>+ *      :n: time (us) per sampling interval</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID` : 0x8A0A</div><div class='add'>+ *      Refers to the start index of doorbell assigned to this VF.</div><div class='add'>+ *</div><div class='add'>+ *      :0: (default)</div><div class='add'>+ *      :1-255: number of doorbells (Gen12)</div><div class='add'>+ *</div><div class='add'>+ * _`GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID` : 0x8A0B</div><div class='add'>+ *      Refers to the start index in context array allocated to this VF’s use.</div><div class='add'>+ *</div><div class='add'>+ *      :0: (default)</div><div class='add'>+ *      :1-65535: number of contexts (Gen12)</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_GGTT_START_KEY		0x0001</div><div class='add'>+#define GUC_KLV_VF_CFG_GGTT_START_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_GGTT_SIZE_KEY		0x0002</div><div class='add'>+#define GUC_KLV_VF_CFG_GGTT_SIZE_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_LMEM_SIZE_KEY		0x0003</div><div class='add'>+#define GUC_KLV_VF_CFG_LMEM_SIZE_LEN		2u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_NUM_CONTEXTS_KEY		0x0004</div><div class='add'>+#define GUC_KLV_VF_CFG_NUM_CONTEXTS_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_TILE_MASK_KEY		0x0005</div><div class='add'>+#define GUC_KLV_VF_CFG_TILE_MASK_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_NUM_DOORBELLS_KEY	0x0006</div><div class='add'>+#define GUC_KLV_VF_CFG_NUM_DOORBELLS_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_EXEC_QUANTUM_KEY		0x8a01</div><div class='add'>+#define GUC_KLV_VF_CFG_EXEC_QUANTUM_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_KEY	0x8a02</div><div class='add'>+#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_KEY		0x8a03</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_KEY	0x8a04</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_KEY		0x8a05</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_KEY		0x8a06</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_KEY		0x8a07</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_LEN		1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_KEY	0x8a08</div><div class='add'>+#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_KEY	0x8a0a</div><div class='add'>+#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_LEN	1u</div><div class='add'>+</div><div class='add'>+#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_KEY	0x8a0b</div><div class='add'>+#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_LEN	1u</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/abi/guc_messages_abi.h b/drivers/gpu/drm/xe/abi/guc_messages_abi.h<br/>new file mode 100644<br/>index 000000000000..3d199016cf88<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/abi/guc_messages_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/abi/guc_messages_abi.h</a></div><div class='hunk'>@@ -0,0 +1,234 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2014-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _ABI_GUC_MESSAGES_ABI_H</div><div class='add'>+#define _ABI_GUC_MESSAGES_ABI_H</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Message</div><div class='add'>+ *</div><div class='add'>+ * All messages exchanged with GuC are defined using 32 bit dwords.</div><div class='add'>+ * First dword is treated as a message header. Remaining dwords are optional.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  | 0 |    31 | **ORIGIN** - originator of the message                       |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_ORIGIN_HOST` = 0                               |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_ORIGIN_GUC` = 1                                |</div><div class='add'>+ *  |   |       |                                                              |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | **TYPE** - message type                                      |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_REQUEST` = 0                              |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_EVENT` = 1                                |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3                     |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5                    |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6                     |</div><div class='add'>+ *  |   |       |   - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7                     |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | **AUX** - auxiliary data (depends on TYPE)                   |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | **PAYLOAD** - optional payload (depends on TYPE)             |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_MSG_MIN_LEN			1u</div><div class='add'>+#define GUC_HXG_MSG_0_ORIGIN			(0x1 &lt;&lt; 31)</div><div class='add'>+#define   GUC_HXG_ORIGIN_HOST			0u</div><div class='add'>+#define   GUC_HXG_ORIGIN_GUC			1u</div><div class='add'>+#define GUC_HXG_MSG_0_TYPE			(0x7 &lt;&lt; 28)</div><div class='add'>+#define   GUC_HXG_TYPE_REQUEST			0u</div><div class='add'>+#define   GUC_HXG_TYPE_EVENT			1u</div><div class='add'>+#define   GUC_HXG_TYPE_NO_RESPONSE_BUSY		3u</div><div class='add'>+#define   GUC_HXG_TYPE_NO_RESPONSE_RETRY	5u</div><div class='add'>+#define   GUC_HXG_TYPE_RESPONSE_FAILURE		6u</div><div class='add'>+#define   GUC_HXG_TYPE_RESPONSE_SUCCESS		7u</div><div class='add'>+#define GUC_HXG_MSG_0_AUX			(0xfffffff &lt;&lt; 0)</div><div class='add'>+#define GUC_HXG_MSG_n_PAYLOAD			(0xffffffff &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Request</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Request`_ message should be used to initiate synchronous activity</div><div class='add'>+ * for which confirmation or return data is expected.</div><div class='add'>+ *</div><div class='add'>+ * The recipient of this message shall use `HXG Response`_, `HXG Failure`_</div><div class='add'>+ * or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_</div><div class='add'>+ * message as a intermediate reply.</div><div class='add'>+ *</div><div class='add'>+ * Format of @DATA0 and all @DATAn fields depends on the @ACTION code.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | **DATA0** - request data (depends on ACTION)                 |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | **ACTION** - requested action code                           |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | **DATAn** - optional data (depends on ACTION)                |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_REQUEST_MSG_MIN_LEN		GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_REQUEST_MSG_0_DATA0		(0xfff &lt;&lt; 16)</div><div class='add'>+#define GUC_HXG_REQUEST_MSG_0_ACTION		(0xffff &lt;&lt; 0)</div><div class='add'>+#define GUC_HXG_REQUEST_MSG_n_DATAn		GUC_HXG_MSG_n_PAYLOAD</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Event</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Event`_ message should be used to initiate asynchronous activity</div><div class='add'>+ * that does not involves immediate confirmation nor data.</div><div class='add'>+ *</div><div class='add'>+ * Format of @DATA0 and all @DATAn fields depends on the @ACTION code.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_EVENT_                                   |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | **DATA0** - event data (depends on ACTION)                   |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | **ACTION** - event action code                               |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | **DATAn** - optional event  data (depends on ACTION)         |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_EVENT_MSG_MIN_LEN		GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_EVENT_MSG_0_DATA0		(0xfff &lt;&lt; 16)</div><div class='add'>+#define GUC_HXG_EVENT_MSG_0_ACTION		(0xffff &lt;&lt; 0)</div><div class='add'>+#define GUC_HXG_EVENT_MSG_n_DATAn		GUC_HXG_MSG_n_PAYLOAD</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Busy</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Busy`_ message may be used to acknowledge reception of the `HXG Request`_</div><div class='add'>+ * message if the recipient expects that it processing will be longer than default</div><div class='add'>+ * timeout.</div><div class='add'>+ *</div><div class='add'>+ * The @COUNTER field may be used as a progress indicator.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_BUSY_                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | **COUNTER** - progress indicator                             |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_BUSY_MSG_LEN			GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_BUSY_MSG_0_COUNTER		GUC_HXG_MSG_0_AUX</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Retry</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Retry`_ message should be used by recipient to indicate that the</div><div class='add'>+ * `HXG Request`_ message was dropped and it should be resent again.</div><div class='add'>+ *</div><div class='add'>+ * The @REASON field may be used to provide additional information.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_NO_RESPONSE_RETRY_                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | **REASON** - reason for retry                                |</div><div class='add'>+ *  |   |       |  - _`GUC_HXG_RETRY_REASON_UNSPECIFIED` = 0                   |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_RETRY_MSG_LEN			GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_RETRY_MSG_0_REASON		GUC_HXG_MSG_0_AUX</div><div class='add'>+#define   GUC_HXG_RETRY_REASON_UNSPECIFIED	0u</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Failure</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Failure`_ message shall be used as a reply to the `HXG Request`_</div><div class='add'>+ * message that could not be processed due to an error.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_FAILURE_                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 27:16 | **HINT** - additional error hint                             |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  15:0 | **ERROR** - error/result code                                |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_FAILURE_MSG_LEN			GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_FAILURE_MSG_0_HINT		(0xfff &lt;&lt; 16)</div><div class='add'>+#define GUC_HXG_FAILURE_MSG_0_ERROR		(0xffff &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: HXG Response</div><div class='add'>+ *</div><div class='add'>+ * The `HXG Response`_ message shall be used as a reply to the `HXG Request`_</div><div class='add'>+ * message that was successfully processed without an error.</div><div class='add'>+ *</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | Bits  | Description                                                  |</div><div class='add'>+ *  +===+=======+==============================================================+</div><div class='add'>+ *  | 0 |    31 | ORIGIN                                                       |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |</div><div class='add'>+ *  |   +-------+--------------------------------------------------------------+</div><div class='add'>+ *  |   |  27:0 | **DATA0** - data (depends on ACTION from `HXG Request`_)     |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ *  | 1 |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  |...|       | **DATAn** - data (depends on ACTION from `HXG Request`_)     |</div><div class='add'>+ *  +---+-------+                                                              |</div><div class='add'>+ *  | n |  31:0 |                                                              |</div><div class='add'>+ *  +---+-------+--------------------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GUC_HXG_RESPONSE_MSG_MIN_LEN		GUC_HXG_MSG_MIN_LEN</div><div class='add'>+#define GUC_HXG_RESPONSE_MSG_0_DATA0		GUC_HXG_MSG_0_AUX</div><div class='add'>+#define GUC_HXG_RESPONSE_MSG_n_DATAn		GUC_HXG_MSG_n_PAYLOAD</div><div class='add'>+</div><div class='add'>+/* deprecated */</div><div class='add'>+#define INTEL_GUC_MSG_TYPE_SHIFT	28</div><div class='add'>+#define INTEL_GUC_MSG_TYPE_MASK		(0xF &lt;&lt; INTEL_GUC_MSG_TYPE_SHIFT)</div><div class='add'>+#define INTEL_GUC_MSG_DATA_SHIFT	16</div><div class='add'>+#define INTEL_GUC_MSG_DATA_MASK		(0xFFF &lt;&lt; INTEL_GUC_MSG_DATA_SHIFT)</div><div class='add'>+#define INTEL_GUC_MSG_CODE_SHIFT	0</div><div class='add'>+#define INTEL_GUC_MSG_CODE_MASK		(0xFFFF &lt;&lt; INTEL_GUC_MSG_CODE_SHIFT)</div><div class='add'>+</div><div class='add'>+enum intel_guc_msg_type {</div><div class='add'>+	INTEL_GUC_MSG_TYPE_REQUEST = 0x0,</div><div class='add'>+	INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h<br/>new file mode 100644<br/>index 000000000000..710cecca972d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_lmem.h</a></div><div class='hunk'>@@ -0,0 +1 @@</div><div class='add'>+/* Empty */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h<br/>new file mode 100644<br/>index 000000000000..650ea2803a97<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_mman.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_GEM_MMAN_H_</div><div class='add'>+#define _I915_GEM_MMAN_H_</div><div class='add'>+</div><div class='add'>+#include "xe_bo_types.h"</div><div class='add'>+#include &lt;drm/drm_prime.h&gt;</div><div class='add'>+</div><div class='add'>+static inline int i915_gem_fb_mmap(struct xe_bo *bo, struct vm_area_struct *vma)</div><div class='add'>+{</div><div class='add'>+	return drm_gem_prime_mmap(&amp;bo-&gt;ttm.base, vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h<br/>new file mode 100644<br/>index 000000000000..5f19550cc845<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h</a></div><div class='hunk'>@@ -0,0 +1,65 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_GEM_OBJECT_H_</div><div class='add'>+#define _I915_GEM_OBJECT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+</div><div class='add'>+#define i915_gem_object_is_shmem(obj) ((obj)-&gt;flags &amp; XE_BO_CREATE_SYSTEM_BIT)</div><div class='add'>+</div><div class='add'>+static inline dma_addr_t i915_gem_object_get_dma_address(const struct xe_bo *bo, pgoff_t n)</div><div class='add'>+{</div><div class='add'>+	/* Should never be called */</div><div class='add'>+	WARN_ON(1);</div><div class='add'>+	return n;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool i915_gem_object_is_tiled(const struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	/* legacy tiling is unused */</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool i915_gem_object_is_userptr(const struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	/* legacy tiling is unused */</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int i915_gem_object_read_from_page(struct xe_bo *bo,</div><div class='add'>+					  u32 ofs, u64 *ptr, u32 size)</div><div class='add'>+{</div><div class='add'>+	struct ttm_bo_kmap_obj map;</div><div class='add'>+	void *virtual;</div><div class='add'>+	bool is_iomem;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(size != 8);</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_lock(bo, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = ttm_bo_kmap(&amp;bo-&gt;ttm, ofs &gt;&gt; PAGE_SHIFT, 1, &amp;map);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	ofs &amp;= ~PAGE_MASK;</div><div class='add'>+	virtual = ttm_kmap_obj_virtual(&amp;map, &amp;is_iomem);</div><div class='add'>+	if (is_iomem)</div><div class='add'>+		*ptr = readq((void __iomem *)(virtual + ofs));</div><div class='add'>+	else</div><div class='add'>+		*ptr = *(u64 *)(virtual + ofs);</div><div class='add'>+</div><div class='add'>+	ttm_bo_kunmap(&amp;map);</div><div class='add'>+out_unlock:</div><div class='add'>+	xe_bo_unlock(bo);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h<br/>new file mode 100644<br/>index 000000000000..2a3f12d2978c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_GEM_OBJECT_FRONTBUFFER_H_</div><div class='add'>+#define _I915_GEM_OBJECT_FRONTBUFFER_H_</div><div class='add'>+</div><div class='add'>+#define i915_gem_object_get_frontbuffer(obj)		NULL</div><div class='add'>+#define i915_gem_object_set_frontbuffer(obj, front)	(front)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h b/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h<br/>new file mode 100644<br/>index 000000000000..21fec9cc837c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_RPS_H__</div><div class='add'>+#define __INTEL_RPS_H__</div><div class='add'>+</div><div class='add'>+#define gen5_rps_irq_handler(x) ({})</div><div class='add'>+</div><div class='add'>+#endif /* __INTEL_RPS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_active.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_active.h<br/>new file mode 100644<br/>index 000000000000..6f0ab3753563<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_active.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_active.h</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_ACTIVE_H_</div><div class='add'>+#define _I915_ACTIVE_H_</div><div class='add'>+</div><div class='add'>+#include "i915_active_types.h"</div><div class='add'>+</div><div class='add'>+static inline void i915_active_init(struct i915_active *ref,</div><div class='add'>+				    int (*active)(struct i915_active *ref),</div><div class='add'>+				    void (*retire)(struct i915_active *ref),</div><div class='add'>+				    unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	(void) active;</div><div class='add'>+	(void) retire;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define i915_active_fini(active) do { } while (0)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h<br/>new file mode 100644<br/>index 000000000000..8c31f9a8b168<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/*</div><div class='add'>+ * SPDX-License-Identifier: MIT</div><div class='add'>+ *</div><div class='add'>+ * Copyright © 2019 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_ACTIVE_TYPES_H_</div><div class='add'>+#define _I915_ACTIVE_TYPES_H_</div><div class='add'>+</div><div class='add'>+struct i915_active {};</div><div class='add'>+#define I915_ACTIVE_RETIRE_SLEEPS 0</div><div class='add'>+</div><div class='add'>+#endif /* _I915_ACTIVE_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_config.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_config.h<br/>new file mode 100644<br/>index 000000000000..e835bea08d1b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_config.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __I915_CONFIG_H__</div><div class='add'>+#define __I915_CONFIG_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/sched.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+</div><div class='add'>+static inline unsigned long</div><div class='add'>+i915_fence_timeout(const struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return MAX_SCHEDULE_TIMEOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* __I915_CONFIG_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h<br/>new file mode 100644<br/>index 000000000000..b4c47617b64b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __I915_DEBUGFS_H__</div><div class='add'>+#define __I915_DEBUGFS_H__</div><div class='add'>+</div><div class='add'>+struct drm_i915_gem_object;</div><div class='add'>+struct seq_file;</div><div class='add'>+</div><div class='add'>+static inline void i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) {}</div><div class='add'>+</div><div class='add'>+#endif /* __I915_DEBUGFS_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h<br/>new file mode 100644<br/>index 000000000000..5d2a77b52db4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h</a></div><div class='hunk'>@@ -0,0 +1,233 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_I915_DRV_H_</div><div class='add'>+#define _XE_I915_DRV_H_</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * "Adaptation header" to allow i915 display to also build for xe driver.</div><div class='add'>+ * TODO: refactor i915 and xe so this can cease to exist</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+</div><div class='add'>+#include "gem/i915_gem_object.h"</div><div class='add'>+</div><div class='add'>+#include "soc/intel_pch.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+#include "i915_gem.h"</div><div class='add'>+#include "i915_gem_stolen.h"</div><div class='add'>+#include "i915_gpu_error.h"</div><div class='add'>+#include "i915_reg_defs.h"</div><div class='add'>+#include "i915_utils.h"</div><div class='add'>+#include "intel_gt_types.h"</div><div class='add'>+#include "intel_step.h"</div><div class='add'>+#include "intel_uc_fw.h"</div><div class='add'>+#include "intel_uncore.h"</div><div class='add'>+#include "intel_runtime_pm.h"</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+</div><div class='add'>+static inline struct drm_i915_private *to_i915(const struct drm_device *dev)</div><div class='add'>+{</div><div class='add'>+	return container_of(dev, struct drm_i915_private, drm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)</div><div class='add'>+{</div><div class='add'>+	return dev_get_drvdata(kdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define INTEL_JASPERLAKE 0</div><div class='add'>+#define INTEL_ELKHARTLAKE 0</div><div class='add'>+#define IS_PLATFORM(xe, x) ((xe)-&gt;info.platform == x)</div><div class='add'>+#define INTEL_INFO(dev_priv)	(&amp;((dev_priv)-&gt;info))</div><div class='add'>+#define INTEL_DEVID(dev_priv)	((dev_priv)-&gt;info.devid)</div><div class='add'>+#define IS_I830(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I845G(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I85X(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I865G(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I915G(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I915GM(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I945G(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I945GM(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I965G(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_I965GM(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_G45(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_GM45(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_G4X(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_PINEVIEW(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_G33(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_IRONLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_IRONLAKE_M(dev_priv) (dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_SANDYBRIDGE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_IVYBRIDGE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_IVB_GT1(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_VALLEYVIEW(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_CHERRYVIEW(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_HASWELL(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_BROADWELL(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_SKYLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_BROXTON(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_KABYLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_GEMINILAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_COFFEELAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_COMETLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_ICELAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_JASPERLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_ELKHARTLAKE(dev_priv)	(dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, XE_TIGERLAKE)</div><div class='add'>+#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, XE_ROCKETLAKE)</div><div class='add'>+#define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, XE_DG1)</div><div class='add'>+#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S)</div><div class='add'>+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P)</div><div class='add'>+#define IS_XEHPSDV(dev_priv) (dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, XE_DG2)</div><div class='add'>+#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC)</div><div class='add'>+#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)</div><div class='add'>+#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)</div><div class='add'>+</div><div class='add'>+#define IS_HASWELL_ULT(dev_priv) (dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_BROADWELL_ULT(dev_priv) (dev_priv &amp;&amp; 0)</div><div class='add'>+#define IS_BROADWELL_ULX(dev_priv) (dev_priv &amp;&amp; 0)</div><div class='add'>+</div><div class='add'>+#define IP_VER(ver, rel)                ((ver) &lt;&lt; 8 | (rel))</div><div class='add'>+</div><div class='add'>+#define INTEL_DISPLAY_ENABLED(xe) (HAS_DISPLAY((xe)) &amp;&amp; !intel_opregion_headless_sku((xe)))</div><div class='add'>+</div><div class='add'>+#define IS_GRAPHICS_VER(xe, first, last) \</div><div class='add'>+	((xe)-&gt;info.graphics_verx100 &gt;= first * 100 &amp;&amp; \</div><div class='add'>+	 (xe)-&gt;info.graphics_verx100 &lt;= (last*100 + 99))</div><div class='add'>+#define IS_MOBILE(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define HAS_LLC(xe) (!IS_DGFX((xe)))</div><div class='add'>+</div><div class='add'>+#define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) &gt;= 1270</div><div class='add'>+</div><div class='add'>+/* Workarounds not handled yet */</div><div class='add'>+#define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)-&gt;info.step.display; first &lt;= __step &amp;&amp; __step &lt;= last; })</div><div class='add'>+#define IS_GRAPHICS_STEP(xe, first, last) ({u8 __step = (xe)-&gt;info.step.graphics; first &lt;= __step &amp;&amp; __step &lt;= last; })</div><div class='add'>+</div><div class='add'>+#define IS_LP(xe) (0)</div><div class='add'>+#define IS_GEN9_LP(xe) (0)</div><div class='add'>+#define IS_GEN9_BC(xe) (0)</div><div class='add'>+</div><div class='add'>+#define IS_TIGERLAKE_UY(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_COMETLAKE_ULX(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_COFFEELAKE_ULX(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_KABYLAKE_ULX(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_SKYLAKE_ULX(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_HASWELL_ULX(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_COMETLAKE_ULT(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_COFFEELAKE_ULT(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_KABYLAKE_ULT(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define IS_SKYLAKE_ULT(xe) (xe &amp;&amp; 0)</div><div class='add'>+</div><div class='add'>+#define IS_DG1_GRAPHICS_STEP(xe, first, last) (IS_DG1(xe) &amp;&amp; IS_GRAPHICS_STEP(xe, first, last))</div><div class='add'>+#define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \</div><div class='add'>+	((xe)-&gt;info.subplatform == XE_SUBPLATFORM_DG2_ ## variant &amp;&amp; \</div><div class='add'>+	 IS_GRAPHICS_STEP(xe, first, last))</div><div class='add'>+#define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) &amp;&amp; IS_GRAPHICS_STEP(xe, first, last))</div><div class='add'>+</div><div class='add'>+/* XXX: No basedie stepping support yet */</div><div class='add'>+#define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) &amp;&amp; IS_PONTEVECCHIO(xe))</div><div class='add'>+</div><div class='add'>+#define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_DG2_DISPLAY_STEP(xe, first, last) (IS_DG2(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_ADLP_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_P(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_ADLS_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_S(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_JSL_EHL_DISPLAY_STEP(xe, first, last) (IS_JSL_EHL(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+#define IS_MTL_DISPLAY_STEP(xe, first, last) (IS_METEORLAKE(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+</div><div class='add'>+/* FIXME: Add subplatform here */</div><div class='add'>+#define IS_MTL_GRAPHICS_STEP(xe, sub, first, last) (IS_METEORLAKE(xe) &amp;&amp; IS_DISPLAY_STEP(xe, first, last))</div><div class='add'>+</div><div class='add'>+#define IS_DG2_G10(xe) ((xe)-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G10)</div><div class='add'>+#define IS_DG2_G11(xe) ((xe)-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G11)</div><div class='add'>+#define IS_DG2_G12(xe) ((xe)-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G12)</div><div class='add'>+#define IS_RAPTORLAKE_U(xe) ((xe)-&gt;info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU)</div><div class='add'>+#define IS_ICL_WITH_PORT_F(xe) (xe &amp;&amp; 0)</div><div class='add'>+#define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe))</div><div class='add'>+#define to_intel_bo(x) gem_to_xe_bo((x))</div><div class='add'>+#define mkwrite_device_info(xe) (INTEL_INFO(xe))</div><div class='add'>+</div><div class='add'>+#define HAS_128_BYTE_Y_TILING(xe) (xe || 1)</div><div class='add'>+</div><div class='add'>+#define intel_has_gpu_reset(a) (a &amp;&amp; 0)</div><div class='add'>+</div><div class='add'>+#include "intel_wakeref.h"</div><div class='add'>+</div><div class='add'>+static inline bool intel_runtime_pm_get(struct xe_runtime_pm *pm)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);</div><div class='add'>+</div><div class='add'>+	if (xe_pm_runtime_get(xe) &lt; 0) {</div><div class='add'>+		xe_pm_runtime_put(xe);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);</div><div class='add'>+</div><div class='add'>+	return xe_pm_runtime_get_if_active(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);</div><div class='add'>+</div><div class='add'>+	xe_pm_runtime_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, bool wakeref)</div><div class='add'>+{</div><div class='add'>+	if (wakeref)</div><div class='add'>+		intel_runtime_pm_put_unchecked(pm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define intel_runtime_pm_get_raw intel_runtime_pm_get</div><div class='add'>+#define intel_runtime_pm_put_raw intel_runtime_pm_put</div><div class='add'>+#define assert_rpm_wakelock_held(x) do { } while (0)</div><div class='add'>+#define assert_rpm_raw_wakeref_held(x) do { } while (0)</div><div class='add'>+</div><div class='add'>+#define intel_uncore_forcewake_get(x, y) do { } while (0)</div><div class='add'>+#define intel_uncore_forcewake_put(x, y) do { } while (0)</div><div class='add'>+</div><div class='add'>+#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0)</div><div class='add'>+</div><div class='add'>+#define I915_PRIORITY_DISPLAY 0</div><div class='add'>+struct i915_sched_attr {</div><div class='add'>+	int priority;</div><div class='add'>+};</div><div class='add'>+#define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0)</div><div class='add'>+</div><div class='add'>+#define with_intel_runtime_pm(rpm, wf) \</div><div class='add'>+	for ((wf) = intel_runtime_pm_get(rpm); (wf); \</div><div class='add'>+	     intel_runtime_pm_put((rpm), (wf)), (wf) = 0)</div><div class='add'>+</div><div class='add'>+#define pdev_to_i915 pdev_to_xe_device</div><div class='add'>+#define RUNTIME_INFO(xe)		(&amp;(xe)-&gt;info.i915_runtime)</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_ALL XE_FORCEWAKE_ALL</div><div class='add'>+#define HPD_STORM_DEFAULT_THRESHOLD 50</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_ARM64</div><div class='add'>+/*</div><div class='add'>+ * arm64 indirectly includes linux/rtc.h,</div><div class='add'>+ * which defines a irq_lock, so include it</div><div class='add'>+ * here before #define-ing it</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/rtc.h&gt;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define irq_lock irq.lock</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h<br/>new file mode 100644<br/>index 000000000000..12c671fd5235<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/i915_fixed.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h<br/>new file mode 100644<br/>index 000000000000..06b723a479c5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __I915_GEM_H__</div><div class='add'>+#define __I915_GEM_H__</div><div class='add'>+#define GEM_BUG_ON</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h<br/>new file mode 100644<br/>index 000000000000..888e7a87a925<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+#ifndef _I915_GEM_STOLEN_H_</div><div class='add'>+#define _I915_GEM_STOLEN_H_</div><div class='add'>+</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+struct i915_stolen_fb {</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline int i915_gem_stolen_insert_node_in_range(struct xe_device *xe,</div><div class='add'>+						       struct i915_stolen_fb *fb,</div><div class='add'>+						       u32 size, u32 align,</div><div class='add'>+						       u32 start, u32 end)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+	u32 flags = XE_BO_CREATE_PINNED_BIT | XE_BO_CREATE_STOLEN_BIT;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe),</div><div class='add'>+				       NULL, size, start, end,</div><div class='add'>+				       ttm_bo_type_kernel, flags);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		err = PTR_ERR(bo);</div><div class='add'>+		bo = NULL;</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+	err = xe_bo_pin(bo);</div><div class='add'>+	xe_bo_unlock_vm_held(bo);</div><div class='add'>+</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_bo_put(fb-&gt;bo);</div><div class='add'>+		bo = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fb-&gt;bo = bo;</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int i915_gem_stolen_insert_node(struct xe_device *xe,</div><div class='add'>+					      struct i915_stolen_fb *fb,</div><div class='add'>+					      u32 size, u32 align)</div><div class='add'>+{</div><div class='add'>+	/* Not used on xe */</div><div class='add'>+	BUG_ON(1);</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void i915_gem_stolen_remove_node(struct xe_device *xe,</div><div class='add'>+					       struct i915_stolen_fb *fb)</div><div class='add'>+{</div><div class='add'>+	xe_bo_unpin_map_no_vm(fb-&gt;bo);</div><div class='add'>+	fb-&gt;bo = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define i915_gem_stolen_initialized(xe) (!!ttm_manager_type(&amp;(xe)-&gt;ttm, XE_PL_STOLEN))</div><div class='add'>+#define i915_gem_stolen_node_allocated(fb) (!!((fb)-&gt;bo))</div><div class='add'>+</div><div class='add'>+static inline u32 i915_gem_stolen_node_offset(struct i915_stolen_fb *fb)</div><div class='add'>+{</div><div class='add'>+	struct xe_res_cursor res;</div><div class='add'>+</div><div class='add'>+	xe_res_first(fb-&gt;bo-&gt;ttm.resource, 0, 4096, &amp;res);</div><div class='add'>+	return res.start;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Used for &lt; gen4. These are not supported by Xe */</div><div class='add'>+#define i915_gem_stolen_area_address(xe) (!WARN_ON(1))</div><div class='add'>+/* Used for gen9 specific WA. Gen9 is not supported by Xe */</div><div class='add'>+#define i915_gem_stolen_area_size(xe) (!WARN_ON(1))</div><div class='add'>+</div><div class='add'>+#define i915_gem_stolen_node_address(xe, fb) (xe_ttm_stolen_gpu_offset(xe) + \</div><div class='add'>+					 i915_gem_stolen_node_offset(fb))</div><div class='add'>+#define i915_gem_stolen_node_size(fb) ((u64)((fb)-&gt;bo-&gt;ttm.base.size))</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h<br/>new file mode 100644<br/>index 000000000000..98e9dd78f670<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_gpu_error.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_GPU_ERROR_H_</div><div class='add'>+#define _I915_GPU_ERROR_H_</div><div class='add'>+</div><div class='add'>+struct drm_i915_error_state_buf;</div><div class='add'>+</div><div class='add'>+__printf(2, 3)</div><div class='add'>+static inline void</div><div class='add'>+i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h<br/>new file mode 100644<br/>index 000000000000..61707a07f91f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/i915_irq.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h<br/>new file mode 100644<br/>index 000000000000..8619ec015ad4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/i915_reg.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h<br/>new file mode 100644<br/>index 000000000000..723279c975b1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/i915_reg_defs.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h<br/>new file mode 100644<br/>index 000000000000..d429d421ac70<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define trace_i915_reg_rw(a...) do { } while (0)</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h<br/>new file mode 100644<br/>index 000000000000..1d7c4360e5c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/i915_utils.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h<br/>new file mode 100644<br/>index 000000000000..80b024d435dc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _I915_VGPU_H_</div><div class='add'>+#define _I915_VGPU_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+struct i915_ggtt;</div><div class='add'>+</div><div class='add'>+static inline void intel_vgpu_detect(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline bool intel_vgpu_active(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+static inline void intel_vgpu_register(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+static inline bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+static inline bool intel_vgpu_has_huge_gtt(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+static inline int intel_vgt_balloon(struct i915_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void intel_vgt_deballoon(struct i915_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* _I915_VGPU_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h<br/>new file mode 100644<br/>index 000000000000..a20d2638ea7a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef I915_VMA_H</div><div class='add'>+#define I915_VMA_H</div><div class='add'>+</div><div class='add'>+#include &lt;uapi/drm/i915_drm.h&gt;</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+</div><div class='add'>+/* We don't want these from i915_drm.h in case of Xe */</div><div class='add'>+#undef I915_TILING_X</div><div class='add'>+#undef I915_TILING_Y</div><div class='add'>+#define I915_TILING_X 0</div><div class='add'>+#define I915_TILING_Y 0</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+struct i915_vma {</div><div class='add'>+	struct xe_bo *bo, *dpt;</div><div class='add'>+	struct drm_mm_node node;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define i915_ggtt_clear_scanout(bo) do { } while (0)</div><div class='add'>+</div><div class='add'>+#define i915_vma_fence_id(vma) -1</div><div class='add'>+</div><div class='add'>+static inline u32 i915_ggtt_offset(const struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;node.start;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h<br/>new file mode 100644<br/>index 000000000000..e7aaf50f5485<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/build_bug.h&gt;</div><div class='add'>+</div><div class='add'>+/* XX: Figure out how to handle this vma mapping in xe */</div><div class='add'>+struct intel_remapped_plane_info {</div><div class='add'>+	/* in gtt pages */</div><div class='add'>+	u32 offset:31;</div><div class='add'>+	u32 linear:1;</div><div class='add'>+	union {</div><div class='add'>+		/* in gtt pages for !linear */</div><div class='add'>+		struct {</div><div class='add'>+			u16 width;</div><div class='add'>+			u16 height;</div><div class='add'>+			u16 src_stride;</div><div class='add'>+			u16 dst_stride;</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		/* in gtt pages for linear */</div><div class='add'>+		u32 size;</div><div class='add'>+	};</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct intel_remapped_info {</div><div class='add'>+	struct intel_remapped_plane_info plane[4];</div><div class='add'>+	/* in gtt pages */</div><div class='add'>+	u32 plane_alignment;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct intel_rotation_info {</div><div class='add'>+	struct intel_remapped_plane_info plane[2];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+enum i915_gtt_view_type {</div><div class='add'>+	I915_GTT_VIEW_NORMAL = 0,</div><div class='add'>+	I915_GTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),</div><div class='add'>+	I915_GTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline void assert_i915_gem_gtt_types(void)</div><div class='add'>+{</div><div class='add'>+	BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 2 * sizeof(u32) + 8 * sizeof(u16));</div><div class='add'>+	BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 5 * sizeof(u32) + 16 * sizeof(u16));</div><div class='add'>+</div><div class='add'>+	/* Check that rotation/remapped shares offsets for simplicity */</div><div class='add'>+	BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=</div><div class='add'>+		     offsetof(struct intel_rotation_info, plane[0]));</div><div class='add'>+	BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=</div><div class='add'>+		     offsetofend(struct intel_rotation_info, plane[1]));</div><div class='add'>+</div><div class='add'>+	/* As we encode the size of each branch inside the union into its type,</div><div class='add'>+	 * we have to be careful that each branch has a unique size.</div><div class='add'>+	 */</div><div class='add'>+	switch ((enum i915_gtt_view_type)0) {</div><div class='add'>+	case I915_GTT_VIEW_NORMAL:</div><div class='add'>+	case I915_GTT_VIEW_ROTATED:</div><div class='add'>+	case I915_GTT_VIEW_REMAPPED:</div><div class='add'>+		/* gcc complains if these are identical cases */</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct i915_gtt_view {</div><div class='add'>+	enum i915_gtt_view_type type;</div><div class='add'>+	union {</div><div class='add'>+		/* Members need to contain no holes/padding */</div><div class='add'>+		struct intel_rotation_info rotated;</div><div class='add'>+		struct intel_remapped_info remapped;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h<br/>new file mode 100644<br/>index 000000000000..ce986f0e8f38<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/intel_clock_gating.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h<br/>new file mode 100644<br/>index 000000000000..c15806d6c4f7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_GT_TYPES__</div><div class='add'>+#define __INTEL_GT_TYPES__</div><div class='add'>+</div><div class='add'>+#define intel_gt_support_legacy_fencing(gt) 0</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h<br/>new file mode 100644<br/>index 000000000000..55b316985340<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/intel_mchbar_regs.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h<br/>new file mode 100644<br/>index 000000000000..8c15867fd613<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/intel_pci_config.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h<br/>new file mode 100644<br/>index 000000000000..0c47661bdc6a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_PCODE_H__</div><div class='add'>+#define __INTEL_PCODE_H__</div><div class='add'>+</div><div class='add'>+#include "intel_uncore.h"</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,</div><div class='add'>+			int fast_timeout_us, int slow_timeout_ms)</div><div class='add'>+{</div><div class='add'>+	return xe_pcode_write_timeout(__compat_uncore_to_gt(uncore), mbox, val,</div><div class='add'>+				      slow_timeout_ms ?: 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+	return xe_pcode_write(__compat_uncore_to_gt(uncore), mbox, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)</div><div class='add'>+{</div><div class='add'>+	return xe_pcode_read(__compat_uncore_to_gt(uncore), mbox, val, val1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+skl_pcode_request(struct intel_uncore *uncore, u32 mbox,</div><div class='add'>+		  u32 request, u32 reply_mask, u32 reply,</div><div class='add'>+		  int timeout_base_ms)</div><div class='add'>+{</div><div class='add'>+	return xe_pcode_request(__compat_uncore_to_gt(uncore), mbox, request, reply_mask, reply,</div><div class='add'>+				timeout_base_ms);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* __INTEL_PCODE_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h<br/>new file mode 100644<br/>index 000000000000..89da3cc62f39<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "intel_wakeref.h"</div><div class='add'>+</div><div class='add'>+#define intel_runtime_pm xe_runtime_pm</div><div class='add'>+</div><div class='add'>+static inline void disable_rpm_wakeref_asserts(void *rpm)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void enable_rpm_wakeref_asserts(void *rpm)</div><div class='add'>+{</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h<br/>new file mode 100644<br/>index 000000000000..0006ef812346<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_step.h</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_STEP_H__</div><div class='add'>+#define __INTEL_STEP_H__</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+</div><div class='add'>+#define intel_display_step_name xe_display_step_name</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+const char *xe_display_step_name(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe_step_name(xe-&gt;info.step.display);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* __INTEL_STEP_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h<br/>new file mode 100644<br/>index 000000000000..009745328992<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_uc_fw.h</a></div><div class='hunk'>@@ -0,0 +1,11 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _INTEL_UC_FW_H_</div><div class='add'>+#define _INTEL_UC_FW_H_</div><div class='add'>+</div><div class='add'>+#define INTEL_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git"</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h<br/>new file mode 100644<br/>index 000000000000..cd26ddc0f69e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h</a></div><div class='hunk'>@@ -0,0 +1,175 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_UNCORE_H__</div><div class='add'>+#define __INTEL_UNCORE_H__</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *__compat_uncore_to_gt(struct intel_uncore *uncore)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);</div><div class='add'>+</div><div class='add'>+	return xe_root_mmio_gt(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_read(struct intel_uncore *uncore,</div><div class='add'>+				    i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_read8(struct intel_uncore *uncore,</div><div class='add'>+				     i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read8(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_read16(struct intel_uncore *uncore,</div><div class='add'>+				      i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read16(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64</div><div class='add'>+intel_uncore_read64_2x32(struct intel_uncore *uncore,</div><div class='add'>+			 i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));</div><div class='add'>+	struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));</div><div class='add'>+	u32 upper, lower, old_upper;</div><div class='add'>+	int loop = 0;</div><div class='add'>+</div><div class='add'>+	upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);</div><div class='add'>+	do {</div><div class='add'>+		old_upper = upper;</div><div class='add'>+		lower = xe_mmio_read32(__compat_uncore_to_gt(uncore), lower_reg);</div><div class='add'>+		upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);</div><div class='add'>+	} while (upper != old_upper &amp;&amp; loop++ &lt; 2);</div><div class='add'>+</div><div class='add'>+	return (u64)upper &lt;&lt; 32 | lower;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_uncore_posting_read(struct intel_uncore *uncore,</div><div class='add'>+					     i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_uncore_write(struct intel_uncore *uncore,</div><div class='add'>+				      i915_reg_t i915_reg, u32 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,</div><div class='add'>+				   i915_reg_t i915_reg, u32 clear, u32 set)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_rmw32(__compat_uncore_to_gt(uncore), reg, clear, set);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int intel_wait_for_register(struct intel_uncore *uncore,</div><div class='add'>+					  i915_reg_t i915_reg, u32 mask,</div><div class='add'>+					  u32 value, unsigned int timeout)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,</div><div class='add'>+			      timeout * USEC_PER_MSEC, NULL, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int intel_wait_for_register_fw(struct intel_uncore *uncore,</div><div class='add'>+					     i915_reg_t i915_reg, u32 mask,</div><div class='add'>+					     u32 value, unsigned int timeout)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,</div><div class='add'>+			      timeout * USEC_PER_MSEC, NULL, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+__intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,</div><div class='add'>+			  u32 mask, u32 value, unsigned int fast_timeout_us,</div><div class='add'>+			  unsigned int slow_timeout_ms, u32 *out_value)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,</div><div class='add'>+			      fast_timeout_us + 1000 * slow_timeout_ms,</div><div class='add'>+			      out_value, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,</div><div class='add'>+				       i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_uncore_write_fw(struct intel_uncore *uncore,</div><div class='add'>+					 i915_reg_t i915_reg, u32 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,</div><div class='add'>+					    i915_reg_t i915_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,</div><div class='add'>+					      i915_reg_t i915_reg, u32 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);</div><div class='add'>+</div><div class='add'>+	return xe_device_get_root_tile(xe)-&gt;mmio.regs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The raw_reg_{read,write} macros are intended as a micro-optimization for</div><div class='add'>+ * interrupt handlers so that the pointer indirection on uncore-&gt;regs can</div><div class='add'>+ * be computed once (and presumably cached in a register) instead of generating</div><div class='add'>+ * extra load instructions for each MMIO access.</div><div class='add'>+ *</div><div class='add'>+ * Given that these macros are only intended for non-GSI interrupt registers</div><div class='add'>+ * (and the goal is to avoid extra instructions generated by the compiler),</div><div class='add'>+ * these macros do not account for uncore-&gt;gsi_offset.  Any caller that needs</div><div class='add'>+ * to use these macros on a GSI register is responsible for adding the</div><div class='add'>+ * appropriate GSI offset to the 'base' parameter.</div><div class='add'>+ */</div><div class='add'>+#define raw_reg_read(base, reg) \</div><div class='add'>+	readl(base + i915_mmio_reg_offset(reg))</div><div class='add'>+#define raw_reg_write(base, reg, value) \</div><div class='add'>+	writel(value, base + i915_mmio_reg_offset(reg))</div><div class='add'>+</div><div class='add'>+#endif /* __INTEL_UNCORE_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h<br/>new file mode 100644<br/>index 000000000000..ecb1c0707706<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h</a></div><div class='hunk'>@@ -0,0 +1,8 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+typedef unsigned long intel_wakeref_t;</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h b/drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h<br/>new file mode 100644<br/>index 000000000000..c2c30ece8f77<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_PXP_H__</div><div class='add'>+#define __INTEL_PXP_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_i915_gem_object;</div><div class='add'>+struct intel_pxp;</div><div class='add'>+</div><div class='add'>+static inline int intel_pxp_key_check(struct intel_pxp *pxp,</div><div class='add'>+				      struct drm_i915_gem_object *obj,</div><div class='add'>+				      bool assign)</div><div class='add'>+{</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool</div><div class='add'>+i915_gem_object_is_protected(const struct drm_i915_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h<br/>new file mode 100644<br/>index 000000000000..65707e20c557<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../../i915/soc/intel_dram.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h<br/>new file mode 100644<br/>index 000000000000..33c5257b3a71<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../../i915/soc/intel_gmch.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h<br/>new file mode 100644<br/>index 000000000000..9c46556d33a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../../i915/soc/intel_pch.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h b/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h<br/>new file mode 100644<br/>index 000000000000..ec6f12de5727<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h</a></div><div class='hunk'>@@ -0,0 +1,132 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2013-2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _VLV_SIDEBAND_H_</div><div class='add'>+#define _VLV_SIDEBAND_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "vlv_sideband_reg.h"</div><div class='add'>+</div><div class='add'>+enum pipe;</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	VLV_IOSF_SB_BUNIT,</div><div class='add'>+	VLV_IOSF_SB_CCK,</div><div class='add'>+	VLV_IOSF_SB_CCU,</div><div class='add'>+	VLV_IOSF_SB_DPIO,</div><div class='add'>+	VLV_IOSF_SB_FLISDSI,</div><div class='add'>+	VLV_IOSF_SB_GPIO,</div><div class='add'>+	VLV_IOSF_SB_NC,</div><div class='add'>+	VLV_IOSF_SB_PUNIT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_iosf_sb_write(struct drm_i915_private *i915,</div><div class='add'>+				     u8 port, u32 reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_bunit_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_bunit_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_cck_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_cck_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_ccu_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_ccu_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_dpio_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_dpio_read(struct drm_i915_private *i915, int pipe, int reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_dpio_write(struct drm_i915_private *i915,</div><div class='add'>+				  int pipe, int reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_dpio_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_flisdsi_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_flisdsi_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_nc_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_nc_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline void vlv_punit_get(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+static inline u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+static inline void vlv_punit_put(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* _VLV_SIDEBAND_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h b/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h<br/>new file mode 100644<br/>index 000000000000..949f134ce3cf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "../../i915/vlv_sideband_reg.h"</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c<br/>new file mode 100644<br/>index 000000000000..bee191a4a97d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/ext/i915_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/ext/i915_irq.c</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "i915_irq.h"</div><div class='add'>+#include "i915_reg.h"</div><div class='add'>+#include "intel_uncore.h"</div><div class='add'>+</div><div class='add'>+void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,</div><div class='add'>+		    i915_reg_t iir, i915_reg_t ier)</div><div class='add'>+{</div><div class='add'>+	intel_uncore_write(uncore, imr, 0xffffffff);</div><div class='add'>+	intel_uncore_posting_read(uncore, imr);</div><div class='add'>+</div><div class='add'>+	intel_uncore_write(uncore, ier, 0);</div><div class='add'>+</div><div class='add'>+	/* IIR can theoretically queue up two events. Be paranoid. */</div><div class='add'>+	intel_uncore_write(uncore, iir, 0xffffffff);</div><div class='add'>+	intel_uncore_posting_read(uncore, iir);</div><div class='add'>+	intel_uncore_write(uncore, iir, 0xffffffff);</div><div class='add'>+	intel_uncore_posting_read(uncore, iir);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * We should clear IMR at preinstall/uninstall, and just check at postinstall.</div><div class='add'>+ */</div><div class='add'>+void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);</div><div class='add'>+	u32 val = intel_uncore_read(uncore, reg);</div><div class='add'>+</div><div class='add'>+	if (val == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_WARN(&amp;xe-&gt;drm, 1,</div><div class='add'>+		 "Interrupt register 0x%x is not zero: 0x%08x\n",</div><div class='add'>+		 i915_mmio_reg_offset(reg), val);</div><div class='add'>+	intel_uncore_write(uncore, reg, 0xffffffff);</div><div class='add'>+	intel_uncore_posting_read(uncore, reg);</div><div class='add'>+	intel_uncore_write(uncore, reg, 0xffffffff);</div><div class='add'>+	intel_uncore_posting_read(uncore, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void gen3_irq_init(struct intel_uncore *uncore,</div><div class='add'>+		   i915_reg_t imr, u32 imr_val,</div><div class='add'>+		   i915_reg_t ier, u32 ier_val,</div><div class='add'>+		   i915_reg_t iir)</div><div class='add'>+{</div><div class='add'>+	gen3_assert_iir_is_zero(uncore, iir);</div><div class='add'>+</div><div class='add'>+	intel_uncore_write(uncore, ier, ier_val);</div><div class='add'>+	intel_uncore_write(uncore, imr, imr_val);</div><div class='add'>+	intel_uncore_posting_read(uncore, imr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool intel_irqs_enabled(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * XXX: i915 has a racy handling of the irq.enabled, since it doesn't</div><div class='add'>+	 * lock its transitions. Because of that, the irq.enabled sometimes</div><div class='add'>+	 * is not read with the irq.lock in place.</div><div class='add'>+	 * However, the most critical cases like vblank and page flips are</div><div class='add'>+	 * properly using the locks.</div><div class='add'>+	 * We cannot take the lock in here or run any kind of assert because</div><div class='add'>+	 * of i915 inconsistency.</div><div class='add'>+	 * But at this point the xe irq is better protected against races,</div><div class='add'>+	 * although the full solution would be protecting the i915 side.</div><div class='add'>+	 */</div><div class='add'>+	return xe-&gt;irq.enabled;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_synchronize_irq(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	synchronize_irq(to_pci_dev(xe-&gt;drm.dev)-&gt;irq);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/ext/i915_utils.c b/drivers/gpu/drm/xe/display/ext/i915_utils.c<br/>new file mode 100644<br/>index 000000000000..43b10a2cc508<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/ext/i915_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/ext/i915_utils.c</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+</div><div class='add'>+bool i915_vtd_active(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	if (device_iommu_mapped(i915-&gt;drm.dev))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* Running as a guest, we assume the host is enforcing VT'd */</div><div class='add'>+	return i915_run_as_guest();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)</div><div class='add'>+</div><div class='add'>+/* i915 specific, just put here for shutting it up */</div><div class='add'>+int __i915_inject_probe_error(struct drm_i915_private *i915, int err,</div><div class='add'>+			      const char *func, int line)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c b/drivers/gpu/drm/xe/display/intel_fb_bo.c<br/>new file mode 100644<br/>index 000000000000..b21da7b745a5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/intel_fb_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fb_bo.c</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_modeset_helper.h&gt;</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_fb_bo.h"</div><div class='add'>+</div><div class='add'>+void intel_fb_bo_framebuffer_fini(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo-&gt;flags &amp; XE_BO_CREATE_PINNED_BIT) {</div><div class='add'>+		/* Unpin our kernel fb first */</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		xe_bo_unpin(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+	}</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='add'>+				 struct xe_bo *bo,</div><div class='add'>+				 struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(bo-&gt;ttm.base.dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_bo_get(bo);</div><div class='add'>+</div><div class='add'>+	ret = ttm_bo_reserve(&amp;bo-&gt;ttm, true, false, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!(bo-&gt;flags &amp; XE_BO_SCANOUT_BIT)) {</div><div class='add'>+		/*</div><div class='add'>+		 * XE_BO_SCANOUT_BIT should ideally be set at creation, or is</div><div class='add'>+		 * automatically set when creating FB. We cannot change caching</div><div class='add'>+		 * mode when the boect is VM_BINDed, so we can only set</div><div class='add'>+		 * coherency with display when unbound.</div><div class='add'>+		 */</div><div class='add'>+		if (XE_IOCTL_DBG(i915, !list_empty(&amp;bo-&gt;ttm.base.gpuva.list))) {</div><div class='add'>+			ttm_bo_unreserve(&amp;bo-&gt;ttm);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		bo-&gt;flags |= XE_BO_SCANOUT_BIT;</div><div class='add'>+	}</div><div class='add'>+	ttm_bo_unreserve(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,</div><div class='add'>+					  struct drm_file *filp,</div><div class='add'>+					  const struct drm_mode_fb_cmd2 *mode_cmd)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_gem_object *bo;</div><div class='add'>+	struct drm_gem_object *gem = drm_gem_object_lookup(filp, mode_cmd-&gt;handles[0]);</div><div class='add'>+</div><div class='add'>+	if (!gem)</div><div class='add'>+		return ERR_PTR(-ENOENT);</div><div class='add'>+</div><div class='add'>+	bo = gem_to_xe_bo(gem);</div><div class='add'>+	/* Require vram placement or dma-buf import */</div><div class='add'>+	if (IS_DGFX(i915) &amp;&amp;</div><div class='add'>+	    !xe_bo_can_migrate(gem_to_xe_bo(gem), XE_PL_VRAM0) &amp;&amp;</div><div class='add'>+	    bo-&gt;ttm.type != ttm_bo_type_sg) {</div><div class='add'>+		drm_gem_object_put(gem);</div><div class='add'>+		return ERR_PTR(-EREMOTE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.h b/drivers/gpu/drm/xe/display/intel_fb_bo.h<br/>new file mode 100644<br/>index 000000000000..5d365b925b7a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/intel_fb_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fb_bo.h</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_FB_BO_H__</div><div class='add'>+#define __INTEL_FB_BO_H__</div><div class='add'>+</div><div class='add'>+struct drm_file;</div><div class='add'>+struct drm_mode_fb_cmd2;</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+struct intel_framebuffer;</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+void intel_fb_bo_framebuffer_fini(struct xe_bo *bo);</div><div class='add'>+int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb,</div><div class='add'>+				 struct xe_bo *bo,</div><div class='add'>+				 struct drm_mode_fb_cmd2 *mode_cmd);</div><div class='add'>+</div><div class='add'>+struct xe_bo *intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915,</div><div class='add'>+					  struct drm_file *filp,</div><div class='add'>+					  const struct drm_mode_fb_cmd2 *mode_cmd);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c<br/>new file mode 100644<br/>index 000000000000..51ae3561fd0d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/intel_fbdev_fb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fbdev_fb.c</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "intel_fbdev_fb.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_fb_helper.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,</div><div class='add'>+			 struct drm_fb_helper_surface_size *sizes)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct drm_device *dev = helper-&gt;dev;</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='add'>+	struct drm_mode_fb_cmd2 mode_cmd = {};</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+	int size;</div><div class='add'>+</div><div class='add'>+	/* we don't do packed 24bpp */</div><div class='add'>+	if (sizes-&gt;surface_bpp == 24)</div><div class='add'>+		sizes-&gt;surface_bpp = 32;</div><div class='add'>+</div><div class='add'>+	mode_cmd.width = sizes-&gt;surface_width;</div><div class='add'>+	mode_cmd.height = sizes-&gt;surface_height;</div><div class='add'>+</div><div class='add'>+	mode_cmd.pitches[0] = ALIGN(mode_cmd.width *</div><div class='add'>+				    DIV_ROUND_UP(sizes-&gt;surface_bpp, 8), XE_PAGE_SIZE);</div><div class='add'>+	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes-&gt;surface_bpp,</div><div class='add'>+							  sizes-&gt;surface_depth);</div><div class='add'>+</div><div class='add'>+	size = mode_cmd.pitches[0] * mode_cmd.height;</div><div class='add'>+	size = PAGE_ALIGN(size);</div><div class='add'>+	obj = ERR_PTR(-ENODEV);</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(dev_priv)) {</div><div class='add'>+		obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv),</div><div class='add'>+					   NULL, size,</div><div class='add'>+					   ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |</div><div class='add'>+					   XE_BO_CREATE_STOLEN_BIT |</div><div class='add'>+					   XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+		if (!IS_ERR(obj))</div><div class='add'>+			drm_info(&amp;dev_priv-&gt;drm, "Allocated fbdev into stolen\n");</div><div class='add'>+		else</div><div class='add'>+			drm_info(&amp;dev_priv-&gt;drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj));</div><div class='add'>+	}</div><div class='add'>+	if (IS_ERR(obj)) {</div><div class='add'>+		obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv), NULL, size,</div><div class='add'>+					  ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(dev_priv)) |</div><div class='add'>+					  XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(obj)) {</div><div class='add'>+		drm_err(&amp;dev_priv-&gt;drm, "failed to allocate framebuffer (%pe)\n", obj);</div><div class='add'>+		fb = ERR_PTR(-ENOMEM);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fb = intel_framebuffer_create(obj, &amp;mode_cmd);</div><div class='add'>+	if (IS_ERR(fb)) {</div><div class='add'>+		xe_bo_unpin_map_no_vm(obj);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_gem_object_put(intel_bo_to_drm_bo(obj));</div><div class='add'>+	return fb;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return fb;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,</div><div class='add'>+			      struct drm_i915_gem_object *obj, struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(i915-&gt;drm.dev);</div><div class='add'>+</div><div class='add'>+	if (!(obj-&gt;flags &amp; XE_BO_CREATE_SYSTEM_BIT)) {</div><div class='add'>+		if (obj-&gt;flags &amp; XE_BO_CREATE_STOLEN_BIT)</div><div class='add'>+			info-&gt;fix.smem_start = xe_ttm_stolen_io_offset(obj, 0);</div><div class='add'>+		else</div><div class='add'>+			info-&gt;fix.smem_start =</div><div class='add'>+				pci_resource_start(pdev, 2) +</div><div class='add'>+				xe_bo_addr(obj, 0, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+		info-&gt;fix.smem_len = obj-&gt;ttm.base.size;</div><div class='add'>+	} else {</div><div class='add'>+		/* XXX: Pure fiction, as the BO may not be physically accessible.. */</div><div class='add'>+		info-&gt;fix.smem_start = 0;</div><div class='add'>+		info-&gt;fix.smem_len = obj-&gt;ttm.base.size;</div><div class='add'>+	}</div><div class='add'>+	XE_WARN_ON(iosys_map_is_null(&amp;obj-&gt;vmap));</div><div class='add'>+</div><div class='add'>+	info-&gt;screen_base = obj-&gt;vmap.vaddr_iomem;</div><div class='add'>+	info-&gt;screen_size = intel_bo_to_drm_bo(obj)-&gt;size;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h b/drivers/gpu/drm/xe/display/intel_fbdev_fb.h<br/>new file mode 100644<br/>index 000000000000..ea186772e0bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/intel_fbdev_fb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/intel_fbdev_fb.h</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __INTEL_FBDEV_FB_H__</div><div class='add'>+#define __INTEL_FBDEV_FB_H__</div><div class='add'>+</div><div class='add'>+struct drm_fb_helper;</div><div class='add'>+struct drm_fb_helper_surface_size;</div><div class='add'>+struct drm_i915_gem_object;</div><div class='add'>+struct drm_i915_private;</div><div class='add'>+struct fb_info;</div><div class='add'>+struct i915_vma;</div><div class='add'>+</div><div class='add'>+struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,</div><div class='add'>+			 struct drm_fb_helper_surface_size *sizes);</div><div class='add'>+int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info,</div><div class='add'>+			      struct drm_i915_gem_object *obj, struct i915_vma *vma);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_display_misc.c b/drivers/gpu/drm/xe/display/xe_display_misc.c<br/>new file mode 100644<br/>index 000000000000..242c2ef4ca93<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_display_misc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_display_misc.c</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+</div><div class='add'>+struct pci_dev;</div><div class='add'>+</div><div class='add'>+unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode);</div><div class='add'>+</div><div class='add'>+unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode)</div><div class='add'>+{</div><div class='add'>+	/* ToDo: Implement the actual handling of vga decode */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_display_rps.c b/drivers/gpu/drm/xe/display/xe_display_rps.c<br/>new file mode 100644<br/>index 000000000000..ab21c581c192<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_display_rps.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_display_rps.c</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "intel_display_rps.h"</div><div class='add'>+</div><div class='add'>+void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc,</div><div class='add'>+					  struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_display_rps_mark_interactive(struct drm_i915_private *i915,</div><div class='add'>+					struct intel_atomic_state *state,</div><div class='add'>+					bool interactive)</div><div class='add'>+{</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c<br/>new file mode 100644<br/>index 000000000000..27c2fb1c002a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_dsb_buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_dsb_buffer.c</a></div><div class='hunk'>@@ -0,0 +1,71 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023, Intel Corporation.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "i915_vma.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_dsb_buffer.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+</div><div class='add'>+u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)</div><div class='add'>+{</div><div class='add'>+	return xe_bo_ggtt_addr(dsb_buf-&gt;vma-&gt;bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)</div><div class='add'>+{</div><div class='add'>+	iosys_map_wr(&amp;dsb_buf-&gt;vma-&gt;bo-&gt;vmap, idx * 4, u32, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)</div><div class='add'>+{</div><div class='add'>+	return iosys_map_rd(&amp;dsb_buf-&gt;vma-&gt;bo-&gt;vmap, idx * 4, u32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)</div><div class='add'>+{</div><div class='add'>+	WARN_ON(idx &gt; (dsb_buf-&gt;buf_size - size) / sizeof(*dsb_buf-&gt;cmd_buf));</div><div class='add'>+</div><div class='add'>+	iosys_map_memset(&amp;dsb_buf-&gt;vma-&gt;bo-&gt;vmap, idx * 4, val, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct drm_i915_private *i915 = to_i915(crtc-&gt;base.dev);</div><div class='add'>+	struct drm_i915_gem_object *obj;</div><div class='add'>+	struct i915_vma *vma;</div><div class='add'>+</div><div class='add'>+	vma = kzalloc(sizeof(*vma), GFP_KERNEL);</div><div class='add'>+	if (!vma)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915),</div><div class='add'>+				   NULL, PAGE_ALIGN(size),</div><div class='add'>+				   ttm_bo_type_kernel,</div><div class='add'>+				   XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) |</div><div class='add'>+				   XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(obj)) {</div><div class='add'>+		kfree(vma);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vma-&gt;bo = obj;</div><div class='add'>+	dsb_buf-&gt;vma = vma;</div><div class='add'>+	dsb_buf-&gt;buf_size = size;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)</div><div class='add'>+{</div><div class='add'>+	xe_bo_unpin_map_no_vm(dsb_buf-&gt;vma-&gt;bo);</div><div class='add'>+	kfree(dsb_buf-&gt;vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)</div><div class='add'>+{</div><div class='add'>+	/* TODO: add xe specific flush_map() for dsb buffer object. */</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c<br/>new file mode 100644<br/>index 000000000000..722c84a56607<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_fb_pin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_fb_pin.c</a></div><div class='hunk'>@@ -0,0 +1,384 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_dpt.h"</div><div class='add'>+#include "intel_fb.h"</div><div class='add'>+#include "intel_fb_pin.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_bo.h&gt;</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ofs,</div><div class='add'>+		  u32 width, u32 height, u32 src_stride, u32 dst_stride)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)-&gt;mem.ggtt;</div><div class='add'>+	u32 column, row;</div><div class='add'>+</div><div class='add'>+	/* TODO: Maybe rewrite so we can traverse the bo addresses sequentially,</div><div class='add'>+	 * by writing dpt/ggtt in a different order?</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	for (column = 0; column &lt; width; column++) {</div><div class='add'>+		u32 src_idx = src_stride * (height - 1) + column + bo_ofs;</div><div class='add'>+</div><div class='add'>+		for (row = 0; row &lt; height; row++) {</div><div class='add'>+			u64 pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,</div><div class='add'>+							      xe-&gt;pat.idx[XE_CACHE_WB]);</div><div class='add'>+</div><div class='add'>+			iosys_map_wr(map, *dpt_ofs, u64, pte);</div><div class='add'>+			*dpt_ofs += 8;</div><div class='add'>+			src_idx -= src_stride;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* The DE ignores the PTEs for the padding tiles */</div><div class='add'>+		*dpt_ofs += (dst_stride - height) * 8;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Align to next page */</div><div class='add'>+	*dpt_ofs = ALIGN(*dpt_ofs, 4096);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,</div><div class='add'>+		   u32 bo_ofs, u32 width, u32 height, u32 src_stride,</div><div class='add'>+		   u32 dst_stride)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)-&gt;mem.ggtt;</div><div class='add'>+	u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index)</div><div class='add'>+		= ggtt-&gt;pt_ops-&gt;pte_encode_bo;</div><div class='add'>+	u32 column, row;</div><div class='add'>+</div><div class='add'>+	for (row = 0; row &lt; height; row++) {</div><div class='add'>+		u32 src_idx = src_stride * row + bo_ofs;</div><div class='add'>+</div><div class='add'>+		for (column = 0; column &lt; width; column++) {</div><div class='add'>+			iosys_map_wr(map, *dpt_ofs, u64,</div><div class='add'>+				     pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,</div><div class='add'>+				     xe-&gt;pat.idx[XE_CACHE_WB]));</div><div class='add'>+</div><div class='add'>+			*dpt_ofs += 8;</div><div class='add'>+			src_idx++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* The DE ignores the PTEs for the padding tiles */</div><div class='add'>+		*dpt_ofs += (dst_stride - width) * 8;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Align to next page */</div><div class='add'>+	*dpt_ofs = ALIGN(*dpt_ofs, 4096);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,</div><div class='add'>+			       const struct i915_gtt_view *view,</div><div class='add'>+			       struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(fb-&gt;base.dev);</div><div class='add'>+	struct xe_tile *tile0 = xe_device_get_root_tile(xe);</div><div class='add'>+	struct xe_ggtt *ggtt = tile0-&gt;mem.ggtt;</div><div class='add'>+	struct xe_bo *bo = intel_fb_obj(&amp;fb-&gt;base), *dpt;</div><div class='add'>+	u32 dpt_size, size = bo-&gt;ttm.base.size;</div><div class='add'>+</div><div class='add'>+	if (view-&gt;type == I915_GTT_VIEW_NORMAL)</div><div class='add'>+		dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);</div><div class='add'>+	else if (view-&gt;type == I915_GTT_VIEW_REMAPPED)</div><div class='add'>+		dpt_size = ALIGN(intel_remapped_info_size(&amp;fb-&gt;remapped_view.gtt.remapped) * 8,</div><div class='add'>+				 XE_PAGE_SIZE);</div><div class='add'>+	else</div><div class='add'>+		/* display uses 4K tiles instead of bytes here, convert to entries.. */</div><div class='add'>+		dpt_size = ALIGN(intel_rotation_info_size(&amp;view-&gt;rotated) * 8,</div><div class='add'>+				 XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,</div><div class='add'>+					   ttm_bo_type_kernel,</div><div class='add'>+					   XE_BO_CREATE_VRAM0_BIT |</div><div class='add'>+					   XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	else</div><div class='add'>+		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,</div><div class='add'>+					   ttm_bo_type_kernel,</div><div class='add'>+					   XE_BO_CREATE_STOLEN_BIT |</div><div class='add'>+					   XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(dpt))</div><div class='add'>+		dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,</div><div class='add'>+					   ttm_bo_type_kernel,</div><div class='add'>+					   XE_BO_CREATE_SYSTEM_BIT |</div><div class='add'>+					   XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(dpt))</div><div class='add'>+		return PTR_ERR(dpt);</div><div class='add'>+</div><div class='add'>+	if (view-&gt;type == I915_GTT_VIEW_NORMAL) {</div><div class='add'>+		u32 x;</div><div class='add'>+</div><div class='add'>+		for (x = 0; x &lt; size / XE_PAGE_SIZE; x++) {</div><div class='add'>+			u64 pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(bo, x * XE_PAGE_SIZE,</div><div class='add'>+							      xe-&gt;pat.idx[XE_CACHE_WB]);</div><div class='add'>+</div><div class='add'>+			iosys_map_wr(&amp;dpt-&gt;vmap, x * 8, u64, pte);</div><div class='add'>+		}</div><div class='add'>+	} else if (view-&gt;type == I915_GTT_VIEW_REMAPPED) {</div><div class='add'>+		const struct intel_remapped_info *remap_info = &amp;view-&gt;remapped;</div><div class='add'>+		u32 i, dpt_ofs = 0;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(remap_info-&gt;plane); i++)</div><div class='add'>+			write_dpt_remapped(bo, &amp;dpt-&gt;vmap, &amp;dpt_ofs,</div><div class='add'>+					   remap_info-&gt;plane[i].offset,</div><div class='add'>+					   remap_info-&gt;plane[i].width,</div><div class='add'>+					   remap_info-&gt;plane[i].height,</div><div class='add'>+					   remap_info-&gt;plane[i].src_stride,</div><div class='add'>+					   remap_info-&gt;plane[i].dst_stride);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		const struct intel_rotation_info *rot_info = &amp;view-&gt;rotated;</div><div class='add'>+		u32 i, dpt_ofs = 0;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(rot_info-&gt;plane); i++)</div><div class='add'>+			write_dpt_rotated(bo, &amp;dpt-&gt;vmap, &amp;dpt_ofs,</div><div class='add'>+					  rot_info-&gt;plane[i].offset,</div><div class='add'>+					  rot_info-&gt;plane[i].width,</div><div class='add'>+					  rot_info-&gt;plane[i].height,</div><div class='add'>+					  rot_info-&gt;plane[i].src_stride,</div><div class='add'>+					  rot_info-&gt;plane[i].dst_stride);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vma-&gt;dpt = dpt;</div><div class='add'>+	vma-&gt;node = dpt-&gt;ggtt_node;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo_ofs,</div><div class='add'>+		   u32 width, u32 height, u32 src_stride, u32 dst_stride)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	u32 column, row;</div><div class='add'>+</div><div class='add'>+	for (column = 0; column &lt; width; column++) {</div><div class='add'>+		u32 src_idx = src_stride * (height - 1) + column + bo_ofs;</div><div class='add'>+</div><div class='add'>+		for (row = 0; row &lt; height; row++) {</div><div class='add'>+			u64 pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,</div><div class='add'>+							      xe-&gt;pat.idx[XE_CACHE_WB]);</div><div class='add'>+</div><div class='add'>+			xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);</div><div class='add'>+			*ggtt_ofs += XE_PAGE_SIZE;</div><div class='add'>+			src_idx -= src_stride;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* The DE ignores the PTEs for the padding tiles */</div><div class='add'>+		*ggtt_ofs += (dst_stride - height) * XE_PAGE_SIZE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,</div><div class='add'>+				const struct i915_gtt_view *view,</div><div class='add'>+				struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = intel_fb_obj(&amp;fb-&gt;base);</div><div class='add'>+	struct xe_device *xe = to_xe_device(fb-&gt;base.dev);</div><div class='add'>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)-&gt;mem.ggtt;</div><div class='add'>+	u32 align;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* TODO: Consider sharing framebuffer mapping?</div><div class='add'>+	 * embed i915_vma inside intel_framebuffer</div><div class='add'>+	 */</div><div class='add'>+	xe_device_mem_access_get(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;ggtt-&gt;lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	align = XE_PAGE_SIZE;</div><div class='add'>+	if (xe_bo_is_vram(bo) &amp;&amp; ggtt-&gt;flags &amp; XE_GGTT_FLAGS_64K)</div><div class='add'>+		align = max_t(u32, align, SZ_64K);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ggtt_node.size &amp;&amp; view-&gt;type == I915_GTT_VIEW_NORMAL) {</div><div class='add'>+		vma-&gt;node = bo-&gt;ggtt_node;</div><div class='add'>+	} else if (view-&gt;type == I915_GTT_VIEW_NORMAL) {</div><div class='add'>+		u32 x, size = bo-&gt;ttm.base.size;</div><div class='add'>+</div><div class='add'>+		ret = xe_ggtt_insert_special_node_locked(ggtt, &amp;vma-&gt;node, size,</div><div class='add'>+							 align, 0);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out_unlock;</div><div class='add'>+</div><div class='add'>+		for (x = 0; x &lt; size; x += XE_PAGE_SIZE) {</div><div class='add'>+			u64 pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(bo, x,</div><div class='add'>+							      xe-&gt;pat.idx[XE_CACHE_WB]);</div><div class='add'>+</div><div class='add'>+			xe_ggtt_set_pte(ggtt, vma-&gt;node.start + x, pte);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		u32 i, ggtt_ofs;</div><div class='add'>+		const struct intel_rotation_info *rot_info = &amp;view-&gt;rotated;</div><div class='add'>+</div><div class='add'>+		/* display seems to use tiles instead of bytes here, so convert it back.. */</div><div class='add'>+		u32 size = intel_rotation_info_size(rot_info) * XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+		ret = xe_ggtt_insert_special_node_locked(ggtt, &amp;vma-&gt;node, size,</div><div class='add'>+							 align, 0);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out_unlock;</div><div class='add'>+</div><div class='add'>+		ggtt_ofs = vma-&gt;node.start;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(rot_info-&gt;plane); i++)</div><div class='add'>+			write_ggtt_rotated(bo, ggtt, &amp;ggtt_ofs,</div><div class='add'>+					   rot_info-&gt;plane[i].offset,</div><div class='add'>+					   rot_info-&gt;plane[i].width,</div><div class='add'>+					   rot_info-&gt;plane[i].height,</div><div class='add'>+					   rot_info-&gt;plane[i].src_stride,</div><div class='add'>+					   rot_info-&gt;plane[i].dst_stride);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_ggtt_invalidate(ggtt);</div><div class='add'>+out_unlock:</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+out:</div><div class='add'>+	xe_device_mem_access_put(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct i915_vma *__xe_pin_fb_vma(struct intel_framebuffer *fb,</div><div class='add'>+					const struct i915_gtt_view *view)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = fb-&gt;base.dev;</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);</div><div class='add'>+	struct xe_bo *bo = intel_fb_obj(&amp;fb-&gt;base);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!vma)</div><div class='add'>+		return ERR_PTR(-ENODEV);</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(to_xe_device(bo-&gt;ttm.base.dev)) &amp;&amp;</div><div class='add'>+	    intel_fb_rc_ccs_cc_plane(&amp;fb-&gt;base) &gt;= 0 &amp;&amp;</div><div class='add'>+	    !(bo-&gt;flags &amp; XE_BO_NEEDS_CPU_ACCESS)) {</div><div class='add'>+		struct xe_tile *tile = xe_device_get_root_tile(xe);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If we need to able to access the clear-color value stored in</div><div class='add'>+		 * the buffer, then we require that such buffers are also CPU</div><div class='add'>+		 * accessible.  This is important on small-bar systems where</div><div class='add'>+		 * only some subset of VRAM is CPU accessible.</div><div class='add'>+		 */</div><div class='add'>+		if (tile-&gt;mem.vram.io_size &lt; tile-&gt;mem.vram.usable_size) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Pin the framebuffer, we can't use xe_bo_(un)pin functions as the</div><div class='add'>+	 * assumptions are incorrect for framebuffers</div><div class='add'>+	 */</div><div class='add'>+	ret = ttm_bo_reserve(&amp;bo-&gt;ttm, false, false, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		ret = xe_bo_migrate(bo, XE_PL_VRAM0);</div><div class='add'>+	else</div><div class='add'>+		ret = xe_bo_validate(bo, NULL, true);</div><div class='add'>+	if (!ret)</div><div class='add'>+		ttm_bo_pin(&amp;bo-&gt;ttm);</div><div class='add'>+	ttm_bo_unreserve(&amp;bo-&gt;ttm);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	vma-&gt;bo = bo;</div><div class='add'>+	if (intel_fb_uses_dpt(&amp;fb-&gt;base))</div><div class='add'>+		ret = __xe_pin_fb_vma_dpt(fb, view, vma);</div><div class='add'>+	else</div><div class='add'>+		ret = __xe_pin_fb_vma_ggtt(fb, view, vma);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_unpin;</div><div class='add'>+</div><div class='add'>+	return vma;</div><div class='add'>+</div><div class='add'>+err_unpin:</div><div class='add'>+	ttm_bo_reserve(&amp;bo-&gt;ttm, false, false, NULL);</div><div class='add'>+	ttm_bo_unpin(&amp;bo-&gt;ttm);</div><div class='add'>+	ttm_bo_unreserve(&amp;bo-&gt;ttm);</div><div class='add'>+err:</div><div class='add'>+	kfree(vma);</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_unpin_fb_vma(struct i915_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(vma-&gt;bo-&gt;ttm.base.dev);</div><div class='add'>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)-&gt;mem.ggtt;</div><div class='add'>+</div><div class='add'>+	if (vma-&gt;dpt)</div><div class='add'>+		xe_bo_unpin_map_no_vm(vma-&gt;dpt);</div><div class='add'>+	else if (!drm_mm_node_allocated(&amp;vma-&gt;bo-&gt;ggtt_node) ||</div><div class='add'>+		 vma-&gt;bo-&gt;ggtt_node.start != vma-&gt;node.start)</div><div class='add'>+		xe_ggtt_remove_node(ggtt, &amp;vma-&gt;node);</div><div class='add'>+</div><div class='add'>+	ttm_bo_reserve(&amp;vma-&gt;bo-&gt;ttm, false, false, NULL);</div><div class='add'>+	ttm_bo_unpin(&amp;vma-&gt;bo-&gt;ttm);</div><div class='add'>+	ttm_bo_unreserve(&amp;vma-&gt;bo-&gt;ttm);</div><div class='add'>+	kfree(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct i915_vma *</div><div class='add'>+intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,</div><div class='add'>+			   bool phys_cursor,</div><div class='add'>+			   const struct i915_gtt_view *view,</div><div class='add'>+			   bool uses_fence,</div><div class='add'>+			   unsigned long *out_flags)</div><div class='add'>+{</div><div class='add'>+	*out_flags = 0;</div><div class='add'>+</div><div class='add'>+	return __xe_pin_fb_vma(to_intel_framebuffer(fb), view);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	__xe_unpin_fb_vma(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_plane_pin_fb(struct intel_plane_state *plane_state)</div><div class='add'>+{</div><div class='add'>+	struct drm_framebuffer *fb = plane_state-&gt;hw.fb;</div><div class='add'>+	struct xe_bo *bo = intel_fb_obj(fb);</div><div class='add'>+	struct i915_vma *vma;</div><div class='add'>+</div><div class='add'>+	/* We reject creating !SCANOUT fb's, so this is weird.. */</div><div class='add'>+	drm_WARN_ON(bo-&gt;ttm.base.dev, !(bo-&gt;flags &amp; XE_BO_SCANOUT_BIT));</div><div class='add'>+</div><div class='add'>+	vma = __xe_pin_fb_vma(to_intel_framebuffer(fb), &amp;plane_state-&gt;view.gtt);</div><div class='add'>+	if (IS_ERR(vma))</div><div class='add'>+		return PTR_ERR(vma);</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;ggtt_vma = vma;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)</div><div class='add'>+{</div><div class='add'>+	__xe_unpin_fb_vma(old_plane_state-&gt;ggtt_vma);</div><div class='add'>+	old_plane_state-&gt;ggtt_vma = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * For Xe introduce dummy intel_dpt_create which just return NULL and</div><div class='add'>+ * intel_dpt_destroy which does nothing.</div><div class='add'>+ */</div><div class='add'>+struct i915_address_space *intel_dpt_create(struct intel_framebuffer *fb)</div><div class='add'>+{</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_dpt_destroy(struct i915_address_space *vm)</div><div class='add'>+{</div><div class='add'>+	return;</div><div class='add'>+}
\ No newline at end of file</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c<br/>new file mode 100644<br/>index 000000000000..0f11a39333e2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_hdcp_gsc.c</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2023, Intel Corporation.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_hdcp_gsc.h"</div><div class='add'>+</div><div class='add'>+bool intel_hdcp_gsc_cs_required(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool intel_hdcp_gsc_check_status(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int intel_hdcp_gsc_init(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+	drm_info(&amp;i915-&gt;drm, "HDCP support not yet implemented\n");</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_hdcp_gsc_fini(struct drm_i915_private *i915)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+ssize_t intel_hdcp_gsc_msg_send(struct drm_i915_private *i915, u8 *msg_in,</div><div class='add'>+				size_t msg_in_len, u8 *msg_out,</div><div class='add'>+				size_t msg_out_len)</div><div class='add'>+{</div><div class='add'>+	return -ENODEV;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c<br/>new file mode 100644<br/>index 000000000000..ccf83c12b545<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/display/xe_plane_initial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/display/xe_plane_initial.c</a></div><div class='hunk'>@@ -0,0 +1,291 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* for ioread64 */</div><div class='add'>+#include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+</div><div class='add'>+#include "i915_drv.h"</div><div class='add'>+#include "intel_atomic_plane.h"</div><div class='add'>+#include "intel_display.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_fb.h"</div><div class='add'>+#include "intel_fb_pin.h"</div><div class='add'>+#include "intel_frontbuffer.h"</div><div class='add'>+#include "intel_plane_initial.h"</div><div class='add'>+</div><div class='add'>+static bool</div><div class='add'>+intel_reuse_initial_plane_obj(struct drm_i915_private *i915,</div><div class='add'>+			      const struct intel_initial_plane_config *plane_config,</div><div class='add'>+			      struct drm_framebuffer **fb)</div><div class='add'>+{</div><div class='add'>+	struct intel_crtc *crtc;</div><div class='add'>+</div><div class='add'>+	for_each_intel_crtc(&amp;i915-&gt;drm, crtc) {</div><div class='add'>+		struct intel_crtc_state *crtc_state =</div><div class='add'>+			to_intel_crtc_state(crtc-&gt;base.state);</div><div class='add'>+		struct intel_plane *plane =</div><div class='add'>+			to_intel_plane(crtc-&gt;base.primary);</div><div class='add'>+		struct intel_plane_state *plane_state =</div><div class='add'>+			to_intel_plane_state(plane-&gt;base.state);</div><div class='add'>+</div><div class='add'>+		if (!crtc_state-&gt;uapi.active)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!plane_state-&gt;ggtt_vma)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (intel_plane_ggtt_offset(plane_state) == plane_config-&gt;base) {</div><div class='add'>+			*fb = plane_state-&gt;hw.fb;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_bo *</div><div class='add'>+initial_plane_bo(struct xe_device *xe,</div><div class='add'>+		 struct intel_initial_plane_config *plane_config)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile0 = xe_device_get_root_tile(xe);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	resource_size_t phys_base;</div><div class='add'>+	u32 base, size, flags;</div><div class='add'>+	u64 page_size = xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;</div><div class='add'>+</div><div class='add'>+	if (plane_config-&gt;size == 0)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	flags = XE_BO_CREATE_PINNED_BIT | XE_BO_SCANOUT_BIT | XE_BO_CREATE_GGTT_BIT;</div><div class='add'>+</div><div class='add'>+	base = round_down(plane_config-&gt;base, page_size);</div><div class='add'>+	if (IS_DGFX(xe)) {</div><div class='add'>+		u64 __iomem *gte = tile0-&gt;mem.ggtt-&gt;gsm;</div><div class='add'>+		u64 pte;</div><div class='add'>+</div><div class='add'>+		gte += base / XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+		pte = ioread64(gte);</div><div class='add'>+		if (!(pte &amp; XE_GGTT_PTE_DM)) {</div><div class='add'>+			drm_err(&amp;xe-&gt;drm,</div><div class='add'>+				"Initial plane programming missing DM bit\n");</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		phys_base = pte &amp; ~(page_size - 1);</div><div class='add'>+		flags |= XE_BO_CREATE_VRAM0_BIT;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * We don't currently expect this to ever be placed in the</div><div class='add'>+		 * stolen portion.</div><div class='add'>+		 */</div><div class='add'>+		if (phys_base &gt;= tile0-&gt;mem.vram.usable_size) {</div><div class='add'>+			drm_err(&amp;xe-&gt;drm,</div><div class='add'>+				"Initial plane programming using invalid range, phys_base=%pa\n",</div><div class='add'>+				&amp;phys_base);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+			"Using phys_base=%pa, based on initial plane programming\n",</div><div class='add'>+			&amp;phys_base);</div><div class='add'>+	} else {</div><div class='add'>+		struct ttm_resource_manager *stolen = ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_STOLEN);</div><div class='add'>+</div><div class='add'>+		if (!stolen)</div><div class='add'>+			return NULL;</div><div class='add'>+		phys_base = base;</div><div class='add'>+		flags |= XE_BO_CREATE_STOLEN_BIT;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If the FB is too big, just don't use it since fbdev is not very</div><div class='add'>+		 * important and we should probably use that space with FBC or other</div><div class='add'>+		 * features.</div><div class='add'>+		 */</div><div class='add'>+		if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &amp;&amp;</div><div class='add'>+		    plane_config-&gt;size * 2 &gt;&gt; PAGE_SHIFT &gt;= stolen-&gt;size)</div><div class='add'>+			return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = round_up(plane_config-&gt;base + plane_config-&gt;size,</div><div class='add'>+			page_size);</div><div class='add'>+	size -= base;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base,</div><div class='add'>+				     ttm_bo_type_kernel, flags);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+			"Failed to create bo phys_base=%pa size %u with flags %x: %li\n",</div><div class='add'>+			&amp;phys_base, size, flags, PTR_ERR(bo));</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool</div><div class='add'>+intel_alloc_initial_plane_obj(struct intel_crtc *crtc,</div><div class='add'>+			      struct intel_initial_plane_config *plane_config)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = crtc-&gt;base.dev;</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='add'>+	struct drm_mode_fb_cmd2 mode_cmd = { 0 };</div><div class='add'>+	struct drm_framebuffer *fb = &amp;plane_config-&gt;fb-&gt;base;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	switch (fb-&gt;modifier) {</div><div class='add'>+	case DRM_FORMAT_MOD_LINEAR:</div><div class='add'>+	case I915_FORMAT_MOD_X_TILED:</div><div class='add'>+	case I915_FORMAT_MOD_Y_TILED:</div><div class='add'>+	case I915_FORMAT_MOD_4_TILED:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_dbg(&amp;dev_priv-&gt;drm,</div><div class='add'>+			"Unsupported modifier for initial FB: 0x%llx\n",</div><div class='add'>+			fb-&gt;modifier);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode_cmd.pixel_format = fb-&gt;format-&gt;format;</div><div class='add'>+	mode_cmd.width = fb-&gt;width;</div><div class='add'>+	mode_cmd.height = fb-&gt;height;</div><div class='add'>+	mode_cmd.pitches[0] = fb-&gt;pitches[0];</div><div class='add'>+	mode_cmd.modifier[0] = fb-&gt;modifier;</div><div class='add'>+	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;</div><div class='add'>+</div><div class='add'>+	bo = initial_plane_bo(dev_priv, plane_config);</div><div class='add'>+	if (!bo)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (intel_framebuffer_init(to_intel_framebuffer(fb),</div><div class='add'>+				   bo, &amp;mode_cmd)) {</div><div class='add'>+		drm_dbg_kms(&amp;dev_priv-&gt;drm, "intel fb init failed\n");</div><div class='add'>+		goto err_bo;</div><div class='add'>+	}</div><div class='add'>+	/* Reference handed over to fb */</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+</div><div class='add'>+err_bo:</div><div class='add'>+	xe_bo_unpin_map_no_vm(bo);</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+intel_find_initial_plane_obj(struct intel_crtc *crtc,</div><div class='add'>+			     struct intel_initial_plane_config *plane_config)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = crtc-&gt;base.dev;</div><div class='add'>+	struct drm_i915_private *dev_priv = to_i915(dev);</div><div class='add'>+	struct intel_plane *plane =</div><div class='add'>+		to_intel_plane(crtc-&gt;base.primary);</div><div class='add'>+	struct intel_plane_state *plane_state =</div><div class='add'>+		to_intel_plane_state(plane-&gt;base.state);</div><div class='add'>+	struct intel_crtc_state *crtc_state =</div><div class='add'>+		to_intel_crtc_state(crtc-&gt;base.state);</div><div class='add'>+	struct drm_framebuffer *fb;</div><div class='add'>+	struct i915_vma *vma;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TODO:</div><div class='add'>+	 *   Disable planes if get_initial_plane_config() failed.</div><div class='add'>+	 *   Make sure things work if the surface base is not page aligned.</div><div class='add'>+	 */</div><div class='add'>+	if (!plane_config-&gt;fb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (intel_alloc_initial_plane_obj(crtc, plane_config))</div><div class='add'>+		fb = &amp;plane_config-&gt;fb-&gt;base;</div><div class='add'>+	else if (!intel_reuse_initial_plane_obj(dev_priv, plane_config, &amp;fb))</div><div class='add'>+		goto nofb;</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;uapi.rotation = plane_config-&gt;rotation;</div><div class='add'>+	intel_fb_fill_view(to_intel_framebuffer(fb),</div><div class='add'>+			   plane_state-&gt;uapi.rotation, &amp;plane_state-&gt;view);</div><div class='add'>+</div><div class='add'>+	vma = intel_pin_and_fence_fb_obj(fb, false, &amp;plane_state-&gt;view.gtt,</div><div class='add'>+					 false, &amp;plane_state-&gt;flags);</div><div class='add'>+	if (IS_ERR(vma))</div><div class='add'>+		goto nofb;</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;ggtt_vma = vma;</div><div class='add'>+	plane_state-&gt;uapi.src_x = 0;</div><div class='add'>+	plane_state-&gt;uapi.src_y = 0;</div><div class='add'>+	plane_state-&gt;uapi.src_w = fb-&gt;width &lt;&lt; 16;</div><div class='add'>+	plane_state-&gt;uapi.src_h = fb-&gt;height &lt;&lt; 16;</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;uapi.crtc_x = 0;</div><div class='add'>+	plane_state-&gt;uapi.crtc_y = 0;</div><div class='add'>+	plane_state-&gt;uapi.crtc_w = fb-&gt;width;</div><div class='add'>+	plane_state-&gt;uapi.crtc_h = fb-&gt;height;</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;uapi.fb = fb;</div><div class='add'>+	drm_framebuffer_get(fb);</div><div class='add'>+</div><div class='add'>+	plane_state-&gt;uapi.crtc = &amp;crtc-&gt;base;</div><div class='add'>+	intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);</div><div class='add'>+</div><div class='add'>+	atomic_or(plane-&gt;frontbuffer_bit, &amp;to_intel_frontbuffer(fb)-&gt;bits);</div><div class='add'>+</div><div class='add'>+	plane_config-&gt;vma = vma;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Flip to the newly created mapping ASAP, so we can re-use the</div><div class='add'>+	 * first part of GGTT for WOPCM, prevent flickering, and prevent</div><div class='add'>+	 * the lookup of sysmem scratch pages.</div><div class='add'>+	 */</div><div class='add'>+	plane-&gt;check_plane(crtc_state, plane_state);</div><div class='add'>+	plane-&gt;async_flip(plane, crtc_state, plane_state, true);</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+nofb:</div><div class='add'>+	/*</div><div class='add'>+	 * We've failed to reconstruct the BIOS FB.  Current display state</div><div class='add'>+	 * indicates that the primary plane is visible, but has a NULL FB,</div><div class='add'>+	 * which will lead to problems later if we don't fix it up.  The</div><div class='add'>+	 * simplest solution is to just disable the primary plane now and</div><div class='add'>+	 * pretend the BIOS never had it enabled.</div><div class='add'>+	 */</div><div class='add'>+	intel_plane_disable_noatomic(crtc, plane);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void plane_config_fini(struct intel_initial_plane_config *plane_config)</div><div class='add'>+{</div><div class='add'>+	if (plane_config-&gt;fb) {</div><div class='add'>+		struct drm_framebuffer *fb = &amp;plane_config-&gt;fb-&gt;base;</div><div class='add'>+</div><div class='add'>+		/* We may only have the stub and not a full framebuffer */</div><div class='add'>+		if (drm_framebuffer_read_refcount(fb))</div><div class='add'>+			drm_framebuffer_put(fb);</div><div class='add'>+		else</div><div class='add'>+			kfree(fb);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void intel_crtc_initial_plane_config(struct intel_crtc *crtc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(crtc-&gt;base.dev);</div><div class='add'>+	struct intel_initial_plane_config plane_config = {};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note that reserving the BIOS fb up front prevents us</div><div class='add'>+	 * from stuffing other stolen allocations like the ring</div><div class='add'>+	 * on top.  This prevents some ugliness at boot time, and</div><div class='add'>+	 * can even allow for smooth boot transitions if the BIOS</div><div class='add'>+	 * fb is large enough for the active pipe configuration.</div><div class='add'>+	 */</div><div class='add'>+	xe-&gt;display.funcs.display-&gt;get_initial_plane_config(crtc, &amp;plane_config);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If the fb is shared between multiple heads, we'll</div><div class='add'>+	 * just get the first one.</div><div class='add'>+	 */</div><div class='add'>+	intel_find_initial_plane_obj(crtc, &amp;plane_config);</div><div class='add'>+</div><div class='add'>+	plane_config_fini(&amp;plane_config);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h b/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h<br/>new file mode 100644<br/>index 000000000000..8e6dd061f2ae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GFXPIPE_COMMANDS_H_</div><div class='add'>+#define _XE_GFXPIPE_COMMANDS_H_</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_instr_defs.h"</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_PIPELINE		REG_GENMASK(28, 27)</div><div class='add'>+#define   PIPELINE_COMMON		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x0)</div><div class='add'>+#define   PIPELINE_SINGLE_DW		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x1)</div><div class='add'>+#define   PIPELINE_COMPUTE		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x2)</div><div class='add'>+#define   PIPELINE_3D			REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x3)</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_OPCODE			REG_GENMASK(26, 24)</div><div class='add'>+#define GFXPIPE_SUBOPCODE		REG_GENMASK(23, 16)</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_MATCH_MASK		(XE_INSTR_CMD_TYPE | \</div><div class='add'>+					 GFXPIPE_PIPELINE | \</div><div class='add'>+					 GFXPIPE_OPCODE | \</div><div class='add'>+					 GFXPIPE_SUBOPCODE)</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_COMMON_CMD(opcode, subopcode) \</div><div class='add'>+	(XE_INSTR_GFXPIPE | PIPELINE_COMMON | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_SINGLE_DW_CMD(opcode, subopcode) \</div><div class='add'>+	(XE_INSTR_GFXPIPE | PIPELINE_SINGLE_DW | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_3D_CMD(opcode, subopcode) \</div><div class='add'>+	(XE_INSTR_GFXPIPE | PIPELINE_3D | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))</div><div class='add'>+</div><div class='add'>+#define GFXPIPE_COMPUTE_CMD(opcode, subopcode) \</div><div class='add'>+	(XE_INSTR_GFXPIPE | PIPELINE_COMPUTE | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \</div><div class='add'>+	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))</div><div class='add'>+</div><div class='add'>+#define STATE_BASE_ADDRESS			GFXPIPE_COMMON_CMD(0x1, 0x1)</div><div class='add'>+#define STATE_SIP				GFXPIPE_COMMON_CMD(0x1, 0x2)</div><div class='add'>+#define GPGPU_CSR_BASE_ADDRESS			GFXPIPE_COMMON_CMD(0x1, 0x4)</div><div class='add'>+#define STATE_COMPUTE_MODE			GFXPIPE_COMMON_CMD(0x1, 0x5)</div><div class='add'>+#define CMD_3DSTATE_BTD				GFXPIPE_COMMON_CMD(0x1, 0x6)</div><div class='add'>+</div><div class='add'>+#define CMD_3DSTATE_VF_STATISTICS		GFXPIPE_SINGLE_DW_CMD(0x0, 0xB)</div><div class='add'>+</div><div class='add'>+#define PIPELINE_SELECT				GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)</div><div class='add'>+</div><div class='add'>+#define CMD_3DSTATE_DRAWING_RECTANGLE_FAST	GFXPIPE_3D_CMD(0x0, 0x0)</div><div class='add'>+#define CMD_3DSTATE_CLEAR_PARAMS		GFXPIPE_3D_CMD(0x0, 0x4)</div><div class='add'>+#define CMD_3DSTATE_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x5)</div><div class='add'>+#define CMD_3DSTATE_STENCIL_BUFFER		GFXPIPE_3D_CMD(0x0, 0x6)</div><div class='add'>+#define CMD_3DSTATE_HIER_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x7)</div><div class='add'>+#define CMD_3DSTATE_VERTEX_BUFFERS		GFXPIPE_3D_CMD(0x0, 0x8)</div><div class='add'>+#define CMD_3DSTATE_VERTEX_ELEMENTS		GFXPIPE_3D_CMD(0x0, 0x9)</div><div class='add'>+#define CMD_3DSTATE_INDEX_BUFFER		GFXPIPE_3D_CMD(0x0, 0xA)</div><div class='add'>+#define CMD_3DSTATE_VF				GFXPIPE_3D_CMD(0x0, 0xC)</div><div class='add'>+#define CMD_3DSTATE_MULTISAMPLE			GFXPIPE_3D_CMD(0x0, 0xD)</div><div class='add'>+#define CMD_3DSTATE_CC_STATE_POINTERS		GFXPIPE_3D_CMD(0x0, 0xE)</div><div class='add'>+#define CMD_3DSTATE_SCISSOR_STATE_POINTERS	GFXPIPE_3D_CMD(0x0, 0xF)</div><div class='add'>+#define CMD_3DSTATE_VS				GFXPIPE_3D_CMD(0x0, 0x10)</div><div class='add'>+#define CMD_3DSTATE_GS				GFXPIPE_3D_CMD(0x0, 0x11)</div><div class='add'>+#define CMD_3DSTATE_CLIP			GFXPIPE_3D_CMD(0x0, 0x12)</div><div class='add'>+#define CMD_3DSTATE_SF				GFXPIPE_3D_CMD(0x0, 0x13)</div><div class='add'>+#define CMD_3DSTATE_WM				GFXPIPE_3D_CMD(0x0, 0x14)</div><div class='add'>+#define CMD_3DSTATE_CONSTANT_VS			GFXPIPE_3D_CMD(0x0, 0x15)</div><div class='add'>+#define CMD_3DSTATE_CONSTANT_GS			GFXPIPE_3D_CMD(0x0, 0x16)</div><div class='add'>+#define CMD_3DSTATE_SAMPLE_MASK			GFXPIPE_3D_CMD(0x0, 0x18)</div><div class='add'>+#define CMD_3DSTATE_CONSTANT_HS			GFXPIPE_3D_CMD(0x0, 0x19)</div><div class='add'>+#define CMD_3DSTATE_CONSTANT_DS			GFXPIPE_3D_CMD(0x0, 0x1A)</div><div class='add'>+#define CMD_3DSTATE_HS				GFXPIPE_3D_CMD(0x0, 0x1B)</div><div class='add'>+#define CMD_3DSTATE_TE				GFXPIPE_3D_CMD(0x0, 0x1C)</div><div class='add'>+#define CMD_3DSTATE_DS				GFXPIPE_3D_CMD(0x0, 0x1D)</div><div class='add'>+#define CMD_3DSTATE_STREAMOUT			GFXPIPE_3D_CMD(0x0, 0x1E)</div><div class='add'>+#define CMD_3DSTATE_SBE				GFXPIPE_3D_CMD(0x0, 0x1F)</div><div class='add'>+#define CMD_3DSTATE_PS				GFXPIPE_3D_CMD(0x0, 0x20)</div><div class='add'>+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP	GFXPIPE_3D_CMD(0x0, 0x21)</div><div class='add'>+#define CMD_3DSTATE_CPS_POINTERS		GFXPIPE_3D_CMD(0x0, 0x22)</div><div class='add'>+#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC	GFXPIPE_3D_CMD(0x0, 0x23)</div><div class='add'>+#define CMD_3DSTATE_BLEND_STATE_POINTERS	GFXPIPE_3D_CMD(0x0, 0x24)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POINTERS_VS	GFXPIPE_3D_CMD(0x0, 0x26)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POINTERS_HS	GFXPIPE_3D_CMD(0x0, 0x27)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POINTERS_DS	GFXPIPE_3D_CMD(0x0, 0x28)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POINTERS_GS	GFXPIPE_3D_CMD(0x0, 0x29)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POINTERS_PS	GFXPIPE_3D_CMD(0x0, 0x2A)</div><div class='add'>+#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_VS	GFXPIPE_3D_CMD(0x0, 0x2B)</div><div class='add'>+#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_HS	GFXPIPE_3D_CMD(0x0, 0x2C)</div><div class='add'>+#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_DS	GFXPIPE_3D_CMD(0x0, 0x2D)</div><div class='add'>+#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_GS	GFXPIPE_3D_CMD(0x0, 0x2E)</div><div class='add'>+#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_PS	GFXPIPE_3D_CMD(0x0, 0x2F)</div><div class='add'>+#define CMD_3DSTATE_VF_INSTANCING		GFXPIPE_3D_CMD(0x0, 0x49)</div><div class='add'>+#define CMD_3DSTATE_VF_SGVS			GFXPIPE_3D_CMD(0x0, 0x4A)</div><div class='add'>+#define CMD_3DSTATE_VF_TOPOLOGY			GFXPIPE_3D_CMD(0x0, 0x4B)</div><div class='add'>+#define CMD_3DSTATE_WM_CHROMAKEY		GFXPIPE_3D_CMD(0x0, 0x4C)</div><div class='add'>+#define CMD_3DSTATE_PS_BLEND			GFXPIPE_3D_CMD(0x0, 0x4D)</div><div class='add'>+#define CMD_3DSTATE_WM_DEPTH_STENCIL		GFXPIPE_3D_CMD(0x0, 0x4E)</div><div class='add'>+#define CMD_3DSTATE_PS_EXTRA			GFXPIPE_3D_CMD(0x0, 0x4F)</div><div class='add'>+#define CMD_3DSTATE_RASTER			GFXPIPE_3D_CMD(0x0, 0x50)</div><div class='add'>+#define CMD_3DSTATE_SBE_SWIZ			GFXPIPE_3D_CMD(0x0, 0x51)</div><div class='add'>+#define CMD_3DSTATE_WM_HZ_OP			GFXPIPE_3D_CMD(0x0, 0x52)</div><div class='add'>+#define CMD_3DSTATE_VF_COMPONENT_PACKING	GFXPIPE_3D_CMD(0x0, 0x55)</div><div class='add'>+#define CMD_3DSTATE_VF_SGVS_2			GFXPIPE_3D_CMD(0x0, 0x56)</div><div class='add'>+#define CMD_3DSTATE_VFG				GFXPIPE_3D_CMD(0x0, 0x57)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_VS		GFXPIPE_3D_CMD(0x0, 0x58)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_HS		GFXPIPE_3D_CMD(0x0, 0x59)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_DS		GFXPIPE_3D_CMD(0x0, 0x5A)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_GS		GFXPIPE_3D_CMD(0x0, 0x5B)</div><div class='add'>+#define CMD_3DSTATE_SO_BUFFER_INDEX_0		GFXPIPE_3D_CMD(0x0, 0x60)</div><div class='add'>+#define CMD_3DSTATE_SO_BUFFER_INDEX_1		GFXPIPE_3D_CMD(0x0, 0x61)</div><div class='add'>+#define CMD_3DSTATE_SO_BUFFER_INDEX_2		GFXPIPE_3D_CMD(0x0, 0x62)</div><div class='add'>+#define CMD_3DSTATE_SO_BUFFER_INDEX_3		GFXPIPE_3D_CMD(0x0, 0x63)</div><div class='add'>+#define CMD_3DSTATE_PRIMITIVE_REPLICATION	GFXPIPE_3D_CMD(0x0, 0x6C)</div><div class='add'>+#define CMD_3DSTATE_TBIMR_TILE_PASS_INFO	GFXPIPE_3D_CMD(0x0, 0x6E)</div><div class='add'>+#define CMD_3DSTATE_AMFS			GFXPIPE_3D_CMD(0x0, 0x6F)</div><div class='add'>+#define CMD_3DSTATE_DEPTH_BOUNDS		GFXPIPE_3D_CMD(0x0, 0x71)</div><div class='add'>+#define CMD_3DSTATE_AMFS_TEXTURE_POINTERS	GFXPIPE_3D_CMD(0x0, 0x72)</div><div class='add'>+#define CMD_3DSTATE_CONSTANT_TS_POINTER		GFXPIPE_3D_CMD(0x0, 0x73)</div><div class='add'>+#define CMD_3DSTATE_MESH_CONTROL		GFXPIPE_3D_CMD(0x0, 0x77)</div><div class='add'>+#define CMD_3DSTATE_MESH_DISTRIB		GFXPIPE_3D_CMD(0x0, 0x78)</div><div class='add'>+#define CMD_3DSTATE_TASK_REDISTRIB		GFXPIPE_3D_CMD(0x0, 0x79)</div><div class='add'>+#define CMD_3DSTATE_MESH_SHADER			GFXPIPE_3D_CMD(0x0, 0x7A)</div><div class='add'>+#define CMD_3DSTATE_MESH_SHADER_DATA		GFXPIPE_3D_CMD(0x0, 0x7B)</div><div class='add'>+#define CMD_3DSTATE_TASK_CONTROL		GFXPIPE_3D_CMD(0x0, 0x7C)</div><div class='add'>+#define CMD_3DSTATE_TASK_SHADER			GFXPIPE_3D_CMD(0x0, 0x7D)</div><div class='add'>+#define CMD_3DSTATE_TASK_SHADER_DATA		GFXPIPE_3D_CMD(0x0, 0x7E)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_MESH		GFXPIPE_3D_CMD(0x0, 0x7F)</div><div class='add'>+#define CMD_3DSTATE_URB_ALLOC_TASK		GFXPIPE_3D_CMD(0x0, 0x80)</div><div class='add'>+#define CMD_3DSTATE_CLIP_MESH			GFXPIPE_3D_CMD(0x0, 0x81)</div><div class='add'>+#define CMD_3DSTATE_SBE_MESH			GFXPIPE_3D_CMD(0x0, 0x82)</div><div class='add'>+#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER	GFXPIPE_3D_CMD(0x0, 0x83)</div><div class='add'>+</div><div class='add'>+#define CMD_3DSTATE_DRAWING_RECTANGLE		GFXPIPE_3D_CMD(0x1, 0x0)</div><div class='add'>+#define CMD_3DSTATE_CHROMA_KEY			GFXPIPE_3D_CMD(0x1, 0x4)</div><div class='add'>+#define CMD_3DSTATE_POLY_STIPPLE_OFFSET		GFXPIPE_3D_CMD(0x1, 0x6)</div><div class='add'>+#define CMD_3DSTATE_POLY_STIPPLE_PATTERN	GFXPIPE_3D_CMD(0x1, 0x7)</div><div class='add'>+#define CMD_3DSTATE_LINE_STIPPLE		GFXPIPE_3D_CMD(0x1, 0x8)</div><div class='add'>+#define CMD_3DSTATE_AA_LINE_PARAMETERS		GFXPIPE_3D_CMD(0x1, 0xA)</div><div class='add'>+#define CMD_3DSTATE_MONOFILTER_SIZE		GFXPIPE_3D_CMD(0x1, 0x11)</div><div class='add'>+#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_VS	GFXPIPE_3D_CMD(0x1, 0x12)</div><div class='add'>+#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_HS	GFXPIPE_3D_CMD(0x1, 0x13)</div><div class='add'>+#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_DS	GFXPIPE_3D_CMD(0x1, 0x14)</div><div class='add'>+#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_GS	GFXPIPE_3D_CMD(0x1, 0x15)</div><div class='add'>+#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_PS	GFXPIPE_3D_CMD(0x1, 0x16)</div><div class='add'>+#define CMD_3DSTATE_SO_DECL_LIST		GFXPIPE_3D_CMD(0x1, 0x17)</div><div class='add'>+#define   CMD_3DSTATE_SO_DECL_LIST_DW_LEN	REG_GENMASK(8, 0)</div><div class='add'>+#define CMD_3DSTATE_SO_BUFFER			GFXPIPE_3D_CMD(0x1, 0x18)</div><div class='add'>+#define CMD_3DSTATE_BINDING_TABLE_POOL_ALLOC	GFXPIPE_3D_CMD(0x1, 0x19)</div><div class='add'>+#define CMD_3DSTATE_SAMPLE_PATTERN		GFXPIPE_3D_CMD(0x1, 0x1C)</div><div class='add'>+#define CMD_3DSTATE_3D_MODE			GFXPIPE_3D_CMD(0x1, 0x1E)</div><div class='add'>+#define CMD_3DSTATE_SUBSLICE_HASH_TABLE		GFXPIPE_3D_CMD(0x1, 0x1F)</div><div class='add'>+#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS	GFXPIPE_3D_CMD(0x1, 0x20)</div><div class='add'>+#define CMD_3DSTATE_PTBR_TILE_PASS_INFO		GFXPIPE_3D_CMD(0x1, 0x22)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/instructions/xe_gsc_commands.h b/drivers/gpu/drm/xe/instructions/xe_gsc_commands.h<br/>new file mode 100644<br/>index 000000000000..f8949cad9d0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/instructions/xe_gsc_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_gsc_commands.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GSC_COMMANDS_H_</div><div class='add'>+#define _XE_GSC_COMMANDS_H_</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_instr_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * All GSCCS-specific commands have fixed length, so we can include it in the</div><div class='add'>+ * defines. Note that the generic GSC command header structure includes an</div><div class='add'>+ * optional data field in bits 9-21, but there are no commands that actually use</div><div class='add'>+ * it; some of the commands are instead defined as having an extended length</div><div class='add'>+ * field spanning bits 0-15, even if the extra bits are not required because the</div><div class='add'>+ * longest GSCCS command is only 8 dwords. To handle this, the defines below use</div><div class='add'>+ * a single field for both data and len. If we ever get a commands that does</div><div class='add'>+ * actually have data and this approach doesn't work for it we can re-work it</div><div class='add'>+ * at that point.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define GSC_OPCODE		REG_GENMASK(28, 22)</div><div class='add'>+#define GSC_CMD_DATA_AND_LEN	REG_GENMASK(21, 0)</div><div class='add'>+</div><div class='add'>+#define __GSC_INSTR(op, dl) \</div><div class='add'>+	(XE_INSTR_GSC | \</div><div class='add'>+	REG_FIELD_PREP(GSC_OPCODE, op) | \</div><div class='add'>+	REG_FIELD_PREP(GSC_CMD_DATA_AND_LEN, dl))</div><div class='add'>+</div><div class='add'>+#define GSC_HECI_CMD_PKT __GSC_INSTR(0, 6)</div><div class='add'>+</div><div class='add'>+#define GSC_FW_LOAD __GSC_INSTR(1, 2)</div><div class='add'>+#define   GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/instructions/xe_instr_defs.h b/drivers/gpu/drm/xe/instructions/xe_instr_defs.h<br/>new file mode 100644<br/>index 000000000000..04179b2a48e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/instructions/xe_instr_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_instr_defs.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_INSTR_DEFS_H_</div><div class='add'>+#define _XE_INSTR_DEFS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The first dword of any GPU instruction is the "instruction header."  Bits</div><div class='add'>+ * 31:29 identify the general type of the command and determine how exact</div><div class='add'>+ * opcodes and sub-opcodes will be encoded in the remaining bits.</div><div class='add'>+ */</div><div class='add'>+#define XE_INSTR_CMD_TYPE		GENMASK(31, 29)</div><div class='add'>+#define   XE_INSTR_MI			REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)</div><div class='add'>+#define   XE_INSTR_GSC			REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)</div><div class='add'>+#define   XE_INSTR_GFXPIPE		REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Most (but not all) instructions have a "length" field in the instruction</div><div class='add'>+ * header.  The value expected is the total number of dwords for the</div><div class='add'>+ * instruction, minus two.</div><div class='add'>+ *</div><div class='add'>+ * Some instructions have length fields longer or shorter than 8 bits, but</div><div class='add'>+ * those are rare.  This definition can be used for the common case where</div><div class='add'>+ * the length field is from 7:0.</div><div class='add'>+ */</div><div class='add'>+#define XE_INSTR_LEN_MASK		GENMASK(7, 0)</div><div class='add'>+#define XE_INSTR_NUM_DW(x)		REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h<br/>new file mode 100644<br/>index 000000000000..1cfa96167fde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/instructions/xe_mi_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/instructions/xe_mi_commands.h</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MI_COMMANDS_H_</div><div class='add'>+#define _XE_MI_COMMANDS_H_</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_instr_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * MI (Memory Interface) commands are supported by all GT engines.  They</div><div class='add'>+ * provide general memory operations and command streamer control.  MI commands</div><div class='add'>+ * have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction</div><div class='add'>+ * header dword and a specific MI opcode in bits 28:23.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define MI_OPCODE			REG_GENMASK(28, 23)</div><div class='add'>+#define MI_SUBOPCODE			REG_GENMASK(22, 17)  /* used with MI_EXPANSION */</div><div class='add'>+</div><div class='add'>+#define __MI_INSTR(opcode) \</div><div class='add'>+	(XE_INSTR_MI | REG_FIELD_PREP(MI_OPCODE, opcode))</div><div class='add'>+</div><div class='add'>+#define MI_NOOP				__MI_INSTR(0x0)</div><div class='add'>+#define MI_USER_INTERRUPT		__MI_INSTR(0x2)</div><div class='add'>+#define MI_ARB_CHECK			__MI_INSTR(0x5)</div><div class='add'>+</div><div class='add'>+#define MI_ARB_ON_OFF			__MI_INSTR(0x8)</div><div class='add'>+#define   MI_ARB_ENABLE			REG_BIT(0)</div><div class='add'>+#define   MI_ARB_DISABLE		0x0</div><div class='add'>+</div><div class='add'>+#define MI_BATCH_BUFFER_END		__MI_INSTR(0xA)</div><div class='add'>+#define MI_TOPOLOGY_FILTER		__MI_INSTR(0xD)</div><div class='add'>+#define MI_FORCE_WAKEUP			__MI_INSTR(0x1D)</div><div class='add'>+</div><div class='add'>+#define MI_STORE_DATA_IMM		__MI_INSTR(0x20)</div><div class='add'>+#define   MI_SDI_GGTT			REG_BIT(22)</div><div class='add'>+#define   MI_SDI_LEN_DW			GENMASK(9, 0)</div><div class='add'>+#define   MI_SDI_NUM_DW(x)		REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)</div><div class='add'>+#define   MI_SDI_NUM_QW(x)		(REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \</div><div class='add'>+					 REG_BIT(21))</div><div class='add'>+</div><div class='add'>+#define MI_LOAD_REGISTER_IMM		__MI_INSTR(0x22)</div><div class='add'>+#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)</div><div class='add'>+#define   MI_LRI_MMIO_REMAP_EN		REG_BIT(17)</div><div class='add'>+#define   MI_LRI_NUM_REGS(x)		XE_INSTR_NUM_DW(2 * (x) + 1)</div><div class='add'>+#define   MI_LRI_FORCE_POSTED		REG_BIT(12)</div><div class='add'>+</div><div class='add'>+#define MI_FLUSH_DW			__MI_INSTR(0x26)</div><div class='add'>+#define   MI_FLUSH_DW_STORE_INDEX	REG_BIT(21)</div><div class='add'>+#define   MI_INVALIDATE_TLB		REG_BIT(18)</div><div class='add'>+#define   MI_FLUSH_DW_CCS		REG_BIT(16)</div><div class='add'>+#define   MI_FLUSH_DW_OP_STOREDW	REG_BIT(14)</div><div class='add'>+#define   MI_FLUSH_DW_LEN_DW		REG_GENMASK(5, 0)</div><div class='add'>+#define   MI_FLUSH_IMM_DW		REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2)</div><div class='add'>+#define   MI_FLUSH_IMM_QW		REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)</div><div class='add'>+#define   MI_FLUSH_DW_USE_GTT		REG_BIT(2)</div><div class='add'>+</div><div class='add'>+#define MI_BATCH_BUFFER_START		__MI_INSTR(0x31)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h<br/>new file mode 100644<br/>index 000000000000..5592774fc690<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_engine_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_engine_regs.h</a></div><div class='hunk'>@@ -0,0 +1,184 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_ENGINE_REGS_H_</div><div class='add'>+#define _XE_ENGINE_REGS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;asm/page.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * These *_BASE values represent the MMIO offset where each hardware engine's</div><div class='add'>+ * registers start.  The other definitions in this header are parameterized</div><div class='add'>+ * macros that will take one of these values as a parameter.</div><div class='add'>+ */</div><div class='add'>+#define RENDER_RING_BASE			0x02000</div><div class='add'>+#define BSD_RING_BASE				0x1c0000</div><div class='add'>+#define BSD2_RING_BASE				0x1c4000</div><div class='add'>+#define BSD3_RING_BASE				0x1d0000</div><div class='add'>+#define BSD4_RING_BASE				0x1d4000</div><div class='add'>+#define XEHP_BSD5_RING_BASE			0x1e0000</div><div class='add'>+#define XEHP_BSD6_RING_BASE			0x1e4000</div><div class='add'>+#define XEHP_BSD7_RING_BASE			0x1f0000</div><div class='add'>+#define XEHP_BSD8_RING_BASE			0x1f4000</div><div class='add'>+#define VEBOX_RING_BASE				0x1c8000</div><div class='add'>+#define VEBOX2_RING_BASE			0x1d8000</div><div class='add'>+#define XEHP_VEBOX3_RING_BASE			0x1e8000</div><div class='add'>+#define XEHP_VEBOX4_RING_BASE			0x1f8000</div><div class='add'>+#define COMPUTE0_RING_BASE			0x1a000</div><div class='add'>+#define COMPUTE1_RING_BASE			0x1c000</div><div class='add'>+#define COMPUTE2_RING_BASE			0x1e000</div><div class='add'>+#define COMPUTE3_RING_BASE			0x26000</div><div class='add'>+#define BLT_RING_BASE				0x22000</div><div class='add'>+#define XEHPC_BCS1_RING_BASE			0x3e0000</div><div class='add'>+#define XEHPC_BCS2_RING_BASE			0x3e2000</div><div class='add'>+#define XEHPC_BCS3_RING_BASE			0x3e4000</div><div class='add'>+#define XEHPC_BCS4_RING_BASE			0x3e6000</div><div class='add'>+#define XEHPC_BCS5_RING_BASE			0x3e8000</div><div class='add'>+#define XEHPC_BCS6_RING_BASE			0x3ea000</div><div class='add'>+#define XEHPC_BCS7_RING_BASE			0x3ec000</div><div class='add'>+#define XEHPC_BCS8_RING_BASE			0x3ee000</div><div class='add'>+#define GSCCS_RING_BASE				0x11a000</div><div class='add'>+</div><div class='add'>+#define RING_TAIL(base)				XE_REG((base) + 0x30)</div><div class='add'>+</div><div class='add'>+#define RING_HEAD(base)				XE_REG((base) + 0x34)</div><div class='add'>+#define   HEAD_ADDR				0x001FFFFC</div><div class='add'>+</div><div class='add'>+#define RING_START(base)			XE_REG((base) + 0x38)</div><div class='add'>+</div><div class='add'>+#define RING_CTL(base)				XE_REG((base) + 0x3c)</div><div class='add'>+#define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -&gt; pages */</div><div class='add'>+#define   RING_CTL_SIZE(size)			((size) - PAGE_SIZE) /* in bytes -&gt; pages */</div><div class='add'>+</div><div class='add'>+#define RING_PSMI_CTL(base)			XE_REG((base) + 0x50, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)</div><div class='add'>+#define   WAIT_FOR_EVENT_POWER_DOWN_DISABLE	REG_BIT(7)</div><div class='add'>+#define   IDLE_MSG_DISABLE			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define RING_PWRCTX_MAXCNT(base)		XE_REG((base) + 0x54)</div><div class='add'>+#define   IDLE_WAIT_TIME			REG_GENMASK(19, 0)</div><div class='add'>+</div><div class='add'>+#define RING_ACTHD_UDW(base)			XE_REG((base) + 0x5c)</div><div class='add'>+#define RING_DMA_FADD_UDW(base)			XE_REG((base) + 0x60)</div><div class='add'>+#define RING_IPEHR(base)			XE_REG((base) + 0x68)</div><div class='add'>+#define RING_ACTHD(base)			XE_REG((base) + 0x74)</div><div class='add'>+#define RING_DMA_FADD(base)			XE_REG((base) + 0x78)</div><div class='add'>+#define RING_HWS_PGA(base)			XE_REG((base) + 0x80)</div><div class='add'>+#define RING_HWSTAM(base)			XE_REG((base) + 0x98)</div><div class='add'>+#define RING_MI_MODE(base)			XE_REG((base) + 0x9c)</div><div class='add'>+#define RING_NOPID(base)			XE_REG((base) + 0x94)</div><div class='add'>+</div><div class='add'>+#define FF_THREAD_MODE(base)			XE_REG((base) + 0xa0)</div><div class='add'>+#define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)</div><div class='add'>+</div><div class='add'>+#define RING_IMR(base)				XE_REG((base) + 0xa8)</div><div class='add'>+</div><div class='add'>+#define RING_EIR(base)				XE_REG((base) + 0xb0)</div><div class='add'>+#define RING_EMR(base)				XE_REG((base) + 0xb4)</div><div class='add'>+#define RING_ESR(base)				XE_REG((base) + 0xb8)</div><div class='add'>+</div><div class='add'>+#define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)</div><div class='add'>+/*</div><div class='add'>+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.</div><div class='add'>+ * The lsb of each can be considered a separate enabling bit for encryption.</div><div class='add'>+ * 6:0 == default MOCS value for reads  =&gt;  6:1 == table index for reads.</div><div class='add'>+ * 13:7 == default MOCS value for writes =&gt; 13:8 == table index for writes.</div><div class='add'>+ * 15:14 == Reserved =&gt; 31:30 are set to 0.</div><div class='add'>+ */</div><div class='add'>+#define   CMD_CCTL_WRITE_OVERRIDE_MASK		REG_GENMASK(13, 8)</div><div class='add'>+#define   CMD_CCTL_READ_OVERRIDE_MASK		REG_GENMASK(6, 1)</div><div class='add'>+</div><div class='add'>+#define CSFE_CHICKEN1(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)</div><div class='add'>+#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)</div><div class='add'>+</div><div class='add'>+#define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)</div><div class='add'>+</div><div class='add'>+#define FF_SLICE_CS_CHICKEN2(base)		XE_REG((base) + 0xe4, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   PERF_FIX_BALANCING_CFE_DISABLE	REG_BIT(15)</div><div class='add'>+</div><div class='add'>+#define CS_DEBUG_MODE1(base)			XE_REG((base) + 0xec, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   FF_DOP_CLOCK_GATE_DISABLE		REG_BIT(1)</div><div class='add'>+#define   REPLAY_MODE_GRANULARITY		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define RING_BBADDR(base)			XE_REG((base) + 0x140)</div><div class='add'>+#define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)</div><div class='add'>+</div><div class='add'>+#define BCS_SWCTRL(base)			XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   BCS_SWCTRL_DISABLE_256B		REG_BIT(2)</div><div class='add'>+</div><div class='add'>+/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */</div><div class='add'>+#define BLIT_CCTL(base)				XE_REG((base) + 0x204)</div><div class='add'>+#define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)</div><div class='add'>+#define   BLIT_CCTL_SRC_MOCS_MASK		REG_GENMASK(6, 1)</div><div class='add'>+</div><div class='add'>+#define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)</div><div class='add'>+#define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)</div><div class='add'>+</div><div class='add'>+#define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244)</div><div class='add'>+#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)</div><div class='add'>+#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define RING_MODE(base)				XE_REG((base) + 0x29c)</div><div class='add'>+#define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)</div><div class='add'>+</div><div class='add'>+#define RING_TIMESTAMP_UDW(base)		XE_REG((base) + 0x358 + 4)</div><div class='add'>+#define   RING_VALID_MASK			0x00000001</div><div class='add'>+#define   RING_VALID				0x00000001</div><div class='add'>+#define   STOP_RING				REG_BIT(8)</div><div class='add'>+#define   TAIL_ADDR				0x001FFFF8</div><div class='add'>+</div><div class='add'>+#define RING_CTX_TIMESTAMP(base)		XE_REG((base) + 0x3a8)</div><div class='add'>+</div><div class='add'>+#define RING_FORCE_TO_NONPRIV(base, i)		XE_REG(((base) + 0x4d0) + (i) * 4)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_DENY		REG_BIT(30)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	REG_GENMASK(29, 28)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ACCESS_RW	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ACCESS_RD	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 1)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ACCESS_WR	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 2)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 3)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK	REG_GENMASK(25, 2)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_RANGE_MASK	REG_GENMASK(1, 0)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_RANGE_1		REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 0)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_RANGE_4		REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 1)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_RANGE_16	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 2)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_RANGE_64	REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 3)</div><div class='add'>+#define   RING_FORCE_TO_NONPRIV_MASK_VALID	(RING_FORCE_TO_NONPRIV_RANGE_MASK | \</div><div class='add'>+						 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \</div><div class='add'>+						 RING_FORCE_TO_NONPRIV_DENY)</div><div class='add'>+#define   RING_MAX_NONPRIV_SLOTS  12</div><div class='add'>+</div><div class='add'>+#define RING_EXECLIST_SQ_CONTENTS_LO(base)	XE_REG((base) + 0x510)</div><div class='add'>+#define RING_EXECLIST_SQ_CONTENTS_HI(base)	XE_REG((base) + 0x510 + 4)</div><div class='add'>+</div><div class='add'>+#define RING_EXECLIST_CONTROL(base)		XE_REG((base) + 0x550)</div><div class='add'>+#define	  EL_CTRL_LOAD				REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define CS_CHICKEN1(base)			XE_REG((base) + 0x580, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   PREEMPT_GPGPU_LEVEL(hi, lo)		(((hi) &lt;&lt; 2) | ((lo) &lt;&lt; 1))</div><div class='add'>+#define   PREEMPT_GPGPU_MID_THREAD_LEVEL	PREEMPT_GPGPU_LEVEL(0, 0)</div><div class='add'>+#define   PREEMPT_GPGPU_THREAD_GROUP_LEVEL	PREEMPT_GPGPU_LEVEL(0, 1)</div><div class='add'>+#define   PREEMPT_GPGPU_COMMAND_LEVEL		PREEMPT_GPGPU_LEVEL(1, 0)</div><div class='add'>+#define   PREEMPT_GPGPU_LEVEL_MASK		PREEMPT_GPGPU_LEVEL(1, 1)</div><div class='add'>+#define   PREEMPT_3D_OBJECT_LEVEL		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define VDBOX_CGCTL3F08(base)			XE_REG((base) + 0x3f08)</div><div class='add'>+#define   CG3DDISHRS_CLKGATE_DIS		REG_BIT(5)</div><div class='add'>+</div><div class='add'>+#define VDBOX_CGCTL3F10(base)			XE_REG((base) + 0x3f10)</div><div class='add'>+#define   IECPUNIT_CLKGATE_DIS			REG_BIT(22)</div><div class='add'>+</div><div class='add'>+#define VDBOX_CGCTL3F18(base)			XE_REG((base) + 0x3f18)</div><div class='add'>+#define   ALNUNIT_CLKGATE_DIS			REG_BIT(13)</div><div class='add'>+</div><div class='add'>+#define VDBOX_CGCTL3F1C(base)			XE_REG((base) + 0x3f1c)</div><div class='add'>+#define   MFXPIPE_CLKGATE_DIS			REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h<br/>new file mode 100644<br/>index 000000000000..a255946b6f77<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_gpu_commands.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gpu_commands.h</a></div><div class='hunk'>@@ -0,0 +1,70 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GPU_COMMANDS_H_</div><div class='add'>+#define _XE_GPU_COMMANDS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+#define XY_CTRL_SURF_COPY_BLT		((2 &lt;&lt; 29) | (0x48 &lt;&lt; 22) | 3)</div><div class='add'>+#define   SRC_ACCESS_TYPE_SHIFT		21</div><div class='add'>+#define   DST_ACCESS_TYPE_SHIFT		20</div><div class='add'>+#define   CCS_SIZE_MASK			GENMASK(17, 8)</div><div class='add'>+#define   XE2_CCS_SIZE_MASK		GENMASK(18, 9)</div><div class='add'>+#define   XY_CTRL_SURF_MOCS_MASK	GENMASK(31, 26)</div><div class='add'>+#define   XE2_XY_CTRL_SURF_MOCS_INDEX_MASK	GENMASK(31, 28)</div><div class='add'>+#define   NUM_CCS_BYTES_PER_BLOCK	256</div><div class='add'>+#define   NUM_BYTES_PER_CCS_BYTE(_xe)	(GRAPHICS_VER(_xe) &gt;= 20 ? 512 : 256)</div><div class='add'>+</div><div class='add'>+#define XY_FAST_COLOR_BLT_CMD		(2 &lt;&lt; 29 | 0x44 &lt;&lt; 22)</div><div class='add'>+#define   XY_FAST_COLOR_BLT_DEPTH_32	(2 &lt;&lt; 19)</div><div class='add'>+#define   XY_FAST_COLOR_BLT_DW		16</div><div class='add'>+#define   XY_FAST_COLOR_BLT_MOCS_MASK	GENMASK(27, 22)</div><div class='add'>+#define   XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK	GENMASK(27, 24)</div><div class='add'>+#define   XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31</div><div class='add'>+</div><div class='add'>+#define XY_FAST_COPY_BLT_CMD		(2 &lt;&lt; 29 | 0x42 &lt;&lt; 22)</div><div class='add'>+#define   XY_FAST_COPY_BLT_DEPTH_32	(3&lt;&lt;24)</div><div class='add'>+#define   XY_FAST_COPY_BLT_D1_SRC_TILE4	REG_BIT(31)</div><div class='add'>+#define   XY_FAST_COPY_BLT_D1_DST_TILE4	REG_BIT(30)</div><div class='add'>+#define   XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK	GENMASK(23, 20)</div><div class='add'>+</div><div class='add'>+#define	PVC_MEM_SET_CMD		(2 &lt;&lt; 29 | 0x5b &lt;&lt; 22)</div><div class='add'>+#define   PVC_MEM_SET_CMD_LEN_DW	7</div><div class='add'>+#define   PVC_MEM_SET_MATRIX		REG_BIT(17)</div><div class='add'>+#define   PVC_MEM_SET_DATA_FIELD	GENMASK(31, 24)</div><div class='add'>+/* Bspec lists field as [6:0], but index alone is from [6:1] */</div><div class='add'>+#define   PVC_MEM_SET_MOCS_INDEX_MASK	GENMASK(6, 1)</div><div class='add'>+#define   XE2_MEM_SET_MOCS_INDEX_MASK	GENMASK(6, 3)</div><div class='add'>+</div><div class='add'>+#define GFX_OP_PIPE_CONTROL(len)	((0x3&lt;&lt;29)|(0x3&lt;&lt;27)|(0x2&lt;&lt;24)|((len)-2))</div><div class='add'>+</div><div class='add'>+#define	  PIPE_CONTROL0_HDC_PIPELINE_FLUSH		BIT(9)	/* gen12 */</div><div class='add'>+</div><div class='add'>+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1&lt;&lt;29)</div><div class='add'>+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1&lt;&lt;28)</div><div class='add'>+#define   PIPE_CONTROL_AMFS_FLUSH			(1&lt;&lt;25)</div><div class='add'>+#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1&lt;&lt;24)</div><div class='add'>+#define   PIPE_CONTROL_LRI_POST_SYNC			BIT(23)</div><div class='add'>+#define   PIPE_CONTROL_STORE_DATA_INDEX			(1&lt;&lt;21)</div><div class='add'>+#define   PIPE_CONTROL_CS_STALL				(1&lt;&lt;20)</div><div class='add'>+#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1&lt;&lt;19)</div><div class='add'>+#define	  PIPE_CONTROL_TLB_INVALIDATE			BIT(18)</div><div class='add'>+#define   PIPE_CONTROL_PSD_SYNC				(1&lt;&lt;17)</div><div class='add'>+#define   PIPE_CONTROL_QW_WRITE				(1&lt;&lt;14)</div><div class='add'>+#define   PIPE_CONTROL_DEPTH_STALL			(1&lt;&lt;13)</div><div class='add'>+#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1&lt;&lt;12)</div><div class='add'>+#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1&lt;&lt;11)</div><div class='add'>+#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1&lt;&lt;10)</div><div class='add'>+#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1&lt;&lt;9)</div><div class='add'>+#define   PIPE_CONTROL_FLUSH_ENABLE			(1&lt;&lt;7)</div><div class='add'>+#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1&lt;&lt;5)</div><div class='add'>+#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1&lt;&lt;4)</div><div class='add'>+#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1&lt;&lt;3)</div><div class='add'>+#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1&lt;&lt;2)</div><div class='add'>+#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1&lt;&lt;1)</div><div class='add'>+#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1&lt;&lt;0)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h<br/>new file mode 100644<br/>index 000000000000..9886ec9cb08e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_gsc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gsc_regs.h</a></div><div class='hunk'>@@ -0,0 +1,41 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GSC_REGS_H_</div><div class='add'>+#define _XE_GSC_REGS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/compiler.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/* Definitions of GSC H/W registers, bits, etc */</div><div class='add'>+</div><div class='add'>+#define MTL_GSC_HECI1_BASE	0x00116000</div><div class='add'>+#define MTL_GSC_HECI2_BASE	0x00117000</div><div class='add'>+</div><div class='add'>+#define HECI_H_CSR(base)	XE_REG((base) + 0x4)</div><div class='add'>+#define   HECI_H_CSR_IE		REG_BIT(0)</div><div class='add'>+#define   HECI_H_CSR_IS		REG_BIT(1)</div><div class='add'>+#define   HECI_H_CSR_IG		REG_BIT(2)</div><div class='add'>+#define   HECI_H_CSR_RDY	REG_BIT(3)</div><div class='add'>+#define   HECI_H_CSR_RST	REG_BIT(4)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The FWSTS register values are FW defined and can be different between</div><div class='add'>+ * HECI1 and HECI2</div><div class='add'>+ */</div><div class='add'>+#define HECI_FWSTS1(base)				XE_REG((base) + 0xc40)</div><div class='add'>+#define   HECI1_FWSTS1_CURRENT_STATE			REG_GENMASK(3, 0)</div><div class='add'>+#define   HECI1_FWSTS1_CURRENT_STATE_RESET		0</div><div class='add'>+#define   HECI1_FWSTS1_PROXY_STATE_NORMAL		5</div><div class='add'>+#define   HECI1_FWSTS1_INIT_COMPLETE			REG_BIT(9)</div><div class='add'>+#define HECI_FWSTS5(base)				XE_REG((base) + 0xc68)</div><div class='add'>+#define   HECI1_FWSTS5_HUC_AUTH_DONE			REG_BIT(19)</div><div class='add'>+</div><div class='add'>+#define HECI_H_GS1(base)	XE_REG((base) + 0xc4c)</div><div class='add'>+#define   HECI_H_GS1_ER_PREP	REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h<br/>new file mode 100644<br/>index 000000000000..1dd361046b5d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_gt_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_gt_regs.h</a></div><div class='hunk'>@@ -0,0 +1,478 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_REGS_H_</div><div class='add'>+#define _XE_GT_REGS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The GSI register range [0x0 - 0x40000) is replicated at a higher offset</div><div class='add'>+ * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically</div><div class='add'>+ * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.</div><div class='add'>+ */</div><div class='add'>+#define MEDIA_GT_GSI_OFFSET				0x380000</div><div class='add'>+#define MEDIA_GT_GSI_LENGTH				0x40000</div><div class='add'>+</div><div class='add'>+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */</div><div class='add'>+#define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)</div><div class='add'>+#define   MTL_CAGF_MASK					REG_GENMASK(8, 0)</div><div class='add'>+#define   MTL_CC_MASK					REG_GENMASK(12, 9)</div><div class='add'>+</div><div class='add'>+/* RPM unit config (Gen8+) */</div><div class='add'>+#define RPM_CONFIG0					XE_REG(0xd00)</div><div class='add'>+#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)</div><div class='add'>+#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0</div><div class='add'>+#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1</div><div class='add'>+#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2</div><div class='add'>+#define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3</div><div class='add'>+#define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)</div><div class='add'>+#define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)</div><div class='add'>+#define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)</div><div class='add'>+</div><div class='add'>+#define GMD_ID					XE_REG(0xd8c)</div><div class='add'>+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)</div><div class='add'>+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)</div><div class='add'>+#define   GMD_ID_REVID				REG_GENMASK(5, 0)</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)</div><div class='add'>+#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)</div><div class='add'>+</div><div class='add'>+#define MCFG_MCR_SELECTOR			XE_REG(0xfd0)</div><div class='add'>+#define MTL_MCR_SELECTOR			XE_REG(0xfd4)</div><div class='add'>+#define SF_MCR_SELECTOR				XE_REG(0xfd8)</div><div class='add'>+#define MCR_SELECTOR				XE_REG(0xfdc)</div><div class='add'>+#define GAM_MCR_SELECTOR			XE_REG(0xfe0)</div><div class='add'>+#define   MCR_MULTICAST				REG_BIT(31)</div><div class='add'>+#define   MCR_SLICE_MASK			REG_GENMASK(30, 27)</div><div class='add'>+#define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)</div><div class='add'>+#define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)</div><div class='add'>+#define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)</div><div class='add'>+#define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)</div><div class='add'>+#define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)</div><div class='add'>+</div><div class='add'>+#define PS_INVOCATION_COUNT			XE_REG(0x2348)</div><div class='add'>+</div><div class='add'>+#define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)</div><div class='add'>+#define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)</div><div class='add'>+#define CCS_AUX_INV				XE_REG(0x4208)</div><div class='add'>+</div><div class='add'>+#define VD0_AUX_INV				XE_REG(0x4218)</div><div class='add'>+#define VE0_AUX_INV				XE_REG(0x4238)</div><div class='add'>+</div><div class='add'>+#define VE1_AUX_INV				XE_REG(0x42b8)</div><div class='add'>+#define   AUX_INV				REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)</div><div class='add'>+#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)</div><div class='add'>+</div><div class='add'>+#define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)</div><div class='add'>+</div><div class='add'>+#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   TBIMR_FAST_CLIP			REG_BIT(5)</div><div class='add'>+</div><div class='add'>+#define FF_MODE					XE_REG_MCR(0x6210)</div><div class='add'>+#define   DIS_TE_AUTOSTRIP			REG_BIT(31)</div><div class='add'>+#define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)</div><div class='add'>+#define   DIS_MESH_AUTOSTRIP			REG_BIT(15)</div><div class='add'>+</div><div class='add'>+#define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)</div><div class='add'>+#define   DIS_AUTOSTRIP				REG_BIT(6)</div><div class='add'>+#define   DIS_OVER_FETCH_CACHE			REG_BIT(1)</div><div class='add'>+#define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define FF_MODE2				XE_REG(0x6604)</div><div class='add'>+#define XEHP_FF_MODE2				XE_REG_MCR(0x6604)</div><div class='add'>+#define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)</div><div class='add'>+#define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)</div><div class='add'>+#define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)</div><div class='add'>+#define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)</div><div class='add'>+</div><div class='add'>+#define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)</div><div class='add'>+</div><div class='add'>+#define COMMON_SLICE_CHICKEN1			XE_REG(0x7010)</div><div class='add'>+</div><div class='add'>+#define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)</div><div class='add'>+#define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)</div><div class='add'>+</div><div class='add'>+#define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)</div><div class='add'>+</div><div class='add'>+#define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   FLSH_IGNORES_PSD			REG_BIT(10)</div><div class='add'>+#define   FD_END_COLLECT			REG_BIT(5)</div><div class='add'>+</div><div class='add'>+#define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)</div><div class='add'>+</div><div class='add'>+#define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)</div><div class='add'>+#define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)</div><div class='add'>+#define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)</div><div class='add'>+#define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)</div><div class='add'>+#define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)</div><div class='add'>+</div><div class='add'>+#define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)</div><div class='add'>+</div><div class='add'>+#define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)</div><div class='add'>+</div><div class='add'>+#define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)</div><div class='add'>+</div><div class='add'>+#define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)</div><div class='add'>+</div><div class='add'>+#define SQCNT1					XE_REG_MCR(0x8718)</div><div class='add'>+#define XELPMP_SQCNT1				XE_REG(0x8718)</div><div class='add'>+#define   ENFORCE_RAR				REG_BIT(23)</div><div class='add'>+</div><div class='add'>+#define XEHP_SQCM				XE_REG_MCR(0x8724)</div><div class='add'>+#define   EN_32B_ACCESS				REG_BIT(30)</div><div class='add'>+</div><div class='add'>+#define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)</div><div class='add'>+#define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GSCPSMI_BASE				XE_REG(0x880c)</div><div class='add'>+</div><div class='add'>+/* Fuse readout registers for GT */</div><div class='add'>+#define XEHP_FUSE4				XE_REG(0x9114)</div><div class='add'>+#define   CCS_EN_MASK				REG_GENMASK(19, 16)</div><div class='add'>+#define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)</div><div class='add'>+</div><div class='add'>+#define	MIRROR_FUSE3				XE_REG(0x9118)</div><div class='add'>+#define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)</div><div class='add'>+#define   L3BANK_PAIR_COUNT			4</div><div class='add'>+#define   L3BANK_MASK				REG_GENMASK(3, 0)</div><div class='add'>+/* on Xe_HP the same fuses indicates mslices instead of L3 banks */</div><div class='add'>+#define   MAX_MSLICES				4</div><div class='add'>+#define   MEML3_EN_MASK				REG_GENMASK(3, 0)</div><div class='add'>+</div><div class='add'>+#define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */</div><div class='add'>+#define   XELP_EU_MASK				REG_GENMASK(7, 0)</div><div class='add'>+#define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)</div><div class='add'>+</div><div class='add'>+#define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)</div><div class='add'>+#define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)</div><div class='add'>+#define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)</div><div class='add'>+</div><div class='add'>+#define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)</div><div class='add'>+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)</div><div class='add'>+#define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)</div><div class='add'>+#define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)</div><div class='add'>+#define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)</div><div class='add'>+</div><div class='add'>+#define GDRST					XE_REG(0x941c)</div><div class='add'>+#define   GRDOM_GUC				REG_BIT(3)</div><div class='add'>+#define   GRDOM_FULL				REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define MISCCPCTL				XE_REG(0x9424)</div><div class='add'>+#define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)</div><div class='add'>+</div><div class='add'>+#define UNSLCGCTL9430				XE_REG(0x9430)</div><div class='add'>+#define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)</div><div class='add'>+#define   VFUNIT_CLKGATE_DIS			REG_BIT(20)</div><div class='add'>+#define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */</div><div class='add'>+#define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */</div><div class='add'>+#define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)</div><div class='add'>+#define   HSUNIT_CLKGATE_DIS			REG_BIT(8)</div><div class='add'>+#define   VSUNIT_CLKGATE_DIS			REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define UNSLCGCTL9440				XE_REG(0x9440)</div><div class='add'>+#define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)</div><div class='add'>+#define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)</div><div class='add'>+#define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)</div><div class='add'>+#define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)</div><div class='add'>+#define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)</div><div class='add'>+#define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)</div><div class='add'>+#define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)</div><div class='add'>+#define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)</div><div class='add'>+#define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)</div><div class='add'>+#define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)</div><div class='add'>+#define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)</div><div class='add'>+#define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)</div><div class='add'>+</div><div class='add'>+#define UNSLCGCTL9444				XE_REG(0x9444)</div><div class='add'>+#define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)</div><div class='add'>+#define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)</div><div class='add'>+#define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)</div><div class='add'>+#define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)</div><div class='add'>+#define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)</div><div class='add'>+#define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)</div><div class='add'>+#define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)</div><div class='add'>+#define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)</div><div class='add'>+#define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)</div><div class='add'>+#define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)</div><div class='add'>+#define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)</div><div class='add'>+#define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)</div><div class='add'>+#define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)</div><div class='add'>+#define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)</div><div class='add'>+#define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)</div><div class='add'>+#define   LTCDD_CLKGATE_DIS			REG_BIT(10)</div><div class='add'>+</div><div class='add'>+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)</div><div class='add'>+#define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)</div><div class='add'>+#define   L3_CLKGATE_DIS			REG_BIT(16)</div><div class='add'>+#define   NODEDSS_CLKGATE_DIS			REG_BIT(12)</div><div class='add'>+#define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)</div><div class='add'>+#define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)</div><div class='add'>+#define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)</div><div class='add'>+#define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)</div><div class='add'>+</div><div class='add'>+#define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)</div><div class='add'>+#define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)</div><div class='add'>+</div><div class='add'>+#define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)</div><div class='add'>+#define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)</div><div class='add'>+#define   GWUNIT_CLKGATE_DIS			REG_BIT(16)</div><div class='add'>+</div><div class='add'>+#define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)</div><div class='add'>+#define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)</div><div class='add'>+</div><div class='add'>+#define SSMCGCTL9530				XE_REG_MCR(0x9530)</div><div class='add'>+#define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)</div><div class='add'>+</div><div class='add'>+#define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)</div><div class='add'>+#define   DFR_DISABLE				REG_BIT(9)</div><div class='add'>+</div><div class='add'>+#define RPNSWREQ				XE_REG(0xa008)</div><div class='add'>+#define   REQ_RATIO_MASK			REG_GENMASK(31, 23)</div><div class='add'>+</div><div class='add'>+#define RP_CONTROL				XE_REG(0xa024)</div><div class='add'>+#define   RPSWCTL_MASK				REG_GENMASK(10, 9)</div><div class='add'>+#define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)</div><div class='add'>+#define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)</div><div class='add'>+#define RC_CONTROL				XE_REG(0xa090)</div><div class='add'>+#define   RC_CTL_HW_ENABLE			REG_BIT(31)</div><div class='add'>+#define   RC_CTL_TO_MODE			REG_BIT(28)</div><div class='add'>+#define   RC_CTL_RC6_ENABLE			REG_BIT(18)</div><div class='add'>+#define RC_STATE				XE_REG(0xa094)</div><div class='add'>+#define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)</div><div class='add'>+</div><div class='add'>+#define PMINTRMSK				XE_REG(0xa168)</div><div class='add'>+#define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)</div><div class='add'>+#define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_GT				XE_REG(0xa188)</div><div class='add'>+</div><div class='add'>+#define PG_ENABLE				XE_REG(0xa210)</div><div class='add'>+</div><div class='add'>+#define CTC_MODE				XE_REG(0xa26c)</div><div class='add'>+#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)</div><div class='add'>+#define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_RENDER			XE_REG(0xa278)</div><div class='add'>+#define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)</div><div class='add'>+#define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)</div><div class='add'>+#define FORCEWAKE_GSC				XE_REG(0xa618)</div><div class='add'>+</div><div class='add'>+#define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   XEHPC_OVRLSCCC			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+/* L3 Cache Control */</div><div class='add'>+#define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)</div><div class='add'>+#define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)</div><div class='add'>+#define LNCFCMOCS_REG_COUNT			32</div><div class='add'>+</div><div class='add'>+#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)</div><div class='add'>+#define   XEHP_LNESPARE				REG_BIT(19)</div><div class='add'>+</div><div class='add'>+#define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)</div><div class='add'>+#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)</div><div class='add'>+</div><div class='add'>+#define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)</div><div class='add'>+#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)</div><div class='add'>+</div><div class='add'>+#define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)</div><div class='add'>+</div><div class='add'>+#define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)</div><div class='add'>+#define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)</div><div class='add'>+#define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)</div><div class='add'>+#define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)</div><div class='add'>+#define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)</div><div class='add'>+#define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)</div><div class='add'>+#define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)</div><div class='add'>+#define   FORCE_MISS_FTLB			REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)</div><div class='add'>+#define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)</div><div class='add'>+#define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)</div><div class='add'>+#define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)</div><div class='add'>+</div><div class='add'>+#define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)</div><div class='add'>+#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)</div><div class='add'>+#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)</div><div class='add'>+</div><div class='add'>+#define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   ENABLE_SMALLPL			REG_BIT(15)</div><div class='add'>+#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)</div><div class='add'>+#define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)</div><div class='add'>+#define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)</div><div class='add'>+</div><div class='add'>+#define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DISABLE_ECC				REG_BIT(5)</div><div class='add'>+#define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DISABLE_GRF_CLEAR			REG_BIT(13)</div><div class='add'>+#define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)</div><div class='add'>+#define   DISABLE_TDL_PUSH			REG_BIT(9)</div><div class='add'>+#define   DIS_PICK_2ND_EU			REG_BIT(7)</div><div class='add'>+#define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)</div><div class='add'>+#define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)</div><div class='add'>+#define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)</div><div class='add'>+</div><div class='add'>+#define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)</div><div class='add'>+</div><div class='add'>+#define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   UGM_BACKUP_MODE			REG_BIT(13)</div><div class='add'>+#define   MDQ_ARBITRATION_MODE			REG_BIT(12)</div><div class='add'>+#define   EARLY_EOT_DIS				REG_BIT(1)</div><div class='add'>+</div><div class='add'>+#define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   DISABLE_READ_SUPPRESSION		REG_BIT(15)</div><div class='add'>+#define   DISABLE_EARLY_READ			REG_BIT(14)</div><div class='add'>+#define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)</div><div class='add'>+#define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)</div><div class='add'>+#define   DISABLE_DOP_GATING			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define RT_CTRL					XE_REG_MCR(0xe530)</div><div class='add'>+#define   DIS_NULL_QUERY			REG_BIT(10)</div><div class='add'>+</div><div class='add'>+#define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)</div><div class='add'>+#define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)</div><div class='add'>+</div><div class='add'>+#define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)</div><div class='add'>+#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)</div><div class='add'>+#define   TGM_WRITE_EOM_FORCE			REG_BIT(17)</div><div class='add'>+#define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)</div><div class='add'>+#define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)</div><div class='add'>+</div><div class='add'>+#define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)</div><div class='add'>+#define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)</div><div class='add'>+#define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)</div><div class='add'>+#define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)</div><div class='add'>+#define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)</div><div class='add'>+#define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)</div><div class='add'>+#define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)</div><div class='add'>+#define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)</div><div class='add'>+#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)</div><div class='add'>+</div><div class='add'>+#define SARB_CHICKEN1				XE_REG_MCR(0xe90c)</div><div class='add'>+#define   COMP_CKN_IN				REG_GENMASK(30, 29)</div><div class='add'>+</div><div class='add'>+#define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)</div><div class='add'>+#define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)</div><div class='add'>+#define   RCU_MODE_CCS_ENABLE			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Total of 4 cslices, where each cslice is in the form:</div><div class='add'>+ *   [0-3]     CCS ID</div><div class='add'>+ *   [4-6]     RSVD</div><div class='add'>+ *   [7]       Disabled</div><div class='add'>+ */</div><div class='add'>+#define CCS_MODE				XE_REG(0x14804)</div><div class='add'>+#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */</div><div class='add'>+#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */</div><div class='add'>+#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)</div><div class='add'>+#define   CCS_MODE_CSLICE(cslice, ccs) \</div><div class='add'>+	((ccs) &lt;&lt; ((cslice) * CCS_MODE_CSLICE_WIDTH))</div><div class='add'>+</div><div class='add'>+#define FORCEWAKE_ACK_GT			XE_REG(0x130044)</div><div class='add'>+#define   FORCEWAKE_KERNEL			BIT(0)</div><div class='add'>+#define   FORCEWAKE_USER			BIT(1)</div><div class='add'>+#define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)</div><div class='add'>+</div><div class='add'>+#define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)</div><div class='add'>+#define MTL_MEDIA_MC6				XE_REG(0x138048)</div><div class='add'>+</div><div class='add'>+#define GT_CORE_STATUS				XE_REG(0x138060)</div><div class='add'>+#define   RCN_MASK				REG_GENMASK(2, 0)</div><div class='add'>+#define   GT_C0					0</div><div class='add'>+#define   GT_C6					3</div><div class='add'>+</div><div class='add'>+#define GT_GFX_RC6_LOCKED			XE_REG(0x138104)</div><div class='add'>+#define GT_GFX_RC6				XE_REG(0x138108)</div><div class='add'>+</div><div class='add'>+#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)</div><div class='add'>+#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3</div><div class='add'>+#define   PROCHOT_MASK				REG_BIT(0)</div><div class='add'>+#define   THERMAL_LIMIT_MASK			REG_BIT(1)</div><div class='add'>+#define   RATL_MASK				REG_BIT(5)</div><div class='add'>+#define   VR_THERMALERT_MASK			REG_BIT(6)</div><div class='add'>+#define   VR_TDC_MASK				REG_BIT(7)</div><div class='add'>+#define   POWER_LIMIT_4_MASK			REG_BIT(8)</div><div class='add'>+#define   POWER_LIMIT_1_MASK			REG_BIT(10)</div><div class='add'>+#define   POWER_LIMIT_2_MASK			REG_BIT(11)</div><div class='add'>+</div><div class='add'>+#define GT_PERF_STATUS				XE_REG(0x1381b4)</div><div class='add'>+#define   VOLTAGE_MASK				REG_GENMASK(10, 0)</div><div class='add'>+</div><div class='add'>+#define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4))</div><div class='add'>+</div><div class='add'>+#define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030)</div><div class='add'>+#define VCS_VECS_INTR_ENABLE			XE_REG(0x190034)</div><div class='add'>+#define GUC_SG_INTR_ENABLE			XE_REG(0x190038)</div><div class='add'>+#define   ENGINE1_MASK				REG_GENMASK(31, 16)</div><div class='add'>+#define   ENGINE0_MASK				REG_GENMASK(15, 0)</div><div class='add'>+#define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c)</div><div class='add'>+#define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044)</div><div class='add'>+#define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048)</div><div class='add'>+</div><div class='add'>+#define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4))</div><div class='add'>+#define   INTR_DATA_VALID			REG_BIT(31)</div><div class='add'>+#define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)</div><div class='add'>+#define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)</div><div class='add'>+#define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)</div><div class='add'>+#define   OTHER_GUC_INSTANCE			0</div><div class='add'>+#define   OTHER_GSC_INSTANCE			6</div><div class='add'>+</div><div class='add'>+#define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4))</div><div class='add'>+#define RCS0_RSVD_INTR_MASK			XE_REG(0x190090)</div><div class='add'>+#define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0)</div><div class='add'>+#define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8)</div><div class='add'>+#define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac)</div><div class='add'>+#define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0)</div><div class='add'>+#define GUC_SG_INTR_MASK			XE_REG(0x1900e8)</div><div class='add'>+#define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec)</div><div class='add'>+#define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4)</div><div class='add'>+#define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)</div><div class='add'>+#define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)</div><div class='add'>+#define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)</div><div class='add'>+#define XEHPC_BCS3_BCS4_INTR_MASK		XE_REG(0x190114)</div><div class='add'>+#define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)</div><div class='add'>+#define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)</div><div class='add'>+#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)</div><div class='add'>+#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)</div><div class='add'>+#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)</div><div class='add'>+#define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)</div><div class='add'>+#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define PVC_GT0_PACKAGE_ENERGY_STATUS		XE_REG(0x281004)</div><div class='add'>+#define PVC_GT0_PACKAGE_RAPL_LIMIT		XE_REG(0x281008)</div><div class='add'>+#define PVC_GT0_PACKAGE_POWER_SKU_UNIT		XE_REG(0x281068)</div><div class='add'>+#define PVC_GT0_PLATFORM_ENERGY_STATUS		XE_REG(0x28106c)</div><div class='add'>+#define PVC_GT0_PACKAGE_POWER_SKU		XE_REG(0x281080)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h<br/>new file mode 100644<br/>index 000000000000..92320bbc9d3d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_guc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_guc_regs.h</a></div><div class='hunk'>@@ -0,0 +1,143 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_REGS_H_</div><div class='add'>+#define _XE_GUC_REGS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/compiler.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/* Definitions of GuC H/W registers, bits, etc */</div><div class='add'>+</div><div class='add'>+#define DIST_DBS_POPULATED			XE_REG(0xd08)</div><div class='add'>+#define   DOORBELLS_PER_SQIDI_MASK		REG_GENMASK(23, 16)</div><div class='add'>+#define   SQIDIS_DOORBELL_EXIST_MASK		REG_GENMASK(15, 0)</div><div class='add'>+</div><div class='add'>+#define DRBREGL(x)				XE_REG(0x1000 + (x) * 8)</div><div class='add'>+#define   DRB_VALID				REG_BIT(0)</div><div class='add'>+#define DRBREGU(x)				XE_REG(0x1000 + (x) * 8 + 4)</div><div class='add'>+</div><div class='add'>+#define GTCR					XE_REG(0x4274)</div><div class='add'>+#define   GTCR_INVALIDATE			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_ARAT_C6DIS				XE_REG(0xa178)</div><div class='add'>+</div><div class='add'>+#define GUC_STATUS				XE_REG(0xc000)</div><div class='add'>+#define   GS_AUTH_STATUS_MASK			REG_GENMASK(31, 30)</div><div class='add'>+#define   GS_AUTH_STATUS_BAD			REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)</div><div class='add'>+#define   GS_AUTH_STATUS_GOOD			REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)</div><div class='add'>+#define   GS_MIA_MASK				REG_GENMASK(18, 16)</div><div class='add'>+#define   GS_MIA_CORE_STATE			REG_FIELD_PREP(GS_MIA_MASK, 0x1)</div><div class='add'>+#define   GS_MIA_HALT_REQUESTED			REG_FIELD_PREP(GS_MIA_MASK, 0x2)</div><div class='add'>+#define   GS_MIA_ISR_ENTRY			REG_FIELD_PREP(GS_MIA_MASK, 0x4)</div><div class='add'>+#define   GS_UKERNEL_MASK			REG_GENMASK(15, 8)</div><div class='add'>+#define   GS_BOOTROM_MASK			REG_GENMASK(7, 1)</div><div class='add'>+#define   GS_BOOTROM_RSA_FAILED			REG_FIELD_PREP(GS_BOOTROM_MASK, 0x50)</div><div class='add'>+#define   GS_BOOTROM_JUMP_PASSED		REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)</div><div class='add'>+#define   GS_MIA_IN_RESET			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_WOPCM_SIZE				XE_REG(0xc050)</div><div class='add'>+#define   GUC_WOPCM_SIZE_MASK			REG_GENMASK(31, 12)</div><div class='add'>+#define   GUC_WOPCM_SIZE_LOCKED			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_SHIM_CONTROL			XE_REG(0xc064)</div><div class='add'>+#define   GUC_MOCS_INDEX_MASK			REG_GENMASK(27, 24)</div><div class='add'>+#define   GUC_SHIM_WC_ENABLE			REG_BIT(21)</div><div class='add'>+#define   GUC_ENABLE_MIA_CLOCK_GATING		REG_BIT(15)</div><div class='add'>+#define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	REG_BIT(10)</div><div class='add'>+#define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	REG_BIT(9)</div><div class='add'>+#define   GUC_MSGCH_ENABLE			REG_BIT(4)</div><div class='add'>+#define   GUC_ENABLE_MIA_CACHING		REG_BIT(2)</div><div class='add'>+#define   GUC_ENABLE_READ_CACHE_LOGIC		REG_BIT(1)</div><div class='add'>+#define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define SOFT_SCRATCH(n)				XE_REG(0xc180 + (n) * 4)</div><div class='add'>+#define SOFT_SCRATCH_COUNT			16</div><div class='add'>+</div><div class='add'>+#define HUC_KERNEL_LOAD_INFO			XE_REG(0xc1dc)</div><div class='add'>+#define   HUC_LOAD_SUCCESSFUL			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define UOS_RSA_SCRATCH(i)			XE_REG(0xc200 + (i) * 4)</div><div class='add'>+#define UOS_RSA_SCRATCH_COUNT			64</div><div class='add'>+</div><div class='add'>+#define DMA_ADDR_0_LOW				XE_REG(0xc300)</div><div class='add'>+#define DMA_ADDR_0_HIGH				XE_REG(0xc304)</div><div class='add'>+#define DMA_ADDR_1_LOW				XE_REG(0xc308)</div><div class='add'>+#define DMA_ADDR_1_HIGH				XE_REG(0xc30c)</div><div class='add'>+#define   DMA_ADDR_SPACE_MASK			REG_GENMASK(20, 16)</div><div class='add'>+#define   DMA_ADDRESS_SPACE_WOPCM		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)</div><div class='add'>+#define   DMA_ADDRESS_SPACE_GGTT		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 8)</div><div class='add'>+#define DMA_COPY_SIZE				XE_REG(0xc310)</div><div class='add'>+#define DMA_CTRL				XE_REG(0xc314)</div><div class='add'>+#define   HUC_UKERNEL				REG_BIT(9)</div><div class='add'>+#define   UOS_MOVE				REG_BIT(4)</div><div class='add'>+#define   START_DMA				REG_BIT(0)</div><div class='add'>+#define DMA_GUC_WOPCM_OFFSET			XE_REG(0xc340)</div><div class='add'>+#define   GUC_WOPCM_OFFSET_SHIFT		14</div><div class='add'>+#define   GUC_WOPCM_OFFSET_MASK			REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)</div><div class='add'>+#define   HUC_LOADING_AGENT_GUC			REG_BIT(1)</div><div class='add'>+#define   GUC_WOPCM_OFFSET_VALID		REG_BIT(0)</div><div class='add'>+#define GUC_MAX_IDLE_COUNT			XE_REG(0xc3e4)</div><div class='add'>+</div><div class='add'>+#define GUC_SEND_INTERRUPT			XE_REG(0xc4c8)</div><div class='add'>+#define   GUC_SEND_TRIGGER			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_BCS_RCS_IER				XE_REG(0xc550)</div><div class='add'>+#define GUC_VCS2_VCS1_IER			XE_REG(0xc554)</div><div class='add'>+#define GUC_WD_VECS_IER				XE_REG(0xc558)</div><div class='add'>+#define GUC_PM_P24C_IER				XE_REG(0xc55c)</div><div class='add'>+</div><div class='add'>+#define GUC_TLB_INV_CR				XE_REG(0xcee8)</div><div class='add'>+#define   GUC_TLB_INV_CR_INVALIDATE		REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define HUC_STATUS2				XE_REG(0xd3b0)</div><div class='add'>+#define   HUC_FW_VERIFIED			REG_BIT(7)</div><div class='add'>+</div><div class='add'>+#define GT_PM_CONFIG				XE_REG(0x13816c)</div><div class='add'>+#define   GT_DOORBELL_ENABLE			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_HOST_INTERRUPT			XE_REG(0x1901f0)</div><div class='add'>+</div><div class='add'>+#define VF_SW_FLAG(n)				XE_REG(0x190240 + (n) * 4)</div><div class='add'>+#define VF_SW_FLAG_COUNT			4</div><div class='add'>+</div><div class='add'>+#define MED_GUC_HOST_INTERRUPT			XE_REG(0x190304)</div><div class='add'>+</div><div class='add'>+#define MED_VF_SW_FLAG(n)			XE_REG(0x190310 + (n) * 4)</div><div class='add'>+#define MED_VF_SW_FLAG_COUNT			4</div><div class='add'>+</div><div class='add'>+/* GuC Interrupt Vector */</div><div class='add'>+#define GUC_INTR_GUC2HOST			REG_BIT(15)</div><div class='add'>+#define GUC_INTR_EXEC_ERROR			REG_BIT(14)</div><div class='add'>+#define GUC_INTR_DISPLAY_EVENT			REG_BIT(13)</div><div class='add'>+#define GUC_INTR_SEM_SIG			REG_BIT(12)</div><div class='add'>+#define GUC_INTR_IOMMU2GUC			REG_BIT(11)</div><div class='add'>+#define GUC_INTR_DOORBELL_RANG			REG_BIT(10)</div><div class='add'>+#define GUC_INTR_DMA_DONE			REG_BIT(9)</div><div class='add'>+#define GUC_INTR_FATAL_ERROR			REG_BIT(8)</div><div class='add'>+#define GUC_INTR_NOTIF_ERROR			REG_BIT(7)</div><div class='add'>+#define GUC_INTR_SW_INT_6			REG_BIT(6)</div><div class='add'>+#define GUC_INTR_SW_INT_5			REG_BIT(5)</div><div class='add'>+#define GUC_INTR_SW_INT_4			REG_BIT(4)</div><div class='add'>+#define GUC_INTR_SW_INT_3			REG_BIT(3)</div><div class='add'>+#define GUC_INTR_SW_INT_2			REG_BIT(2)</div><div class='add'>+#define GUC_INTR_SW_INT_1			REG_BIT(1)</div><div class='add'>+#define GUC_INTR_SW_INT_0			REG_BIT(0)</div><div class='add'>+</div><div class='add'>+#define GUC_NUM_DOORBELLS			256</div><div class='add'>+</div><div class='add'>+/* format of the HW-monitored doorbell cacheline */</div><div class='add'>+struct guc_doorbell_info {</div><div class='add'>+	u32 db_status;</div><div class='add'>+#define GUC_DOORBELL_DISABLED			0</div><div class='add'>+#define GUC_DOORBELL_ENABLED			1</div><div class='add'>+</div><div class='add'>+	u32 cookie;</div><div class='add'>+	u32 reserved[14];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h<br/>new file mode 100644<br/>index 000000000000..4be81abc86ad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_lrc_layout.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_lrc_layout.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_LRC_LAYOUT_H_</div><div class='add'>+#define _XE_LRC_LAYOUT_H_</div><div class='add'>+</div><div class='add'>+#define CTX_CONTEXT_CONTROL		(0x02 + 1)</div><div class='add'>+#define CTX_RING_HEAD			(0x04 + 1)</div><div class='add'>+#define CTX_RING_TAIL			(0x06 + 1)</div><div class='add'>+#define CTX_RING_START			(0x08 + 1)</div><div class='add'>+#define CTX_RING_CTL			(0x0a + 1)</div><div class='add'>+#define CTX_PDP0_UDW			(0x30 + 1)</div><div class='add'>+#define CTX_PDP0_LDW			(0x32 + 1)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h<br/>new file mode 100644<br/>index 000000000000..519dd1067a19<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_mchbar_regs.h</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MCHBAR_REGS_H_</div><div class='add'>+#define _XE_MCHBAR_REGS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * MCHBAR mirror.</div><div class='add'>+ *</div><div class='add'>+ * This mirrors the MCHBAR MMIO space whose location is determined by</div><div class='add'>+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in</div><div class='add'>+ * every way.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define MCHBAR_MIRROR_BASE_SNB			0x140000</div><div class='add'>+</div><div class='add'>+#define PCU_CR_PACKAGE_POWER_SKU		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)</div><div class='add'>+#define   PKG_TDP				GENMASK_ULL(14, 0)</div><div class='add'>+#define   PKG_MIN_PWR				GENMASK_ULL(30, 16)</div><div class='add'>+#define   PKG_MAX_PWR				GENMASK_ULL(46, 32)</div><div class='add'>+#define   PKG_MAX_WIN				GENMASK_ULL(54, 48)</div><div class='add'>+#define     PKG_MAX_WIN_X			GENMASK_ULL(54, 53)</div><div class='add'>+#define     PKG_MAX_WIN_Y			GENMASK_ULL(52, 48)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define PCU_CR_PACKAGE_POWER_SKU_UNIT		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)</div><div class='add'>+#define   PKG_PWR_UNIT				REG_GENMASK(3, 0)</div><div class='add'>+#define   PKG_ENERGY_UNIT			REG_GENMASK(12, 8)</div><div class='add'>+#define   PKG_TIME_UNIT				REG_GENMASK(19, 16)</div><div class='add'>+</div><div class='add'>+#define PCU_CR_PACKAGE_ENERGY_STATUS		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)</div><div class='add'>+</div><div class='add'>+#define PCU_CR_PACKAGE_RAPL_LIMIT		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)</div><div class='add'>+#define   PKG_PWR_LIM_1				REG_GENMASK(14, 0)</div><div class='add'>+#define   PKG_PWR_LIM_1_EN			REG_BIT(15)</div><div class='add'>+#define   PKG_PWR_LIM_1_TIME			REG_GENMASK(23, 17)</div><div class='add'>+#define   PKG_PWR_LIM_1_TIME_X			REG_GENMASK(23, 22)</div><div class='add'>+#define   PKG_PWR_LIM_1_TIME_Y			REG_GENMASK(21, 17)</div><div class='add'>+</div><div class='add'>+#endif /* _XE_MCHBAR_REGS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_reg_defs.h b/drivers/gpu/drm/xe/regs/xe_reg_defs.h<br/>new file mode 100644<br/>index 000000000000..c50e7650c09a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_reg_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_reg_defs.h</a></div><div class='hunk'>@@ -0,0 +1,120 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_REG_DEFS_H_</div><div class='add'>+#define _XE_REG_DEFS_H_</div><div class='add'>+</div><div class='add'>+#include "compat-i915-headers/i915_reg_defs.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_reg - Register definition</div><div class='add'>+ *</div><div class='add'>+ * Register defintion to be used by the individual register. Although the same</div><div class='add'>+ * definition is used for xe_reg and xe_reg_mcr, they use different internal</div><div class='add'>+ * APIs for accesses.</div><div class='add'>+ */</div><div class='add'>+struct xe_reg {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			/** @addr: address */</div><div class='add'>+			u32 addr:28;</div><div class='add'>+			/**</div><div class='add'>+			 * @masked: register is "masked", with upper 16bits used</div><div class='add'>+			 * to identify the bits that are updated on the lower</div><div class='add'>+			 * bits</div><div class='add'>+			 */</div><div class='add'>+			u32 masked:1;</div><div class='add'>+			/**</div><div class='add'>+			 * @mcr: register is multicast/replicated in the</div><div class='add'>+			 * hardware and needs special handling. Any register</div><div class='add'>+			 * with this set should also use a type of xe_reg_mcr_t.</div><div class='add'>+			 * It's only here so the few places that deal with MCR</div><div class='add'>+			 * registers specially (xe_sr.c) and tests using the raw</div><div class='add'>+			 * value can inspect it.</div><div class='add'>+			 */</div><div class='add'>+			u32 mcr:1;</div><div class='add'>+			/**</div><div class='add'>+			 * @ext: access MMIO extension space for current register.</div><div class='add'>+			 */</div><div class='add'>+			u32 ext:1;</div><div class='add'>+		};</div><div class='add'>+		/** @raw: Raw value with both address and options */</div><div class='add'>+		u32 raw;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_reg_mcr - MCR register definition</div><div class='add'>+ *</div><div class='add'>+ * MCR register is the same as a regular register, but uses another type since</div><div class='add'>+ * the internal API used for accessing them is different: it's never correct to</div><div class='add'>+ * use regular MMIO access.</div><div class='add'>+ */</div><div class='add'>+struct xe_reg_mcr {</div><div class='add'>+	/** @__reg: The register */</div><div class='add'>+	struct xe_reg __reg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the</div><div class='add'>+ * written bits on the lower 16 bits.</div><div class='add'>+ *</div><div class='add'>+ * It only applies to registers explicitly marked in bspec with</div><div class='add'>+ * "Access: Masked". Registers with this option can have write operations to</div><div class='add'>+ * specific lower bits by setting the corresponding upper bits. Other bits will</div><div class='add'>+ * not be affected. This allows register writes without needing a RMW cycle and</div><div class='add'>+ * without caching in software the register value.</div><div class='add'>+ *</div><div class='add'>+ * Example: a write with value 0x00010001 will set bit 0 and all other bits</div><div class='add'>+ * retain their previous values.</div><div class='add'>+ *</div><div class='add'>+ * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()</div><div class='add'>+ */</div><div class='add'>+#define XE_REG_OPTION_MASKED		.masked = 1</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_REG_INITIALIZER - Initializer for xe_reg_t.</div><div class='add'>+ * @r_: Register offset</div><div class='add'>+ * @...: Additional options like access mode. See struct xe_reg for available</div><div class='add'>+ *       options.</div><div class='add'>+ *</div><div class='add'>+ * Register field is mandatory, and additional options may be passed as</div><div class='add'>+ * arguments. Usually ``XE_REG()`` should be preferred since it creates an</div><div class='add'>+ * object of the right type. However when initializing static const storage,</div><div class='add'>+ * where a compound statement is not allowed, this can be used instead.</div><div class='add'>+ */</div><div class='add'>+#define XE_REG_INITIALIZER(r_, ...)    { .addr = r_, __VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_REG - Create a struct xe_reg from offset and additional flags</div><div class='add'>+ * @r_: Register offset</div><div class='add'>+ * @...: Additional options like access mode. See struct xe_reg for available</div><div class='add'>+ *       options.</div><div class='add'>+ */</div><div class='add'>+#define XE_REG(r_, ...)		((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_REG_EXT - Create a struct xe_reg from extension offset and additional</div><div class='add'>+ * flags</div><div class='add'>+ * @r_: Register extension offset</div><div class='add'>+ * @...: Additional options like access mode. See struct xe_reg for available</div><div class='add'>+ *       options.</div><div class='add'>+ */</div><div class='add'>+#define XE_REG_EXT(r_, ...)	\</div><div class='add'>+	((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags</div><div class='add'>+ * @r_: Register offset</div><div class='add'>+ * @...: Additional options like access mode. See struct xe_reg for available</div><div class='add'>+ *       options.</div><div class='add'>+ */</div><div class='add'>+#define XE_REG_MCR(r_, ...)	((const struct xe_reg_mcr){					\</div><div class='add'>+				 .__reg = XE_REG_INITIALIZER(r_,  ##__VA_ARGS__, .mcr = 1)	\</div><div class='add'>+				 })</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h<br/>new file mode 100644<br/>index 000000000000..2c214bb9b671<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_regs.h</a></div><div class='hunk'>@@ -0,0 +1,68 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_REGS_H_</div><div class='add'>+#define _XE_REGS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+#define TIMESTAMP_OVERRIDE					XE_REG(0x44074)</div><div class='add'>+#define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	REG_GENMASK(15, 12)</div><div class='add'>+#define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK		REG_GENMASK(9, 0)</div><div class='add'>+</div><div class='add'>+#define PCU_IRQ_OFFSET				0x444e0</div><div class='add'>+#define GU_MISC_IRQ_OFFSET			0x444f0</div><div class='add'>+#define   GU_MISC_GSE				REG_BIT(27)</div><div class='add'>+</div><div class='add'>+#define SOFTWARE_FLAGS_SPR33			XE_REG(0x4f084)</div><div class='add'>+</div><div class='add'>+#define GU_CNTL_PROTECTED			XE_REG(0x10100C)</div><div class='add'>+#define   DRIVERINT_FLR_DIS			REG_BIT(31)</div><div class='add'>+</div><div class='add'>+#define GU_CNTL					XE_REG(0x101010)</div><div class='add'>+#define   LMEM_INIT				REG_BIT(7)</div><div class='add'>+#define   DRIVERFLR				REG_BIT(31)</div><div class='add'>+</div><div class='add'>+#define GU_DEBUG				XE_REG(0x101018)</div><div class='add'>+#define   DRIVERFLR_STATUS			REG_BIT(31)</div><div class='add'>+</div><div class='add'>+#define XEHP_CLOCK_GATE_DIS			XE_REG(0x101014)</div><div class='add'>+#define   SGSI_SIDECLK_DIS			REG_BIT(17)</div><div class='add'>+</div><div class='add'>+#define GGC					XE_REG(0x108040)</div><div class='add'>+#define   GMS_MASK				REG_GENMASK(15, 8)</div><div class='add'>+#define   GGMS_MASK				REG_GENMASK(7, 6)</div><div class='add'>+</div><div class='add'>+#define DSMBASE					XE_REG(0x1080C0)</div><div class='add'>+#define   BDSM_MASK				REG_GENMASK64(63, 20)</div><div class='add'>+</div><div class='add'>+#define GSMBASE					XE_REG(0x108100)</div><div class='add'>+</div><div class='add'>+#define STOLEN_RESERVED				XE_REG(0x1082c0)</div><div class='add'>+#define   WOPCM_SIZE_MASK			REG_GENMASK64(9, 7)</div><div class='add'>+</div><div class='add'>+#define MTL_RP_STATE_CAP			XE_REG(0x138000)</div><div class='add'>+</div><div class='add'>+#define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)</div><div class='add'>+</div><div class='add'>+#define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)</div><div class='add'>+#define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)</div><div class='add'>+#define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)</div><div class='add'>+</div><div class='add'>+#define MTL_MPE_FREQUENCY			XE_REG(0x13802c)</div><div class='add'>+#define   MTL_RPE_MASK				REG_GENMASK(8, 0)</div><div class='add'>+</div><div class='add'>+#define DG1_MSTR_TILE_INTR			XE_REG(0x190008)</div><div class='add'>+#define   DG1_MSTR_IRQ				REG_BIT(31)</div><div class='add'>+#define   DG1_MSTR_TILE(t)			REG_BIT(t)</div><div class='add'>+</div><div class='add'>+#define GFX_MSTR_IRQ				XE_REG(0x190010)</div><div class='add'>+#define   MASTER_IRQ				REG_BIT(31)</div><div class='add'>+#define   GU_MISC_IRQ				REG_BIT(29)</div><div class='add'>+#define   DISPLAY_IRQ				REG_BIT(16)</div><div class='add'>+#define   GT_DW_IRQ(x)				REG_BIT(x)</div><div class='add'>+</div><div class='add'>+#define PVC_RP_STATE_CAP			XE_REG(0x281014)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/regs/xe_sriov_regs.h b/drivers/gpu/drm/xe/regs/xe_sriov_regs.h<br/>new file mode 100644<br/>index 000000000000..58a4e0fad1e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/regs/xe_sriov_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/regs/xe_sriov_regs.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _REGS_XE_SRIOV_REGS_H_</div><div class='add'>+#define _REGS_XE_SRIOV_REGS_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+#define XE2_LMEM_CFG			XE_REG(0x48b0)</div><div class='add'>+</div><div class='add'>+#define LMEM_CFG			XE_REG(0xcf58)</div><div class='add'>+#define   LMEM_EN			REG_BIT(31)</div><div class='add'>+#define   LMTT_DIR_PTR			REG_GENMASK(30, 0) /* in multiples of 64KB */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/Makefile b/drivers/gpu/drm/xe/tests/Makefile<br/>new file mode 100644<br/>index 000000000000..39d8a0892274<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/Makefile</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_DRM_XE_KUNIT_TEST) += \</div><div class='add'>+	xe_bo_test.o \</div><div class='add'>+	xe_dma_buf_test.o \</div><div class='add'>+	xe_migrate_test.o \</div><div class='add'>+	xe_mocs_test.o \</div><div class='add'>+	xe_pci_test.o \</div><div class='add'>+	xe_rtp_test.o \</div><div class='add'>+	xe_wa_test.o</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_bo.c b/drivers/gpu/drm/xe/tests/xe_bo.c<br/>new file mode 100644<br/>index 000000000000..3436fd9cf2b2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo.c</a></div><div class='hunk'>@@ -0,0 +1,352 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 AND MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_bo_test.h"</div><div class='add'>+#include "tests/xe_pci_test.h"</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+</div><div class='add'>+#include "xe_bo_evict.h"</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+</div><div class='add'>+static int ccs_test_migrate(struct xe_tile *tile, struct xe_bo *bo,</div><div class='add'>+			    bool clear, u64 get_val, u64 assign_val,</div><div class='add'>+			    struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct ttm_tt *ttm;</div><div class='add'>+	struct page *page;</div><div class='add'>+	pgoff_t ccs_page;</div><div class='add'>+	long timeout;</div><div class='add'>+	u64 *cpu_map;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	/* Move bo to VRAM if not already there. */</div><div class='add'>+	ret = xe_bo_validate(bo, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to validate bo.\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Optionally clear bo *and* CCS data in VRAM. */</div><div class='add'>+	if (clear) {</div><div class='add'>+		fence = xe_migrate_clear(tile-&gt;migrate, bo, bo-&gt;ttm.resource);</div><div class='add'>+		if (IS_ERR(fence)) {</div><div class='add'>+			KUNIT_FAIL(test, "Failed to submit bo clear.\n");</div><div class='add'>+			return PTR_ERR(fence);</div><div class='add'>+		}</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Evict to system. CCS data should be copied. */</div><div class='add'>+	ret = xe_bo_evict(bo, true);</div><div class='add'>+	if (ret) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to evict bo.\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Sync all migration blits */</div><div class='add'>+	timeout = dma_resv_wait_timeout(bo-&gt;ttm.base.resv,</div><div class='add'>+					DMA_RESV_USAGE_KERNEL,</div><div class='add'>+					true,</div><div class='add'>+					5 * HZ);</div><div class='add'>+	if (timeout &lt;= 0) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to sync bo eviction.\n");</div><div class='add'>+		return -ETIME;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Bo with CCS data is now in system memory. Verify backing store</div><div class='add'>+	 * and data integrity. Then assign for the next testing round while</div><div class='add'>+	 * we still have a CPU map.</div><div class='add'>+	 */</div><div class='add'>+	ttm = bo-&gt;ttm.ttm;</div><div class='add'>+	if (!ttm || !ttm_tt_is_populated(ttm)) {</div><div class='add'>+		KUNIT_FAIL(test, "Bo was not in expected placement.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ccs_page = xe_bo_ccs_pages_start(bo) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	if (ccs_page &gt;= ttm-&gt;num_pages) {</div><div class='add'>+		KUNIT_FAIL(test, "No TTM CCS pages present.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	page = ttm-&gt;pages[ccs_page];</div><div class='add'>+	cpu_map = kmap_local_page(page);</div><div class='add'>+</div><div class='add'>+	/* Check first CCS value */</div><div class='add'>+	if (cpu_map[0] != get_val) {</div><div class='add'>+		KUNIT_FAIL(test,</div><div class='add'>+			   "Expected CCS readout 0x%016llx, got 0x%016llx.\n",</div><div class='add'>+			   (unsigned long long)get_val,</div><div class='add'>+			   (unsigned long long)cpu_map[0]);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check last CCS value, or at least last value in page. */</div><div class='add'>+	offset = xe_device_ccs_bytes(tile_to_xe(tile), bo-&gt;size);</div><div class='add'>+	offset = min_t(u32, offset, PAGE_SIZE) / sizeof(u64) - 1;</div><div class='add'>+	if (cpu_map[offset] != get_val) {</div><div class='add'>+		KUNIT_FAIL(test,</div><div class='add'>+			   "Expected CCS readout 0x%016llx, got 0x%016llx.\n",</div><div class='add'>+			   (unsigned long long)get_val,</div><div class='add'>+			   (unsigned long long)cpu_map[offset]);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cpu_map[0] = assign_val;</div><div class='add'>+	cpu_map[offset] = assign_val;</div><div class='add'>+	kunmap_local(cpu_map);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ccs_test_run_tile(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+			      struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* TODO: Sanity check */</div><div class='add'>+	unsigned int bo_flags = XE_BO_CREATE_VRAM_IF_DGFX(tile);</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		kunit_info(test, "Testing vram id %u\n", tile-&gt;id);</div><div class='add'>+	else</div><div class='add'>+		kunit_info(test, "Testing system memory\n");</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_user(xe, NULL, NULL, SZ_1M, DRM_XE_GEM_CPU_CACHING_WC,</div><div class='add'>+			       ttm_bo_type_device, bo_flags);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to create bo.\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_bo_lock(bo, false);</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Verifying that CCS data is cleared on creation.\n");</div><div class='add'>+	ret = ccs_test_migrate(tile, bo, false, 0ULL, 0xdeadbeefdeadbeefULL,</div><div class='add'>+			       test);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Verifying that CCS data survives migration.\n");</div><div class='add'>+	ret = ccs_test_migrate(tile, bo, false, 0xdeadbeefdeadbeefULL,</div><div class='add'>+			       0xdeadbeefdeadbeefULL, test);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Verifying that CCS data can be properly cleared.\n");</div><div class='add'>+	ret = ccs_test_migrate(tile, bo, true, 0ULL, 0ULL, test);</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	xe_bo_unlock(bo);</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ccs_test_run_device(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	if (!xe_device_has_flat_ccs(xe)) {</div><div class='add'>+		kunit_info(test, "Skipping non-flat-ccs device.\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		/* For igfx run only for primary tile */</div><div class='add'>+		if (!IS_DGFX(xe) &amp;&amp; id &gt; 0)</div><div class='add'>+			continue;</div><div class='add'>+		ccs_test_run_tile(xe, tile, test);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ccs_migrate_kunit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_device(ccs_test_run_device);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_ccs_migrate_kunit);</div><div class='add'>+</div><div class='add'>+static int evict_test_run_tile(struct xe_device *xe, struct xe_tile *tile, struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo, *external;</div><div class='add'>+	unsigned int bo_flags = XE_BO_CREATE_VRAM_IF_DGFX(tile);</div><div class='add'>+	struct xe_vm *vm = xe_migrate_get_vm(xe_device_get_root_tile(xe)-&gt;migrate);</div><div class='add'>+	struct xe_gt *__gt;</div><div class='add'>+	int err, i, id;</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Testing device %s vram id %u\n",</div><div class='add'>+		   dev_name(xe-&gt;drm.dev), tile-&gt;id);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 2; ++i) {</div><div class='add'>+		xe_vm_lock(vm, false);</div><div class='add'>+		bo = xe_bo_create_user(xe, NULL, vm, 0x10000,</div><div class='add'>+				       DRM_XE_GEM_CPU_CACHING_WC,</div><div class='add'>+				       ttm_bo_type_device,</div><div class='add'>+				       bo_flags);</div><div class='add'>+		xe_vm_unlock(vm);</div><div class='add'>+		if (IS_ERR(bo)) {</div><div class='add'>+			KUNIT_FAIL(test, "bo create err=%pe\n", bo);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		external = xe_bo_create_user(xe, NULL, NULL, 0x10000,</div><div class='add'>+					     DRM_XE_GEM_CPU_CACHING_WC,</div><div class='add'>+					     ttm_bo_type_device, bo_flags);</div><div class='add'>+		if (IS_ERR(external)) {</div><div class='add'>+			KUNIT_FAIL(test, "external bo create err=%pe\n", external);</div><div class='add'>+			goto cleanup_bo;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(external, false);</div><div class='add'>+		err = xe_bo_pin_external(external);</div><div class='add'>+		xe_bo_unlock(external);</div><div class='add'>+		if (err) {</div><div class='add'>+			KUNIT_FAIL(test, "external bo pin err=%pe\n",</div><div class='add'>+				   ERR_PTR(err));</div><div class='add'>+			goto cleanup_external;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		err = xe_bo_evict_all(xe);</div><div class='add'>+		if (err) {</div><div class='add'>+			KUNIT_FAIL(test, "evict err=%pe\n", ERR_PTR(err));</div><div class='add'>+			goto cleanup_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for_each_gt(__gt, xe, id)</div><div class='add'>+			xe_gt_sanitize(__gt);</div><div class='add'>+		err = xe_bo_restore_kernel(xe);</div><div class='add'>+		/*</div><div class='add'>+		 * Snapshotting the CTB and copying back a potentially old</div><div class='add'>+		 * version seems risky, depending on what might have been</div><div class='add'>+		 * inflight. Also it seems snapshotting the ADS object and</div><div class='add'>+		 * copying back results in serious breakage. Normally when</div><div class='add'>+		 * calling xe_bo_restore_kernel() we always fully restart the</div><div class='add'>+		 * GT, which re-intializes such things.  We could potentially</div><div class='add'>+		 * skip saving and restoring such objects in xe_bo_evict_all()</div><div class='add'>+		 * however seems quite fragile not to also restart the GT. Try</div><div class='add'>+		 * to do that here by triggering a GT reset.</div><div class='add'>+		 */</div><div class='add'>+		for_each_gt(__gt, xe, id) {</div><div class='add'>+			xe_gt_reset_async(__gt);</div><div class='add'>+			flush_work(&amp;__gt-&gt;reset.worker);</div><div class='add'>+		}</div><div class='add'>+		if (err) {</div><div class='add'>+			KUNIT_FAIL(test, "restore kernel err=%pe\n",</div><div class='add'>+				   ERR_PTR(err));</div><div class='add'>+			goto cleanup_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		err = xe_bo_restore_user(xe);</div><div class='add'>+		if (err) {</div><div class='add'>+			KUNIT_FAIL(test, "restore user err=%pe\n", ERR_PTR(err));</div><div class='add'>+			goto cleanup_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!xe_bo_is_vram(external)) {</div><div class='add'>+			KUNIT_FAIL(test, "external bo is not vram\n");</div><div class='add'>+			err = -EPROTO;</div><div class='add'>+			goto cleanup_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (xe_bo_is_vram(bo)) {</div><div class='add'>+			KUNIT_FAIL(test, "bo is vram\n");</div><div class='add'>+			err = -EPROTO;</div><div class='add'>+			goto cleanup_all;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (i) {</div><div class='add'>+			down_read(&amp;vm-&gt;lock);</div><div class='add'>+			xe_vm_lock(vm, false);</div><div class='add'>+			err = xe_bo_validate(bo, bo-&gt;vm, false);</div><div class='add'>+			xe_vm_unlock(vm);</div><div class='add'>+			up_read(&amp;vm-&gt;lock);</div><div class='add'>+			if (err) {</div><div class='add'>+				KUNIT_FAIL(test, "bo valid err=%pe\n",</div><div class='add'>+					   ERR_PTR(err));</div><div class='add'>+				goto cleanup_all;</div><div class='add'>+			}</div><div class='add'>+			xe_bo_lock(external, false);</div><div class='add'>+			err = xe_bo_validate(external, NULL, false);</div><div class='add'>+			xe_bo_unlock(external);</div><div class='add'>+			if (err) {</div><div class='add'>+				KUNIT_FAIL(test, "external bo valid err=%pe\n",</div><div class='add'>+					   ERR_PTR(err));</div><div class='add'>+				goto cleanup_all;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(external, false);</div><div class='add'>+		xe_bo_unpin_external(external);</div><div class='add'>+		xe_bo_unlock(external);</div><div class='add'>+</div><div class='add'>+		xe_bo_put(external);</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		__xe_bo_unset_bulk_move(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		continue;</div><div class='add'>+</div><div class='add'>+cleanup_all:</div><div class='add'>+		xe_bo_lock(external, false);</div><div class='add'>+		xe_bo_unpin_external(external);</div><div class='add'>+		xe_bo_unlock(external);</div><div class='add'>+cleanup_external:</div><div class='add'>+		xe_bo_put(external);</div><div class='add'>+cleanup_bo:</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		__xe_bo_unset_bulk_move(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int evict_test_run_device(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe)) {</div><div class='add'>+		kunit_info(test, "Skipping non-discrete device %s.\n",</div><div class='add'>+			   dev_name(xe-&gt;drm.dev));</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		evict_test_run_tile(xe, tile, test);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_bo_evict_kunit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_device(evict_test_run_device);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_bo_evict_kunit);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_bo_test.c b/drivers/gpu/drm/xe/tests/xe_bo_test.c<br/>new file mode 100644<br/>index 000000000000..f408f17f2164<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_bo_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo_test.c</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_bo_test.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_bo_tests[] = {</div><div class='add'>+	KUNIT_CASE(xe_ccs_migrate_kunit),</div><div class='add'>+	KUNIT_CASE(xe_bo_evict_kunit),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_bo_test_suite = {</div><div class='add'>+	.name = "xe_bo",</div><div class='add'>+	.test_cases = xe_bo_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_bo_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_bo kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_bo_test.h b/drivers/gpu/drm/xe/tests/xe_bo_test.h<br/>new file mode 100644<br/>index 000000000000..0113ab45066a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_bo_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_bo_test.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BO_TEST_H_</div><div class='add'>+#define _XE_BO_TEST_H_</div><div class='add'>+</div><div class='add'>+struct kunit;</div><div class='add'>+</div><div class='add'>+void xe_ccs_migrate_kunit(struct kunit *test);</div><div class='add'>+void xe_bo_evict_kunit(struct kunit *test);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_dma_buf.c b/drivers/gpu/drm/xe/tests/xe_dma_buf.c<br/>new file mode 100644<br/>index 000000000000..9f6d571d7fa9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf.c</a></div><div class='hunk'>@@ -0,0 +1,278 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 AND MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_dma_buf_test.h"</div><div class='add'>+#include "tests/xe_pci_test.h"</div><div class='add'>+</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+</div><div class='add'>+static bool p2p_enabled(struct dma_buf_test_params *params)</div><div class='add'>+{</div><div class='add'>+	return IS_ENABLED(CONFIG_PCI_P2PDMA) &amp;&amp; params-&gt;attach_ops &amp;&amp;</div><div class='add'>+		params-&gt;attach_ops-&gt;allow_peer2peer;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_dynamic(struct dma_buf_test_params *params)</div><div class='add'>+{</div><div class='add'>+	return IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY) &amp;&amp; params-&gt;attach_ops &amp;&amp;</div><div class='add'>+		params-&gt;attach_ops-&gt;move_notify;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void check_residency(struct kunit *test, struct xe_bo *exported,</div><div class='add'>+			    struct xe_bo *imported, struct dma_buf *dmabuf)</div><div class='add'>+{</div><div class='add'>+	struct dma_buf_test_params *params = to_dma_buf_test_params(test-&gt;priv);</div><div class='add'>+	u32 mem_type;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(exported);</div><div class='add'>+	xe_bo_assert_held(imported);</div><div class='add'>+</div><div class='add'>+	mem_type = XE_PL_VRAM0;</div><div class='add'>+	if (!(params-&gt;mem_mask &amp; XE_BO_CREATE_VRAM0_BIT))</div><div class='add'>+		/* No VRAM allowed */</div><div class='add'>+		mem_type = XE_PL_TT;</div><div class='add'>+	else if (params-&gt;force_different_devices &amp;&amp; !p2p_enabled(params))</div><div class='add'>+		/* No P2P */</div><div class='add'>+		mem_type = XE_PL_TT;</div><div class='add'>+	else if (params-&gt;force_different_devices &amp;&amp; !is_dynamic(params) &amp;&amp;</div><div class='add'>+		 (params-&gt;mem_mask &amp; XE_BO_CREATE_SYSTEM_BIT))</div><div class='add'>+		/* Pin migrated to TT */</div><div class='add'>+		mem_type = XE_PL_TT;</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_mem_type(exported, mem_type)) {</div><div class='add'>+		KUNIT_FAIL(test, "Exported bo was not in expected memory type.\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_pinned(exported))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Evict exporter. Note that the gem object dma_buf member isn't</div><div class='add'>+	 * set from xe_gem_prime_export(), and it's needed for the move_notify()</div><div class='add'>+	 * functionality, so hack that up here. Evicting the exported bo will</div><div class='add'>+	 * evict also the imported bo through the move_notify() functionality if</div><div class='add'>+	 * importer is on a different device. If they're on the same device,</div><div class='add'>+	 * the exporter and the importer should be the same bo.</div><div class='add'>+	 */</div><div class='add'>+	swap(exported-&gt;ttm.base.dma_buf, dmabuf);</div><div class='add'>+	ret = xe_bo_evict(exported, true);</div><div class='add'>+	swap(exported-&gt;ttm.base.dma_buf, dmabuf);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (ret != -EINTR &amp;&amp; ret != -ERESTARTSYS)</div><div class='add'>+			KUNIT_FAIL(test, "Evicting exporter failed with err=%d.\n",</div><div class='add'>+				   ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Verify that also importer has been evicted to SYSTEM */</div><div class='add'>+	if (exported != imported &amp;&amp; !xe_bo_is_mem_type(imported, XE_PL_SYSTEM)) {</div><div class='add'>+		KUNIT_FAIL(test, "Importer wasn't properly evicted.\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Re-validate the importer. This should move also exporter in. */</div><div class='add'>+	ret = xe_bo_validate(imported, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (ret != -EINTR &amp;&amp; ret != -ERESTARTSYS)</div><div class='add'>+			KUNIT_FAIL(test, "Validating importer failed with err=%d.\n",</div><div class='add'>+				   ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If on different devices, the exporter is kept in system  if</div><div class='add'>+	 * possible, saving a migration step as the transfer is just</div><div class='add'>+	 * likely as fast from system memory.</div><div class='add'>+	 */</div><div class='add'>+	if (params-&gt;mem_mask &amp; XE_BO_CREATE_SYSTEM_BIT)</div><div class='add'>+		KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, XE_PL_TT));</div><div class='add'>+	else</div><div class='add'>+		KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, mem_type));</div><div class='add'>+</div><div class='add'>+	if (params-&gt;force_different_devices)</div><div class='add'>+		KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(imported, XE_PL_TT));</div><div class='add'>+	else</div><div class='add'>+		KUNIT_EXPECT_TRUE(test, exported == imported);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_test_dmabuf_import_same_driver(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	struct dma_buf_test_params *params = to_dma_buf_test_params(test-&gt;priv);</div><div class='add'>+	struct drm_gem_object *import;</div><div class='add'>+	struct dma_buf *dmabuf;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	size_t size;</div><div class='add'>+</div><div class='add'>+	/* No VRAM on this device? */</div><div class='add'>+	if (!ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_VRAM0) &amp;&amp;</div><div class='add'>+	    (params-&gt;mem_mask &amp; XE_BO_CREATE_VRAM0_BIT))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	size = PAGE_SIZE;</div><div class='add'>+	if ((params-&gt;mem_mask &amp; XE_BO_CREATE_VRAM0_BIT) &amp;&amp;</div><div class='add'>+	    xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K)</div><div class='add'>+		size = SZ_64K;</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "running %s\n", __func__);</div><div class='add'>+	bo = xe_bo_create_user(xe, NULL, NULL, size, DRM_XE_GEM_CPU_CACHING_WC,</div><div class='add'>+			       ttm_bo_type_device, XE_BO_CREATE_USER_BIT | params-&gt;mem_mask);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		KUNIT_FAIL(test, "xe_bo_create() failed with err=%ld\n",</div><div class='add'>+			   PTR_ERR(bo));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dmabuf = xe_gem_prime_export(&amp;bo-&gt;ttm.base, 0);</div><div class='add'>+	if (IS_ERR(dmabuf)) {</div><div class='add'>+		KUNIT_FAIL(test, "xe_gem_prime_export() failed with err=%ld\n",</div><div class='add'>+			   PTR_ERR(dmabuf));</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	import = xe_gem_prime_import(&amp;xe-&gt;drm, dmabuf);</div><div class='add'>+	if (!IS_ERR(import)) {</div><div class='add'>+		struct xe_bo *import_bo = gem_to_xe_bo(import);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Did import succeed when it shouldn't due to lack of p2p support?</div><div class='add'>+		 */</div><div class='add'>+		if (params-&gt;force_different_devices &amp;&amp;</div><div class='add'>+		    !p2p_enabled(params) &amp;&amp;</div><div class='add'>+		    !(params-&gt;mem_mask &amp; XE_BO_CREATE_SYSTEM_BIT)) {</div><div class='add'>+			KUNIT_FAIL(test,</div><div class='add'>+				   "xe_gem_prime_import() succeeded when it shouldn't have\n");</div><div class='add'>+		} else {</div><div class='add'>+			int err;</div><div class='add'>+</div><div class='add'>+			/* Is everything where we expect it to be? */</div><div class='add'>+			xe_bo_lock(import_bo, false);</div><div class='add'>+			err = xe_bo_validate(import_bo, NULL, false);</div><div class='add'>+</div><div class='add'>+			/* Pinning in VRAM is not allowed. */</div><div class='add'>+			if (!is_dynamic(params) &amp;&amp;</div><div class='add'>+			    params-&gt;force_different_devices &amp;&amp;</div><div class='add'>+			    !(params-&gt;mem_mask &amp; XE_BO_CREATE_SYSTEM_BIT))</div><div class='add'>+				KUNIT_EXPECT_EQ(test, err, -EINVAL);</div><div class='add'>+			/* Otherwise only expect interrupts or success. */</div><div class='add'>+			else if (err &amp;&amp; err != -EINTR &amp;&amp; err != -ERESTARTSYS)</div><div class='add'>+				KUNIT_EXPECT_TRUE(test, !err || err == -EINTR ||</div><div class='add'>+						  err == -ERESTARTSYS);</div><div class='add'>+</div><div class='add'>+			if (!err)</div><div class='add'>+				check_residency(test, bo, import_bo, dmabuf);</div><div class='add'>+			xe_bo_unlock(import_bo);</div><div class='add'>+		}</div><div class='add'>+		drm_gem_object_put(import);</div><div class='add'>+	} else if (PTR_ERR(import) != -EOPNOTSUPP) {</div><div class='add'>+		/* Unexpected error code. */</div><div class='add'>+		KUNIT_FAIL(test,</div><div class='add'>+			   "xe_gem_prime_import failed with the wrong err=%ld\n",</div><div class='add'>+			   PTR_ERR(import));</div><div class='add'>+	} else if (!params-&gt;force_different_devices ||</div><div class='add'>+		   p2p_enabled(params) ||</div><div class='add'>+		   (params-&gt;mem_mask &amp; XE_BO_CREATE_SYSTEM_BIT)) {</div><div class='add'>+		/* Shouldn't fail if we can reuse same bo, use p2p or use system */</div><div class='add'>+		KUNIT_FAIL(test, "dynamic p2p attachment failed with err=%ld\n",</div><div class='add'>+			   PTR_ERR(import));</div><div class='add'>+	}</div><div class='add'>+	dma_buf_put(dmabuf);</div><div class='add'>+out:</div><div class='add'>+	drm_gem_object_put(&amp;bo-&gt;ttm.base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_buf_attach_ops nop2p_attach_ops = {</div><div class='add'>+	.allow_peer2peer = false,</div><div class='add'>+	.move_notify = xe_dma_buf_move_notify</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * We test the implementation with bos of different residency and with</div><div class='add'>+ * importers with different capabilities; some lacking p2p support and some</div><div class='add'>+ * lacking dynamic capabilities (attach_ops == NULL). We also fake</div><div class='add'>+ * different devices avoiding the import shortcut that just reuses the same</div><div class='add'>+ * gem object.</div><div class='add'>+ */</div><div class='add'>+static const struct dma_buf_test_params test_params[] = {</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;xe_dma_buf_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .attach_ops = &amp;nop2p_attach_ops,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT},</div><div class='add'>+	{.mem_mask = XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_VRAM0_BIT,</div><div class='add'>+	 .force_different_devices = true},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dma_buf_run_device(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	const struct dma_buf_test_params *params;</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+</div><div class='add'>+	for (params = test_params; params-&gt;mem_mask; ++params) {</div><div class='add'>+		struct dma_buf_test_params p = *params;</div><div class='add'>+</div><div class='add'>+		p.base.id = XE_TEST_LIVE_DMA_BUF;</div><div class='add'>+		test-&gt;priv = &amp;p;</div><div class='add'>+		xe_test_dmabuf_import_same_driver(xe);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* A non-zero return would halt iteration over driver devices */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_dma_buf_kunit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_device(dma_buf_run_device);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_dma_buf_kunit);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_dma_buf_test.c b/drivers/gpu/drm/xe/tests/xe_dma_buf_test.c<br/>new file mode 100644<br/>index 000000000000..9f5a9cda8c0f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_dma_buf_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf_test.c</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_dma_buf_test.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_dma_buf_tests[] = {</div><div class='add'>+	KUNIT_CASE(xe_dma_buf_kunit),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_dma_buf_test_suite = {</div><div class='add'>+	.name = "xe_dma_buf",</div><div class='add'>+	.test_cases = xe_dma_buf_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_dma_buf_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_dma_buf kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_dma_buf_test.h b/drivers/gpu/drm/xe/tests/xe_dma_buf_test.h<br/>new file mode 100644<br/>index 000000000000..e6b464ddd526<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_dma_buf_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_dma_buf_test.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DMA_BUF_TEST_H_</div><div class='add'>+#define _XE_DMA_BUF_TEST_H_</div><div class='add'>+</div><div class='add'>+struct kunit;</div><div class='add'>+</div><div class='add'>+void xe_dma_buf_kunit(struct kunit *test);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_lmtt_test.c b/drivers/gpu/drm/xe/tests/xe_lmtt_test.c<br/>new file mode 100644<br/>index 000000000000..1f1557c45ae1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_lmtt_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_lmtt_test.c</a></div><div class='hunk'>@@ -0,0 +1,73 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 AND MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+static const struct lmtt_ops_param {</div><div class='add'>+	const char *desc;</div><div class='add'>+	const struct xe_lmtt_ops *ops;</div><div class='add'>+} lmtt_ops_params[] = {</div><div class='add'>+	{ "2-level", &amp;lmtt_2l_ops, },</div><div class='add'>+	{ "multi-level", &amp;lmtt_ml_ops, },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void lmtt_ops_param_get_desc(const struct lmtt_ops_param *p, char *desc)</div><div class='add'>+{</div><div class='add'>+	snprintf(desc, KUNIT_PARAM_DESC_SIZE, "%s", p-&gt;desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+KUNIT_ARRAY_PARAM(lmtt_ops, lmtt_ops_params, lmtt_ops_param_get_desc);</div><div class='add'>+</div><div class='add'>+static void test_ops(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	const struct lmtt_ops_param *p = test-&gt;param_value;</div><div class='add'>+	const struct xe_lmtt_ops *ops = p-&gt;ops;</div><div class='add'>+	unsigned int n;</div><div class='add'>+</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_root_pd_level);</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_pte_num);</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_pte_size);</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_pte_shift);</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_pte_index);</div><div class='add'>+	KUNIT_ASSERT_NOT_NULL(test, ops-&gt;lmtt_pte_encode);</div><div class='add'>+</div><div class='add'>+	KUNIT_EXPECT_NE(test, ops-&gt;lmtt_root_pd_level(), 0);</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt;= ops-&gt;lmtt_root_pd_level(); n++) {</div><div class='add'>+		KUNIT_EXPECT_NE_MSG(test, ops-&gt;lmtt_pte_num(n), 0,</div><div class='add'>+				    "level=%u", n);</div><div class='add'>+		KUNIT_EXPECT_NE_MSG(test, ops-&gt;lmtt_pte_size(n), 0,</div><div class='add'>+				    "level=%u", n);</div><div class='add'>+		KUNIT_EXPECT_NE_MSG(test, ops-&gt;lmtt_pte_encode(0, n), LMTT_PTE_INVALID,</div><div class='add'>+				    "level=%u", n);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt; ops-&gt;lmtt_root_pd_level(); n++) {</div><div class='add'>+		u64 addr = BIT_ULL(ops-&gt;lmtt_pte_shift(n));</div><div class='add'>+</div><div class='add'>+		KUNIT_EXPECT_NE_MSG(test, ops-&gt;lmtt_pte_shift(n), 0,</div><div class='add'>+				    "level=%u", n);</div><div class='add'>+		KUNIT_EXPECT_EQ_MSG(test, ops-&gt;lmtt_pte_index(addr - 1, n), 0,</div><div class='add'>+				    "addr=%#llx level=%u", addr, n);</div><div class='add'>+		KUNIT_EXPECT_EQ_MSG(test, ops-&gt;lmtt_pte_index(addr + 1, n), 1,</div><div class='add'>+				    "addr=%#llx level=%u", addr, n);</div><div class='add'>+		KUNIT_EXPECT_EQ_MSG(test, ops-&gt;lmtt_pte_index(addr * 2 - 1, n), 1,</div><div class='add'>+				    "addr=%#llx level=%u", addr, n);</div><div class='add'>+		KUNIT_EXPECT_EQ_MSG(test, ops-&gt;lmtt_pte_index(addr * 2, n), 2,</div><div class='add'>+				    "addr=%#llx level=%u", addr, n);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kunit_case lmtt_test_cases[] = {</div><div class='add'>+	KUNIT_CASE_PARAM(test_ops, lmtt_ops_gen_params),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite lmtt_suite = {</div><div class='add'>+	.name = "lmtt",</div><div class='add'>+	.test_cases = lmtt_test_cases,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suites(&amp;lmtt_suite);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c<br/>new file mode 100644<br/>index 000000000000..a6523df0f1d3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate.c</a></div><div class='hunk'>@@ -0,0 +1,444 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2020-2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_migrate_test.h"</div><div class='add'>+#include "tests/xe_pci_test.h"</div><div class='add'>+</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+</div><div class='add'>+static bool sanity_fence_failed(struct xe_device *xe, struct dma_fence *fence,</div><div class='add'>+				const char *str, struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	long ret;</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(fence)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to create fence for %s: %li\n", str,</div><div class='add'>+			   PTR_ERR(fence));</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+	if (!fence)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	ret = dma_fence_wait_timeout(fence, false, 5 * HZ);</div><div class='add'>+	if (ret &lt;= 0) {</div><div class='add'>+		KUNIT_FAIL(test, "Fence timed out for %s: %li\n", str, ret);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe,</div><div class='add'>+			  struct xe_bb *bb, u32 second_idx, const char *str,</div><div class='add'>+			  struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	u64 batch_base = xe_migrate_batch_base(m, xe-&gt;info.has_usm);</div><div class='add'>+	struct xe_sched_job *job = xe_bb_create_migration_job(m-&gt;q, bb,</div><div class='add'>+							      batch_base,</div><div class='add'>+							      second_idx);</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",</div><div class='add'>+			   PTR_ERR(job));</div><div class='add'>+		return PTR_ERR(job);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	if (sanity_fence_failed(xe, fence, str, test))</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	kunit_info(test, "%s: Job completed\n", str);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+sanity_populate_cb(struct xe_migrate_pt_update *pt_update,</div><div class='add'>+		   struct xe_tile *tile, struct iosys_map *map, void *dst,</div><div class='add'>+		   u32 qword_ofs, u32 num_qwords,</div><div class='add'>+		   const struct xe_vm_pgtable_update *update)</div><div class='add'>+{</div><div class='add'>+	struct migrate_test_params *p =</div><div class='add'>+		to_migrate_test_params(xe_cur_kunit_priv(XE_TEST_LIVE_MIGRATE));</div><div class='add'>+	int i;</div><div class='add'>+	u64 *ptr = dst;</div><div class='add'>+	u64 value;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_qwords; i++) {</div><div class='add'>+		value = (qword_ofs + i - update-&gt;ofs) * 0x1111111111111111ULL;</div><div class='add'>+		if (map)</div><div class='add'>+			xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *</div><div class='add'>+				  sizeof(u64), u64, value);</div><div class='add'>+		else</div><div class='add'>+			ptr[i] = value;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kunit_info(xe_cur_kunit(), "Used %s.\n", map ? "CPU" : "GPU");</div><div class='add'>+	if (p-&gt;force_gpu &amp;&amp; map)</div><div class='add'>+		KUNIT_FAIL(xe_cur_kunit(), "GPU pagetable update used CPU.\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_migrate_pt_update_ops sanity_ops = {</div><div class='add'>+	.populate = sanity_populate_cb,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define check(_retval, _expected, str, _test)				\</div><div class='add'>+	do { if ((_retval) != (_expected)) {				\</div><div class='add'>+			KUNIT_FAIL(_test, "Sanity check failed: " str	\</div><div class='add'>+				   " expected %llx, got %llx\n",	\</div><div class='add'>+				   (u64)(_expected), (u64)(_retval));	\</div><div class='add'>+		} } while (0)</div><div class='add'>+</div><div class='add'>+static void test_copy(struct xe_migrate *m, struct xe_bo *bo,</div><div class='add'>+		      struct kunit *test, u32 region)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(m-&gt;tile);</div><div class='add'>+	u64 retval, expected = 0;</div><div class='add'>+	bool big = bo-&gt;size &gt;= SZ_2M;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	const char *str = big ? "Copying big bo" : "Copying small bo";</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	struct xe_bo *remote = xe_bo_create_locked(xe, m-&gt;tile, NULL,</div><div class='add'>+						   bo-&gt;size,</div><div class='add'>+						   ttm_bo_type_kernel,</div><div class='add'>+						   region |</div><div class='add'>+						   XE_BO_NEEDS_CPU_ACCESS);</div><div class='add'>+	if (IS_ERR(remote)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to allocate remote bo for %s: %li\n",</div><div class='add'>+			   str, PTR_ERR(remote));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_bo_validate(remote, NULL, false);</div><div class='add'>+	if (err) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to validate system bo for %s: %li\n",</div><div class='add'>+			   str, err);</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_bo_vmap(remote);</div><div class='add'>+	if (err) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to vmap system bo for %s: %li\n",</div><div class='add'>+			   str, err);</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_map_memset(xe, &amp;remote-&gt;vmap, 0, 0xd0, remote-&gt;size);</div><div class='add'>+	fence = xe_migrate_clear(m, remote, remote-&gt;ttm.resource);</div><div class='add'>+	if (!sanity_fence_failed(xe, fence, big ? "Clearing remote big bo" :</div><div class='add'>+				 "Clearing remote small bo", test)) {</div><div class='add'>+		retval = xe_map_rd(xe, &amp;remote-&gt;vmap, 0, u64);</div><div class='add'>+		check(retval, expected, "remote first offset should be cleared",</div><div class='add'>+		      test);</div><div class='add'>+		retval = xe_map_rd(xe, &amp;remote-&gt;vmap, remote-&gt;size - 8, u64);</div><div class='add'>+		check(retval, expected, "remote last offset should be cleared",</div><div class='add'>+		      test);</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	/* Try to copy 0xc0 from remote to vram with 2MB or 64KiB/4KiB pages */</div><div class='add'>+	xe_map_memset(xe, &amp;remote-&gt;vmap, 0, 0xc0, remote-&gt;size);</div><div class='add'>+	xe_map_memset(xe, &amp;bo-&gt;vmap, 0, 0xd0, bo-&gt;size);</div><div class='add'>+</div><div class='add'>+	expected = 0xc0c0c0c0c0c0c0c0;</div><div class='add'>+	fence = xe_migrate_copy(m, remote, bo, remote-&gt;ttm.resource,</div><div class='add'>+				bo-&gt;ttm.resource, false);</div><div class='add'>+	if (!sanity_fence_failed(xe, fence, big ? "Copying big bo remote -&gt; vram" :</div><div class='add'>+				 "Copying small bo remote -&gt; vram", test)) {</div><div class='add'>+		retval = xe_map_rd(xe, &amp;bo-&gt;vmap, 0, u64);</div><div class='add'>+		check(retval, expected,</div><div class='add'>+		      "remote -&gt; vram bo first offset should be copied", test);</div><div class='add'>+		retval = xe_map_rd(xe, &amp;bo-&gt;vmap, bo-&gt;size - 8, u64);</div><div class='add'>+		check(retval, expected,</div><div class='add'>+		      "remote -&gt; vram bo offset should be copied", test);</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	/* And other way around.. slightly hacky.. */</div><div class='add'>+	xe_map_memset(xe, &amp;remote-&gt;vmap, 0, 0xd0, remote-&gt;size);</div><div class='add'>+	xe_map_memset(xe, &amp;bo-&gt;vmap, 0, 0xc0, bo-&gt;size);</div><div class='add'>+</div><div class='add'>+	fence = xe_migrate_copy(m, bo, remote, bo-&gt;ttm.resource,</div><div class='add'>+				remote-&gt;ttm.resource, false);</div><div class='add'>+	if (!sanity_fence_failed(xe, fence, big ? "Copying big bo vram -&gt; remote" :</div><div class='add'>+				 "Copying small bo vram -&gt; remote", test)) {</div><div class='add'>+		retval = xe_map_rd(xe, &amp;remote-&gt;vmap, 0, u64);</div><div class='add'>+		check(retval, expected,</div><div class='add'>+		      "vram -&gt; remote bo first offset should be copied", test);</div><div class='add'>+		retval = xe_map_rd(xe, &amp;remote-&gt;vmap, bo-&gt;size - 8, u64);</div><div class='add'>+		check(retval, expected,</div><div class='add'>+		      "vram -&gt; remote bo last offset should be copied", test);</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	xe_bo_vunmap(remote);</div><div class='add'>+out_unlock:</div><div class='add'>+	xe_bo_unlock(remote);</div><div class='add'>+	xe_bo_put(remote);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void test_copy_sysmem(struct xe_migrate *m, struct xe_bo *bo,</div><div class='add'>+			     struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	test_copy(m, bo, test, XE_BO_CREATE_SYSTEM_BIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void test_copy_vram(struct xe_migrate *m, struct xe_bo *bo,</div><div class='add'>+			   struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	u32 region;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.resource-&gt;mem_type == XE_PL_SYSTEM)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.resource-&gt;mem_type == XE_PL_VRAM0)</div><div class='add'>+		region = XE_BO_CREATE_VRAM1_BIT;</div><div class='add'>+	else</div><div class='add'>+		region = XE_BO_CREATE_VRAM0_BIT;</div><div class='add'>+	test_copy(m, bo, test, region);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt,</div><div class='add'>+			   struct kunit *test, bool force_gpu)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(m-&gt;tile);</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	u64 retval, expected;</div><div class='add'>+	ktime_t then, now;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	struct xe_vm_pgtable_update update = {</div><div class='add'>+		.ofs = 1,</div><div class='add'>+		.qwords = 0x10,</div><div class='add'>+		.pt_bo = pt,</div><div class='add'>+	};</div><div class='add'>+	struct xe_migrate_pt_update pt_update = {</div><div class='add'>+		.ops = &amp;sanity_ops,</div><div class='add'>+	};</div><div class='add'>+	struct migrate_test_params p = {</div><div class='add'>+		.base.id = XE_TEST_LIVE_MIGRATE,</div><div class='add'>+		.force_gpu = force_gpu,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	test-&gt;priv = &amp;p;</div><div class='add'>+	/* Test xe_migrate_update_pgtables() updates the pagetable as expected */</div><div class='add'>+	expected = 0xf0f0f0f0f0f0f0f0ULL;</div><div class='add'>+	xe_map_memset(xe, &amp;pt-&gt;vmap, 0, (u8)expected, pt-&gt;size);</div><div class='add'>+</div><div class='add'>+	then = ktime_get();</div><div class='add'>+	fence = xe_migrate_update_pgtables(m, m-&gt;q-&gt;vm, NULL, m-&gt;q, &amp;update, 1,</div><div class='add'>+					   NULL, 0, &amp;pt_update);</div><div class='add'>+	now = ktime_get();</div><div class='add'>+	if (sanity_fence_failed(xe, fence, "Migration pagetable update", test))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Updating without syncing took %llu us,\n",</div><div class='add'>+		   (unsigned long long)ktime_to_us(ktime_sub(now, then)));</div><div class='add'>+</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	retval = xe_map_rd(xe, &amp;pt-&gt;vmap, 0, u64);</div><div class='add'>+	check(retval, expected, "PTE[0] must stay untouched", test);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; update.qwords; i++) {</div><div class='add'>+		retval = xe_map_rd(xe, &amp;pt-&gt;vmap, (update.ofs + i) * 8, u64);</div><div class='add'>+		check(retval, i * 0x1111111111111111ULL, "PTE update", test);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	retval = xe_map_rd(xe, &amp;pt-&gt;vmap, 8 * (update.ofs + update.qwords),</div><div class='add'>+			   u64);</div><div class='add'>+	check(retval, expected, "PTE[0x11] must stay untouched", test);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = m-&gt;tile;</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_bo *pt, *bo = m-&gt;pt_bo, *big, *tiny;</div><div class='add'>+	struct xe_res_cursor src_it;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	u64 retval, expected;</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	int err;</div><div class='add'>+	u8 id = tile-&gt;id;</div><div class='add'>+</div><div class='add'>+	err = xe_bo_vmap(bo);</div><div class='add'>+	if (err) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to vmap our pagetables: %li\n",</div><div class='add'>+			   PTR_ERR(bo));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	big = xe_bo_create_pin_map(xe, tile, m-&gt;q-&gt;vm, SZ_4M,</div><div class='add'>+				   ttm_bo_type_kernel,</div><div class='add'>+				   XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				   XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	if (IS_ERR(big)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to allocate bo: %li\n", PTR_ERR(big));</div><div class='add'>+		goto vunmap;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pt = xe_bo_create_pin_map(xe, tile, m-&gt;q-&gt;vm, XE_PAGE_SIZE,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				  XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	if (IS_ERR(pt)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",</div><div class='add'>+			   PTR_ERR(pt));</div><div class='add'>+		goto free_big;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tiny = xe_bo_create_pin_map(xe, tile, m-&gt;q-&gt;vm,</div><div class='add'>+				    2 * SZ_4K,</div><div class='add'>+				    ttm_bo_type_kernel,</div><div class='add'>+				    XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				    XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	if (IS_ERR(tiny)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",</div><div class='add'>+			   PTR_ERR(pt));</div><div class='add'>+		goto free_pt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bb = xe_bb_new(tile-&gt;primary_gt, 32, xe-&gt;info.has_usm);</div><div class='add'>+	if (IS_ERR(bb)) {</div><div class='add'>+		KUNIT_FAIL(test, "Failed to create batchbuffer: %li\n",</div><div class='add'>+			   PTR_ERR(bb));</div><div class='add'>+		goto free_tiny;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Starting tests, top level PT addr: %lx, special pagetable base addr: %lx\n",</div><div class='add'>+		   (unsigned long)xe_bo_main_addr(m-&gt;q-&gt;vm-&gt;pt_root[id]-&gt;bo, XE_PAGE_SIZE),</div><div class='add'>+		   (unsigned long)xe_bo_main_addr(m-&gt;pt_bo, XE_PAGE_SIZE));</div><div class='add'>+</div><div class='add'>+	/* First part of the test, are we updating our pagetable bo with a new entry? */</div><div class='add'>+	xe_map_wr(xe, &amp;bo-&gt;vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64,</div><div class='add'>+		  0xdeaddeadbeefbeef);</div><div class='add'>+	expected = m-&gt;q-&gt;vm-&gt;pt_ops-&gt;pte_encode_bo(pt, 0, xe-&gt;pat.idx[XE_CACHE_WB], 0);</div><div class='add'>+	if (m-&gt;q-&gt;vm-&gt;flags &amp; XE_VM_FLAG_64K)</div><div class='add'>+		expected |= XE_PTE_PS64;</div><div class='add'>+	if (xe_bo_is_vram(pt))</div><div class='add'>+		xe_res_first(pt-&gt;ttm.resource, 0, pt-&gt;size, &amp;src_it);</div><div class='add'>+	else</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(pt), 0, pt-&gt;size, &amp;src_it);</div><div class='add'>+</div><div class='add'>+	emit_pte(m, bb, NUM_KERNEL_PDE - 1, xe_bo_is_vram(pt), false,</div><div class='add'>+		 &amp;src_it, XE_PAGE_SIZE, pt-&gt;ttm.resource);</div><div class='add'>+</div><div class='add'>+	run_sanity_job(m, xe, bb, bb-&gt;len, "Writing PTE for our fake PT", test);</div><div class='add'>+</div><div class='add'>+	retval = xe_map_rd(xe, &amp;bo-&gt;vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1),</div><div class='add'>+			   u64);</div><div class='add'>+	check(retval, expected, "PTE entry write", test);</div><div class='add'>+</div><div class='add'>+	/* Now try to write data to our newly mapped 'pagetable', see if it succeeds */</div><div class='add'>+	bb-&gt;len = 0;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+	xe_map_wr(xe, &amp;pt-&gt;vmap, 0, u32, 0xdeaddead);</div><div class='add'>+	expected = 0;</div><div class='add'>+</div><div class='add'>+	emit_clear(tile-&gt;primary_gt, bb, xe_migrate_vm_addr(NUM_KERNEL_PDE - 1, 0), 4, 4,</div><div class='add'>+		   IS_DGFX(xe));</div><div class='add'>+	run_sanity_job(m, xe, bb, 1, "Writing to our newly mapped pagetable",</div><div class='add'>+		       test);</div><div class='add'>+</div><div class='add'>+	retval = xe_map_rd(xe, &amp;pt-&gt;vmap, 0, u32);</div><div class='add'>+	check(retval, expected, "Write to PT after adding PTE", test);</div><div class='add'>+</div><div class='add'>+	/* Sanity checks passed, try the full ones! */</div><div class='add'>+</div><div class='add'>+	/* Clear a small bo */</div><div class='add'>+	kunit_info(test, "Clearing small buffer object\n");</div><div class='add'>+	xe_map_memset(xe, &amp;tiny-&gt;vmap, 0, 0x22, tiny-&gt;size);</div><div class='add'>+	expected = 0;</div><div class='add'>+	fence = xe_migrate_clear(m, tiny, tiny-&gt;ttm.resource);</div><div class='add'>+	if (sanity_fence_failed(xe, fence, "Clearing small bo", test))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	retval = xe_map_rd(xe, &amp;tiny-&gt;vmap, 0, u32);</div><div class='add'>+	check(retval, expected, "Command clear small first value", test);</div><div class='add'>+	retval = xe_map_rd(xe, &amp;tiny-&gt;vmap, tiny-&gt;size - 4, u32);</div><div class='add'>+	check(retval, expected, "Command clear small last value", test);</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Copying small buffer object to system\n");</div><div class='add'>+	test_copy_sysmem(m, tiny, test);</div><div class='add'>+	if (xe-&gt;info.tile_count &gt; 1) {</div><div class='add'>+		kunit_info(test, "Copying small buffer object to other vram\n");</div><div class='add'>+		test_copy_vram(m, tiny, test);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Clear a big bo */</div><div class='add'>+	kunit_info(test, "Clearing big buffer object\n");</div><div class='add'>+	xe_map_memset(xe, &amp;big-&gt;vmap, 0, 0x11, big-&gt;size);</div><div class='add'>+	expected = 0;</div><div class='add'>+	fence = xe_migrate_clear(m, big, big-&gt;ttm.resource);</div><div class='add'>+	if (sanity_fence_failed(xe, fence, "Clearing big bo", test))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	retval = xe_map_rd(xe, &amp;big-&gt;vmap, 0, u32);</div><div class='add'>+	check(retval, expected, "Command clear big first value", test);</div><div class='add'>+	retval = xe_map_rd(xe, &amp;big-&gt;vmap, big-&gt;size - 4, u32);</div><div class='add'>+	check(retval, expected, "Command clear big last value", test);</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Copying big buffer object to system\n");</div><div class='add'>+	test_copy_sysmem(m, big, test);</div><div class='add'>+	if (xe-&gt;info.tile_count &gt; 1) {</div><div class='add'>+		kunit_info(test, "Copying big buffer object to other vram\n");</div><div class='add'>+		test_copy_vram(m, big, test);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "Testing page table update using CPU if GPU idle.\n");</div><div class='add'>+	test_pt_update(m, pt, test, false);</div><div class='add'>+	kunit_info(test, "Testing page table update using GPU\n");</div><div class='add'>+	test_pt_update(m, pt, test, true);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+free_tiny:</div><div class='add'>+	xe_bo_unpin(tiny);</div><div class='add'>+	xe_bo_put(tiny);</div><div class='add'>+free_pt:</div><div class='add'>+	xe_bo_unpin(pt);</div><div class='add'>+	xe_bo_put(pt);</div><div class='add'>+free_big:</div><div class='add'>+	xe_bo_unpin(big);</div><div class='add'>+	xe_bo_put(big);</div><div class='add'>+vunmap:</div><div class='add'>+	xe_bo_vunmap(m-&gt;pt_bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int migrate_test_run_device(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		struct xe_migrate *m = tile-&gt;migrate;</div><div class='add'>+</div><div class='add'>+		kunit_info(test, "Testing tile id %d.\n", id);</div><div class='add'>+		xe_vm_lock(m-&gt;q-&gt;vm, true);</div><div class='add'>+		xe_device_mem_access_get(xe);</div><div class='add'>+		xe_migrate_sanity_test(m, test);</div><div class='add'>+		xe_device_mem_access_put(xe);</div><div class='add'>+		xe_vm_unlock(m-&gt;q-&gt;vm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_migrate_sanity_kunit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_device(migrate_test_run_device);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_migrate_sanity_kunit);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_migrate_test.c b/drivers/gpu/drm/xe/tests/xe_migrate_test.c<br/>new file mode 100644<br/>index 000000000000..cf0c173b945f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_migrate_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate_test.c</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_migrate_test.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_migrate_tests[] = {</div><div class='add'>+	KUNIT_CASE(xe_migrate_sanity_kunit),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_migrate_test_suite = {</div><div class='add'>+	.name = "xe_migrate",</div><div class='add'>+	.test_cases = xe_migrate_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_migrate_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_migrate kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_migrate_test.h b/drivers/gpu/drm/xe/tests/xe_migrate_test.h<br/>new file mode 100644<br/>index 000000000000..7c645c66824f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_migrate_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_migrate_test.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MIGRATE_TEST_H_</div><div class='add'>+#define _XE_MIGRATE_TEST_H_</div><div class='add'>+</div><div class='add'>+struct kunit;</div><div class='add'>+</div><div class='add'>+void xe_migrate_sanity_kunit(struct kunit *test);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_mocs.c b/drivers/gpu/drm/xe/tests/xe_mocs.c<br/>new file mode 100644<br/>index 000000000000..7dd34f94e809<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_mocs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs.c</a></div><div class='hunk'>@@ -0,0 +1,130 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 AND MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_mocs_test.h"</div><div class='add'>+#include "tests/xe_pci_test.h"</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+</div><div class='add'>+struct live_mocs {</div><div class='add'>+	struct xe_mocs_info table;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int live_mocs_init(struct live_mocs *arg, struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	unsigned int flags;</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+</div><div class='add'>+	memset(arg, 0, sizeof(*arg));</div><div class='add'>+</div><div class='add'>+	flags = get_mocs_settings(gt_to_xe(gt), &amp;arg-&gt;table);</div><div class='add'>+</div><div class='add'>+	kunit_info(test, "table size %d", arg-&gt;table.size);</div><div class='add'>+	kunit_info(test, "table uc_index %d", arg-&gt;table.uc_index);</div><div class='add'>+	kunit_info(test, "table n_entries %d", arg-&gt;table.n_entries);</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_l3cc_table(struct xe_gt *gt,</div><div class='add'>+			    const struct xe_mocs_info *info)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 l3cc;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	u32 ret;</div><div class='add'>+</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");</div><div class='add'>+	mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "L3CC entries:%d\n", info-&gt;n_entries);</div><div class='add'>+	for (i = 0;</div><div class='add'>+	     i &lt; (info-&gt;n_entries + 1) / 2 ?</div><div class='add'>+	     (l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),</div><div class='add'>+				  get_entry_l3cc(info, 2 * i + 1))), 1 : 0;</div><div class='add'>+	     i++) {</div><div class='add'>+		if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1250)</div><div class='add'>+			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));</div><div class='add'>+		else</div><div class='add'>+			reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));</div><div class='add'>+		mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "%d 0x%x 0x%x 0x%x\n", i,</div><div class='add'>+			 XELP_LNCFCMOCS(i).addr, reg_val, l3cc);</div><div class='add'>+		if (reg_val != l3cc)</div><div class='add'>+			KUNIT_FAIL(test, "l3cc reg 0x%x has incorrect val.\n",</div><div class='add'>+				   XELP_LNCFCMOCS(i).addr);</div><div class='add'>+	}</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_mocs_table(struct xe_gt *gt,</div><div class='add'>+			    const struct xe_mocs_info *info)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 mocs;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	u32 ret;</div><div class='add'>+</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");</div><div class='add'>+	mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "Global MOCS entries:%d\n", info-&gt;n_entries);</div><div class='add'>+	drm_WARN_ONCE(&amp;xe-&gt;drm, !info-&gt;unused_entries_index,</div><div class='add'>+		      "Unused entries index should have been defined\n");</div><div class='add'>+	for (i = 0;</div><div class='add'>+	     i &lt; info-&gt;n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;</div><div class='add'>+	     i++) {</div><div class='add'>+		if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1250)</div><div class='add'>+			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));</div><div class='add'>+		else</div><div class='add'>+			reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));</div><div class='add'>+		mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "%d 0x%x 0x%x 0x%x\n", i,</div><div class='add'>+			 XELP_GLOBAL_MOCS(i).addr, reg_val, mocs);</div><div class='add'>+		if (reg_val != mocs)</div><div class='add'>+			KUNIT_FAIL(test, "mocs reg 0x%x has incorrect val.\n",</div><div class='add'>+				   XELP_GLOBAL_MOCS(i).addr);</div><div class='add'>+	}</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mocs_kernel_test_run_device(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	/* Basic check the system is configured with the expected mocs table */</div><div class='add'>+</div><div class='add'>+	struct live_mocs mocs;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+</div><div class='add'>+	unsigned int flags;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		flags = live_mocs_init(&amp;mocs, gt);</div><div class='add'>+		if (flags &amp; HAS_GLOBAL_MOCS)</div><div class='add'>+			read_mocs_table(gt, &amp;mocs.table);</div><div class='add'>+		if (flags &amp; HAS_LNCF_MOCS)</div><div class='add'>+			read_l3cc_table(gt, &amp;mocs.table);</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_live_mocs_kernel_kunit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_device(mocs_kernel_test_run_device);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_live_mocs_kernel_kunit);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_mocs_test.c b/drivers/gpu/drm/xe/tests/xe_mocs_test.c<br/>new file mode 100644<br/>index 000000000000..ef56bd517b28<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_mocs_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs_test.c</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_mocs_test.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_mocs_tests[] = {</div><div class='add'>+	KUNIT_CASE(xe_live_mocs_kernel_kunit),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_mocs_test_suite = {</div><div class='add'>+	.name = "xe_mocs",</div><div class='add'>+	.test_cases = xe_mocs_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_mocs_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_mocs_test.h b/drivers/gpu/drm/xe/tests/xe_mocs_test.h<br/>new file mode 100644<br/>index 000000000000..7faa3575e6c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_mocs_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_mocs_test.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MOCS_TEST_H_</div><div class='add'>+#define _XE_MOCS_TEST_H_</div><div class='add'>+</div><div class='add'>+struct kunit;</div><div class='add'>+</div><div class='add'>+void xe_live_mocs_kernel_kunit(struct kunit *test);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_pci.c b/drivers/gpu/drm/xe/tests/xe_pci.c<br/>new file mode 100644<br/>index 000000000000..602793644f61<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci.c</a></div><div class='hunk'>@@ -0,0 +1,166 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 AND MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "tests/xe_pci_test.h"</div><div class='add'>+</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test-bug.h&gt;</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;kunit/test-bug.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+struct kunit_test_data {</div><div class='add'>+	int ndevs;</div><div class='add'>+	xe_device_fn xe_fn;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dev_to_xe_device_fn(struct device *dev, void *__data)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	struct drm_device *drm = dev_get_drvdata(dev);</div><div class='add'>+	struct kunit_test_data *data = __data;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	int idx;</div><div class='add'>+</div><div class='add'>+	data-&gt;ndevs++;</div><div class='add'>+</div><div class='add'>+	if (drm_dev_enter(drm, &amp;idx))</div><div class='add'>+		ret = data-&gt;xe_fn(to_xe_device(dev_get_drvdata(dev)));</div><div class='add'>+	drm_dev_exit(idx);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_call_for_each_device - Iterate over all devices this driver binds to</div><div class='add'>+ * @xe_fn: Function to call for each device.</div><div class='add'>+ *</div><div class='add'>+ * This function iterated over all devices this driver binds to, and calls</div><div class='add'>+ * @xe_fn: for each one of them. If the called function returns anything else</div><div class='add'>+ * than 0, iteration is stopped and the return value is returned by this</div><div class='add'>+ * function. Across each function call, drm_dev_enter() / drm_dev_exit() is</div><div class='add'>+ * called for the corresponding drm device.</div><div class='add'>+ *</div><div class='add'>+ * Return: Number of devices iterated or</div><div class='add'>+ *         the error code of a call to @xe_fn returning an error code.</div><div class='add'>+ */</div><div class='add'>+int xe_call_for_each_device(xe_device_fn xe_fn)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct kunit_test_data data = {</div><div class='add'>+	    .xe_fn = xe_fn,</div><div class='add'>+	    .ndevs = 0,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ret = driver_for_each_device(&amp;xe_pci_driver.driver, NULL,</div><div class='add'>+				     &amp;data, dev_to_xe_device_fn);</div><div class='add'>+</div><div class='add'>+	if (!data.ndevs)</div><div class='add'>+		kunit_skip(current-&gt;kunit_test, "test runs only on hardware\n");</div><div class='add'>+</div><div class='add'>+	return ret ?: data.ndevs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_call_for_each_graphics_ip - Iterate over all recognized graphics IPs</div><div class='add'>+ * @xe_fn: Function to call for each device.</div><div class='add'>+ *</div><div class='add'>+ * This function iterates over the descriptors for all graphics IPs recognized</div><div class='add'>+ * by the driver and calls @xe_fn: for each one of them.</div><div class='add'>+ */</div><div class='add'>+void xe_call_for_each_graphics_ip(xe_graphics_fn xe_fn)</div><div class='add'>+{</div><div class='add'>+	const struct xe_graphics_desc *ip, *last = NULL;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(graphics_ip_map); i++) {</div><div class='add'>+		ip = graphics_ip_map[i].ip;</div><div class='add'>+		if (ip == last)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		xe_fn(ip);</div><div class='add'>+		last = ip;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_call_for_each_graphics_ip);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_call_for_each_media_ip - Iterate over all recognized media IPs</div><div class='add'>+ * @xe_fn: Function to call for each device.</div><div class='add'>+ *</div><div class='add'>+ * This function iterates over the descriptors for all media IPs recognized</div><div class='add'>+ * by the driver and calls @xe_fn: for each one of them.</div><div class='add'>+ */</div><div class='add'>+void xe_call_for_each_media_ip(xe_media_fn xe_fn)</div><div class='add'>+{</div><div class='add'>+	const struct xe_media_desc *ip, *last = NULL;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(media_ip_map); i++) {</div><div class='add'>+		ip = media_ip_map[i].ip;</div><div class='add'>+		if (ip == last)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		xe_fn(ip);</div><div class='add'>+		last = ip;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_call_for_each_media_ip);</div><div class='add'>+</div><div class='add'>+static void fake_read_gmdid(struct xe_device *xe, enum xe_gmdid_type type,</div><div class='add'>+			    u32 *ver, u32 *revid)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = kunit_get_current_test();</div><div class='add'>+	struct xe_pci_fake_data *data = test-&gt;priv;</div><div class='add'>+</div><div class='add'>+	if (type == GMDID_MEDIA) {</div><div class='add'>+		*ver = data-&gt;media_verx100;</div><div class='add'>+		*revid = xe_step_to_gmdid(data-&gt;media_step);</div><div class='add'>+	} else {</div><div class='add'>+		*ver = data-&gt;graphics_verx100;</div><div class='add'>+		*revid = xe_step_to_gmdid(data-&gt;graphics_step);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pci_fake_device_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = kunit_get_current_test();</div><div class='add'>+	struct xe_pci_fake_data *data = test-&gt;priv;</div><div class='add'>+	const struct pci_device_id *ent = pciidlist;</div><div class='add'>+	const struct xe_device_desc *desc;</div><div class='add'>+	const struct xe_subplatform_desc *subplatform_desc;</div><div class='add'>+</div><div class='add'>+	if (!data) {</div><div class='add'>+		desc = (const void *)ent-&gt;driver_data;</div><div class='add'>+		subplatform_desc = NULL;</div><div class='add'>+		goto done;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (ent = pciidlist; ent-&gt;device; ent++) {</div><div class='add'>+		desc = (const void *)ent-&gt;driver_data;</div><div class='add'>+		if (desc-&gt;platform == data-&gt;platform)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!ent-&gt;device)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	for (subplatform_desc = desc-&gt;subplatforms;</div><div class='add'>+	     subplatform_desc &amp;&amp; subplatform_desc-&gt;subplatform;</div><div class='add'>+	     subplatform_desc++)</div><div class='add'>+		if (subplatform_desc-&gt;subplatform == data-&gt;subplatform)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;subplatform != XE_SUBPLATFORM_NONE &amp;&amp; !subplatform_desc)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+done:</div><div class='add'>+	kunit_activate_static_stub(test, read_gmdid, fake_read_gmdid);</div><div class='add'>+</div><div class='add'>+	xe_info_init_early(xe, desc, subplatform_desc);</div><div class='add'>+	xe_info_init(xe, desc-&gt;graphics, desc-&gt;media);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_pci_fake_device_init);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_pci_test.c b/drivers/gpu/drm/xe/tests/xe_pci_test.c<br/>new file mode 100644<br/>index 000000000000..171e4180f1aa<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_pci_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci_test.c</a></div><div class='hunk'>@@ -0,0 +1,71 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_kunit_helpers.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_pci_test.h"</div><div class='add'>+#include "xe_pci_types.h"</div><div class='add'>+</div><div class='add'>+static void check_graphics_ip(const struct xe_graphics_desc *graphics)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	u64 mask = graphics-&gt;hw_engine_mask;</div><div class='add'>+</div><div class='add'>+	/* RCS, CCS, and BCS engines are allowed on the graphics IP */</div><div class='add'>+	mask &amp;= ~(XE_HW_ENGINE_RCS_MASK |</div><div class='add'>+		  XE_HW_ENGINE_CCS_MASK |</div><div class='add'>+		  XE_HW_ENGINE_BCS_MASK);</div><div class='add'>+</div><div class='add'>+	/* Any remaining engines are an error */</div><div class='add'>+	KUNIT_ASSERT_EQ(test, mask, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void check_media_ip(const struct xe_media_desc *media)</div><div class='add'>+{</div><div class='add'>+	struct kunit *test = xe_cur_kunit();</div><div class='add'>+	u64 mask = media-&gt;hw_engine_mask;</div><div class='add'>+</div><div class='add'>+	/* VCS, VECS and GSCCS engines are allowed on the media IP */</div><div class='add'>+	mask &amp;= ~(XE_HW_ENGINE_VCS_MASK |</div><div class='add'>+		  XE_HW_ENGINE_VECS_MASK |</div><div class='add'>+		  XE_HW_ENGINE_GSCCS_MASK);</div><div class='add'>+</div><div class='add'>+	/* Any remaining engines are an error */</div><div class='add'>+	KUNIT_ASSERT_EQ(test, mask, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_gmdid_graphics_ip(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_graphics_ip(check_graphics_ip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_gmdid_media_ip(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	xe_call_for_each_media_ip(check_media_ip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_pci_tests[] = {</div><div class='add'>+	KUNIT_CASE(xe_gmdid_graphics_ip),</div><div class='add'>+	KUNIT_CASE(xe_gmdid_media_ip),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_pci_test_suite = {</div><div class='add'>+	.name = "xe_pci",</div><div class='add'>+	.test_cases = xe_pci_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_pci_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_pci kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_pci_test.h b/drivers/gpu/drm/xe/tests/xe_pci_test.h<br/>new file mode 100644<br/>index 000000000000..811ffe5bd9fd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_pci_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_pci_test.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PCI_TEST_H_</div><div class='add'>+#define _XE_PCI_TEST_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_graphics_desc;</div><div class='add'>+struct xe_media_desc;</div><div class='add'>+</div><div class='add'>+typedef int (*xe_device_fn)(struct xe_device *);</div><div class='add'>+typedef void (*xe_graphics_fn)(const struct xe_graphics_desc *);</div><div class='add'>+typedef void (*xe_media_fn)(const struct xe_media_desc *);</div><div class='add'>+</div><div class='add'>+int xe_call_for_each_device(xe_device_fn xe_fn);</div><div class='add'>+void xe_call_for_each_graphics_ip(xe_graphics_fn xe_fn);</div><div class='add'>+void xe_call_for_each_media_ip(xe_media_fn xe_fn);</div><div class='add'>+</div><div class='add'>+struct xe_pci_fake_data {</div><div class='add'>+	enum xe_platform platform;</div><div class='add'>+	enum xe_subplatform subplatform;</div><div class='add'>+	u32 graphics_verx100;</div><div class='add'>+	u32 media_verx100;</div><div class='add'>+	u32 graphics_step;</div><div class='add'>+	u32 media_step;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_pci_fake_device_init(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_rtp_test.c b/drivers/gpu/drm/xe/tests/xe_rtp_test.c<br/>new file mode 100644<br/>index 000000000000..4a6972897675<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_rtp_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_rtp_test.c</a></div><div class='hunk'>@@ -0,0 +1,319 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_kunit_helpers.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_pci_test.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+</div><div class='add'>+#define REGULAR_REG1	XE_REG(1)</div><div class='add'>+#define REGULAR_REG2	XE_REG(2)</div><div class='add'>+#define REGULAR_REG3	XE_REG(3)</div><div class='add'>+#define MCR_REG1	XE_REG_MCR(1)</div><div class='add'>+#define MCR_REG2	XE_REG_MCR(2)</div><div class='add'>+#define MCR_REG3	XE_REG_MCR(3)</div><div class='add'>+#define MASKED_REG1	XE_REG(1, XE_REG_OPTION_MASKED)</div><div class='add'>+</div><div class='add'>+#undef XE_REG_MCR</div><div class='add'>+#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)</div><div class='add'>+</div><div class='add'>+struct rtp_test_case {</div><div class='add'>+	const char *name;</div><div class='add'>+	struct xe_reg expected_reg;</div><div class='add'>+	u32 expected_set_bits;</div><div class='add'>+	u32 expected_clr_bits;</div><div class='add'>+	unsigned long expected_count;</div><div class='add'>+	unsigned int expected_sr_errors;</div><div class='add'>+	const struct xe_rtp_entry_sr *entries;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool match_yes(const struct xe_gt *gt, const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool match_no(const struct xe_gt *gt, const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct rtp_test_case cases[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "coalesce-same-reg",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0) | REG_BIT(1),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0) | REG_BIT(1),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		/* Different bits on the same register: create a single entry */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "no-match-no-add",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		/* Don't coalesce second entry since rules don't match */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_no)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "no-match-no-add-multiple-rules",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		/* Don't coalesce second entry due to one of the rules */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes), FUNC(match_no)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "two-regs-two-entries",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 2,</div><div class='add'>+		/* Same bits on different registers are not coalesced */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG2, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "clr-one-set-other",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(1) | REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		/* Check clr vs set actions on different bits */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_BIT(1)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+#define TEMP_MASK	REG_GENMASK(10, 8)</div><div class='add'>+#define TEMP_FIELD	REG_FIELD_PREP(TEMP_MASK, 2)</div><div class='add'>+		.name = "set-field",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = TEMP_FIELD,</div><div class='add'>+		.expected_clr_bits = TEMP_MASK,</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		/* Check FIELD_SET works */</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(FIELD_SET(REGULAR_REG1,</div><div class='add'>+						   TEMP_MASK, TEMP_FIELD))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+#undef TEMP_MASK</div><div class='add'>+#undef TEMP_FIELD</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "conflict-duplicate",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		.expected_sr_errors = 1,</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			/* drop: setting same values twice */</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "conflict-not-disjoint",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		.expected_sr_errors = 1,</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			/* drop: bits are not disjoint with previous entries */</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(CLR(REGULAR_REG1, REG_GENMASK(1, 0)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "conflict-reg-type",</div><div class='add'>+		.expected_reg = REGULAR_REG1,</div><div class='add'>+		.expected_set_bits = REG_BIT(0),</div><div class='add'>+		.expected_clr_bits = REG_BIT(0),</div><div class='add'>+		.expected_count = 1,</div><div class='add'>+		.expected_sr_errors = 2,</div><div class='add'>+		.entries = (const struct xe_rtp_entry_sr[]) {</div><div class='add'>+			{ XE_RTP_NAME("basic-1"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			/* drop: regular vs MCR */</div><div class='add'>+			{ XE_RTP_NAME("basic-2"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(MCR_REG1, REG_BIT(1)))</div><div class='add'>+			},</div><div class='add'>+			/* drop: regular vs masked */</div><div class='add'>+			{ XE_RTP_NAME("basic-3"),</div><div class='add'>+			  XE_RTP_RULES(FUNC(match_yes)),</div><div class='add'>+			  XE_RTP_ACTIONS(SET(MASKED_REG1, REG_BIT(0)))</div><div class='add'>+			},</div><div class='add'>+			{}</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe_rtp_process_tests(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	const struct rtp_test_case *param = test-&gt;param_value;</div><div class='add'>+	struct xe_device *xe = test-&gt;priv;</div><div class='add'>+	struct xe_gt *gt = xe_device_get_root_tile(xe)-&gt;primary_gt;</div><div class='add'>+	struct xe_reg_sr *reg_sr = &amp;gt-&gt;reg_sr;</div><div class='add'>+	const struct xe_reg_sr_entry *sre, *sr_entry = NULL;</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);</div><div class='add'>+	unsigned long idx, count = 0;</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_init(reg_sr, "xe_rtp_tests", xe);</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, param-&gt;entries, reg_sr);</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;reg_sr-&gt;xa, idx, sre) {</div><div class='add'>+		if (idx == param-&gt;expected_reg.addr)</div><div class='add'>+			sr_entry = sre;</div><div class='add'>+</div><div class='add'>+		count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	KUNIT_EXPECT_EQ(test, count, param-&gt;expected_count);</div><div class='add'>+	KUNIT_EXPECT_EQ(test, sr_entry-&gt;clr_bits, param-&gt;expected_clr_bits);</div><div class='add'>+	KUNIT_EXPECT_EQ(test, sr_entry-&gt;set_bits, param-&gt;expected_set_bits);</div><div class='add'>+	KUNIT_EXPECT_EQ(test, sr_entry-&gt;reg.raw, param-&gt;expected_reg.raw);</div><div class='add'>+	KUNIT_EXPECT_EQ(test, reg_sr-&gt;errors, param-&gt;expected_sr_errors);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtp_desc(const struct rtp_test_case *t, char *desc)</div><div class='add'>+{</div><div class='add'>+	strscpy(desc, t-&gt;name, KUNIT_PARAM_DESC_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+KUNIT_ARRAY_PARAM(rtp, cases, rtp_desc);</div><div class='add'>+</div><div class='add'>+static int xe_rtp_test_init(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dev = drm_kunit_helper_alloc_device(test);</div><div class='add'>+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);</div><div class='add'>+</div><div class='add'>+	xe = drm_kunit_helper_alloc_drm_device(test, dev,</div><div class='add'>+					       struct xe_device,</div><div class='add'>+					       drm, DRIVER_GEM);</div><div class='add'>+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, xe);</div><div class='add'>+</div><div class='add'>+	/* Initialize an empty device */</div><div class='add'>+	test-&gt;priv = NULL;</div><div class='add'>+	ret = xe_pci_fake_device_init(xe);</div><div class='add'>+	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='add'>+</div><div class='add'>+	xe-&gt;drm.dev = dev;</div><div class='add'>+	test-&gt;priv = xe;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_rtp_test_exit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = test-&gt;priv;</div><div class='add'>+</div><div class='add'>+	drm_kunit_helper_free_device(test, xe-&gt;drm.dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_rtp_tests[] = {</div><div class='add'>+	KUNIT_CASE_PARAM(xe_rtp_process_tests, rtp_gen_params),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_rtp_test_suite = {</div><div class='add'>+	.name = "xe_rtp",</div><div class='add'>+	.init = xe_rtp_test_init,</div><div class='add'>+	.exit = xe_rtp_test_exit,</div><div class='add'>+	.test_cases = xe_rtp_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_rtp_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_rtp kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_test.h b/drivers/gpu/drm/xe/tests/xe_test.h<br/>new file mode 100644<br/>index 000000000000..7a1ae213e750<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_test.h</a></div><div class='hunk'>@@ -0,0 +1,67 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 AND MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TEST_H_</div><div class='add'>+#define _XE_TEST_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include &lt;linux/sched.h&gt;</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Each test that provides a kunit private test structure, place a test id</div><div class='add'>+ * here and point the kunit-&gt;priv to an embedded struct xe_test_priv.</div><div class='add'>+ */</div><div class='add'>+enum xe_test_priv_id {</div><div class='add'>+	XE_TEST_LIVE_DMA_BUF,</div><div class='add'>+	XE_TEST_LIVE_MIGRATE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_test_priv - Base class for test private info</div><div class='add'>+ * @id: enum xe_test_priv_id to identify the subclass.</div><div class='add'>+ */</div><div class='add'>+struct xe_test_priv {</div><div class='add'>+	enum xe_test_priv_id id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE_TEST_DECLARE(x) x</div><div class='add'>+#define XE_TEST_ONLY(x) unlikely(x)</div><div class='add'>+#define XE_TEST_EXPORT</div><div class='add'>+#define xe_cur_kunit() current-&gt;kunit_test</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_cur_kunit_priv - Obtain the struct xe_test_priv pointed to by</div><div class='add'>+ * current-&gt;kunit-&gt;priv if it exists and is embedded in the expected subclass.</div><div class='add'>+ * @id: Id of the expected subclass.</div><div class='add'>+ *</div><div class='add'>+ * Return: NULL if the process is not a kunit test, and NULL if the</div><div class='add'>+ * current kunit-&gt;priv pointer is not pointing to an object of the expected</div><div class='add'>+ * subclass. A pointer to the embedded struct xe_test_priv otherwise.</div><div class='add'>+ */</div><div class='add'>+static inline struct xe_test_priv *</div><div class='add'>+xe_cur_kunit_priv(enum xe_test_priv_id id)</div><div class='add'>+{</div><div class='add'>+	struct xe_test_priv *priv;</div><div class='add'>+</div><div class='add'>+	if (!xe_cur_kunit())</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	priv = xe_cur_kunit()-&gt;priv;</div><div class='add'>+	return priv-&gt;id == id ? priv : NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#else /* if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) */</div><div class='add'>+</div><div class='add'>+#define XE_TEST_DECLARE(x)</div><div class='add'>+#define XE_TEST_ONLY(x) 0</div><div class='add'>+#define XE_TEST_EXPORT static</div><div class='add'>+#define xe_cur_kunit() NULL</div><div class='add'>+#define xe_cur_kunit_priv(_id) NULL</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c<br/>new file mode 100644<br/>index 000000000000..a53c22a19582<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/tests/xe_wa_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/tests/xe_wa_test.c</a></div><div class='hunk'>@@ -0,0 +1,170 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_kunit_helpers.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_pci_test.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+#include "xe_tuning.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+struct platform_test_case {</div><div class='add'>+	const char *name;</div><div class='add'>+	enum xe_platform platform;</div><div class='add'>+	enum xe_subplatform subplatform;</div><div class='add'>+	u32 graphics_verx100;</div><div class='add'>+	u32 media_verx100;</div><div class='add'>+	struct xe_step_info step;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define PLATFORM_CASE(platform__, graphics_step__)				\</div><div class='add'>+	{									\</div><div class='add'>+		.name = #platform__ " (" #graphics_step__ ")",			\</div><div class='add'>+		.platform = XE_ ## platform__,					\</div><div class='add'>+		.subplatform = XE_SUBPLATFORM_NONE,				\</div><div class='add'>+		.step = { .graphics = STEP_ ## graphics_step__ }		\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define SUBPLATFORM_CASE(platform__, subplatform__, graphics_step__)			\</div><div class='add'>+	{										\</div><div class='add'>+		.name = #platform__ "_" #subplatform__ " (" #graphics_step__ ")",	\</div><div class='add'>+		.platform = XE_ ## platform__,						\</div><div class='add'>+		.subplatform = XE_SUBPLATFORM_ ## platform__ ## _ ## subplatform__,	\</div><div class='add'>+		.step = { .graphics = STEP_ ## graphics_step__ }			\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define GMDID_CASE(platform__, graphics_verx100__, graphics_step__,		\</div><div class='add'>+		   media_verx100__, media_step__)				\</div><div class='add'>+	{									\</div><div class='add'>+		.name = #platform__ " (g:" #graphics_step__ ", m:" #media_step__ ")",\</div><div class='add'>+		.platform = XE_ ## platform__,					\</div><div class='add'>+		.subplatform = XE_SUBPLATFORM_NONE,				\</div><div class='add'>+		.graphics_verx100 = graphics_verx100__,				\</div><div class='add'>+		.media_verx100 = media_verx100__,				\</div><div class='add'>+		.step = { .graphics = STEP_ ## graphics_step__,			\</div><div class='add'>+			   .media = STEP_ ## media_step__ }			\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct platform_test_case cases[] = {</div><div class='add'>+	PLATFORM_CASE(TIGERLAKE, B0),</div><div class='add'>+	PLATFORM_CASE(DG1, A0),</div><div class='add'>+	PLATFORM_CASE(DG1, B0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_S, A0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_S, B0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_S, C0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_S, D0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_P, A0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_P, B0),</div><div class='add'>+	PLATFORM_CASE(ALDERLAKE_P, C0),</div><div class='add'>+	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),</div><div class='add'>+	SUBPLATFORM_CASE(ALDERLAKE_P, RPLU, E0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G10, A0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G10, A1),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G10, B0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G10, C0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G11, A0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G11, B0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G11, B1),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G12, A0),</div><div class='add'>+	SUBPLATFORM_CASE(DG2, G12, A1),</div><div class='add'>+	PLATFORM_CASE(PVC, B0),</div><div class='add'>+	PLATFORM_CASE(PVC, B1),</div><div class='add'>+	PLATFORM_CASE(PVC, C0),</div><div class='add'>+	GMDID_CASE(METEORLAKE, 1270, A0, 1300, A0),</div><div class='add'>+	GMDID_CASE(METEORLAKE, 1271, A0, 1300, A0),</div><div class='add'>+	GMDID_CASE(LUNARLAKE, 2004, A0, 2000, A0),</div><div class='add'>+	GMDID_CASE(LUNARLAKE, 2004, B0, 2000, A0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void platform_desc(const struct platform_test_case *t, char *desc)</div><div class='add'>+{</div><div class='add'>+	strscpy(desc, t-&gt;name, KUNIT_PARAM_DESC_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+KUNIT_ARRAY_PARAM(platform, cases, platform_desc);</div><div class='add'>+</div><div class='add'>+static int xe_wa_test_init(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	const struct platform_test_case *param = test-&gt;param_value;</div><div class='add'>+	struct xe_pci_fake_data data = {</div><div class='add'>+		.platform = param-&gt;platform,</div><div class='add'>+		.subplatform = param-&gt;subplatform,</div><div class='add'>+		.graphics_verx100 = param-&gt;graphics_verx100,</div><div class='add'>+		.media_verx100 = param-&gt;media_verx100,</div><div class='add'>+		.graphics_step = param-&gt;step.graphics,</div><div class='add'>+		.media_step = param-&gt;step.media,</div><div class='add'>+	};</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dev = drm_kunit_helper_alloc_device(test);</div><div class='add'>+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dev);</div><div class='add'>+</div><div class='add'>+	xe = drm_kunit_helper_alloc_drm_device(test, dev,</div><div class='add'>+					       struct xe_device,</div><div class='add'>+					       drm, DRIVER_GEM);</div><div class='add'>+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, xe);</div><div class='add'>+</div><div class='add'>+	test-&gt;priv = &amp;data;</div><div class='add'>+	ret = xe_pci_fake_device_init(xe);</div><div class='add'>+	KUNIT_ASSERT_EQ(test, ret, 0);</div><div class='add'>+</div><div class='add'>+	if (!param-&gt;graphics_verx100)</div><div class='add'>+		xe-&gt;info.step = param-&gt;step;</div><div class='add'>+</div><div class='add'>+	/* TODO: init hw engines for engine/LRC WAs */</div><div class='add'>+	xe-&gt;drm.dev = dev;</div><div class='add'>+	test-&gt;priv = xe;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_wa_test_exit(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = test-&gt;priv;</div><div class='add'>+</div><div class='add'>+	drm_kunit_helper_free_device(test, xe-&gt;drm.dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_wa_gt(struct kunit *test)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = test-&gt;priv;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		xe_reg_sr_init(&amp;gt-&gt;reg_sr, "GT", xe);</div><div class='add'>+</div><div class='add'>+		xe_wa_process_gt(gt);</div><div class='add'>+		xe_tuning_process_gt(gt);</div><div class='add'>+</div><div class='add'>+		KUNIT_ASSERT_EQ(test, gt-&gt;reg_sr.errors, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kunit_case xe_wa_tests[] = {</div><div class='add'>+	KUNIT_CASE_PARAM(xe_wa_gt, platform_gen_params),</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct kunit_suite xe_rtp_test_suite = {</div><div class='add'>+	.name = "xe_wa",</div><div class='add'>+	.init = xe_wa_test_init,</div><div class='add'>+	.exit = xe_wa_test_exit,</div><div class='add'>+	.test_cases = xe_wa_tests,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kunit_test_suite(xe_rtp_test_suite);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_DESCRIPTION("xe_wa kunit test");</div><div class='add'>+MODULE_IMPORT_NS(EXPORTED_FOR_KUNIT_TESTING);</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_assert.h b/drivers/gpu/drm/xe/xe_assert.h<br/>new file mode 100644<br/>index 000000000000..34c142e6cfb0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_assert.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_assert.h</a></div><div class='hunk'>@@ -0,0 +1,174 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_ASSERT_H_</div><div class='add'>+#define _XE_ASSERT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/string_helpers.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe ASSERTs</div><div class='add'>+ *</div><div class='add'>+ * While Xe driver aims to be simpler than legacy i915 driver it is still</div><div class='add'>+ * complex enough that some changes introduced while adding new functionality</div><div class='add'>+ * could break the existing code.</div><div class='add'>+ *</div><div class='add'>+ * Adding &amp;drm_WARN or &amp;drm_err to catch unwanted programming usage could lead</div><div class='add'>+ * to undesired increased driver footprint and may impact production driver</div><div class='add'>+ * performance as this additional code will be always present.</div><div class='add'>+ *</div><div class='add'>+ * To allow annotate functions with additional detailed debug checks to assert</div><div class='add'>+ * that all prerequisites are satisfied, without worrying about footprint or</div><div class='add'>+ * performance penalty on production builds where all potential misuses</div><div class='add'>+ * introduced during code integration were already fixed, we introduce family</div><div class='add'>+ * of Xe assert macros that try to follow classic assert() utility:</div><div class='add'>+ *</div><div class='add'>+ *  * xe_assert()</div><div class='add'>+ *  * xe_tile_assert()</div><div class='add'>+ *  * xe_gt_assert()</div><div class='add'>+ *</div><div class='add'>+ * These macros are implemented on top of &amp;drm_WARN, but unlikely to the origin,</div><div class='add'>+ * warning is triggered when provided condition is false. Additionally all above</div><div class='add'>+ * assert macros cannot be used in expressions or as a condition, since</div><div class='add'>+ * underlying code will be compiled out on non-debug builds.</div><div class='add'>+ *</div><div class='add'>+ * Note that these macros are not intended for use to cover known gaps in the</div><div class='add'>+ * implementation; for such cases use regular &amp;drm_WARN or &amp;drm_err and provide</div><div class='add'>+ * valid safe fallback.</div><div class='add'>+ *</div><div class='add'>+ * Also in cases where performance or footprint is not an issue, developers</div><div class='add'>+ * should continue to use the regular &amp;drm_WARN or &amp;drm_err to ensure that bug</div><div class='add'>+ * reports from production builds will contain meaningful diagnostics data.</div><div class='add'>+ *</div><div class='add'>+ * Below code shows how asserts could help in debug to catch unplanned use::</div><div class='add'>+ *</div><div class='add'>+ *	static void one_igfx(struct xe_device *xe)</div><div class='add'>+ *	{</div><div class='add'>+ *		xe_assert(xe, xe-&gt;info.is_dgfx == false);</div><div class='add'>+ *		xe_assert(xe, xe-&gt;info.tile_count == 1);</div><div class='add'>+ *	}</div><div class='add'>+ *</div><div class='add'>+ *	static void two_dgfx(struct xe_device *xe)</div><div class='add'>+ *	{</div><div class='add'>+ *		xe_assert(xe, xe-&gt;info.is_dgfx);</div><div class='add'>+ *		xe_assert(xe, xe-&gt;info.tile_count == 2);</div><div class='add'>+ *	}</div><div class='add'>+ *</div><div class='add'>+ *	void foo(struct xe_device *xe)</div><div class='add'>+ *	{</div><div class='add'>+ *		if (xe-&gt;info.dgfx)</div><div class='add'>+ *			return two_dgfx(xe);</div><div class='add'>+ *		return one_igfx(xe);</div><div class='add'>+ *	}</div><div class='add'>+ *</div><div class='add'>+ *	void bar(struct xe_device *xe)</div><div class='add'>+ *	{</div><div class='add'>+ *		if (drm_WARN_ON(xe-&gt;drm, xe-&gt;info.tile_count &gt; 2))</div><div class='add'>+ *			return;</div><div class='add'>+ *</div><div class='add'>+ *		if (xe-&gt;info.tile_count == 2)</div><div class='add'>+ *			return two_dgfx(xe);</div><div class='add'>+ *		return one_igfx(xe);</div><div class='add'>+ *	}</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)</div><div class='add'>+#define __xe_assert_msg(xe, condition, msg, arg...) ({						\</div><div class='add'>+	(void)drm_WARN(&amp;(xe)-&gt;drm, !(condition), "[" DRM_NAME "] Assertion `%s` failed!\n" msg,	\</div><div class='add'>+		       __stringify(condition), ## arg);						\</div><div class='add'>+})</div><div class='add'>+#else</div><div class='add'>+#define __xe_assert_msg(xe, condition, msg, arg...) ({						\</div><div class='add'>+	typecheck(const struct xe_device *, xe);						\</div><div class='add'>+	BUILD_BUG_ON_INVALID(condition);							\</div><div class='add'>+})</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_assert - warn if condition is false when debugging.</div><div class='add'>+ * @xe: the &amp;struct xe_device pointer to which &amp;condition applies</div><div class='add'>+ * @condition: condition to check</div><div class='add'>+ *</div><div class='add'>+ * xe_assert() uses &amp;drm_WARN to emit a warning and print additional information</div><div class='add'>+ * that could be read from the &amp;xe pointer if provided &amp;condition is false.</div><div class='add'>+ *</div><div class='add'>+ * Contrary to &amp;drm_WARN, xe_assert() is effective only on debug builds</div><div class='add'>+ * (&amp;CONFIG_DRM_XE_DEBUG must be enabled) and cannot be used in expressions</div><div class='add'>+ * or as a condition.</div><div class='add'>+ *</div><div class='add'>+ * See `Xe ASSERTs`_ for general usage guidelines.</div><div class='add'>+ */</div><div class='add'>+#define xe_assert(xe, condition) xe_assert_msg((xe), condition, "")</div><div class='add'>+#define xe_assert_msg(xe, condition, msg, arg...) ({						\</div><div class='add'>+	const struct xe_device *__xe = (xe);							\</div><div class='add'>+	__xe_assert_msg(__xe, condition,							\</div><div class='add'>+			"platform: %d subplatform: %d\n"					\</div><div class='add'>+			"graphics: %s %u.%02u step %s\n"					\</div><div class='add'>+			"media: %s %u.%02u step %s\n"						\</div><div class='add'>+			msg,									\</div><div class='add'>+			__xe-&gt;info.platform, __xe-&gt;info.subplatform,				\</div><div class='add'>+			__xe-&gt;info.graphics_name,						\</div><div class='add'>+			__xe-&gt;info.graphics_verx100 / 100,					\</div><div class='add'>+			__xe-&gt;info.graphics_verx100 % 100,					\</div><div class='add'>+			xe_step_name(__xe-&gt;info.step.graphics),					\</div><div class='add'>+			__xe-&gt;info.media_name,							\</div><div class='add'>+			__xe-&gt;info.media_verx100 / 100,						\</div><div class='add'>+			__xe-&gt;info.media_verx100 % 100,						\</div><div class='add'>+			xe_step_name(__xe-&gt;info.step.media),					\</div><div class='add'>+			## arg);								\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tile_assert - warn if condition is false when debugging.</div><div class='add'>+ * @tile: the &amp;struct xe_tile pointer to which &amp;condition applies</div><div class='add'>+ * @condition: condition to check</div><div class='add'>+ *</div><div class='add'>+ * xe_tile_assert() uses &amp;drm_WARN to emit a warning and print additional</div><div class='add'>+ * information that could be read from the &amp;tile pointer if provided &amp;condition</div><div class='add'>+ * is false.</div><div class='add'>+ *</div><div class='add'>+ * Contrary to &amp;drm_WARN, xe_tile_assert() is effective only on debug builds</div><div class='add'>+ * (&amp;CONFIG_DRM_XE_DEBUG must be enabled) and cannot be used in expressions</div><div class='add'>+ * or as a condition.</div><div class='add'>+ *</div><div class='add'>+ * See `Xe ASSERTs`_ for general usage guidelines.</div><div class='add'>+ */</div><div class='add'>+#define xe_tile_assert(tile, condition) xe_tile_assert_msg((tile), condition, "")</div><div class='add'>+#define xe_tile_assert_msg(tile, condition, msg, arg...) ({					\</div><div class='add'>+	const struct xe_tile *__tile = (tile);							\</div><div class='add'>+	char __buf[10] __maybe_unused;								\</div><div class='add'>+	xe_assert_msg(tile_to_xe(__tile), condition, "tile: %u VRAM %s\n" msg,			\</div><div class='add'>+		      __tile-&gt;id, ({ string_get_size(__tile-&gt;mem.vram.actual_physical_size, 1,	\</div><div class='add'>+				     STRING_UNITS_2, __buf, sizeof(__buf)); __buf; }), ## arg);	\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_assert - warn if condition is false when debugging.</div><div class='add'>+ * @gt: the &amp;struct xe_gt pointer to which &amp;condition applies</div><div class='add'>+ * @condition: condition to check</div><div class='add'>+ *</div><div class='add'>+ * xe_gt_assert() uses &amp;drm_WARN to emit a warning and print additional</div><div class='add'>+ * information that could be safetely read from the &amp;gt pointer if provided</div><div class='add'>+ * &amp;condition is false.</div><div class='add'>+ *</div><div class='add'>+ * Contrary to &amp;drm_WARN, xe_gt_assert() is effective only on debug builds</div><div class='add'>+ * (&amp;CONFIG_DRM_XE_DEBUG must be enabled) and cannot be used in expressions</div><div class='add'>+ * or as a condition.</div><div class='add'>+ *</div><div class='add'>+ * See `Xe ASSERTs`_ for general usage guidelines.</div><div class='add'>+ */</div><div class='add'>+#define xe_gt_assert(gt, condition) xe_gt_assert_msg((gt), condition, "")</div><div class='add'>+#define xe_gt_assert_msg(gt, condition, msg, arg...) ({						\</div><div class='add'>+	const struct xe_gt *__gt = (gt);							\</div><div class='add'>+	xe_tile_assert_msg(gt_to_tile(__gt), condition, "GT: %u type %d\n" msg,			\</div><div class='add'>+			   __gt-&gt;info.id, __gt-&gt;info.type, ## arg);				\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c<br/>new file mode 100644<br/>index 000000000000..7c124475c428<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb.c</a></div><div class='hunk'>@@ -0,0 +1,110 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_sa.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_vm_types.h"</div><div class='add'>+</div><div class='add'>+static int bb_prefetch(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250 &amp;&amp; !xe_gt_is_media_type(gt))</div><div class='add'>+		/*</div><div class='add'>+		 * RCS and CCS require 1K, although other engines would be</div><div class='add'>+		 * okay with 512.</div><div class='add'>+		 */</div><div class='add'>+		return SZ_1K;</div><div class='add'>+	else</div><div class='add'>+		return SZ_512;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_bb *bb = kmalloc(sizeof(*bb), GFP_KERNEL);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!bb)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We need to allocate space for the requested number of dwords,</div><div class='add'>+	 * one additional MI_BATCH_BUFFER_END dword, and additional buffer</div><div class='add'>+	 * space to accomodate the platform-specific hardware prefetch</div><div class='add'>+	 * requirements.</div><div class='add'>+	 */</div><div class='add'>+	bb-&gt;bo = xe_sa_bo_new(!usm ? tile-&gt;mem.kernel_bb_pool : gt-&gt;usm.bb_pool,</div><div class='add'>+			      4 * (dwords + 1) + bb_prefetch(gt));</div><div class='add'>+	if (IS_ERR(bb-&gt;bo)) {</div><div class='add'>+		err = PTR_ERR(bb-&gt;bo);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bb-&gt;cs = xe_sa_bo_cpu_addr(bb-&gt;bo);</div><div class='add'>+	bb-&gt;len = 0;</div><div class='add'>+</div><div class='add'>+	return bb;</div><div class='add'>+err:</div><div class='add'>+	kfree(bb);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_sched_job *</div><div class='add'>+__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr)</div><div class='add'>+{</div><div class='add'>+	u32 size = drm_suballoc_size(bb-&gt;bo);</div><div class='add'>+</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(q-&gt;gt, bb-&gt;len * 4 + bb_prefetch(q-&gt;gt) &lt;= size);</div><div class='add'>+</div><div class='add'>+	xe_sa_bo_flush_write(bb-&gt;bo);</div><div class='add'>+</div><div class='add'>+	return xe_sched_job_create(q, addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,</div><div class='add'>+						struct xe_bb *bb,</div><div class='add'>+						u64 batch_base_ofs,</div><div class='add'>+						u32 second_idx)</div><div class='add'>+{</div><div class='add'>+	u64 addr[2] = {</div><div class='add'>+		batch_base_ofs + drm_suballoc_soffset(bb-&gt;bo),</div><div class='add'>+		batch_base_ofs + drm_suballoc_soffset(bb-&gt;bo) +</div><div class='add'>+		4 * second_idx,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(q-&gt;gt, second_idx &lt;= bb-&gt;len);</div><div class='add'>+	xe_gt_assert(q-&gt;gt, q-&gt;vm-&gt;flags &amp; XE_VM_FLAG_MIGRATION);</div><div class='add'>+</div><div class='add'>+	return __xe_bb_create_job(q, bb, addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,</div><div class='add'>+				      struct xe_bb *bb)</div><div class='add'>+{</div><div class='add'>+	u64 addr = xe_sa_bo_gpu_addr(bb-&gt;bo);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(q-&gt;gt, !(q-&gt;vm &amp;&amp; q-&gt;vm-&gt;flags &amp; XE_VM_FLAG_MIGRATION));</div><div class='add'>+	return __xe_bb_create_job(q, bb, &amp;addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	if (!bb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_sa_bo_free(bb-&gt;bo, fence);</div><div class='add'>+	kfree(bb);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h<br/>new file mode 100644<br/>index 000000000000..fafacd73dcc3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb.h</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BB_H_</div><div class='add'>+#define _XE_BB_H_</div><div class='add'>+</div><div class='add'>+#include "xe_bb_types.h"</div><div class='add'>+</div><div class='add'>+struct dma_fence;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_sched_job;</div><div class='add'>+</div><div class='add'>+struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm);</div><div class='add'>+struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q,</div><div class='add'>+				      struct xe_bb *bb);</div><div class='add'>+struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,</div><div class='add'>+						struct xe_bb *bb, u64 batch_ofs,</div><div class='add'>+						u32 second_idx);</div><div class='add'>+void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bb_types.h b/drivers/gpu/drm/xe/xe_bb_types.h<br/>new file mode 100644<br/>index 000000000000..b7d30308cf90<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bb_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bb_types.h</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BB_TYPES_H_</div><div class='add'>+#define _XE_BB_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_suballoc;</div><div class='add'>+</div><div class='add'>+struct xe_bb {</div><div class='add'>+	struct drm_suballoc *bo;</div><div class='add'>+</div><div class='add'>+	u32 *cs;</div><div class='add'>+	u32 len; /* in dwords */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c<br/>new file mode 100644<br/>index 000000000000..0b0e262e2166<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo.c</a></div><div class='hunk'>@@ -0,0 +1,2269 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-buf.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_gem_ttm_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_device.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_dma_buf.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_preempt_fence.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+static const struct ttm_place sys_placement_flags = {</div><div class='add'>+	.fpfn = 0,</div><div class='add'>+	.lpfn = 0,</div><div class='add'>+	.mem_type = XE_PL_SYSTEM,</div><div class='add'>+	.flags = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct ttm_placement sys_placement = {</div><div class='add'>+	.num_placement = 1,</div><div class='add'>+	.placement = &amp;sys_placement_flags,</div><div class='add'>+	.num_busy_placement = 1,</div><div class='add'>+	.busy_placement = &amp;sys_placement_flags,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ttm_place tt_placement_flags = {</div><div class='add'>+	.fpfn = 0,</div><div class='add'>+	.lpfn = 0,</div><div class='add'>+	.mem_type = XE_PL_TT,</div><div class='add'>+	.flags = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct ttm_placement tt_placement = {</div><div class='add'>+	.num_placement = 1,</div><div class='add'>+	.placement = &amp;tt_placement_flags,</div><div class='add'>+	.num_busy_placement = 1,</div><div class='add'>+	.busy_placement = &amp;sys_placement_flags,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool mem_type_is_vram(u32 mem_type)</div><div class='add'>+{</div><div class='add'>+	return mem_type &gt;= XE_PL_VRAM0 &amp;&amp; mem_type != XE_PL_STOLEN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool resource_is_stolen_vram(struct xe_device *xe, struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	return res-&gt;mem_type == XE_PL_STOLEN &amp;&amp; IS_DGFX(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool resource_is_vram(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	return mem_type_is_vram(res-&gt;mem_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_bo_is_vram(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return resource_is_vram(bo-&gt;ttm.resource) ||</div><div class='add'>+		resource_is_stolen_vram(xe_bo_device(bo), bo-&gt;ttm.resource);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_bo_is_stolen(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return bo-&gt;ttm.resource-&gt;mem_type == XE_PL_STOLEN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_is_stolen_devmem - check if BO is of stolen type accessed via PCI BAR</div><div class='add'>+ * @bo: The BO</div><div class='add'>+ *</div><div class='add'>+ * The stolen memory is accessed through the PCI BAR for both DGFX and some</div><div class='add'>+ * integrated platforms that have a dedicated bit in the PTE for devmem (DM).</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if it's stolen memory accessed via PCI BAR, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_bo_is_stolen_devmem(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return xe_bo_is_stolen(bo) &amp;&amp;</div><div class='add'>+		GRAPHICS_VERx100(xe_bo_device(bo)) &gt;= 1270;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_bo_is_user(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return bo-&gt;flags &amp; XE_BO_CREATE_USER_BIT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_migrate *</div><div class='add'>+mem_type_to_migrate(struct xe_device *xe, u32 mem_type)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, mem_type == XE_PL_STOLEN || mem_type_is_vram(mem_type));</div><div class='add'>+	tile = &amp;xe-&gt;tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];</div><div class='add'>+	return tile-&gt;migrate;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_mem_region *res_to_mem_region(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(res-&gt;bo-&gt;bdev);</div><div class='add'>+	struct ttm_resource_manager *mgr;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, resource_is_vram(res));</div><div class='add'>+	mgr = ttm_manager_type(&amp;xe-&gt;ttm, res-&gt;mem_type);</div><div class='add'>+	return to_xe_ttm_vram_mgr(mgr)-&gt;vram;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void try_add_system(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+			   u32 bo_flags, u32 *c)</div><div class='add'>+{</div><div class='add'>+	if (bo_flags &amp; XE_BO_CREATE_SYSTEM_BIT) {</div><div class='add'>+		xe_assert(xe, *c &lt; ARRAY_SIZE(bo-&gt;placements));</div><div class='add'>+</div><div class='add'>+		bo-&gt;placements[*c] = (struct ttm_place) {</div><div class='add'>+			.mem_type = XE_PL_TT,</div><div class='add'>+		};</div><div class='add'>+		*c += 1;</div><div class='add'>+</div><div class='add'>+		if (bo-&gt;props.preferred_mem_type == XE_BO_PROPS_INVALID)</div><div class='add'>+			bo-&gt;props.preferred_mem_type = XE_PL_TT;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void add_vram(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+		     struct ttm_place *places, u32 bo_flags, u32 mem_type, u32 *c)</div><div class='add'>+{</div><div class='add'>+	struct ttm_place place = { .mem_type = mem_type };</div><div class='add'>+	struct xe_mem_region *vram;</div><div class='add'>+	u64 io_size;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, *c &lt; ARRAY_SIZE(bo-&gt;placements));</div><div class='add'>+</div><div class='add'>+	vram = to_xe_ttm_vram_mgr(ttm_manager_type(&amp;xe-&gt;ttm, mem_type))-&gt;vram;</div><div class='add'>+	xe_assert(xe, vram &amp;&amp; vram-&gt;usable_size);</div><div class='add'>+	io_size = vram-&gt;io_size;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For eviction / restore on suspend / resume objects</div><div class='add'>+	 * pinned in VRAM must be contiguous</div><div class='add'>+	 */</div><div class='add'>+	if (bo_flags &amp; (XE_BO_CREATE_PINNED_BIT |</div><div class='add'>+			XE_BO_CREATE_GGTT_BIT))</div><div class='add'>+		place.flags |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='add'>+</div><div class='add'>+	if (io_size &lt; vram-&gt;usable_size) {</div><div class='add'>+		if (bo_flags &amp; XE_BO_NEEDS_CPU_ACCESS) {</div><div class='add'>+			place.fpfn = 0;</div><div class='add'>+			place.lpfn = io_size &gt;&gt; PAGE_SHIFT;</div><div class='add'>+		} else {</div><div class='add'>+			place.flags |= TTM_PL_FLAG_TOPDOWN;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	places[*c] = place;</div><div class='add'>+	*c += 1;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;props.preferred_mem_type == XE_BO_PROPS_INVALID)</div><div class='add'>+		bo-&gt;props.preferred_mem_type = mem_type;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void try_add_vram(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+			 u32 bo_flags, u32 *c)</div><div class='add'>+{</div><div class='add'>+	if (bo-&gt;props.preferred_gt == XE_GT1) {</div><div class='add'>+		if (bo_flags &amp; XE_BO_CREATE_VRAM1_BIT)</div><div class='add'>+			add_vram(xe, bo, bo-&gt;placements, bo_flags, XE_PL_VRAM1, c);</div><div class='add'>+		if (bo_flags &amp; XE_BO_CREATE_VRAM0_BIT)</div><div class='add'>+			add_vram(xe, bo, bo-&gt;placements, bo_flags, XE_PL_VRAM0, c);</div><div class='add'>+	} else {</div><div class='add'>+		if (bo_flags &amp; XE_BO_CREATE_VRAM0_BIT)</div><div class='add'>+			add_vram(xe, bo, bo-&gt;placements, bo_flags, XE_PL_VRAM0, c);</div><div class='add'>+		if (bo_flags &amp; XE_BO_CREATE_VRAM1_BIT)</div><div class='add'>+			add_vram(xe, bo, bo-&gt;placements, bo_flags, XE_PL_VRAM1, c);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void try_add_stolen(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+			   u32 bo_flags, u32 *c)</div><div class='add'>+{</div><div class='add'>+	if (bo_flags &amp; XE_BO_CREATE_STOLEN_BIT) {</div><div class='add'>+		xe_assert(xe, *c &lt; ARRAY_SIZE(bo-&gt;placements));</div><div class='add'>+</div><div class='add'>+		bo-&gt;placements[*c] = (struct ttm_place) {</div><div class='add'>+			.mem_type = XE_PL_STOLEN,</div><div class='add'>+			.flags = bo_flags &amp; (XE_BO_CREATE_PINNED_BIT |</div><div class='add'>+					     XE_BO_CREATE_GGTT_BIT) ?</div><div class='add'>+				TTM_PL_FLAG_CONTIGUOUS : 0,</div><div class='add'>+		};</div><div class='add'>+		*c += 1;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+				       u32 bo_flags)</div><div class='add'>+{</div><div class='add'>+	u32 c = 0;</div><div class='add'>+</div><div class='add'>+	bo-&gt;props.preferred_mem_type = XE_BO_PROPS_INVALID;</div><div class='add'>+</div><div class='add'>+	/* The order of placements should indicate preferred location */</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;props.preferred_mem_class == DRM_XE_MEM_REGION_CLASS_SYSMEM) {</div><div class='add'>+		try_add_system(xe, bo, bo_flags, &amp;c);</div><div class='add'>+		try_add_vram(xe, bo, bo_flags, &amp;c);</div><div class='add'>+	} else {</div><div class='add'>+		try_add_vram(xe, bo, bo_flags, &amp;c);</div><div class='add'>+		try_add_system(xe, bo, bo_flags, &amp;c);</div><div class='add'>+	}</div><div class='add'>+	try_add_stolen(xe, bo, bo_flags, &amp;c);</div><div class='add'>+</div><div class='add'>+	if (!c)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	bo-&gt;placement = (struct ttm_placement) {</div><div class='add'>+		.num_placement = c,</div><div class='add'>+		.placement = bo-&gt;placements,</div><div class='add'>+		.num_busy_placement = c,</div><div class='add'>+		.busy_placement = bo-&gt;placements,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+			      u32 bo_flags)</div><div class='add'>+{</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+	return __xe_bo_placement_for_flags(xe, bo, bo_flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_evict_flags(struct ttm_buffer_object *tbo,</div><div class='add'>+			   struct ttm_placement *placement)</div><div class='add'>+{</div><div class='add'>+	if (!xe_bo_is_xe_bo(tbo)) {</div><div class='add'>+		/* Don't handle scatter gather BOs */</div><div class='add'>+		if (tbo-&gt;type == ttm_bo_type_sg) {</div><div class='add'>+			placement-&gt;num_placement = 0;</div><div class='add'>+			placement-&gt;num_busy_placement = 0;</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		*placement = sys_placement;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For xe, sg bos that are evicted to system just triggers a</div><div class='add'>+	 * rebind of the sg list upon subsequent validation to XE_PL_TT.</div><div class='add'>+	 */</div><div class='add'>+	switch (tbo-&gt;resource-&gt;mem_type) {</div><div class='add'>+	case XE_PL_VRAM0:</div><div class='add'>+	case XE_PL_VRAM1:</div><div class='add'>+	case XE_PL_STOLEN:</div><div class='add'>+		*placement = tt_placement;</div><div class='add'>+		break;</div><div class='add'>+	case XE_PL_TT:</div><div class='add'>+	default:</div><div class='add'>+		*placement = sys_placement;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_ttm_tt {</div><div class='add'>+	struct ttm_tt ttm;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct sg_table sgt;</div><div class='add'>+	struct sg_table *sg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int xe_tt_map_sg(struct ttm_tt *tt)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_tt *xe_tt = container_of(tt, struct xe_ttm_tt, ttm);</div><div class='add'>+	unsigned long num_pages = tt-&gt;num_pages;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(tt-&gt;page_flags &amp; TTM_TT_FLAG_EXTERNAL);</div><div class='add'>+</div><div class='add'>+	if (xe_tt-&gt;sg)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = sg_alloc_table_from_pages_segment(&amp;xe_tt-&gt;sgt, tt-&gt;pages,</div><div class='add'>+						num_pages, 0,</div><div class='add'>+						(u64)num_pages &lt;&lt; PAGE_SHIFT,</div><div class='add'>+						xe_sg_segment_size(xe_tt-&gt;dev),</div><div class='add'>+						GFP_KERNEL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	xe_tt-&gt;sg = &amp;xe_tt-&gt;sgt;</div><div class='add'>+	ret = dma_map_sgtable(xe_tt-&gt;dev, xe_tt-&gt;sg, DMA_BIDIRECTIONAL,</div><div class='add'>+			      DMA_ATTR_SKIP_CPU_SYNC);</div><div class='add'>+	if (ret) {</div><div class='add'>+		sg_free_table(xe_tt-&gt;sg);</div><div class='add'>+		xe_tt-&gt;sg = NULL;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct sg_table *xe_bo_sg(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct ttm_tt *tt = bo-&gt;ttm.ttm;</div><div class='add'>+	struct xe_ttm_tt *xe_tt = container_of(tt, struct xe_ttm_tt, ttm);</div><div class='add'>+</div><div class='add'>+	return xe_tt-&gt;sg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,</div><div class='add'>+				       u32 page_flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	struct xe_ttm_tt *tt;</div><div class='add'>+	unsigned long extra_pages;</div><div class='add'>+	enum ttm_caching caching;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	tt = kzalloc(sizeof(*tt), GFP_KERNEL);</div><div class='add'>+	if (!tt)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	tt-&gt;dev = xe-&gt;drm.dev;</div><div class='add'>+</div><div class='add'>+	extra_pages = 0;</div><div class='add'>+	if (xe_bo_needs_ccs_pages(bo))</div><div class='add'>+		extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo-&gt;size),</div><div class='add'>+					   PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	switch (bo-&gt;cpu_caching) {</div><div class='add'>+	case DRM_XE_GEM_CPU_CACHING_WC:</div><div class='add'>+		caching = ttm_write_combined;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		caching = ttm_cached;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	WARN_ON((bo-&gt;flags &amp; XE_BO_CREATE_USER_BIT) &amp;&amp; !bo-&gt;cpu_caching);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Display scanout is always non-coherent with the CPU cache.</div><div class='add'>+	 *</div><div class='add'>+	 * For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and</div><div class='add'>+	 * require a CPU:WC mapping.</div><div class='add'>+	 */</div><div class='add'>+	if ((!bo-&gt;cpu_caching &amp;&amp; bo-&gt;flags &amp; XE_BO_SCANOUT_BIT) ||</div><div class='add'>+	    (xe-&gt;info.graphics_verx100 &gt;= 1270 &amp;&amp; bo-&gt;flags &amp; XE_BO_PAGETABLE))</div><div class='add'>+		caching = ttm_write_combined;</div><div class='add'>+</div><div class='add'>+	err = ttm_tt_init(&amp;tt-&gt;ttm, &amp;bo-&gt;ttm, page_flags, caching, extra_pages);</div><div class='add'>+	if (err) {</div><div class='add'>+		kfree(tt);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;tt-&gt;ttm;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_ttm_tt_populate(struct ttm_device *ttm_dev, struct ttm_tt *tt,</div><div class='add'>+			      struct ttm_operation_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * dma-bufs are not populated with pages, and the dma-</div><div class='add'>+	 * addresses are set up when moved to XE_PL_TT.</div><div class='add'>+	 */</div><div class='add'>+	if (tt-&gt;page_flags &amp; TTM_TT_FLAG_EXTERNAL)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = ttm_pool_alloc(&amp;ttm_dev-&gt;pool, tt, ctx);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* A follow up may move this xe_bo_move when BO is moved to XE_PL_TT */</div><div class='add'>+	err = xe_tt_map_sg(tt);</div><div class='add'>+	if (err)</div><div class='add'>+		ttm_pool_free(&amp;ttm_dev-&gt;pool, tt);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_tt_unpopulate(struct ttm_device *ttm_dev, struct ttm_tt *tt)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_tt *xe_tt = container_of(tt, struct xe_ttm_tt, ttm);</div><div class='add'>+</div><div class='add'>+	if (tt-&gt;page_flags &amp; TTM_TT_FLAG_EXTERNAL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (xe_tt-&gt;sg) {</div><div class='add'>+		dma_unmap_sgtable(xe_tt-&gt;dev, xe_tt-&gt;sg,</div><div class='add'>+				  DMA_BIDIRECTIONAL, 0);</div><div class='add'>+		sg_free_table(xe_tt-&gt;sg);</div><div class='add'>+		xe_tt-&gt;sg = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ttm_pool_free(&amp;ttm_dev-&gt;pool, tt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_tt_destroy(struct ttm_device *ttm_dev, struct ttm_tt *tt)</div><div class='add'>+{</div><div class='add'>+	ttm_tt_fini(tt);</div><div class='add'>+	kfree(tt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,</div><div class='add'>+				 struct ttm_resource *mem)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(bdev);</div><div class='add'>+</div><div class='add'>+	switch (mem-&gt;mem_type) {</div><div class='add'>+	case XE_PL_SYSTEM:</div><div class='add'>+	case XE_PL_TT:</div><div class='add'>+		return 0;</div><div class='add'>+	case XE_PL_VRAM0:</div><div class='add'>+	case XE_PL_VRAM1: {</div><div class='add'>+		struct xe_ttm_vram_mgr_resource *vres =</div><div class='add'>+			to_xe_ttm_vram_mgr_resource(mem);</div><div class='add'>+		struct xe_mem_region *vram = res_to_mem_region(mem);</div><div class='add'>+</div><div class='add'>+		if (vres-&gt;used_visible_size &lt; mem-&gt;size)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		mem-&gt;bus.offset = mem-&gt;start &lt;&lt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+		if (vram-&gt;mapping &amp;&amp;</div><div class='add'>+		    mem-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS)</div><div class='add'>+			mem-&gt;bus.addr = (u8 __force *)vram-&gt;mapping +</div><div class='add'>+				mem-&gt;bus.offset;</div><div class='add'>+</div><div class='add'>+		mem-&gt;bus.offset += vram-&gt;io_start;</div><div class='add'>+		mem-&gt;bus.is_iomem = true;</div><div class='add'>+</div><div class='add'>+#if  !defined(CONFIG_X86)</div><div class='add'>+		mem-&gt;bus.caching = ttm_write_combined;</div><div class='add'>+#endif</div><div class='add'>+		return 0;</div><div class='add'>+	} case XE_PL_STOLEN:</div><div class='add'>+		return xe_ttm_stolen_io_mem_reserve(xe, mem);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+				const struct ttm_operation_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct dma_resv_iter cursor;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct drm_gem_object *obj = &amp;bo-&gt;ttm.base;</div><div class='add'>+	struct drm_gpuvm_bo *vm_bo;</div><div class='add'>+	bool idle = false;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dma_resv_assert_held(bo-&gt;ttm.base.resv);</div><div class='add'>+</div><div class='add'>+	if (!list_empty(&amp;bo-&gt;ttm.base.gpuva.list)) {</div><div class='add'>+		dma_resv_iter_begin(&amp;cursor, bo-&gt;ttm.base.resv,</div><div class='add'>+				    DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		dma_resv_for_each_fence_unlocked(&amp;cursor, fence)</div><div class='add'>+			dma_fence_enable_sw_signaling(fence);</div><div class='add'>+		dma_resv_iter_end(&amp;cursor);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_gem_for_each_gpuvm_bo(vm_bo, obj) {</div><div class='add'>+		struct xe_vm *vm = gpuvm_to_vm(vm_bo-&gt;vm);</div><div class='add'>+		struct drm_gpuva *gpuva;</div><div class='add'>+</div><div class='add'>+		if (!xe_vm_in_fault_mode(vm)) {</div><div class='add'>+			drm_gpuvm_bo_evict(vm_bo, true);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!idle) {</div><div class='add'>+			long timeout;</div><div class='add'>+</div><div class='add'>+			if (ctx-&gt;no_wait_gpu &amp;&amp;</div><div class='add'>+			    !dma_resv_test_signaled(bo-&gt;ttm.base.resv,</div><div class='add'>+						    DMA_RESV_USAGE_BOOKKEEP))</div><div class='add'>+				return -EBUSY;</div><div class='add'>+</div><div class='add'>+			timeout = dma_resv_wait_timeout(bo-&gt;ttm.base.resv,</div><div class='add'>+							DMA_RESV_USAGE_BOOKKEEP,</div><div class='add'>+							ctx-&gt;interruptible,</div><div class='add'>+							MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+			if (!timeout)</div><div class='add'>+				return -ETIME;</div><div class='add'>+			if (timeout &lt; 0)</div><div class='add'>+				return timeout;</div><div class='add'>+</div><div class='add'>+			idle = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_gpuvm_bo_for_each_va(gpuva, vm_bo) {</div><div class='add'>+			struct xe_vma *vma = gpuva_to_vma(gpuva);</div><div class='add'>+</div><div class='add'>+			trace_xe_vma_evict(vma);</div><div class='add'>+			ret = xe_vm_invalidate_vma(vma);</div><div class='add'>+			if (XE_WARN_ON(ret))</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The dma-buf map_attachment() / unmap_attachment() is hooked up here.</div><div class='add'>+ * Note that unmapping the attachment is deferred to the next</div><div class='add'>+ * map_attachment time, or to bo destroy (after idling) whichever comes first.</div><div class='add'>+ * This is to avoid syncing before unmap_attachment(), assuming that the</div><div class='add'>+ * caller relies on idling the reservation object before moving the</div><div class='add'>+ * backing store out. Should that assumption not hold, then we will be able</div><div class='add'>+ * to unconditionally call unmap_attachment() when moving out to system.</div><div class='add'>+ */</div><div class='add'>+static int xe_bo_move_dmabuf(struct ttm_buffer_object *ttm_bo,</div><div class='add'>+			     struct ttm_resource *new_res)</div><div class='add'>+{</div><div class='add'>+	struct dma_buf_attachment *attach = ttm_bo-&gt;base.import_attach;</div><div class='add'>+	struct xe_ttm_tt *xe_tt = container_of(ttm_bo-&gt;ttm, struct xe_ttm_tt,</div><div class='add'>+					       ttm);</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(ttm_bo-&gt;bdev);</div><div class='add'>+	struct sg_table *sg;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, attach);</div><div class='add'>+	xe_assert(xe, ttm_bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	if (new_res-&gt;mem_type == XE_PL_SYSTEM)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (ttm_bo-&gt;sg) {</div><div class='add'>+		dma_buf_unmap_attachment(attach, ttm_bo-&gt;sg, DMA_BIDIRECTIONAL);</div><div class='add'>+		ttm_bo-&gt;sg = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sg = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);</div><div class='add'>+	if (IS_ERR(sg))</div><div class='add'>+		return PTR_ERR(sg);</div><div class='add'>+</div><div class='add'>+	ttm_bo-&gt;sg = sg;</div><div class='add'>+	xe_tt-&gt;sg = sg;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	ttm_bo_move_null(ttm_bo, new_res);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_move_notify - Notify subsystems of a pending move</div><div class='add'>+ * @bo: The buffer object</div><div class='add'>+ * @ctx: The struct ttm_operation_ctx controlling locking and waits.</div><div class='add'>+ *</div><div class='add'>+ * This function notifies subsystems of an upcoming buffer move.</div><div class='add'>+ * Upon receiving such a notification, subsystems should schedule</div><div class='add'>+ * halting access to the underlying pages and optionally add a fence</div><div class='add'>+ * to the buffer object's dma_resv object, that signals when access is</div><div class='add'>+ * stopped. The caller will wait on all dma_resv fences before</div><div class='add'>+ * starting the move.</div><div class='add'>+ *</div><div class='add'>+ * A subsystem may commence access to the object after obtaining</div><div class='add'>+ * bindings to the new backing memory under the object lock.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, -EINTR or -ERESTARTSYS if interrupted in fault mode,</div><div class='add'>+ * negative error code on error.</div><div class='add'>+ */</div><div class='add'>+static int xe_bo_move_notify(struct xe_bo *bo,</div><div class='add'>+			     const struct ttm_operation_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct ttm_buffer_object *ttm_bo = &amp;bo-&gt;ttm;</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(ttm_bo-&gt;bdev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If this starts to call into many components, consider</div><div class='add'>+	 * using a notification chain here.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_pinned(bo))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	xe_bo_vunmap(bo);</div><div class='add'>+	ret = xe_bo_trigger_rebind(xe, bo, ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Don't call move_notify() for imported dma-bufs. */</div><div class='add'>+	if (ttm_bo-&gt;base.dma_buf &amp;&amp; !ttm_bo-&gt;base.import_attach)</div><div class='add'>+		dma_buf_move_notify(ttm_bo-&gt;base.dma_buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,</div><div class='add'>+		      struct ttm_operation_ctx *ctx,</div><div class='add'>+		      struct ttm_resource *new_mem,</div><div class='add'>+		      struct ttm_place *hop)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(ttm_bo-&gt;bdev);</div><div class='add'>+	struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);</div><div class='add'>+	struct ttm_resource *old_mem = ttm_bo-&gt;resource;</div><div class='add'>+	u32 old_mem_type = old_mem ? old_mem-&gt;mem_type : XE_PL_SYSTEM;</div><div class='add'>+	struct ttm_tt *ttm = ttm_bo-&gt;ttm;</div><div class='add'>+	struct xe_migrate *migrate = NULL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	bool move_lacks_source;</div><div class='add'>+	bool tt_has_data;</div><div class='add'>+	bool needs_clear;</div><div class='add'>+	bool handle_system_ccs = (!IS_DGFX(xe) &amp;&amp; xe_bo_needs_ccs_pages(bo) &amp;&amp;</div><div class='add'>+				  ttm &amp;&amp; ttm_tt_is_populated(ttm)) ? true : false;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	/* Bo creation path, moving to system or TT. */</div><div class='add'>+	if ((!old_mem &amp;&amp; ttm) &amp;&amp; !handle_system_ccs) {</div><div class='add'>+		ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ttm_bo-&gt;type == ttm_bo_type_sg) {</div><div class='add'>+		ret = xe_bo_move_notify(bo, ctx);</div><div class='add'>+		if (!ret)</div><div class='add'>+			ret = xe_bo_move_dmabuf(ttm_bo, new_mem);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tt_has_data = ttm &amp;&amp; (ttm_tt_is_populated(ttm) ||</div><div class='add'>+			      (ttm-&gt;page_flags &amp; TTM_TT_FLAG_SWAPPED));</div><div class='add'>+</div><div class='add'>+	move_lacks_source = handle_system_ccs ? (!bo-&gt;ccs_cleared)  :</div><div class='add'>+						(!mem_type_is_vram(old_mem_type) &amp;&amp; !tt_has_data);</div><div class='add'>+</div><div class='add'>+	needs_clear = (ttm &amp;&amp; ttm-&gt;page_flags &amp; TTM_TT_FLAG_ZERO_ALLOC) ||</div><div class='add'>+		(!ttm &amp;&amp; ttm_bo-&gt;type == ttm_bo_type_device);</div><div class='add'>+</div><div class='add'>+	if ((move_lacks_source &amp;&amp; !needs_clear)) {</div><div class='add'>+		ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (old_mem_type == XE_PL_SYSTEM &amp;&amp; new_mem-&gt;mem_type == XE_PL_TT &amp;&amp; !handle_system_ccs) {</div><div class='add'>+		ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Failed multi-hop where the old_mem is still marked as</div><div class='add'>+	 * TTM_PL_FLAG_TEMPORARY, should just be a dummy move.</div><div class='add'>+	 */</div><div class='add'>+	if (old_mem_type == XE_PL_TT &amp;&amp;</div><div class='add'>+	    new_mem-&gt;mem_type == XE_PL_TT) {</div><div class='add'>+		ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!move_lacks_source &amp;&amp; !xe_bo_is_pinned(bo)) {</div><div class='add'>+		ret = xe_bo_move_notify(bo, ctx);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (old_mem_type == XE_PL_TT &amp;&amp;</div><div class='add'>+	    new_mem-&gt;mem_type == XE_PL_SYSTEM) {</div><div class='add'>+		long timeout = dma_resv_wait_timeout(ttm_bo-&gt;base.resv,</div><div class='add'>+						     DMA_RESV_USAGE_BOOKKEEP,</div><div class='add'>+						     true,</div><div class='add'>+						     MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+		if (timeout &lt; 0) {</div><div class='add'>+			ret = timeout;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!handle_system_ccs) {</div><div class='add'>+			ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!move_lacks_source &amp;&amp;</div><div class='add'>+	    ((old_mem_type == XE_PL_SYSTEM &amp;&amp; resource_is_vram(new_mem)) ||</div><div class='add'>+	     (mem_type_is_vram(old_mem_type) &amp;&amp;</div><div class='add'>+	      new_mem-&gt;mem_type == XE_PL_SYSTEM))) {</div><div class='add'>+		hop-&gt;fpfn = 0;</div><div class='add'>+		hop-&gt;lpfn = 0;</div><div class='add'>+		hop-&gt;mem_type = XE_PL_TT;</div><div class='add'>+		hop-&gt;flags = TTM_PL_FLAG_TEMPORARY;</div><div class='add'>+		ret = -EMULTIHOP;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;tile)</div><div class='add'>+		migrate = bo-&gt;tile-&gt;migrate;</div><div class='add'>+	else if (resource_is_vram(new_mem))</div><div class='add'>+		migrate = mem_type_to_migrate(xe, new_mem-&gt;mem_type);</div><div class='add'>+	else if (mem_type_is_vram(old_mem_type))</div><div class='add'>+		migrate = mem_type_to_migrate(xe, old_mem_type);</div><div class='add'>+	else</div><div class='add'>+		migrate = xe-&gt;tiles[0].migrate;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, migrate);</div><div class='add'>+</div><div class='add'>+	trace_xe_bo_move(bo);</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_pinned(bo) &amp;&amp; !xe_bo_is_user(bo)) {</div><div class='add'>+		/*</div><div class='add'>+		 * Kernel memory that is pinned should only be moved on suspend</div><div class='add'>+		 * / resume, some of the pinned memory is required for the</div><div class='add'>+		 * device to resume / use the GPU to move other evicted memory</div><div class='add'>+		 * (user memory) around. This likely could be optimized a bit</div><div class='add'>+		 * futher where we find the minimum set of pinned memory</div><div class='add'>+		 * required for resume but for simplity doing a memcpy for all</div><div class='add'>+		 * pinned memory.</div><div class='add'>+		 */</div><div class='add'>+		ret = xe_bo_vmap(bo);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			ret = ttm_bo_move_memcpy(ttm_bo, ctx, new_mem);</div><div class='add'>+</div><div class='add'>+			/* Create a new VMAP once kernel BO back in VRAM */</div><div class='add'>+			if (!ret &amp;&amp; resource_is_vram(new_mem)) {</div><div class='add'>+				struct xe_mem_region *vram = res_to_mem_region(new_mem);</div><div class='add'>+				void __iomem *new_addr = vram-&gt;mapping +</div><div class='add'>+					(new_mem-&gt;start &lt;&lt; PAGE_SHIFT);</div><div class='add'>+</div><div class='add'>+				if (XE_WARN_ON(new_mem-&gt;start == XE_BO_INVALID_OFFSET)) {</div><div class='add'>+					ret = -EINVAL;</div><div class='add'>+					xe_device_mem_access_put(xe);</div><div class='add'>+					goto out;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				xe_assert(xe, new_mem-&gt;start ==</div><div class='add'>+					  bo-&gt;placements-&gt;fpfn);</div><div class='add'>+</div><div class='add'>+				iosys_map_set_vaddr_iomem(&amp;bo-&gt;vmap, new_addr);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (move_lacks_source)</div><div class='add'>+			fence = xe_migrate_clear(migrate, bo, new_mem);</div><div class='add'>+		else</div><div class='add'>+			fence = xe_migrate_copy(migrate, bo, bo, old_mem,</div><div class='add'>+						new_mem, handle_system_ccs);</div><div class='add'>+		if (IS_ERR(fence)) {</div><div class='add'>+			ret = PTR_ERR(fence);</div><div class='add'>+			xe_device_mem_access_put(xe);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+		if (!move_lacks_source) {</div><div class='add'>+			ret = ttm_bo_move_accel_cleanup(ttm_bo, fence, evict,</div><div class='add'>+							true, new_mem);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dma_fence_wait(fence, false);</div><div class='add'>+				ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+				ret = 0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/*</div><div class='add'>+			 * ttm_bo_move_accel_cleanup() may blow up if</div><div class='add'>+			 * bo-&gt;resource == NULL, so just attach the</div><div class='add'>+			 * fence and set the new resource.</div><div class='add'>+			 */</div><div class='add'>+			dma_resv_add_fence(ttm_bo-&gt;base.resv, fence,</div><div class='add'>+					   DMA_RESV_USAGE_KERNEL);</div><div class='add'>+			ttm_bo_move_null(ttm_bo, new_mem);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_evict_pinned() - Evict a pinned VRAM object to system memory</div><div class='add'>+ * @bo: The buffer object to move.</div><div class='add'>+ *</div><div class='add'>+ * On successful completion, the object memory will be moved to sytem memory.</div><div class='add'>+ * This function blocks until the object has been fully moved.</div><div class='add'>+ *</div><div class='add'>+ * This is needed to for special handling of pinned VRAM object during</div><div class='add'>+ * suspend-resume.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success. Negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_evict_pinned(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct ttm_place place = {</div><div class='add'>+		.mem_type = XE_PL_TT,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_placement placement = {</div><div class='add'>+		.placement = &amp;place,</div><div class='add'>+		.num_placement = 1,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = false,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_resource *new_mem;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!bo-&gt;ttm.resource))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!xe_bo_is_pinned(bo)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!xe_bo_is_vram(bo)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = ttm_bo_mem_space(&amp;bo-&gt;ttm, &amp;placement, &amp;new_mem, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!bo-&gt;ttm.ttm) {</div><div class='add'>+		bo-&gt;ttm.ttm = xe_ttm_tt_create(&amp;bo-&gt;ttm, 0);</div><div class='add'>+		if (!bo-&gt;ttm.ttm) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto err_res_free;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = ttm_tt_populate(bo-&gt;ttm.bdev, bo-&gt;ttm.ttm, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	ret = dma_resv_reserve_fences(bo-&gt;ttm.base.resv, 1);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_move(&amp;bo-&gt;ttm, false, &amp;ctx, new_mem, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	dma_resv_wait_timeout(bo-&gt;ttm.base.resv, DMA_RESV_USAGE_KERNEL,</div><div class='add'>+			      false, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_res_free:</div><div class='add'>+	ttm_resource_free(&amp;bo-&gt;ttm, &amp;new_mem);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_restore_pinned() - Restore a pinned VRAM object</div><div class='add'>+ * @bo: The buffer object to move.</div><div class='add'>+ *</div><div class='add'>+ * On successful completion, the object memory will be moved back to VRAM.</div><div class='add'>+ * This function blocks until the object has been fully moved.</div><div class='add'>+ *</div><div class='add'>+ * This is needed to for special handling of pinned VRAM object during</div><div class='add'>+ * suspend-resume.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success. Negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_restore_pinned(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = false,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_resource *new_mem;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!bo-&gt;ttm.resource))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!xe_bo_is_pinned(bo)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(xe_bo_is_vram(bo) || !bo-&gt;ttm.ttm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = ttm_bo_mem_space(&amp;bo-&gt;ttm, &amp;bo-&gt;placement, &amp;new_mem, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = ttm_tt_populate(bo-&gt;ttm.bdev, bo-&gt;ttm.ttm, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	ret = dma_resv_reserve_fences(bo-&gt;ttm.base.resv, 1);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_move(&amp;bo-&gt;ttm, false, &amp;ctx, new_mem, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_res_free;</div><div class='add'>+</div><div class='add'>+	dma_resv_wait_timeout(bo-&gt;ttm.base.resv, DMA_RESV_USAGE_KERNEL,</div><div class='add'>+			      false, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_res_free:</div><div class='add'>+	ttm_resource_free(&amp;bo-&gt;ttm, &amp;new_mem);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,</div><div class='add'>+				       unsigned long page_offset)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);</div><div class='add'>+	struct xe_res_cursor cursor;</div><div class='add'>+	struct xe_mem_region *vram;</div><div class='add'>+</div><div class='add'>+	if (ttm_bo-&gt;resource-&gt;mem_type == XE_PL_STOLEN)</div><div class='add'>+		return xe_ttm_stolen_io_offset(bo, page_offset &lt;&lt; PAGE_SHIFT) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	vram = res_to_mem_region(ttm_bo-&gt;resource);</div><div class='add'>+	xe_res_first(ttm_bo-&gt;resource, (u64)page_offset &lt;&lt; PAGE_SHIFT, 0, &amp;cursor);</div><div class='add'>+	return (vram-&gt;io_start + cursor.start) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_bo_vunmap(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * TODO: Move this function to TTM so we don't rely on how TTM does its</div><div class='add'>+ * locking, thereby abusing TTM internals.</div><div class='add'>+ */</div><div class='add'>+static bool xe_ttm_bo_lock_in_destructor(struct ttm_buffer_object *ttm_bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(ttm_bo-&gt;bdev);</div><div class='add'>+	bool locked;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !kref_read(&amp;ttm_bo-&gt;kref));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We can typically only race with TTM trylocking under the</div><div class='add'>+	 * lru_lock, which will immediately be unlocked again since</div><div class='add'>+	 * the ttm_bo refcount is zero at this point. So trylocking *should*</div><div class='add'>+	 * always succeed here, as long as we hold the lru lock.</div><div class='add'>+	 */</div><div class='add'>+	spin_lock(&amp;ttm_bo-&gt;bdev-&gt;lru_lock);</div><div class='add'>+	locked = dma_resv_trylock(ttm_bo-&gt;base.resv);</div><div class='add'>+	spin_unlock(&amp;ttm_bo-&gt;bdev-&gt;lru_lock);</div><div class='add'>+	xe_assert(xe, locked);</div><div class='add'>+</div><div class='add'>+	return locked;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_bo_release_notify(struct ttm_buffer_object *ttm_bo)</div><div class='add'>+{</div><div class='add'>+	struct dma_resv_iter cursor;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct dma_fence *replacement = NULL;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_xe_bo(ttm_bo))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	bo = ttm_to_xe_bo(ttm_bo);</div><div class='add'>+	xe_assert(xe_bo_device(bo), !(bo-&gt;created &amp;&amp; kref_read(&amp;ttm_bo-&gt;base.refcount)));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Corner case where TTM fails to allocate memory and this BOs resv</div><div class='add'>+	 * still points the VMs resv</div><div class='add'>+	 */</div><div class='add'>+	if (ttm_bo-&gt;base.resv != &amp;ttm_bo-&gt;base._resv)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!xe_ttm_bo_lock_in_destructor(ttm_bo))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Scrub the preempt fences if any. The unbind fence is already</div><div class='add'>+	 * attached to the resv.</div><div class='add'>+	 * TODO: Don't do this for external bos once we scrub them after</div><div class='add'>+	 * unbind.</div><div class='add'>+	 */</div><div class='add'>+	dma_resv_for_each_fence(&amp;cursor, ttm_bo-&gt;base.resv,</div><div class='add'>+				DMA_RESV_USAGE_BOOKKEEP, fence) {</div><div class='add'>+		if (xe_fence_is_xe_preempt(fence) &amp;&amp;</div><div class='add'>+		    !dma_fence_is_signaled(fence)) {</div><div class='add'>+			if (!replacement)</div><div class='add'>+				replacement = dma_fence_get_stub();</div><div class='add'>+</div><div class='add'>+			dma_resv_replace_fences(ttm_bo-&gt;base.resv,</div><div class='add'>+						fence-&gt;context,</div><div class='add'>+						replacement,</div><div class='add'>+						DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(replacement);</div><div class='add'>+</div><div class='add'>+	dma_resv_unlock(ttm_bo-&gt;base.resv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_bo_delete_mem_notify(struct ttm_buffer_object *ttm_bo)</div><div class='add'>+{</div><div class='add'>+	if (!xe_bo_is_xe_bo(ttm_bo))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Object is idle and about to be destroyed. Release the</div><div class='add'>+	 * dma-buf attachment.</div><div class='add'>+	 */</div><div class='add'>+	if (ttm_bo-&gt;type == ttm_bo_type_sg &amp;&amp; ttm_bo-&gt;sg) {</div><div class='add'>+		struct xe_ttm_tt *xe_tt = container_of(ttm_bo-&gt;ttm,</div><div class='add'>+						       struct xe_ttm_tt, ttm);</div><div class='add'>+</div><div class='add'>+		dma_buf_unmap_attachment(ttm_bo-&gt;base.import_attach, ttm_bo-&gt;sg,</div><div class='add'>+					 DMA_BIDIRECTIONAL);</div><div class='add'>+		ttm_bo-&gt;sg = NULL;</div><div class='add'>+		xe_tt-&gt;sg = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct ttm_device_funcs xe_ttm_funcs = {</div><div class='add'>+	.ttm_tt_create = xe_ttm_tt_create,</div><div class='add'>+	.ttm_tt_populate = xe_ttm_tt_populate,</div><div class='add'>+	.ttm_tt_unpopulate = xe_ttm_tt_unpopulate,</div><div class='add'>+	.ttm_tt_destroy = xe_ttm_tt_destroy,</div><div class='add'>+	.evict_flags = xe_evict_flags,</div><div class='add'>+	.move = xe_bo_move,</div><div class='add'>+	.io_mem_reserve = xe_ttm_io_mem_reserve,</div><div class='add'>+	.io_mem_pfn = xe_ttm_io_mem_pfn,</div><div class='add'>+	.release_notify = xe_ttm_bo_release_notify,</div><div class='add'>+	.eviction_valuable = ttm_bo_eviction_valuable,</div><div class='add'>+	.delete_mem_notify = xe_ttm_bo_delete_mem_notify,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe_ttm_bo_destroy(struct ttm_buffer_object *ttm_bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(ttm_bo-&gt;bdev);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.base.import_attach)</div><div class='add'>+		drm_prime_gem_destroy(&amp;bo-&gt;ttm.base, NULL);</div><div class='add'>+	drm_gem_object_release(&amp;bo-&gt;ttm.base);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, list_empty(&amp;ttm_bo-&gt;base.gpuva.list));</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ggtt_node.size)</div><div class='add'>+		xe_ggtt_remove_bo(bo-&gt;tile-&gt;mem.ggtt, bo);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	if (bo-&gt;client)</div><div class='add'>+		xe_drm_client_remove_bo(bo);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;vm &amp;&amp; xe_bo_is_user(bo))</div><div class='add'>+		xe_vm_put(bo-&gt;vm);</div><div class='add'>+</div><div class='add'>+	kfree(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_gem_object_free(struct drm_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	/* Our BO reference counting scheme works as follows:</div><div class='add'>+	 *</div><div class='add'>+	 * The gem object kref is typically used throughout the driver,</div><div class='add'>+	 * and the gem object holds a ttm_buffer_object refcount, so</div><div class='add'>+	 * that when the last gem object reference is put, which is when</div><div class='add'>+	 * we end up in this function, we put also that ttm_buffer_object</div><div class='add'>+	 * refcount. Anything using gem interfaces is then no longer</div><div class='add'>+	 * allowed to access the object in a way that requires a gem</div><div class='add'>+	 * refcount, including locking the object.</div><div class='add'>+	 *</div><div class='add'>+	 * driver ttm callbacks is allowed to use the ttm_buffer_object</div><div class='add'>+	 * refcount directly if needed.</div><div class='add'>+	 */</div><div class='add'>+	__xe_bo_vunmap(gem_to_xe_bo(obj));</div><div class='add'>+	ttm_bo_put(container_of(obj, struct ttm_buffer_object, base));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_gem_object_close(struct drm_gem_object *obj,</div><div class='add'>+				struct drm_file *file_priv)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;vm &amp;&amp; !xe_vm_in_fault_mode(bo-&gt;vm)) {</div><div class='add'>+		xe_assert(xe_bo_device(bo), xe_bo_is_user(bo));</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		ttm_bo_set_bulk_move(&amp;bo-&gt;ttm, NULL);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool should_migrate_to_system(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+</div><div class='add'>+	return xe_device_in_fault_mode(xe) &amp;&amp; bo-&gt;props.cpu_atomic;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static vm_fault_t xe_gem_fault(struct vm_fault *vmf)</div><div class='add'>+{</div><div class='add'>+	struct ttm_buffer_object *tbo = vmf-&gt;vma-&gt;vm_private_data;</div><div class='add'>+	struct drm_device *ddev = tbo-&gt;base.dev;</div><div class='add'>+	vm_fault_t ret;</div><div class='add'>+	int idx, r = 0;</div><div class='add'>+</div><div class='add'>+	ret = ttm_bo_vm_reserve(tbo, vmf);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (drm_dev_enter(ddev, &amp;idx)) {</div><div class='add'>+		struct xe_bo *bo = ttm_to_xe_bo(tbo);</div><div class='add'>+</div><div class='add'>+		trace_xe_bo_cpu_fault(bo);</div><div class='add'>+</div><div class='add'>+		if (should_migrate_to_system(bo)) {</div><div class='add'>+			r = xe_bo_migrate(bo, XE_PL_TT);</div><div class='add'>+			if (r == -EBUSY || r == -ERESTARTSYS || r == -EINTR)</div><div class='add'>+				ret = VM_FAULT_NOPAGE;</div><div class='add'>+			else if (r)</div><div class='add'>+				ret = VM_FAULT_SIGBUS;</div><div class='add'>+		}</div><div class='add'>+		if (!ret)</div><div class='add'>+			ret = ttm_bo_vm_fault_reserved(vmf,</div><div class='add'>+						       vmf-&gt;vma-&gt;vm_page_prot,</div><div class='add'>+						       TTM_BO_VM_NUM_PREFAULT);</div><div class='add'>+		drm_dev_exit(idx);</div><div class='add'>+	} else {</div><div class='add'>+		ret = ttm_bo_vm_dummy_page(vmf, vmf-&gt;vma-&gt;vm_page_prot);</div><div class='add'>+	}</div><div class='add'>+	if (ret == VM_FAULT_RETRY &amp;&amp; !(vmf-&gt;flags &amp; FAULT_FLAG_RETRY_NOWAIT))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dma_resv_unlock(tbo-&gt;base.resv);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vm_operations_struct xe_gem_vm_ops = {</div><div class='add'>+	.fault = xe_gem_fault,</div><div class='add'>+	.open = ttm_bo_vm_open,</div><div class='add'>+	.close = ttm_bo_vm_close,</div><div class='add'>+	.access = ttm_bo_vm_access</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct drm_gem_object_funcs xe_gem_object_funcs = {</div><div class='add'>+	.free = xe_gem_object_free,</div><div class='add'>+	.close = xe_gem_object_close,</div><div class='add'>+	.mmap = drm_gem_ttm_mmap,</div><div class='add'>+	.export = xe_gem_prime_export,</div><div class='add'>+	.vm_ops = &amp;xe_gem_vm_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_alloc - Allocate storage for a struct xe_bo</div><div class='add'>+ *</div><div class='add'>+ * This funcition is intended to allocate storage to be used for input</div><div class='add'>+ * to __xe_bo_create_locked(), in the case a pointer to the bo to be</div><div class='add'>+ * created is needed before the call to __xe_bo_create_locked().</div><div class='add'>+ * If __xe_bo_create_locked ends up never to be called, then the</div><div class='add'>+ * storage allocated with this function needs to be freed using</div><div class='add'>+ * xe_bo_free().</div><div class='add'>+ *</div><div class='add'>+ * Return: A pointer to an uninitialized struct xe_bo on success,</div><div class='add'>+ * ERR_PTR(-ENOMEM) on error.</div><div class='add'>+ */</div><div class='add'>+struct xe_bo *xe_bo_alloc(void)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = kzalloc(sizeof(*bo), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!bo)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_free - Free storage allocated using xe_bo_alloc()</div><div class='add'>+ * @bo: The buffer object storage.</div><div class='add'>+ *</div><div class='add'>+ * Refer to xe_bo_alloc() documentation for valid use-cases.</div><div class='add'>+ */</div><div class='add'>+void xe_bo_free(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	kfree(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *___xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+				     struct xe_tile *tile, struct dma_resv *resv,</div><div class='add'>+				     struct ttm_lru_bulk_move *bulk, size_t size,</div><div class='add'>+				     u16 cpu_caching, enum ttm_bo_type type,</div><div class='add'>+				     u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = true,</div><div class='add'>+		.no_wait_gpu = false,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_placement *placement;</div><div class='add'>+	uint32_t alignment;</div><div class='add'>+	size_t aligned_size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* Only kernel objects should set GT */</div><div class='add'>+	xe_assert(xe, !tile || type == ttm_bo_type_kernel);</div><div class='add'>+</div><div class='add'>+	if (XE_WARN_ON(!size)) {</div><div class='add'>+		xe_bo_free(bo);</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (flags &amp; (XE_BO_CREATE_VRAM_MASK | XE_BO_CREATE_STOLEN_BIT) &amp;&amp;</div><div class='add'>+	    !(flags &amp; XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT) &amp;&amp;</div><div class='add'>+	    xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K) {</div><div class='add'>+		aligned_size = ALIGN(size, SZ_64K);</div><div class='add'>+		if (type != ttm_bo_type_device)</div><div class='add'>+			size = ALIGN(size, SZ_64K);</div><div class='add'>+		flags |= XE_BO_INTERNAL_64K;</div><div class='add'>+		alignment = SZ_64K &gt;&gt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		aligned_size = ALIGN(size, SZ_4K);</div><div class='add'>+		flags &amp;= ~XE_BO_INTERNAL_64K;</div><div class='add'>+		alignment = SZ_4K &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (type == ttm_bo_type_device &amp;&amp; aligned_size != size)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+	if (!bo) {</div><div class='add'>+		bo = xe_bo_alloc();</div><div class='add'>+		if (IS_ERR(bo))</div><div class='add'>+			return bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo-&gt;ccs_cleared = false;</div><div class='add'>+	bo-&gt;tile = tile;</div><div class='add'>+	bo-&gt;size = size;</div><div class='add'>+	bo-&gt;flags = flags;</div><div class='add'>+	bo-&gt;cpu_caching = cpu_caching;</div><div class='add'>+	bo-&gt;ttm.base.funcs = &amp;xe_gem_object_funcs;</div><div class='add'>+	bo-&gt;props.preferred_mem_class = XE_BO_PROPS_INVALID;</div><div class='add'>+	bo-&gt;props.preferred_gt = XE_BO_PROPS_INVALID;</div><div class='add'>+	bo-&gt;props.preferred_mem_type = XE_BO_PROPS_INVALID;</div><div class='add'>+	bo-&gt;ttm.priority = XE_BO_PRIORITY_NORMAL;</div><div class='add'>+	INIT_LIST_HEAD(&amp;bo-&gt;pinned_link);</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	INIT_LIST_HEAD(&amp;bo-&gt;client_link);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	drm_gem_private_object_init(&amp;xe-&gt;drm, &amp;bo-&gt;ttm.base, size);</div><div class='add'>+</div><div class='add'>+	if (resv) {</div><div class='add'>+		ctx.allow_res_evict = !(flags &amp; XE_BO_CREATE_NO_RESV_EVICT);</div><div class='add'>+		ctx.resv = resv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!(flags &amp; XE_BO_FIXED_PLACEMENT_BIT)) {</div><div class='add'>+		err = __xe_bo_placement_for_flags(xe, bo, bo-&gt;flags);</div><div class='add'>+		if (WARN_ON(err)) {</div><div class='add'>+			xe_ttm_bo_destroy(&amp;bo-&gt;ttm);</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Defer populating type_sg bos */</div><div class='add'>+	placement = (type == ttm_bo_type_sg ||</div><div class='add'>+		     bo-&gt;flags &amp; XE_BO_DEFER_BACKING) ? &amp;sys_placement :</div><div class='add'>+		&amp;bo-&gt;placement;</div><div class='add'>+	err = ttm_bo_init_reserved(&amp;xe-&gt;ttm, &amp;bo-&gt;ttm, type,</div><div class='add'>+				   placement, alignment,</div><div class='add'>+				   &amp;ctx, NULL, resv, xe_ttm_bo_destroy);</div><div class='add'>+	if (err)</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The VRAM pages underneath are potentially still being accessed by the</div><div class='add'>+	 * GPU, as per async GPU clearing and async evictions. However TTM makes</div><div class='add'>+	 * sure to add any corresponding move/clear fences into the objects</div><div class='add'>+	 * dma-resv using the DMA_RESV_USAGE_KERNEL slot.</div><div class='add'>+	 *</div><div class='add'>+	 * For KMD internal buffers we don't care about GPU clearing, however we</div><div class='add'>+	 * still need to handle async evictions, where the VRAM is still being</div><div class='add'>+	 * accessed by the GPU. Most internal callers are not expecting this,</div><div class='add'>+	 * since they are missing the required synchronisation before accessing</div><div class='add'>+	 * the memory. To keep things simple just sync wait any kernel fences</div><div class='add'>+	 * here, if the buffer is designated KMD internal.</div><div class='add'>+	 *</div><div class='add'>+	 * For normal userspace objects we should already have the required</div><div class='add'>+	 * pipelining or sync waiting elsewhere, since we already have to deal</div><div class='add'>+	 * with things like async GPU clearing.</div><div class='add'>+	 */</div><div class='add'>+	if (type == ttm_bo_type_kernel) {</div><div class='add'>+		long timeout = dma_resv_wait_timeout(bo-&gt;ttm.base.resv,</div><div class='add'>+						     DMA_RESV_USAGE_KERNEL,</div><div class='add'>+						     ctx.interruptible,</div><div class='add'>+						     MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+</div><div class='add'>+		if (timeout &lt; 0) {</div><div class='add'>+			if (!resv)</div><div class='add'>+				dma_resv_unlock(bo-&gt;ttm.base.resv);</div><div class='add'>+			xe_bo_put(bo);</div><div class='add'>+			return ERR_PTR(timeout);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo-&gt;created = true;</div><div class='add'>+	if (bulk)</div><div class='add'>+		ttm_bo_set_bulk_move(&amp;bo-&gt;ttm, bulk);</div><div class='add'>+	else</div><div class='add'>+		ttm_bo_move_to_lru_tail_unlocked(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_bo_fixed_placement(struct xe_device *xe,</div><div class='add'>+				   struct xe_bo *bo,</div><div class='add'>+				   u32 flags,</div><div class='add'>+				   u64 start, u64 end, u64 size)</div><div class='add'>+{</div><div class='add'>+	struct ttm_place *place = bo-&gt;placements;</div><div class='add'>+</div><div class='add'>+	if (flags &amp; (XE_BO_CREATE_USER_BIT|XE_BO_CREATE_SYSTEM_BIT))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	place-&gt;flags = TTM_PL_FLAG_CONTIGUOUS;</div><div class='add'>+	place-&gt;fpfn = start &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	place-&gt;lpfn = end &gt;&gt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	switch (flags &amp; (XE_BO_CREATE_STOLEN_BIT | XE_BO_CREATE_VRAM_MASK)) {</div><div class='add'>+	case XE_BO_CREATE_VRAM0_BIT:</div><div class='add'>+		place-&gt;mem_type = XE_PL_VRAM0;</div><div class='add'>+		break;</div><div class='add'>+	case XE_BO_CREATE_VRAM1_BIT:</div><div class='add'>+		place-&gt;mem_type = XE_PL_VRAM1;</div><div class='add'>+		break;</div><div class='add'>+	case XE_BO_CREATE_STOLEN_BIT:</div><div class='add'>+		place-&gt;mem_type = XE_PL_STOLEN;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		/* 0 or multiple of the above set */</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo-&gt;placement = (struct ttm_placement) {</div><div class='add'>+		.num_placement = 1,</div><div class='add'>+		.placement = place,</div><div class='add'>+		.num_busy_placement = 1,</div><div class='add'>+		.busy_placement = place,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_bo *</div><div class='add'>+__xe_bo_create_locked(struct xe_device *xe,</div><div class='add'>+		      struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+		      size_t size, u64 start, u64 end,</div><div class='add'>+		      u16 cpu_caching, enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = NULL;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	if (start || end != ~0ULL) {</div><div class='add'>+		bo = xe_bo_alloc();</div><div class='add'>+		if (IS_ERR(bo))</div><div class='add'>+			return bo;</div><div class='add'>+</div><div class='add'>+		flags |= XE_BO_FIXED_PLACEMENT_BIT;</div><div class='add'>+		err = __xe_bo_fixed_placement(xe, bo, flags, start, end, size);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_bo_free(bo);</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo = ___xe_bo_create_locked(xe, bo, tile, vm ? xe_vm_resv(vm) : NULL,</div><div class='add'>+				    vm &amp;&amp; !xe_vm_in_fault_mode(vm) &amp;&amp;</div><div class='add'>+				    flags &amp; XE_BO_CREATE_USER_BIT ?</div><div class='add'>+				    &amp;vm-&gt;lru_bulk_move : NULL, size,</div><div class='add'>+				    cpu_caching, type, flags);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return bo;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note that instead of taking a reference no the drm_gpuvm_resv_bo(),</div><div class='add'>+	 * to ensure the shared resv doesn't disappear under the bo, the bo</div><div class='add'>+	 * will keep a reference to the vm, and avoid circular references</div><div class='add'>+	 * by having all the vm's bo refereferences released at vm close</div><div class='add'>+	 * time.</div><div class='add'>+	 */</div><div class='add'>+	if (vm &amp;&amp; xe_bo_is_user(bo))</div><div class='add'>+		xe_vm_get(vm);</div><div class='add'>+	bo-&gt;vm = vm;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;flags &amp; XE_BO_CREATE_GGTT_BIT) {</div><div class='add'>+		if (!tile &amp;&amp; flags &amp; XE_BO_CREATE_STOLEN_BIT)</div><div class='add'>+			tile = xe_device_get_root_tile(xe);</div><div class='add'>+</div><div class='add'>+		xe_assert(xe, tile);</div><div class='add'>+</div><div class='add'>+		if (flags &amp; XE_BO_FIXED_PLACEMENT_BIT) {</div><div class='add'>+			err = xe_ggtt_insert_bo_at(tile-&gt;mem.ggtt, bo,</div><div class='add'>+						   start + bo-&gt;size, U64_MAX);</div><div class='add'>+		} else {</div><div class='add'>+			err = xe_ggtt_insert_bo(tile-&gt;mem.ggtt, bo);</div><div class='add'>+		}</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_unlock_put_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+</div><div class='add'>+err_unlock_put_bo:</div><div class='add'>+	__xe_bo_unset_bulk_move(bo);</div><div class='add'>+	xe_bo_unlock_vm_held(bo);</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *</div><div class='add'>+xe_bo_create_locked_range(struct xe_device *xe,</div><div class='add'>+			  struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+			  size_t size, u64 start, u64 end,</div><div class='add'>+			  enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	return __xe_bo_create_locked(xe, tile, vm, size, start, end, 0, type, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				  struct xe_vm *vm, size_t size,</div><div class='add'>+				  enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	return __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL, 0, type, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				struct xe_vm *vm, size_t size,</div><div class='add'>+				u16 cpu_caching,</div><div class='add'>+				enum ttm_bo_type type,</div><div class='add'>+				u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL,</div><div class='add'>+						 cpu_caching, type,</div><div class='add'>+						 flags | XE_BO_CREATE_USER_BIT);</div><div class='add'>+	if (!IS_ERR(bo))</div><div class='add'>+		xe_bo_unlock_vm_held(bo);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+			   struct xe_vm *vm, size_t size,</div><div class='add'>+			   enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = xe_bo_create_locked(xe, tile, vm, size, type, flags);</div><div class='add'>+</div><div class='add'>+	if (!IS_ERR(bo))</div><div class='add'>+		xe_bo_unlock_vm_held(bo);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				      struct xe_vm *vm,</div><div class='add'>+				      size_t size, u64 offset,</div><div class='add'>+				      enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+	u64 start = offset == ~0ull ? 0 : offset;</div><div class='add'>+	u64 end = offset == ~0ull ? offset : start + size;</div><div class='add'>+</div><div class='add'>+	if (flags &amp; XE_BO_CREATE_STOLEN_BIT &amp;&amp;</div><div class='add'>+	    xe_ttm_stolen_cpu_access_needs_ggtt(xe))</div><div class='add'>+		flags |= XE_BO_CREATE_GGTT_BIT;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_locked_range(xe, tile, vm, size, start, end, type,</div><div class='add'>+				       flags | XE_BO_NEEDS_CPU_ACCESS);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return bo;</div><div class='add'>+</div><div class='add'>+	err = xe_bo_pin(bo);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_put;</div><div class='add'>+</div><div class='add'>+	err = xe_bo_vmap(bo);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_unpin;</div><div class='add'>+</div><div class='add'>+	xe_bo_unlock_vm_held(bo);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+</div><div class='add'>+err_unpin:</div><div class='add'>+	xe_bo_unpin(bo);</div><div class='add'>+err_put:</div><div class='add'>+	xe_bo_unlock_vm_held(bo);</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				   struct xe_vm *vm, size_t size,</div><div class='add'>+				   enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	return xe_bo_create_pin_map_at(xe, tile, vm, size, ~0ull, type, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				     const void *data, size_t size,</div><div class='add'>+				     enum ttm_bo_type type, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = xe_bo_create_pin_map(xe, tile, NULL,</div><div class='add'>+						ALIGN(size, PAGE_SIZE),</div><div class='add'>+						type, flags);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return bo;</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;bo-&gt;vmap, 0, data, size);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_bo_unpin_map_no_vm(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	xe_bo_unpin_map_no_vm(arg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+					   size_t size, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(xe, tile, NULL, size, ttm_bo_type_kernel, flags);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return bo;</div><div class='add'>+</div><div class='add'>+	ret = drmm_add_action_or_reset(&amp;xe-&gt;drm, __xe_bo_unpin_map_no_vm, bo);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+					     const void *data, size_t size, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = xe_managed_bo_create_pin_map(xe, tile, ALIGN(size, PAGE_SIZE), flags);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return bo;</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;bo-&gt;vmap, 0, data, size);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * XXX: This is in the VM bind data path, likely should calculate this once and</div><div class='add'>+ * store, with a recalculation if the BO is moved.</div><div class='add'>+ */</div><div class='add'>+uint64_t vram_region_gpu_offset(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(res-&gt;bo-&gt;bdev);</div><div class='add'>+</div><div class='add'>+	if (res-&gt;mem_type == XE_PL_STOLEN)</div><div class='add'>+		return xe_ttm_stolen_gpu_offset(xe);</div><div class='add'>+</div><div class='add'>+	return res_to_mem_region(res)-&gt;dpa_base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_pin_external - pin an external BO</div><div class='add'>+ * @bo: buffer object to be pinned</div><div class='add'>+ *</div><div class='add'>+ * Pin an external (not tied to a VM, can be exported via dma-buf / prime FD)</div><div class='add'>+ * BO. Unique call compared to xe_bo_pin as this function has it own set of</div><div class='add'>+ * asserts and code to ensure evict / restore on suspend / resume.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 for success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_pin_external(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !bo-&gt;vm);</div><div class='add'>+	xe_assert(xe, xe_bo_is_user(bo));</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_pinned(bo)) {</div><div class='add'>+		err = xe_bo_validate(bo, NULL, false);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		if (xe_bo_is_vram(bo)) {</div><div class='add'>+			spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			list_add_tail(&amp;bo-&gt;pinned_link,</div><div class='add'>+				      &amp;xe-&gt;pinned.external_vram);</div><div class='add'>+			spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ttm_bo_pin(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: If we always use the reserve / unreserve functions for locking</div><div class='add'>+	 * we do not need this.</div><div class='add'>+	 */</div><div class='add'>+	ttm_bo_move_to_lru_tail_unlocked(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_pin(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* We currently don't expect user BO to be pinned */</div><div class='add'>+	xe_assert(xe, !xe_bo_is_user(bo));</div><div class='add'>+</div><div class='add'>+	/* Pinned object must be in GGTT or have pinned flag */</div><div class='add'>+	xe_assert(xe, bo-&gt;flags &amp; (XE_BO_CREATE_PINNED_BIT |</div><div class='add'>+				   XE_BO_CREATE_GGTT_BIT));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * No reason we can't support pinning imported dma-bufs we just don't</div><div class='add'>+	 * expect to pin an imported dma-buf.</div><div class='add'>+	 */</div><div class='add'>+	xe_assert(xe, !bo-&gt;ttm.base.import_attach);</div><div class='add'>+</div><div class='add'>+	/* We only expect at most 1 pin */</div><div class='add'>+	xe_assert(xe, !xe_bo_is_pinned(bo));</div><div class='add'>+</div><div class='add'>+	err = xe_bo_validate(bo, NULL, false);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For pinned objects in on DGFX, which are also in vram, we expect</div><div class='add'>+	 * these to be in contiguous VRAM memory. Required eviction / restore</div><div class='add'>+	 * during suspend / resume (force restore to same physical address).</div><div class='add'>+	 */</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; !(IS_ENABLED(CONFIG_DRM_XE_DEBUG) &amp;&amp;</div><div class='add'>+	    bo-&gt;flags &amp; XE_BO_INTERNAL_TEST)) {</div><div class='add'>+		struct ttm_place *place = &amp;(bo-&gt;placements[0]);</div><div class='add'>+</div><div class='add'>+		if (mem_type_is_vram(place-&gt;mem_type)) {</div><div class='add'>+			xe_assert(xe, place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS);</div><div class='add'>+</div><div class='add'>+			place-&gt;fpfn = (xe_bo_addr(bo, 0, PAGE_SIZE) -</div><div class='add'>+				       vram_region_gpu_offset(bo-&gt;ttm.resource)) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+			place-&gt;lpfn = place-&gt;fpfn + (bo-&gt;size &gt;&gt; PAGE_SHIFT);</div><div class='add'>+</div><div class='add'>+			spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			list_add_tail(&amp;bo-&gt;pinned_link, &amp;xe-&gt;pinned.kernel_bo_present);</div><div class='add'>+			spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ttm_bo_pin(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: If we always use the reserve / unreserve functions for locking</div><div class='add'>+	 * we do not need this.</div><div class='add'>+	 */</div><div class='add'>+	ttm_bo_move_to_lru_tail_unlocked(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_unpin_external - unpin an external BO</div><div class='add'>+ * @bo: buffer object to be unpinned</div><div class='add'>+ *</div><div class='add'>+ * Unpin an external (not tied to a VM, can be exported via dma-buf / prime FD)</div><div class='add'>+ * BO. Unique call compared to xe_bo_unpin as this function has it own set of</div><div class='add'>+ * asserts and code to ensure evict / restore on suspend / resume.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 for success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+void xe_bo_unpin_external(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !bo-&gt;vm);</div><div class='add'>+	xe_assert(xe, xe_bo_is_pinned(bo));</div><div class='add'>+	xe_assert(xe, xe_bo_is_user(bo));</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.pin_count == 1 &amp;&amp; !list_empty(&amp;bo-&gt;pinned_link)) {</div><div class='add'>+		spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+		list_del_init(&amp;bo-&gt;pinned_link);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ttm_bo_unpin(&amp;bo-&gt;ttm);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: If we always use the reserve / unreserve functions for locking</div><div class='add'>+	 * we do not need this.</div><div class='add'>+	 */</div><div class='add'>+	ttm_bo_move_to_lru_tail_unlocked(&amp;bo-&gt;ttm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_bo_unpin(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !bo-&gt;ttm.base.import_attach);</div><div class='add'>+	xe_assert(xe, xe_bo_is_pinned(bo));</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; !(IS_ENABLED(CONFIG_DRM_XE_DEBUG) &amp;&amp;</div><div class='add'>+	    bo-&gt;flags &amp; XE_BO_INTERNAL_TEST)) {</div><div class='add'>+		struct ttm_place *place = &amp;(bo-&gt;placements[0]);</div><div class='add'>+</div><div class='add'>+		if (mem_type_is_vram(place-&gt;mem_type)) {</div><div class='add'>+			xe_assert(xe, !list_empty(&amp;bo-&gt;pinned_link));</div><div class='add'>+</div><div class='add'>+			spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			list_del_init(&amp;bo-&gt;pinned_link);</div><div class='add'>+			spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ttm_bo_unpin(&amp;bo-&gt;ttm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_validate() - Make sure the bo is in an allowed placement</div><div class='add'>+ * @bo: The bo,</div><div class='add'>+ * @vm: Pointer to a the vm the bo shares a locked dma_resv object with, or</div><div class='add'>+ *      NULL. Used together with @allow_res_evict.</div><div class='add'>+ * @allow_res_evict: Whether it's allowed to evict bos sharing @vm's</div><div class='add'>+ *                   reservation object.</div><div class='add'>+ *</div><div class='add'>+ * Make sure the bo is in allowed placement, migrating it if necessary. If</div><div class='add'>+ * needed, other bos will be evicted. If bos selected for eviction shares</div><div class='add'>+ * the @vm's reservation object, they can be evicted iff @allow_res_evict is</div><div class='add'>+ * set to true, otherwise they will be bypassed.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on failure. May return</div><div class='add'>+ * -EINTR or -ERESTARTSYS if internal waits are interrupted by a signal.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_validate(struct xe_bo *bo, struct xe_vm *vm, bool allow_res_evict)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = true,</div><div class='add'>+		.no_wait_gpu = false,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (vm) {</div><div class='add'>+		lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+		xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+		ctx.allow_res_evict = allow_res_evict;</div><div class='add'>+		ctx.resv = xe_vm_resv(vm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ttm_bo_validate(&amp;bo-&gt;ttm, &amp;bo-&gt;placement, &amp;ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_bo_is_xe_bo(struct ttm_buffer_object *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo-&gt;destroy == &amp;xe_ttm_bo_destroy)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Resolve a BO address. There is no assert to check if the proper lock is held</div><div class='add'>+ * so it should only be used in cases where it is not fatal to get the wrong</div><div class='add'>+ * address, such as printing debug information, but not in cases where memory is</div><div class='add'>+ * written based on this result.</div><div class='add'>+ */</div><div class='add'>+dma_addr_t __xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	struct xe_res_cursor cur;</div><div class='add'>+	u64 page;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, page_size &lt;= PAGE_SIZE);</div><div class='add'>+	page = offset &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	offset &amp;= (PAGE_SIZE - 1);</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_vram(bo) &amp;&amp; !xe_bo_is_stolen(bo)) {</div><div class='add'>+		xe_assert(xe, bo-&gt;ttm.ttm);</div><div class='add'>+</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(bo), page &lt;&lt; PAGE_SHIFT,</div><div class='add'>+				page_size, &amp;cur);</div><div class='add'>+		return xe_res_dma(&amp;cur) + offset;</div><div class='add'>+	} else {</div><div class='add'>+		struct xe_res_cursor cur;</div><div class='add'>+</div><div class='add'>+		xe_res_first(bo-&gt;ttm.resource, page &lt;&lt; PAGE_SHIFT,</div><div class='add'>+			     page_size, &amp;cur);</div><div class='add'>+		return cur.start + offset + vram_region_gpu_offset(bo-&gt;ttm.resource);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dma_addr_t xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size)</div><div class='add'>+{</div><div class='add'>+	if (!READ_ONCE(bo-&gt;ttm.pin_count))</div><div class='add'>+		xe_bo_assert_held(bo);</div><div class='add'>+	return __xe_bo_addr(bo, offset, page_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_vmap(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	void *virtual;</div><div class='add'>+	bool is_iomem;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (!(bo-&gt;flags &amp; XE_BO_NEEDS_CPU_ACCESS))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!iosys_map_is_null(&amp;bo-&gt;vmap))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We use this more or less deprecated interface for now since</div><div class='add'>+	 * ttm_bo_vmap() doesn't offer the optimization of kmapping</div><div class='add'>+	 * single page bos, which is done here.</div><div class='add'>+	 * TODO: Fix up ttm_bo_vmap to do that, or fix up ttm_bo_kmap</div><div class='add'>+	 * to use struct iosys_map.</div><div class='add'>+	 */</div><div class='add'>+	ret = ttm_bo_kmap(&amp;bo-&gt;ttm, 0, bo-&gt;size &gt;&gt; PAGE_SHIFT, &amp;bo-&gt;kmap);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	virtual = ttm_kmap_obj_virtual(&amp;bo-&gt;kmap, &amp;is_iomem);</div><div class='add'>+	if (is_iomem)</div><div class='add'>+		iosys_map_set_vaddr_iomem(&amp;bo-&gt;vmap, (void __iomem *)virtual);</div><div class='add'>+	else</div><div class='add'>+		iosys_map_set_vaddr(&amp;bo-&gt;vmap, virtual);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_bo_vunmap(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (!iosys_map_is_null(&amp;bo-&gt;vmap)) {</div><div class='add'>+		iosys_map_clear(&amp;bo-&gt;vmap);</div><div class='add'>+		ttm_bo_kunmap(&amp;bo-&gt;kmap);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_bo_vunmap(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+	__xe_bo_vunmap(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gem_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_gem_create *args = data;</div><div class='add'>+	struct xe_vm *vm = NULL;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	unsigned int bo_flags;</div><div class='add'>+	u32 handle;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;pad[0] || args-&gt;pad[1] || args-&gt;pad[2]) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* at least one valid memory placement must be specified */</div><div class='add'>+	if (XE_IOCTL_DBG(xe, (args-&gt;placement &amp; ~xe-&gt;info.mem_region_mask) ||</div><div class='add'>+			 !args-&gt;placement))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp;</div><div class='add'>+			 ~(DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING |</div><div class='add'>+			   DRM_XE_GEM_CREATE_FLAG_SCANOUT |</div><div class='add'>+			   DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;handle))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !args-&gt;size))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;size &gt; SIZE_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;size &amp; ~PAGE_MASK))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	bo_flags = 0;</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING)</div><div class='add'>+		bo_flags |= XE_BO_DEFER_BACKING;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_GEM_CREATE_FLAG_SCANOUT)</div><div class='add'>+		bo_flags |= XE_BO_SCANOUT_BIT;</div><div class='add'>+</div><div class='add'>+	bo_flags |= args-&gt;placement &lt;&lt; (ffs(XE_BO_CREATE_SYSTEM_BIT) - 1);</div><div class='add'>+</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM) {</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !(bo_flags &amp; XE_BO_CREATE_VRAM_MASK)))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		bo_flags |= XE_BO_NEEDS_CPU_ACCESS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !args-&gt;cpu_caching ||</div><div class='add'>+			 args-&gt;cpu_caching &gt; DRM_XE_GEM_CPU_CACHING_WC))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, bo_flags &amp; XE_BO_CREATE_VRAM_MASK &amp;&amp;</div><div class='add'>+			 args-&gt;cpu_caching != DRM_XE_GEM_CPU_CACHING_WC))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, bo_flags &amp; XE_BO_SCANOUT_BIT &amp;&amp;</div><div class='add'>+			 args-&gt;cpu_caching == DRM_XE_GEM_CPU_CACHING_WB))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;vm_id) {</div><div class='add'>+		vm = xe_vm_lookup(xef, args-&gt;vm_id);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !vm))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+		err = xe_vm_lock(vm, true);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_vm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_user(xe, NULL, vm, args-&gt;size, args-&gt;cpu_caching,</div><div class='add'>+			       ttm_bo_type_device, bo_flags);</div><div class='add'>+</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_unlock(vm);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		err = PTR_ERR(bo);</div><div class='add'>+		goto out_vm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drm_gem_handle_create(file, &amp;bo-&gt;ttm.base, &amp;handle);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_bulk;</div><div class='add'>+</div><div class='add'>+	args-&gt;handle = handle;</div><div class='add'>+	goto out_put;</div><div class='add'>+</div><div class='add'>+out_bulk:</div><div class='add'>+	if (vm &amp;&amp; !xe_vm_in_fault_mode(vm)) {</div><div class='add'>+		xe_vm_lock(vm, false);</div><div class='add'>+		__xe_bo_unset_bulk_move(bo);</div><div class='add'>+		xe_vm_unlock(vm);</div><div class='add'>+	}</div><div class='add'>+out_put:</div><div class='add'>+	xe_bo_put(bo);</div><div class='add'>+out_vm:</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_put(vm);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			     struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct drm_xe_gem_mmap_offset *args = data;</div><div class='add'>+	struct drm_gem_object *gem_obj;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gem_obj = drm_gem_object_lookup(file, args-&gt;handle);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !gem_obj))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	/* The mmap offset was set up at BO allocation time. */</div><div class='add'>+	args-&gt;offset = drm_vma_node_offset_addr(&amp;gem_obj-&gt;vma_node);</div><div class='add'>+</div><div class='add'>+	xe_bo_put(gem_to_xe_bo(gem_obj));</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_lock() - Lock the buffer object's dma_resv object</div><div class='add'>+ * @bo: The struct xe_bo whose lock is to be taken</div><div class='add'>+ * @intr: Whether to perform any wait interruptible</div><div class='add'>+ *</div><div class='add'>+ * Locks the buffer object's dma_resv object. If the buffer object is</div><div class='add'>+ * pointing to a shared dma_resv object, that shared lock is locked.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, -EINTR if @intr is true and the wait for a</div><div class='add'>+ * contended lock was interrupted. If @intr is set to false, the</div><div class='add'>+ * function always returns 0.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_lock(struct xe_bo *bo, bool intr)</div><div class='add'>+{</div><div class='add'>+	if (intr)</div><div class='add'>+		return dma_resv_lock_interruptible(bo-&gt;ttm.base.resv, NULL);</div><div class='add'>+</div><div class='add'>+	dma_resv_lock(bo-&gt;ttm.base.resv, NULL);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_unlock() - Unlock the buffer object's dma_resv object</div><div class='add'>+ * @bo: The struct xe_bo whose lock is to be released.</div><div class='add'>+ *</div><div class='add'>+ * Unlock a buffer object lock that was locked by xe_bo_lock().</div><div class='add'>+ */</div><div class='add'>+void xe_bo_unlock(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	dma_resv_unlock(bo-&gt;ttm.base.resv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_can_migrate - Whether a buffer object likely can be migrated</div><div class='add'>+ * @bo: The buffer object to migrate</div><div class='add'>+ * @mem_type: The TTM memory type intended to migrate to</div><div class='add'>+ *</div><div class='add'>+ * Check whether the buffer object supports migration to the</div><div class='add'>+ * given memory type. Note that pinning may affect the ability to migrate as</div><div class='add'>+ * returned by this function.</div><div class='add'>+ *</div><div class='add'>+ * This function is primarily intended as a helper for checking the</div><div class='add'>+ * possibility to migrate buffer objects and can be called without</div><div class='add'>+ * the object lock held.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if migration is possible, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_bo_can_migrate(struct xe_bo *bo, u32 mem_type)</div><div class='add'>+{</div><div class='add'>+	unsigned int cur_place;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.type == ttm_bo_type_kernel)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.type == ttm_bo_type_sg)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (cur_place = 0; cur_place &lt; bo-&gt;placement.num_placement;</div><div class='add'>+	     cur_place++) {</div><div class='add'>+		if (bo-&gt;placements[cur_place].mem_type == mem_type)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_place_from_ttm_type(u32 mem_type, struct ttm_place *place)</div><div class='add'>+{</div><div class='add'>+	memset(place, 0, sizeof(*place));</div><div class='add'>+	place-&gt;mem_type = mem_type;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_migrate - Migrate an object to the desired region id</div><div class='add'>+ * @bo: The buffer object to migrate.</div><div class='add'>+ * @mem_type: The TTM region type to migrate to.</div><div class='add'>+ *</div><div class='add'>+ * Attempt to migrate the buffer object to the desired memory region. The</div><div class='add'>+ * buffer object may not be pinned, and must be locked.</div><div class='add'>+ * On successful completion, the object memory type will be updated,</div><div class='add'>+ * but an async migration task may not have completed yet, and to</div><div class='add'>+ * accomplish that, the object's kernel fences must be signaled with</div><div class='add'>+ * the object lock held.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success. Negative error code on failure. In particular may</div><div class='add'>+ * return -EINTR or -ERESTARTSYS if signal pending.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_migrate(struct xe_bo *bo, u32 mem_type)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ttm_to_xe_device(bo-&gt;ttm.bdev);</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = true,</div><div class='add'>+		.no_wait_gpu = false,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_placement placement;</div><div class='add'>+	struct ttm_place requested;</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.resource-&gt;mem_type == mem_type)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_pinned(bo))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_can_migrate(bo, mem_type))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	xe_place_from_ttm_type(mem_type, &amp;requested);</div><div class='add'>+	placement.num_placement = 1;</div><div class='add'>+	placement.num_busy_placement = 1;</div><div class='add'>+	placement.placement = &amp;requested;</div><div class='add'>+	placement.busy_placement = &amp;requested;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Stolen needs to be handled like below VRAM handling if we ever need</div><div class='add'>+	 * to support it.</div><div class='add'>+	 */</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, mem_type == XE_PL_STOLEN);</div><div class='add'>+</div><div class='add'>+	if (mem_type_is_vram(mem_type)) {</div><div class='add'>+		u32 c = 0;</div><div class='add'>+</div><div class='add'>+		add_vram(xe, bo, &amp;requested, bo-&gt;flags, mem_type, &amp;c);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ttm_bo_validate(&amp;bo-&gt;ttm, &amp;placement, &amp;ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_evict - Evict an object to evict placement</div><div class='add'>+ * @bo: The buffer object to migrate.</div><div class='add'>+ * @force_alloc: Set force_alloc in ttm_operation_ctx</div><div class='add'>+ *</div><div class='add'>+ * On successful completion, the object memory will be moved to evict</div><div class='add'>+ * placement. Ths function blocks until the object has been fully moved.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success. Negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_evict(struct xe_bo *bo, bool force_alloc)</div><div class='add'>+{</div><div class='add'>+	struct ttm_operation_ctx ctx = {</div><div class='add'>+		.interruptible = false,</div><div class='add'>+		.no_wait_gpu = false,</div><div class='add'>+		.force_alloc = force_alloc,</div><div class='add'>+	};</div><div class='add'>+	struct ttm_placement placement;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_evict_flags(&amp;bo-&gt;ttm, &amp;placement);</div><div class='add'>+	ret = ttm_bo_validate(&amp;bo-&gt;ttm, &amp;placement, &amp;ctx);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dma_resv_wait_timeout(bo-&gt;ttm.base.resv, DMA_RESV_USAGE_KERNEL,</div><div class='add'>+			      false, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_needs_ccs_pages - Whether a bo needs to back up CCS pages when</div><div class='add'>+ * placed in system memory.</div><div class='add'>+ * @bo: The xe_bo</div><div class='add'>+ *</div><div class='add'>+ * Return: true if extra pages need to be allocated, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_bo_needs_ccs_pages(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+</div><div class='add'>+	if (!xe_device_has_flat_ccs(xe) || bo-&gt;ttm.type != ttm_bo_type_device)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* On discrete GPUs, if the GPU can access this buffer from</div><div class='add'>+	 * system memory (i.e., it allows XE_PL_TT placement), FlatCCS</div><div class='add'>+	 * can't be used since there's no CCS storage associated with</div><div class='add'>+	 * non-VRAM addresses.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; (bo-&gt;flags &amp; XE_BO_CREATE_SYSTEM_BIT))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __xe_bo_release_dummy() - Dummy kref release function</div><div class='add'>+ * @kref: The embedded struct kref.</div><div class='add'>+ *</div><div class='add'>+ * Dummy release function for xe_bo_put_deferred(). Keep off.</div><div class='add'>+ */</div><div class='add'>+void __xe_bo_release_dummy(struct kref *kref)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_put_commit() - Put bos whose put was deferred by xe_bo_put_deferred().</div><div class='add'>+ * @deferred: The lockless list used for the call to xe_bo_put_deferred().</div><div class='add'>+ *</div><div class='add'>+ * Puts all bos whose put was deferred by xe_bo_put_deferred().</div><div class='add'>+ * The @deferred list can be either an onstack local list or a global</div><div class='add'>+ * shared list used by a workqueue.</div><div class='add'>+ */</div><div class='add'>+void xe_bo_put_commit(struct llist_head *deferred)</div><div class='add'>+{</div><div class='add'>+	struct llist_node *freed;</div><div class='add'>+	struct xe_bo *bo, *next;</div><div class='add'>+</div><div class='add'>+	if (!deferred)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	freed = llist_del_all(deferred);</div><div class='add'>+	if (!freed)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	llist_for_each_entry_safe(bo, next, freed, freed)</div><div class='add'>+		drm_gem_object_free(&amp;bo-&gt;ttm.base.refcount);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_dumb_create - Create a dumb bo as backing for a fb</div><div class='add'>+ * @file_priv: ...</div><div class='add'>+ * @dev: ...</div><div class='add'>+ * @args: ...</div><div class='add'>+ *</div><div class='add'>+ * See dumb_create() hook in include/drm/drm_drv.h</div><div class='add'>+ *</div><div class='add'>+ * Return: ...</div><div class='add'>+ */</div><div class='add'>+int xe_bo_dumb_create(struct drm_file *file_priv,</div><div class='add'>+		      struct drm_device *dev,</div><div class='add'>+		      struct drm_mode_create_dumb *args)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	uint32_t handle;</div><div class='add'>+	int cpp = DIV_ROUND_UP(args-&gt;bpp, 8);</div><div class='add'>+	int err;</div><div class='add'>+	u32 page_size = max_t(u32, PAGE_SIZE,</div><div class='add'>+		xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);</div><div class='add'>+</div><div class='add'>+	args-&gt;pitch = ALIGN(args-&gt;width * cpp, 64);</div><div class='add'>+	args-&gt;size = ALIGN(mul_u32_u32(args-&gt;pitch, args-&gt;height),</div><div class='add'>+			   page_size);</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_user(xe, NULL, NULL, args-&gt;size,</div><div class='add'>+			       DRM_XE_GEM_CPU_CACHING_WC,</div><div class='add'>+			       ttm_bo_type_device,</div><div class='add'>+			       XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |</div><div class='add'>+			       XE_BO_CREATE_USER_BIT | XE_BO_SCANOUT_BIT |</div><div class='add'>+			       XE_BO_NEEDS_CPU_ACCESS);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	err = drm_gem_handle_create(file_priv, &amp;bo-&gt;ttm.base, &amp;handle);</div><div class='add'>+	/* drop reference from allocate - handle holds it now */</div><div class='add'>+	drm_gem_object_put(&amp;bo-&gt;ttm.base);</div><div class='add'>+	if (!err)</div><div class='add'>+		args-&gt;handle = handle;</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_bo.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h<br/>new file mode 100644<br/>index 000000000000..9b1279aca127<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo.h</a></div><div class='hunk'>@@ -0,0 +1,355 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BO_H_</div><div class='add'>+#define _XE_BO_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_vm_types.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_assert_held(vm) - Assert that the vm's reservation object is held.</div><div class='add'>+ * @vm: The vm</div><div class='add'>+ */</div><div class='add'>+#define xe_vm_assert_held(vm) dma_resv_assert_held(xe_vm_resv(vm))</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+#define XE_DEFAULT_GTT_SIZE_MB          3072ULL /* 3GB by default */</div><div class='add'>+</div><div class='add'>+#define XE_BO_CREATE_USER_BIT		BIT(0)</div><div class='add'>+/* The bits below need to be contiguous, or things break */</div><div class='add'>+#define XE_BO_CREATE_SYSTEM_BIT		BIT(1)</div><div class='add'>+#define XE_BO_CREATE_VRAM0_BIT		BIT(2)</div><div class='add'>+#define XE_BO_CREATE_VRAM1_BIT		BIT(3)</div><div class='add'>+#define XE_BO_CREATE_VRAM_MASK		(XE_BO_CREATE_VRAM0_BIT | \</div><div class='add'>+					 XE_BO_CREATE_VRAM1_BIT)</div><div class='add'>+/* -- */</div><div class='add'>+#define XE_BO_CREATE_STOLEN_BIT		BIT(4)</div><div class='add'>+#define XE_BO_CREATE_VRAM_IF_DGFX(tile) \</div><div class='add'>+	(IS_DGFX(tile_to_xe(tile)) ? XE_BO_CREATE_VRAM0_BIT &lt;&lt; (tile)-&gt;id : \</div><div class='add'>+	 XE_BO_CREATE_SYSTEM_BIT)</div><div class='add'>+#define XE_BO_CREATE_GGTT_BIT		BIT(5)</div><div class='add'>+#define XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT BIT(6)</div><div class='add'>+#define XE_BO_CREATE_PINNED_BIT		BIT(7)</div><div class='add'>+#define XE_BO_CREATE_NO_RESV_EVICT	BIT(8)</div><div class='add'>+#define XE_BO_DEFER_BACKING		BIT(9)</div><div class='add'>+#define XE_BO_SCANOUT_BIT		BIT(10)</div><div class='add'>+#define XE_BO_FIXED_PLACEMENT_BIT	BIT(11)</div><div class='add'>+#define XE_BO_PAGETABLE			BIT(12)</div><div class='add'>+#define XE_BO_NEEDS_CPU_ACCESS		BIT(13)</div><div class='add'>+/* this one is trigger internally only */</div><div class='add'>+#define XE_BO_INTERNAL_TEST		BIT(30)</div><div class='add'>+#define XE_BO_INTERNAL_64K		BIT(31)</div><div class='add'>+</div><div class='add'>+#define XELPG_PPGTT_PTE_PAT3		BIT_ULL(62)</div><div class='add'>+#define XE2_PPGTT_PTE_PAT4		BIT_ULL(61)</div><div class='add'>+#define XE_PPGTT_PDE_PDPE_PAT2		BIT_ULL(12)</div><div class='add'>+#define XE_PPGTT_PTE_PAT2		BIT_ULL(7)</div><div class='add'>+#define XE_PPGTT_PTE_PAT1		BIT_ULL(4)</div><div class='add'>+#define XE_PPGTT_PTE_PAT0		BIT_ULL(3)</div><div class='add'>+</div><div class='add'>+#define XE_PTE_SHIFT			12</div><div class='add'>+#define XE_PAGE_SIZE			(1 &lt;&lt; XE_PTE_SHIFT)</div><div class='add'>+#define XE_PTE_MASK			(XE_PAGE_SIZE - 1)</div><div class='add'>+#define XE_PDE_SHIFT			(XE_PTE_SHIFT - 3)</div><div class='add'>+#define XE_PDES				(1 &lt;&lt; XE_PDE_SHIFT)</div><div class='add'>+#define XE_PDE_MASK			(XE_PDES - 1)</div><div class='add'>+</div><div class='add'>+#define XE_64K_PTE_SHIFT		16</div><div class='add'>+#define XE_64K_PAGE_SIZE		(1 &lt;&lt; XE_64K_PTE_SHIFT)</div><div class='add'>+#define XE_64K_PTE_MASK			(XE_64K_PAGE_SIZE - 1)</div><div class='add'>+#define XE_64K_PDE_MASK			(XE_PDE_MASK &gt;&gt; 4)</div><div class='add'>+</div><div class='add'>+#define XE_PDE_PS_2M			BIT_ULL(7)</div><div class='add'>+#define XE_PDPE_PS_1G			BIT_ULL(7)</div><div class='add'>+#define XE_PDE_IPS_64K			BIT_ULL(11)</div><div class='add'>+</div><div class='add'>+#define XE_GGTT_PTE_DM			BIT_ULL(1)</div><div class='add'>+#define XE_USM_PPGTT_PTE_AE		BIT_ULL(10)</div><div class='add'>+#define XE_PPGTT_PTE_DM			BIT_ULL(11)</div><div class='add'>+#define XE_PDE_64K			BIT_ULL(6)</div><div class='add'>+#define XE_PTE_PS64			BIT_ULL(8)</div><div class='add'>+#define XE_PTE_NULL			BIT_ULL(9)</div><div class='add'>+</div><div class='add'>+#define XE_PAGE_PRESENT			BIT_ULL(0)</div><div class='add'>+#define XE_PAGE_RW			BIT_ULL(1)</div><div class='add'>+</div><div class='add'>+#define XE_PL_SYSTEM		TTM_PL_SYSTEM</div><div class='add'>+#define XE_PL_TT		TTM_PL_TT</div><div class='add'>+#define XE_PL_VRAM0		TTM_PL_VRAM</div><div class='add'>+#define XE_PL_VRAM1		(XE_PL_VRAM0 + 1)</div><div class='add'>+#define XE_PL_STOLEN		(TTM_NUM_MEM_TYPES - 1)</div><div class='add'>+</div><div class='add'>+#define XE_BO_PROPS_INVALID	(-1)</div><div class='add'>+</div><div class='add'>+struct sg_table;</div><div class='add'>+</div><div class='add'>+struct xe_bo *xe_bo_alloc(void);</div><div class='add'>+void xe_bo_free(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+struct xe_bo *___xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+				     struct xe_tile *tile, struct dma_resv *resv,</div><div class='add'>+				     struct ttm_lru_bulk_move *bulk, size_t size,</div><div class='add'>+				     u16 cpu_caching, enum ttm_bo_type type,</div><div class='add'>+				     u32 flags);</div><div class='add'>+struct xe_bo *</div><div class='add'>+xe_bo_create_locked_range(struct xe_device *xe,</div><div class='add'>+			  struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+			  size_t size, u64 start, u64 end,</div><div class='add'>+			  enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				  struct xe_vm *vm, size_t size,</div><div class='add'>+				  enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+			   struct xe_vm *vm, size_t size,</div><div class='add'>+			   enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				struct xe_vm *vm, size_t size,</div><div class='add'>+				u16 cpu_caching,</div><div class='add'>+				enum ttm_bo_type type,</div><div class='add'>+				u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				   struct xe_vm *vm, size_t size,</div><div class='add'>+				   enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				      struct xe_vm *vm, size_t size, u64 offset,</div><div class='add'>+				      enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				     const void *data, size_t size,</div><div class='add'>+				     enum ttm_bo_type type, u32 flags);</div><div class='add'>+struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+					   size_t size, u32 flags);</div><div class='add'>+struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+					     const void *data, size_t size, u32 flags);</div><div class='add'>+</div><div class='add'>+int xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,</div><div class='add'>+			      u32 bo_flags);</div><div class='add'>+</div><div class='add'>+static inline struct xe_bo *ttm_to_xe_bo(const struct ttm_buffer_object *bo)</div><div class='add'>+{</div><div class='add'>+	return container_of(bo, struct xe_bo, ttm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_bo *gem_to_xe_bo(const struct drm_gem_object *obj)</div><div class='add'>+{</div><div class='add'>+	return container_of(obj, struct xe_bo, ttm.base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define xe_bo_device(bo) ttm_to_xe_device((bo)-&gt;ttm.bdev)</div><div class='add'>+</div><div class='add'>+static inline struct xe_bo *xe_bo_get(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo)</div><div class='add'>+		drm_gem_object_get(&amp;bo-&gt;ttm.base);</div><div class='add'>+</div><div class='add'>+	return bo;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_bo_put(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo)</div><div class='add'>+		drm_gem_object_put(&amp;bo-&gt;ttm.base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __xe_bo_unset_bulk_move(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo)</div><div class='add'>+		ttm_bo_set_bulk_move(&amp;bo-&gt;ttm, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_bo_assert_held(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo)</div><div class='add'>+		dma_resv_assert_held((bo)-&gt;ttm.base.resv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_lock(struct xe_bo *bo, bool intr);</div><div class='add'>+</div><div class='add'>+void xe_bo_unlock(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+static inline void xe_bo_unlock_vm_held(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (bo) {</div><div class='add'>+		XE_WARN_ON(bo-&gt;vm &amp;&amp; bo-&gt;ttm.base.resv != xe_vm_resv(bo-&gt;vm));</div><div class='add'>+		if (bo-&gt;vm)</div><div class='add'>+			xe_vm_assert_held(bo-&gt;vm);</div><div class='add'>+		else</div><div class='add'>+			dma_resv_unlock(bo-&gt;ttm.base.resv);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_pin_external(struct xe_bo *bo);</div><div class='add'>+int xe_bo_pin(struct xe_bo *bo);</div><div class='add'>+void xe_bo_unpin_external(struct xe_bo *bo);</div><div class='add'>+void xe_bo_unpin(struct xe_bo *bo);</div><div class='add'>+int xe_bo_validate(struct xe_bo *bo, struct xe_vm *vm, bool allow_res_evict);</div><div class='add'>+</div><div class='add'>+static inline bool xe_bo_is_pinned(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return bo-&gt;ttm.pin_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_bo_unpin_map_no_vm(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (likely(bo)) {</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		xe_bo_unpin(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_bo_is_xe_bo(struct ttm_buffer_object *bo);</div><div class='add'>+dma_addr_t __xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size);</div><div class='add'>+dma_addr_t xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size);</div><div class='add'>+</div><div class='add'>+static inline dma_addr_t</div><div class='add'>+xe_bo_main_addr(struct xe_bo *bo, size_t page_size)</div><div class='add'>+{</div><div class='add'>+	return xe_bo_addr(bo, 0, page_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32</div><div class='add'>+xe_bo_ggtt_addr(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(bo-&gt;ggtt_node.size &gt; bo-&gt;size);</div><div class='add'>+	XE_WARN_ON(bo-&gt;ggtt_node.start + bo-&gt;ggtt_node.size &gt; (1ull &lt;&lt; 32));</div><div class='add'>+	return bo-&gt;ggtt_node.start;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_bo_vmap(struct xe_bo *bo);</div><div class='add'>+void xe_bo_vunmap(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+bool mem_type_is_vram(u32 mem_type);</div><div class='add'>+bool xe_bo_is_vram(struct xe_bo *bo);</div><div class='add'>+bool xe_bo_is_stolen(struct xe_bo *bo);</div><div class='add'>+bool xe_bo_is_stolen_devmem(struct xe_bo *bo);</div><div class='add'>+uint64_t vram_region_gpu_offset(struct ttm_resource *res);</div><div class='add'>+</div><div class='add'>+bool xe_bo_can_migrate(struct xe_bo *bo, u32 mem_type);</div><div class='add'>+</div><div class='add'>+int xe_bo_migrate(struct xe_bo *bo, u32 mem_type);</div><div class='add'>+int xe_bo_evict(struct xe_bo *bo, bool force_alloc);</div><div class='add'>+</div><div class='add'>+int xe_bo_evict_pinned(struct xe_bo *bo);</div><div class='add'>+int xe_bo_restore_pinned(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+extern struct ttm_device_funcs xe_ttm_funcs;</div><div class='add'>+</div><div class='add'>+int xe_gem_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			struct drm_file *file);</div><div class='add'>+int xe_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			     struct drm_file *file);</div><div class='add'>+int xe_bo_dumb_create(struct drm_file *file_priv,</div><div class='add'>+		      struct drm_device *dev,</div><div class='add'>+		      struct drm_mode_create_dumb *args);</div><div class='add'>+</div><div class='add'>+bool xe_bo_needs_ccs_pages(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+static inline size_t xe_bo_ccs_pages_start(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return PAGE_ALIGN(bo-&gt;ttm.base.size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_bo_has_pages(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if ((bo-&gt;ttm.ttm &amp;&amp; ttm_tt_is_populated(bo-&gt;ttm.ttm)) ||</div><div class='add'>+	    xe_bo_is_vram(bo))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void __xe_bo_release_dummy(struct kref *kref);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_put_deferred() - Put a buffer object with delayed final freeing</div><div class='add'>+ * @bo: The bo to put.</div><div class='add'>+ * @deferred: List to which to add the buffer object if we cannot put, or</div><div class='add'>+ * NULL if the function is to put unconditionally.</div><div class='add'>+ *</div><div class='add'>+ * Since the final freeing of an object includes both sleeping and (!)</div><div class='add'>+ * memory allocation in the dma_resv individualization, it's not ok</div><div class='add'>+ * to put an object from atomic context nor from within a held lock</div><div class='add'>+ * tainted by reclaim. In such situations we want to defer the final</div><div class='add'>+ * freeing until we've exited the restricting context, or in the worst</div><div class='add'>+ * case to a workqueue.</div><div class='add'>+ * This function either puts the object if possible without the refcount</div><div class='add'>+ * reaching zero, or adds it to the @deferred list if that was not possible.</div><div class='add'>+ * The caller needs to follow up with a call to xe_bo_put_commit() to actually</div><div class='add'>+ * put the bo iff this function returns true. It's safe to always</div><div class='add'>+ * follow up with a call to xe_bo_put_commit().</div><div class='add'>+ * TODO: It's TTM that is the villain here. Perhaps TTM should add an</div><div class='add'>+ * interface like this.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if @bo was the first object put on the @freed list,</div><div class='add'>+ * false otherwise.</div><div class='add'>+ */</div><div class='add'>+static inline bool</div><div class='add'>+xe_bo_put_deferred(struct xe_bo *bo, struct llist_head *deferred)</div><div class='add'>+{</div><div class='add'>+	if (!deferred) {</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!kref_put(&amp;bo-&gt;ttm.base.refcount, __xe_bo_release_dummy))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return llist_add(&amp;bo-&gt;freed, deferred);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_bo_put_commit(struct llist_head *deferred);</div><div class='add'>+</div><div class='add'>+struct sg_table *xe_bo_sg(struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * xe_sg_segment_size() - Provides upper limit for sg segment size.</div><div class='add'>+ * @dev: device pointer</div><div class='add'>+ *</div><div class='add'>+ * Returns the maximum segment size for the 'struct scatterlist'</div><div class='add'>+ * elements.</div><div class='add'>+ */</div><div class='add'>+static inline unsigned int xe_sg_segment_size(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct scatterlist __maybe_unused sg;</div><div class='add'>+	size_t max = BIT_ULL(sizeof(sg.length) * 8) - 1;</div><div class='add'>+</div><div class='add'>+	max = min_t(size_t, max, dma_max_mapping_size(dev));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The iommu_dma_map_sg() function ensures iova allocation doesn't</div><div class='add'>+	 * cross dma segment boundary. It does so by padding some sg elements.</div><div class='add'>+	 * This can cause overflow, ending up with sg-&gt;length being set to 0.</div><div class='add'>+	 * Avoid this by ensuring maximum segment size is half of 'max'</div><div class='add'>+	 * rounded down to PAGE_SIZE.</div><div class='add'>+	 */</div><div class='add'>+	return round_down(max / 2, PAGE_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define i915_gem_object_flush_if_display(obj)		((void)(obj))</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_is_mem_type - Whether the bo currently resides in the given</div><div class='add'>+ * TTM memory type</div><div class='add'>+ * @bo: The bo to check.</div><div class='add'>+ * @mem_type: The TTM memory type.</div><div class='add'>+ *</div><div class='add'>+ * Return: true iff the bo resides in @mem_type, false otherwise.</div><div class='add'>+ */</div><div class='add'>+static inline bool xe_bo_is_mem_type(struct xe_bo *bo, u32 mem_type)</div><div class='add'>+{</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+	return bo-&gt;ttm.resource-&gt;mem_type == mem_type;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo_doc.h b/drivers/gpu/drm/xe/xe_bo_doc.h<br/>new file mode 100644<br/>index 000000000000..f57d440cc95a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_doc.h</a></div><div class='hunk'>@@ -0,0 +1,179 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BO_DOC_H_</div><div class='add'>+#define _XE_BO_DOC_H_</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Buffer Objects (BO)</div><div class='add'>+ *</div><div class='add'>+ * BO management</div><div class='add'>+ * =============</div><div class='add'>+ *</div><div class='add'>+ * TTM manages (placement, eviction, etc...) all BOs in XE.</div><div class='add'>+ *</div><div class='add'>+ * BO creation</div><div class='add'>+ * ===========</div><div class='add'>+ *</div><div class='add'>+ * Create a chunk of memory which can be used by the GPU. Placement rules</div><div class='add'>+ * (sysmem or vram region) passed in upon creation. TTM handles placement of BO</div><div class='add'>+ * and can trigger eviction of other BOs to make space for the new BO.</div><div class='add'>+ *</div><div class='add'>+ * Kernel BOs</div><div class='add'>+ * ----------</div><div class='add'>+ *</div><div class='add'>+ * A kernel BO is created as part of driver load (e.g. uC firmware images, GuC</div><div class='add'>+ * ADS, etc...) or a BO created as part of a user operation which requires</div><div class='add'>+ * a kernel BO (e.g. engine state, memory for page tables, etc...). These BOs</div><div class='add'>+ * are typically mapped in the GGTT (any kernel BOs aside memory for page tables</div><div class='add'>+ * are in the GGTT), are pinned (can't move or be evicted at runtime), have a</div><div class='add'>+ * vmap (XE can access the memory via xe_map layer) and have contiguous physical</div><div class='add'>+ * memory.</div><div class='add'>+ *</div><div class='add'>+ * More details of why kernel BOs are pinned and contiguous below.</div><div class='add'>+ *</div><div class='add'>+ * User BOs</div><div class='add'>+ * --------</div><div class='add'>+ *</div><div class='add'>+ * A user BO is created via the DRM_IOCTL_XE_GEM_CREATE IOCTL. Once it is</div><div class='add'>+ * created the BO can be mmap'd (via DRM_IOCTL_XE_GEM_MMAP_OFFSET) for user</div><div class='add'>+ * access and it can be bound for GPU access (via DRM_IOCTL_XE_VM_BIND). All</div><div class='add'>+ * user BOs are evictable and user BOs are never pinned by XE. The allocation of</div><div class='add'>+ * the backing store can be defered from creation time until first use which is</div><div class='add'>+ * either mmap, bind, or pagefault.</div><div class='add'>+ *</div><div class='add'>+ * Private BOs</div><div class='add'>+ * ~~~~~~~~~~~</div><div class='add'>+ *</div><div class='add'>+ * A private BO is a user BO created with a valid VM argument passed into the</div><div class='add'>+ * create IOCTL. If a BO is private it cannot be exported via prime FD and</div><div class='add'>+ * mappings can only be created for the BO within the VM it is tied to. Lastly,</div><div class='add'>+ * the BO dma-resv slots / lock point to the VM's dma-resv slots / lock (all</div><div class='add'>+ * private BOs to a VM share common dma-resv slots / lock).</div><div class='add'>+ *</div><div class='add'>+ * External BOs</div><div class='add'>+ * ~~~~~~~~~~~~</div><div class='add'>+ *</div><div class='add'>+ * An external BO is a user BO created with a NULL VM argument passed into the</div><div class='add'>+ * create IOCTL. An external BO can be shared with different UMDs / devices via</div><div class='add'>+ * prime FD and the BO can be mapped into multiple VMs. An external BO has its</div><div class='add'>+ * own unique dma-resv slots / lock. An external BO will be in an array of all</div><div class='add'>+ * VMs which has a mapping of the BO. This allows VMs to lookup and lock all</div><div class='add'>+ * external BOs mapped in the VM as needed.</div><div class='add'>+ *</div><div class='add'>+ * BO placement</div><div class='add'>+ * ~~~~~~~~~~~~</div><div class='add'>+ *</div><div class='add'>+ * When a user BO is created, a mask of valid placements is passed indicating</div><div class='add'>+ * which memory regions are considered valid.</div><div class='add'>+ *</div><div class='add'>+ * The memory region information is available via query uAPI (TODO: add link).</div><div class='add'>+ *</div><div class='add'>+ * BO validation</div><div class='add'>+ * =============</div><div class='add'>+ *</div><div class='add'>+ * BO validation (ttm_bo_validate) refers to ensuring a BO has a valid</div><div class='add'>+ * placement. If a BO was swapped to temporary storage, a validation call will</div><div class='add'>+ * trigger a move back to a valid (location where GPU can access BO) placement.</div><div class='add'>+ * Validation of a BO may evict other BOs to make room for the BO being</div><div class='add'>+ * validated.</div><div class='add'>+ *</div><div class='add'>+ * BO eviction / moving</div><div class='add'>+ * ====================</div><div class='add'>+ *</div><div class='add'>+ * All eviction (or in other words, moving a BO from one memory location to</div><div class='add'>+ * another) is routed through TTM with a callback into XE.</div><div class='add'>+ *</div><div class='add'>+ * Runtime eviction</div><div class='add'>+ * ----------------</div><div class='add'>+ *</div><div class='add'>+ * Runtime evictions refers to during normal operations where TTM decides it</div><div class='add'>+ * needs to move a BO. Typically this is because TTM needs to make room for</div><div class='add'>+ * another BO and the evicted BO is first BO on LRU list that is not locked.</div><div class='add'>+ *</div><div class='add'>+ * An example of this is a new BO which can only be placed in VRAM but there is</div><div class='add'>+ * not space in VRAM. There could be multiple BOs which have sysmem and VRAM</div><div class='add'>+ * placement rules which currently reside in VRAM, TTM trigger a will move of</div><div class='add'>+ * one (or multiple) of these BO(s) until there is room in VRAM to place the new</div><div class='add'>+ * BO. The evicted BO(s) are valid but still need new bindings before the BO</div><div class='add'>+ * used again (exec or compute mode rebind worker).</div><div class='add'>+ *</div><div class='add'>+ * Another example would be, TTM can't find a BO to evict which has another</div><div class='add'>+ * valid placement. In this case TTM will evict one (or multiple) unlocked BO(s)</div><div class='add'>+ * to a temporary unreachable (invalid) placement. The evicted BO(s) are invalid</div><div class='add'>+ * and before next use need to be moved to a valid placement and rebound.</div><div class='add'>+ *</div><div class='add'>+ * In both cases, moves of these BOs are scheduled behind the fences in the BO's</div><div class='add'>+ * dma-resv slots.</div><div class='add'>+ *</div><div class='add'>+ * WW locking tries to ensures if 2 VMs use 51% of the memory forward progress</div><div class='add'>+ * is made on both VMs.</div><div class='add'>+ *</div><div class='add'>+ * Runtime eviction uses per a GT migration engine (TODO: link to migration</div><div class='add'>+ * engine doc) to do a GPU memcpy from one location to another.</div><div class='add'>+ *</div><div class='add'>+ * Rebinds after runtime eviction</div><div class='add'>+ * ------------------------------</div><div class='add'>+ *</div><div class='add'>+ * When BOs are moved, every mapping (VMA) of the BO needs to rebound before</div><div class='add'>+ * the BO is used again. Every VMA is added to an evicted list of its VM when</div><div class='add'>+ * the BO is moved. This is safe because of the VM locking structure (TODO: link</div><div class='add'>+ * to VM locking doc). On the next use of a VM (exec or compute mode rebind</div><div class='add'>+ * worker) the evicted VMA list is checked and rebinds are triggered. In the</div><div class='add'>+ * case of faulting VM, the rebind is done in the page fault handler.</div><div class='add'>+ *</div><div class='add'>+ * Suspend / resume eviction of VRAM</div><div class='add'>+ * ---------------------------------</div><div class='add'>+ *</div><div class='add'>+ * During device suspend / resume VRAM may lose power which means the contents</div><div class='add'>+ * of VRAM's memory is blown away. Thus BOs present in VRAM at the time of</div><div class='add'>+ * suspend must be moved to sysmem in order for their contents to be saved.</div><div class='add'>+ *</div><div class='add'>+ * A simple TTM call (ttm_resource_manager_evict_all) can move all non-pinned</div><div class='add'>+ * (user) BOs to sysmem. External BOs that are pinned need to be manually</div><div class='add'>+ * evicted with a simple loop + xe_bo_evict call. It gets a little trickier</div><div class='add'>+ * with kernel BOs.</div><div class='add'>+ *</div><div class='add'>+ * Some kernel BOs are used by the GT migration engine to do moves, thus we</div><div class='add'>+ * can't move all of the BOs via the GT migration engine. For simplity, use a</div><div class='add'>+ * TTM memcpy (CPU) to move any kernel (pinned) BO on either suspend or resume.</div><div class='add'>+ *</div><div class='add'>+ * Some kernel BOs need to be restored to the exact same physical location. TTM</div><div class='add'>+ * makes this rather easy but the caveat is the memory must be contiguous. Again</div><div class='add'>+ * for simplity, we enforce that all kernel (pinned) BOs are contiguous and</div><div class='add'>+ * restored to the same physical location.</div><div class='add'>+ *</div><div class='add'>+ * Pinned external BOs in VRAM are restored on resume via the GPU.</div><div class='add'>+ *</div><div class='add'>+ * Rebinds after suspend / resume</div><div class='add'>+ * ------------------------------</div><div class='add'>+ *</div><div class='add'>+ * Most kernel BOs have GGTT mappings which must be restored during the resume</div><div class='add'>+ * process. All user BOs are rebound after validation on their next use.</div><div class='add'>+ *</div><div class='add'>+ * Future work</div><div class='add'>+ * ===========</div><div class='add'>+ *</div><div class='add'>+ * Trim the list of BOs which is saved / restored via TTM memcpy on suspend /</div><div class='add'>+ * resume. All we really need to save / restore via TTM memcpy is the memory</div><div class='add'>+ * required for the GuC to load and the memory for the GT migrate engine to</div><div class='add'>+ * operate.</div><div class='add'>+ *</div><div class='add'>+ * Do not require kernel BOs to be contiguous in physical memory / restored to</div><div class='add'>+ * the same physical address on resume. In all likelihood the only memory that</div><div class='add'>+ * needs to be restored to the same physical address is memory used for page</div><div class='add'>+ * tables. All of that memory is allocated 1 page at time so the contiguous</div><div class='add'>+ * requirement isn't needed. Some work on the vmap code would need to be done if</div><div class='add'>+ * kernel BOs are not contiguous too.</div><div class='add'>+ *</div><div class='add'>+ * Make some kernel BO evictable rather than pinned. An example of this would be</div><div class='add'>+ * engine state, in all likelihood if the dma-slots of these BOs where properly</div><div class='add'>+ * used rather than pinning we could safely evict + rebind these BOs as needed.</div><div class='add'>+ *</div><div class='add'>+ * Some kernel BOs do not need to be restored on resume (e.g. GuC ADS as that is</div><div class='add'>+ * repopulated on resume), add flag to mark such objects as no save / restore.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo_evict.c b/drivers/gpu/drm/xe/xe_bo_evict.c<br/>new file mode 100644<br/>index 000000000000..7a264a9ca06e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo_evict.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_evict.c</a></div><div class='hunk'>@@ -0,0 +1,228 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_bo_evict.h"</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_evict_all - evict all BOs from VRAM</div><div class='add'>+ *</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ *</div><div class='add'>+ * Evict non-pinned user BOs first (via GPU), evict pinned external BOs next</div><div class='add'>+ * (via GPU), wait for evictions, and finally evict pinned kernel BOs via CPU.</div><div class='add'>+ * All eviction magic done via TTM calls.</div><div class='add'>+ *</div><div class='add'>+ * Evict == move VRAM BOs to temporary (typically system) memory.</div><div class='add'>+ *</div><div class='add'>+ * This function should be called before the device goes into a suspend state</div><div class='add'>+ * where the VRAM loses power.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_evict_all(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct ttm_device *bdev = &amp;xe-&gt;ttm;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct list_head still_in_list;</div><div class='add'>+	u32 mem_type;</div><div class='add'>+	u8 id;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* User memory */</div><div class='add'>+	for (mem_type = XE_PL_VRAM0; mem_type &lt;= XE_PL_VRAM1; ++mem_type) {</div><div class='add'>+		struct ttm_resource_manager *man =</div><div class='add'>+			ttm_manager_type(bdev, mem_type);</div><div class='add'>+</div><div class='add'>+		if (man) {</div><div class='add'>+			ret = ttm_resource_manager_evict_all(bdev, man);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Pinned user memory in VRAM */</div><div class='add'>+	INIT_LIST_HEAD(&amp;still_in_list);</div><div class='add'>+	spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	for (;;) {</div><div class='add'>+		bo = list_first_entry_or_null(&amp;xe-&gt;pinned.external_vram,</div><div class='add'>+					      typeof(*bo), pinned_link);</div><div class='add'>+		if (!bo)</div><div class='add'>+			break;</div><div class='add'>+		xe_bo_get(bo);</div><div class='add'>+		list_move_tail(&amp;bo-&gt;pinned_link, &amp;still_in_list);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		ret = xe_bo_evict_pinned(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		if (ret) {</div><div class='add'>+			spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			list_splice_tail(&amp;still_in_list,</div><div class='add'>+					 &amp;xe-&gt;pinned.external_vram);</div><div class='add'>+			spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	}</div><div class='add'>+	list_splice_tail(&amp;still_in_list, &amp;xe-&gt;pinned.external_vram);</div><div class='add'>+	spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wait for all user BO to be evicted as those evictions depend on the</div><div class='add'>+	 * memory moved below.</div><div class='add'>+	 */</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_tile_migrate_wait(tile);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	for (;;) {</div><div class='add'>+		bo = list_first_entry_or_null(&amp;xe-&gt;pinned.kernel_bo_present,</div><div class='add'>+					      typeof(*bo), pinned_link);</div><div class='add'>+		if (!bo)</div><div class='add'>+			break;</div><div class='add'>+		xe_bo_get(bo);</div><div class='add'>+		list_move_tail(&amp;bo-&gt;pinned_link, &amp;xe-&gt;pinned.evicted);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		ret = xe_bo_evict_pinned(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_restore_kernel - restore kernel BOs to VRAM</div><div class='add'>+ *</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ *</div><div class='add'>+ * Move kernel BOs from temporary (typically system) memory to VRAM via CPU. All</div><div class='add'>+ * moves done via TTM calls.</div><div class='add'>+ *</div><div class='add'>+ * This function should be called early, before trying to init the GT, on device</div><div class='add'>+ * resume.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_restore_kernel(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	for (;;) {</div><div class='add'>+		bo = list_first_entry_or_null(&amp;xe-&gt;pinned.evicted,</div><div class='add'>+					      typeof(*bo), pinned_link);</div><div class='add'>+		if (!bo)</div><div class='add'>+			break;</div><div class='add'>+		xe_bo_get(bo);</div><div class='add'>+		list_move_tail(&amp;bo-&gt;pinned_link, &amp;xe-&gt;pinned.kernel_bo_present);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		ret = xe_bo_restore_pinned(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		if (ret) {</div><div class='add'>+			xe_bo_put(bo);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (bo-&gt;flags &amp; XE_BO_CREATE_GGTT_BIT) {</div><div class='add'>+			struct xe_tile *tile = bo-&gt;tile;</div><div class='add'>+</div><div class='add'>+			mutex_lock(&amp;tile-&gt;mem.ggtt-&gt;lock);</div><div class='add'>+			xe_ggtt_map_bo(tile-&gt;mem.ggtt, bo);</div><div class='add'>+			mutex_unlock(&amp;tile-&gt;mem.ggtt-&gt;lock);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * We expect validate to trigger a move VRAM and our move code</div><div class='add'>+		 * should setup the iosys map.</div><div class='add'>+		 */</div><div class='add'>+		xe_assert(xe, !iosys_map_is_null(&amp;bo-&gt;vmap));</div><div class='add'>+		xe_assert(xe, xe_bo_is_vram(bo));</div><div class='add'>+</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_bo_restore_user - restore pinned user BOs to VRAM</div><div class='add'>+ *</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ *</div><div class='add'>+ * Move pinned user BOs from temporary (typically system) memory to VRAM via</div><div class='add'>+ * CPU. All moves done via TTM calls.</div><div class='add'>+ *</div><div class='add'>+ * This function should be called late, after GT init, on device resume.</div><div class='add'>+ */</div><div class='add'>+int xe_bo_restore_user(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct list_head still_in_list;</div><div class='add'>+	u8 id;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Pinned user memory in VRAM should be validated on resume */</div><div class='add'>+	INIT_LIST_HEAD(&amp;still_in_list);</div><div class='add'>+	spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	for (;;) {</div><div class='add'>+		bo = list_first_entry_or_null(&amp;xe-&gt;pinned.external_vram,</div><div class='add'>+					      typeof(*bo), pinned_link);</div><div class='add'>+		if (!bo)</div><div class='add'>+			break;</div><div class='add'>+		list_move_tail(&amp;bo-&gt;pinned_link, &amp;still_in_list);</div><div class='add'>+		xe_bo_get(bo);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+		xe_bo_lock(bo, false);</div><div class='add'>+		ret = xe_bo_restore_pinned(bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+		if (ret) {</div><div class='add'>+			spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			list_splice_tail(&amp;still_in_list,</div><div class='add'>+					 &amp;xe-&gt;pinned.external_vram);</div><div class='add'>+			spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	}</div><div class='add'>+	list_splice_tail(&amp;still_in_list, &amp;xe-&gt;pinned.external_vram);</div><div class='add'>+	spin_unlock(&amp;xe-&gt;pinned.lock);</div><div class='add'>+</div><div class='add'>+	/* Wait for validate to complete */</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_tile_migrate_wait(tile);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo_evict.h b/drivers/gpu/drm/xe/xe_bo_evict.h<br/>new file mode 100644<br/>index 000000000000..746894798852<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo_evict.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_evict.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BO_EVICT_H_</div><div class='add'>+#define _XE_BO_EVICT_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+int xe_bo_evict_all(struct xe_device *xe);</div><div class='add'>+int xe_bo_restore_kernel(struct xe_device *xe);</div><div class='add'>+int xe_bo_restore_user(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h<br/>new file mode 100644<br/>index 000000000000..64c2249a4e40<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_bo_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_bo_types.h</a></div><div class='hunk'>@@ -0,0 +1,96 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_BO_TYPES_H_</div><div class='add'>+#define _XE_BO_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iosys-map.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_bo.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_device.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_execbuf_util.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+#define XE_BO_MAX_PLACEMENTS	3</div><div class='add'>+</div><div class='add'>+/* TODO: To be selected with VM_MADVISE */</div><div class='add'>+#define	XE_BO_PRIORITY_NORMAL	1</div><div class='add'>+</div><div class='add'>+/** @xe_bo: XE buffer object */</div><div class='add'>+struct xe_bo {</div><div class='add'>+	/** @ttm: TTM base buffer object */</div><div class='add'>+	struct ttm_buffer_object ttm;</div><div class='add'>+	/** @size: Size of this buffer object */</div><div class='add'>+	size_t size;</div><div class='add'>+	/** @flags: flags for this buffer object */</div><div class='add'>+	u32 flags;</div><div class='add'>+	/** @vm: VM this BO is attached to, for extobj this will be NULL */</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	/** @tile: Tile this BO is attached to (kernel BO only) */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	/** @placements: valid placements for this BO */</div><div class='add'>+	struct ttm_place placements[XE_BO_MAX_PLACEMENTS];</div><div class='add'>+	/** @placement: current placement for this BO */</div><div class='add'>+	struct ttm_placement placement;</div><div class='add'>+	/** @ggtt_node: GGTT node if this BO is mapped in the GGTT */</div><div class='add'>+	struct drm_mm_node ggtt_node;</div><div class='add'>+	/** @vmap: iosys map of this buffer */</div><div class='add'>+	struct iosys_map vmap;</div><div class='add'>+	/** @ttm_kmap: TTM bo kmap object for internal use only. Keep off. */</div><div class='add'>+	struct ttm_bo_kmap_obj kmap;</div><div class='add'>+	/** @pinned_link: link to present / evicted list of pinned BO */</div><div class='add'>+	struct list_head pinned_link;</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	/**</div><div class='add'>+	 * @client: @xe_drm_client which created the bo</div><div class='add'>+	 */</div><div class='add'>+	struct xe_drm_client *client;</div><div class='add'>+	/**</div><div class='add'>+	 * @client_link: Link into @xe_drm_client.objects_list</div><div class='add'>+	 */</div><div class='add'>+	struct list_head client_link;</div><div class='add'>+#endif</div><div class='add'>+	/** @props: BO user controlled properties */</div><div class='add'>+	struct {</div><div class='add'>+		/** @preferred_mem: preferred memory class for this BO */</div><div class='add'>+		s16 preferred_mem_class;</div><div class='add'>+		/** @prefered_gt: preferred GT for this BO */</div><div class='add'>+		s16 preferred_gt;</div><div class='add'>+		/** @preferred_mem_type: preferred memory type */</div><div class='add'>+		s32 preferred_mem_type;</div><div class='add'>+		/**</div><div class='add'>+		 * @cpu_atomic: the CPU expects to do atomics operations to</div><div class='add'>+		 * this BO</div><div class='add'>+		 */</div><div class='add'>+		bool cpu_atomic;</div><div class='add'>+		/**</div><div class='add'>+		 * @device_atomic: the device expects to do atomics operations</div><div class='add'>+		 * to this BO</div><div class='add'>+		 */</div><div class='add'>+		bool device_atomic;</div><div class='add'>+	} props;</div><div class='add'>+	/** @freed: List node for delayed put. */</div><div class='add'>+	struct llist_node freed;</div><div class='add'>+	/** @created: Whether the bo has passed initial creation */</div><div class='add'>+	bool created;</div><div class='add'>+</div><div class='add'>+	/** @ccs_cleared */</div><div class='add'>+	bool ccs_cleared;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @cpu_caching: CPU caching mode. Currently only used for userspace</div><div class='add'>+	 * objects.</div><div class='add'>+	 */</div><div class='add'>+	u16 cpu_caching;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define intel_bo_to_drm_bo(bo) (&amp;(bo)-&gt;ttm.base)</div><div class='add'>+#define intel_bo_to_i915(bo) to_i915(intel_bo_to_drm_bo(bo)-&gt;dev)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c<br/>new file mode 100644<br/>index 000000000000..c56fd7d59f05<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,148 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_debugfs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/string_helpers.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_debugfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt_debugfs.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_XE_DEBUG</div><div class='add'>+#include "xe_bo_evict.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_FAULT_INJECTION</div><div class='add'>+#include &lt;linux/fault-inject.h&gt; /* XXX: fault-inject.h is broken */</div><div class='add'>+DECLARE_FAULT_ATTR(gt_reset_failure);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static struct xe_device *node_to_xe(struct drm_info_node *node)</div><div class='add'>+{</div><div class='add'>+	return to_xe_device(node-&gt;minor-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int info(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = node_to_xe(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "graphics_verx100 %d\n", xe-&gt;info.graphics_verx100);</div><div class='add'>+	drm_printf(&amp;p, "media_verx100 %d\n", xe-&gt;info.media_verx100);</div><div class='add'>+	drm_printf(&amp;p, "stepping G:%s M:%s D:%s B:%s\n",</div><div class='add'>+		   xe_step_name(xe-&gt;info.step.graphics),</div><div class='add'>+		   xe_step_name(xe-&gt;info.step.media),</div><div class='add'>+		   xe_step_name(xe-&gt;info.step.display),</div><div class='add'>+		   xe_step_name(xe-&gt;info.step.basedie));</div><div class='add'>+	drm_printf(&amp;p, "is_dgfx %s\n", str_yes_no(xe-&gt;info.is_dgfx));</div><div class='add'>+	drm_printf(&amp;p, "platform %d\n", xe-&gt;info.platform);</div><div class='add'>+	drm_printf(&amp;p, "subplatform %d\n",</div><div class='add'>+		   xe-&gt;info.subplatform &gt; XE_SUBPLATFORM_NONE ? xe-&gt;info.subplatform : 0);</div><div class='add'>+	drm_printf(&amp;p, "devid 0x%x\n", xe-&gt;info.devid);</div><div class='add'>+	drm_printf(&amp;p, "revid %d\n", xe-&gt;info.revid);</div><div class='add'>+	drm_printf(&amp;p, "tile_count %d\n", xe-&gt;info.tile_count);</div><div class='add'>+	drm_printf(&amp;p, "vm_max_level %d\n", xe-&gt;info.vm_max_level);</div><div class='add'>+	drm_printf(&amp;p, "force_execlist %s\n", str_yes_no(xe-&gt;info.force_execlist));</div><div class='add'>+	drm_printf(&amp;p, "has_flat_ccs %s\n", str_yes_no(xe-&gt;info.has_flat_ccs));</div><div class='add'>+	drm_printf(&amp;p, "has_usm %s\n", str_yes_no(xe-&gt;info.has_usm));</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		drm_printf(&amp;p, "gt%d force wake %d\n", id,</div><div class='add'>+			   xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));</div><div class='add'>+		drm_printf(&amp;p, "gt%d engine_mask 0x%llx\n", id,</div><div class='add'>+			   gt-&gt;info.engine_mask);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_info_list debugfs_list[] = {</div><div class='add'>+	{"info", info, 0},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int forcewake_open(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = inode-&gt;i_private;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int forcewake_release(struct inode *inode, struct file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = inode-&gt;i_private;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations forcewake_all_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = forcewake_open,</div><div class='add'>+	.release = forcewake_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_debugfs_register(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct ttm_device *bdev = &amp;xe-&gt;ttm;</div><div class='add'>+	struct drm_minor *minor = xe-&gt;drm.primary;</div><div class='add'>+	struct dentry *root = minor-&gt;debugfs_root;</div><div class='add'>+	struct ttm_resource_manager *man;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u32 mem_type;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	drm_debugfs_create_files(debugfs_list,</div><div class='add'>+				 ARRAY_SIZE(debugfs_list),</div><div class='add'>+				 root, minor);</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("forcewake_all", 0400, root, xe,</div><div class='add'>+			    &amp;forcewake_all_fops);</div><div class='add'>+</div><div class='add'>+	for (mem_type = XE_PL_VRAM0; mem_type &lt;= XE_PL_VRAM1; ++mem_type) {</div><div class='add'>+		man = ttm_manager_type(bdev, mem_type);</div><div class='add'>+</div><div class='add'>+		if (man) {</div><div class='add'>+			char name[16];</div><div class='add'>+</div><div class='add'>+			sprintf(name, "vram%d_mm", mem_type - XE_PL_VRAM0);</div><div class='add'>+			ttm_resource_manager_create_debugfs(man, root, name);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	man = ttm_manager_type(bdev, XE_PL_TT);</div><div class='add'>+	ttm_resource_manager_create_debugfs(man, root, "gtt_mm");</div><div class='add'>+</div><div class='add'>+	man = ttm_manager_type(bdev, XE_PL_STOLEN);</div><div class='add'>+	if (man)</div><div class='add'>+		ttm_resource_manager_create_debugfs(man, root, "stolen_mm");</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_gt_debugfs_register(gt);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_FAULT_INJECTION</div><div class='add'>+	fault_create_debugfs_attr("fail_gt_reset", root, &amp;gt_reset_failure);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_debugfs.h b/drivers/gpu/drm/xe/xe_debugfs.h<br/>new file mode 100644<br/>index 000000000000..715b8e2e0bd9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEBUGFS_H_</div><div class='add'>+#define _XE_DEBUGFS_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+void xe_debugfs_register(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c<br/>new file mode 100644<br/>index 000000000000..68abc0b195be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_devcoredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump.c</a></div><div class='hunk'>@@ -0,0 +1,196 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_devcoredump.h"</div><div class='add'>+#include "xe_devcoredump_types.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/devcoredump.h&gt;</div><div class='add'>+#include &lt;generated/utsrelease.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_guc_submit.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe device coredump</div><div class='add'>+ *</div><div class='add'>+ * Devices overview:</div><div class='add'>+ * Xe uses dev_coredump infrastructure for exposing the crash errors in a</div><div class='add'>+ * standardized way.</div><div class='add'>+ * devcoredump exposes a temporary device under /sys/class/devcoredump/</div><div class='add'>+ * which is linked with our card device directly.</div><div class='add'>+ * The core dump can be accessed either from</div><div class='add'>+ * /sys/class/drm/card&lt;n&gt;/device/devcoredump/ or from</div><div class='add'>+ * /sys/class/devcoredump/devcd&lt;m&gt; where</div><div class='add'>+ * /sys/class/devcoredump/devcd&lt;m&gt;/failing_device is a link to</div><div class='add'>+ * /sys/class/drm/card&lt;n&gt;/device/.</div><div class='add'>+ *</div><div class='add'>+ * Snapshot at hang:</div><div class='add'>+ * The 'data' file is printed with a drm_printer pointer at devcoredump read</div><div class='add'>+ * time. For this reason, we need to take snapshots from when the hang has</div><div class='add'>+ * happened, and not only when the user is reading the file. Otherwise the</div><div class='add'>+ * information is outdated since the resets might have happened in between.</div><div class='add'>+ *</div><div class='add'>+ * 'First' failure snapshot:</div><div class='add'>+ * In general, the first hang is the most critical one since the following hangs</div><div class='add'>+ * can be a consequence of the initial hang. For this reason we only take the</div><div class='add'>+ * snapshot of the 'first' failure and ignore subsequent calls of this function,</div><div class='add'>+ * at least while the coredump device is alive. Dev_coredump has a delayed work</div><div class='add'>+ * queue that will eventually delete the device and free all the dump</div><div class='add'>+ * information.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DEV_COREDUMP</div><div class='add'>+</div><div class='add'>+static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump)</div><div class='add'>+{</div><div class='add'>+	return container_of(coredump, struct xe_device, devcoredump);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_guc *exec_queue_to_guc(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return &amp;q-&gt;gt-&gt;uc.guc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t xe_devcoredump_read(char *buffer, loff_t offset,</div><div class='add'>+				   size_t count, void *data, size_t datalen)</div><div class='add'>+{</div><div class='add'>+	struct xe_devcoredump *coredump = data;</div><div class='add'>+	struct xe_devcoredump_snapshot *ss;</div><div class='add'>+	struct drm_printer p;</div><div class='add'>+	struct drm_print_iterator iter;</div><div class='add'>+	struct timespec64 ts;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Our device is gone already... */</div><div class='add'>+	if (!data || !coredump_to_xe(coredump))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	iter.data = buffer;</div><div class='add'>+	iter.offset = 0;</div><div class='add'>+	iter.start = offset;</div><div class='add'>+	iter.remain = count;</div><div class='add'>+</div><div class='add'>+	ss = &amp;coredump-&gt;snapshot;</div><div class='add'>+	p = drm_coredump_printer(&amp;iter);</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "**** Xe Device Coredump ****\n");</div><div class='add'>+	drm_printf(&amp;p, "kernel: " UTS_RELEASE "\n");</div><div class='add'>+	drm_printf(&amp;p, "module: " KBUILD_MODNAME "\n");</div><div class='add'>+</div><div class='add'>+	ts = ktime_to_timespec64(ss-&gt;snapshot_time);</div><div class='add'>+	drm_printf(&amp;p, "Snapshot time: %lld.%09ld\n", ts.tv_sec, ts.tv_nsec);</div><div class='add'>+	ts = ktime_to_timespec64(ss-&gt;boot_time);</div><div class='add'>+	drm_printf(&amp;p, "Uptime: %lld.%09ld\n", ts.tv_sec, ts.tv_nsec);</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "\n**** GuC CT ****\n");</div><div class='add'>+	xe_guc_ct_snapshot_print(coredump-&gt;snapshot.ct, &amp;p);</div><div class='add'>+	xe_guc_exec_queue_snapshot_print(coredump-&gt;snapshot.ge, &amp;p);</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "\n**** HW Engines ****\n");</div><div class='add'>+	for (i = 0; i &lt; XE_NUM_HW_ENGINES; i++)</div><div class='add'>+		if (coredump-&gt;snapshot.hwe[i])</div><div class='add'>+			xe_hw_engine_snapshot_print(coredump-&gt;snapshot.hwe[i],</div><div class='add'>+						    &amp;p);</div><div class='add'>+</div><div class='add'>+	return count - iter.remain;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_devcoredump_free(void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_devcoredump *coredump = data;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Our device is gone. Nothing to do... */</div><div class='add'>+	if (!data || !coredump_to_xe(coredump))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_snapshot_free(coredump-&gt;snapshot.ct);</div><div class='add'>+	xe_guc_exec_queue_snapshot_free(coredump-&gt;snapshot.ge);</div><div class='add'>+	for (i = 0; i &lt; XE_NUM_HW_ENGINES; i++)</div><div class='add'>+		if (coredump-&gt;snapshot.hwe[i])</div><div class='add'>+			xe_hw_engine_snapshot_free(coredump-&gt;snapshot.hwe[i]);</div><div class='add'>+</div><div class='add'>+	coredump-&gt;captured = false;</div><div class='add'>+	drm_info(&amp;coredump_to_xe(coredump)-&gt;drm,</div><div class='add'>+		 "Xe device coredump has been deleted.\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void devcoredump_snapshot(struct xe_devcoredump *coredump,</div><div class='add'>+				 struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_devcoredump_snapshot *ss = &amp;coredump-&gt;snapshot;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 adj_logical_mask = q-&gt;logical_mask;</div><div class='add'>+	u32 width_mask = (0x1 &lt;&lt; q-&gt;width) - 1;</div><div class='add'>+	int i;</div><div class='add'>+	bool cookie;</div><div class='add'>+</div><div class='add'>+	ss-&gt;snapshot_time = ktime_get_real();</div><div class='add'>+	ss-&gt;boot_time = ktime_get_boottime();</div><div class='add'>+</div><div class='add'>+	cookie = dma_fence_begin_signalling();</div><div class='add'>+	for (i = 0; q-&gt;width &gt; 1 &amp;&amp; i &lt; XE_HW_ENGINE_MAX_INSTANCE;) {</div><div class='add'>+		if (adj_logical_mask &amp; BIT(i)) {</div><div class='add'>+			adj_logical_mask |= width_mask &lt;&lt; i;</div><div class='add'>+			i += q-&gt;width;</div><div class='add'>+		} else {</div><div class='add'>+			++i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_force_wake_get(gt_to_fw(q-&gt;gt), XE_FORCEWAKE_ALL);</div><div class='add'>+</div><div class='add'>+	coredump-&gt;snapshot.ct = xe_guc_ct_snapshot_capture(&amp;guc-&gt;ct, true);</div><div class='add'>+	coredump-&gt;snapshot.ge = xe_guc_exec_queue_snapshot_capture(q);</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, q-&gt;gt, id) {</div><div class='add'>+		if (hwe-&gt;class != q-&gt;hwe-&gt;class ||</div><div class='add'>+		    !(BIT(hwe-&gt;logical_instance) &amp; adj_logical_mask)) {</div><div class='add'>+			coredump-&gt;snapshot.hwe[id] = NULL;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+		coredump-&gt;snapshot.hwe[id] = xe_hw_engine_snapshot_capture(hwe);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_force_wake_put(gt_to_fw(q-&gt;gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	dma_fence_end_signalling(cookie);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_devcoredump - Take the required snapshots and initialize coredump device.</div><div class='add'>+ * @q: The faulty xe_exec_queue, where the issue was detected.</div><div class='add'>+ *</div><div class='add'>+ * This function should be called at the crash time within the serialized</div><div class='add'>+ * gt_reset. It is skipped if we still have the core dump device available</div><div class='add'>+ * with the information of the 'first' snapshot.</div><div class='add'>+ */</div><div class='add'>+void xe_devcoredump(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(q-&gt;gt);</div><div class='add'>+	struct xe_devcoredump *coredump = &amp;xe-&gt;devcoredump;</div><div class='add'>+</div><div class='add'>+	if (coredump-&gt;captured) {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Multiple hangs are occurring, but only the first snapshot was taken\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	coredump-&gt;captured = true;</div><div class='add'>+	devcoredump_snapshot(coredump, q);</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Xe device coredump has been created\n");</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Check your /sys/class/drm/card%d/device/devcoredump/data\n",</div><div class='add'>+		 xe-&gt;drm.primary-&gt;index);</div><div class='add'>+</div><div class='add'>+	dev_coredumpm(xe-&gt;drm.dev, THIS_MODULE, coredump, 0, GFP_KERNEL,</div><div class='add'>+		      xe_devcoredump_read, xe_devcoredump_free);</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_devcoredump.h b/drivers/gpu/drm/xe/xe_devcoredump.h<br/>new file mode 100644<br/>index 000000000000..6ac218a5c194<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_devcoredump.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump.h</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEVCOREDUMP_H_</div><div class='add'>+#define _XE_DEVCOREDUMP_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DEV_COREDUMP</div><div class='add'>+void xe_devcoredump(struct xe_exec_queue *q);</div><div class='add'>+#else</div><div class='add'>+static inline void xe_devcoredump(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h<br/>new file mode 100644<br/>index 000000000000..7fdad9c3d3dd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_devcoredump_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_devcoredump_types.h</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEVCOREDUMP_TYPES_H_</div><div class='add'>+#define _XE_DEVCOREDUMP_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/ktime.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_devcoredump_snapshot - Crash snapshot</div><div class='add'>+ *</div><div class='add'>+ * This struct contains all the useful information quickly captured at the time</div><div class='add'>+ * of the crash. So, any subsequent reads of the coredump points to a data that</div><div class='add'>+ * shows the state of the GPU of when the issue has happened.</div><div class='add'>+ */</div><div class='add'>+struct xe_devcoredump_snapshot {</div><div class='add'>+	/** @snapshot_time:  Time of this capture. */</div><div class='add'>+	ktime_t snapshot_time;</div><div class='add'>+	/** @boot_time:  Relative boot time so the uptime can be calculated. */</div><div class='add'>+	ktime_t boot_time;</div><div class='add'>+</div><div class='add'>+	/* GuC snapshots */</div><div class='add'>+	/** @ct: GuC CT snapshot */</div><div class='add'>+	struct xe_guc_ct_snapshot *ct;</div><div class='add'>+	/** @ge: Guc Engine snapshot */</div><div class='add'>+	struct xe_guc_submit_exec_queue_snapshot *ge;</div><div class='add'>+	/** @hwe: HW Engine snapshot array */</div><div class='add'>+	struct xe_hw_engine_snapshot *hwe[XE_NUM_HW_ENGINES];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_devcoredump - Xe devcoredump main structure</div><div class='add'>+ *</div><div class='add'>+ * This struct represents the live and active dev_coredump node.</div><div class='add'>+ * It is created/populated at the time of a crash/error. Then it</div><div class='add'>+ * is read later when user access the device coredump data file</div><div class='add'>+ * for reading the information.</div><div class='add'>+ */</div><div class='add'>+struct xe_devcoredump {</div><div class='add'>+	/** @xe: Xe device. */</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	/** @captured: The snapshot of the first hang has already been taken. */</div><div class='add'>+	bool captured;</div><div class='add'>+	/** @snapshot: Snapshot is captured at time of the first crash */</div><div class='add'>+	struct xe_devcoredump_snapshot snapshot;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c<br/>new file mode 100644<br/>index 000000000000..b8d8da546670<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device.c</a></div><div class='hunk'>@@ -0,0 +1,700 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_aperture.h&gt;</div><div class='add'>+#include &lt;drm/drm_atomic_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_gem_ttm_helper.h&gt;</div><div class='add'>+#include &lt;drm/drm_ioctl.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_debugfs.h"</div><div class='add'>+#include "xe_display.h"</div><div class='add'>+#include "xe_dma_buf.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_drv.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_exec.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_irq.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+#include "xe_pat.h"</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_query.h"</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+#include "xe_ttm_sys_mgr.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+#include "xe_wait_user_fence.h"</div><div class='add'>+#include "xe_hwmon.h"</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_LOCKDEP</div><div class='add'>+struct lockdep_map xe_device_mem_access_lockdep_map = {</div><div class='add'>+	.name = "xe_device_mem_access_lockdep_map"</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static int xe_file_open(struct drm_device *dev, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_drm_client *client;</div><div class='add'>+	struct xe_file *xef;</div><div class='add'>+	int ret = -ENOMEM;</div><div class='add'>+</div><div class='add'>+	xef = kzalloc(sizeof(*xef), GFP_KERNEL);</div><div class='add'>+	if (!xef)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	client = xe_drm_client_alloc();</div><div class='add'>+	if (!client) {</div><div class='add'>+		kfree(xef);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xef-&gt;drm = file;</div><div class='add'>+	xef-&gt;client = client;</div><div class='add'>+	xef-&gt;xe = xe;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;xef-&gt;vm.lock);</div><div class='add'>+	xa_init_flags(&amp;xef-&gt;vm.xa, XA_FLAGS_ALLOC1);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	xa_init_flags(&amp;xef-&gt;exec_queue.xa, XA_FLAGS_ALLOC1);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;clients.lock);</div><div class='add'>+	xe-&gt;clients.count++;</div><div class='add'>+	spin_unlock(&amp;xe-&gt;clients.lock);</div><div class='add'>+</div><div class='add'>+	file-&gt;driver_priv = xef;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void device_kill_persistent_exec_queues(struct xe_device *xe,</div><div class='add'>+					       struct xe_file *xef);</div><div class='add'>+</div><div class='add'>+static void xe_file_close(struct drm_device *dev, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = file-&gt;driver_priv;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	unsigned long idx;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	xa_for_each(&amp;xef-&gt;exec_queue.xa, idx, q) {</div><div class='add'>+		xe_exec_queue_kill(q);</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	xa_destroy(&amp;xef-&gt;exec_queue.xa);</div><div class='add'>+	mutex_destroy(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	device_kill_persistent_exec_queues(xe, xef);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	xa_for_each(&amp;xef-&gt;vm.xa, idx, vm)</div><div class='add'>+		xe_vm_close_and_put(vm);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	xa_destroy(&amp;xef-&gt;vm.xa);</div><div class='add'>+	mutex_destroy(&amp;xef-&gt;vm.lock);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;clients.lock);</div><div class='add'>+	xe-&gt;clients.count--;</div><div class='add'>+	spin_unlock(&amp;xe-&gt;clients.lock);</div><div class='add'>+</div><div class='add'>+	xe_drm_client_put(xef-&gt;client);</div><div class='add'>+	kfree(xef);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_ioctl_desc xe_ioctls[] = {</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_GEM_CREATE, xe_gem_create_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_GEM_MMAP_OFFSET, xe_gem_mmap_offset_ioctl,</div><div class='add'>+			  DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl,</div><div class='add'>+			  DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl,</div><div class='add'>+			  DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl,</div><div class='add'>+			  DRM_RENDER_ALLOW),</div><div class='add'>+	DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl,</div><div class='add'>+			  DRM_RENDER_ALLOW),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct file_operations xe_driver_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = drm_open,</div><div class='add'>+	.release = drm_release_noglobal,</div><div class='add'>+	.unlocked_ioctl = drm_ioctl,</div><div class='add'>+	.mmap = drm_gem_mmap,</div><div class='add'>+	.poll = drm_poll,</div><div class='add'>+	.read = drm_read,</div><div class='add'>+	.compat_ioctl = drm_compat_ioctl,</div><div class='add'>+	.llseek = noop_llseek,</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	.show_fdinfo = drm_show_fdinfo,</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe_driver_release(struct drm_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	pci_set_drvdata(to_pci_dev(xe-&gt;drm.dev), NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct drm_driver driver = {</div><div class='add'>+	/* Don't use MTRRs here; the Xserver or userspace app should</div><div class='add'>+	 * deal with them for Intel hardware.</div><div class='add'>+	 */</div><div class='add'>+	.driver_features =</div><div class='add'>+	    DRIVER_GEM |</div><div class='add'>+	    DRIVER_RENDER | DRIVER_SYNCOBJ |</div><div class='add'>+	    DRIVER_SYNCOBJ_TIMELINE | DRIVER_GEM_GPUVA,</div><div class='add'>+	.open = xe_file_open,</div><div class='add'>+	.postclose = xe_file_close,</div><div class='add'>+</div><div class='add'>+	.gem_prime_import = xe_gem_prime_import,</div><div class='add'>+</div><div class='add'>+	.dumb_create = xe_bo_dumb_create,</div><div class='add'>+	.dumb_map_offset = drm_gem_ttm_dumb_map_offset,</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	.show_fdinfo = xe_drm_client_fdinfo,</div><div class='add'>+#endif</div><div class='add'>+	.release = &amp;xe_driver_release,</div><div class='add'>+</div><div class='add'>+	.ioctls = xe_ioctls,</div><div class='add'>+	.num_ioctls = ARRAY_SIZE(xe_ioctls),</div><div class='add'>+	.fops = &amp;xe_driver_fops,</div><div class='add'>+	.name = DRIVER_NAME,</div><div class='add'>+	.desc = DRIVER_DESC,</div><div class='add'>+	.date = DRIVER_DATE,</div><div class='add'>+	.major = DRIVER_MAJOR,</div><div class='add'>+	.minor = DRIVER_MINOR,</div><div class='add'>+	.patchlevel = DRIVER_PATCHLEVEL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe_device_destroy(struct drm_device *dev, void *dummy)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;ordered_wq)</div><div class='add'>+		destroy_workqueue(xe-&gt;ordered_wq);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;unordered_wq)</div><div class='add'>+		destroy_workqueue(xe-&gt;unordered_wq);</div><div class='add'>+</div><div class='add'>+	ttm_device_fini(&amp;xe-&gt;ttm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_device *xe_device_create(struct pci_dev *pdev,</div><div class='add'>+				   const struct pci_device_id *ent)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_display_driver_set_hooks(&amp;driver);</div><div class='add'>+</div><div class='add'>+	err = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amp;driver);</div><div class='add'>+	if (err)</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+	xe = devm_drm_dev_alloc(&amp;pdev-&gt;dev, &amp;driver, struct xe_device, drm);</div><div class='add'>+	if (IS_ERR(xe))</div><div class='add'>+		return xe;</div><div class='add'>+</div><div class='add'>+	err = ttm_device_init(&amp;xe-&gt;ttm, &amp;xe_ttm_funcs, xe-&gt;drm.dev,</div><div class='add'>+			      xe-&gt;drm.anon_inode-&gt;i_mapping,</div><div class='add'>+			      xe-&gt;drm.vma_offset_manager, false, false);</div><div class='add'>+	if (WARN_ON(err))</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_device_destroy, NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.devid = pdev-&gt;device;</div><div class='add'>+	xe-&gt;info.revid = pdev-&gt;revision;</div><div class='add'>+	xe-&gt;info.force_execlist = xe_modparam.force_execlist;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;xe-&gt;irq.lock);</div><div class='add'>+	spin_lock_init(&amp;xe-&gt;clients.lock);</div><div class='add'>+</div><div class='add'>+	init_waitqueue_head(&amp;xe-&gt;ufence_wq);</div><div class='add'>+</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;usm.lock);</div><div class='add'>+	xa_init_flags(&amp;xe-&gt;usm.asid_to_vm, XA_FLAGS_ALLOC);</div><div class='add'>+</div><div class='add'>+	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {</div><div class='add'>+		/* Trigger a large asid and an early asid wrap. */</div><div class='add'>+		u32 asid;</div><div class='add'>+</div><div class='add'>+		BUILD_BUG_ON(XE_MAX_ASID &lt; 2);</div><div class='add'>+		err = xa_alloc_cyclic(&amp;xe-&gt;usm.asid_to_vm, &amp;asid, NULL,</div><div class='add'>+				      XA_LIMIT(XE_MAX_ASID - 2, XE_MAX_ASID - 1),</div><div class='add'>+				      &amp;xe-&gt;usm.next_asid, GFP_KERNEL);</div><div class='add'>+		drm_WARN_ON(&amp;xe-&gt;drm, err);</div><div class='add'>+		if (err &gt;= 0)</div><div class='add'>+			xa_erase(&amp;xe-&gt;usm.asid_to_vm, asid);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;xe-&gt;persistent_engines.list);</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;xe-&gt;pinned.lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;xe-&gt;pinned.kernel_bo_present);</div><div class='add'>+	INIT_LIST_HEAD(&amp;xe-&gt;pinned.external_vram);</div><div class='add'>+	INIT_LIST_HEAD(&amp;xe-&gt;pinned.evicted);</div><div class='add'>+</div><div class='add'>+	xe-&gt;ordered_wq = alloc_ordered_workqueue("xe-ordered-wq", 0);</div><div class='add'>+	xe-&gt;unordered_wq = alloc_workqueue("xe-unordered-wq", 0, 0);</div><div class='add'>+	if (!xe-&gt;ordered_wq || !xe-&gt;unordered_wq) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Failed to allocate xe workqueues\n");</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_display_create(xe);</div><div class='add'>+	if (WARN_ON(err))</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	return xe;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The driver-initiated FLR is the highest level of reset that we can trigger</div><div class='add'>+ * from within the driver. It is different from the PCI FLR in that it doesn't</div><div class='add'>+ * fully reset the SGUnit and doesn't modify the PCI config space and therefore</div><div class='add'>+ * it doesn't require a re-enumeration of the PCI BARs. However, the</div><div class='add'>+ * driver-initiated FLR does still cause a reset of both GT and display and a</div><div class='add'>+ * memory wipe of local and stolen memory, so recovery would require a full HW</div><div class='add'>+ * re-init and saving/restoring (or re-populating) the wiped memory. Since we</div><div class='add'>+ * perform the FLR as the very last action before releasing access to the HW</div><div class='add'>+ * during the driver release flow, we don't attempt recovery at all, because</div><div class='add'>+ * if/when a new instance of i915 is bound to the device it will do a full</div><div class='add'>+ * re-init anyway.</div><div class='add'>+ */</div><div class='add'>+static void xe_driver_flr(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	const unsigned int flr_timeout = 3 * MICRO; /* specs recommend a 3s wait */</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (xe_mmio_read32(gt, GU_CNTL_PROTECTED) &amp; DRIVERINT_FLR_DIS) {</div><div class='add'>+		drm_info_once(&amp;xe-&gt;drm, "BIOS Disabled Driver-FLR\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Triggering Driver-FLR\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Make sure any pending FLR requests have cleared by waiting for the</div><div class='add'>+	 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS</div><div class='add'>+	 * to make sure it's not still set from a prior attempt (it's a write to</div><div class='add'>+	 * clear bit).</div><div class='add'>+	 * Note that we should never be in a situation where a previous attempt</div><div class='add'>+	 * is still pending (unless the HW is totally dead), but better to be</div><div class='add'>+	 * safe in case something unexpected happens</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);</div><div class='add'>+</div><div class='add'>+	/* Trigger the actual Driver-FLR */</div><div class='add'>+	xe_mmio_rmw32(gt, GU_CNTL, 0, DRIVERFLR);</div><div class='add'>+</div><div class='add'>+	/* Wait for hardware teardown to complete */</div><div class='add'>+	ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Driver-FLR-teardown wait completion failed! %d\n", ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait for hardware/firmware re-init to complete */</div><div class='add'>+	ret = xe_mmio_wait32(gt, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,</div><div class='add'>+			     flr_timeout, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Driver-FLR-reinit wait completion failed! %d\n", ret);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Clear sticky completion status */</div><div class='add'>+	xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_driver_flr_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;needs_flr_on_fini)</div><div class='add'>+		xe_driver_flr(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_device_sanitize(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_gt_sanitize(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_set_dma_info(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	unsigned int mask_size = xe-&gt;info.dma_mask_size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	dma_set_max_seg_size(xe-&gt;drm.dev, xe_sg_segment_size(xe-&gt;drm.dev));</div><div class='add'>+</div><div class='add'>+	err = dma_set_mask(xe-&gt;drm.dev, DMA_BIT_MASK(mask_size));</div><div class='add'>+	if (err)</div><div class='add'>+		goto mask_err;</div><div class='add'>+</div><div class='add'>+	err = dma_set_coherent_mask(xe-&gt;drm.dev, DMA_BIT_MASK(mask_size));</div><div class='add'>+	if (err)</div><div class='add'>+		goto mask_err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+mask_err:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "Can't set DMA mask/consistent mask (%d)\n", err);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initialize MMIO resources that don't require any knowledge about tile count.</div><div class='add'>+ */</div><div class='add'>+int xe_device_probe_early(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_mmio_init(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_mmio_root_tile_init(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_device_set_has_flat_ccs(struct  xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	u32 reg;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VER(xe) &lt; 20 || !xe-&gt;info.has_flat_ccs)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER);</div><div class='add'>+	xe-&gt;info.has_flat_ccs = (reg &amp; XE2_FLAT_CCS_ENABLE);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.has_flat_ccs)</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+			"Flat CCS has been disabled in bios, May lead to performance impact");</div><div class='add'>+</div><div class='add'>+	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_device_probe(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	int err;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	xe_pat_init_early(xe);</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.mem_region_mask = 1;</div><div class='add'>+	err = xe_display_init_nommio(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_set_dma_info(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_mmio_probe_tiles(xe);</div><div class='add'>+</div><div class='add'>+	xe_ttm_sys_mgr_init(xe);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_force_wake_init_gt(gt, gt_to_fw(gt));</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		err = xe_ggtt_init_early(tile-&gt;mem.ggtt);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_driver_flr_fini, xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_pcode_probe(gt);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_display_init_noirq(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_irq_install(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_gt_init_early(gt);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_irq_shutdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_device_set_has_flat_ccs(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_irq_shutdown;</div><div class='add'>+</div><div class='add'>+	err = xe_mmio_probe_vram(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_irq_shutdown;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		err = xe_tile_init_noalloc(tile);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_irq_shutdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Allocate and map stolen after potential VRAM resize */</div><div class='add'>+	xe_ttm_stolen_mgr_init(xe);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Now that GT is initialized (TTM in particular),</div><div class='add'>+	 * we can try to init display, and inherit the initial fb.</div><div class='add'>+	 * This is the reason the first allocation needs to be done</div><div class='add'>+	 * inside display.</div><div class='add'>+	 */</div><div class='add'>+	err = xe_display_init_noaccel(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_irq_shutdown;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_gt_init(gt);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_irq_shutdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_heci_gsc_init(xe);</div><div class='add'>+</div><div class='add'>+	err = xe_display_init(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_irq_shutdown;</div><div class='add'>+</div><div class='add'>+	err = drm_dev_register(&amp;xe-&gt;drm, 0);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fini_display;</div><div class='add'>+</div><div class='add'>+	xe_display_register(xe);</div><div class='add'>+</div><div class='add'>+	xe_debugfs_register(xe);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_register(xe);</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_device_sanitize, xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_fini_display:</div><div class='add'>+	xe_display_driver_remove(xe);</div><div class='add'>+</div><div class='add'>+err_irq_shutdown:</div><div class='add'>+	xe_irq_shutdown(xe);</div><div class='add'>+err:</div><div class='add'>+	xe_display_fini(xe);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_device_remove_display(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xe_display_unregister(xe);</div><div class='add'>+</div><div class='add'>+	drm_dev_unplug(&amp;xe-&gt;drm);</div><div class='add'>+	xe_display_driver_remove(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_remove(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xe_device_remove_display(xe);</div><div class='add'>+</div><div class='add'>+	xe_display_fini(xe);</div><div class='add'>+</div><div class='add'>+	xe_heci_gsc_fini(xe);</div><div class='add'>+</div><div class='add'>+	xe_irq_shutdown(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_shutdown(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+	list_add_tail(&amp;q-&gt;persistent.link, &amp;xe-&gt;persistent_engines.list);</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_remove_persistent_exec_queues(struct xe_device *xe,</div><div class='add'>+					     struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+	if (!list_empty(&amp;q-&gt;persistent.link))</div><div class='add'>+		list_del(&amp;q-&gt;persistent.link);</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void device_kill_persistent_exec_queues(struct xe_device *xe,</div><div class='add'>+					       struct xe_file *xef)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q, *next;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+	list_for_each_entry_safe(q, next, &amp;xe-&gt;persistent_engines.list,</div><div class='add'>+				 persistent.link)</div><div class='add'>+		if (q-&gt;persistent.xef == xef) {</div><div class='add'>+			xe_exec_queue_kill(q);</div><div class='add'>+			list_del_init(&amp;q-&gt;persistent.link);</div><div class='add'>+		}</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;persistent_engines.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_wmb(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	wmb();</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)</div><div class='add'>+{</div><div class='add'>+	return xe_device_has_flat_ccs(xe) ?</div><div class='add'>+		DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE(xe)) : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_device_mem_access_ongoing(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (xe_pm_read_callback_task(xe) != NULL)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return atomic_read(&amp;xe-&gt;mem_access.ref);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_assert_mem_access(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(!xe_device_mem_access_ongoing(xe));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_device_mem_access_get_if_ongoing(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	bool active;</div><div class='add'>+</div><div class='add'>+	if (xe_pm_read_callback_task(xe) == current)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	active = xe_pm_runtime_get_if_active(xe);</div><div class='add'>+	if (active) {</div><div class='add'>+		int ref = atomic_inc_return(&amp;xe-&gt;mem_access.ref);</div><div class='add'>+</div><div class='add'>+		xe_assert(xe, ref != S32_MAX);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return active;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_mem_access_get(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int ref;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This looks racy, but should be fine since the pm_callback_task only</div><div class='add'>+	 * transitions from NULL -&gt; current (and back to NULL again), during the</div><div class='add'>+	 * runtime_resume() or runtime_suspend() callbacks, for which there can</div><div class='add'>+	 * only be a single one running for our device. We only need to prevent</div><div class='add'>+	 * recursively calling the runtime_get or runtime_put from those</div><div class='add'>+	 * callbacks, as well as preventing triggering any access_ongoing</div><div class='add'>+	 * asserts.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_pm_read_callback_task(xe) == current)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Since the resume here is synchronous it can be quite easy to deadlock</div><div class='add'>+	 * if we are not careful. Also in practice it might be quite timing</div><div class='add'>+	 * sensitive to ever see the 0 -&gt; 1 transition with the callers locks</div><div class='add'>+	 * held, so deadlocks might exist but are hard for lockdep to ever see.</div><div class='add'>+	 * With this in mind, help lockdep learn about the potentially scary</div><div class='add'>+	 * stuff that can happen inside the runtime_resume callback by acquiring</div><div class='add'>+	 * a dummy lock (it doesn't protect anything and gets compiled out on</div><div class='add'>+	 * non-debug builds).  Lockdep then only needs to see the</div><div class='add'>+	 * mem_access_lockdep_map -&gt; runtime_resume callback once, and then can</div><div class='add'>+	 * hopefully validate all the (callers_locks) -&gt; mem_access_lockdep_map.</div><div class='add'>+	 * For example if the (callers_locks) are ever grabbed in the</div><div class='add'>+	 * runtime_resume callback, lockdep should give us a nice splat.</div><div class='add'>+	 */</div><div class='add'>+	lock_map_acquire(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+	lock_map_release(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+</div><div class='add'>+	xe_pm_runtime_get(xe);</div><div class='add'>+	ref = atomic_inc_return(&amp;xe-&gt;mem_access.ref);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, ref != S32_MAX);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_mem_access_put(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int ref;</div><div class='add'>+</div><div class='add'>+	if (xe_pm_read_callback_task(xe) == current)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ref = atomic_dec_return(&amp;xe-&gt;mem_access.ref);</div><div class='add'>+	xe_pm_runtime_put(xe);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, ref &gt;= 0);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h<br/>new file mode 100644<br/>index 000000000000..3da83b233206<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device.h</a></div><div class='hunk'>@@ -0,0 +1,173 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEVICE_H_</div><div class='add'>+#define _XE_DEVICE_H_</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_file;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_util.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_LOCKDEP</div><div class='add'>+extern struct lockdep_map xe_device_mem_access_lockdep_map;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static inline struct xe_device *to_xe_device(const struct drm_device *dev)</div><div class='add'>+{</div><div class='add'>+	return container_of(dev, struct xe_device, drm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_device *pdev_to_xe_device(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	return pci_get_drvdata(pdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_device *ttm_to_xe_device(struct ttm_device *ttm)</div><div class='add'>+{</div><div class='add'>+	return container_of(ttm, struct xe_device, ttm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_device *xe_device_create(struct pci_dev *pdev,</div><div class='add'>+				   const struct pci_device_id *ent);</div><div class='add'>+int xe_device_probe_early(struct xe_device *xe);</div><div class='add'>+int xe_device_probe(struct xe_device *xe);</div><div class='add'>+void xe_device_remove(struct xe_device *xe);</div><div class='add'>+void xe_device_shutdown(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q);</div><div class='add'>+void xe_device_remove_persistent_exec_queues(struct xe_device *xe,</div><div class='add'>+					     struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+void xe_device_wmb(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+static inline struct xe_file *to_xe_file(const struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	return file-&gt;driver_priv;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return &amp;xe-&gt;tiles[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define XE_MAX_GT_PER_TILE 2</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *xe_tile_get_gt(struct xe_tile *tile, u8 gt_id)</div><div class='add'>+{</div><div class='add'>+	if (drm_WARN_ON(&amp;tile_to_xe(tile)-&gt;drm, gt_id &gt; XE_MAX_GT_PER_TILE))</div><div class='add'>+		gt_id = 0;</div><div class='add'>+</div><div class='add'>+	return gt_id ? tile-&gt;media_gt : tile-&gt;primary_gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: This only works for now because multi-tile and standalone</div><div class='add'>+	 * media are mutually exclusive on the platforms we have today.</div><div class='add'>+	 *</div><div class='add'>+	 * id =&gt; GT mapping may change once we settle on how we want to handle</div><div class='add'>+	 * our UAPI.</div><div class='add'>+	 */</div><div class='add'>+	if (MEDIA_VER(xe) &gt;= 13) {</div><div class='add'>+		gt = xe_tile_get_gt(root_tile, gt_id);</div><div class='add'>+	} else {</div><div class='add'>+		if (drm_WARN_ON(&amp;xe-&gt;drm, gt_id &gt; XE_MAX_TILES_PER_DEVICE))</div><div class='add'>+			gt_id = 0;</div><div class='add'>+</div><div class='add'>+		gt = xe-&gt;tiles[gt_id].primary_gt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!gt)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, gt-&gt;info.id != gt_id);</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, gt-&gt;info.type == XE_GT_TYPE_UNINITIALIZED);</div><div class='add'>+</div><div class='add'>+	return gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Provide a GT structure suitable for performing non-GT MMIO operations against</div><div class='add'>+ * the primary tile.  Primarily intended for early tile initialization, display</div><div class='add'>+ * handling, top-most interrupt enable/disable, etc.  Since anything using the</div><div class='add'>+ * MMIO handle returned by this function doesn't need GSI offset translation,</div><div class='add'>+ * we'll return the primary GT from the root tile.</div><div class='add'>+ *</div><div class='add'>+ * FIXME: Fix the driver design so that 'gt' isn't the target of all MMIO</div><div class='add'>+ * operations.</div><div class='add'>+ *</div><div class='add'>+ * Returns the primary gt of the root tile.</div><div class='add'>+ */</div><div class='add'>+static inline struct xe_gt *xe_root_mmio_gt(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe_device_get_root_tile(xe)-&gt;primary_gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_uc_enabled(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return !xe-&gt;info.force_execlist;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define for_each_tile(tile__, xe__, id__) \</div><div class='add'>+	for ((id__) = 0; (id__) &lt; (xe__)-&gt;info.tile_count; (id__)++) \</div><div class='add'>+		for_each_if((tile__) = &amp;(xe__)-&gt;tiles[(id__)])</div><div class='add'>+</div><div class='add'>+#define for_each_remote_tile(tile__, xe__, id__) \</div><div class='add'>+	for ((id__) = 1; (id__) &lt; (xe__)-&gt;info.tile_count; (id__)++) \</div><div class='add'>+		for_each_if((tile__) = &amp;(xe__)-&gt;tiles[(id__)])</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * FIXME: This only works for now since multi-tile and standalone media</div><div class='add'>+ * happen to be mutually exclusive.  Future platforms may change this...</div><div class='add'>+ */</div><div class='add'>+#define for_each_gt(gt__, xe__, id__) \</div><div class='add'>+	for ((id__) = 0; (id__) &lt; (xe__)-&gt;info.gt_count; (id__)++) \</div><div class='add'>+		for_each_if((gt__) = xe_device_get_gt((xe__), (id__)))</div><div class='add'>+</div><div class='add'>+static inline struct xe_force_wake *gt_to_fw(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	return &amp;gt-&gt;mmio.fw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_mem_access_get(struct xe_device *xe);</div><div class='add'>+bool xe_device_mem_access_get_if_ongoing(struct xe_device *xe);</div><div class='add'>+void xe_device_mem_access_put(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_device_assert_mem_access(struct xe_device *xe);</div><div class='add'>+bool xe_device_mem_access_ongoing(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_in_fault_mode(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;usm.num_vm_in_fault_mode != 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_in_non_fault_mode(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;usm.num_vm_in_non_fault_mode != 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_has_flat_ccs(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;info.has_flat_ccs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_has_sriov(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;info.has_sriov;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_device_sysfs.c b/drivers/gpu/drm/xe/xe_device_sysfs.c<br/>new file mode 100644<br/>index 000000000000..99113a5a2b84<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_device_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_sysfs.c</a></div><div class='hunk'>@@ -0,0 +1,89 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_device_sysfs.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe device sysfs</div><div class='add'>+ * Xe driver requires exposing certain tunable knobs controlled by user space for</div><div class='add'>+ * each graphics device. Considering this, we need to add sysfs attributes at device</div><div class='add'>+ * level granularity.</div><div class='add'>+ * These sysfs attributes will be available under pci device kobj directory.</div><div class='add'>+ *</div><div class='add'>+ * vram_d3cold_threshold - Report/change vram used threshold(in MB) below</div><div class='add'>+ * which vram save/restore is permissible during runtime D3cold entry/exit.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+vram_d3cold_threshold_show(struct device *dev,</div><div class='add'>+			   struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!xe)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = sysfs_emit(buf, "%d\n", xe-&gt;d3cold.vram_threshold);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+vram_d3cold_threshold_store(struct device *dev, struct device_attribute *attr,</div><div class='add'>+			    const char *buff, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+	u32 vram_d3cold_threshold;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!xe)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32(buff, 0, &amp;vram_d3cold_threshold);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "vram_d3cold_threshold: %u\n", vram_d3cold_threshold);</div><div class='add'>+</div><div class='add'>+	ret = xe_pm_set_vram_threshold(xe, vram_d3cold_threshold);</div><div class='add'>+</div><div class='add'>+	return ret ?: count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR_RW(vram_d3cold_threshold);</div><div class='add'>+</div><div class='add'>+static void xe_device_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_file(&amp;xe-&gt;drm.dev-&gt;kobj, &amp;dev_attr_vram_d3cold_threshold.attr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_device_sysfs_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = sysfs_create_file(&amp;dev-&gt;kobj, &amp;dev_attr_vram_d3cold_threshold.attr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Failed to create sysfs file\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_device_sysfs_fini, xe);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Failed to add sysfs fini drm action\n");</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_device_sysfs.h b/drivers/gpu/drm/xe/xe_device_sysfs.h<br/>new file mode 100644<br/>index 000000000000..38b240684bee<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_device_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_sysfs.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEVICE_SYSFS_H_</div><div class='add'>+#define _XE_DEVICE_SYSFS_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+void xe_device_sysfs_init(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h<br/>new file mode 100644<br/>index 000000000000..5dc9127a2029<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_device_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_device_types.h</a></div><div class='hunk'>@@ -0,0 +1,545 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022-2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DEVICE_TYPES_H_</div><div class='add'>+#define _XE_DEVICE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_file.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_device.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_devcoredump_types.h"</div><div class='add'>+#include "xe_heci_gsc.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_lmtt_types.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_pt_types.h"</div><div class='add'>+#include "xe_sriov_types.h"</div><div class='add'>+#include "xe_step_types.h"</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)</div><div class='add'>+#include "soc/intel_pch.h"</div><div class='add'>+#include "intel_display_core.h"</div><div class='add'>+#include "intel_display_device.h"</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+struct xe_ggtt;</div><div class='add'>+struct xe_pat_ops;</div><div class='add'>+</div><div class='add'>+#define XE_BO_INVALID_OFFSET	LONG_MAX</div><div class='add'>+</div><div class='add'>+#define GRAPHICS_VER(xe) ((xe)-&gt;info.graphics_verx100 / 100)</div><div class='add'>+#define MEDIA_VER(xe) ((xe)-&gt;info.media_verx100 / 100)</div><div class='add'>+#define GRAPHICS_VERx100(xe) ((xe)-&gt;info.graphics_verx100)</div><div class='add'>+#define MEDIA_VERx100(xe) ((xe)-&gt;info.media_verx100)</div><div class='add'>+#define IS_DGFX(xe) ((xe)-&gt;info.is_dgfx)</div><div class='add'>+#define HAS_HECI_GSCFI(xe) ((xe)-&gt;info.has_heci_gscfi)</div><div class='add'>+</div><div class='add'>+#define XE_VRAM_FLAGS_NEED64K		BIT(0)</div><div class='add'>+</div><div class='add'>+#define XE_GT0		0</div><div class='add'>+#define XE_GT1		1</div><div class='add'>+#define XE_MAX_TILES_PER_DEVICE	(XE_GT1 + 1)</div><div class='add'>+</div><div class='add'>+#define XE_MAX_ASID	(BIT(20))</div><div class='add'>+</div><div class='add'>+#define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step)	\</div><div class='add'>+	((_xe)-&gt;info.platform == (_platform) &amp;&amp;			\</div><div class='add'>+	 (_xe)-&gt;info.step.graphics &gt;= (min_step) &amp;&amp;		\</div><div class='add'>+	 (_xe)-&gt;info.step.graphics &lt; (max_step))</div><div class='add'>+#define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step)	\</div><div class='add'>+	((_xe)-&gt;info.platform == (_platform) &amp;&amp;				\</div><div class='add'>+	 (_xe)-&gt;info.subplatform == (sub) &amp;&amp;				\</div><div class='add'>+	 (_xe)-&gt;info.step.graphics &gt;= (min_step) &amp;&amp;			\</div><div class='add'>+	 (_xe)-&gt;info.step.graphics &lt; (max_step))</div><div class='add'>+</div><div class='add'>+#define tile_to_xe(tile__)								\</div><div class='add'>+	_Generic(tile__,								\</div><div class='add'>+		 const struct xe_tile * : (const struct xe_device *)((tile__)-&gt;xe),	\</div><div class='add'>+		 struct xe_tile * : (tile__)-&gt;xe)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_mem_region - memory region structure</div><div class='add'>+ * This is used to describe a memory region in xe</div><div class='add'>+ * device, such as HBM memory or CXL extension memory.</div><div class='add'>+ */</div><div class='add'>+struct xe_mem_region {</div><div class='add'>+	/** @io_start: IO start address of this VRAM instance */</div><div class='add'>+	resource_size_t io_start;</div><div class='add'>+	/**</div><div class='add'>+	 * @io_size: IO size of this VRAM instance</div><div class='add'>+	 *</div><div class='add'>+	 * This represents how much of this VRAM we can access</div><div class='add'>+	 * via the CPU through the VRAM BAR. This can be smaller</div><div class='add'>+	 * than @usable_size, in which case only part of VRAM is CPU</div><div class='add'>+	 * accessible (typically the first 256M). This</div><div class='add'>+	 * configuration is known as small-bar.</div><div class='add'>+	 */</div><div class='add'>+	resource_size_t io_size;</div><div class='add'>+	/** @dpa_base: This memory regions's DPA (device physical address) base */</div><div class='add'>+	resource_size_t dpa_base;</div><div class='add'>+	/**</div><div class='add'>+	 * @usable_size: usable size of VRAM</div><div class='add'>+	 *</div><div class='add'>+	 * Usable size of VRAM excluding reserved portions</div><div class='add'>+	 * (e.g stolen mem)</div><div class='add'>+	 */</div><div class='add'>+	resource_size_t usable_size;</div><div class='add'>+	/**</div><div class='add'>+	 * @actual_physical_size: Actual VRAM size</div><div class='add'>+	 *</div><div class='add'>+	 * Actual VRAM size including reserved portions</div><div class='add'>+	 * (e.g stolen mem)</div><div class='add'>+	 */</div><div class='add'>+	resource_size_t actual_physical_size;</div><div class='add'>+	/** @mapping: pointer to VRAM mappable space */</div><div class='add'>+	void __iomem *mapping;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_tile - hardware tile structure</div><div class='add'>+ *</div><div class='add'>+ * From a driver perspective, a "tile" is effectively a complete GPU, containing</div><div class='add'>+ * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.</div><div class='add'>+ *</div><div class='add'>+ * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI</div><div class='add'>+ * device and designate one "root" tile as being responsible for external PCI</div><div class='add'>+ * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each</div><div class='add'>+ * tile in a stacked layout, and PCI BAR2 exposes the local memory associated</div><div class='add'>+ * with each tile similarly.  Device-wide interrupts can be enabled/disabled</div><div class='add'>+ * at the root tile, and the MSTR_TILE_INTR register will report which tiles</div><div class='add'>+ * have interrupts that need servicing.</div><div class='add'>+ */</div><div class='add'>+struct xe_tile {</div><div class='add'>+	/** @xe: Backpointer to tile's PCI device */</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+</div><div class='add'>+	/** @id: ID of the tile */</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @primary_gt: Primary GT</div><div class='add'>+	 */</div><div class='add'>+	struct xe_gt *primary_gt;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @media_gt: Media GT</div><div class='add'>+	 *</div><div class='add'>+	 * Only present on devices with media version &gt;= 13.</div><div class='add'>+	 */</div><div class='add'>+	struct xe_gt *media_gt;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mmio: MMIO info for a tile.</div><div class='add'>+	 *</div><div class='add'>+	 * Each tile has its own 16MB space in BAR0, laid out as:</div><div class='add'>+	 * * 0-4MB: registers</div><div class='add'>+	 * * 4MB-8MB: reserved</div><div class='add'>+	 * * 8MB-16MB: global GTT</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @size: size of tile's MMIO space */</div><div class='add'>+		size_t size;</div><div class='add'>+</div><div class='add'>+		/** @regs: pointer to tile's MMIO space (starting with registers) */</div><div class='add'>+		void __iomem *regs;</div><div class='add'>+	} mmio;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mmio_ext: MMIO-extension info for a tile.</div><div class='add'>+	 *</div><div class='add'>+	 * Each tile has its own additional 256MB (28-bit) MMIO-extension space.</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @size: size of tile's additional MMIO-extension space */</div><div class='add'>+		size_t size;</div><div class='add'>+</div><div class='add'>+		/** @regs: pointer to tile's additional MMIO-extension space */</div><div class='add'>+		void __iomem *regs;</div><div class='add'>+	} mmio_ext;</div><div class='add'>+</div><div class='add'>+	/** @mem: memory management info for tile */</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @vram: VRAM info for tile.</div><div class='add'>+		 *</div><div class='add'>+		 * Although VRAM is associated with a specific tile, it can</div><div class='add'>+		 * still be accessed by all tiles' GTs.</div><div class='add'>+		 */</div><div class='add'>+		struct xe_mem_region vram;</div><div class='add'>+</div><div class='add'>+		/** @vram_mgr: VRAM TTM manager */</div><div class='add'>+		struct xe_ttm_vram_mgr *vram_mgr;</div><div class='add'>+</div><div class='add'>+		/** @ggtt: Global graphics translation table */</div><div class='add'>+		struct xe_ggtt *ggtt;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @kernel_bb_pool: Pool from which batchbuffers are allocated.</div><div class='add'>+		 *</div><div class='add'>+		 * Media GT shares a pool with its primary GT.</div><div class='add'>+		 */</div><div class='add'>+		struct xe_sa_manager *kernel_bb_pool;</div><div class='add'>+	} mem;</div><div class='add'>+</div><div class='add'>+	/** @sriov: tile level virtualization data */</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			/** @sriov.pf.lmtt: Local Memory Translation Table. */</div><div class='add'>+			struct xe_lmtt lmtt;</div><div class='add'>+		} pf;</div><div class='add'>+	} sriov;</div><div class='add'>+</div><div class='add'>+	/** @migrate: Migration helper for vram blits and clearing */</div><div class='add'>+	struct xe_migrate *migrate;</div><div class='add'>+</div><div class='add'>+	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */</div><div class='add'>+	struct kobject *sysfs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_device - Top level struct of XE device</div><div class='add'>+ */</div><div class='add'>+struct xe_device {</div><div class='add'>+	/** @drm: drm device */</div><div class='add'>+	struct drm_device drm;</div><div class='add'>+</div><div class='add'>+	/** @devcoredump: device coredump */</div><div class='add'>+	struct xe_devcoredump devcoredump;</div><div class='add'>+</div><div class='add'>+	/** @info: device info */</div><div class='add'>+	struct intel_device_info {</div><div class='add'>+		/** @graphics_name: graphics IP name */</div><div class='add'>+		const char *graphics_name;</div><div class='add'>+		/** @media_name: media IP name */</div><div class='add'>+		const char *media_name;</div><div class='add'>+		/** @tile_mmio_ext_size: size of MMIO extension space, per-tile */</div><div class='add'>+		u32 tile_mmio_ext_size;</div><div class='add'>+		/** @graphics_verx100: graphics IP version */</div><div class='add'>+		u32 graphics_verx100;</div><div class='add'>+		/** @media_verx100: media IP version */</div><div class='add'>+		u32 media_verx100;</div><div class='add'>+		/** @mem_region_mask: mask of valid memory regions */</div><div class='add'>+		u32 mem_region_mask;</div><div class='add'>+		/** @platform: XE platform enum */</div><div class='add'>+		enum xe_platform platform;</div><div class='add'>+		/** @subplatform: XE subplatform enum */</div><div class='add'>+		enum xe_subplatform subplatform;</div><div class='add'>+		/** @devid: device ID */</div><div class='add'>+		u16 devid;</div><div class='add'>+		/** @revid: device revision */</div><div class='add'>+		u8 revid;</div><div class='add'>+		/** @step: stepping information for each IP */</div><div class='add'>+		struct xe_step_info step;</div><div class='add'>+		/** @dma_mask_size: DMA address bits */</div><div class='add'>+		u8 dma_mask_size;</div><div class='add'>+		/** @vram_flags: Vram flags */</div><div class='add'>+		u8 vram_flags;</div><div class='add'>+		/** @tile_count: Number of tiles */</div><div class='add'>+		u8 tile_count;</div><div class='add'>+		/** @gt_count: Total number of GTs for entire device */</div><div class='add'>+		u8 gt_count;</div><div class='add'>+		/** @vm_max_level: Max VM level */</div><div class='add'>+		u8 vm_max_level;</div><div class='add'>+		/** @va_bits: Maximum bits of a virtual address */</div><div class='add'>+		u8 va_bits;</div><div class='add'>+</div><div class='add'>+		/** @is_dgfx: is discrete device */</div><div class='add'>+		u8 is_dgfx:1;</div><div class='add'>+		/** @has_asid: Has address space ID */</div><div class='add'>+		u8 has_asid:1;</div><div class='add'>+		/** @force_execlist: Forced execlist submission */</div><div class='add'>+		u8 force_execlist:1;</div><div class='add'>+		/** @has_flat_ccs: Whether flat CCS metadata is used */</div><div class='add'>+		u8 has_flat_ccs:1;</div><div class='add'>+		/** @has_llc: Device has a shared CPU+GPU last level cache */</div><div class='add'>+		u8 has_llc:1;</div><div class='add'>+		/** @has_mmio_ext: Device has extra MMIO address range */</div><div class='add'>+		u8 has_mmio_ext:1;</div><div class='add'>+		/** @has_range_tlb_invalidation: Has range based TLB invalidations */</div><div class='add'>+		u8 has_range_tlb_invalidation:1;</div><div class='add'>+		/** @has_sriov: Supports SR-IOV */</div><div class='add'>+		u8 has_sriov:1;</div><div class='add'>+		/** @has_usm: Device has unified shared memory support */</div><div class='add'>+		u8 has_usm:1;</div><div class='add'>+		/** @enable_display: display enabled */</div><div class='add'>+		u8 enable_display:1;</div><div class='add'>+		/** @skip_mtcfg: skip Multi-Tile configuration from MTCFG register */</div><div class='add'>+		u8 skip_mtcfg:1;</div><div class='add'>+		/** @skip_pcode: skip access to PCODE uC */</div><div class='add'>+		u8 skip_pcode:1;</div><div class='add'>+		/** @has_heci_gscfi: device has heci gscfi */</div><div class='add'>+		u8 has_heci_gscfi:1;</div><div class='add'>+		/** @skip_guc_pc: Skip GuC based PM feature init */</div><div class='add'>+		u8 skip_guc_pc:1;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)</div><div class='add'>+		struct {</div><div class='add'>+			u32 rawclk_freq;</div><div class='add'>+		} i915_runtime;</div><div class='add'>+#endif</div><div class='add'>+	} info;</div><div class='add'>+</div><div class='add'>+	/** @irq: device interrupt state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @lock: lock for processing irq's on this device */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+</div><div class='add'>+		/** @enabled: interrupts enabled on this device */</div><div class='add'>+		bool enabled;</div><div class='add'>+	} irq;</div><div class='add'>+</div><div class='add'>+	/** @ttm: ttm device */</div><div class='add'>+	struct ttm_device ttm;</div><div class='add'>+</div><div class='add'>+	/** @mmio: mmio info for device */</div><div class='add'>+	struct {</div><div class='add'>+		/** @size: size of MMIO space for device */</div><div class='add'>+		size_t size;</div><div class='add'>+		/** @regs: pointer to MMIO space for device */</div><div class='add'>+		void __iomem *regs;</div><div class='add'>+	} mmio;</div><div class='add'>+</div><div class='add'>+	/** @mem: memory info for device */</div><div class='add'>+	struct {</div><div class='add'>+		/** @vram: VRAM info for device */</div><div class='add'>+		struct xe_mem_region vram;</div><div class='add'>+		/** @sys_mgr: system TTM manager */</div><div class='add'>+		struct ttm_resource_manager sys_mgr;</div><div class='add'>+	} mem;</div><div class='add'>+</div><div class='add'>+	/** @sriov: device level virtualization data */</div><div class='add'>+	struct {</div><div class='add'>+		/** @sriov.__mode: SR-IOV mode (Don't access directly!) */</div><div class='add'>+		enum xe_sriov_mode __mode;</div><div class='add'>+	} sriov;</div><div class='add'>+</div><div class='add'>+	/** @clients: drm clients info */</div><div class='add'>+	struct {</div><div class='add'>+		/** @lock: Protects drm clients info */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+</div><div class='add'>+		/** @count: number of drm clients */</div><div class='add'>+		u64 count;</div><div class='add'>+	} clients;</div><div class='add'>+</div><div class='add'>+	/** @usm: unified memory state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @asid: convert a ASID to VM */</div><div class='add'>+		struct xarray asid_to_vm;</div><div class='add'>+		/** @next_asid: next ASID, used to cyclical alloc asids */</div><div class='add'>+		u32 next_asid;</div><div class='add'>+		/** @num_vm_in_fault_mode: number of VM in fault mode */</div><div class='add'>+		u32 num_vm_in_fault_mode;</div><div class='add'>+		/** @num_vm_in_non_fault_mode: number of VM in non-fault mode */</div><div class='add'>+		u32 num_vm_in_non_fault_mode;</div><div class='add'>+		/** @lock: protects UM state */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+	} usm;</div><div class='add'>+</div><div class='add'>+	/** @persistent_engines: engines that are closed but still running */</div><div class='add'>+	struct {</div><div class='add'>+		/** @lock: protects persistent engines */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+		/** @list: list of persistent engines */</div><div class='add'>+		struct list_head list;</div><div class='add'>+	} persistent_engines;</div><div class='add'>+</div><div class='add'>+	/** @pinned: pinned BO state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @lock: protected pinned BO list state */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+		/** @evicted: pinned kernel BO that are present */</div><div class='add'>+		struct list_head kernel_bo_present;</div><div class='add'>+		/** @evicted: pinned BO that have been evicted */</div><div class='add'>+		struct list_head evicted;</div><div class='add'>+		/** @external_vram: pinned external BO in vram*/</div><div class='add'>+		struct list_head external_vram;</div><div class='add'>+	} pinned;</div><div class='add'>+</div><div class='add'>+	/** @ufence_wq: user fence wait queue */</div><div class='add'>+	wait_queue_head_t ufence_wq;</div><div class='add'>+</div><div class='add'>+	/** @ordered_wq: used to serialize compute mode resume */</div><div class='add'>+	struct workqueue_struct *ordered_wq;</div><div class='add'>+</div><div class='add'>+	/** @unordered_wq: used to serialize unordered work, mostly display */</div><div class='add'>+	struct workqueue_struct *unordered_wq;</div><div class='add'>+</div><div class='add'>+	/** @tiles: device tiles */</div><div class='add'>+	struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mem_access: keep track of memory access in the device, possibly</div><div class='add'>+	 * triggering additional actions when they occur.</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @ref: ref count of memory accesses */</div><div class='add'>+		atomic_t ref;</div><div class='add'>+	} mem_access;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pat: Encapsulate PAT related stuff</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** Internal operations to abstract platforms */</div><div class='add'>+		const struct xe_pat_ops *ops;</div><div class='add'>+		/** PAT table to program in the HW */</div><div class='add'>+		const struct xe_pat_table_entry *table;</div><div class='add'>+		/** Number of PAT entries */</div><div class='add'>+		int n_entries;</div><div class='add'>+		u32 idx[__XE_CACHE_LEVEL_COUNT];</div><div class='add'>+	} pat;</div><div class='add'>+</div><div class='add'>+	/** @d3cold: Encapsulate d3cold related stuff */</div><div class='add'>+	struct {</div><div class='add'>+		/** capable: Indicates if root port is d3cold capable */</div><div class='add'>+		bool capable;</div><div class='add'>+</div><div class='add'>+		/** @allowed: Indicates if d3cold is a valid device state */</div><div class='add'>+		bool allowed;</div><div class='add'>+</div><div class='add'>+		/** @power_lost: Indicates if card has really lost power. */</div><div class='add'>+		bool power_lost;</div><div class='add'>+</div><div class='add'>+		/**</div><div class='add'>+		 * @vram_threshold:</div><div class='add'>+		 *</div><div class='add'>+		 * This represents the permissible threshold(in megabytes)</div><div class='add'>+		 * for vram save/restore. d3cold will be disallowed,</div><div class='add'>+		 * when vram_usages is above or equals the threshold value</div><div class='add'>+		 * to avoid the vram save/restore latency.</div><div class='add'>+		 * Default threshold value is 300mb.</div><div class='add'>+		 */</div><div class='add'>+		u32 vram_threshold;</div><div class='add'>+		/** @lock: protect vram_threshold */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+	} d3cold;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pm_callback_task: Track the active task that is running in either</div><div class='add'>+	 * the runtime_suspend or runtime_resume callbacks.</div><div class='add'>+	 */</div><div class='add'>+	struct task_struct *pm_callback_task;</div><div class='add'>+</div><div class='add'>+	/** @hwmon: hwmon subsystem integration */</div><div class='add'>+	struct xe_hwmon *hwmon;</div><div class='add'>+</div><div class='add'>+	/** @heci_gsc: graphics security controller */</div><div class='add'>+	struct xe_heci_gsc heci_gsc;</div><div class='add'>+</div><div class='add'>+	/** @needs_flr_on_fini: requests function-reset on fini */</div><div class='add'>+	bool needs_flr_on_fini;</div><div class='add'>+</div><div class='add'>+	/* private: */</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)</div><div class='add'>+	/*</div><div class='add'>+	 * Any fields below this point are the ones used by display.</div><div class='add'>+	 * They are temporarily added here so xe_device can be desguised as</div><div class='add'>+	 * drm_i915_private during build. After cleanup these should go away,</div><div class='add'>+	 * migrating to the right sub-structs</div><div class='add'>+	 */</div><div class='add'>+	struct intel_display display;</div><div class='add'>+	enum intel_pch pch_type;</div><div class='add'>+	u16 pch_id;</div><div class='add'>+</div><div class='add'>+	struct dram_info {</div><div class='add'>+		bool wm_lv_0_adjust_needed;</div><div class='add'>+		u8 num_channels;</div><div class='add'>+		bool symmetric_memory;</div><div class='add'>+		enum intel_dram_type {</div><div class='add'>+			INTEL_DRAM_UNKNOWN,</div><div class='add'>+			INTEL_DRAM_DDR3,</div><div class='add'>+			INTEL_DRAM_DDR4,</div><div class='add'>+			INTEL_DRAM_LPDDR3,</div><div class='add'>+			INTEL_DRAM_LPDDR4,</div><div class='add'>+			INTEL_DRAM_DDR5,</div><div class='add'>+			INTEL_DRAM_LPDDR5,</div><div class='add'>+		} type;</div><div class='add'>+		u8 num_qgv_points;</div><div class='add'>+		u8 num_psf_gv_points;</div><div class='add'>+	} dram_info;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * edram size in MB.</div><div class='add'>+	 * Cannot be determined by PCIID. You must always read a register.</div><div class='add'>+	 */</div><div class='add'>+	u32 edram_size_mb;</div><div class='add'>+</div><div class='add'>+	/* To shut up runtime pm macros.. */</div><div class='add'>+	struct xe_runtime_pm {} runtime_pm;</div><div class='add'>+</div><div class='add'>+	/* For pcode */</div><div class='add'>+	struct mutex sb_lock;</div><div class='add'>+</div><div class='add'>+	/* Should be in struct intel_display */</div><div class='add'>+	u32 skl_preferred_vco_freq, max_dotclk_freq, hti_state;</div><div class='add'>+	u8 snps_phy_failed_calibration;</div><div class='add'>+	struct drm_atomic_state *modeset_restore_state;</div><div class='add'>+	struct list_head global_obj_list;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/* only to allow build, not used functionally */</div><div class='add'>+		u32 irq_mask;</div><div class='add'>+		u32 de_irq_mask[I915_MAX_PIPES];</div><div class='add'>+	};</div><div class='add'>+	u32 pipestat_irq_mask[I915_MAX_PIPES];</div><div class='add'>+</div><div class='add'>+	bool display_irqs_enabled;</div><div class='add'>+	u32 enabled_irq_mask;</div><div class='add'>+</div><div class='add'>+	struct intel_uncore {</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+	} uncore;</div><div class='add'>+</div><div class='add'>+	/* only to allow build, not used functionally */</div><div class='add'>+	struct {</div><div class='add'>+		unsigned int hpll_freq;</div><div class='add'>+		unsigned int czclk_freq;</div><div class='add'>+		unsigned int fsb_freq, mem_freq, is_ddr3;</div><div class='add'>+		u8 vblank_enabled;</div><div class='add'>+	};</div><div class='add'>+	struct {</div><div class='add'>+		const char *dmc_firmware_path;</div><div class='add'>+	} params;</div><div class='add'>+</div><div class='add'>+	void *pxp;</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_file - file handle for XE driver</div><div class='add'>+ */</div><div class='add'>+struct xe_file {</div><div class='add'>+	/** @xe: xe DEVICE **/</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+</div><div class='add'>+	/** @drm: base DRM file */</div><div class='add'>+	struct drm_file *drm;</div><div class='add'>+</div><div class='add'>+	/** @vm: VM state for file */</div><div class='add'>+	struct {</div><div class='add'>+		/** @xe: xarray to store VMs */</div><div class='add'>+		struct xarray xa;</div><div class='add'>+		/** @lock: protects file VM state */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+	} vm;</div><div class='add'>+</div><div class='add'>+	/** @exec_queue: Submission exec queue state for file */</div><div class='add'>+	struct {</div><div class='add'>+		/** @xe: xarray to store engines */</div><div class='add'>+		struct xarray xa;</div><div class='add'>+		/** @lock: protects file engine state */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+	} exec_queue;</div><div class='add'>+</div><div class='add'>+	/** @client: drm client */</div><div class='add'>+	struct xe_drm_client *client;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c<br/>new file mode 100644<br/>index 000000000000..74391d9b11ae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_display.c</a></div><div class='hunk'>@@ -0,0 +1,422 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_display.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/fb.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "soc/intel_dram.h"</div><div class='add'>+#include "i915_drv.h"		/* FIXME: HAS_DISPLAY() depends on this */</div><div class='add'>+#include "intel_acpi.h"</div><div class='add'>+#include "intel_audio.h"</div><div class='add'>+#include "intel_bw.h"</div><div class='add'>+#include "intel_display.h"</div><div class='add'>+#include "intel_display_driver.h"</div><div class='add'>+#include "intel_display_irq.h"</div><div class='add'>+#include "intel_display_types.h"</div><div class='add'>+#include "intel_dmc.h"</div><div class='add'>+#include "intel_dp.h"</div><div class='add'>+#include "intel_fbdev.h"</div><div class='add'>+#include "intel_hdcp.h"</div><div class='add'>+#include "intel_hotplug.h"</div><div class='add'>+#include "intel_opregion.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+</div><div class='add'>+/* Xe device functions */</div><div class='add'>+</div><div class='add'>+static bool has_display(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return HAS_DISPLAY(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_display_driver_probe_defer - Detect if we need to wait for other drivers</div><div class='add'>+ *				   early on</div><div class='add'>+ * @pdev: PCI device</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if probe needs to be deferred, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool xe_display_driver_probe_defer(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (!xe_modparam.enable_display)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return intel_display_driver_probe_defer(pdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_display_last_close(struct drm_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.enable_display)</div><div class='add'>+		intel_fbdev_restore_mode(to_xe_device(dev));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_display_driver_set_hooks - Add driver flags and hooks for display</div><div class='add'>+ * @driver: DRM device driver</div><div class='add'>+ *</div><div class='add'>+ * Set features and function hooks in @driver that are needed for driving the</div><div class='add'>+ * display IP. This sets the driver's capability of driving display, regardless</div><div class='add'>+ * if the device has it enabled</div><div class='add'>+ */</div><div class='add'>+void xe_display_driver_set_hooks(struct drm_driver *driver)</div><div class='add'>+{</div><div class='add'>+	if (!xe_modparam.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	driver-&gt;driver_features |= DRIVER_MODESET | DRIVER_ATOMIC;</div><div class='add'>+	driver-&gt;lastclose = xe_display_last_close;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void unset_display_features(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xe-&gt;drm.driver_features &amp;= ~(DRIVER_MODESET | DRIVER_ATOMIC);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void display_destroy(struct drm_device *dev, void *dummy)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	destroy_workqueue(xe-&gt;display.hotplug.dp_wq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_display_create - create display struct</div><div class='add'>+ * @xe: XE device instance</div><div class='add'>+ *</div><div class='add'>+ * Initialize all fields used by the display part.</div><div class='add'>+ *</div><div class='add'>+ * TODO: once everything can be inside a single struct, make the struct opaque</div><div class='add'>+ * to the rest of xe and return it to be xe-&gt;display.</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success</div><div class='add'>+ */</div><div class='add'>+int xe_display_create(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;xe-&gt;display.fb_tracking.lock);</div><div class='add'>+</div><div class='add'>+	xe-&gt;display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);</div><div class='add'>+</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;sb_lock);</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;display.backlight.lock);</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;display.audio.mutex);</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;display.wm.wm_mutex);</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;display.pps.mutex);</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;display.hdcp.hdcp_mutex);</div><div class='add'>+	xe-&gt;enabled_irq_mask = ~0;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, display_destroy, NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_display_fini_nommio(struct drm_device *dev, void *dummy)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_power_domains_cleanup(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_display_init_nommio(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Fake uncore lock */</div><div class='add'>+	spin_lock_init(&amp;xe-&gt;uncore.lock);</div><div class='add'>+</div><div class='add'>+	/* This must be called before any calls to HAS_PCH_* */</div><div class='add'>+	intel_detect_pch(xe);</div><div class='add'>+</div><div class='add'>+	err = intel_power_domains_init(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_display_fini_nommio, xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_display_fini_noirq(struct drm_device *dev, void *dummy)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_display_driver_remove_noirq(xe);</div><div class='add'>+	intel_power_domains_driver_remove(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_display_init_noirq(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	intel_display_driver_early_probe(xe);</div><div class='add'>+</div><div class='add'>+	/* Early display init.. */</div><div class='add'>+	intel_opregion_setup(xe);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Fill the dram structure to get the system dram info. This will be</div><div class='add'>+	 * used for memory latency calculation.</div><div class='add'>+	 */</div><div class='add'>+	intel_dram_detect(xe);</div><div class='add'>+</div><div class='add'>+	intel_bw_init_hw(xe);</div><div class='add'>+</div><div class='add'>+	intel_display_device_info_runtime_init(xe);</div><div class='add'>+</div><div class='add'>+	err = intel_display_driver_probe_noirq(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_display_fini_noirq, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_display_fini_noaccel(struct drm_device *dev, void *dummy)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_display_driver_remove_nogem(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_display_init_noaccel(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = intel_display_driver_probe_nogem(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_display_fini_noaccel, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_display_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return intel_display_driver_probe(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_fini(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* poll work can call into fbdev, hence clean that up afterwards */</div><div class='add'>+	intel_hpd_poll_fini(xe);</div><div class='add'>+	intel_fbdev_fini(xe);</div><div class='add'>+</div><div class='add'>+	intel_hdcp_component_fini(xe);</div><div class='add'>+	intel_audio_deinit(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_register(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_display_driver_register(xe);</div><div class='add'>+	intel_register_dsm_handler();</div><div class='add'>+	intel_power_domains_enable(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_unregister(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_unregister_dsm_handler();</div><div class='add'>+	intel_power_domains_disable(xe);</div><div class='add'>+	intel_display_driver_unregister(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_driver_remove(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_display_driver_remove(xe);</div><div class='add'>+</div><div class='add'>+	intel_display_device_remove(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* IRQ-related functions */</div><div class='add'>+</div><div class='add'>+void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (master_ctl &amp; DISPLAY_IRQ)</div><div class='add'>+		gen11_display_irq_handler(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (gu_misc_iir &amp; GU_MISC_GSE)</div><div class='add'>+		intel_opregion_asle_intr(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_irq_reset(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	gen11_display_irq_reset(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;info.id == XE_GT0)</div><div class='add'>+		gen11_de_irq_postinstall(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void intel_suspend_encoders(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *dev = &amp;xe-&gt;drm;</div><div class='add'>+	struct intel_encoder *encoder;</div><div class='add'>+</div><div class='add'>+	if (has_display(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_modeset_lock_all(dev);</div><div class='add'>+	for_each_intel_encoder(dev, encoder)</div><div class='add'>+		if (encoder-&gt;suspend)</div><div class='add'>+			encoder-&gt;suspend(encoder);</div><div class='add'>+	drm_modeset_unlock_all(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool suspend_to_idle(void)</div><div class='add'>+{</div><div class='add'>+#if IS_ENABLED(CONFIG_ACPI_SLEEP)</div><div class='add'>+	if (acpi_target_system_state() &lt; ACPI_STATE_S3)</div><div class='add'>+		return true;</div><div class='add'>+#endif</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_pm_suspend(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	bool s2idle = suspend_to_idle();</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We do a lot of poking in a lot of registers, make sure they work</div><div class='add'>+	 * properly.</div><div class='add'>+	 */</div><div class='add'>+	intel_power_domains_disable(xe);</div><div class='add'>+	if (has_display(xe))</div><div class='add'>+		drm_kms_helper_poll_disable(&amp;xe-&gt;drm);</div><div class='add'>+</div><div class='add'>+	intel_display_driver_suspend(xe);</div><div class='add'>+</div><div class='add'>+	intel_dp_mst_suspend(xe);</div><div class='add'>+</div><div class='add'>+	intel_hpd_cancel_work(xe);</div><div class='add'>+</div><div class='add'>+	intel_suspend_encoders(xe);</div><div class='add'>+</div><div class='add'>+	intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold);</div><div class='add'>+</div><div class='add'>+	intel_fbdev_set_suspend(&amp;xe-&gt;drm, FBINFO_STATE_SUSPENDED, true);</div><div class='add'>+</div><div class='add'>+	intel_dmc_suspend(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_pm_suspend_late(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	bool s2idle = suspend_to_idle();</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_power_domains_suspend(xe, s2idle);</div><div class='add'>+</div><div class='add'>+	intel_display_power_suspend_late(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_pm_resume_early(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_display_power_resume_early(xe);</div><div class='add'>+</div><div class='add'>+	intel_power_domains_resume(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_pm_resume(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	intel_dmc_resume(xe);</div><div class='add'>+</div><div class='add'>+	if (has_display(xe))</div><div class='add'>+		drm_mode_config_reset(&amp;xe-&gt;drm);</div><div class='add'>+</div><div class='add'>+	intel_display_driver_init_hw(xe);</div><div class='add'>+	intel_hpd_init(xe);</div><div class='add'>+</div><div class='add'>+	/* MST sideband requires HPD interrupts enabled */</div><div class='add'>+	intel_dp_mst_resume(xe);</div><div class='add'>+	intel_display_driver_resume(xe);</div><div class='add'>+</div><div class='add'>+	intel_hpd_poll_disable(xe);</div><div class='add'>+	if (has_display(xe))</div><div class='add'>+		drm_kms_helper_poll_enable(&amp;xe-&gt;drm);</div><div class='add'>+</div><div class='add'>+	intel_opregion_resume(xe);</div><div class='add'>+</div><div class='add'>+	intel_fbdev_set_suspend(&amp;xe-&gt;drm, FBINFO_STATE_RUNNING, false);</div><div class='add'>+</div><div class='add'>+	intel_power_domains_enable(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_display_probe(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!xe-&gt;info.enable_display)</div><div class='add'>+		goto no_display;</div><div class='add'>+</div><div class='add'>+	intel_display_device_probe(xe);</div><div class='add'>+</div><div class='add'>+	if (has_display(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+no_display:</div><div class='add'>+	xe-&gt;info.enable_display = false;</div><div class='add'>+	unset_display_features(xe);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_display.h b/drivers/gpu/drm/xe/xe_display.h<br/>new file mode 100644<br/>index 000000000000..710e56180b52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_display.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_display.h</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DISPLAY_H_</div><div class='add'>+#define _XE_DISPLAY_H_</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+</div><div class='add'>+struct drm_driver;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)</div><div class='add'>+</div><div class='add'>+bool xe_display_driver_probe_defer(struct pci_dev *pdev);</div><div class='add'>+void xe_display_driver_set_hooks(struct drm_driver *driver);</div><div class='add'>+void xe_display_driver_remove(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+int xe_display_create(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_display_probe(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+int xe_display_init_nommio(struct xe_device *xe);</div><div class='add'>+int xe_display_init_noirq(struct xe_device *xe);</div><div class='add'>+int xe_display_init_noaccel(struct xe_device *xe);</div><div class='add'>+int xe_display_init(struct xe_device *xe);</div><div class='add'>+void xe_display_fini(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_display_register(struct xe_device *xe);</div><div class='add'>+void xe_display_unregister(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl);</div><div class='add'>+void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir);</div><div class='add'>+void xe_display_irq_reset(struct xe_device *xe);</div><div class='add'>+void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+void xe_display_pm_suspend(struct xe_device *xe);</div><div class='add'>+void xe_display_pm_suspend_late(struct xe_device *xe);</div><div class='add'>+void xe_display_pm_resume_early(struct xe_device *xe);</div><div class='add'>+void xe_display_pm_resume(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+static inline int xe_display_driver_probe_defer(struct pci_dev *pdev) { return 0; }</div><div class='add'>+static inline void xe_display_driver_set_hooks(struct drm_driver *driver) { }</div><div class='add'>+static inline void xe_display_driver_remove(struct xe_device *xe) {}</div><div class='add'>+</div><div class='add'>+static inline int xe_display_create(struct xe_device *xe) { return 0; }</div><div class='add'>+</div><div class='add'>+static inline void xe_display_probe(struct xe_device *xe) { }</div><div class='add'>+</div><div class='add'>+static inline int xe_display_init_nommio(struct xe_device *xe) { return 0; }</div><div class='add'>+static inline int xe_display_init_noirq(struct xe_device *xe) { return 0; }</div><div class='add'>+static inline int xe_display_init_noaccel(struct xe_device *xe) { return 0; }</div><div class='add'>+static inline int xe_display_init(struct xe_device *xe) { return 0; }</div><div class='add'>+static inline void xe_display_fini(struct xe_device *xe) {}</div><div class='add'>+</div><div class='add'>+static inline void xe_display_register(struct xe_device *xe) {}</div><div class='add'>+static inline void xe_display_unregister(struct xe_device *xe) {}</div><div class='add'>+</div><div class='add'>+static inline void xe_display_irq_handler(struct xe_device *xe, u32 master_ctl) {}</div><div class='add'>+static inline void xe_display_irq_enable(struct xe_device *xe, u32 gu_misc_iir) {}</div><div class='add'>+static inline void xe_display_irq_reset(struct xe_device *xe) {}</div><div class='add'>+static inline void xe_display_irq_postinstall(struct xe_device *xe, struct xe_gt *gt) {}</div><div class='add'>+</div><div class='add'>+static inline void xe_display_pm_suspend(struct xe_device *xe) {}</div><div class='add'>+static inline void xe_display_pm_suspend_late(struct xe_device *xe) {}</div><div class='add'>+static inline void xe_display_pm_resume_early(struct xe_device *xe) {}</div><div class='add'>+static inline void xe_display_pm_resume(struct xe_device *xe) {}</div><div class='add'>+</div><div class='add'>+#endif /* CONFIG_DRM_XE_DISPLAY */</div><div class='add'>+#endif /* _XE_DISPLAY_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_dma_buf.c b/drivers/gpu/drm/xe/xe_dma_buf.c<br/>new file mode 100644<br/>index 000000000000..64ed303728fd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_dma_buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_dma_buf.c</a></div><div class='hunk'>@@ -0,0 +1,322 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_dma_buf.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/test.h&gt;</div><div class='add'>+#include &lt;linux/dma-buf.h&gt;</div><div class='add'>+#include &lt;linux/pci-p2pdma.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_prime.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+MODULE_IMPORT_NS(DMA_BUF);</div><div class='add'>+</div><div class='add'>+static int xe_dma_buf_attach(struct dma_buf *dmabuf,</div><div class='add'>+			     struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = attach-&gt;dmabuf-&gt;priv;</div><div class='add'>+</div><div class='add'>+	if (attach-&gt;peer2peer &amp;&amp;</div><div class='add'>+	    pci_p2pdma_distance(to_pci_dev(obj-&gt;dev-&gt;dev), attach-&gt;dev, false) &lt; 0)</div><div class='add'>+		attach-&gt;peer2peer = false;</div><div class='add'>+</div><div class='add'>+	if (!attach-&gt;peer2peer &amp;&amp; !xe_bo_can_migrate(gem_to_xe_bo(obj), XE_PL_TT))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(to_xe_device(obj-&gt;dev));</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_dma_buf_detach(struct dma_buf *dmabuf,</div><div class='add'>+			      struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = attach-&gt;dmabuf-&gt;priv;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(to_xe_device(obj-&gt;dev));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_dma_buf_pin(struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = attach-&gt;dmabuf-&gt;priv;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For now only support pinning in TT memory, for two reasons:</div><div class='add'>+	 * 1) Avoid pinning in a placement not accessible to some importers.</div><div class='add'>+	 * 2) Pinning in VRAM requires PIN accounting which is a to-do.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_bo_is_pinned(bo) &amp;&amp; bo-&gt;ttm.resource-&gt;placement != XE_PL_TT) {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Can't migrate pinned bo for dma-buf pin.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_migrate(bo, XE_PL_TT);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (ret != -EINTR &amp;&amp; ret != -ERESTARTSYS)</div><div class='add'>+			drm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+				"Failed migrating dma-buf to TT memory: %pe\n",</div><div class='add'>+				ERR_PTR(ret));</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_pin_external(bo);</div><div class='add'>+	xe_assert(xe, !ret);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_dma_buf_unpin(struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = attach-&gt;dmabuf-&gt;priv;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+</div><div class='add'>+	xe_bo_unpin_external(bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct sg_table *xe_dma_buf_map(struct dma_buf_attachment *attach,</div><div class='add'>+				       enum dma_data_direction dir)</div><div class='add'>+{</div><div class='add'>+	struct dma_buf *dma_buf = attach-&gt;dmabuf;</div><div class='add'>+	struct drm_gem_object *obj = dma_buf-&gt;priv;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+	struct sg_table *sgt;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (!attach-&gt;peer2peer &amp;&amp; !xe_bo_can_migrate(bo, XE_PL_TT))</div><div class='add'>+		return ERR_PTR(-EOPNOTSUPP);</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_pinned(bo)) {</div><div class='add'>+		if (!attach-&gt;peer2peer)</div><div class='add'>+			r = xe_bo_migrate(bo, XE_PL_TT);</div><div class='add'>+		else</div><div class='add'>+			r = xe_bo_validate(bo, NULL, false);</div><div class='add'>+		if (r)</div><div class='add'>+			return ERR_PTR(r);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (bo-&gt;ttm.resource-&gt;mem_type) {</div><div class='add'>+	case XE_PL_TT:</div><div class='add'>+		sgt = drm_prime_pages_to_sg(obj-&gt;dev,</div><div class='add'>+					    bo-&gt;ttm.ttm-&gt;pages,</div><div class='add'>+					    bo-&gt;ttm.ttm-&gt;num_pages);</div><div class='add'>+		if (IS_ERR(sgt))</div><div class='add'>+			return sgt;</div><div class='add'>+</div><div class='add'>+		if (dma_map_sgtable(attach-&gt;dev, sgt, dir,</div><div class='add'>+				    DMA_ATTR_SKIP_CPU_SYNC))</div><div class='add'>+			goto error_free;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case XE_PL_VRAM0:</div><div class='add'>+	case XE_PL_VRAM1:</div><div class='add'>+		r = xe_ttm_vram_mgr_alloc_sgt(xe_bo_device(bo),</div><div class='add'>+					      bo-&gt;ttm.resource, 0,</div><div class='add'>+					      bo-&gt;ttm.base.size, attach-&gt;dev,</div><div class='add'>+					      dir, &amp;sgt);</div><div class='add'>+		if (r)</div><div class='add'>+			return ERR_PTR(r);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return sgt;</div><div class='add'>+</div><div class='add'>+error_free:</div><div class='add'>+	sg_free_table(sgt);</div><div class='add'>+	kfree(sgt);</div><div class='add'>+	return ERR_PTR(-EBUSY);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_dma_buf_unmap(struct dma_buf_attachment *attach,</div><div class='add'>+			     struct sg_table *sgt,</div><div class='add'>+			     enum dma_data_direction dir)</div><div class='add'>+{</div><div class='add'>+	struct dma_buf *dma_buf = attach-&gt;dmabuf;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(dma_buf-&gt;priv);</div><div class='add'>+</div><div class='add'>+	if (!xe_bo_is_vram(bo)) {</div><div class='add'>+		dma_unmap_sgtable(attach-&gt;dev, sgt, dir, 0);</div><div class='add'>+		sg_free_table(sgt);</div><div class='add'>+		kfree(sgt);</div><div class='add'>+	} else {</div><div class='add'>+		xe_ttm_vram_mgr_free_sgt(attach-&gt;dev, dir, sgt);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,</div><div class='add'>+				       enum dma_data_direction direction)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = dma_buf-&gt;priv;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+	bool reads =  (direction == DMA_BIDIRECTIONAL ||</div><div class='add'>+		       direction == DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='add'>+	if (!reads)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Can we do interruptible lock here? */</div><div class='add'>+	xe_bo_lock(bo, false);</div><div class='add'>+	(void)xe_bo_migrate(bo, XE_PL_TT);</div><div class='add'>+	xe_bo_unlock(bo);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct dma_buf_ops xe_dmabuf_ops = {</div><div class='add'>+	.attach = xe_dma_buf_attach,</div><div class='add'>+	.detach = xe_dma_buf_detach,</div><div class='add'>+	.pin = xe_dma_buf_pin,</div><div class='add'>+	.unpin = xe_dma_buf_unpin,</div><div class='add'>+	.map_dma_buf = xe_dma_buf_map,</div><div class='add'>+	.unmap_dma_buf = xe_dma_buf_unmap,</div><div class='add'>+	.release = drm_gem_dmabuf_release,</div><div class='add'>+	.begin_cpu_access = xe_dma_buf_begin_cpu_access,</div><div class='add'>+	.mmap = drm_gem_dmabuf_mmap,</div><div class='add'>+	.vmap = drm_gem_dmabuf_vmap,</div><div class='add'>+	.vunmap = drm_gem_dmabuf_vunmap,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dma_buf *xe_gem_prime_export(struct drm_gem_object *obj, int flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+	struct dma_buf *buf;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;vm)</div><div class='add'>+		return ERR_PTR(-EPERM);</div><div class='add'>+</div><div class='add'>+	buf = drm_gem_prime_export(obj, flags);</div><div class='add'>+	if (!IS_ERR(buf))</div><div class='add'>+		buf-&gt;ops = &amp;xe_dmabuf_ops;</div><div class='add'>+</div><div class='add'>+	return buf;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct drm_gem_object *</div><div class='add'>+xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage,</div><div class='add'>+		    struct dma_buf *dma_buf)</div><div class='add'>+{</div><div class='add'>+	struct dma_resv *resv = dma_buf-&gt;resv;</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dma_resv_lock(resv, NULL);</div><div class='add'>+	bo = ___xe_bo_create_locked(xe, storage, NULL, resv, NULL, dma_buf-&gt;size,</div><div class='add'>+				    0, /* Will require 1way or 2way for vm_bind */</div><div class='add'>+				    ttm_bo_type_sg, XE_BO_CREATE_SYSTEM_BIT);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		ret = PTR_ERR(bo);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+	dma_resv_unlock(resv);</div><div class='add'>+</div><div class='add'>+	return &amp;bo-&gt;ttm.base;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	dma_resv_unlock(resv);</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_dma_buf_move_notify(struct dma_buf_attachment *attach)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = attach-&gt;importer_priv;</div><div class='add'>+	struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_bo_evict(bo, false));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_buf_attach_ops xe_dma_buf_attach_ops = {</div><div class='add'>+	.allow_peer2peer = true,</div><div class='add'>+	.move_notify = xe_dma_buf_move_notify</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+</div><div class='add'>+struct dma_buf_test_params {</div><div class='add'>+	struct xe_test_priv base;</div><div class='add'>+	const struct dma_buf_attach_ops *attach_ops;</div><div class='add'>+	bool force_different_devices;</div><div class='add'>+	u32 mem_mask;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_dma_buf_test_params(_priv) \</div><div class='add'>+	container_of(_priv, struct dma_buf_test_params, base)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+struct drm_gem_object *xe_gem_prime_import(struct drm_device *dev,</div><div class='add'>+					   struct dma_buf *dma_buf)</div><div class='add'>+{</div><div class='add'>+	XE_TEST_DECLARE(struct dma_buf_test_params *test =</div><div class='add'>+			to_dma_buf_test_params</div><div class='add'>+			(xe_cur_kunit_priv(XE_TEST_LIVE_DMA_BUF));)</div><div class='add'>+	const struct dma_buf_attach_ops *attach_ops;</div><div class='add'>+	struct dma_buf_attachment *attach;</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	if (dma_buf-&gt;ops == &amp;xe_dmabuf_ops) {</div><div class='add'>+		obj = dma_buf-&gt;priv;</div><div class='add'>+		if (obj-&gt;dev == dev &amp;&amp;</div><div class='add'>+		    !XE_TEST_ONLY(test &amp;&amp; test-&gt;force_different_devices)) {</div><div class='add'>+			/*</div><div class='add'>+			 * Importing dmabuf exported from out own gem increases</div><div class='add'>+			 * refcount on gem itself instead of f_count of dmabuf.</div><div class='add'>+			 */</div><div class='add'>+			drm_gem_object_get(obj);</div><div class='add'>+			return obj;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Don't publish the bo until we have a valid attachment, and a</div><div class='add'>+	 * valid attachment needs the bo address. So pre-create a bo before</div><div class='add'>+	 * creating the attachment and publish.</div><div class='add'>+	 */</div><div class='add'>+	bo = xe_bo_alloc();</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return ERR_CAST(bo);</div><div class='add'>+</div><div class='add'>+	attach_ops = &amp;xe_dma_buf_attach_ops;</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+	if (test)</div><div class='add'>+		attach_ops = test-&gt;attach_ops;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	attach = dma_buf_dynamic_attach(dma_buf, dev-&gt;dev, attach_ops, &amp;bo-&gt;ttm.base);</div><div class='add'>+	if (IS_ERR(attach)) {</div><div class='add'>+		obj = ERR_CAST(attach);</div><div class='add'>+		goto out_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Errors here will take care of freeing the bo. */</div><div class='add'>+	obj = xe_dma_buf_init_obj(dev, bo, dma_buf);</div><div class='add'>+	if (IS_ERR(obj))</div><div class='add'>+		return obj;</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+	get_dma_buf(dma_buf);</div><div class='add'>+	obj-&gt;import_attach = attach;</div><div class='add'>+	return obj;</div><div class='add'>+</div><div class='add'>+out_err:</div><div class='add'>+	xe_bo_free(bo);</div><div class='add'>+</div><div class='add'>+	return obj;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_dma_buf.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_dma_buf.h b/drivers/gpu/drm/xe/xe_dma_buf.h<br/>new file mode 100644<br/>index 000000000000..861dd28a862c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_dma_buf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_dma_buf.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DMA_BUF_H_</div><div class='add'>+#define _XE_DMA_BUF_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_gem.h&gt;</div><div class='add'>+</div><div class='add'>+struct dma_buf *xe_gem_prime_export(struct drm_gem_object *obj, int flags);</div><div class='add'>+struct drm_gem_object *xe_gem_prime_import(struct drm_device *dev,</div><div class='add'>+					   struct dma_buf *dma_buf);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_drm_client.c b/drivers/gpu/drm/xe/xe_drm_client.c<br/>new file mode 100644<br/>index 000000000000..82d1305e831f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_drm_client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drm_client.c</a></div><div class='hunk'>@@ -0,0 +1,204 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_bo_types.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_drm_client_alloc() - Allocate drm client</div><div class='add'>+ * @void: No arg</div><div class='add'>+ *</div><div class='add'>+ * Allocate drm client struct to track client memory against</div><div class='add'>+ * same till client life. Call this API whenever new client</div><div class='add'>+ * has opened xe device.</div><div class='add'>+ *</div><div class='add'>+ * Return: pointer to client struct or NULL if can't allocate</div><div class='add'>+ */</div><div class='add'>+struct xe_drm_client *xe_drm_client_alloc(void)</div><div class='add'>+{</div><div class='add'>+	struct xe_drm_client *client;</div><div class='add'>+</div><div class='add'>+	client = kzalloc(sizeof(*client), GFP_KERNEL);</div><div class='add'>+	if (!client)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	kref_init(&amp;client-&gt;kref);</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	spin_lock_init(&amp;client-&gt;bos_lock);</div><div class='add'>+	INIT_LIST_HEAD(&amp;client-&gt;bos_list);</div><div class='add'>+#endif</div><div class='add'>+	return client;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __xe_drm_client_free() - Free client struct</div><div class='add'>+ * @kref: The reference</div><div class='add'>+ *</div><div class='add'>+ * This frees client struct. Call this API when xe device is closed</div><div class='add'>+ * by drm client.</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+void __xe_drm_client_free(struct kref *kref)</div><div class='add'>+{</div><div class='add'>+	struct xe_drm_client *client =</div><div class='add'>+		container_of(kref, typeof(*client), kref);</div><div class='add'>+</div><div class='add'>+	kfree(client);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+/**</div><div class='add'>+ * xe_drm_client_add_bo() - Add BO for tracking client mem usage</div><div class='add'>+ * @client: The drm client ptr</div><div class='add'>+ * @bo: The xe BO ptr</div><div class='add'>+ *</div><div class='add'>+ * Add all BO created by individual drm client by calling this function.</div><div class='add'>+ * This helps in tracking client memory usage.</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+void xe_drm_client_add_bo(struct xe_drm_client *client,</div><div class='add'>+			  struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(bo-&gt;client);</div><div class='add'>+	XE_WARN_ON(!list_empty(&amp;bo-&gt;client_link));</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;client-&gt;bos_lock);</div><div class='add'>+	bo-&gt;client = xe_drm_client_get(client);</div><div class='add'>+	list_add_tail_rcu(&amp;bo-&gt;client_link, &amp;client-&gt;bos_list);</div><div class='add'>+	spin_unlock(&amp;client-&gt;bos_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_drm_client_remove_bo() - Remove BO for tracking client mem usage</div><div class='add'>+ * @bo: The xe BO ptr</div><div class='add'>+ *</div><div class='add'>+ * Remove all BO removed by individual drm client by calling this function.</div><div class='add'>+ * This helps in tracking client memory usage.</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+void xe_drm_client_remove_bo(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_drm_client *client = bo-&gt;client;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;client-&gt;bos_lock);</div><div class='add'>+	list_del_rcu(&amp;bo-&gt;client_link);</div><div class='add'>+	spin_unlock(&amp;client-&gt;bos_lock);</div><div class='add'>+</div><div class='add'>+	xe_drm_client_put(client);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void bo_meminfo(struct xe_bo *bo,</div><div class='add'>+		       struct drm_memory_stats stats[TTM_NUM_MEM_TYPES])</div><div class='add'>+{</div><div class='add'>+	u64 sz = bo-&gt;size;</div><div class='add'>+	u32 mem_type;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;placement.placement)</div><div class='add'>+		mem_type = bo-&gt;placement.placement-&gt;mem_type;</div><div class='add'>+	else</div><div class='add'>+		mem_type = XE_PL_TT;</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;ttm.base.handle_count &gt; 1)</div><div class='add'>+		stats[mem_type].shared += sz;</div><div class='add'>+	else</div><div class='add'>+		stats[mem_type].private += sz;</div><div class='add'>+</div><div class='add'>+	if (xe_bo_has_pages(bo)) {</div><div class='add'>+		stats[mem_type].resident += sz;</div><div class='add'>+</div><div class='add'>+		if (!dma_resv_test_signaled(bo-&gt;ttm.base.resv,</div><div class='add'>+					    DMA_RESV_USAGE_BOOKKEEP))</div><div class='add'>+			stats[mem_type].active += sz;</div><div class='add'>+		else if (mem_type == XE_PL_SYSTEM)</div><div class='add'>+			stats[mem_type].purgeable += sz;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void show_meminfo(struct drm_printer *p, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	static const char *const mem_type_to_name[TTM_NUM_MEM_TYPES]  = {</div><div class='add'>+		[XE_PL_SYSTEM] = "system",</div><div class='add'>+		[XE_PL_TT] = "gtt",</div><div class='add'>+		[XE_PL_VRAM0] = "vram0",</div><div class='add'>+		[XE_PL_VRAM1] = "vram1",</div><div class='add'>+		[4 ... 6] = NULL,</div><div class='add'>+		[XE_PL_STOLEN] = "stolen"</div><div class='add'>+	};</div><div class='add'>+	struct drm_memory_stats stats[TTM_NUM_MEM_TYPES] = {};</div><div class='add'>+	struct xe_file *xef = file-&gt;driver_priv;</div><div class='add'>+	struct ttm_device *bdev = &amp;xef-&gt;xe-&gt;ttm;</div><div class='add'>+	struct ttm_resource_manager *man;</div><div class='add'>+	struct xe_drm_client *client;</div><div class='add'>+	struct drm_gem_object *obj;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	unsigned int id;</div><div class='add'>+	u32 mem_type;</div><div class='add'>+</div><div class='add'>+	client = xef-&gt;client;</div><div class='add'>+</div><div class='add'>+	/* Public objects. */</div><div class='add'>+	spin_lock(&amp;file-&gt;table_lock);</div><div class='add'>+	idr_for_each_entry(&amp;file-&gt;object_idr, obj, id) {</div><div class='add'>+		struct xe_bo *bo = gem_to_xe_bo(obj);</div><div class='add'>+</div><div class='add'>+		bo_meminfo(bo, stats);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;file-&gt;table_lock);</div><div class='add'>+</div><div class='add'>+	/* Internal objects. */</div><div class='add'>+	spin_lock(&amp;client-&gt;bos_lock);</div><div class='add'>+	list_for_each_entry_rcu(bo, &amp;client-&gt;bos_list, client_link) {</div><div class='add'>+		if (!bo || !kref_get_unless_zero(&amp;bo-&gt;ttm.base.refcount))</div><div class='add'>+			continue;</div><div class='add'>+		bo_meminfo(bo, stats);</div><div class='add'>+		xe_bo_put(bo);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;client-&gt;bos_lock);</div><div class='add'>+</div><div class='add'>+	for (mem_type = XE_PL_SYSTEM; mem_type &lt; TTM_NUM_MEM_TYPES; ++mem_type) {</div><div class='add'>+		if (!mem_type_to_name[mem_type])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		man = ttm_manager_type(bdev, mem_type);</div><div class='add'>+</div><div class='add'>+		if (man) {</div><div class='add'>+			drm_print_memory_stats(p,</div><div class='add'>+					       &amp;stats[mem_type],</div><div class='add'>+					       DRM_GEM_OBJECT_RESIDENT |</div><div class='add'>+					       (mem_type != XE_PL_SYSTEM ? 0 :</div><div class='add'>+					       DRM_GEM_OBJECT_PURGEABLE),</div><div class='add'>+					       mem_type_to_name[mem_type]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_drm_client_fdinfo() - Callback for fdinfo interface</div><div class='add'>+ * @p: The drm_printer ptr</div><div class='add'>+ * @file: The drm_file ptr</div><div class='add'>+ *</div><div class='add'>+ * This is callabck for drm fdinfo interface. Register this callback</div><div class='add'>+ * in drm driver ops for show_fdinfo.</div><div class='add'>+ *</div><div class='add'>+ * Return: void</div><div class='add'>+ */</div><div class='add'>+void xe_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	show_meminfo(p, file);</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_drm_client.h b/drivers/gpu/drm/xe/xe_drm_client.h<br/>new file mode 100644<br/>index 000000000000..a9649aa36011<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_drm_client.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drm_client.h</a></div><div class='hunk'>@@ -0,0 +1,70 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DRM_CLIENT_H_</div><div class='add'>+#define _XE_DRM_CLIENT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/pid.h&gt;</div><div class='add'>+#include &lt;linux/rcupdate.h&gt;</div><div class='add'>+#include &lt;linux/sched.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_file;</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+struct xe_drm_client {</div><div class='add'>+	struct kref kref;</div><div class='add'>+	unsigned int id;</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+	/**</div><div class='add'>+	 * @bos_lock: lock protecting @bos_list</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t bos_lock;</div><div class='add'>+	/**</div><div class='add'>+	 * @bos_list: list of bos created by this client</div><div class='add'>+	 *</div><div class='add'>+	 * Protected by @bos_lock.</div><div class='add'>+	 */</div><div class='add'>+	struct list_head bos_list;</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+	static inline struct xe_drm_client *</div><div class='add'>+xe_drm_client_get(struct xe_drm_client *client)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;client-&gt;kref);</div><div class='add'>+	return client;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void __xe_drm_client_free(struct kref *kref);</div><div class='add'>+</div><div class='add'>+static inline void xe_drm_client_put(struct xe_drm_client *client)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;client-&gt;kref, __xe_drm_client_free);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_drm_client *xe_drm_client_alloc(void);</div><div class='add'>+static inline struct xe_drm_client *</div><div class='add'>+xe_drm_client_get(struct xe_drm_client *client);</div><div class='add'>+static inline void xe_drm_client_put(struct xe_drm_client *client);</div><div class='add'>+#ifdef CONFIG_PROC_FS</div><div class='add'>+void xe_drm_client_fdinfo(struct drm_printer *p, struct drm_file *file);</div><div class='add'>+void xe_drm_client_add_bo(struct xe_drm_client *client,</div><div class='add'>+			  struct xe_bo *bo);</div><div class='add'>+void xe_drm_client_remove_bo(struct xe_bo *bo);</div><div class='add'>+#else</div><div class='add'>+static inline void xe_drm_client_add_bo(struct xe_drm_client *client,</div><div class='add'>+					struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_drm_client_remove_bo(struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_drv.h b/drivers/gpu/drm/xe/xe_drv.h<br/>new file mode 100644<br/>index 000000000000..d45b71426cc8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_drv.h</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_DRV_H_</div><div class='add'>+#define _XE_DRV_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+</div><div class='add'>+#define DRIVER_NAME		"xe"</div><div class='add'>+#define DRIVER_DESC		"Intel Xe Graphics"</div><div class='add'>+#define DRIVER_DATE		"20201103"</div><div class='add'>+</div><div class='add'>+/* Interface history:</div><div class='add'>+ *</div><div class='add'>+ * 1.1: Original.</div><div class='add'>+ */</div><div class='add'>+#define DRIVER_MAJOR		1</div><div class='add'>+#define DRIVER_MINOR		1</div><div class='add'>+#define DRIVER_PATCHLEVEL	0</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c<br/>new file mode 100644<br/>index 000000000000..b853feed9ccc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_exec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec.c</a></div><div class='hunk'>@@ -0,0 +1,351 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_exec.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;drm/drm_file.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_ring_ops_types.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_sync.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Execbuf (User GPU command submission)</div><div class='add'>+ *</div><div class='add'>+ * Execs have historically been rather complicated in DRM drivers (at least in</div><div class='add'>+ * the i915) because a few things:</div><div class='add'>+ *</div><div class='add'>+ * - Passing in a list BO which are read / written to creating implicit syncs</div><div class='add'>+ * - Binding at exec time</div><div class='add'>+ * - Flow controlling the ring at exec time</div><div class='add'>+ *</div><div class='add'>+ * In XE we avoid all of this complication by not allowing a BO list to be</div><div class='add'>+ * passed into an exec, using the dma-buf implicit sync uAPI, have binds as</div><div class='add'>+ * seperate operations, and using the DRM scheduler to flow control the ring.</div><div class='add'>+ * Let's deep dive on each of these.</div><div class='add'>+ *</div><div class='add'>+ * We can get away from a BO list by forcing the user to use in / out fences on</div><div class='add'>+ * every exec rather than the kernel tracking dependencies of BO (e.g. if the</div><div class='add'>+ * user knows an exec writes to a BO and reads from the BO in the next exec, it</div><div class='add'>+ * is the user's responsibility to pass in / out fence between the two execs).</div><div class='add'>+ *</div><div class='add'>+ * Implicit dependencies for external BOs are handled by using the dma-buf</div><div class='add'>+ * implicit dependency uAPI (TODO: add link). To make this works each exec must</div><div class='add'>+ * install the job's fence into the DMA_RESV_USAGE_WRITE slot of every external</div><div class='add'>+ * BO mapped in the VM.</div><div class='add'>+ *</div><div class='add'>+ * We do not allow a user to trigger a bind at exec time rather we have a VM</div><div class='add'>+ * bind IOCTL which uses the same in / out fence interface as exec. In that</div><div class='add'>+ * sense, a VM bind is basically the same operation as an exec from the user</div><div class='add'>+ * perspective. e.g. If an exec depends on a VM bind use the in / out fence</div><div class='add'>+ * interface (struct drm_xe_sync) to synchronize like syncing between two</div><div class='add'>+ * dependent execs.</div><div class='add'>+ *</div><div class='add'>+ * Although a user cannot trigger a bind, we still have to rebind userptrs in</div><div class='add'>+ * the VM that have been invalidated since the last exec, likewise we also have</div><div class='add'>+ * to rebind BOs that have been evicted by the kernel. We schedule these rebinds</div><div class='add'>+ * behind any pending kernel operations on any external BOs in VM or any BOs</div><div class='add'>+ * private to the VM. This is accomplished by the rebinds waiting on BOs</div><div class='add'>+ * DMA_RESV_USAGE_KERNEL slot (kernel ops) and kernel ops waiting on all BOs</div><div class='add'>+ * slots (inflight execs are in the DMA_RESV_USAGE_BOOKING for private BOs and</div><div class='add'>+ * in DMA_RESV_USAGE_WRITE for external BOs).</div><div class='add'>+ *</div><div class='add'>+ * Rebinds / dma-resv usage applies to non-compute mode VMs only as for compute</div><div class='add'>+ * mode VMs we use preempt fences and a rebind worker (TODO: add link).</div><div class='add'>+ *</div><div class='add'>+ * There is no need to flow control the ring in the exec as we write the ring at</div><div class='add'>+ * submission time and set the DRM scheduler max job limit SIZE_OF_RING /</div><div class='add'>+ * MAX_JOB_SIZE. The DRM scheduler will then hold all jobs until space in the</div><div class='add'>+ * ring is available.</div><div class='add'>+ *</div><div class='add'>+ * All of this results in a rather simple exec implementation.</div><div class='add'>+ *</div><div class='add'>+ * Flow</div><div class='add'>+ * ~~~~</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	Parse input arguments</div><div class='add'>+ *	Wait for any async VM bind passed as in-fences to start</div><div class='add'>+ *	&lt;----------------------------------------------------------------------|</div><div class='add'>+ *	Lock global VM lock in read mode                                       |</div><div class='add'>+ *	Pin userptrs (also finds userptr invalidated since last exec)          |</div><div class='add'>+ *	Lock exec (VM dma-resv lock, external BOs dma-resv locks)              |</div><div class='add'>+ *	Validate BOs that have been evicted                                    |</div><div class='add'>+ *	Create job                                                             |</div><div class='add'>+ *	Rebind invalidated userptrs + evicted BOs (non-compute-mode)           |</div><div class='add'>+ *	Add rebind fence dependency to job                                     |</div><div class='add'>+ *	Add job VM dma-resv bookkeeping slot (non-compute mode)                |</div><div class='add'>+ *	Add job to external BOs dma-resv write slots (non-compute mode)        |</div><div class='add'>+ *	Check if any userptrs invalidated since pin ------ Drop locks ---------|</div><div class='add'>+ *	Install in / out fences for job</div><div class='add'>+ *	Submit job</div><div class='add'>+ *	Unlock all</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static int xe_exec_fn(struct drm_gpuvm_exec *vm_exec)</div><div class='add'>+{</div><div class='add'>+	return drm_gpuvm_validate(vm_exec-&gt;vm, &amp;vm_exec-&gt;exec);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_exec *args = data;</div><div class='add'>+	struct drm_xe_sync __user *syncs_user = u64_to_user_ptr(args-&gt;syncs);</div><div class='add'>+	u64 __user *addresses_user = u64_to_user_ptr(args-&gt;address);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	struct xe_sync_entry *syncs = NULL;</div><div class='add'>+	u64 addresses[XE_HW_ENGINE_MAX_INSTANCE];</div><div class='add'>+	struct drm_gpuvm_exec vm_exec = {.extra.fn = xe_exec_fn};</div><div class='add'>+	struct drm_exec *exec = &amp;vm_exec.exec;</div><div class='add'>+	u32 i, num_syncs = 0;</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct dma_fence *rebind_fence;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	bool write_locked, skip_retry = false;</div><div class='add'>+	ktime_t end = 0;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;pad[0] || args-&gt;pad[1] || args-&gt;pad[2]) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q = xe_exec_queue_lookup(xef, args-&gt;exec_queue_id);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !q))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;num_batch_buffer &amp;&amp;</div><div class='add'>+			 q-&gt;width != args-&gt;num_batch_buffer))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, q-&gt;flags &amp; EXEC_QUEUE_FLAG_BANNED)) {</div><div class='add'>+		err = -ECANCELED;</div><div class='add'>+		goto err_exec_queue;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (args-&gt;num_syncs) {</div><div class='add'>+		syncs = kcalloc(args-&gt;num_syncs, sizeof(*syncs), GFP_KERNEL);</div><div class='add'>+		if (!syncs) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_exec_queue;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vm = q-&gt;vm;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_syncs; i++) {</div><div class='add'>+		err = xe_sync_entry_parse(xe, xef, &amp;syncs[num_syncs++],</div><div class='add'>+					  &amp;syncs_user[i], SYNC_PARSE_FLAG_EXEC |</div><div class='add'>+					  (xe_vm_in_lr_mode(vm) ?</div><div class='add'>+					   SYNC_PARSE_FLAG_LR_MODE : 0));</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_syncs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		err = __copy_from_user(addresses, addresses_user, sizeof(u64) *</div><div class='add'>+				       q-&gt;width);</div><div class='add'>+		if (err) {</div><div class='add'>+			err = -EFAULT;</div><div class='add'>+			goto err_syncs;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+retry:</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm) &amp;&amp; xe_vm_userptr_check_repin(vm)) {</div><div class='add'>+		err = down_write_killable(&amp;vm-&gt;lock);</div><div class='add'>+		write_locked = true;</div><div class='add'>+	} else {</div><div class='add'>+		/* We don't allow execs while the VM is in error state */</div><div class='add'>+		err = down_read_interruptible(&amp;vm-&gt;lock);</div><div class='add'>+		write_locked = false;</div><div class='add'>+	}</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_syncs;</div><div class='add'>+</div><div class='add'>+	if (write_locked) {</div><div class='add'>+		err = xe_vm_userptr_pin(vm);</div><div class='add'>+		downgrade_write(&amp;vm-&gt;lock);</div><div class='add'>+		write_locked = false;</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_unlock_list;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vm_exec.vm = &amp;vm-&gt;gpuvm;</div><div class='add'>+	vm_exec.num_fences = 1 + vm-&gt;xe-&gt;info.tile_count;</div><div class='add'>+	vm_exec.flags = DRM_EXEC_INTERRUPTIBLE_WAIT;</div><div class='add'>+	if (xe_vm_in_lr_mode(vm)) {</div><div class='add'>+		drm_exec_init(exec, vm_exec.flags, 0);</div><div class='add'>+	} else {</div><div class='add'>+		err = drm_gpuvm_exec_lock(&amp;vm_exec);</div><div class='add'>+		if (err) {</div><div class='add'>+			if (xe_vm_validate_should_retry(exec, err, &amp;end))</div><div class='add'>+				err = -EAGAIN;</div><div class='add'>+			goto err_unlock_list;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_vm_is_closed_or_banned(q-&gt;vm)) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Trying to schedule after vm is closed or banned\n");</div><div class='add'>+		err = -ECANCELED;</div><div class='add'>+		goto err_exec;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!args-&gt;num_batch_buffer) {</div><div class='add'>+		if (!xe_vm_in_lr_mode(vm)) {</div><div class='add'>+			struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+			fence = xe_sync_in_fence_get(syncs, num_syncs, q, vm);</div><div class='add'>+			if (IS_ERR(fence)) {</div><div class='add'>+				err = PTR_ERR(fence);</div><div class='add'>+				goto err_exec;</div><div class='add'>+			}</div><div class='add'>+			for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+				xe_sync_entry_signal(&amp;syncs[i], NULL, fence);</div><div class='add'>+			xe_exec_queue_last_fence_set(q, vm, fence);</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		goto err_exec;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_lr(q) &amp;&amp; xe_exec_queue_ring_full(q)) {</div><div class='add'>+		err = -EWOULDBLOCK;	/* Aliased to -EAGAIN */</div><div class='add'>+		skip_retry = true;</div><div class='add'>+		goto err_exec;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	job = xe_sched_job_create(q, xe_exec_queue_is_parallel(q) ?</div><div class='add'>+				  addresses : &amp;args-&gt;address);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		err = PTR_ERR(job);</div><div class='add'>+		goto err_exec;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Rebind any invalidated userptr or evicted BOs in the VM, non-compute</div><div class='add'>+	 * VM mode only.</div><div class='add'>+	 */</div><div class='add'>+	rebind_fence = xe_vm_rebind(vm, false);</div><div class='add'>+	if (IS_ERR(rebind_fence)) {</div><div class='add'>+		err = PTR_ERR(rebind_fence);</div><div class='add'>+		goto err_put_job;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We store the rebind_fence in the VM so subsequent execs don't get</div><div class='add'>+	 * scheduled before the rebinds of userptrs / evicted BOs is complete.</div><div class='add'>+	 */</div><div class='add'>+	if (rebind_fence) {</div><div class='add'>+		dma_fence_put(vm-&gt;rebind_fence);</div><div class='add'>+		vm-&gt;rebind_fence = rebind_fence;</div><div class='add'>+	}</div><div class='add'>+	if (vm-&gt;rebind_fence) {</div><div class='add'>+		if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,</div><div class='add'>+			     &amp;vm-&gt;rebind_fence-&gt;flags)) {</div><div class='add'>+			dma_fence_put(vm-&gt;rebind_fence);</div><div class='add'>+			vm-&gt;rebind_fence = NULL;</div><div class='add'>+		} else {</div><div class='add'>+			dma_fence_get(vm-&gt;rebind_fence);</div><div class='add'>+			err = drm_sched_job_add_dependency(&amp;job-&gt;drm,</div><div class='add'>+							   vm-&gt;rebind_fence);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_put_job;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait behind munmap style rebinds */</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm)) {</div><div class='add'>+		err = drm_sched_job_add_resv_dependencies(&amp;job-&gt;drm,</div><div class='add'>+							  xe_vm_resv(vm),</div><div class='add'>+							  DMA_RESV_USAGE_KERNEL);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_put_job;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_syncs &amp;&amp; !err; i++)</div><div class='add'>+		err = xe_sync_entry_add_deps(&amp;syncs[i], job);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_put_job;</div><div class='add'>+</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm)) {</div><div class='add'>+		err = xe_sched_job_last_fence_add_dep(job, vm);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_put_job;</div><div class='add'>+</div><div class='add'>+		err = down_read_interruptible(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_put_job;</div><div class='add'>+</div><div class='add'>+		err = __xe_vm_userptr_needs_repin(vm);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_repin;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Point of no return, if we error after this point just set an error on</div><div class='add'>+	 * the job and let the DRM scheduler / backend clean up the job.</div><div class='add'>+	 */</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm))</div><div class='add'>+		drm_gpuvm_resv_add_fence(&amp;vm-&gt;gpuvm, exec, &amp;job-&gt;drm.s_fence-&gt;finished,</div><div class='add'>+					 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_WRITE);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+		xe_sync_entry_signal(&amp;syncs[i], job,</div><div class='add'>+				     &amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_lr(q))</div><div class='add'>+		q-&gt;ring_ops-&gt;emit_job(job);</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm))</div><div class='add'>+		xe_exec_queue_last_fence_set(q, vm, &amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+	xe_vm_reactivate_rebind(vm);</div><div class='add'>+</div><div class='add'>+	if (!err &amp;&amp; !xe_vm_in_lr_mode(vm)) {</div><div class='add'>+		spin_lock(&amp;xe-&gt;ttm.lru_lock);</div><div class='add'>+		ttm_lru_bulk_move_tail(&amp;vm-&gt;lru_bulk_move);</div><div class='add'>+		spin_unlock(&amp;xe-&gt;ttm.lru_lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err_repin:</div><div class='add'>+	if (!xe_vm_in_lr_mode(vm))</div><div class='add'>+		up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+err_put_job:</div><div class='add'>+	if (err)</div><div class='add'>+		xe_sched_job_put(job);</div><div class='add'>+err_exec:</div><div class='add'>+	drm_exec_fini(exec);</div><div class='add'>+err_unlock_list:</div><div class='add'>+	if (write_locked)</div><div class='add'>+		up_write(&amp;vm-&gt;lock);</div><div class='add'>+	else</div><div class='add'>+		up_read(&amp;vm-&gt;lock);</div><div class='add'>+	if (err == -EAGAIN &amp;&amp; !skip_retry)</div><div class='add'>+		goto retry;</div><div class='add'>+err_syncs:</div><div class='add'>+	for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+		xe_sync_entry_cleanup(&amp;syncs[i]);</div><div class='add'>+	kfree(syncs);</div><div class='add'>+err_exec_queue:</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_exec.h b/drivers/gpu/drm/xe/xe_exec.h<br/>new file mode 100644<br/>index 000000000000..e4932494cea3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_exec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_EXEC_H_</div><div class='add'>+#define _XE_EXEC_H_</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_file;</div><div class='add'>+</div><div class='add'>+int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c<br/>new file mode 100644<br/>index 000000000000..bcfc4127c7c5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_exec_queue.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue.c</a></div><div class='hunk'>@@ -0,0 +1,961 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/nospec.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_file.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine_class_sysfs.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_ring_ops_types.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+enum xe_exec_queue_sched_prop {</div><div class='add'>+	XE_EXEC_QUEUE_JOB_TIMEOUT = 0,</div><div class='add'>+	XE_EXEC_QUEUE_TIMESLICE = 1,</div><div class='add'>+	XE_EXEC_QUEUE_PREEMPT_TIMEOUT = 2,</div><div class='add'>+	XE_EXEC_QUEUE_SCHED_PROP_MAX = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct xe_exec_queue *__xe_exec_queue_create(struct xe_device *xe,</div><div class='add'>+						    struct xe_vm *vm,</div><div class='add'>+						    u32 logical_mask,</div><div class='add'>+						    u16 width, struct xe_hw_engine *hwe,</div><div class='add'>+						    u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* only kernel queues can be permanent */</div><div class='add'>+	XE_WARN_ON((flags &amp; EXEC_QUEUE_FLAG_PERMANENT) &amp;&amp; !(flags &amp; EXEC_QUEUE_FLAG_KERNEL));</div><div class='add'>+</div><div class='add'>+	q = kzalloc(sizeof(*q) + sizeof(struct xe_lrc) * width, GFP_KERNEL);</div><div class='add'>+	if (!q)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	kref_init(&amp;q-&gt;refcount);</div><div class='add'>+	q-&gt;flags = flags;</div><div class='add'>+	q-&gt;hwe = hwe;</div><div class='add'>+	q-&gt;gt = gt;</div><div class='add'>+	if (vm)</div><div class='add'>+		q-&gt;vm = xe_vm_get(vm);</div><div class='add'>+	q-&gt;class = hwe-&gt;class;</div><div class='add'>+	q-&gt;width = width;</div><div class='add'>+	q-&gt;logical_mask = logical_mask;</div><div class='add'>+	q-&gt;fence_irq = &amp;gt-&gt;fence_irq[hwe-&gt;class];</div><div class='add'>+	q-&gt;ring_ops = gt-&gt;ring_ops[hwe-&gt;class];</div><div class='add'>+	q-&gt;ops = gt-&gt;exec_queue_ops;</div><div class='add'>+	INIT_LIST_HEAD(&amp;q-&gt;persistent.link);</div><div class='add'>+	INIT_LIST_HEAD(&amp;q-&gt;compute.link);</div><div class='add'>+	INIT_LIST_HEAD(&amp;q-&gt;multi_gt_link);</div><div class='add'>+</div><div class='add'>+	q-&gt;sched_props.timeslice_us = hwe-&gt;eclass-&gt;sched_props.timeslice_us;</div><div class='add'>+	q-&gt;sched_props.preempt_timeout_us =</div><div class='add'>+				hwe-&gt;eclass-&gt;sched_props.preempt_timeout_us;</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL &amp;&amp;</div><div class='add'>+	    q-&gt;flags &amp; EXEC_QUEUE_FLAG_HIGH_PRIORITY)</div><div class='add'>+		q-&gt;sched_props.priority = XE_EXEC_QUEUE_PRIORITY_KERNEL;</div><div class='add'>+	else</div><div class='add'>+		q-&gt;sched_props.priority = XE_EXEC_QUEUE_PRIORITY_NORMAL;</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		q-&gt;parallel.composite_fence_ctx = dma_fence_context_alloc(1);</div><div class='add'>+		q-&gt;parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO;</div><div class='add'>+	}</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM) {</div><div class='add'>+		q-&gt;bind.fence_ctx = dma_fence_context_alloc(1);</div><div class='add'>+		q-&gt;bind.fence_seqno = XE_FENCE_INITIAL_SEQNO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; width; ++i) {</div><div class='add'>+		err = xe_lrc_init(q-&gt;lrc + i, hwe, q, vm, SZ_16K);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_lrc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = q-&gt;ops-&gt;init(q);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_lrc;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Normally the user vm holds an rpm ref to keep the device</div><div class='add'>+	 * awake, and the context holds a ref for the vm, however for</div><div class='add'>+	 * some engines we use the kernels migrate vm underneath which offers no</div><div class='add'>+	 * such rpm ref, or we lack a vm. Make sure we keep a ref here, so we</div><div class='add'>+	 * can perform GuC CT actions when needed. Caller is expected to have</div><div class='add'>+	 * already grabbed the rpm ref outside any sensitive locks.</div><div class='add'>+	 */</div><div class='add'>+	if (!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERMANENT) &amp;&amp; (q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM || !vm))</div><div class='add'>+		drm_WARN_ON(&amp;xe-&gt;drm, !xe_device_mem_access_get_if_ongoing(xe));</div><div class='add'>+</div><div class='add'>+	return q;</div><div class='add'>+</div><div class='add'>+err_lrc:</div><div class='add'>+	for (i = i - 1; i &gt;= 0; --i)</div><div class='add'>+		xe_lrc_finish(q-&gt;lrc + i);</div><div class='add'>+	kfree(q);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm,</div><div class='add'>+					   u32 logical_mask, u16 width,</div><div class='add'>+					   struct xe_hw_engine *hwe, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (vm) {</div><div class='add'>+		err = xe_vm_lock(vm, true);</div><div class='add'>+		if (err)</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+	}</div><div class='add'>+	q = __xe_exec_queue_create(xe, vm, logical_mask, width, hwe, flags);</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_unlock(vm);</div><div class='add'>+</div><div class='add'>+	return q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+						 struct xe_vm *vm,</div><div class='add'>+						 enum xe_engine_class class, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe, *hwe0 = NULL;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 logical_mask = 0;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		if (xe_hw_engine_is_reserved(hwe))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (hwe-&gt;class == class) {</div><div class='add'>+			logical_mask |= BIT(hwe-&gt;logical_instance);</div><div class='add'>+			if (!hwe0)</div><div class='add'>+				hwe0 = hwe;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!logical_mask)</div><div class='add'>+		return ERR_PTR(-ENODEV);</div><div class='add'>+</div><div class='add'>+	return xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_destroy(struct kref *ref)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount);</div><div class='add'>+	struct xe_exec_queue *eq, *next;</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_last_fence_put_unlocked(q);</div><div class='add'>+	if (!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD)) {</div><div class='add'>+		list_for_each_entry_safe(eq, next, &amp;q-&gt;multi_gt_list,</div><div class='add'>+					 multi_gt_link)</div><div class='add'>+			xe_exec_queue_put(eq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q-&gt;ops-&gt;fini(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_fini(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; q-&gt;width; ++i)</div><div class='add'>+		xe_lrc_finish(q-&gt;lrc + i);</div><div class='add'>+	if (!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERMANENT) &amp;&amp; (q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM || !q-&gt;vm))</div><div class='add'>+		xe_device_mem_access_put(gt_to_xe(q-&gt;gt));</div><div class='add'>+	if (q-&gt;vm)</div><div class='add'>+		xe_vm_put(q-&gt;vm);</div><div class='add'>+</div><div class='add'>+	kfree(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_assign_name(struct xe_exec_queue *q, u32 instance)</div><div class='add'>+{</div><div class='add'>+	switch (q-&gt;class) {</div><div class='add'>+	case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+		sprintf(q-&gt;name, "rcs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_DECODE:</div><div class='add'>+		sprintf(q-&gt;name, "vcs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:</div><div class='add'>+		sprintf(q-&gt;name, "vecs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	case XE_ENGINE_CLASS_COPY:</div><div class='add'>+		sprintf(q-&gt;name, "bcs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+		sprintf(q-&gt;name, "ccs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	case XE_ENGINE_CLASS_OTHER:</div><div class='add'>+		sprintf(q-&gt;name, "gsccs%d", instance);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON(q-&gt;class);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	q = xa_load(&amp;xef-&gt;exec_queue.xa, id);</div><div class='add'>+	if (q)</div><div class='add'>+		xe_exec_queue_get(q);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+</div><div class='add'>+	return q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum xe_exec_queue_priority</div><div class='add'>+xe_exec_queue_device_get_max_priority(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return capable(CAP_SYS_NICE) ? XE_EXEC_QUEUE_PRIORITY_HIGH :</div><div class='add'>+				       XE_EXEC_QUEUE_PRIORITY_NORMAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_priority(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				   u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	if (XE_IOCTL_DBG(xe, value &gt; XE_EXEC_QUEUE_PRIORITY_HIGH))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, value &gt; xe_exec_queue_device_get_max_priority(xe)))</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	return q-&gt;ops-&gt;set_priority(q, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_exec_queue_enforce_schedule_limit(void)</div><div class='add'>+{</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT)</div><div class='add'>+	return true;</div><div class='add'>+#else</div><div class='add'>+	return !capable(CAP_SYS_NICE);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_exec_queue_get_prop_minmax(struct xe_hw_engine_class_intf *eclass,</div><div class='add'>+			      enum xe_exec_queue_sched_prop prop,</div><div class='add'>+			      u32 *min, u32 *max)</div><div class='add'>+{</div><div class='add'>+	switch (prop) {</div><div class='add'>+	case XE_EXEC_QUEUE_JOB_TIMEOUT:</div><div class='add'>+		*min = eclass-&gt;sched_props.job_timeout_min;</div><div class='add'>+		*max = eclass-&gt;sched_props.job_timeout_max;</div><div class='add'>+		break;</div><div class='add'>+	case XE_EXEC_QUEUE_TIMESLICE:</div><div class='add'>+		*min = eclass-&gt;sched_props.timeslice_min;</div><div class='add'>+		*max = eclass-&gt;sched_props.timeslice_max;</div><div class='add'>+		break;</div><div class='add'>+	case XE_EXEC_QUEUE_PREEMPT_TIMEOUT:</div><div class='add'>+		*min = eclass-&gt;sched_props.preempt_timeout_min;</div><div class='add'>+		*max = eclass-&gt;sched_props.preempt_timeout_max;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT)</div><div class='add'>+	if (capable(CAP_SYS_NICE)) {</div><div class='add'>+		switch (prop) {</div><div class='add'>+		case XE_EXEC_QUEUE_JOB_TIMEOUT:</div><div class='add'>+			*min = XE_HW_ENGINE_JOB_TIMEOUT_MIN;</div><div class='add'>+			*max = XE_HW_ENGINE_JOB_TIMEOUT_MAX;</div><div class='add'>+			break;</div><div class='add'>+		case XE_EXEC_QUEUE_TIMESLICE:</div><div class='add'>+			*min = XE_HW_ENGINE_TIMESLICE_MIN;</div><div class='add'>+			*max = XE_HW_ENGINE_TIMESLICE_MAX;</div><div class='add'>+			break;</div><div class='add'>+		case XE_EXEC_QUEUE_PREEMPT_TIMEOUT:</div><div class='add'>+			*min = XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN;</div><div class='add'>+			*max = XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_timeslice(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				    u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	u32 min = 0, max = 0;</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_get_prop_minmax(q-&gt;hwe-&gt;eclass,</div><div class='add'>+				      XE_EXEC_QUEUE_TIMESLICE, &amp;min, &amp;max);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_enforce_schedule_limit() &amp;&amp;</div><div class='add'>+	    !xe_hw_engine_timeout_in_range(value, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return q-&gt;ops-&gt;set_timeslice(q, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_preemption_timeout(struct xe_device *xe,</div><div class='add'>+					     struct xe_exec_queue *q, u64 value,</div><div class='add'>+					     bool create)</div><div class='add'>+{</div><div class='add'>+	u32 min = 0, max = 0;</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_get_prop_minmax(q-&gt;hwe-&gt;eclass,</div><div class='add'>+				      XE_EXEC_QUEUE_PREEMPT_TIMEOUT, &amp;min, &amp;max);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_enforce_schedule_limit() &amp;&amp;</div><div class='add'>+	    !xe_hw_engine_timeout_in_range(value, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return q-&gt;ops-&gt;set_preempt_timeout(q, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_persistence(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				      u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !create))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, xe_vm_in_preempt_fence_mode(q-&gt;vm)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (value)</div><div class='add'>+		q-&gt;flags |= EXEC_QUEUE_FLAG_PERSISTENT;</div><div class='add'>+	else</div><div class='add'>+		q-&gt;flags &amp;= ~EXEC_QUEUE_FLAG_PERSISTENT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_job_timeout(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				      u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	u32 min = 0, max = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !create))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_get_prop_minmax(q-&gt;hwe-&gt;eclass,</div><div class='add'>+				      XE_EXEC_QUEUE_JOB_TIMEOUT, &amp;min, &amp;max);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_enforce_schedule_limit() &amp;&amp;</div><div class='add'>+	    !xe_hw_engine_timeout_in_range(value, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return q-&gt;ops-&gt;set_job_timeout(q, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_acc_trigger(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				      u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !create))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !xe-&gt;info.has_usm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q-&gt;usm.acc_trigger = value;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_acc_notify(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				     u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !create))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !xe-&gt;info.has_usm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q-&gt;usm.acc_notify = value;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int exec_queue_set_acc_granularity(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+					  u64 value, bool create)</div><div class='add'>+{</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !create))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !xe-&gt;info.has_usm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (value &gt; DRM_XE_ACC_GRANULARITY_64M)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q-&gt;usm.acc_granularity = value;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe,</div><div class='add'>+					     struct xe_exec_queue *q,</div><div class='add'>+					     u64 value, bool create);</div><div class='add'>+</div><div class='add'>+static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = {</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify,</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int exec_queue_user_ext_set_property(struct xe_device *xe,</div><div class='add'>+					    struct xe_exec_queue *q,</div><div class='add'>+					    u64 extension,</div><div class='add'>+					    bool create)</div><div class='add'>+{</div><div class='add'>+	u64 __user *address = u64_to_user_ptr(extension);</div><div class='add'>+	struct drm_xe_ext_set_property ext;</div><div class='add'>+	int err;</div><div class='add'>+	u32 idx;</div><div class='add'>+</div><div class='add'>+	err = __copy_from_user(&amp;ext, address, sizeof(ext));</div><div class='add'>+	if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, ext.property &gt;=</div><div class='add'>+			 ARRAY_SIZE(exec_queue_set_property_funcs)) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, ext.pad))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs));</div><div class='add'>+	return exec_queue_set_property_funcs[idx](xe, q, ext.value,  create);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe,</div><div class='add'>+					       struct xe_exec_queue *q,</div><div class='add'>+					       u64 extension,</div><div class='add'>+					       bool create);</div><div class='add'>+</div><div class='add'>+static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = {</div><div class='add'>+	[DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_USER_EXTENSIONS	16</div><div class='add'>+static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,</div><div class='add'>+				      u64 extensions, int ext_number, bool create)</div><div class='add'>+{</div><div class='add'>+	u64 __user *address = u64_to_user_ptr(extensions);</div><div class='add'>+	struct drm_xe_user_extension ext;</div><div class='add'>+	int err;</div><div class='add'>+	u32 idx;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, ext_number &gt;= MAX_USER_EXTENSIONS))</div><div class='add'>+		return -E2BIG;</div><div class='add'>+</div><div class='add'>+	err = __copy_from_user(&amp;ext, address, sizeof(ext));</div><div class='add'>+	if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, ext.pad) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, ext.name &gt;=</div><div class='add'>+			 ARRAY_SIZE(exec_queue_user_extension_funcs)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	idx = array_index_nospec(ext.name,</div><div class='add'>+				 ARRAY_SIZE(exec_queue_user_extension_funcs));</div><div class='add'>+	err = exec_queue_user_extension_funcs[idx](xe, q, extensions, create);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (ext.next_extension)</div><div class='add'>+		return exec_queue_user_extensions(xe, q, ext.next_extension,</div><div class='add'>+					      ++ext_number, create);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const enum xe_engine_class user_to_xe_engine_class[] = {</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct xe_hw_engine *</div><div class='add'>+find_hw_engine(struct xe_device *xe,</div><div class='add'>+	       struct drm_xe_engine_class_instance eci)</div><div class='add'>+{</div><div class='add'>+	u32 idx;</div><div class='add'>+</div><div class='add'>+	if (eci.engine_class &gt; ARRAY_SIZE(user_to_xe_engine_class))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (eci.gt_id &gt;= xe-&gt;info.gt_count)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	idx = array_index_nospec(eci.engine_class,</div><div class='add'>+				 ARRAY_SIZE(user_to_xe_engine_class));</div><div class='add'>+</div><div class='add'>+	return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id),</div><div class='add'>+			       user_to_xe_engine_class[idx],</div><div class='add'>+			       eci.engine_instance, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 bind_exec_queue_logical_mask(struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+					struct drm_xe_engine_class_instance *eci,</div><div class='add'>+					u16 width, u16 num_placements)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 logical_mask = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, width != 1))</div><div class='add'>+		return 0;</div><div class='add'>+	if (XE_IOCTL_DBG(xe, num_placements != 1))</div><div class='add'>+		return 0;</div><div class='add'>+	if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		if (xe_hw_engine_is_reserved(hwe))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (hwe-&gt;class ==</div><div class='add'>+		    user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY])</div><div class='add'>+			logical_mask |= BIT(hwe-&gt;logical_instance);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return logical_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+				      struct drm_xe_engine_class_instance *eci,</div><div class='add'>+				      u16 width, u16 num_placements)</div><div class='add'>+{</div><div class='add'>+	int len = width * num_placements;</div><div class='add'>+	int i, j, n;</div><div class='add'>+	u16 class;</div><div class='add'>+	u16 gt_id;</div><div class='add'>+	u32 return_mask = 0, prev_mask;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !xe_device_uc_enabled(xe) &amp;&amp;</div><div class='add'>+			 len &gt; 1))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; width; ++i) {</div><div class='add'>+		u32 current_mask = 0;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; num_placements; ++j) {</div><div class='add'>+			struct xe_hw_engine *hwe;</div><div class='add'>+</div><div class='add'>+			n = j * width + i;</div><div class='add'>+</div><div class='add'>+			hwe = find_hw_engine(xe, eci[n]);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !hwe))</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe)))</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			if (XE_IOCTL_DBG(xe, n &amp;&amp; eci[n].gt_id != gt_id) ||</div><div class='add'>+			    XE_IOCTL_DBG(xe, n &amp;&amp; eci[n].engine_class != class))</div><div class='add'>+				return 0;</div><div class='add'>+</div><div class='add'>+			class = eci[n].engine_class;</div><div class='add'>+			gt_id = eci[n].gt_id;</div><div class='add'>+</div><div class='add'>+			if (width == 1 || !i)</div><div class='add'>+				return_mask |= BIT(eci[n].engine_instance);</div><div class='add'>+			current_mask |= BIT(eci[n].engine_instance);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Parallel submissions must be logically contiguous */</div><div class='add'>+		if (i &amp;&amp; XE_IOCTL_DBG(xe, current_mask != prev_mask &lt;&lt; 1))</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		prev_mask = current_mask;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return return_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			       struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_exec_queue_create *args = data;</div><div class='add'>+	struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE];</div><div class='add'>+	struct drm_xe_engine_class_instance __user *user_eci =</div><div class='add'>+		u64_to_user_ptr(args-&gt;instances);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	struct xe_vm *vm, *migrate_vm;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	struct xe_exec_queue *q = NULL;</div><div class='add'>+	u32 logical_mask;</div><div class='add'>+	u32 id;</div><div class='add'>+	u32 len;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	len = args-&gt;width * args-&gt;num_placements;</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !len || len &gt; XE_HW_ENGINE_MAX_INSTANCE))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	err = __copy_from_user(eci, user_eci,</div><div class='add'>+			       sizeof(struct drm_xe_engine_class_instance) *</div><div class='add'>+			       len);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, eci[0].gt_id &gt;= xe-&gt;info.gt_count))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) {</div><div class='add'>+		for_each_gt(gt, xe, id) {</div><div class='add'>+			struct xe_exec_queue *new;</div><div class='add'>+</div><div class='add'>+			if (xe_gt_is_media_type(gt))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			eci[0].gt_id = gt-&gt;info.id;</div><div class='add'>+			logical_mask = bind_exec_queue_logical_mask(xe, gt, eci,</div><div class='add'>+								    args-&gt;width,</div><div class='add'>+								    args-&gt;num_placements);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !logical_mask))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			hwe = find_hw_engine(xe, eci[0]);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !hwe))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			/* The migration vm doesn't hold rpm ref */</div><div class='add'>+			xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+			migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)-&gt;migrate);</div><div class='add'>+			new = xe_exec_queue_create(xe, migrate_vm, logical_mask,</div><div class='add'>+						   args-&gt;width, hwe,</div><div class='add'>+						   EXEC_QUEUE_FLAG_PERSISTENT |</div><div class='add'>+						   EXEC_QUEUE_FLAG_VM |</div><div class='add'>+						   (id ?</div><div class='add'>+						    EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD :</div><div class='add'>+						    0));</div><div class='add'>+</div><div class='add'>+			xe_device_mem_access_put(xe); /* now held by engine */</div><div class='add'>+</div><div class='add'>+			xe_vm_put(migrate_vm);</div><div class='add'>+			if (IS_ERR(new)) {</div><div class='add'>+				err = PTR_ERR(new);</div><div class='add'>+				if (q)</div><div class='add'>+					goto put_exec_queue;</div><div class='add'>+				return err;</div><div class='add'>+			}</div><div class='add'>+			if (id == 0)</div><div class='add'>+				q = new;</div><div class='add'>+			else</div><div class='add'>+				list_add_tail(&amp;new-&gt;multi_gt_list,</div><div class='add'>+					      &amp;q-&gt;multi_gt_link);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		gt = xe_device_get_gt(xe, eci[0].gt_id);</div><div class='add'>+		logical_mask = calc_validate_logical_mask(xe, gt, eci,</div><div class='add'>+							  args-&gt;width,</div><div class='add'>+							  args-&gt;num_placements);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !logical_mask))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		hwe = find_hw_engine(xe, eci[0]);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !hwe))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		vm = xe_vm_lookup(xef, args-&gt;vm_id);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !vm))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		err = down_read_interruptible(&amp;vm-&gt;lock);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_vm_put(vm);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) {</div><div class='add'>+			up_read(&amp;vm-&gt;lock);</div><div class='add'>+			xe_vm_put(vm);</div><div class='add'>+			return -ENOENT;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		q = xe_exec_queue_create(xe, vm, logical_mask,</div><div class='add'>+					 args-&gt;width, hwe,</div><div class='add'>+					 xe_vm_in_lr_mode(vm) ? 0 :</div><div class='add'>+					 EXEC_QUEUE_FLAG_PERSISTENT);</div><div class='add'>+		up_read(&amp;vm-&gt;lock);</div><div class='add'>+		xe_vm_put(vm);</div><div class='add'>+		if (IS_ERR(q))</div><div class='add'>+			return PTR_ERR(q);</div><div class='add'>+</div><div class='add'>+		if (xe_vm_in_preempt_fence_mode(vm)) {</div><div class='add'>+			q-&gt;compute.context = dma_fence_context_alloc(1);</div><div class='add'>+			spin_lock_init(&amp;q-&gt;compute.lock);</div><div class='add'>+</div><div class='add'>+			err = xe_vm_add_compute_exec_queue(vm, q);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+				goto put_exec_queue;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (args-&gt;extensions) {</div><div class='add'>+		err = exec_queue_user_extensions(xe, q, args-&gt;extensions, 0, true);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, err))</div><div class='add'>+			goto kill_exec_queue;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q-&gt;persistent.xef = xef;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	err = xa_alloc(&amp;xef-&gt;exec_queue.xa, &amp;id, q, xa_limit_32b, GFP_KERNEL);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	if (err)</div><div class='add'>+		goto kill_exec_queue;</div><div class='add'>+</div><div class='add'>+	args-&gt;exec_queue_id = id;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+kill_exec_queue:</div><div class='add'>+	xe_exec_queue_kill(q);</div><div class='add'>+put_exec_queue:</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				     struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_exec_queue_get_property *args = data;</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q = xe_exec_queue_lookup(xef, args-&gt;exec_queue_id);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !q))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	switch (args-&gt;property) {</div><div class='add'>+	case DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN:</div><div class='add'>+		args-&gt;value = !!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_BANNED);</div><div class='add'>+		ret = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_is_lr() - Whether an exec_queue is long-running</div><div class='add'>+ * @q: The exec_queue</div><div class='add'>+ *</div><div class='add'>+ * Return: True if the exec_queue is long-running, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_exec_queue_is_lr(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return q-&gt;vm &amp;&amp; xe_vm_in_lr_mode(q-&gt;vm) &amp;&amp;</div><div class='add'>+		!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s32 xe_exec_queue_num_job_inflight(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return q-&gt;lrc-&gt;fence_ctx.next_seqno - xe_lrc_seqno(q-&gt;lrc) - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_ring_full() - Whether an exec_queue's ring is full</div><div class='add'>+ * @q: The exec_queue</div><div class='add'>+ *</div><div class='add'>+ * Return: True if the exec_queue's ring is full, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_exec_queue_ring_full(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_lrc *lrc = q-&gt;lrc;</div><div class='add'>+	s32 max_job = lrc-&gt;ring.size / MAX_JOB_SIZE_BYTES;</div><div class='add'>+</div><div class='add'>+	return xe_exec_queue_num_job_inflight(q) &gt;= max_job;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_is_idle() - Whether an exec_queue is idle.</div><div class='add'>+ * @q: The exec_queue</div><div class='add'>+ *</div><div class='add'>+ * FIXME: Need to determine what to use as the short-lived</div><div class='add'>+ * timeline lock for the exec_queues, so that the return value</div><div class='add'>+ * of this function becomes more than just an advisory</div><div class='add'>+ * snapshot in time. The timeline lock must protect the</div><div class='add'>+ * seqno from racing submissions on the same exec_queue.</div><div class='add'>+ * Typically vm-&gt;resv, but user-created timeline locks use the migrate vm</div><div class='add'>+ * and never grabs the migrate vm-&gt;resv so we have a race there.</div><div class='add'>+ *</div><div class='add'>+ * Return: True if the exec_queue is idle, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_exec_queue_is_idle(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	if (xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; q-&gt;width; ++i) {</div><div class='add'>+			if (xe_lrc_seqno(&amp;q-&gt;lrc[i]) !=</div><div class='add'>+			    q-&gt;lrc[i].fence_ctx.next_seqno - 1)</div><div class='add'>+				return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return xe_lrc_seqno(&amp;q-&gt;lrc[0]) ==</div><div class='add'>+		q-&gt;lrc[0].fence_ctx.next_seqno - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_kill(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *eq = q, *next;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(eq, next, &amp;eq-&gt;multi_gt_list,</div><div class='add'>+				 multi_gt_link) {</div><div class='add'>+		q-&gt;ops-&gt;kill(eq);</div><div class='add'>+		xe_vm_remove_compute_exec_queue(q-&gt;vm, eq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q-&gt;ops-&gt;kill(q);</div><div class='add'>+	xe_vm_remove_compute_exec_queue(q-&gt;vm, q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_exec_queue_destroy *args = data;</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;pad) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	q = xa_erase(&amp;xef-&gt;exec_queue.xa, args-&gt;exec_queue_id);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;exec_queue.lock);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !q))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERSISTENT))</div><div class='add'>+		xe_exec_queue_kill(q);</div><div class='add'>+	else</div><div class='add'>+		xe_device_add_persistent_exec_queues(xe, q);</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_close(q);</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_exec_queue_last_fence_lockdep_assert(struct xe_exec_queue *q,</div><div class='add'>+						    struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM)</div><div class='add'>+		lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	else</div><div class='add'>+		xe_vm_assert_held(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_last_fence_put() - Drop ref to last fence</div><div class='add'>+ * @q: The exec queue</div><div class='add'>+ * @vm: The VM the engine does a bind or exec for</div><div class='add'>+ */</div><div class='add'>+void xe_exec_queue_last_fence_put(struct xe_exec_queue *q, struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	xe_exec_queue_last_fence_lockdep_assert(q, vm);</div><div class='add'>+</div><div class='add'>+	if (q-&gt;last_fence) {</div><div class='add'>+		dma_fence_put(q-&gt;last_fence);</div><div class='add'>+		q-&gt;last_fence = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_last_fence_put_unlocked() - Drop ref to last fence unlocked</div><div class='add'>+ * @q: The exec queue</div><div class='add'>+ *</div><div class='add'>+ * Only safe to be called from xe_exec_queue_destroy().</div><div class='add'>+ */</div><div class='add'>+void xe_exec_queue_last_fence_put_unlocked(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	if (q-&gt;last_fence) {</div><div class='add'>+		dma_fence_put(q-&gt;last_fence);</div><div class='add'>+		q-&gt;last_fence = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_last_fence_get() - Get last fence</div><div class='add'>+ * @q: The exec queue</div><div class='add'>+ * @vm: The VM the engine does a bind or exec for</div><div class='add'>+ *</div><div class='add'>+ * Get last fence, does not take a ref</div><div class='add'>+ *</div><div class='add'>+ * Returns: last fence if not signaled, dma fence stub if signaled</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *xe_exec_queue_last_fence_get(struct xe_exec_queue *q,</div><div class='add'>+					       struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	xe_exec_queue_last_fence_lockdep_assert(q, vm);</div><div class='add'>+</div><div class='add'>+	if (q-&gt;last_fence &amp;&amp;</div><div class='add'>+	    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &amp;q-&gt;last_fence-&gt;flags))</div><div class='add'>+		xe_exec_queue_last_fence_put(q, vm);</div><div class='add'>+</div><div class='add'>+	return q-&gt;last_fence ? q-&gt;last_fence : dma_fence_get_stub();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_exec_queue_last_fence_set() - Set last fence</div><div class='add'>+ * @q: The exec queue</div><div class='add'>+ * @vm: The VM the engine does a bind or exec for</div><div class='add'>+ * @fence: The fence</div><div class='add'>+ *</div><div class='add'>+ * Set the last fence for the engine. Increases reference count for fence, when</div><div class='add'>+ * closing engine xe_exec_queue_last_fence_put should be called.</div><div class='add'>+ */</div><div class='add'>+void xe_exec_queue_last_fence_set(struct xe_exec_queue *q, struct xe_vm *vm,</div><div class='add'>+				  struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	xe_exec_queue_last_fence_lockdep_assert(q, vm);</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_last_fence_put(q, vm);</div><div class='add'>+	q-&gt;last_fence = dma_fence_get(fence);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h<br/>new file mode 100644<br/>index 000000000000..d959cc4a1a82<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_exec_queue.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue.h</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_EXEC_QUEUE_H_</div><div class='add'>+#define _XE_EXEC_QUEUE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+#include "xe_vm_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_file;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_file;</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm,</div><div class='add'>+					   u32 logical_mask, u16 width,</div><div class='add'>+					   struct xe_hw_engine *hw_engine, u32 flags);</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+						 struct xe_vm *vm,</div><div class='add'>+						 enum xe_engine_class class, u32 flags);</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_fini(struct xe_exec_queue *q);</div><div class='add'>+void xe_exec_queue_destroy(struct kref *ref);</div><div class='add'>+void xe_exec_queue_assign_name(struct xe_exec_queue *q, u32 instance);</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id);</div><div class='add'>+</div><div class='add'>+static inline struct xe_exec_queue *xe_exec_queue_get(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;q-&gt;refcount);</div><div class='add'>+	return q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_exec_queue_put(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;q-&gt;refcount, xe_exec_queue_destroy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_exec_queue_is_parallel(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return q-&gt;width &gt; 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_exec_queue_is_lr(struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+bool xe_exec_queue_ring_full(struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+bool xe_exec_queue_is_idle(struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_kill(struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			       struct drm_file *file);</div><div class='add'>+int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				struct drm_file *file);</div><div class='add'>+int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+				     struct drm_file *file);</div><div class='add'>+enum xe_exec_queue_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_exec_queue_last_fence_put(struct xe_exec_queue *e, struct xe_vm *vm);</div><div class='add'>+void xe_exec_queue_last_fence_put_unlocked(struct xe_exec_queue *e);</div><div class='add'>+struct dma_fence *xe_exec_queue_last_fence_get(struct xe_exec_queue *e,</div><div class='add'>+					       struct xe_vm *vm);</div><div class='add'>+void xe_exec_queue_last_fence_set(struct xe_exec_queue *e, struct xe_vm *vm,</div><div class='add'>+				  struct dma_fence *fence);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h<br/>new file mode 100644<br/>index 000000000000..8d4b7feb8c30<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_exec_queue_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_exec_queue_types.h</a></div><div class='hunk'>@@ -0,0 +1,224 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_EXEC_QUEUE_TYPES_H_</div><div class='add'>+#define _XE_EXEC_QUEUE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/gpu_scheduler.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gpu_scheduler_types.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_hw_fence_types.h"</div><div class='add'>+#include "xe_lrc_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_execlist_exec_queue;</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_guc_exec_queue;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+enum xe_exec_queue_priority {</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_UNSET = -2, /* For execlist usage only */</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_LOW = 0,</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_NORMAL,</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_HIGH,</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_KERNEL,</div><div class='add'>+</div><div class='add'>+	XE_EXEC_QUEUE_PRIORITY_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_exec_queue - Execution queue</div><div class='add'>+ *</div><div class='add'>+ * Contains all state necessary for submissions. Can either be a user object or</div><div class='add'>+ * a kernel object.</div><div class='add'>+ */</div><div class='add'>+struct xe_exec_queue {</div><div class='add'>+	/** @gt: graphics tile this exec queue can submit to */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	/**</div><div class='add'>+	 * @hwe: A hardware of the same class. May (physical engine) or may not</div><div class='add'>+	 * (virtual engine) be where jobs actual engine up running. Should never</div><div class='add'>+	 * really be used for submissions.</div><div class='add'>+	 */</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	/** @refcount: ref count of this exec queue */</div><div class='add'>+	struct kref refcount;</div><div class='add'>+	/** @vm: VM (address space) for this exec queue */</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	/** @class: class of this exec queue */</div><div class='add'>+	enum xe_engine_class class;</div><div class='add'>+	/**</div><div class='add'>+	 * @logical_mask: logical mask of where job submitted to exec queue can run</div><div class='add'>+	 */</div><div class='add'>+	u32 logical_mask;</div><div class='add'>+	/** @name: name of this exec queue */</div><div class='add'>+	char name[MAX_FENCE_NAME_LEN];</div><div class='add'>+	/** @width: width (number BB submitted per exec) of this exec queue */</div><div class='add'>+	u16 width;</div><div class='add'>+	/** @fence_irq: fence IRQ used to signal job completion */</div><div class='add'>+	struct xe_hw_fence_irq *fence_irq;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @last_fence: last fence on exec queue, protected by vm-&gt;lock in write</div><div class='add'>+	 * mode if bind exec queue, protected by dma resv lock if non-bind exec</div><div class='add'>+	 * queue</div><div class='add'>+	 */</div><div class='add'>+	struct dma_fence *last_fence;</div><div class='add'>+</div><div class='add'>+/* queue no longer allowed to submit */</div><div class='add'>+#define EXEC_QUEUE_FLAG_BANNED			BIT(0)</div><div class='add'>+/* queue used for kernel submission only */</div><div class='add'>+#define EXEC_QUEUE_FLAG_KERNEL			BIT(1)</div><div class='add'>+/* kernel engine only destroyed at driver unload */</div><div class='add'>+#define EXEC_QUEUE_FLAG_PERMANENT		BIT(2)</div><div class='add'>+/* queue keeps running pending jobs after destroy ioctl */</div><div class='add'>+#define EXEC_QUEUE_FLAG_PERSISTENT		BIT(3)</div><div class='add'>+/* for VM jobs. Caller needs to hold rpm ref when creating queue with this flag */</div><div class='add'>+#define EXEC_QUEUE_FLAG_VM			BIT(4)</div><div class='add'>+/* child of VM queue for multi-tile VM jobs */</div><div class='add'>+#define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD	BIT(5)</div><div class='add'>+/* kernel exec_queue only, set priority to highest level */</div><div class='add'>+#define EXEC_QUEUE_FLAG_HIGH_PRIORITY		BIT(6)</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @flags: flags for this exec queue, should statically setup aside from ban</div><div class='add'>+	 * bit</div><div class='add'>+	 */</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/** @multi_gt_list: list head for VM bind engines if multi-GT */</div><div class='add'>+		struct list_head multi_gt_list;</div><div class='add'>+		/** @multi_gt_link: link for VM bind engines if multi-GT */</div><div class='add'>+		struct list_head multi_gt_link;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/** @execlist: execlist backend specific state for exec queue */</div><div class='add'>+		struct xe_execlist_exec_queue *execlist;</div><div class='add'>+		/** @guc: GuC backend specific state for exec queue */</div><div class='add'>+		struct xe_guc_exec_queue *guc;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @persistent: persistent exec queue state</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @xef: file which this exec queue belongs to */</div><div class='add'>+		struct xe_file *xef;</div><div class='add'>+		/** @link: link in list of persistent exec queues */</div><div class='add'>+		struct list_head link;</div><div class='add'>+	} persistent;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/**</div><div class='add'>+		 * @parallel: parallel submission state</div><div class='add'>+		 */</div><div class='add'>+		struct {</div><div class='add'>+			/** @composite_fence_ctx: context composite fence */</div><div class='add'>+			u64 composite_fence_ctx;</div><div class='add'>+			/** @composite_fence_seqno: seqno for composite fence */</div><div class='add'>+			u32 composite_fence_seqno;</div><div class='add'>+		} parallel;</div><div class='add'>+		/**</div><div class='add'>+		 * @bind: bind submission state</div><div class='add'>+		 */</div><div class='add'>+		struct {</div><div class='add'>+			/** @fence_ctx: context bind fence */</div><div class='add'>+			u64 fence_ctx;</div><div class='add'>+			/** @fence_seqno: seqno for bind fence */</div><div class='add'>+			u32 fence_seqno;</div><div class='add'>+		} bind;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/** @sched_props: scheduling properties */</div><div class='add'>+	struct {</div><div class='add'>+		/** @timeslice_us: timeslice period in micro-seconds */</div><div class='add'>+		u32 timeslice_us;</div><div class='add'>+		/** @preempt_timeout_us: preemption timeout in micro-seconds */</div><div class='add'>+		u32 preempt_timeout_us;</div><div class='add'>+		/** @priority: priority of this exec queue */</div><div class='add'>+		enum xe_exec_queue_priority priority;</div><div class='add'>+	} sched_props;</div><div class='add'>+</div><div class='add'>+	/** @compute: compute exec queue state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @pfence: preemption fence */</div><div class='add'>+		struct dma_fence *pfence;</div><div class='add'>+		/** @context: preemption fence context */</div><div class='add'>+		u64 context;</div><div class='add'>+		/** @seqno: preemption fence seqno */</div><div class='add'>+		u32 seqno;</div><div class='add'>+		/** @link: link into VM's list of exec queues */</div><div class='add'>+		struct list_head link;</div><div class='add'>+		/** @lock: preemption fences lock */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+	} compute;</div><div class='add'>+</div><div class='add'>+	/** @usm: unified shared memory state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @acc_trigger: access counter trigger */</div><div class='add'>+		u32 acc_trigger;</div><div class='add'>+		/** @acc_notify: access counter notify */</div><div class='add'>+		u32 acc_notify;</div><div class='add'>+		/** @acc_granularity: access counter granularity */</div><div class='add'>+		u32 acc_granularity;</div><div class='add'>+	} usm;</div><div class='add'>+</div><div class='add'>+	/** @ops: submission backend exec queue operations */</div><div class='add'>+	const struct xe_exec_queue_ops *ops;</div><div class='add'>+</div><div class='add'>+	/** @ring_ops: ring operations for this exec queue */</div><div class='add'>+	const struct xe_ring_ops *ring_ops;</div><div class='add'>+	/** @entity: DRM sched entity for this exec queue (1 to 1 relationship) */</div><div class='add'>+	struct drm_sched_entity *entity;</div><div class='add'>+	/** @lrc: logical ring context for this exec queue */</div><div class='add'>+	struct xe_lrc lrc[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_exec_queue_ops - Submission backend exec queue operations</div><div class='add'>+ */</div><div class='add'>+struct xe_exec_queue_ops {</div><div class='add'>+	/** @init: Initialize exec queue for submission backend */</div><div class='add'>+	int (*init)(struct xe_exec_queue *q);</div><div class='add'>+	/** @kill: Kill inflight submissions for backend */</div><div class='add'>+	void (*kill)(struct xe_exec_queue *q);</div><div class='add'>+	/** @fini: Fini exec queue for submission backend */</div><div class='add'>+	void (*fini)(struct xe_exec_queue *q);</div><div class='add'>+	/** @set_priority: Set priority for exec queue */</div><div class='add'>+	int (*set_priority)(struct xe_exec_queue *q,</div><div class='add'>+			    enum xe_exec_queue_priority priority);</div><div class='add'>+	/** @set_timeslice: Set timeslice for exec queue */</div><div class='add'>+	int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us);</div><div class='add'>+	/** @set_preempt_timeout: Set preemption timeout for exec queue */</div><div class='add'>+	int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us);</div><div class='add'>+	/** @set_job_timeout: Set job timeout for exec queue */</div><div class='add'>+	int (*set_job_timeout)(struct xe_exec_queue *q, u32 job_timeout_ms);</div><div class='add'>+	/**</div><div class='add'>+	 * @suspend: Suspend exec queue from executing, allowed to be called</div><div class='add'>+	 * multiple times in a row before resume with the caveat that</div><div class='add'>+	 * suspend_wait returns before calling suspend again.</div><div class='add'>+	 */</div><div class='add'>+	int (*suspend)(struct xe_exec_queue *q);</div><div class='add'>+	/**</div><div class='add'>+	 * @suspend_wait: Wait for an exec queue to suspend executing, should be</div><div class='add'>+	 * call after suspend.</div><div class='add'>+	 */</div><div class='add'>+	void (*suspend_wait)(struct xe_exec_queue *q);</div><div class='add'>+	/**</div><div class='add'>+	 * @resume: Resume exec queue execution, exec queue must be in a suspended</div><div class='add'>+	 * state and dma fence returned from most recent suspend call must be</div><div class='add'>+	 * signalled when this function is called.</div><div class='add'>+	 */</div><div class='add'>+	void (*resume)(struct xe_exec_queue *q);</div><div class='add'>+	/** @reset_status: check exec queue reset status */</div><div class='add'>+	bool (*reset_status)(struct xe_exec_queue *q);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c<br/>new file mode 100644<br/>index 000000000000..96b5224eb478<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_execlist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist.c</a></div><div class='hunk'>@@ -0,0 +1,474 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_execlist.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_lrc_layout.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+#include "xe_ring_ops_types.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+</div><div class='add'>+#define XE_EXECLIST_HANG_LIMIT 1</div><div class='add'>+</div><div class='add'>+#define SW_CTX_ID_SHIFT 37</div><div class='add'>+#define SW_CTX_ID_WIDTH 11</div><div class='add'>+#define XEHP_SW_CTX_ID_SHIFT  39</div><div class='add'>+#define XEHP_SW_CTX_ID_WIDTH  16</div><div class='add'>+</div><div class='add'>+#define SW_CTX_ID \</div><div class='add'>+	GENMASK_ULL(SW_CTX_ID_WIDTH + SW_CTX_ID_SHIFT - 1, \</div><div class='add'>+		    SW_CTX_ID_SHIFT)</div><div class='add'>+</div><div class='add'>+#define XEHP_SW_CTX_ID \</div><div class='add'>+	GENMASK_ULL(XEHP_SW_CTX_ID_WIDTH + XEHP_SW_CTX_ID_SHIFT - 1, \</div><div class='add'>+		    XEHP_SW_CTX_ID_SHIFT)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,</div><div class='add'>+			u32 ctx_id)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u64 lrc_desc;</div><div class='add'>+</div><div class='add'>+	lrc_desc = xe_lrc_descriptor(lrc);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250) {</div><div class='add'>+		xe_gt_assert(hwe-&gt;gt, FIELD_FIT(XEHP_SW_CTX_ID, ctx_id));</div><div class='add'>+		lrc_desc |= FIELD_PREP(XEHP_SW_CTX_ID, ctx_id);</div><div class='add'>+	} else {</div><div class='add'>+		xe_gt_assert(hwe-&gt;gt, FIELD_FIT(SW_CTX_ID, ctx_id));</div><div class='add'>+		lrc_desc |= FIELD_PREP(SW_CTX_ID, ctx_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hwe-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+		xe_mmio_write32(hwe-&gt;gt, RCU_MODE,</div><div class='add'>+				_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc-&gt;ring.tail);</div><div class='add'>+	lrc-&gt;ring.old_tail = lrc-&gt;ring.tail;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Make sure the context image is complete before we submit it to HW.</div><div class='add'>+	 *</div><div class='add'>+	 * Ostensibly, writes (including the WCB) should be flushed prior to</div><div class='add'>+	 * an uncached write such as our mmio register access, the empirical</div><div class='add'>+	 * evidence (esp. on Braswell) suggests that the WC write into memory</div><div class='add'>+	 * may not be visible to the HW prior to the completion of the UC</div><div class='add'>+	 * register write and that we may begin execution from the context</div><div class='add'>+	 * before its image is complete leading to invalid PD chasing.</div><div class='add'>+	 */</div><div class='add'>+	wmb();</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, RING_HWS_PGA(hwe-&gt;mmio_base),</div><div class='add'>+			xe_bo_ggtt_addr(hwe-&gt;hwsp));</div><div class='add'>+	xe_mmio_read32(gt, RING_HWS_PGA(hwe-&gt;mmio_base));</div><div class='add'>+	xe_mmio_write32(gt, RING_MODE(hwe-&gt;mmio_base),</div><div class='add'>+			_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe-&gt;mmio_base),</div><div class='add'>+			lower_32_bits(lrc_desc));</div><div class='add'>+	xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe-&gt;mmio_base),</div><div class='add'>+			upper_32_bits(lrc_desc));</div><div class='add'>+	xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe-&gt;mmio_base),</div><div class='add'>+			EL_CTRL_LOAD);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_execlist_port_start(struct xe_execlist_port *port,</div><div class='add'>+				     struct xe_execlist_exec_queue *exl)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(port-&gt;hwe-&gt;gt);</div><div class='add'>+	int max_ctx = FIELD_MAX(SW_CTX_ID);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250)</div><div class='add'>+		max_ctx = FIELD_MAX(XEHP_SW_CTX_ID);</div><div class='add'>+</div><div class='add'>+	xe_execlist_port_assert_held(port);</div><div class='add'>+</div><div class='add'>+	if (port-&gt;running_exl != exl || !exl-&gt;has_run) {</div><div class='add'>+		port-&gt;last_ctx_id++;</div><div class='add'>+</div><div class='add'>+		/* 0 is reserved for the kernel context */</div><div class='add'>+		if (port-&gt;last_ctx_id &gt; max_ctx)</div><div class='add'>+			port-&gt;last_ctx_id = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	__start_lrc(port-&gt;hwe, exl-&gt;q-&gt;lrc, port-&gt;last_ctx_id);</div><div class='add'>+	port-&gt;running_exl = exl;</div><div class='add'>+	exl-&gt;has_run = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_execlist_port_idle(struct xe_execlist_port *port)</div><div class='add'>+{</div><div class='add'>+	u32 noop[2] = { MI_NOOP, MI_NOOP };</div><div class='add'>+</div><div class='add'>+	xe_execlist_port_assert_held(port);</div><div class='add'>+</div><div class='add'>+	if (!port-&gt;running_exl)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ring(&amp;port-&gt;hwe-&gt;kernel_lrc, noop, sizeof(noop));</div><div class='add'>+	__start_lrc(port-&gt;hwe, &amp;port-&gt;hwe-&gt;kernel_lrc, 0);</div><div class='add'>+	port-&gt;running_exl = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_execlist_is_idle(struct xe_execlist_exec_queue *exl)</div><div class='add'>+{</div><div class='add'>+	struct xe_lrc *lrc = exl-&gt;q-&gt;lrc;</div><div class='add'>+</div><div class='add'>+	return lrc-&gt;ring.tail == lrc-&gt;ring.old_tail;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port)</div><div class='add'>+{</div><div class='add'>+	struct xe_execlist_exec_queue *exl = NULL;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_execlist_port_assert_held(port);</div><div class='add'>+</div><div class='add'>+	for (i = ARRAY_SIZE(port-&gt;active) - 1; i &gt;= 0; i--) {</div><div class='add'>+		while (!list_empty(&amp;port-&gt;active[i])) {</div><div class='add'>+			exl = list_first_entry(&amp;port-&gt;active[i],</div><div class='add'>+					       struct xe_execlist_exec_queue,</div><div class='add'>+					       active_link);</div><div class='add'>+			list_del(&amp;exl-&gt;active_link);</div><div class='add'>+</div><div class='add'>+			if (xe_execlist_is_idle(exl)) {</div><div class='add'>+				exl-&gt;active_priority = XE_EXEC_QUEUE_PRIORITY_UNSET;</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			list_add_tail(&amp;exl-&gt;active_link, &amp;port-&gt;active[i]);</div><div class='add'>+			__xe_execlist_port_start(port, exl);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	__xe_execlist_port_idle(port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 read_execlist_status(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	u32 hi, lo;</div><div class='add'>+</div><div class='add'>+	lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe-&gt;mmio_base));</div><div class='add'>+	hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe-&gt;mmio_base));</div><div class='add'>+</div><div class='add'>+	return lo | (u64)hi &lt;&lt; 32;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_execlist_port_irq_handler_locked(struct xe_execlist_port *port)</div><div class='add'>+{</div><div class='add'>+	u64 status;</div><div class='add'>+</div><div class='add'>+	xe_execlist_port_assert_held(port);</div><div class='add'>+</div><div class='add'>+	status = read_execlist_status(port-&gt;hwe);</div><div class='add'>+	if (status &amp; BIT(7))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	__xe_execlist_port_start_next_active(port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_execlist_port_irq_handler(struct xe_hw_engine *hwe,</div><div class='add'>+					 u16 intr_vec)</div><div class='add'>+{</div><div class='add'>+	struct xe_execlist_port *port = hwe-&gt;exl_port;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;port-&gt;lock);</div><div class='add'>+	xe_execlist_port_irq_handler_locked(port);</div><div class='add'>+	spin_unlock(&amp;port-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_execlist_port_wake_locked(struct xe_execlist_port *port,</div><div class='add'>+					 enum xe_exec_queue_priority priority)</div><div class='add'>+{</div><div class='add'>+	xe_execlist_port_assert_held(port);</div><div class='add'>+</div><div class='add'>+	if (port-&gt;running_exl &amp;&amp; port-&gt;running_exl-&gt;active_priority &gt;= priority)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	__xe_execlist_port_start_next_active(port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_execlist_make_active(struct xe_execlist_exec_queue *exl)</div><div class='add'>+{</div><div class='add'>+	struct xe_execlist_port *port = exl-&gt;port;</div><div class='add'>+	enum xe_exec_queue_priority priority = exl-&gt;active_priority;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(priority == XE_EXEC_QUEUE_PRIORITY_UNSET);</div><div class='add'>+	XE_WARN_ON(priority &lt; 0);</div><div class='add'>+	XE_WARN_ON(priority &gt;= ARRAY_SIZE(exl-&gt;port-&gt;active));</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;port-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (exl-&gt;active_priority != priority &amp;&amp;</div><div class='add'>+	    exl-&gt;active_priority != XE_EXEC_QUEUE_PRIORITY_UNSET) {</div><div class='add'>+		/* Priority changed, move it to the right list */</div><div class='add'>+		list_del(&amp;exl-&gt;active_link);</div><div class='add'>+		exl-&gt;active_priority = XE_EXEC_QUEUE_PRIORITY_UNSET;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (exl-&gt;active_priority == XE_EXEC_QUEUE_PRIORITY_UNSET) {</div><div class='add'>+		exl-&gt;active_priority = priority;</div><div class='add'>+		list_add_tail(&amp;exl-&gt;active_link, &amp;port-&gt;active[priority]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_execlist_port_wake_locked(exl-&gt;port, priority);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irq(&amp;port-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_execlist_port_irq_fail_timer(struct timer_list *timer)</div><div class='add'>+{</div><div class='add'>+	struct xe_execlist_port *port =</div><div class='add'>+		container_of(timer, struct xe_execlist_port, irq_fail);</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;port-&gt;lock);</div><div class='add'>+	xe_execlist_port_irq_handler_locked(port);</div><div class='add'>+	spin_unlock_irq(&amp;port-&gt;lock);</div><div class='add'>+</div><div class='add'>+	port-&gt;irq_fail.expires = jiffies + msecs_to_jiffies(1000);</div><div class='add'>+	add_timer(&amp;port-&gt;irq_fail);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_execlist_port *xe_execlist_port_create(struct xe_device *xe,</div><div class='add'>+						 struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *drm = &amp;xe-&gt;drm;</div><div class='add'>+	struct xe_execlist_port *port;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	port = drmm_kzalloc(drm, sizeof(*port), GFP_KERNEL);</div><div class='add'>+	if (!port)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	port-&gt;hwe = hwe;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;port-&gt;lock);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(port-&gt;active); i++)</div><div class='add'>+		INIT_LIST_HEAD(&amp;port-&gt;active[i]);</div><div class='add'>+</div><div class='add'>+	port-&gt;last_ctx_id = 1;</div><div class='add'>+	port-&gt;running_exl = NULL;</div><div class='add'>+</div><div class='add'>+	hwe-&gt;irq_handler = xe_execlist_port_irq_handler;</div><div class='add'>+</div><div class='add'>+	/* TODO: Fix the interrupt code so it doesn't race like mad */</div><div class='add'>+	timer_setup(&amp;port-&gt;irq_fail, xe_execlist_port_irq_fail_timer, 0);</div><div class='add'>+	port-&gt;irq_fail.expires = jiffies + msecs_to_jiffies(1000);</div><div class='add'>+	add_timer(&amp;port-&gt;irq_fail);</div><div class='add'>+</div><div class='add'>+	return port;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_execlist_port_destroy(struct xe_execlist_port *port)</div><div class='add'>+{</div><div class='add'>+	del_timer(&amp;port-&gt;irq_fail);</div><div class='add'>+</div><div class='add'>+	/* Prevent an interrupt while we're destroying */</div><div class='add'>+	spin_lock_irq(&amp;gt_to_xe(port-&gt;hwe-&gt;gt)-&gt;irq.lock);</div><div class='add'>+	port-&gt;hwe-&gt;irq_handler = NULL;</div><div class='add'>+	spin_unlock_irq(&amp;gt_to_xe(port-&gt;hwe-&gt;gt)-&gt;irq.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+execlist_run_job(struct drm_sched_job *drm_job)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job = to_xe_sched_job(drm_job);</div><div class='add'>+	struct xe_exec_queue *q = job-&gt;q;</div><div class='add'>+	struct xe_execlist_exec_queue *exl = job-&gt;q-&gt;execlist;</div><div class='add'>+</div><div class='add'>+	q-&gt;ring_ops-&gt;emit_job(job);</div><div class='add'>+	xe_execlist_make_active(exl);</div><div class='add'>+</div><div class='add'>+	return dma_fence_get(job-&gt;fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_job_free(struct drm_sched_job *drm_job)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job = to_xe_sched_job(drm_job);</div><div class='add'>+</div><div class='add'>+	xe_sched_job_put(job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_sched_backend_ops drm_sched_ops = {</div><div class='add'>+	.run_job = execlist_run_job,</div><div class='add'>+	.free_job = execlist_job_free,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_init(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct drm_gpu_scheduler *sched;</div><div class='add'>+	struct xe_execlist_exec_queue *exl;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(q-&gt;gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !xe_device_uc_enabled(xe));</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Enabling execlist submission (GuC submission disabled)\n");</div><div class='add'>+</div><div class='add'>+	exl = kzalloc(sizeof(*exl), GFP_KERNEL);</div><div class='add'>+	if (!exl)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	exl-&gt;q = q;</div><div class='add'>+</div><div class='add'>+	err = drm_sched_init(&amp;exl-&gt;sched, &amp;drm_sched_ops, NULL, 1,</div><div class='add'>+			     q-&gt;lrc[0].ring.size / MAX_JOB_SIZE_BYTES,</div><div class='add'>+			     XE_SCHED_HANG_LIMIT, XE_SCHED_JOB_TIMEOUT,</div><div class='add'>+			     NULL, NULL, q-&gt;hwe-&gt;name,</div><div class='add'>+			     gt_to_xe(q-&gt;gt)-&gt;drm.dev);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_free;</div><div class='add'>+</div><div class='add'>+	sched = &amp;exl-&gt;sched;</div><div class='add'>+	err = drm_sched_entity_init(&amp;exl-&gt;entity, 0, &amp;sched, 1, NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_sched;</div><div class='add'>+</div><div class='add'>+	exl-&gt;port = q-&gt;hwe-&gt;exl_port;</div><div class='add'>+	exl-&gt;has_run = false;</div><div class='add'>+	exl-&gt;active_priority = XE_EXEC_QUEUE_PRIORITY_UNSET;</div><div class='add'>+	q-&gt;execlist = exl;</div><div class='add'>+	q-&gt;entity = &amp;exl-&gt;entity;</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_assign_name(q, ffs(q-&gt;logical_mask) - 1);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_sched:</div><div class='add'>+	drm_sched_fini(&amp;exl-&gt;sched);</div><div class='add'>+err_free:</div><div class='add'>+	kfree(exl);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_exec_queue_fini_async(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_execlist_exec_queue *ee =</div><div class='add'>+		container_of(w, struct xe_execlist_exec_queue, fini_async);</div><div class='add'>+	struct xe_exec_queue *q = ee-&gt;q;</div><div class='add'>+	struct xe_execlist_exec_queue *exl = q-&gt;execlist;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(q-&gt;gt);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !xe_device_uc_enabled(xe));</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;exl-&gt;port-&gt;lock, flags);</div><div class='add'>+	if (WARN_ON(exl-&gt;active_priority != XE_EXEC_QUEUE_PRIORITY_UNSET))</div><div class='add'>+		list_del(&amp;exl-&gt;active_link);</div><div class='add'>+	spin_unlock_irqrestore(&amp;exl-&gt;port-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERSISTENT)</div><div class='add'>+		xe_device_remove_persistent_exec_queues(xe, q);</div><div class='add'>+	drm_sched_entity_fini(&amp;exl-&gt;entity);</div><div class='add'>+	drm_sched_fini(&amp;exl-&gt;sched);</div><div class='add'>+	kfree(exl);</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_fini(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_exec_queue_kill(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_exec_queue_fini(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	INIT_WORK(&amp;q-&gt;execlist-&gt;fini_async, execlist_exec_queue_fini_async);</div><div class='add'>+	queue_work(system_unbound_wq, &amp;q-&gt;execlist-&gt;fini_async);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_set_priority(struct xe_exec_queue *q,</div><div class='add'>+					    enum xe_exec_queue_priority priority)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,</div><div class='add'>+						   u32 preempt_timeout_us)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_set_job_timeout(struct xe_exec_queue *q,</div><div class='add'>+					       u32 job_timeout_ms)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int execlist_exec_queue_suspend(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_exec_queue_suspend_wait(struct xe_exec_queue *q)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void execlist_exec_queue_resume(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool execlist_exec_queue_reset_status(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	/* NIY */</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_exec_queue_ops execlist_exec_queue_ops = {</div><div class='add'>+	.init = execlist_exec_queue_init,</div><div class='add'>+	.kill = execlist_exec_queue_kill,</div><div class='add'>+	.fini = execlist_exec_queue_fini,</div><div class='add'>+	.set_priority = execlist_exec_queue_set_priority,</div><div class='add'>+	.set_timeslice = execlist_exec_queue_set_timeslice,</div><div class='add'>+	.set_preempt_timeout = execlist_exec_queue_set_preempt_timeout,</div><div class='add'>+	.set_job_timeout = execlist_exec_queue_set_job_timeout,</div><div class='add'>+	.suspend = execlist_exec_queue_suspend,</div><div class='add'>+	.suspend_wait = execlist_exec_queue_suspend_wait,</div><div class='add'>+	.resume = execlist_exec_queue_resume,</div><div class='add'>+	.reset_status = execlist_exec_queue_reset_status,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_execlist_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/* GuC submission enabled, nothing to do */</div><div class='add'>+	if (xe_device_uc_enabled(gt_to_xe(gt)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	gt-&gt;exec_queue_ops = &amp;execlist_exec_queue_ops;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_execlist.h b/drivers/gpu/drm/xe/xe_execlist.h<br/>new file mode 100644<br/>index 000000000000..26f600ac8552<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_execlist.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist.h</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_EXECLIST_H_</div><div class='add'>+#define _XE_EXECLIST_H_</div><div class='add'>+</div><div class='add'>+#include "xe_execlist_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+#define xe_execlist_port_assert_held(port) lockdep_assert_held(&amp;(port)-&gt;lock)</div><div class='add'>+</div><div class='add'>+int xe_execlist_init(struct xe_gt *gt);</div><div class='add'>+struct xe_execlist_port *xe_execlist_port_create(struct xe_device *xe,</div><div class='add'>+						 struct xe_hw_engine *hwe);</div><div class='add'>+void xe_execlist_port_destroy(struct xe_execlist_port *port);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_execlist_types.h b/drivers/gpu/drm/xe/xe_execlist_types.h<br/>new file mode 100644<br/>index 000000000000..f94bbf4c53e4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_execlist_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_execlist_types.h</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_EXECLIST_TYPES_H_</div><div class='add'>+#define _XE_EXECLIST_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_execlist_exec_queue;</div><div class='add'>+</div><div class='add'>+struct xe_execlist_port {</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+</div><div class='add'>+	struct list_head active[XE_EXEC_QUEUE_PRIORITY_COUNT];</div><div class='add'>+</div><div class='add'>+	u32 last_ctx_id;</div><div class='add'>+</div><div class='add'>+	struct xe_execlist_exec_queue *running_exl;</div><div class='add'>+</div><div class='add'>+	struct timer_list irq_fail;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_execlist_exec_queue {</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	struct drm_gpu_scheduler sched;</div><div class='add'>+</div><div class='add'>+	struct drm_sched_entity entity;</div><div class='add'>+</div><div class='add'>+	struct xe_execlist_port *port;</div><div class='add'>+</div><div class='add'>+	bool has_run;</div><div class='add'>+</div><div class='add'>+	struct work_struct fini_async;</div><div class='add'>+</div><div class='add'>+	enum xe_exec_queue_priority active_priority;</div><div class='add'>+	struct list_head active_link;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c<br/>new file mode 100644<br/>index 000000000000..9bbe8a5040da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_force_wake.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake.c</a></div><div class='hunk'>@@ -0,0 +1,199 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_util.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+#define XE_FORCE_WAKE_ACK_TIMEOUT_MS	50</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+fw_to_gt(struct xe_force_wake *fw)</div><div class='add'>+{</div><div class='add'>+	return fw-&gt;gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+fw_to_xe(struct xe_force_wake *fw)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(fw_to_gt(fw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void domain_init(struct xe_force_wake_domain *domain,</div><div class='add'>+			enum xe_force_wake_domain_id id,</div><div class='add'>+			struct xe_reg reg, struct xe_reg ack, u32 val, u32 mask)</div><div class='add'>+{</div><div class='add'>+	domain-&gt;id = id;</div><div class='add'>+	domain-&gt;reg_ctl = reg;</div><div class='add'>+	domain-&gt;reg_ack = ack;</div><div class='add'>+	domain-&gt;val = val;</div><div class='add'>+	domain-&gt;mask = mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	fw-&gt;gt = gt;</div><div class='add'>+	spin_lock_init(&amp;fw-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Assuming gen11+ so assert this assumption is correct */</div><div class='add'>+	xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) &gt;= 11);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.graphics_verx100 &gt;= 1270) {</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_GT],</div><div class='add'>+			    XE_FW_DOMAIN_ID_GT,</div><div class='add'>+			    FORCEWAKE_GT,</div><div class='add'>+			    FORCEWAKE_ACK_GT_MTL,</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+	} else {</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_GT],</div><div class='add'>+			    XE_FW_DOMAIN_ID_GT,</div><div class='add'>+			    FORCEWAKE_GT,</div><div class='add'>+			    FORCEWAKE_ACK_GT,</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	/* Assuming gen11+ so assert this assumption is correct */</div><div class='add'>+	xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) &gt;= 11);</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_is_media_type(gt))</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_RENDER],</div><div class='add'>+			    XE_FW_DOMAIN_ID_RENDER,</div><div class='add'>+			    FORCEWAKE_RENDER,</div><div class='add'>+			    FORCEWAKE_ACK_RENDER,</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+</div><div class='add'>+	for (i = XE_HW_ENGINE_VCS0, j = 0; i &lt;= XE_HW_ENGINE_VCS7; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],</div><div class='add'>+			    XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,</div><div class='add'>+			    FORCEWAKE_MEDIA_VDBOX(j),</div><div class='add'>+			    FORCEWAKE_ACK_MEDIA_VDBOX(j),</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = XE_HW_ENGINE_VECS0, j = 0; i &lt;= XE_HW_ENGINE_VECS3; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],</div><div class='add'>+			    XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,</div><div class='add'>+			    FORCEWAKE_MEDIA_VEBOX(j),</div><div class='add'>+			    FORCEWAKE_ACK_MEDIA_VEBOX(j),</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;info.engine_mask &amp; BIT(XE_HW_ENGINE_GSCCS0))</div><div class='add'>+		domain_init(&amp;fw-&gt;domains[XE_FW_DOMAIN_ID_GSC],</div><div class='add'>+			    XE_FW_DOMAIN_ID_GSC,</div><div class='add'>+			    FORCEWAKE_GSC,</div><div class='add'>+			    FORCEWAKE_ACK_GSC,</div><div class='add'>+			    BIT(0), BIT(16));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void domain_wake(struct xe_gt *gt, struct xe_force_wake_domain *domain)</div><div class='add'>+{</div><div class='add'>+	xe_mmio_write32(gt, domain-&gt;reg_ctl, domain-&gt;mask | domain-&gt;val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int domain_wake_wait(struct xe_gt *gt,</div><div class='add'>+			    struct xe_force_wake_domain *domain)</div><div class='add'>+{</div><div class='add'>+	return xe_mmio_wait32(gt, domain-&gt;reg_ack, domain-&gt;val, domain-&gt;val,</div><div class='add'>+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,</div><div class='add'>+			      NULL, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)</div><div class='add'>+{</div><div class='add'>+	xe_mmio_write32(gt, domain-&gt;reg_ctl, domain-&gt;mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int domain_sleep_wait(struct xe_gt *gt,</div><div class='add'>+			     struct xe_force_wake_domain *domain)</div><div class='add'>+{</div><div class='add'>+	return xe_mmio_wait32(gt, domain-&gt;reg_ack, domain-&gt;val, 0,</div><div class='add'>+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,</div><div class='add'>+			      NULL, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \</div><div class='add'>+	for (tmp__ = (mask__); tmp__; tmp__ &amp;= ~BIT(ffs(tmp__) - 1)) \</div><div class='add'>+		for_each_if((domain__ = ((fw__)-&gt;domains + \</div><div class='add'>+					 (ffs(tmp__) - 1))) &amp;&amp; \</div><div class='add'>+					 domain__-&gt;reg_ctl.addr)</div><div class='add'>+</div><div class='add'>+int xe_force_wake_get(struct xe_force_wake *fw,</div><div class='add'>+		      enum xe_force_wake_domains domains)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = fw_to_xe(fw);</div><div class='add'>+	struct xe_gt *gt = fw_to_gt(fw);</div><div class='add'>+	struct xe_force_wake_domain *domain;</div><div class='add'>+	enum xe_force_wake_domains tmp, woken = 0;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int ret, ret2 = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;fw-&gt;lock, flags);</div><div class='add'>+	for_each_fw_domain_masked(domain, domains, fw, tmp) {</div><div class='add'>+		if (!domain-&gt;ref++) {</div><div class='add'>+			woken |= BIT(domain-&gt;id);</div><div class='add'>+			domain_wake(gt, domain);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	for_each_fw_domain_masked(domain, woken, fw, tmp) {</div><div class='add'>+		ret = domain_wake_wait(gt, domain);</div><div class='add'>+		ret2 |= ret;</div><div class='add'>+		if (ret)</div><div class='add'>+			drm_notice(&amp;xe-&gt;drm, "Force wake domain (%d) failed to ack wake, ret=%d\n",</div><div class='add'>+				   domain-&gt;id, ret);</div><div class='add'>+	}</div><div class='add'>+	fw-&gt;awake_domains |= woken;</div><div class='add'>+	spin_unlock_irqrestore(&amp;fw-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	return ret2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_force_wake_put(struct xe_force_wake *fw,</div><div class='add'>+		      enum xe_force_wake_domains domains)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = fw_to_xe(fw);</div><div class='add'>+	struct xe_gt *gt = fw_to_gt(fw);</div><div class='add'>+	struct xe_force_wake_domain *domain;</div><div class='add'>+	enum xe_force_wake_domains tmp, sleep = 0;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int ret, ret2 = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;fw-&gt;lock, flags);</div><div class='add'>+	for_each_fw_domain_masked(domain, domains, fw, tmp) {</div><div class='add'>+		if (!--domain-&gt;ref) {</div><div class='add'>+			sleep |= BIT(domain-&gt;id);</div><div class='add'>+			domain_sleep(gt, domain);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	for_each_fw_domain_masked(domain, sleep, fw, tmp) {</div><div class='add'>+		ret = domain_sleep_wait(gt, domain);</div><div class='add'>+		ret2 |= ret;</div><div class='add'>+		if (ret)</div><div class='add'>+			drm_notice(&amp;xe-&gt;drm, "Force wake domain (%d) failed to ack sleep, ret=%d\n",</div><div class='add'>+				   domain-&gt;id, ret);</div><div class='add'>+	}</div><div class='add'>+	fw-&gt;awake_domains &amp;= ~sleep;</div><div class='add'>+	spin_unlock_irqrestore(&amp;fw-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	return ret2;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_force_wake.h b/drivers/gpu/drm/xe/xe_force_wake.h<br/>new file mode 100644<br/>index 000000000000..83cb157da7cc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_force_wake.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake.h</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_FORCE_WAKE_H_</div><div class='add'>+#define _XE_FORCE_WAKE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_force_wake_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_force_wake_init_gt(struct xe_gt *gt,</div><div class='add'>+			   struct xe_force_wake *fw);</div><div class='add'>+void xe_force_wake_init_engines(struct xe_gt *gt,</div><div class='add'>+				struct xe_force_wake *fw);</div><div class='add'>+int xe_force_wake_get(struct xe_force_wake *fw,</div><div class='add'>+		      enum xe_force_wake_domains domains);</div><div class='add'>+int xe_force_wake_put(struct xe_force_wake *fw,</div><div class='add'>+		      enum xe_force_wake_domains domains);</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+xe_force_wake_ref(struct xe_force_wake *fw,</div><div class='add'>+		  enum xe_force_wake_domains domain)</div><div class='add'>+{</div><div class='add'>+	xe_gt_assert(fw-&gt;gt, domain);</div><div class='add'>+	return fw-&gt;domains[ffs(domain) - 1].ref;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+xe_force_wake_assert_held(struct xe_force_wake *fw,</div><div class='add'>+			  enum xe_force_wake_domains domain)</div><div class='add'>+{</div><div class='add'>+	xe_gt_assert(fw-&gt;gt, fw-&gt;awake_domains &amp; domain);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_force_wake_types.h b/drivers/gpu/drm/xe/xe_force_wake_types.h<br/>new file mode 100644<br/>index 000000000000..ed0edc2cdf9f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_force_wake_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_force_wake_types.h</a></div><div class='hunk'>@@ -0,0 +1,86 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_FORCE_WAKE_TYPES_H_</div><div class='add'>+#define _XE_FORCE_WAKE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+enum xe_force_wake_domain_id {</div><div class='add'>+	XE_FW_DOMAIN_ID_GT = 0,</div><div class='add'>+	XE_FW_DOMAIN_ID_RENDER,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX0,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX1,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX2,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX3,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX4,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX5,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX6,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VDBOX7,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VEBOX0,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VEBOX1,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VEBOX2,</div><div class='add'>+	XE_FW_DOMAIN_ID_MEDIA_VEBOX3,</div><div class='add'>+	XE_FW_DOMAIN_ID_GSC,</div><div class='add'>+	XE_FW_DOMAIN_ID_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_force_wake_domains {</div><div class='add'>+	XE_FW_GT		= BIT(XE_FW_DOMAIN_ID_GT),</div><div class='add'>+	XE_FW_RENDER		= BIT(XE_FW_DOMAIN_ID_RENDER),</div><div class='add'>+	XE_FW_MEDIA		= BIT(XE_FW_DOMAIN_ID_MEDIA),</div><div class='add'>+	XE_FW_MEDIA_VDBOX0	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX0),</div><div class='add'>+	XE_FW_MEDIA_VDBOX1	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX1),</div><div class='add'>+	XE_FW_MEDIA_VDBOX2	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX2),</div><div class='add'>+	XE_FW_MEDIA_VDBOX3	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX3),</div><div class='add'>+	XE_FW_MEDIA_VDBOX4	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX4),</div><div class='add'>+	XE_FW_MEDIA_VDBOX5	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX5),</div><div class='add'>+	XE_FW_MEDIA_VDBOX6	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX6),</div><div class='add'>+	XE_FW_MEDIA_VDBOX7	= BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX7),</div><div class='add'>+	XE_FW_MEDIA_VEBOX0	= BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX0),</div><div class='add'>+	XE_FW_MEDIA_VEBOX1	= BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX1),</div><div class='add'>+	XE_FW_MEDIA_VEBOX2	= BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX2),</div><div class='add'>+	XE_FW_MEDIA_VEBOX3	= BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX3),</div><div class='add'>+	XE_FW_GSC		= BIT(XE_FW_DOMAIN_ID_GSC),</div><div class='add'>+	XE_FORCEWAKE_ALL	= BIT(XE_FW_DOMAIN_ID_COUNT) - 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_force_wake_domain - XE force wake domains</div><div class='add'>+ */</div><div class='add'>+struct xe_force_wake_domain {</div><div class='add'>+	/** @id: domain force wake id */</div><div class='add'>+	enum xe_force_wake_domain_id id;</div><div class='add'>+	/** @reg_ctl: domain wake control register address */</div><div class='add'>+	struct xe_reg reg_ctl;</div><div class='add'>+	/** @reg_ack: domain ack register address */</div><div class='add'>+	struct xe_reg reg_ack;</div><div class='add'>+	/** @val: domain wake write value */</div><div class='add'>+	u32 val;</div><div class='add'>+	/** @mask: domain mask */</div><div class='add'>+	u32 mask;</div><div class='add'>+	/** @ref: domain reference */</div><div class='add'>+	u32 ref;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_force_wake - XE force wake</div><div class='add'>+ */</div><div class='add'>+struct xe_force_wake {</div><div class='add'>+	/** @gt: back pointers to GT */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	/** @lock: protects everything force wake struct */</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+	/** @awake_domains: mask of all domains awake */</div><div class='add'>+	enum xe_force_wake_domains awake_domains;</div><div class='add'>+	/** @domains: force wake domains */</div><div class='add'>+	struct xe_force_wake_domain domains[XE_FW_DOMAIN_ID_COUNT];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gen_wa_oob.c b/drivers/gpu/drm/xe/xe_gen_wa_oob.c<br/>new file mode 100644<br/>index 000000000000..106ee2b027f0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gen_wa_oob.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gen_wa_oob.c</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define _GNU_SOURCE</div><div class='add'>+#include &lt;ctype.h&gt;</div><div class='add'>+#include &lt;errno.h&gt;</div><div class='add'>+#include &lt;stdbool.h&gt;</div><div class='add'>+#include &lt;stdio.h&gt;</div><div class='add'>+#include &lt;string.h&gt;</div><div class='add'>+</div><div class='add'>+#define HEADER \</div><div class='add'>+	"// SPDX-License-Identifier: MIT\n" \</div><div class='add'>+	"\n" \</div><div class='add'>+	"/*\n" \</div><div class='add'>+	" * DO NOT MODIFY.\n" \</div><div class='add'>+	" *\n" \</div><div class='add'>+	" * This file was generated from rules: %s\n" \</div><div class='add'>+	" */\n" \</div><div class='add'>+	"#ifndef _GENERATED_XE_WA_OOB_\n" \</div><div class='add'>+	"#define _GENERATED_XE_WA_OOB_\n" \</div><div class='add'>+	"\n" \</div><div class='add'>+	"enum {\n"</div><div class='add'>+</div><div class='add'>+#define FOOTER \</div><div class='add'>+	"};\n" \</div><div class='add'>+	"\n" \</div><div class='add'>+	"#endif\n"</div><div class='add'>+</div><div class='add'>+static void print_usage(FILE *f)</div><div class='add'>+{</div><div class='add'>+	fprintf(f, "usage: %s &lt;input-rule-file&gt; &lt;generated-c-source-file&gt; &lt;generated-c-header-file&gt;\n",</div><div class='add'>+		program_invocation_short_name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void print_parse_error(const char *err_msg, const char *line,</div><div class='add'>+			      unsigned int lineno)</div><div class='add'>+{</div><div class='add'>+	fprintf(stderr, "ERROR: %s\nERROR: %u: %.60s\n",</div><div class='add'>+		err_msg, lineno, line);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static char *strip(char *line, size_t linelen)</div><div class='add'>+{</div><div class='add'>+	while (isspace(*(line + linelen)))</div><div class='add'>+		linelen--;</div><div class='add'>+</div><div class='add'>+	line[linelen - 1] = '\0';</div><div class='add'>+</div><div class='add'>+	return  line + strspn(line, " \f\n\r\t\v");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MAX_LINE_LEN 4096</div><div class='add'>+static int parse(FILE *input, FILE *csource, FILE *cheader)</div><div class='add'>+{</div><div class='add'>+	char line[MAX_LINE_LEN + 1];</div><div class='add'>+	char *name, *prev_name = NULL, *rules;</div><div class='add'>+	unsigned int lineno = 0, idx = 0;</div><div class='add'>+</div><div class='add'>+	while (fgets(line, sizeof(line), input)) {</div><div class='add'>+		size_t linelen;</div><div class='add'>+		bool is_continuation;</div><div class='add'>+</div><div class='add'>+		if (line[0] == '\0' || line[0] == '#' || line[0] == '\n') {</div><div class='add'>+			lineno++;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		linelen = strlen(line);</div><div class='add'>+		if (linelen == MAX_LINE_LEN) {</div><div class='add'>+			print_parse_error("line too long", line, lineno);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		is_continuation = isspace(line[0]);</div><div class='add'>+		name = strip(line, linelen);</div><div class='add'>+</div><div class='add'>+		if (!is_continuation) {</div><div class='add'>+			name = strtok(name, " \t");</div><div class='add'>+			rules = strtok(NULL, "");</div><div class='add'>+		} else {</div><div class='add'>+			if (!prev_name) {</div><div class='add'>+				print_parse_error("invalid rule continuation",</div><div class='add'>+						  line, lineno);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			rules = name;</div><div class='add'>+			name = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (rules[0] == '\0') {</div><div class='add'>+			print_parse_error("invalid empty rule\n", line, lineno);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (name) {</div><div class='add'>+			fprintf(cheader, "\tXE_WA_OOB_%s = %u,\n", name, idx);</div><div class='add'>+			fprintf(csource, "{ XE_RTP_NAME(\"%s\"), XE_RTP_RULES(%s) },\n",</div><div class='add'>+				name, rules);</div><div class='add'>+		} else {</div><div class='add'>+			fprintf(csource, "{ XE_RTP_NAME(NULL), XE_RTP_RULES(%s) },\n",</div><div class='add'>+				rules);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		idx++;</div><div class='add'>+		lineno++;</div><div class='add'>+		if (!is_continuation)</div><div class='add'>+			prev_name = name;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fprintf(cheader, "\t_XE_WA_OOB_COUNT = %u\n", idx);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int main(int argc, const char *argv[])</div><div class='add'>+{</div><div class='add'>+	enum {</div><div class='add'>+		ARGS_INPUT,</div><div class='add'>+		ARGS_CSOURCE,</div><div class='add'>+		ARGS_CHEADER,</div><div class='add'>+		_ARGS_COUNT</div><div class='add'>+	};</div><div class='add'>+	struct {</div><div class='add'>+		const char *fn;</div><div class='add'>+		const char *mode;</div><div class='add'>+		FILE *f;</div><div class='add'>+	} args[] = {</div><div class='add'>+		[ARGS_INPUT] = { .fn = argv[1], .mode = "r" },</div><div class='add'>+		[ARGS_CSOURCE] = { .fn = argv[2], .mode = "w" },</div><div class='add'>+		[ARGS_CHEADER] = { .fn = argv[3], .mode = "w" },</div><div class='add'>+	};</div><div class='add'>+	int ret = 1;</div><div class='add'>+</div><div class='add'>+	if (argc &lt; 3) {</div><div class='add'>+		fprintf(stderr, "ERROR: wrong arguments\n");</div><div class='add'>+		print_usage(stderr);</div><div class='add'>+		return 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; _ARGS_COUNT; i++) {</div><div class='add'>+		args[i].f = fopen(args[i].fn, args[i].mode);</div><div class='add'>+		if (!args[i].f) {</div><div class='add'>+			fprintf(stderr, "ERROR: Can't open %s: %m\n",</div><div class='add'>+				args[i].fn);</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fprintf(args[ARGS_CHEADER].f, HEADER, args[ARGS_INPUT].fn);</div><div class='add'>+	ret = parse(args[ARGS_INPUT].f, args[ARGS_CSOURCE].f,</div><div class='add'>+		    args[ARGS_CHEADER].f);</div><div class='add'>+	if (!ret)</div><div class='add'>+		fprintf(args[ARGS_CHEADER].f, FOOTER);</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	for (int i = 0; i &lt; _ARGS_COUNT; i++) {</div><div class='add'>+		if (args[i].f)</div><div class='add'>+			fclose(args[i].f);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c<br/>new file mode 100644<br/>index 000000000000..3efd2d066bf7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ggtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt.c</a></div><div class='hunk'>@@ -0,0 +1,428 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/i915_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_wopcm.h"</div><div class='add'>+</div><div class='add'>+#define XELPG_GGTT_PTE_PAT0	BIT_ULL(52)</div><div class='add'>+#define XELPG_GGTT_PTE_PAT1	BIT_ULL(53)</div><div class='add'>+</div><div class='add'>+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */</div><div class='add'>+#define GUC_GGTT_TOP	0xFEE00000</div><div class='add'>+</div><div class='add'>+static u64 xelp_ggtt_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+				   u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	u64 pte;</div><div class='add'>+</div><div class='add'>+	pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);</div><div class='add'>+	pte |= XE_PAGE_PRESENT;</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo))</div><div class='add'>+		pte |= XE_GGTT_PTE_DM;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xelpg_ggtt_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+				    u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	u64 pte;</div><div class='add'>+</div><div class='add'>+	pte = xelp_ggtt_pte_encode_bo(bo, bo_offset, pat_index);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, pat_index &lt;= 3);</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(0))</div><div class='add'>+		pte |= XELPG_GGTT_PTE_PAT0;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(1))</div><div class='add'>+		pte |= XELPG_GGTT_PTE_PAT1;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int probe_gsm_size(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	u16 gmch_ctl, ggms;</div><div class='add'>+</div><div class='add'>+	pci_read_config_word(pdev, SNB_GMCH_CTRL, &amp;gmch_ctl);</div><div class='add'>+	ggms = (gmch_ctl &gt;&gt; BDW_GMCH_GGMS_SHIFT) &amp; BDW_GMCH_GGMS_MASK;</div><div class='add'>+	return ggms ? SZ_1M &lt;&lt; ggms : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte)</div><div class='add'>+{</div><div class='add'>+	xe_tile_assert(ggtt-&gt;tile, !(addr &amp; XE_PTE_MASK));</div><div class='add'>+	xe_tile_assert(ggtt-&gt;tile, addr &lt; ggtt-&gt;size);</div><div class='add'>+</div><div class='add'>+	writeq(pte, &amp;ggtt-&gt;gsm[addr &gt;&gt; XE_PTE_SHIFT]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)</div><div class='add'>+{</div><div class='add'>+	u16 pat_index = tile_to_xe(ggtt-&gt;tile)-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+	u64 end = start + size - 1;</div><div class='add'>+	u64 scratch_pte;</div><div class='add'>+</div><div class='add'>+	xe_tile_assert(ggtt-&gt;tile, start &lt; end);</div><div class='add'>+</div><div class='add'>+	if (ggtt-&gt;scratch)</div><div class='add'>+		scratch_pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(ggtt-&gt;scratch, 0,</div><div class='add'>+							  pat_index);</div><div class='add'>+	else</div><div class='add'>+		scratch_pte = 0;</div><div class='add'>+</div><div class='add'>+	while (start &lt; end) {</div><div class='add'>+		xe_ggtt_set_pte(ggtt, start, scratch_pte);</div><div class='add'>+		start += XE_PAGE_SIZE;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ggtt_fini_early(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_ggtt *ggtt = arg;</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;ggtt-&gt;lock);</div><div class='add'>+	drm_mm_takedown(&amp;ggtt-&gt;mm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ggtt_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_ggtt *ggtt = arg;</div><div class='add'>+</div><div class='add'>+	ggtt-&gt;scratch = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void primelockdep(struct xe_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	if (!IS_ENABLED(CONFIG_LOCKDEP))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fs_reclaim_acquire(GFP_KERNEL);</div><div class='add'>+	might_lock(&amp;ggtt-&gt;lock);</div><div class='add'>+	fs_reclaim_release(GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_ggtt_pt_ops xelp_pt_ops = {</div><div class='add'>+	.pte_encode_bo = xelp_ggtt_pte_encode_bo,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_ggtt_pt_ops xelpg_pt_ops = {</div><div class='add'>+	.pte_encode_bo = xelpg_ggtt_pte_encode_bo,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Early GGTT initialization, which allows to create new mappings usable by the</div><div class='add'>+ * GuC.</div><div class='add'>+ * Mappings are not usable by the HW engines, as it doesn't have scratch /</div><div class='add'>+ * initial clear done to it yet. That will happen in the regular, non-early</div><div class='add'>+ * GGTT init.</div><div class='add'>+ */</div><div class='add'>+int xe_ggtt_init_early(struct xe_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(ggtt-&gt;tile);</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	unsigned int gsm_size;</div><div class='add'>+</div><div class='add'>+	gsm_size = probe_gsm_size(pdev);</div><div class='add'>+	if (gsm_size == 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Hardware reported no preallocated GSM\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ggtt-&gt;gsm = ggtt-&gt;tile-&gt;mmio.regs + SZ_8M;</div><div class='add'>+	ggtt-&gt;size = (gsm_size / 8) * (u64) XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K)</div><div class='add'>+		ggtt-&gt;flags |= XE_GGTT_FLAGS_64K;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * 8B per entry, each points to a 4KB page.</div><div class='add'>+	 *</div><div class='add'>+	 * The GuC address space is limited on both ends of the GGTT, because</div><div class='add'>+	 * the GuC shim HW redirects accesses to those addresses to other HW</div><div class='add'>+	 * areas instead of going through the GGTT. On the bottom end, the GuC</div><div class='add'>+	 * can't access offsets below the WOPCM size, while on the top side the</div><div class='add'>+	 * limit is fixed at GUC_GGTT_TOP. To keep things simple, instead of</div><div class='add'>+	 * checking each object to see if they are accessed by GuC or not, we</div><div class='add'>+	 * just exclude those areas from the allocator. Additionally, to</div><div class='add'>+	 * simplify the driver load, we use the maximum WOPCM size in this logic</div><div class='add'>+	 * instead of the programmed one, so we don't need to wait until the</div><div class='add'>+	 * actual size to be programmed is determined (which requires FW fetch)</div><div class='add'>+	 * before initializing the GGTT. These simplifications might waste space</div><div class='add'>+	 * in the GGTT (about 20-25 MBs depending on the platform) but we can</div><div class='add'>+	 * live with this.</div><div class='add'>+	 *</div><div class='add'>+	 * Another benifit of this is the GuC bootrom can't access anything</div><div class='add'>+	 * below the WOPCM max size so anything the bootom needs to access (e.g.</div><div class='add'>+	 * a RSA key) needs to be placed in the GGTT above the WOPCM max size.</div><div class='add'>+	 * Starting the GGTT allocations above the WOPCM max give us the correct</div><div class='add'>+	 * placement for free.</div><div class='add'>+	 */</div><div class='add'>+	if (ggtt-&gt;size &gt; GUC_GGTT_TOP)</div><div class='add'>+		ggtt-&gt;size = GUC_GGTT_TOP;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		ggtt-&gt;pt_ops = &amp;xelpg_pt_ops;</div><div class='add'>+	else</div><div class='add'>+		ggtt-&gt;pt_ops = &amp;xelp_pt_ops;</div><div class='add'>+</div><div class='add'>+	drm_mm_init(&amp;ggtt-&gt;mm, xe_wopcm_size(xe),</div><div class='add'>+		    ggtt-&gt;size - xe_wopcm_size(xe));</div><div class='add'>+	mutex_init(&amp;ggtt-&gt;lock);</div><div class='add'>+	primelockdep(ggtt);</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, ggtt_fini_early, ggtt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	struct drm_mm_node *hole;</div><div class='add'>+	u64 start, end;</div><div class='add'>+</div><div class='add'>+	/* Display may have allocated inside ggtt, so be careful with clearing here */</div><div class='add'>+	xe_device_mem_access_get(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+	mutex_lock(&amp;ggtt-&gt;lock);</div><div class='add'>+	drm_mm_for_each_hole(hole, &amp;ggtt-&gt;mm, start, end)</div><div class='add'>+		xe_ggtt_clear(ggtt, start, end - start);</div><div class='add'>+</div><div class='add'>+	xe_ggtt_invalidate(ggtt);</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+	xe_device_mem_access_put(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_init(struct xe_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(ggtt-&gt;tile);</div><div class='add'>+	unsigned int flags;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * So we don't need to worry about 64K GGTT layout when dealing with</div><div class='add'>+	 * scratch entires, rather keep the scratch page in system memory on</div><div class='add'>+	 * platforms where 64K pages are needed for VRAM.</div><div class='add'>+	 */</div><div class='add'>+	flags = XE_BO_CREATE_PINNED_BIT;</div><div class='add'>+	if (ggtt-&gt;flags &amp; XE_GGTT_FLAGS_64K)</div><div class='add'>+		flags |= XE_BO_CREATE_SYSTEM_BIT;</div><div class='add'>+	else</div><div class='add'>+		flags |= XE_BO_CREATE_VRAM_IF_DGFX(ggtt-&gt;tile);</div><div class='add'>+</div><div class='add'>+	ggtt-&gt;scratch = xe_managed_bo_create_pin_map(xe, ggtt-&gt;tile, XE_PAGE_SIZE, flags);</div><div class='add'>+	if (IS_ERR(ggtt-&gt;scratch)) {</div><div class='add'>+		err = PTR_ERR(ggtt-&gt;scratch);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_map_memset(xe, &amp;ggtt-&gt;scratch-&gt;vmap, 0, 0, ggtt-&gt;scratch-&gt;size);</div><div class='add'>+</div><div class='add'>+	xe_ggtt_initial_clear(ggtt);</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, ggtt_fini, ggtt);</div><div class='add'>+err:</div><div class='add'>+	ggtt-&gt;scratch = NULL;</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define GUC_TLB_INV_CR				XE_REG(0xcee8)</div><div class='add'>+#define   GUC_TLB_INV_CR_INVALIDATE		REG_BIT(0)</div><div class='add'>+#define PVC_GUC_TLB_INV_DESC0			XE_REG(0xcf7c)</div><div class='add'>+#define   PVC_GUC_TLB_INV_DESC0_VALID		REG_BIT(0)</div><div class='add'>+#define PVC_GUC_TLB_INV_DESC1			XE_REG(0xcf80)</div><div class='add'>+#define   PVC_GUC_TLB_INV_DESC1_INVALIDATE	REG_BIT(6)</div><div class='add'>+</div><div class='add'>+static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (!gt)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Invalidation can happen when there's no in-flight work keeping the</div><div class='add'>+	 * GT awake.  We need to explicitly grab forcewake to ensure the GT</div><div class='add'>+	 * and GuC are accessible.</div><div class='add'>+	 */</div><div class='add'>+	xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	/* TODO: vfunc for GuC vs. non-GuC */</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;uc.guc.submission_state.enabled) {</div><div class='add'>+		int seqno;</div><div class='add'>+</div><div class='add'>+		seqno = xe_gt_tlb_invalidation_guc(gt);</div><div class='add'>+		xe_gt_assert(gt, seqno &gt; 0);</div><div class='add'>+		if (seqno &gt; 0)</div><div class='add'>+			xe_gt_tlb_invalidation_wait(gt, seqno);</div><div class='add'>+	} else if (xe_device_uc_enabled(gt_to_xe(gt))) {</div><div class='add'>+		struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+		if (xe-&gt;info.platform == XE_PVC || GRAPHICS_VER(xe) &gt;= 20) {</div><div class='add'>+			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,</div><div class='add'>+					PVC_GUC_TLB_INV_DESC1_INVALIDATE);</div><div class='add'>+			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,</div><div class='add'>+					PVC_GUC_TLB_INV_DESC0_VALID);</div><div class='add'>+		} else</div><div class='add'>+			xe_mmio_write32(gt, GUC_TLB_INV_CR,</div><div class='add'>+					GUC_TLB_INV_CR_INVALIDATE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_invalidate(struct xe_ggtt *ggtt)</div><div class='add'>+{</div><div class='add'>+	/* Each GT in a tile has its own TLB to cache GGTT lookups */</div><div class='add'>+	ggtt_invalidate_gt_tlb(ggtt-&gt;tile-&gt;primary_gt);</div><div class='add'>+	ggtt_invalidate_gt_tlb(ggtt-&gt;tile-&gt;media_gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix)</div><div class='add'>+{</div><div class='add'>+	u16 pat_index = tile_to_xe(ggtt-&gt;tile)-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+	u64 addr, scratch_pte;</div><div class='add'>+</div><div class='add'>+	scratch_pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(ggtt-&gt;scratch, 0, pat_index);</div><div class='add'>+</div><div class='add'>+	printk("%sGlobal GTT:", prefix);</div><div class='add'>+	for (addr = 0; addr &lt; ggtt-&gt;size; addr += XE_PAGE_SIZE) {</div><div class='add'>+		unsigned int i = addr / XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+		xe_tile_assert(ggtt-&gt;tile, addr &lt;= U32_MAX);</div><div class='add'>+		if (ggtt-&gt;gsm[i] == scratch_pte)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		printk("%s    ggtt[0x%08x] = 0x%016llx",</div><div class='add'>+		       prefix, (u32)addr, ggtt-&gt;gsm[i]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_insert_special_node_locked(struct xe_ggtt *ggtt, struct drm_mm_node *node,</div><div class='add'>+				       u32 size, u32 align, u32 mm_flags)</div><div class='add'>+{</div><div class='add'>+	return drm_mm_insert_node_generic(&amp;ggtt-&gt;mm, node, size, align, 0,</div><div class='add'>+					  mm_flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,</div><div class='add'>+				u32 size, u32 align)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ggtt-&gt;lock);</div><div class='add'>+	ret = xe_ggtt_insert_special_node_locked(ggtt, node, size,</div><div class='add'>+						 align, DRM_MM_INSERT_HIGH);</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	u16 pat_index = tile_to_xe(ggtt-&gt;tile)-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+	u64 start = bo-&gt;ggtt_node.start;</div><div class='add'>+	u64 offset, pte;</div><div class='add'>+</div><div class='add'>+	for (offset = 0; offset &lt; bo-&gt;size; offset += XE_PAGE_SIZE) {</div><div class='add'>+		pte = ggtt-&gt;pt_ops-&gt;pte_encode_bo(bo, offset, pat_index);</div><div class='add'>+		xe_ggtt_set_pte(ggtt, start + offset, pte);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_ggtt_invalidate(ggtt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,</div><div class='add'>+				  u64 start, u64 end)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	u64 alignment = XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_vram(bo) &amp;&amp; ggtt-&gt;flags &amp; XE_GGTT_FLAGS_64K)</div><div class='add'>+		alignment = SZ_64K;</div><div class='add'>+</div><div class='add'>+	if (XE_WARN_ON(bo-&gt;ggtt_node.size)) {</div><div class='add'>+		/* Someone's already inserted this BO in the GGTT */</div><div class='add'>+		xe_tile_assert(ggtt-&gt;tile, bo-&gt;ggtt_node.size == bo-&gt;size);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_bo_validate(bo, NULL, false);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+	mutex_lock(&amp;ggtt-&gt;lock);</div><div class='add'>+	err = drm_mm_insert_node_in_range(&amp;ggtt-&gt;mm, &amp;bo-&gt;ggtt_node, bo-&gt;size,</div><div class='add'>+					  alignment, 0, start, end, 0);</div><div class='add'>+	if (!err)</div><div class='add'>+		xe_ggtt_map_bo(ggtt, bo);</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+	xe_device_mem_access_put(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,</div><div class='add'>+			 u64 start, u64 end)</div><div class='add'>+{</div><div class='add'>+	return __xe_ggtt_insert_bo_at(ggtt, bo, start, end);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_insert_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	return __xe_ggtt_insert_bo_at(ggtt, bo, 0, U64_MAX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node)</div><div class='add'>+{</div><div class='add'>+	xe_device_mem_access_get(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+	mutex_lock(&amp;ggtt-&gt;lock);</div><div class='add'>+</div><div class='add'>+	xe_ggtt_clear(ggtt, node-&gt;start, node-&gt;size);</div><div class='add'>+	drm_mm_remove_node(node);</div><div class='add'>+	node-&gt;size = 0;</div><div class='add'>+</div><div class='add'>+	xe_ggtt_invalidate(ggtt);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+	xe_device_mem_access_put(tile_to_xe(ggtt-&gt;tile));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ggtt_remove_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	if (XE_WARN_ON(!bo-&gt;ggtt_node.size))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* This BO is not currently in the GGTT */</div><div class='add'>+	xe_tile_assert(ggtt-&gt;tile, bo-&gt;ggtt_node.size == bo-&gt;size);</div><div class='add'>+</div><div class='add'>+	xe_ggtt_remove_node(ggtt, &amp;bo-&gt;ggtt_node);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ggtt_dump(struct xe_ggtt *ggtt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = mutex_lock_interruptible(&amp;ggtt-&gt;lock);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	drm_mm_print(&amp;ggtt-&gt;mm, p);</div><div class='add'>+	mutex_unlock(&amp;ggtt-&gt;lock);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h<br/>new file mode 100644<br/>index 000000000000..a09c166dff70<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ggtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GGTT_H_</div><div class='add'>+#define _XE_GGTT_H_</div><div class='add'>+</div><div class='add'>+#include "xe_ggtt_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte);</div><div class='add'>+void xe_ggtt_invalidate(struct xe_ggtt *ggtt);</div><div class='add'>+int xe_ggtt_init_early(struct xe_ggtt *ggtt);</div><div class='add'>+int xe_ggtt_init(struct xe_ggtt *ggtt);</div><div class='add'>+void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix);</div><div class='add'>+</div><div class='add'>+int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,</div><div class='add'>+				u32 size, u32 align);</div><div class='add'>+int xe_ggtt_insert_special_node_locked(struct xe_ggtt *ggtt,</div><div class='add'>+				       struct drm_mm_node *node,</div><div class='add'>+				       u32 size, u32 align, u32 mm_flags);</div><div class='add'>+void xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node);</div><div class='add'>+void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo);</div><div class='add'>+int xe_ggtt_insert_bo(struct xe_ggtt *ggtt, struct xe_bo *bo);</div><div class='add'>+int xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,</div><div class='add'>+			 u64 start, u64 end);</div><div class='add'>+void xe_ggtt_remove_bo(struct xe_ggtt *ggtt, struct xe_bo *bo);</div><div class='add'>+</div><div class='add'>+int xe_ggtt_dump(struct xe_ggtt *ggtt, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ggtt_types.h b/drivers/gpu/drm/xe/xe_ggtt_types.h<br/>new file mode 100644<br/>index 000000000000..d8c584d9a8c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ggtt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ggtt_types.h</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GGTT_TYPES_H_</div><div class='add'>+#define _XE_GGTT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_pt_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+struct xe_ggtt_pt_ops {</div><div class='add'>+	u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_ggtt {</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	u64 size;</div><div class='add'>+</div><div class='add'>+#define XE_GGTT_FLAGS_64K BIT(0)</div><div class='add'>+	unsigned int flags;</div><div class='add'>+</div><div class='add'>+	struct xe_bo *scratch;</div><div class='add'>+</div><div class='add'>+	struct mutex lock;</div><div class='add'>+</div><div class='add'>+	u64 __iomem *gsm;</div><div class='add'>+</div><div class='add'>+	const struct xe_ggtt_pt_ops *pt_ops;</div><div class='add'>+</div><div class='add'>+	struct drm_mm mm;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.c b/drivers/gpu/drm/xe/xe_gpu_scheduler.c<br/>new file mode 100644<br/>index 000000000000..e4ad1d6ce1d5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gpu_scheduler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler.c</a></div><div class='hunk'>@@ -0,0 +1,101 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gpu_scheduler.h"</div><div class='add'>+</div><div class='add'>+static void xe_sched_process_msg_queue(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	if (!READ_ONCE(sched-&gt;base.pause_submit))</div><div class='add'>+		queue_work(sched-&gt;base.submit_wq, &amp;sched-&gt;work_process_msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_sched_process_msg_queue_if_ready(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+	msg = list_first_entry_or_null(&amp;sched-&gt;msgs, struct xe_sched_msg, link);</div><div class='add'>+	if (msg)</div><div class='add'>+		xe_sched_process_msg_queue(sched);</div><div class='add'>+	spin_unlock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_sched_msg *</div><div class='add'>+xe_sched_get_msg(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+	msg = list_first_entry_or_null(&amp;sched-&gt;msgs,</div><div class='add'>+				       struct xe_sched_msg, link);</div><div class='add'>+	if (msg)</div><div class='add'>+		list_del(&amp;msg-&gt;link);</div><div class='add'>+	spin_unlock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+</div><div class='add'>+	return msg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_sched_process_msg_work(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_gpu_scheduler *sched =</div><div class='add'>+		container_of(w, struct xe_gpu_scheduler, work_process_msg);</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	if (READ_ONCE(sched-&gt;base.pause_submit))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	msg = xe_sched_get_msg(sched);</div><div class='add'>+	if (msg) {</div><div class='add'>+		sched-&gt;ops-&gt;process_msg(msg);</div><div class='add'>+</div><div class='add'>+		xe_sched_process_msg_queue_if_ready(sched);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_sched_init(struct xe_gpu_scheduler *sched,</div><div class='add'>+		  const struct drm_sched_backend_ops *ops,</div><div class='add'>+		  const struct xe_sched_backend_ops *xe_ops,</div><div class='add'>+		  struct workqueue_struct *submit_wq,</div><div class='add'>+		  uint32_t hw_submission, unsigned hang_limit,</div><div class='add'>+		  long timeout, struct workqueue_struct *timeout_wq,</div><div class='add'>+		  atomic_t *score, const char *name,</div><div class='add'>+		  struct device *dev)</div><div class='add'>+{</div><div class='add'>+	sched-&gt;ops = xe_ops;</div><div class='add'>+	INIT_LIST_HEAD(&amp;sched-&gt;msgs);</div><div class='add'>+	INIT_WORK(&amp;sched-&gt;work_process_msg, xe_sched_process_msg_work);</div><div class='add'>+</div><div class='add'>+	return drm_sched_init(&amp;sched-&gt;base, ops, submit_wq, 1, hw_submission,</div><div class='add'>+			      hang_limit, timeout, timeout_wq, score, name,</div><div class='add'>+			      dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_fini(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	xe_sched_submission_stop(sched);</div><div class='add'>+	drm_sched_fini(&amp;sched-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_submission_start(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	drm_sched_wqueue_start(&amp;sched-&gt;base);</div><div class='add'>+	queue_work(sched-&gt;base.submit_wq, &amp;sched-&gt;work_process_msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_submission_stop(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	drm_sched_wqueue_stop(&amp;sched-&gt;base);</div><div class='add'>+	cancel_work_sync(&amp;sched-&gt;work_process_msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_add_msg(struct xe_gpu_scheduler *sched,</div><div class='add'>+		      struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	spin_lock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+	list_add_tail(&amp;msg-&gt;link, &amp;sched-&gt;msgs);</div><div class='add'>+	spin_unlock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+</div><div class='add'>+	xe_sched_process_msg_queue(sched);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.h b/drivers/gpu/drm/xe/xe_gpu_scheduler.h<br/>new file mode 100644<br/>index 000000000000..10c6bb9c9386<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gpu_scheduler.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler.h</a></div><div class='hunk'>@@ -0,0 +1,73 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GPU_SCHEDULER_H_</div><div class='add'>+#define _XE_GPU_SCHEDULER_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gpu_scheduler_types.h"</div><div class='add'>+#include "xe_sched_job_types.h"</div><div class='add'>+</div><div class='add'>+int xe_sched_init(struct xe_gpu_scheduler *sched,</div><div class='add'>+		  const struct drm_sched_backend_ops *ops,</div><div class='add'>+		  const struct xe_sched_backend_ops *xe_ops,</div><div class='add'>+		  struct workqueue_struct *submit_wq,</div><div class='add'>+		  uint32_t hw_submission, unsigned hang_limit,</div><div class='add'>+		  long timeout, struct workqueue_struct *timeout_wq,</div><div class='add'>+		  atomic_t *score, const char *name,</div><div class='add'>+		  struct device *dev);</div><div class='add'>+void xe_sched_fini(struct xe_gpu_scheduler *sched);</div><div class='add'>+</div><div class='add'>+void xe_sched_submission_start(struct xe_gpu_scheduler *sched);</div><div class='add'>+void xe_sched_submission_stop(struct xe_gpu_scheduler *sched);</div><div class='add'>+</div><div class='add'>+void xe_sched_add_msg(struct xe_gpu_scheduler *sched,</div><div class='add'>+		      struct xe_sched_msg *msg);</div><div class='add'>+</div><div class='add'>+static inline void xe_sched_stop(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	drm_sched_stop(&amp;sched-&gt;base, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_sched_tdr_queue_imm(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	drm_sched_tdr_queue_imm(&amp;sched-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_sched_resubmit_jobs(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	drm_sched_resubmit_jobs(&amp;sched-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool</div><div class='add'>+xe_sched_invalidate_job(struct xe_sched_job *job, int threshold)</div><div class='add'>+{</div><div class='add'>+	return drm_sched_invalidate_job(&amp;job-&gt;drm, threshold);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_sched_add_pending_job(struct xe_gpu_scheduler *sched,</div><div class='add'>+					    struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	list_add(&amp;job-&gt;drm.list, &amp;sched-&gt;base.pending_list);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+struct xe_sched_job *xe_sched_first_pending_job(struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	return list_first_entry_or_null(&amp;sched-&gt;base.pending_list,</div><div class='add'>+					struct xe_sched_job, drm.list);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+xe_sched_entity_init(struct xe_sched_entity *entity,</div><div class='add'>+		     struct xe_gpu_scheduler *sched)</div><div class='add'>+{</div><div class='add'>+	return drm_sched_entity_init(entity, 0,</div><div class='add'>+				     (struct drm_gpu_scheduler **)&amp;sched,</div><div class='add'>+				     1, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define xe_sched_entity_fini drm_sched_entity_fini</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h b/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h<br/>new file mode 100644<br/>index 000000000000..6731b13da8bb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gpu_scheduler_types.h</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GPU_SCHEDULER_TYPES_H_</div><div class='add'>+#define _XE_GPU_SCHEDULER_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/gpu_scheduler.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_sched_msg - an in-band (relative to GPU scheduler run queue)</div><div class='add'>+ * message</div><div class='add'>+ *</div><div class='add'>+ * Generic enough for backend defined messages, backend can expand if needed.</div><div class='add'>+ */</div><div class='add'>+struct xe_sched_msg {</div><div class='add'>+	/** @link: list link into the gpu scheduler list of messages */</div><div class='add'>+	struct list_head		link;</div><div class='add'>+	/**</div><div class='add'>+	 * @private_data: opaque pointer to message private data (backend defined)</div><div class='add'>+	 */</div><div class='add'>+	void				*private_data;</div><div class='add'>+	/** @opcode: opcode of message (backend defined) */</div><div class='add'>+	unsigned int			opcode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_sched_backend_ops - Define the backend operations called by the</div><div class='add'>+ * scheduler</div><div class='add'>+ */</div><div class='add'>+struct xe_sched_backend_ops {</div><div class='add'>+	/**</div><div class='add'>+	 * @process_msg: Process a message. Allowed to block, it is this</div><div class='add'>+	 * function's responsibility to free message if dynamically allocated.</div><div class='add'>+	 */</div><div class='add'>+	void (*process_msg)(struct xe_sched_msg *msg);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_gpu_scheduler - Xe GPU scheduler</div><div class='add'>+ */</div><div class='add'>+struct xe_gpu_scheduler {</div><div class='add'>+	/** @base: DRM GPU scheduler */</div><div class='add'>+	struct drm_gpu_scheduler		base;</div><div class='add'>+	/** @ops: Xe scheduler ops */</div><div class='add'>+	const struct xe_sched_backend_ops	*ops;</div><div class='add'>+	/** @msgs: list of messages to be processed in @work_process_msg */</div><div class='add'>+	struct list_head			msgs;</div><div class='add'>+	/** @work_process_msg: processes messages */</div><div class='add'>+	struct work_struct		work_process_msg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define xe_sched_entity		drm_sched_entity</div><div class='add'>+#define xe_sched_policy		drm_sched_policy</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c<br/>new file mode 100644<br/>index 000000000000..a8a895cf4b44<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc.c</a></div><div class='hunk'>@@ -0,0 +1,438 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gsc.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/gsc_mkhi_commands_abi.h"</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gsc_submit.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_huc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+#include "instructions/xe_gsc_commands.h"</div><div class='add'>+#include "regs/xe_gsc_regs.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+gsc_to_gt(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	return container_of(gsc, struct xe_gt, uc.gsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int memcpy_fw(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 fw_size = gsc-&gt;fw.size;</div><div class='add'>+	void *storage;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: xe_migrate_copy does not work with stolen mem yet, so we use</div><div class='add'>+	 * a memcpy for now.</div><div class='add'>+	 */</div><div class='add'>+	storage = kmalloc(fw_size, GFP_KERNEL);</div><div class='add'>+	if (!storage)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_from(xe, storage, &amp;gsc-&gt;fw.bo-&gt;vmap, 0, fw_size);</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;gsc-&gt;private-&gt;vmap, 0, storage, fw_size);</div><div class='add'>+	xe_map_memset(xe, &amp;gsc-&gt;private-&gt;vmap, fw_size, 0, gsc-&gt;private-&gt;size - fw_size);</div><div class='add'>+</div><div class='add'>+	kfree(storage);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_gsc_upload(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	u64 offset = xe_bo_ggtt_addr(gsc-&gt;private);</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	long timeout;</div><div class='add'>+</div><div class='add'>+	bb = xe_bb_new(gt, 4, false);</div><div class='add'>+	if (IS_ERR(bb))</div><div class='add'>+		return PTR_ERR(bb);</div><div class='add'>+</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = GSC_FW_LOAD;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = lower_32_bits(offset);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = upper_32_bits(offset);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = (gsc-&gt;private-&gt;size / SZ_4K) | GSC_FW_LOAD_LIMIT_VALID;</div><div class='add'>+</div><div class='add'>+	job = xe_bb_create_job(gsc-&gt;q, bb);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+		return PTR_ERR(job);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	timeout = dma_fence_wait_timeout(fence, false, HZ);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+	if (timeout &lt; 0)</div><div class='add'>+		return timeout;</div><div class='add'>+	else if (!timeout)</div><div class='add'>+		return -ETIME;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define version_query_wr(xe_, map_, offset_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(xe_, map_, offset_, struct gsc_get_compatibility_version_in, field_, val_)</div><div class='add'>+#define version_query_rd(xe_, map_, offset_, field_) \</div><div class='add'>+	xe_map_rd_field(xe_, map_, offset_, struct gsc_get_compatibility_version_out, field_)</div><div class='add'>+</div><div class='add'>+static u32 emit_version_query_msg(struct xe_device *xe, struct iosys_map *map, u32 wr_offset)</div><div class='add'>+{</div><div class='add'>+	xe_map_memset(xe, map, wr_offset, 0, sizeof(struct gsc_get_compatibility_version_in));</div><div class='add'>+</div><div class='add'>+	version_query_wr(xe, map, wr_offset, header.group_id, MKHI_GROUP_ID_GFX_SRV);</div><div class='add'>+	version_query_wr(xe, map, wr_offset, header.command,</div><div class='add'>+			 MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION);</div><div class='add'>+</div><div class='add'>+	return wr_offset + sizeof(struct gsc_get_compatibility_version_in);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define GSC_VER_PKT_SZ SZ_4K /* 4K each for input and output */</div><div class='add'>+static int query_compatibility_version(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_uc_fw_version *compat = &amp;gsc-&gt;fw.versions.found[XE_UC_FW_VER_COMPATIBILITY];</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	u32 wr_offset;</div><div class='add'>+	u32 rd_offset;</div><div class='add'>+	u64 ggtt_offset;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(xe, tile, NULL, GSC_VER_PKT_SZ * 2,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_SYSTEM_BIT |</div><div class='add'>+				  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		xe_gt_err(gt, "failed to allocate bo for GSC version query\n");</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ggtt_offset = xe_bo_ggtt_addr(bo);</div><div class='add'>+</div><div class='add'>+	wr_offset = xe_gsc_emit_header(xe, &amp;bo-&gt;vmap, 0, HECI_MEADDRESS_MKHI, 0,</div><div class='add'>+				       sizeof(struct gsc_get_compatibility_version_in));</div><div class='add'>+	wr_offset = emit_version_query_msg(xe, &amp;bo-&gt;vmap, wr_offset);</div><div class='add'>+</div><div class='add'>+	err = xe_gsc_pkt_submit_kernel(gsc, ggtt_offset, wr_offset,</div><div class='add'>+				       ggtt_offset + GSC_VER_PKT_SZ,</div><div class='add'>+				       GSC_VER_PKT_SZ);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_gt_err(gt,</div><div class='add'>+			  "failed to submit GSC request for compatibility version: %d\n",</div><div class='add'>+			  err);</div><div class='add'>+		goto out_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_gsc_read_out_header(xe, &amp;bo-&gt;vmap, GSC_VER_PKT_SZ,</div><div class='add'>+				     sizeof(struct gsc_get_compatibility_version_out),</div><div class='add'>+				     &amp;rd_offset);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_gt_err(gt, "HuC: invalid GSC reply for version query (err=%d)\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	compat-&gt;major = version_query_rd(xe, &amp;bo-&gt;vmap, rd_offset, compat_major);</div><div class='add'>+	compat-&gt;minor = version_query_rd(xe, &amp;bo-&gt;vmap, rd_offset, compat_minor);</div><div class='add'>+</div><div class='add'>+	xe_gt_info(gt, "found GSC cv%u.%u\n", compat-&gt;major, compat-&gt;minor);</div><div class='add'>+</div><div class='add'>+out_bo:</div><div class='add'>+	xe_bo_unpin_map_no_vm(bo);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gsc_fw_is_loaded(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	return xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &amp;</div><div class='add'>+			      HECI1_FWSTS1_INIT_COMPLETE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gsc_fw_wait(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * GSC load can take up to 250ms from the moment the instruction is</div><div class='add'>+	 * executed by the GSCCS. To account for possible submission delays or</div><div class='add'>+	 * other issues, we use a 500ms timeout in the wait here.</div><div class='add'>+	 */</div><div class='add'>+	return xe_mmio_wait32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE),</div><div class='add'>+			      HECI1_FWSTS1_INIT_COMPLETE,</div><div class='add'>+			      HECI1_FWSTS1_INIT_COMPLETE,</div><div class='add'>+			      500 * USEC_PER_MSEC, NULL, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gsc_upload(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* we should only be here if the init step were successful */</div><div class='add'>+	xe_assert(xe, xe_uc_fw_is_loadable(&amp;gsc-&gt;fw) &amp;&amp; gsc-&gt;q);</div><div class='add'>+</div><div class='add'>+	if (gsc_fw_is_loaded(gt)) {</div><div class='add'>+		xe_gt_err(gt, "GSC already loaded at upload time\n");</div><div class='add'>+		return -EEXIST;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = memcpy_fw(gsc);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_gt_err(gt, "Failed to memcpy GSC FW\n");</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * GSC is only killed by an FLR, so we need to trigger one on unload to</div><div class='add'>+	 * make sure we stop it. This is because we assign a chunk of memory to</div><div class='add'>+	 * the GSC as part of the FW load, so we need to make sure it stops</div><div class='add'>+	 * using it when we release it to the system on driver unload. Note that</div><div class='add'>+	 * this is not a problem of the unload per-se, because the GSC will not</div><div class='add'>+	 * touch that memory unless there are requests for it coming from the</div><div class='add'>+	 * driver; therefore, no accesses will happen while Xe is not loaded,</div><div class='add'>+	 * but if we re-load the driver then the GSC might wake up and try to</div><div class='add'>+	 * access that old memory location again.</div><div class='add'>+	 * Given that an FLR is a very disruptive action (see the FLR function</div><div class='add'>+	 * for details), we want to do it as the last action before releasing</div><div class='add'>+	 * the access to the MMIO bar, which means we need to do it as part of</div><div class='add'>+	 * mmio cleanup.</div><div class='add'>+	 */</div><div class='add'>+	xe-&gt;needs_flr_on_fini = true;</div><div class='add'>+</div><div class='add'>+	err = emit_gsc_upload(gsc);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_gt_err(gt, "Failed to emit GSC FW upload (%pe)\n", ERR_PTR(err));</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = gsc_fw_wait(gt);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_gt_err(gt, "Failed to wait for GSC load (%pe)\n", ERR_PTR(err));</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = query_compatibility_version(gsc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_uc_fw_check_version_requirements(&amp;gsc-&gt;fw);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_gt_dbg(gt, "GSC FW async load completed\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gsc_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct xe_gsc *gsc = container_of(work, typeof(*gsc), work);</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC);</div><div class='add'>+</div><div class='add'>+	ret = gsc_upload(gsc);</div><div class='add'>+	if (ret &amp;&amp; ret != -EEXIST) {</div><div class='add'>+		xe_uc_fw_change_status(&amp;gsc-&gt;fw, XE_UC_FIRMWARE_LOAD_FAIL);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;gsc-&gt;fw, XE_UC_FIRMWARE_TRANSFERRED);</div><div class='add'>+</div><div class='add'>+	/* HuC auth failure is not fatal */</div><div class='add'>+	if (xe_huc_is_authenticated(&amp;gt-&gt;uc.huc, XE_HUC_AUTH_VIA_GUC))</div><div class='add'>+		xe_huc_auth(&amp;gt-&gt;uc.huc, XE_HUC_AUTH_VIA_GSC);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gsc_init(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	gsc-&gt;fw.type = XE_UC_FW_TYPE_GSC;</div><div class='add'>+	INIT_WORK(&amp;gsc-&gt;work, gsc_work);</div><div class='add'>+</div><div class='add'>+	/* The GSC uC is only available on the media GT */</div><div class='add'>+	if (tile-&gt;media_gt &amp;&amp; (gt != tile-&gt;media_gt)) {</div><div class='add'>+		xe_uc_fw_change_status(&amp;gsc-&gt;fw, XE_UC_FIRMWARE_NOT_SUPPORTED);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Some platforms can have GuC but not GSC. That would cause</div><div class='add'>+	 * xe_uc_fw_init(gsc) to return a "not supported" failure code and abort</div><div class='add'>+	 * all firmware loading. So check for GSC being enabled before</div><div class='add'>+	 * propagating the failure back up. That way the higher level will keep</div><div class='add'>+	 * going and load GuC as appropriate.</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_uc_fw_init(&amp;gsc-&gt;fw);</div><div class='add'>+	if (!xe_uc_fw_is_enabled(&amp;gsc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+	else if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_gt_err(gt, "GSC init failed with %d", ret);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_resources(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_gsc *gsc = arg;</div><div class='add'>+</div><div class='add'>+	if (gsc-&gt;wq) {</div><div class='add'>+		destroy_workqueue(gsc-&gt;wq);</div><div class='add'>+		gsc-&gt;wq = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gsc-&gt;q) {</div><div class='add'>+		xe_exec_queue_put(gsc-&gt;q);</div><div class='add'>+		gsc-&gt;q = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gsc-&gt;private) {</div><div class='add'>+		xe_bo_unpin_map_no_vm(gsc-&gt;private);</div><div class='add'>+		gsc-&gt;private = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gsc_init_post_hwconfig(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_hw_engine *hwe = xe_gt_hw_engine(gt, XE_ENGINE_CLASS_OTHER, 0, true);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	struct workqueue_struct *wq;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_available(&amp;gsc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!hwe)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(xe, tile, NULL, SZ_4M,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_STOLEN_BIT |</div><div class='add'>+				  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	q = xe_exec_queue_create(xe, NULL,</div><div class='add'>+				 BIT(hwe-&gt;logical_instance), 1, hwe,</div><div class='add'>+				 EXEC_QUEUE_FLAG_KERNEL |</div><div class='add'>+				 EXEC_QUEUE_FLAG_PERMANENT);</div><div class='add'>+	if (IS_ERR(q)) {</div><div class='add'>+		xe_gt_err(gt, "Failed to create queue for GSC submission\n");</div><div class='add'>+		err = PTR_ERR(q);</div><div class='add'>+		goto out_bo;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wq = alloc_ordered_workqueue("gsc-ordered-wq", 0);</div><div class='add'>+	if (!wq) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto out_q;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gsc-&gt;private = bo;</div><div class='add'>+	gsc-&gt;q = q;</div><div class='add'>+	gsc-&gt;wq = wq;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, free_resources, gsc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;gsc-&gt;fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_q:</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+out_bo:</div><div class='add'>+	xe_bo_unpin_map_no_vm(bo);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gsc_load_start(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_loadable(&amp;gsc-&gt;fw) || !gsc-&gt;q)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* GSC FW survives GT reset and D3Hot */</div><div class='add'>+	if (gsc_fw_is_loaded(gt)) {</div><div class='add'>+		xe_uc_fw_change_status(&amp;gsc-&gt;fw, XE_UC_FIRMWARE_TRANSFERRED);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue_work(gsc-&gt;wq, &amp;gsc-&gt;work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gsc_wait_for_worker_completion(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	if (xe_uc_fw_is_loadable(&amp;gsc-&gt;fw) &amp;&amp; gsc-&gt;wq)</div><div class='add'>+		flush_work(&amp;gsc-&gt;work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * wa_14015076503: if the GSC FW is loaded, we need to alert it before doing a</div><div class='add'>+ * GSC engine reset by writing a notification bit in the GS1 register and then</div><div class='add'>+ * triggering an interrupt to GSC; from the interrupt it will take up to 200ms</div><div class='add'>+ * for the FW to get prepare for the reset, so we need to wait for that amount</div><div class='add'>+ * of time.</div><div class='add'>+ * After the reset is complete we need to then clear the GS1 register.</div><div class='add'>+ */</div><div class='add'>+void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)</div><div class='add'>+{</div><div class='add'>+	u32 gs1_set = prep ? HECI_H_GS1_ER_PREP : 0;</div><div class='add'>+	u32 gs1_clr = prep ? 0 : HECI_H_GS1_ER_PREP;</div><div class='add'>+</div><div class='add'>+	/* WA only applies if the GSC is loaded */</div><div class='add'>+	if (!XE_WA(gt, 14015076503) || !gsc_fw_is_loaded(gt))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_mmio_rmw32(gt, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);</div><div class='add'>+</div><div class='add'>+	if (prep) {</div><div class='add'>+		/* make sure the reset bit is clear when writing the CSR reg */</div><div class='add'>+		xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE),</div><div class='add'>+			      HECI_H_CSR_RST, HECI_H_CSR_IG);</div><div class='add'>+		msleep(200);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gsc.h b/drivers/gpu/drm/xe/xe_gsc.h<br/>new file mode 100644<br/>index 000000000000..bc1ef7f31ea2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc.h</a></div><div class='hunk'>@@ -0,0 +1,20 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GSC_H_</div><div class='add'>+#define _XE_GSC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gsc_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+int xe_gsc_init(struct xe_gsc *gsc);</div><div class='add'>+int xe_gsc_init_post_hwconfig(struct xe_gsc *gsc);</div><div class='add'>+void xe_gsc_wait_for_worker_completion(struct xe_gsc *gsc);</div><div class='add'>+void xe_gsc_load_start(struct xe_gsc *gsc);</div><div class='add'>+</div><div class='add'>+void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gsc_submit.c b/drivers/gpu/drm/xe/xe_gsc_submit.c<br/>new file mode 100644<br/>index 000000000000..8c5381e5913f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gsc_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_submit.c</a></div><div class='hunk'>@@ -0,0 +1,184 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gsc_submit.h"</div><div class='add'>+</div><div class='add'>+#include "abi/gsc_command_header_abi.h"</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "instructions/xe_gsc_commands.h"</div><div class='add'>+#include "regs/xe_gsc_regs.h"</div><div class='add'>+</div><div class='add'>+#define GSC_HDR_SIZE (sizeof(struct intel_gsc_mtl_header)) /* shorthand define */</div><div class='add'>+</div><div class='add'>+#define mtl_gsc_header_wr(xe_, map_, offset_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(xe_, map_, offset_, struct intel_gsc_mtl_header, field_, val_)</div><div class='add'>+</div><div class='add'>+#define mtl_gsc_header_rd(xe_, map_, offset_, field_) \</div><div class='add'>+	xe_map_rd_field(xe_, map_, offset_, struct intel_gsc_mtl_header, field_)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GSC FW allows us to define the host_session_handle as we see fit, as long</div><div class='add'>+ * as we use unique identifier for each user, with handle 0 being reserved for</div><div class='add'>+ * kernel usage.</div><div class='add'>+ * To be able to differentiate which client subsystem owns the given session, we</div><div class='add'>+ * include the client id in the top 8 bits of the handle.</div><div class='add'>+ */</div><div class='add'>+#define HOST_SESSION_CLIENT_MASK GENMASK_ULL(63, 56)</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+gsc_to_gt(struct xe_gsc *gsc)</div><div class='add'>+{</div><div class='add'>+	return container_of(gsc, struct xe_gt, uc.gsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gsc_emit_header - write the MTL GSC header in memory</div><div class='add'>+ * @xe: the Xe device</div><div class='add'>+ * @map: the iosys map to write to</div><div class='add'>+ * @offset: offset from the start of the map at which to write the header</div><div class='add'>+ * @heci_client_id: client id identifying the type of command (see abi for values)</div><div class='add'>+ * @host_session_id: host session ID of the caller</div><div class='add'>+ * @payload_size: size of the payload that follows the header</div><div class='add'>+ *</div><div class='add'>+ * Returns: offset memory location following the header</div><div class='add'>+ */</div><div class='add'>+u32 xe_gsc_emit_header(struct xe_device *xe, struct iosys_map *map, u32 offset,</div><div class='add'>+		       u8 heci_client_id, u64 host_session_id, u32 payload_size)</div><div class='add'>+{</div><div class='add'>+	xe_assert(xe, !(host_session_id &amp; HOST_SESSION_CLIENT_MASK));</div><div class='add'>+</div><div class='add'>+	if (host_session_id)</div><div class='add'>+		host_session_id |= FIELD_PREP(HOST_SESSION_CLIENT_MASK, heci_client_id);</div><div class='add'>+</div><div class='add'>+	xe_map_memset(xe, map, offset, 0, GSC_HDR_SIZE);</div><div class='add'>+</div><div class='add'>+	mtl_gsc_header_wr(xe, map, offset, validity_marker, GSC_HECI_VALIDITY_MARKER);</div><div class='add'>+	mtl_gsc_header_wr(xe, map, offset, heci_client_id, heci_client_id);</div><div class='add'>+	mtl_gsc_header_wr(xe, map, offset, host_session_handle, host_session_id);</div><div class='add'>+	mtl_gsc_header_wr(xe, map, offset, header_version, MTL_GSC_HEADER_VERSION);</div><div class='add'>+	mtl_gsc_header_wr(xe, map, offset, message_size, payload_size + GSC_HDR_SIZE);</div><div class='add'>+</div><div class='add'>+	return offset + GSC_HDR_SIZE;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gsc_check_and_update_pending - check the pending bit and update the input</div><div class='add'>+ * header with the retry handle from the output header</div><div class='add'>+ * @xe: the Xe device</div><div class='add'>+ * @in: the iosys map containing the input buffer</div><div class='add'>+ * @offset_in: offset within the iosys at which the input buffer is located</div><div class='add'>+ * @out: the iosys map containing the output buffer</div><div class='add'>+ * @offset_out: offset within the iosys at which the output buffer is located</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if the pending bit was set, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool xe_gsc_check_and_update_pending(struct xe_device *xe,</div><div class='add'>+				     struct iosys_map *in, u32 offset_in,</div><div class='add'>+				     struct iosys_map *out, u32 offset_out)</div><div class='add'>+{</div><div class='add'>+	if (mtl_gsc_header_rd(xe, out, offset_out, flags) &amp; GSC_OUTFLAG_MSG_PENDING) {</div><div class='add'>+		u64 handle = mtl_gsc_header_rd(xe, out, offset_out, gsc_message_handle);</div><div class='add'>+</div><div class='add'>+		mtl_gsc_header_wr(xe, in, offset_in, gsc_message_handle, handle);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gsc_read_out_header - reads and validates the output header and returns</div><div class='add'>+ * the offset of the reply following the header</div><div class='add'>+ * @xe: the Xe device</div><div class='add'>+ * @map: the iosys map containing the output buffer</div><div class='add'>+ * @offset: offset within the iosys at which the output buffer is located</div><div class='add'>+ * @min_payload_size: minimum size of the message excluding the gsc header</div><div class='add'>+ * @payload_offset: optional pointer to be set to the payload offset</div><div class='add'>+ *</div><div class='add'>+ * Returns: -errno value on failure, 0 otherwise</div><div class='add'>+ */</div><div class='add'>+int xe_gsc_read_out_header(struct xe_device *xe,</div><div class='add'>+			   struct iosys_map *map, u32 offset,</div><div class='add'>+			   u32 min_payload_size,</div><div class='add'>+			   u32 *payload_offset)</div><div class='add'>+{</div><div class='add'>+	u32 marker = mtl_gsc_header_rd(xe, map, offset, validity_marker);</div><div class='add'>+	u32 size = mtl_gsc_header_rd(xe, map, offset, message_size);</div><div class='add'>+	u32 payload_size = size - GSC_HDR_SIZE;</div><div class='add'>+</div><div class='add'>+	if (marker != GSC_HECI_VALIDITY_MARKER)</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	if (size &lt; GSC_HDR_SIZE || payload_size &lt; min_payload_size)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	if (payload_offset)</div><div class='add'>+		*payload_offset = offset + GSC_HDR_SIZE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gsc_pkt_submit_kernel - submit a kernel heci pkt to the GSC</div><div class='add'>+ * @gsc: the GSC uC</div><div class='add'>+ * @addr_in: GGTT address of the message to send to the GSC</div><div class='add'>+ * @size_in: size of the message to send to the GSC</div><div class='add'>+ * @addr_out: GGTT address for the GSC to write the reply to</div><div class='add'>+ * @size_out: size of the memory reserved for the reply</div><div class='add'>+ */</div><div class='add'>+int xe_gsc_pkt_submit_kernel(struct xe_gsc *gsc, u64 addr_in, u32 size_in,</div><div class='add'>+			     u64 addr_out, u32 size_out)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gsc_to_gt(gsc);</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	long timeout;</div><div class='add'>+</div><div class='add'>+	if (size_in &lt; GSC_HDR_SIZE)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	if (size_out &lt; GSC_HDR_SIZE)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	bb = xe_bb_new(gt, 8, false);</div><div class='add'>+	if (IS_ERR(bb))</div><div class='add'>+		return PTR_ERR(bb);</div><div class='add'>+</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = GSC_HECI_CMD_PKT;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = lower_32_bits(addr_in);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = upper_32_bits(addr_in);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = size_in;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = lower_32_bits(addr_out);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = upper_32_bits(addr_out);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = size_out;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = 0;</div><div class='add'>+</div><div class='add'>+	job = xe_bb_create_job(gsc-&gt;q, bb);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+		return PTR_ERR(job);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	timeout = dma_fence_wait_timeout(fence, false, HZ);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+	if (timeout &lt; 0)</div><div class='add'>+		return timeout;</div><div class='add'>+	else if (!timeout)</div><div class='add'>+		return -ETIME;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gsc_submit.h b/drivers/gpu/drm/xe/xe_gsc_submit.h<br/>new file mode 100644<br/>index 000000000000..0801da5d446a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gsc_submit.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_submit.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GSC_SUBMIT_H_</div><div class='add'>+#define _XE_GSC_SUBMIT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct iosys_map;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_gsc;</div><div class='add'>+</div><div class='add'>+u32 xe_gsc_emit_header(struct xe_device *xe, struct iosys_map *map, u32 offset,</div><div class='add'>+		       u8 heci_client_id, u64 host_session_id, u32 payload_size);</div><div class='add'>+</div><div class='add'>+bool xe_gsc_check_and_update_pending(struct xe_device *xe,</div><div class='add'>+				     struct iosys_map *in, u32 offset_in,</div><div class='add'>+				     struct iosys_map *out, u32 offset_out);</div><div class='add'>+</div><div class='add'>+int xe_gsc_read_out_header(struct xe_device *xe,</div><div class='add'>+			   struct iosys_map *map, u32 offset,</div><div class='add'>+			   u32 min_payload_size,</div><div class='add'>+			   u32 *payload_offset);</div><div class='add'>+</div><div class='add'>+int xe_gsc_pkt_submit_kernel(struct xe_gsc *gsc, u64 addr_in, u32 size_in,</div><div class='add'>+			     u64 addr_out, u32 size_out);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gsc_types.h b/drivers/gpu/drm/xe/xe_gsc_types.h<br/>new file mode 100644<br/>index 000000000000..57fefd66a7ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gsc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gsc_types.h</a></div><div class='hunk'>@@ -0,0 +1,39 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GSC_TYPES_H_</div><div class='add'>+#define _XE_GSC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_uc_fw_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_gsc - GSC</div><div class='add'>+ */</div><div class='add'>+struct xe_gsc {</div><div class='add'>+	/** @fw: Generic uC firmware management */</div><div class='add'>+	struct xe_uc_fw fw;</div><div class='add'>+</div><div class='add'>+	/** @security_version: SVN found in the fetched blob */</div><div class='add'>+	u32 security_version;</div><div class='add'>+</div><div class='add'>+	/** @private: Private data for use by the GSC FW */</div><div class='add'>+	struct xe_bo *private;</div><div class='add'>+</div><div class='add'>+	/** @q: Default queue used for submissions to GSC FW */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	/** @wq: workqueue to handle jobs for delayed load and proxy handling */</div><div class='add'>+	struct workqueue_struct *wq;</div><div class='add'>+</div><div class='add'>+	/** @work: delayed load and proxy handling work */</div><div class='add'>+	struct work_struct work;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c<br/>new file mode 100644<br/>index 000000000000..3af2adec1295<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt.c</a></div><div class='hunk'>@@ -0,0 +1,778 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/minmax.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_gfxpipe_commands.h"</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_execlist.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gsc.h"</div><div class='add'>+#include "xe_gt_ccs_mode.h"</div><div class='add'>+#include "xe_gt_clock.h"</div><div class='add'>+#include "xe_gt_freq.h"</div><div class='add'>+#include "xe_gt_idle.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_gt_pagefault.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+#include "xe_guc_exec_queue_types.h"</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_hw_engine_class_sysfs.h"</div><div class='add'>+#include "xe_irq.h"</div><div class='add'>+#include "xe_lmtt.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_pat.h"</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+#include "xe_ring_ops.h"</div><div class='add'>+#include "xe_sa.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_sriov.h"</div><div class='add'>+#include "xe_tuning.h"</div><div class='add'>+#include "xe_uc.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+#include "xe_wopcm.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt *xe_gt_alloc(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+</div><div class='add'>+	gt = drmm_kzalloc(&amp;tile_to_xe(tile)-&gt;drm, sizeof(*gt), GFP_KERNEL);</div><div class='add'>+	if (!gt)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	gt-&gt;tile = tile;</div><div class='add'>+	gt-&gt;ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0);</div><div class='add'>+</div><div class='add'>+	return gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_sanitize(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not</div><div class='add'>+	 * reload</div><div class='add'>+	 */</div><div class='add'>+	gt-&gt;uc.guc.submission_state.enabled = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gt_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = arg;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	destroy_workqueue(gt-&gt;ordered_wq);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; XE_ENGINE_CLASS_MAX; ++i)</div><div class='add'>+		xe_hw_fence_irq_finish(&amp;gt-&gt;fence_irq[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gt_reset_worker(struct work_struct *w);</div><div class='add'>+</div><div class='add'>+static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	long timeout;</div><div class='add'>+</div><div class='add'>+	bb = xe_bb_new(gt, 4, false);</div><div class='add'>+	if (IS_ERR(bb))</div><div class='add'>+		return PTR_ERR(bb);</div><div class='add'>+</div><div class='add'>+	job = xe_bb_create_job(q, bb);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+		return PTR_ERR(job);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	timeout = dma_fence_wait_timeout(fence, false, HZ);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+	if (timeout &lt; 0)</div><div class='add'>+		return timeout;</div><div class='add'>+	else if (!timeout)</div><div class='add'>+		return -ETIME;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Convert back from encoded value to type-safe, only to be used when reg.mcr</div><div class='add'>+ * is true</div><div class='add'>+ */</div><div class='add'>+static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	return (const struct xe_reg_mcr){.__reg.raw = reg.raw };</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr *sr = &amp;q-&gt;hwe-&gt;reg_lrc;</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	unsigned long idx;</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	long timeout;</div><div class='add'>+	int count = 0;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;hwe-&gt;class == XE_ENGINE_CLASS_RENDER)</div><div class='add'>+		/* Big enough to emit all of the context's 3DSTATE */</div><div class='add'>+		bb = xe_bb_new(gt, xe_lrc_size(gt_to_xe(gt), q-&gt;hwe-&gt;class), false);</div><div class='add'>+	else</div><div class='add'>+		/* Just pick a large BB size */</div><div class='add'>+		bb = xe_bb_new(gt, SZ_4K, false);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(bb))</div><div class='add'>+		return PTR_ERR(bb);</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;sr-&gt;xa, idx, entry)</div><div class='add'>+		++count;</div><div class='add'>+</div><div class='add'>+	if (count) {</div><div class='add'>+		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr-&gt;name);</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);</div><div class='add'>+</div><div class='add'>+		xa_for_each(&amp;sr-&gt;xa, idx, entry) {</div><div class='add'>+			struct xe_reg reg = entry-&gt;reg;</div><div class='add'>+			struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg);</div><div class='add'>+			u32 val;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Skip reading the register if it's not really needed</div><div class='add'>+			 */</div><div class='add'>+			if (reg.masked)</div><div class='add'>+				val = entry-&gt;clr_bits &lt;&lt; 16;</div><div class='add'>+			else if (entry-&gt;clr_bits + 1)</div><div class='add'>+				val = (reg.mcr ?</div><div class='add'>+				       xe_gt_mcr_unicast_read_any(gt, reg_mcr) :</div><div class='add'>+				       xe_mmio_read32(gt, reg)) &amp; (~entry-&gt;clr_bits);</div><div class='add'>+			else</div><div class='add'>+				val = 0;</div><div class='add'>+</div><div class='add'>+			val |= entry-&gt;set_bits;</div><div class='add'>+</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = reg.addr;</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = val;</div><div class='add'>+			xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_lrc_emit_hwe_state_instructions(q, bb);</div><div class='add'>+</div><div class='add'>+	job = xe_bb_create_job(q, bb);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+		return PTR_ERR(job);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	timeout = dma_fence_wait_timeout(fence, false, HZ);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+	if (timeout &lt; 0)</div><div class='add'>+		return timeout;</div><div class='add'>+	else if (!timeout)</div><div class='add'>+		return -ETIME;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_record_default_lrcs(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		struct xe_exec_queue *q, *nop_q;</div><div class='add'>+		void *default_lrc;</div><div class='add'>+</div><div class='add'>+		if (gt-&gt;default_lrc[hwe-&gt;class])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		xe_reg_sr_init(&amp;hwe-&gt;reg_lrc, hwe-&gt;name, xe);</div><div class='add'>+		xe_wa_process_lrc(hwe);</div><div class='add'>+		xe_hw_engine_setup_default_lrc_state(hwe);</div><div class='add'>+		xe_tuning_process_lrc(hwe);</div><div class='add'>+</div><div class='add'>+		default_lrc = drmm_kzalloc(&amp;xe-&gt;drm,</div><div class='add'>+					   xe_lrc_size(xe, hwe-&gt;class),</div><div class='add'>+					   GFP_KERNEL);</div><div class='add'>+		if (!default_lrc)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		q = xe_exec_queue_create(xe, NULL, BIT(hwe-&gt;logical_instance), 1,</div><div class='add'>+					 hwe, EXEC_QUEUE_FLAG_KERNEL);</div><div class='add'>+		if (IS_ERR(q)) {</div><div class='add'>+			err = PTR_ERR(q);</div><div class='add'>+			xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n",</div><div class='add'>+				  hwe-&gt;name, q);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Prime golden LRC with known good state */</div><div class='add'>+		err = emit_wa_job(gt, q);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n",</div><div class='add'>+				  hwe-&gt;name, ERR_PTR(err), q-&gt;guc-&gt;id);</div><div class='add'>+			goto put_exec_queue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe-&gt;logical_instance),</div><div class='add'>+					     1, hwe, EXEC_QUEUE_FLAG_KERNEL);</div><div class='add'>+		if (IS_ERR(nop_q)) {</div><div class='add'>+			err = PTR_ERR(nop_q);</div><div class='add'>+			xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n",</div><div class='add'>+				  hwe-&gt;name, nop_q);</div><div class='add'>+			goto put_exec_queue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Switch to different LRC */</div><div class='add'>+		err = emit_nop_job(gt, nop_q);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n",</div><div class='add'>+				  hwe-&gt;name, ERR_PTR(err), nop_q-&gt;guc-&gt;id);</div><div class='add'>+			goto put_nop_q;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Reload golden LRC to record the effect of any indirect W/A */</div><div class='add'>+		err = emit_nop_job(gt, q);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",</div><div class='add'>+				  hwe-&gt;name, ERR_PTR(err), q-&gt;guc-&gt;id);</div><div class='add'>+			goto put_nop_q;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_map_memcpy_from(xe, default_lrc,</div><div class='add'>+				   &amp;q-&gt;lrc[0].bo-&gt;vmap,</div><div class='add'>+				   xe_lrc_pphwsp_offset(&amp;q-&gt;lrc[0]),</div><div class='add'>+				   xe_lrc_size(xe, hwe-&gt;class));</div><div class='add'>+</div><div class='add'>+		gt-&gt;default_lrc[hwe-&gt;class] = default_lrc;</div><div class='add'>+put_nop_q:</div><div class='add'>+		xe_exec_queue_put(nop_q);</div><div class='add'>+put_exec_queue:</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_init_early(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_gt_topology_init(gt);</div><div class='add'>+	xe_gt_mcr_init(gt);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_init(&amp;gt-&gt;reg_sr, "GT", gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	err = xe_wa_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_wa_process_gt(gt);</div><div class='add'>+	xe_wa_process_oob(gt);</div><div class='add'>+	xe_tuning_process_gt(gt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dump_pat_on_error(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p;</div><div class='add'>+	char prefix[32];</div><div class='add'>+</div><div class='add'>+	snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt-&gt;info.id);</div><div class='add'>+	p = drm_debug_printer(prefix);</div><div class='add'>+</div><div class='add'>+	xe_pat_dump(gt, &amp;p);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gt_fw_domain_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err, i;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_hw_fence_irq;</div><div class='add'>+</div><div class='add'>+	xe_pat_init(gt);</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_is_media_type(gt)) {</div><div class='add'>+		err = xe_ggtt_init(gt_to_tile(gt)-&gt;mem.ggtt);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_force_wake;</div><div class='add'>+		if (IS_SRIOV_PF(gt_to_xe(gt)))</div><div class='add'>+			xe_lmtt_init(&amp;gt_to_tile(gt)-&gt;sriov.pf.lmtt);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_uc_init(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	/* Raise GT freq to speed up HuC/GuC load */</div><div class='add'>+	xe_guc_pc_init_early(&amp;gt-&gt;uc.guc.pc);</div><div class='add'>+</div><div class='add'>+	err = xe_uc_init_hwconfig(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	xe_gt_idle_sysfs_init(&amp;gt-&gt;gtidle);</div><div class='add'>+</div><div class='add'>+	/* XXX: Fake that we pull the engine mask from hwconfig blob */</div><div class='add'>+	gt-&gt;info.engine_mask = gt-&gt;info.__engine_mask;</div><div class='add'>+</div><div class='add'>+	/* Enable per hw engine IRQs */</div><div class='add'>+	xe_irq_enable_hwe(gt);</div><div class='add'>+</div><div class='add'>+	/* Rerun MCR init as we now have hw engine list */</div><div class='add'>+	xe_gt_mcr_init(gt);</div><div class='add'>+</div><div class='add'>+	err = xe_hw_engines_init_early(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	err = xe_hw_engine_class_sysfs_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;gt_to_xe(gt)-&gt;drm,</div><div class='add'>+			 "failed to register engines sysfs directory, err: %d\n",</div><div class='add'>+			 err);</div><div class='add'>+</div><div class='add'>+	/* Initialize CCS mode sysfs after early initialization of HW engines */</div><div class='add'>+	xe_gt_ccs_mode_sysfs_init(gt);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	XE_WARN_ON(err);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	dump_pat_on_error(gt);</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_hw_fence_irq:</div><div class='add'>+	for (i = 0; i &lt; XE_ENGINE_CLASS_MAX; ++i)</div><div class='add'>+		xe_hw_fence_irq_finish(&amp;gt-&gt;fence_irq[i]);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int all_fw_domain_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err, i;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_hw_fence_irq;</div><div class='add'>+</div><div class='add'>+	xe_gt_mcr_set_implicit_defaults(gt);</div><div class='add'>+	xe_reg_sr_apply_mmio(&amp;gt-&gt;reg_sr, gt);</div><div class='add'>+</div><div class='add'>+	err = xe_gt_clock_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	xe_mocs_init(gt);</div><div class='add'>+	err = xe_execlist_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	err = xe_hw_engines_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	err = xe_uc_init_post_hwconfig(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_is_media_type(gt)) {</div><div class='add'>+		/*</div><div class='add'>+		 * USM has its only SA pool to non-block behind user operations</div><div class='add'>+		 */</div><div class='add'>+		if (gt_to_xe(gt)-&gt;info.has_usm) {</div><div class='add'>+			gt-&gt;usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), SZ_1M, 16);</div><div class='add'>+			if (IS_ERR(gt-&gt;usm.bb_pool)) {</div><div class='add'>+				err = PTR_ERR(gt-&gt;usm.bb_pool);</div><div class='add'>+				goto err_force_wake;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_is_media_type(gt)) {</div><div class='add'>+		struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+</div><div class='add'>+		tile-&gt;migrate = xe_migrate_init(tile);</div><div class='add'>+		if (IS_ERR(tile-&gt;migrate)) {</div><div class='add'>+			err = PTR_ERR(tile-&gt;migrate);</div><div class='add'>+			goto err_force_wake;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_uc_init_hw(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	/* Configure default CCS mode of 1 engine with all resources */</div><div class='add'>+	if (xe_gt_ccs_mode_enabled(gt)) {</div><div class='add'>+		gt-&gt;ccs_mode = 1;</div><div class='add'>+		xe_gt_apply_ccs_mode(gt);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_PF(gt_to_xe(gt)) &amp;&amp; !xe_gt_is_media_type(gt))</div><div class='add'>+		xe_lmtt_init_hw(&amp;gt_to_tile(gt)-&gt;sriov.pf.lmtt);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	XE_WARN_ON(err);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+err_hw_fence_irq:</div><div class='add'>+	for (i = 0; i &lt; XE_ENGINE_CLASS_MAX; ++i)</div><div class='add'>+		xe_hw_fence_irq_finish(&amp;gt-&gt;fence_irq[i]);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;gt-&gt;reset.worker, gt_reset_worker);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; XE_ENGINE_CLASS_MAX; ++i) {</div><div class='add'>+		gt-&gt;ring_ops[i] = xe_ring_ops_get(gt, i);</div><div class='add'>+		xe_hw_fence_irq_init(&amp;gt-&gt;fence_irq[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_gt_tlb_invalidation_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_gt_pagefault_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_mocs_init_early(gt);</div><div class='add'>+</div><div class='add'>+	xe_gt_sysfs_init(gt);</div><div class='add'>+</div><div class='add'>+	err = gt_fw_domain_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_gt_freq_init(gt);</div><div class='add'>+</div><div class='add'>+	xe_force_wake_init_engines(gt, gt_to_fw(gt));</div><div class='add'>+</div><div class='add'>+	err = all_fw_domain_init(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;gt_to_xe(gt)-&gt;drm, gt_fini, gt);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int do_gt_reset(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_gsc_wa_14015076503(gt, true);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, GDRST, GRDOM_FULL);</div><div class='add'>+	err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false);</div><div class='add'>+	if (err)</div><div class='add'>+		xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n",</div><div class='add'>+			  ERR_PTR(err));</div><div class='add'>+</div><div class='add'>+	xe_gsc_wa_14015076503(gt, false);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int do_gt_restart(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_pat_init(gt);</div><div class='add'>+</div><div class='add'>+	xe_gt_mcr_set_implicit_defaults(gt);</div><div class='add'>+	xe_reg_sr_apply_mmio(&amp;gt-&gt;reg_sr, gt);</div><div class='add'>+</div><div class='add'>+	err = xe_wopcm_init(&amp;gt-&gt;uc.wopcm);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xe_hw_engine_enable_ring(hwe);</div><div class='add'>+</div><div class='add'>+	err = xe_uc_sanitize_reset(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_uc_init_hw(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (IS_SRIOV_PF(gt_to_xe(gt)) &amp;&amp; !xe_gt_is_media_type(gt))</div><div class='add'>+		xe_lmtt_init_hw(&amp;gt_to_tile(gt)-&gt;sriov.pf.lmtt);</div><div class='add'>+</div><div class='add'>+	xe_mocs_init(gt);</div><div class='add'>+	err = xe_uc_start(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		xe_reg_sr_apply_mmio(&amp;hwe-&gt;reg_sr, gt);</div><div class='add'>+		xe_reg_sr_apply_whitelist(hwe);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get CCS mode in sync between sw/hw */</div><div class='add'>+	xe_gt_apply_ccs_mode(gt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gt_reset(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* We only support GT resets with GuC submission */</div><div class='add'>+	if (!xe_device_uc_enabled(gt_to_xe(gt)))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	xe_gt_info(gt, "reset started\n");</div><div class='add'>+</div><div class='add'>+	if (xe_fault_inject_gt_reset()) {</div><div class='add'>+		err = -ECANCELED;</div><div class='add'>+		goto err_fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_sanitize(gt);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_msg;</div><div class='add'>+</div><div class='add'>+	xe_uc_gucrc_disable(&amp;gt-&gt;uc);</div><div class='add'>+	xe_uc_stop_prepare(&amp;gt-&gt;uc);</div><div class='add'>+	xe_gt_pagefault_reset(gt);</div><div class='add'>+</div><div class='add'>+	err = xe_uc_stop(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	err = do_gt_reset(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	xe_gt_tlb_invalidation_reset(gt);</div><div class='add'>+</div><div class='add'>+	err = do_gt_restart(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	XE_WARN_ON(err);</div><div class='add'>+</div><div class='add'>+	xe_gt_info(gt, "reset done\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+err_msg:</div><div class='add'>+	XE_WARN_ON(xe_uc_start(&amp;gt-&gt;uc));</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+err_fail:</div><div class='add'>+	xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err));</div><div class='add'>+</div><div class='add'>+	gt_to_xe(gt)-&gt;needs_flr_on_fini = true;</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gt_reset_worker(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker);</div><div class='add'>+</div><div class='add'>+	gt_reset(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_reset_async(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	xe_gt_info(gt, "trying reset\n");</div><div class='add'>+</div><div class='add'>+	/* Don't do a reset while one is already in flight */</div><div class='add'>+	if (!xe_fault_inject_gt_reset() &amp;&amp; xe_uc_reset_prepare(&amp;gt-&gt;uc))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_gt_info(gt, "reset queued\n");</div><div class='add'>+	queue_work(gt-&gt;ordered_wq, &amp;gt-&gt;reset.worker);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_suspend_prepare(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+</div><div class='add'>+	xe_uc_stop_prepare(&amp;gt-&gt;uc);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_suspend(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_gt_sanitize(gt);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_msg;</div><div class='add'>+</div><div class='add'>+	err = xe_uc_suspend(&amp;gt-&gt;uc);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	xe_gt_info(gt, "suspended\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+err_msg:</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_resume(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_msg;</div><div class='add'>+</div><div class='add'>+	err = do_gt_restart(gt);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	xe_gt_info(gt, "resumed\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+err_msg:</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,</div><div class='add'>+				     enum xe_engine_class class,</div><div class='add'>+				     u16 instance, bool logical)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		if (hwe-&gt;class == class &amp;&amp;</div><div class='add'>+		    ((!logical &amp;&amp; hwe-&gt;instance == instance) ||</div><div class='add'>+		    (logical &amp;&amp; hwe-&gt;logical_instance == instance)))</div><div class='add'>+			return hwe;</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt,</div><div class='add'>+							 enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		switch (class) {</div><div class='add'>+		case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+		case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+			if (hwe-&gt;class == XE_ENGINE_CLASS_RENDER ||</div><div class='add'>+			    hwe-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+				return hwe;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			if (hwe-&gt;class == class)</div><div class='add'>+				return hwe;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h<br/>new file mode 100644<br/>index 000000000000..4486e083f5ef<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt.h</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_H_</div><div class='add'>+#define _XE_GT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_util.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+</div><div class='add'>+#define for_each_hw_engine(hwe__, gt__, id__) \</div><div class='add'>+	for ((id__) = 0; (id__) &lt; ARRAY_SIZE((gt__)-&gt;hw_engines); (id__)++) \</div><div class='add'>+		for_each_if(((hwe__) = (gt__)-&gt;hw_engines + (id__)) &amp;&amp; \</div><div class='add'>+			  xe_hw_engine_is_valid((hwe__)))</div><div class='add'>+</div><div class='add'>+#define CCS_MASK(gt) (((gt)-&gt;info.engine_mask &amp; XE_HW_ENGINE_CCS_MASK) &gt;&gt; XE_HW_ENGINE_CCS0)</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_FAULT_INJECTION</div><div class='add'>+#include &lt;linux/fault-inject.h&gt; /* XXX: fault-inject.h is broken */</div><div class='add'>+extern struct fault_attr gt_reset_failure;</div><div class='add'>+static inline bool xe_fault_inject_gt_reset(void)</div><div class='add'>+{</div><div class='add'>+	return should_fail(&amp;gt_reset_failure, 1);</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+static inline bool xe_fault_inject_gt_reset(void)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+struct xe_gt *xe_gt_alloc(struct xe_tile *tile);</div><div class='add'>+int xe_gt_init_early(struct xe_gt *gt);</div><div class='add'>+int xe_gt_init(struct xe_gt *gt);</div><div class='add'>+int xe_gt_record_default_lrcs(struct xe_gt *gt);</div><div class='add'>+void xe_gt_suspend_prepare(struct xe_gt *gt);</div><div class='add'>+int xe_gt_suspend(struct xe_gt *gt);</div><div class='add'>+int xe_gt_resume(struct xe_gt *gt);</div><div class='add'>+void xe_gt_reset_async(struct xe_gt *gt);</div><div class='add'>+void xe_gt_sanitize(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_any_hw_engine_by_reset_domain - scan the list of engines and return the</div><div class='add'>+ * first that matches the same reset domain as @class</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @class: hw engine class to lookup</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_engine *</div><div class='add'>+xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, enum xe_engine_class class);</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt,</div><div class='add'>+				     enum xe_engine_class class,</div><div class='add'>+				     u16 instance,</div><div class='add'>+				     bool logical);</div><div class='add'>+</div><div class='add'>+static inline bool xe_gt_is_media_type(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	return gt-&gt;info.type == XE_GT_TYPE_MEDIA;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_gt_is_usm_hwe(struct xe_gt *gt, struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	return xe-&gt;info.has_usm &amp;&amp; hwe-&gt;class == XE_ENGINE_CLASS_COPY &amp;&amp;</div><div class='add'>+		hwe-&gt;instance == gt-&gt;usm.reserved_bcs_instance;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c<br/>new file mode 100644<br/>index 000000000000..529fc286cd06<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_ccs_mode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_ccs_mode.c</a></div><div class='hunk'>@@ -0,0 +1,191 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_ccs_mode.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)</div><div class='add'>+{</div><div class='add'>+	u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */</div><div class='add'>+	int num_slices = hweight32(CCS_MASK(gt));</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int width, cslice = 0;</div><div class='add'>+	u32 config = 0;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, xe_gt_ccs_mode_enabled(gt));</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, num_engines &amp;&amp; num_engines &lt;= num_slices);</div><div class='add'>+	xe_assert(xe, !(num_slices % num_engines));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Loop over all available slices and assign each a user engine.</div><div class='add'>+	 * For example, if there are four compute slices available, the</div><div class='add'>+	 * assignment of compute slices to compute engines would be,</div><div class='add'>+	 *</div><div class='add'>+	 * With 1 engine (ccs0):</div><div class='add'>+	 *   slice 0, 1, 2, 3: ccs0</div><div class='add'>+	 *</div><div class='add'>+	 * With 2 engines (ccs0, ccs1):</div><div class='add'>+	 *   slice 0, 2: ccs0</div><div class='add'>+	 *   slice 1, 3: ccs1</div><div class='add'>+	 *</div><div class='add'>+	 * With 4 engines (ccs0, ccs1, ccs2, ccs3):</div><div class='add'>+	 *   slice 0: ccs0</div><div class='add'>+	 *   slice 1: ccs1</div><div class='add'>+	 *   slice 2: ccs2</div><div class='add'>+	 *   slice 3: ccs3</div><div class='add'>+	 */</div><div class='add'>+	for (width = num_slices / num_engines; width; width--) {</div><div class='add'>+		struct xe_hw_engine *hwe;</div><div class='add'>+		enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+		for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+			if (hwe-&gt;class != XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (hwe-&gt;logical_instance &gt;= num_engines)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			config |= BIT(hwe-&gt;instance) &lt;&lt; XE_HW_ENGINE_CCS0;</div><div class='add'>+</div><div class='add'>+			/* If a slice is fused off, leave disabled */</div><div class='add'>+			while ((CCS_MASK(gt) &amp; BIT(cslice)) == 0)</div><div class='add'>+				cslice++;</div><div class='add'>+</div><div class='add'>+			mode &amp;= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK);</div><div class='add'>+			mode |= CCS_MODE_CSLICE(cslice, hwe-&gt;instance);</div><div class='add'>+			cslice++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, CCS_MODE, mode);</div><div class='add'>+</div><div class='add'>+	xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",</div><div class='add'>+		   mode, config, num_engines, num_slices);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_apply_ccs_mode(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (!gt-&gt;ccs_mode)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	__xe_gt_apply_ccs_mode(gt, gt-&gt;ccs_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+num_cslices_show(struct device *kdev,</div><div class='add'>+		 struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = kobj_to_gt(&amp;kdev-&gt;kobj);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n", hweight32(CCS_MASK(gt)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR_RO(num_cslices);</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+ccs_mode_show(struct device *kdev,</div><div class='add'>+	      struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = kobj_to_gt(&amp;kdev-&gt;kobj);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n", gt-&gt;ccs_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+ccs_mode_store(struct device *kdev, struct device_attribute *attr,</div><div class='add'>+	       const char *buff, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = kobj_to_gt(&amp;kdev-&gt;kobj);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 num_engines, num_slices;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32(buff, 0, &amp;num_engines);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Ensure number of engines specified is valid and there is an</div><div class='add'>+	 * exact multiple of engines for slices.</div><div class='add'>+	 */</div><div class='add'>+	num_slices = hweight32(CCS_MASK(gt));</div><div class='add'>+	if (!num_engines || num_engines &gt; num_slices || num_slices % num_engines) {</div><div class='add'>+		xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n",</div><div class='add'>+			  num_engines, num_slices);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* CCS mode can only be updated when there are no drm clients */</div><div class='add'>+	spin_lock(&amp;xe-&gt;clients.lock);</div><div class='add'>+	if (xe-&gt;clients.count) {</div><div class='add'>+		spin_unlock(&amp;xe-&gt;clients.lock);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;ccs_mode != num_engines) {</div><div class='add'>+		xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);</div><div class='add'>+		gt-&gt;ccs_mode = num_engines;</div><div class='add'>+		xe_gt_reset_async(gt);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;xe-&gt;clients.lock);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR_RW(ccs_mode);</div><div class='add'>+</div><div class='add'>+static const struct attribute *gt_ccs_mode_attrs[] = {</div><div class='add'>+	&amp;dev_attr_ccs_mode.attr,</div><div class='add'>+	&amp;dev_attr_num_cslices.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe_gt_ccs_mode_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_files(gt-&gt;sysfs, gt_ccs_mode_attrs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_ccs_mode_sysfs_init - Initialize CCS mode sysfs interfaces</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ *</div><div class='add'>+ * Through a per-gt 'ccs_mode' sysfs interface, the user can enable a fixed</div><div class='add'>+ * number of compute hardware engines to which the available compute slices</div><div class='add'>+ * are to be allocated. This user configuration change triggers a gt reset</div><div class='add'>+ * and it is expected that there are no open drm clients while doing so.</div><div class='add'>+ * The number of available compute slices is exposed to user through a per-gt</div><div class='add'>+ * 'num_cslices' sysfs interface.</div><div class='add'>+ */</div><div class='add'>+void xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_ccs_mode_enabled(gt))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	err = sysfs_create_files(gt-&gt;sysfs, gt_ccs_mode_attrs);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Sysfs creation for ccs_mode failed err: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_gt_ccs_mode_sysfs_fini, gt);</div><div class='add'>+	if (err) {</div><div class='add'>+		sysfs_remove_files(gt-&gt;sysfs, gt_ccs_mode_attrs);</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h<br/>new file mode 100644<br/>index 000000000000..f39975aaaab0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_ccs_mode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_ccs_mode.h</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_CCS_MODE_H_</div><div class='add'>+#define _XE_GT_CCS_MODE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+</div><div class='add'>+void xe_gt_apply_ccs_mode(struct xe_gt *gt);</div><div class='add'>+void xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+static inline bool xe_gt_ccs_mode_enabled(const struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/* Check if there are more than one compute engines available */</div><div class='add'>+	return hweight32(CCS_MASK(gt)) &gt; 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c<br/>new file mode 100644<br/>index 000000000000..937054e31d72<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_clock.c</a></div><div class='hunk'>@@ -0,0 +1,85 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_clock.h"</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+static u32 read_reference_ts_freq(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);</div><div class='add'>+	u32 base_freq, frac_freq;</div><div class='add'>+</div><div class='add'>+	base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,</div><div class='add'>+				  ts_override) + 1;</div><div class='add'>+	base_freq *= 1000000;</div><div class='add'>+</div><div class='add'>+	frac_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK,</div><div class='add'>+				  ts_override);</div><div class='add'>+	frac_freq = 1000000 / (frac_freq + 1);</div><div class='add'>+</div><div class='add'>+	return base_freq + frac_freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_crystal_clock_freq(u32 rpm_config_reg)</div><div class='add'>+{</div><div class='add'>+	const u32 f19_2_mhz = 19200000;</div><div class='add'>+	const u32 f24_mhz = 24000000;</div><div class='add'>+	const u32 f25_mhz = 25000000;</div><div class='add'>+	const u32 f38_4_mhz = 38400000;</div><div class='add'>+	u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,</div><div class='add'>+					  rpm_config_reg);</div><div class='add'>+</div><div class='add'>+	switch (crystal_clock) {</div><div class='add'>+	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:</div><div class='add'>+		return f24_mhz;</div><div class='add'>+	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:</div><div class='add'>+		return f19_2_mhz;</div><div class='add'>+	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:</div><div class='add'>+		return f38_4_mhz;</div><div class='add'>+	case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:</div><div class='add'>+		return f25_mhz;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON("NOT_POSSIBLE");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_gt_clock_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);</div><div class='add'>+	u32 freq = 0;</div><div class='add'>+</div><div class='add'>+	/* Assuming gen11+ so assert this assumption is correct */</div><div class='add'>+	xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) &gt;= 11);</div><div class='add'>+</div><div class='add'>+	if (ctc_reg &amp; CTC_SOURCE_DIVIDE_LOGIC) {</div><div class='add'>+		freq = read_reference_ts_freq(gt);</div><div class='add'>+	} else {</div><div class='add'>+		u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);</div><div class='add'>+</div><div class='add'>+		freq = get_crystal_clock_freq(c0);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Now figure out how the command stream's timestamp</div><div class='add'>+		 * register increments from this frequency (it might</div><div class='add'>+		 * increment only every few clock cycle).</div><div class='add'>+		 */</div><div class='add'>+		freq &gt;&gt;= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt-&gt;info.reference_clock = freq;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_gt_clock_cycles_to_ns(const struct xe_gt *gt, u64 count)</div><div class='add'>+{</div><div class='add'>+	return DIV_ROUND_CLOSEST_ULL(count * NSEC_PER_SEC, gt-&gt;info.reference_clock);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_clock.h b/drivers/gpu/drm/xe/xe_gt_clock.h<br/>new file mode 100644<br/>index 000000000000..aa162722f859<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_clock.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_clock.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_CLOCK_H_</div><div class='add'>+#define _XE_GT_CLOCK_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+int xe_gt_clock_init(struct xe_gt *gt);</div><div class='add'>+u64 xe_gt_clock_cycles_to_ns(const struct xe_gt *gt, u64 count);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c<br/>new file mode 100644<br/>index 000000000000..c4b67cf09f8f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,249 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_debugfs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_debugfs.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_pat.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+#include "xe_reg_whitelist.h"</div><div class='add'>+#include "xe_uc_debugfs.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *node_to_gt(struct drm_info_node *node)</div><div class='add'>+{</div><div class='add'>+	return node-&gt;info_ent-&gt;data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hw_engines(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_device_mem_access_put(xe);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xe_hw_engine_print(hwe, &amp;p);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int force_reset(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+</div><div class='add'>+	xe_gt_reset_async(gt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sa_info(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(node_to_gt(m-&gt;private));</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	drm_suballoc_dump_debug_info(&amp;tile-&gt;mem.kernel_bb_pool-&gt;base, &amp;p,</div><div class='add'>+				     tile-&gt;mem.kernel_bb_pool-&gt;gpu_addr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int topology(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_gt_topology_dump(gt, &amp;p);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int steering(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_gt_mcr_steering_dump(gt, &amp;p);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ggtt(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	return xe_ggtt_dump(gt_to_tile(gt)-&gt;mem.ggtt, &amp;p);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int register_save_restore(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_dump(&amp;gt-&gt;reg_sr, &amp;p);</div><div class='add'>+	drm_printf(&amp;p, "\n");</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "Engine\n");</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xe_reg_sr_dump(&amp;hwe-&gt;reg_sr, &amp;p);</div><div class='add'>+	drm_printf(&amp;p, "\n");</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "LRC\n");</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xe_reg_sr_dump(&amp;hwe-&gt;reg_lrc, &amp;p);</div><div class='add'>+	drm_printf(&amp;p, "\n");</div><div class='add'>+</div><div class='add'>+	drm_printf(&amp;p, "Whitelist\n");</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xe_reg_whitelist_dump(&amp;hwe-&gt;reg_whitelist, &amp;p);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int workarounds(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_wa_dump(gt, &amp;p);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pat(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = node_to_gt(m-&gt;private);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_pat_dump(gt, &amp;p);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rcs_default_lrc(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_lrc_dump_default(&amp;p, node_to_gt(m-&gt;private), XE_ENGINE_CLASS_RENDER);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ccs_default_lrc(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_lrc_dump_default(&amp;p, node_to_gt(m-&gt;private), XE_ENGINE_CLASS_COMPUTE);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bcs_default_lrc(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_lrc_dump_default(&amp;p, node_to_gt(m-&gt;private), XE_ENGINE_CLASS_COPY);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vcs_default_lrc(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_lrc_dump_default(&amp;p, node_to_gt(m-&gt;private), XE_ENGINE_CLASS_VIDEO_DECODE);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vecs_default_lrc(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_lrc_dump_default(&amp;p, node_to_gt(m-&gt;private), XE_ENGINE_CLASS_VIDEO_ENHANCE);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_info_list debugfs_list[] = {</div><div class='add'>+	{"hw_engines", hw_engines, 0},</div><div class='add'>+	{"force_reset", force_reset, 0},</div><div class='add'>+	{"sa_info", sa_info, 0},</div><div class='add'>+	{"topology", topology, 0},</div><div class='add'>+	{"steering", steering, 0},</div><div class='add'>+	{"ggtt", ggtt, 0},</div><div class='add'>+	{"register-save-restore", register_save_restore, 0},</div><div class='add'>+	{"workarounds", workarounds, 0},</div><div class='add'>+	{"pat", pat, 0},</div><div class='add'>+	{"default_lrc_rcs", rcs_default_lrc},</div><div class='add'>+	{"default_lrc_ccs", ccs_default_lrc},</div><div class='add'>+	{"default_lrc_bcs", bcs_default_lrc},</div><div class='add'>+	{"default_lrc_vcs", vcs_default_lrc},</div><div class='add'>+	{"default_lrc_vecs", vecs_default_lrc},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_gt_debugfs_register(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct drm_minor *minor = gt_to_xe(gt)-&gt;drm.primary;</div><div class='add'>+	struct dentry *root;</div><div class='add'>+	struct drm_info_list *local;</div><div class='add'>+	char name[8];</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, minor-&gt;debugfs_root);</div><div class='add'>+</div><div class='add'>+	sprintf(name, "gt%d", gt-&gt;info.id);</div><div class='add'>+	root = debugfs_create_dir(name, minor-&gt;debugfs_root);</div><div class='add'>+	if (IS_ERR(root)) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Create GT directory failed");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Allocate local copy as we need to pass in the GT to the debugfs</div><div class='add'>+	 * entry and drm_debugfs_create_files just references the drm_info_list</div><div class='add'>+	 * passed in (e.g. can't define this on the stack).</div><div class='add'>+	 */</div><div class='add'>+#define DEBUGFS_SIZE	(ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))</div><div class='add'>+	local = drmm_kmalloc(&amp;xe-&gt;drm, DEBUGFS_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!local)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memcpy(local, debugfs_list, DEBUGFS_SIZE);</div><div class='add'>+#undef DEBUGFS_SIZE</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(debugfs_list); ++i)</div><div class='add'>+		local[i].data = gt;</div><div class='add'>+</div><div class='add'>+	drm_debugfs_create_files(local,</div><div class='add'>+				 ARRAY_SIZE(debugfs_list),</div><div class='add'>+				 root, minor);</div><div class='add'>+</div><div class='add'>+	xe_uc_debugfs_register(&amp;gt-&gt;uc, root);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.h b/drivers/gpu/drm/xe/xe_gt_debugfs.h<br/>new file mode 100644<br/>index 000000000000..5a329f118a57<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_DEBUGFS_H_</div><div class='add'>+#define _XE_GT_DEBUGFS_H_</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_gt_debugfs_register(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c<br/>new file mode 100644<br/>index 000000000000..e5b0f4ecdbe8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_freq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_freq.c</a></div><div class='hunk'>@@ -0,0 +1,222 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_freq.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_gt_throttle_sysfs.h"</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe GT Frequency Management</div><div class='add'>+ *</div><div class='add'>+ * This component is responsible for the raw GT frequency management, including</div><div class='add'>+ * the sysfs API.</div><div class='add'>+ *</div><div class='add'>+ * Underneath, Xe enables GuC SLPC automated frequency management. GuC is then</div><div class='add'>+ * allowed to request PCODE any frequency between the Minimum and the Maximum</div><div class='add'>+ * selected by this component. Furthermore, it is important to highlight that</div><div class='add'>+ * PCODE is the ultimate decision maker of the actual running frequency, based</div><div class='add'>+ * on thermal and other running conditions.</div><div class='add'>+ *</div><div class='add'>+ * Xe's Freq provides a sysfs API for frequency management:</div><div class='add'>+ *</div><div class='add'>+ * device/tile#/gt#/freq0/&lt;item&gt;_freq *read-only* files:</div><div class='add'>+ * - act_freq: The actual resolved frequency decided by PCODE.</div><div class='add'>+ * - cur_freq: The current one requested by GuC PC to the PCODE.</div><div class='add'>+ * - rpn_freq: The Render Performance (RP) N level, which is the minimal one.</div><div class='add'>+ * - rpe_freq: The Render Performance (RP) E level, which is the efficient one.</div><div class='add'>+ * - rp0_freq: The Render Performance (RP) 0 level, which is the maximum one.</div><div class='add'>+ *</div><div class='add'>+ * device/tile#/gt#/freq0/&lt;item&gt;_freq *read-write* files:</div><div class='add'>+ * - min_freq: Min frequency request.</div><div class='add'>+ * - max_freq: Max frequency request.</div><div class='add'>+ *             If max &lt;= min, then freq_min becomes a fixed frequency request.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static struct xe_guc_pc *</div><div class='add'>+dev_to_pc(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	return &amp;kobj_to_gt(dev-&gt;kobj.parent)-&gt;uc.guc.pc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t act_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", xe_guc_pc_get_act_freq(pc));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(act_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t cur_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+	u32 freq;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_get_cur_freq(pc, &amp;freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", freq);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(cur_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t rp0_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rp0_freq(pc));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(rp0_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t rpe_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpe_freq(pc));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(rpe_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t rpn_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpn_freq(pc));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(rpn_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t min_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+	u32 freq;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_get_min_freq(pc, &amp;freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t min_freq_store(struct device *dev, struct device_attribute *attr,</div><div class='add'>+			      const char *buff, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+	u32 freq;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32(buff, 0, &amp;freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_set_min_freq(pc, freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(min_freq);</div><div class='add'>+</div><div class='add'>+static ssize_t max_freq_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+	u32 freq;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_get_max_freq(pc, &amp;freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t max_freq_store(struct device *dev, struct device_attribute *attr,</div><div class='add'>+			      const char *buff, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_pc *pc = dev_to_pc(dev);</div><div class='add'>+	u32 freq;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtou32(buff, 0, &amp;freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_set_max_freq(pc, freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(max_freq);</div><div class='add'>+</div><div class='add'>+static const struct attribute *freq_attrs[] = {</div><div class='add'>+	&amp;dev_attr_act_freq.attr,</div><div class='add'>+	&amp;dev_attr_cur_freq.attr,</div><div class='add'>+	&amp;dev_attr_rp0_freq.attr,</div><div class='add'>+	&amp;dev_attr_rpe_freq.attr,</div><div class='add'>+	&amp;dev_attr_rpn_freq.attr,</div><div class='add'>+	&amp;dev_attr_min_freq.attr,</div><div class='add'>+	&amp;dev_attr_max_freq.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void freq_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_files(kobj, freq_attrs);</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_freq_init - Initialize Xe Freq component</div><div class='add'>+ * @gt: Xe GT object</div><div class='add'>+ *</div><div class='add'>+ * It needs to be initialized after GT Sysfs and GuC PC components are ready.</div><div class='add'>+ */</div><div class='add'>+void xe_gt_freq_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	gt-&gt;freq = kobject_create_and_add("freq0", gt-&gt;sysfs);</div><div class='add'>+	if (!gt-&gt;freq) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "failed to add freq0 directory to %s\n",</div><div class='add'>+			 kobject_name(gt-&gt;sysfs));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, freq_fini, gt-&gt;freq);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = sysfs_create_files(gt-&gt;freq, freq_attrs);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm,  "failed to add freq attrs to %s, err: %d\n",</div><div class='add'>+			 kobject_name(gt-&gt;freq), err);</div><div class='add'>+</div><div class='add'>+	xe_gt_throttle_sysfs_init(gt);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_freq.h b/drivers/gpu/drm/xe/xe_gt_freq.h<br/>new file mode 100644<br/>index 000000000000..f3fe3c90491a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_freq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_freq.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_FREQ_H_</div><div class='add'>+#define _XE_GT_FREQ_H_</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_gt_freq_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c<br/>new file mode 100644<br/>index 000000000000..9358f7336889<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_idle.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle.c</a></div><div class='hunk'>@@ -0,0 +1,192 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_idle.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe GT Idle</div><div class='add'>+ *</div><div class='add'>+ * Contains functions that init GT idle features like C6</div><div class='add'>+ *</div><div class='add'>+ * device/gt#/gtidle/name - name of the state</div><div class='add'>+ * device/gt#/gtidle/idle_residency_ms - Provides residency of the idle state in ms</div><div class='add'>+ * device/gt#/gtidle/idle_status - Provides current idle state</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static struct xe_gt_idle *dev_to_gtidle(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = &amp;dev-&gt;kobj;</div><div class='add'>+</div><div class='add'>+	return &amp;kobj_to_gt(kobj-&gt;parent)-&gt;gtidle;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *gtidle_to_gt(struct xe_gt_idle *gtidle)</div><div class='add'>+{</div><div class='add'>+	return container_of(gtidle, struct xe_gt, gtidle);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_guc_pc *gtidle_to_pc(struct xe_gt_idle *gtidle)</div><div class='add'>+{</div><div class='add'>+	return &amp;gtidle_to_gt(gtidle)-&gt;uc.guc.pc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *gt_idle_state_to_string(enum xe_gt_idle_state state)</div><div class='add'>+{</div><div class='add'>+	switch (state) {</div><div class='add'>+	case GT_IDLE_C0:</div><div class='add'>+		return "gt-c0";</div><div class='add'>+	case GT_IDLE_C6:</div><div class='add'>+		return "gt-c6";</div><div class='add'>+	default:</div><div class='add'>+		return "unknown";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 get_residency_ms(struct xe_gt_idle *gtidle, u64 cur_residency)</div><div class='add'>+{</div><div class='add'>+	u64 delta, overflow_residency, prev_residency;</div><div class='add'>+</div><div class='add'>+	overflow_residency = BIT_ULL(32);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Counter wrap handling</div><div class='add'>+	 * Store previous hw counter values for counter wrap-around handling</div><div class='add'>+	 * Relying on sufficient frequency of queries otherwise counters can still wrap.</div><div class='add'>+	 */</div><div class='add'>+	prev_residency = gtidle-&gt;prev_residency;</div><div class='add'>+	gtidle-&gt;prev_residency = cur_residency;</div><div class='add'>+</div><div class='add'>+	/* delta */</div><div class='add'>+	if (cur_residency &gt;= prev_residency)</div><div class='add'>+		delta = cur_residency - prev_residency;</div><div class='add'>+	else</div><div class='add'>+		delta = cur_residency + (overflow_residency - prev_residency);</div><div class='add'>+</div><div class='add'>+	/* Add delta to extended raw driver copy of idle residency */</div><div class='add'>+	cur_residency = gtidle-&gt;cur_residency + delta;</div><div class='add'>+	gtidle-&gt;cur_residency = cur_residency;</div><div class='add'>+</div><div class='add'>+	/* residency multiplier in ns, convert to ms */</div><div class='add'>+	cur_residency = mul_u64_u32_div(cur_residency, gtidle-&gt;residency_multiplier, 1e6);</div><div class='add'>+</div><div class='add'>+	return cur_residency;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t name_show(struct device *dev,</div><div class='add'>+			 struct device_attribute *attr, char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt_idle *gtidle = dev_to_gtidle(dev);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%s\n", gtidle-&gt;name);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(name);</div><div class='add'>+</div><div class='add'>+static ssize_t idle_status_show(struct device *dev,</div><div class='add'>+				struct device_attribute *attr, char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt_idle *gtidle = dev_to_gtidle(dev);</div><div class='add'>+	struct xe_guc_pc *pc = gtidle_to_pc(gtidle);</div><div class='add'>+	enum xe_gt_idle_state state;</div><div class='add'>+</div><div class='add'>+	state = gtidle-&gt;idle_status(pc);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%s\n", gt_idle_state_to_string(state));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(idle_status);</div><div class='add'>+</div><div class='add'>+static ssize_t idle_residency_ms_show(struct device *dev,</div><div class='add'>+				      struct device_attribute *attr, char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt_idle *gtidle = dev_to_gtidle(dev);</div><div class='add'>+	struct xe_guc_pc *pc = gtidle_to_pc(gtidle);</div><div class='add'>+	u64 residency;</div><div class='add'>+</div><div class='add'>+	residency = gtidle-&gt;idle_residency(pc);</div><div class='add'>+	return sysfs_emit(buff, "%llu\n", get_residency_ms(gtidle, residency));</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(idle_residency_ms);</div><div class='add'>+</div><div class='add'>+static const struct attribute *gt_idle_attrs[] = {</div><div class='add'>+	&amp;dev_attr_name.attr,</div><div class='add'>+	&amp;dev_attr_idle_status.attr,</div><div class='add'>+	&amp;dev_attr_idle_residency_ms.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gt_idle_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_files(kobj, gt_idle_attrs);</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = gtidle_to_gt(gtidle);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct kobject *kobj;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	kobj = kobject_create_and_add("gtidle", gt-&gt;sysfs);</div><div class='add'>+	if (!kobj) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s failed, err: %d\n", __func__, -ENOMEM);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt)) {</div><div class='add'>+		sprintf(gtidle-&gt;name, "gt%d-mc\n", gt-&gt;info.id);</div><div class='add'>+		gtidle-&gt;idle_residency = xe_guc_pc_mc6_residency;</div><div class='add'>+	} else {</div><div class='add'>+		sprintf(gtidle-&gt;name, "gt%d-rc\n", gt-&gt;info.id);</div><div class='add'>+		gtidle-&gt;idle_residency = xe_guc_pc_rc6_residency;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Multiplier for Residency counter in units of 1.28us */</div><div class='add'>+	gtidle-&gt;residency_multiplier = 1280;</div><div class='add'>+	gtidle-&gt;idle_status = xe_guc_pc_c_status;</div><div class='add'>+</div><div class='add'>+	err = sysfs_create_files(kobj, gt_idle_attrs);</div><div class='add'>+	if (err) {</div><div class='add'>+		kobject_put(kobj);</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "failed to register gtidle sysfs, err: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, gt_idle_sysfs_fini, kobj);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_idle_enable_c6(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(gt_to_xe(gt));</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	/* Units of 1280 ns for a total of 5s */</div><div class='add'>+	xe_mmio_write32(gt, RC_IDLE_HYSTERSIS, 0x3B9ACA);</div><div class='add'>+	/* Enable RC6 */</div><div class='add'>+	xe_mmio_write32(gt, RC_CONTROL,</div><div class='add'>+			RC_CTL_HW_ENABLE | RC_CTL_TO_MODE | RC_CTL_RC6_ENABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_idle_disable_c6(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(gt_to_xe(gt));</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, PG_ENABLE, 0);</div><div class='add'>+	xe_mmio_write32(gt, RC_CONTROL, 0);</div><div class='add'>+	xe_mmio_write32(gt, RC_STATE, 0);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_idle.h b/drivers/gpu/drm/xe/xe_gt_idle.h<br/>new file mode 100644<br/>index 000000000000..69280fd16b03<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_idle.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_IDLE_H_</div><div class='add'>+#define _XE_GT_IDLE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gt_idle_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle);</div><div class='add'>+void xe_gt_idle_enable_c6(struct xe_gt *gt);</div><div class='add'>+void xe_gt_idle_disable_c6(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_IDLE_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_idle_types.h b/drivers/gpu/drm/xe/xe_gt_idle_types.h<br/>new file mode 100644<br/>index 000000000000..f99b447534f3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_idle_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_idle_types.h</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_IDLE_SYSFS_TYPES_H_</div><div class='add'>+#define _XE_GT_IDLE_SYSFS_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_guc_pc;</div><div class='add'>+</div><div class='add'>+/* States of GT Idle */</div><div class='add'>+enum xe_gt_idle_state {</div><div class='add'>+	GT_IDLE_C0,</div><div class='add'>+	GT_IDLE_C6,</div><div class='add'>+	GT_IDLE_UNKNOWN,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_gt_idle - A struct that contains idle properties based of gt</div><div class='add'>+ */</div><div class='add'>+struct xe_gt_idle {</div><div class='add'>+	/** @name: name */</div><div class='add'>+	char name[16];</div><div class='add'>+	/** @residency_multiplier: residency multiplier in ns */</div><div class='add'>+	u32 residency_multiplier;</div><div class='add'>+	/** @cur_residency: raw driver copy of idle residency */</div><div class='add'>+	u64 cur_residency;</div><div class='add'>+	/** @prev_residency: previous residency counter */</div><div class='add'>+	u64 prev_residency;</div><div class='add'>+	/** @idle_status: get the current idle state */</div><div class='add'>+	enum xe_gt_idle_state (*idle_status)(struct xe_guc_pc *pc);</div><div class='add'>+	/** @idle_residency: get idle residency counter */</div><div class='add'>+	u64 (*idle_residency)(struct xe_guc_pc *pc);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_IDLE_SYSFS_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c<br/>new file mode 100644<br/>index 000000000000..77925b35cf8d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_mcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_mcr.c</a></div><div class='hunk'>@@ -0,0 +1,685 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GT Multicast/Replicated (MCR) Register Support</div><div class='add'>+ *</div><div class='add'>+ * Some GT registers are designed as "multicast" or "replicated" registers:</div><div class='add'>+ * multiple instances of the same register share a single MMIO offset.  MCR</div><div class='add'>+ * registers are generally used when the hardware needs to potentially track</div><div class='add'>+ * independent values of a register per hardware unit (e.g., per-subslice,</div><div class='add'>+ * per-L3bank, etc.).  The specific types of replication that exist vary</div><div class='add'>+ * per-platform.</div><div class='add'>+ *</div><div class='add'>+ * MMIO accesses to MCR registers are controlled according to the settings</div><div class='add'>+ * programmed in the platform's MCR_SELECTOR register(s).  MMIO writes to MCR</div><div class='add'>+ * registers can be done in either multicast (a single write updates all</div><div class='add'>+ * instances of the register to the same value) or unicast (a write updates only</div><div class='add'>+ * one specific instance) form.  Reads of MCR registers always operate in a</div><div class='add'>+ * unicast manner regardless of how the multicast/unicast bit is set in</div><div class='add'>+ * MCR_SELECTOR.  Selection of a specific MCR instance for unicast operations is</div><div class='add'>+ * referred to as "steering."</div><div class='add'>+ *</div><div class='add'>+ * If MCR register operations are steered toward a hardware unit that is</div><div class='add'>+ * fused off or currently powered down due to power gating, the MMIO operation</div><div class='add'>+ * is "terminated" by the hardware.  Terminated read operations will return a</div><div class='add'>+ * value of zero and terminated unicast write operations will be silently</div><div class='add'>+ * ignored. During device initialization, the goal of the various</div><div class='add'>+ * ``init_steering_*()`` functions is to apply the platform-specific rules for</div><div class='add'>+ * each MCR register type to identify a steering target that will select a</div><div class='add'>+ * non-terminated instance.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define STEER_SEMAPHORE		XE_REG(0xFD0)</div><div class='add'>+</div><div class='add'>+static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)</div><div class='add'>+{</div><div class='add'>+	return reg_mcr.__reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	MCR_OP_READ,</div><div class='add'>+	MCR_OP_WRITE</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xelp_l3bank_steering_table[] = {</div><div class='add'>+	{ 0x00B100, 0x00B3FF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xehp_l3bank_steering_table[] = {</div><div class='add'>+	{ 0x008C80, 0x008CFF },</div><div class='add'>+	{ 0x00B100, 0x00B3FF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Although the bspec lists more "MSLICE" ranges than shown here, some of those</div><div class='add'>+ * are of a "GAM" subclass that has special rules and doesn't need to be</div><div class='add'>+ * included here.</div><div class='add'>+ */</div><div class='add'>+static const struct xe_mmio_range xehp_mslice_steering_table[] = {</div><div class='add'>+	{ 0x00DD00, 0x00DDFF },</div><div class='add'>+	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xehp_lncf_steering_table[] = {</div><div class='add'>+	{ 0x00B000, 0x00B0FF },</div><div class='add'>+	{ 0x00D880, 0x00D8FF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * We have several types of MCR registers where steering to (0,0) will always</div><div class='add'>+ * provide us with a non-terminated value.  We'll stick them all in the same</div><div class='add'>+ * table for simplicity.</div><div class='add'>+ */</div><div class='add'>+static const struct xe_mmio_range xehpc_instance0_steering_table[] = {</div><div class='add'>+	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x008800, 0x00887F },		/* CC */</div><div class='add'>+	{ 0x008A80, 0x008AFF },		/* TILEPSMI */</div><div class='add'>+	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x00B100, 0x00B3FF },		/* L3BANK */</div><div class='add'>+	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x00DD00, 0x00DDFF },		/* BSLICE */</div><div class='add'>+	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */</div><div class='add'>+	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xelpg_instance0_steering_table[] = {</div><div class='add'>+	{ 0x000B00, 0x000BFF },         /* SQIDI */</div><div class='add'>+	{ 0x001000, 0x001FFF },         /* SQIDI */</div><div class='add'>+	{ 0x004000, 0x0048FF },         /* GAM */</div><div class='add'>+	{ 0x008700, 0x0087FF },         /* SQIDI */</div><div class='add'>+	{ 0x00B000, 0x00B0FF },         /* NODE */</div><div class='add'>+	{ 0x00C800, 0x00CFFF },         /* GAM */</div><div class='add'>+	{ 0x00D880, 0x00D8FF },         /* NODE */</div><div class='add'>+	{ 0x00DD00, 0x00DDFF },         /* OAAL2 */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xelpg_l3bank_steering_table[] = {</div><div class='add'>+	{ 0x00B100, 0x00B3FF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xelp_dss_steering_table[] = {</div><div class='add'>+	{ 0x008150, 0x00815F },</div><div class='add'>+	{ 0x009520, 0x00955F },</div><div class='add'>+	{ 0x00DE80, 0x00E8FF },</div><div class='add'>+	{ 0x024A00, 0x024A7F },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DSS steering is used for GSLICE ranges as well */</div><div class='add'>+static const struct xe_mmio_range xehp_dss_steering_table[] = {</div><div class='add'>+	{ 0x005200, 0x0052FF },		/* GSLICE */</div><div class='add'>+	{ 0x005400, 0x007FFF },		/* GSLICE */</div><div class='add'>+	{ 0x008140, 0x00815F },		/* GSLICE (0x8140-0x814F), DSS (0x8150-0x815F) */</div><div class='add'>+	{ 0x008D00, 0x008DFF },		/* DSS */</div><div class='add'>+	{ 0x0094D0, 0x00955F },		/* GSLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */</div><div class='add'>+	{ 0x009680, 0x0096FF },		/* DSS */</div><div class='add'>+	{ 0x00D800, 0x00D87F },		/* GSLICE */</div><div class='add'>+	{ 0x00DC00, 0x00DCFF },		/* GSLICE */</div><div class='add'>+	{ 0x00DE80, 0x00E8FF },		/* DSS (0xE000-0xE0FF reserved ) */</div><div class='add'>+	{ 0x017000, 0x017FFF },		/* GSLICE */</div><div class='add'>+	{ 0x024A00, 0x024A7F },		/* DSS */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DSS steering is used for COMPUTE ranges as well */</div><div class='add'>+static const struct xe_mmio_range xehpc_dss_steering_table[] = {</div><div class='add'>+	{ 0x008140, 0x00817F },		/* COMPUTE (0x8140-0x814F &amp; 0x8160-0x817F), DSS (0x8150-0x815F) */</div><div class='add'>+	{ 0x0094D0, 0x00955F },		/* COMPUTE (0x94D0-0x951F), DSS (0x9520-0x955F) */</div><div class='add'>+	{ 0x009680, 0x0096FF },		/* DSS */</div><div class='add'>+	{ 0x00DC00, 0x00DCFF },		/* COMPUTE */</div><div class='add'>+	{ 0x00DE80, 0x00E7FF },		/* DSS (0xDF00-0xE1FF reserved ) */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* DSS steering is used for SLICE ranges as well */</div><div class='add'>+static const struct xe_mmio_range xelpg_dss_steering_table[] = {</div><div class='add'>+	{ 0x005200, 0x0052FF },		/* SLICE */</div><div class='add'>+	{ 0x005500, 0x007FFF },		/* SLICE */</div><div class='add'>+	{ 0x008140, 0x00815F },		/* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */</div><div class='add'>+	{ 0x0094D0, 0x00955F },		/* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */</div><div class='add'>+	{ 0x009680, 0x0096FF },		/* DSS */</div><div class='add'>+	{ 0x00D800, 0x00D87F },		/* SLICE */</div><div class='add'>+	{ 0x00DC00, 0x00DCFF },		/* SLICE */</div><div class='add'>+	{ 0x00DE80, 0x00E8FF },		/* DSS (0xE000-0xE0FF reserved) */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {</div><div class='add'>+	{ 0x393200, 0x39323F },</div><div class='add'>+	{ 0x393400, 0x3934FF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range dg2_implicit_steering_table[] = {</div><div class='add'>+	{ 0x000B00, 0x000BFF },		/* SF (SQIDI replication) */</div><div class='add'>+	{ 0x001000, 0x001FFF },		/* SF (SQIDI replication) */</div><div class='add'>+	{ 0x004000, 0x004AFF },		/* GAM (MSLICE replication) */</div><div class='add'>+	{ 0x008700, 0x0087FF },		/* MCFG (SQIDI replication) */</div><div class='add'>+	{ 0x00C800, 0x00CFFF },		/* GAM (MSLICE replication) */</div><div class='add'>+	{ 0x00F000, 0x00FFFF },		/* GAM (MSLICE replication) */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xe2lpg_dss_steering_table[] = {</div><div class='add'>+	{ 0x005200, 0x0052FF },         /* SLICE */</div><div class='add'>+	{ 0x005500, 0x007FFF },         /* SLICE */</div><div class='add'>+	{ 0x008140, 0x00815F },         /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */</div><div class='add'>+	{ 0x0094D0, 0x00955F },         /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */</div><div class='add'>+	{ 0x009680, 0x0096FF },         /* DSS */</div><div class='add'>+	{ 0x00D800, 0x00D87F },         /* SLICE */</div><div class='add'>+	{ 0x00DC00, 0x00DCFF },         /* SLICE */</div><div class='add'>+	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */</div><div class='add'>+	{ 0x00E980, 0x00E9FF },         /* SLICE */</div><div class='add'>+	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-0x133FF) */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xe2lpg_sqidi_psmi_steering_table[] = {</div><div class='add'>+	{ 0x000B00, 0x000BFF },</div><div class='add'>+	{ 0x001000, 0x001FFF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xe2lpg_instance0_steering_table[] = {</div><div class='add'>+	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */</div><div class='add'>+	{ 0x008700, 0x00887F },         /* SQIDI, MEMPIPE */</div><div class='add'>+	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */</div><div class='add'>+	{ 0x00C800, 0x00CFFF },         /* GAM */</div><div class='add'>+	{ 0x00D880, 0x00D8FF },         /* NODE */</div><div class='add'>+	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */</div><div class='add'>+	{ 0x00E900, 0x00E97F },         /* MEMPIPE */</div><div class='add'>+	{ 0x00F000, 0x00FFFF },         /* GAM, GAMWKR */</div><div class='add'>+	{ 0x013400, 0x0135FF },         /* MEMPIPE */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xe2lpm_gpmxmt_steering_table[] = {</div><div class='add'>+	{ 0x388160, 0x38817F },</div><div class='add'>+	{ 0x389480, 0x3894CF },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {</div><div class='add'>+	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */</div><div class='add'>+	{ 0x384900, 0x384AFF },         /* GAM */</div><div class='add'>+	{ 0x389560, 0x3895FF },         /* MEDIAINF */</div><div class='add'>+	{ 0x38B600, 0x38B8FF },         /* L3BANK */</div><div class='add'>+	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */</div><div class='add'>+	{ 0x38F000, 0x38F0FF },         /* GAM */</div><div class='add'>+	{ 0x393C00, 0x393C7F },         /* MEDIAINF */</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void init_steering_l3bank(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1270) {</div><div class='add'>+		u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,</div><div class='add'>+						xe_mmio_read32(gt, MIRROR_FUSE3));</div><div class='add'>+		u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,</div><div class='add'>+					      xe_mmio_read32(gt, XEHP_FUSE4));</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Group selects mslice, instance selects bank within mslice.</div><div class='add'>+		 * Bank 0 is always valid _except_ when the bank mask is 010b.</div><div class='add'>+		 */</div><div class='add'>+		gt-&gt;steering[L3BANK].group_target = __ffs(mslice_mask);</div><div class='add'>+		gt-&gt;steering[L3BANK].instance_target =</div><div class='add'>+			bank_mask &amp; BIT(0) ? 0 : 2;</div><div class='add'>+	} else if (gt_to_xe(gt)-&gt;info.platform == XE_DG2) {</div><div class='add'>+		u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,</div><div class='add'>+						xe_mmio_read32(gt, MIRROR_FUSE3));</div><div class='add'>+		u32 bank = __ffs(mslice_mask) * 8;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Like mslice registers, look for a valid mslice and steer to</div><div class='add'>+		 * the first L3BANK of that quad. Access to the Nth L3 bank is</div><div class='add'>+		 * split between the first bits of group and instance</div><div class='add'>+		 */</div><div class='add'>+		gt-&gt;steering[L3BANK].group_target = (bank &gt;&gt; 2) &amp; 0x7;</div><div class='add'>+		gt-&gt;steering[L3BANK].instance_target = bank &amp; 0x3;</div><div class='add'>+	} else {</div><div class='add'>+		u32 fuse = REG_FIELD_GET(L3BANK_MASK,</div><div class='add'>+					 ~xe_mmio_read32(gt, MIRROR_FUSE3));</div><div class='add'>+</div><div class='add'>+		gt-&gt;steering[L3BANK].group_target = 0;	/* unused */</div><div class='add'>+		gt-&gt;steering[L3BANK].instance_target = __ffs(fuse);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_steering_mslice(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 mask = REG_FIELD_GET(MEML3_EN_MASK,</div><div class='add'>+				 xe_mmio_read32(gt, MIRROR_FUSE3));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * mslice registers are valid (not terminated) if either the meml3</div><div class='add'>+	 * associated with the mslice is present, or at least one DSS associated</div><div class='add'>+	 * with the mslice is present.  There will always be at least one meml3</div><div class='add'>+	 * so we can just use that to find a non-terminated mslice and ignore</div><div class='add'>+	 * the DSS fusing.</div><div class='add'>+	 */</div><div class='add'>+	gt-&gt;steering[MSLICE].group_target = __ffs(mask);</div><div class='add'>+	gt-&gt;steering[MSLICE].instance_target = 0;	/* unused */</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * LNCF termination is also based on mslice presence, so we'll set</div><div class='add'>+	 * it up here.  Either LNCF within a non-terminated mslice will work,</div><div class='add'>+	 * so we just always pick LNCF 0 here.</div><div class='add'>+	 */</div><div class='add'>+	gt-&gt;steering[LNCF].group_target = __ffs(mask) &lt;&lt; 1;</div><div class='add'>+	gt-&gt;steering[LNCF].instance_target = 0;		/* unused */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_steering_dss(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	unsigned int dss = min(xe_dss_mask_group_ffs(gt-&gt;fuse_topo.g_dss_mask, 0, 0),</div><div class='add'>+			       xe_dss_mask_group_ffs(gt-&gt;fuse_topo.c_dss_mask, 0, 0));</div><div class='add'>+	unsigned int dss_per_grp = gt_to_xe(gt)-&gt;info.platform == XE_PVC ? 8 : 4;</div><div class='add'>+</div><div class='add'>+	gt-&gt;steering[DSS].group_target = dss / dss_per_grp;</div><div class='add'>+	gt-&gt;steering[DSS].instance_target = dss % dss_per_grp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_steering_oaddrm(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * First instance is only terminated if the entire first media slice</div><div class='add'>+	 * is absent (i.e., no VCS0 or VECS0).</div><div class='add'>+	 */</div><div class='add'>+	if (gt-&gt;info.engine_mask &amp; (XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0))</div><div class='add'>+		gt-&gt;steering[OADDRM].group_target = 0;</div><div class='add'>+	else</div><div class='add'>+		gt-&gt;steering[OADDRM].group_target = 1;</div><div class='add'>+</div><div class='add'>+	gt-&gt;steering[DSS].instance_target = 0;		/* unused */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_steering_sqidi_psmi(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK,</div><div class='add'>+				 xe_mmio_read32(gt, MIRROR_FUSE3));</div><div class='add'>+	u32 select = __ffs(mask);</div><div class='add'>+</div><div class='add'>+	gt-&gt;steering[SQIDI_PSMI].group_target = select &gt;&gt; 1;</div><div class='add'>+	gt-&gt;steering[SQIDI_PSMI].instance_target = select &amp; 0x1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_steering_inst0(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	gt-&gt;steering[DSS].group_target = 0;		/* unused */</div><div class='add'>+	gt-&gt;steering[DSS].instance_target = 0;		/* unused */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct {</div><div class='add'>+	const char *name;</div><div class='add'>+	void (*init)(struct xe_gt *gt);</div><div class='add'>+} xe_steering_types[] = {</div><div class='add'>+	[L3BANK] =	{ "L3BANK",	init_steering_l3bank },</div><div class='add'>+	[MSLICE] =	{ "MSLICE",	init_steering_mslice },</div><div class='add'>+	[LNCF] =	{ "LNCF",	NULL }, /* initialized by mslice init */</div><div class='add'>+	[DSS] =		{ "DSS",	init_steering_dss },</div><div class='add'>+	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },</div><div class='add'>+	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },</div><div class='add'>+	[INSTANCE0] =	{ "INSTANCE 0",	init_steering_inst0 },</div><div class='add'>+	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(IMPLICIT_STEERING + 1 != NUM_STEERING_TYPES);</div><div class='add'>+	BUILD_BUG_ON(ARRAY_SIZE(xe_steering_types) != NUM_STEERING_TYPES);</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;gt-&gt;mcr_lock);</div><div class='add'>+</div><div class='add'>+	if (gt-&gt;info.type == XE_GT_TYPE_MEDIA) {</div><div class='add'>+		drm_WARN_ON(&amp;xe-&gt;drm, MEDIA_VER(xe) &lt; 13);</div><div class='add'>+</div><div class='add'>+		if (MEDIA_VER(xe) &gt;= 20) {</div><div class='add'>+			gt-&gt;steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table;</div><div class='add'>+			gt-&gt;steering[INSTANCE0].ranges = xe2lpm_instance0_steering_table;</div><div class='add'>+		} else {</div><div class='add'>+			gt-&gt;steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20) {</div><div class='add'>+			gt-&gt;steering[DSS].ranges = xe2lpg_dss_steering_table;</div><div class='add'>+			gt-&gt;steering[SQIDI_PSMI].ranges = xe2lpg_sqidi_psmi_steering_table;</div><div class='add'>+			gt-&gt;steering[INSTANCE0].ranges = xe2lpg_instance0_steering_table;</div><div class='add'>+		} else if (GRAPHICS_VERx100(xe) &gt;= 1270) {</div><div class='add'>+			gt-&gt;steering[INSTANCE0].ranges = xelpg_instance0_steering_table;</div><div class='add'>+			gt-&gt;steering[L3BANK].ranges = xelpg_l3bank_steering_table;</div><div class='add'>+			gt-&gt;steering[DSS].ranges = xelpg_dss_steering_table;</div><div class='add'>+		} else if (xe-&gt;info.platform == XE_PVC) {</div><div class='add'>+			gt-&gt;steering[INSTANCE0].ranges = xehpc_instance0_steering_table;</div><div class='add'>+			gt-&gt;steering[DSS].ranges = xehpc_dss_steering_table;</div><div class='add'>+		} else if (xe-&gt;info.platform == XE_DG2) {</div><div class='add'>+			gt-&gt;steering[L3BANK].ranges = xehp_l3bank_steering_table;</div><div class='add'>+			gt-&gt;steering[MSLICE].ranges = xehp_mslice_steering_table;</div><div class='add'>+			gt-&gt;steering[LNCF].ranges = xehp_lncf_steering_table;</div><div class='add'>+			gt-&gt;steering[DSS].ranges = xehp_dss_steering_table;</div><div class='add'>+			gt-&gt;steering[IMPLICIT_STEERING].ranges = dg2_implicit_steering_table;</div><div class='add'>+		} else {</div><div class='add'>+			gt-&gt;steering[L3BANK].ranges = xelp_l3bank_steering_table;</div><div class='add'>+			gt-&gt;steering[DSS].ranges = xelp_dss_steering_table;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Select non-terminated steering target for each type */</div><div class='add'>+	for (int i = 0; i &lt; NUM_STEERING_TYPES; i++)</div><div class='add'>+		if (gt-&gt;steering[i].ranges &amp;&amp; xe_steering_types[i].init)</div><div class='add'>+			xe_steering_types[i].init(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_mcr_set_implicit_defaults - Initialize steer control registers</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ *</div><div class='add'>+ * Some register ranges don't need to have their steering control registers</div><div class='add'>+ * changed on each access - it's sufficient to set them once on initialization.</div><div class='add'>+ * This function sets those registers for each platform *</div><div class='add'>+ */</div><div class='add'>+void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.platform == XE_DG2) {</div><div class='add'>+		u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |</div><div class='add'>+			REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);</div><div class='add'>+</div><div class='add'>+		xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);</div><div class='add'>+		xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);</div><div class='add'>+		/*</div><div class='add'>+		 * For GAM registers, all reads should be directed to instance 1</div><div class='add'>+		 * (unicast reads against other instances are not allowed),</div><div class='add'>+		 * and instance 1 is already the hardware's default steering</div><div class='add'>+		 * target, which we never change</div><div class='add'>+		 */</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * xe_gt_mcr_get_nonterminated_steering - find group/instance values that</div><div class='add'>+ *    will steer a register to a non-terminated instance</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @reg: register for which the steering is required</div><div class='add'>+ * @group: return variable for group steering</div><div class='add'>+ * @instance: return variable for instance steering</div><div class='add'>+ *</div><div class='add'>+ * This function returns a group/instance pair that is guaranteed to work for</div><div class='add'>+ * read steering of the given register. Note that a value will be returned even</div><div class='add'>+ * if the register is not replicated and therefore does not actually require</div><div class='add'>+ * steering.</div><div class='add'>+ *</div><div class='add'>+ * Returns true if the caller should steer to the @group/@instance values</div><div class='add'>+ * returned.  Returns false if the caller need not perform any steering</div><div class='add'>+ */</div><div class='add'>+static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,</div><div class='add'>+						 struct xe_reg_mcr reg_mcr,</div><div class='add'>+						 u8 *group, u8 *instance)</div><div class='add'>+{</div><div class='add'>+	const struct xe_reg reg = to_xe_reg(reg_mcr);</div><div class='add'>+	const struct xe_mmio_range *implicit_ranges;</div><div class='add'>+</div><div class='add'>+	for (int type = 0; type &lt; IMPLICIT_STEERING; type++) {</div><div class='add'>+		if (!gt-&gt;steering[type].ranges)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (int i = 0; gt-&gt;steering[type].ranges[i].end &gt; 0; i++) {</div><div class='add'>+			if (xe_mmio_in_range(gt, &amp;gt-&gt;steering[type].ranges[i], reg)) {</div><div class='add'>+				*group = gt-&gt;steering[type].group_target;</div><div class='add'>+				*instance = gt-&gt;steering[type].instance_target;</div><div class='add'>+				return true;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	implicit_ranges = gt-&gt;steering[IMPLICIT_STEERING].ranges;</div><div class='add'>+	if (implicit_ranges)</div><div class='add'>+		for (int i = 0; implicit_ranges[i].end &gt; 0; i++)</div><div class='add'>+			if (xe_mmio_in_range(gt, &amp;implicit_ranges[i], reg))</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Not found in a steering table and not a register with implicit</div><div class='add'>+	 * steering. Just steer to 0/0 as a guess and raise a warning.</div><div class='add'>+	 */</div><div class='add'>+	drm_WARN(&amp;gt_to_xe(gt)-&gt;drm, true,</div><div class='add'>+		 "Did not find MCR register %#x in any MCR steering table\n",</div><div class='add'>+		 reg.addr);</div><div class='add'>+	*group = 0;</div><div class='add'>+	*instance = 0;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Obtain exclusive access to MCR steering.  On MTL and beyond we also need</div><div class='add'>+ * to synchronize with external clients (e.g., firmware), so a semaphore</div><div class='add'>+ * register will also need to be taken.</div><div class='add'>+ */</div><div class='add'>+static void mcr_lock(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;gt-&gt;mcr_lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Starting with MTL we also need to grab a semaphore register</div><div class='add'>+	 * to synchronize with external agents (e.g., firmware) that now</div><div class='add'>+	 * shares the same steering control register. The semaphore is obtained</div><div class='add'>+	 * when a read to the relevant register returns 1.</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,</div><div class='add'>+				     true);</div><div class='add'>+</div><div class='add'>+	drm_WARN_ON_ONCE(&amp;xe-&gt;drm, ret == -ETIMEDOUT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mcr_unlock(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/* Release hardware semaphore - this is done by writing 1 to the register */</div><div class='add'>+	if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1270)</div><div class='add'>+		xe_mmio_write32(gt, STEER_SEMAPHORE, 0x1);</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;gt-&gt;mcr_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Access a register with specific MCR steering</div><div class='add'>+ *</div><div class='add'>+ * Caller needs to make sure the relevant forcewake wells are up.</div><div class='add'>+ */</div><div class='add'>+static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,</div><div class='add'>+				u8 rw_flag, int group, int instance, u32 value)</div><div class='add'>+{</div><div class='add'>+	const struct xe_reg reg = to_xe_reg(reg_mcr);</div><div class='add'>+	struct xe_reg steer_reg;</div><div class='add'>+	u32 steer_val, val = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;gt-&gt;mcr_lock);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1270) {</div><div class='add'>+		steer_reg = MTL_MCR_SELECTOR;</div><div class='add'>+		steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |</div><div class='add'>+			REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);</div><div class='add'>+	} else {</div><div class='add'>+		steer_reg = MCR_SELECTOR;</div><div class='add'>+		steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, group) |</div><div class='add'>+			REG_FIELD_PREP(MCR_SUBSLICE_MASK, instance);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Always leave the hardware in multicast mode when doing reads and only</div><div class='add'>+	 * change it to unicast mode when doing writes of a specific instance.</div><div class='add'>+	 *</div><div class='add'>+	 * The setting of the multicast/unicast bit usually wouldn't matter for</div><div class='add'>+	 * read operations (which always return the value from a single register</div><div class='add'>+	 * instance regardless of how that bit is set), but some platforms may</div><div class='add'>+	 * have workarounds requiring us to remain in multicast mode for reads,</div><div class='add'>+	 * e.g. Wa_22013088509 on PVC.  There's no real downside to this, so</div><div class='add'>+	 * we'll just go ahead and do so on all platforms; we'll only clear the</div><div class='add'>+	 * multicast bit from the mask when explicitly doing a write operation.</div><div class='add'>+	 *</div><div class='add'>+	 * No need to save old steering reg value.</div><div class='add'>+	 */</div><div class='add'>+	if (rw_flag == MCR_OP_READ)</div><div class='add'>+		steer_val |= MCR_MULTICAST;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, steer_reg, steer_val);</div><div class='add'>+</div><div class='add'>+	if (rw_flag == MCR_OP_READ)</div><div class='add'>+		val = xe_mmio_read32(gt, reg);</div><div class='add'>+	else</div><div class='add'>+		xe_mmio_write32(gt, reg, value);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we turned off the multicast bit (during a write) we're required</div><div class='add'>+	 * to turn it back on before finishing.  The group and instance values</div><div class='add'>+	 * don't matter since they'll be re-programmed on the next MCR</div><div class='add'>+	 * operation.</div><div class='add'>+	 */</div><div class='add'>+	if (rw_flag == MCR_OP_WRITE)</div><div class='add'>+		xe_mmio_write32(gt, steer_reg, MCR_MULTICAST);</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_mcr_unicast_read_any - reads a non-terminated instance of an MCR register</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @reg_mcr: register to read</div><div class='add'>+ *</div><div class='add'>+ * Reads a GT MCR register.  The read will be steered to a non-terminated</div><div class='add'>+ * instance (i.e., one that isn't fused off or powered down by power gating).</div><div class='add'>+ * This function assumes the caller is already holding any necessary forcewake</div><div class='add'>+ * domains.</div><div class='add'>+ *</div><div class='add'>+ * Returns the value from a non-terminated instance of @reg.</div><div class='add'>+ */</div><div class='add'>+u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)</div><div class='add'>+{</div><div class='add'>+	const struct xe_reg reg = to_xe_reg(reg_mcr);</div><div class='add'>+	u8 group, instance;</div><div class='add'>+	u32 val;</div><div class='add'>+	bool steer;</div><div class='add'>+</div><div class='add'>+	steer = xe_gt_mcr_get_nonterminated_steering(gt, reg_mcr,</div><div class='add'>+						     &amp;group, &amp;instance);</div><div class='add'>+</div><div class='add'>+	if (steer) {</div><div class='add'>+		mcr_lock(gt);</div><div class='add'>+		val = rw_with_mcr_steering(gt, reg_mcr, MCR_OP_READ,</div><div class='add'>+					   group, instance, 0);</div><div class='add'>+		mcr_unlock(gt);</div><div class='add'>+	} else {</div><div class='add'>+		val = xe_mmio_read32(gt, reg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_mcr_unicast_read - read a specific instance of an MCR register</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @reg_mcr: the MCR register to read</div><div class='add'>+ * @group: the MCR group</div><div class='add'>+ * @instance: the MCR instance</div><div class='add'>+ *</div><div class='add'>+ * Returns the value read from an MCR register after steering toward a specific</div><div class='add'>+ * group/instance.</div><div class='add'>+ */</div><div class='add'>+u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,</div><div class='add'>+			   struct xe_reg_mcr reg_mcr,</div><div class='add'>+			   int group, int instance)</div><div class='add'>+{</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	mcr_lock(gt);</div><div class='add'>+	val = rw_with_mcr_steering(gt, reg_mcr, MCR_OP_READ, group, instance, 0);</div><div class='add'>+	mcr_unlock(gt);</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_mcr_unicast_write - write a specific instance of an MCR register</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @reg_mcr: the MCR register to write</div><div class='add'>+ * @value: value to write</div><div class='add'>+ * @group: the MCR group</div><div class='add'>+ * @instance: the MCR instance</div><div class='add'>+ *</div><div class='add'>+ * Write an MCR register in unicast mode after steering toward a specific</div><div class='add'>+ * group/instance.</div><div class='add'>+ */</div><div class='add'>+void xe_gt_mcr_unicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,</div><div class='add'>+			     u32 value, int group, int instance)</div><div class='add'>+{</div><div class='add'>+	mcr_lock(gt);</div><div class='add'>+	rw_with_mcr_steering(gt, reg_mcr, MCR_OP_WRITE, group, instance, value);</div><div class='add'>+	mcr_unlock(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_mcr_multicast_write - write a value to all instances of an MCR register</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @reg_mcr: the MCR register to write</div><div class='add'>+ * @value: value to write</div><div class='add'>+ *</div><div class='add'>+ * Write an MCR register in multicast mode to update all instances.</div><div class='add'>+ */</div><div class='add'>+void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,</div><div class='add'>+			       u32 value)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = to_xe_reg(reg_mcr);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Synchronize with any unicast operations.  Once we have exclusive</div><div class='add'>+	 * access, the MULTICAST bit should already be set, so there's no need</div><div class='add'>+	 * to touch the steering register.</div><div class='add'>+	 */</div><div class='add'>+	mcr_lock(gt);</div><div class='add'>+	xe_mmio_write32(gt, reg, value);</div><div class='add'>+	mcr_unlock(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	for (int i = 0; i &lt; NUM_STEERING_TYPES; i++) {</div><div class='add'>+		if (gt-&gt;steering[i].ranges) {</div><div class='add'>+			drm_printf(p, "%s steering: group=%#x, instance=%#x\n",</div><div class='add'>+				   xe_steering_types[i].name,</div><div class='add'>+				   gt-&gt;steering[i].group_target,</div><div class='add'>+				   gt-&gt;steering[i].instance_target);</div><div class='add'>+			for (int j = 0; gt-&gt;steering[i].ranges[j].end; j++)</div><div class='add'>+				drm_printf(p, "\t0x%06x - 0x%06x\n",</div><div class='add'>+					   gt-&gt;steering[i].ranges[j].start,</div><div class='add'>+					   gt-&gt;steering[i].ranges[j].end);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h<br/>new file mode 100644<br/>index 000000000000..27ca1bc880a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_mcr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_mcr.h</a></div><div class='hunk'>@@ -0,0 +1,29 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_MCR_H_</div><div class='add'>+#define _XE_GT_MCR_H_</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,</div><div class='add'>+			   int group, int instance);</div><div class='add'>+u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr mcr_reg);</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_unicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,</div><div class='add'>+			     u32 value, int group, int instance);</div><div class='add'>+void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,</div><div class='add'>+			       u32 value);</div><div class='add'>+</div><div class='add'>+void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_MCR_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c<br/>new file mode 100644<br/>index 000000000000..59a70d2e0a7a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_pagefault.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_pagefault.c</a></div><div class='hunk'>@@ -0,0 +1,646 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_pagefault.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/circ_buf.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_execbuf_util.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_pt.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+struct pagefault {</div><div class='add'>+	u64 page_addr;</div><div class='add'>+	u32 asid;</div><div class='add'>+	u16 pdata;</div><div class='add'>+	u8 vfid;</div><div class='add'>+	u8 access_type;</div><div class='add'>+	u8 fault_type;</div><div class='add'>+	u8 fault_level;</div><div class='add'>+	u8 engine_class;</div><div class='add'>+	u8 engine_instance;</div><div class='add'>+	u8 fault_unsuccessful;</div><div class='add'>+	bool trva_fault;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum access_type {</div><div class='add'>+	ACCESS_TYPE_READ = 0,</div><div class='add'>+	ACCESS_TYPE_WRITE = 1,</div><div class='add'>+	ACCESS_TYPE_ATOMIC = 2,</div><div class='add'>+	ACCESS_TYPE_RESERVED = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum fault_type {</div><div class='add'>+	NOT_PRESENT = 0,</div><div class='add'>+	WRITE_ACCESS_VIOLATION = 1,</div><div class='add'>+	ATOMIC_ACCESS_VIOLATION = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct acc {</div><div class='add'>+	u64 va_range_base;</div><div class='add'>+	u32 asid;</div><div class='add'>+	u32 sub_granularity;</div><div class='add'>+	u8 granularity;</div><div class='add'>+	u8 vfid;</div><div class='add'>+	u8 access_type;</div><div class='add'>+	u8 engine_class;</div><div class='add'>+	u8 engine_instance;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool access_is_atomic(enum access_type access_type)</div><div class='add'>+{</div><div class='add'>+	return access_type == ACCESS_TYPE_ATOMIC;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return BIT(tile-&gt;id) &amp; vma-&gt;tile_present &amp;&amp;</div><div class='add'>+		!(BIT(tile-&gt;id) &amp; vma-&gt;usm.tile_invalidated);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vma_matches(struct xe_vma *vma, u64 page_addr)</div><div class='add'>+{</div><div class='add'>+	if (page_addr &gt; xe_vma_end(vma) - 1 ||</div><div class='add'>+	    page_addr + SZ_4K - 1 &lt; xe_vma_start(vma))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_vma *lookup_vma(struct xe_vm *vm, u64 page_addr)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma = NULL;</div><div class='add'>+</div><div class='add'>+	if (vm-&gt;usm.last_fault_vma) {   /* Fast lookup */</div><div class='add'>+		if (vma_matches(vm-&gt;usm.last_fault_vma, page_addr))</div><div class='add'>+			vma = vm-&gt;usm.last_fault_vma;</div><div class='add'>+	}</div><div class='add'>+	if (!vma)</div><div class='add'>+		vma = xe_vm_find_overlapping_vma(vm, page_addr, SZ_4K);</div><div class='add'>+</div><div class='add'>+	return vma;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pf_begin(struct drm_exec *exec, struct xe_vma *vma,</div><div class='add'>+		       bool atomic, unsigned int id)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = xe_vma_bo(vma);</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	unsigned int num_shared = 2; /* slots for bind + move */</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_vm_prepare_vma(exec, vma, num_shared);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (atomic &amp;&amp; IS_DGFX(vm-&gt;xe)) {</div><div class='add'>+		if (xe_vma_is_userptr(vma)) {</div><div class='add'>+			err = -EACCES;</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Migrate to VRAM, move should invalidate the VMA first */</div><div class='add'>+		err = xe_bo_migrate(bo, XE_PL_VRAM0 + id);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	} else if (bo) {</div><div class='add'>+		/* Create backing store if needed */</div><div class='add'>+		err = xe_bo_validate(bo, vm, true);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	struct xe_vma *vma = NULL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	bool write_locked;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	bool atomic;</div><div class='add'>+</div><div class='add'>+	/* SW isn't expected to handle TRTT faults */</div><div class='add'>+	if (pf-&gt;trva_fault)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	/* ASID to VM */</div><div class='add'>+	mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	vm = xa_load(&amp;xe-&gt;usm.asid_to_vm, pf-&gt;asid);</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_get(vm);</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	if (!vm || !xe_vm_in_fault_mode(vm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+retry_userptr:</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: Avoid exclusive lock if VM doesn't have userptrs, or</div><div class='add'>+	 * start out read-locked?</div><div class='add'>+	 */</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	write_locked = true;</div><div class='add'>+	vma = lookup_vma(vm, pf-&gt;page_addr);</div><div class='add'>+	if (!vma) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto unlock_vm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe_vma_is_userptr(vma) || !xe_vma_userptr_check_repin(vma)) {</div><div class='add'>+		downgrade_write(&amp;vm-&gt;lock);</div><div class='add'>+		write_locked = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_vma_pagefault(vma);</div><div class='add'>+</div><div class='add'>+	atomic = access_is_atomic(pf-&gt;access_type);</div><div class='add'>+</div><div class='add'>+	/* Check if VMA is valid */</div><div class='add'>+	if (vma_is_valid(tile, vma) &amp;&amp; !atomic)</div><div class='add'>+		goto unlock_vm;</div><div class='add'>+</div><div class='add'>+	/* TODO: Validate fault */</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma) &amp;&amp; write_locked) {</div><div class='add'>+		spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		list_del_init(&amp;vma-&gt;userptr.invalidate_link);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+</div><div class='add'>+		ret = xe_vma_userptr_pin_pages(vma);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto unlock_vm;</div><div class='add'>+</div><div class='add'>+		downgrade_write(&amp;vm-&gt;lock);</div><div class='add'>+		write_locked = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Lock VM and BOs dma-resv */</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		ret = xe_pf_begin(&amp;exec, vma, atomic, tile-&gt;id);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto unlock_dma_resv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Bind VMA only to the GT that has faulted */</div><div class='add'>+	trace_xe_vma_pf_bind(vma);</div><div class='add'>+	fence = __xe_pt_bind_vma(tile, vma, xe_tile_migrate_engine(tile), NULL, 0,</div><div class='add'>+				 vma-&gt;tile_present &amp; BIT(tile-&gt;id));</div><div class='add'>+	if (IS_ERR(fence)) {</div><div class='add'>+		ret = PTR_ERR(fence);</div><div class='add'>+		goto unlock_dma_resv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * XXX: Should we drop the lock before waiting? This only helps if doing</div><div class='add'>+	 * GPU binds which is currently only done if we have to wait for more</div><div class='add'>+	 * than 10ms on a move.</div><div class='add'>+	 */</div><div class='add'>+	dma_fence_wait(fence, false);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma))</div><div class='add'>+		ret = xe_vma_userptr_check_repin(vma);</div><div class='add'>+	vma-&gt;usm.tile_invalidated &amp;= ~BIT(tile-&gt;id);</div><div class='add'>+</div><div class='add'>+unlock_dma_resv:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+unlock_vm:</div><div class='add'>+	if (!ret)</div><div class='add'>+		vm-&gt;usm.last_fault_vma = vma;</div><div class='add'>+	if (write_locked)</div><div class='add'>+		up_write(&amp;vm-&gt;lock);</div><div class='add'>+	else</div><div class='add'>+		up_read(&amp;vm-&gt;lock);</div><div class='add'>+	if (ret == -EAGAIN)</div><div class='add'>+		goto retry_userptr;</div><div class='add'>+</div><div class='add'>+	if (!ret) {</div><div class='add'>+		ret = xe_gt_tlb_invalidation_vma(gt, NULL, vma);</div><div class='add'>+		if (ret &gt;= 0)</div><div class='add'>+			ret = 0;</div><div class='add'>+	}</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int send_pagefault_reply(struct xe_guc *guc,</div><div class='add'>+				struct xe_guc_pagefault_reply *reply)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_PAGE_FAULT_RES_DESC,</div><div class='add'>+		reply-&gt;dw0,</div><div class='add'>+		reply-&gt;dw1,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return xe_guc_ct_send(&amp;guc-&gt;ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void print_pagefault(struct xe_device *xe, struct pagefault *pf)</div><div class='add'>+{</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "\n\tASID: %d\n"</div><div class='add'>+		 "\tVFID: %d\n"</div><div class='add'>+		 "\tPDATA: 0x%04x\n"</div><div class='add'>+		 "\tFaulted Address: 0x%08x%08x\n"</div><div class='add'>+		 "\tFaultType: %d\n"</div><div class='add'>+		 "\tAccessType: %d\n"</div><div class='add'>+		 "\tFaultLevel: %d\n"</div><div class='add'>+		 "\tEngineClass: %d\n"</div><div class='add'>+		 "\tEngineInstance: %d\n",</div><div class='add'>+		 pf-&gt;asid, pf-&gt;vfid, pf-&gt;pdata, upper_32_bits(pf-&gt;page_addr),</div><div class='add'>+		 lower_32_bits(pf-&gt;page_addr),</div><div class='add'>+		 pf-&gt;fault_type, pf-&gt;access_type, pf-&gt;fault_level,</div><div class='add'>+		 pf-&gt;engine_class, pf-&gt;engine_instance);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define PF_MSG_LEN_DW	4</div><div class='add'>+</div><div class='add'>+static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf)</div><div class='add'>+{</div><div class='add'>+	const struct xe_guc_pagefault_desc *desc;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;pf_queue-&gt;lock);</div><div class='add'>+	if (pf_queue-&gt;head != pf_queue-&gt;tail) {</div><div class='add'>+		desc = (const struct xe_guc_pagefault_desc *)</div><div class='add'>+			(pf_queue-&gt;data + pf_queue-&gt;head);</div><div class='add'>+</div><div class='add'>+		pf-&gt;fault_level = FIELD_GET(PFD_FAULT_LEVEL, desc-&gt;dw0);</div><div class='add'>+		pf-&gt;trva_fault = FIELD_GET(XE2_PFD_TRVA_FAULT, desc-&gt;dw0);</div><div class='add'>+		pf-&gt;engine_class = FIELD_GET(PFD_ENG_CLASS, desc-&gt;dw0);</div><div class='add'>+		pf-&gt;engine_instance = FIELD_GET(PFD_ENG_INSTANCE, desc-&gt;dw0);</div><div class='add'>+		pf-&gt;pdata = FIELD_GET(PFD_PDATA_HI, desc-&gt;dw1) &lt;&lt;</div><div class='add'>+			PFD_PDATA_HI_SHIFT;</div><div class='add'>+		pf-&gt;pdata |= FIELD_GET(PFD_PDATA_LO, desc-&gt;dw0);</div><div class='add'>+		pf-&gt;asid = FIELD_GET(PFD_ASID, desc-&gt;dw1);</div><div class='add'>+		pf-&gt;vfid = FIELD_GET(PFD_VFID, desc-&gt;dw2);</div><div class='add'>+		pf-&gt;access_type = FIELD_GET(PFD_ACCESS_TYPE, desc-&gt;dw2);</div><div class='add'>+		pf-&gt;fault_type = FIELD_GET(PFD_FAULT_TYPE, desc-&gt;dw2);</div><div class='add'>+		pf-&gt;page_addr = (u64)(FIELD_GET(PFD_VIRTUAL_ADDR_HI, desc-&gt;dw3)) &lt;&lt;</div><div class='add'>+			PFD_VIRTUAL_ADDR_HI_SHIFT;</div><div class='add'>+		pf-&gt;page_addr |= FIELD_GET(PFD_VIRTUAL_ADDR_LO, desc-&gt;dw2) &lt;&lt;</div><div class='add'>+			PFD_VIRTUAL_ADDR_LO_SHIFT;</div><div class='add'>+</div><div class='add'>+		pf_queue-&gt;head = (pf_queue-&gt;head + PF_MSG_LEN_DW) %</div><div class='add'>+			PF_QUEUE_NUM_DW;</div><div class='add'>+		ret = true;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irq(&amp;pf_queue-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool pf_queue_full(struct pf_queue *pf_queue)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;pf_queue-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return CIRC_SPACE(pf_queue-&gt;tail, pf_queue-&gt;head, PF_QUEUE_NUM_DW) &lt;=</div><div class='add'>+		PF_MSG_LEN_DW;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct pf_queue *pf_queue;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u32 asid;</div><div class='add'>+	bool full;</div><div class='add'>+</div><div class='add'>+	if (unlikely(len != PF_MSG_LEN_DW))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	asid = FIELD_GET(PFD_ASID, msg[1]);</div><div class='add'>+	pf_queue = &amp;gt-&gt;usm.pf_queue[asid % NUM_PF_QUEUE];</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;pf_queue-&gt;lock, flags);</div><div class='add'>+	full = pf_queue_full(pf_queue);</div><div class='add'>+	if (!full) {</div><div class='add'>+		memcpy(pf_queue-&gt;data + pf_queue-&gt;tail, msg, len * sizeof(u32));</div><div class='add'>+		pf_queue-&gt;tail = (pf_queue-&gt;tail + len) % PF_QUEUE_NUM_DW;</div><div class='add'>+		queue_work(gt-&gt;usm.pf_wq, &amp;pf_queue-&gt;worker);</div><div class='add'>+	} else {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "PF Queue full, shouldn't be possible");</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;pf_queue-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	return full ? -ENOSPC : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define USM_QUEUE_MAX_RUNTIME_MS	20</div><div class='add'>+</div><div class='add'>+static void pf_queue_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct pf_queue *pf_queue = container_of(w, struct pf_queue, worker);</div><div class='add'>+	struct xe_gt *gt = pf_queue-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_guc_pagefault_reply reply = {};</div><div class='add'>+	struct pagefault pf = {};</div><div class='add'>+	unsigned long threshold;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);</div><div class='add'>+</div><div class='add'>+	while (get_pagefault(pf_queue, &amp;pf)) {</div><div class='add'>+		ret = handle_pagefault(gt, &amp;pf);</div><div class='add'>+		if (unlikely(ret)) {</div><div class='add'>+			print_pagefault(xe, &amp;pf);</div><div class='add'>+			pf.fault_unsuccessful = 1;</div><div class='add'>+			drm_dbg(&amp;xe-&gt;drm, "Fault response: Unsuccessful %d\n", ret);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		reply.dw0 = FIELD_PREP(PFR_VALID, 1) |</div><div class='add'>+			FIELD_PREP(PFR_SUCCESS, pf.fault_unsuccessful) |</div><div class='add'>+			FIELD_PREP(PFR_REPLY, PFR_ACCESS) |</div><div class='add'>+			FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) |</div><div class='add'>+			FIELD_PREP(PFR_ASID, pf.asid);</div><div class='add'>+</div><div class='add'>+		reply.dw1 = FIELD_PREP(PFR_VFID, pf.vfid) |</div><div class='add'>+			FIELD_PREP(PFR_ENG_INSTANCE, pf.engine_instance) |</div><div class='add'>+			FIELD_PREP(PFR_ENG_CLASS, pf.engine_class) |</div><div class='add'>+			FIELD_PREP(PFR_PDATA, pf.pdata);</div><div class='add'>+</div><div class='add'>+		send_pagefault_reply(&amp;gt-&gt;uc.guc, &amp;reply);</div><div class='add'>+</div><div class='add'>+		if (time_after(jiffies, threshold) &amp;&amp;</div><div class='add'>+		    pf_queue-&gt;head != pf_queue-&gt;tail) {</div><div class='add'>+			queue_work(gt-&gt;usm.pf_wq, w);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void acc_queue_work_func(struct work_struct *w);</div><div class='add'>+</div><div class='add'>+int xe_gt_pagefault_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.has_usm)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_PF_QUEUE; ++i) {</div><div class='add'>+		gt-&gt;usm.pf_queue[i].gt = gt;</div><div class='add'>+		spin_lock_init(&amp;gt-&gt;usm.pf_queue[i].lock);</div><div class='add'>+		INIT_WORK(&amp;gt-&gt;usm.pf_queue[i].worker, pf_queue_work_func);</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; NUM_ACC_QUEUE; ++i) {</div><div class='add'>+		gt-&gt;usm.acc_queue[i].gt = gt;</div><div class='add'>+		spin_lock_init(&amp;gt-&gt;usm.acc_queue[i].lock);</div><div class='add'>+		INIT_WORK(&amp;gt-&gt;usm.acc_queue[i].worker, acc_queue_work_func);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt-&gt;usm.pf_wq = alloc_workqueue("xe_gt_page_fault_work_queue",</div><div class='add'>+					WQ_UNBOUND | WQ_HIGHPRI, NUM_PF_QUEUE);</div><div class='add'>+	if (!gt-&gt;usm.pf_wq)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	gt-&gt;usm.acc_wq = alloc_workqueue("xe_gt_access_counter_work_queue",</div><div class='add'>+					 WQ_UNBOUND | WQ_HIGHPRI,</div><div class='add'>+					 NUM_ACC_QUEUE);</div><div class='add'>+	if (!gt-&gt;usm.acc_wq)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_pagefault_reset(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.has_usm)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_PF_QUEUE; ++i) {</div><div class='add'>+		spin_lock_irq(&amp;gt-&gt;usm.pf_queue[i].lock);</div><div class='add'>+		gt-&gt;usm.pf_queue[i].head = 0;</div><div class='add'>+		gt-&gt;usm.pf_queue[i].tail = 0;</div><div class='add'>+		spin_unlock_irq(&amp;gt-&gt;usm.pf_queue[i].lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_ACC_QUEUE; ++i) {</div><div class='add'>+		spin_lock(&amp;gt-&gt;usm.acc_queue[i].lock);</div><div class='add'>+		gt-&gt;usm.acc_queue[i].head = 0;</div><div class='add'>+		gt-&gt;usm.acc_queue[i].tail = 0;</div><div class='add'>+		spin_unlock(&amp;gt-&gt;usm.acc_queue[i].lock);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int granularity_in_byte(int val)</div><div class='add'>+{</div><div class='add'>+	switch (val) {</div><div class='add'>+	case 0:</div><div class='add'>+		return SZ_128K;</div><div class='add'>+	case 1:</div><div class='add'>+		return SZ_2M;</div><div class='add'>+	case 2:</div><div class='add'>+		return SZ_16M;</div><div class='add'>+	case 3:</div><div class='add'>+		return SZ_64M;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sub_granularity_in_byte(int val)</div><div class='add'>+{</div><div class='add'>+	return (granularity_in_byte(val) / 32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void print_acc(struct xe_device *xe, struct acc *acc)</div><div class='add'>+{</div><div class='add'>+	drm_warn(&amp;xe-&gt;drm, "Access counter request:\n"</div><div class='add'>+		 "\tType: %s\n"</div><div class='add'>+		 "\tASID: %d\n"</div><div class='add'>+		 "\tVFID: %d\n"</div><div class='add'>+		 "\tEngine: %d:%d\n"</div><div class='add'>+		 "\tGranularity: 0x%x KB Region/ %d KB sub-granularity\n"</div><div class='add'>+		 "\tSub_Granularity Vector: 0x%08x\n"</div><div class='add'>+		 "\tVA Range base: 0x%016llx\n",</div><div class='add'>+		 acc-&gt;access_type ? "AC_NTFY_VAL" : "AC_TRIG_VAL",</div><div class='add'>+		 acc-&gt;asid, acc-&gt;vfid, acc-&gt;engine_class, acc-&gt;engine_instance,</div><div class='add'>+		 granularity_in_byte(acc-&gt;granularity) / SZ_1K,</div><div class='add'>+		 sub_granularity_in_byte(acc-&gt;granularity) / SZ_1K,</div><div class='add'>+		 acc-&gt;sub_granularity, acc-&gt;va_range_base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc)</div><div class='add'>+{</div><div class='add'>+	u64 page_va = acc-&gt;va_range_base + (ffs(acc-&gt;sub_granularity) - 1) *</div><div class='add'>+		sub_granularity_in_byte(acc-&gt;granularity);</div><div class='add'>+</div><div class='add'>+	return xe_vm_find_overlapping_vma(vm, page_va, SZ_4K);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int handle_acc(struct xe_gt *gt, struct acc *acc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* We only support ACC_TRIGGER at the moment */</div><div class='add'>+	if (acc-&gt;access_type != ACC_TRIGGER)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* ASID to VM */</div><div class='add'>+	mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	vm = xa_load(&amp;xe-&gt;usm.asid_to_vm, acc-&gt;asid);</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_get(vm);</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	if (!vm || !xe_vm_in_fault_mode(vm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	down_read(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Lookup VMA */</div><div class='add'>+	vma = get_acc_vma(vm, acc);</div><div class='add'>+	if (!vma) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto unlock_vm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_vma_acc(vma);</div><div class='add'>+</div><div class='add'>+	/* Userptr or null can't be migrated, nothing to do */</div><div class='add'>+	if (xe_vma_has_no_bo(vma))</div><div class='add'>+		goto unlock_vm;</div><div class='add'>+</div><div class='add'>+	/* Lock VM and BOs dma-resv */</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		ret = xe_pf_begin(&amp;exec, vma, true, tile-&gt;id);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+unlock_vm:</div><div class='add'>+	up_read(&amp;vm-&gt;lock);</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define make_u64(hi__, low__)  ((u64)(hi__) &lt;&lt; 32 | (u64)(low__))</div><div class='add'>+</div><div class='add'>+#define ACC_MSG_LEN_DW        4</div><div class='add'>+</div><div class='add'>+static bool get_acc(struct acc_queue *acc_queue, struct acc *acc)</div><div class='add'>+{</div><div class='add'>+	const struct xe_guc_acc_desc *desc;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;acc_queue-&gt;lock);</div><div class='add'>+	if (acc_queue-&gt;head != acc_queue-&gt;tail) {</div><div class='add'>+		desc = (const struct xe_guc_acc_desc *)</div><div class='add'>+			(acc_queue-&gt;data + acc_queue-&gt;head);</div><div class='add'>+</div><div class='add'>+		acc-&gt;granularity = FIELD_GET(ACC_GRANULARITY, desc-&gt;dw2);</div><div class='add'>+		acc-&gt;sub_granularity = FIELD_GET(ACC_SUBG_HI, desc-&gt;dw1) &lt;&lt; 31 |</div><div class='add'>+			FIELD_GET(ACC_SUBG_LO, desc-&gt;dw0);</div><div class='add'>+		acc-&gt;engine_class = FIELD_GET(ACC_ENG_CLASS, desc-&gt;dw1);</div><div class='add'>+		acc-&gt;engine_instance = FIELD_GET(ACC_ENG_INSTANCE, desc-&gt;dw1);</div><div class='add'>+		acc-&gt;asid =  FIELD_GET(ACC_ASID, desc-&gt;dw1);</div><div class='add'>+		acc-&gt;vfid =  FIELD_GET(ACC_VFID, desc-&gt;dw2);</div><div class='add'>+		acc-&gt;access_type = FIELD_GET(ACC_TYPE, desc-&gt;dw0);</div><div class='add'>+		acc-&gt;va_range_base = make_u64(desc-&gt;dw3 &amp; ACC_VIRTUAL_ADDR_RANGE_HI,</div><div class='add'>+					      desc-&gt;dw2 &amp; ACC_VIRTUAL_ADDR_RANGE_LO);</div><div class='add'>+</div><div class='add'>+		acc_queue-&gt;head = (acc_queue-&gt;head + ACC_MSG_LEN_DW) %</div><div class='add'>+				  ACC_QUEUE_NUM_DW;</div><div class='add'>+		ret = true;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;acc_queue-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void acc_queue_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct acc_queue *acc_queue = container_of(w, struct acc_queue, worker);</div><div class='add'>+	struct xe_gt *gt = acc_queue-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct acc acc = {};</div><div class='add'>+	unsigned long threshold;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);</div><div class='add'>+</div><div class='add'>+	while (get_acc(acc_queue, &amp;acc)) {</div><div class='add'>+		ret = handle_acc(gt, &amp;acc);</div><div class='add'>+		if (unlikely(ret)) {</div><div class='add'>+			print_acc(xe, &amp;acc);</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm, "ACC: Unsuccessful %d\n", ret);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (time_after(jiffies, threshold) &amp;&amp;</div><div class='add'>+		    acc_queue-&gt;head != acc_queue-&gt;tail) {</div><div class='add'>+			queue_work(gt-&gt;usm.acc_wq, w);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool acc_queue_full(struct acc_queue *acc_queue)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;acc_queue-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return CIRC_SPACE(acc_queue-&gt;tail, acc_queue-&gt;head, ACC_QUEUE_NUM_DW) &lt;=</div><div class='add'>+		ACC_MSG_LEN_DW;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	struct acc_queue *acc_queue;</div><div class='add'>+	u32 asid;</div><div class='add'>+	bool full;</div><div class='add'>+</div><div class='add'>+	if (unlikely(len != ACC_MSG_LEN_DW))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	asid = FIELD_GET(ACC_ASID, msg[1]);</div><div class='add'>+	acc_queue = &amp;gt-&gt;usm.acc_queue[asid % NUM_ACC_QUEUE];</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;acc_queue-&gt;lock);</div><div class='add'>+	full = acc_queue_full(acc_queue);</div><div class='add'>+	if (!full) {</div><div class='add'>+		memcpy(acc_queue-&gt;data + acc_queue-&gt;tail, msg,</div><div class='add'>+		       len * sizeof(u32));</div><div class='add'>+		acc_queue-&gt;tail = (acc_queue-&gt;tail + len) % ACC_QUEUE_NUM_DW;</div><div class='add'>+		queue_work(gt-&gt;usm.acc_wq, &amp;acc_queue-&gt;worker);</div><div class='add'>+	} else {</div><div class='add'>+		drm_warn(&amp;gt_to_xe(gt)-&gt;drm, "ACC Queue full, dropping ACC");</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;acc_queue-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return full ? -ENOSPC : 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.h b/drivers/gpu/drm/xe/xe_gt_pagefault.h<br/>new file mode 100644<br/>index 000000000000..839c065a5e4c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_pagefault.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_pagefault.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_PAGEFAULT_H_</div><div class='add'>+#define _XE_GT_PAGEFAULT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_guc;</div><div class='add'>+</div><div class='add'>+int xe_gt_pagefault_init(struct xe_gt *gt);</div><div class='add'>+void xe_gt_pagefault_reset(struct xe_gt *gt);</div><div class='add'>+int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+</div><div class='add'>+#endif	/* _XE_GT_PAGEFAULT_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h<br/>new file mode 100644<br/>index 000000000000..5991bcadd47e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_printk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_printk.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_PRINTK_H_</div><div class='add'>+#define _XE_GT_PRINTK_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+</div><div class='add'>+#define xe_gt_printk(_gt, _level, _fmt, ...) \</div><div class='add'>+	drm_##_level(&amp;gt_to_xe(_gt)-&gt;drm, "GT%u: " _fmt, (_gt)-&gt;info.id, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_err(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_warn(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), warn, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_notice(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), notice, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_info(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), info, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_dbg(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), dbg, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_err_ratelimited(_gt, _fmt, ...) \</div><div class='add'>+	xe_gt_printk((_gt), err_ratelimited, _fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_WARN(_gt, _condition, _fmt, ...) \</div><div class='add'>+	drm_WARN(&amp;gt_to_xe(_gt)-&gt;drm, _condition, "GT%u: " _fmt, (_gt)-&gt;info.id, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_WARN_ONCE(_gt, _condition, _fmt, ...) \</div><div class='add'>+	drm_WARN_ONCE(&amp;gt_to_xe(_gt)-&gt;drm, _condition, "GT%u: " _fmt, (_gt)-&gt;info.id, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_gt_WARN_ON(_gt, _condition) \</div><div class='add'>+	xe_gt_WARN((_gt), _condition, "%s(%s)", "gt_WARN_ON", __stringify(_condition))</div><div class='add'>+</div><div class='add'>+#define xe_gt_WARN_ON_ONCE(_gt, _condition) \</div><div class='add'>+	xe_gt_WARN_ONCE((_gt), _condition, "%s(%s)", "gt_WARN_ON_ONCE", __stringify(_condition))</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_sysfs.c b/drivers/gpu/drm/xe/xe_gt_sysfs.c<br/>new file mode 100644<br/>index 000000000000..c69d2e8a0fe1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs.c</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+</div><div class='add'>+static void xe_gt_sysfs_kobj_release(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	kfree(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xe_gt_sysfs_kobj_type = {</div><div class='add'>+	.release = xe_gt_sysfs_kobj_release,</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gt_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = arg;</div><div class='add'>+</div><div class='add'>+	kobject_put(gt-&gt;sysfs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_sysfs_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct kobj_gt *kg;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	kg = kzalloc(sizeof(*kg), GFP_KERNEL);</div><div class='add'>+	if (!kg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kobject_init(&amp;kg-&gt;base, &amp;xe_gt_sysfs_kobj_type);</div><div class='add'>+	kg-&gt;gt = gt;</div><div class='add'>+</div><div class='add'>+	err = kobject_add(&amp;kg-&gt;base, tile-&gt;sysfs, "gt%d", gt-&gt;info.id);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "failed to add GT sysfs directory, err: %d\n", err);</div><div class='add'>+		kobject_put(&amp;kg-&gt;base);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt-&gt;sysfs = &amp;kg-&gt;base;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, gt_sysfs_fini, gt);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_sysfs.h b/drivers/gpu/drm/xe/xe_gt_sysfs.h<br/>new file mode 100644<br/>index 000000000000..e3ec278ca0be<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_SYSFS_H_</div><div class='add'>+#define _XE_GT_SYSFS_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gt_sysfs_types.h"</div><div class='add'>+</div><div class='add'>+void xe_gt_sysfs_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *</div><div class='add'>+kobj_to_gt(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	return container_of(kobj, struct kobj_gt, base)-&gt;gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_SYSFS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_sysfs_types.h b/drivers/gpu/drm/xe/xe_gt_sysfs_types.h<br/>new file mode 100644<br/>index 000000000000..d3bc6b83360f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_sysfs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_sysfs_types.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_SYSFS_TYPES_H_</div><div class='add'>+#define _XE_GT_SYSFS_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct kobj_gt - A GT's kobject struct that connects the kobject and the GT</div><div class='add'>+ *</div><div class='add'>+ * When dealing with multiple GTs, this struct helps to understand which GT</div><div class='add'>+ * needs to be addressed on a given sysfs call.</div><div class='add'>+ */</div><div class='add'>+struct kobj_gt {</div><div class='add'>+	/** @base: The actual kobject */</div><div class='add'>+	struct kobject base;</div><div class='add'>+	/** @gt: A pointer to the GT itself */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif	/* _XE_GT_SYSFS_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c b/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c<br/>new file mode 100644<br/>index 000000000000..63d640591a52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_throttle_sysfs.c</a></div><div class='hunk'>@@ -0,0 +1,251 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;regs/xe_gt_regs.h&gt;</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_gt_throttle_sysfs.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe GT Throttle</div><div class='add'>+ *</div><div class='add'>+ * Provides sysfs entries for frequency throttle reasons in GT</div><div class='add'>+ *</div><div class='add'>+ * device/gt#/freq0/throttle/status - Overall status</div><div class='add'>+ * device/gt#/freq0/throttle/reason_pl1 - Frequency throttle due to PL1</div><div class='add'>+ * device/gt#/freq0/throttle/reason_pl2 - Frequency throttle due to PL2</div><div class='add'>+ * device/gt#/freq0/throttle/reason_pl4 - Frequency throttle due to PL4, Iccmax etc.</div><div class='add'>+ * device/gt#/freq0/throttle/reason_thermal - Frequency throttle due to thermal</div><div class='add'>+ * device/gt#/freq0/throttle/reason_prochot - Frequency throttle due to prochot</div><div class='add'>+ * device/gt#/freq0/throttle/reason_ratl - Frequency throttle due to RATL</div><div class='add'>+ * device/gt#/freq0/throttle/reason_vr_thermalert - Frequency throttle due to VR THERMALERT</div><div class='add'>+ * device/gt#/freq0/throttle/reason_vr_tdc -  Frequency throttle due to VR TDC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+dev_to_gt(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	return kobj_to_gt(dev-&gt;kobj.parent);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_perf_limit_reasons(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_MEDIA_PERF_LIMIT_REASONS);</div><div class='add'>+	else</div><div class='add'>+		reg = xe_mmio_read32(gt, GT0_PERF_LIMIT_REASONS);</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_status(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 status = read_perf_limit_reasons(gt) &amp; GT0_PERF_LIMIT_REASONS_MASK;</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_pl1(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 pl1 = read_perf_limit_reasons(gt) &amp; POWER_LIMIT_1_MASK;</div><div class='add'>+</div><div class='add'>+	return pl1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_pl2(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 pl2 = read_perf_limit_reasons(gt) &amp; POWER_LIMIT_2_MASK;</div><div class='add'>+</div><div class='add'>+	return pl2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_pl4(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 pl4 = read_perf_limit_reasons(gt) &amp; POWER_LIMIT_4_MASK;</div><div class='add'>+</div><div class='add'>+	return pl4;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_thermal(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 thermal = read_perf_limit_reasons(gt) &amp; THERMAL_LIMIT_MASK;</div><div class='add'>+</div><div class='add'>+	return thermal;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_prochot(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 prochot = read_perf_limit_reasons(gt) &amp; PROCHOT_MASK;</div><div class='add'>+</div><div class='add'>+	return prochot;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_ratl(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 ratl = read_perf_limit_reasons(gt) &amp; RATL_MASK;</div><div class='add'>+</div><div class='add'>+	return ratl;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_vr_thermalert(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 thermalert = read_perf_limit_reasons(gt) &amp; VR_THERMALERT_MASK;</div><div class='add'>+</div><div class='add'>+	return thermalert;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 read_reason_vr_tdc(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 tdc = read_perf_limit_reasons(gt) &amp; VR_TDC_MASK;</div><div class='add'>+</div><div class='add'>+	return tdc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t status_show(struct device *dev,</div><div class='add'>+			   struct device_attribute *attr,</div><div class='add'>+			   char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool status = !!read_status(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", status);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(status);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_pl1_show(struct device *dev,</div><div class='add'>+			       struct device_attribute *attr,</div><div class='add'>+			       char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool pl1 = !!read_reason_pl1(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", pl1);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_pl1);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_pl2_show(struct device *dev,</div><div class='add'>+			       struct device_attribute *attr,</div><div class='add'>+			       char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool pl2 = !!read_reason_pl2(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", pl2);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_pl2);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_pl4_show(struct device *dev,</div><div class='add'>+			       struct device_attribute *attr,</div><div class='add'>+			       char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool pl4 = !!read_reason_pl4(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", pl4);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_pl4);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_thermal_show(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr,</div><div class='add'>+				   char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool thermal = !!read_reason_thermal(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", thermal);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_thermal);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_prochot_show(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr,</div><div class='add'>+				   char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool prochot = !!read_reason_prochot(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", prochot);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_prochot);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_ratl_show(struct device *dev,</div><div class='add'>+				struct device_attribute *attr,</div><div class='add'>+				char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool ratl = !!read_reason_ratl(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", ratl);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_ratl);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_vr_thermalert_show(struct device *dev,</div><div class='add'>+					 struct device_attribute *attr,</div><div class='add'>+					 char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool thermalert = !!read_reason_vr_thermalert(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", thermalert);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_vr_thermalert);</div><div class='add'>+</div><div class='add'>+static ssize_t reason_vr_tdc_show(struct device *dev,</div><div class='add'>+				  struct device_attribute *attr,</div><div class='add'>+				  char *buff)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = dev_to_gt(dev);</div><div class='add'>+	bool tdc = !!read_reason_vr_tdc(gt);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buff, "%u\n", tdc);</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(reason_vr_tdc);</div><div class='add'>+</div><div class='add'>+static struct attribute *throttle_attrs[] = {</div><div class='add'>+	&amp;dev_attr_status.attr,</div><div class='add'>+	&amp;dev_attr_reason_pl1.attr,</div><div class='add'>+	&amp;dev_attr_reason_pl2.attr,</div><div class='add'>+	&amp;dev_attr_reason_pl4.attr,</div><div class='add'>+	&amp;dev_attr_reason_thermal.attr,</div><div class='add'>+	&amp;dev_attr_reason_prochot.attr,</div><div class='add'>+	&amp;dev_attr_reason_ratl.attr,</div><div class='add'>+	&amp;dev_attr_reason_vr_thermalert.attr,</div><div class='add'>+	&amp;dev_attr_reason_vr_tdc.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute_group throttle_group_attrs = {</div><div class='add'>+	.name = "throttle",</div><div class='add'>+	.attrs = throttle_attrs,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void gt_throttle_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_group(gt-&gt;freq, &amp;throttle_group_attrs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_gt_throttle_sysfs_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = sysfs_create_group(gt-&gt;freq, &amp;throttle_group_attrs);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "failed to register throttle sysfs, err: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, gt_throttle_sysfs_fini, gt);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h b/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h<br/>new file mode 100644<br/>index 000000000000..3ecfd4beffe1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_throttle_sysfs.h</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_THROTTLE_SYSFS_H_</div><div class='add'>+#define _XE_GT_THROTTLE_SYSFS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_gt_throttle_sysfs_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_THROTTLE_SYSFS_H_ */</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c<br/>new file mode 100644<br/>index 000000000000..7eef23a00d77<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c</a></div><div class='hunk'>@@ -0,0 +1,406 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+</div><div class='add'>+#define TLB_TIMEOUT	(HZ / 4)</div><div class='add'>+</div><div class='add'>+static void xe_gt_tlb_fence_timeout(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = container_of(work, struct xe_gt,</div><div class='add'>+					tlb_invalidation.fence_tdr.work);</div><div class='add'>+	struct xe_gt_tlb_invalidation_fence *fence, *next;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+	list_for_each_entry_safe(fence, next,</div><div class='add'>+				 &amp;gt-&gt;tlb_invalidation.pending_fences, link) {</div><div class='add'>+		s64 since_inval_ms = ktime_ms_delta(ktime_get(),</div><div class='add'>+						    fence-&gt;invalidation_time);</div><div class='add'>+</div><div class='add'>+		if (msecs_to_jiffies(since_inval_ms) &lt; TLB_TIMEOUT)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		trace_xe_gt_tlb_invalidation_fence_timeout(fence);</div><div class='add'>+		drm_err(&amp;gt_to_xe(gt)-&gt;drm, "gt%d: TLB invalidation fence timeout, seqno=%d recv=%d",</div><div class='add'>+			gt-&gt;info.id, fence-&gt;seqno, gt-&gt;tlb_invalidation.seqno_recv);</div><div class='add'>+</div><div class='add'>+		list_del(&amp;fence-&gt;link);</div><div class='add'>+		fence-&gt;base.error = -ETIME;</div><div class='add'>+		dma_fence_signal(&amp;fence-&gt;base);</div><div class='add'>+		dma_fence_put(&amp;fence-&gt;base);</div><div class='add'>+	}</div><div class='add'>+	if (!list_empty(&amp;gt-&gt;tlb_invalidation.pending_fences))</div><div class='add'>+		queue_delayed_work(system_wq,</div><div class='add'>+				   &amp;gt-&gt;tlb_invalidation.fence_tdr,</div><div class='add'>+				   TLB_TIMEOUT);</div><div class='add'>+	spin_unlock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_tlb_invalidation_init - Initialize GT TLB invalidation state</div><div class='add'>+ * @gt: graphics tile</div><div class='add'>+ *</div><div class='add'>+ * Initialize GT TLB invalidation state, purely software initialization, should</div><div class='add'>+ * be called once during driver load.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_gt_tlb_invalidation_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	gt-&gt;tlb_invalidation.seqno = 1;</div><div class='add'>+	INIT_LIST_HEAD(&amp;gt-&gt;tlb_invalidation.pending_fences);</div><div class='add'>+	spin_lock_init(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+	spin_lock_init(&amp;gt-&gt;tlb_invalidation.lock);</div><div class='add'>+	gt-&gt;tlb_invalidation.fence_context = dma_fence_context_alloc(1);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;gt-&gt;tlb_invalidation.fence_tdr,</div><div class='add'>+			  xe_gt_tlb_fence_timeout);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+__invalidation_fence_signal(struct xe_gt_tlb_invalidation_fence *fence)</div><div class='add'>+{</div><div class='add'>+	trace_xe_gt_tlb_invalidation_fence_signal(fence);</div><div class='add'>+	dma_fence_signal(&amp;fence-&gt;base);</div><div class='add'>+	dma_fence_put(&amp;fence-&gt;base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+invalidation_fence_signal(struct xe_gt_tlb_invalidation_fence *fence)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;fence-&gt;link);</div><div class='add'>+	__invalidation_fence_signal(fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_tlb_invalidation_reset - Initialize GT TLB invalidation reset</div><div class='add'>+ * @gt: graphics tile</div><div class='add'>+ *</div><div class='add'>+ * Signal any pending invalidation fences, should be called during a GT reset</div><div class='add'>+ */</div><div class='add'>+void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt_tlb_invalidation_fence *fence, *next;</div><div class='add'>+	struct xe_guc *guc = &amp;gt-&gt;uc.guc;</div><div class='add'>+	int pending_seqno;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * CT channel is already disabled at this point. No new TLB requests can</div><div class='add'>+	 * appear.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;uc.guc.ct.lock);</div><div class='add'>+	spin_lock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+	cancel_delayed_work(&amp;gt-&gt;tlb_invalidation.fence_tdr);</div><div class='add'>+	/*</div><div class='add'>+	 * We might have various kworkers waiting for TLB flushes to complete</div><div class='add'>+	 * which are not tracked with an explicit TLB fence, however at this</div><div class='add'>+	 * stage that will never happen since the CT is already disabled, so</div><div class='add'>+	 * make sure we signal them here under the assumption that we have</div><div class='add'>+	 * completed a full GT reset.</div><div class='add'>+	 */</div><div class='add'>+	if (gt-&gt;tlb_invalidation.seqno == 1)</div><div class='add'>+		pending_seqno = TLB_INVALIDATION_SEQNO_MAX - 1;</div><div class='add'>+	else</div><div class='add'>+		pending_seqno = gt-&gt;tlb_invalidation.seqno - 1;</div><div class='add'>+	WRITE_ONCE(gt-&gt;tlb_invalidation.seqno_recv, pending_seqno);</div><div class='add'>+	wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(fence, next,</div><div class='add'>+				 &amp;gt-&gt;tlb_invalidation.pending_fences, link)</div><div class='add'>+		invalidation_fence_signal(fence);</div><div class='add'>+	spin_unlock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;uc.guc.ct.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool tlb_invalidation_seqno_past(struct xe_gt *gt, int seqno)</div><div class='add'>+{</div><div class='add'>+	int seqno_recv = READ_ONCE(gt-&gt;tlb_invalidation.seqno_recv);</div><div class='add'>+</div><div class='add'>+	if (seqno - seqno_recv &lt; -(TLB_INVALIDATION_SEQNO_MAX / 2))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (seqno - seqno_recv &gt; (TLB_INVALIDATION_SEQNO_MAX / 2))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return seqno_recv &gt;= seqno;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int send_tlb_invalidation(struct xe_guc *guc,</div><div class='add'>+				 struct xe_gt_tlb_invalidation_fence *fence,</div><div class='add'>+				 u32 *action, int len)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	int seqno;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * XXX: The seqno algorithm relies on TLB invalidation being processed</div><div class='add'>+	 * in order which they currently are, if that changes the algorithm will</div><div class='add'>+	 * need to be updated.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;ct.lock);</div><div class='add'>+	seqno = gt-&gt;tlb_invalidation.seqno;</div><div class='add'>+	if (fence) {</div><div class='add'>+		fence-&gt;seqno = seqno;</div><div class='add'>+		trace_xe_gt_tlb_invalidation_fence_send(fence);</div><div class='add'>+	}</div><div class='add'>+	action[1] = seqno;</div><div class='add'>+	ret = xe_guc_ct_send_locked(&amp;guc-&gt;ct, action, len,</div><div class='add'>+				    G2H_LEN_DW_TLB_INVALIDATE, 1);</div><div class='add'>+	if (!ret &amp;&amp; fence) {</div><div class='add'>+		spin_lock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+		/*</div><div class='add'>+		 * We haven't actually published the TLB fence as per</div><div class='add'>+		 * pending_fences, but in theory our seqno could have already</div><div class='add'>+		 * been written as we acquired the pending_lock. In such a case</div><div class='add'>+		 * we can just go ahead and signal the fence here.</div><div class='add'>+		 */</div><div class='add'>+		if (tlb_invalidation_seqno_past(gt, seqno)) {</div><div class='add'>+			__invalidation_fence_signal(fence);</div><div class='add'>+		} else {</div><div class='add'>+			fence-&gt;invalidation_time = ktime_get();</div><div class='add'>+			list_add_tail(&amp;fence-&gt;link,</div><div class='add'>+				      &amp;gt-&gt;tlb_invalidation.pending_fences);</div><div class='add'>+</div><div class='add'>+			if (list_is_singular(&amp;gt-&gt;tlb_invalidation.pending_fences))</div><div class='add'>+				queue_delayed_work(system_wq,</div><div class='add'>+						   &amp;gt-&gt;tlb_invalidation.fence_tdr,</div><div class='add'>+						   TLB_TIMEOUT);</div><div class='add'>+		}</div><div class='add'>+		spin_unlock_irq(&amp;gt-&gt;tlb_invalidation.pending_lock);</div><div class='add'>+	} else if (ret &lt; 0 &amp;&amp; fence) {</div><div class='add'>+		__invalidation_fence_signal(fence);</div><div class='add'>+	}</div><div class='add'>+	if (!ret) {</div><div class='add'>+		gt-&gt;tlb_invalidation.seqno = (gt-&gt;tlb_invalidation.seqno + 1) %</div><div class='add'>+			TLB_INVALIDATION_SEQNO_MAX;</div><div class='add'>+		if (!gt-&gt;tlb_invalidation.seqno)</div><div class='add'>+			gt-&gt;tlb_invalidation.seqno = 1;</div><div class='add'>+		ret = seqno;</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;ct.lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MAKE_INVAL_OP(type)	((type &lt;&lt; XE_GUC_TLB_INVAL_TYPE_SHIFT) | \</div><div class='add'>+		XE_GUC_TLB_INVAL_MODE_HEAVY &lt;&lt; XE_GUC_TLB_INVAL_MODE_SHIFT | \</div><div class='add'>+		XE_GUC_TLB_INVAL_FLUSH_CACHE)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_tlb_invalidation_guc - Issue a TLB invalidation on this GT for the GuC</div><div class='add'>+ * @gt: graphics tile</div><div class='add'>+ *</div><div class='add'>+ * Issue a TLB invalidation for the GuC. Completion of TLB is asynchronous and</div><div class='add'>+ * caller can use seqno + xe_gt_tlb_invalidation_wait to wait for completion.</div><div class='add'>+ *</div><div class='add'>+ * Return: Seqno which can be passed to xe_gt_tlb_invalidation_wait on success,</div><div class='add'>+ * negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_gt_tlb_invalidation_guc(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_TLB_INVALIDATION,</div><div class='add'>+		0,  /* seqno, replaced in send_tlb_invalidation */</div><div class='add'>+		MAKE_INVAL_OP(XE_GUC_TLB_INVAL_GUC),</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return send_tlb_invalidation(&amp;gt-&gt;uc.guc, NULL, action,</div><div class='add'>+				     ARRAY_SIZE(action));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_tlb_invalidation_vma - Issue a TLB invalidation on this GT for a VMA</div><div class='add'>+ * @gt: graphics tile</div><div class='add'>+ * @fence: invalidation fence which will be signal on TLB invalidation</div><div class='add'>+ * completion, can be NULL</div><div class='add'>+ * @vma: VMA to invalidate</div><div class='add'>+ *</div><div class='add'>+ * Issue a range based TLB invalidation if supported, if not fallback to a full</div><div class='add'>+ * TLB invalidation. Completion of TLB is asynchronous and caller can either use</div><div class='add'>+ * the invalidation fence or seqno + xe_gt_tlb_invalidation_wait to wait for</div><div class='add'>+ * completion.</div><div class='add'>+ *</div><div class='add'>+ * Return: Seqno which can be passed to xe_gt_tlb_invalidation_wait on success,</div><div class='add'>+ * negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_gt_tlb_invalidation_vma(struct xe_gt *gt,</div><div class='add'>+			       struct xe_gt_tlb_invalidation_fence *fence,</div><div class='add'>+			       struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+#define MAX_TLB_INVALIDATION_LEN	7</div><div class='add'>+	u32 action[MAX_TLB_INVALIDATION_LEN];</div><div class='add'>+	int len = 0;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, vma);</div><div class='add'>+</div><div class='add'>+	action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;</div><div class='add'>+	action[len++] = 0; /* seqno, replaced in send_tlb_invalidation */</div><div class='add'>+	if (!xe-&gt;info.has_range_tlb_invalidation) {</div><div class='add'>+		action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);</div><div class='add'>+	} else {</div><div class='add'>+		u64 start = xe_vma_start(vma);</div><div class='add'>+		u64 length = xe_vma_size(vma);</div><div class='add'>+		u64 align, end;</div><div class='add'>+</div><div class='add'>+		if (length &lt; SZ_4K)</div><div class='add'>+			length = SZ_4K;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * We need to invalidate a higher granularity if start address</div><div class='add'>+		 * is not aligned to length. When start is not aligned with</div><div class='add'>+		 * length we need to find the length large enough to create an</div><div class='add'>+		 * address mask covering the required range.</div><div class='add'>+		 */</div><div class='add'>+		align = roundup_pow_of_two(length);</div><div class='add'>+		start = ALIGN_DOWN(xe_vma_start(vma), align);</div><div class='add'>+		end = ALIGN(xe_vma_end(vma), align);</div><div class='add'>+		length = align;</div><div class='add'>+		while (start + length &lt; end) {</div><div class='add'>+			length &lt;&lt;= 1;</div><div class='add'>+			start = ALIGN_DOWN(xe_vma_start(vma), length);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Minimum invalidation size for a 2MB page that the hardware</div><div class='add'>+		 * expects is 16MB</div><div class='add'>+		 */</div><div class='add'>+		if (length &gt;= SZ_2M) {</div><div class='add'>+			length = max_t(u64, SZ_16M, length);</div><div class='add'>+			start = ALIGN_DOWN(xe_vma_start(vma), length);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_gt_assert(gt, length &gt;= SZ_4K);</div><div class='add'>+		xe_gt_assert(gt, is_power_of_2(length));</div><div class='add'>+		xe_gt_assert(gt, !(length &amp; GENMASK(ilog2(SZ_16M) - 1, ilog2(SZ_2M) + 1)));</div><div class='add'>+		xe_gt_assert(gt, IS_ALIGNED(start, length));</div><div class='add'>+</div><div class='add'>+		action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);</div><div class='add'>+		action[len++] = xe_vma_vm(vma)-&gt;usm.asid;</div><div class='add'>+		action[len++] = lower_32_bits(start);</div><div class='add'>+		action[len++] = upper_32_bits(start);</div><div class='add'>+		action[len++] = ilog2(length) - ilog2(SZ_4K);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, len &lt;= MAX_TLB_INVALIDATION_LEN);</div><div class='add'>+</div><div class='add'>+	return send_tlb_invalidation(&amp;gt-&gt;uc.guc, fence, action, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_tlb_invalidation_wait - Wait for TLB to complete</div><div class='add'>+ * @gt: graphics tile</div><div class='add'>+ * @seqno: seqno to wait which was returned from xe_gt_tlb_invalidation</div><div class='add'>+ *</div><div class='add'>+ * Wait for 200ms for a TLB invalidation to complete, in practice we always</div><div class='add'>+ * should receive the TLB invalidation within 200ms.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, -ETIME on TLB invalidation timeout</div><div class='add'>+ */</div><div class='add'>+int xe_gt_tlb_invalidation_wait(struct xe_gt *gt, int seqno)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_guc *guc = &amp;gt-&gt;uc.guc;</div><div class='add'>+	struct drm_printer p = drm_err_printer(__func__);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * XXX: See above, this algorithm only works if seqno are always in</div><div class='add'>+	 * order</div><div class='add'>+	 */</div><div class='add'>+	ret = wait_event_timeout(guc-&gt;ct.wq,</div><div class='add'>+				 tlb_invalidation_seqno_past(gt, seqno),</div><div class='add'>+				 TLB_TIMEOUT);</div><div class='add'>+	if (!ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "gt%d: TLB invalidation time'd out, seqno=%d, recv=%d\n",</div><div class='add'>+			gt-&gt;info.id, seqno, gt-&gt;tlb_invalidation.seqno_recv);</div><div class='add'>+		xe_guc_ct_print(&amp;guc-&gt;ct, &amp;p, true);</div><div class='add'>+		return -ETIME;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_tlb_invalidation_done_handler - TLB invalidation done handler</div><div class='add'>+ * @guc: guc</div><div class='add'>+ * @msg: message indicating TLB invalidation done</div><div class='add'>+ * @len: length of message</div><div class='add'>+ *</div><div class='add'>+ * Parse seqno of TLB invalidation, wake any waiters for seqno, and signal any</div><div class='add'>+ * invalidation fences for seqno. Algorithm for this depends on seqno being</div><div class='add'>+ * received in-order and asserts this assumption.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, -EPROTO for malformed messages.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	struct xe_gt_tlb_invalidation_fence *fence, *next;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	if (unlikely(len != 1))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This can also be run both directly from the IRQ handler and also in</div><div class='add'>+	 * process_g2h_msg(). Only one may process any individual CT message,</div><div class='add'>+	 * however the order they are processed here could result in skipping a</div><div class='add'>+	 * seqno. To handle that we just process all the seqnos from the last</div><div class='add'>+	 * seqno_recv up to and including the one in msg[0]. The delta should be</div><div class='add'>+	 * very small so there shouldn't be much of pending_fences we actually</div><div class='add'>+	 * need to iterate over here.</div><div class='add'>+	 *</div><div class='add'>+	 * From GuC POV we expect the seqnos to always appear in-order, so if we</div><div class='add'>+	 * see something later in the timeline we can be sure that anything</div><div class='add'>+	 * appearing earlier has already signalled, just that we have yet to</div><div class='add'>+	 * officially process the CT message like if racing against</div><div class='add'>+	 * process_g2h_msg().</div><div class='add'>+	 */</div><div class='add'>+	spin_lock_irqsave(&amp;gt-&gt;tlb_invalidation.pending_lock, flags);</div><div class='add'>+	if (tlb_invalidation_seqno_past(gt, msg[0])) {</div><div class='add'>+		spin_unlock_irqrestore(&amp;gt-&gt;tlb_invalidation.pending_lock, flags);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * wake_up_all() and wait_event_timeout() already have the correct</div><div class='add'>+	 * barriers.</div><div class='add'>+	 */</div><div class='add'>+	WRITE_ONCE(gt-&gt;tlb_invalidation.seqno_recv, msg[0]);</div><div class='add'>+	wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(fence, next,</div><div class='add'>+				 &amp;gt-&gt;tlb_invalidation.pending_fences, link) {</div><div class='add'>+		trace_xe_gt_tlb_invalidation_fence_recv(fence);</div><div class='add'>+</div><div class='add'>+		if (!tlb_invalidation_seqno_past(gt, fence-&gt;seqno))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		invalidation_fence_signal(fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!list_empty(&amp;gt-&gt;tlb_invalidation.pending_fences))</div><div class='add'>+		mod_delayed_work(system_wq,</div><div class='add'>+				 &amp;gt-&gt;tlb_invalidation.fence_tdr,</div><div class='add'>+				 TLB_TIMEOUT);</div><div class='add'>+	else</div><div class='add'>+		cancel_delayed_work(&amp;gt-&gt;tlb_invalidation.fence_tdr);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;gt-&gt;tlb_invalidation.pending_lock, flags);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h<br/>new file mode 100644<br/>index 000000000000..b333c1709397<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_TLB_INVALIDATION_H_</div><div class='add'>+#define _XE_GT_TLB_INVALIDATION_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt_tlb_invalidation_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_guc;</div><div class='add'>+struct xe_vma;</div><div class='add'>+</div><div class='add'>+int xe_gt_tlb_invalidation_init(struct xe_gt *gt);</div><div class='add'>+void xe_gt_tlb_invalidation_reset(struct xe_gt *gt);</div><div class='add'>+int xe_gt_tlb_invalidation_guc(struct xe_gt *gt);</div><div class='add'>+int xe_gt_tlb_invalidation_vma(struct xe_gt *gt,</div><div class='add'>+			       struct xe_gt_tlb_invalidation_fence *fence,</div><div class='add'>+			       struct xe_vma *vma);</div><div class='add'>+int xe_gt_tlb_invalidation_wait(struct xe_gt *gt, int seqno);</div><div class='add'>+int xe_guc_tlb_invalidation_done_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+</div><div class='add'>+#endif	/* _XE_GT_TLB_INVALIDATION_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h<br/>new file mode 100644<br/>index 000000000000..934c828efe31<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_TLB_INVALIDATION_TYPES_H_</div><div class='add'>+#define _XE_GT_TLB_INVALIDATION_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_gt_tlb_invalidation_fence - XE GT TLB invalidation fence</div><div class='add'>+ *</div><div class='add'>+ * Optionally passed to xe_gt_tlb_invalidation and will be signaled upon TLB</div><div class='add'>+ * invalidation completion.</div><div class='add'>+ */</div><div class='add'>+struct xe_gt_tlb_invalidation_fence {</div><div class='add'>+	/** @base: dma fence base */</div><div class='add'>+	struct dma_fence base;</div><div class='add'>+	/** @link: link into list of pending tlb fences */</div><div class='add'>+	struct list_head link;</div><div class='add'>+	/** @seqno: seqno of TLB invalidation to signal fence one */</div><div class='add'>+	int seqno;</div><div class='add'>+	/** @invalidation_time: time of TLB invalidation */</div><div class='add'>+	ktime_t invalidation_time;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c<br/>new file mode 100644<br/>index 000000000000..a8d7f272c30a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_topology.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_topology.c</a></div><div class='hunk'>@@ -0,0 +1,169 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)</div><div class='add'>+#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)</div><div class='add'>+{</div><div class='add'>+	va_list argp;</div><div class='add'>+	u32 fuse_val[XE_MAX_DSS_FUSE_REGS] = {};</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (drm_WARN_ON(&amp;gt_to_xe(gt)-&gt;drm, numregs &gt; XE_MAX_DSS_FUSE_REGS))</div><div class='add'>+		numregs = XE_MAX_DSS_FUSE_REGS;</div><div class='add'>+</div><div class='add'>+	va_start(argp, numregs);</div><div class='add'>+	for (i = 0; i &lt; numregs; i++)</div><div class='add'>+		fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));</div><div class='add'>+	va_end(argp);</div><div class='add'>+</div><div class='add'>+	bitmap_from_arr32(mask, fuse_val, numregs * 32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);</div><div class='add'>+	u32 val = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(XE_MAX_EU_FUSE_REGS &gt; 1);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Pre-Xe_HP platforms inverted the bit meaning (disable instead</div><div class='add'>+	 * of enable).</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1250)</div><div class='add'>+		reg_val = ~reg_val &amp; XELP_EU_MASK;</div><div class='add'>+</div><div class='add'>+	/* On PVC, one bit = one EU */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) == 1260) {</div><div class='add'>+		val = reg_val;</div><div class='add'>+	} else {</div><div class='add'>+		/* All other platforms, one bit = 2 EU */</div><div class='add'>+		for (i = 0; i &lt; fls(reg_val); i++)</div><div class='add'>+			if (reg_val &amp; BIT(i))</div><div class='add'>+				val |= 0x3 &lt;&lt; 2 * i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bitmap_from_arr32(mask, &amp;val, XE_MAX_EU_FUSE_BITS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+get_num_dss_regs(struct xe_device *xe, int *geometry_regs, int *compute_regs)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VER(xe) &gt; 20) {</div><div class='add'>+		*geometry_regs = 3;</div><div class='add'>+		*compute_regs = 3;</div><div class='add'>+	} else if (GRAPHICS_VERx100(xe) == 1260) {</div><div class='add'>+		*geometry_regs = 0;</div><div class='add'>+		*compute_regs = 2;</div><div class='add'>+	} else if (GRAPHICS_VERx100(xe) &gt;= 1250) {</div><div class='add'>+		*geometry_regs = 1;</div><div class='add'>+		*compute_regs = 1;</div><div class='add'>+	} else {</div><div class='add'>+		*geometry_regs = 1;</div><div class='add'>+		*compute_regs = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+xe_gt_topology_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct drm_printer p = drm_debug_printer("GT topology");</div><div class='add'>+	int num_geometry_regs, num_compute_regs;</div><div class='add'>+</div><div class='add'>+	get_num_dss_regs(xe, &amp;num_geometry_regs, &amp;num_compute_regs);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Register counts returned shouldn't exceed the number of registers</div><div class='add'>+	 * passed as parameters below.</div><div class='add'>+	 */</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, num_geometry_regs &gt; 3);</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, num_compute_regs &gt; 3);</div><div class='add'>+</div><div class='add'>+	load_dss_mask(gt, gt-&gt;fuse_topo.g_dss_mask,</div><div class='add'>+		      num_geometry_regs,</div><div class='add'>+		      XELP_GT_GEOMETRY_DSS_ENABLE,</div><div class='add'>+		      XE2_GT_GEOMETRY_DSS_1,</div><div class='add'>+		      XE2_GT_GEOMETRY_DSS_2);</div><div class='add'>+	load_dss_mask(gt, gt-&gt;fuse_topo.c_dss_mask, num_compute_regs,</div><div class='add'>+		      XEHP_GT_COMPUTE_DSS_ENABLE,</div><div class='add'>+		      XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,</div><div class='add'>+		      XE2_GT_COMPUTE_DSS_2);</div><div class='add'>+	load_eu_mask(gt, gt-&gt;fuse_topo.eu_mask_per_dss);</div><div class='add'>+</div><div class='add'>+	xe_gt_topology_dump(gt, &amp;p);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	drm_printf(p, "dss mask (geometry): %*pb\n", XE_MAX_DSS_FUSE_BITS,</div><div class='add'>+		   gt-&gt;fuse_topo.g_dss_mask);</div><div class='add'>+	drm_printf(p, "dss mask (compute):  %*pb\n", XE_MAX_DSS_FUSE_BITS,</div><div class='add'>+		   gt-&gt;fuse_topo.c_dss_mask);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "EU mask per DSS:     %*pb\n", XE_MAX_EU_FUSE_BITS,</div><div class='add'>+		   gt-&gt;fuse_topo.eu_mask_per_dss);</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Used to obtain the index of the first DSS.  Can start searching from the</div><div class='add'>+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if</div><div class='add'>+ * groupsize and groupnum are non-zero.</div><div class='add'>+ */</div><div class='add'>+unsigned int</div><div class='add'>+xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum)</div><div class='add'>+{</div><div class='add'>+	return find_next_bit(mask, XE_MAX_DSS_FUSE_BITS, groupnum * groupsize);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_dss_mask_empty(const xe_dss_mask_t mask)</div><div class='add'>+{</div><div class='add'>+	return bitmap_empty(mask, XE_MAX_DSS_FUSE_BITS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_gt_topology_has_dss_in_quadrant - check fusing of DSS in GT quadrant</div><div class='add'>+ * @gt: GT to check</div><div class='add'>+ * @quad: Which quadrant of the DSS space to check</div><div class='add'>+ *</div><div class='add'>+ * Since Xe_HP platforms can have up to four CCS engines, those engines</div><div class='add'>+ * are each logically associated with a quarter of the possible DSS.  If there</div><div class='add'>+ * are no DSS present in one of the four quadrants of the DSS space, the</div><div class='add'>+ * corresponding CCS engine is also not available for use.</div><div class='add'>+ *</div><div class='add'>+ * Returns false if all DSS in a quadrant of the GT are fused off, else true.</div><div class='add'>+ */</div><div class='add'>+bool xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	xe_dss_mask_t all_dss;</div><div class='add'>+	int g_dss_regs, c_dss_regs, dss_per_quad, quad_first;</div><div class='add'>+</div><div class='add'>+	bitmap_or(all_dss, gt-&gt;fuse_topo.g_dss_mask, gt-&gt;fuse_topo.c_dss_mask,</div><div class='add'>+		  XE_MAX_DSS_FUSE_BITS);</div><div class='add'>+</div><div class='add'>+	get_num_dss_regs(xe, &amp;g_dss_regs, &amp;c_dss_regs);</div><div class='add'>+	dss_per_quad = 32 * max(g_dss_regs, c_dss_regs) / 4;</div><div class='add'>+</div><div class='add'>+	quad_first = xe_dss_mask_group_ffs(all_dss, dss_per_quad, quad);</div><div class='add'>+</div><div class='add'>+	return quad_first &lt; (quad + 1) * dss_per_quad;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_topology.h b/drivers/gpu/drm/xe/xe_gt_topology.h<br/>new file mode 100644<br/>index 000000000000..d1b54fb52ea6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_topology.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_topology.h</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_TOPOLOGY_H_</div><div class='add'>+#define _XE_GT_TOPOLOGY_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+void xe_gt_topology_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+void xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+unsigned int</div><div class='add'>+xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum);</div><div class='add'>+</div><div class='add'>+bool xe_dss_mask_empty(const xe_dss_mask_t mask);</div><div class='add'>+</div><div class='add'>+bool</div><div class='add'>+xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad);</div><div class='add'>+</div><div class='add'>+#endif /* _XE_GT_TOPOLOGY_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h<br/>new file mode 100644<br/>index 000000000000..f74684660475<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_gt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_gt_types.h</a></div><div class='hunk'>@@ -0,0 +1,363 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022-2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GT_TYPES_H_</div><div class='add'>+#define _XE_GT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_force_wake_types.h"</div><div class='add'>+#include "xe_gt_idle_types.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_hw_fence_types.h"</div><div class='add'>+#include "xe_reg_sr_types.h"</div><div class='add'>+#include "xe_sa_types.h"</div><div class='add'>+#include "xe_uc_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue_ops;</div><div class='add'>+struct xe_migrate;</div><div class='add'>+struct xe_ring_ops;</div><div class='add'>+</div><div class='add'>+enum xe_gt_type {</div><div class='add'>+	XE_GT_TYPE_UNINITIALIZED,</div><div class='add'>+	XE_GT_TYPE_MAIN,</div><div class='add'>+	XE_GT_TYPE_MEDIA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE_MAX_DSS_FUSE_REGS	3</div><div class='add'>+#define XE_MAX_EU_FUSE_REGS	1</div><div class='add'>+</div><div class='add'>+typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];</div><div class='add'>+typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)];</div><div class='add'>+</div><div class='add'>+struct xe_mmio_range {</div><div class='add'>+	u32 start;</div><div class='add'>+	u32 end;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The hardware has multiple kinds of multicast register ranges that need</div><div class='add'>+ * special register steering (and future platforms are expected to add</div><div class='add'>+ * additional types).</div><div class='add'>+ *</div><div class='add'>+ * During driver startup, we initialize the steering control register to</div><div class='add'>+ * direct reads to a slice/subslice that are valid for the 'subslice' class</div><div class='add'>+ * of multicast registers.  If another type of steering does not have any</div><div class='add'>+ * overlap in valid steering targets with 'subslice' style registers, we will</div><div class='add'>+ * need to explicitly re-steer reads of registers of the other type.</div><div class='add'>+ *</div><div class='add'>+ * Only the replication types that may need additional non-default steering</div><div class='add'>+ * are listed here.</div><div class='add'>+ */</div><div class='add'>+enum xe_steering_type {</div><div class='add'>+	L3BANK,</div><div class='add'>+	MSLICE,</div><div class='add'>+	LNCF,</div><div class='add'>+	DSS,</div><div class='add'>+	OADDRM,</div><div class='add'>+	SQIDI_PSMI,</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * On some platforms there are multiple types of MCR registers that</div><div class='add'>+	 * will always return a non-terminated value at instance (0, 0).  We'll</div><div class='add'>+	 * lump those all into a single category to keep things simple.</div><div class='add'>+	 */</div><div class='add'>+	INSTANCE0,</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Register ranges that don't need special steering for each register:</div><div class='add'>+	 * it's sufficient to keep the HW-default for the selector, or only</div><div class='add'>+	 * change it once, on GT initialization. This needs to be the last</div><div class='add'>+	 * steering type.</div><div class='add'>+	 */</div><div class='add'>+	IMPLICIT_STEERING,</div><div class='add'>+	NUM_STEERING_TYPES</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define gt_to_tile(gt__)							\</div><div class='add'>+	_Generic(gt__,								\</div><div class='add'>+		 const struct xe_gt * : (const struct xe_tile *)((gt__)-&gt;tile),	\</div><div class='add'>+		 struct xe_gt * : (gt__)-&gt;tile)</div><div class='add'>+</div><div class='add'>+#define gt_to_xe(gt__)										\</div><div class='add'>+	_Generic(gt__,										\</div><div class='add'>+		 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)-&gt;xe),	\</div><div class='add'>+		 struct xe_gt * : gt_to_tile(gt__)-&gt;xe)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_gt - A "Graphics Technology" unit of the GPU</div><div class='add'>+ *</div><div class='add'>+ * A GT ("Graphics Technology") is the subset of a GPU primarily responsible</div><div class='add'>+ * for implementing the graphics, compute, and/or media IP.  It encapsulates</div><div class='add'>+ * the hardware engines, programmable execution units, and GuC.   Each GT has</div><div class='add'>+ * its own handling of power management (RC6+forcewake) and multicast register</div><div class='add'>+ * steering.</div><div class='add'>+ *</div><div class='add'>+ * A GPU/tile may have a single GT that supplies all graphics, compute, and</div><div class='add'>+ * media functionality, or the graphics/compute and media may be split into</div><div class='add'>+ * separate GTs within a tile.</div><div class='add'>+ */</div><div class='add'>+struct xe_gt {</div><div class='add'>+	/** @tile: Backpointer to GT's tile */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	/** @info: GT info */</div><div class='add'>+	struct {</div><div class='add'>+		/** @type: type of GT */</div><div class='add'>+		enum xe_gt_type type;</div><div class='add'>+		/** @id: Unique ID of this GT within the PCI Device */</div><div class='add'>+		u8 id;</div><div class='add'>+		/** @reference_clock: clock frequency */</div><div class='add'>+		u32 reference_clock;</div><div class='add'>+		/** @engine_mask: mask of engines present on GT */</div><div class='add'>+		u64 engine_mask;</div><div class='add'>+		/**</div><div class='add'>+		 * @__engine_mask: mask of engines present on GT read from</div><div class='add'>+		 * xe_pci.c, used to fake reading the engine_mask from the</div><div class='add'>+		 * hwconfig blob.</div><div class='add'>+		 */</div><div class='add'>+		u64 __engine_mask;</div><div class='add'>+	} info;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mmio: mmio info for GT.  All GTs within a tile share the same</div><div class='add'>+	 * register space, but have their own copy of GSI registers at a</div><div class='add'>+	 * specific offset, as well as their own forcewake handling.</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @fw: force wake for GT */</div><div class='add'>+		struct xe_force_wake fw;</div><div class='add'>+		/**</div><div class='add'>+		 * @adj_limit: adjust MMIO address if address is below this</div><div class='add'>+		 * value</div><div class='add'>+		 */</div><div class='add'>+		u32 adj_limit;</div><div class='add'>+		/** @adj_offset: offect to add to MMIO address when adjusting */</div><div class='add'>+		u32 adj_offset;</div><div class='add'>+	} mmio;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @reg_sr: table with registers to be restored on GT init/resume/reset</div><div class='add'>+	 */</div><div class='add'>+	struct xe_reg_sr reg_sr;</div><div class='add'>+</div><div class='add'>+	/** @reset: state for GT resets */</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @worker: work so GT resets can done async allowing to reset</div><div class='add'>+		 * code to safely flush all code paths</div><div class='add'>+		 */</div><div class='add'>+		struct work_struct worker;</div><div class='add'>+	} reset;</div><div class='add'>+</div><div class='add'>+	/** @tlb_invalidation: TLB invalidation state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @seqno: TLB invalidation seqno, protected by CT lock */</div><div class='add'>+#define TLB_INVALIDATION_SEQNO_MAX	0x100000</div><div class='add'>+		int seqno;</div><div class='add'>+		/**</div><div class='add'>+		 * @seqno_recv: last received TLB invalidation seqno, protected by CT lock</div><div class='add'>+		 */</div><div class='add'>+		int seqno_recv;</div><div class='add'>+		/**</div><div class='add'>+		 * @pending_fences: list of pending fences waiting TLB</div><div class='add'>+		 * invaliations, protected by CT lock</div><div class='add'>+		 */</div><div class='add'>+		struct list_head pending_fences;</div><div class='add'>+		/**</div><div class='add'>+		 * @pending_lock: protects @pending_fences and updating</div><div class='add'>+		 * @seqno_recv.</div><div class='add'>+		 */</div><div class='add'>+		spinlock_t pending_lock;</div><div class='add'>+		/**</div><div class='add'>+		 * @fence_tdr: schedules a delayed call to</div><div class='add'>+		 * xe_gt_tlb_fence_timeout after the timeut interval is over.</div><div class='add'>+		 */</div><div class='add'>+		struct delayed_work fence_tdr;</div><div class='add'>+		/** @fence_context: context for TLB invalidation fences */</div><div class='add'>+		u64 fence_context;</div><div class='add'>+		/**</div><div class='add'>+		 * @fence_seqno: seqno to TLB invalidation fences, protected by</div><div class='add'>+		 * tlb_invalidation.lock</div><div class='add'>+		 */</div><div class='add'>+		u32 fence_seqno;</div><div class='add'>+		/** @lock: protects TLB invalidation fences */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+	} tlb_invalidation;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ccs_mode: Number of compute engines enabled.</div><div class='add'>+	 * Allows fixed mapping of available compute slices to compute engines.</div><div class='add'>+	 * By default only the first available compute engine is enabled and all</div><div class='add'>+	 * available compute slices are allocated to it.</div><div class='add'>+	 */</div><div class='add'>+	u32 ccs_mode;</div><div class='add'>+</div><div class='add'>+	/** @usm: unified shared memory state */</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @bb_pool: Pool from which batchbuffers, for USM operations</div><div class='add'>+		 * (e.g. migrations, fixing page tables), are allocated.</div><div class='add'>+		 * Dedicated pool needed so USM operations to not get blocked</div><div class='add'>+		 * behind any user operations which may have resulted in a</div><div class='add'>+		 * fault.</div><div class='add'>+		 */</div><div class='add'>+		struct xe_sa_manager *bb_pool;</div><div class='add'>+		/**</div><div class='add'>+		 * @reserved_bcs_instance: reserved BCS instance used for USM</div><div class='add'>+		 * operations (e.g. mmigrations, fixing page tables)</div><div class='add'>+		 */</div><div class='add'>+		u16 reserved_bcs_instance;</div><div class='add'>+		/** @pf_wq: page fault work queue, unbound, high priority */</div><div class='add'>+		struct workqueue_struct *pf_wq;</div><div class='add'>+		/** @acc_wq: access counter work queue, unbound, high priority */</div><div class='add'>+		struct workqueue_struct *acc_wq;</div><div class='add'>+		/**</div><div class='add'>+		 * @pf_queue: Page fault queue used to sync faults so faults can</div><div class='add'>+		 * be processed not under the GuC CT lock. The queue is sized so</div><div class='add'>+		 * it can sync all possible faults (1 per physical engine).</div><div class='add'>+		 * Multiple queues exists for page faults from different VMs are</div><div class='add'>+		 * be processed in parallel.</div><div class='add'>+		 */</div><div class='add'>+		struct pf_queue {</div><div class='add'>+			/** @gt: back pointer to GT */</div><div class='add'>+			struct xe_gt *gt;</div><div class='add'>+#define PF_QUEUE_NUM_DW	128</div><div class='add'>+			/** @data: data in the page fault queue */</div><div class='add'>+			u32 data[PF_QUEUE_NUM_DW];</div><div class='add'>+			/**</div><div class='add'>+			 * @head: head pointer in DWs for page fault queue,</div><div class='add'>+			 * moved by worker which processes faults.</div><div class='add'>+			 */</div><div class='add'>+			u16 head;</div><div class='add'>+			/**</div><div class='add'>+			 * @tail: tail pointer in DWs for page fault queue,</div><div class='add'>+			 * moved by G2H handler.</div><div class='add'>+			 */</div><div class='add'>+			u16 tail;</div><div class='add'>+			/** @lock: protects page fault queue */</div><div class='add'>+			spinlock_t lock;</div><div class='add'>+			/** @worker: to process page faults */</div><div class='add'>+			struct work_struct worker;</div><div class='add'>+#define NUM_PF_QUEUE	4</div><div class='add'>+		} pf_queue[NUM_PF_QUEUE];</div><div class='add'>+		/**</div><div class='add'>+		 * @acc_queue: Same as page fault queue, cannot process access</div><div class='add'>+		 * counters under CT lock.</div><div class='add'>+		 */</div><div class='add'>+		struct acc_queue {</div><div class='add'>+			/** @gt: back pointer to GT */</div><div class='add'>+			struct xe_gt *gt;</div><div class='add'>+#define ACC_QUEUE_NUM_DW	128</div><div class='add'>+			/** @data: data in the page fault queue */</div><div class='add'>+			u32 data[ACC_QUEUE_NUM_DW];</div><div class='add'>+			/**</div><div class='add'>+			 * @head: head pointer in DWs for page fault queue,</div><div class='add'>+			 * moved by worker which processes faults.</div><div class='add'>+			 */</div><div class='add'>+			u16 head;</div><div class='add'>+			/**</div><div class='add'>+			 * @tail: tail pointer in DWs for page fault queue,</div><div class='add'>+			 * moved by G2H handler.</div><div class='add'>+			 */</div><div class='add'>+			u16 tail;</div><div class='add'>+			/** @lock: protects page fault queue */</div><div class='add'>+			spinlock_t lock;</div><div class='add'>+			/** @worker: to process access counters */</div><div class='add'>+			struct work_struct worker;</div><div class='add'>+#define NUM_ACC_QUEUE	4</div><div class='add'>+		} acc_queue[NUM_ACC_QUEUE];</div><div class='add'>+	} usm;</div><div class='add'>+</div><div class='add'>+	/** @ordered_wq: used to serialize GT resets and TDRs */</div><div class='add'>+	struct workqueue_struct *ordered_wq;</div><div class='add'>+</div><div class='add'>+	/** @uc: micro controllers on the GT */</div><div class='add'>+	struct xe_uc uc;</div><div class='add'>+</div><div class='add'>+	/** @gtidle: idle properties of GT */</div><div class='add'>+	struct xe_gt_idle gtidle;</div><div class='add'>+</div><div class='add'>+	/** @exec_queue_ops: submission backend exec queue operations */</div><div class='add'>+	const struct xe_exec_queue_ops *exec_queue_ops;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @ring_ops: ring operations for this hw engine (1 per engine class)</div><div class='add'>+	 */</div><div class='add'>+	const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX];</div><div class='add'>+</div><div class='add'>+	/** @fence_irq: fence IRQs (1 per engine class) */</div><div class='add'>+	struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX];</div><div class='add'>+</div><div class='add'>+	/** @default_lrc: default LRC state */</div><div class='add'>+	void *default_lrc[XE_ENGINE_CLASS_MAX];</div><div class='add'>+</div><div class='add'>+	/** @hw_engines: hardware engines on the GT */</div><div class='add'>+	struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];</div><div class='add'>+</div><div class='add'>+	/** @eclass: per hardware engine class interface on the GT */</div><div class='add'>+	struct xe_hw_engine_class_intf  eclass[XE_ENGINE_CLASS_MAX];</div><div class='add'>+</div><div class='add'>+	/** @pcode: GT's PCODE */</div><div class='add'>+	struct {</div><div class='add'>+		/** @lock: protecting GT's PCODE mailbox data */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+	} pcode;</div><div class='add'>+</div><div class='add'>+	/** @sysfs: sysfs' kobj used by xe_gt_sysfs */</div><div class='add'>+	struct kobject *sysfs;</div><div class='add'>+</div><div class='add'>+	/** @freq: Main GT freq sysfs control */</div><div class='add'>+	struct kobject *freq;</div><div class='add'>+</div><div class='add'>+	/** @mocs: info */</div><div class='add'>+	struct {</div><div class='add'>+		/** @uc_index: UC index */</div><div class='add'>+		u8 uc_index;</div><div class='add'>+		/** @wb_index: WB index, only used on L3_CCS platforms */</div><div class='add'>+		u8 wb_index;</div><div class='add'>+	} mocs;</div><div class='add'>+</div><div class='add'>+	/** @fuse_topo: GT topology reported by fuse registers */</div><div class='add'>+	struct {</div><div class='add'>+		/** @g_dss_mask: dual-subslices usable by geometry */</div><div class='add'>+		xe_dss_mask_t g_dss_mask;</div><div class='add'>+</div><div class='add'>+		/** @c_dss_mask: dual-subslices usable by compute */</div><div class='add'>+		xe_dss_mask_t c_dss_mask;</div><div class='add'>+</div><div class='add'>+		/** @eu_mask_per_dss: EU mask per DSS*/</div><div class='add'>+		xe_eu_mask_t eu_mask_per_dss;</div><div class='add'>+	} fuse_topo;</div><div class='add'>+</div><div class='add'>+	/** @steering: register steering for individual HW units */</div><div class='add'>+	struct {</div><div class='add'>+		/* @ranges: register ranges used for this steering type */</div><div class='add'>+		const struct xe_mmio_range *ranges;</div><div class='add'>+</div><div class='add'>+		/** @group_target: target to steer accesses to */</div><div class='add'>+		u16 group_target;</div><div class='add'>+		/** @instance_target: instance to steer accesses to */</div><div class='add'>+		u16 instance_target;</div><div class='add'>+	} steering[NUM_STEERING_TYPES];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @mcr_lock: protects the MCR_SELECTOR register for the duration</div><div class='add'>+	 *    of a steered operation</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t mcr_lock;</div><div class='add'>+</div><div class='add'>+	/** @wa_active: keep track of active workarounds */</div><div class='add'>+	struct {</div><div class='add'>+		/** @gt: bitmap with active GT workarounds */</div><div class='add'>+		unsigned long *gt;</div><div class='add'>+		/** @engine: bitmap with active engine workarounds */</div><div class='add'>+		unsigned long *engine;</div><div class='add'>+		/** @lrc: bitmap with active LRC workarounds */</div><div class='add'>+		unsigned long *lrc;</div><div class='add'>+		/** @oob: bitmap with active OOB workaroudns */</div><div class='add'>+		unsigned long *oob;</div><div class='add'>+	} wa_active;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c<br/>new file mode 100644<br/>index 000000000000..0a61390c64a7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc.c</a></div><div class='hunk'>@@ -0,0 +1,916 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "abi/guc_errors_abi.h"</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_guc_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc_ads.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_guc_hwconfig.h"</div><div class='add'>+#include "xe_guc_log.h"</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+#include "xe_guc_submit.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_uc.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+#include "xe_wopcm.h"</div><div class='add'>+</div><div class='add'>+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */</div><div class='add'>+#define GUC_GGTT_TOP    0xFEE00000</div><div class='add'>+static u32 guc_bo_ggtt_addr(struct xe_guc *guc,</div><div class='add'>+			    struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 addr = xe_bo_ggtt_addr(bo);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, addr &gt;= xe_wopcm_size(guc_to_xe(guc)));</div><div class='add'>+	xe_assert(xe, addr &lt; GUC_GGTT_TOP);</div><div class='add'>+	xe_assert(xe, bo-&gt;size &lt;= GUC_GGTT_TOP - addr);</div><div class='add'>+</div><div class='add'>+	return addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_debug_flags(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	u32 level = xe_guc_log_get_level(&amp;guc-&gt;log);</div><div class='add'>+	u32 flags = 0;</div><div class='add'>+</div><div class='add'>+	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))</div><div class='add'>+		flags |= GUC_LOG_DISABLED;</div><div class='add'>+	else</div><div class='add'>+		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) &lt;&lt;</div><div class='add'>+			 GUC_LOG_VERBOSITY_SHIFT;</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_feature_flags(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	u32 flags = 0;</div><div class='add'>+</div><div class='add'>+	if (!guc_to_xe(guc)-&gt;info.skip_guc_pc)</div><div class='add'>+		flags |= GUC_CTL_ENABLE_SLPC;</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_log_params_flags(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	u32 offset = guc_bo_ggtt_addr(guc, guc-&gt;log.bo) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	u32 flags;</div><div class='add'>+</div><div class='add'>+	#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)</div><div class='add'>+	#define LOG_UNIT SZ_1M</div><div class='add'>+	#define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS</div><div class='add'>+	#else</div><div class='add'>+	#define LOG_UNIT SZ_4K</div><div class='add'>+	#define LOG_FLAG 0</div><div class='add'>+	#endif</div><div class='add'>+</div><div class='add'>+	#if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0)</div><div class='add'>+	#define CAPTURE_UNIT SZ_1M</div><div class='add'>+	#define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS</div><div class='add'>+	#else</div><div class='add'>+	#define CAPTURE_UNIT SZ_4K</div><div class='add'>+	#define CAPTURE_FLAG 0</div><div class='add'>+	#endif</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);</div><div class='add'>+	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT));</div><div class='add'>+	BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);</div><div class='add'>+	BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT));</div><div class='add'>+	BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE);</div><div class='add'>+	BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT));</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) &gt;</div><div class='add'>+			(GUC_LOG_CRASH_MASK &gt;&gt; GUC_LOG_CRASH_SHIFT));</div><div class='add'>+	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) &gt;</div><div class='add'>+			(GUC_LOG_DEBUG_MASK &gt;&gt; GUC_LOG_DEBUG_SHIFT));</div><div class='add'>+	BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) &gt;</div><div class='add'>+			(GUC_LOG_CAPTURE_MASK &gt;&gt; GUC_LOG_CAPTURE_SHIFT));</div><div class='add'>+</div><div class='add'>+	flags = GUC_LOG_VALID |</div><div class='add'>+		GUC_LOG_NOTIFY_ON_HALF_FULL |</div><div class='add'>+		CAPTURE_FLAG |</div><div class='add'>+		LOG_FLAG |</div><div class='add'>+		((CRASH_BUFFER_SIZE / LOG_UNIT - 1) &lt;&lt; GUC_LOG_CRASH_SHIFT) |</div><div class='add'>+		((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) &lt;&lt; GUC_LOG_DEBUG_SHIFT) |</div><div class='add'>+		((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) &lt;&lt;</div><div class='add'>+		 GUC_LOG_CAPTURE_SHIFT) |</div><div class='add'>+		(offset &lt;&lt; GUC_LOG_BUF_ADDR_SHIFT);</div><div class='add'>+</div><div class='add'>+	#undef LOG_UNIT</div><div class='add'>+	#undef LOG_FLAG</div><div class='add'>+	#undef CAPTURE_UNIT</div><div class='add'>+	#undef CAPTURE_FLAG</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_ads_flags(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	u32 ads = guc_bo_ggtt_addr(guc, guc-&gt;ads.bo) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	u32 flags = ads &lt;&lt; GUC_ADS_ADDR_SHIFT;</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_wa_flags(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 flags = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 22012773006))</div><div class='add'>+		flags |= GUC_WA_POLLCS;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 16011759253))</div><div class='add'>+		flags |= GUC_WA_GAM_CREDITS;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 14014475959))</div><div class='add'>+		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 22011391025) || XE_WA(gt, 14012197797))</div><div class='add'>+		flags |= GUC_WA_DUAL_QUEUE;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wa_22011802037: FIXME - there's more to be done than simply setting</div><div class='add'>+	 * this flag: make sure each CS is stopped when preparing for GT reset</div><div class='add'>+	 * and wait for pending MI_FW.</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1270)</div><div class='add'>+		flags |= GUC_WA_PRE_PARSER;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 16011777198))</div><div class='add'>+		flags |= GUC_WA_RCS_RESET_BEFORE_RC6;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685))</div><div class='add'>+		flags |= GUC_WA_CONTEXT_ISOLATION;</div><div class='add'>+</div><div class='add'>+	if ((XE_WA(gt, 16015675438) || XE_WA(gt, 18020744125)) &amp;&amp;</div><div class='add'>+	    !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER))</div><div class='add'>+		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 1509372804))</div><div class='add'>+		flags |= GUC_WA_RENDER_RST_RC6_EXIT;</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 guc_ctl_devid(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	return (((u32)xe-&gt;info.devid) &lt;&lt; 16) | xe-&gt;info.revid;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_init_params(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 *params = guc-&gt;params;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(sizeof(guc-&gt;params) != GUC_CTL_MAX_DWORDS * sizeof(u32));</div><div class='add'>+	BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT);</div><div class='add'>+</div><div class='add'>+	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);</div><div class='add'>+	params[GUC_CTL_FEATURE] = 0;</div><div class='add'>+	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);</div><div class='add'>+	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);</div><div class='add'>+	params[GUC_CTL_WA] = 0;</div><div class='add'>+	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; GUC_CTL_MAX_DWORDS; i++)</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "GuC param[%2d] = 0x%08x\n", i, params[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_init_params_post_hwconfig(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 *params = guc-&gt;params;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(sizeof(guc-&gt;params) != GUC_CTL_MAX_DWORDS * sizeof(u32));</div><div class='add'>+	BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT);</div><div class='add'>+</div><div class='add'>+	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);</div><div class='add'>+	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);</div><div class='add'>+	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);</div><div class='add'>+	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);</div><div class='add'>+	params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);</div><div class='add'>+	params[GUC_CTL_DEVID] = guc_ctl_devid(guc);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; GUC_CTL_MAX_DWORDS; i++)</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "GuC param[%2d] = 0x%08x\n", i, params[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initialize the GuC parameter block before starting the firmware</div><div class='add'>+ * transfer. These parameters are read by the firmware on startup</div><div class='add'>+ * and cannot be changed thereafter.</div><div class='add'>+ */</div><div class='add'>+static void guc_write_params(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; GUC_CTL_MAX_DWORDS; i++)</div><div class='add'>+		xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc-&gt;params[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = arg;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_get(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL);</div><div class='add'>+	xe_guc_pc_fini(&amp;guc-&gt;pc);</div><div class='add'>+	xe_uc_fini_hw(&amp;guc_to_gt(guc)-&gt;uc);</div><div class='add'>+	xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_init(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guc-&gt;fw.type = XE_UC_FW_TYPE_GUC;</div><div class='add'>+	ret = xe_uc_fw_init(&amp;guc-&gt;fw);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_enabled(&amp;guc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_log_init(&amp;guc-&gt;log);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ads_init(&amp;guc-&gt;ads);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ct_init(&amp;guc-&gt;ct);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_init(&amp;guc-&gt;pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = drmm_add_action_or_reset(&amp;gt_to_xe(gt)-&gt;drm, guc_fini, guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	guc_init_params(guc);</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		guc-&gt;notify_reg = MED_GUC_HOST_INTERRUPT;</div><div class='add'>+	else</div><div class='add'>+		guc-&gt;notify_reg = GUC_HOST_INTERRUPT;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;guc-&gt;fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "GuC init failed with %d", ret);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load</div><div class='add'>+ * @guc: The GuC object</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_init_post_hwconfig(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	guc_init_params_post_hwconfig(guc);</div><div class='add'>+</div><div class='add'>+	return xe_guc_ads_init_post_hwconfig(&amp;guc-&gt;ads);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_post_load_init(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	xe_guc_ads_populate_post_load(&amp;guc-&gt;ads);</div><div class='add'>+	guc-&gt;submission_state.enabled = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_reset(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 guc_status, gdrst;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, GDRST, GRDOM_GUC);</div><div class='add'>+</div><div class='add'>+	ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &amp;gdrst, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "GuC reset timed out, GDRST=0x%8x\n",</div><div class='add'>+			gdrst);</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	guc_status = xe_mmio_read32(gt, GUC_STATUS);</div><div class='add'>+	if (!(guc_status &amp; GS_MIA_IN_RESET)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm,</div><div class='add'>+			"GuC status: 0x%x, MIA core expected to be in reset\n",</div><div class='add'>+			guc_status);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_prepare_xfer(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	struct xe_device *xe =  guc_to_xe(guc);</div><div class='add'>+	u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |</div><div class='add'>+		GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |</div><div class='add'>+		GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |</div><div class='add'>+		GUC_ENABLE_MIA_CLOCK_GATING;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1250)</div><div class='add'>+		shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |</div><div class='add'>+				GUC_ENABLE_MIA_CACHING;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VER(xe) &gt;= 20 || xe-&gt;info.platform == XE_PVC)</div><div class='add'>+		shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+</div><div class='add'>+	/* Must program this register before loading the ucode with DMA */</div><div class='add'>+	xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Supporting MMIO &amp; in memory RSA</div><div class='add'>+ */</div><div class='add'>+static int guc_xfer_rsa(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 rsa[UOS_RSA_SCRATCH_COUNT];</div><div class='add'>+	size_t copied;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (guc-&gt;fw.rsa_size &gt; 256) {</div><div class='add'>+		u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc-&gt;fw.bo) +</div><div class='add'>+				    xe_uc_fw_rsa_offset(&amp;guc-&gt;fw);</div><div class='add'>+		xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	copied = xe_uc_fw_copy_rsa(&amp;guc-&gt;fw, rsa, sizeof(rsa));</div><div class='add'>+	if (copied &lt; sizeof(rsa))</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; UOS_RSA_SCRATCH_COUNT; i++)</div><div class='add'>+		xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_wait_ucode(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 status;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wait for the GuC to start up.</div><div class='add'>+	 * NB: Docs recommend not using the interrupt for completion.</div><div class='add'>+	 * Measurements indicate this should take no more than 20ms</div><div class='add'>+	 * (assuming the GT clock is at maximum frequency). So, a</div><div class='add'>+	 * timeout here indicates that the GuC has failed and is unusable.</div><div class='add'>+	 * (Higher levels of the driver may decide to reset the GuC and</div><div class='add'>+	 * attempt the ucode load again if this happens.)</div><div class='add'>+	 *</div><div class='add'>+	 * FIXME: There is a known (but exceedingly unlikely) race condition</div><div class='add'>+	 * where the asynchronous frequency management code could reduce</div><div class='add'>+	 * the GT clock while a GuC reload is in progress (during a full</div><div class='add'>+	 * GT reset). A fix is in progress but there are complex locking</div><div class='add'>+	 * issues to be resolved. In the meantime bump the timeout to</div><div class='add'>+	 * 200ms. Even at slowest clock, this should be sufficient. And</div><div class='add'>+	 * in the working case, a larger timeout makes no difference.</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS, GS_UKERNEL_MASK,</div><div class='add'>+			     FIELD_PREP(GS_UKERNEL_MASK, XE_GUC_LOAD_STATUS_READY),</div><div class='add'>+			     200000, &amp;status, false);</div><div class='add'>+</div><div class='add'>+	if (ret) {</div><div class='add'>+		struct drm_device *drm = &amp;xe-&gt;drm;</div><div class='add'>+		struct drm_printer p = drm_info_printer(drm-&gt;dev);</div><div class='add'>+</div><div class='add'>+		drm_info(drm, "GuC load failed: status = 0x%08X\n", status);</div><div class='add'>+		drm_info(drm, "GuC load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",</div><div class='add'>+			 REG_FIELD_GET(GS_MIA_IN_RESET, status),</div><div class='add'>+			 REG_FIELD_GET(GS_BOOTROM_MASK, status),</div><div class='add'>+			 REG_FIELD_GET(GS_UKERNEL_MASK, status),</div><div class='add'>+			 REG_FIELD_GET(GS_MIA_MASK, status),</div><div class='add'>+			 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));</div><div class='add'>+</div><div class='add'>+		if ((status &amp; GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {</div><div class='add'>+			drm_info(drm, "GuC firmware signature verification failed\n");</div><div class='add'>+			ret = -ENOEXEC;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (REG_FIELD_GET(GS_UKERNEL_MASK, status) ==</div><div class='add'>+		    XE_GUC_LOAD_STATUS_EXCEPTION) {</div><div class='add'>+			drm_info(drm, "GuC firmware exception. EIP: %#x\n",</div><div class='add'>+				 xe_mmio_read32(guc_to_gt(guc),</div><div class='add'>+						SOFT_SCRATCH(13)));</div><div class='add'>+			ret = -ENXIO;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_guc_log_print(&amp;guc-&gt;log, &amp;p);</div><div class='add'>+	} else {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "GuC successfully loaded");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_guc_upload(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guc_write_params(guc);</div><div class='add'>+	guc_prepare_xfer(guc);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note that GuC needs the CSS header plus uKernel code to be copied</div><div class='add'>+	 * by the DMA engine in one operation, whereas the RSA signature is</div><div class='add'>+	 * loaded separately, either by copying it to the UOS_RSA_SCRATCH</div><div class='add'>+	 * register (if key size &lt;= 256) or through a ggtt-pinned vma (if key</div><div class='add'>+	 * size &gt; 256). The RSA size and therefore the way we provide it to the</div><div class='add'>+	 * HW is fixed for each platform and hard-coded in the bootrom.</div><div class='add'>+	 */</div><div class='add'>+	ret = guc_xfer_rsa(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+	/*</div><div class='add'>+	 * Current uCode expects the code to be loaded at 8k; locations below</div><div class='add'>+	 * this are used for the stack.</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_uc_fw_upload(&amp;guc-&gt;fw, 0x2000, UOS_MOVE);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* Wait for authentication */</div><div class='add'>+	ret = guc_wait_ucode(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;guc-&gt;fw, XE_UC_FIRMWARE_RUNNING);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_uc_fw_change_status(&amp;guc-&gt;fw, XE_UC_FIRMWARE_LOAD_FAIL);</div><div class='add'>+	return 0	/* FIXME: ret, don't want to stop load currently */;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table</div><div class='add'>+ * @guc: The GuC object</div><div class='add'>+ *</div><div class='add'>+ * This function uploads a minimal GuC that does not support submissions but</div><div class='add'>+ * in a state where the hwconfig table can be read. Next, it reads and parses</div><div class='add'>+ * the hwconfig table so it can be used for subsequent steps in the driver load.</div><div class='add'>+ * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only).</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_guc_ads_populate_minimal(&amp;guc-&gt;ads);</div><div class='add'>+</div><div class='add'>+	ret = __xe_guc_upload(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_hwconfig_init(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_enable_communication(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_upload(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	xe_guc_ads_populate(&amp;guc-&gt;ads);</div><div class='add'>+</div><div class='add'>+	return __xe_guc_upload(guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_handle_mmio_msg(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 msg;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));</div><div class='add'>+	msg &amp;= XE_GUC_RECV_MSG_EXCEPTION |</div><div class='add'>+		XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;</div><div class='add'>+	xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);</div><div class='add'>+</div><div class='add'>+	if (msg &amp; XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)</div><div class='add'>+		drm_err(&amp;guc_to_xe(guc)-&gt;drm,</div><div class='add'>+			"Received early GuC crash dump notification!\n");</div><div class='add'>+</div><div class='add'>+	if (msg &amp; XE_GUC_RECV_MSG_EXCEPTION)</div><div class='add'>+		drm_err(&amp;guc_to_xe(guc)-&gt;drm,</div><div class='add'>+			"Received early GuC exception notification!\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_enable_irq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 events = xe_gt_is_media_type(gt) ?</div><div class='add'>+		REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST)  :</div><div class='add'>+		REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);</div><div class='add'>+</div><div class='add'>+	/* Primary GuC and media GuC share a single enable bit */</div><div class='add'>+	xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,</div><div class='add'>+			REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * There are separate mask bits for primary and media GuCs, so use</div><div class='add'>+	 * a RMW operation to avoid clobbering the other GuC's setting.</div><div class='add'>+	 */</div><div class='add'>+	xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_enable_communication(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	guc_enable_irq(guc);</div><div class='add'>+</div><div class='add'>+	xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK,</div><div class='add'>+		      ARAT_EXPIRED_INTRMSK, 0);</div><div class='add'>+</div><div class='add'>+	err = xe_guc_ct_enable(&amp;guc-&gt;ct);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	guc_handle_mmio_msg(guc);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_suspend(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_CLIENT_SOFT_RESET,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;guc_to_xe(guc)-&gt;drm,</div><div class='add'>+			"GuC suspend: CLIENT_SOFT_RESET fail: %d!\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_guc_sanitize(guc);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_notify(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	const u32 default_notify_data = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass</div><div class='add'>+	 * additional payload data to the GuC but this capability is not</div><div class='add'>+	 * used by the firmware yet. Use default value in the meantime.</div><div class='add'>+	 */</div><div class='add'>+	xe_mmio_write32(gt, guc-&gt;notify_reg, default_notify_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_AUTHENTICATE_HUC,</div><div class='add'>+		rsa_addr</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return xe_guc_ct_send_block(&amp;guc-&gt;ct, action, ARRAY_SIZE(action));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,</div><div class='add'>+			  u32 len, u32 *response_buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 header, reply;</div><div class='add'>+	struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?</div><div class='add'>+		MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);</div><div class='add'>+	const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1;</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !guc-&gt;ct.enabled);</div><div class='add'>+	xe_assert(xe, len);</div><div class='add'>+	xe_assert(xe, len &lt;= VF_SW_FLAG_COUNT);</div><div class='add'>+	xe_assert(xe, len &lt;= MED_VF_SW_FLAG_COUNT);</div><div class='add'>+	xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) ==</div><div class='add'>+		  GUC_HXG_ORIGIN_HOST);</div><div class='add'>+	xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) ==</div><div class='add'>+		  GUC_HXG_TYPE_REQUEST);</div><div class='add'>+</div><div class='add'>+retry:</div><div class='add'>+	/* Not in critical data-path, just do if else for GT type */</div><div class='add'>+	if (xe_gt_is_media_type(gt)) {</div><div class='add'>+		for (i = 0; i &lt; len; ++i)</div><div class='add'>+			xe_mmio_write32(gt, MED_VF_SW_FLAG(i),</div><div class='add'>+					request[i]);</div><div class='add'>+		xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));</div><div class='add'>+	} else {</div><div class='add'>+		for (i = 0; i &lt; len; ++i)</div><div class='add'>+			xe_mmio_write32(gt, VF_SW_FLAG(i),</div><div class='add'>+					request[i]);</div><div class='add'>+		xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_guc_notify(guc);</div><div class='add'>+</div><div class='add'>+	ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN,</div><div class='add'>+			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC),</div><div class='add'>+			     50000, &amp;reply, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+timeout:</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "mmio request %#x: no reply %#x\n",</div><div class='add'>+			request[0], reply);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	header = xe_mmio_read32(gt, reply_reg);</div><div class='add'>+	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==</div><div class='add'>+	    GUC_HXG_TYPE_NO_RESPONSE_BUSY) {</div><div class='add'>+		/*</div><div class='add'>+		 * Once we got a BUSY reply we must wait again for the final</div><div class='add'>+		 * response but this time we can't use ORIGIN mask anymore.</div><div class='add'>+		 * To spot a right change in the reply, we take advantage that</div><div class='add'>+		 * response SUCCESS and FAILURE differ only by the single bit</div><div class='add'>+		 * and all other bits are set and can be used as a new mask.</div><div class='add'>+		 */</div><div class='add'>+		u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS &amp; GUC_HXG_TYPE_RESPONSE_FAILURE;</div><div class='add'>+		u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits);</div><div class='add'>+</div><div class='add'>+		BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS);</div><div class='add'>+		BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1);</div><div class='add'>+</div><div class='add'>+		ret = xe_mmio_wait32(gt, reply_reg,  resp_mask, resp_mask,</div><div class='add'>+				     1000000, &amp;header, false);</div><div class='add'>+</div><div class='add'>+		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=</div><div class='add'>+			     GUC_HXG_ORIGIN_GUC))</div><div class='add'>+			goto proto;</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			goto timeout;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==</div><div class='add'>+	    GUC_HXG_TYPE_NO_RESPONSE_RETRY) {</div><div class='add'>+		u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);</div><div class='add'>+</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "mmio request %#x: retrying, reason %#x\n",</div><div class='add'>+			request[0], reason);</div><div class='add'>+		goto retry;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==</div><div class='add'>+	    GUC_HXG_TYPE_RESPONSE_FAILURE) {</div><div class='add'>+		u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);</div><div class='add'>+		u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);</div><div class='add'>+</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "mmio request %#x: failure %#x/%#x\n",</div><div class='add'>+			request[0], error, hint);</div><div class='add'>+		return -ENXIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) !=</div><div class='add'>+	    GUC_HXG_TYPE_RESPONSE_SUCCESS) {</div><div class='add'>+proto:</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "mmio request %#x: unexpected reply %#x\n",</div><div class='add'>+			request[0], header);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Just copy entire possible message response */</div><div class='add'>+	if (response_buf) {</div><div class='add'>+		response_buf[0] = header;</div><div class='add'>+</div><div class='add'>+		for (i = 1; i &lt; VF_SW_FLAG_COUNT; i++) {</div><div class='add'>+			reply_reg.addr += sizeof(u32);</div><div class='add'>+			response_buf[i] = xe_mmio_read32(gt, reply_reg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Use data from the GuC response as our return value */</div><div class='add'>+	return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)</div><div class='add'>+{</div><div class='add'>+	return xe_guc_mmio_send_recv(guc, request, len, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {</div><div class='add'>+		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |</div><div class='add'>+		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |</div><div class='add'>+		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION,</div><div class='add'>+			   GUC_ACTION_HOST2GUC_SELF_CFG),</div><div class='add'>+		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |</div><div class='add'>+		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),</div><div class='add'>+		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32,</div><div class='add'>+			   lower_32_bits(val)),</div><div class='add'>+		FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64,</div><div class='add'>+			   upper_32_bits(val)),</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, len &lt;= 2);</div><div class='add'>+	xe_assert(xe, len != 1 || !upper_32_bits(val));</div><div class='add'>+</div><div class='add'>+	/* Self config must go over MMIO */</div><div class='add'>+	ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request));</div><div class='add'>+</div><div class='add'>+	if (unlikely(ret &lt; 0))</div><div class='add'>+		return ret;</div><div class='add'>+	if (unlikely(ret &gt; 1))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	if (unlikely(!ret))</div><div class='add'>+		return -ENOKEY;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val)</div><div class='add'>+{</div><div class='add'>+	return guc_self_cfg(guc, key, 1, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val)</div><div class='add'>+{</div><div class='add'>+	return guc_self_cfg(guc, key, 2, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir)</div><div class='add'>+{</div><div class='add'>+	if (iir &amp; GUC_INTR_GUC2HOST)</div><div class='add'>+		xe_guc_ct_irq_handler(&amp;guc-&gt;ct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_sanitize(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	xe_uc_fw_change_status(&amp;guc-&gt;fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+	xe_guc_ct_disable(&amp;guc-&gt;ct);</div><div class='add'>+	guc-&gt;submission_state.enabled = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_reset_prepare(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return xe_guc_submit_reset_prepare(guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_reset_wait(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	xe_guc_submit_reset_wait(guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_stop_prepare(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(xe_guc_pc_stop(&amp;guc-&gt;pc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_stop(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_disable(&amp;guc-&gt;ct);</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_submit_stop(guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_start(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_start(&amp;guc-&gt;pc);</div><div class='add'>+	XE_WARN_ON(ret);</div><div class='add'>+</div><div class='add'>+	return xe_guc_submit_start(guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 status;</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_print(&amp;guc-&gt;fw, p);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	status = xe_mmio_read32(gt, GUC_STATUS);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nGuC status 0x%08x:\n", status);</div><div class='add'>+	drm_printf(p, "\tBootrom status = 0x%x\n",</div><div class='add'>+		   REG_FIELD_GET(GS_BOOTROM_MASK, status));</div><div class='add'>+	drm_printf(p, "\tuKernel status = 0x%x\n",</div><div class='add'>+		   REG_FIELD_GET(GS_UKERNEL_MASK, status));</div><div class='add'>+	drm_printf(p, "\tMIA Core status = 0x%x\n",</div><div class='add'>+		   REG_FIELD_GET(GS_MIA_MASK, status));</div><div class='add'>+	drm_printf(p, "\tLog level = %d\n",</div><div class='add'>+		   xe_guc_log_get_level(&amp;guc-&gt;log));</div><div class='add'>+</div><div class='add'>+	drm_puts(p, "\nScratch registers:\n");</div><div class='add'>+	for (i = 0; i &lt; SOFT_SCRATCH_COUNT; i++) {</div><div class='add'>+		drm_printf(p, "\t%2d: \t0x%x\n",</div><div class='add'>+			   i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_print(&amp;guc-&gt;ct, p, false);</div><div class='add'>+	xe_guc_submit_print(guc, p);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_in_reset() - Detect if GuC MIA is in reset.</div><div class='add'>+ * @guc: The GuC object</div><div class='add'>+ *</div><div class='add'>+ * This function detects runtime resume from d3cold by leveraging</div><div class='add'>+ * GUC_STATUS, GUC doesn't get reset during d3hot,</div><div class='add'>+ * it strictly to be called from RPM resume handler.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if failed to get forcewake or GuC MIA is in Reset,</div><div class='add'>+ * otherwise false.</div><div class='add'>+ */</div><div class='add'>+bool xe_guc_in_reset(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	u32 status;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	status = xe_mmio_read32(gt, GUC_STATUS);</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	return  status &amp; GS_MIA_IN_RESET;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h<br/>new file mode 100644<br/>index 000000000000..d3e49e7fd7c3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc.h</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_H_</div><div class='add'>+#define _XE_GUC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc_types.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+int xe_guc_init(struct xe_guc *guc);</div><div class='add'>+int xe_guc_init_post_hwconfig(struct xe_guc *guc);</div><div class='add'>+int xe_guc_post_load_init(struct xe_guc *guc);</div><div class='add'>+int xe_guc_reset(struct xe_guc *guc);</div><div class='add'>+int xe_guc_upload(struct xe_guc *guc);</div><div class='add'>+int xe_guc_min_load_for_hwconfig(struct xe_guc *guc);</div><div class='add'>+int xe_guc_enable_communication(struct xe_guc *guc);</div><div class='add'>+int xe_guc_suspend(struct xe_guc *guc);</div><div class='add'>+void xe_guc_notify(struct xe_guc *guc);</div><div class='add'>+int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);</div><div class='add'>+int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);</div><div class='add'>+int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len,</div><div class='add'>+			  u32 *response_buf);</div><div class='add'>+int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);</div><div class='add'>+int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);</div><div class='add'>+void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);</div><div class='add'>+void xe_guc_sanitize(struct xe_guc *guc);</div><div class='add'>+void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p);</div><div class='add'>+int xe_guc_reset_prepare(struct xe_guc *guc);</div><div class='add'>+void xe_guc_reset_wait(struct xe_guc *guc);</div><div class='add'>+void xe_guc_stop_prepare(struct xe_guc *guc);</div><div class='add'>+int xe_guc_stop(struct xe_guc *guc);</div><div class='add'>+int xe_guc_start(struct xe_guc *guc);</div><div class='add'>+bool xe_guc_in_reset(struct xe_guc *guc);</div><div class='add'>+</div><div class='add'>+static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	switch (class) {</div><div class='add'>+	case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+		return GUC_RENDER_CLASS;</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_DECODE:</div><div class='add'>+		return GUC_VIDEO_CLASS;</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:</div><div class='add'>+		return GUC_VIDEOENHANCE_CLASS;</div><div class='add'>+	case XE_ENGINE_CLASS_COPY:</div><div class='add'>+		return GUC_BLITTER_CLASS;</div><div class='add'>+	case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+		return GUC_COMPUTE_CLASS;</div><div class='add'>+	case XE_ENGINE_CLASS_OTHER:</div><div class='add'>+		return GUC_GSC_OTHER_CLASS;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON(class);</div><div class='add'>+		return -1;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return container_of(guc, struct xe_gt, uc.guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_device *guc_to_xe(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(guc_to_gt(guc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c<br/>new file mode 100644<br/>index 000000000000..390e6f1bf4e1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ads.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads.c</a></div><div class='hunk'>@@ -0,0 +1,672 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_ads.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_guc_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_ccs_mode.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+</div><div class='add'>+/* Slack of a few additional entries per engine */</div><div class='add'>+#define ADS_REGSET_EXTRA_MAX	8</div><div class='add'>+</div><div class='add'>+static struct xe_guc *</div><div class='add'>+ads_to_guc(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return container_of(ads, struct xe_guc, ads);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+ads_to_gt(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return container_of(ads, struct xe_gt, uc.guc.ads);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+ads_to_xe(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(ads_to_gt(ads));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct iosys_map *</div><div class='add'>+ads_to_map(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return &amp;ads-&gt;bo-&gt;vmap;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* UM Queue parameters: */</div><div class='add'>+#define GUC_UM_QUEUE_SIZE       (SZ_64K)</div><div class='add'>+#define GUC_PAGE_RES_TIMEOUT_US (-1)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The Additional Data Struct (ADS) has pointers for different buffers used by</div><div class='add'>+ * the GuC. One single gem object contains the ADS struct itself (guc_ads) and</div><div class='add'>+ * all the extra buffers indirectly linked via the ADS struct's entries.</div><div class='add'>+ *</div><div class='add'>+ * Layout of the ADS blob allocated for the GuC:</div><div class='add'>+ *</div><div class='add'>+ *      +---------------------------------------+ &lt;== base</div><div class='add'>+ *      | guc_ads                               |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | guc_policies                          |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | guc_gt_system_info                    |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | guc_engine_usage                      |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | guc_um_init_params                    |</div><div class='add'>+ *      +---------------------------------------+ &lt;== static</div><div class='add'>+ *      | guc_mmio_reg[countA] (engine 0.0)     |</div><div class='add'>+ *      | guc_mmio_reg[countB] (engine 0.1)     |</div><div class='add'>+ *      | guc_mmio_reg[countC] (engine 1.0)     |</div><div class='add'>+ *      |   ...                                 |</div><div class='add'>+ *      +---------------------------------------+ &lt;== dynamic</div><div class='add'>+ *      | padding                               |</div><div class='add'>+ *      +---------------------------------------+ &lt;== 4K aligned</div><div class='add'>+ *      | golden contexts                       |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | padding                               |</div><div class='add'>+ *      +---------------------------------------+ &lt;== 4K aligned</div><div class='add'>+ *      | capture lists                         |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | padding                               |</div><div class='add'>+ *      +---------------------------------------+ &lt;== 4K aligned</div><div class='add'>+ *      | UM queues                             |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | padding                               |</div><div class='add'>+ *      +---------------------------------------+ &lt;== 4K aligned</div><div class='add'>+ *      | private data                          |</div><div class='add'>+ *      +---------------------------------------+</div><div class='add'>+ *      | padding                               |</div><div class='add'>+ *      +---------------------------------------+ &lt;== 4K aligned</div><div class='add'>+ */</div><div class='add'>+struct __guc_ads_blob {</div><div class='add'>+	struct guc_ads ads;</div><div class='add'>+	struct guc_policies policies;</div><div class='add'>+	struct guc_gt_system_info system_info;</div><div class='add'>+	struct guc_engine_usage engine_usage;</div><div class='add'>+	struct guc_um_init_params um_init_params;</div><div class='add'>+	/* From here on, location is dynamic! Refer to above diagram. */</div><div class='add'>+	struct guc_mmio_reg regset[0];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#define ads_blob_read(ads_, field_) \</div><div class='add'>+	xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \</div><div class='add'>+			struct __guc_ads_blob, field_)</div><div class='add'>+</div><div class='add'>+#define ads_blob_write(ads_, field_, val_)			\</div><div class='add'>+	xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0,	\</div><div class='add'>+			struct __guc_ads_blob, field_, val_)</div><div class='add'>+</div><div class='add'>+#define info_map_write(xe_, map_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_)</div><div class='add'>+</div><div class='add'>+#define info_map_read(xe_, map_, field_) \</div><div class='add'>+	xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_)</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_regset_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, ads-&gt;regset_size);</div><div class='add'>+</div><div class='add'>+	return ads-&gt;regset_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return PAGE_ALIGN(ads-&gt;golden_lrc_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_capture_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	/* FIXME: Allocate a proper capture list */</div><div class='add'>+	return PAGE_ALIGN(PAGE_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.has_usm)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return PAGE_ALIGN(ads_to_guc(ads)-&gt;fw.private_data_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_regset_offset(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return offsetof(struct __guc_ads_blob, regset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	size_t offset;</div><div class='add'>+</div><div class='add'>+	offset = guc_ads_regset_offset(ads) +</div><div class='add'>+		guc_ads_regset_size(ads);</div><div class='add'>+</div><div class='add'>+	return PAGE_ALIGN(offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	size_t offset;</div><div class='add'>+</div><div class='add'>+	offset = guc_ads_golden_lrc_offset(ads) +</div><div class='add'>+		guc_ads_golden_lrc_size(ads);</div><div class='add'>+</div><div class='add'>+	return PAGE_ALIGN(offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	offset = guc_ads_capture_offset(ads) +</div><div class='add'>+		 guc_ads_capture_size(ads);</div><div class='add'>+</div><div class='add'>+	return PAGE_ALIGN(offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	size_t offset;</div><div class='add'>+</div><div class='add'>+	offset = guc_ads_um_queues_offset(ads) +</div><div class='add'>+		guc_ads_um_queues_size(ads);</div><div class='add'>+</div><div class='add'>+	return PAGE_ALIGN(offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_ads_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	return guc_ads_private_data_offset(ads) +</div><div class='add'>+		guc_ads_private_data_size(ads);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool needs_wa_1607983814(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return GRAPHICS_VERx100(xe) &lt; 1250;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t calculate_regset_size(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr_entry *sr_entry;</div><div class='add'>+	unsigned long sr_idx;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	unsigned int count = 0;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		xa_for_each(&amp;hwe-&gt;reg_sr.xa, sr_idx, sr_entry)</div><div class='add'>+			count++;</div><div class='add'>+</div><div class='add'>+	count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES;</div><div class='add'>+</div><div class='add'>+	if (needs_wa_1607983814(gt_to_xe(gt)))</div><div class='add'>+		count += LNCFCMOCS_REG_COUNT;</div><div class='add'>+</div><div class='add'>+	return count * sizeof(struct guc_mmio_reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 mask = 0;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id)</div><div class='add'>+		if (hwe-&gt;class == class)</div><div class='add'>+			mask |= BIT(hwe-&gt;instance);</div><div class='add'>+</div><div class='add'>+	return mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	size_t total_size = 0, alloc_size, real_size;</div><div class='add'>+	int class;</div><div class='add'>+</div><div class='add'>+	for (class = 0; class &lt; XE_ENGINE_CLASS_MAX; ++class) {</div><div class='add'>+		if (!engine_enable_mask(gt, class))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		real_size = xe_lrc_size(xe, class);</div><div class='add'>+		alloc_size = PAGE_ALIGN(real_size);</div><div class='add'>+		total_size += alloc_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return total_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MAX_GOLDEN_LRC_SIZE	(SZ_4K * 64)</div><div class='add'>+</div><div class='add'>+int xe_guc_ads_init(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	ads-&gt;golden_lrc_size = calculate_golden_lrc_size(ads);</div><div class='add'>+	ads-&gt;regset_size = calculate_regset_size(gt);</div><div class='add'>+</div><div class='add'>+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+					  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	ads-&gt;bo = bo;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load</div><div class='add'>+ * @ads: Additional data structures object</div><div class='add'>+ *</div><div class='add'>+ * Recalcuate golden_lrc_size &amp; regset_size as the number hardware engines may</div><div class='add'>+ * have changed after the hwconfig was loaded. Also verify the new sizes fit in</div><div class='add'>+ * the already allocated ADS buffer object.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	u32 prev_regset_size = ads-&gt;regset_size;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, ads-&gt;bo);</div><div class='add'>+</div><div class='add'>+	ads-&gt;golden_lrc_size = calculate_golden_lrc_size(ads);</div><div class='add'>+	ads-&gt;regset_size = calculate_regset_size(gt);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, ads-&gt;golden_lrc_size +</div><div class='add'>+		     (ads-&gt;regset_size - prev_regset_size) &lt;=</div><div class='add'>+		     MAX_GOLDEN_LRC_SIZE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_policies_init(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	ads_blob_write(ads, policies.dpc_promote_time,</div><div class='add'>+		       GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);</div><div class='add'>+	ads_blob_write(ads, policies.max_num_work_items,</div><div class='add'>+		       GLOBAL_POLICY_MAX_NUM_WI);</div><div class='add'>+	ads_blob_write(ads, policies.global_flags, 0);</div><div class='add'>+	ads_blob_write(ads, policies.is_valid, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void fill_engine_enable_masks(struct xe_gt *gt,</div><div class='add'>+				     struct iosys_map *info_map)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));</div><div class='add'>+	info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));</div><div class='add'>+	info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));</div><div class='add'>+	info_map_write(xe, info_map,</div><div class='add'>+		       engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));</div><div class='add'>+	info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));</div><div class='add'>+	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],</div><div class='add'>+		       engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),</div><div class='add'>+			offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	u8 guc_class;</div><div class='add'>+</div><div class='add'>+	for (guc_class = 0; guc_class &lt;= GUC_MAX_ENGINE_CLASSES; ++guc_class) {</div><div class='add'>+		if (!info_map_read(xe, &amp;info_map,</div><div class='add'>+				   engine_enabled_masks[guc_class]))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ads_blob_write(ads, ads.eng_state_size[guc_class],</div><div class='add'>+			       guc_ads_golden_lrc_size(ads) -</div><div class='add'>+			       xe_lrc_skip_size(xe));</div><div class='add'>+		ads_blob_write(ads, ads.golden_context_lrca[guc_class],</div><div class='add'>+			       xe_bo_ggtt_addr(ads-&gt;bo) +</div><div class='add'>+			       guc_ads_golden_lrc_offset(ads));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_mapping_table_init_invalid(struct xe_gt *gt,</div><div class='add'>+					   struct iosys_map *info_map)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+</div><div class='add'>+	/* Table must be set to invalid values for entries not used */</div><div class='add'>+	for (i = 0; i &lt; GUC_MAX_ENGINE_CLASSES; ++i)</div><div class='add'>+		for (j = 0; j &lt; GUC_MAX_INSTANCES_PER_CLASS; ++j)</div><div class='add'>+			info_map_write(xe, info_map, mapping_table[i][j],</div><div class='add'>+				       GUC_MAX_INSTANCES_PER_CLASS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_mapping_table_init(struct xe_gt *gt,</div><div class='add'>+				   struct iosys_map *info_map)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	guc_mapping_table_init_invalid(gt, info_map);</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		u8 guc_class;</div><div class='add'>+</div><div class='add'>+		guc_class = xe_engine_class_to_guc_class(hwe-&gt;class);</div><div class='add'>+		info_map_write(xe, info_map,</div><div class='add'>+			       mapping_table[guc_class][hwe-&gt;logical_instance],</div><div class='add'>+			       hwe-&gt;instance);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_capture_list_init(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	int i, j;</div><div class='add'>+	u32 addr = xe_bo_ggtt_addr(ads-&gt;bo) + guc_ads_capture_offset(ads);</div><div class='add'>+</div><div class='add'>+	/* FIXME: Populate a proper capture list */</div><div class='add'>+	for (i = 0; i &lt; GUC_CAPTURE_LIST_INDEX_MAX; i++) {</div><div class='add'>+		for (j = 0; j &lt; GUC_MAX_ENGINE_CLASSES; j++) {</div><div class='add'>+			ads_blob_write(ads, ads.capture_instance[i][j], addr);</div><div class='add'>+			ads_blob_write(ads, ads.capture_class[i][j], addr);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ads_blob_write(ads, ads.capture_global[i], addr);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,</div><div class='add'>+				      struct iosys_map *regset_map,</div><div class='add'>+				      struct xe_reg reg,</div><div class='add'>+				      unsigned int n_entry)</div><div class='add'>+{</div><div class='add'>+	struct guc_mmio_reg entry = {</div><div class='add'>+		.offset = reg.addr,</div><div class='add'>+		.flags = reg.masked ? GUC_REGSET_MASKED : 0,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),</div><div class='add'>+			 &amp;entry, sizeof(entry));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,</div><div class='add'>+					  struct iosys_map *regset_map,</div><div class='add'>+					  struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_hw_engine *hwe_rcs_reset_domain =</div><div class='add'>+		xe_gt_any_hw_engine_by_reset_domain(hwe-&gt;gt, XE_ENGINE_CLASS_RENDER);</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	unsigned long idx;</div><div class='add'>+	unsigned int count = 0;</div><div class='add'>+	const struct {</div><div class='add'>+		struct xe_reg reg;</div><div class='add'>+		bool skip;</div><div class='add'>+	} *e, extra_regs[] = {</div><div class='add'>+		{ .reg = RING_MODE(hwe-&gt;mmio_base),			},</div><div class='add'>+		{ .reg = RING_HWS_PGA(hwe-&gt;mmio_base),			},</div><div class='add'>+		{ .reg = RING_IMR(hwe-&gt;mmio_base),			},</div><div class='add'>+		{ .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain	},</div><div class='add'>+		{ .reg = CCS_MODE,</div><div class='add'>+		  .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe-&gt;gt) },</div><div class='add'>+	};</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(ARRAY_SIZE(extra_regs) &gt; ADS_REGSET_EXTRA_MAX);</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;hwe-&gt;reg_sr.xa, idx, entry)</div><div class='add'>+		guc_mmio_regset_write_one(ads, regset_map, entry-&gt;reg, count++);</div><div class='add'>+</div><div class='add'>+	for (e = extra_regs; e &lt; extra_regs + ARRAY_SIZE(extra_regs); e++) {</div><div class='add'>+		if (e-&gt;skip)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		guc_mmio_regset_write_one(ads, regset_map, e-&gt;reg, count++);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wa_1607983814 */</div><div class='add'>+	if (needs_wa_1607983814(xe) &amp;&amp; hwe-&gt;class == XE_ENGINE_CLASS_RENDER) {</div><div class='add'>+		for (i = 0; i &lt; LNCFCMOCS_REG_COUNT; i++) {</div><div class='add'>+			guc_mmio_regset_write_one(ads, regset_map,</div><div class='add'>+						  XELP_LNCFCMOCS(i), count++);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	size_t regset_offset = guc_ads_regset_offset(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 addr = xe_bo_ggtt_addr(ads-&gt;bo) + regset_offset;</div><div class='add'>+	struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),</div><div class='add'>+							    regset_offset);</div><div class='add'>+	unsigned int regset_used = 0;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		unsigned int count;</div><div class='add'>+		u8 gc;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 1. Write all MMIO entries for this exec queue to the table. No</div><div class='add'>+		 * need to worry about fused-off engines and when there are</div><div class='add'>+		 * entries in the regset: the reg_state_list has been zero'ed</div><div class='add'>+		 * by xe_guc_ads_populate()</div><div class='add'>+		 */</div><div class='add'>+		count = guc_mmio_regset_write(ads, &amp;regset_map, hwe);</div><div class='add'>+		if (!count)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * 2. Record in the header (ads.reg_state_list) the address</div><div class='add'>+		 * location and number of entries</div><div class='add'>+		 */</div><div class='add'>+		gc = xe_engine_class_to_guc_class(hwe-&gt;class);</div><div class='add'>+		ads_blob_write(ads, ads.reg_state_list[gc][hwe-&gt;instance].address, addr);</div><div class='add'>+		ads_blob_write(ads, ads.reg_state_list[gc][hwe-&gt;instance].count, count);</div><div class='add'>+</div><div class='add'>+		addr += count * sizeof(struct guc_mmio_reg);</div><div class='add'>+		iosys_map_incr(&amp;regset_map, count * sizeof(struct guc_mmio_reg));</div><div class='add'>+</div><div class='add'>+		regset_used += count * sizeof(struct guc_mmio_reg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, regset_used &lt;= ads-&gt;regset_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_um_init_params(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	u32 um_queue_offset = guc_ads_um_queues_offset(ads);</div><div class='add'>+	u64 base_dpa;</div><div class='add'>+	u32 base_ggtt;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	base_ggtt = xe_bo_ggtt_addr(ads-&gt;bo) + um_queue_offset;</div><div class='add'>+	base_dpa = xe_bo_main_addr(ads-&gt;bo, PAGE_SIZE) + um_queue_offset;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; GUC_UM_HW_QUEUE_MAX; ++i) {</div><div class='add'>+		ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,</div><div class='add'>+			       base_dpa + (i * GUC_UM_QUEUE_SIZE));</div><div class='add'>+		ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,</div><div class='add'>+			       base_ggtt + (i * GUC_UM_QUEUE_SIZE));</div><div class='add'>+		ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,</div><div class='add'>+			       GUC_UM_QUEUE_SIZE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ads_blob_write(ads, um_init_params.page_response_timeout_in_us,</div><div class='add'>+		       GUC_PAGE_RES_TIMEOUT_US);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_doorbell_init(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VER(xe) &gt;= 12 &amp;&amp; !IS_DGFX(xe)) {</div><div class='add'>+		u32 distdbreg =</div><div class='add'>+			xe_mmio_read32(gt, DIST_DBS_POPULATED);</div><div class='add'>+</div><div class='add'>+		ads_blob_write(ads,</div><div class='add'>+			       system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],</div><div class='add'>+			       REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ads_populate_minimal - populate minimal ADS</div><div class='add'>+ * @ads: Additional data structures object</div><div class='add'>+ *</div><div class='add'>+ * This function populates a minimal ADS that does not support submissions but</div><div class='add'>+ * enough so the GuC can load and the hwconfig table can be read.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),</div><div class='add'>+			offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	u32 base = xe_bo_ggtt_addr(ads-&gt;bo);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, ads-&gt;bo);</div><div class='add'>+</div><div class='add'>+	xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads-&gt;bo-&gt;size);</div><div class='add'>+	guc_policies_init(ads);</div><div class='add'>+	guc_prep_golden_lrc_null(ads);</div><div class='add'>+	guc_mapping_table_init_invalid(gt, &amp;info_map);</div><div class='add'>+	guc_doorbell_init(ads);</div><div class='add'>+</div><div class='add'>+	ads_blob_write(ads, ads.scheduler_policies, base +</div><div class='add'>+		       offsetof(struct __guc_ads_blob, policies));</div><div class='add'>+	ads_blob_write(ads, ads.gt_system_info, base +</div><div class='add'>+		       offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	ads_blob_write(ads, ads.private_data, base +</div><div class='add'>+		       guc_ads_private_data_offset(ads));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_ads_populate(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),</div><div class='add'>+			offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	u32 base = xe_bo_ggtt_addr(ads-&gt;bo);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, ads-&gt;bo);</div><div class='add'>+</div><div class='add'>+	xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads-&gt;bo-&gt;size);</div><div class='add'>+	guc_policies_init(ads);</div><div class='add'>+	fill_engine_enable_masks(gt, &amp;info_map);</div><div class='add'>+	guc_mmio_reg_state_init(ads);</div><div class='add'>+	guc_prep_golden_lrc_null(ads);</div><div class='add'>+	guc_mapping_table_init(gt, &amp;info_map);</div><div class='add'>+	guc_capture_list_init(ads);</div><div class='add'>+	guc_doorbell_init(ads);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.has_usm) {</div><div class='add'>+		guc_um_init_params(ads);</div><div class='add'>+		ads_blob_write(ads, ads.um_init_data, base +</div><div class='add'>+			       offsetof(struct __guc_ads_blob, um_init_params));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ads_blob_write(ads, ads.scheduler_policies, base +</div><div class='add'>+		       offsetof(struct __guc_ads_blob, policies));</div><div class='add'>+	ads_blob_write(ads, ads.gt_system_info, base +</div><div class='add'>+		       offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	ads_blob_write(ads, ads.private_data, base +</div><div class='add'>+		       guc_ads_private_data_offset(ads));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_populate_golden_lrc(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ads_to_xe(ads);</div><div class='add'>+	struct xe_gt *gt = ads_to_gt(ads);</div><div class='add'>+	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),</div><div class='add'>+			offsetof(struct __guc_ads_blob, system_info));</div><div class='add'>+	size_t total_size = 0, alloc_size, real_size;</div><div class='add'>+	u32 addr_ggtt, offset;</div><div class='add'>+	int class;</div><div class='add'>+</div><div class='add'>+	offset = guc_ads_golden_lrc_offset(ads);</div><div class='add'>+	addr_ggtt = xe_bo_ggtt_addr(ads-&gt;bo) + offset;</div><div class='add'>+</div><div class='add'>+	for (class = 0; class &lt; XE_ENGINE_CLASS_MAX; ++class) {</div><div class='add'>+		u8 guc_class;</div><div class='add'>+</div><div class='add'>+		guc_class = xe_engine_class_to_guc_class(class);</div><div class='add'>+</div><div class='add'>+		if (!info_map_read(xe, &amp;info_map,</div><div class='add'>+				   engine_enabled_masks[guc_class]))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		xe_gt_assert(gt, gt-&gt;default_lrc[class]);</div><div class='add'>+</div><div class='add'>+		real_size = xe_lrc_size(xe, class);</div><div class='add'>+		alloc_size = PAGE_ALIGN(real_size);</div><div class='add'>+		total_size += alloc_size;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This interface is slightly confusing. We need to pass the</div><div class='add'>+		 * base address of the full golden context and the size of just</div><div class='add'>+		 * the engine state, which is the section of the context image</div><div class='add'>+		 * that starts after the execlists LRC registers. This is</div><div class='add'>+		 * required to allow the GuC to restore just the engine state</div><div class='add'>+		 * when a watchdog reset occurs.</div><div class='add'>+		 * We calculate the engine state size by removing the size of</div><div class='add'>+		 * what comes before it in the context image (which is identical</div><div class='add'>+		 * on all engines).</div><div class='add'>+		 */</div><div class='add'>+		ads_blob_write(ads, ads.eng_state_size[guc_class],</div><div class='add'>+			       real_size - xe_lrc_skip_size(xe));</div><div class='add'>+		ads_blob_write(ads, ads.golden_context_lrca[guc_class],</div><div class='add'>+			       addr_ggtt);</div><div class='add'>+</div><div class='add'>+		xe_map_memcpy_to(xe, ads_to_map(ads), offset,</div><div class='add'>+				 gt-&gt;default_lrc[class], real_size);</div><div class='add'>+</div><div class='add'>+		addr_ggtt += alloc_size;</div><div class='add'>+		offset += alloc_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, total_size == ads-&gt;golden_lrc_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads)</div><div class='add'>+{</div><div class='add'>+	guc_populate_golden_lrc(ads);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ads.h b/drivers/gpu/drm/xe/xe_guc_ads.h<br/>new file mode 100644<br/>index 000000000000..138ef6267671<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ads.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_ADS_H_</div><div class='add'>+#define _XE_GUC_ADS_H_</div><div class='add'>+</div><div class='add'>+#include "xe_guc_ads_types.h"</div><div class='add'>+</div><div class='add'>+int xe_guc_ads_init(struct xe_guc_ads *ads);</div><div class='add'>+int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads);</div><div class='add'>+void xe_guc_ads_populate(struct xe_guc_ads *ads);</div><div class='add'>+void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads);</div><div class='add'>+void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h<br/>new file mode 100644<br/>index 000000000000..4afe44bece4b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ads_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ads_types.h</a></div><div class='hunk'>@@ -0,0 +1,25 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_ADS_TYPES_H_</div><div class='add'>+#define _XE_GUC_ADS_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_ads - GuC additional data structures (ADS)</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_ads {</div><div class='add'>+	/** @bo: XE BO for GuC ads blob */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	/** @golden_lrc_size: golden LRC size */</div><div class='add'>+	size_t golden_lrc_size;</div><div class='add'>+	/** @regset_size: size of register set passed to GuC for save/restore */</div><div class='add'>+	u32 regset_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c<br/>new file mode 100644<br/>index 000000000000..24a33fa36496<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ct.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct.c</a></div><div class='hunk'>@@ -0,0 +1,1320 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/circ_buf.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "abi/guc_klvs_abi.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_pagefault.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_submit.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+</div><div class='add'>+/* Used when a CT send wants to block and / or receive data */</div><div class='add'>+struct g2h_fence {</div><div class='add'>+	u32 *response_buffer;</div><div class='add'>+	u32 seqno;</div><div class='add'>+	u16 response_len;</div><div class='add'>+	u16 error;</div><div class='add'>+	u16 hint;</div><div class='add'>+	u16 reason;</div><div class='add'>+	bool retry;</div><div class='add'>+	bool fail;</div><div class='add'>+	bool done;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer)</div><div class='add'>+{</div><div class='add'>+	g2h_fence-&gt;response_buffer = response_buffer;</div><div class='add'>+	g2h_fence-&gt;response_len = 0;</div><div class='add'>+	g2h_fence-&gt;fail = false;</div><div class='add'>+	g2h_fence-&gt;retry = false;</div><div class='add'>+	g2h_fence-&gt;done = false;</div><div class='add'>+	g2h_fence-&gt;seqno = ~0x0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)</div><div class='add'>+{</div><div class='add'>+	return g2h_fence-&gt;seqno == ~0x0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_guc *</div><div class='add'>+ct_to_guc(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	return container_of(ct, struct xe_guc, ct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+ct_to_gt(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	return container_of(ct, struct xe_gt, uc.guc.ct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+ct_to_xe(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(ct_to_gt(ct));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC CTB Blob</div><div class='add'>+ *</div><div class='add'>+ * We allocate single blob to hold both CTB descriptors and buffers:</div><div class='add'>+ *</div><div class='add'>+ *      +--------+-----------------------------------------------+------+</div><div class='add'>+ *      | offset | contents                                      | size |</div><div class='add'>+ *      +========+===============================================+======+</div><div class='add'>+ *      | 0x0000 | H2G CTB Descriptor (send)                     |      |</div><div class='add'>+ *      +--------+-----------------------------------------------+  4K  |</div><div class='add'>+ *      | 0x0800 | G2H CTB Descriptor (g2h)                      |      |</div><div class='add'>+ *      +--------+-----------------------------------------------+------+</div><div class='add'>+ *      | 0x1000 | H2G CT Buffer (send)                          | n*4K |</div><div class='add'>+ *      |        |                                               |      |</div><div class='add'>+ *      +--------+-----------------------------------------------+------+</div><div class='add'>+ *      | 0x1000 | G2H CT Buffer (g2h)                           | m*4K |</div><div class='add'>+ *      | + n*4K |                                               |      |</div><div class='add'>+ *      +--------+-----------------------------------------------+------+</div><div class='add'>+ *</div><div class='add'>+ * Size of each ``CT Buffer`` must be multiple of 4K.</div><div class='add'>+ * We don't expect too many messages in flight at any time, unless we are</div><div class='add'>+ * using the GuC submission. In that case each request requires a minimum</div><div class='add'>+ * 2 dwords which gives us a maximum 256 queue'd requests. Hopefully this</div><div class='add'>+ * enough space to avoid backpressure on the driver. We increase the size</div><div class='add'>+ * of the receive buffer (relative to the send) to ensure a G2H response</div><div class='add'>+ * CTB has a landing spot.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)</div><div class='add'>+#define CTB_H2G_BUFFER_SIZE	(SZ_4K)</div><div class='add'>+#define CTB_G2H_BUFFER_SIZE	(4 * CTB_H2G_BUFFER_SIZE)</div><div class='add'>+#define G2H_ROOM_BUFFER_SIZE	(CTB_G2H_BUFFER_SIZE / 4)</div><div class='add'>+</div><div class='add'>+static size_t guc_ct_size(void)</div><div class='add'>+{</div><div class='add'>+	return 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +</div><div class='add'>+		CTB_G2H_BUFFER_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_ct_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct *ct = arg;</div><div class='add'>+</div><div class='add'>+	xa_destroy(&amp;ct-&gt;fence_lookup);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void g2h_worker_func(struct work_struct *w);</div><div class='add'>+</div><div class='add'>+static void primelockdep(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	if (!IS_ENABLED(CONFIG_LOCKDEP))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fs_reclaim_acquire(GFP_KERNEL);</div><div class='add'>+	might_lock(&amp;ct-&gt;lock);</div><div class='add'>+	fs_reclaim_release(GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_init(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct xe_gt *gt = ct_to_gt(ct);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !(guc_ct_size() % PAGE_SIZE));</div><div class='add'>+</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;ct-&gt;lock);</div><div class='add'>+	spin_lock_init(&amp;ct-&gt;fast_lock);</div><div class='add'>+	xa_init(&amp;ct-&gt;fence_lookup);</div><div class='add'>+	INIT_WORK(&amp;ct-&gt;g2h_worker, g2h_worker_func);</div><div class='add'>+	init_waitqueue_head(&amp;ct-&gt;wq);</div><div class='add'>+	init_waitqueue_head(&amp;ct-&gt;g2h_fence_wq);</div><div class='add'>+</div><div class='add'>+	primelockdep(ct);</div><div class='add'>+</div><div class='add'>+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+					  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	ct-&gt;bo = bo;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, guc_ct_fini, ct);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define desc_read(xe_, guc_ctb__, field_)			\</div><div class='add'>+	xe_map_rd_field(xe_, &amp;guc_ctb__-&gt;desc, 0,		\</div><div class='add'>+			struct guc_ct_buffer_desc, field_)</div><div class='add'>+</div><div class='add'>+#define desc_write(xe_, guc_ctb__, field_, val_)		\</div><div class='add'>+	xe_map_wr_field(xe_, &amp;guc_ctb__-&gt;desc, 0,		\</div><div class='add'>+			struct guc_ct_buffer_desc, field_, val_)</div><div class='add'>+</div><div class='add'>+static void guc_ct_ctb_h2g_init(struct xe_device *xe, struct guc_ctb *h2g,</div><div class='add'>+				struct iosys_map *map)</div><div class='add'>+{</div><div class='add'>+	h2g-&gt;info.size = CTB_H2G_BUFFER_SIZE / sizeof(u32);</div><div class='add'>+	h2g-&gt;info.resv_space = 0;</div><div class='add'>+	h2g-&gt;info.tail = 0;</div><div class='add'>+	h2g-&gt;info.head = 0;</div><div class='add'>+	h2g-&gt;info.space = CIRC_SPACE(h2g-&gt;info.tail, h2g-&gt;info.head,</div><div class='add'>+				     h2g-&gt;info.size) -</div><div class='add'>+			  h2g-&gt;info.resv_space;</div><div class='add'>+	h2g-&gt;info.broken = false;</div><div class='add'>+</div><div class='add'>+	h2g-&gt;desc = *map;</div><div class='add'>+	xe_map_memset(xe, &amp;h2g-&gt;desc, 0, 0, sizeof(struct guc_ct_buffer_desc));</div><div class='add'>+</div><div class='add'>+	h2g-&gt;cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE * 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,</div><div class='add'>+				struct iosys_map *map)</div><div class='add'>+{</div><div class='add'>+	g2h-&gt;info.size = CTB_G2H_BUFFER_SIZE / sizeof(u32);</div><div class='add'>+	g2h-&gt;info.resv_space = G2H_ROOM_BUFFER_SIZE / sizeof(u32);</div><div class='add'>+	g2h-&gt;info.head = 0;</div><div class='add'>+	g2h-&gt;info.tail = 0;</div><div class='add'>+	g2h-&gt;info.space = CIRC_SPACE(g2h-&gt;info.tail, g2h-&gt;info.head,</div><div class='add'>+				     g2h-&gt;info.size) -</div><div class='add'>+			  g2h-&gt;info.resv_space;</div><div class='add'>+	g2h-&gt;info.broken = false;</div><div class='add'>+</div><div class='add'>+	g2h-&gt;desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);</div><div class='add'>+	xe_map_memset(xe, &amp;g2h-&gt;desc, 0, 0, sizeof(struct guc_ct_buffer_desc));</div><div class='add'>+</div><div class='add'>+	g2h-&gt;cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE * 2 +</div><div class='add'>+					    CTB_H2G_BUFFER_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = ct_to_guc(ct);</div><div class='add'>+	u32 desc_addr, ctb_addr, size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	desc_addr = xe_bo_ggtt_addr(ct-&gt;bo);</div><div class='add'>+	ctb_addr = xe_bo_ggtt_addr(ct-&gt;bo) + CTB_DESC_SIZE * 2;</div><div class='add'>+	size = ct-&gt;ctbs.h2g.info.size * sizeof(u32);</div><div class='add'>+</div><div class='add'>+	err = xe_guc_self_cfg64(guc,</div><div class='add'>+				GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY,</div><div class='add'>+				desc_addr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_guc_self_cfg64(guc,</div><div class='add'>+				GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY,</div><div class='add'>+				ctb_addr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return xe_guc_self_cfg32(guc,</div><div class='add'>+				 GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY,</div><div class='add'>+				 size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = ct_to_guc(ct);</div><div class='add'>+	u32 desc_addr, ctb_addr, size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	desc_addr = xe_bo_ggtt_addr(ct-&gt;bo) + CTB_DESC_SIZE;</div><div class='add'>+	ctb_addr = xe_bo_ggtt_addr(ct-&gt;bo) + CTB_DESC_SIZE * 2 +</div><div class='add'>+		CTB_H2G_BUFFER_SIZE;</div><div class='add'>+	size = ct-&gt;ctbs.g2h.info.size * sizeof(u32);</div><div class='add'>+</div><div class='add'>+	err = xe_guc_self_cfg64(guc,</div><div class='add'>+				GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY,</div><div class='add'>+				desc_addr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_guc_self_cfg64(guc,</div><div class='add'>+				GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY,</div><div class='add'>+				ctb_addr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return xe_guc_self_cfg32(guc,</div><div class='add'>+				 GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY,</div><div class='add'>+				 size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_ct_control_toggle(struct xe_guc_ct *ct, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 request[HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN] = {</div><div class='add'>+		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |</div><div class='add'>+		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |</div><div class='add'>+		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION,</div><div class='add'>+			   GUC_ACTION_HOST2GUC_CONTROL_CTB),</div><div class='add'>+		FIELD_PREP(HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL,</div><div class='add'>+			   enable ? GUC_CTB_CONTROL_ENABLE :</div><div class='add'>+			   GUC_CTB_CONTROL_DISABLE),</div><div class='add'>+	};</div><div class='add'>+	int ret = xe_guc_mmio_send(ct_to_guc(ct), request, ARRAY_SIZE(request));</div><div class='add'>+</div><div class='add'>+	return ret &gt; 0 ? -EPROTO : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_enable(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !ct-&gt;enabled);</div><div class='add'>+</div><div class='add'>+	guc_ct_ctb_h2g_init(xe, &amp;ct-&gt;ctbs.h2g, &amp;ct-&gt;bo-&gt;vmap);</div><div class='add'>+	guc_ct_ctb_g2h_init(xe, &amp;ct-&gt;ctbs.g2h, &amp;ct-&gt;bo-&gt;vmap);</div><div class='add'>+</div><div class='add'>+	err = guc_ct_ctb_h2g_register(ct);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	err = guc_ct_ctb_g2h_register(ct);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	err = guc_ct_control_toggle(ct, true);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ct-&gt;lock);</div><div class='add'>+	spin_lock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	ct-&gt;g2h_outstanding = 0;</div><div class='add'>+	ct-&gt;enabled = true;</div><div class='add'>+	spin_unlock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	mutex_unlock(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	smp_mb();</div><div class='add'>+	wake_up_all(&amp;ct-&gt;wq);</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "GuC CT communication channel enabled\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "Failed to enable CT (%d)\n", err);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_ct_disable(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;ct-&gt;lock); /* Serialise dequeue_one_g2h() */</div><div class='add'>+	spin_lock_irq(&amp;ct-&gt;fast_lock); /* Serialise CT fast-path */</div><div class='add'>+	ct-&gt;enabled = false; /* Finally disable CT communication */</div><div class='add'>+	spin_unlock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	mutex_unlock(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	xa_destroy(&amp;ct-&gt;fence_lookup);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool h2g_has_room(struct xe_guc_ct *ct, u32 cmd_len)</div><div class='add'>+{</div><div class='add'>+	struct guc_ctb *h2g = &amp;ct-&gt;ctbs.h2g;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (cmd_len &gt; h2g-&gt;info.space) {</div><div class='add'>+		h2g-&gt;info.head = desc_read(ct_to_xe(ct), h2g, head);</div><div class='add'>+		h2g-&gt;info.space = CIRC_SPACE(h2g-&gt;info.tail, h2g-&gt;info.head,</div><div class='add'>+					     h2g-&gt;info.size) -</div><div class='add'>+				  h2g-&gt;info.resv_space;</div><div class='add'>+		if (cmd_len &gt; h2g-&gt;info.space)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool g2h_has_room(struct xe_guc_ct *ct, u32 g2h_len)</div><div class='add'>+{</div><div class='add'>+	if (!g2h_len)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;fast_lock);</div><div class='add'>+</div><div class='add'>+	return ct-&gt;ctbs.g2h.info.space &gt; g2h_len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int has_room(struct xe_guc_ct *ct, u32 cmd_len, u32 g2h_len)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (!g2h_has_room(ct, g2h_len) || !h2g_has_room(ct, cmd_len))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void h2g_reserve_space(struct xe_guc_ct *ct, u32 cmd_len)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+	ct-&gt;ctbs.h2g.info.space -= cmd_len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __g2h_reserve_space(struct xe_guc_ct *ct, u32 g2h_len, u32 num_g2h)</div><div class='add'>+{</div><div class='add'>+	xe_assert(ct_to_xe(ct), g2h_len &lt;= ct-&gt;ctbs.g2h.info.space);</div><div class='add'>+</div><div class='add'>+	if (g2h_len) {</div><div class='add'>+		lockdep_assert_held(&amp;ct-&gt;fast_lock);</div><div class='add'>+</div><div class='add'>+		ct-&gt;ctbs.g2h.info.space -= g2h_len;</div><div class='add'>+		ct-&gt;g2h_outstanding += num_g2h;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __g2h_release_space(struct xe_guc_ct *ct, u32 g2h_len)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;fast_lock);</div><div class='add'>+	xe_assert(ct_to_xe(ct), ct-&gt;ctbs.g2h.info.space + g2h_len &lt;=</div><div class='add'>+		  ct-&gt;ctbs.g2h.info.size - ct-&gt;ctbs.g2h.info.resv_space);</div><div class='add'>+</div><div class='add'>+	ct-&gt;ctbs.g2h.info.space += g2h_len;</div><div class='add'>+	--ct-&gt;g2h_outstanding;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void g2h_release_space(struct xe_guc_ct *ct, u32 g2h_len)</div><div class='add'>+{</div><div class='add'>+	spin_lock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	__g2h_release_space(ct, g2h_len);</div><div class='add'>+	spin_unlock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define H2G_CT_HEADERS (GUC_CTB_HDR_LEN + 1) /* one DW CTB header and one DW HxG header */</div><div class='add'>+</div><div class='add'>+static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+		     u32 ct_fence_value, bool want_response)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct guc_ctb *h2g = &amp;ct-&gt;ctbs.h2g;</div><div class='add'>+	u32 cmd[H2G_CT_HEADERS];</div><div class='add'>+	u32 tail = h2g-&gt;info.tail;</div><div class='add'>+	u32 full_len;</div><div class='add'>+	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&amp;h2g-&gt;cmds,</div><div class='add'>+							 tail * sizeof(u32));</div><div class='add'>+</div><div class='add'>+	full_len = len + GUC_CTB_HDR_LEN;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+	xe_assert(xe, full_len &lt;= GUC_CTB_MSG_MAX_LEN);</div><div class='add'>+	xe_assert(xe, tail &lt;= h2g-&gt;info.size);</div><div class='add'>+</div><div class='add'>+	/* Command will wrap, zero fill (NOPs), return and check credits again */</div><div class='add'>+	if (tail + full_len &gt; h2g-&gt;info.size) {</div><div class='add'>+		xe_map_memset(xe, &amp;map, 0, 0,</div><div class='add'>+			      (h2g-&gt;info.size - tail) * sizeof(u32));</div><div class='add'>+		h2g_reserve_space(ct, (h2g-&gt;info.size - tail));</div><div class='add'>+		h2g-&gt;info.tail = 0;</div><div class='add'>+		desc_write(xe, h2g, tail, h2g-&gt;info.tail);</div><div class='add'>+</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * dw0: CT header (including fence)</div><div class='add'>+	 * dw1: HXG header (including action code)</div><div class='add'>+	 * dw2+: action data</div><div class='add'>+	 */</div><div class='add'>+	cmd[0] = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, GUC_CTB_FORMAT_HXG) |</div><div class='add'>+		FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |</div><div class='add'>+		FIELD_PREP(GUC_CTB_MSG_0_FENCE, ct_fence_value);</div><div class='add'>+	if (want_response) {</div><div class='add'>+		cmd[1] =</div><div class='add'>+			FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |</div><div class='add'>+			FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |</div><div class='add'>+				   GUC_HXG_EVENT_MSG_0_DATA0, action[0]);</div><div class='add'>+	} else {</div><div class='add'>+		cmd[1] =</div><div class='add'>+			FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) |</div><div class='add'>+			FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |</div><div class='add'>+				   GUC_HXG_EVENT_MSG_0_DATA0, action[0]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* H2G header in cmd[1] replaces action[0] so: */</div><div class='add'>+	--len;</div><div class='add'>+	++action;</div><div class='add'>+</div><div class='add'>+	/* Write H2G ensuring visable before descriptor update */</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;map, 0, cmd, H2G_CT_HEADERS * sizeof(u32));</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;map, H2G_CT_HEADERS * sizeof(u32), action, len * sizeof(u32));</div><div class='add'>+	xe_device_wmb(xe);</div><div class='add'>+</div><div class='add'>+	/* Update local copies */</div><div class='add'>+	h2g-&gt;info.tail = (tail + full_len) % h2g-&gt;info.size;</div><div class='add'>+	h2g_reserve_space(ct, full_len);</div><div class='add'>+</div><div class='add'>+	/* Update descriptor */</div><div class='add'>+	desc_write(xe, h2g, tail, h2g-&gt;info.tail);</div><div class='add'>+</div><div class='add'>+	trace_xe_guc_ctb_h2g(ct_to_gt(ct)-&gt;info.id, *(action - 1), full_len,</div><div class='add'>+			     desc_read(xe, h2g, head), h2g-&gt;info.tail);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __guc_ct_send_locked(struct xe_guc_ct *ct, const u32 *action,</div><div class='add'>+				u32 len, u32 g2h_len, u32 num_g2h,</div><div class='add'>+				struct g2h_fence *g2h_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !g2h_len || !g2h_fence);</div><div class='add'>+	xe_assert(xe, !num_g2h || !g2h_fence);</div><div class='add'>+	xe_assert(xe, !g2h_len || num_g2h);</div><div class='add'>+	xe_assert(xe, g2h_len || !num_g2h);</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (unlikely(ct-&gt;ctbs.h2g.info.broken)) {</div><div class='add'>+		ret = -EPIPE;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (unlikely(!ct-&gt;enabled)) {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (g2h_fence) {</div><div class='add'>+		g2h_len = GUC_CTB_HXG_MSG_MAX_LEN;</div><div class='add'>+		num_g2h = 1;</div><div class='add'>+</div><div class='add'>+		if (g2h_fence_needs_alloc(g2h_fence)) {</div><div class='add'>+			void *ptr;</div><div class='add'>+</div><div class='add'>+			g2h_fence-&gt;seqno = (ct-&gt;fence_seqno++ &amp; 0xffff);</div><div class='add'>+			ptr = xa_store(&amp;ct-&gt;fence_lookup,</div><div class='add'>+				       g2h_fence-&gt;seqno,</div><div class='add'>+				       g2h_fence, GFP_ATOMIC);</div><div class='add'>+			if (IS_ERR(ptr)) {</div><div class='add'>+				ret = PTR_ERR(ptr);</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (g2h_len)</div><div class='add'>+		spin_lock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+retry:</div><div class='add'>+	ret = has_room(ct, len + GUC_CTB_HDR_LEN, g2h_len);</div><div class='add'>+	if (unlikely(ret))</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	ret = h2g_write(ct, action, len, g2h_fence ? g2h_fence-&gt;seqno : 0,</div><div class='add'>+			!!g2h_fence);</div><div class='add'>+	if (unlikely(ret)) {</div><div class='add'>+		if (ret == -EAGAIN)</div><div class='add'>+			goto retry;</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	__g2h_reserve_space(ct, g2h_len, num_g2h);</div><div class='add'>+	xe_guc_notify(ct_to_guc(ct));</div><div class='add'>+out_unlock:</div><div class='add'>+	if (g2h_len)</div><div class='add'>+		spin_unlock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+out:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void kick_reset(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	xe_gt_reset_async(ct_to_gt(ct));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dequeue_one_g2h(struct xe_guc_ct *ct);</div><div class='add'>+</div><div class='add'>+static int guc_ct_send_locked(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			      u32 g2h_len, u32 num_g2h,</div><div class='add'>+			      struct g2h_fence *g2h_fence)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *drm = &amp;ct_to_xe(ct)-&gt;drm;</div><div class='add'>+	struct drm_printer p = drm_info_printer(drm-&gt;dev);</div><div class='add'>+	unsigned int sleep_period_ms = 1;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_assert(ct_to_xe(ct), !g2h_len || !g2h_fence);</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+	xe_device_assert_mem_access(ct_to_xe(ct));</div><div class='add'>+</div><div class='add'>+try_again:</div><div class='add'>+	ret = __guc_ct_send_locked(ct, action, len, g2h_len, num_g2h,</div><div class='add'>+				   g2h_fence);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We wait to try to restore credits for about 1 second before bailing.</div><div class='add'>+	 * In the case of H2G credits we have no choice but just to wait for the</div><div class='add'>+	 * GuC to consume H2Gs in the channel so we use a wait / sleep loop. In</div><div class='add'>+	 * the case of G2H we process any G2H in the channel, hopefully freeing</div><div class='add'>+	 * credits as we consume the G2H messages.</div><div class='add'>+	 */</div><div class='add'>+	if (unlikely(ret == -EBUSY &amp;&amp;</div><div class='add'>+		     !h2g_has_room(ct, len + GUC_CTB_HDR_LEN))) {</div><div class='add'>+		struct guc_ctb *h2g = &amp;ct-&gt;ctbs.h2g;</div><div class='add'>+</div><div class='add'>+		if (sleep_period_ms == 1024)</div><div class='add'>+			goto broken;</div><div class='add'>+</div><div class='add'>+		trace_xe_guc_ct_h2g_flow_control(h2g-&gt;info.head, h2g-&gt;info.tail,</div><div class='add'>+						 h2g-&gt;info.size,</div><div class='add'>+						 h2g-&gt;info.space,</div><div class='add'>+						 len + GUC_CTB_HDR_LEN);</div><div class='add'>+		msleep(sleep_period_ms);</div><div class='add'>+		sleep_period_ms &lt;&lt;= 1;</div><div class='add'>+</div><div class='add'>+		goto try_again;</div><div class='add'>+	} else if (unlikely(ret == -EBUSY)) {</div><div class='add'>+		struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+		struct guc_ctb *g2h = &amp;ct-&gt;ctbs.g2h;</div><div class='add'>+</div><div class='add'>+		trace_xe_guc_ct_g2h_flow_control(g2h-&gt;info.head,</div><div class='add'>+						 desc_read(xe, g2h, tail),</div><div class='add'>+						 g2h-&gt;info.size,</div><div class='add'>+						 g2h-&gt;info.space,</div><div class='add'>+						 g2h_fence ?</div><div class='add'>+						 GUC_CTB_HXG_MSG_MAX_LEN :</div><div class='add'>+						 g2h_len);</div><div class='add'>+</div><div class='add'>+#define g2h_avail(ct)	\</div><div class='add'>+	(desc_read(ct_to_xe(ct), (&amp;ct-&gt;ctbs.g2h), tail) != ct-&gt;ctbs.g2h.info.head)</div><div class='add'>+		if (!wait_event_timeout(ct-&gt;wq, !ct-&gt;g2h_outstanding ||</div><div class='add'>+					g2h_avail(ct), HZ))</div><div class='add'>+			goto broken;</div><div class='add'>+#undef g2h_avail</div><div class='add'>+</div><div class='add'>+		if (dequeue_one_g2h(ct) &lt; 0)</div><div class='add'>+			goto broken;</div><div class='add'>+</div><div class='add'>+		goto try_again;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+broken:</div><div class='add'>+	drm_err(drm, "No forward process on H2G, reset required");</div><div class='add'>+	xe_guc_ct_print(ct, &amp;p, true);</div><div class='add'>+	ct-&gt;ctbs.h2g.info.broken = true;</div><div class='add'>+</div><div class='add'>+	return -EDEADLK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_ct_send(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+		       u32 g2h_len, u32 num_g2h, struct g2h_fence *g2h_fence)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_assert(ct_to_xe(ct), !g2h_len || !g2h_fence);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;ct-&gt;lock);</div><div class='add'>+	ret = guc_ct_send_locked(ct, action, len, g2h_len, num_g2h, g2h_fence);</div><div class='add'>+	mutex_unlock(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_send(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+		   u32 g2h_len, u32 num_g2h)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = guc_ct_send(ct, action, len, g2h_len, num_g2h, NULL);</div><div class='add'>+	if (ret == -EDEADLK)</div><div class='add'>+		kick_reset(ct);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_send_locked(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			  u32 g2h_len, u32 num_g2h)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = guc_ct_send_locked(ct, action, len, g2h_len, num_g2h, NULL);</div><div class='add'>+	if (ret == -EDEADLK)</div><div class='add'>+		kick_reset(ct);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_send_g2h_handler(struct xe_guc_ct *ct, const u32 *action, u32 len)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ret = guc_ct_send_locked(ct, action, len, 0, 0, NULL);</div><div class='add'>+	if (ret == -EDEADLK)</div><div class='add'>+		kick_reset(ct);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Check if a GT reset is in progress or will occur and if GT reset brought the</div><div class='add'>+ * CT back up. Randomly picking 5 seconds for an upper limit to do a GT a reset.</div><div class='add'>+ */</div><div class='add'>+static bool retry_failure(struct xe_guc_ct *ct, int ret)</div><div class='add'>+{</div><div class='add'>+	if (!(ret == -EDEADLK || ret == -EPIPE || ret == -ENODEV))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+#define ct_alive(ct)	\</div><div class='add'>+	(ct-&gt;enabled &amp;&amp; !ct-&gt;ctbs.h2g.info.broken &amp;&amp; !ct-&gt;ctbs.g2h.info.broken)</div><div class='add'>+	if (!wait_event_interruptible_timeout(ct-&gt;wq, ct_alive(ct),  HZ * 5))</div><div class='add'>+		return false;</div><div class='add'>+#undef ct_alive</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			    u32 *response_buffer, bool no_fail)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct g2h_fence g2h_fence;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We use a fence to implement blocking sends / receiving response data.</div><div class='add'>+	 * The seqno of the fence is sent in the H2G, returned in the G2H, and</div><div class='add'>+	 * an xarray is used as storage media with the seqno being to key.</div><div class='add'>+	 * Fields in the fence hold success, failure, retry status and the</div><div class='add'>+	 * response data. Safe to allocate on the stack as the xarray is the</div><div class='add'>+	 * only reference and it cannot be present after this function exits.</div><div class='add'>+	 */</div><div class='add'>+retry:</div><div class='add'>+	g2h_fence_init(&amp;g2h_fence, response_buffer);</div><div class='add'>+retry_same_fence:</div><div class='add'>+	ret = guc_ct_send(ct, action, len, 0, 0, &amp;g2h_fence);</div><div class='add'>+	if (unlikely(ret == -ENOMEM)) {</div><div class='add'>+		void *ptr;</div><div class='add'>+</div><div class='add'>+		/* Retry allocation /w GFP_KERNEL */</div><div class='add'>+		ptr = xa_store(&amp;ct-&gt;fence_lookup,</div><div class='add'>+			       g2h_fence.seqno,</div><div class='add'>+			       &amp;g2h_fence, GFP_KERNEL);</div><div class='add'>+		if (IS_ERR(ptr))</div><div class='add'>+			return PTR_ERR(ptr);</div><div class='add'>+</div><div class='add'>+		goto retry_same_fence;</div><div class='add'>+	} else if (unlikely(ret)) {</div><div class='add'>+		if (ret == -EDEADLK)</div><div class='add'>+			kick_reset(ct);</div><div class='add'>+</div><div class='add'>+		if (no_fail &amp;&amp; retry_failure(ct, ret))</div><div class='add'>+			goto retry_same_fence;</div><div class='add'>+</div><div class='add'>+		if (!g2h_fence_needs_alloc(&amp;g2h_fence))</div><div class='add'>+			xa_erase_irq(&amp;ct-&gt;fence_lookup, g2h_fence.seqno);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wait_event_timeout(ct-&gt;g2h_fence_wq, g2h_fence.done, HZ);</div><div class='add'>+	if (!ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Timed out wait for G2H, fence %u, action %04x",</div><div class='add'>+			g2h_fence.seqno, action[0]);</div><div class='add'>+		xa_erase_irq(&amp;ct-&gt;fence_lookup, g2h_fence.seqno);</div><div class='add'>+		return -ETIME;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (g2h_fence.retry) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Send retry, action 0x%04x, reason %d",</div><div class='add'>+			 action[0], g2h_fence.reason);</div><div class='add'>+		goto retry;</div><div class='add'>+	}</div><div class='add'>+	if (g2h_fence.fail) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Send failed, action 0x%04x, error %d, hint %d",</div><div class='add'>+			action[0], g2h_fence.error, g2h_fence.hint);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret &gt; 0 ? 0 : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			u32 *response_buffer)</div><div class='add'>+{</div><div class='add'>+	return guc_ct_send_recv(ct, action, len, response_buffer, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_send_recv_no_fail(struct xe_guc_ct *ct, const u32 *action,</div><div class='add'>+				u32 len, u32 *response_buffer)</div><div class='add'>+{</div><div class='add'>+	return guc_ct_send_recv(ct, action, len, response_buffer, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_g2h_event(struct xe_guc_ct *ct, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	u32 action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, msg[1]);</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	switch (action) {</div><div class='add'>+	case XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:</div><div class='add'>+	case XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE:</div><div class='add'>+	case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE:</div><div class='add'>+	case XE_GUC_ACTION_TLB_INVALIDATION_DONE:</div><div class='add'>+		g2h_release_space(ct, len);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	u32 response_len = len - GUC_CTB_MSG_MIN_LEN;</div><div class='add'>+	u32 fence = FIELD_GET(GUC_CTB_MSG_0_FENCE, msg[0]);</div><div class='add'>+	u32 type = FIELD_GET(GUC_HXG_MSG_0_TYPE, msg[1]);</div><div class='add'>+	struct g2h_fence *g2h_fence;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	g2h_fence = xa_erase(&amp;ct-&gt;fence_lookup, fence);</div><div class='add'>+	if (unlikely(!g2h_fence)) {</div><div class='add'>+		/* Don't tear down channel, as send could've timed out */</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "G2H fence (%u) not found!\n", fence);</div><div class='add'>+		g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, fence == g2h_fence-&gt;seqno);</div><div class='add'>+</div><div class='add'>+	if (type == GUC_HXG_TYPE_RESPONSE_FAILURE) {</div><div class='add'>+		g2h_fence-&gt;fail = true;</div><div class='add'>+		g2h_fence-&gt;error =</div><div class='add'>+			FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, msg[1]);</div><div class='add'>+		g2h_fence-&gt;hint =</div><div class='add'>+			FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, msg[1]);</div><div class='add'>+	} else if (type == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {</div><div class='add'>+		g2h_fence-&gt;retry = true;</div><div class='add'>+		g2h_fence-&gt;reason =</div><div class='add'>+			FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, msg[1]);</div><div class='add'>+	} else if (g2h_fence-&gt;response_buffer) {</div><div class='add'>+		g2h_fence-&gt;response_len = response_len;</div><div class='add'>+		memcpy(g2h_fence-&gt;response_buffer, msg + GUC_CTB_MSG_MIN_LEN,</div><div class='add'>+		       response_len * sizeof(u32));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);</div><div class='add'>+</div><div class='add'>+	g2h_fence-&gt;done = true;</div><div class='add'>+	smp_mb();</div><div class='add'>+</div><div class='add'>+	wake_up_all(&amp;ct-&gt;g2h_fence_wq);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	u32 hxg, origin, type;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	hxg = msg[1];</div><div class='add'>+</div><div class='add'>+	origin = FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg);</div><div class='add'>+	if (unlikely(origin != GUC_HXG_ORIGIN_GUC)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm,</div><div class='add'>+			"G2H channel broken on read, origin=%d, reset required\n",</div><div class='add'>+			origin);</div><div class='add'>+		ct-&gt;ctbs.g2h.info.broken = true;</div><div class='add'>+</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	type = FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg);</div><div class='add'>+	switch (type) {</div><div class='add'>+	case GUC_HXG_TYPE_EVENT:</div><div class='add'>+		ret = parse_g2h_event(ct, msg, len);</div><div class='add'>+		break;</div><div class='add'>+	case GUC_HXG_TYPE_RESPONSE_SUCCESS:</div><div class='add'>+	case GUC_HXG_TYPE_RESPONSE_FAILURE:</div><div class='add'>+	case GUC_HXG_TYPE_NO_RESPONSE_RETRY:</div><div class='add'>+		ret = parse_g2h_response(ct, msg, len);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_err(&amp;xe-&gt;drm,</div><div class='add'>+			"G2H channel broken on read, type=%d, reset required\n",</div><div class='add'>+			type);</div><div class='add'>+		ct-&gt;ctbs.g2h.info.broken = true;</div><div class='add'>+</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct xe_guc *guc = ct_to_guc(ct);</div><div class='add'>+	u32 action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, msg[1]);</div><div class='add'>+	u32 *payload = msg + GUC_CTB_HXG_MSG_MIN_LEN;</div><div class='add'>+	u32 adj_len = len - GUC_CTB_HXG_MSG_MIN_LEN;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, msg[1]) != GUC_HXG_TYPE_EVENT)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (action) {</div><div class='add'>+	case XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:</div><div class='add'>+		ret = xe_guc_sched_done_handler(guc, payload, adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE:</div><div class='add'>+		ret = xe_guc_deregister_done_handler(guc, payload, adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION:</div><div class='add'>+		ret = xe_guc_exec_queue_reset_handler(guc, payload, adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:</div><div class='add'>+		ret = xe_guc_exec_queue_reset_failure_handler(guc, payload,</div><div class='add'>+							      adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE:</div><div class='add'>+		/* Selftest only at the moment */</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION:</div><div class='add'>+	case XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE:</div><div class='add'>+		/* FIXME: Handle this */</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR:</div><div class='add'>+		ret = xe_guc_exec_queue_memory_cat_error_handler(guc, payload,</div><div class='add'>+								 adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC:</div><div class='add'>+		ret = xe_guc_pagefault_handler(guc, payload, adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_TLB_INVALIDATION_DONE:</div><div class='add'>+		ret = xe_guc_tlb_invalidation_done_handler(guc, payload,</div><div class='add'>+							   adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY:</div><div class='add'>+		ret = xe_guc_access_counter_notify_handler(guc, payload,</div><div class='add'>+							   adj_len);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "unexpected action 0x%04x\n", action);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "action 0x%04x failed processing, ret=%d\n",</div><div class='add'>+			action, ret);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int g2h_read(struct xe_guc_ct *ct, u32 *msg, bool fast_path)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct guc_ctb *g2h = &amp;ct-&gt;ctbs.g2h;</div><div class='add'>+	u32 tail, head, len;</div><div class='add'>+	s32 avail;</div><div class='add'>+	u32 action;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;fast_lock);</div><div class='add'>+</div><div class='add'>+	if (!ct-&gt;enabled)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	if (g2h-&gt;info.broken)</div><div class='add'>+		return -EPIPE;</div><div class='add'>+</div><div class='add'>+	/* Calculate DW available to read */</div><div class='add'>+	tail = desc_read(xe, g2h, tail);</div><div class='add'>+	avail = tail - g2h-&gt;info.head;</div><div class='add'>+	if (unlikely(avail == 0))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (avail &lt; 0)</div><div class='add'>+		avail += g2h-&gt;info.size;</div><div class='add'>+</div><div class='add'>+	/* Read header */</div><div class='add'>+	xe_map_memcpy_from(xe, msg, &amp;g2h-&gt;cmds, sizeof(u32) * g2h-&gt;info.head,</div><div class='add'>+			   sizeof(u32));</div><div class='add'>+	len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, msg[0]) + GUC_CTB_MSG_MIN_LEN;</div><div class='add'>+	if (len &gt; avail) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm,</div><div class='add'>+			"G2H channel broken on read, avail=%d, len=%d, reset required\n",</div><div class='add'>+			avail, len);</div><div class='add'>+		g2h-&gt;info.broken = true;</div><div class='add'>+</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	head = (g2h-&gt;info.head + 1) % g2h-&gt;info.size;</div><div class='add'>+	avail = len - 1;</div><div class='add'>+</div><div class='add'>+	/* Read G2H message */</div><div class='add'>+	if (avail + head &gt; g2h-&gt;info.size) {</div><div class='add'>+		u32 avail_til_wrap = g2h-&gt;info.size - head;</div><div class='add'>+</div><div class='add'>+		xe_map_memcpy_from(xe, msg + 1,</div><div class='add'>+				   &amp;g2h-&gt;cmds, sizeof(u32) * head,</div><div class='add'>+				   avail_til_wrap * sizeof(u32));</div><div class='add'>+		xe_map_memcpy_from(xe, msg + 1 + avail_til_wrap,</div><div class='add'>+				   &amp;g2h-&gt;cmds, 0,</div><div class='add'>+				   (avail - avail_til_wrap) * sizeof(u32));</div><div class='add'>+	} else {</div><div class='add'>+		xe_map_memcpy_from(xe, msg + 1,</div><div class='add'>+				   &amp;g2h-&gt;cmds, sizeof(u32) * head,</div><div class='add'>+				   avail * sizeof(u32));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, msg[1]);</div><div class='add'>+</div><div class='add'>+	if (fast_path) {</div><div class='add'>+		if (FIELD_GET(GUC_HXG_MSG_0_TYPE, msg[1]) != GUC_HXG_TYPE_EVENT)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		switch (action) {</div><div class='add'>+		case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC:</div><div class='add'>+		case XE_GUC_ACTION_TLB_INVALIDATION_DONE:</div><div class='add'>+			break;	/* Process these in fast-path */</div><div class='add'>+		default:</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Update local / descriptor header */</div><div class='add'>+	g2h-&gt;info.head = (head + avail) % g2h-&gt;info.size;</div><div class='add'>+	desc_write(xe, g2h, head, g2h-&gt;info.head);</div><div class='add'>+</div><div class='add'>+	trace_xe_guc_ctb_g2h(ct_to_gt(ct)-&gt;info.id, action, len,</div><div class='add'>+			     g2h-&gt;info.head, tail);</div><div class='add'>+</div><div class='add'>+	return len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void g2h_fast_path(struct xe_guc_ct *ct, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct xe_guc *guc = ct_to_guc(ct);</div><div class='add'>+	u32 action = FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, msg[1]);</div><div class='add'>+	u32 *payload = msg + GUC_CTB_HXG_MSG_MIN_LEN;</div><div class='add'>+	u32 adj_len = len - GUC_CTB_HXG_MSG_MIN_LEN;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	switch (action) {</div><div class='add'>+	case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC:</div><div class='add'>+		ret = xe_guc_pagefault_handler(guc, payload, adj_len);</div><div class='add'>+		break;</div><div class='add'>+	case XE_GUC_ACTION_TLB_INVALIDATION_DONE:</div><div class='add'>+		__g2h_release_space(ct, len);</div><div class='add'>+		ret = xe_guc_tlb_invalidation_done_handler(guc, payload,</div><div class='add'>+							   adj_len);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "NOT_POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "action 0x%04x failed processing, ret=%d\n",</div><div class='add'>+			action, ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ct_fast_path - process critical G2H in the IRQ handler</div><div class='add'>+ * @ct: GuC CT object</div><div class='add'>+ *</div><div class='add'>+ * Anything related to page faults is critical for performance, process these</div><div class='add'>+ * critical G2H in the IRQ. This is safe as these handlers either just wake up</div><div class='add'>+ * waiters or queue another worker.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_ct_fast_path(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	bool ongoing;</div><div class='add'>+	int len;</div><div class='add'>+</div><div class='add'>+	ongoing = xe_device_mem_access_get_if_ongoing(ct_to_xe(ct));</div><div class='add'>+	if (!ongoing &amp;&amp; xe_pm_read_callback_task(ct_to_xe(ct)) == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;ct-&gt;fast_lock);</div><div class='add'>+	do {</div><div class='add'>+		len = g2h_read(ct, ct-&gt;fast_msg, true);</div><div class='add'>+		if (len &gt; 0)</div><div class='add'>+			g2h_fast_path(ct, ct-&gt;fast_msg, len);</div><div class='add'>+	} while (len &gt; 0);</div><div class='add'>+	spin_unlock(&amp;ct-&gt;fast_lock);</div><div class='add'>+</div><div class='add'>+	if (ongoing)</div><div class='add'>+		xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Returns less than zero on error, 0 on done, 1 on more available */</div><div class='add'>+static int dequeue_one_g2h(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	int len;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	len = g2h_read(ct, ct-&gt;msg, false);</div><div class='add'>+	spin_unlock_irq(&amp;ct-&gt;fast_lock);</div><div class='add'>+	if (len &lt;= 0)</div><div class='add'>+		return len;</div><div class='add'>+</div><div class='add'>+	ret = parse_g2h_msg(ct, ct-&gt;msg, len);</div><div class='add'>+	if (unlikely(ret &lt; 0))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = process_g2h_msg(ct, ct-&gt;msg, len);</div><div class='add'>+	if (unlikely(ret &lt; 0))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void g2h_worker_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct *ct = container_of(w, struct xe_guc_ct, g2h_worker);</div><div class='add'>+	bool ongoing;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Normal users must always hold mem_access.ref around CT calls. However</div><div class='add'>+	 * during the runtime pm callbacks we rely on CT to talk to the GuC, but</div><div class='add'>+	 * at this stage we can't rely on mem_access.ref and even the</div><div class='add'>+	 * callback_task will be different than current.  For such cases we just</div><div class='add'>+	 * need to ensure we always process the responses from any blocking</div><div class='add'>+	 * ct_send requests or where we otherwise expect some response when</div><div class='add'>+	 * initiated from those callbacks (which will need to wait for the below</div><div class='add'>+	 * dequeue_one_g2h()).  The dequeue_one_g2h() will gracefully fail if</div><div class='add'>+	 * the device has suspended to the point that the CT communication has</div><div class='add'>+	 * been disabled.</div><div class='add'>+	 *</div><div class='add'>+	 * If we are inside the runtime pm callback, we can be the only task</div><div class='add'>+	 * still issuing CT requests (since that requires having the</div><div class='add'>+	 * mem_access.ref).  It seems like it might in theory be possible to</div><div class='add'>+	 * receive unsolicited events from the GuC just as we are</div><div class='add'>+	 * suspending-resuming, but those will currently anyway be lost when</div><div class='add'>+	 * eventually exiting from suspend, hence no need to wake up the device</div><div class='add'>+	 * here. If we ever need something stronger than get_if_ongoing() then</div><div class='add'>+	 * we need to be careful with blocking the pm callbacks from getting CT</div><div class='add'>+	 * responses, if the worker here is blocked on those callbacks</div><div class='add'>+	 * completing, creating a deadlock.</div><div class='add'>+	 */</div><div class='add'>+	ongoing = xe_device_mem_access_get_if_ongoing(ct_to_xe(ct));</div><div class='add'>+	if (!ongoing &amp;&amp; xe_pm_read_callback_task(ct_to_xe(ct)) == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		mutex_lock(&amp;ct-&gt;lock);</div><div class='add'>+		ret = dequeue_one_g2h(ct);</div><div class='add'>+		mutex_unlock(&amp;ct-&gt;lock);</div><div class='add'>+</div><div class='add'>+		if (unlikely(ret == -EPROTO || ret == -EOPNOTSUPP)) {</div><div class='add'>+			struct drm_device *drm = &amp;ct_to_xe(ct)-&gt;drm;</div><div class='add'>+			struct drm_printer p = drm_info_printer(drm-&gt;dev);</div><div class='add'>+</div><div class='add'>+			xe_guc_ct_print(ct, &amp;p, false);</div><div class='add'>+			kick_reset(ct);</div><div class='add'>+		}</div><div class='add'>+	} while (ret == 1);</div><div class='add'>+</div><div class='add'>+	if (ongoing)</div><div class='add'>+		xe_device_mem_access_put(ct_to_xe(ct));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_ctb_snapshot_capture(struct xe_device *xe, struct guc_ctb *ctb,</div><div class='add'>+				     struct guc_ctb_snapshot *snapshot,</div><div class='add'>+				     bool atomic)</div><div class='add'>+{</div><div class='add'>+	u32 head, tail;</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_from(xe, &amp;snapshot-&gt;desc, &amp;ctb-&gt;desc, 0,</div><div class='add'>+			   sizeof(struct guc_ct_buffer_desc));</div><div class='add'>+	memcpy(&amp;snapshot-&gt;info, &amp;ctb-&gt;info, sizeof(struct guc_ctb_info));</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;cmds = kmalloc_array(ctb-&gt;info.size, sizeof(u32),</div><div class='add'>+				       atomic ? GFP_ATOMIC : GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!snapshot-&gt;cmds) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Skipping CTB commands snapshot. Only CTB info will be available.\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	head = snapshot-&gt;desc.head;</div><div class='add'>+	tail = snapshot-&gt;desc.tail;</div><div class='add'>+</div><div class='add'>+	if (head != tail) {</div><div class='add'>+		struct iosys_map map =</div><div class='add'>+			IOSYS_MAP_INIT_OFFSET(&amp;ctb-&gt;cmds, head * sizeof(u32));</div><div class='add'>+</div><div class='add'>+		while (head != tail) {</div><div class='add'>+			snapshot-&gt;cmds[head] = xe_map_rd(xe, &amp;map, 0, u32);</div><div class='add'>+			++head;</div><div class='add'>+			if (head == ctb-&gt;info.size) {</div><div class='add'>+				head = 0;</div><div class='add'>+				map = ctb-&gt;cmds;</div><div class='add'>+			} else {</div><div class='add'>+				iosys_map_incr(&amp;map, sizeof(u32));</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_ctb_snapshot_print(struct guc_ctb_snapshot *snapshot,</div><div class='add'>+				   struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	u32 head, tail;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\tsize: %d\n", snapshot-&gt;info.size);</div><div class='add'>+	drm_printf(p, "\tresv_space: %d\n", snapshot-&gt;info.resv_space);</div><div class='add'>+	drm_printf(p, "\thead: %d\n", snapshot-&gt;info.head);</div><div class='add'>+	drm_printf(p, "\ttail: %d\n", snapshot-&gt;info.tail);</div><div class='add'>+	drm_printf(p, "\tspace: %d\n", snapshot-&gt;info.space);</div><div class='add'>+	drm_printf(p, "\tbroken: %d\n", snapshot-&gt;info.broken);</div><div class='add'>+	drm_printf(p, "\thead (memory): %d\n", snapshot-&gt;desc.head);</div><div class='add'>+	drm_printf(p, "\ttail (memory): %d\n", snapshot-&gt;desc.tail);</div><div class='add'>+	drm_printf(p, "\tstatus (memory): 0x%x\n", snapshot-&gt;desc.status);</div><div class='add'>+</div><div class='add'>+	if (!snapshot-&gt;cmds)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	head = snapshot-&gt;desc.head;</div><div class='add'>+	tail = snapshot-&gt;desc.tail;</div><div class='add'>+</div><div class='add'>+	while (head != tail) {</div><div class='add'>+		drm_printf(p, "\tcmd[%d]: 0x%08x\n", head,</div><div class='add'>+			   snapshot-&gt;cmds[head]);</div><div class='add'>+		++head;</div><div class='add'>+		if (head == snapshot-&gt;info.size)</div><div class='add'>+			head = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_ctb_snapshot_free(struct guc_ctb_snapshot *snapshot)</div><div class='add'>+{</div><div class='add'>+	kfree(snapshot-&gt;cmds);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ct_snapshot_capture - Take a quick snapshot of the CT state.</div><div class='add'>+ * @ct: GuC CT object.</div><div class='add'>+ * @atomic: Boolean to indicate if this is called from atomic context like</div><div class='add'>+ * reset or CTB handler or from some regular path like debugfs.</div><div class='add'>+ *</div><div class='add'>+ * This can be printed out in a later stage like during dev_coredump</div><div class='add'>+ * analysis.</div><div class='add'>+ *</div><div class='add'>+ * Returns: a GuC CT snapshot object that must be freed by the caller</div><div class='add'>+ * by using `xe_guc_ct_snapshot_free`.</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_ct_snapshot *xe_guc_ct_snapshot_capture(struct xe_guc_ct *ct,</div><div class='add'>+						      bool atomic)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = ct_to_xe(ct);</div><div class='add'>+	struct xe_guc_ct_snapshot *snapshot;</div><div class='add'>+</div><div class='add'>+	snapshot = kzalloc(sizeof(*snapshot),</div><div class='add'>+			   atomic ? GFP_ATOMIC : GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (!snapshot) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Skipping CTB snapshot entirely.\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ct-&gt;enabled) {</div><div class='add'>+		snapshot-&gt;ct_enabled = true;</div><div class='add'>+		snapshot-&gt;g2h_outstanding = READ_ONCE(ct-&gt;g2h_outstanding);</div><div class='add'>+		guc_ctb_snapshot_capture(xe, &amp;ct-&gt;ctbs.h2g,</div><div class='add'>+					 &amp;snapshot-&gt;h2g, atomic);</div><div class='add'>+		guc_ctb_snapshot_capture(xe, &amp;ct-&gt;ctbs.g2h,</div><div class='add'>+					 &amp;snapshot-&gt;g2h, atomic);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return snapshot;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ct_snapshot_print - Print out a given GuC CT snapshot.</div><div class='add'>+ * @snapshot: GuC CT snapshot object.</div><div class='add'>+ * @p: drm_printer where it will be printed out.</div><div class='add'>+ *</div><div class='add'>+ * This function prints out a given GuC CT snapshot object.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot,</div><div class='add'>+			      struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (snapshot-&gt;ct_enabled) {</div><div class='add'>+		drm_puts(p, "\nH2G CTB (all sizes in DW):\n");</div><div class='add'>+		guc_ctb_snapshot_print(&amp;snapshot-&gt;h2g, p);</div><div class='add'>+</div><div class='add'>+		drm_puts(p, "\nG2H CTB (all sizes in DW):\n");</div><div class='add'>+		guc_ctb_snapshot_print(&amp;snapshot-&gt;g2h, p);</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "\tg2h outstanding: %d\n",</div><div class='add'>+			   snapshot-&gt;g2h_outstanding);</div><div class='add'>+	} else {</div><div class='add'>+		drm_puts(p, "\nCT disabled\n");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ct_snapshot_free - Free all allocated objects for a given snapshot.</div><div class='add'>+ * @snapshot: GuC CT snapshot object.</div><div class='add'>+ *</div><div class='add'>+ * This function free all the memory that needed to be allocated at capture</div><div class='add'>+ * time.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot)</div><div class='add'>+{</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	guc_ctb_snapshot_free(&amp;snapshot-&gt;h2g);</div><div class='add'>+	guc_ctb_snapshot_free(&amp;snapshot-&gt;g2h);</div><div class='add'>+	kfree(snapshot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_ct_print - GuC CT Print.</div><div class='add'>+ * @ct: GuC CT.</div><div class='add'>+ * @p: drm_printer where it will be printed out.</div><div class='add'>+ * @atomic: Boolean to indicate if this is called from atomic context like</div><div class='add'>+ * reset or CTB handler or from some regular path like debugfs.</div><div class='add'>+ *</div><div class='add'>+ * This function quickly capture a snapshot and immediately print it out.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool atomic)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct_snapshot *snapshot;</div><div class='add'>+</div><div class='add'>+	snapshot = xe_guc_ct_snapshot_capture(ct, atomic);</div><div class='add'>+	xe_guc_ct_snapshot_print(snapshot, p);</div><div class='add'>+	xe_guc_ct_snapshot_free(snapshot);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h<br/>new file mode 100644<br/>index 000000000000..f15f8a4857e0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ct.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct.h</a></div><div class='hunk'>@@ -0,0 +1,59 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_CT_H_</div><div class='add'>+#define _XE_GUC_CT_H_</div><div class='add'>+</div><div class='add'>+#include "xe_guc_ct_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+int xe_guc_ct_init(struct xe_guc_ct *ct);</div><div class='add'>+int xe_guc_ct_enable(struct xe_guc_ct *ct);</div><div class='add'>+void xe_guc_ct_disable(struct xe_guc_ct *ct);</div><div class='add'>+void xe_guc_ct_fast_path(struct xe_guc_ct *ct);</div><div class='add'>+</div><div class='add'>+struct xe_guc_ct_snapshot *</div><div class='add'>+xe_guc_ct_snapshot_capture(struct xe_guc_ct *ct, bool atomic);</div><div class='add'>+void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot,</div><div class='add'>+			      struct drm_printer *p);</div><div class='add'>+void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot);</div><div class='add'>+void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool atomic);</div><div class='add'>+</div><div class='add'>+static inline void xe_guc_ct_irq_handler(struct xe_guc_ct *ct)</div><div class='add'>+{</div><div class='add'>+	wake_up_all(&amp;ct-&gt;wq);</div><div class='add'>+	if (ct-&gt;enabled)</div><div class='add'>+		queue_work(system_unbound_wq, &amp;ct-&gt;g2h_worker);</div><div class='add'>+	xe_guc_ct_fast_path(ct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Basic CT send / receives */</div><div class='add'>+int xe_guc_ct_send(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+		   u32 g2h_len, u32 num_g2h);</div><div class='add'>+int xe_guc_ct_send_locked(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			  u32 g2h_len, u32 num_g2h);</div><div class='add'>+int xe_guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,</div><div class='add'>+			u32 *response_buffer);</div><div class='add'>+static inline int</div><div class='add'>+xe_guc_ct_send_block(struct xe_guc_ct *ct, const u32 *action, u32 len)</div><div class='add'>+{</div><div class='add'>+	return xe_guc_ct_send_recv(ct, action, len, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This is only version of the send CT you can call from a G2H handler */</div><div class='add'>+int xe_guc_ct_send_g2h_handler(struct xe_guc_ct *ct, const u32 *action,</div><div class='add'>+			       u32 len);</div><div class='add'>+</div><div class='add'>+/* Can't fail because a GT reset is in progress */</div><div class='add'>+int xe_guc_ct_send_recv_no_fail(struct xe_guc_ct *ct, const u32 *action,</div><div class='add'>+				u32 len, u32 *response_buffer);</div><div class='add'>+static inline int</div><div class='add'>+xe_guc_ct_send_block_no_fail(struct xe_guc_ct *ct, const u32 *action, u32 len)</div><div class='add'>+{</div><div class='add'>+	return xe_guc_ct_send_recv_no_fail(ct, action, len, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h<br/>new file mode 100644<br/>index 000000000000..d814d4ee3fc6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_ct_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_ct_types.h</a></div><div class='hunk'>@@ -0,0 +1,115 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_CT_TYPES_H_</div><div class='add'>+#define _XE_GUC_CT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/iosys-map.h&gt;</div><div class='add'>+#include &lt;linux/spinlock_types.h&gt;</div><div class='add'>+#include &lt;linux/wait.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_communication_ctb_abi.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct guc_ctb_info - GuC command transport buffer (CTB) info</div><div class='add'>+ */</div><div class='add'>+struct guc_ctb_info {</div><div class='add'>+	/** @size: size of CTB commands (DW) */</div><div class='add'>+	u32 size;</div><div class='add'>+	/** @resv_space: reserved space of CTB commands (DW) */</div><div class='add'>+	u32 resv_space;</div><div class='add'>+	/** @head: head of CTB commands (DW) */</div><div class='add'>+	u32 head;</div><div class='add'>+	/** @tail: tail of CTB commands (DW) */</div><div class='add'>+	u32 tail;</div><div class='add'>+	/** @space: space in CTB commands (DW) */</div><div class='add'>+	u32 space;</div><div class='add'>+	/** @broken: channel broken */</div><div class='add'>+	bool broken;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct guc_ctb - GuC command transport buffer (CTB)</div><div class='add'>+ */</div><div class='add'>+struct guc_ctb {</div><div class='add'>+	/** @desc: dma buffer map for CTB descriptor */</div><div class='add'>+	struct iosys_map desc;</div><div class='add'>+	/** @cmds: dma buffer map for CTB commands */</div><div class='add'>+	struct iosys_map cmds;</div><div class='add'>+	/** @info: CTB info */</div><div class='add'>+	struct guc_ctb_info info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct guc_ctb_snapshot - GuC command transport buffer (CTB) snapshot</div><div class='add'>+ */</div><div class='add'>+struct guc_ctb_snapshot {</div><div class='add'>+	/** @desc: snapshot of the CTB descriptor */</div><div class='add'>+	struct guc_ct_buffer_desc desc;</div><div class='add'>+	/** @cmds: snapshot of the CTB commands */</div><div class='add'>+	u32 *cmds;</div><div class='add'>+	/** @info: snapshot of the CTB info */</div><div class='add'>+	struct guc_ctb_info info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_ct_snapshot - GuC command transport (CT) snapshot</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_ct_snapshot {</div><div class='add'>+	/** @ct_enabled: CT enabled info at capture time. */</div><div class='add'>+	bool ct_enabled;</div><div class='add'>+	/** @g2h_outstanding: G2H outstanding info at the capture time */</div><div class='add'>+	u32 g2h_outstanding;</div><div class='add'>+	/** @g2h: G2H CTB snapshot */</div><div class='add'>+	struct guc_ctb_snapshot g2h;</div><div class='add'>+	/** @h2g: H2G CTB snapshot */</div><div class='add'>+	struct guc_ctb_snapshot h2g;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_ct - GuC command transport (CT) layer</div><div class='add'>+ *</div><div class='add'>+ * Includes a pair of CT buffers for bi-directional communication and tracking</div><div class='add'>+ * for the H2G and G2H requests sent and received through the buffers.</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_ct {</div><div class='add'>+	/** @bo: XE BO for CT */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	/** @lock: protects everything in CT layer */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	/** @fast_lock: protects G2H channel and credits */</div><div class='add'>+	spinlock_t fast_lock;</div><div class='add'>+	/** @ctbs: buffers for sending and receiving commands */</div><div class='add'>+	struct {</div><div class='add'>+		/** @send: Host to GuC (H2G, send) channel */</div><div class='add'>+		struct guc_ctb h2g;</div><div class='add'>+		/** @recv: GuC to Host (G2H, receive) channel */</div><div class='add'>+		struct guc_ctb g2h;</div><div class='add'>+	} ctbs;</div><div class='add'>+	/** @g2h_outstanding: number of outstanding G2H */</div><div class='add'>+	u32 g2h_outstanding;</div><div class='add'>+	/** @g2h_worker: worker to process G2H messages */</div><div class='add'>+	struct work_struct g2h_worker;</div><div class='add'>+	/** @enabled: CT enabled */</div><div class='add'>+	bool enabled;</div><div class='add'>+	/** @fence_seqno: G2H fence seqno - 16 bits used by CT */</div><div class='add'>+	u32 fence_seqno;</div><div class='add'>+	/** @fence_lookup: G2H fence lookup */</div><div class='add'>+	struct xarray fence_lookup;</div><div class='add'>+	/** @wq: wait queue used for reliable CT sends and freeing G2H credits */</div><div class='add'>+	wait_queue_head_t wq;</div><div class='add'>+	/** @g2h_fence_wq: wait queue used for G2H fencing */</div><div class='add'>+	wait_queue_head_t g2h_fence_wq;</div><div class='add'>+	/** @msg: Message buffer */</div><div class='add'>+	u32 msg[GUC_CTB_MSG_MAX_LEN];</div><div class='add'>+	/** @fast_msg: Message buffer */</div><div class='add'>+	u32 fast_msg[GUC_CTB_MSG_MAX_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_debugfs.c b/drivers/gpu/drm/xe/xe_guc_debugfs.c<br/>new file mode 100644<br/>index 000000000000..ffd7d53bcc42<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_debugfs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_debugfs.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_guc_log.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+static struct xe_guc *node_to_guc(struct drm_info_node *node)</div><div class='add'>+{</div><div class='add'>+	return node-&gt;info_ent-&gt;data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_info(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = node_to_guc(m-&gt;private);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_guc_print_info(guc, &amp;p);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_log(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = node_to_guc(m-&gt;private);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_guc_log_print(&amp;guc-&gt;log, &amp;p);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_info_list debugfs_list[] = {</div><div class='add'>+	{"guc_info", guc_info, 0},</div><div class='add'>+	{"guc_log", guc_log, 0},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_guc_debugfs_register(struct xe_guc *guc, struct dentry *parent)</div><div class='add'>+{</div><div class='add'>+	struct drm_minor *minor = guc_to_xe(guc)-&gt;drm.primary;</div><div class='add'>+	struct drm_info_list *local;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+#define DEBUGFS_SIZE	(ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))</div><div class='add'>+	local = drmm_kmalloc(&amp;guc_to_xe(guc)-&gt;drm, DEBUGFS_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!local)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memcpy(local, debugfs_list, DEBUGFS_SIZE);</div><div class='add'>+#undef DEBUGFS_SIZE</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(debugfs_list); ++i)</div><div class='add'>+		local[i].data = guc;</div><div class='add'>+</div><div class='add'>+	drm_debugfs_create_files(local,</div><div class='add'>+				 ARRAY_SIZE(debugfs_list),</div><div class='add'>+				 parent, minor);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_debugfs.h b/drivers/gpu/drm/xe/xe_guc_debugfs.h<br/>new file mode 100644<br/>index 000000000000..4756dff26fca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_DEBUGFS_H_</div><div class='add'>+#define _XE_GUC_DEBUGFS_H_</div><div class='add'>+</div><div class='add'>+struct dentry;</div><div class='add'>+struct xe_guc;</div><div class='add'>+</div><div class='add'>+void xe_guc_debugfs_register(struct xe_guc *guc, struct dentry *parent);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h<br/>new file mode 100644<br/>index 000000000000..4c39f01e4f52<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_exec_queue_types.h</a></div><div class='hunk'>@@ -0,0 +1,54 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_ENGINE_TYPES_H_</div><div class='add'>+#define _XE_GUC_ENGINE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gpu_scheduler_types.h"</div><div class='add'>+</div><div class='add'>+struct dma_fence;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_exec_queue - GuC specific state for an xe_exec_queue</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_exec_queue {</div><div class='add'>+	/** @q: Backpointer to parent xe_exec_queue */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	/** @sched: GPU scheduler for this xe_exec_queue */</div><div class='add'>+	struct xe_gpu_scheduler sched;</div><div class='add'>+	/** @entity: Scheduler entity for this xe_exec_queue */</div><div class='add'>+	struct xe_sched_entity entity;</div><div class='add'>+	/**</div><div class='add'>+	 * @static_msgs: Static messages for this xe_exec_queue, used when</div><div class='add'>+	 * a message needs to sent through the GPU scheduler but memory</div><div class='add'>+	 * allocations are not allowed.</div><div class='add'>+	 */</div><div class='add'>+#define MAX_STATIC_MSG_TYPE	3</div><div class='add'>+	struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE];</div><div class='add'>+	/** @lr_tdr: long running TDR worker */</div><div class='add'>+	struct work_struct lr_tdr;</div><div class='add'>+	/** @fini_async: do final fini async from this worker */</div><div class='add'>+	struct work_struct fini_async;</div><div class='add'>+	/** @resume_time: time of last resume */</div><div class='add'>+	u64 resume_time;</div><div class='add'>+	/** @state: GuC specific state for this xe_exec_queue */</div><div class='add'>+	atomic_t state;</div><div class='add'>+	/** @wqi_head: work queue item tail */</div><div class='add'>+	u32 wqi_head;</div><div class='add'>+	/** @wqi_tail: work queue item tail */</div><div class='add'>+	u32 wqi_tail;</div><div class='add'>+	/** @id: GuC id for this exec_queue */</div><div class='add'>+	u16 id;</div><div class='add'>+	/** @suspend_wait: wait queue used to wait on pending suspends */</div><div class='add'>+	wait_queue_head_t suspend_wait;</div><div class='add'>+	/** @suspend_pending: a suspend of the exec_queue is pending */</div><div class='add'>+	bool suspend_pending;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h<br/>new file mode 100644<br/>index 000000000000..4dd5a88a7826<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_fwif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_fwif.h</a></div><div class='hunk'>@@ -0,0 +1,361 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_FWIF_H</div><div class='add'>+#define _XE_GUC_FWIF_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_klvs_abi.h"</div><div class='add'>+</div><div class='add'>+#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4</div><div class='add'>+#define G2H_LEN_DW_DEREGISTER_CONTEXT		3</div><div class='add'>+#define G2H_LEN_DW_TLB_INVALIDATE		3</div><div class='add'>+</div><div class='add'>+#define GUC_CONTEXT_DISABLE		0</div><div class='add'>+#define GUC_CONTEXT_ENABLE		1</div><div class='add'>+</div><div class='add'>+#define GUC_CLIENT_PRIORITY_KMD_HIGH	0</div><div class='add'>+#define GUC_CLIENT_PRIORITY_HIGH	1</div><div class='add'>+#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2</div><div class='add'>+#define GUC_CLIENT_PRIORITY_NORMAL	3</div><div class='add'>+#define GUC_CLIENT_PRIORITY_NUM		4</div><div class='add'>+</div><div class='add'>+#define GUC_RENDER_ENGINE		0</div><div class='add'>+#define GUC_VIDEO_ENGINE		1</div><div class='add'>+#define GUC_BLITTER_ENGINE		2</div><div class='add'>+#define GUC_VIDEOENHANCE_ENGINE		3</div><div class='add'>+#define GUC_VIDEO_ENGINE2		4</div><div class='add'>+#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)</div><div class='add'>+</div><div class='add'>+#define GUC_RENDER_CLASS		0</div><div class='add'>+#define GUC_VIDEO_CLASS			1</div><div class='add'>+#define GUC_VIDEOENHANCE_CLASS		2</div><div class='add'>+#define GUC_BLITTER_CLASS		3</div><div class='add'>+#define GUC_COMPUTE_CLASS		4</div><div class='add'>+#define GUC_GSC_OTHER_CLASS		5</div><div class='add'>+#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS</div><div class='add'>+#define GUC_MAX_ENGINE_CLASSES		16</div><div class='add'>+#define GUC_MAX_INSTANCES_PER_CLASS	32</div><div class='add'>+</div><div class='add'>+/* Helper for context registration H2G */</div><div class='add'>+struct guc_ctxt_registration_info {</div><div class='add'>+	u32 flags;</div><div class='add'>+	u32 context_idx;</div><div class='add'>+	u32 engine_class;</div><div class='add'>+	u32 engine_submit_mask;</div><div class='add'>+	u32 wq_desc_lo;</div><div class='add'>+	u32 wq_desc_hi;</div><div class='add'>+	u32 wq_base_lo;</div><div class='add'>+	u32 wq_base_hi;</div><div class='add'>+	u32 wq_size;</div><div class='add'>+	u32 hwlrca_lo;</div><div class='add'>+	u32 hwlrca_hi;</div><div class='add'>+};</div><div class='add'>+#define CONTEXT_REGISTRATION_FLAG_KMD	BIT(0)</div><div class='add'>+</div><div class='add'>+/* 32-bit KLV structure as used by policy updates and others */</div><div class='add'>+struct guc_klv_generic_dw_t {</div><div class='add'>+	u32 kl;</div><div class='add'>+	u32 value;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */</div><div class='add'>+struct guc_update_exec_queue_policy_header {</div><div class='add'>+	u32 action;</div><div class='add'>+	u32 guc_id;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct guc_update_exec_queue_policy {</div><div class='add'>+	struct guc_update_exec_queue_policy_header header;</div><div class='add'>+	struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* GUC_CTL_* - Parameters for loading the GuC */</div><div class='add'>+#define GUC_CTL_LOG_PARAMS		0</div><div class='add'>+#define   GUC_LOG_VALID			BIT(0)</div><div class='add'>+#define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)</div><div class='add'>+#define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)</div><div class='add'>+#define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)</div><div class='add'>+#define   GUC_LOG_CRASH_SHIFT		4</div><div class='add'>+#define   GUC_LOG_CRASH_MASK		(0x3 &lt;&lt; GUC_LOG_CRASH_SHIFT)</div><div class='add'>+#define   GUC_LOG_DEBUG_SHIFT		6</div><div class='add'>+#define   GUC_LOG_DEBUG_MASK	        (0xF &lt;&lt; GUC_LOG_DEBUG_SHIFT)</div><div class='add'>+#define   GUC_LOG_CAPTURE_SHIFT		10</div><div class='add'>+#define   GUC_LOG_CAPTURE_MASK	        (0x3 &lt;&lt; GUC_LOG_CAPTURE_SHIFT)</div><div class='add'>+#define   GUC_LOG_BUF_ADDR_SHIFT	12</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_WA			1</div><div class='add'>+#define   GUC_WA_GAM_CREDITS		BIT(10)</div><div class='add'>+#define   GUC_WA_DUAL_QUEUE		BIT(11)</div><div class='add'>+#define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)</div><div class='add'>+#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)</div><div class='add'>+#define   GUC_WA_PRE_PARSER		BIT(14)</div><div class='add'>+#define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)</div><div class='add'>+#define   GUC_WA_POLLCS			BIT(18)</div><div class='add'>+#define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)</div><div class='add'>+#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_FEATURE			2</div><div class='add'>+#define   GUC_CTL_ENABLE_SLPC		BIT(2)</div><div class='add'>+#define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_DEBUG			3</div><div class='add'>+#define   GUC_LOG_VERBOSITY_SHIFT	0</div><div class='add'>+#define   GUC_LOG_VERBOSITY_LOW		(0 &lt;&lt; GUC_LOG_VERBOSITY_SHIFT)</div><div class='add'>+#define   GUC_LOG_VERBOSITY_MED		(1 &lt;&lt; GUC_LOG_VERBOSITY_SHIFT)</div><div class='add'>+#define   GUC_LOG_VERBOSITY_HIGH	(2 &lt;&lt; GUC_LOG_VERBOSITY_SHIFT)</div><div class='add'>+#define   GUC_LOG_VERBOSITY_ULTRA	(3 &lt;&lt; GUC_LOG_VERBOSITY_SHIFT)</div><div class='add'>+#define	  GUC_LOG_VERBOSITY_MIN		0</div><div class='add'>+#define	  GUC_LOG_VERBOSITY_MAX		3</div><div class='add'>+#define	  GUC_LOG_VERBOSITY_MASK	0x0000000f</div><div class='add'>+#define	  GUC_LOG_DESTINATION_MASK	(3 &lt;&lt; 4)</div><div class='add'>+#define   GUC_LOG_DISABLED		(1 &lt;&lt; 6)</div><div class='add'>+#define   GUC_PROFILE_ENABLED		(1 &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_ADS			4</div><div class='add'>+#define   GUC_ADS_ADDR_SHIFT		1</div><div class='add'>+#define   GUC_ADS_ADDR_MASK		(0xFFFFF &lt;&lt; GUC_ADS_ADDR_SHIFT)</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_DEVID			5</div><div class='add'>+</div><div class='add'>+#define GUC_CTL_MAX_DWORDS		14</div><div class='add'>+</div><div class='add'>+/* Scheduling policy settings */</div><div class='add'>+</div><div class='add'>+#define GLOBAL_POLICY_MAX_NUM_WI 15</div><div class='add'>+</div><div class='add'>+/* Don't reset an engine upon preemption failure */</div><div class='add'>+#define GLOBAL_POLICY_DISABLE_ENGINE_RESET				BIT(0)</div><div class='add'>+</div><div class='add'>+#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000</div><div class='add'>+</div><div class='add'>+struct guc_policies {</div><div class='add'>+	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	/*</div><div class='add'>+	 * In micro seconds. How much time to allow before DPC processing is</div><div class='add'>+	 * called back via interrupt (to prevent DPC queue drain starving).</div><div class='add'>+	 * Typically 1000s of micro seconds (example only, not granularity).</div><div class='add'>+	 */</div><div class='add'>+	u32 dpc_promote_time;</div><div class='add'>+</div><div class='add'>+	/* Must be set to take these new values. */</div><div class='add'>+	u32 is_valid;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Max number of WIs to process per call. A large value may keep CS</div><div class='add'>+	 * idle.</div><div class='add'>+	 */</div><div class='add'>+	u32 max_num_work_items;</div><div class='add'>+</div><div class='add'>+	u32 global_flags;</div><div class='add'>+	u32 reserved[4];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* GuC MMIO reg state struct */</div><div class='add'>+struct guc_mmio_reg {</div><div class='add'>+	u32 offset;</div><div class='add'>+	u32 value;</div><div class='add'>+	u32 flags;</div><div class='add'>+	u32 mask;</div><div class='add'>+#define GUC_REGSET_MASKED		BIT(0)</div><div class='add'>+#define GUC_REGSET_MASKED_WITH_VALUE	BIT(2)</div><div class='add'>+#define GUC_REGSET_RESTORE_ONLY		BIT(3)</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* GuC register sets */</div><div class='add'>+struct guc_mmio_reg_set {</div><div class='add'>+	u32 address;</div><div class='add'>+	u16 count;</div><div class='add'>+	u16 reserved;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Generic GT SysInfo data types */</div><div class='add'>+#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED		0</div><div class='add'>+#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK	1</div><div class='add'>+#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI	2</div><div class='add'>+#define GUC_GENERIC_GT_SYSINFO_MAX			16</div><div class='add'>+</div><div class='add'>+/* HW info */</div><div class='add'>+struct guc_gt_system_info {</div><div class='add'>+	u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];</div><div class='add'>+	u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	GUC_CAPTURE_LIST_INDEX_PF = 0,</div><div class='add'>+	GUC_CAPTURE_LIST_INDEX_VF = 1,</div><div class='add'>+	GUC_CAPTURE_LIST_INDEX_MAX = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GuC Additional Data Struct */</div><div class='add'>+struct guc_ads {</div><div class='add'>+	struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];</div><div class='add'>+	u32 reserved0;</div><div class='add'>+	u32 scheduler_policies;</div><div class='add'>+	u32 gt_system_info;</div><div class='add'>+	u32 reserved1;</div><div class='add'>+	u32 control_data;</div><div class='add'>+	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	u32 private_data;</div><div class='add'>+	u32 um_init_data;</div><div class='add'>+	u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];</div><div class='add'>+	u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];</div><div class='add'>+	u32 reserved[14];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Engine usage stats */</div><div class='add'>+struct guc_engine_usage_record {</div><div class='add'>+	u32 current_context_index;</div><div class='add'>+	u32 last_switch_in_stamp;</div><div class='add'>+	u32 reserved0;</div><div class='add'>+	u32 total_runtime;</div><div class='add'>+	u32 reserved1[4];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct guc_engine_usage {</div><div class='add'>+	struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */</div><div class='add'>+enum xe_guc_recv_message {</div><div class='add'>+	XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),</div><div class='add'>+	XE_GUC_RECV_MSG_EXCEPTION = BIT(30),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Page fault structures */</div><div class='add'>+struct access_counter_desc {</div><div class='add'>+	u32 dw0;</div><div class='add'>+#define ACCESS_COUNTER_TYPE	BIT(0)</div><div class='add'>+#define ACCESS_COUNTER_SUBG_LO	GENMASK(31, 1)</div><div class='add'>+</div><div class='add'>+	u32 dw1;</div><div class='add'>+#define ACCESS_COUNTER_SUBG_HI	BIT(0)</div><div class='add'>+#define ACCESS_COUNTER_RSVD0	GENMASK(2, 1)</div><div class='add'>+#define ACCESS_COUNTER_ENG_INSTANCE	GENMASK(8, 3)</div><div class='add'>+#define ACCESS_COUNTER_ENG_CLASS	GENMASK(11, 9)</div><div class='add'>+#define ACCESS_COUNTER_ASID	GENMASK(31, 12)</div><div class='add'>+</div><div class='add'>+	u32 dw2;</div><div class='add'>+#define ACCESS_COUNTER_VFID	GENMASK(5, 0)</div><div class='add'>+#define ACCESS_COUNTER_RSVD1	GENMASK(7, 6)</div><div class='add'>+#define ACCESS_COUNTER_GRANULARITY	GENMASK(10, 8)</div><div class='add'>+#define ACCESS_COUNTER_RSVD2	GENMASK(16, 11)</div><div class='add'>+#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)</div><div class='add'>+</div><div class='add'>+	u32 dw3;</div><div class='add'>+#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+enum guc_um_queue_type {</div><div class='add'>+	GUC_UM_HW_QUEUE_PAGE_FAULT = 0,</div><div class='add'>+	GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,</div><div class='add'>+	GUC_UM_HW_QUEUE_ACCESS_COUNTER,</div><div class='add'>+	GUC_UM_HW_QUEUE_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct guc_um_queue_params {</div><div class='add'>+	u64 base_dpa;</div><div class='add'>+	u32 base_ggtt_address;</div><div class='add'>+	u32 size_in_bytes;</div><div class='add'>+	u32 rsvd[4];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct guc_um_init_params {</div><div class='add'>+	u64 page_response_timeout_in_us;</div><div class='add'>+	u32 rsvd[6];</div><div class='add'>+	struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+enum xe_guc_fault_reply_type {</div><div class='add'>+	PFR_ACCESS = 0,</div><div class='add'>+	PFR_ENGINE,</div><div class='add'>+	PFR_VFID,</div><div class='add'>+	PFR_ALL,</div><div class='add'>+	PFR_INVALID</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_guc_response_desc_type {</div><div class='add'>+	TLB_INVALIDATION_DESC = 0,</div><div class='add'>+	FAULT_RESPONSE_DESC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_guc_pagefault_desc {</div><div class='add'>+	u32 dw0;</div><div class='add'>+#define PFD_FAULT_LEVEL		GENMASK(2, 0)</div><div class='add'>+#define PFD_SRC_ID		GENMASK(10, 3)</div><div class='add'>+#define PFD_RSVD_0		GENMASK(17, 11)</div><div class='add'>+#define XE2_PFD_TRVA_FAULT	BIT(18)</div><div class='add'>+#define PFD_ENG_INSTANCE	GENMASK(24, 19)</div><div class='add'>+#define PFD_ENG_CLASS		GENMASK(27, 25)</div><div class='add'>+#define PFD_PDATA_LO		GENMASK(31, 28)</div><div class='add'>+</div><div class='add'>+	u32 dw1;</div><div class='add'>+#define PFD_PDATA_HI		GENMASK(11, 0)</div><div class='add'>+#define PFD_PDATA_HI_SHIFT	4</div><div class='add'>+#define PFD_ASID		GENMASK(31, 12)</div><div class='add'>+</div><div class='add'>+	u32 dw2;</div><div class='add'>+#define PFD_ACCESS_TYPE		GENMASK(1, 0)</div><div class='add'>+#define PFD_FAULT_TYPE		GENMASK(3, 2)</div><div class='add'>+#define PFD_VFID		GENMASK(9, 4)</div><div class='add'>+#define PFD_RSVD_1		GENMASK(11, 10)</div><div class='add'>+#define PFD_VIRTUAL_ADDR_LO	GENMASK(31, 12)</div><div class='add'>+#define PFD_VIRTUAL_ADDR_LO_SHIFT 12</div><div class='add'>+</div><div class='add'>+	u32 dw3;</div><div class='add'>+#define PFD_VIRTUAL_ADDR_HI	GENMASK(31, 0)</div><div class='add'>+#define PFD_VIRTUAL_ADDR_HI_SHIFT 32</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct xe_guc_pagefault_reply {</div><div class='add'>+	u32 dw0;</div><div class='add'>+#define PFR_VALID		BIT(0)</div><div class='add'>+#define PFR_SUCCESS		BIT(1)</div><div class='add'>+#define PFR_REPLY		GENMASK(4, 2)</div><div class='add'>+#define PFR_RSVD_0		GENMASK(9, 5)</div><div class='add'>+#define PFR_DESC_TYPE		GENMASK(11, 10)</div><div class='add'>+#define PFR_ASID		GENMASK(31, 12)</div><div class='add'>+</div><div class='add'>+	u32 dw1;</div><div class='add'>+#define PFR_VFID		GENMASK(5, 0)</div><div class='add'>+#define PFR_RSVD_1		BIT(6)</div><div class='add'>+#define PFR_ENG_INSTANCE	GENMASK(12, 7)</div><div class='add'>+#define PFR_ENG_CLASS		GENMASK(15, 13)</div><div class='add'>+#define PFR_PDATA		GENMASK(31, 16)</div><div class='add'>+</div><div class='add'>+	u32 dw2;</div><div class='add'>+#define PFR_RSVD_2		GENMASK(31, 0)</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct xe_guc_acc_desc {</div><div class='add'>+	u32 dw0;</div><div class='add'>+#define ACC_TYPE	BIT(0)</div><div class='add'>+#define ACC_TRIGGER	0</div><div class='add'>+#define ACC_NOTIFY	1</div><div class='add'>+#define ACC_SUBG_LO	GENMASK(31, 1)</div><div class='add'>+</div><div class='add'>+	u32 dw1;</div><div class='add'>+#define ACC_SUBG_HI	BIT(0)</div><div class='add'>+#define ACC_RSVD0	GENMASK(2, 1)</div><div class='add'>+#define ACC_ENG_INSTANCE	GENMASK(8, 3)</div><div class='add'>+#define ACC_ENG_CLASS	GENMASK(11, 9)</div><div class='add'>+#define ACC_ASID	GENMASK(31, 12)</div><div class='add'>+</div><div class='add'>+	u32 dw2;</div><div class='add'>+#define ACC_VFID	GENMASK(5, 0)</div><div class='add'>+#define ACC_RSVD1	GENMASK(7, 6)</div><div class='add'>+#define ACC_GRANULARITY	GENMASK(10, 8)</div><div class='add'>+#define ACC_RSVD2	GENMASK(16, 11)</div><div class='add'>+#define ACC_VIRTUAL_ADDR_RANGE_LO	GENMASK(31, 17)</div><div class='add'>+</div><div class='add'>+	u32 dw3;</div><div class='add'>+#define ACC_VIRTUAL_ADDR_RANGE_HI	GENMASK(31, 0)</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c<br/>new file mode 100644<br/>index 000000000000..2a13a00917f8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_hwconfig.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_hwconfig.c</a></div><div class='hunk'>@@ -0,0 +1,104 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_hwconfig.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+</div><div class='add'>+static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_GET_HWCONFIG,</div><div class='add'>+		lower_32_bits(ggtt_addr),</div><div class='add'>+		upper_32_bits(ggtt_addr),</div><div class='add'>+		size,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)</div><div class='add'>+{</div><div class='add'>+	int ret = send_get_hwconfig(guc, 0, 0);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*size = ret;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_hwconfig_copy(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc-&gt;hwconfig.bo),</div><div class='add'>+				    guc-&gt;hwconfig.size);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_hwconfig_init(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	u32 size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* Initialization already done */</div><div class='add'>+	if (guc-&gt;hwconfig.bo)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All hwconfig the same across GTs so only GT0 needs to be configured</div><div class='add'>+	 */</div><div class='add'>+	if (gt-&gt;info.id != XE_GT0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* ADL_P, DG2+ supports hwconfig table */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1255 &amp;&amp; xe-&gt;info.platform != XE_ALDERLAKE_P)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = guc_hwconfig_size(guc, &amp;size);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+	if (!size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+					  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+	guc-&gt;hwconfig.bo = bo;</div><div class='add'>+	guc-&gt;hwconfig.size = size;</div><div class='add'>+</div><div class='add'>+	return guc_hwconfig_copy(guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_guc_hwconfig_size(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return !guc-&gt;hwconfig.bo ? 0 : guc-&gt;hwconfig.size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!guc-&gt;hwconfig.bo);</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_from(xe, dst, &amp;guc-&gt;hwconfig.bo-&gt;vmap, 0,</div><div class='add'>+			   guc-&gt;hwconfig.size);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.h b/drivers/gpu/drm/xe/xe_guc_hwconfig.h<br/>new file mode 100644<br/>index 000000000000..b5794d641900<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_hwconfig.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_hwconfig.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_HWCONFIG_H_</div><div class='add'>+#define _XE_GUC_HWCONFIG_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_guc;</div><div class='add'>+</div><div class='add'>+int xe_guc_hwconfig_init(struct xe_guc *guc);</div><div class='add'>+u32 xe_guc_hwconfig_size(struct xe_guc *guc);</div><div class='add'>+void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c<br/>new file mode 100644<br/>index 000000000000..bcd2f4d34081<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_log.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log.c</a></div><div class='hunk'>@@ -0,0 +1,97 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_log.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+log_to_gt(struct xe_guc_log *log)</div><div class='add'>+{</div><div class='add'>+	return container_of(log, struct xe_gt, uc.guc.log);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+log_to_xe(struct xe_guc_log *log)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(log_to_gt(log));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t guc_log_size(void)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 *  GuC Log buffer Layout</div><div class='add'>+	 *</div><div class='add'>+	 *  +===============================+ 00B</div><div class='add'>+	 *  |    Crash dump state header    |</div><div class='add'>+	 *  +-------------------------------+ 32B</div><div class='add'>+	 *  |      Debug state header       |</div><div class='add'>+	 *  +-------------------------------+ 64B</div><div class='add'>+	 *  |     Capture state header      |</div><div class='add'>+	 *  +-------------------------------+ 96B</div><div class='add'>+	 *  |                               |</div><div class='add'>+	 *  +===============================+ PAGE_SIZE (4KB)</div><div class='add'>+	 *  |        Crash Dump logs        |</div><div class='add'>+	 *  +===============================+ + CRASH_SIZE</div><div class='add'>+	 *  |          Debug logs           |</div><div class='add'>+	 *  +===============================+ + DEBUG_SIZE</div><div class='add'>+	 *  |         Capture logs          |</div><div class='add'>+	 *  +===============================+ + CAPTURE_SIZE</div><div class='add'>+	 */</div><div class='add'>+	return PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +</div><div class='add'>+		CAPTURE_BUFFER_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = log_to_xe(log);</div><div class='add'>+	size_t size;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, log-&gt;bo);</div><div class='add'>+</div><div class='add'>+	size = log-&gt;bo-&gt;size;</div><div class='add'>+</div><div class='add'>+#define DW_PER_READ		128</div><div class='add'>+	xe_assert(xe, !(size % (DW_PER_READ * sizeof(u32))));</div><div class='add'>+	for (i = 0; i &lt; size / sizeof(u32); i += DW_PER_READ) {</div><div class='add'>+		u32 read[DW_PER_READ];</div><div class='add'>+</div><div class='add'>+		xe_map_memcpy_from(xe, read, &amp;log-&gt;bo-&gt;vmap, i * sizeof(u32),</div><div class='add'>+				   DW_PER_READ * sizeof(u32));</div><div class='add'>+#define DW_PER_PRINT		4</div><div class='add'>+		for (j = 0; j &lt; DW_PER_READ / DW_PER_PRINT; ++j) {</div><div class='add'>+			u32 *print = read + j * DW_PER_PRINT;</div><div class='add'>+</div><div class='add'>+			drm_printf(p, "0x%08x 0x%08x 0x%08x 0x%08x\n",</div><div class='add'>+				   *(print + 0), *(print + 1),</div><div class='add'>+				   *(print + 2), *(print + 3));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_log_init(struct xe_guc_log *log)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = log_to_xe(log);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(log_to_gt(log));</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_log_size(),</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+					  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	xe_map_memset(xe, &amp;bo-&gt;vmap, 0, 0, guc_log_size());</div><div class='add'>+	log-&gt;bo = bo;</div><div class='add'>+	log-&gt;level = xe_modparam.guc_log_level;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_log.h b/drivers/gpu/drm/xe/xe_guc_log.h<br/>new file mode 100644<br/>index 000000000000..2d25ab28b4b3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_log.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log.h</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_LOG_H_</div><div class='add'>+#define _XE_GUC_LOG_H_</div><div class='add'>+</div><div class='add'>+#include "xe_guc_log_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_LARGE_GUC_BUFFER)</div><div class='add'>+#define CRASH_BUFFER_SIZE       SZ_1M</div><div class='add'>+#define DEBUG_BUFFER_SIZE       SZ_8M</div><div class='add'>+#define CAPTURE_BUFFER_SIZE     SZ_2M</div><div class='add'>+#else</div><div class='add'>+#define CRASH_BUFFER_SIZE	SZ_8K</div><div class='add'>+#define DEBUG_BUFFER_SIZE	SZ_64K</div><div class='add'>+#define CAPTURE_BUFFER_SIZE	SZ_16K</div><div class='add'>+#endif</div><div class='add'>+/*</div><div class='add'>+ * While we're using plain log level in i915, GuC controls are much more...</div><div class='add'>+ * "elaborate"? We have a couple of bits for verbosity, separate bit for actual</div><div class='add'>+ * log enabling, and separate bit for default logging - which "conveniently"</div><div class='add'>+ * ignores the enable bit.</div><div class='add'>+ */</div><div class='add'>+#define GUC_LOG_LEVEL_DISABLED		0</div><div class='add'>+#define GUC_LOG_LEVEL_NON_VERBOSE	1</div><div class='add'>+#define GUC_LOG_LEVEL_IS_ENABLED(x)	((x) &gt; GUC_LOG_LEVEL_DISABLED)</div><div class='add'>+#define GUC_LOG_LEVEL_IS_VERBOSE(x)	((x) &gt; GUC_LOG_LEVEL_NON_VERBOSE)</div><div class='add'>+#define GUC_LOG_LEVEL_TO_VERBOSITY(x) ({		\</div><div class='add'>+	typeof(x) _x = (x);				\</div><div class='add'>+	GUC_LOG_LEVEL_IS_VERBOSE(_x) ? _x - 2 : 0;	\</div><div class='add'>+})</div><div class='add'>+#define GUC_VERBOSITY_TO_LOG_LEVEL(x)	((x) + 2)</div><div class='add'>+#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)</div><div class='add'>+</div><div class='add'>+int xe_guc_log_init(struct xe_guc_log *log);</div><div class='add'>+void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+static inline u32</div><div class='add'>+xe_guc_log_get_level(struct xe_guc_log *log)</div><div class='add'>+{</div><div class='add'>+	return log-&gt;level;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_log_types.h b/drivers/gpu/drm/xe/xe_guc_log_types.h<br/>new file mode 100644<br/>index 000000000000..125080d138a7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_log_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_log_types.h</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_LOG_TYPES_H_</div><div class='add'>+#define _XE_GUC_LOG_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_log - GuC log</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_log {</div><div class='add'>+	/** @level: GuC log level */</div><div class='add'>+	u32 level;</div><div class='add'>+	/** @bo: XE BO for GuC log */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c<br/>new file mode 100644<br/>index 000000000000..f71085228cb3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_pc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc.c</a></div><div class='hunk'>@@ -0,0 +1,1000 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "abi/guc_actions_slpc_abi.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_idle.h"</div><div class='add'>+#include "xe_gt_sysfs.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+</div><div class='add'>+#define MCHBAR_MIRROR_BASE_SNB	0x140000</div><div class='add'>+</div><div class='add'>+#define RP_STATE_CAP		XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)</div><div class='add'>+#define   RP0_MASK		REG_GENMASK(7, 0)</div><div class='add'>+#define   RP1_MASK		REG_GENMASK(15, 8)</div><div class='add'>+#define   RPN_MASK		REG_GENMASK(23, 16)</div><div class='add'>+</div><div class='add'>+#define FREQ_INFO_REC	XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)</div><div class='add'>+#define   RPE_MASK		REG_GENMASK(15, 8)</div><div class='add'>+</div><div class='add'>+#define GT_PERF_STATUS		XE_REG(0x1381b4)</div><div class='add'>+#define   CAGF_MASK	REG_GENMASK(19, 11)</div><div class='add'>+</div><div class='add'>+#define GT_FREQUENCY_MULTIPLIER	50</div><div class='add'>+#define GT_FREQUENCY_SCALER	3</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GuC Power Conservation (PC)</div><div class='add'>+ *</div><div class='add'>+ * GuC Power Conservation (PC) supports multiple features for the most</div><div class='add'>+ * efficient and performing use of the GT when GuC submission is enabled,</div><div class='add'>+ * including frequency management, Render-C states management, and various</div><div class='add'>+ * algorithms for power balancing.</div><div class='add'>+ *</div><div class='add'>+ * Single Loop Power Conservation (SLPC) is the name given to the suite of</div><div class='add'>+ * connected power conservation features in the GuC firmware. The firmware</div><div class='add'>+ * exposes a programming interface to the host for the control of SLPC.</div><div class='add'>+ *</div><div class='add'>+ * Frequency management:</div><div class='add'>+ * =====================</div><div class='add'>+ *</div><div class='add'>+ * Xe driver enables SLPC with all of its defaults features and frequency</div><div class='add'>+ * selection, which varies per platform.</div><div class='add'>+ *</div><div class='add'>+ * Render-C States:</div><div class='add'>+ * ================</div><div class='add'>+ *</div><div class='add'>+ * Render-C states is also a GuC PC feature that is now enabled in Xe for</div><div class='add'>+ * all platforms.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static struct xe_guc *</div><div class='add'>+pc_to_guc(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	return container_of(pc, struct xe_guc, pc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+pc_to_xe(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = pc_to_guc(pc);</div><div class='add'>+	struct xe_gt *gt = container_of(guc, struct xe_gt, uc.guc);</div><div class='add'>+</div><div class='add'>+	return gt_to_xe(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+pc_to_gt(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	return container_of(pc, struct xe_gt, uc.guc.pc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct iosys_map *</div><div class='add'>+pc_to_maps(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	return &amp;pc-&gt;bo-&gt;vmap;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define slpc_shared_data_read(pc_, field_) \</div><div class='add'>+	xe_map_rd_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \</div><div class='add'>+			struct slpc_shared_data, field_)</div><div class='add'>+</div><div class='add'>+#define slpc_shared_data_write(pc_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \</div><div class='add'>+			struct slpc_shared_data, field_, val_)</div><div class='add'>+</div><div class='add'>+#define SLPC_EVENT(id, count) \</div><div class='add'>+	(FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \</div><div class='add'>+	 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, count))</div><div class='add'>+</div><div class='add'>+static int wait_for_pc_state(struct xe_guc_pc *pc,</div><div class='add'>+			     enum slpc_global_state state)</div><div class='add'>+{</div><div class='add'>+	int timeout_us = 5000; /* rought 5ms, but no need for precision */</div><div class='add'>+	int slept, wait = 10;</div><div class='add'>+</div><div class='add'>+	xe_device_assert_mem_access(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	for (slept = 0; slept &lt; timeout_us;) {</div><div class='add'>+		if (slpc_shared_data_read(pc, header.global_state) == state)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		usleep_range(wait, wait &lt;&lt; 1);</div><div class='add'>+		slept += wait;</div><div class='add'>+		wait &lt;&lt;= 1;</div><div class='add'>+		if (slept + wait &gt; timeout_us)</div><div class='add'>+			wait = timeout_us - slept;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_action_reset(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct  xe_guc_ct *ct = &amp;pc_to_guc(pc)-&gt;ct;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,</div><div class='add'>+		SLPC_EVENT(SLPC_EVENT_RESET, 2),</div><div class='add'>+		xe_bo_ggtt_addr(pc-&gt;bo),</div><div class='add'>+		0,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC PC reset: %pe", ERR_PTR(ret));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_action_shutdown(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct  xe_guc_ct *ct = &amp;pc_to_guc(pc)-&gt;ct;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,</div><div class='add'>+		SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2),</div><div class='add'>+		xe_bo_ggtt_addr(pc-&gt;bo),</div><div class='add'>+		0,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC PC shutdown %pe",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_action_query_task_state(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct *ct = &amp;pc_to_guc(pc)-&gt;ct;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,</div><div class='add'>+		SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),</div><div class='add'>+		xe_bo_ggtt_addr(pc-&gt;bo),</div><div class='add'>+		0,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	/* Blocking here to ensure the results are ready before reading them */</div><div class='add'>+	ret = xe_guc_ct_send_block(ct, action, ARRAY_SIZE(action));</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm,</div><div class='add'>+			"GuC PC query task state failed: %pe", ERR_PTR(ret));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct *ct = &amp;pc_to_guc(pc)-&gt;ct;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,</div><div class='add'>+		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),</div><div class='add'>+		id,</div><div class='add'>+		value,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC PC set param failed: %pe",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_ct *ct = &amp;pc_to_guc(pc)-&gt;ct;</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_SETUP_PC_GUCRC,</div><div class='add'>+		mode,</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC RC enable failed: %pe",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 decode_freq(u32 raw)</div><div class='add'>+{</div><div class='add'>+	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,</div><div class='add'>+				 GT_FREQUENCY_SCALER);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 encode_freq(u32 freq)</div><div class='add'>+{</div><div class='add'>+	return DIV_ROUND_CLOSEST(freq * GT_FREQUENCY_SCALER,</div><div class='add'>+				 GT_FREQUENCY_MULTIPLIER);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 pc_get_min_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	u32 freq;</div><div class='add'>+</div><div class='add'>+	freq = FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,</div><div class='add'>+			 slpc_shared_data_read(pc, task_state_data.freq));</div><div class='add'>+</div><div class='add'>+	return decode_freq(freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE;</div><div class='add'>+</div><div class='add'>+	/* Allow/Disallow punit to process software freq requests */</div><div class='add'>+	xe_mmio_write32(gt, RP_CONTROL, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 rpnswreq;</div><div class='add'>+</div><div class='add'>+	pc_set_manual_rp_ctrl(pc, true);</div><div class='add'>+</div><div class='add'>+	/* Req freq is in units of 16.66 Mhz */</div><div class='add'>+	rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq));</div><div class='add'>+	xe_mmio_write32(gt, RPNSWREQ, rpnswreq);</div><div class='add'>+</div><div class='add'>+	/* Sleep for a small time to allow pcode to respond */</div><div class='add'>+	usleep_range(100, 300);</div><div class='add'>+</div><div class='add'>+	pc_set_manual_rp_ctrl(pc, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Let's only check for the rpn-rp0 range. If max &lt; min,</div><div class='add'>+	 * min becomes a fixed request.</div><div class='add'>+	 */</div><div class='add'>+	if (freq &lt; pc-&gt;rpn_freq || freq &gt; pc-&gt;rp0_freq)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * GuC policy is to elevate minimum frequency to the efficient levels</div><div class='add'>+	 * Our goal is to have the admin choices respected.</div><div class='add'>+	 */</div><div class='add'>+	pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,</div><div class='add'>+			    freq &lt; pc-&gt;rpe_freq);</div><div class='add'>+</div><div class='add'>+	return pc_action_set_param(pc,</div><div class='add'>+				   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,</div><div class='add'>+				   freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_get_max_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	u32 freq;</div><div class='add'>+</div><div class='add'>+	freq = FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,</div><div class='add'>+			 slpc_shared_data_read(pc, task_state_data.freq));</div><div class='add'>+</div><div class='add'>+	return decode_freq(freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Let's only check for the rpn-rp0 range. If max &lt; min,</div><div class='add'>+	 * min becomes a fixed request.</div><div class='add'>+	 * Also, overclocking is not supported.</div><div class='add'>+	 */</div><div class='add'>+	if (freq &lt; pc-&gt;rpn_freq || freq &gt; pc-&gt;rp0_freq)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return pc_action_set_param(pc,</div><div class='add'>+				   SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,</div><div class='add'>+				   freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtl_update_rpe_value(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);</div><div class='add'>+	else</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);</div><div class='add'>+</div><div class='add'>+	pc-&gt;rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tgl_update_rpe_value(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For PVC we still need to use fused RP1 as the approximation for RPe</div><div class='add'>+	 * For other platforms than PVC we get the resolved RPe directly from</div><div class='add'>+	 * PCODE at a different register</div><div class='add'>+	 */</div><div class='add'>+	if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+		reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);</div><div class='add'>+	else</div><div class='add'>+		reg = xe_mmio_read32(gt, FREQ_INFO_REC);</div><div class='add'>+</div><div class='add'>+	pc-&gt;rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pc_update_rp_values(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		mtl_update_rpe_value(pc);</div><div class='add'>+	else</div><div class='add'>+		tgl_update_rpe_value(pc);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * RPe is decided at runtime by PCODE. In the rare case where that's</div><div class='add'>+	 * smaller than the fused min, we will trust the PCODE and use that</div><div class='add'>+	 * as our minimum one.</div><div class='add'>+	 */</div><div class='add'>+	pc-&gt;rpn_freq = min(pc-&gt;rpn_freq, pc-&gt;rpe_freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_act_freq - Get Actual running frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ *</div><div class='add'>+ * Returns: The Actual running frequency. Which might be 0 if GT is in Render-C sleep state (RC6).</div><div class='add'>+ */</div><div class='add'>+u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 freq;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	/* When in RC6, actual frequency reported will be 0. */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1270) {</div><div class='add'>+		freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);</div><div class='add'>+		freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);</div><div class='add'>+	} else {</div><div class='add'>+		freq = xe_mmio_read32(gt, GT_PERF_STATUS);</div><div class='add'>+		freq = REG_FIELD_GET(CAGF_MASK, freq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	freq = decode_freq(freq);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_cur_freq - Get Current requested frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ * @freq: A pointer to a u32 where the freq value will be returned</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success,</div><div class='add'>+ *         -EAGAIN if GuC PC not ready (likely in middle of a reset).</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	/*</div><div class='add'>+	 * GuC SLPC plays with cur freq request when GuCRC is enabled</div><div class='add'>+	 * Block RC6 for a more reliable read.</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	*freq = xe_mmio_read32(gt, RPNSWREQ);</div><div class='add'>+</div><div class='add'>+	*freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq);</div><div class='add'>+	*freq = decode_freq(*freq);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+out:</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_rp0_freq - Get the RP0 freq</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ *</div><div class='add'>+ * Returns: RP0 freq.</div><div class='add'>+ */</div><div class='add'>+u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	return pc-&gt;rp0_freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_rpe_freq - Get the RPe freq</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ *</div><div class='add'>+ * Returns: RPe freq.</div><div class='add'>+ */</div><div class='add'>+u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	pc_update_rp_values(pc);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return pc-&gt;rpe_freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_rpn_freq - Get the RPn freq</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ *</div><div class='add'>+ * Returns: RPn freq.</div><div class='add'>+ */</div><div class='add'>+u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	return pc-&gt;rpn_freq;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_min_freq - Get the min operational frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ * @freq: A pointer to a u32 where the freq value will be returned</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success,</div><div class='add'>+ *         -EAGAIN if GuC PC not ready (likely in middle of a reset).</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	if (!pc-&gt;freq_ready) {</div><div class='add'>+		/* Might be in the middle of a gt reset */</div><div class='add'>+		ret = -EAGAIN;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * GuC SLPC plays with min freq request when GuCRC is enabled</div><div class='add'>+	 * Block RC6 for a more reliable read.</div><div class='add'>+	 */</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = pc_action_query_task_state(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fw;</div><div class='add'>+</div><div class='add'>+	*freq = pc_get_min_freq(pc);</div><div class='add'>+</div><div class='add'>+fw:</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_set_min_freq - Set the minimal operational frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ * @freq: The selected minimal frequency</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success,</div><div class='add'>+ *         -EAGAIN if GuC PC not ready (likely in middle of a reset),</div><div class='add'>+ *         -EINVAL if value out of bounds.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	if (!pc-&gt;freq_ready) {</div><div class='add'>+		/* Might be in the middle of a gt reset */</div><div class='add'>+		ret = -EAGAIN;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pc_set_min_freq(pc, freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	pc-&gt;user_requested_min = freq;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_get_max_freq - Get Maximum operational frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ * @freq: A pointer to a u32 where the freq value will be returned</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success,</div><div class='add'>+ *         -EAGAIN if GuC PC not ready (likely in middle of a reset).</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	if (!pc-&gt;freq_ready) {</div><div class='add'>+		/* Might be in the middle of a gt reset */</div><div class='add'>+		ret = -EAGAIN;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pc_action_query_task_state(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	*freq = pc_get_max_freq(pc);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_set_max_freq - Set the maximum operational frequency</div><div class='add'>+ * @pc: The GuC PC</div><div class='add'>+ * @freq: The selected maximum frequency value</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success,</div><div class='add'>+ *         -EAGAIN if GuC PC not ready (likely in middle of a reset),</div><div class='add'>+ *         -EINVAL if value out of bounds.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	if (!pc-&gt;freq_ready) {</div><div class='add'>+		/* Might be in the middle of a gt reset */</div><div class='add'>+		ret = -EAGAIN;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pc_set_max_freq(pc, freq);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	pc-&gt;user_requested_max = freq;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_c_status - get the current GT C state</div><div class='add'>+ * @pc: XE_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 reg, gt_c_state;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1270) {</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);</div><div class='add'>+		gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);</div><div class='add'>+	} else {</div><div class='add'>+		reg = xe_mmio_read32(gt, GT_CORE_STATUS);</div><div class='add'>+		gt_c_state = REG_FIELD_GET(RCN_MASK, reg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	switch (gt_c_state) {</div><div class='add'>+	case GT_C6:</div><div class='add'>+		return GT_IDLE_C6;</div><div class='add'>+	case GT_C0:</div><div class='add'>+		return GT_IDLE_C0;</div><div class='add'>+	default:</div><div class='add'>+		return GT_IDLE_UNKNOWN;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_rc6_residency - rc6 residency counter</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	reg = xe_mmio_read32(gt, GT_GFX_RC6);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_mc6_residency - mc6 residency counter</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u64 reg;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(gt));</div><div class='add'>+	reg = xe_mmio_read32(gt, MTL_MEDIA_MC6);</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(gt));</div><div class='add'>+</div><div class='add'>+	return reg;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	xe_device_assert_mem_access(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);</div><div class='add'>+	else</div><div class='add'>+		reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);</div><div class='add'>+</div><div class='add'>+	pc-&gt;rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg));</div><div class='add'>+</div><div class='add'>+	pc-&gt;rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	xe_device_assert_mem_access(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+		reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);</div><div class='add'>+	else</div><div class='add'>+		reg = xe_mmio_read32(gt, RP_STATE_CAP);</div><div class='add'>+	pc-&gt;rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;</div><div class='add'>+	pc-&gt;rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pc_init_fused_rp_values(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		mtl_init_fused_rp_values(pc);</div><div class='add'>+	else</div><div class='add'>+		tgl_init_fused_rp_values(pc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_init_early - Initialize RPx values and request a higher GT</div><div class='add'>+ * frequency to allow faster GuC load times</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+void xe_guc_pc_init_early(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	pc_init_fused_rp_values(pc);</div><div class='add'>+	pc_set_cur_freq(pc, pc-&gt;rp0_freq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;pc-&gt;freq_lock);</div><div class='add'>+</div><div class='add'>+	ret = pc_action_query_task_state(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * GuC defaults to some RPmax that is not actually achievable without</div><div class='add'>+	 * overclocking. Let's adjust it to the Hardware RP0, which is the</div><div class='add'>+	 * regular maximum</div><div class='add'>+	 */</div><div class='add'>+	if (pc_get_max_freq(pc) &gt; pc-&gt;rp0_freq)</div><div class='add'>+		pc_set_max_freq(pc, pc-&gt;rp0_freq);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Same thing happens for Server platforms where min is listed as</div><div class='add'>+	 * RPMax</div><div class='add'>+	 */</div><div class='add'>+	if (pc_get_min_freq(pc) &gt; pc-&gt;rp0_freq)</div><div class='add'>+		pc_set_min_freq(pc, pc-&gt;rp0_freq);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_adjust_requested_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;pc-&gt;freq_lock);</div><div class='add'>+</div><div class='add'>+	if (pc-&gt;user_requested_min != 0) {</div><div class='add'>+		ret = pc_set_min_freq(pc, pc-&gt;user_requested_min);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pc-&gt;user_requested_max != 0) {</div><div class='add'>+		ret = pc_set_max_freq(pc, pc-&gt;user_requested_max);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_gucrc_disable - Disable GuC RC</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ *</div><div class='add'>+ * Disables GuC RC by taking control of RC6 back from GuC.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = pc_to_xe(pc);</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	ret = pc_action_setup_gucrc(pc, XE_GUCRC_HOST_CONTROL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	xe_gt_idle_disable_c6(gt);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pc_init_pcode_freq(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	u32 min = DIV_ROUND_CLOSEST(pc-&gt;rpn_freq, GT_FREQUENCY_MULTIPLIER);</div><div class='add'>+	u32 max = DIV_ROUND_CLOSEST(pc-&gt;rp0_freq, GT_FREQUENCY_MULTIPLIER);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_pcode_init_min_freq_table(pc_to_gt(pc), min, max));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pc_init_freqs(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+</div><div class='add'>+	ret = pc_adjust_freq_bounds(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = pc_adjust_requested_freq(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	pc_update_rp_values(pc);</div><div class='add'>+</div><div class='add'>+	pc_init_pcode_freq(pc);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The frequencies are really ready for use only after the user</div><div class='add'>+	 * requested ones got restored.</div><div class='add'>+	 */</div><div class='add'>+	pc-&gt;freq_ready = true;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_start - Start GuC's Power Conservation component</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_start(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = pc_to_xe(pc);</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, xe_device_uc_enabled(xe));</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	ret = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_fail_force_wake;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc) {</div><div class='add'>+		if (xe-&gt;info.platform != XE_PVC)</div><div class='add'>+			xe_gt_idle_enable_c6(gt);</div><div class='add'>+</div><div class='add'>+		/* Request max possible since dynamic freq mgmt is not enabled */</div><div class='add'>+		pc_set_cur_freq(pc, UINT_MAX);</div><div class='add'>+</div><div class='add'>+		ret = 0;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(pc-&gt;bo-&gt;vmap.vaddr, 0, size);</div><div class='add'>+	slpc_shared_data_write(pc, header.size, size);</div><div class='add'>+</div><div class='add'>+	ret = pc_action_reset(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) {</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC PC Start failed\n");</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pc_init_freqs(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.platform == XE_PVC) {</div><div class='add'>+		xe_guc_pc_gucrc_disable(pc);</div><div class='add'>+		ret = 0;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pc_action_setup_gucrc(pc, XE_GUCRC_FIRMWARE_CONTROL);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));</div><div class='add'>+out_fail_force_wake:</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_stop - Stop GuC's Power Conservation component</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_stop(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = pc_to_xe(pc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(pc_to_xe(pc));</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc) {</div><div class='add'>+		xe_gt_idle_disable_c6(pc_to_gt(pc));</div><div class='add'>+		ret = 0;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;pc-&gt;freq_lock);</div><div class='add'>+	pc-&gt;freq_ready = false;</div><div class='add'>+	mutex_unlock(&amp;pc-&gt;freq_lock);</div><div class='add'>+</div><div class='add'>+	ret = pc_action_shutdown(pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_NOT_RUNNING)) {</div><div class='add'>+		drm_err(&amp;pc_to_xe(pc)-&gt;drm, "GuC PC Shutdown failed\n");</div><div class='add'>+		ret = -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	xe_device_mem_access_put(pc_to_xe(pc));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_fini - Finalize GuC's Power Conservation component</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+void xe_guc_pc_fini(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = pc_to_xe(pc);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc) {</div><div class='add'>+		xe_gt_idle_disable_c6(pc_to_gt(pc));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(xe_guc_pc_gucrc_disable(pc));</div><div class='add'>+	XE_WARN_ON(xe_guc_pc_stop(pc));</div><div class='add'>+	mutex_destroy(&amp;pc-&gt;freq_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_pc_init - Initialize GuC's Power Conservation component</div><div class='add'>+ * @pc: Xe_GuC_PC instance</div><div class='add'>+ */</div><div class='add'>+int xe_guc_pc_init(struct xe_guc_pc *pc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = pc_to_gt(pc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.skip_guc_pc)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;pc-&gt;freq_lock);</div><div class='add'>+</div><div class='add'>+	bo = xe_managed_bo_create_pin_map(xe, tile, size,</div><div class='add'>+					  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+					  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	pc-&gt;bo = bo;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h<br/>new file mode 100644<br/>index 000000000000..cecad8e9300b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_pc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc.h</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_PC_H_</div><div class='add'>+#define _XE_GUC_PC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_guc_pc_types.h"</div><div class='add'>+</div><div class='add'>+int xe_guc_pc_init(struct xe_guc_pc *pc);</div><div class='add'>+void xe_guc_pc_fini(struct xe_guc_pc *pc);</div><div class='add'>+int xe_guc_pc_start(struct xe_guc_pc *pc);</div><div class='add'>+int xe_guc_pc_stop(struct xe_guc_pc *pc);</div><div class='add'>+int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);</div><div class='add'>+</div><div class='add'>+u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);</div><div class='add'>+int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);</div><div class='add'>+u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);</div><div class='add'>+u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);</div><div class='add'>+u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc);</div><div class='add'>+int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq);</div><div class='add'>+int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq);</div><div class='add'>+int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq);</div><div class='add'>+int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq);</div><div class='add'>+</div><div class='add'>+enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc);</div><div class='add'>+u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc);</div><div class='add'>+u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);</div><div class='add'>+void xe_guc_pc_init_early(struct xe_guc_pc *pc);</div><div class='add'>+#endif /* _XE_GUC_PC_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h<br/>new file mode 100644<br/>index 000000000000..2afd0dbc3542<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_pc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_pc_types.h</a></div><div class='hunk'>@@ -0,0 +1,34 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_PC_TYPES_H_</div><div class='add'>+#define _XE_GUC_PC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_pc - GuC Power Conservation (PC)</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_pc {</div><div class='add'>+	/** @bo: GGTT buffer object that is shared with GuC PC */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	/** @rp0_freq: HW RP0 frequency - The Maximum one */</div><div class='add'>+	u32 rp0_freq;</div><div class='add'>+	/** @rpe_freq: HW RPe frequency - The Efficient one */</div><div class='add'>+	u32 rpe_freq;</div><div class='add'>+	/** @rpn_freq: HW RPN frequency - The Minimum one */</div><div class='add'>+	u32 rpn_freq;</div><div class='add'>+	/** @user_requested_min: Stash the minimum requested freq by user */</div><div class='add'>+	u32 user_requested_min;</div><div class='add'>+	/** @user_requested_max: Stash the maximum requested freq by user */</div><div class='add'>+	u32 user_requested_max;</div><div class='add'>+	/** @freq_lock: Let's protect the frequencies */</div><div class='add'>+	struct mutex freq_lock;</div><div class='add'>+	/** @freq_ready: Only handle freq changes, if they are really ready */</div><div class='add'>+	bool freq_ready;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif	/* _XE_GUC_PC_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c<br/>new file mode 100644<br/>index 000000000000..54ffcfcdd41f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_submit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit.c</a></div><div class='hunk'>@@ -0,0 +1,1989 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_guc_submit.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/bitmap.h&gt;</div><div class='add'>+#include &lt;linux/circ_buf.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/dma-fence-array.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/guc_actions_abi.h"</div><div class='add'>+#include "abi/guc_klvs_abi.h"</div><div class='add'>+#include "regs/xe_lrc_layout.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_devcoredump.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gpu_scheduler.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_ct.h"</div><div class='add'>+#include "xe_guc_exec_queue_types.h"</div><div class='add'>+#include "xe_guc_submit_types.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+#include "xe_ring_ops_types.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+static struct xe_guc *</div><div class='add'>+exec_queue_to_guc(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return &amp;q-&gt;gt-&gt;uc.guc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helpers for engine state, using an atomic as some of the bits can transition</div><div class='add'>+ * as the same time (e.g. a suspend can be happning at the same time as schedule</div><div class='add'>+ * engine done being processed).</div><div class='add'>+ */</div><div class='add'>+#define EXEC_QUEUE_STATE_REGISTERED		(1 &lt;&lt; 0)</div><div class='add'>+#define ENGINE_STATE_ENABLED		(1 &lt;&lt; 1)</div><div class='add'>+#define EXEC_QUEUE_STATE_PENDING_ENABLE	(1 &lt;&lt; 2)</div><div class='add'>+#define EXEC_QUEUE_STATE_PENDING_DISABLE	(1 &lt;&lt; 3)</div><div class='add'>+#define EXEC_QUEUE_STATE_DESTROYED		(1 &lt;&lt; 4)</div><div class='add'>+#define ENGINE_STATE_SUSPENDED		(1 &lt;&lt; 5)</div><div class='add'>+#define EXEC_QUEUE_STATE_RESET		(1 &lt;&lt; 6)</div><div class='add'>+#define ENGINE_STATE_KILLED		(1 &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+static bool exec_queue_registered(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; EXEC_QUEUE_STATE_REGISTERED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_registered(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(EXEC_QUEUE_STATE_REGISTERED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_exec_queue_registered(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_enabled(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; ENGINE_STATE_ENABLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_enabled(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(ENGINE_STATE_ENABLED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_exec_queue_enabled(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_and(~ENGINE_STATE_ENABLED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_pending_enable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; EXEC_QUEUE_STATE_PENDING_ENABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_pending_enable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_exec_queue_pending_enable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_pending_disable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; EXEC_QUEUE_STATE_PENDING_DISABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_pending_disable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_exec_queue_pending_disable(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_destroyed(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; EXEC_QUEUE_STATE_DESTROYED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_destroyed(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(EXEC_QUEUE_STATE_DESTROYED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_banned(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return (q-&gt;flags &amp; EXEC_QUEUE_FLAG_BANNED);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_banned(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	q-&gt;flags |= EXEC_QUEUE_FLAG_BANNED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_suspended(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; ENGINE_STATE_SUSPENDED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_suspended(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(ENGINE_STATE_SUSPENDED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void clear_exec_queue_suspended(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_and(~ENGINE_STATE_SUSPENDED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_reset(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; EXEC_QUEUE_STATE_RESET;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_reset(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(EXEC_QUEUE_STATE_RESET, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_killed(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;q-&gt;guc-&gt;state) &amp; ENGINE_STATE_KILLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_exec_queue_killed(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	atomic_or(ENGINE_STATE_KILLED, &amp;q-&gt;guc-&gt;state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool exec_queue_killed_or_banned(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return exec_queue_killed(q) || exec_queue_banned(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PROVE_LOCKING</div><div class='add'>+static int alloc_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_SUBMIT_WQ; ++i) {</div><div class='add'>+		guc-&gt;submission_state.submit_wq_pool[i] =</div><div class='add'>+			alloc_ordered_workqueue("submit_wq", 0);</div><div class='add'>+		if (!guc-&gt;submission_state.submit_wq_pool[i])</div><div class='add'>+			goto err_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_free:</div><div class='add'>+	while (i)</div><div class='add'>+		destroy_workqueue(guc-&gt;submission_state.submit_wq_pool[--i]);</div><div class='add'>+</div><div class='add'>+	return -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; NUM_SUBMIT_WQ; ++i)</div><div class='add'>+		destroy_workqueue(guc-&gt;submission_state.submit_wq_pool[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int idx = guc-&gt;submission_state.submit_wq_idx++ % NUM_SUBMIT_WQ;</div><div class='add'>+</div><div class='add'>+	return guc-&gt;submission_state.submit_wq_pool[idx];</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+static int alloc_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static void guc_submit_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = arg;</div><div class='add'>+</div><div class='add'>+	xa_destroy(&amp;guc-&gt;submission_state.exec_queue_lookup);</div><div class='add'>+	ida_destroy(&amp;guc-&gt;submission_state.guc_ids);</div><div class='add'>+	bitmap_free(guc-&gt;submission_state.guc_ids_bitmap);</div><div class='add'>+	free_submit_wq(guc);</div><div class='add'>+	mutex_destroy(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define GUC_ID_MAX		65535</div><div class='add'>+#define GUC_ID_NUMBER_MLRC	4096</div><div class='add'>+#define GUC_ID_NUMBER_SLRC	(GUC_ID_MAX - GUC_ID_NUMBER_MLRC)</div><div class='add'>+#define GUC_ID_START_MLRC	GUC_ID_NUMBER_SLRC</div><div class='add'>+</div><div class='add'>+static const struct xe_exec_queue_ops guc_exec_queue_ops;</div><div class='add'>+</div><div class='add'>+static void primelockdep(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	if (!IS_ENABLED(CONFIG_LOCKDEP))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	fs_reclaim_acquire(GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+	might_lock(&amp;guc-&gt;submission_state.suspend.lock);</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	fs_reclaim_release(GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_init(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gt *gt = guc_to_gt(guc);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	guc-&gt;submission_state.guc_ids_bitmap =</div><div class='add'>+		bitmap_zalloc(GUC_ID_NUMBER_MLRC, GFP_KERNEL);</div><div class='add'>+	if (!guc-&gt;submission_state.guc_ids_bitmap)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	err = alloc_submit_wq(guc);</div><div class='add'>+	if (err) {</div><div class='add'>+		bitmap_free(guc-&gt;submission_state.guc_ids_bitmap);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt-&gt;exec_queue_ops = &amp;guc_exec_queue_ops;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+	xa_init(&amp;guc-&gt;submission_state.exec_queue_lookup);</div><div class='add'>+	ida_init(&amp;guc-&gt;submission_state.guc_ids);</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;guc-&gt;submission_state.suspend.lock);</div><div class='add'>+	guc-&gt;submission_state.suspend.context = dma_fence_context_alloc(1);</div><div class='add'>+</div><div class='add'>+	primelockdep(guc);</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, guc_submit_fini, guc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xa_count; ++i)</div><div class='add'>+		xa_erase(&amp;guc-&gt;submission_state.exec_queue_lookup, q-&gt;guc-&gt;id + i);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q))</div><div class='add'>+		bitmap_release_region(guc-&gt;submission_state.guc_ids_bitmap,</div><div class='add'>+				      q-&gt;guc-&gt;id - GUC_ID_START_MLRC,</div><div class='add'>+				      order_base_2(q-&gt;width));</div><div class='add'>+	else</div><div class='add'>+		ida_simple_remove(&amp;guc-&gt;submission_state.guc_ids, q-&gt;guc-&gt;id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	void *ptr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path,</div><div class='add'>+	 * worse case user gets -ENOMEM on engine create and has to try again.</div><div class='add'>+	 *</div><div class='add'>+	 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent</div><div class='add'>+	 * failure.</div><div class='add'>+	 */</div><div class='add'>+	lockdep_assert_held(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		void *bitmap = guc-&gt;submission_state.guc_ids_bitmap;</div><div class='add'>+</div><div class='add'>+		ret = bitmap_find_free_region(bitmap, GUC_ID_NUMBER_MLRC,</div><div class='add'>+					      order_base_2(q-&gt;width));</div><div class='add'>+	} else {</div><div class='add'>+		ret = ida_simple_get(&amp;guc-&gt;submission_state.guc_ids, 0,</div><div class='add'>+				     GUC_ID_NUMBER_SLRC, GFP_NOWAIT);</div><div class='add'>+	}</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	q-&gt;guc-&gt;id = ret;</div><div class='add'>+	if (xe_exec_queue_is_parallel(q))</div><div class='add'>+		q-&gt;guc-&gt;id += GUC_ID_START_MLRC;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; q-&gt;width; ++i) {</div><div class='add'>+		ptr = xa_store(&amp;guc-&gt;submission_state.exec_queue_lookup,</div><div class='add'>+			       q-&gt;guc-&gt;id + i, q, GFP_NOWAIT);</div><div class='add'>+		if (IS_ERR(ptr)) {</div><div class='add'>+			ret = PTR_ERR(ptr);</div><div class='add'>+			goto err_release;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_release:</div><div class='add'>+	__release_guc_id(guc, q, i);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+	__release_guc_id(guc, q, q-&gt;width);</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct exec_queue_policy {</div><div class='add'>+	u32 count;</div><div class='add'>+	struct guc_update_exec_queue_policy h2g;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy)</div><div class='add'>+{</div><div class='add'>+	size_t bytes = sizeof(policy-&gt;h2g.header) +</div><div class='add'>+		       (sizeof(policy-&gt;h2g.klv[0]) * policy-&gt;count);</div><div class='add'>+</div><div class='add'>+	return bytes / sizeof(u32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy,</div><div class='add'>+					      u16 guc_id)</div><div class='add'>+{</div><div class='add'>+	policy-&gt;h2g.header.action =</div><div class='add'>+		XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;</div><div class='add'>+	policy-&gt;h2g.header.guc_id = guc_id;</div><div class='add'>+	policy-&gt;count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \</div><div class='add'>+static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \</div><div class='add'>+					   u32 data) \</div><div class='add'>+{ \</div><div class='add'>+	XE_WARN_ON(policy-&gt;count &gt;= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \</div><div class='add'>+\</div><div class='add'>+	policy-&gt;h2g.klv[policy-&gt;count].kl = \</div><div class='add'>+		FIELD_PREP(GUC_KLV_0_KEY, \</div><div class='add'>+			   GUC_CONTEXT_POLICIES_KLV_ID_##id) | \</div><div class='add'>+		FIELD_PREP(GUC_KLV_0_LEN, 1); \</div><div class='add'>+	policy-&gt;h2g.klv[policy-&gt;count].value = data; \</div><div class='add'>+	policy-&gt;count++; \</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)</div><div class='add'>+MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)</div><div class='add'>+MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY)</div><div class='add'>+#undef MAKE_EXEC_QUEUE_POLICY_ADD</div><div class='add'>+</div><div class='add'>+static const int xe_exec_queue_prio_to_guc[] = {</div><div class='add'>+	[XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL,</div><div class='add'>+	[XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL,</div><div class='add'>+	[XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH,</div><div class='add'>+	[XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct exec_queue_policy policy;</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	enum xe_exec_queue_priority prio = q-&gt;sched_props.priority;</div><div class='add'>+	u32 timeslice_us = q-&gt;sched_props.timeslice_us;</div><div class='add'>+	u32 preempt_timeout_us = q-&gt;sched_props.preempt_timeout_us;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, exec_queue_registered(q));</div><div class='add'>+</div><div class='add'>+	__guc_exec_queue_policy_start_klv(&amp;policy, q-&gt;guc-&gt;id);</div><div class='add'>+	__guc_exec_queue_policy_add_priority(&amp;policy, xe_exec_queue_prio_to_guc[prio]);</div><div class='add'>+	__guc_exec_queue_policy_add_execution_quantum(&amp;policy, timeslice_us);</div><div class='add'>+	__guc_exec_queue_policy_add_preemption_timeout(&amp;policy, preempt_timeout_us);</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, (u32 *)&amp;policy.h2g,</div><div class='add'>+		       __guc_exec_queue_policy_action_size(&amp;policy), 0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct exec_queue_policy policy;</div><div class='add'>+</div><div class='add'>+	__guc_exec_queue_policy_start_klv(&amp;policy, q-&gt;guc-&gt;id);</div><div class='add'>+	__guc_exec_queue_policy_add_preemption_timeout(&amp;policy, 1);</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, (u32 *)&amp;policy.h2g,</div><div class='add'>+		       __guc_exec_queue_policy_action_size(&amp;policy), 0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define parallel_read(xe_, map_, field_) \</div><div class='add'>+	xe_map_rd_field(xe_, &amp;map_, 0, struct guc_submit_parallel_scratch, \</div><div class='add'>+			field_)</div><div class='add'>+#define parallel_write(xe_, map_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(xe_, &amp;map_, 0, struct guc_submit_parallel_scratch, \</div><div class='add'>+			field_, val_)</div><div class='add'>+</div><div class='add'>+static void __register_mlrc_engine(struct xe_guc *guc,</div><div class='add'>+				   struct xe_exec_queue *q,</div><div class='add'>+				   struct guc_ctxt_registration_info *info)</div><div class='add'>+{</div><div class='add'>+#define MAX_MLRC_REG_SIZE      (13 + XE_HW_ENGINE_MAX_INSTANCE * 2)</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u32 action[MAX_MLRC_REG_SIZE];</div><div class='add'>+	int len = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, xe_exec_queue_is_parallel(q));</div><div class='add'>+</div><div class='add'>+	action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;</div><div class='add'>+	action[len++] = info-&gt;flags;</div><div class='add'>+	action[len++] = info-&gt;context_idx;</div><div class='add'>+	action[len++] = info-&gt;engine_class;</div><div class='add'>+	action[len++] = info-&gt;engine_submit_mask;</div><div class='add'>+	action[len++] = info-&gt;wq_desc_lo;</div><div class='add'>+	action[len++] = info-&gt;wq_desc_hi;</div><div class='add'>+	action[len++] = info-&gt;wq_base_lo;</div><div class='add'>+	action[len++] = info-&gt;wq_base_hi;</div><div class='add'>+	action[len++] = info-&gt;wq_size;</div><div class='add'>+	action[len++] = q-&gt;width;</div><div class='add'>+	action[len++] = info-&gt;hwlrca_lo;</div><div class='add'>+	action[len++] = info-&gt;hwlrca_hi;</div><div class='add'>+</div><div class='add'>+	for (i = 1; i &lt; q-&gt;width; ++i) {</div><div class='add'>+		struct xe_lrc *lrc = q-&gt;lrc + i;</div><div class='add'>+</div><div class='add'>+		action[len++] = lower_32_bits(xe_lrc_descriptor(lrc));</div><div class='add'>+		action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, len &lt;= MAX_MLRC_REG_SIZE);</div><div class='add'>+#undef MAX_MLRC_REG_SIZE</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, action, len, 0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __register_engine(struct xe_guc *guc,</div><div class='add'>+			      struct guc_ctxt_registration_info *info)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_REGISTER_CONTEXT,</div><div class='add'>+		info-&gt;flags,</div><div class='add'>+		info-&gt;context_idx,</div><div class='add'>+		info-&gt;engine_class,</div><div class='add'>+		info-&gt;engine_submit_mask,</div><div class='add'>+		info-&gt;wq_desc_lo,</div><div class='add'>+		info-&gt;wq_desc_hi,</div><div class='add'>+		info-&gt;wq_base_lo,</div><div class='add'>+		info-&gt;wq_base_hi,</div><div class='add'>+		info-&gt;wq_size,</div><div class='add'>+		info-&gt;hwlrca_lo,</div><div class='add'>+		info-&gt;hwlrca_hi,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, action, ARRAY_SIZE(action), 0, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void register_engine(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_lrc *lrc = q-&gt;lrc;</div><div class='add'>+	struct guc_ctxt_registration_info info;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !exec_queue_registered(q));</div><div class='add'>+</div><div class='add'>+	memset(&amp;info, 0, sizeof(info));</div><div class='add'>+	info.context_idx = q-&gt;guc-&gt;id;</div><div class='add'>+	info.engine_class = xe_engine_class_to_guc_class(q-&gt;class);</div><div class='add'>+	info.engine_submit_mask = q-&gt;logical_mask;</div><div class='add'>+	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));</div><div class='add'>+	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));</div><div class='add'>+	info.flags = CONTEXT_REGISTRATION_FLAG_KMD;</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		u32 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);</div><div class='add'>+		struct iosys_map map = xe_lrc_parallel_map(lrc);</div><div class='add'>+</div><div class='add'>+		info.wq_desc_lo = lower_32_bits(ggtt_addr +</div><div class='add'>+			offsetof(struct guc_submit_parallel_scratch, wq_desc));</div><div class='add'>+		info.wq_desc_hi = upper_32_bits(ggtt_addr +</div><div class='add'>+			offsetof(struct guc_submit_parallel_scratch, wq_desc));</div><div class='add'>+		info.wq_base_lo = lower_32_bits(ggtt_addr +</div><div class='add'>+			offsetof(struct guc_submit_parallel_scratch, wq[0]));</div><div class='add'>+		info.wq_base_hi = upper_32_bits(ggtt_addr +</div><div class='add'>+			offsetof(struct guc_submit_parallel_scratch, wq[0]));</div><div class='add'>+		info.wq_size = WQ_SIZE;</div><div class='add'>+</div><div class='add'>+		q-&gt;guc-&gt;wqi_head = 0;</div><div class='add'>+		q-&gt;guc-&gt;wqi_tail = 0;</div><div class='add'>+		xe_map_memset(xe, &amp;map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE);</div><div class='add'>+		parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We must keep a reference for LR engines if engine is registered with</div><div class='add'>+	 * the GuC as jobs signal immediately and can't destroy an engine if the</div><div class='add'>+	 * GuC has a reference to it.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_exec_queue_is_lr(q))</div><div class='add'>+		xe_exec_queue_get(q);</div><div class='add'>+</div><div class='add'>+	set_exec_queue_registered(q);</div><div class='add'>+	trace_xe_exec_queue_register(q);</div><div class='add'>+	if (xe_exec_queue_is_parallel(q))</div><div class='add'>+		__register_mlrc_engine(guc, q, &amp;info);</div><div class='add'>+	else</div><div class='add'>+		__register_engine(guc, &amp;info);</div><div class='add'>+	init_policies(guc, q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 wq_space_until_wrap(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return (WQ_SIZE - q-&gt;guc-&gt;wqi_tail);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct iosys_map map = xe_lrc_parallel_map(q-&gt;lrc);</div><div class='add'>+	unsigned int sleep_period_ms = 1;</div><div class='add'>+</div><div class='add'>+#define AVAILABLE_SPACE \</div><div class='add'>+	CIRC_SPACE(q-&gt;guc-&gt;wqi_tail, q-&gt;guc-&gt;wqi_head, WQ_SIZE)</div><div class='add'>+	if (wqi_size &gt; AVAILABLE_SPACE) {</div><div class='add'>+try_again:</div><div class='add'>+		q-&gt;guc-&gt;wqi_head = parallel_read(xe, map, wq_desc.head);</div><div class='add'>+		if (wqi_size &gt; AVAILABLE_SPACE) {</div><div class='add'>+			if (sleep_period_ms == 1024) {</div><div class='add'>+				xe_gt_reset_async(q-&gt;gt);</div><div class='add'>+				return -ENODEV;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			msleep(sleep_period_ms);</div><div class='add'>+			sleep_period_ms &lt;&lt;= 1;</div><div class='add'>+			goto try_again;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+#undef AVAILABLE_SPACE</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wq_noop_append(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct iosys_map map = xe_lrc_parallel_map(q-&gt;lrc);</div><div class='add'>+	u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1;</div><div class='add'>+</div><div class='add'>+	if (wq_wait_for_space(q, wq_space_until_wrap(q)))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, FIELD_FIT(WQ_LEN_MASK, len_dw));</div><div class='add'>+</div><div class='add'>+	parallel_write(xe, map, wq[q-&gt;guc-&gt;wqi_tail / sizeof(u32)],</div><div class='add'>+		       FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) |</div><div class='add'>+		       FIELD_PREP(WQ_LEN_MASK, len_dw));</div><div class='add'>+	q-&gt;guc-&gt;wqi_tail = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wq_item_append(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct iosys_map map = xe_lrc_parallel_map(q-&gt;lrc);</div><div class='add'>+#define WQ_HEADER_SIZE	4	/* Includes 1 LRC address too */</div><div class='add'>+	u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)];</div><div class='add'>+	u32 wqi_size = (q-&gt;width + (WQ_HEADER_SIZE - 1)) * sizeof(u32);</div><div class='add'>+	u32 len_dw = (wqi_size / sizeof(u32)) - 1;</div><div class='add'>+	int i = 0, j;</div><div class='add'>+</div><div class='add'>+	if (wqi_size &gt; wq_space_until_wrap(q)) {</div><div class='add'>+		if (wq_noop_append(q))</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='add'>+	if (wq_wait_for_space(q, wqi_size))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) |</div><div class='add'>+		FIELD_PREP(WQ_LEN_MASK, len_dw);</div><div class='add'>+	wqi[i++] = xe_lrc_descriptor(q-&gt;lrc);</div><div class='add'>+	wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q-&gt;guc-&gt;id) |</div><div class='add'>+		FIELD_PREP(WQ_RING_TAIL_MASK, q-&gt;lrc-&gt;ring.tail / sizeof(u64));</div><div class='add'>+	wqi[i++] = 0;</div><div class='add'>+	for (j = 1; j &lt; q-&gt;width; ++j) {</div><div class='add'>+		struct xe_lrc *lrc = q-&gt;lrc + j;</div><div class='add'>+</div><div class='add'>+		wqi[i++] = lrc-&gt;ring.tail / sizeof(u64);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, i == wqi_size / sizeof(u32));</div><div class='add'>+</div><div class='add'>+	iosys_map_incr(&amp;map, offsetof(struct guc_submit_parallel_scratch,</div><div class='add'>+				      wq[q-&gt;guc-&gt;wqi_tail / sizeof(u32)]));</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;map, 0, wqi, wqi_size);</div><div class='add'>+	q-&gt;guc-&gt;wqi_tail += wqi_size;</div><div class='add'>+	xe_assert(xe, q-&gt;guc-&gt;wqi_tail &lt;= WQ_SIZE);</div><div class='add'>+</div><div class='add'>+	xe_device_wmb(xe);</div><div class='add'>+</div><div class='add'>+	map = xe_lrc_parallel_map(q-&gt;lrc);</div><div class='add'>+	parallel_write(xe, map, wq_desc.tail, q-&gt;guc-&gt;wqi_tail);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define RESUME_PENDING	~0x0ull</div><div class='add'>+static void submit_exec_queue(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_lrc *lrc = q-&gt;lrc;</div><div class='add'>+	u32 action[3];</div><div class='add'>+	u32 g2h_len = 0;</div><div class='add'>+	u32 num_g2h = 0;</div><div class='add'>+	int len = 0;</div><div class='add'>+	bool extra_submit = false;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, exec_queue_registered(q));</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_parallel(q))</div><div class='add'>+		wq_item_append(q);</div><div class='add'>+	else</div><div class='add'>+		xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc-&gt;ring.tail);</div><div class='add'>+</div><div class='add'>+	if (exec_queue_suspended(q) &amp;&amp; !xe_exec_queue_is_parallel(q))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!exec_queue_enabled(q) &amp;&amp; !exec_queue_suspended(q)) {</div><div class='add'>+		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;</div><div class='add'>+		action[len++] = q-&gt;guc-&gt;id;</div><div class='add'>+		action[len++] = GUC_CONTEXT_ENABLE;</div><div class='add'>+		g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET;</div><div class='add'>+		num_g2h = 1;</div><div class='add'>+		if (xe_exec_queue_is_parallel(q))</div><div class='add'>+			extra_submit = true;</div><div class='add'>+</div><div class='add'>+		q-&gt;guc-&gt;resume_time = RESUME_PENDING;</div><div class='add'>+		set_exec_queue_pending_enable(q);</div><div class='add'>+		set_exec_queue_enabled(q);</div><div class='add'>+		trace_xe_exec_queue_scheduling_enable(q);</div><div class='add'>+	} else {</div><div class='add'>+		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;</div><div class='add'>+		action[len++] = q-&gt;guc-&gt;id;</div><div class='add'>+		trace_xe_exec_queue_submit(q);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, action, len, g2h_len, num_g2h);</div><div class='add'>+</div><div class='add'>+	if (extra_submit) {</div><div class='add'>+		len = 0;</div><div class='add'>+		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;</div><div class='add'>+		action[len++] = q-&gt;guc-&gt;id;</div><div class='add'>+		trace_xe_exec_queue_submit(q);</div><div class='add'>+</div><div class='add'>+		xe_guc_ct_send(&amp;guc-&gt;ct, action, len, 0, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+guc_exec_queue_run_job(struct drm_sched_job *drm_job)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job = to_xe_sched_job(drm_job);</div><div class='add'>+	struct xe_exec_queue *q = job-&gt;q;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	bool lr = xe_exec_queue_is_lr(q);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) ||</div><div class='add'>+		  exec_queue_banned(q) || exec_queue_suspended(q));</div><div class='add'>+</div><div class='add'>+	trace_xe_sched_job_run(job);</div><div class='add'>+</div><div class='add'>+	if (!exec_queue_killed_or_banned(q) &amp;&amp; !xe_sched_job_is_error(job)) {</div><div class='add'>+		if (!exec_queue_registered(q))</div><div class='add'>+			register_engine(q);</div><div class='add'>+		if (!lr)	/* LR jobs are emitted in the exec IOCTL */</div><div class='add'>+			q-&gt;ring_ops-&gt;emit_job(job);</div><div class='add'>+		submit_exec_queue(q);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (lr) {</div><div class='add'>+		xe_sched_job_set_error(job, -EOPNOTSUPP);</div><div class='add'>+		return NULL;</div><div class='add'>+	} else if (test_and_set_bit(JOB_FLAG_SUBMIT, &amp;job-&gt;fence-&gt;flags)) {</div><div class='add'>+		return job-&gt;fence;</div><div class='add'>+	} else {</div><div class='add'>+		return dma_fence_get(job-&gt;fence);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_free_job(struct drm_sched_job *drm_job)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job = to_xe_sched_job(drm_job);</div><div class='add'>+</div><div class='add'>+	trace_xe_sched_job_free(job);</div><div class='add'>+	xe_sched_job_put(job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_read_stopped(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	return atomic_read(&amp;guc-&gt;submission_state.stopped);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable)			\</div><div class='add'>+	u32 action[] = {						\</div><div class='add'>+		XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET,			\</div><div class='add'>+		q-&gt;guc-&gt;id,						\</div><div class='add'>+		GUC_CONTEXT_##enable_disable,				\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static void disable_scheduling_deregister(struct xe_guc *guc,</div><div class='add'>+					  struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	set_min_preemption_timeout(guc, q);</div><div class='add'>+	smp_rmb();</div><div class='add'>+	ret = wait_event_timeout(guc-&gt;ct.wq, !exec_queue_pending_enable(q) ||</div><div class='add'>+				 guc_read_stopped(guc), HZ * 5);</div><div class='add'>+	if (!ret) {</div><div class='add'>+		struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Pending enable failed to respond");</div><div class='add'>+		xe_sched_submission_start(sched);</div><div class='add'>+		xe_gt_reset_async(q-&gt;gt);</div><div class='add'>+		xe_sched_tdr_queue_imm(sched);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clear_exec_queue_enabled(q);</div><div class='add'>+	set_exec_queue_pending_disable(q);</div><div class='add'>+	set_exec_queue_destroyed(q);</div><div class='add'>+	trace_xe_exec_queue_scheduling_disable(q);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H</div><div class='add'>+	 * handler and we are not allowed to reserved G2H space in handlers.</div><div class='add'>+	 */</div><div class='add'>+	xe_guc_ct_send(&amp;guc-&gt;ct, action, ARRAY_SIZE(action),</div><div class='add'>+		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +</div><div class='add'>+		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE)</div><div class='add'>+static void simple_error_capture(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct drm_printer p = drm_err_printer("");</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	u32 adj_logical_mask = q-&gt;logical_mask;</div><div class='add'>+	u32 width_mask = (0x1 &lt;&lt; q-&gt;width) - 1;</div><div class='add'>+	int i;</div><div class='add'>+	bool cookie;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;vm &amp;&amp; !q-&gt;vm-&gt;error_capture.capture_once) {</div><div class='add'>+		q-&gt;vm-&gt;error_capture.capture_once = true;</div><div class='add'>+		cookie = dma_fence_begin_signalling();</div><div class='add'>+		for (i = 0; q-&gt;width &gt; 1 &amp;&amp; i &lt; XE_HW_ENGINE_MAX_INSTANCE;) {</div><div class='add'>+			if (adj_logical_mask &amp; BIT(i)) {</div><div class='add'>+				adj_logical_mask |= width_mask &lt;&lt; i;</div><div class='add'>+				i += q-&gt;width;</div><div class='add'>+			} else {</div><div class='add'>+				++i;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_force_wake_get(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL);</div><div class='add'>+		xe_guc_ct_print(&amp;guc-&gt;ct, &amp;p, true);</div><div class='add'>+		guc_exec_queue_print(q, &amp;p);</div><div class='add'>+		for_each_hw_engine(hwe, guc_to_gt(guc), id) {</div><div class='add'>+			if (hwe-&gt;class != q-&gt;hwe-&gt;class ||</div><div class='add'>+			    !(BIT(hwe-&gt;logical_instance) &amp; adj_logical_mask))</div><div class='add'>+				continue;</div><div class='add'>+			xe_hw_engine_print(hwe, &amp;p);</div><div class='add'>+		}</div><div class='add'>+		xe_analyze_vm(&amp;p, q-&gt;vm, q-&gt;gt-&gt;info.id);</div><div class='add'>+		xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL);</div><div class='add'>+		dma_fence_end_signalling(cookie);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+static void simple_error_capture(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */</div><div class='add'>+	wake_up_all(&amp;xe-&gt;ufence_wq);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_lr(q))</div><div class='add'>+		queue_work(guc_to_gt(guc)-&gt;ordered_wq, &amp;q-&gt;guc-&gt;lr_tdr);</div><div class='add'>+	else</div><div class='add'>+		xe_sched_tdr_queue_imm(&amp;q-&gt;guc-&gt;sched);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_exec_queue *ge =</div><div class='add'>+		container_of(w, struct xe_guc_exec_queue, lr_tdr);</div><div class='add'>+	struct xe_exec_queue *q = ge-&gt;q;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;ge-&gt;sched;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, xe_exec_queue_is_lr(q));</div><div class='add'>+	trace_xe_exec_queue_lr_cleanup(q);</div><div class='add'>+</div><div class='add'>+	/* Kill the run_job / process_msg entry points */</div><div class='add'>+	xe_sched_submission_stop(sched);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Engine state now mostly stable, disable scheduling / deregister if</div><div class='add'>+	 * needed. This cleanup routine might be called multiple times, where</div><div class='add'>+	 * the actual async engine deregister drops the final engine ref.</div><div class='add'>+	 * Calling disable_scheduling_deregister will mark the engine as</div><div class='add'>+	 * destroyed and fire off the CT requests to disable scheduling /</div><div class='add'>+	 * deregister, which we only want to do once. We also don't want to mark</div><div class='add'>+	 * the engine as pending_disable again as this may race with the</div><div class='add'>+	 * xe_guc_deregister_done_handler() which treats it as an unexpected</div><div class='add'>+	 * state.</div><div class='add'>+	 */</div><div class='add'>+	if (exec_queue_registered(q) &amp;&amp; !exec_queue_destroyed(q)) {</div><div class='add'>+		struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		set_exec_queue_banned(q);</div><div class='add'>+		disable_scheduling_deregister(guc, q);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Must wait for scheduling to be disabled before signalling</div><div class='add'>+		 * any fences, if GT broken the GT reset code should signal us.</div><div class='add'>+		 */</div><div class='add'>+		ret = wait_event_timeout(guc-&gt;ct.wq,</div><div class='add'>+					 !exec_queue_pending_disable(q) ||</div><div class='add'>+					 guc_read_stopped(guc), HZ * 5);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm, "Schedule disable failed to respond");</div><div class='add'>+			xe_sched_submission_start(sched);</div><div class='add'>+			xe_gt_reset_async(q-&gt;gt);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_submission_start(sched);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum drm_gpu_sched_stat</div><div class='add'>+guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job = to_xe_sched_job(drm_job);</div><div class='add'>+	struct xe_sched_job *tmp_job;</div><div class='add'>+	struct xe_exec_queue *q = job-&gt;q;</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+	struct xe_device *xe = guc_to_xe(exec_queue_to_guc(q));</div><div class='add'>+	int err = -ETIME;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &amp;job-&gt;fence-&gt;flags)) {</div><div class='add'>+		xe_assert(xe, !(q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL));</div><div class='add'>+		xe_assert(xe, !(q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM &amp;&amp; !exec_queue_killed(q)));</div><div class='add'>+</div><div class='add'>+		drm_notice(&amp;xe-&gt;drm, "Timedout job: seqno=%u, guc_id=%d, flags=0x%lx",</div><div class='add'>+			   xe_sched_job_seqno(job), q-&gt;guc-&gt;id, q-&gt;flags);</div><div class='add'>+		simple_error_capture(q);</div><div class='add'>+		xe_devcoredump(q);</div><div class='add'>+	} else {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Timedout signaled job: seqno=%u, guc_id=%d, flags=0x%lx",</div><div class='add'>+			 xe_sched_job_seqno(job), q-&gt;guc-&gt;id, q-&gt;flags);</div><div class='add'>+	}</div><div class='add'>+	trace_xe_sched_job_timedout(job);</div><div class='add'>+</div><div class='add'>+	/* Kill the run_job entry point */</div><div class='add'>+	xe_sched_submission_stop(sched);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Kernel jobs should never fail, nor should VM jobs if they do</div><div class='add'>+	 * somethings has gone wrong and the GT needs a reset</div><div class='add'>+	 */</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL ||</div><div class='add'>+	    (q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM &amp;&amp; !exec_queue_killed(q))) {</div><div class='add'>+		if (!xe_sched_invalidate_job(job, 2)) {</div><div class='add'>+			xe_sched_add_pending_job(sched, job);</div><div class='add'>+			xe_sched_submission_start(sched);</div><div class='add'>+			xe_gt_reset_async(q-&gt;gt);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Engine state now stable, disable scheduling if needed */</div><div class='add'>+	if (exec_queue_registered(q)) {</div><div class='add'>+		struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		if (exec_queue_reset(q))</div><div class='add'>+			err = -EIO;</div><div class='add'>+		set_exec_queue_banned(q);</div><div class='add'>+		if (!exec_queue_destroyed(q)) {</div><div class='add'>+			xe_exec_queue_get(q);</div><div class='add'>+			disable_scheduling_deregister(guc, q);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Must wait for scheduling to be disabled before signalling</div><div class='add'>+		 * any fences, if GT broken the GT reset code should signal us.</div><div class='add'>+		 *</div><div class='add'>+		 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault</div><div class='add'>+		 * error) messages which can cause the schedule disable to get</div><div class='add'>+		 * lost. If this occurs, trigger a GT reset to recover.</div><div class='add'>+		 */</div><div class='add'>+		smp_rmb();</div><div class='add'>+		ret = wait_event_timeout(guc-&gt;ct.wq,</div><div class='add'>+					 !exec_queue_pending_disable(q) ||</div><div class='add'>+					 guc_read_stopped(guc), HZ * 5);</div><div class='add'>+		if (!ret || guc_read_stopped(guc)) {</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm, "Schedule disable failed to respond");</div><div class='add'>+			xe_sched_add_pending_job(sched, job);</div><div class='add'>+			xe_sched_submission_start(sched);</div><div class='add'>+			xe_gt_reset_async(q-&gt;gt);</div><div class='add'>+			xe_sched_tdr_queue_imm(sched);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Stop fence signaling */</div><div class='add'>+	xe_hw_fence_irq_stop(q-&gt;fence_irq);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Fence state now stable, stop / start scheduler which cleans up any</div><div class='add'>+	 * fences that are complete</div><div class='add'>+	 */</div><div class='add'>+	xe_sched_add_pending_job(sched, job);</div><div class='add'>+	xe_sched_submission_start(sched);</div><div class='add'>+	xe_guc_exec_queue_trigger_cleanup(q);</div><div class='add'>+</div><div class='add'>+	/* Mark all outstanding jobs as bad, thus completing them */</div><div class='add'>+	spin_lock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+	list_for_each_entry(tmp_job, &amp;sched-&gt;base.pending_list, drm.list)</div><div class='add'>+		xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED);</div><div class='add'>+	spin_unlock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+</div><div class='add'>+	/* Start fence signaling */</div><div class='add'>+	xe_hw_fence_irq_start(q-&gt;fence_irq);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	return DRM_GPU_SCHED_STAT_NOMINAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_fini_async(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_exec_queue *ge =</div><div class='add'>+		container_of(w, struct xe_guc_exec_queue, fini_async);</div><div class='add'>+	struct xe_exec_queue *q = ge-&gt;q;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_destroy(q);</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_lr(q))</div><div class='add'>+		cancel_work_sync(&amp;ge-&gt;lr_tdr);</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERSISTENT)</div><div class='add'>+		xe_device_remove_persistent_exec_queues(gt_to_xe(q-&gt;gt), q);</div><div class='add'>+	release_guc_id(guc, q);</div><div class='add'>+	xe_sched_entity_fini(&amp;ge-&gt;entity);</div><div class='add'>+	xe_sched_fini(&amp;ge-&gt;sched);</div><div class='add'>+</div><div class='add'>+	kfree(ge);</div><div class='add'>+	xe_exec_queue_fini(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_fini_async(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	INIT_WORK(&amp;q-&gt;guc-&gt;fini_async, __guc_exec_queue_fini_async);</div><div class='add'>+</div><div class='add'>+	/* We must block on kernel engines so slabs are empty on driver unload */</div><div class='add'>+	if (q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERMANENT)</div><div class='add'>+		__guc_exec_queue_fini_async(&amp;q-&gt;guc-&gt;fini_async);</div><div class='add'>+	else</div><div class='add'>+		queue_work(system_wq, &amp;q-&gt;guc-&gt;fini_async);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Might be done from within the GPU scheduler, need to do async as we</div><div class='add'>+	 * fini the scheduler when the engine is fini'd, the scheduler can't</div><div class='add'>+	 * complete fini within itself (circular dependency). Async resolves</div><div class='add'>+	 * this we and don't really care when everything is fini'd, just that it</div><div class='add'>+	 * is.</div><div class='add'>+	 */</div><div class='add'>+	guc_exec_queue_fini_async(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = msg-&gt;private_data;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !(q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERMANENT));</div><div class='add'>+	trace_xe_exec_queue_cleanup_entity(q);</div><div class='add'>+</div><div class='add'>+	if (exec_queue_registered(q))</div><div class='add'>+		disable_scheduling_deregister(guc, q);</div><div class='add'>+	else</div><div class='add'>+		__guc_exec_queue_fini(guc, q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return !exec_queue_killed_or_banned(q) &amp;&amp; exec_queue_registered(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = msg-&gt;private_data;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+</div><div class='add'>+	if (guc_exec_queue_allowed_to_change_state(q))</div><div class='add'>+		init_policies(guc, q);</div><div class='add'>+	kfree(msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void suspend_fence_signal(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) ||</div><div class='add'>+		  guc_read_stopped(guc));</div><div class='add'>+	xe_assert(xe, q-&gt;guc-&gt;suspend_pending);</div><div class='add'>+</div><div class='add'>+	q-&gt;guc-&gt;suspend_pending = false;</div><div class='add'>+	smp_wmb();</div><div class='add'>+	wake_up(&amp;q-&gt;guc-&gt;suspend_wait);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = msg-&gt;private_data;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+</div><div class='add'>+	if (guc_exec_queue_allowed_to_change_state(q) &amp;&amp; !exec_queue_suspended(q) &amp;&amp;</div><div class='add'>+	    exec_queue_enabled(q)) {</div><div class='add'>+		wait_event(guc-&gt;ct.wq, q-&gt;guc-&gt;resume_time != RESUME_PENDING ||</div><div class='add'>+			   guc_read_stopped(guc));</div><div class='add'>+</div><div class='add'>+		if (!guc_read_stopped(guc)) {</div><div class='add'>+			MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);</div><div class='add'>+			s64 since_resume_ms =</div><div class='add'>+				ktime_ms_delta(ktime_get(),</div><div class='add'>+					       q-&gt;guc-&gt;resume_time);</div><div class='add'>+			s64 wait_ms = q-&gt;vm-&gt;preempt.min_run_period_ms -</div><div class='add'>+				since_resume_ms;</div><div class='add'>+</div><div class='add'>+			if (wait_ms &gt; 0 &amp;&amp; q-&gt;guc-&gt;resume_time)</div><div class='add'>+				msleep(wait_ms);</div><div class='add'>+</div><div class='add'>+			set_exec_queue_suspended(q);</div><div class='add'>+			clear_exec_queue_enabled(q);</div><div class='add'>+			set_exec_queue_pending_disable(q);</div><div class='add'>+			trace_xe_exec_queue_scheduling_disable(q);</div><div class='add'>+</div><div class='add'>+			xe_guc_ct_send(&amp;guc-&gt;ct, action, ARRAY_SIZE(action),</div><div class='add'>+				       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);</div><div class='add'>+		}</div><div class='add'>+	} else if (q-&gt;guc-&gt;suspend_pending) {</div><div class='add'>+		set_exec_queue_suspended(q);</div><div class='add'>+		suspend_fence_signal(q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = msg-&gt;private_data;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+</div><div class='add'>+	if (guc_exec_queue_allowed_to_change_state(q)) {</div><div class='add'>+		MAKE_SCHED_CONTEXT_ACTION(q, ENABLE);</div><div class='add'>+</div><div class='add'>+		q-&gt;guc-&gt;resume_time = RESUME_PENDING;</div><div class='add'>+		clear_exec_queue_suspended(q);</div><div class='add'>+		set_exec_queue_pending_enable(q);</div><div class='add'>+		set_exec_queue_enabled(q);</div><div class='add'>+		trace_xe_exec_queue_scheduling_enable(q);</div><div class='add'>+</div><div class='add'>+		xe_guc_ct_send(&amp;guc-&gt;ct, action, ARRAY_SIZE(action),</div><div class='add'>+			       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);</div><div class='add'>+	} else {</div><div class='add'>+		clear_exec_queue_suspended(q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define CLEANUP		1	/* Non-zero values to catch uninitialized msg */</div><div class='add'>+#define SET_SCHED_PROPS	2</div><div class='add'>+#define SUSPEND		3</div><div class='add'>+#define RESUME		4</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)</div><div class='add'>+{</div><div class='add'>+	trace_xe_sched_msg_recv(msg);</div><div class='add'>+</div><div class='add'>+	switch (msg-&gt;opcode) {</div><div class='add'>+	case CLEANUP:</div><div class='add'>+		__guc_exec_queue_process_msg_cleanup(msg);</div><div class='add'>+		break;</div><div class='add'>+	case SET_SCHED_PROPS:</div><div class='add'>+		__guc_exec_queue_process_msg_set_sched_props(msg);</div><div class='add'>+		break;</div><div class='add'>+	case SUSPEND:</div><div class='add'>+		__guc_exec_queue_process_msg_suspend(msg);</div><div class='add'>+		break;</div><div class='add'>+	case RESUME:</div><div class='add'>+		__guc_exec_queue_process_msg_resume(msg);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON("Unknown message type");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_sched_backend_ops drm_sched_ops = {</div><div class='add'>+	.run_job = guc_exec_queue_run_job,</div><div class='add'>+	.free_job = guc_exec_queue_free_job,</div><div class='add'>+	.timedout_job = guc_exec_queue_timedout_job,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_sched_backend_ops xe_sched_ops = {</div><div class='add'>+	.process_msg = guc_exec_queue_process_msg,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_init(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_gpu_scheduler *sched;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_guc_exec_queue *ge;</div><div class='add'>+	long timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, xe_device_uc_enabled(guc_to_xe(guc)));</div><div class='add'>+</div><div class='add'>+	ge = kzalloc(sizeof(*ge), GFP_KERNEL);</div><div class='add'>+	if (!ge)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	q-&gt;guc = ge;</div><div class='add'>+	ge-&gt;q = q;</div><div class='add'>+	init_waitqueue_head(&amp;ge-&gt;suspend_wait);</div><div class='add'>+</div><div class='add'>+	timeout = (q-&gt;vm &amp;&amp; xe_vm_in_lr_mode(q-&gt;vm)) ? MAX_SCHEDULE_TIMEOUT :</div><div class='add'>+		  q-&gt;hwe-&gt;eclass-&gt;sched_props.job_timeout_ms;</div><div class='add'>+	err = xe_sched_init(&amp;ge-&gt;sched, &amp;drm_sched_ops, &amp;xe_sched_ops,</div><div class='add'>+			    get_submit_wq(guc),</div><div class='add'>+			    q-&gt;lrc[0].ring.size / MAX_JOB_SIZE_BYTES, 64,</div><div class='add'>+			    timeout, guc_to_gt(guc)-&gt;ordered_wq, NULL,</div><div class='add'>+			    q-&gt;name, gt_to_xe(q-&gt;gt)-&gt;drm.dev);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_free;</div><div class='add'>+</div><div class='add'>+	sched = &amp;ge-&gt;sched;</div><div class='add'>+	err = xe_sched_entity_init(&amp;ge-&gt;entity, sched);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_sched;</div><div class='add'>+</div><div class='add'>+	if (xe_exec_queue_is_lr(q))</div><div class='add'>+		INIT_WORK(&amp;q-&gt;guc-&gt;lr_tdr, xe_guc_exec_queue_lr_cleanup);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	err = alloc_guc_id(guc, q);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_entity;</div><div class='add'>+</div><div class='add'>+	q-&gt;entity = &amp;ge-&gt;entity;</div><div class='add'>+</div><div class='add'>+	if (guc_read_stopped(guc))</div><div class='add'>+		xe_sched_stop(sched);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_assign_name(q, q-&gt;guc-&gt;id);</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_create(q);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_entity:</div><div class='add'>+	xe_sched_entity_fini(&amp;ge-&gt;entity);</div><div class='add'>+err_sched:</div><div class='add'>+	xe_sched_fini(&amp;ge-&gt;sched);</div><div class='add'>+err_free:</div><div class='add'>+	kfree(ge);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_kill(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	trace_xe_exec_queue_kill(q);</div><div class='add'>+	set_exec_queue_killed(q);</div><div class='add'>+	xe_guc_exec_queue_trigger_cleanup(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg,</div><div class='add'>+				   u32 opcode)</div><div class='add'>+{</div><div class='add'>+	INIT_LIST_HEAD(&amp;msg-&gt;link);</div><div class='add'>+	msg-&gt;opcode = opcode;</div><div class='add'>+	msg-&gt;private_data = q;</div><div class='add'>+</div><div class='add'>+	trace_xe_sched_msg_add(msg);</div><div class='add'>+	xe_sched_add_msg(&amp;q-&gt;guc-&gt;sched, msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define STATIC_MSG_CLEANUP	0</div><div class='add'>+#define STATIC_MSG_SUSPEND	1</div><div class='add'>+#define STATIC_MSG_RESUME	2</div><div class='add'>+static void guc_exec_queue_fini(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg = q-&gt;guc-&gt;static_msgs + STATIC_MSG_CLEANUP;</div><div class='add'>+</div><div class='add'>+	if (!(q-&gt;flags &amp; EXEC_QUEUE_FLAG_PERMANENT))</div><div class='add'>+		guc_exec_queue_add_msg(q, msg, CLEANUP);</div><div class='add'>+	else</div><div class='add'>+		__guc_exec_queue_fini(exec_queue_to_guc(q), q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_set_priority(struct xe_exec_queue *q,</div><div class='add'>+				       enum xe_exec_queue_priority priority)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;sched_props.priority == priority || exec_queue_killed_or_banned(q))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	msg = kmalloc(sizeof(*msg), GFP_KERNEL);</div><div class='add'>+	if (!msg)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	q-&gt;sched_props.priority = priority;</div><div class='add'>+	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;sched_props.timeslice_us == timeslice_us ||</div><div class='add'>+	    exec_queue_killed_or_banned(q))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	msg = kmalloc(sizeof(*msg), GFP_KERNEL);</div><div class='add'>+	if (!msg)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	q-&gt;sched_props.timeslice_us = timeslice_us;</div><div class='add'>+	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,</div><div class='add'>+					      u32 preempt_timeout_us)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;sched_props.preempt_timeout_us == preempt_timeout_us ||</div><div class='add'>+	    exec_queue_killed_or_banned(q))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	msg = kmalloc(sizeof(*msg), GFP_KERNEL);</div><div class='add'>+	if (!msg)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	q-&gt;sched_props.preempt_timeout_us = preempt_timeout_us;</div><div class='add'>+	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_set_job_timeout(struct xe_exec_queue *q, u32 job_timeout_ms)</div><div class='add'>+{</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !exec_queue_registered(q));</div><div class='add'>+	xe_assert(xe, !exec_queue_banned(q));</div><div class='add'>+	xe_assert(xe, !exec_queue_killed(q));</div><div class='add'>+</div><div class='add'>+	sched-&gt;base.timeout = job_timeout_ms;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int guc_exec_queue_suspend(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg = q-&gt;guc-&gt;static_msgs + STATIC_MSG_SUSPEND;</div><div class='add'>+</div><div class='add'>+	if (exec_queue_killed_or_banned(q) || q-&gt;guc-&gt;suspend_pending)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	q-&gt;guc-&gt;suspend_pending = true;</div><div class='add'>+	guc_exec_queue_add_msg(q, msg, SUSPEND);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+</div><div class='add'>+	wait_event(q-&gt;guc-&gt;suspend_wait, !q-&gt;guc-&gt;suspend_pending ||</div><div class='add'>+		   guc_read_stopped(guc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_resume(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_msg *msg = q-&gt;guc-&gt;static_msgs + STATIC_MSG_RESUME;</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !q-&gt;guc-&gt;suspend_pending);</div><div class='add'>+</div><div class='add'>+	guc_exec_queue_add_msg(q, msg, RESUME);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return exec_queue_reset(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * All of these functions are an abstraction layer which other parts of XE can</div><div class='add'>+ * use to trap into the GuC backend. All of these functions, aside from init,</div><div class='add'>+ * really shouldn't do much other than trap into the DRM scheduler which</div><div class='add'>+ * synchronizes these operations.</div><div class='add'>+ */</div><div class='add'>+static const struct xe_exec_queue_ops guc_exec_queue_ops = {</div><div class='add'>+	.init = guc_exec_queue_init,</div><div class='add'>+	.kill = guc_exec_queue_kill,</div><div class='add'>+	.fini = guc_exec_queue_fini,</div><div class='add'>+	.set_priority = guc_exec_queue_set_priority,</div><div class='add'>+	.set_timeslice = guc_exec_queue_set_timeslice,</div><div class='add'>+	.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,</div><div class='add'>+	.set_job_timeout = guc_exec_queue_set_job_timeout,</div><div class='add'>+	.suspend = guc_exec_queue_suspend,</div><div class='add'>+	.suspend_wait = guc_exec_queue_suspend_wait,</div><div class='add'>+	.resume = guc_exec_queue_resume,</div><div class='add'>+	.reset_status = guc_exec_queue_reset_status,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+</div><div class='add'>+	/* Stop scheduling + flush any DRM scheduler operations */</div><div class='add'>+	xe_sched_submission_stop(sched);</div><div class='add'>+</div><div class='add'>+	/* Clean up lost G2H + reset engine state */</div><div class='add'>+	if (exec_queue_registered(q)) {</div><div class='add'>+		if ((exec_queue_banned(q) &amp;&amp; exec_queue_destroyed(q)) ||</div><div class='add'>+		    xe_exec_queue_is_lr(q))</div><div class='add'>+			xe_exec_queue_put(q);</div><div class='add'>+		else if (exec_queue_destroyed(q))</div><div class='add'>+			__guc_exec_queue_fini(guc, q);</div><div class='add'>+	}</div><div class='add'>+	if (q-&gt;guc-&gt;suspend_pending) {</div><div class='add'>+		set_exec_queue_suspended(q);</div><div class='add'>+		suspend_fence_signal(q);</div><div class='add'>+	}</div><div class='add'>+	atomic_and(EXEC_QUEUE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED,</div><div class='add'>+		   &amp;q-&gt;guc-&gt;state);</div><div class='add'>+	q-&gt;guc-&gt;resume_time = 0;</div><div class='add'>+	trace_xe_exec_queue_stop(q);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Ban any engine (aside from kernel and engines used for VM ops) with a</div><div class='add'>+	 * started but not complete job or if a job has gone through a GT reset</div><div class='add'>+	 * more than twice.</div><div class='add'>+	 */</div><div class='add'>+	if (!(q-&gt;flags &amp; (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) {</div><div class='add'>+		struct xe_sched_job *job = xe_sched_first_pending_job(sched);</div><div class='add'>+</div><div class='add'>+		if (job) {</div><div class='add'>+			if ((xe_sched_job_started(job) &amp;&amp;</div><div class='add'>+			    !xe_sched_job_completed(job)) ||</div><div class='add'>+			    xe_sched_invalidate_job(job, 2)) {</div><div class='add'>+				trace_xe_sched_job_ban(job);</div><div class='add'>+				xe_sched_tdr_queue_imm(&amp;q-&gt;guc-&gt;sched);</div><div class='add'>+				set_exec_queue_banned(q);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_reset_prepare(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Using an atomic here rather than submission_state.lock as this</div><div class='add'>+	 * function can be called while holding the CT lock (engine reset</div><div class='add'>+	 * failure). submission_state.lock needs the CT lock to resubmit jobs.</div><div class='add'>+	 * Atomic is not ideal, but it works to prevent against concurrent reset</div><div class='add'>+	 * and releasing any TDRs waiting on guc-&gt;submission_state.stopped.</div><div class='add'>+	 */</div><div class='add'>+	ret = atomic_fetch_or(1, &amp;guc-&gt;submission_state.stopped);</div><div class='add'>+	smp_wmb();</div><div class='add'>+	wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_guc_submit_reset_wait(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	wait_event(guc-&gt;ct.wq, !guc_read_stopped(guc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_stop(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	unsigned long index;</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, guc_read_stopped(guc) == 1);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;guc-&gt;submission_state.exec_queue_lookup, index, q)</div><div class='add'>+		guc_exec_queue_stop(guc, q);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * No one can enter the backend at this point, aside from new engine</div><div class='add'>+	 * creation which is protected by guc-&gt;submission_state.lock.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_start(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+</div><div class='add'>+	if (!exec_queue_killed_or_banned(q)) {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		trace_xe_exec_queue_resubmit(q);</div><div class='add'>+		for (i = 0; i &lt; q-&gt;width; ++i)</div><div class='add'>+			xe_lrc_set_ring_head(q-&gt;lrc + i, q-&gt;lrc[i].ring.tail);</div><div class='add'>+		xe_sched_resubmit_jobs(sched);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_sched_submission_start(sched);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_start(struct xe_guc *guc)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	unsigned long index;</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, guc_read_stopped(guc) == 1);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+	atomic_dec(&amp;guc-&gt;submission_state.stopped);</div><div class='add'>+	xa_for_each(&amp;guc-&gt;submission_state.exec_queue_lookup, index, q)</div><div class='add'>+		guc_exec_queue_start(q);</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+</div><div class='add'>+	wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_exec_queue *</div><div class='add'>+g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	if (unlikely(guc_id &gt;= GUC_ID_MAX)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid guc_id %u", guc_id);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q = xa_load(&amp;guc-&gt;submission_state.exec_queue_lookup, guc_id);</div><div class='add'>+	if (unlikely(!q)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Not engine present for guc_id %u", guc_id);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, guc_id &gt;= q-&gt;guc-&gt;id);</div><div class='add'>+	xe_assert(xe, guc_id &lt; (q-&gt;guc-&gt;id + q-&gt;width));</div><div class='add'>+</div><div class='add'>+	return q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	u32 action[] = {</div><div class='add'>+		XE_GUC_ACTION_DEREGISTER_CONTEXT,</div><div class='add'>+		q-&gt;guc-&gt;id,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_deregister(q);</div><div class='add'>+</div><div class='add'>+	xe_guc_ct_send_g2h_handler(&amp;guc-&gt;ct, action, ARRAY_SIZE(action));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	u32 guc_id = msg[0];</div><div class='add'>+</div><div class='add'>+	if (unlikely(len &lt; 2)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid length %u", len);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q = g2h_exec_queue_lookup(guc, guc_id);</div><div class='add'>+	if (unlikely(!q))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!exec_queue_pending_enable(q) &amp;&amp;</div><div class='add'>+		     !exec_queue_pending_disable(q))) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Unexpected engine state 0x%04x",</div><div class='add'>+			atomic_read(&amp;q-&gt;guc-&gt;state));</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_scheduling_done(q);</div><div class='add'>+</div><div class='add'>+	if (exec_queue_pending_enable(q)) {</div><div class='add'>+		q-&gt;guc-&gt;resume_time = ktime_get();</div><div class='add'>+		clear_exec_queue_pending_enable(q);</div><div class='add'>+		smp_wmb();</div><div class='add'>+		wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+	} else {</div><div class='add'>+		clear_exec_queue_pending_disable(q);</div><div class='add'>+		if (q-&gt;guc-&gt;suspend_pending) {</div><div class='add'>+			suspend_fence_signal(q);</div><div class='add'>+		} else {</div><div class='add'>+			if (exec_queue_banned(q)) {</div><div class='add'>+				smp_wmb();</div><div class='add'>+				wake_up_all(&amp;guc-&gt;ct.wq);</div><div class='add'>+			}</div><div class='add'>+			deregister_exec_queue(guc, q);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	u32 guc_id = msg[0];</div><div class='add'>+</div><div class='add'>+	if (unlikely(len &lt; 1)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid length %u", len);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q = g2h_exec_queue_lookup(guc, guc_id);</div><div class='add'>+	if (unlikely(!q))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) ||</div><div class='add'>+	    exec_queue_pending_enable(q) || exec_queue_enabled(q)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Unexpected engine state 0x%04x",</div><div class='add'>+			atomic_read(&amp;q-&gt;guc-&gt;state));</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_deregister_done(q);</div><div class='add'>+</div><div class='add'>+	clear_exec_queue_registered(q);</div><div class='add'>+</div><div class='add'>+	if (exec_queue_banned(q) || xe_exec_queue_is_lr(q))</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+	else</div><div class='add'>+		__guc_exec_queue_fini(guc, q);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	u32 guc_id = msg[0];</div><div class='add'>+</div><div class='add'>+	if (unlikely(len &lt; 1)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid length %u", len);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q = g2h_exec_queue_lookup(guc, guc_id);</div><div class='add'>+	if (unlikely(!q))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Engine reset: guc_id=%d", guc_id);</div><div class='add'>+</div><div class='add'>+	/* FIXME: Do error capture, most likely async */</div><div class='add'>+</div><div class='add'>+	trace_xe_exec_queue_reset(q);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * A banned engine is a NOP at this point (came from</div><div class='add'>+	 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel</div><div class='add'>+	 * jobs by setting timeout of the job to the minimum value kicking</div><div class='add'>+	 * guc_exec_queue_timedout_job.</div><div class='add'>+	 */</div><div class='add'>+	set_exec_queue_reset(q);</div><div class='add'>+	if (!exec_queue_banned(q))</div><div class='add'>+		xe_guc_exec_queue_trigger_cleanup(q);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,</div><div class='add'>+					       u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	u32 guc_id = msg[0];</div><div class='add'>+</div><div class='add'>+	if (unlikely(len &lt; 1)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid length %u", len);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	q = g2h_exec_queue_lookup(guc, guc_id);</div><div class='add'>+	if (unlikely(!q))</div><div class='add'>+		return -EPROTO;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Engine memory cat error: guc_id=%d", guc_id);</div><div class='add'>+	trace_xe_exec_queue_memory_cat_error(q);</div><div class='add'>+</div><div class='add'>+	/* Treat the same as engine reset */</div><div class='add'>+	set_exec_queue_reset(q);</div><div class='add'>+	if (!exec_queue_banned(q))</div><div class='add'>+		xe_guc_exec_queue_trigger_cleanup(q);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	u8 guc_class, instance;</div><div class='add'>+	u32 reason;</div><div class='add'>+</div><div class='add'>+	if (unlikely(len != 3)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Invalid length %u", len);</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	guc_class = msg[0];</div><div class='add'>+	instance = msg[1];</div><div class='add'>+	reason = msg[2];</div><div class='add'>+</div><div class='add'>+	/* Unexpected failure of a hardware feature, log an actual error */</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "GuC engine reset request failed on %d:%d because 0x%08X",</div><div class='add'>+		guc_class, instance, reason);</div><div class='add'>+</div><div class='add'>+	xe_gt_reset_async(guc_to_gt(guc));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q,</div><div class='add'>+				   struct xe_guc_submit_exec_queue_snapshot *snapshot)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct iosys_map map = xe_lrc_parallel_map(q-&gt;lrc);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;guc.wqi_head = q-&gt;guc-&gt;wqi_head;</div><div class='add'>+	snapshot-&gt;guc.wqi_tail = q-&gt;guc-&gt;wqi_tail;</div><div class='add'>+	snapshot-&gt;parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head);</div><div class='add'>+	snapshot-&gt;parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail);</div><div class='add'>+	snapshot-&gt;parallel.wq_desc.status = parallel_read(xe, map,</div><div class='add'>+							  wq_desc.wq_status);</div><div class='add'>+</div><div class='add'>+	if (snapshot-&gt;parallel.wq_desc.head !=</div><div class='add'>+	    snapshot-&gt;parallel.wq_desc.tail) {</div><div class='add'>+		for (i = snapshot-&gt;parallel.wq_desc.head;</div><div class='add'>+		     i != snapshot-&gt;parallel.wq_desc.tail;</div><div class='add'>+		     i = (i + sizeof(u32)) % WQ_SIZE)</div><div class='add'>+			snapshot-&gt;parallel.wq[i / sizeof(u32)] =</div><div class='add'>+				parallel_read(xe, map, wq[i / sizeof(u32)]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,</div><div class='add'>+				 struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n",</div><div class='add'>+		   snapshot-&gt;guc.wqi_head, snapshot-&gt;parallel.wq_desc.head);</div><div class='add'>+	drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n",</div><div class='add'>+		   snapshot-&gt;guc.wqi_tail, snapshot-&gt;parallel.wq_desc.tail);</div><div class='add'>+	drm_printf(p, "\tWQ status: %u\n", snapshot-&gt;parallel.wq_desc.status);</div><div class='add'>+</div><div class='add'>+	if (snapshot-&gt;parallel.wq_desc.head !=</div><div class='add'>+	    snapshot-&gt;parallel.wq_desc.tail) {</div><div class='add'>+		for (i = snapshot-&gt;parallel.wq_desc.head;</div><div class='add'>+		     i != snapshot-&gt;parallel.wq_desc.tail;</div><div class='add'>+		     i = (i + sizeof(u32)) % WQ_SIZE)</div><div class='add'>+			drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32),</div><div class='add'>+				   snapshot-&gt;parallel.wq[i / sizeof(u32)]);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine.</div><div class='add'>+ * @q: Xe exec queue.</div><div class='add'>+ *</div><div class='add'>+ * This can be printed out in a later stage like during dev_coredump</div><div class='add'>+ * analysis.</div><div class='add'>+ *</div><div class='add'>+ * Returns: a GuC Submit Engine snapshot object that must be freed by the</div><div class='add'>+ * caller, using `xe_guc_exec_queue_snapshot_free`.</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_submit_exec_queue_snapshot *</div><div class='add'>+xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc *guc = exec_queue_to_guc(q);</div><div class='add'>+	struct xe_device *xe = guc_to_xe(guc);</div><div class='add'>+	struct xe_gpu_scheduler *sched = &amp;q-&gt;guc-&gt;sched;</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct xe_guc_submit_exec_queue_snapshot *snapshot;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);</div><div class='add'>+</div><div class='add'>+	if (!snapshot) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Skipping GuC Engine snapshot entirely.\n");</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;guc.id = q-&gt;guc-&gt;id;</div><div class='add'>+	memcpy(&amp;snapshot-&gt;name, &amp;q-&gt;name, sizeof(snapshot-&gt;name));</div><div class='add'>+	snapshot-&gt;class = q-&gt;class;</div><div class='add'>+	snapshot-&gt;logical_mask = q-&gt;logical_mask;</div><div class='add'>+	snapshot-&gt;width = q-&gt;width;</div><div class='add'>+	snapshot-&gt;refcount = kref_read(&amp;q-&gt;refcount);</div><div class='add'>+	snapshot-&gt;sched_timeout = sched-&gt;base.timeout;</div><div class='add'>+	snapshot-&gt;sched_props.timeslice_us = q-&gt;sched_props.timeslice_us;</div><div class='add'>+	snapshot-&gt;sched_props.preempt_timeout_us =</div><div class='add'>+		q-&gt;sched_props.preempt_timeout_us;</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;lrc = kmalloc_array(q-&gt;width, sizeof(struct lrc_snapshot),</div><div class='add'>+				      GFP_ATOMIC);</div><div class='add'>+</div><div class='add'>+	if (!snapshot-&gt;lrc) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Skipping GuC Engine LRC snapshot.\n");</div><div class='add'>+	} else {</div><div class='add'>+		for (i = 0; i &lt; q-&gt;width; ++i) {</div><div class='add'>+			struct xe_lrc *lrc = q-&gt;lrc + i;</div><div class='add'>+</div><div class='add'>+			snapshot-&gt;lrc[i].context_desc =</div><div class='add'>+				lower_32_bits(xe_lrc_ggtt_addr(lrc));</div><div class='add'>+			snapshot-&gt;lrc[i].head = xe_lrc_ring_head(lrc);</div><div class='add'>+			snapshot-&gt;lrc[i].tail.internal = lrc-&gt;ring.tail;</div><div class='add'>+			snapshot-&gt;lrc[i].tail.memory =</div><div class='add'>+				xe_lrc_read_ctx_reg(lrc, CTX_RING_TAIL);</div><div class='add'>+			snapshot-&gt;lrc[i].start_seqno = xe_lrc_start_seqno(lrc);</div><div class='add'>+			snapshot-&gt;lrc[i].seqno = xe_lrc_seqno(lrc);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;schedule_state = atomic_read(&amp;q-&gt;guc-&gt;state);</div><div class='add'>+	snapshot-&gt;exec_queue_flags = q-&gt;flags;</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;parallel_execution = xe_exec_queue_is_parallel(q);</div><div class='add'>+	if (snapshot-&gt;parallel_execution)</div><div class='add'>+		guc_exec_queue_wq_snapshot_capture(q, snapshot);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+	snapshot-&gt;pending_list_size = list_count_nodes(&amp;sched-&gt;base.pending_list);</div><div class='add'>+	snapshot-&gt;pending_list = kmalloc_array(snapshot-&gt;pending_list_size,</div><div class='add'>+					       sizeof(struct pending_list_snapshot),</div><div class='add'>+					       GFP_ATOMIC);</div><div class='add'>+</div><div class='add'>+	if (!snapshot-&gt;pending_list) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Skipping GuC Engine pending_list snapshot.\n");</div><div class='add'>+	} else {</div><div class='add'>+		i = 0;</div><div class='add'>+		list_for_each_entry(job, &amp;sched-&gt;base.pending_list, drm.list) {</div><div class='add'>+			snapshot-&gt;pending_list[i].seqno =</div><div class='add'>+				xe_sched_job_seqno(job);</div><div class='add'>+			snapshot-&gt;pending_list[i].fence =</div><div class='add'>+				dma_fence_is_signaled(job-&gt;fence) ? 1 : 0;</div><div class='add'>+			snapshot-&gt;pending_list[i].finished =</div><div class='add'>+				dma_fence_is_signaled(&amp;job-&gt;drm.s_fence-&gt;finished)</div><div class='add'>+				? 1 : 0;</div><div class='add'>+			i++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;sched-&gt;base.job_list_lock);</div><div class='add'>+</div><div class='add'>+	return snapshot;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot.</div><div class='add'>+ * @snapshot: GuC Submit Engine snapshot object.</div><div class='add'>+ * @p: drm_printer where it will be printed out.</div><div class='add'>+ *</div><div class='add'>+ * This function prints out a given GuC Submit Engine snapshot object.</div><div class='add'>+ */</div><div class='add'>+void</div><div class='add'>+xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,</div><div class='add'>+				 struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nGuC ID: %d\n", snapshot-&gt;guc.id);</div><div class='add'>+	drm_printf(p, "\tName: %s\n", snapshot-&gt;name);</div><div class='add'>+	drm_printf(p, "\tClass: %d\n", snapshot-&gt;class);</div><div class='add'>+	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot-&gt;logical_mask);</div><div class='add'>+	drm_printf(p, "\tWidth: %d\n", snapshot-&gt;width);</div><div class='add'>+	drm_printf(p, "\tRef: %d\n", snapshot-&gt;refcount);</div><div class='add'>+	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot-&gt;sched_timeout);</div><div class='add'>+	drm_printf(p, "\tTimeslice: %u (us)\n",</div><div class='add'>+		   snapshot-&gt;sched_props.timeslice_us);</div><div class='add'>+	drm_printf(p, "\tPreempt timeout: %u (us)\n",</div><div class='add'>+		   snapshot-&gt;sched_props.preempt_timeout_us);</div><div class='add'>+</div><div class='add'>+	for (i = 0; snapshot-&gt;lrc &amp;&amp; i &lt; snapshot-&gt;width; ++i) {</div><div class='add'>+		drm_printf(p, "\tHW Context Desc: 0x%08x\n",</div><div class='add'>+			   snapshot-&gt;lrc[i].context_desc);</div><div class='add'>+		drm_printf(p, "\tLRC Head: (memory) %u\n",</div><div class='add'>+			   snapshot-&gt;lrc[i].head);</div><div class='add'>+		drm_printf(p, "\tLRC Tail: (internal) %u, (memory) %u\n",</div><div class='add'>+			   snapshot-&gt;lrc[i].tail.internal,</div><div class='add'>+			   snapshot-&gt;lrc[i].tail.memory);</div><div class='add'>+		drm_printf(p, "\tStart seqno: (memory) %d\n",</div><div class='add'>+			   snapshot-&gt;lrc[i].start_seqno);</div><div class='add'>+		drm_printf(p, "\tSeqno: (memory) %d\n", snapshot-&gt;lrc[i].seqno);</div><div class='add'>+	}</div><div class='add'>+	drm_printf(p, "\tSchedule State: 0x%x\n", snapshot-&gt;schedule_state);</div><div class='add'>+	drm_printf(p, "\tFlags: 0x%lx\n", snapshot-&gt;exec_queue_flags);</div><div class='add'>+</div><div class='add'>+	if (snapshot-&gt;parallel_execution)</div><div class='add'>+		guc_exec_queue_wq_snapshot_print(snapshot, p);</div><div class='add'>+</div><div class='add'>+	for (i = 0; snapshot-&gt;pending_list &amp;&amp; i &lt; snapshot-&gt;pending_list_size;</div><div class='add'>+	     i++)</div><div class='add'>+		drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",</div><div class='add'>+			   snapshot-&gt;pending_list[i].seqno,</div><div class='add'>+			   snapshot-&gt;pending_list[i].fence,</div><div class='add'>+			   snapshot-&gt;pending_list[i].finished);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given</div><div class='add'>+ * snapshot.</div><div class='add'>+ * @snapshot: GuC Submit Engine snapshot object.</div><div class='add'>+ *</div><div class='add'>+ * This function free all the memory that needed to be allocated at capture</div><div class='add'>+ * time.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot)</div><div class='add'>+{</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kfree(snapshot-&gt;lrc);</div><div class='add'>+	kfree(snapshot-&gt;pending_list);</div><div class='add'>+	kfree(snapshot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_guc_submit_exec_queue_snapshot *snapshot;</div><div class='add'>+</div><div class='add'>+	snapshot = xe_guc_exec_queue_snapshot_capture(q);</div><div class='add'>+	xe_guc_exec_queue_snapshot_print(snapshot, p);</div><div class='add'>+	xe_guc_exec_queue_snapshot_free(snapshot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_guc_submit_print - GuC Submit Print.</div><div class='add'>+ * @guc: GuC.</div><div class='add'>+ * @p: drm_printer where it will be printed out.</div><div class='add'>+ *</div><div class='add'>+ * This function capture and prints snapshots of **all** GuC Engines.</div><div class='add'>+ */</div><div class='add'>+void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	unsigned long index;</div><div class='add'>+</div><div class='add'>+	if (!xe_device_uc_enabled(guc_to_xe(guc)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+	xa_for_each(&amp;guc-&gt;submission_state.exec_queue_lookup, index, q)</div><div class='add'>+		guc_exec_queue_print(q, p);</div><div class='add'>+	mutex_unlock(&amp;guc-&gt;submission_state.lock);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h<br/>new file mode 100644<br/>index 000000000000..fc97869c5b86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_submit.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit.h</a></div><div class='hunk'>@@ -0,0 +1,38 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_SUBMIT_H_</div><div class='add'>+#define _XE_GUC_SUBMIT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_guc;</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_init(struct xe_guc *guc);</div><div class='add'>+</div><div class='add'>+int xe_guc_submit_reset_prepare(struct xe_guc *guc);</div><div class='add'>+void xe_guc_submit_reset_wait(struct xe_guc *guc);</div><div class='add'>+int xe_guc_submit_stop(struct xe_guc *guc);</div><div class='add'>+int xe_guc_submit_start(struct xe_guc *guc);</div><div class='add'>+</div><div class='add'>+int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,</div><div class='add'>+					       u32 len);</div><div class='add'>+int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len);</div><div class='add'>+</div><div class='add'>+struct xe_guc_submit_exec_queue_snapshot *</div><div class='add'>+xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q);</div><div class='add'>+void</div><div class='add'>+xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,</div><div class='add'>+				 struct drm_printer *p);</div><div class='add'>+void</div><div class='add'>+xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot);</div><div class='add'>+void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h<br/>new file mode 100644<br/>index 000000000000..649b0a852692<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_submit_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_submit_types.h</a></div><div class='hunk'>@@ -0,0 +1,155 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_SUBMIT_TYPES_H_</div><div class='add'>+#define _XE_GUC_SUBMIT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+</div><div class='add'>+/* Work item for submitting workloads into work queue of GuC. */</div><div class='add'>+#define WQ_STATUS_ACTIVE		1</div><div class='add'>+#define WQ_STATUS_SUSPENDED		2</div><div class='add'>+#define WQ_STATUS_CMD_ERROR		3</div><div class='add'>+#define WQ_STATUS_ENGINE_ID_NOT_USED	4</div><div class='add'>+#define WQ_STATUS_SUSPENDED_FROM_RESET	5</div><div class='add'>+#define WQ_TYPE_NOOP			0x4</div><div class='add'>+#define WQ_TYPE_MULTI_LRC		0x5</div><div class='add'>+#define WQ_TYPE_MASK			GENMASK(7, 0)</div><div class='add'>+#define WQ_LEN_MASK			GENMASK(26, 16)</div><div class='add'>+</div><div class='add'>+#define WQ_GUC_ID_MASK			GENMASK(15, 0)</div><div class='add'>+#define WQ_RING_TAIL_MASK		GENMASK(28, 18)</div><div class='add'>+</div><div class='add'>+#define PARALLEL_SCRATCH_SIZE	2048</div><div class='add'>+#define WQ_SIZE			(PARALLEL_SCRATCH_SIZE / 2)</div><div class='add'>+#define WQ_OFFSET		(PARALLEL_SCRATCH_SIZE - WQ_SIZE)</div><div class='add'>+#define CACHELINE_BYTES		64</div><div class='add'>+</div><div class='add'>+struct guc_sched_wq_desc {</div><div class='add'>+	u32 head;</div><div class='add'>+	u32 tail;</div><div class='add'>+	u32 error_offset;</div><div class='add'>+	u32 wq_status;</div><div class='add'>+	u32 reserved[28];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct sync_semaphore {</div><div class='add'>+	u32 semaphore;</div><div class='add'>+	u8 unused[CACHELINE_BYTES - sizeof(u32)];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct guc_submit_parallel_scratch - A scratch shared mapped buffer.</div><div class='add'>+ */</div><div class='add'>+struct guc_submit_parallel_scratch {</div><div class='add'>+	/** @wq_desc: Guc scheduler workqueue descriptor */</div><div class='add'>+	struct guc_sched_wq_desc wq_desc;</div><div class='add'>+</div><div class='add'>+	/** @go: Go Semaphore */</div><div class='add'>+	struct sync_semaphore go;</div><div class='add'>+	/** @join: Joined semaphore for the relevant hw engine instances */</div><div class='add'>+	struct sync_semaphore join[XE_HW_ENGINE_MAX_INSTANCE];</div><div class='add'>+</div><div class='add'>+	/** @unused: Unused/Reserved memory space */</div><div class='add'>+	u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -</div><div class='add'>+		  sizeof(struct sync_semaphore) *</div><div class='add'>+		  (XE_HW_ENGINE_MAX_INSTANCE + 1)];</div><div class='add'>+</div><div class='add'>+	/** @wq: Workqueue info */</div><div class='add'>+	u32 wq[WQ_SIZE / sizeof(u32)];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct lrc_snapshot {</div><div class='add'>+	u32 context_desc;</div><div class='add'>+	u32 head;</div><div class='add'>+	struct {</div><div class='add'>+		u32 internal;</div><div class='add'>+		u32 memory;</div><div class='add'>+	} tail;</div><div class='add'>+	u32 start_seqno;</div><div class='add'>+	u32 seqno;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct pending_list_snapshot {</div><div class='add'>+	u32 seqno;</div><div class='add'>+	bool fence;</div><div class='add'>+	bool finished;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc_submit_exec_queue_snapshot - Snapshot for devcoredump</div><div class='add'>+ */</div><div class='add'>+struct xe_guc_submit_exec_queue_snapshot {</div><div class='add'>+	/** @name: name of this exec queue */</div><div class='add'>+	char name[MAX_FENCE_NAME_LEN];</div><div class='add'>+	/** @class: class of this exec queue */</div><div class='add'>+	enum xe_engine_class class;</div><div class='add'>+	/**</div><div class='add'>+	 * @logical_mask: logical mask of where job submitted to exec queue can run</div><div class='add'>+	 */</div><div class='add'>+	u32 logical_mask;</div><div class='add'>+	/** @width: width (number BB submitted per exec) of this exec queue */</div><div class='add'>+	u16 width;</div><div class='add'>+	/** @refcount: ref count of this exec queue */</div><div class='add'>+	u32 refcount;</div><div class='add'>+	/**</div><div class='add'>+	 * @sched_timeout: the time after which a job is removed from the</div><div class='add'>+	 * scheduler.</div><div class='add'>+	 */</div><div class='add'>+	long sched_timeout;</div><div class='add'>+</div><div class='add'>+	/** @sched_props: scheduling properties */</div><div class='add'>+	struct {</div><div class='add'>+		/** @timeslice_us: timeslice period in micro-seconds */</div><div class='add'>+		u32 timeslice_us;</div><div class='add'>+		/** @preempt_timeout_us: preemption timeout in micro-seconds */</div><div class='add'>+		u32 preempt_timeout_us;</div><div class='add'>+	} sched_props;</div><div class='add'>+</div><div class='add'>+	/** @lrc: LRC Snapshot */</div><div class='add'>+	struct lrc_snapshot *lrc;</div><div class='add'>+</div><div class='add'>+	/** @schedule_state: Schedule State at the moment of Crash */</div><div class='add'>+	u32 schedule_state;</div><div class='add'>+	/** @exec_queue_flags: Flags of the faulty exec_queue */</div><div class='add'>+	unsigned long exec_queue_flags;</div><div class='add'>+</div><div class='add'>+	/** @guc: GuC Engine Snapshot */</div><div class='add'>+	struct {</div><div class='add'>+		/** @wqi_head: work queue item head */</div><div class='add'>+		u32 wqi_head;</div><div class='add'>+		/** @wqi_tail: work queue item tail */</div><div class='add'>+		u32 wqi_tail;</div><div class='add'>+		/** @id: GuC id for this exec_queue */</div><div class='add'>+		u16 id;</div><div class='add'>+	} guc;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @parallel_execution: Indication if the failure was during parallel</div><div class='add'>+	 * execution</div><div class='add'>+	 */</div><div class='add'>+	bool parallel_execution;</div><div class='add'>+	/** @parallel: snapshot of the useful parallel scratch */</div><div class='add'>+	struct {</div><div class='add'>+		/** @wq_desc: Workqueue description */</div><div class='add'>+		struct {</div><div class='add'>+			/** @head: Workqueue Head */</div><div class='add'>+			u32 head;</div><div class='add'>+			/** @tail: Workqueue Tail */</div><div class='add'>+			u32 tail;</div><div class='add'>+			/** @status: Workqueue Status */</div><div class='add'>+			u32 status;</div><div class='add'>+		} wq_desc;</div><div class='add'>+		/** @wq: Workqueue Items */</div><div class='add'>+		u32 wq[WQ_SIZE / sizeof(u32)];</div><div class='add'>+	} parallel;</div><div class='add'>+</div><div class='add'>+	/** @pending_list_size: Size of the pending list snapshot array */</div><div class='add'>+	int pending_list_size;</div><div class='add'>+	/** @pending_list: snapshot of the pending list info */</div><div class='add'>+	struct pending_list_snapshot *pending_list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h<br/>new file mode 100644<br/>index 000000000000..cd80802e8918<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_guc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_guc_types.h</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_GUC_TYPES_H_</div><div class='add'>+#define _XE_GUC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/idr.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+#include "xe_guc_ads_types.h"</div><div class='add'>+#include "xe_guc_ct_types.h"</div><div class='add'>+#include "xe_guc_fwif.h"</div><div class='add'>+#include "xe_guc_log_types.h"</div><div class='add'>+#include "xe_guc_pc_types.h"</div><div class='add'>+#include "xe_uc_fw_types.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_guc - Graphic micro controller</div><div class='add'>+ */</div><div class='add'>+struct xe_guc {</div><div class='add'>+	/** @fw: Generic uC firmware management */</div><div class='add'>+	struct xe_uc_fw fw;</div><div class='add'>+	/** @log: GuC log */</div><div class='add'>+	struct xe_guc_log log;</div><div class='add'>+	/** @ads: GuC ads */</div><div class='add'>+	struct xe_guc_ads ads;</div><div class='add'>+	/** @ct: GuC ct */</div><div class='add'>+	struct xe_guc_ct ct;</div><div class='add'>+	/** @pc: GuC Power Conservation */</div><div class='add'>+	struct xe_guc_pc pc;</div><div class='add'>+	/** @submission_state: GuC submission state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @exec_queue_lookup: Lookup an xe_engine from guc_id */</div><div class='add'>+		struct xarray exec_queue_lookup;</div><div class='add'>+		/** @guc_ids: used to allocate new guc_ids, single-lrc */</div><div class='add'>+		struct ida guc_ids;</div><div class='add'>+		/** @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc */</div><div class='add'>+		unsigned long *guc_ids_bitmap;</div><div class='add'>+		/** @stopped: submissions are stopped */</div><div class='add'>+		atomic_t stopped;</div><div class='add'>+		/** @lock: protects submission state */</div><div class='add'>+		struct mutex lock;</div><div class='add'>+		/** @suspend: suspend fence state */</div><div class='add'>+		struct {</div><div class='add'>+			/** @lock: suspend fences lock */</div><div class='add'>+			spinlock_t lock;</div><div class='add'>+			/** @context: suspend fences context */</div><div class='add'>+			u64 context;</div><div class='add'>+			/** @seqno: suspend fences seqno */</div><div class='add'>+			u32 seqno;</div><div class='add'>+		} suspend;</div><div class='add'>+#ifdef CONFIG_PROVE_LOCKING</div><div class='add'>+#define NUM_SUBMIT_WQ	256</div><div class='add'>+		/** @submit_wq_pool: submission ordered workqueues pool */</div><div class='add'>+		struct workqueue_struct *submit_wq_pool[NUM_SUBMIT_WQ];</div><div class='add'>+		/** @submit_wq_idx: submission ordered workqueue index */</div><div class='add'>+		int submit_wq_idx;</div><div class='add'>+#endif</div><div class='add'>+		/** @enabled: submission is enabled */</div><div class='add'>+		bool enabled;</div><div class='add'>+	} submission_state;</div><div class='add'>+	/** @hwconfig: Hardware config state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @bo: buffer object of the hardware config */</div><div class='add'>+		struct xe_bo *bo;</div><div class='add'>+		/** @size: size of the hardware config */</div><div class='add'>+		u32 size;</div><div class='add'>+	} hwconfig;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @notify_reg: Register which is written to notify GuC of H2G messages</div><div class='add'>+	 */</div><div class='add'>+	struct xe_reg notify_reg;</div><div class='add'>+	/** @params: Control params for fw initialization */</div><div class='add'>+	u32 params[GUC_CTL_MAX_DWORDS];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c<br/>new file mode 100644<br/>index 000000000000..bfdd33b9b23b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_heci_gsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_heci_gsc.c</a></div><div class='hunk'>@@ -0,0 +1,234 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright(c) 2023, Intel Corporation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/irq.h&gt;</div><div class='add'>+#include &lt;linux/mei_aux.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_drv.h"</div><div class='add'>+#include "xe_heci_gsc.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+</div><div class='add'>+#define GSC_BAR_LENGTH  0x00000FFC</div><div class='add'>+</div><div class='add'>+#define DG1_GSC_HECI2_BASE			0x259000</div><div class='add'>+#define PVC_GSC_HECI2_BASE			0x285000</div><div class='add'>+#define DG2_GSC_HECI2_BASE			0x374000</div><div class='add'>+</div><div class='add'>+static void heci_gsc_irq_mask(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	/* generic irq handling */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void heci_gsc_irq_unmask(struct irq_data *d)</div><div class='add'>+{</div><div class='add'>+	/* generic irq handling */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct irq_chip heci_gsc_irq_chip = {</div><div class='add'>+	.name = "gsc_irq_chip",</div><div class='add'>+	.irq_mask = heci_gsc_irq_mask,</div><div class='add'>+	.irq_unmask = heci_gsc_irq_unmask,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int heci_gsc_irq_init(int irq)</div><div class='add'>+{</div><div class='add'>+	irq_set_chip_and_handler_name(irq, &amp;heci_gsc_irq_chip,</div><div class='add'>+				      handle_simple_irq, "heci_gsc_irq_handler");</div><div class='add'>+</div><div class='add'>+	return irq_set_chip_data(irq, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct heci_gsc_def - graphics security controller heci interface definitions</div><div class='add'>+ *</div><div class='add'>+ * @name: name of the heci device</div><div class='add'>+ * @bar: address of the mmio bar</div><div class='add'>+ * @bar_size: size of the mmio bar</div><div class='add'>+ * @use_polling: indication of using polling mode for the device</div><div class='add'>+ * @slow_firmware: indication of whether the device is slow (needs longer timeouts)</div><div class='add'>+ */</div><div class='add'>+struct heci_gsc_def {</div><div class='add'>+	const char *name;</div><div class='add'>+	unsigned long bar;</div><div class='add'>+	size_t bar_size;</div><div class='add'>+	bool use_polling;</div><div class='add'>+	bool slow_firmware;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* gsc resources and definitions */</div><div class='add'>+static const struct heci_gsc_def heci_gsc_def_dg1 = {</div><div class='add'>+	.name = "mei-gscfi",</div><div class='add'>+	.bar = DG1_GSC_HECI2_BASE,</div><div class='add'>+	.bar_size = GSC_BAR_LENGTH,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct heci_gsc_def heci_gsc_def_dg2 = {</div><div class='add'>+	.name = "mei-gscfi",</div><div class='add'>+	.bar = DG2_GSC_HECI2_BASE,</div><div class='add'>+	.bar_size = GSC_BAR_LENGTH,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct heci_gsc_def heci_gsc_def_pvc = {</div><div class='add'>+	.name = "mei-gscfi",</div><div class='add'>+	.bar = PVC_GSC_HECI2_BASE,</div><div class='add'>+	.bar_size = GSC_BAR_LENGTH,</div><div class='add'>+	.slow_firmware = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void heci_gsc_release_dev(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);</div><div class='add'>+	struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);</div><div class='add'>+</div><div class='add'>+	kfree(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_heci_gsc_fini(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_heci_gsc *heci_gsc = &amp;xe-&gt;heci_gsc;</div><div class='add'>+</div><div class='add'>+	if (!HAS_HECI_GSCFI(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (heci_gsc-&gt;adev) {</div><div class='add'>+		struct auxiliary_device *aux_dev = &amp;heci_gsc-&gt;adev-&gt;aux_dev;</div><div class='add'>+</div><div class='add'>+		auxiliary_device_delete(aux_dev);</div><div class='add'>+		auxiliary_device_uninit(aux_dev);</div><div class='add'>+		heci_gsc-&gt;adev = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (heci_gsc-&gt;irq &gt;= 0)</div><div class='add'>+		irq_free_desc(heci_gsc-&gt;irq);</div><div class='add'>+	heci_gsc-&gt;irq = -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int heci_gsc_irq_setup(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_heci_gsc *heci_gsc = &amp;xe-&gt;heci_gsc;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	heci_gsc-&gt;irq = irq_alloc_desc(0);</div><div class='add'>+	if (heci_gsc-&gt;irq &lt; 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "gsc irq error %d\n", heci_gsc-&gt;irq);</div><div class='add'>+		return heci_gsc-&gt;irq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = heci_gsc_irq_init(heci_gsc-&gt;irq);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "gsc irq init failed %d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int heci_gsc_add_device(struct xe_device *xe, const struct heci_gsc_def *def)</div><div class='add'>+{</div><div class='add'>+	struct xe_heci_gsc *heci_gsc = &amp;xe-&gt;heci_gsc;</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	struct auxiliary_device *aux_dev;</div><div class='add'>+	struct mei_aux_device *adev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	adev = kzalloc(sizeof(*adev), GFP_KERNEL);</div><div class='add'>+	if (!adev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	adev-&gt;irq = heci_gsc-&gt;irq;</div><div class='add'>+	adev-&gt;bar.parent = &amp;pdev-&gt;resource[0];</div><div class='add'>+	adev-&gt;bar.start = def-&gt;bar + pdev-&gt;resource[0].start;</div><div class='add'>+	adev-&gt;bar.end = adev-&gt;bar.start + def-&gt;bar_size - 1;</div><div class='add'>+	adev-&gt;bar.flags = IORESOURCE_MEM;</div><div class='add'>+	adev-&gt;bar.desc = IORES_DESC_NONE;</div><div class='add'>+	adev-&gt;slow_firmware = def-&gt;slow_firmware;</div><div class='add'>+</div><div class='add'>+	aux_dev = &amp;adev-&gt;aux_dev;</div><div class='add'>+	aux_dev-&gt;name = def-&gt;name;</div><div class='add'>+	aux_dev-&gt;id = (pci_domain_nr(pdev-&gt;bus) &lt;&lt; 16) |</div><div class='add'>+		      PCI_DEVID(pdev-&gt;bus-&gt;number, pdev-&gt;devfn);</div><div class='add'>+	aux_dev-&gt;dev.parent = &amp;pdev-&gt;dev;</div><div class='add'>+	aux_dev-&gt;dev.release = heci_gsc_release_dev;</div><div class='add'>+</div><div class='add'>+	ret = auxiliary_device_init(aux_dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "gsc aux init failed %d\n", ret);</div><div class='add'>+		kfree(adev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	heci_gsc-&gt;adev = adev; /* needed by the notifier */</div><div class='add'>+	ret = auxiliary_device_add(aux_dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "gsc aux add failed %d\n", ret);</div><div class='add'>+		heci_gsc-&gt;adev = NULL;</div><div class='add'>+</div><div class='add'>+		/* adev will be freed with the put_device() and .release sequence */</div><div class='add'>+		auxiliary_device_uninit(aux_dev);</div><div class='add'>+	}</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_heci_gsc_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_heci_gsc *heci_gsc = &amp;xe-&gt;heci_gsc;</div><div class='add'>+	const struct heci_gsc_def *def;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!HAS_HECI_GSCFI(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	heci_gsc-&gt;irq = -1;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.platform == XE_PVC) {</div><div class='add'>+		def = &amp;heci_gsc_def_pvc;</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_DG2) {</div><div class='add'>+		def = &amp;heci_gsc_def_dg2;</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_DG1) {</div><div class='add'>+		def = &amp;heci_gsc_def_dg1;</div><div class='add'>+	} else {</div><div class='add'>+		drm_warn_once(&amp;xe-&gt;drm, "Unknown platform\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!def-&gt;name) {</div><div class='add'>+		drm_warn_once(&amp;xe-&gt;drm, "HECI is not implemented!\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!def-&gt;use_polling) {</div><div class='add'>+		ret = heci_gsc_irq_setup(xe);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = heci_gsc_add_device(xe, def);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+fail:</div><div class='add'>+	xe_heci_gsc_fini(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if ((iir &amp; GSC_IRQ_INTF(1)) == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!HAS_HECI_GSCFI(xe)) {</div><div class='add'>+		drm_warn_once(&amp;xe-&gt;drm, "GSC irq: not supported");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;heci_gsc.irq &lt; 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ret = generic_handle_irq(xe-&gt;heci_gsc.irq);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err_ratelimited(&amp;xe-&gt;drm, "error handling GSC irq: %d\n", ret);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.h b/drivers/gpu/drm/xe/xe_heci_gsc.h<br/>new file mode 100644<br/>index 000000000000..9db454478fae<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_heci_gsc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_heci_gsc.h</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright(c) 2023, Intel Corporation. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+#ifndef __XE_HECI_GSC_DEV_H__</div><div class='add'>+#define __XE_HECI_GSC_DEV_H__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct mei_aux_device;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The HECI1 bit corresponds to bit15 and HECI2 to bit14.</div><div class='add'>+ * The reason for this is to allow growth for more interfaces in the future.</div><div class='add'>+ */</div><div class='add'>+#define GSC_IRQ_INTF(_x)  BIT(15 - (_x))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_heci_gsc - graphics security controller for xe, HECI interface</div><div class='add'>+ *</div><div class='add'>+ * @adev : pointer to mei auxiliary device structure</div><div class='add'>+ * @irq : irq number</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+struct xe_heci_gsc {</div><div class='add'>+	struct mei_aux_device *adev;</div><div class='add'>+	int irq;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_heci_gsc_init(struct xe_device *xe);</div><div class='add'>+void xe_heci_gsc_fini(struct xe_device *xe);</div><div class='add'>+void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir);</div><div class='add'>+</div><div class='add'>+#endif /* __XE_HECI_GSC_DEV_H__ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c<br/>new file mode 100644<br/>index 000000000000..eca109791c6a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_huc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc.c</a></div><div class='hunk'>@@ -0,0 +1,307 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_huc.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "abi/gsc_pxp_commands_abi.h"</div><div class='add'>+#include "regs/xe_gsc_regs.h"</div><div class='add'>+#include "regs/xe_guc_regs.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gsc_submit.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+huc_to_gt(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	return container_of(huc, struct xe_gt, uc.huc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+huc_to_xe(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(huc_to_gt(huc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_guc *</div><div class='add'>+huc_to_guc(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	return &amp;container_of(huc, struct xe_uc, huc)-&gt;guc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_gsc_pkt(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_huc *huc = arg;</div><div class='add'>+</div><div class='add'>+	xe_bo_unpin_map_no_vm(huc-&gt;gsc_pkt);</div><div class='add'>+	huc-&gt;gsc_pkt = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define PXP43_HUC_AUTH_INOUT_SIZE SZ_4K</div><div class='add'>+static int huc_alloc_gsc_pkt(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* we use a single object for both input and output */</div><div class='add'>+	bo = xe_bo_create_pin_map(xe, gt_to_tile(gt), NULL,</div><div class='add'>+				  PXP43_HUC_AUTH_INOUT_SIZE * 2,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_SYSTEM_BIT |</div><div class='add'>+				  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	huc-&gt;gsc_pkt = bo;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, free_gsc_pkt, huc);</div><div class='add'>+	if (err) {</div><div class='add'>+		free_gsc_pkt(&amp;xe-&gt;drm, huc);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_huc_init(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	huc-&gt;fw.type = XE_UC_FW_TYPE_HUC;</div><div class='add'>+</div><div class='add'>+	/* On platforms with a media GT the HuC is only available there */</div><div class='add'>+	if (tile-&gt;media_gt &amp;&amp; (gt != tile-&gt;media_gt)) {</div><div class='add'>+		xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_NOT_SUPPORTED);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = xe_uc_fw_init(&amp;huc-&gt;fw);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_enabled(&amp;huc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (huc-&gt;fw.has_gsc_headers) {</div><div class='add'>+		ret = huc_alloc_gsc_pkt(huc);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "HuC init failed with %d", ret);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_huc_upload(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	if (!xe_uc_fw_is_loadable(&amp;huc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+	return xe_uc_fw_upload(&amp;huc-&gt;fw, 0, HUC_UKERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define huc_auth_msg_wr(xe_, map_, offset_, field_, val_) \</div><div class='add'>+	xe_map_wr_field(xe_, map_, offset_, struct pxp43_new_huc_auth_in, field_, val_)</div><div class='add'>+#define huc_auth_msg_rd(xe_, map_, offset_, field_) \</div><div class='add'>+	xe_map_rd_field(xe_, map_, offset_, struct pxp43_huc_auth_out, field_)</div><div class='add'>+</div><div class='add'>+static u32 huc_emit_pxp_auth_msg(struct xe_device *xe, struct iosys_map *map,</div><div class='add'>+				 u32 wr_offset, u32 huc_offset, u32 huc_size)</div><div class='add'>+{</div><div class='add'>+	xe_map_memset(xe, map, wr_offset, 0, sizeof(struct pxp43_new_huc_auth_in));</div><div class='add'>+</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, header.api_version, PXP_APIVER(4, 3));</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, header.command_id, PXP43_CMDID_NEW_HUC_AUTH);</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, header.status, 0);</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, header.buffer_len,</div><div class='add'>+			sizeof(struct pxp43_new_huc_auth_in) - sizeof(struct pxp_cmd_header));</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, huc_base_address, huc_offset);</div><div class='add'>+	huc_auth_msg_wr(xe, map, wr_offset, huc_size, huc_size);</div><div class='add'>+</div><div class='add'>+	return wr_offset + sizeof(struct pxp43_new_huc_auth_in);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int huc_auth_via_gsccs(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_bo *pkt = huc-&gt;gsc_pkt;</div><div class='add'>+	u32 wr_offset;</div><div class='add'>+	u32 rd_offset;</div><div class='add'>+	u64 ggtt_offset;</div><div class='add'>+	u32 out_status;</div><div class='add'>+	int retry = 5;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	if (!pkt)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	ggtt_offset = xe_bo_ggtt_addr(pkt);</div><div class='add'>+</div><div class='add'>+	wr_offset = xe_gsc_emit_header(xe, &amp;pkt-&gt;vmap, 0, HECI_MEADDRESS_PXP, 0,</div><div class='add'>+				       sizeof(struct pxp43_new_huc_auth_in));</div><div class='add'>+	wr_offset = huc_emit_pxp_auth_msg(xe, &amp;pkt-&gt;vmap, wr_offset,</div><div class='add'>+					  xe_bo_ggtt_addr(huc-&gt;fw.bo),</div><div class='add'>+					  huc-&gt;fw.bo-&gt;size);</div><div class='add'>+	do {</div><div class='add'>+		err = xe_gsc_pkt_submit_kernel(&amp;gt-&gt;uc.gsc, ggtt_offset, wr_offset,</div><div class='add'>+					       ggtt_offset + PXP43_HUC_AUTH_INOUT_SIZE,</div><div class='add'>+					       PXP43_HUC_AUTH_INOUT_SIZE);</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (xe_gsc_check_and_update_pending(xe, &amp;pkt-&gt;vmap, 0, &amp;pkt-&gt;vmap,</div><div class='add'>+						    PXP43_HUC_AUTH_INOUT_SIZE)) {</div><div class='add'>+			err = -EBUSY;</div><div class='add'>+			msleep(50);</div><div class='add'>+		}</div><div class='add'>+	} while (--retry &amp;&amp; err == -EBUSY);</div><div class='add'>+</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "failed to submit GSC request to auth: %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_gsc_read_out_header(xe, &amp;pkt-&gt;vmap, PXP43_HUC_AUTH_INOUT_SIZE,</div><div class='add'>+				     sizeof(struct pxp43_huc_auth_out), &amp;rd_offset);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "HuC: invalid GSC reply for auth (err=%d)\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The GSC will return PXP_STATUS_OP_NOT_PERMITTED if the HuC is already</div><div class='add'>+	 * authenticated. If the same error is ever returned with HuC not loaded</div><div class='add'>+	 * we'll still catch it when we check the authentication bit later.</div><div class='add'>+	 */</div><div class='add'>+	out_status = huc_auth_msg_rd(xe, &amp;pkt-&gt;vmap, rd_offset, header.status);</div><div class='add'>+	if (out_status != PXP_STATUS_SUCCESS &amp;&amp; out_status != PXP_STATUS_OP_NOT_PERMITTED) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "auth failed with GSC error = 0x%x\n", out_status);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct {</div><div class='add'>+	const char *name;</div><div class='add'>+	struct xe_reg reg;</div><div class='add'>+	u32 val;</div><div class='add'>+} huc_auth_modes[XE_HUC_AUTH_TYPES_COUNT] = {</div><div class='add'>+	[XE_HUC_AUTH_VIA_GUC] = { "GuC",</div><div class='add'>+				  HUC_KERNEL_LOAD_INFO,</div><div class='add'>+				  HUC_LOAD_SUCCESSFUL },</div><div class='add'>+	[XE_HUC_AUTH_VIA_GSC] = { "GSC",</div><div class='add'>+				  HECI_FWSTS5(MTL_GSC_HECI1_BASE),</div><div class='add'>+				  HECI1_FWSTS5_HUC_AUTH_DONE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+bool xe_huc_is_authenticated(struct xe_huc *huc, enum xe_huc_auth_types type)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read32(gt, huc_auth_modes[type].reg) &amp; huc_auth_modes[type].val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = huc_to_xe(huc);</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+	struct xe_guc *guc = huc_to_guc(huc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_loadable(&amp;huc-&gt;fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* On newer platforms the HuC survives reset, so no need to re-auth */</div><div class='add'>+	if (xe_huc_is_authenticated(huc, type)) {</div><div class='add'>+		xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_RUNNING);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_loaded(&amp;huc-&gt;fw))</div><div class='add'>+		return -ENOEXEC;</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case XE_HUC_AUTH_VIA_GUC:</div><div class='add'>+		ret = xe_guc_auth_huc(guc, xe_bo_ggtt_addr(huc-&gt;fw.bo) +</div><div class='add'>+				      xe_uc_fw_rsa_offset(&amp;huc-&gt;fw));</div><div class='add'>+		break;</div><div class='add'>+	case XE_HUC_AUTH_VIA_GSC:</div><div class='add'>+		ret = huc_auth_via_gsccs(huc);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON(type);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Failed to trigger HuC auth via %s: %d\n",</div><div class='add'>+			huc_auth_modes[type].name, ret);</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = xe_mmio_wait32(gt, huc_auth_modes[type].reg, huc_auth_modes[type].val,</div><div class='add'>+			     huc_auth_modes[type].val, 100000, NULL, false);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "HuC: Firmware not verified %d\n", ret);</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_RUNNING);</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "HuC authenticated via %s\n", huc_auth_modes[type].name);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "HuC: Auth via %s failed: %d\n",</div><div class='add'>+		huc_auth_modes[type].name, ret);</div><div class='add'>+	xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_LOAD_FAIL);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_huc_sanitize(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	if (!xe_uc_fw_is_loadable(&amp;huc-&gt;fw))</div><div class='add'>+		return;</div><div class='add'>+	xe_uc_fw_change_status(&amp;huc-&gt;fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = huc_to_gt(huc);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_print(&amp;huc-&gt;fw, p);</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_enabled(&amp;huc-&gt;fw))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nHuC status: 0x%08x\n",</div><div class='add'>+		   xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));</div><div class='add'>+</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_huc.h b/drivers/gpu/drm/xe/xe_huc.h<br/>new file mode 100644<br/>index 000000000000..532017230287<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_huc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HUC_H_</div><div class='add'>+#define _XE_HUC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_huc_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+enum xe_huc_auth_types {</div><div class='add'>+	XE_HUC_AUTH_VIA_GUC = 0,</div><div class='add'>+	XE_HUC_AUTH_VIA_GSC,</div><div class='add'>+	XE_HUC_AUTH_TYPES_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_huc_init(struct xe_huc *huc);</div><div class='add'>+int xe_huc_upload(struct xe_huc *huc);</div><div class='add'>+int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type);</div><div class='add'>+bool xe_huc_is_authenticated(struct xe_huc *huc, enum xe_huc_auth_types type);</div><div class='add'>+void xe_huc_sanitize(struct xe_huc *huc);</div><div class='add'>+void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_huc_debugfs.c b/drivers/gpu/drm/xe/xe_huc_debugfs.c<br/>new file mode 100644<br/>index 000000000000..18585a7eeb9d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_huc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,70 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_huc_debugfs.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_debugfs.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_huc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+huc_to_gt(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	return container_of(huc, struct xe_gt, uc.huc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+huc_to_xe(struct xe_huc *huc)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(huc_to_gt(huc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_huc *node_to_huc(struct drm_info_node *node)</div><div class='add'>+{</div><div class='add'>+	return node-&gt;info_ent-&gt;data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int huc_info(struct seq_file *m, void *data)</div><div class='add'>+{</div><div class='add'>+	struct xe_huc *huc = node_to_huc(m-&gt;private);</div><div class='add'>+	struct xe_device *xe = huc_to_xe(huc);</div><div class='add'>+	struct drm_printer p = drm_seq_file_printer(m);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_huc_print_info(huc, &amp;p);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct drm_info_list debugfs_list[] = {</div><div class='add'>+	{"huc_info", huc_info, 0},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_huc_debugfs_register(struct xe_huc *huc, struct dentry *parent)</div><div class='add'>+{</div><div class='add'>+	struct drm_minor *minor = huc_to_xe(huc)-&gt;drm.primary;</div><div class='add'>+	struct drm_info_list *local;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+#define DEBUGFS_SIZE	(ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))</div><div class='add'>+	local = drmm_kmalloc(&amp;huc_to_xe(huc)-&gt;drm, DEBUGFS_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!local)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	memcpy(local, debugfs_list, DEBUGFS_SIZE);</div><div class='add'>+#undef DEBUGFS_SIZE</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(debugfs_list); ++i)</div><div class='add'>+		local[i].data = huc;</div><div class='add'>+</div><div class='add'>+	drm_debugfs_create_files(local,</div><div class='add'>+				 ARRAY_SIZE(debugfs_list),</div><div class='add'>+				 parent, minor);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_huc_debugfs.h b/drivers/gpu/drm/xe/xe_huc_debugfs.h<br/>new file mode 100644<br/>index 000000000000..ec58f1818804<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_huc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HUC_DEBUGFS_H_</div><div class='add'>+#define _XE_HUC_DEBUGFS_H_</div><div class='add'>+</div><div class='add'>+struct dentry;</div><div class='add'>+struct xe_huc;</div><div class='add'>+</div><div class='add'>+void xe_huc_debugfs_register(struct xe_huc *huc, struct dentry *parent);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_huc_types.h b/drivers/gpu/drm/xe/xe_huc_types.h<br/>new file mode 100644<br/>index 000000000000..cfbaa5e0dfca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_huc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_huc_types.h</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HUC_TYPES_H_</div><div class='add'>+#define _XE_HUC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_uc_fw_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_huc - HuC</div><div class='add'>+ */</div><div class='add'>+struct xe_huc {</div><div class='add'>+	/** @fw: Generic uC firmware management */</div><div class='add'>+	struct xe_uc_fw fw;</div><div class='add'>+</div><div class='add'>+	/** @gsc_pkt: bo to store the packet for auth via GSC */</div><div class='add'>+	struct xe_bo *gsc_pkt;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c<br/>new file mode 100644<br/>index 000000000000..1fa5cf5eea97<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_engine.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine.c</a></div><div class='hunk'>@@ -0,0 +1,883 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_execlist.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_ccs_mode.h"</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_irq.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_tuning.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+#define MAX_MMIO_BASES 3</div><div class='add'>+struct engine_info {</div><div class='add'>+	const char *name;</div><div class='add'>+	unsigned int class : 8;</div><div class='add'>+	unsigned int instance : 8;</div><div class='add'>+	enum xe_force_wake_domains domain;</div><div class='add'>+	u32 mmio_base;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct engine_info engine_infos[] = {</div><div class='add'>+	[XE_HW_ENGINE_RCS0] = {</div><div class='add'>+		.name = "rcs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_RENDER,</div><div class='add'>+		.instance = 0,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = RENDER_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS0] = {</div><div class='add'>+		.name = "bcs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 0,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = BLT_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS1] = {</div><div class='add'>+		.name = "bcs1",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 1,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS1_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS2] = {</div><div class='add'>+		.name = "bcs2",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 2,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS2_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS3] = {</div><div class='add'>+		.name = "bcs3",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 3,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS3_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS4] = {</div><div class='add'>+		.name = "bcs4",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 4,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS4_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS5] = {</div><div class='add'>+		.name = "bcs5",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 5,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS5_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS6] = {</div><div class='add'>+		.name = "bcs6",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 6,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS6_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS7] = {</div><div class='add'>+		.name = "bcs7",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 7,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS7_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_BCS8] = {</div><div class='add'>+		.name = "bcs8",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COPY,</div><div class='add'>+		.instance = 8,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = XEHPC_BCS8_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	[XE_HW_ENGINE_VCS0] = {</div><div class='add'>+		.name = "vcs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 0,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX0,</div><div class='add'>+		.mmio_base = BSD_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS1] = {</div><div class='add'>+		.name = "vcs1",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 1,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX1,</div><div class='add'>+		.mmio_base = BSD2_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS2] = {</div><div class='add'>+		.name = "vcs2",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 2,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX2,</div><div class='add'>+		.mmio_base = BSD3_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS3] = {</div><div class='add'>+		.name = "vcs3",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 3,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX3,</div><div class='add'>+		.mmio_base = BSD4_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS4] = {</div><div class='add'>+		.name = "vcs4",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 4,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX4,</div><div class='add'>+		.mmio_base = XEHP_BSD5_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS5] = {</div><div class='add'>+		.name = "vcs5",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 5,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX5,</div><div class='add'>+		.mmio_base = XEHP_BSD6_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS6] = {</div><div class='add'>+		.name = "vcs6",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 6,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX6,</div><div class='add'>+		.mmio_base = XEHP_BSD7_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VCS7] = {</div><div class='add'>+		.name = "vcs7",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+		.instance = 7,</div><div class='add'>+		.domain = XE_FW_MEDIA_VDBOX7,</div><div class='add'>+		.mmio_base = XEHP_BSD8_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VECS0] = {</div><div class='add'>+		.name = "vecs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+		.instance = 0,</div><div class='add'>+		.domain = XE_FW_MEDIA_VEBOX0,</div><div class='add'>+		.mmio_base = VEBOX_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VECS1] = {</div><div class='add'>+		.name = "vecs1",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+		.instance = 1,</div><div class='add'>+		.domain = XE_FW_MEDIA_VEBOX1,</div><div class='add'>+		.mmio_base = VEBOX2_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VECS2] = {</div><div class='add'>+		.name = "vecs2",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+		.instance = 2,</div><div class='add'>+		.domain = XE_FW_MEDIA_VEBOX2,</div><div class='add'>+		.mmio_base = XEHP_VEBOX3_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_VECS3] = {</div><div class='add'>+		.name = "vecs3",</div><div class='add'>+		.class = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+		.instance = 3,</div><div class='add'>+		.domain = XE_FW_MEDIA_VEBOX3,</div><div class='add'>+		.mmio_base = XEHP_VEBOX4_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_CCS0] = {</div><div class='add'>+		.name = "ccs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+		.instance = 0,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = COMPUTE0_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_CCS1] = {</div><div class='add'>+		.name = "ccs1",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+		.instance = 1,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = COMPUTE1_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_CCS2] = {</div><div class='add'>+		.name = "ccs2",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+		.instance = 2,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = COMPUTE2_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_CCS3] = {</div><div class='add'>+		.name = "ccs3",</div><div class='add'>+		.class = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+		.instance = 3,</div><div class='add'>+		.domain = XE_FW_RENDER,</div><div class='add'>+		.mmio_base = COMPUTE3_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+	[XE_HW_ENGINE_GSCCS0] = {</div><div class='add'>+		.name = "gsccs0",</div><div class='add'>+		.class = XE_ENGINE_CLASS_OTHER,</div><div class='add'>+		.instance = OTHER_GSC_INSTANCE,</div><div class='add'>+		.domain = XE_FW_GSC,</div><div class='add'>+		.mmio_base = GSCCS_RING_BASE,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void hw_engine_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe = arg;</div><div class='add'>+</div><div class='add'>+	if (hwe-&gt;exl_port)</div><div class='add'>+		xe_execlist_port_destroy(hwe-&gt;exl_port);</div><div class='add'>+	xe_lrc_finish(&amp;hwe-&gt;kernel_lrc);</div><div class='add'>+</div><div class='add'>+	hwe-&gt;gt = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg,</div><div class='add'>+				   u32 val)</div><div class='add'>+{</div><div class='add'>+	xe_gt_assert(hwe-&gt;gt, !(reg.addr &amp; hwe-&gt;mmio_base));</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(hwe-&gt;gt), hwe-&gt;domain);</div><div class='add'>+</div><div class='add'>+	reg.addr += hwe-&gt;mmio_base;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(hwe-&gt;gt, reg, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	xe_gt_assert(hwe-&gt;gt, !(reg.addr &amp; hwe-&gt;mmio_base));</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(hwe-&gt;gt), hwe-&gt;domain);</div><div class='add'>+</div><div class='add'>+	reg.addr += hwe-&gt;mmio_base;</div><div class='add'>+</div><div class='add'>+	return xe_mmio_read32(hwe-&gt;gt, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	u32 ccs_mask =</div><div class='add'>+		xe_hw_engine_mask_per_class(hwe-&gt;gt, XE_ENGINE_CLASS_COMPUTE);</div><div class='add'>+</div><div class='add'>+	if (hwe-&gt;class == XE_ENGINE_CLASS_COMPUTE &amp;&amp; ccs_mask)</div><div class='add'>+		xe_mmio_write32(hwe-&gt;gt, RCU_MODE,</div><div class='add'>+				_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));</div><div class='add'>+</div><div class='add'>+	hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);</div><div class='add'>+	hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),</div><div class='add'>+			       xe_bo_ggtt_addr(hwe-&gt;hwsp));</div><div class='add'>+	hw_engine_mmio_write32(hwe, RING_MODE(0),</div><div class='add'>+			       _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));</div><div class='add'>+	hw_engine_mmio_write32(hwe, RING_MI_MODE(0),</div><div class='add'>+			       _MASKED_BIT_DISABLE(STOP_RING));</div><div class='add'>+	hw_engine_mmio_read32(hwe, RING_MI_MODE(0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_gt *gt,</div><div class='add'>+						 const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return xe_gt_ccs_mode_enabled(gt) &amp;&amp;</div><div class='add'>+	       xe_rtp_match_first_render_or_compute(gt, hwe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	const u8 mocs_write_idx = gt-&gt;mocs.uc_index;</div><div class='add'>+	const u8 mocs_read_idx = gt-&gt;mocs.uc_index;</div><div class='add'>+	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |</div><div class='add'>+			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+	const struct xe_rtp_entry_sr lrc_was[] = {</div><div class='add'>+		/*</div><div class='add'>+		 * Some blitter commands do not have a field for MOCS, those</div><div class='add'>+		 * commands will use MOCS index pointed by BLIT_CCTL.</div><div class='add'>+		 * BLIT_CCTL registers are needed to be programmed to un-cached.</div><div class='add'>+		 */</div><div class='add'>+		{ XE_RTP_NAME("BLIT_CCTL_default_MOCS"),</div><div class='add'>+		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),</div><div class='add'>+			       ENGINE_CLASS(COPY)),</div><div class='add'>+		  XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),</div><div class='add'>+				 BLIT_CCTL_DST_MOCS_MASK |</div><div class='add'>+				 BLIT_CCTL_SRC_MOCS_MASK,</div><div class='add'>+				 blit_cctl_val,</div><div class='add'>+				 XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+		},</div><div class='add'>+		/* Use Fixed slice CCS mode */</div><div class='add'>+		{ XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),</div><div class='add'>+		  XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),</div><div class='add'>+		  XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,</div><div class='add'>+					   RCU_MODE_FIXED_SLICE_CCS_MODE))</div><div class='add'>+		},</div><div class='add'>+		{}</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, lrc_was, &amp;hwe-&gt;reg_lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+hw_engine_setup_default_state(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	/*</div><div class='add'>+	 * RING_CMD_CCTL specifies the default MOCS entry that will be</div><div class='add'>+	 * used by the command streamer when executing commands that</div><div class='add'>+	 * don't have a way to explicitly specify a MOCS setting.</div><div class='add'>+	 * The default should usually reference whichever MOCS entry</div><div class='add'>+	 * corresponds to uncached behavior, although use of a WB cached</div><div class='add'>+	 * entry is recommended by the spec in certain circumstances on</div><div class='add'>+	 * specific platforms.</div><div class='add'>+	 * Bspec: 72161</div><div class='add'>+	 */</div><div class='add'>+	const u8 mocs_write_idx = gt-&gt;mocs.uc_index;</div><div class='add'>+	const u8 mocs_read_idx = hwe-&gt;class == XE_ENGINE_CLASS_COMPUTE &amp;&amp;</div><div class='add'>+				 (GRAPHICS_VER(xe) &gt;= 20 || xe-&gt;info.platform == XE_PVC) ?</div><div class='add'>+				 gt-&gt;mocs.wb_index : gt-&gt;mocs.uc_index;</div><div class='add'>+	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |</div><div class='add'>+				REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+	const struct xe_rtp_entry_sr engine_entries[] = {</div><div class='add'>+		{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),</div><div class='add'>+		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)),</div><div class='add'>+		  XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),</div><div class='add'>+					   CMD_CCTL_WRITE_OVERRIDE_MASK |</div><div class='add'>+					   CMD_CCTL_READ_OVERRIDE_MASK,</div><div class='add'>+					   ring_cmd_cctl_val,</div><div class='add'>+					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+		},</div><div class='add'>+		/*</div><div class='add'>+		 * To allow the GSC engine to go idle on MTL we need to enable</div><div class='add'>+		 * idle messaging and set the hysteresis value (we use 0xA=5us</div><div class='add'>+		 * as recommended in spec). On platforms after MTL this is</div><div class='add'>+		 * enabled by default.</div><div class='add'>+		 */</div><div class='add'>+		{ XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),</div><div class='add'>+		  XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),</div><div class='add'>+		  XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),</div><div class='add'>+				     IDLE_MSG_DISABLE,</div><div class='add'>+				     XE_RTP_ACTION_FLAG(ENGINE_BASE)),</div><div class='add'>+				 FIELD_SET(RING_PWRCTX_MAXCNT(0),</div><div class='add'>+					   IDLE_WAIT_TIME,</div><div class='add'>+					   0xA,</div><div class='add'>+					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+		},</div><div class='add'>+		{}</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, engine_entries, &amp;hwe-&gt;reg_sr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,</div><div class='add'>+				 enum xe_hw_engine_id id)</div><div class='add'>+{</div><div class='add'>+	const struct engine_info *info;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(id &gt;= ARRAY_SIZE(engine_infos) || !engine_infos[id].name))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!(gt-&gt;info.engine_mask &amp; BIT(id)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	info = &amp;engine_infos[id];</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, !hwe-&gt;gt);</div><div class='add'>+</div><div class='add'>+	hwe-&gt;gt = gt;</div><div class='add'>+	hwe-&gt;class = info-&gt;class;</div><div class='add'>+	hwe-&gt;instance = info-&gt;instance;</div><div class='add'>+	hwe-&gt;mmio_base = info-&gt;mmio_base;</div><div class='add'>+	hwe-&gt;domain = info-&gt;domain;</div><div class='add'>+	hwe-&gt;name = info-&gt;name;</div><div class='add'>+	hwe-&gt;fence_irq = &amp;gt-&gt;fence_irq[info-&gt;class];</div><div class='add'>+	hwe-&gt;engine_id = id;</div><div class='add'>+</div><div class='add'>+	hwe-&gt;eclass = &amp;gt-&gt;eclass[hwe-&gt;class];</div><div class='add'>+	if (!hwe-&gt;eclass-&gt;sched_props.job_timeout_ms) {</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.job_timeout_ms = 5 * 1000;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.job_timeout_min = XE_HW_ENGINE_JOB_TIMEOUT_MIN;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.job_timeout_max = XE_HW_ENGINE_JOB_TIMEOUT_MAX;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.timeslice_us = 1 * 1000;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.timeslice_min = XE_HW_ENGINE_TIMESLICE_MIN;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.timeslice_max = XE_HW_ENGINE_TIMESLICE_MAX;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.preempt_timeout_us = XE_HW_ENGINE_PREEMPT_TIMEOUT;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.preempt_timeout_min = XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN;</div><div class='add'>+		hwe-&gt;eclass-&gt;sched_props.preempt_timeout_max = XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX;</div><div class='add'>+		/* Record default props */</div><div class='add'>+		hwe-&gt;eclass-&gt;defaults = hwe-&gt;eclass-&gt;sched_props;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_init(&amp;hwe-&gt;reg_sr, hwe-&gt;name, gt_to_xe(gt));</div><div class='add'>+	xe_tuning_process_engine(hwe);</div><div class='add'>+	xe_wa_process_engine(hwe);</div><div class='add'>+	hw_engine_setup_default_state(hwe);</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_init(&amp;hwe-&gt;reg_whitelist, hwe-&gt;name, gt_to_xe(gt));</div><div class='add'>+	xe_reg_whitelist_process_engine(hwe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,</div><div class='add'>+			  enum xe_hw_engine_id id)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, id &lt; ARRAY_SIZE(engine_infos) &amp;&amp; engine_infos[id].name);</div><div class='add'>+	xe_gt_assert(gt, gt-&gt;info.engine_mask &amp; BIT(id));</div><div class='add'>+</div><div class='add'>+	xe_reg_sr_apply_mmio(&amp;hwe-&gt;reg_sr, gt);</div><div class='add'>+	xe_reg_sr_apply_whitelist(hwe);</div><div class='add'>+</div><div class='add'>+	hwe-&gt;hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K,</div><div class='add'>+						 XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+						 XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(hwe-&gt;hwsp)) {</div><div class='add'>+		err = PTR_ERR(hwe-&gt;hwsp);</div><div class='add'>+		goto err_name;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_lrc_init(&amp;hwe-&gt;kernel_lrc, hwe, NULL, NULL, SZ_16K);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_hwsp;</div><div class='add'>+</div><div class='add'>+	if (!xe_device_uc_enabled(xe)) {</div><div class='add'>+		hwe-&gt;exl_port = xe_execlist_port_create(xe, hwe);</div><div class='add'>+		if (IS_ERR(hwe-&gt;exl_port)) {</div><div class='add'>+			err = PTR_ERR(hwe-&gt;exl_port);</div><div class='add'>+			goto err_kernel_lrc;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_device_uc_enabled(xe))</div><div class='add'>+		xe_hw_engine_enable_ring(hwe);</div><div class='add'>+</div><div class='add'>+	/* We reserve the highest BCS instance for USM */</div><div class='add'>+	if (xe-&gt;info.has_usm &amp;&amp; hwe-&gt;class == XE_ENGINE_CLASS_COPY)</div><div class='add'>+		gt-&gt;usm.reserved_bcs_instance = hwe-&gt;instance;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, hw_engine_fini, hwe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_kernel_lrc:</div><div class='add'>+	xe_lrc_finish(&amp;hwe-&gt;kernel_lrc);</div><div class='add'>+err_hwsp:</div><div class='add'>+	xe_bo_unpin_map_no_vm(hwe-&gt;hwsp);</div><div class='add'>+err_name:</div><div class='add'>+	hwe-&gt;name = NULL;</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hw_engine_setup_logical_mapping(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int class;</div><div class='add'>+</div><div class='add'>+	/* FIXME: Doing a simple logical mapping that works for most hardware */</div><div class='add'>+	for (class = 0; class &lt; XE_ENGINE_CLASS_MAX; ++class) {</div><div class='add'>+		struct xe_hw_engine *hwe;</div><div class='add'>+		enum xe_hw_engine_id id;</div><div class='add'>+		int logical_instance = 0;</div><div class='add'>+</div><div class='add'>+		for_each_hw_engine(hwe, gt, id)</div><div class='add'>+			if (hwe-&gt;class == class)</div><div class='add'>+				hwe-&gt;logical_instance = logical_instance++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_media_fuses(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 media_fuse;</div><div class='add'>+	u16 vdbox_mask;</div><div class='add'>+	u16 vebox_mask;</div><div class='add'>+	int i, j;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Pre-Xe_HP platforms had register bits representing absent engines,</div><div class='add'>+	 * whereas Xe_HP and beyond have bits representing present engines.</div><div class='add'>+	 * Invert the polarity on old platforms so that we can use common</div><div class='add'>+	 * handling below.</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1250)</div><div class='add'>+		media_fuse = ~media_fuse;</div><div class='add'>+</div><div class='add'>+	vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse);</div><div class='add'>+	vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse);</div><div class='add'>+</div><div class='add'>+	for (i = XE_HW_ENGINE_VCS0, j = 0; i &lt;= XE_HW_ENGINE_VCS7; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!(BIT(j) &amp; vdbox_mask)) {</div><div class='add'>+			gt-&gt;info.engine_mask &amp;= ~BIT(i);</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "vcs%u fused off\n", j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = XE_HW_ENGINE_VECS0, j = 0; i &lt;= XE_HW_ENGINE_VECS3; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!(BIT(j) &amp; vebox_mask)) {</div><div class='add'>+			gt-&gt;info.engine_mask &amp;= ~BIT(i);</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "vecs%u fused off\n", j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_copy_fuses(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 bcs_mask;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1260 || GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);</div><div class='add'>+	bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);</div><div class='add'>+</div><div class='add'>+	/* BCS0 is always present; only BCS1-BCS8 may be fused off */</div><div class='add'>+	for (int i = XE_HW_ENGINE_BCS1, j = 0; i &lt;= XE_HW_ENGINE_BCS8; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!(BIT(j / 2) &amp; bcs_mask)) {</div><div class='add'>+			gt-&gt;info.engine_mask &amp;= ~BIT(i);</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "bcs%u fused off\n", j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_compute_fuses_from_dss(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * CCS fusing based on DSS masks only applies to platforms that can</div><div class='add'>+	 * have more than one CCS.</div><div class='add'>+	 */</div><div class='add'>+	if (hweight64(gt-&gt;info.engine_mask &amp;</div><div class='add'>+		      GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)) &lt;= 1)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * CCS availability on Xe_HP is inferred from the presence of DSS in</div><div class='add'>+	 * each quadrant.</div><div class='add'>+	 */</div><div class='add'>+	for (int i = XE_HW_ENGINE_CCS0, j = 0; i &lt;= XE_HW_ENGINE_CCS3; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!xe_gt_topology_has_dss_in_quadrant(gt, j)) {</div><div class='add'>+			gt-&gt;info.engine_mask &amp;= ~BIT(i);</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "ccs%u fused off\n", j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_compute_fuses_from_reg(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 ccs_mask;</div><div class='add'>+</div><div class='add'>+	ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4);</div><div class='add'>+	ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);</div><div class='add'>+</div><div class='add'>+	for (int i = XE_HW_ENGINE_CCS0, j = 0; i &lt;= XE_HW_ENGINE_CCS3; ++i, ++j) {</div><div class='add'>+		if (!(gt-&gt;info.engine_mask &amp; BIT(i)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if ((ccs_mask &amp; BIT(j)) == 0) {</div><div class='add'>+			gt-&gt;info.engine_mask &amp;= ~BIT(i);</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "ccs%u fused off\n", j);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void read_compute_fuses(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VER(gt_to_xe(gt)) &gt;= 20)</div><div class='add'>+		read_compute_fuses_from_reg(gt);</div><div class='add'>+	else</div><div class='add'>+		read_compute_fuses_from_dss(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void check_gsc_availability(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (!(gt-&gt;info.engine_mask &amp; BIT(XE_HW_ENGINE_GSCCS0)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The GSCCS is only used to communicate with the GSC FW, so if we don't</div><div class='add'>+	 * have the FW there is nothing we need the engine for and can therefore</div><div class='add'>+	 * skip its initialization.</div><div class='add'>+	 */</div><div class='add'>+	if (!xe_uc_fw_is_available(&amp;gt-&gt;uc.gsc.fw)) {</div><div class='add'>+		gt-&gt;info.engine_mask &amp;= ~BIT(XE_HW_ENGINE_GSCCS0);</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "gsccs disabled due to lack of FW\n");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_hw_engines_init_early(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	read_media_fuses(gt);</div><div class='add'>+	read_copy_fuses(gt);</div><div class='add'>+	read_compute_fuses(gt);</div><div class='add'>+	check_gsc_availability(gt);</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT &lt; XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN);</div><div class='add'>+	BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT &gt; XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(gt-&gt;hw_engines); i++)</div><div class='add'>+		hw_engine_init_early(gt, &amp;gt-&gt;hw_engines[i], i);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_hw_engines_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		err = hw_engine_init(gt, hwe, id);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hw_engine_setup_logical_mapping(gt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)</div><div class='add'>+{</div><div class='add'>+	wake_up_all(&amp;gt_to_xe(hwe-&gt;gt)-&gt;ufence_wq);</div><div class='add'>+</div><div class='add'>+	if (hwe-&gt;irq_handler)</div><div class='add'>+		hwe-&gt;irq_handler(hwe, intr_vec);</div><div class='add'>+</div><div class='add'>+	if (intr_vec &amp; GT_RENDER_USER_INTERRUPT)</div><div class='add'>+		xe_hw_fence_irq_run(hwe-&gt;fence_irq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW Engine.</div><div class='add'>+ * @hwe: Xe HW Engine.</div><div class='add'>+ *</div><div class='add'>+ * This can be printed out in a later stage like during dev_coredump</div><div class='add'>+ * analysis.</div><div class='add'>+ *</div><div class='add'>+ * Returns: a Xe HW Engine snapshot object that must be freed by the</div><div class='add'>+ * caller, using `xe_hw_engine_snapshot_free`.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_engine_snapshot *</div><div class='add'>+xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_snapshot *snapshot;</div><div class='add'>+	int len;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_is_valid(hwe))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);</div><div class='add'>+</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	len = strlen(hwe-&gt;name) + 1;</div><div class='add'>+	snapshot-&gt;name = kzalloc(len, GFP_ATOMIC);</div><div class='add'>+	if (snapshot-&gt;name)</div><div class='add'>+		strscpy(snapshot-&gt;name, hwe-&gt;name, len);</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;class = hwe-&gt;class;</div><div class='add'>+	snapshot-&gt;logical_instance = hwe-&gt;logical_instance;</div><div class='add'>+	snapshot-&gt;forcewake.domain = hwe-&gt;domain;</div><div class='add'>+	snapshot-&gt;forcewake.ref = xe_force_wake_ref(gt_to_fw(hwe-&gt;gt),</div><div class='add'>+						    hwe-&gt;domain);</div><div class='add'>+	snapshot-&gt;mmio_base = hwe-&gt;mmio_base;</div><div class='add'>+</div><div class='add'>+	snapshot-&gt;reg.ring_hwstam = hw_engine_mmio_read32(hwe, RING_HWSTAM(0));</div><div class='add'>+	snapshot-&gt;reg.ring_hws_pga = hw_engine_mmio_read32(hwe,</div><div class='add'>+							   RING_HWS_PGA(0));</div><div class='add'>+	snapshot-&gt;reg.ring_execlist_status_lo =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0));</div><div class='add'>+	snapshot-&gt;reg.ring_execlist_status_hi =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0));</div><div class='add'>+	snapshot-&gt;reg.ring_execlist_sq_contents_lo =</div><div class='add'>+		hw_engine_mmio_read32(hwe,</div><div class='add'>+				      RING_EXECLIST_SQ_CONTENTS_LO(0));</div><div class='add'>+	snapshot-&gt;reg.ring_execlist_sq_contents_hi =</div><div class='add'>+		hw_engine_mmio_read32(hwe,</div><div class='add'>+				      RING_EXECLIST_SQ_CONTENTS_HI(0));</div><div class='add'>+	snapshot-&gt;reg.ring_start = hw_engine_mmio_read32(hwe, RING_START(0));</div><div class='add'>+	snapshot-&gt;reg.ring_head =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_HEAD(0)) &amp; HEAD_ADDR;</div><div class='add'>+	snapshot-&gt;reg.ring_tail =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_TAIL(0)) &amp; TAIL_ADDR;</div><div class='add'>+	snapshot-&gt;reg.ring_ctl = hw_engine_mmio_read32(hwe, RING_CTL(0));</div><div class='add'>+	snapshot-&gt;reg.ring_mi_mode =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_MI_MODE(0));</div><div class='add'>+	snapshot-&gt;reg.ring_mode = hw_engine_mmio_read32(hwe, RING_MODE(0));</div><div class='add'>+	snapshot-&gt;reg.ring_imr = hw_engine_mmio_read32(hwe, RING_IMR(0));</div><div class='add'>+	snapshot-&gt;reg.ring_esr = hw_engine_mmio_read32(hwe, RING_ESR(0));</div><div class='add'>+	snapshot-&gt;reg.ring_emr = hw_engine_mmio_read32(hwe, RING_EMR(0));</div><div class='add'>+	snapshot-&gt;reg.ring_eir = hw_engine_mmio_read32(hwe, RING_EIR(0));</div><div class='add'>+	snapshot-&gt;reg.ring_acthd_udw =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0));</div><div class='add'>+	snapshot-&gt;reg.ring_acthd = hw_engine_mmio_read32(hwe, RING_ACTHD(0));</div><div class='add'>+	snapshot-&gt;reg.ring_bbaddr_udw =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0));</div><div class='add'>+	snapshot-&gt;reg.ring_bbaddr = hw_engine_mmio_read32(hwe, RING_BBADDR(0));</div><div class='add'>+	snapshot-&gt;reg.ring_dma_fadd_udw =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0));</div><div class='add'>+	snapshot-&gt;reg.ring_dma_fadd =</div><div class='add'>+		hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));</div><div class='add'>+	snapshot-&gt;reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0));</div><div class='add'>+</div><div class='add'>+	if (snapshot-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+		snapshot-&gt;reg.rcu_mode = xe_mmio_read32(hwe-&gt;gt, RCU_MODE);</div><div class='add'>+</div><div class='add'>+	return snapshot;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_snapshot_print - Print out a given Xe HW Engine snapshot.</div><div class='add'>+ * @snapshot: Xe HW Engine snapshot object.</div><div class='add'>+ * @p: drm_printer where it will be printed out.</div><div class='add'>+ *</div><div class='add'>+ * This function prints out a given Xe HW Engine snapshot object.</div><div class='add'>+ */</div><div class='add'>+void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,</div><div class='add'>+				 struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "%s (physical), logical instance=%d\n",</div><div class='add'>+		   snapshot-&gt;name ? snapshot-&gt;name : "",</div><div class='add'>+		   snapshot-&gt;logical_instance);</div><div class='add'>+	drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n",</div><div class='add'>+		   snapshot-&gt;forcewake.domain, snapshot-&gt;forcewake.ref);</div><div class='add'>+	drm_printf(p, "\tHWSTAM: 0x%08x\n", snapshot-&gt;reg.ring_hwstam);</div><div class='add'>+	drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n", snapshot-&gt;reg.ring_hws_pga);</div><div class='add'>+	drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_execlist_status_lo);</div><div class='add'>+	drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_execlist_status_hi);</div><div class='add'>+	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_execlist_sq_contents_lo);</div><div class='add'>+	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_execlist_sq_contents_hi);</div><div class='add'>+	drm_printf(p, "\tRING_START: 0x%08x\n", snapshot-&gt;reg.ring_start);</div><div class='add'>+	drm_printf(p, "\tRING_HEAD:  0x%08x\n", snapshot-&gt;reg.ring_head);</div><div class='add'>+	drm_printf(p, "\tRING_TAIL:  0x%08x\n", snapshot-&gt;reg.ring_tail);</div><div class='add'>+	drm_printf(p, "\tRING_CTL: 0x%08x\n", snapshot-&gt;reg.ring_ctl);</div><div class='add'>+	drm_printf(p, "\tRING_MI_MODE: 0x%08x\n", snapshot-&gt;reg.ring_mi_mode);</div><div class='add'>+	drm_printf(p, "\tRING_MODE: 0x%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_mode);</div><div class='add'>+	drm_printf(p, "\tRING_IMR:   0x%08x\n", snapshot-&gt;reg.ring_imr);</div><div class='add'>+	drm_printf(p, "\tRING_ESR:   0x%08x\n", snapshot-&gt;reg.ring_esr);</div><div class='add'>+	drm_printf(p, "\tRING_EMR:   0x%08x\n", snapshot-&gt;reg.ring_emr);</div><div class='add'>+	drm_printf(p, "\tRING_EIR:   0x%08x\n", snapshot-&gt;reg.ring_eir);</div><div class='add'>+	drm_printf(p, "\tACTHD:  0x%08x_%08x\n", snapshot-&gt;reg.ring_acthd_udw,</div><div class='add'>+		   snapshot-&gt;reg.ring_acthd);</div><div class='add'>+	drm_printf(p, "\tBBADDR: 0x%08x_%08x\n", snapshot-&gt;reg.ring_bbaddr_udw,</div><div class='add'>+		   snapshot-&gt;reg.ring_bbaddr);</div><div class='add'>+	drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",</div><div class='add'>+		   snapshot-&gt;reg.ring_dma_fadd_udw,</div><div class='add'>+		   snapshot-&gt;reg.ring_dma_fadd);</div><div class='add'>+	drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot-&gt;reg.ipehr);</div><div class='add'>+	if (snapshot-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+		drm_printf(p, "\tRCU_MODE: 0x%08x\n",</div><div class='add'>+			   snapshot-&gt;reg.rcu_mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_snapshot_free - Free all allocated objects for a given snapshot.</div><div class='add'>+ * @snapshot: Xe HW Engine snapshot object.</div><div class='add'>+ *</div><div class='add'>+ * This function free all the memory that needed to be allocated at capture</div><div class='add'>+ * time.</div><div class='add'>+ */</div><div class='add'>+void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot)</div><div class='add'>+{</div><div class='add'>+	if (!snapshot)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kfree(snapshot-&gt;name);</div><div class='add'>+	kfree(snapshot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_print - Xe HW Engine Print.</div><div class='add'>+ * @hwe: Hardware Engine.</div><div class='add'>+ * @p: drm_printer.</div><div class='add'>+ *</div><div class='add'>+ * This function quickly capture a snapshot and immediately print it out.</div><div class='add'>+ */</div><div class='add'>+void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_snapshot *snapshot;</div><div class='add'>+</div><div class='add'>+	snapshot = xe_hw_engine_snapshot_capture(hwe);</div><div class='add'>+	xe_hw_engine_snapshot_print(snapshot, p);</div><div class='add'>+	xe_hw_engine_snapshot_free(snapshot);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,</div><div class='add'>+				enum xe_engine_class engine_class)</div><div class='add'>+{</div><div class='add'>+	u32 mask = 0;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	for (id = 0; id &lt; XE_NUM_HW_ENGINES; ++id) {</div><div class='add'>+		if (engine_infos[id].class == engine_class &amp;&amp;</div><div class='add'>+		    gt-&gt;info.engine_mask &amp; BIT(id))</div><div class='add'>+			mask |= BIT(engine_infos[id].instance);</div><div class='add'>+	}</div><div class='add'>+	return mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (hwe-&gt;class == XE_ENGINE_CLASS_OTHER)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* Check for engines disabled by ccs_mode setting */</div><div class='add'>+	if (xe_gt_ccs_mode_enabled(gt) &amp;&amp;</div><div class='add'>+	    hwe-&gt;class == XE_ENGINE_CLASS_COMPUTE &amp;&amp;</div><div class='add'>+	    hwe-&gt;logical_instance &gt;= gt-&gt;ccs_mode)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return xe-&gt;info.has_usm &amp;&amp; hwe-&gt;class == XE_ENGINE_CLASS_COPY &amp;&amp;</div><div class='add'>+		hwe-&gt;instance == gt-&gt;usm.reserved_bcs_instance;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h<br/>new file mode 100644<br/>index 000000000000..71968ee2f600<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_engine.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine.h</a></div><div class='hunk'>@@ -0,0 +1,70 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HW_ENGINE_H_</div><div class='add'>+#define _XE_HW_ENGINE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MIN</div><div class='add'>+#define XE_HW_ENGINE_JOB_TIMEOUT_MIN CONFIG_DRM_XE_JOB_TIMEOUT_MIN</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_JOB_TIMEOUT_MIN 1</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_JOB_TIMEOUT_MAX</div><div class='add'>+#define XE_HW_ENGINE_JOB_TIMEOUT_MAX CONFIG_DRM_XE_JOB_TIMEOUT_MAX</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_JOB_TIMEOUT_MAX (10 * 1000)</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_TIMESLICE_MIN</div><div class='add'>+#define XE_HW_ENGINE_TIMESLICE_MIN CONFIG_DRM_XE_TIMESLICE_MIN</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_TIMESLICE_MIN 1</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_TIMESLICE_MAX</div><div class='add'>+#define XE_HW_ENGINE_TIMESLICE_MAX CONFIG_DRM_XE_TIMESLICE_MAX</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_TIMESLICE_MAX (10 * 1000 * 1000)</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT CONFIG_DRM_XE_PREEMPT_TIMEOUT</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT (640 * 1000)</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN 1</div><div class='add'>+#endif</div><div class='add'>+#ifdef CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX</div><div class='add'>+#else</div><div class='add'>+#define XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX (10 * 1000 * 1000)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+int xe_hw_engines_init_early(struct xe_gt *gt);</div><div class='add'>+int xe_hw_engines_init(struct xe_gt *gt);</div><div class='add'>+void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);</div><div class='add'>+void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);</div><div class='add'>+u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,</div><div class='add'>+				enum xe_engine_class engine_class);</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine_snapshot *</div><div class='add'>+xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe);</div><div class='add'>+void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot);</div><div class='add'>+void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,</div><div class='add'>+				 struct drm_printer *p);</div><div class='add'>+void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p);</div><div class='add'>+void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);</div><div class='add'>+static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return hwe-&gt;name;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c b/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c<br/>new file mode 100644<br/>index 000000000000..e49bc14f0ecf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c</a></div><div class='hunk'>@@ -0,0 +1,675 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine_class_sysfs.h"</div><div class='add'>+</div><div class='add'>+#define MAX_ENGINE_CLASS_NAME_LEN    16</div><div class='add'>+static int xe_add_hw_engine_class_defaults(struct xe_device *xe,</div><div class='add'>+					   struct kobject *parent);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_timeout_in_range - Helper to check if timeout is in range</div><div class='add'>+ * @timeout: timeout to validate</div><div class='add'>+ * @min: min value of valid range</div><div class='add'>+ * @max: max value of valid range</div><div class='add'>+ *</div><div class='add'>+ * This helper helps to validate if timeout is in min-max range of HW engine</div><div class='add'>+ * scheduler.</div><div class='add'>+ *</div><div class='add'>+ * Returns: Returns false value for failure and true for success.</div><div class='add'>+ */</div><div class='add'>+bool xe_hw_engine_timeout_in_range(u64 timeout, u64 min, u64 max)</div><div class='add'>+{</div><div class='add'>+	return timeout &gt;= min &amp;&amp; timeout &lt;= max;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void kobj_xe_hw_engine_release(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	kfree(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kobj_type kobj_xe_hw_engine_type = {</div><div class='add'>+	.release = kobj_xe_hw_engine_release,</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_max_store(struct kobject *kobj,</div><div class='add'>+				     struct kobj_attribute *attr,</div><div class='add'>+				     const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (timeout &lt; eclass-&gt;sched_props.job_timeout_min)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout,</div><div class='add'>+					   XE_HW_ENGINE_JOB_TIMEOUT_MIN,</div><div class='add'>+					   XE_HW_ENGINE_JOB_TIMEOUT_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.job_timeout_max, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_max_show(struct kobject *kobj,</div><div class='add'>+				    struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.job_timeout_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_max_attr =</div><div class='add'>+__ATTR(job_timeout_max, 0644, job_timeout_max_show, job_timeout_max_store);</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_min_store(struct kobject *kobj,</div><div class='add'>+				     struct kobj_attribute *attr,</div><div class='add'>+				     const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (timeout &gt; eclass-&gt;sched_props.job_timeout_max)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout,</div><div class='add'>+					   XE_HW_ENGINE_JOB_TIMEOUT_MIN,</div><div class='add'>+					   XE_HW_ENGINE_JOB_TIMEOUT_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.job_timeout_min, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_min_show(struct kobject *kobj,</div><div class='add'>+				    struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.job_timeout_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_min_attr =</div><div class='add'>+__ATTR(job_timeout_min, 0644, job_timeout_min_show, job_timeout_min_store);</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_store(struct kobject *kobj,</div><div class='add'>+				 struct kobj_attribute *attr,</div><div class='add'>+				 const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 min = eclass-&gt;sched_props.job_timeout_min;</div><div class='add'>+	u32 max = eclass-&gt;sched_props.job_timeout_max;</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.job_timeout_ms, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_show(struct kobject *kobj,</div><div class='add'>+				struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.job_timeout_ms);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_attr =</div><div class='add'>+__ATTR(job_timeout_ms, 0644, job_timeout_show, job_timeout_store);</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_default(struct kobject *kobj,</div><div class='add'>+				   struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.job_timeout_ms);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_def =</div><div class='add'>+__ATTR(job_timeout_ms, 0444, job_timeout_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_min_default(struct kobject *kobj,</div><div class='add'>+				       struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.job_timeout_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_min_def =</div><div class='add'>+__ATTR(job_timeout_min, 0444, job_timeout_min_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t job_timeout_max_default(struct kobject *kobj,</div><div class='add'>+				       struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.job_timeout_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute job_timeout_max_def =</div><div class='add'>+__ATTR(job_timeout_max, 0444, job_timeout_max_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_store(struct kobject *kobj,</div><div class='add'>+					struct kobj_attribute *attr,</div><div class='add'>+					const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 min = eclass-&gt;sched_props.timeslice_min;</div><div class='add'>+	u32 max = eclass-&gt;sched_props.timeslice_max;</div><div class='add'>+	u32 duration;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;duration);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(duration, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.timeslice_us, duration);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_max_store(struct kobject *kobj,</div><div class='add'>+					    struct kobj_attribute *attr,</div><div class='add'>+					    const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 duration;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;duration);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (duration &lt; eclass-&gt;sched_props.timeslice_min)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(duration,</div><div class='add'>+					   XE_HW_ENGINE_TIMESLICE_MIN,</div><div class='add'>+					   XE_HW_ENGINE_TIMESLICE_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.timeslice_max, duration);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_max_show(struct kobject *kobj,</div><div class='add'>+					   struct kobj_attribute *attr,</div><div class='add'>+					   char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.timeslice_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_max_attr =</div><div class='add'>+	__ATTR(timeslice_duration_max, 0644, timeslice_duration_max_show,</div><div class='add'>+	       timeslice_duration_max_store);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_min_store(struct kobject *kobj,</div><div class='add'>+					    struct kobj_attribute *attr,</div><div class='add'>+					    const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 duration;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;duration);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (duration &gt; eclass-&gt;sched_props.timeslice_max)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(duration,</div><div class='add'>+					   XE_HW_ENGINE_TIMESLICE_MIN,</div><div class='add'>+					   XE_HW_ENGINE_TIMESLICE_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.timeslice_min, duration);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_min_show(struct kobject *kobj,</div><div class='add'>+					   struct kobj_attribute *attr,</div><div class='add'>+					   char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.timeslice_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_min_attr =</div><div class='add'>+	__ATTR(timeslice_duration_min, 0644, timeslice_duration_min_show,</div><div class='add'>+	       timeslice_duration_min_store);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_duration_show(struct kobject *kobj,</div><div class='add'>+				       struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.timeslice_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_attr =</div><div class='add'>+	__ATTR(timeslice_duration_us, 0644, timeslice_duration_show,</div><div class='add'>+	       timeslice_duration_store);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_default(struct kobject *kobj,</div><div class='add'>+				 struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.timeslice_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_def =</div><div class='add'>+__ATTR(timeslice_duration_us, 0444, timeslice_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_min_default(struct kobject *kobj,</div><div class='add'>+				     struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.timeslice_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_min_def =</div><div class='add'>+__ATTR(timeslice_duration_min, 0444, timeslice_min_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t timeslice_max_default(struct kobject *kobj,</div><div class='add'>+				     struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.timeslice_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute timeslice_duration_max_def =</div><div class='add'>+__ATTR(timeslice_duration_max, 0444, timeslice_max_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_store(struct kobject *kobj,</div><div class='add'>+				     struct kobj_attribute *attr,</div><div class='add'>+				     const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 min = eclass-&gt;sched_props.preempt_timeout_min;</div><div class='add'>+	u32 max = eclass-&gt;sched_props.preempt_timeout_max;</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout, min, max))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.preempt_timeout_us, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_show(struct kobject *kobj,</div><div class='add'>+				    struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.preempt_timeout_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_attr =</div><div class='add'>+__ATTR(preempt_timeout_us, 0644, preempt_timeout_show, preempt_timeout_store);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_default(struct kobject *kobj,</div><div class='add'>+				       struct kobj_attribute *attr,</div><div class='add'>+				       char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.preempt_timeout_us);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_def =</div><div class='add'>+__ATTR(preempt_timeout_us, 0444, preempt_timeout_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_min_default(struct kobject *kobj,</div><div class='add'>+					   struct kobj_attribute *attr,</div><div class='add'>+					   char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.preempt_timeout_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_min_def =</div><div class='add'>+__ATTR(preempt_timeout_min, 0444, preempt_timeout_min_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_max_default(struct kobject *kobj,</div><div class='add'>+					   struct kobj_attribute *attr,</div><div class='add'>+					   char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;defaults.preempt_timeout_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_max_def =</div><div class='add'>+__ATTR(preempt_timeout_max, 0444, preempt_timeout_max_default, NULL);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_max_store(struct kobject *kobj,</div><div class='add'>+					 struct kobj_attribute *attr,</div><div class='add'>+					 const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (timeout &lt; eclass-&gt;sched_props.preempt_timeout_min)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout,</div><div class='add'>+					   XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN,</div><div class='add'>+					   XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.preempt_timeout_max, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_max_show(struct kobject *kobj,</div><div class='add'>+					struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.preempt_timeout_max);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_max_attr =</div><div class='add'>+	__ATTR(preempt_timeout_max, 0644, preempt_timeout_max_show,</div><div class='add'>+	       preempt_timeout_max_store);</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_min_store(struct kobject *kobj,</div><div class='add'>+					 struct kobj_attribute *attr,</div><div class='add'>+					 const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+	u32 timeout;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = kstrtou32(buf, 0, &amp;timeout);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (timeout &gt; eclass-&gt;sched_props.preempt_timeout_max)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!xe_hw_engine_timeout_in_range(timeout,</div><div class='add'>+					   XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN,</div><div class='add'>+					   XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	WRITE_ONCE(eclass-&gt;sched_props.preempt_timeout_min, timeout);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t preempt_timeout_min_show(struct kobject *kobj,</div><div class='add'>+					struct kobj_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass = kobj_to_eclass(kobj);</div><div class='add'>+</div><div class='add'>+	return sprintf(buf, "%u\n", eclass-&gt;sched_props.preempt_timeout_min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct kobj_attribute preempt_timeout_min_attr =</div><div class='add'>+	__ATTR(preempt_timeout_min, 0644, preempt_timeout_min_show,</div><div class='add'>+	       preempt_timeout_min_store);</div><div class='add'>+</div><div class='add'>+static const struct attribute *defaults[] = {</div><div class='add'>+	&amp;job_timeout_def.attr,</div><div class='add'>+	&amp;job_timeout_min_def.attr,</div><div class='add'>+	&amp;job_timeout_max_def.attr,</div><div class='add'>+	&amp;timeslice_duration_def.attr,</div><div class='add'>+	&amp;timeslice_duration_min_def.attr,</div><div class='add'>+	&amp;timeslice_duration_max_def.attr,</div><div class='add'>+	&amp;preempt_timeout_def.attr,</div><div class='add'>+	&amp;preempt_timeout_min_def.attr,</div><div class='add'>+	&amp;preempt_timeout_max_def.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute *files[] = {</div><div class='add'>+	&amp;job_timeout_attr.attr,</div><div class='add'>+	&amp;job_timeout_min_attr.attr,</div><div class='add'>+	&amp;job_timeout_max_attr.attr,</div><div class='add'>+	&amp;timeslice_duration_attr.attr,</div><div class='add'>+	&amp;timeslice_duration_min_attr.attr,</div><div class='add'>+	&amp;timeslice_duration_max_attr.attr,</div><div class='add'>+	&amp;preempt_timeout_attr.attr,</div><div class='add'>+	&amp;preempt_timeout_min_attr.attr,</div><div class='add'>+	&amp;preempt_timeout_max_attr.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void kobj_xe_hw_engine_class_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_files(kobj, files);</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+	static struct kobj_eclass *</div><div class='add'>+kobj_xe_hw_engine_class(struct xe_device *xe, struct kobject *parent, char *name)</div><div class='add'>+{</div><div class='add'>+	struct kobj_eclass *keclass;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	keclass = kzalloc(sizeof(*keclass), GFP_KERNEL);</div><div class='add'>+	if (!keclass)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	kobject_init(&amp;keclass-&gt;base, &amp;kobj_xe_hw_engine_type);</div><div class='add'>+	if (kobject_add(&amp;keclass-&gt;base, parent, "%s", name)) {</div><div class='add'>+		kobject_put(&amp;keclass-&gt;base);</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, kobj_xe_hw_engine_class_fini,</div><div class='add'>+				       &amp;keclass-&gt;base);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm,</div><div class='add'>+			 "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+	return keclass;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hw_engine_class_defaults_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = arg;</div><div class='add'>+</div><div class='add'>+	sysfs_remove_files(kobj, defaults);</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_add_hw_engine_class_defaults(struct xe_device *xe,</div><div class='add'>+					   struct kobject *parent)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	kobj = kzalloc(sizeof(*kobj), GFP_KERNEL);</div><div class='add'>+	if (!kobj)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	kobject_init(kobj, &amp;kobj_xe_hw_engine_type);</div><div class='add'>+	err = kobject_add(kobj, parent, "%s", ".defaults");</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_object;</div><div class='add'>+</div><div class='add'>+	err = sysfs_create_files(kobj, defaults);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_object;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, hw_engine_class_defaults_fini,</div><div class='add'>+				       kobj);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm,</div><div class='add'>+			 "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+	return err;</div><div class='add'>+err_object:</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hw_engine_sysfs_kobj_release(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	kfree(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xe_hw_engine_sysfs_kobj_type = {</div><div class='add'>+	.release = xe_hw_engine_sysfs_kobj_release,</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void hw_engine_class_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct kobject *kobj = arg;</div><div class='add'>+</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_hw_engine_class_sysfs_init - Init HW engine classes on GT.</div><div class='add'>+ * @gt: Xe GT.</div><div class='add'>+ *</div><div class='add'>+ * This routine creates sysfs for HW engine classes and adds methods</div><div class='add'>+ * to get/set different scheduling properties for HW engines class.</div><div class='add'>+ *</div><div class='add'>+ * Returns: Returns error value for failure and 0 for success.</div><div class='add'>+ */</div><div class='add'>+int xe_hw_engine_class_sysfs_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	struct kobject *kobj;</div><div class='add'>+	u16 class_mask = 0;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	kobj = kzalloc(sizeof(*kobj), GFP_KERNEL);</div><div class='add'>+	if (!kobj)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	kobject_init(kobj, &amp;xe_hw_engine_sysfs_kobj_type);</div><div class='add'>+</div><div class='add'>+	err = kobject_add(kobj, gt-&gt;sysfs, "engines");</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_object;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		char name[MAX_ENGINE_CLASS_NAME_LEN];</div><div class='add'>+		struct kobj_eclass *keclass;</div><div class='add'>+</div><div class='add'>+		if (hwe-&gt;class == XE_ENGINE_CLASS_OTHER ||</div><div class='add'>+		    hwe-&gt;class == XE_ENGINE_CLASS_MAX)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if ((class_mask &gt;&gt; hwe-&gt;class) &amp; 1)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		class_mask |= 1 &lt;&lt; hwe-&gt;class;</div><div class='add'>+</div><div class='add'>+		switch (hwe-&gt;class) {</div><div class='add'>+		case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+			strcpy(name, "rcs");</div><div class='add'>+			break;</div><div class='add'>+		case XE_ENGINE_CLASS_VIDEO_DECODE:</div><div class='add'>+			strcpy(name, "vcs");</div><div class='add'>+			break;</div><div class='add'>+		case XE_ENGINE_CLASS_VIDEO_ENHANCE:</div><div class='add'>+			strcpy(name, "vecs");</div><div class='add'>+			break;</div><div class='add'>+		case XE_ENGINE_CLASS_COPY:</div><div class='add'>+			strcpy(name, "bcs");</div><div class='add'>+			break;</div><div class='add'>+		case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+			strcpy(name, "ccs");</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto err_object;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		keclass = kobj_xe_hw_engine_class(xe, kobj, name);</div><div class='add'>+		if (!keclass) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto err_object;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		keclass-&gt;eclass = hwe-&gt;eclass;</div><div class='add'>+		err = xe_add_hw_engine_class_defaults(xe, &amp;keclass-&gt;base);</div><div class='add'>+		if (err) {</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm,</div><div class='add'>+				 "Add .defaults to engines failed!, err: %d\n",</div><div class='add'>+				 err);</div><div class='add'>+			goto err_object;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		err = sysfs_create_files(&amp;keclass-&gt;base, files);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_object;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, hw_engine_class_sysfs_fini,</div><div class='add'>+				       kobj);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm,</div><div class='add'>+			 "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+err_object:</div><div class='add'>+	kobject_put(kobj);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h b/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h<br/>new file mode 100644<br/>index 000000000000..ec5ba673b314<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_ENGINE_CLASS_SYSFS_H_</div><div class='add'>+#define _XE_ENGINE_CLASS_SYSFS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_hw_engine_class_intf;</div><div class='add'>+</div><div class='add'>+int xe_hw_engine_class_sysfs_init(struct xe_gt *gt);</div><div class='add'>+bool xe_hw_engine_timeout_in_range(u64 timeout, u64 min, u64 max);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct kobj_eclass - A eclass's kobject struct that connects the kobject and the</div><div class='add'>+ * eclass.</div><div class='add'>+ *</div><div class='add'>+ * When dealing with multiple eclass, this struct helps to understand which eclass</div><div class='add'>+ * needs to be addressed on a given sysfs call.</div><div class='add'>+ */</div><div class='add'>+struct kobj_eclass {</div><div class='add'>+	/** @base: The actual kobject */</div><div class='add'>+	struct kobject base;</div><div class='add'>+	/** @eclass: A pointer to the hw engine class interface */</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct xe_hw_engine_class_intf *kobj_to_eclass(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	return container_of(kobj, struct kobj_eclass, base)-&gt;eclass;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h<br/>new file mode 100644<br/>index 000000000000..39908dec042a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_engine_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_engine_types.h</a></div><div class='hunk'>@@ -0,0 +1,225 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HW_ENGINE_TYPES_H_</div><div class='add'>+#define _XE_HW_ENGINE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_force_wake_types.h"</div><div class='add'>+#include "xe_lrc_types.h"</div><div class='add'>+#include "xe_reg_sr_types.h"</div><div class='add'>+</div><div class='add'>+/* See "Engine ID Definition" struct in the Icelake PRM */</div><div class='add'>+enum xe_engine_class {</div><div class='add'>+	XE_ENGINE_CLASS_RENDER = 0,</div><div class='add'>+	XE_ENGINE_CLASS_VIDEO_DECODE = 1,</div><div class='add'>+	XE_ENGINE_CLASS_VIDEO_ENHANCE = 2,</div><div class='add'>+	XE_ENGINE_CLASS_COPY = 3,</div><div class='add'>+	XE_ENGINE_CLASS_OTHER = 4,</div><div class='add'>+	XE_ENGINE_CLASS_COMPUTE = 5,</div><div class='add'>+	XE_ENGINE_CLASS_MAX = 6,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_hw_engine_id {</div><div class='add'>+	XE_HW_ENGINE_RCS0,</div><div class='add'>+#define XE_HW_ENGINE_RCS_MASK	GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)</div><div class='add'>+	XE_HW_ENGINE_BCS0,</div><div class='add'>+	XE_HW_ENGINE_BCS1,</div><div class='add'>+	XE_HW_ENGINE_BCS2,</div><div class='add'>+	XE_HW_ENGINE_BCS3,</div><div class='add'>+	XE_HW_ENGINE_BCS4,</div><div class='add'>+	XE_HW_ENGINE_BCS5,</div><div class='add'>+	XE_HW_ENGINE_BCS6,</div><div class='add'>+	XE_HW_ENGINE_BCS7,</div><div class='add'>+	XE_HW_ENGINE_BCS8,</div><div class='add'>+#define XE_HW_ENGINE_BCS_MASK	GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)</div><div class='add'>+	XE_HW_ENGINE_VCS0,</div><div class='add'>+	XE_HW_ENGINE_VCS1,</div><div class='add'>+	XE_HW_ENGINE_VCS2,</div><div class='add'>+	XE_HW_ENGINE_VCS3,</div><div class='add'>+	XE_HW_ENGINE_VCS4,</div><div class='add'>+	XE_HW_ENGINE_VCS5,</div><div class='add'>+	XE_HW_ENGINE_VCS6,</div><div class='add'>+	XE_HW_ENGINE_VCS7,</div><div class='add'>+#define XE_HW_ENGINE_VCS_MASK	GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)</div><div class='add'>+	XE_HW_ENGINE_VECS0,</div><div class='add'>+	XE_HW_ENGINE_VECS1,</div><div class='add'>+	XE_HW_ENGINE_VECS2,</div><div class='add'>+	XE_HW_ENGINE_VECS3,</div><div class='add'>+#define XE_HW_ENGINE_VECS_MASK	GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)</div><div class='add'>+	XE_HW_ENGINE_CCS0,</div><div class='add'>+	XE_HW_ENGINE_CCS1,</div><div class='add'>+	XE_HW_ENGINE_CCS2,</div><div class='add'>+	XE_HW_ENGINE_CCS3,</div><div class='add'>+#define XE_HW_ENGINE_CCS_MASK	GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)</div><div class='add'>+	XE_HW_ENGINE_GSCCS0,</div><div class='add'>+#define XE_HW_ENGINE_GSCCS_MASK	GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)</div><div class='add'>+	XE_NUM_HW_ENGINES,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* FIXME: s/XE_HW_ENGINE_MAX_INSTANCE/XE_HW_ENGINE_MAX_COUNT */</div><div class='add'>+#define XE_HW_ENGINE_MAX_INSTANCE	9</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_execlist_port;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_engine_class_intf - per hw engine class struct interface</div><div class='add'>+ *</div><div class='add'>+ * Contains all the hw engine properties per engine class.</div><div class='add'>+ *</div><div class='add'>+ * @sched_props: scheduling properties</div><div class='add'>+ * @defaults: default scheduling properties</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_engine_class_intf {</div><div class='add'>+	/**</div><div class='add'>+	 * @sched_props: scheduling properties</div><div class='add'>+	 * @defaults: default scheduling properties</div><div class='add'>+	 */</div><div class='add'>+	struct {</div><div class='add'>+		/** @set_job_timeout: Set job timeout in ms for engine */</div><div class='add'>+		u32 job_timeout_ms;</div><div class='add'>+		/** @job_timeout_min: Min job timeout in ms for engine */</div><div class='add'>+		u32 job_timeout_min;</div><div class='add'>+		/** @job_timeout_max: Max job timeout in ms for engine */</div><div class='add'>+		u32 job_timeout_max;</div><div class='add'>+		/** @timeslice_us: timeslice period in micro-seconds */</div><div class='add'>+		u32 timeslice_us;</div><div class='add'>+		/** @timeslice_min: min timeslice period in micro-seconds */</div><div class='add'>+		u32 timeslice_min;</div><div class='add'>+		/** @timeslice_max: max timeslice period in micro-seconds */</div><div class='add'>+		u32 timeslice_max;</div><div class='add'>+		/** @preempt_timeout_us: preemption timeout in micro-seconds */</div><div class='add'>+		u32 preempt_timeout_us;</div><div class='add'>+		/** @preempt_timeout_min: min preemption timeout in micro-seconds */</div><div class='add'>+		u32 preempt_timeout_min;</div><div class='add'>+		/** @preempt_timeout_max: max preemption timeout in micro-seconds */</div><div class='add'>+		u32 preempt_timeout_max;</div><div class='add'>+	} sched_props, defaults;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_engine - Hardware engine</div><div class='add'>+ *</div><div class='add'>+ * Contains all the hardware engine state for physical instances.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_engine {</div><div class='add'>+	/** @gt: graphics tile this hw engine belongs to */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	/** @name: name of this hw engine */</div><div class='add'>+	const char *name;</div><div class='add'>+	/** @class: class of this hw engine */</div><div class='add'>+	enum xe_engine_class class;</div><div class='add'>+	/** @instance: physical instance of this hw engine */</div><div class='add'>+	u16 instance;</div><div class='add'>+	/** @logical_instance: logical instance of this hw engine */</div><div class='add'>+	u16 logical_instance;</div><div class='add'>+	/** @mmio_base: MMIO base address of this hw engine*/</div><div class='add'>+	u32 mmio_base;</div><div class='add'>+	/**</div><div class='add'>+	 * @reg_sr: table with registers to be restored on GT init/resume/reset</div><div class='add'>+	 */</div><div class='add'>+	struct xe_reg_sr reg_sr;</div><div class='add'>+	/**</div><div class='add'>+	 * @reg_whitelist: table with registers to be whitelisted</div><div class='add'>+	 */</div><div class='add'>+	struct xe_reg_sr reg_whitelist;</div><div class='add'>+	/**</div><div class='add'>+	 * @reg_lrc: LRC workaround registers</div><div class='add'>+	 */</div><div class='add'>+	struct xe_reg_sr reg_lrc;</div><div class='add'>+	/** @domain: force wake domain of this hw engine */</div><div class='add'>+	enum xe_force_wake_domains domain;</div><div class='add'>+	/** @hwsp: hardware status page buffer object */</div><div class='add'>+	struct xe_bo *hwsp;</div><div class='add'>+	/** @kernel_lrc: Kernel LRC (should be replaced /w an xe_engine) */</div><div class='add'>+	struct xe_lrc kernel_lrc;</div><div class='add'>+	/** @exl_port: execlists port */</div><div class='add'>+	struct xe_execlist_port *exl_port;</div><div class='add'>+	/** @fence_irq: fence IRQ to run when a hw engine IRQ is received */</div><div class='add'>+	struct xe_hw_fence_irq *fence_irq;</div><div class='add'>+	/** @irq_handler: IRQ handler to run when hw engine IRQ is received */</div><div class='add'>+	void (*irq_handler)(struct xe_hw_engine *hwe, u16 intr_vec);</div><div class='add'>+	/** @engine_id: id  for this hw engine */</div><div class='add'>+	enum xe_hw_engine_id engine_id;</div><div class='add'>+	/** @eclass: pointer to per hw engine class interface */</div><div class='add'>+	struct xe_hw_engine_class_intf *eclass;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_engine_snapshot - Hardware engine snapshot</div><div class='add'>+ *</div><div class='add'>+ * Contains the snapshot of useful hardware engine info and registers.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_engine_snapshot {</div><div class='add'>+	/** @name: name of the hw engine */</div><div class='add'>+	char *name;</div><div class='add'>+	/** @class: class of this hw engine */</div><div class='add'>+	enum xe_engine_class class;</div><div class='add'>+	/** @logical_instance: logical instance of this hw engine */</div><div class='add'>+	u16 logical_instance;</div><div class='add'>+	/** @forcewake: Force Wake information snapshot */</div><div class='add'>+	struct {</div><div class='add'>+		/** @domain: force wake domain of this hw engine */</div><div class='add'>+		enum xe_force_wake_domains domain;</div><div class='add'>+		/** @ref: Forcewake ref for the above domain */</div><div class='add'>+		int ref;</div><div class='add'>+	} forcewake;</div><div class='add'>+	/** @mmio_base: MMIO base address of this hw engine*/</div><div class='add'>+	u32 mmio_base;</div><div class='add'>+	/** @reg: Useful MMIO register snapshot */</div><div class='add'>+	struct {</div><div class='add'>+		/** @ring_hwstam: RING_HWSTAM */</div><div class='add'>+		u32 ring_hwstam;</div><div class='add'>+		/** @ring_hws_pga: RING_HWS_PGA */</div><div class='add'>+		u32 ring_hws_pga;</div><div class='add'>+		/** @ring_execlist_status_lo: RING_EXECLIST_STATUS_LO */</div><div class='add'>+		u32 ring_execlist_status_lo;</div><div class='add'>+		/** @ring_execlist_status_hi: RING_EXECLIST_STATUS_HI */</div><div class='add'>+		u32 ring_execlist_status_hi;</div><div class='add'>+		/** @ring_execlist_sq_contents_lo: RING_EXECLIST_SQ_CONTENTS */</div><div class='add'>+		u32 ring_execlist_sq_contents_lo;</div><div class='add'>+		/** @ring_execlist_sq_contents_hi: RING_EXECLIST_SQ_CONTENTS + 4 */</div><div class='add'>+		u32 ring_execlist_sq_contents_hi;</div><div class='add'>+		/** @ring_start: RING_START */</div><div class='add'>+		u32 ring_start;</div><div class='add'>+		/** @ring_head: RING_HEAD */</div><div class='add'>+		u32 ring_head;</div><div class='add'>+		/** @ring_tail: RING_TAIL */</div><div class='add'>+		u32 ring_tail;</div><div class='add'>+		/** @ring_ctl: RING_CTL */</div><div class='add'>+		u32 ring_ctl;</div><div class='add'>+		/** @ring_mi_mode: RING_MI_MODE */</div><div class='add'>+		u32 ring_mi_mode;</div><div class='add'>+		/** @ring_mode: RING_MODE */</div><div class='add'>+		u32 ring_mode;</div><div class='add'>+		/** @ring_imr: RING_IMR */</div><div class='add'>+		u32 ring_imr;</div><div class='add'>+		/** @ring_esr: RING_ESR */</div><div class='add'>+		u32 ring_esr;</div><div class='add'>+		/** @ring_emr: RING_EMR */</div><div class='add'>+		u32 ring_emr;</div><div class='add'>+		/** @ring_eir: RING_EIR */</div><div class='add'>+		u32 ring_eir;</div><div class='add'>+		/** @ring_acthd_udw: RING_ACTHD_UDW */</div><div class='add'>+		u32 ring_acthd_udw;</div><div class='add'>+		/** @ring_acthd: RING_ACTHD */</div><div class='add'>+		u32 ring_acthd;</div><div class='add'>+		/** @ring_bbaddr_udw: RING_BBADDR_UDW */</div><div class='add'>+		u32 ring_bbaddr_udw;</div><div class='add'>+		/** @ring_bbaddr: RING_BBADDR */</div><div class='add'>+		u32 ring_bbaddr;</div><div class='add'>+		/** @ring_dma_fadd_udw: RING_DMA_FADD_UDW */</div><div class='add'>+		u32 ring_dma_fadd_udw;</div><div class='add'>+		/** @ring_dma_fadd: RING_DMA_FADD */</div><div class='add'>+		u32 ring_dma_fadd;</div><div class='add'>+		/** @ipehr: IPEHR */</div><div class='add'>+		u32 ipehr;</div><div class='add'>+		/** @rcu_mode: RCU_MODE */</div><div class='add'>+		u32 rcu_mode;</div><div class='add'>+	} reg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c<br/>new file mode 100644<br/>index 000000000000..a6094c81f2ad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence.c</a></div><div class='hunk'>@@ -0,0 +1,230 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+</div><div class='add'>+static struct kmem_cache *xe_hw_fence_slab;</div><div class='add'>+</div><div class='add'>+int __init xe_hw_fence_module_init(void)</div><div class='add'>+{</div><div class='add'>+	xe_hw_fence_slab = kmem_cache_create("xe_hw_fence",</div><div class='add'>+					     sizeof(struct xe_hw_fence), 0,</div><div class='add'>+					     SLAB_HWCACHE_ALIGN, NULL);</div><div class='add'>+	if (!xe_hw_fence_slab)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_module_exit(void)</div><div class='add'>+{</div><div class='add'>+	rcu_barrier();</div><div class='add'>+	kmem_cache_destroy(xe_hw_fence_slab);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_hw_fence *fence_alloc(void)</div><div class='add'>+{</div><div class='add'>+	return kmem_cache_zalloc(xe_hw_fence_slab, GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void fence_free(struct rcu_head *rcu)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence =</div><div class='add'>+		container_of(rcu, struct xe_hw_fence, dma.rcu);</div><div class='add'>+</div><div class='add'>+	if (!WARN_ON_ONCE(!fence))</div><div class='add'>+		kmem_cache_free(xe_hw_fence_slab, fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hw_fence_irq_run_cb(struct irq_work *work)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence_irq *irq = container_of(work, typeof(*irq), work);</div><div class='add'>+	struct xe_hw_fence *fence, *next;</div><div class='add'>+	bool tmp;</div><div class='add'>+</div><div class='add'>+	tmp = dma_fence_begin_signalling();</div><div class='add'>+	spin_lock(&amp;irq-&gt;lock);</div><div class='add'>+	if (irq-&gt;enabled) {</div><div class='add'>+		list_for_each_entry_safe(fence, next, &amp;irq-&gt;pending, irq_link) {</div><div class='add'>+			struct dma_fence *dma_fence = &amp;fence-&gt;dma;</div><div class='add'>+</div><div class='add'>+			trace_xe_hw_fence_try_signal(fence);</div><div class='add'>+			if (dma_fence_is_signaled_locked(dma_fence)) {</div><div class='add'>+				trace_xe_hw_fence_signal(fence);</div><div class='add'>+				list_del_init(&amp;fence-&gt;irq_link);</div><div class='add'>+				dma_fence_put(dma_fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;irq-&gt;lock);</div><div class='add'>+	dma_fence_end_signalling(tmp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_init(struct xe_hw_fence_irq *irq)</div><div class='add'>+{</div><div class='add'>+	spin_lock_init(&amp;irq-&gt;lock);</div><div class='add'>+	init_irq_work(&amp;irq-&gt;work, hw_fence_irq_run_cb);</div><div class='add'>+	INIT_LIST_HEAD(&amp;irq-&gt;pending);</div><div class='add'>+	irq-&gt;enabled = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_finish(struct xe_hw_fence_irq *irq)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence, *next;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int err;</div><div class='add'>+	bool tmp;</div><div class='add'>+</div><div class='add'>+	if (XE_WARN_ON(!list_empty(&amp;irq-&gt;pending))) {</div><div class='add'>+		tmp = dma_fence_begin_signalling();</div><div class='add'>+		spin_lock_irqsave(&amp;irq-&gt;lock, flags);</div><div class='add'>+		list_for_each_entry_safe(fence, next, &amp;irq-&gt;pending, irq_link) {</div><div class='add'>+			list_del_init(&amp;fence-&gt;irq_link);</div><div class='add'>+			err = dma_fence_signal_locked(&amp;fence-&gt;dma);</div><div class='add'>+			dma_fence_put(&amp;fence-&gt;dma);</div><div class='add'>+			XE_WARN_ON(err);</div><div class='add'>+		}</div><div class='add'>+		spin_unlock_irqrestore(&amp;irq-&gt;lock, flags);</div><div class='add'>+		dma_fence_end_signalling(tmp);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_run(struct xe_hw_fence_irq *irq)</div><div class='add'>+{</div><div class='add'>+	irq_work_queue(&amp;irq-&gt;work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_stop(struct xe_hw_fence_irq *irq)</div><div class='add'>+{</div><div class='add'>+	spin_lock_irq(&amp;irq-&gt;lock);</div><div class='add'>+	irq-&gt;enabled = false;</div><div class='add'>+	spin_unlock_irq(&amp;irq-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_start(struct xe_hw_fence_irq *irq)</div><div class='add'>+{</div><div class='add'>+	spin_lock_irq(&amp;irq-&gt;lock);</div><div class='add'>+	irq-&gt;enabled = true;</div><div class='add'>+	spin_unlock_irq(&amp;irq-&gt;lock);</div><div class='add'>+</div><div class='add'>+	irq_work_queue(&amp;irq-&gt;work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_ctx_init(struct xe_hw_fence_ctx *ctx, struct xe_gt *gt,</div><div class='add'>+			  struct xe_hw_fence_irq *irq, const char *name)</div><div class='add'>+{</div><div class='add'>+	ctx-&gt;gt = gt;</div><div class='add'>+	ctx-&gt;irq = irq;</div><div class='add'>+	ctx-&gt;dma_fence_ctx = dma_fence_context_alloc(1);</div><div class='add'>+	ctx-&gt;next_seqno = XE_FENCE_INITIAL_SEQNO;</div><div class='add'>+	sprintf(ctx-&gt;name, "%s", name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_ctx_finish(struct xe_hw_fence_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence);</div><div class='add'>+</div><div class='add'>+static struct xe_hw_fence_irq *xe_hw_fence_irq(struct xe_hw_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return container_of(fence-&gt;dma.lock, struct xe_hw_fence_irq, lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *xe_hw_fence_get_driver_name(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);</div><div class='add'>+</div><div class='add'>+	return dev_name(gt_to_xe(fence-&gt;ctx-&gt;gt)-&gt;drm.dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *xe_hw_fence_get_timeline_name(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);</div><div class='add'>+</div><div class='add'>+	return fence-&gt;ctx-&gt;name;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_hw_fence_signaled(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(fence-&gt;ctx-&gt;gt);</div><div class='add'>+	u32 seqno = xe_map_rd(xe, &amp;fence-&gt;seqno_map, 0, u32);</div><div class='add'>+</div><div class='add'>+	return dma_fence-&gt;error ||</div><div class='add'>+		!__dma_fence_is_later(dma_fence-&gt;seqno, seqno, dma_fence-&gt;ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_hw_fence_enable_signaling(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);</div><div class='add'>+	struct xe_hw_fence_irq *irq = xe_hw_fence_irq(fence);</div><div class='add'>+</div><div class='add'>+	dma_fence_get(dma_fence);</div><div class='add'>+	list_add_tail(&amp;fence-&gt;irq_link, &amp;irq-&gt;pending);</div><div class='add'>+</div><div class='add'>+	/* SW completed (no HW IRQ) so kick handler to signal fence */</div><div class='add'>+	if (xe_hw_fence_signaled(dma_fence))</div><div class='add'>+		xe_hw_fence_irq_run(irq);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hw_fence_release(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);</div><div class='add'>+</div><div class='add'>+	trace_xe_hw_fence_free(fence);</div><div class='add'>+	XE_WARN_ON(!list_empty(&amp;fence-&gt;irq_link));</div><div class='add'>+	call_rcu(&amp;dma_fence-&gt;rcu, fence_free);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops xe_hw_fence_ops = {</div><div class='add'>+	.get_driver_name = xe_hw_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = xe_hw_fence_get_timeline_name,</div><div class='add'>+	.enable_signaling = xe_hw_fence_enable_signaling,</div><div class='add'>+	.signaled = xe_hw_fence_signaled,</div><div class='add'>+	.release = xe_hw_fence_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	if (XE_WARN_ON(fence-&gt;ops != &amp;xe_hw_fence_ops))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return container_of(fence, struct xe_hw_fence, dma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_hw_fence *xe_hw_fence_create(struct xe_hw_fence_ctx *ctx,</div><div class='add'>+				       struct iosys_map seqno_map)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_fence *fence;</div><div class='add'>+</div><div class='add'>+	fence = fence_alloc();</div><div class='add'>+	if (!fence)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	dma_fence_init(&amp;fence-&gt;dma, &amp;xe_hw_fence_ops, &amp;ctx-&gt;irq-&gt;lock,</div><div class='add'>+		       ctx-&gt;dma_fence_ctx, ctx-&gt;next_seqno++);</div><div class='add'>+</div><div class='add'>+	fence-&gt;ctx = ctx;</div><div class='add'>+	fence-&gt;seqno_map = seqno_map;</div><div class='add'>+	INIT_LIST_HEAD(&amp;fence-&gt;irq_link);</div><div class='add'>+</div><div class='add'>+	trace_xe_hw_fence_create(fence);</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_fence.h b/drivers/gpu/drm/xe/xe_hw_fence.h<br/>new file mode 100644<br/>index 000000000000..cfe5fd603787<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HW_FENCE_H_</div><div class='add'>+#define _XE_HW_FENCE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_hw_fence_types.h"</div><div class='add'>+</div><div class='add'>+/* Cause an early wrap to catch wrapping errors */</div><div class='add'>+#define XE_FENCE_INITIAL_SEQNO (-127)</div><div class='add'>+</div><div class='add'>+int xe_hw_fence_module_init(void);</div><div class='add'>+void xe_hw_fence_module_exit(void);</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_irq_init(struct xe_hw_fence_irq *irq);</div><div class='add'>+void xe_hw_fence_irq_finish(struct xe_hw_fence_irq *irq);</div><div class='add'>+void xe_hw_fence_irq_run(struct xe_hw_fence_irq *irq);</div><div class='add'>+void xe_hw_fence_irq_stop(struct xe_hw_fence_irq *irq);</div><div class='add'>+void xe_hw_fence_irq_start(struct xe_hw_fence_irq *irq);</div><div class='add'>+</div><div class='add'>+void xe_hw_fence_ctx_init(struct xe_hw_fence_ctx *ctx, struct xe_gt *gt,</div><div class='add'>+			  struct xe_hw_fence_irq *irq, const char *name);</div><div class='add'>+void xe_hw_fence_ctx_finish(struct xe_hw_fence_ctx *ctx);</div><div class='add'>+</div><div class='add'>+struct xe_hw_fence *xe_hw_fence_create(struct xe_hw_fence_ctx *ctx,</div><div class='add'>+				       struct iosys_map seqno_map);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hw_fence_types.h b/drivers/gpu/drm/xe/xe_hw_fence_types.h<br/>new file mode 100644<br/>index 000000000000..b33c4956e8ea<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hw_fence_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hw_fence_types.h</a></div><div class='hunk'>@@ -0,0 +1,72 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HW_FENCE_TYPES_H_</div><div class='add'>+#define _XE_HW_FENCE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/iosys-map.h&gt;</div><div class='add'>+#include &lt;linux/irq_work.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_fence_irq - hardware fence IRQ handler</div><div class='add'>+ *</div><div class='add'>+ * One per engine class, signals completed xe_hw_fences, triggered via hw engine</div><div class='add'>+ * interrupt. On each trigger, search list of pending fences and signal.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_fence_irq {</div><div class='add'>+	/** @lock: protects all xe_hw_fences + pending list */</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+	/** @work: IRQ worker run to signal the fences */</div><div class='add'>+	struct irq_work work;</div><div class='add'>+	/** @pending: list of pending xe_hw_fences */</div><div class='add'>+	struct list_head pending;</div><div class='add'>+	/** @enabled: fence signaling enabled */</div><div class='add'>+	bool enabled;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_FENCE_NAME_LEN	16</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_fence_ctx - hardware fence context</div><div class='add'>+ *</div><div class='add'>+ * The context for a hardware fence. 1 to 1 relationship with xe_engine. Points</div><div class='add'>+ * to a xe_hw_fence_irq, maintains serial seqno.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_fence_ctx {</div><div class='add'>+	/** @gt: graphics tile of hardware fence context */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	/** @irq: fence irq handler */</div><div class='add'>+	struct xe_hw_fence_irq *irq;</div><div class='add'>+	/** @dma_fence_ctx: dma fence context for hardware fence */</div><div class='add'>+	u64 dma_fence_ctx;</div><div class='add'>+	/** @next_seqno: next seqno for hardware fence */</div><div class='add'>+	u32 next_seqno;</div><div class='add'>+	/** @name: name of hardware fence context */</div><div class='add'>+	char name[MAX_FENCE_NAME_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hw_fence - hardware fence</div><div class='add'>+ *</div><div class='add'>+ * Used to indicate a xe_sched_job is complete via a seqno written to memory.</div><div class='add'>+ * Signals on error or seqno past.</div><div class='add'>+ */</div><div class='add'>+struct xe_hw_fence {</div><div class='add'>+	/** @dma: base dma fence for hardware fence context */</div><div class='add'>+	struct dma_fence dma;</div><div class='add'>+	/** @ctx: hardware fence context */</div><div class='add'>+	struct xe_hw_fence_ctx *ctx;</div><div class='add'>+	/** @seqno_map: I/O map for seqno */</div><div class='add'>+	struct iosys_map seqno_map;</div><div class='add'>+	/** @irq_link: Link in struct xe_hw_fence_irq.pending */</div><div class='add'>+	struct list_head irq_link;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c<br/>new file mode 100644<br/>index 000000000000..6ef2aa1eae8b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hwmon.c</a></div><div class='hunk'>@@ -0,0 +1,776 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/hwmon-sysfs.h&gt;</div><div class='add'>+#include &lt;linux/hwmon.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_mchbar_regs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hwmon.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+#include "xe_pcode_api.h"</div><div class='add'>+</div><div class='add'>+enum xe_hwmon_reg {</div><div class='add'>+	REG_PKG_RAPL_LIMIT,</div><div class='add'>+	REG_PKG_POWER_SKU,</div><div class='add'>+	REG_PKG_POWER_SKU_UNIT,</div><div class='add'>+	REG_GT_PERF_STATUS,</div><div class='add'>+	REG_PKG_ENERGY_STATUS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_hwmon_reg_operation {</div><div class='add'>+	REG_READ32,</div><div class='add'>+	REG_RMW32,</div><div class='add'>+	REG_READ64,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SF_* - scale factors for particular quantities according to hwmon spec.</div><div class='add'>+ */</div><div class='add'>+#define SF_POWER	1000000		/* microwatts */</div><div class='add'>+#define SF_CURR		1000		/* milliamperes */</div><div class='add'>+#define SF_VOLTAGE	1000		/* millivolts */</div><div class='add'>+#define SF_ENERGY	1000000		/* microjoules */</div><div class='add'>+#define SF_TIME		1000		/* milliseconds */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hwmon_energy_info - to accumulate energy</div><div class='add'>+ */</div><div class='add'>+struct xe_hwmon_energy_info {</div><div class='add'>+	/** @reg_val_prev: previous energy reg val */</div><div class='add'>+	u32 reg_val_prev;</div><div class='add'>+	/** @accum_energy: accumulated energy */</div><div class='add'>+	long accum_energy;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_hwmon - xe hwmon data structure</div><div class='add'>+ */</div><div class='add'>+struct xe_hwmon {</div><div class='add'>+	/** @hwmon_dev: hwmon device for xe */</div><div class='add'>+	struct device *hwmon_dev;</div><div class='add'>+	/** @gt: primary gt */</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	/** @hwmon_lock: lock for rw attributes*/</div><div class='add'>+	struct mutex hwmon_lock;</div><div class='add'>+	/** @scl_shift_power: pkg power unit */</div><div class='add'>+	int scl_shift_power;</div><div class='add'>+	/** @scl_shift_energy: pkg energy unit */</div><div class='add'>+	int scl_shift_energy;</div><div class='add'>+	/** @scl_shift_time: pkg time unit */</div><div class='add'>+	int scl_shift_time;</div><div class='add'>+	/** @ei: Energy info for energy1_input */</div><div class='add'>+	struct xe_hwmon_energy_info ei;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(hwmon-&gt;gt);</div><div class='add'>+	struct xe_reg reg = XE_REG(0);</div><div class='add'>+</div><div class='add'>+	switch (hwmon_reg) {</div><div class='add'>+	case REG_PKG_RAPL_LIMIT:</div><div class='add'>+		if (xe-&gt;info.platform == XE_DG2)</div><div class='add'>+			reg = PCU_CR_PACKAGE_RAPL_LIMIT;</div><div class='add'>+		else if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+			reg = PVC_GT0_PACKAGE_RAPL_LIMIT;</div><div class='add'>+		break;</div><div class='add'>+	case REG_PKG_POWER_SKU:</div><div class='add'>+		if (xe-&gt;info.platform == XE_DG2)</div><div class='add'>+			reg = PCU_CR_PACKAGE_POWER_SKU;</div><div class='add'>+		else if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+			reg = PVC_GT0_PACKAGE_POWER_SKU;</div><div class='add'>+		break;</div><div class='add'>+	case REG_PKG_POWER_SKU_UNIT:</div><div class='add'>+		if (xe-&gt;info.platform == XE_DG2)</div><div class='add'>+			reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;</div><div class='add'>+		else if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+			reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;</div><div class='add'>+		break;</div><div class='add'>+	case REG_GT_PERF_STATUS:</div><div class='add'>+		if (xe-&gt;info.platform == XE_DG2)</div><div class='add'>+			reg = GT_PERF_STATUS;</div><div class='add'>+		break;</div><div class='add'>+	case REG_PKG_ENERGY_STATUS:</div><div class='add'>+		if (xe-&gt;info.platform == XE_DG2)</div><div class='add'>+			reg = PCU_CR_PACKAGE_ENERGY_STATUS;</div><div class='add'>+		else if (xe-&gt;info.platform == XE_PVC)</div><div class='add'>+			reg = PVC_GT0_PLATFORM_ENERGY_STATUS;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return reg.raw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,</div><div class='add'>+				 enum xe_hwmon_reg_operation operation, u64 *value,</div><div class='add'>+				 u32 clr, u32 set)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg;</div><div class='add'>+</div><div class='add'>+	reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);</div><div class='add'>+</div><div class='add'>+	if (!reg.raw)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (operation) {</div><div class='add'>+	case REG_READ32:</div><div class='add'>+		*value = xe_mmio_read32(hwmon-&gt;gt, reg);</div><div class='add'>+		break;</div><div class='add'>+	case REG_RMW32:</div><div class='add'>+		*value = xe_mmio_rmw32(hwmon-&gt;gt, reg, clr, set);</div><div class='add'>+		break;</div><div class='add'>+	case REG_READ64:</div><div class='add'>+		*value = xe_mmio_read64_2x32(hwmon-&gt;gt, reg);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;gt_to_xe(hwmon-&gt;gt)-&gt;drm, "Invalid xe hwmon reg operation: %d\n",</div><div class='add'>+			 operation);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define PL1_DISABLE 0</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * HW allows arbitrary PL1 limits to be set but silently clamps these values to</div><div class='add'>+ * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the</div><div class='add'>+ * same pattern for sysfs, allow arbitrary PL1 limits to be set but display</div><div class='add'>+ * clamped values when read.</div><div class='add'>+ */</div><div class='add'>+static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val, min, max;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, &amp;reg_val, 0, 0);</div><div class='add'>+	/* Check if PL1 limit is disabled */</div><div class='add'>+	if (!(reg_val &amp; PKG_PWR_LIM_1_EN)) {</div><div class='add'>+		*value = PL1_DISABLE;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);</div><div class='add'>+	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon-&gt;scl_shift_power);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ64, &amp;reg_val, 0, 0);</div><div class='add'>+	min = REG_FIELD_GET(PKG_MIN_PWR, reg_val);</div><div class='add'>+	min = mul_u64_u32_shr(min, SF_POWER, hwmon-&gt;scl_shift_power);</div><div class='add'>+	max = REG_FIELD_GET(PKG_MAX_PWR, reg_val);</div><div class='add'>+	max = mul_u64_u32_shr(max, SF_POWER, hwmon-&gt;scl_shift_power);</div><div class='add'>+</div><div class='add'>+	if (min &amp;&amp; max)</div><div class='add'>+		*value = clamp_t(u64, *value, min, max);</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	/* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */</div><div class='add'>+	if (value == PL1_DISABLE) {</div><div class='add'>+		xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, &amp;reg_val,</div><div class='add'>+				     PKG_PWR_LIM_1_EN, 0);</div><div class='add'>+		xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ32, &amp;reg_val,</div><div class='add'>+				     PKG_PWR_LIM_1_EN, 0);</div><div class='add'>+</div><div class='add'>+		if (reg_val &amp; PKG_PWR_LIM_1_EN) {</div><div class='add'>+			ret = -EOPNOTSUPP;</div><div class='add'>+			goto unlock;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Computation in 64-bits to avoid overflow. Round to nearest. */</div><div class='add'>+	reg_val = DIV_ROUND_CLOSEST_ULL((u64)value &lt;&lt; hwmon-&gt;scl_shift_power, SF_POWER);</div><div class='add'>+	reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, &amp;reg_val,</div><div class='add'>+			     PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ32, &amp;reg_val, 0, 0);</div><div class='add'>+	reg_val = REG_FIELD_GET(PKG_TDP, reg_val);</div><div class='add'>+	*value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon-&gt;scl_shift_power);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * xe_hwmon_energy_get - Obtain energy value</div><div class='add'>+ *</div><div class='add'>+ * The underlying energy hardware register is 32-bits and is subject to</div><div class='add'>+ * overflow. How long before overflow? For example, with an example</div><div class='add'>+ * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and</div><div class='add'>+ * a power draw of 1000 watts, the 32-bit counter will overflow in</div><div class='add'>+ * approximately 4.36 minutes.</div><div class='add'>+ *</div><div class='add'>+ * Examples:</div><div class='add'>+ *    1 watt:  (2^32 &gt;&gt; 14) /    1 W / (60 * 60 * 24) secs/day -&gt; 3 days</div><div class='add'>+ * 1000 watts: (2^32 &gt;&gt; 14) / 1000 W / 60             secs/min -&gt; 4.36 minutes</div><div class='add'>+ *</div><div class='add'>+ * The function significantly increases overflow duration (from 4.36</div><div class='add'>+ * minutes) by accumulating the energy register into a 'long' as allowed by</div><div class='add'>+ * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),</div><div class='add'>+ * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and</div><div class='add'>+ * hwmon-&gt;scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before</div><div class='add'>+ * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon_energy_info *ei = &amp;hwmon-&gt;ei;</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ32,</div><div class='add'>+			     &amp;reg_val, 0, 0);</div><div class='add'>+</div><div class='add'>+	if (reg_val &gt;= ei-&gt;reg_val_prev)</div><div class='add'>+		ei-&gt;accum_energy += reg_val - ei-&gt;reg_val_prev;</div><div class='add'>+	else</div><div class='add'>+		ei-&gt;accum_energy += UINT_MAX - ei-&gt;reg_val_prev + reg_val;</div><div class='add'>+</div><div class='add'>+	ei-&gt;reg_val_prev = reg_val;</div><div class='add'>+</div><div class='add'>+	*energy = mul_u64_u32_shr(ei-&gt;accum_energy, SF_ENERGY,</div><div class='add'>+				  hwmon-&gt;scl_shift_energy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,</div><div class='add'>+				  char *buf)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = dev_get_drvdata(dev);</div><div class='add'>+	u32 x, y, x_w = 2; /* 2 bits */</div><div class='add'>+	u64 r, tau4, out;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,</div><div class='add'>+			     REG_READ32, &amp;r, 0, 0);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);</div><div class='add'>+	y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)</div><div class='add'>+	 *     = (4 | x) &lt;&lt; (y - 2)</div><div class='add'>+	 *</div><div class='add'>+	 * Here (y - 2) ensures a 1.x fixed point representation of 1.x</div><div class='add'>+	 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75</div><div class='add'>+	 *</div><div class='add'>+	 * As y can be &lt; 2, we compute tau4 = (4 | x) &lt;&lt; y</div><div class='add'>+	 * and then add 2 when doing the final right shift to account for units</div><div class='add'>+	 */</div><div class='add'>+	tau4 = ((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='add'>+</div><div class='add'>+	/* val in hwmon interface units (millisec) */</div><div class='add'>+	out = mul_u64_u32_shr(tau4, SF_TIME, hwmon-&gt;scl_shift_time + x_w);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%llu\n", out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t</div><div class='add'>+xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,</div><div class='add'>+				   const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = dev_get_drvdata(dev);</div><div class='add'>+	u32 x, y, rxy, x_w = 2; /* 2 bits */</div><div class='add'>+	u64 tau4, r, max_win;</div><div class='add'>+	unsigned long val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtoul(buf, 0, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12.</div><div class='add'>+	 * The hwmon-&gt;scl_shift_time default of 0xa results in a max tau of 256 seconds.</div><div class='add'>+	 *</div><div class='add'>+	 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register.</div><div class='add'>+	 * However, it is observed that existing discrete GPUs does not provide correct</div><div class='add'>+	 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs</div><div class='add'>+	 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU.</div><div class='add'>+	 */</div><div class='add'>+#define PKG_MAX_WIN_DEFAULT 0x12ull</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * val must be &lt; max in hwmon interface units. The steps below are</div><div class='add'>+	 * explained in xe_hwmon_power1_max_interval_show()</div><div class='add'>+	 */</div><div class='add'>+	r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);</div><div class='add'>+	x = REG_FIELD_GET(PKG_MAX_WIN_X, r);</div><div class='add'>+	y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);</div><div class='add'>+	tau4 = ((1 &lt;&lt; x_w) | x) &lt;&lt; y;</div><div class='add'>+	max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon-&gt;scl_shift_time + x_w);</div><div class='add'>+</div><div class='add'>+	if (val &gt; max_win)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* val in hw units */</div><div class='add'>+	val = DIV_ROUND_CLOSEST_ULL((u64)val &lt;&lt; hwmon-&gt;scl_shift_time, SF_TIME);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Convert val to 1.x * power(2,y)</div><div class='add'>+	 * y = ilog2(val)</div><div class='add'>+	 * x = (val - (1 &lt;&lt; y)) &gt;&gt; (y - 2)</div><div class='add'>+	 */</div><div class='add'>+	if (!val) {</div><div class='add'>+		y = 0;</div><div class='add'>+		x = 0;</div><div class='add'>+	} else {</div><div class='add'>+		y = ilog2(val);</div><div class='add'>+		x = (val - (1ul &lt;&lt; y)) &lt;&lt; x_w &gt;&gt; y;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW32, (u64 *)&amp;r,</div><div class='add'>+			     PKG_PWR_LIM_1_TIME, rxy);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,</div><div class='add'>+			  xe_hwmon_power1_max_interval_show,</div><div class='add'>+			  xe_hwmon_power1_max_interval_store, 0);</div><div class='add'>+</div><div class='add'>+static struct attribute *hwmon_attributes[] = {</div><div class='add'>+	&amp;sensor_dev_attr_power1_max_interval.dev_attr.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,</div><div class='add'>+					   struct attribute *attr, int index)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct xe_hwmon *hwmon = dev_get_drvdata(dev);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	if (attr == &amp;sensor_dev_attr_power1_max_interval.dev_attr.attr)</div><div class='add'>+		ret = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? attr-&gt;mode : 0;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct attribute_group hwmon_attrgroup = {</div><div class='add'>+	.attrs = hwmon_attributes,</div><div class='add'>+	.is_visible = xe_hwmon_attributes_visible,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute_group *hwmon_groups[] = {</div><div class='add'>+	&amp;hwmon_attrgroup,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwmon_channel_info *hwmon_info[] = {</div><div class='add'>+	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),</div><div class='add'>+	HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),</div><div class='add'>+	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),</div><div class='add'>+	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */</div><div class='add'>+static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval)</div><div class='add'>+{</div><div class='add'>+	/* Avoid Illegal Subcommand error */</div><div class='add'>+	if (gt_to_xe(gt)-&gt;info.platform == XE_DG2)</div><div class='add'>+		return -ENXIO;</div><div class='add'>+</div><div class='add'>+	return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,</div><div class='add'>+			     POWER_SETUP_SUBCOMMAND_READ_I1, 0),</div><div class='add'>+			     uval, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)</div><div class='add'>+{</div><div class='add'>+	return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,</div><div class='add'>+			      POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),</div><div class='add'>+			      uval);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, long *value, u32 scale_factor)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 uval;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	ret = xe_hwmon_pcode_read_i1(hwmon-&gt;gt, &amp;uval);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto unlock;</div><div class='add'>+</div><div class='add'>+	*value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),</div><div class='add'>+				 scale_factor, POWER_SETUP_I1_SHIFT);</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, long value, u32 scale_factor)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 uval;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+</div><div class='add'>+	uval = DIV_ROUND_CLOSEST_ULL(value &lt;&lt; POWER_SETUP_I1_SHIFT, scale_factor);</div><div class='add'>+	ret = xe_hwmon_pcode_write_i1(hwmon-&gt;gt, uval);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, long *value)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	xe_hwmon_process_reg(hwmon, REG_GT_PERF_STATUS,</div><div class='add'>+			     REG_READ32, &amp;reg_val, 0, 0);</div><div class='add'>+	/* HW register value in units of 2.5 millivolt */</div><div class='add'>+	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t</div><div class='add'>+xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)</div><div class='add'>+{</div><div class='add'>+	u32 uval;</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_power_max:</div><div class='add'>+		return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;</div><div class='add'>+	case hwmon_power_rated_max:</div><div class='add'>+		return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;</div><div class='add'>+	case hwmon_power_crit:</div><div class='add'>+		return (xe_hwmon_pcode_read_i1(hwmon-&gt;gt, &amp;uval) ||</div><div class='add'>+			!(uval &amp; POWER_SETUP_I1_WATTS)) ? 0 : 0644;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_power_max:</div><div class='add'>+		xe_hwmon_power_max_read(hwmon, val);</div><div class='add'>+		return 0;</div><div class='add'>+	case hwmon_power_rated_max:</div><div class='add'>+		xe_hwmon_power_rated_max_read(hwmon, val);</div><div class='add'>+		return 0;</div><div class='add'>+	case hwmon_power_crit:</div><div class='add'>+		return xe_hwmon_power_curr_crit_read(hwmon, val, SF_POWER);</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_power_max:</div><div class='add'>+		return xe_hwmon_power_max_write(hwmon, val);</div><div class='add'>+	case hwmon_power_crit:</div><div class='add'>+		return xe_hwmon_power_curr_crit_write(hwmon, val, SF_POWER);</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t</div><div class='add'>+xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr)</div><div class='add'>+{</div><div class='add'>+	u32 uval;</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_curr_crit:</div><div class='add'>+		return (xe_hwmon_pcode_read_i1(hwmon-&gt;gt, &amp;uval) ||</div><div class='add'>+			(uval &amp; POWER_SETUP_I1_WATTS)) ? 0 : 0644;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, long *val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_curr_crit:</div><div class='add'>+		return xe_hwmon_power_curr_crit_read(hwmon, val, SF_CURR);</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_curr_crit:</div><div class='add'>+		return xe_hwmon_power_curr_crit_write(hwmon, val, SF_CURR);</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t</div><div class='add'>+xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_in_input:</div><div class='add'>+		return xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS) ? 0444 : 0;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_in_input:</div><div class='add'>+		xe_hwmon_get_voltage(hwmon, val);</div><div class='add'>+		return 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t</div><div class='add'>+xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_energy_input:</div><div class='add'>+		return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)</div><div class='add'>+{</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_energy_input:</div><div class='add'>+		xe_hwmon_energy_get(hwmon, val);</div><div class='add'>+		return 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t</div><div class='add'>+xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,</div><div class='add'>+		    u32 attr, int channel)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_power:</div><div class='add'>+		ret = xe_hwmon_power_is_visible(hwmon, attr, channel);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_curr:</div><div class='add'>+		ret = xe_hwmon_curr_is_visible(hwmon, attr);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_in:</div><div class='add'>+		ret = xe_hwmon_in_is_visible(hwmon, attr);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_energy:</div><div class='add'>+		ret = xe_hwmon_energy_is_visible(hwmon, attr);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = 0;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,</div><div class='add'>+	      int channel, long *val)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_power:</div><div class='add'>+		ret = xe_hwmon_power_read(hwmon, attr, channel, val);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_curr:</div><div class='add'>+		ret = xe_hwmon_curr_read(hwmon, attr, val);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_in:</div><div class='add'>+		ret = xe_hwmon_in_read(hwmon, attr, val);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_energy:</div><div class='add'>+		ret = xe_hwmon_energy_read(hwmon, attr, val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,</div><div class='add'>+	       int channel, long val)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_power:</div><div class='add'>+		ret = xe_hwmon_power_write(hwmon, attr, channel, val);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_curr:</div><div class='add'>+		ret = xe_hwmon_curr_write(hwmon, attr, val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_put(gt_to_xe(hwmon-&gt;gt));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hwmon_ops hwmon_ops = {</div><div class='add'>+	.is_visible = xe_hwmon_is_visible,</div><div class='add'>+	.read = xe_hwmon_read,</div><div class='add'>+	.write = xe_hwmon_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwmon_chip_info hwmon_chip_info = {</div><div class='add'>+	.ops = &amp;hwmon_ops,</div><div class='add'>+	.info = hwmon_info,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_hwmon_get_preregistration_info(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = xe-&gt;hwmon;</div><div class='add'>+	long energy;</div><div class='add'>+	u64 val_sku_unit = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The contents of register PKG_POWER_SKU_UNIT do not change,</div><div class='add'>+	 * so read it once and store the shift values.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT)) {</div><div class='add'>+		xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT,</div><div class='add'>+				     REG_READ32, &amp;val_sku_unit, 0, 0);</div><div class='add'>+		hwmon-&gt;scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);</div><div class='add'>+		hwmon-&gt;scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);</div><div class='add'>+		hwmon-&gt;scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the</div><div class='add'>+	 * first value of the energy register read</div><div class='add'>+	 */</div><div class='add'>+	if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))</div><div class='add'>+		xe_hwmon_energy_get(hwmon, &amp;energy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_hwmon_mutex_destroy(void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_hwmon *hwmon = arg;</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_hwmon_register(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+	struct xe_hwmon *hwmon;</div><div class='add'>+</div><div class='add'>+	/* hwmon is available only for dGfx */</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);</div><div class='add'>+	if (!hwmon)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe-&gt;hwmon = hwmon;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;hwmon-&gt;hwmon_lock);</div><div class='add'>+	if (devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* primary GT to access device level properties */</div><div class='add'>+	hwmon-&gt;gt = xe-&gt;tiles[0].primary_gt;</div><div class='add'>+</div><div class='add'>+	xe_hwmon_get_preregistration_info(xe);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Register xe hwmon interface\n");</div><div class='add'>+</div><div class='add'>+	/*  hwmon_dev points to device hwmon&lt;i&gt; */</div><div class='add'>+	hwmon-&gt;hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon,</div><div class='add'>+								&amp;hwmon_chip_info,</div><div class='add'>+								hwmon_groups);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(hwmon-&gt;hwmon_dev)) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Failed to register xe hwmon (%pe)\n", hwmon-&gt;hwmon_dev);</div><div class='add'>+		xe-&gt;hwmon = NULL;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h<br/>new file mode 100644<br/>index 000000000000..c42a1de2cd7a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_hwmon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_hwmon.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_HWMON_H_</div><div class='add'>+#define _XE_HWMON_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+#if IS_REACHABLE(CONFIG_HWMON)</div><div class='add'>+void xe_hwmon_register(struct xe_device *xe);</div><div class='add'>+#else</div><div class='add'>+static inline void xe_hwmon_register(struct xe_device *xe) { };</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#endif /* _XE_HWMON_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c<br/>new file mode 100644<br/>index 000000000000..d1f5ba4bb745<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_irq.c</a></div><div class='hunk'>@@ -0,0 +1,666 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_irq.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/sched/clock.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_display.h"</div><div class='add'>+#include "xe_drv.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Interrupt registers for a unit are always consecutive and ordered</div><div class='add'>+ * ISR, IMR, IIR, IER.</div><div class='add'>+ */</div><div class='add'>+#define IMR(offset)				XE_REG(offset + 0x4)</div><div class='add'>+#define IIR(offset)				XE_REG(offset + 0x8)</div><div class='add'>+#define IER(offset)				XE_REG(offset + 0xc)</div><div class='add'>+</div><div class='add'>+static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	u32 val = xe_mmio_read32(mmio, reg);</div><div class='add'>+</div><div class='add'>+	if (val == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_WARN(&amp;gt_to_xe(mmio)-&gt;drm, 1,</div><div class='add'>+		 "Interrupt register 0x%x is not zero: 0x%08x\n",</div><div class='add'>+		 reg.addr, val);</div><div class='add'>+	xe_mmio_write32(mmio, reg, 0xffffffff);</div><div class='add'>+	xe_mmio_read32(mmio, reg);</div><div class='add'>+	xe_mmio_write32(mmio, reg, 0xffffffff);</div><div class='add'>+	xe_mmio_read32(mmio, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Unmask and enable the specified interrupts.  Does not check current state,</div><div class='add'>+ * so any bits not specified here will become masked and disabled.</div><div class='add'>+ */</div><div class='add'>+static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we're just enabling an interrupt now, it shouldn't already</div><div class='add'>+	 * be raised in the IIR.</div><div class='add'>+	 */</div><div class='add'>+	assert_iir_is_zero(mmio, IIR(irqregs));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, IER(irqregs), bits);</div><div class='add'>+	xe_mmio_write32(mmio, IMR(irqregs), ~bits);</div><div class='add'>+</div><div class='add'>+	/* Posting read */</div><div class='add'>+	xe_mmio_read32(mmio, IMR(irqregs));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Mask and disable all interrupts. */</div><div class='add'>+static void mask_and_disable(struct xe_tile *tile, u32 irqregs)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, IMR(irqregs), ~0);</div><div class='add'>+	/* Posting read */</div><div class='add'>+	xe_mmio_read32(mmio, IMR(irqregs));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, IER(irqregs), 0);</div><div class='add'>+</div><div class='add'>+	/* IIR can theoretically queue up two events. Be paranoid. */</div><div class='add'>+	xe_mmio_write32(mmio, IIR(irqregs), ~0);</div><div class='add'>+	xe_mmio_read32(mmio, IIR(irqregs));</div><div class='add'>+	xe_mmio_write32(mmio, IIR(irqregs), ~0);</div><div class='add'>+	xe_mmio_read32(mmio, IIR(irqregs));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 xelp_intr_disable(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Now with master disabled, get a sample of level indications</div><div class='add'>+	 * for this interrupt. Indications will be cleared on related acks.</div><div class='add'>+	 * New indications can and will light up during processing,</div><div class='add'>+	 * and will generate new interrupt after enabling master.</div><div class='add'>+	 */</div><div class='add'>+	return xe_mmio_read32(mmio, GFX_MSTR_IRQ);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32</div><div class='add'>+gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+	u32 iir;</div><div class='add'>+</div><div class='add'>+	if (!(master_ctl &amp; GU_MISC_IRQ))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));</div><div class='add'>+	if (likely(iir))</div><div class='add'>+		xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);</div><div class='add'>+</div><div class='add'>+	return iir;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xelp_intr_enable(struct xe_device *xe, bool stall)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);</div><div class='add'>+	if (stall)</div><div class='add'>+		xe_mmio_read32(mmio, GFX_MSTR_IRQ);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable/unmask the HWE interrupts for a specific GT's engines. */</div><div class='add'>+void xe_irq_enable_hwe(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 ccs_mask, bcs_mask;</div><div class='add'>+	u32 irqs, dmask, smask;</div><div class='add'>+	u32 gsc_mask = 0;</div><div class='add'>+</div><div class='add'>+	if (xe_device_uc_enabled(xe)) {</div><div class='add'>+		irqs = GT_RENDER_USER_INTERRUPT |</div><div class='add'>+			GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;</div><div class='add'>+	} else {</div><div class='add'>+		irqs = GT_RENDER_USER_INTERRUPT |</div><div class='add'>+		       GT_CS_MASTER_ERROR_INTERRUPT |</div><div class='add'>+		       GT_CONTEXT_SWITCH_INTERRUPT |</div><div class='add'>+		       GT_WAIT_SEMAPHORE_INTERRUPT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);</div><div class='add'>+	bcs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);</div><div class='add'>+</div><div class='add'>+	dmask = irqs &lt;&lt; 16 | irqs;</div><div class='add'>+	smask = irqs &lt;&lt; 16;</div><div class='add'>+</div><div class='add'>+	if (!xe_gt_is_media_type(gt)) {</div><div class='add'>+		/* Enable interrupts for each engine class */</div><div class='add'>+		xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);</div><div class='add'>+		if (ccs_mask)</div><div class='add'>+			xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);</div><div class='add'>+</div><div class='add'>+		/* Unmask interrupts for each engine instance */</div><div class='add'>+		xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);</div><div class='add'>+		xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);</div><div class='add'>+		if (bcs_mask &amp; (BIT(1)|BIT(2)))</div><div class='add'>+			xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);</div><div class='add'>+		if (bcs_mask &amp; (BIT(3)|BIT(4)))</div><div class='add'>+			xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);</div><div class='add'>+		if (bcs_mask &amp; (BIT(5)|BIT(6)))</div><div class='add'>+			xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);</div><div class='add'>+		if (bcs_mask &amp; (BIT(7)|BIT(8)))</div><div class='add'>+			xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);</div><div class='add'>+		if (ccs_mask &amp; (BIT(0)|BIT(1)))</div><div class='add'>+			xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);</div><div class='add'>+		if (ccs_mask &amp; (BIT(2)|BIT(3)))</div><div class='add'>+			xe_mmio_write32(gt,  CCS2_CCS3_INTR_MASK, ~dmask);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) &lt; 13) {</div><div class='add'>+		/* Enable interrupts for each engine class */</div><div class='add'>+		xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);</div><div class='add'>+</div><div class='add'>+		/* Unmask interrupts for each engine instance */</div><div class='add'>+		xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);</div><div class='add'>+		xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);</div><div class='add'>+		xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);</div><div class='add'>+</div><div class='add'>+		if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER))</div><div class='add'>+			gsc_mask = irqs;</div><div class='add'>+		else if (HAS_HECI_GSCFI(xe))</div><div class='add'>+			gsc_mask = GSC_IRQ_INTF(1);</div><div class='add'>+		if (gsc_mask) {</div><div class='add'>+			xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask);</div><div class='add'>+			xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32</div><div class='add'>+gt_engine_identity(struct xe_device *xe,</div><div class='add'>+		   struct xe_gt *mmio,</div><div class='add'>+		   const unsigned int bank,</div><div class='add'>+		   const unsigned int bit)</div><div class='add'>+{</div><div class='add'>+	u32 timeout_ts;</div><div class='add'>+	u32 ident;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;xe-&gt;irq.lock);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * NB: Specs do not specify how long to spin wait,</div><div class='add'>+	 * so we do ~100us as an educated guess.</div><div class='add'>+	 */</div><div class='add'>+	timeout_ts = (local_clock() &gt;&gt; 10) + 100;</div><div class='add'>+	do {</div><div class='add'>+		ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));</div><div class='add'>+	} while (!(ident &amp; INTR_DATA_VALID) &amp;&amp;</div><div class='add'>+		 !time_after32(local_clock() &gt;&gt; 10, timeout_ts));</div><div class='add'>+</div><div class='add'>+	if (unlikely(!(ident &amp; INTR_DATA_VALID))) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",</div><div class='add'>+			bank, bit, ident);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident);</div><div class='add'>+</div><div class='add'>+	return ident;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define   OTHER_MEDIA_GUC_INSTANCE           16</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+gt_other_irq_handler(struct xe_gt *gt, const u8 instance, const u16 iir)</div><div class='add'>+{</div><div class='add'>+	if (instance == OTHER_GUC_INSTANCE &amp;&amp; !xe_gt_is_media_type(gt))</div><div class='add'>+		return xe_guc_irq_handler(&amp;gt-&gt;uc.guc, iir);</div><div class='add'>+	if (instance == OTHER_MEDIA_GUC_INSTANCE &amp;&amp; xe_gt_is_media_type(gt))</div><div class='add'>+		return xe_guc_irq_handler(&amp;gt-&gt;uc.guc, iir);</div><div class='add'>+</div><div class='add'>+	if (instance != OTHER_GUC_INSTANCE &amp;&amp;</div><div class='add'>+	    instance != OTHER_MEDIA_GUC_INSTANCE) {</div><div class='add'>+		WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",</div><div class='add'>+			  instance, iir);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *pick_engine_gt(struct xe_tile *tile,</div><div class='add'>+				    enum xe_engine_class class,</div><div class='add'>+				    unsigned int instance)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+</div><div class='add'>+	if (MEDIA_VER(xe) &lt; 13)</div><div class='add'>+		return tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	if (class == XE_ENGINE_CLASS_VIDEO_DECODE ||</div><div class='add'>+	    class == XE_ENGINE_CLASS_VIDEO_ENHANCE)</div><div class='add'>+		return tile-&gt;media_gt;</div><div class='add'>+</div><div class='add'>+	if (class == XE_ENGINE_CLASS_OTHER &amp;&amp;</div><div class='add'>+	    (instance == OTHER_MEDIA_GUC_INSTANCE || instance == OTHER_GSC_INSTANCE))</div><div class='add'>+		return tile-&gt;media_gt;</div><div class='add'>+</div><div class='add'>+	return tile-&gt;primary_gt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gt_irq_handler(struct xe_tile *tile,</div><div class='add'>+			   u32 master_ctl, unsigned long *intr_dw,</div><div class='add'>+			   u32 *identity)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+	unsigned int bank, bit;</div><div class='add'>+	u16 instance, intr_vec;</div><div class='add'>+	enum xe_engine_class class;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;irq.lock);</div><div class='add'>+</div><div class='add'>+	for (bank = 0; bank &lt; 2; bank++) {</div><div class='add'>+		if (!(master_ctl &amp; GT_DW_IRQ(bank)))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));</div><div class='add'>+		for_each_set_bit(bit, intr_dw + bank, 32)</div><div class='add'>+			identity[bit] = gt_engine_identity(xe, mmio, bank, bit);</div><div class='add'>+		xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);</div><div class='add'>+</div><div class='add'>+		for_each_set_bit(bit, intr_dw + bank, 32) {</div><div class='add'>+			struct xe_gt *engine_gt;</div><div class='add'>+</div><div class='add'>+			class = INTR_ENGINE_CLASS(identity[bit]);</div><div class='add'>+			instance = INTR_ENGINE_INSTANCE(identity[bit]);</div><div class='add'>+			intr_vec = INTR_ENGINE_INTR(identity[bit]);</div><div class='add'>+</div><div class='add'>+			engine_gt = pick_engine_gt(tile, class, instance);</div><div class='add'>+</div><div class='add'>+			hwe = xe_gt_hw_engine(engine_gt, class, instance, false);</div><div class='add'>+			if (hwe) {</div><div class='add'>+				xe_hw_engine_handle_irq(hwe, intr_vec);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (class == XE_ENGINE_CLASS_OTHER) {</div><div class='add'>+				/* HECI GSCFI interrupts come from outside of GT */</div><div class='add'>+				if (HAS_HECI_GSCFI(xe) &amp;&amp; instance == OTHER_GSC_INSTANCE)</div><div class='add'>+					xe_heci_gsc_irq_handler(xe, intr_vec);</div><div class='add'>+				else</div><div class='add'>+					gt_other_irq_handler(engine_gt, instance, intr_vec);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;xe-&gt;irq.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Top-level interrupt handler for Xe_LP platforms (which did not have</div><div class='add'>+ * a "master tile" interrupt register.</div><div class='add'>+ */</div><div class='add'>+static irqreturn_t xelp_irq_handler(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+	struct xe_tile *tile = xe_device_get_root_tile(xe);</div><div class='add'>+	u32 master_ctl, gu_misc_iir;</div><div class='add'>+	unsigned long intr_dw[2];</div><div class='add'>+	u32 identity[32];</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;irq.lock);</div><div class='add'>+	if (!xe-&gt;irq.enabled) {</div><div class='add'>+		spin_unlock(&amp;xe-&gt;irq.lock);</div><div class='add'>+		return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;xe-&gt;irq.lock);</div><div class='add'>+</div><div class='add'>+	master_ctl = xelp_intr_disable(xe);</div><div class='add'>+	if (!master_ctl) {</div><div class='add'>+		xelp_intr_enable(xe, false);</div><div class='add'>+		return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt_irq_handler(tile, master_ctl, intr_dw, identity);</div><div class='add'>+</div><div class='add'>+	xe_display_irq_handler(xe, master_ctl);</div><div class='add'>+</div><div class='add'>+	gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);</div><div class='add'>+</div><div class='add'>+	xelp_intr_enable(xe, false);</div><div class='add'>+</div><div class='add'>+	xe_display_irq_enable(xe, gu_misc_iir);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 dg1_intr_disable(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	/* First disable interrupts */</div><div class='add'>+	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);</div><div class='add'>+</div><div class='add'>+	/* Get the indication levels and ack the master unit */</div><div class='add'>+	val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);</div><div class='add'>+	if (unlikely(!val))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dg1_intr_enable(struct xe_device *xe, bool stall)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);</div><div class='add'>+	if (stall)</div><div class='add'>+		xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Top-level interrupt handler for Xe_LP+ and beyond.  These platforms have</div><div class='add'>+ * a "master tile" interrupt register which must be consulted before the</div><div class='add'>+ * "graphics master" interrupt register.</div><div class='add'>+ */</div><div class='add'>+static irqreturn_t dg1_irq_handler(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u32 master_tile_ctl, master_ctl = 0, gu_misc_iir = 0;</div><div class='add'>+	unsigned long intr_dw[2];</div><div class='add'>+	u32 identity[32];</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	/* TODO: This really shouldn't be copied+pasted */</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;xe-&gt;irq.lock);</div><div class='add'>+	if (!xe-&gt;irq.enabled) {</div><div class='add'>+		spin_unlock(&amp;xe-&gt;irq.lock);</div><div class='add'>+		return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;xe-&gt;irq.lock);</div><div class='add'>+</div><div class='add'>+	master_tile_ctl = dg1_intr_disable(xe);</div><div class='add'>+	if (!master_tile_ctl) {</div><div class='add'>+		dg1_intr_enable(xe, false);</div><div class='add'>+		return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+		if ((master_tile_ctl &amp; DG1_MSTR_TILE(tile-&gt;id)) == 0)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * We might be in irq handler just when PCIe DPC is initiated</div><div class='add'>+		 * and all MMIO reads will be returned with all 1's. Ignore this</div><div class='add'>+		 * irq as device is inaccessible.</div><div class='add'>+		 */</div><div class='add'>+		if (master_ctl == REG_GENMASK(31, 0)) {</div><div class='add'>+			dev_dbg(tile_to_xe(tile)-&gt;drm.dev,</div><div class='add'>+				"Ignore this IRQ as device might be in DPC containment.\n");</div><div class='add'>+			return IRQ_HANDLED;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);</div><div class='add'>+</div><div class='add'>+		gt_irq_handler(tile, master_ctl, intr_dw, identity);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Display interrupts (including display backlight operations</div><div class='add'>+		 * that get reported as Gunit GSE) would only be hooked up to</div><div class='add'>+		 * the primary tile.</div><div class='add'>+		 */</div><div class='add'>+		if (id == 0) {</div><div class='add'>+			xe_display_irq_handler(xe, master_ctl);</div><div class='add'>+			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dg1_intr_enable(xe, false);</div><div class='add'>+	xe_display_irq_enable(xe, gu_misc_iir);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gt_irq_reset(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	u32 ccs_mask = xe_hw_engine_mask_per_class(tile-&gt;primary_gt,</div><div class='add'>+						   XE_ENGINE_CLASS_COMPUTE);</div><div class='add'>+	u32 bcs_mask = xe_hw_engine_mask_per_class(tile-&gt;primary_gt,</div><div class='add'>+						   XE_ENGINE_CLASS_COPY);</div><div class='add'>+</div><div class='add'>+	/* Disable RCS, BCS, VCS and VECS class engines. */</div><div class='add'>+	xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);</div><div class='add'>+	xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);</div><div class='add'>+	if (ccs_mask)</div><div class='add'>+		xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);</div><div class='add'>+</div><div class='add'>+	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */</div><div class='add'>+	xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK,	~0);</div><div class='add'>+	xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK,	~0);</div><div class='add'>+	if (bcs_mask &amp; (BIT(1)|BIT(2)))</div><div class='add'>+		xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);</div><div class='add'>+	if (bcs_mask &amp; (BIT(3)|BIT(4)))</div><div class='add'>+		xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);</div><div class='add'>+	if (bcs_mask &amp; (BIT(5)|BIT(6)))</div><div class='add'>+		xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);</div><div class='add'>+	if (bcs_mask &amp; (BIT(7)|BIT(8)))</div><div class='add'>+		xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);</div><div class='add'>+	xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK,	~0);</div><div class='add'>+	xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK,	~0);</div><div class='add'>+	xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK,	~0);</div><div class='add'>+	if (ccs_mask &amp; (BIT(0)|BIT(1)))</div><div class='add'>+		xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);</div><div class='add'>+	if (ccs_mask &amp; (BIT(2)|BIT(3)))</div><div class='add'>+		xe_mmio_write32(mmio,  CCS2_CCS3_INTR_MASK, ~0);</div><div class='add'>+</div><div class='add'>+	if ((tile-&gt;media_gt &amp;&amp;</div><div class='add'>+	     xe_hw_engine_mask_per_class(tile-&gt;media_gt, XE_ENGINE_CLASS_OTHER)) ||</div><div class='add'>+	    HAS_HECI_GSCFI(tile_to_xe(tile))) {</div><div class='add'>+		xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0);</div><div class='add'>+		xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);</div><div class='add'>+	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK,  ~0);</div><div class='add'>+	xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE,	 0);</div><div class='add'>+	xe_mmio_write32(mmio, GUC_SG_INTR_MASK,		~0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xelp_irq_reset(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	xelp_intr_disable(tile_to_xe(tile));</div><div class='add'>+</div><div class='add'>+	gt_irq_reset(tile);</div><div class='add'>+</div><div class='add'>+	mask_and_disable(tile, PCU_IRQ_OFFSET);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dg1_irq_reset(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	if (tile-&gt;id == 0)</div><div class='add'>+		dg1_intr_disable(tile_to_xe(tile));</div><div class='add'>+</div><div class='add'>+	gt_irq_reset(tile);</div><div class='add'>+</div><div class='add'>+	mask_and_disable(tile, PCU_IRQ_OFFSET);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dg1_irq_reset_mstr(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_irq_reset(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (GRAPHICS_VERx100(xe) &gt;= 1210)</div><div class='add'>+			dg1_irq_reset(tile);</div><div class='add'>+		else</div><div class='add'>+			xelp_irq_reset(tile);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tile = xe_device_get_root_tile(xe);</div><div class='add'>+	mask_and_disable(tile, GU_MISC_IRQ_OFFSET);</div><div class='add'>+	xe_display_irq_reset(xe);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The tile's top-level status register should be the last one</div><div class='add'>+	 * to be reset to avoid possible bit re-latching from lower</div><div class='add'>+	 * level interrupts.</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1210) {</div><div class='add'>+		for_each_tile(tile, xe, id)</div><div class='add'>+			dg1_irq_reset_mstr(tile);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_irq_postinstall(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xe_display_irq_postinstall(xe, xe_root_mmio_gt(xe));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * ASLE backlight operations are reported via GUnit GSE interrupts</div><div class='add'>+	 * on the root tile.</div><div class='add'>+	 */</div><div class='add'>+	unmask_and_enable(xe_device_get_root_tile(xe),</div><div class='add'>+			  GU_MISC_IRQ_OFFSET, GU_MISC_GSE);</div><div class='add'>+</div><div class='add'>+	/* Enable top-level interrupts */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1210)</div><div class='add'>+		dg1_intr_enable(xe, true);</div><div class='add'>+	else</div><div class='add'>+		xelp_intr_enable(xe, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irq_handler_t xe_irq_handler(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1210)</div><div class='add'>+		return dg1_irq_handler;</div><div class='add'>+	else</div><div class='add'>+		return xelp_irq_handler;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void irq_uninstall(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	int irq;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;irq.enabled)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe-&gt;irq.enabled = false;</div><div class='add'>+	xe_irq_reset(xe);</div><div class='add'>+</div><div class='add'>+	irq = pci_irq_vector(pdev, 0);</div><div class='add'>+	free_irq(irq, xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_irq_install(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	irq_handler_t irq_handler;</div><div class='add'>+	int err, irq;</div><div class='add'>+</div><div class='add'>+	irq_handler = xe_irq_handler(xe);</div><div class='add'>+	if (!irq_handler) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "No supported interrupt handler");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_irq_reset(xe);</div><div class='add'>+</div><div class='add'>+	err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);</div><div class='add'>+	if (err &lt; 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "MSI/MSIX: Failed to enable support %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	irq = pci_irq_vector(pdev, 0);</div><div class='add'>+	err = request_irq(irq, irq_handler, IRQF_SHARED, DRIVER_NAME, xe);</div><div class='add'>+	if (err &lt; 0) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Failed to request MSI/MSIX IRQ %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe-&gt;irq.enabled = true;</div><div class='add'>+</div><div class='add'>+	xe_irq_postinstall(xe);</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, irq_uninstall, xe);</div><div class='add'>+	if (err)</div><div class='add'>+		goto free_irq_handler;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_irq_handler:</div><div class='add'>+	free_irq(irq, xe);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_irq_shutdown(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	irq_uninstall(&amp;xe-&gt;drm, xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_irq_suspend(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	int irq = to_pci_dev(xe-&gt;drm.dev)-&gt;irq;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;xe-&gt;irq.lock);</div><div class='add'>+	xe-&gt;irq.enabled = false; /* no new irqs */</div><div class='add'>+	spin_unlock_irq(&amp;xe-&gt;irq.lock);</div><div class='add'>+</div><div class='add'>+	synchronize_irq(irq); /* flush irqs */</div><div class='add'>+	xe_irq_reset(xe); /* turn irqs off */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_irq_resume(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * lock not needed:</div><div class='add'>+	 * 1. no irq will arrive before the postinstall</div><div class='add'>+	 * 2. display is not yet resumed</div><div class='add'>+	 */</div><div class='add'>+	xe-&gt;irq.enabled = true;</div><div class='add'>+	xe_irq_reset(xe);</div><div class='add'>+	xe_irq_postinstall(xe); /* turn irqs on */</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_irq_enable_hwe(gt);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h<br/>new file mode 100644<br/>index 000000000000..bc42bc90d967<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_irq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_irq.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_IRQ_H_</div><div class='add'>+#define _XE_IRQ_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_tile;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+int xe_irq_install(struct xe_device *xe);</div><div class='add'>+void xe_irq_shutdown(struct xe_device *xe);</div><div class='add'>+void xe_irq_suspend(struct xe_device *xe);</div><div class='add'>+void xe_irq_resume(struct xe_device *xe);</div><div class='add'>+void xe_irq_enable_hwe(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c<br/>new file mode 100644<br/>index 000000000000..0d7c5514e092<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lmtt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt.c</a></div><div class='hunk'>@@ -0,0 +1,506 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_sriov_regs.h"</div><div class='add'>+</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_lmtt.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_sriov.h"</div><div class='add'>+#include "xe_sriov_printk.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Local Memory Translation Table</div><div class='add'>+ *</div><div class='add'>+ * The Local Memory Translation Table (LMTT) provides additional abstraction</div><div class='add'>+ * when Virtual Function (VF) is accessing device Local Memory (VRAM).</div><div class='add'>+ *</div><div class='add'>+ * The Root LMTT Page Directory contains one entry for each VF. Entries are</div><div class='add'>+ * indexed by the function number (1-based, index 0 is unused).</div><div class='add'>+ *</div><div class='add'>+ * See `Two-Level LMTT Structure`_ and `Multi-Level LMTT Structure`_.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define lmtt_assert(lmtt, condition)	xe_tile_assert(lmtt_to_tile(lmtt), condition)</div><div class='add'>+#define lmtt_debug(lmtt, msg...)	xe_sriov_dbg_verbose(lmtt_to_xe(lmtt), "LMTT: " msg)</div><div class='add'>+</div><div class='add'>+static bool xe_has_multi_level_lmtt(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;info.platform == XE_PVC;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_tile *lmtt_to_tile(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	return container_of(lmtt, struct xe_tile, sriov.pf.lmtt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *lmtt_to_xe(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	return tile_to_xe(lmtt_to_tile(lmtt));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 lmtt_page_size(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	return BIT_ULL(lmtt-&gt;ops-&gt;lmtt_pte_shift(0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_lmtt_pt *lmtt_pt_alloc(struct xe_lmtt *lmtt, unsigned int level)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_entries = level ? lmtt-&gt;ops-&gt;lmtt_pte_num(level) : 0;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	pt = kzalloc(struct_size(pt, entries, num_entries), GFP_KERNEL);</div><div class='add'>+	if (!pt) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(lmtt_to_xe(lmtt), lmtt_to_tile(lmtt), NULL,</div><div class='add'>+				  PAGE_ALIGN(lmtt-&gt;ops-&gt;lmtt_pte_size(level) *</div><div class='add'>+					     lmtt-&gt;ops-&gt;lmtt_pte_num(level)),</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_VRAM_IF_DGFX(lmtt_to_tile(lmtt)) |</div><div class='add'>+				  XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		err = PTR_ERR(bo);</div><div class='add'>+		goto out_free_pt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, xe_bo_is_vram(bo));</div><div class='add'>+</div><div class='add'>+	pt-&gt;level = level;</div><div class='add'>+	pt-&gt;bo = bo;</div><div class='add'>+	return pt;</div><div class='add'>+</div><div class='add'>+out_free_pt:</div><div class='add'>+	kfree(pt);</div><div class='add'>+out:</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_pt_free(struct xe_lmtt_pt *pt)</div><div class='add'>+{</div><div class='add'>+	xe_bo_unpin_map_no_vm(pt-&gt;bo);</div><div class='add'>+	kfree(pt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int lmtt_init_pd(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt_pt *pd;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, !lmtt-&gt;pd);</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;ops-&gt;lmtt_root_pd_level());</div><div class='add'>+</div><div class='add'>+	pd = lmtt_pt_alloc(lmtt, lmtt-&gt;ops-&gt;lmtt_root_pd_level());</div><div class='add'>+	if (IS_ERR(pd))</div><div class='add'>+		return PTR_ERR(pd);</div><div class='add'>+</div><div class='add'>+	lmtt-&gt;pd = pd;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_fini_pd(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt_pt *pd = lmtt-&gt;pd;</div><div class='add'>+	unsigned int num_entries = lmtt-&gt;ops-&gt;lmtt_pte_num(pd-&gt;level);</div><div class='add'>+	unsigned int n = 0;</div><div class='add'>+</div><div class='add'>+	/* make sure we don't leak */</div><div class='add'>+	for (n = 0; n &lt; num_entries; n++)</div><div class='add'>+		lmtt_assert(lmtt, !pd-&gt;entries[n]);</div><div class='add'>+</div><div class='add'>+	lmtt-&gt;pd = NULL;</div><div class='add'>+	lmtt_pt_free(pd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void fini_lmtt(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt *lmtt = arg;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, !(!!lmtt-&gt;ops ^ !!lmtt-&gt;pd));</div><div class='add'>+</div><div class='add'>+	if (!lmtt-&gt;pd)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	lmtt_fini_pd(lmtt);</div><div class='add'>+	lmtt-&gt;ops = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_init - LMTT software initialization.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt to initialize</div><div class='add'>+ *</div><div class='add'>+ * The LMTT initialization requires two steps.</div><div class='add'>+ *</div><div class='add'>+ * The xe_lmtt_init() checks if LMTT is required on current device and selects</div><div class='add'>+ * and initialize proper variant of the LMTT Root Directory. Currently supported</div><div class='add'>+ * variants are `Two-Level LMTT Structure`_ and `Multi-Level LMTT Structure`_.</div><div class='add'>+ *</div><div class='add'>+ * In next step xe_lmtt_init_hw() will register this directory on the hardware.</div><div class='add'>+ *</div><div class='add'>+ * Notes:</div><div class='add'>+ * The LMTT allocations are managed and will be implicitly released on driver unload.</div><div class='add'>+ * This function shall be called only once and only when running as a PF driver.</div><div class='add'>+ * Any LMTT initialization failure should block VFs enabling.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_lmtt_init(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = lmtt_to_xe(lmtt);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, IS_SRIOV_PF(xe));</div><div class='add'>+	lmtt_assert(lmtt, !lmtt-&gt;ops);</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (xe_has_multi_level_lmtt(xe))</div><div class='add'>+		lmtt-&gt;ops = &amp;lmtt_ml_ops;</div><div class='add'>+	else</div><div class='add'>+		lmtt-&gt;ops = &amp;lmtt_2l_ops;</div><div class='add'>+</div><div class='add'>+	err = lmtt_init_pd(lmtt);</div><div class='add'>+	if (unlikely(err))</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, fini_lmtt, lmtt);</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	lmtt-&gt;ops = NULL;</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_setup_dir_ptr(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = lmtt_to_tile(lmtt);</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	dma_addr_t offset = xe_bo_main_addr(lmtt-&gt;pd-&gt;bo, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	lmtt_debug(lmtt, "DIR offset %pad\n", &amp;offset);</div><div class='add'>+	lmtt_assert(lmtt, xe_bo_is_vram(lmtt-&gt;pd-&gt;bo));</div><div class='add'>+	lmtt_assert(lmtt, IS_ALIGNED(offset, SZ_64K));</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(tile-&gt;primary_gt,</div><div class='add'>+			GRAPHICS_VER(xe) &gt;= 20 ? XE2_LMEM_CFG : LMEM_CFG,</div><div class='add'>+			LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_init_hw - Perform LMTT hardware initialization.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt to initialize</div><div class='add'>+ *</div><div class='add'>+ * This function is a second step of the LMTT initialization.</div><div class='add'>+ * This function registers LMTT Root Directory prepared in xe_lmtt_init().</div><div class='add'>+ *</div><div class='add'>+ * This function shall be called after every hardware reset.</div><div class='add'>+ * This function shall be called only when running as a PF driver.</div><div class='add'>+ */</div><div class='add'>+void xe_lmtt_init_hw(struct xe_lmtt *lmtt)</div><div class='add'>+{</div><div class='add'>+	if (!lmtt-&gt;pd)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	lmtt_setup_dir_ptr(lmtt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_write_pte(struct xe_lmtt *lmtt, struct xe_lmtt_pt *pt,</div><div class='add'>+			   u64 pte, unsigned int idx)</div><div class='add'>+{</div><div class='add'>+	unsigned int level = pt-&gt;level;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, idx &lt;= lmtt-&gt;ops-&gt;lmtt_pte_num(level));</div><div class='add'>+	lmtt_debug(lmtt, "WRITE level=%u index=%u pte=%#llx\n", level, idx, pte);</div><div class='add'>+</div><div class='add'>+	switch (lmtt-&gt;ops-&gt;lmtt_pte_size(level)) {</div><div class='add'>+	case sizeof(u32):</div><div class='add'>+		xe_map_wr(lmtt_to_xe(lmtt), &amp;pt-&gt;bo-&gt;vmap, idx * sizeof(u32), u32, pte);</div><div class='add'>+		break;</div><div class='add'>+	case sizeof(u64):</div><div class='add'>+		xe_map_wr(lmtt_to_xe(lmtt), &amp;pt-&gt;bo-&gt;vmap, idx * sizeof(u64), u64, pte);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		lmtt_assert(lmtt, !!!"invalid pte size");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_destroy_pt(struct xe_lmtt *lmtt, struct xe_lmtt_pt *pd)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_entries = pd-&gt;level ? lmtt-&gt;ops-&gt;lmtt_pte_num(pd-&gt;level) : 0;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		pt = pd-&gt;entries[i];</div><div class='add'>+		pd-&gt;entries[i] = NULL;</div><div class='add'>+		if (!pt)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		lmtt_destroy_pt(lmtt, pt);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lmtt_pt_free(pd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_drop_pages(struct xe_lmtt *lmtt, unsigned int vfid)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt_pt *pd = lmtt-&gt;pd;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+</div><div class='add'>+	pt = pd-&gt;entries[vfid];</div><div class='add'>+	pd-&gt;entries[vfid] = NULL;</div><div class='add'>+	if (!pt)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	lmtt_write_pte(lmtt, pd, LMTT_PTE_INVALID, vfid);</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, pd-&gt;level &gt; 0);</div><div class='add'>+	lmtt_assert(lmtt, pt-&gt;level == pd-&gt;level - 1);</div><div class='add'>+	lmtt_destroy_pt(lmtt, pt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __lmtt_alloc_range(struct xe_lmtt *lmtt, struct xe_lmtt_pt *pd,</div><div class='add'>+			      u64 start, u64 end)</div><div class='add'>+{</div><div class='add'>+	u64 pte_addr_shift = BIT_ULL(lmtt-&gt;ops-&gt;lmtt_pte_shift(pd-&gt;level));</div><div class='add'>+	u64 offset;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, pd-&gt;level &gt; 0);</div><div class='add'>+</div><div class='add'>+	offset = start;</div><div class='add'>+	while (offset &lt; end) {</div><div class='add'>+		struct xe_lmtt_pt *pt;</div><div class='add'>+		u64 next, pde, pt_addr;</div><div class='add'>+		unsigned int idx;</div><div class='add'>+</div><div class='add'>+		pt = lmtt_pt_alloc(lmtt, pd-&gt;level - 1);</div><div class='add'>+		if (IS_ERR(pt))</div><div class='add'>+			return PTR_ERR(pt);</div><div class='add'>+</div><div class='add'>+		pt_addr = xe_bo_main_addr(pt-&gt;bo, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+		idx = lmtt-&gt;ops-&gt;lmtt_pte_index(offset, pd-&gt;level);</div><div class='add'>+		pde = lmtt-&gt;ops-&gt;lmtt_pte_encode(pt_addr, pd-&gt;level);</div><div class='add'>+</div><div class='add'>+		lmtt_write_pte(lmtt, pd, pde, idx);</div><div class='add'>+</div><div class='add'>+		pd-&gt;entries[idx] = pt;</div><div class='add'>+</div><div class='add'>+		next = min(end, round_up(offset + 1, pte_addr_shift));</div><div class='add'>+</div><div class='add'>+		if (pt-&gt;level != 0) {</div><div class='add'>+			err = __lmtt_alloc_range(lmtt, pt, offset, next);</div><div class='add'>+			if (err)</div><div class='add'>+				return err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		offset = next;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int lmtt_alloc_range(struct xe_lmtt *lmtt, unsigned int vfid, u64 start, u64 end)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt_pt *pd = lmtt-&gt;pd;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+	u64 pt_addr;</div><div class='add'>+	u64 pde;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, pd-&gt;level &gt; 0);</div><div class='add'>+	lmtt_assert(lmtt, vfid &lt;= lmtt-&gt;ops-&gt;lmtt_pte_num(pd-&gt;level));</div><div class='add'>+	lmtt_assert(lmtt, IS_ALIGNED(start, lmtt_page_size(lmtt)));</div><div class='add'>+	lmtt_assert(lmtt, IS_ALIGNED(end, lmtt_page_size(lmtt)));</div><div class='add'>+</div><div class='add'>+	if (pd-&gt;entries[vfid])</div><div class='add'>+		return -ENOTEMPTY;</div><div class='add'>+</div><div class='add'>+	pt = lmtt_pt_alloc(lmtt, pd-&gt;level - 1);</div><div class='add'>+	if (IS_ERR(pt))</div><div class='add'>+		return PTR_ERR(pt);</div><div class='add'>+</div><div class='add'>+	pt_addr = xe_bo_main_addr(pt-&gt;bo, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	pde = lmtt-&gt;ops-&gt;lmtt_pte_encode(pt_addr, pd-&gt;level);</div><div class='add'>+</div><div class='add'>+	lmtt_write_pte(lmtt, pd, pde, vfid);</div><div class='add'>+</div><div class='add'>+	pd-&gt;entries[vfid] = pt;</div><div class='add'>+</div><div class='add'>+	if (pt-&gt;level != 0) {</div><div class='add'>+		err = __lmtt_alloc_range(lmtt, pt, start, end);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_free_pt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_free_pt:</div><div class='add'>+	lmtt_pt_free(pt);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_lmtt_pt *lmtt_leaf_pt(struct xe_lmtt *lmtt, unsigned int vfid, u64 addr)</div><div class='add'>+{</div><div class='add'>+	struct xe_lmtt_pt *pd = lmtt-&gt;pd;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, vfid &lt;= lmtt-&gt;ops-&gt;lmtt_pte_num(pd-&gt;level));</div><div class='add'>+	pt = pd-&gt;entries[vfid];</div><div class='add'>+</div><div class='add'>+	while (pt-&gt;level) {</div><div class='add'>+		lmtt_assert(lmtt, lmtt-&gt;ops-&gt;lmtt_pte_index(addr, pt-&gt;level) &lt;=</div><div class='add'>+			    lmtt-&gt;ops-&gt;lmtt_pte_num(pt-&gt;level));</div><div class='add'>+</div><div class='add'>+		pt = pt-&gt;entries[lmtt-&gt;ops-&gt;lmtt_pte_index(addr, pt-&gt;level)];</div><div class='add'>+</div><div class='add'>+		addr &gt;&gt;= lmtt-&gt;ops-&gt;lmtt_pte_shift(pt-&gt;level);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;ops-&gt;lmtt_pte_index(addr, pt-&gt;level) &lt;=</div><div class='add'>+		    lmtt-&gt;ops-&gt;lmtt_pte_num(pt-&gt;level));</div><div class='add'>+	lmtt_assert(lmtt, pt-&gt;level != pd-&gt;level);</div><div class='add'>+	lmtt_assert(lmtt, pt-&gt;level == 0);</div><div class='add'>+	return pt;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void lmtt_insert_bo(struct xe_lmtt *lmtt, unsigned int vfid, struct xe_bo *bo, u64 start)</div><div class='add'>+{</div><div class='add'>+	u64 page_size = lmtt_page_size(lmtt);</div><div class='add'>+	struct xe_res_cursor cur;</div><div class='add'>+	struct xe_lmtt_pt *pt;</div><div class='add'>+	u64 addr, vram_offset;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, IS_ALIGNED(start, page_size));</div><div class='add'>+	lmtt_assert(lmtt, IS_ALIGNED(bo-&gt;size, page_size));</div><div class='add'>+	lmtt_assert(lmtt, xe_bo_is_vram(bo));</div><div class='add'>+</div><div class='add'>+	vram_offset = vram_region_gpu_offset(bo-&gt;ttm.resource);</div><div class='add'>+	xe_res_first(bo-&gt;ttm.resource, 0, bo-&gt;size, &amp;cur);</div><div class='add'>+	while (cur.remaining) {</div><div class='add'>+		addr = xe_res_dma(&amp;cur);</div><div class='add'>+		addr += vram_offset; /* XXX */</div><div class='add'>+</div><div class='add'>+		pt = lmtt_leaf_pt(lmtt, vfid, start);</div><div class='add'>+</div><div class='add'>+		lmtt_write_pte(lmtt, pt, lmtt-&gt;ops-&gt;lmtt_pte_encode(addr, 0),</div><div class='add'>+					 lmtt-&gt;ops-&gt;lmtt_pte_index(start, 0));</div><div class='add'>+</div><div class='add'>+		xe_res_next(&amp;cur, page_size);</div><div class='add'>+		start += page_size;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_prepare_pages - Create VF's LMTT Page Tables.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt to update</div><div class='add'>+ * @vfid: the VF identifier (1-based)</div><div class='add'>+ * @range: top range of LMEM offset to be supported</div><div class='add'>+ *</div><div class='add'>+ * This function creates empty LMTT page tables for given VF to support</div><div class='add'>+ * up to maximum #range LMEM offset. The LMTT page tables created by this</div><div class='add'>+ * function must be released using xe_lmtt_drop_pages() function.</div><div class='add'>+ *</div><div class='add'>+ * Notes:</div><div class='add'>+ * This function shall be called only after successful LMTT initialization.</div><div class='add'>+ * See xe_lmtt_init().</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_lmtt_prepare_pages(struct xe_lmtt *lmtt, unsigned int vfid, u64 range)</div><div class='add'>+{</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;pd);</div><div class='add'>+	lmtt_assert(lmtt, vfid);</div><div class='add'>+</div><div class='add'>+	return lmtt_alloc_range(lmtt, vfid, 0, range);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_populate_pages - Update VF's LMTT Page Table Entries.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt to update</div><div class='add'>+ * @vfid: the VF identifier (1-based)</div><div class='add'>+ * @bo: the buffer object with LMEM allocation to be mapped</div><div class='add'>+ * @offset: the offset at which #bo should be mapped</div><div class='add'>+ *</div><div class='add'>+ * This function updates VF's LMTT entries to use given buffer object as a backstore.</div><div class='add'>+ *</div><div class='add'>+ * Notes:</div><div class='add'>+ * This function shall be called only after successful preparation of the</div><div class='add'>+ * VF's LMTT Page Tables. See xe_lmtt_prepare().</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success or a negative error code on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_lmtt_populate_pages(struct xe_lmtt *lmtt, unsigned int vfid, struct xe_bo *bo, u64 offset)</div><div class='add'>+{</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;pd);</div><div class='add'>+	lmtt_assert(lmtt, vfid);</div><div class='add'>+</div><div class='add'>+	lmtt_insert_bo(lmtt, vfid, bo, offset);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_drop_pages - Remove VF's LMTT Pages.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt to update</div><div class='add'>+ * @vfid: the VF identifier (1-based)</div><div class='add'>+ *</div><div class='add'>+ * This function removes all LMTT Page Tables prepared by xe_lmtt_prepare_pages().</div><div class='add'>+ *</div><div class='add'>+ * This function shall be called only after successful LMTT initialization.</div><div class='add'>+ * See xe_lmtt_init().</div><div class='add'>+ */</div><div class='add'>+void xe_lmtt_drop_pages(struct xe_lmtt *lmtt, unsigned int vfid)</div><div class='add'>+{</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;pd);</div><div class='add'>+	lmtt_assert(lmtt, vfid);</div><div class='add'>+</div><div class='add'>+	lmtt_drop_pages(lmtt, vfid);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_lmtt_estimate_pt_size - Estimate size of LMTT PT allocations.</div><div class='add'>+ * @lmtt: the &amp;xe_lmtt</div><div class='add'>+ * @size: the size of the LMEM to be mapped over LMTT (including any offset)</div><div class='add'>+ *</div><div class='add'>+ * This function shall be called only by PF.</div><div class='add'>+ *</div><div class='add'>+ * Return: size of the PT allocation(s) needed to support given LMEM size.</div><div class='add'>+ */</div><div class='add'>+u64 xe_lmtt_estimate_pt_size(struct xe_lmtt *lmtt, u64 size)</div><div class='add'>+{</div><div class='add'>+	unsigned int level = 0;</div><div class='add'>+	u64 pt_size;</div><div class='add'>+</div><div class='add'>+	lmtt_assert(lmtt, IS_SRIOV_PF(lmtt_to_xe(lmtt)));</div><div class='add'>+	lmtt_assert(lmtt, IS_DGFX(lmtt_to_xe(lmtt)));</div><div class='add'>+	lmtt_assert(lmtt, lmtt-&gt;ops);</div><div class='add'>+</div><div class='add'>+	pt_size = PAGE_ALIGN(lmtt-&gt;ops-&gt;lmtt_pte_size(level) *</div><div class='add'>+			     lmtt-&gt;ops-&gt;lmtt_pte_num(level));</div><div class='add'>+</div><div class='add'>+	while (++level &lt; lmtt-&gt;ops-&gt;lmtt_root_pd_level()) {</div><div class='add'>+		pt_size *= lmtt-&gt;ops-&gt;lmtt_pte_index(size, level) + 1;</div><div class='add'>+		pt_size += PAGE_ALIGN(lmtt-&gt;ops-&gt;lmtt_pte_size(level) *</div><div class='add'>+				      lmtt-&gt;ops-&gt;lmtt_pte_num(level));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return pt_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_BUILTIN(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_lmtt_test.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lmtt.h b/drivers/gpu/drm/xe/xe_lmtt.h<br/>new file mode 100644<br/>index 000000000000..cb10ef994db6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lmtt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt.h</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_LMTT_H_</div><div class='add'>+#define _XE_LMTT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_lmtt;</div><div class='add'>+struct xe_lmtt_ops;</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PCI_IOV</div><div class='add'>+int xe_lmtt_init(struct xe_lmtt *lmtt);</div><div class='add'>+void xe_lmtt_init_hw(struct xe_lmtt *lmtt);</div><div class='add'>+int xe_lmtt_prepare_pages(struct xe_lmtt *lmtt, unsigned int vfid, u64 range);</div><div class='add'>+int xe_lmtt_populate_pages(struct xe_lmtt *lmtt, unsigned int vfid, struct xe_bo *bo, u64 offset);</div><div class='add'>+void xe_lmtt_drop_pages(struct xe_lmtt *lmtt, unsigned int vfid);</div><div class='add'>+u64 xe_lmtt_estimate_pt_size(struct xe_lmtt *lmtt, u64 size);</div><div class='add'>+#else</div><div class='add'>+static inline int xe_lmtt_init(struct xe_lmtt *lmtt) { return 0; }</div><div class='add'>+static inline void xe_lmtt_init_hw(struct xe_lmtt *lmtt) { }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lmtt_2l.c b/drivers/gpu/drm/xe/xe_lmtt_2l.c<br/>new file mode 100644<br/>index 000000000000..84bc5c4212b5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lmtt_2l.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_2l.c</a></div><div class='hunk'>@@ -0,0 +1,150 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/log2.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_lmtt_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Two-Level LMTT Structure</div><div class='add'>+ *</div><div class='add'>+ * LMHAW (Local Memory Host Address Width) is 37 bit (128GB)</div><div class='add'>+ *</div><div class='add'>+ * LMGAW (Local Memory Guest Address Width) is 37 bit (128GB)</div><div class='add'>+ *</div><div class='add'>+ * The following figure illustrates the structure and function of the 2L LMTT::</div><div class='add'>+ *</div><div class='add'>+ *            LMTT Directory</div><div class='add'>+ *           (1 Entry per VF)</div><div class='add'>+ *            +-----------+                     LMTT (per VF)</div><div class='add'>+ *            |           |                     +-----------+</div><div class='add'>+ *            |           |                     |           |</div><div class='add'>+ *            |           |          index:     |           |</div><div class='add'>+ *            |           |          LMEM VF    +===========+</div><div class='add'>+ *            |           |          offset --&gt; |    PTE    | ==&gt; LMEM PF offset</div><div class='add'>+ *            |           |                     +===========+</div><div class='add'>+ *   index:   +===========+                     |           |</div><div class='add'>+ *   VFID --&gt; |    PDE    |  -----------------&gt; +-----------+</div><div class='add'>+ *            +===========+                    /              \.</div><div class='add'>+ *            |           |                   /                 \.</div><div class='add'>+ *            |           |                  /                    \.</div><div class='add'>+ *            |           |                 /                       \.</div><div class='add'>+ *            +-----------+ &lt;== [LMTT Directory Ptr]                  \.</div><div class='add'>+ *           /             \              /                             \.</div><div class='add'>+ *          /               \         +-----------+-----------------+------+---+</div><div class='add'>+ *         /                 \        | 31:HAW-16 |        HAW-17:5 |  4:1 | 0 |</div><div class='add'>+ *        /                   \       +===========+=================+======+===+</div><div class='add'>+ *       /                     \      |  Reserved | LMEM Page (2MB) | Rsvd | V |</div><div class='add'>+ *      /                       \     +-----------+-----------------+------+---+</div><div class='add'>+ *     /                         \.</div><div class='add'>+ *   +-----------+-----------------+------+---+</div><div class='add'>+ *   | 31:HAW-12 |        HAW-13:4 |  3:1 | 0 |</div><div class='add'>+ *   +===========+=================+======+===+</div><div class='add'>+ *   |  Reserved | LMTT Ptr (64KB) | Rsvd | V |</div><div class='add'>+ *   +-----------+-----------------+------+---+</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+typedef u32 lmtt_2l_pde_t;</div><div class='add'>+typedef u32 lmtt_2l_pte_t;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_LMTT_2L_128GB)</div><div class='add'>+#define LMTT_2L_HAW			37 /* 128 GiB */</div><div class='add'>+#else</div><div class='add'>+#define LMTT_2L_HAW			35 /* 32 GiB */</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define LMTT_2L_PDE_MAX_NUM		64 /* SRIOV with PF and 63 VFs, index 0 (PF) is unused */</div><div class='add'>+#define LMTT_2L_PDE_LMTT_PTR		GENMASK(LMTT_2L_HAW - 13, 4)</div><div class='add'>+#define LMTT_2L_PDE_VALID		BIT(0)</div><div class='add'>+</div><div class='add'>+#define LMTT_2L_PTE_MAX_NUM		BIT(LMTT_2L_HAW - ilog2(SZ_2M))</div><div class='add'>+#define LMTT_2L_PTE_LMEM_PAGE		GENMASK(LMTT_2L_HAW - 17, 5)</div><div class='add'>+#define LMTT_2L_PTE_VALID		BIT(0)</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_2l_root_pd_level(void)</div><div class='add'>+{</div><div class='add'>+	return 1; /* implementation is 0-based */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_2l_pte_num(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 1:</div><div class='add'>+		return LMTT_2L_PDE_MAX_NUM;</div><div class='add'>+	case 0:</div><div class='add'>+		BUILD_BUG_ON(LMTT_2L_HAW == 37 &amp;&amp; LMTT_2L_PTE_MAX_NUM != SZ_64K);</div><div class='add'>+		BUILD_BUG_ON(LMTT_2L_HAW == 35 &amp;&amp; LMTT_2L_PTE_MAX_NUM != SZ_16K);</div><div class='add'>+		return LMTT_2L_PTE_MAX_NUM;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_2l_pte_size(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 1:</div><div class='add'>+		return sizeof(lmtt_2l_pde_t);</div><div class='add'>+	case 0:</div><div class='add'>+		return sizeof(lmtt_2l_pte_t);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_2l_pte_shift(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 0:</div><div class='add'>+		return ilog2(SZ_2M);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_2l_pte_index(u64 addr, unsigned int level)</div><div class='add'>+{</div><div class='add'>+	addr &gt;&gt;= lmtt_2l_pte_shift(level);</div><div class='add'>+</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 0:</div><div class='add'>+		/* SZ_2M increments */</div><div class='add'>+		BUILD_BUG_ON_NOT_POWER_OF_2(LMTT_2L_PTE_MAX_NUM);</div><div class='add'>+		return addr &amp; (LMTT_2L_PTE_MAX_NUM - 1);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 lmtt_2l_pte_encode(unsigned long offset, unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 0:</div><div class='add'>+		XE_WARN_ON(!IS_ALIGNED(offset, SZ_2M));</div><div class='add'>+		XE_WARN_ON(!FIELD_FIT(LMTT_2L_PTE_LMEM_PAGE, offset / SZ_2M));</div><div class='add'>+		return FIELD_PREP(LMTT_2L_PTE_LMEM_PAGE, offset / SZ_2M) | LMTT_2L_PTE_VALID;</div><div class='add'>+	case 1:</div><div class='add'>+		XE_WARN_ON(!IS_ALIGNED(offset, SZ_64K));</div><div class='add'>+		XE_WARN_ON(!FIELD_FIT(LMTT_2L_PDE_LMTT_PTR, offset / SZ_64K));</div><div class='add'>+		return FIELD_PREP(LMTT_2L_PDE_LMTT_PTR, offset / SZ_64K) | LMTT_2L_PDE_VALID;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON(true);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct xe_lmtt_ops lmtt_2l_ops = {</div><div class='add'>+	.lmtt_root_pd_level = lmtt_2l_root_pd_level,</div><div class='add'>+	.lmtt_pte_num = lmtt_2l_pte_num,</div><div class='add'>+	.lmtt_pte_size = lmtt_2l_pte_size,</div><div class='add'>+	.lmtt_pte_shift = lmtt_2l_pte_shift,</div><div class='add'>+	.lmtt_pte_index = lmtt_2l_pte_index,</div><div class='add'>+	.lmtt_pte_encode = lmtt_2l_pte_encode,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lmtt_ml.c b/drivers/gpu/drm/xe/xe_lmtt_ml.c<br/>new file mode 100644<br/>index 000000000000..b21215a2edd6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lmtt_ml.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_ml.c</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/log2.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_lmtt_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Multi-Level LMTT Structure</div><div class='add'>+ *</div><div class='add'>+ * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)</div><div class='add'>+ *</div><div class='add'>+ * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)</div><div class='add'>+ *</div><div class='add'>+ * The following figure illustrates the structure and function of the ML LMTT::</div><div class='add'>+ *</div><div class='add'>+ *           LMTT L3 Directory</div><div class='add'>+ *           (1 Entry per VF)                                       LMTT L1 Leaf</div><div class='add'>+ *            +-----------+                                         +-----------+</div><div class='add'>+ *            |           |             LMTT L2 (per VF)            |           |</div><div class='add'>+ *            |           |              +-----------+              |           |</div><div class='add'>+ *            |           |              |           |     index:   +===========+</div><div class='add'>+ *            |           |              |           |     GDPA --&gt; |    PTE    | =&gt; LMEM PF offset</div><div class='add'>+ *            |           |              |           |     34:21    +===========+</div><div class='add'>+ *            |           |    index:    |           |              |           |</div><div class='add'>+ *            |           |    LMEM VF   +===========+              |           |</div><div class='add'>+ *            |           |    offset -&gt; |    PTE    |  ----------&gt; +-----------+</div><div class='add'>+ *            |           |    GAW-1:35  +===========+              /           \.</div><div class='add'>+ *   index:   +===========+              |           |             /              \.</div><div class='add'>+ *   VFID --&gt; |    PDE    |  ---------&gt;  +-----------+            /                 \.</div><div class='add'>+ *            +===========+             /           /            /                    \.</div><div class='add'>+ *            |           |           /            /            /                       \.</div><div class='add'>+ *            +-----------+  &lt;== [LMTT Directory Ptr]          /                          \.</div><div class='add'>+ *           /             \      /              /            /                             \.</div><div class='add'>+ *          /                \  /               /       +-----------+-----------------+------+---+</div><div class='add'>+ *         /                  /\               /        | 31:HAW-16 |        HAW-17:5 |  4:1 | 0 |</div><div class='add'>+ *        /                 /    \            /         +===========+=================+======+===+</div><div class='add'>+ *       /                /        \         /          |  Reserved | LMEM Page (2MB) | Rsvd | V |</div><div class='add'>+ *      /                                   /           +-----------+-----------------+------+---+</div><div class='add'>+ *     /                                   /</div><div class='add'>+ *  +-----------+-----------------+------+---+</div><div class='add'>+ *  | 63:HAW-12 |        HAW-13:4 |  3:1 | 0 |</div><div class='add'>+ *  +===========+=================+======+===+</div><div class='add'>+ *  |  Reserved | LMTT Ptr (64KB) | Rsvd | V |</div><div class='add'>+ *  +-----------+-----------------+------+---+</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+typedef u64 lmtt_ml_pde_t;</div><div class='add'>+typedef u32 lmtt_ml_pte_t;</div><div class='add'>+</div><div class='add'>+#define LMTT_ML_HAW			48 /* 256 TiB */</div><div class='add'>+</div><div class='add'>+#define LMTT_ML_PDE_MAX_NUM		64 /* SRIOV with PF and 63 VFs, index 0 (PF) is unused */</div><div class='add'>+#define LMTT_ML_PDE_LMTT_PTR		GENMASK_ULL(LMTT_ML_HAW - 13, 4)</div><div class='add'>+#define LMTT_ML_PDE_VALID		BIT(0)</div><div class='add'>+</div><div class='add'>+#define LMTT_ML_PDE_L2_SHIFT		35</div><div class='add'>+#define LMTT_ML_PDE_L2_MAX_NUM		BIT_ULL(LMTT_ML_HAW - 35)</div><div class='add'>+</div><div class='add'>+#define LMTT_ML_PTE_MAX_NUM		BIT(35 - ilog2(SZ_2M))</div><div class='add'>+#define LMTT_ML_PTE_LMEM_PAGE		GENMASK(LMTT_ML_HAW - 17, 5)</div><div class='add'>+#define LMTT_ML_PTE_VALID		BIT(0)</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_ml_root_pd_level(void)</div><div class='add'>+{</div><div class='add'>+	return 2; /* implementation is 0-based */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_ml_pte_num(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 2:</div><div class='add'>+		return LMTT_ML_PDE_MAX_NUM;</div><div class='add'>+	case 1:</div><div class='add'>+		BUILD_BUG_ON(LMTT_ML_HAW == 48 &amp;&amp; LMTT_ML_PDE_L2_MAX_NUM != SZ_8K);</div><div class='add'>+		return LMTT_ML_PDE_L2_MAX_NUM;</div><div class='add'>+	case 0:</div><div class='add'>+		BUILD_BUG_ON(LMTT_ML_PTE_MAX_NUM != SZ_16K);</div><div class='add'>+		return LMTT_ML_PTE_MAX_NUM;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_ml_pte_size(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 2:</div><div class='add'>+	case 1:</div><div class='add'>+		return sizeof(lmtt_ml_pde_t);</div><div class='add'>+	case 0:</div><div class='add'>+		return sizeof(lmtt_ml_pte_t);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_ml_pte_shift(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 1:</div><div class='add'>+		BUILD_BUG_ON(BIT_ULL(LMTT_ML_PDE_L2_SHIFT) != SZ_32G);</div><div class='add'>+		return ilog2(SZ_32G);</div><div class='add'>+	case 0:</div><div class='add'>+		return ilog2(SZ_2M);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int lmtt_ml_pte_index(u64 addr, unsigned int level)</div><div class='add'>+{</div><div class='add'>+	addr &gt;&gt;= lmtt_ml_pte_shift(level);</div><div class='add'>+</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 1:</div><div class='add'>+		/* SZ_32G increments */</div><div class='add'>+		BUILD_BUG_ON_NOT_POWER_OF_2(LMTT_ML_PDE_L2_MAX_NUM);</div><div class='add'>+		return addr &amp; (LMTT_ML_PDE_L2_MAX_NUM - 1);</div><div class='add'>+	case 0:</div><div class='add'>+		/* SZ_2M increments */</div><div class='add'>+		BUILD_BUG_ON_NOT_POWER_OF_2(LMTT_ML_PTE_MAX_NUM);</div><div class='add'>+		return addr &amp; (LMTT_ML_PTE_MAX_NUM - 1);</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 lmtt_ml_pte_encode(unsigned long offset, unsigned int level)</div><div class='add'>+{</div><div class='add'>+	switch (level) {</div><div class='add'>+	case 0:</div><div class='add'>+		XE_WARN_ON(!IS_ALIGNED(offset, SZ_2M));</div><div class='add'>+		XE_WARN_ON(!FIELD_FIT(LMTT_ML_PTE_LMEM_PAGE, offset / SZ_2M));</div><div class='add'>+		return FIELD_PREP(LMTT_ML_PTE_LMEM_PAGE, offset / SZ_2M) | LMTT_ML_PTE_VALID;</div><div class='add'>+	case 1:</div><div class='add'>+	case 2:</div><div class='add'>+		XE_WARN_ON(!IS_ALIGNED(offset, SZ_64K));</div><div class='add'>+		XE_WARN_ON(!FIELD_FIT(LMTT_ML_PDE_LMTT_PTR, offset / SZ_64K));</div><div class='add'>+		return FIELD_PREP(LMTT_ML_PDE_LMTT_PTR, offset / SZ_64K) | LMTT_ML_PDE_VALID;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON(true);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct xe_lmtt_ops lmtt_ml_ops = {</div><div class='add'>+	.lmtt_root_pd_level = lmtt_ml_root_pd_level,</div><div class='add'>+	.lmtt_pte_num = lmtt_ml_pte_num,</div><div class='add'>+	.lmtt_pte_size = lmtt_ml_pte_size,</div><div class='add'>+	.lmtt_pte_shift = lmtt_ml_pte_shift,</div><div class='add'>+	.lmtt_pte_index = lmtt_ml_pte_index,</div><div class='add'>+	.lmtt_pte_encode = lmtt_ml_pte_encode,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lmtt_types.h b/drivers/gpu/drm/xe/xe_lmtt_types.h<br/>new file mode 100644<br/>index 000000000000..b37abad23416<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lmtt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lmtt_types.h</a></div><div class='hunk'>@@ -0,0 +1,63 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_LMTT_TYPES_H_</div><div class='add'>+#define _XE_LMTT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_lmtt;</div><div class='add'>+struct xe_lmtt_pt;</div><div class='add'>+struct xe_lmtt_ops;</div><div class='add'>+</div><div class='add'>+#define LMTT_PTE_INVALID	ULL(0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_lmtt - Local Memory Translation Table Manager</div><div class='add'>+ */</div><div class='add'>+struct xe_lmtt {</div><div class='add'>+	/** @pd: root LMTT Directory */</div><div class='add'>+	struct xe_lmtt_pt *pd;</div><div class='add'>+</div><div class='add'>+	/** @ops: LMTT functions */</div><div class='add'>+	const struct xe_lmtt_ops *ops;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_lmtt_pt - Local Memory Translation Table Page Table</div><div class='add'>+ *</div><div class='add'>+ * Represents single level of the LMTT.</div><div class='add'>+ */</div><div class='add'>+struct xe_lmtt_pt {</div><div class='add'>+	/** @level: page table level, 0 is leaf */</div><div class='add'>+	unsigned int level;</div><div class='add'>+</div><div class='add'>+	/** @bo: buffer object with actual LMTT PTE values */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	/** @entries: leaf page tables, exist only for root/non-leaf */</div><div class='add'>+	struct xe_lmtt_pt *entries[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_lmtt_ops - Local Memory Translation Table Operations</div><div class='add'>+ *</div><div class='add'>+ * Provides abstraction of the LMTT variants.</div><div class='add'>+ */</div><div class='add'>+struct xe_lmtt_ops {</div><div class='add'>+	/* private: */</div><div class='add'>+	unsigned int (*lmtt_root_pd_level)(void);</div><div class='add'>+	unsigned int (*lmtt_pte_num)(unsigned int level);</div><div class='add'>+	unsigned int (*lmtt_pte_size)(unsigned int level);</div><div class='add'>+	unsigned int (*lmtt_pte_shift)(unsigned int level);</div><div class='add'>+	unsigned int (*lmtt_pte_index)(u64 addr, unsigned int level);</div><div class='add'>+	u64 (*lmtt_pte_encode)(unsigned long offset, unsigned int level);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct xe_lmtt_ops lmtt_2l_ops;</div><div class='add'>+extern const struct xe_lmtt_ops lmtt_ml_ops;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c<br/>new file mode 100644<br/>index 000000000000..b7fa3831b684<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc.c</a></div><div class='hunk'>@@ -0,0 +1,1272 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "instructions/xe_gfxpipe_commands.h"</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "regs/xe_lrc_layout.h"</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+#define CTX_VALID				(1 &lt;&lt; 0)</div><div class='add'>+#define CTX_PRIVILEGE				(1 &lt;&lt; 8)</div><div class='add'>+#define CTX_ADDRESSING_MODE_SHIFT		3</div><div class='add'>+#define LEGACY_64B_CONTEXT			3</div><div class='add'>+</div><div class='add'>+#define ENGINE_CLASS_SHIFT			61</div><div class='add'>+#define ENGINE_INSTANCE_SHIFT			48</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+lrc_to_xe(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(lrc-&gt;fence_ctx.gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	switch (class) {</div><div class='add'>+	case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+			return 4 * SZ_4K;</div><div class='add'>+		else</div><div class='add'>+			return 14 * SZ_4K;</div><div class='add'>+	case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+		/* 14 pages since graphics_ver == 11 */</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+			return 3 * SZ_4K;</div><div class='add'>+		else</div><div class='add'>+			return 14 * SZ_4K;</div><div class='add'>+	default:</div><div class='add'>+		WARN(1, "Unknown engine class: %d", class);</div><div class='add'>+		fallthrough;</div><div class='add'>+	case XE_ENGINE_CLASS_COPY:</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_DECODE:</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:</div><div class='add'>+	case XE_ENGINE_CLASS_OTHER:</div><div class='add'>+		return 2 * SZ_4K;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The per-platform tables are u8-encoded in @data. Decode @data and set the</div><div class='add'>+ * addresses' offset and commands in @regs. The following encoding is used</div><div class='add'>+ * for each byte. There are 2 steps: decoding commands and decoding addresses.</div><div class='add'>+ *</div><div class='add'>+ * Commands:</div><div class='add'>+ * [7]: create NOPs - number of NOPs are set in lower bits</div><div class='add'>+ * [6]: When creating MI_LOAD_REGISTER_IMM command, allow to set</div><div class='add'>+ *      MI_LRI_FORCE_POSTED</div><div class='add'>+ * [5:0]: Number of NOPs or registers to set values to in case of</div><div class='add'>+ *        MI_LOAD_REGISTER_IMM</div><div class='add'>+ *</div><div class='add'>+ * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"</div><div class='add'>+ * number of registers. They are set by using the REG/REG16 macros: the former</div><div class='add'>+ * is used for offsets smaller than 0x200 while the latter is for values bigger</div><div class='add'>+ * than that. Those macros already set all the bits documented below correctly:</div><div class='add'>+ *</div><div class='add'>+ * [7]: When a register offset needs more than 6 bits, use additional bytes, to</div><div class='add'>+ *      follow, for the lower bits</div><div class='add'>+ * [6:0]: Register offset, without considering the engine base.</div><div class='add'>+ *</div><div class='add'>+ * This function only tweaks the commands and register offsets. Values are not</div><div class='add'>+ * filled out.</div><div class='add'>+ */</div><div class='add'>+static void set_offsets(u32 *regs,</div><div class='add'>+			const u8 *data,</div><div class='add'>+			const struct xe_hw_engine *hwe)</div><div class='add'>+#define NOP(x) (BIT(7) | (x))</div><div class='add'>+#define LRI(count, flags) ((flags) &lt;&lt; 6 | (count) | \</div><div class='add'>+			   BUILD_BUG_ON_ZERO(count &gt;= BIT(6)))</div><div class='add'>+#define POSTED BIT(0)</div><div class='add'>+#define REG(x) (((x) &gt;&gt; 2) | BUILD_BUG_ON_ZERO(x &gt;= 0x200))</div><div class='add'>+#define REG16(x) \</div><div class='add'>+	(((x) &gt;&gt; 9) | BIT(7) | BUILD_BUG_ON_ZERO(x &gt;= 0x10000)), \</div><div class='add'>+	(((x) &gt;&gt; 2) &amp; 0x7f)</div><div class='add'>+#define END 0</div><div class='add'>+{</div><div class='add'>+	const u32 base = hwe-&gt;mmio_base;</div><div class='add'>+</div><div class='add'>+	while (*data) {</div><div class='add'>+		u8 count, flags;</div><div class='add'>+</div><div class='add'>+		if (*data &amp; BIT(7)) { /* skip */</div><div class='add'>+			count = *data++ &amp; ~BIT(7);</div><div class='add'>+			regs += count;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		count = *data &amp; 0x3f;</div><div class='add'>+		flags = *data &gt;&gt; 6;</div><div class='add'>+		data++;</div><div class='add'>+</div><div class='add'>+		*regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);</div><div class='add'>+		if (flags &amp; POSTED)</div><div class='add'>+			*regs |= MI_LRI_FORCE_POSTED;</div><div class='add'>+		*regs |= MI_LRI_LRM_CS_MMIO;</div><div class='add'>+		regs++;</div><div class='add'>+</div><div class='add'>+		xe_gt_assert(hwe-&gt;gt, count);</div><div class='add'>+		do {</div><div class='add'>+			u32 offset = 0;</div><div class='add'>+			u8 v;</div><div class='add'>+</div><div class='add'>+			do {</div><div class='add'>+				v = *data++;</div><div class='add'>+				offset &lt;&lt;= 7;</div><div class='add'>+				offset |= v &amp; ~BIT(7);</div><div class='add'>+			} while (v &amp; BIT(7));</div><div class='add'>+</div><div class='add'>+			regs[0] = base + (offset &lt;&lt; 2);</div><div class='add'>+			regs += 2;</div><div class='add'>+		} while (--count);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*regs = MI_BATCH_BUFFER_END | BIT(0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const u8 gen12_xcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(13, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+</div><div class='add'>+	NOP(5),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 dg2_xcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(15, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+	REG(0x120),</div><div class='add'>+	REG(0x124),</div><div class='add'>+</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 gen12_rcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(13, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+</div><div class='add'>+	NOP(5),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	LRI(3, POSTED),</div><div class='add'>+	REG(0x1b0),</div><div class='add'>+	REG16(0x5a8),</div><div class='add'>+	REG16(0x5ac),</div><div class='add'>+</div><div class='add'>+	NOP(6),</div><div class='add'>+	LRI(1, 0),</div><div class='add'>+	REG(0x0c8),</div><div class='add'>+	NOP(3 + 9 + 1),</div><div class='add'>+</div><div class='add'>+	LRI(51, POSTED),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG16(0x588),</div><div class='add'>+	REG(0x028),</div><div class='add'>+	REG(0x09c),</div><div class='add'>+	REG(0x0c0),</div><div class='add'>+	REG(0x178),</div><div class='add'>+	REG(0x17c),</div><div class='add'>+	REG16(0x358),</div><div class='add'>+	REG(0x170),</div><div class='add'>+	REG(0x150),</div><div class='add'>+	REG(0x154),</div><div class='add'>+	REG(0x158),</div><div class='add'>+	REG16(0x41c),</div><div class='add'>+	REG16(0x600),</div><div class='add'>+	REG16(0x604),</div><div class='add'>+	REG16(0x608),</div><div class='add'>+	REG16(0x60c),</div><div class='add'>+	REG16(0x610),</div><div class='add'>+	REG16(0x614),</div><div class='add'>+	REG16(0x618),</div><div class='add'>+	REG16(0x61c),</div><div class='add'>+	REG16(0x620),</div><div class='add'>+	REG16(0x624),</div><div class='add'>+	REG16(0x628),</div><div class='add'>+	REG16(0x62c),</div><div class='add'>+	REG16(0x630),</div><div class='add'>+	REG16(0x634),</div><div class='add'>+	REG16(0x638),</div><div class='add'>+	REG16(0x63c),</div><div class='add'>+	REG16(0x640),</div><div class='add'>+	REG16(0x644),</div><div class='add'>+	REG16(0x648),</div><div class='add'>+	REG16(0x64c),</div><div class='add'>+	REG16(0x650),</div><div class='add'>+	REG16(0x654),</div><div class='add'>+	REG16(0x658),</div><div class='add'>+	REG16(0x65c),</div><div class='add'>+	REG16(0x660),</div><div class='add'>+	REG16(0x664),</div><div class='add'>+	REG16(0x668),</div><div class='add'>+	REG16(0x66c),</div><div class='add'>+	REG16(0x670),</div><div class='add'>+	REG16(0x674),</div><div class='add'>+	REG16(0x678),</div><div class='add'>+	REG16(0x67c),</div><div class='add'>+	REG(0x068),</div><div class='add'>+	REG(0x084),</div><div class='add'>+	NOP(1),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 xehp_rcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(13, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+</div><div class='add'>+	NOP(5),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	LRI(3, POSTED),</div><div class='add'>+	REG(0x1b0),</div><div class='add'>+	REG16(0x5a8),</div><div class='add'>+	REG16(0x5ac),</div><div class='add'>+</div><div class='add'>+	NOP(6),</div><div class='add'>+	LRI(1, 0),</div><div class='add'>+	REG(0x0c8),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 dg2_rcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(15, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+	REG(0x120),</div><div class='add'>+	REG(0x124),</div><div class='add'>+</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	LRI(3, POSTED),</div><div class='add'>+	REG(0x1b0),</div><div class='add'>+	REG16(0x5a8),</div><div class='add'>+	REG16(0x5ac),</div><div class='add'>+</div><div class='add'>+	NOP(6),</div><div class='add'>+	LRI(1, 0),</div><div class='add'>+	REG(0x0c8),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 mtl_rcs_offsets[] = {</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(15, POSTED),</div><div class='add'>+	REG16(0x244),</div><div class='add'>+	REG(0x034),</div><div class='add'>+	REG(0x030),</div><div class='add'>+	REG(0x038),</div><div class='add'>+	REG(0x03c),</div><div class='add'>+	REG(0x168),</div><div class='add'>+	REG(0x140),</div><div class='add'>+	REG(0x110),</div><div class='add'>+	REG(0x1c0),</div><div class='add'>+	REG(0x1c4),</div><div class='add'>+	REG(0x1c8),</div><div class='add'>+	REG(0x180),</div><div class='add'>+	REG16(0x2b4),</div><div class='add'>+	REG(0x120),</div><div class='add'>+	REG(0x124),</div><div class='add'>+</div><div class='add'>+	NOP(1),</div><div class='add'>+	LRI(9, POSTED),</div><div class='add'>+	REG16(0x3a8),</div><div class='add'>+	REG16(0x28c),</div><div class='add'>+	REG16(0x288),</div><div class='add'>+	REG16(0x284),</div><div class='add'>+	REG16(0x280),</div><div class='add'>+	REG16(0x27c),</div><div class='add'>+	REG16(0x278),</div><div class='add'>+	REG16(0x274),</div><div class='add'>+	REG16(0x270),</div><div class='add'>+</div><div class='add'>+	NOP(2),</div><div class='add'>+	LRI(2, POSTED),</div><div class='add'>+	REG16(0x5a8),</div><div class='add'>+	REG16(0x5ac),</div><div class='add'>+</div><div class='add'>+	NOP(6),</div><div class='add'>+	LRI(1, 0),</div><div class='add'>+	REG(0x0c8),</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE2_CTX_COMMON \</div><div class='add'>+	NOP(1),                 /* [0x00] */ \</div><div class='add'>+	LRI(15, POSTED),        /* [0x01] */ \</div><div class='add'>+	REG16(0x244),           /* [0x02] CTXT_SR_CTL */ \</div><div class='add'>+	REG(0x034),             /* [0x04] RING_BUFFER_HEAD */ \</div><div class='add'>+	REG(0x030),             /* [0x06] RING_BUFFER_TAIL */ \</div><div class='add'>+	REG(0x038),             /* [0x08] RING_BUFFER_START */ \</div><div class='add'>+	REG(0x03c),             /* [0x0a] RING_BUFFER_CONTROL */ \</div><div class='add'>+	REG(0x168),             /* [0x0c] BB_ADDR_UDW */ \</div><div class='add'>+	REG(0x140),             /* [0x0e] BB_ADDR */ \</div><div class='add'>+	REG(0x110),             /* [0x10] BB_STATE */ \</div><div class='add'>+	REG(0x1c0),             /* [0x12] BB_PER_CTX_PTR */ \</div><div class='add'>+	REG(0x1c4),             /* [0x14] RCS_INDIRECT_CTX */ \</div><div class='add'>+	REG(0x1c8),             /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \</div><div class='add'>+	REG(0x180),             /* [0x18] CCID */ \</div><div class='add'>+	REG16(0x2b4),           /* [0x1a] SEMAPHORE_TOKEN */ \</div><div class='add'>+	REG(0x120),             /* [0x1c] PRT_BB_STATE */ \</div><div class='add'>+	REG(0x124),             /* [0x1e] PRT_BB_STATE_UDW */ \</div><div class='add'>+	\</div><div class='add'>+	NOP(1),                 /* [0x20] */ \</div><div class='add'>+	LRI(9, POSTED),         /* [0x21] */ \</div><div class='add'>+	REG16(0x3a8),           /* [0x22] CTX_TIMESTAMP */ \</div><div class='add'>+	REG16(0x3ac),           /* [0x24] CTX_TIMESTAMP_UDW */ \</div><div class='add'>+	REG(0x108),             /* [0x26] INDIRECT_RING_STATE */ \</div><div class='add'>+	REG16(0x284),           /* [0x28] dummy reg */ \</div><div class='add'>+	REG16(0x280),           /* [0x2a] CS_ACC_CTR_THOLD */ \</div><div class='add'>+	REG16(0x27c),           /* [0x2c] CS_CTX_SYS_PASID */ \</div><div class='add'>+	REG16(0x278),           /* [0x2e] CS_CTX_ASID */ \</div><div class='add'>+	REG16(0x274),           /* [0x30] PTBP_UDW */ \</div><div class='add'>+	REG16(0x270)            /* [0x32] PTBP_LDW */</div><div class='add'>+</div><div class='add'>+static const u8 xe2_rcs_offsets[] = {</div><div class='add'>+	XE2_CTX_COMMON,</div><div class='add'>+</div><div class='add'>+	NOP(2),                 /* [0x34] */</div><div class='add'>+	LRI(2, POSTED),         /* [0x36] */</div><div class='add'>+	REG16(0x5a8),           /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */</div><div class='add'>+	REG16(0x5ac),           /* [0x39] PREEMPTION_STATUS */</div><div class='add'>+</div><div class='add'>+	NOP(6),                 /* [0x41] */</div><div class='add'>+	LRI(1, 0),              /* [0x47] */</div><div class='add'>+	REG(0x0c8),             /* [0x48] R_PWR_CLK_STATE */</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 xe2_bcs_offsets[] = {</div><div class='add'>+	XE2_CTX_COMMON,</div><div class='add'>+</div><div class='add'>+	NOP(4 + 8 + 1),         /* [0x34] */</div><div class='add'>+	LRI(2, POSTED),         /* [0x41] */</div><div class='add'>+	REG16(0x200),           /* [0x42] BCS_SWCTRL */</div><div class='add'>+	REG16(0x204),           /* [0x44] BLIT_CCTL */</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 xe2_xcs_offsets[] = {</div><div class='add'>+	XE2_CTX_COMMON,</div><div class='add'>+</div><div class='add'>+	END</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#undef END</div><div class='add'>+#undef REG16</div><div class='add'>+#undef REG</div><div class='add'>+#undef LRI</div><div class='add'>+#undef NOP</div><div class='add'>+</div><div class='add'>+static const u8 *reg_offsets(struct xe_device *xe, enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	if (class == XE_ENGINE_CLASS_RENDER) {</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+			return xe2_rcs_offsets;</div><div class='add'>+		else if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+			return mtl_rcs_offsets;</div><div class='add'>+		else if (GRAPHICS_VERx100(xe) &gt;= 1255)</div><div class='add'>+			return dg2_rcs_offsets;</div><div class='add'>+		else if (GRAPHICS_VERx100(xe) &gt;= 1250)</div><div class='add'>+			return xehp_rcs_offsets;</div><div class='add'>+		else</div><div class='add'>+			return gen12_rcs_offsets;</div><div class='add'>+	} else if (class == XE_ENGINE_CLASS_COPY) {</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+			return xe2_bcs_offsets;</div><div class='add'>+		else</div><div class='add'>+			return gen12_xcs_offsets;</div><div class='add'>+	} else {</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+			return xe2_xcs_offsets;</div><div class='add'>+		else if (GRAPHICS_VERx100(xe) &gt;= 1255)</div><div class='add'>+			return dg2_xcs_offsets;</div><div class='add'>+		else</div><div class='add'>+			return gen12_xcs_offsets;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	regs[CTX_CONTEXT_CONTROL] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH) |</div><div class='add'>+				    _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |</div><div class='add'>+				    CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;</div><div class='add'>+</div><div class='add'>+	/* TODO: Timestamp */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int lrc_ring_mi_mode(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(hwe-&gt;gt);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250)</div><div class='add'>+		return 0x70;</div><div class='add'>+	else</div><div class='add'>+		return 0x60;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reset_stop_ring(u32 *regs, struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	int x;</div><div class='add'>+</div><div class='add'>+	x = lrc_ring_mi_mode(hwe);</div><div class='add'>+	regs[x + 1] &amp;= ~STOP_RING;</div><div class='add'>+	regs[x + 1] |= STOP_RING &lt;&lt; 16;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_lrc_ring_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return lrc-&gt;ring.size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Make the magic macros work */</div><div class='add'>+#define __xe_lrc_pphwsp_offset xe_lrc_pphwsp_offset</div><div class='add'>+</div><div class='add'>+#define LRC_SEQNO_PPHWSP_OFFSET 512</div><div class='add'>+#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)</div><div class='add'>+#define LRC_PARALLEL_PPHWSP_OFFSET 2048</div><div class='add'>+#define LRC_PPHWSP_SIZE SZ_4K</div><div class='add'>+</div><div class='add'>+static size_t lrc_reg_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250)</div><div class='add'>+		return 96 * sizeof(u32);</div><div class='add'>+	else</div><div class='add'>+		return 80 * sizeof(u32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+size_t xe_lrc_skip_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return LRC_PPHWSP_SIZE + lrc_reg_size(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	/* The seqno is stored in the driver-defined portion of PPHWSP */</div><div class='add'>+	return xe_lrc_pphwsp_offset(lrc) + LRC_SEQNO_PPHWSP_OFFSET;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_lrc_start_seqno_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	/* The start seqno is stored in the driver-defined portion of PPHWSP */</div><div class='add'>+	return xe_lrc_pphwsp_offset(lrc) + LRC_START_SEQNO_PPHWSP_OFFSET;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_lrc_parallel_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	/* The parallel is stored in the driver-defined portion of PPHWSP */</div><div class='add'>+	return xe_lrc_pphwsp_offset(lrc) + LRC_PARALLEL_PPHWSP_OFFSET;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_lrc_regs_offset(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return xe_lrc_pphwsp_offset(lrc) + LRC_PPHWSP_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define DECL_MAP_ADDR_HELPERS(elem) \</div><div class='add'>+static inline struct iosys_map __xe_lrc_##elem##_map(struct xe_lrc *lrc) \</div><div class='add'>+{ \</div><div class='add'>+	struct iosys_map map = lrc-&gt;bo-&gt;vmap; \</div><div class='add'>+\</div><div class='add'>+	xe_assert(lrc_to_xe(lrc), !iosys_map_is_null(&amp;map));  \</div><div class='add'>+	iosys_map_incr(&amp;map, __xe_lrc_##elem##_offset(lrc)); \</div><div class='add'>+	return map; \</div><div class='add'>+} \</div><div class='add'>+static inline u32 __xe_lrc_##elem##_ggtt_addr(struct xe_lrc *lrc) \</div><div class='add'>+{ \</div><div class='add'>+	return xe_bo_ggtt_addr(lrc-&gt;bo) + __xe_lrc_##elem##_offset(lrc); \</div><div class='add'>+} \</div><div class='add'>+</div><div class='add'>+DECL_MAP_ADDR_HELPERS(ring)</div><div class='add'>+DECL_MAP_ADDR_HELPERS(pphwsp)</div><div class='add'>+DECL_MAP_ADDR_HELPERS(seqno)</div><div class='add'>+DECL_MAP_ADDR_HELPERS(regs)</div><div class='add'>+DECL_MAP_ADDR_HELPERS(start_seqno)</div><div class='add'>+DECL_MAP_ADDR_HELPERS(parallel)</div><div class='add'>+</div><div class='add'>+#undef DECL_MAP_ADDR_HELPERS</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return __xe_lrc_pphwsp_ggtt_addr(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = lrc_to_xe(lrc);</div><div class='add'>+	struct iosys_map map;</div><div class='add'>+</div><div class='add'>+	map = __xe_lrc_regs_map(lrc);</div><div class='add'>+	iosys_map_incr(&amp;map, reg_nr * sizeof(u32));</div><div class='add'>+	return xe_map_read32(xe, &amp;map);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = lrc_to_xe(lrc);</div><div class='add'>+	struct iosys_map map;</div><div class='add'>+</div><div class='add'>+	map = __xe_lrc_regs_map(lrc);</div><div class='add'>+	iosys_map_incr(&amp;map, reg_nr * sizeof(u32));</div><div class='add'>+	xe_map_write32(xe, &amp;map, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void *empty_lrc_data(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(hwe-&gt;gt);</div><div class='add'>+	void *data;</div><div class='add'>+	u32 *regs;</div><div class='add'>+</div><div class='add'>+	data = kzalloc(xe_lrc_size(xe, hwe-&gt;class), GFP_KERNEL);</div><div class='add'>+	if (!data)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	/* 1st page: Per-Process of HW status Page */</div><div class='add'>+	regs = data + LRC_PPHWSP_SIZE;</div><div class='add'>+	set_offsets(regs, reg_offsets(xe, hwe-&gt;class), hwe);</div><div class='add'>+	set_context_control(regs, hwe);</div><div class='add'>+	reset_stop_ring(regs, hwe);</div><div class='add'>+</div><div class='add'>+	return data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	u64 desc = xe_vm_pdp4_descriptor(vm, lrc-&gt;tile);</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_PDP0_UDW, upper_32_bits(desc));</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_PDP0_LDW, lower_32_bits(desc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define PVC_CTX_ASID		(0x2e + 1)</div><div class='add'>+#define PVC_CTX_ACC_CTR_THOLD	(0x2a + 1)</div><div class='add'>+#define ACC_GRANULARITY_S       20</div><div class='add'>+#define ACC_NOTIFY_S            16</div><div class='add'>+</div><div class='add'>+int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,</div><div class='add'>+		struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct iosys_map map;</div><div class='add'>+	void *init_data = NULL;</div><div class='add'>+	u32 arb_enable;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lrc-&gt;flags = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address</div><div class='add'>+	 * via VM bind calls.</div><div class='add'>+	 */</div><div class='add'>+	lrc-&gt;bo = xe_bo_create_pin_map(xe, tile, vm,</div><div class='add'>+				      ring_size + xe_lrc_size(xe, hwe-&gt;class),</div><div class='add'>+				      ttm_bo_type_kernel,</div><div class='add'>+				      XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				      XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(lrc-&gt;bo))</div><div class='add'>+		return PTR_ERR(lrc-&gt;bo);</div><div class='add'>+</div><div class='add'>+	lrc-&gt;tile = gt_to_tile(hwe-&gt;gt);</div><div class='add'>+	lrc-&gt;ring.size = ring_size;</div><div class='add'>+	lrc-&gt;ring.tail = 0;</div><div class='add'>+</div><div class='add'>+	xe_hw_fence_ctx_init(&amp;lrc-&gt;fence_ctx, hwe-&gt;gt,</div><div class='add'>+			     hwe-&gt;fence_irq, hwe-&gt;name);</div><div class='add'>+</div><div class='add'>+	if (!gt-&gt;default_lrc[hwe-&gt;class]) {</div><div class='add'>+		init_data = empty_lrc_data(hwe);</div><div class='add'>+		if (!init_data) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_lrc_finish;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Init Per-Process of HW status Page, LRC / context state to known</div><div class='add'>+	 * values</div><div class='add'>+	 */</div><div class='add'>+	map = __xe_lrc_pphwsp_map(lrc);</div><div class='add'>+	if (!init_data) {</div><div class='add'>+		xe_map_memset(xe, &amp;map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */</div><div class='add'>+		xe_map_memcpy_to(xe, &amp;map, LRC_PPHWSP_SIZE,</div><div class='add'>+				 gt-&gt;default_lrc[hwe-&gt;class] + LRC_PPHWSP_SIZE,</div><div class='add'>+				 xe_lrc_size(xe, hwe-&gt;class) - LRC_PPHWSP_SIZE);</div><div class='add'>+	} else {</div><div class='add'>+		xe_map_memcpy_to(xe, &amp;map, 0, init_data,</div><div class='add'>+				 xe_lrc_size(xe, hwe-&gt;class));</div><div class='add'>+		kfree(init_data);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vm) {</div><div class='add'>+		xe_lrc_set_ppgtt(lrc, vm);</div><div class='add'>+</div><div class='add'>+		if (vm-&gt;xef)</div><div class='add'>+			xe_drm_client_add_bo(vm-&gt;xef-&gt;client, lrc-&gt;bo);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc));</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0);</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc-&gt;ring.tail);</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_CTL,</div><div class='add'>+			     RING_CTL_SIZE(lrc-&gt;ring.size) | RING_VALID);</div><div class='add'>+	if (xe-&gt;info.has_asid &amp;&amp; vm)</div><div class='add'>+		xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID,</div><div class='add'>+				     (q-&gt;usm.acc_granularity &lt;&lt;</div><div class='add'>+				      ACC_GRANULARITY_S) | vm-&gt;usm.asid);</div><div class='add'>+	if (xe-&gt;info.has_usm &amp;&amp; vm)</div><div class='add'>+		xe_lrc_write_ctx_reg(lrc, PVC_CTX_ACC_CTR_THOLD,</div><div class='add'>+				     (q-&gt;usm.acc_notify &lt;&lt; ACC_NOTIFY_S) |</div><div class='add'>+				     q-&gt;usm.acc_trigger);</div><div class='add'>+</div><div class='add'>+	lrc-&gt;desc = CTX_VALID;</div><div class='add'>+	lrc-&gt;desc |= LEGACY_64B_CONTEXT &lt;&lt; CTX_ADDRESSING_MODE_SHIFT;</div><div class='add'>+	/* TODO: Priority */</div><div class='add'>+</div><div class='add'>+	/* While this appears to have something about privileged batches or</div><div class='add'>+	 * some such, it really just means PPGTT mode.</div><div class='add'>+	 */</div><div class='add'>+	if (vm)</div><div class='add'>+		lrc-&gt;desc |= CTX_PRIVILEGE;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1250) {</div><div class='add'>+		lrc-&gt;desc |= (u64)hwe-&gt;instance &lt;&lt; ENGINE_INSTANCE_SHIFT;</div><div class='add'>+		lrc-&gt;desc |= (u64)hwe-&gt;class &lt;&lt; ENGINE_CLASS_SHIFT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	arb_enable = MI_ARB_ON_OFF | MI_ARB_ENABLE;</div><div class='add'>+	xe_lrc_write_ring(lrc, &amp;arb_enable, sizeof(arb_enable));</div><div class='add'>+</div><div class='add'>+	map = __xe_lrc_seqno_map(lrc);</div><div class='add'>+	xe_map_write32(lrc_to_xe(lrc), &amp;map, lrc-&gt;fence_ctx.next_seqno - 1);</div><div class='add'>+</div><div class='add'>+	map = __xe_lrc_start_seqno_map(lrc);</div><div class='add'>+	xe_map_write32(lrc_to_xe(lrc), &amp;map, lrc-&gt;fence_ctx.next_seqno - 1);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_lrc_finish:</div><div class='add'>+	xe_lrc_finish(lrc);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_lrc_finish(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	xe_hw_fence_ctx_finish(&amp;lrc-&gt;fence_ctx);</div><div class='add'>+	xe_bo_lock(lrc-&gt;bo, false);</div><div class='add'>+	xe_bo_unpin(lrc-&gt;bo);</div><div class='add'>+	xe_bo_unlock(lrc-&gt;bo);</div><div class='add'>+	xe_bo_put(lrc-&gt;bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head)</div><div class='add'>+{</div><div class='add'>+	xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, head);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_ring_head(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return xe_lrc_read_ctx_reg(lrc, CTX_RING_HEAD) &amp; HEAD_ADDR;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_ring_space(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	const u32 head = xe_lrc_ring_head(lrc);</div><div class='add'>+	const u32 tail = lrc-&gt;ring.tail;</div><div class='add'>+	const u32 size = lrc-&gt;ring.size;</div><div class='add'>+</div><div class='add'>+	return ((head - tail - 1) &amp; (size - 1)) + 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __xe_lrc_write_ring(struct xe_lrc *lrc, struct iosys_map ring,</div><div class='add'>+				const void *data, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = lrc_to_xe(lrc);</div><div class='add'>+</div><div class='add'>+	iosys_map_incr(&amp;ring, lrc-&gt;ring.tail);</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;ring, 0, data, size);</div><div class='add'>+	lrc-&gt;ring.tail = (lrc-&gt;ring.tail + size) &amp; (lrc-&gt;ring.size - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_lrc_write_ring(struct xe_lrc *lrc, const void *data, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = lrc_to_xe(lrc);</div><div class='add'>+	struct iosys_map ring;</div><div class='add'>+	u32 rhs;</div><div class='add'>+	size_t aligned_size;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, IS_ALIGNED(size, 4));</div><div class='add'>+	aligned_size = ALIGN(size, 8);</div><div class='add'>+</div><div class='add'>+	ring = __xe_lrc_ring_map(lrc);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, lrc-&gt;ring.tail &lt; lrc-&gt;ring.size);</div><div class='add'>+	rhs = lrc-&gt;ring.size - lrc-&gt;ring.tail;</div><div class='add'>+	if (size &gt; rhs) {</div><div class='add'>+		__xe_lrc_write_ring(lrc, ring, data, rhs);</div><div class='add'>+		__xe_lrc_write_ring(lrc, ring, data + rhs, size - rhs);</div><div class='add'>+	} else {</div><div class='add'>+		__xe_lrc_write_ring(lrc, ring, data, size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (aligned_size &gt; size) {</div><div class='add'>+		u32 noop = MI_NOOP;</div><div class='add'>+</div><div class='add'>+		__xe_lrc_write_ring(lrc, ring, &amp;noop, sizeof(noop));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_lrc_descriptor(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return lrc-&gt;desc | xe_lrc_ggtt_addr(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_seqno_ggtt_addr(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return __xe_lrc_seqno_ggtt_addr(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dma_fence *xe_lrc_create_seqno_fence(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return &amp;xe_hw_fence_create(&amp;lrc-&gt;fence_ctx,</div><div class='add'>+				   __xe_lrc_seqno_map(lrc))-&gt;dma;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+s32 xe_lrc_seqno(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	struct iosys_map map = __xe_lrc_seqno_map(lrc);</div><div class='add'>+</div><div class='add'>+	return xe_map_read32(lrc_to_xe(lrc), &amp;map);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+s32 xe_lrc_start_seqno(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	struct iosys_map map = __xe_lrc_start_seqno_map(lrc);</div><div class='add'>+</div><div class='add'>+	return xe_map_read32(lrc_to_xe(lrc), &amp;map);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_start_seqno_ggtt_addr(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return __xe_lrc_start_seqno_ggtt_addr(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_parallel_ggtt_addr(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return __xe_lrc_parallel_ggtt_addr(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc)</div><div class='add'>+{</div><div class='add'>+	return __xe_lrc_parallel_map(lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int instr_dw(u32 cmd_header)</div><div class='add'>+{</div><div class='add'>+	/* GFXPIPE "SINGLE_DW" opcodes are a single dword */</div><div class='add'>+	if ((cmd_header &amp; (XE_INSTR_CMD_TYPE | GFXPIPE_PIPELINE)) ==</div><div class='add'>+	    GFXPIPE_SINGLE_DW_CMD(0, 0))</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	/* 3DSTATE_SO_DECL_LIST has a 9-bit dword length rather than 8 */</div><div class='add'>+	if ((cmd_header &amp; GFXPIPE_MATCH_MASK) == CMD_3DSTATE_SO_DECL_LIST)</div><div class='add'>+		return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2;</div><div class='add'>+</div><div class='add'>+	/* Most instructions have the # of dwords (minus 2) in 7:0 */</div><div class='add'>+	return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dump_mi_command(struct drm_printer *p,</div><div class='add'>+			   struct xe_gt *gt,</div><div class='add'>+			   u32 *dw,</div><div class='add'>+			   int remaining_dw)</div><div class='add'>+{</div><div class='add'>+	u32 inst_header = *dw;</div><div class='add'>+	u32 numdw = instr_dw(inst_header);</div><div class='add'>+	u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header);</div><div class='add'>+	int num_noop;</div><div class='add'>+</div><div class='add'>+	/* First check for commands that don't have/use a '# DW' field */</div><div class='add'>+	switch (inst_header &amp; MI_OPCODE) {</div><div class='add'>+	case MI_NOOP:</div><div class='add'>+		num_noop = 1;</div><div class='add'>+		while (num_noop &lt; remaining_dw &amp;&amp;</div><div class='add'>+		       (*(++dw) &amp; REG_GENMASK(31, 23)) == MI_NOOP)</div><div class='add'>+			num_noop++;</div><div class='add'>+		drm_printf(p, "[%#010x] MI_NOOP (%d dwords)\n", inst_header, num_noop);</div><div class='add'>+		return num_noop;</div><div class='add'>+</div><div class='add'>+	case MI_TOPOLOGY_FILTER:</div><div class='add'>+		drm_printf(p, "[%#010x] MI_TOPOLOGY_FILTER\n", inst_header);</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	case MI_BATCH_BUFFER_END:</div><div class='add'>+		drm_printf(p, "[%#010x] MI_BATCH_BUFFER_END\n", inst_header);</div><div class='add'>+		/* Return 'remaining_dw' to consume the rest of the LRC */</div><div class='add'>+		return remaining_dw;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Any remaining commands include a # of dwords.  We should make sure</div><div class='add'>+	 * it doesn't exceed the remaining size of the LRC.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_gt_WARN_ON(gt, numdw &gt; remaining_dw))</div><div class='add'>+		numdw = remaining_dw;</div><div class='add'>+</div><div class='add'>+	switch (inst_header &amp; MI_OPCODE) {</div><div class='add'>+	case MI_LOAD_REGISTER_IMM:</div><div class='add'>+		drm_printf(p, "[%#010x] MI_LOAD_REGISTER_IMM: %d regs\n",</div><div class='add'>+			   inst_header, (numdw - 1) / 2);</div><div class='add'>+		for (int i = 1; i &lt; numdw; i += 2)</div><div class='add'>+			drm_printf(p, " - %#6x = %#010x\n", dw[i], dw[i + 1]);</div><div class='add'>+		return numdw;</div><div class='add'>+</div><div class='add'>+	case MI_FORCE_WAKEUP:</div><div class='add'>+		drm_printf(p, "[%#010x] MI_FORCE_WAKEUP\n", inst_header);</div><div class='add'>+		return numdw;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		drm_printf(p, "[%#010x] unknown MI opcode %#x, likely %d dwords\n",</div><div class='add'>+			   inst_header, opcode, numdw);</div><div class='add'>+		return numdw;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dump_gfxpipe_command(struct drm_printer *p,</div><div class='add'>+				struct xe_gt *gt,</div><div class='add'>+				u32 *dw,</div><div class='add'>+				int remaining_dw)</div><div class='add'>+{</div><div class='add'>+	u32 numdw = instr_dw(*dw);</div><div class='add'>+	u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw);</div><div class='add'>+	u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw);</div><div class='add'>+	u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Make sure we haven't mis-parsed a number of dwords that exceeds the</div><div class='add'>+	 * remaining size of the LRC.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_gt_WARN_ON(gt, numdw &gt; remaining_dw))</div><div class='add'>+		numdw = remaining_dw;</div><div class='add'>+</div><div class='add'>+	switch (*dw &amp; GFXPIPE_MATCH_MASK) {</div><div class='add'>+#define MATCH(cmd) \</div><div class='add'>+	case cmd: \</div><div class='add'>+		drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \</div><div class='add'>+		return numdw</div><div class='add'>+#define MATCH3D(cmd) \</div><div class='add'>+	case CMD_##cmd: \</div><div class='add'>+		drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \</div><div class='add'>+		return numdw</div><div class='add'>+</div><div class='add'>+	MATCH(STATE_BASE_ADDRESS);</div><div class='add'>+	MATCH(STATE_SIP);</div><div class='add'>+	MATCH(GPGPU_CSR_BASE_ADDRESS);</div><div class='add'>+	MATCH(STATE_COMPUTE_MODE);</div><div class='add'>+	MATCH3D(3DSTATE_BTD);</div><div class='add'>+</div><div class='add'>+	MATCH3D(3DSTATE_VF_STATISTICS);</div><div class='add'>+</div><div class='add'>+	MATCH(PIPELINE_SELECT);</div><div class='add'>+</div><div class='add'>+	MATCH3D(3DSTATE_DRAWING_RECTANGLE_FAST);</div><div class='add'>+	MATCH3D(3DSTATE_CLEAR_PARAMS);</div><div class='add'>+	MATCH3D(3DSTATE_DEPTH_BUFFER);</div><div class='add'>+	MATCH3D(3DSTATE_STENCIL_BUFFER);</div><div class='add'>+	MATCH3D(3DSTATE_HIER_DEPTH_BUFFER);</div><div class='add'>+	MATCH3D(3DSTATE_VERTEX_BUFFERS);</div><div class='add'>+	MATCH3D(3DSTATE_VERTEX_ELEMENTS);</div><div class='add'>+	MATCH3D(3DSTATE_INDEX_BUFFER);</div><div class='add'>+	MATCH3D(3DSTATE_VF);</div><div class='add'>+	MATCH3D(3DSTATE_MULTISAMPLE);</div><div class='add'>+	MATCH3D(3DSTATE_CC_STATE_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_SCISSOR_STATE_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_VS);</div><div class='add'>+	MATCH3D(3DSTATE_GS);</div><div class='add'>+	MATCH3D(3DSTATE_CLIP);</div><div class='add'>+	MATCH3D(3DSTATE_SF);</div><div class='add'>+	MATCH3D(3DSTATE_WM);</div><div class='add'>+	MATCH3D(3DSTATE_CONSTANT_VS);</div><div class='add'>+	MATCH3D(3DSTATE_CONSTANT_GS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLE_MASK);</div><div class='add'>+	MATCH3D(3DSTATE_CONSTANT_HS);</div><div class='add'>+	MATCH3D(3DSTATE_CONSTANT_DS);</div><div class='add'>+	MATCH3D(3DSTATE_HS);</div><div class='add'>+	MATCH3D(3DSTATE_TE);</div><div class='add'>+	MATCH3D(3DSTATE_DS);</div><div class='add'>+	MATCH3D(3DSTATE_STREAMOUT);</div><div class='add'>+	MATCH3D(3DSTATE_SBE);</div><div class='add'>+	MATCH3D(3DSTATE_PS);</div><div class='add'>+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);</div><div class='add'>+	MATCH3D(3DSTATE_CPS_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC);</div><div class='add'>+	MATCH3D(3DSTATE_BLEND_STATE_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_VS);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_HS);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_DS);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_GS);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_PS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_VS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_HS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_DS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_GS);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_PS);</div><div class='add'>+	MATCH3D(3DSTATE_VF_INSTANCING);</div><div class='add'>+	MATCH3D(3DSTATE_VF_SGVS);</div><div class='add'>+	MATCH3D(3DSTATE_VF_TOPOLOGY);</div><div class='add'>+	MATCH3D(3DSTATE_WM_CHROMAKEY);</div><div class='add'>+	MATCH3D(3DSTATE_PS_BLEND);</div><div class='add'>+	MATCH3D(3DSTATE_WM_DEPTH_STENCIL);</div><div class='add'>+	MATCH3D(3DSTATE_PS_EXTRA);</div><div class='add'>+	MATCH3D(3DSTATE_RASTER);</div><div class='add'>+	MATCH3D(3DSTATE_SBE_SWIZ);</div><div class='add'>+	MATCH3D(3DSTATE_WM_HZ_OP);</div><div class='add'>+	MATCH3D(3DSTATE_VF_COMPONENT_PACKING);</div><div class='add'>+	MATCH3D(3DSTATE_VF_SGVS_2);</div><div class='add'>+	MATCH3D(3DSTATE_VFG);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_VS);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_HS);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_DS);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_GS);</div><div class='add'>+	MATCH3D(3DSTATE_SO_BUFFER_INDEX_0);</div><div class='add'>+	MATCH3D(3DSTATE_SO_BUFFER_INDEX_1);</div><div class='add'>+	MATCH3D(3DSTATE_SO_BUFFER_INDEX_2);</div><div class='add'>+	MATCH3D(3DSTATE_SO_BUFFER_INDEX_3);</div><div class='add'>+	MATCH3D(3DSTATE_PRIMITIVE_REPLICATION);</div><div class='add'>+	MATCH3D(3DSTATE_TBIMR_TILE_PASS_INFO);</div><div class='add'>+	MATCH3D(3DSTATE_AMFS);</div><div class='add'>+	MATCH3D(3DSTATE_DEPTH_BOUNDS);</div><div class='add'>+	MATCH3D(3DSTATE_AMFS_TEXTURE_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_CONSTANT_TS_POINTER);</div><div class='add'>+	MATCH3D(3DSTATE_MESH_CONTROL);</div><div class='add'>+	MATCH3D(3DSTATE_MESH_DISTRIB);</div><div class='add'>+	MATCH3D(3DSTATE_TASK_REDISTRIB);</div><div class='add'>+	MATCH3D(3DSTATE_MESH_SHADER);</div><div class='add'>+	MATCH3D(3DSTATE_MESH_SHADER_DATA);</div><div class='add'>+	MATCH3D(3DSTATE_TASK_CONTROL);</div><div class='add'>+	MATCH3D(3DSTATE_TASK_SHADER);</div><div class='add'>+	MATCH3D(3DSTATE_TASK_SHADER_DATA);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_MESH);</div><div class='add'>+	MATCH3D(3DSTATE_URB_ALLOC_TASK);</div><div class='add'>+	MATCH3D(3DSTATE_CLIP_MESH);</div><div class='add'>+	MATCH3D(3DSTATE_SBE_MESH);</div><div class='add'>+	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);</div><div class='add'>+</div><div class='add'>+	MATCH3D(3DSTATE_DRAWING_RECTANGLE);</div><div class='add'>+	MATCH3D(3DSTATE_CHROMA_KEY);</div><div class='add'>+	MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);</div><div class='add'>+	MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);</div><div class='add'>+	MATCH3D(3DSTATE_LINE_STIPPLE);</div><div class='add'>+	MATCH3D(3DSTATE_AA_LINE_PARAMETERS);</div><div class='add'>+	MATCH3D(3DSTATE_MONOFILTER_SIZE);</div><div class='add'>+	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_VS);</div><div class='add'>+	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_HS);</div><div class='add'>+	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_DS);</div><div class='add'>+	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_GS);</div><div class='add'>+	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_PS);</div><div class='add'>+	MATCH3D(3DSTATE_SO_DECL_LIST);</div><div class='add'>+	MATCH3D(3DSTATE_SO_BUFFER);</div><div class='add'>+	MATCH3D(3DSTATE_BINDING_TABLE_POOL_ALLOC);</div><div class='add'>+	MATCH3D(3DSTATE_SAMPLE_PATTERN);</div><div class='add'>+	MATCH3D(3DSTATE_3D_MODE);</div><div class='add'>+	MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);</div><div class='add'>+	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);</div><div class='add'>+	MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",</div><div class='add'>+			   *dw, pipeline, opcode, subopcode, numdw);</div><div class='add'>+		return numdw;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_lrc_dump_default(struct drm_printer *p,</div><div class='add'>+			 struct xe_gt *gt,</div><div class='add'>+			 enum xe_engine_class hwe_class)</div><div class='add'>+{</div><div class='add'>+	u32 *dw;</div><div class='add'>+	int remaining_dw, num_dw;</div><div class='add'>+</div><div class='add'>+	if (!gt-&gt;default_lrc[hwe_class]) {</div><div class='add'>+		drm_printf(p, "No default LRC for class %d\n", hwe_class);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Skip the beginning of the LRC since it contains the per-process</div><div class='add'>+	 * hardware status page.</div><div class='add'>+	 */</div><div class='add'>+	dw = gt-&gt;default_lrc[hwe_class] + LRC_PPHWSP_SIZE;</div><div class='add'>+	remaining_dw = (xe_lrc_size(gt_to_xe(gt), hwe_class) - LRC_PPHWSP_SIZE) / 4;</div><div class='add'>+</div><div class='add'>+	while (remaining_dw &gt; 0) {</div><div class='add'>+		if ((*dw &amp; XE_INSTR_CMD_TYPE) == XE_INSTR_MI) {</div><div class='add'>+			num_dw = dump_mi_command(p, gt, dw, remaining_dw);</div><div class='add'>+		} else if ((*dw &amp; XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {</div><div class='add'>+			num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);</div><div class='add'>+		} else {</div><div class='add'>+			num_dw = min(instr_dw(*dw), remaining_dw);</div><div class='add'>+			drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",</div><div class='add'>+				   *dw, REG_FIELD_GET(XE_INSTR_CMD_TYPE, *dw),</div><div class='add'>+				   num_dw);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dw += num_dw;</div><div class='add'>+		remaining_dw -= num_dw;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct instr_state {</div><div class='add'>+	u32 instr;</div><div class='add'>+	u16 num_dw;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct instr_state xe_hpg_svg_state[] = {</div><div class='add'>+	{ .instr = CMD_3DSTATE_CONSTANT_VS, .num_dw = 11 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_CONSTANT_HS, .num_dw = 11 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_CONSTANT_DS, .num_dw = 11 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_CONSTANT_GS, .num_dw = 11 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VERTEX_ELEMENTS, .num_dw = 69 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VF_COMPONENT_PACKING, .num_dw = 5 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VF_SGVS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VF_SGVS_2, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VS, .num_dw = 9 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_VS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_VS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_VS, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_STREAMOUT, .num_dw = 5 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SO_BUFFER_INDEX_0, .num_dw = 8 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SO_BUFFER_INDEX_1, .num_dw = 8 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SO_BUFFER_INDEX_2, .num_dw = 8 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SO_BUFFER_INDEX_3, .num_dw = 8 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_CLIP, .num_dw = 4 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_PRIMITIVE_REPLICATION, .num_dw = 6 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_CLIP_MESH, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SF, .num_dw = 4 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SCISSOR_STATE_POINTERS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_RASTER, .num_dw = 5 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TBIMR_TILE_PASS_INFO, .num_dw = 4 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_WM_HZ_OP, .num_dw = 6 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_MULTISAMPLE, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_HS, .num_dw = 9 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_HS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_HS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_HS, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TASK_CONTROL, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TASK_SHADER, .num_dw = 7 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TASK_SHADER_DATA, .num_dw = 10 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_TASK, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TE, .num_dw = 5 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_TASK_REDISTRIB, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_DS, .num_dw = 11 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_DS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_DS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_DS, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_GS, .num_dw = 10 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_BINDING_TABLE_POINTERS_GS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_SAMPLER_STATE_POINTERS_GS, .num_dw = 2 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_GS, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_MESH_CONTROL, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_MESH_SHADER_DATA, .num_dw = 10 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_URB_ALLOC_MESH, .num_dw = 3 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_MESH_SHADER, .num_dw = 8 },</div><div class='add'>+	{ .instr = CMD_3DSTATE_DRAWING_RECTANGLE, .num_dw = 4 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = q-&gt;hwe-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	const struct instr_state *state_table = NULL;</div><div class='add'>+	int state_table_size = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * At the moment we only need to emit non-register state for the RCS</div><div class='add'>+	 * engine.</div><div class='add'>+	 */</div><div class='add'>+	if (q-&gt;hwe-&gt;class != XE_ENGINE_CLASS_RENDER)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (GRAPHICS_VERx100(xe)) {</div><div class='add'>+	case 1255:</div><div class='add'>+	case 1270 ... 2004:</div><div class='add'>+		state_table = xe_hpg_svg_state;</div><div class='add'>+		state_table_size = ARRAY_SIZE(xe_hpg_svg_state);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		xe_gt_dbg(gt, "No non-register state to emit on graphics ver %d.%02d\n",</div><div class='add'>+			  GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; state_table_size; i++) {</div><div class='add'>+		u32 instr = state_table[i].instr;</div><div class='add'>+		u16 num_dw = state_table[i].num_dw;</div><div class='add'>+		bool is_single_dw = ((instr &amp; GFXPIPE_PIPELINE) == PIPELINE_SINGLE_DW);</div><div class='add'>+</div><div class='add'>+		xe_gt_assert(gt, (instr &amp; XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE);</div><div class='add'>+		xe_gt_assert(gt, num_dw != 0);</div><div class='add'>+		xe_gt_assert(gt, is_single_dw ^ (num_dw &gt; 1));</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Xe2's SVG context is the same as the one on DG2 / MTL</div><div class='add'>+		 * except that 3DSTATE_DRAWING_RECTANGLE (non-pipelined) has</div><div class='add'>+		 * been replaced by 3DSTATE_DRAWING_RECTANGLE_FAST (pipelined).</div><div class='add'>+		 * Just make the replacement here rather than defining a</div><div class='add'>+		 * whole separate table for the single trivial change.</div><div class='add'>+		 */</div><div class='add'>+		if (GRAPHICS_VER(xe) &gt;= 20 &amp;&amp;</div><div class='add'>+		    instr == CMD_3DSTATE_DRAWING_RECTANGLE)</div><div class='add'>+			instr = CMD_3DSTATE_DRAWING_RECTANGLE_FAST;</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len] = instr;</div><div class='add'>+		if (!is_single_dw)</div><div class='add'>+			bb-&gt;cs[bb-&gt;len] |= (num_dw - 2);</div><div class='add'>+</div><div class='add'>+		bb-&gt;len += num_dw;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h<br/>new file mode 100644<br/>index 000000000000..28b1d3f404d4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lrc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc.h</a></div><div class='hunk'>@@ -0,0 +1,58 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_LRC_H_</div><div class='add'>+#define _XE_LRC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_lrc_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_bb;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+enum xe_engine_class;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+#define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4)</div><div class='add'>+</div><div class='add'>+int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,</div><div class='add'>+		struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size);</div><div class='add'>+void xe_lrc_finish(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class);</div><div class='add'>+u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head);</div><div class='add'>+u32 xe_lrc_ring_head(struct xe_lrc *lrc);</div><div class='add'>+u32 xe_lrc_ring_space(struct xe_lrc *lrc);</div><div class='add'>+void xe_lrc_write_ring(struct xe_lrc *lrc, const void *data, size_t size);</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc);</div><div class='add'>+u32 *xe_lrc_regs(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);</div><div class='add'>+void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);</div><div class='add'>+</div><div class='add'>+u64 xe_lrc_descriptor(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_seqno_ggtt_addr(struct xe_lrc *lrc);</div><div class='add'>+struct dma_fence *xe_lrc_create_seqno_fence(struct xe_lrc *lrc);</div><div class='add'>+s32 xe_lrc_seqno(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_start_seqno_ggtt_addr(struct xe_lrc *lrc);</div><div class='add'>+s32 xe_lrc_start_seqno(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+u32 xe_lrc_parallel_ggtt_addr(struct xe_lrc *lrc);</div><div class='add'>+struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc);</div><div class='add'>+</div><div class='add'>+size_t xe_lrc_skip_size(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_lrc_dump_default(struct drm_printer *p,</div><div class='add'>+			 struct xe_gt *gt,</div><div class='add'>+			 enum xe_engine_class);</div><div class='add'>+</div><div class='add'>+void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h<br/>new file mode 100644<br/>index 000000000000..78220336062c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_lrc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_lrc_types.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_LRC_TYPES_H_</div><div class='add'>+#define _XE_LRC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_hw_fence_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_lrc - Logical ring context (LRC) and submission ring object</div><div class='add'>+ */</div><div class='add'>+struct xe_lrc {</div><div class='add'>+	/**</div><div class='add'>+	 * @bo: buffer object (memory) for logical ring context, per process HW</div><div class='add'>+	 * status page, and submission ring.</div><div class='add'>+	 */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	/** @tile: tile which this LRC belongs to */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	/** @flags: LRC flags */</div><div class='add'>+	u32 flags;</div><div class='add'>+</div><div class='add'>+	/** @ring: submission ring state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @size: size of submission ring */</div><div class='add'>+		u32 size;</div><div class='add'>+		/** @tail: tail of submission ring */</div><div class='add'>+		u32 tail;</div><div class='add'>+		/** @old_tail: shadow of tail */</div><div class='add'>+		u32 old_tail;</div><div class='add'>+	} ring;</div><div class='add'>+</div><div class='add'>+	/** @desc: LRC descriptor */</div><div class='add'>+	u64 desc;</div><div class='add'>+</div><div class='add'>+	/** @fence_ctx: context for hw fence */</div><div class='add'>+	struct xe_hw_fence_ctx fence_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h<br/>new file mode 100644<br/>index 000000000000..daf56c846d03<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_macros.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_macros.h</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MACROS_H_</div><div class='add'>+#define _XE_MACROS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bug.h&gt;</div><div class='add'>+</div><div class='add'>+#define XE_WARN_ON WARN_ON</div><div class='add'>+</div><div class='add'>+#define XE_IOCTL_DBG(xe, cond) \</div><div class='add'>+	((cond) &amp;&amp; (drm_dbg(&amp;(xe)-&gt;drm, \</div><div class='add'>+			    "Ioctl argument check failed at %s:%d: %s", \</div><div class='add'>+			    __FILE__, __LINE__, #cond), 1))</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_map.h b/drivers/gpu/drm/xe/xe_map.h<br/>new file mode 100644<br/>index 000000000000..f62e0c8b67ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_map.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_map.h</a></div><div class='hunk'>@@ -0,0 +1,93 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MAP_H_</div><div class='add'>+#define _XE_MAP_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iosys-map.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;xe_device.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Map layer</div><div class='add'>+ *</div><div class='add'>+ * All access to any memory shared with a device (both sysmem and vram) in the</div><div class='add'>+ * XE driver should go through this layer (xe_map). This layer is built on top</div><div class='add'>+ * of :ref:`driver-api/device-io:Generalizing Access to System and I/O Memory`</div><div class='add'>+ * and with extra hooks into the XE driver that allows adding asserts to memory</div><div class='add'>+ * accesses (e.g. for blocking runtime_pm D3Cold on Discrete Graphics).</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static inline void xe_map_memcpy_to(struct xe_device *xe, struct iosys_map *dst,</div><div class='add'>+				    size_t dst_offset, const void *src,</div><div class='add'>+				    size_t len)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(xe);</div><div class='add'>+	iosys_map_memcpy_to(dst, dst_offset, src, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_map_memcpy_from(struct xe_device *xe, void *dst,</div><div class='add'>+				      const struct iosys_map *src,</div><div class='add'>+				      size_t src_offset, size_t len)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(xe);</div><div class='add'>+	iosys_map_memcpy_from(dst, src, src_offset, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_map_memset(struct xe_device *xe,</div><div class='add'>+				 struct iosys_map *dst, size_t offset,</div><div class='add'>+				 int value, size_t len)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(xe);</div><div class='add'>+	iosys_map_memset(dst, offset, value, len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* FIXME: We likely should kill these two functions sooner or later */</div><div class='add'>+static inline u32 xe_map_read32(struct xe_device *xe, struct iosys_map *map)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(xe);</div><div class='add'>+</div><div class='add'>+	if (map-&gt;is_iomem)</div><div class='add'>+		return readl(map-&gt;vaddr_iomem);</div><div class='add'>+	else</div><div class='add'>+		return READ_ONCE(*(u32 *)map-&gt;vaddr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_map_write32(struct xe_device *xe, struct iosys_map *map,</div><div class='add'>+				  u32 val)</div><div class='add'>+{</div><div class='add'>+	xe_device_assert_mem_access(xe);</div><div class='add'>+</div><div class='add'>+	if (map-&gt;is_iomem)</div><div class='add'>+		writel(val, map-&gt;vaddr_iomem);</div><div class='add'>+	else</div><div class='add'>+		*(u32 *)map-&gt;vaddr = val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define xe_map_rd(xe__, map__, offset__, type__) ({			\</div><div class='add'>+	struct xe_device *__xe = xe__;					\</div><div class='add'>+	xe_device_assert_mem_access(__xe);				\</div><div class='add'>+	iosys_map_rd(map__, offset__, type__);				\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#define xe_map_wr(xe__, map__, offset__, type__, val__) ({		\</div><div class='add'>+	struct xe_device *__xe = xe__;					\</div><div class='add'>+	xe_device_assert_mem_access(__xe);				\</div><div class='add'>+	iosys_map_wr(map__, offset__, type__, val__);			\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#define xe_map_rd_field(xe__, map__, struct_offset__, struct_type__, field__) ({	\</div><div class='add'>+	struct xe_device *__xe = xe__;					\</div><div class='add'>+	xe_device_assert_mem_access(__xe);				\</div><div class='add'>+	iosys_map_rd_field(map__, struct_offset__, struct_type__, field__);		\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#define xe_map_wr_field(xe__, map__, struct_offset__, struct_type__, field__, val__) ({	\</div><div class='add'>+	struct xe_device *__xe = xe__;					\</div><div class='add'>+	xe_device_assert_mem_access(__xe);				\</div><div class='add'>+	iosys_map_wr_field(map__, struct_offset__, struct_type__, field__, val__);	\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c<br/>new file mode 100644<br/>index 000000000000..e05e9e7282b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_migrate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate.c</a></div><div class='hunk'>@@ -0,0 +1,1439 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2020 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "tests/xe_test.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bb.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+#include "xe_pt.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_sync.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_migrate - migrate context.</div><div class='add'>+ */</div><div class='add'>+struct xe_migrate {</div><div class='add'>+	/** @q: Default exec queue used for migration */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	/** @tile: Backpointer to the tile this struct xe_migrate belongs to. */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	/** @job_mutex: Timeline mutex for @eng. */</div><div class='add'>+	struct mutex job_mutex;</div><div class='add'>+	/** @pt_bo: Page-table buffer object. */</div><div class='add'>+	struct xe_bo *pt_bo;</div><div class='add'>+	/** @batch_base_ofs: VM offset of the migration batch buffer */</div><div class='add'>+	u64 batch_base_ofs;</div><div class='add'>+	/** @usm_batch_base_ofs: VM offset of the usm batch buffer */</div><div class='add'>+	u64 usm_batch_base_ofs;</div><div class='add'>+	/** @cleared_mem_ofs: VM offset of @cleared_bo. */</div><div class='add'>+	u64 cleared_mem_ofs;</div><div class='add'>+	/**</div><div class='add'>+	 * @fence: dma-fence representing the last migration job batch.</div><div class='add'>+	 * Protected by @job_mutex.</div><div class='add'>+	 */</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	/**</div><div class='add'>+	 * @vm_update_sa: For integrated, used to suballocate page-tables</div><div class='add'>+	 * out of the pt_bo.</div><div class='add'>+	 */</div><div class='add'>+	struct drm_suballoc_manager vm_update_sa;</div><div class='add'>+	/** @min_chunk_size: For dgfx, Minimum chunk size */</div><div class='add'>+	u64 min_chunk_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */</div><div class='add'>+#define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */</div><div class='add'>+#define NUM_KERNEL_PDE 17</div><div class='add'>+#define NUM_PT_SLOTS 32</div><div class='add'>+#define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tile_migrate_engine() - Get this tile's migrate engine.</div><div class='add'>+ * @tile: The tile.</div><div class='add'>+ *</div><div class='add'>+ * Returns the default migrate engine of this tile.</div><div class='add'>+ * TODO: Perhaps this function is slightly misplaced, and even unneeded?</div><div class='add'>+ *</div><div class='add'>+ * Return: The default migrate engine</div><div class='add'>+ */</div><div class='add'>+struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	return tile-&gt;migrate-&gt;q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_migrate_fini(struct drm_device *dev, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_migrate *m = arg;</div><div class='add'>+</div><div class='add'>+	xe_vm_lock(m-&gt;q-&gt;vm, false);</div><div class='add'>+	xe_bo_unpin(m-&gt;pt_bo);</div><div class='add'>+	xe_vm_unlock(m-&gt;q-&gt;vm);</div><div class='add'>+</div><div class='add'>+	dma_fence_put(m-&gt;fence);</div><div class='add'>+	xe_bo_put(m-&gt;pt_bo);</div><div class='add'>+	drm_suballoc_manager_fini(&amp;m-&gt;vm_update_sa);</div><div class='add'>+	mutex_destroy(&amp;m-&gt;job_mutex);</div><div class='add'>+	xe_vm_close_and_put(m-&gt;q-&gt;vm);</div><div class='add'>+	xe_exec_queue_put(m-&gt;q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_migrate_vm_addr(u64 slot, u32 level)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(slot &gt;= NUM_PT_SLOTS);</div><div class='add'>+</div><div class='add'>+	/* First slot is reserved for mapping of PT bo and bb, start from 1 */</div><div class='add'>+	return (slot + 1ULL) &lt;&lt; xe_pt_shift(level + 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Remove the DPA to get a correct offset into identity table for the</div><div class='add'>+	 * migrate offset</div><div class='add'>+	 */</div><div class='add'>+	addr -= xe-&gt;mem.vram.dpa_base;</div><div class='add'>+	return addr + (256ULL &lt;&lt; xe_pt_shift(2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,</div><div class='add'>+				 struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	u16 pat_index = xe-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+	u8 id = tile-&gt;id;</div><div class='add'>+	u32 num_entries = NUM_PT_SLOTS, num_level = vm-&gt;pt_root[id]-&gt;level;</div><div class='add'>+	u32 map_ofs, level, i;</div><div class='add'>+	struct xe_bo *bo, *batch = tile-&gt;mem.kernel_bb_pool-&gt;bo;</div><div class='add'>+	u64 entry;</div><div class='add'>+</div><div class='add'>+	/* Can't bump NUM_PT_SLOTS too high */</div><div class='add'>+	BUILD_BUG_ON(NUM_PT_SLOTS &gt; SZ_2M/XE_PAGE_SIZE);</div><div class='add'>+	/* Must be a multiple of 64K to support all platforms */</div><div class='add'>+	BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);</div><div class='add'>+	/* And one slot reserved for the 4KiB page table updates */</div><div class='add'>+	BUILD_BUG_ON(!(NUM_KERNEL_PDE &amp; 1));</div><div class='add'>+</div><div class='add'>+	/* Need to be sure everything fits in the first PT, or create more */</div><div class='add'>+	xe_tile_assert(tile, m-&gt;batch_base_ofs + batch-&gt;size &lt; SZ_2M);</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(vm-&gt;xe, tile, vm,</div><div class='add'>+				  num_entries * XE_PAGE_SIZE,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				  XE_BO_CREATE_PINNED_BIT);</div><div class='add'>+	if (IS_ERR(bo))</div><div class='add'>+		return PTR_ERR(bo);</div><div class='add'>+</div><div class='add'>+	entry = vm-&gt;pt_ops-&gt;pde_encode_bo(bo, bo-&gt;size - XE_PAGE_SIZE, pat_index);</div><div class='add'>+	xe_pt_write(xe, &amp;vm-&gt;pt_root[id]-&gt;bo-&gt;vmap, 0, entry);</div><div class='add'>+</div><div class='add'>+	map_ofs = (num_entries - num_level) * XE_PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+	/* Map the entire BO in our level 0 pt */</div><div class='add'>+	for (i = 0, level = 0; i &lt; num_entries; level++) {</div><div class='add'>+		entry = vm-&gt;pt_ops-&gt;pte_encode_bo(bo, i * XE_PAGE_SIZE,</div><div class='add'>+						  pat_index, 0);</div><div class='add'>+</div><div class='add'>+		xe_map_wr(xe, &amp;bo-&gt;vmap, map_ofs + level * 8, u64, entry);</div><div class='add'>+</div><div class='add'>+		if (vm-&gt;flags &amp; XE_VM_FLAG_64K)</div><div class='add'>+			i += 16;</div><div class='add'>+		else</div><div class='add'>+			i += 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe)) {</div><div class='add'>+		/* Write out batch too */</div><div class='add'>+		m-&gt;batch_base_ofs = NUM_PT_SLOTS * XE_PAGE_SIZE;</div><div class='add'>+		if (xe-&gt;info.has_usm) {</div><div class='add'>+			batch = tile-&gt;primary_gt-&gt;usm.bb_pool-&gt;bo;</div><div class='add'>+			m-&gt;usm_batch_base_ofs = m-&gt;batch_base_ofs;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; batch-&gt;size;</div><div class='add'>+		     i += vm-&gt;flags &amp; XE_VM_FLAG_64K ? XE_64K_PAGE_SIZE :</div><div class='add'>+		     XE_PAGE_SIZE) {</div><div class='add'>+			entry = vm-&gt;pt_ops-&gt;pte_encode_bo(batch, i,</div><div class='add'>+							  pat_index, 0);</div><div class='add'>+</div><div class='add'>+			xe_map_wr(xe, &amp;bo-&gt;vmap, map_ofs + level * 8, u64,</div><div class='add'>+				  entry);</div><div class='add'>+			level++;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		u64 batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+		m-&gt;batch_base_ofs = xe_migrate_vram_ofs(xe, batch_addr);</div><div class='add'>+</div><div class='add'>+		if (xe-&gt;info.has_usm) {</div><div class='add'>+			batch = tile-&gt;primary_gt-&gt;usm.bb_pool-&gt;bo;</div><div class='add'>+			batch_addr = xe_bo_addr(batch, 0, XE_PAGE_SIZE);</div><div class='add'>+			m-&gt;usm_batch_base_ofs = xe_migrate_vram_ofs(xe, batch_addr);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (level = 1; level &lt; num_level; level++) {</div><div class='add'>+		u32 flags = 0;</div><div class='add'>+</div><div class='add'>+		if (vm-&gt;flags &amp; XE_VM_FLAG_64K &amp;&amp; level == 1)</div><div class='add'>+			flags = XE_PDE_64K;</div><div class='add'>+</div><div class='add'>+		entry = vm-&gt;pt_ops-&gt;pde_encode_bo(bo, map_ofs + (level - 1) *</div><div class='add'>+						  XE_PAGE_SIZE, pat_index);</div><div class='add'>+		xe_map_wr(xe, &amp;bo-&gt;vmap, map_ofs + XE_PAGE_SIZE * level, u64,</div><div class='add'>+			  entry | flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Write PDE's that point to our BO. */</div><div class='add'>+	for (i = 0; i &lt; num_entries - num_level; i++) {</div><div class='add'>+		entry = vm-&gt;pt_ops-&gt;pde_encode_bo(bo, i * XE_PAGE_SIZE,</div><div class='add'>+						  pat_index);</div><div class='add'>+</div><div class='add'>+		xe_map_wr(xe, &amp;bo-&gt;vmap, map_ofs + XE_PAGE_SIZE +</div><div class='add'>+			  (i + 1) * 8, u64, entry);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set up a 1GiB NULL mapping at 255GiB offset. */</div><div class='add'>+	level = 2;</div><div class='add'>+	xe_map_wr(xe, &amp;bo-&gt;vmap, map_ofs + XE_PAGE_SIZE * level + 255 * 8, u64,</div><div class='add'>+		  vm-&gt;pt_ops-&gt;pte_encode_addr(xe, 0, pat_index, level, IS_DGFX(xe), 0)</div><div class='add'>+		  | XE_PTE_NULL);</div><div class='add'>+	m-&gt;cleared_mem_ofs = (255ULL &lt;&lt; xe_pt_shift(level));</div><div class='add'>+</div><div class='add'>+	/* Identity map the entire vram at 256GiB offset */</div><div class='add'>+	if (IS_DGFX(xe)) {</div><div class='add'>+		u64 pos, ofs, flags;</div><div class='add'>+</div><div class='add'>+		level = 2;</div><div class='add'>+		ofs = map_ofs + XE_PAGE_SIZE * level + 256 * 8;</div><div class='add'>+		flags = vm-&gt;pt_ops-&gt;pte_encode_addr(xe, 0, pat_index, level,</div><div class='add'>+						    true, 0);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Use 1GB pages, it shouldn't matter the physical amount of</div><div class='add'>+		 * vram is less, when we don't access it.</div><div class='add'>+		 */</div><div class='add'>+		for (pos = xe-&gt;mem.vram.dpa_base;</div><div class='add'>+		     pos &lt; xe-&gt;mem.vram.actual_physical_size + xe-&gt;mem.vram.dpa_base;</div><div class='add'>+		     pos += SZ_1G, ofs += 8)</div><div class='add'>+			xe_map_wr(xe, &amp;bo-&gt;vmap, ofs, u64, pos | flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Example layout created above, with root level = 3:</div><div class='add'>+	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's</div><div class='add'>+	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's</div><div class='add'>+	 * [PT9...PT28]: Userspace PT's for VM_BIND, 4 KiB PTE's</div><div class='add'>+	 * [PT29 = PDE 0] [PT30 = PDE 1] [PT31 = PDE 2]</div><div class='add'>+	 *</div><div class='add'>+	 * This makes the lowest part of the VM point to the pagetables.</div><div class='add'>+	 * Hence the lowest 2M in the vm should point to itself, with a few writes</div><div class='add'>+	 * and flushes, other parts of the VM can be used either for copying and</div><div class='add'>+	 * clearing.</div><div class='add'>+	 *</div><div class='add'>+	 * For performance, the kernel reserves PDE's, so about 20 are left</div><div class='add'>+	 * for async VM updates.</div><div class='add'>+	 *</div><div class='add'>+	 * To make it easier to work, each scratch PT is put in slot (1 + PT #)</div><div class='add'>+	 * everywhere, this allows lockless updates to scratch pages by using</div><div class='add'>+	 * the different addresses in VM.</div><div class='add'>+	 */</div><div class='add'>+#define NUM_VMUSA_UNIT_PER_PAGE	32</div><div class='add'>+#define VM_SA_UPDATE_UNIT_SIZE		(XE_PAGE_SIZE / NUM_VMUSA_UNIT_PER_PAGE)</div><div class='add'>+#define NUM_VMUSA_WRITES_PER_UNIT	(VM_SA_UPDATE_UNIT_SIZE / sizeof(u64))</div><div class='add'>+	drm_suballoc_manager_init(&amp;m-&gt;vm_update_sa,</div><div class='add'>+				  (map_ofs / XE_PAGE_SIZE - NUM_KERNEL_PDE) *</div><div class='add'>+				  NUM_VMUSA_UNIT_PER_PAGE, 0);</div><div class='add'>+</div><div class='add'>+	m-&gt;pt_bo = bo;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Due to workaround 16017236439, odd instance hardware copy engines are</div><div class='add'>+ * faster than even instance ones.</div><div class='add'>+ * This function returns the mask involving all fast copy engines and the</div><div class='add'>+ * reserved copy engine to be used as logical mask for migrate engine.</div><div class='add'>+ * Including the reserved copy engine is required to avoid deadlocks due to</div><div class='add'>+ * migrate jobs servicing the faults gets stuck behind the job that faulted.</div><div class='add'>+ */</div><div class='add'>+static u32 xe_migrate_usm_logical_mask(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 logical_mask = 0;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+	for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+		if (hwe-&gt;class != XE_ENGINE_CLASS_COPY)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!XE_WA(gt, 16017236439) ||</div><div class='add'>+		    xe_gt_is_usm_hwe(gt, hwe) || hwe-&gt;instance &amp; 1)</div><div class='add'>+			logical_mask |= BIT(hwe-&gt;logical_instance);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return logical_mask;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_migrate_init() - Initialize a migrate context</div><div class='add'>+ * @tile: Back-pointer to the tile we're initializing for.</div><div class='add'>+ *</div><div class='add'>+ * Return: Pointer to a migrate context on success. Error pointer on error.</div><div class='add'>+ */</div><div class='add'>+struct xe_migrate *xe_migrate_init(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_gt *primary_gt = tile-&gt;primary_gt;</div><div class='add'>+	struct xe_migrate *m;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	m = drmm_kzalloc(&amp;xe-&gt;drm, sizeof(*m), GFP_KERNEL);</div><div class='add'>+	if (!m)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	m-&gt;tile = tile;</div><div class='add'>+</div><div class='add'>+	/* Special layout, prepared below.. */</div><div class='add'>+	vm = xe_vm_create(xe, XE_VM_FLAG_MIGRATION |</div><div class='add'>+			  XE_VM_FLAG_SET_TILE_ID(tile));</div><div class='add'>+	if (IS_ERR(vm))</div><div class='add'>+		return ERR_CAST(vm);</div><div class='add'>+</div><div class='add'>+	xe_vm_lock(vm, false);</div><div class='add'>+	err = xe_migrate_prepare_vm(tile, m, vm);</div><div class='add'>+	xe_vm_unlock(vm);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_vm_close_and_put(vm);</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.has_usm) {</div><div class='add'>+		struct xe_hw_engine *hwe = xe_gt_hw_engine(primary_gt,</div><div class='add'>+							   XE_ENGINE_CLASS_COPY,</div><div class='add'>+							   primary_gt-&gt;usm.reserved_bcs_instance,</div><div class='add'>+							   false);</div><div class='add'>+		u32 logical_mask = xe_migrate_usm_logical_mask(primary_gt);</div><div class='add'>+</div><div class='add'>+		if (!hwe || !logical_mask)</div><div class='add'>+			return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+		m-&gt;q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe,</div><div class='add'>+					    EXEC_QUEUE_FLAG_KERNEL |</div><div class='add'>+					    EXEC_QUEUE_FLAG_PERMANENT |</div><div class='add'>+					    EXEC_QUEUE_FLAG_HIGH_PRIORITY);</div><div class='add'>+	} else {</div><div class='add'>+		m-&gt;q = xe_exec_queue_create_class(xe, primary_gt, vm,</div><div class='add'>+						  XE_ENGINE_CLASS_COPY,</div><div class='add'>+						  EXEC_QUEUE_FLAG_KERNEL |</div><div class='add'>+						  EXEC_QUEUE_FLAG_PERMANENT);</div><div class='add'>+	}</div><div class='add'>+	if (IS_ERR(m-&gt;q)) {</div><div class='add'>+		xe_vm_close_and_put(vm);</div><div class='add'>+		return ERR_CAST(m-&gt;q);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;m-&gt;job_mutex);</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_migrate_fini, m);</div><div class='add'>+	if (err)</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe)) {</div><div class='add'>+		if (xe_device_has_flat_ccs(xe))</div><div class='add'>+			/* min chunk size corresponds to 4K of CCS Metadata */</div><div class='add'>+			m-&gt;min_chunk_size = SZ_4K * SZ_64K /</div><div class='add'>+				xe_device_ccs_bytes(xe, SZ_64K);</div><div class='add'>+		else</div><div class='add'>+			/* Somewhat arbitrary to avoid a huge amount of blits */</div><div class='add'>+			m-&gt;min_chunk_size = SZ_64K;</div><div class='add'>+		m-&gt;min_chunk_size = roundup_pow_of_two(m-&gt;min_chunk_size);</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Migrate min chunk size is 0x%08llx\n",</div><div class='add'>+			(unsigned long long)m-&gt;min_chunk_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return m;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 max_mem_transfer_per_pass(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (!IS_DGFX(xe) &amp;&amp; xe_device_has_flat_ccs(xe))</div><div class='add'>+		return MAX_CCS_LIMITED_TRANSFER;</div><div class='add'>+</div><div class='add'>+	return MAX_PREEMPTDISABLE_TRANSFER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_migrate_res_sizes(struct xe_migrate *m, struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(m-&gt;tile);</div><div class='add'>+	u64 size = min_t(u64, max_mem_transfer_per_pass(xe), cur-&gt;remaining);</div><div class='add'>+</div><div class='add'>+	if (mem_type_is_vram(cur-&gt;mem_type)) {</div><div class='add'>+		/*</div><div class='add'>+		 * VRAM we want to blit in chunks with sizes aligned to</div><div class='add'>+		 * min_chunk_size in order for the offset to CCS metadata to be</div><div class='add'>+		 * page-aligned. If it's the last chunk it may be smaller.</div><div class='add'>+		 *</div><div class='add'>+		 * Another constraint is that we need to limit the blit to</div><div class='add'>+		 * the VRAM block size, unless size is smaller than</div><div class='add'>+		 * min_chunk_size.</div><div class='add'>+		 */</div><div class='add'>+		u64 chunk = max_t(u64, cur-&gt;size, m-&gt;min_chunk_size);</div><div class='add'>+</div><div class='add'>+		size = min_t(u64, size, chunk);</div><div class='add'>+		if (size &gt; m-&gt;min_chunk_size)</div><div class='add'>+			size = round_down(size, m-&gt;min_chunk_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_migrate_allow_identity(u64 size, const struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	/* If the chunk is not fragmented, allow identity map. */</div><div class='add'>+	return cur-&gt;size &gt;= size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 pte_update_size(struct xe_migrate *m,</div><div class='add'>+			   bool is_vram,</div><div class='add'>+			   struct ttm_resource *res,</div><div class='add'>+			   struct xe_res_cursor *cur,</div><div class='add'>+			   u64 *L0, u64 *L0_ofs, u32 *L0_pt,</div><div class='add'>+			   u32 cmd_size, u32 pt_ofs, u32 avail_pts)</div><div class='add'>+{</div><div class='add'>+	u32 cmds = 0;</div><div class='add'>+</div><div class='add'>+	*L0_pt = pt_ofs;</div><div class='add'>+	if (is_vram &amp;&amp; xe_migrate_allow_identity(*L0, cur)) {</div><div class='add'>+		/* Offset into identity map. */</div><div class='add'>+		*L0_ofs = xe_migrate_vram_ofs(tile_to_xe(m-&gt;tile),</div><div class='add'>+					      cur-&gt;start + vram_region_gpu_offset(res));</div><div class='add'>+		cmds += cmd_size;</div><div class='add'>+	} else {</div><div class='add'>+		/* Clip L0 to available size */</div><div class='add'>+		u64 size = min(*L0, (u64)avail_pts * SZ_2M);</div><div class='add'>+		u64 num_4k_pages = DIV_ROUND_UP(size, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+		*L0 = size;</div><div class='add'>+		*L0_ofs = xe_migrate_vm_addr(pt_ofs, 0);</div><div class='add'>+</div><div class='add'>+		/* MI_STORE_DATA_IMM */</div><div class='add'>+		cmds += 3 * DIV_ROUND_UP(num_4k_pages, 0x1ff);</div><div class='add'>+</div><div class='add'>+		/* PDE qwords */</div><div class='add'>+		cmds += num_4k_pages * 2;</div><div class='add'>+</div><div class='add'>+		/* Each chunk has a single blit command */</div><div class='add'>+		cmds += cmd_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cmds;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_pte(struct xe_migrate *m,</div><div class='add'>+		     struct xe_bb *bb, u32 at_pt,</div><div class='add'>+		     bool is_vram, bool is_comp_pte,</div><div class='add'>+		     struct xe_res_cursor *cur,</div><div class='add'>+		     u32 size, struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(m-&gt;tile);</div><div class='add'>+	struct xe_vm *vm = m-&gt;q-&gt;vm;</div><div class='add'>+	u16 pat_index;</div><div class='add'>+	u32 ptes;</div><div class='add'>+	u64 ofs = at_pt * XE_PAGE_SIZE;</div><div class='add'>+	u64 cur_ofs;</div><div class='add'>+</div><div class='add'>+	/* Indirect access needs compression enabled uncached PAT index */</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 2000)</div><div class='add'>+		pat_index = is_comp_pte ? xe-&gt;pat.idx[XE_CACHE_NONE_COMPRESSION] :</div><div class='add'>+					  xe-&gt;pat.idx[XE_CACHE_NONE];</div><div class='add'>+	else</div><div class='add'>+		pat_index = xe-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+</div><div class='add'>+	ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	while (ptes) {</div><div class='add'>+		u32 chunk = min(0x1ffU, ptes);</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = ofs;</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = 0;</div><div class='add'>+</div><div class='add'>+		cur_ofs = ofs;</div><div class='add'>+		ofs += chunk * 8;</div><div class='add'>+		ptes -= chunk;</div><div class='add'>+</div><div class='add'>+		while (chunk--) {</div><div class='add'>+			u64 addr, flags = 0;</div><div class='add'>+			bool devmem = false;</div><div class='add'>+</div><div class='add'>+			addr = xe_res_dma(cur) &amp; PAGE_MASK;</div><div class='add'>+			if (is_vram) {</div><div class='add'>+				if (vm-&gt;flags &amp; XE_VM_FLAG_64K) {</div><div class='add'>+					u64 va = cur_ofs * XE_PAGE_SIZE / 8;</div><div class='add'>+</div><div class='add'>+					xe_assert(xe, (va &amp; (SZ_64K - 1)) ==</div><div class='add'>+						  (addr &amp; (SZ_64K - 1)));</div><div class='add'>+</div><div class='add'>+					flags |= XE_PTE_PS64;</div><div class='add'>+				}</div><div class='add'>+</div><div class='add'>+				addr += vram_region_gpu_offset(res);</div><div class='add'>+				devmem = true;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			addr = vm-&gt;pt_ops-&gt;pte_encode_addr(m-&gt;tile-&gt;xe,</div><div class='add'>+							   addr, pat_index,</div><div class='add'>+							   0, devmem, flags);</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = lower_32_bits(addr);</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = upper_32_bits(addr);</div><div class='add'>+</div><div class='add'>+			xe_res_next(cur, min_t(u32, size, PAGE_SIZE));</div><div class='add'>+			cur_ofs += 8;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define EMIT_COPY_CCS_DW 5</div><div class='add'>+static void emit_copy_ccs(struct xe_gt *gt, struct xe_bb *bb,</div><div class='add'>+			  u64 dst_ofs, bool dst_is_indirect,</div><div class='add'>+			  u64 src_ofs, bool src_is_indirect,</div><div class='add'>+			  u32 size)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 *cs = bb-&gt;cs + bb-&gt;len;</div><div class='add'>+	u32 num_ccs_blks;</div><div class='add'>+	u32 num_pages;</div><div class='add'>+	u32 ccs_copy_size;</div><div class='add'>+	u32 mocs;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 2000) {</div><div class='add'>+		num_pages = DIV_ROUND_UP(size, XE_PAGE_SIZE);</div><div class='add'>+		xe_gt_assert(gt, FIELD_FIT(XE2_CCS_SIZE_MASK, num_pages - 1));</div><div class='add'>+</div><div class='add'>+		ccs_copy_size = REG_FIELD_PREP(XE2_CCS_SIZE_MASK, num_pages - 1);</div><div class='add'>+		mocs = FIELD_PREP(XE2_XY_CTRL_SURF_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),</div><div class='add'>+					    NUM_CCS_BYTES_PER_BLOCK);</div><div class='add'>+		xe_gt_assert(gt, FIELD_FIT(CCS_SIZE_MASK, num_ccs_blks - 1));</div><div class='add'>+</div><div class='add'>+		ccs_copy_size = REG_FIELD_PREP(CCS_SIZE_MASK, num_ccs_blks - 1);</div><div class='add'>+		mocs = FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*cs++ = XY_CTRL_SURF_COPY_BLT |</div><div class='add'>+		(src_is_indirect ? 0x0 : 0x1) &lt;&lt; SRC_ACCESS_TYPE_SHIFT |</div><div class='add'>+		(dst_is_indirect ? 0x0 : 0x1) &lt;&lt; DST_ACCESS_TYPE_SHIFT |</div><div class='add'>+		ccs_copy_size;</div><div class='add'>+	*cs++ = lower_32_bits(src_ofs);</div><div class='add'>+	*cs++ = upper_32_bits(src_ofs) | mocs;</div><div class='add'>+	*cs++ = lower_32_bits(dst_ofs);</div><div class='add'>+	*cs++ = upper_32_bits(dst_ofs) | mocs;</div><div class='add'>+</div><div class='add'>+	bb-&gt;len = cs - bb-&gt;cs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define EMIT_COPY_DW 10</div><div class='add'>+static void emit_copy(struct xe_gt *gt, struct xe_bb *bb,</div><div class='add'>+		      u64 src_ofs, u64 dst_ofs, unsigned int size,</div><div class='add'>+		      unsigned int pitch)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 mocs = 0;</div><div class='add'>+	u32 tile_y = 0;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, size / pitch &lt;= S16_MAX);</div><div class='add'>+	xe_gt_assert(gt, pitch / 4 &lt;= S16_MAX);</div><div class='add'>+	xe_gt_assert(gt, pitch &lt;= U16_MAX);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+		mocs = FIELD_PREP(XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 1250)</div><div class='add'>+		tile_y = XY_FAST_COPY_BLT_D1_SRC_TILE4 | XY_FAST_COPY_BLT_D1_DST_TILE4;</div><div class='add'>+</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = XY_FAST_COPY_BLT_CMD | (10 - 2);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = XY_FAST_COPY_BLT_DEPTH_32 | pitch | tile_y | mocs;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = 0;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = (size / pitch) &lt;&lt; 16 | pitch / 4;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = lower_32_bits(dst_ofs);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = upper_32_bits(dst_ofs);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = 0;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = pitch | mocs;</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = lower_32_bits(src_ofs);</div><div class='add'>+	bb-&gt;cs[bb-&gt;len++] = upper_32_bits(src_ofs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int job_add_deps(struct xe_sched_job *job, struct dma_resv *resv,</div><div class='add'>+			enum dma_resv_usage usage)</div><div class='add'>+{</div><div class='add'>+	return drm_sched_job_add_resv_dependencies(&amp;job-&gt;drm, resv, usage);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_migrate_batch_base(struct xe_migrate *m, bool usm)</div><div class='add'>+{</div><div class='add'>+	return usm ? m-&gt;usm_batch_base_ofs : m-&gt;batch_base_ofs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 xe_migrate_ccs_copy(struct xe_migrate *m,</div><div class='add'>+			       struct xe_bb *bb,</div><div class='add'>+			       u64 src_ofs, bool src_is_indirect,</div><div class='add'>+			       u64 dst_ofs, bool dst_is_indirect, u32 dst_size,</div><div class='add'>+			       u64 ccs_ofs, bool copy_ccs)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = m-&gt;tile-&gt;primary_gt;</div><div class='add'>+	u32 flush_flags = 0;</div><div class='add'>+</div><div class='add'>+	if (xe_device_has_flat_ccs(gt_to_xe(gt)) &amp;&amp; !copy_ccs &amp;&amp; dst_is_indirect) {</div><div class='add'>+		/*</div><div class='add'>+		 * If the src is already in vram, then it should already</div><div class='add'>+		 * have been cleared by us, or has been populated by the</div><div class='add'>+		 * user. Make sure we copy the CCS aux state as-is.</div><div class='add'>+		 *</div><div class='add'>+		 * Otherwise if the bo doesn't have any CCS metadata attached,</div><div class='add'>+		 * we still need to clear it for security reasons.</div><div class='add'>+		 */</div><div class='add'>+		u64 ccs_src_ofs =  src_is_indirect ? src_ofs : m-&gt;cleared_mem_ofs;</div><div class='add'>+</div><div class='add'>+		emit_copy_ccs(gt, bb,</div><div class='add'>+			      dst_ofs, true,</div><div class='add'>+			      ccs_src_ofs, src_is_indirect, dst_size);</div><div class='add'>+</div><div class='add'>+		flush_flags = MI_FLUSH_DW_CCS;</div><div class='add'>+	} else if (copy_ccs) {</div><div class='add'>+		if (!src_is_indirect)</div><div class='add'>+			src_ofs = ccs_ofs;</div><div class='add'>+		else if (!dst_is_indirect)</div><div class='add'>+			dst_ofs = ccs_ofs;</div><div class='add'>+</div><div class='add'>+		xe_gt_assert(gt, src_is_indirect || dst_is_indirect);</div><div class='add'>+</div><div class='add'>+		emit_copy_ccs(gt, bb, dst_ofs, dst_is_indirect, src_ofs,</div><div class='add'>+			      src_is_indirect, dst_size);</div><div class='add'>+		if (dst_is_indirect)</div><div class='add'>+			flush_flags = MI_FLUSH_DW_CCS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return flush_flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_migrate_copy() - Copy content of TTM resources.</div><div class='add'>+ * @m: The migration context.</div><div class='add'>+ * @src_bo: The buffer object @src is currently bound to.</div><div class='add'>+ * @dst_bo: If copying between resources created for the same bo, set this to</div><div class='add'>+ * the same value as @src_bo. If copying between buffer objects, set it to</div><div class='add'>+ * the buffer object @dst is currently bound to.</div><div class='add'>+ * @src: The source TTM resource.</div><div class='add'>+ * @dst: The dst TTM resource.</div><div class='add'>+ * @copy_only_ccs: If true copy only CCS metadata</div><div class='add'>+ *</div><div class='add'>+ * Copies the contents of @src to @dst: On flat CCS devices,</div><div class='add'>+ * the CCS metadata is copied as well if needed, or if not present,</div><div class='add'>+ * the CCS metadata of @dst is cleared for security reasons.</div><div class='add'>+ *</div><div class='add'>+ * Return: Pointer to a dma_fence representing the last copy batch, or</div><div class='add'>+ * an error pointer on failure. If there is a failure, any copy operation</div><div class='add'>+ * started by the function call has been synced.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *xe_migrate_copy(struct xe_migrate *m,</div><div class='add'>+				  struct xe_bo *src_bo,</div><div class='add'>+				  struct xe_bo *dst_bo,</div><div class='add'>+				  struct ttm_resource *src,</div><div class='add'>+				  struct ttm_resource *dst,</div><div class='add'>+				  bool copy_only_ccs)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = m-&gt;tile-&gt;primary_gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='add'>+	u64 size = src_bo-&gt;size;</div><div class='add'>+	struct xe_res_cursor src_it, dst_it, ccs_it;</div><div class='add'>+	u64 src_L0_ofs, dst_L0_ofs;</div><div class='add'>+	u32 src_L0_pt, dst_L0_pt;</div><div class='add'>+	u64 src_L0, dst_L0;</div><div class='add'>+	int pass = 0;</div><div class='add'>+	int err;</div><div class='add'>+	bool src_is_pltt = src-&gt;mem_type == XE_PL_TT;</div><div class='add'>+	bool dst_is_pltt = dst-&gt;mem_type == XE_PL_TT;</div><div class='add'>+	bool src_is_vram = mem_type_is_vram(src-&gt;mem_type);</div><div class='add'>+	bool dst_is_vram = mem_type_is_vram(dst-&gt;mem_type);</div><div class='add'>+	bool copy_ccs = xe_device_has_flat_ccs(xe) &amp;&amp;</div><div class='add'>+		xe_bo_needs_ccs_pages(src_bo) &amp;&amp; xe_bo_needs_ccs_pages(dst_bo);</div><div class='add'>+	bool copy_system_ccs = copy_ccs &amp;&amp; (!src_is_vram || !dst_is_vram);</div><div class='add'>+</div><div class='add'>+	/* Copying CCS between two different BOs is not supported yet. */</div><div class='add'>+	if (XE_WARN_ON(copy_ccs &amp;&amp; src_bo != dst_bo))</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+	if (src_bo != dst_bo &amp;&amp; XE_WARN_ON(src_bo-&gt;size != dst_bo-&gt;size))</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+	if (!src_is_vram)</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(src_bo), 0, size, &amp;src_it);</div><div class='add'>+	else</div><div class='add'>+		xe_res_first(src, 0, size, &amp;src_it);</div><div class='add'>+	if (!dst_is_vram)</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(dst_bo), 0, size, &amp;dst_it);</div><div class='add'>+	else</div><div class='add'>+		xe_res_first(dst, 0, size, &amp;dst_it);</div><div class='add'>+</div><div class='add'>+	if (copy_system_ccs)</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(src_bo), xe_bo_ccs_pages_start(src_bo),</div><div class='add'>+				PAGE_ALIGN(xe_device_ccs_bytes(xe, size)),</div><div class='add'>+				&amp;ccs_it);</div><div class='add'>+</div><div class='add'>+	while (size) {</div><div class='add'>+		u32 batch_size = 2; /* arb_clear() + MI_BATCH_BUFFER_END */</div><div class='add'>+		struct xe_sched_job *job;</div><div class='add'>+		struct xe_bb *bb;</div><div class='add'>+		u32 flush_flags;</div><div class='add'>+		u32 update_idx;</div><div class='add'>+		u64 ccs_ofs, ccs_size;</div><div class='add'>+		u32 ccs_pt;</div><div class='add'>+</div><div class='add'>+		bool usm = xe-&gt;info.has_usm;</div><div class='add'>+		u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;</div><div class='add'>+</div><div class='add'>+		src_L0 = xe_migrate_res_sizes(m, &amp;src_it);</div><div class='add'>+		dst_L0 = xe_migrate_res_sizes(m, &amp;dst_it);</div><div class='add'>+</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Pass %u, sizes: %llu &amp; %llu\n",</div><div class='add'>+			pass++, src_L0, dst_L0);</div><div class='add'>+</div><div class='add'>+		src_L0 = min(src_L0, dst_L0);</div><div class='add'>+</div><div class='add'>+		batch_size += pte_update_size(m, src_is_vram, src, &amp;src_it, &amp;src_L0,</div><div class='add'>+					      &amp;src_L0_ofs, &amp;src_L0_pt, 0, 0,</div><div class='add'>+					      avail_pts);</div><div class='add'>+</div><div class='add'>+		batch_size += pte_update_size(m, dst_is_vram, dst, &amp;dst_it, &amp;src_L0,</div><div class='add'>+					      &amp;dst_L0_ofs, &amp;dst_L0_pt, 0,</div><div class='add'>+					      avail_pts, avail_pts);</div><div class='add'>+</div><div class='add'>+		if (copy_system_ccs) {</div><div class='add'>+			ccs_size = xe_device_ccs_bytes(xe, src_L0);</div><div class='add'>+			batch_size += pte_update_size(m, false, NULL, &amp;ccs_it, &amp;ccs_size,</div><div class='add'>+						      &amp;ccs_ofs, &amp;ccs_pt, 0,</div><div class='add'>+						      2 * avail_pts,</div><div class='add'>+						      avail_pts);</div><div class='add'>+			xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Add copy commands size here */</div><div class='add'>+		batch_size += ((copy_only_ccs) ? 0 : EMIT_COPY_DW) +</div><div class='add'>+			((xe_device_has_flat_ccs(xe) ? EMIT_COPY_CCS_DW : 0));</div><div class='add'>+</div><div class='add'>+		bb = xe_bb_new(gt, batch_size, usm);</div><div class='add'>+		if (IS_ERR(bb)) {</div><div class='add'>+			err = PTR_ERR(bb);</div><div class='add'>+			goto err_sync;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (src_is_vram &amp;&amp; xe_migrate_allow_identity(src_L0, &amp;src_it))</div><div class='add'>+			xe_res_next(&amp;src_it, src_L0);</div><div class='add'>+		else</div><div class='add'>+			emit_pte(m, bb, src_L0_pt, src_is_vram, true, &amp;src_it, src_L0,</div><div class='add'>+				 src);</div><div class='add'>+</div><div class='add'>+		if (dst_is_vram &amp;&amp; xe_migrate_allow_identity(src_L0, &amp;dst_it))</div><div class='add'>+			xe_res_next(&amp;dst_it, src_L0);</div><div class='add'>+		else</div><div class='add'>+			emit_pte(m, bb, dst_L0_pt, dst_is_vram, true, &amp;dst_it, src_L0,</div><div class='add'>+				 dst);</div><div class='add'>+</div><div class='add'>+		if (copy_system_ccs)</div><div class='add'>+			emit_pte(m, bb, ccs_pt, false, false, &amp;ccs_it, ccs_size, src);</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+		update_idx = bb-&gt;len;</div><div class='add'>+</div><div class='add'>+		if (!copy_only_ccs)</div><div class='add'>+			emit_copy(gt, bb, src_L0_ofs, dst_L0_ofs, src_L0, XE_PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+		flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs,</div><div class='add'>+						  IS_DGFX(xe) ? src_is_vram : src_is_pltt,</div><div class='add'>+						  dst_L0_ofs,</div><div class='add'>+						  IS_DGFX(xe) ? dst_is_vram : dst_is_pltt,</div><div class='add'>+						  src_L0, ccs_ofs, copy_ccs);</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;m-&gt;job_mutex);</div><div class='add'>+		job = xe_bb_create_migration_job(m-&gt;q, bb,</div><div class='add'>+						 xe_migrate_batch_base(m, usm),</div><div class='add'>+						 update_idx);</div><div class='add'>+		if (IS_ERR(job)) {</div><div class='add'>+			err = PTR_ERR(job);</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_sched_job_add_migrate_flush(job, flush_flags);</div><div class='add'>+		if (!fence) {</div><div class='add'>+			err = job_add_deps(job, src_bo-&gt;ttm.base.resv,</div><div class='add'>+					   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+			if (!err &amp;&amp; src_bo != dst_bo)</div><div class='add'>+				err = job_add_deps(job, dst_bo-&gt;ttm.base.resv,</div><div class='add'>+						   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_job;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_sched_job_arm(job);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+		fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+		xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+		dma_fence_put(m-&gt;fence);</div><div class='add'>+		m-&gt;fence = dma_fence_get(fence);</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+</div><div class='add'>+		xe_bb_free(bb, fence);</div><div class='add'>+		size -= src_L0;</div><div class='add'>+		continue;</div><div class='add'>+</div><div class='add'>+err_job:</div><div class='add'>+		xe_sched_job_put(job);</div><div class='add'>+err:</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+</div><div class='add'>+err_sync:</div><div class='add'>+		/* Sync partial copy if any. FIXME: under job_mutex? */</div><div class='add'>+		if (fence) {</div><div class='add'>+			dma_fence_wait(fence, false);</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,</div><div class='add'>+				 u32 size, u32 pitch)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 *cs = bb-&gt;cs + bb-&gt;len;</div><div class='add'>+	u32 len = PVC_MEM_SET_CMD_LEN_DW;</div><div class='add'>+</div><div class='add'>+	*cs++ = PVC_MEM_SET_CMD | PVC_MEM_SET_MATRIX | (len - 2);</div><div class='add'>+	*cs++ = pitch - 1;</div><div class='add'>+	*cs++ = (size / pitch) - 1;</div><div class='add'>+	*cs++ = pitch - 1;</div><div class='add'>+	*cs++ = lower_32_bits(src_ofs);</div><div class='add'>+	*cs++ = upper_32_bits(src_ofs);</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 2000)</div><div class='add'>+		*cs++ = FIELD_PREP(XE2_MEM_SET_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+	else</div><div class='add'>+		*cs++ = FIELD_PREP(PVC_MEM_SET_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, cs - bb-&gt;cs == len + bb-&gt;len);</div><div class='add'>+</div><div class='add'>+	bb-&gt;len += len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_clear_main_copy(struct xe_gt *gt, struct xe_bb *bb,</div><div class='add'>+				 u64 src_ofs, u32 size, u32 pitch, bool is_vram)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	u32 *cs = bb-&gt;cs + bb-&gt;len;</div><div class='add'>+	u32 len = XY_FAST_COLOR_BLT_DW;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &lt; 1250)</div><div class='add'>+		len = 11;</div><div class='add'>+</div><div class='add'>+	*cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |</div><div class='add'>+		(len - 2);</div><div class='add'>+	if (GRAPHICS_VERx100(xe) &gt;= 2000)</div><div class='add'>+		*cs++ = FIELD_PREP(XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK, gt-&gt;mocs.uc_index) |</div><div class='add'>+			(pitch - 1);</div><div class='add'>+	else</div><div class='add'>+		*cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, gt-&gt;mocs.uc_index) |</div><div class='add'>+			(pitch - 1);</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = (size / pitch) &lt;&lt; 16 | pitch / 4;</div><div class='add'>+	*cs++ = lower_32_bits(src_ofs);</div><div class='add'>+	*cs++ = upper_32_bits(src_ofs);</div><div class='add'>+	*cs++ = (is_vram ? 0x0 : 0x1) &lt;&lt;  XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+	*cs++ = 0;</div><div class='add'>+</div><div class='add'>+	if (len &gt; 11) {</div><div class='add'>+		*cs++ = 0;</div><div class='add'>+		*cs++ = 0;</div><div class='add'>+		*cs++ = 0;</div><div class='add'>+		*cs++ = 0;</div><div class='add'>+		*cs++ = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, cs - bb-&gt;cs == len + bb-&gt;len);</div><div class='add'>+</div><div class='add'>+	bb-&gt;len += len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool has_service_copy_support(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * What we care about is whether the architecture was designed with</div><div class='add'>+	 * service copy functionality (specifically the new MEM_SET / MEM_COPY</div><div class='add'>+	 * instructions) so check the architectural engine list rather than the</div><div class='add'>+	 * actual list since these instructions are usable on BCS0 even if</div><div class='add'>+	 * all of the actual service copy engines (BCS1-BCS8) have been fused</div><div class='add'>+	 * off.</div><div class='add'>+	 */</div><div class='add'>+	return gt-&gt;info.__engine_mask &amp; GENMASK(XE_HW_ENGINE_BCS8,</div><div class='add'>+						XE_HW_ENGINE_BCS1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 emit_clear_cmd_len(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	if (has_service_copy_support(gt))</div><div class='add'>+		return PVC_MEM_SET_CMD_LEN_DW;</div><div class='add'>+	else</div><div class='add'>+		return XY_FAST_COLOR_BLT_DW;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_clear(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,</div><div class='add'>+		       u32 size, u32 pitch, bool is_vram)</div><div class='add'>+{</div><div class='add'>+	if (has_service_copy_support(gt))</div><div class='add'>+		emit_clear_link_copy(gt, bb, src_ofs, size, pitch);</div><div class='add'>+	else</div><div class='add'>+		emit_clear_main_copy(gt, bb, src_ofs, size, pitch,</div><div class='add'>+				     is_vram);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_migrate_clear() - Copy content of TTM resources.</div><div class='add'>+ * @m: The migration context.</div><div class='add'>+ * @bo: The buffer object @dst is currently bound to.</div><div class='add'>+ * @dst: The dst TTM resource to be cleared.</div><div class='add'>+ *</div><div class='add'>+ * Clear the contents of @dst to zero. On flat CCS devices,</div><div class='add'>+ * the CCS metadata is cleared to zero as well on VRAM destinations.</div><div class='add'>+ * TODO: Eliminate the @bo argument.</div><div class='add'>+ *</div><div class='add'>+ * Return: Pointer to a dma_fence representing the last clear batch, or</div><div class='add'>+ * an error pointer on failure. If there is a failure, any clear operation</div><div class='add'>+ * started by the function call has been synced.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *xe_migrate_clear(struct xe_migrate *m,</div><div class='add'>+				   struct xe_bo *bo,</div><div class='add'>+				   struct ttm_resource *dst)</div><div class='add'>+{</div><div class='add'>+	bool clear_vram = mem_type_is_vram(dst-&gt;mem_type);</div><div class='add'>+	struct xe_gt *gt = m-&gt;tile-&gt;primary_gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	bool clear_system_ccs = (xe_bo_needs_ccs_pages(bo) &amp;&amp; !IS_DGFX(xe)) ? true : false;</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='add'>+	u64 size = bo-&gt;size;</div><div class='add'>+	struct xe_res_cursor src_it;</div><div class='add'>+	struct ttm_resource *src = dst;</div><div class='add'>+	int err;</div><div class='add'>+	int pass = 0;</div><div class='add'>+</div><div class='add'>+	if (!clear_vram)</div><div class='add'>+		xe_res_first_sg(xe_bo_sg(bo), 0, bo-&gt;size, &amp;src_it);</div><div class='add'>+	else</div><div class='add'>+		xe_res_first(src, 0, bo-&gt;size, &amp;src_it);</div><div class='add'>+</div><div class='add'>+	while (size) {</div><div class='add'>+		u64 clear_L0_ofs;</div><div class='add'>+		u32 clear_L0_pt;</div><div class='add'>+		u32 flush_flags = 0;</div><div class='add'>+		u64 clear_L0;</div><div class='add'>+		struct xe_sched_job *job;</div><div class='add'>+		struct xe_bb *bb;</div><div class='add'>+		u32 batch_size, update_idx;</div><div class='add'>+</div><div class='add'>+		bool usm = xe-&gt;info.has_usm;</div><div class='add'>+		u32 avail_pts = max_mem_transfer_per_pass(xe) / LEVEL0_PAGE_TABLE_ENCODE_SIZE;</div><div class='add'>+</div><div class='add'>+		clear_L0 = xe_migrate_res_sizes(m, &amp;src_it);</div><div class='add'>+</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Pass %u, size: %llu\n", pass++, clear_L0);</div><div class='add'>+</div><div class='add'>+		/* Calculate final sizes and batch size.. */</div><div class='add'>+		batch_size = 2 +</div><div class='add'>+			pte_update_size(m, clear_vram, src, &amp;src_it,</div><div class='add'>+					&amp;clear_L0, &amp;clear_L0_ofs, &amp;clear_L0_pt,</div><div class='add'>+					clear_system_ccs ? 0 : emit_clear_cmd_len(gt), 0,</div><div class='add'>+					avail_pts);</div><div class='add'>+</div><div class='add'>+		if (xe_device_has_flat_ccs(xe))</div><div class='add'>+			batch_size += EMIT_COPY_CCS_DW;</div><div class='add'>+</div><div class='add'>+		/* Clear commands */</div><div class='add'>+</div><div class='add'>+		if (WARN_ON_ONCE(!clear_L0))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		bb = xe_bb_new(gt, batch_size, usm);</div><div class='add'>+		if (IS_ERR(bb)) {</div><div class='add'>+			err = PTR_ERR(bb);</div><div class='add'>+			goto err_sync;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		size -= clear_L0;</div><div class='add'>+		/* Preemption is enabled again by the ring ops. */</div><div class='add'>+		if (clear_vram &amp;&amp; xe_migrate_allow_identity(clear_L0, &amp;src_it))</div><div class='add'>+			xe_res_next(&amp;src_it, clear_L0);</div><div class='add'>+		else</div><div class='add'>+			emit_pte(m, bb, clear_L0_pt, clear_vram, true, &amp;src_it, clear_L0,</div><div class='add'>+				 dst);</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+		update_idx = bb-&gt;len;</div><div class='add'>+</div><div class='add'>+		if (!clear_system_ccs)</div><div class='add'>+			emit_clear(gt, bb, clear_L0_ofs, clear_L0, XE_PAGE_SIZE, clear_vram);</div><div class='add'>+</div><div class='add'>+		if (xe_device_has_flat_ccs(xe)) {</div><div class='add'>+			emit_copy_ccs(gt, bb, clear_L0_ofs, true,</div><div class='add'>+				      m-&gt;cleared_mem_ofs, false, clear_L0);</div><div class='add'>+			flush_flags = MI_FLUSH_DW_CCS;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;m-&gt;job_mutex);</div><div class='add'>+		job = xe_bb_create_migration_job(m-&gt;q, bb,</div><div class='add'>+						 xe_migrate_batch_base(m, usm),</div><div class='add'>+						 update_idx);</div><div class='add'>+		if (IS_ERR(job)) {</div><div class='add'>+			err = PTR_ERR(job);</div><div class='add'>+			goto err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_sched_job_add_migrate_flush(job, flush_flags);</div><div class='add'>+		if (!fence) {</div><div class='add'>+			/*</div><div class='add'>+			 * There can't be anything userspace related at this</div><div class='add'>+			 * point, so we just need to respect any potential move</div><div class='add'>+			 * fences, which are always tracked as</div><div class='add'>+			 * DMA_RESV_USAGE_KERNEL.</div><div class='add'>+			 */</div><div class='add'>+			err = job_add_deps(job, bo-&gt;ttm.base.resv,</div><div class='add'>+					   DMA_RESV_USAGE_KERNEL);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_job;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_sched_job_arm(job);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+		fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+		xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+		dma_fence_put(m-&gt;fence);</div><div class='add'>+		m-&gt;fence = dma_fence_get(fence);</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+</div><div class='add'>+		xe_bb_free(bb, fence);</div><div class='add'>+		continue;</div><div class='add'>+</div><div class='add'>+err_job:</div><div class='add'>+		xe_sched_job_put(job);</div><div class='add'>+err:</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+		xe_bb_free(bb, NULL);</div><div class='add'>+err_sync:</div><div class='add'>+		/* Sync partial copies if any. FIXME: job_mutex? */</div><div class='add'>+		if (fence) {</div><div class='add'>+			dma_fence_wait(m-&gt;fence, false);</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (clear_system_ccs)</div><div class='add'>+		bo-&gt;ccs_cleared = true;</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,</div><div class='add'>+			  const struct xe_vm_pgtable_update *update,</div><div class='add'>+			  struct xe_migrate_pt_update *pt_update)</div><div class='add'>+{</div><div class='add'>+	const struct xe_migrate_pt_update_ops *ops = pt_update-&gt;ops;</div><div class='add'>+	u32 chunk;</div><div class='add'>+	u32 ofs = update-&gt;ofs, size = update-&gt;qwords;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we have 512 entries (max), we would populate it ourselves,</div><div class='add'>+	 * and update the PDE above it to the new pointer.</div><div class='add'>+	 * The only time this can only happen if we have to update the top</div><div class='add'>+	 * PDE. This requires a BO that is almost vm-&gt;size big.</div><div class='add'>+	 *</div><div class='add'>+	 * This shouldn't be possible in practice.. might change when 16K</div><div class='add'>+	 * pages are used. Hence the assert.</div><div class='add'>+	 */</div><div class='add'>+	xe_tile_assert(tile, update-&gt;qwords &lt;= 0x1ff);</div><div class='add'>+	if (!ppgtt_ofs)</div><div class='add'>+		ppgtt_ofs = xe_migrate_vram_ofs(tile_to_xe(tile),</div><div class='add'>+						xe_bo_addr(update-&gt;pt_bo, 0,</div><div class='add'>+							   XE_PAGE_SIZE));</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		u64 addr = ppgtt_ofs + ofs * 8;</div><div class='add'>+</div><div class='add'>+		chunk = min(update-&gt;qwords, 0x1ffU);</div><div class='add'>+</div><div class='add'>+		/* Ensure populatefn can do memset64 by aligning bb-&gt;cs */</div><div class='add'>+		if (!(bb-&gt;len &amp; 1))</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = MI_NOOP;</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = lower_32_bits(addr);</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = upper_32_bits(addr);</div><div class='add'>+		ops-&gt;populate(pt_update, tile, NULL, bb-&gt;cs + bb-&gt;len, ofs, chunk,</div><div class='add'>+			      update);</div><div class='add'>+</div><div class='add'>+		bb-&gt;len += chunk * 2;</div><div class='add'>+		ofs += chunk;</div><div class='add'>+		size -= chunk;</div><div class='add'>+	} while (size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m)</div><div class='add'>+{</div><div class='add'>+	return xe_vm_get(m-&gt;q-&gt;vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+struct migrate_test_params {</div><div class='add'>+	struct xe_test_priv base;</div><div class='add'>+	bool force_gpu;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_migrate_test_params(_priv) \</div><div class='add'>+	container_of(_priv, struct migrate_test_params, base)</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+xe_migrate_update_pgtables_cpu(struct xe_migrate *m,</div><div class='add'>+			       struct xe_vm *vm, struct xe_bo *bo,</div><div class='add'>+			       const struct  xe_vm_pgtable_update *updates,</div><div class='add'>+			       u32 num_updates, bool wait_vm,</div><div class='add'>+			       struct xe_migrate_pt_update *pt_update)</div><div class='add'>+{</div><div class='add'>+	XE_TEST_DECLARE(struct migrate_test_params *test =</div><div class='add'>+			to_migrate_test_params</div><div class='add'>+			(xe_cur_kunit_priv(XE_TEST_LIVE_MIGRATE));)</div><div class='add'>+	const struct xe_migrate_pt_update_ops *ops = pt_update-&gt;ops;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	int err;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	if (XE_TEST_ONLY(test &amp;&amp; test-&gt;force_gpu))</div><div class='add'>+		return ERR_PTR(-ETIME);</div><div class='add'>+</div><div class='add'>+	if (bo &amp;&amp; !dma_resv_test_signaled(bo-&gt;ttm.base.resv,</div><div class='add'>+					  DMA_RESV_USAGE_KERNEL))</div><div class='add'>+		return ERR_PTR(-ETIME);</div><div class='add'>+</div><div class='add'>+	if (wait_vm &amp;&amp; !dma_resv_test_signaled(xe_vm_resv(vm),</div><div class='add'>+					       DMA_RESV_USAGE_BOOKKEEP))</div><div class='add'>+		return ERR_PTR(-ETIME);</div><div class='add'>+</div><div class='add'>+	if (ops-&gt;pre_commit) {</div><div class='add'>+		pt_update-&gt;job = NULL;</div><div class='add'>+		err = ops-&gt;pre_commit(pt_update);</div><div class='add'>+		if (err)</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; num_updates; i++) {</div><div class='add'>+		const struct xe_vm_pgtable_update *update = &amp;updates[i];</div><div class='add'>+</div><div class='add'>+		ops-&gt;populate(pt_update, m-&gt;tile, &amp;update-&gt;pt_bo-&gt;vmap, NULL,</div><div class='add'>+			      update-&gt;ofs, update-&gt;qwords, update);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vm) {</div><div class='add'>+		trace_xe_vm_cpu_bind(vm);</div><div class='add'>+		xe_device_wmb(vm-&gt;xe);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fence = dma_fence_get_stub();</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool no_in_syncs(struct xe_vm *vm, struct xe_exec_queue *q,</div><div class='add'>+			struct xe_sync_entry *syncs, u32 num_syncs)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_syncs; i++) {</div><div class='add'>+		fence = syncs[i].fence;</div><div class='add'>+</div><div class='add'>+		if (fence &amp;&amp; !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,</div><div class='add'>+				       &amp;fence-&gt;flags))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+	if (q) {</div><div class='add'>+		fence = xe_exec_queue_last_fence_get(q, vm);</div><div class='add'>+		if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &amp;fence-&gt;flags))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_migrate_update_pgtables() - Pipelined page-table update</div><div class='add'>+ * @m: The migrate context.</div><div class='add'>+ * @vm: The vm we'll be updating.</div><div class='add'>+ * @bo: The bo whose dma-resv we will await before updating, or NULL if userptr.</div><div class='add'>+ * @q: The exec queue to be used for the update or NULL if the default</div><div class='add'>+ * migration engine is to be used.</div><div class='add'>+ * @updates: An array of update descriptors.</div><div class='add'>+ * @num_updates: Number of descriptors in @updates.</div><div class='add'>+ * @syncs: Array of xe_sync_entry to await before updating. Note that waits</div><div class='add'>+ * will block the engine timeline.</div><div class='add'>+ * @num_syncs: Number of entries in @syncs.</div><div class='add'>+ * @pt_update: Pointer to a struct xe_migrate_pt_update, which contains</div><div class='add'>+ * pointers to callback functions and, if subclassed, private arguments to</div><div class='add'>+ * those.</div><div class='add'>+ *</div><div class='add'>+ * Perform a pipelined page-table update. The update descriptors are typically</div><div class='add'>+ * built under the same lock critical section as a call to this function. If</div><div class='add'>+ * using the default engine for the updates, they will be performed in the</div><div class='add'>+ * order they grab the job_mutex. If different engines are used, external</div><div class='add'>+ * synchronization is needed for overlapping updates to maintain page-table</div><div class='add'>+ * consistency. Note that the meaing of "overlapping" is that the updates</div><div class='add'>+ * touch the same page-table, which might be a higher-level page-directory.</div><div class='add'>+ * If no pipelining is needed, then updates may be performed by the cpu.</div><div class='add'>+ *</div><div class='add'>+ * Return: A dma_fence that, when signaled, indicates the update completion.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_migrate_update_pgtables(struct xe_migrate *m,</div><div class='add'>+			   struct xe_vm *vm,</div><div class='add'>+			   struct xe_bo *bo,</div><div class='add'>+			   struct xe_exec_queue *q,</div><div class='add'>+			   const struct xe_vm_pgtable_update *updates,</div><div class='add'>+			   u32 num_updates,</div><div class='add'>+			   struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+			   struct xe_migrate_pt_update *pt_update)</div><div class='add'>+{</div><div class='add'>+	const struct xe_migrate_pt_update_ops *ops = pt_update-&gt;ops;</div><div class='add'>+	struct xe_tile *tile = m-&gt;tile;</div><div class='add'>+	struct xe_gt *gt = tile-&gt;primary_gt;</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct drm_suballoc *sa_bo = NULL;</div><div class='add'>+	struct xe_vma *vma = pt_update-&gt;vma;</div><div class='add'>+	struct xe_bb *bb;</div><div class='add'>+	u32 i, batch_size, ppgtt_ofs, update_idx, page_ofs = 0;</div><div class='add'>+	u64 addr;</div><div class='add'>+	int err = 0;</div><div class='add'>+	bool usm = !q &amp;&amp; xe-&gt;info.has_usm;</div><div class='add'>+	bool first_munmap_rebind = vma &amp;&amp;</div><div class='add'>+		vma-&gt;gpuva.flags &amp; XE_VMA_FIRST_REBIND;</div><div class='add'>+	struct xe_exec_queue *q_override = !q ? m-&gt;q : q;</div><div class='add'>+	u16 pat_index = xe-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+</div><div class='add'>+	/* Use the CPU if no in syncs and engine is idle */</div><div class='add'>+	if (no_in_syncs(vm, q, syncs, num_syncs) &amp;&amp; xe_exec_queue_is_idle(q_override)) {</div><div class='add'>+		fence =  xe_migrate_update_pgtables_cpu(m, vm, bo, updates,</div><div class='add'>+							num_updates,</div><div class='add'>+							first_munmap_rebind,</div><div class='add'>+							pt_update);</div><div class='add'>+		if (!IS_ERR(fence) || fence == ERR_PTR(-EAGAIN))</div><div class='add'>+			return fence;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* fixed + PTE entries */</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		batch_size = 2;</div><div class='add'>+	else</div><div class='add'>+		batch_size = 6 + num_updates * 2;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_updates; i++) {</div><div class='add'>+		u32 num_cmds = DIV_ROUND_UP(updates[i].qwords, 0x1ff);</div><div class='add'>+</div><div class='add'>+		/* align noop + MI_STORE_DATA_IMM cmd prefix */</div><div class='add'>+		batch_size += 4 * num_cmds + updates[i].qwords * 2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * XXX: Create temp bo to copy from, if batch_size becomes too big?</div><div class='add'>+	 *</div><div class='add'>+	 * Worst case: Sum(2 * (each lower level page size) + (top level page size))</div><div class='add'>+	 * Should be reasonably bound..</div><div class='add'>+	 */</div><div class='add'>+	xe_tile_assert(tile, batch_size &lt; SZ_128K);</div><div class='add'>+</div><div class='add'>+	bb = xe_bb_new(gt, batch_size, !q &amp;&amp; xe-&gt;info.has_usm);</div><div class='add'>+	if (IS_ERR(bb))</div><div class='add'>+		return ERR_CAST(bb);</div><div class='add'>+</div><div class='add'>+	/* For sysmem PTE's, need to map them in our hole.. */</div><div class='add'>+	if (!IS_DGFX(xe)) {</div><div class='add'>+		ppgtt_ofs = NUM_KERNEL_PDE - 1;</div><div class='add'>+		if (q) {</div><div class='add'>+			xe_tile_assert(tile, num_updates &lt;= NUM_VMUSA_WRITES_PER_UNIT);</div><div class='add'>+</div><div class='add'>+			sa_bo = drm_suballoc_new(&amp;m-&gt;vm_update_sa, 1,</div><div class='add'>+						 GFP_KERNEL, true, 0);</div><div class='add'>+			if (IS_ERR(sa_bo)) {</div><div class='add'>+				err = PTR_ERR(sa_bo);</div><div class='add'>+				goto err;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			ppgtt_ofs = NUM_KERNEL_PDE +</div><div class='add'>+				(drm_suballoc_soffset(sa_bo) /</div><div class='add'>+				 NUM_VMUSA_UNIT_PER_PAGE);</div><div class='add'>+			page_ofs = (drm_suballoc_soffset(sa_bo) %</div><div class='add'>+				    NUM_VMUSA_UNIT_PER_PAGE) *</div><div class='add'>+				VM_SA_UPDATE_UNIT_SIZE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Map our PT's to gtt */</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(num_updates);</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = ppgtt_ofs * XE_PAGE_SIZE + page_ofs;</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = 0; /* upper_32_bits */</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; num_updates; i++) {</div><div class='add'>+			struct xe_bo *pt_bo = updates[i].pt_bo;</div><div class='add'>+</div><div class='add'>+			xe_tile_assert(tile, pt_bo-&gt;size == SZ_4K);</div><div class='add'>+</div><div class='add'>+			addr = vm-&gt;pt_ops-&gt;pte_encode_bo(pt_bo, 0, pat_index, 0);</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = lower_32_bits(addr);</div><div class='add'>+			bb-&gt;cs[bb-&gt;len++] = upper_32_bits(addr);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+		update_idx = bb-&gt;len;</div><div class='add'>+</div><div class='add'>+		addr = xe_migrate_vm_addr(ppgtt_ofs, 0) +</div><div class='add'>+			(page_ofs / sizeof(u64)) * XE_PAGE_SIZE;</div><div class='add'>+		for (i = 0; i &lt; num_updates; i++)</div><div class='add'>+			write_pgtable(tile, bb, addr + i * XE_PAGE_SIZE,</div><div class='add'>+				      &amp;updates[i], pt_update);</div><div class='add'>+	} else {</div><div class='add'>+		/* phys pages, no preamble required */</div><div class='add'>+		bb-&gt;cs[bb-&gt;len++] = MI_BATCH_BUFFER_END;</div><div class='add'>+		update_idx = bb-&gt;len;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; num_updates; i++)</div><div class='add'>+			write_pgtable(tile, bb, 0, &amp;updates[i], pt_update);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!q)</div><div class='add'>+		mutex_lock(&amp;m-&gt;job_mutex);</div><div class='add'>+</div><div class='add'>+	job = xe_bb_create_migration_job(q ?: m-&gt;q, bb,</div><div class='add'>+					 xe_migrate_batch_base(m, usm),</div><div class='add'>+					 update_idx);</div><div class='add'>+	if (IS_ERR(job)) {</div><div class='add'>+		err = PTR_ERR(job);</div><div class='add'>+		goto err_bb;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait on BO move */</div><div class='add'>+	if (bo) {</div><div class='add'>+		err = job_add_deps(job, bo-&gt;ttm.base.resv,</div><div class='add'>+				   DMA_RESV_USAGE_KERNEL);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_job;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Munmap style VM unbind, need to wait for all jobs to be complete /</div><div class='add'>+	 * trigger preempts before moving forward</div><div class='add'>+	 */</div><div class='add'>+	if (first_munmap_rebind) {</div><div class='add'>+		err = job_add_deps(job, xe_vm_resv(vm),</div><div class='add'>+				   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_job;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_sched_job_last_fence_add_dep(job, vm);</div><div class='add'>+	for (i = 0; !err &amp;&amp; i &lt; num_syncs; i++)</div><div class='add'>+		err = xe_sync_entry_add_deps(&amp;syncs[i], job);</div><div class='add'>+</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_job;</div><div class='add'>+</div><div class='add'>+	if (ops-&gt;pre_commit) {</div><div class='add'>+		pt_update-&gt;job = job;</div><div class='add'>+		err = ops-&gt;pre_commit(pt_update);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_job;</div><div class='add'>+	}</div><div class='add'>+	xe_sched_job_arm(job);</div><div class='add'>+	fence = dma_fence_get(&amp;job-&gt;drm.s_fence-&gt;finished);</div><div class='add'>+	xe_sched_job_push(job);</div><div class='add'>+</div><div class='add'>+	if (!q)</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+</div><div class='add'>+	xe_bb_free(bb, fence);</div><div class='add'>+	drm_suballoc_free(sa_bo, fence);</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+</div><div class='add'>+err_job:</div><div class='add'>+	xe_sched_job_put(job);</div><div class='add'>+err_bb:</div><div class='add'>+	if (!q)</div><div class='add'>+		mutex_unlock(&amp;m-&gt;job_mutex);</div><div class='add'>+	xe_bb_free(bb, NULL);</div><div class='add'>+err:</div><div class='add'>+	drm_suballoc_free(sa_bo, NULL);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_migrate_wait() - Complete all operations using the xe_migrate context</div><div class='add'>+ * @m: Migrate context to wait for.</div><div class='add'>+ *</div><div class='add'>+ * Waits until the GPU no longer uses the migrate context's default engine</div><div class='add'>+ * or its page-table objects. FIXME: What about separate page-table update</div><div class='add'>+ * engines?</div><div class='add'>+ */</div><div class='add'>+void xe_migrate_wait(struct xe_migrate *m)</div><div class='add'>+{</div><div class='add'>+	if (m-&gt;fence)</div><div class='add'>+		dma_fence_wait(m-&gt;fence, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_migrate.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h<br/>new file mode 100644<br/>index 000000000000..951f19318ea4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_migrate.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate.h</a></div><div class='hunk'>@@ -0,0 +1,110 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2020 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MIGRATE_</div><div class='add'>+#define _XE_MIGRATE_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+</div><div class='add'>+struct dma_fence;</div><div class='add'>+struct iosys_map;</div><div class='add'>+struct ttm_resource;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_migrate;</div><div class='add'>+struct xe_migrate_pt_update;</div><div class='add'>+struct xe_sync_entry;</div><div class='add'>+struct xe_pt;</div><div class='add'>+struct xe_tile;</div><div class='add'>+struct xe_vm;</div><div class='add'>+struct xe_vm_pgtable_update;</div><div class='add'>+struct xe_vma;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_migrate_pt_update_ops - Callbacks for the</div><div class='add'>+ * xe_migrate_update_pgtables() function.</div><div class='add'>+ */</div><div class='add'>+struct xe_migrate_pt_update_ops {</div><div class='add'>+	/**</div><div class='add'>+	 * @populate: Populate a command buffer or page-table with ptes.</div><div class='add'>+	 * @pt_update: Embeddable callback argument.</div><div class='add'>+	 * @tile: The tile for the current operation.</div><div class='add'>+	 * @map: struct iosys_map into the memory to be populated.</div><div class='add'>+	 * @pos: If @map is NULL, map into the memory to be populated.</div><div class='add'>+	 * @ofs: qword offset into @map, unused if @map is NULL.</div><div class='add'>+	 * @num_qwords: Number of qwords to write.</div><div class='add'>+	 * @update: Information about the PTEs to be inserted.</div><div class='add'>+	 *</div><div class='add'>+	 * This interface is intended to be used as a callback into the</div><div class='add'>+	 * page-table system to populate command buffers or shared</div><div class='add'>+	 * page-tables with PTEs.</div><div class='add'>+	 */</div><div class='add'>+	void (*populate)(struct xe_migrate_pt_update *pt_update,</div><div class='add'>+			 struct xe_tile *tile, struct iosys_map *map,</div><div class='add'>+			 void *pos, u32 ofs, u32 num_qwords,</div><div class='add'>+			 const struct xe_vm_pgtable_update *update);</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pre_commit: Callback to be called just before arming the</div><div class='add'>+	 * sched_job.</div><div class='add'>+	 * @pt_update: Pointer to embeddable callback argument.</div><div class='add'>+	 *</div><div class='add'>+	 * Return: 0 on success, negative error code on error.</div><div class='add'>+	 */</div><div class='add'>+	int (*pre_commit)(struct xe_migrate_pt_update *pt_update);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_migrate_pt_update - Argument to the</div><div class='add'>+ * struct xe_migrate_pt_update_ops callbacks.</div><div class='add'>+ *</div><div class='add'>+ * Intended to be subclassed to support additional arguments if necessary.</div><div class='add'>+ */</div><div class='add'>+struct xe_migrate_pt_update {</div><div class='add'>+	/** @ops: Pointer to the struct xe_migrate_pt_update_ops callbacks */</div><div class='add'>+	const struct xe_migrate_pt_update_ops *ops;</div><div class='add'>+	/** @vma: The vma we're updating the pagetable for. */</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	/** @job: The job if a GPU page-table update. NULL otherwise */</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	/** @start: Start of update for the range fence */</div><div class='add'>+	u64 start;</div><div class='add'>+	/** @last: Last of update for the range fence */</div><div class='add'>+	u64 last;</div><div class='add'>+	/** @tile_id: Tile ID of the update */</div><div class='add'>+	u8 tile_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_migrate *xe_migrate_init(struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+struct dma_fence *xe_migrate_copy(struct xe_migrate *m,</div><div class='add'>+				  struct xe_bo *src_bo,</div><div class='add'>+				  struct xe_bo *dst_bo,</div><div class='add'>+				  struct ttm_resource *src,</div><div class='add'>+				  struct ttm_resource *dst,</div><div class='add'>+				  bool copy_only_ccs);</div><div class='add'>+</div><div class='add'>+struct dma_fence *xe_migrate_clear(struct xe_migrate *m,</div><div class='add'>+				   struct xe_bo *bo,</div><div class='add'>+				   struct ttm_resource *dst);</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m);</div><div class='add'>+</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_migrate_update_pgtables(struct xe_migrate *m,</div><div class='add'>+			   struct xe_vm *vm,</div><div class='add'>+			   struct xe_bo *bo,</div><div class='add'>+			   struct xe_exec_queue *q,</div><div class='add'>+			   const struct xe_vm_pgtable_update *updates,</div><div class='add'>+			   u32 num_updates,</div><div class='add'>+			   struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+			   struct xe_migrate_pt_update *pt_update);</div><div class='add'>+</div><div class='add'>+void xe_migrate_wait(struct xe_migrate *m);</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_migrate_doc.h b/drivers/gpu/drm/xe/xe_migrate_doc.h<br/>new file mode 100644<br/>index 000000000000..63c7d67b5b62<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_migrate_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_migrate_doc.h</a></div><div class='hunk'>@@ -0,0 +1,88 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MIGRATE_DOC_H_</div><div class='add'>+#define _XE_MIGRATE_DOC_H_</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Migrate Layer</div><div class='add'>+ *</div><div class='add'>+ * The XE migrate layer is used generate jobs which can copy memory (eviction),</div><div class='add'>+ * clear memory, or program tables (binds). This layer exists in every GT, has</div><div class='add'>+ * a migrate engine, and uses a special VM for all generated jobs.</div><div class='add'>+ *</div><div class='add'>+ * Special VM details</div><div class='add'>+ * ==================</div><div class='add'>+ *</div><div class='add'>+ * The special VM is configured with a page structure where we can dynamically</div><div class='add'>+ * map BOs which need to be copied and cleared, dynamically map other VM's page</div><div class='add'>+ * table BOs for updates, and identity map the entire device's VRAM with 1 GB</div><div class='add'>+ * pages.</div><div class='add'>+ *</div><div class='add'>+ * Currently the page structure consists of 32 physical pages with 16 being</div><div class='add'>+ * reserved for BO mapping during copies and clear, 1 reserved for kernel binds,</div><div class='add'>+ * several pages are needed to setup the identity mappings (exact number based</div><div class='add'>+ * on how many bits of address space the device has), and the rest are reserved</div><div class='add'>+ * user bind operations.</div><div class='add'>+ *</div><div class='add'>+ * TODO: Diagram of layout</div><div class='add'>+ *</div><div class='add'>+ * Bind jobs</div><div class='add'>+ * =========</div><div class='add'>+ *</div><div class='add'>+ * A bind job consist of two batches and runs either on the migrate engine</div><div class='add'>+ * (kernel binds) or the bind engine passed in (user binds). In both cases the</div><div class='add'>+ * VM of the engine is the migrate VM.</div><div class='add'>+ *</div><div class='add'>+ * The first batch is used to update the migration VM page structure to point to</div><div class='add'>+ * the bind VM page table BOs which need to be updated. A physical page is</div><div class='add'>+ * required for this. If it is a user bind, the page is allocated from pool of</div><div class='add'>+ * pages reserved user bind operations with drm_suballoc managing this pool. If</div><div class='add'>+ * it is a kernel bind, the page reserved for kernel binds is used.</div><div class='add'>+ *</div><div class='add'>+ * The first batch is only required for devices without VRAM as when the device</div><div class='add'>+ * has VRAM the bind VM page table BOs are in VRAM and the identity mapping can</div><div class='add'>+ * be used.</div><div class='add'>+ *</div><div class='add'>+ * The second batch is used to program page table updated in the bind VM. Why</div><div class='add'>+ * not just one batch? Well the TLBs need to be invalidated between these two</div><div class='add'>+ * batches and that only can be done from the ring.</div><div class='add'>+ *</div><div class='add'>+ * When the bind job complete, the page allocated is returned the pool of pages</div><div class='add'>+ * reserved for user bind operations if a user bind. No need do this for kernel</div><div class='add'>+ * binds as the reserved kernel page is serially used by each job.</div><div class='add'>+ *</div><div class='add'>+ * Copy / clear jobs</div><div class='add'>+ * =================</div><div class='add'>+ *</div><div class='add'>+ * A copy or clear job consist of two batches and runs on the migrate engine.</div><div class='add'>+ *</div><div class='add'>+ * Like binds, the first batch is used update the migration VM page structure.</div><div class='add'>+ * In copy jobs, we need to map the source and destination of the BO into page</div><div class='add'>+ * the structure. In clear jobs, we just need to add 1 mapping of BO into the</div><div class='add'>+ * page structure. We use the 16 reserved pages in migration VM for mappings,</div><div class='add'>+ * this gives us a maximum copy size of 16 MB and maximum clear size of 32 MB.</div><div class='add'>+ *</div><div class='add'>+ * The second batch is used do either do the copy or clear. Again similar to</div><div class='add'>+ * binds, two batches are required as the TLBs need to be invalidated from the</div><div class='add'>+ * ring between the batches.</div><div class='add'>+ *</div><div class='add'>+ * More than one job will be generated if the BO is larger than maximum copy /</div><div class='add'>+ * clear size.</div><div class='add'>+ *</div><div class='add'>+ * Future work</div><div class='add'>+ * ===========</div><div class='add'>+ *</div><div class='add'>+ * Update copy and clear code to use identity mapped VRAM.</div><div class='add'>+ *</div><div class='add'>+ * Can we rework the use of the pages async binds to use all the entries in each</div><div class='add'>+ * page?</div><div class='add'>+ *</div><div class='add'>+ * Using large pages for sysmem mappings.</div><div class='add'>+ *</div><div class='add'>+ * Is it possible to identity map the sysmem? We should explore this.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c<br/>new file mode 100644<br/>index 000000000000..c8c5d74b6e90<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mmio.c</a></div><div class='hunk'>@@ -0,0 +1,524 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021-2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/minmax.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+</div><div class='add'>+#define XEHP_MTCFG_ADDR		XE_REG(0x101800)</div><div class='add'>+#define TILE_COUNT		REG_GENMASK(15, 8)</div><div class='add'>+</div><div class='add'>+#define BAR_SIZE_SHIFT 20</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+_resize_bar(struct xe_device *xe, int resno, resource_size_t size)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	int bar_size = pci_rebar_bytes_to_size(size);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (pci_resource_len(pdev, resno))</div><div class='add'>+		pci_release_resource(pdev, resno);</div><div class='add'>+</div><div class='add'>+	ret = pci_resize_resource(pdev, resno, bar_size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "Failed to resize BAR%d to %dM (%pe). Consider enabling 'Resizable BAR' support in your BIOS\n",</div><div class='add'>+			 resno, 1 &lt;&lt; bar_size, ERR_PTR(ret));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "BAR%d resized to %dM\n", resno, 1 &lt;&lt; bar_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * if force_vram_bar_size is set, attempt to set to the requested size</div><div class='add'>+ * else set to maximum possible size</div><div class='add'>+ */</div><div class='add'>+static void xe_resize_vram_bar(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	struct pci_bus *root = pdev-&gt;bus;</div><div class='add'>+	resource_size_t current_size;</div><div class='add'>+	resource_size_t rebar_size;</div><div class='add'>+	struct resource *root_res;</div><div class='add'>+	u32 bar_size_mask;</div><div class='add'>+	u32 pci_cmd;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* gather some relevant info */</div><div class='add'>+	current_size = pci_resource_len(pdev, LMEM_BAR);</div><div class='add'>+	bar_size_mask = pci_rebar_get_possible_sizes(pdev, LMEM_BAR);</div><div class='add'>+</div><div class='add'>+	if (!bar_size_mask)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* set to a specific size? */</div><div class='add'>+	if (force_vram_bar_size) {</div><div class='add'>+		u32 bar_size_bit;</div><div class='add'>+</div><div class='add'>+		rebar_size = force_vram_bar_size * (resource_size_t)SZ_1M;</div><div class='add'>+</div><div class='add'>+		bar_size_bit = bar_size_mask &amp; BIT(pci_rebar_bytes_to_size(rebar_size));</div><div class='add'>+</div><div class='add'>+		if (!bar_size_bit) {</div><div class='add'>+			drm_info(&amp;xe-&gt;drm,</div><div class='add'>+				 "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leaving default: %lluMiB\n",</div><div class='add'>+				 (u64)rebar_size &gt;&gt; 20, bar_size_mask, (u64)current_size &gt;&gt; 20);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		rebar_size = 1ULL &lt;&lt; (__fls(bar_size_bit) + BAR_SIZE_SHIFT);</div><div class='add'>+</div><div class='add'>+		if (rebar_size == current_size)</div><div class='add'>+			return;</div><div class='add'>+	} else {</div><div class='add'>+		rebar_size = 1ULL &lt;&lt; (__fls(bar_size_mask) + BAR_SIZE_SHIFT);</div><div class='add'>+</div><div class='add'>+		/* only resize if larger than current */</div><div class='add'>+		if (rebar_size &lt;= current_size)</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Attempting to resize bar from %lluMiB -&gt; %lluMiB\n",</div><div class='add'>+		 (u64)current_size &gt;&gt; 20, (u64)rebar_size &gt;&gt; 20);</div><div class='add'>+</div><div class='add'>+	while (root-&gt;parent)</div><div class='add'>+		root = root-&gt;parent;</div><div class='add'>+</div><div class='add'>+	pci_bus_for_each_resource(root, root_res, i) {</div><div class='add'>+		if (root_res &amp;&amp; root_res-&gt;flags &amp; (IORESOURCE_MEM | IORESOURCE_MEM_64) &amp;&amp;</div><div class='add'>+		    root_res-&gt;start &gt; 0x100000000ull)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!root_res) {</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "Can't resize VRAM BAR - platform support is missing. Consider enabling 'Resizable BAR' support in your BIOS\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, PCI_COMMAND, &amp;pci_cmd);</div><div class='add'>+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd &amp; ~PCI_COMMAND_MEMORY);</div><div class='add'>+</div><div class='add'>+	_resize_bar(xe, LMEM_BAR, rebar_size);</div><div class='add'>+</div><div class='add'>+	pci_assign_unassigned_bus_resources(pdev-&gt;bus);</div><div class='add'>+	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)</div><div class='add'>+{</div><div class='add'>+	if (!pci_resource_flags(pdev, bar))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (pci_resource_flags(pdev, bar) &amp; IORESOURCE_UNSET)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!pci_resource_len(pdev, bar))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_determine_lmem_bar_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+</div><div class='add'>+	if (!xe_pci_resource_valid(pdev, LMEM_BAR)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "pci resource is not valid\n");</div><div class='add'>+		return -ENXIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_resize_vram_bar(xe);</div><div class='add'>+</div><div class='add'>+	xe-&gt;mem.vram.io_start = pci_resource_start(pdev, LMEM_BAR);</div><div class='add'>+	xe-&gt;mem.vram.io_size = pci_resource_len(pdev, LMEM_BAR);</div><div class='add'>+	if (!xe-&gt;mem.vram.io_size)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	/* XXX: Need to change when xe link code is ready */</div><div class='add'>+	xe-&gt;mem.vram.dpa_base = 0;</div><div class='add'>+</div><div class='add'>+	/* set up a map to the total memory area. */</div><div class='add'>+	xe-&gt;mem.vram.mapping = ioremap_wc(xe-&gt;mem.vram.io_start, xe-&gt;mem.vram.io_size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_mmio_tile_vram_size() - Collect vram size and offset information</div><div class='add'>+ * @tile: tile to get info for</div><div class='add'>+ * @vram_size: available vram (size - device reserved portions)</div><div class='add'>+ * @tile_size: actual vram size</div><div class='add'>+ * @tile_offset: physical start point in the vram address space</div><div class='add'>+ *</div><div class='add'>+ * There are 4 places for size information:</div><div class='add'>+ * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1)</div><div class='add'>+ * - TILEx size (actual vram size)</div><div class='add'>+ * - GSMBASE offset (TILEx - "stolen")</div><div class='add'>+ * - CSSBASE offset (TILEx - CSS space necessary)</div><div class='add'>+ *</div><div class='add'>+ * CSSBASE is always a lower/smaller offset then GSMBASE.</div><div class='add'>+ *</div><div class='add'>+ * The actual available size of memory is to the CCS or GSM base.</div><div class='add'>+ * NOTE: multi-tile bases will include the tile offset.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size,</div><div class='add'>+				  u64 *tile_size, u64 *tile_offset)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_gt *gt = tile-&gt;primary_gt;</div><div class='add'>+	u64 offset;</div><div class='add'>+	int err;</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* actual size */</div><div class='add'>+	if (unlikely(xe-&gt;info.platform == XE_DG1)) {</div><div class='add'>+		*tile_size = pci_resource_len(to_pci_dev(xe-&gt;drm.dev), LMEM_BAR);</div><div class='add'>+		*tile_offset = 0;</div><div class='add'>+	} else {</div><div class='add'>+		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE_ADDR_RANGE(gt-&gt;info.id));</div><div class='add'>+		*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;</div><div class='add'>+		*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* minus device usage */</div><div class='add'>+	if (xe-&gt;info.has_flat_ccs) {</div><div class='add'>+		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);</div><div class='add'>+		offset = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;</div><div class='add'>+	} else {</div><div class='add'>+		offset = xe_mmio_read64_2x32(gt, GSMBASE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* remove the tile offset so we have just the available size */</div><div class='add'>+	*vram_size = offset - *tile_offset;</div><div class='add'>+</div><div class='add'>+	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_mmio_probe_vram(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	resource_size_t io_size;</div><div class='add'>+	u64 available_size = 0;</div><div class='add'>+	u64 total_size = 0;</div><div class='add'>+	u64 tile_offset;</div><div class='add'>+	u64 tile_size;</div><div class='add'>+	u64 vram_size;</div><div class='add'>+	int err;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Get the size of the root tile's vram for later accessibility comparison */</div><div class='add'>+	tile = xe_device_get_root_tile(xe);</div><div class='add'>+	err = xe_mmio_tile_vram_size(tile, &amp;vram_size, &amp;tile_size, &amp;tile_offset);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_determine_lmem_bar_size(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "VISIBLE VRAM: %pa, %pa\n", &amp;xe-&gt;mem.vram.io_start,</div><div class='add'>+		 &amp;xe-&gt;mem.vram.io_size);</div><div class='add'>+</div><div class='add'>+	io_size = xe-&gt;mem.vram.io_size;</div><div class='add'>+</div><div class='add'>+	/* tile specific ranges */</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		err = xe_mmio_tile_vram_size(tile, &amp;vram_size, &amp;tile_size, &amp;tile_offset);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		tile-&gt;mem.vram.actual_physical_size = tile_size;</div><div class='add'>+		tile-&gt;mem.vram.io_start = xe-&gt;mem.vram.io_start + tile_offset;</div><div class='add'>+		tile-&gt;mem.vram.io_size = min_t(u64, vram_size, io_size);</div><div class='add'>+</div><div class='add'>+		if (!tile-&gt;mem.vram.io_size) {</div><div class='add'>+			drm_err(&amp;xe-&gt;drm, "Tile without any CPU visible VRAM. Aborting.\n");</div><div class='add'>+			return -ENODEV;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		tile-&gt;mem.vram.dpa_base = xe-&gt;mem.vram.dpa_base + tile_offset;</div><div class='add'>+		tile-&gt;mem.vram.usable_size = vram_size;</div><div class='add'>+		tile-&gt;mem.vram.mapping = xe-&gt;mem.vram.mapping + tile_offset;</div><div class='add'>+</div><div class='add'>+		if (tile-&gt;mem.vram.io_size &lt; tile-&gt;mem.vram.usable_size)</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "Small BAR device\n");</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "VRAM[%u, %u]: Actual physical size %pa, usable size exclude stolen %pa, CPU accessible size %pa\n", id,</div><div class='add'>+			 tile-&gt;id, &amp;tile-&gt;mem.vram.actual_physical_size, &amp;tile-&gt;mem.vram.usable_size, &amp;tile-&gt;mem.vram.io_size);</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "VRAM[%u, %u]: DPA range: [%pa-%llx], io range: [%pa-%llx]\n", id, tile-&gt;id,</div><div class='add'>+			 &amp;tile-&gt;mem.vram.dpa_base, tile-&gt;mem.vram.dpa_base + tile-&gt;mem.vram.actual_physical_size,</div><div class='add'>+			 &amp;tile-&gt;mem.vram.io_start, tile-&gt;mem.vram.io_start + tile-&gt;mem.vram.io_size);</div><div class='add'>+</div><div class='add'>+		/* calculate total size using tile size to get the correct HW sizing */</div><div class='add'>+		total_size += tile_size;</div><div class='add'>+		available_size += vram_size;</div><div class='add'>+</div><div class='add'>+		if (total_size &gt; xe-&gt;mem.vram.io_size) {</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "VRAM: %pa is larger than resource %pa\n",</div><div class='add'>+				 &amp;total_size, &amp;xe-&gt;mem.vram.io_size);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		io_size -= min_t(u64, tile_size, io_size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe-&gt;mem.vram.actual_physical_size = total_size;</div><div class='add'>+</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Total VRAM: %pa, %pa\n", &amp;xe-&gt;mem.vram.io_start,</div><div class='add'>+		 &amp;xe-&gt;mem.vram.actual_physical_size);</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "Available VRAM: %pa, %pa\n", &amp;xe-&gt;mem.vram.io_start,</div><div class='add'>+		 &amp;available_size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_mmio_probe_tiles(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	size_t tile_mmio_size = SZ_16M, tile_mmio_ext_size = xe-&gt;info.tile_mmio_ext_size;</div><div class='add'>+	u8 id, tile_count = xe-&gt;info.tile_count;</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	void __iomem *regs;</div><div class='add'>+	u32 mtcfg;</div><div class='add'>+</div><div class='add'>+	if (tile_count == 1)</div><div class='add'>+		goto add_mmio_ext;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.skip_mtcfg) {</div><div class='add'>+		mtcfg = xe_mmio_read64_2x32(gt, XEHP_MTCFG_ADDR);</div><div class='add'>+		tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;</div><div class='add'>+		if (tile_count &lt; xe-&gt;info.tile_count) {</div><div class='add'>+			drm_info(&amp;xe-&gt;drm, "tile_count: %d, reduced_tile_count %d\n",</div><div class='add'>+					xe-&gt;info.tile_count, tile_count);</div><div class='add'>+			xe-&gt;info.tile_count = tile_count;</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * FIXME: Needs some work for standalone media, but should be impossible</div><div class='add'>+			 * with multi-tile for now.</div><div class='add'>+			 */</div><div class='add'>+			xe-&gt;info.gt_count = xe-&gt;info.tile_count;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	regs = xe-&gt;mmio.regs;</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		tile-&gt;mmio.size = tile_mmio_size;</div><div class='add'>+		tile-&gt;mmio.regs = regs;</div><div class='add'>+		regs += tile_mmio_size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+add_mmio_ext:</div><div class='add'>+	/*</div><div class='add'>+	 * By design, there's a contiguous multi-tile MMIO space (16MB hard coded per tile).</div><div class='add'>+	 * When supported, there could be an additional contiguous multi-tile MMIO extension</div><div class='add'>+	 * space ON TOP of it, and hence the necessity for distinguished MMIO spaces.</div><div class='add'>+	 */</div><div class='add'>+	if (xe-&gt;info.has_mmio_ext) {</div><div class='add'>+		regs = xe-&gt;mmio.regs + tile_mmio_size * tile_count;</div><div class='add'>+</div><div class='add'>+		for_each_tile(tile, xe, id) {</div><div class='add'>+			tile-&gt;mmio_ext.size = tile_mmio_ext_size;</div><div class='add'>+			tile-&gt;mmio_ext.regs = regs;</div><div class='add'>+</div><div class='add'>+			regs += tile_mmio_ext_size;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmio_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = arg;</div><div class='add'>+</div><div class='add'>+	pci_iounmap(to_pci_dev(xe-&gt;drm.dev), xe-&gt;mmio.regs);</div><div class='add'>+	if (xe-&gt;mem.vram.mapping)</div><div class='add'>+		iounmap(xe-&gt;mem.vram.mapping);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_verify_lmem_ready(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The boot firmware initializes local memory and assesses its health.</div><div class='add'>+	 * If memory training fails, the punit will have been instructed to</div><div class='add'>+	 * keep the GT powered down; we won't be able to communicate with it</div><div class='add'>+	 * and we should not continue with driver initialization.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; !(xe_mmio_read32(gt, GU_CNTL) &amp; LMEM_INIT)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "VRAM not initialized by firmware\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_mmio_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	const int mmio_bar = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Map the entire BAR.</div><div class='add'>+	 * The first 16MB of the BAR, belong to the root tile, and include:</div><div class='add'>+	 * registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).</div><div class='add'>+	 */</div><div class='add'>+	xe-&gt;mmio.size = pci_resource_len(pdev, mmio_bar);</div><div class='add'>+	xe-&gt;mmio.regs = pci_iomap(pdev, mmio_bar, 0);</div><div class='add'>+	if (xe-&gt;mmio.regs == NULL) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "failed to map registers\n");</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, mmio_fini, xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_mmio_root_tile_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* Setup first tile; other tiles (if present) will be setup later. */</div><div class='add'>+	root_tile-&gt;mmio.size = SZ_16M;</div><div class='add'>+	root_tile-&gt;mmio.regs = xe-&gt;mmio.regs;</div><div class='add'>+</div><div class='add'>+	err = xe_verify_lmem_ready(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_mmio_read64_2x32() - Read a 64-bit register as two 32-bit reads</div><div class='add'>+ * @gt: MMIO target GT</div><div class='add'>+ * @reg: register to read value from</div><div class='add'>+ *</div><div class='add'>+ * Although Intel GPUs have some 64-bit registers, the hardware officially</div><div class='add'>+ * only supports GTTMMADR register reads of 32 bits or smaller.  Even if</div><div class='add'>+ * a readq operation may return a reasonable value, that violation of the</div><div class='add'>+ * spec shouldn't be relied upon and all 64-bit register reads should be</div><div class='add'>+ * performed as two 32-bit reads of the upper and lower dwords.</div><div class='add'>+ *</div><div class='add'>+ * When reading registers that may be changing (such as</div><div class='add'>+ * counters), a rollover of the lower dword between the two 32-bit reads</div><div class='add'>+ * can be problematic.  This function attempts to ensure the upper dword has</div><div class='add'>+ * stabilized before returning the 64-bit value.</div><div class='add'>+ *</div><div class='add'>+ * Note that because this function may re-read the register multiple times</div><div class='add'>+ * while waiting for the value to stabilize it should not be used to read</div><div class='add'>+ * any registers where read operations have side effects.</div><div class='add'>+ *</div><div class='add'>+ * Returns the value of the 64-bit register.</div><div class='add'>+ */</div><div class='add'>+u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };</div><div class='add'>+	u32 ldw, udw, oldudw, retries;</div><div class='add'>+</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit) {</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+		reg_udw.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	oldudw = xe_mmio_read32(gt, reg_udw);</div><div class='add'>+	for (retries = 5; retries; --retries) {</div><div class='add'>+		ldw = xe_mmio_read32(gt, reg);</div><div class='add'>+		udw = xe_mmio_read32(gt, reg_udw);</div><div class='add'>+</div><div class='add'>+		if (udw == oldudw)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		oldudw = udw;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_WARN(gt, retries == 0,</div><div class='add'>+		   "64-bit read of %#x did not stabilize\n", reg.addr);</div><div class='add'>+</div><div class='add'>+	return (u64)udw &lt;&lt; 32 | ldw;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_mmio_wait32() - Wait for a register to match the desired masked value</div><div class='add'>+ * @gt: MMIO target GT</div><div class='add'>+ * @reg: register to read value from</div><div class='add'>+ * @mask: mask to be applied to the value read from the register</div><div class='add'>+ * @val: desired value after applying the mask</div><div class='add'>+ * @timeout_us: time out after this period of time. Wait logic tries to be</div><div class='add'>+ * smart, applying an exponential backoff until @timeout_us is reached.</div><div class='add'>+ * @out_val: if not NULL, points where to store the last unmasked value</div><div class='add'>+ * @atomic: needs to be true if calling from an atomic context</div><div class='add'>+ *</div><div class='add'>+ * This function polls for the desired masked value and returns zero on success</div><div class='add'>+ * or -ETIMEDOUT if timed out.</div><div class='add'>+ *</div><div class='add'>+ * Note that @timeout_us represents the minimum amount of time to wait before</div><div class='add'>+ * giving up. The actual time taken by this function can be a little more than</div><div class='add'>+ * @timeout_us for different reasons, specially in non-atomic contexts. Thus,</div><div class='add'>+ * it is possible that this function succeeds even after @timeout_us has passed.</div><div class='add'>+ */</div><div class='add'>+int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,</div><div class='add'>+		   u32 *out_val, bool atomic)</div><div class='add'>+{</div><div class='add'>+	ktime_t cur = ktime_get_raw();</div><div class='add'>+	const ktime_t end = ktime_add_us(cur, timeout_us);</div><div class='add'>+	int ret = -ETIMEDOUT;</div><div class='add'>+	s64 wait = 10;</div><div class='add'>+	u32 read;</div><div class='add'>+</div><div class='add'>+	for (;;) {</div><div class='add'>+		read = xe_mmio_read32(gt, reg);</div><div class='add'>+		if ((read &amp; mask) == val) {</div><div class='add'>+			ret = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cur = ktime_get_raw();</div><div class='add'>+		if (!ktime_before(cur, end))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (ktime_after(ktime_add_us(cur, wait), end))</div><div class='add'>+			wait = ktime_us_delta(end, cur);</div><div class='add'>+</div><div class='add'>+		if (atomic)</div><div class='add'>+			udelay(wait);</div><div class='add'>+		else</div><div class='add'>+			usleep_range(wait, wait &lt;&lt; 1);</div><div class='add'>+		wait &lt;&lt;= 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret != 0) {</div><div class='add'>+		read = xe_mmio_read32(gt, reg);</div><div class='add'>+		if ((read &amp; mask) == val)</div><div class='add'>+			ret = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (out_val)</div><div class='add'>+		*out_val = read;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h<br/>new file mode 100644<br/>index 000000000000..98de5c13c89b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_mmio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mmio.h</a></div><div class='hunk'>@@ -0,0 +1,107 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021-2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MMIO_H_</div><div class='add'>+#define _XE_MMIO_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_file;</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+#define LMEM_BAR		2</div><div class='add'>+</div><div class='add'>+int xe_mmio_init(struct xe_device *xe);</div><div class='add'>+int xe_mmio_root_tile_init(struct xe_device *xe);</div><div class='add'>+void xe_mmio_probe_tiles(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+static inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit)</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+</div><div class='add'>+	return readb((reg.ext ? tile-&gt;mmio_ext.regs : tile-&gt;mmio.regs) + reg.addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit)</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+</div><div class='add'>+	return readw((reg.ext ? tile-&gt;mmio_ext.regs : tile-&gt;mmio.regs) + reg.addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_mmio_write32(struct xe_gt *gt,</div><div class='add'>+				   struct xe_reg reg, u32 val)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit)</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+</div><div class='add'>+	writel(val, (reg.ext ? tile-&gt;mmio_ext.regs : tile-&gt;mmio.regs) + reg.addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit)</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+</div><div class='add'>+	return readl((reg.ext ? tile-&gt;mmio_ext.regs : tile-&gt;mmio.regs) + reg.addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,</div><div class='add'>+				u32 set)</div><div class='add'>+{</div><div class='add'>+	u32 old, reg_val;</div><div class='add'>+</div><div class='add'>+	old = xe_mmio_read32(gt, reg);</div><div class='add'>+	reg_val = (old &amp; ~clr) | set;</div><div class='add'>+	xe_mmio_write32(gt, reg, reg_val);</div><div class='add'>+</div><div class='add'>+	return old;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,</div><div class='add'>+					     struct xe_reg reg, u32 val,</div><div class='add'>+					     u32 mask, u32 eval)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, reg, val);</div><div class='add'>+	reg_val = xe_mmio_read32(gt, reg);</div><div class='add'>+</div><div class='add'>+	return (reg_val &amp; mask) != eval ? -EINVAL : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_mmio_in_range(const struct xe_gt *gt,</div><div class='add'>+				    const struct xe_mmio_range *range,</div><div class='add'>+				    struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	if (reg.addr &lt; gt-&gt;mmio.adj_limit)</div><div class='add'>+		reg.addr += gt-&gt;mmio.adj_offset;</div><div class='add'>+</div><div class='add'>+	return range &amp;&amp; reg.addr &gt;= range-&gt;start &amp;&amp; reg.addr &lt;= range-&gt;end;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_mmio_probe_vram(struct xe_device *xe);</div><div class='add'>+u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg);</div><div class='add'>+int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,</div><div class='add'>+		   u32 *out_val, bool atomic);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c<br/>new file mode 100644<br/>index 000000000000..ef79552e4f2f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_mocs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mocs.c</a></div><div class='hunk'>@@ -0,0 +1,580 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_mocs.h"</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_step_types.h"</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)</div><div class='add'>+#define mocs_dbg drm_dbg</div><div class='add'>+#else</div><div class='add'>+__printf(2, 3)</div><div class='add'>+static inline void mocs_dbg(const struct drm_device *dev,</div><div class='add'>+			    const char *format, ...)</div><div class='add'>+{ /* noop */ }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	HAS_GLOBAL_MOCS = BIT(0),</div><div class='add'>+	HAS_LNCF_MOCS = BIT(1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_mocs_entry {</div><div class='add'>+	u32 control_value;</div><div class='add'>+	u16 l3cc_value;</div><div class='add'>+	u16 used;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_mocs_info {</div><div class='add'>+	unsigned int size;</div><div class='add'>+	unsigned int n_entries;</div><div class='add'>+	const struct xe_mocs_entry *table;</div><div class='add'>+	u8 uc_index;</div><div class='add'>+	u8 wb_index;</div><div class='add'>+	u8 unused_entries_index;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */</div><div class='add'>+#define _LE_CACHEABILITY(value)	((value) &lt;&lt; 0)</div><div class='add'>+#define _LE_TGT_CACHE(value)	((value) &lt;&lt; 2)</div><div class='add'>+#define LE_LRUM(value)		((value) &lt;&lt; 4)</div><div class='add'>+#define LE_AOM(value)		((value) &lt;&lt; 6)</div><div class='add'>+#define LE_RSC(value)		((value) &lt;&lt; 7)</div><div class='add'>+#define LE_SCC(value)		((value) &lt;&lt; 8)</div><div class='add'>+#define LE_PFM(value)		((value) &lt;&lt; 11)</div><div class='add'>+#define LE_SCF(value)		((value) &lt;&lt; 14)</div><div class='add'>+#define LE_COS(value)		((value) &lt;&lt; 15)</div><div class='add'>+#define LE_SSE(value)		((value) &lt;&lt; 17)</div><div class='add'>+</div><div class='add'>+/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */</div><div class='add'>+#define L3_ESC(value)		((value) &lt;&lt; 0)</div><div class='add'>+#define L3_SCC(value)		((value) &lt;&lt; 1)</div><div class='add'>+#define _L3_CACHEABILITY(value)	((value) &lt;&lt; 4)</div><div class='add'>+#define L3_GLBGO(value)		((value) &lt;&lt; 6)</div><div class='add'>+#define L3_LKUP(value)		((value) &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */</div><div class='add'>+#define IG_PAT				REG_BIT(8)</div><div class='add'>+#define L3_CACHE_POLICY_MASK		REG_GENMASK(5, 4)</div><div class='add'>+#define L4_CACHE_POLICY_MASK		REG_GENMASK(3, 2)</div><div class='add'>+</div><div class='add'>+/* Helper defines */</div><div class='add'>+#define XELP_NUM_MOCS_ENTRIES	64  /* 63-64 are reserved, but configured. */</div><div class='add'>+#define PVC_NUM_MOCS_ENTRIES	3</div><div class='add'>+#define MTL_NUM_MOCS_ENTRIES    16</div><div class='add'>+#define XE2_NUM_MOCS_ENTRIES	16</div><div class='add'>+</div><div class='add'>+/* (e)LLC caching options */</div><div class='add'>+/*</div><div class='add'>+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means</div><div class='add'>+ * the same as LE_UC</div><div class='add'>+ */</div><div class='add'>+#define LE_0_PAGETABLE		_LE_CACHEABILITY(0)</div><div class='add'>+#define LE_1_UC			_LE_CACHEABILITY(1)</div><div class='add'>+#define LE_2_WT			_LE_CACHEABILITY(2)</div><div class='add'>+#define LE_3_WB			_LE_CACHEABILITY(3)</div><div class='add'>+</div><div class='add'>+/* Target cache */</div><div class='add'>+#define LE_TC_0_PAGETABLE	_LE_TGT_CACHE(0)</div><div class='add'>+#define LE_TC_1_LLC		_LE_TGT_CACHE(1)</div><div class='add'>+#define LE_TC_2_LLC_ELLC	_LE_TGT_CACHE(2)</div><div class='add'>+#define LE_TC_3_LLC_ELLC_ALT	_LE_TGT_CACHE(3)</div><div class='add'>+</div><div class='add'>+/* L3 caching options */</div><div class='add'>+#define L3_0_DIRECT		_L3_CACHEABILITY(0)</div><div class='add'>+#define L3_1_UC			_L3_CACHEABILITY(1)</div><div class='add'>+#define L3_2_RESERVED		_L3_CACHEABILITY(2)</div><div class='add'>+#define L3_3_WB			_L3_CACHEABILITY(3)</div><div class='add'>+</div><div class='add'>+/* L4 caching options */</div><div class='add'>+#define L4_0_WB                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 0)</div><div class='add'>+#define L4_1_WT                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 1)</div><div class='add'>+#define L4_3_UC                 REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 3)</div><div class='add'>+</div><div class='add'>+#define XE2_L3_0_WB		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 0)</div><div class='add'>+/* XD: WB Transient Display */</div><div class='add'>+#define XE2_L3_1_XD		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 1)</div><div class='add'>+#define XE2_L3_3_UC		REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 3)</div><div class='add'>+</div><div class='add'>+#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \</div><div class='add'>+	[__idx] = { \</div><div class='add'>+		.control_value = __control_value, \</div><div class='add'>+		.l3cc_value = __l3cc_value, \</div><div class='add'>+		.used = 1, \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * MOCS tables</div><div class='add'>+ *</div><div class='add'>+ * These are the MOCS tables that are programmed across all the rings.</div><div class='add'>+ * The control value is programmed to all the rings that support the</div><div class='add'>+ * MOCS registers. While the l3cc_values are only programmed to the</div><div class='add'>+ * LNCFCMOCS0 - LNCFCMOCS32 registers.</div><div class='add'>+ *</div><div class='add'>+ * These tables are intended to be kept reasonably consistent across</div><div class='add'>+ * HW platforms, and for ICL+, be identical across OSes. To achieve</div><div class='add'>+ * that, the list of entries is published as part of bspec.</div><div class='add'>+ *</div><div class='add'>+ * Entries not part of the following tables are undefined as far as userspace is</div><div class='add'>+ * concerned and shouldn't be relied upon. The last few entries are reserved by</div><div class='add'>+ * the hardware. They should be initialized according to bspec and never used.</div><div class='add'>+ *</div><div class='add'>+ * NOTE1: These tables are part of bspec and defined as part of the hardware</div><div class='add'>+ * interface. It is expected that, for specific hardware platform, existing</div><div class='add'>+ * entries will remain constant and the table will only be updated by adding new</div><div class='add'>+ * entries, filling unused positions.</div><div class='add'>+ *</div><div class='add'>+ * NOTE2: Reserved and unspecified MOCS indices have been set to L3 WB. These</div><div class='add'>+ * reserved entries should never be used. They may be changed to low performant</div><div class='add'>+ * variants with better coherency in the future if more entries are needed.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry gen12_mocs_desc[] = {</div><div class='add'>+	/* Base - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(2,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Base - Uncached */</div><div class='add'>+	MOCS_ENTRY(3,</div><div class='add'>+		   LE_1_UC | LE_TC_1_LLC,</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Base - L3 */</div><div class='add'>+	MOCS_ENTRY(4,</div><div class='add'>+		   LE_1_UC | LE_TC_1_LLC,</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Base - LLC */</div><div class='add'>+	MOCS_ENTRY(5,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Age 0 - LLC */</div><div class='add'>+	MOCS_ENTRY(6,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Age 0 - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(7,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Age: Don't Chg. - LLC */</div><div class='add'>+	MOCS_ENTRY(8,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Age: Don't Chg. - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(9,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* No AOM - LLC */</div><div class='add'>+	MOCS_ENTRY(10,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* No AOM - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(11,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* No AOM; Age 0 - LLC */</div><div class='add'>+	MOCS_ENTRY(12,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* No AOM; Age 0 - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(13,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* No AOM; Age:DC - LLC */</div><div class='add'>+	MOCS_ENTRY(14,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* No AOM; Age:DC - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(15,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Self-Snoop - L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(18,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Skip Caching - L3 + LLC(12.5%) */</div><div class='add'>+	MOCS_ENTRY(19,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Skip Caching - L3 + LLC(25%) */</div><div class='add'>+	MOCS_ENTRY(20,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Skip Caching - L3 + LLC(50%) */</div><div class='add'>+	MOCS_ENTRY(21,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Skip Caching - L3 + LLC(75%) */</div><div class='add'>+	MOCS_ENTRY(22,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Skip Caching - L3 + LLC(87.5%) */</div><div class='add'>+	MOCS_ENTRY(23,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */</div><div class='add'>+	MOCS_ENTRY(48,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Implicitly enable L1 - HDC:L1 + L3 */</div><div class='add'>+	MOCS_ENTRY(49,</div><div class='add'>+		   LE_1_UC | LE_TC_1_LLC,</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* Implicitly enable L1 - HDC:L1 + LLC */</div><div class='add'>+	MOCS_ENTRY(50,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Implicitly enable L1 - HDC:L1 */</div><div class='add'>+	MOCS_ENTRY(51,</div><div class='add'>+		   LE_1_UC | LE_TC_1_LLC,</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* HW Special Case (CCS) */</div><div class='add'>+	MOCS_ENTRY(60,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* HW Special Case (Displayable) */</div><div class='add'>+	MOCS_ENTRY(61,</div><div class='add'>+		   LE_1_UC | LE_TC_1_LLC,</div><div class='add'>+		   L3_3_WB),</div><div class='add'>+	/* HW Reserved - SW program but never use */</div><div class='add'>+	MOCS_ENTRY(62,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* HW Reserved - SW program but never use */</div><div class='add'>+	MOCS_ENTRY(63,</div><div class='add'>+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),</div><div class='add'>+		   L3_1_UC)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry dg1_mocs_desc[] = {</div><div class='add'>+	/* UC */</div><div class='add'>+	MOCS_ENTRY(1, 0, L3_1_UC),</div><div class='add'>+	/* WB - L3 */</div><div class='add'>+	MOCS_ENTRY(5, 0, L3_3_WB),</div><div class='add'>+	/* WB - L3 50% */</div><div class='add'>+	MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),</div><div class='add'>+	/* WB - L3 25% */</div><div class='add'>+	MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),</div><div class='add'>+	/* WB - L3 12.5% */</div><div class='add'>+	MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),</div><div class='add'>+</div><div class='add'>+	/* HDC:L1 + L3 */</div><div class='add'>+	MOCS_ENTRY(48, 0, L3_3_WB),</div><div class='add'>+	/* HDC:L1 */</div><div class='add'>+	MOCS_ENTRY(49, 0, L3_1_UC),</div><div class='add'>+</div><div class='add'>+	/* HW Reserved */</div><div class='add'>+	MOCS_ENTRY(60, 0, L3_1_UC),</div><div class='add'>+	MOCS_ENTRY(61, 0, L3_1_UC),</div><div class='add'>+	MOCS_ENTRY(62, 0, L3_1_UC),</div><div class='add'>+	MOCS_ENTRY(63, 0, L3_1_UC),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry dg2_mocs_desc[] = {</div><div class='add'>+	/* UC - Coherent; GO:L3 */</div><div class='add'>+	MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),</div><div class='add'>+	/* UC - Coherent; GO:Memory */</div><div class='add'>+	MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),</div><div class='add'>+	/* UC - Non-Coherent; GO:Memory */</div><div class='add'>+	MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),</div><div class='add'>+</div><div class='add'>+	/* WB - LC */</div><div class='add'>+	MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry dg2_mocs_desc_g10_ax[] = {</div><div class='add'>+	/* Wa_14011441408: Set Go to Memory for MOCS#0 */</div><div class='add'>+	MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),</div><div class='add'>+	/* UC - Coherent; GO:Memory */</div><div class='add'>+	MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),</div><div class='add'>+	/* UC - Non-Coherent; GO:Memory */</div><div class='add'>+	MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),</div><div class='add'>+</div><div class='add'>+	/* WB - LC */</div><div class='add'>+	MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry pvc_mocs_desc[] = {</div><div class='add'>+	/* Error */</div><div class='add'>+	MOCS_ENTRY(0, 0, L3_3_WB),</div><div class='add'>+</div><div class='add'>+	/* UC */</div><div class='add'>+	MOCS_ENTRY(1, 0, L3_1_UC),</div><div class='add'>+</div><div class='add'>+	/* WB */</div><div class='add'>+	MOCS_ENTRY(2, 0, L3_3_WB),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry mtl_mocs_desc[] = {</div><div class='add'>+	/* Error - Reserved for Non-Use */</div><div class='add'>+	MOCS_ENTRY(0,</div><div class='add'>+		   0,</div><div class='add'>+		   L3_LKUP(1) | L3_3_WB),</div><div class='add'>+	/* Cached - L3 + L4 */</div><div class='add'>+	MOCS_ENTRY(1,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_LKUP(1) | L3_3_WB),</div><div class='add'>+	/* L4 - GO:L3 */</div><div class='add'>+	MOCS_ENTRY(2,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_LKUP(1) | L3_1_UC),</div><div class='add'>+	/* Uncached - GO:L3 */</div><div class='add'>+	MOCS_ENTRY(3,</div><div class='add'>+		   IG_PAT | L4_3_UC,</div><div class='add'>+		   L3_LKUP(1) | L3_1_UC),</div><div class='add'>+	/* L4 - GO:Mem */</div><div class='add'>+	MOCS_ENTRY(4,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),</div><div class='add'>+	/* Uncached - GO:Mem */</div><div class='add'>+	MOCS_ENTRY(5,</div><div class='add'>+		   IG_PAT | L4_3_UC,</div><div class='add'>+		   L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),</div><div class='add'>+	/* L4 - L3:NoLKUP; GO:L3 */</div><div class='add'>+	MOCS_ENTRY(6,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* Uncached - L3:NoLKUP; GO:L3 */</div><div class='add'>+	MOCS_ENTRY(7,</div><div class='add'>+		   IG_PAT | L4_3_UC,</div><div class='add'>+		   L3_1_UC),</div><div class='add'>+	/* L4 - L3:NoLKUP; GO:Mem */</div><div class='add'>+	MOCS_ENTRY(8,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_GLBGO(1) | L3_1_UC),</div><div class='add'>+	/* Uncached - L3:NoLKUP; GO:Mem */</div><div class='add'>+	MOCS_ENTRY(9,</div><div class='add'>+		   IG_PAT | L4_3_UC,</div><div class='add'>+		   L3_GLBGO(1) | L3_1_UC),</div><div class='add'>+	/* Display - L3; L4:WT */</div><div class='add'>+	MOCS_ENTRY(14,</div><div class='add'>+		   IG_PAT | L4_1_WT,</div><div class='add'>+		   L3_LKUP(1) | L3_3_WB),</div><div class='add'>+	/* CCS - Non-Displayable */</div><div class='add'>+	MOCS_ENTRY(15,</div><div class='add'>+		   IG_PAT,</div><div class='add'>+		   L3_GLBGO(1) | L3_1_UC),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_mocs_entry xe2_mocs_table[] = {</div><div class='add'>+	/* Defer to PAT */</div><div class='add'>+	MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),</div><div class='add'>+	/* Cached L3, Uncached L4 */</div><div class='add'>+	MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),</div><div class='add'>+	/* Uncached L3, Cached L4 */</div><div class='add'>+	MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),</div><div class='add'>+	/* Uncached L3 + L4 */</div><div class='add'>+	MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),</div><div class='add'>+	/* Cached L3 + L4 */</div><div class='add'>+	MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static unsigned int get_mocs_settings(struct xe_device *xe,</div><div class='add'>+				      struct xe_mocs_info *info)</div><div class='add'>+{</div><div class='add'>+	unsigned int flags = 0;</div><div class='add'>+</div><div class='add'>+	memset(info, 0, sizeof(struct xe_mocs_info));</div><div class='add'>+</div><div class='add'>+	switch (xe-&gt;info.platform) {</div><div class='add'>+	case XE_LUNARLAKE:</div><div class='add'>+		info-&gt;size = ARRAY_SIZE(xe2_mocs_table);</div><div class='add'>+		info-&gt;table = xe2_mocs_table;</div><div class='add'>+		info-&gt;n_entries = XE2_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;uc_index = 3;</div><div class='add'>+		info-&gt;wb_index = 4;</div><div class='add'>+		info-&gt;unused_entries_index = 4;</div><div class='add'>+		break;</div><div class='add'>+	case XE_PVC:</div><div class='add'>+		info-&gt;size = ARRAY_SIZE(pvc_mocs_desc);</div><div class='add'>+		info-&gt;table = pvc_mocs_desc;</div><div class='add'>+		info-&gt;n_entries = PVC_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;uc_index = 1;</div><div class='add'>+		info-&gt;wb_index = 2;</div><div class='add'>+		info-&gt;unused_entries_index = 2;</div><div class='add'>+		break;</div><div class='add'>+	case XE_METEORLAKE:</div><div class='add'>+		info-&gt;size = ARRAY_SIZE(mtl_mocs_desc);</div><div class='add'>+		info-&gt;table = mtl_mocs_desc;</div><div class='add'>+		info-&gt;n_entries = MTL_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;uc_index = 9;</div><div class='add'>+		info-&gt;unused_entries_index = 1;</div><div class='add'>+		break;</div><div class='add'>+	case XE_DG2:</div><div class='add'>+		if (xe-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G10 &amp;&amp;</div><div class='add'>+		    xe-&gt;info.step.graphics &gt;= STEP_A0 &amp;&amp;</div><div class='add'>+		    xe-&gt;info.step.graphics &lt;= STEP_B0) {</div><div class='add'>+			info-&gt;size = ARRAY_SIZE(dg2_mocs_desc_g10_ax);</div><div class='add'>+			info-&gt;table = dg2_mocs_desc_g10_ax;</div><div class='add'>+		} else {</div><div class='add'>+			info-&gt;size = ARRAY_SIZE(dg2_mocs_desc);</div><div class='add'>+			info-&gt;table = dg2_mocs_desc;</div><div class='add'>+		}</div><div class='add'>+		info-&gt;uc_index = 1;</div><div class='add'>+		info-&gt;n_entries = XELP_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;unused_entries_index = 3;</div><div class='add'>+		break;</div><div class='add'>+	case XE_DG1:</div><div class='add'>+		info-&gt;size = ARRAY_SIZE(dg1_mocs_desc);</div><div class='add'>+		info-&gt;table = dg1_mocs_desc;</div><div class='add'>+		info-&gt;uc_index = 1;</div><div class='add'>+		info-&gt;n_entries = XELP_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;unused_entries_index = 5;</div><div class='add'>+		break;</div><div class='add'>+	case XE_TIGERLAKE:</div><div class='add'>+	case XE_ROCKETLAKE:</div><div class='add'>+	case XE_ALDERLAKE_S:</div><div class='add'>+	case XE_ALDERLAKE_P:</div><div class='add'>+	case XE_ALDERLAKE_N:</div><div class='add'>+		info-&gt;size  = ARRAY_SIZE(gen12_mocs_desc);</div><div class='add'>+		info-&gt;table = gen12_mocs_desc;</div><div class='add'>+		info-&gt;n_entries = XELP_NUM_MOCS_ENTRIES;</div><div class='add'>+		info-&gt;uc_index = 3;</div><div class='add'>+		info-&gt;unused_entries_index = 2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Platform that should have a MOCS table does not.\n");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Index 0 is a reserved/unused table entry on most platforms, but</div><div class='add'>+	 * even on those where it does represent a legitimate MOCS entry, it</div><div class='add'>+	 * never represents the "most cached, least coherent" behavior we want</div><div class='add'>+	 * to populate undefined table rows with.  So if unused_entries_index</div><div class='add'>+	 * is still 0 at this point, we'll assume that it was omitted by</div><div class='add'>+	 * mistake in the switch statement above.</div><div class='add'>+	 */</div><div class='add'>+	xe_assert(xe, info-&gt;unused_entries_index != 0);</div><div class='add'>+</div><div class='add'>+	if (XE_WARN_ON(info-&gt;size &gt; info-&gt;n_entries)) {</div><div class='add'>+		info-&gt;table = NULL;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) &gt;= 20)</div><div class='add'>+		flags |= HAS_GLOBAL_MOCS;</div><div class='add'>+	if (GRAPHICS_VER(xe) &lt; 20)</div><div class='add'>+		flags |= HAS_LNCF_MOCS;</div><div class='add'>+</div><div class='add'>+	return flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Get control_value from MOCS entry.  If the table entry is not defined, the</div><div class='add'>+ * settings from unused_entries_index will be returned.</div><div class='add'>+ */</div><div class='add'>+static u32 get_entry_control(const struct xe_mocs_info *info,</div><div class='add'>+			     unsigned int index)</div><div class='add'>+{</div><div class='add'>+	if (index &lt; info-&gt;size &amp;&amp; info-&gt;table[index].used)</div><div class='add'>+		return info-&gt;table[index].control_value;</div><div class='add'>+	return info-&gt;table[info-&gt;unused_entries_index].control_value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __init_mocs_table(struct xe_gt *gt,</div><div class='add'>+			      const struct xe_mocs_info *info)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 mocs;</div><div class='add'>+</div><div class='add'>+	mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "entries:%d\n", info-&gt;n_entries);</div><div class='add'>+	drm_WARN_ONCE(&amp;xe-&gt;drm, !info-&gt;unused_entries_index,</div><div class='add'>+		      "Unused entries index should have been defined\n");</div><div class='add'>+	for (i = 0;</div><div class='add'>+	     i &lt; info-&gt;n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;</div><div class='add'>+	     i++) {</div><div class='add'>+		mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "GLOB_MOCS[%d] 0x%x 0x%x\n", i,</div><div class='add'>+			 XELP_GLOBAL_MOCS(i).addr, mocs);</div><div class='add'>+</div><div class='add'>+		if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt; 1250)</div><div class='add'>+			xe_gt_mcr_multicast_write(gt, XEHP_GLOBAL_MOCS(i), mocs);</div><div class='add'>+		else</div><div class='add'>+			xe_mmio_write32(gt, XELP_GLOBAL_MOCS(i), mocs);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Get l3cc_value from MOCS entry taking into account when it's not used</div><div class='add'>+ * then if unused_entries_index is not zero then its value will be returned</div><div class='add'>+ * otherwise I915_MOCS_PTE's value is returned in this case.</div><div class='add'>+ */</div><div class='add'>+static u16 get_entry_l3cc(const struct xe_mocs_info *info,</div><div class='add'>+			  unsigned int index)</div><div class='add'>+{</div><div class='add'>+	if (index &lt; info-&gt;size &amp;&amp; info-&gt;table[index].used)</div><div class='add'>+		return info-&gt;table[index].l3cc_value;</div><div class='add'>+	return info-&gt;table[info-&gt;unused_entries_index].l3cc_value;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 l3cc_combine(u16 low, u16 high)</div><div class='add'>+{</div><div class='add'>+	return low | (u32)high &lt;&lt; 16;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void init_l3cc_table(struct xe_gt *gt,</div><div class='add'>+			    const struct xe_mocs_info *info)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 l3cc;</div><div class='add'>+</div><div class='add'>+	mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "entries:%d\n", info-&gt;n_entries);</div><div class='add'>+	for (i = 0;</div><div class='add'>+	     i &lt; (info-&gt;n_entries + 1) / 2 ?</div><div class='add'>+	     (l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),</div><div class='add'>+				  get_entry_l3cc(info, 2 * i + 1))), 1 : 0;</div><div class='add'>+	     i++) {</div><div class='add'>+		mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "LNCFCMOCS[%d] 0x%x 0x%x\n", i, XELP_LNCFCMOCS(i).addr,</div><div class='add'>+			 l3cc);</div><div class='add'>+</div><div class='add'>+		if (GRAPHICS_VERx100(gt_to_xe(gt)) &gt;= 1250)</div><div class='add'>+			xe_gt_mcr_multicast_write(gt, XEHP_LNCFCMOCS(i), l3cc);</div><div class='add'>+		else</div><div class='add'>+			xe_mmio_write32(gt, XELP_LNCFCMOCS(i), l3cc);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_mocs_init_early(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_mocs_info table;</div><div class='add'>+</div><div class='add'>+	get_mocs_settings(gt_to_xe(gt), &amp;table);</div><div class='add'>+	gt-&gt;mocs.uc_index = table.uc_index;</div><div class='add'>+	gt-&gt;mocs.wb_index = table.wb_index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_mocs_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_mocs_info table;</div><div class='add'>+	unsigned int flags;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * MOCS settings are split between "GLOB_MOCS" and/or "LNCFCMOCS"</div><div class='add'>+	 * registers depending on platform.</div><div class='add'>+	 *</div><div class='add'>+	 * These registers should be programmed before GuC initialization</div><div class='add'>+	 * since their values will affect some of the memory transactions</div><div class='add'>+	 * performed by the GuC.</div><div class='add'>+	 */</div><div class='add'>+	flags = get_mocs_settings(gt_to_xe(gt), &amp;table);</div><div class='add'>+	mocs_dbg(&amp;gt_to_xe(gt)-&gt;drm, "flag:0x%x\n", flags);</div><div class='add'>+</div><div class='add'>+	if (flags &amp; HAS_GLOBAL_MOCS)</div><div class='add'>+		__init_mocs_table(gt, &amp;table);</div><div class='add'>+	if (flags &amp; HAS_LNCF_MOCS)</div><div class='add'>+		init_l3cc_table(gt, &amp;table);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_mocs.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h<br/>new file mode 100644<br/>index 000000000000..053754c5a94e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_mocs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_mocs.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MOCS_H_</div><div class='add'>+#define _XE_MOCS_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+void xe_mocs_init_early(struct xe_gt *gt);</div><div class='add'>+void xe_mocs_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c<br/>new file mode 100644<br/>index 000000000000..110b69864656<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_module.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_module.c</a></div><div class='hunk'>@@ -0,0 +1,101 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_drv.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+</div><div class='add'>+struct xe_modparam xe_modparam = {</div><div class='add'>+	.enable_display = true,</div><div class='add'>+	.guc_log_level = 5,</div><div class='add'>+	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,</div><div class='add'>+	/* the rest are 0 by default */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_param_named_unsafe(force_execlist, xe_modparam.force_execlist, bool, 0444);</div><div class='add'>+MODULE_PARM_DESC(force_execlist, "Force Execlist submission");</div><div class='add'>+</div><div class='add'>+module_param_named(enable_display, xe_modparam.enable_display, bool, 0444);</div><div class='add'>+MODULE_PARM_DESC(enable_display, "Enable display");</div><div class='add'>+</div><div class='add'>+module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size, uint, 0600);</div><div class='add'>+MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size(in MiB)");</div><div class='add'>+</div><div class='add'>+module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);</div><div class='add'>+MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");</div><div class='add'>+</div><div class='add'>+module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);</div><div class='add'>+MODULE_PARM_DESC(guc_firmware_path,</div><div class='add'>+		 "GuC firmware path to use instead of the default one");</div><div class='add'>+</div><div class='add'>+module_param_named_unsafe(huc_firmware_path, xe_modparam.huc_firmware_path, charp, 0400);</div><div class='add'>+MODULE_PARM_DESC(huc_firmware_path,</div><div class='add'>+		 "HuC firmware path to use instead of the default one - empty string disables");</div><div class='add'>+</div><div class='add'>+module_param_named_unsafe(gsc_firmware_path, xe_modparam.gsc_firmware_path, charp, 0400);</div><div class='add'>+MODULE_PARM_DESC(gsc_firmware_path,</div><div class='add'>+		 "GSC firmware path to use instead of the default one - empty string disables");</div><div class='add'>+</div><div class='add'>+module_param_named_unsafe(force_probe, xe_modparam.force_probe, charp, 0400);</div><div class='add'>+MODULE_PARM_DESC(force_probe,</div><div class='add'>+		 "Force probe options for specified devices. See CONFIG_DRM_XE_FORCE_PROBE for details.");</div><div class='add'>+</div><div class='add'>+struct init_funcs {</div><div class='add'>+	int (*init)(void);</div><div class='add'>+	void (*exit)(void);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct init_funcs init_funcs[] = {</div><div class='add'>+	{</div><div class='add'>+		.init = xe_hw_fence_module_init,</div><div class='add'>+		.exit = xe_hw_fence_module_exit,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.init = xe_sched_job_module_init,</div><div class='add'>+		.exit = xe_sched_job_module_exit,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.init = xe_register_pci_driver,</div><div class='add'>+		.exit = xe_unregister_pci_driver,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init xe_init(void)</div><div class='add'>+{</div><div class='add'>+	int err, i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(init_funcs); i++) {</div><div class='add'>+		err = init_funcs[i].init();</div><div class='add'>+		if (err) {</div><div class='add'>+			while (i--)</div><div class='add'>+				init_funcs[i].exit();</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit xe_exit(void)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = ARRAY_SIZE(init_funcs) - 1; i &gt;= 0; i--)</div><div class='add'>+		init_funcs[i].exit();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+module_init(xe_init);</div><div class='add'>+module_exit(xe_exit);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Intel Corporation");</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION(DRIVER_DESC);</div><div class='add'>+MODULE_LICENSE("GPL and additional rights");</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h<br/>new file mode 100644<br/>index 000000000000..88ef0e8b2bfd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_module.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_module.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_MODULE_H_</div><div class='add'>+#define _XE_MODULE_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/* Module modprobe variables */</div><div class='add'>+struct xe_modparam {</div><div class='add'>+	bool force_execlist;</div><div class='add'>+	bool enable_display;</div><div class='add'>+	u32 force_vram_bar_size;</div><div class='add'>+	int guc_log_level;</div><div class='add'>+	char *guc_firmware_path;</div><div class='add'>+	char *huc_firmware_path;</div><div class='add'>+	char *gsc_firmware_path;</div><div class='add'>+	char *force_probe;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern struct xe_modparam xe_modparam;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c<br/>new file mode 100644<br/>index 000000000000..1ff6bc79e7d4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pat.c</a></div><div class='hunk'>@@ -0,0 +1,459 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_pat.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+</div><div class='add'>+#define _PAT_ATS				0x47fc</div><div class='add'>+#define _PAT_INDEX(index)			_PICK_EVEN_2RANGES(index, 8, \</div><div class='add'>+								   0x4800, 0x4804, \</div><div class='add'>+								   0x4848, 0x484c)</div><div class='add'>+#define _PAT_PTA				0x4820</div><div class='add'>+</div><div class='add'>+#define XE2_NO_PROMOTE				REG_BIT(10)</div><div class='add'>+#define XE2_COMP_EN				REG_BIT(9)</div><div class='add'>+#define XE2_L3_CLOS				REG_GENMASK(7, 6)</div><div class='add'>+#define XE2_L3_POLICY				REG_GENMASK(5, 4)</div><div class='add'>+#define XE2_L4_POLICY				REG_GENMASK(3, 2)</div><div class='add'>+#define XE2_COH_MODE				REG_GENMASK(1, 0)</div><div class='add'>+</div><div class='add'>+#define XELPG_L4_POLICY_MASK			REG_GENMASK(3, 2)</div><div class='add'>+#define XELPG_PAT_3_UC				REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 3)</div><div class='add'>+#define XELPG_PAT_1_WT				REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 1)</div><div class='add'>+#define XELPG_PAT_0_WB				REG_FIELD_PREP(XELPG_L4_POLICY_MASK, 0)</div><div class='add'>+#define XELPG_INDEX_COH_MODE_MASK		REG_GENMASK(1, 0)</div><div class='add'>+#define XELPG_3_COH_2W				REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 3)</div><div class='add'>+#define XELPG_2_COH_1W				REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 2)</div><div class='add'>+#define XELPG_0_COH_NON				REG_FIELD_PREP(XELPG_INDEX_COH_MODE_MASK, 0)</div><div class='add'>+</div><div class='add'>+#define XEHPC_CLOS_LEVEL_MASK			REG_GENMASK(3, 2)</div><div class='add'>+#define XEHPC_PAT_CLOS(x)			REG_FIELD_PREP(XEHPC_CLOS_LEVEL_MASK, x)</div><div class='add'>+</div><div class='add'>+#define XELP_MEM_TYPE_MASK			REG_GENMASK(1, 0)</div><div class='add'>+#define XELP_PAT_WB				REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 3)</div><div class='add'>+#define XELP_PAT_WT				REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 2)</div><div class='add'>+#define XELP_PAT_WC				REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 1)</div><div class='add'>+#define XELP_PAT_UC				REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0)</div><div class='add'>+</div><div class='add'>+static const char *XELP_MEM_TYPE_STR_MAP[] = { "UC", "WC", "WT", "WB" };</div><div class='add'>+</div><div class='add'>+struct xe_pat_ops {</div><div class='add'>+	void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+				 int n_entries);</div><div class='add'>+	void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+			      int n_entries);</div><div class='add'>+	void (*dump)(struct xe_gt *gt, struct drm_printer *p);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_table_entry xelp_pat_table[] = {</div><div class='add'>+	[0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+	[1] = { XELP_PAT_WC, XE_COH_NONE },</div><div class='add'>+	[2] = { XELP_PAT_WT, XE_COH_NONE },</div><div class='add'>+	[3] = { XELP_PAT_UC, XE_COH_NONE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_table_entry xehpc_pat_table[] = {</div><div class='add'>+	[0] = { XELP_PAT_UC, XE_COH_NONE },</div><div class='add'>+	[1] = { XELP_PAT_WC, XE_COH_NONE },</div><div class='add'>+	[2] = { XELP_PAT_WT, XE_COH_NONE },</div><div class='add'>+	[3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+	[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },</div><div class='add'>+	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+	[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },</div><div class='add'>+	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_table_entry xelpg_pat_table[] = {</div><div class='add'>+	[0] = { XELPG_PAT_0_WB, XE_COH_NONE },</div><div class='add'>+	[1] = { XELPG_PAT_1_WT, XE_COH_NONE },</div><div class='add'>+	[2] = { XELPG_PAT_3_UC, XE_COH_NONE },</div><div class='add'>+	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The Xe2 table is getting large/complicated so it's easier to review if</div><div class='add'>+ * provided in a form that exactly matches the bspec's formatting.  The meaning</div><div class='add'>+ * of the fields here are:</div><div class='add'>+ *   - no_promote:  0=promotable, 1=no promote</div><div class='add'>+ *   - comp_en:     0=disable, 1=enable</div><div class='add'>+ *   - l3clos:      L3 class of service (0-3)</div><div class='add'>+ *   - l3_policy:   0=WB, 1=XD ("WB - Transient Display"), 3=UC</div><div class='add'>+ *   - l4_policy:   0=WB, 1=WT, 3=UC</div><div class='add'>+ *   - coh_mode:    0=no snoop, 2=1-way coherent, 3=2-way coherent</div><div class='add'>+ *</div><div class='add'>+ * Reserved entries should be programmed with the maximum caching, minimum</div><div class='add'>+ * coherency (which matches an all-0's encoding), so we can just omit them</div><div class='add'>+ * in the table.</div><div class='add'>+ */</div><div class='add'>+#define XE2_PAT(no_promote, comp_en, l3clos, l3_policy, l4_policy, __coh_mode) \</div><div class='add'>+	{ \</div><div class='add'>+		.value = (no_promote ? XE2_NO_PROMOTE : 0) | \</div><div class='add'>+			(comp_en ? XE2_COMP_EN : 0) | \</div><div class='add'>+			REG_FIELD_PREP(XE2_L3_CLOS, l3clos) | \</div><div class='add'>+			REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \</div><div class='add'>+			REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \</div><div class='add'>+			REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \</div><div class='add'>+		.coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_table_entry xe2_pat_table[] = {</div><div class='add'>+	[ 0] = XE2_PAT( 0, 0, 0, 0, 3, 0 ),</div><div class='add'>+	[ 1] = XE2_PAT( 0, 0, 0, 0, 3, 2 ),</div><div class='add'>+	[ 2] = XE2_PAT( 0, 0, 0, 0, 3, 3 ),</div><div class='add'>+	[ 3] = XE2_PAT( 0, 0, 0, 3, 3, 0 ),</div><div class='add'>+	[ 4] = XE2_PAT( 0, 0, 0, 3, 0, 2 ),</div><div class='add'>+	[ 5] = XE2_PAT( 0, 0, 0, 3, 3, 2 ),</div><div class='add'>+	[ 6] = XE2_PAT( 1, 0, 0, 1, 3, 0 ),</div><div class='add'>+	[ 7] = XE2_PAT( 0, 0, 0, 3, 0, 3 ),</div><div class='add'>+	[ 8] = XE2_PAT( 0, 0, 0, 3, 0, 0 ),</div><div class='add'>+	[ 9] = XE2_PAT( 0, 1, 0, 0, 3, 0 ),</div><div class='add'>+	[10] = XE2_PAT( 0, 1, 0, 3, 0, 0 ),</div><div class='add'>+	[11] = XE2_PAT( 1, 1, 0, 1, 3, 0 ),</div><div class='add'>+	[12] = XE2_PAT( 0, 1, 0, 3, 3, 0 ),</div><div class='add'>+	[13] = XE2_PAT( 0, 0, 0, 0, 0, 0 ),</div><div class='add'>+	[14] = XE2_PAT( 0, 1, 0, 0, 0, 0 ),</div><div class='add'>+	[15] = XE2_PAT( 1, 1, 0, 1, 1, 0 ),</div><div class='add'>+	/* 16..19 are reserved; leave set to all 0's */</div><div class='add'>+	[20] = XE2_PAT( 0, 0, 1, 0, 3, 0 ),</div><div class='add'>+	[21] = XE2_PAT( 0, 1, 1, 0, 3, 0 ),</div><div class='add'>+	[22] = XE2_PAT( 0, 0, 1, 0, 3, 2 ),</div><div class='add'>+	[23] = XE2_PAT( 0, 0, 1, 0, 3, 3 ),</div><div class='add'>+	[24] = XE2_PAT( 0, 0, 2, 0, 3, 0 ),</div><div class='add'>+	[25] = XE2_PAT( 0, 1, 2, 0, 3, 0 ),</div><div class='add'>+	[26] = XE2_PAT( 0, 0, 2, 0, 3, 2 ),</div><div class='add'>+	[27] = XE2_PAT( 0, 0, 2, 0, 3, 3 ),</div><div class='add'>+	[28] = XE2_PAT( 0, 0, 3, 0, 3, 0 ),</div><div class='add'>+	[29] = XE2_PAT( 0, 1, 3, 0, 3, 0 ),</div><div class='add'>+	[30] = XE2_PAT( 0, 0, 3, 0, 3, 2 ),</div><div class='add'>+	[31] = XE2_PAT( 0, 0, 3, 0, 3, 3 ),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Special PAT values programmed outside the main table */</div><div class='add'>+static const struct xe_pat_table_entry xe2_pat_ats = XE2_PAT( 0, 0, 0, 0, 3, 3 );</div><div class='add'>+</div><div class='add'>+u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	WARN_ON(pat_index &gt;= xe-&gt;pat.n_entries);</div><div class='add'>+	return xe-&gt;pat.table[pat_index].coh_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+			int n_entries)</div><div class='add'>+{</div><div class='add'>+	for (int i = 0; i &lt; n_entries; i++) {</div><div class='add'>+		struct xe_reg reg = XE_REG(_PAT_INDEX(i));</div><div class='add'>+</div><div class='add'>+		xe_mmio_write32(gt, reg, table[i].value);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+			    int n_entries)</div><div class='add'>+{</div><div class='add'>+	for (int i = 0; i &lt; n_entries; i++) {</div><div class='add'>+		struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));</div><div class='add'>+</div><div class='add'>+		xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xelp_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i, err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fw;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "PAT table:\n");</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xe-&gt;pat.n_entries; i++) {</div><div class='add'>+		u32 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));</div><div class='add'>+		u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,</div><div class='add'>+			   XELP_MEM_TYPE_STR_MAP[mem_type], pat);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_fw:</div><div class='add'>+	xe_assert(xe, !err);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_ops xelp_pat_ops = {</div><div class='add'>+	.program_graphics = program_pat,</div><div class='add'>+	.dump = xelp_dump,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xehp_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i, err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fw;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "PAT table:\n");</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xe-&gt;pat.n_entries; i++) {</div><div class='add'>+		u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));</div><div class='add'>+		u8 mem_type;</div><div class='add'>+</div><div class='add'>+		mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,</div><div class='add'>+			   XELP_MEM_TYPE_STR_MAP[mem_type], pat);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_fw:</div><div class='add'>+	xe_assert(xe, !err);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_ops xehp_pat_ops = {</div><div class='add'>+	.program_graphics = program_pat_mcr,</div><div class='add'>+	.dump = xehp_dump,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xehpc_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i, err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fw;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "PAT table:\n");</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xe-&gt;pat.n_entries; i++) {</div><div class='add'>+		u32 pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i,</div><div class='add'>+			   REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat),</div><div class='add'>+			   REG_FIELD_GET(XEHPC_CLOS_LEVEL_MASK, pat), pat);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_fw:</div><div class='add'>+	xe_assert(xe, !err);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_ops xehpc_pat_ops = {</div><div class='add'>+	.program_graphics = program_pat_mcr,</div><div class='add'>+	.dump = xehpc_dump,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xelpg_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i, err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fw;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "PAT table:\n");</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xe-&gt;pat.n_entries; i++) {</div><div class='add'>+		u32 pat;</div><div class='add'>+</div><div class='add'>+		if (xe_gt_is_media_type(gt))</div><div class='add'>+			pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));</div><div class='add'>+		else</div><div class='add'>+			pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "PAT[%2d] = [ %u, %u ] (%#8x)\n", i,</div><div class='add'>+			   REG_FIELD_GET(XELPG_L4_POLICY_MASK, pat),</div><div class='add'>+			   REG_FIELD_GET(XELPG_INDEX_COH_MODE_MASK, pat), pat);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_fw:</div><div class='add'>+	xe_assert(xe, !err);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * SAMedia register offsets are adjusted by the write methods and they target</div><div class='add'>+ * registers that are not MCR, while for normal GT they are MCR</div><div class='add'>+ */</div><div class='add'>+static const struct xe_pat_ops xelpg_pat_ops = {</div><div class='add'>+	.program_graphics = program_pat,</div><div class='add'>+	.program_media = program_pat_mcr,</div><div class='add'>+	.dump = xelpg_dump,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void xe2lpg_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+			       int n_entries)</div><div class='add'>+{</div><div class='add'>+	program_pat_mcr(gt, table, n_entries);</div><div class='add'>+	xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe2_pat_ats.value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],</div><div class='add'>+			       int n_entries)</div><div class='add'>+{</div><div class='add'>+	program_pat(gt, table, n_entries);</div><div class='add'>+	xe_mmio_write32(gt, XE_REG(_PAT_ATS), xe2_pat_ats.value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	int i, err;</div><div class='add'>+	u32 pat;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fw;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "PAT table:\n");</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; xe-&gt;pat.n_entries; i++) {</div><div class='add'>+		if (xe_gt_is_media_type(gt))</div><div class='add'>+			pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));</div><div class='add'>+		else</div><div class='add'>+			pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));</div><div class='add'>+</div><div class='add'>+		drm_printf(p, "PAT[%2d] = [ %u, %u, %u, %u, %u, %u ]  (%#8x)\n", i,</div><div class='add'>+			   !!(pat &amp; XE2_NO_PROMOTE),</div><div class='add'>+			   !!(pat &amp; XE2_COMP_EN),</div><div class='add'>+			   REG_FIELD_GET(XE2_L3_CLOS, pat),</div><div class='add'>+			   REG_FIELD_GET(XE2_L3_POLICY, pat),</div><div class='add'>+			   REG_FIELD_GET(XE2_L4_POLICY, pat),</div><div class='add'>+			   REG_FIELD_GET(XE2_COH_MODE, pat),</div><div class='add'>+			   pat);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Also print PTA_MODE, which describes how the hardware accesses</div><div class='add'>+	 * PPGTT entries.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		pat = xe_mmio_read32(gt, XE_REG(_PAT_PTA));</div><div class='add'>+	else</div><div class='add'>+		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "Page Table Access:\n");</div><div class='add'>+	drm_printf(p, "PTA_MODE= [ %u, %u, %u, %u, %u, %u ]  (%#8x)\n",</div><div class='add'>+		   !!(pat &amp; XE2_NO_PROMOTE),</div><div class='add'>+		   !!(pat &amp; XE2_COMP_EN),</div><div class='add'>+		   REG_FIELD_GET(XE2_L3_CLOS, pat),</div><div class='add'>+		   REG_FIELD_GET(XE2_L3_POLICY, pat),</div><div class='add'>+		   REG_FIELD_GET(XE2_L4_POLICY, pat),</div><div class='add'>+		   REG_FIELD_GET(XE2_COH_MODE, pat),</div><div class='add'>+		   pat);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+err_fw:</div><div class='add'>+	xe_assert(xe, !err);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pat_ops xe2_pat_ops = {</div><div class='add'>+	.program_graphics = xe2lpg_program_pat,</div><div class='add'>+	.program_media = xe2lpm_program_pat,</div><div class='add'>+	.dump = xe2_dump,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_pat_init_early(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	if (GRAPHICS_VER(xe) == 20) {</div><div class='add'>+		xe-&gt;pat.ops = &amp;xe2_pat_ops;</div><div class='add'>+		xe-&gt;pat.table = xe2_pat_table;</div><div class='add'>+		xe-&gt;pat.n_entries = ARRAY_SIZE(xe2_pat_table);</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE] = 3;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WT] = 15;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WB] = 2;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE_COMPRESSION] = 12; /*Applicable on xe2 and beyond */</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_METEORLAKE) {</div><div class='add'>+		xe-&gt;pat.ops = &amp;xelpg_pat_ops;</div><div class='add'>+		xe-&gt;pat.table = xelpg_pat_table;</div><div class='add'>+		xe-&gt;pat.n_entries = ARRAY_SIZE(xelpg_pat_table);</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE] = 2;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WT] = 1;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WB] = 3;</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_PVC) {</div><div class='add'>+		xe-&gt;pat.ops = &amp;xehpc_pat_ops;</div><div class='add'>+		xe-&gt;pat.table = xehpc_pat_table;</div><div class='add'>+		xe-&gt;pat.n_entries = ARRAY_SIZE(xehpc_pat_table);</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE] = 0;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WT] = 2;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WB] = 3;</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_DG2) {</div><div class='add'>+		/*</div><div class='add'>+		 * Table is the same as previous platforms, but programming</div><div class='add'>+		 * method has changed.</div><div class='add'>+		 */</div><div class='add'>+		xe-&gt;pat.ops = &amp;xehp_pat_ops;</div><div class='add'>+		xe-&gt;pat.table = xelp_pat_table;</div><div class='add'>+		xe-&gt;pat.n_entries = ARRAY_SIZE(xelp_pat_table);</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE] = 3;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WT] = 2;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WB] = 0;</div><div class='add'>+	} else if (GRAPHICS_VERx100(xe) &lt;= 1210) {</div><div class='add'>+		WARN_ON_ONCE(!IS_DGFX(xe) &amp;&amp; !xe-&gt;info.has_llc);</div><div class='add'>+		xe-&gt;pat.ops = &amp;xelp_pat_ops;</div><div class='add'>+		xe-&gt;pat.table = xelp_pat_table;</div><div class='add'>+		xe-&gt;pat.n_entries = ARRAY_SIZE(xelp_pat_table);</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_NONE] = 3;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WT] = 2;</div><div class='add'>+		xe-&gt;pat.idx[XE_CACHE_WB] = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * Going forward we expect to need new PAT settings for most</div><div class='add'>+		 * new platforms; failure to provide a new table can easily</div><div class='add'>+		 * lead to subtle, hard-to-debug problems.  If none of the</div><div class='add'>+		 * conditions above match the platform we're running on we'll</div><div class='add'>+		 * raise an error rather than trying to silently inherit the</div><div class='add'>+		 * most recent platform's behavior.</div><div class='add'>+		 */</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Missing PAT table for platform with graphics version %d.%02d!\n",</div><div class='add'>+			GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pat_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;pat.ops)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (xe_gt_is_media_type(gt))</div><div class='add'>+		xe-&gt;pat.ops-&gt;program_media(gt, xe-&gt;pat.table, xe-&gt;pat.n_entries);</div><div class='add'>+	else</div><div class='add'>+		xe-&gt;pat.ops-&gt;program_graphics(gt, xe-&gt;pat.table, xe-&gt;pat.n_entries);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;pat.ops-&gt;dump)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe-&gt;pat.ops-&gt;dump(gt, p);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h<br/>new file mode 100644<br/>index 000000000000..fa0dfbe525cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pat.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pat.h</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PAT_H_</div><div class='add'>+#define _XE_PAT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_pat_table_entry - The pat_index encoding and other meta information.</div><div class='add'>+ */</div><div class='add'>+struct xe_pat_table_entry {</div><div class='add'>+	/**</div><div class='add'>+	 * @value: The platform specific value encoding the various memory</div><div class='add'>+	 * attributes (this maps to some fixed pat_index). So things like</div><div class='add'>+	 * caching, coherency, compression etc can be encoded here.</div><div class='add'>+	 */</div><div class='add'>+	u32 value;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @coh_mode: The GPU coherency mode that @value maps to.</div><div class='add'>+	 */</div><div class='add'>+#define XE_COH_NONE          1</div><div class='add'>+#define XE_COH_AT_LEAST_1WAY 2</div><div class='add'>+	u16 coh_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pat_init_early - SW initialization, setting up data based on device</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ */</div><div class='add'>+void xe_pat_init_early(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pat_init - Program HW PAT table</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ */</div><div class='add'>+void xe_pat_init(struct xe_gt *gt);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pat_dump - Dump PAT table</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @p: Printer to dump info to</div><div class='add'>+ */</div><div class='add'>+void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pat_index_get_coh_mode - Extract the coherency mode for the given</div><div class='add'>+ * pat_index.</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ * @pat_index: The pat_index to query</div><div class='add'>+ */</div><div class='add'>+u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c<br/>new file mode 100644<br/>index 000000000000..dcc5ded1558e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci.c</a></div><div class='hunk'>@@ -0,0 +1,951 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_pci.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/static_stub.h&gt;</div><div class='add'>+#include &lt;linux/device/driver.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_color_mgmt.h&gt;</div><div class='add'>+#include &lt;drm/drm_drv.h&gt;</div><div class='add'>+#include &lt;drm/xe_pciids.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_display.h"</div><div class='add'>+#include "xe_drv.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+#include "xe_pci_types.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_sriov.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+</div><div class='add'>+enum toggle_d3cold {</div><div class='add'>+	D3COLD_DISABLE,</div><div class='add'>+	D3COLD_ENABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_subplatform_desc {</div><div class='add'>+	enum xe_subplatform subplatform;</div><div class='add'>+	const char *name;</div><div class='add'>+	const u16 *pciidlist;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_gt_desc {</div><div class='add'>+	enum xe_gt_type type;</div><div class='add'>+	u32 mmio_adj_limit;</div><div class='add'>+	u32 mmio_adj_offset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_device_desc {</div><div class='add'>+	/* Should only ever be set for platforms without GMD_ID */</div><div class='add'>+	const struct xe_graphics_desc *graphics;</div><div class='add'>+	/* Should only ever be set for platforms without GMD_ID */</div><div class='add'>+	const struct xe_media_desc *media;</div><div class='add'>+</div><div class='add'>+	const char *platform_name;</div><div class='add'>+	const struct xe_subplatform_desc *subplatforms;</div><div class='add'>+</div><div class='add'>+	enum xe_platform platform;</div><div class='add'>+</div><div class='add'>+	u8 require_force_probe:1;</div><div class='add'>+	u8 is_dgfx:1;</div><div class='add'>+</div><div class='add'>+	u8 has_display:1;</div><div class='add'>+	u8 has_heci_gscfi:1;</div><div class='add'>+	u8 has_llc:1;</div><div class='add'>+	u8 has_mmio_ext:1;</div><div class='add'>+	u8 has_sriov:1;</div><div class='add'>+	u8 skip_guc_pc:1;</div><div class='add'>+	u8 skip_mtcfg:1;</div><div class='add'>+	u8 skip_pcode:1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+__diag_push();</div><div class='add'>+__diag_ignore_all("-Woverride-init", "Allow field overrides in table");</div><div class='add'>+</div><div class='add'>+#define PLATFORM(x)		\</div><div class='add'>+	.platform = (x),	\</div><div class='add'>+	.platform_name = #x</div><div class='add'>+</div><div class='add'>+#define NOP(x)	x</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xelp = {</div><div class='add'>+	.name = "Xe_LP",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 0,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),</div><div class='add'>+</div><div class='add'>+	.dma_mask_size = 39,</div><div class='add'>+	.va_bits = 48,</div><div class='add'>+	.vm_max_level = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xelpp = {</div><div class='add'>+	.name = "Xe_LP+",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 10,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),</div><div class='add'>+</div><div class='add'>+	.dma_mask_size = 39,</div><div class='add'>+	.va_bits = 48,</div><div class='add'>+	.vm_max_level = 3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE_HP_FEATURES \</div><div class='add'>+	.has_range_tlb_invalidation = true, \</div><div class='add'>+	.has_flat_ccs = true, \</div><div class='add'>+	.dma_mask_size = 46, \</div><div class='add'>+	.va_bits = 48, \</div><div class='add'>+	.vm_max_level = 3</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xehpg = {</div><div class='add'>+	.name = "Xe_HPG",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 55,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |</div><div class='add'>+		BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |</div><div class='add'>+		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),</div><div class='add'>+</div><div class='add'>+	XE_HP_FEATURES,</div><div class='add'>+	.vram_flags = XE_VRAM_FLAGS_NEED64K,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xehpc = {</div><div class='add'>+	.name = "Xe_HPC",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 60,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS8) |</div><div class='add'>+		BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |</div><div class='add'>+		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),</div><div class='add'>+</div><div class='add'>+	XE_HP_FEATURES,</div><div class='add'>+	.dma_mask_size = 52,</div><div class='add'>+	.max_remote_tiles = 1,</div><div class='add'>+	.va_bits = 57,</div><div class='add'>+	.vm_max_level = 4,</div><div class='add'>+	.vram_flags = XE_VRAM_FLAGS_NEED64K,</div><div class='add'>+</div><div class='add'>+	.has_asid = 1,</div><div class='add'>+	.has_flat_ccs = 0,</div><div class='add'>+	.has_usm = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xelpg = {</div><div class='add'>+	.name = "Xe_LPG",</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |</div><div class='add'>+		BIT(XE_HW_ENGINE_CCS0),</div><div class='add'>+</div><div class='add'>+	XE_HP_FEATURES,</div><div class='add'>+	.has_flat_ccs = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE2_GFX_FEATURES \</div><div class='add'>+	.dma_mask_size = 46, \</div><div class='add'>+	.has_asid = 1, \</div><div class='add'>+	.has_flat_ccs = 1, \</div><div class='add'>+	.has_range_tlb_invalidation = 1, \</div><div class='add'>+	.has_usm = 0 /* FIXME: implementation missing */, \</div><div class='add'>+	.va_bits = 48, \</div><div class='add'>+	.vm_max_level = 4, \</div><div class='add'>+	.hw_engine_mask = \</div><div class='add'>+		BIT(XE_HW_ENGINE_RCS0) | \</div><div class='add'>+		BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \</div><div class='add'>+		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)</div><div class='add'>+</div><div class='add'>+static const struct xe_graphics_desc graphics_xe2 = {</div><div class='add'>+	.name = "Xe2_LPG",</div><div class='add'>+</div><div class='add'>+	XE2_GFX_FEATURES,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_media_desc media_xem = {</div><div class='add'>+	.name = "Xe_M",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 0,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |</div><div class='add'>+		BIT(XE_HW_ENGINE_VECS0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_media_desc media_xehpm = {</div><div class='add'>+	.name = "Xe_HPM",</div><div class='add'>+	.ver = 12,</div><div class='add'>+	.rel = 55,</div><div class='add'>+</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |</div><div class='add'>+		BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VECS1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_media_desc media_xelpmp = {</div><div class='add'>+	.name = "Xe_LPM+",</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |</div><div class='add'>+		BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_GSCCS0)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_media_desc media_xe2 = {</div><div class='add'>+	.name = "Xe2_LPM",</div><div class='add'>+	.hw_engine_mask =</div><div class='add'>+		BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0), /* TODO: GSC0 */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc tgl_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	PLATFORM(XE_TIGERLAKE),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_llc = true,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc rkl_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	PLATFORM(XE_ROCKETLAKE),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_llc = true,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc adl_s_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	PLATFORM(XE_ALDERLAKE_S),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_llc = true,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+	.subplatforms = (const struct xe_subplatform_desc[]) {</div><div class='add'>+		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },</div><div class='add'>+		{},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc adl_p_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	PLATFORM(XE_ALDERLAKE_P),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_llc = true,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+	.subplatforms = (const struct xe_subplatform_desc[]) {</div><div class='add'>+		{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },</div><div class='add'>+		{},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc adl_n_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	PLATFORM(XE_ALDERLAKE_N),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_llc = true,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define DGFX_FEATURES \</div><div class='add'>+	.is_dgfx = 1</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc dg1_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xelpp,</div><div class='add'>+	.media = &amp;media_xem,</div><div class='add'>+	DGFX_FEATURES,</div><div class='add'>+	PLATFORM(XE_DG1),</div><div class='add'>+	.has_display = true,</div><div class='add'>+	.has_heci_gscfi = 1,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };</div><div class='add'>+static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 };</div><div class='add'>+static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };</div><div class='add'>+</div><div class='add'>+#define DG2_FEATURES \</div><div class='add'>+	DGFX_FEATURES, \</div><div class='add'>+	PLATFORM(XE_DG2), \</div><div class='add'>+	.has_heci_gscfi = 1, \</div><div class='add'>+	.subplatforms = (const struct xe_subplatform_desc[]) { \</div><div class='add'>+		{ XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \</div><div class='add'>+		{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \</div><div class='add'>+		{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \</div><div class='add'>+		{ } \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc ats_m_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xehpg,</div><div class='add'>+	.media = &amp;media_xehpm,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+</div><div class='add'>+	DG2_FEATURES,</div><div class='add'>+	.has_display = false,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc dg2_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xehpg,</div><div class='add'>+	.media = &amp;media_xehpm,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+</div><div class='add'>+	DG2_FEATURES,</div><div class='add'>+	.has_display = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const __maybe_unused struct xe_device_desc pvc_desc = {</div><div class='add'>+	.graphics = &amp;graphics_xehpc,</div><div class='add'>+	DGFX_FEATURES,</div><div class='add'>+	PLATFORM(XE_PVC),</div><div class='add'>+	.has_display = false,</div><div class='add'>+	.has_heci_gscfi = 1,</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc mtl_desc = {</div><div class='add'>+	/* .graphics and .media determined via GMD_ID */</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+	PLATFORM(XE_METEORLAKE),</div><div class='add'>+	.has_display = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_device_desc lnl_desc = {</div><div class='add'>+	PLATFORM(XE_LUNARLAKE),</div><div class='add'>+	.require_force_probe = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#undef PLATFORM</div><div class='add'>+__diag_pop();</div><div class='add'>+</div><div class='add'>+/* Map of GMD_ID values to graphics IP */</div><div class='add'>+static struct gmdid_map graphics_ip_map[] = {</div><div class='add'>+	{ 1270, &amp;graphics_xelpg },</div><div class='add'>+	{ 1271, &amp;graphics_xelpg },</div><div class='add'>+	{ 2004, &amp;graphics_xe2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Map of GMD_ID values to media IP */</div><div class='add'>+static struct gmdid_map media_ip_map[] = {</div><div class='add'>+	{ 1300, &amp;media_xelpmp },</div><div class='add'>+	{ 2000, &amp;media_xe2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define INTEL_VGA_DEVICE(id, info) {			\</div><div class='add'>+	PCI_DEVICE(PCI_VENDOR_ID_INTEL, id),		\</div><div class='add'>+	PCI_BASE_CLASS_DISPLAY &lt;&lt; 16, 0xff &lt;&lt; 16,	\</div><div class='add'>+	(unsigned long) info }</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Make sure any device matches here are from most specific to most</div><div class='add'>+ * general.  For example, since the Quanta match is based on the subsystem</div><div class='add'>+ * and subvendor IDs, we need it to come before the more general IVB</div><div class='add'>+ * PCI ID matches, otherwise we'll use the wrong info struct above.</div><div class='add'>+ */</div><div class='add'>+static const struct pci_device_id pciidlist[] = {</div><div class='add'>+	XE_TGL_IDS(INTEL_VGA_DEVICE, &amp;tgl_desc),</div><div class='add'>+	XE_RKL_IDS(INTEL_VGA_DEVICE, &amp;rkl_desc),</div><div class='add'>+	XE_ADLS_IDS(INTEL_VGA_DEVICE, &amp;adl_s_desc),</div><div class='add'>+	XE_ADLP_IDS(INTEL_VGA_DEVICE, &amp;adl_p_desc),</div><div class='add'>+	XE_ADLN_IDS(INTEL_VGA_DEVICE, &amp;adl_n_desc),</div><div class='add'>+	XE_RPLP_IDS(INTEL_VGA_DEVICE, &amp;adl_p_desc),</div><div class='add'>+	XE_RPLS_IDS(INTEL_VGA_DEVICE, &amp;adl_s_desc),</div><div class='add'>+	XE_DG1_IDS(INTEL_VGA_DEVICE, &amp;dg1_desc),</div><div class='add'>+	XE_ATS_M_IDS(INTEL_VGA_DEVICE, &amp;ats_m_desc),</div><div class='add'>+	XE_DG2_IDS(INTEL_VGA_DEVICE, &amp;dg2_desc),</div><div class='add'>+	XE_MTL_IDS(INTEL_VGA_DEVICE, &amp;mtl_desc),</div><div class='add'>+	XE_LNL_IDS(INTEL_VGA_DEVICE, &amp;lnl_desc),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(pci, pciidlist);</div><div class='add'>+</div><div class='add'>+#undef INTEL_VGA_DEVICE</div><div class='add'>+</div><div class='add'>+/* is device_id present in comma separated list of ids */</div><div class='add'>+static bool device_id_in_list(u16 device_id, const char *devices, bool negative)</div><div class='add'>+{</div><div class='add'>+	char *s, *p, *tok;</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	if (!devices || !*devices)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* match everything */</div><div class='add'>+	if (negative &amp;&amp; strcmp(devices, "!*") == 0)</div><div class='add'>+		return true;</div><div class='add'>+	if (!negative &amp;&amp; strcmp(devices, "*") == 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	s = kstrdup(devices, GFP_KERNEL);</div><div class='add'>+	if (!s)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (p = s, ret = false; (tok = strsep(&amp;p, ",")) != NULL; ) {</div><div class='add'>+		u16 val;</div><div class='add'>+</div><div class='add'>+		if (negative &amp;&amp; tok[0] == '!')</div><div class='add'>+			tok++;</div><div class='add'>+		else if ((negative &amp;&amp; tok[0] != '!') ||</div><div class='add'>+			 (!negative &amp;&amp; tok[0] == '!'))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (kstrtou16(tok, 16, &amp;val) == 0 &amp;&amp; val == device_id) {</div><div class='add'>+			ret = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(s);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool id_forced(u16 device_id)</div><div class='add'>+{</div><div class='add'>+	return device_id_in_list(device_id, xe_modparam.force_probe, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool id_blocked(u16 device_id)</div><div class='add'>+{</div><div class='add'>+	return device_id_in_list(device_id, xe_modparam.force_probe, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_subplatform_desc *</div><div class='add'>+find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)</div><div class='add'>+{</div><div class='add'>+	const struct xe_subplatform_desc *sp;</div><div class='add'>+	const u16 *id;</div><div class='add'>+</div><div class='add'>+	for (sp = desc-&gt;subplatforms; sp &amp;&amp; sp-&gt;subplatform; sp++)</div><div class='add'>+		for (id = sp-&gt;pciidlist; *id; id++)</div><div class='add'>+			if (*id == xe-&gt;info.devid)</div><div class='add'>+				return sp;</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum xe_gmdid_type {</div><div class='add'>+	GMDID_GRAPHICS,</div><div class='add'>+	GMDID_MEDIA</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+	struct xe_reg gmdid_reg = GMD_ID;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);</div><div class='add'>+</div><div class='add'>+	if (type == GMDID_MEDIA)</div><div class='add'>+		gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;</div><div class='add'>+</div><div class='add'>+	val = xe_mmio_read32(gt, gmdid_reg);</div><div class='add'>+	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);</div><div class='add'>+	*revid = REG_FIELD_GET(GMD_ID_REVID, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Pre-GMD_ID platform: device descriptor already points to the appropriate</div><div class='add'>+ * graphics descriptor. Simply forward the description and calculate the version</div><div class='add'>+ * appropriately. "graphics" should be present in all such platforms, while</div><div class='add'>+ * media is optional.</div><div class='add'>+ */</div><div class='add'>+static void handle_pre_gmdid(struct xe_device *xe,</div><div class='add'>+			     const struct xe_graphics_desc *graphics,</div><div class='add'>+			     const struct xe_media_desc *media)</div><div class='add'>+{</div><div class='add'>+	xe-&gt;info.graphics_verx100 = graphics-&gt;ver * 100 + graphics-&gt;rel;</div><div class='add'>+</div><div class='add'>+	if (media)</div><div class='add'>+		xe-&gt;info.media_verx100 = media-&gt;ver * 100 + media-&gt;rel;</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * GMD_ID platform: read IP version from hardware and select graphics descriptor</div><div class='add'>+ * based on the result.</div><div class='add'>+ */</div><div class='add'>+static void handle_gmdid(struct xe_device *xe,</div><div class='add'>+			 const struct xe_graphics_desc **graphics,</div><div class='add'>+			 const struct xe_media_desc **media,</div><div class='add'>+			 u32 *graphics_revid,</div><div class='add'>+			 u32 *media_revid)</div><div class='add'>+{</div><div class='add'>+	u32 ver;</div><div class='add'>+</div><div class='add'>+	read_gmdid(xe, GMDID_GRAPHICS, &amp;ver, graphics_revid);</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(graphics_ip_map); i++) {</div><div class='add'>+		if (ver == graphics_ip_map[i].ver) {</div><div class='add'>+			xe-&gt;info.graphics_verx100 = ver;</div><div class='add'>+			*graphics = graphics_ip_map[i].ip;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.graphics_verx100) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Hardware reports unknown graphics version %u.%02u\n",</div><div class='add'>+			ver / 100, ver % 100);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	read_gmdid(xe, GMDID_MEDIA, &amp;ver, media_revid);</div><div class='add'>+</div><div class='add'>+	/* Media may legitimately be fused off / not present */</div><div class='add'>+	if (ver == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(media_ip_map); i++) {</div><div class='add'>+		if (ver == media_ip_map[i].ver) {</div><div class='add'>+			xe-&gt;info.media_verx100 = ver;</div><div class='add'>+			*media = media_ip_map[i].ip;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;info.media_verx100) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Hardware reports unknown media version %u.%02u\n",</div><div class='add'>+			ver / 100, ver % 100);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initialize device info content that only depends on static driver_data</div><div class='add'>+ * passed to the driver at probe time from PCI ID table.</div><div class='add'>+ */</div><div class='add'>+static int xe_info_init_early(struct xe_device *xe,</div><div class='add'>+			      const struct xe_device_desc *desc,</div><div class='add'>+			      const struct xe_subplatform_desc *subplatform_desc)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.platform = desc-&gt;platform;</div><div class='add'>+	xe-&gt;info.subplatform = subplatform_desc ?</div><div class='add'>+		subplatform_desc-&gt;subplatform : XE_SUBPLATFORM_NONE;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.is_dgfx = desc-&gt;is_dgfx;</div><div class='add'>+	xe-&gt;info.has_heci_gscfi = desc-&gt;has_heci_gscfi;</div><div class='add'>+	xe-&gt;info.has_llc = desc-&gt;has_llc;</div><div class='add'>+	xe-&gt;info.has_mmio_ext = desc-&gt;has_mmio_ext;</div><div class='add'>+	xe-&gt;info.has_sriov = desc-&gt;has_sriov;</div><div class='add'>+	xe-&gt;info.skip_guc_pc = desc-&gt;skip_guc_pc;</div><div class='add'>+	xe-&gt;info.skip_mtcfg = desc-&gt;skip_mtcfg;</div><div class='add'>+	xe-&gt;info.skip_pcode = desc-&gt;skip_pcode;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.enable_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &amp;&amp;</div><div class='add'>+				  xe_modparam.enable_display &amp;&amp;</div><div class='add'>+				  desc-&gt;has_display;</div><div class='add'>+</div><div class='add'>+	err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initialize device info content that does require knowledge about</div><div class='add'>+ * graphics / media IP version.</div><div class='add'>+ * Make sure that GT / tile structures allocated by the driver match the data</div><div class='add'>+ * present in device info.</div><div class='add'>+ */</div><div class='add'>+static int xe_info_init(struct xe_device *xe,</div><div class='add'>+			const struct xe_graphics_desc *graphics_desc,</div><div class='add'>+			const struct xe_media_desc *media_desc)</div><div class='add'>+{</div><div class='add'>+	u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If this platform supports GMD_ID, we'll detect the proper IP</div><div class='add'>+	 * descriptor to use from hardware registers. desc-&gt;graphics will only</div><div class='add'>+	 * ever be set at this point for platforms before GMD_ID. In that case</div><div class='add'>+	 * the IP descriptions and versions are simply derived from that.</div><div class='add'>+	 */</div><div class='add'>+	if (graphics_desc) {</div><div class='add'>+		handle_pre_gmdid(xe, graphics_desc, media_desc);</div><div class='add'>+		xe-&gt;info.step = xe_step_pre_gmdid_get(xe);</div><div class='add'>+	} else {</div><div class='add'>+		xe_assert(xe, !media_desc);</div><div class='add'>+		handle_gmdid(xe, &amp;graphics_desc, &amp;media_desc,</div><div class='add'>+			     &amp;graphics_gmdid_revid, &amp;media_gmdid_revid);</div><div class='add'>+		xe-&gt;info.step = xe_step_gmdid_get(xe,</div><div class='add'>+						  graphics_gmdid_revid,</div><div class='add'>+						  media_gmdid_revid);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we couldn't detect the graphics IP, that's considered a fatal</div><div class='add'>+	 * error and we should abort driver load.  Failing to detect media</div><div class='add'>+	 * IP is non-fatal; we'll just proceed without enabling media support.</div><div class='add'>+	 */</div><div class='add'>+	if (!graphics_desc)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.graphics_name = graphics_desc-&gt;name;</div><div class='add'>+	xe-&gt;info.media_name = media_desc ? media_desc-&gt;name : "none";</div><div class='add'>+	xe-&gt;info.tile_mmio_ext_size = graphics_desc-&gt;tile_mmio_ext_size;</div><div class='add'>+</div><div class='add'>+	xe-&gt;info.dma_mask_size = graphics_desc-&gt;dma_mask_size;</div><div class='add'>+	xe-&gt;info.vram_flags = graphics_desc-&gt;vram_flags;</div><div class='add'>+	xe-&gt;info.va_bits = graphics_desc-&gt;va_bits;</div><div class='add'>+	xe-&gt;info.vm_max_level = graphics_desc-&gt;vm_max_level;</div><div class='add'>+	xe-&gt;info.has_asid = graphics_desc-&gt;has_asid;</div><div class='add'>+	xe-&gt;info.has_flat_ccs = graphics_desc-&gt;has_flat_ccs;</div><div class='add'>+	xe-&gt;info.has_range_tlb_invalidation = graphics_desc-&gt;has_range_tlb_invalidation;</div><div class='add'>+	xe-&gt;info.has_usm = graphics_desc-&gt;has_usm;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All platforms have at least one primary GT.  Any platform with media</div><div class='add'>+	 * version 13 or higher has an additional dedicated media GT.  And</div><div class='add'>+	 * depending on the graphics IP there may be additional "remote tiles."</div><div class='add'>+	 * All of these together determine the overall GT count.</div><div class='add'>+	 *</div><div class='add'>+	 * FIXME: 'tile_count' here is misnamed since the rest of the driver</div><div class='add'>+	 * treats it as the number of GTs rather than just the number of tiles.</div><div class='add'>+	 */</div><div class='add'>+	xe-&gt;info.tile_count = 1 + graphics_desc-&gt;max_remote_tiles;</div><div class='add'>+</div><div class='add'>+	for_each_remote_tile(tile, xe, id) {</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		err = xe_tile_init_early(tile, xe, id);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		gt = tile-&gt;primary_gt;</div><div class='add'>+		gt-&gt;info.id = xe-&gt;info.gt_count++;</div><div class='add'>+		gt-&gt;info.type = XE_GT_TYPE_MAIN;</div><div class='add'>+		gt-&gt;info.__engine_mask = graphics_desc-&gt;hw_engine_mask;</div><div class='add'>+		if (MEDIA_VER(xe) &lt; 13 &amp;&amp; media_desc)</div><div class='add'>+			gt-&gt;info.__engine_mask |= media_desc-&gt;hw_engine_mask;</div><div class='add'>+</div><div class='add'>+		if (MEDIA_VER(xe) &lt; 13 || !media_desc)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Allocate and setup media GT for platforms with standalone</div><div class='add'>+		 * media.</div><div class='add'>+		 */</div><div class='add'>+		tile-&gt;media_gt = xe_gt_alloc(tile);</div><div class='add'>+		if (IS_ERR(tile-&gt;media_gt))</div><div class='add'>+			return PTR_ERR(tile-&gt;media_gt);</div><div class='add'>+</div><div class='add'>+		gt = tile-&gt;media_gt;</div><div class='add'>+		gt-&gt;info.type = XE_GT_TYPE_MEDIA;</div><div class='add'>+		gt-&gt;info.__engine_mask = media_desc-&gt;hw_engine_mask;</div><div class='add'>+		gt-&gt;mmio.adj_offset = MEDIA_GT_GSI_OFFSET;</div><div class='add'>+		gt-&gt;mmio.adj_limit = MEDIA_GT_GSI_LENGTH;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * FIXME: At the moment multi-tile and standalone media are</div><div class='add'>+		 * mutually exclusive on current platforms.  We'll need to</div><div class='add'>+		 * come up with a better way to number GTs if we ever wind</div><div class='add'>+		 * up with platforms that support both together.</div><div class='add'>+		 */</div><div class='add'>+		drm_WARN_ON(&amp;xe-&gt;drm, id != 0);</div><div class='add'>+		gt-&gt;info.id = xe-&gt;info.gt_count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pci_remove(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+</div><div class='add'>+	xe = pci_get_drvdata(pdev);</div><div class='add'>+	if (!xe) /* driver load aborted, nothing to cleanup */</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_device_remove(xe);</div><div class='add'>+	xe_pm_runtime_fini(xe);</div><div class='add'>+	pci_set_drvdata(pdev, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='add'>+{</div><div class='add'>+	const struct xe_device_desc *desc = (const void *)ent-&gt;driver_data;</div><div class='add'>+	const struct xe_subplatform_desc *subplatform_desc;</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (desc-&gt;require_force_probe &amp;&amp; !id_forced(pdev-&gt;device)) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Your graphics device %04x is not officially supported\n"</div><div class='add'>+			 "by xe driver in this kernel version. To force Xe probe,\n"</div><div class='add'>+			 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"</div><div class='add'>+			 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"</div><div class='add'>+			 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",</div><div class='add'>+			 pdev-&gt;device, pdev-&gt;device, pdev-&gt;device,</div><div class='add'>+			 pdev-&gt;device, pdev-&gt;device);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (id_blocked(pdev-&gt;device)) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev, "Probe blocked for device [%04x:%04x].\n",</div><div class='add'>+			 pdev-&gt;vendor, pdev-&gt;device);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_display_driver_probe_defer(pdev))</div><div class='add'>+		return -EPROBE_DEFER;</div><div class='add'>+</div><div class='add'>+	err = pcim_enable_device(pdev);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe = xe_device_create(pdev, ent);</div><div class='add'>+	if (IS_ERR(xe))</div><div class='add'>+		return PTR_ERR(xe);</div><div class='add'>+</div><div class='add'>+	pci_set_drvdata(pdev, xe);</div><div class='add'>+</div><div class='add'>+	xe_pm_assert_unbounded_bridge(xe);</div><div class='add'>+	subplatform_desc = find_subplatform(xe, desc);</div><div class='add'>+</div><div class='add'>+	pci_set_master(pdev);</div><div class='add'>+</div><div class='add'>+	err = xe_info_init_early(xe, desc, subplatform_desc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_sriov_probe_early(xe, desc-&gt;has_sriov);</div><div class='add'>+</div><div class='add'>+	err = xe_device_probe_early(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_info_init(xe, desc-&gt;graphics, desc-&gt;media);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_display_probe(xe);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d",</div><div class='add'>+		desc-&gt;platform_name,</div><div class='add'>+		subplatform_desc ? subplatform_desc-&gt;name : "",</div><div class='add'>+		xe-&gt;info.devid, xe-&gt;info.revid,</div><div class='add'>+		xe-&gt;info.is_dgfx,</div><div class='add'>+		xe-&gt;info.graphics_name,</div><div class='add'>+		xe-&gt;info.graphics_verx100 / 100,</div><div class='add'>+		xe-&gt;info.graphics_verx100 % 100,</div><div class='add'>+		xe-&gt;info.media_name,</div><div class='add'>+		xe-&gt;info.media_verx100 / 100,</div><div class='add'>+		xe-&gt;info.media_verx100 % 100,</div><div class='add'>+		str_yes_no(xe-&gt;info.enable_display),</div><div class='add'>+		xe-&gt;info.dma_mask_size, xe-&gt;info.tile_count,</div><div class='add'>+		xe-&gt;info.has_heci_gscfi);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n",</div><div class='add'>+		xe_step_name(xe-&gt;info.step.graphics),</div><div class='add'>+		xe_step_name(xe-&gt;info.step.media),</div><div class='add'>+		xe_step_name(xe-&gt;info.step.display),</div><div class='add'>+		xe_step_name(xe-&gt;info.step.basedie));</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "SR-IOV support: %s (mode: %s)\n",</div><div class='add'>+		str_yes_no(xe_device_has_sriov(xe)),</div><div class='add'>+		xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));</div><div class='add'>+</div><div class='add'>+	err = xe_device_probe(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_pm_init(xe);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "d3cold: capable=%s\n",</div><div class='add'>+		str_yes_no(xe-&gt;d3cold.capable));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pci_shutdown(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	xe_device_shutdown(pdev_to_xe_device(pdev));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PM_SLEEP</div><div class='add'>+static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+	struct pci_dev *root_pdev;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;d3cold.capable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	root_pdev = pcie_find_root_port(pdev);</div><div class='add'>+	if (!root_pdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	switch (toggle) {</div><div class='add'>+	case D3COLD_DISABLE:</div><div class='add'>+		pci_d3cold_disable(root_pdev);</div><div class='add'>+		break;</div><div class='add'>+	case D3COLD_ENABLE:</div><div class='add'>+		pci_d3cold_enable(root_pdev);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_pm_suspend(pdev_to_xe_device(pdev));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enabling D3Cold is needed for S2Idle/S0ix.</div><div class='add'>+	 * It is save to allow here since xe_pm_suspend has evicted</div><div class='add'>+	 * the local memory and the direct complete optimization is disabled.</div><div class='add'>+	 */</div><div class='add'>+	d3cold_toggle(pdev, D3COLD_ENABLE);</div><div class='add'>+</div><div class='add'>+	pci_save_state(pdev);</div><div class='add'>+	pci_disable_device(pdev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* Give back the D3Cold decision to the runtime P M*/</div><div class='add'>+	d3cold_toggle(pdev, D3COLD_DISABLE);</div><div class='add'>+</div><div class='add'>+	err = pci_set_power_state(pdev, PCI_D0);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = pci_enable_device(pdev);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	pci_set_master(pdev);</div><div class='add'>+</div><div class='add'>+	err = xe_pm_resume(pdev_to_xe_device(pdev));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = xe_pm_runtime_suspend(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	pci_save_state(pdev);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed) {</div><div class='add'>+		d3cold_toggle(pdev, D3COLD_ENABLE);</div><div class='add'>+		pci_disable_device(pdev);</div><div class='add'>+		pci_ignore_hotplug(pdev);</div><div class='add'>+		pci_set_power_state(pdev, PCI_D3cold);</div><div class='add'>+	} else {</div><div class='add'>+		d3cold_toggle(pdev, D3COLD_DISABLE);</div><div class='add'>+		pci_set_power_state(pdev, PCI_D3hot);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_runtime_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = pci_set_power_state(pdev, PCI_D0);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	pci_restore_state(pdev);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed) {</div><div class='add'>+		err = pci_enable_device(pdev);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		pci_set_master(pdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return xe_pm_runtime_resume(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pci_runtime_idle(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(dev);</div><div class='add'>+	struct xe_device *xe = pdev_to_xe_device(pdev);</div><div class='add'>+</div><div class='add'>+	xe_pm_d3cold_allowed_toggle(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops xe_pm_ops = {</div><div class='add'>+	SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)</div><div class='add'>+	SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static struct pci_driver xe_pci_driver = {</div><div class='add'>+	.name = DRIVER_NAME,</div><div class='add'>+	.id_table = pciidlist,</div><div class='add'>+	.probe = xe_pci_probe,</div><div class='add'>+	.remove = xe_pci_remove,</div><div class='add'>+	.shutdown = xe_pci_shutdown,</div><div class='add'>+#ifdef CONFIG_PM_SLEEP</div><div class='add'>+	.driver.pm = &amp;xe_pm_ops,</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_register_pci_driver(void)</div><div class='add'>+{</div><div class='add'>+	return pci_register_driver(&amp;xe_pci_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_unregister_pci_driver(void)</div><div class='add'>+{</div><div class='add'>+	pci_unregister_driver(&amp;xe_pci_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+#include "tests/xe_pci.c"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pci.h b/drivers/gpu/drm/xe/xe_pci.h<br/>new file mode 100644<br/>index 000000000000..611c1209b14c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci.h</a></div><div class='hunk'>@@ -0,0 +1,12 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PCI_H_</div><div class='add'>+#define _XE_PCI_H_</div><div class='add'>+</div><div class='add'>+int xe_register_pci_driver(void);</div><div class='add'>+void xe_unregister_pci_driver(void);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h<br/>new file mode 100644<br/>index 000000000000..b1ad12fa22d6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pci_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pci_types.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PCI_TYPES_H_</div><div class='add'>+#define _XE_PCI_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_graphics_desc {</div><div class='add'>+	const char *name;</div><div class='add'>+	u8 ver;</div><div class='add'>+	u8 rel;</div><div class='add'>+</div><div class='add'>+	u8 dma_mask_size;	/* available DMA address bits */</div><div class='add'>+	u8 va_bits;</div><div class='add'>+	u8 vm_max_level;</div><div class='add'>+	u8 vram_flags;</div><div class='add'>+</div><div class='add'>+	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */</div><div class='add'>+</div><div class='add'>+	u32 tile_mmio_ext_size; /* size of MMIO extension space, per-tile */</div><div class='add'>+</div><div class='add'>+	u8 max_remote_tiles:2;</div><div class='add'>+</div><div class='add'>+	u8 has_asid:1;</div><div class='add'>+	u8 has_flat_ccs:1;</div><div class='add'>+	u8 has_range_tlb_invalidation:1;</div><div class='add'>+	u8 has_usm:1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_media_desc {</div><div class='add'>+	const char *name;</div><div class='add'>+	u8 ver;</div><div class='add'>+	u8 rel;</div><div class='add'>+</div><div class='add'>+	u64 hw_engine_mask;	/* hardware engines provided by media IP */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gmdid_map {</div><div class='add'>+	unsigned int ver;</div><div class='add'>+	const void *ip;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c<br/>new file mode 100644<br/>index 000000000000..b324dc2a5deb<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pcode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode.c</a></div><div class='hunk'>@@ -0,0 +1,296 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_pcode_api.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: PCODE</div><div class='add'>+ *</div><div class='add'>+ * Xe PCODE is the component responsible for interfacing with the PCODE</div><div class='add'>+ * firmware.</div><div class='add'>+ * It shall provide a very simple ABI to other Xe components, but be the</div><div class='add'>+ * single and consolidated place that will communicate with PCODE. All read</div><div class='add'>+ * and write operations to PCODE will be internal and private to this component.</div><div class='add'>+ *</div><div class='add'>+ * What's next:</div><div class='add'>+ * - PCODE hw metrics</div><div class='add'>+ * - PCODE for display operations</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static int pcode_mailbox_status(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 err;</div><div class='add'>+	static const struct pcode_err_decode err_decode[] = {</div><div class='add'>+		[PCODE_ILLEGAL_CMD] = {-ENXIO, "Illegal Command"},</div><div class='add'>+		[PCODE_TIMEOUT] = {-ETIMEDOUT, "Timed out"},</div><div class='add'>+		[PCODE_ILLEGAL_DATA] = {-EINVAL, "Illegal Data"},</div><div class='add'>+		[PCODE_ILLEGAL_SUBCOMMAND] = {-ENXIO, "Illegal Subcommand"},</div><div class='add'>+		[PCODE_LOCKED] = {-EBUSY, "PCODE Locked"},</div><div class='add'>+		[PCODE_GT_RATIO_OUT_OF_RANGE] = {-EOVERFLOW,</div><div class='add'>+			"GT ratio out of range"},</div><div class='add'>+		[PCODE_REJECTED] = {-EACCES, "PCODE Rejected"},</div><div class='add'>+		[PCODE_ERROR_MASK] = {-EPROTO, "Unknown"},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	err = xe_mmio_read32(gt, PCODE_MAILBOX) &amp; PCODE_ERROR_MASK;</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_err(&amp;gt_to_xe(gt)-&gt;drm, "PCODE Mailbox failed: %d %s", err,</div><div class='add'>+			err_decode[err].str ?: "Unknown");</div><div class='add'>+		return err_decode[err].errno ?: -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,</div><div class='add'>+			    unsigned int timeout_ms, bool return_data,</div><div class='add'>+			    bool atomic)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (gt_to_xe(gt)-&gt;info.skip_pcode)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	if ((xe_mmio_read32(gt, PCODE_MAILBOX) &amp; PCODE_READY) != 0)</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	xe_mmio_write32(gt, PCODE_DATA0, *data0);</div><div class='add'>+	xe_mmio_write32(gt, PCODE_DATA1, data1 ? *data1 : 0);</div><div class='add'>+	xe_mmio_write32(gt, PCODE_MAILBOX, PCODE_READY | mbox);</div><div class='add'>+</div><div class='add'>+	err = xe_mmio_wait32(gt, PCODE_MAILBOX, PCODE_READY, 0,</div><div class='add'>+			     timeout_ms * 1000, NULL, atomic);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (return_data) {</div><div class='add'>+		*data0 = xe_mmio_read32(gt, PCODE_DATA0);</div><div class='add'>+		if (data1)</div><div class='add'>+			*data1 = xe_mmio_read32(gt, PCODE_DATA1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return pcode_mailbox_status(gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 data, int timeout)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	err = pcode_mailbox_rw(gt, mbox, &amp;data, NULL, timeout, false, false);</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	err = pcode_mailbox_rw(gt, mbox, val, val1, 1, true, false);</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pcode_try_request(struct xe_gt *gt, u32 mbox,</div><div class='add'>+				u32 request, u32 reply_mask, u32 reply,</div><div class='add'>+				u32 *status, bool atomic, int timeout_us)</div><div class='add'>+{</div><div class='add'>+	int slept, wait = 10;</div><div class='add'>+</div><div class='add'>+	for (slept = 0; slept &lt; timeout_us; slept += wait) {</div><div class='add'>+		*status = pcode_mailbox_rw(gt, mbox, &amp;request, NULL, 1, true,</div><div class='add'>+					   atomic);</div><div class='add'>+		if ((*status == 0) &amp;&amp; ((request &amp; reply_mask) == reply))</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		if (atomic)</div><div class='add'>+			udelay(wait);</div><div class='add'>+		else</div><div class='add'>+			usleep_range(wait, wait &lt;&lt; 1);</div><div class='add'>+		wait &lt;&lt;= 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pcode_request - send PCODE request until acknowledgment</div><div class='add'>+ * @gt: gt</div><div class='add'>+ * @mbox: PCODE mailbox ID the request is targeted for</div><div class='add'>+ * @request: request ID</div><div class='add'>+ * @reply_mask: mask used to check for request acknowledgment</div><div class='add'>+ * @reply: value used to check for request acknowledgment</div><div class='add'>+ * @timeout_base_ms: timeout for polling with preemption enabled</div><div class='add'>+ *</div><div class='add'>+ * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE</div><div class='add'>+ * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.</div><div class='add'>+ * The request is acknowledged once the PCODE reply dword equals @reply after</div><div class='add'>+ * applying @reply_mask. Polling is first attempted with preemption enabled</div><div class='add'>+ * for @timeout_base_ms and if this times out for another 50 ms with</div><div class='add'>+ * preemption disabled.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 on success, %-ETIMEDOUT in case of a timeout, &lt;0 in case of some</div><div class='add'>+ * other error as reported by PCODE.</div><div class='add'>+ */</div><div class='add'>+int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,</div><div class='add'>+		      u32 reply_mask, u32 reply, int timeout_base_ms)</div><div class='add'>+{</div><div class='add'>+	u32 status;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	ret = xe_pcode_try_request(gt, mbox, request, reply_mask, reply, &amp;status,</div><div class='add'>+				   false, timeout_base_ms * 1000);</div><div class='add'>+	if (!ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The above can time out if the number of requests was low (2 in the</div><div class='add'>+	 * worst case) _and_ PCODE was busy for some reason even after a</div><div class='add'>+	 * (queued) request and @timeout_base_ms delay. As a workaround retry</div><div class='add'>+	 * the poll with preemption disabled to maximize the number of</div><div class='add'>+	 * requests. Increase the timeout from @timeout_base_ms to 50ms to</div><div class='add'>+	 * account for interrupts that could reduce the number of these</div><div class='add'>+	 * requests, and for any quirks of the PCODE firmware that delays</div><div class='add'>+	 * the request completion.</div><div class='add'>+	 */</div><div class='add'>+	drm_err(&amp;gt_to_xe(gt)-&gt;drm,</div><div class='add'>+		"PCODE timeout, retrying with preemption disabled\n");</div><div class='add'>+	drm_WARN_ON_ONCE(&amp;gt_to_xe(gt)-&gt;drm, timeout_base_ms &gt; 1);</div><div class='add'>+	preempt_disable();</div><div class='add'>+	ret = xe_pcode_try_request(gt, mbox, request, reply_mask, reply, &amp;status,</div><div class='add'>+				   true, timeout_base_ms * 1000);</div><div class='add'>+	preempt_enable();</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	return status ? status : ret;</div><div class='add'>+}</div><div class='add'>+/**</div><div class='add'>+ * xe_pcode_init_min_freq_table - Initialize PCODE's QOS frequency table</div><div class='add'>+ * @gt: gt instance</div><div class='add'>+ * @min_gt_freq: Minimal (RPn) GT frequency in units of 50MHz.</div><div class='add'>+ * @max_gt_freq: Maximal (RP0) GT frequency in units of 50MHz.</div><div class='add'>+ *</div><div class='add'>+ * This function initialize PCODE's QOS frequency table for a proper minimal</div><div class='add'>+ * frequency/power steering decision, depending on the current requested GT</div><div class='add'>+ * frequency. For older platforms this was a more complete table including</div><div class='add'>+ * the IA freq. However for the latest platforms this table become a simple</div><div class='add'>+ * 1-1 Ring vs GT frequency. Even though, without setting it, PCODE might</div><div class='add'>+ * not take the right decisions for some memory frequencies and affect latency.</div><div class='add'>+ *</div><div class='add'>+ * It returns 0 on success, and -ERROR number on failure, -EINVAL if max</div><div class='add'>+ * frequency is higher then the minimal, and other errors directly translated</div><div class='add'>+ * from the PCODE Error returs:</div><div class='add'>+ * - -ENXIO: "Illegal Command"</div><div class='add'>+ * - -ETIMEDOUT: "Timed out"</div><div class='add'>+ * - -EINVAL: "Illegal Data"</div><div class='add'>+ * - -ENXIO, "Illegal Subcommand"</div><div class='add'>+ * - -EBUSY: "PCODE Locked"</div><div class='add'>+ * - -EOVERFLOW, "GT ratio out of range"</div><div class='add'>+ * - -EACCES, "PCODE Rejected"</div><div class='add'>+ * - -EPROTO, "Unknown"</div><div class='add'>+ */</div><div class='add'>+int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,</div><div class='add'>+				 u32 max_gt_freq)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 freq;</div><div class='add'>+</div><div class='add'>+	if (!gt_to_xe(gt)-&gt;info.has_llc)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (max_gt_freq &lt;= min_gt_freq)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	for (freq = min_gt_freq; freq &lt;= max_gt_freq; freq++) {</div><div class='add'>+		u32 data = freq &lt;&lt; PCODE_FREQ_RING_RATIO_SHIFT | freq;</div><div class='add'>+</div><div class='add'>+		ret = pcode_mailbox_rw(gt, PCODE_WRITE_MIN_FREQ_TABLE,</div><div class='add'>+				       &amp;data, NULL, 1, false, false);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pcode_init - Ensure PCODE is initialized</div><div class='add'>+ * @gt: gt instance</div><div class='add'>+ *</div><div class='add'>+ * This function ensures that PCODE is properly initialized. To be called during</div><div class='add'>+ * probe and resume paths.</div><div class='add'>+ *</div><div class='add'>+ * It returns 0 on success, and -error number on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_pcode_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	u32 status, request = DGFX_GET_INIT_STATUS;</div><div class='add'>+	int timeout_us = 180000000; /* 3 min */</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (gt_to_xe(gt)-&gt;info.skip_pcode)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(gt_to_xe(gt)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+	ret = xe_pcode_try_request(gt, DGFX_PCODE_STATUS, request,</div><div class='add'>+				   DGFX_INIT_STATUS_COMPLETE,</div><div class='add'>+				   DGFX_INIT_STATUS_COMPLETE,</div><div class='add'>+				   &amp;status, false, timeout_us);</div><div class='add'>+	mutex_unlock(&amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;gt_to_xe(gt)-&gt;drm,</div><div class='add'>+			"PCODE initialization timedout after: 3 min\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pcode_probe - Prepare xe_pcode and also ensure PCODE is initialized.</div><div class='add'>+ * @gt: gt instance</div><div class='add'>+ *</div><div class='add'>+ * This function initializes the xe_pcode component, and when needed, it ensures</div><div class='add'>+ * that PCODE has properly performed its initialization and it is really ready</div><div class='add'>+ * to go. To be called once only during probe.</div><div class='add'>+ *</div><div class='add'>+ * It returns 0 on success, and -error number on failure.</div><div class='add'>+ */</div><div class='add'>+int xe_pcode_probe(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	drmm_mutex_init(&amp;gt_to_xe(gt)-&gt;drm, &amp;gt-&gt;pcode.lock);</div><div class='add'>+</div><div class='add'>+	if (gt_to_xe(gt)-&gt;info.skip_pcode)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!IS_DGFX(gt_to_xe(gt)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return xe_pcode_init(gt);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h<br/>new file mode 100644<br/>index 000000000000..08cb1d047cba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pcode.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode.h</a></div><div class='hunk'>@@ -0,0 +1,30 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PCODE_H_</div><div class='add'>+#define _XE_PCODE_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+int xe_pcode_probe(struct xe_gt *gt);</div><div class='add'>+int xe_pcode_init(struct xe_gt *gt);</div><div class='add'>+int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,</div><div class='add'>+				 u32 max_gt_freq);</div><div class='add'>+int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1);</div><div class='add'>+int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,</div><div class='add'>+			   int timeout_ms);</div><div class='add'>+#define xe_pcode_write(gt, mbox, val) \</div><div class='add'>+	xe_pcode_write_timeout(gt, mbox, val, 1)</div><div class='add'>+</div><div class='add'>+int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,</div><div class='add'>+		     u32 reply_mask, u32 reply, int timeout_ms);</div><div class='add'>+</div><div class='add'>+#define PCODE_MBOX(mbcmd, param1, param2)\</div><div class='add'>+	(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\</div><div class='add'>+	| FIELD_PREP(PCODE_MB_PARAM1, param1)\</div><div class='add'>+	| FIELD_PREP(PCODE_MB_PARAM2, param2))</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h<br/>new file mode 100644<br/>index 000000000000..5935cfe30204<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pcode_api.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pcode_api.h</a></div><div class='hunk'>@@ -0,0 +1,49 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Internal to xe_pcode */</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+#define PCODE_MAILBOX			XE_REG(0x138124)</div><div class='add'>+#define   PCODE_READY			REG_BIT(31)</div><div class='add'>+#define   PCODE_MB_PARAM2		REG_GENMASK(23, 16)</div><div class='add'>+#define   PCODE_MB_PARAM1		REG_GENMASK(15, 8)</div><div class='add'>+#define   PCODE_MB_COMMAND		REG_GENMASK(7, 0)</div><div class='add'>+#define   PCODE_ERROR_MASK		0xFF</div><div class='add'>+#define     PCODE_SUCCESS		0x0</div><div class='add'>+#define     PCODE_ILLEGAL_CMD		0x1</div><div class='add'>+#define     PCODE_TIMEOUT		0x2</div><div class='add'>+#define     PCODE_ILLEGAL_DATA		0x3</div><div class='add'>+#define     PCODE_ILLEGAL_SUBCOMMAND	0x4</div><div class='add'>+#define     PCODE_LOCKED		0x6</div><div class='add'>+#define     PCODE_GT_RATIO_OUT_OF_RANGE	0x10</div><div class='add'>+#define     PCODE_REJECTED		0x11</div><div class='add'>+</div><div class='add'>+#define PCODE_DATA0			XE_REG(0x138128)</div><div class='add'>+#define PCODE_DATA1			XE_REG(0x13812C)</div><div class='add'>+</div><div class='add'>+/* Min Freq QOS Table */</div><div class='add'>+#define   PCODE_WRITE_MIN_FREQ_TABLE	0x8</div><div class='add'>+#define   PCODE_READ_MIN_FREQ_TABLE	0x9</div><div class='add'>+#define   PCODE_FREQ_RING_RATIO_SHIFT	16</div><div class='add'>+</div><div class='add'>+/* PCODE Init */</div><div class='add'>+#define   DGFX_PCODE_STATUS		0x7E</div><div class='add'>+#define     DGFX_GET_INIT_STATUS	0x0</div><div class='add'>+#define     DGFX_INIT_STATUS_COMPLETE	0x1</div><div class='add'>+</div><div class='add'>+#define   PCODE_POWER_SETUP			0x7C</div><div class='add'>+#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4</div><div class='add'>+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5</div><div class='add'>+#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)</div><div class='add'>+#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */</div><div class='add'>+#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)</div><div class='add'>+</div><div class='add'>+struct pcode_err_decode {</div><div class='add'>+	int errno;</div><div class='add'>+	const char *str;</div><div class='add'>+};</div><div class='add'>+</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h<br/>new file mode 100644<br/>index 000000000000..553f53dbd093<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_platform_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_platform_types.h</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PLATFORM_INFO_TYPES_H_</div><div class='add'>+#define _XE_PLATFORM_INFO_TYPES_H_</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Keep this in graphics version based order and chronological order within a</div><div class='add'>+ * version</div><div class='add'>+ */</div><div class='add'>+enum xe_platform {</div><div class='add'>+	XE_PLATFORM_UNINITIALIZED = 0,</div><div class='add'>+	XE_TIGERLAKE,</div><div class='add'>+	XE_ROCKETLAKE,</div><div class='add'>+	XE_ALDERLAKE_S,</div><div class='add'>+	XE_ALDERLAKE_P,</div><div class='add'>+	XE_ALDERLAKE_N,</div><div class='add'>+	XE_DG1,</div><div class='add'>+	XE_DG2,</div><div class='add'>+	XE_PVC,</div><div class='add'>+	XE_METEORLAKE,</div><div class='add'>+	XE_LUNARLAKE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_subplatform {</div><div class='add'>+	XE_SUBPLATFORM_UNINITIALIZED = 0,</div><div class='add'>+	XE_SUBPLATFORM_NONE,</div><div class='add'>+	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,</div><div class='add'>+	XE_SUBPLATFORM_ALDERLAKE_S_RPLS,</div><div class='add'>+	XE_SUBPLATFORM_DG2_G10,</div><div class='add'>+	XE_SUBPLATFORM_DG2_G11,</div><div class='add'>+	XE_SUBPLATFORM_DG2_G12,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c<br/>new file mode 100644<br/>index 000000000000..b429c2876a76<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pm.c</a></div><div class='hunk'>@@ -0,0 +1,405 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_bo_evict.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_device_sysfs.h"</div><div class='add'>+#include "xe_display.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_irq.h"</div><div class='add'>+#include "xe_pcode.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Xe Power Management</div><div class='add'>+ *</div><div class='add'>+ * Xe PM shall be guided by the simplicity.</div><div class='add'>+ * Use the simplest hook options whenever possible.</div><div class='add'>+ * Let's not reinvent the runtime_pm references and hooks.</div><div class='add'>+ * Shall have a clear separation of display and gt underneath this component.</div><div class='add'>+ *</div><div class='add'>+ * What's next:</div><div class='add'>+ *</div><div class='add'>+ * For now s2idle and s3 are only working in integrated devices. The next step</div><div class='add'>+ * is to iterate through all VRAM's BO backing them up into the system memory</div><div class='add'>+ * before allowing the system suspend.</div><div class='add'>+ *</div><div class='add'>+ * Also runtime_pm needs to be here from the beginning.</div><div class='add'>+ *</div><div class='add'>+ * RC6/RPS are also critical PM features. Let's start with GuCRC and GuC SLPC</div><div class='add'>+ * and no wait boost. Frequency optimizations should come on a next stage.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pm_suspend - Helper for System suspend, i.e. S0-&gt;S3 / S0-&gt;S2idle</div><div class='add'>+ * @xe: xe device instance</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success</div><div class='add'>+ */</div><div class='add'>+int xe_pm_suspend(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_gt_suspend_prepare(gt);</div><div class='add'>+</div><div class='add'>+	/* FIXME: Super racey... */</div><div class='add'>+	err = xe_bo_evict_all(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_display_pm_suspend(xe);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_gt_suspend(gt);</div><div class='add'>+		if (err) {</div><div class='add'>+			xe_display_pm_resume(xe);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_irq_suspend(xe);</div><div class='add'>+</div><div class='add'>+	xe_display_pm_suspend_late(xe);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pm_resume - Helper for System resume S3-&gt;S0 / S2idle-&gt;S0</div><div class='add'>+ * @xe: xe device instance</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success</div><div class='add'>+ */</div><div class='add'>+int xe_pm_resume(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_wa_apply_tile_workarounds(tile);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_pcode_init(gt);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_display_pm_resume_early(xe);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This only restores pinned memory which is the memory required for the</div><div class='add'>+	 * GT(s) to resume.</div><div class='add'>+	 */</div><div class='add'>+	err = xe_bo_restore_kernel(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_irq_resume(xe);</div><div class='add'>+</div><div class='add'>+	xe_display_pm_resume(xe);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_gt_resume(gt);</div><div class='add'>+</div><div class='add'>+	err = xe_bo_restore_user(xe);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_pm_pci_d3cold_capable(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *root_pdev;</div><div class='add'>+</div><div class='add'>+	root_pdev = pcie_find_root_port(pdev);</div><div class='add'>+	if (!root_pdev)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* D3Cold requires PME capability and _PR3 power resource */</div><div class='add'>+	if (!pci_pme_capable(root_pdev, PCI_D3cold) || !pci_pr3_present(root_pdev))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pm_runtime_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Disable the system suspend direct complete optimization.</div><div class='add'>+	 * We need to ensure that the regular device suspend/resume functions</div><div class='add'>+	 * are called since our runtime_pm cannot guarantee local memory</div><div class='add'>+	 * eviction for d3cold.</div><div class='add'>+	 * TODO: Check HDA audio dependencies claimed by i915, and then enforce</div><div class='add'>+	 *       this option to integrated graphics as well.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		dev_pm_set_driver_flags(dev, DPM_FLAG_NO_DIRECT_COMPLETE);</div><div class='add'>+</div><div class='add'>+	pm_runtime_use_autosuspend(dev);</div><div class='add'>+	pm_runtime_set_autosuspend_delay(dev, 1000);</div><div class='add'>+	pm_runtime_set_active(dev);</div><div class='add'>+	pm_runtime_allow(dev);</div><div class='add'>+	pm_runtime_mark_last_busy(dev);</div><div class='add'>+	pm_runtime_put(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pm_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+</div><div class='add'>+	/* For now suspend/resume is only allowed with GuC */</div><div class='add'>+	if (!xe_device_uc_enabled(xe))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drmm_mutex_init(&amp;xe-&gt;drm, &amp;xe-&gt;d3cold.lock);</div><div class='add'>+</div><div class='add'>+	xe-&gt;d3cold.capable = xe_pm_pci_d3cold_capable(pdev);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.capable) {</div><div class='add'>+		xe_device_sysfs_init(xe);</div><div class='add'>+		xe_pm_set_vram_threshold(xe, DEFAULT_VRAM_THRESHOLD);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_pm_runtime_init(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pm_runtime_fini(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+</div><div class='add'>+	pm_runtime_get_sync(dev);</div><div class='add'>+	pm_runtime_forbid(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pm_write_callback_task(struct xe_device *xe,</div><div class='add'>+				      struct task_struct *task)</div><div class='add'>+{</div><div class='add'>+	WRITE_ONCE(xe-&gt;pm_callback_task, task);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Just in case it's somehow possible for our writes to be reordered to</div><div class='add'>+	 * the extent that something else re-uses the task written in</div><div class='add'>+	 * pm_callback_task. For example after returning from the callback, but</div><div class='add'>+	 * before the reordered write that resets pm_callback_task back to NULL.</div><div class='add'>+	 */</div><div class='add'>+	smp_mb(); /* pairs with xe_pm_read_callback_task */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct task_struct *xe_pm_read_callback_task(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	smp_mb(); /* pairs with xe_pm_write_callback_task */</div><div class='add'>+</div><div class='add'>+	return READ_ONCE(xe-&gt;pm_callback_task);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_runtime_suspend(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed &amp;&amp; xe_device_mem_access_ongoing(xe))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	/* Disable access_ongoing asserts and prevent recursive pm calls */</div><div class='add'>+	xe_pm_write_callback_task(xe, current);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The actual xe_device_mem_access_put() is always async underneath, so</div><div class='add'>+	 * exactly where that is called should makes no difference to us. However</div><div class='add'>+	 * we still need to be very careful with the locks that this callback</div><div class='add'>+	 * acquires and the locks that are acquired and held by any callers of</div><div class='add'>+	 * xe_device_mem_access_get(). We already have the matching annotation</div><div class='add'>+	 * on that side, but we also need it here. For example lockdep should be</div><div class='add'>+	 * able to tell us if the following scenario is in theory possible:</div><div class='add'>+	 *</div><div class='add'>+	 * CPU0                          | CPU1 (kworker)</div><div class='add'>+	 * lock(A)                       |</div><div class='add'>+	 *                               | xe_pm_runtime_suspend()</div><div class='add'>+	 *                               |      lock(A)</div><div class='add'>+	 * xe_device_mem_access_get()    |</div><div class='add'>+	 *</div><div class='add'>+	 * This will clearly deadlock since rpm core needs to wait for</div><div class='add'>+	 * xe_pm_runtime_suspend() to complete, but here we are holding lock(A)</div><div class='add'>+	 * on CPU0 which prevents CPU1 making forward progress.  With the</div><div class='add'>+	 * annotation here and in xe_device_mem_access_get() lockdep will see</div><div class='add'>+	 * the potential lock inversion and give us a nice splat.</div><div class='add'>+	 */</div><div class='add'>+	lock_map_acquire(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed) {</div><div class='add'>+		err = xe_bo_evict_all(xe);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		err = xe_gt_suspend(gt);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_irq_suspend(xe);</div><div class='add'>+out:</div><div class='add'>+	lock_map_release(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+	xe_pm_write_callback_task(xe, NULL);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_runtime_resume(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 id;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	/* Disable access_ongoing asserts and prevent recursive pm calls */</div><div class='add'>+	xe_pm_write_callback_task(xe, current);</div><div class='add'>+</div><div class='add'>+	lock_map_acquire(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * It can be possible that xe has allowed d3cold but other pcie devices</div><div class='add'>+	 * in gfx card soc would have blocked d3cold, therefore card has not</div><div class='add'>+	 * really lost power. Detecting primary Gt power is sufficient.</div><div class='add'>+	 */</div><div class='add'>+	gt = xe_device_get_gt(xe, 0);</div><div class='add'>+	xe-&gt;d3cold.power_lost = xe_guc_in_reset(&amp;gt-&gt;uc.guc);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed &amp;&amp; xe-&gt;d3cold.power_lost) {</div><div class='add'>+		for_each_gt(gt, xe, id) {</div><div class='add'>+			err = xe_pcode_init(gt);</div><div class='add'>+			if (err)</div><div class='add'>+				goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This only restores pinned memory which is the memory</div><div class='add'>+		 * required for the GT(s) to resume.</div><div class='add'>+		 */</div><div class='add'>+		err = xe_bo_restore_kernel(xe);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_irq_resume(xe);</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id)</div><div class='add'>+		xe_gt_resume(gt);</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;d3cold.allowed &amp;&amp; xe-&gt;d3cold.power_lost) {</div><div class='add'>+		err = xe_bo_restore_user(xe);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='add'>+out:</div><div class='add'>+	lock_map_release(&amp;xe_device_mem_access_lockdep_map);</div><div class='add'>+	xe_pm_write_callback_task(xe, NULL);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_runtime_get(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return pm_runtime_get_sync(xe-&gt;drm.dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_runtime_put(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	pm_runtime_mark_last_busy(xe-&gt;drm.dev);</div><div class='add'>+	return pm_runtime_put(xe-&gt;drm.dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_runtime_get_if_active(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return pm_runtime_get_if_active(xe-&gt;drm.dev, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pm_assert_unbounded_bridge(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	struct pci_dev *bridge = pci_upstream_bridge(pdev);</div><div class='add'>+</div><div class='add'>+	if (!bridge)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!bridge-&gt;driver) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "unbounded parent pci bridge, device won't support any PM support.\n");</div><div class='add'>+		device_set_pm_not_required(&amp;pdev-&gt;dev);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_pm_set_vram_threshold(struct xe_device *xe, u32 threshold)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *man;</div><div class='add'>+	u32 vram_total_mb = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = XE_PL_VRAM0; i &lt;= XE_PL_VRAM1; ++i) {</div><div class='add'>+		man = ttm_manager_type(&amp;xe-&gt;ttm, i);</div><div class='add'>+		if (man)</div><div class='add'>+			vram_total_mb += DIV_ROUND_UP_ULL(man-&gt;size, 1024 * 1024);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Total vram %u mb\n", vram_total_mb);</div><div class='add'>+</div><div class='add'>+	if (threshold &gt; vram_total_mb)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xe-&gt;d3cold.lock);</div><div class='add'>+	xe-&gt;d3cold.vram_threshold = threshold;</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;d3cold.lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_pm_d3cold_allowed_toggle(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *man;</div><div class='add'>+	u32 total_vram_used_mb = 0;</div><div class='add'>+	u64 vram_used;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!xe-&gt;d3cold.capable) {</div><div class='add'>+		xe-&gt;d3cold.allowed = false;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = XE_PL_VRAM0; i &lt;= XE_PL_VRAM1; ++i) {</div><div class='add'>+		man = ttm_manager_type(&amp;xe-&gt;ttm, i);</div><div class='add'>+		if (man) {</div><div class='add'>+			vram_used = ttm_resource_manager_usage(man);</div><div class='add'>+			total_vram_used_mb += DIV_ROUND_UP_ULL(vram_used, 1024 * 1024);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xe-&gt;d3cold.lock);</div><div class='add'>+</div><div class='add'>+	if (total_vram_used_mb &lt; xe-&gt;d3cold.vram_threshold)</div><div class='add'>+		xe-&gt;d3cold.allowed = true;</div><div class='add'>+	else</div><div class='add'>+		xe-&gt;d3cold.allowed = false;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;d3cold.lock);</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+		"d3cold: allowed=%s\n", str_yes_no(xe-&gt;d3cold.allowed));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pm.h b/drivers/gpu/drm/xe/xe_pm.h<br/>new file mode 100644<br/>index 000000000000..6b9031f7af24<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pm.h</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PM_H_</div><div class='add'>+#define _XE_PM_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * TODO: Threshold = 0 will block D3Cold.</div><div class='add'>+ *       Before we can move this to a higher value (like 300), we need to:</div><div class='add'>+ *           1. rewrite the VRAM save / restore to avoid buffer object locks</div><div class='add'>+ */</div><div class='add'>+#define DEFAULT_VRAM_THRESHOLD 0 /* in MB */</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+int xe_pm_suspend(struct xe_device *xe);</div><div class='add'>+int xe_pm_resume(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+void xe_pm_init(struct xe_device *xe);</div><div class='add'>+void xe_pm_runtime_fini(struct xe_device *xe);</div><div class='add'>+int xe_pm_runtime_suspend(struct xe_device *xe);</div><div class='add'>+int xe_pm_runtime_resume(struct xe_device *xe);</div><div class='add'>+int xe_pm_runtime_get(struct xe_device *xe);</div><div class='add'>+int xe_pm_runtime_put(struct xe_device *xe);</div><div class='add'>+int xe_pm_runtime_get_if_active(struct xe_device *xe);</div><div class='add'>+void xe_pm_assert_unbounded_bridge(struct xe_device *xe);</div><div class='add'>+int xe_pm_set_vram_threshold(struct xe_device *xe, u32 threshold);</div><div class='add'>+void xe_pm_d3cold_allowed_toggle(struct xe_device *xe);</div><div class='add'>+struct task_struct *xe_pm_read_callback_task(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.c b/drivers/gpu/drm/xe/xe_preempt_fence.c<br/>new file mode 100644<br/>index 000000000000..7bce2a332603<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_preempt_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence.c</a></div><div class='hunk'>@@ -0,0 +1,158 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_preempt_fence.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+static void preempt_fence_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	bool cookie = dma_fence_begin_signalling();</div><div class='add'>+	struct xe_preempt_fence *pfence =</div><div class='add'>+		container_of(w, typeof(*pfence), preempt_work);</div><div class='add'>+	struct xe_exec_queue *q = pfence-&gt;q;</div><div class='add'>+</div><div class='add'>+	if (pfence-&gt;error)</div><div class='add'>+		dma_fence_set_error(&amp;pfence-&gt;base, pfence-&gt;error);</div><div class='add'>+	else</div><div class='add'>+		q-&gt;ops-&gt;suspend_wait(q);</div><div class='add'>+</div><div class='add'>+	dma_fence_signal(&amp;pfence-&gt;base);</div><div class='add'>+	dma_fence_end_signalling(cookie);</div><div class='add'>+</div><div class='add'>+	xe_vm_queue_rebind_worker(q-&gt;vm);</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+preempt_fence_get_driver_name(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return "xe";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+preempt_fence_get_timeline_name(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return "preempt";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool preempt_fence_enable_signaling(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_preempt_fence *pfence =</div><div class='add'>+		container_of(fence, typeof(*pfence), base);</div><div class='add'>+	struct xe_exec_queue *q = pfence-&gt;q;</div><div class='add'>+</div><div class='add'>+	pfence-&gt;error = q-&gt;ops-&gt;suspend(q);</div><div class='add'>+	queue_work(system_unbound_wq, &amp;pfence-&gt;preempt_work);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops preempt_fence_ops = {</div><div class='add'>+	.get_driver_name = preempt_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = preempt_fence_get_timeline_name,</div><div class='add'>+	.enable_signaling = preempt_fence_enable_signaling,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_preempt_fence_alloc() - Allocate a preempt fence with minimal</div><div class='add'>+ * initialization</div><div class='add'>+ *</div><div class='add'>+ * Allocate a preempt fence, and initialize its list head.</div><div class='add'>+ * If the preempt_fence allocated has been armed with</div><div class='add'>+ * xe_preempt_fence_arm(), it must be freed using dma_fence_put(). If not,</div><div class='add'>+ * it must be freed using xe_preempt_fence_free().</div><div class='add'>+ *</div><div class='add'>+ * Return: A struct xe_preempt_fence pointer used for calling into</div><div class='add'>+ * xe_preempt_fence_arm() or xe_preempt_fence_free().</div><div class='add'>+ * An error pointer on error.</div><div class='add'>+ */</div><div class='add'>+struct xe_preempt_fence *xe_preempt_fence_alloc(void)</div><div class='add'>+{</div><div class='add'>+	struct xe_preempt_fence *pfence;</div><div class='add'>+</div><div class='add'>+	pfence = kmalloc(sizeof(*pfence), GFP_KERNEL);</div><div class='add'>+	if (!pfence)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;pfence-&gt;link);</div><div class='add'>+	INIT_WORK(&amp;pfence-&gt;preempt_work, preempt_fence_work_func);</div><div class='add'>+</div><div class='add'>+	return pfence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_preempt_fence_free() - Free a preempt fence allocated using</div><div class='add'>+ * xe_preempt_fence_alloc().</div><div class='add'>+ * @pfence: pointer obtained from xe_preempt_fence_alloc();</div><div class='add'>+ *</div><div class='add'>+ * Free a preempt fence that has not yet been armed.</div><div class='add'>+ */</div><div class='add'>+void xe_preempt_fence_free(struct xe_preempt_fence *pfence)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;pfence-&gt;link);</div><div class='add'>+	kfree(pfence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_preempt_fence_arm() - Arm a preempt fence allocated using</div><div class='add'>+ * xe_preempt_fence_alloc().</div><div class='add'>+ * @pfence: The struct xe_preempt_fence pointer returned from</div><div class='add'>+ *          xe_preempt_fence_alloc().</div><div class='add'>+ * @q: The struct xe_exec_queue used for arming.</div><div class='add'>+ * @context: The dma-fence context used for arming.</div><div class='add'>+ * @seqno: The dma-fence seqno used for arming.</div><div class='add'>+ *</div><div class='add'>+ * Inserts the preempt fence into @context's timeline, takes @link off any</div><div class='add'>+ * list, and registers the struct xe_exec_queue as the xe_engine to be preempted.</div><div class='add'>+ *</div><div class='add'>+ * Return: A pointer to a struct dma_fence embedded into the preempt fence.</div><div class='add'>+ * This function doesn't error.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q,</div><div class='add'>+		     u64 context, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	list_del_init(&amp;pfence-&gt;link);</div><div class='add'>+	pfence-&gt;q = xe_exec_queue_get(q);</div><div class='add'>+	dma_fence_init(&amp;pfence-&gt;base, &amp;preempt_fence_ops,</div><div class='add'>+		      &amp;q-&gt;compute.lock, context, seqno);</div><div class='add'>+</div><div class='add'>+	return &amp;pfence-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_preempt_fence_create() - Helper to create and arm a preempt fence.</div><div class='add'>+ * @q: The struct xe_exec_queue used for arming.</div><div class='add'>+ * @context: The dma-fence context used for arming.</div><div class='add'>+ * @seqno: The dma-fence seqno used for arming.</div><div class='add'>+ *</div><div class='add'>+ * Allocates and inserts the preempt fence into @context's timeline,</div><div class='add'>+ * and registers @e as the struct xe_exec_queue to be preempted.</div><div class='add'>+ *</div><div class='add'>+ * Return: A pointer to the resulting struct dma_fence on success. An error</div><div class='add'>+ * pointer on error. In particular if allocation fails it returns</div><div class='add'>+ * ERR_PTR(-ENOMEM);</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_preempt_fence_create(struct xe_exec_queue *q,</div><div class='add'>+			u64 context, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	struct xe_preempt_fence *pfence;</div><div class='add'>+</div><div class='add'>+	pfence = xe_preempt_fence_alloc();</div><div class='add'>+	if (IS_ERR(pfence))</div><div class='add'>+		return ERR_CAST(pfence);</div><div class='add'>+</div><div class='add'>+	return xe_preempt_fence_arm(pfence, q, context, seqno);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_fence_is_xe_preempt(const struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return fence-&gt;ops == &amp;preempt_fence_ops;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.h b/drivers/gpu/drm/xe/xe_preempt_fence.h<br/>new file mode 100644<br/>index 000000000000..9406c6fea525<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_preempt_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence.h</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PREEMPT_FENCE_H_</div><div class='add'>+#define _XE_PREEMPT_FENCE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_preempt_fence_types.h"</div><div class='add'>+</div><div class='add'>+struct list_head;</div><div class='add'>+</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_preempt_fence_create(struct xe_exec_queue *q,</div><div class='add'>+			u64 context, u32 seqno);</div><div class='add'>+</div><div class='add'>+struct xe_preempt_fence *xe_preempt_fence_alloc(void);</div><div class='add'>+</div><div class='add'>+void xe_preempt_fence_free(struct xe_preempt_fence *pfence);</div><div class='add'>+</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q,</div><div class='add'>+		     u64 context, u32 seqno);</div><div class='add'>+</div><div class='add'>+static inline struct xe_preempt_fence *</div><div class='add'>+to_preempt_fence(struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	return container_of(fence, struct xe_preempt_fence, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_preempt_fence_link() - Return a link used to keep unarmed preempt</div><div class='add'>+ * fences on a list.</div><div class='add'>+ * @pfence: Pointer to the preempt fence.</div><div class='add'>+ *</div><div class='add'>+ * The link is embedded in the struct xe_preempt_fence. Use</div><div class='add'>+ * link_to_preempt_fence() to convert back to the preempt fence.</div><div class='add'>+ *</div><div class='add'>+ * Return: A pointer to an embedded struct list_head.</div><div class='add'>+ */</div><div class='add'>+static inline struct list_head *</div><div class='add'>+xe_preempt_fence_link(struct xe_preempt_fence *pfence)</div><div class='add'>+{</div><div class='add'>+	return &amp;pfence-&gt;link;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * to_preempt_fence_from_link() - Convert back to a preempt fence pointer</div><div class='add'>+ * from a link obtained with xe_preempt_fence_link().</div><div class='add'>+ * @link: The struct list_head obtained from xe_preempt_fence_link().</div><div class='add'>+ *</div><div class='add'>+ * Return: A pointer to the embedding struct xe_preempt_fence.</div><div class='add'>+ */</div><div class='add'>+static inline struct xe_preempt_fence *</div><div class='add'>+to_preempt_fence_from_link(struct list_head *link)</div><div class='add'>+{</div><div class='add'>+	return container_of(link, struct xe_preempt_fence, link);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_fence_is_xe_preempt(const struct dma_fence *fence);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_preempt_fence_types.h b/drivers/gpu/drm/xe/xe_preempt_fence_types.h<br/>new file mode 100644<br/>index 000000000000..b54b5c29b533<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_preempt_fence_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_preempt_fence_types.h</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PREEMPT_FENCE_TYPES_H_</div><div class='add'>+#define _XE_PREEMPT_FENCE_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/workqueue.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_preempt_fence - XE preempt fence</div><div class='add'>+ *</div><div class='add'>+ * hardware and triggers a callback once the xe_engine is complete.</div><div class='add'>+ */</div><div class='add'>+struct xe_preempt_fence {</div><div class='add'>+	/** @base: dma fence base */</div><div class='add'>+	struct dma_fence base;</div><div class='add'>+	/** @link: link into list of pending preempt fences */</div><div class='add'>+	struct list_head link;</div><div class='add'>+	/** @q: exec queue for this preempt fence */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	/** @preempt_work: work struct which issues preemption */</div><div class='add'>+	struct work_struct preempt_work;</div><div class='add'>+	/** @error: preempt fence is in error state */</div><div class='add'>+	int error;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c<br/>new file mode 100644<br/>index 000000000000..de1030a47588<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt.c</a></div><div class='hunk'>@@ -0,0 +1,1653 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_pt.h"</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_pt_types.h"</div><div class='add'>+#include "xe_pt_walk.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+struct xe_pt_dir {</div><div class='add'>+	struct xe_pt pt;</div><div class='add'>+	/** @dir: Directory structure for the xe_pt_walk functionality */</div><div class='add'>+	struct xe_ptw_dir dir;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)</div><div class='add'>+#define xe_pt_set_addr(__xe_pt, __addr) ((__xe_pt)-&gt;addr = (__addr))</div><div class='add'>+#define xe_pt_addr(__xe_pt) ((__xe_pt)-&gt;addr)</div><div class='add'>+#else</div><div class='add'>+#define xe_pt_set_addr(__xe_pt, __addr)</div><div class='add'>+#define xe_pt_addr(__xe_pt) 0ull</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static const u64 xe_normal_pt_shifts[] = {12, 21, 30, 39, 48};</div><div class='add'>+static const u64 xe_compact_pt_shifts[] = {16, 21, 30, 39, 48};</div><div class='add'>+</div><div class='add'>+#define XE_PT_HIGHEST_LEVEL (ARRAY_SIZE(xe_normal_pt_shifts) - 1)</div><div class='add'>+</div><div class='add'>+static struct xe_pt_dir *as_xe_pt_dir(struct xe_pt *pt)</div><div class='add'>+{</div><div class='add'>+	return container_of(pt, struct xe_pt_dir, pt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_pt *xe_pt_entry(struct xe_pt_dir *pt_dir, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	return container_of(pt_dir-&gt;dir.entries[index], struct xe_pt, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+			     unsigned int level)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	u16 pat_index = xe-&gt;pat.idx[XE_CACHE_WB];</div><div class='add'>+	u8 id = tile-&gt;id;</div><div class='add'>+</div><div class='add'>+	if (!xe_vm_has_scratch(vm))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (level &gt; MAX_HUGEPTE_LEVEL)</div><div class='add'>+		return vm-&gt;pt_ops-&gt;pde_encode_bo(vm-&gt;scratch_pt[id][level - 1]-&gt;bo,</div><div class='add'>+						 0, pat_index);</div><div class='add'>+</div><div class='add'>+	return vm-&gt;pt_ops-&gt;pte_encode_addr(xe, 0, pat_index, level, IS_DGFX(xe), 0) |</div><div class='add'>+		XE_PTE_NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_create() - Create a page-table.</div><div class='add'>+ * @vm: The vm to create for.</div><div class='add'>+ * @tile: The tile to create for.</div><div class='add'>+ * @level: The page-table level.</div><div class='add'>+ *</div><div class='add'>+ * Allocate and initialize a single struct xe_pt metadata structure. Also</div><div class='add'>+ * create the corresponding page-table bo, but don't initialize it. If the</div><div class='add'>+ * level is grater than zero, then it's assumed to be a directory page-</div><div class='add'>+ * table and the directory structure is also allocated and initialized to</div><div class='add'>+ * NULL pointers.</div><div class='add'>+ *</div><div class='add'>+ * Return: A valid struct xe_pt pointer on success, Pointer error code on</div><div class='add'>+ * error.</div><div class='add'>+ */</div><div class='add'>+struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,</div><div class='add'>+			   unsigned int level)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt *pt;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	size_t size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	size = !level ?  sizeof(struct xe_pt) : sizeof(struct xe_pt_dir) +</div><div class='add'>+		XE_PDES * sizeof(struct xe_ptw *);</div><div class='add'>+	pt = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!pt)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(vm-&gt;xe, tile, vm, SZ_4K,</div><div class='add'>+				  ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				  XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT |</div><div class='add'>+				  XE_BO_CREATE_PINNED_BIT |</div><div class='add'>+				  XE_BO_CREATE_NO_RESV_EVICT |</div><div class='add'>+				  XE_BO_PAGETABLE);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		err = PTR_ERR(bo);</div><div class='add'>+		goto err_kfree;</div><div class='add'>+	}</div><div class='add'>+	pt-&gt;bo = bo;</div><div class='add'>+	pt-&gt;level = level;</div><div class='add'>+	pt-&gt;base.dir = level ? &amp;as_xe_pt_dir(pt)-&gt;dir : NULL;</div><div class='add'>+</div><div class='add'>+	if (vm-&gt;xef)</div><div class='add'>+		xe_drm_client_add_bo(vm-&gt;xef-&gt;client, pt-&gt;bo);</div><div class='add'>+	xe_tile_assert(tile, level &lt;= XE_VM_MAX_LEVEL);</div><div class='add'>+</div><div class='add'>+	return pt;</div><div class='add'>+</div><div class='add'>+err_kfree:</div><div class='add'>+	kfree(pt);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_populate_empty() - Populate a page-table bo with scratch- or zero</div><div class='add'>+ * entries.</div><div class='add'>+ * @tile: The tile the scratch pagetable of which to use.</div><div class='add'>+ * @vm: The vm we populate for.</div><div class='add'>+ * @pt: The pagetable the bo of which to initialize.</div><div class='add'>+ *</div><div class='add'>+ * Populate the page-table bo of @pt with entries pointing into the tile's</div><div class='add'>+ * scratch page-table tree if any. Otherwise populate with zeros.</div><div class='add'>+ */</div><div class='add'>+void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+			  struct xe_pt *pt)</div><div class='add'>+{</div><div class='add'>+	struct iosys_map *map = &amp;pt-&gt;bo-&gt;vmap;</div><div class='add'>+	u64 empty;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!xe_vm_has_scratch(vm)) {</div><div class='add'>+		/*</div><div class='add'>+		 * FIXME: Some memory is allocated already allocated to zero?</div><div class='add'>+		 * Find out which memory that is and avoid this memset...</div><div class='add'>+		 */</div><div class='add'>+		xe_map_memset(vm-&gt;xe, map, 0, 0, SZ_4K);</div><div class='add'>+	} else {</div><div class='add'>+		empty = __xe_pt_empty_pte(tile, vm, pt-&gt;level);</div><div class='add'>+		for (i = 0; i &lt; XE_PDES; i++)</div><div class='add'>+			xe_pt_write(vm-&gt;xe, map, i, empty);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_shift() - Return the ilog2 value of the size of the address range of</div><div class='add'>+ * a page-table at a certain level.</div><div class='add'>+ * @level: The level.</div><div class='add'>+ *</div><div class='add'>+ * Return: The ilog2 value of the size of the address range of a page-table</div><div class='add'>+ * at level @level.</div><div class='add'>+ */</div><div class='add'>+unsigned int xe_pt_shift(unsigned int level)</div><div class='add'>+{</div><div class='add'>+	return XE_PTE_SHIFT + XE_PDE_SHIFT * level;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_destroy() - Destroy a page-table tree.</div><div class='add'>+ * @pt: The root of the page-table tree to destroy.</div><div class='add'>+ * @flags: vm flags. Currently unused.</div><div class='add'>+ * @deferred: List head of lockless list for deferred putting. NULL for</div><div class='add'>+ *            immediate putting.</div><div class='add'>+ *</div><div class='add'>+ * Puts the page-table bo, recursively calls xe_pt_destroy on all children</div><div class='add'>+ * and finally frees @pt. TODO: Can we remove the @flags argument?</div><div class='add'>+ */</div><div class='add'>+void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!pt)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!list_empty(&amp;pt-&gt;bo-&gt;ttm.base.gpuva.list));</div><div class='add'>+	xe_bo_unpin(pt-&gt;bo);</div><div class='add'>+	xe_bo_put_deferred(pt-&gt;bo, deferred);</div><div class='add'>+</div><div class='add'>+	if (pt-&gt;level &gt; 0 &amp;&amp; pt-&gt;num_live) {</div><div class='add'>+		struct xe_pt_dir *pt_dir = as_xe_pt_dir(pt);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; XE_PDES; i++) {</div><div class='add'>+			if (xe_pt_entry(pt_dir, i))</div><div class='add'>+				xe_pt_destroy(xe_pt_entry(pt_dir, i), flags,</div><div class='add'>+					      deferred);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	kfree(pt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Pagetable building</div><div class='add'>+ *</div><div class='add'>+ * Below we use the term "page-table" for both page-directories, containing</div><div class='add'>+ * pointers to lower level page-directories or page-tables, and level 0</div><div class='add'>+ * page-tables that contain only page-table-entries pointing to memory pages.</div><div class='add'>+ *</div><div class='add'>+ * When inserting an address range in an already existing page-table tree</div><div class='add'>+ * there will typically be a set of page-tables that are shared with other</div><div class='add'>+ * address ranges, and a set that are private to this address range.</div><div class='add'>+ * The set of shared page-tables can be at most two per level,</div><div class='add'>+ * and those can't be updated immediately because the entries of those</div><div class='add'>+ * page-tables may still be in use by the gpu for other mappings. Therefore</div><div class='add'>+ * when inserting entries into those, we instead stage those insertions by</div><div class='add'>+ * adding insertion data into struct xe_vm_pgtable_update structures. This</div><div class='add'>+ * data, (subtrees for the cpu and page-table-entries for the gpu) is then</div><div class='add'>+ * added in a separate commit step. CPU-data is committed while still under the</div><div class='add'>+ * vm lock, the object lock and for userptr, the notifier lock in read mode.</div><div class='add'>+ * The GPU async data is committed either by the GPU or CPU after fulfilling</div><div class='add'>+ * relevant dependencies.</div><div class='add'>+ * For non-shared page-tables (and, in fact, for shared ones that aren't</div><div class='add'>+ * existing at the time of staging), we add the data in-place without the</div><div class='add'>+ * special update structures. This private part of the page-table tree will</div><div class='add'>+ * remain disconnected from the vm page-table tree until data is committed to</div><div class='add'>+ * the shared page tables of the vm tree in the commit phase.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct xe_pt_update {</div><div class='add'>+	/** @update: The update structure we're building for this parent. */</div><div class='add'>+	struct xe_vm_pgtable_update *update;</div><div class='add'>+	/** @parent: The parent. Used to detect a parent change. */</div><div class='add'>+	struct xe_pt *parent;</div><div class='add'>+	/** @preexisting: Whether the parent was pre-existing or allocated */</div><div class='add'>+	bool preexisting;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_pt_stage_bind_walk {</div><div class='add'>+	/** base: The base class. */</div><div class='add'>+	struct xe_pt_walk base;</div><div class='add'>+</div><div class='add'>+	/* Input parameters for the walk */</div><div class='add'>+	/** @vm: The vm we're building for. */</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	/** @tile: The tile we're building for. */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	/** @default_pte: PTE flag only template. No address is associated */</div><div class='add'>+	u64 default_pte;</div><div class='add'>+	/** @dma_offset: DMA offset to add to the PTE. */</div><div class='add'>+	u64 dma_offset;</div><div class='add'>+	/**</div><div class='add'>+	 * @needs_64k: This address range enforces 64K alignment and</div><div class='add'>+	 * granularity.</div><div class='add'>+	 */</div><div class='add'>+	bool needs_64K;</div><div class='add'>+	/**</div><div class='add'>+	 * @vma: VMA being mapped</div><div class='add'>+	 */</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+</div><div class='add'>+	/* Also input, but is updated during the walk*/</div><div class='add'>+	/** @curs: The DMA address cursor. */</div><div class='add'>+	struct xe_res_cursor *curs;</div><div class='add'>+	/** @va_curs_start: The Virtual address coresponding to @curs-&gt;start */</div><div class='add'>+	u64 va_curs_start;</div><div class='add'>+</div><div class='add'>+	/* Output */</div><div class='add'>+	struct xe_walk_update {</div><div class='add'>+		/** @wupd.entries: Caller provided storage. */</div><div class='add'>+		struct xe_vm_pgtable_update *entries;</div><div class='add'>+		/** @wupd.num_used_entries: Number of update @entries used. */</div><div class='add'>+		unsigned int num_used_entries;</div><div class='add'>+		/** @wupd.updates: Tracks the update entry at a given level */</div><div class='add'>+		struct xe_pt_update updates[XE_VM_MAX_LEVEL + 1];</div><div class='add'>+	} wupd;</div><div class='add'>+</div><div class='add'>+	/* Walk state */</div><div class='add'>+	/**</div><div class='add'>+	 * @l0_end_addr: The end address of the current l0 leaf. Used for</div><div class='add'>+	 * 64K granularity detection.</div><div class='add'>+	 */</div><div class='add'>+	u64 l0_end_addr;</div><div class='add'>+	/** @addr_64K: The start address of the current 64K chunk. */</div><div class='add'>+	u64 addr_64K;</div><div class='add'>+	/** @found_64: Whether @add_64K actually points to a 64K chunk. */</div><div class='add'>+	bool found_64K;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_pt_new_shared(struct xe_walk_update *wupd, struct xe_pt *parent,</div><div class='add'>+		 pgoff_t offset, bool alloc_entries)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_update *upd = &amp;wupd-&gt;updates[parent-&gt;level];</div><div class='add'>+	struct xe_vm_pgtable_update *entry;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For *each level*, we could only have one active</div><div class='add'>+	 * struct xt_pt_update at any one time. Once we move on to a</div><div class='add'>+	 * new parent and page-directory, the old one is complete, and</div><div class='add'>+	 * updates are either already stored in the build tree or in</div><div class='add'>+	 * @wupd-&gt;entries</div><div class='add'>+	 */</div><div class='add'>+	if (likely(upd-&gt;parent == parent))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	upd-&gt;parent = parent;</div><div class='add'>+	upd-&gt;preexisting = true;</div><div class='add'>+</div><div class='add'>+	if (wupd-&gt;num_used_entries == XE_VM_MAX_LEVEL * 2 + 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	entry = wupd-&gt;entries + wupd-&gt;num_used_entries++;</div><div class='add'>+	upd-&gt;update = entry;</div><div class='add'>+	entry-&gt;ofs = offset;</div><div class='add'>+	entry-&gt;pt_bo = parent-&gt;bo;</div><div class='add'>+	entry-&gt;pt = parent;</div><div class='add'>+	entry-&gt;flags = 0;</div><div class='add'>+	entry-&gt;qwords = 0;</div><div class='add'>+</div><div class='add'>+	if (alloc_entries) {</div><div class='add'>+		entry-&gt;pt_entries = kmalloc_array(XE_PDES,</div><div class='add'>+						  sizeof(*entry-&gt;pt_entries),</div><div class='add'>+						  GFP_KERNEL);</div><div class='add'>+		if (!entry-&gt;pt_entries)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * NOTE: This is a very frequently called function so we allow ourselves</div><div class='add'>+ * to annotate (using branch prediction hints) the fastpath of updating a</div><div class='add'>+ * non-pre-existing pagetable with leaf ptes.</div><div class='add'>+ */</div><div class='add'>+static int</div><div class='add'>+xe_pt_insert_entry(struct xe_pt_stage_bind_walk *xe_walk, struct xe_pt *parent,</div><div class='add'>+		   pgoff_t offset, struct xe_pt *xe_child, u64 pte)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_update *upd = &amp;xe_walk-&gt;wupd.updates[parent-&gt;level];</div><div class='add'>+	struct xe_pt_update *child_upd = xe_child ?</div><div class='add'>+		&amp;xe_walk-&gt;wupd.updates[xe_child-&gt;level] : NULL;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_pt_new_shared(&amp;xe_walk-&gt;wupd, parent, offset, true);</div><div class='add'>+	if (unlikely(ret))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Register this new pagetable so that it won't be recognized as</div><div class='add'>+	 * a shared pagetable by a subsequent insertion.</div><div class='add'>+	 */</div><div class='add'>+	if (unlikely(child_upd)) {</div><div class='add'>+		child_upd-&gt;update = NULL;</div><div class='add'>+		child_upd-&gt;parent = xe_child;</div><div class='add'>+		child_upd-&gt;preexisting = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (likely(!upd-&gt;preexisting)) {</div><div class='add'>+		/* Continue building a non-connected subtree. */</div><div class='add'>+		struct iosys_map *map = &amp;parent-&gt;bo-&gt;vmap;</div><div class='add'>+</div><div class='add'>+		if (unlikely(xe_child))</div><div class='add'>+			parent-&gt;base.dir-&gt;entries[offset] = &amp;xe_child-&gt;base;</div><div class='add'>+</div><div class='add'>+		xe_pt_write(xe_walk-&gt;vm-&gt;xe, map, offset, pte);</div><div class='add'>+		parent-&gt;num_live++;</div><div class='add'>+	} else {</div><div class='add'>+		/* Shared pt. Stage update. */</div><div class='add'>+		unsigned int idx;</div><div class='add'>+		struct xe_vm_pgtable_update *entry = upd-&gt;update;</div><div class='add'>+</div><div class='add'>+		idx = offset - entry-&gt;ofs;</div><div class='add'>+		entry-&gt;pt_entries[idx].pt = xe_child;</div><div class='add'>+		entry-&gt;pt_entries[idx].pte = pte;</div><div class='add'>+		entry-&gt;qwords++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_pt_hugepte_possible(u64 addr, u64 next, unsigned int level,</div><div class='add'>+				   struct xe_pt_stage_bind_walk *xe_walk)</div><div class='add'>+{</div><div class='add'>+	u64 size, dma;</div><div class='add'>+</div><div class='add'>+	if (level &gt; MAX_HUGEPTE_LEVEL)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Does the virtual range requested cover a huge pte? */</div><div class='add'>+	if (!xe_pt_covers(addr, next, level, &amp;xe_walk-&gt;base))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* Does the DMA segment cover the whole pte? */</div><div class='add'>+	if (next - xe_walk-&gt;va_curs_start &gt; xe_walk-&gt;curs-&gt;size)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* null VMA's do not have dma addresses */</div><div class='add'>+	if (xe_vma_is_null(xe_walk-&gt;vma))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* Is the DMA address huge PTE size aligned? */</div><div class='add'>+	size = next - addr;</div><div class='add'>+	dma = addr - xe_walk-&gt;va_curs_start + xe_res_dma(xe_walk-&gt;curs);</div><div class='add'>+</div><div class='add'>+	return IS_ALIGNED(dma, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Scan the requested mapping to check whether it can be done entirely</div><div class='add'>+ * with 64K PTEs.</div><div class='add'>+ */</div><div class='add'>+static bool</div><div class='add'>+xe_pt_scan_64K(u64 addr, u64 next, struct xe_pt_stage_bind_walk *xe_walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_res_cursor curs = *xe_walk-&gt;curs;</div><div class='add'>+</div><div class='add'>+	if (!IS_ALIGNED(addr, SZ_64K))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (next &gt; xe_walk-&gt;l0_end_addr)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	/* null VMA's do not have dma addresses */</div><div class='add'>+	if (xe_vma_is_null(xe_walk-&gt;vma))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	xe_res_next(&amp;curs, addr - xe_walk-&gt;va_curs_start);</div><div class='add'>+	for (; addr &lt; next; addr += SZ_64K) {</div><div class='add'>+		if (!IS_ALIGNED(xe_res_dma(&amp;curs), SZ_64K) || curs.size &lt; SZ_64K)</div><div class='add'>+			return false;</div><div class='add'>+</div><div class='add'>+		xe_res_next(&amp;curs, SZ_64K);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return addr == next;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * For non-compact "normal" 4K level-0 pagetables, we want to try to group</div><div class='add'>+ * addresses together in 64K-contigous regions to add a 64K TLB hint for the</div><div class='add'>+ * device to the PTE.</div><div class='add'>+ * This function determines whether the address is part of such a</div><div class='add'>+ * segment. For VRAM in normal pagetables, this is strictly necessary on</div><div class='add'>+ * some devices.</div><div class='add'>+ */</div><div class='add'>+static bool</div><div class='add'>+xe_pt_is_pte_ps64K(u64 addr, u64 next, struct xe_pt_stage_bind_walk *xe_walk)</div><div class='add'>+{</div><div class='add'>+	/* Address is within an already found 64k region */</div><div class='add'>+	if (xe_walk-&gt;found_64K &amp;&amp; addr - xe_walk-&gt;addr_64K &lt; SZ_64K)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	xe_walk-&gt;found_64K = xe_pt_scan_64K(addr, addr + SZ_64K, xe_walk);</div><div class='add'>+	xe_walk-&gt;addr_64K = addr;</div><div class='add'>+</div><div class='add'>+	return xe_walk-&gt;found_64K;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,</div><div class='add'>+		       unsigned int level, u64 addr, u64 next,</div><div class='add'>+		       struct xe_ptw **child,</div><div class='add'>+		       enum page_walk_action *action,</div><div class='add'>+		       struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_stage_bind_walk *xe_walk =</div><div class='add'>+		container_of(walk, typeof(*xe_walk), base);</div><div class='add'>+	u16 pat_index = xe_walk-&gt;vma-&gt;pat_index;</div><div class='add'>+	struct xe_pt *xe_parent = container_of(parent, typeof(*xe_parent), base);</div><div class='add'>+	struct xe_vm *vm = xe_walk-&gt;vm;</div><div class='add'>+	struct xe_pt *xe_child;</div><div class='add'>+	bool covers;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u64 pte;</div><div class='add'>+</div><div class='add'>+	/* Is this a leaf entry ?*/</div><div class='add'>+	if (level == 0 || xe_pt_hugepte_possible(addr, next, level, xe_walk)) {</div><div class='add'>+		struct xe_res_cursor *curs = xe_walk-&gt;curs;</div><div class='add'>+		bool is_null = xe_vma_is_null(xe_walk-&gt;vma);</div><div class='add'>+</div><div class='add'>+		XE_WARN_ON(xe_walk-&gt;va_curs_start != addr);</div><div class='add'>+</div><div class='add'>+		pte = vm-&gt;pt_ops-&gt;pte_encode_vma(is_null ? 0 :</div><div class='add'>+						 xe_res_dma(curs) + xe_walk-&gt;dma_offset,</div><div class='add'>+						 xe_walk-&gt;vma, pat_index, level);</div><div class='add'>+		pte |= xe_walk-&gt;default_pte;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Set the XE_PTE_PS64 hint if possible, otherwise if</div><div class='add'>+		 * this device *requires* 64K PTE size for VRAM, fail.</div><div class='add'>+		 */</div><div class='add'>+		if (level == 0 &amp;&amp; !xe_parent-&gt;is_compact) {</div><div class='add'>+			if (xe_pt_is_pte_ps64K(addr, next, xe_walk))</div><div class='add'>+				pte |= XE_PTE_PS64;</div><div class='add'>+			else if (XE_WARN_ON(xe_walk-&gt;needs_64K))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = xe_pt_insert_entry(xe_walk, xe_parent, offset, NULL, pte);</div><div class='add'>+		if (unlikely(ret))</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		if (!is_null)</div><div class='add'>+			xe_res_next(curs, next - addr);</div><div class='add'>+		xe_walk-&gt;va_curs_start = next;</div><div class='add'>+		xe_walk-&gt;vma-&gt;gpuva.flags |= (XE_VMA_PTE_4K &lt;&lt; level);</div><div class='add'>+		*action = ACTION_CONTINUE;</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Descending to lower level. Determine if we need to allocate a</div><div class='add'>+	 * new page table or -directory, which we do if there is no</div><div class='add'>+	 * previous one or there is one we can completely replace.</div><div class='add'>+	 */</div><div class='add'>+	if (level == 1) {</div><div class='add'>+		walk-&gt;shifts = xe_normal_pt_shifts;</div><div class='add'>+		xe_walk-&gt;l0_end_addr = next;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	covers = xe_pt_covers(addr, next, level, &amp;xe_walk-&gt;base);</div><div class='add'>+	if (covers || !*child) {</div><div class='add'>+		u64 flags = 0;</div><div class='add'>+</div><div class='add'>+		xe_child = xe_pt_create(xe_walk-&gt;vm, xe_walk-&gt;tile, level - 1);</div><div class='add'>+		if (IS_ERR(xe_child))</div><div class='add'>+			return PTR_ERR(xe_child);</div><div class='add'>+</div><div class='add'>+		xe_pt_set_addr(xe_child,</div><div class='add'>+			       round_down(addr, 1ull &lt;&lt; walk-&gt;shifts[level]));</div><div class='add'>+</div><div class='add'>+		if (!covers)</div><div class='add'>+			xe_pt_populate_empty(xe_walk-&gt;tile, xe_walk-&gt;vm, xe_child);</div><div class='add'>+</div><div class='add'>+		*child = &amp;xe_child-&gt;base;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Prefer the compact pagetable layout for L0 if possible.</div><div class='add'>+		 * TODO: Suballocate the pt bo to avoid wasting a lot of</div><div class='add'>+		 * memory.</div><div class='add'>+		 */</div><div class='add'>+		if (GRAPHICS_VERx100(tile_to_xe(xe_walk-&gt;tile)) &gt;= 1250 &amp;&amp; level == 1 &amp;&amp;</div><div class='add'>+		    covers &amp;&amp; xe_pt_scan_64K(addr, next, xe_walk)) {</div><div class='add'>+			walk-&gt;shifts = xe_compact_pt_shifts;</div><div class='add'>+			flags |= XE_PDE_64K;</div><div class='add'>+			xe_child-&gt;is_compact = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pte = vm-&gt;pt_ops-&gt;pde_encode_bo(xe_child-&gt;bo, 0, pat_index) | flags;</div><div class='add'>+		ret = xe_pt_insert_entry(xe_walk, xe_parent, offset, xe_child,</div><div class='add'>+					 pte);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*action = ACTION_SUBTREE;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pt_walk_ops xe_pt_stage_bind_ops = {</div><div class='add'>+	.pt_entry = xe_pt_stage_bind_entry,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_stage_bind() - Build a disconnected page-table tree for a given address</div><div class='add'>+ * range.</div><div class='add'>+ * @tile: The tile we're building for.</div><div class='add'>+ * @vma: The vma indicating the address range.</div><div class='add'>+ * @entries: Storage for the update entries used for connecting the tree to</div><div class='add'>+ * the main tree at commit time.</div><div class='add'>+ * @num_entries: On output contains the number of @entries used.</div><div class='add'>+ *</div><div class='add'>+ * This function builds a disconnected page-table tree for a given address</div><div class='add'>+ * range. The tree is connected to the main vm tree for the gpu using</div><div class='add'>+ * xe_migrate_update_pgtables() and for the cpu using xe_pt_commit_bind().</div><div class='add'>+ * The function builds xe_vm_pgtable_update structures for already existing</div><div class='add'>+ * shared page-tables, and non-existing shared and non-shared page-tables</div><div class='add'>+ * are built and populated directly.</div><div class='add'>+ *</div><div class='add'>+ * Return 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+static int</div><div class='add'>+xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,</div><div class='add'>+		 struct xe_vm_pgtable_update *entries, u32 *num_entries)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_bo *bo = xe_vma_bo(vma);</div><div class='add'>+	bool is_devmem = !xe_vma_is_userptr(vma) &amp;&amp; bo &amp;&amp;</div><div class='add'>+		(xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo));</div><div class='add'>+	struct xe_res_cursor curs;</div><div class='add'>+	struct xe_pt_stage_bind_walk xe_walk = {</div><div class='add'>+		.base = {</div><div class='add'>+			.ops = &amp;xe_pt_stage_bind_ops,</div><div class='add'>+			.shifts = xe_normal_pt_shifts,</div><div class='add'>+			.max_level = XE_PT_HIGHEST_LEVEL,</div><div class='add'>+		},</div><div class='add'>+		.vm = xe_vma_vm(vma),</div><div class='add'>+		.tile = tile,</div><div class='add'>+		.curs = &amp;curs,</div><div class='add'>+		.va_curs_start = xe_vma_start(vma),</div><div class='add'>+		.vma = vma,</div><div class='add'>+		.wupd.entries = entries,</div><div class='add'>+		.needs_64K = (xe_vma_vm(vma)-&gt;flags &amp; XE_VM_FLAG_64K) &amp;&amp; is_devmem,</div><div class='add'>+	};</div><div class='add'>+	struct xe_pt *pt = xe_vma_vm(vma)-&gt;pt_root[tile-&gt;id];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (vma &amp;&amp; (vma-&gt;gpuva.flags &amp; XE_VMA_ATOMIC_PTE_BIT) &amp;&amp;</div><div class='add'>+	    (is_devmem || !IS_DGFX(xe)))</div><div class='add'>+		xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;</div><div class='add'>+</div><div class='add'>+	if (is_devmem) {</div><div class='add'>+		xe_walk.default_pte |= XE_PPGTT_PTE_DM;</div><div class='add'>+		xe_walk.dma_offset = vram_region_gpu_offset(bo-&gt;ttm.resource);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!xe_vma_has_no_bo(vma) &amp;&amp; xe_bo_is_stolen(bo))</div><div class='add'>+		xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (!xe_vma_is_null(vma)) {</div><div class='add'>+		if (xe_vma_is_userptr(vma))</div><div class='add'>+			xe_res_first_sg(vma-&gt;userptr.sg, 0, xe_vma_size(vma),</div><div class='add'>+					&amp;curs);</div><div class='add'>+		else if (xe_bo_is_vram(bo) || xe_bo_is_stolen(bo))</div><div class='add'>+			xe_res_first(bo-&gt;ttm.resource, xe_vma_bo_offset(vma),</div><div class='add'>+				     xe_vma_size(vma), &amp;curs);</div><div class='add'>+		else</div><div class='add'>+			xe_res_first_sg(xe_bo_sg(bo), xe_vma_bo_offset(vma),</div><div class='add'>+					xe_vma_size(vma), &amp;curs);</div><div class='add'>+	} else {</div><div class='add'>+		curs.size = xe_vma_size(vma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = xe_pt_walk_range(&amp;pt-&gt;base, pt-&gt;level, xe_vma_start(vma),</div><div class='add'>+			       xe_vma_end(vma), &amp;xe_walk.base);</div><div class='add'>+</div><div class='add'>+	*num_entries = xe_walk.wupd.num_used_entries;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_nonshared_offsets() - Determine the non-shared entry offsets of a</div><div class='add'>+ * shared pagetable.</div><div class='add'>+ * @addr: The start address within the non-shared pagetable.</div><div class='add'>+ * @end: The end address within the non-shared pagetable.</div><div class='add'>+ * @level: The level of the non-shared pagetable.</div><div class='add'>+ * @walk: Walk info. The function adjusts the walk action.</div><div class='add'>+ * @action: next action to perform (see enum page_walk_action)</div><div class='add'>+ * @offset: Ignored on input, First non-shared entry on output.</div><div class='add'>+ * @end_offset: Ignored on input, Last non-shared entry + 1 on output.</div><div class='add'>+ *</div><div class='add'>+ * A non-shared page-table has some entries that belong to the address range</div><div class='add'>+ * and others that don't. This function determines the entries that belong</div><div class='add'>+ * fully to the address range. Depending on level, some entries may</div><div class='add'>+ * partially belong to the address range (that can't happen at level 0).</div><div class='add'>+ * The function detects that and adjust those offsets to not include those</div><div class='add'>+ * partial entries. Iff it does detect partial entries, we know that there must</div><div class='add'>+ * be shared page tables also at lower levels, so it adjusts the walk action</div><div class='add'>+ * accordingly.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if there were non-shared entries, false otherwise.</div><div class='add'>+ */</div><div class='add'>+static bool xe_pt_nonshared_offsets(u64 addr, u64 end, unsigned int level,</div><div class='add'>+				    struct xe_pt_walk *walk,</div><div class='add'>+				    enum page_walk_action *action,</div><div class='add'>+				    pgoff_t *offset, pgoff_t *end_offset)</div><div class='add'>+{</div><div class='add'>+	u64 size = 1ull &lt;&lt; walk-&gt;shifts[level];</div><div class='add'>+</div><div class='add'>+	*offset = xe_pt_offset(addr, level, walk);</div><div class='add'>+	*end_offset = xe_pt_num_entries(addr, end, level, walk) + *offset;</div><div class='add'>+</div><div class='add'>+	if (!level)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If addr or next are not size aligned, there are shared pts at lower</div><div class='add'>+	 * level, so in that case traverse down the subtree</div><div class='add'>+	 */</div><div class='add'>+	*action = ACTION_CONTINUE;</div><div class='add'>+	if (!IS_ALIGNED(addr, size)) {</div><div class='add'>+		*action = ACTION_SUBTREE;</div><div class='add'>+		(*offset)++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!IS_ALIGNED(end, size)) {</div><div class='add'>+		*action = ACTION_SUBTREE;</div><div class='add'>+		(*end_offset)--;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return *end_offset &gt; *offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_pt_zap_ptes_walk {</div><div class='add'>+	/** @base: The walk base-class */</div><div class='add'>+	struct xe_pt_walk base;</div><div class='add'>+</div><div class='add'>+	/* Input parameters for the walk */</div><div class='add'>+	/** @tile: The tile we're building for */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	/* Output */</div><div class='add'>+	/** @needs_invalidate: Whether we need to invalidate TLB*/</div><div class='add'>+	bool needs_invalidate;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int xe_pt_zap_ptes_entry(struct xe_ptw *parent, pgoff_t offset,</div><div class='add'>+				unsigned int level, u64 addr, u64 next,</div><div class='add'>+				struct xe_ptw **child,</div><div class='add'>+				enum page_walk_action *action,</div><div class='add'>+				struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_zap_ptes_walk *xe_walk =</div><div class='add'>+		container_of(walk, typeof(*xe_walk), base);</div><div class='add'>+	struct xe_pt *xe_child = container_of(*child, typeof(*xe_child), base);</div><div class='add'>+	pgoff_t end_offset;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!*child);</div><div class='add'>+	XE_WARN_ON(!level &amp;&amp; xe_child-&gt;is_compact);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note that we're called from an entry callback, and we're dealing</div><div class='add'>+	 * with the child of that entry rather than the parent, so need to</div><div class='add'>+	 * adjust level down.</div><div class='add'>+	 */</div><div class='add'>+	if (xe_pt_nonshared_offsets(addr, next, --level, walk, action, &amp;offset,</div><div class='add'>+				    &amp;end_offset)) {</div><div class='add'>+		xe_map_memset(tile_to_xe(xe_walk-&gt;tile), &amp;xe_child-&gt;bo-&gt;vmap,</div><div class='add'>+			      offset * sizeof(u64), 0,</div><div class='add'>+			      (end_offset - offset) * sizeof(u64));</div><div class='add'>+		xe_walk-&gt;needs_invalidate = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {</div><div class='add'>+	.pt_entry = xe_pt_zap_ptes_entry,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_zap_ptes() - Zap (zero) gpu ptes of an address range</div><div class='add'>+ * @tile: The tile we're zapping for.</div><div class='add'>+ * @vma: GPU VMA detailing address range.</div><div class='add'>+ *</div><div class='add'>+ * Eviction and Userptr invalidation needs to be able to zap the</div><div class='add'>+ * gpu ptes of a given address range in pagefaulting mode.</div><div class='add'>+ * In order to be able to do that, that function needs access to the shared</div><div class='add'>+ * page-table entrieaso it can either clear the leaf PTEs or</div><div class='add'>+ * clear the pointers to lower-level page-tables. The caller is required</div><div class='add'>+ * to hold the necessary locks to ensure neither the page-table connectivity</div><div class='add'>+ * nor the page-table entries of the range is updated from under us.</div><div class='add'>+ *</div><div class='add'>+ * Return: Whether ptes were actually updated and a TLB invalidation is</div><div class='add'>+ * required.</div><div class='add'>+ */</div><div class='add'>+bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_zap_ptes_walk xe_walk = {</div><div class='add'>+		.base = {</div><div class='add'>+			.ops = &amp;xe_pt_zap_ptes_ops,</div><div class='add'>+			.shifts = xe_normal_pt_shifts,</div><div class='add'>+			.max_level = XE_PT_HIGHEST_LEVEL,</div><div class='add'>+		},</div><div class='add'>+		.tile = tile,</div><div class='add'>+	};</div><div class='add'>+	struct xe_pt *pt = xe_vma_vm(vma)-&gt;pt_root[tile-&gt;id];</div><div class='add'>+</div><div class='add'>+	if (!(vma-&gt;tile_present &amp; BIT(tile-&gt;id)))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	(void)xe_pt_walk_shared(&amp;pt-&gt;base, pt-&gt;level, xe_vma_start(vma),</div><div class='add'>+				xe_vma_end(vma), &amp;xe_walk.base);</div><div class='add'>+</div><div class='add'>+	return xe_walk.needs_invalidate;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_tile *tile,</div><div class='add'>+		       struct iosys_map *map, void *data,</div><div class='add'>+		       u32 qword_ofs, u32 num_qwords,</div><div class='add'>+		       const struct xe_vm_pgtable_update *update)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_entry *ptes = update-&gt;pt_entries;</div><div class='add'>+	u64 *ptr = data;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_qwords; i++) {</div><div class='add'>+		if (map)</div><div class='add'>+			xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *</div><div class='add'>+				  sizeof(u64), u64, ptes[i].pte);</div><div class='add'>+		else</div><div class='add'>+			ptr[i] = ptes[i].pte;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pt_abort_bind(struct xe_vma *vma,</div><div class='add'>+			     struct xe_vm_pgtable_update *entries,</div><div class='add'>+			     u32 num_entries)</div><div class='add'>+{</div><div class='add'>+	u32 i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		if (!entries[i].pt_entries)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; entries[i].qwords; j++)</div><div class='add'>+			xe_pt_destroy(entries[i].pt_entries[j].pt, xe_vma_vm(vma)-&gt;flags, NULL);</div><div class='add'>+		kfree(entries[i].pt_entries);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pt_commit_locks_assert(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma))</div><div class='add'>+		lockdep_assert_held_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	else if (!xe_vma_is_null(vma))</div><div class='add'>+		dma_resv_assert_held(xe_vma_bo(vma)-&gt;ttm.base.resv);</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pt_commit_bind(struct xe_vma *vma,</div><div class='add'>+			      struct xe_vm_pgtable_update *entries,</div><div class='add'>+			      u32 num_entries, bool rebind,</div><div class='add'>+			      struct llist_head *deferred)</div><div class='add'>+{</div><div class='add'>+	u32 i, j;</div><div class='add'>+</div><div class='add'>+	xe_pt_commit_locks_assert(vma);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		struct xe_pt *pt = entries[i].pt;</div><div class='add'>+		struct xe_pt_dir *pt_dir;</div><div class='add'>+</div><div class='add'>+		if (!rebind)</div><div class='add'>+			pt-&gt;num_live += entries[i].qwords;</div><div class='add'>+</div><div class='add'>+		if (!pt-&gt;level) {</div><div class='add'>+			kfree(entries[i].pt_entries);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pt_dir = as_xe_pt_dir(pt);</div><div class='add'>+		for (j = 0; j &lt; entries[i].qwords; j++) {</div><div class='add'>+			u32 j_ = j + entries[i].ofs;</div><div class='add'>+			struct xe_pt *newpte = entries[i].pt_entries[j].pt;</div><div class='add'>+</div><div class='add'>+			if (xe_pt_entry(pt_dir, j_))</div><div class='add'>+				xe_pt_destroy(xe_pt_entry(pt_dir, j_),</div><div class='add'>+					      xe_vma_vm(vma)-&gt;flags, deferred);</div><div class='add'>+</div><div class='add'>+			pt_dir-&gt;dir.entries[j_] = &amp;newpte-&gt;base;</div><div class='add'>+		}</div><div class='add'>+		kfree(entries[i].pt_entries);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_pt_prepare_bind(struct xe_tile *tile, struct xe_vma *vma,</div><div class='add'>+		   struct xe_vm_pgtable_update *entries, u32 *num_entries,</div><div class='add'>+		   bool rebind)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	*num_entries = 0;</div><div class='add'>+	err = xe_pt_stage_bind(tile, vma, entries, num_entries);</div><div class='add'>+	if (!err)</div><div class='add'>+		xe_tile_assert(tile, *num_entries);</div><div class='add'>+	else /* abort! */</div><div class='add'>+		xe_pt_abort_bind(vma, entries, *num_entries);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_dbg_print_entries(struct xe_device *xe,</div><div class='add'>+				    const struct xe_vm_pgtable_update *entries,</div><div class='add'>+				    unsigned int num_entries)</div><div class='add'>+#if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM))</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	vm_dbg(&amp;xe-&gt;drm, "%u entries to update\n", num_entries);</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		const struct xe_vm_pgtable_update *entry = &amp;entries[i];</div><div class='add'>+		struct xe_pt *xe_pt = entry-&gt;pt;</div><div class='add'>+		u64 page_size = 1ull &lt;&lt; xe_pt_shift(xe_pt-&gt;level);</div><div class='add'>+		u64 end;</div><div class='add'>+		u64 start;</div><div class='add'>+</div><div class='add'>+		xe_assert(xe, !entry-&gt;pt-&gt;is_compact);</div><div class='add'>+		start = entry-&gt;ofs * page_size;</div><div class='add'>+		end = start + page_size * entry-&gt;qwords;</div><div class='add'>+		vm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+		       "\t%u: Update level %u at (%u + %u) [%llx...%llx) f:%x\n",</div><div class='add'>+		       i, xe_pt-&gt;level, entry-&gt;ofs, entry-&gt;qwords,</div><div class='add'>+		       xe_pt_addr(xe_pt) + start, xe_pt_addr(xe_pt) + end, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+{}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_DRM_XE_USERPTR_INVAL_INJECT</div><div class='add'>+</div><div class='add'>+static int xe_pt_userptr_inject_eagain(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	u32 divisor = vma-&gt;userptr.divisor ? vma-&gt;userptr.divisor : 2;</div><div class='add'>+	static u32 count;</div><div class='add'>+</div><div class='add'>+	if (count++ % divisor == divisor - 1) {</div><div class='add'>+		struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+</div><div class='add'>+		vma-&gt;userptr.divisor = divisor &lt;&lt; 1;</div><div class='add'>+		spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		list_move_tail(&amp;vma-&gt;userptr.invalidate_link,</div><div class='add'>+			       &amp;vm-&gt;userptr.invalidated);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#else</div><div class='add'>+</div><div class='add'>+static bool xe_pt_userptr_inject_eagain(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_pt_migrate_pt_update - Callback argument for pre-commit callbacks</div><div class='add'>+ * @base: Base we derive from.</div><div class='add'>+ * @bind: Whether this is a bind or an unbind operation. A bind operation</div><div class='add'>+ *        makes the pre-commit callback error with -EAGAIN if it detects a</div><div class='add'>+ *        pending invalidation.</div><div class='add'>+ * @locked: Whether the pre-commit callback locked the userptr notifier lock</div><div class='add'>+ *          and it needs unlocking.</div><div class='add'>+ */</div><div class='add'>+struct xe_pt_migrate_pt_update {</div><div class='add'>+	struct xe_migrate_pt_update base;</div><div class='add'>+	bool bind;</div><div class='add'>+	bool locked;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This function adds the needed dependencies to a page-table update job</div><div class='add'>+ * to make sure racing jobs for separate bind engines don't race writing</div><div class='add'>+ * to the same page-table range, wreaking havoc. Initially use a single</div><div class='add'>+ * fence for the entire VM. An optimization would use smaller granularity.</div><div class='add'>+ */</div><div class='add'>+static int xe_pt_vm_dependencies(struct xe_sched_job *job,</div><div class='add'>+				 struct xe_range_fence_tree *rftree,</div><div class='add'>+				 u64 start, u64 last)</div><div class='add'>+{</div><div class='add'>+	struct xe_range_fence *rtfence;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	rtfence = xe_range_fence_tree_first(rftree, start, last);</div><div class='add'>+	while (rtfence) {</div><div class='add'>+		fence = rtfence-&gt;fence;</div><div class='add'>+</div><div class='add'>+		if (!dma_fence_is_signaled(fence)) {</div><div class='add'>+			/*</div><div class='add'>+			 * Is this a CPU update? GPU is busy updating, so return</div><div class='add'>+			 * an error</div><div class='add'>+			 */</div><div class='add'>+			if (!job)</div><div class='add'>+				return -ETIME;</div><div class='add'>+</div><div class='add'>+			dma_fence_get(fence);</div><div class='add'>+			err = drm_sched_job_add_dependency(&amp;job-&gt;drm, fence);</div><div class='add'>+			if (err)</div><div class='add'>+				return err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		rtfence = xe_range_fence_tree_next(rtfence, start, last);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pt_pre_commit(struct xe_migrate_pt_update *pt_update)</div><div class='add'>+{</div><div class='add'>+	struct xe_range_fence_tree *rftree =</div><div class='add'>+		&amp;xe_vma_vm(pt_update-&gt;vma)-&gt;rftree[pt_update-&gt;tile_id];</div><div class='add'>+</div><div class='add'>+	return xe_pt_vm_dependencies(pt_update-&gt;job, rftree,</div><div class='add'>+				     pt_update-&gt;start, pt_update-&gt;last);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pt_userptr_pre_commit(struct xe_migrate_pt_update *pt_update)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_migrate_pt_update *userptr_update =</div><div class='add'>+		container_of(pt_update, typeof(*userptr_update), base);</div><div class='add'>+	struct xe_vma *vma = pt_update-&gt;vma;</div><div class='add'>+	unsigned long notifier_seq = vma-&gt;userptr.notifier_seq;</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	int err = xe_pt_vm_dependencies(pt_update-&gt;job,</div><div class='add'>+					&amp;vm-&gt;rftree[pt_update-&gt;tile_id],</div><div class='add'>+					pt_update-&gt;start,</div><div class='add'>+					pt_update-&gt;last);</div><div class='add'>+</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	userptr_update-&gt;locked = false;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wait until nobody is running the invalidation notifier, and</div><div class='add'>+	 * since we're exiting the loop holding the notifier lock,</div><div class='add'>+	 * nobody can proceed invalidating either.</div><div class='add'>+	 *</div><div class='add'>+	 * Note that we don't update the vma-&gt;userptr.notifier_seq since</div><div class='add'>+	 * we don't update the userptr pages.</div><div class='add'>+	 */</div><div class='add'>+	do {</div><div class='add'>+		down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		if (!mmu_interval_read_retry(&amp;vma-&gt;userptr.notifier,</div><div class='add'>+					     notifier_seq))</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+		if (userptr_update-&gt;bind)</div><div class='add'>+			return -EAGAIN;</div><div class='add'>+</div><div class='add'>+		notifier_seq = mmu_interval_read_begin(&amp;vma-&gt;userptr.notifier);</div><div class='add'>+	} while (true);</div><div class='add'>+</div><div class='add'>+	/* Inject errors to test_whether they are handled correctly */</div><div class='add'>+	if (userptr_update-&gt;bind &amp;&amp; xe_pt_userptr_inject_eagain(vma)) {</div><div class='add'>+		up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	userptr_update-&gt;locked = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_migrate_pt_update_ops bind_ops = {</div><div class='add'>+	.populate = xe_vm_populate_pgtable,</div><div class='add'>+	.pre_commit = xe_pt_pre_commit,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_migrate_pt_update_ops userptr_bind_ops = {</div><div class='add'>+	.populate = xe_vm_populate_pgtable,</div><div class='add'>+	.pre_commit = xe_pt_userptr_pre_commit,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct invalidation_fence {</div><div class='add'>+	struct xe_gt_tlb_invalidation_fence base;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct dma_fence_cb cb;</div><div class='add'>+	struct work_struct work;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+invalidation_fence_get_driver_name(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	return "xe";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *</div><div class='add'>+invalidation_fence_get_timeline_name(struct dma_fence *dma_fence)</div><div class='add'>+{</div><div class='add'>+	return "invalidation_fence";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dma_fence_ops invalidation_fence_ops = {</div><div class='add'>+	.get_driver_name = invalidation_fence_get_driver_name,</div><div class='add'>+	.get_timeline_name = invalidation_fence_get_timeline_name,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void invalidation_fence_cb(struct dma_fence *fence,</div><div class='add'>+				  struct dma_fence_cb *cb)</div><div class='add'>+{</div><div class='add'>+	struct invalidation_fence *ifence =</div><div class='add'>+		container_of(cb, struct invalidation_fence, cb);</div><div class='add'>+</div><div class='add'>+	trace_xe_gt_tlb_invalidation_fence_cb(&amp;ifence-&gt;base);</div><div class='add'>+	if (!ifence-&gt;fence-&gt;error) {</div><div class='add'>+		queue_work(system_wq, &amp;ifence-&gt;work);</div><div class='add'>+	} else {</div><div class='add'>+		ifence-&gt;base.base.error = ifence-&gt;fence-&gt;error;</div><div class='add'>+		dma_fence_signal(&amp;ifence-&gt;base.base);</div><div class='add'>+		dma_fence_put(&amp;ifence-&gt;base.base);</div><div class='add'>+	}</div><div class='add'>+	dma_fence_put(ifence-&gt;fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void invalidation_fence_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct invalidation_fence *ifence =</div><div class='add'>+		container_of(w, struct invalidation_fence, work);</div><div class='add'>+</div><div class='add'>+	trace_xe_gt_tlb_invalidation_fence_work_func(&amp;ifence-&gt;base);</div><div class='add'>+	xe_gt_tlb_invalidation_vma(ifence-&gt;gt, &amp;ifence-&gt;base, ifence-&gt;vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int invalidation_fence_init(struct xe_gt *gt,</div><div class='add'>+				   struct invalidation_fence *ifence,</div><div class='add'>+				   struct dma_fence *fence,</div><div class='add'>+				   struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	trace_xe_gt_tlb_invalidation_fence_create(&amp;ifence-&gt;base);</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;gt-&gt;tlb_invalidation.lock);</div><div class='add'>+	dma_fence_init(&amp;ifence-&gt;base.base, &amp;invalidation_fence_ops,</div><div class='add'>+		       &amp;gt-&gt;tlb_invalidation.lock,</div><div class='add'>+		       gt-&gt;tlb_invalidation.fence_context,</div><div class='add'>+		       ++gt-&gt;tlb_invalidation.fence_seqno);</div><div class='add'>+	spin_unlock_irq(&amp;gt-&gt;tlb_invalidation.lock);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;ifence-&gt;base.link);</div><div class='add'>+</div><div class='add'>+	dma_fence_get(&amp;ifence-&gt;base.base);	/* Ref for caller */</div><div class='add'>+	ifence-&gt;fence = fence;</div><div class='add'>+	ifence-&gt;gt = gt;</div><div class='add'>+	ifence-&gt;vma = vma;</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;ifence-&gt;work, invalidation_fence_work_func);</div><div class='add'>+	ret = dma_fence_add_callback(fence, &amp;ifence-&gt;cb, invalidation_fence_cb);</div><div class='add'>+	if (ret == -ENOENT) {</div><div class='add'>+		dma_fence_put(ifence-&gt;fence);	/* Usually dropped in CB */</div><div class='add'>+		invalidation_fence_work_func(&amp;ifence-&gt;work);</div><div class='add'>+	} else if (ret) {</div><div class='add'>+		dma_fence_put(&amp;ifence-&gt;base.base);	/* Caller ref */</div><div class='add'>+		dma_fence_put(&amp;ifence-&gt;base.base);	/* Creation ref */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, !ret || ret == -ENOENT);</div><div class='add'>+</div><div class='add'>+	return ret &amp;&amp; ret != -ENOENT ? ret : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_pt_calc_rfence_interval(struct xe_vma *vma,</div><div class='add'>+				       struct xe_pt_migrate_pt_update *update,</div><div class='add'>+				       struct xe_vm_pgtable_update *entries,</div><div class='add'>+				       u32 num_entries)</div><div class='add'>+{</div><div class='add'>+	int i, level = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		const struct xe_vm_pgtable_update *entry = &amp;entries[i];</div><div class='add'>+</div><div class='add'>+		if (entry-&gt;pt-&gt;level &gt; level)</div><div class='add'>+			level = entry-&gt;pt-&gt;level;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Greedy (non-optimal) calculation but simple */</div><div class='add'>+	update-&gt;base.start = ALIGN_DOWN(xe_vma_start(vma),</div><div class='add'>+					0x1ull &lt;&lt; xe_pt_shift(level));</div><div class='add'>+	update-&gt;base.last = ALIGN(xe_vma_end(vma),</div><div class='add'>+				  0x1ull &lt;&lt; xe_pt_shift(level)) - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __xe_pt_bind_vma() - Build and connect a page-table tree for the vma</div><div class='add'>+ * address range.</div><div class='add'>+ * @tile: The tile to bind for.</div><div class='add'>+ * @vma: The vma to bind.</div><div class='add'>+ * @q: The exec_queue with which to do pipelined page-table updates.</div><div class='add'>+ * @syncs: Entries to sync on before binding the built tree to the live vm tree.</div><div class='add'>+ * @num_syncs: Number of @sync entries.</div><div class='add'>+ * @rebind: Whether we're rebinding this vma to the same address range without</div><div class='add'>+ * an unbind in-between.</div><div class='add'>+ *</div><div class='add'>+ * This function builds a page-table tree (see xe_pt_stage_bind() for more</div><div class='add'>+ * information on page-table building), and the xe_vm_pgtable_update entries</div><div class='add'>+ * abstracting the operations needed to attach it to the main vm tree. It</div><div class='add'>+ * then takes the relevant locks and updates the metadata side of the main</div><div class='add'>+ * vm tree and submits the operations for pipelined attachment of the</div><div class='add'>+ * gpu page-table to the vm main tree, (which can be done either by the</div><div class='add'>+ * cpu and the GPU).</div><div class='add'>+ *</div><div class='add'>+ * Return: A valid dma-fence representing the pipelined attachment operation</div><div class='add'>+ * on success, an error pointer on error.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		 struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+		 bool rebind)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1];</div><div class='add'>+	struct xe_pt_migrate_pt_update bind_pt_update = {</div><div class='add'>+		.base = {</div><div class='add'>+			.ops = xe_vma_is_userptr(vma) ? &amp;userptr_bind_ops : &amp;bind_ops,</div><div class='add'>+			.vma = vma,</div><div class='add'>+			.tile_id = tile-&gt;id,</div><div class='add'>+		},</div><div class='add'>+		.bind = true,</div><div class='add'>+	};</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	u32 num_entries;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct invalidation_fence *ifence = NULL;</div><div class='add'>+	struct xe_range_fence *rfence;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	bind_pt_update.locked = false;</div><div class='add'>+	xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	vm_dbg(&amp;xe_vma_vm(vma)-&gt;xe-&gt;drm,</div><div class='add'>+	       "Preparing bind, with range [%llx...%llx) engine %p.\n",</div><div class='add'>+	       xe_vma_start(vma), xe_vma_end(vma), q);</div><div class='add'>+</div><div class='add'>+	err = xe_pt_prepare_bind(tile, vma, entries, &amp;num_entries, rebind);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err;</div><div class='add'>+	xe_tile_assert(tile, num_entries &lt;= ARRAY_SIZE(entries));</div><div class='add'>+</div><div class='add'>+	xe_vm_dbg_print_entries(tile_to_xe(tile), entries, num_entries);</div><div class='add'>+	xe_pt_calc_rfence_interval(vma, &amp;bind_pt_update, entries,</div><div class='add'>+				   num_entries);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If rebind, we have to invalidate TLB on !LR vms to invalidate</div><div class='add'>+	 * cached PTEs point to freed memory. on LR vms this is done</div><div class='add'>+	 * automatically when the context is re-enabled by the rebind worker,</div><div class='add'>+	 * or in fault mode it was invalidated on PTE zapping.</div><div class='add'>+	 *</div><div class='add'>+	 * If !rebind, and scratch enabled VMs, there is a chance the scratch</div><div class='add'>+	 * PTE is already cached in the TLB so it needs to be invalidated.</div><div class='add'>+	 * on !LR VMs this is done in the ring ops preceding a batch, but on</div><div class='add'>+	 * non-faulting LR, in particular on user-space batch buffer chaining,</div><div class='add'>+	 * it needs to be done here.</div><div class='add'>+	 */</div><div class='add'>+	if ((rebind &amp;&amp; !xe_vm_in_lr_mode(vm) &amp;&amp; !vm-&gt;batch_invalidate_tlb) ||</div><div class='add'>+	    (!rebind &amp;&amp; xe_vm_has_scratch(vm) &amp;&amp; xe_vm_in_preempt_fence_mode(vm))) {</div><div class='add'>+		ifence = kzalloc(sizeof(*ifence), GFP_KERNEL);</div><div class='add'>+		if (!ifence)</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rfence = kzalloc(sizeof(*rfence), GFP_KERNEL);</div><div class='add'>+	if (!rfence) {</div><div class='add'>+		kfree(ifence);</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fence = xe_migrate_update_pgtables(tile-&gt;migrate,</div><div class='add'>+					   vm, xe_vma_bo(vma), q,</div><div class='add'>+					   entries, num_entries,</div><div class='add'>+					   syncs, num_syncs,</div><div class='add'>+					   &amp;bind_pt_update.base);</div><div class='add'>+	if (!IS_ERR(fence)) {</div><div class='add'>+		bool last_munmap_rebind = vma-&gt;gpuva.flags &amp; XE_VMA_LAST_REBIND;</div><div class='add'>+		LLIST_HEAD(deferred);</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		err = xe_range_fence_insert(&amp;vm-&gt;rftree[tile-&gt;id], rfence,</div><div class='add'>+					    &amp;xe_range_fence_kfree_ops,</div><div class='add'>+					    bind_pt_update.base.start,</div><div class='add'>+					    bind_pt_update.base.last, fence);</div><div class='add'>+		if (err)</div><div class='add'>+			dma_fence_wait(fence, false);</div><div class='add'>+</div><div class='add'>+		/* TLB invalidation must be done before signaling rebind */</div><div class='add'>+		if (ifence) {</div><div class='add'>+			int err = invalidation_fence_init(tile-&gt;primary_gt, ifence, fence,</div><div class='add'>+							  vma);</div><div class='add'>+			if (err) {</div><div class='add'>+				dma_fence_put(fence);</div><div class='add'>+				kfree(ifence);</div><div class='add'>+				return ERR_PTR(err);</div><div class='add'>+			}</div><div class='add'>+			fence = &amp;ifence-&gt;base.base;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* add shared fence now for pagetable delayed destroy */</div><div class='add'>+		dma_resv_add_fence(xe_vm_resv(vm), fence, !rebind &amp;&amp;</div><div class='add'>+				   last_munmap_rebind ?</div><div class='add'>+				   DMA_RESV_USAGE_KERNEL :</div><div class='add'>+				   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+</div><div class='add'>+		if (!xe_vma_has_no_bo(vma) &amp;&amp; !xe_vma_bo(vma)-&gt;vm)</div><div class='add'>+			dma_resv_add_fence(xe_vma_bo(vma)-&gt;ttm.base.resv, fence,</div><div class='add'>+					   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		xe_pt_commit_bind(vma, entries, num_entries, rebind,</div><div class='add'>+				  bind_pt_update.locked ? &amp;deferred : NULL);</div><div class='add'>+</div><div class='add'>+		/* This vma is live (again?) now */</div><div class='add'>+		vma-&gt;tile_present |= BIT(tile-&gt;id);</div><div class='add'>+</div><div class='add'>+		if (bind_pt_update.locked) {</div><div class='add'>+			vma-&gt;userptr.initial_bind = true;</div><div class='add'>+			up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			xe_bo_put_commit(&amp;deferred);</div><div class='add'>+		}</div><div class='add'>+		if (!rebind &amp;&amp; last_munmap_rebind &amp;&amp;</div><div class='add'>+		    xe_vm_in_preempt_fence_mode(vm))</div><div class='add'>+			xe_vm_queue_rebind_worker(vm);</div><div class='add'>+	} else {</div><div class='add'>+		kfree(rfence);</div><div class='add'>+		kfree(ifence);</div><div class='add'>+		if (bind_pt_update.locked)</div><div class='add'>+			up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		xe_pt_abort_bind(vma, entries, num_entries);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_pt_stage_unbind_walk {</div><div class='add'>+	/** @base: The pagewalk base-class. */</div><div class='add'>+	struct xe_pt_walk base;</div><div class='add'>+</div><div class='add'>+	/* Input parameters for the walk */</div><div class='add'>+	/** @tile: The tile we're unbinding from. */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @modified_start: Walk range start, modified to include any</div><div class='add'>+	 * shared pagetables that we're the only user of and can thus</div><div class='add'>+	 * treat as private.</div><div class='add'>+	 */</div><div class='add'>+	u64 modified_start;</div><div class='add'>+	/** @modified_end: Walk range start, modified like @modified_start. */</div><div class='add'>+	u64 modified_end;</div><div class='add'>+</div><div class='add'>+	/* Output */</div><div class='add'>+	/* @wupd: Structure to track the page-table updates we're building */</div><div class='add'>+	struct xe_walk_update wupd;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Check whether this range is the only one populating this pagetable,</div><div class='add'>+ * and in that case, update the walk range checks so that higher levels don't</div><div class='add'>+ * view us as a shared pagetable.</div><div class='add'>+ */</div><div class='add'>+static bool xe_pt_check_kill(u64 addr, u64 next, unsigned int level,</div><div class='add'>+			     const struct xe_pt *child,</div><div class='add'>+			     enum page_walk_action *action,</div><div class='add'>+			     struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_stage_unbind_walk *xe_walk =</div><div class='add'>+		container_of(walk, typeof(*xe_walk), base);</div><div class='add'>+	unsigned int shift = walk-&gt;shifts[level];</div><div class='add'>+	u64 size = 1ull &lt;&lt; shift;</div><div class='add'>+</div><div class='add'>+	if (IS_ALIGNED(addr, size) &amp;&amp; IS_ALIGNED(next, size) &amp;&amp;</div><div class='add'>+	    ((next - addr) &gt;&gt; shift) == child-&gt;num_live) {</div><div class='add'>+		u64 size = 1ull &lt;&lt; walk-&gt;shifts[level + 1];</div><div class='add'>+</div><div class='add'>+		*action = ACTION_CONTINUE;</div><div class='add'>+</div><div class='add'>+		if (xe_walk-&gt;modified_start &gt;= addr)</div><div class='add'>+			xe_walk-&gt;modified_start = round_down(addr, size);</div><div class='add'>+		if (xe_walk-&gt;modified_end &lt;= next)</div><div class='add'>+			xe_walk-&gt;modified_end = round_up(next, size);</div><div class='add'>+</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_pt_stage_unbind_entry(struct xe_ptw *parent, pgoff_t offset,</div><div class='add'>+				    unsigned int level, u64 addr, u64 next,</div><div class='add'>+				    struct xe_ptw **child,</div><div class='add'>+				    enum page_walk_action *action,</div><div class='add'>+				    struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt *xe_child = container_of(*child, typeof(*xe_child), base);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!*child);</div><div class='add'>+	XE_WARN_ON(!level &amp;&amp; xe_child-&gt;is_compact);</div><div class='add'>+</div><div class='add'>+	xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+xe_pt_stage_unbind_post_descend(struct xe_ptw *parent, pgoff_t offset,</div><div class='add'>+				unsigned int level, u64 addr, u64 next,</div><div class='add'>+				struct xe_ptw **child,</div><div class='add'>+				enum page_walk_action *action,</div><div class='add'>+				struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_stage_unbind_walk *xe_walk =</div><div class='add'>+		container_of(walk, typeof(*xe_walk), base);</div><div class='add'>+	struct xe_pt *xe_child = container_of(*child, typeof(*xe_child), base);</div><div class='add'>+	pgoff_t end_offset;</div><div class='add'>+	u64 size = 1ull &lt;&lt; walk-&gt;shifts[--level];</div><div class='add'>+</div><div class='add'>+	if (!IS_ALIGNED(addr, size))</div><div class='add'>+		addr = xe_walk-&gt;modified_start;</div><div class='add'>+	if (!IS_ALIGNED(next, size))</div><div class='add'>+		next = xe_walk-&gt;modified_end;</div><div class='add'>+</div><div class='add'>+	/* Parent == *child is the root pt. Don't kill it. */</div><div class='add'>+	if (parent != *child &amp;&amp;</div><div class='add'>+	    xe_pt_check_kill(addr, next, level, xe_child, action, walk))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!xe_pt_nonshared_offsets(addr, next, level, walk, action, &amp;offset,</div><div class='add'>+				     &amp;end_offset))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	(void)xe_pt_new_shared(&amp;xe_walk-&gt;wupd, xe_child, offset, false);</div><div class='add'>+	xe_walk-&gt;wupd.updates[level].update-&gt;qwords = end_offset - offset;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pt_walk_ops xe_pt_stage_unbind_ops = {</div><div class='add'>+	.pt_entry = xe_pt_stage_unbind_entry,</div><div class='add'>+	.pt_post_descend = xe_pt_stage_unbind_post_descend,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_stage_unbind() - Build page-table update structures for an unbind</div><div class='add'>+ * operation</div><div class='add'>+ * @tile: The tile we're unbinding for.</div><div class='add'>+ * @vma: The vma we're unbinding.</div><div class='add'>+ * @entries: Caller-provided storage for the update structures.</div><div class='add'>+ *</div><div class='add'>+ * Builds page-table update structures for an unbind operation. The function</div><div class='add'>+ * will attempt to remove all page-tables that we're the only user</div><div class='add'>+ * of, and for that to work, the unbind operation must be committed in the</div><div class='add'>+ * same critical section that blocks racing binds to the same page-table tree.</div><div class='add'>+ *</div><div class='add'>+ * Return: The number of entries used.</div><div class='add'>+ */</div><div class='add'>+static unsigned int xe_pt_stage_unbind(struct xe_tile *tile, struct xe_vma *vma,</div><div class='add'>+				       struct xe_vm_pgtable_update *entries)</div><div class='add'>+{</div><div class='add'>+	struct xe_pt_stage_unbind_walk xe_walk = {</div><div class='add'>+		.base = {</div><div class='add'>+			.ops = &amp;xe_pt_stage_unbind_ops,</div><div class='add'>+			.shifts = xe_normal_pt_shifts,</div><div class='add'>+			.max_level = XE_PT_HIGHEST_LEVEL,</div><div class='add'>+		},</div><div class='add'>+		.tile = tile,</div><div class='add'>+		.modified_start = xe_vma_start(vma),</div><div class='add'>+		.modified_end = xe_vma_end(vma),</div><div class='add'>+		.wupd.entries = entries,</div><div class='add'>+	};</div><div class='add'>+	struct xe_pt *pt = xe_vma_vm(vma)-&gt;pt_root[tile-&gt;id];</div><div class='add'>+</div><div class='add'>+	(void)xe_pt_walk_shared(&amp;pt-&gt;base, pt-&gt;level, xe_vma_start(vma),</div><div class='add'>+				xe_vma_end(vma), &amp;xe_walk.base);</div><div class='add'>+</div><div class='add'>+	return xe_walk.wupd.num_used_entries;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_migrate_clear_pgtable_callback(struct xe_migrate_pt_update *pt_update,</div><div class='add'>+				  struct xe_tile *tile, struct iosys_map *map,</div><div class='add'>+				  void *ptr, u32 qword_ofs, u32 num_qwords,</div><div class='add'>+				  const struct xe_vm_pgtable_update *update)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma = pt_update-&gt;vma;</div><div class='add'>+	u64 empty = __xe_pt_empty_pte(tile, xe_vma_vm(vma), update-&gt;pt-&gt;level);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (map &amp;&amp; map-&gt;is_iomem)</div><div class='add'>+		for (i = 0; i &lt; num_qwords; ++i)</div><div class='add'>+			xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *</div><div class='add'>+				  sizeof(u64), u64, empty);</div><div class='add'>+	else if (map)</div><div class='add'>+		memset64(map-&gt;vaddr + qword_ofs * sizeof(u64), empty,</div><div class='add'>+			 num_qwords);</div><div class='add'>+	else</div><div class='add'>+		memset64(ptr, empty, num_qwords);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_pt_commit_unbind(struct xe_vma *vma,</div><div class='add'>+		    struct xe_vm_pgtable_update *entries, u32 num_entries,</div><div class='add'>+		    struct llist_head *deferred)</div><div class='add'>+{</div><div class='add'>+	u32 j;</div><div class='add'>+</div><div class='add'>+	xe_pt_commit_locks_assert(vma);</div><div class='add'>+</div><div class='add'>+	for (j = 0; j &lt; num_entries; ++j) {</div><div class='add'>+		struct xe_vm_pgtable_update *entry = &amp;entries[j];</div><div class='add'>+		struct xe_pt *pt = entry-&gt;pt;</div><div class='add'>+</div><div class='add'>+		pt-&gt;num_live -= entry-&gt;qwords;</div><div class='add'>+		if (pt-&gt;level) {</div><div class='add'>+			struct xe_pt_dir *pt_dir = as_xe_pt_dir(pt);</div><div class='add'>+			u32 i;</div><div class='add'>+</div><div class='add'>+			for (i = entry-&gt;ofs; i &lt; entry-&gt;ofs + entry-&gt;qwords;</div><div class='add'>+			     i++) {</div><div class='add'>+				if (xe_pt_entry(pt_dir, i))</div><div class='add'>+					xe_pt_destroy(xe_pt_entry(pt_dir, i),</div><div class='add'>+						      xe_vma_vm(vma)-&gt;flags, deferred);</div><div class='add'>+</div><div class='add'>+				pt_dir-&gt;dir.entries[i] = NULL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_migrate_pt_update_ops unbind_ops = {</div><div class='add'>+	.populate = xe_migrate_clear_pgtable_callback,</div><div class='add'>+	.pre_commit = xe_pt_pre_commit,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_migrate_pt_update_ops userptr_unbind_ops = {</div><div class='add'>+	.populate = xe_migrate_clear_pgtable_callback,</div><div class='add'>+	.pre_commit = xe_pt_userptr_pre_commit,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __xe_pt_unbind_vma() - Disconnect and free a page-table tree for the vma</div><div class='add'>+ * address range.</div><div class='add'>+ * @tile: The tile to unbind for.</div><div class='add'>+ * @vma: The vma to unbind.</div><div class='add'>+ * @q: The exec_queue with which to do pipelined page-table updates.</div><div class='add'>+ * @syncs: Entries to sync on before disconnecting the tree to be destroyed.</div><div class='add'>+ * @num_syncs: Number of @sync entries.</div><div class='add'>+ *</div><div class='add'>+ * This function builds a the xe_vm_pgtable_update entries abstracting the</div><div class='add'>+ * operations needed to detach the page-table tree to be destroyed from the</div><div class='add'>+ * man vm tree.</div><div class='add'>+ * It then takes the relevant locks and submits the operations for</div><div class='add'>+ * pipelined detachment of the gpu page-table from  the vm main tree,</div><div class='add'>+ * (which can be done either by the cpu and the GPU), Finally it frees the</div><div class='add'>+ * detached page-table tree.</div><div class='add'>+ *</div><div class='add'>+ * Return: A valid dma-fence representing the pipelined detachment operation</div><div class='add'>+ * on success, an error pointer on error.</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		   struct xe_sync_entry *syncs, u32 num_syncs)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1];</div><div class='add'>+	struct xe_pt_migrate_pt_update unbind_pt_update = {</div><div class='add'>+		.base = {</div><div class='add'>+			.ops = xe_vma_is_userptr(vma) ? &amp;userptr_unbind_ops :</div><div class='add'>+			&amp;unbind_ops,</div><div class='add'>+			.vma = vma,</div><div class='add'>+			.tile_id = tile-&gt;id,</div><div class='add'>+		},</div><div class='add'>+	};</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	u32 num_entries;</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='add'>+	struct invalidation_fence *ifence;</div><div class='add'>+	struct xe_range_fence *rfence;</div><div class='add'>+</div><div class='add'>+	LLIST_HEAD(deferred);</div><div class='add'>+</div><div class='add'>+	xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	vm_dbg(&amp;xe_vma_vm(vma)-&gt;xe-&gt;drm,</div><div class='add'>+	       "Preparing unbind, with range [%llx...%llx) engine %p.\n",</div><div class='add'>+	       xe_vma_start(vma), xe_vma_end(vma), q);</div><div class='add'>+</div><div class='add'>+	num_entries = xe_pt_stage_unbind(tile, vma, entries);</div><div class='add'>+	xe_tile_assert(tile, num_entries &lt;= ARRAY_SIZE(entries));</div><div class='add'>+</div><div class='add'>+	xe_vm_dbg_print_entries(tile_to_xe(tile), entries, num_entries);</div><div class='add'>+	xe_pt_calc_rfence_interval(vma, &amp;unbind_pt_update, entries,</div><div class='add'>+				   num_entries);</div><div class='add'>+</div><div class='add'>+	ifence = kzalloc(sizeof(*ifence), GFP_KERNEL);</div><div class='add'>+	if (!ifence)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	rfence = kzalloc(sizeof(*rfence), GFP_KERNEL);</div><div class='add'>+	if (!rfence) {</div><div class='add'>+		kfree(ifence);</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Even if we were already evicted and unbind to destroy, we need to</div><div class='add'>+	 * clear again here. The eviction may have updated pagetables at a</div><div class='add'>+	 * lower level, because it needs to be more conservative.</div><div class='add'>+	 */</div><div class='add'>+	fence = xe_migrate_update_pgtables(tile-&gt;migrate,</div><div class='add'>+					   vm, NULL, q ? q :</div><div class='add'>+					   vm-&gt;q[tile-&gt;id],</div><div class='add'>+					   entries, num_entries,</div><div class='add'>+					   syncs, num_syncs,</div><div class='add'>+					   &amp;unbind_pt_update.base);</div><div class='add'>+	if (!IS_ERR(fence)) {</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		err = xe_range_fence_insert(&amp;vm-&gt;rftree[tile-&gt;id], rfence,</div><div class='add'>+					    &amp;xe_range_fence_kfree_ops,</div><div class='add'>+					    unbind_pt_update.base.start,</div><div class='add'>+					    unbind_pt_update.base.last, fence);</div><div class='add'>+		if (err)</div><div class='add'>+			dma_fence_wait(fence, false);</div><div class='add'>+</div><div class='add'>+		/* TLB invalidation must be done before signaling unbind */</div><div class='add'>+		err = invalidation_fence_init(tile-&gt;primary_gt, ifence, fence, vma);</div><div class='add'>+		if (err) {</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+			kfree(ifence);</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+		}</div><div class='add'>+		fence = &amp;ifence-&gt;base.base;</div><div class='add'>+</div><div class='add'>+		/* add shared fence now for pagetable delayed destroy */</div><div class='add'>+		dma_resv_add_fence(xe_vm_resv(vm), fence,</div><div class='add'>+				   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+</div><div class='add'>+		/* This fence will be installed by caller when doing eviction */</div><div class='add'>+		if (!xe_vma_has_no_bo(vma) &amp;&amp; !xe_vma_bo(vma)-&gt;vm)</div><div class='add'>+			dma_resv_add_fence(xe_vma_bo(vma)-&gt;ttm.base.resv, fence,</div><div class='add'>+					   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		xe_pt_commit_unbind(vma, entries, num_entries,</div><div class='add'>+				    unbind_pt_update.locked ? &amp;deferred : NULL);</div><div class='add'>+		vma-&gt;tile_present &amp;= ~BIT(tile-&gt;id);</div><div class='add'>+	} else {</div><div class='add'>+		kfree(rfence);</div><div class='add'>+		kfree(ifence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!vma-&gt;tile_present)</div><div class='add'>+		list_del_init(&amp;vma-&gt;combined_links.rebind);</div><div class='add'>+</div><div class='add'>+	if (unbind_pt_update.locked) {</div><div class='add'>+		xe_tile_assert(tile, xe_vma_is_userptr(vma));</div><div class='add'>+</div><div class='add'>+		if (!vma-&gt;tile_present) {</div><div class='add'>+			spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+			list_del_init(&amp;vma-&gt;userptr.invalidate_link);</div><div class='add'>+			spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		}</div><div class='add'>+		up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		xe_bo_put_commit(&amp;deferred);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h<br/>new file mode 100644<br/>index 000000000000..71a4fbfcff43<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt.h</a></div><div class='hunk'>@@ -0,0 +1,48 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_PT_H_</div><div class='add'>+#define _XE_PT_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_pt_types.h"</div><div class='add'>+</div><div class='add'>+struct dma_fence;</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_sync_entry;</div><div class='add'>+struct xe_tile;</div><div class='add'>+struct xe_vm;</div><div class='add'>+struct xe_vma;</div><div class='add'>+</div><div class='add'>+/* Largest huge pte is currently 1GiB. May become device dependent. */</div><div class='add'>+#define MAX_HUGEPTE_LEVEL 2</div><div class='add'>+</div><div class='add'>+#define xe_pt_write(xe, map, idx, data) \</div><div class='add'>+	xe_map_wr(xe, map, (idx) * sizeof(u64), u64, data)</div><div class='add'>+</div><div class='add'>+unsigned int xe_pt_shift(unsigned int level);</div><div class='add'>+</div><div class='add'>+struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile,</div><div class='add'>+			   unsigned int level);</div><div class='add'>+</div><div class='add'>+void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm,</div><div class='add'>+			  struct xe_pt *pt);</div><div class='add'>+</div><div class='add'>+void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred);</div><div class='add'>+</div><div class='add'>+struct dma_fence *</div><div class='add'>+__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		 struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+		 bool rebind);</div><div class='add'>+</div><div class='add'>+struct dma_fence *</div><div class='add'>+__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		   struct xe_sync_entry *syncs, u32 num_syncs);</div><div class='add'>+</div><div class='add'>+bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h<br/>new file mode 100644<br/>index 000000000000..cee70cb0f014<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pt_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_types.h</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_PT_TYPES_H_</div><div class='add'>+#define _XE_PT_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_pt_walk.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_vma;</div><div class='add'>+</div><div class='add'>+enum xe_cache_level {</div><div class='add'>+	XE_CACHE_NONE,</div><div class='add'>+	XE_CACHE_WT,</div><div class='add'>+	XE_CACHE_WB,</div><div class='add'>+	XE_CACHE_NONE_COMPRESSION, /*UC + COH_NONE + COMPRESSION */</div><div class='add'>+	__XE_CACHE_LEVEL_COUNT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE_VM_MAX_LEVEL 4</div><div class='add'>+</div><div class='add'>+struct xe_pt {</div><div class='add'>+	struct xe_ptw base;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	unsigned int level;</div><div class='add'>+	unsigned int num_live;</div><div class='add'>+	bool rebind;</div><div class='add'>+	bool is_compact;</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)</div><div class='add'>+	/** addr: Virtual address start address of the PT. */</div><div class='add'>+	u64 addr;</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_pt_ops {</div><div class='add'>+	u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+			     u16 pat_index, u32 pt_level);</div><div class='add'>+	u64 (*pte_encode_vma)(u64 pte, struct xe_vma *vma,</div><div class='add'>+			      u16 pat_index, u32 pt_level);</div><div class='add'>+	u64 (*pte_encode_addr)(struct xe_device *xe, u64 addr,</div><div class='add'>+			       u16 pat_index,</div><div class='add'>+			       u32 pt_level, bool devmem, u64 flags);</div><div class='add'>+	u64 (*pde_encode_bo)(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+			     u16 pat_index);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_pt_entry {</div><div class='add'>+	struct xe_pt *pt;</div><div class='add'>+	u64 pte;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_vm_pgtable_update {</div><div class='add'>+	/** @bo: page table bo to write to */</div><div class='add'>+	struct xe_bo *pt_bo;</div><div class='add'>+</div><div class='add'>+	/** @ofs: offset inside this PTE to begin writing to (in qwords) */</div><div class='add'>+	u32 ofs;</div><div class='add'>+</div><div class='add'>+	/** @qwords: number of PTE's to write */</div><div class='add'>+	u32 qwords;</div><div class='add'>+</div><div class='add'>+	/** @pt: opaque pointer useful for the caller of xe_migrate_update_pgtables */</div><div class='add'>+	struct xe_pt *pt;</div><div class='add'>+</div><div class='add'>+	/** @pt_entries: Newly added pagetable entries */</div><div class='add'>+	struct xe_pt_entry *pt_entries;</div><div class='add'>+</div><div class='add'>+	/** @flags: Target flags */</div><div class='add'>+	u32 flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pt_walk.c b/drivers/gpu/drm/xe/xe_pt_walk.c<br/>new file mode 100644<br/>index 000000000000..8f6c8d063f39<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pt_walk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_walk.c</a></div><div class='hunk'>@@ -0,0 +1,160 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#include "xe_pt_walk.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GPU page-table tree walking.</div><div class='add'>+ * The utilities in this file are similar to the CPU page-table walk</div><div class='add'>+ * utilities in mm/pagewalk.c. The main difference is that we distinguish</div><div class='add'>+ * the various levels of a page-table tree with an unsigned integer rather</div><div class='add'>+ * than by name. 0 is the lowest level, and page-tables with level 0 can</div><div class='add'>+ * not be directories pointing to lower levels, whereas all other levels</div><div class='add'>+ * can. The user of the utilities determines the highest level.</div><div class='add'>+ *</div><div class='add'>+ * Nomenclature:</div><div class='add'>+ * Each struct xe_ptw, regardless of level is referred to as a page table, and</div><div class='add'>+ * multiple page tables typically form a page table tree with page tables at</div><div class='add'>+ * intermediate levels being page directories pointing at page tables at lower</div><div class='add'>+ * levels. A shared page table for a given address range is a page-table which</div><div class='add'>+ * is neither fully within nor fully outside the address range and that can</div><div class='add'>+ * thus be shared by two or more address ranges.</div><div class='add'>+ *</div><div class='add'>+ * Please keep this code generic so that it can used as a drm-wide page-</div><div class='add'>+ * table walker should other drivers find use for it.</div><div class='add'>+ */</div><div class='add'>+static u64 xe_pt_addr_end(u64 addr, u64 end, unsigned int level,</div><div class='add'>+			  const struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	u64 size = 1ull &lt;&lt; walk-&gt;shifts[level];</div><div class='add'>+	u64 tmp = round_up(addr + 1, size);</div><div class='add'>+</div><div class='add'>+	return min_t(u64, tmp, end);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_pt_next(pgoff_t *offset, u64 *addr, u64 next, u64 end,</div><div class='add'>+		       unsigned int level, const struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	pgoff_t step = 1;</div><div class='add'>+</div><div class='add'>+	/* Shared pt walk skips to the last pagetable */</div><div class='add'>+	if (unlikely(walk-&gt;shared_pt_mode)) {</div><div class='add'>+		unsigned int shift = walk-&gt;shifts[level];</div><div class='add'>+		u64 skip_to = round_down(end, 1ull &lt;&lt; shift);</div><div class='add'>+</div><div class='add'>+		if (skip_to &gt; next) {</div><div class='add'>+			step += (skip_to - next) &gt;&gt; shift;</div><div class='add'>+			next = skip_to;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*addr = next;</div><div class='add'>+	*offset += step;</div><div class='add'>+</div><div class='add'>+	return next != end;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_walk_range() - Walk a range of a gpu page table tree with callbacks</div><div class='add'>+ * for each page-table entry in all levels.</div><div class='add'>+ * @parent: The root page table for walk start.</div><div class='add'>+ * @level: The root page table level.</div><div class='add'>+ * @addr: Virtual address start.</div><div class='add'>+ * @end: Virtual address end + 1.</div><div class='add'>+ * @walk: Walk info.</div><div class='add'>+ *</div><div class='add'>+ * Similar to the CPU page-table walker, this is a helper to walk</div><div class='add'>+ * a gpu page table and call a provided callback function for each entry.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error. The error is</div><div class='add'>+ * propagated from the callback and on error the walk is terminated.</div><div class='add'>+ */</div><div class='add'>+int xe_pt_walk_range(struct xe_ptw *parent, unsigned int level,</div><div class='add'>+		     u64 addr, u64 end, struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	pgoff_t offset = xe_pt_offset(addr, level, walk);</div><div class='add'>+	struct xe_ptw **entries = parent-&gt;dir ? parent-&gt;dir-&gt;entries : NULL;</div><div class='add'>+	const struct xe_pt_walk_ops *ops = walk-&gt;ops;</div><div class='add'>+	enum page_walk_action action;</div><div class='add'>+	struct xe_ptw *child;</div><div class='add'>+	int err = 0;</div><div class='add'>+	u64 next;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		next = xe_pt_addr_end(addr, end, level, walk);</div><div class='add'>+		if (walk-&gt;shared_pt_mode &amp;&amp; xe_pt_covers(addr, next, level,</div><div class='add'>+							 walk))</div><div class='add'>+			continue;</div><div class='add'>+again:</div><div class='add'>+		action = ACTION_SUBTREE;</div><div class='add'>+		child = entries ? entries[offset] : NULL;</div><div class='add'>+		err = ops-&gt;pt_entry(parent, offset, level, addr, next,</div><div class='add'>+				    &amp;child, &amp;action, walk);</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		/* Probably not needed yet for gpu pagetable walk. */</div><div class='add'>+		if (unlikely(action == ACTION_AGAIN))</div><div class='add'>+			goto again;</div><div class='add'>+</div><div class='add'>+		if (likely(!level || !child || action == ACTION_CONTINUE))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		err = xe_pt_walk_range(child, level - 1, addr, next, walk);</div><div class='add'>+</div><div class='add'>+		if (!err &amp;&amp; ops-&gt;pt_post_descend)</div><div class='add'>+			err = ops-&gt;pt_post_descend(parent, offset, level, addr,</div><div class='add'>+						   next, &amp;child, &amp;action, walk);</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+	} while (xe_pt_next(&amp;offset, &amp;addr, next, end, level, walk));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_walk_shared() - Walk shared page tables of a page-table tree.</div><div class='add'>+ * @parent: Root page table directory.</div><div class='add'>+ * @level: Level of the root.</div><div class='add'>+ * @addr: Start address.</div><div class='add'>+ * @end: Last address + 1.</div><div class='add'>+ * @walk: Walk info.</div><div class='add'>+ *</div><div class='add'>+ * This function is similar to xe_pt_walk_range() but it skips page tables</div><div class='add'>+ * that are private to the range. Since the root (or @parent) page table is</div><div class='add'>+ * typically also a shared page table this function is different in that it</div><div class='add'>+ * calls the pt_entry callback and the post_descend callback also for the</div><div class='add'>+ * root. The root can be detected in the callbacks by checking whether</div><div class='add'>+ * parent == *child.</div><div class='add'>+ * Walking only the shared page tables is common for unbind-type operations</div><div class='add'>+ * where the page-table entries for an address range are cleared or detached</div><div class='add'>+ * from the main page-table tree.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error: If a callback</div><div class='add'>+ * returns an error, the walk will be terminated and the error returned by</div><div class='add'>+ * this function.</div><div class='add'>+ */</div><div class='add'>+int xe_pt_walk_shared(struct xe_ptw *parent, unsigned int level,</div><div class='add'>+		      u64 addr, u64 end, struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	const struct xe_pt_walk_ops *ops = walk-&gt;ops;</div><div class='add'>+	enum page_walk_action action = ACTION_SUBTREE;</div><div class='add'>+	struct xe_ptw *child = parent;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	walk-&gt;shared_pt_mode = true;</div><div class='add'>+	err = walk-&gt;ops-&gt;pt_entry(parent, 0, level + 1, addr, end,</div><div class='add'>+				  &amp;child, &amp;action, walk);</div><div class='add'>+</div><div class='add'>+	if (err || action != ACTION_SUBTREE)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_pt_walk_range(parent, level, addr, end, walk);</div><div class='add'>+	if (!err &amp;&amp; ops-&gt;pt_post_descend) {</div><div class='add'>+		err = ops-&gt;pt_post_descend(parent, 0, level + 1, addr, end,</div><div class='add'>+					   &amp;child, &amp;action, walk);</div><div class='add'>+	}</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_pt_walk.h b/drivers/gpu/drm/xe/xe_pt_walk.h<br/>new file mode 100644<br/>index 000000000000..ec3d1e9efa6d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_pt_walk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_pt_walk.h</a></div><div class='hunk'>@@ -0,0 +1,161 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef __XE_PT_WALK__</div><div class='add'>+#define __XE_PT_WALK__</div><div class='add'>+</div><div class='add'>+#include &lt;linux/pagewalk.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_ptw_dir;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_ptw - base class for driver pagetable subclassing.</div><div class='add'>+ * @dir: Pointer to an array of children if any.</div><div class='add'>+ *</div><div class='add'>+ * Drivers could subclass this, and if it's a page-directory, typically</div><div class='add'>+ * embed the xe_ptw_dir::entries array in the same allocation.</div><div class='add'>+ */</div><div class='add'>+struct xe_ptw {</div><div class='add'>+	struct xe_ptw_dir *dir;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_ptw_dir - page directory structure</div><div class='add'>+ * @entries: Array holding page directory children.</div><div class='add'>+ *</div><div class='add'>+ * It is the responsibility of the user to ensure @entries is</div><div class='add'>+ * correctly sized.</div><div class='add'>+ */</div><div class='add'>+struct xe_ptw_dir {</div><div class='add'>+	struct xe_ptw *entries[0];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_pt_walk - Embeddable struct for walk parameters</div><div class='add'>+ */</div><div class='add'>+struct xe_pt_walk {</div><div class='add'>+	/** @ops: The walk ops used for the pagewalk */</div><div class='add'>+	const struct xe_pt_walk_ops *ops;</div><div class='add'>+	/**</div><div class='add'>+	 * @shifts: Array of page-table entry shifts used for the</div><div class='add'>+	 * different levels, starting out with the leaf level 0</div><div class='add'>+	 * page-shift as the first entry. It's legal for this pointer to be</div><div class='add'>+	 * changed during the walk.</div><div class='add'>+	 */</div><div class='add'>+	const u64 *shifts;</div><div class='add'>+	/** @max_level: Highest populated level in @sizes */</div><div class='add'>+	unsigned int max_level;</div><div class='add'>+	/**</div><div class='add'>+	 * @shared_pt_mode: Whether to skip all entries that are private</div><div class='add'>+	 * to the address range and called only for entries that are</div><div class='add'>+	 * shared with other address ranges. Such entries are referred to</div><div class='add'>+	 * as shared pagetables.</div><div class='add'>+	 */</div><div class='add'>+	bool shared_pt_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * typedef xe_pt_entry_fn - gpu page-table-walk callback-function</div><div class='add'>+ * @parent: The parent page.table.</div><div class='add'>+ * @offset: The offset (number of entries) into the page table.</div><div class='add'>+ * @level: The level of @parent.</div><div class='add'>+ * @addr: The virtual address.</div><div class='add'>+ * @next: The virtual address for the next call, or end address.</div><div class='add'>+ * @child: Pointer to pointer to child page-table at this @offset. The</div><div class='add'>+ * function may modify the value pointed to if, for example, allocating a</div><div class='add'>+ * child page table.</div><div class='add'>+ * @action: The walk action to take upon return. See &lt;linux/pagewalk.h&gt;.</div><div class='add'>+ * @walk: The walk parameters.</div><div class='add'>+ */</div><div class='add'>+typedef int (*xe_pt_entry_fn)(struct xe_ptw *parent, pgoff_t offset,</div><div class='add'>+			      unsigned int level, u64 addr, u64 next,</div><div class='add'>+			      struct xe_ptw **child,</div><div class='add'>+			      enum page_walk_action *action,</div><div class='add'>+			      struct xe_pt_walk *walk);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_pt_walk_ops - Walk callbacks.</div><div class='add'>+ */</div><div class='add'>+struct xe_pt_walk_ops {</div><div class='add'>+	/**</div><div class='add'>+	 * @pt_entry: Callback to be called for each page table entry prior</div><div class='add'>+	 * to descending to the next level. The returned value of the action</div><div class='add'>+	 * function parameter is honored.</div><div class='add'>+	 */</div><div class='add'>+	xe_pt_entry_fn pt_entry;</div><div class='add'>+	/**</div><div class='add'>+	 * @pt_post_descend: Callback to be called for each page table entry</div><div class='add'>+	 * after return from descending to the next level. The returned value</div><div class='add'>+	 * of the action function parameter is ignored.</div><div class='add'>+	 */</div><div class='add'>+	xe_pt_entry_fn pt_post_descend;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_pt_walk_range(struct xe_ptw *parent, unsigned int level,</div><div class='add'>+		     u64 addr, u64 end, struct xe_pt_walk *walk);</div><div class='add'>+</div><div class='add'>+int xe_pt_walk_shared(struct xe_ptw *parent, unsigned int level,</div><div class='add'>+		      u64 addr, u64 end, struct xe_pt_walk *walk);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_covers - Whether the address range covers an entire entry in @level</div><div class='add'>+ * @addr: Start of the range.</div><div class='add'>+ * @end: End of range + 1.</div><div class='add'>+ * @level: Page table level.</div><div class='add'>+ * @walk: Page table walk info.</div><div class='add'>+ *</div><div class='add'>+ * This function is a helper to aid in determining whether a leaf page table</div><div class='add'>+ * entry can be inserted at this @level.</div><div class='add'>+ *</div><div class='add'>+ * Return: Whether the range provided covers exactly an entry at this level.</div><div class='add'>+ */</div><div class='add'>+static inline bool xe_pt_covers(u64 addr, u64 end, unsigned int level,</div><div class='add'>+				const struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	u64 pt_size = 1ull &lt;&lt; walk-&gt;shifts[level];</div><div class='add'>+</div><div class='add'>+	return end - addr == pt_size &amp;&amp; IS_ALIGNED(addr, pt_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_num_entries: Number of page-table entries of a given range at this</div><div class='add'>+ * level</div><div class='add'>+ * @addr: Start address.</div><div class='add'>+ * @end: End address.</div><div class='add'>+ * @level: Page table level.</div><div class='add'>+ * @walk: Walk info.</div><div class='add'>+ *</div><div class='add'>+ * Return: The number of page table entries at this level between @start and</div><div class='add'>+ * @end.</div><div class='add'>+ */</div><div class='add'>+static inline pgoff_t</div><div class='add'>+xe_pt_num_entries(u64 addr, u64 end, unsigned int level,</div><div class='add'>+		  const struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	u64 pt_size = 1ull &lt;&lt; walk-&gt;shifts[level];</div><div class='add'>+</div><div class='add'>+	return (round_up(end, pt_size) - round_down(addr, pt_size)) &gt;&gt;</div><div class='add'>+		walk-&gt;shifts[level];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_pt_offset: Offset of the page-table entry for a given address.</div><div class='add'>+ * @addr: The address.</div><div class='add'>+ * @level: Page table level.</div><div class='add'>+ * @walk: Walk info.</div><div class='add'>+ *</div><div class='add'>+ * Return: The page table entry offset for the given address in a</div><div class='add'>+ * page table with size indicated by @level.</div><div class='add'>+ */</div><div class='add'>+static inline pgoff_t</div><div class='add'>+xe_pt_offset(u64 addr, unsigned int level, const struct xe_pt_walk *walk)</div><div class='add'>+{</div><div class='add'>+	if (level &lt; walk-&gt;max_level)</div><div class='add'>+		addr &amp;= ((1ull &lt;&lt; walk-&gt;shifts[level + 1]) - 1);</div><div class='add'>+</div><div class='add'>+	return addr &gt;&gt; walk-&gt;shifts[level];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c<br/>new file mode 100644<br/>index 000000000000..9b35673b286c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_query.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_query.c</a></div><div class='hunk'>@@ -0,0 +1,552 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_query.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/nospec.h&gt;</div><div class='add'>+#include &lt;linux/sched/clock.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc_hwconfig.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+</div><div class='add'>+static const u16 xe_to_user_engine_class[] = {</div><div class='add'>+	[XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,</div><div class='add'>+	[XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY,</div><div class='add'>+	[XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+	[XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+	[XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const enum xe_engine_class user_to_xe_engine_class[] = {</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE,</div><div class='add'>+	[DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static size_t calc_hw_engine_info_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 gt_id;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, gt_id)</div><div class='add'>+		for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+			if (xe_hw_engine_is_reserved(hwe))</div><div class='add'>+				continue;</div><div class='add'>+			i++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	return sizeof(struct drm_xe_query_engines) +</div><div class='add'>+		i * sizeof(struct drm_xe_engine);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+typedef u64 (*__ktime_func_t)(void);</div><div class='add'>+static __ktime_func_t __clock_id_to_func(clockid_t clk_id)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Use logic same as the perf subsystem to allow user to select the</div><div class='add'>+	 * reference clock id to be used for timestamps.</div><div class='add'>+	 */</div><div class='add'>+	switch (clk_id) {</div><div class='add'>+	case CLOCK_MONOTONIC:</div><div class='add'>+		return &amp;ktime_get_ns;</div><div class='add'>+	case CLOCK_MONOTONIC_RAW:</div><div class='add'>+		return &amp;ktime_get_raw_ns;</div><div class='add'>+	case CLOCK_REALTIME:</div><div class='add'>+		return &amp;ktime_get_real_ns;</div><div class='add'>+	case CLOCK_BOOTTIME:</div><div class='add'>+		return &amp;ktime_get_boottime_ns;</div><div class='add'>+	case CLOCK_TAI:</div><div class='add'>+		return &amp;ktime_get_clocktai_ns;</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+__read_timestamps(struct xe_gt *gt,</div><div class='add'>+		  struct xe_reg lower_reg,</div><div class='add'>+		  struct xe_reg upper_reg,</div><div class='add'>+		  u64 *engine_ts,</div><div class='add'>+		  u64 *cpu_ts,</div><div class='add'>+		  u64 *cpu_delta,</div><div class='add'>+		  __ktime_func_t cpu_clock)</div><div class='add'>+{</div><div class='add'>+	u32 upper, lower, old_upper, loop = 0;</div><div class='add'>+</div><div class='add'>+	upper = xe_mmio_read32(gt, upper_reg);</div><div class='add'>+	do {</div><div class='add'>+		*cpu_delta = local_clock();</div><div class='add'>+		*cpu_ts = cpu_clock();</div><div class='add'>+		lower = xe_mmio_read32(gt, lower_reg);</div><div class='add'>+		*cpu_delta = local_clock() - *cpu_delta;</div><div class='add'>+		old_upper = upper;</div><div class='add'>+		upper = xe_mmio_read32(gt, upper_reg);</div><div class='add'>+	} while (upper != old_upper &amp;&amp; loop++ &lt; 2);</div><div class='add'>+</div><div class='add'>+	*engine_ts = (u64)upper &lt;&lt; 32 | lower;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+query_engine_cycles(struct xe_device *xe,</div><div class='add'>+		    struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	struct drm_xe_query_engine_cycles __user *query_ptr;</div><div class='add'>+	struct drm_xe_engine_class_instance *eci;</div><div class='add'>+	struct drm_xe_query_engine_cycles resp;</div><div class='add'>+	size_t size = sizeof(resp);</div><div class='add'>+	__ktime_func_t cpu_clock;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	query_ptr = u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	if (copy_from_user(&amp;resp, query_ptr, size))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	cpu_clock = __clock_id_to_func(resp.clockid);</div><div class='add'>+	if (!cpu_clock)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	eci = &amp;resp.eci;</div><div class='add'>+	if (eci-&gt;gt_id &gt; XE_MAX_GT_PER_TILE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gt = xe_device_get_gt(xe, eci-&gt;gt_id);</div><div class='add'>+	if (!gt)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (eci-&gt;engine_class &gt;= ARRAY_SIZE(user_to_xe_engine_class))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	hwe = xe_gt_hw_engine(gt, user_to_xe_engine_class[eci-&gt;engine_class],</div><div class='add'>+			      eci-&gt;engine_instance, true);</div><div class='add'>+	if (!hwe)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+</div><div class='add'>+	__read_timestamps(gt,</div><div class='add'>+			  RING_TIMESTAMP(hwe-&gt;mmio_base),</div><div class='add'>+			  RING_TIMESTAMP_UDW(hwe-&gt;mmio_base),</div><div class='add'>+			  &amp;resp.engine_cycles,</div><div class='add'>+			  &amp;resp.cpu_timestamp,</div><div class='add'>+			  &amp;resp.cpu_delta,</div><div class='add'>+			  cpu_clock);</div><div class='add'>+</div><div class='add'>+	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+	resp.width = 36;</div><div class='add'>+</div><div class='add'>+	/* Only write to the output fields of user query */</div><div class='add'>+	if (put_user(resp.cpu_timestamp, &amp;query_ptr-&gt;cpu_timestamp))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (put_user(resp.cpu_delta, &amp;query_ptr-&gt;cpu_delta))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (put_user(resp.engine_cycles, &amp;query_ptr-&gt;engine_cycles))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (put_user(resp.width, &amp;query_ptr-&gt;width))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_engines(struct xe_device *xe,</div><div class='add'>+			 struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	size_t size = calc_hw_engine_info_size(xe);</div><div class='add'>+	struct drm_xe_query_engines __user *query_ptr =</div><div class='add'>+		u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	struct drm_xe_query_engines *engines;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	enum xe_hw_engine_id id;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	u8 gt_id;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	engines = kmalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!engines)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, gt_id)</div><div class='add'>+		for_each_hw_engine(hwe, gt, id) {</div><div class='add'>+			if (xe_hw_engine_is_reserved(hwe))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			engines-&gt;engines[i].instance.engine_class =</div><div class='add'>+				xe_to_user_engine_class[hwe-&gt;class];</div><div class='add'>+			engines-&gt;engines[i].instance.engine_instance =</div><div class='add'>+				hwe-&gt;logical_instance;</div><div class='add'>+			engines-&gt;engines[i].instance.gt_id = gt-&gt;info.id;</div><div class='add'>+			engines-&gt;engines[i].instance.pad = 0;</div><div class='add'>+			memset(engines-&gt;engines[i].reserved, 0,</div><div class='add'>+			       sizeof(engines-&gt;engines[i].reserved));</div><div class='add'>+</div><div class='add'>+			i++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	engines-&gt;pad = 0;</div><div class='add'>+	engines-&gt;num_engines = i;</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(query_ptr, engines, size)) {</div><div class='add'>+		kfree(engines);</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+	kfree(engines);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t calc_mem_regions_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	u32 num_managers = 1;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = XE_PL_VRAM0; i &lt;= XE_PL_VRAM1; ++i)</div><div class='add'>+		if (ttm_manager_type(&amp;xe-&gt;ttm, i))</div><div class='add'>+			num_managers++;</div><div class='add'>+</div><div class='add'>+	return offsetof(struct drm_xe_query_mem_regions, mem_regions[num_managers]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_mem_regions(struct xe_device *xe,</div><div class='add'>+			    struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	size_t size = calc_mem_regions_size(xe);</div><div class='add'>+	struct drm_xe_query_mem_regions *mem_regions;</div><div class='add'>+	struct drm_xe_query_mem_regions __user *query_ptr =</div><div class='add'>+		u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	struct ttm_resource_manager *man;</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mem_regions = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !mem_regions))</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	man = ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_TT);</div><div class='add'>+	mem_regions-&gt;mem_regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM;</div><div class='add'>+	/*</div><div class='add'>+	 * The instance needs to be a unique number that represents the index</div><div class='add'>+	 * in the placement mask used at xe_gem_create_ioctl() for the</div><div class='add'>+	 * xe_bo_create() placement.</div><div class='add'>+	 */</div><div class='add'>+	mem_regions-&gt;mem_regions[0].instance = 0;</div><div class='add'>+	mem_regions-&gt;mem_regions[0].min_page_size = PAGE_SIZE;</div><div class='add'>+	mem_regions-&gt;mem_regions[0].total_size = man-&gt;size &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	if (perfmon_capable())</div><div class='add'>+		mem_regions-&gt;mem_regions[0].used = ttm_resource_manager_usage(man);</div><div class='add'>+	mem_regions-&gt;num_mem_regions = 1;</div><div class='add'>+</div><div class='add'>+	for (i = XE_PL_VRAM0; i &lt;= XE_PL_VRAM1; ++i) {</div><div class='add'>+		man = ttm_manager_type(&amp;xe-&gt;ttm, i);</div><div class='add'>+		if (man) {</div><div class='add'>+			mem_regions-&gt;mem_regions[mem_regions-&gt;num_mem_regions].mem_class =</div><div class='add'>+				DRM_XE_MEM_REGION_CLASS_VRAM;</div><div class='add'>+			mem_regions-&gt;mem_regions[mem_regions-&gt;num_mem_regions].instance =</div><div class='add'>+				mem_regions-&gt;num_mem_regions;</div><div class='add'>+			mem_regions-&gt;mem_regions[mem_regions-&gt;num_mem_regions].min_page_size =</div><div class='add'>+				xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K ?</div><div class='add'>+				SZ_64K : PAGE_SIZE;</div><div class='add'>+			mem_regions-&gt;mem_regions[mem_regions-&gt;num_mem_regions].total_size =</div><div class='add'>+				man-&gt;size;</div><div class='add'>+</div><div class='add'>+			if (perfmon_capable()) {</div><div class='add'>+				xe_ttm_vram_get_used(man,</div><div class='add'>+					&amp;mem_regions-&gt;mem_regions</div><div class='add'>+					[mem_regions-&gt;num_mem_regions].used,</div><div class='add'>+					&amp;mem_regions-&gt;mem_regions</div><div class='add'>+					[mem_regions-&gt;num_mem_regions].cpu_visible_used);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			mem_regions-&gt;mem_regions[mem_regions-&gt;num_mem_regions].cpu_visible_size =</div><div class='add'>+				xe_ttm_vram_get_cpu_visible_size(man);</div><div class='add'>+			mem_regions-&gt;num_mem_regions++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!copy_to_user(query_ptr, mem_regions, size))</div><div class='add'>+		ret = 0;</div><div class='add'>+	else</div><div class='add'>+		ret = -ENOSPC;</div><div class='add'>+</div><div class='add'>+	kfree(mem_regions);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_config(struct xe_device *xe, struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	const u32 num_params = DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1;</div><div class='add'>+	size_t size =</div><div class='add'>+		sizeof(struct drm_xe_query_config) + num_params * sizeof(u64);</div><div class='add'>+	struct drm_xe_query_config __user *query_ptr =</div><div class='add'>+		u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	struct drm_xe_query_config *config;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	config = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!config)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	config-&gt;num_params = num_params;</div><div class='add'>+	config-&gt;info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] =</div><div class='add'>+		xe-&gt;info.devid | (xe-&gt;info.revid &lt;&lt; 16);</div><div class='add'>+	if (xe_device_get_root_tile(xe)-&gt;mem.vram.usable_size)</div><div class='add'>+		config-&gt;info[DRM_XE_QUERY_CONFIG_FLAGS] =</div><div class='add'>+			DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM;</div><div class='add'>+	config-&gt;info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] =</div><div class='add'>+		xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;</div><div class='add'>+	config-&gt;info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe-&gt;info.va_bits;</div><div class='add'>+	config-&gt;info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY] =</div><div class='add'>+		xe_exec_queue_device_get_max_priority(xe);</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(query_ptr, config, size)) {</div><div class='add'>+		kfree(config);</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+	kfree(config);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_gt_list(struct xe_device *xe, struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	size_t size = sizeof(struct drm_xe_query_gt_list) +</div><div class='add'>+		xe-&gt;info.gt_count * sizeof(struct drm_xe_gt);</div><div class='add'>+	struct drm_xe_query_gt_list __user *query_ptr =</div><div class='add'>+		u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	struct drm_xe_query_gt_list *gt_list;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gt_list = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!gt_list)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	gt_list-&gt;num_gt = xe-&gt;info.gt_count;</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		if (xe_gt_is_media_type(gt))</div><div class='add'>+			gt_list-&gt;gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MEDIA;</div><div class='add'>+		else</div><div class='add'>+			gt_list-&gt;gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MAIN;</div><div class='add'>+		gt_list-&gt;gt_list[id].tile_id = gt_to_tile(gt)-&gt;id;</div><div class='add'>+		gt_list-&gt;gt_list[id].gt_id = gt-&gt;info.id;</div><div class='add'>+		gt_list-&gt;gt_list[id].reference_clock = gt-&gt;info.reference_clock;</div><div class='add'>+		/*</div><div class='add'>+		 * The mem_regions indexes in the mask below need to</div><div class='add'>+		 * directly identify the struct</div><div class='add'>+		 * drm_xe_query_mem_regions' instance constructed at</div><div class='add'>+		 * query_mem_regions()</div><div class='add'>+		 *</div><div class='add'>+		 * For our current platforms:</div><div class='add'>+		 * Bit 0 -&gt; System Memory</div><div class='add'>+		 * Bit 1 -&gt; VRAM0 on Tile0</div><div class='add'>+		 * Bit 2 -&gt; VRAM1 on Tile1</div><div class='add'>+		 * However the uAPI is generic and it's userspace's</div><div class='add'>+		 * responsibility to check the mem_class, without any</div><div class='add'>+		 * assumption.</div><div class='add'>+		 */</div><div class='add'>+		if (!IS_DGFX(xe))</div><div class='add'>+			gt_list-&gt;gt_list[id].near_mem_regions = 0x1;</div><div class='add'>+		else</div><div class='add'>+			gt_list-&gt;gt_list[id].near_mem_regions =</div><div class='add'>+				BIT(gt_to_tile(gt)-&gt;id) &lt;&lt; 1;</div><div class='add'>+		gt_list-&gt;gt_list[id].far_mem_regions = xe-&gt;info.mem_region_mask ^</div><div class='add'>+			gt_list-&gt;gt_list[id].near_mem_regions;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(query_ptr, gt_list, size)) {</div><div class='add'>+		kfree(gt_list);</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+	kfree(gt_list);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_hwconfig(struct xe_device *xe,</div><div class='add'>+			  struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = xe_root_mmio_gt(xe);</div><div class='add'>+	size_t size = xe_guc_hwconfig_size(&amp;gt-&gt;uc.guc);</div><div class='add'>+	void __user *query_ptr = u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	void *hwconfig;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hwconfig = kzalloc(size, GFP_KERNEL);</div><div class='add'>+	if (!hwconfig)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(xe);</div><div class='add'>+	xe_guc_hwconfig_copy(&amp;gt-&gt;uc.guc, hwconfig);</div><div class='add'>+	xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(query_ptr, hwconfig, size)) {</div><div class='add'>+		kfree(hwconfig);</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+	kfree(hwconfig);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static size_t calc_topo_query_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;info.gt_count *</div><div class='add'>+		(3 * sizeof(struct drm_xe_query_topology_mask) +</div><div class='add'>+		 sizeof_field(struct xe_gt, fuse_topo.g_dss_mask) +</div><div class='add'>+		 sizeof_field(struct xe_gt, fuse_topo.c_dss_mask) +</div><div class='add'>+		 sizeof_field(struct xe_gt, fuse_topo.eu_mask_per_dss));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __user *copy_mask(void __user *ptr,</div><div class='add'>+			      struct drm_xe_query_topology_mask *topo,</div><div class='add'>+			      void *mask, size_t mask_size)</div><div class='add'>+{</div><div class='add'>+	topo-&gt;num_bytes = mask_size;</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(ptr, topo, sizeof(*topo)))</div><div class='add'>+		return ERR_PTR(-EFAULT);</div><div class='add'>+	ptr += sizeof(topo);</div><div class='add'>+</div><div class='add'>+	if (copy_to_user(ptr, mask, mask_size))</div><div class='add'>+		return ERR_PTR(-EFAULT);</div><div class='add'>+	ptr += mask_size;</div><div class='add'>+</div><div class='add'>+	return ptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int query_gt_topology(struct xe_device *xe,</div><div class='add'>+			     struct drm_xe_device_query *query)</div><div class='add'>+{</div><div class='add'>+	void __user *query_ptr = u64_to_user_ptr(query-&gt;data);</div><div class='add'>+	size_t size = calc_topo_query_size(xe);</div><div class='add'>+	struct drm_xe_query_topology_mask topo;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	if (query-&gt;size == 0) {</div><div class='add'>+		query-&gt;size = size;</div><div class='add'>+		return 0;</div><div class='add'>+	} else if (XE_IOCTL_DBG(xe, query-&gt;size != size)) {</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_gt(gt, xe, id) {</div><div class='add'>+		topo.gt_id = id;</div><div class='add'>+</div><div class='add'>+		topo.type = DRM_XE_TOPO_DSS_GEOMETRY;</div><div class='add'>+		query_ptr = copy_mask(query_ptr, &amp;topo,</div><div class='add'>+				      gt-&gt;fuse_topo.g_dss_mask,</div><div class='add'>+				      sizeof(gt-&gt;fuse_topo.g_dss_mask));</div><div class='add'>+		if (IS_ERR(query_ptr))</div><div class='add'>+			return PTR_ERR(query_ptr);</div><div class='add'>+</div><div class='add'>+		topo.type = DRM_XE_TOPO_DSS_COMPUTE;</div><div class='add'>+		query_ptr = copy_mask(query_ptr, &amp;topo,</div><div class='add'>+				      gt-&gt;fuse_topo.c_dss_mask,</div><div class='add'>+				      sizeof(gt-&gt;fuse_topo.c_dss_mask));</div><div class='add'>+		if (IS_ERR(query_ptr))</div><div class='add'>+			return PTR_ERR(query_ptr);</div><div class='add'>+</div><div class='add'>+		topo.type = DRM_XE_TOPO_EU_PER_DSS;</div><div class='add'>+		query_ptr = copy_mask(query_ptr, &amp;topo,</div><div class='add'>+				      gt-&gt;fuse_topo.eu_mask_per_dss,</div><div class='add'>+				      sizeof(gt-&gt;fuse_topo.eu_mask_per_dss));</div><div class='add'>+		if (IS_ERR(query_ptr))</div><div class='add'>+			return PTR_ERR(query_ptr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int (* const xe_query_funcs[])(struct xe_device *xe,</div><div class='add'>+				      struct drm_xe_device_query *query) = {</div><div class='add'>+	query_engines,</div><div class='add'>+	query_mem_regions,</div><div class='add'>+	query_config,</div><div class='add'>+	query_gt_list,</div><div class='add'>+	query_hwconfig,</div><div class='add'>+	query_gt_topology,</div><div class='add'>+	query_engine_cycles,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct drm_xe_device_query *query = data;</div><div class='add'>+	u32 idx;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, query-&gt;extensions) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, query-&gt;reserved[0] || query-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, query-&gt;query &gt;= ARRAY_SIZE(xe_query_funcs)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	idx = array_index_nospec(query-&gt;query, ARRAY_SIZE(xe_query_funcs));</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !xe_query_funcs[idx]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return xe_query_funcs[idx](xe, query);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_query.h b/drivers/gpu/drm/xe/xe_query.h<br/>new file mode 100644<br/>index 000000000000..beeb7a8192b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_query.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_query.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_QUERY_H_</div><div class='add'>+#define _XE_QUERY_H_</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_file;</div><div class='add'>+</div><div class='add'>+int xe_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_range_fence.c b/drivers/gpu/drm/xe/xe_range_fence.c<br/>new file mode 100644<br/>index 000000000000..d35d9ec58e86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_range_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_range_fence.c</a></div><div class='hunk'>@@ -0,0 +1,156 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/interval_tree_generic.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_range_fence.h"</div><div class='add'>+</div><div class='add'>+#define XE_RANGE_TREE_START(_node)	((_node)-&gt;start)</div><div class='add'>+#define XE_RANGE_TREE_LAST(_node)	((_node)-&gt;last)</div><div class='add'>+</div><div class='add'>+INTERVAL_TREE_DEFINE(struct xe_range_fence, rb, u64, __subtree_last,</div><div class='add'>+		     XE_RANGE_TREE_START, XE_RANGE_TREE_LAST, static,</div><div class='add'>+		     xe_range_fence_tree);</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+xe_range_fence_signal_notify(struct dma_fence *fence, struct dma_fence_cb *cb)</div><div class='add'>+{</div><div class='add'>+	struct xe_range_fence *rfence = container_of(cb, typeof(*rfence), cb);</div><div class='add'>+	struct xe_range_fence_tree *tree = rfence-&gt;tree;</div><div class='add'>+</div><div class='add'>+	llist_add(&amp;rfence-&gt;link, &amp;tree-&gt;list);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool __xe_range_fence_tree_cleanup(struct xe_range_fence_tree *tree)</div><div class='add'>+{</div><div class='add'>+	struct llist_node *node = llist_del_all(&amp;tree-&gt;list);</div><div class='add'>+	struct xe_range_fence *rfence, *next;</div><div class='add'>+</div><div class='add'>+	llist_for_each_entry_safe(rfence, next, node, link) {</div><div class='add'>+		xe_range_fence_tree_remove(rfence, &amp;tree-&gt;root);</div><div class='add'>+		dma_fence_put(rfence-&gt;fence);</div><div class='add'>+		kfree(rfence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return !!node;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_range_fence_insert() - range fence insert</div><div class='add'>+ * @tree: range fence tree to insert intoi</div><div class='add'>+ * @rfence: range fence</div><div class='add'>+ * @ops: range fence ops</div><div class='add'>+ * @start: start address of range fence</div><div class='add'>+ * @last: last address of range fence</div><div class='add'>+ * @fence: dma fence which signals range fence can be removed + freed</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, non-zero on failure</div><div class='add'>+ */</div><div class='add'>+int xe_range_fence_insert(struct xe_range_fence_tree *tree,</div><div class='add'>+			  struct xe_range_fence *rfence,</div><div class='add'>+			  const struct xe_range_fence_ops *ops,</div><div class='add'>+			  u64 start, u64 last, struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	__xe_range_fence_tree_cleanup(tree);</div><div class='add'>+</div><div class='add'>+	if (dma_fence_is_signaled(fence))</div><div class='add'>+		goto free;</div><div class='add'>+</div><div class='add'>+	rfence-&gt;ops = ops;</div><div class='add'>+	rfence-&gt;start = start;</div><div class='add'>+	rfence-&gt;last = last;</div><div class='add'>+	rfence-&gt;tree = tree;</div><div class='add'>+	rfence-&gt;fence = dma_fence_get(fence);</div><div class='add'>+	err = dma_fence_add_callback(fence, &amp;rfence-&gt;cb,</div><div class='add'>+				     xe_range_fence_signal_notify);</div><div class='add'>+	if (err == -ENOENT) {</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+		err = 0;</div><div class='add'>+		goto free;</div><div class='add'>+	} else if (err == 0) {</div><div class='add'>+		xe_range_fence_tree_insert(rfence, &amp;tree-&gt;root);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+free:</div><div class='add'>+	if (ops-&gt;free)</div><div class='add'>+		ops-&gt;free(rfence);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_range_fence_tree_remove_all(struct xe_range_fence_tree *tree)</div><div class='add'>+{</div><div class='add'>+	struct xe_range_fence *rfence;</div><div class='add'>+	bool retry = true;</div><div class='add'>+</div><div class='add'>+	rfence = xe_range_fence_tree_iter_first(&amp;tree-&gt;root, 0, U64_MAX);</div><div class='add'>+	while (rfence) {</div><div class='add'>+		/* Should be ok with the minimalistic callback */</div><div class='add'>+		if (dma_fence_remove_callback(rfence-&gt;fence, &amp;rfence-&gt;cb))</div><div class='add'>+			llist_add(&amp;rfence-&gt;link, &amp;tree-&gt;list);</div><div class='add'>+		rfence = xe_range_fence_tree_iter_next(rfence, 0, U64_MAX);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	while (retry)</div><div class='add'>+		retry = __xe_range_fence_tree_cleanup(tree);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_range_fence_tree_init() - Init range fence tree</div><div class='add'>+ * @tree: range fence tree</div><div class='add'>+ */</div><div class='add'>+void xe_range_fence_tree_init(struct xe_range_fence_tree *tree)</div><div class='add'>+{</div><div class='add'>+	memset(tree, 0, sizeof(*tree));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_range_fence_tree_fini() - Fini range fence tree</div><div class='add'>+ * @tree: range fence tree</div><div class='add'>+ */</div><div class='add'>+void xe_range_fence_tree_fini(struct xe_range_fence_tree *tree)</div><div class='add'>+{</div><div class='add'>+	xe_range_fence_tree_remove_all(tree);</div><div class='add'>+	XE_WARN_ON(!RB_EMPTY_ROOT(&amp;tree-&gt;root.rb_root));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_range_fence_tree_first() - range fence tree iterator first</div><div class='add'>+ * @tree: range fence tree</div><div class='add'>+ * @start: start address of range fence</div><div class='add'>+ * @last: last address of range fence</div><div class='add'>+ *</div><div class='add'>+ * Return: first range fence found in range or NULL</div><div class='add'>+ */</div><div class='add'>+struct xe_range_fence *</div><div class='add'>+xe_range_fence_tree_first(struct xe_range_fence_tree *tree, u64 start,</div><div class='add'>+			  u64 last)</div><div class='add'>+{</div><div class='add'>+	return xe_range_fence_tree_iter_first(&amp;tree-&gt;root, start, last);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_range_fence_tree_next() - range fence tree iterator next</div><div class='add'>+ * @rfence: current range fence</div><div class='add'>+ * @start: start address of range fence</div><div class='add'>+ * @last: last address of range fence</div><div class='add'>+ *</div><div class='add'>+ * Return: next range fence found in range or NULL</div><div class='add'>+ */</div><div class='add'>+struct xe_range_fence *</div><div class='add'>+xe_range_fence_tree_next(struct xe_range_fence *rfence, u64 start, u64 last)</div><div class='add'>+{</div><div class='add'>+	return xe_range_fence_tree_iter_next(rfence, start, last);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct xe_range_fence_ops xe_range_fence_kfree_ops = {</div><div class='add'>+	.free = (void (*)(struct xe_range_fence *rfence)) kfree,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_range_fence.h b/drivers/gpu/drm/xe/xe_range_fence.h<br/>new file mode 100644<br/>index 000000000000..edd58b34f5c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_range_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_range_fence.h</a></div><div class='hunk'>@@ -0,0 +1,75 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RANGE_FENCE_H_</div><div class='add'>+#define _XE_RANGE_FENCE_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence.h&gt;</div><div class='add'>+#include &lt;linux/rbtree.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_range_fence_tree;</div><div class='add'>+struct xe_range_fence;</div><div class='add'>+</div><div class='add'>+/** struct xe_range_fence_ops - XE range fence ops */</div><div class='add'>+struct xe_range_fence_ops {</div><div class='add'>+	/** @free: free range fence op */</div><div class='add'>+	void (*free)(struct xe_range_fence *rfence);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_range_fence - XE range fence (address conflict tracking) */</div><div class='add'>+struct xe_range_fence {</div><div class='add'>+	/** @rb: RB tree node inserted into interval tree */</div><div class='add'>+	struct rb_node rb;</div><div class='add'>+	/** @start: start address of range fence is interval tree */</div><div class='add'>+	u64 start;</div><div class='add'>+	/** @last: last address (inclusive) of range fence is interval tree */</div><div class='add'>+	u64 last;</div><div class='add'>+	/** @__subtree_last: interval tree internal usage */</div><div class='add'>+	u64 __subtree_last;</div><div class='add'>+	/**</div><div class='add'>+	 * @fence: fence signals address in range fence no longer has conflict</div><div class='add'>+	 */</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	/** @tree: interval tree which range fence belongs to */</div><div class='add'>+	struct xe_range_fence_tree *tree;</div><div class='add'>+	/**</div><div class='add'>+	 * @cb: callback when fence signals to remove range fence free from interval tree</div><div class='add'>+	 */</div><div class='add'>+	struct dma_fence_cb cb;</div><div class='add'>+	/** @link: used to defer free of range fence to non-irq context */</div><div class='add'>+	struct llist_node link;</div><div class='add'>+	/** @ops: range fence ops */</div><div class='add'>+	const struct xe_range_fence_ops *ops;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_range_fence_tree - interval tree to store range fences */</div><div class='add'>+struct xe_range_fence_tree {</div><div class='add'>+	/** @root: interval tree root */</div><div class='add'>+	struct rb_root_cached root;</div><div class='add'>+	/** @list: list of pending range fences to be freed */</div><div class='add'>+	struct llist_head list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct xe_range_fence_ops xe_range_fence_kfree_ops;</div><div class='add'>+</div><div class='add'>+struct xe_range_fence *</div><div class='add'>+xe_range_fence_tree_first(struct xe_range_fence_tree *tree, u64 start,</div><div class='add'>+			  u64 last);</div><div class='add'>+</div><div class='add'>+struct xe_range_fence *</div><div class='add'>+xe_range_fence_tree_next(struct xe_range_fence *rfence, u64 start, u64 last);</div><div class='add'>+</div><div class='add'>+void xe_range_fence_tree_init(struct xe_range_fence_tree *tree);</div><div class='add'>+</div><div class='add'>+void xe_range_fence_tree_fini(struct xe_range_fence_tree *tree);</div><div class='add'>+</div><div class='add'>+int xe_range_fence_insert(struct xe_range_fence_tree *tree,</div><div class='add'>+			  struct xe_range_fence *rfence,</div><div class='add'>+			  const struct xe_range_fence_ops *ops,</div><div class='add'>+			  u64 start, u64 end,</div><div class='add'>+			  struct dma_fence *fence);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c<br/>new file mode 100644<br/>index 000000000000..87adefb56024<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_reg_sr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr.c</a></div><div class='hunk'>@@ -0,0 +1,284 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+#include &lt;linux/string_helpers.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_mcr.h"</div><div class='add'>+#include "xe_gt_printk.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_reg_whitelist.h"</div><div class='add'>+#include "xe_rtp_types.h"</div><div class='add'>+</div><div class='add'>+#define XE_REG_SR_GROW_STEP_DEFAULT	16</div><div class='add'>+</div><div class='add'>+static void reg_sr_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr *sr = arg;</div><div class='add'>+</div><div class='add'>+	xa_destroy(&amp;sr-&gt;xa);</div><div class='add'>+	kfree(sr-&gt;pool.arr);</div><div class='add'>+	memset(&amp;sr-&gt;pool, 0, sizeof(sr-&gt;pool));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_reg_sr_init(struct xe_reg_sr *sr, const char *name, struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xa_init(&amp;sr-&gt;xa);</div><div class='add'>+	memset(&amp;sr-&gt;pool, 0, sizeof(sr-&gt;pool));</div><div class='add'>+	sr-&gt;pool.grow_step = XE_REG_SR_GROW_STEP_DEFAULT;</div><div class='add'>+	sr-&gt;name = name;</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, reg_sr_fini, sr);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_reg_sr_init);</div><div class='add'>+</div><div class='add'>+static struct xe_reg_sr_entry *alloc_entry(struct xe_reg_sr *sr)</div><div class='add'>+{</div><div class='add'>+	if (sr-&gt;pool.used == sr-&gt;pool.allocated) {</div><div class='add'>+		struct xe_reg_sr_entry *arr;</div><div class='add'>+</div><div class='add'>+		arr = krealloc_array(sr-&gt;pool.arr,</div><div class='add'>+				     ALIGN(sr-&gt;pool.allocated + 1, sr-&gt;pool.grow_step),</div><div class='add'>+				     sizeof(*arr), GFP_KERNEL);</div><div class='add'>+		if (!arr)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		sr-&gt;pool.arr = arr;</div><div class='add'>+		sr-&gt;pool.allocated += sr-&gt;pool.grow_step;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;sr-&gt;pool.arr[sr-&gt;pool.used++];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool compatible_entries(const struct xe_reg_sr_entry *e1,</div><div class='add'>+			       const struct xe_reg_sr_entry *e2)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Don't allow overwriting values: clr_bits/set_bits should be disjoint</div><div class='add'>+	 * when operating in the same register</div><div class='add'>+	 */</div><div class='add'>+	if (e1-&gt;clr_bits &amp; e2-&gt;clr_bits || e1-&gt;set_bits &amp; e2-&gt;set_bits ||</div><div class='add'>+	    e1-&gt;clr_bits &amp; e2-&gt;set_bits || e1-&gt;set_bits &amp; e2-&gt;clr_bits)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (e1-&gt;reg.raw != e2-&gt;reg.raw)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void reg_sr_inc_error(struct xe_reg_sr *sr)</div><div class='add'>+{</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+	sr-&gt;errors++;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_reg_sr_add(struct xe_reg_sr *sr,</div><div class='add'>+		  const struct xe_reg_sr_entry *e,</div><div class='add'>+		  struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	unsigned long idx = e-&gt;reg.addr;</div><div class='add'>+	struct xe_reg_sr_entry *pentry = xa_load(&amp;sr-&gt;xa, idx);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (pentry) {</div><div class='add'>+		if (!compatible_entries(pentry, e)) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto fail;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pentry-&gt;clr_bits |= e-&gt;clr_bits;</div><div class='add'>+		pentry-&gt;set_bits |= e-&gt;set_bits;</div><div class='add'>+		pentry-&gt;read_mask |= e-&gt;read_mask;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pentry = alloc_entry(sr);</div><div class='add'>+	if (!pentry) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*pentry = *e;</div><div class='add'>+	ret = xa_err(xa_store(&amp;sr-&gt;xa, idx, pentry, GFP_KERNEL));</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	xe_gt_err(gt,</div><div class='add'>+		  "discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n",</div><div class='add'>+		  idx, e-&gt;clr_bits, e-&gt;set_bits,</div><div class='add'>+		  str_yes_no(e-&gt;reg.masked),</div><div class='add'>+		  str_yes_no(e-&gt;reg.mcr),</div><div class='add'>+		  ret);</div><div class='add'>+	reg_sr_inc_error(sr);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Convert back from encoded value to type-safe, only to be used when reg.mcr</div><div class='add'>+ * is true</div><div class='add'>+ */</div><div class='add'>+static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg)</div><div class='add'>+{</div><div class='add'>+	return (const struct xe_reg_mcr){.__reg.raw = reg.raw };</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg reg = entry-&gt;reg;</div><div class='add'>+	struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg);</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If this is a masked register, need to set the upper 16 bits.</div><div class='add'>+	 * Set them to clr_bits since that is always a superset of the bits</div><div class='add'>+	 * being modified.</div><div class='add'>+	 *</div><div class='add'>+	 * When it's not masked, we have to read it from hardware, unless we are</div><div class='add'>+	 * supposed to set all bits.</div><div class='add'>+	 */</div><div class='add'>+	if (reg.masked)</div><div class='add'>+		val = entry-&gt;clr_bits &lt;&lt; 16;</div><div class='add'>+	else if (entry-&gt;clr_bits + 1)</div><div class='add'>+		val = (reg.mcr ?</div><div class='add'>+		       xe_gt_mcr_unicast_read_any(gt, reg_mcr) :</div><div class='add'>+		       xe_mmio_read32(gt, reg)) &amp; (~entry-&gt;clr_bits);</div><div class='add'>+	else</div><div class='add'>+		val = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: add selftest to validate all tables, regardless of platform:</div><div class='add'>+	 *   - Masked registers can't have set_bits with upper bits set</div><div class='add'>+	 *   - set_bits must be contained in clr_bits</div><div class='add'>+	 */</div><div class='add'>+	val |= entry-&gt;set_bits;</div><div class='add'>+</div><div class='add'>+	xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val);</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;reg.mcr)</div><div class='add'>+		xe_gt_mcr_multicast_write(gt, reg_mcr, val);</div><div class='add'>+	else</div><div class='add'>+		xe_mmio_write32(gt, reg, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	unsigned long reg;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (xa_empty(&amp;sr-&gt;xa))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_gt_dbg(gt, "Applying %s save-restore MMIOs\n", sr-&gt;name);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(&amp;gt-&gt;mmio.fw, XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;sr-&gt;xa, reg, entry)</div><div class='add'>+		apply_one_mmio(gt, entry);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(&amp;gt-&gt;mmio.fw, XE_FORCEWAKE_ALL);</div><div class='add'>+	XE_WARN_ON(err);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	xe_gt_err(gt, "Failed to apply, err=%d\n", err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr *sr = &amp;hwe-&gt;reg_whitelist;</div><div class='add'>+	struct xe_gt *gt = hwe-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	struct drm_printer p;</div><div class='add'>+	u32 mmio_base = hwe-&gt;mmio_base;</div><div class='add'>+	unsigned long reg;</div><div class='add'>+	unsigned int slot = 0;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (xa_empty(&amp;sr-&gt;xa))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Whitelisting %s registers\n", sr-&gt;name);</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_get(&amp;gt-&gt;mmio.fw, XE_FORCEWAKE_ALL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_force_wake;</div><div class='add'>+</div><div class='add'>+	p = drm_debug_printer(KBUILD_MODNAME);</div><div class='add'>+	xa_for_each(&amp;sr-&gt;xa, reg, entry) {</div><div class='add'>+		if (slot == RING_MAX_NONPRIV_SLOTS) {</div><div class='add'>+			xe_gt_err(gt,</div><div class='add'>+				  "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n",</div><div class='add'>+				  hwe-&gt;name, RING_MAX_NONPRIV_SLOTS);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_reg_whitelist_print_entry(&amp;p, 0, reg, entry);</div><div class='add'>+		xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),</div><div class='add'>+				reg | entry-&gt;set_bits);</div><div class='add'>+		slot++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* And clear the rest just in case of garbage */</div><div class='add'>+	for (; slot &lt; RING_MAX_NONPRIV_SLOTS; slot++) {</div><div class='add'>+		u32 addr = RING_NOPID(mmio_base).addr;</div><div class='add'>+</div><div class='add'>+		xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = xe_force_wake_put(&amp;gt-&gt;mmio.fw, XE_FORCEWAKE_ALL);</div><div class='add'>+	XE_WARN_ON(err);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+err_force_wake:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "Failed to apply, err=%d\n", err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_reg_sr_dump - print all save/restore entries</div><div class='add'>+ * @sr: Save/restore entries</div><div class='add'>+ * @p: DRM printer</div><div class='add'>+ */</div><div class='add'>+void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	unsigned long reg;</div><div class='add'>+</div><div class='add'>+	if (!sr-&gt;name || xa_empty(&amp;sr-&gt;xa))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "%s\n", sr-&gt;name);</div><div class='add'>+	xa_for_each(&amp;sr-&gt;xa, reg, entry)</div><div class='add'>+		drm_printf(p, "\tREG[0x%lx] clr=0x%08x set=0x%08x masked=%s mcr=%s\n",</div><div class='add'>+			   reg, entry-&gt;clr_bits, entry-&gt;set_bits,</div><div class='add'>+			   str_yes_no(entry-&gt;reg.masked),</div><div class='add'>+			   str_yes_no(entry-&gt;reg.mcr));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h<br/>new file mode 100644<br/>index 000000000000..e3197c33afe2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_reg_sr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_REG_SR_</div><div class='add'>+#define _XE_REG_SR_</div><div class='add'>+</div><div class='add'>+#include "xe_reg_sr_types.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Reg save/restore bookkeeping</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+int xe_reg_sr_init(struct xe_reg_sr *sr, const char *name, struct xe_device *xe);</div><div class='add'>+void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+int xe_reg_sr_add(struct xe_reg_sr *sr, const struct xe_reg_sr_entry *e,</div><div class='add'>+		  struct xe_gt *gt);</div><div class='add'>+void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt);</div><div class='add'>+void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h<br/>new file mode 100644<br/>index 000000000000..ad48a52b824a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_reg_sr_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_sr_types.h</a></div><div class='hunk'>@@ -0,0 +1,37 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_REG_SR_TYPES_</div><div class='add'>+#define _XE_REG_SR_TYPES_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+struct xe_reg_sr_entry {</div><div class='add'>+	struct xe_reg	reg;</div><div class='add'>+	u32		clr_bits;</div><div class='add'>+	u32		set_bits;</div><div class='add'>+	/* Mask for bits to consider when reading value back */</div><div class='add'>+	u32		read_mask;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_reg_sr {</div><div class='add'>+	struct {</div><div class='add'>+		struct xe_reg_sr_entry *arr;</div><div class='add'>+		unsigned int used;</div><div class='add'>+		unsigned int allocated;</div><div class='add'>+		unsigned int grow_step;</div><div class='add'>+	} pool;</div><div class='add'>+	struct xarray xa;</div><div class='add'>+	const char *name;</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)</div><div class='add'>+	unsigned int errors;</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c<br/>new file mode 100644<br/>index 000000000000..e66ae1bdaf9c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_reg_whitelist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_whitelist.c</a></div><div class='hunk'>@@ -0,0 +1,146 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_reg_whitelist.h"</div><div class='add'>+</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+</div><div class='add'>+#undef XE_REG_MCR</div><div class='add'>+#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)</div><div class='add'>+</div><div class='add'>+static bool match_not_render(const struct xe_gt *gt,</div><div class='add'>+			     const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return hwe-&gt;class != XE_ENGINE_CLASS_RENDER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr register_whitelist[] = {</div><div class='add'>+	{ XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_ACCESS_RD |</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_RANGE_4))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1508744258, 14012131227, 1808121037"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1806527549"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("allow_read_ctx_timestamp"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),</div><div class='add'>+				RING_FORCE_TO_NONPRIV_ACCESS_RD,</div><div class='add'>+				XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16014440446"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_DENY |</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_RANGE_64),</div><div class='add'>+			 WHITELIST(XE_REG(0x4500),</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_DENY |</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_RANGE_64))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16017236439"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),</div><div class='add'>+	  XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),</div><div class='add'>+				   RING_FORCE_TO_NONPRIV_DENY,</div><div class='add'>+				   XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+	},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_reg_whitelist_process_engine - process table of registers to whitelist</div><div class='add'>+ * @hwe: engine instance to process whitelist for</div><div class='add'>+ *</div><div class='add'>+ * Process wwhitelist table for this platform, saving in @hwe all the</div><div class='add'>+ * registers that need to be whitelisted by the hardware so they can be accessed</div><div class='add'>+ * by userspace.</div><div class='add'>+ */</div><div class='add'>+void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, register_whitelist, &amp;hwe-&gt;reg_whitelist);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_reg_whitelist_print_entry - print one whitelist entry</div><div class='add'>+ * @p: DRM printer</div><div class='add'>+ * @indent: indent level</div><div class='add'>+ * @reg: register allowed/denied</div><div class='add'>+ * @entry: save-restore entry</div><div class='add'>+ *</div><div class='add'>+ * Print details about the entry added to allow/deny access</div><div class='add'>+ */</div><div class='add'>+void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,</div><div class='add'>+				  u32 reg, struct xe_reg_sr_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 val = entry-&gt;set_bits;</div><div class='add'>+	const char *access_str = "(invalid)";</div><div class='add'>+	unsigned int range_bit = 2;</div><div class='add'>+	u32 range_start, range_end;</div><div class='add'>+	bool deny;</div><div class='add'>+</div><div class='add'>+	deny = val &amp; RING_FORCE_TO_NONPRIV_DENY;</div><div class='add'>+</div><div class='add'>+	switch (val &amp; RING_FORCE_TO_NONPRIV_RANGE_MASK) {</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_RANGE_4:</div><div class='add'>+		range_bit = 4;</div><div class='add'>+		break;</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_RANGE_16:</div><div class='add'>+		range_bit = 6;</div><div class='add'>+		break;</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_RANGE_64:</div><div class='add'>+		range_bit = 8;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	range_start = reg &amp; REG_GENMASK(25, range_bit);</div><div class='add'>+	range_end = range_start | REG_GENMASK(range_bit, 0);</div><div class='add'>+</div><div class='add'>+	switch (val &amp; RING_FORCE_TO_NONPRIV_ACCESS_MASK) {</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_ACCESS_RW:</div><div class='add'>+		access_str = "rw";</div><div class='add'>+		break;</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_ACCESS_RD:</div><div class='add'>+		access_str = "read";</div><div class='add'>+		break;</div><div class='add'>+	case RING_FORCE_TO_NONPRIV_ACCESS_WR:</div><div class='add'>+		access_str = "write";</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",</div><div class='add'>+			  range_start, range_end,</div><div class='add'>+			  deny ? "deny" : "allow",</div><div class='add'>+			  access_str);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_reg_whitelist_dump - print all whitelist entries</div><div class='add'>+ * @sr: Save/restore entries</div><div class='add'>+ * @p: DRM printer</div><div class='add'>+ */</div><div class='add'>+void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr_entry *entry;</div><div class='add'>+	unsigned long reg;</div><div class='add'>+</div><div class='add'>+	if (!sr-&gt;name || xa_empty(&amp;sr-&gt;xa))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "%s\n", sr-&gt;name);</div><div class='add'>+	xa_for_each(&amp;sr-&gt;xa, reg, entry)</div><div class='add'>+		xe_reg_whitelist_print_entry(p, 1, reg, entry);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h<br/>new file mode 100644<br/>index 000000000000..69b121d377da<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_reg_whitelist.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_reg_whitelist.h</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_REG_WHITELIST_</div><div class='add'>+#define _XE_REG_WHITELIST_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_reg_sr;</div><div class='add'>+struct xe_reg_sr_entry;</div><div class='add'>+</div><div class='add'>+void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,</div><div class='add'>+				  u32 reg, struct xe_reg_sr_entry *entry);</div><div class='add'>+</div><div class='add'>+void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res_cursor.h<br/>new file mode 100644<br/>index 000000000000..0a306963aa8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_res_cursor.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_res_cursor.h</a></div><div class='hunk'>@@ -0,0 +1,240 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2020 Advanced Micro Devices, Inc.</div><div class='add'>+ *</div><div class='add'>+ * Permission is hereby granted, free of charge, to any person obtaining a</div><div class='add'>+ * copy of this software and associated documentation files (the "Software"),</div><div class='add'>+ * to deal in the Software without restriction, including without limitation</div><div class='add'>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,</div><div class='add'>+ * and/or sell copies of the Software, and to permit persons to whom the</div><div class='add'>+ * Software is furnished to do so, subject to the following conditions:</div><div class='add'>+ *</div><div class='add'>+ * The above copyright notice and this permission notice shall be included in</div><div class='add'>+ * all copies or substantial portions of the Software.</div><div class='add'>+ *</div><div class='add'>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR</div><div class='add'>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,</div><div class='add'>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL</div><div class='add'>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR</div><div class='add'>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</div><div class='add'>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</div><div class='add'>+ * OTHER DEALINGS IN THE SOFTWARE.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RES_CURSOR_H_</div><div class='add'>+#define _XE_RES_CURSOR_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/scatterlist.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_range_manager.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_resource.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+</div><div class='add'>+/* state back for walking over vram_mgr, stolen_mgr, and gtt_mgr allocations */</div><div class='add'>+struct xe_res_cursor {</div><div class='add'>+	u64 start;</div><div class='add'>+	u64 size;</div><div class='add'>+	u64 remaining;</div><div class='add'>+	void *node;</div><div class='add'>+	u32 mem_type;</div><div class='add'>+	struct scatterlist *sgl;</div><div class='add'>+	struct drm_buddy *mm;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct drm_buddy *xe_res_get_buddy(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *mgr;</div><div class='add'>+</div><div class='add'>+	mgr = ttm_manager_type(res-&gt;bo-&gt;bdev, res-&gt;mem_type);</div><div class='add'>+	return &amp;to_xe_ttm_vram_mgr(mgr)-&gt;mm;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_res_first - initialize a xe_res_cursor</div><div class='add'>+ *</div><div class='add'>+ * @res: TTM resource object to walk</div><div class='add'>+ * @start: Start of the range</div><div class='add'>+ * @size: Size of the range</div><div class='add'>+ * @cur: cursor object to initialize</div><div class='add'>+ *</div><div class='add'>+ * Start walking over the range of allocations between @start and @size.</div><div class='add'>+ */</div><div class='add'>+static inline void xe_res_first(struct ttm_resource *res,</div><div class='add'>+				u64 start, u64 size,</div><div class='add'>+				struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	cur-&gt;sgl = NULL;</div><div class='add'>+	if (!res)</div><div class='add'>+		goto fallback;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(start + size &gt; res-&gt;size);</div><div class='add'>+</div><div class='add'>+	cur-&gt;mem_type = res-&gt;mem_type;</div><div class='add'>+</div><div class='add'>+	switch (cur-&gt;mem_type) {</div><div class='add'>+	case XE_PL_STOLEN:</div><div class='add'>+	case XE_PL_VRAM0:</div><div class='add'>+	case XE_PL_VRAM1: {</div><div class='add'>+		struct drm_buddy_block *block;</div><div class='add'>+		struct list_head *head, *next;</div><div class='add'>+		struct drm_buddy *mm = xe_res_get_buddy(res);</div><div class='add'>+</div><div class='add'>+		head = &amp;to_xe_ttm_vram_mgr_resource(res)-&gt;blocks;</div><div class='add'>+</div><div class='add'>+		block = list_first_entry_or_null(head,</div><div class='add'>+						 struct drm_buddy_block,</div><div class='add'>+						 link);</div><div class='add'>+		if (!block)</div><div class='add'>+			goto fallback;</div><div class='add'>+</div><div class='add'>+		while (start &gt;= drm_buddy_block_size(mm, block)) {</div><div class='add'>+			start -= drm_buddy_block_size(mm, block);</div><div class='add'>+</div><div class='add'>+			next = block-&gt;link.next;</div><div class='add'>+			if (next != head)</div><div class='add'>+				block = list_entry(next, struct drm_buddy_block,</div><div class='add'>+						   link);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cur-&gt;mm = mm;</div><div class='add'>+		cur-&gt;start = drm_buddy_block_offset(block) + start;</div><div class='add'>+		cur-&gt;size = min(drm_buddy_block_size(mm, block) - start,</div><div class='add'>+				size);</div><div class='add'>+		cur-&gt;remaining = size;</div><div class='add'>+		cur-&gt;node = block;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	default:</div><div class='add'>+		goto fallback;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+fallback:</div><div class='add'>+	cur-&gt;start = start;</div><div class='add'>+	cur-&gt;size = size;</div><div class='add'>+	cur-&gt;remaining = size;</div><div class='add'>+	cur-&gt;node = NULL;</div><div class='add'>+	cur-&gt;mem_type = XE_PL_TT;</div><div class='add'>+	XE_WARN_ON(res &amp;&amp; start + size &gt; res-&gt;size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __xe_res_sg_next(struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	struct scatterlist *sgl = cur-&gt;sgl;</div><div class='add'>+	u64 start = cur-&gt;start;</div><div class='add'>+</div><div class='add'>+	while (start &gt;= sg_dma_len(sgl)) {</div><div class='add'>+		start -= sg_dma_len(sgl);</div><div class='add'>+		sgl = sg_next(sgl);</div><div class='add'>+		XE_WARN_ON(!sgl);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cur-&gt;start = start;</div><div class='add'>+	cur-&gt;size = sg_dma_len(sgl) - start;</div><div class='add'>+	cur-&gt;sgl = sgl;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_res_first_sg - initialize a xe_res_cursor with a scatter gather table</div><div class='add'>+ *</div><div class='add'>+ * @sg: scatter gather table to walk</div><div class='add'>+ * @start: Start of the range</div><div class='add'>+ * @size: Size of the range</div><div class='add'>+ * @cur: cursor object to initialize</div><div class='add'>+ *</div><div class='add'>+ * Start walking over the range of allocations between @start and @size.</div><div class='add'>+ */</div><div class='add'>+static inline void xe_res_first_sg(const struct sg_table *sg,</div><div class='add'>+				   u64 start, u64 size,</div><div class='add'>+				   struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(!sg);</div><div class='add'>+	XE_WARN_ON(!IS_ALIGNED(start, PAGE_SIZE) ||</div><div class='add'>+		   !IS_ALIGNED(size, PAGE_SIZE));</div><div class='add'>+	cur-&gt;node = NULL;</div><div class='add'>+	cur-&gt;start = start;</div><div class='add'>+	cur-&gt;remaining = size;</div><div class='add'>+	cur-&gt;size = 0;</div><div class='add'>+	cur-&gt;sgl = sg-&gt;sgl;</div><div class='add'>+	cur-&gt;mem_type = XE_PL_TT;</div><div class='add'>+	__xe_res_sg_next(cur);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_res_next - advance the cursor</div><div class='add'>+ *</div><div class='add'>+ * @cur: the cursor to advance</div><div class='add'>+ * @size: number of bytes to move forward</div><div class='add'>+ *</div><div class='add'>+ * Move the cursor @size bytes forwrad, walking to the next node if necessary.</div><div class='add'>+ */</div><div class='add'>+static inline void xe_res_next(struct xe_res_cursor *cur, u64 size)</div><div class='add'>+{</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+	struct list_head *next;</div><div class='add'>+	u64 start;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(size &gt; cur-&gt;remaining);</div><div class='add'>+</div><div class='add'>+	cur-&gt;remaining -= size;</div><div class='add'>+	if (!cur-&gt;remaining)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (cur-&gt;size &gt; size) {</div><div class='add'>+		cur-&gt;size -= size;</div><div class='add'>+		cur-&gt;start += size;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cur-&gt;sgl) {</div><div class='add'>+		cur-&gt;start += size;</div><div class='add'>+		__xe_res_sg_next(cur);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (cur-&gt;mem_type) {</div><div class='add'>+	case XE_PL_STOLEN:</div><div class='add'>+	case XE_PL_VRAM0:</div><div class='add'>+	case XE_PL_VRAM1:</div><div class='add'>+		start = size - cur-&gt;size;</div><div class='add'>+		block = cur-&gt;node;</div><div class='add'>+</div><div class='add'>+		next = block-&gt;link.next;</div><div class='add'>+		block = list_entry(next, struct drm_buddy_block, link);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+		while (start &gt;= drm_buddy_block_size(cur-&gt;mm, block)) {</div><div class='add'>+			start -= drm_buddy_block_size(cur-&gt;mm, block);</div><div class='add'>+</div><div class='add'>+			next = block-&gt;link.next;</div><div class='add'>+			block = list_entry(next, struct drm_buddy_block, link);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cur-&gt;start = drm_buddy_block_offset(block) + start;</div><div class='add'>+		cur-&gt;size = min(drm_buddy_block_size(cur-&gt;mm, block) - start,</div><div class='add'>+				cur-&gt;remaining);</div><div class='add'>+		cur-&gt;node = block;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_res_dma - return dma address of cursor at current position</div><div class='add'>+ *</div><div class='add'>+ * @cur: the cursor to return the dma address from</div><div class='add'>+ */</div><div class='add'>+static inline u64 xe_res_dma(const struct xe_res_cursor *cur)</div><div class='add'>+{</div><div class='add'>+	return cur-&gt;sgl ? sg_dma_address(cur-&gt;sgl) + cur-&gt;start : cur-&gt;start;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c<br/>new file mode 100644<br/>index 000000000000..1e4c06eacd98<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ring_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops.c</a></div><div class='hunk'>@@ -0,0 +1,482 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_ring_ops.h"</div><div class='add'>+</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "instructions/xe_mi_commands.h"</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gpu_commands.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_lrc_layout.h"</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_vm_types.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * 3D-related flags that can't be set on _engines_ that lack access to the 3D</div><div class='add'>+ * pipeline (i.e., CCS engines).</div><div class='add'>+ */</div><div class='add'>+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\</div><div class='add'>+		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \</div><div class='add'>+		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \</div><div class='add'>+		PIPE_CONTROL_TILE_CACHE_FLUSH | \</div><div class='add'>+		PIPE_CONTROL_DEPTH_STALL | \</div><div class='add'>+		PIPE_CONTROL_STALL_AT_SCOREBOARD | \</div><div class='add'>+		PIPE_CONTROL_PSD_SYNC | \</div><div class='add'>+		PIPE_CONTROL_AMFS_FLUSH | \</div><div class='add'>+		PIPE_CONTROL_VF_CACHE_INVALIDATE | \</div><div class='add'>+		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)</div><div class='add'>+</div><div class='add'>+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */</div><div class='add'>+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \</div><div class='add'>+		PIPE_CONTROL_3D_ENGINE_FLAGS | \</div><div class='add'>+		PIPE_CONTROL_INDIRECT_STATE_DISABLE | \</div><div class='add'>+		PIPE_CONTROL_FLUSH_ENABLE | \</div><div class='add'>+		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \</div><div class='add'>+		PIPE_CONTROL_DC_FLUSH_ENABLE)</div><div class='add'>+</div><div class='add'>+static u32 preparser_disable(bool state)</div><div class='add'>+{</div><div class='add'>+	return MI_ARB_CHECK | BIT(8) | state;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,</div><div class='add'>+			      u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;</div><div class='add'>+	dw[i++] = reg.addr + gt-&gt;mmio.adj_offset;</div><div class='add'>+	dw[i++] = AUX_INV;</div><div class='add'>+	dw[i++] = MI_NOOP;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_user_interrupt(u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_USER_INTERRUPT;</div><div class='add'>+	dw[i++] = MI_ARB_ON_OFF | MI_ARB_ENABLE;</div><div class='add'>+	dw[i++] = MI_ARB_CHECK;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);</div><div class='add'>+	dw[i++] = addr;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = value;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,</div><div class='add'>+			       u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |</div><div class='add'>+		(invalidate_tlb ? MI_INVALIDATE_TLB : 0);</div><div class='add'>+	dw[i++] = addr | MI_FLUSH_DW_USE_GTT;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = value;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);</div><div class='add'>+	dw[i++] = lower_32_bits(batch_addr);</div><div class='add'>+	dw[i++] = upper_32_bits(batch_addr);</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_flush_invalidate(u32 flag, u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i] = MI_FLUSH_DW;</div><div class='add'>+	dw[i] |= flag;</div><div class='add'>+	dw[i++] |= MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |</div><div class='add'>+		MI_FLUSH_DW_STORE_INDEX;</div><div class='add'>+</div><div class='add'>+	dw[i++] = LRC_PPHWSP_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = ~0U;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,</div><div class='add'>+				int i)</div><div class='add'>+{</div><div class='add'>+	u32 flags = PIPE_CONTROL_CS_STALL |</div><div class='add'>+		PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_VF_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_CONST_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_STATE_CACHE_INVALIDATE |</div><div class='add'>+		PIPE_CONTROL_QW_WRITE |</div><div class='add'>+		PIPE_CONTROL_STORE_DATA_INDEX;</div><div class='add'>+</div><div class='add'>+	if (invalidate_tlb)</div><div class='add'>+		flags |= PIPE_CONTROL_TLB_INVALIDATE;</div><div class='add'>+</div><div class='add'>+	flags &amp;= ~mask_flags;</div><div class='add'>+</div><div class='add'>+	dw[i++] = GFX_OP_PIPE_CONTROL(6);</div><div class='add'>+	dw[i++] = flags;</div><div class='add'>+	dw[i++] = LRC_PPHWSP_SCRATCH_ADDR;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,</div><div class='add'>+				       u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);</div><div class='add'>+	dw[i++] = lower_32_bits(addr);</div><div class='add'>+	dw[i++] = upper_32_bits(addr);</div><div class='add'>+	dw[i++] = lower_32_bits(value);</div><div class='add'>+	dw[i++] = upper_32_bits(value);</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = job-&gt;q-&gt;gt;</div><div class='add'>+	bool lacks_render = !(gt-&gt;info.engine_mask &amp; XE_HW_ENGINE_RCS_MASK);</div><div class='add'>+	u32 flags;</div><div class='add'>+</div><div class='add'>+	flags = (PIPE_CONTROL_CS_STALL |</div><div class='add'>+		 PIPE_CONTROL_TILE_CACHE_FLUSH |</div><div class='add'>+		 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |</div><div class='add'>+		 PIPE_CONTROL_DEPTH_CACHE_FLUSH |</div><div class='add'>+		 PIPE_CONTROL_DC_FLUSH_ENABLE |</div><div class='add'>+		 PIPE_CONTROL_FLUSH_ENABLE);</div><div class='add'>+</div><div class='add'>+	if (XE_WA(gt, 1409600907))</div><div class='add'>+		flags |= PIPE_CONTROL_DEPTH_STALL;</div><div class='add'>+</div><div class='add'>+	if (lacks_render)</div><div class='add'>+		flags &amp;= ~PIPE_CONTROL_3D_ARCH_FLAGS;</div><div class='add'>+	else if (job-&gt;q-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+		flags &amp;= ~PIPE_CONTROL_3D_ENGINE_FLAGS;</div><div class='add'>+</div><div class='add'>+	dw[i++] = GFX_OP_PIPE_CONTROL(6) | PIPE_CONTROL0_HDC_PIPELINE_FLUSH;</div><div class='add'>+	dw[i++] = flags;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)</div><div class='add'>+{</div><div class='add'>+	if (hwe-&gt;class != XE_ENGINE_CLASS_RENDER)</div><div class='add'>+		return i;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(hwe-&gt;gt, 16020292621)) {</div><div class='add'>+		dw[i++] = GFX_OP_PIPE_CONTROL(6);</div><div class='add'>+		dw[i++] = PIPE_CONTROL_LRI_POST_SYNC;</div><div class='add'>+		dw[i++] = RING_NOPID(hwe-&gt;mmio_base).addr;</div><div class='add'>+		dw[i++] = 0;</div><div class='add'>+		dw[i++] = 0;</div><div class='add'>+		dw[i++] = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,</div><div class='add'>+			      int i)</div><div class='add'>+{</div><div class='add'>+	dw[i++] = GFX_OP_PIPE_CONTROL(6);</div><div class='add'>+	dw[i++] = (stall_only ? PIPE_CONTROL_CS_STALL :</div><div class='add'>+		   PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL) |</div><div class='add'>+		PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE;</div><div class='add'>+	dw[i++] = addr;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = value;</div><div class='add'>+	dw[i++] = 0; /* We're thrashing one extra dword. */</div><div class='add'>+</div><div class='add'>+	return i;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_ppgtt_flag(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	return job-&gt;q-&gt;vm ? BIT(8) : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */</div><div class='add'>+static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,</div><div class='add'>+				    u64 batch_addr, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	u32 dw[MAX_JOB_SIZE_DW], i = 0;</div><div class='add'>+	u32 ppgtt_flag = get_ppgtt_flag(job);</div><div class='add'>+	struct xe_vm *vm = job-&gt;q-&gt;vm;</div><div class='add'>+	struct xe_gt *gt = job-&gt;q-&gt;gt;</div><div class='add'>+</div><div class='add'>+	if (vm &amp;&amp; vm-&gt;batch_invalidate_tlb) {</div><div class='add'>+		dw[i++] = preparser_disable(true);</div><div class='add'>+		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+					seqno, true, dw, i);</div><div class='add'>+		dw[i++] = preparser_disable(false);</div><div class='add'>+	} else {</div><div class='add'>+		i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+					seqno, dw, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);</div><div class='add'>+</div><div class='add'>+	if (job-&gt;user_fence.used)</div><div class='add'>+		i = emit_store_imm_ppgtt_posted(job-&gt;user_fence.addr,</div><div class='add'>+						job-&gt;user_fence.value,</div><div class='add'>+						dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_user_interrupt(dw, i);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, i &lt;= MAX_JOB_SIZE_DW);</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool has_aux_ccs(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * PVC is a special case that has no compression of either type</div><div class='add'>+	 * (FlatCCS or AuxCCS).  Also, AuxCCS is no longer used from Xe2</div><div class='add'>+	 * onward, so any future platforms with no FlatCCS will not have</div><div class='add'>+	 * AuxCCS either.</div><div class='add'>+	 */</div><div class='add'>+	if (GRAPHICS_VER(xe) &gt;= 20 || xe-&gt;info.platform == XE_PVC)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return !xe-&gt;info.has_flat_ccs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,</div><div class='add'>+				   u64 batch_addr, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	u32 dw[MAX_JOB_SIZE_DW], i = 0;</div><div class='add'>+	u32 ppgtt_flag = get_ppgtt_flag(job);</div><div class='add'>+	struct xe_gt *gt = job-&gt;q-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	bool decode = job-&gt;q-&gt;class == XE_ENGINE_CLASS_VIDEO_DECODE;</div><div class='add'>+	struct xe_vm *vm = job-&gt;q-&gt;vm;</div><div class='add'>+</div><div class='add'>+	dw[i++] = preparser_disable(true);</div><div class='add'>+</div><div class='add'>+	/* hsdes: 1809175790 */</div><div class='add'>+	if (has_aux_ccs(xe)) {</div><div class='add'>+		if (decode)</div><div class='add'>+			i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i);</div><div class='add'>+		else</div><div class='add'>+			i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vm &amp;&amp; vm-&gt;batch_invalidate_tlb)</div><div class='add'>+		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+					seqno, true, dw, i);</div><div class='add'>+</div><div class='add'>+	dw[i++] = preparser_disable(false);</div><div class='add'>+</div><div class='add'>+	if (!vm || !vm-&gt;batch_invalidate_tlb)</div><div class='add'>+		i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+					seqno, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);</div><div class='add'>+</div><div class='add'>+	if (job-&gt;user_fence.used)</div><div class='add'>+		i = emit_store_imm_ppgtt_posted(job-&gt;user_fence.addr,</div><div class='add'>+						job-&gt;user_fence.value,</div><div class='add'>+						dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_user_interrupt(dw, i);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, i &lt;= MAX_JOB_SIZE_DW);</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __emit_job_gen12_render_compute(struct xe_sched_job *job,</div><div class='add'>+					    struct xe_lrc *lrc,</div><div class='add'>+					    u64 batch_addr, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	u32 dw[MAX_JOB_SIZE_DW], i = 0;</div><div class='add'>+	u32 ppgtt_flag = get_ppgtt_flag(job);</div><div class='add'>+	struct xe_gt *gt = job-&gt;q-&gt;gt;</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	bool lacks_render = !(gt-&gt;info.engine_mask &amp; XE_HW_ENGINE_RCS_MASK);</div><div class='add'>+	struct xe_vm *vm = job-&gt;q-&gt;vm;</div><div class='add'>+	u32 mask_flags = 0;</div><div class='add'>+</div><div class='add'>+	dw[i++] = preparser_disable(true);</div><div class='add'>+	if (lacks_render)</div><div class='add'>+		mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;</div><div class='add'>+	else if (job-&gt;q-&gt;class == XE_ENGINE_CLASS_COMPUTE)</div><div class='add'>+		mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS;</div><div class='add'>+</div><div class='add'>+	/* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */</div><div class='add'>+	i = emit_pipe_invalidate(mask_flags, vm &amp;&amp; vm-&gt;batch_invalidate_tlb, dw, i);</div><div class='add'>+</div><div class='add'>+	/* hsdes: 1809175790 */</div><div class='add'>+	if (has_aux_ccs(xe))</div><div class='add'>+		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);</div><div class='add'>+</div><div class='add'>+	dw[i++] = preparser_disable(false);</div><div class='add'>+</div><div class='add'>+	i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+				seqno, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_render_cache_flush(job, dw, i);</div><div class='add'>+</div><div class='add'>+	if (job-&gt;user_fence.used)</div><div class='add'>+		i = emit_store_imm_ppgtt_posted(job-&gt;user_fence.addr,</div><div class='add'>+						job-&gt;user_fence.value,</div><div class='add'>+						dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_pipe_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_user_interrupt(dw, i);</div><div class='add'>+</div><div class='add'>+	i = emit_pipe_control_to_ring_end(job-&gt;q-&gt;hwe, dw, i);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, i &lt;= MAX_JOB_SIZE_DW);</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_migration_job_gen12(struct xe_sched_job *job,</div><div class='add'>+				     struct xe_lrc *lrc, u32 seqno)</div><div class='add'>+{</div><div class='add'>+	u32 dw[MAX_JOB_SIZE_DW], i = 0;</div><div class='add'>+</div><div class='add'>+	i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),</div><div class='add'>+				seqno, dw, i);</div><div class='add'>+</div><div class='add'>+	dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */</div><div class='add'>+</div><div class='add'>+	i = emit_bb_start(job-&gt;batch_addr[0], BIT(8), dw, i);</div><div class='add'>+</div><div class='add'>+	/* XXX: Do we need this? Leaving for now. */</div><div class='add'>+	dw[i++] = preparser_disable(true);</div><div class='add'>+	i = emit_flush_invalidate(0, dw, i);</div><div class='add'>+	dw[i++] = preparser_disable(false);</div><div class='add'>+</div><div class='add'>+	i = emit_bb_start(job-&gt;batch_addr[1], BIT(8), dw, i);</div><div class='add'>+</div><div class='add'>+	dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | job-&gt;migrate_flush_flags |</div><div class='add'>+		MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW;</div><div class='add'>+	dw[i++] = xe_lrc_seqno_ggtt_addr(lrc) | MI_FLUSH_DW_USE_GTT;</div><div class='add'>+	dw[i++] = 0;</div><div class='add'>+	dw[i++] = seqno; /* value */</div><div class='add'>+</div><div class='add'>+	i = emit_user_interrupt(dw, i);</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(job-&gt;q-&gt;gt, i &lt;= MAX_JOB_SIZE_DW);</div><div class='add'>+</div><div class='add'>+	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_job_gen12_gsc(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = job-&gt;q-&gt;gt;</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, job-&gt;q-&gt;width &lt;= 1); /* no parallel submission for GSCCS */</div><div class='add'>+</div><div class='add'>+	__emit_job_gen12_simple(job, job-&gt;q-&gt;lrc,</div><div class='add'>+				job-&gt;batch_addr[0],</div><div class='add'>+				xe_sched_job_seqno(job));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_job_gen12_copy(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (xe_sched_job_is_migration(job-&gt;q)) {</div><div class='add'>+		emit_migration_job_gen12(job, job-&gt;q-&gt;lrc,</div><div class='add'>+					 xe_sched_job_seqno(job));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; job-&gt;q-&gt;width; ++i)</div><div class='add'>+		__emit_job_gen12_simple(job, job-&gt;q-&gt;lrc + i,</div><div class='add'>+				        job-&gt;batch_addr[i],</div><div class='add'>+				        xe_sched_job_seqno(job));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_job_gen12_video(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* FIXME: Not doing parallel handshake for now */</div><div class='add'>+	for (i = 0; i &lt; job-&gt;q-&gt;width; ++i)</div><div class='add'>+		__emit_job_gen12_video(job, job-&gt;q-&gt;lrc + i,</div><div class='add'>+				       job-&gt;batch_addr[i],</div><div class='add'>+				       xe_sched_job_seqno(job));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void emit_job_gen12_render_compute(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; job-&gt;q-&gt;width; ++i)</div><div class='add'>+		__emit_job_gen12_render_compute(job, job-&gt;q-&gt;lrc + i,</div><div class='add'>+						job-&gt;batch_addr[i],</div><div class='add'>+						xe_sched_job_seqno(job));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_ring_ops ring_ops_gen12_gsc = {</div><div class='add'>+	.emit_job = emit_job_gen12_gsc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_ring_ops ring_ops_gen12_copy = {</div><div class='add'>+	.emit_job = emit_job_gen12_copy,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_ring_ops ring_ops_gen12_video = {</div><div class='add'>+	.emit_job = emit_job_gen12_video,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_ring_ops ring_ops_gen12_render_compute = {</div><div class='add'>+	.emit_job = emit_job_gen12_render_compute,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct xe_ring_ops *</div><div class='add'>+xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class)</div><div class='add'>+{</div><div class='add'>+	switch (class) {</div><div class='add'>+	case XE_ENGINE_CLASS_OTHER:</div><div class='add'>+		return &amp;ring_ops_gen12_gsc;</div><div class='add'>+	case XE_ENGINE_CLASS_COPY:</div><div class='add'>+		return &amp;ring_ops_gen12_copy;</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_DECODE:</div><div class='add'>+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:</div><div class='add'>+		return &amp;ring_ops_gen12_video;</div><div class='add'>+	case XE_ENGINE_CLASS_RENDER:</div><div class='add'>+	case XE_ENGINE_CLASS_COMPUTE:</div><div class='add'>+		return &amp;ring_ops_gen12_render_compute;</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ring_ops.h b/drivers/gpu/drm/xe/xe_ring_ops.h<br/>new file mode 100644<br/>index 000000000000..e942735d76a6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ring_ops.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops.h</a></div><div class='hunk'>@@ -0,0 +1,17 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RING_OPS_H_</div><div class='add'>+#define _XE_RING_OPS_H_</div><div class='add'>+</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_ring_ops_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+const struct xe_ring_ops *</div><div class='add'>+xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h<br/>new file mode 100644<br/>index 000000000000..1ae56e2ee7b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ring_ops_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ring_ops_types.h</a></div><div class='hunk'>@@ -0,0 +1,22 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RING_OPS_TYPES_H_</div><div class='add'>+#define _XE_RING_OPS_TYPES_H_</div><div class='add'>+</div><div class='add'>+struct xe_sched_job;</div><div class='add'>+</div><div class='add'>+#define MAX_JOB_SIZE_DW 48</div><div class='add'>+#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_ring_ops - Ring operations</div><div class='add'>+ */</div><div class='add'>+struct xe_ring_ops {</div><div class='add'>+	/** @emit_job: Write job to ring */</div><div class='add'>+	void (*emit_job)(struct xe_sched_job *job);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c<br/>new file mode 100644<br/>index 000000000000..fb44cc7521d8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_rtp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp.c</a></div><div class='hunk'>@@ -0,0 +1,325 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_topology.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_reg_sr.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Register Table Processing</div><div class='add'>+ *</div><div class='add'>+ * Internal infrastructure to define how registers should be updated based on</div><div class='add'>+ * rules and actions. This can be used to define tables with multiple entries</div><div class='add'>+ * (one per register) that will be walked over at some point in time to apply</div><div class='add'>+ * the values to the registers that have matching rules.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static bool has_samedia(const struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe-&gt;info.media_verx100 &gt;= 1300;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool rule_matches(const struct xe_device *xe,</div><div class='add'>+			 struct xe_gt *gt,</div><div class='add'>+			 struct xe_hw_engine *hwe,</div><div class='add'>+			 const struct xe_rtp_rule *rules,</div><div class='add'>+			 unsigned int n_rules)</div><div class='add'>+{</div><div class='add'>+	const struct xe_rtp_rule *r;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	bool match;</div><div class='add'>+</div><div class='add'>+	for (r = rules, i = 0; i &lt; n_rules; r = &amp;rules[++i]) {</div><div class='add'>+		switch (r-&gt;match_type) {</div><div class='add'>+		case XE_RTP_MATCH_PLATFORM:</div><div class='add'>+			match = xe-&gt;info.platform == r-&gt;platform;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_SUBPLATFORM:</div><div class='add'>+			match = xe-&gt;info.platform == r-&gt;platform &amp;&amp;</div><div class='add'>+				xe-&gt;info.subplatform == r-&gt;subplatform;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_GRAPHICS_VERSION:</div><div class='add'>+			match = xe-&gt;info.graphics_verx100 == r-&gt;ver_start &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || !xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_GRAPHICS_VERSION_RANGE:</div><div class='add'>+			match = xe-&gt;info.graphics_verx100 &gt;= r-&gt;ver_start &amp;&amp;</div><div class='add'>+				xe-&gt;info.graphics_verx100 &lt;= r-&gt;ver_end &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || !xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_GRAPHICS_STEP:</div><div class='add'>+			match = xe-&gt;info.step.graphics &gt;= r-&gt;step_start &amp;&amp;</div><div class='add'>+				xe-&gt;info.step.graphics &lt; r-&gt;step_end &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || !xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_MEDIA_VERSION:</div><div class='add'>+			match = xe-&gt;info.media_verx100 == r-&gt;ver_start &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_MEDIA_VERSION_RANGE:</div><div class='add'>+			match = xe-&gt;info.media_verx100 &gt;= r-&gt;ver_start &amp;&amp;</div><div class='add'>+				xe-&gt;info.media_verx100 &lt;= r-&gt;ver_end &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_MEDIA_STEP:</div><div class='add'>+			match = xe-&gt;info.step.media &gt;= r-&gt;step_start &amp;&amp;</div><div class='add'>+				xe-&gt;info.step.media &lt; r-&gt;step_end &amp;&amp;</div><div class='add'>+				(!has_samedia(xe) || xe_gt_is_media_type(gt));</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_INTEGRATED:</div><div class='add'>+			match = !xe-&gt;info.is_dgfx;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_DISCRETE:</div><div class='add'>+			match = xe-&gt;info.is_dgfx;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_ENGINE_CLASS:</div><div class='add'>+			if (drm_WARN_ON(&amp;xe-&gt;drm, !hwe))</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='add'>+			match = hwe-&gt;class == r-&gt;engine_class;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_NOT_ENGINE_CLASS:</div><div class='add'>+			if (drm_WARN_ON(&amp;xe-&gt;drm, !hwe))</div><div class='add'>+				return false;</div><div class='add'>+</div><div class='add'>+			match = hwe-&gt;class != r-&gt;engine_class;</div><div class='add'>+			break;</div><div class='add'>+		case XE_RTP_MATCH_FUNC:</div><div class='add'>+			match = r-&gt;match_func(gt, hwe);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm, "Invalid RTP match %u\n",</div><div class='add'>+				 r-&gt;match_type);</div><div class='add'>+			match = false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!match)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtp_add_sr_entry(const struct xe_rtp_action *action,</div><div class='add'>+			     struct xe_gt *gt,</div><div class='add'>+			     u32 mmio_base,</div><div class='add'>+			     struct xe_reg_sr *sr)</div><div class='add'>+{</div><div class='add'>+	struct xe_reg_sr_entry sr_entry = {</div><div class='add'>+		.reg = action-&gt;reg,</div><div class='add'>+		.clr_bits = action-&gt;clr_bits,</div><div class='add'>+		.set_bits = action-&gt;set_bits,</div><div class='add'>+		.read_mask = action-&gt;read_mask,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	sr_entry.reg.addr += mmio_base;</div><div class='add'>+	xe_reg_sr_add(sr, &amp;sr_entry, gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool rtp_process_one_sr(const struct xe_rtp_entry_sr *entry,</div><div class='add'>+			       struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+			       struct xe_hw_engine *hwe, struct xe_reg_sr *sr)</div><div class='add'>+{</div><div class='add'>+	const struct xe_rtp_action *action;</div><div class='add'>+	u32 mmio_base;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (!rule_matches(xe, gt, hwe, entry-&gt;rules, entry-&gt;n_rules))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	for (i = 0, action = &amp;entry-&gt;actions[0]; i &lt; entry-&gt;n_actions; action++, i++) {</div><div class='add'>+		if ((entry-&gt;flags &amp; XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) ||</div><div class='add'>+		    (action-&gt;flags &amp; XE_RTP_ACTION_FLAG_ENGINE_BASE))</div><div class='add'>+			mmio_base = hwe-&gt;mmio_base;</div><div class='add'>+		else</div><div class='add'>+			mmio_base = 0;</div><div class='add'>+</div><div class='add'>+		rtp_add_sr_entry(action, gt, mmio_base, sr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtp_get_context(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+			    struct xe_hw_engine **hwe,</div><div class='add'>+			    struct xe_gt **gt,</div><div class='add'>+			    struct xe_device **xe)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;type) {</div><div class='add'>+	case XE_RTP_PROCESS_TYPE_GT:</div><div class='add'>+		*hwe = NULL;</div><div class='add'>+		*gt = ctx-&gt;gt;</div><div class='add'>+		*xe = gt_to_xe(*gt);</div><div class='add'>+		break;</div><div class='add'>+	case XE_RTP_PROCESS_TYPE_ENGINE:</div><div class='add'>+		*hwe = ctx-&gt;hwe;</div><div class='add'>+		*gt = (*hwe)-&gt;gt;</div><div class='add'>+		*xe = gt_to_xe(*gt);</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_rtp_process_ctx_enable_active_tracking - Enable tracking of active entries</div><div class='add'>+ *</div><div class='add'>+ * Set additional metadata to track what entries are considered "active", i.e.</div><div class='add'>+ * their rules match the condition. Bits are never cleared: entries with</div><div class='add'>+ * matching rules set the corresponding bit in the bitmap.</div><div class='add'>+ *</div><div class='add'>+ * @ctx: The context for processing the table</div><div class='add'>+ * @active_entries: bitmap to store the active entries</div><div class='add'>+ * @n_entries: number of entries to be processed</div><div class='add'>+ */</div><div class='add'>+void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+					       unsigned long *active_entries,</div><div class='add'>+					       size_t n_entries)</div><div class='add'>+{</div><div class='add'>+	ctx-&gt;active_entries = active_entries;</div><div class='add'>+	ctx-&gt;n_entries = n_entries;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtp_mark_active(struct xe_device *xe,</div><div class='add'>+			    struct xe_rtp_process_ctx *ctx,</div><div class='add'>+			    unsigned int first, unsigned int last)</div><div class='add'>+{</div><div class='add'>+	if (!ctx-&gt;active_entries)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, last &gt; ctx-&gt;n_entries))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (first == last)</div><div class='add'>+		bitmap_set(ctx-&gt;active_entries, first, 1);</div><div class='add'>+	else</div><div class='add'>+		bitmap_set(ctx-&gt;active_entries, first, last - first + 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_rtp_process_to_sr - Process all rtp @entries, adding the matching ones to</div><div class='add'>+ *                        the save-restore argument.</div><div class='add'>+ * @ctx: The context for processing the table, with one of device, gt or hwe</div><div class='add'>+ * @entries: Table with RTP definitions</div><div class='add'>+ * @sr: Save-restore struct where matching rules execute the action. This can be</div><div class='add'>+ *      viewed as the "coalesced view" of multiple the tables. The bits for each</div><div class='add'>+ *      register set are expected not to collide with previously added entries</div><div class='add'>+ *</div><div class='add'>+ * Walk the table pointed by @entries (with an empty sentinel) and add all</div><div class='add'>+ * entries with matching rules to @sr. If @hwe is not NULL, its mmio_base is</div><div class='add'>+ * used to calculate the right register offset</div><div class='add'>+ */</div><div class='add'>+void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+			  const struct xe_rtp_entry_sr *entries,</div><div class='add'>+			  struct xe_reg_sr *sr)</div><div class='add'>+{</div><div class='add'>+	const struct xe_rtp_entry_sr *entry;</div><div class='add'>+	struct xe_hw_engine *hwe = NULL;</div><div class='add'>+	struct xe_gt *gt = NULL;</div><div class='add'>+	struct xe_device *xe = NULL;</div><div class='add'>+</div><div class='add'>+	rtp_get_context(ctx, &amp;hwe, &amp;gt, &amp;xe);</div><div class='add'>+</div><div class='add'>+	for (entry = entries; entry &amp;&amp; entry-&gt;name; entry++) {</div><div class='add'>+		bool match = false;</div><div class='add'>+</div><div class='add'>+		if (entry-&gt;flags &amp; XE_RTP_ENTRY_FLAG_FOREACH_ENGINE) {</div><div class='add'>+			struct xe_hw_engine *each_hwe;</div><div class='add'>+			enum xe_hw_engine_id id;</div><div class='add'>+</div><div class='add'>+			for_each_hw_engine(each_hwe, gt, id)</div><div class='add'>+				match |= rtp_process_one_sr(entry, xe, gt,</div><div class='add'>+							    each_hwe, sr);</div><div class='add'>+		} else {</div><div class='add'>+			match = rtp_process_one_sr(entry, xe, gt, hwe, sr);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (match)</div><div class='add'>+			rtp_mark_active(xe, ctx, entry - entries,</div><div class='add'>+					entry - entries);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_rtp_process_to_sr);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_rtp_process - Process all rtp @entries, without running any action</div><div class='add'>+ * @ctx: The context for processing the table, with one of device, gt or hwe</div><div class='add'>+ * @entries: Table with RTP definitions</div><div class='add'>+ *</div><div class='add'>+ * Walk the table pointed by @entries (with an empty sentinel), executing the</div><div class='add'>+ * rules. A few differences from xe_rtp_process_to_sr():</div><div class='add'>+ *</div><div class='add'>+ * 1. There is no action associated with each entry since this uses</div><div class='add'>+ *    struct xe_rtp_entry. Its main use is for marking active workarounds via</div><div class='add'>+ *    xe_rtp_process_ctx_enable_active_tracking().</div><div class='add'>+ * 2. There is support for OR operations by having entries with no name.</div><div class='add'>+ */</div><div class='add'>+void xe_rtp_process(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+		    const struct xe_rtp_entry *entries)</div><div class='add'>+{</div><div class='add'>+	const struct xe_rtp_entry *entry, *first_entry;</div><div class='add'>+	struct xe_hw_engine *hwe;</div><div class='add'>+	struct xe_gt *gt;</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+</div><div class='add'>+	rtp_get_context(ctx, &amp;hwe, &amp;gt, &amp;xe);</div><div class='add'>+</div><div class='add'>+	first_entry = entries;</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, !first_entry-&gt;name))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (entry = entries; entry &amp;&amp; entry-&gt;rules; entry++) {</div><div class='add'>+		if (entry-&gt;name)</div><div class='add'>+			first_entry = entry;</div><div class='add'>+</div><div class='add'>+		if (!rule_matches(xe, gt, hwe, entry-&gt;rules, entry-&gt;n_rules))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Fast-forward entry, eliminating the OR'ed entries */</div><div class='add'>+		for (entry++; entry &amp;&amp; entry-&gt;rules; entry++)</div><div class='add'>+			if (entry-&gt;name)</div><div class='add'>+				break;</div><div class='add'>+		entry--;</div><div class='add'>+</div><div class='add'>+		rtp_mark_active(xe, ctx, first_entry - entries,</div><div class='add'>+				entry - entries);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_rtp_match_even_instance(const struct xe_gt *gt,</div><div class='add'>+				const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	return hwe-&gt;instance % 2 == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,</div><div class='add'>+					  const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	u64 render_compute_mask = gt-&gt;info.engine_mask &amp;</div><div class='add'>+		(XE_HW_ENGINE_CCS_MASK | XE_HW_ENGINE_RCS_MASK);</div><div class='add'>+</div><div class='add'>+	return render_compute_mask &amp;&amp;</div><div class='add'>+		hwe-&gt;engine_id == __ffs(render_compute_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_rtp_match_first_gslice_fused_off(const struct xe_gt *gt,</div><div class='add'>+					 const struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	unsigned int dss_per_gslice = 4;</div><div class='add'>+	unsigned int dss;</div><div class='add'>+</div><div class='add'>+	if (drm_WARN(&amp;gt_to_xe(gt)-&gt;drm, xe_dss_mask_empty(gt-&gt;fuse_topo.g_dss_mask),</div><div class='add'>+		     "Checking gslice for platform without geometry pipeline\n"))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	dss = xe_dss_mask_group_ffs(gt-&gt;fuse_topo.g_dss_mask, 0, 0);</div><div class='add'>+</div><div class='add'>+	return dss &gt;= dss_per_gslice;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h<br/>new file mode 100644<br/>index 000000000000..c56fedd126e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_rtp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp.h</a></div><div class='hunk'>@@ -0,0 +1,430 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RTP_</div><div class='add'>+#define _XE_RTP_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/xarray.h&gt;</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_INCLUDE_PRIVATE_HELPERS</div><div class='add'>+</div><div class='add'>+#include "xe_rtp_helpers.h"</div><div class='add'>+#include "xe_rtp_types.h"</div><div class='add'>+</div><div class='add'>+#undef _XE_RTP_INCLUDE_PRIVATE_HELPERS</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Register table poke infrastructure</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_reg_sr;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Macros to encode rules to match against platform, IP version, stepping, etc.</div><div class='add'>+ * Shouldn't be used directly - see XE_RTP_RULES()</div><div class='add'>+ */</div><div class='add'>+#define _XE_RTP_RULE_PLATFORM(plat__)						\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_PLATFORM, .platform = plat__ }</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_RULE_SUBPLATFORM(plat__, sub__)					\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_SUBPLATFORM,				\</div><div class='add'>+	  .platform = plat__, .subplatform = sub__ }</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_RULE_GRAPHICS_STEP(start__, end__)				\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_GRAPHICS_STEP,				\</div><div class='add'>+	  .step_start = start__, .step_end = end__ }</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_RULE_MEDIA_STEP(start__, end__)					\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_MEDIA_STEP,				\</div><div class='add'>+	  .step_start = start__, .step_end = end__ }</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_RULE_ENGINE_CLASS(cls__)					\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_ENGINE_CLASS,				\</div><div class='add'>+	  .engine_class = (cls__) }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_PLATFORM - Create rule matching platform</div><div class='add'>+ * @plat_: platform to match</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_PLATFORM(plat_)						\</div><div class='add'>+	_XE_RTP_RULE_PLATFORM(XE_##plat_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_SUBPLATFORM - Create rule matching platform and sub-platform</div><div class='add'>+ * @plat_: platform to match</div><div class='add'>+ * @sub_: sub-platform to match</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_SUBPLATFORM(plat_, sub_)					\</div><div class='add'>+	_XE_RTP_RULE_SUBPLATFORM(XE_##plat_, XE_SUBPLATFORM_##plat_##_##sub_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_GRAPHICS_STEP - Create rule matching graphics stepping</div><div class='add'>+ * @start_: First stepping matching the rule</div><div class='add'>+ * @end_: First stepping that does not match the rule</div><div class='add'>+ *</div><div class='add'>+ * Note that the range matching this rule is [ @start_, @end_ ), i.e. inclusive</div><div class='add'>+ * on the left, exclusive on the right.</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_GRAPHICS_STEP(start_, end_)					\</div><div class='add'>+	_XE_RTP_RULE_GRAPHICS_STEP(STEP_##start_, STEP_##end_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_MEDIA_STEP - Create rule matching media stepping</div><div class='add'>+ * @start_: First stepping matching the rule</div><div class='add'>+ * @end_: First stepping that does not match the rule</div><div class='add'>+ *</div><div class='add'>+ * Note that the range matching this rule is [ @start_, @end_ ), i.e. inclusive</div><div class='add'>+ * on the left, exclusive on the right.</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_MEDIA_STEP(start_, end_)					\</div><div class='add'>+	_XE_RTP_RULE_MEDIA_STEP(STEP_##start_, STEP_##end_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_ENGINE_CLASS - Create rule matching an engine class</div><div class='add'>+ * @cls_: Engine class to match</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_ENGINE_CLASS(cls_)						\</div><div class='add'>+	_XE_RTP_RULE_ENGINE_CLASS(XE_ENGINE_CLASS_##cls_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_FUNC - Create rule using callback function for match</div><div class='add'>+ * @func__: Function to call to decide if rule matches</div><div class='add'>+ *</div><div class='add'>+ * This allows more complex checks to be performed. The ``XE_RTP``</div><div class='add'>+ * infrastructure will simply call the function @func_ passed to decide if this</div><div class='add'>+ * rule matches the device.</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_FUNC(func__)						\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_FUNC,					\</div><div class='add'>+	  .match_func = (func__) }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_GRAPHICS_VERSION - Create rule matching graphics version</div><div class='add'>+ * @ver__: Graphics IP version to match</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_GRAPHICS_VERSION(ver__)					\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_GRAPHICS_VERSION,				\</div><div class='add'>+	  .ver_start = ver__, }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_GRAPHICS_VERSION_RANGE - Create rule matching a range of graphics version</div><div class='add'>+ * @ver_start__: First graphics IP version to match</div><div class='add'>+ * @ver_end__: Last graphics IP version to match</div><div class='add'>+ *</div><div class='add'>+ * Note that the range matching this rule is [ @ver_start__, @ver_end__ ], i.e.</div><div class='add'>+ * inclusive on boths sides</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_GRAPHICS_VERSION_RANGE(ver_start__, ver_end__)		\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_GRAPHICS_VERSION_RANGE,			\</div><div class='add'>+	  .ver_start = ver_start__, .ver_end = ver_end__, }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_MEDIA_VERSION - Create rule matching media version</div><div class='add'>+ * @ver__: Graphics IP version to match</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_MEDIA_VERSION(ver__)					\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_MEDIA_VERSION,				\</div><div class='add'>+	  .ver_start = ver__, }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_MEDIA_VERSION_RANGE - Create rule matching a range of media version</div><div class='add'>+ * @ver_start__: First media IP version to match</div><div class='add'>+ * @ver_end__: Last media IP version to match</div><div class='add'>+ *</div><div class='add'>+ * Note that the range matching this rule is [ @ver_start__, @ver_end__ ], i.e.</div><div class='add'>+ * inclusive on boths sides</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_MEDIA_VERSION_RANGE(ver_start__, ver_end__)			\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_MEDIA_VERSION_RANGE,			\</div><div class='add'>+	  .ver_start = ver_start__, .ver_end = ver_end__, }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_IS_INTEGRATED - Create a rule matching integrated graphics devices</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_IS_INTEGRATED						\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_INTEGRATED }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULE_IS_DISCRETE - Create a rule matching discrete graphics devices</div><div class='add'>+ *</div><div class='add'>+ * Refer to XE_RTP_RULES() for expected usage.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULE_IS_DISCRETE							\</div><div class='add'>+	{ .match_type = XE_RTP_MATCH_DISCRETE }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_WR - Helper to write a value to the register, overriding all</div><div class='add'>+ *                    the bits</div><div class='add'>+ * @reg_: Register</div><div class='add'>+ * @val_: Value to set</div><div class='add'>+ * @...: Additional fields to override in the struct xe_rtp_action entry</div><div class='add'>+ *</div><div class='add'>+ * The correspondent notation in bspec is:</div><div class='add'>+ *</div><div class='add'>+ *	REGNAME = VALUE</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_WR(reg_, val_, ...)					\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .clr_bits = ~0u, .set_bits = (val_),					\</div><div class='add'>+	  .read_mask = (~0u), ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_SET - Set bits from @val_ in the register.</div><div class='add'>+ * @reg_: Register</div><div class='add'>+ * @val_: Bits to set in the register</div><div class='add'>+ * @...: Additional fields to override in the struct xe_rtp_action entry</div><div class='add'>+ *</div><div class='add'>+ * For masked registers this translates to a single write, while for other</div><div class='add'>+ * registers it's a RMW. The correspondent bspec notation is (example for bits 2</div><div class='add'>+ * and 5, but could be any):</div><div class='add'>+ *</div><div class='add'>+ *	REGNAME[2] = 1</div><div class='add'>+ *	REGNAME[5] = 1</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_SET(reg_, val_, ...)					\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .clr_bits = val_, .set_bits = val_,					\</div><div class='add'>+	  .read_mask = val_, ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_CLR: Clear bits from @val_ in the register.</div><div class='add'>+ * @reg_: Register</div><div class='add'>+ * @val_: Bits to clear in the register</div><div class='add'>+ * @...: Additional fields to override in the struct xe_rtp_action entry</div><div class='add'>+ *</div><div class='add'>+ * For masked registers this translates to a single write, while for other</div><div class='add'>+ * registers it's a RMW. The correspondent bspec notation is (example for bits 2</div><div class='add'>+ * and 5, but could be any):</div><div class='add'>+ *</div><div class='add'>+ *	REGNAME[2] = 0</div><div class='add'>+ *	REGNAME[5] = 0</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_CLR(reg_, val_, ...)					\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .clr_bits = val_, .set_bits = 0,					\</div><div class='add'>+	  .read_mask = val_, ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_FIELD_SET: Set a bit range</div><div class='add'>+ * @reg_: Register</div><div class='add'>+ * @mask_bits_: Mask of bits to be changed in the register, forming a field</div><div class='add'>+ * @val_: Value to set in the field denoted by @mask_bits_</div><div class='add'>+ * @...: Additional fields to override in the struct xe_rtp_action entry</div><div class='add'>+ *</div><div class='add'>+ * For masked registers this translates to a single write, while for other</div><div class='add'>+ * registers it's a RMW. The correspondent bspec notation is:</div><div class='add'>+ *</div><div class='add'>+ *	REGNAME[&lt;end&gt;:&lt;start&gt;] = VALUE</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_FIELD_SET(reg_, mask_bits_, val_, ...)			\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .clr_bits = mask_bits_, .set_bits = val_,				\</div><div class='add'>+	  .read_mask = mask_bits_, ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+#define XE_RTP_ACTION_FIELD_SET_NO_READ_MASK(reg_, mask_bits_, val_, ...)	\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .clr_bits = (mask_bits_), .set_bits = (val_),				\</div><div class='add'>+	  .read_mask = 0, ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_WHITELIST - Add register to userspace whitelist</div><div class='add'>+ * @reg_: Register</div><div class='add'>+ * @val_: Whitelist-specific flags to set</div><div class='add'>+ * @...: Additional fields to override in the struct xe_rtp_action entry</div><div class='add'>+ *</div><div class='add'>+ * Add a register to the whitelist, allowing userspace to modify the ster with</div><div class='add'>+ * regular user privileges.</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_WHITELIST(reg_, val_, ...)				\</div><div class='add'>+	/* TODO fail build if ((flags) &amp; ~(RING_FORCE_TO_NONPRIV_MASK_VALID)) */\</div><div class='add'>+	{ .reg = XE_RTP_DROP_CAST(reg_),					\</div><div class='add'>+	  .set_bits = val_,							\</div><div class='add'>+	  .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID,				\</div><div class='add'>+	  ##__VA_ARGS__ }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_NAME - Helper to set the name in xe_rtp_entry</div><div class='add'>+ * @s_: Name describing this rule, often a HW-specific number</div><div class='add'>+ *</div><div class='add'>+ * TODO: maybe move this behind a debug config?</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_NAME(s_)	.name = (s_)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ENTRY_FLAG - Helper to add multiple flags to a struct xe_rtp_entry_sr</div><div class='add'>+ * @...: Entry flags, without the ``XE_RTP_ENTRY_FLAG_`` prefix</div><div class='add'>+ *</div><div class='add'>+ * Helper to automatically add a ``XE_RTP_ENTRY_FLAG_`` prefix to the flags</div><div class='add'>+ * when defining struct xe_rtp_entry entries. Example:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block:: c</div><div class='add'>+ *</div><div class='add'>+ *	const struct xe_rtp_entry_sr wa_entries[] = {</div><div class='add'>+ *		...</div><div class='add'>+ *		{ XE_RTP_NAME("test-entry"),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		},</div><div class='add'>+ *		...</div><div class='add'>+ *	};</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ENTRY_FLAG(...)							\</div><div class='add'>+	.flags = (XE_RTP_PASTE_FOREACH(ENTRY_FLAG_, BITWISE_OR, (__VA_ARGS__)))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTION_FLAG - Helper to add multiple flags to a struct xe_rtp_action</div><div class='add'>+ * @...: Action flags, without the ``XE_RTP_ACTION_FLAG_`` prefix</div><div class='add'>+ *</div><div class='add'>+ * Helper to automatically add a ``XE_RTP_ACTION_FLAG_`` prefix to the flags</div><div class='add'>+ * when defining struct xe_rtp_action entries. Example:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block:: c</div><div class='add'>+ *</div><div class='add'>+ *	const struct xe_rtp_entry_sr wa_entries[] = {</div><div class='add'>+ *		...</div><div class='add'>+ *		{ XE_RTP_NAME("test-entry"),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		  XE_RTP_ACTION_SET(..., XE_RTP_ACTION_FLAG(FOREACH_ENGINE)),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		},</div><div class='add'>+ *		...</div><div class='add'>+ *	};</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTION_FLAG(...)							\</div><div class='add'>+	.flags = (XE_RTP_PASTE_FOREACH(ACTION_FLAG_, BITWISE_OR, (__VA_ARGS__)))</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_RULES - Helper to set multiple rules to a struct xe_rtp_entry_sr entry</div><div class='add'>+ * @...: Rules</div><div class='add'>+ *</div><div class='add'>+ * At least one rule is needed and up to 4 are supported. Multiple rules are</div><div class='add'>+ * AND'ed together, i.e. all the rules must evaluate to true for the entry to</div><div class='add'>+ * be processed. See XE_RTP_MATCH_* for the possible match rules. Example:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block:: c</div><div class='add'>+ *</div><div class='add'>+ *	const struct xe_rtp_entry_sr wa_entries[] = {</div><div class='add'>+ *		...</div><div class='add'>+ *		{ XE_RTP_NAME("test-entry"),</div><div class='add'>+ *		  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		},</div><div class='add'>+ *		...</div><div class='add'>+ *	};</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_RULES(...)							\</div><div class='add'>+	.n_rules = _XE_COUNT_ARGS(__VA_ARGS__),					\</div><div class='add'>+	.rules = (const struct xe_rtp_rule[]) {					\</div><div class='add'>+		XE_RTP_PASTE_FOREACH(RULE_, COMMA, (__VA_ARGS__))	\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_RTP_ACTIONS - Helper to set multiple actions to a struct xe_rtp_entry_sr</div><div class='add'>+ * @...: Actions to be taken</div><div class='add'>+ *</div><div class='add'>+ * At least one action is needed and up to 4 are supported. See XE_RTP_ACTION_*</div><div class='add'>+ * for the possible actions. Example:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block:: c</div><div class='add'>+ *</div><div class='add'>+ *	const struct xe_rtp_entry_sr wa_entries[] = {</div><div class='add'>+ *		...</div><div class='add'>+ *		{ XE_RTP_NAME("test-entry"),</div><div class='add'>+ *		  XE_RTP_RULES(...),</div><div class='add'>+ *		  XE_RTP_ACTIONS(SET(..), SET(...), CLR(...)),</div><div class='add'>+ *		  ...</div><div class='add'>+ *		},</div><div class='add'>+ *		...</div><div class='add'>+ *	};</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_ACTIONS(...)							\</div><div class='add'>+	.n_actions = _XE_COUNT_ARGS(__VA_ARGS__),				\</div><div class='add'>+	.actions = (const struct xe_rtp_action[]) {				\</div><div class='add'>+		XE_RTP_PASTE_FOREACH(ACTION_, COMMA, (__VA_ARGS__))	\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__),							\</div><div class='add'>+	struct xe_hw_engine * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE },	\</div><div class='add'>+	struct xe_gt * :	(struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT })</div><div class='add'>+</div><div class='add'>+void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+					       unsigned long *active_entries,</div><div class='add'>+					       size_t n_entries);</div><div class='add'>+</div><div class='add'>+void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+			  const struct xe_rtp_entry_sr *entries,</div><div class='add'>+			  struct xe_reg_sr *sr);</div><div class='add'>+</div><div class='add'>+void xe_rtp_process(struct xe_rtp_process_ctx *ctx,</div><div class='add'>+		    const struct xe_rtp_entry *entries);</div><div class='add'>+</div><div class='add'>+/* Match functions to be used with XE_RTP_MATCH_FUNC */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_rtp_match_even_instance - Match if engine instance is even</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @hwe: Engine instance</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if engine instance is even, false otherwise</div><div class='add'>+ */</div><div class='add'>+bool xe_rtp_match_even_instance(const struct xe_gt *gt,</div><div class='add'>+				const struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * xe_rtp_match_first_render_or_compute - Match if it's first render or compute</div><div class='add'>+ * engine in the GT</div><div class='add'>+ *</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @hwe: Engine instance</div><div class='add'>+ *</div><div class='add'>+ * Registers on the render reset domain need to have their values re-applied</div><div class='add'>+ * when any of those engines are reset. Since the engines reset together, a</div><div class='add'>+ * programming can be set to just one of them. For simplicity the first engine</div><div class='add'>+ * of either render or compute class can be chosen.</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if engine id is the first to match the render reset domain,</div><div class='add'>+ * false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,</div><div class='add'>+					  const struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * xe_rtp_match_first_gslice_fused_off - Match when first gslice is fused off</div><div class='add'>+ *</div><div class='add'>+ * @gt: GT structure</div><div class='add'>+ * @hwe: Engine instance</div><div class='add'>+ *</div><div class='add'>+ * Returns: true if first gslice is fused off, false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_rtp_match_first_gslice_fused_off(const struct xe_gt *gt,</div><div class='add'>+					 const struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h<br/>new file mode 100644<br/>index 000000000000..181b6290fac3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_rtp_helpers.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp_helpers.h</a></div><div class='hunk'>@@ -0,0 +1,81 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RTP_HELPERS_</div><div class='add'>+#define _XE_RTP_HELPERS_</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RTP_INCLUDE_PRIVATE_HELPERS</div><div class='add'>+#error "This header is supposed to be included by xe_rtp.h only"</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Helper macros - not to be used outside this header.</div><div class='add'>+ */</div><div class='add'>+#define _XE_ESC(...) __VA_ARGS__</div><div class='add'>+#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__, 5, 4, 3, 2, 1,))</div><div class='add'>+#define __XE_COUNT_ARGS(_, _5, _4, _3, _2, X_, ...) X_</div><div class='add'>+</div><div class='add'>+#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))</div><div class='add'>+#define __XE_FIRST(x_, ...) x_</div><div class='add'>+#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))</div><div class='add'>+#define __XE_TUPLE_TAIL(x_, ...) (__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__</div><div class='add'>+</div><div class='add'>+#define _XE_RTP_CONCAT(a, b) __XE_RTP_CONCAT(a, b)</div><div class='add'>+#define __XE_RTP_CONCAT(a, b) XE_RTP_ ## a ## b</div><div class='add'>+</div><div class='add'>+#define __XE_RTP_PASTE_SEP_COMMA		,</div><div class='add'>+#define __XE_RTP_PASTE_SEP_BITWISE_OR		|</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * XE_RTP_PASTE_FOREACH - Paste XE_RTP_&lt;@prefix_&gt; on each element of the tuple</div><div class='add'>+ * @args, with the end result separated by @sep_. @sep must be one of the</div><div class='add'>+ * previously declared macros __XE_RTP_PASTE_SEP_*, or declared with such</div><div class='add'>+ * prefix.</div><div class='add'>+ *</div><div class='add'>+ * Examples:</div><div class='add'>+ *</div><div class='add'>+ * 1) XE_RTP_PASTE_FOREACH(TEST_, COMMA, (FOO, BAR))</div><div class='add'>+ *    expands to:</div><div class='add'>+ *</div><div class='add'>+ *	XE_RTP_TEST_FOO , XE_RTP_TEST_BAR</div><div class='add'>+ *</div><div class='add'>+ * 2) XE_RTP_PASTE_FOREACH(TEST2_, COMMA, (FOO))</div><div class='add'>+ *    expands to:</div><div class='add'>+ *</div><div class='add'>+ *	XE_RTP_TEST2_FOO</div><div class='add'>+ *</div><div class='add'>+ * 3) XE_RTP_PASTE_FOREACH(TEST3, BITWISE_OR, (FOO, BAR))</div><div class='add'>+ *    expands to:</div><div class='add'>+ *</div><div class='add'>+ *	XE_RTP_TEST3_FOO | XE_RTP_TEST3_BAR</div><div class='add'>+ *</div><div class='add'>+ * 4) #define __XE_RTP_PASTE_SEP_MY_SEP	BANANA</div><div class='add'>+ *    XE_RTP_PASTE_FOREACH(TEST_, MY_SEP, (FOO, BAR))</div><div class='add'>+ *    expands to:</div><div class='add'>+ *</div><div class='add'>+ *	XE_RTP_TEST_FOO BANANA XE_RTP_TEST_BAR</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_PASTE_FOREACH(prefix_, sep_, args_) _XE_ESC(_XE_RTP_CONCAT(PASTE_, _XE_COUNT_ARGS args_)(prefix_, sep_, args_))</div><div class='add'>+#define XE_RTP_PASTE_1(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_)</div><div class='add'>+#define XE_RTP_PASTE_2(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)</div><div class='add'>+#define XE_RTP_PASTE_3(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)</div><div class='add'>+#define XE_RTP_PASTE_4(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_3(prefix_, sep_, _XE_TUPLE_TAIL args_)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * XE_RTP_DROP_CAST - Drop cast to convert a compound statement to a initializer</div><div class='add'>+ *</div><div class='add'>+ * Example:</div><div class='add'>+ *</div><div class='add'>+ *	#define foo(a_)	((struct foo){ .a = a_ })</div><div class='add'>+ *	XE_RTP_DROP_CAST(foo(10))</div><div class='add'>+ *	expands to:</div><div class='add'>+ *</div><div class='add'>+ *	{ .a = 10 }</div><div class='add'>+ */</div><div class='add'>+#define XE_RTP_DROP_CAST(...) _XE_ESC(_XE_DROP_FIRST _XE_ESC __VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h<br/>new file mode 100644<br/>index 000000000000..637acc7626a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_rtp_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_rtp_types.h</a></div><div class='hunk'>@@ -0,0 +1,124 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_RTP_TYPES_</div><div class='add'>+#define _XE_RTP_TYPES_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_reg_defs.h"</div><div class='add'>+</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_rtp_action - action to take for any matching rule</div><div class='add'>+ *</div><div class='add'>+ * This struct records what action should be taken in a register that has a</div><div class='add'>+ * matching rule. Example of actions: set/clear bits.</div><div class='add'>+ */</div><div class='add'>+struct xe_rtp_action {</div><div class='add'>+	/** @reg: Register */</div><div class='add'>+	struct xe_reg		reg;</div><div class='add'>+	/**</div><div class='add'>+	 * @clr_bits: bits to clear when updating register. It's always a</div><div class='add'>+	 * superset of bits being modified</div><div class='add'>+	 */</div><div class='add'>+	u32			clr_bits;</div><div class='add'>+	/** @set_bits: bits to set when updating register */</div><div class='add'>+	u32			set_bits;</div><div class='add'>+#define XE_RTP_NOCHECK		.read_mask = 0</div><div class='add'>+	/** @read_mask: mask for bits to consider when reading value back */</div><div class='add'>+	u32			read_mask;</div><div class='add'>+#define XE_RTP_ACTION_FLAG_ENGINE_BASE		BIT(0)</div><div class='add'>+	/** @flags: flags to apply on rule evaluation or action */</div><div class='add'>+	u8			flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	XE_RTP_MATCH_PLATFORM,</div><div class='add'>+	XE_RTP_MATCH_SUBPLATFORM,</div><div class='add'>+	XE_RTP_MATCH_GRAPHICS_VERSION,</div><div class='add'>+	XE_RTP_MATCH_GRAPHICS_VERSION_RANGE,</div><div class='add'>+	XE_RTP_MATCH_GRAPHICS_STEP,</div><div class='add'>+	XE_RTP_MATCH_MEDIA_VERSION,</div><div class='add'>+	XE_RTP_MATCH_MEDIA_VERSION_RANGE,</div><div class='add'>+	XE_RTP_MATCH_MEDIA_STEP,</div><div class='add'>+	XE_RTP_MATCH_INTEGRATED,</div><div class='add'>+	XE_RTP_MATCH_DISCRETE,</div><div class='add'>+	XE_RTP_MATCH_ENGINE_CLASS,</div><div class='add'>+	XE_RTP_MATCH_NOT_ENGINE_CLASS,</div><div class='add'>+	XE_RTP_MATCH_FUNC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_rtp_rule - match rule for processing entry */</div><div class='add'>+struct xe_rtp_rule {</div><div class='add'>+	u8 match_type;</div><div class='add'>+</div><div class='add'>+	/* match filters */</div><div class='add'>+	union {</div><div class='add'>+		/* MATCH_PLATFORM / MATCH_SUBPLATFORM */</div><div class='add'>+		struct {</div><div class='add'>+			u8 platform;</div><div class='add'>+			u8 subplatform;</div><div class='add'>+		};</div><div class='add'>+		/*</div><div class='add'>+		 * MATCH_GRAPHICS_VERSION / XE_RTP_MATCH_GRAPHICS_VERSION_RANGE /</div><div class='add'>+		 * MATCH_MEDIA_VERSION  / XE_RTP_MATCH_MEDIA_VERSION_RANGE</div><div class='add'>+		 */</div><div class='add'>+		struct {</div><div class='add'>+			u32 ver_start;</div><div class='add'>+#define XE_RTP_END_VERSION_UNDEFINED	U32_MAX</div><div class='add'>+			u32 ver_end;</div><div class='add'>+		};</div><div class='add'>+		/* MATCH_STEP */</div><div class='add'>+		struct {</div><div class='add'>+			u8 step_start;</div><div class='add'>+			u8 step_end;</div><div class='add'>+		};</div><div class='add'>+		/* MATCH_ENGINE_CLASS / MATCH_NOT_ENGINE_CLASS */</div><div class='add'>+		struct {</div><div class='add'>+			u8 engine_class;</div><div class='add'>+		};</div><div class='add'>+		/* MATCH_FUNC */</div><div class='add'>+		bool (*match_func)(const struct xe_gt *gt,</div><div class='add'>+				   const struct xe_hw_engine *hwe);</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_rtp_entry_sr - Entry in an rtp table */</div><div class='add'>+struct xe_rtp_entry_sr {</div><div class='add'>+	const char *name;</div><div class='add'>+	const struct xe_rtp_action *actions;</div><div class='add'>+	const struct xe_rtp_rule *rules;</div><div class='add'>+	u8 n_rules;</div><div class='add'>+	u8 n_actions;</div><div class='add'>+#define XE_RTP_ENTRY_FLAG_FOREACH_ENGINE	BIT(0)</div><div class='add'>+	u8 flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_rtp_entry - Entry in an rtp table, with no action associated */</div><div class='add'>+struct xe_rtp_entry {</div><div class='add'>+	const char *name;</div><div class='add'>+	const struct xe_rtp_rule *rules;</div><div class='add'>+	u8 n_rules;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_rtp_process_type {</div><div class='add'>+	XE_RTP_PROCESS_TYPE_GT,</div><div class='add'>+	XE_RTP_PROCESS_TYPE_ENGINE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_rtp_process_ctx {</div><div class='add'>+	union {</div><div class='add'>+		struct xe_gt *gt;</div><div class='add'>+		struct xe_hw_engine *hwe;</div><div class='add'>+	};</div><div class='add'>+	enum xe_rtp_process_type type;</div><div class='add'>+	unsigned long *active_entries;</div><div class='add'>+	size_t n_entries;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sa.c b/drivers/gpu/drm/xe/xe_sa.c<br/>new file mode 100644<br/>index 000000000000..2c4632259edd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa.c</a></div><div class='hunk'>@@ -0,0 +1,106 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_sa.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+</div><div class='add'>+static void xe_sa_bo_manager_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_sa_manager *sa_manager = arg;</div><div class='add'>+	struct xe_bo *bo = sa_manager-&gt;bo;</div><div class='add'>+</div><div class='add'>+	if (!bo) {</div><div class='add'>+		drm_err(drm, "no bo for sa manager\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_suballoc_manager_fini(&amp;sa_manager-&gt;base);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;vmap.is_iomem)</div><div class='add'>+		kvfree(sa_manager-&gt;cpu_ptr);</div><div class='add'>+</div><div class='add'>+	xe_bo_unpin_map_no_vm(bo);</div><div class='add'>+	sa_manager-&gt;bo = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	u32 managed_size = size - SZ_4K;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	struct xe_sa_manager *sa_manager = drmm_kzalloc(&amp;tile_to_xe(tile)-&gt;drm,</div><div class='add'>+							sizeof(*sa_manager),</div><div class='add'>+							GFP_KERNEL);</div><div class='add'>+	if (!sa_manager)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	sa_manager-&gt;bo = NULL;</div><div class='add'>+</div><div class='add'>+	bo = xe_bo_create_pin_map(xe, tile, NULL, size, ttm_bo_type_kernel,</div><div class='add'>+				  XE_BO_CREATE_VRAM_IF_DGFX(tile) |</div><div class='add'>+				  XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+	if (IS_ERR(bo)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "failed to allocate bo for sa manager: %ld\n",</div><div class='add'>+			PTR_ERR(bo));</div><div class='add'>+		return (struct xe_sa_manager *)bo;</div><div class='add'>+	}</div><div class='add'>+	sa_manager-&gt;bo = bo;</div><div class='add'>+</div><div class='add'>+	drm_suballoc_manager_init(&amp;sa_manager-&gt;base, managed_size, align);</div><div class='add'>+	sa_manager-&gt;gpu_addr = xe_bo_ggtt_addr(bo);</div><div class='add'>+</div><div class='add'>+	if (bo-&gt;vmap.is_iomem) {</div><div class='add'>+		sa_manager-&gt;cpu_ptr = kvzalloc(managed_size, GFP_KERNEL);</div><div class='add'>+		if (!sa_manager-&gt;cpu_ptr) {</div><div class='add'>+			xe_bo_unpin_map_no_vm(sa_manager-&gt;bo);</div><div class='add'>+			sa_manager-&gt;bo = NULL;</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		sa_manager-&gt;cpu_ptr = bo-&gt;vmap.vaddr;</div><div class='add'>+		memset(sa_manager-&gt;cpu_ptr, 0, bo-&gt;ttm.base.size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = drmm_add_action_or_reset(&amp;xe-&gt;drm, xe_sa_bo_manager_fini,</div><div class='add'>+				       sa_manager);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+</div><div class='add'>+	return sa_manager;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager,</div><div class='add'>+				  unsigned int size)</div><div class='add'>+{</div><div class='add'>+	return drm_suballoc_new(&amp;sa_manager-&gt;base, size, GFP_KERNEL, true, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_sa_manager *sa_manager = to_xe_sa_manager(sa_bo-&gt;manager);</div><div class='add'>+	struct xe_device *xe = tile_to_xe(sa_manager-&gt;bo-&gt;tile);</div><div class='add'>+</div><div class='add'>+	if (!sa_manager-&gt;bo-&gt;vmap.is_iomem)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_to(xe, &amp;sa_manager-&gt;bo-&gt;vmap, drm_suballoc_soffset(sa_bo),</div><div class='add'>+			 xe_sa_bo_cpu_addr(sa_bo),</div><div class='add'>+			 drm_suballoc_size(sa_bo));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sa_bo_free(struct drm_suballoc *sa_bo,</div><div class='add'>+		   struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	drm_suballoc_free(sa_bo, fence);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sa.h b/drivers/gpu/drm/xe/xe_sa.h<br/>new file mode 100644<br/>index 000000000000..4e96483057d7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa.h</a></div><div class='hunk'>@@ -0,0 +1,40 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_SA_H_</div><div class='add'>+#define _XE_SA_H_</div><div class='add'>+</div><div class='add'>+#include "xe_sa_types.h"</div><div class='add'>+</div><div class='add'>+struct dma_fence;</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_tile;</div><div class='add'>+</div><div class='add'>+struct xe_sa_manager *xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u32 align);</div><div class='add'>+</div><div class='add'>+struct drm_suballoc *xe_sa_bo_new(struct xe_sa_manager *sa_manager,</div><div class='add'>+				  u32 size);</div><div class='add'>+void xe_sa_bo_flush_write(struct drm_suballoc *sa_bo);</div><div class='add'>+void xe_sa_bo_free(struct drm_suballoc *sa_bo,</div><div class='add'>+		   struct dma_fence *fence);</div><div class='add'>+</div><div class='add'>+static inline struct xe_sa_manager *</div><div class='add'>+to_xe_sa_manager(struct drm_suballoc_manager *mng)</div><div class='add'>+{</div><div class='add'>+	return container_of(mng, struct xe_sa_manager, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 xe_sa_bo_gpu_addr(struct drm_suballoc *sa)</div><div class='add'>+{</div><div class='add'>+	return to_xe_sa_manager(sa-&gt;manager)-&gt;gpu_addr +</div><div class='add'>+		drm_suballoc_soffset(sa);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void *xe_sa_bo_cpu_addr(struct drm_suballoc *sa)</div><div class='add'>+{</div><div class='add'>+	return to_xe_sa_manager(sa-&gt;manager)-&gt;cpu_ptr +</div><div class='add'>+		drm_suballoc_soffset(sa);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sa_types.h b/drivers/gpu/drm/xe/xe_sa_types.h<br/>new file mode 100644<br/>index 000000000000..2ef896aeca1d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sa_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sa_types.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+#ifndef _XE_SA_TYPES_H_</div><div class='add'>+#define _XE_SA_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_suballoc.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+struct xe_sa_manager {</div><div class='add'>+	struct drm_suballoc_manager base;</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+	u64 gpu_addr;</div><div class='add'>+	void *cpu_ptr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c<br/>new file mode 100644<br/>index 000000000000..01106a1156ad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sched_job.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job.c</a></div><div class='hunk'>@@ -0,0 +1,280 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence-array.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_hw_fence.h"</div><div class='add'>+#include "xe_lrc.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+static struct kmem_cache *xe_sched_job_slab;</div><div class='add'>+static struct kmem_cache *xe_sched_job_parallel_slab;</div><div class='add'>+</div><div class='add'>+int __init xe_sched_job_module_init(void)</div><div class='add'>+{</div><div class='add'>+	xe_sched_job_slab =</div><div class='add'>+		kmem_cache_create("xe_sched_job",</div><div class='add'>+				  sizeof(struct xe_sched_job) +</div><div class='add'>+				  sizeof(u64), 0,</div><div class='add'>+				  SLAB_HWCACHE_ALIGN, NULL);</div><div class='add'>+	if (!xe_sched_job_slab)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	xe_sched_job_parallel_slab =</div><div class='add'>+		kmem_cache_create("xe_sched_job_parallel",</div><div class='add'>+				  sizeof(struct xe_sched_job) +</div><div class='add'>+				  sizeof(u64) *</div><div class='add'>+				  XE_HW_ENGINE_MAX_INSTANCE, 0,</div><div class='add'>+				  SLAB_HWCACHE_ALIGN, NULL);</div><div class='add'>+	if (!xe_sched_job_parallel_slab) {</div><div class='add'>+		kmem_cache_destroy(xe_sched_job_slab);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_job_module_exit(void)</div><div class='add'>+{</div><div class='add'>+	kmem_cache_destroy(xe_sched_job_slab);</div><div class='add'>+	kmem_cache_destroy(xe_sched_job_parallel_slab);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_sched_job *job_alloc(bool parallel)</div><div class='add'>+{</div><div class='add'>+	return kmem_cache_zalloc(parallel ? xe_sched_job_parallel_slab :</div><div class='add'>+				 xe_sched_job_slab, GFP_KERNEL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_sched_job_is_migration(struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return q-&gt;vm &amp;&amp; (q-&gt;vm-&gt;flags &amp; XE_VM_FLAG_MIGRATION);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void job_free(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q = job-&gt;q;</div><div class='add'>+	bool is_migration = xe_sched_job_is_migration(q);</div><div class='add'>+</div><div class='add'>+	kmem_cache_free(xe_exec_queue_is_parallel(job-&gt;q) || is_migration ?</div><div class='add'>+			xe_sched_job_parallel_slab : xe_sched_job_slab, job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *job_to_xe(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(job-&gt;q-&gt;gt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,</div><div class='add'>+					 u64 *batch_addr)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job;</div><div class='add'>+	struct dma_fence **fences;</div><div class='add'>+	bool is_migration = xe_sched_job_is_migration(q);</div><div class='add'>+	int err;</div><div class='add'>+	int i, j;</div><div class='add'>+	u32 width;</div><div class='add'>+</div><div class='add'>+	/* only a kernel context can submit a vm-less job */</div><div class='add'>+	XE_WARN_ON(!q-&gt;vm &amp;&amp; !(q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL));</div><div class='add'>+</div><div class='add'>+	/* Migration and kernel engines have their own locking */</div><div class='add'>+	if (!(q-&gt;flags &amp; (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) {</div><div class='add'>+		lockdep_assert_held(&amp;q-&gt;vm-&gt;lock);</div><div class='add'>+		if (!xe_vm_in_lr_mode(q-&gt;vm))</div><div class='add'>+			xe_vm_assert_held(q-&gt;vm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration);</div><div class='add'>+	if (!job)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	job-&gt;q = q;</div><div class='add'>+	kref_init(&amp;job-&gt;refcount);</div><div class='add'>+	xe_exec_queue_get(job-&gt;q);</div><div class='add'>+</div><div class='add'>+	err = drm_sched_job_init(&amp;job-&gt;drm, q-&gt;entity, 1, NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_free;</div><div class='add'>+</div><div class='add'>+	if (!xe_exec_queue_is_parallel(q)) {</div><div class='add'>+		job-&gt;fence = xe_lrc_create_seqno_fence(q-&gt;lrc);</div><div class='add'>+		if (IS_ERR(job-&gt;fence)) {</div><div class='add'>+			err = PTR_ERR(job-&gt;fence);</div><div class='add'>+			goto err_sched_job;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		struct dma_fence_array *cf;</div><div class='add'>+</div><div class='add'>+		fences = kmalloc_array(q-&gt;width, sizeof(*fences), GFP_KERNEL);</div><div class='add'>+		if (!fences) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_sched_job;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; q-&gt;width; ++j) {</div><div class='add'>+			fences[j] = xe_lrc_create_seqno_fence(q-&gt;lrc + j);</div><div class='add'>+			if (IS_ERR(fences[j])) {</div><div class='add'>+				err = PTR_ERR(fences[j]);</div><div class='add'>+				goto err_fences;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cf = dma_fence_array_create(q-&gt;width, fences,</div><div class='add'>+					    q-&gt;parallel.composite_fence_ctx,</div><div class='add'>+					    q-&gt;parallel.composite_fence_seqno++,</div><div class='add'>+					    false);</div><div class='add'>+		if (!cf) {</div><div class='add'>+			--q-&gt;parallel.composite_fence_seqno;</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_fences;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Sanity check */</div><div class='add'>+		for (j = 0; j &lt; q-&gt;width; ++j)</div><div class='add'>+			xe_assert(job_to_xe(job), cf-&gt;base.seqno == fences[j]-&gt;seqno);</div><div class='add'>+</div><div class='add'>+		job-&gt;fence = &amp;cf-&gt;base;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	width = q-&gt;width;</div><div class='add'>+	if (is_migration)</div><div class='add'>+		width = 2;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; width; ++i)</div><div class='add'>+		job-&gt;batch_addr[i] = batch_addr[i];</div><div class='add'>+</div><div class='add'>+	/* All other jobs require a VM to be open which has a ref */</div><div class='add'>+	if (unlikely(q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL))</div><div class='add'>+		xe_device_mem_access_get(job_to_xe(job));</div><div class='add'>+	xe_device_assert_mem_access(job_to_xe(job));</div><div class='add'>+</div><div class='add'>+	trace_xe_sched_job_create(job);</div><div class='add'>+	return job;</div><div class='add'>+</div><div class='add'>+err_fences:</div><div class='add'>+	for (j = j - 1; j &gt;= 0; --j) {</div><div class='add'>+		--q-&gt;lrc[j].fence_ctx.next_seqno;</div><div class='add'>+		dma_fence_put(fences[j]);</div><div class='add'>+	}</div><div class='add'>+	kfree(fences);</div><div class='add'>+err_sched_job:</div><div class='add'>+	drm_sched_job_cleanup(&amp;job-&gt;drm);</div><div class='add'>+err_free:</div><div class='add'>+	xe_exec_queue_put(q);</div><div class='add'>+	job_free(job);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sched_job_destroy - Destroy XE schedule job</div><div class='add'>+ * @ref: reference to XE schedule job</div><div class='add'>+ *</div><div class='add'>+ * Called when ref == 0, drop a reference to job's xe_engine + fence, cleanup</div><div class='add'>+ * base DRM schedule job, and free memory for XE schedule job.</div><div class='add'>+ */</div><div class='add'>+void xe_sched_job_destroy(struct kref *ref)</div><div class='add'>+{</div><div class='add'>+	struct xe_sched_job *job =</div><div class='add'>+		container_of(ref, struct xe_sched_job, refcount);</div><div class='add'>+</div><div class='add'>+	if (unlikely(job-&gt;q-&gt;flags &amp; EXEC_QUEUE_FLAG_KERNEL))</div><div class='add'>+		xe_device_mem_access_put(job_to_xe(job));</div><div class='add'>+	xe_exec_queue_put(job-&gt;q);</div><div class='add'>+	dma_fence_put(job-&gt;fence);</div><div class='add'>+	drm_sched_job_cleanup(&amp;job-&gt;drm);</div><div class='add'>+	job_free(job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_job_set_error(struct xe_sched_job *job, int error)</div><div class='add'>+{</div><div class='add'>+	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &amp;job-&gt;fence-&gt;flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	dma_fence_set_error(job-&gt;fence, error);</div><div class='add'>+</div><div class='add'>+	if (dma_fence_is_array(job-&gt;fence)) {</div><div class='add'>+		struct dma_fence_array *array =</div><div class='add'>+			to_dma_fence_array(job-&gt;fence);</div><div class='add'>+		struct dma_fence **child = array-&gt;fences;</div><div class='add'>+		unsigned int nchild = array-&gt;num_fences;</div><div class='add'>+</div><div class='add'>+		do {</div><div class='add'>+			struct dma_fence *current_fence = *child++;</div><div class='add'>+</div><div class='add'>+			if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,</div><div class='add'>+				     &amp;current_fence-&gt;flags))</div><div class='add'>+				continue;</div><div class='add'>+			dma_fence_set_error(current_fence, error);</div><div class='add'>+		} while (--nchild);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_sched_job_set_error(job);</div><div class='add'>+</div><div class='add'>+	dma_fence_enable_sw_signaling(job-&gt;fence);</div><div class='add'>+	xe_hw_fence_irq_run(job-&gt;q-&gt;fence_irq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_sched_job_started(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	struct xe_lrc *lrc = job-&gt;q-&gt;lrc;</div><div class='add'>+</div><div class='add'>+	return !__dma_fence_is_later(xe_sched_job_seqno(job),</div><div class='add'>+				     xe_lrc_start_seqno(lrc),</div><div class='add'>+				     job-&gt;fence-&gt;ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_sched_job_completed(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	struct xe_lrc *lrc = job-&gt;q-&gt;lrc;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Can safely check just LRC[0] seqno as that is last seqno written when</div><div class='add'>+	 * parallel handshake is done.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	return !__dma_fence_is_later(xe_sched_job_seqno(job), xe_lrc_seqno(lrc),</div><div class='add'>+				     job-&gt;fence-&gt;ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_job_arm(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	drm_sched_job_arm(&amp;job-&gt;drm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_job_push(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	xe_sched_job_get(job);</div><div class='add'>+	trace_xe_sched_job_exec(job);</div><div class='add'>+	drm_sched_entity_push_job(&amp;job-&gt;drm);</div><div class='add'>+	xe_sched_job_put(job);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sched_job_last_fence_add_dep - Add last fence dependency to job</div><div class='add'>+ * @job:job to add the last fence dependency to</div><div class='add'>+ * @vm: virtual memory job belongs to</div><div class='add'>+ *</div><div class='add'>+ * Returns:</div><div class='add'>+ * 0 on success, or an error on failing to expand the array.</div><div class='add'>+ */</div><div class='add'>+int xe_sched_job_last_fence_add_dep(struct xe_sched_job *job, struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+	fence = xe_exec_queue_last_fence_get(job-&gt;q, vm);</div><div class='add'>+	dma_fence_get(fence);</div><div class='add'>+</div><div class='add'>+	return drm_sched_job_add_dependency(&amp;job-&gt;drm, fence);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sched_job.h b/drivers/gpu/drm/xe/xe_sched_job.h<br/>new file mode 100644<br/>index 000000000000..34f475ba7f50<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sched_job.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job.h</a></div><div class='hunk'>@@ -0,0 +1,80 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SCHED_JOB_H_</div><div class='add'>+#define _XE_SCHED_JOB_H_</div><div class='add'>+</div><div class='add'>+#include "xe_sched_job_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+#define XE_SCHED_HANG_LIMIT 1</div><div class='add'>+#define XE_SCHED_JOB_TIMEOUT LONG_MAX</div><div class='add'>+</div><div class='add'>+int xe_sched_job_module_init(void);</div><div class='add'>+void xe_sched_job_module_exit(void);</div><div class='add'>+</div><div class='add'>+struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,</div><div class='add'>+					 u64 *batch_addr);</div><div class='add'>+void xe_sched_job_destroy(struct kref *ref);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sched_job_get - get reference to XE schedule job</div><div class='add'>+ * @job: XE schedule job object</div><div class='add'>+ *</div><div class='add'>+ * Increment XE schedule job's reference count</div><div class='add'>+ */</div><div class='add'>+static inline struct xe_sched_job *xe_sched_job_get(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;job-&gt;refcount);</div><div class='add'>+	return job;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sched_job_put - put reference to XE schedule job</div><div class='add'>+ * @job: XE schedule job object</div><div class='add'>+ *</div><div class='add'>+ * Decrement XE schedule job's reference count, call xe_sched_job_destroy when</div><div class='add'>+ * reference count == 0.</div><div class='add'>+ */</div><div class='add'>+static inline void xe_sched_job_put(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;job-&gt;refcount, xe_sched_job_destroy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sched_job_set_error(struct xe_sched_job *job, int error);</div><div class='add'>+static inline bool xe_sched_job_is_error(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	return job-&gt;fence-&gt;error &lt; 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_sched_job_started(struct xe_sched_job *job);</div><div class='add'>+bool xe_sched_job_completed(struct xe_sched_job *job);</div><div class='add'>+</div><div class='add'>+void xe_sched_job_arm(struct xe_sched_job *job);</div><div class='add'>+void xe_sched_job_push(struct xe_sched_job *job);</div><div class='add'>+</div><div class='add'>+int xe_sched_job_last_fence_add_dep(struct xe_sched_job *job, struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+static inline struct xe_sched_job *</div><div class='add'>+to_xe_sched_job(struct drm_sched_job *drm)</div><div class='add'>+{</div><div class='add'>+	return container_of(drm, struct xe_sched_job, drm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 xe_sched_job_seqno(struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	return job-&gt;fence-&gt;seqno;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+xe_sched_job_add_migrate_flush(struct xe_sched_job *job, u32 flags)</div><div class='add'>+{</div><div class='add'>+	job-&gt;migrate_flush_flags = flags;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool xe_sched_job_is_migration(struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h<br/>new file mode 100644<br/>index 000000000000..71213ba9735b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sched_job_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sched_job_types.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SCHED_JOB_TYPES_H_</div><div class='add'>+#define _XE_SCHED_JOB_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/gpu_scheduler.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_sched_job - XE schedule job (batch buffer tracking)</div><div class='add'>+ */</div><div class='add'>+struct xe_sched_job {</div><div class='add'>+	/** @drm: base DRM scheduler job */</div><div class='add'>+	struct drm_sched_job drm;</div><div class='add'>+	/** @q: Exec queue */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	/** @refcount: ref count of this job */</div><div class='add'>+	struct kref refcount;</div><div class='add'>+	/**</div><div class='add'>+	 * @fence: dma fence to indicate completion. 1 way relationship - job</div><div class='add'>+	 * can safely reference fence, fence cannot safely reference job.</div><div class='add'>+	 */</div><div class='add'>+#define JOB_FLAG_SUBMIT		DMA_FENCE_FLAG_USER_BITS</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	/** @user_fence: write back value when BB is complete */</div><div class='add'>+	struct {</div><div class='add'>+		/** @used: user fence is used */</div><div class='add'>+		bool used;</div><div class='add'>+		/** @addr: address to write to */</div><div class='add'>+		u64 addr;</div><div class='add'>+		/** @value: write back value */</div><div class='add'>+		u64 value;</div><div class='add'>+	} user_fence;</div><div class='add'>+	/** @migrate_flush_flags: Additional flush flags for migration jobs */</div><div class='add'>+	u32 migrate_flush_flags;</div><div class='add'>+	/** @batch_addr: batch buffer address of job */</div><div class='add'>+	u64 batch_addr[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c<br/>new file mode 100644<br/>index 000000000000..42a0e0c917a0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov.c</a></div><div class='hunk'>@@ -0,0 +1,55 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_sriov.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sriov_mode_to_string - Convert enum value to string.</div><div class='add'>+ * @mode: the &amp;xe_sriov_mode to convert</div><div class='add'>+ *</div><div class='add'>+ * Returns: SR-IOV mode as a user friendly string.</div><div class='add'>+ */</div><div class='add'>+const char *xe_sriov_mode_to_string(enum xe_sriov_mode mode)</div><div class='add'>+{</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case XE_SRIOV_MODE_NONE:</div><div class='add'>+		return "none";</div><div class='add'>+	case XE_SRIOV_MODE_PF:</div><div class='add'>+		return "SR-IOV PF";</div><div class='add'>+	case XE_SRIOV_MODE_VF:</div><div class='add'>+		return "SR-IOV VF";</div><div class='add'>+	default:</div><div class='add'>+		return "&lt;invalid&gt;";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sriov_probe_early - Probe a SR-IOV mode.</div><div class='add'>+ * @xe: the &amp;xe_device to probe mode on</div><div class='add'>+ * @has_sriov: flag indicating hardware support for SR-IOV</div><div class='add'>+ *</div><div class='add'>+ * This function should be called only once and as soon as possible during</div><div class='add'>+ * driver probe to detect whether we are running a SR-IOV Physical Function</div><div class='add'>+ * (PF) or a Virtual Function (VF) device.</div><div class='add'>+ *</div><div class='add'>+ * SR-IOV PF mode detection is based on PCI @dev_is_pf() function.</div><div class='add'>+ * SR-IOV VF mode detection is based on dedicated MMIO register read.</div><div class='add'>+ */</div><div class='add'>+void xe_sriov_probe_early(struct xe_device *xe, bool has_sriov)</div><div class='add'>+{</div><div class='add'>+	enum xe_sriov_mode mode = XE_SRIOV_MODE_NONE;</div><div class='add'>+</div><div class='add'>+	/* TODO: replace with proper mode detection */</div><div class='add'>+	xe_assert(xe, !has_sriov);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !xe-&gt;sriov.__mode);</div><div class='add'>+	xe-&gt;sriov.__mode = mode;</div><div class='add'>+	xe_assert(xe, xe-&gt;sriov.__mode);</div><div class='add'>+</div><div class='add'>+	if (has_sriov)</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "Running in %s mode\n",</div><div class='add'>+			 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sriov.h b/drivers/gpu/drm/xe/xe_sriov.h<br/>new file mode 100644<br/>index 000000000000..5af73a3172b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sriov.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov.h</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SRIOV_H_</div><div class='add'>+#define _XE_SRIOV_H_</div><div class='add'>+</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_sriov_types.h"</div><div class='add'>+</div><div class='add'>+const char *xe_sriov_mode_to_string(enum xe_sriov_mode mode);</div><div class='add'>+</div><div class='add'>+void xe_sriov_probe_early(struct xe_device *xe, bool has_sriov);</div><div class='add'>+</div><div class='add'>+static inline enum xe_sriov_mode xe_device_sriov_mode(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	xe_assert(xe, xe-&gt;sriov.__mode);</div><div class='add'>+	return xe-&gt;sriov.__mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_is_sriov_pf(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe_device_sriov_mode(xe) == XE_SRIOV_MODE_PF;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_device_is_sriov_vf(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return xe_device_sriov_mode(xe) == XE_SRIOV_MODE_VF;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_PCI_IOV</div><div class='add'>+#define IS_SRIOV_PF(xe) xe_device_is_sriov_pf(xe)</div><div class='add'>+#else</div><div class='add'>+#define IS_SRIOV_PF(xe) (typecheck(struct xe_device *, (xe)) &amp;&amp; false)</div><div class='add'>+#endif</div><div class='add'>+#define IS_SRIOV_VF(xe) xe_device_is_sriov_vf(xe)</div><div class='add'>+</div><div class='add'>+#define IS_SRIOV(xe) (IS_SRIOV_PF(xe) || IS_SRIOV_VF(xe))</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sriov_printk.h b/drivers/gpu/drm/xe/xe_sriov_printk.h<br/>new file mode 100644<br/>index 000000000000..117e1d541692<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sriov_printk.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov_printk.h</a></div><div class='hunk'>@@ -0,0 +1,46 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SRIOV_PRINTK_H_</div><div class='add'>+#define _XE_SRIOV_PRINTK_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_sriov_types.h"</div><div class='add'>+</div><div class='add'>+#define xe_sriov_printk_prefix(xe) \</div><div class='add'>+	((xe)-&gt;sriov.__mode == XE_SRIOV_MODE_PF ? "PF: " : \</div><div class='add'>+	 (xe)-&gt;sriov.__mode == XE_SRIOV_MODE_VF ? "VF: " : "")</div><div class='add'>+</div><div class='add'>+#define xe_sriov_printk(xe, _level, fmt, ...) \</div><div class='add'>+	drm_##_level(&amp;(xe)-&gt;drm, "%s" fmt, xe_sriov_printk_prefix(xe), ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_err(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), err, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_err_ratelimited(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), err_ratelimited, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_warn(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), warn, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_notice(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), notice, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_info(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), info, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+#define xe_sriov_dbg(xe, fmt, ...) \</div><div class='add'>+	xe_sriov_printk((xe), dbg, fmt, ##__VA_ARGS__)</div><div class='add'>+</div><div class='add'>+/* for low level noisy debug messages */</div><div class='add'>+#ifdef CONFIG_DRM_XE_DEBUG_SRIOV</div><div class='add'>+#define xe_sriov_dbg_verbose(xe, fmt, ...) xe_sriov_dbg(xe, fmt, ##__VA_ARGS__)</div><div class='add'>+#else</div><div class='add'>+#define xe_sriov_dbg_verbose(xe, fmt, ...) typecheck(struct xe_device *, (xe))</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sriov_types.h b/drivers/gpu/drm/xe/xe_sriov_types.h<br/>new file mode 100644<br/>index 000000000000..999a4311b98b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sriov_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sriov_types.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SRIOV_TYPES_H_</div><div class='add'>+#define _XE_SRIOV_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/build_bug.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * enum xe_sriov_mode - SR-IOV mode</div><div class='add'>+ * @XE_SRIOV_MODE_NONE: bare-metal mode (non-virtualized)</div><div class='add'>+ * @XE_SRIOV_MODE_PF: SR-IOV Physical Function (PF) mode</div><div class='add'>+ * @XE_SRIOV_MODE_VF: SR-IOV Virtual Function (VF) mode</div><div class='add'>+ */</div><div class='add'>+enum xe_sriov_mode {</div><div class='add'>+	/*</div><div class='add'>+	 * Note: We don't use default enum value 0 to allow catch any too early</div><div class='add'>+	 * attempt of checking the SR-IOV mode prior to the actual mode probe.</div><div class='add'>+	 */</div><div class='add'>+	XE_SRIOV_MODE_NONE = 1,</div><div class='add'>+	XE_SRIOV_MODE_PF,</div><div class='add'>+	XE_SRIOV_MODE_VF,</div><div class='add'>+};</div><div class='add'>+static_assert(XE_SRIOV_MODE_NONE);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c<br/>new file mode 100644<br/>index 000000000000..eaf1b718f26c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_step.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step.c</a></div><div class='hunk'>@@ -0,0 +1,264 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Provide mapping between PCI's revision ID to the individual GMD</div><div class='add'>+ * (Graphics/Media/Display) stepping values that can be compared numerically.</div><div class='add'>+ *</div><div class='add'>+ * Some platforms may have unusual ways of mapping PCI revision ID to GMD</div><div class='add'>+ * steppings.  E.g., in some cases a higher PCI revision may translate to a</div><div class='add'>+ * lower stepping of the GT and/or display IP.</div><div class='add'>+ *</div><div class='add'>+ * Also note that some revisions/steppings may have been set aside as</div><div class='add'>+ * placeholders but never materialized in real hardware; in those cases there</div><div class='add'>+ * may be jumps in the revision IDs or stepping values in the tables below.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Some platforms always have the same stepping value for GT and display;</div><div class='add'>+ * use a macro to define these to make it easier to identify the platforms</div><div class='add'>+ * where the two steppings can deviate.</div><div class='add'>+ */</div><div class='add'>+#define COMMON_GT_MEDIA_STEP(x_)	\</div><div class='add'>+	.graphics = STEP_##x_,		\</div><div class='add'>+	.media = STEP_##x_</div><div class='add'>+</div><div class='add'>+#define COMMON_STEP(x_)			\</div><div class='add'>+	COMMON_GT_MEDIA_STEP(x_),	\</div><div class='add'>+	.graphics = STEP_##x_,		\</div><div class='add'>+	.media = STEP_##x_,		\</div><div class='add'>+	.display = STEP_##x_</div><div class='add'>+</div><div class='add'>+__diag_push();</div><div class='add'>+__diag_ignore_all("-Woverride-init", "Allow field overrides in table");</div><div class='add'>+</div><div class='add'>+/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */</div><div class='add'>+static const struct xe_step_info tgl_revids[] = {</div><div class='add'>+	[0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 },</div><div class='add'>+	[1] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_D0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info dg1_revids[] = {</div><div class='add'>+	[0] = { COMMON_STEP(A0) },</div><div class='add'>+	[1] = { COMMON_STEP(B0) },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info adls_revids[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },</div><div class='add'>+	[0x1] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A2 },</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },</div><div class='add'>+	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_B0 },</div><div class='add'>+	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info adls_rpls_revids[] = {</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_D0 },</div><div class='add'>+	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info adlp_revids[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },</div><div class='add'>+	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 },</div><div class='add'>+	[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_D0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info adlp_rpl_revids[] = {</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_E0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info adln_revids[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_D0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info dg2_g10_revid_step_tbl[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },</div><div class='add'>+	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_A0 },</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 },</div><div class='add'>+	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info dg2_g11_revid_step_tbl[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 },</div><div class='add'>+	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_C0 },</div><div class='add'>+	[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info dg2_g12_revid_step_tbl[] = {</div><div class='add'>+	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_C0 },</div><div class='add'>+	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_step_info pvc_revid_step_tbl[] = {</div><div class='add'>+	[0x5] = { .graphics = STEP_B0 },</div><div class='add'>+	[0x6] = { .graphics = STEP_B1 },</div><div class='add'>+	[0x7] = { .graphics = STEP_C0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int pvc_basedie_subids[] = {</div><div class='add'>+	[0x3] = STEP_B0,</div><div class='add'>+	[0x4] = STEP_B1,</div><div class='add'>+	[0x5] = STEP_B3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+__diag_pop();</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_step_pre_gmdid_get - Determine IP steppings from PCI revid</div><div class='add'>+ * @xe: Xe device</div><div class='add'>+ *</div><div class='add'>+ * Convert the PCI revid into proper IP steppings.  This should only be</div><div class='add'>+ * used on platforms that do not have GMD_ID support.</div><div class='add'>+ */</div><div class='add'>+struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	const struct xe_step_info *revids = NULL;</div><div class='add'>+	struct xe_step_info step = {};</div><div class='add'>+	u16 revid = xe-&gt;info.revid;</div><div class='add'>+	int size = 0;</div><div class='add'>+	const int *basedie_info = NULL;</div><div class='add'>+	int basedie_size = 0;</div><div class='add'>+	int baseid = 0;</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.platform == XE_PVC) {</div><div class='add'>+		baseid = FIELD_GET(GENMASK(5, 3), xe-&gt;info.revid);</div><div class='add'>+		revid = FIELD_GET(GENMASK(2, 0), xe-&gt;info.revid);</div><div class='add'>+		revids = pvc_revid_step_tbl;</div><div class='add'>+		size = ARRAY_SIZE(pvc_revid_step_tbl);</div><div class='add'>+		basedie_info = pvc_basedie_subids;</div><div class='add'>+		basedie_size = ARRAY_SIZE(pvc_basedie_subids);</div><div class='add'>+	} else if (xe-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G10) {</div><div class='add'>+		revids = dg2_g10_revid_step_tbl;</div><div class='add'>+		size = ARRAY_SIZE(dg2_g10_revid_step_tbl);</div><div class='add'>+	} else if (xe-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G11) {</div><div class='add'>+		revids = dg2_g11_revid_step_tbl;</div><div class='add'>+		size = ARRAY_SIZE(dg2_g11_revid_step_tbl);</div><div class='add'>+	} else if (xe-&gt;info.subplatform == XE_SUBPLATFORM_DG2_G12) {</div><div class='add'>+		revids = dg2_g12_revid_step_tbl;</div><div class='add'>+		size = ARRAY_SIZE(dg2_g12_revid_step_tbl);</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_ALDERLAKE_N) {</div><div class='add'>+		revids = adln_revids;</div><div class='add'>+		size = ARRAY_SIZE(adln_revids);</div><div class='add'>+	} else if (xe-&gt;info.subplatform == XE_SUBPLATFORM_ALDERLAKE_S_RPLS) {</div><div class='add'>+		revids = adls_rpls_revids;</div><div class='add'>+		size = ARRAY_SIZE(adls_rpls_revids);</div><div class='add'>+	} else if (xe-&gt;info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) {</div><div class='add'>+		revids = adlp_rpl_revids;</div><div class='add'>+		size = ARRAY_SIZE(adlp_rpl_revids);</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_ALDERLAKE_P) {</div><div class='add'>+		revids = adlp_revids;</div><div class='add'>+		size = ARRAY_SIZE(adlp_revids);</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_ALDERLAKE_S) {</div><div class='add'>+		revids = adls_revids;</div><div class='add'>+		size = ARRAY_SIZE(adls_revids);</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_DG1) {</div><div class='add'>+		revids = dg1_revids;</div><div class='add'>+		size = ARRAY_SIZE(dg1_revids);</div><div class='add'>+	} else if (xe-&gt;info.platform == XE_TIGERLAKE) {</div><div class='add'>+		revids = tgl_revids;</div><div class='add'>+		size = ARRAY_SIZE(tgl_revids);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Not using the stepping scheme for the platform yet. */</div><div class='add'>+	if (!revids)</div><div class='add'>+		return step;</div><div class='add'>+</div><div class='add'>+	if (revid &lt; size &amp;&amp; revids[revid].graphics != STEP_NONE) {</div><div class='add'>+		step = revids[revid];</div><div class='add'>+	} else {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "Unknown revid 0x%02x\n", revid);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * If we hit a gap in the revid array, use the information for</div><div class='add'>+		 * the next revid.</div><div class='add'>+		 *</div><div class='add'>+		 * This may be wrong in all sorts of ways, especially if the</div><div class='add'>+		 * steppings in the array are not monotonically increasing, but</div><div class='add'>+		 * it's better than defaulting to 0.</div><div class='add'>+		 */</div><div class='add'>+		while (revid &lt; size &amp;&amp; revids[revid].graphics == STEP_NONE)</div><div class='add'>+			revid++;</div><div class='add'>+</div><div class='add'>+		if (revid &lt; size) {</div><div class='add'>+			drm_dbg(&amp;xe-&gt;drm, "Using steppings for revid 0x%02x\n",</div><div class='add'>+				revid);</div><div class='add'>+			step = revids[revid];</div><div class='add'>+		} else {</div><div class='add'>+			drm_dbg(&amp;xe-&gt;drm, "Using future steppings\n");</div><div class='add'>+			step.graphics = STEP_FUTURE;</div><div class='add'>+			step.display = STEP_FUTURE;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, step.graphics == STEP_NONE);</div><div class='add'>+</div><div class='add'>+	if (basedie_info &amp;&amp; basedie_size) {</div><div class='add'>+		if (baseid &lt; basedie_size &amp;&amp; basedie_info[baseid] != STEP_NONE) {</div><div class='add'>+			step.basedie = basedie_info[baseid];</div><div class='add'>+		} else {</div><div class='add'>+			drm_warn(&amp;xe-&gt;drm, "Unknown baseid 0x%02x\n", baseid);</div><div class='add'>+			step.basedie = STEP_FUTURE;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return step;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_step_gmdid_get - Determine IP steppings from GMD_ID revid fields</div><div class='add'>+ * @xe: Xe device</div><div class='add'>+ * @graphics_gmdid_revid: value of graphics GMD_ID register's revid field</div><div class='add'>+ * @media_gmdid_revid: value of media GMD_ID register's revid field</div><div class='add'>+ *</div><div class='add'>+ * Convert the revid fields of the GMD_ID registers into proper IP steppings.</div><div class='add'>+ *</div><div class='add'>+ * GMD_ID revid values are currently expected to have consistent meanings on</div><div class='add'>+ * all platforms:  major steppings (A0, B0, etc.) are 4 apart, with minor</div><div class='add'>+ * steppings (A1, A2, etc.) taking the values in between.</div><div class='add'>+ */</div><div class='add'>+struct xe_step_info xe_step_gmdid_get(struct xe_device *xe,</div><div class='add'>+				      u32 graphics_gmdid_revid,</div><div class='add'>+				      u32 media_gmdid_revid)</div><div class='add'>+{</div><div class='add'>+	struct xe_step_info step = {</div><div class='add'>+		.graphics = STEP_A0 + graphics_gmdid_revid,</div><div class='add'>+		.media = STEP_A0 + media_gmdid_revid,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (step.graphics &gt;= STEP_FUTURE) {</div><div class='add'>+		step.graphics = STEP_FUTURE;</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Graphics GMD_ID revid value %d treated as future stepping\n",</div><div class='add'>+			graphics_gmdid_revid);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (step.media &gt;= STEP_FUTURE) {</div><div class='add'>+		step.media = STEP_FUTURE;</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "Media GMD_ID revid value %d treated as future stepping\n",</div><div class='add'>+			media_gmdid_revid);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return step;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define STEP_NAME_CASE(name)	\</div><div class='add'>+	case STEP_##name:	\</div><div class='add'>+		return #name;</div><div class='add'>+</div><div class='add'>+const char *xe_step_name(enum xe_step step)</div><div class='add'>+{</div><div class='add'>+	switch (step) {</div><div class='add'>+	STEP_NAME_LIST(STEP_NAME_CASE);</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return "**";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_step.h b/drivers/gpu/drm/xe/xe_step.h<br/>new file mode 100644<br/>index 000000000000..686cb59200c2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_step.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step.h</a></div><div class='hunk'>@@ -0,0 +1,23 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_STEP_H_</div><div class='add'>+#define _XE_STEP_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_step_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+struct xe_step_info xe_step_pre_gmdid_get(struct xe_device *xe);</div><div class='add'>+struct xe_step_info xe_step_gmdid_get(struct xe_device *xe,</div><div class='add'>+				      u32 graphics_gmdid_revid,</div><div class='add'>+				      u32 media_gmdid_revid);</div><div class='add'>+static inline u32 xe_step_to_gmdid(enum xe_step step) { return step - STEP_A0; }</div><div class='add'>+</div><div class='add'>+const char *xe_step_name(enum xe_step step);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_step_types.h b/drivers/gpu/drm/xe/xe_step_types.h<br/>new file mode 100644<br/>index 000000000000..ccc9b4795e95<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_step_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_step_types.h</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_STEP_TYPES_H_</div><div class='add'>+#define _XE_STEP_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_step_info {</div><div class='add'>+	u8 graphics;</div><div class='add'>+	u8 media;</div><div class='add'>+	u8 display;</div><div class='add'>+	u8 basedie;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define STEP_ENUM_VAL(name)  STEP_##name,</div><div class='add'>+</div><div class='add'>+#define STEP_NAME_LIST(func)		\</div><div class='add'>+	func(A0)			\</div><div class='add'>+	func(A1)			\</div><div class='add'>+	func(A2)			\</div><div class='add'>+	func(A3)			\</div><div class='add'>+	func(B0)			\</div><div class='add'>+	func(B1)			\</div><div class='add'>+	func(B2)			\</div><div class='add'>+	func(B3)			\</div><div class='add'>+	func(C0)			\</div><div class='add'>+	func(C1)			\</div><div class='add'>+	func(C2)			\</div><div class='add'>+	func(C3)			\</div><div class='add'>+	func(D0)			\</div><div class='add'>+	func(D1)			\</div><div class='add'>+	func(D2)			\</div><div class='add'>+	func(D3)			\</div><div class='add'>+	func(E0)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Symbolic steppings that do not match the hardware. These are valid both as gt</div><div class='add'>+ * and display steppings as symbolic names.</div><div class='add'>+ */</div><div class='add'>+enum xe_step {</div><div class='add'>+	STEP_NONE = 0,</div><div class='add'>+	STEP_NAME_LIST(STEP_ENUM_VAL)</div><div class='add'>+	STEP_FUTURE,</div><div class='add'>+	STEP_FOREVER,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c<br/>new file mode 100644<br/>index 000000000000..e4c220cf9115<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sync.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync.c</a></div><div class='hunk'>@@ -0,0 +1,344 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_sync.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence-array.h&gt;</div><div class='add'>+#include &lt;linux/kthread.h&gt;</div><div class='add'>+#include &lt;linux/sched/mm.h&gt;</div><div class='add'>+#include &lt;linux/uaccess.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+#include &lt;drm/drm_syncobj.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_sched_job_types.h"</div><div class='add'>+</div><div class='add'>+struct user_fence {</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+	struct kref refcount;</div><div class='add'>+	struct dma_fence_cb cb;</div><div class='add'>+	struct work_struct worker;</div><div class='add'>+	struct mm_struct *mm;</div><div class='add'>+	u64 __user *addr;</div><div class='add'>+	u64 value;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void user_fence_destroy(struct kref *kref)</div><div class='add'>+{</div><div class='add'>+	struct user_fence *ufence = container_of(kref, struct user_fence,</div><div class='add'>+						 refcount);</div><div class='add'>+</div><div class='add'>+	mmdrop(ufence-&gt;mm);</div><div class='add'>+	kfree(ufence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void user_fence_get(struct user_fence *ufence)</div><div class='add'>+{</div><div class='add'>+	kref_get(&amp;ufence-&gt;refcount);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void user_fence_put(struct user_fence *ufence)</div><div class='add'>+{</div><div class='add'>+	kref_put(&amp;ufence-&gt;refcount, user_fence_destroy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct user_fence *user_fence_create(struct xe_device *xe, u64 addr,</div><div class='add'>+					    u64 value)</div><div class='add'>+{</div><div class='add'>+	struct user_fence *ufence;</div><div class='add'>+</div><div class='add'>+	ufence = kmalloc(sizeof(*ufence), GFP_KERNEL);</div><div class='add'>+	if (!ufence)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	ufence-&gt;xe = xe;</div><div class='add'>+	kref_init(&amp;ufence-&gt;refcount);</div><div class='add'>+	ufence-&gt;addr = u64_to_user_ptr(addr);</div><div class='add'>+	ufence-&gt;value = value;</div><div class='add'>+	ufence-&gt;mm = current-&gt;mm;</div><div class='add'>+	mmgrab(ufence-&gt;mm);</div><div class='add'>+</div><div class='add'>+	return ufence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void user_fence_worker(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct user_fence *ufence = container_of(w, struct user_fence, worker);</div><div class='add'>+</div><div class='add'>+	if (mmget_not_zero(ufence-&gt;mm)) {</div><div class='add'>+		kthread_use_mm(ufence-&gt;mm);</div><div class='add'>+		if (copy_to_user(ufence-&gt;addr, &amp;ufence-&gt;value, sizeof(ufence-&gt;value)))</div><div class='add'>+			XE_WARN_ON("Copy to user failed");</div><div class='add'>+		kthread_unuse_mm(ufence-&gt;mm);</div><div class='add'>+		mmput(ufence-&gt;mm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wake_up_all(&amp;ufence-&gt;xe-&gt;ufence_wq);</div><div class='add'>+	user_fence_put(ufence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void kick_ufence(struct user_fence *ufence, struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	INIT_WORK(&amp;ufence-&gt;worker, user_fence_worker);</div><div class='add'>+	queue_work(ufence-&gt;xe-&gt;ordered_wq, &amp;ufence-&gt;worker);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void user_fence_cb(struct dma_fence *fence, struct dma_fence_cb *cb)</div><div class='add'>+{</div><div class='add'>+	struct user_fence *ufence = container_of(cb, struct user_fence, cb);</div><div class='add'>+</div><div class='add'>+	kick_ufence(ufence, fence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_sync_entry_parse(struct xe_device *xe, struct xe_file *xef,</div><div class='add'>+			struct xe_sync_entry *sync,</div><div class='add'>+			struct drm_xe_sync __user *sync_user,</div><div class='add'>+			unsigned int flags)</div><div class='add'>+{</div><div class='add'>+	struct drm_xe_sync sync_in;</div><div class='add'>+	int err;</div><div class='add'>+	bool exec = flags &amp; SYNC_PARSE_FLAG_EXEC;</div><div class='add'>+	bool in_lr_mode = flags &amp; SYNC_PARSE_FLAG_LR_MODE;</div><div class='add'>+	bool disallow_user_fence = flags &amp; SYNC_PARSE_FLAG_DISALLOW_USER_FENCE;</div><div class='add'>+	bool signal;</div><div class='add'>+</div><div class='add'>+	if (copy_from_user(&amp;sync_in, sync_user, sizeof(*sync_user)))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, sync_in.flags &amp; ~DRM_XE_SYNC_FLAG_SIGNAL) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, sync_in.reserved[0] || sync_in.reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	signal = sync_in.flags &amp; DRM_XE_SYNC_FLAG_SIGNAL;</div><div class='add'>+	switch (sync_in.type) {</div><div class='add'>+	case DRM_XE_SYNC_TYPE_SYNCOBJ:</div><div class='add'>+		if (XE_IOCTL_DBG(xe, in_lr_mode &amp;&amp; signal))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, upper_32_bits(sync_in.addr)))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		sync-&gt;syncobj = drm_syncobj_find(xef-&gt;drm, sync_in.handle);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !sync-&gt;syncobj))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		if (!signal) {</div><div class='add'>+			sync-&gt;fence = drm_syncobj_fence_get(sync-&gt;syncobj);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !sync-&gt;fence))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ:</div><div class='add'>+		if (XE_IOCTL_DBG(xe, in_lr_mode &amp;&amp; signal))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, upper_32_bits(sync_in.addr)))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, sync_in.timeline_value == 0))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		sync-&gt;syncobj = drm_syncobj_find(xef-&gt;drm, sync_in.handle);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !sync-&gt;syncobj))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+</div><div class='add'>+		if (signal) {</div><div class='add'>+			sync-&gt;chain_fence = dma_fence_chain_alloc();</div><div class='add'>+			if (!sync-&gt;chain_fence)</div><div class='add'>+				return -ENOMEM;</div><div class='add'>+		} else {</div><div class='add'>+			sync-&gt;fence = drm_syncobj_fence_get(sync-&gt;syncobj);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !sync-&gt;fence))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			err = dma_fence_chain_find_seqno(&amp;sync-&gt;fence,</div><div class='add'>+							 sync_in.timeline_value);</div><div class='add'>+			if (err)</div><div class='add'>+				return err;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case DRM_XE_SYNC_TYPE_USER_FENCE:</div><div class='add'>+		if (XE_IOCTL_DBG(xe, disallow_user_fence))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !signal))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, sync_in.addr &amp; 0x7))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (exec) {</div><div class='add'>+			sync-&gt;addr = sync_in.addr;</div><div class='add'>+		} else {</div><div class='add'>+			sync-&gt;ufence = user_fence_create(xe, sync_in.addr,</div><div class='add'>+							 sync_in.timeline_value);</div><div class='add'>+			if (XE_IOCTL_DBG(xe, !sync-&gt;ufence))</div><div class='add'>+				return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sync-&gt;type = sync_in.type;</div><div class='add'>+	sync-&gt;flags = sync_in.flags;</div><div class='add'>+	sync-&gt;timeline_value = sync_in.timeline_value;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_sync_entry_wait(struct xe_sync_entry *sync)</div><div class='add'>+{</div><div class='add'>+	if (sync-&gt;fence)</div><div class='add'>+		dma_fence_wait(sync-&gt;fence, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_sync_entry_add_deps(struct xe_sync_entry *sync, struct xe_sched_job *job)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (sync-&gt;fence) {</div><div class='add'>+		err = drm_sched_job_add_dependency(&amp;job-&gt;drm,</div><div class='add'>+						   dma_fence_get(sync-&gt;fence));</div><div class='add'>+		if (err) {</div><div class='add'>+			dma_fence_put(sync-&gt;fence);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sync_entry_signal(struct xe_sync_entry *sync, struct xe_sched_job *job,</div><div class='add'>+			  struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	if (!(sync-&gt;flags &amp; DRM_XE_SYNC_FLAG_SIGNAL))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (sync-&gt;chain_fence) {</div><div class='add'>+		drm_syncobj_add_point(sync-&gt;syncobj, sync-&gt;chain_fence,</div><div class='add'>+				      fence, sync-&gt;timeline_value);</div><div class='add'>+		/*</div><div class='add'>+		 * The chain's ownership is transferred to the</div><div class='add'>+		 * timeline.</div><div class='add'>+		 */</div><div class='add'>+		sync-&gt;chain_fence = NULL;</div><div class='add'>+	} else if (sync-&gt;syncobj) {</div><div class='add'>+		drm_syncobj_replace_fence(sync-&gt;syncobj, fence);</div><div class='add'>+	} else if (sync-&gt;ufence) {</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		dma_fence_get(fence);</div><div class='add'>+		user_fence_get(sync-&gt;ufence);</div><div class='add'>+		err = dma_fence_add_callback(fence, &amp;sync-&gt;ufence-&gt;cb,</div><div class='add'>+					     user_fence_cb);</div><div class='add'>+		if (err == -ENOENT) {</div><div class='add'>+			kick_ufence(sync-&gt;ufence, fence);</div><div class='add'>+		} else if (err) {</div><div class='add'>+			XE_WARN_ON("failed to add user fence");</div><div class='add'>+			user_fence_put(sync-&gt;ufence);</div><div class='add'>+			dma_fence_put(fence);</div><div class='add'>+		}</div><div class='add'>+	} else if (sync-&gt;type == DRM_XE_SYNC_TYPE_USER_FENCE) {</div><div class='add'>+		job-&gt;user_fence.used = true;</div><div class='add'>+		job-&gt;user_fence.addr = sync-&gt;addr;</div><div class='add'>+		job-&gt;user_fence.value = sync-&gt;timeline_value;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_sync_entry_cleanup(struct xe_sync_entry *sync)</div><div class='add'>+{</div><div class='add'>+	if (sync-&gt;syncobj)</div><div class='add'>+		drm_syncobj_put(sync-&gt;syncobj);</div><div class='add'>+	if (sync-&gt;fence)</div><div class='add'>+		dma_fence_put(sync-&gt;fence);</div><div class='add'>+	if (sync-&gt;chain_fence)</div><div class='add'>+		dma_fence_put(&amp;sync-&gt;chain_fence-&gt;base);</div><div class='add'>+	if (sync-&gt;ufence)</div><div class='add'>+		user_fence_put(sync-&gt;ufence);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_sync_in_fence_get() - Get a fence from syncs, exec queue, and VM</div><div class='add'>+ * @sync: input syncs</div><div class='add'>+ * @num_sync: number of syncs</div><div class='add'>+ * @q: exec queue</div><div class='add'>+ * @vm: VM</div><div class='add'>+ *</div><div class='add'>+ * Get a fence from syncs, exec queue, and VM. If syncs contain in-fences create</div><div class='add'>+ * and return a composite fence of all in-fences + last fence. If no in-fences</div><div class='add'>+ * return last fence on  input exec queue. Caller must drop reference to</div><div class='add'>+ * returned fence.</div><div class='add'>+ *</div><div class='add'>+ * Return: fence on success, ERR_PTR(-ENOMEM) on failure</div><div class='add'>+ */</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,</div><div class='add'>+		     struct xe_exec_queue *q, struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence **fences = NULL;</div><div class='add'>+	struct dma_fence_array *cf = NULL;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	int i, num_in_fence = 0, current_fence = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Count in-fences */</div><div class='add'>+	for (i = 0; i &lt; num_sync; ++i) {</div><div class='add'>+		if (sync[i].fence) {</div><div class='add'>+			++num_in_fence;</div><div class='add'>+			fence = sync[i].fence;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Easy case... */</div><div class='add'>+	if (!num_in_fence) {</div><div class='add'>+		fence = xe_exec_queue_last_fence_get(q, vm);</div><div class='add'>+		dma_fence_get(fence);</div><div class='add'>+		return fence;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Create composite fence */</div><div class='add'>+	fences = kmalloc_array(num_in_fence + 1, sizeof(*fences), GFP_KERNEL);</div><div class='add'>+	if (!fences)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	for (i = 0; i &lt; num_sync; ++i) {</div><div class='add'>+		if (sync[i].fence) {</div><div class='add'>+			dma_fence_get(sync[i].fence);</div><div class='add'>+			fences[current_fence++] = sync[i].fence;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	fences[current_fence++] = xe_exec_queue_last_fence_get(q, vm);</div><div class='add'>+	dma_fence_get(fences[current_fence - 1]);</div><div class='add'>+	cf = dma_fence_array_create(num_in_fence, fences,</div><div class='add'>+				    vm-&gt;composite_fence_ctx,</div><div class='add'>+				    vm-&gt;composite_fence_seqno++,</div><div class='add'>+				    false);</div><div class='add'>+	if (!cf) {</div><div class='add'>+		--vm-&gt;composite_fence_seqno;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;cf-&gt;base;</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	while (current_fence)</div><div class='add'>+		dma_fence_put(fences[--current_fence]);</div><div class='add'>+	kfree(fences);</div><div class='add'>+	kfree(cf);</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-ENOMEM);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sync.h b/drivers/gpu/drm/xe/xe_sync.h<br/>new file mode 100644<br/>index 000000000000..d284afbe917c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sync.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync.h</a></div><div class='hunk'>@@ -0,0 +1,36 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SYNC_H_</div><div class='add'>+#define _XE_SYNC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_sync_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_file;</div><div class='add'>+struct xe_sched_job;</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+#define SYNC_PARSE_FLAG_EXEC			BIT(0)</div><div class='add'>+#define SYNC_PARSE_FLAG_LR_MODE			BIT(1)</div><div class='add'>+#define SYNC_PARSE_FLAG_DISALLOW_USER_FENCE	BIT(2)</div><div class='add'>+</div><div class='add'>+int xe_sync_entry_parse(struct xe_device *xe, struct xe_file *xef,</div><div class='add'>+			struct xe_sync_entry *sync,</div><div class='add'>+			struct drm_xe_sync __user *sync_user,</div><div class='add'>+			unsigned int flags);</div><div class='add'>+int xe_sync_entry_wait(struct xe_sync_entry *sync);</div><div class='add'>+int xe_sync_entry_add_deps(struct xe_sync_entry *sync,</div><div class='add'>+			   struct xe_sched_job *job);</div><div class='add'>+void xe_sync_entry_signal(struct xe_sync_entry *sync,</div><div class='add'>+			  struct xe_sched_job *job,</div><div class='add'>+			  struct dma_fence *fence);</div><div class='add'>+void xe_sync_entry_cleanup(struct xe_sync_entry *sync);</div><div class='add'>+struct dma_fence *</div><div class='add'>+xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,</div><div class='add'>+		     struct xe_exec_queue *q, struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_sync_types.h b/drivers/gpu/drm/xe/xe_sync_types.h<br/>new file mode 100644<br/>index 000000000000..852db5e7884f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_sync_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_sync_types.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_SYNC_TYPES_H_</div><div class='add'>+#define _XE_SYNC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct drm_syncobj;</div><div class='add'>+struct dma_fence;</div><div class='add'>+struct dma_fence_chain;</div><div class='add'>+struct drm_xe_sync;</div><div class='add'>+struct user_fence;</div><div class='add'>+</div><div class='add'>+struct xe_sync_entry {</div><div class='add'>+	struct drm_syncobj *syncobj;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct dma_fence_chain *chain_fence;</div><div class='add'>+	struct user_fence *ufence;</div><div class='add'>+	u64 addr;</div><div class='add'>+	u64 timeline_value;</div><div class='add'>+	u32 type;</div><div class='add'>+	u32 flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c<br/>new file mode 100644<br/>index 000000000000..044c20881de7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tile.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile.c</a></div><div class='hunk'>@@ -0,0 +1,185 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_ggtt.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_sa.h"</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+#include "xe_tile_sysfs.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Multi-tile Design</div><div class='add'>+ *</div><div class='add'>+ * Different vendors use the term "tile" a bit differently, but in the Intel</div><div class='add'>+ * world, a 'tile' is pretty close to what most people would think of as being</div><div class='add'>+ * a complete GPU.  When multiple GPUs are placed behind a single PCI device,</div><div class='add'>+ * that's what is referred to as a "multi-tile device."  In such cases, pretty</div><div class='add'>+ * much all hardware is replicated per-tile, although certain responsibilities</div><div class='add'>+ * like PCI communication, reporting of interrupts to the OS, etc. are handled</div><div class='add'>+ * solely by the "root tile."  A multi-tile platform takes care of tying the</div><div class='add'>+ * tiles together in a way such that interrupt notifications from remote tiles</div><div class='add'>+ * are forwarded to the root tile, the per-tile vram is combined into a single</div><div class='add'>+ * address space, etc.</div><div class='add'>+ *</div><div class='add'>+ * In contrast, a "GT" (which officially stands for "Graphics Technology") is</div><div class='add'>+ * the subset of a GPU/tile that is responsible for implementing graphics</div><div class='add'>+ * and/or media operations.  The GT is where a lot of the driver implementation</div><div class='add'>+ * happens since it's where the hardware engines, the execution units, and the</div><div class='add'>+ * GuC all reside.</div><div class='add'>+ *</div><div class='add'>+ * Historically most Intel devices were single-tile devices that contained a</div><div class='add'>+ * single GT.  PVC is an example of an Intel platform built on a multi-tile</div><div class='add'>+ * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only</div><div class='add'>+ * has a single GT.  In contrast, platforms like MTL that have separate chips</div><div class='add'>+ * for render and media IP are still only a single logical GPU, but the</div><div class='add'>+ * graphics and media IP blocks are each exposed as a separate GT within that</div><div class='add'>+ * single GPU.  This is important from a software perspective because multi-GT</div><div class='add'>+ * platforms like MTL only replicate a subset of the GPU hardware and behave</div><div class='add'>+ * differently than multi-tile platforms like PVC where nearly everything is</div><div class='add'>+ * replicated.</div><div class='add'>+ *</div><div class='add'>+ * Per-tile functionality (shared by all GTs within the tile):</div><div class='add'>+ *  - Complete 4MB MMIO space (containing SGunit/SoC registers, GT</div><div class='add'>+ *    registers, display registers, etc.)</div><div class='add'>+ *  - Global GTT</div><div class='add'>+ *  - VRAM (if discrete)</div><div class='add'>+ *  - Interrupt flows</div><div class='add'>+ *  - Migration context</div><div class='add'>+ *  - kernel batchbuffer pool</div><div class='add'>+ *  - Primary GT</div><div class='add'>+ *  - Media GT (if media version &gt;= 13)</div><div class='add'>+ *</div><div class='add'>+ * Per-GT functionality:</div><div class='add'>+ *  - GuC</div><div class='add'>+ *  - Hardware engines</div><div class='add'>+ *  - Programmable hardware units (subslices, EUs)</div><div class='add'>+ *  - GSI subset of registers (multiple copies of these registers reside</div><div class='add'>+ *    within the complete MMIO space provided by the tile, but at different</div><div class='add'>+ *    offsets --- 0 for render, 0x380000 for media)</div><div class='add'>+ *  - Multicast register steering</div><div class='add'>+ *  - TLBs to cache page table translations</div><div class='add'>+ *  - Reset capability</div><div class='add'>+ *  - Low-level power management (e.g., C6)</div><div class='add'>+ *  - Clock frequency</div><div class='add'>+ *  - MOCS and PAT programming</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tile_alloc - Perform per-tile memory allocation</div><div class='add'>+ * @tile: Tile to perform allocations for</div><div class='add'>+ *</div><div class='add'>+ * Allocates various per-tile data structures using DRM-managed allocations.</div><div class='add'>+ * Does not touch the hardware.</div><div class='add'>+ *</div><div class='add'>+ * Returns -ENOMEM if allocations fail, otherwise 0.</div><div class='add'>+ */</div><div class='add'>+static int xe_tile_alloc(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct drm_device *drm = &amp;tile_to_xe(tile)-&gt;drm;</div><div class='add'>+</div><div class='add'>+	tile-&gt;mem.ggtt = drmm_kzalloc(drm, sizeof(*tile-&gt;mem.ggtt),</div><div class='add'>+				      GFP_KERNEL);</div><div class='add'>+	if (!tile-&gt;mem.ggtt)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	tile-&gt;mem.ggtt-&gt;tile = tile;</div><div class='add'>+</div><div class='add'>+	tile-&gt;mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile-&gt;mem.vram_mgr), GFP_KERNEL);</div><div class='add'>+	if (!tile-&gt;mem.vram_mgr)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tile_init_early - Initialize the tile and primary GT</div><div class='add'>+ * @tile: Tile to initialize</div><div class='add'>+ * @xe: Parent Xe device</div><div class='add'>+ * @id: Tile ID</div><div class='add'>+ *</div><div class='add'>+ * Initializes per-tile resources that don't require any interactions with the</div><div class='add'>+ * hardware or any knowledge about the Graphics/Media IP version.</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	tile-&gt;xe = xe;</div><div class='add'>+	tile-&gt;id = id;</div><div class='add'>+</div><div class='add'>+	err = xe_tile_alloc(tile);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	tile-&gt;primary_gt = xe_gt_alloc(tile);</div><div class='add'>+	if (IS_ERR(tile-&gt;primary_gt))</div><div class='add'>+		return PTR_ERR(tile-&gt;primary_gt);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tile_ttm_mgr_init(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (tile-&gt;mem.vram.usable_size) {</div><div class='add'>+		err = xe_ttm_vram_mgr_init(tile, tile-&gt;mem.vram_mgr);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+		xe-&gt;info.mem_region_mask |= BIT(tile-&gt;id) &lt;&lt; 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.</div><div class='add'>+ * @tile: The tile to initialize.</div><div class='add'>+ *</div><div class='add'>+ * This function prepares the tile to allow memory allocations to VRAM, but is</div><div class='add'>+ * not allowed to allocate memory itself. This state is useful for display</div><div class='add'>+ * readout, because the inherited display framebuffer will otherwise be</div><div class='add'>+ * overwritten as it is usually put at the start of VRAM.</div><div class='add'>+ *</div><div class='add'>+ * Note that since this is tile initialization, it should not perform any</div><div class='add'>+ * GT-specific operations, and thus does not need to hold GT forcewake.</div><div class='add'>+ *</div><div class='add'>+ * Returns: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_tile_init_noalloc(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_device_mem_access_get(tile_to_xe(tile));</div><div class='add'>+</div><div class='add'>+	err = tile_ttm_mgr_init(tile);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_mem_access;</div><div class='add'>+</div><div class='add'>+	tile-&gt;mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);</div><div class='add'>+	if (IS_ERR(tile-&gt;mem.kernel_bb_pool))</div><div class='add'>+		err = PTR_ERR(tile-&gt;mem.kernel_bb_pool);</div><div class='add'>+</div><div class='add'>+	xe_wa_apply_tile_workarounds(tile);</div><div class='add'>+</div><div class='add'>+	xe_tile_sysfs_init(tile);</div><div class='add'>+</div><div class='add'>+err_mem_access:</div><div class='add'>+	xe_device_mem_access_put(tile_to_xe(tile));</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_tile_migrate_wait(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	xe_migrate_wait(tile-&gt;migrate);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tile.h b/drivers/gpu/drm/xe/xe_tile.h<br/>new file mode 100644<br/>index 000000000000..1c9e42ade6b0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tile.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile.h</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TILE_H_</div><div class='add'>+#define _XE_TILE_H_</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_tile;</div><div class='add'>+</div><div class='add'>+int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id);</div><div class='add'>+int xe_tile_init_noalloc(struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+void xe_tile_migrate_wait(struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs.c b/drivers/gpu/drm/xe/xe_tile_sysfs.c<br/>new file mode 100644<br/>index 000000000000..0f8d3e7fce46<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tile_sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs.c</a></div><div class='hunk'>@@ -0,0 +1,57 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_tile.h"</div><div class='add'>+#include "xe_tile_sysfs.h"</div><div class='add'>+</div><div class='add'>+static void xe_tile_sysfs_kobj_release(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	kfree(kobj);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct kobj_type xe_tile_sysfs_kobj_type = {</div><div class='add'>+	.release = xe_tile_sysfs_kobj_release,</div><div class='add'>+	.sysfs_ops = &amp;kobj_sysfs_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void tile_sysfs_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = arg;</div><div class='add'>+</div><div class='add'>+	kobject_put(tile-&gt;sysfs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_tile_sysfs_init(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+	struct kobj_tile *kt;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	kt = kzalloc(sizeof(*kt), GFP_KERNEL);</div><div class='add'>+	if (!kt)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	kobject_init(&amp;kt-&gt;base, &amp;xe_tile_sysfs_kobj_type);</div><div class='add'>+	kt-&gt;tile = tile;</div><div class='add'>+</div><div class='add'>+	err = kobject_add(&amp;kt-&gt;base, &amp;dev-&gt;kobj, "tile%d", tile-&gt;id);</div><div class='add'>+	if (err) {</div><div class='add'>+		kobject_put(&amp;kt-&gt;base);</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "failed to register TILE sysfs directory, err: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tile-&gt;sysfs = &amp;kt-&gt;base;</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, tile_sysfs_fini, tile);</div><div class='add'>+	if (err)</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s: drmm_add_action_or_reset failed, err: %d\n",</div><div class='add'>+			 __func__, err);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs.h b/drivers/gpu/drm/xe/xe_tile_sysfs.h<br/>new file mode 100644<br/>index 000000000000..e4f065039eba<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tile_sysfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs.h</a></div><div class='hunk'>@@ -0,0 +1,19 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TILE_SYSFS_H_</div><div class='add'>+#define _XE_TILE_SYSFS_H_</div><div class='add'>+</div><div class='add'>+#include "xe_tile_sysfs_types.h"</div><div class='add'>+</div><div class='add'>+void xe_tile_sysfs_init(struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+static inline struct xe_tile *</div><div class='add'>+kobj_to_tile(struct kobject *kobj)</div><div class='add'>+{</div><div class='add'>+	return container_of(kobj, struct kobj_tile, base)-&gt;tile;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif /* _XE_TILE_SYSFS_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tile_sysfs_types.h b/drivers/gpu/drm/xe/xe_tile_sysfs_types.h<br/>new file mode 100644<br/>index 000000000000..75906ba11a9e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tile_sysfs_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tile_sysfs_types.h</a></div><div class='hunk'>@@ -0,0 +1,27 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TILE_SYSFS_TYPES_H_</div><div class='add'>+#define _XE_TILE_SYSFS_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kobject.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_tile;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct kobj_tile - A tile's kobject struct that connects the kobject</div><div class='add'>+ * and the TILE</div><div class='add'>+ *</div><div class='add'>+ * When dealing with multiple TILEs, this struct helps to understand which</div><div class='add'>+ * TILE needs to be addressed on a given sysfs call.</div><div class='add'>+ */</div><div class='add'>+struct kobj_tile {</div><div class='add'>+	/** @base: The actual kobject */</div><div class='add'>+	struct kobject base;</div><div class='add'>+	/** @tile: A pointer to the tile itself */</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif	/* _XE_TILE_SYSFS_TYPES_H_ */</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_trace.c b/drivers/gpu/drm/xe/xe_trace.c<br/>new file mode 100644<br/>index 000000000000..2527c556bff1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_trace.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_trace.c</a></div><div class='hunk'>@@ -0,0 +1,9 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __CHECKER__</div><div class='add'>+#define CREATE_TRACE_POINTS</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h<br/>new file mode 100644<br/>index 000000000000..95163c303f3e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_trace.h</a></div><div class='hunk'>@@ -0,0 +1,608 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#undef TRACE_SYSTEM</div><div class='add'>+#define TRACE_SYSTEM xe</div><div class='add'>+</div><div class='add'>+#if !defined(_XE_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)</div><div class='add'>+#define _XE_TRACE_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/tracepoint.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo_types.h"</div><div class='add'>+#include "xe_exec_queue_types.h"</div><div class='add'>+#include "xe_gpu_scheduler_types.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation_types.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_guc_exec_queue_types.h"</div><div class='add'>+#include "xe_sched_job.h"</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_gt_tlb_invalidation_fence,</div><div class='add'>+		    TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+		    TP_ARGS(fence),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u64, fence)</div><div class='add'>+			     __field(int, seqno)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;fence = (u64)fence;</div><div class='add'>+			   __entry-&gt;seqno = fence-&gt;seqno;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("fence=0x%016llx, seqno=%d",</div><div class='add'>+			      __entry-&gt;fence, __entry-&gt;seqno)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_create,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence,</div><div class='add'>+	     xe_gt_tlb_invalidation_fence_work_func,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_cb,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_send,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_recv,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_signal,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_gt_tlb_invalidation_fence, xe_gt_tlb_invalidation_fence_timeout,</div><div class='add'>+	     TP_PROTO(struct xe_gt_tlb_invalidation_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_bo,</div><div class='add'>+		    TP_PROTO(struct xe_bo *bo),</div><div class='add'>+		    TP_ARGS(bo),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(size_t, size)</div><div class='add'>+			     __field(u32, flags)</div><div class='add'>+			     __field(u64, vm)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;size = bo-&gt;size;</div><div class='add'>+			   __entry-&gt;flags = bo-&gt;flags;</div><div class='add'>+			   __entry-&gt;vm = (unsigned long)bo-&gt;vm;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("size=%zu, flags=0x%02x, vm=0x%016llx",</div><div class='add'>+			      __entry-&gt;size, __entry-&gt;flags, __entry-&gt;vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_bo, xe_bo_cpu_fault,</div><div class='add'>+	     TP_PROTO(struct xe_bo *bo),</div><div class='add'>+	     TP_ARGS(bo)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_bo, xe_bo_move,</div><div class='add'>+	     TP_PROTO(struct xe_bo *bo),</div><div class='add'>+	     TP_ARGS(bo)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_exec_queue,</div><div class='add'>+		    TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+		    TP_ARGS(q),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(enum xe_engine_class, class)</div><div class='add'>+			     __field(u32, logical_mask)</div><div class='add'>+			     __field(u8, gt_id)</div><div class='add'>+			     __field(u16, width)</div><div class='add'>+			     __field(u16, guc_id)</div><div class='add'>+			     __field(u32, guc_state)</div><div class='add'>+			     __field(u32, flags)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;class = q-&gt;class;</div><div class='add'>+			   __entry-&gt;logical_mask = q-&gt;logical_mask;</div><div class='add'>+			   __entry-&gt;gt_id = q-&gt;gt-&gt;info.id;</div><div class='add'>+			   __entry-&gt;width = q-&gt;width;</div><div class='add'>+			   __entry-&gt;guc_id = q-&gt;guc-&gt;id;</div><div class='add'>+			   __entry-&gt;guc_state = atomic_read(&amp;q-&gt;guc-&gt;state);</div><div class='add'>+			   __entry-&gt;flags = q-&gt;flags;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("%d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x",</div><div class='add'>+			      __entry-&gt;class, __entry-&gt;logical_mask,</div><div class='add'>+			      __entry-&gt;gt_id, __entry-&gt;width, __entry-&gt;guc_id,</div><div class='add'>+			      __entry-&gt;guc_state, __entry-&gt;flags)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_create,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_supress_resume,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_submit,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_enable,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_disable,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_done,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_register,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister_done,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_close,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_kill,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cleanup_entity,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_destroy,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_reset,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_memory_cat_error,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_stop,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_resubmit,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_lr_cleanup,</div><div class='add'>+	     TP_PROTO(struct xe_exec_queue *q),</div><div class='add'>+	     TP_ARGS(q)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_sched_job,</div><div class='add'>+		    TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+		    TP_ARGS(job),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u32, seqno)</div><div class='add'>+			     __field(u16, guc_id)</div><div class='add'>+			     __field(u32, guc_state)</div><div class='add'>+			     __field(u32, flags)</div><div class='add'>+			     __field(int, error)</div><div class='add'>+			     __field(u64, fence)</div><div class='add'>+			     __field(u64, batch_addr)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;seqno = xe_sched_job_seqno(job);</div><div class='add'>+			   __entry-&gt;guc_id = job-&gt;q-&gt;guc-&gt;id;</div><div class='add'>+			   __entry-&gt;guc_state =</div><div class='add'>+			   atomic_read(&amp;job-&gt;q-&gt;guc-&gt;state);</div><div class='add'>+			   __entry-&gt;flags = job-&gt;q-&gt;flags;</div><div class='add'>+			   __entry-&gt;error = job-&gt;fence-&gt;error;</div><div class='add'>+			   __entry-&gt;fence = (unsigned long)job-&gt;fence;</div><div class='add'>+			   __entry-&gt;batch_addr = (u64)job-&gt;batch_addr[0];</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("fence=0x%016llx, seqno=%u, guc_id=%d, batch_addr=0x%012llx, guc_state=0x%x, flags=0x%x, error=%d",</div><div class='add'>+			      __entry-&gt;fence, __entry-&gt;seqno, __entry-&gt;guc_id,</div><div class='add'>+			      __entry-&gt;batch_addr, __entry-&gt;guc_state,</div><div class='add'>+			      __entry-&gt;flags, __entry-&gt;error)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_create,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_exec,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_run,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_free,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_timedout,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_set_error,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_job, xe_sched_job_ban,</div><div class='add'>+	     TP_PROTO(struct xe_sched_job *job),</div><div class='add'>+	     TP_ARGS(job)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_sched_msg,</div><div class='add'>+		    TP_PROTO(struct xe_sched_msg *msg),</div><div class='add'>+		    TP_ARGS(msg),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u32, opcode)</div><div class='add'>+			     __field(u16, guc_id)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;opcode = msg-&gt;opcode;</div><div class='add'>+			   __entry-&gt;guc_id =</div><div class='add'>+			   ((struct xe_exec_queue *)msg-&gt;private_data)-&gt;guc-&gt;id;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("guc_id=%d, opcode=%u", __entry-&gt;guc_id,</div><div class='add'>+			      __entry-&gt;opcode)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_msg, xe_sched_msg_add,</div><div class='add'>+	     TP_PROTO(struct xe_sched_msg *msg),</div><div class='add'>+	     TP_ARGS(msg)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_sched_msg, xe_sched_msg_recv,</div><div class='add'>+	     TP_PROTO(struct xe_sched_msg *msg),</div><div class='add'>+	     TP_ARGS(msg)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_hw_fence,</div><div class='add'>+		    TP_PROTO(struct xe_hw_fence *fence),</div><div class='add'>+		    TP_ARGS(fence),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u64, ctx)</div><div class='add'>+			     __field(u32, seqno)</div><div class='add'>+			     __field(u64, fence)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;ctx = fence-&gt;dma.context;</div><div class='add'>+			   __entry-&gt;seqno = fence-&gt;dma.seqno;</div><div class='add'>+			   __entry-&gt;fence = (unsigned long)fence;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("ctx=0x%016llx, fence=0x%016llx, seqno=%u",</div><div class='add'>+			      __entry-&gt;ctx, __entry-&gt;fence, __entry-&gt;seqno)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_hw_fence, xe_hw_fence_create,</div><div class='add'>+	     TP_PROTO(struct xe_hw_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_hw_fence, xe_hw_fence_signal,</div><div class='add'>+	     TP_PROTO(struct xe_hw_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_hw_fence, xe_hw_fence_try_signal,</div><div class='add'>+	     TP_PROTO(struct xe_hw_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_hw_fence, xe_hw_fence_free,</div><div class='add'>+	     TP_PROTO(struct xe_hw_fence *fence),</div><div class='add'>+	     TP_ARGS(fence)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_vma,</div><div class='add'>+		    TP_PROTO(struct xe_vma *vma),</div><div class='add'>+		    TP_ARGS(vma),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u64, vma)</div><div class='add'>+			     __field(u32, asid)</div><div class='add'>+			     __field(u64, start)</div><div class='add'>+			     __field(u64, end)</div><div class='add'>+			     __field(u64, ptr)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;vma = (unsigned long)vma;</div><div class='add'>+			   __entry-&gt;asid = xe_vma_vm(vma)-&gt;usm.asid;</div><div class='add'>+			   __entry-&gt;start = xe_vma_start(vma);</div><div class='add'>+			   __entry-&gt;end = xe_vma_end(vma) - 1;</div><div class='add'>+			   __entry-&gt;ptr = xe_vma_userptr(vma);</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("vma=0x%016llx, asid=0x%05x, start=0x%012llx, end=0x%012llx, ptr=0x%012llx,",</div><div class='add'>+			      __entry-&gt;vma, __entry-&gt;asid, __entry-&gt;start,</div><div class='add'>+			      __entry-&gt;end, __entry-&gt;ptr)</div><div class='add'>+)</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_flush,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_pagefault,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_acc,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_fail,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_bind,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_pf_bind,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_unbind,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_userptr_rebind_worker,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_userptr_rebind_exec,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_rebind_worker,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_rebind_exec,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_userptr_invalidate,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_usm_invalidate,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_evict,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vma, xe_vma_userptr_invalidate_complete,</div><div class='add'>+	     TP_PROTO(struct xe_vma *vma),</div><div class='add'>+	     TP_ARGS(vma)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_vm,</div><div class='add'>+		    TP_PROTO(struct xe_vm *vm),</div><div class='add'>+		    TP_ARGS(vm),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u64, vm)</div><div class='add'>+			     __field(u32, asid)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;vm = (unsigned long)vm;</div><div class='add'>+			   __entry-&gt;asid = vm-&gt;usm.asid;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("vm=0x%016llx, asid=0x%05x",  __entry-&gt;vm,</div><div class='add'>+			      __entry-&gt;asid)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_kill,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_create,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_free,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_cpu_bind,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_restart,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_rebind_worker_enter,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_rebind_worker_retry,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_vm, xe_vm_rebind_worker_exit,</div><div class='add'>+	     TP_PROTO(struct xe_vm *vm),</div><div class='add'>+	     TP_ARGS(vm)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+/* GuC */</div><div class='add'>+DECLARE_EVENT_CLASS(xe_guc_ct_flow_control,</div><div class='add'>+		    TP_PROTO(u32 _head, u32 _tail, u32 size, u32 space, u32 len),</div><div class='add'>+		    TP_ARGS(_head, _tail, size, space, len),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+			     __field(u32, _head)</div><div class='add'>+			     __field(u32, _tail)</div><div class='add'>+			     __field(u32, size)</div><div class='add'>+			     __field(u32, space)</div><div class='add'>+			     __field(u32, len)</div><div class='add'>+			     ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			   __entry-&gt;_head = _head;</div><div class='add'>+			   __entry-&gt;_tail = _tail;</div><div class='add'>+			   __entry-&gt;size = size;</div><div class='add'>+			   __entry-&gt;space = space;</div><div class='add'>+			   __entry-&gt;len = len;</div><div class='add'>+			   ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("h2g flow control: head=%u, tail=%u, size=%u, space=%u, len=%u",</div><div class='add'>+			      __entry-&gt;_head, __entry-&gt;_tail, __entry-&gt;size,</div><div class='add'>+			      __entry-&gt;space, __entry-&gt;len)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_guc_ct_flow_control, xe_guc_ct_h2g_flow_control,</div><div class='add'>+	     TP_PROTO(u32 _head, u32 _tail, u32 size, u32 space, u32 len),</div><div class='add'>+	     TP_ARGS(_head, _tail, size, space, len)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT_PRINT(xe_guc_ct_flow_control, xe_guc_ct_g2h_flow_control,</div><div class='add'>+		   TP_PROTO(u32 _head, u32 _tail, u32 size, u32 space, u32 len),</div><div class='add'>+		   TP_ARGS(_head, _tail, size, space, len),</div><div class='add'>+</div><div class='add'>+		   TP_printk("g2h flow control: head=%u, tail=%u, size=%u, space=%u, len=%u",</div><div class='add'>+			     __entry-&gt;_head, __entry-&gt;_tail, __entry-&gt;size,</div><div class='add'>+			     __entry-&gt;space, __entry-&gt;len)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(xe_guc_ctb,</div><div class='add'>+		    TP_PROTO(u8 gt_id, u32 action, u32 len, u32 _head, u32 tail),</div><div class='add'>+		    TP_ARGS(gt_id, action, len, _head, tail),</div><div class='add'>+</div><div class='add'>+		    TP_STRUCT__entry(</div><div class='add'>+				__field(u8, gt_id)</div><div class='add'>+				__field(u32, action)</div><div class='add'>+				__field(u32, len)</div><div class='add'>+				__field(u32, tail)</div><div class='add'>+				__field(u32, _head)</div><div class='add'>+		    ),</div><div class='add'>+</div><div class='add'>+		    TP_fast_assign(</div><div class='add'>+			    __entry-&gt;gt_id = gt_id;</div><div class='add'>+			    __entry-&gt;action = action;</div><div class='add'>+			    __entry-&gt;len = len;</div><div class='add'>+			    __entry-&gt;tail = tail;</div><div class='add'>+			    __entry-&gt;_head = _head;</div><div class='add'>+		    ),</div><div class='add'>+</div><div class='add'>+		    TP_printk("gt%d: H2G CTB: action=0x%x, len=%d, tail=%d, head=%d\n",</div><div class='add'>+			      __entry-&gt;gt_id, __entry-&gt;action, __entry-&gt;len,</div><div class='add'>+			      __entry-&gt;tail, __entry-&gt;_head)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(xe_guc_ctb, xe_guc_ctb_h2g,</div><div class='add'>+	     TP_PROTO(u8 gt_id, u32 action, u32 len, u32 _head, u32 tail),</div><div class='add'>+	     TP_ARGS(gt_id, action, len, _head, tail)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT_PRINT(xe_guc_ctb, xe_guc_ctb_g2h,</div><div class='add'>+		   TP_PROTO(u8 gt_id, u32 action, u32 len, u32 _head, u32 tail),</div><div class='add'>+		   TP_ARGS(gt_id, action, len, _head, tail),</div><div class='add'>+</div><div class='add'>+		   TP_printk("gt%d: G2H CTB: action=0x%x, len=%d, tail=%d, head=%d\n",</div><div class='add'>+			     __entry-&gt;gt_id, __entry-&gt;action, __entry-&gt;len,</div><div class='add'>+			     __entry-&gt;tail, __entry-&gt;_head)</div><div class='add'>+</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/* This part must be outside protection */</div><div class='add'>+#undef TRACE_INCLUDE_PATH</div><div class='add'>+#undef TRACE_INCLUDE_FILE</div><div class='add'>+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe</div><div class='add'>+#define TRACE_INCLUDE_FILE xe_trace</div><div class='add'>+#include &lt;trace/define_trace.h&gt;</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c<br/>new file mode 100644<br/>index 000000000000..e5d7d5e2bec1<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,334 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021-2023 Intel Corporation</div><div class='add'>+ * Copyright (C) 2021-2002 Red Hat</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;drm/drm_mm.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_device.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_range_manager.h&gt;</div><div class='add'>+</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_ttm_stolen_mgr.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+struct xe_ttm_stolen_mgr {</div><div class='add'>+	struct xe_ttm_vram_mgr base;</div><div class='add'>+</div><div class='add'>+	/* PCI base offset */</div><div class='add'>+	resource_size_t io_base;</div><div class='add'>+	/* GPU base offset */</div><div class='add'>+	resource_size_t stolen_base;</div><div class='add'>+</div><div class='add'>+	void __iomem *mapping;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct xe_ttm_stolen_mgr *</div><div class='add'>+to_stolen_mgr(struct ttm_resource_manager *man)</div><div class='add'>+{</div><div class='add'>+	return container_of(man, struct xe_ttm_stolen_mgr, base.manager);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_ttm_stolen_cpu_access_needs_ggtt() - If we can't directly CPU access</div><div class='add'>+ * stolen, can we then fallback to mapping through the GGTT.</div><div class='add'>+ * @xe: xe device</div><div class='add'>+ *</div><div class='add'>+ * Some older integrated platforms don't support reliable CPU access for stolen,</div><div class='add'>+ * however on such hardware we can always use the mappable part of the GGTT for</div><div class='add'>+ * CPU access. Check if that's the case for this device.</div><div class='add'>+ */</div><div class='add'>+bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return GRAPHICS_VERx100(xe) &lt; 1270 &amp;&amp; !IS_DGFX(xe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = xe_device_get_root_tile(xe);</div><div class='add'>+	struct xe_gt *mmio = xe_root_mmio_gt(xe);</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	u64 stolen_size;</div><div class='add'>+	u64 tile_offset;</div><div class='add'>+	u64 tile_size;</div><div class='add'>+</div><div class='add'>+	tile_offset = tile-&gt;mem.vram.io_start - xe-&gt;mem.vram.io_start;</div><div class='add'>+	tile_size = tile-&gt;mem.vram.actual_physical_size;</div><div class='add'>+</div><div class='add'>+	/* Use DSM base address instead for stolen memory */</div><div class='add'>+	mgr-&gt;stolen_base = (xe_mmio_read64_2x32(mmio, DSMBASE) &amp; BDSM_MASK) - tile_offset;</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, tile_size &lt; mgr-&gt;stolen_base))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	stolen_size = tile_size - mgr-&gt;stolen_base;</div><div class='add'>+</div><div class='add'>+	/* Verify usage fits in the actual resource available */</div><div class='add'>+	if (mgr-&gt;stolen_base + stolen_size &lt;= pci_resource_len(pdev, LMEM_BAR))</div><div class='add'>+		mgr-&gt;io_base = tile-&gt;mem.vram.io_start + mgr-&gt;stolen_base;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * There may be few KB of platform dependent reserved memory at the end</div><div class='add'>+	 * of vram which is not part of the DSM. Such reserved memory portion is</div><div class='add'>+	 * always less then DSM granularity so align down the stolen_size to DSM</div><div class='add'>+	 * granularity to accommodate such reserve vram portion.</div><div class='add'>+	 */</div><div class='add'>+	return ALIGN_DOWN(stolen_size, SZ_1M);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_wopcm_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	u32 wopcm_size;</div><div class='add'>+	u64 val;</div><div class='add'>+</div><div class='add'>+	val = xe_mmio_read64_2x32(xe_root_mmio_gt(xe), STOLEN_RESERVED);</div><div class='add'>+	val = REG_FIELD_GET64(WOPCM_SIZE_MASK, val);</div><div class='add'>+</div><div class='add'>+	switch (val) {</div><div class='add'>+	case 0x5 ... 0x6:</div><div class='add'>+		val--;</div><div class='add'>+		fallthrough;</div><div class='add'>+	case 0x0 ... 0x3:</div><div class='add'>+		wopcm_size = (1U &lt;&lt; val) * SZ_1M;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		WARN(1, "Missing case wopcm_size=%llx\n", val);</div><div class='add'>+		wopcm_size = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wopcm_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	struct xe_gt *media_gt = xe_device_get_root_tile(xe)-&gt;media_gt;</div><div class='add'>+	u32 stolen_size, wopcm_size;</div><div class='add'>+	u32 ggc, gms;</div><div class='add'>+</div><div class='add'>+	ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check GGMS: it should be fixed 0x3 (8MB), which corresponds to the</div><div class='add'>+	 * GTT size</div><div class='add'>+	 */</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, (ggc &amp; GGMS_MASK) != GGMS_MASK))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Graphics &gt;= 1270 uses the offset to the GSMBASE as address in the</div><div class='add'>+	 * PTEs, together with the DM flag being set. Previously there was no</div><div class='add'>+	 * such flag so the address was the io_base.</div><div class='add'>+	 *</div><div class='add'>+	 * DSMBASE = GSMBASE + 8MB</div><div class='add'>+	 */</div><div class='add'>+	mgr-&gt;stolen_base = SZ_8M;</div><div class='add'>+	mgr-&gt;io_base = pci_resource_start(pdev, 2) + mgr-&gt;stolen_base;</div><div class='add'>+</div><div class='add'>+	/* return valid GMS value, -EIO if invalid */</div><div class='add'>+	gms = REG_FIELD_GET(GMS_MASK, ggc);</div><div class='add'>+	switch (gms) {</div><div class='add'>+	case 0x0 ... 0x04:</div><div class='add'>+		stolen_size = gms * 32 * SZ_1M;</div><div class='add'>+		break;</div><div class='add'>+	case 0xf0 ... 0xfe:</div><div class='add'>+		stolen_size = (gms - 0xf0 + 1) * 4 * SZ_1M;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Carve out the top of DSM as it contains the reserved WOPCM region */</div><div class='add'>+	wopcm_size = get_wopcm_size(xe);</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, !wopcm_size))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	stolen_size -= wopcm_size;</div><div class='add'>+</div><div class='add'>+	if (media_gt &amp;&amp; XE_WA(media_gt, 14019821291)) {</div><div class='add'>+		u64 gscpsmi_base = xe_mmio_read64_2x32(media_gt, GSCPSMI_BASE)</div><div class='add'>+			&amp; ~GENMASK_ULL(5, 0);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This workaround is primarily implemented by the BIOS.  We</div><div class='add'>+		 * just need to figure out whether the BIOS has applied the</div><div class='add'>+		 * workaround (meaning the programmed address falls within</div><div class='add'>+		 * the DSM) and, if so, reserve that part of the DSM to</div><div class='add'>+		 * prevent accidental reuse.  The DSM location should be just</div><div class='add'>+		 * below the WOPCM.</div><div class='add'>+		 */</div><div class='add'>+		if (gscpsmi_base &gt;= mgr-&gt;io_base &amp;&amp;</div><div class='add'>+		    gscpsmi_base &lt; mgr-&gt;io_base + stolen_size) {</div><div class='add'>+			xe_gt_dbg(media_gt,</div><div class='add'>+				  "Reserving %llu bytes of DSM for Wa_14019821291\n",</div><div class='add'>+				  mgr-&gt;io_base + stolen_size - gscpsmi_base);</div><div class='add'>+			stolen_size = gscpsmi_base - mgr-&gt;io_base;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, stolen_size + SZ_8M &gt; pci_resource_len(pdev, 2)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return stolen_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+extern struct resource intel_graphics_stolen_res;</div><div class='add'>+</div><div class='add'>+static u64 detect_stolen(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)</div><div class='add'>+{</div><div class='add'>+#ifdef CONFIG_X86</div><div class='add'>+	/* Map into GGTT */</div><div class='add'>+	mgr-&gt;io_base = pci_resource_start(to_pci_dev(xe-&gt;drm.dev), 2);</div><div class='add'>+</div><div class='add'>+	/* Stolen memory is x86 only */</div><div class='add'>+	mgr-&gt;stolen_base = intel_graphics_stolen_res.start;</div><div class='add'>+	return resource_size(&amp;intel_graphics_stolen_res);</div><div class='add'>+#else</div><div class='add'>+	return 0;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ttm_stolen_mgr_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_stolen_mgr *mgr = drmm_kzalloc(&amp;xe-&gt;drm, sizeof(*mgr), GFP_KERNEL);</div><div class='add'>+	struct pci_dev *pdev = to_pci_dev(xe-&gt;drm.dev);</div><div class='add'>+	u64 stolen_size, io_size, pgsize;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe))</div><div class='add'>+		stolen_size = detect_bar2_dgfx(xe, mgr);</div><div class='add'>+	else if (GRAPHICS_VERx100(xe) &gt;= 1270)</div><div class='add'>+		stolen_size = detect_bar2_integrated(xe, mgr);</div><div class='add'>+	else</div><div class='add'>+		stolen_size = detect_stolen(xe, mgr);</div><div class='add'>+</div><div class='add'>+	if (!stolen_size) {</div><div class='add'>+		drm_dbg_kms(&amp;xe-&gt;drm, "No stolen memory support\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pgsize = xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;</div><div class='add'>+	if (pgsize &lt; PAGE_SIZE)</div><div class='add'>+		pgsize = PAGE_SIZE;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We don't try to attempt partial visible support for stolen vram,</div><div class='add'>+	 * since stolen is always at the end of vram, and the BAR size is pretty</div><div class='add'>+	 * much always 256M, with small-bar.</div><div class='add'>+	 */</div><div class='add'>+	io_size = 0;</div><div class='add'>+	if (mgr-&gt;io_base &amp;&amp; !xe_ttm_stolen_cpu_access_needs_ggtt(xe))</div><div class='add'>+		io_size = stolen_size;</div><div class='add'>+</div><div class='add'>+	err = __xe_ttm_vram_mgr_init(xe, &amp;mgr-&gt;base, XE_PL_STOLEN, stolen_size,</div><div class='add'>+				     io_size, pgsize);</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_dbg_kms(&amp;xe-&gt;drm, "Stolen mgr init failed: %i\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_dbg_kms(&amp;xe-&gt;drm, "Initialized stolen memory support with %llu bytes\n",</div><div class='add'>+		    stolen_size);</div><div class='add'>+</div><div class='add'>+	if (io_size)</div><div class='add'>+		mgr-&gt;mapping = devm_ioremap_wc(&amp;pdev-&gt;dev, mgr-&gt;io_base, io_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_ttm_stolen_io_offset(struct xe_bo *bo, u32 offset)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	struct ttm_resource_manager *ttm_mgr = ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_STOLEN);</div><div class='add'>+	struct xe_ttm_stolen_mgr *mgr = to_stolen_mgr(ttm_mgr);</div><div class='add'>+	struct xe_res_cursor cur;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!mgr-&gt;io_base);</div><div class='add'>+</div><div class='add'>+	if (xe_ttm_stolen_cpu_access_needs_ggtt(xe))</div><div class='add'>+		return mgr-&gt;io_base + xe_bo_ggtt_addr(bo) + offset;</div><div class='add'>+</div><div class='add'>+	xe_res_first(bo-&gt;ttm.resource, offset, 4096, &amp;cur);</div><div class='add'>+	return mgr-&gt;io_base + cur.start;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_ttm_stolen_io_mem_reserve_bar2(struct xe_device *xe,</div><div class='add'>+					       struct xe_ttm_stolen_mgr *mgr,</div><div class='add'>+					       struct ttm_resource *mem)</div><div class='add'>+{</div><div class='add'>+	struct xe_res_cursor cur;</div><div class='add'>+</div><div class='add'>+	if (!mgr-&gt;io_base)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	xe_res_first(mem, 0, 4096, &amp;cur);</div><div class='add'>+	mem-&gt;bus.offset = cur.start;</div><div class='add'>+</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, !(mem-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS));</div><div class='add'>+</div><div class='add'>+	if (mem-&gt;placement &amp; TTM_PL_FLAG_CONTIGUOUS &amp;&amp; mgr-&gt;mapping)</div><div class='add'>+		mem-&gt;bus.addr = (u8 __force *)mgr-&gt;mapping + mem-&gt;bus.offset;</div><div class='add'>+</div><div class='add'>+	mem-&gt;bus.offset += mgr-&gt;io_base;</div><div class='add'>+	mem-&gt;bus.is_iomem = true;</div><div class='add'>+	mem-&gt;bus.caching = ttm_write_combined;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_ttm_stolen_io_mem_reserve_stolen(struct xe_device *xe,</div><div class='add'>+						 struct xe_ttm_stolen_mgr *mgr,</div><div class='add'>+						 struct ttm_resource *mem)</div><div class='add'>+{</div><div class='add'>+#ifdef CONFIG_X86</div><div class='add'>+	struct xe_bo *bo = ttm_to_xe_bo(mem-&gt;bo);</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(IS_DGFX(xe));</div><div class='add'>+</div><div class='add'>+	/* XXX: Require BO to be mapped to GGTT? */</div><div class='add'>+	if (drm_WARN_ON(&amp;xe-&gt;drm, !(bo-&gt;flags &amp; XE_BO_CREATE_GGTT_BIT)))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	/* GGTT is always contiguously mapped */</div><div class='add'>+	mem-&gt;bus.offset = xe_bo_ggtt_addr(bo) + mgr-&gt;io_base;</div><div class='add'>+</div><div class='add'>+	mem-&gt;bus.is_iomem = true;</div><div class='add'>+	mem-&gt;bus.caching = ttm_write_combined;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+#else</div><div class='add'>+	/* How is it even possible to get here without gen12 stolen? */</div><div class='add'>+	drm_WARN_ON(&amp;xe-&gt;drm, 1);</div><div class='add'>+	return -EIO;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ttm_stolen_io_mem_reserve(struct xe_device *xe, struct ttm_resource *mem)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *ttm_mgr = ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_STOLEN);</div><div class='add'>+	struct xe_ttm_stolen_mgr *mgr = ttm_mgr ? to_stolen_mgr(ttm_mgr) : NULL;</div><div class='add'>+</div><div class='add'>+	if (!mgr || !mgr-&gt;io_base)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	if (xe_ttm_stolen_cpu_access_needs_ggtt(xe))</div><div class='add'>+		return __xe_ttm_stolen_io_mem_reserve_stolen(xe, mgr, mem);</div><div class='add'>+	else</div><div class='add'>+		return __xe_ttm_stolen_io_mem_reserve_bar2(xe, mgr, mem);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_ttm_stolen_gpu_offset(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_stolen_mgr *mgr =</div><div class='add'>+		to_stolen_mgr(ttm_manager_type(&amp;xe-&gt;ttm, XE_PL_STOLEN));</div><div class='add'>+</div><div class='add'>+	return mgr-&gt;stolen_base;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h<br/>new file mode 100644<br/>index 000000000000..1777245ff810<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h</a></div><div class='hunk'>@@ -0,0 +1,21 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TTM_STOLEN_MGR_H_</div><div class='add'>+#define _XE_TTM_STOLEN_MGR_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct ttm_resource;</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+void xe_ttm_stolen_mgr_init(struct xe_device *xe);</div><div class='add'>+int xe_ttm_stolen_io_mem_reserve(struct xe_device *xe, struct ttm_resource *mem);</div><div class='add'>+bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe);</div><div class='add'>+u64 xe_ttm_stolen_io_offset(struct xe_bo *bo, u32 offset);</div><div class='add'>+u64 xe_ttm_stolen_gpu_offset(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_sys_mgr.c b/drivers/gpu/drm/xe/xe_ttm_sys_mgr.c<br/>new file mode 100644<br/>index 000000000000..3e1fa0c832ca<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_sys_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_sys_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,118 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021-2022 Intel Corporation</div><div class='add'>+ * Copyright (C) 2021-2002 Red Hat</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_ttm_sys_mgr.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_range_manager.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+</div><div class='add'>+struct xe_ttm_sys_node {</div><div class='add'>+	struct ttm_buffer_object *tbo;</div><div class='add'>+	struct ttm_range_mgr_node base;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct xe_ttm_sys_node *</div><div class='add'>+to_xe_ttm_sys_node(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	return container_of(res, struct xe_ttm_sys_node, base.base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_ttm_sys_mgr_new(struct ttm_resource_manager *man,</div><div class='add'>+			      struct ttm_buffer_object *tbo,</div><div class='add'>+			      const struct ttm_place *place,</div><div class='add'>+			      struct ttm_resource **res)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_sys_node *node;</div><div class='add'>+	int r;</div><div class='add'>+</div><div class='add'>+	node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL);</div><div class='add'>+	if (!node)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	node-&gt;tbo = tbo;</div><div class='add'>+	ttm_resource_init(tbo, place, &amp;node-&gt;base.base);</div><div class='add'>+</div><div class='add'>+	if (!(place-&gt;flags &amp; TTM_PL_FLAG_TEMPORARY) &amp;&amp;</div><div class='add'>+	    ttm_resource_manager_usage(man) &gt; (man-&gt;size &lt;&lt; PAGE_SHIFT)) {</div><div class='add'>+		r = -ENOSPC;</div><div class='add'>+		goto err_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	node-&gt;base.mm_nodes[0].start = 0;</div><div class='add'>+	node-&gt;base.mm_nodes[0].size = PFN_UP(node-&gt;base.base.size);</div><div class='add'>+	node-&gt;base.base.start = XE_BO_INVALID_OFFSET;</div><div class='add'>+</div><div class='add'>+	*res = &amp;node-&gt;base.base;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_fini:</div><div class='add'>+	ttm_resource_fini(man, &amp;node-&gt;base.base);</div><div class='add'>+	kfree(node);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_sys_mgr_del(struct ttm_resource_manager *man,</div><div class='add'>+			       struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_sys_node *node = to_xe_ttm_sys_node(res);</div><div class='add'>+</div><div class='add'>+	ttm_resource_fini(man, res);</div><div class='add'>+	kfree(node);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_sys_mgr_debug(struct ttm_resource_manager *man,</div><div class='add'>+				 struct drm_printer *printer)</div><div class='add'>+{</div><div class='add'>+</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct ttm_resource_manager_func xe_ttm_sys_mgr_func = {</div><div class='add'>+	.alloc = xe_ttm_sys_mgr_new,</div><div class='add'>+	.free = xe_ttm_sys_mgr_del,</div><div class='add'>+	.debug = xe_ttm_sys_mgr_debug</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void ttm_sys_mgr_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = (struct xe_device *)arg;</div><div class='add'>+	struct ttm_resource_manager *man = &amp;xe-&gt;mem.sys_mgr;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	ttm_resource_manager_set_used(man, false);</div><div class='add'>+</div><div class='add'>+	err = ttm_resource_manager_evict_all(&amp;xe-&gt;ttm, man);</div><div class='add'>+	if (err)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ttm_resource_manager_cleanup(man);</div><div class='add'>+	ttm_set_driver_manager(&amp;xe-&gt;ttm, XE_PL_TT, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ttm_sys_mgr_init(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *man = &amp;xe-&gt;mem.sys_mgr;</div><div class='add'>+	struct sysinfo si;</div><div class='add'>+	u64 gtt_size;</div><div class='add'>+</div><div class='add'>+	si_meminfo(&amp;si);</div><div class='add'>+	gtt_size = (u64)si.totalram * si.mem_unit;</div><div class='add'>+	/* TTM limits allocation of all TTM devices by 50% of system memory */</div><div class='add'>+	gtt_size /= 2;</div><div class='add'>+</div><div class='add'>+	man-&gt;use_tt = true;</div><div class='add'>+	man-&gt;func = &amp;xe_ttm_sys_mgr_func;</div><div class='add'>+	ttm_resource_manager_init(man, &amp;xe-&gt;ttm, gtt_size &gt;&gt; PAGE_SHIFT);</div><div class='add'>+	ttm_set_driver_manager(&amp;xe-&gt;ttm, XE_PL_TT, man);</div><div class='add'>+	ttm_resource_manager_set_used(man, true);</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, ttm_sys_mgr_fini, xe);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_sys_mgr.h b/drivers/gpu/drm/xe/xe_ttm_sys_mgr.h<br/>new file mode 100644<br/>index 000000000000..e8f5cd395b28<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_sys_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_sys_mgr.h</a></div><div class='hunk'>@@ -0,0 +1,13 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2023 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TTM_SYS_MGR_H_</div><div class='add'>+#define _XE_TTM_SYS_MGR_H_</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+int xe_ttm_sys_mgr_init(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c<br/>new file mode 100644<br/>index 000000000000..115ec745e502<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr.c</a></div><div class='hunk'>@@ -0,0 +1,480 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021-2022 Intel Corporation</div><div class='add'>+ * Copyright (C) 2021-2002 Red Hat</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/ttm/ttm_placement.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_range_manager.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_ttm_vram_mgr.h"</div><div class='add'>+</div><div class='add'>+static inline struct drm_buddy_block *</div><div class='add'>+xe_ttm_vram_mgr_first_block(struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	return list_first_entry_or_null(list, struct drm_buddy_block, link);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_is_vram_mgr_blocks_contiguous(struct drm_buddy *mm,</div><div class='add'>+						    struct list_head *head)</div><div class='add'>+{</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+	u64 start, size;</div><div class='add'>+</div><div class='add'>+	block = xe_ttm_vram_mgr_first_block(head);</div><div class='add'>+	if (!block)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	while (head != block-&gt;link.next) {</div><div class='add'>+		start = drm_buddy_block_offset(block);</div><div class='add'>+		size = drm_buddy_block_size(mm, block);</div><div class='add'>+</div><div class='add'>+		block = list_entry(block-&gt;link.next, struct drm_buddy_block,</div><div class='add'>+				   link);</div><div class='add'>+		if (start + size != drm_buddy_block_offset(block))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,</div><div class='add'>+			       struct ttm_buffer_object *tbo,</div><div class='add'>+			       const struct ttm_place *place,</div><div class='add'>+			       struct ttm_resource **res)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+	struct xe_ttm_vram_mgr_resource *vres;</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+	u64 size, remaining_size, min_page_size;</div><div class='add'>+	unsigned long lpfn;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lpfn = place-&gt;lpfn;</div><div class='add'>+	if (!lpfn || lpfn &gt; man-&gt;size &gt;&gt; PAGE_SHIFT)</div><div class='add'>+		lpfn = man-&gt;size &gt;&gt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	if (tbo-&gt;base.size &gt;&gt; PAGE_SHIFT &gt; (lpfn - place-&gt;fpfn))</div><div class='add'>+		return -E2BIG; /* don't trigger eviction for the impossible */</div><div class='add'>+</div><div class='add'>+	vres = kzalloc(sizeof(*vres), GFP_KERNEL);</div><div class='add'>+	if (!vres)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ttm_resource_init(tbo, place, &amp;vres-&gt;base);</div><div class='add'>+</div><div class='add'>+	/* bail out quickly if there's likely not enough VRAM for this BO */</div><div class='add'>+	if (ttm_resource_manager_usage(man) &gt; man-&gt;size) {</div><div class='add'>+		err = -ENOSPC;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vres-&gt;blocks);</div><div class='add'>+</div><div class='add'>+	if (place-&gt;flags &amp; TTM_PL_FLAG_TOPDOWN)</div><div class='add'>+		vres-&gt;flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;</div><div class='add'>+</div><div class='add'>+	if (place-&gt;fpfn || lpfn != man-&gt;size &gt;&gt; PAGE_SHIFT)</div><div class='add'>+		vres-&gt;flags |= DRM_BUDDY_RANGE_ALLOCATION;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!vres-&gt;base.size)) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+	size = vres-&gt;base.size;</div><div class='add'>+</div><div class='add'>+	min_page_size = mgr-&gt;default_page_size;</div><div class='add'>+	if (tbo-&gt;page_alignment)</div><div class='add'>+		min_page_size = tbo-&gt;page_alignment &lt;&lt; PAGE_SHIFT;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(min_page_size &lt; mm-&gt;chunk_size)) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(min_page_size &gt; SZ_2G)) { /* FIXME: sg limit */</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (WARN_ON((size &gt; SZ_2G &amp;&amp;</div><div class='add'>+		     (vres-&gt;base.placement &amp; TTM_PL_FLAG_CONTIGUOUS)))) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!IS_ALIGNED(size, min_page_size))) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	if (lpfn &lt;= mgr-&gt;visible_size &gt;&gt; PAGE_SHIFT &amp;&amp; size &gt; mgr-&gt;visible_avail) {</div><div class='add'>+		mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+		err = -ENOSPC;</div><div class='add'>+		goto error_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (place-&gt;fpfn + (size &gt;&gt; PAGE_SHIFT) != place-&gt;lpfn &amp;&amp;</div><div class='add'>+	    place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS) {</div><div class='add'>+		size = roundup_pow_of_two(size);</div><div class='add'>+		min_page_size = size;</div><div class='add'>+</div><div class='add'>+		lpfn = max_t(unsigned long, place-&gt;fpfn + (size &gt;&gt; PAGE_SHIFT), lpfn);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	remaining_size = size;</div><div class='add'>+	do {</div><div class='add'>+		/*</div><div class='add'>+		 * Limit maximum size to 2GiB due to SG table limitations.</div><div class='add'>+		 * FIXME: Should maybe be handled as part of sg construction.</div><div class='add'>+		 */</div><div class='add'>+		u64 alloc_size = min_t(u64, remaining_size, SZ_2G);</div><div class='add'>+</div><div class='add'>+		err = drm_buddy_alloc_blocks(mm, (u64)place-&gt;fpfn &lt;&lt; PAGE_SHIFT,</div><div class='add'>+					     (u64)lpfn &lt;&lt; PAGE_SHIFT,</div><div class='add'>+					     alloc_size,</div><div class='add'>+					     min_page_size,</div><div class='add'>+					     &amp;vres-&gt;blocks,</div><div class='add'>+					     vres-&gt;flags);</div><div class='add'>+		if (err)</div><div class='add'>+			goto error_free_blocks;</div><div class='add'>+</div><div class='add'>+		remaining_size -= alloc_size;</div><div class='add'>+	} while (remaining_size);</div><div class='add'>+</div><div class='add'>+	if (place-&gt;flags &amp; TTM_PL_FLAG_CONTIGUOUS) {</div><div class='add'>+		if (!drm_buddy_block_trim(mm, vres-&gt;base.size, &amp;vres-&gt;blocks))</div><div class='add'>+			size = vres-&gt;base.size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (lpfn &lt;= mgr-&gt;visible_size &gt;&gt; PAGE_SHIFT) {</div><div class='add'>+		vres-&gt;used_visible_size = size;</div><div class='add'>+	} else {</div><div class='add'>+		struct drm_buddy_block *block;</div><div class='add'>+</div><div class='add'>+		list_for_each_entry(block, &amp;vres-&gt;blocks, link) {</div><div class='add'>+			u64 start = drm_buddy_block_offset(block);</div><div class='add'>+</div><div class='add'>+			if (start &lt; mgr-&gt;visible_size) {</div><div class='add'>+				u64 end = start + drm_buddy_block_size(mm, block);</div><div class='add'>+</div><div class='add'>+				vres-&gt;used_visible_size +=</div><div class='add'>+					min(end, mgr-&gt;visible_size) - start;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mgr-&gt;visible_avail -= vres-&gt;used_visible_size;</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (!(vres-&gt;base.placement &amp; TTM_PL_FLAG_CONTIGUOUS) &amp;&amp;</div><div class='add'>+	    xe_is_vram_mgr_blocks_contiguous(mm, &amp;vres-&gt;blocks))</div><div class='add'>+		vres-&gt;base.placement |= TTM_PL_FLAG_CONTIGUOUS;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For some kernel objects we still rely on the start when io mapping</div><div class='add'>+	 * the object.</div><div class='add'>+	 */</div><div class='add'>+	if (vres-&gt;base.placement &amp; TTM_PL_FLAG_CONTIGUOUS) {</div><div class='add'>+		struct drm_buddy_block *block = list_first_entry(&amp;vres-&gt;blocks,</div><div class='add'>+								 typeof(*block),</div><div class='add'>+								 link);</div><div class='add'>+</div><div class='add'>+		vres-&gt;base.start = drm_buddy_block_offset(block) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	} else {</div><div class='add'>+		vres-&gt;base.start = XE_BO_INVALID_OFFSET;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*res = &amp;vres-&gt;base;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_free_blocks:</div><div class='add'>+	drm_buddy_free_list(mm, &amp;vres-&gt;blocks);</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+error_fini:</div><div class='add'>+	ttm_resource_fini(man, &amp;vres-&gt;base);</div><div class='add'>+	kfree(vres);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_vram_mgr_del(struct ttm_resource_manager *man,</div><div class='add'>+				struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr_resource *vres =</div><div class='add'>+		to_xe_ttm_vram_mgr_resource(res);</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	drm_buddy_free_list(mm, &amp;vres-&gt;blocks);</div><div class='add'>+	mgr-&gt;visible_avail += vres-&gt;used_visible_size;</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ttm_resource_fini(man, res);</div><div class='add'>+</div><div class='add'>+	kfree(vres);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_ttm_vram_mgr_debug(struct ttm_resource_manager *man,</div><div class='add'>+				  struct drm_printer *printer)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	drm_printf(printer, "default_page_size: %lluKiB\n",</div><div class='add'>+		   mgr-&gt;default_page_size &gt;&gt; 10);</div><div class='add'>+	drm_printf(printer, "visible_avail: %lluMiB\n",</div><div class='add'>+		   (u64)mgr-&gt;visible_avail &gt;&gt; 20);</div><div class='add'>+	drm_printf(printer, "visible_size: %lluMiB\n",</div><div class='add'>+		   (u64)mgr-&gt;visible_size &gt;&gt; 20);</div><div class='add'>+</div><div class='add'>+	drm_buddy_print(mm, printer);</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+	drm_printf(printer, "man size:%llu\n", man-&gt;size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_ttm_vram_mgr_intersects(struct ttm_resource_manager *man,</div><div class='add'>+				       struct ttm_resource *res,</div><div class='add'>+				       const struct ttm_place *place,</div><div class='add'>+				       size_t size)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+	struct xe_ttm_vram_mgr_resource *vres =</div><div class='add'>+		to_xe_ttm_vram_mgr_resource(res);</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+</div><div class='add'>+	if (!place-&gt;fpfn &amp;&amp; !place-&gt;lpfn)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (!place-&gt;fpfn &amp;&amp; place-&gt;lpfn == mgr-&gt;visible_size &gt;&gt; PAGE_SHIFT)</div><div class='add'>+		return vres-&gt;used_visible_size &gt; 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(block, &amp;vres-&gt;blocks, link) {</div><div class='add'>+		unsigned long fpfn =</div><div class='add'>+			drm_buddy_block_offset(block) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+		unsigned long lpfn = fpfn +</div><div class='add'>+			(drm_buddy_block_size(mm, block) &gt;&gt; PAGE_SHIFT);</div><div class='add'>+</div><div class='add'>+		if (place-&gt;fpfn &lt; lpfn &amp;&amp; place-&gt;lpfn &gt; fpfn)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_ttm_vram_mgr_compatible(struct ttm_resource_manager *man,</div><div class='add'>+				       struct ttm_resource *res,</div><div class='add'>+				       const struct ttm_place *place,</div><div class='add'>+				       size_t size)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+	struct xe_ttm_vram_mgr_resource *vres =</div><div class='add'>+		to_xe_ttm_vram_mgr_resource(res);</div><div class='add'>+	struct drm_buddy *mm = &amp;mgr-&gt;mm;</div><div class='add'>+	struct drm_buddy_block *block;</div><div class='add'>+</div><div class='add'>+	if (!place-&gt;fpfn &amp;&amp; !place-&gt;lpfn)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	if (!place-&gt;fpfn &amp;&amp; place-&gt;lpfn == mgr-&gt;visible_size &gt;&gt; PAGE_SHIFT)</div><div class='add'>+		return vres-&gt;used_visible_size == size;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(block, &amp;vres-&gt;blocks, link) {</div><div class='add'>+		unsigned long fpfn =</div><div class='add'>+			drm_buddy_block_offset(block) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+		unsigned long lpfn = fpfn +</div><div class='add'>+			(drm_buddy_block_size(mm, block) &gt;&gt; PAGE_SHIFT);</div><div class='add'>+</div><div class='add'>+		if (fpfn &lt; place-&gt;fpfn || lpfn &gt; place-&gt;lpfn)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct ttm_resource_manager_func xe_ttm_vram_mgr_func = {</div><div class='add'>+	.alloc	= xe_ttm_vram_mgr_new,</div><div class='add'>+	.free	= xe_ttm_vram_mgr_del,</div><div class='add'>+	.intersects = xe_ttm_vram_mgr_intersects,</div><div class='add'>+	.compatible = xe_ttm_vram_mgr_compatible,</div><div class='add'>+	.debug	= xe_ttm_vram_mgr_debug</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void ttm_vram_mgr_fini(struct drm_device *dev, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = arg;</div><div class='add'>+	struct ttm_resource_manager *man = &amp;mgr-&gt;manager;</div><div class='add'>+</div><div class='add'>+	ttm_resource_manager_set_used(man, false);</div><div class='add'>+</div><div class='add'>+	if (ttm_resource_manager_evict_all(&amp;xe-&gt;ttm, man))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(mgr-&gt;visible_avail != mgr-&gt;visible_size);</div><div class='add'>+</div><div class='add'>+	drm_buddy_fini(&amp;mgr-&gt;mm);</div><div class='add'>+</div><div class='add'>+	ttm_resource_manager_cleanup(&amp;mgr-&gt;manager);</div><div class='add'>+</div><div class='add'>+	ttm_set_driver_manager(&amp;xe-&gt;ttm, mgr-&gt;mem_type, NULL);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;mgr-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,</div><div class='add'>+			   u32 mem_type, u64 size, u64 io_size,</div><div class='add'>+			   u64 default_page_size)</div><div class='add'>+{</div><div class='add'>+	struct ttm_resource_manager *man = &amp;mgr-&gt;manager;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	man-&gt;func = &amp;xe_ttm_vram_mgr_func;</div><div class='add'>+	mgr-&gt;mem_type = mem_type;</div><div class='add'>+	mutex_init(&amp;mgr-&gt;lock);</div><div class='add'>+	mgr-&gt;default_page_size = default_page_size;</div><div class='add'>+	mgr-&gt;visible_size = io_size;</div><div class='add'>+	mgr-&gt;visible_avail = io_size;</div><div class='add'>+</div><div class='add'>+	ttm_resource_manager_init(man, &amp;xe-&gt;ttm, size);</div><div class='add'>+	err = drm_buddy_init(&amp;mgr-&gt;mm, man-&gt;size, default_page_size);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	ttm_set_driver_manager(&amp;xe-&gt;ttm, mem_type, &amp;mgr-&gt;manager);</div><div class='add'>+	ttm_resource_manager_set_used(&amp;mgr-&gt;manager, true);</div><div class='add'>+</div><div class='add'>+	return drmm_add_action_or_reset(&amp;xe-&gt;drm, ttm_vram_mgr_fini, mgr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = tile_to_xe(tile);</div><div class='add'>+	struct xe_mem_region *vram = &amp;tile-&gt;mem.vram;</div><div class='add'>+</div><div class='add'>+	mgr-&gt;vram = vram;</div><div class='add'>+	return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + tile-&gt;id,</div><div class='add'>+				      vram-&gt;usable_size, vram-&gt;io_size,</div><div class='add'>+				      PAGE_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,</div><div class='add'>+			      struct ttm_resource *res,</div><div class='add'>+			      u64 offset, u64 length,</div><div class='add'>+			      struct device *dev,</div><div class='add'>+			      enum dma_data_direction dir,</div><div class='add'>+			      struct sg_table **sgt)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile = &amp;xe-&gt;tiles[res-&gt;mem_type - XE_PL_VRAM0];</div><div class='add'>+	struct xe_ttm_vram_mgr_resource *vres = to_xe_ttm_vram_mgr_resource(res);</div><div class='add'>+	struct xe_res_cursor cursor;</div><div class='add'>+	struct scatterlist *sg;</div><div class='add'>+	int num_entries = 0;</div><div class='add'>+	int i, r;</div><div class='add'>+</div><div class='add'>+	if (vres-&gt;used_visible_size &lt; res-&gt;size)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	*sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);</div><div class='add'>+	if (!*sgt)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Determine the number of DRM_BUDDY blocks to export */</div><div class='add'>+	xe_res_first(res, offset, length, &amp;cursor);</div><div class='add'>+	while (cursor.remaining) {</div><div class='add'>+		num_entries++;</div><div class='add'>+		xe_res_next(&amp;cursor, cursor.size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	r = sg_alloc_table(*sgt, num_entries, GFP_KERNEL);</div><div class='add'>+	if (r)</div><div class='add'>+		goto error_free;</div><div class='add'>+</div><div class='add'>+	/* Initialize scatterlist nodes of sg_table */</div><div class='add'>+	for_each_sgtable_sg((*sgt), sg, i)</div><div class='add'>+		sg-&gt;length = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Walk down DRM_BUDDY blocks to populate scatterlist nodes</div><div class='add'>+	 * @note: Use iterator api to get first the DRM_BUDDY block</div><div class='add'>+	 * and the number of bytes from it. Access the following</div><div class='add'>+	 * DRM_BUDDY block(s) if more buffer needs to exported</div><div class='add'>+	 */</div><div class='add'>+	xe_res_first(res, offset, length, &amp;cursor);</div><div class='add'>+	for_each_sgtable_sg((*sgt), sg, i) {</div><div class='add'>+		phys_addr_t phys = cursor.start + tile-&gt;mem.vram.io_start;</div><div class='add'>+		size_t size = cursor.size;</div><div class='add'>+		dma_addr_t addr;</div><div class='add'>+</div><div class='add'>+		addr = dma_map_resource(dev, phys, size, dir,</div><div class='add'>+					DMA_ATTR_SKIP_CPU_SYNC);</div><div class='add'>+		r = dma_mapping_error(dev, addr);</div><div class='add'>+		if (r)</div><div class='add'>+			goto error_unmap;</div><div class='add'>+</div><div class='add'>+		sg_set_page(sg, NULL, size, 0);</div><div class='add'>+		sg_dma_address(sg) = addr;</div><div class='add'>+		sg_dma_len(sg) = size;</div><div class='add'>+</div><div class='add'>+		xe_res_next(&amp;cursor, cursor.size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_unmap:</div><div class='add'>+	for_each_sgtable_sg((*sgt), sg, i) {</div><div class='add'>+		if (!sg-&gt;length)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		dma_unmap_resource(dev, sg-&gt;dma_address,</div><div class='add'>+				   sg-&gt;length, dir,</div><div class='add'>+				   DMA_ATTR_SKIP_CPU_SYNC);</div><div class='add'>+	}</div><div class='add'>+	sg_free_table(*sgt);</div><div class='add'>+</div><div class='add'>+error_free:</div><div class='add'>+	kfree(*sgt);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ttm_vram_mgr_free_sgt(struct device *dev, enum dma_data_direction dir,</div><div class='add'>+			      struct sg_table *sgt)</div><div class='add'>+{</div><div class='add'>+	struct scatterlist *sg;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for_each_sgtable_sg(sgt, sg, i)</div><div class='add'>+		dma_unmap_resource(dev, sg-&gt;dma_address,</div><div class='add'>+				   sg-&gt;length, dir,</div><div class='add'>+				   DMA_ATTR_SKIP_CPU_SYNC);</div><div class='add'>+	sg_free_table(sgt);</div><div class='add'>+	kfree(sgt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_ttm_vram_get_cpu_visible_size(struct ttm_resource_manager *man)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+</div><div class='add'>+	return mgr-&gt;visible_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_ttm_vram_get_used(struct ttm_resource_manager *man,</div><div class='add'>+			  u64 *used, u64 *used_visible)</div><div class='add'>+{</div><div class='add'>+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mgr-&gt;lock);</div><div class='add'>+	*used = mgr-&gt;mm.size - mgr-&gt;mm.avail;</div><div class='add'>+	*used_visible = mgr-&gt;visible_size - mgr-&gt;visible_avail;</div><div class='add'>+	mutex_unlock(&amp;mgr-&gt;lock);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h<br/>new file mode 100644<br/>index 000000000000..d184e19a9230<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr.h</a></div><div class='hunk'>@@ -0,0 +1,44 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TTM_VRAM_MGR_H_</div><div class='add'>+#define _XE_TTM_VRAM_MGR_H_</div><div class='add'>+</div><div class='add'>+#include "xe_ttm_vram_mgr_types.h"</div><div class='add'>+</div><div class='add'>+enum dma_data_direction;</div><div class='add'>+struct xe_device;</div><div class='add'>+struct xe_tile;</div><div class='add'>+</div><div class='add'>+int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,</div><div class='add'>+			   u32 mem_type, u64 size, u64 io_size,</div><div class='add'>+			   u64 default_page_size);</div><div class='add'>+int xe_ttm_vram_mgr_init(struct xe_tile *tile, struct xe_ttm_vram_mgr *mgr);</div><div class='add'>+int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,</div><div class='add'>+			      struct ttm_resource *res,</div><div class='add'>+			      u64 offset, u64 length,</div><div class='add'>+			      struct device *dev,</div><div class='add'>+			      enum dma_data_direction dir,</div><div class='add'>+			      struct sg_table **sgt);</div><div class='add'>+void xe_ttm_vram_mgr_free_sgt(struct device *dev, enum dma_data_direction dir,</div><div class='add'>+			      struct sg_table *sgt);</div><div class='add'>+</div><div class='add'>+u64 xe_ttm_vram_get_cpu_visible_size(struct ttm_resource_manager *man);</div><div class='add'>+void xe_ttm_vram_get_used(struct ttm_resource_manager *man,</div><div class='add'>+			  u64 *used, u64 *used_visible);</div><div class='add'>+</div><div class='add'>+static inline struct xe_ttm_vram_mgr_resource *</div><div class='add'>+to_xe_ttm_vram_mgr_resource(struct ttm_resource *res)</div><div class='add'>+{</div><div class='add'>+	return container_of(res, struct xe_ttm_vram_mgr_resource, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_ttm_vram_mgr *</div><div class='add'>+to_xe_ttm_vram_mgr(struct ttm_resource_manager *man)</div><div class='add'>+{</div><div class='add'>+	return container_of(man, struct xe_ttm_vram_mgr, manager);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h<br/>new file mode 100644<br/>index 000000000000..2d75cf126289<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TTM_VRAM_MGR_TYPES_H_</div><div class='add'>+#define _XE_TTM_VRAM_MGR_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_buddy.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_device.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_mem_region;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_ttm_vram_mgr - XE TTM VRAM manager</div><div class='add'>+ *</div><div class='add'>+ * Manages placement of TTM resource in VRAM.</div><div class='add'>+ */</div><div class='add'>+struct xe_ttm_vram_mgr {</div><div class='add'>+	/** @manager: Base TTM resource manager */</div><div class='add'>+	struct ttm_resource_manager manager;</div><div class='add'>+	/** @mm: DRM buddy allocator which manages the VRAM */</div><div class='add'>+	struct drm_buddy mm;</div><div class='add'>+	/** @vram: ptr to details of associated VRAM region */</div><div class='add'>+	struct xe_mem_region *vram;</div><div class='add'>+	/** @visible_size: Proped size of the CPU visible portion */</div><div class='add'>+	u64 visible_size;</div><div class='add'>+	/** @visible_avail: CPU visible portion still unallocated */</div><div class='add'>+	u64 visible_avail;</div><div class='add'>+	/** @default_page_size: default page size */</div><div class='add'>+	u64 default_page_size;</div><div class='add'>+	/** @lock: protects allocations of VRAM */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	/** @mem_type: The TTM memory type */</div><div class='add'>+	u32 mem_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_ttm_vram_mgr_resource - XE TTM VRAM resource</div><div class='add'>+ */</div><div class='add'>+struct xe_ttm_vram_mgr_resource {</div><div class='add'>+	/** @base: Base TTM resource */</div><div class='add'>+	struct ttm_resource base;</div><div class='add'>+	/** @blocks: list of DRM buddy blocks */</div><div class='add'>+	struct list_head blocks;</div><div class='add'>+	/** @used_visible_size: How many CPU visible bytes this resource is using */</div><div class='add'>+	u64 used_visible_size;</div><div class='add'>+	/** @flags: flags associated with the resource */</div><div class='add'>+	unsigned long flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c<br/>new file mode 100644<br/>index 000000000000..53ccd338fd8c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tuning.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tuning.c</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_tuning.h"</div><div class='add'>+</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "xe_gt_types.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+</div><div class='add'>+#undef XE_REG_MCR</div><div class='add'>+#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr gt_tunings[] = {</div><div class='add'>+	{ XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("Tuning: 32B Access Enable"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe2 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("Tuning: L3 cache"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,</div><div class='add'>+				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("Tuning: L3 cache - media"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(2000)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,</div><div class='add'>+				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr engine_tunings[] = {</div><div class='add'>+	{ XE_RTP_NAME("Tuning: Set Indirect State Override"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1271),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))</div><div class='add'>+	},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr lrc_tunings[] = {</div><div class='add'>+	{ XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  /* read verification is ignored due to 1608008084. */</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(FF_MODE2,</div><div class='add'>+						FF_MODE2_GS_TIMER_MASK,</div><div class='add'>+						FF_MODE2_GS_TIMER_224))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG2 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("Tuning: L3 cache"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,</div><div class='add'>+				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("Tuning: TDS gang timer"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  /* read verification is ignored as in i915 - need to check enabling */</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,</div><div class='add'>+						FF_MODE2_TDS_TIMER_MASK,</div><div class='add'>+						FF_MODE2_TDS_TIMER_128))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("Tuning: TBIMR fast clip"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("Tuning: L3 cache"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,</div><div class='add'>+				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void xe_tuning_process_gt(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, gt_tunings, &amp;gt-&gt;reg_sr);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_gt);</div><div class='add'>+</div><div class='add'>+void xe_tuning_process_engine(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, engine_tunings, &amp;hwe-&gt;reg_sr);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_tuning_process_engine);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_tuning_process_lrc - process lrc tunings</div><div class='add'>+ * @hwe: engine instance to process tunings for</div><div class='add'>+ *</div><div class='add'>+ * Process LRC table for this platform, saving in @hwe all the tunings that need</div><div class='add'>+ * to be applied on context restore. These are tunings touching registers that</div><div class='add'>+ * are part of the HW context image.</div><div class='add'>+ */</div><div class='add'>+void xe_tuning_process_lrc(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, lrc_tunings, &amp;hwe-&gt;reg_lrc);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_tuning.h b/drivers/gpu/drm/xe/xe_tuning.h<br/>new file mode 100644<br/>index 000000000000..4f9c3ac3b516<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_tuning.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_tuning.h</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_TUNING_</div><div class='add'>+#define _XE_TUNING_</div><div class='add'>+</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+</div><div class='add'>+void xe_tuning_process_gt(struct xe_gt *gt);</div><div class='add'>+void xe_tuning_process_engine(struct xe_hw_engine *hwe);</div><div class='add'>+void xe_tuning_process_lrc(struct xe_hw_engine *hwe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c<br/>new file mode 100644<br/>index 000000000000..25e1ddfd2f86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc.c</a></div><div class='hunk'>@@ -0,0 +1,258 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_uc.h"</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gsc.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc.h"</div><div class='add'>+#include "xe_guc_pc.h"</div><div class='add'>+#include "xe_guc_submit.h"</div><div class='add'>+#include "xe_huc.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+#include "xe_wopcm.h"</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+uc_to_gt(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	return container_of(uc, struct xe_gt, uc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *</div><div class='add'>+uc_to_xe(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(uc_to_gt(uc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Should be called once at driver load only */</div><div class='add'>+int xe_uc_init(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We call the GuC/HuC/GSC init functions even if GuC submission is off</div><div class='add'>+	 * to correctly move our tracking of the FW state to "disabled".</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_init(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = xe_huc_init(&amp;uc-&gt;huc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = xe_gsc_init(&amp;uc-&gt;gsc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = xe_wopcm_init(&amp;uc-&gt;wopcm);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_submit_init(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_uc_init_post_hwconfig - init Uc post hwconfig load</div><div class='add'>+ * @uc: The UC object</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_uc_init_post_hwconfig(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = xe_uc_sanitize_reset(uc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = xe_guc_init_post_hwconfig(&amp;uc-&gt;guc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return xe_gsc_init_post_hwconfig(&amp;uc-&gt;gsc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int uc_reset(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_to_xe(uc);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_reset(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "Failed to reset GuC, ret = %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_uc_sanitize(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	xe_huc_sanitize(&amp;uc-&gt;huc);</div><div class='add'>+	xe_guc_sanitize(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_sanitize_reset(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	xe_uc_sanitize(uc);</div><div class='add'>+</div><div class='add'>+	return uc_reset(uc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_uc_init_hwconfig - minimally init Uc, read and parse hwconfig</div><div class='add'>+ * @uc: The UC object</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+int xe_uc_init_hwconfig(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_min_load_for_hwconfig(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Should be called during driver load, after every GT reset, and after every</div><div class='add'>+ * suspend to reload / auth the firmwares.</div><div class='add'>+ */</div><div class='add'>+int xe_uc_init_hw(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = xe_huc_upload(&amp;uc-&gt;huc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_upload(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_enable_communication(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_gt_record_default_lrcs(uc_to_gt(uc));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_post_load_init(&amp;uc-&gt;guc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = xe_guc_pc_start(&amp;uc-&gt;guc.pc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* We don't fail the driver load if HuC fails to auth, but let's warn */</div><div class='add'>+	ret = xe_huc_auth(&amp;uc-&gt;huc, XE_HUC_AUTH_VIA_GUC);</div><div class='add'>+	xe_gt_assert(uc_to_gt(uc), !ret);</div><div class='add'>+</div><div class='add'>+	/* GSC load is async */</div><div class='add'>+	xe_gsc_load_start(&amp;uc-&gt;gsc);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_fini_hw(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	return xe_uc_sanitize_reset(uc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_reset_prepare(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return xe_guc_reset_prepare(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_uc_gucrc_disable(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(xe_guc_pc_gucrc_disable(&amp;uc-&gt;guc.pc));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_uc_stop_prepare(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	xe_gsc_wait_for_worker_completion(&amp;uc-&gt;gsc);</div><div class='add'>+	xe_guc_stop_prepare(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_stop(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return xe_guc_stop(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_start(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return xe_guc_start(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void uc_reset_wait(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+again:</div><div class='add'>+	xe_guc_reset_wait(&amp;uc-&gt;guc);</div><div class='add'>+</div><div class='add'>+	ret = xe_uc_reset_prepare(uc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto again;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_suspend(struct xe_uc *uc)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* GuC submission not enabled, nothing to do */</div><div class='add'>+	if (!xe_device_uc_enabled(uc_to_xe(uc)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	uc_reset_wait(uc);</div><div class='add'>+</div><div class='add'>+	ret = xe_uc_stop(uc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return xe_guc_suspend(&amp;uc-&gt;guc);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc.h b/drivers/gpu/drm/xe/xe_uc.h<br/>new file mode 100644<br/>index 000000000000..5d5110c0c834<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc.h</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_H_</div><div class='add'>+#define _XE_UC_H_</div><div class='add'>+</div><div class='add'>+#include "xe_uc_types.h"</div><div class='add'>+</div><div class='add'>+int xe_uc_init(struct xe_uc *uc);</div><div class='add'>+int xe_uc_init_hwconfig(struct xe_uc *uc);</div><div class='add'>+int xe_uc_init_post_hwconfig(struct xe_uc *uc);</div><div class='add'>+int xe_uc_init_hw(struct xe_uc *uc);</div><div class='add'>+int xe_uc_fini_hw(struct xe_uc *uc);</div><div class='add'>+void xe_uc_gucrc_disable(struct xe_uc *uc);</div><div class='add'>+int xe_uc_reset_prepare(struct xe_uc *uc);</div><div class='add'>+void xe_uc_stop_prepare(struct xe_uc *uc);</div><div class='add'>+int xe_uc_stop(struct xe_uc *uc);</div><div class='add'>+int xe_uc_start(struct xe_uc *uc);</div><div class='add'>+int xe_uc_suspend(struct xe_uc *uc);</div><div class='add'>+int xe_uc_sanitize_reset(struct xe_uc *uc);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_debugfs.c b/drivers/gpu/drm/xe/xe_uc_debugfs.c<br/>new file mode 100644<br/>index 000000000000..0a39ec5a6e99<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_debugfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_guc_debugfs.h"</div><div class='add'>+#include "xe_huc_debugfs.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_uc_debugfs.h"</div><div class='add'>+</div><div class='add'>+void xe_uc_debugfs_register(struct xe_uc *uc, struct dentry *parent)</div><div class='add'>+{</div><div class='add'>+	struct dentry *root;</div><div class='add'>+</div><div class='add'>+	root = debugfs_create_dir("uc", parent);</div><div class='add'>+	if (IS_ERR(root)) {</div><div class='add'>+		XE_WARN_ON("Create UC directory failed");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_guc_debugfs_register(&amp;uc-&gt;guc, root);</div><div class='add'>+	xe_huc_debugfs_register(&amp;uc-&gt;huc, root);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_debugfs.h b/drivers/gpu/drm/xe/xe_uc_debugfs.h<br/>new file mode 100644<br/>index 000000000000..a13382df2bd7<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,14 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_DEBUGFS_H_</div><div class='add'>+#define _XE_UC_DEBUGFS_H_</div><div class='add'>+</div><div class='add'>+struct dentry;</div><div class='add'>+struct xe_uc;</div><div class='add'>+</div><div class='add'>+void xe_uc_debugfs_register(struct xe_uc *uc, struct dentry *parent);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c<br/>new file mode 100644<br/>index 000000000000..9dff96dfe455<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw.c</a></div><div class='hunk'>@@ -0,0 +1,882 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+</div><div class='add'>+#include "regs/xe_guc_regs.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gsc.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_module.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * List of required GuC and HuC binaries per-platform. They must be ordered</div><div class='add'>+ * based on platform, from newer to older.</div><div class='add'>+ *</div><div class='add'>+ * Versioning follows the guidelines from</div><div class='add'>+ * Documentation/driver-api/firmware/firmware-usage-guidelines.rst. There is a</div><div class='add'>+ * distinction for platforms being officially supported by the driver or not.</div><div class='add'>+ * Platforms not available publicly or not yet officially supported by the</div><div class='add'>+ * driver (under force-probe), use the mmp_ver(): the firmware autoselect logic</div><div class='add'>+ * will select the firmware from disk with filename that matches the full</div><div class='add'>+ * "mpp version", i.e. major.minor.patch. mmp_ver() should only be used for</div><div class='add'>+ * this case.</div><div class='add'>+ *</div><div class='add'>+ * For platforms officially supported by the driver, the filename always only</div><div class='add'>+ * ever contains the major version (GuC) or no version at all (HuC).</div><div class='add'>+ *</div><div class='add'>+ * After loading the file, the driver parses the versions embedded in the blob.</div><div class='add'>+ * The major version needs to match a major version supported by the driver (if</div><div class='add'>+ * any). The minor version is also checked and a notice emitted to the log if</div><div class='add'>+ * the version found is smaller than the version wanted. This is done only for</div><div class='add'>+ * informational purposes so users may have a chance to upgrade, but the driver</div><div class='add'>+ * still loads and use the older firmware.</div><div class='add'>+ *</div><div class='add'>+ * Examples:</div><div class='add'>+ *</div><div class='add'>+ *	1) Platform officially supported by i915 - using Tigerlake as example.</div><div class='add'>+ *	   Driver loads the following firmware blobs from disk:</div><div class='add'>+ *</div><div class='add'>+ *		- i915/tgl_guc_&lt;major&gt;.bin</div><div class='add'>+ *		- i915/tgl_huc.bin</div><div class='add'>+ *</div><div class='add'>+ *	   &lt;major&gt; number for GuC is checked that it matches the version inside</div><div class='add'>+ *	   the blob. &lt;minor&gt; version is checked and if smaller than the expected</div><div class='add'>+ *	   an info message is emitted about that.</div><div class='add'>+ *</div><div class='add'>+ *	1) XE_&lt;FUTUREINTELPLATFORM&gt;, still under require_force_probe. Using</div><div class='add'>+ *	   "wipplat" as a short-name. Driver loads the following firmware blobs</div><div class='add'>+ *	   from disk:</div><div class='add'>+ *</div><div class='add'>+ *		- xe/wipplat_guc_&lt;major&gt;.&lt;minor&gt;.&lt;patch&gt;.bin</div><div class='add'>+ *		- xe/wipplat_huc_&lt;major&gt;.&lt;minor&gt;.&lt;patch&gt;.bin</div><div class='add'>+ *</div><div class='add'>+ *	   &lt;major&gt; and &lt;minor&gt; are checked that they match the version inside</div><div class='add'>+ *	   the blob. Both of them need to match exactly what the driver is</div><div class='add'>+ *	   expecting, otherwise it fails.</div><div class='add'>+ *</div><div class='add'>+ *	3) Platform officially supported by xe and out of force-probe. Using</div><div class='add'>+ *	   "plat" as a short-name. Except for the different directory, the</div><div class='add'>+ *	   behavior is the same as (1). Driver loads the following firmware</div><div class='add'>+ *	   blobs from disk:</div><div class='add'>+ *</div><div class='add'>+ *		- xe/plat_guc_&lt;major&gt;.bin</div><div class='add'>+ *		- xe/plat_huc.bin</div><div class='add'>+ *</div><div class='add'>+ *	   &lt;major&gt; number for GuC is checked that it matches the version inside</div><div class='add'>+ *	   the blob. &lt;minor&gt; version is checked and if smaller than the expected</div><div class='add'>+ *	   an info message is emitted about that.</div><div class='add'>+ *</div><div class='add'>+ * For the platforms already released with a major version, they should never be</div><div class='add'>+ * removed from the table. Instead new entries with newer versions may be added</div><div class='add'>+ * before them, so they take precedence.</div><div class='add'>+ *</div><div class='add'>+ * TODO: Currently there's no fallback on major version. That's because xe</div><div class='add'>+ * driver only supports the one major version of each firmware in the table.</div><div class='add'>+ * This needs to be fixed when the major version of GuC is updated.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct uc_fw_entry {</div><div class='add'>+	enum xe_platform platform;</div><div class='add'>+	struct {</div><div class='add'>+		const char *path;</div><div class='add'>+		u16 major;</div><div class='add'>+		u16 minor;</div><div class='add'>+		bool full_ver_required;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct fw_blobs_by_type {</div><div class='add'>+	const struct uc_fw_entry *entries;</div><div class='add'>+	u32 count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver)			\</div><div class='add'>+	fw_def(METEORLAKE,	major_ver(i915,	guc,	mtl,	70, 7))		\</div><div class='add'>+	fw_def(DG2,		major_ver(i915,	guc,	dg2,	70, 5))		\</div><div class='add'>+	fw_def(DG1,		major_ver(i915,	guc,	dg1,	70, 5))		\</div><div class='add'>+	fw_def(ALDERLAKE_N,	major_ver(i915,	guc,	tgl,	70, 5))		\</div><div class='add'>+	fw_def(ALDERLAKE_P,	major_ver(i915,	guc,	adlp,	70, 5))		\</div><div class='add'>+	fw_def(ALDERLAKE_S,	major_ver(i915,	guc,	tgl,	70, 5))		\</div><div class='add'>+	fw_def(ROCKETLAKE,	major_ver(i915,	guc,	tgl,	70, 5))		\</div><div class='add'>+	fw_def(TIGERLAKE,	major_ver(i915,	guc,	tgl,	70, 5))</div><div class='add'>+</div><div class='add'>+#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver)		\</div><div class='add'>+	fw_def(METEORLAKE,	no_ver(i915,	huc_gsc,	mtl))		\</div><div class='add'>+	fw_def(DG1,		no_ver(i915,	huc,		dg1))		\</div><div class='add'>+	fw_def(ALDERLAKE_P,	no_ver(i915,	huc,		tgl))		\</div><div class='add'>+	fw_def(ALDERLAKE_S,	no_ver(i915,	huc,		tgl))		\</div><div class='add'>+	fw_def(ROCKETLAKE,	no_ver(i915,	huc,		tgl))		\</div><div class='add'>+	fw_def(TIGERLAKE,	no_ver(i915,	huc,		tgl))</div><div class='add'>+</div><div class='add'>+/* for the GSC FW we match the compatibility version and not the release one */</div><div class='add'>+#define XE_GSC_FIRMWARE_DEFS(fw_def, major_ver)		\</div><div class='add'>+	fw_def(METEORLAKE,	major_ver(i915,	gsc,	mtl,	1, 0))</div><div class='add'>+</div><div class='add'>+#define MAKE_FW_PATH(dir__, uc__, shortname__, version__)			\</div><div class='add'>+	__stringify(dir__) "/" __stringify(shortname__) "_" __stringify(uc__) version__ ".bin"</div><div class='add'>+</div><div class='add'>+#define fw_filename_mmp_ver(dir_, uc_, shortname_, a, b, c)			\</div><div class='add'>+	MAKE_FW_PATH(dir_, uc_, shortname_, "_" __stringify(a ## . ## b ## . ## c))</div><div class='add'>+#define fw_filename_major_ver(dir_, uc_, shortname_, a, b)			\</div><div class='add'>+	MAKE_FW_PATH(dir_, uc_, shortname_, "_" __stringify(a))</div><div class='add'>+#define fw_filename_no_ver(dir_, uc_, shortname_)				\</div><div class='add'>+	MAKE_FW_PATH(dir_, uc_, shortname_, "")</div><div class='add'>+</div><div class='add'>+#define uc_fw_entry_mmp_ver(dir_, uc_, shortname_, a, b, c)			\</div><div class='add'>+	{ fw_filename_mmp_ver(dir_, uc_, shortname_, a, b, c),			\</div><div class='add'>+	  a, b, true }</div><div class='add'>+#define uc_fw_entry_major_ver(dir_, uc_, shortname_, a, b)			\</div><div class='add'>+	{ fw_filename_major_ver(dir_, uc_, shortname_, a, b),			\</div><div class='add'>+	  a, b }</div><div class='add'>+#define uc_fw_entry_no_ver(dir_, uc_, shortname_)				\</div><div class='add'>+	{ fw_filename_no_ver(dir_, uc_, shortname_),				\</div><div class='add'>+	  0, 0 }</div><div class='add'>+</div><div class='add'>+/* All blobs need to be declared via MODULE_FIRMWARE() */</div><div class='add'>+#define XE_UC_MODULE_FIRMWARE(platform__, fw_filename)				\</div><div class='add'>+	MODULE_FIRMWARE(fw_filename);</div><div class='add'>+</div><div class='add'>+#define XE_UC_FW_ENTRY(platform__, entry__)					\</div><div class='add'>+	{									\</div><div class='add'>+		.platform = XE_ ## platform__,					\</div><div class='add'>+		entry__,							\</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+XE_GUC_FIRMWARE_DEFS(XE_UC_MODULE_FIRMWARE,</div><div class='add'>+		     fw_filename_mmp_ver, fw_filename_major_ver)</div><div class='add'>+XE_HUC_FIRMWARE_DEFS(XE_UC_MODULE_FIRMWARE,</div><div class='add'>+		     fw_filename_mmp_ver, fw_filename_no_ver)</div><div class='add'>+XE_GSC_FIRMWARE_DEFS(XE_UC_MODULE_FIRMWARE, fw_filename_major_ver)</div><div class='add'>+</div><div class='add'>+static struct xe_gt *</div><div class='add'>+__uc_fw_to_gt(struct xe_uc_fw *uc_fw, enum xe_uc_fw_type type)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(type &gt;= XE_UC_FW_NUM_TYPES);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case XE_UC_FW_TYPE_GUC:</div><div class='add'>+		return container_of(uc_fw, struct xe_gt, uc.guc.fw);</div><div class='add'>+	case XE_UC_FW_TYPE_HUC:</div><div class='add'>+		return container_of(uc_fw, struct xe_gt, uc.huc.fw);</div><div class='add'>+	case XE_UC_FW_TYPE_GSC:</div><div class='add'>+		return container_of(uc_fw, struct xe_gt, uc.gsc.fw);</div><div class='add'>+	default:</div><div class='add'>+		return NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_gt *uc_fw_to_gt(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __uc_fw_to_gt(uc_fw, uc_fw-&gt;type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(uc_fw_to_gt(uc_fw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+uc_fw_auto_select(struct xe_device *xe, struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	static const struct uc_fw_entry entries_guc[] = {</div><div class='add'>+		XE_GUC_FIRMWARE_DEFS(XE_UC_FW_ENTRY,</div><div class='add'>+				     uc_fw_entry_mmp_ver,</div><div class='add'>+				     uc_fw_entry_major_ver)</div><div class='add'>+	};</div><div class='add'>+	static const struct uc_fw_entry entries_huc[] = {</div><div class='add'>+		XE_HUC_FIRMWARE_DEFS(XE_UC_FW_ENTRY,</div><div class='add'>+				     uc_fw_entry_mmp_ver,</div><div class='add'>+				     uc_fw_entry_no_ver)</div><div class='add'>+	};</div><div class='add'>+	static const struct uc_fw_entry entries_gsc[] = {</div><div class='add'>+		XE_GSC_FIRMWARE_DEFS(XE_UC_FW_ENTRY, uc_fw_entry_major_ver)</div><div class='add'>+	};</div><div class='add'>+	static const struct fw_blobs_by_type blobs_all[XE_UC_FW_NUM_TYPES] = {</div><div class='add'>+		[XE_UC_FW_TYPE_GUC] = { entries_guc, ARRAY_SIZE(entries_guc) },</div><div class='add'>+		[XE_UC_FW_TYPE_HUC] = { entries_huc, ARRAY_SIZE(entries_huc) },</div><div class='add'>+		[XE_UC_FW_TYPE_GSC] = { entries_gsc, ARRAY_SIZE(entries_gsc) },</div><div class='add'>+	};</div><div class='add'>+	static const struct uc_fw_entry *entries;</div><div class='add'>+	enum xe_platform p = xe-&gt;info.platform;</div><div class='add'>+	u32 count;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, uc_fw-&gt;type &lt; ARRAY_SIZE(blobs_all));</div><div class='add'>+	entries = blobs_all[uc_fw-&gt;type].entries;</div><div class='add'>+	count = blobs_all[uc_fw-&gt;type].count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count &amp;&amp; p &lt;= entries[i].platform; i++) {</div><div class='add'>+		if (p == entries[i].platform) {</div><div class='add'>+			uc_fw-&gt;path = entries[i].path;</div><div class='add'>+			uc_fw-&gt;versions.wanted.major = entries[i].major;</div><div class='add'>+			uc_fw-&gt;versions.wanted.minor = entries[i].minor;</div><div class='add'>+			uc_fw-&gt;full_ver_required = entries[i].full_ver_required;</div><div class='add'>+</div><div class='add'>+			if (uc_fw-&gt;type == XE_UC_FW_TYPE_GSC)</div><div class='add'>+				uc_fw-&gt;versions.wanted_type = XE_UC_FW_VER_COMPATIBILITY;</div><div class='add'>+			else</div><div class='add'>+				uc_fw-&gt;versions.wanted_type = XE_UC_FW_VER_RELEASE;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+uc_fw_override(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	char *path_override = NULL;</div><div class='add'>+</div><div class='add'>+	/* empty string disables, but it's not allowed for GuC */</div><div class='add'>+	switch (uc_fw-&gt;type) {</div><div class='add'>+	case XE_UC_FW_TYPE_GUC:</div><div class='add'>+		if (xe_modparam.guc_firmware_path &amp;&amp; *xe_modparam.guc_firmware_path)</div><div class='add'>+			path_override = xe_modparam.guc_firmware_path;</div><div class='add'>+		break;</div><div class='add'>+	case XE_UC_FW_TYPE_HUC:</div><div class='add'>+		path_override = xe_modparam.huc_firmware_path;</div><div class='add'>+		break;</div><div class='add'>+	case XE_UC_FW_TYPE_GSC:</div><div class='add'>+		path_override = xe_modparam.gsc_firmware_path;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (path_override) {</div><div class='add'>+		uc_fw-&gt;path = path_override;</div><div class='add'>+		uc_fw-&gt;user_overridden = true;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_uc_fw_copy_rsa - copy fw RSA to buffer</div><div class='add'>+ *</div><div class='add'>+ * @uc_fw: uC firmware</div><div class='add'>+ * @dst: dst buffer</div><div class='add'>+ * @max_len: max number of bytes to copy</div><div class='add'>+ *</div><div class='add'>+ * Return: number of copied bytes.</div><div class='add'>+ */</div><div class='add'>+size_t xe_uc_fw_copy_rsa(struct xe_uc_fw *uc_fw, void *dst, u32 max_len)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	u32 size = min_t(u32, uc_fw-&gt;rsa_size, max_len);</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !(size % 4));</div><div class='add'>+	xe_assert(xe, xe_uc_fw_is_available(uc_fw));</div><div class='add'>+</div><div class='add'>+	xe_map_memcpy_from(xe, dst, &amp;uc_fw-&gt;bo-&gt;vmap,</div><div class='add'>+			   xe_uc_fw_rsa_offset(uc_fw), size);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void uc_fw_fini(struct drm_device *drm, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct xe_uc_fw *uc_fw = arg;</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_available(uc_fw))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_SELECTED);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);</div><div class='add'>+	struct xe_uc_fw_version *release = &amp;uc_fw-&gt;versions.found[XE_UC_FW_VER_RELEASE];</div><div class='add'>+	struct xe_uc_fw_version *compatibility = &amp;uc_fw-&gt;versions.found[XE_UC_FW_VER_COMPATIBILITY];</div><div class='add'>+</div><div class='add'>+	xe_gt_assert(gt, uc_fw-&gt;type == XE_UC_FW_TYPE_GUC);</div><div class='add'>+	xe_gt_assert(gt, release-&gt;major &gt;= 70);</div><div class='add'>+</div><div class='add'>+	if (release-&gt;major &gt; 70 || release-&gt;minor &gt;= 6) {</div><div class='add'>+		/* v70.6.0 adds CSS header support */</div><div class='add'>+		compatibility-&gt;major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR,</div><div class='add'>+						 css-&gt;submission_version);</div><div class='add'>+		compatibility-&gt;minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR,</div><div class='add'>+						 css-&gt;submission_version);</div><div class='add'>+		compatibility-&gt;patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH,</div><div class='add'>+						 css-&gt;submission_version);</div><div class='add'>+	} else if (release-&gt;minor &gt;= 3) {</div><div class='add'>+		/* v70.3.0 introduced v1.1.0 */</div><div class='add'>+		compatibility-&gt;major = 1;</div><div class='add'>+		compatibility-&gt;minor = 1;</div><div class='add'>+		compatibility-&gt;patch = 0;</div><div class='add'>+	} else {</div><div class='add'>+		/* v70.0.0 introduced v1.0.0 */</div><div class='add'>+		compatibility-&gt;major = 1;</div><div class='add'>+		compatibility-&gt;minor = 0;</div><div class='add'>+		compatibility-&gt;patch = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	uc_fw-&gt;private_data_size = css-&gt;private_data_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_fw_check_version_requirements(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	struct xe_uc_fw_version *wanted = &amp;uc_fw-&gt;versions.wanted;</div><div class='add'>+	struct xe_uc_fw_version *found = &amp;uc_fw-&gt;versions.found[uc_fw-&gt;versions.wanted_type];</div><div class='add'>+</div><div class='add'>+	/* Driver has no requirement on any version, any is good. */</div><div class='add'>+	if (!wanted-&gt;major)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If full version is required, both major and minor should match.</div><div class='add'>+	 * Otherwise, at least the major version.</div><div class='add'>+	 */</div><div class='add'>+	if (wanted-&gt;major != found-&gt;major ||</div><div class='add'>+	    (uc_fw-&gt;full_ver_required &amp;&amp; wanted-&gt;minor != found-&gt;minor)) {</div><div class='add'>+		drm_notice(&amp;xe-&gt;drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",</div><div class='add'>+			   xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path,</div><div class='add'>+			   found-&gt;major, found-&gt;minor,</div><div class='add'>+			   wanted-&gt;major, wanted-&gt;minor);</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (wanted-&gt;minor &gt; found-&gt;minor) {</div><div class='add'>+		drm_notice(&amp;xe-&gt;drm, "%s firmware (%u.%u) is recommended, but only (%u.%u) was found in %s\n",</div><div class='add'>+			   xe_uc_fw_type_repr(uc_fw-&gt;type),</div><div class='add'>+			   wanted-&gt;major, wanted-&gt;minor,</div><div class='add'>+			   found-&gt;major, found-&gt;minor,</div><div class='add'>+			   uc_fw-&gt;path);</div><div class='add'>+		drm_info(&amp;xe-&gt;drm, "Consider updating your linux-firmware pkg or downloading from %s\n",</div><div class='add'>+			 XE_UC_FIRMWARE_URL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	if (xe_uc_fw_is_overridden(uc_fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return -ENOEXEC;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Refer to the "CSS-based Firmware Layout" documentation entry for details */</div><div class='add'>+static int parse_css_header(struct xe_uc_fw *uc_fw, const void *fw_data, size_t fw_size)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	struct xe_uc_fw_version *release = &amp;uc_fw-&gt;versions.found[XE_UC_FW_VER_RELEASE];</div><div class='add'>+	struct uc_css_header *css;</div><div class='add'>+	size_t size;</div><div class='add'>+</div><div class='add'>+	/* Check the size of the blob before examining buffer contents */</div><div class='add'>+	if (unlikely(fw_size &lt; sizeof(struct uc_css_header))) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s firmware %s: invalid size: %zu &lt; %zu\n",</div><div class='add'>+			 xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path,</div><div class='add'>+			 fw_size, sizeof(struct uc_css_header));</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	css = (struct uc_css_header *)fw_data;</div><div class='add'>+</div><div class='add'>+	/* Check integrity of size values inside CSS header */</div><div class='add'>+	size = (css-&gt;header_size_dw - css-&gt;key_size_dw - css-&gt;modulus_size_dw -</div><div class='add'>+		css-&gt;exponent_size_dw) * sizeof(u32);</div><div class='add'>+	if (unlikely(size != sizeof(struct uc_css_header))) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm,</div><div class='add'>+			 "%s firmware %s: unexpected header size: %zu != %zu\n",</div><div class='add'>+			 xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path,</div><div class='add'>+			 fw_size, sizeof(struct uc_css_header));</div><div class='add'>+		return -EPROTO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* uCode size must calculated from other sizes */</div><div class='add'>+	uc_fw-&gt;ucode_size = (css-&gt;size_dw - css-&gt;header_size_dw) * sizeof(u32);</div><div class='add'>+</div><div class='add'>+	/* now RSA */</div><div class='add'>+	uc_fw-&gt;rsa_size = css-&gt;key_size_dw * sizeof(u32);</div><div class='add'>+</div><div class='add'>+	/* At least, it should have header, uCode and RSA. Size of all three. */</div><div class='add'>+	size = sizeof(struct uc_css_header) + uc_fw-&gt;ucode_size +</div><div class='add'>+		uc_fw-&gt;rsa_size;</div><div class='add'>+	if (unlikely(fw_size &lt; size)) {</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "%s firmware %s: invalid size: %zu &lt; %zu\n",</div><div class='add'>+			 xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path,</div><div class='add'>+			 fw_size, size);</div><div class='add'>+		return -ENOEXEC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get version numbers from the CSS header */</div><div class='add'>+	release-&gt;major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css-&gt;sw_version);</div><div class='add'>+	release-&gt;minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css-&gt;sw_version);</div><div class='add'>+	release-&gt;patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css-&gt;sw_version);</div><div class='add'>+</div><div class='add'>+	if (uc_fw-&gt;type == XE_UC_FW_TYPE_GUC)</div><div class='add'>+		guc_read_css_info(uc_fw, css);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool is_cpd_header(const void *data)</div><div class='add'>+{</div><div class='add'>+	const u32 *marker = data;</div><div class='add'>+</div><div class='add'>+	return *marker == GSC_CPD_HEADER_MARKER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 entry_offset(const struct gsc_cpd_header_v2 *header, const char *name)</div><div class='add'>+{</div><div class='add'>+	const struct gsc_cpd_entry *entry;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	entry = (void *)header + header-&gt;header_length;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; header-&gt;num_of_entries; i++, entry++)</div><div class='add'>+		if (strcmp(entry-&gt;name, name) == 0)</div><div class='add'>+			return entry-&gt;offset &amp; GSC_CPD_ENTRY_OFFSET_MASK;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Refer to the "GSC-based Firmware Layout" documentation entry for details */</div><div class='add'>+static int parse_cpd_header(struct xe_uc_fw *uc_fw, const void *data, size_t size,</div><div class='add'>+			    const char *manifest_entry, const char *css_entry)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	const struct gsc_cpd_header_v2 *header = data;</div><div class='add'>+	struct xe_uc_fw_version *release = &amp;uc_fw-&gt;versions.found[XE_UC_FW_VER_RELEASE];</div><div class='add'>+	const struct gsc_manifest_header *manifest;</div><div class='add'>+	size_t min_size = sizeof(*header);</div><div class='add'>+	u32 offset;</div><div class='add'>+</div><div class='add'>+	/* manifest_entry is mandatory, css_entry is optional */</div><div class='add'>+	xe_assert(xe, manifest_entry);</div><div class='add'>+</div><div class='add'>+	if (size &lt; min_size || !is_cpd_header(header))</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	if (header-&gt;header_length &lt; sizeof(struct gsc_cpd_header_v2)) {</div><div class='add'>+		xe_gt_err(gt, "invalid CPD header length %u!\n", header-&gt;header_length);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_size = header-&gt;header_length + sizeof(struct gsc_cpd_entry) * header-&gt;num_of_entries;</div><div class='add'>+	if (size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "FW too small! %zu &lt; %zu\n", size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Look for the manifest first */</div><div class='add'>+	offset = entry_offset(header, manifest_entry);</div><div class='add'>+	if (!offset) {</div><div class='add'>+		xe_gt_err(gt, "Failed to find %s manifest!\n",</div><div class='add'>+			  xe_uc_fw_type_repr(uc_fw-&gt;type));</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_size = offset + sizeof(struct gsc_manifest_header);</div><div class='add'>+	if (size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "FW too small! %zu &lt; %zu\n", size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	manifest = data + offset;</div><div class='add'>+</div><div class='add'>+	release-&gt;major = manifest-&gt;fw_version.major;</div><div class='add'>+	release-&gt;minor = manifest-&gt;fw_version.minor;</div><div class='add'>+	release-&gt;patch = manifest-&gt;fw_version.hotfix;</div><div class='add'>+</div><div class='add'>+	if (uc_fw-&gt;type == XE_UC_FW_TYPE_GSC) {</div><div class='add'>+		struct xe_gsc *gsc = container_of(uc_fw, struct xe_gsc, fw);</div><div class='add'>+</div><div class='add'>+		release-&gt;build = manifest-&gt;fw_version.build;</div><div class='add'>+		gsc-&gt;security_version = manifest-&gt;security_version;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* then optionally look for the css header */</div><div class='add'>+	if (css_entry) {</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * This section does not contain a CSS entry on DG2. We</div><div class='add'>+		 * don't support DG2 HuC right now, so no need to handle</div><div class='add'>+		 * it, just add a reminder in case that changes.</div><div class='add'>+		 */</div><div class='add'>+		xe_assert(xe, xe-&gt;info.platform != XE_DG2);</div><div class='add'>+</div><div class='add'>+		offset = entry_offset(header, css_entry);</div><div class='add'>+</div><div class='add'>+		/* the CSS header parser will check that the CSS header fits */</div><div class='add'>+		if (offset &gt; size) {</div><div class='add'>+			xe_gt_err(gt, "FW too small! %zu &lt; %u\n", size, offset);</div><div class='add'>+			return -ENODATA;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = parse_css_header(uc_fw, data + offset, size - offset);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		uc_fw-&gt;css_offset = offset;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	uc_fw-&gt;has_gsc_headers = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_gsc_layout(struct xe_uc_fw *uc_fw, const void *data, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);</div><div class='add'>+	const struct gsc_layout_pointers *layout = data;</div><div class='add'>+	const struct gsc_bpdt_header *bpdt_header = NULL;</div><div class='add'>+	const struct gsc_bpdt_entry *bpdt_entry = NULL;</div><div class='add'>+	size_t min_size = sizeof(*layout);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "GSC FW too small! %zu &lt; %zu\n", size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_size = layout-&gt;boot1.offset + layout-&gt;boot1.size;</div><div class='add'>+	if (size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "GSC FW too small for boot section! %zu &lt; %zu\n",</div><div class='add'>+			  size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_size = sizeof(*bpdt_header);</div><div class='add'>+	if (layout-&gt;boot1.size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "GSC FW boot section too small for BPDT header: %u &lt; %zu\n",</div><div class='add'>+			  layout-&gt;boot1.size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bpdt_header = data + layout-&gt;boot1.offset;</div><div class='add'>+	if (bpdt_header-&gt;signature != GSC_BPDT_HEADER_SIGNATURE) {</div><div class='add'>+		xe_gt_err(gt, "invalid signature for BPDT header: 0x%08x!\n",</div><div class='add'>+			  bpdt_header-&gt;signature);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_size += sizeof(*bpdt_entry) * bpdt_header-&gt;descriptor_count;</div><div class='add'>+	if (layout-&gt;boot1.size &lt; min_size) {</div><div class='add'>+		xe_gt_err(gt, "GSC FW boot section too small for BPDT entries: %u &lt; %zu\n",</div><div class='add'>+			  layout-&gt;boot1.size, min_size);</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	bpdt_entry = (void *)bpdt_header + sizeof(*bpdt_header);</div><div class='add'>+	for (i = 0; i &lt; bpdt_header-&gt;descriptor_count; i++, bpdt_entry++) {</div><div class='add'>+		if ((bpdt_entry-&gt;type &amp; GSC_BPDT_ENTRY_TYPE_MASK) !=</div><div class='add'>+		    GSC_BPDT_ENTRY_TYPE_GSC_RBE)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		min_size = bpdt_entry-&gt;sub_partition_offset;</div><div class='add'>+</div><div class='add'>+		/* the CPD header parser will check that the CPD header fits */</div><div class='add'>+		if (layout-&gt;boot1.size &lt; min_size) {</div><div class='add'>+			xe_gt_err(gt, "GSC FW boot section too small for CPD offset: %u &lt; %zu\n",</div><div class='add'>+				  layout-&gt;boot1.size, min_size);</div><div class='add'>+			return -ENODATA;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return parse_cpd_header(uc_fw,</div><div class='add'>+					(void *)bpdt_header + min_size,</div><div class='add'>+					layout-&gt;boot1.size - min_size,</div><div class='add'>+					"RBEP.man", NULL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_gt_err(gt, "couldn't find CPD header in GSC binary!\n");</div><div class='add'>+	return -ENODATA;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_headers(struct xe_uc_fw *uc_fw, const struct firmware *fw)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All GuC releases and older HuC ones use CSS headers, while newer HuC</div><div class='add'>+	 * releases use GSC CPD headers.</div><div class='add'>+	 */</div><div class='add'>+	switch (uc_fw-&gt;type) {</div><div class='add'>+	case XE_UC_FW_TYPE_GSC:</div><div class='add'>+		return parse_gsc_layout(uc_fw, fw-&gt;data, fw-&gt;size);</div><div class='add'>+	case XE_UC_FW_TYPE_HUC:</div><div class='add'>+		ret = parse_cpd_header(uc_fw, fw-&gt;data, fw-&gt;size, "HUCP.man", "huc_fw");</div><div class='add'>+		if (!ret || ret != -ENOENT)</div><div class='add'>+			return ret;</div><div class='add'>+		fallthrough;</div><div class='add'>+	case XE_UC_FW_TYPE_GUC:</div><div class='add'>+		return parse_css_header(uc_fw, fw-&gt;data, fw-&gt;size);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define print_uc_fw_version(p_, version_, prefix_, ...) \</div><div class='add'>+do { \</div><div class='add'>+	struct xe_uc_fw_version *ver_ = (version_); \</div><div class='add'>+	if (ver_-&gt;build) \</div><div class='add'>+		drm_printf(p_, prefix_ " version %u.%u.%u.%u\n", ##__VA_ARGS__, \</div><div class='add'>+			   ver_-&gt;major, ver_-&gt;minor, \</div><div class='add'>+			   ver_-&gt;patch, ver_-&gt;build); \</div><div class='add'>+	else \</div><div class='add'>+		drm_printf(p_, prefix_ " version %u.%u.%u\n", ##__VA_ARGS__, \</div><div class='add'>+			  ver_-&gt;major, ver_-&gt;minor, ver_-&gt;patch); \</div><div class='add'>+} while (0)</div><div class='add'>+</div><div class='add'>+static int uc_fw_request(struct xe_uc_fw *uc_fw, const struct firmware **firmware_p)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	struct device *dev = xe-&gt;drm.dev;</div><div class='add'>+	struct drm_printer p = drm_info_printer(dev);</div><div class='add'>+	const struct firmware *fw = NULL;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw-&gt;status</div><div class='add'>+	 * before we're looked at the HW caps to see if we have uc support</div><div class='add'>+	 */</div><div class='add'>+	BUILD_BUG_ON(XE_UC_FIRMWARE_UNINITIALIZED);</div><div class='add'>+	xe_assert(xe, !uc_fw-&gt;status);</div><div class='add'>+	xe_assert(xe, !uc_fw-&gt;path);</div><div class='add'>+</div><div class='add'>+	uc_fw_auto_select(xe, uc_fw);</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, uc_fw-&gt;path ?</div><div class='add'>+			       XE_UC_FIRMWARE_SELECTED :</div><div class='add'>+			       XE_UC_FIRMWARE_NOT_SUPPORTED);</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_supported(uc_fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	uc_fw_override(uc_fw);</div><div class='add'>+</div><div class='add'>+	/* an empty path means the firmware is disabled */</div><div class='add'>+	if (!xe_device_uc_enabled(xe) || !(*uc_fw-&gt;path)) {</div><div class='add'>+		xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_DISABLED);</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "%s disabled", xe_uc_fw_type_repr(uc_fw-&gt;type));</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = request_firmware(&amp;fw, uc_fw-&gt;path, dev);</div><div class='add'>+	if (err)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	err = parse_headers(uc_fw, fw);</div><div class='add'>+	if (err)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	print_uc_fw_version(&amp;p,</div><div class='add'>+			    &amp;uc_fw-&gt;versions.found[XE_UC_FW_VER_RELEASE],</div><div class='add'>+			    "Using %s firmware from %s",</div><div class='add'>+			    xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path);</div><div class='add'>+</div><div class='add'>+	/* for GSC FW we want the compatibility version, which we query after load */</div><div class='add'>+	if (uc_fw-&gt;type != XE_UC_FW_TYPE_GSC) {</div><div class='add'>+		err = xe_uc_fw_check_version_requirements(uc_fw);</div><div class='add'>+		if (err)</div><div class='add'>+			goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*firmware_p = fw;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, err == -ENOENT ?</div><div class='add'>+			       XE_UC_FIRMWARE_MISSING :</div><div class='add'>+			       XE_UC_FIRMWARE_ERROR);</div><div class='add'>+</div><div class='add'>+	drm_notice(&amp;xe-&gt;drm, "%s firmware %s: fetch failed with error %d\n",</div><div class='add'>+		   xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path, err);</div><div class='add'>+	drm_info(&amp;xe-&gt;drm, "%s firmware(s) can be downloaded from %s\n",</div><div class='add'>+		 xe_uc_fw_type_repr(uc_fw-&gt;type), XE_UC_FIRMWARE_URL);</div><div class='add'>+</div><div class='add'>+	release_firmware(fw);		/* OK even if fw is NULL */</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void uc_fw_release(const struct firmware *fw)</div><div class='add'>+{</div><div class='add'>+	release_firmware(fw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int uc_fw_copy(struct xe_uc_fw *uc_fw, const void *data, size_t size, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);</div><div class='add'>+	struct xe_tile *tile = gt_to_tile(gt);</div><div class='add'>+	struct xe_bo *obj;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	obj = xe_managed_bo_create_from_data(xe, tile, data, size, flags);</div><div class='add'>+	if (IS_ERR(obj)) {</div><div class='add'>+		drm_notice(&amp;xe-&gt;drm, "%s firmware %s: failed to create / populate bo",</div><div class='add'>+			   xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path);</div><div class='add'>+		err = PTR_ERR(obj);</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	uc_fw-&gt;bo = obj;</div><div class='add'>+	uc_fw-&gt;size = size;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_AVAILABLE);</div><div class='add'>+</div><div class='add'>+	err = drmm_add_action_or_reset(&amp;xe-&gt;drm, uc_fw_fini, uc_fw);</div><div class='add'>+	if (err)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_ERROR);</div><div class='add'>+	drm_notice(&amp;xe-&gt;drm, "%s firmware %s: copy failed with error %d\n",</div><div class='add'>+		   xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path, err);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_fw_init(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	const struct firmware *fw = NULL;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = uc_fw_request(uc_fw, &amp;fw);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* no error and no firmware means nothing to copy */</div><div class='add'>+	if (!fw)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = uc_fw_copy(uc_fw, fw-&gt;data, fw-&gt;size,</div><div class='add'>+			 XE_BO_CREATE_SYSTEM_BIT | XE_BO_CREATE_GGTT_BIT);</div><div class='add'>+</div><div class='add'>+	uc_fw_release(fw);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 uc_fw_ggtt_offset(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return xe_bo_ggtt_addr(uc_fw-&gt;bo);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);</div><div class='add'>+	u32 src_offset, dma_ctrl;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+</div><div class='add'>+	/* Set the source address for the uCode */</div><div class='add'>+	src_offset = uc_fw_ggtt_offset(uc_fw) + uc_fw-&gt;css_offset;</div><div class='add'>+	xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));</div><div class='add'>+	xe_mmio_write32(gt, DMA_ADDR_0_HIGH,</div><div class='add'>+			upper_32_bits(src_offset) | DMA_ADDRESS_SPACE_GGTT);</div><div class='add'>+</div><div class='add'>+	/* Set the DMA destination */</div><div class='add'>+	xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);</div><div class='add'>+	xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set the transfer size. The header plus uCode will be copied to WOPCM</div><div class='add'>+	 * via DMA, excluding any other components</div><div class='add'>+	 */</div><div class='add'>+	xe_mmio_write32(gt, DMA_COPY_SIZE,</div><div class='add'>+			sizeof(struct uc_css_header) + uc_fw-&gt;ucode_size);</div><div class='add'>+</div><div class='add'>+	/* Start the DMA */</div><div class='add'>+	xe_mmio_write32(gt, DMA_CTRL,</div><div class='add'>+			_MASKED_BIT_ENABLE(dma_flags | START_DMA));</div><div class='add'>+</div><div class='add'>+	/* Wait for DMA to finish */</div><div class='add'>+	ret = xe_mmio_wait32(gt, DMA_CTRL, START_DMA, 0, 100000, &amp;dma_ctrl,</div><div class='add'>+			     false);</div><div class='add'>+	if (ret)</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "DMA for %s fw failed, DMA_CTRL=%u\n",</div><div class='add'>+			xe_uc_fw_type_repr(uc_fw-&gt;type), dma_ctrl);</div><div class='add'>+</div><div class='add'>+	/* Disable the bits once DMA is over */</div><div class='add'>+	xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_uc_fw_upload(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = uc_fw_to_xe(uc_fw);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* make sure the status was cleared the last time we reset the uc */</div><div class='add'>+	xe_assert(xe, !xe_uc_fw_is_loaded(uc_fw));</div><div class='add'>+</div><div class='add'>+	if (!xe_uc_fw_is_loadable(uc_fw))</div><div class='add'>+		return -ENOEXEC;</div><div class='add'>+</div><div class='add'>+	/* Call custom loader */</div><div class='add'>+	err = uc_fw_xfer(uc_fw, offset, dma_flags);</div><div class='add'>+	if (err)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_TRANSFERRED);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail:</div><div class='add'>+	drm_err(&amp;xe-&gt;drm, "Failed to load %s firmware %s (%d)\n",</div><div class='add'>+		xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path,</div><div class='add'>+		err);</div><div class='add'>+	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_LOAD_FAIL);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *version_type_repr(enum xe_uc_fw_version_types type)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case XE_UC_FW_VER_RELEASE:</div><div class='add'>+		return "release";</div><div class='add'>+	case XE_UC_FW_VER_COMPATIBILITY:</div><div class='add'>+		return "compatibility";</div><div class='add'>+	default:</div><div class='add'>+		return "Unknown version type";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_uc_fw_print(struct xe_uc_fw *uc_fw, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "%s firmware: %s\n",</div><div class='add'>+		   xe_uc_fw_type_repr(uc_fw-&gt;type), uc_fw-&gt;path);</div><div class='add'>+	drm_printf(p, "\tstatus: %s\n",</div><div class='add'>+		   xe_uc_fw_status_repr(uc_fw-&gt;status));</div><div class='add'>+</div><div class='add'>+	print_uc_fw_version(p, &amp;uc_fw-&gt;versions.wanted, "\twanted %s",</div><div class='add'>+			    version_type_repr(uc_fw-&gt;versions.wanted_type));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; XE_UC_FW_VER_TYPE_COUNT; i++) {</div><div class='add'>+		struct xe_uc_fw_version *ver = &amp;uc_fw-&gt;versions.found[i];</div><div class='add'>+</div><div class='add'>+		if (ver-&gt;major)</div><div class='add'>+			print_uc_fw_version(p, ver, "\tfound %s",</div><div class='add'>+					    version_type_repr(i));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (uc_fw-&gt;ucode_size)</div><div class='add'>+		drm_printf(p, "\tuCode: %u bytes\n", uc_fw-&gt;ucode_size);</div><div class='add'>+	if (uc_fw-&gt;rsa_size)</div><div class='add'>+		drm_printf(p, "\tRSA: %u bytes\n", uc_fw-&gt;rsa_size);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.h b/drivers/gpu/drm/xe/xe_uc_fw.h<br/>new file mode 100644<br/>index 000000000000..85c20795d1f8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_fw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw.h</a></div><div class='hunk'>@@ -0,0 +1,184 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_FW_H_</div><div class='add'>+#define _XE_UC_FW_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_uc_fw_abi.h"</div><div class='add'>+#include "xe_uc_fw_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+</div><div class='add'>+int xe_uc_fw_init(struct xe_uc_fw *uc_fw);</div><div class='add'>+size_t xe_uc_fw_copy_rsa(struct xe_uc_fw *uc_fw, void *dst, u32 max_len);</div><div class='add'>+int xe_uc_fw_upload(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags);</div><div class='add'>+int xe_uc_fw_check_version_requirements(struct xe_uc_fw *uc_fw);</div><div class='add'>+void xe_uc_fw_print(struct xe_uc_fw *uc_fw, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+static inline u32 xe_uc_fw_rsa_offset(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return sizeof(struct uc_css_header) + uc_fw-&gt;ucode_size + uc_fw-&gt;css_offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw,</div><div class='add'>+					  enum xe_uc_fw_status status)</div><div class='add'>+{</div><div class='add'>+	uc_fw-&gt;__status = status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+const char *xe_uc_fw_status_repr(enum xe_uc_fw_status status)</div><div class='add'>+{</div><div class='add'>+	switch (status) {</div><div class='add'>+	case XE_UC_FIRMWARE_NOT_SUPPORTED:</div><div class='add'>+		return "N/A";</div><div class='add'>+	case XE_UC_FIRMWARE_UNINITIALIZED:</div><div class='add'>+		return "UNINITIALIZED";</div><div class='add'>+	case XE_UC_FIRMWARE_DISABLED:</div><div class='add'>+		return "DISABLED";</div><div class='add'>+	case XE_UC_FIRMWARE_SELECTED:</div><div class='add'>+		return "SELECTED";</div><div class='add'>+	case XE_UC_FIRMWARE_MISSING:</div><div class='add'>+		return "MISSING";</div><div class='add'>+	case XE_UC_FIRMWARE_ERROR:</div><div class='add'>+		return "ERROR";</div><div class='add'>+	case XE_UC_FIRMWARE_AVAILABLE:</div><div class='add'>+		return "AVAILABLE";</div><div class='add'>+	case XE_UC_FIRMWARE_INIT_FAIL:</div><div class='add'>+		return "INIT FAIL";</div><div class='add'>+	case XE_UC_FIRMWARE_LOADABLE:</div><div class='add'>+		return "LOADABLE";</div><div class='add'>+	case XE_UC_FIRMWARE_LOAD_FAIL:</div><div class='add'>+		return "LOAD FAIL";</div><div class='add'>+	case XE_UC_FIRMWARE_TRANSFERRED:</div><div class='add'>+		return "TRANSFERRED";</div><div class='add'>+	case XE_UC_FIRMWARE_RUNNING:</div><div class='add'>+		return "RUNNING";</div><div class='add'>+	}</div><div class='add'>+	return "&lt;invalid&gt;";</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int xe_uc_fw_status_to_error(enum xe_uc_fw_status status)</div><div class='add'>+{</div><div class='add'>+	switch (status) {</div><div class='add'>+	case XE_UC_FIRMWARE_NOT_SUPPORTED:</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	case XE_UC_FIRMWARE_UNINITIALIZED:</div><div class='add'>+		return -EACCES;</div><div class='add'>+	case XE_UC_FIRMWARE_DISABLED:</div><div class='add'>+		return -EPERM;</div><div class='add'>+	case XE_UC_FIRMWARE_MISSING:</div><div class='add'>+		return -ENOENT;</div><div class='add'>+	case XE_UC_FIRMWARE_ERROR:</div><div class='add'>+		return -ENOEXEC;</div><div class='add'>+	case XE_UC_FIRMWARE_INIT_FAIL:</div><div class='add'>+	case XE_UC_FIRMWARE_LOAD_FAIL:</div><div class='add'>+		return -EIO;</div><div class='add'>+	case XE_UC_FIRMWARE_SELECTED:</div><div class='add'>+		return -ESTALE;</div><div class='add'>+	case XE_UC_FIRMWARE_AVAILABLE:</div><div class='add'>+	case XE_UC_FIRMWARE_LOADABLE:</div><div class='add'>+	case XE_UC_FIRMWARE_TRANSFERRED:</div><div class='add'>+	case XE_UC_FIRMWARE_RUNNING:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline const char *xe_uc_fw_type_repr(enum xe_uc_fw_type type)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case XE_UC_FW_TYPE_GUC:</div><div class='add'>+		return "GuC";</div><div class='add'>+	case XE_UC_FW_TYPE_HUC:</div><div class='add'>+		return "HuC";</div><div class='add'>+	case XE_UC_FW_TYPE_GSC:</div><div class='add'>+		return "GSC";</div><div class='add'>+	default:</div><div class='add'>+		return "uC";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline enum xe_uc_fw_status</div><div class='add'>+__xe_uc_fw_status(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	/* shouldn't call this before checking hw/blob availability */</div><div class='add'>+	XE_WARN_ON(uc_fw-&gt;status == XE_UC_FIRMWARE_UNINITIALIZED);</div><div class='add'>+	return uc_fw-&gt;status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_supported(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) != XE_UC_FIRMWARE_NOT_SUPPORTED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_enabled(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) &gt; XE_UC_FIRMWARE_DISABLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_disabled(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) == XE_UC_FIRMWARE_DISABLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_available(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) &gt;= XE_UC_FIRMWARE_AVAILABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_loadable(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) &gt;= XE_UC_FIRMWARE_LOADABLE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_loaded(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) &gt;= XE_UC_FIRMWARE_TRANSFERRED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_running(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return __xe_uc_fw_status(uc_fw) == XE_UC_FIRMWARE_RUNNING;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_uc_fw_is_overridden(const struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return uc_fw-&gt;user_overridden;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_uc_fw_sanitize(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	if (xe_uc_fw_is_loaded(uc_fw))</div><div class='add'>+		xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_LOADABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 __xe_uc_fw_get_upload_size(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	return sizeof(struct uc_css_header) + uc_fw-&gt;ucode_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.</div><div class='add'>+ * @uc_fw: uC firmware.</div><div class='add'>+ *</div><div class='add'>+ * Get the size of the firmware and header that will be uploaded to WOPCM.</div><div class='add'>+ *</div><div class='add'>+ * Return: Upload firmware size, or zero on firmware fetch failure.</div><div class='add'>+ */</div><div class='add'>+static inline u32 xe_uc_fw_get_upload_size(struct xe_uc_fw *uc_fw)</div><div class='add'>+{</div><div class='add'>+	if (!xe_uc_fw_is_available(uc_fw))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return __xe_uc_fw_get_upload_size(uc_fw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define XE_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git"</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h<br/>new file mode 100644<br/>index 000000000000..87ade41209d0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_fw_abi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw_abi.h</a></div><div class='hunk'>@@ -0,0 +1,321 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_FW_ABI_H</div><div class='add'>+#define _XE_UC_FW_ABI_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/build_bug.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: CSS-based Firmware Layout</div><div class='add'>+ *</div><div class='add'>+ * The CSS-based firmware structure is used for GuC releases on all platforms</div><div class='add'>+ * and for HuC releases up to DG1. Starting from DG2/MTL the HuC uses the GSC</div><div class='add'>+ * layout instead.</div><div class='add'>+ * The CSS firmware layout looks like this::</div><div class='add'>+ *</div><div class='add'>+ *      +======================================================================+</div><div class='add'>+ *      |  Firmware blob                                                       |</div><div class='add'>+ *      +===============+===============+============+============+============+</div><div class='add'>+ *      |  CSS header   |     uCode     |  RSA key   |  modulus   |  exponent  |</div><div class='add'>+ *      +===============+===============+============+============+============+</div><div class='add'>+ *       &lt;-header size-&gt;                 &lt;---header size continued -----------&gt;</div><div class='add'>+ *       &lt;--- size -----------------------------------------------------------&gt;</div><div class='add'>+ *                                       &lt;-key size-&gt;</div><div class='add'>+ *                                                    &lt;-mod size-&gt;</div><div class='add'>+ *                                                                 &lt;-exp size-&gt;</div><div class='add'>+ *</div><div class='add'>+ * The firmware may or may not have modulus key and exponent data. The header,</div><div class='add'>+ * uCode and RSA signature are must-have components that will be used by driver.</div><div class='add'>+ * Length of each components, which is all in dwords, can be found in header.</div><div class='add'>+ * In the case that modulus and exponent are not present in fw, a.k.a truncated</div><div class='add'>+ * image, the length value still appears in header.</div><div class='add'>+ *</div><div class='add'>+ * Driver will do some basic fw size validation based on the following rules:</div><div class='add'>+ *</div><div class='add'>+ * 1. Header, uCode and RSA are must-have components.</div><div class='add'>+ * 2. All firmware components, if they present, are in the sequence illustrated</div><div class='add'>+ *    in the layout table above.</div><div class='add'>+ * 3. Length info of each component can be found in header, in dwords.</div><div class='add'>+ * 4. Modulus and exponent key are not required by driver. They may not appear</div><div class='add'>+ *    in fw. So driver will load a truncated firmware in this case.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct uc_css_header {</div><div class='add'>+	u32 module_type;</div><div class='add'>+	/*</div><div class='add'>+	 * header_size includes all non-uCode bits, including css_header, rsa</div><div class='add'>+	 * key, modulus key and exponent data.</div><div class='add'>+	 */</div><div class='add'>+	u32 header_size_dw;</div><div class='add'>+	u32 header_version;</div><div class='add'>+	u32 module_id;</div><div class='add'>+	u32 module_vendor;</div><div class='add'>+	u32 date;</div><div class='add'>+#define CSS_DATE_DAY			(0xFF &lt;&lt; 0)</div><div class='add'>+#define CSS_DATE_MONTH			(0xFF &lt;&lt; 8)</div><div class='add'>+#define CSS_DATE_YEAR			(0xFFFF &lt;&lt; 16)</div><div class='add'>+	u32 size_dw; /* uCode plus header_size_dw */</div><div class='add'>+	u32 key_size_dw;</div><div class='add'>+	u32 modulus_size_dw;</div><div class='add'>+	u32 exponent_size_dw;</div><div class='add'>+	u32 time;</div><div class='add'>+#define CSS_TIME_HOUR			(0xFF &lt;&lt; 0)</div><div class='add'>+#define CSS_DATE_MIN			(0xFF &lt;&lt; 8)</div><div class='add'>+#define CSS_DATE_SEC			(0xFFFF &lt;&lt; 16)</div><div class='add'>+	char username[8];</div><div class='add'>+	char buildnumber[12];</div><div class='add'>+	u32 sw_version;</div><div class='add'>+#define CSS_SW_VERSION_UC_MAJOR		(0xFF &lt;&lt; 16)</div><div class='add'>+#define CSS_SW_VERSION_UC_MINOR		(0xFF &lt;&lt; 8)</div><div class='add'>+#define CSS_SW_VERSION_UC_PATCH		(0xFF &lt;&lt; 0)</div><div class='add'>+	union {</div><div class='add'>+		u32 submission_version; /* only applies to GuC */</div><div class='add'>+		u32 reserved2;</div><div class='add'>+	};</div><div class='add'>+	u32 reserved0[12];</div><div class='add'>+	union {</div><div class='add'>+		u32 private_data_size; /* only applies to GuC */</div><div class='add'>+		u32 reserved1;</div><div class='add'>+	};</div><div class='add'>+	u32 header_info;</div><div class='add'>+} __packed;</div><div class='add'>+static_assert(sizeof(struct uc_css_header) == 128);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: GSC-based Firmware Layout</div><div class='add'>+ *</div><div class='add'>+ * The GSC-based firmware structure is used for GSC releases on all platforms</div><div class='add'>+ * and for HuC releases starting from DG2/MTL. Older HuC releases use the</div><div class='add'>+ * CSS-based layout instead. Differently from the CSS headers, the GSC headers</div><div class='add'>+ * uses a directory + entries structure (i.e., there is array of addresses</div><div class='add'>+ * pointing to specific header extensions identified by a name). Although the</div><div class='add'>+ * header structures are the same, some of the entries are specific to GSC while</div><div class='add'>+ * others are specific to HuC. The manifest header entry, which includes basic</div><div class='add'>+ * information about the binary (like the version) is always present, but it is</div><div class='add'>+ * named differently based on the binary type.</div><div class='add'>+ *</div><div class='add'>+ * The HuC binary starts with a Code Partition Directory (CPD) header. The</div><div class='add'>+ * entries we're interested in for use in the driver are:</div><div class='add'>+ *</div><div class='add'>+ * 1. "HUCP.man": points to the manifest header for the HuC.</div><div class='add'>+ * 2. "huc_fw": points to the FW code. On platforms that support load via DMA</div><div class='add'>+ *    and 2-step HuC authentication (i.e. MTL+) this is a full CSS-based binary,</div><div class='add'>+ *    while if the GSC is the one doing the load (which only happens on DG2)</div><div class='add'>+ *    this section only contains the uCode.</div><div class='add'>+ *</div><div class='add'>+ * The GSC-based HuC firmware layout looks like this::</div><div class='add'>+ *</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *	|  CPD Header                                    |</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *	|  CPD entries[]                                 |</div><div class='add'>+ *	|      entry1                                    |</div><div class='add'>+ *	|      ...                                       |</div><div class='add'>+ *	|      entryX                                    |</div><div class='add'>+ *	|          "HUCP.man"                            |</div><div class='add'>+ *	|           ...                                  |</div><div class='add'>+ *	|           offset  &gt;----------------------------|------o</div><div class='add'>+ *	|      ...                                       |      |</div><div class='add'>+ *	|      entryY                                    |      |</div><div class='add'>+ *	|          "huc_fw"                              |      |</div><div class='add'>+ *	|           ...                                  |      |</div><div class='add'>+ *	|           offset  &gt;----------------------------|----------o</div><div class='add'>+ *	+================================================+      |   |</div><div class='add'>+ *	                                                        |   |</div><div class='add'>+ *	+================================================+      |   |</div><div class='add'>+ *	|  Manifest Header                               |&lt;-----o   |</div><div class='add'>+ *	|      ...                                       |          |</div><div class='add'>+ *	|      FW version                                |          |</div><div class='add'>+ *	|      ...                                       |          |</div><div class='add'>+ *	+================================================+          |</div><div class='add'>+ *	                                                            |</div><div class='add'>+ *	+================================================+          |</div><div class='add'>+ *	|  FW binary                                     |&lt;---------o</div><div class='add'>+ *	|      CSS (MTL+ only)                           |</div><div class='add'>+ *	|      uCode                                     |</div><div class='add'>+ *	|      RSA Key (MTL+ only)                       |</div><div class='add'>+ *	|      ...                                       |</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *</div><div class='add'>+ * The GSC binary starts instead with a layout header, which contains the</div><div class='add'>+ * locations of the various partitions of the binary. The one we're interested</div><div class='add'>+ * in is the boot1 partition, where we can find a BPDT header followed by</div><div class='add'>+ * entries, one of which points to the RBE sub-section of the partition, which</div><div class='add'>+ * contains the CPD. The GSC blob does not contain a CSS-based binary, so we</div><div class='add'>+ * only need to look for the manifest, which is under the "RBEP.man" CPD entry.</div><div class='add'>+ * Note that we have no need to find where the actual FW code is inside the</div><div class='add'>+ * image because the GSC ROM will itself parse the headers to find it and load</div><div class='add'>+ * it.</div><div class='add'>+ * The GSC firmware header layout looks like this::</div><div class='add'>+ *</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *	|  Layout Pointers                               |</div><div class='add'>+ *	|      ...                                       |</div><div class='add'>+ *	|      Boot1 offset  &gt;---------------------------|------o</div><div class='add'>+ *	|      ...                                       |      |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	                                                        |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	|  BPDT header                                   |&lt;-----o</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *	|  BPDT entries[]                                |</div><div class='add'>+ *	|      entry1                                    |</div><div class='add'>+ *	|      ...                                       |</div><div class='add'>+ *	|      entryX                                    |</div><div class='add'>+ *	|          type == GSC_RBE                       |</div><div class='add'>+ *	|          offset  &gt;-----------------------------|------o</div><div class='add'>+ *	|      ...                                       |      |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	                                                        |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	|  CPD Header                                    |&lt;-----o</div><div class='add'>+ *	+================================================+</div><div class='add'>+ *	|  CPD entries[]                                 |</div><div class='add'>+ *	|      entry1                                    |</div><div class='add'>+ *	|      ...                                       |</div><div class='add'>+ *	|      entryX                                    |</div><div class='add'>+ *	|          "RBEP.man"                            |</div><div class='add'>+ *	|           ...                                  |</div><div class='add'>+ *	|           offset  &gt;----------------------------|------o</div><div class='add'>+ *	|      ...                                       |      |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	                                                        |</div><div class='add'>+ *	+================================================+      |</div><div class='add'>+ *	| Manifest Header                                |&lt;-----o</div><div class='add'>+ *	|  ...                                           |</div><div class='add'>+ *	|  FW version                                    |</div><div class='add'>+ *	|  ...                                           |</div><div class='add'>+ *	|  Security version                              |</div><div class='add'>+ *	|  ...                                           |</div><div class='add'>+ *	+================================================+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct gsc_version {</div><div class='add'>+	u16 major;</div><div class='add'>+	u16 minor;</div><div class='add'>+	u16 hotfix;</div><div class='add'>+	u16 build;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_partition {</div><div class='add'>+	u32 offset;</div><div class='add'>+	u32 size;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_layout_pointers {</div><div class='add'>+	u8 rom_bypass_vector[16];</div><div class='add'>+</div><div class='add'>+	/* size of this header section, not including ROM bypass vector */</div><div class='add'>+	u16 size;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * bit0: Backup copy of layout pointers exists</div><div class='add'>+	 * bits1-15: reserved</div><div class='add'>+	 */</div><div class='add'>+	u8 flags;</div><div class='add'>+</div><div class='add'>+	u8 reserved;</div><div class='add'>+</div><div class='add'>+	u32 crc32;</div><div class='add'>+</div><div class='add'>+	struct gsc_partition datap;</div><div class='add'>+	struct gsc_partition boot1;</div><div class='add'>+	struct gsc_partition boot2;</div><div class='add'>+	struct gsc_partition boot3;</div><div class='add'>+	struct gsc_partition boot4;</div><div class='add'>+	struct gsc_partition boot5;</div><div class='add'>+	struct gsc_partition temp_pages;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Boot partition structures */</div><div class='add'>+struct gsc_bpdt_header {</div><div class='add'>+	u32 signature;</div><div class='add'>+#define GSC_BPDT_HEADER_SIGNATURE 0x000055AA</div><div class='add'>+</div><div class='add'>+	u16 descriptor_count; /* num of entries after the header */</div><div class='add'>+</div><div class='add'>+	u8 version;</div><div class='add'>+	u8 configuration;</div><div class='add'>+</div><div class='add'>+	u32 crc32;</div><div class='add'>+</div><div class='add'>+	u32 build_version;</div><div class='add'>+	struct gsc_version tool_version;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_bpdt_entry {</div><div class='add'>+	/*</div><div class='add'>+	 * Bits 0-15: BPDT entry type</div><div class='add'>+	 * Bits 16-17: reserved</div><div class='add'>+	 * Bit 18: code sub-partition</div><div class='add'>+	 * Bits 19-31: reserved</div><div class='add'>+	 */</div><div class='add'>+	u32 type;</div><div class='add'>+#define GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)</div><div class='add'>+#define GSC_BPDT_ENTRY_TYPE_GSC_RBE 0x1</div><div class='add'>+</div><div class='add'>+	u32 sub_partition_offset; /* from the base of the BPDT header */</div><div class='add'>+	u32 sub_partition_size;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Code partition directory (CPD) structures */</div><div class='add'>+struct gsc_cpd_header_v2 {</div><div class='add'>+	u32 header_marker;</div><div class='add'>+#define GSC_CPD_HEADER_MARKER 0x44504324</div><div class='add'>+</div><div class='add'>+	u32 num_of_entries;</div><div class='add'>+	u8 header_version;</div><div class='add'>+	u8 entry_version;</div><div class='add'>+	u8 header_length; /* in bytes */</div><div class='add'>+	u8 flags;</div><div class='add'>+	u32 partition_name;</div><div class='add'>+	u32 crc32;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_cpd_entry {</div><div class='add'>+	u8 name[12];</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Bits 0-24: offset from the beginning of the code partition</div><div class='add'>+	 * Bit 25: huffman compressed</div><div class='add'>+	 * Bits 26-31: reserved</div><div class='add'>+	 */</div><div class='add'>+	u32 offset;</div><div class='add'>+#define GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)</div><div class='add'>+#define GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Module/Item length, in bytes. For Huffman-compressed modules, this</div><div class='add'>+	 * refers to the uncompressed size. For software-compressed modules,</div><div class='add'>+	 * this refers to the compressed size.</div><div class='add'>+	 */</div><div class='add'>+	u32 length;</div><div class='add'>+</div><div class='add'>+	u8 reserved[4];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gsc_manifest_header {</div><div class='add'>+	u32 header_type; /* 0x4 for manifest type */</div><div class='add'>+	u32 header_length; /* in dwords */</div><div class='add'>+	u32 header_version;</div><div class='add'>+	u32 flags;</div><div class='add'>+	u32 vendor;</div><div class='add'>+	u32 date;</div><div class='add'>+	u32 size; /* In dwords, size of entire manifest (header + extensions) */</div><div class='add'>+	u32 header_id;</div><div class='add'>+	u32 internal_data;</div><div class='add'>+	struct gsc_version fw_version;</div><div class='add'>+	u32 security_version;</div><div class='add'>+	struct gsc_version meu_kit_version;</div><div class='add'>+	u32 meu_manifest_version;</div><div class='add'>+	u8 general_data[4];</div><div class='add'>+	u8 reserved3[56];</div><div class='add'>+	u32 modulus_size; /* in dwords */</div><div class='add'>+	u32 exponent_size; /* in dwords */</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_fw_types.h b/drivers/gpu/drm/xe/xe_uc_fw_types.h<br/>new file mode 100644<br/>index 000000000000..ee914a5d8523<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_fw_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_fw_types.h</a></div><div class='hunk'>@@ -0,0 +1,146 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_FW_TYPES_H_</div><div class='add'>+#define _XE_UC_FW_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * +------------+---------------------------------------------------+</div><div class='add'>+ * |   PHASE    |           FIRMWARE STATUS TRANSITIONS             |</div><div class='add'>+ * +============+===================================================+</div><div class='add'>+ * |            |               UNINITIALIZED                       |</div><div class='add'>+ * +------------+-               /   |   \                         -+</div><div class='add'>+ * |            |   DISABLED &lt;--/    |    \--&gt; NOT_SUPPORTED        |</div><div class='add'>+ * | init_early |                    V                              |</div><div class='add'>+ * |            |                 SELECTED                          |</div><div class='add'>+ * +------------+-               /   |   \                         -+</div><div class='add'>+ * |            |    MISSING &lt;--/    |    \--&gt; ERROR                |</div><div class='add'>+ * |   fetch    |                    V                              |</div><div class='add'>+ * |            |                 AVAILABLE                         |</div><div class='add'>+ * +------------+-                   |   \                         -+</div><div class='add'>+ * |            |                    |    \--&gt; INIT FAIL            |</div><div class='add'>+ * |   init     |                    V                              |</div><div class='add'>+ * |            |        /------&gt; LOADABLE &lt;----&lt;-----------\       |</div><div class='add'>+ * +------------+-       \         /    \        \           \     -+</div><div class='add'>+ * |            |    LOAD FAIL &lt;--&lt;      \--&gt; TRANSFERRED     \     |</div><div class='add'>+ * |   upload   |                  \           /   \          /     |</div><div class='add'>+ * |            |                   \---------/     \--&gt; RUNNING    |</div><div class='add'>+ * +------------+---------------------------------------------------+</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * FIXME: Ported from the i915 and this is state machine is way too complicated.</div><div class='add'>+ * Circle back and simplify this.</div><div class='add'>+ */</div><div class='add'>+enum xe_uc_fw_status {</div><div class='add'>+	XE_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW */</div><div class='add'>+	XE_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done too early */</div><div class='add'>+	XE_UC_FIRMWARE_DISABLED, /* disabled */</div><div class='add'>+	XE_UC_FIRMWARE_SELECTED, /* selected the blob we want to load */</div><div class='add'>+	XE_UC_FIRMWARE_MISSING, /* blob not found on the system */</div><div class='add'>+	XE_UC_FIRMWARE_ERROR, /* invalid format or version */</div><div class='add'>+	XE_UC_FIRMWARE_AVAILABLE, /* blob found and copied in mem */</div><div class='add'>+	XE_UC_FIRMWARE_INIT_FAIL, /* failed to prepare fw objects for load */</div><div class='add'>+	XE_UC_FIRMWARE_LOADABLE, /* all fw-required objects are ready */</div><div class='add'>+	XE_UC_FIRMWARE_LOAD_FAIL, /* failed to xfer or init/auth the fw */</div><div class='add'>+	XE_UC_FIRMWARE_TRANSFERRED, /* dma xfer done */</div><div class='add'>+	XE_UC_FIRMWARE_RUNNING /* init/auth done */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_uc_fw_type {</div><div class='add'>+	XE_UC_FW_TYPE_GUC = 0,</div><div class='add'>+	XE_UC_FW_TYPE_HUC,</div><div class='add'>+	XE_UC_FW_TYPE_GSC,</div><div class='add'>+	XE_UC_FW_NUM_TYPES</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_uc_fw_version - Version for XE micro controller firmware</div><div class='add'>+ */</div><div class='add'>+struct xe_uc_fw_version {</div><div class='add'>+	/** @major: major version of the FW */</div><div class='add'>+	u16 major;</div><div class='add'>+	/** @minor: minor version of the FW */</div><div class='add'>+	u16 minor;</div><div class='add'>+	/** @patch: patch version of the FW */</div><div class='add'>+	u16 patch;</div><div class='add'>+	/** @build: build version of the FW (not always available) */</div><div class='add'>+	u16 build;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum xe_uc_fw_version_types {</div><div class='add'>+	XE_UC_FW_VER_RELEASE,</div><div class='add'>+	XE_UC_FW_VER_COMPATIBILITY,</div><div class='add'>+	XE_UC_FW_VER_TYPE_COUNT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_uc_fw - XE micro controller firmware</div><div class='add'>+ */</div><div class='add'>+struct xe_uc_fw {</div><div class='add'>+	/** @type: type uC firmware */</div><div class='add'>+	enum xe_uc_fw_type type;</div><div class='add'>+	union {</div><div class='add'>+		/** @status: firmware load status */</div><div class='add'>+		const enum xe_uc_fw_status status;</div><div class='add'>+		/**</div><div class='add'>+		 * @__status: private firmware load status - only to be used</div><div class='add'>+		 * by firmware laoding code</div><div class='add'>+		 */</div><div class='add'>+		enum xe_uc_fw_status __status;</div><div class='add'>+	};</div><div class='add'>+	/** @path: path to uC firmware */</div><div class='add'>+	const char *path;</div><div class='add'>+	/** @user_overridden: user provided path to uC firmware via modparam */</div><div class='add'>+	bool user_overridden;</div><div class='add'>+	/**</div><div class='add'>+	 * @full_ver_required: driver still under development and not ready</div><div class='add'>+	 * for backward-compatible firmware. To be used only for **new**</div><div class='add'>+	 * platforms, i.e. still under require_force_probe protection and not</div><div class='add'>+	 * supported by i915.</div><div class='add'>+	 */</div><div class='add'>+	bool full_ver_required;</div><div class='add'>+	/** @size: size of uC firmware including css header */</div><div class='add'>+	size_t size;</div><div class='add'>+</div><div class='add'>+	/** @bo: XE BO for uC firmware */</div><div class='add'>+	struct xe_bo *bo;</div><div class='add'>+</div><div class='add'>+	/** @has_gsc_headers: whether the FW image starts with GSC headers */</div><div class='add'>+	bool has_gsc_headers;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The firmware build process will generate a version header file with</div><div class='add'>+	 * major and minor version defined. The versions are built into CSS</div><div class='add'>+	 * header of firmware. The xe kernel driver set the minimal firmware</div><div class='add'>+	 * version required per platform.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	/** @versions: FW versions wanted and found */</div><div class='add'>+	struct {</div><div class='add'>+		/** @wanted: firmware version wanted by platform */</div><div class='add'>+		struct xe_uc_fw_version wanted;</div><div class='add'>+		/** @wanted_type: type of firmware version wanted (release vs compatibility) */</div><div class='add'>+		enum xe_uc_fw_version_types wanted_type;</div><div class='add'>+		/** @found: fw versions found in firmware blob */</div><div class='add'>+		struct xe_uc_fw_version found[XE_UC_FW_VER_TYPE_COUNT];</div><div class='add'>+	} versions;</div><div class='add'>+</div><div class='add'>+	/** @rsa_size: RSA size */</div><div class='add'>+	u32 rsa_size;</div><div class='add'>+	/** @ucode_size: micro kernel size */</div><div class='add'>+	u32 ucode_size;</div><div class='add'>+	/** @css_offset: offset within the blob at which the CSS is located */</div><div class='add'>+	u32 css_offset;</div><div class='add'>+</div><div class='add'>+	/** @private_data_size: size of private data found in uC css header */</div><div class='add'>+	u32 private_data_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_uc_types.h b/drivers/gpu/drm/xe/xe_uc_types.h<br/>new file mode 100644<br/>index 000000000000..9924e4484866<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_uc_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_uc_types.h</a></div><div class='hunk'>@@ -0,0 +1,28 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_UC_TYPES_H_</div><div class='add'>+#define _XE_UC_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include "xe_gsc_types.h"</div><div class='add'>+#include "xe_guc_types.h"</div><div class='add'>+#include "xe_huc_types.h"</div><div class='add'>+#include "xe_wopcm_types.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_uc - XE micro controllers</div><div class='add'>+ */</div><div class='add'>+struct xe_uc {</div><div class='add'>+	/** @guc: Graphics micro controller */</div><div class='add'>+	struct xe_guc guc;</div><div class='add'>+	/** @huc: HuC */</div><div class='add'>+	struct xe_huc huc;</div><div class='add'>+	/** @gsc: Graphics Security Controller */</div><div class='add'>+	struct xe_gsc gsc;</div><div class='add'>+	/** @wopcm: WOPCM */</div><div class='add'>+	struct xe_wopcm wopcm;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c<br/>new file mode 100644<br/>index 000000000000..10b6995fbf29<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_vm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm.c</a></div><div class='hunk'>@@ -0,0 +1,3212 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_vm.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-fence-array.h&gt;</div><div class='add'>+#include &lt;linux/nospec.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_exec.h&gt;</div><div class='add'>+#include &lt;drm/drm_print.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_execbuf_util.h&gt;</div><div class='add'>+#include &lt;drm/ttm/ttm_tt.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/kthread.h&gt;</div><div class='add'>+#include &lt;linux/mm.h&gt;</div><div class='add'>+#include &lt;linux/swap.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_assert.h"</div><div class='add'>+#include "xe_bo.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_drm_client.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_gt_pagefault.h"</div><div class='add'>+#include "xe_gt_tlb_invalidation.h"</div><div class='add'>+#include "xe_migrate.h"</div><div class='add'>+#include "xe_pat.h"</div><div class='add'>+#include "xe_pm.h"</div><div class='add'>+#include "xe_preempt_fence.h"</div><div class='add'>+#include "xe_pt.h"</div><div class='add'>+#include "xe_res_cursor.h"</div><div class='add'>+#include "xe_sync.h"</div><div class='add'>+#include "xe_trace.h"</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+#define TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+</div><div class='add'>+static struct drm_gem_object *xe_vm_obj(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;gpuvm.r_obj;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vma_userptr_check_repin() - Advisory check for repin needed</div><div class='add'>+ * @vma: The userptr vma</div><div class='add'>+ *</div><div class='add'>+ * Check if the userptr vma has been invalidated since last successful</div><div class='add'>+ * repin. The check is advisory only and can the function can be called</div><div class='add'>+ * without the vm-&gt;userptr.notifier_lock held. There is no guarantee that the</div><div class='add'>+ * vma userptr will remain valid after a lockless check, so typically</div><div class='add'>+ * the call needs to be followed by a proper check under the notifier_lock.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 if userptr vma is valid, -EAGAIN otherwise; repin recommended.</div><div class='add'>+ */</div><div class='add'>+int xe_vma_userptr_check_repin(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return mmu_interval_check_retry(&amp;vma-&gt;userptr.notifier,</div><div class='add'>+					vma-&gt;userptr.notifier_seq) ?</div><div class='add'>+		-EAGAIN : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vma_userptr_pin_pages(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	struct xe_device *xe = vm-&gt;xe;</div><div class='add'>+	const unsigned long num_pages = xe_vma_size(vma) &gt;&gt; PAGE_SHIFT;</div><div class='add'>+	struct page **pages;</div><div class='add'>+	bool in_kthread = !current-&gt;mm;</div><div class='add'>+	unsigned long notifier_seq;</div><div class='add'>+	int pinned, ret, i;</div><div class='add'>+	bool read_only = xe_vma_read_only(vma);</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	xe_assert(xe, xe_vma_is_userptr(vma));</div><div class='add'>+retry:</div><div class='add'>+	if (vma-&gt;gpuva.flags &amp; XE_VMA_DESTROYED)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	notifier_seq = mmu_interval_read_begin(&amp;vma-&gt;userptr.notifier);</div><div class='add'>+	if (notifier_seq == vma-&gt;userptr.notifier_seq)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	pages = kvmalloc_array(num_pages, sizeof(*pages), GFP_KERNEL);</div><div class='add'>+	if (!pages)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	if (vma-&gt;userptr.sg) {</div><div class='add'>+		dma_unmap_sgtable(xe-&gt;drm.dev,</div><div class='add'>+				  vma-&gt;userptr.sg,</div><div class='add'>+				  read_only ? DMA_TO_DEVICE :</div><div class='add'>+				  DMA_BIDIRECTIONAL, 0);</div><div class='add'>+		sg_free_table(vma-&gt;userptr.sg);</div><div class='add'>+		vma-&gt;userptr.sg = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pinned = ret = 0;</div><div class='add'>+	if (in_kthread) {</div><div class='add'>+		if (!mmget_not_zero(vma-&gt;userptr.notifier.mm)) {</div><div class='add'>+			ret = -EFAULT;</div><div class='add'>+			goto mm_closed;</div><div class='add'>+		}</div><div class='add'>+		kthread_use_mm(vma-&gt;userptr.notifier.mm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	while (pinned &lt; num_pages) {</div><div class='add'>+		ret = get_user_pages_fast(xe_vma_userptr(vma) +</div><div class='add'>+					  pinned * PAGE_SIZE,</div><div class='add'>+					  num_pages - pinned,</div><div class='add'>+					  read_only ? 0 : FOLL_WRITE,</div><div class='add'>+					  &amp;pages[pinned]);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			if (in_kthread)</div><div class='add'>+				ret = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pinned += ret;</div><div class='add'>+		ret = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (in_kthread) {</div><div class='add'>+		kthread_unuse_mm(vma-&gt;userptr.notifier.mm);</div><div class='add'>+		mmput(vma-&gt;userptr.notifier.mm);</div><div class='add'>+	}</div><div class='add'>+mm_closed:</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = sg_alloc_table_from_pages_segment(&amp;vma-&gt;userptr.sgt, pages,</div><div class='add'>+						pinned, 0,</div><div class='add'>+						(u64)pinned &lt;&lt; PAGE_SHIFT,</div><div class='add'>+						xe_sg_segment_size(xe-&gt;drm.dev),</div><div class='add'>+						GFP_KERNEL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		vma-&gt;userptr.sg = NULL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+	vma-&gt;userptr.sg = &amp;vma-&gt;userptr.sgt;</div><div class='add'>+</div><div class='add'>+	ret = dma_map_sgtable(xe-&gt;drm.dev, vma-&gt;userptr.sg,</div><div class='add'>+			      read_only ? DMA_TO_DEVICE :</div><div class='add'>+			      DMA_BIDIRECTIONAL,</div><div class='add'>+			      DMA_ATTR_SKIP_CPU_SYNC |</div><div class='add'>+			      DMA_ATTR_NO_KERNEL_MAPPING);</div><div class='add'>+	if (ret) {</div><div class='add'>+		sg_free_table(vma-&gt;userptr.sg);</div><div class='add'>+		vma-&gt;userptr.sg = NULL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pinned; ++i) {</div><div class='add'>+		if (!read_only) {</div><div class='add'>+			lock_page(pages[i]);</div><div class='add'>+			set_page_dirty(pages[i]);</div><div class='add'>+			unlock_page(pages[i]);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		mark_page_accessed(pages[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	release_pages(pages, pinned);</div><div class='add'>+	kvfree(pages);</div><div class='add'>+</div><div class='add'>+	if (!(ret &lt; 0)) {</div><div class='add'>+		vma-&gt;userptr.notifier_seq = notifier_seq;</div><div class='add'>+		if (xe_vma_userptr_check_repin(vma) == -EAGAIN)</div><div class='add'>+			goto retry;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret &lt; 0 ? ret : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool preempt_fences_waiting(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link) {</div><div class='add'>+		if (!q-&gt;compute.pfence ||</div><div class='add'>+		    (q-&gt;compute.pfence &amp;&amp; test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,</div><div class='add'>+						   &amp;q-&gt;compute.pfence-&gt;flags))) {</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void free_preempt_fences(struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct list_head *link, *next;</div><div class='add'>+</div><div class='add'>+	list_for_each_safe(link, next, list)</div><div class='add'>+		xe_preempt_fence_free(to_preempt_fence_from_link(link));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list,</div><div class='add'>+				unsigned int *count)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	if (*count &gt;= vm-&gt;preempt.num_exec_queues)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (; *count &lt; vm-&gt;preempt.num_exec_queues; ++(*count)) {</div><div class='add'>+		struct xe_preempt_fence *pfence = xe_preempt_fence_alloc();</div><div class='add'>+</div><div class='add'>+		if (IS_ERR(pfence))</div><div class='add'>+			return PTR_ERR(pfence);</div><div class='add'>+</div><div class='add'>+		list_move_tail(xe_preempt_fence_link(pfence), list);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wait_for_existing_preempt_fences(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link) {</div><div class='add'>+		if (q-&gt;compute.pfence) {</div><div class='add'>+			long timeout = dma_fence_wait(q-&gt;compute.pfence, false);</div><div class='add'>+</div><div class='add'>+			if (timeout &lt; 0)</div><div class='add'>+				return -ETIME;</div><div class='add'>+			dma_fence_put(q-&gt;compute.pfence);</div><div class='add'>+			q-&gt;compute.pfence = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool xe_vm_is_idle(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link) {</div><div class='add'>+		if (!xe_exec_queue_is_idle(q))</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list)</div><div class='add'>+{</div><div class='add'>+	struct list_head *link;</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link) {</div><div class='add'>+		struct dma_fence *fence;</div><div class='add'>+</div><div class='add'>+		link = list-&gt;next;</div><div class='add'>+		xe_assert(vm-&gt;xe, link != list);</div><div class='add'>+</div><div class='add'>+		fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link),</div><div class='add'>+					     q, q-&gt;compute.context,</div><div class='add'>+					     ++q-&gt;compute.seqno);</div><div class='add'>+		dma_fence_put(q-&gt;compute.pfence);</div><div class='add'>+		q-&gt;compute.pfence = fence;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!vm-&gt;preempt.num_exec_queues)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = xe_bo_lock(bo, true);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = dma_resv_reserve_fences(bo-&gt;ttm.base.resv, vm-&gt;preempt.num_exec_queues);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link)</div><div class='add'>+		if (q-&gt;compute.pfence) {</div><div class='add'>+			dma_resv_add_fence(bo-&gt;ttm.base.resv,</div><div class='add'>+					   q-&gt;compute.pfence,</div><div class='add'>+					   DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	xe_bo_unlock(bo);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void resume_and_reinstall_preempt_fences(struct xe_vm *vm,</div><div class='add'>+						struct drm_exec *exec)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link) {</div><div class='add'>+		q-&gt;ops-&gt;resume(q);</div><div class='add'>+</div><div class='add'>+		drm_gpuvm_resv_add_fence(&amp;vm-&gt;gpuvm, exec, q-&gt;compute.pfence,</div><div class='add'>+					 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct drm_gpuvm_exec vm_exec = {</div><div class='add'>+		.vm = &amp;vm-&gt;gpuvm,</div><div class='add'>+		.flags = DRM_EXEC_INTERRUPTIBLE_WAIT,</div><div class='add'>+		.num_fences = 1,</div><div class='add'>+	};</div><div class='add'>+	struct drm_exec *exec = &amp;vm_exec.exec;</div><div class='add'>+	struct dma_fence *pfence;</div><div class='add'>+	int err;</div><div class='add'>+	bool wait;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vm_in_preempt_fence_mode(vm));</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	err = drm_gpuvm_exec_lock(&amp;vm_exec);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_up_write;</div><div class='add'>+</div><div class='add'>+	pfence = xe_preempt_fence_create(q, q-&gt;compute.context,</div><div class='add'>+					 ++q-&gt;compute.seqno);</div><div class='add'>+	if (!pfence) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto out_fini;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	list_add(&amp;q-&gt;compute.link, &amp;vm-&gt;preempt.exec_queues);</div><div class='add'>+	++vm-&gt;preempt.num_exec_queues;</div><div class='add'>+	q-&gt;compute.pfence = pfence;</div><div class='add'>+</div><div class='add'>+	down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+	drm_gpuvm_resv_add_fence(&amp;vm-&gt;gpuvm, exec, pfence,</div><div class='add'>+				 DMA_RESV_USAGE_BOOKKEEP, DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check to see if a preemption on VM is in flight or userptr</div><div class='add'>+	 * invalidation, if so trigger this preempt fence to sync state with</div><div class='add'>+	 * other preempt fences on the VM.</div><div class='add'>+	 */</div><div class='add'>+	wait = __xe_vm_userptr_needs_repin(vm) || preempt_fences_waiting(vm);</div><div class='add'>+	if (wait)</div><div class='add'>+		dma_fence_enable_sw_signaling(pfence);</div><div class='add'>+</div><div class='add'>+	up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+out_fini:</div><div class='add'>+	drm_exec_fini(exec);</div><div class='add'>+out_up_write:</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_remove_compute_exec_queue() - Remove compute exec queue from VM</div><div class='add'>+ * @vm: The VM.</div><div class='add'>+ * @q: The exec_queue</div><div class='add'>+ */</div><div class='add'>+void xe_vm_remove_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	if (!xe_vm_in_preempt_fence_mode(vm))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	list_del(&amp;q-&gt;compute.link);</div><div class='add'>+	--vm-&gt;preempt.num_exec_queues;</div><div class='add'>+	if (q-&gt;compute.pfence) {</div><div class='add'>+		dma_fence_enable_sw_signaling(q-&gt;compute.pfence);</div><div class='add'>+		dma_fence_put(q-&gt;compute.pfence);</div><div class='add'>+		q-&gt;compute.pfence = NULL;</div><div class='add'>+	}</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __xe_vm_userptr_needs_repin() - Check whether the VM does have userptrs</div><div class='add'>+ * that need repinning.</div><div class='add'>+ * @vm: The VM.</div><div class='add'>+ *</div><div class='add'>+ * This function checks for whether the VM has userptrs that need repinning,</div><div class='add'>+ * and provides a release-type barrier on the userptr.notifier_lock after</div><div class='add'>+ * checking.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 if there are no userptrs needing repinning, -EAGAIN if there are.</div><div class='add'>+ */</div><div class='add'>+int __xe_vm_userptr_needs_repin(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+	return (list_empty(&amp;vm-&gt;userptr.repin_list) &amp;&amp;</div><div class='add'>+		list_empty(&amp;vm-&gt;userptr.invalidated)) ? 0 : -EAGAIN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define XE_VM_REBIND_RETRY_TIMEOUT_MS 1000</div><div class='add'>+</div><div class='add'>+static void xe_vm_kill(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	xe_vm_lock(vm, false);</div><div class='add'>+	vm-&gt;flags |= XE_VM_FLAG_BANNED;</div><div class='add'>+	trace_xe_vm_kill(vm);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(q, &amp;vm-&gt;preempt.exec_queues, compute.link)</div><div class='add'>+		q-&gt;ops-&gt;kill(q);</div><div class='add'>+	xe_vm_unlock(vm);</div><div class='add'>+</div><div class='add'>+	/* TODO: Inform user the VM is banned */</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_validate_should_retry() - Whether to retry after a validate error.</div><div class='add'>+ * @exec: The drm_exec object used for locking before validation.</div><div class='add'>+ * @err: The error returned from ttm_bo_validate().</div><div class='add'>+ * @end: A ktime_t cookie that should be set to 0 before first use and</div><div class='add'>+ * that should be reused on subsequent calls.</div><div class='add'>+ *</div><div class='add'>+ * With multiple active VMs, under memory pressure, it is possible that</div><div class='add'>+ * ttm_bo_validate() run into -EDEADLK and in such case returns -ENOMEM.</div><div class='add'>+ * Until ttm properly handles locking in such scenarios, best thing the</div><div class='add'>+ * driver can do is retry with a timeout. Check if that is necessary, and</div><div class='add'>+ * if so unlock the drm_exec's objects while keeping the ticket to prepare</div><div class='add'>+ * for a rerun.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if a retry after drm_exec_init() is recommended;</div><div class='add'>+ * false otherwise.</div><div class='add'>+ */</div><div class='add'>+bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end)</div><div class='add'>+{</div><div class='add'>+	ktime_t cur;</div><div class='add'>+</div><div class='add'>+	if (err != -ENOMEM)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	cur = ktime_get();</div><div class='add'>+	*end = *end ? : ktime_add_ms(cur, XE_VM_REBIND_RETRY_TIMEOUT_MS);</div><div class='add'>+	if (!ktime_before(cur, *end))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	msleep(20);</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_gpuvm_validate(struct drm_gpuvm_bo *vm_bo, struct drm_exec *exec)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = gpuvm_to_vm(vm_bo-&gt;vm);</div><div class='add'>+	struct drm_gpuva *gpuva;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	drm_gpuvm_bo_for_each_va(gpuva, vm_bo)</div><div class='add'>+		list_move_tail(&amp;gpuva_to_vma(gpuva)-&gt;combined_links.rebind,</div><div class='add'>+			       &amp;vm-&gt;rebind_list);</div><div class='add'>+</div><div class='add'>+	ret = xe_bo_validate(gem_to_xe_bo(vm_bo-&gt;obj), vm, false);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	vm_bo-&gt;evicted = false;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_preempt_work_begin(struct drm_exec *exec, struct xe_vm *vm,</div><div class='add'>+				 bool *done)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * 1 fence for each preempt fence plus a fence for each tile from a</div><div class='add'>+	 * possible rebind</div><div class='add'>+	 */</div><div class='add'>+	err = drm_gpuvm_prepare_vm(&amp;vm-&gt;gpuvm, exec, vm-&gt;preempt.num_exec_queues +</div><div class='add'>+				   vm-&gt;xe-&gt;info.tile_count);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (xe_vm_is_idle(vm)) {</div><div class='add'>+		vm-&gt;preempt.rebind_deactivated = true;</div><div class='add'>+		*done = true;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!preempt_fences_waiting(vm)) {</div><div class='add'>+		*done = true;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = drm_gpuvm_prepare_objects(&amp;vm-&gt;gpuvm, exec, vm-&gt;preempt.num_exec_queues);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = wait_for_existing_preempt_fences(vm);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return drm_gpuvm_validate(&amp;vm-&gt;gpuvm, exec);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void preempt_rebind_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = container_of(w, struct xe_vm, preempt.rebind_work);</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct dma_fence *rebind_fence;</div><div class='add'>+	unsigned int fence_count = 0;</div><div class='add'>+	LIST_HEAD(preempt_fences);</div><div class='add'>+	ktime_t end = 0;</div><div class='add'>+	int err = 0;</div><div class='add'>+	long wait;</div><div class='add'>+	int __maybe_unused tries = 0;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vm_in_preempt_fence_mode(vm));</div><div class='add'>+	trace_xe_vm_rebind_worker_enter(vm);</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (xe_vm_is_closed_or_banned(vm)) {</div><div class='add'>+		up_write(&amp;vm-&gt;lock);</div><div class='add'>+		trace_xe_vm_rebind_worker_exit(vm);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+retry:</div><div class='add'>+	if (xe_vm_userptr_check_repin(vm)) {</div><div class='add'>+		err = xe_vm_userptr_pin(vm);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_unlock_outer;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		bool done = false;</div><div class='add'>+</div><div class='add'>+		err = xe_preempt_work_begin(&amp;exec, vm, &amp;done);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (err || done) {</div><div class='add'>+			drm_exec_fini(&amp;exec);</div><div class='add'>+			if (err &amp;&amp; xe_vm_validate_should_retry(&amp;exec, err, &amp;end))</div><div class='add'>+				err = -EAGAIN;</div><div class='add'>+</div><div class='add'>+			goto out_unlock_outer;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = alloc_preempt_fences(vm, &amp;preempt_fences, &amp;fence_count);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	rebind_fence = xe_vm_rebind(vm, true);</div><div class='add'>+	if (IS_ERR(rebind_fence)) {</div><div class='add'>+		err = PTR_ERR(rebind_fence);</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (rebind_fence) {</div><div class='add'>+		dma_fence_wait(rebind_fence, false);</div><div class='add'>+		dma_fence_put(rebind_fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Wait on munmap style VM unbinds */</div><div class='add'>+	wait = dma_resv_wait_timeout(xe_vm_resv(vm),</div><div class='add'>+				     DMA_RESV_USAGE_KERNEL,</div><div class='add'>+				     false, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+	if (wait &lt;= 0) {</div><div class='add'>+		err = -ETIME;</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#define retry_required(__tries, __vm) \</div><div class='add'>+	(IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT) ? \</div><div class='add'>+	(!(__tries)++ || __xe_vm_userptr_needs_repin(__vm)) : \</div><div class='add'>+	__xe_vm_userptr_needs_repin(__vm))</div><div class='add'>+</div><div class='add'>+	down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	if (retry_required(tries, vm)) {</div><div class='add'>+		up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		err = -EAGAIN;</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+#undef retry_required</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;vm-&gt;xe-&gt;ttm.lru_lock);</div><div class='add'>+	ttm_lru_bulk_move_tail(&amp;vm-&gt;lru_bulk_move);</div><div class='add'>+	spin_unlock(&amp;vm-&gt;xe-&gt;ttm.lru_lock);</div><div class='add'>+</div><div class='add'>+	/* Point of no return. */</div><div class='add'>+	arm_preempt_fences(vm, &amp;preempt_fences);</div><div class='add'>+	resume_and_reinstall_preempt_fences(vm, &amp;exec);</div><div class='add'>+	up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+out_unlock_outer:</div><div class='add'>+	if (err == -EAGAIN) {</div><div class='add'>+		trace_xe_vm_rebind_worker_retry(vm);</div><div class='add'>+		goto retry;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (err) {</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "VM worker error: %d\n", err);</div><div class='add'>+		xe_vm_kill(vm);</div><div class='add'>+	}</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	free_preempt_fences(&amp;preempt_fences);</div><div class='add'>+</div><div class='add'>+	trace_xe_vm_rebind_worker_exit(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool vma_userptr_invalidate(struct mmu_interval_notifier *mni,</div><div class='add'>+				   const struct mmu_notifier_range *range,</div><div class='add'>+				   unsigned long cur_seq)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma = container_of(mni, struct xe_vma, userptr.notifier);</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	struct dma_resv_iter cursor;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	long err;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vma_is_userptr(vma));</div><div class='add'>+	trace_xe_vma_userptr_invalidate(vma);</div><div class='add'>+</div><div class='add'>+	if (!mmu_notifier_range_blockable(range))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	mmu_interval_set_seq(mni, cur_seq);</div><div class='add'>+</div><div class='add'>+	/* No need to stop gpu access if the userptr is not yet bound. */</div><div class='add'>+	if (!vma-&gt;userptr.initial_bind) {</div><div class='add'>+		up_write(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Tell exec and rebind worker they need to repin and rebind this</div><div class='add'>+	 * userptr.</div><div class='add'>+	 */</div><div class='add'>+	if (!xe_vm_in_fault_mode(vm) &amp;&amp;</div><div class='add'>+	    !(vma-&gt;gpuva.flags &amp; XE_VMA_DESTROYED) &amp;&amp; vma-&gt;tile_present) {</div><div class='add'>+		spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		list_move_tail(&amp;vma-&gt;userptr.invalidate_link,</div><div class='add'>+			       &amp;vm-&gt;userptr.invalidated);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	up_write(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Preempt fences turn into schedule disables, pipeline these.</div><div class='add'>+	 * Note that even in fault mode, we need to wait for binds and</div><div class='add'>+	 * unbinds to complete, and those are attached as BOOKMARK fences</div><div class='add'>+	 * to the vm.</div><div class='add'>+	 */</div><div class='add'>+	dma_resv_iter_begin(&amp;cursor, xe_vm_resv(vm),</div><div class='add'>+			    DMA_RESV_USAGE_BOOKKEEP);</div><div class='add'>+	dma_resv_for_each_fence_unlocked(&amp;cursor, fence)</div><div class='add'>+		dma_fence_enable_sw_signaling(fence);</div><div class='add'>+	dma_resv_iter_end(&amp;cursor);</div><div class='add'>+</div><div class='add'>+	err = dma_resv_wait_timeout(xe_vm_resv(vm),</div><div class='add'>+				    DMA_RESV_USAGE_BOOKKEEP,</div><div class='add'>+				    false, MAX_SCHEDULE_TIMEOUT);</div><div class='add'>+	XE_WARN_ON(err &lt;= 0);</div><div class='add'>+</div><div class='add'>+	if (xe_vm_in_fault_mode(vm)) {</div><div class='add'>+		err = xe_vm_invalidate_vma(vma);</div><div class='add'>+		XE_WARN_ON(err);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	trace_xe_vma_userptr_invalidate_complete(vma);</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mmu_interval_notifier_ops vma_userptr_notifier_ops = {</div><div class='add'>+	.invalidate = vma_userptr_invalidate,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int xe_vm_userptr_pin(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma, *next;</div><div class='add'>+	int err = 0;</div><div class='add'>+	LIST_HEAD(tmp_evict);</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Collect invalidated userptrs */</div><div class='add'>+	spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+	list_for_each_entry_safe(vma, next, &amp;vm-&gt;userptr.invalidated,</div><div class='add'>+				 userptr.invalidate_link) {</div><div class='add'>+		list_del_init(&amp;vma-&gt;userptr.invalidate_link);</div><div class='add'>+		list_move_tail(&amp;vma-&gt;combined_links.userptr,</div><div class='add'>+			       &amp;vm-&gt;userptr.repin_list);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+</div><div class='add'>+	/* Pin and move to temporary list */</div><div class='add'>+	list_for_each_entry_safe(vma, next, &amp;vm-&gt;userptr.repin_list,</div><div class='add'>+				 combined_links.userptr) {</div><div class='add'>+		err = xe_vma_userptr_pin_pages(vma);</div><div class='add'>+		if (err &lt; 0)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		list_move_tail(&amp;vma-&gt;combined_links.userptr, &amp;vm-&gt;rebind_list);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_userptr_check_repin() - Check whether the VM might have userptrs</div><div class='add'>+ * that need repinning.</div><div class='add'>+ * @vm: The VM.</div><div class='add'>+ *</div><div class='add'>+ * This function does an advisory check for whether the VM has userptrs that</div><div class='add'>+ * need repinning.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 if there are no indications of userptrs needing repinning,</div><div class='add'>+ * -EAGAIN if there are.</div><div class='add'>+ */</div><div class='add'>+int xe_vm_userptr_check_repin(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return (list_empty_careful(&amp;vm-&gt;userptr.repin_list) &amp;&amp;</div><div class='add'>+		list_empty_careful(&amp;vm-&gt;userptr.invalidated)) ? 0 : -EAGAIN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+	       struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+	       bool first_op, bool last_op);</div><div class='add'>+</div><div class='add'>+struct dma_fence *xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='add'>+	struct xe_vma *vma, *next;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	if (xe_vm_in_lr_mode(vm) &amp;&amp; !rebind_worker)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	list_for_each_entry_safe(vma, next, &amp;vm-&gt;rebind_list,</div><div class='add'>+				 combined_links.rebind) {</div><div class='add'>+		xe_assert(vm-&gt;xe, vma-&gt;tile_present);</div><div class='add'>+</div><div class='add'>+		list_del_init(&amp;vma-&gt;combined_links.rebind);</div><div class='add'>+		dma_fence_put(fence);</div><div class='add'>+		if (rebind_worker)</div><div class='add'>+			trace_xe_vma_rebind_worker(vma);</div><div class='add'>+		else</div><div class='add'>+			trace_xe_vma_rebind_exec(vma);</div><div class='add'>+		fence = xe_vm_bind_vma(vma, NULL, NULL, 0, false, false);</div><div class='add'>+		if (IS_ERR(fence))</div><div class='add'>+			return fence;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define VMA_CREATE_FLAG_READ_ONLY	BIT(0)</div><div class='add'>+#define VMA_CREATE_FLAG_IS_NULL		BIT(1)</div><div class='add'>+</div><div class='add'>+static struct xe_vma *xe_vma_create(struct xe_vm *vm,</div><div class='add'>+				    struct xe_bo *bo,</div><div class='add'>+				    u64 bo_offset_or_userptr,</div><div class='add'>+				    u64 start, u64 end,</div><div class='add'>+				    u16 pat_index, unsigned int flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u8 id;</div><div class='add'>+	bool read_only = (flags &amp; VMA_CREATE_FLAG_READ_ONLY);</div><div class='add'>+	bool is_null = (flags &amp; VMA_CREATE_FLAG_IS_NULL);</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, start &lt; end);</div><div class='add'>+	xe_assert(vm-&gt;xe, end &lt; vm-&gt;size);</div><div class='add'>+</div><div class='add'>+	if (!bo &amp;&amp; !is_null)	/* userptr */</div><div class='add'>+		vma = kzalloc(sizeof(*vma), GFP_KERNEL);</div><div class='add'>+	else</div><div class='add'>+		vma = kzalloc(sizeof(*vma) - sizeof(struct xe_userptr),</div><div class='add'>+			      GFP_KERNEL);</div><div class='add'>+	if (!vma) {</div><div class='add'>+		vma = ERR_PTR(-ENOMEM);</div><div class='add'>+		return vma;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vma-&gt;combined_links.rebind);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vma-&gt;gpuva.gem.entry);</div><div class='add'>+	vma-&gt;gpuva.vm = &amp;vm-&gt;gpuvm;</div><div class='add'>+	vma-&gt;gpuva.va.addr = start;</div><div class='add'>+	vma-&gt;gpuva.va.range = end - start + 1;</div><div class='add'>+	if (read_only)</div><div class='add'>+		vma-&gt;gpuva.flags |= XE_VMA_READ_ONLY;</div><div class='add'>+	if (is_null)</div><div class='add'>+		vma-&gt;gpuva.flags |= DRM_GPUVA_SPARSE;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, vm-&gt;xe, id)</div><div class='add'>+		vma-&gt;tile_mask |= 0x1 &lt;&lt; id;</div><div class='add'>+</div><div class='add'>+	if (GRAPHICS_VER(vm-&gt;xe) &gt;= 20 || vm-&gt;xe-&gt;info.platform == XE_PVC)</div><div class='add'>+		vma-&gt;gpuva.flags |= XE_VMA_ATOMIC_PTE_BIT;</div><div class='add'>+</div><div class='add'>+	vma-&gt;pat_index = pat_index;</div><div class='add'>+</div><div class='add'>+	if (bo) {</div><div class='add'>+		struct drm_gpuvm_bo *vm_bo;</div><div class='add'>+</div><div class='add'>+		xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+		vm_bo = drm_gpuvm_bo_obtain(vma-&gt;gpuva.vm, &amp;bo-&gt;ttm.base);</div><div class='add'>+		if (IS_ERR(vm_bo)) {</div><div class='add'>+			kfree(vma);</div><div class='add'>+			return ERR_CAST(vm_bo);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_gpuvm_bo_extobj_add(vm_bo);</div><div class='add'>+		drm_gem_object_get(&amp;bo-&gt;ttm.base);</div><div class='add'>+		vma-&gt;gpuva.gem.obj = &amp;bo-&gt;ttm.base;</div><div class='add'>+		vma-&gt;gpuva.gem.offset = bo_offset_or_userptr;</div><div class='add'>+		drm_gpuva_link(&amp;vma-&gt;gpuva, vm_bo);</div><div class='add'>+		drm_gpuvm_bo_put(vm_bo);</div><div class='add'>+	} else /* userptr or null */ {</div><div class='add'>+		if (!is_null) {</div><div class='add'>+			u64 size = end - start + 1;</div><div class='add'>+			int err;</div><div class='add'>+</div><div class='add'>+			INIT_LIST_HEAD(&amp;vma-&gt;userptr.invalidate_link);</div><div class='add'>+			vma-&gt;gpuva.gem.offset = bo_offset_or_userptr;</div><div class='add'>+</div><div class='add'>+			err = mmu_interval_notifier_insert(&amp;vma-&gt;userptr.notifier,</div><div class='add'>+							   current-&gt;mm,</div><div class='add'>+							   xe_vma_userptr(vma), size,</div><div class='add'>+							   &amp;vma_userptr_notifier_ops);</div><div class='add'>+			if (err) {</div><div class='add'>+				kfree(vma);</div><div class='add'>+				vma = ERR_PTR(err);</div><div class='add'>+				return vma;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			vma-&gt;userptr.notifier_seq = LONG_MAX;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_vm_get(vm);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return vma;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vma_destroy_late(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	struct xe_device *xe = vm-&gt;xe;</div><div class='add'>+	bool read_only = xe_vma_read_only(vma);</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma)) {</div><div class='add'>+		if (vma-&gt;userptr.sg) {</div><div class='add'>+			dma_unmap_sgtable(xe-&gt;drm.dev,</div><div class='add'>+					  vma-&gt;userptr.sg,</div><div class='add'>+					  read_only ? DMA_TO_DEVICE :</div><div class='add'>+					  DMA_BIDIRECTIONAL, 0);</div><div class='add'>+			sg_free_table(vma-&gt;userptr.sg);</div><div class='add'>+			vma-&gt;userptr.sg = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Since userptr pages are not pinned, we can't remove</div><div class='add'>+		 * the notifer until we're sure the GPU is not accessing</div><div class='add'>+		 * them anymore</div><div class='add'>+		 */</div><div class='add'>+		mmu_interval_notifier_remove(&amp;vma-&gt;userptr.notifier);</div><div class='add'>+		xe_vm_put(vm);</div><div class='add'>+	} else if (xe_vma_is_null(vma)) {</div><div class='add'>+		xe_vm_put(vm);</div><div class='add'>+	} else {</div><div class='add'>+		xe_bo_put(xe_vma_bo(vma));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kfree(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vma_destroy_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma =</div><div class='add'>+		container_of(w, struct xe_vma, destroy_work);</div><div class='add'>+</div><div class='add'>+	xe_vma_destroy_late(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vma_destroy_cb(struct dma_fence *fence,</div><div class='add'>+			   struct dma_fence_cb *cb)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma = container_of(cb, struct xe_vma, destroy_cb);</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;vma-&gt;destroy_work, vma_destroy_work_func);</div><div class='add'>+	queue_work(system_unbound_wq, &amp;vma-&gt;destroy_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vma_destroy(struct xe_vma *vma, struct dma_fence *fence)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+	xe_assert(vm-&gt;xe, list_empty(&amp;vma-&gt;combined_links.destroy));</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma)) {</div><div class='add'>+		xe_assert(vm-&gt;xe, vma-&gt;gpuva.flags &amp; XE_VMA_DESTROYED);</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+		list_del(&amp;vma-&gt;userptr.invalidate_link);</div><div class='add'>+		spin_unlock(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+	} else if (!xe_vma_is_null(vma)) {</div><div class='add'>+		xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+</div><div class='add'>+		drm_gpuva_unlink(&amp;vma-&gt;gpuva);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	if (fence) {</div><div class='add'>+		int ret = dma_fence_add_callback(fence, &amp;vma-&gt;destroy_cb,</div><div class='add'>+						 vma_destroy_cb);</div><div class='add'>+</div><div class='add'>+		if (ret) {</div><div class='add'>+			XE_WARN_ON(ret != -ENOENT);</div><div class='add'>+			xe_vma_destroy_late(vma);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		xe_vma_destroy_late(vma);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_prepare_vma() - drm_exec utility to lock a vma</div><div class='add'>+ * @exec: The drm_exec object we're currently locking for.</div><div class='add'>+ * @vma: The vma for witch we want to lock the vm resv and any attached</div><div class='add'>+ * object's resv.</div><div class='add'>+ * @num_shared: The number of dma-fence slots to pre-allocate in the</div><div class='add'>+ * objects' reservation objects.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error. In particular</div><div class='add'>+ * may return -EDEADLK on WW transaction contention and -EINTR if</div><div class='add'>+ * an interruptible wait is terminated by a signal.</div><div class='add'>+ */</div><div class='add'>+int xe_vm_prepare_vma(struct drm_exec *exec, struct xe_vma *vma,</div><div class='add'>+		      unsigned int num_shared)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	struct xe_bo *bo = xe_vma_bo(vma);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!vm);</div><div class='add'>+	err = drm_exec_prepare_obj(exec, xe_vm_obj(vm), num_shared);</div><div class='add'>+	if (!err &amp;&amp; bo &amp;&amp; !bo-&gt;vm)</div><div class='add'>+		err = drm_exec_prepare_obj(exec, &amp;bo-&gt;ttm.base, num_shared);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vma_destroy_unlocked(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	drm_exec_init(&amp;exec, 0, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		err = xe_vm_prepare_vma(&amp;exec, vma, 0);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (XE_WARN_ON(err))</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_vma_destroy(vma, NULL);</div><div class='add'>+</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_vma *</div><div class='add'>+xe_vm_find_overlapping_vma(struct xe_vm *vm, u64 start, u64 range)</div><div class='add'>+{</div><div class='add'>+	struct drm_gpuva *gpuva;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (xe_vm_is_closed_or_banned(vm))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, start + range &lt;= vm-&gt;size);</div><div class='add'>+</div><div class='add'>+	gpuva = drm_gpuva_find_first(&amp;vm-&gt;gpuvm, start, range);</div><div class='add'>+</div><div class='add'>+	return gpuva ? gpuva_to_vma(gpuva) : NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_vm_insert_vma(struct xe_vm *vm, struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vma_vm(vma) == vm);</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	err = drm_gpuva_insert(&amp;vm-&gt;gpuvm, &amp;vma-&gt;gpuva);</div><div class='add'>+	XE_WARN_ON(err);	/* Shouldn't be possible */</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_remove_vma(struct xe_vm *vm, struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vma_vm(vma) == vm);</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	drm_gpuva_remove(&amp;vma-&gt;gpuva);</div><div class='add'>+	if (vm-&gt;usm.last_fault_vma == vma)</div><div class='add'>+		vm-&gt;usm.last_fault_vma = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct drm_gpuva_op *xe_vm_op_alloc(void)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma_op *op;</div><div class='add'>+</div><div class='add'>+	op = kzalloc(sizeof(*op), GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	if (unlikely(!op))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return &amp;op-&gt;base;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_free(struct drm_gpuvm *gpuvm);</div><div class='add'>+</div><div class='add'>+static struct drm_gpuvm_ops gpuvm_ops = {</div><div class='add'>+	.op_alloc = xe_vm_op_alloc,</div><div class='add'>+	.vm_bo_validate = xe_gpuvm_validate,</div><div class='add'>+	.vm_free = xe_vm_free,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u64 pde_encode_pat_index(struct xe_device *xe, u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	u64 pte = 0;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(0))</div><div class='add'>+		pte |= XE_PPGTT_PTE_PAT0;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(1))</div><div class='add'>+		pte |= XE_PPGTT_PTE_PAT1;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index,</div><div class='add'>+				u32 pt_level)</div><div class='add'>+{</div><div class='add'>+	u64 pte = 0;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(0))</div><div class='add'>+		pte |= XE_PPGTT_PTE_PAT0;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(1))</div><div class='add'>+		pte |= XE_PPGTT_PTE_PAT1;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(2)) {</div><div class='add'>+		if (pt_level)</div><div class='add'>+			pte |= XE_PPGTT_PDE_PDPE_PAT2;</div><div class='add'>+		else</div><div class='add'>+			pte |= XE_PPGTT_PTE_PAT2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; BIT(3))</div><div class='add'>+		pte |= XELPG_PPGTT_PTE_PAT3;</div><div class='add'>+</div><div class='add'>+	if (pat_index &amp; (BIT(4)))</div><div class='add'>+		pte |= XE2_PPGTT_PTE_PAT4;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 pte_encode_ps(u32 pt_level)</div><div class='add'>+{</div><div class='add'>+	XE_WARN_ON(pt_level &gt; MAX_HUGEPTE_LEVEL);</div><div class='add'>+</div><div class='add'>+	if (pt_level == 1)</div><div class='add'>+		return XE_PDE_PS_2M;</div><div class='add'>+	else if (pt_level == 2)</div><div class='add'>+		return XE_PDPE_PS_1G;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xelp_pde_encode_bo(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+			      const u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	u64 pde;</div><div class='add'>+</div><div class='add'>+	pde = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);</div><div class='add'>+	pde |= XE_PAGE_PRESENT | XE_PAGE_RW;</div><div class='add'>+	pde |= pde_encode_pat_index(xe, pat_index);</div><div class='add'>+</div><div class='add'>+	return pde;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xelp_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,</div><div class='add'>+			      u16 pat_index, u32 pt_level)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_bo_device(bo);</div><div class='add'>+	u64 pte;</div><div class='add'>+</div><div class='add'>+	pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);</div><div class='add'>+	pte |= XE_PAGE_PRESENT | XE_PAGE_RW;</div><div class='add'>+	pte |= pte_encode_pat_index(xe, pat_index, pt_level);</div><div class='add'>+	pte |= pte_encode_ps(pt_level);</div><div class='add'>+</div><div class='add'>+	if (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo))</div><div class='add'>+		pte |= XE_PPGTT_PTE_DM;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma,</div><div class='add'>+			       u16 pat_index, u32 pt_level)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_vma_vm(vma)-&gt;xe;</div><div class='add'>+</div><div class='add'>+	pte |= XE_PAGE_PRESENT;</div><div class='add'>+</div><div class='add'>+	if (likely(!xe_vma_read_only(vma)))</div><div class='add'>+		pte |= XE_PAGE_RW;</div><div class='add'>+</div><div class='add'>+	pte |= pte_encode_pat_index(xe, pat_index, pt_level);</div><div class='add'>+	pte |= pte_encode_ps(pt_level);</div><div class='add'>+</div><div class='add'>+	if (unlikely(xe_vma_is_null(vma)))</div><div class='add'>+		pte |= XE_PTE_NULL;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xelp_pte_encode_addr(struct xe_device *xe, u64 addr,</div><div class='add'>+				u16 pat_index,</div><div class='add'>+				u32 pt_level, bool devmem, u64 flags)</div><div class='add'>+{</div><div class='add'>+	u64 pte;</div><div class='add'>+</div><div class='add'>+	/* Avoid passing random bits directly as flags */</div><div class='add'>+	xe_assert(xe, !(flags &amp; ~XE_PTE_PS64));</div><div class='add'>+</div><div class='add'>+	pte = addr;</div><div class='add'>+	pte |= XE_PAGE_PRESENT | XE_PAGE_RW;</div><div class='add'>+	pte |= pte_encode_pat_index(xe, pat_index, pt_level);</div><div class='add'>+	pte |= pte_encode_ps(pt_level);</div><div class='add'>+</div><div class='add'>+	if (devmem)</div><div class='add'>+		pte |= XE_PPGTT_PTE_DM;</div><div class='add'>+</div><div class='add'>+	pte |= flags;</div><div class='add'>+</div><div class='add'>+	return pte;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xe_pt_ops xelp_pt_ops = {</div><div class='add'>+	.pte_encode_bo = xelp_pte_encode_bo,</div><div class='add'>+	.pte_encode_vma = xelp_pte_encode_vma,</div><div class='add'>+	.pte_encode_addr = xelp_pte_encode_addr,</div><div class='add'>+	.pde_encode_bo = xelp_pde_encode_bo,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void vm_destroy_work_func(struct work_struct *w);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_create_scratch() - Setup a scratch memory pagetable tree for the</div><div class='add'>+ * given tile and vm.</div><div class='add'>+ * @xe: xe device.</div><div class='add'>+ * @tile: tile to set up for.</div><div class='add'>+ * @vm: vm to set up for.</div><div class='add'>+ *</div><div class='add'>+ * Sets up a pagetable tree with one page-table per level and a single</div><div class='add'>+ * leaf PTE. All pagetable entries point to the single page-table or,</div><div class='add'>+ * for MAX_HUGEPTE_LEVEL, a NULL huge PTE returning 0 on read and</div><div class='add'>+ * writes become NOPs.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, negative error code on error.</div><div class='add'>+ */</div><div class='add'>+static int xe_vm_create_scratch(struct xe_device *xe, struct xe_tile *tile,</div><div class='add'>+				struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	u8 id = tile-&gt;id;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = MAX_HUGEPTE_LEVEL; i &lt; vm-&gt;pt_root[id]-&gt;level; i++) {</div><div class='add'>+		vm-&gt;scratch_pt[id][i] = xe_pt_create(vm, tile, i);</div><div class='add'>+		if (IS_ERR(vm-&gt;scratch_pt[id][i]))</div><div class='add'>+			return PTR_ERR(vm-&gt;scratch_pt[id][i]);</div><div class='add'>+</div><div class='add'>+		xe_pt_populate_empty(tile, vm, vm-&gt;scratch_pt[id][i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_free_scratch(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	if (!xe_vm_has_scratch(vm))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, vm-&gt;xe, id) {</div><div class='add'>+		u32 i;</div><div class='add'>+</div><div class='add'>+		if (!vm-&gt;pt_root[id])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (i = MAX_HUGEPTE_LEVEL; i &lt; vm-&gt;pt_root[id]-&gt;level; ++i)</div><div class='add'>+			if (vm-&gt;scratch_pt[id][i])</div><div class='add'>+				xe_pt_destroy(vm-&gt;scratch_pt[id][i], vm-&gt;flags, NULL);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *vm_resv_obj;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	int err, number_tiles = 0;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	vm = kzalloc(sizeof(*vm), GFP_KERNEL);</div><div class='add'>+	if (!vm)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	vm-&gt;xe = xe;</div><div class='add'>+</div><div class='add'>+	vm-&gt;size = 1ull &lt;&lt; xe-&gt;info.va_bits;</div><div class='add'>+</div><div class='add'>+	vm-&gt;flags = flags;</div><div class='add'>+</div><div class='add'>+	init_rwsem(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vm-&gt;rebind_list);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vm-&gt;userptr.repin_list);</div><div class='add'>+	INIT_LIST_HEAD(&amp;vm-&gt;userptr.invalidated);</div><div class='add'>+	init_rwsem(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	spin_lock_init(&amp;vm-&gt;userptr.invalidated_lock);</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;vm-&gt;destroy_work, vm_destroy_work_func);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;vm-&gt;preempt.exec_queues);</div><div class='add'>+	vm-&gt;preempt.min_run_period_ms = 10;	/* FIXME: Wire up to uAPI */</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_range_fence_tree_init(&amp;vm-&gt;rftree[id]);</div><div class='add'>+</div><div class='add'>+	vm-&gt;pt_ops = &amp;xelp_pt_ops;</div><div class='add'>+</div><div class='add'>+	if (!(flags &amp; XE_VM_FLAG_MIGRATION))</div><div class='add'>+		xe_device_mem_access_get(xe);</div><div class='add'>+</div><div class='add'>+	vm_resv_obj = drm_gpuvm_resv_object_alloc(&amp;xe-&gt;drm);</div><div class='add'>+	if (!vm_resv_obj) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto err_no_resv;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_gpuvm_init(&amp;vm-&gt;gpuvm, "Xe VM", DRM_GPUVM_RESV_PROTECTED, &amp;xe-&gt;drm,</div><div class='add'>+		       vm_resv_obj, 0, vm-&gt;size, 0, 0, &amp;gpuvm_ops);</div><div class='add'>+</div><div class='add'>+	drm_gem_object_put(vm_resv_obj);</div><div class='add'>+</div><div class='add'>+	err = dma_resv_lock_interruptible(xe_vm_resv(vm), NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_close;</div><div class='add'>+</div><div class='add'>+	if (IS_DGFX(xe) &amp;&amp; xe-&gt;info.vram_flags &amp; XE_VRAM_FLAGS_NEED64K)</div><div class='add'>+		vm-&gt;flags |= XE_VM_FLAG_64K;</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (flags &amp; XE_VM_FLAG_MIGRATION &amp;&amp;</div><div class='add'>+		    tile-&gt;id != XE_VM_FLAG_TILE_ID(flags))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vm-&gt;pt_root[id] = xe_pt_create(vm, tile, xe-&gt;info.vm_max_level);</div><div class='add'>+		if (IS_ERR(vm-&gt;pt_root[id])) {</div><div class='add'>+			err = PTR_ERR(vm-&gt;pt_root[id]);</div><div class='add'>+			vm-&gt;pt_root[id] = NULL;</div><div class='add'>+			goto err_unlock_close;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe_vm_has_scratch(vm)) {</div><div class='add'>+		for_each_tile(tile, xe, id) {</div><div class='add'>+			if (!vm-&gt;pt_root[id])</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			err = xe_vm_create_scratch(xe, tile, vm);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_unlock_close;</div><div class='add'>+		}</div><div class='add'>+		vm-&gt;batch_invalidate_tlb = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (flags &amp; XE_VM_FLAG_LR_MODE) {</div><div class='add'>+		INIT_WORK(&amp;vm-&gt;preempt.rebind_work, preempt_rebind_work_func);</div><div class='add'>+		vm-&gt;flags |= XE_VM_FLAG_LR_MODE;</div><div class='add'>+		vm-&gt;batch_invalidate_tlb = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Fill pt_root after allocating scratch tables */</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (!vm-&gt;pt_root[id])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		xe_pt_populate_empty(tile, vm, vm-&gt;pt_root[id]);</div><div class='add'>+	}</div><div class='add'>+	dma_resv_unlock(xe_vm_resv(vm));</div><div class='add'>+</div><div class='add'>+	/* Kernel migration VM shouldn't have a circular loop.. */</div><div class='add'>+	if (!(flags &amp; XE_VM_FLAG_MIGRATION)) {</div><div class='add'>+		for_each_tile(tile, xe, id) {</div><div class='add'>+			struct xe_gt *gt = tile-&gt;primary_gt;</div><div class='add'>+			struct xe_vm *migrate_vm;</div><div class='add'>+			struct xe_exec_queue *q;</div><div class='add'>+			u32 create_flags = EXEC_QUEUE_FLAG_VM;</div><div class='add'>+</div><div class='add'>+			if (!vm-&gt;pt_root[id])</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			migrate_vm = xe_migrate_get_vm(tile-&gt;migrate);</div><div class='add'>+			q = xe_exec_queue_create_class(xe, gt, migrate_vm,</div><div class='add'>+						       XE_ENGINE_CLASS_COPY,</div><div class='add'>+						       create_flags);</div><div class='add'>+			xe_vm_put(migrate_vm);</div><div class='add'>+			if (IS_ERR(q)) {</div><div class='add'>+				err = PTR_ERR(q);</div><div class='add'>+				goto err_close;</div><div class='add'>+			}</div><div class='add'>+			vm-&gt;q[id] = q;</div><div class='add'>+			number_tiles++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (number_tiles &gt; 1)</div><div class='add'>+		vm-&gt;composite_fence_ctx = dma_fence_context_alloc(1);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	if (flags &amp; XE_VM_FLAG_FAULT_MODE)</div><div class='add'>+		xe-&gt;usm.num_vm_in_fault_mode++;</div><div class='add'>+	else if (!(flags &amp; XE_VM_FLAG_MIGRATION))</div><div class='add'>+		xe-&gt;usm.num_vm_in_non_fault_mode++;</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+</div><div class='add'>+	trace_xe_vm_create(vm);</div><div class='add'>+</div><div class='add'>+	return vm;</div><div class='add'>+</div><div class='add'>+err_unlock_close:</div><div class='add'>+	dma_resv_unlock(xe_vm_resv(vm));</div><div class='add'>+err_close:</div><div class='add'>+	xe_vm_close_and_put(vm);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+err_no_resv:</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_range_fence_tree_fini(&amp;vm-&gt;rftree[id]);</div><div class='add'>+	kfree(vm);</div><div class='add'>+	if (!(flags &amp; XE_VM_FLAG_MIGRATION))</div><div class='add'>+		xe_device_mem_access_put(xe);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_close(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	vm-&gt;size = 0;</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_vm_close_and_put(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	LIST_HEAD(contested);</div><div class='add'>+	struct xe_device *xe = vm-&gt;xe;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct xe_vma *vma, *next_vma;</div><div class='add'>+	struct drm_gpuva *gpuva, *next;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, !vm-&gt;preempt.num_exec_queues);</div><div class='add'>+</div><div class='add'>+	xe_vm_close(vm);</div><div class='add'>+	if (xe_vm_in_preempt_fence_mode(vm))</div><div class='add'>+		flush_work(&amp;vm-&gt;preempt.rebind_work);</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (vm-&gt;q[id])</div><div class='add'>+			xe_exec_queue_last_fence_put(vm-&gt;q[id], vm);</div><div class='add'>+	}</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (vm-&gt;q[id]) {</div><div class='add'>+			xe_exec_queue_kill(vm-&gt;q[id]);</div><div class='add'>+			xe_exec_queue_put(vm-&gt;q[id]);</div><div class='add'>+			vm-&gt;q[id] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	down_write(&amp;vm-&gt;lock);</div><div class='add'>+	xe_vm_lock(vm, false);</div><div class='add'>+	drm_gpuvm_for_each_va_safe(gpuva, next, &amp;vm-&gt;gpuvm) {</div><div class='add'>+		vma = gpuva_to_vma(gpuva);</div><div class='add'>+</div><div class='add'>+		if (xe_vma_has_no_bo(vma)) {</div><div class='add'>+			down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			vma-&gt;gpuva.flags |= XE_VMA_DESTROYED;</div><div class='add'>+			up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		xe_vm_remove_vma(vm, vma);</div><div class='add'>+</div><div class='add'>+		/* easy case, remove from VMA? */</div><div class='add'>+		if (xe_vma_has_no_bo(vma) || xe_vma_bo(vma)-&gt;vm) {</div><div class='add'>+			list_del_init(&amp;vma-&gt;combined_links.rebind);</div><div class='add'>+			xe_vma_destroy(vma, NULL);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		list_move_tail(&amp;vma-&gt;combined_links.destroy, &amp;contested);</div><div class='add'>+		vma-&gt;gpuva.flags |= XE_VMA_DESTROYED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * All vm operations will add shared fences to resv.</div><div class='add'>+	 * The only exception is eviction for a shared object,</div><div class='add'>+	 * but even so, the unbind when evicted would still</div><div class='add'>+	 * install a fence to resv. Hence it's safe to</div><div class='add'>+	 * destroy the pagetables immediately.</div><div class='add'>+	 */</div><div class='add'>+	xe_vm_free_scratch(vm);</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (vm-&gt;pt_root[id]) {</div><div class='add'>+			xe_pt_destroy(vm-&gt;pt_root[id], vm-&gt;flags, NULL);</div><div class='add'>+			vm-&gt;pt_root[id] = NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	xe_vm_unlock(vm);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * VM is now dead, cannot re-add nodes to vm-&gt;vmas if it's NULL</div><div class='add'>+	 * Since we hold a refcount to the bo, we can remove and free</div><div class='add'>+	 * the members safely without locking.</div><div class='add'>+	 */</div><div class='add'>+	list_for_each_entry_safe(vma, next_vma, &amp;contested,</div><div class='add'>+				 combined_links.destroy) {</div><div class='add'>+		list_del_init(&amp;vma-&gt;combined_links.destroy);</div><div class='add'>+		xe_vma_destroy_unlocked(vma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+	if (vm-&gt;flags &amp; XE_VM_FLAG_FAULT_MODE)</div><div class='add'>+		xe-&gt;usm.num_vm_in_fault_mode--;</div><div class='add'>+	else if (!(vm-&gt;flags &amp; XE_VM_FLAG_MIGRATION))</div><div class='add'>+		xe-&gt;usm.num_vm_in_non_fault_mode--;</div><div class='add'>+	mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		xe_range_fence_tree_fini(&amp;vm-&gt;rftree[id]);</div><div class='add'>+</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vm_destroy_work_func(struct work_struct *w)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm =</div><div class='add'>+		container_of(w, struct xe_vm, destroy_work);</div><div class='add'>+	struct xe_device *xe = vm-&gt;xe;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u8 id;</div><div class='add'>+	void *lookup;</div><div class='add'>+</div><div class='add'>+	/* xe_vm_close_and_put was not called? */</div><div class='add'>+	xe_assert(xe, !vm-&gt;size);</div><div class='add'>+</div><div class='add'>+	if (!(vm-&gt;flags &amp; XE_VM_FLAG_MIGRATION)) {</div><div class='add'>+		xe_device_mem_access_put(xe);</div><div class='add'>+</div><div class='add'>+		if (xe-&gt;info.has_asid &amp;&amp; vm-&gt;usm.asid) {</div><div class='add'>+			mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+			lookup = xa_erase(&amp;xe-&gt;usm.asid_to_vm, vm-&gt;usm.asid);</div><div class='add'>+			xe_assert(xe, lookup == vm);</div><div class='add'>+			mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		XE_WARN_ON(vm-&gt;pt_root[id]);</div><div class='add'>+</div><div class='add'>+	trace_xe_vm_free(vm);</div><div class='add'>+	dma_fence_put(vm-&gt;rebind_fence);</div><div class='add'>+	kfree(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vm_free(struct drm_gpuvm *gpuvm)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = container_of(gpuvm, struct xe_vm, gpuvm);</div><div class='add'>+</div><div class='add'>+	/* To destroy the VM we need to be able to sleep */</div><div class='add'>+	queue_work(system_unbound_wq, &amp;vm-&gt;destroy_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	vm = xa_load(&amp;xef-&gt;vm.xa, id);</div><div class='add'>+	if (vm)</div><div class='add'>+		xe_vm_get(vm);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;vm.lock);</div><div class='add'>+</div><div class='add'>+	return vm;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;pt_ops-&gt;pde_encode_bo(vm-&gt;pt_root[tile-&gt;id]-&gt;bo, 0,</div><div class='add'>+					 tile_to_xe(tile)-&gt;pat.idx[XE_CACHE_WB]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_exec_queue *</div><div class='add'>+to_wait_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)</div><div class='add'>+{</div><div class='add'>+	return q ? q : vm-&gt;q[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		 struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+		 bool first_op, bool last_op)</div><div class='add'>+{</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct dma_fence *fence = NULL;</div><div class='add'>+	struct dma_fence **fences = NULL;</div><div class='add'>+	struct dma_fence_array *cf = NULL;</div><div class='add'>+	int cur_fence = 0, i;</div><div class='add'>+	int number_tiles = hweight8(vma-&gt;tile_present);</div><div class='add'>+	int err;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	trace_xe_vma_unbind(vma);</div><div class='add'>+</div><div class='add'>+	if (number_tiles &gt; 1) {</div><div class='add'>+		fences = kmalloc_array(number_tiles, sizeof(*fences),</div><div class='add'>+				       GFP_KERNEL);</div><div class='add'>+		if (!fences)</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, vm-&gt;xe, id) {</div><div class='add'>+		if (!(vma-&gt;tile_present &amp; BIT(id)))</div><div class='add'>+			goto next;</div><div class='add'>+</div><div class='add'>+		fence = __xe_pt_unbind_vma(tile, vma, q ? q : vm-&gt;q[id],</div><div class='add'>+					   first_op ? syncs : NULL,</div><div class='add'>+					   first_op ? num_syncs : 0);</div><div class='add'>+		if (IS_ERR(fence)) {</div><div class='add'>+			err = PTR_ERR(fence);</div><div class='add'>+			goto err_fences;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (fences)</div><div class='add'>+			fences[cur_fence++] = fence;</div><div class='add'>+</div><div class='add'>+next:</div><div class='add'>+		if (q &amp;&amp; vm-&gt;pt_root[id] &amp;&amp; !list_empty(&amp;q-&gt;multi_gt_list))</div><div class='add'>+			q = list_next_entry(q, multi_gt_list);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fences) {</div><div class='add'>+		cf = dma_fence_array_create(number_tiles, fences,</div><div class='add'>+					    vm-&gt;composite_fence_ctx,</div><div class='add'>+					    vm-&gt;composite_fence_seqno++,</div><div class='add'>+					    false);</div><div class='add'>+		if (!cf) {</div><div class='add'>+			--vm-&gt;composite_fence_seqno;</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_fences;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fence = cf ? &amp;cf-&gt;base : !fence ?</div><div class='add'>+		xe_exec_queue_last_fence_get(wait_exec_queue, vm) : fence;</div><div class='add'>+	if (last_op) {</div><div class='add'>+		for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+			xe_sync_entry_signal(&amp;syncs[i], NULL, fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return fence;</div><div class='add'>+</div><div class='add'>+err_fences:</div><div class='add'>+	if (fences) {</div><div class='add'>+		while (cur_fence)</div><div class='add'>+			dma_fence_put(fences[--cur_fence]);</div><div class='add'>+		kfree(fences);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct dma_fence *</div><div class='add'>+xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+	       struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+	       bool first_op, bool last_op)</div><div class='add'>+{</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct dma_fence **fences = NULL;</div><div class='add'>+	struct dma_fence_array *cf = NULL;</div><div class='add'>+	struct xe_vm *vm = xe_vma_vm(vma);</div><div class='add'>+	int cur_fence = 0, i;</div><div class='add'>+	int number_tiles = hweight8(vma-&gt;tile_mask);</div><div class='add'>+	int err;</div><div class='add'>+	u8 id;</div><div class='add'>+</div><div class='add'>+	trace_xe_vma_bind(vma);</div><div class='add'>+</div><div class='add'>+	if (number_tiles &gt; 1) {</div><div class='add'>+		fences = kmalloc_array(number_tiles, sizeof(*fences),</div><div class='add'>+				       GFP_KERNEL);</div><div class='add'>+		if (!fences)</div><div class='add'>+			return ERR_PTR(-ENOMEM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, vm-&gt;xe, id) {</div><div class='add'>+		if (!(vma-&gt;tile_mask &amp; BIT(id)))</div><div class='add'>+			goto next;</div><div class='add'>+</div><div class='add'>+		fence = __xe_pt_bind_vma(tile, vma, q ? q : vm-&gt;q[id],</div><div class='add'>+					 first_op ? syncs : NULL,</div><div class='add'>+					 first_op ? num_syncs : 0,</div><div class='add'>+					 vma-&gt;tile_present &amp; BIT(id));</div><div class='add'>+		if (IS_ERR(fence)) {</div><div class='add'>+			err = PTR_ERR(fence);</div><div class='add'>+			goto err_fences;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (fences)</div><div class='add'>+			fences[cur_fence++] = fence;</div><div class='add'>+</div><div class='add'>+next:</div><div class='add'>+		if (q &amp;&amp; vm-&gt;pt_root[id] &amp;&amp; !list_empty(&amp;q-&gt;multi_gt_list))</div><div class='add'>+			q = list_next_entry(q, multi_gt_list);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fences) {</div><div class='add'>+		cf = dma_fence_array_create(number_tiles, fences,</div><div class='add'>+					    vm-&gt;composite_fence_ctx,</div><div class='add'>+					    vm-&gt;composite_fence_seqno++,</div><div class='add'>+					    false);</div><div class='add'>+		if (!cf) {</div><div class='add'>+			--vm-&gt;composite_fence_seqno;</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto err_fences;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (last_op) {</div><div class='add'>+		for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+			xe_sync_entry_signal(&amp;syncs[i], NULL,</div><div class='add'>+					     cf ? &amp;cf-&gt;base : fence);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cf ? &amp;cf-&gt;base : fence;</div><div class='add'>+</div><div class='add'>+err_fences:</div><div class='add'>+	if (fences) {</div><div class='add'>+		while (cur_fence)</div><div class='add'>+			dma_fence_put(fences[--cur_fence]);</div><div class='add'>+		kfree(fences);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma,</div><div class='add'>+			struct xe_exec_queue *q, struct xe_sync_entry *syncs,</div><div class='add'>+			u32 num_syncs, bool immediate, bool first_op,</div><div class='add'>+			bool last_op)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+</div><div class='add'>+	if (immediate) {</div><div class='add'>+		fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op,</div><div class='add'>+				       last_op);</div><div class='add'>+		if (IS_ERR(fence))</div><div class='add'>+			return PTR_ERR(fence);</div><div class='add'>+	} else {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		xe_assert(vm-&gt;xe, xe_vm_in_fault_mode(vm));</div><div class='add'>+</div><div class='add'>+		fence = xe_exec_queue_last_fence_get(wait_exec_queue, vm);</div><div class='add'>+		if (last_op) {</div><div class='add'>+			for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+				xe_sync_entry_signal(&amp;syncs[i], NULL, fence);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (last_op)</div><div class='add'>+		xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q,</div><div class='add'>+		      struct xe_bo *bo, struct xe_sync_entry *syncs,</div><div class='add'>+		      u32 num_syncs, bool immediate, bool first_op,</div><div class='add'>+		      bool last_op)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	xe_bo_assert_held(bo);</div><div class='add'>+</div><div class='add'>+	if (bo &amp;&amp; immediate) {</div><div class='add'>+		err = xe_bo_validate(bo, vm, true);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return __xe_vm_bind(vm, vma, q, syncs, num_syncs, immediate, first_op,</div><div class='add'>+			    last_op);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma,</div><div class='add'>+			struct xe_exec_queue *q, struct xe_sync_entry *syncs,</div><div class='add'>+			u32 num_syncs, bool first_op, bool last_op)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+</div><div class='add'>+	fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op);</div><div class='add'>+	if (IS_ERR(fence))</div><div class='add'>+		return PTR_ERR(fence);</div><div class='add'>+</div><div class='add'>+	xe_vma_destroy(vma, fence);</div><div class='add'>+	if (last_op)</div><div class='add'>+		xe_exec_queue_last_fence_set(wait_exec_queue, vm, fence);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define ALL_DRM_XE_VM_CREATE_FLAGS (DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE | \</div><div class='add'>+				    DRM_XE_VM_CREATE_FLAG_LR_MODE | \</div><div class='add'>+				    DRM_XE_VM_CREATE_FLAG_FAULT_MODE)</div><div class='add'>+</div><div class='add'>+int xe_vm_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+		       struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_vm_create *args = data;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	u32 id, asid;</div><div class='add'>+	int err;</div><div class='add'>+	u32 flags = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(xe_root_mmio_gt(xe), 14016763929))</div><div class='add'>+		args-&gt;flags |= DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE &amp;&amp;</div><div class='add'>+			 !xe-&gt;info.has_usm))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp; ~ALL_DRM_XE_VM_CREATE_FLAGS))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE &amp;&amp;</div><div class='add'>+			 args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !(args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_LR_MODE) &amp;&amp;</div><div class='add'>+			 args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE &amp;&amp;</div><div class='add'>+			 xe_device_in_non_fault_mode(xe)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !(args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE) &amp;&amp;</div><div class='add'>+			 xe_device_in_fault_mode(xe)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE)</div><div class='add'>+		flags |= XE_VM_FLAG_SCRATCH_PAGE;</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_LR_MODE)</div><div class='add'>+		flags |= XE_VM_FLAG_LR_MODE;</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_VM_CREATE_FLAG_FAULT_MODE)</div><div class='add'>+		flags |= XE_VM_FLAG_FAULT_MODE;</div><div class='add'>+</div><div class='add'>+	vm = xe_vm_create(xe, flags);</div><div class='add'>+	if (IS_ERR(vm))</div><div class='add'>+		return PTR_ERR(vm);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	err = xa_alloc(&amp;xef-&gt;vm.xa, &amp;id, vm, xa_limit_32b, GFP_KERNEL);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	if (err) {</div><div class='add'>+		xe_vm_close_and_put(vm);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (xe-&gt;info.has_asid) {</div><div class='add'>+		mutex_lock(&amp;xe-&gt;usm.lock);</div><div class='add'>+		err = xa_alloc_cyclic(&amp;xe-&gt;usm.asid_to_vm, &amp;asid, vm,</div><div class='add'>+				      XA_LIMIT(1, XE_MAX_ASID - 1),</div><div class='add'>+				      &amp;xe-&gt;usm.next_asid, GFP_KERNEL);</div><div class='add'>+		mutex_unlock(&amp;xe-&gt;usm.lock);</div><div class='add'>+		if (err &lt; 0) {</div><div class='add'>+			xe_vm_close_and_put(vm);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+		err = 0;</div><div class='add'>+		vm-&gt;usm.asid = asid;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	args-&gt;vm_id = id;</div><div class='add'>+	vm-&gt;xef = xef;</div><div class='add'>+</div><div class='add'>+	/* Record BO memory for VM pagetable created against client */</div><div class='add'>+	for_each_tile(tile, xe, id)</div><div class='add'>+		if (vm-&gt;pt_root[id])</div><div class='add'>+			xe_drm_client_add_bo(vm-&gt;xef-&gt;client, vm-&gt;pt_root[id]-&gt;bo);</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)</div><div class='add'>+	/* Warning: Security issue - never enable by default */</div><div class='add'>+	args-&gt;reserved[0] = xe_bo_main_addr(vm-&gt;pt_root[0]-&gt;bo, XE_PAGE_SIZE);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vm_destroy_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_vm_destroy *args = data;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;pad) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;xef-&gt;vm.lock);</div><div class='add'>+	vm = xa_load(&amp;xef-&gt;vm.xa, args-&gt;vm_id);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !vm))</div><div class='add'>+		err = -ENOENT;</div><div class='add'>+	else if (XE_IOCTL_DBG(xe, vm-&gt;preempt.num_exec_queues))</div><div class='add'>+		err = -EBUSY;</div><div class='add'>+	else</div><div class='add'>+		xa_erase(&amp;xef-&gt;vm.xa, args-&gt;vm_id);</div><div class='add'>+	mutex_unlock(&amp;xef-&gt;vm.lock);</div><div class='add'>+</div><div class='add'>+	if (!err)</div><div class='add'>+		xe_vm_close_and_put(vm);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const u32 region_to_mem_type[] = {</div><div class='add'>+	XE_PL_TT,</div><div class='add'>+	XE_PL_VRAM0,</div><div class='add'>+	XE_PL_VRAM1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma,</div><div class='add'>+			  struct xe_exec_queue *q, u32 region,</div><div class='add'>+			  struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+			  bool first_op, bool last_op)</div><div class='add'>+{</div><div class='add'>+	struct xe_exec_queue *wait_exec_queue = to_wait_exec_queue(vm, q);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xe_assert(vm-&gt;xe, region &lt;= ARRAY_SIZE(region_to_mem_type));</div><div class='add'>+</div><div class='add'>+	if (!xe_vma_has_no_bo(vma)) {</div><div class='add'>+		err = xe_bo_migrate(xe_vma_bo(vma), region_to_mem_type[region]);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vma-&gt;tile_mask != (vma-&gt;tile_present &amp; ~vma-&gt;usm.tile_invalidated)) {</div><div class='add'>+		return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs,</div><div class='add'>+				  true, first_op, last_op);</div><div class='add'>+	} else {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		/* Nothing to do, signal fences now */</div><div class='add'>+		if (last_op) {</div><div class='add'>+			for (i = 0; i &lt; num_syncs; i++) {</div><div class='add'>+				struct dma_fence *fence =</div><div class='add'>+					xe_exec_queue_last_fence_get(wait_exec_queue, vm);</div><div class='add'>+</div><div class='add'>+				xe_sync_entry_signal(&amp;syncs[i], NULL, fence);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void prep_vma_destroy(struct xe_vm *vm, struct xe_vma *vma,</div><div class='add'>+			     bool post_commit)</div><div class='add'>+{</div><div class='add'>+	down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	vma-&gt;gpuva.flags |= XE_VMA_DESTROYED;</div><div class='add'>+	up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+	if (post_commit)</div><div class='add'>+		xe_vm_remove_vma(vm, vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#undef ULL</div><div class='add'>+#define ULL	unsigned long long</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)</div><div class='add'>+static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+</div><div class='add'>+	switch (op-&gt;op) {</div><div class='add'>+	case DRM_GPUVA_OP_MAP:</div><div class='add'>+		vm_dbg(&amp;xe-&gt;drm, "MAP: addr=0x%016llx, range=0x%016llx",</div><div class='add'>+		       (ULL)op-&gt;map.va.addr, (ULL)op-&gt;map.va.range);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_REMAP:</div><div class='add'>+		vma = gpuva_to_vma(op-&gt;remap.unmap-&gt;va);</div><div class='add'>+		vm_dbg(&amp;xe-&gt;drm, "REMAP:UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d",</div><div class='add'>+		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma),</div><div class='add'>+		       op-&gt;remap.unmap-&gt;keep ? 1 : 0);</div><div class='add'>+		if (op-&gt;remap.prev)</div><div class='add'>+			vm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+			       "REMAP:PREV: addr=0x%016llx, range=0x%016llx",</div><div class='add'>+			       (ULL)op-&gt;remap.prev-&gt;va.addr,</div><div class='add'>+			       (ULL)op-&gt;remap.prev-&gt;va.range);</div><div class='add'>+		if (op-&gt;remap.next)</div><div class='add'>+			vm_dbg(&amp;xe-&gt;drm,</div><div class='add'>+			       "REMAP:NEXT: addr=0x%016llx, range=0x%016llx",</div><div class='add'>+			       (ULL)op-&gt;remap.next-&gt;va.addr,</div><div class='add'>+			       (ULL)op-&gt;remap.next-&gt;va.range);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+		vma = gpuva_to_vma(op-&gt;unmap.va);</div><div class='add'>+		vm_dbg(&amp;xe-&gt;drm, "UNMAP: addr=0x%016llx, range=0x%016llx, keep=%d",</div><div class='add'>+		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma),</div><div class='add'>+		       op-&gt;unmap.keep ? 1 : 0);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+		vma = gpuva_to_vma(op-&gt;prefetch.va);</div><div class='add'>+		vm_dbg(&amp;xe-&gt;drm, "PREFETCH: addr=0x%016llx, range=0x%016llx",</div><div class='add'>+		       (ULL)xe_vma_start(vma), (ULL)xe_vma_size(vma));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Create operations list from IOCTL arguments, setup operations fields so parse</div><div class='add'>+ * and commit steps are decoupled from IOCTL arguments. This step can fail.</div><div class='add'>+ */</div><div class='add'>+static struct drm_gpuva_ops *</div><div class='add'>+vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,</div><div class='add'>+			 u64 bo_offset_or_userptr, u64 addr, u64 range,</div><div class='add'>+			 u32 operation, u32 flags,</div><div class='add'>+			 u32 prefetch_region, u16 pat_index)</div><div class='add'>+{</div><div class='add'>+	struct drm_gem_object *obj = bo ? &amp;bo-&gt;ttm.base : NULL;</div><div class='add'>+	struct drm_gpuva_ops *ops;</div><div class='add'>+	struct drm_gpuva_op *__op;</div><div class='add'>+	struct xe_vma_op *op;</div><div class='add'>+	struct drm_gpuvm_bo *vm_bo;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	vm_dbg(&amp;vm-&gt;xe-&gt;drm,</div><div class='add'>+	       "op=%d, addr=0x%016llx, range=0x%016llx, bo_offset_or_userptr=0x%016llx",</div><div class='add'>+	       operation, (ULL)addr, (ULL)range,</div><div class='add'>+	       (ULL)bo_offset_or_userptr);</div><div class='add'>+</div><div class='add'>+	switch (operation) {</div><div class='add'>+	case DRM_XE_VM_BIND_OP_MAP:</div><div class='add'>+	case DRM_XE_VM_BIND_OP_MAP_USERPTR:</div><div class='add'>+		ops = drm_gpuvm_sm_map_ops_create(&amp;vm-&gt;gpuvm, addr, range,</div><div class='add'>+						  obj, bo_offset_or_userptr);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_VM_BIND_OP_UNMAP:</div><div class='add'>+		ops = drm_gpuvm_sm_unmap_ops_create(&amp;vm-&gt;gpuvm, addr, range);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_VM_BIND_OP_PREFETCH:</div><div class='add'>+		ops = drm_gpuvm_prefetch_ops_create(&amp;vm-&gt;gpuvm, addr, range);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_VM_BIND_OP_UNMAP_ALL:</div><div class='add'>+		xe_assert(vm-&gt;xe, bo);</div><div class='add'>+</div><div class='add'>+		err = xe_bo_lock(bo, true);</div><div class='add'>+		if (err)</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+		vm_bo = drm_gpuvm_bo_obtain(&amp;vm-&gt;gpuvm, obj);</div><div class='add'>+		if (IS_ERR(vm_bo)) {</div><div class='add'>+			xe_bo_unlock(bo);</div><div class='add'>+			return ERR_CAST(vm_bo);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ops = drm_gpuvm_bo_unmap_ops_create(vm_bo);</div><div class='add'>+		drm_gpuvm_bo_put(vm_bo);</div><div class='add'>+		xe_bo_unlock(bo);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+		ops = ERR_PTR(-EINVAL);</div><div class='add'>+	}</div><div class='add'>+	if (IS_ERR(ops))</div><div class='add'>+		return ops;</div><div class='add'>+</div><div class='add'>+#ifdef TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+	if (operation &amp; FORCE_ASYNC_OP_ERROR) {</div><div class='add'>+		op = list_first_entry_or_null(&amp;ops-&gt;list, struct xe_vma_op,</div><div class='add'>+					      base.entry);</div><div class='add'>+		if (op)</div><div class='add'>+			op-&gt;inject_error = true;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	drm_gpuva_for_each_op(__op, ops) {</div><div class='add'>+		struct xe_vma_op *op = gpuva_op_to_vma_op(__op);</div><div class='add'>+</div><div class='add'>+		if (__op-&gt;op == DRM_GPUVA_OP_MAP) {</div><div class='add'>+			op-&gt;map.immediate =</div><div class='add'>+				flags &amp; DRM_XE_VM_BIND_FLAG_IMMEDIATE;</div><div class='add'>+			op-&gt;map.read_only =</div><div class='add'>+				flags &amp; DRM_XE_VM_BIND_FLAG_READONLY;</div><div class='add'>+			op-&gt;map.is_null = flags &amp; DRM_XE_VM_BIND_FLAG_NULL;</div><div class='add'>+			op-&gt;map.pat_index = pat_index;</div><div class='add'>+		} else if (__op-&gt;op == DRM_GPUVA_OP_PREFETCH) {</div><div class='add'>+			op-&gt;prefetch.region = prefetch_region;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		print_op(vm-&gt;xe, __op);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ops;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op,</div><div class='add'>+			      u16 pat_index, unsigned int flags)</div><div class='add'>+{</div><div class='add'>+	struct xe_bo *bo = op-&gt;gem.obj ? gem_to_xe_bo(op-&gt;gem.obj) : NULL;</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (bo) {</div><div class='add'>+		drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+		drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+			err = 0;</div><div class='add'>+			if (!bo-&gt;vm) {</div><div class='add'>+				err = drm_exec_lock_obj(&amp;exec, xe_vm_obj(vm));</div><div class='add'>+				drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+			}</div><div class='add'>+			if (!err) {</div><div class='add'>+				err = drm_exec_lock_obj(&amp;exec, &amp;bo-&gt;ttm.base);</div><div class='add'>+				drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+			}</div><div class='add'>+			if (err) {</div><div class='add'>+				drm_exec_fini(&amp;exec);</div><div class='add'>+				return ERR_PTR(err);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	vma = xe_vma_create(vm, bo, op-&gt;gem.offset,</div><div class='add'>+			    op-&gt;va.addr, op-&gt;va.addr +</div><div class='add'>+			    op-&gt;va.range - 1, pat_index, flags);</div><div class='add'>+	if (bo)</div><div class='add'>+		drm_exec_fini(&amp;exec);</div><div class='add'>+</div><div class='add'>+	if (xe_vma_is_userptr(vma)) {</div><div class='add'>+		err = xe_vma_userptr_pin_pages(vma);</div><div class='add'>+		if (err) {</div><div class='add'>+			prep_vma_destroy(vm, vma, false);</div><div class='add'>+			xe_vma_destroy_unlocked(vma);</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+		}</div><div class='add'>+	} else if (!xe_vma_has_no_bo(vma) &amp;&amp; !bo-&gt;vm) {</div><div class='add'>+		err = add_preempt_fences(vm, bo);</div><div class='add'>+		if (err) {</div><div class='add'>+			prep_vma_destroy(vm, vma, false);</div><div class='add'>+			xe_vma_destroy_unlocked(vma);</div><div class='add'>+			return ERR_PTR(err);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return vma;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_vma_max_pte_size(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	if (vma-&gt;gpuva.flags &amp; XE_VMA_PTE_1G)</div><div class='add'>+		return SZ_1G;</div><div class='add'>+	else if (vma-&gt;gpuva.flags &amp; XE_VMA_PTE_2M)</div><div class='add'>+		return SZ_2M;</div><div class='add'>+</div><div class='add'>+	return SZ_4K;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 xe_vma_set_pte_size(struct xe_vma *vma, u64 size)</div><div class='add'>+{</div><div class='add'>+	switch (size) {</div><div class='add'>+	case SZ_1G:</div><div class='add'>+		vma-&gt;gpuva.flags |= XE_VMA_PTE_1G;</div><div class='add'>+		break;</div><div class='add'>+	case SZ_2M:</div><div class='add'>+		vma-&gt;gpuva.flags |= XE_VMA_PTE_2M;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return SZ_4K;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_vma_op_commit(struct xe_vm *vm, struct xe_vma_op *op)</div><div class='add'>+{</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	switch (op-&gt;base.op) {</div><div class='add'>+	case DRM_GPUVA_OP_MAP:</div><div class='add'>+		err |= xe_vm_insert_vma(vm, op-&gt;map.vma);</div><div class='add'>+		if (!err)</div><div class='add'>+			op-&gt;flags |= XE_VMA_OP_COMMITTED;</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_REMAP:</div><div class='add'>+	{</div><div class='add'>+		u8 tile_present =</div><div class='add'>+			gpuva_to_vma(op-&gt;base.remap.unmap-&gt;va)-&gt;tile_present;</div><div class='add'>+</div><div class='add'>+		prep_vma_destroy(vm, gpuva_to_vma(op-&gt;base.remap.unmap-&gt;va),</div><div class='add'>+				 true);</div><div class='add'>+		op-&gt;flags |= XE_VMA_OP_COMMITTED;</div><div class='add'>+</div><div class='add'>+		if (op-&gt;remap.prev) {</div><div class='add'>+			err |= xe_vm_insert_vma(vm, op-&gt;remap.prev);</div><div class='add'>+			if (!err)</div><div class='add'>+				op-&gt;flags |= XE_VMA_OP_PREV_COMMITTED;</div><div class='add'>+			if (!err &amp;&amp; op-&gt;remap.skip_prev) {</div><div class='add'>+				op-&gt;remap.prev-&gt;tile_present =</div><div class='add'>+					tile_present;</div><div class='add'>+				op-&gt;remap.prev = NULL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (op-&gt;remap.next) {</div><div class='add'>+			err |= xe_vm_insert_vma(vm, op-&gt;remap.next);</div><div class='add'>+			if (!err)</div><div class='add'>+				op-&gt;flags |= XE_VMA_OP_NEXT_COMMITTED;</div><div class='add'>+			if (!err &amp;&amp; op-&gt;remap.skip_next) {</div><div class='add'>+				op-&gt;remap.next-&gt;tile_present =</div><div class='add'>+					tile_present;</div><div class='add'>+				op-&gt;remap.next = NULL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Adjust for partial unbind after removin VMA from VM */</div><div class='add'>+		if (!err) {</div><div class='add'>+			op-&gt;base.remap.unmap-&gt;va-&gt;va.addr = op-&gt;remap.start;</div><div class='add'>+			op-&gt;base.remap.unmap-&gt;va-&gt;va.range = op-&gt;remap.range;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+		prep_vma_destroy(vm, gpuva_to_vma(op-&gt;base.unmap.va), true);</div><div class='add'>+		op-&gt;flags |= XE_VMA_OP_COMMITTED;</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+		op-&gt;flags |= XE_VMA_OP_COMMITTED;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q,</div><div class='add'>+				   struct drm_gpuva_ops *ops,</div><div class='add'>+				   struct xe_sync_entry *syncs, u32 num_syncs,</div><div class='add'>+				   struct list_head *ops_list, bool last)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma_op *last_op = NULL;</div><div class='add'>+	struct drm_gpuva_op *__op;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	drm_gpuva_for_each_op(__op, ops) {</div><div class='add'>+		struct xe_vma_op *op = gpuva_op_to_vma_op(__op);</div><div class='add'>+		struct xe_vma *vma;</div><div class='add'>+		bool first = list_empty(ops_list);</div><div class='add'>+		unsigned int flags = 0;</div><div class='add'>+</div><div class='add'>+		INIT_LIST_HEAD(&amp;op-&gt;link);</div><div class='add'>+		list_add_tail(&amp;op-&gt;link, ops_list);</div><div class='add'>+</div><div class='add'>+		if (first) {</div><div class='add'>+			op-&gt;flags |= XE_VMA_OP_FIRST;</div><div class='add'>+			op-&gt;num_syncs = num_syncs;</div><div class='add'>+			op-&gt;syncs = syncs;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		op-&gt;q = q;</div><div class='add'>+</div><div class='add'>+		switch (op-&gt;base.op) {</div><div class='add'>+		case DRM_GPUVA_OP_MAP:</div><div class='add'>+		{</div><div class='add'>+			flags |= op-&gt;map.read_only ?</div><div class='add'>+				VMA_CREATE_FLAG_READ_ONLY : 0;</div><div class='add'>+			flags |= op-&gt;map.is_null ?</div><div class='add'>+				VMA_CREATE_FLAG_IS_NULL : 0;</div><div class='add'>+</div><div class='add'>+			vma = new_vma(vm, &amp;op-&gt;base.map, op-&gt;map.pat_index,</div><div class='add'>+				      flags);</div><div class='add'>+			if (IS_ERR(vma))</div><div class='add'>+				return PTR_ERR(vma);</div><div class='add'>+</div><div class='add'>+			op-&gt;map.vma = vma;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		case DRM_GPUVA_OP_REMAP:</div><div class='add'>+		{</div><div class='add'>+			struct xe_vma *old =</div><div class='add'>+				gpuva_to_vma(op-&gt;base.remap.unmap-&gt;va);</div><div class='add'>+</div><div class='add'>+			op-&gt;remap.start = xe_vma_start(old);</div><div class='add'>+			op-&gt;remap.range = xe_vma_size(old);</div><div class='add'>+</div><div class='add'>+			if (op-&gt;base.remap.prev) {</div><div class='add'>+				flags |= op-&gt;base.remap.unmap-&gt;va-&gt;flags &amp;</div><div class='add'>+					XE_VMA_READ_ONLY ?</div><div class='add'>+					VMA_CREATE_FLAG_READ_ONLY : 0;</div><div class='add'>+				flags |= op-&gt;base.remap.unmap-&gt;va-&gt;flags &amp;</div><div class='add'>+					DRM_GPUVA_SPARSE ?</div><div class='add'>+					VMA_CREATE_FLAG_IS_NULL : 0;</div><div class='add'>+</div><div class='add'>+				vma = new_vma(vm, op-&gt;base.remap.prev,</div><div class='add'>+					      old-&gt;pat_index, flags);</div><div class='add'>+				if (IS_ERR(vma))</div><div class='add'>+					return PTR_ERR(vma);</div><div class='add'>+</div><div class='add'>+				op-&gt;remap.prev = vma;</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * Userptr creates a new SG mapping so</div><div class='add'>+				 * we must also rebind.</div><div class='add'>+				 */</div><div class='add'>+				op-&gt;remap.skip_prev = !xe_vma_is_userptr(old) &amp;&amp;</div><div class='add'>+					IS_ALIGNED(xe_vma_end(vma),</div><div class='add'>+						   xe_vma_max_pte_size(old));</div><div class='add'>+				if (op-&gt;remap.skip_prev) {</div><div class='add'>+					xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old));</div><div class='add'>+					op-&gt;remap.range -=</div><div class='add'>+						xe_vma_end(vma) -</div><div class='add'>+						xe_vma_start(old);</div><div class='add'>+					op-&gt;remap.start = xe_vma_end(vma);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (op-&gt;base.remap.next) {</div><div class='add'>+				flags |= op-&gt;base.remap.unmap-&gt;va-&gt;flags &amp;</div><div class='add'>+					XE_VMA_READ_ONLY ?</div><div class='add'>+					VMA_CREATE_FLAG_READ_ONLY : 0;</div><div class='add'>+				flags |= op-&gt;base.remap.unmap-&gt;va-&gt;flags &amp;</div><div class='add'>+					DRM_GPUVA_SPARSE ?</div><div class='add'>+					VMA_CREATE_FLAG_IS_NULL : 0;</div><div class='add'>+</div><div class='add'>+				vma = new_vma(vm, op-&gt;base.remap.next,</div><div class='add'>+					      old-&gt;pat_index, flags);</div><div class='add'>+				if (IS_ERR(vma))</div><div class='add'>+					return PTR_ERR(vma);</div><div class='add'>+</div><div class='add'>+				op-&gt;remap.next = vma;</div><div class='add'>+</div><div class='add'>+				/*</div><div class='add'>+				 * Userptr creates a new SG mapping so</div><div class='add'>+				 * we must also rebind.</div><div class='add'>+				 */</div><div class='add'>+				op-&gt;remap.skip_next = !xe_vma_is_userptr(old) &amp;&amp;</div><div class='add'>+					IS_ALIGNED(xe_vma_start(vma),</div><div class='add'>+						   xe_vma_max_pte_size(old));</div><div class='add'>+				if (op-&gt;remap.skip_next) {</div><div class='add'>+					xe_vma_set_pte_size(vma, xe_vma_max_pte_size(old));</div><div class='add'>+					op-&gt;remap.range -=</div><div class='add'>+						xe_vma_end(old) -</div><div class='add'>+						xe_vma_start(vma);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+		case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+			/* Nothing to do */</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		last_op = op;</div><div class='add'>+</div><div class='add'>+		err = xe_vma_op_commit(vm, op);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* FIXME: Unhandled corner case */</div><div class='add'>+	XE_WARN_ON(!last_op &amp;&amp; last &amp;&amp; !list_empty(ops_list));</div><div class='add'>+</div><div class='add'>+	if (!last_op)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	last_op-&gt;ops = ops;</div><div class='add'>+	if (last) {</div><div class='add'>+		last_op-&gt;flags |= XE_VMA_OP_LAST;</div><div class='add'>+		last_op-&gt;num_syncs = num_syncs;</div><div class='add'>+		last_op-&gt;syncs = syncs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int op_execute(struct drm_exec *exec, struct xe_vm *vm,</div><div class='add'>+		      struct xe_vma *vma, struct xe_vma_op *op)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	err = xe_vm_prepare_vma(exec, vma, 1);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	xe_vm_assert_held(vm);</div><div class='add'>+	xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+</div><div class='add'>+	switch (op-&gt;base.op) {</div><div class='add'>+	case DRM_GPUVA_OP_MAP:</div><div class='add'>+		err = xe_vm_bind(vm, vma, op-&gt;q, xe_vma_bo(vma),</div><div class='add'>+				 op-&gt;syncs, op-&gt;num_syncs,</div><div class='add'>+				 op-&gt;map.immediate || !xe_vm_in_fault_mode(vm),</div><div class='add'>+				 op-&gt;flags &amp; XE_VMA_OP_FIRST,</div><div class='add'>+				 op-&gt;flags &amp; XE_VMA_OP_LAST);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_REMAP:</div><div class='add'>+	{</div><div class='add'>+		bool prev = !!op-&gt;remap.prev;</div><div class='add'>+		bool next = !!op-&gt;remap.next;</div><div class='add'>+</div><div class='add'>+		if (!op-&gt;remap.unmap_done) {</div><div class='add'>+			if (prev || next)</div><div class='add'>+				vma-&gt;gpuva.flags |= XE_VMA_FIRST_REBIND;</div><div class='add'>+			err = xe_vm_unbind(vm, vma, op-&gt;q, op-&gt;syncs,</div><div class='add'>+					   op-&gt;num_syncs,</div><div class='add'>+					   op-&gt;flags &amp; XE_VMA_OP_FIRST,</div><div class='add'>+					   op-&gt;flags &amp; XE_VMA_OP_LAST &amp;&amp;</div><div class='add'>+					   !prev &amp;&amp; !next);</div><div class='add'>+			if (err)</div><div class='add'>+				break;</div><div class='add'>+			op-&gt;remap.unmap_done = true;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (prev) {</div><div class='add'>+			op-&gt;remap.prev-&gt;gpuva.flags |= XE_VMA_LAST_REBIND;</div><div class='add'>+			err = xe_vm_bind(vm, op-&gt;remap.prev, op-&gt;q,</div><div class='add'>+					 xe_vma_bo(op-&gt;remap.prev), op-&gt;syncs,</div><div class='add'>+					 op-&gt;num_syncs, true, false,</div><div class='add'>+					 op-&gt;flags &amp; XE_VMA_OP_LAST &amp;&amp; !next);</div><div class='add'>+			op-&gt;remap.prev-&gt;gpuva.flags &amp;= ~XE_VMA_LAST_REBIND;</div><div class='add'>+			if (err)</div><div class='add'>+				break;</div><div class='add'>+			op-&gt;remap.prev = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (next) {</div><div class='add'>+			op-&gt;remap.next-&gt;gpuva.flags |= XE_VMA_LAST_REBIND;</div><div class='add'>+			err = xe_vm_bind(vm, op-&gt;remap.next, op-&gt;q,</div><div class='add'>+					 xe_vma_bo(op-&gt;remap.next),</div><div class='add'>+					 op-&gt;syncs, op-&gt;num_syncs,</div><div class='add'>+					 true, false,</div><div class='add'>+					 op-&gt;flags &amp; XE_VMA_OP_LAST);</div><div class='add'>+			op-&gt;remap.next-&gt;gpuva.flags &amp;= ~XE_VMA_LAST_REBIND;</div><div class='add'>+			if (err)</div><div class='add'>+				break;</div><div class='add'>+			op-&gt;remap.next = NULL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+		err = xe_vm_unbind(vm, vma, op-&gt;q, op-&gt;syncs,</div><div class='add'>+				   op-&gt;num_syncs, op-&gt;flags &amp; XE_VMA_OP_FIRST,</div><div class='add'>+				   op-&gt;flags &amp; XE_VMA_OP_LAST);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+		err = xe_vm_prefetch(vm, vma, op-&gt;q, op-&gt;prefetch.region,</div><div class='add'>+				     op-&gt;syncs, op-&gt;num_syncs,</div><div class='add'>+				     op-&gt;flags &amp; XE_VMA_OP_FIRST,</div><div class='add'>+				     op-&gt;flags &amp; XE_VMA_OP_LAST);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (err)</div><div class='add'>+		trace_xe_vma_fail(vma);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma,</div><div class='add'>+			       struct xe_vma_op *op)</div><div class='add'>+{</div><div class='add'>+	struct drm_exec exec;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+retry_userptr:</div><div class='add'>+	drm_exec_init(&amp;exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);</div><div class='add'>+	drm_exec_until_all_locked(&amp;exec) {</div><div class='add'>+		err = op_execute(&amp;exec, vm, vma, op);</div><div class='add'>+		drm_exec_retry_on_contention(&amp;exec);</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	drm_exec_fini(&amp;exec);</div><div class='add'>+</div><div class='add'>+	if (err == -EAGAIN &amp;&amp; xe_vma_is_userptr(vma)) {</div><div class='add'>+		lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+		err = xe_vma_userptr_pin_pages(vma);</div><div class='add'>+		if (!err)</div><div class='add'>+			goto retry_userptr;</div><div class='add'>+</div><div class='add'>+		trace_xe_vma_fail(vma);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int xe_vma_op_execute(struct xe_vm *vm, struct xe_vma_op *op)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+#ifdef TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+	if (op-&gt;inject_error) {</div><div class='add'>+		op-&gt;inject_error = false;</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	switch (op-&gt;base.op) {</div><div class='add'>+	case DRM_GPUVA_OP_MAP:</div><div class='add'>+		ret = __xe_vma_op_execute(vm, op-&gt;map.vma, op);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_REMAP:</div><div class='add'>+	{</div><div class='add'>+		struct xe_vma *vma;</div><div class='add'>+</div><div class='add'>+		if (!op-&gt;remap.unmap_done)</div><div class='add'>+			vma = gpuva_to_vma(op-&gt;base.remap.unmap-&gt;va);</div><div class='add'>+		else if (op-&gt;remap.prev)</div><div class='add'>+			vma = op-&gt;remap.prev;</div><div class='add'>+		else</div><div class='add'>+			vma = op-&gt;remap.next;</div><div class='add'>+</div><div class='add'>+		ret = __xe_vma_op_execute(vm, vma, op);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+		ret = __xe_vma_op_execute(vm, gpuva_to_vma(op-&gt;base.unmap.va),</div><div class='add'>+					  op);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+		ret = __xe_vma_op_execute(vm,</div><div class='add'>+					  gpuva_to_vma(op-&gt;base.prefetch.va),</div><div class='add'>+					  op);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op)</div><div class='add'>+{</div><div class='add'>+	bool last = op-&gt;flags &amp; XE_VMA_OP_LAST;</div><div class='add'>+</div><div class='add'>+	if (last) {</div><div class='add'>+		while (op-&gt;num_syncs--)</div><div class='add'>+			xe_sync_entry_cleanup(&amp;op-&gt;syncs[op-&gt;num_syncs]);</div><div class='add'>+		kfree(op-&gt;syncs);</div><div class='add'>+		if (op-&gt;q)</div><div class='add'>+			xe_exec_queue_put(op-&gt;q);</div><div class='add'>+	}</div><div class='add'>+	if (!list_empty(&amp;op-&gt;link))</div><div class='add'>+		list_del(&amp;op-&gt;link);</div><div class='add'>+	if (op-&gt;ops)</div><div class='add'>+		drm_gpuva_ops_free(&amp;vm-&gt;gpuvm, op-&gt;ops);</div><div class='add'>+	if (last)</div><div class='add'>+		xe_vm_put(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void xe_vma_op_unwind(struct xe_vm *vm, struct xe_vma_op *op,</div><div class='add'>+			     bool post_commit, bool prev_post_commit,</div><div class='add'>+			     bool next_post_commit)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	switch (op-&gt;base.op) {</div><div class='add'>+	case DRM_GPUVA_OP_MAP:</div><div class='add'>+		if (op-&gt;map.vma) {</div><div class='add'>+			prep_vma_destroy(vm, op-&gt;map.vma, post_commit);</div><div class='add'>+			xe_vma_destroy_unlocked(op-&gt;map.vma);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case DRM_GPUVA_OP_UNMAP:</div><div class='add'>+	{</div><div class='add'>+		struct xe_vma *vma = gpuva_to_vma(op-&gt;base.unmap.va);</div><div class='add'>+</div><div class='add'>+		if (vma) {</div><div class='add'>+			down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			vma-&gt;gpuva.flags &amp;= ~XE_VMA_DESTROYED;</div><div class='add'>+			up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			if (post_commit)</div><div class='add'>+				xe_vm_insert_vma(vm, vma);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DRM_GPUVA_OP_REMAP:</div><div class='add'>+	{</div><div class='add'>+		struct xe_vma *vma = gpuva_to_vma(op-&gt;base.remap.unmap-&gt;va);</div><div class='add'>+</div><div class='add'>+		if (op-&gt;remap.prev) {</div><div class='add'>+			prep_vma_destroy(vm, op-&gt;remap.prev, prev_post_commit);</div><div class='add'>+			xe_vma_destroy_unlocked(op-&gt;remap.prev);</div><div class='add'>+		}</div><div class='add'>+		if (op-&gt;remap.next) {</div><div class='add'>+			prep_vma_destroy(vm, op-&gt;remap.next, next_post_commit);</div><div class='add'>+			xe_vma_destroy_unlocked(op-&gt;remap.next);</div><div class='add'>+		}</div><div class='add'>+		if (vma) {</div><div class='add'>+			down_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			vma-&gt;gpuva.flags &amp;= ~XE_VMA_DESTROYED;</div><div class='add'>+			up_read(&amp;vm-&gt;userptr.notifier_lock);</div><div class='add'>+			if (post_commit)</div><div class='add'>+				xe_vm_insert_vma(vm, vma);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DRM_GPUVA_OP_PREFETCH:</div><div class='add'>+		/* Nothing to do */</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		drm_warn(&amp;vm-&gt;xe-&gt;drm, "NOT POSSIBLE");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vm_bind_ioctl_ops_unwind(struct xe_vm *vm,</div><div class='add'>+				     struct drm_gpuva_ops **ops,</div><div class='add'>+				     int num_ops_list)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = num_ops_list - 1; i; ++i) {</div><div class='add'>+		struct drm_gpuva_ops *__ops = ops[i];</div><div class='add'>+		struct drm_gpuva_op *__op;</div><div class='add'>+</div><div class='add'>+		if (!__ops)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		drm_gpuva_for_each_op_reverse(__op, __ops) {</div><div class='add'>+			struct xe_vma_op *op = gpuva_op_to_vma_op(__op);</div><div class='add'>+</div><div class='add'>+			xe_vma_op_unwind(vm, op,</div><div class='add'>+					 op-&gt;flags &amp; XE_VMA_OP_COMMITTED,</div><div class='add'>+					 op-&gt;flags &amp; XE_VMA_OP_PREV_COMMITTED,</div><div class='add'>+					 op-&gt;flags &amp; XE_VMA_OP_NEXT_COMMITTED);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		drm_gpuva_ops_free(&amp;vm-&gt;gpuvm, __ops);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vm_bind_ioctl_ops_execute(struct xe_vm *vm,</div><div class='add'>+				     struct list_head *ops_list)</div><div class='add'>+{</div><div class='add'>+	struct xe_vma_op *op, *next;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(op, next, ops_list, link) {</div><div class='add'>+		err = xe_vma_op_execute(vm, op);</div><div class='add'>+		if (err) {</div><div class='add'>+			drm_warn(&amp;vm-&gt;xe-&gt;drm, "VM op(%d) failed with %d",</div><div class='add'>+				 op-&gt;base.op, err);</div><div class='add'>+			/*</div><div class='add'>+			 * FIXME: Killing VM rather than proper error handling</div><div class='add'>+			 */</div><div class='add'>+			xe_vm_kill(vm);</div><div class='add'>+			return -ENOSPC;</div><div class='add'>+		}</div><div class='add'>+		xe_vma_op_cleanup(vm, op);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+#define SUPPORTED_FLAGS	\</div><div class='add'>+	(FORCE_ASYNC_OP_ERROR | DRM_XE_VM_BIND_FLAG_READONLY | \</div><div class='add'>+	 DRM_XE_VM_BIND_FLAG_IMMEDIATE | DRM_XE_VM_BIND_FLAG_NULL | 0xffff)</div><div class='add'>+#else</div><div class='add'>+#define SUPPORTED_FLAGS	\</div><div class='add'>+	(DRM_XE_VM_BIND_FLAG_READONLY | \</div><div class='add'>+	 DRM_XE_VM_BIND_FLAG_IMMEDIATE | DRM_XE_VM_BIND_FLAG_NULL | \</div><div class='add'>+	 0xffff)</div><div class='add'>+#endif</div><div class='add'>+#define XE_64K_PAGE_MASK 0xffffull</div><div class='add'>+#define ALL_DRM_XE_SYNCS_FLAGS (DRM_XE_SYNCS_FLAG_WAIT_FOR_OP)</div><div class='add'>+</div><div class='add'>+#define MAX_BINDS	512	/* FIXME: Picking random upper limit */</div><div class='add'>+</div><div class='add'>+static int vm_bind_ioctl_check_args(struct xe_device *xe,</div><div class='add'>+				    struct drm_xe_vm_bind *args,</div><div class='add'>+				    struct drm_xe_vm_bind_op **bind_ops)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;pad || args-&gt;pad2) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;num_binds &gt; MAX_BINDS))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;num_binds &gt; 1) {</div><div class='add'>+		u64 __user *bind_user =</div><div class='add'>+			u64_to_user_ptr(args-&gt;vector_of_binds);</div><div class='add'>+</div><div class='add'>+		*bind_ops = kmalloc(sizeof(struct drm_xe_vm_bind_op) *</div><div class='add'>+				    args-&gt;num_binds, GFP_KERNEL);</div><div class='add'>+		if (!*bind_ops)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		err = __copy_from_user(*bind_ops, bind_user,</div><div class='add'>+				       sizeof(struct drm_xe_vm_bind_op) *</div><div class='add'>+				       args-&gt;num_binds);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, err)) {</div><div class='add'>+			err = -EFAULT;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*bind_ops = &amp;args-&gt;bind;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_binds; ++i) {</div><div class='add'>+		u64 range = (*bind_ops)[i].range;</div><div class='add'>+		u64 addr = (*bind_ops)[i].addr;</div><div class='add'>+		u32 op = (*bind_ops)[i].op;</div><div class='add'>+		u32 flags = (*bind_ops)[i].flags;</div><div class='add'>+		u32 obj = (*bind_ops)[i].obj;</div><div class='add'>+		u64 obj_offset = (*bind_ops)[i].obj_offset;</div><div class='add'>+		u32 prefetch_region = (*bind_ops)[i].prefetch_mem_region_instance;</div><div class='add'>+		bool is_null = flags &amp; DRM_XE_VM_BIND_FLAG_NULL;</div><div class='add'>+		u16 pat_index = (*bind_ops)[i].pat_index;</div><div class='add'>+		u16 coh_mode;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, pat_index &gt;= xe-&gt;pat.n_entries)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		pat_index = array_index_nospec(pat_index, xe-&gt;pat.n_entries);</div><div class='add'>+		(*bind_ops)[i].pat_index = pat_index;</div><div class='add'>+		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !coh_mode)) { /* hw reserved */</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (XE_WARN_ON(coh_mode &gt; XE_COH_AT_LEAST_1WAY)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, op &gt; DRM_XE_VM_BIND_OP_PREFETCH) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, flags &amp; ~SUPPORTED_FLAGS) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj &amp;&amp; is_null) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj_offset &amp;&amp; is_null) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, op != DRM_XE_VM_BIND_OP_MAP &amp;&amp;</div><div class='add'>+				 is_null) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, !obj &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_MAP &amp;&amp;</div><div class='add'>+				 !is_null) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, !obj &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, addr &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, range &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_PREFETCH) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, prefetch_region &amp;&amp;</div><div class='add'>+				 op != DRM_XE_VM_BIND_OP_PREFETCH) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, !(BIT(prefetch_region) &amp;</div><div class='add'>+				       xe-&gt;info.mem_region_mask)) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj &amp;&amp;</div><div class='add'>+				 op == DRM_XE_VM_BIND_OP_UNMAP)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, obj_offset &amp; ~PAGE_MASK) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, addr &amp; ~PAGE_MASK) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, range &amp; ~PAGE_MASK) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, !range &amp;&amp;</div><div class='add'>+				 op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto free_bind_ops;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_bind_ops:</div><div class='add'>+	if (args-&gt;num_binds &gt; 1)</div><div class='add'>+		kfree(*bind_ops);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vm_bind_ioctl_signal_fences(struct xe_vm *vm,</div><div class='add'>+				       struct xe_exec_queue *q,</div><div class='add'>+				       struct xe_sync_entry *syncs,</div><div class='add'>+				       int num_syncs)</div><div class='add'>+{</div><div class='add'>+	struct dma_fence *fence;</div><div class='add'>+	int i, err = 0;</div><div class='add'>+</div><div class='add'>+	fence = xe_sync_in_fence_get(syncs, num_syncs,</div><div class='add'>+				     to_wait_exec_queue(vm, q), vm);</div><div class='add'>+	if (IS_ERR(fence))</div><div class='add'>+		return PTR_ERR(fence);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_syncs; i++)</div><div class='add'>+		xe_sync_entry_signal(&amp;syncs[i], NULL, fence);</div><div class='add'>+</div><div class='add'>+	xe_exec_queue_last_fence_set(to_wait_exec_queue(vm, q), vm,</div><div class='add'>+				     fence);</div><div class='add'>+	dma_fence_put(fence);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	struct drm_xe_vm_bind *args = data;</div><div class='add'>+	struct drm_xe_sync __user *syncs_user;</div><div class='add'>+	struct xe_bo **bos = NULL;</div><div class='add'>+	struct drm_gpuva_ops **ops = NULL;</div><div class='add'>+	struct xe_vm *vm;</div><div class='add'>+	struct xe_exec_queue *q = NULL;</div><div class='add'>+	u32 num_syncs;</div><div class='add'>+	struct xe_sync_entry *syncs = NULL;</div><div class='add'>+	struct drm_xe_vm_bind_op *bind_ops;</div><div class='add'>+	LIST_HEAD(ops_list);</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	err = vm_bind_ioctl_check_args(xe, args, &amp;bind_ops);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;exec_queue_id) {</div><div class='add'>+		q = xe_exec_queue_lookup(xef, args-&gt;exec_queue_id);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !q)) {</div><div class='add'>+			err = -ENOENT;</div><div class='add'>+			goto free_objs;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !(q-&gt;flags &amp; EXEC_QUEUE_FLAG_VM))) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto put_exec_queue;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vm = xe_vm_lookup(xef, args-&gt;vm_id);</div><div class='add'>+	if (XE_IOCTL_DBG(xe, !vm)) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto put_exec_queue;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = down_write_killable(&amp;vm-&gt;lock);</div><div class='add'>+	if (err)</div><div class='add'>+		goto put_vm;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) {</div><div class='add'>+		err = -ENOENT;</div><div class='add'>+		goto release_vm_lock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_binds; ++i) {</div><div class='add'>+		u64 range = bind_ops[i].range;</div><div class='add'>+		u64 addr = bind_ops[i].addr;</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, range &gt; vm-&gt;size) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, addr &gt; vm-&gt;size - range)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto release_vm_lock;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (args-&gt;num_binds) {</div><div class='add'>+		bos = kcalloc(args-&gt;num_binds, sizeof(*bos), GFP_KERNEL);</div><div class='add'>+		if (!bos) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto release_vm_lock;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ops = kcalloc(args-&gt;num_binds, sizeof(*ops), GFP_KERNEL);</div><div class='add'>+		if (!ops) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto release_vm_lock;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_binds; ++i) {</div><div class='add'>+		struct drm_gem_object *gem_obj;</div><div class='add'>+		u64 range = bind_ops[i].range;</div><div class='add'>+		u64 addr = bind_ops[i].addr;</div><div class='add'>+		u32 obj = bind_ops[i].obj;</div><div class='add'>+		u64 obj_offset = bind_ops[i].obj_offset;</div><div class='add'>+		u16 pat_index = bind_ops[i].pat_index;</div><div class='add'>+		u16 coh_mode;</div><div class='add'>+</div><div class='add'>+		if (!obj)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		gem_obj = drm_gem_object_lookup(file, obj);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !gem_obj)) {</div><div class='add'>+			err = -ENOENT;</div><div class='add'>+			goto put_obj;</div><div class='add'>+		}</div><div class='add'>+		bos[i] = gem_to_xe_bo(gem_obj);</div><div class='add'>+</div><div class='add'>+		if (XE_IOCTL_DBG(xe, range &gt; bos[i]-&gt;size) ||</div><div class='add'>+		    XE_IOCTL_DBG(xe, obj_offset &gt;</div><div class='add'>+				 bos[i]-&gt;size - range)) {</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto put_obj;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (bos[i]-&gt;flags &amp; XE_BO_INTERNAL_64K) {</div><div class='add'>+			if (XE_IOCTL_DBG(xe, obj_offset &amp;</div><div class='add'>+					 XE_64K_PAGE_MASK) ||</div><div class='add'>+			    XE_IOCTL_DBG(xe, addr &amp; XE_64K_PAGE_MASK) ||</div><div class='add'>+			    XE_IOCTL_DBG(xe, range &amp; XE_64K_PAGE_MASK)) {</div><div class='add'>+				err = -EINVAL;</div><div class='add'>+				goto put_obj;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);</div><div class='add'>+		if (bos[i]-&gt;cpu_caching) {</div><div class='add'>+			if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &amp;&amp;</div><div class='add'>+					 bos[i]-&gt;cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) {</div><div class='add'>+				err = -EINVAL;</div><div class='add'>+				goto put_obj;</div><div class='add'>+			}</div><div class='add'>+		} else if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE)) {</div><div class='add'>+			/*</div><div class='add'>+			 * Imported dma-buf from a different device should</div><div class='add'>+			 * require 1way or 2way coherency since we don't know</div><div class='add'>+			 * how it was mapped on the CPU. Just assume is it</div><div class='add'>+			 * potentially cached on CPU side.</div><div class='add'>+			 */</div><div class='add'>+			err = -EINVAL;</div><div class='add'>+			goto put_obj;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (args-&gt;num_syncs) {</div><div class='add'>+		syncs = kcalloc(args-&gt;num_syncs, sizeof(*syncs), GFP_KERNEL);</div><div class='add'>+		if (!syncs) {</div><div class='add'>+			err = -ENOMEM;</div><div class='add'>+			goto put_obj;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	syncs_user = u64_to_user_ptr(args-&gt;syncs);</div><div class='add'>+	for (num_syncs = 0; num_syncs &lt; args-&gt;num_syncs; num_syncs++) {</div><div class='add'>+		err = xe_sync_entry_parse(xe, xef, &amp;syncs[num_syncs],</div><div class='add'>+					  &amp;syncs_user[num_syncs],</div><div class='add'>+					  (xe_vm_in_lr_mode(vm) ?</div><div class='add'>+					   SYNC_PARSE_FLAG_LR_MODE : 0) |</div><div class='add'>+					  (!args-&gt;num_binds ?</div><div class='add'>+					   SYNC_PARSE_FLAG_DISALLOW_USER_FENCE : 0));</div><div class='add'>+		if (err)</div><div class='add'>+			goto free_syncs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!args-&gt;num_binds) {</div><div class='add'>+		err = -ENODATA;</div><div class='add'>+		goto free_syncs;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_binds; ++i) {</div><div class='add'>+		u64 range = bind_ops[i].range;</div><div class='add'>+		u64 addr = bind_ops[i].addr;</div><div class='add'>+		u32 op = bind_ops[i].op;</div><div class='add'>+		u32 flags = bind_ops[i].flags;</div><div class='add'>+		u64 obj_offset = bind_ops[i].obj_offset;</div><div class='add'>+		u32 prefetch_region = bind_ops[i].prefetch_mem_region_instance;</div><div class='add'>+		u16 pat_index = bind_ops[i].pat_index;</div><div class='add'>+</div><div class='add'>+		ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset,</div><div class='add'>+						  addr, range, op, flags,</div><div class='add'>+						  prefetch_region, pat_index);</div><div class='add'>+		if (IS_ERR(ops[i])) {</div><div class='add'>+			err = PTR_ERR(ops[i]);</div><div class='add'>+			ops[i] = NULL;</div><div class='add'>+			goto unwind_ops;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		err = vm_bind_ioctl_ops_parse(vm, q, ops[i], syncs, num_syncs,</div><div class='add'>+					      &amp;ops_list,</div><div class='add'>+					      i == args-&gt;num_binds - 1);</div><div class='add'>+		if (err)</div><div class='add'>+			goto unwind_ops;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Nothing to do */</div><div class='add'>+	if (list_empty(&amp;ops_list)) {</div><div class='add'>+		err = -ENODATA;</div><div class='add'>+		goto unwind_ops;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xe_vm_get(vm);</div><div class='add'>+	if (q)</div><div class='add'>+		xe_exec_queue_get(q);</div><div class='add'>+</div><div class='add'>+	err = vm_bind_ioctl_ops_execute(vm, &amp;ops_list);</div><div class='add'>+</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (q)</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+</div><div class='add'>+	for (i = 0; bos &amp;&amp; i &lt; args-&gt;num_binds; ++i)</div><div class='add'>+		xe_bo_put(bos[i]);</div><div class='add'>+</div><div class='add'>+	kfree(bos);</div><div class='add'>+	kfree(ops);</div><div class='add'>+	if (args-&gt;num_binds &gt; 1)</div><div class='add'>+		kfree(bind_ops);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+</div><div class='add'>+unwind_ops:</div><div class='add'>+	vm_bind_ioctl_ops_unwind(vm, ops, args-&gt;num_binds);</div><div class='add'>+free_syncs:</div><div class='add'>+	if (err == -ENODATA)</div><div class='add'>+		err = vm_bind_ioctl_signal_fences(vm, q, syncs, num_syncs);</div><div class='add'>+	while (num_syncs--)</div><div class='add'>+		xe_sync_entry_cleanup(&amp;syncs[num_syncs]);</div><div class='add'>+</div><div class='add'>+	kfree(syncs);</div><div class='add'>+put_obj:</div><div class='add'>+	for (i = 0; i &lt; args-&gt;num_binds; ++i)</div><div class='add'>+		xe_bo_put(bos[i]);</div><div class='add'>+release_vm_lock:</div><div class='add'>+	up_write(&amp;vm-&gt;lock);</div><div class='add'>+put_vm:</div><div class='add'>+	xe_vm_put(vm);</div><div class='add'>+put_exec_queue:</div><div class='add'>+	if (q)</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+free_objs:</div><div class='add'>+	kfree(bos);</div><div class='add'>+	kfree(ops);</div><div class='add'>+	if (args-&gt;num_binds &gt; 1)</div><div class='add'>+		kfree(bind_ops);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_lock() - Lock the vm's dma_resv object</div><div class='add'>+ * @vm: The struct xe_vm whose lock is to be locked</div><div class='add'>+ * @intr: Whether to perform any wait interruptible</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, -EINTR if @intr is true and the wait for a</div><div class='add'>+ * contended lock was interrupted. If @intr is false, the function</div><div class='add'>+ * always returns 0.</div><div class='add'>+ */</div><div class='add'>+int xe_vm_lock(struct xe_vm *vm, bool intr)</div><div class='add'>+{</div><div class='add'>+	if (intr)</div><div class='add'>+		return dma_resv_lock_interruptible(xe_vm_resv(vm), NULL);</div><div class='add'>+</div><div class='add'>+	return dma_resv_lock(xe_vm_resv(vm), NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_unlock() - Unlock the vm's dma_resv object</div><div class='add'>+ * @vm: The struct xe_vm whose lock is to be released.</div><div class='add'>+ *</div><div class='add'>+ * Unlock a buffer object lock that was locked by xe_vm_lock().</div><div class='add'>+ */</div><div class='add'>+void xe_vm_unlock(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	dma_resv_unlock(xe_vm_resv(vm));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_invalidate_vma - invalidate GPU mappings for VMA without a lock</div><div class='add'>+ * @vma: VMA to invalidate</div><div class='add'>+ *</div><div class='add'>+ * Walks a list of page tables leaves which it memset the entries owned by this</div><div class='add'>+ * VMA to zero, invalidates the TLBs, and block until TLBs invalidation is</div><div class='add'>+ * complete.</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 for success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int xe_vm_invalidate_vma(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = xe_vma_vm(vma)-&gt;xe;</div><div class='add'>+	struct xe_tile *tile;</div><div class='add'>+	u32 tile_needs_invalidate = 0;</div><div class='add'>+	int seqno[XE_MAX_TILES_PER_DEVICE];</div><div class='add'>+	u8 id;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	xe_assert(xe, xe_vm_in_fault_mode(xe_vma_vm(vma)));</div><div class='add'>+	xe_assert(xe, !xe_vma_is_null(vma));</div><div class='add'>+	trace_xe_vma_usm_invalidate(vma);</div><div class='add'>+</div><div class='add'>+	/* Check that we don't race with page-table updates */</div><div class='add'>+	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {</div><div class='add'>+		if (xe_vma_is_userptr(vma)) {</div><div class='add'>+			WARN_ON_ONCE(!mmu_interval_check_retry</div><div class='add'>+				     (&amp;vma-&gt;userptr.notifier,</div><div class='add'>+				      vma-&gt;userptr.notifier_seq));</div><div class='add'>+			WARN_ON_ONCE(!dma_resv_test_signaled(xe_vm_resv(xe_vma_vm(vma)),</div><div class='add'>+							     DMA_RESV_USAGE_BOOKKEEP));</div><div class='add'>+</div><div class='add'>+		} else {</div><div class='add'>+			xe_bo_assert_held(xe_vma_bo(vma));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (xe_pt_zap_ptes(tile, vma)) {</div><div class='add'>+			tile_needs_invalidate |= BIT(id);</div><div class='add'>+			xe_device_wmb(xe);</div><div class='add'>+			/*</div><div class='add'>+			 * FIXME: We potentially need to invalidate multiple</div><div class='add'>+			 * GTs within the tile</div><div class='add'>+			 */</div><div class='add'>+			seqno[id] = xe_gt_tlb_invalidation_vma(tile-&gt;primary_gt, NULL, vma);</div><div class='add'>+			if (seqno[id] &lt; 0)</div><div class='add'>+				return seqno[id];</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for_each_tile(tile, xe, id) {</div><div class='add'>+		if (tile_needs_invalidate &amp; BIT(id)) {</div><div class='add'>+			ret = xe_gt_tlb_invalidation_wait(tile-&gt;primary_gt, seqno[id]);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vma-&gt;usm.tile_invalidated = vma-&gt;tile_mask;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id)</div><div class='add'>+{</div><div class='add'>+	struct drm_gpuva *gpuva;</div><div class='add'>+	bool is_vram;</div><div class='add'>+	uint64_t addr;</div><div class='add'>+</div><div class='add'>+	if (!down_read_trylock(&amp;vm-&gt;lock)) {</div><div class='add'>+		drm_printf(p, " Failed to acquire VM lock to dump capture");</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	if (vm-&gt;pt_root[gt_id]) {</div><div class='add'>+		addr = xe_bo_addr(vm-&gt;pt_root[gt_id]-&gt;bo, 0, XE_PAGE_SIZE);</div><div class='add'>+		is_vram = xe_bo_is_vram(vm-&gt;pt_root[gt_id]-&gt;bo);</div><div class='add'>+		drm_printf(p, " VM root: A:0x%llx %s\n", addr,</div><div class='add'>+			   is_vram ? "VRAM" : "SYS");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	drm_gpuvm_for_each_va(gpuva, &amp;vm-&gt;gpuvm) {</div><div class='add'>+		struct xe_vma *vma = gpuva_to_vma(gpuva);</div><div class='add'>+		bool is_userptr = xe_vma_is_userptr(vma);</div><div class='add'>+		bool is_null = xe_vma_is_null(vma);</div><div class='add'>+</div><div class='add'>+		if (is_null) {</div><div class='add'>+			addr = 0;</div><div class='add'>+		} else if (is_userptr) {</div><div class='add'>+			struct xe_res_cursor cur;</div><div class='add'>+</div><div class='add'>+			if (vma-&gt;userptr.sg) {</div><div class='add'>+				xe_res_first_sg(vma-&gt;userptr.sg, 0, XE_PAGE_SIZE,</div><div class='add'>+						&amp;cur);</div><div class='add'>+				addr = xe_res_dma(&amp;cur);</div><div class='add'>+			} else {</div><div class='add'>+				addr = 0;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			addr = __xe_bo_addr(xe_vma_bo(vma), 0, XE_PAGE_SIZE);</div><div class='add'>+			is_vram = xe_bo_is_vram(xe_vma_bo(vma));</div><div class='add'>+		}</div><div class='add'>+		drm_printf(p, " [%016llx-%016llx] S:0x%016llx A:%016llx %s\n",</div><div class='add'>+			   xe_vma_start(vma), xe_vma_end(vma) - 1,</div><div class='add'>+			   xe_vma_size(vma),</div><div class='add'>+			   addr, is_null ? "NULL" : is_userptr ? "USR" :</div><div class='add'>+			   is_vram ? "VRAM" : "SYS");</div><div class='add'>+	}</div><div class='add'>+	up_read(&amp;vm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h<br/>new file mode 100644<br/>index 000000000000..cf2f96e8c1ab<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_vm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm.h</a></div><div class='hunk'>@@ -0,0 +1,263 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2021 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_VM_H_</div><div class='add'>+#define _XE_VM_H_</div><div class='add'>+</div><div class='add'>+#include "xe_bo_types.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_map.h"</div><div class='add'>+#include "xe_vm_types.h"</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct drm_file;</div><div class='add'>+</div><div class='add'>+struct ttm_buffer_object;</div><div class='add'>+struct ttm_validate_buffer;</div><div class='add'>+</div><div class='add'>+struct xe_exec_queue;</div><div class='add'>+struct xe_file;</div><div class='add'>+struct xe_sync_entry;</div><div class='add'>+struct drm_exec;</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags);</div><div class='add'>+</div><div class='add'>+struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id);</div><div class='add'>+int xe_vma_cmp_vma_cb(const void *key, const struct rb_node *node);</div><div class='add'>+</div><div class='add'>+static inline struct xe_vm *xe_vm_get(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	drm_gpuvm_get(&amp;vm-&gt;gpuvm);</div><div class='add'>+	return vm;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void xe_vm_put(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	drm_gpuvm_put(&amp;vm-&gt;gpuvm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vm_lock(struct xe_vm *vm, bool intr);</div><div class='add'>+</div><div class='add'>+void xe_vm_unlock(struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_is_closed(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	/* Only guaranteed not to change when vm-&gt;lock is held */</div><div class='add'>+	return !vm-&gt;size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_is_banned(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;flags &amp; XE_VM_FLAG_BANNED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_is_closed_or_banned(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;vm-&gt;lock);</div><div class='add'>+	return xe_vm_is_closed(vm) || xe_vm_is_banned(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct xe_vma *</div><div class='add'>+xe_vm_find_overlapping_vma(struct xe_vm *vm, u64 start, u64 range);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_has_scratch() - Whether the vm is configured for scratch PTEs</div><div class='add'>+ * @vm: The vm</div><div class='add'>+ *</div><div class='add'>+ * Return: whether the vm populates unmapped areas with scratch PTEs</div><div class='add'>+ */</div><div class='add'>+static inline bool xe_vm_has_scratch(const struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;flags &amp; XE_VM_FLAG_SCRATCH_PAGE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * gpuvm_to_vm() - Return the embedding xe_vm from a struct drm_gpuvm pointer</div><div class='add'>+ * @gpuvm: The struct drm_gpuvm pointer</div><div class='add'>+ *</div><div class='add'>+ * Return: Pointer to the embedding struct xe_vm.</div><div class='add'>+ */</div><div class='add'>+static inline struct xe_vm *gpuvm_to_vm(struct drm_gpuvm *gpuvm)</div><div class='add'>+{</div><div class='add'>+	return container_of(gpuvm, struct xe_vm, gpuvm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_vm *gpuva_to_vm(struct drm_gpuva *gpuva)</div><div class='add'>+{</div><div class='add'>+	return gpuvm_to_vm(gpuva-&gt;vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_vma *gpuva_to_vma(struct drm_gpuva *gpuva)</div><div class='add'>+{</div><div class='add'>+	return container_of(gpuva, struct xe_vma, gpuva);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_vma_op *gpuva_op_to_vma_op(struct drm_gpuva_op *op)</div><div class='add'>+{</div><div class='add'>+	return container_of(op, struct xe_vma_op, base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Provide accessors for vma members to facilitate easy change of</div><div class='add'>+ * implementation.</div><div class='add'>+ */</div><div class='add'>+static inline u64 xe_vma_start(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.va.addr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 xe_vma_size(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.va.range;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 xe_vma_end(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return xe_vma_start(vma) + xe_vma_size(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 xe_vma_bo_offset(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.gem.offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_bo *xe_vma_bo(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return !vma-&gt;gpuva.gem.obj ? NULL :</div><div class='add'>+		container_of(vma-&gt;gpuva.gem.obj, struct xe_bo, ttm.base);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_vm *xe_vma_vm(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return container_of(vma-&gt;gpuva.vm, struct xe_vm, gpuvm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vma_read_only(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.flags &amp; XE_VMA_READ_ONLY;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 xe_vma_userptr(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.gem.offset;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vma_is_null(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return vma-&gt;gpuva.flags &amp; DRM_GPUVA_SPARSE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vma_has_no_bo(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return !xe_vma_bo(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vma_is_userptr(struct xe_vma *vma)</div><div class='add'>+{</div><div class='add'>+	return xe_vma_has_no_bo(vma) &amp;&amp; !xe_vma_is_null(vma);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+int xe_vm_create_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+		       struct drm_file *file);</div><div class='add'>+int xe_vm_destroy_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			struct drm_file *file);</div><div class='add'>+int xe_vm_bind_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+		     struct drm_file *file);</div><div class='add'>+</div><div class='add'>+void xe_vm_close_and_put(struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_in_fault_mode(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;flags &amp; XE_VM_FLAG_FAULT_MODE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_in_lr_mode(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return vm-&gt;flags &amp; XE_VM_FLAG_LR_MODE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool xe_vm_in_preempt_fence_mode(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return xe_vm_in_lr_mode(vm) &amp;&amp; !xe_vm_in_fault_mode(vm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q);</div><div class='add'>+void xe_vm_remove_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q);</div><div class='add'>+</div><div class='add'>+int xe_vm_userptr_pin(struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+int __xe_vm_userptr_needs_repin(struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+int xe_vm_userptr_check_repin(struct xe_vm *vm);</div><div class='add'>+</div><div class='add'>+struct dma_fence *xe_vm_rebind(struct xe_vm *vm, bool rebind_worker);</div><div class='add'>+</div><div class='add'>+int xe_vm_invalidate_vma(struct xe_vma *vma);</div><div class='add'>+</div><div class='add'>+extern struct ttm_device_funcs xe_ttm_funcs;</div><div class='add'>+</div><div class='add'>+static inline void xe_vm_queue_rebind_worker(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	xe_assert(vm-&gt;xe, xe_vm_in_preempt_fence_mode(vm));</div><div class='add'>+	queue_work(vm-&gt;xe-&gt;ordered_wq, &amp;vm-&gt;preempt.rebind_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_reactivate_rebind() - Reactivate the rebind functionality on compute</div><div class='add'>+ * vms.</div><div class='add'>+ * @vm: The vm.</div><div class='add'>+ *</div><div class='add'>+ * If the rebind functionality on a compute vm was disabled due</div><div class='add'>+ * to nothing to execute. Reactivate it and run the rebind worker.</div><div class='add'>+ * This function should be called after submitting a batch to a compute vm.</div><div class='add'>+ */</div><div class='add'>+static inline void xe_vm_reactivate_rebind(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	if (xe_vm_in_preempt_fence_mode(vm) &amp;&amp; vm-&gt;preempt.rebind_deactivated) {</div><div class='add'>+		vm-&gt;preempt.rebind_deactivated = false;</div><div class='add'>+		xe_vm_queue_rebind_worker(vm);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_vma_userptr_pin_pages(struct xe_vma *vma);</div><div class='add'>+</div><div class='add'>+int xe_vma_userptr_check_repin(struct xe_vma *vma);</div><div class='add'>+</div><div class='add'>+bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end);</div><div class='add'>+</div><div class='add'>+int xe_analyze_vm(struct drm_printer *p, struct xe_vm *vm, int gt_id);</div><div class='add'>+</div><div class='add'>+int xe_vm_prepare_vma(struct drm_exec *exec, struct xe_vma *vma,</div><div class='add'>+		      unsigned int num_shared);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_resv() - Return's the vm's reservation object</div><div class='add'>+ * @vm: The vm</div><div class='add'>+ *</div><div class='add'>+ * Return: Pointer to the vm's reservation object.</div><div class='add'>+ */</div><div class='add'>+static inline struct dma_resv *xe_vm_resv(struct xe_vm *vm)</div><div class='add'>+{</div><div class='add'>+	return drm_gpuvm_resv(&amp;vm-&gt;gpuvm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_vm_assert_held(vm) - Assert that the vm's reservation object is held.</div><div class='add'>+ * @vm: The vm</div><div class='add'>+ */</div><div class='add'>+#define xe_vm_assert_held(vm) dma_resv_assert_held(xe_vm_resv(vm))</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)</div><div class='add'>+#define vm_dbg drm_dbg</div><div class='add'>+#else</div><div class='add'>+__printf(2, 3)</div><div class='add'>+static inline void vm_dbg(const struct drm_device *dev,</div><div class='add'>+			  const char *format, ...)</div><div class='add'>+{ /* noop */ }</div><div class='add'>+#endif</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_vm_doc.h b/drivers/gpu/drm/xe/xe_vm_doc.h<br/>new file mode 100644<br/>index 000000000000..bdc6659891a5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_vm_doc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm_doc.h</a></div><div class='hunk'>@@ -0,0 +1,555 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_VM_DOC_H_</div><div class='add'>+#define _XE_VM_DOC_H_</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: XE VM (user address space)</div><div class='add'>+ *</div><div class='add'>+ * VM creation</div><div class='add'>+ * ===========</div><div class='add'>+ *</div><div class='add'>+ * Allocate a physical page for root of the page table structure, create default</div><div class='add'>+ * bind engine, and return a handle to the user.</div><div class='add'>+ *</div><div class='add'>+ * Scratch page</div><div class='add'>+ * ------------</div><div class='add'>+ *</div><div class='add'>+ * If the VM is created with the flag, DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE, set the</div><div class='add'>+ * entire page table structure defaults pointing to blank page allocated by the</div><div class='add'>+ * VM. Invalid memory access rather than fault just read / write to this page.</div><div class='add'>+ *</div><div class='add'>+ * VM bind (create GPU mapping for a BO or userptr)</div><div class='add'>+ * ================================================</div><div class='add'>+ *</div><div class='add'>+ * Creates GPU mapings for a BO or userptr within a VM. VM binds uses the same</div><div class='add'>+ * in / out fence interface (struct drm_xe_sync) as execs which allows users to</div><div class='add'>+ * think of binds and execs as more or less the same operation.</div><div class='add'>+ *</div><div class='add'>+ * Operations</div><div class='add'>+ * ----------</div><div class='add'>+ *</div><div class='add'>+ * DRM_XE_VM_BIND_OP_MAP		- Create mapping for a BO</div><div class='add'>+ * DRM_XE_VM_BIND_OP_UNMAP		- Destroy mapping for a BO / userptr</div><div class='add'>+ * DRM_XE_VM_BIND_OP_MAP_USERPTR	- Create mapping for userptr</div><div class='add'>+ *</div><div class='add'>+ * Implementation details</div><div class='add'>+ * ~~~~~~~~~~~~~~~~~~~~~~</div><div class='add'>+ *</div><div class='add'>+ * All bind operations are implemented via a hybrid approach of using the CPU</div><div class='add'>+ * and GPU to modify page tables. If a new physical page is allocated in the</div><div class='add'>+ * page table structure we populate that page via the CPU and insert that new</div><div class='add'>+ * page into the existing page table structure via a GPU job. Also any existing</div><div class='add'>+ * pages in the page table structure that need to be modified also are updated</div><div class='add'>+ * via the GPU job. As the root physical page is prealloced on VM creation our</div><div class='add'>+ * GPU job will always have at least 1 update. The in / out fences are passed to</div><div class='add'>+ * this job so again this is conceptually the same as an exec.</div><div class='add'>+ *</div><div class='add'>+ * Very simple example of few binds on an empty VM with 48 bits of address space</div><div class='add'>+ * and the resulting operations:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	bind BO0 0x0-0x1000</div><div class='add'>+ *	alloc page level 3a, program PTE[0] to BO0 phys address (CPU)</div><div class='add'>+ *	alloc page level 2, program PDE[0] page level 3a phys address (CPU)</div><div class='add'>+ *	alloc page level 1, program PDE[0] page level 2 phys address (CPU)</div><div class='add'>+ *	update root PDE[0] to page level 1 phys address (GPU)</div><div class='add'>+ *</div><div class='add'>+ *	bind BO1 0x201000-0x202000</div><div class='add'>+ *	alloc page level 3b, program PTE[1] to BO1 phys address (CPU)</div><div class='add'>+ *	update page level 2 PDE[1] to page level 3b phys address (GPU)</div><div class='add'>+ *</div><div class='add'>+ *	bind BO2 0x1ff000-0x201000</div><div class='add'>+ *	update page level 3a PTE[511] to BO2 phys addres (GPU)</div><div class='add'>+ *	update page level 3b PTE[0] to BO2 phys addres + 0x1000 (GPU)</div><div class='add'>+ *</div><div class='add'>+ * GPU bypass</div><div class='add'>+ * ~~~~~~~~~~</div><div class='add'>+ *</div><div class='add'>+ * In the above example the steps using the GPU can be converted to CPU if the</div><div class='add'>+ * bind can be done immediately (all in-fences satisfied, VM dma-resv kernel</div><div class='add'>+ * slot is idle).</div><div class='add'>+ *</div><div class='add'>+ * Address space</div><div class='add'>+ * -------------</div><div class='add'>+ *</div><div class='add'>+ * Depending on platform either 48 or 57 bits of address space is supported.</div><div class='add'>+ *</div><div class='add'>+ * Page sizes</div><div class='add'>+ * ----------</div><div class='add'>+ *</div><div class='add'>+ * The minimum page size is either 4k or 64k depending on platform and memory</div><div class='add'>+ * placement (sysmem vs. VRAM). We enforce that binds must be aligned to the</div><div class='add'>+ * minimum page size.</div><div class='add'>+ *</div><div class='add'>+ * Larger pages (2M or 1GB) can be used for BOs in VRAM, the BO physical address</div><div class='add'>+ * is aligned to the larger pages size, and VA is aligned to the larger page</div><div class='add'>+ * size. Larger pages for userptrs / BOs in sysmem should be possible but is not</div><div class='add'>+ * yet implemented.</div><div class='add'>+ *</div><div class='add'>+ * Sync error handling mode</div><div class='add'>+ * ------------------------</div><div class='add'>+ *</div><div class='add'>+ * In both modes during the bind IOCTL the user input is validated. In sync</div><div class='add'>+ * error handling mode the newly bound BO is validated (potentially moved back</div><div class='add'>+ * to a region of memory where is can be used), page tables are updated by the</div><div class='add'>+ * CPU and the job to do the GPU binds is created in the IOCTL itself. This step</div><div class='add'>+ * can fail due to memory pressure. The user can recover by freeing memory and</div><div class='add'>+ * trying this operation again.</div><div class='add'>+ *</div><div class='add'>+ * Async error handling mode</div><div class='add'>+ * -------------------------</div><div class='add'>+ *</div><div class='add'>+ * In async error handling the step of validating the BO, updating page tables,</div><div class='add'>+ * and generating a job are deferred to an async worker. As this step can now</div><div class='add'>+ * fail after the IOCTL has reported success we need an error handling flow for</div><div class='add'>+ * which the user can recover from.</div><div class='add'>+ *</div><div class='add'>+ * The solution is for a user to register a user address with the VM which the</div><div class='add'>+ * VM uses to report errors to. The ufence wait interface can be used to wait on</div><div class='add'>+ * a VM going into an error state. Once an error is reported the VM's async</div><div class='add'>+ * worker is paused. While the VM's async worker is paused sync,</div><div class='add'>+ * DRM_XE_VM_BIND_OP_UNMAP operations are allowed (this can free memory). Once the</div><div class='add'>+ * uses believe the error state is fixed, the async worker can be resumed via</div><div class='add'>+ * XE_VM_BIND_OP_RESTART operation. When VM async bind work is restarted, the</div><div class='add'>+ * first operation processed is the operation that caused the original error.</div><div class='add'>+ *</div><div class='add'>+ * Bind queues / engines</div><div class='add'>+ * ---------------------</div><div class='add'>+ *</div><div class='add'>+ * Think of the case where we have two bind operations A + B and are submitted</div><div class='add'>+ * in that order. A has in fences while B has none. If using a single bind</div><div class='add'>+ * queue, B is now blocked on A's in fences even though it is ready to run. This</div><div class='add'>+ * example is a real use case for VK sparse binding. We work around this</div><div class='add'>+ * limitation by implementing bind engines.</div><div class='add'>+ *</div><div class='add'>+ * In the bind IOCTL the user can optionally pass in an engine ID which must map</div><div class='add'>+ * to an engine which is of the special class DRM_XE_ENGINE_CLASS_VM_BIND.</div><div class='add'>+ * Underneath this is a really virtual engine that can run on any of the copy</div><div class='add'>+ * hardware engines. The job(s) created each IOCTL are inserted into this</div><div class='add'>+ * engine's ring. In the example above if A and B have different bind engines B</div><div class='add'>+ * is free to pass A. If the engine ID field is omitted, the default bind queue</div><div class='add'>+ * for the VM is used.</div><div class='add'>+ *</div><div class='add'>+ * TODO: Explain race in issue 41 and how we solve it</div><div class='add'>+ *</div><div class='add'>+ * Array of bind operations</div><div class='add'>+ * ------------------------</div><div class='add'>+ *</div><div class='add'>+ * The uAPI allows multiple binds operations to be passed in via a user array,</div><div class='add'>+ * of struct drm_xe_vm_bind_op, in a single VM bind IOCTL. This interface</div><div class='add'>+ * matches the VK sparse binding API. The implementation is rather simple, parse</div><div class='add'>+ * the array into a list of operations, pass the in fences to the first operation,</div><div class='add'>+ * and pass the out fences to the last operation. The ordered nature of a bind</div><div class='add'>+ * engine makes this possible.</div><div class='add'>+ *</div><div class='add'>+ * Munmap semantics for unbinds</div><div class='add'>+ * ----------------------------</div><div class='add'>+ *</div><div class='add'>+ * Munmap allows things like:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	0x0000-0x2000 and 0x3000-0x5000 have mappings</div><div class='add'>+ *	Munmap 0x1000-0x4000, results in mappings 0x0000-0x1000 and 0x4000-0x5000</div><div class='add'>+ *</div><div class='add'>+ * To support this semantic in the above example we decompose the above example</div><div class='add'>+ * into 4 operations:</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	unbind 0x0000-0x2000</div><div class='add'>+ *	unbind 0x3000-0x5000</div><div class='add'>+ *	rebind 0x0000-0x1000</div><div class='add'>+ *	rebind 0x4000-0x5000</div><div class='add'>+ *</div><div class='add'>+ * Why not just do a partial unbind of 0x1000-0x2000 and 0x3000-0x4000? This</div><div class='add'>+ * falls apart when using large pages at the edges and the unbind forces us to</div><div class='add'>+ * use a smaller page size. For simplity we always issue a set of unbinds</div><div class='add'>+ * unmapping anything in the range and at most 2 rebinds on the edges.</div><div class='add'>+ *</div><div class='add'>+ * Similar to an array of binds, in fences are passed to the first operation and</div><div class='add'>+ * out fences are signaled on the last operation.</div><div class='add'>+ *</div><div class='add'>+ * In this example there is a window of time where 0x0000-0x1000 and</div><div class='add'>+ * 0x4000-0x5000 are invalid but the user didn't ask for these addresses to be</div><div class='add'>+ * removed from the mapping. To work around this we treat any munmap style</div><div class='add'>+ * unbinds which require a rebind as a kernel operations (BO eviction or userptr</div><div class='add'>+ * invalidation). The first operation waits on the VM's</div><div class='add'>+ * DMA_RESV_USAGE_PREEMPT_FENCE slots (waits for all pending jobs on VM to</div><div class='add'>+ * complete / triggers preempt fences) and the last operation is installed in</div><div class='add'>+ * the VM's DMA_RESV_USAGE_KERNEL slot (blocks future jobs / resume compute mode</div><div class='add'>+ * VM). The caveat is all dma-resv slots must be updated atomically with respect</div><div class='add'>+ * to execs and compute mode rebind worker. To accomplish this, hold the</div><div class='add'>+ * vm-&gt;lock in write mode from the first operation until the last.</div><div class='add'>+ *</div><div class='add'>+ * Deferred binds in fault mode</div><div class='add'>+ * ----------------------------</div><div class='add'>+ *</div><div class='add'>+ * In a VM is in fault mode (TODO: link to fault mode), new bind operations that</div><div class='add'>+ * create mappings are by default are deferred to the page fault handler (first</div><div class='add'>+ * use). This behavior can be overriden by setting the flag</div><div class='add'>+ * DRM_XE_VM_BIND_FLAG_IMMEDIATE which indicates to creating the mapping</div><div class='add'>+ * immediately.</div><div class='add'>+ *</div><div class='add'>+ * User pointer</div><div class='add'>+ * ============</div><div class='add'>+ *</div><div class='add'>+ * User pointers are user allocated memory (malloc'd, mmap'd, etc..) for which the</div><div class='add'>+ * user wants to create a GPU mapping. Typically in other DRM drivers a dummy BO</div><div class='add'>+ * was created and then a binding was created. We bypass creating a dummy BO in</div><div class='add'>+ * XE and simply create a binding directly from the userptr.</div><div class='add'>+ *</div><div class='add'>+ * Invalidation</div><div class='add'>+ * ------------</div><div class='add'>+ *</div><div class='add'>+ * Since this a core kernel managed memory the kernel can move this memory</div><div class='add'>+ * whenever it wants. We register an invalidation MMU notifier to alert XE when</div><div class='add'>+ * a user poiter is about to move. The invalidation notifier needs to block</div><div class='add'>+ * until all pending users (jobs or compute mode engines) of the userptr are</div><div class='add'>+ * idle to ensure no faults. This done by waiting on all of VM's dma-resv slots.</div><div class='add'>+ *</div><div class='add'>+ * Rebinds</div><div class='add'>+ * -------</div><div class='add'>+ *</div><div class='add'>+ * Either the next exec (non-compute) or rebind worker (compute mode) will</div><div class='add'>+ * rebind the userptr. The invalidation MMU notifier kicks the rebind worker</div><div class='add'>+ * after the VM dma-resv wait if the VM is in compute mode.</div><div class='add'>+ *</div><div class='add'>+ * Compute mode</div><div class='add'>+ * ============</div><div class='add'>+ *</div><div class='add'>+ * A VM in compute mode enables long running workloads and ultra low latency</div><div class='add'>+ * submission (ULLS). ULLS is implemented via a continuously running batch +</div><div class='add'>+ * semaphores. This enables to the user to insert jump to new batch commands</div><div class='add'>+ * into the continuously running batch. In both cases these batches exceed the</div><div class='add'>+ * time a dma fence is allowed to exist for before signaling, as such dma fences</div><div class='add'>+ * are not used when a VM is in compute mode. User fences (TODO: link user fence</div><div class='add'>+ * doc) are used instead to signal operation's completion.</div><div class='add'>+ *</div><div class='add'>+ * Preempt fences</div><div class='add'>+ * --------------</div><div class='add'>+ *</div><div class='add'>+ * If the kernel decides to move memory around (either userptr invalidate, BO</div><div class='add'>+ * eviction, or mumap style unbind which results in a rebind) and a batch is</div><div class='add'>+ * running on an engine, that batch can fault or cause a memory corruption as</div><div class='add'>+ * page tables for the moved memory are no longer valid. To work around this we</div><div class='add'>+ * introduce the concept of preempt fences. When sw signaling is enabled on a</div><div class='add'>+ * preempt fence it tells the submission backend to kick that engine off the</div><div class='add'>+ * hardware and the preempt fence signals when the engine is off the hardware.</div><div class='add'>+ * Once all preempt fences are signaled for a VM the kernel can safely move the</div><div class='add'>+ * memory and kick the rebind worker which resumes all the engines execution.</div><div class='add'>+ *</div><div class='add'>+ * A preempt fence, for every engine using the VM, is installed the VM's</div><div class='add'>+ * dma-resv DMA_RESV_USAGE_PREEMPT_FENCE slot. The same preempt fence, for every</div><div class='add'>+ * engine using the VM, is also installed into the same dma-resv slot of every</div><div class='add'>+ * external BO mapped in the VM.</div><div class='add'>+ *</div><div class='add'>+ * Rebind worker</div><div class='add'>+ * -------------</div><div class='add'>+ *</div><div class='add'>+ * The rebind worker is very similar to an exec. It is resposible for rebinding</div><div class='add'>+ * evicted BOs or userptrs, waiting on those operations, installing new preempt</div><div class='add'>+ * fences, and finally resuming executing of engines in the VM.</div><div class='add'>+ *</div><div class='add'>+ * Flow</div><div class='add'>+ * ~~~~</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	&lt;----------------------------------------------------------------------|</div><div class='add'>+ *	Check if VM is closed, if so bail out                                  |</div><div class='add'>+ *	Lock VM global lock in read mode                                       |</div><div class='add'>+ *	Pin userptrs (also finds userptr invalidated since last rebind worker) |</div><div class='add'>+ *	Lock VM dma-resv and external BOs dma-resv                             |</div><div class='add'>+ *	Validate BOs that have been evicted                                    |</div><div class='add'>+ *	Wait on and allocate new preempt fences for every engine using the VM  |</div><div class='add'>+ *	Rebind invalidated userptrs + evicted BOs                              |</div><div class='add'>+ *	Wait on last rebind fence                                              |</div><div class='add'>+ *	Wait VM's DMA_RESV_USAGE_KERNEL dma-resv slot                          |</div><div class='add'>+ *	Install preeempt fences and issue resume for every engine using the VM |</div><div class='add'>+ *	Check if any userptrs invalidated since pin                            |</div><div class='add'>+ *		Squash resume for all engines                                  |</div><div class='add'>+ *		Unlock all                                                     |</div><div class='add'>+ *		Wait all VM's dma-resv slots                                   |</div><div class='add'>+ *		Retry ----------------------------------------------------------</div><div class='add'>+ *	Release all engines waiting to resume</div><div class='add'>+ *	Unlock all</div><div class='add'>+ *</div><div class='add'>+ * Timeslicing</div><div class='add'>+ * -----------</div><div class='add'>+ *</div><div class='add'>+ * In order to prevent an engine from continuously being kicked off the hardware</div><div class='add'>+ * and making no forward progress an engine has a period of time it allowed to</div><div class='add'>+ * run after resume before it can be kicked off again. This effectively gives</div><div class='add'>+ * each engine a timeslice.</div><div class='add'>+ *</div><div class='add'>+ * Handling multiple GTs</div><div class='add'>+ * =====================</div><div class='add'>+ *</div><div class='add'>+ * If a GT has slower access to some regions and the page table structure are in</div><div class='add'>+ * the slow region, the performance on that GT could adversely be affected. To</div><div class='add'>+ * work around this we allow a VM page tables to be shadowed in multiple GTs.</div><div class='add'>+ * When VM is created, a default bind engine and PT table structure are created</div><div class='add'>+ * on each GT.</div><div class='add'>+ *</div><div class='add'>+ * Binds can optionally pass in a mask of GTs where a mapping should be created,</div><div class='add'>+ * if this mask is zero then default to all the GTs where the VM has page</div><div class='add'>+ * tables.</div><div class='add'>+ *</div><div class='add'>+ * The implementation for this breaks down into a bunch for_each_gt loops in</div><div class='add'>+ * various places plus exporting a composite fence for multi-GT binds to the</div><div class='add'>+ * user.</div><div class='add'>+ *</div><div class='add'>+ * Fault mode (unified shared memory)</div><div class='add'>+ * ==================================</div><div class='add'>+ *</div><div class='add'>+ * A VM in fault mode can be enabled on devices that support page faults. If</div><div class='add'>+ * page faults are enabled, using dma fences can potentially induce a deadlock:</div><div class='add'>+ * A pending page fault can hold up the GPU work which holds up the dma fence</div><div class='add'>+ * signaling, and memory allocation is usually required to resolve a page</div><div class='add'>+ * fault, but memory allocation is not allowed to gate dma fence signaling. As</div><div class='add'>+ * such, dma fences are not allowed when VM is in fault mode. Because dma-fences</div><div class='add'>+ * are not allowed, long running workloads and ULLS are enabled on a faulting</div><div class='add'>+ * VM.</div><div class='add'>+ *</div><div class='add'>+ * Defered VM binds</div><div class='add'>+ * ----------------</div><div class='add'>+ *</div><div class='add'>+ * By default, on a faulting VM binds just allocate the VMA and the actual</div><div class='add'>+ * updating of the page tables is defered to the page fault handler. This</div><div class='add'>+ * behavior can be overridden by setting the flag DRM_XE_VM_BIND_FLAG_IMMEDIATE in</div><div class='add'>+ * the VM bind which will then do the bind immediately.</div><div class='add'>+ *</div><div class='add'>+ * Page fault handler</div><div class='add'>+ * ------------------</div><div class='add'>+ *</div><div class='add'>+ * Page faults are received in the G2H worker under the CT lock which is in the</div><div class='add'>+ * path of dma fences (no memory allocations are allowed, faults require memory</div><div class='add'>+ * allocations) thus we cannot process faults under the CT lock. Another issue</div><div class='add'>+ * is faults issue TLB invalidations which require G2H credits and we cannot</div><div class='add'>+ * allocate G2H credits in the G2H handlers without deadlocking. Lastly, we do</div><div class='add'>+ * not want the CT lock to be an outer lock of the VM global lock (VM global</div><div class='add'>+ * lock required to fault processing).</div><div class='add'>+ *</div><div class='add'>+ * To work around the above issue with processing faults in the G2H worker, we</div><div class='add'>+ * sink faults to a buffer which is large enough to sink all possible faults on</div><div class='add'>+ * the GT (1 per hardware engine) and kick a worker to process the faults. Since</div><div class='add'>+ * the page faults G2H are already received in a worker, kicking another worker</div><div class='add'>+ * adds more latency to a critical performance path. We add a fast path in the</div><div class='add'>+ * G2H irq handler which looks at first G2H and if it is a page fault we sink</div><div class='add'>+ * the fault to the buffer and kick the worker to process the fault. TLB</div><div class='add'>+ * invalidation responses are also in the critical path so these can also be</div><div class='add'>+ * processed in this fast path.</div><div class='add'>+ *</div><div class='add'>+ * Multiple buffers and workers are used and hashed over based on the ASID so</div><div class='add'>+ * faults from different VMs can be processed in parallel.</div><div class='add'>+ *</div><div class='add'>+ * The page fault handler itself is rather simple, flow is below.</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	Lookup VM from ASID in page fault G2H</div><div class='add'>+ *	Lock VM global lock in read mode</div><div class='add'>+ *	Lookup VMA from address in page fault G2H</div><div class='add'>+ *	Check if VMA is valid, if not bail</div><div class='add'>+ *	Check if VMA's BO has backing store, if not allocate</div><div class='add'>+ *	&lt;----------------------------------------------------------------------|</div><div class='add'>+ *	If userptr, pin pages                                                  |</div><div class='add'>+ *	Lock VM &amp; BO dma-resv locks                                            |</div><div class='add'>+ *	If atomic fault, migrate to VRAM, else validate BO location            |</div><div class='add'>+ *	Issue rebind                                                           |</div><div class='add'>+ *	Wait on rebind to complete                                             |</div><div class='add'>+ *	Check if userptr invalidated since pin                                 |</div><div class='add'>+ *		Drop VM &amp; BO dma-resv locks                                    |</div><div class='add'>+ *		Retry ----------------------------------------------------------</div><div class='add'>+ *	Unlock all</div><div class='add'>+ *	Issue blocking TLB invalidation                                        |</div><div class='add'>+ *	Send page fault response to GuC</div><div class='add'>+ *</div><div class='add'>+ * Access counters</div><div class='add'>+ * ---------------</div><div class='add'>+ *</div><div class='add'>+ * Access counters can be configured to trigger a G2H indicating the device is</div><div class='add'>+ * accessing VMAs in system memory frequently as hint to migrate those VMAs to</div><div class='add'>+ * VRAM.</div><div class='add'>+ *</div><div class='add'>+ * Same as the page fault handler, access counters G2H cannot be processed the</div><div class='add'>+ * G2H worker under the CT lock. Again we use a buffer to sink access counter</div><div class='add'>+ * G2H. Unlike page faults there is no upper bound so if the buffer is full we</div><div class='add'>+ * simply drop the G2H. Access counters are a best case optimization and it is</div><div class='add'>+ * safe to drop these unlike page faults.</div><div class='add'>+ *</div><div class='add'>+ * The access counter handler itself is rather simple flow is below.</div><div class='add'>+ *</div><div class='add'>+ * .. code-block::</div><div class='add'>+ *</div><div class='add'>+ *	Lookup VM from ASID in access counter G2H</div><div class='add'>+ *	Lock VM global lock in read mode</div><div class='add'>+ *	Lookup VMA from address in access counter G2H</div><div class='add'>+ *	If userptr, bail nothing to do</div><div class='add'>+ *	Lock VM &amp; BO dma-resv locks</div><div class='add'>+ *	Issue migration to VRAM</div><div class='add'>+ *	Unlock all</div><div class='add'>+ *</div><div class='add'>+ * Notice no rebind is issued in the access counter handler as the rebind will</div><div class='add'>+ * be issued on next page fault.</div><div class='add'>+ *</div><div class='add'>+ * Cavets with eviction / user pointer invalidation</div><div class='add'>+ * ------------------------------------------------</div><div class='add'>+ *</div><div class='add'>+ * In the case of eviction and user pointer invalidation on a faulting VM, there</div><div class='add'>+ * is no need to issue a rebind rather we just need to blow away the page tables</div><div class='add'>+ * for the VMAs and the page fault handler will rebind the VMAs when they fault.</div><div class='add'>+ * The cavet is to update / read the page table structure the VM global lock is</div><div class='add'>+ * neeeed. In both the case of eviction and user pointer invalidation locks are</div><div class='add'>+ * held which make acquiring the VM global lock impossible. To work around this</div><div class='add'>+ * every VMA maintains a list of leaf page table entries which should be written</div><div class='add'>+ * to zero to blow away the VMA's page tables. After writing zero to these</div><div class='add'>+ * entries a blocking TLB invalidate is issued. At this point it is safe for the</div><div class='add'>+ * kernel to move the VMA's memory around. This is a necessary lockless</div><div class='add'>+ * algorithm and is safe as leafs cannot be changed while either an eviction or</div><div class='add'>+ * userptr invalidation is occurring.</div><div class='add'>+ *</div><div class='add'>+ * Locking</div><div class='add'>+ * =======</div><div class='add'>+ *</div><div class='add'>+ * VM locking protects all of the core data paths (bind operations, execs,</div><div class='add'>+ * evictions, and compute mode rebind worker) in XE.</div><div class='add'>+ *</div><div class='add'>+ * Locks</div><div class='add'>+ * -----</div><div class='add'>+ *</div><div class='add'>+ * VM global lock (vm-&gt;lock) - rw semaphore lock. Outer most lock which protects</div><div class='add'>+ * the list of userptrs mapped in the VM, the list of engines using this VM, and</div><div class='add'>+ * the array of external BOs mapped in the VM. When adding or removing any of the</div><div class='add'>+ * aforemented state from the VM should acquire this lock in write mode. The VM</div><div class='add'>+ * bind path also acquires this lock in write while the exec / compute mode</div><div class='add'>+ * rebind worker acquire this lock in read mode.</div><div class='add'>+ *</div><div class='add'>+ * VM dma-resv lock (vm-&gt;ttm.base.resv-&gt;lock) - WW lock. Protects VM dma-resv</div><div class='add'>+ * slots which is shared with any private BO in the VM. Expected to be acquired</div><div class='add'>+ * during VM binds, execs, and compute mode rebind worker. This lock is also</div><div class='add'>+ * held when private BOs are being evicted.</div><div class='add'>+ *</div><div class='add'>+ * external BO dma-resv lock (bo-&gt;ttm.base.resv-&gt;lock) - WW lock. Protects</div><div class='add'>+ * external BO dma-resv slots. Expected to be acquired during VM binds (in</div><div class='add'>+ * addition to the VM dma-resv lock). All external BO dma-locks within a VM are</div><div class='add'>+ * expected to be acquired (in addition to the VM dma-resv lock) during execs</div><div class='add'>+ * and the compute mode rebind worker. This lock is also held when an external</div><div class='add'>+ * BO is being evicted.</div><div class='add'>+ *</div><div class='add'>+ * Putting it all together</div><div class='add'>+ * -----------------------</div><div class='add'>+ *</div><div class='add'>+ * 1. An exec and bind operation with the same VM can't be executing at the same</div><div class='add'>+ * time (vm-&gt;lock).</div><div class='add'>+ *</div><div class='add'>+ * 2. A compute mode rebind worker and bind operation with the same VM can't be</div><div class='add'>+ * executing at the same time (vm-&gt;lock).</div><div class='add'>+ *</div><div class='add'>+ * 3. We can't add / remove userptrs or external BOs to a VM while an exec with</div><div class='add'>+ * the same VM is executing (vm-&gt;lock).</div><div class='add'>+ *</div><div class='add'>+ * 4. We can't add / remove userptrs, external BOs, or engines to a VM while a</div><div class='add'>+ * compute mode rebind worker with the same VM is executing (vm-&gt;lock).</div><div class='add'>+ *</div><div class='add'>+ * 5. Evictions within a VM can't be happen while an exec with the same VM is</div><div class='add'>+ * executing (dma-resv locks).</div><div class='add'>+ *</div><div class='add'>+ * 6. Evictions within a VM can't be happen while a compute mode rebind worker</div><div class='add'>+ * with the same VM is executing (dma-resv locks).</div><div class='add'>+ *</div><div class='add'>+ * dma-resv usage</div><div class='add'>+ * ==============</div><div class='add'>+ *</div><div class='add'>+ * As previously stated to enforce the ordering of kernel ops (eviction, userptr</div><div class='add'>+ * invalidation, munmap style unbinds which result in a rebind), rebinds during</div><div class='add'>+ * execs, execs, and resumes in the rebind worker we use both the VMs and</div><div class='add'>+ * external BOs dma-resv slots. Let try to make this as clear as possible.</div><div class='add'>+ *</div><div class='add'>+ * Slot installation</div><div class='add'>+ * -----------------</div><div class='add'>+ *</div><div class='add'>+ * 1. Jobs from kernel ops install themselves into the DMA_RESV_USAGE_KERNEL</div><div class='add'>+ * slot of either an external BO or VM (depends on if kernel op is operating on</div><div class='add'>+ * an external or private BO)</div><div class='add'>+ *</div><div class='add'>+ * 2. In non-compute mode, jobs from execs install themselves into the</div><div class='add'>+ * DMA_RESV_USAGE_BOOKKEEP slot of the VM</div><div class='add'>+ *</div><div class='add'>+ * 3. In non-compute mode, jobs from execs install themselves into the</div><div class='add'>+ * DMA_RESV_USAGE_WRITE slot of all external BOs in the VM</div><div class='add'>+ *</div><div class='add'>+ * 4. Jobs from binds install themselves into the DMA_RESV_USAGE_BOOKKEEP slot</div><div class='add'>+ * of the VM</div><div class='add'>+ *</div><div class='add'>+ * 5. Jobs from binds install themselves into the DMA_RESV_USAGE_BOOKKEEP slot</div><div class='add'>+ * of the external BO (if the bind is to an external BO, this is addition to #4)</div><div class='add'>+ *</div><div class='add'>+ * 6. Every engine using a compute mode VM has a preempt fence in installed into</div><div class='add'>+ * the DMA_RESV_USAGE_PREEMPT_FENCE slot of the VM</div><div class='add'>+ *</div><div class='add'>+ * 7. Every engine using a compute mode VM has a preempt fence in installed into</div><div class='add'>+ * the DMA_RESV_USAGE_PREEMPT_FENCE slot of all the external BOs in the VM</div><div class='add'>+ *</div><div class='add'>+ * Slot waiting</div><div class='add'>+ * ------------</div><div class='add'>+ *</div><div class='add'>+ * 1. The exection of all jobs from kernel ops shall wait on all slots</div><div class='add'>+ * (DMA_RESV_USAGE_PREEMPT_FENCE) of either an external BO or VM (depends on if</div><div class='add'>+ * kernel op is operating on external or private BO)</div><div class='add'>+ *</div><div class='add'>+ * 2. In non-compute mode, the exection of all jobs from rebinds in execs shall</div><div class='add'>+ * wait on the DMA_RESV_USAGE_KERNEL slot of either an external BO or VM</div><div class='add'>+ * (depends on if the rebind is operatiing on an external or private BO)</div><div class='add'>+ *</div><div class='add'>+ * 3. In non-compute mode, the exection of all jobs from execs shall wait on the</div><div class='add'>+ * last rebind job</div><div class='add'>+ *</div><div class='add'>+ * 4. In compute mode, the exection of all jobs from rebinds in the rebind</div><div class='add'>+ * worker shall wait on the DMA_RESV_USAGE_KERNEL slot of either an external BO</div><div class='add'>+ * or VM (depends on if rebind is operating on external or private BO)</div><div class='add'>+ *</div><div class='add'>+ * 5. In compute mode, resumes in rebind worker shall wait on last rebind fence</div><div class='add'>+ *</div><div class='add'>+ * 6. In compute mode, resumes in rebind worker shall wait on the</div><div class='add'>+ * DMA_RESV_USAGE_KERNEL slot of the VM</div><div class='add'>+ *</div><div class='add'>+ * Putting it all together</div><div class='add'>+ * -----------------------</div><div class='add'>+ *</div><div class='add'>+ * 1. New jobs from kernel ops are blocked behind any existing jobs from</div><div class='add'>+ * non-compute mode execs</div><div class='add'>+ *</div><div class='add'>+ * 2. New jobs from non-compute mode execs are blocked behind any existing jobs</div><div class='add'>+ * from kernel ops and rebinds</div><div class='add'>+ *</div><div class='add'>+ * 3. New jobs from kernel ops are blocked behind all preempt fences signaling in</div><div class='add'>+ * compute mode</div><div class='add'>+ *</div><div class='add'>+ * 4. Compute mode engine resumes are blocked behind any existing jobs from</div><div class='add'>+ * kernel ops and rebinds</div><div class='add'>+ *</div><div class='add'>+ * Future work</div><div class='add'>+ * ===========</div><div class='add'>+ *</div><div class='add'>+ * Support large pages for sysmem and userptr.</div><div class='add'>+ *</div><div class='add'>+ * Update page faults to handle BOs are page level grainularity (e.g. part of BO</div><div class='add'>+ * could be in system memory while another part could be in VRAM).</div><div class='add'>+ *</div><div class='add'>+ * Page fault handler likely we be optimized a bit more (e.g. Rebinds always</div><div class='add'>+ * wait on the dma-resv kernel slots of VM or BO, technically we only have to</div><div class='add'>+ * wait the BO moving. If using a job to do the rebind, we could not block in</div><div class='add'>+ * the page fault handler rather attach a callback to fence of the rebind job to</div><div class='add'>+ * signal page fault complete. Our handling of short circuting for atomic faults</div><div class='add'>+ * for bound VMAs could be better. etc...). We can tune all of this once we have</div><div class='add'>+ * benchmarks / performance number from workloads up and running.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h<br/>new file mode 100644<br/>index 000000000000..63e8a50b88e9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_vm_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_vm_types.h</a></div><div class='hunk'>@@ -0,0 +1,373 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_VM_TYPES_H_</div><div class='add'>+#define _XE_VM_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_gpuvm.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/dma-resv.h&gt;</div><div class='add'>+#include &lt;linux/kref.h&gt;</div><div class='add'>+#include &lt;linux/mmu_notifier.h&gt;</div><div class='add'>+#include &lt;linux/scatterlist.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_pt_types.h"</div><div class='add'>+#include "xe_range_fence.h"</div><div class='add'>+</div><div class='add'>+struct xe_bo;</div><div class='add'>+struct xe_sync_entry;</div><div class='add'>+struct xe_vm;</div><div class='add'>+</div><div class='add'>+#define TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+#define FORCE_ASYNC_OP_ERROR	BIT(31)</div><div class='add'>+</div><div class='add'>+#define XE_VMA_READ_ONLY	DRM_GPUVA_USERBITS</div><div class='add'>+#define XE_VMA_DESTROYED	(DRM_GPUVA_USERBITS &lt;&lt; 1)</div><div class='add'>+#define XE_VMA_ATOMIC_PTE_BIT	(DRM_GPUVA_USERBITS &lt;&lt; 2)</div><div class='add'>+#define XE_VMA_FIRST_REBIND	(DRM_GPUVA_USERBITS &lt;&lt; 3)</div><div class='add'>+#define XE_VMA_LAST_REBIND	(DRM_GPUVA_USERBITS &lt;&lt; 4)</div><div class='add'>+#define XE_VMA_PTE_4K		(DRM_GPUVA_USERBITS &lt;&lt; 5)</div><div class='add'>+#define XE_VMA_PTE_2M		(DRM_GPUVA_USERBITS &lt;&lt; 6)</div><div class='add'>+#define XE_VMA_PTE_1G		(DRM_GPUVA_USERBITS &lt;&lt; 7)</div><div class='add'>+</div><div class='add'>+/** struct xe_userptr - User pointer */</div><div class='add'>+struct xe_userptr {</div><div class='add'>+	/** @invalidate_link: Link for the vm::userptr.invalidated list */</div><div class='add'>+	struct list_head invalidate_link;</div><div class='add'>+	/**</div><div class='add'>+	 * @notifier: MMU notifier for user pointer (invalidation call back)</div><div class='add'>+	 */</div><div class='add'>+	struct mmu_interval_notifier notifier;</div><div class='add'>+	/** @sgt: storage for a scatter gather table */</div><div class='add'>+	struct sg_table sgt;</div><div class='add'>+	/** @sg: allocated scatter gather table */</div><div class='add'>+	struct sg_table *sg;</div><div class='add'>+	/** @notifier_seq: notifier sequence number */</div><div class='add'>+	unsigned long notifier_seq;</div><div class='add'>+	/**</div><div class='add'>+	 * @initial_bind: user pointer has been bound at least once.</div><div class='add'>+	 * write: vm-&gt;userptr.notifier_lock in read mode and vm-&gt;resv held.</div><div class='add'>+	 * read: vm-&gt;userptr.notifier_lock in write mode or vm-&gt;resv held.</div><div class='add'>+	 */</div><div class='add'>+	bool initial_bind;</div><div class='add'>+#if IS_ENABLED(CONFIG_DRM_XE_USERPTR_INVAL_INJECT)</div><div class='add'>+	u32 divisor;</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_vma {</div><div class='add'>+	/** @gpuva: Base GPUVA object */</div><div class='add'>+	struct drm_gpuva gpuva;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @combined_links: links into lists which are mutually exclusive.</div><div class='add'>+	 * Locking: vm lock in write mode OR vm lock in read mode and the vm's</div><div class='add'>+	 * resv.</div><div class='add'>+	 */</div><div class='add'>+	union {</div><div class='add'>+		/** @userptr: link into VM repin list if userptr. */</div><div class='add'>+		struct list_head userptr;</div><div class='add'>+		/** @rebind: link into VM if this VMA needs rebinding. */</div><div class='add'>+		struct list_head rebind;</div><div class='add'>+		/** @destroy: link to contested list when VM is being closed. */</div><div class='add'>+		struct list_head destroy;</div><div class='add'>+	} combined_links;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/** @destroy_cb: callback to destroy VMA when unbind job is done */</div><div class='add'>+		struct dma_fence_cb destroy_cb;</div><div class='add'>+		/** @destroy_work: worker to destroy this BO */</div><div class='add'>+		struct work_struct destroy_work;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/** @usm: unified shared memory state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @tile_invalidated: VMA has been invalidated */</div><div class='add'>+		u8 tile_invalidated;</div><div class='add'>+	} usm;</div><div class='add'>+</div><div class='add'>+	/** @tile_mask: Tile mask of where to create binding for this VMA */</div><div class='add'>+	u8 tile_mask;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @tile_present: GT mask of binding are present for this VMA.</div><div class='add'>+	 * protected by vm-&gt;lock, vm-&gt;resv and for userptrs,</div><div class='add'>+	 * vm-&gt;userptr.notifier_lock for writing. Needs either for reading,</div><div class='add'>+	 * but if reading is done under the vm-&gt;lock only, it needs to be held</div><div class='add'>+	 * in write mode.</div><div class='add'>+	 */</div><div class='add'>+	u8 tile_present;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @pat_index: The pat index to use when encoding the PTEs for this vma.</div><div class='add'>+	 */</div><div class='add'>+	u16 pat_index;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @userptr: user pointer state, only allocated for VMAs that are</div><div class='add'>+	 * user pointers</div><div class='add'>+	 */</div><div class='add'>+	struct xe_userptr userptr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+struct xe_vm {</div><div class='add'>+	/** @gpuvm: base GPUVM used to track VMAs */</div><div class='add'>+	struct drm_gpuvm gpuvm;</div><div class='add'>+</div><div class='add'>+	struct xe_device *xe;</div><div class='add'>+</div><div class='add'>+	/* exec queue used for (un)binding vma's */</div><div class='add'>+	struct xe_exec_queue *q[XE_MAX_TILES_PER_DEVICE];</div><div class='add'>+</div><div class='add'>+	/** @lru_bulk_move: Bulk LRU move list for this VM's BOs */</div><div class='add'>+	struct ttm_lru_bulk_move lru_bulk_move;</div><div class='add'>+</div><div class='add'>+	u64 size;</div><div class='add'>+</div><div class='add'>+	struct xe_pt *pt_root[XE_MAX_TILES_PER_DEVICE];</div><div class='add'>+	struct xe_pt *scratch_pt[XE_MAX_TILES_PER_DEVICE][XE_VM_MAX_LEVEL];</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @flags: flags for this VM, statically setup a creation time aside</div><div class='add'>+	 * from XE_VM_FLAG_BANNED which requires vm-&gt;lock to set / read safely</div><div class='add'>+	 */</div><div class='add'>+#define XE_VM_FLAG_64K			BIT(0)</div><div class='add'>+#define XE_VM_FLAG_LR_MODE		BIT(1)</div><div class='add'>+#define XE_VM_FLAG_MIGRATION		BIT(2)</div><div class='add'>+#define XE_VM_FLAG_SCRATCH_PAGE		BIT(3)</div><div class='add'>+#define XE_VM_FLAG_FAULT_MODE		BIT(4)</div><div class='add'>+#define XE_VM_FLAG_BANNED		BIT(5)</div><div class='add'>+#define XE_VM_FLAG_TILE_ID(flags)	FIELD_GET(GENMASK(7, 6), flags)</div><div class='add'>+#define XE_VM_FLAG_SET_TILE_ID(tile)	FIELD_PREP(GENMASK(7, 6), (tile)-&gt;id)</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	/** @composite_fence_ctx: context composite fence */</div><div class='add'>+	u64 composite_fence_ctx;</div><div class='add'>+	/** @composite_fence_seqno: seqno for composite fence */</div><div class='add'>+	u32 composite_fence_seqno;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @lock: outer most lock, protects objects of anything attached to this</div><div class='add'>+	 * VM</div><div class='add'>+	 */</div><div class='add'>+	struct rw_semaphore lock;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @rebind_list: list of VMAs that need rebinding. Protected by the</div><div class='add'>+	 * vm-&gt;lock in write mode, OR (the vm-&gt;lock in read mode and the</div><div class='add'>+	 * vm resv).</div><div class='add'>+	 */</div><div class='add'>+	struct list_head rebind_list;</div><div class='add'>+</div><div class='add'>+	/** @rebind_fence: rebind fence from execbuf */</div><div class='add'>+	struct dma_fence *rebind_fence;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @destroy_work: worker to destroy VM, needed as a dma_fence signaling</div><div class='add'>+	 * from an irq context can be last put and the destroy needs to be able</div><div class='add'>+	 * to sleep.</div><div class='add'>+	 */</div><div class='add'>+	struct work_struct destroy_work;</div><div class='add'>+</div><div class='add'>+	/**</div><div class='add'>+	 * @rftree: range fence tree to track updates to page table structure.</div><div class='add'>+	 * Used to implement conflict tracking between independent bind engines.</div><div class='add'>+	 */</div><div class='add'>+	struct xe_range_fence_tree rftree[XE_MAX_TILES_PER_DEVICE];</div><div class='add'>+</div><div class='add'>+	/** @async_ops: async VM operations (bind / unbinds) */</div><div class='add'>+	struct {</div><div class='add'>+		/** @list: list of pending async VM ops */</div><div class='add'>+		struct list_head pending;</div><div class='add'>+		/** @work: worker to execute async VM ops */</div><div class='add'>+		struct work_struct work;</div><div class='add'>+		/** @lock: protects list of pending async VM ops and fences */</div><div class='add'>+		spinlock_t lock;</div><div class='add'>+		/** @fence: fence state */</div><div class='add'>+		struct {</div><div class='add'>+			/** @context: context of async fence */</div><div class='add'>+			u64 context;</div><div class='add'>+			/** @seqno: seqno of async fence */</div><div class='add'>+			u32 seqno;</div><div class='add'>+		} fence;</div><div class='add'>+		/** @error: error state for async VM ops */</div><div class='add'>+		int error;</div><div class='add'>+		/**</div><div class='add'>+		 * @munmap_rebind_inflight: an munmap style VM bind is in the</div><div class='add'>+		 * middle of a set of ops which requires a rebind at the end.</div><div class='add'>+		 */</div><div class='add'>+		bool munmap_rebind_inflight;</div><div class='add'>+	} async_ops;</div><div class='add'>+</div><div class='add'>+	const struct xe_pt_ops *pt_ops;</div><div class='add'>+</div><div class='add'>+	/** @userptr: user pointer state */</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @userptr.repin_list: list of VMAs which are user pointers,</div><div class='add'>+		 * and needs repinning. Protected by @lock.</div><div class='add'>+		 */</div><div class='add'>+		struct list_head repin_list;</div><div class='add'>+		/**</div><div class='add'>+		 * @notifier_lock: protects notifier in write mode and</div><div class='add'>+		 * submission in read mode.</div><div class='add'>+		 */</div><div class='add'>+		struct rw_semaphore notifier_lock;</div><div class='add'>+		/**</div><div class='add'>+		 * @userptr.invalidated_lock: Protects the</div><div class='add'>+		 * @userptr.invalidated list.</div><div class='add'>+		 */</div><div class='add'>+		spinlock_t invalidated_lock;</div><div class='add'>+		/**</div><div class='add'>+		 * @userptr.invalidated: List of invalidated userptrs, not yet</div><div class='add'>+		 * picked</div><div class='add'>+		 * up for revalidation. Protected from access with the</div><div class='add'>+		 * @invalidated_lock. Removing items from the list</div><div class='add'>+		 * additionally requires @lock in write mode, and adding</div><div class='add'>+		 * items to the list requires the @userptr.notifer_lock in</div><div class='add'>+		 * write mode.</div><div class='add'>+		 */</div><div class='add'>+		struct list_head invalidated;</div><div class='add'>+	} userptr;</div><div class='add'>+</div><div class='add'>+	/** @preempt: preempt state */</div><div class='add'>+	struct {</div><div class='add'>+		/**</div><div class='add'>+		 * @min_run_period_ms: The minimum run period before preempting</div><div class='add'>+		 * an engine again</div><div class='add'>+		 */</div><div class='add'>+		s64 min_run_period_ms;</div><div class='add'>+		/** @exec_queues: list of exec queues attached to this VM */</div><div class='add'>+		struct list_head exec_queues;</div><div class='add'>+		/** @num_exec_queues: number exec queues attached to this VM */</div><div class='add'>+		int num_exec_queues;</div><div class='add'>+		/**</div><div class='add'>+		 * @rebind_deactivated: Whether rebind has been temporarily deactivated</div><div class='add'>+		 * due to no work available. Protected by the vm resv.</div><div class='add'>+		 */</div><div class='add'>+		bool rebind_deactivated;</div><div class='add'>+		/**</div><div class='add'>+		 * @rebind_work: worker to rebind invalidated userptrs / evicted</div><div class='add'>+		 * BOs</div><div class='add'>+		 */</div><div class='add'>+		struct work_struct rebind_work;</div><div class='add'>+	} preempt;</div><div class='add'>+</div><div class='add'>+	/** @um: unified memory state */</div><div class='add'>+	struct {</div><div class='add'>+		/** @asid: address space ID, unique to each VM */</div><div class='add'>+		u32 asid;</div><div class='add'>+		/**</div><div class='add'>+		 * @last_fault_vma: Last fault VMA, used for fast lookup when we</div><div class='add'>+		 * get a flood of faults to the same VMA</div><div class='add'>+		 */</div><div class='add'>+		struct xe_vma *last_fault_vma;</div><div class='add'>+	} usm;</div><div class='add'>+</div><div class='add'>+	/** @error_capture: allow to track errors */</div><div class='add'>+	struct {</div><div class='add'>+		/** @capture_once: capture only one error per VM */</div><div class='add'>+		bool capture_once;</div><div class='add'>+	} error_capture;</div><div class='add'>+</div><div class='add'>+	/** @batch_invalidate_tlb: Always invalidate TLB before batch start */</div><div class='add'>+	bool batch_invalidate_tlb;</div><div class='add'>+	/** @xef: XE file handle for tracking this VM's drm client */</div><div class='add'>+	struct xe_file *xef;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_vma_op_map - VMA map operation */</div><div class='add'>+struct xe_vma_op_map {</div><div class='add'>+	/** @vma: VMA to map */</div><div class='add'>+	struct xe_vma *vma;</div><div class='add'>+	/** @immediate: Immediate bind */</div><div class='add'>+	bool immediate;</div><div class='add'>+	/** @read_only: Read only */</div><div class='add'>+	bool read_only;</div><div class='add'>+	/** @is_null: is NULL binding */</div><div class='add'>+	bool is_null;</div><div class='add'>+	/** @pat_index: The pat index to use for this operation. */</div><div class='add'>+	u16 pat_index;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_vma_op_remap - VMA remap operation */</div><div class='add'>+struct xe_vma_op_remap {</div><div class='add'>+	/** @prev: VMA preceding part of a split mapping */</div><div class='add'>+	struct xe_vma *prev;</div><div class='add'>+	/** @next: VMA subsequent part of a split mapping */</div><div class='add'>+	struct xe_vma *next;</div><div class='add'>+	/** @start: start of the VMA unmap */</div><div class='add'>+	u64 start;</div><div class='add'>+	/** @range: range of the VMA unmap */</div><div class='add'>+	u64 range;</div><div class='add'>+	/** @skip_prev: skip prev rebind */</div><div class='add'>+	bool skip_prev;</div><div class='add'>+	/** @skip_next: skip next rebind */</div><div class='add'>+	bool skip_next;</div><div class='add'>+	/** @unmap_done: unmap operation in done */</div><div class='add'>+	bool unmap_done;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_vma_op_prefetch - VMA prefetch operation */</div><div class='add'>+struct xe_vma_op_prefetch {</div><div class='add'>+	/** @region: memory region to prefetch to */</div><div class='add'>+	u32 region;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** enum xe_vma_op_flags - flags for VMA operation */</div><div class='add'>+enum xe_vma_op_flags {</div><div class='add'>+	/** @XE_VMA_OP_FIRST: first VMA operation for a set of syncs */</div><div class='add'>+	XE_VMA_OP_FIRST			= BIT(0),</div><div class='add'>+	/** @XE_VMA_OP_LAST: last VMA operation for a set of syncs */</div><div class='add'>+	XE_VMA_OP_LAST			= BIT(1),</div><div class='add'>+	/** @XE_VMA_OP_COMMITTED: VMA operation committed */</div><div class='add'>+	XE_VMA_OP_COMMITTED		= BIT(2),</div><div class='add'>+	/** @XE_VMA_OP_PREV_COMMITTED: Previous VMA operation committed */</div><div class='add'>+	XE_VMA_OP_PREV_COMMITTED	= BIT(3),</div><div class='add'>+	/** @XE_VMA_OP_NEXT_COMMITTED: Next VMA operation committed */</div><div class='add'>+	XE_VMA_OP_NEXT_COMMITTED	= BIT(4),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/** struct xe_vma_op - VMA operation */</div><div class='add'>+struct xe_vma_op {</div><div class='add'>+	/** @base: GPUVA base operation */</div><div class='add'>+	struct drm_gpuva_op base;</div><div class='add'>+	/**</div><div class='add'>+	 * @ops: GPUVA ops, when set call drm_gpuva_ops_free after this</div><div class='add'>+	 * operations is processed</div><div class='add'>+	 */</div><div class='add'>+	struct drm_gpuva_ops *ops;</div><div class='add'>+	/** @q: exec queue for this operation */</div><div class='add'>+	struct xe_exec_queue *q;</div><div class='add'>+	/**</div><div class='add'>+	 * @syncs: syncs for this operation, only used on first and last</div><div class='add'>+	 * operation</div><div class='add'>+	 */</div><div class='add'>+	struct xe_sync_entry *syncs;</div><div class='add'>+	/** @num_syncs: number of syncs */</div><div class='add'>+	u32 num_syncs;</div><div class='add'>+	/** @link: async operation link */</div><div class='add'>+	struct list_head link;</div><div class='add'>+	/** @flags: operation flags */</div><div class='add'>+	enum xe_vma_op_flags flags;</div><div class='add'>+</div><div class='add'>+#ifdef TEST_VM_ASYNC_OPS_ERROR</div><div class='add'>+	/** @inject_error: inject error to test async op error handling */</div><div class='add'>+	bool inject_error;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/** @map: VMA map operation specific data */</div><div class='add'>+		struct xe_vma_op_map map;</div><div class='add'>+		/** @remap: VMA remap operation specific data */</div><div class='add'>+		struct xe_vma_op_remap remap;</div><div class='add'>+		/** @prefetch: VMA prefetch operation specific data */</div><div class='add'>+		struct xe_vma_op_prefetch prefetch;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c<br/>new file mode 100644<br/>index 000000000000..5f61dd87c586<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa.c</a></div><div class='hunk'>@@ -0,0 +1,895 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_wa.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_managed.h&gt;</div><div class='add'>+#include &lt;kunit/visibility.h&gt;</div><div class='add'>+#include &lt;linux/compiler_types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "generated/xe_wa_oob.h"</div><div class='add'>+#include "regs/xe_engine_regs.h"</div><div class='add'>+#include "regs/xe_gt_regs.h"</div><div class='add'>+#include "regs/xe_regs.h"</div><div class='add'>+#include "xe_device_types.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_hw_engine_types.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_platform_types.h"</div><div class='add'>+#include "xe_rtp.h"</div><div class='add'>+#include "xe_step.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Hardware workarounds</div><div class='add'>+ *</div><div class='add'>+ * Hardware workarounds are register programming documented to be executed in</div><div class='add'>+ * the driver that fall outside of the normal programming sequences for a</div><div class='add'>+ * platform. There are some basic categories of workarounds, depending on</div><div class='add'>+ * how/when they are applied:</div><div class='add'>+ *</div><div class='add'>+ * - LRC workarounds: workarounds that touch registers that are</div><div class='add'>+ *   saved/restored to/from the HW context image. The list is emitted (via Load</div><div class='add'>+ *   Register Immediate commands) once when initializing the device and saved in</div><div class='add'>+ *   the default context. That default context is then used on every context</div><div class='add'>+ *   creation to have a "primed golden context", i.e. a context image that</div><div class='add'>+ *   already contains the changes needed to all the registers.</div><div class='add'>+ *</div><div class='add'>+ * - Engine workarounds: the list of these WAs is applied whenever the specific</div><div class='add'>+ *   engine is reset. It's also possible that a set of engine classes share a</div><div class='add'>+ *   common power domain and they are reset together. This happens on some</div><div class='add'>+ *   platforms with render and compute engines. In this case (at least) one of</div><div class='add'>+ *   them need to keeep the workaround programming: the approach taken in the</div><div class='add'>+ *   driver is to tie those workarounds to the first compute/render engine that</div><div class='add'>+ *   is registered.  When executing with GuC submission, engine resets are</div><div class='add'>+ *   outside of kernel driver control, hence the list of registers involved in</div><div class='add'>+ *   written once, on engine initialization, and then passed to GuC, that</div><div class='add'>+ *   saves/restores their values before/after the reset takes place. See</div><div class='add'>+ *   ``drivers/gpu/drm/xe/xe_guc_ads.c`` for reference.</div><div class='add'>+ *</div><div class='add'>+ * - GT workarounds: the list of these WAs is applied whenever these registers</div><div class='add'>+ *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.</div><div class='add'>+ *</div><div class='add'>+ * - Register whitelist: some workarounds need to be implemented in userspace,</div><div class='add'>+ *   but need to touch privileged registers. The whitelist in the kernel</div><div class='add'>+ *   instructs the hardware to allow the access to happen. From the kernel side,</div><div class='add'>+ *   this is just a special case of a MMIO workaround (as we write the list of</div><div class='add'>+ *   these to/be-whitelisted registers to some special HW registers).</div><div class='add'>+ *</div><div class='add'>+ * - Workaround batchbuffers: buffers that get executed automatically by the</div><div class='add'>+ *   hardware on every HW context restore. These buffers are created and</div><div class='add'>+ *   programmed in the default context so the hardware always go through those</div><div class='add'>+ *   programming sequences when switching contexts. The support for workaround</div><div class='add'>+ *   batchbuffers is enabled these hardware mechanisms:</div><div class='add'>+ *</div><div class='add'>+ *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default</div><div class='add'>+ *      context, pointing the hardware to jump to that location when that offset</div><div class='add'>+ *      is reached in the context restore. Workaround batchbuffer in the driver</div><div class='add'>+ *      currently uses this mechanism for all platforms.</div><div class='add'>+ *</div><div class='add'>+ *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,</div><div class='add'>+ *      pointing the hardware to a buffer to continue executing after the</div><div class='add'>+ *      engine registers are restored in a context restore sequence. This is</div><div class='add'>+ *      currently not used in the driver.</div><div class='add'>+ *</div><div class='add'>+ * - Other/OOB:  There are WAs that, due to their nature, cannot be applied from</div><div class='add'>+ *   a central place. Those are peppered around the rest of the code, as needed.</div><div class='add'>+ *   Workarounds related to the display IP are the main example.</div><div class='add'>+ *</div><div class='add'>+ * .. [1] Technically, some registers are powercontext saved &amp; restored, so they</div><div class='add'>+ *    survive a suspend/resume. In practice, writing them again is not too</div><div class='add'>+ *    costly and simplifies things, so it's the approach taken in the driver.</div><div class='add'>+ *</div><div class='add'>+ * .. note::</div><div class='add'>+ *    Hardware workarounds in xe work the same way as in i915, with the</div><div class='add'>+ *    difference of how they are maintained in the code. In xe it uses the</div><div class='add'>+ *    xe_rtp infrastructure so the workarounds can be kept in tables, following</div><div class='add'>+ *    a more declarative approach rather than procedural.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#undef XE_REG_MCR</div><div class='add'>+#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)</div><div class='add'>+</div><div class='add'>+__diag_push();</div><div class='add'>+__diag_ignore_all("-Woverride-init", "Allow field overrides in table");</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr gt_was[] = {</div><div class='add'>+	{ XE_RTP_NAME("14011060649"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),</div><div class='add'>+		       ENGINE_CLASS(VIDEO_DECODE),</div><div class='add'>+		       FUNC(xe_rtp_match_even_instance)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011059788"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14015795083"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG1 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("1409420604"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG1)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1408615072"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG1)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE2_DIS))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG2 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16010515920"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10),</div><div class='add'>+		       GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(VIDEO_DECODE)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F18(0), ALNUNIT_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22010523718"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, CG3DDISCFEG_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011006942"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE, DSS_ROUTER_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14012362059"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14012362059"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010948348"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011037102"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLCGCTL9444, LTCDD_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011371254"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011431319"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLCGCTL9440,</div><div class='add'>+			     GAMTLBOACS_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVDBOX7_CLKGATE_DIS | GAMTLBVDBOX6_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVDBOX5_CLKGATE_DIS | GAMTLBVDBOX4_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVDBOX3_CLKGATE_DIS | GAMTLBVDBOX2_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVDBOX1_CLKGATE_DIS | GAMTLBVDBOX0_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBKCR_CLKGATE_DIS | GAMTLBGUC_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBBLT_CLKGATE_DIS),</div><div class='add'>+			 SET(UNSLCGCTL9444,</div><div class='add'>+			     GAMTLBGFXA0_CLKGATE_DIS | GAMTLBGFXA1_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBCOMPA0_CLKGATE_DIS | GAMTLBCOMPA1_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBCOMPB0_CLKGATE_DIS | GAMTLBCOMPB1_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBCOMPC0_CLKGATE_DIS | GAMTLBCOMPC1_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBCOMPD0_CLKGATE_DIS | GAMTLBCOMPD1_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBMERT_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVEBOX3_CLKGATE_DIS | GAMTLBVEBOX2_CLKGATE_DIS |</div><div class='add'>+			     GAMTLBVEBOX1_CLKGATE_DIS | GAMTLBVEBOX0_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010569222"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE, GAMEDIA_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14011028019"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SSMCGCTL9530, RTFUNIT_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010680813"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_GAMSTLB_CTRL,</div><div class='add'>+			     CONTROL_BLOCK_CLKGATE_DIS |</div><div class='add'>+			     EGRESS_BLOCK_CLKGATE_DIS |</div><div class='add'>+			     TAG_BLOCK_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14014830051"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(SARB_CHICKEN1, COMP_CKN_IN))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("18018781329"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1509235366"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_GAMCNTRL_CTRL,</div><div class='add'>+			     INVALIDATION_BROADCAST_MODE_DIS |</div><div class='add'>+			     GLOBAL_INVALIDATION_MODE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010648519"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_L3NODEARBCFG, XEHP_LNESPARE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* PVC */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("18018781329"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),</div><div class='add'>+			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16016694945"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("14015795083"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14018575942"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22016670082"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe_LPM+ */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16021867713"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(1300),</div><div class='add'>+		       ENGINE_CLASS(VIDEO_DECODE)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22016670082"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(1300)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe2_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16020975621"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14018157293"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),</div><div class='add'>+			 SET(XEHPC_L3CLOS_MASK(1), ~0),</div><div class='add'>+			 SET(XEHPC_L3CLOS_MASK(2), ~0),</div><div class='add'>+			 SET(XEHPC_L3CLOS_MASK(3), ~0))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe2_LPM */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("14017421178"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(2000),</div><div class='add'>+		       ENGINE_CLASS(VIDEO_DECODE)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16021867713"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(2000),</div><div class='add'>+		       ENGINE_CLASS(VIDEO_DECODE)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019449301"),</div><div class='add'>+	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),</div><div class='add'>+	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr engine_was[] = {</div><div class='add'>+	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),</div><div class='add'>+			     FF_TESSELATION_DOP_GATE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1409804808"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(1200),</div><div class='add'>+		       ENGINE_CLASS(RENDER),</div><div class='add'>+		       IS_INTEGRATED),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, PUSH_CONST_DEREF_HOLD_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010229206, 1409085225"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(1200),</div><div class='add'>+		       ENGINE_CLASS(RENDER),</div><div class='add'>+		       IS_INTEGRATED),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1606931601"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_EARLY_READ))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010826681, 1606700617, 22010271021, 18019627453"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1255), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),</div><div class='add'>+			     FF_DOP_CLOCK_GATE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1406941453"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, ENABLE_SMALLPL))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),</div><div class='add'>+			     FFSC_PERCTX_PREEMPT_CTRL))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* TGL */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),</div><div class='add'>+			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |</div><div class='add'>+			     RC_SEMA_IDLE_MSG_DISABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* RKL */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),</div><div class='add'>+			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |</div><div class='add'>+			     RC_SEMA_IDLE_MSG_DISABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* ADL-P */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("1607297627, 1607030317, 1607186500"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(ALDERLAKE_P), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),</div><div class='add'>+			     WAIT_FOR_EVENT_POWER_DOWN_DISABLE |</div><div class='add'>+			     RC_SEMA_IDLE_MSG_DISABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG2 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("22013037850"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,</div><div class='add'>+			     DISABLE_128B_EVICTION_COMMAND_UDW))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22014226127"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("18017747507"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VFG_PREEMPTION_CHICKEN,</div><div class='add'>+			     POLYGON_TRIFAN_LINELOOP_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012826095, 22013059131"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,</div><div class='add'>+				   MAXREQS_PER_BANK,</div><div class='add'>+				   REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012826095, 22013059131"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(LSC_CHICKEN_BIT_0_UDW,</div><div class='add'>+				   MAXREQS_PER_BANK,</div><div class='add'>+				   REG_FIELD_PREP(MAXREQS_PER_BANK, 2)))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22013059131"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22013059131"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010918519"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,</div><div class='add'>+			     FORCE_SLM_FENCE_SCOPE_TO_TILE |</div><div class='add'>+			     FORCE_UGM_FENCE_SCOPE_TO_TILE,</div><div class='add'>+			     /*</div><div class='add'>+			      * Ignore read back as it always returns 0 in these</div><div class='add'>+			      * steps</div><div class='add'>+			      */</div><div class='add'>+			     .read_mask = 0))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14015227452"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16015675438"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),</div><div class='add'>+			     PERF_FIX_BALANCING_CFE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("18028616096"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16011620976, 22015475538"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012654132"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,</div><div class='add'>+			     /*</div><div class='add'>+			      * Register can't be read back for verification on</div><div class='add'>+			      * DG2 due to Wa_14012342262</div><div class='add'>+			      */</div><div class='add'>+			     .read_mask = 0))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012654132"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, ENABLE_PREFETCH_INTO_IC,</div><div class='add'>+			     /*</div><div class='add'>+			      * Register can't be read back for verification on</div><div class='add'>+			      * DG2 due to Wa_14012342262</div><div class='add'>+			      */</div><div class='add'>+			     .read_mask = 0))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1509727124"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012856258"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, DISABLE_READ_SUPPRESSION))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14013392000"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN2, ENABLE_LARGE_GRF_MODE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14012419201"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4,</div><div class='add'>+			     DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14012419201"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4,</div><div class='add'>+			     DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1308578152"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),</div><div class='add'>+		       ENGINE_CLASS(RENDER),</div><div class='add'>+		       FUNC(xe_rtp_match_first_gslice_fused_off)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(CS_DEBUG_MODE1(RENDER_RING_BASE),</div><div class='add'>+			     REPLAY_MODE_GRANULARITY))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22010960976, 14013347512"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(XEHP_HDC_CHICKEN0,</div><div class='add'>+			     LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1608949956, 14010198302"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN,</div><div class='add'>+			     MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22010430635"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4,</div><div class='add'>+			     DISABLE_GRF_CLEAR))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14013202645"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(B0, C0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14013202645"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012532006"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,</div><div class='add'>+			     DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22012532006"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7,</div><div class='add'>+			     DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14015150844"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,</div><div class='add'>+			     XE_RTP_NOCHECK))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* PVC */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("22014226127"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14015227452"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16015675438"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN2(RENDER_RING_BASE),</div><div class='add'>+			     PERF_FIX_BALANCING_CFE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14014999345"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COMPUTE),</div><div class='add'>+		       GRAPHICS_STEP(B0, C0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("14017856879"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_FIX_EOT1_FLUSH))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14015150844"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES,</div><div class='add'>+			     XE_RTP_NOCHECK))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe2_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("18032247524"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16018712365"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14018957109"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16021540221"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019322943"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14018471104"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16018737384"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS))</div><div class='add'>+	},</div><div class='add'>+	/*</div><div class='add'>+	 * These two workarounds are the same, just applying to different</div><div class='add'>+	 * engines.  Although Wa_18032095049 (for the RCS) isn't required on</div><div class='add'>+	 * all steppings, disabling these reports has no impact for our</div><div class='add'>+	 * driver or the GuC, so we go ahead and treat it the same as</div><div class='add'>+	 * Wa_16021639441 which does apply to all steppings.</div><div class='add'>+	 */</div><div class='add'>+	{ XE_RTP_NAME("18032095049, 16021639441"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),</div><div class='add'>+			     GHWSP_CSB_REPORT_DIS |</div><div class='add'>+			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,</div><div class='add'>+			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct xe_rtp_entry_sr lrc_was[] = {</div><div class='add'>+	{ XE_RTP_NAME("1409342910, 14010698770, 14010443199, 1408979724, 1409178076, 1409207793, 1409217633, 1409252684, 1409347922, 1409142259"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN3,</div><div class='add'>+			     DISABLE_CPS_AWARE_COLOR_PIPE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("WaDisableGPGPUMidThreadPreemption"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),</div><div class='add'>+				   PREEMPT_GPGPU_LEVEL_MASK,</div><div class='add'>+				   PREEMPT_GPGPU_THREAD_GROUP_LEVEL))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1806527549"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("1606376872"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG1 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("1409044764"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG1)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(COMMON_SLICE_CHICKEN3,</div><div class='add'>+			     DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("22010493298"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG1)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(HIZ_CHICKEN,</div><div class='add'>+			     DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* DG2 */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16011186671"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(CLR(VFLSKPD, DIS_MULT_MISS_RD_SQUASH),</div><div class='add'>+			 SET(VFLSKPD, DIS_OVER_FETCH_CACHE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010469329"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,</div><div class='add'>+			     XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14010698770, 22010613112, 22010465075"),</div><div class='add'>+	  XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_COMMON_SLICE_CHICKEN3,</div><div class='add'>+			     DISABLE_CPS_AWARE_COLOR_PIPE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("16013271637"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_SLICE_COMMON_ECO_CHICKEN1,</div><div class='add'>+			     MSC_MSAA_REODER_BUF_BYPASS_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14014947963"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(FIELD_SET(VF_PREEMPTION,</div><div class='add'>+				   PREEMPTION_VERTEX_COUNT,</div><div class='add'>+				   0x4000))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("18018764978"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_PSS_MODE2,</div><div class='add'>+			     SCOREBOARD_STALL_FLUSH_CONTROL))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("18019271663"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019877138"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(DG2)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* PVC */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16017236439"),</div><div class='add'>+	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),</div><div class='add'>+		       FUNC(xe_rtp_match_even_instance)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),</div><div class='add'>+			     BCS_SWCTRL_DISABLE_256B,</div><div class='add'>+			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("18019271663"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	/* Xe2_LPG */</div><div class='add'>+</div><div class='add'>+	{ XE_RTP_NAME("16020518922"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(FF_MODE,</div><div class='add'>+			     DIS_TE_AUTOSTRIP |</div><div class='add'>+			     DIS_MESH_PARTIAL_AUTOSTRIP |</div><div class='add'>+			     DIS_MESH_AUTOSTRIP),</div><div class='add'>+			 SET(VFLSKPD,</div><div class='add'>+			     DIS_PARTIAL_AUTOSTRIP |</div><div class='add'>+			     DIS_AUTOSTRIP))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019386621"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019877138"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14020013138"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),</div><div class='add'>+		       ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))</div><div class='add'>+	},</div><div class='add'>+	{ XE_RTP_NAME("14019988906"),</div><div class='add'>+	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),</div><div class='add'>+	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static __maybe_unused const struct xe_rtp_entry oob_was[] = {</div><div class='add'>+#include &lt;generated/xe_wa_oob.c&gt;</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);</div><div class='add'>+</div><div class='add'>+__diag_pop();</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wa_process_oob - process OOB workaround table</div><div class='add'>+ * @gt: GT instance to process workarounds for</div><div class='add'>+ *</div><div class='add'>+ * Process OOB workaround table for this platform, marking in @gt the</div><div class='add'>+ * workarounds that are active.</div><div class='add'>+ */</div><div class='add'>+void xe_wa_process_oob(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_ctx_enable_active_tracking(&amp;ctx, gt-&gt;wa_active.oob,</div><div class='add'>+						  ARRAY_SIZE(oob_was));</div><div class='add'>+	xe_rtp_process(&amp;ctx, oob_was);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wa_process_gt - process GT workaround table</div><div class='add'>+ * @gt: GT instance to process workarounds for</div><div class='add'>+ *</div><div class='add'>+ * Process GT workaround table for this platform, saving in @gt all the</div><div class='add'>+ * workarounds that need to be applied at the GT level.</div><div class='add'>+ */</div><div class='add'>+void xe_wa_process_gt(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(gt);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_ctx_enable_active_tracking(&amp;ctx, gt-&gt;wa_active.gt,</div><div class='add'>+						  ARRAY_SIZE(gt_was));</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, gt_was, &amp;gt-&gt;reg_sr);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_IF_KUNIT(xe_wa_process_gt);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wa_process_engine - process engine workaround table</div><div class='add'>+ * @hwe: engine instance to process workarounds for</div><div class='add'>+ *</div><div class='add'>+ * Process engine workaround table for this platform, saving in @hwe all the</div><div class='add'>+ * workarounds that need to be applied at the engine level that match this</div><div class='add'>+ * engine.</div><div class='add'>+ */</div><div class='add'>+void xe_wa_process_engine(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_ctx_enable_active_tracking(&amp;ctx, hwe-&gt;gt-&gt;wa_active.engine,</div><div class='add'>+						  ARRAY_SIZE(engine_was));</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, engine_was, &amp;hwe-&gt;reg_sr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wa_process_lrc - process context workaround table</div><div class='add'>+ * @hwe: engine instance to process workarounds for</div><div class='add'>+ *</div><div class='add'>+ * Process context workaround table for this platform, saving in @hwe all the</div><div class='add'>+ * workarounds that need to be applied on context restore. These are workarounds</div><div class='add'>+ * touching registers that are part of the HW context image.</div><div class='add'>+ */</div><div class='add'>+void xe_wa_process_lrc(struct xe_hw_engine *hwe)</div><div class='add'>+{</div><div class='add'>+	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);</div><div class='add'>+</div><div class='add'>+	xe_rtp_process_ctx_enable_active_tracking(&amp;ctx, hwe-&gt;gt-&gt;wa_active.lrc,</div><div class='add'>+						  ARRAY_SIZE(lrc_was));</div><div class='add'>+	xe_rtp_process_to_sr(&amp;ctx, lrc_was, &amp;hwe-&gt;reg_lrc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wa_init - initialize gt with workaround bookkeeping</div><div class='add'>+ * @gt: GT instance to initialize</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 for success, negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int xe_wa_init(struct xe_gt *gt)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = gt_to_xe(gt);</div><div class='add'>+	size_t n_oob, n_lrc, n_engine, n_gt, total;</div><div class='add'>+	unsigned long *p;</div><div class='add'>+</div><div class='add'>+	n_gt = BITS_TO_LONGS(ARRAY_SIZE(gt_was));</div><div class='add'>+	n_engine = BITS_TO_LONGS(ARRAY_SIZE(engine_was));</div><div class='add'>+	n_lrc = BITS_TO_LONGS(ARRAY_SIZE(lrc_was));</div><div class='add'>+	n_oob = BITS_TO_LONGS(ARRAY_SIZE(oob_was));</div><div class='add'>+	total = n_gt + n_engine + n_lrc + n_oob;</div><div class='add'>+</div><div class='add'>+	p = drmm_kzalloc(&amp;xe-&gt;drm, sizeof(*p) * total, GFP_KERNEL);</div><div class='add'>+	if (!p)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	gt-&gt;wa_active.gt = p;</div><div class='add'>+	p += n_gt;</div><div class='add'>+	gt-&gt;wa_active.engine = p;</div><div class='add'>+	p += n_engine;</div><div class='add'>+	gt-&gt;wa_active.lrc = p;</div><div class='add'>+	p += n_lrc;</div><div class='add'>+	gt-&gt;wa_active.oob = p;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)</div><div class='add'>+{</div><div class='add'>+	size_t idx;</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "GT Workarounds\n");</div><div class='add'>+	for_each_set_bit(idx, gt-&gt;wa_active.gt, ARRAY_SIZE(gt_was))</div><div class='add'>+		drm_printf_indent(p, 1, "%s\n", gt_was[idx].name);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nEngine Workarounds\n");</div><div class='add'>+	for_each_set_bit(idx, gt-&gt;wa_active.engine, ARRAY_SIZE(engine_was))</div><div class='add'>+		drm_printf_indent(p, 1, "%s\n", engine_was[idx].name);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nLRC Workarounds\n");</div><div class='add'>+	for_each_set_bit(idx, gt-&gt;wa_active.lrc, ARRAY_SIZE(lrc_was))</div><div class='add'>+		drm_printf_indent(p, 1, "%s\n", lrc_was[idx].name);</div><div class='add'>+</div><div class='add'>+	drm_printf(p, "\nOOB Workarounds\n");</div><div class='add'>+	for_each_set_bit(idx, gt-&gt;wa_active.oob, ARRAY_SIZE(oob_was))</div><div class='add'>+		if (oob_was[idx].name)</div><div class='add'>+			drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Apply tile (non-GT, non-display) workarounds.  Think very carefully before</div><div class='add'>+ * adding anything to this function; most workarounds should be implemented</div><div class='add'>+ * elsewhere.  The programming here is primarily for sgunit/soc workarounds,</div><div class='add'>+ * which are relatively rare.  Since the registers these workarounds target are</div><div class='add'>+ * outside the GT, they should only need to be applied once at device</div><div class='add'>+ * probe/resume; they will not lose their values on any kind of GT or engine</div><div class='add'>+ * reset.</div><div class='add'>+ *</div><div class='add'>+ * TODO:  We may want to move this over to xe_rtp in the future once we have</div><div class='add'>+ * enough workarounds to justify the work.</div><div class='add'>+ */</div><div class='add'>+void xe_wa_apply_tile_workarounds(struct xe_tile *tile)</div><div class='add'>+{</div><div class='add'>+	struct xe_gt *mmio = tile-&gt;primary_gt;</div><div class='add'>+</div><div class='add'>+	if (XE_WA(mmio, 22010954014))</div><div class='add'>+		xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h<br/>new file mode 100644<br/>index 000000000000..1b24d66f9d80<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa.h</a></div><div class='hunk'>@@ -0,0 +1,32 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_WA_</div><div class='add'>+#define _XE_WA_</div><div class='add'>+</div><div class='add'>+struct drm_printer;</div><div class='add'>+struct xe_gt;</div><div class='add'>+struct xe_hw_engine;</div><div class='add'>+struct xe_tile;</div><div class='add'>+</div><div class='add'>+int xe_wa_init(struct xe_gt *gt);</div><div class='add'>+void xe_wa_process_oob(struct xe_gt *gt);</div><div class='add'>+void xe_wa_process_gt(struct xe_gt *gt);</div><div class='add'>+void xe_wa_process_engine(struct xe_hw_engine *hwe);</div><div class='add'>+void xe_wa_process_lrc(struct xe_hw_engine *hwe);</div><div class='add'>+void xe_wa_apply_tile_workarounds(struct xe_tile *tile);</div><div class='add'>+</div><div class='add'>+void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);</div><div class='add'>+void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * XE_WA - Out-of-band workarounds, that don't fit the lifecycle any</div><div class='add'>+ *         other more specific type</div><div class='add'>+ * @gt__: gt instance</div><div class='add'>+ * @id__: XE_OOB_&lt;id__&gt;, as generated by build system in generated/xe_wa_oob.h</div><div class='add'>+ */</div><div class='add'>+#define XE_WA(gt__, id__) test_bit(XE_WA_OOB_ ## id__, (gt__)-&gt;wa_active.oob)</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules<br/>new file mode 100644<br/>index 000000000000..727bdc429212<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wa_oob.rules?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wa_oob.rules</a></div><div class='hunk'>@@ -0,0 +1,24 @@</div><div class='add'>+22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)</div><div class='add'>+16011759253	SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)</div><div class='add'>+14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)</div><div class='add'>+		PLATFORM(DG2)</div><div class='add'>+22011391025	PLATFORM(DG2)</div><div class='add'>+14012197797	PLATFORM(DG2), GRAPHICS_STEP(A0, B0)</div><div class='add'>+16011777198	SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)</div><div class='add'>+		SUBPLATFORM(DG2, G11), GRAPHICS_STEP(A0, B0)</div><div class='add'>+22012727170	SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, C0)</div><div class='add'>+		SUBPLATFORM(DG2, G11)</div><div class='add'>+22012727685	SUBPLATFORM(DG2, G11)</div><div class='add'>+16015675438	PLATFORM(PVC)</div><div class='add'>+		SUBPLATFORM(DG2, G10)</div><div class='add'>+		SUBPLATFORM(DG2, G12)</div><div class='add'>+18020744125	PLATFORM(PVC)</div><div class='add'>+1509372804	PLATFORM(PVC), GRAPHICS_STEP(A0, C0)</div><div class='add'>+1409600907	GRAPHICS_VERSION_RANGE(1200, 1250)</div><div class='add'>+14016763929	SUBPLATFORM(DG2, G10)</div><div class='add'>+		SUBPLATFORM(DG2, G12)</div><div class='add'>+16017236439	PLATFORM(PVC)</div><div class='add'>+22010954014	PLATFORM(DG2)</div><div class='add'>+14019821291	MEDIA_VERSION_RANGE(1300, 2000)</div><div class='add'>+14015076503	MEDIA_VERSION(1300)</div><div class='add'>+16020292621	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c<br/>new file mode 100644<br/>index 000000000000..a75eeba7bfe5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wait_user_fence.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wait_user_fence.c</a></div><div class='hunk'>@@ -0,0 +1,179 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_wait_user_fence.h"</div><div class='add'>+</div><div class='add'>+#include &lt;drm/drm_device.h&gt;</div><div class='add'>+#include &lt;drm/drm_file.h&gt;</div><div class='add'>+#include &lt;drm/drm_utils.h&gt;</div><div class='add'>+#include &lt;drm/xe_drm.h&gt;</div><div class='add'>+</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_macros.h"</div><div class='add'>+#include "xe_exec_queue.h"</div><div class='add'>+</div><div class='add'>+static int do_compare(u64 addr, u64 value, u64 mask, u16 op)</div><div class='add'>+{</div><div class='add'>+	u64 rvalue;</div><div class='add'>+	int err;</div><div class='add'>+	bool passed;</div><div class='add'>+</div><div class='add'>+	err = copy_from_user(&amp;rvalue, u64_to_user_ptr(addr), sizeof(rvalue));</div><div class='add'>+	if (err)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	switch (op) {</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_EQ:</div><div class='add'>+		passed = (rvalue &amp; mask) == (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_NEQ:</div><div class='add'>+		passed = (rvalue &amp; mask) != (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_GT:</div><div class='add'>+		passed = (rvalue &amp; mask) &gt; (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_GTE:</div><div class='add'>+		passed = (rvalue &amp; mask) &gt;= (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_LT:</div><div class='add'>+		passed = (rvalue &amp; mask) &lt; (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	case DRM_XE_UFENCE_WAIT_OP_LTE:</div><div class='add'>+		passed = (rvalue &amp; mask) &lt;= (value &amp; mask);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		XE_WARN_ON("Not possible");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return passed ? 0 : 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define VALID_FLAGS	DRM_XE_UFENCE_WAIT_FLAG_ABSTIME</div><div class='add'>+#define MAX_OP		DRM_XE_UFENCE_WAIT_OP_LTE</div><div class='add'>+</div><div class='add'>+static long to_jiffies_timeout(struct xe_device *xe,</div><div class='add'>+			       struct drm_xe_wait_user_fence *args)</div><div class='add'>+{</div><div class='add'>+	unsigned long long t;</div><div class='add'>+	long timeout;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For negative timeout we want to wait "forever" by setting</div><div class='add'>+	 * MAX_SCHEDULE_TIMEOUT. But we have to assign this value also</div><div class='add'>+	 * to args-&gt;timeout to avoid being zeroed on the signal delivery</div><div class='add'>+	 * (see arithmetics after wait).</div><div class='add'>+	 */</div><div class='add'>+	if (args-&gt;timeout &lt; 0) {</div><div class='add'>+		args-&gt;timeout = MAX_SCHEDULE_TIMEOUT;</div><div class='add'>+		return MAX_SCHEDULE_TIMEOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (args-&gt;timeout == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Save the timeout to an u64 variable because nsecs_to_jiffies</div><div class='add'>+	 * might return a value that overflows s32 variable.</div><div class='add'>+	 */</div><div class='add'>+	if (args-&gt;flags &amp; DRM_XE_UFENCE_WAIT_FLAG_ABSTIME)</div><div class='add'>+		t = drm_timeout_abs_to_jiffies(args-&gt;timeout);</div><div class='add'>+	else</div><div class='add'>+		t = nsecs_to_jiffies(args-&gt;timeout);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Anything greater then MAX_SCHEDULE_TIMEOUT is meaningless,</div><div class='add'>+	 * also we don't want to cap it at MAX_SCHEDULE_TIMEOUT because</div><div class='add'>+	 * apparently user doesn't mean to wait forever, otherwise the</div><div class='add'>+	 * args-&gt;timeout should have been set to a negative value.</div><div class='add'>+	 */</div><div class='add'>+	if (t &gt; MAX_SCHEDULE_TIMEOUT)</div><div class='add'>+		timeout = MAX_SCHEDULE_TIMEOUT - 1;</div><div class='add'>+	else</div><div class='add'>+		timeout = t;</div><div class='add'>+</div><div class='add'>+	return timeout ?: 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			     struct drm_file *file)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = to_xe_device(dev);</div><div class='add'>+	struct xe_file *xef = to_xe_file(file);</div><div class='add'>+	DEFINE_WAIT_FUNC(w_wait, woken_wake_function);</div><div class='add'>+	struct drm_xe_wait_user_fence *args = data;</div><div class='add'>+	struct xe_exec_queue *q = NULL;</div><div class='add'>+	u64 addr = args-&gt;addr;</div><div class='add'>+	int err = 0;</div><div class='add'>+	long timeout;</div><div class='add'>+	ktime_t start;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;extensions) || XE_IOCTL_DBG(xe, args-&gt;pad) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;pad2) ||</div><div class='add'>+	    XE_IOCTL_DBG(xe, args-&gt;reserved[0] || args-&gt;reserved[1]))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;flags &amp; ~VALID_FLAGS))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, args-&gt;op &gt; MAX_OP))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (XE_IOCTL_DBG(xe, addr &amp; 0x7))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (args-&gt;exec_queue_id) {</div><div class='add'>+		q = xe_exec_queue_lookup(xef, args-&gt;exec_queue_id);</div><div class='add'>+		if (XE_IOCTL_DBG(xe, !q))</div><div class='add'>+			return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	timeout = to_jiffies_timeout(xe, args);</div><div class='add'>+</div><div class='add'>+	start = ktime_get();</div><div class='add'>+</div><div class='add'>+	add_wait_queue(&amp;xe-&gt;ufence_wq, &amp;w_wait);</div><div class='add'>+	for (;;) {</div><div class='add'>+		err = do_compare(addr, args-&gt;value, args-&gt;mask, args-&gt;op);</div><div class='add'>+		if (err &lt;= 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (signal_pending(current)) {</div><div class='add'>+			err = -ERESTARTSYS;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (q) {</div><div class='add'>+			if (q-&gt;ops-&gt;reset_status(q)) {</div><div class='add'>+				drm_info(&amp;xe-&gt;drm, "exec gueue reset detected\n");</div><div class='add'>+				err = -EIO;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!timeout) {</div><div class='add'>+			err = -ETIME;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		timeout = wait_woken(&amp;w_wait, TASK_INTERRUPTIBLE, timeout);</div><div class='add'>+	}</div><div class='add'>+	remove_wait_queue(&amp;xe-&gt;ufence_wq, &amp;w_wait);</div><div class='add'>+</div><div class='add'>+	if (!(args-&gt;flags &amp; DRM_XE_UFENCE_WAIT_FLAG_ABSTIME)) {</div><div class='add'>+		args-&gt;timeout -= ktime_to_ns(ktime_sub(ktime_get(), start));</div><div class='add'>+		if (args-&gt;timeout &lt; 0)</div><div class='add'>+			args-&gt;timeout = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!timeout &amp;&amp; !(err &lt; 0))</div><div class='add'>+		err = -ETIME;</div><div class='add'>+</div><div class='add'>+	if (q)</div><div class='add'>+		xe_exec_queue_put(q);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.h b/drivers/gpu/drm/xe/xe_wait_user_fence.h<br/>new file mode 100644<br/>index 000000000000..0e268978f9e6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wait_user_fence.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wait_user_fence.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_WAIT_USER_FENCE_H_</div><div class='add'>+#define _XE_WAIT_USER_FENCE_H_</div><div class='add'>+</div><div class='add'>+struct drm_device;</div><div class='add'>+struct drm_file;</div><div class='add'>+</div><div class='add'>+int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,</div><div class='add'>+			     struct drm_file *file);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c<br/>new file mode 100644<br/>index 000000000000..d3a99157e523<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wopcm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm.c</a></div><div class='hunk'>@@ -0,0 +1,270 @@</div><div class='add'>+// SPDX-License-Identifier: MIT</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "xe_wopcm.h"</div><div class='add'>+</div><div class='add'>+#include "regs/xe_guc_regs.h"</div><div class='add'>+#include "xe_device.h"</div><div class='add'>+#include "xe_force_wake.h"</div><div class='add'>+#include "xe_gt.h"</div><div class='add'>+#include "xe_mmio.h"</div><div class='add'>+#include "xe_uc_fw.h"</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * DOC: Write Once Protected Content Memory (WOPCM) Layout</div><div class='add'>+ *</div><div class='add'>+ * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and</div><div class='add'>+ * offset registers whose values are calculated and determined by HuC/GuC</div><div class='add'>+ * firmware size and set of hardware requirements/restrictions as shown below:</div><div class='add'>+ *</div><div class='add'>+ * ::</div><div class='add'>+ *</div><div class='add'>+ *    +=========&gt; +====================+ &lt;== WOPCM Top</div><div class='add'>+ *    ^           |  HW contexts RSVD  |</div><div class='add'>+ *    |     +===&gt; +====================+ &lt;== GuC WOPCM Top</div><div class='add'>+ *    |     ^     |                    |</div><div class='add'>+ *    |     |     |                    |</div><div class='add'>+ *    |     |     |                    |</div><div class='add'>+ *    |    GuC    |                    |</div><div class='add'>+ *    |   WOPCM   |                    |</div><div class='add'>+ *    |    Size   +--------------------+</div><div class='add'>+ *  WOPCM   |     |    GuC FW RSVD     |</div><div class='add'>+ *    |     |     +--------------------+</div><div class='add'>+ *    |     |     |   GuC Stack RSVD   |</div><div class='add'>+ *    |     |     +------------------- +</div><div class='add'>+ *    |     v     |   GuC WOPCM RSVD   |</div><div class='add'>+ *    |     +===&gt; +====================+ &lt;== GuC WOPCM base</div><div class='add'>+ *    |           |     WOPCM RSVD     |</div><div class='add'>+ *    |           +------------------- + &lt;== HuC Firmware Top</div><div class='add'>+ *    v           |      HuC FW        |</div><div class='add'>+ *    +=========&gt; +====================+ &lt;== WOPCM Base</div><div class='add'>+ *</div><div class='add'>+ * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.</div><div class='add'>+ * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6</div><div class='add'>+ * context).</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */</div><div class='add'>+/* FIXME: Larger size require for 2 tile PVC, do a proper probe sooner or later */</div><div class='add'>+#define DGFX_WOPCM_SIZE			SZ_4M</div><div class='add'>+/* FIXME: Larger size require for MTL, do a proper probe sooner or later */</div><div class='add'>+#define MTL_WOPCM_SIZE			SZ_4M</div><div class='add'>+#define WOPCM_SIZE			SZ_2M</div><div class='add'>+</div><div class='add'>+#define MAX_WOPCM_SIZE			SZ_8M</div><div class='add'>+</div><div class='add'>+/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */</div><div class='add'>+#define WOPCM_RESERVED_SIZE		SZ_16K</div><div class='add'>+</div><div class='add'>+/* 16KB reserved at the beginning of GuC WOPCM. */</div><div class='add'>+#define GUC_WOPCM_RESERVED		SZ_16K</div><div class='add'>+/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */</div><div class='add'>+#define GUC_WOPCM_STACK_RESERVED	SZ_8K</div><div class='add'>+</div><div class='add'>+/* GuC WOPCM Offset value needs to be aligned to 16KB. */</div><div class='add'>+#define GUC_WOPCM_OFFSET_ALIGNMENT	(1UL &lt;&lt; GUC_WOPCM_OFFSET_SHIFT)</div><div class='add'>+</div><div class='add'>+/* 36KB WOPCM reserved at the end of WOPCM */</div><div class='add'>+#define WOPCM_HW_CTX_RESERVED		(SZ_32K + SZ_4K)</div><div class='add'>+</div><div class='add'>+static inline struct xe_gt *wopcm_to_gt(struct xe_wopcm *wopcm)</div><div class='add'>+{</div><div class='add'>+	return container_of(wopcm, struct xe_gt, uc.wopcm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct xe_device *wopcm_to_xe(struct xe_wopcm *wopcm)</div><div class='add'>+{</div><div class='add'>+	return gt_to_xe(wopcm_to_gt(wopcm));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 context_reserved_size(void)</div><div class='add'>+{</div><div class='add'>+	return WOPCM_HW_CTX_RESERVED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool __check_layout(struct xe_device *xe, u32 wopcm_size,</div><div class='add'>+			   u32 guc_wopcm_base, u32 guc_wopcm_size,</div><div class='add'>+			   u32 guc_fw_size, u32 huc_fw_size)</div><div class='add'>+{</div><div class='add'>+	const u32 ctx_rsvd = context_reserved_size();</div><div class='add'>+	u32 size;</div><div class='add'>+</div><div class='add'>+	size = wopcm_size - ctx_rsvd;</div><div class='add'>+	if (unlikely(guc_wopcm_base &gt;= size ||</div><div class='add'>+		     guc_wopcm_size &gt; size - guc_wopcm_base)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm,</div><div class='add'>+			"WOPCM: invalid GuC region layout: %uK + %uK &gt; %uK\n",</div><div class='add'>+			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,</div><div class='add'>+			size / SZ_1K);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;</div><div class='add'>+	if (unlikely(guc_wopcm_size &lt; size)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "WOPCM: no space for %s: %uK &lt; %uK\n",</div><div class='add'>+			xe_uc_fw_type_repr(XE_UC_FW_TYPE_GUC),</div><div class='add'>+			guc_wopcm_size / SZ_1K, size / SZ_1K);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = huc_fw_size + WOPCM_RESERVED_SIZE;</div><div class='add'>+	if (unlikely(guc_wopcm_base &lt; size)) {</div><div class='add'>+		drm_err(&amp;xe-&gt;drm, "WOPCM: no space for %s: %uK &lt; %uK\n",</div><div class='add'>+			xe_uc_fw_type_repr(XE_UC_FW_TYPE_HUC),</div><div class='add'>+			guc_wopcm_base / SZ_1K, size / SZ_1K);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool __wopcm_regs_locked(struct xe_gt *gt,</div><div class='add'>+				u32 *guc_wopcm_base, u32 *guc_wopcm_size)</div><div class='add'>+{</div><div class='add'>+	u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);</div><div class='add'>+	u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);</div><div class='add'>+</div><div class='add'>+	if (!(reg_size &amp; GUC_WOPCM_SIZE_LOCKED) ||</div><div class='add'>+	    !(reg_base &amp; GUC_WOPCM_OFFSET_VALID))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	*guc_wopcm_base = reg_base &amp; GUC_WOPCM_OFFSET_MASK;</div><div class='add'>+	*guc_wopcm_size = reg_size &amp; GUC_WOPCM_SIZE_MASK;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,</div><div class='add'>+			     struct xe_wopcm *wopcm)</div><div class='add'>+{</div><div class='add'>+	u32 base = wopcm-&gt;guc.base;</div><div class='add'>+	u32 size = wopcm-&gt;guc.size;</div><div class='add'>+	u32 huc_agent = xe_uc_fw_is_available(&amp;gt-&gt;uc.huc.fw) ? HUC_LOADING_AGENT_GUC : 0;</div><div class='add'>+	u32 mask;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	XE_WARN_ON(!(base &amp; GUC_WOPCM_OFFSET_MASK));</div><div class='add'>+	XE_WARN_ON(base &amp; ~GUC_WOPCM_OFFSET_MASK);</div><div class='add'>+	XE_WARN_ON(!(size &amp; GUC_WOPCM_SIZE_MASK));</div><div class='add'>+	XE_WARN_ON(size &amp; ~GUC_WOPCM_SIZE_MASK);</div><div class='add'>+</div><div class='add'>+	mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;</div><div class='add'>+	err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,</div><div class='add'>+					 size | GUC_WOPCM_SIZE_LOCKED);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;</div><div class='add'>+	err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,</div><div class='add'>+					 base | huc_agent, mask,</div><div class='add'>+					 base | huc_agent |</div><div class='add'>+					 GUC_WOPCM_OFFSET_VALID);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	drm_notice(&amp;xe-&gt;drm, "Failed to init uC WOPCM registers!\n");</div><div class='add'>+	drm_notice(&amp;xe-&gt;drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",</div><div class='add'>+		   DMA_GUC_WOPCM_OFFSET.addr,</div><div class='add'>+		   xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));</div><div class='add'>+	drm_notice(&amp;xe-&gt;drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",</div><div class='add'>+		   GUC_WOPCM_SIZE.addr,</div><div class='add'>+		   xe_mmio_read32(gt, GUC_WOPCM_SIZE));</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+u32 xe_wopcm_size(struct xe_device *xe)</div><div class='add'>+{</div><div class='add'>+	return IS_DGFX(xe) ? DGFX_WOPCM_SIZE :</div><div class='add'>+		xe-&gt;info.platform == XE_METEORLAKE ? MTL_WOPCM_SIZE :</div><div class='add'>+		WOPCM_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * xe_wopcm_init() - Initialize the WOPCM structure.</div><div class='add'>+ * @wopcm: pointer to xe_wopcm.</div><div class='add'>+ *</div><div class='add'>+ * This function will partition WOPCM space based on GuC and HuC firmware sizes</div><div class='add'>+ * and will allocate max remaining for use by GuC. This function will also</div><div class='add'>+ * enforce platform dependent hardware restrictions on GuC WOPCM offset and</div><div class='add'>+ * size. It will fail the WOPCM init if any of these checks fail, so that the</div><div class='add'>+ * following WOPCM registers setup and GuC firmware uploading would be aborted.</div><div class='add'>+ */</div><div class='add'>+int xe_wopcm_init(struct xe_wopcm *wopcm)</div><div class='add'>+{</div><div class='add'>+	struct xe_device *xe = wopcm_to_xe(wopcm);</div><div class='add'>+	struct xe_gt *gt = wopcm_to_gt(wopcm);</div><div class='add'>+	u32 guc_fw_size = xe_uc_fw_get_upload_size(&amp;gt-&gt;uc.guc.fw);</div><div class='add'>+	u32 huc_fw_size = xe_uc_fw_get_upload_size(&amp;gt-&gt;uc.huc.fw);</div><div class='add'>+	u32 ctx_rsvd = context_reserved_size();</div><div class='add'>+	u32 guc_wopcm_base;</div><div class='add'>+	u32 guc_wopcm_size;</div><div class='add'>+	bool locked;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!guc_fw_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	wopcm-&gt;size = xe_wopcm_size(xe);</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "WOPCM: %uK\n", wopcm-&gt;size / SZ_1K);</div><div class='add'>+</div><div class='add'>+	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);</div><div class='add'>+	XE_WARN_ON(guc_fw_size &gt;= wopcm-&gt;size);</div><div class='add'>+	XE_WARN_ON(huc_fw_size &gt;= wopcm-&gt;size);</div><div class='add'>+	XE_WARN_ON(ctx_rsvd + WOPCM_RESERVED_SIZE &gt;= wopcm-&gt;size);</div><div class='add'>+</div><div class='add'>+	locked = __wopcm_regs_locked(gt, &amp;guc_wopcm_base, &amp;guc_wopcm_size);</div><div class='add'>+	if (locked) {</div><div class='add'>+		drm_dbg(&amp;xe-&gt;drm, "GuC WOPCM is already locked [%uK, %uK)\n",</div><div class='add'>+			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);</div><div class='add'>+		/*</div><div class='add'>+		 * When the GuC wopcm base and size are preprogrammed by</div><div class='add'>+		 * BIOS/IFWI, check against the max allowed wopcm size to</div><div class='add'>+		 * validate if the programmed values align to the wopcm layout.</div><div class='add'>+		 */</div><div class='add'>+		wopcm-&gt;size = MAX_WOPCM_SIZE;</div><div class='add'>+</div><div class='add'>+		goto check;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Aligned value of guc_wopcm_base will determine available WOPCM space</div><div class='add'>+	 * for HuC firmware and mandatory reserved area.</div><div class='add'>+	 */</div><div class='add'>+	guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;</div><div class='add'>+	guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Need to clamp guc_wopcm_base now to make sure the following math is</div><div class='add'>+	 * correct. Formal check of whole WOPCM layout will be done below.</div><div class='add'>+	 */</div><div class='add'>+	guc_wopcm_base = min(guc_wopcm_base, wopcm-&gt;size - ctx_rsvd);</div><div class='add'>+</div><div class='add'>+	/* Aligned remainings of usable WOPCM space can be assigned to GuC. */</div><div class='add'>+	guc_wopcm_size = wopcm-&gt;size - ctx_rsvd - guc_wopcm_base;</div><div class='add'>+	guc_wopcm_size &amp;= GUC_WOPCM_SIZE_MASK;</div><div class='add'>+</div><div class='add'>+	drm_dbg(&amp;xe-&gt;drm, "Calculated GuC WOPCM [%uK, %uK)\n",</div><div class='add'>+		guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);</div><div class='add'>+</div><div class='add'>+check:</div><div class='add'>+	if (__check_layout(xe, wopcm-&gt;size, guc_wopcm_base, guc_wopcm_size,</div><div class='add'>+			   guc_fw_size, huc_fw_size)) {</div><div class='add'>+		wopcm-&gt;guc.base = guc_wopcm_base;</div><div class='add'>+		wopcm-&gt;guc.size = guc_wopcm_size;</div><div class='add'>+		XE_WARN_ON(!wopcm-&gt;guc.base);</div><div class='add'>+		XE_WARN_ON(!wopcm-&gt;guc.size);</div><div class='add'>+	} else {</div><div class='add'>+		drm_notice(&amp;xe-&gt;drm, "Unsuccessful WOPCM partitioning\n");</div><div class='add'>+		return -E2BIG;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!locked)</div><div class='add'>+		ret = __wopcm_init_regs(xe, gt, wopcm);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wopcm.h b/drivers/gpu/drm/xe/xe_wopcm.h<br/>new file mode 100644<br/>index 000000000000..0197a282460b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wopcm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm.h</a></div><div class='hunk'>@@ -0,0 +1,16 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_WOPCM_H_</div><div class='add'>+#define _XE_WOPCM_H_</div><div class='add'>+</div><div class='add'>+#include "xe_wopcm_types.h"</div><div class='add'>+</div><div class='add'>+struct xe_device;</div><div class='add'>+</div><div class='add'>+int xe_wopcm_init(struct xe_wopcm *wopcm);</div><div class='add'>+u32 xe_wopcm_size(struct xe_device *xe);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/gpu/drm/xe/xe_wopcm_types.h b/drivers/gpu/drm/xe/xe_wopcm_types.h<br/>new file mode 100644<br/>index 000000000000..486d850c4084<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/gpu/drm/xe/xe_wopcm_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/gpu/drm/xe/xe_wopcm_types.h</a></div><div class='hunk'>@@ -0,0 +1,26 @@</div><div class='add'>+/* SPDX-License-Identifier: MIT */</div><div class='add'>+/*</div><div class='add'>+ * Copyright © 2022 Intel Corporation</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _XE_WOPCM_TYPES_H_</div><div class='add'>+#define _XE_WOPCM_TYPES_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct xe_wopcm - Overall WOPCM info and WOPCM regions.</div><div class='add'>+ */</div><div class='add'>+struct xe_wopcm {</div><div class='add'>+	/** @size: Size of overall WOPCM */</div><div class='add'>+	u32 size;</div><div class='add'>+	/** @guc: GuC WOPCM Region info */</div><div class='add'>+	struct {</div><div class='add'>+		/** @base: GuC WOPCM base which is offset from WOPCM base */</div><div class='add'>+		u32 base;</div><div class='add'>+		/** @size: Size of the GuC WOPCM region */</div><div class='add'>+		u32 size;</div><div class='add'>+	} guc;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/greybus/Kconfig b/drivers/greybus/Kconfig<br/>index 033d31dbf3b8..ab81ceceb337 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/greybus/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/greybus/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/greybus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/greybus/Kconfig</a></div><div class='hunk'>@@ -20,6 +20,7 @@ if GREYBUS</div><div class='ctx'> config GREYBUS_BEAGLEPLAY</div><div class='ctx'> 	tristate "Greybus BeaglePlay driver"</div><div class='ctx'> 	depends on SERIAL_DEV_BUS</div><div class='add'>+	select CRC_CCITT</div><div class='ctx'> 	help</div><div class='ctx'> 	  Select this option if you have a BeaglePlay where CC1352</div><div class='ctx'> 	  co-processor acts as Greybus SVC.</div><div class='head'>diff --git a/drivers/greybus/gb-beagleplay.c b/drivers/greybus/gb-beagleplay.c<br/>index 43318c1993ba..c3e90025064b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/greybus/gb-beagleplay.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/greybus/gb-beagleplay.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/greybus/gb-beagleplay.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/greybus/gb-beagleplay.c</a></div><div class='hunk'>@@ -85,17 +85,31 @@ struct hdlc_payload {</div><div class='ctx'> 	void *buf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct hdlc_greybus_frame - Structure to represent greybus HDLC frame payload</div><div class='add'>+ *</div><div class='add'>+ * @cport: cport id</div><div class='add'>+ * @hdr: greybus operation header</div><div class='add'>+ * @payload: greybus message payload</div><div class='add'>+ *</div><div class='add'>+ * The HDLC payload sent over UART for greybus address has cport preappended to greybus message</div><div class='add'>+ */</div><div class='add'>+struct hdlc_greybus_frame {</div><div class='add'>+	__le16 cport;</div><div class='add'>+	struct gb_operation_msg_hdr hdr;</div><div class='add'>+	u8 payload[];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='ctx'> static void hdlc_rx_greybus_frame(struct gb_beagleplay *bg, u8 *buf, u16 len)</div><div class='ctx'> {</div><div class='del'>-	u16 cport_id;</div><div class='del'>-	struct gb_operation_msg_hdr *hdr = (struct gb_operation_msg_hdr *)buf;</div><div class='del'>-</div><div class='del'>-	memcpy(&amp;cport_id, hdr-&gt;pad, sizeof(cport_id));</div><div class='add'>+	struct hdlc_greybus_frame *gb_frame = (struct hdlc_greybus_frame *)buf;</div><div class='add'>+	u16 cport_id = le16_to_cpu(gb_frame-&gt;cport);</div><div class='add'>+	u16 gb_msg_len = le16_to_cpu(gb_frame-&gt;hdr.size);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;bg-&gt;sd-&gt;dev, "Greybus Operation %u type %X cport %u status %u received",</div><div class='del'>-		hdr-&gt;operation_id, hdr-&gt;type, cport_id, hdr-&gt;result);</div><div class='add'>+		gb_frame-&gt;hdr.operation_id, gb_frame-&gt;hdr.type, cport_id, gb_frame-&gt;hdr.result);</div><div class='ctx'> </div><div class='del'>-	greybus_data_rcvd(bg-&gt;gb_hd, cport_id, buf, len);</div><div class='add'>+	greybus_data_rcvd(bg-&gt;gb_hd, cport_id, (u8 *)&amp;gb_frame-&gt;hdr, gb_msg_len);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void hdlc_rx_dbg_frame(const struct gb_beagleplay *bg, const char *buf, u16 len)</div><div class='hunk'>@@ -257,7 +271,7 @@ static void hdlc_rx_frame(struct gb_beagleplay *bg)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hdlc_rx(struct gb_beagleplay *bg, const u8 *data, size_t count)</div><div class='add'>+static ssize_t hdlc_rx(struct gb_beagleplay *bg, const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	size_t i;</div><div class='ctx'> 	u8 c;</div><div class='hunk'>@@ -317,7 +331,8 @@ static void hdlc_deinit(struct gb_beagleplay *bg)</div><div class='ctx'> 	flush_work(&amp;bg-&gt;tx_work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gb_tty_receive(struct serdev_device *sd, const unsigned char *data, size_t count)</div><div class='add'>+static ssize_t gb_tty_receive(struct serdev_device *sd, const u8 *data,</div><div class='add'>+			      size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct gb_beagleplay *bg = serdev_device_get_drvdata(sd);</div><div class='ctx'> </div><div class='hunk'>@@ -336,25 +351,39 @@ static struct serdev_device_ops gb_beagleplay_ops = {</div><div class='ctx'> 	.write_wakeup = gb_tty_wakeup,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * gb_message_send() - Send greybus message using HDLC over UART</div><div class='add'>+ *</div><div class='add'>+ * @hd: pointer to greybus host device</div><div class='add'>+ * @cport: AP cport where message originates</div><div class='add'>+ * @msg: greybus message to send</div><div class='add'>+ * @mask: gfp mask</div><div class='add'>+ *</div><div class='add'>+ * Greybus HDLC frame has the following payload:</div><div class='add'>+ * 1. le16 cport</div><div class='add'>+ * 2. gb_operation_msg_hdr msg_header</div><div class='add'>+ * 3. u8 *msg_payload</div><div class='add'>+ */</div><div class='ctx'> static int gb_message_send(struct gb_host_device *hd, u16 cport, struct gb_message *msg, gfp_t mask)</div><div class='ctx'> {</div><div class='ctx'> 	struct gb_beagleplay *bg = dev_get_drvdata(&amp;hd-&gt;dev);</div><div class='del'>-	struct hdlc_payload payloads[2];</div><div class='add'>+	struct hdlc_payload payloads[3];</div><div class='add'>+	__le16 cport_id = cpu_to_le16(cport);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;hd-&gt;dev, "Sending greybus message with Operation %u, Type: %X on Cport %u",</div><div class='ctx'> 		msg-&gt;header-&gt;operation_id, msg-&gt;header-&gt;type, cport);</div><div class='ctx'> </div><div class='del'>-	if (msg-&gt;header-&gt;size &gt; RX_HDLC_PAYLOAD)</div><div class='add'>+	if (le16_to_cpu(msg-&gt;header-&gt;size) &gt; RX_HDLC_PAYLOAD)</div><div class='ctx'> 		return dev_err_probe(&amp;hd-&gt;dev, -E2BIG, "Greybus message too big");</div><div class='ctx'> </div><div class='del'>-	memcpy(msg-&gt;header-&gt;pad, &amp;cport, sizeof(cport));</div><div class='del'>-</div><div class='del'>-	payloads[0].buf = msg-&gt;header;</div><div class='del'>-	payloads[0].len = sizeof(*msg-&gt;header);</div><div class='del'>-	payloads[1].buf = msg-&gt;payload;</div><div class='del'>-	payloads[1].len = msg-&gt;payload_size;</div><div class='add'>+	payloads[0].buf = &amp;cport_id;</div><div class='add'>+	payloads[0].len = sizeof(cport_id);</div><div class='add'>+	payloads[1].buf = msg-&gt;header;</div><div class='add'>+	payloads[1].len = sizeof(*msg-&gt;header);</div><div class='add'>+	payloads[2].buf = msg-&gt;payload;</div><div class='add'>+	payloads[2].len = msg-&gt;payload_size;</div><div class='ctx'> </div><div class='del'>-	hdlc_tx_frames(bg, ADDRESS_GREYBUS, 0x03, payloads, 2);</div><div class='add'>+	hdlc_tx_frames(bg, ADDRESS_GREYBUS, 0x03, payloads, 3);</div><div class='ctx'> 	greybus_message_sent(bg-&gt;gb_hd, msg, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig<br/>index 4ce74af79657..4c682c650704 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/Kconfig</a></div><div class='hunk'>@@ -761,14 +761,15 @@ config HID_MULTITOUCH</div><div class='ctx'> 	  module will be called hid-multitouch.</div><div class='ctx'> </div><div class='ctx'> config HID_NINTENDO</div><div class='del'>-	tristate "Nintendo Joy-Con and Pro Controller support"</div><div class='add'>+	tristate "Nintendo Joy-Con, NSO, and Pro Controller support"</div><div class='ctx'> 	depends on NEW_LEDS</div><div class='ctx'> 	depends on LEDS_CLASS</div><div class='ctx'> 	select POWER_SUPPLY</div><div class='ctx'> 	help</div><div class='del'>-	Adds support for the Nintendo Switch Joy-Cons and Pro Controller.</div><div class='add'>+	Adds support for the Nintendo Switch Joy-Cons, NSO, Pro Controller.</div><div class='ctx'> 	All controllers support bluetooth, and the Pro Controller also supports</div><div class='del'>-	its USB mode.</div><div class='add'>+	its USB mode. This also includes support for the Nintendo Switch Online</div><div class='add'>+	Controllers which include the Genesis, SNES, and N64 controllers.</div><div class='ctx'> </div><div class='ctx'> 	To compile this driver as a module, choose M here: the</div><div class='ctx'> 	module will be called hid-nintendo.</div><div class='hunk'>@@ -779,9 +780,9 @@ config NINTENDO_FF</div><div class='ctx'> 	select INPUT_FF_MEMLESS</div><div class='ctx'> 	help</div><div class='ctx'> 	Say Y here if you have a Nintendo Switch controller and want to enable</div><div class='del'>-	force feedback support for it. This works for both joy-cons and the pro</div><div class='del'>-	controller. For the pro controller, both rumble motors can be controlled</div><div class='del'>-	individually.</div><div class='add'>+	force feedback support for it. This works for both joy-cons, the pro</div><div class='add'>+	controller, and the NSO N64 controller. For the pro controller, both</div><div class='add'>+	rumble motors can be controlled individually.</div><div class='ctx'> </div><div class='ctx'> config HID_NTI</div><div class='ctx'> 	tristate "NTI keyboard adapters"</div><div class='hunk'>@@ -1296,6 +1297,15 @@ config HID_ALPS</div><div class='ctx'> 	Say Y here if you have a Alps touchpads over i2c-hid or usbhid</div><div class='ctx'> 	and want support for its special functionalities.</div><div class='ctx'> </div><div class='add'>+config HID_MCP2200</div><div class='add'>+	tristate "Microchip MCP2200 HID USB-to-GPIO bridge"</div><div class='add'>+	depends on USB_HID &amp;&amp; GPIOLIB</div><div class='add'>+	help</div><div class='add'>+	  Provides GPIO functionality over USB-HID through MCP2200 device.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module</div><div class='add'>+	  will be called hid-mcp2200.ko.</div><div class='add'>+</div><div class='ctx'> config HID_MCP2221</div><div class='ctx'> 	tristate "Microchip MCP2221 HID USB-to-I2C/SMbus host support"</div><div class='ctx'> 	depends on USB_HID &amp;&amp; I2C</div><div class='head'>diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile<br/>index 8a06d0f840bc..082a728eac60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/Makefile</a></div><div class='hunk'>@@ -79,6 +79,7 @@ obj-$(CONFIG_HID_LOGITECH_HIDPP)	+= hid-logitech-hidpp.o</div><div class='ctx'> obj-$(CONFIG_HID_MACALLY)	+= hid-macally.o</div><div class='ctx'> obj-$(CONFIG_HID_MAGICMOUSE)	+= hid-magicmouse.o</div><div class='ctx'> obj-$(CONFIG_HID_MALTRON)	+= hid-maltron.o</div><div class='add'>+obj-$(CONFIG_HID_MCP2200)	+= hid-mcp2200.o</div><div class='ctx'> obj-$(CONFIG_HID_MCP2221)	+= hid-mcp2221.o</div><div class='ctx'> obj-$(CONFIG_HID_MAYFLASH)	+= hid-mf.o</div><div class='ctx'> obj-$(CONFIG_HID_MEGAWORLD_FF)	+= hid-megaworld.o</div><div class='head'>diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_common.h b/drivers/hid/amd-sfh-hid/amd_sfh_common.h<br/>index 2643bb14fee2..a1950bc6e6ce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/amd_sfh_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/amd-sfh-hid/amd_sfh_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/amd_sfh_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/amd_sfh_common.h</a></div><div class='hunk'>@@ -37,6 +37,11 @@ struct amd_mp2_sensor_info {</div><div class='ctx'> 	dma_addr_t dma_address;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct sfh_dev_status {</div><div class='add'>+	bool is_hpd_present;</div><div class='add'>+	bool is_als_present;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct amd_mp2_dev {</div><div class='ctx'> 	struct pci_dev *pdev;</div><div class='ctx'> 	struct amdtp_cl_data *cl_data;</div><div class='hunk'>@@ -47,6 +52,7 @@ struct amd_mp2_dev {</div><div class='ctx'> 	struct amd_input_data in_data;</div><div class='ctx'> 	/* mp2 active control status */</div><div class='ctx'> 	u32 mp2_acs;</div><div class='add'>+	struct sfh_dev_status dev_en;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct amd_mp2_ops {</div><div class='head'>diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c<br/>index 8a037de08e92..33fbdde8aff0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_desc.c</a></div><div class='hunk'>@@ -132,7 +132,7 @@ static void get_common_inputs(struct common_input_property *common, int report_i</div><div class='ctx'> 	common-&gt;event_type = HID_USAGE_SENSOR_EVENT_DATA_UPDATED_ENUM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int float_to_int(u32 flt32_val)</div><div class='add'>+int amd_sfh_float_to_int(u32 flt32_val)</div><div class='ctx'> {</div><div class='ctx'> 	int fraction, shift, mantissa, sign, exp, zeropre;</div><div class='ctx'> </div><div class='hunk'>@@ -201,9 +201,9 @@ static u8 get_input_rep(u8 current_index, int sensor_idx, int report_id,</div><div class='ctx'> 			     OFFSET_SENSOR_DATA_DEFAULT;</div><div class='ctx'> 		memcpy_fromio(&amp;accel_data, sensoraddr, sizeof(struct sfh_accel_data));</div><div class='ctx'> 		get_common_inputs(&amp;acc_input.common_property, report_id);</div><div class='del'>-		acc_input.in_accel_x_value = float_to_int(accel_data.acceldata.x) / 100;</div><div class='del'>-		acc_input.in_accel_y_value = float_to_int(accel_data.acceldata.y) / 100;</div><div class='del'>-		acc_input.in_accel_z_value = float_to_int(accel_data.acceldata.z) / 100;</div><div class='add'>+		acc_input.in_accel_x_value = amd_sfh_float_to_int(accel_data.acceldata.x) / 100;</div><div class='add'>+		acc_input.in_accel_y_value = amd_sfh_float_to_int(accel_data.acceldata.y) / 100;</div><div class='add'>+		acc_input.in_accel_z_value = amd_sfh_float_to_int(accel_data.acceldata.z) / 100;</div><div class='ctx'> 		memcpy(input_report, &amp;acc_input, sizeof(acc_input));</div><div class='ctx'> 		report_size = sizeof(acc_input);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -212,9 +212,9 @@ static u8 get_input_rep(u8 current_index, int sensor_idx, int report_id,</div><div class='ctx'> 			     OFFSET_SENSOR_DATA_DEFAULT;</div><div class='ctx'> 		memcpy_fromio(&amp;gyro_data, sensoraddr, sizeof(struct sfh_gyro_data));</div><div class='ctx'> 		get_common_inputs(&amp;gyro_input.common_property, report_id);</div><div class='del'>-		gyro_input.in_angel_x_value = float_to_int(gyro_data.gyrodata.x) / 1000;</div><div class='del'>-		gyro_input.in_angel_y_value = float_to_int(gyro_data.gyrodata.y) / 1000;</div><div class='del'>-		gyro_input.in_angel_z_value = float_to_int(gyro_data.gyrodata.z) / 1000;</div><div class='add'>+		gyro_input.in_angel_x_value = amd_sfh_float_to_int(gyro_data.gyrodata.x) / 1000;</div><div class='add'>+		gyro_input.in_angel_y_value = amd_sfh_float_to_int(gyro_data.gyrodata.y) / 1000;</div><div class='add'>+		gyro_input.in_angel_z_value = amd_sfh_float_to_int(gyro_data.gyrodata.z) / 1000;</div><div class='ctx'> 		memcpy(input_report, &amp;gyro_input, sizeof(gyro_input));</div><div class='ctx'> 		report_size = sizeof(gyro_input);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -223,9 +223,9 @@ static u8 get_input_rep(u8 current_index, int sensor_idx, int report_id,</div><div class='ctx'> 			     OFFSET_SENSOR_DATA_DEFAULT;</div><div class='ctx'> 		memcpy_fromio(&amp;mag_data, sensoraddr, sizeof(struct sfh_mag_data));</div><div class='ctx'> 		get_common_inputs(&amp;magno_input.common_property, report_id);</div><div class='del'>-		magno_input.in_magno_x = float_to_int(mag_data.magdata.x) / 100;</div><div class='del'>-		magno_input.in_magno_y = float_to_int(mag_data.magdata.y) / 100;</div><div class='del'>-		magno_input.in_magno_z = float_to_int(mag_data.magdata.z) / 100;</div><div class='add'>+		magno_input.in_magno_x = amd_sfh_float_to_int(mag_data.magdata.x) / 100;</div><div class='add'>+		magno_input.in_magno_y = amd_sfh_float_to_int(mag_data.magdata.y) / 100;</div><div class='add'>+		magno_input.in_magno_z = amd_sfh_float_to_int(mag_data.magdata.z) / 100;</div><div class='ctx'> 		magno_input.in_magno_accuracy = mag_data.accuracy / 100;</div><div class='ctx'> 		memcpy(input_report, &amp;magno_input, sizeof(magno_input));</div><div class='ctx'> 		report_size = sizeof(magno_input);</div><div class='hunk'>@@ -235,13 +235,15 @@ static u8 get_input_rep(u8 current_index, int sensor_idx, int report_id,</div><div class='ctx'> 			     OFFSET_SENSOR_DATA_DEFAULT;</div><div class='ctx'> 		memcpy_fromio(&amp;als_data, sensoraddr, sizeof(struct sfh_als_data));</div><div class='ctx'> 		get_common_inputs(&amp;als_input.common_property, report_id);</div><div class='del'>-		als_input.illuminance_value = float_to_int(als_data.lux);</div><div class='add'>+		als_input.illuminance_value = amd_sfh_float_to_int(als_data.lux);</div><div class='ctx'> </div><div class='ctx'> 		memcpy_fromio(&amp;binfo, mp2-&gt;vsbase, sizeof(struct sfh_base_info));</div><div class='ctx'> 		if (binfo.sbase.s_prop[ALS_IDX].sf.feat &amp; 0x2) {</div><div class='ctx'> 			als_input.light_color_temp = als_data.light_color_temp;</div><div class='del'>-			als_input.chromaticity_x_value = float_to_int(als_data.chromaticity_x);</div><div class='del'>-			als_input.chromaticity_y_value = float_to_int(als_data.chromaticity_y);</div><div class='add'>+			als_input.chromaticity_x_value =</div><div class='add'>+				amd_sfh_float_to_int(als_data.chromaticity_x);</div><div class='add'>+			als_input.chromaticity_y_value =</div><div class='add'>+				amd_sfh_float_to_int(als_data.chromaticity_y);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		report_size = sizeof(als_input);</div><div class='head'>diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c<br/>index e9c6413af24a..9dbe6f4cb294 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c</a></div><div class='hunk'>@@ -73,6 +73,15 @@ static int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata)</div><div class='ctx'> 	int i, status;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; cl_data-&gt;num_hid_devices; i++) {</div><div class='add'>+		switch (cl_data-&gt;sensor_idx[i]) {</div><div class='add'>+		case HPD_IDX:</div><div class='add'>+			privdata-&gt;dev_en.is_hpd_present = false;</div><div class='add'>+			break;</div><div class='add'>+		case ALS_IDX:</div><div class='add'>+			privdata-&gt;dev_en.is_als_present = false;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (cl_data-&gt;sensor_sts[i] == SENSOR_ENABLED) {</div><div class='ctx'> 			privdata-&gt;mp2_ops-&gt;stop(privdata, cl_data-&gt;sensor_idx[i]);</div><div class='ctx'> 			status = amd_sfh_wait_for_response</div><div class='hunk'>@@ -178,6 +187,14 @@ static int amd_sfh1_1_hid_client_init(struct amd_mp2_dev *privdata)</div><div class='ctx'> 			rc = amdtp_hid_probe(i, cl_data);</div><div class='ctx'> 			if (rc)</div><div class='ctx'> 				goto cleanup;</div><div class='add'>+			switch (cl_data-&gt;sensor_idx[i]) {</div><div class='add'>+			case HPD_IDX:</div><div class='add'>+				privdata-&gt;dev_en.is_hpd_present = true;</div><div class='add'>+				break;</div><div class='add'>+			case ALS_IDX:</div><div class='add'>+				privdata-&gt;dev_en.is_als_present = true;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		dev_dbg(dev, "sid 0x%x (%s) status 0x%x\n",</div><div class='ctx'> 			cl_data-&gt;sensor_idx[i], get_sensor_name(cl_data-&gt;sensor_idx[i]),</div><div class='hunk'>@@ -259,6 +276,7 @@ static void amd_mp2_pci_remove(void *privdata)</div><div class='ctx'> {</div><div class='ctx'> 	struct amd_mp2_dev *mp2 = privdata;</div><div class='ctx'> </div><div class='add'>+	sfh_deinit_emp2();</div><div class='ctx'> 	amd_sfh_hid_client_deinit(privdata);</div><div class='ctx'> 	mp2-&gt;mp2_ops-&gt;stop_all(mp2);</div><div class='ctx'> 	pci_intx(mp2-&gt;pdev, false);</div><div class='hunk'>@@ -311,12 +329,14 @@ int amd_sfh1_1_init(struct amd_mp2_dev *mp2)</div><div class='ctx'> </div><div class='ctx'> 	rc = amd_sfh_irq_init(mp2);</div><div class='ctx'> 	if (rc) {</div><div class='add'>+		sfh_deinit_emp2();</div><div class='ctx'> 		dev_err(dev, "amd_sfh_irq_init failed\n");</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rc = amd_sfh1_1_hid_client_init(mp2);</div><div class='ctx'> 	if (rc) {</div><div class='add'>+		sfh_deinit_emp2();</div><div class='ctx'> 		dev_err(dev, "amd_sfh1_1_hid_client_init failed\n");</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c<br/>index 4f81ef2d4f56..ae36312bc236 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c</a></div><div class='hunk'>@@ -7,11 +7,14 @@</div><div class='ctx'>  *</div><div class='ctx'>  * Author: Basavaraj Natikar &lt;Basavaraj.Natikar@amd.com&gt;</div><div class='ctx'>  */</div><div class='add'>+#include &lt;linux/amd-pmf-io.h&gt;</div><div class='ctx'> #include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "amd_sfh_interface.h"</div><div class='ctx'> </div><div class='add'>+static struct amd_mp2_dev *emp2;</div><div class='add'>+</div><div class='ctx'> static int amd_sfh_wait_response(struct amd_mp2_dev *mp2, u8 sid, u32 cmd_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct sfh_cmd_response cmd_resp;</div><div class='hunk'>@@ -73,7 +76,63 @@ static struct amd_mp2_ops amd_sfh_ops = {</div><div class='ctx'> 	.response = amd_sfh_wait_response,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+void sfh_deinit_emp2(void)</div><div class='add'>+{</div><div class='add'>+	emp2 = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void sfh_interface_init(struct amd_mp2_dev *mp2)</div><div class='ctx'> {</div><div class='ctx'> 	mp2-&gt;mp2_ops = &amp;amd_sfh_ops;</div><div class='add'>+	emp2 = mp2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amd_sfh_hpd_info(u8 *user_present)</div><div class='add'>+{</div><div class='add'>+	struct hpd_status hpdstatus;</div><div class='add'>+</div><div class='add'>+	if (!user_present)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!emp2 || !emp2-&gt;dev_en.is_hpd_present)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	hpdstatus.val = readl(emp2-&gt;mmio + AMD_C2P_MSG(4));</div><div class='add'>+	*user_present = hpdstatus.shpd.presence;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int amd_sfh_als_info(u32 *ambient_light)</div><div class='add'>+{</div><div class='add'>+	struct sfh_als_data als_data;</div><div class='add'>+	void __iomem *sensoraddr;</div><div class='add'>+</div><div class='add'>+	if (!ambient_light)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!emp2 || !emp2-&gt;dev_en.is_als_present)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	sensoraddr = emp2-&gt;vsbase +</div><div class='add'>+		(ALS_IDX * SENSOR_DATA_MEM_SIZE_DEFAULT) +</div><div class='add'>+		OFFSET_SENSOR_DATA_DEFAULT;</div><div class='add'>+	memcpy_fromio(&amp;als_data, sensoraddr, sizeof(struct sfh_als_data));</div><div class='add'>+	*ambient_light = amd_sfh_float_to_int(als_data.lux);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int amd_get_sfh_info(struct amd_sfh_info *sfh_info, enum sfh_message_type op)</div><div class='add'>+{</div><div class='add'>+	if (sfh_info) {</div><div class='add'>+		switch (op) {</div><div class='add'>+		case MT_HPD:</div><div class='add'>+			return amd_sfh_hpd_info(&amp;sfh_info-&gt;user_present);</div><div class='add'>+		case MT_ALS:</div><div class='add'>+			return amd_sfh_als_info(&amp;sfh_info-&gt;ambient_light);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return -EINVAL;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(amd_get_sfh_info);</div><div class='head'>diff --git a/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h b/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h<br/>index 656c3e95ef8c..2c211d28764d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.h</a></div><div class='hunk'>@@ -165,5 +165,7 @@ struct hpd_status {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void sfh_interface_init(struct amd_mp2_dev *mp2);</div><div class='add'>+void sfh_deinit_emp2(void);</div><div class='ctx'> void amd_sfh1_1_set_desc_ops(struct amd_mp2_ops *mp2_ops);</div><div class='add'>+int amd_sfh_float_to_int(u32 flt32_val);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/hid/hid-apple.c b/drivers/hid/hid-apple.c<br/>index d9e9829b2200..b9c7c0ed7bcc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-apple.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-apple.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-apple.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-apple.c</a></div><div class='hunk'>@@ -347,6 +347,8 @@ static const struct apple_non_apple_keyboard non_apple_keyboards[] = {</div><div class='ctx'> 	{ "Hailuck" },</div><div class='ctx'> 	{ "Jamesdonkey" },</div><div class='ctx'> 	{ "A3R" },</div><div class='add'>+	{ "hfd.cn" },</div><div class='add'>+	{ "WKB603" },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static bool apple_is_non_apple_keyboard(struct hid_device *hdev)</div><div class='head'>diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c<br/>index e0181218ad85..de7a477d6665 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-core.c</a></div><div class='hunk'>@@ -2749,7 +2749,7 @@ static int hid_uevent(const struct device *dev, struct kobj_uevent_env *env)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct bus_type hid_bus_type = {</div><div class='add'>+const struct bus_type hid_bus_type = {</div><div class='ctx'> 	.name		= "hid",</div><div class='ctx'> 	.dev_groups	= hid_dev_groups,</div><div class='ctx'> 	.drv_groups	= hid_drv_groups,</div><div class='head'>diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h<br/>index c6e4e0d1f214..fb30e228d35f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-ids.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-ids.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-ids.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-ids.h</a></div><div class='hunk'>@@ -740,6 +740,7 @@</div><div class='ctx'> </div><div class='ctx'> #define USB_VENDOR_ID_LABTEC		0x1020</div><div class='ctx'> #define USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD	0x0006</div><div class='add'>+#define USB_DEVICE_ID_LABTEC_ODDOR_HANDBRAKE	0x8888</div><div class='ctx'> </div><div class='ctx'> #define USB_VENDOR_ID_LAVIEW		0x22D4</div><div class='ctx'> #define USB_DEVICE_ID_GLORIOUS_MODEL_I	0x1503</div><div class='hunk'>@@ -915,6 +916,7 @@</div><div class='ctx'> #define USB_DEVICE_ID_PICK16F1454	0x0042</div><div class='ctx'> #define USB_DEVICE_ID_PICK16F1454_V2	0xf2f7</div><div class='ctx'> #define USB_DEVICE_ID_LUXAFOR		0xf372</div><div class='add'>+#define USB_DEVICE_ID_MCP2200		0x00df</div><div class='ctx'> #define USB_DEVICE_ID_MCP2221		0x00dd</div><div class='ctx'> </div><div class='ctx'> #define USB_VENDOR_ID_MICROSOFT		0x045e</div><div class='hunk'>@@ -986,7 +988,10 @@</div><div class='ctx'> #define USB_DEVICE_ID_NINTENDO_JOYCONL	0x2006</div><div class='ctx'> #define USB_DEVICE_ID_NINTENDO_JOYCONR	0x2007</div><div class='ctx'> #define USB_DEVICE_ID_NINTENDO_PROCON	0x2009</div><div class='del'>-#define USB_DEVICE_ID_NINTENDO_CHRGGRIP	0x200E</div><div class='add'>+#define USB_DEVICE_ID_NINTENDO_CHRGGRIP	0x200e</div><div class='add'>+#define USB_DEVICE_ID_NINTENDO_SNESCON	0x2017</div><div class='add'>+#define USB_DEVICE_ID_NINTENDO_GENCON	0x201e</div><div class='add'>+#define USB_DEVICE_ID_NINTENDO_N64CON	0x2019</div><div class='ctx'> </div><div class='ctx'> #define USB_VENDOR_ID_NOVATEK		0x0603</div><div class='ctx'> #define USB_DEVICE_ID_NOVATEK_PCT	0x0600</div><div class='head'>diff --git a/drivers/hid/hid-lenovo.c b/drivers/hid/hid-lenovo.c<br/>index 7c1b33be9d13..149a3c74346b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-lenovo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-lenovo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-lenovo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-lenovo.c</a></div><div class='hunk'>@@ -692,7 +692,8 @@ static int lenovo_event_cptkbd(struct hid_device *hdev,</div><div class='ctx'> 		 * so set middlebutton_state to 3</div><div class='ctx'> 		 * to never apply workaround anymore</div><div class='ctx'> 		 */</div><div class='del'>-		if (cptkbd_data-&gt;middlebutton_state == 1 &amp;&amp;</div><div class='add'>+		if (hdev-&gt;product == USB_DEVICE_ID_LENOVO_CUSBKBD &amp;&amp;</div><div class='add'>+				cptkbd_data-&gt;middlebutton_state == 1 &amp;&amp;</div><div class='ctx'> 				usage-&gt;type == EV_REL &amp;&amp;</div><div class='ctx'> 				(usage-&gt;code == REL_X || usage-&gt;code == REL_Y)) {</div><div class='ctx'> 			cptkbd_data-&gt;middlebutton_state = 3;</div><div class='head'>diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c<br/>index c9c968d4b36a..a46ff4e8b99f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-magicmouse.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-magicmouse.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-magicmouse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-magicmouse.c</a></div><div class='hunk'>@@ -120,6 +120,9 @@ MODULE_PARM_DESC(report_undeciphered, "Report undeciphered multi-touch state fie</div><div class='ctx'>  * @scroll_jiffies: Time of last scroll motion.</div><div class='ctx'>  * @touches: Most recent data for a touch, indexed by tracking ID.</div><div class='ctx'>  * @tracking_ids: Mapping of current touch input data to @touches.</div><div class='add'>+ * @hdev: Pointer to the underlying HID device.</div><div class='add'>+ * @work: Workqueue to handle initialization retry for quirky devices.</div><div class='add'>+ * @battery_timer: Timer for obtaining battery level information.</div><div class='ctx'>  */</div><div class='ctx'> struct magicmouse_sc {</div><div class='ctx'> 	struct input_dev *input;</div><div class='head'>diff --git a/drivers/hid/hid-mcp2200.c b/drivers/hid/hid-mcp2200.c<br/>new file mode 100644<br/>index 000000000000..bf57f7f6caa0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-mcp2200.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-mcp2200.c</a></div><div class='hunk'>@@ -0,0 +1,392 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * MCP2200 - Microchip USB to GPIO bridge</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023, Johannes Roith &lt;johannes@gnu-linux.rocks&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22228A.pdf</div><div class='add'>+ * App Note for HID: https://ww1.microchip.com/downloads/en/DeviceDoc/93066A.pdf</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/completion.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/gpio/driver.h&gt;</div><div class='add'>+#include &lt;linux/hid.h&gt;</div><div class='add'>+#include &lt;linux/hidraw.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include "hid-ids.h"</div><div class='add'>+</div><div class='add'>+/* Commands codes in a raw output report */</div><div class='add'>+#define SET_CLEAR_OUTPUTS	0x08</div><div class='add'>+#define CONFIGURE		0x10</div><div class='add'>+#define READ_EE			0x20</div><div class='add'>+#define WRITE_EE		0x40</div><div class='add'>+#define READ_ALL		0x80</div><div class='add'>+</div><div class='add'>+/* MCP GPIO direction encoding */</div><div class='add'>+enum MCP_IO_DIR {</div><div class='add'>+	MCP2200_DIR_OUT = 0x00,</div><div class='add'>+	MCP2200_DIR_IN  = 0x01,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Altternative pin assignments */</div><div class='add'>+#define TXLED		2</div><div class='add'>+#define RXLED		3</div><div class='add'>+#define USBCFG		6</div><div class='add'>+#define SSPND		7</div><div class='add'>+#define MCP_NGPIO	8</div><div class='add'>+</div><div class='add'>+/* CMD to set or clear a GPIO output */</div><div class='add'>+struct mcp_set_clear_outputs {</div><div class='add'>+	u8 cmd;</div><div class='add'>+	u8 dummys1[10];</div><div class='add'>+	u8 set_bmap;</div><div class='add'>+	u8 clear_bmap;</div><div class='add'>+	u8 dummys2[3];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* CMD to configure the IOs */</div><div class='add'>+struct mcp_configure {</div><div class='add'>+	u8 cmd;</div><div class='add'>+	u8 dummys1[3];</div><div class='add'>+	u8 io_bmap;</div><div class='add'>+	u8 config_alt_pins;</div><div class='add'>+	u8 io_default_val_bmap;</div><div class='add'>+	u8 config_alt_options;</div><div class='add'>+	u8 baud_h;</div><div class='add'>+	u8 baud_l;</div><div class='add'>+	u8 dummys2[6];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* CMD to read all parameters */</div><div class='add'>+struct mcp_read_all {</div><div class='add'>+	u8 cmd;</div><div class='add'>+	u8 dummys[15];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+/* Response to the read all cmd */</div><div class='add'>+struct mcp_read_all_resp {</div><div class='add'>+	u8 cmd;</div><div class='add'>+	u8 eep_addr;</div><div class='add'>+	u8 dummy;</div><div class='add'>+	u8 eep_val;</div><div class='add'>+	u8 io_bmap;</div><div class='add'>+	u8 config_alt_pins;</div><div class='add'>+	u8 io_default_val_bmap;</div><div class='add'>+	u8 config_alt_options;</div><div class='add'>+	u8 baud_h;</div><div class='add'>+	u8 baud_l;</div><div class='add'>+	u8 io_port_val_bmap;</div><div class='add'>+	u8 dummys[5];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct mcp2200 {</div><div class='add'>+	struct hid_device *hdev;</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	struct completion wait_in_report;</div><div class='add'>+	u8 gpio_dir;</div><div class='add'>+	u8 gpio_val;</div><div class='add'>+	u8 gpio_inval;</div><div class='add'>+	u8 baud_h;</div><div class='add'>+	u8 baud_l;</div><div class='add'>+	u8 config_alt_pins;</div><div class='add'>+	u8 gpio_reset_val;</div><div class='add'>+	u8 config_alt_options;</div><div class='add'>+	int status;</div><div class='add'>+	struct gpio_chip gc;</div><div class='add'>+	u8 hid_report[16];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* this executes the READ_ALL cmd */</div><div class='add'>+static int mcp_cmd_read_all(struct mcp2200 *mcp)</div><div class='add'>+{</div><div class='add'>+	struct mcp_read_all *read_all;</div><div class='add'>+	int len, t;</div><div class='add'>+</div><div class='add'>+	reinit_completion(&amp;mcp-&gt;wait_in_report);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcp-&gt;lock);</div><div class='add'>+</div><div class='add'>+	read_all = (struct mcp_read_all *) mcp-&gt;hid_report;</div><div class='add'>+	read_all-&gt;cmd = READ_ALL;</div><div class='add'>+	len = hid_hw_output_report(mcp-&gt;hdev, (u8 *) read_all,</div><div class='add'>+				   sizeof(struct mcp_read_all));</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;mcp-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (len != sizeof(struct mcp_read_all))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	t = wait_for_completion_timeout(&amp;mcp-&gt;wait_in_report,</div><div class='add'>+					msecs_to_jiffies(4000));</div><div class='add'>+	if (!t)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	/* return status, negative value if wrong response was received */</div><div class='add'>+	return mcp-&gt;status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mcp_set_multiple(struct gpio_chip *gc, unsigned long *mask,</div><div class='add'>+			     unsigned long *bits)</div><div class='add'>+{</div><div class='add'>+	struct mcp2200 *mcp = gpiochip_get_data(gc);</div><div class='add'>+	u8 value;</div><div class='add'>+	int status;</div><div class='add'>+	struct mcp_set_clear_outputs *cmd;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcp-&gt;lock);</div><div class='add'>+	cmd = (struct mcp_set_clear_outputs *) mcp-&gt;hid_report;</div><div class='add'>+</div><div class='add'>+	value = mcp-&gt;gpio_val &amp; ~*mask;</div><div class='add'>+	value |= (*mask &amp; *bits);</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd = SET_CLEAR_OUTPUTS;</div><div class='add'>+	cmd-&gt;set_bmap = value;</div><div class='add'>+	cmd-&gt;clear_bmap = ~(value);</div><div class='add'>+</div><div class='add'>+	status = hid_hw_output_report(mcp-&gt;hdev, (u8 *) cmd,</div><div class='add'>+		       sizeof(struct mcp_set_clear_outputs));</div><div class='add'>+</div><div class='add'>+	if (status == sizeof(struct mcp_set_clear_outputs))</div><div class='add'>+		mcp-&gt;gpio_val = value;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;mcp-&gt;lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mcp_set(struct gpio_chip *gc, unsigned int gpio_nr, int value)</div><div class='add'>+{</div><div class='add'>+	unsigned long mask = 1 &lt;&lt; gpio_nr;</div><div class='add'>+	unsigned long bmap_value = value &lt;&lt; gpio_nr;</div><div class='add'>+</div><div class='add'>+	mcp_set_multiple(gc, &amp;mask, &amp;bmap_value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_get_multiple(struct gpio_chip *gc, unsigned long *mask,</div><div class='add'>+		unsigned long *bits)</div><div class='add'>+{</div><div class='add'>+	u32 val;</div><div class='add'>+	struct mcp2200 *mcp = gpiochip_get_data(gc);</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	status = mcp_cmd_read_all(mcp);</div><div class='add'>+	if (status)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	val = mcp-&gt;gpio_inval;</div><div class='add'>+	*bits = (val &amp; *mask);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_get(struct gpio_chip *gc, unsigned int gpio_nr)</div><div class='add'>+{</div><div class='add'>+	unsigned long mask = 0, bits = 0;</div><div class='add'>+</div><div class='add'>+	mask = (1 &lt;&lt; gpio_nr);</div><div class='add'>+	mcp_get_multiple(gc, &amp;mask, &amp;bits);</div><div class='add'>+	return bits &gt; 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_get_direction(struct gpio_chip *gc, unsigned int gpio_nr)</div><div class='add'>+{</div><div class='add'>+	struct mcp2200 *mcp = gpiochip_get_data(gc);</div><div class='add'>+</div><div class='add'>+	return (mcp-&gt;gpio_dir &amp; (MCP2200_DIR_IN &lt;&lt; gpio_nr))</div><div class='add'>+		? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_set_direction(struct gpio_chip *gc, unsigned int gpio_nr,</div><div class='add'>+			     enum MCP_IO_DIR io_direction)</div><div class='add'>+{</div><div class='add'>+	struct mcp2200 *mcp = gpiochip_get_data(gc);</div><div class='add'>+	struct mcp_configure *conf;</div><div class='add'>+	int status;</div><div class='add'>+	/* after the configure cmd we will need to set the outputs again */</div><div class='add'>+	unsigned long mask = ~(mcp-&gt;gpio_dir); /* only set outputs */</div><div class='add'>+	unsigned long bits = mcp-&gt;gpio_val;</div><div class='add'>+	/* Offsets of alternative pins in config_alt_pins, 0 is not used */</div><div class='add'>+	u8 alt_pin_conf[8] = {SSPND, USBCFG, 0, 0, 0, 0, RXLED, TXLED};</div><div class='add'>+	u8 config_alt_pins = mcp-&gt;config_alt_pins;</div><div class='add'>+</div><div class='add'>+	/* Read in the reset baudrate first, we need it later */</div><div class='add'>+	status = mcp_cmd_read_all(mcp);</div><div class='add'>+	if (status != 0)</div><div class='add'>+		return status;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcp-&gt;lock);</div><div class='add'>+	conf = (struct mcp_configure  *) mcp-&gt;hid_report;</div><div class='add'>+</div><div class='add'>+	/* configure will reset the chip! */</div><div class='add'>+	conf-&gt;cmd = CONFIGURE;</div><div class='add'>+	conf-&gt;io_bmap = (mcp-&gt;gpio_dir &amp; ~(1 &lt;&lt; gpio_nr))</div><div class='add'>+		| (io_direction &lt;&lt; gpio_nr);</div><div class='add'>+	/* Don't overwrite the reset parameters */</div><div class='add'>+	conf-&gt;baud_h = mcp-&gt;baud_h;</div><div class='add'>+	conf-&gt;baud_l = mcp-&gt;baud_l;</div><div class='add'>+	conf-&gt;config_alt_options = mcp-&gt;config_alt_options;</div><div class='add'>+	conf-&gt;io_default_val_bmap = mcp-&gt;gpio_reset_val;</div><div class='add'>+	/* Adjust alt. func if necessary */</div><div class='add'>+	if (alt_pin_conf[gpio_nr])</div><div class='add'>+		config_alt_pins &amp;= ~(1 &lt;&lt; alt_pin_conf[gpio_nr]);</div><div class='add'>+	conf-&gt;config_alt_pins = config_alt_pins;</div><div class='add'>+</div><div class='add'>+	status = hid_hw_output_report(mcp-&gt;hdev, (u8 *) conf,</div><div class='add'>+				      sizeof(struct mcp_set_clear_outputs));</div><div class='add'>+</div><div class='add'>+	if (status == sizeof(struct mcp_set_clear_outputs)) {</div><div class='add'>+		mcp-&gt;gpio_dir = conf-&gt;io_bmap;</div><div class='add'>+		mcp-&gt;config_alt_pins = config_alt_pins;</div><div class='add'>+	} else {</div><div class='add'>+		mutex_unlock(&amp;mcp-&gt;lock);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;mcp-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Configure CMD will clear all IOs -&gt; rewrite them */</div><div class='add'>+	mcp_set_multiple(gc, &amp;mask, &amp;bits);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_direction_input(struct gpio_chip *gc, unsigned int gpio_nr)</div><div class='add'>+{</div><div class='add'>+	return mcp_set_direction(gc, gpio_nr, MCP2200_DIR_IN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp_direction_output(struct gpio_chip *gc, unsigned int gpio_nr,</div><div class='add'>+				int value)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	unsigned long mask, bmap_value;</div><div class='add'>+</div><div class='add'>+	mask = 1 &lt;&lt; gpio_nr;</div><div class='add'>+	bmap_value = value &lt;&lt; gpio_nr;</div><div class='add'>+</div><div class='add'>+	ret = mcp_set_direction(gc, gpio_nr, MCP2200_DIR_OUT);</div><div class='add'>+	if (!ret)</div><div class='add'>+		mcp_set_multiple(gc, &amp;mask, &amp;bmap_value);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct gpio_chip template_chip = {</div><div class='add'>+	.label			= "mcp2200",</div><div class='add'>+	.owner			= THIS_MODULE,</div><div class='add'>+	.get_direction		= mcp_get_direction,</div><div class='add'>+	.direction_input	= mcp_direction_input,</div><div class='add'>+	.direction_output	= mcp_direction_output,</div><div class='add'>+	.set			= mcp_set,</div><div class='add'>+	.set_multiple		= mcp_set_multiple,</div><div class='add'>+	.get			= mcp_get,</div><div class='add'>+	.get_multiple		= mcp_get_multiple,</div><div class='add'>+	.base			= -1,</div><div class='add'>+	.ngpio			= MCP_NGPIO,</div><div class='add'>+	.can_sleep		= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * MCP2200 uses interrupt endpoint for input reports. This function</div><div class='add'>+ * is called by HID layer when it receives i/p report from mcp2200,</div><div class='add'>+ * which is actually a response to the previously sent command.</div><div class='add'>+ */</div><div class='add'>+static int mcp2200_raw_event(struct hid_device *hdev, struct hid_report *report,</div><div class='add'>+		u8 *data, int size)</div><div class='add'>+{</div><div class='add'>+	struct mcp2200 *mcp = hid_get_drvdata(hdev);</div><div class='add'>+	struct mcp_read_all_resp *all_resp;</div><div class='add'>+</div><div class='add'>+	switch (data[0]) {</div><div class='add'>+	case READ_ALL:</div><div class='add'>+		all_resp = (struct mcp_read_all_resp *) data;</div><div class='add'>+		mcp-&gt;status = 0;</div><div class='add'>+		mcp-&gt;gpio_inval = all_resp-&gt;io_port_val_bmap;</div><div class='add'>+		mcp-&gt;baud_h = all_resp-&gt;baud_h;</div><div class='add'>+		mcp-&gt;baud_l = all_resp-&gt;baud_l;</div><div class='add'>+		mcp-&gt;gpio_reset_val = all_resp-&gt;io_default_val_bmap;</div><div class='add'>+		mcp-&gt;config_alt_pins = all_resp-&gt;config_alt_pins;</div><div class='add'>+		mcp-&gt;config_alt_options = all_resp-&gt;config_alt_options;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		mcp-&gt;status = -EIO;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	complete(&amp;mcp-&gt;wait_in_report);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp2200_probe(struct hid_device *hdev, const struct hid_device_id *id)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct mcp2200 *mcp;</div><div class='add'>+</div><div class='add'>+	mcp = devm_kzalloc(&amp;hdev-&gt;dev, sizeof(*mcp), GFP_KERNEL);</div><div class='add'>+	if (!mcp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = hid_parse(hdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "can't parse reports\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = hid_hw_start(hdev, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "can't start hardware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hid_info(hdev, "USB HID v%x.%02x Device [%s] on %s\n", hdev-&gt;version &gt;&gt; 8,</div><div class='add'>+			hdev-&gt;version &amp; 0xff, hdev-&gt;name, hdev-&gt;phys);</div><div class='add'>+</div><div class='add'>+	ret = hid_hw_open(hdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "can't open device\n");</div><div class='add'>+		hid_hw_stop(hdev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;mcp-&gt;lock);</div><div class='add'>+	init_completion(&amp;mcp-&gt;wait_in_report);</div><div class='add'>+	hid_set_drvdata(hdev, mcp);</div><div class='add'>+	mcp-&gt;hdev = hdev;</div><div class='add'>+</div><div class='add'>+	mcp-&gt;gc = template_chip;</div><div class='add'>+	mcp-&gt;gc.parent = &amp;hdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = devm_gpiochip_add_data(&amp;hdev-&gt;dev, &amp;mcp-&gt;gc, mcp);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		hid_err(hdev, "Unable to register gpiochip\n");</div><div class='add'>+		hid_hw_close(hdev);</div><div class='add'>+		hid_hw_stop(hdev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mcp2200_remove(struct hid_device *hdev)</div><div class='add'>+{</div><div class='add'>+	hid_hw_close(hdev);</div><div class='add'>+	hid_hw_stop(hdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hid_device_id mcp2200_devices[] = {</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_MCP2200) },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(hid, mcp2200_devices);</div><div class='add'>+</div><div class='add'>+static struct hid_driver mcp2200_driver = {</div><div class='add'>+	.name		= "mcp2200",</div><div class='add'>+	.id_table	= mcp2200_devices,</div><div class='add'>+	.probe		= mcp2200_probe,</div><div class='add'>+	.remove		= mcp2200_remove,</div><div class='add'>+	.raw_event	= mcp2200_raw_event,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Register with HID core */</div><div class='add'>+module_hid_driver(mcp2200_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Johannes Roith &lt;johannes@gnu-linux.rocks&gt;");</div><div class='add'>+MODULE_DESCRIPTION("MCP2200 Microchip HID USB to GPIO bridge");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/hid/hid-mcp2221.c b/drivers/hid/hid-mcp2221.c<br/>index aef0785c91cc..f9cceaeffd08 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-mcp2221.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-mcp2221.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-mcp2221.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-mcp2221.c</a></div><div class='hunk'>@@ -49,6 +49,7 @@ enum {</div><div class='ctx'> 	MCP2221_I2C_MASK_ADDR_NACK = 0x40,</div><div class='ctx'> 	MCP2221_I2C_WRADDRL_SEND = 0x21,</div><div class='ctx'> 	MCP2221_I2C_ADDR_NACK = 0x25,</div><div class='add'>+	MCP2221_I2C_READ_PARTIAL = 0x54,</div><div class='ctx'> 	MCP2221_I2C_READ_COMPL = 0x55,</div><div class='ctx'> 	MCP2221_ALT_F_NOT_GPIOV = 0xEE,</div><div class='ctx'> 	MCP2221_ALT_F_NOT_GPIOD = 0xEF,</div><div class='hunk'>@@ -187,6 +188,25 @@ static int mcp_cancel_last_cmd(struct mcp2221 *mcp)</div><div class='ctx'> 	return mcp_send_data_req_status(mcp, mcp-&gt;txbuf, 8);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Check if the last command succeeded or failed and return the result.</div><div class='add'>+ * If the command did fail, cancel that command which will free the i2c bus.</div><div class='add'>+ */</div><div class='add'>+static int mcp_chk_last_cmd_status_free_bus(struct mcp2221 *mcp)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mcp_chk_last_cmd_status(mcp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		/* The last command was a failure.</div><div class='add'>+		 * Send a cancel which will also free the bus.</div><div class='add'>+		 */</div><div class='add'>+		usleep_range(980, 1000);</div><div class='add'>+		mcp_cancel_last_cmd(mcp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mcp_set_i2c_speed(struct mcp2221 *mcp)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -241,7 +261,7 @@ static int mcp_i2c_write(struct mcp2221 *mcp,</div><div class='ctx'> 		usleep_range(980, 1000);</div><div class='ctx'> </div><div class='ctx'> 		if (last_status) {</div><div class='del'>-			ret = mcp_chk_last_cmd_status(mcp);</div><div class='add'>+			ret = mcp_chk_last_cmd_status_free_bus(mcp);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -278,6 +298,7 @@ static int mcp_i2c_smbus_read(struct mcp2221 *mcp,</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u16 total_len;</div><div class='add'>+	int retries = 0;</div><div class='ctx'> </div><div class='ctx'> 	mcp-&gt;txbuf[0] = type;</div><div class='ctx'> 	if (msg) {</div><div class='hunk'>@@ -301,20 +322,31 @@ static int mcp_i2c_smbus_read(struct mcp2221 *mcp,</div><div class='ctx'> 	mcp-&gt;rxbuf_idx = 0;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='add'>+		/* Wait for the data to be read by the device */</div><div class='add'>+		usleep_range(980, 1000);</div><div class='add'>+</div><div class='ctx'> 		memset(mcp-&gt;txbuf, 0, 4);</div><div class='ctx'> 		mcp-&gt;txbuf[0] = MCP2221_I2C_GET_DATA;</div><div class='ctx'> </div><div class='ctx'> 		ret = mcp_send_data_req_status(mcp, mcp-&gt;txbuf, 1);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		ret = mcp_chk_last_cmd_status(mcp);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		usleep_range(980, 1000);</div><div class='add'>+		if (ret) {</div><div class='add'>+			if (retries &lt; 5) {</div><div class='add'>+				/* The data wasn't ready to read.</div><div class='add'>+				 * Wait a bit longer and try again.</div><div class='add'>+				 */</div><div class='add'>+				usleep_range(90, 100);</div><div class='add'>+				retries++;</div><div class='add'>+			} else {</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			retries = 0;</div><div class='add'>+		}</div><div class='ctx'> 	} while (mcp-&gt;rxbuf_idx &lt; total_len);</div><div class='ctx'> </div><div class='add'>+	usleep_range(980, 1000);</div><div class='add'>+	ret = mcp_chk_last_cmd_status_free_bus(mcp);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -328,11 +360,6 @@ static int mcp_i2c_xfer(struct i2c_adapter *adapter,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mcp-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	/* Setting speed before every transaction is required for mcp2221 */</div><div class='del'>-	ret = mcp_set_i2c_speed(mcp);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto exit;</div><div class='del'>-</div><div class='ctx'> 	if (num == 1) {</div><div class='ctx'> 		if (msgs-&gt;flags &amp; I2C_M_RD) {</div><div class='ctx'> 			ret = mcp_i2c_smbus_read(mcp, msgs, MCP2221_I2C_RD_DATA,</div><div class='hunk'>@@ -417,9 +444,7 @@ static int mcp_smbus_write(struct mcp2221 *mcp, u16 addr,</div><div class='ctx'> 	if (last_status) {</div><div class='ctx'> 		usleep_range(980, 1000);</div><div class='ctx'> </div><div class='del'>-		ret = mcp_chk_last_cmd_status(mcp);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		ret = mcp_chk_last_cmd_status_free_bus(mcp);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -437,10 +462,6 @@ static int mcp_smbus_xfer(struct i2c_adapter *adapter, u16 addr,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mcp-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	ret = mcp_set_i2c_speed(mcp);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto exit;</div><div class='del'>-</div><div class='ctx'> 	switch (size) {</div><div class='ctx'> </div><div class='ctx'> 	case I2C_SMBUS_QUICK:</div><div class='hunk'>@@ -791,7 +812,8 @@ static int mcp2221_raw_event(struct hid_device *hdev,</div><div class='ctx'> 				mcp-&gt;status = -EIO;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='del'>-			if (data[2] == MCP2221_I2C_READ_COMPL) {</div><div class='add'>+			if (data[2] == MCP2221_I2C_READ_COMPL ||</div><div class='add'>+			    data[2] == MCP2221_I2C_READ_PARTIAL) {</div><div class='ctx'> 				buf = mcp-&gt;rxbuf;</div><div class='ctx'> 				memcpy(&amp;buf[mcp-&gt;rxbuf_idx], &amp;data[4], data[3]);</div><div class='ctx'> 				mcp-&gt;rxbuf_idx = mcp-&gt;rxbuf_idx + data[3];</div><div class='hunk'>@@ -1150,12 +1172,18 @@ static int mcp2221_probe(struct hid_device *hdev,</div><div class='ctx'> 	if (i2c_clk_freq &lt; 50)</div><div class='ctx'> 		i2c_clk_freq = 50;</div><div class='ctx'> 	mcp-&gt;cur_i2c_clk_div = (12000000 / (i2c_clk_freq * 1000)) - 3;</div><div class='add'>+	ret = mcp_set_i2c_speed(mcp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "can't set i2c speed: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mcp-&gt;adapter.owner = THIS_MODULE;</div><div class='ctx'> 	mcp-&gt;adapter.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	mcp-&gt;adapter.algo = &amp;mcp_i2c_algo;</div><div class='ctx'> 	mcp-&gt;adapter.retries = 1;</div><div class='ctx'> 	mcp-&gt;adapter.dev.parent = &amp;hdev-&gt;dev;</div><div class='add'>+	ACPI_COMPANION_SET(&amp;mcp-&gt;adapter.dev, ACPI_COMPANION(hdev-&gt;dev.parent));</div><div class='ctx'> 	snprintf(mcp-&gt;adapter.name, sizeof(mcp-&gt;adapter.name),</div><div class='ctx'> 			"MCP2221 usb-i2c bridge");</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hid/hid-nintendo.c b/drivers/hid/hid-nintendo.c<br/>index 138f154fecef..ccc4032fb2b0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-nintendo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-nintendo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-nintendo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-nintendo.c</a></div><div class='hunk'>@@ -3,6 +3,9 @@</div><div class='ctx'>  * HID driver for Nintendo Switch Joy-Cons and Pro Controllers</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (c) 2019-2021 Daniel J. Ogorchock &lt;djogorchock@gmail.com&gt;</div><div class='add'>+ * Portions Copyright (c) 2020 Nadia Holmquist Pedersen &lt;nadia@nhp.sh&gt;</div><div class='add'>+ * Copyright (c) 2022 Emily Strickland &lt;linux@emily.st&gt;</div><div class='add'>+ * Copyright (c) 2023 Ryan McClelland &lt;rymcclel@gmail.com&gt;</div><div class='ctx'>  *</div><div class='ctx'>  * The following resources/projects were referenced for this driver:</div><div class='ctx'>  *   https://github.com/dekuNukem/Nintendo_Switch_Reverse_Engineering</div><div class='hunk'>@@ -17,6 +20,9 @@</div><div class='ctx'>  * This driver supports the Nintendo Switch Joy-Cons and Pro Controllers. The</div><div class='ctx'>  * Pro Controllers can either be used over USB or Bluetooth.</div><div class='ctx'>  *</div><div class='add'>+ * This driver also incorporates support for Nintendo Switch Online controllers</div><div class='add'>+ * for the NES, SNES, Sega Genesis, and N64.</div><div class='add'>+ *</div><div class='ctx'>  * The driver will retrieve the factory calibration info from the controllers,</div><div class='ctx'>  * so little to no user calibration should be required.</div><div class='ctx'>  *</div><div class='hunk'>@@ -305,9 +311,14 @@ enum joycon_ctlr_state {</div><div class='ctx'> </div><div class='ctx'> /* Controller type received as part of device info */</div><div class='ctx'> enum joycon_ctlr_type {</div><div class='del'>-	JOYCON_CTLR_TYPE_JCL = 0x01,</div><div class='del'>-	JOYCON_CTLR_TYPE_JCR = 0x02,</div><div class='del'>-	JOYCON_CTLR_TYPE_PRO = 0x03,</div><div class='add'>+	JOYCON_CTLR_TYPE_JCL  = 0x01,</div><div class='add'>+	JOYCON_CTLR_TYPE_JCR  = 0x02,</div><div class='add'>+	JOYCON_CTLR_TYPE_PRO  = 0x03,</div><div class='add'>+	JOYCON_CTLR_TYPE_NESL = 0x09,</div><div class='add'>+	JOYCON_CTLR_TYPE_NESR = 0x0A,</div><div class='add'>+	JOYCON_CTLR_TYPE_SNES = 0x0B,</div><div class='add'>+	JOYCON_CTLR_TYPE_GEN  = 0x0D,</div><div class='add'>+	JOYCON_CTLR_TYPE_N64  = 0x0C,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct joycon_stick_cal {</div><div class='hunk'>@@ -325,28 +336,159 @@ struct joycon_imu_cal {</div><div class='ctx'>  * All the controller's button values are stored in a u32.</div><div class='ctx'>  * They can be accessed with bitwise ANDs.</div><div class='ctx'>  */</div><div class='del'>-static const u32 JC_BTN_Y	= BIT(0);</div><div class='del'>-static const u32 JC_BTN_X	= BIT(1);</div><div class='del'>-static const u32 JC_BTN_B	= BIT(2);</div><div class='del'>-static const u32 JC_BTN_A	= BIT(3);</div><div class='del'>-static const u32 JC_BTN_SR_R	= BIT(4);</div><div class='del'>-static const u32 JC_BTN_SL_R	= BIT(5);</div><div class='del'>-static const u32 JC_BTN_R	= BIT(6);</div><div class='del'>-static const u32 JC_BTN_ZR	= BIT(7);</div><div class='del'>-static const u32 JC_BTN_MINUS	= BIT(8);</div><div class='del'>-static const u32 JC_BTN_PLUS	= BIT(9);</div><div class='del'>-static const u32 JC_BTN_RSTICK	= BIT(10);</div><div class='del'>-static const u32 JC_BTN_LSTICK	= BIT(11);</div><div class='del'>-static const u32 JC_BTN_HOME	= BIT(12);</div><div class='del'>-static const u32 JC_BTN_CAP	= BIT(13); /* capture button */</div><div class='del'>-static const u32 JC_BTN_DOWN	= BIT(16);</div><div class='del'>-static const u32 JC_BTN_UP	= BIT(17);</div><div class='del'>-static const u32 JC_BTN_RIGHT	= BIT(18);</div><div class='del'>-static const u32 JC_BTN_LEFT	= BIT(19);</div><div class='del'>-static const u32 JC_BTN_SR_L	= BIT(20);</div><div class='del'>-static const u32 JC_BTN_SL_L	= BIT(21);</div><div class='del'>-static const u32 JC_BTN_L	= BIT(22);</div><div class='del'>-static const u32 JC_BTN_ZL	= BIT(23);</div><div class='add'>+#define JC_BTN_Y	 BIT(0)</div><div class='add'>+#define JC_BTN_X	 BIT(1)</div><div class='add'>+#define JC_BTN_B	 BIT(2)</div><div class='add'>+#define JC_BTN_A	 BIT(3)</div><div class='add'>+#define JC_BTN_SR_R	 BIT(4)</div><div class='add'>+#define JC_BTN_SL_R	 BIT(5)</div><div class='add'>+#define JC_BTN_R	 BIT(6)</div><div class='add'>+#define JC_BTN_ZR	 BIT(7)</div><div class='add'>+#define JC_BTN_MINUS	 BIT(8)</div><div class='add'>+#define JC_BTN_PLUS	 BIT(9)</div><div class='add'>+#define JC_BTN_RSTICK	 BIT(10)</div><div class='add'>+#define JC_BTN_LSTICK	 BIT(11)</div><div class='add'>+#define JC_BTN_HOME	 BIT(12)</div><div class='add'>+#define JC_BTN_CAP	 BIT(13) /* capture button */</div><div class='add'>+#define JC_BTN_DOWN	 BIT(16)</div><div class='add'>+#define JC_BTN_UP	 BIT(17)</div><div class='add'>+#define JC_BTN_RIGHT	 BIT(18)</div><div class='add'>+#define JC_BTN_LEFT	 BIT(19)</div><div class='add'>+#define JC_BTN_SR_L	 BIT(20)</div><div class='add'>+#define JC_BTN_SL_L	 BIT(21)</div><div class='add'>+#define JC_BTN_L	 BIT(22)</div><div class='add'>+#define JC_BTN_ZL	 BIT(23)</div><div class='add'>+</div><div class='add'>+struct joycon_ctlr_button_mapping {</div><div class='add'>+	u32 code;</div><div class='add'>+	u32 bit;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * D-pad is configured as buttons for the left Joy-Con only!</div><div class='add'>+ */</div><div class='add'>+static const struct joycon_ctlr_button_mapping left_joycon_button_mappings[] = {</div><div class='add'>+	{ BTN_TL,		JC_BTN_L,	},</div><div class='add'>+	{ BTN_TL2,		JC_BTN_ZL,	},</div><div class='add'>+	{ BTN_SELECT,		JC_BTN_MINUS,	},</div><div class='add'>+	{ BTN_THUMBL,		JC_BTN_LSTICK,	},</div><div class='add'>+	{ BTN_DPAD_UP,		JC_BTN_UP,	},</div><div class='add'>+	{ BTN_DPAD_DOWN,	JC_BTN_DOWN,	},</div><div class='add'>+	{ BTN_DPAD_LEFT,	JC_BTN_LEFT,	},</div><div class='add'>+	{ BTN_DPAD_RIGHT,	JC_BTN_RIGHT,	},</div><div class='add'>+	{ BTN_Z,		JC_BTN_CAP,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The unused *right*-side triggers become the SL/SR triggers for the *left*</div><div class='add'>+ * Joy-Con, if and only if we're not using a charging grip.</div><div class='add'>+ */</div><div class='add'>+static const struct joycon_ctlr_button_mapping left_joycon_s_button_mappings[] = {</div><div class='add'>+	{ BTN_TR,	JC_BTN_SL_L,	},</div><div class='add'>+	{ BTN_TR2,	JC_BTN_SR_L,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct joycon_ctlr_button_mapping right_joycon_button_mappings[] = {</div><div class='add'>+	{ BTN_EAST,	JC_BTN_A,	},</div><div class='add'>+	{ BTN_SOUTH,	JC_BTN_B,	},</div><div class='add'>+	{ BTN_NORTH,	JC_BTN_X,	},</div><div class='add'>+	{ BTN_WEST,	JC_BTN_Y,	},</div><div class='add'>+	{ BTN_TR,	JC_BTN_R,	},</div><div class='add'>+	{ BTN_TR2,	JC_BTN_ZR,	},</div><div class='add'>+	{ BTN_START,	JC_BTN_PLUS,	},</div><div class='add'>+	{ BTN_THUMBR,	JC_BTN_RSTICK,	},</div><div class='add'>+	{ BTN_MODE,	JC_BTN_HOME,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The unused *left*-side triggers become the SL/SR triggers for the *right*</div><div class='add'>+ * Joy-Con, if and only if we're not using a charging grip.</div><div class='add'>+ */</div><div class='add'>+static const struct joycon_ctlr_button_mapping right_joycon_s_button_mappings[] = {</div><div class='add'>+	{ BTN_TL,	JC_BTN_SL_R,	},</div><div class='add'>+	{ BTN_TL2,	JC_BTN_SR_R,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct joycon_ctlr_button_mapping procon_button_mappings[] = {</div><div class='add'>+	{ BTN_EAST,	JC_BTN_A,	},</div><div class='add'>+	{ BTN_SOUTH,	JC_BTN_B,	},</div><div class='add'>+	{ BTN_NORTH,	JC_BTN_X,	},</div><div class='add'>+	{ BTN_WEST,	JC_BTN_Y,	},</div><div class='add'>+	{ BTN_TL,	JC_BTN_L,	},</div><div class='add'>+	{ BTN_TR,	JC_BTN_R,	},</div><div class='add'>+	{ BTN_TL2,	JC_BTN_ZL,	},</div><div class='add'>+	{ BTN_TR2,	JC_BTN_ZR,	},</div><div class='add'>+	{ BTN_SELECT,	JC_BTN_MINUS,	},</div><div class='add'>+	{ BTN_START,	JC_BTN_PLUS,	},</div><div class='add'>+	{ BTN_THUMBL,	JC_BTN_LSTICK,	},</div><div class='add'>+	{ BTN_THUMBR,	JC_BTN_RSTICK,	},</div><div class='add'>+	{ BTN_MODE,	JC_BTN_HOME,	},</div><div class='add'>+	{ BTN_Z,	JC_BTN_CAP,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct joycon_ctlr_button_mapping nescon_button_mappings[] = {</div><div class='add'>+	{ BTN_SOUTH,	JC_BTN_A,	},</div><div class='add'>+	{ BTN_EAST,	JC_BTN_B,	},</div><div class='add'>+	{ BTN_TL,	JC_BTN_L,	},</div><div class='add'>+	{ BTN_TR,	JC_BTN_R,	},</div><div class='add'>+	{ BTN_SELECT,	JC_BTN_MINUS,	},</div><div class='add'>+	{ BTN_START,	JC_BTN_PLUS,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct joycon_ctlr_button_mapping snescon_button_mappings[] = {</div><div class='add'>+	{ BTN_EAST,	JC_BTN_A,	},</div><div class='add'>+	{ BTN_SOUTH,	JC_BTN_B,	},</div><div class='add'>+	{ BTN_NORTH,	JC_BTN_X,	},</div><div class='add'>+	{ BTN_WEST,	JC_BTN_Y,	},</div><div class='add'>+	{ BTN_TL,	JC_BTN_L,	},</div><div class='add'>+	{ BTN_TR,	JC_BTN_R,	},</div><div class='add'>+	{ BTN_TL2,	JC_BTN_ZL,	},</div><div class='add'>+	{ BTN_TR2,	JC_BTN_ZR,	},</div><div class='add'>+	{ BTN_SELECT,	JC_BTN_MINUS,	},</div><div class='add'>+	{ BTN_START,	JC_BTN_PLUS,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * "A", "B", and "C" are mapped positionally, rather than by label (e.g., "A"</div><div class='add'>+ * gets assigned to BTN_EAST instead of BTN_A).</div><div class='add'>+ */</div><div class='add'>+static const struct joycon_ctlr_button_mapping gencon_button_mappings[] = {</div><div class='add'>+	{ BTN_SOUTH,	JC_BTN_A,	},</div><div class='add'>+	{ BTN_EAST,	JC_BTN_B,	},</div><div class='add'>+	{ BTN_WEST,	JC_BTN_R,	},</div><div class='add'>+	{ BTN_SELECT,	JC_BTN_ZR,	},</div><div class='add'>+	{ BTN_START,	JC_BTN_PLUS,	},</div><div class='add'>+	{ BTN_MODE,	JC_BTN_HOME,	},</div><div class='add'>+	{ BTN_Z,	JC_BTN_CAP,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * N64's C buttons get assigned to d-pad directions and registered as buttons.</div><div class='add'>+ */</div><div class='add'>+static const struct joycon_ctlr_button_mapping n64con_button_mappings[] = {</div><div class='add'>+	{ BTN_A,		JC_BTN_A,	},</div><div class='add'>+	{ BTN_B,		JC_BTN_B,	},</div><div class='add'>+	{ BTN_TL2,		JC_BTN_ZL,	}, /* Z */</div><div class='add'>+	{ BTN_TL,		JC_BTN_L,	},</div><div class='add'>+	{ BTN_TR,		JC_BTN_R,	},</div><div class='add'>+	{ BTN_TR2,		JC_BTN_LSTICK,	}, /* ZR */</div><div class='add'>+	{ BTN_START,		JC_BTN_PLUS,	},</div><div class='add'>+	{ BTN_FORWARD,		JC_BTN_Y,	}, /* C UP */</div><div class='add'>+	{ BTN_BACK,		JC_BTN_ZR,	}, /* C DOWN */</div><div class='add'>+	{ BTN_LEFT,		JC_BTN_X,	}, /* C LEFT */</div><div class='add'>+	{ BTN_RIGHT,		JC_BTN_MINUS,	}, /* C RIGHT */</div><div class='add'>+	{ BTN_MODE,		JC_BTN_HOME,	},</div><div class='add'>+	{ BTN_Z,		JC_BTN_CAP,	},</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> enum joycon_msg_type {</div><div class='ctx'> 	JOYCON_MSG_TYPE_NONE,</div><div class='hunk'>@@ -506,13 +648,182 @@ struct joycon_ctlr {</div><div class='ctx'> /* Does this controller have inputs associated with left joycon? */</div><div class='ctx'> #define jc_type_has_left(ctlr) \</div><div class='ctx'> 	(ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_JCL || \</div><div class='del'>-	 ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_PRO)</div><div class='add'>+	 ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_PRO || \</div><div class='add'>+	 ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_N64)</div><div class='ctx'> </div><div class='ctx'> /* Does this controller have inputs associated with right joycon? */</div><div class='ctx'> #define jc_type_has_right(ctlr) \</div><div class='ctx'> 	(ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_JCR || \</div><div class='ctx'> 	 ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_PRO)</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Controller device helpers</div><div class='add'>+ *</div><div class='add'>+ * These look at the device ID known to the HID subsystem to identify a device,</div><div class='add'>+ * but take caution: some NSO devices lie about themselves (NES Joy-Cons and</div><div class='add'>+ * Sega Genesis controller). See type helpers below.</div><div class='add'>+ *</div><div class='add'>+ * These helpers are most useful early during the HID probe or in conjunction</div><div class='add'>+ * with the capability helpers below.</div><div class='add'>+ */</div><div class='add'>+static inline bool joycon_device_is_left_joycon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_JOYCONL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_right_joycon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_JOYCONR;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_procon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_PROCON;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_chrggrip(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_CHRGGRIP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_snescon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_SNESCON;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_gencon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_GENCON;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_is_n64con(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;product == USB_DEVICE_ID_NINTENDO_N64CON;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_device_has_usb(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_device_is_procon(ctlr) ||</div><div class='add'>+	       joycon_device_is_chrggrip(ctlr) ||</div><div class='add'>+	       joycon_device_is_snescon(ctlr) ||</div><div class='add'>+	       joycon_device_is_gencon(ctlr) ||</div><div class='add'>+	       joycon_device_is_n64con(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Controller type helpers</div><div class='add'>+ *</div><div class='add'>+ * These are slightly different than the device-ID-based helpers above. They are</div><div class='add'>+ * generally more reliable, since they can distinguish between, e.g., Genesis</div><div class='add'>+ * versus SNES, or NES Joy-Cons versus regular Switch Joy-Cons. They're most</div><div class='add'>+ * useful for reporting available inputs. For other kinds of distinctions, see</div><div class='add'>+ * the capability helpers below.</div><div class='add'>+ *</div><div class='add'>+ * They have two major drawbacks: (1) they're not available until after we set</div><div class='add'>+ * the reporting method and then request the device info; (2) they can't</div><div class='add'>+ * distinguish all controllers (like the Charging Grip from the Pro controller.)</div><div class='add'>+ */</div><div class='add'>+static inline bool joycon_type_is_left_joycon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_JCL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_right_joycon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_JCR;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_procon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_PRO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_snescon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_SNES;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_gencon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_GEN;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_n64con(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_N64;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_left_nescon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_NESL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_right_nescon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;ctlr_type == JOYCON_CTLR_TYPE_NESR;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_has_left_controls(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_type_is_left_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_procon(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_has_right_controls(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_type_is_right_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_procon(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_any_joycon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_type_is_left_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_right_joycon(ctlr) ||</div><div class='add'>+	       joycon_device_is_chrggrip(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_type_is_any_nescon(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_type_is_left_nescon(ctlr) ||</div><div class='add'>+	       joycon_type_is_right_nescon(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Controller capability helpers</div><div class='add'>+ *</div><div class='add'>+ * These helpers combine the use of the helpers above to detect certain</div><div class='add'>+ * capabilities during initialization. They are always accurate but (since they</div><div class='add'>+ * use type helpers) cannot be used early in the HID probe.</div><div class='add'>+ */</div><div class='add'>+static inline bool joycon_has_imu(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_device_is_chrggrip(ctlr) ||</div><div class='add'>+	       joycon_type_is_any_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_procon(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_has_joysticks(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_device_is_chrggrip(ctlr) ||</div><div class='add'>+	       joycon_type_is_any_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_procon(ctlr) ||</div><div class='add'>+	       joycon_type_is_n64con(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_has_rumble(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return joycon_device_is_chrggrip(ctlr) ||</div><div class='add'>+	       joycon_type_is_any_joycon(ctlr) ||</div><div class='add'>+	       joycon_type_is_procon(ctlr) ||</div><div class='add'>+	       joycon_type_is_n64con(ctlr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool joycon_using_usb(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	return ctlr-&gt;hdev-&gt;bus == BUS_USB;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int __joycon_hid_send(struct hid_device *hdev, u8 *data, size_t len)</div><div class='ctx'> {</div><div class='ctx'> 	u8 *buf;</div><div class='hunk'>@@ -927,14 +1238,27 @@ static int joycon_request_calibration(struct joycon_ctlr *ctlr)</div><div class='ctx'>  */</div><div class='ctx'> static void joycon_calc_imu_cal_divisors(struct joycon_ctlr *ctlr)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	int i, divz = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; 3; i++) {</div><div class='ctx'> 		ctlr-&gt;imu_cal_accel_divisor[i] = ctlr-&gt;accel_cal.scale[i] -</div><div class='ctx'> 						ctlr-&gt;accel_cal.offset[i];</div><div class='ctx'> 		ctlr-&gt;imu_cal_gyro_divisor[i] = ctlr-&gt;gyro_cal.scale[i] -</div><div class='ctx'> 						ctlr-&gt;gyro_cal.offset[i];</div><div class='add'>+</div><div class='add'>+		if (ctlr-&gt;imu_cal_accel_divisor[i] == 0) {</div><div class='add'>+			ctlr-&gt;imu_cal_accel_divisor[i] = 1;</div><div class='add'>+			divz++;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ctlr-&gt;imu_cal_gyro_divisor[i] == 0) {</div><div class='add'>+			ctlr-&gt;imu_cal_gyro_divisor[i] = 1;</div><div class='add'>+			divz++;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (divz)</div><div class='add'>+		hid_warn(ctlr-&gt;hdev, "inaccurate IMU divisors (%d)\n", divz);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const s16 DFLT_ACCEL_OFFSET /*= 0*/;</div><div class='hunk'>@@ -1163,16 +1487,16 @@ static void joycon_parse_imu_report(struct joycon_ctlr *ctlr,</div><div class='ctx'> 		    JC_IMU_SAMPLES_PER_DELTA_AVG) {</div><div class='ctx'> 			ctlr-&gt;imu_avg_delta_ms = ctlr-&gt;imu_delta_samples_sum /</div><div class='ctx'> 						 ctlr-&gt;imu_delta_samples_count;</div><div class='del'>-			/* don't ever want divide by zero shenanigans */</div><div class='del'>-			if (ctlr-&gt;imu_avg_delta_ms == 0) {</div><div class='del'>-				ctlr-&gt;imu_avg_delta_ms = 1;</div><div class='del'>-				hid_warn(ctlr-&gt;hdev,</div><div class='del'>-					 "calculated avg imu delta of 0\n");</div><div class='del'>-			}</div><div class='ctx'> 			ctlr-&gt;imu_delta_samples_count = 0;</div><div class='ctx'> 			ctlr-&gt;imu_delta_samples_sum = 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/* don't ever want divide by zero shenanigans */</div><div class='add'>+		if (ctlr-&gt;imu_avg_delta_ms == 0) {</div><div class='add'>+			ctlr-&gt;imu_avg_delta_ms = 1;</div><div class='add'>+			hid_warn(ctlr-&gt;hdev, "calculated avg imu delta of 0\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		/* useful for debugging IMU sample rate */</div><div class='ctx'> 		hid_dbg(ctlr-&gt;hdev,</div><div class='ctx'> 			"imu_report: ms=%u last_ms=%u delta=%u avg_delta=%u\n",</div><div class='hunk'>@@ -1283,15 +1607,10 @@ static void joycon_parse_imu_report(struct joycon_ctlr *ctlr,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void joycon_parse_report(struct joycon_ctlr *ctlr,</div><div class='del'>-				struct joycon_input_report *rep)</div><div class='add'>+static void joycon_handle_rumble_report(struct joycon_ctlr *ctlr, struct joycon_input_report *rep)</div><div class='ctx'> {</div><div class='del'>-	struct input_dev *dev = ctlr-&gt;input;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	u8 tmp;</div><div class='del'>-	u32 btns;</div><div class='ctx'> 	unsigned long msecs = jiffies_to_msecs(jiffies);</div><div class='del'>-	unsigned long report_delta_ms = msecs - ctlr-&gt;last_input_report_msecs;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;ctlr-&gt;lock, flags);</div><div class='ctx'> 	if (IS_ENABLED(CONFIG_NINTENDO_FF) &amp;&amp; rep-&gt;vibrator_report &amp;&amp;</div><div class='hunk'>@@ -1310,11 +1629,21 @@ static void joycon_parse_report(struct joycon_ctlr *ctlr,</div><div class='ctx'> 		queue_work(ctlr-&gt;rumble_queue, &amp;ctlr-&gt;rumble_worker);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Parse the battery status */</div><div class='add'>+	spin_unlock_irqrestore(&amp;ctlr-&gt;lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void joycon_parse_battery_status(struct joycon_ctlr *ctlr, struct joycon_input_report *rep)</div><div class='add'>+{</div><div class='add'>+	u8 tmp;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;ctlr-&gt;lock, flags);</div><div class='add'>+</div><div class='ctx'> 	tmp = rep-&gt;bat_con;</div><div class='ctx'> 	ctlr-&gt;host_powered = tmp &amp; BIT(0);</div><div class='ctx'> 	ctlr-&gt;battery_charging = tmp &amp; BIT(4);</div><div class='ctx'> 	tmp = tmp &gt;&gt; 5;</div><div class='add'>+</div><div class='ctx'> 	switch (tmp) {</div><div class='ctx'> 	case 0: /* empty */</div><div class='ctx'> 		ctlr-&gt;battery_capacity = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL;</div><div class='hunk'>@@ -1336,102 +1665,121 @@ static void joycon_parse_report(struct joycon_ctlr *ctlr,</div><div class='ctx'> 		hid_warn(ctlr-&gt;hdev, "Invalid battery status\n");</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;ctlr-&gt;lock, flags);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/* Parse the buttons and sticks */</div><div class='del'>-	btns = hid_field_extract(ctlr-&gt;hdev, rep-&gt;button_status, 0, 24);</div><div class='del'>-</div><div class='del'>-	if (jc_type_has_left(ctlr)) {</div><div class='del'>-		u16 raw_x;</div><div class='del'>-		u16 raw_y;</div><div class='del'>-		s32 x;</div><div class='del'>-		s32 y;</div><div class='del'>-</div><div class='del'>-		/* get raw stick values */</div><div class='del'>-		raw_x = hid_field_extract(ctlr-&gt;hdev, rep-&gt;left_stick, 0, 12);</div><div class='del'>-		raw_y = hid_field_extract(ctlr-&gt;hdev,</div><div class='del'>-					  rep-&gt;left_stick + 1, 4, 12);</div><div class='del'>-		/* map the stick values */</div><div class='del'>-		x = joycon_map_stick_val(&amp;ctlr-&gt;left_stick_cal_x, raw_x);</div><div class='del'>-		y = -joycon_map_stick_val(&amp;ctlr-&gt;left_stick_cal_y, raw_y);</div><div class='del'>-		/* report sticks */</div><div class='del'>-		input_report_abs(dev, ABS_X, x);</div><div class='del'>-		input_report_abs(dev, ABS_Y, y);</div><div class='del'>-</div><div class='del'>-		/* report buttons */</div><div class='del'>-		input_report_key(dev, BTN_TL, btns &amp; JC_BTN_L);</div><div class='del'>-		input_report_key(dev, BTN_TL2, btns &amp; JC_BTN_ZL);</div><div class='del'>-		input_report_key(dev, BTN_SELECT, btns &amp; JC_BTN_MINUS);</div><div class='del'>-		input_report_key(dev, BTN_THUMBL, btns &amp; JC_BTN_LSTICK);</div><div class='del'>-		input_report_key(dev, BTN_Z, btns &amp; JC_BTN_CAP);</div><div class='del'>-</div><div class='del'>-		if (jc_type_is_joycon(ctlr)) {</div><div class='del'>-			/* Report the S buttons as the non-existent triggers */</div><div class='del'>-			input_report_key(dev, BTN_TR, btns &amp; JC_BTN_SL_L);</div><div class='del'>-			input_report_key(dev, BTN_TR2, btns &amp; JC_BTN_SR_L);</div><div class='del'>-</div><div class='del'>-			/* Report d-pad as digital buttons for the joy-cons */</div><div class='del'>-			input_report_key(dev, BTN_DPAD_DOWN,</div><div class='del'>-					 btns &amp; JC_BTN_DOWN);</div><div class='del'>-			input_report_key(dev, BTN_DPAD_UP, btns &amp; JC_BTN_UP);</div><div class='del'>-			input_report_key(dev, BTN_DPAD_RIGHT,</div><div class='del'>-					 btns &amp; JC_BTN_RIGHT);</div><div class='del'>-			input_report_key(dev, BTN_DPAD_LEFT,</div><div class='del'>-					 btns &amp; JC_BTN_LEFT);</div><div class='del'>-		} else {</div><div class='del'>-			int hatx = 0;</div><div class='del'>-			int haty = 0;</div><div class='del'>-</div><div class='del'>-			/* d-pad x */</div><div class='del'>-			if (btns &amp; JC_BTN_LEFT)</div><div class='del'>-				hatx = -1;</div><div class='del'>-			else if (btns &amp; JC_BTN_RIGHT)</div><div class='del'>-				hatx = 1;</div><div class='del'>-			input_report_abs(dev, ABS_HAT0X, hatx);</div><div class='del'>-</div><div class='del'>-			/* d-pad y */</div><div class='del'>-			if (btns &amp; JC_BTN_UP)</div><div class='del'>-				haty = -1;</div><div class='del'>-			else if (btns &amp; JC_BTN_DOWN)</div><div class='del'>-				haty = 1;</div><div class='del'>-			input_report_abs(dev, ABS_HAT0Y, haty);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if (jc_type_has_right(ctlr)) {</div><div class='del'>-		u16 raw_x;</div><div class='del'>-		u16 raw_y;</div><div class='del'>-		s32 x;</div><div class='del'>-		s32 y;</div><div class='del'>-</div><div class='del'>-		/* get raw stick values */</div><div class='del'>-		raw_x = hid_field_extract(ctlr-&gt;hdev, rep-&gt;right_stick, 0, 12);</div><div class='del'>-		raw_y = hid_field_extract(ctlr-&gt;hdev,</div><div class='del'>-					  rep-&gt;right_stick + 1, 4, 12);</div><div class='del'>-		/* map stick values */</div><div class='del'>-		x = joycon_map_stick_val(&amp;ctlr-&gt;right_stick_cal_x, raw_x);</div><div class='del'>-		y = -joycon_map_stick_val(&amp;ctlr-&gt;right_stick_cal_y, raw_y);</div><div class='del'>-		/* report sticks */</div><div class='del'>-		input_report_abs(dev, ABS_RX, x);</div><div class='del'>-		input_report_abs(dev, ABS_RY, y);</div><div class='del'>-</div><div class='del'>-		/* report buttons */</div><div class='del'>-		input_report_key(dev, BTN_TR, btns &amp; JC_BTN_R);</div><div class='del'>-		input_report_key(dev, BTN_TR2, btns &amp; JC_BTN_ZR);</div><div class='del'>-		if (jc_type_is_joycon(ctlr)) {</div><div class='del'>-			/* Report the S buttons as the non-existent triggers */</div><div class='del'>-			input_report_key(dev, BTN_TL, btns &amp; JC_BTN_SL_R);</div><div class='del'>-			input_report_key(dev, BTN_TL2, btns &amp; JC_BTN_SR_R);</div><div class='del'>-		}</div><div class='del'>-		input_report_key(dev, BTN_START, btns &amp; JC_BTN_PLUS);</div><div class='del'>-		input_report_key(dev, BTN_THUMBR, btns &amp; JC_BTN_RSTICK);</div><div class='del'>-		input_report_key(dev, BTN_MODE, btns &amp; JC_BTN_HOME);</div><div class='del'>-		input_report_key(dev, BTN_WEST, btns &amp; JC_BTN_Y);</div><div class='del'>-		input_report_key(dev, BTN_NORTH, btns &amp; JC_BTN_X);</div><div class='del'>-		input_report_key(dev, BTN_EAST, btns &amp; JC_BTN_A);</div><div class='del'>-		input_report_key(dev, BTN_SOUTH, btns &amp; JC_BTN_B);</div><div class='add'>+static void joycon_report_left_stick(struct joycon_ctlr *ctlr,</div><div class='add'>+				     struct joycon_input_report *rep)</div><div class='add'>+{</div><div class='add'>+	u16 raw_x;</div><div class='add'>+	u16 raw_y;</div><div class='add'>+	s32 x;</div><div class='add'>+	s32 y;</div><div class='add'>+</div><div class='add'>+	raw_x = hid_field_extract(ctlr-&gt;hdev, rep-&gt;left_stick, 0, 12);</div><div class='add'>+	raw_y = hid_field_extract(ctlr-&gt;hdev, rep-&gt;left_stick + 1, 4, 12);</div><div class='add'>+</div><div class='add'>+	x = joycon_map_stick_val(&amp;ctlr-&gt;left_stick_cal_x, raw_x);</div><div class='add'>+	y = -joycon_map_stick_val(&amp;ctlr-&gt;left_stick_cal_y, raw_y);</div><div class='add'>+</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_X, x);</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_Y, y);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void joycon_report_right_stick(struct joycon_ctlr *ctlr,</div><div class='add'>+				      struct joycon_input_report *rep)</div><div class='add'>+{</div><div class='add'>+	u16 raw_x;</div><div class='add'>+	u16 raw_y;</div><div class='add'>+	s32 x;</div><div class='add'>+	s32 y;</div><div class='add'>+</div><div class='add'>+	raw_x = hid_field_extract(ctlr-&gt;hdev, rep-&gt;right_stick, 0, 12);</div><div class='add'>+	raw_y = hid_field_extract(ctlr-&gt;hdev, rep-&gt;right_stick + 1, 4, 12);</div><div class='add'>+</div><div class='add'>+	x = joycon_map_stick_val(&amp;ctlr-&gt;right_stick_cal_x, raw_x);</div><div class='add'>+	y = -joycon_map_stick_val(&amp;ctlr-&gt;right_stick_cal_y, raw_y);</div><div class='add'>+</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_RX, x);</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_RY, y);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void joycon_report_dpad(struct joycon_ctlr *ctlr,</div><div class='add'>+			       struct joycon_input_report *rep)</div><div class='add'>+{</div><div class='add'>+	int hatx = 0;</div><div class='add'>+	int haty = 0;</div><div class='add'>+	u32 btns = hid_field_extract(ctlr-&gt;hdev, rep-&gt;button_status, 0, 24);</div><div class='add'>+</div><div class='add'>+	if (btns &amp; JC_BTN_LEFT)</div><div class='add'>+		hatx = -1;</div><div class='add'>+	else if (btns &amp; JC_BTN_RIGHT)</div><div class='add'>+		hatx = 1;</div><div class='add'>+</div><div class='add'>+	if (btns &amp; JC_BTN_UP)</div><div class='add'>+		haty = -1;</div><div class='add'>+	else if (btns &amp; JC_BTN_DOWN)</div><div class='add'>+		haty = 1;</div><div class='add'>+</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_HAT0X, hatx);</div><div class='add'>+	input_report_abs(ctlr-&gt;input, ABS_HAT0Y, haty);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void joycon_report_buttons(struct joycon_ctlr *ctlr,</div><div class='add'>+				  struct joycon_input_report *rep,</div><div class='add'>+				  const struct joycon_ctlr_button_mapping button_mappings[])</div><div class='add'>+{</div><div class='add'>+	const struct joycon_ctlr_button_mapping *button;</div><div class='add'>+	u32 status = hid_field_extract(ctlr-&gt;hdev, rep-&gt;button_status, 0, 24);</div><div class='add'>+</div><div class='add'>+	for (button = button_mappings; button-&gt;code; button++)</div><div class='add'>+		input_report_key(ctlr-&gt;input, button-&gt;code, status &amp; button-&gt;bit);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void joycon_parse_report(struct joycon_ctlr *ctlr,</div><div class='add'>+				struct joycon_input_report *rep)</div><div class='add'>+{</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	unsigned long msecs = jiffies_to_msecs(jiffies);</div><div class='add'>+	unsigned long report_delta_ms = msecs - ctlr-&gt;last_input_report_msecs;</div><div class='add'>+</div><div class='add'>+	if (joycon_has_rumble(ctlr))</div><div class='add'>+		joycon_handle_rumble_report(ctlr, rep);</div><div class='add'>+</div><div class='add'>+	joycon_parse_battery_status(ctlr, rep);</div><div class='add'>+</div><div class='add'>+	if (joycon_type_is_left_joycon(ctlr)) {</div><div class='add'>+		joycon_report_left_stick(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, left_joycon_button_mappings);</div><div class='add'>+		if (!joycon_device_is_chrggrip(ctlr))</div><div class='add'>+			joycon_report_buttons(ctlr, rep, left_joycon_s_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_right_joycon(ctlr)) {</div><div class='add'>+		joycon_report_right_stick(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, right_joycon_button_mappings);</div><div class='add'>+		if (!joycon_device_is_chrggrip(ctlr))</div><div class='add'>+			joycon_report_buttons(ctlr, rep, right_joycon_s_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_procon(ctlr)) {</div><div class='add'>+		joycon_report_left_stick(ctlr, rep);</div><div class='add'>+		joycon_report_right_stick(ctlr, rep);</div><div class='add'>+		joycon_report_dpad(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, procon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_any_nescon(ctlr)) {</div><div class='add'>+		joycon_report_dpad(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, nescon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_snescon(ctlr)) {</div><div class='add'>+		joycon_report_dpad(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, snescon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_gencon(ctlr)) {</div><div class='add'>+		joycon_report_dpad(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, gencon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_n64con(ctlr)) {</div><div class='add'>+		joycon_report_left_stick(ctlr, rep);</div><div class='add'>+		joycon_report_dpad(ctlr, rep);</div><div class='add'>+		joycon_report_buttons(ctlr, rep, n64con_button_mappings);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	input_sync(dev);</div><div class='add'>+	input_sync(ctlr-&gt;input);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;ctlr-&gt;lock, flags);</div><div class='ctx'> 	ctlr-&gt;last_input_report_msecs = msecs;</div><div class='hunk'>@@ -1471,7 +1819,7 @@ static void joycon_parse_report(struct joycon_ctlr *ctlr,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* parse IMU data if present */</div><div class='del'>-	if (rep-&gt;id == JC_INPUT_IMU_DATA)</div><div class='add'>+	if ((rep-&gt;id == JC_INPUT_IMU_DATA) &amp;&amp; joycon_has_imu(ctlr))</div><div class='ctx'> 		joycon_parse_imu_report(ctlr, rep);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1684,123 +2032,65 @@ static int joycon_play_effect(struct input_dev *dev, void *data,</div><div class='ctx'> }</div><div class='ctx'> #endif /* IS_ENABLED(CONFIG_NINTENDO_FF) */</div><div class='ctx'> </div><div class='del'>-static const unsigned int joycon_button_inputs_l[] = {</div><div class='del'>-	BTN_SELECT, BTN_Z, BTN_THUMBL,</div><div class='del'>-	BTN_TL, BTN_TL2,</div><div class='del'>-	0 /* 0 signals end of array */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const unsigned int joycon_button_inputs_r[] = {</div><div class='del'>-	BTN_START, BTN_MODE, BTN_THUMBR,</div><div class='del'>-	BTN_SOUTH, BTN_EAST, BTN_NORTH, BTN_WEST,</div><div class='del'>-	BTN_TR, BTN_TR2,</div><div class='del'>-	0 /* 0 signals end of array */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* We report joy-con d-pad inputs as buttons and pro controller as a hat. */</div><div class='del'>-static const unsigned int joycon_dpad_inputs_jc[] = {</div><div class='del'>-	BTN_DPAD_UP, BTN_DPAD_DOWN, BTN_DPAD_LEFT, BTN_DPAD_RIGHT,</div><div class='del'>-	0 /* 0 signals end of array */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int joycon_input_create(struct joycon_ctlr *ctlr)</div><div class='add'>+static void joycon_config_left_stick(struct input_dev *idev)</div><div class='ctx'> {</div><div class='del'>-	struct hid_device *hdev;</div><div class='del'>-	const char *name;</div><div class='del'>-	const char *imu_name;</div><div class='del'>-	int ret;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	hdev = ctlr-&gt;hdev;</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_X,</div><div class='add'>+			     -JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_STICK_FUZZ,</div><div class='add'>+			     JC_STICK_FLAT);</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_Y,</div><div class='add'>+			     -JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_STICK_FUZZ,</div><div class='add'>+			     JC_STICK_FLAT);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	switch (hdev-&gt;product) {</div><div class='del'>-	case USB_DEVICE_ID_NINTENDO_PROCON:</div><div class='del'>-		name = "Nintendo Switch Pro Controller";</div><div class='del'>-		imu_name = "Nintendo Switch Pro Controller IMU";</div><div class='del'>-		break;</div><div class='del'>-	case USB_DEVICE_ID_NINTENDO_CHRGGRIP:</div><div class='del'>-		if (jc_type_has_left(ctlr)) {</div><div class='del'>-			name = "Nintendo Switch Left Joy-Con (Grip)";</div><div class='del'>-			imu_name = "Nintendo Switch Left Joy-Con IMU (Grip)";</div><div class='del'>-		} else {</div><div class='del'>-			name = "Nintendo Switch Right Joy-Con (Grip)";</div><div class='del'>-			imu_name = "Nintendo Switch Right Joy-Con IMU (Grip)";</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case USB_DEVICE_ID_NINTENDO_JOYCONL:</div><div class='del'>-		name = "Nintendo Switch Left Joy-Con";</div><div class='del'>-		imu_name = "Nintendo Switch Left Joy-Con IMU";</div><div class='del'>-		break;</div><div class='del'>-	case USB_DEVICE_ID_NINTENDO_JOYCONR:</div><div class='del'>-		name = "Nintendo Switch Right Joy-Con";</div><div class='del'>-		imu_name = "Nintendo Switch Right Joy-Con IMU";</div><div class='del'>-		break;</div><div class='del'>-	default: /* Should be impossible */</div><div class='del'>-		hid_err(hdev, "Invalid hid product\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='add'>+static void joycon_config_right_stick(struct input_dev *idev)</div><div class='add'>+{</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_RX,</div><div class='add'>+			     -JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_STICK_FUZZ,</div><div class='add'>+			     JC_STICK_FLAT);</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_RY,</div><div class='add'>+			     -JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_MAX_STICK_MAG,</div><div class='add'>+			     JC_STICK_FUZZ,</div><div class='add'>+			     JC_STICK_FLAT);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	ctlr-&gt;input = devm_input_allocate_device(&amp;hdev-&gt;dev);</div><div class='del'>-	if (!ctlr-&gt;input)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	ctlr-&gt;input-&gt;id.bustype = hdev-&gt;bus;</div><div class='del'>-	ctlr-&gt;input-&gt;id.vendor = hdev-&gt;vendor;</div><div class='del'>-	ctlr-&gt;input-&gt;id.product = hdev-&gt;product;</div><div class='del'>-	ctlr-&gt;input-&gt;id.version = hdev-&gt;version;</div><div class='del'>-	ctlr-&gt;input-&gt;uniq = ctlr-&gt;mac_addr_str;</div><div class='del'>-	ctlr-&gt;input-&gt;name = name;</div><div class='del'>-	ctlr-&gt;input-&gt;phys = hdev-&gt;phys;</div><div class='del'>-	input_set_drvdata(ctlr-&gt;input, ctlr);</div><div class='add'>+static void joycon_config_dpad(struct input_dev *idev)</div><div class='add'>+{</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_HAT0X,</div><div class='add'>+			     -JC_MAX_DPAD_MAG,</div><div class='add'>+			     JC_MAX_DPAD_MAG,</div><div class='add'>+			     JC_DPAD_FUZZ,</div><div class='add'>+			     JC_DPAD_FLAT);</div><div class='add'>+	input_set_abs_params(idev,</div><div class='add'>+			     ABS_HAT0Y,</div><div class='add'>+			     -JC_MAX_DPAD_MAG,</div><div class='add'>+			     JC_MAX_DPAD_MAG,</div><div class='add'>+			     JC_DPAD_FUZZ,</div><div class='add'>+			     JC_DPAD_FLAT);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	/* set up sticks and buttons */</div><div class='del'>-	if (jc_type_has_left(ctlr)) {</div><div class='del'>-		input_set_abs_params(ctlr-&gt;input, ABS_X,</div><div class='del'>-				     -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,</div><div class='del'>-				     JC_STICK_FUZZ, JC_STICK_FLAT);</div><div class='del'>-		input_set_abs_params(ctlr-&gt;input, ABS_Y,</div><div class='del'>-				     -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,</div><div class='del'>-				     JC_STICK_FUZZ, JC_STICK_FLAT);</div><div class='del'>-</div><div class='del'>-		for (i = 0; joycon_button_inputs_l[i] &gt; 0; i++)</div><div class='del'>-			input_set_capability(ctlr-&gt;input, EV_KEY,</div><div class='del'>-					     joycon_button_inputs_l[i]);</div><div class='del'>-</div><div class='del'>-		/* configure d-pad differently for joy-con vs pro controller */</div><div class='del'>-		if (hdev-&gt;product != USB_DEVICE_ID_NINTENDO_PROCON) {</div><div class='del'>-			for (i = 0; joycon_dpad_inputs_jc[i] &gt; 0; i++)</div><div class='del'>-				input_set_capability(ctlr-&gt;input, EV_KEY,</div><div class='del'>-						     joycon_dpad_inputs_jc[i]);</div><div class='del'>-		} else {</div><div class='del'>-			input_set_abs_params(ctlr-&gt;input, ABS_HAT0X,</div><div class='del'>-					     -JC_MAX_DPAD_MAG, JC_MAX_DPAD_MAG,</div><div class='del'>-					     JC_DPAD_FUZZ, JC_DPAD_FLAT);</div><div class='del'>-			input_set_abs_params(ctlr-&gt;input, ABS_HAT0Y,</div><div class='del'>-					     -JC_MAX_DPAD_MAG, JC_MAX_DPAD_MAG,</div><div class='del'>-					     JC_DPAD_FUZZ, JC_DPAD_FLAT);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if (jc_type_has_right(ctlr)) {</div><div class='del'>-		input_set_abs_params(ctlr-&gt;input, ABS_RX,</div><div class='del'>-				     -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,</div><div class='del'>-				     JC_STICK_FUZZ, JC_STICK_FLAT);</div><div class='del'>-		input_set_abs_params(ctlr-&gt;input, ABS_RY,</div><div class='del'>-				     -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,</div><div class='del'>-				     JC_STICK_FUZZ, JC_STICK_FLAT);</div><div class='del'>-</div><div class='del'>-		for (i = 0; joycon_button_inputs_r[i] &gt; 0; i++)</div><div class='del'>-			input_set_capability(ctlr-&gt;input, EV_KEY,</div><div class='del'>-					     joycon_button_inputs_r[i]);</div><div class='del'>-	}</div><div class='add'>+static void joycon_config_buttons(struct input_dev *idev,</div><div class='add'>+		 const struct joycon_ctlr_button_mapping button_mappings[])</div><div class='add'>+{</div><div class='add'>+	const struct joycon_ctlr_button_mapping *button;</div><div class='ctx'> </div><div class='del'>-	/* Let's report joy-con S triggers separately */</div><div class='del'>-	if (hdev-&gt;product == USB_DEVICE_ID_NINTENDO_JOYCONL) {</div><div class='del'>-		input_set_capability(ctlr-&gt;input, EV_KEY, BTN_TR);</div><div class='del'>-		input_set_capability(ctlr-&gt;input, EV_KEY, BTN_TR2);</div><div class='del'>-	} else if (hdev-&gt;product == USB_DEVICE_ID_NINTENDO_JOYCONR) {</div><div class='del'>-		input_set_capability(ctlr-&gt;input, EV_KEY, BTN_TL);</div><div class='del'>-		input_set_capability(ctlr-&gt;input, EV_KEY, BTN_TL2);</div><div class='del'>-	}</div><div class='add'>+	for (button = button_mappings; button-&gt;code; button++)</div><div class='add'>+		input_set_capability(idev, EV_KEY, button-&gt;code);</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+static void joycon_config_rumble(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='ctx'> #if IS_ENABLED(CONFIG_NINTENDO_FF)</div><div class='ctx'> 	/* set up rumble */</div><div class='ctx'> 	input_set_capability(ctlr-&gt;input, EV_FF, FF_RUMBLE);</div><div class='hunk'>@@ -1813,10 +2103,15 @@ static int joycon_input_create(struct joycon_ctlr *ctlr)</div><div class='ctx'> 	joycon_set_rumble(ctlr, 0, 0, false);</div><div class='ctx'> 	ctlr-&gt;rumble_msecs = jiffies_to_msecs(jiffies);</div><div class='ctx'> #endif</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	ret = input_register_device(ctlr-&gt;input);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+static int joycon_imu_input_create(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	struct hid_device *hdev;</div><div class='add'>+	const char *imu_name;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	hdev = ctlr-&gt;hdev;</div><div class='ctx'> </div><div class='ctx'> 	/* configure the imu input device */</div><div class='ctx'> 	ctlr-&gt;imu_input = devm_input_allocate_device(&amp;hdev-&gt;dev);</div><div class='hunk'>@@ -1828,8 +2123,14 @@ static int joycon_input_create(struct joycon_ctlr *ctlr)</div><div class='ctx'> 	ctlr-&gt;imu_input-&gt;id.product = hdev-&gt;product;</div><div class='ctx'> 	ctlr-&gt;imu_input-&gt;id.version = hdev-&gt;version;</div><div class='ctx'> 	ctlr-&gt;imu_input-&gt;uniq = ctlr-&gt;mac_addr_str;</div><div class='del'>-	ctlr-&gt;imu_input-&gt;name = imu_name;</div><div class='ctx'> 	ctlr-&gt;imu_input-&gt;phys = hdev-&gt;phys;</div><div class='add'>+</div><div class='add'>+	imu_name = devm_kasprintf(&amp;hdev-&gt;dev, GFP_KERNEL, "%s (IMU)", ctlr-&gt;input-&gt;name);</div><div class='add'>+	if (!imu_name)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ctlr-&gt;imu_input-&gt;name = imu_name;</div><div class='add'>+</div><div class='ctx'> 	input_set_drvdata(ctlr-&gt;imu_input, ctlr);</div><div class='ctx'> </div><div class='ctx'> 	/* configure imu axes */</div><div class='hunk'>@@ -1871,6 +2172,71 @@ static int joycon_input_create(struct joycon_ctlr *ctlr)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int joycon_input_create(struct joycon_ctlr *ctlr)</div><div class='add'>+{</div><div class='add'>+	struct hid_device *hdev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	hdev = ctlr-&gt;hdev;</div><div class='add'>+</div><div class='add'>+	ctlr-&gt;input = devm_input_allocate_device(&amp;hdev-&gt;dev);</div><div class='add'>+	if (!ctlr-&gt;input)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	ctlr-&gt;input-&gt;id.bustype = hdev-&gt;bus;</div><div class='add'>+	ctlr-&gt;input-&gt;id.vendor = hdev-&gt;vendor;</div><div class='add'>+	ctlr-&gt;input-&gt;id.product = hdev-&gt;product;</div><div class='add'>+	ctlr-&gt;input-&gt;id.version = hdev-&gt;version;</div><div class='add'>+	ctlr-&gt;input-&gt;uniq = ctlr-&gt;mac_addr_str;</div><div class='add'>+	ctlr-&gt;input-&gt;name = hdev-&gt;name;</div><div class='add'>+	ctlr-&gt;input-&gt;phys = hdev-&gt;phys;</div><div class='add'>+	input_set_drvdata(ctlr-&gt;input, ctlr);</div><div class='add'>+</div><div class='add'>+	ret = input_register_device(ctlr-&gt;input);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (joycon_type_is_right_joycon(ctlr)) {</div><div class='add'>+		joycon_config_right_stick(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, right_joycon_button_mappings);</div><div class='add'>+		if (!joycon_device_is_chrggrip(ctlr))</div><div class='add'>+			joycon_config_buttons(ctlr-&gt;input, right_joycon_s_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_left_joycon(ctlr)) {</div><div class='add'>+		joycon_config_left_stick(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, left_joycon_button_mappings);</div><div class='add'>+		if (!joycon_device_is_chrggrip(ctlr))</div><div class='add'>+			joycon_config_buttons(ctlr-&gt;input, left_joycon_s_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_procon(ctlr)) {</div><div class='add'>+		joycon_config_left_stick(ctlr-&gt;input);</div><div class='add'>+		joycon_config_right_stick(ctlr-&gt;input);</div><div class='add'>+		joycon_config_dpad(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, procon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_any_nescon(ctlr)) {</div><div class='add'>+		joycon_config_dpad(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, nescon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_snescon(ctlr)) {</div><div class='add'>+		joycon_config_dpad(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, snescon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_gencon(ctlr)) {</div><div class='add'>+		joycon_config_dpad(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, gencon_button_mappings);</div><div class='add'>+	} else if (joycon_type_is_n64con(ctlr)) {</div><div class='add'>+		joycon_config_dpad(ctlr-&gt;input);</div><div class='add'>+		joycon_config_left_stick(ctlr-&gt;input);</div><div class='add'>+		joycon_config_buttons(ctlr-&gt;input, n64con_button_mappings);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (joycon_has_imu(ctlr)) {</div><div class='add'>+		ret = joycon_imu_input_create(ctlr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (joycon_has_rumble(ctlr))</div><div class='add'>+		joycon_config_rumble(ctlr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Because the subcommand sets all the leds at once, the brightness argument is ignored */</div><div class='ctx'> static int joycon_player_led_brightness_set(struct led_classdev *led,</div><div class='ctx'> 					    enum led_brightness brightness)</div><div class='hunk'>@@ -2107,9 +2473,7 @@ static int joycon_read_info(struct joycon_ctlr *ctlr)</div><div class='ctx'> 	struct joycon_input_report *report;</div><div class='ctx'> </div><div class='ctx'> 	req.subcmd_id = JC_SUBCMD_REQ_DEV_INFO;</div><div class='del'>-	mutex_lock(&amp;ctlr-&gt;output_mutex);</div><div class='ctx'> 	ret = joycon_send_subcmd(ctlr, &amp;req, 0, HZ);</div><div class='del'>-	mutex_unlock(&amp;ctlr-&gt;output_mutex);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		hid_err(ctlr-&gt;hdev, "Failed to get joycon info; ret=%d\n", ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -2132,8 +2496,17 @@ static int joycon_read_info(struct joycon_ctlr *ctlr)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	hid_info(ctlr-&gt;hdev, "controller MAC = %s\n", ctlr-&gt;mac_addr_str);</div><div class='ctx'> </div><div class='del'>-	/* Retrieve the type so we can distinguish for charging grip */</div><div class='add'>+	/*</div><div class='add'>+	 * Retrieve the type so we can distinguish the controller type</div><div class='add'>+	 * Unfortantly the hdev-&gt;product can't always be used due to a ?bug?</div><div class='add'>+	 * with the NSO Genesis controller. Over USB, it will report the</div><div class='add'>+	 * PID as 0x201E, but over bluetooth it will report the PID as 0x2017</div><div class='add'>+	 * which is the same as the NSO SNES controller. This is different from</div><div class='add'>+	 * the rest of the controllers which will report the same PID over USB</div><div class='add'>+	 * and bluetooth.</div><div class='add'>+	 */</div><div class='ctx'> 	ctlr-&gt;ctlr_type = report-&gt;subcmd_reply.data[2];</div><div class='add'>+	hid_dbg(ctlr-&gt;hdev, "controller type = 0x%02X\n", ctlr-&gt;ctlr_type);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2145,8 +2518,7 @@ static int joycon_init(struct hid_device *hdev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ctlr-&gt;output_mutex);</div><div class='ctx'> 	/* if handshake command fails, assume ble pro controller */</div><div class='del'>-	if ((jc_type_is_procon(ctlr) || jc_type_is_chrggrip(ctlr)) &amp;&amp;</div><div class='del'>-	    !joycon_send_usb(ctlr, JC_USB_CMD_HANDSHAKE, HZ)) {</div><div class='add'>+	if (joycon_using_usb(ctlr) &amp;&amp; !joycon_send_usb(ctlr, JC_USB_CMD_HANDSHAKE, HZ)) {</div><div class='ctx'> 		hid_dbg(hdev, "detected USB controller\n");</div><div class='ctx'> 		/* set baudrate for improved latency */</div><div class='ctx'> 		ret = joycon_send_usb(ctlr, JC_USB_CMD_BAUDRATE_3M, HZ);</div><div class='hunk'>@@ -2171,24 +2543,43 @@ static int joycon_init(struct hid_device *hdev)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* get controller calibration data, and parse it */</div><div class='del'>-	ret = joycon_request_calibration(ctlr);</div><div class='add'>+	/* needed to retrieve the controller type */</div><div class='add'>+	ret = joycon_read_info(ctlr);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		/*</div><div class='del'>-		 * We can function with default calibration, but it may be</div><div class='del'>-		 * inaccurate. Provide a warning, and continue on.</div><div class='del'>-		 */</div><div class='del'>-		hid_warn(hdev, "Analog stick positions may be inaccurate\n");</div><div class='add'>+		hid_err(hdev, "Failed to retrieve controller info; ret=%d\n",</div><div class='add'>+			ret);</div><div class='add'>+		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* get IMU calibration data, and parse it */</div><div class='del'>-	ret = joycon_request_imu_calibration(ctlr);</div><div class='del'>-	if (ret) {</div><div class='del'>-		/*</div><div class='del'>-		 * We can function with default calibration, but it may be</div><div class='del'>-		 * inaccurate. Provide a warning, and continue on.</div><div class='del'>-		 */</div><div class='del'>-		hid_warn(hdev, "Unable to read IMU calibration data\n");</div><div class='add'>+	if (joycon_has_joysticks(ctlr)) {</div><div class='add'>+		/* get controller calibration data, and parse it */</div><div class='add'>+		ret = joycon_request_calibration(ctlr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * We can function with default calibration, but it may be</div><div class='add'>+			 * inaccurate. Provide a warning, and continue on.</div><div class='add'>+			 */</div><div class='add'>+			hid_warn(hdev, "Analog stick positions may be inaccurate\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (joycon_has_imu(ctlr)) {</div><div class='add'>+		/* get IMU calibration data, and parse it */</div><div class='add'>+		ret = joycon_request_imu_calibration(ctlr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * We can function with default calibration, but it may be</div><div class='add'>+			 * inaccurate. Provide a warning, and continue on.</div><div class='add'>+			 */</div><div class='add'>+			hid_warn(hdev, "Unable to read IMU calibration data\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Enable the IMU */</div><div class='add'>+		ret = joycon_enable_imu(ctlr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			hid_err(hdev, "Failed to enable the IMU; ret=%d\n", ret);</div><div class='add'>+			goto out_unlock;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set the reporting mode to 0x30, which is the full report mode */</div><div class='hunk'>@@ -2198,18 +2589,13 @@ static int joycon_init(struct hid_device *hdev)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Enable rumble */</div><div class='del'>-	ret = joycon_enable_rumble(ctlr);</div><div class='del'>-	if (ret) {</div><div class='del'>-		hid_err(hdev, "Failed to enable rumble; ret=%d\n", ret);</div><div class='del'>-		goto out_unlock;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Enable the IMU */</div><div class='del'>-	ret = joycon_enable_imu(ctlr);</div><div class='del'>-	if (ret) {</div><div class='del'>-		hid_err(hdev, "Failed to enable the IMU; ret=%d\n", ret);</div><div class='del'>-		goto out_unlock;</div><div class='add'>+	if (joycon_has_rumble(ctlr)) {</div><div class='add'>+		/* Enable rumble */</div><div class='add'>+		ret = joycon_enable_rumble(ctlr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			hid_err(hdev, "Failed to enable rumble; ret=%d\n", ret);</div><div class='add'>+			goto out_unlock;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out_unlock:</div><div class='hunk'>@@ -2354,13 +2740,6 @@ static int nintendo_hid_probe(struct hid_device *hdev,</div><div class='ctx'> 		goto err_close;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = joycon_read_info(ctlr);</div><div class='del'>-	if (ret) {</div><div class='del'>-		hid_err(hdev, "Failed to retrieve controller info; ret=%d\n",</div><div class='del'>-			ret);</div><div class='del'>-		goto err_close;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Initialize the leds */</div><div class='ctx'> 	ret = joycon_leds_create(ctlr);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2432,6 +2811,12 @@ static int nintendo_hid_resume(struct hid_device *hdev)</div><div class='ctx'> static const struct hid_device_id nintendo_hid_devices[] = {</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='ctx'> 			 USB_DEVICE_ID_NINTENDO_PROCON) },</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_SNESCON) },</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_GENCON) },</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_N64CON) },</div><div class='ctx'> 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='ctx'> 			 USB_DEVICE_ID_NINTENDO_PROCON) },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='hunk'>@@ -2440,6 +2825,12 @@ static const struct hid_device_id nintendo_hid_devices[] = {</div><div class='ctx'> 			 USB_DEVICE_ID_NINTENDO_JOYCONL) },</div><div class='ctx'> 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='ctx'> 			 USB_DEVICE_ID_NINTENDO_JOYCONR) },</div><div class='add'>+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_SNESCON) },</div><div class='add'>+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_GENCON) },</div><div class='add'>+	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,</div><div class='add'>+			 USB_DEVICE_ID_NINTENDO_N64CON) },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(hid, nintendo_hid_devices);</div><div class='hunk'>@@ -2458,6 +2849,7 @@ static struct hid_driver nintendo_hid_driver = {</div><div class='ctx'> module_hid_driver(nintendo_hid_driver);</div><div class='ctx'> </div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Ryan McClelland &lt;rymcclel@gmail.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Emily Strickland &lt;linux@emily.st&gt;");</div><div class='ctx'> MODULE_AUTHOR("Daniel J. Ogorchock &lt;djogorchock@gmail.com&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("Driver for Nintendo Switch Controllers");</div><div class='del'>-</div><div class='head'>diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c<br/>index ea472923fab0..e0bbf0c6345d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-quirks.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-quirks.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-quirks.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-quirks.c</a></div><div class='hunk'>@@ -121,6 +121,7 @@ static const struct hid_device_id hid_quirks[] = {</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X_V2), HID_QUIRK_MULTI_INPUT },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_PENSKETCH_T609A), HID_QUIRK_MULTI_INPUT },</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_LABTEC, USB_DEVICE_ID_LABTEC_ODDOR_HANDBRAKE), HID_QUIRK_ALWAYS_POLL },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_OPTICAL_USB_MOUSE_600E), HID_QUIRK_ALWAYS_POLL },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL },</div><div class='ctx'> 	{ HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019), HID_QUIRK_ALWAYS_POLL },</div><div class='head'>diff --git a/drivers/hid/hid-sensor-hub.c b/drivers/hid/hid-sensor-hub.c<br/>index 2eba152e8b90..26e93a331a51 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-sensor-hub.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-sensor-hub.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-sensor-hub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-sensor-hub.c</a></div><div class='hunk'>@@ -632,7 +632,7 @@ static int sensor_hub_probe(struct hid_device *hdev,</div><div class='ctx'> 	}</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;hdev-&gt;inputs);</div><div class='ctx'> </div><div class='del'>-	ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT);</div><div class='add'>+	ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT | HID_CONNECT_DRIVER);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		hid_err(hdev, "hw start failed\n");</div><div class='ctx'> 		return ret;</div><div class='head'>diff --git a/drivers/hid/hid-steam.c b/drivers/hid/hid-steam.c<br/>index b110818fc945..b3c4e50e248a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/hid-steam.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/hid-steam.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/hid-steam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/hid-steam.c</a></div><div class='hunk'>@@ -71,60 +71,222 @@ static LIST_HEAD(steam_devices);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Commands that can be sent in a feature report.</div><div class='del'>- * Thanks to Valve for some valuable hints.</div><div class='add'>+ * Thanks to Valve and SDL for the names.</div><div class='ctx'>  */</div><div class='del'>-#define STEAM_CMD_SET_MAPPINGS		0x80</div><div class='del'>-#define STEAM_CMD_CLEAR_MAPPINGS	0x81</div><div class='del'>-#define STEAM_CMD_GET_MAPPINGS		0x82</div><div class='del'>-#define STEAM_CMD_GET_ATTRIB		0x83</div><div class='del'>-#define STEAM_CMD_GET_ATTRIB_LABEL	0x84</div><div class='del'>-#define STEAM_CMD_DEFAULT_MAPPINGS	0x85</div><div class='del'>-#define STEAM_CMD_FACTORY_RESET		0x86</div><div class='del'>-#define STEAM_CMD_WRITE_REGISTER	0x87</div><div class='del'>-#define STEAM_CMD_CLEAR_REGISTER	0x88</div><div class='del'>-#define STEAM_CMD_READ_REGISTER		0x89</div><div class='del'>-#define STEAM_CMD_GET_REGISTER_LABEL	0x8a</div><div class='del'>-#define STEAM_CMD_GET_REGISTER_MAX	0x8b</div><div class='del'>-#define STEAM_CMD_GET_REGISTER_DEFAULT	0x8c</div><div class='del'>-#define STEAM_CMD_SET_MODE		0x8d</div><div class='del'>-#define STEAM_CMD_DEFAULT_MOUSE		0x8e</div><div class='del'>-#define STEAM_CMD_FORCEFEEDBAK		0x8f</div><div class='del'>-#define STEAM_CMD_REQUEST_COMM_STATUS	0xb4</div><div class='del'>-#define STEAM_CMD_GET_SERIAL		0xae</div><div class='del'>-#define STEAM_CMD_HAPTIC_RUMBLE		0xeb</div><div class='del'>-</div><div class='del'>-/* Some useful register ids */</div><div class='del'>-#define STEAM_REG_LPAD_MODE		0x07</div><div class='del'>-#define STEAM_REG_RPAD_MODE		0x08</div><div class='del'>-#define STEAM_REG_RPAD_MARGIN		0x18</div><div class='del'>-#define STEAM_REG_LED			0x2d</div><div class='del'>-#define STEAM_REG_GYRO_MODE		0x30</div><div class='del'>-#define STEAM_REG_LPAD_CLICK_PRESSURE	0x34</div><div class='del'>-#define STEAM_REG_RPAD_CLICK_PRESSURE	0x35</div><div class='del'>-</div><div class='del'>-/* Raw event identifiers */</div><div class='del'>-#define STEAM_EV_INPUT_DATA		0x01</div><div class='del'>-#define STEAM_EV_CONNECT		0x03</div><div class='del'>-#define STEAM_EV_BATTERY		0x04</div><div class='del'>-#define STEAM_EV_DECK_INPUT_DATA	0x09</div><div class='add'>+enum {</div><div class='add'>+	ID_SET_DIGITAL_MAPPINGS		= 0x80,</div><div class='add'>+	ID_CLEAR_DIGITAL_MAPPINGS	= 0x81,</div><div class='add'>+	ID_GET_DIGITAL_MAPPINGS		= 0x82,</div><div class='add'>+	ID_GET_ATTRIBUTES_VALUES	= 0x83,</div><div class='add'>+	ID_GET_ATTRIBUTE_LABEL		= 0x84,</div><div class='add'>+	ID_SET_DEFAULT_DIGITAL_MAPPINGS	= 0x85,</div><div class='add'>+	ID_FACTORY_RESET		= 0x86,</div><div class='add'>+	ID_SET_SETTINGS_VALUES		= 0x87,</div><div class='add'>+	ID_CLEAR_SETTINGS_VALUES	= 0x88,</div><div class='add'>+	ID_GET_SETTINGS_VALUES		= 0x89,</div><div class='add'>+	ID_GET_SETTING_LABEL		= 0x8A,</div><div class='add'>+	ID_GET_SETTINGS_MAXS		= 0x8B,</div><div class='add'>+	ID_GET_SETTINGS_DEFAULTS	= 0x8C,</div><div class='add'>+	ID_SET_CONTROLLER_MODE		= 0x8D,</div><div class='add'>+	ID_LOAD_DEFAULT_SETTINGS	= 0x8E,</div><div class='add'>+	ID_TRIGGER_HAPTIC_PULSE		= 0x8F,</div><div class='add'>+	ID_TURN_OFF_CONTROLLER		= 0x9F,</div><div class='add'>+</div><div class='add'>+	ID_GET_DEVICE_INFO		= 0xA1,</div><div class='add'>+</div><div class='add'>+	ID_CALIBRATE_TRACKPADS		= 0xA7,</div><div class='add'>+	ID_RESERVED_0			= 0xA8,</div><div class='add'>+	ID_SET_SERIAL_NUMBER		= 0xA9,</div><div class='add'>+	ID_GET_TRACKPAD_CALIBRATION	= 0xAA,</div><div class='add'>+	ID_GET_TRACKPAD_FACTORY_CALIBRATION = 0xAB,</div><div class='add'>+	ID_GET_TRACKPAD_RAW_DATA	= 0xAC,</div><div class='add'>+	ID_ENABLE_PAIRING		= 0xAD,</div><div class='add'>+	ID_GET_STRING_ATTRIBUTE		= 0xAE,</div><div class='add'>+	ID_RADIO_ERASE_RECORDS		= 0xAF,</div><div class='add'>+	ID_RADIO_WRITE_RECORD		= 0xB0,</div><div class='add'>+	ID_SET_DONGLE_SETTING		= 0xB1,</div><div class='add'>+	ID_DONGLE_DISCONNECT_DEVICE	= 0xB2,</div><div class='add'>+	ID_DONGLE_COMMIT_DEVICE		= 0xB3,</div><div class='add'>+	ID_DONGLE_GET_WIRELESS_STATE	= 0xB4,</div><div class='add'>+	ID_CALIBRATE_GYRO		= 0xB5,</div><div class='add'>+	ID_PLAY_AUDIO			= 0xB6,</div><div class='add'>+	ID_AUDIO_UPDATE_START		= 0xB7,</div><div class='add'>+	ID_AUDIO_UPDATE_DATA		= 0xB8,</div><div class='add'>+	ID_AUDIO_UPDATE_COMPLETE	= 0xB9,</div><div class='add'>+	ID_GET_CHIPID			= 0xBA,</div><div class='add'>+</div><div class='add'>+	ID_CALIBRATE_JOYSTICK		= 0xBF,</div><div class='add'>+	ID_CALIBRATE_ANALOG_TRIGGERS	= 0xC0,</div><div class='add'>+	ID_SET_AUDIO_MAPPING		= 0xC1,</div><div class='add'>+	ID_CHECK_GYRO_FW_LOAD		= 0xC2,</div><div class='add'>+	ID_CALIBRATE_ANALOG		= 0xC3,</div><div class='add'>+	ID_DONGLE_GET_CONNECTED_SLOTS	= 0xC4,</div><div class='add'>+</div><div class='add'>+	ID_RESET_IMU			= 0xCE,</div><div class='add'>+</div><div class='add'>+	ID_TRIGGER_HAPTIC_CMD		= 0xEA,</div><div class='add'>+	ID_TRIGGER_RUMBLE_CMD		= 0xEB,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Settings IDs */</div><div class='add'>+enum {</div><div class='add'>+	/* 0 */</div><div class='add'>+	SETTING_MOUSE_SENSITIVITY,</div><div class='add'>+	SETTING_MOUSE_ACCELERATION,</div><div class='add'>+	SETTING_TRACKBALL_ROTATION_ANGLE,</div><div class='add'>+	SETTING_HAPTIC_INTENSITY_UNUSED,</div><div class='add'>+	SETTING_LEFT_GAMEPAD_STICK_ENABLED,</div><div class='add'>+	SETTING_RIGHT_GAMEPAD_STICK_ENABLED,</div><div class='add'>+	SETTING_USB_DEBUG_MODE,</div><div class='add'>+	SETTING_LEFT_TRACKPAD_MODE,</div><div class='add'>+	SETTING_RIGHT_TRACKPAD_MODE,</div><div class='add'>+	SETTING_MOUSE_POINTER_ENABLED,</div><div class='add'>+</div><div class='add'>+	/* 10 */</div><div class='add'>+	SETTING_DPAD_DEADZONE,</div><div class='add'>+	SETTING_MINIMUM_MOMENTUM_VEL,</div><div class='add'>+	SETTING_MOMENTUM_DECAY_AMMOUNT,</div><div class='add'>+	SETTING_TRACKPAD_RELATIVE_MODE_TICKS_PER_PIXEL,</div><div class='add'>+	SETTING_HAPTIC_INCREMENT,</div><div class='add'>+	SETTING_DPAD_ANGLE_SIN,</div><div class='add'>+	SETTING_DPAD_ANGLE_COS,</div><div class='add'>+	SETTING_MOMENTUM_VERTICAL_DIVISOR,</div><div class='add'>+	SETTING_MOMENTUM_MAXIMUM_VELOCITY,</div><div class='add'>+	SETTING_TRACKPAD_Z_ON,</div><div class='add'>+</div><div class='add'>+	/* 20 */</div><div class='add'>+	SETTING_TRACKPAD_Z_OFF,</div><div class='add'>+	SETTING_SENSITIVY_SCALE_AMMOUNT,</div><div class='add'>+	SETTING_LEFT_TRACKPAD_SECONDARY_MODE,</div><div class='add'>+	SETTING_RIGHT_TRACKPAD_SECONDARY_MODE,</div><div class='add'>+	SETTING_SMOOTH_ABSOLUTE_MOUSE,</div><div class='add'>+	SETTING_STEAMBUTTON_POWEROFF_TIME,</div><div class='add'>+	SETTING_UNUSED_1,</div><div class='add'>+	SETTING_TRACKPAD_OUTER_RADIUS,</div><div class='add'>+	SETTING_TRACKPAD_Z_ON_LEFT,</div><div class='add'>+	SETTING_TRACKPAD_Z_OFF_LEFT,</div><div class='add'>+</div><div class='add'>+	/* 30 */</div><div class='add'>+	SETTING_TRACKPAD_OUTER_SPIN_VEL,</div><div class='add'>+	SETTING_TRACKPAD_OUTER_SPIN_RADIUS,</div><div class='add'>+	SETTING_TRACKPAD_OUTER_SPIN_HORIZONTAL_ONLY,</div><div class='add'>+	SETTING_TRACKPAD_RELATIVE_MODE_DEADZONE,</div><div class='add'>+	SETTING_TRACKPAD_RELATIVE_MODE_MAX_VEL,</div><div class='add'>+	SETTING_TRACKPAD_RELATIVE_MODE_INVERT_Y,</div><div class='add'>+	SETTING_TRACKPAD_DOUBLE_TAP_BEEP_ENABLED,</div><div class='add'>+	SETTING_TRACKPAD_DOUBLE_TAP_BEEP_PERIOD,</div><div class='add'>+	SETTING_TRACKPAD_DOUBLE_TAP_BEEP_COUNT,</div><div class='add'>+	SETTING_TRACKPAD_OUTER_RADIUS_RELEASE_ON_TRANSITION,</div><div class='add'>+</div><div class='add'>+	/* 40 */</div><div class='add'>+	SETTING_RADIAL_MODE_ANGLE,</div><div class='add'>+	SETTING_HAPTIC_INTENSITY_MOUSE_MODE,</div><div class='add'>+	SETTING_LEFT_DPAD_REQUIRES_CLICK,</div><div class='add'>+	SETTING_RIGHT_DPAD_REQUIRES_CLICK,</div><div class='add'>+	SETTING_LED_BASELINE_BRIGHTNESS,</div><div class='add'>+	SETTING_LED_USER_BRIGHTNESS,</div><div class='add'>+	SETTING_ENABLE_RAW_JOYSTICK,</div><div class='add'>+	SETTING_ENABLE_FAST_SCAN,</div><div class='add'>+	SETTING_IMU_MODE,</div><div class='add'>+	SETTING_WIRELESS_PACKET_VERSION,</div><div class='add'>+</div><div class='add'>+	/* 50 */</div><div class='add'>+	SETTING_SLEEP_INACTIVITY_TIMEOUT,</div><div class='add'>+	SETTING_TRACKPAD_NOISE_THRESHOLD,</div><div class='add'>+	SETTING_LEFT_TRACKPAD_CLICK_PRESSURE,</div><div class='add'>+	SETTING_RIGHT_TRACKPAD_CLICK_PRESSURE,</div><div class='add'>+	SETTING_LEFT_BUMPER_CLICK_PRESSURE,</div><div class='add'>+	SETTING_RIGHT_BUMPER_CLICK_PRESSURE,</div><div class='add'>+	SETTING_LEFT_GRIP_CLICK_PRESSURE,</div><div class='add'>+	SETTING_RIGHT_GRIP_CLICK_PRESSURE,</div><div class='add'>+	SETTING_LEFT_GRIP2_CLICK_PRESSURE,</div><div class='add'>+	SETTING_RIGHT_GRIP2_CLICK_PRESSURE,</div><div class='add'>+</div><div class='add'>+	/* 60 */</div><div class='add'>+	SETTING_PRESSURE_MODE,</div><div class='add'>+	SETTING_CONTROLLER_TEST_MODE,</div><div class='add'>+	SETTING_TRIGGER_MODE,</div><div class='add'>+	SETTING_TRACKPAD_Z_THRESHOLD,</div><div class='add'>+	SETTING_FRAME_RATE,</div><div class='add'>+	SETTING_TRACKPAD_FILT_CTRL,</div><div class='add'>+	SETTING_TRACKPAD_CLIP,</div><div class='add'>+	SETTING_DEBUG_OUTPUT_SELECT,</div><div class='add'>+	SETTING_TRIGGER_THRESHOLD_PERCENT,</div><div class='add'>+	SETTING_TRACKPAD_FREQUENCY_HOPPING,</div><div class='add'>+</div><div class='add'>+	/* 70 */</div><div class='add'>+	SETTING_HAPTICS_ENABLED,</div><div class='add'>+	SETTING_STEAM_WATCHDOG_ENABLE,</div><div class='add'>+	SETTING_TIMP_TOUCH_THRESHOLD_ON,</div><div class='add'>+	SETTING_TIMP_TOUCH_THRESHOLD_OFF,</div><div class='add'>+	SETTING_FREQ_HOPPING,</div><div class='add'>+	SETTING_TEST_CONTROL,</div><div class='add'>+	SETTING_HAPTIC_MASTER_GAIN_DB,</div><div class='add'>+	SETTING_THUMB_TOUCH_THRESH,</div><div class='add'>+	SETTING_DEVICE_POWER_STATUS,</div><div class='add'>+	SETTING_HAPTIC_INTENSITY,</div><div class='add'>+</div><div class='add'>+	/* 80 */</div><div class='add'>+	SETTING_STABILIZER_ENABLED,</div><div class='add'>+	SETTING_TIMP_MODE_MTE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Input report identifiers */</div><div class='add'>+enum</div><div class='add'>+{</div><div class='add'>+	ID_CONTROLLER_STATE = 1,</div><div class='add'>+	ID_CONTROLLER_DEBUG = 2,</div><div class='add'>+	ID_CONTROLLER_WIRELESS = 3,</div><div class='add'>+	ID_CONTROLLER_STATUS = 4,</div><div class='add'>+	ID_CONTROLLER_DEBUG2 = 5,</div><div class='add'>+	ID_CONTROLLER_SECONDARY_STATE = 6,</div><div class='add'>+	ID_CONTROLLER_BLE_STATE = 7,</div><div class='add'>+	ID_CONTROLLER_DECK_STATE = 9</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* String attribute idenitifiers */</div><div class='add'>+enum {</div><div class='add'>+	ATTRIB_STR_BOARD_SERIAL,</div><div class='add'>+	ATTRIB_STR_UNIT_SERIAL,</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /* Values for GYRO_MODE (bitmask) */</div><div class='del'>-#define STEAM_GYRO_MODE_OFF		0x0000</div><div class='del'>-#define STEAM_GYRO_MODE_STEERING	0x0001</div><div class='del'>-#define STEAM_GYRO_MODE_TILT		0x0002</div><div class='del'>-#define STEAM_GYRO_MODE_SEND_ORIENTATION	0x0004</div><div class='del'>-#define STEAM_GYRO_MODE_SEND_RAW_ACCEL		0x0008</div><div class='del'>-#define STEAM_GYRO_MODE_SEND_RAW_GYRO		0x0010</div><div class='add'>+enum {</div><div class='add'>+	SETTING_GYRO_MODE_OFF			= 0,</div><div class='add'>+	SETTING_GYRO_MODE_STEERING		= BIT(0),</div><div class='add'>+	SETTING_GYRO_MODE_TILT			= BIT(1),</div><div class='add'>+	SETTING_GYRO_MODE_SEND_ORIENTATION	= BIT(2),</div><div class='add'>+	SETTING_GYRO_MODE_SEND_RAW_ACCEL	= BIT(3),</div><div class='add'>+	SETTING_GYRO_MODE_SEND_RAW_GYRO		= BIT(4),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Trackpad modes */</div><div class='add'>+enum {</div><div class='add'>+	TRACKPAD_ABSOLUTE_MOUSE,</div><div class='add'>+	TRACKPAD_RELATIVE_MOUSE,</div><div class='add'>+	TRACKPAD_DPAD_FOUR_WAY_DISCRETE,</div><div class='add'>+	TRACKPAD_DPAD_FOUR_WAY_OVERLAP,</div><div class='add'>+	TRACKPAD_DPAD_EIGHT_WAY,</div><div class='add'>+	TRACKPAD_RADIAL_MODE,</div><div class='add'>+	TRACKPAD_ABSOLUTE_DPAD,</div><div class='add'>+	TRACKPAD_NONE,</div><div class='add'>+	TRACKPAD_GESTURE_KEYBOARD,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Pad identifiers for the deck */</div><div class='add'>+#define STEAM_PAD_LEFT 0</div><div class='add'>+#define STEAM_PAD_RIGHT 1</div><div class='add'>+#define STEAM_PAD_BOTH 2</div><div class='ctx'> </div><div class='ctx'> /* Other random constants */</div><div class='del'>-#define STEAM_SERIAL_LEN 10</div><div class='add'>+#define STEAM_SERIAL_LEN 0x15</div><div class='ctx'> </div><div class='ctx'> struct steam_device {</div><div class='ctx'> 	struct list_head list;</div><div class='ctx'> 	spinlock_t lock;</div><div class='ctx'> 	struct hid_device *hdev, *client_hdev;</div><div class='del'>-	struct mutex mutex;</div><div class='del'>-	bool client_opened;</div><div class='add'>+	struct mutex report_mutex;</div><div class='add'>+	unsigned long client_opened;</div><div class='ctx'> 	struct input_dev __rcu *input;</div><div class='ctx'> 	unsigned long quirks;</div><div class='ctx'> 	struct work_struct work_connect;</div><div class='hunk'>@@ -134,7 +296,9 @@ struct steam_device {</div><div class='ctx'> 	struct power_supply __rcu *battery;</div><div class='ctx'> 	u8 battery_charge;</div><div class='ctx'> 	u16 voltage;</div><div class='del'>-	struct delayed_work heartbeat;</div><div class='add'>+	struct delayed_work mode_switch;</div><div class='add'>+	bool did_mode_switch;</div><div class='add'>+	bool gamepad_mode;</div><div class='ctx'> 	struct work_struct rumble_work;</div><div class='ctx'> 	u16 rumble_left;</div><div class='ctx'> 	u16 rumble_right;</div><div class='hunk'>@@ -226,13 +390,13 @@ static inline int steam_send_report_byte(struct steam_device *steam, u8 cmd)</div><div class='ctx'> 	return steam_send_report(steam, &amp;cmd, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int steam_write_registers(struct steam_device *steam,</div><div class='add'>+static int steam_write_settings(struct steam_device *steam,</div><div class='ctx'> 		/* u8 reg, u16 val */...)</div><div class='ctx'> {</div><div class='ctx'> 	/* Send: 0x87 len (reg valLo valHi)* */</div><div class='ctx'> 	u8 reg;</div><div class='ctx'> 	u16 val;</div><div class='del'>-	u8 cmd[64] = {STEAM_CMD_WRITE_REGISTER, 0x00};</div><div class='add'>+	u8 cmd[64] = {ID_SET_SETTINGS_VALUES, 0x00};</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	va_list args;</div><div class='ctx'> </div><div class='hunk'>@@ -265,23 +429,29 @@ static int steam_get_serial(struct steam_device *steam)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Send: 0xae 0x15 0x01</div><div class='del'>-	 * Recv: 0xae 0x15 0x01 serialnumber (10 chars)</div><div class='add'>+	 * Recv: 0xae 0x15 0x01 serialnumber</div><div class='ctx'> 	 */</div><div class='del'>-	int ret;</div><div class='del'>-	u8 cmd[] = {STEAM_CMD_GET_SERIAL, 0x15, 0x01};</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u8 cmd[] = {ID_GET_STRING_ATTRIBUTE, sizeof(steam-&gt;serial_no), ATTRIB_STR_UNIT_SERIAL};</div><div class='ctx'> 	u8 reply[3 + STEAM_SERIAL_LEN + 1];</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 	ret = steam_send_report(steam, cmd, sizeof(cmd));</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+		goto out;</div><div class='ctx'> 	ret = steam_recv_report(steam, reply, sizeof(reply));</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='del'>-	if (reply[0] != 0xae || reply[1] != 0x15 || reply[2] != 0x01)</div><div class='del'>-		return -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	if (reply[0] != ID_GET_STRING_ATTRIBUTE || reply[1] &lt; 1 ||</div><div class='add'>+	    reply[1] &gt; sizeof(steam-&gt;serial_no) || reply[2] != ATTRIB_STR_UNIT_SERIAL) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='ctx'> 	reply[3 + STEAM_SERIAL_LEN] = 0;</div><div class='del'>-	strscpy(steam-&gt;serial_no, reply + 3, sizeof(steam-&gt;serial_no));</div><div class='del'>-	return 0;</div><div class='add'>+	strscpy(steam-&gt;serial_no, reply + 3, reply[1]);</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -291,14 +461,50 @@ static int steam_get_serial(struct steam_device *steam)</div><div class='ctx'>  */</div><div class='ctx'> static inline int steam_request_conn_status(struct steam_device *steam)</div><div class='ctx'> {</div><div class='del'>-	return steam_send_report_byte(steam, STEAM_CMD_REQUEST_COMM_STATUS);</div><div class='add'>+	int ret;</div><div class='add'>+	mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	ret = steam_send_report_byte(steam, ID_DONGLE_GET_WIRELESS_STATE);</div><div class='add'>+	mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Send a haptic pulse to the trackpads</div><div class='add'>+ * Duration and interval are measured in microseconds, count is the number</div><div class='add'>+ * of pulses to send for duration time with interval microseconds between them</div><div class='add'>+ * and gain is measured in decibels, ranging from -24 to +6</div><div class='add'>+ */</div><div class='add'>+static inline int steam_haptic_pulse(struct steam_device *steam, u8 pad,</div><div class='add'>+				u16 duration, u16 interval, u16 count, u8 gain)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u8 report[10] = {ID_TRIGGER_HAPTIC_PULSE, 8};</div><div class='add'>+</div><div class='add'>+	/* Left and right are swapped on this report for legacy reasons */</div><div class='add'>+	if (pad &lt; STEAM_PAD_BOTH)</div><div class='add'>+		pad ^= 1;</div><div class='add'>+</div><div class='add'>+	report[2] = pad;</div><div class='add'>+	report[3] = duration &amp; 0xFF;</div><div class='add'>+	report[4] = duration &gt;&gt; 8;</div><div class='add'>+	report[5] = interval &amp; 0xFF;</div><div class='add'>+	report[6] = interval &gt;&gt; 8;</div><div class='add'>+	report[7] = count &amp; 0xFF;</div><div class='add'>+	report[8] = count &gt;&gt; 8;</div><div class='add'>+	report[9] = gain;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	ret = steam_send_report(steam, report, sizeof(report));</div><div class='add'>+	mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int steam_haptic_rumble(struct steam_device *steam,</div><div class='ctx'> 				u16 intensity, u16 left_speed, u16 right_speed,</div><div class='ctx'> 				u8 left_gain, u8 right_gain)</div><div class='ctx'> {</div><div class='del'>-	u8 report[11] = {STEAM_CMD_HAPTIC_RUMBLE, 9};</div><div class='add'>+	int ret;</div><div class='add'>+	u8 report[11] = {ID_TRIGGER_RUMBLE_CMD, 9};</div><div class='ctx'> </div><div class='ctx'> 	report[3] = intensity &amp; 0xFF;</div><div class='ctx'> 	report[4] = intensity &gt;&gt; 8;</div><div class='hunk'>@@ -309,7 +515,10 @@ static inline int steam_haptic_rumble(struct steam_device *steam,</div><div class='ctx'> 	report[9] = left_gain;</div><div class='ctx'> 	report[10] = right_gain;</div><div class='ctx'> </div><div class='del'>-	return steam_send_report(steam, report, sizeof(report));</div><div class='add'>+	mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	ret = steam_send_report(steam, report, sizeof(report));</div><div class='add'>+	mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void steam_haptic_rumble_cb(struct work_struct *work)</div><div class='hunk'>@@ -335,40 +544,36 @@ static int steam_play_effect(struct input_dev *dev, void *data,</div><div class='ctx'> </div><div class='ctx'> static void steam_set_lizard_mode(struct steam_device *steam, bool enable)</div><div class='ctx'> {</div><div class='add'>+	if (steam-&gt;gamepad_mode)</div><div class='add'>+		enable = false;</div><div class='add'>+</div><div class='ctx'> 	if (enable) {</div><div class='add'>+		mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 		/* enable esc, enter, cursors */</div><div class='del'>-		steam_send_report_byte(steam, STEAM_CMD_DEFAULT_MAPPINGS);</div><div class='del'>-		/* enable mouse */</div><div class='del'>-		steam_send_report_byte(steam, STEAM_CMD_DEFAULT_MOUSE);</div><div class='del'>-		steam_write_registers(steam,</div><div class='del'>-			STEAM_REG_RPAD_MARGIN, 0x01, /* enable margin */</div><div class='del'>-			0);</div><div class='del'>-</div><div class='del'>-		cancel_delayed_work_sync(&amp;steam-&gt;heartbeat);</div><div class='add'>+		steam_send_report_byte(steam, ID_SET_DEFAULT_DIGITAL_MAPPINGS);</div><div class='add'>+		/* reset settings */</div><div class='add'>+		steam_send_report_byte(steam, ID_LOAD_DEFAULT_SETTINGS);</div><div class='add'>+		mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 	} else {</div><div class='add'>+		mutex_lock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 		/* disable esc, enter, cursor */</div><div class='del'>-		steam_send_report_byte(steam, STEAM_CMD_CLEAR_MAPPINGS);</div><div class='add'>+		steam_send_report_byte(steam, ID_CLEAR_DIGITAL_MAPPINGS);</div><div class='ctx'> </div><div class='ctx'> 		if (steam-&gt;quirks &amp; STEAM_QUIRK_DECK) {</div><div class='del'>-			steam_write_registers(steam,</div><div class='del'>-				STEAM_REG_RPAD_MARGIN, 0x00, /* disable margin */</div><div class='del'>-				STEAM_REG_LPAD_MODE, 0x07, /* disable mouse */</div><div class='del'>-				STEAM_REG_RPAD_MODE, 0x07, /* disable mouse */</div><div class='del'>-				STEAM_REG_LPAD_CLICK_PRESSURE, 0xFFFF, /* disable clicky pad */</div><div class='del'>-				STEAM_REG_RPAD_CLICK_PRESSURE, 0xFFFF, /* disable clicky pad */</div><div class='add'>+			steam_write_settings(steam,</div><div class='add'>+				SETTING_LEFT_TRACKPAD_MODE, TRACKPAD_NONE, /* disable mouse */</div><div class='add'>+				SETTING_RIGHT_TRACKPAD_MODE, TRACKPAD_NONE, /* disable mouse */</div><div class='add'>+				SETTING_LEFT_TRACKPAD_CLICK_PRESSURE, 0xFFFF, /* disable haptic click */</div><div class='add'>+				SETTING_RIGHT_TRACKPAD_CLICK_PRESSURE, 0xFFFF, /* disable haptic click */</div><div class='add'>+				SETTING_STEAM_WATCHDOG_ENABLE, 0, /* disable watchdog that tests if Steam is active */</div><div class='ctx'> 				0);</div><div class='del'>-			/*</div><div class='del'>-			 * The Steam Deck has a watchdog that automatically enables</div><div class='del'>-			 * lizard mode if it doesn't see any traffic for too long</div><div class='del'>-			 */</div><div class='del'>-			if (!work_busy(&amp;steam-&gt;heartbeat.work))</div><div class='del'>-				schedule_delayed_work(&amp;steam-&gt;heartbeat, 5 * HZ);</div><div class='add'>+			mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 		} else {</div><div class='del'>-			steam_write_registers(steam,</div><div class='del'>-				STEAM_REG_RPAD_MARGIN, 0x00, /* disable margin */</div><div class='del'>-				STEAM_REG_LPAD_MODE, 0x07, /* disable mouse */</div><div class='del'>-				STEAM_REG_RPAD_MODE, 0x07, /* disable mouse */</div><div class='add'>+			steam_write_settings(steam,</div><div class='add'>+				SETTING_LEFT_TRACKPAD_MODE, TRACKPAD_NONE, /* disable mouse */</div><div class='add'>+				SETTING_RIGHT_TRACKPAD_MODE, TRACKPAD_NONE, /* disable mouse */</div><div class='ctx'> 				0);</div><div class='add'>+			mutex_unlock(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -376,22 +581,38 @@ static void steam_set_lizard_mode(struct steam_device *steam, bool enable)</div><div class='ctx'> static int steam_input_open(struct input_dev *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct steam_device *steam = input_get_drvdata(dev);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool set_lizard_mode;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Disabling lizard mode automatically is only done on the Steam</div><div class='add'>+	 * Controller. On the Steam Deck, this is toggled manually by holding</div><div class='add'>+	 * the options button instead, handled by steam_mode_switch_cb.</div><div class='add'>+	 */</div><div class='add'>+	if (!(steam-&gt;quirks &amp; STEAM_QUIRK_DECK)) {</div><div class='add'>+		spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='add'>+		set_lizard_mode = !steam-&gt;client_opened &amp;&amp; lizard_mode;</div><div class='add'>+		spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='add'>+		if (set_lizard_mode)</div><div class='add'>+			steam_set_lizard_mode(steam, false);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='del'>-	if (!steam-&gt;client_opened &amp;&amp; lizard_mode)</div><div class='del'>-		steam_set_lizard_mode(steam, false);</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void steam_input_close(struct input_dev *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct steam_device *steam = input_get_drvdata(dev);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool set_lizard_mode;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='del'>-	if (!steam-&gt;client_opened &amp;&amp; lizard_mode)</div><div class='del'>-		steam_set_lizard_mode(steam, true);</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='add'>+	if (!(steam-&gt;quirks &amp; STEAM_QUIRK_DECK)) {</div><div class='add'>+		spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='add'>+		set_lizard_mode = !steam-&gt;client_opened &amp;&amp; lizard_mode;</div><div class='add'>+		spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='add'>+		if (set_lizard_mode)</div><div class='add'>+			steam_set_lizard_mode(steam, true);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum power_supply_property steam_battery_props[] = {</div><div class='hunk'>@@ -635,7 +856,8 @@ static void steam_battery_unregister(struct steam_device *steam)</div><div class='ctx'> static int steam_register(struct steam_device *steam)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='del'>-	bool client_opened;</div><div class='add'>+	unsigned long client_opened;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * This function can be called several times in a row with the</div><div class='hunk'>@@ -648,11 +870,9 @@ static int steam_register(struct steam_device *steam)</div><div class='ctx'> 		 * Unlikely, but getting the serial could fail, and it is not so</div><div class='ctx'> 		 * important, so make up a serial number and go on.</div><div class='ctx'> 		 */</div><div class='del'>-		mutex_lock(&amp;steam-&gt;mutex);</div><div class='ctx'> 		if (steam_get_serial(steam) &lt; 0)</div><div class='ctx'> 			strscpy(steam-&gt;serial_no, "XXXXXXXXXX",</div><div class='ctx'> 					sizeof(steam-&gt;serial_no));</div><div class='del'>-		mutex_unlock(&amp;steam-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 		hid_info(steam-&gt;hdev, "Steam Controller '%s' connected",</div><div class='ctx'> 				steam-&gt;serial_no);</div><div class='hunk'>@@ -667,15 +887,13 @@ static int steam_register(struct steam_device *steam)</div><div class='ctx'> 		mutex_unlock(&amp;steam_devices_lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='add'>+	spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='ctx'> 	client_opened = steam-&gt;client_opened;</div><div class='del'>-	if (!client_opened)</div><div class='add'>+	spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='add'>+	if (!client_opened) {</div><div class='ctx'> 		steam_set_lizard_mode(steam, lizard_mode);</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	if (!client_opened)</div><div class='ctx'> 		ret = steam_input_register(steam);</div><div class='del'>-	else</div><div class='add'>+	} else</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -719,6 +937,34 @@ static void steam_work_connect_cb(struct work_struct *work)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void steam_mode_switch_cb(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct steam_device *steam = container_of(to_delayed_work(work),</div><div class='add'>+							struct steam_device, mode_switch);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool client_opened;</div><div class='add'>+	steam-&gt;gamepad_mode = !steam-&gt;gamepad_mode;</div><div class='add'>+	if (!lizard_mode)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (steam-&gt;gamepad_mode)</div><div class='add'>+		steam_set_lizard_mode(steam, false);</div><div class='add'>+	else {</div><div class='add'>+		spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='add'>+		client_opened = steam-&gt;client_opened;</div><div class='add'>+		spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='add'>+		if (!client_opened)</div><div class='add'>+			steam_set_lizard_mode(steam, lizard_mode);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	steam_haptic_pulse(steam, STEAM_PAD_RIGHT, 0x190, 0, 1, 0);</div><div class='add'>+	if (steam-&gt;gamepad_mode) {</div><div class='add'>+		steam_haptic_pulse(steam, STEAM_PAD_LEFT, 0x14D, 0x14D, 0x2D, 0);</div><div class='add'>+	} else {</div><div class='add'>+		steam_haptic_pulse(steam, STEAM_PAD_LEFT, 0x1F4, 0x1F4, 0x1E, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool steam_is_valve_interface(struct hid_device *hdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct hid_report_enum *rep_enum;</div><div class='hunk'>@@ -738,22 +984,6 @@ static bool steam_is_valve_interface(struct hid_device *hdev)</div><div class='ctx'> 	return !list_empty(&amp;rep_enum-&gt;report_list);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void steam_lizard_mode_heartbeat(struct work_struct *work)</div><div class='del'>-{</div><div class='del'>-	struct steam_device *steam = container_of(work, struct steam_device,</div><div class='del'>-							heartbeat.work);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='del'>-	if (!steam-&gt;client_opened &amp;&amp; steam-&gt;client_hdev) {</div><div class='del'>-		steam_send_report_byte(steam, STEAM_CMD_CLEAR_MAPPINGS);</div><div class='del'>-		steam_write_registers(steam,</div><div class='del'>-			STEAM_REG_RPAD_MODE, 0x07, /* disable mouse */</div><div class='del'>-			0);</div><div class='del'>-		schedule_delayed_work(&amp;steam-&gt;heartbeat, 5 * HZ);</div><div class='del'>-	}</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int steam_client_ll_parse(struct hid_device *hdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct steam_device *steam = hdev-&gt;driver_data;</div><div class='hunk'>@@ -774,10 +1004,11 @@ static void steam_client_ll_stop(struct hid_device *hdev)</div><div class='ctx'> static int steam_client_ll_open(struct hid_device *hdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct steam_device *steam = hdev-&gt;driver_data;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='del'>-	steam-&gt;client_opened = true;</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='add'>+	spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='add'>+	steam-&gt;client_opened++;</div><div class='add'>+	spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	steam_input_unregister(steam);</div><div class='ctx'> </div><div class='hunk'>@@ -792,17 +1023,14 @@ static void steam_client_ll_close(struct hid_device *hdev)</div><div class='ctx'> 	bool connected;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;steam-&gt;lock, flags);</div><div class='del'>-	connected = steam-&gt;connected;</div><div class='add'>+	steam-&gt;client_opened--;</div><div class='add'>+	connected = steam-&gt;connected &amp;&amp; !steam-&gt;client_opened;</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;steam-&gt;lock, flags);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='del'>-	steam-&gt;client_opened = false;</div><div class='del'>-	if (connected)</div><div class='add'>+	if (connected) {</div><div class='ctx'> 		steam_set_lizard_mode(steam, lizard_mode);</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	if (connected)</div><div class='ctx'> 		steam_input_register(steam);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int steam_client_ll_raw_request(struct hid_device *hdev,</div><div class='hunk'>@@ -888,20 +1116,13 @@ static int steam_probe(struct hid_device *hdev,</div><div class='ctx'> 	steam-&gt;hdev = hdev;</div><div class='ctx'> 	hid_set_drvdata(hdev, steam);</div><div class='ctx'> 	spin_lock_init(&amp;steam-&gt;lock);</div><div class='del'>-	mutex_init(&amp;steam-&gt;mutex);</div><div class='add'>+	mutex_init(&amp;steam-&gt;report_mutex);</div><div class='ctx'> 	steam-&gt;quirks = id-&gt;driver_data;</div><div class='ctx'> 	INIT_WORK(&amp;steam-&gt;work_connect, steam_work_connect_cb);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;steam-&gt;mode_switch, steam_mode_switch_cb);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;steam-&gt;list);</div><div class='del'>-	INIT_DEFERRABLE_WORK(&amp;steam-&gt;heartbeat, steam_lizard_mode_heartbeat);</div><div class='ctx'> 	INIT_WORK(&amp;steam-&gt;rumble_work, steam_haptic_rumble_cb);</div><div class='ctx'> </div><div class='del'>-	steam-&gt;client_hdev = steam_create_client_hid(hdev);</div><div class='del'>-	if (IS_ERR(steam-&gt;client_hdev)) {</div><div class='del'>-		ret = PTR_ERR(steam-&gt;client_hdev);</div><div class='del'>-		goto client_hdev_fail;</div><div class='del'>-	}</div><div class='del'>-	steam-&gt;client_hdev-&gt;driver_data = steam;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * With the real steam controller interface, do not connect hidraw.</div><div class='ctx'> 	 * Instead, create the client_hid and connect that.</div><div class='hunk'>@@ -910,10 +1131,6 @@ static int steam_probe(struct hid_device *hdev,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto hid_hw_start_fail;</div><div class='ctx'> </div><div class='del'>-	ret = hid_add_device(steam-&gt;client_hdev);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto client_hdev_add_fail;</div><div class='del'>-</div><div class='ctx'> 	ret = hid_hw_open(hdev);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		hid_err(hdev,</div><div class='hunk'>@@ -939,17 +1156,28 @@ static int steam_probe(struct hid_device *hdev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	steam-&gt;client_hdev = steam_create_client_hid(hdev);</div><div class='add'>+	if (IS_ERR(steam-&gt;client_hdev)) {</div><div class='add'>+		ret = PTR_ERR(steam-&gt;client_hdev);</div><div class='add'>+		goto client_hdev_fail;</div><div class='add'>+	}</div><div class='add'>+	steam-&gt;client_hdev-&gt;driver_data = steam;</div><div class='add'>+</div><div class='add'>+	ret = hid_add_device(steam-&gt;client_hdev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto client_hdev_add_fail;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-input_register_fail:</div><div class='del'>-hid_hw_open_fail:</div><div class='ctx'> client_hdev_add_fail:</div><div class='ctx'> 	hid_hw_stop(hdev);</div><div class='del'>-hid_hw_start_fail:</div><div class='del'>-	hid_destroy_device(steam-&gt;client_hdev);</div><div class='ctx'> client_hdev_fail:</div><div class='add'>+	hid_destroy_device(steam-&gt;client_hdev);</div><div class='add'>+input_register_fail:</div><div class='add'>+hid_hw_open_fail:</div><div class='add'>+hid_hw_start_fail:</div><div class='ctx'> 	cancel_work_sync(&amp;steam-&gt;work_connect);</div><div class='del'>-	cancel_delayed_work_sync(&amp;steam-&gt;heartbeat);</div><div class='add'>+	cancel_delayed_work_sync(&amp;steam-&gt;mode_switch);</div><div class='ctx'> 	cancel_work_sync(&amp;steam-&gt;rumble_work);</div><div class='ctx'> steam_alloc_fail:</div><div class='ctx'> 	hid_err(hdev, "%s: failed with error %d\n",</div><div class='hunk'>@@ -966,13 +1194,11 @@ static void steam_remove(struct hid_device *hdev)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	cancel_delayed_work_sync(&amp;steam-&gt;mode_switch);</div><div class='add'>+	cancel_work_sync(&amp;steam-&gt;work_connect);</div><div class='ctx'> 	hid_destroy_device(steam-&gt;client_hdev);</div><div class='del'>-	mutex_lock(&amp;steam-&gt;mutex);</div><div class='ctx'> 	steam-&gt;client_hdev = NULL;</div><div class='del'>-	steam-&gt;client_opened = false;</div><div class='del'>-	cancel_delayed_work_sync(&amp;steam-&gt;heartbeat);</div><div class='del'>-	mutex_unlock(&amp;steam-&gt;mutex);</div><div class='del'>-	cancel_work_sync(&amp;steam-&gt;work_connect);</div><div class='add'>+	steam-&gt;client_opened = 0;</div><div class='ctx'> 	if (steam-&gt;quirks &amp; STEAM_QUIRK_WIRELESS) {</div><div class='ctx'> 		hid_info(hdev, "Steam wireless receiver disconnected");</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1254,6 +1480,17 @@ static void steam_do_deck_input_event(struct steam_device *steam,</div><div class='ctx'> 	b13 = data[13];</div><div class='ctx'> 	b14 = data[14];</div><div class='ctx'> </div><div class='add'>+	if (!(b9 &amp; BIT(6)) &amp;&amp; steam-&gt;did_mode_switch) {</div><div class='add'>+		steam-&gt;did_mode_switch = false;</div><div class='add'>+		cancel_delayed_work_sync(&amp;steam-&gt;mode_switch);</div><div class='add'>+	} else if (!steam-&gt;client_opened &amp;&amp; (b9 &amp; BIT(6)) &amp;&amp; !steam-&gt;did_mode_switch) {</div><div class='add'>+		steam-&gt;did_mode_switch = true;</div><div class='add'>+		schedule_delayed_work(&amp;steam-&gt;mode_switch, 45 * HZ / 100);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!steam-&gt;gamepad_mode)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	lpad_touched = b10 &amp; BIT(3);</div><div class='ctx'> 	rpad_touched = b10 &amp; BIT(4);</div><div class='ctx'> </div><div class='hunk'>@@ -1375,7 +1612,7 @@ static int steam_raw_event(struct hid_device *hdev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (data[2]) {</div><div class='del'>-	case STEAM_EV_INPUT_DATA:</div><div class='add'>+	case ID_CONTROLLER_STATE:</div><div class='ctx'> 		if (steam-&gt;client_opened)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		rcu_read_lock();</div><div class='hunk'>@@ -1384,7 +1621,7 @@ static int steam_raw_event(struct hid_device *hdev,</div><div class='ctx'> 			steam_do_input_event(steam, input, data);</div><div class='ctx'> 		rcu_read_unlock();</div><div class='ctx'> 		break;</div><div class='del'>-	case STEAM_EV_DECK_INPUT_DATA:</div><div class='add'>+	case ID_CONTROLLER_DECK_STATE:</div><div class='ctx'> 		if (steam-&gt;client_opened)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		rcu_read_lock();</div><div class='hunk'>@@ -1393,7 +1630,7 @@ static int steam_raw_event(struct hid_device *hdev,</div><div class='ctx'> 			steam_do_deck_input_event(steam, input, data);</div><div class='ctx'> 		rcu_read_unlock();</div><div class='ctx'> 		break;</div><div class='del'>-	case STEAM_EV_CONNECT:</div><div class='add'>+	case ID_CONTROLLER_WIRELESS:</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The payload of this event is a single byte:</div><div class='ctx'> 		 *  0x01: disconnected.</div><div class='hunk'>@@ -1408,7 +1645,7 @@ static int steam_raw_event(struct hid_device *hdev,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='del'>-	case STEAM_EV_BATTERY:</div><div class='add'>+	case ID_CONTROLLER_STATUS:</div><div class='ctx'> 		if (steam-&gt;quirks &amp; STEAM_QUIRK_WIRELESS) {</div><div class='ctx'> 			rcu_read_lock();</div><div class='ctx'> 			battery = rcu_dereference(steam-&gt;battery);</div><div class='hunk'>@@ -1439,10 +1676,8 @@ static int steam_param_set_lizard_mode(const char *val,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;steam_devices_lock);</div><div class='ctx'> 	list_for_each_entry(steam, &amp;steam_devices, list) {</div><div class='del'>-		mutex_lock(&amp;steam-&gt;mutex);</div><div class='ctx'> 		if (!steam-&gt;client_opened)</div><div class='ctx'> 			steam_set_lizard_mode(steam, lizard_mode);</div><div class='del'>-		mutex_unlock(&amp;steam-&gt;mutex);</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;steam_devices_lock);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/hid/i2c-hid/i2c-hid-acpi.c b/drivers/hid/i2c-hid/i2c-hid-acpi.c<br/>index ac918a9ea8d3..1b49243adb16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-acpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/i2c-hid/i2c-hid-acpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-acpi.c</a></div><div class='hunk'>@@ -40,6 +40,11 @@ static const struct acpi_device_id i2c_hid_acpi_blacklist[] = {</div><div class='ctx'> 	 * ICN8505 controller, has a _CID of PNP0C50 but is not HID compatible.</div><div class='ctx'> 	 */</div><div class='ctx'> 	{ "CHPN0001" },</div><div class='add'>+	/*</div><div class='add'>+	 * The IDEA5002 ACPI device causes high interrupt usage and spurious</div><div class='add'>+	 * wakeups from suspend.</div><div class='add'>+	 */</div><div class='add'>+	{ "IDEA5002" },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hid/i2c-hid/i2c-hid-core.c b/drivers/hid/i2c-hid/i2c-hid-core.c<br/>index 2735cd585af0..90f316ae9819 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/i2c-hid/i2c-hid-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-core.c</a></div><div class='hunk'>@@ -44,12 +44,11 @@</div><div class='ctx'> #include "i2c-hid.h"</div><div class='ctx'> </div><div class='ctx'> /* quirks to control the device */</div><div class='del'>-#define I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV	BIT(0)</div><div class='del'>-#define I2C_HID_QUIRK_NO_IRQ_AFTER_RESET	BIT(1)</div><div class='del'>-#define I2C_HID_QUIRK_BOGUS_IRQ			BIT(4)</div><div class='del'>-#define I2C_HID_QUIRK_RESET_ON_RESUME		BIT(5)</div><div class='del'>-#define I2C_HID_QUIRK_BAD_INPUT_SIZE		BIT(6)</div><div class='del'>-#define I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET	BIT(7)</div><div class='add'>+#define I2C_HID_QUIRK_NO_IRQ_AFTER_RESET	BIT(0)</div><div class='add'>+#define I2C_HID_QUIRK_BOGUS_IRQ			BIT(1)</div><div class='add'>+#define I2C_HID_QUIRK_RESET_ON_RESUME		BIT(2)</div><div class='add'>+#define I2C_HID_QUIRK_BAD_INPUT_SIZE		BIT(3)</div><div class='add'>+#define I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET	BIT(4)</div><div class='ctx'> </div><div class='ctx'> /* Command opcodes */</div><div class='ctx'> #define I2C_HID_OPCODE_RESET			0x01</div><div class='hunk'>@@ -120,8 +119,6 @@ static const struct i2c_hid_quirks {</div><div class='ctx'> 	__u16 idProduct;</div><div class='ctx'> 	__u32 quirks;</div><div class='ctx'> } i2c_hid_quirks[] = {</div><div class='del'>-	{ USB_VENDOR_ID_WEIDA, HID_ANY_ID,</div><div class='del'>-		I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV },</div><div class='ctx'> 	{ I2C_VENDOR_ID_HANTICK, I2C_PRODUCT_ID_HANTICK_5288,</div><div class='ctx'> 		I2C_HID_QUIRK_NO_IRQ_AFTER_RESET },</div><div class='ctx'> 	{ I2C_VENDOR_ID_ITE, I2C_DEVICE_ID_ITE_VOYO_WINPAD_A15,</div><div class='hunk'>@@ -395,8 +392,7 @@ static int i2c_hid_set_power(struct i2c_hid *ihid, int power_state)</div><div class='ctx'> 	 * The call will get a return value (EREMOTEIO) but device will be</div><div class='ctx'> 	 * triggered and activated. After that, it goes like a normal device.</div><div class='ctx'> 	 */</div><div class='del'>-	if (power_state == I2C_HID_PWR_ON &amp;&amp;</div><div class='del'>-	    ihid-&gt;quirks &amp; I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV) {</div><div class='add'>+	if (power_state == I2C_HID_PWR_ON) {</div><div class='ctx'> 		ret = i2c_hid_set_power_command(ihid, I2C_HID_PWR_ON);</div><div class='ctx'> </div><div class='ctx'> 		/* Device was already activated */</div><div class='hunk'>@@ -426,12 +422,23 @@ set_pwr_exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int i2c_hid_execute_reset(struct i2c_hid *ihid)</div><div class='add'>+static int i2c_hid_start_hwreset(struct i2c_hid *ihid)</div><div class='ctx'> {</div><div class='ctx'> 	size_t length = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	i2c_hid_dbg(ihid, "resetting...\n");</div><div class='add'>+	i2c_hid_dbg(ihid, "%s\n", __func__);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This prevents sending feature reports while the device is</div><div class='add'>+	 * being reset. Otherwise we may lose the reset complete</div><div class='add'>+	 * interrupt.</div><div class='add'>+	 */</div><div class='add'>+	lockdep_assert_held(&amp;ihid-&gt;reset_lock);</div><div class='add'>+</div><div class='add'>+	ret = i2c_hid_set_power(ihid, I2C_HID_PWR_ON);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Prepare reset command. Command register goes first. */</div><div class='ctx'> 	*(__le16 *)ihid-&gt;cmdbuf = ihid-&gt;hdesc.wCommandRegister;</div><div class='hunk'>@@ -444,60 +451,40 @@ static int i2c_hid_execute_reset(struct i2c_hid *ihid)</div><div class='ctx'> </div><div class='ctx'> 	ret = i2c_hid_xfer(ihid, ihid-&gt;cmdbuf, length, NULL, 0);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(&amp;ihid-&gt;client-&gt;dev, "failed to reset device.\n");</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ihid-&gt;quirks &amp; I2C_HID_QUIRK_NO_IRQ_AFTER_RESET) {</div><div class='del'>-		msleep(100);</div><div class='del'>-		goto out;</div><div class='add'>+		dev_err(&amp;ihid-&gt;client-&gt;dev,</div><div class='add'>+			"failed to reset device: %d\n", ret);</div><div class='add'>+		goto err_clear_reset;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	i2c_hid_dbg(ihid, "%s: waiting...\n", __func__);</div><div class='del'>-	if (!wait_event_timeout(ihid-&gt;wait,</div><div class='del'>-				!test_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags),</div><div class='del'>-				msecs_to_jiffies(5000))) {</div><div class='del'>-		ret = -ENODATA;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-	i2c_hid_dbg(ihid, "%s: finished.\n", __func__);</div><div class='add'>+	return 0;</div><div class='ctx'> </div><div class='del'>-out:</div><div class='add'>+err_clear_reset:</div><div class='ctx'> 	clear_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags);</div><div class='add'>+	i2c_hid_set_power(ihid, I2C_HID_PWR_SLEEP);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int i2c_hid_hwreset(struct i2c_hid *ihid)</div><div class='add'>+static int i2c_hid_finish_hwreset(struct i2c_hid *ihid)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	i2c_hid_dbg(ihid, "%s\n", __func__);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * This prevents sending feature reports while the device is</div><div class='del'>-	 * being reset. Otherwise we may lose the reset complete</div><div class='del'>-	 * interrupt.</div><div class='del'>-	 */</div><div class='del'>-	mutex_lock(&amp;ihid-&gt;reset_lock);</div><div class='del'>-</div><div class='del'>-	ret = i2c_hid_set_power(ihid, I2C_HID_PWR_ON);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto out_unlock;</div><div class='add'>+	i2c_hid_dbg(ihid, "%s: waiting...\n", __func__);</div><div class='ctx'> </div><div class='del'>-	ret = i2c_hid_execute_reset(ihid);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;ihid-&gt;client-&gt;dev,</div><div class='del'>-			"failed to reset device: %d\n", ret);</div><div class='del'>-		i2c_hid_set_power(ihid, I2C_HID_PWR_SLEEP);</div><div class='del'>-		goto out_unlock;</div><div class='add'>+	if (ihid-&gt;quirks &amp; I2C_HID_QUIRK_NO_IRQ_AFTER_RESET) {</div><div class='add'>+		msleep(100);</div><div class='add'>+		clear_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags);</div><div class='add'>+	} else if (!wait_event_timeout(ihid-&gt;wait,</div><div class='add'>+				       !test_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags),</div><div class='add'>+				       msecs_to_jiffies(1000))) {</div><div class='add'>+		dev_warn(&amp;ihid-&gt;client-&gt;dev, "device did not ack reset within 1000 ms\n");</div><div class='add'>+		clear_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags);</div><div class='ctx'> 	}</div><div class='add'>+	i2c_hid_dbg(ihid, "%s: finished.\n", __func__);</div><div class='ctx'> </div><div class='ctx'> 	/* At least some SIS devices need this after reset */</div><div class='ctx'> 	if (!(ihid-&gt;quirks &amp; I2C_HID_QUIRK_NO_WAKEUP_AFTER_RESET))</div><div class='ctx'> 		ret = i2c_hid_set_power(ihid, I2C_HID_PWR_ON);</div><div class='ctx'> </div><div class='del'>-out_unlock:</div><div class='del'>-	mutex_unlock(&amp;ihid-&gt;reset_lock);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -729,11 +716,10 @@ static int i2c_hid_parse(struct hid_device *hid)</div><div class='ctx'> 	struct i2c_client *client = hid-&gt;driver_data;</div><div class='ctx'> 	struct i2c_hid *ihid = i2c_get_clientdata(client);</div><div class='ctx'> 	struct i2c_hid_desc *hdesc = &amp;ihid-&gt;hdesc;</div><div class='add'>+	char *rdesc = NULL, *use_override = NULL;</div><div class='ctx'> 	unsigned int rsize;</div><div class='del'>-	char *rdesc;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int tries = 3;</div><div class='del'>-	char *use_override;</div><div class='ctx'> </div><div class='ctx'> 	i2c_hid_dbg(ihid, "entering %s\n", __func__);</div><div class='ctx'> </div><div class='hunk'>@@ -743,14 +729,15 @@ static int i2c_hid_parse(struct hid_device *hid)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;ihid-&gt;reset_lock);</div><div class='ctx'> 	do {</div><div class='del'>-		ret = i2c_hid_hwreset(ihid);</div><div class='add'>+		ret = i2c_hid_start_hwreset(ihid);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			msleep(1000);</div><div class='ctx'> 	} while (tries-- &gt; 0 &amp;&amp; ret);</div><div class='ctx'> </div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto abort_reset;</div><div class='ctx'> </div><div class='ctx'> 	use_override = i2c_hid_get_dmi_hid_report_desc_override(client-&gt;name,</div><div class='ctx'> 								&amp;rsize);</div><div class='hunk'>@@ -762,8 +749,8 @@ static int i2c_hid_parse(struct hid_device *hid)</div><div class='ctx'> 		rdesc = kzalloc(rsize, GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 		if (!rdesc) {</div><div class='del'>-			dbg_hid("couldn't allocate rdesc memory\n");</div><div class='del'>-			return -ENOMEM;</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto abort_reset;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		i2c_hid_dbg(ihid, "asking HID report descriptor\n");</div><div class='hunk'>@@ -773,23 +760,34 @@ static int i2c_hid_parse(struct hid_device *hid)</div><div class='ctx'> 					    rdesc, rsize);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			hid_err(hid, "reading report descriptor failed\n");</div><div class='del'>-			kfree(rdesc);</div><div class='del'>-			return -EIO;</div><div class='add'>+			goto abort_reset;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Windows directly reads the report-descriptor after sending reset</div><div class='add'>+	 * and then waits for resets completion afterwards. Some touchpads</div><div class='add'>+	 * actually wait for the report-descriptor to be read before signalling</div><div class='add'>+	 * reset completion.</div><div class='add'>+	 */</div><div class='add'>+	ret = i2c_hid_finish_hwreset(ihid);</div><div class='add'>+abort_reset:</div><div class='add'>+	clear_bit(I2C_HID_RESET_PENDING, &amp;ihid-&gt;flags);</div><div class='add'>+	mutex_unlock(&amp;ihid-&gt;reset_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	i2c_hid_dbg(ihid, "Report Descriptor: %*ph\n", rsize, rdesc);</div><div class='ctx'> </div><div class='ctx'> 	ret = hid_parse_report(hid, rdesc, rsize);</div><div class='add'>+	if (ret)</div><div class='add'>+		dbg_hid("parsing report descriptor failed\n");</div><div class='add'>+</div><div class='add'>+out:</div><div class='ctx'> 	if (!use_override)</div><div class='ctx'> 		kfree(rdesc);</div><div class='ctx'> </div><div class='del'>-	if (ret) {</div><div class='del'>-		dbg_hid("parsing report descriptor failed\n");</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int i2c_hid_start(struct hid_device *hid)</div><div class='hunk'>@@ -987,10 +985,15 @@ static int i2c_hid_core_resume(struct i2c_hid *ihid)</div><div class='ctx'> 	 * However some ALPS touchpads generate IRQ storm without reset, so</div><div class='ctx'> 	 * let's still reset them here.</div><div class='ctx'> 	 */</div><div class='del'>-	if (ihid-&gt;quirks &amp; I2C_HID_QUIRK_RESET_ON_RESUME)</div><div class='del'>-		ret = i2c_hid_hwreset(ihid);</div><div class='del'>-	else</div><div class='add'>+	if (ihid-&gt;quirks &amp; I2C_HID_QUIRK_RESET_ON_RESUME) {</div><div class='add'>+		mutex_lock(&amp;ihid-&gt;reset_lock);</div><div class='add'>+		ret = i2c_hid_start_hwreset(ihid);</div><div class='add'>+		if (ret == 0)</div><div class='add'>+			ret = i2c_hid_finish_hwreset(ihid);</div><div class='add'>+		mutex_unlock(&amp;ihid-&gt;reset_lock);</div><div class='add'>+	} else {</div><div class='ctx'> 		ret = i2c_hid_set_power(ihid, I2C_HID_PWR_ON);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='head'>diff --git a/drivers/hid/i2c-hid/i2c-hid-of-elan.c b/drivers/hid/i2c-hid/i2c-hid-of-elan.c<br/>index 31abab57ad44..5b91fb106cfc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-of-elan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/i2c-hid/i2c-hid-of-elan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/i2c-hid/i2c-hid-of-elan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/i2c-hid/i2c-hid-of-elan.c</a></div><div class='hunk'>@@ -130,9 +130,17 @@ static const struct elan_i2c_hid_chip_data ilitek_ili9882t_chip_data = {</div><div class='ctx'> 	.main_supply_name = NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct elan_i2c_hid_chip_data ilitek_ili2901_chip_data = {</div><div class='add'>+	.post_power_delay_ms = 10,</div><div class='add'>+	.post_gpio_reset_on_delay_ms = 100,</div><div class='add'>+	.hid_descriptor_address = 0x0001,</div><div class='add'>+	.main_supply_name = "vcc33",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id elan_i2c_hid_of_match[] = {</div><div class='ctx'> 	{ .compatible = "elan,ekth6915", .data = &amp;elan_ekth6915_chip_data },</div><div class='ctx'> 	{ .compatible = "ilitek,ili9882t", .data = &amp;ilitek_ili9882t_chip_data },</div><div class='add'>+	{ .compatible = "ilitek,ili2901", .data = &amp;ilitek_ili2901_chip_data },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, elan_i2c_hid_of_match);</div><div class='head'>diff --git a/drivers/hid/intel-ish-hid/ipc/pci-ish.c b/drivers/hid/intel-ish-hid/ipc/pci-ish.c<br/>index 710fda5f19e1..65e7eeb2fa64 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ipc/pci-ish.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/intel-ish-hid/ipc/pci-ish.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ipc/pci-ish.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ipc/pci-ish.c</a></div><div class='hunk'>@@ -119,50 +119,6 @@ static inline bool ish_should_leave_d0i3(struct pci_dev *pdev)</div><div class='ctx'> 	return !pm_resume_via_firmware() || pdev-&gt;device == CHV_DEVICE_ID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int enable_gpe(struct device *dev)</div><div class='del'>-{</div><div class='del'>-#ifdef CONFIG_ACPI</div><div class='del'>-	acpi_status acpi_sts;</div><div class='del'>-	struct acpi_device *adev;</div><div class='del'>-	struct acpi_device_wakeup *wakeup;</div><div class='del'>-</div><div class='del'>-	adev = ACPI_COMPANION(dev);</div><div class='del'>-	if (!adev) {</div><div class='del'>-		dev_err(dev, "get acpi handle failed\n");</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-	wakeup = &amp;adev-&gt;wakeup;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Call acpi_disable_gpe(), so that reference count</div><div class='del'>-	 * gpe_event_info-&gt;runtime_count doesn't overflow.</div><div class='del'>-	 * When gpe_event_info-&gt;runtime_count = 0, the call</div><div class='del'>-	 * to acpi_disable_gpe() simply return.</div><div class='del'>-	 */</div><div class='del'>-	acpi_disable_gpe(wakeup-&gt;gpe_device, wakeup-&gt;gpe_number);</div><div class='del'>-</div><div class='del'>-	acpi_sts = acpi_enable_gpe(wakeup-&gt;gpe_device, wakeup-&gt;gpe_number);</div><div class='del'>-	if (ACPI_FAILURE(acpi_sts)) {</div><div class='del'>-		dev_err(dev, "enable ose_gpe failed\n");</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-#else</div><div class='del'>-	return -ENODEV;</div><div class='del'>-#endif</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void enable_pme_wake(struct pci_dev *pdev)</div><div class='del'>-{</div><div class='del'>-	if ((pci_pme_capable(pdev, PCI_D0) ||</div><div class='del'>-	     pci_pme_capable(pdev, PCI_D3hot) ||</div><div class='del'>-	     pci_pme_capable(pdev, PCI_D3cold)) &amp;&amp; !enable_gpe(&amp;pdev-&gt;dev)) {</div><div class='del'>-		pci_pme_active(pdev, true);</div><div class='del'>-		dev_dbg(&amp;pdev-&gt;dev, "ish ipc driver pme wake enabled\n");</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * ish_probe() - PCI driver probe callback</div><div class='ctx'>  * @pdev:	pci device</div><div class='hunk'>@@ -233,7 +189,7 @@ static int ish_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> </div><div class='ctx'> 	/* Enable PME for EHL */</div><div class='ctx'> 	if (pdev-&gt;device == EHL_Ax_DEVICE_ID)</div><div class='del'>-		enable_pme_wake(pdev);</div><div class='add'>+		device_init_wakeup(dev, true);</div><div class='ctx'> </div><div class='ctx'> 	ret = ish_init(ishtp);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -256,6 +212,19 @@ static void ish_remove(struct pci_dev *pdev)</div><div class='ctx'> 	ish_device_disable(ishtp_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ish_shutdown() - PCI driver shutdown callback</div><div class='add'>+ * @pdev:	pci device</div><div class='add'>+ *</div><div class='add'>+ * This function sets up wakeup for S5</div><div class='add'>+ */</div><div class='add'>+static void ish_shutdown(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	if (pdev-&gt;device == EHL_Ax_DEVICE_ID)</div><div class='add'>+		pci_prepare_to_sleep(pdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct device __maybe_unused *ish_resume_device;</div><div class='ctx'> </div><div class='ctx'> /* 50ms to get resume response */</div><div class='hunk'>@@ -378,13 +347,6 @@ static int __maybe_unused ish_resume(struct device *device)</div><div class='ctx'> 	struct pci_dev *pdev = to_pci_dev(device);</div><div class='ctx'> 	struct ishtp_device *dev = pci_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	/* add this to finish power flow for EHL */</div><div class='del'>-	if (dev-&gt;pdev-&gt;device == EHL_Ax_DEVICE_ID) {</div><div class='del'>-		pci_set_power_state(pdev, PCI_D0);</div><div class='del'>-		enable_pme_wake(pdev);</div><div class='del'>-		dev_dbg(dev-&gt;devc, "set power state to D0 for ehl\n");</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	ish_resume_device = device;</div><div class='ctx'> 	dev-&gt;resume_flag = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -400,6 +362,7 @@ static struct pci_driver ish_driver = {</div><div class='ctx'> 	.id_table = ish_pci_tbl,</div><div class='ctx'> 	.probe = ish_probe,</div><div class='ctx'> 	.remove = ish_remove,</div><div class='add'>+	.shutdown = ish_shutdown,</div><div class='ctx'> 	.driver.pm = &amp;ish_pm_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hid/intel-ish-hid/ishtp-fw-loader.c b/drivers/hid/intel-ish-hid/ishtp-fw-loader.c<br/>index 16aa030af845..e157863a8b25 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp-fw-loader.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/intel-ish-hid/ishtp-fw-loader.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp-fw-loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp-fw-loader.c</a></div><div class='hunk'>@@ -840,43 +840,22 @@ static void load_fw_from_host_handler(struct work_struct *work)</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 for success, negative error code for failure</div><div class='ctx'>  */</div><div class='del'>-static int loader_init(struct ishtp_cl *loader_ishtp_cl, int reset)</div><div class='add'>+static int loader_init(struct ishtp_cl *loader_ishtp_cl, bool reset)</div><div class='ctx'> {</div><div class='ctx'> 	int rv;</div><div class='del'>-	struct ishtp_fw_client *fw_client;</div><div class='ctx'> 	struct ishtp_cl_data *client_data =</div><div class='ctx'> 		ishtp_get_client_data(loader_ishtp_cl);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(cl_data_to_dev(client_data), "reset flag: %d\n", reset);</div><div class='ctx'> </div><div class='del'>-	rv = ishtp_cl_link(loader_ishtp_cl);</div><div class='del'>-	if (rv &lt; 0) {</div><div class='del'>-		dev_err(cl_data_to_dev(client_data), "ishtp_cl_link failed\n");</div><div class='del'>-		return rv;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Connect to firmware client */</div><div class='del'>-	ishtp_set_tx_ring_size(loader_ishtp_cl, LOADER_CL_TX_RING_SIZE);</div><div class='del'>-	ishtp_set_rx_ring_size(loader_ishtp_cl, LOADER_CL_RX_RING_SIZE);</div><div class='del'>-</div><div class='del'>-	fw_client =</div><div class='del'>-		ishtp_fw_cl_get_client(ishtp_get_ishtp_device(loader_ishtp_cl),</div><div class='del'>-				       &amp;loader_ishtp_id_table[0].guid);</div><div class='del'>-	if (!fw_client) {</div><div class='del'>-		dev_err(cl_data_to_dev(client_data),</div><div class='del'>-			"ISH client uuid not found\n");</div><div class='del'>-		rv = -ENOENT;</div><div class='del'>-		goto err_cl_unlink;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ishtp_cl_set_fw_client_id(loader_ishtp_cl,</div><div class='del'>-				  ishtp_get_fw_client_id(fw_client));</div><div class='del'>-	ishtp_set_connection_state(loader_ishtp_cl, ISHTP_CL_CONNECTING);</div><div class='del'>-</div><div class='del'>-	rv = ishtp_cl_connect(loader_ishtp_cl);</div><div class='add'>+	rv = ishtp_cl_establish_connection(loader_ishtp_cl,</div><div class='add'>+					   &amp;loader_ishtp_id_table[0].guid,</div><div class='add'>+					   LOADER_CL_TX_RING_SIZE,</div><div class='add'>+					   LOADER_CL_RX_RING_SIZE,</div><div class='add'>+					   reset);</div><div class='ctx'> 	if (rv &lt; 0) {</div><div class='ctx'> 		dev_err(cl_data_to_dev(client_data), "Client connect fail\n");</div><div class='del'>-		goto err_cl_unlink;</div><div class='add'>+		goto err_cl_disconnect;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(cl_data_to_dev(client_data), "Client connected\n");</div><div class='hunk'>@@ -885,17 +864,14 @@ static int loader_init(struct ishtp_cl *loader_ishtp_cl, int reset)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err_cl_unlink:</div><div class='del'>-	ishtp_cl_unlink(loader_ishtp_cl);</div><div class='add'>+err_cl_disconnect:</div><div class='add'>+	ishtp_cl_destroy_connection(loader_ishtp_cl, reset);</div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void loader_deinit(struct ishtp_cl *loader_ishtp_cl)</div><div class='ctx'> {</div><div class='del'>-	ishtp_set_connection_state(loader_ishtp_cl, ISHTP_CL_DISCONNECTING);</div><div class='del'>-	ishtp_cl_disconnect(loader_ishtp_cl);</div><div class='del'>-	ishtp_cl_unlink(loader_ishtp_cl);</div><div class='del'>-	ishtp_cl_flush_queues(loader_ishtp_cl);</div><div class='add'>+	ishtp_cl_destroy_connection(loader_ishtp_cl, false);</div><div class='ctx'> </div><div class='ctx'> 	/* Disband and free all Tx and Rx client-level rings */</div><div class='ctx'> 	ishtp_cl_free(loader_ishtp_cl);</div><div class='hunk'>@@ -914,19 +890,7 @@ static void reset_handler(struct work_struct *work)</div><div class='ctx'> 	loader_ishtp_cl = client_data-&gt;loader_ishtp_cl;</div><div class='ctx'> 	cl_device = client_data-&gt;cl_device;</div><div class='ctx'> </div><div class='del'>-	/* Unlink, flush queues &amp; start again */</div><div class='del'>-	ishtp_cl_unlink(loader_ishtp_cl);</div><div class='del'>-	ishtp_cl_flush_queues(loader_ishtp_cl);</div><div class='del'>-	ishtp_cl_free(loader_ishtp_cl);</div><div class='del'>-</div><div class='del'>-	loader_ishtp_cl = ishtp_cl_allocate(cl_device);</div><div class='del'>-	if (!loader_ishtp_cl)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	ishtp_set_drvdata(cl_device, loader_ishtp_cl);</div><div class='del'>-	ishtp_set_client_data(loader_ishtp_cl, client_data);</div><div class='del'>-	client_data-&gt;loader_ishtp_cl = loader_ishtp_cl;</div><div class='del'>-	client_data-&gt;cl_device = cl_device;</div><div class='add'>+	ishtp_cl_destroy_connection(loader_ishtp_cl, true);</div><div class='ctx'> </div><div class='ctx'> 	rv = loader_init(loader_ishtp_cl, 1);</div><div class='ctx'> 	if (rv &lt; 0) {</div><div class='hunk'>@@ -974,7 +938,7 @@ static int loader_ishtp_cl_probe(struct ishtp_cl_device *cl_device)</div><div class='ctx'> 	INIT_WORK(&amp;client_data-&gt;work_fw_load,</div><div class='ctx'> 		  load_fw_from_host_handler);</div><div class='ctx'> </div><div class='del'>-	rv = loader_init(loader_ishtp_cl, 0);</div><div class='add'>+	rv = loader_init(loader_ishtp_cl, false);</div><div class='ctx'> 	if (rv &lt; 0) {</div><div class='ctx'> 		ishtp_cl_free(loader_ishtp_cl);</div><div class='ctx'> 		return rv;</div><div class='head'>diff --git a/drivers/hid/intel-ish-hid/ishtp-hid-client.c b/drivers/hid/intel-ish-hid/ishtp-hid-client.c<br/>index e3d70c5460e9..fbd4f8ea1951 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp-hid-client.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/intel-ish-hid/ishtp-hid-client.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp-hid-client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp-hid-client.c</a></div><div class='hunk'>@@ -639,47 +639,26 @@ static int ishtp_get_report_descriptor(struct ishtp_cl *hid_ishtp_cl,</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 on success, non zero on error</div><div class='ctx'>  */</div><div class='del'>-static int hid_ishtp_cl_init(struct ishtp_cl *hid_ishtp_cl, int reset)</div><div class='add'>+static int hid_ishtp_cl_init(struct ishtp_cl *hid_ishtp_cl, bool reset)</div><div class='ctx'> {</div><div class='del'>-	struct ishtp_device *dev;</div><div class='ctx'> 	struct ishtp_cl_data *client_data = ishtp_get_client_data(hid_ishtp_cl);</div><div class='del'>-	struct ishtp_fw_client *fw_client;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int rv;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(cl_data_to_dev(client_data), "%s\n", __func__);</div><div class='ctx'> 	hid_ishtp_trace(client_data,  "%s reset flag: %d\n", __func__, reset);</div><div class='ctx'> </div><div class='del'>-	rv = ishtp_cl_link(hid_ishtp_cl);</div><div class='del'>-	if (rv) {</div><div class='del'>-		dev_err(cl_data_to_dev(client_data),</div><div class='del'>-			"ishtp_cl_link failed\n");</div><div class='del'>-		return	-ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	client_data-&gt;init_done = 0;</div><div class='ctx'> </div><div class='del'>-	dev = ishtp_get_ishtp_device(hid_ishtp_cl);</div><div class='del'>-</div><div class='del'>-	/* Connect to FW client */</div><div class='del'>-	ishtp_set_tx_ring_size(hid_ishtp_cl, HID_CL_TX_RING_SIZE);</div><div class='del'>-	ishtp_set_rx_ring_size(hid_ishtp_cl, HID_CL_RX_RING_SIZE);</div><div class='del'>-</div><div class='del'>-	fw_client = ishtp_fw_cl_get_client(dev, &amp;hid_ishtp_id_table[0].guid);</div><div class='del'>-	if (!fw_client) {</div><div class='del'>-		dev_err(cl_data_to_dev(client_data),</div><div class='del'>-			"ish client uuid not found\n");</div><div class='del'>-		return -ENOENT;</div><div class='del'>-	}</div><div class='del'>-	ishtp_cl_set_fw_client_id(hid_ishtp_cl,</div><div class='del'>-				  ishtp_get_fw_client_id(fw_client));</div><div class='del'>-	ishtp_set_connection_state(hid_ishtp_cl, ISHTP_CL_CONNECTING);</div><div class='del'>-</div><div class='del'>-	rv = ishtp_cl_connect(hid_ishtp_cl);</div><div class='add'>+	rv = ishtp_cl_establish_connection(hid_ishtp_cl,</div><div class='add'>+					   &amp;hid_ishtp_id_table[0].guid,</div><div class='add'>+					   HID_CL_TX_RING_SIZE,</div><div class='add'>+					   HID_CL_RX_RING_SIZE,</div><div class='add'>+					   reset);</div><div class='ctx'> 	if (rv) {</div><div class='ctx'> 		dev_err(cl_data_to_dev(client_data),</div><div class='ctx'> 			"client connect fail\n");</div><div class='del'>-		goto err_cl_unlink;</div><div class='add'>+		goto err_cl_disconnect;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	hid_ishtp_trace(client_data,  "%s client connected\n", __func__);</div><div class='hunk'>@@ -723,10 +702,7 @@ static int hid_ishtp_cl_init(struct ishtp_cl *hid_ishtp_cl, int reset)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_cl_disconnect:</div><div class='del'>-	ishtp_set_connection_state(hid_ishtp_cl, ISHTP_CL_DISCONNECTING);</div><div class='del'>-	ishtp_cl_disconnect(hid_ishtp_cl);</div><div class='del'>-err_cl_unlink:</div><div class='del'>-	ishtp_cl_unlink(hid_ishtp_cl);</div><div class='add'>+	ishtp_cl_destroy_connection(hid_ishtp_cl, reset);</div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -738,8 +714,7 @@ err_cl_unlink:</div><div class='ctx'>  */</div><div class='ctx'> static void hid_ishtp_cl_deinit(struct ishtp_cl *hid_ishtp_cl)</div><div class='ctx'> {</div><div class='del'>-	ishtp_cl_unlink(hid_ishtp_cl);</div><div class='del'>-	ishtp_cl_flush_queues(hid_ishtp_cl);</div><div class='add'>+	ishtp_cl_destroy_connection(hid_ishtp_cl, false);</div><div class='ctx'> </div><div class='ctx'> 	/* disband and free all Tx and Rx client-level rings */</div><div class='ctx'> 	ishtp_cl_free(hid_ishtp_cl);</div><div class='hunk'>@@ -749,33 +724,23 @@ static void hid_ishtp_cl_reset_handler(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct ishtp_cl_data *client_data;</div><div class='ctx'> 	struct ishtp_cl *hid_ishtp_cl;</div><div class='del'>-	struct ishtp_cl_device *cl_device;</div><div class='ctx'> 	int retry;</div><div class='ctx'> 	int rv;</div><div class='ctx'> </div><div class='ctx'> 	client_data = container_of(work, struct ishtp_cl_data, work);</div><div class='ctx'> </div><div class='ctx'> 	hid_ishtp_cl = client_data-&gt;hid_ishtp_cl;</div><div class='del'>-	cl_device = client_data-&gt;cl_device;</div><div class='ctx'> </div><div class='ctx'> 	hid_ishtp_trace(client_data, "%s hid_ishtp_cl %p\n", __func__,</div><div class='ctx'> 			hid_ishtp_cl);</div><div class='ctx'> 	dev_dbg(ishtp_device(client_data-&gt;cl_device), "%s\n", __func__);</div><div class='ctx'> </div><div class='del'>-	hid_ishtp_cl_deinit(hid_ishtp_cl);</div><div class='del'>-</div><div class='del'>-	hid_ishtp_cl = ishtp_cl_allocate(cl_device);</div><div class='del'>-	if (!hid_ishtp_cl)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	ishtp_set_drvdata(cl_device, hid_ishtp_cl);</div><div class='del'>-	ishtp_set_client_data(hid_ishtp_cl, client_data);</div><div class='del'>-	client_data-&gt;hid_ishtp_cl = hid_ishtp_cl;</div><div class='add'>+	ishtp_cl_destroy_connection(hid_ishtp_cl, true);</div><div class='ctx'> </div><div class='ctx'> 	client_data-&gt;num_hid_devices = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (retry = 0; retry &lt; 3; ++retry) {</div><div class='del'>-		rv = hid_ishtp_cl_init(hid_ishtp_cl, 1);</div><div class='add'>+		rv = hid_ishtp_cl_init(hid_ishtp_cl, true);</div><div class='ctx'> 		if (!rv)</div><div class='ctx'> 			break;</div><div class='ctx'> 		dev_err(cl_data_to_dev(client_data), "Retry reset init\n");</div><div class='hunk'>@@ -841,7 +806,7 @@ static int hid_ishtp_cl_probe(struct ishtp_cl_device *cl_device)</div><div class='ctx'> </div><div class='ctx'> 	ishtp_hid_print_trace = ishtp_trace_callback(cl_device);</div><div class='ctx'> </div><div class='del'>-	rv = hid_ishtp_cl_init(hid_ishtp_cl, 0);</div><div class='add'>+	rv = hid_ishtp_cl_init(hid_ishtp_cl, false);</div><div class='ctx'> 	if (rv) {</div><div class='ctx'> 		ishtp_cl_free(hid_ishtp_cl);</div><div class='ctx'> 		return rv;</div><div class='hunk'>@@ -868,11 +833,9 @@ static void hid_ishtp_cl_remove(struct ishtp_cl_device *cl_device)</div><div class='ctx'> 			hid_ishtp_cl);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(ishtp_device(cl_device), "%s\n", __func__);</div><div class='del'>-	ishtp_set_connection_state(hid_ishtp_cl, ISHTP_CL_DISCONNECTING);</div><div class='del'>-	ishtp_cl_disconnect(hid_ishtp_cl);</div><div class='add'>+	hid_ishtp_cl_deinit(hid_ishtp_cl);</div><div class='ctx'> 	ishtp_put_device(cl_device);</div><div class='ctx'> 	ishtp_hid_remove(client_data);</div><div class='del'>-	hid_ishtp_cl_deinit(hid_ishtp_cl);</div><div class='ctx'> </div><div class='ctx'> 	hid_ishtp_cl = NULL;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hid/intel-ish-hid/ishtp/bus.c b/drivers/hid/intel-ish-hid/ishtp/bus.c<br/>index 7fc738a22375..aa6cb033bb06 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp/bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/intel-ish-hid/ishtp/bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp/bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp/bus.c</a></div><div class='hunk'>@@ -378,7 +378,7 @@ static const struct dev_pm_ops ishtp_cl_bus_dev_pm_ops = {</div><div class='ctx'> 	.restore = ishtp_cl_device_resume,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct bus_type ishtp_cl_bus_type = {</div><div class='add'>+static const struct bus_type ishtp_cl_bus_type = {</div><div class='ctx'> 	.name		= "ishtp",</div><div class='ctx'> 	.dev_groups	= ishtp_cl_dev_groups,</div><div class='ctx'> 	.probe		= ishtp_cl_device_probe,</div><div class='head'>diff --git a/drivers/hid/intel-ish-hid/ishtp/client.c b/drivers/hid/intel-ish-hid/ishtp/client.c<br/>index 2d92fc129ce4..82c907f01bd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp/client.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/intel-ish-hid/ishtp/client.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/intel-ish-hid/ishtp/client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/intel-ish-hid/ishtp/client.c</a></div><div class='hunk'>@@ -339,16 +339,17 @@ static bool ishtp_cl_is_other_connecting(struct ishtp_cl *cl)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ishtp_cl_connect() - Send connect request to firmware</div><div class='add'>+ * ishtp_cl_connect_to_fw() - Send connect request to firmware</div><div class='ctx'>  * @cl: client device instance</div><div class='ctx'>  *</div><div class='del'>- * Send a connect request for a client to firmware. If successful it will</div><div class='del'>- * RX and TX ring buffers</div><div class='add'>+ * Send a connect request to the firmware and wait for firmware response.</div><div class='add'>+ * If there is successful connection response from the firmware, change</div><div class='add'>+ * client state to ISHTP_CL_CONNECTED, and bind client to related</div><div class='add'>+ * firmware client_id.</div><div class='ctx'>  *</div><div class='del'>- * Return: 0 if successful connect response from the firmware and able</div><div class='del'>- * to bind and allocate ring buffers or error code on failure</div><div class='add'>+ * Return: 0 for success and error code on failure</div><div class='ctx'>  */</div><div class='del'>-int ishtp_cl_connect(struct ishtp_cl *cl)</div><div class='add'>+static int ishtp_cl_connect_to_fw(struct ishtp_cl *cl)</div><div class='ctx'> {</div><div class='ctx'> 	struct ishtp_device *dev;</div><div class='ctx'> 	int rets;</div><div class='hunk'>@@ -358,8 +359,6 @@ int ishtp_cl_connect(struct ishtp_cl *cl)</div><div class='ctx'> </div><div class='ctx'> 	dev = cl-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	dev-&gt;print_log(dev, "%s() current_state = %d\n", __func__, cl-&gt;state);</div><div class='del'>-</div><div class='ctx'> 	if (ishtp_cl_is_other_connecting(cl)) {</div><div class='ctx'> 		dev-&gt;print_log(dev, "%s() Busy\n", __func__);</div><div class='ctx'> 		return	-EBUSY;</div><div class='hunk'>@@ -405,6 +404,38 @@ int ishtp_cl_connect(struct ishtp_cl *cl)</div><div class='ctx'> 		return rets;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return rets;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ishtp_cl_connect() - Build connection with firmware</div><div class='add'>+ * @cl: client device instance</div><div class='add'>+ *</div><div class='add'>+ * Call ishtp_cl_connect_to_fw() to connect and bind to firmware. If successful,</div><div class='add'>+ * allocate RX and TX ring buffers, and start flow control with firmware to</div><div class='add'>+ * start communication.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 if there is successful connection to the firmware, allocate</div><div class='add'>+ * ring buffers.</div><div class='add'>+ */</div><div class='add'>+int ishtp_cl_connect(struct ishtp_cl *cl)</div><div class='add'>+{</div><div class='add'>+	struct ishtp_device *dev;</div><div class='add'>+	int rets;</div><div class='add'>+</div><div class='add'>+	if (!cl || !cl-&gt;dev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	dev = cl-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev-&gt;print_log(dev, "%s() current_state = %d\n", __func__, cl-&gt;state);</div><div class='add'>+</div><div class='add'>+	rets = ishtp_cl_connect_to_fw(cl);</div><div class='add'>+	if (rets) {</div><div class='add'>+		dev-&gt;print_log(dev, "%s() Connect to fw failed\n", __func__);</div><div class='add'>+		return rets;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rets = ishtp_cl_alloc_rx_ring(cl);</div><div class='ctx'> 	if (rets) {</div><div class='ctx'> 		dev-&gt;print_log(dev, "%s() Alloc RX ring failed\n", __func__);</div><div class='hunk'>@@ -422,16 +453,148 @@ int ishtp_cl_connect(struct ishtp_cl *cl)</div><div class='ctx'> 		return rets;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Upon successful connection and allocation, emit flow-control */</div><div class='add'>+	/*</div><div class='add'>+	 * Upon successful connection and allocation, start flow-control.</div><div class='add'>+	 */</div><div class='ctx'> 	rets = ishtp_cl_read_start(cl);</div><div class='ctx'> </div><div class='del'>-	dev-&gt;print_log(dev, "%s() successful\n", __func__);</div><div class='del'>-</div><div class='ctx'> 	return rets;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(ishtp_cl_connect);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ishtp_cl_establish_connection() - Establish connection with the firmware</div><div class='add'>+ * @cl: client device instance</div><div class='add'>+ * @uuid: uuid of the client to search</div><div class='add'>+ * @tx_size: TX ring buffer size</div><div class='add'>+ * @rx_size: RX ring buffer size</div><div class='add'>+ * @reset: true if called for reset connection, otherwise for first connection</div><div class='add'>+ *</div><div class='add'>+ * This is a helper function for client driver to build connection with firmware.</div><div class='add'>+ * If it's first time connecting to the firmware, set reset to false, this</div><div class='add'>+ * function will link client to bus, find client id and send connect request to</div><div class='add'>+ * the firmware.</div><div class='add'>+ *</div><div class='add'>+ * If it's called for reset handler where client lost connection after</div><div class='add'>+ * firmware reset, set reset to true, this function will reinit client state and</div><div class='add'>+ * establish connection again. In this case, this function reuses current client</div><div class='add'>+ * structure and ring buffers to avoid allocation failure and memory fragments.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 for successful connection with the firmware,</div><div class='add'>+ * or error code on failure</div><div class='add'>+ */</div><div class='add'>+int ishtp_cl_establish_connection(struct ishtp_cl *cl, const guid_t *uuid,</div><div class='add'>+				  int tx_size, int rx_size, bool reset)</div><div class='add'>+{</div><div class='add'>+	struct ishtp_device *dev;</div><div class='add'>+	struct ishtp_fw_client *fw_client;</div><div class='add'>+	int rets;</div><div class='add'>+</div><div class='add'>+	if (!cl || !cl-&gt;dev)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	dev = cl-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ishtp_set_connection_state(cl, ISHTP_CL_INITIALIZING);</div><div class='add'>+</div><div class='add'>+	/* reinit ishtp_cl structure if call for reset */</div><div class='add'>+	if (reset) {</div><div class='add'>+		cl-&gt;host_client_id = 0;</div><div class='add'>+		cl-&gt;fw_client_id = 0;</div><div class='add'>+		cl-&gt;ishtp_flow_ctrl_creds = 0;</div><div class='add'>+		cl-&gt;out_flow_ctrl_creds = 0;</div><div class='add'>+</div><div class='add'>+		cl-&gt;last_tx_path = CL_TX_PATH_IPC;</div><div class='add'>+		cl-&gt;last_dma_acked = 1;</div><div class='add'>+		cl-&gt;last_dma_addr = NULL;</div><div class='add'>+		cl-&gt;last_ipc_acked = 1;</div><div class='add'>+</div><div class='add'>+		cl-&gt;sending = 0;</div><div class='add'>+		cl-&gt;err_send_msg = 0;</div><div class='add'>+		cl-&gt;err_send_fc = 0;</div><div class='add'>+</div><div class='add'>+		cl-&gt;send_msg_cnt_ipc = 0;</div><div class='add'>+		cl-&gt;send_msg_cnt_dma = 0;</div><div class='add'>+		cl-&gt;recv_msg_cnt_ipc = 0;</div><div class='add'>+		cl-&gt;recv_msg_cnt_dma = 0;</div><div class='add'>+		cl-&gt;recv_msg_num_frags = 0;</div><div class='add'>+		cl-&gt;ishtp_flow_ctrl_cnt = 0;</div><div class='add'>+		cl-&gt;out_flow_ctrl_cnt = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* link to bus */</div><div class='add'>+	rets = ishtp_cl_link(cl);</div><div class='add'>+	if (rets) {</div><div class='add'>+		dev-&gt;print_log(dev, "%s() ishtp_cl_link failed\n", __func__);</div><div class='add'>+		return rets;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* find firmware client */</div><div class='add'>+	fw_client = ishtp_fw_cl_get_client(dev, uuid);</div><div class='add'>+	if (!fw_client) {</div><div class='add'>+		dev-&gt;print_log(dev,</div><div class='add'>+			       "%s() ish client uuid not found\n", __func__);</div><div class='add'>+		return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ishtp_set_tx_ring_size(cl, tx_size);</div><div class='add'>+	ishtp_set_rx_ring_size(cl, rx_size);</div><div class='add'>+</div><div class='add'>+	ishtp_cl_set_fw_client_id(cl, ishtp_get_fw_client_id(fw_client));</div><div class='add'>+</div><div class='add'>+	ishtp_set_connection_state(cl, ISHTP_CL_CONNECTING);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * For reset case, not allocate tx/rx ring buffer which are already</div><div class='add'>+	 * done in ishtp_cl_connect() during first connection.</div><div class='add'>+	 */</div><div class='add'>+	if (reset) {</div><div class='add'>+		rets = ishtp_cl_connect_to_fw(cl);</div><div class='add'>+		if (!rets)</div><div class='add'>+			rets = ishtp_cl_read_start(cl);</div><div class='add'>+		else</div><div class='add'>+			dev-&gt;print_log(dev,</div><div class='add'>+				"%s() connect to fw failed\n", __func__);</div><div class='add'>+	} else {</div><div class='add'>+		rets = ishtp_cl_connect(cl);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return rets;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(ishtp_cl_establish_connection);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ishtp_cl_destroy_connection() - Disconnect with the firmware</div><div class='add'>+ * @cl: client device instance</div><div class='add'>+ * @reset: true if called for firmware reset, false for normal disconnection</div><div class='add'>+ *</div><div class='add'>+ * This is a helper function for client driver to disconnect with firmware,</div><div class='add'>+ * unlink to bus and flush message queue.</div><div class='add'>+ */</div><div class='add'>+void ishtp_cl_destroy_connection(struct ishtp_cl *cl, bool reset)</div><div class='add'>+{</div><div class='add'>+	if (!cl)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (reset) {</div><div class='add'>+		/*</div><div class='add'>+		 * For reset case, connection is already lost during fw reset.</div><div class='add'>+		 * Just set state to DISCONNECTED is enough.</div><div class='add'>+		 */</div><div class='add'>+		ishtp_set_connection_state(cl, ISHTP_CL_DISCONNECTED);</div><div class='add'>+	} else {</div><div class='add'>+		if (cl-&gt;state != ISHTP_CL_DISCONNECTED) {</div><div class='add'>+			ishtp_set_connection_state(cl, ISHTP_CL_DISCONNECTING);</div><div class='add'>+			ishtp_cl_disconnect(cl);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ishtp_cl_unlink(cl);</div><div class='add'>+	ishtp_cl_flush_queues(cl);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(ishtp_cl_destroy_connection);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ishtp_cl_read_start() - Prepare to read client message</div><div class='ctx'>  * @cl: client device instance</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c<br/>index 4588d2cd4ea4..a54c7995b9be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/uhid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/uhid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/uhid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/uhid.c</a></div><div class='hunk'>@@ -490,7 +490,7 @@ static int uhid_dev_create2(struct uhid_device *uhid,</div><div class='ctx'> 			    const struct uhid_event *ev)</div><div class='ctx'> {</div><div class='ctx'> 	struct hid_device *hid;</div><div class='del'>-	size_t rd_size, len;</div><div class='add'>+	size_t rd_size;</div><div class='ctx'> 	void *rd_data;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -514,13 +514,12 @@ static int uhid_dev_create2(struct uhid_device *uhid,</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* @hid is zero-initialized, strncpy() is correct, strlcpy() not */</div><div class='del'>-	len = min(sizeof(hid-&gt;name), sizeof(ev-&gt;u.create2.name)) - 1;</div><div class='del'>-	strncpy(hid-&gt;name, ev-&gt;u.create2.name, len);</div><div class='del'>-	len = min(sizeof(hid-&gt;phys), sizeof(ev-&gt;u.create2.phys)) - 1;</div><div class='del'>-	strncpy(hid-&gt;phys, ev-&gt;u.create2.phys, len);</div><div class='del'>-	len = min(sizeof(hid-&gt;uniq), sizeof(ev-&gt;u.create2.uniq)) - 1;</div><div class='del'>-	strncpy(hid-&gt;uniq, ev-&gt;u.create2.uniq, len);</div><div class='add'>+	BUILD_BUG_ON(sizeof(hid-&gt;name) != sizeof(ev-&gt;u.create2.name));</div><div class='add'>+	strscpy(hid-&gt;name, ev-&gt;u.create2.name, sizeof(hid-&gt;name));</div><div class='add'>+	BUILD_BUG_ON(sizeof(hid-&gt;phys) != sizeof(ev-&gt;u.create2.phys));</div><div class='add'>+	strscpy(hid-&gt;phys, ev-&gt;u.create2.phys, sizeof(hid-&gt;phys));</div><div class='add'>+	BUILD_BUG_ON(sizeof(hid-&gt;uniq) != sizeof(ev-&gt;u.create2.uniq));</div><div class='add'>+	strscpy(hid-&gt;uniq, ev-&gt;u.create2.uniq, sizeof(hid-&gt;uniq));</div><div class='ctx'> </div><div class='ctx'> 	hid-&gt;ll_driver = &amp;uhid_hid_driver;</div><div class='ctx'> 	hid-&gt;bus = ev-&gt;u.create2.bus;</div><div class='head'>diff --git a/drivers/hid/wacom.h b/drivers/hid/wacom.h<br/>index 166a76c9bcad..77c5fb26cd14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/wacom.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/wacom.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/wacom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom.h</a></div><div class='hunk'>@@ -164,6 +164,7 @@ struct wacom {</div><div class='ctx'> 	struct work_struct battery_work;</div><div class='ctx'> 	struct work_struct remote_work;</div><div class='ctx'> 	struct delayed_work init_work;</div><div class='add'>+	struct delayed_work aes_battery_work;</div><div class='ctx'> 	struct wacom_remote *remote;</div><div class='ctx'> 	struct work_struct mode_change_work;</div><div class='ctx'> 	struct timer_list idleprox_timer;</div><div class='head'>diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c<br/>index 3f704b8072e8..b613f11ed949 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/wacom_sys.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/wacom_sys.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/wacom_sys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_sys.c</a></div><div class='hunk'>@@ -1813,6 +1813,13 @@ static void wacom_destroy_battery(struct wacom *wacom)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void wacom_aes_battery_handler(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct wacom *wacom = container_of(work, struct wacom, aes_battery_work.work);</div><div class='add'>+</div><div class='add'>+	wacom_destroy_battery(wacom);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static ssize_t wacom_show_speed(struct device *dev,</div><div class='ctx'> 				struct device_attribute</div><div class='ctx'> 				*attr, char *buf)</div><div class='hunk'>@@ -2794,6 +2801,7 @@ static int wacom_probe(struct hid_device *hdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;wacom-&gt;lock);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;wacom-&gt;init_work, wacom_init_work);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;wacom-&gt;aes_battery_work, wacom_aes_battery_handler);</div><div class='ctx'> 	INIT_WORK(&amp;wacom-&gt;wireless_work, wacom_wireless_work);</div><div class='ctx'> 	INIT_WORK(&amp;wacom-&gt;battery_work, wacom_battery_work);</div><div class='ctx'> 	INIT_WORK(&amp;wacom-&gt;remote_work, wacom_remote_work);</div><div class='head'>diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c<br/>index 471db78dbbf0..da8a01fedd39 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/wacom_wac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/wacom_wac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/wacom_wac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_wac.c</a></div><div class='hunk'>@@ -2528,11 +2528,12 @@ static void wacom_wac_pen_report(struct hid_device *hdev,</div><div class='ctx'> 	struct input_dev *input = wacom_wac-&gt;pen_input;</div><div class='ctx'> 	bool range = wacom_wac-&gt;hid_data.inrange_state;</div><div class='ctx'> 	bool sense = wacom_wac-&gt;hid_data.sense_state;</div><div class='add'>+	bool entering_range = !wacom_wac-&gt;tool[0] &amp;&amp; range;</div><div class='ctx'> </div><div class='ctx'> 	if (wacom_wac-&gt;is_invalid_bt_frame)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!wacom_wac-&gt;tool[0] &amp;&amp; range) { /* first in range */</div><div class='add'>+	if (entering_range) { /* first in range */</div><div class='ctx'> 		/* Going into range select tool */</div><div class='ctx'> 		if (wacom_wac-&gt;hid_data.invert_state)</div><div class='ctx'> 			wacom_wac-&gt;tool[0] = BTN_TOOL_RUBBER;</div><div class='hunk'>@@ -2583,6 +2584,15 @@ static void wacom_wac_pen_report(struct hid_device *hdev,</div><div class='ctx'> 		input_sync(input);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Handle AES battery timeout behavior */</div><div class='add'>+	if (wacom_wac-&gt;features.quirks &amp; WACOM_QUIRK_AESPEN) {</div><div class='add'>+		if (entering_range)</div><div class='add'>+			cancel_delayed_work(&amp;wacom-&gt;aes_battery_work);</div><div class='add'>+		if (!sense)</div><div class='add'>+			schedule_delayed_work(&amp;wacom-&gt;aes_battery_work,</div><div class='add'>+					      msecs_to_jiffies(WACOM_AES_BATTERY_TIMEOUT));</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!sense) {</div><div class='ctx'> 		wacom_wac-&gt;tool[0] = 0;</div><div class='ctx'> 		wacom_wac-&gt;id[0] = 0;</div><div class='hunk'>@@ -2649,8 +2659,8 @@ static void wacom_wac_finger_slot(struct wacom_wac *wacom_wac,</div><div class='ctx'> {</div><div class='ctx'> 	struct hid_data *hid_data = &amp;wacom_wac-&gt;hid_data;</div><div class='ctx'> 	bool mt = wacom_wac-&gt;features.touch_max &gt; 1;</div><div class='del'>-	bool prox = hid_data-&gt;tipswitch &amp;&amp;</div><div class='del'>-		    report_touch_events(wacom_wac);</div><div class='add'>+	bool touch_down = hid_data-&gt;tipswitch &amp;&amp; hid_data-&gt;confidence;</div><div class='add'>+	bool prox = touch_down &amp;&amp; report_touch_events(wacom_wac);</div><div class='ctx'> </div><div class='ctx'> 	if (touch_is_muted(wacom_wac)) {</div><div class='ctx'> 		if (!wacom_wac-&gt;shared-&gt;touch_down)</div><div class='hunk'>@@ -2700,24 +2710,6 @@ static void wacom_wac_finger_slot(struct wacom_wac *wacom_wac,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool wacom_wac_slot_is_active(struct input_dev *dev, int key)</div><div class='del'>-{</div><div class='del'>-	struct input_mt *mt = dev-&gt;mt;</div><div class='del'>-	struct input_mt_slot *s;</div><div class='del'>-</div><div class='del'>-	if (!mt)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	for (s = mt-&gt;slots; s != mt-&gt;slots + mt-&gt;num_slots; s++) {</div><div class='del'>-		if (s-&gt;key == key &amp;&amp;</div><div class='del'>-			input_mt_get_value(s, ABS_MT_TRACKING_ID) &gt;= 0) {</div><div class='del'>-			return true;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void wacom_wac_finger_event(struct hid_device *hdev,</div><div class='ctx'> 		struct hid_field *field, struct hid_usage *usage, __s32 value)</div><div class='ctx'> {</div><div class='hunk'>@@ -2768,14 +2760,8 @@ static void wacom_wac_finger_event(struct hid_device *hdev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (usage-&gt;usage_index + 1 == field-&gt;report_count) {</div><div class='del'>-		if (equivalent_usage == wacom_wac-&gt;hid_data.last_slot_field) {</div><div class='del'>-			bool touch_removed = wacom_wac_slot_is_active(wacom_wac-&gt;touch_input,</div><div class='del'>-				wacom_wac-&gt;hid_data.id) &amp;&amp; !wacom_wac-&gt;hid_data.tipswitch;</div><div class='del'>-</div><div class='del'>-			if (wacom_wac-&gt;hid_data.confidence || touch_removed) {</div><div class='del'>-				wacom_wac_finger_slot(wacom_wac, wacom_wac-&gt;touch_input);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+		if (equivalent_usage == wacom_wac-&gt;hid_data.last_slot_field)</div><div class='add'>+			wacom_wac_finger_slot(wacom_wac, wacom_wac-&gt;touch_input);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hid/wacom_wac.h b/drivers/hid/wacom_wac.h<br/>index 57e185f18d53..e63b1e806e34 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hid/wacom_wac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hid/wacom_wac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hid/wacom_wac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hid/wacom_wac.h</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #define WACOM_MAX_REMOTES	5</div><div class='ctx'> #define WACOM_STATUS_UNKNOWN	255</div><div class='ctx'> #define WACOM_REMOTE_BATTERY_TIMEOUT	21000000000ll</div><div class='add'>+#define WACOM_AES_BATTERY_TIMEOUT       1800000</div><div class='ctx'> </div><div class='ctx'> /* packet length for individual models */</div><div class='ctx'> #define WACOM_PKGLEN_BBFUN	 9</div><div class='head'>diff --git a/drivers/hsi/controllers/omap_ssi_core.c b/drivers/hsi/controllers/omap_ssi_core.c<br/>index 4c1a00f9929e..6802efb4d6cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hsi/controllers/omap_ssi_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hsi/controllers/omap_ssi_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hsi/controllers/omap_ssi_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hsi/controllers/omap_ssi_core.c</a></div><div class='hunk'>@@ -355,7 +355,7 @@ static int ssi_add_controller(struct hsi_controller *ssi,</div><div class='ctx'> 	if (!omap_ssi)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	err = ida_simple_get(&amp;platform_omap_ssi_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	err = ida_alloc(&amp;platform_omap_ssi_ida, GFP_KERNEL);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	ssi-&gt;id = err;</div><div class='hunk'>@@ -417,7 +417,7 @@ static int ssi_add_controller(struct hsi_controller *ssi,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_err:</div><div class='del'>-	ida_simple_remove(&amp;platform_omap_ssi_ida, ssi-&gt;id);</div><div class='add'>+	ida_free(&amp;platform_omap_ssi_ida, ssi-&gt;id);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -451,7 +451,7 @@ static void ssi_remove_controller(struct hsi_controller *ssi)</div><div class='ctx'> 	tasklet_kill(&amp;omap_ssi-&gt;gdd_tasklet);</div><div class='ctx'> 	hsi_unregister_controller(ssi);</div><div class='ctx'> 	clk_notifier_unregister(omap_ssi-&gt;fck, &amp;omap_ssi-&gt;fck_nb);</div><div class='del'>-	ida_simple_remove(&amp;platform_omap_ssi_ida, id);</div><div class='add'>+	ida_free(&amp;platform_omap_ssi_ida, id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int ssi_of_get_available_ports_count(const struct device_node *np)</div><div class='head'>diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c<br/>index 4372f5d146ab..0285a74363b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hv/hv_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hv/hv_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hv/hv_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hv/hv_common.c</a></div><div class='hunk'>@@ -488,7 +488,7 @@ void hv_setup_dma_ops(struct device *dev, bool coherent)</div><div class='ctx'> 	 * Hyper-V does not offer a vIOMMU in the guest</div><div class='ctx'> 	 * VM, so pass 0/NULL for the IOMMU settings</div><div class='ctx'> 	 */</div><div class='del'>-	arch_setup_dma_ops(dev, 0, 0, NULL, coherent);</div><div class='add'>+	arch_setup_dma_ops(dev, 0, 0, coherent);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(hv_setup_dma_ops);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig<br/>index cf27523eed5a..a608264da87d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/Kconfig</a></div><div class='hunk'>@@ -512,6 +512,7 @@ config SENSORS_DS1621</div><div class='ctx'> </div><div class='ctx'> config SENSORS_DELL_SMM</div><div class='ctx'> 	tristate "Dell laptop SMM BIOS hwmon driver"</div><div class='add'>+	depends on ACPI_WMI</div><div class='ctx'> 	depends on X86</div><div class='ctx'> 	imply THERMAL</div><div class='ctx'> 	help</div><div class='hunk'>@@ -663,6 +664,16 @@ config SENSORS_FTSTEUTATES</div><div class='ctx'> 	  This driver can also be built as a module. If so, the module</div><div class='ctx'> 	  will be called ftsteutates.</div><div class='ctx'> </div><div class='add'>+config SENSORS_GIGABYTE_WATERFORCE</div><div class='add'>+	tristate "Gigabyte Waterforce X240/X280/X360 AIO CPU coolers"</div><div class='add'>+	depends on USB_HID</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get support for hardware monitoring for the</div><div class='add'>+	  Gigabyte Waterforce X240/X280/X360 all-in-one CPU liquid coolers.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module</div><div class='add'>+	  will be called gigabyte_waterforce.</div><div class='add'>+</div><div class='ctx'> config SENSORS_GL518SM</div><div class='ctx'> 	tristate "Genesys Logic GL518SM"</div><div class='ctx'> 	depends on I2C</div><div class='head'>diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile<br/>index e84bd9685b5c..47be39af5c03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/Makefile</a></div><div class='hunk'>@@ -80,6 +80,7 @@ obj-$(CONFIG_SENSORS_FSCHMD)	+= fschmd.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_FTSTEUTATES) += ftsteutates.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_G760A)	+= g760a.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_G762)	+= g762.o</div><div class='add'>+obj-$(CONFIG_SENSORS_GIGABYTE_WATERFORCE) += gigabyte_waterforce.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_GL518SM)	+= gl518sm.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_GL520SM)	+= gl520sm.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_GSC)	+= gsc-hwmon.o</div><div class='head'>diff --git a/drivers/hwmon/acpi_power_meter.c b/drivers/hwmon/acpi_power_meter.c<br/>index 8db740214ffd..703666b95bf4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/acpi_power_meter.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/acpi_power_meter.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/acpi_power_meter.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/acpi_power_meter.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'> #define POWER_METER_CAN_NOTIFY	(1 &lt;&lt; 3)</div><div class='ctx'> #define POWER_METER_IS_BATTERY	(1 &lt;&lt; 8)</div><div class='ctx'> #define UNKNOWN_HYSTERESIS	0xFFFFFFFF</div><div class='add'>+#define UNKNOWN_POWER		0xFFFFFFFF</div><div class='ctx'> </div><div class='ctx'> #define METER_NOTIFY_CONFIG	0x80</div><div class='ctx'> #define METER_NOTIFY_TRIP	0x81</div><div class='hunk'>@@ -348,6 +349,9 @@ static ssize_t show_power(struct device *dev,</div><div class='ctx'> 	update_meter(resource);</div><div class='ctx'> 	mutex_unlock(&amp;resource-&gt;lock);</div><div class='ctx'> </div><div class='add'>+	if (resource-&gt;power == UNKNOWN_POWER)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='ctx'> 	return sprintf(buf, "%llu\n", resource-&gt;power * 1000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwmon/aquacomputer_d5next.c b/drivers/hwmon/aquacomputer_d5next.c<br/>index 4fdd2e12427b..2efe97f8d003 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/aquacomputer_d5next.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/aquacomputer_d5next.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/aquacomputer_d5next.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/aquacomputer_d5next.c</a></div><div class='hunk'>@@ -1476,8 +1476,6 @@ static int aqc_raw_event(struct hid_device *hdev, struct hid_report *report, u8</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_DEBUG_FS</div><div class='del'>-</div><div class='ctx'> static int serial_number_show(struct seq_file *seqf, void *unused)</div><div class='ctx'> {</div><div class='ctx'> 	struct aqc_data *priv = seqf-&gt;private;</div><div class='hunk'>@@ -1527,14 +1525,6 @@ static void aqc_debugfs_init(struct aqc_data *priv)</div><div class='ctx'> 		debugfs_create_file("power_cycles", 0444, priv-&gt;debugfs, priv, &amp;power_cycles_fops);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#else</div><div class='del'>-</div><div class='del'>-static void aqc_debugfs_init(struct aqc_data *priv)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> static int aqc_probe(struct hid_device *hdev, const struct hid_device_id *id)</div><div class='ctx'> {</div><div class='ctx'> 	struct aqc_data *priv;</div><div class='head'>diff --git a/drivers/hwmon/aspeed-pwm-tacho.c b/drivers/hwmon/aspeed-pwm-tacho.c<br/>index 997df4b40509..f6e1e55e8292 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/aspeed-pwm-tacho.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/aspeed-pwm-tacho.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/aspeed-pwm-tacho.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/aspeed-pwm-tacho.c</a></div><div class='hunk'>@@ -166,6 +166,8 @@</div><div class='ctx'> </div><div class='ctx'> #define MAX_CDEV_NAME_LEN 16</div><div class='ctx'> </div><div class='add'>+#define MAX_ASPEED_FAN_TACH_CHANNELS 16</div><div class='add'>+</div><div class='ctx'> struct aspeed_cooling_device {</div><div class='ctx'> 	char name[16];</div><div class='ctx'> 	struct aspeed_pwm_tacho_data *priv;</div><div class='hunk'>@@ -181,7 +183,7 @@ struct aspeed_pwm_tacho_data {</div><div class='ctx'> 	struct reset_control *rst;</div><div class='ctx'> 	unsigned long clk_freq;</div><div class='ctx'> 	bool pwm_present[8];</div><div class='del'>-	bool fan_tach_present[16];</div><div class='add'>+	bool fan_tach_present[MAX_ASPEED_FAN_TACH_CHANNELS];</div><div class='ctx'> 	u8 type_pwm_clock_unit[3];</div><div class='ctx'> 	u8 type_pwm_clock_division_h[3];</div><div class='ctx'> 	u8 type_pwm_clock_division_l[3];</div><div class='hunk'>@@ -190,7 +192,7 @@ struct aspeed_pwm_tacho_data {</div><div class='ctx'> 	u16 type_fan_tach_unit[3];</div><div class='ctx'> 	u8 pwm_port_type[8];</div><div class='ctx'> 	u8 pwm_port_fan_ctrl[8];</div><div class='del'>-	u8 fan_tach_ch_source[16];</div><div class='add'>+	u8 fan_tach_ch_source[MAX_ASPEED_FAN_TACH_CHANNELS];</div><div class='ctx'> 	struct aspeed_cooling_device *cdev[8];</div><div class='ctx'> 	const struct attribute_group *groups[3];</div><div class='ctx'> };</div><div class='hunk'>@@ -737,20 +739,27 @@ static void aspeed_create_pwm_port(struct aspeed_pwm_tacho_data *priv,</div><div class='ctx'> 	aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void aspeed_create_fan_tach_channel(struct aspeed_pwm_tacho_data *priv,</div><div class='del'>-					   u8 *fan_tach_ch,</div><div class='del'>-					   int count,</div><div class='del'>-					   u8 pwm_source)</div><div class='add'>+static int aspeed_create_fan_tach_channel(struct device *dev,</div><div class='add'>+					  struct aspeed_pwm_tacho_data *priv,</div><div class='add'>+					  u8 *fan_tach_ch,</div><div class='add'>+					  int count,</div><div class='add'>+					  u8 pwm_source)</div><div class='ctx'> {</div><div class='ctx'> 	u8 val, index;</div><div class='ctx'> </div><div class='ctx'> 	for (val = 0; val &lt; count; val++) {</div><div class='ctx'> 		index = fan_tach_ch[val];</div><div class='add'>+		if (index &gt;= MAX_ASPEED_FAN_TACH_CHANNELS) {</div><div class='add'>+			dev_err(dev, "Invalid Fan Tach input channel %u\n.", index);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 		aspeed_set_fan_tach_ch_enable(priv-&gt;regmap, index, true);</div><div class='ctx'> 		priv-&gt;fan_tach_present[index] = true;</div><div class='ctx'> 		priv-&gt;fan_tach_ch_source[index] = pwm_source;</div><div class='ctx'> 		aspeed_set_fan_tach_ch_source(priv-&gt;regmap, index, pwm_source);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='hunk'>@@ -874,7 +883,10 @@ static int aspeed_create_fan(struct device *dev,</div><div class='ctx'> 					fan_tach_ch, count);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='del'>-	aspeed_create_fan_tach_channel(priv, fan_tach_ch, count, pwm_port);</div><div class='add'>+</div><div class='add'>+	ret = aspeed_create_fan_tach_channel(dev, priv, fan_tach_ch, count, pwm_port);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/hwmon/corsair-cpro.c b/drivers/hwmon/corsair-cpro.c<br/>index 463ab4296ede..a284a02839fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/corsair-cpro.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/corsair-cpro.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/corsair-cpro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/corsair-cpro.c</a></div><div class='hunk'>@@ -524,7 +524,7 @@ static int ccp_probe(struct hid_device *hdev, const struct hid_device_id *id)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_hw_close;</div><div class='ctx'> 	ccp-&gt;hwmon_dev = hwmon_device_register_with_info(&amp;hdev-&gt;dev, "corsaircpro",</div><div class='del'>-							 ccp, &amp;ccp_chip_info, 0);</div><div class='add'>+							 ccp, &amp;ccp_chip_info, NULL);</div><div class='ctx'> 	if (IS_ERR(ccp-&gt;hwmon_dev)) {</div><div class='ctx'> 		ret = PTR_ERR(ccp-&gt;hwmon_dev);</div><div class='ctx'> 		goto out_hw_close;</div><div class='head'>diff --git a/drivers/hwmon/corsair-psu.c b/drivers/hwmon/corsair-psu.c<br/>index 904890598c11..2c7c92272fe3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/corsair-psu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/corsair-psu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/corsair-psu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/corsair-psu.c</a></div><div class='hunk'>@@ -899,7 +899,23 @@ static struct hid_driver corsairpsu_driver = {</div><div class='ctx'> 	.reset_resume	= corsairpsu_resume,</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='del'>-module_hid_driver(corsairpsu_driver);</div><div class='add'>+</div><div class='add'>+static int __init corsair_init(void)</div><div class='add'>+{</div><div class='add'>+	return hid_register_driver(&amp;corsairpsu_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit corsair_exit(void)</div><div class='add'>+{</div><div class='add'>+	hid_unregister_driver(&amp;corsairpsu_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * With module_init() the driver would load before the HID bus when</div><div class='add'>+ * built-in, so use late_initcall() instead.</div><div class='add'>+ */</div><div class='add'>+late_initcall(corsair_init);</div><div class='add'>+module_exit(corsair_exit);</div><div class='ctx'> </div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_AUTHOR("Wilken Gottwalt &lt;wilken.gottwalt@posteo.net&gt;");</div><div class='head'>diff --git a/drivers/hwmon/dell-smm-hwmon.c b/drivers/hwmon/dell-smm-hwmon.c<br/>index 44aaf9b9191d..6d8c0f328b7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/dell-smm-hwmon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/dell-smm-hwmon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/dell-smm-hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/dell-smm-hwmon.c</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> </div><div class='ctx'> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/capability.h&gt;</div><div class='ctx'> #include &lt;linux/cpu.h&gt;</div><div class='ctx'> #include &lt;linux/ctype.h&gt;</div><div class='hunk'>@@ -34,8 +35,10 @@</div><div class='ctx'> #include &lt;linux/thermal.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='add'>+#include &lt;linux/wmi.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/i8k.h&gt;</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define I8K_SMM_FN_STATUS	0x0025</div><div class='ctx'> #define I8K_SMM_POWER_STATUS	0x0069</div><div class='hunk'>@@ -66,9 +69,26 @@</div><div class='ctx'> #define I8K_POWER_AC		0x05</div><div class='ctx'> #define I8K_POWER_BATTERY	0x01</div><div class='ctx'> </div><div class='add'>+#define DELL_SMM_WMI_GUID	"F1DDEE52-063C-4784-A11E-8A06684B9B01"</div><div class='add'>+#define DELL_SMM_LEGACY_EXECUTE	0x1</div><div class='add'>+</div><div class='ctx'> #define DELL_SMM_NO_TEMP	10</div><div class='ctx'> #define DELL_SMM_NO_FANS	3</div><div class='ctx'> </div><div class='add'>+struct smm_regs {</div><div class='add'>+	unsigned int eax;</div><div class='add'>+	unsigned int ebx;</div><div class='add'>+	unsigned int ecx;</div><div class='add'>+	unsigned int edx;</div><div class='add'>+	unsigned int esi;</div><div class='add'>+	unsigned int edi;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dell_smm_ops {</div><div class='add'>+	struct device *smm_dev;</div><div class='add'>+	int (*smm_call)(struct device *smm_dev, struct smm_regs *regs);</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct dell_smm_data {</div><div class='ctx'> 	struct mutex i8k_mutex; /* lock for sensors writes */</div><div class='ctx'> 	char bios_version[4];</div><div class='hunk'>@@ -76,14 +96,11 @@ struct dell_smm_data {</div><div class='ctx'> 	uint i8k_fan_mult;</div><div class='ctx'> 	uint i8k_pwm_mult;</div><div class='ctx'> 	uint i8k_fan_max;</div><div class='del'>-	bool disallow_fan_type_call;</div><div class='del'>-	bool disallow_fan_support;</div><div class='del'>-	unsigned int manual_fan;</div><div class='del'>-	unsigned int auto_fan;</div><div class='ctx'> 	int temp_type[DELL_SMM_NO_TEMP];</div><div class='ctx'> 	bool fan[DELL_SMM_NO_FANS];</div><div class='ctx'> 	int fan_type[DELL_SMM_NO_FANS];</div><div class='ctx'> 	int *fan_nominal_speed[DELL_SMM_NO_FANS];</div><div class='add'>+	const struct dell_smm_ops *ops;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct dell_smm_cooling_data {</div><div class='hunk'>@@ -123,14 +140,9 @@ static uint fan_max;</div><div class='ctx'> module_param(fan_max, uint, 0);</div><div class='ctx'> MODULE_PARM_DESC(fan_max, "Maximum configurable fan speed (default: autodetect)");</div><div class='ctx'> </div><div class='del'>-struct smm_regs {</div><div class='del'>-	unsigned int eax;</div><div class='del'>-	unsigned int ebx;</div><div class='del'>-	unsigned int ecx;</div><div class='del'>-	unsigned int edx;</div><div class='del'>-	unsigned int esi;</div><div class='del'>-	unsigned int edi;</div><div class='del'>-};</div><div class='add'>+static bool disallow_fan_type_call, disallow_fan_support;</div><div class='add'>+</div><div class='add'>+static unsigned int manual_fan, auto_fan;</div><div class='ctx'> </div><div class='ctx'> static const char * const temp_labels[] = {</div><div class='ctx'> 	"CPU",</div><div class='hunk'>@@ -171,12 +183,8 @@ static inline const char __init *i8k_get_dmi_data(int field)</div><div class='ctx'>  */</div><div class='ctx'> static int i8k_smm_func(void *par)</div><div class='ctx'> {</div><div class='del'>-	ktime_t calltime = ktime_get();</div><div class='ctx'> 	struct smm_regs *regs = par;</div><div class='del'>-	int eax = regs-&gt;eax;</div><div class='del'>-	int ebx = regs-&gt;ebx;</div><div class='ctx'> 	unsigned char carry;</div><div class='del'>-	long long duration;</div><div class='ctx'> </div><div class='ctx'> 	/* SMM requires CPU 0 */</div><div class='ctx'> 	if (smp_processor_id() != 0)</div><div class='hunk'>@@ -193,14 +201,7 @@ static int i8k_smm_func(void *par)</div><div class='ctx'> 		       "+S" (regs-&gt;esi),</div><div class='ctx'> 		       "+D" (regs-&gt;edi));</div><div class='ctx'> </div><div class='del'>-	duration = ktime_us_delta(ktime_get(), calltime);</div><div class='del'>-	pr_debug("smm(0x%.4x 0x%.4x) = 0x%.4x carry: %d (took %7lld usecs)\n",</div><div class='del'>-		 eax, ebx, regs-&gt;eax &amp; 0xffff, carry, duration);</div><div class='del'>-</div><div class='del'>-	if (duration &gt; DELL_SMM_MAX_DURATION)</div><div class='del'>-		pr_warn_once("SMM call took %lld usecs!\n", duration);</div><div class='del'>-</div><div class='del'>-	if (carry || (regs-&gt;eax &amp; 0xffff) == 0xffff || regs-&gt;eax == eax)</div><div class='add'>+	if (carry)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -209,7 +210,7 @@ static int i8k_smm_func(void *par)</div><div class='ctx'> /*</div><div class='ctx'>  * Call the System Management Mode BIOS.</div><div class='ctx'>  */</div><div class='del'>-static int i8k_smm(struct smm_regs *regs)</div><div class='add'>+static int i8k_smm_call(struct device *dummy, struct smm_regs *regs)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -220,6 +221,134 @@ static int i8k_smm(struct smm_regs *regs)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct dell_smm_ops i8k_smm_ops = {</div><div class='add'>+	.smm_call = i8k_smm_call,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Call the System Management Mode BIOS over WMI.</div><div class='add'>+ */</div><div class='add'>+static ssize_t wmi_parse_register(u8 *buffer, u32 length, unsigned int *reg)</div><div class='add'>+{</div><div class='add'>+	__le32 value;</div><div class='add'>+	u32 reg_size;</div><div class='add'>+</div><div class='add'>+	if (length &lt;= sizeof(reg_size))</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	reg_size = get_unaligned_le32(buffer);</div><div class='add'>+	if (!reg_size || reg_size &gt; sizeof(value))</div><div class='add'>+		return -ENOMSG;</div><div class='add'>+</div><div class='add'>+	if (length &lt; sizeof(reg_size) + reg_size)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	memcpy_and_pad(&amp;value, sizeof(value), buffer + sizeof(reg_size), reg_size, 0);</div><div class='add'>+	*reg = le32_to_cpu(value);</div><div class='add'>+</div><div class='add'>+	return reg_size + sizeof(reg_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wmi_parse_response(u8 *buffer, u32 length, struct smm_regs *regs)</div><div class='add'>+{</div><div class='add'>+	unsigned int *registers[] = {</div><div class='add'>+		&amp;regs-&gt;eax,</div><div class='add'>+		&amp;regs-&gt;ebx,</div><div class='add'>+		&amp;regs-&gt;ecx,</div><div class='add'>+		&amp;regs-&gt;edx</div><div class='add'>+	};</div><div class='add'>+	u32 offset = 0;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(registers); i++) {</div><div class='add'>+		if (offset &gt;= length)</div><div class='add'>+			return -ENODATA;</div><div class='add'>+</div><div class='add'>+		ret = wmi_parse_register(buffer + offset, length - offset, registers[i]);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		offset += ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (offset != length)</div><div class='add'>+		return -ENOMSG;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wmi_smm_call(struct device *dev, struct smm_regs *regs)</div><div class='add'>+{</div><div class='add'>+	struct wmi_device *wdev = container_of(dev, struct wmi_device, dev);</div><div class='add'>+	struct acpi_buffer out = { ACPI_ALLOCATE_BUFFER, NULL };</div><div class='add'>+	u32 wmi_payload[] = {</div><div class='add'>+		sizeof(regs-&gt;eax),</div><div class='add'>+		regs-&gt;eax,</div><div class='add'>+		sizeof(regs-&gt;ebx),</div><div class='add'>+		regs-&gt;ebx,</div><div class='add'>+		sizeof(regs-&gt;ecx),</div><div class='add'>+		regs-&gt;ecx,</div><div class='add'>+		sizeof(regs-&gt;edx),</div><div class='add'>+		regs-&gt;edx</div><div class='add'>+	};</div><div class='add'>+	const struct acpi_buffer in = {</div><div class='add'>+		.length = sizeof(wmi_payload),</div><div class='add'>+		.pointer = &amp;wmi_payload,</div><div class='add'>+	};</div><div class='add'>+	union acpi_object *obj;</div><div class='add'>+	acpi_status status;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	status = wmidev_evaluate_method(wdev, 0x0, DELL_SMM_LEGACY_EXECUTE, &amp;in, &amp;out);</div><div class='add'>+	if (ACPI_FAILURE(status))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	obj = out.pointer;</div><div class='add'>+	if (!obj)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	if (obj-&gt;type != ACPI_TYPE_BUFFER) {</div><div class='add'>+		ret = -ENOMSG;</div><div class='add'>+</div><div class='add'>+		goto err_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wmi_parse_response(obj-&gt;buffer.pointer, obj-&gt;buffer.length, regs);</div><div class='add'>+</div><div class='add'>+err_free:</div><div class='add'>+	kfree(obj);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dell_smm_call(const struct dell_smm_ops *ops, struct smm_regs *regs)</div><div class='add'>+{</div><div class='add'>+	unsigned int eax = regs-&gt;eax;</div><div class='add'>+	unsigned int ebx = regs-&gt;ebx;</div><div class='add'>+	long long duration;</div><div class='add'>+	ktime_t calltime;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	calltime = ktime_get();</div><div class='add'>+	ret = ops-&gt;smm_call(ops-&gt;smm_dev, regs);</div><div class='add'>+	duration = ktime_us_delta(ktime_get(), calltime);</div><div class='add'>+</div><div class='add'>+	pr_debug("SMM(0x%.4x 0x%.4x) = 0x%.4x status: %d (took %7lld usecs)\n",</div><div class='add'>+		 eax, ebx, regs-&gt;eax &amp; 0xffff, ret, duration);</div><div class='add'>+</div><div class='add'>+	if (duration &gt; DELL_SMM_MAX_DURATION)</div><div class='add'>+		pr_warn_once("SMM call took %lld usecs!\n", duration);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if ((regs-&gt;eax &amp; 0xffff) == 0xffff || regs-&gt;eax == eax)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Read the fan status.</div><div class='ctx'>  */</div><div class='hunk'>@@ -230,10 +359,10 @@ static int i8k_get_fan_status(const struct dell_smm_data *data, u8 fan)</div><div class='ctx'> 		.ebx = fan,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support)</div><div class='add'>+	if (disallow_fan_support)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : regs.eax &amp; 0xff;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : regs.eax &amp; 0xff;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -246,10 +375,10 @@ static int i8k_get_fan_speed(const struct dell_smm_data *data, u8 fan)</div><div class='ctx'> 		.ebx = fan,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support)</div><div class='add'>+	if (disallow_fan_support)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : (regs.eax &amp; 0xffff) * data-&gt;i8k_fan_mult;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : (regs.eax &amp; 0xffff) * data-&gt;i8k_fan_mult;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -262,10 +391,10 @@ static int _i8k_get_fan_type(const struct dell_smm_data *data, u8 fan)</div><div class='ctx'> 		.ebx = fan,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support || data-&gt;disallow_fan_type_call)</div><div class='add'>+	if (disallow_fan_support || disallow_fan_type_call)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : regs.eax &amp; 0xff;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : regs.eax &amp; 0xff;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int i8k_get_fan_type(struct dell_smm_data *data, u8 fan)</div><div class='hunk'>@@ -280,17 +409,17 @@ static int i8k_get_fan_type(struct dell_smm_data *data, u8 fan)</div><div class='ctx'> /*</div><div class='ctx'>  * Read the fan nominal rpm for specific fan speed.</div><div class='ctx'>  */</div><div class='del'>-static int __init i8k_get_fan_nominal_speed(const struct dell_smm_data *data, u8 fan, int speed)</div><div class='add'>+static int i8k_get_fan_nominal_speed(const struct dell_smm_data *data, u8 fan, int speed)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = {</div><div class='ctx'> 		.eax = I8K_SMM_GET_NOM_SPEED,</div><div class='ctx'> 		.ebx = fan | (speed &lt;&lt; 8),</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support)</div><div class='add'>+	if (disallow_fan_support)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : (regs.eax &amp; 0xffff);</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : (regs.eax &amp; 0xffff);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -300,11 +429,11 @@ static int i8k_enable_fan_auto_mode(const struct dell_smm_data *data, bool enabl</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = { };</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support)</div><div class='add'>+	if (disallow_fan_support)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	regs.eax = enable ? data-&gt;auto_fan : data-&gt;manual_fan;</div><div class='del'>-	return i8k_smm(&amp;regs);</div><div class='add'>+	regs.eax = enable ? auto_fan : manual_fan;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -314,41 +443,41 @@ static int i8k_set_fan(const struct dell_smm_data *data, u8 fan, int speed)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = { .eax = I8K_SMM_SET_FAN, };</div><div class='ctx'> </div><div class='del'>-	if (data-&gt;disallow_fan_support)</div><div class='add'>+	if (disallow_fan_support)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	speed = (speed &lt; 0) ? 0 : ((speed &gt; data-&gt;i8k_fan_max) ? data-&gt;i8k_fan_max : speed);</div><div class='ctx'> 	regs.ebx = fan | (speed &lt;&lt; 8);</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs);</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __init i8k_get_temp_type(u8 sensor)</div><div class='add'>+static int i8k_get_temp_type(const struct dell_smm_data *data, u8 sensor)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = {</div><div class='ctx'> 		.eax = I8K_SMM_GET_TEMP_TYPE,</div><div class='ctx'> 		.ebx = sensor,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : regs.eax &amp; 0xff;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : regs.eax &amp; 0xff;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Read the cpu temperature.</div><div class='ctx'>  */</div><div class='del'>-static int _i8k_get_temp(u8 sensor)</div><div class='add'>+static int _i8k_get_temp(const struct dell_smm_data *data, u8 sensor)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = {</div><div class='ctx'> 		.eax = I8K_SMM_GET_TEMP,</div><div class='ctx'> 		.ebx = sensor,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	return i8k_smm(&amp;regs) ? : regs.eax &amp; 0xff;</div><div class='add'>+	return dell_smm_call(data-&gt;ops, &amp;regs) ? : regs.eax &amp; 0xff;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int i8k_get_temp(u8 sensor)</div><div class='add'>+static int i8k_get_temp(const struct dell_smm_data *data, u8 sensor)</div><div class='ctx'> {</div><div class='del'>-	int temp = _i8k_get_temp(sensor);</div><div class='add'>+	int temp = _i8k_get_temp(data, sensor);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Sometimes the temperature sensor returns 0x99, which is out of range.</div><div class='hunk'>@@ -359,7 +488,7 @@ static int i8k_get_temp(u8 sensor)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (temp == 0x99) {</div><div class='ctx'> 		msleep(100);</div><div class='del'>-		temp = _i8k_get_temp(sensor);</div><div class='add'>+		temp = _i8k_get_temp(data, sensor);</div><div class='ctx'> 	}</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Return -ENODATA for all invalid temperatures.</div><div class='hunk'>@@ -375,12 +504,12 @@ static int i8k_get_temp(u8 sensor)</div><div class='ctx'> 	return temp;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __init i8k_get_dell_signature(int req_fn)</div><div class='add'>+static int dell_smm_get_signature(const struct dell_smm_ops *ops, int req_fn)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = { .eax = req_fn, };</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	rc = i8k_smm(&amp;regs);</div><div class='add'>+	rc = dell_smm_call(ops, &amp;regs);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -392,12 +521,12 @@ static int __init i8k_get_dell_signature(int req_fn)</div><div class='ctx'> /*</div><div class='ctx'>  * Read the Fn key status.</div><div class='ctx'>  */</div><div class='del'>-static int i8k_get_fn_status(void)</div><div class='add'>+static int i8k_get_fn_status(const struct dell_smm_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = { .eax = I8K_SMM_FN_STATUS, };</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	rc = i8k_smm(&amp;regs);</div><div class='add'>+	rc = dell_smm_call(data-&gt;ops, &amp;regs);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -416,12 +545,12 @@ static int i8k_get_fn_status(void)</div><div class='ctx'> /*</div><div class='ctx'>  * Read the power status.</div><div class='ctx'>  */</div><div class='del'>-static int i8k_get_power_status(void)</div><div class='add'>+static int i8k_get_power_status(const struct dell_smm_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct smm_regs regs = { .eax = I8K_SMM_POWER_STATUS, };</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	rc = i8k_smm(&amp;regs);</div><div class='add'>+	rc = dell_smm_call(data-&gt;ops, &amp;regs);</div><div class='ctx'> 	if (rc &lt; 0)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -464,15 +593,15 @@ static long i8k_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='ctx'> 	case I8K_FN_STATUS:</div><div class='del'>-		val = i8k_get_fn_status();</div><div class='add'>+		val = i8k_get_fn_status(data);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case I8K_POWER_STATUS:</div><div class='del'>-		val = i8k_get_power_status();</div><div class='add'>+		val = i8k_get_power_status(data);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case I8K_GET_TEMP:</div><div class='del'>-		val = i8k_get_temp(0);</div><div class='add'>+		val = i8k_get_temp(data, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case I8K_GET_SPEED:</div><div class='hunk'>@@ -539,14 +668,14 @@ static int i8k_proc_show(struct seq_file *seq, void *offset)</div><div class='ctx'> 	int fn_key, cpu_temp, ac_power;</div><div class='ctx'> 	int left_fan, right_fan, left_speed, right_speed;</div><div class='ctx'> </div><div class='del'>-	cpu_temp	= i8k_get_temp(0);				/* 11100 µs */</div><div class='add'>+	cpu_temp	= i8k_get_temp(data, 0);			/* 11100 µs */</div><div class='ctx'> 	left_fan	= i8k_get_fan_status(data, I8K_FAN_LEFT);	/*   580 µs */</div><div class='ctx'> 	right_fan	= i8k_get_fan_status(data, I8K_FAN_RIGHT);	/*   580 µs */</div><div class='ctx'> 	left_speed	= i8k_get_fan_speed(data, I8K_FAN_LEFT);	/*   580 µs */</div><div class='ctx'> 	right_speed	= i8k_get_fan_speed(data, I8K_FAN_RIGHT);	/*   580 µs */</div><div class='del'>-	fn_key		= i8k_get_fn_status();				/*   750 µs */</div><div class='add'>+	fn_key		= i8k_get_fn_status(data);			/*   750 µs */</div><div class='ctx'> 	if (power_status)</div><div class='del'>-		ac_power = i8k_get_power_status();			/* 14700 µs */</div><div class='add'>+		ac_power = i8k_get_power_status(data);			/* 14700 µs */</div><div class='ctx'> 	else</div><div class='ctx'> 		ac_power = -1;</div><div class='ctx'> </div><div class='hunk'>@@ -597,6 +726,11 @@ static void __init i8k_init_procfs(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dell_smm_data *data = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='add'>+	strscpy(data-&gt;bios_version, i8k_get_dmi_data(DMI_BIOS_VERSION),</div><div class='add'>+		sizeof(data-&gt;bios_version));</div><div class='add'>+	strscpy(data-&gt;bios_machineid, i8k_get_dmi_data(DMI_PRODUCT_SERIAL),</div><div class='add'>+		sizeof(data-&gt;bios_machineid));</div><div class='add'>+</div><div class='ctx'> 	/* Only register exit function if creation was successful */</div><div class='ctx'> 	if (proc_create_data("i8k", 0, NULL, &amp;i8k_proc_ops, data))</div><div class='ctx'> 		devm_add_action_or_reset(dev, i8k_exit_procfs, NULL);</div><div class='hunk'>@@ -665,7 +799,7 @@ static umode_t dell_smm_is_visible(const void *drvdata, enum hwmon_sensor_types</div><div class='ctx'> 		switch (attr) {</div><div class='ctx'> 		case hwmon_temp_input:</div><div class='ctx'> 			/* _i8k_get_temp() is fine since we do not care about the actual value */</div><div class='del'>-			if (data-&gt;temp_type[channel] &gt;= 0 || _i8k_get_temp(channel) &gt;= 0)</div><div class='add'>+			if (data-&gt;temp_type[channel] &gt;= 0 || _i8k_get_temp(data, channel) &gt;= 0)</div><div class='ctx'> 				return 0444;</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='hunk'>@@ -679,7 +813,7 @@ static umode_t dell_smm_is_visible(const void *drvdata, enum hwmon_sensor_types</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case hwmon_fan:</div><div class='del'>-		if (data-&gt;disallow_fan_support)</div><div class='add'>+		if (disallow_fan_support)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		switch (attr) {</div><div class='hunk'>@@ -689,7 +823,7 @@ static umode_t dell_smm_is_visible(const void *drvdata, enum hwmon_sensor_types</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='ctx'> 		case hwmon_fan_label:</div><div class='del'>-			if (data-&gt;fan[channel] &amp;&amp; !data-&gt;disallow_fan_type_call)</div><div class='add'>+			if (data-&gt;fan[channel] &amp;&amp; !disallow_fan_type_call)</div><div class='ctx'> 				return 0444;</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='hunk'>@@ -705,7 +839,7 @@ static umode_t dell_smm_is_visible(const void *drvdata, enum hwmon_sensor_types</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case hwmon_pwm:</div><div class='del'>-		if (data-&gt;disallow_fan_support)</div><div class='add'>+		if (disallow_fan_support)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		switch (attr) {</div><div class='hunk'>@@ -715,7 +849,7 @@ static umode_t dell_smm_is_visible(const void *drvdata, enum hwmon_sensor_types</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='ctx'> 		case hwmon_pwm_enable:</div><div class='del'>-			if (data-&gt;auto_fan)</div><div class='add'>+			if (auto_fan)</div><div class='ctx'> 				/*</div><div class='ctx'> 				 * There is no command for retrieve the current status</div><div class='ctx'> 				 * from BIOS, and userspace/firmware itself can change</div><div class='hunk'>@@ -747,7 +881,7 @@ static int dell_smm_read(struct device *dev, enum hwmon_sensor_types type, u32 a</div><div class='ctx'> 	case hwmon_temp:</div><div class='ctx'> 		switch (attr) {</div><div class='ctx'> 		case hwmon_temp_input:</div><div class='del'>-			ret = i8k_get_temp(channel);</div><div class='add'>+			ret = i8k_get_temp(data, channel);</div><div class='ctx'> 			if (ret &lt; 0)</div><div class='ctx'> 				return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -955,7 +1089,7 @@ static const struct hwmon_chip_info dell_smm_chip_info = {</div><div class='ctx'> 	.info = dell_smm_info,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int __init dell_smm_init_cdev(struct device *dev, u8 fan_num)</div><div class='add'>+static int dell_smm_init_cdev(struct device *dev, u8 fan_num)</div><div class='ctx'> {</div><div class='ctx'> 	struct dell_smm_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct thermal_cooling_device *cdev;</div><div class='hunk'>@@ -986,7 +1120,7 @@ static int __init dell_smm_init_cdev(struct device *dev, u8 fan_num)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __init dell_smm_init_hwmon(struct device *dev)</div><div class='add'>+static int dell_smm_init_hwmon(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dell_smm_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct device *dell_smm_hwmon_dev;</div><div class='hunk'>@@ -994,7 +1128,7 @@ static int __init dell_smm_init_hwmon(struct device *dev)</div><div class='ctx'> 	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; DELL_SMM_NO_TEMP; i++) {</div><div class='del'>-		data-&gt;temp_type[i] = i8k_get_temp_type(i);</div><div class='add'>+		data-&gt;temp_type[i] = i8k_get_temp_type(data, i);</div><div class='ctx'> 		if (data-&gt;temp_type[i] &lt; 0)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -1052,41 +1186,25 @@ static int __init dell_smm_init_hwmon(struct device *dev)</div><div class='ctx'> 	return PTR_ERR_OR_ZERO(dell_smm_hwmon_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct i8k_config_data {</div><div class='del'>-	uint fan_mult;</div><div class='del'>-	uint fan_max;</div><div class='del'>-};</div><div class='add'>+static int dell_smm_init_data(struct device *dev, const struct dell_smm_ops *ops)</div><div class='add'>+{</div><div class='add'>+	struct dell_smm_data *data;</div><div class='ctx'> </div><div class='del'>-enum i8k_configs {</div><div class='del'>-	DELL_LATITUDE_D520,</div><div class='del'>-	DELL_PRECISION_490,</div><div class='del'>-	DELL_STUDIO,</div><div class='del'>-	DELL_XPS,</div><div class='del'>-};</div><div class='add'>+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);</div><div class='add'>+	if (!data)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Only use for machines which need some special configuration</div><div class='del'>- * in order to work correctly (e.g. if autoconfig fails on this machines).</div><div class='del'>- */</div><div class='add'>+	mutex_init(&amp;data-&gt;i8k_mutex);</div><div class='add'>+	dev_set_drvdata(dev, data);</div><div class='ctx'> </div><div class='del'>-static const struct i8k_config_data i8k_config_data[] __initconst = {</div><div class='del'>-	[DELL_LATITUDE_D520] = {</div><div class='del'>-		.fan_mult = 1,</div><div class='del'>-		.fan_max = I8K_FAN_TURBO,</div><div class='del'>-	},</div><div class='del'>-	[DELL_PRECISION_490] = {</div><div class='del'>-		.fan_mult = 1,</div><div class='del'>-		.fan_max = I8K_FAN_TURBO,</div><div class='del'>-	},</div><div class='del'>-	[DELL_STUDIO] = {</div><div class='del'>-		.fan_mult = 1,</div><div class='del'>-		.fan_max = I8K_FAN_HIGH,</div><div class='del'>-	},</div><div class='del'>-	[DELL_XPS] = {</div><div class='del'>-		.fan_mult = 1,</div><div class='del'>-		.fan_max = I8K_FAN_HIGH,</div><div class='del'>-	},</div><div class='del'>-};</div><div class='add'>+	data-&gt;ops = ops;</div><div class='add'>+	/* All options must not be 0 */</div><div class='add'>+	data-&gt;i8k_fan_mult = fan_mult ? : I8K_FAN_MULT;</div><div class='add'>+	data-&gt;i8k_fan_max = fan_max ? : I8K_FAN_HIGH;</div><div class='add'>+	data-&gt;i8k_pwm_mult = DIV_ROUND_UP(255, data-&gt;i8k_fan_max);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> 	{</div><div class='hunk'>@@ -1118,14 +1236,6 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.ident = "Dell Latitude D520",</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME, "Latitude D520"),</div><div class='del'>-		},</div><div class='del'>-		.driver_data = (void *)&amp;i8k_config_data[DELL_LATITUDE_D520],</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.ident = "Dell Latitude 2",</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='hunk'>@@ -1147,15 +1257,6 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.ident = "Dell Precision 490",</div><div class='del'>-		.matches = {</div><div class='del'>-			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='del'>-			DMI_MATCH(DMI_PRODUCT_NAME,</div><div class='del'>-				  "Precision WorkStation 490"),</div><div class='del'>-		},</div><div class='del'>-		.driver_data = (void *)&amp;i8k_config_data[DELL_PRECISION_490],</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.ident = "Dell Precision",</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='hunk'>@@ -1175,7 +1276,6 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='ctx'> 			DMI_MATCH(DMI_PRODUCT_NAME, "Studio"),</div><div class='ctx'> 		},</div><div class='del'>-		.driver_data = (void *)&amp;i8k_config_data[DELL_STUDIO],</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.ident = "Dell XPS M140",</div><div class='hunk'>@@ -1183,7 +1283,6 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='ctx'> 			DMI_MATCH(DMI_PRODUCT_NAME, "MXC051"),</div><div class='ctx'> 		},</div><div class='del'>-		.driver_data = (void *)&amp;i8k_config_data[DELL_XPS],</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.ident = "Dell XPS",</div><div class='hunk'>@@ -1198,6 +1297,78 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = {</div><div class='ctx'> MODULE_DEVICE_TABLE(dmi, i8k_dmi_table);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * Only use for machines which need some special configuration</div><div class='add'>+ * in order to work correctly (e.g. if autoconfig fails on this machines).</div><div class='add'>+ */</div><div class='add'>+struct i8k_config_data {</div><div class='add'>+	uint fan_mult;</div><div class='add'>+	uint fan_max;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum i8k_configs {</div><div class='add'>+	DELL_LATITUDE_D520,</div><div class='add'>+	DELL_PRECISION_490,</div><div class='add'>+	DELL_STUDIO,</div><div class='add'>+	DELL_XPS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct i8k_config_data i8k_config_data[] __initconst = {</div><div class='add'>+	[DELL_LATITUDE_D520] = {</div><div class='add'>+		.fan_mult = 1,</div><div class='add'>+		.fan_max = I8K_FAN_TURBO,</div><div class='add'>+	},</div><div class='add'>+	[DELL_PRECISION_490] = {</div><div class='add'>+		.fan_mult = 1,</div><div class='add'>+		.fan_max = I8K_FAN_TURBO,</div><div class='add'>+	},</div><div class='add'>+	[DELL_STUDIO] = {</div><div class='add'>+		.fan_mult = 1,</div><div class='add'>+		.fan_max = I8K_FAN_HIGH,</div><div class='add'>+	},</div><div class='add'>+	[DELL_XPS] = {</div><div class='add'>+		.fan_mult = 1,</div><div class='add'>+		.fan_max = I8K_FAN_HIGH,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dmi_system_id i8k_config_dmi_table[] __initconst = {</div><div class='add'>+	{</div><div class='add'>+		.ident = "Dell Latitude D520",</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "Latitude D520"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)&amp;i8k_config_data[DELL_LATITUDE_D520],</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.ident = "Dell Precision 490",</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME,</div><div class='add'>+				  "Precision WorkStation 490"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)&amp;i8k_config_data[DELL_PRECISION_490],</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.ident = "Dell Studio",</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "Studio"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)&amp;i8k_config_data[DELL_STUDIO],</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.ident = "Dell XPS M140",</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "MXC051"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)&amp;i8k_config_data[DELL_XPS],</div><div class='add'>+	},</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * On some machines once I8K_SMM_GET_FAN_TYPE is issued then CPU fan speed</div><div class='ctx'>  * randomly going up and down due to bug in Dell SMM or BIOS. Here is blacklist</div><div class='ctx'>  * of affected Dell machines for which we disallow I8K_SMM_GET_FAN_TYPE call.</div><div class='hunk'>@@ -1338,119 +1509,174 @@ static const struct dmi_system_id i8k_whitelist_fan_control[] __initconst = {</div><div class='ctx'> 		},</div><div class='ctx'> 		.driver_data = (void *)&amp;i8k_fan_control_data[I8K_FAN_34A3_35A3],</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+		.ident = "Dell Optiplex 7000",</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),</div><div class='add'>+			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "OptiPlex 7000"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)&amp;i8k_fan_control_data[I8K_FAN_34A3_35A3],</div><div class='add'>+	},</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Legacy SMM backend driver.</div><div class='add'>+ */</div><div class='ctx'> static int __init dell_smm_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	struct dell_smm_data *data;</div><div class='del'>-	const struct dmi_system_id *id, *fan_control;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	data = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(struct dell_smm_data), GFP_KERNEL);</div><div class='del'>-	if (!data)</div><div class='add'>+	ret = dell_smm_init_data(&amp;pdev-&gt;dev, &amp;i8k_smm_ops);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = dell_smm_init_hwmon(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	i8k_init_procfs(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver dell_smm_driver = {</div><div class='add'>+	.driver		= {</div><div class='add'>+		.name	= KBUILD_MODNAME,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct platform_device *dell_smm_device;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * WMI SMM backend driver.</div><div class='add'>+ */</div><div class='add'>+static int dell_smm_wmi_probe(struct wmi_device *wdev, const void *context)</div><div class='add'>+{</div><div class='add'>+	struct dell_smm_ops *ops;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ops = devm_kzalloc(&amp;wdev-&gt;dev, sizeof(*ops), GFP_KERNEL);</div><div class='add'>+	if (!ops)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	mutex_init(&amp;data-&gt;i8k_mutex);</div><div class='del'>-	platform_set_drvdata(pdev, data);</div><div class='add'>+	ops-&gt;smm_call = wmi_smm_call;</div><div class='add'>+	ops-&gt;smm_dev = &amp;wdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (dell_smm_get_signature(ops, I8K_SMM_GET_DELL_SIG1) &amp;&amp;</div><div class='add'>+	    dell_smm_get_signature(ops, I8K_SMM_GET_DELL_SIG2))</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	ret = dell_smm_init_data(&amp;wdev-&gt;dev, ops);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return dell_smm_init_hwmon(&amp;wdev-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct wmi_device_id dell_smm_wmi_id_table[] = {</div><div class='add'>+	{ DELL_SMM_WMI_GUID, NULL },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(wmi, dell_smm_wmi_id_table);</div><div class='add'>+</div><div class='add'>+static struct wmi_driver dell_smm_wmi_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = KBUILD_MODNAME,</div><div class='add'>+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,</div><div class='add'>+	},</div><div class='add'>+	.id_table = dell_smm_wmi_id_table,</div><div class='add'>+	.probe = dell_smm_wmi_probe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Probe for the presence of a supported laptop.</div><div class='add'>+ */</div><div class='add'>+static void __init dell_smm_init_dmi(void)</div><div class='add'>+{</div><div class='add'>+	struct i8k_fan_control_data *control;</div><div class='add'>+	struct i8k_config_data *config;</div><div class='add'>+	const struct dmi_system_id *id;</div><div class='ctx'> </div><div class='ctx'> 	if (dmi_check_system(i8k_blacklist_fan_support_dmi_table)) {</div><div class='ctx'> 		if (!force) {</div><div class='del'>-			dev_notice(&amp;pdev-&gt;dev, "Disabling fan support due to BIOS bugs\n");</div><div class='del'>-			data-&gt;disallow_fan_support = true;</div><div class='add'>+			pr_notice("Disabling fan support due to BIOS bugs\n");</div><div class='add'>+			disallow_fan_support = true;</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_warn(&amp;pdev-&gt;dev, "Enabling fan support despite BIOS bugs\n");</div><div class='add'>+			pr_warn("Enabling fan support despite BIOS bugs\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (dmi_check_system(i8k_blacklist_fan_type_dmi_table)) {</div><div class='ctx'> 		if (!force) {</div><div class='del'>-			dev_notice(&amp;pdev-&gt;dev, "Disabling fan type call due to BIOS bugs\n");</div><div class='del'>-			data-&gt;disallow_fan_type_call = true;</div><div class='add'>+			pr_notice("Disabling fan type call due to BIOS bugs\n");</div><div class='add'>+			disallow_fan_type_call = true;</div><div class='ctx'> 		} else {</div><div class='del'>-			dev_warn(&amp;pdev-&gt;dev, "Enabling fan type call despite BIOS bugs\n");</div><div class='add'>+			pr_warn("Enabling fan type call despite BIOS bugs\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	strscpy(data-&gt;bios_version, i8k_get_dmi_data(DMI_BIOS_VERSION),</div><div class='del'>-		sizeof(data-&gt;bios_version));</div><div class='del'>-	strscpy(data-&gt;bios_machineid, i8k_get_dmi_data(DMI_PRODUCT_SERIAL),</div><div class='del'>-		sizeof(data-&gt;bios_machineid));</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='del'>-	 * Set fan multiplier and maximal fan speed from dmi config</div><div class='del'>-	 * Values specified in module parameters override values from dmi</div><div class='add'>+	 * Set fan multiplier and maximal fan speed from DMI config.</div><div class='add'>+	 * Values specified in module parameters override values from DMI.</div><div class='ctx'> 	 */</div><div class='del'>-	id = dmi_first_match(i8k_dmi_table);</div><div class='add'>+	id = dmi_first_match(i8k_config_dmi_table);</div><div class='ctx'> 	if (id &amp;&amp; id-&gt;driver_data) {</div><div class='del'>-		const struct i8k_config_data *conf = id-&gt;driver_data;</div><div class='add'>+		config = id-&gt;driver_data;</div><div class='add'>+		if (!fan_mult &amp;&amp; config-&gt;fan_mult)</div><div class='add'>+			fan_mult = config-&gt;fan_mult;</div><div class='ctx'> </div><div class='del'>-		if (!fan_mult &amp;&amp; conf-&gt;fan_mult)</div><div class='del'>-			fan_mult = conf-&gt;fan_mult;</div><div class='del'>-</div><div class='del'>-		if (!fan_max &amp;&amp; conf-&gt;fan_max)</div><div class='del'>-			fan_max = conf-&gt;fan_max;</div><div class='add'>+		if (!fan_max &amp;&amp; config-&gt;fan_max)</div><div class='add'>+			fan_max = config-&gt;fan_max;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* All options must not be 0 */</div><div class='del'>-	data-&gt;i8k_fan_mult = fan_mult ? : I8K_FAN_MULT;</div><div class='del'>-	data-&gt;i8k_fan_max = fan_max ? : I8K_FAN_HIGH;</div><div class='del'>-	data-&gt;i8k_pwm_mult = DIV_ROUND_UP(255, data-&gt;i8k_fan_max);</div><div class='del'>-</div><div class='del'>-	fan_control = dmi_first_match(i8k_whitelist_fan_control);</div><div class='del'>-	if (fan_control &amp;&amp; fan_control-&gt;driver_data) {</div><div class='del'>-		const struct i8k_fan_control_data *control = fan_control-&gt;driver_data;</div><div class='add'>+	id = dmi_first_match(i8k_whitelist_fan_control);</div><div class='add'>+	if (id &amp;&amp; id-&gt;driver_data) {</div><div class='add'>+		control = id-&gt;driver_data;</div><div class='add'>+		manual_fan = control-&gt;manual_fan;</div><div class='add'>+		auto_fan = control-&gt;auto_fan;</div><div class='ctx'> </div><div class='del'>-		data-&gt;manual_fan = control-&gt;manual_fan;</div><div class='del'>-		data-&gt;auto_fan = control-&gt;auto_fan;</div><div class='del'>-		dev_info(&amp;pdev-&gt;dev, "enabling support for setting automatic/manual fan control\n");</div><div class='add'>+		pr_info("Enabling support for setting automatic/manual fan control\n");</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	ret = dell_smm_init_hwmon(&amp;pdev-&gt;dev);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	i8k_init_procfs(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct platform_driver dell_smm_driver = {</div><div class='del'>-	.driver		= {</div><div class='del'>-		.name	= KBUILD_MODNAME,</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct platform_device *dell_smm_device;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Probe for the presence of a supported laptop.</div><div class='del'>- */</div><div class='del'>-static int __init i8k_init(void)</div><div class='add'>+static int __init dell_smm_legacy_check(void)</div><div class='ctx'> {</div><div class='del'>-	/*</div><div class='del'>-	 * Get DMI information</div><div class='del'>-	 */</div><div class='ctx'> 	if (!dmi_check_system(i8k_dmi_table)) {</div><div class='ctx'> 		if (!ignore_dmi &amp;&amp; !force)</div><div class='ctx'> 			return -ENODEV;</div><div class='ctx'> </div><div class='del'>-		pr_info("not running on a supported Dell system.\n");</div><div class='add'>+		pr_info("Probing for legacy SMM handler on unsupported machine\n");</div><div class='ctx'> 		pr_info("vendor=%s, model=%s, version=%s\n",</div><div class='ctx'> 			i8k_get_dmi_data(DMI_SYS_VENDOR),</div><div class='ctx'> 			i8k_get_dmi_data(DMI_PRODUCT_NAME),</div><div class='ctx'> 			i8k_get_dmi_data(DMI_BIOS_VERSION));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Get SMM Dell signature</div><div class='del'>-	 */</div><div class='del'>-	if (i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG1) &amp;&amp;</div><div class='del'>-	    i8k_get_dell_signature(I8K_SMM_GET_DELL_SIG2)) {</div><div class='add'>+	if (dell_smm_get_signature(&amp;i8k_smm_ops, I8K_SMM_GET_DELL_SIG1) &amp;&amp;</div><div class='add'>+	    dell_smm_get_signature(&amp;i8k_smm_ops, I8K_SMM_GET_DELL_SIG2)) {</div><div class='ctx'> 		if (!force)</div><div class='ctx'> 			return -ENODEV;</div><div class='ctx'> </div><div class='del'>-		pr_err("Unable to get Dell SMM signature\n");</div><div class='add'>+		pr_warn("Forcing legacy SMM calls on a possibly incompatible machine\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __init i8k_init(void)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dell_smm_init_dmi();</div><div class='add'>+</div><div class='add'>+	ret = dell_smm_legacy_check();</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		/*</div><div class='add'>+		 * On modern machines, SMM communication happens over WMI, meaning</div><div class='add'>+		 * the SMM handler might not react to legacy SMM calls.</div><div class='add'>+		 */</div><div class='add'>+		return wmi_driver_register(&amp;dell_smm_wmi_driver);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dell_smm_device = platform_create_bundle(&amp;dell_smm_driver, dell_smm_probe, NULL, 0, NULL,</div><div class='hunk'>@@ -1461,8 +1687,12 @@ static int __init i8k_init(void)</div><div class='ctx'> </div><div class='ctx'> static void __exit i8k_exit(void)</div><div class='ctx'> {</div><div class='del'>-	platform_device_unregister(dell_smm_device);</div><div class='del'>-	platform_driver_unregister(&amp;dell_smm_driver);</div><div class='add'>+	if (dell_smm_device) {</div><div class='add'>+		platform_device_unregister(dell_smm_device);</div><div class='add'>+		platform_driver_unregister(&amp;dell_smm_driver);</div><div class='add'>+	} else {</div><div class='add'>+		wmi_driver_unregister(&amp;dell_smm_wmi_driver);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> module_init(i8k_init);</div><div class='head'>diff --git a/drivers/hwmon/emc1403.c b/drivers/hwmon/emc1403.c<br/>index bb7c859e799d..1332e4ac078c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/emc1403.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/emc1403.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/emc1403.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/emc1403.c</a></div><div class='hunk'>@@ -346,6 +346,9 @@ static int emc1403_detect(struct i2c_client *client,</div><div class='ctx'> 	case 0x27:</div><div class='ctx'> 		strscpy(info-&gt;type, "emc1424", I2C_NAME_SIZE);</div><div class='ctx'> 		break;</div><div class='add'>+	case 0x60:</div><div class='add'>+		strscpy(info-&gt;type, "emc1442", I2C_NAME_SIZE);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -430,7 +433,7 @@ static int emc1403_probe(struct i2c_client *client)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const unsigned short emc1403_address_list[] = {</div><div class='del'>-	0x18, 0x1c, 0x29, 0x4c, 0x4d, 0x5c, I2C_CLIENT_END</div><div class='add'>+	0x18, 0x1c, 0x29, 0x3c, 0x4c, 0x4d, 0x5c, I2C_CLIENT_END</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Last digit of chip name indicates number of channels */</div><div class='hunk'>@@ -444,6 +447,7 @@ static const struct i2c_device_id emc1403_idtable[] = {</div><div class='ctx'> 	{ "emc1422", emc1402 },</div><div class='ctx'> 	{ "emc1423", emc1403 },</div><div class='ctx'> 	{ "emc1424", emc1404 },</div><div class='add'>+	{ "emc1442", emc1402 },</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, emc1403_idtable);</div><div class='head'>diff --git a/drivers/hwmon/gigabyte_waterforce.c b/drivers/hwmon/gigabyte_waterforce.c<br/>new file mode 100644<br/>index 000000000000..85e523775714<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/gigabyte_waterforce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/gigabyte_waterforce.c</a></div><div class='hunk'>@@ -0,0 +1,430 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * hwmon driver for Gigabyte AORUS Waterforce AIO CPU coolers: X240, X280 and X360.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 Aleksa Savic &lt;savicaleksa83@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/hid.h&gt;</div><div class='add'>+#include &lt;linux/hwmon.h&gt;</div><div class='add'>+#include &lt;linux/jiffies.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#define DRIVER_NAME	"gigabyte_waterforce"</div><div class='add'>+</div><div class='add'>+#define USB_VENDOR_ID_GIGABYTE		0x1044</div><div class='add'>+#define USB_PRODUCT_ID_WATERFORCE	0x7a4d	/* Gigabyte AORUS WATERFORCE X240, X280 and X360 */</div><div class='add'>+</div><div class='add'>+#define STATUS_VALIDITY		(2 * 1000)	/* ms */</div><div class='add'>+#define MAX_REPORT_LENGTH	6144</div><div class='add'>+</div><div class='add'>+#define WATERFORCE_TEMP_SENSOR	0xD</div><div class='add'>+#define WATERFORCE_FAN_SPEED	0x02</div><div class='add'>+#define WATERFORCE_PUMP_SPEED	0x05</div><div class='add'>+#define WATERFORCE_FAN_DUTY	0x08</div><div class='add'>+#define WATERFORCE_PUMP_DUTY	0x09</div><div class='add'>+</div><div class='add'>+/* Control commands, inner offsets and lengths */</div><div class='add'>+static const u8 get_status_cmd[] = { 0x99, 0xDA };</div><div class='add'>+</div><div class='add'>+#define FIRMWARE_VER_START_OFFSET_1	2</div><div class='add'>+#define FIRMWARE_VER_START_OFFSET_2	3</div><div class='add'>+static const u8 get_firmware_ver_cmd[] = { 0x99, 0xD6 };</div><div class='add'>+</div><div class='add'>+/* Command lengths */</div><div class='add'>+#define GET_STATUS_CMD_LENGTH		2</div><div class='add'>+#define GET_FIRMWARE_VER_CMD_LENGTH	2</div><div class='add'>+</div><div class='add'>+static const char *const waterforce_temp_label[] = {</div><div class='add'>+	"Coolant temp"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char *const waterforce_speed_label[] = {</div><div class='add'>+	"Fan speed",</div><div class='add'>+	"Pump speed"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct waterforce_data {</div><div class='add'>+	struct hid_device *hdev;</div><div class='add'>+	struct device *hwmon_dev;</div><div class='add'>+	struct dentry *debugfs;</div><div class='add'>+	/* For locking access to buffer */</div><div class='add'>+	struct mutex buffer_lock;</div><div class='add'>+	/* For queueing multiple readers */</div><div class='add'>+	struct mutex status_report_request_mutex;</div><div class='add'>+	/* For reinitializing the completion below */</div><div class='add'>+	spinlock_t status_report_request_lock;</div><div class='add'>+	struct completion status_report_received;</div><div class='add'>+	struct completion fw_version_processed;</div><div class='add'>+</div><div class='add'>+	/* Sensor data */</div><div class='add'>+	s32 temp_input[1];</div><div class='add'>+	u16 speed_input[2];	/* Fan and pump speed in RPM */</div><div class='add'>+	u8 duty_input[2];	/* Fan and pump duty in 0-100% */</div><div class='add'>+</div><div class='add'>+	u8 *buffer;</div><div class='add'>+	int firmware_version;</div><div class='add'>+	unsigned long updated;	/* jiffies */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static umode_t waterforce_is_visible(const void *data,</div><div class='add'>+				     enum hwmon_sensor_types type, u32 attr, int channel)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_temp:</div><div class='add'>+		switch (attr) {</div><div class='add'>+		case hwmon_temp_label:</div><div class='add'>+		case hwmon_temp_input:</div><div class='add'>+			return 0444;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_fan:</div><div class='add'>+		switch (attr) {</div><div class='add'>+		case hwmon_fan_label:</div><div class='add'>+		case hwmon_fan_input:</div><div class='add'>+			return 0444;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_pwm:</div><div class='add'>+		switch (attr) {</div><div class='add'>+		case hwmon_pwm_input:</div><div class='add'>+			return 0444;</div><div class='add'>+		default:</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Writes the command to the device with the rest of the report filled with zeroes */</div><div class='add'>+static int waterforce_write_expanded(struct waterforce_data *priv, const u8 *cmd, int cmd_length)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;priv-&gt;buffer_lock);</div><div class='add'>+</div><div class='add'>+	memcpy_and_pad(priv-&gt;buffer, MAX_REPORT_LENGTH, cmd, cmd_length, 0x00);</div><div class='add'>+	ret = hid_hw_output_report(priv-&gt;hdev, priv-&gt;buffer, MAX_REPORT_LENGTH);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;buffer_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int waterforce_get_status(struct waterforce_data *priv)</div><div class='add'>+{</div><div class='add'>+	int ret = mutex_lock_interruptible(&amp;priv-&gt;status_report_request_mutex);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!time_after(jiffies, priv-&gt;updated + msecs_to_jiffies(STATUS_VALIDITY))) {</div><div class='add'>+		/* Data is up to date */</div><div class='add'>+		goto unlock_and_return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Disable raw event parsing for a moment to safely reinitialize the</div><div class='add'>+	 * completion. Reinit is done because hidraw could have triggered</div><div class='add'>+	 * the raw event parsing and marked the priv-&gt;status_report_received</div><div class='add'>+	 * completion as done.</div><div class='add'>+	 */</div><div class='add'>+	spin_lock_bh(&amp;priv-&gt;status_report_request_lock);</div><div class='add'>+	reinit_completion(&amp;priv-&gt;status_report_received);</div><div class='add'>+	spin_unlock_bh(&amp;priv-&gt;status_report_request_lock);</div><div class='add'>+</div><div class='add'>+	/* Send command for getting status */</div><div class='add'>+	ret = waterforce_write_expanded(priv, get_status_cmd, GET_STATUS_CMD_LENGTH);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wait_for_completion_interruptible_timeout(&amp;priv-&gt;status_report_received,</div><div class='add'>+							msecs_to_jiffies(STATUS_VALIDITY));</div><div class='add'>+	if (ret == 0)</div><div class='add'>+		ret = -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+unlock_and_return:</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;status_report_request_mutex);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int waterforce_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='add'>+			   u32 attr, int channel, long *val)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv = dev_get_drvdata(dev);</div><div class='add'>+	int ret = waterforce_get_status(priv);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_temp:</div><div class='add'>+		*val = priv-&gt;temp_input[channel];</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_fan:</div><div class='add'>+		*val = priv-&gt;speed_input[channel];</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_pwm:</div><div class='add'>+		switch (attr) {</div><div class='add'>+		case hwmon_pwm_input:</div><div class='add'>+			*val = DIV_ROUND_CLOSEST(priv-&gt;duty_input[channel] * 255, 100);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;	/* unreachable */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int waterforce_read_string(struct device *dev, enum hwmon_sensor_types type,</div><div class='add'>+				  u32 attr, int channel, const char **str)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case hwmon_temp:</div><div class='add'>+		*str = waterforce_temp_label[channel];</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_fan:</div><div class='add'>+		*str = waterforce_speed_label[channel];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;	/* unreachable */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int waterforce_get_fw_ver(struct hid_device *hdev)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv = hid_get_drvdata(hdev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = waterforce_write_expanded(priv, get_firmware_ver_cmd, GET_FIRMWARE_VER_CMD_LENGTH);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wait_for_completion_interruptible_timeout(&amp;priv-&gt;fw_version_processed,</div><div class='add'>+							msecs_to_jiffies(STATUS_VALIDITY));</div><div class='add'>+	if (ret == 0)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	else if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hwmon_ops waterforce_hwmon_ops = {</div><div class='add'>+	.is_visible = waterforce_is_visible,</div><div class='add'>+	.read = waterforce_read,</div><div class='add'>+	.read_string = waterforce_read_string</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwmon_channel_info *waterforce_info[] = {</div><div class='add'>+	HWMON_CHANNEL_INFO(temp,</div><div class='add'>+			   HWMON_T_INPUT | HWMON_T_LABEL),</div><div class='add'>+	HWMON_CHANNEL_INFO(fan,</div><div class='add'>+			   HWMON_F_INPUT | HWMON_F_LABEL,</div><div class='add'>+			   HWMON_F_INPUT | HWMON_F_LABEL),</div><div class='add'>+	HWMON_CHANNEL_INFO(pwm,</div><div class='add'>+			   HWMON_PWM_INPUT,</div><div class='add'>+			   HWMON_PWM_INPUT),</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwmon_chip_info waterforce_chip_info = {</div><div class='add'>+	.ops = &amp;waterforce_hwmon_ops,</div><div class='add'>+	.info = waterforce_info,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int waterforce_raw_event(struct hid_device *hdev, struct hid_report *report, u8 *data,</div><div class='add'>+				int size)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv = hid_get_drvdata(hdev);</div><div class='add'>+</div><div class='add'>+	if (data[0] == get_firmware_ver_cmd[0] &amp;&amp; data[1] == get_firmware_ver_cmd[1]) {</div><div class='add'>+		/* Received a firmware version report */</div><div class='add'>+		priv-&gt;firmware_version =</div><div class='add'>+		    data[FIRMWARE_VER_START_OFFSET_1] * 10 + data[FIRMWARE_VER_START_OFFSET_2];</div><div class='add'>+</div><div class='add'>+		if (!completion_done(&amp;priv-&gt;fw_version_processed))</div><div class='add'>+			complete_all(&amp;priv-&gt;fw_version_processed);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (data[0] != get_status_cmd[0] || data[1] != get_status_cmd[1])</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	priv-&gt;temp_input[0] = data[WATERFORCE_TEMP_SENSOR] * 1000;</div><div class='add'>+	priv-&gt;speed_input[0] = get_unaligned_le16(data + WATERFORCE_FAN_SPEED);</div><div class='add'>+	priv-&gt;speed_input[1] = get_unaligned_le16(data + WATERFORCE_PUMP_SPEED);</div><div class='add'>+	priv-&gt;duty_input[0] = data[WATERFORCE_FAN_DUTY];</div><div class='add'>+	priv-&gt;duty_input[1] = data[WATERFORCE_PUMP_DUTY];</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;priv-&gt;status_report_request_lock);</div><div class='add'>+	if (!completion_done(&amp;priv-&gt;status_report_received))</div><div class='add'>+		complete_all(&amp;priv-&gt;status_report_received);</div><div class='add'>+	spin_unlock(&amp;priv-&gt;status_report_request_lock);</div><div class='add'>+</div><div class='add'>+	priv-&gt;updated = jiffies;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int firmware_version_show(struct seq_file *seqf, void *unused)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv = seqf-&gt;private;</div><div class='add'>+</div><div class='add'>+	seq_printf(seqf, "%u\n", priv-&gt;firmware_version);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+DEFINE_SHOW_ATTRIBUTE(firmware_version);</div><div class='add'>+</div><div class='add'>+static void waterforce_debugfs_init(struct waterforce_data *priv)</div><div class='add'>+{</div><div class='add'>+	char name[64];</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;firmware_version)</div><div class='add'>+		return;	/* There's nothing to show in debugfs */</div><div class='add'>+</div><div class='add'>+	scnprintf(name, sizeof(name), "%s-%s", DRIVER_NAME, dev_name(&amp;priv-&gt;hdev-&gt;dev));</div><div class='add'>+</div><div class='add'>+	priv-&gt;debugfs = debugfs_create_dir(name, NULL);</div><div class='add'>+	debugfs_create_file("firmware_version", 0444, priv-&gt;debugfs, priv, &amp;firmware_version_fops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int waterforce_probe(struct hid_device *hdev, const struct hid_device_id *id)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(&amp;hdev-&gt;dev, sizeof(*priv), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;hdev = hdev;</div><div class='add'>+	hid_set_drvdata(hdev, priv);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Initialize priv-&gt;updated to STATUS_VALIDITY seconds in the past, making</div><div class='add'>+	 * the initial empty data invalid for waterforce_read() without the need for</div><div class='add'>+	 * a special case there.</div><div class='add'>+	 */</div><div class='add'>+	priv-&gt;updated = jiffies - msecs_to_jiffies(STATUS_VALIDITY);</div><div class='add'>+</div><div class='add'>+	ret = hid_parse(hdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "hid parse failed with %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enable hidraw so existing user-space tools can continue to work.</div><div class='add'>+	 */</div><div class='add'>+	ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "hid hw start failed with %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = hid_hw_open(hdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		hid_err(hdev, "hid hw open failed with %d\n", ret);</div><div class='add'>+		goto fail_and_stop;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	priv-&gt;buffer = devm_kzalloc(&amp;hdev-&gt;dev, MAX_REPORT_LENGTH, GFP_KERNEL);</div><div class='add'>+	if (!priv-&gt;buffer) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto fail_and_close;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;priv-&gt;status_report_request_mutex);</div><div class='add'>+	mutex_init(&amp;priv-&gt;buffer_lock);</div><div class='add'>+	spin_lock_init(&amp;priv-&gt;status_report_request_lock);</div><div class='add'>+	init_completion(&amp;priv-&gt;status_report_received);</div><div class='add'>+	init_completion(&amp;priv-&gt;fw_version_processed);</div><div class='add'>+</div><div class='add'>+	hid_device_io_start(hdev);</div><div class='add'>+	ret = waterforce_get_fw_ver(hdev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		hid_warn(hdev, "fw version request failed with %d\n", ret);</div><div class='add'>+</div><div class='add'>+	priv-&gt;hwmon_dev = hwmon_device_register_with_info(&amp;hdev-&gt;dev, "waterforce",</div><div class='add'>+							  priv, &amp;waterforce_chip_info, NULL);</div><div class='add'>+	if (IS_ERR(priv-&gt;hwmon_dev)) {</div><div class='add'>+		ret = PTR_ERR(priv-&gt;hwmon_dev);</div><div class='add'>+		hid_err(hdev, "hwmon registration failed with %d\n", ret);</div><div class='add'>+		goto fail_and_close;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	waterforce_debugfs_init(priv);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail_and_close:</div><div class='add'>+	hid_hw_close(hdev);</div><div class='add'>+fail_and_stop:</div><div class='add'>+	hid_hw_stop(hdev);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void waterforce_remove(struct hid_device *hdev)</div><div class='add'>+{</div><div class='add'>+	struct waterforce_data *priv = hid_get_drvdata(hdev);</div><div class='add'>+</div><div class='add'>+	debugfs_remove_recursive(priv-&gt;debugfs);</div><div class='add'>+	hwmon_device_unregister(priv-&gt;hwmon_dev);</div><div class='add'>+</div><div class='add'>+	hid_hw_close(hdev);</div><div class='add'>+	hid_hw_stop(hdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hid_device_id waterforce_table[] = {</div><div class='add'>+	{ HID_USB_DEVICE(USB_VENDOR_ID_GIGABYTE, USB_PRODUCT_ID_WATERFORCE) },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+MODULE_DEVICE_TABLE(hid, waterforce_table);</div><div class='add'>+</div><div class='add'>+static struct hid_driver waterforce_driver = {</div><div class='add'>+	.name = "waterforce",</div><div class='add'>+	.id_table = waterforce_table,</div><div class='add'>+	.probe = waterforce_probe,</div><div class='add'>+	.remove = waterforce_remove,</div><div class='add'>+	.raw_event = waterforce_raw_event,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init waterforce_init(void)</div><div class='add'>+{</div><div class='add'>+	return hid_register_driver(&amp;waterforce_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void __exit waterforce_exit(void)</div><div class='add'>+{</div><div class='add'>+	hid_unregister_driver(&amp;waterforce_driver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* When compiled into the kernel, initialize after the HID bus */</div><div class='add'>+late_initcall(waterforce_init);</div><div class='add'>+module_exit(waterforce_exit);</div><div class='add'>+</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Aleksa Savic &lt;savicaleksa83@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Hwmon driver for Gigabyte AORUS Waterforce AIO coolers");</div><div class='head'>diff --git a/drivers/hwmon/hp-wmi-sensors.c b/drivers/hwmon/hp-wmi-sensors.c<br/>index 17ae62f88bbf..b5325d0e72b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/hp-wmi-sensors.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/hp-wmi-sensors.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/hp-wmi-sensors.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/hp-wmi-sensors.c</a></div><div class='hunk'>@@ -17,6 +17,8 @@</div><div class='ctx'>  *     Available: https://github.com/linuxhw/ACPI</div><div class='ctx'>  * [4] P. Rohár, "bmfdec - Decompile binary MOF file (BMF) from WMI buffer",</div><div class='ctx'>  *     2017. [Online]. Available: https://github.com/pali/bmfdec</div><div class='add'>+ * [5] Microsoft Corporation, "Driver-Defined WMI Data Items", 2017. [Online].</div><div class='add'>+ *     Available: https://learn.microsoft.com/en-us/windows-hardware/drivers/kernel/driver-defined-wmi-data-items</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='hunk'>@@ -24,6 +26,7 @@</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='ctx'> #include &lt;linux/jiffies.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/nls.h&gt;</div><div class='ctx'> #include &lt;linux/units.h&gt;</div><div class='ctx'> #include &lt;linux/wmi.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -395,6 +398,50 @@ struct hp_wmi_sensors {</div><div class='ctx'> 	struct mutex lock;	/* Lock polling WMI and driver state changes. */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static bool is_raw_wmi_string(const u8 *pointer, u32 length)</div><div class='add'>+{</div><div class='add'>+	const u16 *ptr;</div><div class='add'>+	u16 len;</div><div class='add'>+</div><div class='add'>+	/* WMI strings are length-prefixed UTF-16 [5]. */</div><div class='add'>+	if (length &lt;= sizeof(*ptr))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	length -= sizeof(*ptr);</div><div class='add'>+	ptr = (const u16 *)pointer;</div><div class='add'>+	len = *ptr;</div><div class='add'>+</div><div class='add'>+	return len &lt;= length &amp;&amp; !(len &amp; 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static char *convert_raw_wmi_string(const u8 *buf)</div><div class='add'>+{</div><div class='add'>+	const wchar_t *src;</div><div class='add'>+	unsigned int cps;</div><div class='add'>+	unsigned int len;</div><div class='add'>+	char *dst;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	src = (const wchar_t *)buf;</div><div class='add'>+</div><div class='add'>+	/* Count UTF-16 code points. Exclude trailing null padding. */</div><div class='add'>+	cps = *src / sizeof(*src);</div><div class='add'>+	while (cps &amp;&amp; !src[cps])</div><div class='add'>+		cps--;</div><div class='add'>+</div><div class='add'>+	/* Each code point becomes up to 3 UTF-8 characters. */</div><div class='add'>+	len = min(cps * 3, HP_WMI_MAX_STR_SIZE - 1);</div><div class='add'>+</div><div class='add'>+	dst = kmalloc((len + 1) * sizeof(*dst), GFP_KERNEL);</div><div class='add'>+	if (!dst)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	i = utf16s_to_utf8s(++src, cps, UTF16_LITTLE_ENDIAN, dst, len);</div><div class='add'>+	dst[i] = '\0';</div><div class='add'>+</div><div class='add'>+	return dst;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* hp_wmi_strdup - devm_kstrdup, but length-limited */</div><div class='ctx'> static char *hp_wmi_strdup(struct device *dev, const char *src)</div><div class='ctx'> {</div><div class='hunk'>@@ -412,6 +459,23 @@ static char *hp_wmi_strdup(struct device *dev, const char *src)</div><div class='ctx'> 	return dst;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* hp_wmi_wstrdup - hp_wmi_strdup, but for a raw WMI string */</div><div class='add'>+static char *hp_wmi_wstrdup(struct device *dev, const u8 *buf)</div><div class='add'>+{</div><div class='add'>+	char *src;</div><div class='add'>+	char *dst;</div><div class='add'>+</div><div class='add'>+	src = convert_raw_wmi_string(buf);</div><div class='add'>+	if (!src)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	dst = hp_wmi_strdup(dev, strim(src));	/* Note: Copy is trimmed. */</div><div class='add'>+</div><div class='add'>+	kfree(src);</div><div class='add'>+</div><div class='add'>+	return dst;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * hp_wmi_get_wobj - poll WMI for a WMI object instance</div><div class='ctx'>  * @guid: WMI object GUID</div><div class='hunk'>@@ -462,8 +526,14 @@ static int check_wobj(const union acpi_object *wobj,</div><div class='ctx'> 	for (prop = 0; prop &lt;= last_prop; prop++) {</div><div class='ctx'> 		type = elements[prop].type;</div><div class='ctx'> 		valid_type = property_map[prop];</div><div class='del'>-		if (type != valid_type)</div><div class='add'>+		if (type != valid_type) {</div><div class='add'>+			if (type == ACPI_TYPE_BUFFER &amp;&amp;</div><div class='add'>+			    valid_type == ACPI_TYPE_STRING &amp;&amp;</div><div class='add'>+			    is_raw_wmi_string(elements[prop].buffer.pointer,</div><div class='add'>+					      elements[prop].buffer.length))</div><div class='add'>+				continue;</div><div class='ctx'> 			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -480,7 +550,9 @@ static int extract_acpi_value(struct device *dev,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case ACPI_TYPE_STRING:</div><div class='del'>-		*out_string = hp_wmi_strdup(dev, strim(element-&gt;string.pointer));</div><div class='add'>+		*out_string = element-&gt;type == ACPI_TYPE_BUFFER ?</div><div class='add'>+			hp_wmi_wstrdup(dev, element-&gt;buffer.pointer) :</div><div class='add'>+			hp_wmi_strdup(dev, strim(element-&gt;string.pointer));</div><div class='ctx'> 		if (!*out_string)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -861,7 +933,9 @@ update_numeric_sensor_from_wobj(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	const union acpi_object *elements;</div><div class='ctx'> 	const union acpi_object *element;</div><div class='del'>-	const char *string;</div><div class='add'>+	const char *new_string;</div><div class='add'>+	char *trimmed;</div><div class='add'>+	char *string;</div><div class='ctx'> 	bool is_new;</div><div class='ctx'> 	int offset;</div><div class='ctx'> 	u8 size;</div><div class='hunk'>@@ -885,11 +959,21 @@ update_numeric_sensor_from_wobj(struct device *dev,</div><div class='ctx'> 	offset = is_new ? size - 1 : -2;</div><div class='ctx'> </div><div class='ctx'> 	element = &amp;elements[HP_WMI_PROPERTY_CURRENT_STATE + offset];</div><div class='del'>-	string = strim(element-&gt;string.pointer);</div><div class='del'>-</div><div class='del'>-	if (strcmp(string, nsensor-&gt;current_state)) {</div><div class='del'>-		devm_kfree(dev, nsensor-&gt;current_state);</div><div class='del'>-		nsensor-&gt;current_state = hp_wmi_strdup(dev, string);</div><div class='add'>+	string = element-&gt;type == ACPI_TYPE_BUFFER ?</div><div class='add'>+		convert_raw_wmi_string(element-&gt;buffer.pointer) :</div><div class='add'>+		element-&gt;string.pointer;</div><div class='add'>+</div><div class='add'>+	if (string) {</div><div class='add'>+		trimmed = strim(string);</div><div class='add'>+		if (strcmp(trimmed, nsensor-&gt;current_state)) {</div><div class='add'>+			new_string = hp_wmi_strdup(dev, trimmed);</div><div class='add'>+			if (new_string) {</div><div class='add'>+				devm_kfree(dev, nsensor-&gt;current_state);</div><div class='add'>+				nsensor-&gt;current_state = new_string;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (element-&gt;type == ACPI_TYPE_BUFFER)</div><div class='add'>+			kfree(string);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Old variant: -2 (not -1) because it lacks the Size property. */</div><div class='hunk'>@@ -996,11 +1080,15 @@ static int check_event_wobj(const union acpi_object *wobj)</div><div class='ctx'> 			  HP_WMI_EVENT_PROPERTY_STATUS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int populate_event_from_wobj(struct hp_wmi_event *event,</div><div class='add'>+static int populate_event_from_wobj(struct device *dev,</div><div class='add'>+				    struct hp_wmi_event *event,</div><div class='ctx'> 				    union acpi_object *wobj)</div><div class='ctx'> {</div><div class='ctx'> 	int prop = HP_WMI_EVENT_PROPERTY_NAME;</div><div class='ctx'> 	union acpi_object *element;</div><div class='add'>+	acpi_object_type type;</div><div class='add'>+	char *string;</div><div class='add'>+	u32 value;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = check_event_wobj(wobj);</div><div class='hunk'>@@ -1009,20 +1097,24 @@ static int populate_event_from_wobj(struct hp_wmi_event *event,</div><div class='ctx'> </div><div class='ctx'> 	element = wobj-&gt;package.elements;</div><div class='ctx'> </div><div class='del'>-	/* Extracted strings are NOT device-managed copies. */</div><div class='del'>-</div><div class='ctx'> 	for (; prop &lt;= HP_WMI_EVENT_PROPERTY_CATEGORY; prop++, element++) {</div><div class='add'>+		type = hp_wmi_event_property_map[prop];</div><div class='add'>+</div><div class='add'>+		err = extract_acpi_value(dev, element, type, &amp;value, &amp;string);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='ctx'> 		switch (prop) {</div><div class='ctx'> 		case HP_WMI_EVENT_PROPERTY_NAME:</div><div class='del'>-			event-&gt;name = strim(element-&gt;string.pointer);</div><div class='add'>+			event-&gt;name = string;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		case HP_WMI_EVENT_PROPERTY_DESCRIPTION:</div><div class='del'>-			event-&gt;description = strim(element-&gt;string.pointer);</div><div class='add'>+			event-&gt;description = string;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		case HP_WMI_EVENT_PROPERTY_CATEGORY:</div><div class='del'>-			event-&gt;category = element-&gt;integer.value;</div><div class='add'>+			event-&gt;category = value;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		default:</div><div class='hunk'>@@ -1511,8 +1603,8 @@ static void hp_wmi_notify(u32 value, void *context)</div><div class='ctx'> 	struct acpi_buffer out = { ACPI_ALLOCATE_BUFFER, NULL };</div><div class='ctx'> 	struct hp_wmi_sensors *state = context;</div><div class='ctx'> 	struct device *dev = &amp;state-&gt;wdev-&gt;dev;</div><div class='add'>+	struct hp_wmi_event event = {};</div><div class='ctx'> 	struct hp_wmi_info *fan_info;</div><div class='del'>-	struct hp_wmi_event event;</div><div class='ctx'> 	union acpi_object *wobj;</div><div class='ctx'> 	acpi_status err;</div><div class='ctx'> 	int event_type;</div><div class='hunk'>@@ -1546,7 +1638,7 @@ static void hp_wmi_notify(u32 value, void *context)</div><div class='ctx'> </div><div class='ctx'> 	wobj = out.pointer;</div><div class='ctx'> </div><div class='del'>-	err = populate_event_from_wobj(&amp;event, wobj);</div><div class='add'>+	err = populate_event_from_wobj(dev, &amp;event, wobj);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_warn(dev, "Bad event data (ACPI type %d)\n", wobj-&gt;type);</div><div class='ctx'> 		goto out_free_wobj;</div><div class='hunk'>@@ -1577,6 +1669,9 @@ static void hp_wmi_notify(u32 value, void *context)</div><div class='ctx'> out_free_wobj:</div><div class='ctx'> 	kfree(wobj);</div><div class='ctx'> </div><div class='add'>+	devm_kfree(dev, event.name);</div><div class='add'>+	devm_kfree(dev, event.description);</div><div class='add'>+</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;state-&gt;lock);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c<br/>index bae0becfa24b..8092312c0a87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/k10temp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/k10temp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/k10temp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/k10temp.c</a></div><div class='hunk'>@@ -455,6 +455,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)</div><div class='ctx'> </div><div class='ctx'> 		switch (boot_cpu_data.x86_model) {</div><div class='ctx'> 		case 0x0 ... 0x1:	/* Zen3 SP3/TR */</div><div class='add'>+		case 0x8:		/* Zen3 TR Chagall */</div><div class='ctx'> 		case 0x21:		/* Zen3 Ryzen Desktop */</div><div class='ctx'> 		case 0x50 ... 0x5f:	/* Green Sardine */</div><div class='ctx'> 			data-&gt;ccd_offset = 0x154;</div><div class='head'>diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c<br/>index 5b2ea05c951e..e00750718536 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/lm75.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/lm75.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/lm75.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/lm75.c</a></div><div class='hunk'>@@ -7,11 +7,11 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/jiffies.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='del'>-#include &lt;linux/hwmon-sysfs.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='hunk'>@@ -25,6 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> enum lm75_type {		/* keep sorted in alphabetical order */</div><div class='ctx'> 	adt75,</div><div class='add'>+	as6200,</div><div class='ctx'> 	at30ts74,</div><div class='ctx'> 	ds1775,</div><div class='ctx'> 	ds75,</div><div class='hunk'>@@ -55,6 +56,7 @@ enum lm75_type {		/* keep sorted in alphabetical order */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct lm75_params - lm75 configuration parameters.</div><div class='add'>+ * @config_reg_16bits:	Configure register size is 2 bytes.</div><div class='ctx'>  * @set_mask:		Bits to set in configuration register when configuring</div><div class='ctx'>  *			the chip.</div><div class='ctx'>  * @clr_mask:		Bits to clear in configuration register when configuring</div><div class='hunk'>@@ -75,17 +77,20 @@ enum lm75_type {		/* keep sorted in alphabetical order */</div><div class='ctx'>  * @sample_times:	All the possible sample times to be set. Mandatory if</div><div class='ctx'>  *			num_sample_times is larger than 1. If set, number of</div><div class='ctx'>  *			entries must match num_sample_times.</div><div class='add'>+ * @alarm:		Alarm bit is supported.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> struct lm75_params {</div><div class='del'>-	u8			set_mask;</div><div class='del'>-	u8			clr_mask;</div><div class='add'>+	bool			config_reg_16bits;</div><div class='add'>+	u16			set_mask;</div><div class='add'>+	u16			clr_mask;</div><div class='ctx'> 	u8			default_resolution;</div><div class='ctx'> 	u8			resolution_limits;</div><div class='ctx'> 	const u8		*resolutions;</div><div class='ctx'> 	unsigned int		default_sample_time;</div><div class='ctx'> 	u8			num_sample_times;</div><div class='ctx'> 	const unsigned int	*sample_times;</div><div class='add'>+	bool			alarm;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Addresses scanned */</div><div class='hunk'>@@ -104,8 +109,8 @@ struct lm75_data {</div><div class='ctx'> 	struct i2c_client		*client;</div><div class='ctx'> 	struct regmap			*regmap;</div><div class='ctx'> 	struct regulator		*vs;</div><div class='del'>-	u8				orig_conf;</div><div class='del'>-	u8				current_conf;</div><div class='add'>+	u16				orig_conf;</div><div class='add'>+	u16				current_conf;</div><div class='ctx'> 	u8				resolution;	/* In bits, 9 to 16 */</div><div class='ctx'> 	unsigned int			sample_time;	/* In ms */</div><div class='ctx'> 	enum lm75_type			kind;</div><div class='hunk'>@@ -128,6 +133,15 @@ static const struct lm75_params device_params[] = {</div><div class='ctx'> 		.default_resolution = 12,</div><div class='ctx'> 		.default_sample_time = MSEC_PER_SEC / 10,</div><div class='ctx'> 	},</div><div class='add'>+	[as6200] = {</div><div class='add'>+		.config_reg_16bits = true,</div><div class='add'>+		.set_mask = 0x94C0,	/* 8 sample/s, 4 CF, positive polarity */</div><div class='add'>+		.default_resolution = 12,</div><div class='add'>+		.default_sample_time = 125,</div><div class='add'>+		.num_sample_times = 4,</div><div class='add'>+		.sample_times = (unsigned int []){ 125, 250, 1000, 4000 },</div><div class='add'>+		.alarm = true,</div><div class='add'>+	},</div><div class='ctx'> 	[at30ts74] = {</div><div class='ctx'> 		.set_mask = 3 &lt;&lt; 5,	/* 12-bit mode*/</div><div class='ctx'> 		.default_resolution = 12,</div><div class='hunk'>@@ -255,8 +269,9 @@ static const struct lm75_params device_params[] = {</div><div class='ctx'> 		.resolutions = (u8 []) {9, 10, 11, 12 },</div><div class='ctx'> 	},</div><div class='ctx'> 	[tmp112] = {</div><div class='del'>-		.set_mask = 3 &lt;&lt; 5,	/* 8 samples / second */</div><div class='del'>-		.clr_mask = 1 &lt;&lt; 7,	/* no one-shot mode*/</div><div class='add'>+		.config_reg_16bits = true,</div><div class='add'>+		.set_mask = 0x60C0,	/* 12-bit mode, 8 samples / second */</div><div class='add'>+		.clr_mask = 1 &lt;&lt; 15,	/* no one-shot mode*/</div><div class='ctx'> 		.default_resolution = 12,</div><div class='ctx'> 		.default_sample_time = 125,</div><div class='ctx'> 		.num_sample_times = 4,</div><div class='hunk'>@@ -317,20 +332,23 @@ static inline long lm75_reg_to_mc(s16 temp, u8 resolution)</div><div class='ctx'> 	return ((temp &gt;&gt; (16 - resolution)) * 1000) &gt;&gt; (resolution - 8);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int lm75_write_config(struct lm75_data *data, u8 set_mask,</div><div class='del'>-			     u8 clr_mask)</div><div class='add'>+static int lm75_write_config(struct lm75_data *data, u16 set_mask,</div><div class='add'>+			     u16 clr_mask)</div><div class='ctx'> {</div><div class='del'>-	u8 value;</div><div class='add'>+	unsigned int value;</div><div class='ctx'> </div><div class='del'>-	clr_mask |= LM75_SHUTDOWN;</div><div class='add'>+	clr_mask |= LM75_SHUTDOWN &lt;&lt; (8 * data-&gt;params-&gt;config_reg_16bits);</div><div class='ctx'> 	value = data-&gt;current_conf &amp; ~clr_mask;</div><div class='ctx'> 	value |= set_mask;</div><div class='ctx'> </div><div class='ctx'> 	if (data-&gt;current_conf != value) {</div><div class='ctx'> 		s32 err;</div><div class='del'>-</div><div class='del'>-		err = i2c_smbus_write_byte_data(data-&gt;client, LM75_REG_CONF,</div><div class='del'>-						value);</div><div class='add'>+		if (data-&gt;params-&gt;config_reg_16bits)</div><div class='add'>+			err = regmap_write(data-&gt;regmap, LM75_REG_CONF, value);</div><div class='add'>+		else</div><div class='add'>+			err = i2c_smbus_write_byte_data(data-&gt;client,</div><div class='add'>+							LM75_REG_CONF,</div><div class='add'>+							value);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 		data-&gt;current_conf = value;</div><div class='hunk'>@@ -338,6 +356,27 @@ static int lm75_write_config(struct lm75_data *data, u8 set_mask,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int lm75_read_config(struct lm75_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	unsigned int status;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;params-&gt;config_reg_16bits) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, LM75_REG_CONF, &amp;status);</div><div class='add'>+		return ret ? ret : status;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return i2c_smbus_read_byte_data(data-&gt;client, LM75_REG_CONF);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t lm75_alarm_handler(int irq, void *private)</div><div class='add'>+{</div><div class='add'>+	struct device *hwmon_dev = private;</div><div class='add'>+</div><div class='add'>+	hwmon_notify_event(hwmon_dev, hwmon_temp, hwmon_temp_alarm, 0);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int lm75_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 		     u32 attr, int channel, long *val)</div><div class='ctx'> {</div><div class='hunk'>@@ -366,6 +405,9 @@ static int lm75_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 		case hwmon_temp_max_hyst:</div><div class='ctx'> 			reg = LM75_REG_HYST;</div><div class='ctx'> 			break;</div><div class='add'>+		case hwmon_temp_alarm:</div><div class='add'>+			reg = LM75_REG_CONF;</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -373,7 +415,17 @@ static int lm75_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 		if (err &lt; 0)</div><div class='ctx'> 			return err;</div><div class='ctx'> </div><div class='del'>-		*val = lm75_reg_to_mc(regval, data-&gt;resolution);</div><div class='add'>+		if (attr == hwmon_temp_alarm) {</div><div class='add'>+			switch (data-&gt;kind) {</div><div class='add'>+			case as6200:</div><div class='add'>+				*val = (regval &gt;&gt; 5) &amp; 0x1;</div><div class='add'>+				break;</div><div class='add'>+			default:</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			*val = lm75_reg_to_mc(regval, data-&gt;resolution);</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -436,6 +488,7 @@ static int lm75_update_interval(struct device *dev, long val)</div><div class='ctx'> 			data-&gt;resolution = data-&gt;params-&gt;resolutions[index];</div><div class='ctx'> 		break;</div><div class='ctx'> 	case tmp112:</div><div class='add'>+	case as6200:</div><div class='ctx'> 		err = regmap_read(data-&gt;regmap, LM75_REG_CONF, &amp;reg);</div><div class='ctx'> 		if (err &lt; 0)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -503,6 +556,10 @@ static umode_t lm75_is_visible(const void *data, enum hwmon_sensor_types type,</div><div class='ctx'> 		case hwmon_temp_max:</div><div class='ctx'> 		case hwmon_temp_max_hyst:</div><div class='ctx'> 			return 0644;</div><div class='add'>+		case hwmon_temp_alarm:</div><div class='add'>+			if (config_data-&gt;params-&gt;alarm)</div><div class='add'>+				return 0444;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -515,7 +572,8 @@ static const struct hwmon_channel_info * const lm75_info[] = {</div><div class='ctx'> 	HWMON_CHANNEL_INFO(chip,</div><div class='ctx'> 			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),</div><div class='ctx'> 	HWMON_CHANNEL_INFO(temp,</div><div class='del'>-			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),</div><div class='add'>+			   HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |</div><div class='add'>+			   HWMON_T_ALARM),</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -623,7 +681,7 @@ static int lm75_probe(struct i2c_client *client)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Cache original configuration */</div><div class='del'>-	status = i2c_smbus_read_byte_data(client, LM75_REG_CONF);</div><div class='add'>+	status = lm75_read_config(data);</div><div class='ctx'> 	if (status &lt; 0) {</div><div class='ctx'> 		dev_dbg(dev, "Can't read config? %d\n", status);</div><div class='ctx'> 		return status;</div><div class='hunk'>@@ -646,6 +704,23 @@ static int lm75_probe(struct i2c_client *client)</div><div class='ctx'> 	if (IS_ERR(hwmon_dev))</div><div class='ctx'> 		return PTR_ERR(hwmon_dev);</div><div class='ctx'> </div><div class='add'>+	if (client-&gt;irq) {</div><div class='add'>+		if (data-&gt;params-&gt;alarm) {</div><div class='add'>+			err = devm_request_threaded_irq(dev,</div><div class='add'>+							client-&gt;irq,</div><div class='add'>+							NULL,</div><div class='add'>+							&amp;lm75_alarm_handler,</div><div class='add'>+							IRQF_ONESHOT,</div><div class='add'>+							client-&gt;name,</div><div class='add'>+							hwmon_dev);</div><div class='add'>+			if (err)</div><div class='add'>+				return err;</div><div class='add'>+		} else {</div><div class='add'>+			 /* alarm is only supported for chips with alarm bit */</div><div class='add'>+			dev_err(dev, "alarm interrupt is not supported\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dev_info(dev, "%s: sensor '%s'\n", dev_name(hwmon_dev), client-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -653,6 +728,7 @@ static int lm75_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> static const struct i2c_device_id lm75_ids[] = {</div><div class='ctx'> 	{ "adt75", adt75, },</div><div class='add'>+	{ "as6200", as6200, },</div><div class='ctx'> 	{ "at30ts74", at30ts74, },</div><div class='ctx'> 	{ "ds1775", ds1775, },</div><div class='ctx'> 	{ "ds75", ds75, },</div><div class='hunk'>@@ -690,6 +766,10 @@ static const struct of_device_id __maybe_unused lm75_of_match[] = {</div><div class='ctx'> 		.data = (void *)adt75</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		.compatible = "ams,as6200",</div><div class='add'>+		.data = (void *)as6200</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		.compatible = "atmel,at30ts74",</div><div class='ctx'> 		.data = (void *)at30ts74</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/hwmon/ltc2991.c b/drivers/hwmon/ltc2991.c<br/>index bd63c61129a9..80a6e391f266 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/ltc2991.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/ltc2991.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/ltc2991.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/ltc2991.c</a></div><div class='hunk'>@@ -54,7 +54,6 @@</div><div class='ctx'> #define LTC2991_VCC_CH_NR		0</div><div class='ctx'> </div><div class='ctx'> struct ltc2991_state {</div><div class='del'>-	struct device		*dev;</div><div class='ctx'> 	struct regmap		*regmap;</div><div class='ctx'> 	u32			r_sense_uohm[LTC2991_MAX_CHANNEL];</div><div class='ctx'> 	bool			temp_en[LTC2991_MAX_CHANNEL];</div><div class='hunk'>@@ -283,19 +282,19 @@ static const struct regmap_config ltc2991_regmap_config = {</div><div class='ctx'> 	.max_register = 0x1D,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int ltc2991_init(struct ltc2991_state *st)</div><div class='add'>+static int ltc2991_init(struct ltc2991_state *st, struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fwnode_handle *child;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u32 val, addr;</div><div class='ctx'> 	u8 v5_v8_reg_data = 0, v1_v4_reg_data = 0;</div><div class='ctx'> </div><div class='del'>-	ret = devm_regulator_get_enable(st-&gt;dev, "vcc");</div><div class='add'>+	ret = devm_regulator_get_enable(dev, "vcc");</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(st-&gt;dev, ret,</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='ctx'> 				     "failed to enable regulator\n");</div><div class='ctx'> </div><div class='del'>-	device_for_each_child_node(st-&gt;dev, child) {</div><div class='add'>+	device_for_each_child_node(dev, child) {</div><div class='ctx'> 		ret = fwnode_property_read_u32(child, "reg", &amp;addr);</div><div class='ctx'> 		if (ret &lt; 0) {</div><div class='ctx'> 			fwnode_handle_put(child);</div><div class='hunk'>@@ -312,7 +311,7 @@ static int ltc2991_init(struct ltc2991_state *st)</div><div class='ctx'> 					       &amp;val);</div><div class='ctx'> 		if (!ret) {</div><div class='ctx'> 			if (!val)</div><div class='del'>-				return dev_err_probe(st-&gt;dev, -EINVAL,</div><div class='add'>+				return dev_err_probe(dev, -EINVAL,</div><div class='ctx'> 						     "shunt resistor value cannot be zero\n");</div><div class='ctx'> </div><div class='ctx'> 			st-&gt;r_sense_uohm[addr] = val;</div><div class='hunk'>@@ -361,19 +360,19 @@ static int ltc2991_init(struct ltc2991_state *st)</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_write(st-&gt;regmap, LTC2991_V5_V8_CTRL, v5_v8_reg_data);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(st-&gt;dev, ret,</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='ctx'> 				     "Error: Failed to set V5-V8 CTRL reg.\n");</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_write(st-&gt;regmap, LTC2991_V1_V4_CTRL, v1_v4_reg_data);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(st-&gt;dev, ret,</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='ctx'> 				     "Error: Failed to set V1-V4 CTRL reg.\n");</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_write(st-&gt;regmap, LTC2991_PWM_TH_LSB_T_INT,</div><div class='ctx'> 			   LTC2991_REPEAT_ACQ_EN);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return dev_err_probe(st-&gt;dev, ret,</div><div class='del'>-				     "Error: Failed to set contiuous mode.\n");</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+				     "Error: Failed to set continuous mode.\n");</div><div class='ctx'> </div><div class='ctx'> 	/* Enable all channels and trigger conversions */</div><div class='ctx'> 	return regmap_write(st-&gt;regmap, LTC2991_CH_EN_TRIGGER,</div><div class='hunk'>@@ -392,12 +391,11 @@ static int ltc2991_i2c_probe(struct i2c_client *client)</div><div class='ctx'> 	if (!st)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	st-&gt;dev = &amp;client-&gt;dev;</div><div class='ctx'> 	st-&gt;regmap = devm_regmap_init_i2c(client, &amp;ltc2991_regmap_config);</div><div class='ctx'> 	if (IS_ERR(st-&gt;regmap))</div><div class='ctx'> 		return PTR_ERR(st-&gt;regmap);</div><div class='ctx'> </div><div class='del'>-	ret = ltc2991_init(st);</div><div class='add'>+	ret = ltc2991_init(st, &amp;client-&gt;dev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwmon/max31827.c b/drivers/hwmon/max31827.c<br/>index fd1fed1a797c..4a8c3e37c5d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/max31827.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/max31827.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/max31827.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/max31827.c</a></div><div class='hunk'>@@ -11,7 +11,9 @@</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define MAX31827_T_REG			0x0</div><div class='ctx'> #define MAX31827_CONFIGURATION_REG	0x2</div><div class='hunk'>@@ -22,15 +24,30 @@</div><div class='ctx'> </div><div class='ctx'> #define MAX31827_CONFIGURATION_1SHOT_MASK	BIT(0)</div><div class='ctx'> #define MAX31827_CONFIGURATION_CNV_RATE_MASK	GENMASK(3, 1)</div><div class='add'>+#define MAX31827_CONFIGURATION_TIMEOUT_MASK	BIT(5)</div><div class='add'>+#define MAX31827_CONFIGURATION_RESOLUTION_MASK	GENMASK(7, 6)</div><div class='add'>+#define MAX31827_CONFIGURATION_ALRM_POL_MASK	BIT(8)</div><div class='add'>+#define MAX31827_CONFIGURATION_COMP_INT_MASK	BIT(9)</div><div class='add'>+#define MAX31827_CONFIGURATION_FLT_Q_MASK	GENMASK(11, 10)</div><div class='ctx'> #define MAX31827_CONFIGURATION_U_TEMP_STAT_MASK	BIT(14)</div><div class='ctx'> #define MAX31827_CONFIGURATION_O_TEMP_STAT_MASK	BIT(15)</div><div class='ctx'> </div><div class='add'>+#define MAX31827_ALRM_POL_LOW	0x0</div><div class='add'>+#define MAX31827_ALRM_POL_HIGH	0x1</div><div class='add'>+#define MAX31827_FLT_Q_1	0x0</div><div class='add'>+#define MAX31827_FLT_Q_4	0x2</div><div class='add'>+</div><div class='add'>+#define MAX31827_8_BIT_CNV_TIME		9</div><div class='add'>+#define MAX31827_9_BIT_CNV_TIME		18</div><div class='add'>+#define MAX31827_10_BIT_CNV_TIME	35</div><div class='ctx'> #define MAX31827_12_BIT_CNV_TIME	140</div><div class='ctx'> </div><div class='ctx'> #define MAX31827_16_BIT_TO_M_DGR(x)	(sign_extend32(x, 15) * 1000 / 16)</div><div class='ctx'> #define MAX31827_M_DGR_TO_16_BIT(x)	(((x) &lt;&lt; 4) / 1000)</div><div class='ctx'> #define MAX31827_DEVICE_ENABLE(x)	((x) ? 0xA : 0x0)</div><div class='ctx'> </div><div class='add'>+enum chips { max31827 = 1, max31828, max31829 };</div><div class='add'>+</div><div class='ctx'> enum max31827_cnv {</div><div class='ctx'> 	MAX31827_CNV_1_DIV_64_HZ = 1,</div><div class='ctx'> 	MAX31827_CNV_1_DIV_32_HZ,</div><div class='hunk'>@@ -51,6 +68,27 @@ static const u16 max31827_conversions[] = {</div><div class='ctx'> 	[MAX31827_CNV_8_HZ] = 125,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum max31827_resolution {</div><div class='add'>+	MAX31827_RES_8_BIT = 0,</div><div class='add'>+	MAX31827_RES_9_BIT,</div><div class='add'>+	MAX31827_RES_10_BIT,</div><div class='add'>+	MAX31827_RES_12_BIT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 max31827_resolutions[] = {</div><div class='add'>+	[MAX31827_RES_8_BIT] = 1000,</div><div class='add'>+	[MAX31827_RES_9_BIT] = 500,</div><div class='add'>+	[MAX31827_RES_10_BIT] = 250,</div><div class='add'>+	[MAX31827_RES_12_BIT] = 62,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 max31827_conv_times[] = {</div><div class='add'>+	[MAX31827_RES_8_BIT] = MAX31827_8_BIT_CNV_TIME,</div><div class='add'>+	[MAX31827_RES_9_BIT] = MAX31827_9_BIT_CNV_TIME,</div><div class='add'>+	[MAX31827_RES_10_BIT] = MAX31827_10_BIT_CNV_TIME,</div><div class='add'>+	[MAX31827_RES_12_BIT] = MAX31827_12_BIT_CNV_TIME,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct max31827_state {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Prevent simultaneous access to the i2c client.</div><div class='hunk'>@@ -58,6 +96,8 @@ struct max31827_state {</div><div class='ctx'> 	struct mutex lock;</div><div class='ctx'> 	struct regmap *regmap;</div><div class='ctx'> 	bool enable;</div><div class='add'>+	unsigned int resolution;</div><div class='add'>+	unsigned int update_interval;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct regmap_config max31827_regmap = {</div><div class='hunk'>@@ -67,16 +107,16 @@ static const struct regmap_config max31827_regmap = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int shutdown_write(struct max31827_state *st, unsigned int reg,</div><div class='del'>-			  unsigned int val)</div><div class='add'>+			  unsigned int mask, unsigned int val)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int cfg;</div><div class='ctx'> 	unsigned int cnv_rate;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Before the Temperature Threshold Alarm and Alarm Hysteresis Threshold</div><div class='del'>-	 * register values are changed over I2C, the part must be in shutdown</div><div class='del'>-	 * mode.</div><div class='add'>+	 * Before the Temperature Threshold Alarm, Alarm Hysteresis Threshold</div><div class='add'>+	 * and Resolution bits from Configuration register are changed over I2C,</div><div class='add'>+	 * the part must be in shutdown mode.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * Mutex is used to ensure, that some other process doesn't change the</div><div class='ctx'> 	 * configuration register.</div><div class='hunk'>@@ -84,7 +124,10 @@ static int shutdown_write(struct max31827_state *st, unsigned int reg,</div><div class='ctx'> 	mutex_lock(&amp;st-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (!st-&gt;enable) {</div><div class='del'>-		ret = regmap_write(st-&gt;regmap, reg, val);</div><div class='add'>+		if (!mask)</div><div class='add'>+			ret = regmap_write(st-&gt;regmap, reg, val);</div><div class='add'>+		else</div><div class='add'>+			ret = regmap_update_bits(st-&gt;regmap, reg, mask, val);</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -99,7 +142,11 @@ static int shutdown_write(struct max31827_state *st, unsigned int reg,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='del'>-	ret = regmap_write(st-&gt;regmap, reg, val);</div><div class='add'>+	if (!mask)</div><div class='add'>+		ret = regmap_write(st-&gt;regmap, reg, val);</div><div class='add'>+	else</div><div class='add'>+		ret = regmap_update_bits(st-&gt;regmap, reg, mask, val);</div><div class='add'>+</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -117,7 +164,7 @@ static int write_alarm_val(struct max31827_state *st, unsigned int reg,</div><div class='ctx'> {</div><div class='ctx'> 	val = MAX31827_M_DGR_TO_16_BIT(val);</div><div class='ctx'> </div><div class='del'>-	return shutdown_write(st, reg, val);</div><div class='add'>+	return shutdown_write(st, reg, 0, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static umode_t max31827_is_visible(const void *state,</div><div class='hunk'>@@ -187,9 +234,18 @@ static int max31827_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 					mutex_unlock(&amp;st-&gt;lock);</div><div class='ctx'> 					return ret;</div><div class='ctx'> 				}</div><div class='del'>-</div><div class='del'>-				msleep(MAX31827_12_BIT_CNV_TIME);</div><div class='add'>+				msleep(max31827_conv_times[st-&gt;resolution]);</div><div class='ctx'> 			}</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * For 12-bit resolution the conversion time is 140 ms,</div><div class='add'>+			 * thus an additional 15 ms is needed to complete the</div><div class='add'>+			 * conversion: 125 ms + 15 ms = 140 ms</div><div class='add'>+			 */</div><div class='add'>+			if (max31827_resolutions[st-&gt;resolution] == 12 &amp;&amp;</div><div class='add'>+			    st-&gt;update_interval == 125)</div><div class='add'>+				usleep_range(15000, 20000);</div><div class='add'>+</div><div class='ctx'> 			ret = regmap_read(st-&gt;regmap, MAX31827_T_REG, &amp;uval);</div><div class='ctx'> </div><div class='ctx'> 			mutex_unlock(&amp;st-&gt;lock);</div><div class='hunk'>@@ -340,17 +396,20 @@ static int max31827_write(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 			       val &lt; max31827_conversions[res])</div><div class='ctx'> 				res++;</div><div class='ctx'> </div><div class='del'>-			if (res == ARRAY_SIZE(max31827_conversions) ||</div><div class='del'>-			    val != max31827_conversions[res])</div><div class='del'>-				return -EINVAL;</div><div class='add'>+			if (res == ARRAY_SIZE(max31827_conversions))</div><div class='add'>+				res = ARRAY_SIZE(max31827_conversions) - 1;</div><div class='ctx'> </div><div class='ctx'> 			res = FIELD_PREP(MAX31827_CONFIGURATION_CNV_RATE_MASK,</div><div class='ctx'> 					 res);</div><div class='ctx'> </div><div class='del'>-			return regmap_update_bits(st-&gt;regmap,</div><div class='del'>-						  MAX31827_CONFIGURATION_REG,</div><div class='del'>-						  MAX31827_CONFIGURATION_CNV_RATE_MASK,</div><div class='del'>-						  res);</div><div class='add'>+			ret = regmap_update_bits(st-&gt;regmap,</div><div class='add'>+						 MAX31827_CONFIGURATION_REG,</div><div class='add'>+						 MAX31827_CONFIGURATION_CNV_RATE_MASK,</div><div class='add'>+						 res);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			st-&gt;update_interval = val;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='hunk'>@@ -358,17 +417,165 @@ static int max31827_write(struct device *dev, enum hwmon_sensor_types type,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return -EOPNOTSUPP;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t temp1_resolution_show(struct device *dev,</div><div class='add'>+				     struct device_attribute *devattr,</div><div class='add'>+				     char *buf)</div><div class='add'>+{</div><div class='add'>+	struct max31827_state *st = dev_get_drvdata(dev);</div><div class='add'>+	unsigned int val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(st-&gt;regmap, MAX31827_CONFIGURATION_REG, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	val = FIELD_GET(MAX31827_CONFIGURATION_RESOLUTION_MASK, val);</div><div class='add'>+</div><div class='add'>+	return scnprintf(buf, PAGE_SIZE, "%u\n", max31827_resolutions[val]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int max31827_init_client(struct max31827_state *st)</div><div class='add'>+static ssize_t temp1_resolution_store(struct device *dev,</div><div class='add'>+				      struct device_attribute *devattr,</div><div class='add'>+				      const char *buf, size_t count)</div><div class='ctx'> {</div><div class='add'>+	struct max31827_state *st = dev_get_drvdata(dev);</div><div class='add'>+	unsigned int idx = 0;</div><div class='add'>+	unsigned int val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtouint(buf, 10, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Convert the desired resolution into register</div><div class='add'>+	 * bits. idx is already initialized with 0.</div><div class='add'>+	 *</div><div class='add'>+	 * This was inspired by lm73 driver.</div><div class='add'>+	 */</div><div class='add'>+	while (idx &lt; ARRAY_SIZE(max31827_resolutions) &amp;&amp;</div><div class='add'>+	       val &lt; max31827_resolutions[idx])</div><div class='add'>+		idx++;</div><div class='add'>+</div><div class='add'>+	if (idx == ARRAY_SIZE(max31827_resolutions))</div><div class='add'>+		idx = ARRAY_SIZE(max31827_resolutions) - 1;</div><div class='add'>+</div><div class='add'>+	st-&gt;resolution = idx;</div><div class='add'>+</div><div class='add'>+	ret = shutdown_write(st, MAX31827_CONFIGURATION_REG,</div><div class='add'>+			     MAX31827_CONFIGURATION_RESOLUTION_MASK,</div><div class='add'>+			     FIELD_PREP(MAX31827_CONFIGURATION_RESOLUTION_MASK,</div><div class='add'>+					idx));</div><div class='add'>+</div><div class='add'>+	return ret ? ret : count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR_RW(temp1_resolution);</div><div class='add'>+</div><div class='add'>+static struct attribute *max31827_attrs[] = {</div><div class='add'>+	&amp;dev_attr_temp1_resolution.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+ATTRIBUTE_GROUPS(max31827);</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id max31827_i2c_ids[] = {</div><div class='add'>+	{ "max31827", max31827 },</div><div class='add'>+	{ "max31828", max31828 },</div><div class='add'>+	{ "max31829", max31829 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, max31827_i2c_ids);</div><div class='add'>+</div><div class='add'>+static int max31827_init_client(struct max31827_state *st,</div><div class='add'>+				struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct fwnode_handle *fwnode;</div><div class='add'>+	unsigned int res = 0;</div><div class='add'>+	u32 data, lsb_idx;</div><div class='add'>+	enum chips type;</div><div class='add'>+	bool prop;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	fwnode = dev_fwnode(dev);</div><div class='add'>+</div><div class='ctx'> 	st-&gt;enable = true;</div><div class='add'>+	res |= MAX31827_DEVICE_ENABLE(1);</div><div class='ctx'> </div><div class='del'>-	return regmap_update_bits(st-&gt;regmap, MAX31827_CONFIGURATION_REG,</div><div class='del'>-				  MAX31827_CONFIGURATION_1SHOT_MASK |</div><div class='del'>-					  MAX31827_CONFIGURATION_CNV_RATE_MASK,</div><div class='del'>-				  MAX31827_DEVICE_ENABLE(1));</div><div class='add'>+	res |= MAX31827_CONFIGURATION_RESOLUTION_MASK;</div><div class='add'>+</div><div class='add'>+	prop = fwnode_property_read_bool(fwnode, "adi,comp-int");</div><div class='add'>+	res |= FIELD_PREP(MAX31827_CONFIGURATION_COMP_INT_MASK, prop);</div><div class='add'>+</div><div class='add'>+	prop = fwnode_property_read_bool(fwnode, "adi,timeout-enable");</div><div class='add'>+	res |= FIELD_PREP(MAX31827_CONFIGURATION_TIMEOUT_MASK, !prop);</div><div class='add'>+</div><div class='add'>+	type = (enum chips)(uintptr_t)device_get_match_data(dev);</div><div class='add'>+</div><div class='add'>+	if (fwnode_property_present(fwnode, "adi,alarm-pol")) {</div><div class='add'>+		ret = fwnode_property_read_u32(fwnode, "adi,alarm-pol", &amp;data);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK, !!data);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * Set default value.</div><div class='add'>+		 */</div><div class='add'>+		switch (type) {</div><div class='add'>+		case max31827:</div><div class='add'>+		case max31828:</div><div class='add'>+			res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,</div><div class='add'>+					  MAX31827_ALRM_POL_LOW);</div><div class='add'>+			break;</div><div class='add'>+		case max31829:</div><div class='add'>+			res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,</div><div class='add'>+					  MAX31827_ALRM_POL_HIGH);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fwnode_property_present(fwnode, "adi,fault-q")) {</div><div class='add'>+		ret = fwnode_property_read_u32(fwnode, "adi,fault-q", &amp;data);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Convert the desired fault queue into register bits.</div><div class='add'>+		 */</div><div class='add'>+		if (data != 0)</div><div class='add'>+			lsb_idx = __ffs(data);</div><div class='add'>+</div><div class='add'>+		if (hweight32(data) != 1 || lsb_idx &gt; 4) {</div><div class='add'>+			dev_err(dev, "Invalid data in adi,fault-q\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK, lsb_idx);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * Set default value.</div><div class='add'>+		 */</div><div class='add'>+		switch (type) {</div><div class='add'>+		case max31827:</div><div class='add'>+			res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,</div><div class='add'>+					  MAX31827_FLT_Q_1);</div><div class='add'>+			break;</div><div class='add'>+		case max31828:</div><div class='add'>+		case max31829:</div><div class='add'>+			res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,</div><div class='add'>+					  MAX31827_FLT_Q_4);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return regmap_write(st-&gt;regmap, MAX31827_CONFIGURATION_REG, res);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct hwmon_channel_info *max31827_info[] = {</div><div class='hunk'>@@ -416,25 +623,30 @@ static int max31827_probe(struct i2c_client *client)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return dev_err_probe(dev, err, "failed to enable regulator\n");</div><div class='ctx'> </div><div class='del'>-	err = max31827_init_client(st);</div><div class='add'>+	err = max31827_init_client(st, dev);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client-&gt;name, st,</div><div class='ctx'> 							 &amp;max31827_chip_info,</div><div class='del'>-							 NULL);</div><div class='add'>+							 max31827_groups);</div><div class='ctx'> </div><div class='ctx'> 	return PTR_ERR_OR_ZERO(hwmon_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct i2c_device_id max31827_i2c_ids[] = {</div><div class='del'>-	{ "max31827", 0 },</div><div class='del'>-	{ }</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(i2c, max31827_i2c_ids);</div><div class='del'>-</div><div class='ctx'> static const struct of_device_id max31827_of_match[] = {</div><div class='del'>-	{ .compatible = "adi,max31827" },</div><div class='add'>+	{</div><div class='add'>+		.compatible = "adi,max31827",</div><div class='add'>+		.data = (void *)max31827</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "adi,max31828",</div><div class='add'>+		.data = (void *)max31828</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "adi,max31829",</div><div class='add'>+		.data = (void *)max31829</div><div class='add'>+	},</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, max31827_of_match);</div><div class='head'>diff --git a/drivers/hwmon/max6650.c b/drivers/hwmon/max6650.c<br/>index cc8428a3045d..9649c6611d5f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/max6650.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/max6650.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/max6650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/max6650.c</a></div><div class='hunk'>@@ -26,7 +26,7 @@</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='ctx'> #include &lt;linux/hwmon-sysfs.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/thermal.h&gt;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -763,8 +763,6 @@ static int max6650_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct thermal_cooling_device *cooling_dev;</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='del'>-	const struct of_device_id *of_id =</div><div class='del'>-		of_match_device(of_match_ptr(max6650_dt_match), dev);</div><div class='ctx'> 	struct max6650_data *data;</div><div class='ctx'> 	struct device *hwmon_dev;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -776,8 +774,8 @@ static int max6650_probe(struct i2c_client *client)</div><div class='ctx'> 	data-&gt;client = client;</div><div class='ctx'> 	i2c_set_clientdata(client, data);</div><div class='ctx'> 	mutex_init(&amp;data-&gt;update_lock);</div><div class='del'>-	data-&gt;nr_fans = of_id ? (int)(uintptr_t)of_id-&gt;data :</div><div class='del'>-				i2c_match_id(max6650_id, client)-&gt;driver_data;</div><div class='add'>+</div><div class='add'>+	data-&gt;nr_fans = (uintptr_t)i2c_get_match_data(client);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Initialize the max6650 chip</div><div class='head'>diff --git a/drivers/hwmon/nct6775-core.c b/drivers/hwmon/nct6775-core.c<br/>index d928eb8ae5a3..8d2ef3145bca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/nct6775-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-core.c</a></div><div class='hunk'>@@ -63,19 +63,19 @@</div><div class='ctx'> </div><div class='ctx'> /* used to set data-&gt;name = nct6775_device_names[data-&gt;sio_kind] */</div><div class='ctx'> static const char * const nct6775_device_names[] = {</div><div class='del'>-	"nct6106",</div><div class='del'>-	"nct6116",</div><div class='del'>-	"nct6775",</div><div class='del'>-	"nct6776",</div><div class='del'>-	"nct6779",</div><div class='del'>-	"nct6791",</div><div class='del'>-	"nct6792",</div><div class='del'>-	"nct6793",</div><div class='del'>-	"nct6795",</div><div class='del'>-	"nct6796",</div><div class='del'>-	"nct6797",</div><div class='del'>-	"nct6798",</div><div class='del'>-	"nct6799",</div><div class='add'>+	[nct6106] = "nct6106",</div><div class='add'>+	[nct6116] = "nct6116",</div><div class='add'>+	[nct6775] = "nct6775",</div><div class='add'>+	[nct6776] = "nct6776",</div><div class='add'>+	[nct6779] = "nct6779",</div><div class='add'>+	[nct6791] = "nct6791",</div><div class='add'>+	[nct6792] = "nct6792",</div><div class='add'>+	[nct6793] = "nct6793",</div><div class='add'>+	[nct6795] = "nct6795",</div><div class='add'>+	[nct6796] = "nct6796",</div><div class='add'>+	[nct6797] = "nct6797",</div><div class='add'>+	[nct6798] = "nct6798",</div><div class='add'>+	[nct6799] = "nct6799",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Common and NCT6775 specific data */</div><div class='hunk'>@@ -767,9 +767,9 @@ static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };</div><div class='ctx'> static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };</div><div class='ctx'> static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };</div><div class='ctx'> </div><div class='del'>-static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };</div><div class='del'>-static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };</div><div class='del'>-static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };</div><div class='add'>+static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3, 0, 0 };</div><div class='add'>+static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04, 0, 0 };</div><div class='add'>+static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c, 0xd8, 0xd9 };</div><div class='ctx'> static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };</div><div class='ctx'> static const u16 NCT6106_REG_TEMP_SOURCE[] = {</div><div class='ctx'> 	0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };</div><div class='hunk'>@@ -2553,6 +2553,13 @@ store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u16 reg;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * The fan control mode should be set to manual if the user wants to adjust</div><div class='add'>+	 * the fan speed. Otherwise, it will fail to set.</div><div class='add'>+	 */</div><div class='add'>+	if (index == 0 &amp;&amp; data-&gt;pwm_enable[nr] &gt; manual)</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='ctx'> 	err = kstrtoul(buf, 10, &amp;val);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -3595,7 +3602,7 @@ int nct6775_probe(struct device *dev, struct nct6775_data *data,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case nct6116:</div><div class='ctx'> 		data-&gt;in_num = 9;</div><div class='del'>-		data-&gt;pwm_num = 3;</div><div class='add'>+		data-&gt;pwm_num = 5;</div><div class='ctx'> 		data-&gt;auto_pwm_num = 4;</div><div class='ctx'> 		data-&gt;temp_fixed_num = 3;</div><div class='ctx'> 		data-&gt;num_temp_alarms = 3;</div><div class='head'>diff --git a/drivers/hwmon/nct6775-i2c.c b/drivers/hwmon/nct6775-i2c.c<br/>index 87a4fc78c571..aff69fa50461 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/nct6775-i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-i2c.c</a></div><div class='hunk'>@@ -21,7 +21,7 @@</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='ctx'> #include &lt;linux/hwmon-sysfs.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include "nct6775.h"</div><div class='ctx'> </div><div class='hunk'>@@ -155,23 +155,13 @@ static const struct regmap_config nct6775_i2c_regmap_config = {</div><div class='ctx'> static int nct6775_i2c_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct nct6775_data *data;</div><div class='del'>-	const struct of_device_id *of_id;</div><div class='del'>-	const struct i2c_device_id *i2c_id;</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	of_id = of_match_device(nct6775_i2c_of_match, dev);</div><div class='del'>-	i2c_id = i2c_match_id(nct6775_i2c_id, client);</div><div class='del'>-</div><div class='del'>-	if (of_id &amp;&amp; (unsigned long)of_id-&gt;data != i2c_id-&gt;driver_data)</div><div class='del'>-		dev_notice(dev, "Device mismatch: %s in device tree, %s detected\n",</div><div class='del'>-			   of_id-&gt;name, i2c_id-&gt;name);</div><div class='del'>-</div><div class='ctx'> 	data = devm_kzalloc(&amp;client-&gt;dev, sizeof(*data), GFP_KERNEL);</div><div class='ctx'> 	if (!data)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	data-&gt;kind = i2c_id-&gt;driver_data;</div><div class='del'>-</div><div class='add'>+	data-&gt;kind = (enum kinds)(uintptr_t)i2c_get_match_data(client);</div><div class='ctx'> 	data-&gt;read_only = true;</div><div class='ctx'> 	data-&gt;driver_data = client;</div><div class='ctx'> 	data-&gt;driver_init = nct6775_i2c_probe_init;</div><div class='head'>diff --git a/drivers/hwmon/nct6775-platform.c b/drivers/hwmon/nct6775-platform.c<br/>index 0adeeab7ee03..9aa4dcf4a6f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-platform.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/nct6775-platform.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775-platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775-platform.c</a></div><div class='hunk'>@@ -23,19 +23,19 @@</div><div class='ctx'> enum sensor_access { access_direct, access_asuswmi };</div><div class='ctx'> </div><div class='ctx'> static const char * const nct6775_sio_names[] __initconst = {</div><div class='del'>-	"NCT6106D",</div><div class='del'>-	"NCT6116D",</div><div class='del'>-	"NCT6775F",</div><div class='del'>-	"NCT6776D/F",</div><div class='del'>-	"NCT6779D",</div><div class='del'>-	"NCT6791D",</div><div class='del'>-	"NCT6792D",</div><div class='del'>-	"NCT6793D",</div><div class='del'>-	"NCT6795D",</div><div class='del'>-	"NCT6796D",</div><div class='del'>-	"NCT6797D",</div><div class='del'>-	"NCT6798D",</div><div class='del'>-	"NCT6796D-S/NCT6799D-R",</div><div class='add'>+	[nct6106] = "NCT6106D",</div><div class='add'>+	[nct6116] = "NCT6116D",</div><div class='add'>+	[nct6775] = "NCT6775F",</div><div class='add'>+	[nct6776] = "NCT6776D/F",</div><div class='add'>+	[nct6779] = "NCT6779D",</div><div class='add'>+	[nct6791] = "NCT6791D",</div><div class='add'>+	[nct6792] = "NCT6792D",</div><div class='add'>+	[nct6793] = "NCT6793D",</div><div class='add'>+	[nct6795] = "NCT6795D",</div><div class='add'>+	[nct6796] = "NCT6796D",</div><div class='add'>+	[nct6797] = "NCT6797D",</div><div class='add'>+	[nct6798] = "NCT6798D",</div><div class='add'>+	[nct6799] = "NCT6796D-S/NCT6799D-R",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static unsigned short force_id;</div><div class='head'>diff --git a/drivers/hwmon/nct6775.h b/drivers/hwmon/nct6775.h<br/>index 296eff99d003..d31e7a030216 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/nct6775.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/nct6775.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nct6775.h</a></div><div class='hunk'>@@ -4,7 +4,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='del'>-enum kinds { nct6106, nct6116, nct6775, nct6776, nct6779, nct6791, nct6792,</div><div class='add'>+enum kinds { nct6106 = 1, nct6116, nct6775, nct6776, nct6779, nct6791, nct6792,</div><div class='ctx'> 	     nct6793, nct6795, nct6796, nct6797, nct6798, nct6799 };</div><div class='ctx'> enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwmon/npcm750-pwm-fan.c b/drivers/hwmon/npcm750-pwm-fan.c<br/>index 4702e4edc662..904816abb7c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/npcm750-pwm-fan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/npcm750-pwm-fan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/npcm750-pwm-fan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/npcm750-pwm-fan.c</a></div><div class='hunk'>@@ -46,9 +46,9 @@</div><div class='ctx'> #define NPCM7XX_PWM_CTRL_CH3_EN_BIT		BIT(16)</div><div class='ctx'> </div><div class='ctx'> /* Define the maximum PWM channel number */</div><div class='del'>-#define NPCM7XX_PWM_MAX_CHN_NUM			8</div><div class='add'>+#define NPCM7XX_PWM_MAX_CHN_NUM			12</div><div class='ctx'> #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE	4</div><div class='del'>-#define NPCM7XX_PWM_MAX_MODULES                 2</div><div class='add'>+#define NPCM7XX_PWM_MAX_MODULES                 3</div><div class='ctx'> </div><div class='ctx'> /* Define the Counter Register, value = 100 for match 100% */</div><div class='ctx'> #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM		255</div><div class='hunk'>@@ -171,6 +171,10 @@</div><div class='ctx'> #define FAN_PREPARE_TO_GET_FIRST_CAPTURE	0x01</div><div class='ctx'> #define FAN_ENOUGH_SAMPLE			0x02</div><div class='ctx'> </div><div class='add'>+struct npcm_hwmon_info {</div><div class='add'>+	u32 pwm_max_channel;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct npcm7xx_fan_dev {</div><div class='ctx'> 	u8 fan_st_flg;</div><div class='ctx'> 	u8 fan_pls_per_rev;</div><div class='hunk'>@@ -191,6 +195,7 @@ struct npcm7xx_cooling_device {</div><div class='ctx'> struct npcm7xx_pwm_fan_data {</div><div class='ctx'> 	void __iomem *pwm_base;</div><div class='ctx'> 	void __iomem *fan_base;</div><div class='add'>+	int pwm_modules;</div><div class='ctx'> 	unsigned long pwm_clk_freq;</div><div class='ctx'> 	unsigned long fan_clk_freq;</div><div class='ctx'> 	struct clk *pwm_clk;</div><div class='hunk'>@@ -204,6 +209,7 @@ struct npcm7xx_pwm_fan_data {</div><div class='ctx'> 	struct timer_list fan_timer;</div><div class='ctx'> 	struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];</div><div class='ctx'> 	struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];</div><div class='add'>+	const struct npcm_hwmon_info *info;</div><div class='ctx'> 	u8 fan_select;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -542,7 +548,7 @@ static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)</div><div class='ctx'> {</div><div class='ctx'> 	const struct npcm7xx_pwm_fan_data *data = _data;</div><div class='ctx'> </div><div class='del'>-	if (!data-&gt;pwm_present[channel])</div><div class='add'>+	if (!data-&gt;pwm_present[channel] || channel &gt;= data-&gt;info-&gt;pwm_max_channel)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (attr) {</div><div class='hunk'>@@ -638,6 +644,10 @@ static const struct hwmon_channel_info * const npcm7xx_info[] = {</div><div class='ctx'> 			   HWMON_PWM_INPUT,</div><div class='ctx'> 			   HWMON_PWM_INPUT,</div><div class='ctx'> 			   HWMON_PWM_INPUT,</div><div class='add'>+			   HWMON_PWM_INPUT,</div><div class='add'>+			   HWMON_PWM_INPUT,</div><div class='add'>+			   HWMON_PWM_INPUT,</div><div class='add'>+			   HWMON_PWM_INPUT,</div><div class='ctx'> 			   HWMON_PWM_INPUT),</div><div class='ctx'> 	HWMON_CHANNEL_INFO(fan,</div><div class='ctx'> 			   HWMON_F_INPUT,</div><div class='hunk'>@@ -670,6 +680,14 @@ static const struct hwmon_chip_info npcm7xx_chip_info = {</div><div class='ctx'> 	.info = npcm7xx_info,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct npcm_hwmon_info npxm7xx_hwmon_info = {</div><div class='add'>+	.pwm_max_channel = 8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct npcm_hwmon_info npxm8xx_hwmon_info = {</div><div class='add'>+	.pwm_max_channel = 12,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	int m, ch;</div><div class='hunk'>@@ -693,7 +711,7 @@ static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)</div><div class='ctx'> 	/* Setting PWM Prescale Register value register to both modules */</div><div class='ctx'> 	prescale_val |= (prescale_val &lt;&lt; NPCM7XX_PWM_PRESCALE_SHIFT_CH01);</div><div class='ctx'> </div><div class='del'>-	for (m = 0; m &lt; NPCM7XX_PWM_MAX_MODULES  ; m++) {</div><div class='add'>+	for (m = 0; m &lt; data-&gt;pwm_modules; m++) {</div><div class='ctx'> 		iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data-&gt;pwm_base, m));</div><div class='ctx'> 		iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,</div><div class='ctx'> 			  NPCM7XX_PWM_REG_CSR(data-&gt;pwm_base, m));</div><div class='hunk'>@@ -925,6 +943,12 @@ static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (!data)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	data-&gt;info = device_get_match_data(dev);</div><div class='add'>+	if (!data-&gt;info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	data-&gt;pwm_modules = data-&gt;info-&gt;pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE;</div><div class='add'>+</div><div class='ctx'> 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");</div><div class='ctx'> 	if (!res) {</div><div class='ctx'> 		dev_err(dev, "pwm resource not found\n");</div><div class='hunk'>@@ -962,7 +986,7 @@ static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)</div><div class='ctx'> 	output_freq = npcm7xx_pwm_init(data);</div><div class='ctx'> 	npcm7xx_fan_init(data);</div><div class='ctx'> </div><div class='del'>-	for (cnt = 0; cnt &lt; NPCM7XX_PWM_MAX_MODULES  ; cnt++)</div><div class='add'>+	for (cnt = 0; cnt &lt; data-&gt;pwm_modules; cnt++)</div><div class='ctx'> 		mutex_init(&amp;data-&gt;pwm_lock[cnt]);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NPCM7XX_FAN_MAX_MODULE; i++) {</div><div class='hunk'>@@ -1017,7 +1041,8 @@ static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id of_pwm_fan_match_table[] = {</div><div class='del'>-	{ .compatible = "nuvoton,npcm750-pwm-fan", },</div><div class='add'>+	{ .compatible = "nuvoton,npcm750-pwm-fan", .data = &amp;npxm7xx_hwmon_info},</div><div class='add'>+	{ .compatible = "nuvoton,npcm845-pwm-fan", .data = &amp;npxm8xx_hwmon_info},</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);</div><div class='head'>diff --git a/drivers/hwmon/nzxt-kraken2.c b/drivers/hwmon/nzxt-kraken2.c<br/>index 428c77b5fce5..7caf387eb144 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/nzxt-kraken2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/nzxt-kraken2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/nzxt-kraken2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/nzxt-kraken2.c</a></div><div class='hunk'>@@ -161,13 +161,13 @@ static int kraken2_probe(struct hid_device *hdev,</div><div class='ctx'> 	ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		hid_err(hdev, "hid hw start failed with %d\n", ret);</div><div class='del'>-		goto fail_and_stop;</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = hid_hw_open(hdev);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		hid_err(hdev, "hid hw open failed with %d\n", ret);</div><div class='del'>-		goto fail_and_close;</div><div class='add'>+		goto fail_and_stop;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	priv-&gt;hwmon_dev = hwmon_device_register_with_info(&amp;hdev-&gt;dev, "kraken2",</div><div class='head'>diff --git a/drivers/hwmon/pc87360.c b/drivers/hwmon/pc87360.c<br/>index 926ea1fe133c..9e9681b2e8c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/pc87360.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/pc87360.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pc87360.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pc87360.c</a></div><div class='hunk'>@@ -323,7 +323,11 @@ static struct pc87360_data *pc87360_update_device(struct device *dev)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Voltages */</div><div class='del'>-		for (i = 0; i &lt; data-&gt;innr; i++) {</div><div class='add'>+		/*</div><div class='add'>+		 * The min() below does not have any practical meaning and is</div><div class='add'>+		 * only needed to silence a warning observed with gcc 12+.</div><div class='add'>+		 */</div><div class='add'>+		for (i = 0; i &lt; min(data-&gt;innr, ARRAY_SIZE(data-&gt;in)); i++) {</div><div class='ctx'> 			data-&gt;in_status[i] = pc87360_read_value(data, LD_IN, i,</div><div class='ctx'> 					     PC87365_REG_IN_STATUS);</div><div class='ctx'> 			/* Clear bits */</div><div class='head'>diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c<br/>index 5ca4d04e4b14..4a72e9712408 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/peci/dimmtemp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/peci/dimmtemp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/peci/dimmtemp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/peci/dimmtemp.c</a></div><div class='hunk'>@@ -47,7 +47,7 @@</div><div class='ctx'> #define GET_TEMP_MAX(x)		(((x) &amp; DIMM_TEMP_MAX) &gt;&gt; 8)</div><div class='ctx'> #define GET_TEMP_CRIT(x)	(((x) &amp; DIMM_TEMP_CRIT) &gt;&gt; 16)</div><div class='ctx'> </div><div class='del'>-#define NO_DIMM_RETRY_COUNT_MAX	5</div><div class='add'>+#define NO_DIMM_RETRY_COUNT_MAX	120</div><div class='ctx'> </div><div class='ctx'> struct peci_dimmtemp;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig<br/>index b4e93bd5835e..294808f5240a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/pmbus/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/Kconfig</a></div><div class='hunk'>@@ -227,6 +227,16 @@ config SENSORS_LTC3815</div><div class='ctx'> 	  This driver can also be built as a module. If so, the module will</div><div class='ctx'> 	  be called ltc3815.</div><div class='ctx'> </div><div class='add'>+config SENSORS_LTC4286</div><div class='add'>+	bool "Analog Devices LTC4286"</div><div class='add'>+	help</div><div class='add'>+	  LTC4286 is an integrated solution for hot swap applications that</div><div class='add'>+	  allows a board to be safely inserted and removed from a live</div><div class='add'>+	  backplane.</div><div class='add'>+	  This chip could be used to monitor voltage, current, ...etc.</div><div class='add'>+	  If you say yes here you get hardware monitoring support for Analog</div><div class='add'>+	  Devices LTC4286.</div><div class='add'>+</div><div class='ctx'> config SENSORS_MAX15301</div><div class='ctx'> 	tristate "Maxim MAX15301"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -299,6 +309,15 @@ config SENSORS_MAX8688</div><div class='ctx'> 	  This driver can also be built as a module. If so, the module will</div><div class='ctx'> 	  be called max8688.</div><div class='ctx'> </div><div class='add'>+config SENSORS_MP2856</div><div class='add'>+	tristate "MPS MP2856"</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get hardware monitoring support for MPS</div><div class='add'>+	  MP2856 MP2857 Dual Loop Digital Multi-Phase Controller.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module will</div><div class='add'>+	  be called mp2856.</div><div class='add'>+</div><div class='ctx'> config SENSORS_MP2888</div><div class='ctx'> 	tristate "MPS MP2888"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -333,6 +352,15 @@ config SENSORS_MP5023</div><div class='ctx'> 	  This driver can also be built as a module. If so, the module will</div><div class='ctx'> 	  be called mp5023.</div><div class='ctx'> </div><div class='add'>+config SENSORS_MP5990</div><div class='add'>+	tristate "MPS MP5990"</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get hardware monitoring support for MPS</div><div class='add'>+	  MP5990.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module will</div><div class='add'>+	  be called mp5990.</div><div class='add'>+</div><div class='ctx'> config SENSORS_MPQ7932_REGULATOR</div><div class='ctx'> 	bool "Regulator support for MPQ7932"</div><div class='ctx'> 	depends on SENSORS_MPQ7932 &amp;&amp; REGULATOR</div><div class='head'>diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile<br/>index 84ee960a6c2d..cf8a76744545 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/pmbus/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/Makefile</a></div><div class='hunk'>@@ -24,6 +24,7 @@ obj-$(CONFIG_SENSORS_LM25066)	+= lm25066.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_LT7182S)	+= lt7182s.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_LTC2978)	+= ltc2978.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_LTC3815)	+= ltc3815.o</div><div class='add'>+obj-$(CONFIG_SENSORS_LTC4286)	+= ltc4286.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX15301)	+= max15301.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX16064)	+= max16064.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX16601)	+= max16601.o</div><div class='hunk'>@@ -32,9 +33,11 @@ obj-$(CONFIG_SENSORS_MAX20751)	+= max20751.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX31785)	+= max31785.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX34440)	+= max34440.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MAX8688)	+= max8688.o</div><div class='add'>+obj-$(CONFIG_SENSORS_MP2856)	+= mp2856.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MP2888)	+= mp2888.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MP2975)	+= mp2975.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MP5023)	+= mp5023.o</div><div class='add'>+obj-$(CONFIG_SENSORS_MP5990)	+= mp5990.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_MPQ7932)	+= mpq7932.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_PLI1209BC)	+= pli1209bc.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_PM6764TR)	+= pm6764tr.o</div><div class='head'>diff --git a/drivers/hwmon/pmbus/lm25066.c b/drivers/hwmon/pmbus/lm25066.c<br/>index 929fa6d34efd..3a20df5a43ec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/lm25066.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/pmbus/lm25066.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/lm25066.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/lm25066.c</a></div><div class='hunk'>@@ -14,10 +14,10 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/log2.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include "pmbus.h"</div><div class='ctx'> </div><div class='del'>-enum chips { lm25056, lm25066, lm5064, lm5066, lm5066i };</div><div class='add'>+enum chips { lm25056 = 1, lm25066, lm5064, lm5066, lm5066i };</div><div class='ctx'> </div><div class='ctx'> #define LM25066_READ_VAUX		0xd0</div><div class='ctx'> #define LM25066_MFR_READ_IIN		0xd1</div><div class='hunk'>@@ -468,8 +468,6 @@ static int lm25066_probe(struct i2c_client *client)</div><div class='ctx'> 	struct lm25066_data *data;</div><div class='ctx'> 	struct pmbus_driver_info *info;</div><div class='ctx'> 	const struct __coeff *coeff;</div><div class='del'>-	const struct of_device_id *of_id;</div><div class='del'>-	const struct i2c_device_id *i2c_id;</div><div class='ctx'> </div><div class='ctx'> 	if (!i2c_check_functionality(client-&gt;adapter,</div><div class='ctx'> 				     I2C_FUNC_SMBUS_READ_BYTE_DATA))</div><div class='hunk'>@@ -484,14 +482,8 @@ static int lm25066_probe(struct i2c_client *client)</div><div class='ctx'> 	if (config &lt; 0)</div><div class='ctx'> 		return config;</div><div class='ctx'> </div><div class='del'>-	i2c_id = i2c_match_id(lm25066_id, client);</div><div class='add'>+	data-&gt;id = (enum chips)(unsigned long)i2c_get_match_data(client);</div><div class='ctx'> </div><div class='del'>-	of_id = of_match_device(lm25066_of_match, &amp;client-&gt;dev);</div><div class='del'>-	if (of_id &amp;&amp; (unsigned long)of_id-&gt;data != i2c_id-&gt;driver_data)</div><div class='del'>-		dev_notice(&amp;client-&gt;dev, "Device mismatch: %s in device tree, %s detected\n",</div><div class='del'>-			   of_id-&gt;name, i2c_id-&gt;name);</div><div class='del'>-</div><div class='del'>-	data-&gt;id = i2c_id-&gt;driver_data;</div><div class='ctx'> 	info = &amp;data-&gt;info;</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;pages = 1;</div><div class='head'>diff --git a/drivers/hwmon/pmbus/ltc4286.c b/drivers/hwmon/pmbus/ltc4286.c<br/>new file mode 100644<br/>index 000000000000..9e7ceeb7e789<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/ltc4286.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/ltc4286.c</a></div><div class='hunk'>@@ -0,0 +1,175 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pmbus.h&gt;</div><div class='add'>+#include "pmbus.h"</div><div class='add'>+</div><div class='add'>+/* LTC4286 register */</div><div class='add'>+#define LTC4286_MFR_CONFIG1	0xF2</div><div class='add'>+</div><div class='add'>+/* LTC4286 configuration */</div><div class='add'>+#define VRANGE_SELECT_BIT	BIT(1)</div><div class='add'>+</div><div class='add'>+#define LTC4286_MFR_ID_SIZE	3</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Initialize the MBR as default settings which is referred to LTC4286 datasheet</div><div class='add'>+ * (March 22, 2022 version) table 3 page 16</div><div class='add'>+ */</div><div class='add'>+static struct pmbus_driver_info ltc4286_info = {</div><div class='add'>+	.pages = 1,</div><div class='add'>+	.format[PSC_VOLTAGE_IN] = direct,</div><div class='add'>+	.format[PSC_VOLTAGE_OUT] = direct,</div><div class='add'>+	.format[PSC_CURRENT_OUT] = direct,</div><div class='add'>+	.format[PSC_POWER] = direct,</div><div class='add'>+	.format[PSC_TEMPERATURE] = direct,</div><div class='add'>+	.m[PSC_VOLTAGE_IN] = 32,</div><div class='add'>+	.b[PSC_VOLTAGE_IN] = 0,</div><div class='add'>+	.R[PSC_VOLTAGE_IN] = 1,</div><div class='add'>+	.m[PSC_VOLTAGE_OUT] = 32,</div><div class='add'>+	.b[PSC_VOLTAGE_OUT] = 0,</div><div class='add'>+	.R[PSC_VOLTAGE_OUT] = 1,</div><div class='add'>+	.m[PSC_CURRENT_OUT] = 1024,</div><div class='add'>+	.b[PSC_CURRENT_OUT] = 0,</div><div class='add'>+	/*</div><div class='add'>+	 * The rsense value used in MBR formula in LTC4286 datasheet should be ohm unit.</div><div class='add'>+	 * However, the rsense value that user input is micro ohm.</div><div class='add'>+	 * Thus, the MBR setting which involves rsense should be shifted by 6 digits.</div><div class='add'>+	 */</div><div class='add'>+	.R[PSC_CURRENT_OUT] = 3 - 6,</div><div class='add'>+	.m[PSC_POWER] = 1,</div><div class='add'>+	.b[PSC_POWER] = 0,</div><div class='add'>+	/*</div><div class='add'>+	 * The rsense value used in MBR formula in LTC4286 datasheet should be ohm unit.</div><div class='add'>+	 * However, the rsense value that user input is micro ohm.</div><div class='add'>+	 * Thus, the MBR setting which involves rsense should be shifted by 6 digits.</div><div class='add'>+	 */</div><div class='add'>+	.R[PSC_POWER] = 4 - 6,</div><div class='add'>+	.m[PSC_TEMPERATURE] = 1,</div><div class='add'>+	.b[PSC_TEMPERATURE] = 273,</div><div class='add'>+	.R[PSC_TEMPERATURE] = 0,</div><div class='add'>+	.func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT |</div><div class='add'>+		   PMBUS_HAVE_PIN | PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_VOUT |</div><div class='add'>+		   PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_STATUS_TEMP,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id ltc4286_id[] = {</div><div class='add'>+	{ "ltc4286", 0 },</div><div class='add'>+	{ "ltc4287", 1 },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, ltc4286_id);</div><div class='add'>+</div><div class='add'>+static int ltc4286_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	const struct i2c_device_id *mid;</div><div class='add'>+	u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1];</div><div class='add'>+	struct pmbus_driver_info *info;</div><div class='add'>+	u32 rsense;</div><div class='add'>+	int vrange_nval, vrange_oval;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_block_data(client, PMBUS_MFR_ID, block_buffer);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "Failed to read manufacturer id\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Refer to ltc4286 datasheet page 20</div><div class='add'>+	 * the manufacturer id is LTC</div><div class='add'>+	 */</div><div class='add'>+	if (ret != LTC4286_MFR_ID_SIZE ||</div><div class='add'>+	    strncmp(block_buffer, "LTC", LTC4286_MFR_ID_SIZE)) {</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, -ENODEV,</div><div class='add'>+				     "Manufacturer id mismatch\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_block_data(client, PMBUS_MFR_MODEL, block_buffer);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "Failed to read manufacturer model\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (mid = ltc4286_id; mid-&gt;name[0]; mid++) {</div><div class='add'>+		if (!strncasecmp(mid-&gt;name, block_buffer, strlen(mid-&gt;name)))</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	if (!mid-&gt;name[0])</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, -ENODEV,</div><div class='add'>+				     "Unsupported device\n");</div><div class='add'>+</div><div class='add'>+	if (of_property_read_u32(client-&gt;dev.of_node,</div><div class='add'>+				 "shunt-resistor-micro-ohms", &amp;rsense))</div><div class='add'>+		rsense = 300; /* 0.3 mOhm if not set via DT */</div><div class='add'>+</div><div class='add'>+	if (rsense == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Check for the latter MBR value won't overflow */</div><div class='add'>+	if (rsense &gt; (INT_MAX / 1024))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	info = devm_kmemdup(&amp;client-&gt;dev, &amp;ltc4286_info, sizeof(*info),</div><div class='add'>+			    GFP_KERNEL);</div><div class='add'>+	if (!info)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Check MFR1 CONFIG register bit 1 VRANGE_SELECT before driver loading */</div><div class='add'>+	vrange_oval = i2c_smbus_read_word_data(client, LTC4286_MFR_CONFIG1);</div><div class='add'>+	if (vrange_oval &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, vrange_oval,</div><div class='add'>+				     "Failed to read manufacturer configuration one\n");</div><div class='add'>+	vrange_nval = vrange_oval;</div><div class='add'>+</div><div class='add'>+	if (device_property_read_bool(&amp;client-&gt;dev, "adi,vrange-low-enable")) {</div><div class='add'>+		vrange_nval &amp;=</div><div class='add'>+			~VRANGE_SELECT_BIT; /* VRANGE_SELECT = 0, 25.6 volts */</div><div class='add'>+</div><div class='add'>+		info-&gt;m[PSC_VOLTAGE_IN] = 128;</div><div class='add'>+		info-&gt;m[PSC_VOLTAGE_OUT] = 128;</div><div class='add'>+		info-&gt;m[PSC_POWER] = 4 * rsense;</div><div class='add'>+	} else {</div><div class='add'>+		vrange_nval |=</div><div class='add'>+			VRANGE_SELECT_BIT; /* VRANGE_SELECT = 1, 102.4 volts */</div><div class='add'>+</div><div class='add'>+		info-&gt;m[PSC_POWER] = rsense;</div><div class='add'>+	}</div><div class='add'>+	if (vrange_nval != vrange_oval) {</div><div class='add'>+		/* Set MFR1 CONFIG register bit 1 VRANGE_SELECT */</div><div class='add'>+		ret = i2c_smbus_write_word_data(client, LTC4286_MFR_CONFIG1,</div><div class='add'>+						vrange_nval);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+					     "Failed to set vrange\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	info-&gt;m[PSC_CURRENT_OUT] = 1024 * rsense;</div><div class='add'>+</div><div class='add'>+	return pmbus_do_probe(client, info);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ltc4286_of_match[] = {</div><div class='add'>+	{ .compatible = "lltc,ltc4286" },</div><div class='add'>+	{ .compatible = "lltc,ltc4287" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct i2c_driver ltc4286_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "ltc4286",</div><div class='add'>+		.of_match_table = ltc4286_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = ltc4286_probe,</div><div class='add'>+	.id_table = ltc4286_id,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(ltc4286_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Delphine CC Chiu &lt;Delphine_CC_Chiu@wiwynn.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("PMBUS driver for LTC4286 and compatibles");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/hwmon/pmbus/mp2856.c b/drivers/hwmon/pmbus/mp2856.c<br/>new file mode 100644<br/>index 000000000000..6969350f5d7d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/mp2856.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/mp2856.c</a></div><div class='hunk'>@@ -0,0 +1,466 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Hardware monitoring driver for MPS2856/2857</div><div class='add'>+ * Monolithic Power Systems VR Controllers</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Quanta Computer lnc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pmbus.h&gt;</div><div class='add'>+#include "pmbus.h"</div><div class='add'>+</div><div class='add'>+/* Vendor specific registers. */</div><div class='add'>+#define MP2856_MFR_VR_MULTI_CONFIG_R1	0x0d</div><div class='add'>+#define MP2856_MFR_VR_MULTI_CONFIG_R2	0x1d</div><div class='add'>+</div><div class='add'>+#define MP2856_MUL1_BOOT_SR_R2		0x10</div><div class='add'>+#define MP2856_VR_ACTIVE		BIT(15)</div><div class='add'>+</div><div class='add'>+#define MP2856_MFR_VR_CONFIG2		0x5e</div><div class='add'>+#define MP2856_VOUT_MODE		BIT(11)</div><div class='add'>+</div><div class='add'>+#define MP2856_MFR_VR_CONFIG1		0x68</div><div class='add'>+#define MP2856_DRMOS_KCS		GENMASK(13, 12)</div><div class='add'>+</div><div class='add'>+#define MP2856_MFR_READ_CS1_2_R1	0x82</div><div class='add'>+#define MP2856_MFR_READ_CS3_4_R1	0x83</div><div class='add'>+#define MP2856_MFR_READ_CS5_6_R1	0x84</div><div class='add'>+#define MP2856_MFR_READ_CS7_8_R1	0x85</div><div class='add'>+#define MP2856_MFR_READ_CS9_10_R1	0x86</div><div class='add'>+#define MP2856_MFR_READ_CS11_12_R1	0x87</div><div class='add'>+</div><div class='add'>+#define MP2856_MFR_READ_CS1_2_R2	0x85</div><div class='add'>+#define MP2856_MFR_READ_CS3_4_R2	0x86</div><div class='add'>+#define MP2856_MFR_READ_CS5_6_R2	0x87</div><div class='add'>+</div><div class='add'>+#define MP2856_MAX_PHASE_RAIL1		8</div><div class='add'>+#define MP2856_MAX_PHASE_RAIL2		4</div><div class='add'>+</div><div class='add'>+#define MP2857_MAX_PHASE_RAIL1		12</div><div class='add'>+#define MP2857_MAX_PHASE_RAIL2		4</div><div class='add'>+</div><div class='add'>+#define MP2856_PAGE_NUM			2</div><div class='add'>+</div><div class='add'>+enum chips { mp2856 = 1, mp2857 };</div><div class='add'>+</div><div class='add'>+static const int mp2856_max_phases[][MP2856_PAGE_NUM] = {</div><div class='add'>+	[mp2856] = { MP2856_MAX_PHASE_RAIL1, MP2856_MAX_PHASE_RAIL2 },</div><div class='add'>+	[mp2857] = { MP2857_MAX_PHASE_RAIL1, MP2857_MAX_PHASE_RAIL2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id mp2856_id[] = {</div><div class='add'>+	{"mp2856", mp2856},</div><div class='add'>+	{"mp2857", mp2857},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, mp2856_id);</div><div class='add'>+</div><div class='add'>+struct mp2856_data {</div><div class='add'>+	struct pmbus_driver_info info;</div><div class='add'>+	int vout_format[MP2856_PAGE_NUM];</div><div class='add'>+	int curr_sense_gain[MP2856_PAGE_NUM];</div><div class='add'>+	int max_phases[MP2856_PAGE_NUM];</div><div class='add'>+	enum chips chip_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_mp2856_data(x)	container_of(x, struct mp2856_data, info)</div><div class='add'>+</div><div class='add'>+#define MAX_LIN_MANTISSA	(1023 * 1000)</div><div class='add'>+#define MIN_LIN_MANTISSA	(511 * 1000)</div><div class='add'>+</div><div class='add'>+static u16 val2linear11(s64 val)</div><div class='add'>+{</div><div class='add'>+	s16 exponent = 0, mantissa;</div><div class='add'>+	bool negative = false;</div><div class='add'>+</div><div class='add'>+	if (val == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (val &lt; 0) {</div><div class='add'>+		negative = true;</div><div class='add'>+		val = -val;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Reduce large mantissa until it fits into 10 bit */</div><div class='add'>+	while (val &gt;= MAX_LIN_MANTISSA &amp;&amp; exponent &lt; 15) {</div><div class='add'>+		exponent++;</div><div class='add'>+		val &gt;&gt;= 1;</div><div class='add'>+	}</div><div class='add'>+	/* Increase small mantissa to improve precision */</div><div class='add'>+	while (val &lt; MIN_LIN_MANTISSA &amp;&amp; exponent &gt; -15) {</div><div class='add'>+		exponent--;</div><div class='add'>+		val &lt;&lt;= 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Convert mantissa from milli-units to units */</div><div class='add'>+	mantissa = clamp_val(DIV_ROUND_CLOSEST_ULL(val, 1000), 0, 0x3ff);</div><div class='add'>+</div><div class='add'>+	/* restore sign */</div><div class='add'>+	if (negative)</div><div class='add'>+		mantissa = -mantissa;</div><div class='add'>+</div><div class='add'>+	/* Convert to 5 bit exponent, 11 bit mantissa */</div><div class='add'>+	return (mantissa &amp; 0x7ff) | ((exponent &lt;&lt; 11) &amp; 0xf800);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg,</div><div class='add'>+			u16 mask)</div><div class='add'>+{</div><div class='add'>+	int ret = pmbus_read_word_data(client, page, phase, reg);</div><div class='add'>+</div><div class='add'>+	return (ret &gt; 0) ? ret &amp; mask : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_vout(struct i2c_client *client, struct mp2856_data *data, int page,</div><div class='add'>+		 int phase, u8 reg)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mp2856_read_word_helper(client, page, phase, reg,</div><div class='add'>+				      GENMASK(9, 0));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* convert vout result to direct format */</div><div class='add'>+	ret = (data-&gt;vout_format[page] == vid) ?</div><div class='add'>+		((ret + 49) * 5) : ((ret * 1000) &gt;&gt; 8);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_phase(struct i2c_client *client, struct mp2856_data *data,</div><div class='add'>+		  int page, int phase, u8 reg)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	ret = pmbus_read_word_data(client, page, phase, reg);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!((phase + 1) % MP2856_PAGE_NUM))</div><div class='add'>+		ret &gt;&gt;= 8;</div><div class='add'>+	ret &amp;= 0xff;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Output value is calculated as: (READ_CSx * 12.5mV - 1.23V) / (Kcs * Rcs)</div><div class='add'>+	 */</div><div class='add'>+	val = (ret * 125) - 12300;</div><div class='add'>+</div><div class='add'>+	return val2linear11(val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_phases(struct i2c_client *client, struct mp2856_data *data,</div><div class='add'>+		   int page, int phase)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (page == 0) {</div><div class='add'>+		switch (phase) {</div><div class='add'>+		case 0 ... 1:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS1_2_R1);</div><div class='add'>+			break;</div><div class='add'>+		case 2 ... 3:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS3_4_R1);</div><div class='add'>+			break;</div><div class='add'>+		case 4 ... 5:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS5_6_R1);</div><div class='add'>+			break;</div><div class='add'>+		case 6 ... 7:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS7_8_R1);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -ENODATA;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		switch (phase) {</div><div class='add'>+		case 0 ... 1:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS1_2_R2);</div><div class='add'>+			break;</div><div class='add'>+		case 2 ... 3:</div><div class='add'>+			ret = mp2856_read_phase(client, data, page, phase,</div><div class='add'>+						MP2856_MFR_READ_CS1_2_R2);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -ENODATA;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_word_data(struct i2c_client *client, int page,</div><div class='add'>+		      int phase, int reg)</div><div class='add'>+{</div><div class='add'>+	const struct pmbus_driver_info *info = pmbus_get_driver_info(client);</div><div class='add'>+	struct mp2856_data *data = to_mp2856_data(info);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case PMBUS_READ_VOUT:</div><div class='add'>+		ret = mp2856_read_vout(client, data, page, phase, reg);</div><div class='add'>+		break;</div><div class='add'>+	case PMBUS_READ_IOUT:</div><div class='add'>+		if (phase != 0xff)</div><div class='add'>+			ret = mp2856_read_phases(client, data, page, phase);</div><div class='add'>+		else</div><div class='add'>+			ret = pmbus_read_word_data(client, page, phase, reg);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_read_byte_data(struct i2c_client *client, int page, int reg)</div><div class='add'>+{</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case PMBUS_VOUT_MODE:</div><div class='add'>+		/* Enforce VOUT direct format. */</div><div class='add'>+		return PB_VOUT_MODE_DIRECT;</div><div class='add'>+	default:</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_identify_multiphase(struct i2c_client *client, u8 reg, u8 max_phase,</div><div class='add'>+			   u16 mask)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_word_data(client, reg);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret &amp;= mask;</div><div class='add'>+	return (ret &gt;= max_phase) ? max_phase : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_identify_multiphase_rail1(struct i2c_client *client,</div><div class='add'>+				 struct mp2856_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	ret = mp2856_identify_multiphase(client, MP2856_MFR_VR_MULTI_CONFIG_R1,</div><div class='add'>+					 MP2856_MAX_PHASE_RAIL1, GENMASK(3, 0));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;info.phases[0] = (ret &gt; data-&gt;max_phases[0]) ?</div><div class='add'>+				data-&gt;max_phases[0] : ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0 ; i &lt; data-&gt;info.phases[0]; i++)</div><div class='add'>+		data-&gt;info.pfunc[i] |= PMBUS_HAVE_IOUT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_identify_multiphase_rail2(struct i2c_client *client,</div><div class='add'>+				 struct mp2856_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	ret = mp2856_identify_multiphase(client, MP2856_MFR_VR_MULTI_CONFIG_R2,</div><div class='add'>+					 MP2856_MAX_PHASE_RAIL2, GENMASK(2, 0));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;info.phases[1] = (ret &gt; data-&gt;max_phases[1]) ?</div><div class='add'>+				data-&gt;max_phases[1] : ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0 ; i &lt; data-&gt;info.phases[0]; i++)</div><div class='add'>+		data-&gt;info.pfunc[i] |= PMBUS_HAVE_IOUT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_current_sense_gain_get(struct i2c_client *client,</div><div class='add'>+			      struct mp2856_data *data)</div><div class='add'>+{</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Obtain DrMOS current sense gain of power stage from the register</div><div class='add'>+	 * MP2856_MFR_VR_CONFIG1, bits 13-12. The value is selected as below:</div><div class='add'>+	 * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. Other</div><div class='add'>+	 * values are invalid.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0 ; i &lt; data-&gt;info.pages; i++) {</div><div class='add'>+		ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+		ret = i2c_smbus_read_word_data(client,</div><div class='add'>+					       MP2856_MFR_VR_CONFIG1);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		switch ((ret &amp; MP2856_DRMOS_KCS) &gt;&gt; 12) {</div><div class='add'>+		case 0:</div><div class='add'>+			data-&gt;curr_sense_gain[i] = 50;</div><div class='add'>+			break;</div><div class='add'>+		case 1:</div><div class='add'>+			data-&gt;curr_sense_gain[i] = 85;</div><div class='add'>+			break;</div><div class='add'>+		case 2:</div><div class='add'>+			data-&gt;curr_sense_gain[i] = 97;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			data-&gt;curr_sense_gain[i] = 100;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mp2856_identify_vout_format(struct i2c_client *client,</div><div class='add'>+			    struct mp2856_data *data)</div><div class='add'>+{</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; data-&gt;info.pages; i++) {</div><div class='add'>+		ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = i2c_smbus_read_word_data(client, MP2856_MFR_VR_CONFIG2);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		data-&gt;vout_format[i] = (ret &amp; MP2856_VOUT_MODE) ? linear : vid;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool</div><div class='add'>+mp2856_is_rail2_active(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_word_data(client, MP2856_MUL1_BOOT_SR_R2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return (ret &amp; MP2856_VR_ACTIVE) ? true : false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct pmbus_driver_info mp2856_info = {</div><div class='add'>+	.pages = MP2856_PAGE_NUM,</div><div class='add'>+	.format[PSC_VOLTAGE_IN] = linear,</div><div class='add'>+	.format[PSC_VOLTAGE_OUT] = direct,</div><div class='add'>+	.format[PSC_TEMPERATURE] = linear,</div><div class='add'>+	.format[PSC_CURRENT_IN] = linear,</div><div class='add'>+	.format[PSC_CURRENT_OUT] = linear,</div><div class='add'>+	.format[PSC_POWER] = linear,</div><div class='add'>+	.m[PSC_VOLTAGE_OUT] = 1,</div><div class='add'>+	.R[PSC_VOLTAGE_OUT] = 3,</div><div class='add'>+	.func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |</div><div class='add'>+		PMBUS_HAVE_IIN | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |</div><div class='add'>+		PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | PMBUS_HAVE_POUT |</div><div class='add'>+		PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT,</div><div class='add'>+	.func[1] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_IOUT |</div><div class='add'>+		PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_POUT | PMBUS_HAVE_TEMP,</div><div class='add'>+	.read_byte_data = mp2856_read_byte_data,</div><div class='add'>+	.read_word_data = mp2856_read_word_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mp2856_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct pmbus_driver_info *info;</div><div class='add'>+	struct mp2856_data *data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	data = devm_kzalloc(&amp;client-&gt;dev, sizeof(struct mp2856_data),</div><div class='add'>+			    GFP_KERNEL);</div><div class='add'>+	if (!data)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	data-&gt;chip_id = (enum chips)(uintptr_t)i2c_get_match_data(client);</div><div class='add'>+</div><div class='add'>+	memcpy(data-&gt;max_phases, mp2856_max_phases[data-&gt;chip_id],</div><div class='add'>+	       sizeof(data-&gt;max_phases));</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;data-&gt;info, &amp;mp2856_info, sizeof(*info));</div><div class='add'>+	info = &amp;data-&gt;info;</div><div class='add'>+</div><div class='add'>+	/* Identify multiphase configuration. */</div><div class='add'>+	ret = mp2856_identify_multiphase_rail1(client, data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (mp2856_is_rail2_active(client)) {</div><div class='add'>+		ret = mp2856_identify_multiphase_rail2(client, data);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+	} else {</div><div class='add'>+		/* rail2 is not active */</div><div class='add'>+		info-&gt;pages = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Obtain current sense gain of power stage. */</div><div class='add'>+	ret = mp2856_current_sense_gain_get(client, data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Identify vout format. */</div><div class='add'>+	ret = mp2856_identify_vout_format(client, data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* set the device to page 0 */</div><div class='add'>+	i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0);</div><div class='add'>+</div><div class='add'>+	return pmbus_do_probe(client, info);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id __maybe_unused mp2856_of_match[] = {</div><div class='add'>+	{.compatible = "mps,mp2856", .data = (void *)mp2856},</div><div class='add'>+	{.compatible = "mps,mp2857", .data = (void *)mp2857},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, mp2856_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver mp2856_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "mp2856",</div><div class='add'>+		.of_match_table = mp2856_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = mp2856_probe,</div><div class='add'>+	.id_table = mp2856_id,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(mp2856_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Peter Yin &lt;peter.yin@quantatw.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("PMBus driver for MPS MP2856/MP2857 device");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(PMBUS);</div><div class='head'>diff --git a/drivers/hwmon/pmbus/mp5990.c b/drivers/hwmon/pmbus/mp5990.c<br/>new file mode 100644<br/>index 000000000000..1dfbab25a064<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pmbus/mp5990.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pmbus/mp5990.c</a></div><div class='hunk'>@@ -0,0 +1,179 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Driver for MPS MP5990 Hot-Swap Controller</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include "pmbus.h"</div><div class='add'>+</div><div class='add'>+#define MP5990_EFUSE_CFG	(0xC4)</div><div class='add'>+#define MP5990_VOUT_FORMAT	BIT(9)</div><div class='add'>+</div><div class='add'>+struct mp5990_data {</div><div class='add'>+	struct pmbus_driver_info info;</div><div class='add'>+	u8 vout_mode;</div><div class='add'>+	u8 vout_linear_exponent;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_mp5990_data(x)  container_of(x, struct mp5990_data, info)</div><div class='add'>+</div><div class='add'>+static int mp5990_read_byte_data(struct i2c_client *client, int page, int reg)</div><div class='add'>+{</div><div class='add'>+	const struct pmbus_driver_info *info = pmbus_get_driver_info(client);</div><div class='add'>+	struct mp5990_data *data = to_mp5990_data(info);</div><div class='add'>+</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case PMBUS_VOUT_MODE:</div><div class='add'>+		if (data-&gt;vout_mode == linear) {</div><div class='add'>+			/*</div><div class='add'>+			 * The VOUT format used by the chip is linear11,</div><div class='add'>+			 * not linear16. Report that VOUT is in linear mode</div><div class='add'>+			 * and return exponent value extracted while probing</div><div class='add'>+			 * the chip.</div><div class='add'>+			 */</div><div class='add'>+			return data-&gt;vout_linear_exponent;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The datasheet does not support the VOUT command,</div><div class='add'>+		 * but the device responds with a default value of 0x17.</div><div class='add'>+		 * In the standard, 0x17 represents linear mode.</div><div class='add'>+		 * Therefore, we should report that VOUT is in direct</div><div class='add'>+		 * format when the chip is configured for it.</div><div class='add'>+		 */</div><div class='add'>+		return PB_VOUT_MODE_DIRECT;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mp5990_read_word_data(struct i2c_client *client, int page,</div><div class='add'>+				 int phase, int reg)</div><div class='add'>+{</div><div class='add'>+	const struct pmbus_driver_info *info = pmbus_get_driver_info(client);</div><div class='add'>+	struct mp5990_data *data = to_mp5990_data(info);</div><div class='add'>+	int ret;</div><div class='add'>+	s32 mantissa;</div><div class='add'>+</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case PMBUS_READ_VOUT:</div><div class='add'>+		ret = pmbus_read_word_data(client, page, phase, reg);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+		/*</div><div class='add'>+		 * Because the VOUT format used by the chip is linear11 and not</div><div class='add'>+		 * linear16, we disregard bits[15:11]. The exponent is reported</div><div class='add'>+		 * as part of the VOUT_MODE command.</div><div class='add'>+		 */</div><div class='add'>+		if (data-&gt;vout_mode == linear) {</div><div class='add'>+			mantissa = ((s16)((ret &amp; 0x7ff) &lt;&lt; 5)) &gt;&gt; 5;</div><div class='add'>+			ret = mantissa;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct pmbus_driver_info mp5990_info = {</div><div class='add'>+	.pages = 1,</div><div class='add'>+	.format[PSC_VOLTAGE_IN] = direct,</div><div class='add'>+	.format[PSC_VOLTAGE_OUT] = direct,</div><div class='add'>+	.format[PSC_CURRENT_OUT] = direct,</div><div class='add'>+	.format[PSC_POWER] = direct,</div><div class='add'>+	.format[PSC_TEMPERATURE] = direct,</div><div class='add'>+	.m[PSC_VOLTAGE_IN] = 32,</div><div class='add'>+	.b[PSC_VOLTAGE_IN] = 0,</div><div class='add'>+	.R[PSC_VOLTAGE_IN] = 0,</div><div class='add'>+	.m[PSC_VOLTAGE_OUT] = 32,</div><div class='add'>+	.b[PSC_VOLTAGE_OUT] = 0,</div><div class='add'>+	.R[PSC_VOLTAGE_OUT] = 0,</div><div class='add'>+	.m[PSC_CURRENT_OUT] = 16,</div><div class='add'>+	.b[PSC_CURRENT_OUT] = 0,</div><div class='add'>+	.R[PSC_CURRENT_OUT] = 0,</div><div class='add'>+	.m[PSC_POWER] = 1,</div><div class='add'>+	.b[PSC_POWER] = 0,</div><div class='add'>+	.R[PSC_POWER] = 0,</div><div class='add'>+	.m[PSC_TEMPERATURE] = 1,</div><div class='add'>+	.b[PSC_TEMPERATURE] = 0,</div><div class='add'>+	.R[PSC_TEMPERATURE] = 0,</div><div class='add'>+	.func[0] =</div><div class='add'>+		PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_PIN |</div><div class='add'>+		PMBUS_HAVE_TEMP | PMBUS_HAVE_IOUT |</div><div class='add'>+		PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP,</div><div class='add'>+	.read_byte_data = mp5990_read_byte_data,</div><div class='add'>+	.read_word_data = mp5990_read_word_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mp5990_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct pmbus_driver_info *info;</div><div class='add'>+	struct mp5990_data *data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	data = devm_kzalloc(&amp;client-&gt;dev, sizeof(struct mp5990_data),</div><div class='add'>+			    GFP_KERNEL);</div><div class='add'>+	if (!data)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;data-&gt;info, &amp;mp5990_info, sizeof(*info));</div><div class='add'>+	info = &amp;data-&gt;info;</div><div class='add'>+</div><div class='add'>+	/* Read Vout Config */</div><div class='add'>+	ret = i2c_smbus_read_word_data(client, MP5990_EFUSE_CFG);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Can't get vout mode.");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * EFUSE_CFG (0xC4) bit9=1 is linear mode, bit=0 is direct mode.</div><div class='add'>+	 */</div><div class='add'>+	if (ret &amp; MP5990_VOUT_FORMAT) {</div><div class='add'>+		data-&gt;vout_mode = linear;</div><div class='add'>+		data-&gt;info.format[PSC_VOLTAGE_IN] = linear;</div><div class='add'>+		data-&gt;info.format[PSC_VOLTAGE_OUT] = linear;</div><div class='add'>+		data-&gt;info.format[PSC_CURRENT_OUT] = linear;</div><div class='add'>+		data-&gt;info.format[PSC_POWER] = linear;</div><div class='add'>+		ret = i2c_smbus_read_word_data(client, PMBUS_READ_VOUT);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev, "Can't get vout exponent.");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+		data-&gt;vout_linear_exponent = (u8)((ret &gt;&gt; 11) &amp; 0x1f);</div><div class='add'>+	} else {</div><div class='add'>+		data-&gt;vout_mode = direct;</div><div class='add'>+	}</div><div class='add'>+	return pmbus_do_probe(client, info);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id mp5990_of_match[] = {</div><div class='add'>+	{ .compatible = "mps,mp5990" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id mp5990_id[] = {</div><div class='add'>+	{"mp5990", 0},</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, mp5990_id);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver mp5990_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		   .name = "mp5990",</div><div class='add'>+		   .of_match_table = mp5990_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = mp5990_probe,</div><div class='add'>+	.id_table = mp5990_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(mp5990_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Peter Yin &lt;peter.yin@quantatw.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("PMBus driver for MP5990 HSC");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(PMBUS);</div><div class='head'>diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c<br/>index 6e4516c2ab89..b67bc9e833c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/pwm-fan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/pwm-fan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/pwm-fan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/pwm-fan.c</a></div><div class='hunk'>@@ -151,7 +151,7 @@ static int pwm_fan_power_on(struct pwm_fan_ctx *ctx)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	state-&gt;enabled = true;</div><div class='del'>-	ret = pwm_apply_state(ctx-&gt;pwm, state);</div><div class='add'>+	ret = pwm_apply_might_sleep(ctx-&gt;pwm, state);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(ctx-&gt;dev, "failed to enable PWM\n");</div><div class='ctx'> 		goto disable_regulator;</div><div class='hunk'>@@ -181,7 +181,7 @@ static int pwm_fan_power_off(struct pwm_fan_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	state-&gt;enabled = false;</div><div class='ctx'> 	state-&gt;duty_cycle = 0;</div><div class='del'>-	ret = pwm_apply_state(ctx-&gt;pwm, state);</div><div class='add'>+	ret = pwm_apply_might_sleep(ctx-&gt;pwm, state);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(ctx-&gt;dev, "failed to disable PWM\n");</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -207,7 +207,7 @@ static int  __set_pwm(struct pwm_fan_ctx *ctx, unsigned long pwm)</div><div class='ctx'> </div><div class='ctx'> 		period = state-&gt;period;</div><div class='ctx'> 		state-&gt;duty_cycle = DIV_ROUND_UP(pwm * (period - 1), MAX_PWM);</div><div class='del'>-		ret = pwm_apply_state(ctx-&gt;pwm, state);</div><div class='add'>+		ret = pwm_apply_might_sleep(ctx-&gt;pwm, state);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		ret = pwm_fan_power_on(ctx);</div><div class='hunk'>@@ -278,7 +278,7 @@ static int pwm_fan_update_enable(struct pwm_fan_ctx *ctx, long val)</div><div class='ctx'> 						    state,</div><div class='ctx'> 						    &amp;enable_regulator);</div><div class='ctx'> </div><div class='del'>-			pwm_apply_state(ctx-&gt;pwm, state);</div><div class='add'>+			pwm_apply_might_sleep(ctx-&gt;pwm, state);</div><div class='ctx'> 			pwm_fan_switch_power(ctx, enable_regulator);</div><div class='ctx'> 			pwm_fan_update_state(ctx, 0);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/hwmon/sht4x.c b/drivers/hwmon/sht4x.c<br/>index 7ee797410458..4883755d4b1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/sht4x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/sht4x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/sht4x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/sht4x.c</a></div><div class='hunk'>@@ -49,6 +49,7 @@ DECLARE_CRC8_TABLE(sht4x_crc8_table);</div><div class='ctx'>  * struct sht4x_data - All the data required to operate an SHT4X chip</div><div class='ctx'>  * @client: the i2c client associated with the SHT4X</div><div class='ctx'>  * @lock: a mutex that is used to prevent parallel access to the i2c client</div><div class='add'>+ * @valid: validity of fields below</div><div class='ctx'>  * @update_interval: the minimum poll interval</div><div class='ctx'>  * @last_updated: the previous time that the SHT4X was polled</div><div class='ctx'>  * @temperature: the latest temperature value received from the SHT4X</div><div class='hunk'>@@ -66,7 +67,7 @@ struct sht4x_data {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * sht4x_read_values() - read and parse the raw data from the SHT4X</div><div class='del'>- * @sht4x_data: the struct sht4x_data to use for the lock</div><div class='add'>+ * @data: the struct sht4x_data to use for the lock</div><div class='ctx'>  * Return: 0 if successful, -ERRNO if not</div><div class='ctx'>  */</div><div class='ctx'> static int sht4x_read_values(struct sht4x_data *data)</div><div class='head'>diff --git a/drivers/hwmon/smsc47m1.c b/drivers/hwmon/smsc47m1.c<br/>index 37531b5c8254..0d46edbcb144 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/smsc47m1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/smsc47m1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/smsc47m1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/smsc47m1.c</a></div><div class='hunk'>@@ -33,7 +33,7 @@ static unsigned short force_id;</div><div class='ctx'> module_param(force_id, ushort, 0);</div><div class='ctx'> MODULE_PARM_DESC(force_id, "Override the detected device ID");</div><div class='ctx'> </div><div class='del'>-static struct platform_device *pdev;</div><div class='add'>+static struct platform_device *smsc47m1_pdev;</div><div class='ctx'> </div><div class='ctx'> #define DRVNAME "smsc47m1"</div><div class='ctx'> enum chips { smsc47m1, smsc47m2 };</div><div class='hunk'>@@ -840,70 +840,57 @@ error_remove_files:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit smsc47m1_remove(struct platform_device *pdev)</div><div class='add'>+static void __exit smsc47m1_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct smsc47m1_data *data = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	hwmon_device_unregister(data-&gt;hwmon_dev);</div><div class='ctx'> 	smsc47m1_remove_files(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct platform_driver smsc47m1_driver = {</div><div class='add'>+/*</div><div class='add'>+ * smsc47m1_remove() lives in .exit.text. For drivers registered via</div><div class='add'>+ * module_platform_driver_probe() this ok because they cannot get unbound at</div><div class='add'>+ * runtime. The driver needs to be marked with __refdata, otherwise modpost</div><div class='add'>+ * triggers a section mismatch warning.</div><div class='add'>+ */</div><div class='add'>+static struct platform_driver smsc47m1_driver __refdata = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= DRVNAME,</div><div class='ctx'> 	},</div><div class='del'>-	.remove		= __exit_p(smsc47m1_remove),</div><div class='add'>+	.remove_new	= __exit_p(smsc47m1_remove),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init smsc47m1_device_add(unsigned short address,</div><div class='ctx'> 				      const struct smsc47m1_sio_data *sio_data)</div><div class='ctx'> {</div><div class='del'>-	struct resource res = {</div><div class='add'>+	const struct resource res = {</div><div class='ctx'> 		.start	= address,</div><div class='ctx'> 		.end	= address + SMSC_EXTENT - 1,</div><div class='ctx'> 		.name	= DRVNAME,</div><div class='ctx'> 		.flags	= IORESOURCE_IO,</div><div class='ctx'> 	};</div><div class='add'>+	const struct platform_device_info pdevinfo = {</div><div class='add'>+		.name = DRVNAME,</div><div class='add'>+		.id = address,</div><div class='add'>+		.res = &amp;res,</div><div class='add'>+		.num_res = 1,</div><div class='add'>+		.data = sio_data,</div><div class='add'>+		.size_data = sizeof(struct smsc47m1_sio_data),</div><div class='add'>+	};</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = smsc47m1_handle_resources(address, sio_data-&gt;type, CHECK, NULL);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto exit;</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='del'>-	pdev = platform_device_alloc(DRVNAME, address);</div><div class='del'>-	if (!pdev) {</div><div class='del'>-		err = -ENOMEM;</div><div class='add'>+	smsc47m1_pdev = platform_device_register_full(&amp;pdevinfo);</div><div class='add'>+	if (IS_ERR(smsc47m1_pdev)) {</div><div class='ctx'> 		pr_err("Device allocation failed\n");</div><div class='del'>-		goto exit;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	err = platform_device_add_resources(pdev, &amp;res, 1);</div><div class='del'>-	if (err) {</div><div class='del'>-		pr_err("Device resource addition failed (%d)\n", err);</div><div class='del'>-		goto exit_device_put;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	err = platform_device_add_data(pdev, sio_data,</div><div class='del'>-				       sizeof(struct smsc47m1_sio_data));</div><div class='del'>-	if (err) {</div><div class='del'>-		pr_err("Platform data allocation failed\n");</div><div class='del'>-		goto exit_device_put;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	err = platform_device_add(pdev);</div><div class='del'>-	if (err) {</div><div class='del'>-		pr_err("Device addition failed (%d)\n", err);</div><div class='del'>-		goto exit_device_put;</div><div class='add'>+		return PTR_ERR(smsc47m1_pdev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='del'>-exit_device_put:</div><div class='del'>-	platform_device_put(pdev);</div><div class='del'>-exit:</div><div class='del'>-	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __init sm_smsc47m1_init(void)</div><div class='hunk'>@@ -917,7 +904,7 @@ static int __init sm_smsc47m1_init(void)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	address = err;</div><div class='ctx'> </div><div class='del'>-	/* Sets global pdev as a side effect */</div><div class='add'>+	/* Sets global smsc47m1_pdev as a side effect */</div><div class='ctx'> 	err = smsc47m1_device_add(address, &amp;sio_data);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -929,7 +916,7 @@ static int __init sm_smsc47m1_init(void)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> exit_device:</div><div class='del'>-	platform_device_unregister(pdev);</div><div class='add'>+	platform_device_unregister(smsc47m1_pdev);</div><div class='ctx'> 	smsc47m1_restore(&amp;sio_data);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -937,8 +924,8 @@ exit_device:</div><div class='ctx'> static void __exit sm_smsc47m1_exit(void)</div><div class='ctx'> {</div><div class='ctx'> 	platform_driver_unregister(&amp;smsc47m1_driver);</div><div class='del'>-	smsc47m1_restore(dev_get_platdata(&amp;pdev-&gt;dev));</div><div class='del'>-	platform_device_unregister(pdev);</div><div class='add'>+	smsc47m1_restore(dev_get_platdata(&amp;smsc47m1_pdev-&gt;dev));</div><div class='add'>+	platform_device_unregister(smsc47m1_pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Mark D. Studebaker &lt;mdsxyz123@yahoo.com&gt;");</div><div class='head'>diff --git a/drivers/hwmon/tmp513.c b/drivers/hwmon/tmp513.c<br/>index 8a7cf08733c6..ea6f4416c124 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwmon/tmp513.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwmon/tmp513.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwmon/tmp513.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwmon/tmp513.c</a></div><div class='hunk'>@@ -19,15 +19,20 @@</div><div class='ctx'>  * the Free Software Foundation; version 2 of the License.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/bug.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/hwmon.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/math.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/util_macros.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='ctx'> </div><div class='ctx'> // Common register definition</div><div class='ctx'> #define TMP51X_SHUNT_CONFIG		0x00</div><div class='hunk'>@@ -97,8 +102,8 @@</div><div class='ctx'> #define TMP51X_REMOTE_TEMP_LIMIT_2_POS		8</div><div class='ctx'> #define TMP513_REMOTE_TEMP_LIMIT_3_POS		7</div><div class='ctx'> </div><div class='del'>-#define TMP51X_VBUS_RANGE_32V		32000000</div><div class='del'>-#define TMP51X_VBUS_RANGE_16V		16000000</div><div class='add'>+#define TMP51X_VBUS_RANGE_32V		(32 * MICRO)</div><div class='add'>+#define TMP51X_VBUS_RANGE_16V		(16 * MICRO)</div><div class='ctx'> </div><div class='ctx'> // Max and Min value</div><div class='ctx'> #define MAX_BUS_VOLTAGE_32_LIMIT	32764</div><div class='hunk'>@@ -200,7 +205,7 @@ static int tmp51x_get_value(struct tmp51x_data *data, u8 reg, u8 pos,</div><div class='ctx'> 		 * on the pga gain setting. 1lsb = 10uV</div><div class='ctx'> 		 */</div><div class='ctx'> 		*val = sign_extend32(regval, 17 - tmp51x_get_pga_shift(data));</div><div class='del'>-		*val = DIV_ROUND_CLOSEST(*val * 10000, data-&gt;shunt_uohms);</div><div class='add'>+		*val = DIV_ROUND_CLOSEST(*val * 10 * MILLI, data-&gt;shunt_uohms);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TMP51X_BUS_VOLTAGE_RESULT:</div><div class='ctx'> 	case TMP51X_BUS_VOLTAGE_H_LIMIT:</div><div class='hunk'>@@ -216,7 +221,7 @@ static int tmp51x_get_value(struct tmp51x_data *data, u8 reg, u8 pos,</div><div class='ctx'> 	case TMP51X_BUS_CURRENT_RESULT:</div><div class='ctx'> 		// Current = (ShuntVoltage * CalibrationRegister) / 4096</div><div class='ctx'> 		*val = sign_extend32(regval, 16) * data-&gt;curr_lsb_ua;</div><div class='del'>-		*val = DIV_ROUND_CLOSEST(*val, 1000);</div><div class='add'>+		*val = DIV_ROUND_CLOSEST(*val, MILLI);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TMP51X_LOCAL_TEMP_RESULT:</div><div class='ctx'> 	case TMP51X_REMOTE_TEMP_RESULT_1:</div><div class='hunk'>@@ -256,7 +261,7 @@ static int tmp51x_set_value(struct tmp51x_data *data, u8 reg, long val)</div><div class='ctx'> 		 * The user enter current value and we convert it to</div><div class='ctx'> 		 * voltage. 1lsb = 10uV</div><div class='ctx'> 		 */</div><div class='del'>-		val = DIV_ROUND_CLOSEST(val * data-&gt;shunt_uohms, 10000);</div><div class='add'>+		val = DIV_ROUND_CLOSEST(val * data-&gt;shunt_uohms, 10 * MILLI);</div><div class='ctx'> 		max_val = U16_MAX &gt;&gt; tmp51x_get_pga_shift(data);</div><div class='ctx'> 		regval = clamp_val(val, -max_val, max_val);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -546,18 +551,16 @@ static int tmp51x_calibrate(struct tmp51x_data *data)</div><div class='ctx'> 	if (data-&gt;shunt_uohms == 0)</div><div class='ctx'> 		return regmap_write(data-&gt;regmap, TMP51X_SHUNT_CALIBRATION, 0);</div><div class='ctx'> </div><div class='del'>-	max_curr_ma = DIV_ROUND_CLOSEST_ULL(vshunt_max * 1000 * 1000,</div><div class='del'>-					    data-&gt;shunt_uohms);</div><div class='add'>+	max_curr_ma = DIV_ROUND_CLOSEST_ULL(vshunt_max * MICRO, data-&gt;shunt_uohms);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Calculate the minimal bit resolution for the current and the power.</div><div class='ctx'> 	 * Those values will be used during register interpretation.</div><div class='ctx'> 	 */</div><div class='del'>-	data-&gt;curr_lsb_ua = DIV_ROUND_CLOSEST_ULL(max_curr_ma * 1000, 32767);</div><div class='add'>+	data-&gt;curr_lsb_ua = DIV_ROUND_CLOSEST_ULL(max_curr_ma * MILLI, 32767);</div><div class='ctx'> 	data-&gt;pwr_lsb_uw = 20 * data-&gt;curr_lsb_ua;</div><div class='ctx'> </div><div class='del'>-	div = DIV_ROUND_CLOSEST_ULL(data-&gt;curr_lsb_ua * data-&gt;shunt_uohms,</div><div class='del'>-				    1000 * 1000);</div><div class='add'>+	div = DIV_ROUND_CLOSEST_ULL(data-&gt;curr_lsb_ua * data-&gt;shunt_uohms, MICRO);</div><div class='ctx'> </div><div class='ctx'> 	return regmap_write(data-&gt;regmap, TMP51X_SHUNT_CALIBRATION,</div><div class='ctx'> 			    DIV_ROUND_CLOSEST(40960, div));</div><div class='hunk'>@@ -626,9 +629,9 @@ static int tmp51x_vbus_range_to_reg(struct device *dev,</div><div class='ctx'> 	} else if (data-&gt;vbus_range_uvolt == TMP51X_VBUS_RANGE_16V) {</div><div class='ctx'> 		data-&gt;shunt_config &amp;= ~TMP51X_BUS_VOLTAGE_MASK;</div><div class='ctx'> 	} else {</div><div class='del'>-		dev_err(dev, "ti,bus-range-microvolt is invalid: %u\n",</div><div class='del'>-			data-&gt;vbus_range_uvolt);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				     "ti,bus-range-microvolt is invalid: %u\n",</div><div class='add'>+				     data-&gt;vbus_range_uvolt);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -644,8 +647,8 @@ static int tmp51x_pga_gain_to_reg(struct device *dev, struct tmp51x_data *data)</div><div class='ctx'> 	} else if (data-&gt;pga_gain == 1) {</div><div class='ctx'> 		data-&gt;shunt_config |= CURRENT_SENSE_VOLTAGE_40_MASK;</div><div class='ctx'> 	} else {</div><div class='del'>-		dev_err(dev, "ti,pga-gain is invalid: %u\n", data-&gt;pga_gain);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				     "ti,pga-gain is invalid: %u\n", data-&gt;pga_gain);</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -674,10 +677,10 @@ static int tmp51x_read_properties(struct device *dev, struct tmp51x_data *data)</div><div class='ctx'> 				       data-&gt;max_channels - 1);</div><div class='ctx'> </div><div class='ctx'> 	// Check if shunt value is compatible with pga-gain</div><div class='del'>-	if (data-&gt;shunt_uohms &gt; data-&gt;pga_gain * 40 * 1000 * 1000) {</div><div class='del'>-		dev_err(dev, "shunt-resistor: %u too big for pga_gain: %u\n",</div><div class='del'>-			data-&gt;shunt_uohms, data-&gt;pga_gain);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	if (data-&gt;shunt_uohms &gt; data-&gt;pga_gain * 40 * MICRO) {</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				     "shunt-resistor: %u too big for pga_gain: %u\n",</div><div class='add'>+				     data-&gt;shunt_uohms, data-&gt;pga_gain);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -717,22 +720,17 @@ static int tmp51x_probe(struct i2c_client *client)</div><div class='ctx'> 	data-&gt;max_channels = (uintptr_t)i2c_get_match_data(client);</div><div class='ctx'> </div><div class='ctx'> 	ret = tmp51x_configure(dev, data);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_err(dev, "error configuring the device: %d\n", ret);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(dev, ret, "error configuring the device\n");</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;regmap = devm_regmap_init_i2c(client, &amp;tmp51x_regmap_config);</div><div class='del'>-	if (IS_ERR(data-&gt;regmap)) {</div><div class='del'>-		dev_err(dev, "failed to allocate register map\n");</div><div class='del'>-		return PTR_ERR(data-&gt;regmap);</div><div class='del'>-	}</div><div class='add'>+	if (IS_ERR(data-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(data-&gt;regmap),</div><div class='add'>+				     "failed to allocate register map\n");</div><div class='ctx'> </div><div class='ctx'> 	ret = tmp51x_init(data);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_err(dev, "error configuring the device: %d\n", ret);</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(dev, ret, "error configuring the device\n");</div><div class='ctx'> </div><div class='ctx'> 	hwmon_dev = devm_hwmon_device_register_with_info(dev, client-&gt;name,</div><div class='ctx'> 							 data,</div><div class='head'>diff --git a/drivers/hwspinlock/hwspinlock_core.c b/drivers/hwspinlock/hwspinlock_core.c<br/>index ada694ba9f95..0c0a932c00f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwspinlock/hwspinlock_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwspinlock/hwspinlock_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwspinlock/hwspinlock_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwspinlock/hwspinlock_core.c</a></div><div class='hunk'>@@ -84,8 +84,9 @@ static DEFINE_MUTEX(hwspinlock_tree_lock);</div><div class='ctx'>  * should decide between spin_trylock, spin_trylock_irq and</div><div class='ctx'>  * spin_trylock_irqsave.</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 if we successfully locked the hwspinlock or -EBUSY if</div><div class='add'>+ * Returns: %0 if we successfully locked the hwspinlock or -EBUSY if</div><div class='ctx'>  * the hwspinlock was already taken.</div><div class='add'>+ *</div><div class='ctx'>  * This function will never sleep.</div><div class='ctx'>  */</div><div class='ctx'> int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags)</div><div class='hunk'>@@ -171,7 +172,7 @@ EXPORT_SYMBOL_GPL(__hwspin_trylock);</div><div class='ctx'> /**</div><div class='ctx'>  * __hwspin_lock_timeout() - lock an hwspinlock with timeout limit</div><div class='ctx'>  * @hwlock: the hwspinlock to be locked</div><div class='del'>- * @timeout: timeout value in msecs</div><div class='add'>+ * @to: timeout value in msecs</div><div class='ctx'>  * @mode: mode which controls whether local interrupts are disabled or not</div><div class='ctx'>  * @flags: a pointer to where the caller's interrupt state will be saved at (if</div><div class='ctx'>  *         requested)</div><div class='hunk'>@@ -199,9 +200,11 @@ EXPORT_SYMBOL_GPL(__hwspin_trylock);</div><div class='ctx'>  * to choose the appropriate @mode of operation, exactly the same way users</div><div class='ctx'>  * should decide between spin_lock, spin_lock_irq and spin_lock_irqsave.</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 when the @hwlock was successfully taken, and an appropriate</div><div class='add'>+ * Returns: %0 when the @hwlock was successfully taken, and an appropriate</div><div class='ctx'>  * error code otherwise (most notably -ETIMEDOUT if the @hwlock is still</div><div class='del'>- * busy after @timeout msecs). The function will never sleep.</div><div class='add'>+ * busy after @timeout msecs).</div><div class='add'>+ *</div><div class='add'>+ * The function will never sleep.</div><div class='ctx'>  */</div><div class='ctx'> int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to,</div><div class='ctx'> 					int mode, unsigned long *flags)</div><div class='hunk'>@@ -304,13 +307,12 @@ EXPORT_SYMBOL_GPL(__hwspin_unlock);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id</div><div class='del'>- * @bank: the hwspinlock device bank</div><div class='ctx'>  * @hwlock_spec: hwlock specifier as found in the device tree</div><div class='ctx'>  *</div><div class='ctx'>  * This is a simple translation function, suitable for hwspinlock platform</div><div class='ctx'>  * drivers that only has a lock specifier length of 1.</div><div class='ctx'>  *</div><div class='del'>- * Returns a relative index of the lock within a specified bank on success,</div><div class='add'>+ * Returns: a relative index of the lock within a specified bank on success,</div><div class='ctx'>  * or -EINVAL on invalid specifier cell count.</div><div class='ctx'>  */</div><div class='ctx'> static inline int</div><div class='hunk'>@@ -332,9 +334,10 @@ of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec)</div><div class='ctx'>  * hwspinlock device, so that it can be requested using the normal</div><div class='ctx'>  * hwspin_lock_request_specific() API.</div><div class='ctx'>  *</div><div class='del'>- * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock</div><div class='del'>- * device is not yet registered, -EINVAL on invalid args specifier value or an</div><div class='del'>- * appropriate error as returned from the OF parsing of the DT client node.</div><div class='add'>+ * Returns: the global lock id number on success, -EPROBE_DEFER if the</div><div class='add'>+ * hwspinlock device is not yet registered, -EINVAL on invalid args</div><div class='add'>+ * specifier value or an appropriate error as returned from the OF parsing</div><div class='add'>+ * of the DT client node.</div><div class='ctx'>  */</div><div class='ctx'> int of_hwspin_lock_get_id(struct device_node *np, int index)</div><div class='ctx'> {</div><div class='hunk'>@@ -399,9 +402,10 @@ EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id);</div><div class='ctx'>  * the hwspinlock device, so that it can be requested using the normal</div><div class='ctx'>  * hwspin_lock_request_specific() API.</div><div class='ctx'>  *</div><div class='del'>- * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock</div><div class='del'>- * device is not yet registered, -EINVAL on invalid args specifier value or an</div><div class='del'>- * appropriate error as returned from the OF parsing of the DT client node.</div><div class='add'>+ * Returns: the global lock id number on success, -EPROBE_DEFER if the</div><div class='add'>+ * hwspinlock device is not yet registered, -EINVAL on invalid args</div><div class='add'>+ * specifier value or an appropriate error as returned from the OF parsing</div><div class='add'>+ * of the DT client node.</div><div class='ctx'>  */</div><div class='ctx'> int of_hwspin_lock_get_id_byname(struct device_node *np, const char *name)</div><div class='ctx'> {</div><div class='hunk'>@@ -481,7 +485,7 @@ out:</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int hwspin_lock_register(struct hwspinlock_device *bank, struct device *dev,</div><div class='ctx'> 		const struct hwspinlock_ops *ops, int base_id, int num_locks)</div><div class='hunk'>@@ -529,7 +533,7 @@ EXPORT_SYMBOL_GPL(hwspin_lock_register);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int hwspin_lock_unregister(struct hwspinlock_device *bank)</div><div class='ctx'> {</div><div class='hunk'>@@ -578,7 +582,7 @@ static int devm_hwspin_lock_device_match(struct device *dev, void *res,</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int devm_hwspin_lock_unregister(struct device *dev,</div><div class='ctx'> 				struct hwspinlock_device *bank)</div><div class='hunk'>@@ -607,7 +611,7 @@ EXPORT_SYMBOL_GPL(devm_hwspin_lock_unregister);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int devm_hwspin_lock_register(struct device *dev,</div><div class='ctx'> 			      struct hwspinlock_device *bank,</div><div class='hunk'>@@ -635,12 +639,13 @@ EXPORT_SYMBOL_GPL(devm_hwspin_lock_register);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * __hwspin_lock_request() - tag an hwspinlock as used and power it up</div><div class='add'>+ * @hwlock: the target hwspinlock</div><div class='ctx'>  *</div><div class='ctx'>  * This is an internal function that prepares an hwspinlock instance</div><div class='ctx'>  * before it is given to the user. The function assumes that</div><div class='ctx'>  * hwspinlock_tree_lock is taken.</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 or positive to indicate success, and a negative value to</div><div class='add'>+ * Returns: %0 or positive to indicate success, and a negative value to</div><div class='ctx'>  * indicate an error (with the appropriate error code)</div><div class='ctx'>  */</div><div class='ctx'> static int __hwspin_lock_request(struct hwspinlock *hwlock)</div><div class='hunk'>@@ -680,7 +685,7 @@ static int __hwspin_lock_request(struct hwspinlock *hwlock)</div><div class='ctx'>  * hwspin_lock_get_id() - retrieve id number of a given hwspinlock</div><div class='ctx'>  * @hwlock: a valid hwspinlock instance</div><div class='ctx'>  *</div><div class='del'>- * Returns the id number of a given @hwlock, or -EINVAL if @hwlock is invalid.</div><div class='add'>+ * Returns: the id number of a given @hwlock, or -EINVAL if @hwlock is invalid.</div><div class='ctx'>  */</div><div class='ctx'> int hwspin_lock_get_id(struct hwspinlock *hwlock)</div><div class='ctx'> {</div><div class='hunk'>@@ -704,7 +709,7 @@ EXPORT_SYMBOL_GPL(hwspin_lock_get_id);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns the address of the assigned hwspinlock, or NULL on error</div><div class='add'>+ * Returns: the address of the assigned hwspinlock, or %NULL on error</div><div class='ctx'>  */</div><div class='ctx'> struct hwspinlock *hwspin_lock_request(void)</div><div class='ctx'> {</div><div class='hunk'>@@ -747,7 +752,7 @@ EXPORT_SYMBOL_GPL(hwspin_lock_request);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns the address of the assigned hwspinlock, or NULL on error</div><div class='add'>+ * Returns: the address of the assigned hwspinlock, or %NULL on error</div><div class='ctx'>  */</div><div class='ctx'> struct hwspinlock *hwspin_lock_request_specific(unsigned int id)</div><div class='ctx'> {</div><div class='hunk'>@@ -795,7 +800,7 @@ EXPORT_SYMBOL_GPL(hwspin_lock_request_specific);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int hwspin_lock_free(struct hwspinlock *hwlock)</div><div class='ctx'> {</div><div class='hunk'>@@ -865,7 +870,7 @@ static void devm_hwspin_lock_release(struct device *dev, void *res)</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns 0 on success, or an appropriate error code on failure</div><div class='add'>+ * Returns: %0 on success, or an appropriate error code on failure</div><div class='ctx'>  */</div><div class='ctx'> int devm_hwspin_lock_free(struct device *dev, struct hwspinlock *hwlock)</div><div class='ctx'> {</div><div class='hunk'>@@ -891,7 +896,7 @@ EXPORT_SYMBOL_GPL(devm_hwspin_lock_free);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns the address of the assigned hwspinlock, or NULL on error</div><div class='add'>+ * Returns: the address of the assigned hwspinlock, or %NULL on error</div><div class='ctx'>  */</div><div class='ctx'> struct hwspinlock *devm_hwspin_lock_request(struct device *dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -926,7 +931,7 @@ EXPORT_SYMBOL_GPL(devm_hwspin_lock_request);</div><div class='ctx'>  *</div><div class='ctx'>  * Should be called from a process context (might sleep)</div><div class='ctx'>  *</div><div class='del'>- * Returns the address of the assigned hwspinlock, or NULL on error</div><div class='add'>+ * Returns: the address of the assigned hwspinlock, or %NULL on error</div><div class='ctx'>  */</div><div class='ctx'> struct hwspinlock *devm_hwspin_lock_request_specific(struct device *dev,</div><div class='ctx'> 						     unsigned int id)</div><div class='head'>diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c<br/>index a0fd67fd2934..814dfe8697bf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwspinlock/qcom_hwspinlock.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwspinlock/qcom_hwspinlock.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwspinlock/qcom_hwspinlock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwspinlock/qcom_hwspinlock.c</a></div><div class='hunk'>@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,sfpb-mutex", .data = &amp;of_sfpb_mutex },</div><div class='ctx'> 	{ .compatible = "qcom,tcsr-mutex", .data = &amp;of_tcsr_mutex },</div><div class='ctx'> 	{ .compatible = "qcom,apq8084-tcsr-mutex", .data = &amp;of_msm8226_tcsr_mutex },</div><div class='del'>-	{ .compatible = "qcom,ipq6018-tcsr-mutex", .data = &amp;of_msm8226_tcsr_mutex },</div><div class='ctx'> 	{ .compatible = "qcom,msm8226-tcsr-mutex", .data = &amp;of_msm8226_tcsr_mutex },</div><div class='ctx'> 	{ .compatible = "qcom,msm8974-tcsr-mutex", .data = &amp;of_msm8226_tcsr_mutex },</div><div class='ctx'> 	{ .compatible = "qcom,msm8994-tcsr-mutex", .data = &amp;of_msm8226_tcsr_mutex },</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c<br/>index 9fabe00a40d6..d7f0e231feb9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-core.c</a></div><div class='hunk'>@@ -1093,6 +1093,7 @@ static int coresight_validate_source(struct coresight_device *csdev,</div><div class='ctx'> </div><div class='ctx'> 	if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &amp;&amp;</div><div class='ctx'> 	    subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &amp;&amp;</div><div class='add'>+	    subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM &amp;&amp;</div><div class='ctx'> 	    subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) {</div><div class='ctx'> 		dev_err(&amp;csdev-&gt;dev, "wrong device subtype in %s\n", function);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1162,6 +1163,7 @@ int coresight_enable(struct coresight_device *csdev)</div><div class='ctx'> 		per_cpu(tracer_path, cpu) = path;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:</div><div class='add'>+	case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM:</div><div class='ctx'> 	case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Use the hash of source's device name as ID</div><div class='hunk'>@@ -1212,6 +1214,7 @@ void coresight_disable(struct coresight_device *csdev)</div><div class='ctx'> 		per_cpu(tracer_path, cpu) = NULL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:</div><div class='add'>+	case CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM:</div><div class='ctx'> 	case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS:</div><div class='ctx'> 		hash = hashlen_hash(hashlen_string(NULL, dev_name(&amp;csdev-&gt;dev)));</div><div class='ctx'> 		/* Find the path by the hash. */</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c<br/>index e4deafae7bc2..ac70c0b491be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-dummy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-dummy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-dummy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-dummy.c</a></div><div class='hunk'>@@ -122,14 +122,13 @@ static int dummy_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dummy_remove(struct platform_device *pdev)</div><div class='add'>+static void dummy_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dummy_drvdata *drvdata = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(dev);</div><div class='ctx'> 	coresight_unregister(drvdata-&gt;csdev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id dummy_match[] = {</div><div class='hunk'>@@ -140,7 +139,7 @@ static const struct of_device_id dummy_match[] = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver dummy_driver = {</div><div class='ctx'> 	.probe	= dummy_probe,</div><div class='del'>-	.remove	= dummy_remove,</div><div class='add'>+	.remove_new = dummy_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name   = "coresight-dummy",</div><div class='ctx'> 		.of_match_table = dummy_match,</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c<br/>index 5ca6278baff4..a52cfcce25d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm-perf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-etm-perf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm-perf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm-perf.c</a></div><div class='hunk'>@@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset,		"config:0-3");</div><div class='ctx'> PMU_FORMAT_ATTR(sinkid,		"config2:0-31");</div><div class='ctx'> /* config ID - set if a system configuration is selected */</div><div class='ctx'> PMU_FORMAT_ATTR(configid,	"config2:32-63");</div><div class='add'>+PMU_FORMAT_ATTR(cc_threshold,	"config3:0-11");</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = {</div><div class='ctx'> 	&amp;format_attr_preset.attr,</div><div class='ctx'> 	&amp;format_attr_configid.attr,</div><div class='ctx'> 	&amp;format_attr_branch_broadcast.attr,</div><div class='add'>+	&amp;format_attr_cc_threshold.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -493,7 +495,7 @@ static void etm_event_start(struct perf_event *event, int flags)</div><div class='ctx'> 		goto fail_end_stop;</div><div class='ctx'> </div><div class='ctx'> 	/* Finally enable the tracer */</div><div class='del'>-	if (coresight_enable_source(csdev, CS_MODE_PERF, event))</div><div class='add'>+	if (source_ops(csdev)-&gt;enable(csdev, event, CS_MODE_PERF))</div><div class='ctx'> 		goto fail_disable_path;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -587,7 +589,7 @@ static void etm_event_stop(struct perf_event *event, int mode)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* stop tracer */</div><div class='del'>-	coresight_disable_source(csdev, event);</div><div class='add'>+	source_ops(csdev)-&gt;disable(csdev, event);</div><div class='ctx'> </div><div class='ctx'> 	/* tell the core */</div><div class='ctx'> 	event-&gt;hw.state = PERF_HES_STOPPED;</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c<br/>index 77b0271ce6eb..ce1995a2827f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm4x-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-etm4x-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm4x-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm4x-core.c</a></div><div class='hunk'>@@ -644,7 +644,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,</div><div class='ctx'> 	struct etmv4_config *config = &amp;drvdata-&gt;config;</div><div class='ctx'> 	struct perf_event_attr *attr = &amp;event-&gt;attr;</div><div class='ctx'> 	unsigned long cfg_hash;</div><div class='del'>-	int preset;</div><div class='add'>+	int preset, cc_threshold;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear configuration from previous run */</div><div class='ctx'> 	memset(config, 0, sizeof(struct etmv4_config));</div><div class='hunk'>@@ -667,7 +667,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev,</div><div class='ctx'> 	if (attr-&gt;config &amp; BIT(ETM_OPT_CYCACC)) {</div><div class='ctx'> 		config-&gt;cfg |= TRCCONFIGR_CCI;</div><div class='ctx'> 		/* TRM: Must program this for cycacc to work */</div><div class='del'>-		config-&gt;ccctlr = ETM_CYC_THRESHOLD_DEFAULT;</div><div class='add'>+		cc_threshold = attr-&gt;config3 &amp; ETM_CYC_THRESHOLD_MASK;</div><div class='add'>+		if (!cc_threshold)</div><div class='add'>+			cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;</div><div class='add'>+		if (cc_threshold &lt; drvdata-&gt;ccitmin)</div><div class='add'>+			cc_threshold = drvdata-&gt;ccitmin;</div><div class='add'>+		config-&gt;ccctlr = cc_threshold;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (attr-&gt;config &amp; BIT(ETM_OPT_TS)) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -1150,6 +1155,41 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)</div><div class='ctx'> 	drvdata-&gt;trfcr = trfcr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * The following errata on applicable cpu ranges, affect the CCITMIN filed</div><div class='add'>+ * in TCRIDR3 register. Software read for the field returns 0x100 limiting</div><div class='add'>+ * the cycle threshold granularity, whereas the right value should have</div><div class='add'>+ * been 0x4, which is well supported in the hardware.</div><div class='add'>+ */</div><div class='add'>+static struct midr_range etm_wrong_ccitmin_cpus[] = {</div><div class='add'>+	/* Erratum #1490853 - Cortex-A76 */</div><div class='add'>+	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),</div><div class='add'>+	/* Erratum #1490853 - Neoverse-N1 */</div><div class='add'>+	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),</div><div class='add'>+	/* Erratum #1491015 - Cortex-A77 */</div><div class='add'>+	MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),</div><div class='add'>+	/* Erratum #1502854 - Cortex-X1 */</div><div class='add'>+	MIDR_REV(MIDR_CORTEX_X1, 0, 0),</div><div class='add'>+	/* Erratum #1619801 - Neoverse-V1 */</div><div class='add'>+	MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Erratum affected cpus will read 256 as the minimum</div><div class='add'>+	 * instruction trace cycle counting threshold whereas</div><div class='add'>+	 * the correct value should be 4 instead. Override the</div><div class='add'>+	 * recorded value for 'drvdata-&gt;ccitmin' to workaround</div><div class='add'>+	 * this problem.</div><div class='add'>+	 */</div><div class='add'>+	if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) {</div><div class='add'>+		if (drvdata-&gt;ccitmin == 256)</div><div class='add'>+			drvdata-&gt;ccitmin = 4;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void etm4_init_arch_data(void *info)</div><div class='ctx'> {</div><div class='ctx'> 	u32 etmidr0;</div><div class='hunk'>@@ -1214,6 +1254,8 @@ static void etm4_init_arch_data(void *info)</div><div class='ctx'> 	etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);</div><div class='ctx'> 	/* CCITMIN, bits[11:0] minimum threshold value that can be programmed */</div><div class='ctx'> 	drvdata-&gt;ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);</div><div class='add'>+	etm4_fixup_wrong_ccitmin(drvdata);</div><div class='add'>+</div><div class='ctx'> 	/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */</div><div class='ctx'> 	drvdata-&gt;s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);</div><div class='ctx'> 	drvdata-&gt;config.s_ex_level = drvdata-&gt;s_ex_level;</div><div class='hunk'>@@ -2224,7 +2266,7 @@ static void clear_etmdrvdata(void *info)</div><div class='ctx'> 	per_cpu(delayed_probe, cpu) = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)</div><div class='add'>+static void etm4_remove_dev(struct etmv4_drvdata *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	bool had_delayed_probe;</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2253,7 +2295,7 @@ static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __exit etm4_remove_amba(struct amba_device *adev)</div><div class='add'>+static void etm4_remove_amba(struct amba_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct etmv4_drvdata *drvdata = dev_get_drvdata(&amp;adev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -2261,7 +2303,7 @@ static void __exit etm4_remove_amba(struct amba_device *adev)</div><div class='ctx'> 		etm4_remove_dev(drvdata);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit etm4_remove_platform_dev(struct platform_device *pdev)</div><div class='add'>+static void etm4_remove_platform_dev(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct etmv4_drvdata *drvdata = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -2271,8 +2313,6 @@ static int __exit etm4_remove_platform_dev(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	if (drvdata &amp;&amp; !IS_ERR_OR_NULL(drvdata-&gt;pclk))</div><div class='ctx'> 		clk_put(drvdata-&gt;pclk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct amba_id etm4_ids[] = {</div><div class='hunk'>@@ -2358,7 +2398,7 @@ MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver etm4_platform_driver = {</div><div class='ctx'> 	.probe		= etm4_probe_platform_dev,</div><div class='del'>-	.remove		= etm4_remove_platform_dev,</div><div class='add'>+	.remove_new	= etm4_remove_platform_dev,</div><div class='ctx'> 	.driver			= {</div><div class='ctx'> 		.name			= "coresight-etm4x",</div><div class='ctx'> 		.of_match_table		= etm4_sysreg_match,</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h<br/>index 20e2e4cb7614..da17b6c49b0f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm4x.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-etm4x.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-etm4x.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-etm4x.h</a></div><div class='hunk'>@@ -1036,7 +1036,7 @@ struct etmv4_drvdata {</div><div class='ctx'> 	u8				ctxid_size;</div><div class='ctx'> 	u8				vmid_size;</div><div class='ctx'> 	u8				ccsize;</div><div class='del'>-	u8				ccitmin;</div><div class='add'>+	u16				ccitmin;</div><div class='ctx'> 	u8				s_ex_level;</div><div class='ctx'> 	u8				ns_ex_level;</div><div class='ctx'> 	u8				q_support;</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c<br/>index b8e150e45b27..a5b1fc787766 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-funnel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-funnel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-funnel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-funnel.c</a></div><div class='hunk'>@@ -335,11 +335,10 @@ static int static_funnel_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int static_funnel_remove(struct platform_device *pdev)</div><div class='add'>+static void static_funnel_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	funnel_remove(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id static_funnel_match[] = {</div><div class='hunk'>@@ -360,7 +359,7 @@ MODULE_DEVICE_TABLE(acpi, static_funnel_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver static_funnel_driver = {</div><div class='ctx'> 	.probe          = static_funnel_probe,</div><div class='del'>-	.remove          = static_funnel_remove,</div><div class='add'>+	.remove_new      = static_funnel_remove,</div><div class='ctx'> 	.driver         = {</div><div class='ctx'> 		.name   = "coresight-static-funnel",</div><div class='ctx'> 		/* THIS_MODULE is taken care of by platform_driver_register() */</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c<br/>index b6be73034996..91d93060dda5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-replicator.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-replicator.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-replicator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-replicator.c</a></div><div class='hunk'>@@ -320,11 +320,10 @@ static int static_replicator_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int static_replicator_remove(struct platform_device *pdev)</div><div class='add'>+static void static_replicator_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	replicator_remove(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM</div><div class='hunk'>@@ -373,7 +372,7 @@ MODULE_DEVICE_TABLE(acpi, static_replicator_acpi_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver static_replicator_driver = {</div><div class='ctx'> 	.probe          = static_replicator_probe,</div><div class='del'>-	.remove         = static_replicator_remove,</div><div class='add'>+	.remove_new     = static_replicator_remove,</div><div class='ctx'> 	.driver         = {</div><div class='ctx'> 		.name   = "coresight-static-replicator",</div><div class='ctx'> 		/* THIS_MODULE is taken care of by platform_driver_register() */</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c<br/>index c106d142e632..7ec5365e2b64 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tmc-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc-core.c</a></div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/idr.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/iommu.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/fs.h&gt;</div><div class='ctx'> #include &lt;linux/miscdevice.h&gt;</div><div class='hunk'>@@ -344,7 +345,14 @@ static const struct attribute_group coresight_tmc_mgmt_group = {</div><div class='ctx'> 	.name = "mgmt",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct attribute_group *coresight_tmc_groups[] = {</div><div class='add'>+static const struct attribute_group *coresight_etf_groups[] = {</div><div class='add'>+	&amp;coresight_tmc_group,</div><div class='add'>+	&amp;coresight_tmc_mgmt_group,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute_group *coresight_etr_groups[] = {</div><div class='add'>+	&amp;coresight_etr_group,</div><div class='ctx'> 	&amp;coresight_tmc_group,</div><div class='ctx'> 	&amp;coresight_tmc_mgmt_group,</div><div class='ctx'> 	NULL,</div><div class='hunk'>@@ -465,6 +473,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> 	drvdata-&gt;memwidth = tmc_get_memwidth(devid);</div><div class='ctx'> 	/* This device is not associated with a session */</div><div class='ctx'> 	drvdata-&gt;pid = -1;</div><div class='add'>+	drvdata-&gt;etr_mode = ETR_MODE_AUTO;</div><div class='ctx'> </div><div class='ctx'> 	if (drvdata-&gt;config_type == TMC_CONFIG_TYPE_ETR) {</div><div class='ctx'> 		drvdata-&gt;size = tmc_etr_get_default_buffer_size(dev);</div><div class='hunk'>@@ -474,16 +483,17 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	desc.dev = dev;</div><div class='del'>-	desc.groups = coresight_tmc_groups;</div><div class='ctx'> </div><div class='ctx'> 	switch (drvdata-&gt;config_type) {</div><div class='ctx'> 	case TMC_CONFIG_TYPE_ETB:</div><div class='add'>+		desc.groups = coresight_etf_groups;</div><div class='ctx'> 		desc.type = CORESIGHT_DEV_TYPE_SINK;</div><div class='ctx'> 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;</div><div class='ctx'> 		desc.ops = &amp;tmc_etb_cs_ops;</div><div class='ctx'> 		dev_list = &amp;etb_devs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TMC_CONFIG_TYPE_ETR:</div><div class='add'>+		desc.groups = coresight_etr_groups;</div><div class='ctx'> 		desc.type = CORESIGHT_DEV_TYPE_SINK;</div><div class='ctx'> 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM;</div><div class='ctx'> 		desc.ops = &amp;tmc_etr_cs_ops;</div><div class='hunk'>@@ -496,6 +506,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> 		dev_list = &amp;etr_devs;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TMC_CONFIG_TYPE_ETF:</div><div class='add'>+		desc.groups = coresight_etf_groups;</div><div class='ctx'> 		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;</div><div class='ctx'> 		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;</div><div class='ctx'> 		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c<br/>index 8311e1028ddb..af02ba5d5f15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc-etr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tmc-etr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc-etr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc-etr.c</a></div><div class='hunk'>@@ -26,6 +26,12 @@ struct etr_flat_buf {</div><div class='ctx'> 	size_t		size;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct etr_buf_hw {</div><div class='add'>+	bool	has_iommu;</div><div class='add'>+	bool	has_etr_sg;</div><div class='add'>+	bool	has_catu;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * etr_perf_buffer - Perf buffer used for ETR</div><div class='ctx'>  * @drvdata		- The ETR drvdaga this buffer has been allocated for.</div><div class='hunk'>@@ -830,6 +836,22 @@ static inline int tmc_etr_mode_alloc_buf(int mode,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw)</div><div class='add'>+{</div><div class='add'>+	struct tmc_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	buf_hw-&gt;has_iommu = iommu_get_domain_for_dev(dev-&gt;parent);</div><div class='add'>+	buf_hw-&gt;has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);</div><div class='add'>+	buf_hw-&gt;has_catu = !!tmc_etr_get_catu_device(drvdata);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size)</div><div class='add'>+{</div><div class='add'>+	bool has_sg = buf_hw-&gt;has_catu || buf_hw-&gt;has_etr_sg;</div><div class='add'>+</div><div class='add'>+	return !has_sg || buf_hw-&gt;has_iommu || etr_buf_size &lt; SZ_1M;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * tmc_alloc_etr_buf: Allocate a buffer use by ETR.</div><div class='ctx'>  * @drvdata	: ETR device details.</div><div class='hunk'>@@ -843,23 +865,22 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,</div><div class='ctx'> 					 int node, void **pages)</div><div class='ctx'> {</div><div class='ctx'> 	int rc = -ENOMEM;</div><div class='del'>-	bool has_etr_sg, has_iommu;</div><div class='del'>-	bool has_sg, has_catu;</div><div class='ctx'> 	struct etr_buf *etr_buf;</div><div class='add'>+	struct etr_buf_hw buf_hw;</div><div class='ctx'> 	struct device *dev = &amp;drvdata-&gt;csdev-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);</div><div class='del'>-	has_iommu = iommu_get_domain_for_dev(dev-&gt;parent);</div><div class='del'>-	has_catu = !!tmc_etr_get_catu_device(drvdata);</div><div class='del'>-</div><div class='del'>-	has_sg = has_catu || has_etr_sg;</div><div class='del'>-</div><div class='add'>+	get_etr_buf_hw(dev, &amp;buf_hw);</div><div class='ctx'> 	etr_buf = kzalloc(sizeof(*etr_buf), GFP_KERNEL);</div><div class='ctx'> 	if (!etr_buf)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='ctx'> 	etr_buf-&gt;size = size;</div><div class='ctx'> </div><div class='add'>+	/* If there is user directive for buffer mode, try that first */</div><div class='add'>+	if (drvdata-&gt;etr_mode != ETR_MODE_AUTO)</div><div class='add'>+		rc = tmc_etr_mode_alloc_buf(drvdata-&gt;etr_mode, drvdata,</div><div class='add'>+					    etr_buf, node, pages);</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we have to use an existing list of pages, we cannot reliably</div><div class='ctx'> 	 * use a contiguous DMA memory (even if we have an IOMMU). Otherwise,</div><div class='hunk'>@@ -872,14 +893,13 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,</div><div class='ctx'> 	 * Fallback to available mechanisms.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 */</div><div class='del'>-	if (!pages &amp;&amp;</div><div class='del'>-	    (!has_sg || has_iommu || size &lt; SZ_1M))</div><div class='add'>+	if (rc &amp;&amp; !pages &amp;&amp; etr_can_use_flat_mode(&amp;buf_hw, size))</div><div class='ctx'> 		rc = tmc_etr_mode_alloc_buf(ETR_MODE_FLAT, drvdata,</div><div class='ctx'> 					    etr_buf, node, pages);</div><div class='del'>-	if (rc &amp;&amp; has_etr_sg)</div><div class='add'>+	if (rc &amp;&amp; buf_hw.has_etr_sg)</div><div class='ctx'> 		rc = tmc_etr_mode_alloc_buf(ETR_MODE_ETR_SG, drvdata,</div><div class='ctx'> 					    etr_buf, node, pages);</div><div class='del'>-	if (rc &amp;&amp; has_catu)</div><div class='add'>+	if (rc &amp;&amp; buf_hw.has_catu)</div><div class='ctx'> 		rc = tmc_etr_mode_alloc_buf(ETR_MODE_CATU, drvdata,</div><div class='ctx'> 					    etr_buf, node, pages);</div><div class='ctx'> 	if (rc) {</div><div class='hunk'>@@ -1804,3 +1824,70 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static const char *const buf_modes_str[] = {</div><div class='add'>+	[ETR_MODE_FLAT]		= "flat",</div><div class='add'>+	[ETR_MODE_ETR_SG]	= "tmc-sg",</div><div class='add'>+	[ETR_MODE_CATU]		= "catu",</div><div class='add'>+	[ETR_MODE_AUTO]		= "auto",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static ssize_t buf_modes_available_show(struct device *dev,</div><div class='add'>+					    struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct etr_buf_hw buf_hw;</div><div class='add'>+	ssize_t size = 0;</div><div class='add'>+</div><div class='add'>+	get_etr_buf_hw(dev, &amp;buf_hw);</div><div class='add'>+	size += sysfs_emit(buf, "%s ", buf_modes_str[ETR_MODE_AUTO]);</div><div class='add'>+	size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_FLAT]);</div><div class='add'>+	if (buf_hw.has_etr_sg)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_ETR_SG]);</div><div class='add'>+</div><div class='add'>+	if (buf_hw.has_catu)</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]);</div><div class='add'>+</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RO(buf_modes_available);</div><div class='add'>+</div><div class='add'>+static ssize_t buf_mode_preferred_show(struct device *dev,</div><div class='add'>+					 struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tmc_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%s\n", buf_modes_str[drvdata-&gt;etr_mode]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t buf_mode_preferred_store(struct device *dev,</div><div class='add'>+					  struct device_attribute *attr,</div><div class='add'>+					  const char *buf, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tmc_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	struct etr_buf_hw buf_hw;</div><div class='add'>+</div><div class='add'>+	get_etr_buf_hw(dev, &amp;buf_hw);</div><div class='add'>+	if (sysfs_streq(buf, buf_modes_str[ETR_MODE_FLAT]))</div><div class='add'>+		drvdata-&gt;etr_mode = ETR_MODE_FLAT;</div><div class='add'>+	else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_ETR_SG]) &amp;&amp; buf_hw.has_etr_sg)</div><div class='add'>+		drvdata-&gt;etr_mode = ETR_MODE_ETR_SG;</div><div class='add'>+	else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) &amp;&amp; buf_hw.has_catu)</div><div class='add'>+		drvdata-&gt;etr_mode = ETR_MODE_CATU;</div><div class='add'>+	else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO]))</div><div class='add'>+		drvdata-&gt;etr_mode = ETR_MODE_AUTO;</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(buf_mode_preferred);</div><div class='add'>+</div><div class='add'>+static struct attribute *coresight_etr_attrs[] = {</div><div class='add'>+	&amp;dev_attr_buf_modes_available.attr,</div><div class='add'>+	&amp;dev_attr_buf_mode_preferred.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct attribute_group coresight_etr_group = {</div><div class='add'>+	.attrs = coresight_etr_attrs,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h<br/>index 0ee48c5ba764..8dcb426ac3e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tmc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tmc.h</a></div><div class='hunk'>@@ -135,6 +135,7 @@ enum etr_mode {</div><div class='ctx'> 	ETR_MODE_FLAT,		/* Uses contiguous flat buffer */</div><div class='ctx'> 	ETR_MODE_ETR_SG,	/* Uses in-built TMC ETR SG mechanism */</div><div class='ctx'> 	ETR_MODE_CATU,		/* Use SG mechanism in CATU */</div><div class='add'>+	ETR_MODE_AUTO,		/* Use the default mechanism */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct etr_buf_operations;</div><div class='hunk'>@@ -207,6 +208,7 @@ struct tmc_drvdata {</div><div class='ctx'> 	enum tmc_mem_intf_width	memwidth;</div><div class='ctx'> 	u32			trigger_cntr;</div><div class='ctx'> 	u32			etr_caps;</div><div class='add'>+	enum etr_mode		etr_mode;</div><div class='ctx'> 	struct idr		idr;</div><div class='ctx'> 	struct mutex		idr_mutex;</div><div class='ctx'> 	struct etr_buf		*sysfs_buf;</div><div class='hunk'>@@ -334,5 +336,6 @@ void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);</div><div class='ctx'> void tmc_etr_remove_catu_ops(void);</div><div class='ctx'> struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,</div><div class='ctx'> 				   enum cs_mode mode, void *data);</div><div class='add'>+extern const struct attribute_group coresight_etr_group;</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c<br/>index 8d2b9d29237d..5f82737c37bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpda.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tpda.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpda.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpda.c</a></div><div class='hunk'>@@ -21,6 +21,80 @@</div><div class='ctx'> </div><div class='ctx'> DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");</div><div class='ctx'> </div><div class='add'>+static bool coresight_device_is_tpdm(struct coresight_device *csdev)</div><div class='add'>+{</div><div class='add'>+	return (csdev-&gt;type == CORESIGHT_DEV_TYPE_SOURCE) &amp;&amp;</div><div class='add'>+	       (csdev-&gt;subtype.source_subtype ==</div><div class='add'>+			CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Read the DSB element size from the TPDM device</div><div class='add'>+ * Returns</div><div class='add'>+ *    The dsb element size read from the devicetree if available.</div><div class='add'>+ *    0 - Otherwise, with a warning once.</div><div class='add'>+ */</div><div class='add'>+static int tpdm_read_dsb_element_size(struct coresight_device *csdev)</div><div class='add'>+{</div><div class='add'>+	int rc = 0;</div><div class='add'>+	u8 size = 0;</div><div class='add'>+</div><div class='add'>+	rc = fwnode_property_read_u8(dev_fwnode(csdev-&gt;dev.parent),</div><div class='add'>+			"qcom,dsb-element-size", &amp;size);</div><div class='add'>+	if (rc)</div><div class='add'>+		dev_warn_once(&amp;csdev-&gt;dev,</div><div class='add'>+			"Failed to read TPDM DSB Element size: %d\n", rc);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Search and read element data size from the TPDM node in</div><div class='add'>+ * the devicetree. Each input port of TPDA is connected to</div><div class='add'>+ * a TPDM. Different TPDM supports different types of dataset,</div><div class='add'>+ * and some may support more than one type of dataset.</div><div class='add'>+ * Parameter "inport" is used to pass in the input port number</div><div class='add'>+ * of TPDA, and it is set to -1 in the recursize call.</div><div class='add'>+ */</div><div class='add'>+static int tpda_get_element_size(struct coresight_device *csdev,</div><div class='add'>+				 int inport)</div><div class='add'>+{</div><div class='add'>+	int dsb_size = -ENOENT;</div><div class='add'>+	int i, size;</div><div class='add'>+	struct coresight_device *in;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; csdev-&gt;pdata-&gt;nr_inconns; i++) {</div><div class='add'>+		in = csdev-&gt;pdata-&gt;in_conns[i]-&gt;src_dev;</div><div class='add'>+		if (!in)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Ignore the paths that do not match port */</div><div class='add'>+		if (inport &gt; 0 &amp;&amp;</div><div class='add'>+		    csdev-&gt;pdata-&gt;in_conns[i]-&gt;dest_port != inport)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (coresight_device_is_tpdm(in)) {</div><div class='add'>+			size = tpdm_read_dsb_element_size(in);</div><div class='add'>+		} else {</div><div class='add'>+			/* Recurse down the path */</div><div class='add'>+			size = tpda_get_element_size(in, -1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (size &lt; 0)</div><div class='add'>+			return size;</div><div class='add'>+</div><div class='add'>+		if (dsb_size &lt; 0) {</div><div class='add'>+			/* Found a size, save it. */</div><div class='add'>+			dsb_size = size;</div><div class='add'>+		} else {</div><div class='add'>+			/* Found duplicate TPDMs */</div><div class='add'>+			return -EEXIST;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dsb_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Settings pre enabling port control register */</div><div class='ctx'> static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)</div><div class='ctx'> {</div><div class='hunk'>@@ -32,26 +106,55 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)</div><div class='ctx'> 	writel_relaxed(val, drvdata-&gt;base + TPDA_CR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)</div><div class='add'>+static int tpda_enable_port(struct tpda_drvdata *drvdata, int port)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val;</div><div class='add'>+	int size;</div><div class='ctx'> </div><div class='ctx'> 	val = readl_relaxed(drvdata-&gt;base + TPDA_Pn_CR(port));</div><div class='add'>+	/*</div><div class='add'>+	 * Configure aggregator port n DSB data set element size</div><div class='add'>+	 * Set the bit to 0 if the size is 32</div><div class='add'>+	 * Set the bit to 1 if the size is 64</div><div class='add'>+	 */</div><div class='add'>+	size = tpda_get_element_size(drvdata-&gt;csdev, port);</div><div class='add'>+	switch (size) {</div><div class='add'>+	case 32:</div><div class='add'>+		val &amp;= ~TPDA_Pn_CR_DSBSIZE;</div><div class='add'>+		break;</div><div class='add'>+	case 64:</div><div class='add'>+		val |= TPDA_Pn_CR_DSBSIZE;</div><div class='add'>+		break;</div><div class='add'>+	case 0:</div><div class='add'>+		return -EEXIST;</div><div class='add'>+	case -EEXIST:</div><div class='add'>+		dev_warn_once(&amp;drvdata-&gt;csdev-&gt;dev,</div><div class='add'>+			"Detected multiple TPDMs on port %d", -EEXIST);</div><div class='add'>+		return -EEXIST;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Enable the port */</div><div class='ctx'> 	val |= TPDA_Pn_CR_ENA;</div><div class='ctx'> 	writel_relaxed(val, drvdata-&gt;base + TPDA_Pn_CR(port));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __tpda_enable(struct tpda_drvdata *drvdata, int port)</div><div class='add'>+static int __tpda_enable(struct tpda_drvdata *drvdata, int port)</div><div class='ctx'> {</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='ctx'> 	CS_UNLOCK(drvdata-&gt;base);</div><div class='ctx'> </div><div class='ctx'> 	if (!drvdata-&gt;csdev-&gt;enable)</div><div class='ctx'> 		tpda_enable_pre_port(drvdata);</div><div class='ctx'> </div><div class='del'>-	tpda_enable_port(drvdata, port);</div><div class='del'>-</div><div class='add'>+	ret = tpda_enable_port(drvdata, port);</div><div class='ctx'> 	CS_LOCK(drvdata-&gt;base);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int tpda_enable(struct coresight_device *csdev,</div><div class='hunk'>@@ -59,16 +162,19 @@ static int tpda_enable(struct coresight_device *csdev,</div><div class='ctx'> 		       struct coresight_connection *out)</div><div class='ctx'> {</div><div class='ctx'> 	struct tpda_drvdata *drvdata = dev_get_drvdata(csdev-&gt;dev.parent);</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='del'>-	if (atomic_read(&amp;in-&gt;dest_refcnt) == 0)</div><div class='del'>-		__tpda_enable(drvdata, in-&gt;dest_port);</div><div class='add'>+	if (atomic_read(&amp;in-&gt;dest_refcnt) == 0) {</div><div class='add'>+		ret = __tpda_enable(drvdata, in-&gt;dest_port);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			atomic_inc(&amp;in-&gt;dest_refcnt);</div><div class='add'>+			dev_dbg(drvdata-&gt;dev, "TPDA inport %d enabled.\n", in-&gt;dest_port);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	atomic_inc(&amp;in-&gt;dest_refcnt);</div><div class='ctx'> 	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='del'>-</div><div class='del'>-	dev_dbg(drvdata-&gt;dev, "TPDA inport %d enabled.\n", in-&gt;dest_port);</div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __tpda_disable(struct tpda_drvdata *drvdata, int port)</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h<br/>index 0399678df312..b3b38fd41b64 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpda.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tpda.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpda.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpda.h</a></div><div class='hunk'>@@ -10,6 +10,8 @@</div><div class='ctx'> #define TPDA_Pn_CR(n)		(0x004 + (n * 4))</div><div class='ctx'> /* Aggregator port enable bit */</div><div class='ctx'> #define TPDA_Pn_CR_ENA		BIT(0)</div><div class='add'>+/* Aggregator port DSB data set element size bit */</div><div class='add'>+#define TPDA_Pn_CR_DSBSIZE		BIT(8)</div><div class='ctx'> </div><div class='ctx'> #define TPDA_MAX_INPORTS	32</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c<br/>index f4854af0431e..97654aa4b772 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpdm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tpdm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpdm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpdm.c</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/amba/bus.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/bitmap.h&gt;</div><div class='ctx'> #include &lt;linux/coresight.h&gt;</div><div class='ctx'> #include &lt;linux/coresight-pmu.h&gt;</div><div class='hunk'>@@ -20,23 +21,265 @@</div><div class='ctx'> </div><div class='ctx'> DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");</div><div class='ctx'> </div><div class='del'>-static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)</div><div class='add'>+/* Read dataset array member with the index number */</div><div class='add'>+static ssize_t tpdm_simple_dataset_show(struct device *dev,</div><div class='add'>+					struct device_attribute *attr,</div><div class='add'>+					char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	struct tpdm_dataset_attribute *tpdm_attr =</div><div class='add'>+		container_of(attr, struct tpdm_dataset_attribute, attr);</div><div class='add'>+</div><div class='add'>+	switch (tpdm_attr-&gt;mem) {</div><div class='add'>+	case DSB_EDGE_CTRL:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_EDCR)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;edge_ctrl[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_EDGE_CTRL_MASK:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_EDCMR)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;edge_ctrl_mask[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_TRIG_PATT:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_PATT)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;trig_patt[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_TRIG_PATT_MASK:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_PATT)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;trig_patt_mask[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_PATT:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_PATT)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;patt_val[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_PATT_MASK:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= TPDM_DSB_MAX_PATT)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+			drvdata-&gt;dsb-&gt;patt_mask[tpdm_attr-&gt;idx]);</div><div class='add'>+	case DSB_MSR:</div><div class='add'>+		if (tpdm_attr-&gt;idx &gt;= drvdata-&gt;dsb_msr_num)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		return sysfs_emit(buf, "0x%x\n",</div><div class='add'>+				drvdata-&gt;dsb-&gt;msr[tpdm_attr-&gt;idx]);</div><div class='add'>+	}</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Write dataset array member with the index number */</div><div class='add'>+static ssize_t tpdm_simple_dataset_store(struct device *dev,</div><div class='add'>+					 struct device_attribute *attr,</div><div class='add'>+					 const char *buf,</div><div class='add'>+					 size_t size)</div><div class='add'>+{</div><div class='add'>+	unsigned long val;</div><div class='add'>+	ssize_t ret = size;</div><div class='add'>+</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	struct tpdm_dataset_attribute *tpdm_attr =</div><div class='add'>+		container_of(attr, struct tpdm_dataset_attribute, attr);</div><div class='add'>+</div><div class='add'>+	if (kstrtoul(buf, 0, &amp;val))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	switch (tpdm_attr-&gt;mem) {</div><div class='add'>+	case DSB_TRIG_PATT:</div><div class='add'>+		if (tpdm_attr-&gt;idx &lt; TPDM_DSB_MAX_PATT)</div><div class='add'>+			drvdata-&gt;dsb-&gt;trig_patt[tpdm_attr-&gt;idx] = val;</div><div class='add'>+		else</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	case DSB_TRIG_PATT_MASK:</div><div class='add'>+		if (tpdm_attr-&gt;idx &lt; TPDM_DSB_MAX_PATT)</div><div class='add'>+			drvdata-&gt;dsb-&gt;trig_patt_mask[tpdm_attr-&gt;idx] = val;</div><div class='add'>+		else</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	case DSB_PATT:</div><div class='add'>+		if (tpdm_attr-&gt;idx &lt; TPDM_DSB_MAX_PATT)</div><div class='add'>+			drvdata-&gt;dsb-&gt;patt_val[tpdm_attr-&gt;idx] = val;</div><div class='add'>+		else</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	case DSB_PATT_MASK:</div><div class='add'>+		if (tpdm_attr-&gt;idx &lt; TPDM_DSB_MAX_PATT)</div><div class='add'>+			drvdata-&gt;dsb-&gt;patt_mask[tpdm_attr-&gt;idx] = val;</div><div class='add'>+		else</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	case DSB_MSR:</div><div class='add'>+		if (tpdm_attr-&gt;idx &lt; drvdata-&gt;dsb_msr_num)</div><div class='add'>+			drvdata-&gt;dsb-&gt;msr[tpdm_attr-&gt;idx] = val;</div><div class='add'>+		else</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)</div><div class='add'>+{</div><div class='add'>+	return (drvdata-&gt;datasets &amp; TPDM_PIDR0_DS_DSB);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t tpdm_dsb_is_visible(struct kobject *kobj,</div><div class='add'>+				   struct attribute *attr, int n)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	if (drvdata &amp;&amp; tpdm_has_dsb_dataset(drvdata))</div><div class='add'>+		return attr-&gt;mode;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj,</div><div class='add'>+				       struct attribute *attr, int n)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = kobj_to_dev(kobj);</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	struct device_attribute *dev_attr =</div><div class='add'>+		container_of(attr, struct device_attribute, attr);</div><div class='add'>+	struct tpdm_dataset_attribute *tpdm_attr =</div><div class='add'>+		container_of(dev_attr, struct tpdm_dataset_attribute, attr);</div><div class='add'>+</div><div class='add'>+	if (tpdm_attr-&gt;idx &lt; drvdata-&gt;dsb_msr_num)</div><div class='add'>+		return attr-&gt;mode;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)</div><div class='add'>+{</div><div class='add'>+	if (tpdm_has_dsb_dataset(drvdata)) {</div><div class='add'>+		memset(drvdata-&gt;dsb, 0, sizeof(struct dsb_dataset));</div><div class='add'>+</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_ts = true;</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_type = false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val)</div><div class='add'>+{</div><div class='add'>+	u32 mode;</div><div class='add'>+</div><div class='add'>+	/* Set the test accurate mode */</div><div class='add'>+	mode = TPDM_DSB_MODE_TEST(drvdata-&gt;dsb-&gt;mode);</div><div class='add'>+	*val &amp;= ~TPDM_DSB_CR_TEST_MODE;</div><div class='add'>+	*val |= FIELD_PREP(TPDM_DSB_CR_TEST_MODE, mode);</div><div class='add'>+</div><div class='add'>+	/* Set the byte lane for high-performance mode */</div><div class='add'>+	mode = TPDM_DSB_MODE_HPBYTESEL(drvdata-&gt;dsb-&gt;mode);</div><div class='add'>+	*val &amp;= ~TPDM_DSB_CR_HPSEL;</div><div class='add'>+	*val |= FIELD_PREP(TPDM_DSB_CR_HPSEL, mode);</div><div class='add'>+</div><div class='add'>+	/* Set the performance mode */</div><div class='add'>+	if (drvdata-&gt;dsb-&gt;mode &amp; TPDM_DSB_MODE_PERF)</div><div class='add'>+		*val |= TPDM_DSB_CR_MODE;</div><div class='add'>+	else</div><div class='add'>+		*val &amp;= ~TPDM_DSB_CR_MODE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_dsb_tier(struct tpdm_drvdata *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	/* Set the enable bit of DSB control register to 1 */</div><div class='add'>+	val = readl_relaxed(drvdata-&gt;base + TPDM_DSB_TIER);</div><div class='add'>+</div><div class='add'>+	/* Clear all relevant fields */</div><div class='add'>+	val &amp;= ~(TPDM_DSB_TIER_PATT_TSENAB | TPDM_DSB_TIER_PATT_TYPE |</div><div class='add'>+		 TPDM_DSB_TIER_XTRIG_TSENAB);</div><div class='add'>+</div><div class='add'>+	/* Set pattern timestamp type and enablement */</div><div class='add'>+	if (drvdata-&gt;dsb-&gt;patt_ts) {</div><div class='add'>+		val |= TPDM_DSB_TIER_PATT_TSENAB;</div><div class='add'>+		if (drvdata-&gt;dsb-&gt;patt_type)</div><div class='add'>+			val |= TPDM_DSB_TIER_PATT_TYPE;</div><div class='add'>+		else</div><div class='add'>+			val &amp;= ~TPDM_DSB_TIER_PATT_TYPE;</div><div class='add'>+	} else {</div><div class='add'>+		val &amp;= ~TPDM_DSB_TIER_PATT_TSENAB;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set trigger timestamp */</div><div class='add'>+	if (drvdata-&gt;dsb-&gt;trig_ts)</div><div class='add'>+		val |= TPDM_DSB_TIER_XTRIG_TSENAB;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~TPDM_DSB_TIER_XTRIG_TSENAB;</div><div class='add'>+</div><div class='add'>+	writel_relaxed(val, drvdata-&gt;base + TPDM_DSB_TIER);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void set_dsb_msr(struct tpdm_drvdata *drvdata)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; drvdata-&gt;dsb_msr_num; i++)</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;msr[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_MSR(i));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)</div><div class='add'>+{</div><div class='add'>+	u32 val, i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; TPDM_DSB_MAX_EDCR; i++)</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;edge_ctrl[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_EDCR(i));</div><div class='add'>+	for (i = 0; i &lt; TPDM_DSB_MAX_EDCMR; i++)</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;edge_ctrl_mask[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_EDCMR(i));</div><div class='add'>+	for (i = 0; i &lt; TPDM_DSB_MAX_PATT; i++) {</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;patt_val[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_TPR(i));</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;patt_mask[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_TPMR(i));</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;trig_patt[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_XPR(i));</div><div class='add'>+		writel_relaxed(drvdata-&gt;dsb-&gt;trig_patt_mask[i],</div><div class='add'>+			   drvdata-&gt;base + TPDM_DSB_XPMR(i));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	set_dsb_tier(drvdata);</div><div class='add'>+</div><div class='add'>+	set_dsb_msr(drvdata);</div><div class='add'>+</div><div class='ctx'> 	val = readl_relaxed(drvdata-&gt;base + TPDM_DSB_CR);</div><div class='add'>+	/* Set the mode of DSB dataset */</div><div class='add'>+	set_dsb_mode(drvdata, &amp;val);</div><div class='add'>+	/* Set trigger type */</div><div class='add'>+	if (drvdata-&gt;dsb-&gt;trig_type)</div><div class='add'>+		val |= TPDM_DSB_CR_TRIG_TYPE;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~TPDM_DSB_CR_TRIG_TYPE;</div><div class='add'>+	/* Set the enable bit of DSB control register to 1 */</div><div class='ctx'> 	val |= TPDM_DSB_CR_ENA;</div><div class='ctx'> 	writel_relaxed(val, drvdata-&gt;base + TPDM_DSB_CR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* TPDM enable operations */</div><div class='add'>+/*</div><div class='add'>+ * TPDM enable operations</div><div class='add'>+ * The TPDM or Monitor serves as data collection component for various</div><div class='add'>+ * dataset types. It covers Basic Counts(BC), Tenure Counts(TC),</div><div class='add'>+ * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single</div><div class='add'>+ * Bit(DSB). This function will initialize the configuration according</div><div class='add'>+ * to the dataset type supported by the TPDM.</div><div class='add'>+ */</div><div class='ctx'> static void __tpdm_enable(struct tpdm_drvdata *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	CS_UNLOCK(drvdata-&gt;base);</div><div class='ctx'> </div><div class='del'>-	/* Check if DSB datasets is present for TPDM. */</div><div class='del'>-	if (drvdata-&gt;datasets &amp; TPDM_PIDR0_DS_DSB)</div><div class='add'>+	if (tpdm_has_dsb_dataset(drvdata))</div><div class='ctx'> 		tpdm_enable_dsb(drvdata);</div><div class='ctx'> </div><div class='ctx'> 	CS_LOCK(drvdata-&gt;base);</div><div class='hunk'>@@ -76,8 +319,7 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	CS_UNLOCK(drvdata-&gt;base);</div><div class='ctx'> </div><div class='del'>-	/* Check if DSB datasets is present for TPDM. */</div><div class='del'>-	if (drvdata-&gt;datasets &amp; TPDM_PIDR0_DS_DSB)</div><div class='add'>+	if (tpdm_has_dsb_dataset(drvdata))</div><div class='ctx'> 		tpdm_disable_dsb(drvdata);</div><div class='ctx'> </div><div class='ctx'> 	CS_LOCK(drvdata-&gt;base);</div><div class='hunk'>@@ -110,16 +352,45 @@ static const struct coresight_ops tpdm_cs_ops = {</div><div class='ctx'> 	.source_ops	= &amp;tpdm_source_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)</div><div class='add'>+static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	u32 pidr;</div><div class='ctx'> </div><div class='del'>-	CS_UNLOCK(drvdata-&gt;base);</div><div class='ctx'> 	/*  Get the datasets present on the TPDM. */</div><div class='ctx'> 	pidr = readl_relaxed(drvdata-&gt;base + CORESIGHT_PERIPHIDR0);</div><div class='ctx'> 	drvdata-&gt;datasets |= pidr &amp; GENMASK(TPDM_DATASETS - 1, 0);</div><div class='del'>-	CS_LOCK(drvdata-&gt;base);</div><div class='add'>+</div><div class='add'>+	if (tpdm_has_dsb_dataset(drvdata) &amp;&amp; (!drvdata-&gt;dsb)) {</div><div class='add'>+		drvdata-&gt;dsb = devm_kzalloc(drvdata-&gt;dev,</div><div class='add'>+						sizeof(*drvdata-&gt;dsb), GFP_KERNEL);</div><div class='add'>+		if (!drvdata-&gt;dsb)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	tpdm_reset_datasets(drvdata);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t reset_dataset_store(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr,</div><div class='add'>+				   const char *buf,</div><div class='add'>+				   size_t size)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	unsigned long val;</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	ret = kstrtoul(buf, 0, &amp;val);</div><div class='add'>+	if (ret || val != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	tpdm_reset_datasets(drvdata);</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='ctx'> }</div><div class='add'>+static DEVICE_ATTR_WO(reset_dataset);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * value 1: 64 bits test data</div><div class='hunk'>@@ -161,6 +432,7 @@ static ssize_t integration_test_store(struct device *dev,</div><div class='ctx'> static DEVICE_ATTR_WO(integration_test);</div><div class='ctx'> </div><div class='ctx'> static struct attribute *tpdm_attrs[] = {</div><div class='add'>+	&amp;dev_attr_reset_dataset.attr,</div><div class='ctx'> 	&amp;dev_attr_integration_test.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='hunk'>@@ -169,8 +441,421 @@ static struct attribute_group tpdm_attr_grp = {</div><div class='ctx'> 	.attrs = tpdm_attrs,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static ssize_t dsb_mode_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr,</div><div class='add'>+			     char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%x\n", drvdata-&gt;dsb-&gt;mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t dsb_mode_store(struct device *dev,</div><div class='add'>+			      struct device_attribute *attr,</div><div class='add'>+			      const char *buf,</div><div class='add'>+			      size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &lt; 0) ||</div><div class='add'>+			(val &amp; ~TPDM_DSB_MODE_MASK))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	drvdata-&gt;dsb-&gt;mode = val &amp; TPDM_DSB_MODE_MASK;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(dsb_mode);</div><div class='add'>+</div><div class='add'>+static ssize_t ctrl_idx_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr,</div><div class='add'>+			     char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			(unsigned int)drvdata-&gt;dsb-&gt;edge_ctrl_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The EDCR registers can include up to 16 32-bit registers, and each</div><div class='add'>+ * one can be configured to control up to 16 edge detections(2 bits</div><div class='add'>+ * control one edge detection). So a total 256 edge detections can be</div><div class='add'>+ * configured. This function provides a way to set the index number of</div><div class='add'>+ * the edge detection which needs to be configured.</div><div class='add'>+ */</div><div class='add'>+static ssize_t ctrl_idx_store(struct device *dev,</div><div class='add'>+			      struct device_attribute *attr,</div><div class='add'>+			      const char *buf,</div><div class='add'>+			      size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &gt;= TPDM_DSB_MAX_LINES))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	drvdata-&gt;dsb-&gt;edge_ctrl_idx = val;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(ctrl_idx);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This function is used to control the edge detection according</div><div class='add'>+ * to the index number that has been set.</div><div class='add'>+ * "edge_ctrl" should be one of the following values.</div><div class='add'>+ * 0 - Rising edge detection</div><div class='add'>+ * 1 - Falling edge detection</div><div class='add'>+ * 2 - Rising and falling edge detection (toggle detection)</div><div class='add'>+ */</div><div class='add'>+static ssize_t ctrl_val_store(struct device *dev,</div><div class='add'>+			      struct device_attribute *attr,</div><div class='add'>+			      const char *buf,</div><div class='add'>+			      size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val, edge_ctrl;</div><div class='add'>+	int reg;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;edge_ctrl)) || (edge_ctrl &gt; 0x2))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	/*</div><div class='add'>+	 * There are 2 bit per DSB Edge Control line.</div><div class='add'>+	 * Thus we have 16 lines in a 32bit word.</div><div class='add'>+	 */</div><div class='add'>+	reg = EDCR_TO_WORD_IDX(drvdata-&gt;dsb-&gt;edge_ctrl_idx);</div><div class='add'>+	val = drvdata-&gt;dsb-&gt;edge_ctrl[reg];</div><div class='add'>+	val &amp;= ~EDCR_TO_WORD_MASK(drvdata-&gt;dsb-&gt;edge_ctrl_idx);</div><div class='add'>+	val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata-&gt;dsb-&gt;edge_ctrl_idx);</div><div class='add'>+	drvdata-&gt;dsb-&gt;edge_ctrl[reg] = val;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_WO(ctrl_val);</div><div class='add'>+</div><div class='add'>+static ssize_t ctrl_mask_store(struct device *dev,</div><div class='add'>+			       struct device_attribute *attr,</div><div class='add'>+			       const char *buf,</div><div class='add'>+			       size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+	u32 set;</div><div class='add'>+	int reg;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &amp; ~1UL))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	/*</div><div class='add'>+	 * There is 1 bit per DSB Edge Control Mark line.</div><div class='add'>+	 * Thus we have 32 lines in a 32bit word.</div><div class='add'>+	 */</div><div class='add'>+	reg = EDCMR_TO_WORD_IDX(drvdata-&gt;dsb-&gt;edge_ctrl_idx);</div><div class='add'>+	set = drvdata-&gt;dsb-&gt;edge_ctrl_mask[reg];</div><div class='add'>+	if (val)</div><div class='add'>+		set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata-&gt;dsb-&gt;edge_ctrl_idx));</div><div class='add'>+	else</div><div class='add'>+		set &amp;= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata-&gt;dsb-&gt;edge_ctrl_idx));</div><div class='add'>+	drvdata-&gt;dsb-&gt;edge_ctrl_mask[reg] = set;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_WO(ctrl_mask);</div><div class='add'>+</div><div class='add'>+static ssize_t enable_ts_show(struct device *dev,</div><div class='add'>+			      struct device_attribute *attr,</div><div class='add'>+			      char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			 (unsigned int)drvdata-&gt;dsb-&gt;patt_ts);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * value 1: Enable/Disable DSB pattern timestamp</div><div class='add'>+ */</div><div class='add'>+static ssize_t enable_ts_store(struct device *dev,</div><div class='add'>+			       struct device_attribute *attr,</div><div class='add'>+			       const char *buf,</div><div class='add'>+			       size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &amp; ~1UL))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	drvdata-&gt;dsb-&gt;patt_ts = !!val;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(enable_ts);</div><div class='add'>+</div><div class='add'>+static ssize_t set_type_show(struct device *dev,</div><div class='add'>+			     struct device_attribute *attr,</div><div class='add'>+			     char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			 (unsigned int)drvdata-&gt;dsb-&gt;patt_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * value 1: Set DSB pattern type</div><div class='add'>+ */</div><div class='add'>+static ssize_t set_type_store(struct device *dev,</div><div class='add'>+			      struct device_attribute *attr,</div><div class='add'>+			      const char *buf, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &amp; ~1UL))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	drvdata-&gt;dsb-&gt;patt_type = val;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(set_type);</div><div class='add'>+</div><div class='add'>+static ssize_t dsb_trig_type_show(struct device *dev,</div><div class='add'>+				  struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			 (unsigned int)drvdata-&gt;dsb-&gt;trig_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Trigger type (boolean):</div><div class='add'>+ * false - Disable trigger type.</div><div class='add'>+ * true  - Enable trigger type.</div><div class='add'>+ */</div><div class='add'>+static ssize_t dsb_trig_type_store(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr,</div><div class='add'>+				   const char *buf,</div><div class='add'>+				   size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &amp; ~1UL))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	if (val)</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_type = true;</div><div class='add'>+	else</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_type = false;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(dsb_trig_type);</div><div class='add'>+</div><div class='add'>+static ssize_t dsb_trig_ts_show(struct device *dev,</div><div class='add'>+				struct device_attribute *attr,</div><div class='add'>+				char *buf)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			 (unsigned int)drvdata-&gt;dsb-&gt;trig_ts);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Trigger timestamp (boolean):</div><div class='add'>+ * false - Disable trigger timestamp.</div><div class='add'>+ * true  - Enable trigger timestamp.</div><div class='add'>+ */</div><div class='add'>+static ssize_t dsb_trig_ts_store(struct device *dev,</div><div class='add'>+				 struct device_attribute *attr,</div><div class='add'>+				 const char *buf,</div><div class='add'>+				 size_t size)</div><div class='add'>+{</div><div class='add'>+	struct tpdm_drvdata *drvdata = dev_get_drvdata(dev-&gt;parent);</div><div class='add'>+	unsigned long val;</div><div class='add'>+</div><div class='add'>+	if ((kstrtoul(buf, 0, &amp;val)) || (val &amp; ~1UL))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	if (val)</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_ts = true;</div><div class='add'>+	else</div><div class='add'>+		drvdata-&gt;dsb-&gt;trig_ts = false;</div><div class='add'>+	spin_unlock(&amp;drvdata-&gt;spinlock);</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+static DEVICE_ATTR_RW(dsb_trig_ts);</div><div class='add'>+</div><div class='add'>+static struct attribute *tpdm_dsb_edge_attrs[] = {</div><div class='add'>+	&amp;dev_attr_ctrl_idx.attr,</div><div class='add'>+	&amp;dev_attr_ctrl_val.attr,</div><div class='add'>+	&amp;dev_attr_ctrl_mask.attr,</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(0),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(1),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(2),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(3),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(4),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(5),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(6),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(7),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(8),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(9),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(10),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(11),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(12),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(13),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(14),</div><div class='add'>+	DSB_EDGE_CTRL_ATTR(15),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(0),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(1),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(2),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(3),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(4),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(5),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(6),</div><div class='add'>+	DSB_EDGE_CTRL_MASK_ATTR(7),</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute *tpdm_dsb_trig_patt_attrs[] = {</div><div class='add'>+	DSB_TRIG_PATT_ATTR(0),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(1),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(2),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(3),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(4),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(5),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(6),</div><div class='add'>+	DSB_TRIG_PATT_ATTR(7),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(0),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(1),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(2),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(3),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(4),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(5),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(6),</div><div class='add'>+	DSB_TRIG_PATT_MASK_ATTR(7),</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute *tpdm_dsb_patt_attrs[] = {</div><div class='add'>+	DSB_PATT_ATTR(0),</div><div class='add'>+	DSB_PATT_ATTR(1),</div><div class='add'>+	DSB_PATT_ATTR(2),</div><div class='add'>+	DSB_PATT_ATTR(3),</div><div class='add'>+	DSB_PATT_ATTR(4),</div><div class='add'>+	DSB_PATT_ATTR(5),</div><div class='add'>+	DSB_PATT_ATTR(6),</div><div class='add'>+	DSB_PATT_ATTR(7),</div><div class='add'>+	DSB_PATT_MASK_ATTR(0),</div><div class='add'>+	DSB_PATT_MASK_ATTR(1),</div><div class='add'>+	DSB_PATT_MASK_ATTR(2),</div><div class='add'>+	DSB_PATT_MASK_ATTR(3),</div><div class='add'>+	DSB_PATT_MASK_ATTR(4),</div><div class='add'>+	DSB_PATT_MASK_ATTR(5),</div><div class='add'>+	DSB_PATT_MASK_ATTR(6),</div><div class='add'>+	DSB_PATT_MASK_ATTR(7),</div><div class='add'>+	&amp;dev_attr_enable_ts.attr,</div><div class='add'>+	&amp;dev_attr_set_type.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute *tpdm_dsb_msr_attrs[] = {</div><div class='add'>+	DSB_MSR_ATTR(0),</div><div class='add'>+	DSB_MSR_ATTR(1),</div><div class='add'>+	DSB_MSR_ATTR(2),</div><div class='add'>+	DSB_MSR_ATTR(3),</div><div class='add'>+	DSB_MSR_ATTR(4),</div><div class='add'>+	DSB_MSR_ATTR(5),</div><div class='add'>+	DSB_MSR_ATTR(6),</div><div class='add'>+	DSB_MSR_ATTR(7),</div><div class='add'>+	DSB_MSR_ATTR(8),</div><div class='add'>+	DSB_MSR_ATTR(9),</div><div class='add'>+	DSB_MSR_ATTR(10),</div><div class='add'>+	DSB_MSR_ATTR(11),</div><div class='add'>+	DSB_MSR_ATTR(12),</div><div class='add'>+	DSB_MSR_ATTR(13),</div><div class='add'>+	DSB_MSR_ATTR(14),</div><div class='add'>+	DSB_MSR_ATTR(15),</div><div class='add'>+	DSB_MSR_ATTR(16),</div><div class='add'>+	DSB_MSR_ATTR(17),</div><div class='add'>+	DSB_MSR_ATTR(18),</div><div class='add'>+	DSB_MSR_ATTR(19),</div><div class='add'>+	DSB_MSR_ATTR(20),</div><div class='add'>+	DSB_MSR_ATTR(21),</div><div class='add'>+	DSB_MSR_ATTR(22),</div><div class='add'>+	DSB_MSR_ATTR(23),</div><div class='add'>+	DSB_MSR_ATTR(24),</div><div class='add'>+	DSB_MSR_ATTR(25),</div><div class='add'>+	DSB_MSR_ATTR(26),</div><div class='add'>+	DSB_MSR_ATTR(27),</div><div class='add'>+	DSB_MSR_ATTR(28),</div><div class='add'>+	DSB_MSR_ATTR(29),</div><div class='add'>+	DSB_MSR_ATTR(30),</div><div class='add'>+	DSB_MSR_ATTR(31),</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute *tpdm_dsb_attrs[] = {</div><div class='add'>+	&amp;dev_attr_dsb_mode.attr,</div><div class='add'>+	&amp;dev_attr_dsb_trig_ts.attr,</div><div class='add'>+	&amp;dev_attr_dsb_trig_type.attr,</div><div class='add'>+	NULL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute_group tpdm_dsb_attr_grp = {</div><div class='add'>+	.attrs = tpdm_dsb_attrs,</div><div class='add'>+	.is_visible = tpdm_dsb_is_visible,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute_group tpdm_dsb_edge_grp = {</div><div class='add'>+	.attrs = tpdm_dsb_edge_attrs,</div><div class='add'>+	.is_visible = tpdm_dsb_is_visible,</div><div class='add'>+	.name = "dsb_edge",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute_group tpdm_dsb_trig_patt_grp = {</div><div class='add'>+	.attrs = tpdm_dsb_trig_patt_attrs,</div><div class='add'>+	.is_visible = tpdm_dsb_is_visible,</div><div class='add'>+	.name = "dsb_trig_patt",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute_group tpdm_dsb_patt_grp = {</div><div class='add'>+	.attrs = tpdm_dsb_patt_attrs,</div><div class='add'>+	.is_visible = tpdm_dsb_is_visible,</div><div class='add'>+	.name = "dsb_patt",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct attribute_group tpdm_dsb_msr_grp = {</div><div class='add'>+	.attrs = tpdm_dsb_msr_attrs,</div><div class='add'>+	.is_visible = tpdm_dsb_msr_is_visible,</div><div class='add'>+	.name = "dsb_msr",</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct attribute_group *tpdm_attr_grps[] = {</div><div class='ctx'> 	&amp;tpdm_attr_grp,</div><div class='add'>+	&amp;tpdm_dsb_attr_grp,</div><div class='add'>+	&amp;tpdm_dsb_edge_grp,</div><div class='add'>+	&amp;tpdm_dsb_trig_patt_grp,</div><div class='add'>+	&amp;tpdm_dsb_patt_grp,</div><div class='add'>+	&amp;tpdm_dsb_msr_grp,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -181,6 +866,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> 	struct coresight_platform_data *pdata;</div><div class='ctx'> 	struct tpdm_drvdata *drvdata;</div><div class='ctx'> 	struct coresight_desc desc = { 0 };</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	pdata = coresight_get_platform_data(dev);</div><div class='ctx'> 	if (IS_ERR(pdata))</div><div class='hunk'>@@ -200,12 +886,20 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> </div><div class='ctx'> 	drvdata-&gt;base = base;</div><div class='ctx'> </div><div class='add'>+	ret = tpdm_datasets_setup(drvdata);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (drvdata &amp;&amp; tpdm_has_dsb_dataset(drvdata))</div><div class='add'>+		of_property_read_u32(drvdata-&gt;dev-&gt;of_node,</div><div class='add'>+			   "qcom,dsb-msrs-num", &amp;drvdata-&gt;dsb_msr_num);</div><div class='add'>+</div><div class='ctx'> 	/* Set up coresight component description */</div><div class='ctx'> 	desc.name = coresight_alloc_device_name(&amp;tpdm_devs, dev);</div><div class='ctx'> 	if (!desc.name)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	desc.type = CORESIGHT_DEV_TYPE_SOURCE;</div><div class='del'>-	desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS;</div><div class='add'>+	desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM;</div><div class='ctx'> 	desc.ops = &amp;tpdm_cs_ops;</div><div class='ctx'> 	desc.pdata = adev-&gt;dev.platform_data;</div><div class='ctx'> 	desc.dev = &amp;adev-&gt;dev;</div><div class='hunk'>@@ -216,7 +910,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)</div><div class='ctx'> 		return PTR_ERR(drvdata-&gt;csdev);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;drvdata-&gt;spinlock);</div><div class='del'>-	tpdm_init_default_data(drvdata);</div><div class='add'>+</div><div class='ctx'> 	/* Decrease pm refcount when probe is done.*/</div><div class='ctx'> 	pm_runtime_put(&amp;adev-&gt;dev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h<br/>index 543854043a2d..4115b2a17b8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpdm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-tpdm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-tpdm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-tpdm.h</a></div><div class='hunk'>@@ -11,8 +11,52 @@</div><div class='ctx'> </div><div class='ctx'> /* DSB Subunit Registers */</div><div class='ctx'> #define TPDM_DSB_CR		(0x780)</div><div class='add'>+#define TPDM_DSB_TIER		(0x784)</div><div class='add'>+#define TPDM_DSB_TPR(n)		(0x788 + (n * 4))</div><div class='add'>+#define TPDM_DSB_TPMR(n)	(0x7A8 + (n * 4))</div><div class='add'>+#define TPDM_DSB_XPR(n)		(0x7C8 + (n * 4))</div><div class='add'>+#define TPDM_DSB_XPMR(n)	(0x7E8 + (n * 4))</div><div class='add'>+#define TPDM_DSB_EDCR(n)	(0x808 + (n * 4))</div><div class='add'>+#define TPDM_DSB_EDCMR(n)	(0x848 + (n * 4))</div><div class='add'>+#define TPDM_DSB_MSR(n)		(0x980 + (n * 4))</div><div class='add'>+</div><div class='ctx'> /* Enable bit for DSB subunit */</div><div class='ctx'> #define TPDM_DSB_CR_ENA		BIT(0)</div><div class='add'>+/* Enable bit for DSB subunit perfmance mode */</div><div class='add'>+#define TPDM_DSB_CR_MODE		BIT(1)</div><div class='add'>+/* Enable bit for DSB subunit trigger type */</div><div class='add'>+#define TPDM_DSB_CR_TRIG_TYPE		BIT(12)</div><div class='add'>+/* Data bits for DSB high performace mode */</div><div class='add'>+#define TPDM_DSB_CR_HPSEL		GENMASK(6, 2)</div><div class='add'>+/* Data bits for DSB test mode */</div><div class='add'>+#define TPDM_DSB_CR_TEST_MODE		GENMASK(10, 9)</div><div class='add'>+</div><div class='add'>+/* Enable bit for DSB subunit pattern timestamp */</div><div class='add'>+#define TPDM_DSB_TIER_PATT_TSENAB		BIT(0)</div><div class='add'>+/* Enable bit for DSB subunit trigger timestamp */</div><div class='add'>+#define TPDM_DSB_TIER_XTRIG_TSENAB		BIT(1)</div><div class='add'>+/* Bit for DSB subunit pattern type */</div><div class='add'>+#define TPDM_DSB_TIER_PATT_TYPE			BIT(2)</div><div class='add'>+</div><div class='add'>+/* DSB programming modes */</div><div class='add'>+/* DSB mode bits mask */</div><div class='add'>+#define TPDM_DSB_MODE_MASK			GENMASK(8, 0)</div><div class='add'>+/* Test mode control bit*/</div><div class='add'>+#define TPDM_DSB_MODE_TEST(val)	(val &amp; GENMASK(1, 0))</div><div class='add'>+/* Performance mode */</div><div class='add'>+#define TPDM_DSB_MODE_PERF		BIT(3)</div><div class='add'>+/* High performance mode */</div><div class='add'>+#define TPDM_DSB_MODE_HPBYTESEL(val)	(val &amp; GENMASK(8, 4))</div><div class='add'>+</div><div class='add'>+#define EDCRS_PER_WORD			16</div><div class='add'>+#define EDCR_TO_WORD_IDX(r)		((r) / EDCRS_PER_WORD)</div><div class='add'>+#define EDCR_TO_WORD_SHIFT(r)		((r % EDCRS_PER_WORD) * 2)</div><div class='add'>+#define EDCR_TO_WORD_VAL(val, r)	(val &lt;&lt; EDCR_TO_WORD_SHIFT(r))</div><div class='add'>+#define EDCR_TO_WORD_MASK(r)		EDCR_TO_WORD_VAL(0x3, r)</div><div class='add'>+</div><div class='add'>+#define EDCMRS_PER_WORD				32</div><div class='add'>+#define EDCMR_TO_WORD_IDX(r)		((r) / EDCMRS_PER_WORD)</div><div class='add'>+#define EDCMR_TO_WORD_SHIFT(r)		((r) % EDCMRS_PER_WORD)</div><div class='ctx'> </div><div class='ctx'> /* TPDM integration test registers */</div><div class='ctx'> #define TPDM_ITATBCNTRL		(0xEF0)</div><div class='hunk'>@@ -40,6 +84,95 @@</div><div class='ctx'> #define TPDM_PIDR0_DS_IMPDEF	BIT(0)</div><div class='ctx'> #define TPDM_PIDR0_DS_DSB	BIT(1)</div><div class='ctx'> </div><div class='add'>+#define TPDM_DSB_MAX_LINES	256</div><div class='add'>+/* MAX number of EDCR registers */</div><div class='add'>+#define TPDM_DSB_MAX_EDCR	16</div><div class='add'>+/* MAX number of EDCMR registers */</div><div class='add'>+#define TPDM_DSB_MAX_EDCMR	8</div><div class='add'>+/* MAX number of DSB pattern */</div><div class='add'>+#define TPDM_DSB_MAX_PATT	8</div><div class='add'>+/* MAX number of DSB MSR */</div><div class='add'>+#define TPDM_DSB_MAX_MSR 32</div><div class='add'>+</div><div class='add'>+#define tpdm_simple_dataset_ro(name, mem, idx)			\</div><div class='add'>+	(&amp;((struct tpdm_dataset_attribute[]) {			\</div><div class='add'>+	   {								\</div><div class='add'>+		__ATTR(name, 0444, tpdm_simple_dataset_show, NULL),	\</div><div class='add'>+		mem,							\</div><div class='add'>+		idx,							\</div><div class='add'>+	   }								\</div><div class='add'>+	})[0].attr.attr)</div><div class='add'>+</div><div class='add'>+#define tpdm_simple_dataset_rw(name, mem, idx)			\</div><div class='add'>+	(&amp;((struct tpdm_dataset_attribute[]) {			\</div><div class='add'>+	   {								\</div><div class='add'>+		__ATTR(name, 0644, tpdm_simple_dataset_show,		\</div><div class='add'>+		tpdm_simple_dataset_store),		\</div><div class='add'>+		mem,							\</div><div class='add'>+		idx,							\</div><div class='add'>+	   }								\</div><div class='add'>+	})[0].attr.attr)</div><div class='add'>+</div><div class='add'>+#define DSB_EDGE_CTRL_ATTR(nr)					\</div><div class='add'>+		tpdm_simple_dataset_ro(edcr##nr,		\</div><div class='add'>+		DSB_EDGE_CTRL, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_EDGE_CTRL_MASK_ATTR(nr)				\</div><div class='add'>+		tpdm_simple_dataset_ro(edcmr##nr,		\</div><div class='add'>+		DSB_EDGE_CTRL_MASK, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_TRIG_PATT_ATTR(nr)					\</div><div class='add'>+		tpdm_simple_dataset_rw(xpr##nr,			\</div><div class='add'>+		DSB_TRIG_PATT, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_TRIG_PATT_MASK_ATTR(nr)				\</div><div class='add'>+		tpdm_simple_dataset_rw(xpmr##nr,		\</div><div class='add'>+		DSB_TRIG_PATT_MASK, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_PATT_ATTR(nr)					\</div><div class='add'>+		tpdm_simple_dataset_rw(tpr##nr,			\</div><div class='add'>+		DSB_PATT, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_PATT_MASK_ATTR(nr)					\</div><div class='add'>+		tpdm_simple_dataset_rw(tpmr##nr,		\</div><div class='add'>+		DSB_PATT_MASK, nr)</div><div class='add'>+</div><div class='add'>+#define DSB_MSR_ATTR(nr)					\</div><div class='add'>+		tpdm_simple_dataset_rw(msr##nr,			\</div><div class='add'>+		DSB_MSR, nr)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dsb_dataset - specifics associated to dsb dataset</div><div class='add'>+ * @mode:             DSB programming mode</div><div class='add'>+ * @edge_ctrl_idx     Index number of the edge control</div><div class='add'>+ * @edge_ctrl:        Save value for edge control</div><div class='add'>+ * @edge_ctrl_mask:   Save value for edge control mask</div><div class='add'>+ * @patt_val:         Save value for pattern</div><div class='add'>+ * @patt_mask:        Save value for pattern mask</div><div class='add'>+ * @trig_patt:        Save value for trigger pattern</div><div class='add'>+ * @trig_patt_mask:   Save value for trigger pattern mask</div><div class='add'>+ * @msr               Save value for MSR</div><div class='add'>+ * @patt_ts:          Enable/Disable pattern timestamp</div><div class='add'>+ * @patt_type:        Set pattern type</div><div class='add'>+ * @trig_ts:          Enable/Disable trigger timestamp.</div><div class='add'>+ * @trig_type:        Enable/Disable trigger type.</div><div class='add'>+ */</div><div class='add'>+struct dsb_dataset {</div><div class='add'>+	u32			mode;</div><div class='add'>+	u32			edge_ctrl_idx;</div><div class='add'>+	u32			edge_ctrl[TPDM_DSB_MAX_EDCR];</div><div class='add'>+	u32			edge_ctrl_mask[TPDM_DSB_MAX_EDCMR];</div><div class='add'>+	u32			patt_val[TPDM_DSB_MAX_PATT];</div><div class='add'>+	u32			patt_mask[TPDM_DSB_MAX_PATT];</div><div class='add'>+	u32			trig_patt[TPDM_DSB_MAX_PATT];</div><div class='add'>+	u32			trig_patt_mask[TPDM_DSB_MAX_PATT];</div><div class='add'>+	u32			msr[TPDM_DSB_MAX_MSR];</div><div class='add'>+	bool			patt_ts;</div><div class='add'>+	bool			patt_type;</div><div class='add'>+	bool			trig_ts;</div><div class='add'>+	bool			trig_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct tpdm_drvdata - specifics associated to an TPDM component</div><div class='ctx'>  * @base:       memory mapped base address for this component.</div><div class='hunk'>@@ -48,6 +181,8 @@</div><div class='ctx'>  * @spinlock:   lock for the drvdata value.</div><div class='ctx'>  * @enable:     enable status of the component.</div><div class='ctx'>  * @datasets:   The datasets types present of the TPDM.</div><div class='add'>+ * @dsb         Specifics associated to TPDM DSB.</div><div class='add'>+ * @dsb_msr_num Number of MSR supported by DSB TPDM</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> struct tpdm_drvdata {</div><div class='hunk'>@@ -57,6 +192,32 @@ struct tpdm_drvdata {</div><div class='ctx'> 	spinlock_t		spinlock;</div><div class='ctx'> 	bool			enable;</div><div class='ctx'> 	unsigned long		datasets;</div><div class='add'>+	struct dsb_dataset	*dsb;</div><div class='add'>+	u32			dsb_msr_num;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Enumerate members of various datasets */</div><div class='add'>+enum dataset_mem {</div><div class='add'>+	DSB_EDGE_CTRL,</div><div class='add'>+	DSB_EDGE_CTRL_MASK,</div><div class='add'>+	DSB_TRIG_PATT,</div><div class='add'>+	DSB_TRIG_PATT_MASK,</div><div class='add'>+	DSB_PATT,</div><div class='add'>+	DSB_PATT_MASK,</div><div class='add'>+	DSB_MSR,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct tpdm_dataset_attribute - Record the member variables and</div><div class='add'>+ * index number of datasets that need to be operated by sysfs file</div><div class='add'>+ * @attr:       The device attribute</div><div class='add'>+ * @mem:        The member in the dataset data structure</div><div class='add'>+ * @idx:        The index number of the array data</div><div class='add'>+ */</div><div class='add'>+struct tpdm_dataset_attribute {</div><div class='add'>+	struct device_attribute attr;</div><div class='add'>+	enum dataset_mem mem;</div><div class='add'>+	u32 idx;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif  /* _CORESIGHT_CORESIGHT_TPDM_H */</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c<br/>index e20c1c6acc73..6136776482e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-trbe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-trbe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-trbe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-trbe.c</a></div><div class='hunk'>@@ -1253,8 +1253,18 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp</div><div class='ctx'> 	desc.name = devm_kasprintf(dev, GFP_KERNEL, "trbe%d", cpu);</div><div class='ctx'> 	if (!desc.name)</div><div class='ctx'> 		goto cpu_clear;</div><div class='del'>-</div><div class='del'>-	desc.pdata = coresight_get_platform_data(dev);</div><div class='add'>+	/*</div><div class='add'>+	 * TRBE coresight devices do not need regular connections</div><div class='add'>+	 * information, as the paths get built between all percpu</div><div class='add'>+	 * source and their respective percpu sink devices. Though</div><div class='add'>+	 * coresight_register() expect device connections via the</div><div class='add'>+	 * platform_data, which TRBE devices do not have. As they</div><div class='add'>+	 * are not real ACPI devices, coresight_get_platform_data()</div><div class='add'>+	 * ends up failing. Instead let's allocate a dummy zeroed</div><div class='add'>+	 * coresight_platform_data structure and assign that back</div><div class='add'>+	 * into the device for that purpose.</div><div class='add'>+	 */</div><div class='add'>+	desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL);</div><div class='ctx'> 	if (IS_ERR(desc.pdata))</div><div class='ctx'> 		goto cpu_clear;</div><div class='ctx'> </div><div class='hunk'>@@ -1520,14 +1530,13 @@ probe_failed:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int arm_trbe_device_remove(struct platform_device *pdev)</div><div class='add'>+static void arm_trbe_device_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct trbe_drvdata *drvdata = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	arm_trbe_remove_cpuhp(drvdata);</div><div class='ctx'> 	arm_trbe_remove_coresight(drvdata);</div><div class='ctx'> 	arm_trbe_remove_irq(drvdata);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id arm_trbe_of_match[] = {</div><div class='hunk'>@@ -1536,14 +1545,23 @@ static const struct of_device_id arm_trbe_of_match[] = {</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, arm_trbe_of_match);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_ACPI</div><div class='add'>+static const struct platform_device_id arm_trbe_acpi_match[] = {</div><div class='add'>+	{ ARMV8_TRBE_PDEV_NAME, 0 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(platform, arm_trbe_acpi_match);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> static struct platform_driver arm_trbe_driver = {</div><div class='add'>+	.id_table = ACPI_PTR(arm_trbe_acpi_match),</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = DRVNAME,</div><div class='ctx'> 		.of_match_table = of_match_ptr(arm_trbe_of_match),</div><div class='ctx'> 		.suppress_bind_attrs = true,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe	= arm_trbe_device_probe,</div><div class='del'>-	.remove	= arm_trbe_device_remove,</div><div class='add'>+	.remove_new = arm_trbe_device_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init arm_trbe_init(void)</div><div class='head'>diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h<br/>index e915e749be55..45202c48acce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-trbe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/coresight-trbe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/coresight-trbe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/coresight-trbe.h</a></div><div class='hunk'>@@ -7,11 +7,13 @@</div><div class='ctx'>  *</div><div class='ctx'>  * Author: Anshuman Khandual &lt;anshuman.khandual@arm.com&gt;</div><div class='ctx'>  */</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/coresight.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/perf/arm_pmu.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/smp.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c<br/>index e9a32a97fbee..10e886455b8b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/ultrasoc-smb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/ultrasoc-smb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/ultrasoc-smb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/ultrasoc-smb.c</a></div><div class='hunk'>@@ -97,27 +97,19 @@ static int smb_open(struct inode *inode, struct file *file)</div><div class='ctx'> {</div><div class='ctx'> 	struct smb_drv_data *drvdata = container_of(file-&gt;private_data,</div><div class='ctx'> 					struct smb_drv_data, miscdev);</div><div class='del'>-	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='add'>+	guard(spinlock)(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> </div><div class='del'>-	if (drvdata-&gt;reading) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (drvdata-&gt;reading)</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='del'>-	if (atomic_read(&amp;drvdata-&gt;csdev-&gt;refcnt)) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (atomic_read(&amp;drvdata-&gt;csdev-&gt;refcnt))</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	smb_update_data_size(drvdata);</div><div class='del'>-</div><div class='ctx'> 	drvdata-&gt;reading = true;</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t smb_read(struct file *file, char __user *data, size_t len,</div><div class='hunk'>@@ -132,10 +124,8 @@ static ssize_t smb_read(struct file *file, char __user *data, size_t len,</div><div class='ctx'> 	if (!len)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='del'>-</div><div class='ctx'> 	if (!sdb-&gt;data_size)</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	to_copy = min(sdb-&gt;data_size, len);</div><div class='ctx'> </div><div class='hunk'>@@ -145,20 +135,15 @@ static ssize_t smb_read(struct file *file, char __user *data, size_t len,</div><div class='ctx'> </div><div class='ctx'> 	if (copy_to_user(data, sdb-&gt;buf_base + sdb-&gt;buf_rdptr, to_copy)) {</div><div class='ctx'> 		dev_dbg(dev, "Failed to copy data to user\n");</div><div class='del'>-		to_copy = -EFAULT;</div><div class='del'>-		goto out;</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	*ppos += to_copy;</div><div class='del'>-</div><div class='ctx'> 	smb_update_read_ptr(drvdata, to_copy);</div><div class='del'>-</div><div class='del'>-	dev_dbg(dev, "%zu bytes copied\n", to_copy);</div><div class='del'>-out:</div><div class='ctx'> 	if (!sdb-&gt;data_size)</div><div class='ctx'> 		smb_reset_buffer(drvdata);</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='add'>+	dev_dbg(dev, "%zu bytes copied\n", to_copy);</div><div class='ctx'> 	return to_copy;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -167,9 +152,8 @@ static int smb_release(struct inode *inode, struct file *file)</div><div class='ctx'> 	struct smb_drv_data *drvdata = container_of(file-&gt;private_data,</div><div class='ctx'> 					struct smb_drv_data, miscdev);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='add'>+	guard(spinlock)(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> 	drvdata-&gt;reading = false;</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -262,19 +246,15 @@ static int smb_enable(struct coresight_device *csdev, enum cs_mode mode,</div><div class='ctx'> 	struct smb_drv_data *drvdata = dev_get_drvdata(csdev-&gt;dev.parent);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='add'>+	guard(spinlock)(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> </div><div class='ctx'> 	/* Do nothing, the trace data is reading by other interface now */</div><div class='del'>-	if (drvdata-&gt;reading) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (drvdata-&gt;reading)</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	/* Do nothing, the SMB is already enabled as other mode */</div><div class='del'>-	if (drvdata-&gt;mode != CS_MODE_DISABLED &amp;&amp; drvdata-&gt;mode != mode) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (drvdata-&gt;mode != CS_MODE_DISABLED &amp;&amp; drvdata-&gt;mode != mode)</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	switch (mode) {</div><div class='ctx'> 	case CS_MODE_SYSFS:</div><div class='hunk'>@@ -288,13 +268,10 @@ static int smb_enable(struct coresight_device *csdev, enum cs_mode mode,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto out;</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	atomic_inc(&amp;csdev-&gt;refcnt);</div><div class='del'>-</div><div class='ctx'> 	dev_dbg(&amp;csdev-&gt;dev, "Ultrasoc SMB enabled\n");</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -302,19 +279,14 @@ out:</div><div class='ctx'> static int smb_disable(struct coresight_device *csdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct smb_drv_data *drvdata = dev_get_drvdata(csdev-&gt;dev.parent);</div><div class='del'>-	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='add'>+	guard(spinlock)(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> </div><div class='del'>-	if (drvdata-&gt;reading) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (drvdata-&gt;reading)</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='del'>-	if (atomic_dec_return(&amp;csdev-&gt;refcnt)) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='add'>+	if (atomic_dec_return(&amp;csdev-&gt;refcnt))</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	/* Complain if we (somehow) got out of sync */</div><div class='ctx'> 	WARN_ON_ONCE(drvdata-&gt;mode == CS_MODE_DISABLED);</div><div class='hunk'>@@ -324,12 +296,9 @@ static int smb_disable(struct coresight_device *csdev)</div><div class='ctx'> 	/* Dissociate from the target process. */</div><div class='ctx'> 	drvdata-&gt;pid = -1;</div><div class='ctx'> 	drvdata-&gt;mode = CS_MODE_DISABLED;</div><div class='del'>-</div><div class='ctx'> 	dev_dbg(&amp;csdev-&gt;dev, "Ultrasoc SMB disabled\n");</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void *smb_alloc_buffer(struct coresight_device *csdev,</div><div class='hunk'>@@ -402,17 +371,17 @@ static unsigned long smb_update_buffer(struct coresight_device *csdev,</div><div class='ctx'> 	struct smb_drv_data *drvdata = dev_get_drvdata(csdev-&gt;dev.parent);</div><div class='ctx'> 	struct smb_data_buffer *sdb = &amp;drvdata-&gt;sdb;</div><div class='ctx'> 	struct cs_buffers *buf = sink_config;</div><div class='del'>-	unsigned long data_size = 0;</div><div class='add'>+	unsigned long data_size;</div><div class='ctx'> 	bool lost = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!buf)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;drvdata-&gt;mutex);</div><div class='add'>+	guard(spinlock)(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> </div><div class='ctx'> 	/* Don't do anything if another tracer is using this sink. */</div><div class='ctx'> 	if (atomic_read(&amp;csdev-&gt;refcnt) != 1)</div><div class='del'>-		goto out;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	smb_disable_hw(drvdata);</div><div class='ctx'> 	smb_update_data_size(drvdata);</div><div class='hunk'>@@ -431,8 +400,6 @@ static unsigned long smb_update_buffer(struct coresight_device *csdev,</div><div class='ctx'> 	smb_sync_perf_buffer(drvdata, buf, handle-&gt;head);</div><div class='ctx'> 	if (!buf-&gt;snapshot &amp;&amp; lost)</div><div class='ctx'> 		perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;drvdata-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return data_size;</div><div class='ctx'> }</div><div class='hunk'>@@ -484,7 +451,6 @@ static int smb_init_data_buffer(struct platform_device *pdev,</div><div class='ctx'> static void smb_init_hw(struct smb_drv_data *drvdata)</div><div class='ctx'> {</div><div class='ctx'> 	smb_disable_hw(drvdata);</div><div class='del'>-	smb_reset_buffer(drvdata);</div><div class='ctx'> </div><div class='ctx'> 	writel(SMB_LB_CFG_LO_DEFAULT, drvdata-&gt;base + SMB_LB_CFG_LO_REG);</div><div class='ctx'> 	writel(SMB_LB_CFG_HI_DEFAULT, drvdata-&gt;base + SMB_LB_CFG_HI_REG);</div><div class='hunk'>@@ -590,38 +556,32 @@ static int smb_probe(struct platform_device *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_init(&amp;drvdata-&gt;mutex);</div><div class='add'>+	ret = smb_config_inport(dev, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	smb_reset_buffer(drvdata);</div><div class='add'>+	platform_set_drvdata(pdev, drvdata);</div><div class='add'>+	spin_lock_init(&amp;drvdata-&gt;spinlock);</div><div class='ctx'> 	drvdata-&gt;pid = -1;</div><div class='ctx'> </div><div class='ctx'> 	ret = smb_register_sink(pdev, drvdata);</div><div class='ctx'> 	if (ret) {</div><div class='add'>+		smb_config_inport(&amp;pdev-&gt;dev, false);</div><div class='ctx'> 		dev_err(dev, "Failed to register SMB sink\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = smb_config_inport(dev, true);</div><div class='del'>-	if (ret) {</div><div class='del'>-		smb_unregister_sink(drvdata);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	platform_set_drvdata(pdev, drvdata);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int smb_remove(struct platform_device *pdev)</div><div class='add'>+static void smb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct smb_drv_data *drvdata = platform_get_drvdata(pdev);</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = smb_config_inport(&amp;pdev-&gt;dev, false);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='ctx'> </div><div class='ctx'> 	smb_unregister_sink(drvdata);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	smb_config_inport(&amp;pdev-&gt;dev, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_ACPI</div><div class='hunk'>@@ -639,7 +599,7 @@ static struct platform_driver smb_driver = {</div><div class='ctx'> 		.suppress_bind_attrs = true,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = smb_probe,</div><div class='del'>-	.remove = smb_remove,</div><div class='add'>+	.remove_new = smb_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(smb_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h<br/>index d2e14e8d2c8a..82a44c14a882 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/ultrasoc-smb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/coresight/ultrasoc-smb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/coresight/ultrasoc-smb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/coresight/ultrasoc-smb.h</a></div><div class='hunk'>@@ -8,7 +8,7 @@</div><div class='ctx'> #define _ULTRASOC_SMB_H</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/miscdevice.h&gt;</div><div class='del'>-#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='ctx'> </div><div class='ctx'> /* Offset of SMB global registers */</div><div class='ctx'> #define SMB_GLB_CFG_REG		0x00</div><div class='hunk'>@@ -105,7 +105,7 @@ struct smb_data_buffer {</div><div class='ctx'>  * @csdev:	Component vitals needed by the framework.</div><div class='ctx'>  * @sdb:	Data buffer for SMB.</div><div class='ctx'>  * @miscdev:	Specifics to handle "/dev/xyz.smb" entry.</div><div class='del'>- * @mutex:	Control data access to one at a time.</div><div class='add'>+ * @spinlock:	Control data access to one at a time.</div><div class='ctx'>  * @reading:	Synchronise user space access to SMB buffer.</div><div class='ctx'>  * @pid:	Process ID of the process being monitored by the</div><div class='ctx'>  *		session that is using this component.</div><div class='hunk'>@@ -116,7 +116,7 @@ struct smb_drv_data {</div><div class='ctx'> 	struct coresight_device	*csdev;</div><div class='ctx'> 	struct smb_data_buffer sdb;</div><div class='ctx'> 	struct miscdevice miscdev;</div><div class='del'>-	struct mutex mutex;</div><div class='add'>+	spinlock_t spinlock;</div><div class='ctx'> 	bool reading;</div><div class='ctx'> 	pid_t pid;</div><div class='ctx'> 	enum cs_mode mode;</div><div class='head'>diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c<br/>index 49ea1b0f7489..c1b5fd2b8974 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/ptt/hisi_ptt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/ptt/hisi_ptt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/ptt/hisi_ptt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/ptt/hisi_ptt.c</a></div><div class='hunk'>@@ -183,6 +183,10 @@ static void hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt)</div><div class='ctx'> static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt)</div><div class='ctx'> {</div><div class='ctx'> 	writel(0, hisi_ptt-&gt;iobase + HISI_PTT_TRACE_CTRL);</div><div class='add'>+</div><div class='add'>+	/* Mask the interrupt on the end */</div><div class='add'>+	writel(HISI_PTT_TRACE_INT_MASK_ALL, hisi_ptt-&gt;iobase + HISI_PTT_TRACE_INT_MASK);</div><div class='add'>+</div><div class='ctx'> 	hisi_ptt-&gt;trace_ctrl.started = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -270,15 +274,14 @@ static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop)</div><div class='ctx'> 	buf-&gt;pos += size;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Just commit the traced data if we're going to stop. Otherwise if the</div><div class='del'>-	 * resident AUX buffer cannot contain the data of next trace buffer,</div><div class='del'>-	 * apply a new one.</div><div class='add'>+	 * Always commit the data to the AUX buffer in time to make sure</div><div class='add'>+	 * userspace got enough time to consume the data.</div><div class='add'>+	 *</div><div class='add'>+	 * If we're not going to stop, apply a new one and check whether</div><div class='add'>+	 * there's enough room for the next trace.</div><div class='ctx'> 	 */</div><div class='del'>-	if (stop) {</div><div class='del'>-		perf_aux_output_end(handle, buf-&gt;pos);</div><div class='del'>-	} else if (buf-&gt;length - buf-&gt;pos &lt; HISI_PTT_TRACE_BUF_SIZE) {</div><div class='del'>-		perf_aux_output_end(handle, buf-&gt;pos);</div><div class='del'>-</div><div class='add'>+	perf_aux_output_end(handle, size);</div><div class='add'>+	if (!stop) {</div><div class='ctx'> 		buf = perf_aux_output_begin(handle, event);</div><div class='ctx'> 		if (!buf)</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -342,9 +345,9 @@ static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	hisi_ptt-&gt;trace_irq = pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ);</div><div class='del'>-	ret = devm_request_threaded_irq(&amp;pdev-&gt;dev, hisi_ptt-&gt;trace_irq,</div><div class='del'>-					NULL, hisi_ptt_isr, 0,</div><div class='del'>-					DRV_NAME, hisi_ptt);</div><div class='add'>+	ret = devm_request_irq(&amp;pdev-&gt;dev, hisi_ptt-&gt;trace_irq, hisi_ptt_isr,</div><div class='add'>+				IRQF_NOBALANCING | IRQF_NO_THREAD, DRV_NAME,</div><div class='add'>+				hisi_ptt);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		pci_err(pdev, "failed to request irq %d, ret = %d\n",</div><div class='ctx'> 			hisi_ptt-&gt;trace_irq, ret);</div><div class='hunk'>@@ -1000,6 +1003,9 @@ static int hisi_ptt_pmu_event_init(struct perf_event *event)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (event-&gt;attach_state &amp; PERF_ATTACH_TASK)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	if (event-&gt;attr.type != hisi_ptt-&gt;hisi_ptt_pmu.type)</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='hunk'>@@ -1178,6 +1184,10 @@ static void hisi_ptt_pmu_del(struct perf_event *event, int flags)</div><div class='ctx'> 	hisi_ptt_pmu_stop(event, PERF_EF_UPDATE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void hisi_ptt_pmu_read(struct perf_event *event)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void hisi_ptt_remove_cpuhp_instance(void *hotplug_node)</div><div class='ctx'> {</div><div class='ctx'> 	cpuhp_state_remove_instance_nocalls(hisi_ptt_pmu_online, hotplug_node);</div><div class='hunk'>@@ -1221,6 +1231,7 @@ static int hisi_ptt_register_pmu(struct hisi_ptt *hisi_ptt)</div><div class='ctx'> 		.stop		= hisi_ptt_pmu_stop,</div><div class='ctx'> 		.add		= hisi_ptt_pmu_add,</div><div class='ctx'> 		.del		= hisi_ptt_pmu_del,</div><div class='add'>+		.read		= hisi_ptt_pmu_read,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	reg = readl(hisi_ptt-&gt;iobase + HISI_PTT_LOCATION);</div><div class='head'>diff --git a/drivers/hwtracing/ptt/hisi_ptt.h b/drivers/hwtracing/ptt/hisi_ptt.h<br/>index e17f045d7e72..46030aa88081 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/hwtracing/ptt/hisi_ptt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/hwtracing/ptt/hisi_ptt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/hwtracing/ptt/hisi_ptt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/hwtracing/ptt/hisi_ptt.h</a></div><div class='hunk'>@@ -47,6 +47,7 @@</div><div class='ctx'> #define HISI_PTT_TRACE_INT_STAT		0x0890</div><div class='ctx'> #define   HISI_PTT_TRACE_INT_STAT_MASK	GENMASK(3, 0)</div><div class='ctx'> #define HISI_PTT_TRACE_INT_MASK		0x0894</div><div class='add'>+#define   HISI_PTT_TRACE_INT_MASK_ALL	GENMASK(3, 0)</div><div class='ctx'> #define HISI_PTT_TUNING_INT_STAT	0x0898</div><div class='ctx'> #define   HISI_PTT_TUNING_INT_STAT_MASK	BIT(0)</div><div class='ctx'> #define HISI_PTT_TRACE_WR_STS		0x08a0</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-ali1535.c b/drivers/i2c/busses/i2c-ali1535.c<br/>index ee83c4581bce..461eb23f9d47 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali1535.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-ali1535.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali1535.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali1535.c</a></div><div class='hunk'>@@ -477,7 +477,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter ali1535_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-ali1563.c b/drivers/i2c/busses/i2c-ali1563.c<br/>index 55a9e93fbfeb..307fb0666ecb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali1563.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-ali1563.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali1563.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali1563.c</a></div><div class='hunk'>@@ -390,7 +390,7 @@ static const struct i2c_algorithm ali1563_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter ali1563_adapter = {</div><div class='ctx'> 	.owner	= THIS_MODULE,</div><div class='del'>-	.class	= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class	= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo	= &amp;ali1563_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-ali15x3.c b/drivers/i2c/busses/i2c-ali15x3.c<br/>index 0231c5be6354..d2fa30deb054 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali15x3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-ali15x3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ali15x3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ali15x3.c</a></div><div class='hunk'>@@ -461,7 +461,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter ali15x3_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-amd756.c b/drivers/i2c/busses/i2c-amd756.c<br/>index ef1307a258e9..208310db906d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-amd756.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-amd756.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-amd756.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-amd756.c</a></div><div class='hunk'>@@ -285,7 +285,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> struct i2c_adapter amd756_smbus = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c<br/>index 1ed7e945bb6d..42a9b1221065 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-amd8111.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-amd8111.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-amd8111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-amd8111.c</a></div><div class='hunk'>@@ -449,7 +449,7 @@ static int amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id)</div><div class='ctx'> 	smbus-&gt;adapter.owner = THIS_MODULE;</div><div class='ctx'> 	snprintf(smbus-&gt;adapter.name, sizeof(smbus-&gt;adapter.name),</div><div class='ctx'> 		"SMBus2 AMD8111 adapter at %04x", smbus-&gt;base);</div><div class='del'>-	smbus-&gt;adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	smbus-&gt;adapter.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	smbus-&gt;adapter.algo = &amp;smbus_algorithm;</div><div class='ctx'> 	smbus-&gt;adapter.algo_data = smbus;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c<br/>index 28e2a5fc4528..5511fd46a65e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-aspeed.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-aspeed.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-aspeed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-aspeed.c</a></div><div class='hunk'>@@ -249,18 +249,46 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)</div><div class='ctx'> 	if (!slave)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	command = readl(bus-&gt;base + ASPEED_I2C_CMD_REG);</div><div class='add'>+	/*</div><div class='add'>+	 * Handle stop conditions early, prior to SLAVE_MATCH. Some masters may drive</div><div class='add'>+	 * transfers with low enough latency between the nak/stop phase of the current</div><div class='add'>+	 * command and the start/address phase of the following command that the</div><div class='add'>+	 * interrupts are coalesced by the time we process them.</div><div class='add'>+	 */</div><div class='add'>+	if (irq_status &amp; ASPEED_I2CD_INTR_NORMAL_STOP) {</div><div class='add'>+		irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;</div><div class='add'>+		bus-&gt;slave_state = ASPEED_I2C_SLAVE_STOP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (irq_status &amp; ASPEED_I2CD_INTR_TX_NAK &amp;&amp;</div><div class='add'>+	    bus-&gt;slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {</div><div class='add'>+		irq_handled |= ASPEED_I2CD_INTR_TX_NAK;</div><div class='add'>+		bus-&gt;slave_state = ASPEED_I2C_SLAVE_STOP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Propagate any stop conditions to the slave implementation. */</div><div class='add'>+	if (bus-&gt;slave_state == ASPEED_I2C_SLAVE_STOP) {</div><div class='add'>+		i2c_slave_event(slave, I2C_SLAVE_STOP, &amp;value);</div><div class='add'>+		bus-&gt;slave_state = ASPEED_I2C_SLAVE_INACTIVE;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* Slave was requested, restart state machine. */</div><div class='add'>+	/*</div><div class='add'>+	 * Now that we've dealt with any potentially coalesced stop conditions,</div><div class='add'>+	 * address any start conditions.</div><div class='add'>+	 */</div><div class='ctx'> 	if (irq_status &amp; ASPEED_I2CD_INTR_SLAVE_MATCH) {</div><div class='ctx'> 		irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;</div><div class='ctx'> 		bus-&gt;slave_state = ASPEED_I2C_SLAVE_START;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Slave is not currently active, irq was for someone else. */</div><div class='add'>+	/*</div><div class='add'>+	 * If the slave has been stopped and not started then slave interrupt</div><div class='add'>+	 * handling is complete.</div><div class='add'>+	 */</div><div class='ctx'> 	if (bus-&gt;slave_state == ASPEED_I2C_SLAVE_INACTIVE)</div><div class='ctx'> 		return irq_handled;</div><div class='ctx'> </div><div class='add'>+	command = readl(bus-&gt;base + ASPEED_I2C_CMD_REG);</div><div class='ctx'> 	dev_dbg(bus-&gt;dev, "slave irq status 0x%08x, cmd 0x%08x\n",</div><div class='ctx'> 		irq_status, command);</div><div class='ctx'> </div><div class='hunk'>@@ -279,17 +307,6 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)</div><div class='ctx'> 		irq_handled |= ASPEED_I2CD_INTR_RX_DONE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Slave was asked to stop. */</div><div class='del'>-	if (irq_status &amp; ASPEED_I2CD_INTR_NORMAL_STOP) {</div><div class='del'>-		irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;</div><div class='del'>-		bus-&gt;slave_state = ASPEED_I2C_SLAVE_STOP;</div><div class='del'>-	}</div><div class='del'>-	if (irq_status &amp; ASPEED_I2CD_INTR_TX_NAK &amp;&amp;</div><div class='del'>-	    bus-&gt;slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) {</div><div class='del'>-		irq_handled |= ASPEED_I2CD_INTR_TX_NAK;</div><div class='del'>-		bus-&gt;slave_state = ASPEED_I2C_SLAVE_STOP;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	switch (bus-&gt;slave_state) {</div><div class='ctx'> 	case ASPEED_I2C_SLAVE_READ_REQUESTED:</div><div class='ctx'> 		if (unlikely(irq_status &amp; ASPEED_I2CD_INTR_TX_ACK))</div><div class='hunk'>@@ -324,8 +341,7 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)</div><div class='ctx'> 		i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &amp;value);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ASPEED_I2C_SLAVE_STOP:</div><div class='del'>-		i2c_slave_event(slave, I2C_SLAVE_STOP, &amp;value);</div><div class='del'>-		bus-&gt;slave_state = ASPEED_I2C_SLAVE_INACTIVE;</div><div class='add'>+		/* Stop event handling is done early. Unreachable. */</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ASPEED_I2C_SLAVE_START:</div><div class='ctx'> 		/* Slave was just started. Waiting for the next event. */;</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c<br/>index 9a664abf734d..4404b4aac676 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-cpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-cpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-cpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-cpm.c</a></div><div class='hunk'>@@ -658,7 +658,7 @@ static int cpm_i2c_probe(struct platform_device *ofdev)</div><div class='ctx'> 	/* register new adapter to i2c module... */</div><div class='ctx'> </div><div class='ctx'> 	data = of_get_property(ofdev-&gt;dev.of_node, "linux,i2c-index", &amp;len);</div><div class='del'>-	cpm-&gt;adap.nr = (data &amp;&amp; len == 4) ? be32_to_cpup(data) : -1;</div><div class='add'>+	cpm-&gt;adap.nr = (data &amp;&amp; len == 4) ? *data : -1;</div><div class='ctx'> 	result = i2c_add_numbered_adapter(&amp;cpm-&gt;adap);</div><div class='ctx'> </div><div class='ctx'> 	if (result &lt; 0)</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-elektor.c b/drivers/i2c/busses/i2c-elektor.c<br/>index b0f50dce9d0f..cfe8665cacd2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-elektor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-elektor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-elektor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-elektor.c</a></div><div class='hunk'>@@ -188,7 +188,7 @@ static struct i2c_algo_pcf_data pcf_isa_data = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter pcf_isa_ops = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo_data	= &amp;pcf_isa_data,</div><div class='ctx'> 	.name		= "i2c-elektor",</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c<br/>index fb35a75fe0e3..4f1411b1a775 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-gpio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-gpio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-gpio.c</a></div><div class='hunk'>@@ -25,7 +25,6 @@ struct i2c_gpio_private_data {</div><div class='ctx'> 	struct i2c_algo_bit_data bit_data;</div><div class='ctx'> 	struct i2c_gpio_platform_data pdata;</div><div class='ctx'> #ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR</div><div class='del'>-	struct dentry *debug_dir;</div><div class='ctx'> 	/* these must be protected by bus lock */</div><div class='ctx'> 	struct completion scl_irq_completion;</div><div class='ctx'> 	u64 scl_irq_data;</div><div class='hunk'>@@ -72,7 +71,6 @@ static int i2c_gpio_getscl(void *data)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR</div><div class='del'>-static struct dentry *i2c_gpio_debug_dir;</div><div class='ctx'> </div><div class='ctx'> #define setsda(bd, val)	((bd)-&gt;setsda((bd)-&gt;data, val))</div><div class='ctx'> #define setscl(bd, val)	((bd)-&gt;setscl((bd)-&gt;data, val))</div><div class='hunk'>@@ -258,41 +256,23 @@ static void i2c_gpio_fault_injector_init(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * If there will be a debugfs-dir per i2c adapter somewhen, put the</div><div class='del'>-	 * 'fault-injector' dir there. Until then, we have a global dir with</div><div class='del'>-	 * all adapters as subdirs.</div><div class='del'>-	 */</div><div class='del'>-	if (!i2c_gpio_debug_dir)</div><div class='del'>-		i2c_gpio_debug_dir = debugfs_create_dir("i2c-fault-injector", NULL);</div><div class='del'>-</div><div class='del'>-	priv-&gt;debug_dir = debugfs_create_dir(pdev-&gt;name, i2c_gpio_debug_dir);</div><div class='del'>-</div><div class='ctx'> 	init_completion(&amp;priv-&gt;scl_irq_completion);</div><div class='ctx'> </div><div class='del'>-	debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv-&gt;debug_dir,</div><div class='add'>+	debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv-&gt;adap.debugfs,</div><div class='ctx'> 				   priv, &amp;fops_incomplete_addr_phase);</div><div class='del'>-	debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv-&gt;debug_dir,</div><div class='add'>+	debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv-&gt;adap.debugfs,</div><div class='ctx'> 				   priv, &amp;fops_incomplete_write_byte);</div><div class='ctx'> 	if (priv-&gt;bit_data.getscl) {</div><div class='del'>-		debugfs_create_file_unsafe("inject_panic", 0200, priv-&gt;debug_dir,</div><div class='add'>+		debugfs_create_file_unsafe("inject_panic", 0200, priv-&gt;adap.debugfs,</div><div class='ctx'> 					   priv, &amp;fops_inject_panic);</div><div class='del'>-		debugfs_create_file_unsafe("lose_arbitration", 0200, priv-&gt;debug_dir,</div><div class='add'>+		debugfs_create_file_unsafe("lose_arbitration", 0200, priv-&gt;adap.debugfs,</div><div class='ctx'> 					   priv, &amp;fops_lose_arbitration);</div><div class='ctx'> 	}</div><div class='del'>-	debugfs_create_file_unsafe("scl", 0600, priv-&gt;debug_dir, priv, &amp;fops_scl);</div><div class='del'>-	debugfs_create_file_unsafe("sda", 0600, priv-&gt;debug_dir, priv, &amp;fops_sda);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void i2c_gpio_fault_injector_exit(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev);</div><div class='del'>-</div><div class='del'>-	debugfs_remove_recursive(priv-&gt;debug_dir);</div><div class='add'>+	debugfs_create_file_unsafe("scl", 0600, priv-&gt;adap.debugfs, priv, &amp;fops_scl);</div><div class='add'>+	debugfs_create_file_unsafe("sda", 0600, priv-&gt;adap.debugfs, priv, &amp;fops_sda);</div><div class='ctx'> }</div><div class='ctx'> #else</div><div class='ctx'> static inline void i2c_gpio_fault_injector_init(struct platform_device *pdev) {}</div><div class='del'>-static inline void i2c_gpio_fault_injector_exit(struct platform_device *pdev) {}</div><div class='ctx'> #endif /* CONFIG_I2C_GPIO_FAULT_INJECTOR*/</div><div class='ctx'> </div><div class='ctx'> /* Get i2c-gpio properties from DT or ACPI table */</div><div class='hunk'>@@ -444,7 +424,7 @@ static int i2c_gpio_probe(struct platform_device *pdev)</div><div class='ctx'> 		snprintf(adap-&gt;name, sizeof(adap-&gt;name), "i2c-gpio%d", pdev-&gt;id);</div><div class='ctx'> </div><div class='ctx'> 	adap-&gt;algo_data = bit_data;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	adap-&gt;class = I2C_CLASS_HWMON;</div><div class='ctx'> 	adap-&gt;dev.parent = dev;</div><div class='ctx'> 	device_set_node(&amp;adap-&gt;dev, fwnode);</div><div class='ctx'> </div><div class='hunk'>@@ -475,8 +455,6 @@ static void i2c_gpio_remove(struct platform_device *pdev)</div><div class='ctx'> 	struct i2c_gpio_private_data *priv;</div><div class='ctx'> 	struct i2c_adapter *adap;</div><div class='ctx'> </div><div class='del'>-	i2c_gpio_fault_injector_exit(pdev);</div><div class='del'>-</div><div class='ctx'> 	priv = platform_get_drvdata(pdev);</div><div class='ctx'> 	adap = &amp;priv-&gt;adap;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c<br/>index 070999139c6d..3932e8d96a17 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-i801.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-i801.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-i801.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-i801.c</a></div><div class='hunk'>@@ -1230,8 +1230,10 @@ static const struct {</div><div class='ctx'> 	 * Additional individual entries were added after verification.</div><div class='ctx'> 	 */</div><div class='ctx'> 	{ "Latitude 5480",      0x29 },</div><div class='add'>+	{ "Precision 3540",     0x29 },</div><div class='ctx'> 	{ "Vostro V131",        0x1d },</div><div class='ctx'> 	{ "Vostro 5568",        0x29 },</div><div class='add'>+	{ "XPS 15 7590",        0x29 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c<br/>index 408820319ec4..7fb87b78923e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ibm_iic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-ibm_iic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-ibm_iic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-ibm_iic.c</a></div><div class='hunk'>@@ -739,7 +739,7 @@ static int iic_probe(struct platform_device *ofdev)</div><div class='ctx'> 	adap-&gt;dev.of_node = of_node_get(np);</div><div class='ctx'> 	strscpy(adap-&gt;name, "IBM IIC", sizeof(adap-&gt;name));</div><div class='ctx'> 	i2c_set_adapdata(adap, dev);</div><div class='del'>-	adap-&gt;class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	adap-&gt;class = I2C_CLASS_HWMON;</div><div class='ctx'> 	adap-&gt;algo = &amp;iic_algo;</div><div class='ctx'> 	adap-&gt;timeout = HZ;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c<br/>index 1775a79aeba2..88a053987403 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-imx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-imx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-imx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-imx.c</a></div><div class='hunk'>@@ -1401,7 +1401,7 @@ static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,</div><div class='ctx'> 			PINCTRL_STATE_DEFAULT);</div><div class='ctx'> 	i2c_imx-&gt;pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx-&gt;pinctrl,</div><div class='ctx'> 			"gpio");</div><div class='del'>-	rinfo-&gt;sda_gpiod = devm_gpiod_get(&amp;pdev-&gt;dev, "sda", GPIOD_IN);</div><div class='add'>+	rinfo-&gt;sda_gpiod = devm_gpiod_get_optional(&amp;pdev-&gt;dev, "sda", GPIOD_IN);</div><div class='ctx'> 	rinfo-&gt;scl_gpiod = devm_gpiod_get(&amp;pdev-&gt;dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);</div><div class='ctx'> </div><div class='ctx'> 	if (PTR_ERR(rinfo-&gt;sda_gpiod) == -EPROBE_DEFER ||</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c<br/>index f2f7ebeeaecb..2e5f0165c3d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-iop3xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-iop3xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-iop3xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-iop3xx.c</a></div><div class='hunk'>@@ -478,7 +478,7 @@ iop3xx_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	memcpy(new_adapter-&gt;name, pdev-&gt;name, strlen(pdev-&gt;name));</div><div class='ctx'> 	new_adapter-&gt;owner = THIS_MODULE;</div><div class='del'>-	new_adapter-&gt;class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	new_adapter-&gt;class = I2C_CLASS_HWMON;</div><div class='ctx'> 	new_adapter-&gt;dev.parent = &amp;pdev-&gt;dev;</div><div class='ctx'> 	new_adapter-&gt;dev.of_node = pdev-&gt;dev.of_node;</div><div class='ctx'> 	new_adapter-&gt;nr = pdev-&gt;id;</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c<br/>index 1dc1ceaa4443..416a9968ed28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-isch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-isch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-isch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-isch.c</a></div><div class='hunk'>@@ -249,7 +249,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter sch_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-kempld.c b/drivers/i2c/busses/i2c-kempld.c<br/>index e01d75308288..c3a529a73b5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-kempld.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-kempld.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-kempld.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-kempld.c</a></div><div class='hunk'>@@ -283,8 +283,7 @@ static const struct i2c_algorithm kempld_i2c_algorithm = {</div><div class='ctx'> static const struct i2c_adapter kempld_i2c_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='ctx'> 	.name		= "i2c-kempld",</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD |</div><div class='del'>-			  I2C_CLASS_DEPRECATED,</div><div class='add'>+	.class		= I2C_CLASS_HWMON | I2C_CLASS_DEPRECATED,</div><div class='ctx'> 	.algo		= &amp;kempld_i2c_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c<br/>index 6fec64ea67fb..099291a0411d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-mlxcpld.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-mlxcpld.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-mlxcpld.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-mlxcpld.c</a></div><div class='hunk'>@@ -477,7 +477,7 @@ static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext2 = {</div><div class='ctx'> static struct i2c_adapter mlxcpld_i2c_adapter = {</div><div class='ctx'> 	.owner          = THIS_MODULE,</div><div class='ctx'> 	.name           = "i2c-mlxcpld",</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo           = &amp;mlxcpld_i2c_algo,</div><div class='ctx'> 	.quirks		= &amp;mlxcpld_i2c_quirks,</div><div class='ctx'> 	.retries	= MLXCPLD_I2C_RETR_NUM,</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c<br/>index 38d203d93eee..fab662e6bc08 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-nforce2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-nforce2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-nforce2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-nforce2.c</a></div><div class='hunk'>@@ -349,7 +349,7 @@ static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> 	smbus-&gt;adapter.owner = THIS_MODULE;</div><div class='del'>-	smbus-&gt;adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	smbus-&gt;adapter.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	smbus-&gt;adapter.algo = &amp;smbus_algorithm;</div><div class='ctx'> 	smbus-&gt;adapter.algo_data = smbus;</div><div class='ctx'> 	smbus-&gt;adapter.dev.parent = &amp;dev-&gt;dev;</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c<br/>index ae4bae63ad4f..54181b3f1919 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-npcm7xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-npcm7xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-npcm7xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-npcm7xx.c</a></div><div class='hunk'>@@ -326,7 +326,6 @@ struct npcm_i2c {</div><div class='ctx'> 	u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];</div><div class='ctx'> 	u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];</div><div class='ctx'> #endif</div><div class='del'>-	struct dentry *debugfs; /* debugfs device directory */</div><div class='ctx'> 	u64 ber_cnt;</div><div class='ctx'> 	u64 rec_succ_cnt;</div><div class='ctx'> 	u64 rec_fail_cnt;</div><div class='hunk'>@@ -2250,27 +2249,15 @@ static const struct i2c_algorithm npcm_i2c_algo = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* i2c debugfs directory: used to keep health monitor of i2c devices */</div><div class='del'>-static struct dentry *npcm_i2c_debugfs_dir;</div><div class='del'>-</div><div class='ctx'> static void npcm_i2c_init_debugfs(struct platform_device *pdev,</div><div class='ctx'> 				  struct npcm_i2c *bus)</div><div class='ctx'> {</div><div class='del'>-	struct dentry *d;</div><div class='del'>-</div><div class='del'>-	if (!npcm_i2c_debugfs_dir)</div><div class='del'>-		return;</div><div class='del'>-	d = debugfs_create_dir(dev_name(&amp;pdev-&gt;dev), npcm_i2c_debugfs_dir);</div><div class='del'>-	if (IS_ERR_OR_NULL(d))</div><div class='del'>-		return;</div><div class='del'>-	debugfs_create_u64("ber_cnt", 0444, d, &amp;bus-&gt;ber_cnt);</div><div class='del'>-	debugfs_create_u64("nack_cnt", 0444, d, &amp;bus-&gt;nack_cnt);</div><div class='del'>-	debugfs_create_u64("rec_succ_cnt", 0444, d, &amp;bus-&gt;rec_succ_cnt);</div><div class='del'>-	debugfs_create_u64("rec_fail_cnt", 0444, d, &amp;bus-&gt;rec_fail_cnt);</div><div class='del'>-	debugfs_create_u64("timeout_cnt", 0444, d, &amp;bus-&gt;timeout_cnt);</div><div class='del'>-	debugfs_create_u64("tx_complete_cnt", 0444, d, &amp;bus-&gt;tx_complete_cnt);</div><div class='del'>-</div><div class='del'>-	bus-&gt;debugfs = d;</div><div class='add'>+	debugfs_create_u64("ber_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;ber_cnt);</div><div class='add'>+	debugfs_create_u64("nack_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;nack_cnt);</div><div class='add'>+	debugfs_create_u64("rec_succ_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;rec_succ_cnt);</div><div class='add'>+	debugfs_create_u64("rec_fail_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;rec_fail_cnt);</div><div class='add'>+	debugfs_create_u64("timeout_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;timeout_cnt);</div><div class='add'>+	debugfs_create_u64("tx_complete_cnt", 0444, bus-&gt;adap.debugfs, &amp;bus-&gt;tx_complete_cnt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int npcm_i2c_probe_bus(struct platform_device *pdev)</div><div class='hunk'>@@ -2362,7 +2349,6 @@ static void npcm_i2c_remove_bus(struct platform_device *pdev)</div><div class='ctx'> 	unsigned long lock_flags;</div><div class='ctx'> 	struct npcm_i2c *bus = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	debugfs_remove_recursive(bus-&gt;debugfs);</div><div class='ctx'> 	spin_lock_irqsave(&amp;bus-&gt;lock, lock_flags);</div><div class='ctx'> 	npcm_i2c_disable(bus);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;bus-&gt;lock, lock_flags);</div><div class='hunk'>@@ -2385,28 +2371,7 @@ static struct platform_driver npcm_i2c_bus_driver = {</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int __init npcm_i2c_init(void)</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);</div><div class='del'>-</div><div class='del'>-	ret = platform_driver_register(&amp;npcm_i2c_bus_driver);</div><div class='del'>-	if (ret) {</div><div class='del'>-		debugfs_remove_recursive(npcm_i2c_debugfs_dir);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-module_init(npcm_i2c_init);</div><div class='del'>-</div><div class='del'>-static void __exit npcm_i2c_exit(void)</div><div class='del'>-{</div><div class='del'>-	platform_driver_unregister(&amp;npcm_i2c_bus_driver);</div><div class='del'>-	debugfs_remove_recursive(npcm_i2c_debugfs_dir);</div><div class='del'>-}</div><div class='del'>-module_exit(npcm_i2c_exit);</div><div class='add'>+module_platform_driver(npcm_i2c_bus_driver);</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Avi Fishman &lt;avi.fishman@gmail.com&gt;");</div><div class='ctx'> MODULE_AUTHOR("Tali Perry &lt;tali.perry@nuvoton.com&gt;");</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-pasemi-pci.c b/drivers/i2c/busses/i2c-pasemi-pci.c<br/>index cfc89e04eb94..77f90c7436ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-pasemi-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-pasemi-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-pasemi-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-pasemi-pci.c</a></div><div class='hunk'>@@ -56,7 +56,7 @@ static int pasemi_smb_pci_probe(struct pci_dev *dev,</div><div class='ctx'> 	if (!smbus-&gt;ioaddr)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='del'>-	smbus-&gt;adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	smbus-&gt;adapter.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	error = pasemi_i2c_common_probe(smbus);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c<br/>index 809fbd014cd6..6a0392172b2f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-piix4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-piix4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-piix4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-piix4.c</a></div><div class='hunk'>@@ -943,7 +943,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	adap-&gt;owner = THIS_MODULE;</div><div class='del'>-	adap-&gt;class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	adap-&gt;class = I2C_CLASS_HWMON;</div><div class='ctx'> 	adap-&gt;algo = sb800_main ? &amp;piix4_smbus_algorithm_sb800</div><div class='ctx'> 				: &amp;smbus_algorithm;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c<br/>index 6d829ed2f868..0d2e7171e3a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-qcom-geni.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-qcom-geni.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-qcom-geni.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-qcom-geni.c</a></div><div class='hunk'>@@ -858,6 +858,7 @@ static int geni_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 	ret = geni_se_resources_on(&amp;gi2c-&gt;se);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Error turning on resources %d\n", ret);</div><div class='add'>+		clk_disable_unprepare(gi2c-&gt;core_clk);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	proto = geni_se_read_proto(&amp;gi2c-&gt;se);</div><div class='hunk'>@@ -877,8 +878,11 @@ static int geni_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 		/* FIFO is disabled, so we can only use GPI DMA */</div><div class='ctx'> 		gi2c-&gt;gpi_mode = true;</div><div class='ctx'> 		ret = setup_gpi_dma(gi2c);</div><div class='del'>-		if (ret)</div><div class='add'>+		if (ret) {</div><div class='add'>+			geni_se_resources_off(&amp;gi2c-&gt;se);</div><div class='add'>+			clk_disable_unprepare(gi2c-&gt;core_clk);</div><div class='ctx'> 			return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n");</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		dev_dbg(dev, "Using GPI DMA mode for I2C\n");</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -891,6 +895,8 @@ static int geni_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 		if (!tx_depth) {</div><div class='ctx'> 			dev_err(dev, "Invalid TX FIFO depth\n");</div><div class='add'>+			geni_se_resources_off(&amp;gi2c-&gt;se);</div><div class='add'>+			clk_disable_unprepare(gi2c-&gt;core_clk);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c<br/>index 829ac053bbb7..828aa2ea0fe4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-rcar.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-rcar.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-rcar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-rcar.c</a></div><div class='hunk'>@@ -89,6 +89,7 @@</div><div class='ctx'> #define TMDMAE	BIT(0)	/* DMA Master Transmitted Enable */</div><div class='ctx'> </div><div class='ctx'> /* ICCCR2 */</div><div class='add'>+#define FMPE	BIT(7)	/* Fast Mode Plus Enable */</div><div class='ctx'> #define CDFD	BIT(2)	/* CDF Disable */</div><div class='ctx'> #define HLSE	BIT(1)	/* HIGH/LOW Separate Control Enable */</div><div class='ctx'> #define SME	BIT(0)	/* SCL Mask Enable */</div><div class='hunk'>@@ -122,16 +123,18 @@</div><div class='ctx'> #define ID_NACK			BIT(4)</div><div class='ctx'> #define ID_EPROTO		BIT(5)</div><div class='ctx'> /* persistent flags */</div><div class='add'>+#define ID_P_FMPLUS		BIT(27)</div><div class='ctx'> #define ID_P_NOT_ATOMIC		BIT(28)</div><div class='ctx'> #define ID_P_HOST_NOTIFY	BIT(29)</div><div class='ctx'> #define ID_P_NO_RXDMA		BIT(30) /* HW forbids RXDMA sometimes */</div><div class='ctx'> #define ID_P_PM_BLOCKED		BIT(31)</div><div class='del'>-#define ID_P_MASK		GENMASK(31, 28)</div><div class='add'>+#define ID_P_MASK		GENMASK(31, 27)</div><div class='ctx'> </div><div class='ctx'> enum rcar_i2c_type {</div><div class='ctx'> 	I2C_RCAR_GEN1,</div><div class='ctx'> 	I2C_RCAR_GEN2,</div><div class='ctx'> 	I2C_RCAR_GEN3,</div><div class='add'>+	I2C_RCAR_GEN4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct rcar_i2c_priv {</div><div class='hunk'>@@ -148,6 +151,7 @@ struct rcar_i2c_priv {</div><div class='ctx'> 	u32 icccr;</div><div class='ctx'> 	u16 schd;</div><div class='ctx'> 	u16 scld;</div><div class='add'>+	u8 smd;</div><div class='ctx'> 	u8 recovery_icmcr;	/* protected by adapter lock */</div><div class='ctx'> 	enum rcar_i2c_type devtype;</div><div class='ctx'> 	struct i2c_client *slave;</div><div class='hunk'>@@ -239,9 +243,14 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)</div><div class='ctx'> 	if (priv-&gt;devtype &lt; I2C_RCAR_GEN3) {</div><div class='ctx'> 		rcar_i2c_write(priv, ICCCR, priv-&gt;icccr);</div><div class='ctx'> 	} else {</div><div class='del'>-		rcar_i2c_write(priv, ICCCR2, CDFD | HLSE | SME);</div><div class='add'>+		u32 icccr2 = CDFD | HLSE | SME;</div><div class='add'>+</div><div class='add'>+		if (priv-&gt;flags &amp; ID_P_FMPLUS)</div><div class='add'>+			icccr2 |= FMPE;</div><div class='add'>+</div><div class='add'>+		rcar_i2c_write(priv, ICCCR2, icccr2);</div><div class='ctx'> 		rcar_i2c_write(priv, ICCCR, priv-&gt;icccr);</div><div class='del'>-		rcar_i2c_write(priv, ICMPR, RCAR_DEFAULT_SMD);</div><div class='add'>+		rcar_i2c_write(priv, ICMPR, priv-&gt;smd);</div><div class='ctx'> 		rcar_i2c_write(priv, ICHPR, priv-&gt;schd);</div><div class='ctx'> 		rcar_i2c_write(priv, ICLPR, priv-&gt;scld);</div><div class='ctx'> 		rcar_i2c_write(priv, ICFBSCR, TCYC17);</div><div class='hunk'>@@ -278,6 +287,7 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)</div><div class='ctx'> </div><div class='ctx'> 	/* Fall back to previously used values if not supplied */</div><div class='ctx'> 	i2c_parse_fw_timings(dev, &amp;t, false);</div><div class='add'>+	priv-&gt;smd = RCAR_DEFAULT_SMD;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * calculate SCL clock</div><div class='hunk'>@@ -303,6 +313,11 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)</div><div class='ctx'> 	if (cdf &gt;= 1U &lt;&lt; cdf_width)</div><div class='ctx'> 		goto err_no_val;</div><div class='ctx'> </div><div class='add'>+	if (t.bus_freq_hz &gt; I2C_MAX_FAST_MODE_FREQ &amp;&amp; priv-&gt;devtype &gt;= I2C_RCAR_GEN4)</div><div class='add'>+		priv-&gt;flags |= ID_P_FMPLUS;</div><div class='add'>+	else</div><div class='add'>+		priv-&gt;flags &amp;= ~ID_P_FMPLUS;</div><div class='add'>+</div><div class='ctx'> 	/* On Gen3+, we use cdf only for the filters, not as a SCL divider */</div><div class='ctx'> 	ick = rate / (priv-&gt;devtype &lt; I2C_RCAR_GEN3 ? (cdf + 1) : 1);</div><div class='ctx'> </div><div class='hunk'>@@ -344,30 +359,30 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)</div><div class='ctx'> 		 * x as a base value for the SCLD/SCHD ratio:</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp])</div><div class='del'>-		 * SCL = clkp / (8 + 2 * RCAR_DEFAULT_SMD + RCAR_SCLD_RATIO * x</div><div class='add'>+		 * SCL = clkp / (8 + 2 * SMD + RCAR_SCLD_RATIO * x</div><div class='ctx'> 		 *		 + RCAR_SCHD_RATIO * x + F[...])</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO</div><div class='del'>-		 * and:  smd = RCAR_DEFAULT_SMD</div><div class='ctx'> 		 *</div><div class='ctx'> 		 * SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...])</div><div class='ctx'> 		 * 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL</div><div class='ctx'> 		 * x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio</div><div class='ctx'> 		 */</div><div class='ctx'> 		x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1);</div><div class='del'>-		x = DIV_ROUND_UP(x - 8 - 2 * RCAR_DEFAULT_SMD - round, sum_ratio);</div><div class='del'>-		scl = rate / (8 + 2 * RCAR_DEFAULT_SMD + sum_ratio * x + round);</div><div class='add'>+		x = DIV_ROUND_UP(x - 8 - 2 * priv-&gt;smd - round, sum_ratio);</div><div class='add'>+		scl = rate / (8 + 2 * priv-&gt;smd + sum_ratio * x + round);</div><div class='ctx'> </div><div class='del'>-		/* Bail out if values don't fit into 16 bit or SMD became too large */</div><div class='del'>-		if (x * RCAR_SCLD_RATIO &gt; 0xffff || RCAR_DEFAULT_SMD &gt; x * RCAR_SCHD_RATIO)</div><div class='add'>+		if (x == 0 || x * RCAR_SCLD_RATIO &gt; 0xffff)</div><div class='ctx'> 			goto err_no_val;</div><div class='ctx'> </div><div class='ctx'> 		priv-&gt;icccr = cdf;</div><div class='ctx'> 		priv-&gt;schd = RCAR_SCHD_RATIO * x;</div><div class='ctx'> 		priv-&gt;scld = RCAR_SCLD_RATIO * x;</div><div class='add'>+		if (priv-&gt;smd &gt;= priv-&gt;schd)</div><div class='add'>+			priv-&gt;smd = priv-&gt;schd - 1;</div><div class='ctx'> </div><div class='del'>-		dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u\n",</div><div class='del'>-			scl, t.bus_freq_hz, rate, round, cdf, priv-&gt;schd, priv-&gt;scld);</div><div class='add'>+		dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u SMD %u\n",</div><div class='add'>+			scl, t.bus_freq_hz, rate, round, cdf, priv-&gt;schd, priv-&gt;scld, priv-&gt;smd);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -431,8 +446,8 @@ static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)</div><div class='ctx'> 	dma_unmap_single(chan-&gt;device-&gt;dev, sg_dma_address(&amp;priv-&gt;sg),</div><div class='ctx'> 			 sg_dma_len(&amp;priv-&gt;sg), priv-&gt;dma_direction);</div><div class='ctx'> </div><div class='del'>-	/* Gen3 can only do one RXDMA per transfer and we just completed it */</div><div class='del'>-	if (priv-&gt;devtype == I2C_RCAR_GEN3 &amp;&amp;</div><div class='add'>+	/* Gen3+ can only do one RXDMA per transfer and we just completed it */</div><div class='add'>+	if (priv-&gt;devtype &gt;= I2C_RCAR_GEN3 &amp;&amp;</div><div class='ctx'> 	    priv-&gt;dma_direction == DMA_FROM_DEVICE)</div><div class='ctx'> 		priv-&gt;flags |= ID_P_NO_RXDMA;</div><div class='ctx'> </div><div class='hunk'>@@ -886,8 +901,8 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	/* Gen3 needs a reset before allowing RXDMA once */</div><div class='del'>-	if (priv-&gt;devtype == I2C_RCAR_GEN3) {</div><div class='add'>+	/* Gen3+ needs a reset. That also allows RXDMA once */</div><div class='add'>+	if (priv-&gt;devtype &gt;= I2C_RCAR_GEN3) {</div><div class='ctx'> 		priv-&gt;flags &amp;= ~ID_P_NO_RXDMA;</div><div class='ctx'> 		ret = rcar_i2c_do_reset(priv);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -1072,10 +1087,12 @@ static const struct of_device_id rcar_i2c_dt_ids[] = {</div><div class='ctx'> 	{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },</div><div class='ctx'> 	{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },</div><div class='ctx'> 	{ .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },</div><div class='add'>+	/* S4 has no FM+ bit */</div><div class='add'>+	{ .compatible = "renesas,i2c-r8a779f0", .data = (void *)I2C_RCAR_GEN3 },</div><div class='ctx'> 	{ .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },</div><div class='ctx'> 	{ .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },</div><div class='ctx'> 	{ .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },</div><div class='del'>-	{ .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN3 },</div><div class='add'>+	{ .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN4 },</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);</div><div class='hunk'>@@ -1151,7 +1168,7 @@ static int rcar_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (of_property_read_bool(dev-&gt;of_node, "smbus"))</div><div class='ctx'> 		priv-&gt;flags |= ID_P_HOST_NOTIFY;</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;devtype == I2C_RCAR_GEN3) {</div><div class='add'>+	if (priv-&gt;devtype &gt;= I2C_RCAR_GEN3) {</div><div class='ctx'> 		priv-&gt;rstc = devm_reset_control_get_exclusive(&amp;pdev-&gt;dev, NULL);</div><div class='ctx'> 		if (IS_ERR(priv-&gt;rstc)) {</div><div class='ctx'> 			ret = PTR_ERR(priv-&gt;rstc);</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c<br/>index a044ca0c35a1..086fdf262e7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-rk3x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-rk3x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-rk3x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-rk3x.c</a></div><div class='hunk'>@@ -178,6 +178,7 @@ struct rk3x_i2c_soc_data {</div><div class='ctx'>  * @clk: function clk for rk3399 or function &amp; Bus clks for others</div><div class='ctx'>  * @pclk: Bus clk for rk3399</div><div class='ctx'>  * @clk_rate_nb: i2c clk rate change notify</div><div class='add'>+ * @irq: irq number</div><div class='ctx'>  * @t: I2C known timing information</div><div class='ctx'>  * @lock: spinlock for the i2c bus</div><div class='ctx'>  * @wait: the waitqueue to wait for i2c transfer</div><div class='hunk'>@@ -200,6 +201,7 @@ struct rk3x_i2c {</div><div class='ctx'> 	struct clk *clk;</div><div class='ctx'> 	struct clk *pclk;</div><div class='ctx'> 	struct notifier_block clk_rate_nb;</div><div class='add'>+	int irq;</div><div class='ctx'> </div><div class='ctx'> 	/* Settings */</div><div class='ctx'> 	struct i2c_timings t;</div><div class='hunk'>@@ -1087,13 +1089,18 @@ static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,</div><div class='ctx'> </div><div class='ctx'> 		spin_unlock_irqrestore(&amp;i2c-&gt;lock, flags);</div><div class='ctx'> </div><div class='del'>-		rk3x_i2c_start(i2c);</div><div class='del'>-</div><div class='ctx'> 		if (!polling) {</div><div class='add'>+			rk3x_i2c_start(i2c);</div><div class='add'>+</div><div class='ctx'> 			timeout = wait_event_timeout(i2c-&gt;wait, !i2c-&gt;busy,</div><div class='ctx'> 						     msecs_to_jiffies(WAIT_TIMEOUT));</div><div class='ctx'> 		} else {</div><div class='add'>+			disable_irq(i2c-&gt;irq);</div><div class='add'>+			rk3x_i2c_start(i2c);</div><div class='add'>+</div><div class='ctx'> 			timeout = rk3x_i2c_wait_xfer_poll(i2c);</div><div class='add'>+</div><div class='add'>+			enable_irq(i2c-&gt;irq);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		spin_lock_irqsave(&amp;i2c-&gt;lock, flags);</div><div class='hunk'>@@ -1288,8 +1295,12 @@ static int rk3x_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		/* 27+i: write mask, 11+i: value */</div><div class='del'>-		value = BIT(27 + bus_nr) | BIT(11 + bus_nr);</div><div class='add'>+		/* rv1126 i2c2 uses non-sequential write mask 20, value 4 */</div><div class='add'>+		if (i2c-&gt;soc_data == &amp;rv1126_soc_data &amp;&amp; bus_nr == 2)</div><div class='add'>+			value = BIT(20) | BIT(4);</div><div class='add'>+		else</div><div class='add'>+			/* 27+i: write mask, 11+i: value */</div><div class='add'>+			value = BIT(27 + bus_nr) | BIT(11 + bus_nr);</div><div class='ctx'> </div><div class='ctx'> 		ret = regmap_write(grf, i2c-&gt;soc_data-&gt;grf_offset, value);</div><div class='ctx'> 		if (ret != 0) {</div><div class='hunk'>@@ -1310,6 +1321,8 @@ static int rk3x_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	i2c-&gt;irq = irq;</div><div class='add'>+</div><div class='ctx'> 	platform_set_drvdata(pdev, i2c);</div><div class='ctx'> </div><div class='ctx'> 	if (i2c-&gt;soc_data-&gt;calc_timings == rk3x_i2c_v0_calc_timings) {</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c<br/>index c56886af724e..275f7c42165c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-s3c2410.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-s3c2410.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-s3c2410.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-s3c2410.c</a></div><div class='hunk'>@@ -76,6 +76,7 @@</div><div class='ctx'> #define QUIRK_HDMIPHY		(1 &lt;&lt; 1)</div><div class='ctx'> #define QUIRK_NO_GPIO		(1 &lt;&lt; 2)</div><div class='ctx'> #define QUIRK_POLL		(1 &lt;&lt; 3)</div><div class='add'>+#define QUIRK_ATOMIC		(1 &lt;&lt; 4)</div><div class='ctx'> </div><div class='ctx'> /* Max time to wait for bus to become idle after a xfer (in us) */</div><div class='ctx'> #define S3C2410_IDLE_TIMEOUT	5000</div><div class='hunk'>@@ -174,7 +175,7 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		i2c-&gt;msg_idx = ret;</div><div class='ctx'> </div><div class='del'>-	if (!(i2c-&gt;quirks &amp; QUIRK_POLL))</div><div class='add'>+	if (!(i2c-&gt;quirks &amp; (QUIRK_POLL | QUIRK_ATOMIC)))</div><div class='ctx'> 		wake_up(&amp;i2c-&gt;wait);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -216,8 +217,17 @@ static bool is_ack(struct s3c24xx_i2c *i2c)</div><div class='ctx'> 	int tries;</div><div class='ctx'> </div><div class='ctx'> 	for (tries = 50; tries; --tries) {</div><div class='del'>-		if (readl(i2c-&gt;regs + S3C2410_IICCON)</div><div class='del'>-			&amp; S3C2410_IICCON_IRQPEND) {</div><div class='add'>+		unsigned long tmp = readl(i2c-&gt;regs + S3C2410_IICCON);</div><div class='add'>+</div><div class='add'>+		if (!(tmp &amp; S3C2410_IICCON_ACKEN)) {</div><div class='add'>+			/*</div><div class='add'>+			 * Wait a bit for the bus to stabilize,</div><div class='add'>+			 * delay estimated experimentally.</div><div class='add'>+			 */</div><div class='add'>+			usleep_range(100, 200);</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		if (tmp &amp; S3C2410_IICCON_IRQPEND) {</div><div class='ctx'> 			if (!(readl(i2c-&gt;regs + S3C2410_IICSTAT)</div><div class='ctx'> 				&amp; S3C2410_IICSTAT_LASTBIT))</div><div class='ctx'> 				return true;</div><div class='hunk'>@@ -270,16 +280,6 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,</div><div class='ctx'> </div><div class='ctx'> 	stat |= S3C2410_IICSTAT_START;</div><div class='ctx'> 	writel(stat, i2c-&gt;regs + S3C2410_IICSTAT);</div><div class='del'>-</div><div class='del'>-	if (i2c-&gt;quirks &amp; QUIRK_POLL) {</div><div class='del'>-		while ((i2c-&gt;msg_num != 0) &amp;&amp; is_ack(i2c)) {</div><div class='del'>-			i2c_s3c_irq_nextbyte(i2c, stat);</div><div class='del'>-			stat = readl(i2c-&gt;regs + S3C2410_IICSTAT);</div><div class='del'>-</div><div class='del'>-			if (stat &amp; S3C2410_IICSTAT_ARBITR)</div><div class='del'>-				dev_err(i2c-&gt;dev, "deal with arbitration loss\n");</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)</div><div class='hunk'>@@ -685,7 +685,7 @@ static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)</div><div class='ctx'> static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,</div><div class='ctx'> 			      struct i2c_msg *msgs, int num)</div><div class='ctx'> {</div><div class='del'>-	unsigned long timeout;</div><div class='add'>+	unsigned long timeout = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = s3c24xx_i2c_set_master(i2c);</div><div class='hunk'>@@ -704,17 +704,20 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,</div><div class='ctx'> 	s3c24xx_i2c_enable_irq(i2c);</div><div class='ctx'> 	s3c24xx_i2c_message_start(i2c, msgs);</div><div class='ctx'> </div><div class='del'>-	if (i2c-&gt;quirks &amp; QUIRK_POLL) {</div><div class='del'>-		ret = i2c-&gt;msg_idx;</div><div class='add'>+	if (i2c-&gt;quirks &amp; (QUIRK_POLL | QUIRK_ATOMIC)) {</div><div class='add'>+		while ((i2c-&gt;msg_num != 0) &amp;&amp; is_ack(i2c)) {</div><div class='add'>+			unsigned long stat = readl(i2c-&gt;regs + S3C2410_IICSTAT);</div><div class='ctx'> </div><div class='del'>-		if (ret != num)</div><div class='del'>-			dev_dbg(i2c-&gt;dev, "incomplete xfer (%d)\n", ret);</div><div class='add'>+			i2c_s3c_irq_nextbyte(i2c, stat);</div><div class='ctx'> </div><div class='del'>-		goto out;</div><div class='add'>+			stat = readl(i2c-&gt;regs + S3C2410_IICSTAT);</div><div class='add'>+			if (stat &amp; S3C2410_IICSTAT_ARBITR)</div><div class='add'>+				dev_err(i2c-&gt;dev, "deal with arbitration loss\n");</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		timeout = wait_event_timeout(i2c-&gt;wait, i2c-&gt;msg_num == 0, HZ * 5);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	timeout = wait_event_timeout(i2c-&gt;wait, i2c-&gt;msg_num == 0, HZ * 5);</div><div class='del'>-</div><div class='ctx'> 	ret = i2c-&gt;msg_idx;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -773,6 +776,21 @@ static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,</div><div class='ctx'> 	return -EREMOTEIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int s3c24xx_i2c_xfer_atomic(struct i2c_adapter *adap,</div><div class='add'>+				   struct i2c_msg *msgs, int num)</div><div class='add'>+{</div><div class='add'>+	struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap-&gt;algo_data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	disable_irq(i2c-&gt;irq);</div><div class='add'>+	i2c-&gt;quirks |= QUIRK_ATOMIC;</div><div class='add'>+	ret = s3c24xx_i2c_xfer(adap, msgs, num);</div><div class='add'>+	i2c-&gt;quirks &amp;= ~QUIRK_ATOMIC;</div><div class='add'>+	enable_irq(i2c-&gt;irq);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* declare our i2c functionality */</div><div class='ctx'> static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)</div><div class='ctx'> {</div><div class='hunk'>@@ -783,6 +801,7 @@ static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)</div><div class='ctx'> /* i2c bus registration info */</div><div class='ctx'> static const struct i2c_algorithm s3c24xx_i2c_algorithm = {</div><div class='ctx'> 	.master_xfer		= s3c24xx_i2c_xfer,</div><div class='add'>+	.master_xfer_atomic     = s3c24xx_i2c_xfer_atomic,</div><div class='ctx'> 	.functionality		= s3c24xx_i2c_func,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-scmi.c b/drivers/i2c/busses/i2c-scmi.c<br/>index 421735acfa14..d7af8e0d7599 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-scmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-scmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-scmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-scmi.c</a></div><div class='hunk'>@@ -385,7 +385,7 @@ static int smbus_cmi_probe(struct platform_device *device)</div><div class='ctx'> 	smbus_cmi-&gt;adapter.owner = THIS_MODULE;</div><div class='ctx'> 	smbus_cmi-&gt;adapter.algo = &amp;acpi_smbus_cmi_algorithm;</div><div class='ctx'> 	smbus_cmi-&gt;adapter.algo_data = smbus_cmi;</div><div class='del'>-	smbus_cmi-&gt;adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	smbus_cmi-&gt;adapter.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	smbus_cmi-&gt;adapter.dev.parent = &amp;device-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = i2c_add_adapter(&amp;smbus_cmi-&gt;adapter);</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-sh7760.c b/drivers/i2c/busses/i2c-sh7760.c<br/>index 1ad2a26156d1..8a043f5fca1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sh7760.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-sh7760.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sh7760.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sh7760.c</a></div><div class='hunk'>@@ -477,7 +477,7 @@ static int sh7760_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	id-&gt;adap.nr = pdev-&gt;id;</div><div class='ctx'> 	id-&gt;adap.algo = &amp;sh7760_i2c_algo;</div><div class='del'>-	id-&gt;adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	id-&gt;adap.class = I2C_CLASS_HWMON;</div><div class='ctx'> 	id-&gt;adap.retries = 3;</div><div class='ctx'> 	id-&gt;adap.algo_data = id;</div><div class='ctx'> 	id-&gt;adap.dev.parent = &amp;pdev-&gt;dev;</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c<br/>index 8f71f01cb169..49f8f4f1b0f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sibyte.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-sibyte.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sibyte.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sibyte.c</a></div><div class='hunk'>@@ -142,7 +142,7 @@ static struct i2c_algo_sibyte_data sibyte_board_data[2] = {</div><div class='ctx'> static struct i2c_adapter sibyte_board_adapter[2] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.owner		= THIS_MODULE,</div><div class='del'>-		.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+		.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 		.algo		= NULL,</div><div class='ctx'> 		.algo_data	= &amp;sibyte_board_data[0],</div><div class='ctx'> 		.nr		= 0,</div><div class='hunk'>@@ -150,7 +150,7 @@ static struct i2c_adapter sibyte_board_adapter[2] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.owner		= THIS_MODULE,</div><div class='del'>-		.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+		.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 		.algo		= NULL,</div><div class='ctx'> 		.algo_data	= &amp;sibyte_board_data[1],</div><div class='ctx'> 		.nr		= 1,</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c<br/>index 486f1e9dfb74..32476dc10ad6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis5595.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-sis5595.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis5595.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis5595.c</a></div><div class='hunk'>@@ -353,7 +353,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter sis5595_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-sis630.c b/drivers/i2c/busses/i2c-sis630.c<br/>index 87d56250d78a..3505cf29cedd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis630.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-sis630.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis630.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis630.c</a></div><div class='hunk'>@@ -493,7 +493,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter sis630_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> 	.retries	= 3</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-sis96x.c b/drivers/i2c/busses/i2c-sis96x.c<br/>index cde8003985a5..77529dda6fcd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis96x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-sis96x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-sis96x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-sis96x.c</a></div><div class='hunk'>@@ -228,7 +228,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter sis96x_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c<br/>index 983509936727..01210452216b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-stm32f7.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-stm32f7.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-stm32f7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-stm32f7.c</a></div><div class='hunk'>@@ -50,6 +50,7 @@</div><div class='ctx'> #define STM32F7_I2C_TXDR			0x28</div><div class='ctx'> </div><div class='ctx'> /* STM32F7 I2C control 1 */</div><div class='add'>+#define STM32_I2C_CR1_FMP			BIT(24)</div><div class='ctx'> #define STM32F7_I2C_CR1_PECEN			BIT(23)</div><div class='ctx'> #define STM32F7_I2C_CR1_ALERTEN			BIT(22)</div><div class='ctx'> #define STM32F7_I2C_CR1_SMBHEN			BIT(20)</div><div class='hunk'>@@ -226,6 +227,8 @@ struct stm32f7_i2c_spec {</div><div class='ctx'>  * @rise_time: Rise time (ns)</div><div class='ctx'>  * @fall_time: Fall time (ns)</div><div class='ctx'>  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register</div><div class='add'>+ * @single_it_line: Only a single IT line is used for both events/errors</div><div class='add'>+ * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1</div><div class='ctx'>  */</div><div class='ctx'> struct stm32f7_i2c_setup {</div><div class='ctx'> 	u32 speed_freq;</div><div class='hunk'>@@ -233,6 +236,8 @@ struct stm32f7_i2c_setup {</div><div class='ctx'> 	u32 rise_time;</div><div class='ctx'> 	u32 fall_time;</div><div class='ctx'> 	u32 fmp_clr_offset;</div><div class='add'>+	bool single_it_line;</div><div class='add'>+	bool fmp_cr1_bit;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -418,6 +423,13 @@ static const struct stm32f7_i2c_setup stm32mp13_setup = {</div><div class='ctx'> 	.fmp_clr_offset = 0x4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct stm32f7_i2c_setup stm32mp25_setup = {</div><div class='add'>+	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,</div><div class='add'>+	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,</div><div class='add'>+	.single_it_line = true,</div><div class='add'>+	.fmp_cr1_bit = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)</div><div class='ctx'> {</div><div class='ctx'> 	writel_relaxed(readl_relaxed(reg) | mask, reg);</div><div class='hunk'>@@ -1419,15 +1431,13 @@ static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)</div><div class='ctx'> 	return i == busy;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)</div><div class='add'>+static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status)</div><div class='ctx'> {</div><div class='ctx'> 	void __iomem *base = i2c_dev-&gt;base;</div><div class='del'>-	u32 cr2, status, mask;</div><div class='add'>+	u32 cr2, mask;</div><div class='ctx'> 	u8 val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	status = readl_relaxed(i2c_dev-&gt;base + STM32F7_I2C_ISR);</div><div class='del'>-</div><div class='ctx'> 	/* Slave transmitter mode */</div><div class='ctx'> 	if (status &amp; STM32F7_I2C_ISR_TXIS) {</div><div class='ctx'> 		i2c_slave_event(i2c_dev-&gt;slave_running,</div><div class='hunk'>@@ -1494,23 +1504,81 @@ static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)</div><div class='add'>+static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status)</div><div class='ctx'> {</div><div class='del'>-	struct stm32f7_i2c_dev *i2c_dev = data;</div><div class='ctx'> 	struct stm32f7_i2c_msg *f7_msg = &amp;i2c_dev-&gt;f7_msg;</div><div class='del'>-	struct stm32_i2c_dma *dma = i2c_dev-&gt;dma;</div><div class='add'>+	u16 addr = f7_msg-&gt;addr;</div><div class='ctx'> 	void __iomem *base = i2c_dev-&gt;base;</div><div class='del'>-	u32 status, mask;</div><div class='del'>-	int ret = IRQ_HANDLED;</div><div class='add'>+	struct device *dev = i2c_dev-&gt;dev;</div><div class='add'>+	struct stm32_i2c_dma *dma = i2c_dev-&gt;dma;</div><div class='ctx'> </div><div class='del'>-	/* Check if the interrupt if for a slave device */</div><div class='del'>-	if (!i2c_dev-&gt;master_mode) {</div><div class='del'>-		ret = stm32f7_i2c_slave_isr_event(i2c_dev);</div><div class='del'>-		return ret;</div><div class='add'>+	/* Bus error */</div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_BERR) {</div><div class='add'>+		dev_err(dev, "Bus error accessing addr 0x%x\n", addr);</div><div class='add'>+		writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);</div><div class='add'>+		stm32f7_i2c_release_bus(&amp;i2c_dev-&gt;adap);</div><div class='add'>+		f7_msg-&gt;result = -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Arbitration loss */</div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_ARLO) {</div><div class='add'>+		dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr);</div><div class='add'>+		writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);</div><div class='add'>+		f7_msg-&gt;result = -EAGAIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_PECERR) {</div><div class='add'>+		dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr);</div><div class='add'>+		writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);</div><div class='add'>+		f7_msg-&gt;result = -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_ALERT) {</div><div class='add'>+		dev_dbg(dev, "SMBus alert received\n");</div><div class='add'>+		writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);</div><div class='add'>+		i2c_handle_smbus_alert(i2c_dev-&gt;alert-&gt;ara);</div><div class='add'>+		return IRQ_HANDLED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!i2c_dev-&gt;slave_running) {</div><div class='add'>+		u32 mask;</div><div class='add'>+		/* Disable interrupts */</div><div class='add'>+		if (stm32f7_i2c_is_slave_registered(i2c_dev))</div><div class='add'>+			mask = STM32F7_I2C_XFER_IRQ_MASK;</div><div class='add'>+		else</div><div class='add'>+			mask = STM32F7_I2C_ALL_IRQ_MASK;</div><div class='add'>+		stm32f7_i2c_disable_irq(i2c_dev, mask);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Disable dma */</div><div class='add'>+	if (i2c_dev-&gt;use_dma) {</div><div class='add'>+		stm32f7_i2c_disable_dma_req(i2c_dev);</div><div class='add'>+		dmaengine_terminate_async(dma-&gt;chan_using);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	i2c_dev-&gt;master_mode = false;</div><div class='add'>+	complete(&amp;i2c_dev-&gt;complete);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\</div><div class='add'>+			    STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT)</div><div class='add'>+static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct stm32f7_i2c_dev *i2c_dev = data;</div><div class='add'>+	u32 status;</div><div class='add'>+</div><div class='ctx'> 	status = readl_relaxed(i2c_dev-&gt;base + STM32F7_I2C_ISR);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Check if the interrupt is for a slave device or related</div><div class='add'>+	 * to errors flags (in case of single it line mode)</div><div class='add'>+	 */</div><div class='add'>+	if (!i2c_dev-&gt;master_mode ||</div><div class='add'>+	    (i2c_dev-&gt;setup.single_it_line &amp;&amp; (status &amp; STM32F7_ERR_EVENTS)))</div><div class='add'>+		return IRQ_WAKE_THREAD;</div><div class='add'>+</div><div class='ctx'> 	/* Tx empty */</div><div class='ctx'> 	if (status &amp; STM32F7_I2C_ISR_TXIS)</div><div class='ctx'> 		stm32f7_i2c_write_tx_data(i2c_dev);</div><div class='hunk'>@@ -1519,6 +1587,33 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)</div><div class='ctx'> 	if (status &amp; STM32F7_I2C_ISR_RXNE)</div><div class='ctx'> 		stm32f7_i2c_read_rx_data(i2c_dev);</div><div class='ctx'> </div><div class='add'>+	/* Wake up the thread if other flags are raised */</div><div class='add'>+	if (status &amp;</div><div class='add'>+	    (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF |</div><div class='add'>+	     STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR))</div><div class='add'>+		return IRQ_WAKE_THREAD;</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct stm32f7_i2c_dev *i2c_dev = data;</div><div class='add'>+	struct stm32f7_i2c_msg *f7_msg = &amp;i2c_dev-&gt;f7_msg;</div><div class='add'>+	struct stm32_i2c_dma *dma = i2c_dev-&gt;dma;</div><div class='add'>+	void __iomem *base = i2c_dev-&gt;base;</div><div class='add'>+	u32 status, mask;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	status = readl_relaxed(i2c_dev-&gt;base + STM32F7_I2C_ISR);</div><div class='add'>+</div><div class='add'>+	if (!i2c_dev-&gt;master_mode)</div><div class='add'>+		return stm32f7_i2c_slave_isr_event(i2c_dev, status);</div><div class='add'>+</div><div class='add'>+	/* Handle errors in case of this handler is used for events/errors */</div><div class='add'>+	if (i2c_dev-&gt;setup.single_it_line &amp;&amp; (status &amp; STM32F7_ERR_EVENTS))</div><div class='add'>+		return stm32f7_i2c_handle_isr_errs(i2c_dev, status);</div><div class='add'>+</div><div class='ctx'> 	/* NACK received */</div><div class='ctx'> 	if (status &amp; STM32F7_I2C_ISR_NACKF) {</div><div class='ctx'> 		dev_dbg(i2c_dev-&gt;dev, "&lt;%s&gt;: Receive NACK (addr %x)\n",</div><div class='hunk'>@@ -1531,33 +1626,28 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)</div><div class='ctx'> 		f7_msg-&gt;result = -ENXIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* STOP detection flag */</div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_STOPF) {</div><div class='del'>-		/* Disable interrupts */</div><div class='del'>-		if (stm32f7_i2c_is_slave_registered(i2c_dev))</div><div class='del'>-			mask = STM32F7_I2C_XFER_IRQ_MASK;</div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_TCR) {</div><div class='add'>+		if (f7_msg-&gt;smbus)</div><div class='add'>+			stm32f7_i2c_smbus_reload(i2c_dev);</div><div class='ctx'> 		else</div><div class='del'>-			mask = STM32F7_I2C_ALL_IRQ_MASK;</div><div class='del'>-		stm32f7_i2c_disable_irq(i2c_dev, mask);</div><div class='del'>-</div><div class='del'>-		/* Clear STOP flag */</div><div class='del'>-		writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);</div><div class='del'>-</div><div class='del'>-		if (i2c_dev-&gt;use_dma &amp;&amp; !f7_msg-&gt;result) {</div><div class='del'>-			ret = IRQ_WAKE_THREAD;</div><div class='del'>-		} else {</div><div class='del'>-			i2c_dev-&gt;master_mode = false;</div><div class='del'>-			complete(&amp;i2c_dev-&gt;complete);</div><div class='del'>-		}</div><div class='add'>+			stm32f7_i2c_reload(i2c_dev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Transfer complete */</div><div class='ctx'> 	if (status &amp; STM32F7_I2C_ISR_TC) {</div><div class='add'>+		/* Wait for dma transfer completion before sending next message */</div><div class='add'>+		if (i2c_dev-&gt;use_dma &amp;&amp; !f7_msg-&gt;result) {</div><div class='add'>+			ret = wait_for_completion_timeout(&amp;i2c_dev-&gt;dma-&gt;dma_complete, HZ);</div><div class='add'>+			if (!ret) {</div><div class='add'>+				dev_dbg(i2c_dev-&gt;dev, "&lt;%s&gt;: Timed out\n", __func__);</div><div class='add'>+				stm32f7_i2c_disable_dma_req(i2c_dev);</div><div class='add'>+				dmaengine_terminate_async(dma-&gt;chan_using);</div><div class='add'>+				f7_msg-&gt;result = -ETIMEDOUT;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		if (f7_msg-&gt;stop) {</div><div class='ctx'> 			mask = STM32F7_I2C_CR2_STOP;</div><div class='ctx'> 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);</div><div class='del'>-		} else if (i2c_dev-&gt;use_dma &amp;&amp; !f7_msg-&gt;result) {</div><div class='del'>-			ret = IRQ_WAKE_THREAD;</div><div class='ctx'> 		} else if (f7_msg-&gt;smbus) {</div><div class='ctx'> 			stm32f7_i2c_smbus_rep_start(i2c_dev);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1567,47 +1657,18 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_TCR) {</div><div class='del'>-		if (f7_msg-&gt;smbus)</div><div class='del'>-			stm32f7_i2c_smbus_reload(i2c_dev);</div><div class='add'>+	/* STOP detection flag */</div><div class='add'>+	if (status &amp; STM32F7_I2C_ISR_STOPF) {</div><div class='add'>+		/* Disable interrupts */</div><div class='add'>+		if (stm32f7_i2c_is_slave_registered(i2c_dev))</div><div class='add'>+			mask = STM32F7_I2C_XFER_IRQ_MASK;</div><div class='ctx'> 		else</div><div class='del'>-			stm32f7_i2c_reload(i2c_dev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)</div><div class='del'>-{</div><div class='del'>-	struct stm32f7_i2c_dev *i2c_dev = data;</div><div class='del'>-	struct stm32f7_i2c_msg *f7_msg = &amp;i2c_dev-&gt;f7_msg;</div><div class='del'>-	struct stm32_i2c_dma *dma = i2c_dev-&gt;dma;</div><div class='del'>-	u32 status;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Wait for dma transfer completion before sending next message or</div><div class='del'>-	 * notity the end of xfer to the client</div><div class='del'>-	 */</div><div class='del'>-	ret = wait_for_completion_timeout(&amp;i2c_dev-&gt;dma-&gt;dma_complete, HZ);</div><div class='del'>-	if (!ret) {</div><div class='del'>-		dev_dbg(i2c_dev-&gt;dev, "&lt;%s&gt;: Timed out\n", __func__);</div><div class='del'>-		stm32f7_i2c_disable_dma_req(i2c_dev);</div><div class='del'>-		dmaengine_terminate_async(dma-&gt;chan_using);</div><div class='del'>-		f7_msg-&gt;result = -ETIMEDOUT;</div><div class='del'>-	}</div><div class='add'>+			mask = STM32F7_I2C_ALL_IRQ_MASK;</div><div class='add'>+		stm32f7_i2c_disable_irq(i2c_dev, mask);</div><div class='ctx'> </div><div class='del'>-	status = readl_relaxed(i2c_dev-&gt;base + STM32F7_I2C_ISR);</div><div class='add'>+		/* Clear STOP flag */</div><div class='add'>+		writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);</div><div class='ctx'> </div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_TC) {</div><div class='del'>-		if (f7_msg-&gt;smbus) {</div><div class='del'>-			stm32f7_i2c_smbus_rep_start(i2c_dev);</div><div class='del'>-		} else {</div><div class='del'>-			i2c_dev-&gt;msg_id++;</div><div class='del'>-			i2c_dev-&gt;msg++;</div><div class='del'>-			stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev-&gt;msg);</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='ctx'> 		i2c_dev-&gt;master_mode = false;</div><div class='ctx'> 		complete(&amp;i2c_dev-&gt;complete);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1615,68 +1676,14 @@ static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)</div><div class='add'>+static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct stm32f7_i2c_dev *i2c_dev = data;</div><div class='del'>-	struct stm32f7_i2c_msg *f7_msg = &amp;i2c_dev-&gt;f7_msg;</div><div class='del'>-	void __iomem *base = i2c_dev-&gt;base;</div><div class='del'>-	struct device *dev = i2c_dev-&gt;dev;</div><div class='del'>-	struct stm32_i2c_dma *dma = i2c_dev-&gt;dma;</div><div class='ctx'> 	u32 status;</div><div class='ctx'> </div><div class='ctx'> 	status = readl_relaxed(i2c_dev-&gt;base + STM32F7_I2C_ISR);</div><div class='ctx'> </div><div class='del'>-	/* Bus error */</div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_BERR) {</div><div class='del'>-		dev_err(dev, "&lt;%s&gt;: Bus error accessing addr 0x%x\n",</div><div class='del'>-			__func__, f7_msg-&gt;addr);</div><div class='del'>-		writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);</div><div class='del'>-		stm32f7_i2c_release_bus(&amp;i2c_dev-&gt;adap);</div><div class='del'>-		f7_msg-&gt;result = -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Arbitration loss */</div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_ARLO) {</div><div class='del'>-		dev_dbg(dev, "&lt;%s&gt;: Arbitration loss accessing addr 0x%x\n",</div><div class='del'>-			__func__, f7_msg-&gt;addr);</div><div class='del'>-		writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);</div><div class='del'>-		f7_msg-&gt;result = -EAGAIN;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_PECERR) {</div><div class='del'>-		dev_err(dev, "&lt;%s&gt;: PEC error in reception accessing addr 0x%x\n",</div><div class='del'>-			__func__, f7_msg-&gt;addr);</div><div class='del'>-		writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);</div><div class='del'>-		f7_msg-&gt;result = -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; STM32F7_I2C_ISR_ALERT) {</div><div class='del'>-		dev_dbg(dev, "&lt;%s&gt;: SMBus alert received\n", __func__);</div><div class='del'>-		writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);</div><div class='del'>-		i2c_handle_smbus_alert(i2c_dev-&gt;alert-&gt;ara);</div><div class='del'>-		return IRQ_HANDLED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!i2c_dev-&gt;slave_running) {</div><div class='del'>-		u32 mask;</div><div class='del'>-		/* Disable interrupts */</div><div class='del'>-		if (stm32f7_i2c_is_slave_registered(i2c_dev))</div><div class='del'>-			mask = STM32F7_I2C_XFER_IRQ_MASK;</div><div class='del'>-		else</div><div class='del'>-			mask = STM32F7_I2C_ALL_IRQ_MASK;</div><div class='del'>-		stm32f7_i2c_disable_irq(i2c_dev, mask);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Disable dma */</div><div class='del'>-	if (i2c_dev-&gt;use_dma) {</div><div class='del'>-		stm32f7_i2c_disable_dma_req(i2c_dev);</div><div class='del'>-		dmaengine_terminate_async(dma-&gt;chan_using);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	i2c_dev-&gt;master_mode = false;</div><div class='del'>-	complete(&amp;i2c_dev-&gt;complete);</div><div class='del'>-</div><div class='del'>-	return IRQ_HANDLED;</div><div class='add'>+	return stm32f7_i2c_handle_isr_errs(i2c_dev, status);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)</div><div class='hunk'>@@ -2012,23 +2019,27 @@ static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)</div><div class='ctx'> static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,</div><div class='ctx'> 					  bool enable)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (i2c_dev-&gt;bus_rate &lt;= I2C_MAX_FAST_MODE_FREQ ||</div><div class='del'>-	    IS_ERR_OR_NULL(i2c_dev-&gt;regmap))</div><div class='add'>+	    (!i2c_dev-&gt;setup.fmp_cr1_bit &amp;&amp; IS_ERR_OR_NULL(i2c_dev-&gt;regmap)))</div><div class='ctx'> 		/* Optional */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (i2c_dev-&gt;fmp_sreg == i2c_dev-&gt;fmp_creg)</div><div class='del'>-		ret = regmap_update_bits(i2c_dev-&gt;regmap,</div><div class='del'>-					 i2c_dev-&gt;fmp_sreg,</div><div class='del'>-					 i2c_dev-&gt;fmp_mask,</div><div class='del'>-					 enable ? i2c_dev-&gt;fmp_mask : 0);</div><div class='del'>-	else</div><div class='del'>-		ret = regmap_write(i2c_dev-&gt;regmap,</div><div class='del'>-				   enable ? i2c_dev-&gt;fmp_sreg :</div><div class='del'>-					    i2c_dev-&gt;fmp_creg,</div><div class='del'>-				   i2c_dev-&gt;fmp_mask);</div><div class='add'>+	if (i2c_dev-&gt;setup.fmp_cr1_bit) {</div><div class='add'>+		if (enable)</div><div class='add'>+			stm32f7_i2c_set_bits(i2c_dev-&gt;base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);</div><div class='add'>+		else</div><div class='add'>+			stm32f7_i2c_clr_bits(i2c_dev-&gt;base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);</div><div class='add'>+	} else {</div><div class='add'>+		if (i2c_dev-&gt;fmp_sreg == i2c_dev-&gt;fmp_creg)</div><div class='add'>+			ret = regmap_update_bits(i2c_dev-&gt;regmap, i2c_dev-&gt;fmp_sreg,</div><div class='add'>+						 i2c_dev-&gt;fmp_mask, enable ? i2c_dev-&gt;fmp_mask : 0);</div><div class='add'>+		else</div><div class='add'>+			ret = regmap_write(i2c_dev-&gt;regmap,</div><div class='add'>+					   enable ? i2c_dev-&gt;fmp_sreg : i2c_dev-&gt;fmp_creg,</div><div class='add'>+					   i2c_dev-&gt;fmp_mask);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -2162,6 +2173,13 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (!i2c_dev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	setup = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (!setup) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Can't get device data\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	i2c_dev-&gt;setup = *setup;</div><div class='add'>+</div><div class='ctx'> 	i2c_dev-&gt;base = devm_platform_get_and_ioremap_resource(pdev, 0, &amp;res);</div><div class='ctx'> 	if (IS_ERR(i2c_dev-&gt;base))</div><div class='ctx'> 		return PTR_ERR(i2c_dev-&gt;base);</div><div class='hunk'>@@ -2171,10 +2189,6 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (irq_event &lt; 0)</div><div class='ctx'> 		return irq_event;</div><div class='ctx'> </div><div class='del'>-	irq_error = platform_get_irq(pdev, 1);</div><div class='del'>-	if (irq_error &lt; 0)</div><div class='del'>-		return irq_error;</div><div class='del'>-</div><div class='ctx'> 	i2c_dev-&gt;wakeup_src = of_property_read_bool(pdev-&gt;dev.of_node,</div><div class='ctx'> 						    "wakeup-source");</div><div class='ctx'> </div><div class='hunk'>@@ -2199,26 +2213,22 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 					stm32f7_i2c_isr_event_thread,</div><div class='ctx'> 					IRQF_ONESHOT,</div><div class='ctx'> 					pdev-&gt;name, i2c_dev);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to request irq event %i\n",</div><div class='del'>-			irq_event);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = devm_request_irq(&amp;pdev-&gt;dev, irq_error, stm32f7_i2c_isr_error, 0,</div><div class='del'>-			       pdev-&gt;name, i2c_dev);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to request irq error %i\n",</div><div class='del'>-			irq_error);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	setup = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='del'>-	if (!setup) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Can't get device data\n");</div><div class='del'>-		return -ENODEV;</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, ret, "Failed to request irq event\n");</div><div class='add'>+</div><div class='add'>+	if (!i2c_dev-&gt;setup.single_it_line) {</div><div class='add'>+		irq_error = platform_get_irq(pdev, 1);</div><div class='add'>+		if (irq_error &lt; 0)</div><div class='add'>+			return irq_error;</div><div class='add'>+</div><div class='add'>+		ret = devm_request_threaded_irq(&amp;pdev-&gt;dev, irq_error,</div><div class='add'>+						NULL,</div><div class='add'>+						stm32f7_i2c_isr_error_thread,</div><div class='add'>+						IRQF_ONESHOT,</div><div class='add'>+						pdev-&gt;name, i2c_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return dev_err_probe(&amp;pdev-&gt;dev, ret, "Failed to request irq error\n");</div><div class='ctx'> 	}</div><div class='del'>-	i2c_dev-&gt;setup = *setup;</div><div class='ctx'> </div><div class='ctx'> 	ret = stm32f7_i2c_setup_timing(i2c_dev, &amp;i2c_dev-&gt;setup);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -2226,9 +2236,12 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	/* Setup Fast mode plus if necessary */</div><div class='ctx'> 	if (i2c_dev-&gt;bus_rate &gt; I2C_MAX_FAST_MODE_FREQ) {</div><div class='del'>-		ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (!i2c_dev-&gt;setup.fmp_cr1_bit) {</div><div class='add'>+			ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -2507,6 +2520,7 @@ static const struct of_device_id stm32f7_i2c_match[] = {</div><div class='ctx'> 	{ .compatible = "st,stm32f7-i2c", .data = &amp;stm32f7_setup},</div><div class='ctx'> 	{ .compatible = "st,stm32mp15-i2c", .data = &amp;stm32mp15_setup},</div><div class='ctx'> 	{ .compatible = "st,stm32mp13-i2c", .data = &amp;stm32mp13_setup},</div><div class='add'>+	{ .compatible = "st,stm32mp25-i2c", .data = &amp;stm32mp25_setup},</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-via.c b/drivers/i2c/busses/i2c-via.c<br/>index ad4f09c7f027..7ed29992a97f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-via.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-via.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-via.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-via.c</a></div><div class='hunk'>@@ -70,7 +70,7 @@ static struct i2c_algo_bit_data bit_data = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter vt586b_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class          = I2C_CLASS_HWMON,</div><div class='ctx'> 	.name		= "VIA i2c",</div><div class='ctx'> 	.algo_data	= &amp;bit_data,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c<br/>index 970ccdcbb889..2cc7bba3b8bf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-viapro.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-viapro.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-viapro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-viapro.c</a></div><div class='hunk'>@@ -304,7 +304,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter vt596_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c<br/>index 76118abc6e10..ec2a8da134e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-wmt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/i2c-wmt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/i2c-wmt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/i2c-wmt.c</a></div><div class='hunk'>@@ -74,9 +74,6 @@</div><div class='ctx'> #define MCR_APB_96M		7</div><div class='ctx'> #define MCR_APB_166M		12</div><div class='ctx'> </div><div class='del'>-#define I2C_MODE_STANDARD	0</div><div class='del'>-#define I2C_MODE_FAST		1</div><div class='del'>-</div><div class='ctx'> #define WMT_I2C_TIMEOUT		(msecs_to_jiffies(1000))</div><div class='ctx'> </div><div class='ctx'> struct wmt_i2c_dev {</div><div class='hunk'>@@ -85,7 +82,7 @@ struct wmt_i2c_dev {</div><div class='ctx'> 	struct device		*dev;</div><div class='ctx'> 	void __iomem		*base;</div><div class='ctx'> 	struct clk		*clk;</div><div class='del'>-	int			mode;</div><div class='add'>+	u16			tcr;</div><div class='ctx'> 	int			irq;</div><div class='ctx'> 	u16			cmd_status;</div><div class='ctx'> };</div><div class='hunk'>@@ -109,6 +106,12 @@ static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)</div><div class='ctx'> static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret = 0;</div><div class='add'>+	unsigned long wait_result;</div><div class='add'>+</div><div class='add'>+	wait_result = wait_for_completion_timeout(&amp;i2c_dev-&gt;complete,</div><div class='add'>+						msecs_to_jiffies(500));</div><div class='add'>+	if (!wait_result)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='ctx'> </div><div class='ctx'> 	if (i2c_dev-&gt;cmd_status &amp; ISR_NACK_ADDR)</div><div class='ctx'> 		ret = -EIO;</div><div class='hunk'>@@ -119,21 +122,13 @@ static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='add'>+static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg,</div><div class='ctx'> 			 int last)</div><div class='ctx'> {</div><div class='del'>-	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);</div><div class='del'>-	u16 val, tcr_val;</div><div class='add'>+	u16 val, tcr_val = i2c_dev-&gt;tcr;</div><div class='ctx'> 	int ret;</div><div class='del'>-	unsigned long wait_result;</div><div class='ctx'> 	int xfer_len = 0;</div><div class='ctx'> </div><div class='del'>-	if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART)) {</div><div class='del'>-		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (pmsg-&gt;len == 0) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * We still need to run through the while (..) once, so</div><div class='hunk'>@@ -148,20 +143,12 @@ static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='ctx'> 	if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART)) {</div><div class='ctx'> 		val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='ctx'> 		val &amp;= ~CR_TX_END;</div><div class='del'>-		writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-</div><div class='del'>-		val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='ctx'> 		val |= CR_CPU_RDY;</div><div class='ctx'> 		writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	reinit_completion(&amp;i2c_dev-&gt;complete);</div><div class='ctx'> </div><div class='del'>-	if (i2c_dev-&gt;mode == I2C_MODE_STANDARD)</div><div class='del'>-		tcr_val = TCR_STANDARD_MODE;</div><div class='del'>-	else</div><div class='del'>-		tcr_val = TCR_FAST_MODE;</div><div class='del'>-</div><div class='ctx'> 	tcr_val |= (TCR_MASTER_WRITE | (pmsg-&gt;addr &amp; TCR_SLAVE_ADDR_MASK));</div><div class='ctx'> </div><div class='ctx'> 	writew(tcr_val, i2c_dev-&gt;base + REG_TCR);</div><div class='hunk'>@@ -173,12 +160,6 @@ static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	while (xfer_len &lt; pmsg-&gt;len) {</div><div class='del'>-		wait_result = wait_for_completion_timeout(&amp;i2c_dev-&gt;complete,</div><div class='del'>-							msecs_to_jiffies(500));</div><div class='del'>-</div><div class='del'>-		if (wait_result == 0)</div><div class='del'>-			return -ETIMEDOUT;</div><div class='del'>-</div><div class='ctx'> 		ret = wmt_check_status(i2c_dev);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -210,47 +191,24 @@ static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='del'>-			int last)</div><div class='add'>+static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg)</div><div class='ctx'> {</div><div class='del'>-	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);</div><div class='del'>-	u16 val, tcr_val;</div><div class='add'>+	u16 val, tcr_val = i2c_dev-&gt;tcr;</div><div class='ctx'> 	int ret;</div><div class='del'>-	unsigned long wait_result;</div><div class='ctx'> 	u32 xfer_len = 0;</div><div class='ctx'> </div><div class='del'>-	if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART)) {</div><div class='del'>-		ret = wmt_i2c_wait_bus_not_busy(i2c_dev);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='del'>-	val &amp;= ~CR_TX_END;</div><div class='del'>-	writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-</div><div class='ctx'> 	val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='del'>-	val &amp;= ~CR_TX_NEXT_NO_ACK;</div><div class='del'>-	writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='add'>+	val &amp;= ~(CR_TX_END | CR_TX_NEXT_NO_ACK);</div><div class='ctx'> </div><div class='del'>-	if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART)) {</div><div class='del'>-		val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='add'>+	if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART))</div><div class='ctx'> 		val |= CR_CPU_RDY;</div><div class='del'>-		writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (pmsg-&gt;len == 1) {</div><div class='del'>-		val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='add'>+	if (pmsg-&gt;len == 1)</div><div class='ctx'> 		val |= CR_TX_NEXT_NO_ACK;</div><div class='del'>-		writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	reinit_completion(&amp;i2c_dev-&gt;complete);</div><div class='add'>+	writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='ctx'> </div><div class='del'>-	if (i2c_dev-&gt;mode == I2C_MODE_STANDARD)</div><div class='del'>-		tcr_val = TCR_STANDARD_MODE;</div><div class='del'>-	else</div><div class='del'>-		tcr_val = TCR_FAST_MODE;</div><div class='add'>+	reinit_completion(&amp;i2c_dev-&gt;complete);</div><div class='ctx'> </div><div class='ctx'> 	tcr_val |= TCR_MASTER_READ | (pmsg-&gt;addr &amp; TCR_SLAVE_ADDR_MASK);</div><div class='ctx'> </div><div class='hunk'>@@ -263,12 +221,6 @@ static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	while (xfer_len &lt; pmsg-&gt;len) {</div><div class='del'>-		wait_result = wait_for_completion_timeout(&amp;i2c_dev-&gt;complete,</div><div class='del'>-							msecs_to_jiffies(500));</div><div class='del'>-</div><div class='del'>-		if (!wait_result)</div><div class='del'>-			return -ETIMEDOUT;</div><div class='del'>-</div><div class='ctx'> 		ret = wmt_check_status(i2c_dev);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -276,15 +228,10 @@ static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,</div><div class='ctx'> 		pmsg-&gt;buf[xfer_len] = readw(i2c_dev-&gt;base + REG_CDR) &gt;&gt; 8;</div><div class='ctx'> 		xfer_len++;</div><div class='ctx'> </div><div class='del'>-		if (xfer_len == pmsg-&gt;len - 1) {</div><div class='del'>-			val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='del'>-			val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);</div><div class='del'>-			writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-		} else {</div><div class='del'>-			val = readw(i2c_dev-&gt;base + REG_CR);</div><div class='del'>-			val |= CR_CPU_RDY;</div><div class='del'>-			writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='del'>-		}</div><div class='add'>+		val = readw(i2c_dev-&gt;base + REG_CR) | CR_CPU_RDY;</div><div class='add'>+		if (xfer_len == pmsg-&gt;len - 1)</div><div class='add'>+			val |= CR_TX_NEXT_NO_ACK;</div><div class='add'>+		writew(val, i2c_dev-&gt;base + REG_CR);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -295,17 +242,22 @@ static int wmt_i2c_xfer(struct i2c_adapter *adap,</div><div class='ctx'> 			int num)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_msg *pmsg;</div><div class='del'>-	int i, is_last;</div><div class='add'>+	int i;</div><div class='ctx'> 	int ret = 0;</div><div class='add'>+	struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; ret &gt;= 0 &amp;&amp; i &lt; num; i++) {</div><div class='del'>-		is_last = ((i + 1) == num);</div><div class='del'>-</div><div class='ctx'> 		pmsg = &amp;msgs[i];</div><div class='add'>+		if (!(pmsg-&gt;flags &amp; I2C_M_NOSTART)) {</div><div class='add'>+			ret = wmt_i2c_wait_bus_not_busy(i2c_dev);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if (pmsg-&gt;flags &amp; I2C_M_RD)</div><div class='del'>-			ret = wmt_i2c_read(adap, pmsg, is_last);</div><div class='add'>+			ret = wmt_i2c_read(i2c_dev, pmsg);</div><div class='ctx'> 		else</div><div class='del'>-			ret = wmt_i2c_write(adap, pmsg, is_last);</div><div class='add'>+			ret = wmt_i2c_write(i2c_dev, pmsg, (i + 1) == num);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return (ret &lt; 0) ? ret : i;</div><div class='hunk'>@@ -359,10 +311,10 @@ static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)</div><div class='ctx'> 	readw(i2c_dev-&gt;base + REG_CSR);		/* read clear */</div><div class='ctx'> 	writew(ISR_WRITE_ALL, i2c_dev-&gt;base + REG_ISR);</div><div class='ctx'> </div><div class='del'>-	if (i2c_dev-&gt;mode == I2C_MODE_STANDARD)</div><div class='del'>-		writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev-&gt;base + REG_TR);</div><div class='del'>-	else</div><div class='add'>+	if (i2c_dev-&gt;tcr == TCR_FAST_MODE)</div><div class='ctx'> 		writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev-&gt;base + REG_TR);</div><div class='add'>+	else</div><div class='add'>+		writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev-&gt;base + REG_TR);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -395,10 +347,9 @@ static int wmt_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 		return PTR_ERR(i2c_dev-&gt;clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	i2c_dev-&gt;mode = I2C_MODE_STANDARD;</div><div class='ctx'> 	err = of_property_read_u32(np, "clock-frequency", &amp;clk_rate);</div><div class='ctx'> 	if (!err &amp;&amp; (clk_rate == I2C_MAX_FAST_MODE_FREQ))</div><div class='del'>-		i2c_dev-&gt;mode = I2C_MODE_FAST;</div><div class='add'>+		i2c_dev-&gt;tcr = TCR_FAST_MODE;</div><div class='ctx'> </div><div class='ctx'> 	i2c_dev-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c<br/>index 83c1db610f54..3648382b885a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/busses/scx200_acb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/busses/scx200_acb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/busses/scx200_acb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/busses/scx200_acb.c</a></div><div class='hunk'>@@ -427,7 +427,7 @@ static struct scx200_acb_iface *scx200_create_iface(const char *text,</div><div class='ctx'> 	snprintf(adapter-&gt;name, sizeof(adapter-&gt;name), "%s ACB%d", text, index);</div><div class='ctx'> 	adapter-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	adapter-&gt;algo = &amp;scx200_acb_algorithm;</div><div class='del'>-	adapter-&gt;class = I2C_CLASS_HWMON | I2C_CLASS_SPD;</div><div class='add'>+	adapter-&gt;class = I2C_CLASS_HWMON;</div><div class='ctx'> 	adapter-&gt;dev.parent = dev;</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;iface-&gt;mutex);</div><div class='head'>diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c<br/>index eac90a3cf61a..3bd48d4b6318 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-core-base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/i2c-core-base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-core-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-core-base.c</a></div><div class='hunk'>@@ -16,6 +16,7 @@</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='ctx'> #include &lt;linux/clk/clk-conf.h&gt;</div><div class='ctx'> #include &lt;linux/completion.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='hunk'>@@ -67,6 +68,8 @@ static int i2c_detect(struct i2c_adapter *adapter, struct i2c_driver *driver);</div><div class='ctx'> static DEFINE_STATIC_KEY_FALSE(i2c_trace_msg_key);</div><div class='ctx'> static bool is_registered;</div><div class='ctx'> </div><div class='add'>+static struct dentry *i2c_debugfs_root;</div><div class='add'>+</div><div class='ctx'> int i2c_transfer_trace_reg(void)</div><div class='ctx'> {</div><div class='ctx'> 	static_branch_inc(&amp;i2c_trace_msg_key);</div><div class='hunk'>@@ -689,7 +692,7 @@ static struct attribute *i2c_dev_attrs[] = {</div><div class='ctx'> };</div><div class='ctx'> ATTRIBUTE_GROUPS(i2c_dev);</div><div class='ctx'> </div><div class='del'>-struct bus_type i2c_bus_type = {</div><div class='add'>+const struct bus_type i2c_bus_type = {</div><div class='ctx'> 	.name		= "i2c",</div><div class='ctx'> 	.match		= i2c_device_match,</div><div class='ctx'> 	.probe		= i2c_device_probe,</div><div class='hunk'>@@ -1524,6 +1527,8 @@ static int i2c_register_adapter(struct i2c_adapter *adap)</div><div class='ctx'> 		goto out_list;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	adap-&gt;debugfs = debugfs_create_dir(dev_name(&amp;adap-&gt;dev), i2c_debugfs_root);</div><div class='add'>+</div><div class='ctx'> 	res = i2c_setup_smbus_alert(adap);</div><div class='ctx'> 	if (res)</div><div class='ctx'> 		goto out_reg;</div><div class='hunk'>@@ -1563,6 +1568,7 @@ static int i2c_register_adapter(struct i2c_adapter *adap)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_reg:</div><div class='add'>+	debugfs_remove_recursive(adap-&gt;debugfs);</div><div class='ctx'> 	init_completion(&amp;adap-&gt;dev_released);</div><div class='ctx'> 	device_unregister(&amp;adap-&gt;dev);</div><div class='ctx'> 	wait_for_completion(&amp;adap-&gt;dev_released);</div><div class='hunk'>@@ -1764,6 +1770,8 @@ void i2c_del_adapter(struct i2c_adapter *adap)</div><div class='ctx'> </div><div class='ctx'> 	i2c_host_notify_irq_teardown(adap);</div><div class='ctx'> </div><div class='add'>+	debugfs_remove_recursive(adap-&gt;debugfs);</div><div class='add'>+</div><div class='ctx'> 	/* wait until all references to the device are gone</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * FIXME: This is old code and should ideally be replaced by an</div><div class='hunk'>@@ -2061,6 +2069,8 @@ static int __init i2c_init(void)</div><div class='ctx'> </div><div class='ctx'> 	is_registered = true;</div><div class='ctx'> </div><div class='add'>+	i2c_debugfs_root = debugfs_create_dir("i2c", NULL);</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_I2C_COMPAT</div><div class='ctx'> 	i2c_adapter_compat_class = class_compat_register("i2c-adapter");</div><div class='ctx'> 	if (!i2c_adapter_compat_class) {</div><div class='hunk'>@@ -2099,6 +2109,7 @@ static void __exit i2c_exit(void)</div><div class='ctx'> #ifdef CONFIG_I2C_COMPAT</div><div class='ctx'> 	class_compat_unregister(i2c_adapter_compat_class);</div><div class='ctx'> #endif</div><div class='add'>+	debugfs_remove_recursive(i2c_debugfs_root);</div><div class='ctx'> 	bus_unregister(&amp;i2c_bus_type);</div><div class='ctx'> 	tracepoint_synchronize_unregister();</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/i2c/i2c-core.h b/drivers/i2c/i2c-core.h<br/>index 05b8b8dfa9bd..36587f38dff3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/i2c-core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-core.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * i2c-core.h - interfaces internal to the I2C framework</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/kconfig.h&gt;</div><div class='ctx'> #include &lt;linux/rwsem.h&gt;</div><div class='ctx'> </div><div class='ctx'> struct i2c_devinfo {</div><div class='hunk'>@@ -29,7 +30,8 @@ int i2c_dev_irq_from_resources(const struct resource *resources,</div><div class='ctx'>  */</div><div class='ctx'> static inline bool i2c_in_atomic_xfer_mode(void)</div><div class='ctx'> {</div><div class='del'>-	return system_state &gt; SYSTEM_RUNNING &amp;&amp; !preemptible();</div><div class='add'>+	return system_state &gt; SYSTEM_RUNNING &amp;&amp;</div><div class='add'>+	       (IS_ENABLED(CONFIG_PREEMPT_COUNT) ? !preemptible() : irqs_disabled());</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int __i2c_lock_bus_helper(struct i2c_adapter *adap)</div><div class='head'>diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c<br/>index 138c3f5e0093..74807c6db596 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-smbus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/i2c-smbus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-smbus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-smbus.c</a></div><div class='hunk'>@@ -308,8 +308,8 @@ EXPORT_SYMBOL_GPL(i2c_free_slave_host_notify_device);</div><div class='ctx'>  * target systems are the same.</div><div class='ctx'>  * Restrictions to automatic SPD instantiation:</div><div class='ctx'>  *  - Only works if all filled slots have the same memory type</div><div class='del'>- *  - Only works for DDR2, DDR3 and DDR4 for now</div><div class='del'>- *  - Only works on systems with 1 to 4 memory slots</div><div class='add'>+ *  - Only works for DDR, DDR2, DDR3 and DDR4 for now</div><div class='add'>+ *  - Only works on systems with 1 to 8 memory slots</div><div class='ctx'>  */</div><div class='ctx'> #if IS_ENABLED(CONFIG_DMI)</div><div class='ctx'> void i2c_register_spd(struct i2c_adapter *adap)</div><div class='hunk'>@@ -354,9 +354,9 @@ void i2c_register_spd(struct i2c_adapter *adap)</div><div class='ctx'> 	dev_info(&amp;adap-&gt;dev, "%d/%d memory slots populated (from DMI)\n",</div><div class='ctx'> 		 dimm_count, slot_count);</div><div class='ctx'> </div><div class='del'>-	if (slot_count &gt; 4) {</div><div class='add'>+	if (slot_count &gt; 8) {</div><div class='ctx'> 		dev_warn(&amp;adap-&gt;dev,</div><div class='del'>-			 "Systems with more than 4 memory slots not supported yet, not instantiating SPD\n");</div><div class='add'>+			 "Systems with more than 8 memory slots not supported yet, not instantiating SPD\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/i2c/i2c-stub.c b/drivers/i2c/i2c-stub.c<br/>index d642cad219d9..09e7b7bf4c5f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-stub.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/i2c-stub.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/i2c-stub.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/i2c-stub.c</a></div><div class='hunk'>@@ -308,7 +308,7 @@ static const struct i2c_algorithm smbus_algorithm = {</div><div class='ctx'> </div><div class='ctx'> static struct i2c_adapter stub_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;smbus_algorithm,</div><div class='ctx'> 	.name		= "SMBus stub driver",</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/i2c/muxes/i2c-mux-reg.c b/drivers/i2c/muxes/i2c-mux-reg.c<br/>index 9efc1ed01577..8489971babd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i2c/muxes/i2c-mux-reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i2c/muxes/i2c-mux-reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i2c/muxes/i2c-mux-reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i2c/muxes/i2c-mux-reg.c</a></div><div class='hunk'>@@ -159,7 +159,6 @@ static int i2c_mux_reg_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct regmux *mux;</div><div class='ctx'> 	struct i2c_adapter *parent;</div><div class='ctx'> 	struct resource *res;</div><div class='del'>-	unsigned int class;</div><div class='ctx'> 	int i, ret, nr;</div><div class='ctx'> </div><div class='ctx'> 	mux = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*mux), GFP_KERNEL);</div><div class='hunk'>@@ -213,9 +212,8 @@ static int i2c_mux_reg_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; mux-&gt;data.n_values; i++) {</div><div class='ctx'> 		nr = mux-&gt;data.base_nr ? (mux-&gt;data.base_nr + i) : 0;</div><div class='del'>-		class = mux-&gt;data.classes ? mux-&gt;data.classes[i] : 0;</div><div class='ctx'> </div><div class='del'>-		ret = i2c_mux_add_adapter(muxc, nr, mux-&gt;data.values[i], class);</div><div class='add'>+		ret = i2c_mux_add_adapter(muxc, nr, mux-&gt;data.values[i], 0);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto err_del_mux_adapters;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c<br/>index 95caa162706f..3afa530c5e32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master.c</a></div><div class='hunk'>@@ -557,6 +557,88 @@ static ssize_t i2c_scl_frequency_show(struct device *dev,</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(i2c_scl_frequency);</div><div class='ctx'> </div><div class='add'>+static int i3c_set_hotjoin(struct i3c_master_controller *master, bool enable)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!master || !master-&gt;ops)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!master-&gt;ops-&gt;enable_hotjoin || !master-&gt;ops-&gt;disable_hotjoin)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	i3c_bus_normaluse_lock(&amp;master-&gt;bus);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		ret = master-&gt;ops-&gt;enable_hotjoin(master);</div><div class='add'>+	else</div><div class='add'>+		ret = master-&gt;ops-&gt;disable_hotjoin(master);</div><div class='add'>+</div><div class='add'>+	master-&gt;hotjoin = enable;</div><div class='add'>+</div><div class='add'>+	i3c_bus_normaluse_unlock(&amp;master-&gt;bus);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t hotjoin_store(struct device *dev, struct device_attribute *attr,</div><div class='add'>+			     const char *buf, size_t count)</div><div class='add'>+{</div><div class='add'>+	struct i3c_bus *i3cbus = dev_to_i3cbus(dev);</div><div class='add'>+	int ret;</div><div class='add'>+	bool res;</div><div class='add'>+</div><div class='add'>+	if (!i3cbus-&gt;cur_master)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (kstrtobool(buf, &amp;res))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = i3c_set_hotjoin(i3cbus-&gt;cur_master-&gt;common.master, res);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * i3c_master_enable_hotjoin - Enable hotjoin</div><div class='add'>+ * @master: I3C master object</div><div class='add'>+ *</div><div class='add'>+ * Return: a 0 in case of success, an negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int i3c_master_enable_hotjoin(struct i3c_master_controller *master)</div><div class='add'>+{</div><div class='add'>+	return i3c_set_hotjoin(master, true);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(i3c_master_enable_hotjoin);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * i3c_master_disable_hotjoin - Disable hotjoin</div><div class='add'>+ * @master: I3C master object</div><div class='add'>+ *</div><div class='add'>+ * Return: a 0 in case of success, an negative error code otherwise.</div><div class='add'>+ */</div><div class='add'>+int i3c_master_disable_hotjoin(struct i3c_master_controller *master)</div><div class='add'>+{</div><div class='add'>+	return i3c_set_hotjoin(master, false);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(i3c_master_disable_hotjoin);</div><div class='add'>+</div><div class='add'>+static ssize_t hotjoin_show(struct device *dev, struct device_attribute *da, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct i3c_bus *i3cbus = dev_to_i3cbus(dev);</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	i3c_bus_normaluse_lock(i3cbus);</div><div class='add'>+	ret = sysfs_emit(buf, "%d\n", i3cbus-&gt;cur_master-&gt;common.master-&gt;hotjoin);</div><div class='add'>+	i3c_bus_normaluse_unlock(i3cbus);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEVICE_ATTR_RW(hotjoin);</div><div class='add'>+</div><div class='ctx'> static struct attribute *i3c_masterdev_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_mode.attr,</div><div class='ctx'> 	&amp;dev_attr_current_master.attr,</div><div class='hunk'>@@ -567,6 +649,7 @@ static struct attribute *i3c_masterdev_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_pid.attr,</div><div class='ctx'> 	&amp;dev_attr_dynamic_address.attr,</div><div class='ctx'> 	&amp;dev_attr_hdrcap.attr,</div><div class='add'>+	&amp;dev_attr_hotjoin.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> ATTRIBUTE_GROUPS(i3c_masterdev);</div><div class='hunk'>@@ -1130,8 +1213,16 @@ static int i3c_master_getmxds_locked(struct i3c_master_controller *master,</div><div class='ctx'> </div><div class='ctx'> 	i3c_ccc_cmd_init(&amp;cmd, true, I3C_CCC_GETMXDS, &amp;dest, 1);</div><div class='ctx'> 	ret = i3c_master_send_ccc_cmd_locked(master, &amp;cmd);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto out;</div><div class='add'>+	if (ret) {</div><div class='add'>+		/*</div><div class='add'>+		 * Retry when the device does not support max read turnaround</div><div class='add'>+		 * while expecting shorter length from this CCC command.</div><div class='add'>+		 */</div><div class='add'>+		dest.payload.len -= 3;</div><div class='add'>+		ret = i3c_master_send_ccc_cmd_locked(master, &amp;cmd);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (dest.payload.len != 2 &amp;&amp; dest.payload.len != 5) {</div><div class='ctx'> 		ret = -EIO;</div><div class='head'>diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c<br/>index bcbe8f914149..c1627f3552ce 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/i3c-master-cdns.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/i3c-master-cdns.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/i3c-master-cdns.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/i3c-master-cdns.c</a></div><div class='hunk'>@@ -76,7 +76,8 @@</div><div class='ctx'> #define PRESCL_CTRL0			0x14</div><div class='ctx'> #define PRESCL_CTRL0_I2C(x)		((x) &lt;&lt; 16)</div><div class='ctx'> #define PRESCL_CTRL0_I3C(x)		(x)</div><div class='del'>-#define PRESCL_CTRL0_MAX		GENMASK(9, 0)</div><div class='add'>+#define PRESCL_CTRL0_I3C_MAX		GENMASK(9, 0)</div><div class='add'>+#define PRESCL_CTRL0_I2C_MAX		GENMASK(15, 0)</div><div class='ctx'> </div><div class='ctx'> #define PRESCL_CTRL1			0x18</div><div class='ctx'> #define PRESCL_CTRL1_PP_LOW_MASK	GENMASK(15, 8)</div><div class='hunk'>@@ -1233,7 +1234,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	pres = DIV_ROUND_UP(sysclk_rate, (bus-&gt;scl_rate.i3c * 4)) - 1;</div><div class='del'>-	if (pres &gt; PRESCL_CTRL0_MAX)</div><div class='add'>+	if (pres &gt; PRESCL_CTRL0_I3C_MAX)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> </div><div class='ctx'> 	bus-&gt;scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);</div><div class='hunk'>@@ -1246,7 +1247,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)</div><div class='ctx'> 	max_i2cfreq = bus-&gt;scl_rate.i2c;</div><div class='ctx'> </div><div class='ctx'> 	pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;</div><div class='del'>-	if (pres &gt; PRESCL_CTRL0_MAX)</div><div class='add'>+	if (pres &gt; PRESCL_CTRL0_I2C_MAX)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> </div><div class='ctx'> 	bus-&gt;scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);</div><div class='head'>diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c b/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c<br/>index 2b2323aa6714..638b054d6c92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/mipi-i3c-hci/cmd_v1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/cmd_v1.c</a></div><div class='hunk'>@@ -298,7 +298,7 @@ static int hci_cmd_v1_daa(struct i3c_hci *hci)</div><div class='ctx'> 	unsigned int dcr, bcr;</div><div class='ctx'> 	DECLARE_COMPLETION_ONSTACK(done);</div><div class='ctx'> </div><div class='del'>-	xfer = hci_alloc_xfer(2);</div><div class='add'>+	xfer = hci_alloc_xfer(1);</div><div class='ctx'> 	if (!xfer)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -339,12 +339,13 @@ static int hci_cmd_v1_daa(struct i3c_hci *hci)</div><div class='ctx'> 			ret = -ETIME;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		if (RESP_STATUS(xfer[0].response) == RESP_ERR_NACK &amp;&amp;</div><div class='add'>+		if ((RESP_STATUS(xfer-&gt;response) == RESP_ERR_ADDR_HEADER ||</div><div class='add'>+		     RESP_STATUS(xfer-&gt;response) == RESP_ERR_NACK) &amp;&amp;</div><div class='ctx'> 		    RESP_DATA_LENGTH(xfer-&gt;response) == 1) {</div><div class='ctx'> 			ret = 0;  /* no more devices to be assigned */</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) {</div><div class='add'>+		if (RESP_STATUS(xfer-&gt;response) != RESP_SUCCESS) {</div><div class='ctx'> 			ret = -EIO;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c<br/>index 1ae56a5699c6..d7e966a25583 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/mipi-i3c-hci/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/core.c</a></div><div class='hunk'>@@ -245,7 +245,14 @@ static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m,</div><div class='ctx'> 		if (ccc-&gt;rnw)</div><div class='ctx'> 			ccc-&gt;dests[i - prefixed].payload.len =</div><div class='ctx'> 				RESP_DATA_LENGTH(xfer[i].response);</div><div class='del'>-		if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) {</div><div class='add'>+		switch (RESP_STATUS(xfer[i].response)) {</div><div class='add'>+		case RESP_SUCCESS:</div><div class='add'>+			continue;</div><div class='add'>+		case RESP_ERR_ADDR_HEADER:</div><div class='add'>+		case RESP_ERR_NACK:</div><div class='add'>+			ccc-&gt;err = I3C_ERROR_M2;</div><div class='add'>+			fallthrough;</div><div class='add'>+		default:</div><div class='ctx'> 			ret = -EIO;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -269,6 +276,34 @@ static int i3c_hci_daa(struct i3c_master_controller *m)</div><div class='ctx'> 	return hci-&gt;cmd-&gt;perform_daa(hci);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int i3c_hci_alloc_safe_xfer_buf(struct i3c_hci *hci,</div><div class='add'>+				       struct hci_xfer *xfer)</div><div class='add'>+{</div><div class='add'>+	if (hci-&gt;io != &amp;mipi_i3c_hci_dma ||</div><div class='add'>+	    xfer-&gt;data == NULL || !is_vmalloc_addr(xfer-&gt;data))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (xfer-&gt;rnw)</div><div class='add'>+		xfer-&gt;bounce_buf = kzalloc(xfer-&gt;data_len, GFP_KERNEL);</div><div class='add'>+	else</div><div class='add'>+		xfer-&gt;bounce_buf = kmemdup(xfer-&gt;data,</div><div class='add'>+					   xfer-&gt;data_len, GFP_KERNEL);</div><div class='add'>+</div><div class='add'>+	return xfer-&gt;bounce_buf == NULL ? -ENOMEM : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void i3c_hci_free_safe_xfer_buf(struct i3c_hci *hci,</div><div class='add'>+				       struct hci_xfer *xfer)</div><div class='add'>+{</div><div class='add'>+	if (hci-&gt;io != &amp;mipi_i3c_hci_dma || xfer-&gt;bounce_buf == NULL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (xfer-&gt;rnw)</div><div class='add'>+		memcpy(xfer-&gt;data, xfer-&gt;bounce_buf, xfer-&gt;data_len);</div><div class='add'>+</div><div class='add'>+	kfree(xfer-&gt;bounce_buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev,</div><div class='ctx'> 			      struct i3c_priv_xfer *i3c_xfers,</div><div class='ctx'> 			      int nxfers)</div><div class='hunk'>@@ -302,6 +337,9 @@ static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev,</div><div class='ctx'> 		}</div><div class='ctx'> 		hci-&gt;cmd-&gt;prep_i3c_xfer(hci, dev, &amp;xfer[i]);</div><div class='ctx'> 		xfer[i].cmd_desc[0] |= CMD_0_ROC;</div><div class='add'>+		ret = i3c_hci_alloc_safe_xfer_buf(hci, &amp;xfer[i]);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	last = i - 1;</div><div class='ctx'> 	xfer[last].cmd_desc[0] |= CMD_0_TOC;</div><div class='hunk'>@@ -325,6 +363,9 @@ static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='add'>+	for (i = 0; i &lt; nxfers; i++)</div><div class='add'>+		i3c_hci_free_safe_xfer_buf(hci, &amp;xfer[i]);</div><div class='add'>+</div><div class='ctx'> 	hci_free_xfer(xfer, nxfers);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -350,6 +391,9 @@ static int i3c_hci_i2c_xfers(struct i2c_dev_desc *dev,</div><div class='ctx'> 		xfer[i].rnw = i2c_xfers[i].flags &amp; I2C_M_RD;</div><div class='ctx'> 		hci-&gt;cmd-&gt;prep_i2c_xfer(hci, dev, &amp;xfer[i]);</div><div class='ctx'> 		xfer[i].cmd_desc[0] |= CMD_0_ROC;</div><div class='add'>+		ret = i3c_hci_alloc_safe_xfer_buf(hci, &amp;xfer[i]);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	last = i - 1;</div><div class='ctx'> 	xfer[last].cmd_desc[0] |= CMD_0_TOC;</div><div class='hunk'>@@ -371,6 +415,9 @@ static int i3c_hci_i2c_xfers(struct i2c_dev_desc *dev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='add'>+	for (i = 0; i &lt; nxfers; i++)</div><div class='add'>+		i3c_hci_free_safe_xfer_buf(hci, &amp;xfer[i]);</div><div class='add'>+</div><div class='ctx'> 	hci_free_xfer(xfer, nxfers);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c<br/>index c805a8497319..4e01a95cc4d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/mipi-i3c-hci/dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/dma.c</a></div><div class='hunk'>@@ -362,6 +362,7 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci,</div><div class='ctx'> 	struct hci_rh_data *rh;</div><div class='ctx'> 	unsigned int i, ring, enqueue_ptr;</div><div class='ctx'> 	u32 op1_val, op2_val;</div><div class='add'>+	void *buf;</div><div class='ctx'> </div><div class='ctx'> 	/* For now we only use ring 0 */</div><div class='ctx'> 	ring = 0;</div><div class='hunk'>@@ -390,9 +391,10 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci,</div><div class='ctx'> </div><div class='ctx'> 		/* 2nd and 3rd words of Data Buffer Descriptor Structure */</div><div class='ctx'> 		if (xfer-&gt;data) {</div><div class='add'>+			buf = xfer-&gt;bounce_buf ? xfer-&gt;bounce_buf : xfer-&gt;data;</div><div class='ctx'> 			xfer-&gt;data_dma =</div><div class='ctx'> 				dma_map_single(&amp;hci-&gt;master.dev,</div><div class='del'>-					       xfer-&gt;data,</div><div class='add'>+					       buf,</div><div class='ctx'> 					       xfer-&gt;data_len,</div><div class='ctx'> 					       xfer-&gt;rnw ?</div><div class='ctx'> 						  DMA_FROM_DEVICE :</div><div class='head'>diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h<br/>index f109923f6c3f..f94d95e024be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/hci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/mipi-i3c-hci/hci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/mipi-i3c-hci/hci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/mipi-i3c-hci/hci.h</a></div><div class='hunk'>@@ -90,6 +90,7 @@ struct hci_xfer {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			/* DMA specific */</div><div class='ctx'> 			dma_addr_t data_dma;</div><div class='add'>+			void *bounce_buf;</div><div class='ctx'> 			int ring_number;</div><div class='ctx'> 			int ring_entry;</div><div class='ctx'> 		};</div><div class='head'>diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c<br/>index cf703c00f633..5ee4db68988e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/i3c/master/svc-i3c-master.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/i3c/master/svc-i3c-master.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/i3c/master/svc-i3c-master.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/i3c/master/svc-i3c-master.c</a></div><div class='hunk'>@@ -128,13 +128,17 @@</div><div class='ctx'> /* This parameter depends on the implementation and may be tuned */</div><div class='ctx'> #define SVC_I3C_FIFO_SIZE 16</div><div class='ctx'> </div><div class='add'>+#define SVC_I3C_EVENT_IBI	BIT(0)</div><div class='add'>+#define SVC_I3C_EVENT_HOTJOIN	BIT(1)</div><div class='add'>+</div><div class='ctx'> struct svc_i3c_cmd {</div><div class='ctx'> 	u8 addr;</div><div class='ctx'> 	bool rnw;</div><div class='ctx'> 	u8 *in;</div><div class='ctx'> 	const void *out;</div><div class='ctx'> 	unsigned int len;</div><div class='del'>-	unsigned int read_len;</div><div class='add'>+	unsigned int actual_len;</div><div class='add'>+	struct i3c_priv_xfer *xfer;</div><div class='ctx'> 	bool continued;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -177,6 +181,7 @@ struct svc_i3c_regs_save {</div><div class='ctx'>  * @ibi.tbq_slot: To be queued IBI slot</div><div class='ctx'>  * @ibi.lock: IBI lock</div><div class='ctx'>  * @lock: Transfer lock, protect between IBI work thread and callbacks from master</div><div class='add'>+ * @enabled_events: Bit masks for enable events (IBI, HotJoin).</div><div class='ctx'>  */</div><div class='ctx'> struct svc_i3c_master {</div><div class='ctx'> 	struct i3c_master_controller base;</div><div class='hunk'>@@ -206,6 +211,7 @@ struct svc_i3c_master {</div><div class='ctx'> 		spinlock_t lock;</div><div class='ctx'> 	} ibi;</div><div class='ctx'> 	struct mutex lock;</div><div class='add'>+	int enabled_events;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -220,6 +226,11 @@ struct svc_i3c_i2c_dev_data {</div><div class='ctx'> 	struct i3c_generic_ibi_pool *ibi_pool;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask)</div><div class='add'>+{</div><div class='add'>+	return !!(master-&gt;enabled_events &amp; mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool svc_i3c_master_error(struct svc_i3c_master *master)</div><div class='ctx'> {</div><div class='ctx'> 	u32 mstatus, merrwarn;</div><div class='hunk'>@@ -429,13 +440,16 @@ static void svc_i3c_master_ibi_work(struct work_struct *work)</div><div class='ctx'> 	switch (ibitype) {</div><div class='ctx'> 	case SVC_I3C_MSTATUS_IBITYPE_IBI:</div><div class='ctx'> 		dev = svc_i3c_master_dev_from_addr(master, ibiaddr);</div><div class='del'>-		if (!dev)</div><div class='add'>+		if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI))</div><div class='ctx'> 			svc_i3c_master_nack_ibi(master);</div><div class='ctx'> 		else</div><div class='ctx'> 			svc_i3c_master_handle_ibi(master, dev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:</div><div class='del'>-		svc_i3c_master_ack_ibi(master, false);</div><div class='add'>+		if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))</div><div class='add'>+			svc_i3c_master_ack_ibi(master, false);</div><div class='add'>+		else</div><div class='add'>+			svc_i3c_master_nack_ibi(master);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:</div><div class='ctx'> 		svc_i3c_master_nack_ibi(master);</div><div class='hunk'>@@ -472,7 +486,9 @@ static void svc_i3c_master_ibi_work(struct work_struct *work)</div><div class='ctx'> 		svc_i3c_master_emit_stop(master);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:</div><div class='del'>-		queue_work(master-&gt;base.wq, &amp;master-&gt;hj_work);</div><div class='add'>+		svc_i3c_master_emit_stop(master);</div><div class='add'>+		if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))</div><div class='add'>+			queue_work(master-&gt;base.wq, &amp;master-&gt;hj_work);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1024,7 +1040,7 @@ static int svc_i3c_master_write(struct svc_i3c_master *master,</div><div class='ctx'> static int svc_i3c_master_xfer(struct svc_i3c_master *master,</div><div class='ctx'> 			       bool rnw, unsigned int xfer_type, u8 addr,</div><div class='ctx'> 			       u8 *in, const u8 *out, unsigned int xfer_len,</div><div class='del'>-			       unsigned int *read_len, bool continued)</div><div class='add'>+			       unsigned int *actual_len, bool continued)</div><div class='ctx'> {</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1037,7 +1053,7 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,</div><div class='ctx'> 	       SVC_I3C_MCTRL_IBIRESP_NACK |</div><div class='ctx'> 	       SVC_I3C_MCTRL_DIR(rnw) |</div><div class='ctx'> 	       SVC_I3C_MCTRL_ADDR(addr) |</div><div class='del'>-	       SVC_I3C_MCTRL_RDTERM(*read_len),</div><div class='add'>+	       SVC_I3C_MCTRL_RDTERM(*actual_len),</div><div class='ctx'> 	       master-&gt;regs + SVC_I3C_MCTRL);</div><div class='ctx'> </div><div class='ctx'> 	ret = readl_poll_timeout(master-&gt;regs + SVC_I3C_MSTATUS, reg,</div><div class='hunk'>@@ -1047,6 +1063,7 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,</div><div class='ctx'> </div><div class='ctx'> 	if (readl(master-&gt;regs + SVC_I3C_MERRWARN) &amp; SVC_I3C_MERRWARN_NACK) {</div><div class='ctx'> 		ret = -ENXIO;</div><div class='add'>+		*actual_len = 0;</div><div class='ctx'> 		goto emit_stop;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1064,6 +1081,7 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (SVC_I3C_MSTATUS_IBIWON(reg)) {</div><div class='ctx'> 		ret = -ENXIO;</div><div class='add'>+		*actual_len = 0;</div><div class='ctx'> 		goto emit_stop;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1075,7 +1093,7 @@ static int svc_i3c_master_xfer(struct svc_i3c_master *master,</div><div class='ctx'> 		goto emit_stop;</div><div class='ctx'> </div><div class='ctx'> 	if (rnw)</div><div class='del'>-		*read_len = ret;</div><div class='add'>+		*actual_len = ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = readl_poll_timeout(master-&gt;regs + SVC_I3C_MSTATUS, reg,</div><div class='ctx'> 				 SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000);</div><div class='hunk'>@@ -1157,8 +1175,12 @@ static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master)</div><div class='ctx'> </div><div class='ctx'> 		ret = svc_i3c_master_xfer(master, cmd-&gt;rnw, xfer-&gt;type,</div><div class='ctx'> 					  cmd-&gt;addr, cmd-&gt;in, cmd-&gt;out,</div><div class='del'>-					  cmd-&gt;len, &amp;cmd-&gt;read_len,</div><div class='add'>+					  cmd-&gt;len, &amp;cmd-&gt;actual_len,</div><div class='ctx'> 					  cmd-&gt;continued);</div><div class='add'>+		/* cmd-&gt;xfer is NULL if I2C or CCC transfer */</div><div class='add'>+		if (cmd-&gt;xfer)</div><div class='add'>+			cmd-&gt;xfer-&gt;actual_len = cmd-&gt;actual_len;</div><div class='add'>+</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1243,7 +1265,7 @@ static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master,</div><div class='ctx'> 	cmd-&gt;in = NULL;</div><div class='ctx'> 	cmd-&gt;out = buf;</div><div class='ctx'> 	cmd-&gt;len = xfer_len;</div><div class='del'>-	cmd-&gt;read_len = 0;</div><div class='add'>+	cmd-&gt;actual_len = 0;</div><div class='ctx'> 	cmd-&gt;continued = false;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;master-&gt;lock);</div><div class='hunk'>@@ -1263,7 +1285,7 @@ static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,</div><div class='ctx'> 					      struct i3c_ccc_cmd *ccc)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int xfer_len = ccc-&gt;dests[0].payload.len;</div><div class='del'>-	unsigned int read_len = ccc-&gt;rnw ? xfer_len : 0;</div><div class='add'>+	unsigned int actual_len = ccc-&gt;rnw ? xfer_len : 0;</div><div class='ctx'> 	struct svc_i3c_xfer *xfer;</div><div class='ctx'> 	struct svc_i3c_cmd *cmd;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1281,7 +1303,7 @@ static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,</div><div class='ctx'> 	cmd-&gt;in = NULL;</div><div class='ctx'> 	cmd-&gt;out = &amp;ccc-&gt;id;</div><div class='ctx'> 	cmd-&gt;len = 1;</div><div class='del'>-	cmd-&gt;read_len = 0;</div><div class='add'>+	cmd-&gt;actual_len = 0;</div><div class='ctx'> 	cmd-&gt;continued = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Directed message */</div><div class='hunk'>@@ -1291,7 +1313,7 @@ static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,</div><div class='ctx'> 	cmd-&gt;in = ccc-&gt;rnw ? ccc-&gt;dests[0].payload.data : NULL;</div><div class='ctx'> 	cmd-&gt;out = ccc-&gt;rnw ? NULL : ccc-&gt;dests[0].payload.data,</div><div class='ctx'> 	cmd-&gt;len = xfer_len;</div><div class='del'>-	cmd-&gt;read_len = read_len;</div><div class='add'>+	cmd-&gt;actual_len = actual_len;</div><div class='ctx'> 	cmd-&gt;continued = false;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;master-&gt;lock);</div><div class='hunk'>@@ -1300,8 +1322,8 @@ static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,</div><div class='ctx'> 		svc_i3c_master_dequeue_xfer(master, xfer);</div><div class='ctx'> 	mutex_unlock(&amp;master-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	if (cmd-&gt;read_len != xfer_len)</div><div class='del'>-		ccc-&gt;dests[0].payload.len = cmd-&gt;read_len;</div><div class='add'>+	if (cmd-&gt;actual_len != xfer_len)</div><div class='add'>+		ccc-&gt;dests[0].payload.len = cmd-&gt;actual_len;</div><div class='ctx'> </div><div class='ctx'> 	ret = xfer-&gt;ret;</div><div class='ctx'> 	svc_i3c_master_free_xfer(xfer);</div><div class='hunk'>@@ -1346,12 +1368,13 @@ static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev,</div><div class='ctx'> 	for (i = 0; i &lt; nxfers; i++) {</div><div class='ctx'> 		struct svc_i3c_cmd *cmd = &amp;xfer-&gt;cmds[i];</div><div class='ctx'> </div><div class='add'>+		cmd-&gt;xfer = &amp;xfers[i];</div><div class='ctx'> 		cmd-&gt;addr = master-&gt;addrs[data-&gt;index];</div><div class='ctx'> 		cmd-&gt;rnw = xfers[i].rnw;</div><div class='ctx'> 		cmd-&gt;in = xfers[i].rnw ? xfers[i].data.in : NULL;</div><div class='ctx'> 		cmd-&gt;out = xfers[i].rnw ? NULL : xfers[i].data.out;</div><div class='ctx'> 		cmd-&gt;len = xfers[i].len;</div><div class='del'>-		cmd-&gt;read_len = xfers[i].rnw ? xfers[i].len : 0;</div><div class='add'>+		cmd-&gt;actual_len = xfers[i].rnw ? xfers[i].len : 0;</div><div class='ctx'> 		cmd-&gt;continued = (i + 1) &lt; nxfers;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1391,7 +1414,7 @@ static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,</div><div class='ctx'> 		cmd-&gt;in = cmd-&gt;rnw ? xfers[i].buf : NULL;</div><div class='ctx'> 		cmd-&gt;out = cmd-&gt;rnw ? NULL : xfers[i].buf;</div><div class='ctx'> 		cmd-&gt;len = xfers[i].len;</div><div class='del'>-		cmd-&gt;read_len = cmd-&gt;rnw ? xfers[i].len : 0;</div><div class='add'>+		cmd-&gt;actual_len = cmd-&gt;rnw ? xfers[i].len : 0;</div><div class='ctx'> 		cmd-&gt;continued = (i + 1 &lt; nxfers);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1472,6 +1495,7 @@ static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	master-&gt;enabled_events |= SVC_I3C_EVENT_IBI;</div><div class='ctx'> 	svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);</div><div class='ctx'> </div><div class='ctx'> 	return i3c_master_enec_locked(m, dev-&gt;info.dyn_addr, I3C_CCC_EVENT_SIR);</div><div class='hunk'>@@ -1483,7 +1507,9 @@ static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev)</div><div class='ctx'> 	struct svc_i3c_master *master = to_svc_i3c_master(m);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	svc_i3c_master_disable_interrupts(master);</div><div class='add'>+	master-&gt;enabled_events &amp;= ~SVC_I3C_EVENT_IBI;</div><div class='add'>+	if (!master-&gt;enabled_events)</div><div class='add'>+		svc_i3c_master_disable_interrupts(master);</div><div class='ctx'> </div><div class='ctx'> 	ret = i3c_master_disec_locked(m, dev-&gt;info.dyn_addr, I3C_CCC_EVENT_SIR);</div><div class='ctx'> </div><div class='hunk'>@@ -1493,6 +1519,39 @@ static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int svc_i3c_master_enable_hotjoin(struct i3c_master_controller *m)</div><div class='add'>+{</div><div class='add'>+	struct svc_i3c_master *master = to_svc_i3c_master(m);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(master-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(master-&gt;dev, "&lt;%s&gt; Cannot get runtime PM.\n", __func__);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	master-&gt;enabled_events |= SVC_I3C_EVENT_HOTJOIN;</div><div class='add'>+</div><div class='add'>+	svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int svc_i3c_master_disable_hotjoin(struct i3c_master_controller *m)</div><div class='add'>+{</div><div class='add'>+	struct svc_i3c_master *master = to_svc_i3c_master(m);</div><div class='add'>+</div><div class='add'>+	master-&gt;enabled_events &amp;= ~SVC_I3C_EVENT_HOTJOIN;</div><div class='add'>+</div><div class='add'>+	if (!master-&gt;enabled_events)</div><div class='add'>+		svc_i3c_master_disable_interrupts(master);</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(master-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(master-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,</div><div class='ctx'> 					    struct i3c_ibi_slot *slot)</div><div class='ctx'> {</div><div class='hunk'>@@ -1519,6 +1578,8 @@ static const struct i3c_master_controller_ops svc_i3c_master_ops = {</div><div class='ctx'> 	.recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot,</div><div class='ctx'> 	.enable_ibi = svc_i3c_master_enable_ibi,</div><div class='ctx'> 	.disable_ibi = svc_i3c_master_disable_ibi,</div><div class='add'>+	.enable_hotjoin = svc_i3c_master_enable_hotjoin,</div><div class='add'>+	.disable_hotjoin = svc_i3c_master_disable_hotjoin,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)</div><div class='head'>diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c<br/>index dcda0afecfc5..bcf1198e8991 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/idle/intel_idle.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/idle/intel_idle.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/idle/intel_idle.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/idle/intel_idle.c</a></div><div class='hunk'>@@ -131,11 +131,12 @@ static unsigned int mwait_substates __initdata;</div><div class='ctx'> #define MWAIT2flg(eax) ((eax &amp; 0xFF) &lt;&lt; 24)</div><div class='ctx'> </div><div class='ctx'> static __always_inline int __intel_idle(struct cpuidle_device *dev,</div><div class='del'>-					struct cpuidle_driver *drv, int index)</div><div class='add'>+					struct cpuidle_driver *drv,</div><div class='add'>+					int index, bool irqoff)</div><div class='ctx'> {</div><div class='ctx'> 	struct cpuidle_state *state = &amp;drv-&gt;states[index];</div><div class='ctx'> 	unsigned long eax = flg2MWAIT(state-&gt;flags);</div><div class='del'>-	unsigned long ecx = 1; /* break on interrupt flag */</div><div class='add'>+	unsigned long ecx = 1*irqoff; /* break on interrupt flag */</div><div class='ctx'> </div><div class='ctx'> 	mwait_idle_with_hints(eax, ecx);</div><div class='ctx'> </div><div class='hunk'>@@ -159,19 +160,13 @@ static __always_inline int __intel_idle(struct cpuidle_device *dev,</div><div class='ctx'> static __cpuidle int intel_idle(struct cpuidle_device *dev,</div><div class='ctx'> 				struct cpuidle_driver *drv, int index)</div><div class='ctx'> {</div><div class='del'>-	return __intel_idle(dev, drv, index);</div><div class='add'>+	return __intel_idle(dev, drv, index, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static __cpuidle int intel_idle_irq(struct cpuidle_device *dev,</div><div class='ctx'> 				    struct cpuidle_driver *drv, int index)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	raw_local_irq_enable();</div><div class='del'>-	ret = __intel_idle(dev, drv, index);</div><div class='del'>-	raw_local_irq_disable();</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='add'>+	return __intel_idle(dev, drv, index, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,</div><div class='hunk'>@@ -184,7 +179,7 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,</div><div class='ctx'> 	if (smt_active)</div><div class='ctx'> 		__update_spec_ctrl(0);</div><div class='ctx'> </div><div class='del'>-	ret = __intel_idle(dev, drv, index);</div><div class='add'>+	ret = __intel_idle(dev, drv, index, true);</div><div class='ctx'> </div><div class='ctx'> 	if (smt_active)</div><div class='ctx'> 		__update_spec_ctrl(spec_ctrl);</div><div class='hunk'>@@ -196,7 +191,7 @@ static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,</div><div class='ctx'> 				       struct cpuidle_driver *drv, int index)</div><div class='ctx'> {</div><div class='ctx'> 	fpu_idle_fpregs();</div><div class='del'>-	return __intel_idle(dev, drv, index);</div><div class='add'>+	return __intel_idle(dev, drv, index, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -923,6 +918,35 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {</div><div class='ctx'> 		.enter = NULL }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct cpuidle_state mtl_l_cstates[] __initdata = {</div><div class='add'>+	{</div><div class='add'>+		.name = "C1E",</div><div class='add'>+		.desc = "MWAIT 0x01",</div><div class='add'>+		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,</div><div class='add'>+		.exit_latency = 1,</div><div class='add'>+		.target_residency = 1,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C6",</div><div class='add'>+		.desc = "MWAIT 0x20",</div><div class='add'>+		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,</div><div class='add'>+		.exit_latency = 140,</div><div class='add'>+		.target_residency = 420,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C10",</div><div class='add'>+		.desc = "MWAIT 0x60",</div><div class='add'>+		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,</div><div class='add'>+		.exit_latency = 310,</div><div class='add'>+		.target_residency = 930,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.enter = NULL }</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct cpuidle_state gmt_cstates[] __initdata = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "C1",</div><div class='hunk'>@@ -1242,6 +1266,72 @@ static struct cpuidle_state snr_cstates[] __initdata = {</div><div class='ctx'> 		.enter = NULL }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct cpuidle_state grr_cstates[] __initdata = {</div><div class='add'>+	{</div><div class='add'>+		.name = "C1",</div><div class='add'>+		.desc = "MWAIT 0x00",</div><div class='add'>+		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,</div><div class='add'>+		.exit_latency = 1,</div><div class='add'>+		.target_residency = 1,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C1E",</div><div class='add'>+		.desc = "MWAIT 0x01",</div><div class='add'>+		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,</div><div class='add'>+		.exit_latency = 2,</div><div class='add'>+		.target_residency = 10,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C6S",</div><div class='add'>+		.desc = "MWAIT 0x22",</div><div class='add'>+		.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,</div><div class='add'>+		.exit_latency = 140,</div><div class='add'>+		.target_residency = 500,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.enter = NULL }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct cpuidle_state srf_cstates[] __initdata = {</div><div class='add'>+	{</div><div class='add'>+		.name = "C1",</div><div class='add'>+		.desc = "MWAIT 0x00",</div><div class='add'>+		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,</div><div class='add'>+		.exit_latency = 1,</div><div class='add'>+		.target_residency = 1,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C1E",</div><div class='add'>+		.desc = "MWAIT 0x01",</div><div class='add'>+		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,</div><div class='add'>+		.exit_latency = 2,</div><div class='add'>+		.target_residency = 10,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C6S",</div><div class='add'>+		.desc = "MWAIT 0x22",</div><div class='add'>+		.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,</div><div class='add'>+		.exit_latency = 270,</div><div class='add'>+		.target_residency = 700,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.name = "C6SP",</div><div class='add'>+		.desc = "MWAIT 0x23",</div><div class='add'>+		.flags = MWAIT2flg(0x23) | CPUIDLE_FLAG_TLB_FLUSHED,</div><div class='add'>+		.exit_latency = 310,</div><div class='add'>+		.target_residency = 900,</div><div class='add'>+		.enter = &amp;intel_idle,</div><div class='add'>+		.enter_s2idle = intel_idle_s2idle, },</div><div class='add'>+	{</div><div class='add'>+		.enter = NULL }</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct idle_cpu idle_cpu_nehalem __initconst = {</div><div class='ctx'> 	.state_table = nehalem_cstates,</div><div class='ctx'> 	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,</div><div class='hunk'>@@ -1349,6 +1439,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {</div><div class='ctx'> 	.state_table = adl_l_cstates,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct idle_cpu idle_cpu_mtl_l __initconst = {</div><div class='add'>+	.state_table = mtl_l_cstates,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct idle_cpu idle_cpu_gmt __initconst = {</div><div class='ctx'> 	.state_table = gmt_cstates,</div><div class='ctx'> };</div><div class='hunk'>@@ -1387,6 +1481,18 @@ static const struct idle_cpu idle_cpu_snr __initconst = {</div><div class='ctx'> 	.use_acpi = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct idle_cpu idle_cpu_grr __initconst = {</div><div class='add'>+	.state_table = grr_cstates,</div><div class='add'>+	.disable_promotion_to_c1e = true,</div><div class='add'>+	.use_acpi = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct idle_cpu idle_cpu_srf __initconst = {</div><div class='add'>+	.state_table = srf_cstates,</div><div class='add'>+	.disable_promotion_to_c1e = true,</div><div class='add'>+	.use_acpi = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct x86_cpu_id intel_idle_ids[] __initconst = {</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP,		&amp;idle_cpu_nhx),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM,		&amp;idle_cpu_nehalem),</div><div class='hunk'>@@ -1423,6 +1529,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		&amp;idle_cpu_icx),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&amp;idle_cpu_adl),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&amp;idle_cpu_adl_l),</div><div class='add'>+	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L,	&amp;idle_cpu_mtl_l),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&amp;idle_cpu_gmt),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&amp;idle_cpu_spr),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&amp;idle_cpu_spr),</div><div class='hunk'>@@ -1432,6 +1539,8 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&amp;idle_cpu_bxt),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&amp;idle_cpu_dnv),</div><div class='ctx'> 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&amp;idle_cpu_snr),</div><div class='add'>+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT,	&amp;idle_cpu_grr),</div><div class='add'>+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X,	&amp;idle_cpu_srf),</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig<br/>index f113dae59048..91adcac875a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/accel/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/accel/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/accel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/Kconfig</a></div><div class='hunk'>@@ -260,10 +260,11 @@ config BMI088_ACCEL</div><div class='ctx'> 	select REGMAP</div><div class='ctx'> 	select BMI088_ACCEL_SPI</div><div class='ctx'> 	help</div><div class='del'>-	  Say yes here to build support for the Bosch BMI088 accelerometer.</div><div class='add'>+	  Say yes here to build support for the following Bosch accelerometers:</div><div class='add'>+	  BMI088, BMI085, BMI090L. Note that all of these are combo module that</div><div class='add'>+	  include both accelerometer and gyroscope.</div><div class='ctx'> </div><div class='del'>-	  This is a combo module with both accelerometer and gyroscope. This</div><div class='del'>-	  driver only implements the accelerometer part, which has its own</div><div class='add'>+	  This driver only implements the accelerometer part, which has its own</div><div class='ctx'> 	  address and register map. BMG160 provides the gyroscope driver.</div><div class='ctx'> </div><div class='ctx'> config BMI088_ACCEL_SPI</div><div class='head'>diff --git a/drivers/iio/accel/bmi088-accel-core.c b/drivers/iio/accel/bmi088-accel-core.c<br/>index 84edcc78d796..4d989708e6c3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/accel/bmi088-accel-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/accel/bmi088-accel-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/accel/bmi088-accel-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/bmi088-accel-core.c</a></div><div class='hunk'>@@ -2,6 +2,8 @@</div><div class='ctx'> /*</div><div class='ctx'>  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:</div><div class='ctx'>  *  - BMI088</div><div class='add'>+ *  - BMI085</div><div class='add'>+ *  - BMI090L</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (c) 2018-2021, Topic Embedded Products</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/iio/accel/bmi088-accel-spi.c b/drivers/iio/accel/bmi088-accel-spi.c<br/>index ee540edd8412..7b419a7b2478 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/accel/bmi088-accel-spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/accel/bmi088-accel-spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/accel/bmi088-accel-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/bmi088-accel-spi.c</a></div><div class='hunk'>@@ -2,6 +2,8 @@</div><div class='ctx'> /*</div><div class='ctx'>  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:</div><div class='ctx'>  *  - BMI088</div><div class='add'>+ *  - BMI085</div><div class='add'>+ *  - BMI090L</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (c) 2018-2020, Topic Embedded Products</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/iio/accel/kionix-kx022a.c b/drivers/iio/accel/kionix-kx022a.c<br/>index 60864be3a667..53d59a04ae15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/accel/kionix-kx022a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/accel/kionix-kx022a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/accel/kionix-kx022a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/accel/kionix-kx022a.c</a></div><div class='hunk'>@@ -393,17 +393,17 @@ static const unsigned int kx022a_odrs[] = {</div><div class='ctx'>  *	(range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2</div><div class='ctx'>  *	=&gt; KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed</div><div class='ctx'>  *	in low-power mode(?) )</div><div class='del'>- *	=&gt; +/-2G  =&gt; 4 / 2^16 * 9,80665 * 10^6 (to scale to micro)</div><div class='del'>- *	=&gt; +/-2G  - 598.550415</div><div class='del'>- *	   +/-4G  - 1197.10083</div><div class='del'>- *	   +/-8G  - 2394.20166</div><div class='del'>- *	   +/-16G - 4788.40332</div><div class='add'>+ *	=&gt; +/-2G  =&gt; 4 / 2^16 * 9,80665</div><div class='add'>+ *	=&gt; +/-2G  - 0.000598550415</div><div class='add'>+ *	   +/-4G  - 0.00119710083</div><div class='add'>+ *	   +/-8G  - 0.00239420166</div><div class='add'>+ *	   +/-16G - 0.00478840332</div><div class='ctx'>  */</div><div class='ctx'> static const int kx022a_scale_table[][2] = {</div><div class='del'>-	{ 598, 550415 },</div><div class='del'>-	{ 1197, 100830 },</div><div class='del'>-	{ 2394, 201660 },</div><div class='del'>-	{ 4788, 403320 },</div><div class='add'>+	{ 0, 598550 },</div><div class='add'>+	{ 0, 1197101 },</div><div class='add'>+	{ 0, 2394202 },</div><div class='add'>+	{ 0, 4788403 },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int kx022a_read_avail(struct iio_dev *indio_dev,</div><div class='hunk'>@@ -422,7 +422,7 @@ static int kx022a_read_avail(struct iio_dev *indio_dev,</div><div class='ctx'> 		*vals = (const int *)kx022a_scale_table;</div><div class='ctx'> 		*length = ARRAY_SIZE(kx022a_scale_table) *</div><div class='ctx'> 			  ARRAY_SIZE(kx022a_scale_table[0]);</div><div class='del'>-		*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		*type = IIO_VAL_INT_PLUS_NANO;</div><div class='ctx'> 		return IIO_AVAIL_LIST;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -485,6 +485,20 @@ static int kx022a_turn_on_unlock(struct kx022a_data *data)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int kx022a_write_raw_get_fmt(struct iio_dev *idev,</div><div class='add'>+				    struct iio_chan_spec const *chan,</div><div class='add'>+				    long mask)</div><div class='add'>+{</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int kx022a_write_raw(struct iio_dev *idev,</div><div class='ctx'> 			    struct iio_chan_spec const *chan,</div><div class='ctx'> 			    int val, int val2, long mask)</div><div class='hunk'>@@ -629,7 +643,7 @@ static int kx022a_read_raw(struct iio_dev *idev,</div><div class='ctx'> </div><div class='ctx'> 		kx022a_reg2scale(regval, val, val2);</div><div class='ctx'> </div><div class='del'>-		return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return -EINVAL;</div><div class='hunk'>@@ -856,6 +870,7 @@ static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples)</div><div class='ctx'> static const struct iio_info kx022a_info = {</div><div class='ctx'> 	.read_raw = &amp;kx022a_read_raw,</div><div class='ctx'> 	.write_raw = &amp;kx022a_write_raw,</div><div class='add'>+	.write_raw_get_fmt = &amp;kx022a_write_raw_get_fmt,</div><div class='ctx'> 	.read_avail = &amp;kx022a_read_avail,</div><div class='ctx'> </div><div class='ctx'> 	.validate_trigger	= iio_validate_own_trigger,</div><div class='head'>diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig<br/>index 35f9867da12c..3b73c509bd68 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/Kconfig</a></div><div class='hunk'>@@ -36,13 +36,29 @@ config AD4130</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module will be</div><div class='ctx'> 	  called ad4130.</div><div class='ctx'> </div><div class='add'>+config AD7091R</div><div class='add'>+	tristate</div><div class='add'>+</div><div class='ctx'> config AD7091R5</div><div class='ctx'> 	tristate "Analog Devices AD7091R5 ADC Driver"</div><div class='ctx'> 	depends on I2C</div><div class='add'>+	select AD7091R</div><div class='ctx'> 	select REGMAP_I2C</div><div class='ctx'> 	help</div><div class='ctx'> 	  Say yes here to build support for Analog Devices AD7091R-5 ADC.</div><div class='ctx'> </div><div class='add'>+config AD7091R8</div><div class='add'>+	tristate "Analog Devices AD7091R8 ADC Driver"</div><div class='add'>+	depends on SPI</div><div class='add'>+	select AD7091R</div><div class='add'>+	select REGMAP_SPI</div><div class='add'>+	help</div><div class='add'>+	  Say yes here to build support for Analog Devices AD7091R-2, AD7091R-4,</div><div class='add'>+	  and AD7091R-8 ADC.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module will be</div><div class='add'>+	  called ad7091r8.</div><div class='add'>+</div><div class='ctx'> config AD7124</div><div class='ctx'> 	tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver"</div><div class='ctx'> 	depends on SPI_MASTER</div><div class='hunk'>@@ -292,7 +308,7 @@ config ADI_AXI_ADC</div><div class='ctx'> 	select IIO_BUFFER</div><div class='ctx'> 	select IIO_BUFFER_HW_CONSUMER</div><div class='ctx'> 	select IIO_BUFFER_DMAENGINE</div><div class='del'>-	depends on HAS_IOMEM</div><div class='add'>+	select REGMAP_MMIO</div><div class='ctx'> 	depends on OF</div><div class='ctx'> 	help</div><div class='ctx'> 	  Say yes here to build support for Analog Devices Generic</div><div class='hunk'>@@ -745,6 +761,17 @@ config MAX1363</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module will be</div><div class='ctx'> 	  called max1363.</div><div class='ctx'> </div><div class='add'>+config MAX34408</div><div class='add'>+	tristate "Maxim max34408/max344089 ADC driver"</div><div class='add'>+	depends on I2C</div><div class='add'>+	help</div><div class='add'>+	  Say yes here to build support for Maxim max34408/max34409 current sense</div><div class='add'>+	  monitor with 8-bits ADC interface with overcurrent delay/threshold and</div><div class='add'>+	  shutdown delay.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module will be</div><div class='add'>+	  called max34408.</div><div class='add'>+</div><div class='ctx'> config MAX77541_ADC</div><div class='ctx'> 	tristate "Analog Devices MAX77541 ADC driver"</div><div class='ctx'> 	depends on MFD_MAX77541</div><div class='head'>diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile<br/>index bee11d442af4..d2fda54a3259 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/Makefile</a></div><div class='hunk'>@@ -7,7 +7,9 @@</div><div class='ctx'> obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o</div><div class='ctx'> obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o</div><div class='ctx'> obj-$(CONFIG_AD4130) += ad4130.o</div><div class='del'>-obj-$(CONFIG_AD7091R5) += ad7091r5.o ad7091r-base.o</div><div class='add'>+obj-$(CONFIG_AD7091R) += ad7091r-base.o</div><div class='add'>+obj-$(CONFIG_AD7091R5) += ad7091r5.o</div><div class='add'>+obj-$(CONFIG_AD7091R8) += ad7091r8.o</div><div class='ctx'> obj-$(CONFIG_AD7124) += ad7124.o</div><div class='ctx'> obj-$(CONFIG_AD7192) += ad7192.o</div><div class='ctx'> obj-$(CONFIG_AD7266) += ad7266.o</div><div class='hunk'>@@ -68,6 +70,7 @@ obj-$(CONFIG_MAX11205) += max11205.o</div><div class='ctx'> obj-$(CONFIG_MAX11410) += max11410.o</div><div class='ctx'> obj-$(CONFIG_MAX1241) += max1241.o</div><div class='ctx'> obj-$(CONFIG_MAX1363) += max1363.o</div><div class='add'>+obj-$(CONFIG_MAX34408) += max34408.o</div><div class='ctx'> obj-$(CONFIG_MAX77541_ADC) += max77541-adc.o</div><div class='ctx'> obj-$(CONFIG_MAX9611) += max9611.o</div><div class='ctx'> obj-$(CONFIG_MCP320X) += mcp320x.o</div><div class='head'>diff --git a/drivers/iio/adc/ad7091r-base.c b/drivers/iio/adc/ad7091r-base.c<br/>index 8e252cde735b..f4255b91acfc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r-base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/ad7091r-base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r-base.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/iio/events.h&gt;</div><div class='ctx'> #include &lt;linux/iio/iio.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='hunk'>@@ -15,67 +16,26 @@</div><div class='ctx'> </div><div class='ctx'> #include "ad7091r-base.h"</div><div class='ctx'> </div><div class='del'>-#define AD7091R_REG_RESULT  0</div><div class='del'>-#define AD7091R_REG_CHANNEL 1</div><div class='del'>-#define AD7091R_REG_CONF    2</div><div class='del'>-#define AD7091R_REG_ALERT   3</div><div class='del'>-#define AD7091R_REG_CH_LOW_LIMIT(ch) ((ch) * 3 + 4)</div><div class='del'>-#define AD7091R_REG_CH_HIGH_LIMIT(ch) ((ch) * 3 + 5)</div><div class='del'>-#define AD7091R_REG_CH_HYSTERESIS(ch) ((ch) * 3 + 6)</div><div class='del'>-</div><div class='del'>-/* AD7091R_REG_RESULT */</div><div class='del'>-#define AD7091R_REG_RESULT_CH_ID(x)	    (((x) &gt;&gt; 13) &amp; 0x3)</div><div class='del'>-#define AD7091R_REG_RESULT_CONV_RESULT(x)   ((x) &amp; 0xfff)</div><div class='del'>-</div><div class='del'>-/* AD7091R_REG_CONF */</div><div class='del'>-#define AD7091R_REG_CONF_AUTO   BIT(8)</div><div class='del'>-#define AD7091R_REG_CONF_CMD    BIT(10)</div><div class='del'>-</div><div class='del'>-#define AD7091R_REG_CONF_MODE_MASK  \</div><div class='del'>-	(AD7091R_REG_CONF_AUTO | AD7091R_REG_CONF_CMD)</div><div class='del'>-</div><div class='del'>-enum ad7091r_mode {</div><div class='del'>-	AD7091R_MODE_SAMPLE,</div><div class='del'>-	AD7091R_MODE_COMMAND,</div><div class='del'>-	AD7091R_MODE_AUTOCYCLE,</div><div class='add'>+const struct iio_event_spec ad7091r_events[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_THRESH,</div><div class='add'>+		.dir = IIO_EV_DIR_RISING,</div><div class='add'>+		.mask_separate = BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				 BIT(IIO_EV_INFO_ENABLE),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_THRESH,</div><div class='add'>+		.dir = IIO_EV_DIR_FALLING,</div><div class='add'>+		.mask_separate = BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				 BIT(IIO_EV_INFO_ENABLE),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_THRESH,</div><div class='add'>+		.dir = IIO_EV_DIR_EITHER,</div><div class='add'>+		.mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),</div><div class='add'>+	},</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-struct ad7091r_state {</div><div class='del'>-	struct device *dev;</div><div class='del'>-	struct regmap *map;</div><div class='del'>-	struct regulator *vref;</div><div class='del'>-	const struct ad7091r_chip_info *chip_info;</div><div class='del'>-	enum ad7091r_mode mode;</div><div class='del'>-	struct mutex lock; /*lock to prevent concurent reads */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int ad7091r_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)</div><div class='del'>-{</div><div class='del'>-	int ret, conf;</div><div class='del'>-</div><div class='del'>-	switch (mode) {</div><div class='del'>-	case AD7091R_MODE_SAMPLE:</div><div class='del'>-		conf = 0;</div><div class='del'>-		break;</div><div class='del'>-	case AD7091R_MODE_COMMAND:</div><div class='del'>-		conf = AD7091R_REG_CONF_CMD;</div><div class='del'>-		break;</div><div class='del'>-	case AD7091R_MODE_AUTOCYCLE:</div><div class='del'>-		conf = AD7091R_REG_CONF_AUTO;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = regmap_update_bits(st-&gt;map, AD7091R_REG_CONF,</div><div class='del'>-				 AD7091R_REG_CONF_MODE_MASK, conf);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	st-&gt;mode = mode;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(ad7091r_events, IIO_AD7091R);</div><div class='ctx'> </div><div class='ctx'> static int ad7091r_set_channel(struct ad7091r_state *st, unsigned int channel)</div><div class='ctx'> {</div><div class='hunk'>@@ -110,7 +70,7 @@ static int ad7091r_read_one(struct iio_dev *iio_dev,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (AD7091R_REG_RESULT_CH_ID(val) != channel)</div><div class='add'>+	if (st-&gt;chip_info-&gt;reg_result_chan_id(val) != channel)</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	*read_val = AD7091R_REG_RESULT_CONV_RESULT(val);</div><div class='hunk'>@@ -168,14 +128,148 @@ unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ad7091r_read_event_config(struct iio_dev *indio_dev,</div><div class='add'>+				     const struct iio_chan_spec *chan,</div><div class='add'>+				     enum iio_event_type type,</div><div class='add'>+				     enum iio_event_direction dir)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = iio_priv(indio_dev);</div><div class='add'>+	int val, ret;</div><div class='add'>+</div><div class='add'>+	switch (dir) {</div><div class='add'>+	case IIO_EV_DIR_RISING:</div><div class='add'>+		ret = regmap_read(st-&gt;map,</div><div class='add'>+				  AD7091R_REG_CH_HIGH_LIMIT(chan-&gt;channel),</div><div class='add'>+				  &amp;val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		return val != AD7091R_HIGH_LIMIT;</div><div class='add'>+	case IIO_EV_DIR_FALLING:</div><div class='add'>+		ret = regmap_read(st-&gt;map,</div><div class='add'>+				  AD7091R_REG_CH_LOW_LIMIT(chan-&gt;channel),</div><div class='add'>+				  &amp;val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		return val != AD7091R_LOW_LIMIT;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r_write_event_config(struct iio_dev *indio_dev,</div><div class='add'>+				      const struct iio_chan_spec *chan,</div><div class='add'>+				      enum iio_event_type type,</div><div class='add'>+				      enum iio_event_direction dir, int state)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	if (state) {</div><div class='add'>+		return regmap_set_bits(st-&gt;map, AD7091R_REG_CONF,</div><div class='add'>+				       AD7091R_REG_CONF_ALERT_EN);</div><div class='add'>+	} else {</div><div class='add'>+		/*</div><div class='add'>+		 * Set thresholds either to 0 or to 2^12 - 1 as appropriate to</div><div class='add'>+		 * prevent alerts and thus disable event generation.</div><div class='add'>+		 */</div><div class='add'>+		switch (dir) {</div><div class='add'>+		case IIO_EV_DIR_RISING:</div><div class='add'>+			return regmap_write(st-&gt;map,</div><div class='add'>+					    AD7091R_REG_CH_HIGH_LIMIT(chan-&gt;channel),</div><div class='add'>+					    AD7091R_HIGH_LIMIT);</div><div class='add'>+		case IIO_EV_DIR_FALLING:</div><div class='add'>+			return regmap_write(st-&gt;map,</div><div class='add'>+					    AD7091R_REG_CH_LOW_LIMIT(chan-&gt;channel),</div><div class='add'>+					    AD7091R_LOW_LIMIT);</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r_read_event_value(struct iio_dev *indio_dev,</div><div class='add'>+				    const struct iio_chan_spec *chan,</div><div class='add'>+				    enum iio_event_type type,</div><div class='add'>+				    enum iio_event_direction dir,</div><div class='add'>+				    enum iio_event_info info, int *val, int *val2)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (info) {</div><div class='add'>+	case IIO_EV_INFO_VALUE:</div><div class='add'>+		switch (dir) {</div><div class='add'>+		case IIO_EV_DIR_RISING:</div><div class='add'>+			ret = regmap_read(st-&gt;map,</div><div class='add'>+					  AD7091R_REG_CH_HIGH_LIMIT(chan-&gt;channel),</div><div class='add'>+					  val);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+			return IIO_VAL_INT;</div><div class='add'>+		case IIO_EV_DIR_FALLING:</div><div class='add'>+			ret = regmap_read(st-&gt;map,</div><div class='add'>+					  AD7091R_REG_CH_LOW_LIMIT(chan-&gt;channel),</div><div class='add'>+					  val);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+			return IIO_VAL_INT;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_INFO_HYSTERESIS:</div><div class='add'>+		ret = regmap_read(st-&gt;map,</div><div class='add'>+				  AD7091R_REG_CH_HYSTERESIS(chan-&gt;channel),</div><div class='add'>+				  val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r_write_event_value(struct iio_dev *indio_dev,</div><div class='add'>+				     const struct iio_chan_spec *chan,</div><div class='add'>+				     enum iio_event_type type,</div><div class='add'>+				     enum iio_event_direction dir,</div><div class='add'>+				     enum iio_event_info info, int val, int val2)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	switch (info) {</div><div class='add'>+	case IIO_EV_INFO_VALUE:</div><div class='add'>+		switch (dir) {</div><div class='add'>+		case IIO_EV_DIR_RISING:</div><div class='add'>+			return regmap_write(st-&gt;map,</div><div class='add'>+					    AD7091R_REG_CH_HIGH_LIMIT(chan-&gt;channel),</div><div class='add'>+					    val);</div><div class='add'>+		case IIO_EV_DIR_FALLING:</div><div class='add'>+			return regmap_write(st-&gt;map,</div><div class='add'>+					    AD7091R_REG_CH_LOW_LIMIT(chan-&gt;channel),</div><div class='add'>+					    val);</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_INFO_HYSTERESIS:</div><div class='add'>+		return regmap_write(st-&gt;map,</div><div class='add'>+				    AD7091R_REG_CH_HYSTERESIS(chan-&gt;channel),</div><div class='add'>+				    val);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct iio_info ad7091r_info = {</div><div class='ctx'> 	.read_raw = ad7091r_read_raw,</div><div class='add'>+	.read_event_config = &amp;ad7091r_read_event_config,</div><div class='add'>+	.write_event_config = &amp;ad7091r_write_event_config,</div><div class='add'>+	.read_event_value = &amp;ad7091r_read_event_value,</div><div class='add'>+	.write_event_value = &amp;ad7091r_write_event_value,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t ad7091r_event_handler(int irq, void *private)</div><div class='ctx'> {</div><div class='del'>-	struct ad7091r_state *st = (struct ad7091r_state *) private;</div><div class='del'>-	struct iio_dev *iio_dev = dev_get_drvdata(st-&gt;dev);</div><div class='add'>+	struct iio_dev *iio_dev = private;</div><div class='add'>+	struct ad7091r_state *st = iio_priv(iio_dev);</div><div class='ctx'> 	unsigned int i, read_val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	s64 timestamp = iio_get_time_ns(iio_dev);</div><div class='hunk'>@@ -207,9 +301,8 @@ static void ad7091r_remove(void *data)</div><div class='ctx'> 	regulator_disable(st-&gt;vref);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ad7091r_probe(struct device *dev, const char *name,</div><div class='del'>-		const struct ad7091r_chip_info *chip_info,</div><div class='del'>-		struct regmap *map, int irq)</div><div class='add'>+int ad7091r_probe(struct device *dev, const struct ad7091r_init_info *init_info,</div><div class='add'>+		  int irq)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dev *iio_dev;</div><div class='ctx'> 	struct ad7091r_state *st;</div><div class='hunk'>@@ -221,29 +314,54 @@ int ad7091r_probe(struct device *dev, const char *name,</div><div class='ctx'> </div><div class='ctx'> 	st = iio_priv(iio_dev);</div><div class='ctx'> 	st-&gt;dev = dev;</div><div class='del'>-	st-&gt;chip_info = chip_info;</div><div class='del'>-	st-&gt;map = map;</div><div class='add'>+	init_info-&gt;init_adc_regmap(st, init_info-&gt;regmap_config);</div><div class='add'>+	if (IS_ERR(st-&gt;map))</div><div class='add'>+		return dev_err_probe(st-&gt;dev, PTR_ERR(st-&gt;map),</div><div class='add'>+				     "Error initializing regmap\n");</div><div class='ctx'> </div><div class='del'>-	iio_dev-&gt;name = name;</div><div class='ctx'> 	iio_dev-&gt;info = &amp;ad7091r_info;</div><div class='ctx'> 	iio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='ctx'> </div><div class='del'>-	iio_dev-&gt;num_channels = chip_info-&gt;num_channels;</div><div class='del'>-	iio_dev-&gt;channels = chip_info-&gt;channels;</div><div class='add'>+	if (init_info-&gt;setup) {</div><div class='add'>+		ret = init_info-&gt;setup(st);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (irq) {</div><div class='add'>+		st-&gt;chip_info = init_info-&gt;info_irq;</div><div class='add'>+		ret = regmap_update_bits(st-&gt;map, AD7091R_REG_CONF,</div><div class='add'>+					 AD7091R_REG_CONF_ALERT_EN, BIT(4));</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='ctx'> 		ret = devm_request_threaded_irq(dev, irq, NULL,</div><div class='del'>-				ad7091r_event_handler,</div><div class='del'>-				IRQF_TRIGGER_FALLING | IRQF_ONESHOT, name, st);</div><div class='add'>+						ad7091r_event_handler,</div><div class='add'>+						IRQF_TRIGGER_FALLING |</div><div class='add'>+						IRQF_ONESHOT,</div><div class='add'>+						st-&gt;chip_info-&gt;name, iio_dev);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='add'>+	} else {</div><div class='add'>+		st-&gt;chip_info = init_info-&gt;info_no_irq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	iio_dev-&gt;name = st-&gt;chip_info-&gt;name;</div><div class='add'>+	iio_dev-&gt;num_channels = st-&gt;chip_info-&gt;num_channels;</div><div class='add'>+	iio_dev-&gt;channels = st-&gt;chip_info-&gt;channels;</div><div class='add'>+</div><div class='ctx'> 	st-&gt;vref = devm_regulator_get_optional(dev, "vref");</div><div class='ctx'> 	if (IS_ERR(st-&gt;vref)) {</div><div class='ctx'> 		if (PTR_ERR(st-&gt;vref) == -EPROBE_DEFER)</div><div class='ctx'> 			return -EPROBE_DEFER;</div><div class='add'>+</div><div class='ctx'> 		st-&gt;vref = NULL;</div><div class='add'>+		/* Enable internal vref */</div><div class='add'>+		ret = regmap_set_bits(st-&gt;map, AD7091R_REG_CONF,</div><div class='add'>+				      AD7091R_REG_CONF_INT_VREF);</div><div class='add'>+		if (ret)</div><div class='add'>+			return dev_err_probe(st-&gt;dev, ret,</div><div class='add'>+					     "Error on enable internal reference\n");</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = regulator_enable(st-&gt;vref);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -254,7 +372,7 @@ int ad7091r_probe(struct device *dev, const char *name,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Use command mode by default to convert only desired channels*/</div><div class='del'>-	ret = ad7091r_set_mode(st, AD7091R_MODE_COMMAND);</div><div class='add'>+	ret = st-&gt;chip_info-&gt;set_mode(st, AD7091R_MODE_COMMAND);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -262,7 +380,7 @@ int ad7091r_probe(struct device *dev, const char *name,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(ad7091r_probe, IIO_AD7091R);</div><div class='ctx'> </div><div class='del'>-static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)</div><div class='add'>+bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)</div><div class='ctx'> {</div><div class='ctx'> 	switch (reg) {</div><div class='ctx'> 	case AD7091R_REG_RESULT:</div><div class='hunk'>@@ -272,8 +390,9 @@ static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(ad7091r_writeable_reg, IIO_AD7091R);</div><div class='ctx'> </div><div class='del'>-static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)</div><div class='add'>+bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)</div><div class='ctx'> {</div><div class='ctx'> 	switch (reg) {</div><div class='ctx'> 	case AD7091R_REG_RESULT:</div><div class='hunk'>@@ -283,14 +402,7 @@ static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-const struct regmap_config ad7091r_regmap_config = {</div><div class='del'>-	.reg_bits = 8,</div><div class='del'>-	.val_bits = 16,</div><div class='del'>-	.writeable_reg = ad7091r_writeable_reg,</div><div class='del'>-	.volatile_reg = ad7091r_volatile_reg,</div><div class='del'>-};</div><div class='del'>-EXPORT_SYMBOL_NS_GPL(ad7091r_regmap_config, IIO_AD7091R);</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(ad7091r_volatile_reg, IIO_AD7091R);</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Beniamin Bia &lt;beniamin.bia@analog.com&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("Analog Devices AD7091Rx multi-channel converters");</div><div class='head'>diff --git a/drivers/iio/adc/ad7091r-base.h b/drivers/iio/adc/ad7091r-base.h<br/>index 509748aef9b1..696bf7a897bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r-base.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/ad7091r-base.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r-base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r-base.h</a></div><div class='hunk'>@@ -8,19 +8,92 @@</div><div class='ctx'> #ifndef __DRIVERS_IIO_ADC_AD7091R_BASE_H__</div><div class='ctx'> #define __DRIVERS_IIO_ADC_AD7091R_BASE_H__</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#define AD7091R_REG_RESULT  0</div><div class='add'>+#define AD7091R_REG_CHANNEL 1</div><div class='add'>+#define AD7091R_REG_CONF    2</div><div class='add'>+#define AD7091R_REG_ALERT   3</div><div class='add'>+#define AD7091R_REG_CH_LOW_LIMIT(ch) ((ch) * 3 + 4)</div><div class='add'>+#define AD7091R_REG_CH_HIGH_LIMIT(ch) ((ch) * 3 + 5)</div><div class='add'>+#define AD7091R_REG_CH_HYSTERESIS(ch) ((ch) * 3 + 6)</div><div class='add'>+</div><div class='add'>+/* AD7091R_REG_RESULT */</div><div class='add'>+#define AD7091R5_REG_RESULT_CH_ID(x)	    (((x) &gt;&gt; 13) &amp; 0x3)</div><div class='add'>+#define AD7091R8_REG_RESULT_CH_ID(x)	    (((x) &gt;&gt; 13) &amp; 0x7)</div><div class='add'>+#define AD7091R_REG_RESULT_CONV_RESULT(x)   ((x) &amp; 0xfff)</div><div class='add'>+</div><div class='add'>+/* AD7091R_REG_CONF */</div><div class='add'>+#define AD7091R_REG_CONF_INT_VREF	BIT(0)</div><div class='add'>+#define AD7091R_REG_CONF_ALERT_EN	BIT(4)</div><div class='add'>+#define AD7091R_REG_CONF_AUTO		BIT(8)</div><div class='add'>+#define AD7091R_REG_CONF_CMD		BIT(10)</div><div class='add'>+</div><div class='add'>+#define AD7091R_REG_CONF_MODE_MASK  \</div><div class='add'>+	(AD7091R_REG_CONF_AUTO | AD7091R_REG_CONF_CMD)</div><div class='add'>+</div><div class='add'>+/* AD7091R_REG_CH_LIMIT */</div><div class='add'>+#define AD7091R_HIGH_LIMIT		0xFFF</div><div class='add'>+#define AD7091R_LOW_LIMIT		0x0</div><div class='add'>+</div><div class='add'>+#define AD7091R_CHANNEL(idx, bits, ev, num_ev) {			\</div><div class='add'>+	.type = IIO_VOLTAGE,						\</div><div class='add'>+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\</div><div class='add'>+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\</div><div class='add'>+	.indexed = 1,							\</div><div class='add'>+	.channel = idx,							\</div><div class='add'>+	.event_spec = ev,						\</div><div class='add'>+	.num_event_specs = num_ev,					\</div><div class='add'>+	.scan_type.storagebits = 16,					\</div><div class='add'>+	.scan_type.realbits = bits,					\</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct device;</div><div class='del'>-struct ad7091r_state;</div><div class='add'>+struct gpio_desc;</div><div class='add'>+</div><div class='add'>+enum ad7091r_mode {</div><div class='add'>+	AD7091R_MODE_SAMPLE,</div><div class='add'>+	AD7091R_MODE_COMMAND,</div><div class='add'>+	AD7091R_MODE_AUTOCYCLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ad7091r_state {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct regmap *map;</div><div class='add'>+	struct gpio_desc *convst_gpio;</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct regulator *vref;</div><div class='add'>+	const struct ad7091r_chip_info *chip_info;</div><div class='add'>+	enum ad7091r_mode mode;</div><div class='add'>+	struct mutex lock; /*lock to prevent concurent reads */</div><div class='add'>+	__be16 tx_buf __aligned(IIO_DMA_MINALIGN);</div><div class='add'>+	__be16 rx_buf;</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> struct ad7091r_chip_info {</div><div class='add'>+	const char *name;</div><div class='ctx'> 	unsigned int num_channels;</div><div class='ctx'> 	const struct iio_chan_spec *channels;</div><div class='ctx'> 	unsigned int vref_mV;</div><div class='add'>+	unsigned int (*reg_result_chan_id)(unsigned int val);</div><div class='add'>+	int (*set_mode)(struct ad7091r_state *st, enum ad7091r_mode mode);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-extern const struct regmap_config ad7091r_regmap_config;</div><div class='add'>+struct ad7091r_init_info {</div><div class='add'>+	const struct ad7091r_chip_info *info_irq;</div><div class='add'>+	const struct ad7091r_chip_info *info_no_irq;</div><div class='add'>+	const struct regmap_config *regmap_config;</div><div class='add'>+	void (*init_adc_regmap)(struct ad7091r_state *st,</div><div class='add'>+				const struct regmap_config *regmap_conf);</div><div class='add'>+	int (*setup)(struct ad7091r_state *st);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+extern const struct iio_event_spec ad7091r_events[3];</div><div class='add'>+</div><div class='add'>+int ad7091r_probe(struct device *dev, const struct ad7091r_init_info *init_info,</div><div class='add'>+		  int irq);</div><div class='ctx'> </div><div class='del'>-int ad7091r_probe(struct device *dev, const char *name,</div><div class='del'>-		const struct ad7091r_chip_info *chip_info,</div><div class='del'>-		struct regmap *map, int irq);</div><div class='add'>+bool ad7091r_volatile_reg(struct device *dev, unsigned int reg);</div><div class='add'>+bool ad7091r_writeable_reg(struct device *dev, unsigned int reg);</div><div class='ctx'> </div><div class='ctx'> #endif /* __DRIVERS_IIO_ADC_AD7091R_BASE_H__ */</div><div class='head'>diff --git a/drivers/iio/adc/ad7091r5.c b/drivers/iio/adc/ad7091r5.c<br/>index 2f048527b7b7..a75837334157 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/ad7091r5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r5.c</a></div><div class='hunk'>@@ -12,42 +12,11 @@</div><div class='ctx'> </div><div class='ctx'> #include "ad7091r-base.h"</div><div class='ctx'> </div><div class='del'>-static const struct iio_event_spec ad7091r5_events[] = {</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_EV_TYPE_THRESH,</div><div class='del'>-		.dir = IIO_EV_DIR_RISING,</div><div class='del'>-		.mask_separate = BIT(IIO_EV_INFO_VALUE) |</div><div class='del'>-				 BIT(IIO_EV_INFO_ENABLE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_EV_TYPE_THRESH,</div><div class='del'>-		.dir = IIO_EV_DIR_FALLING,</div><div class='del'>-		.mask_separate = BIT(IIO_EV_INFO_VALUE) |</div><div class='del'>-				 BIT(IIO_EV_INFO_ENABLE),</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_EV_TYPE_THRESH,</div><div class='del'>-		.dir = IIO_EV_DIR_EITHER,</div><div class='del'>-		.mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define AD7091R_CHANNEL(idx, bits, ev, num_ev) { \</div><div class='del'>-	.type = IIO_VOLTAGE, \</div><div class='del'>-	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \</div><div class='del'>-	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \</div><div class='del'>-	.indexed = 1, \</div><div class='del'>-	.channel = idx, \</div><div class='del'>-	.event_spec = ev, \</div><div class='del'>-	.num_event_specs = num_ev, \</div><div class='del'>-	.scan_type.storagebits = 16, \</div><div class='del'>-	.scan_type.realbits = bits, \</div><div class='del'>-}</div><div class='ctx'> static const struct iio_chan_spec ad7091r5_channels_irq[] = {</div><div class='del'>-	AD7091R_CHANNEL(0, 12, ad7091r5_events, ARRAY_SIZE(ad7091r5_events)),</div><div class='del'>-	AD7091R_CHANNEL(1, 12, ad7091r5_events, ARRAY_SIZE(ad7091r5_events)),</div><div class='del'>-	AD7091R_CHANNEL(2, 12, ad7091r5_events, ARRAY_SIZE(ad7091r5_events)),</div><div class='del'>-	AD7091R_CHANNEL(3, 12, ad7091r5_events, ARRAY_SIZE(ad7091r5_events)),</div><div class='add'>+	AD7091R_CHANNEL(0, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(2, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(3, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct iio_chan_spec ad7091r5_channels_noirq[] = {</div><div class='hunk'>@@ -57,43 +26,98 @@ static const struct iio_chan_spec ad7091r5_channels_noirq[] = {</div><div class='ctx'> 	AD7091R_CHANNEL(3, 12, NULL, 0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int ad7091r5_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)</div><div class='add'>+{</div><div class='add'>+	int ret, conf;</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case AD7091R_MODE_SAMPLE:</div><div class='add'>+		conf = 0;</div><div class='add'>+		break;</div><div class='add'>+	case AD7091R_MODE_COMMAND:</div><div class='add'>+		conf = AD7091R_REG_CONF_CMD;</div><div class='add'>+		break;</div><div class='add'>+	case AD7091R_MODE_AUTOCYCLE:</div><div class='add'>+		conf = AD7091R_REG_CONF_AUTO;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(st-&gt;map, AD7091R_REG_CONF,</div><div class='add'>+				 AD7091R_REG_CONF_MODE_MASK, conf);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	st-&gt;mode = mode;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int ad7091r5_reg_result_chan_id(unsigned int val)</div><div class='add'>+{</div><div class='add'>+	return AD7091R5_REG_RESULT_CH_ID(val);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct ad7091r_chip_info ad7091r5_chip_info_irq = {</div><div class='add'>+	.name = "ad7091r-5",</div><div class='ctx'> 	.channels = ad7091r5_channels_irq,</div><div class='ctx'> 	.num_channels = ARRAY_SIZE(ad7091r5_channels_irq),</div><div class='ctx'> 	.vref_mV = 2500,</div><div class='add'>+	.reg_result_chan_id = &amp;ad7091r5_reg_result_chan_id,</div><div class='add'>+	.set_mode = &amp;ad7091r5_set_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct ad7091r_chip_info ad7091r5_chip_info_noirq = {</div><div class='add'>+	.name = "ad7091r-5",</div><div class='ctx'> 	.channels = ad7091r5_channels_noirq,</div><div class='ctx'> 	.num_channels = ARRAY_SIZE(ad7091r5_channels_noirq),</div><div class='ctx'> 	.vref_mV = 2500,</div><div class='add'>+	.reg_result_chan_id = &amp;ad7091r5_reg_result_chan_id,</div><div class='add'>+	.set_mode = &amp;ad7091r5_set_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int ad7091r5_i2c_probe(struct i2c_client *i2c)</div><div class='add'>+static const struct regmap_config ad7091r_regmap_config = {</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+	.writeable_reg = ad7091r_writeable_reg,</div><div class='add'>+	.volatile_reg = ad7091r_volatile_reg,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void ad7091r5_regmap_init(struct ad7091r_state *st,</div><div class='add'>+				 const struct regmap_config *regmap_conf)</div><div class='ctx'> {</div><div class='del'>-	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);</div><div class='del'>-	const struct ad7091r_chip_info *chip_info;</div><div class='del'>-	struct regmap *map = devm_regmap_init_i2c(i2c, &amp;ad7091r_regmap_config);</div><div class='add'>+	struct i2c_client *i2c = container_of(st-&gt;dev, struct i2c_client, dev);</div><div class='ctx'> </div><div class='del'>-	if (IS_ERR(map))</div><div class='del'>-		return PTR_ERR(map);</div><div class='add'>+	st-&gt;map = devm_regmap_init_i2c(i2c, regmap_conf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct ad7091r_init_info ad7091r5_init_info = {</div><div class='add'>+	.info_irq = &amp;ad7091r5_chip_info_irq,</div><div class='add'>+	.info_no_irq = &amp;ad7091r5_chip_info_noirq,</div><div class='add'>+	.regmap_config = &amp;ad7091r_regmap_config,</div><div class='add'>+	.init_adc_regmap = &amp;ad7091r5_regmap_init</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ad7091r5_i2c_probe(struct i2c_client *i2c)</div><div class='add'>+{</div><div class='add'>+	const struct ad7091r_init_info *init_info;</div><div class='ctx'> </div><div class='del'>-	if (i2c-&gt;irq)</div><div class='del'>-		chip_info = &amp;ad7091r5_chip_info_irq;</div><div class='del'>-	else</div><div class='del'>-		chip_info = &amp;ad7091r5_chip_info_noirq;</div><div class='add'>+	init_info = i2c_get_match_data(i2c);</div><div class='add'>+	if (!init_info)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return ad7091r_probe(&amp;i2c-&gt;dev, id-&gt;name, chip_info, map, i2c-&gt;irq);</div><div class='add'>+	return ad7091r_probe(&amp;i2c-&gt;dev, init_info, i2c-&gt;irq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ad7091r5_dt_ids[] = {</div><div class='del'>-	{ .compatible = "adi,ad7091r5" },</div><div class='add'>+	{ .compatible = "adi,ad7091r5", .data = &amp;ad7091r5_init_info },</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, ad7091r5_dt_ids);</div><div class='ctx'> </div><div class='ctx'> static const struct i2c_device_id ad7091r5_i2c_ids[] = {</div><div class='del'>-	{"ad7091r5", 0},</div><div class='add'>+	{"ad7091r5", (kernel_ulong_t)&amp;ad7091r5_init_info },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, ad7091r5_i2c_ids);</div><div class='head'>diff --git a/drivers/iio/adc/ad7091r8.c b/drivers/iio/adc/ad7091r8.c<br/>new file mode 100644<br/>index 000000000000..57700f124803<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad7091r8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad7091r8.c</a></div><div class='hunk'>@@ -0,0 +1,272 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Analog Devices AD7091R8 12-bit SAR ADC driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 Analog Devices Inc.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/spi/spi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "ad7091r-base.h"</div><div class='add'>+</div><div class='add'>+#define AD7091R8_REG_ADDR_MSK				GENMASK(15, 11)</div><div class='add'>+#define AD7091R8_RD_WR_FLAG_MSK				BIT(10)</div><div class='add'>+#define AD7091R8_REG_DATA_MSK				GENMASK(9, 0)</div><div class='add'>+</div><div class='add'>+#define AD7091R_SPI_REGMAP_CONFIG(n) {					\</div><div class='add'>+	.reg_bits = 8,							\</div><div class='add'>+	.val_bits = 16,							\</div><div class='add'>+	.volatile_reg = ad7091r_volatile_reg,				\</div><div class='add'>+	.writeable_reg = ad7091r_writeable_reg,				\</div><div class='add'>+	.max_register = AD7091R_REG_CH_HYSTERESIS(n),			\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r8_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)</div><div class='add'>+{</div><div class='add'>+	/* AD7091R-2/-4/-8 don't set sample/command/autocycle mode in conf reg */</div><div class='add'>+	st-&gt;mode = mode;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int ad7091r8_reg_result_chan_id(unsigned int val)</div><div class='add'>+{</div><div class='add'>+	return AD7091R8_REG_RESULT_CH_ID(val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define AD7091R_SPI_CHIP_INFO(_n, _name) {				\</div><div class='add'>+	.name = _name,							\</div><div class='add'>+	.channels = ad7091r##_n##_channels,				\</div><div class='add'>+	.num_channels = ARRAY_SIZE(ad7091r##_n##_channels),		\</div><div class='add'>+	.vref_mV = 2500,						\</div><div class='add'>+	.reg_result_chan_id = &amp;ad7091r8_reg_result_chan_id,	\</div><div class='add'>+	.set_mode = &amp;ad7091r8_set_mode,				\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define AD7091R_SPI_CHIP_INFO_IRQ(_n, _name) {				\</div><div class='add'>+	.name = _name,							\</div><div class='add'>+	.channels = ad7091r##_n##_channels_irq,				\</div><div class='add'>+	.num_channels = ARRAY_SIZE(ad7091r##_n##_channels_irq),		\</div><div class='add'>+	.vref_mV = 2500,						\</div><div class='add'>+	.reg_result_chan_id = &amp;ad7091r8_reg_result_chan_id,	\</div><div class='add'>+	.set_mode = &amp;ad7091r8_set_mode,				\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum ad7091r8_info_ids {</div><div class='add'>+	AD7091R2_INFO,</div><div class='add'>+	AD7091R4_INFO,</div><div class='add'>+	AD7091R4_INFO_IRQ,</div><div class='add'>+	AD7091R8_INFO,</div><div class='add'>+	AD7091R8_INFO_IRQ,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ad7091r2_channels[] = {</div><div class='add'>+	AD7091R_CHANNEL(0, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, NULL, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ad7091r4_channels[] = {</div><div class='add'>+	AD7091R_CHANNEL(0, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(2, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(3, 12, NULL, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ad7091r4_channels_irq[] = {</div><div class='add'>+	AD7091R_CHANNEL(0, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(2, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(3, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ad7091r8_channels[] = {</div><div class='add'>+	AD7091R_CHANNEL(0, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(2, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(3, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(4, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(5, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(6, 12, NULL, 0),</div><div class='add'>+	AD7091R_CHANNEL(7, 12, NULL, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ad7091r8_channels_irq[] = {</div><div class='add'>+	AD7091R_CHANNEL(0, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(1, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(2, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(3, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(4, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(5, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(6, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+	AD7091R_CHANNEL(7, 12, ad7091r_events, ARRAY_SIZE(ad7091r_events)),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void ad7091r_pulse_convst(struct ad7091r_state *st)</div><div class='add'>+{</div><div class='add'>+	gpiod_set_value_cansleep(st-&gt;convst_gpio, 1);</div><div class='add'>+	gpiod_set_value_cansleep(st-&gt;convst_gpio, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r_regmap_bus_reg_read(void *context, unsigned int reg,</div><div class='add'>+				       unsigned int *val)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = context;</div><div class='add'>+	struct spi_device *spi = container_of(st-&gt;dev, struct spi_device, dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	struct spi_transfer t[] = {</div><div class='add'>+		{</div><div class='add'>+			.tx_buf = &amp;st-&gt;tx_buf,</div><div class='add'>+			.len = 2,</div><div class='add'>+			.cs_change = 1,</div><div class='add'>+		}, {</div><div class='add'>+			.rx_buf = &amp;st-&gt;rx_buf,</div><div class='add'>+			.len = 2,</div><div class='add'>+		}</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (reg == AD7091R_REG_RESULT)</div><div class='add'>+		ad7091r_pulse_convst(st);</div><div class='add'>+</div><div class='add'>+	st-&gt;tx_buf = cpu_to_be16(reg &lt;&lt; 11);</div><div class='add'>+</div><div class='add'>+	ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*val = be16_to_cpu(st-&gt;rx_buf);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r_regmap_bus_reg_write(void *context, unsigned int reg,</div><div class='add'>+					unsigned int val)</div><div class='add'>+{</div><div class='add'>+	struct ad7091r_state *st = context;</div><div class='add'>+	struct spi_device *spi = container_of(st-&gt;dev, struct spi_device, dev);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * AD7091R-2/-4/-8 protocol (datasheet page 31) is to do a single SPI</div><div class='add'>+	 * transfer with reg address set in bits B15:B11 and value set in B9:B0.</div><div class='add'>+	 */</div><div class='add'>+	st-&gt;tx_buf = cpu_to_be16(FIELD_PREP(AD7091R8_REG_DATA_MSK, val) |</div><div class='add'>+				 FIELD_PREP(AD7091R8_RD_WR_FLAG_MSK, 1) |</div><div class='add'>+				 FIELD_PREP(AD7091R8_REG_ADDR_MSK, reg));</div><div class='add'>+</div><div class='add'>+	return spi_write(spi, &amp;st-&gt;tx_buf, 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct regmap_bus ad7091r8_regmap_bus = {</div><div class='add'>+	.reg_read = ad7091r_regmap_bus_reg_read,</div><div class='add'>+	.reg_write = ad7091r_regmap_bus_reg_write,</div><div class='add'>+	.reg_format_endian_default = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.val_format_endian_default = REGMAP_ENDIAN_BIG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ad7091r_chip_info ad7091r8_infos[] = {</div><div class='add'>+	[AD7091R2_INFO] = AD7091R_SPI_CHIP_INFO(2, "ad7091r-2"),</div><div class='add'>+	[AD7091R4_INFO] = AD7091R_SPI_CHIP_INFO(4, "ad7091r-4"),</div><div class='add'>+	[AD7091R4_INFO_IRQ] = AD7091R_SPI_CHIP_INFO_IRQ(4, "ad7091r-4"),</div><div class='add'>+	[AD7091R8_INFO] = AD7091R_SPI_CHIP_INFO(8, "ad7091r-8"),</div><div class='add'>+	[AD7091R8_INFO_IRQ] = AD7091R_SPI_CHIP_INFO_IRQ(8, "ad7091r-8")</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config ad7091r2_reg_conf = AD7091R_SPI_REGMAP_CONFIG(2);</div><div class='add'>+static const struct regmap_config ad7091r4_reg_conf = AD7091R_SPI_REGMAP_CONFIG(4);</div><div class='add'>+static const struct regmap_config ad7091r8_reg_conf = AD7091R_SPI_REGMAP_CONFIG(8);</div><div class='add'>+</div><div class='add'>+static void ad7091r8_regmap_init(struct ad7091r_state *st,</div><div class='add'>+				 const struct regmap_config *regmap_conf)</div><div class='add'>+{</div><div class='add'>+	st-&gt;map = devm_regmap_init(st-&gt;dev, &amp;ad7091r8_regmap_bus, st,</div><div class='add'>+				   regmap_conf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ad7091r8_gpio_setup(struct ad7091r_state *st)</div><div class='add'>+{</div><div class='add'>+	st-&gt;convst_gpio = devm_gpiod_get(st-&gt;dev, "convst", GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(st-&gt;convst_gpio))</div><div class='add'>+		return dev_err_probe(st-&gt;dev, PTR_ERR(st-&gt;convst_gpio),</div><div class='add'>+				     "Error getting convst GPIO\n");</div><div class='add'>+</div><div class='add'>+	st-&gt;reset_gpio = devm_gpiod_get_optional(st-&gt;dev, "reset",</div><div class='add'>+						 GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(st-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(st-&gt;dev, PTR_ERR(st-&gt;convst_gpio),</div><div class='add'>+				     "Error on requesting reset GPIO\n");</div><div class='add'>+</div><div class='add'>+	if (st-&gt;reset_gpio) {</div><div class='add'>+		fsleep(20);</div><div class='add'>+		gpiod_set_value_cansleep(st-&gt;reset_gpio, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct ad7091r_init_info ad7091r2_init_info = {</div><div class='add'>+	.info_no_irq = &amp;ad7091r8_infos[AD7091R2_INFO],</div><div class='add'>+	.regmap_config = &amp;ad7091r2_reg_conf,</div><div class='add'>+	.init_adc_regmap = &amp;ad7091r8_regmap_init,</div><div class='add'>+	.setup = &amp;ad7091r8_gpio_setup</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct ad7091r_init_info ad7091r4_init_info = {</div><div class='add'>+	.info_no_irq = &amp;ad7091r8_infos[AD7091R4_INFO],</div><div class='add'>+	.info_irq = &amp;ad7091r8_infos[AD7091R4_INFO_IRQ],</div><div class='add'>+	.regmap_config = &amp;ad7091r4_reg_conf,</div><div class='add'>+	.init_adc_regmap = &amp;ad7091r8_regmap_init,</div><div class='add'>+	.setup = &amp;ad7091r8_gpio_setup</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct ad7091r_init_info ad7091r8_init_info = {</div><div class='add'>+	.info_no_irq = &amp;ad7091r8_infos[AD7091R8_INFO],</div><div class='add'>+	.info_irq = &amp;ad7091r8_infos[AD7091R8_INFO_IRQ],</div><div class='add'>+	.regmap_config = &amp;ad7091r8_reg_conf,</div><div class='add'>+	.init_adc_regmap = &amp;ad7091r8_regmap_init,</div><div class='add'>+	.setup = &amp;ad7091r8_gpio_setup</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ad7091r8_spi_probe(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	const struct ad7091r_init_info *init_info;</div><div class='add'>+</div><div class='add'>+	init_info = spi_get_device_match_data(spi);</div><div class='add'>+	if (!init_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return ad7091r_probe(&amp;spi-&gt;dev, init_info, spi-&gt;irq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ad7091r8_of_match[] = {</div><div class='add'>+	{ .compatible = "adi,ad7091r2", .data = &amp;ad7091r2_init_info },</div><div class='add'>+	{ .compatible = "adi,ad7091r4", .data = &amp;ad7091r4_init_info },</div><div class='add'>+	{ .compatible = "adi,ad7091r8", .data = &amp;ad7091r8_init_info },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ad7091r8_of_match);</div><div class='add'>+</div><div class='add'>+static const struct spi_device_id ad7091r8_spi_id[] = {</div><div class='add'>+	{ "ad7091r2", (kernel_ulong_t)&amp;ad7091r2_init_info },</div><div class='add'>+	{ "ad7091r4", (kernel_ulong_t)&amp;ad7091r4_init_info },</div><div class='add'>+	{ "ad7091r8", (kernel_ulong_t)&amp;ad7091r8_init_info },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, ad7091r8_spi_id);</div><div class='add'>+</div><div class='add'>+static struct spi_driver ad7091r8_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "ad7091r8",</div><div class='add'>+		.of_match_table = ad7091r8_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = ad7091r8_spi_probe,</div><div class='add'>+	.id_table = ad7091r8_spi_id,</div><div class='add'>+};</div><div class='add'>+module_spi_driver(ad7091r8_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Marcelo Schmitt &lt;marcelo.schmitt@analog.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Analog Devices AD7091R8 ADC driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(IIO_AD7091R);</div><div class='head'>diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c<br/>index 39eccc28debe..6581fce4ba95 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad9467.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/ad9467.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ad9467.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ad9467.c</a></div><div class='hunk'>@@ -4,8 +4,9 @@</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright 2012-2020 Analog Devices Inc.</div><div class='ctx'>  */</div><div class='del'>-</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='hunk'>@@ -100,12 +101,6 @@</div><div class='ctx'> #define AD9467_DEF_OUTPUT_MODE		0x08</div><div class='ctx'> #define AD9467_REG_VREF_MASK		0x0F</div><div class='ctx'> </div><div class='del'>-enum {</div><div class='del'>-	ID_AD9265,</div><div class='del'>-	ID_AD9434,</div><div class='del'>-	ID_AD9467,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct ad9467_chip_info {</div><div class='ctx'> 	struct adi_axi_adc_chip_info	axi_adc_info;</div><div class='ctx'> 	unsigned int			default_output_mode;</div><div class='hunk'>@@ -119,9 +114,11 @@ struct ad9467_state {</div><div class='ctx'> 	struct spi_device		*spi;</div><div class='ctx'> 	struct clk			*clk;</div><div class='ctx'> 	unsigned int			output_mode;</div><div class='add'>+	unsigned int                    (*scales)[2];</div><div class='ctx'> </div><div class='ctx'> 	struct gpio_desc		*pwrdown_gpio;</div><div class='del'>-	struct gpio_desc		*reset_gpio;</div><div class='add'>+	/* ensure consistent state obtained on multiple related accesses */</div><div class='add'>+	struct mutex			lock;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)</div><div class='hunk'>@@ -161,11 +158,13 @@ static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,</div><div class='ctx'> 	struct spi_device *spi = st-&gt;spi;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (readval == NULL) {</div><div class='add'>+	if (!readval) {</div><div class='add'>+		guard(mutex)(&amp;st-&gt;lock);</div><div class='ctx'> 		ret = ad9467_spi_write(spi, reg, writeval);</div><div class='del'>-		ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,</div><div class='del'>-				 AN877_ADC_TRANSFER_SYNC);</div><div class='del'>-		return ret;</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,</div><div class='add'>+					AN877_ADC_TRANSFER_SYNC);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = ad9467_spi_read(spi, reg);</div><div class='hunk'>@@ -212,6 +211,7 @@ static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,</div><div class='ctx'> 	.channel = _chan,						\</div><div class='ctx'> 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |		\</div><div class='ctx'> 		BIT(IIO_CHAN_INFO_SAMP_FREQ),				\</div><div class='add'>+	.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \</div><div class='ctx'> 	.scan_index = _si,						\</div><div class='ctx'> 	.scan_type = {							\</div><div class='ctx'> 		.sign = _sign,						\</div><div class='hunk'>@@ -228,43 +228,46 @@ static const struct iio_chan_spec ad9467_channels[] = {</div><div class='ctx'> 	AD9467_CHAN(0, 0, 16, 'S'),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct ad9467_chip_info ad9467_chip_tbl[] = {</div><div class='del'>-	[ID_AD9265] = {</div><div class='del'>-		.axi_adc_info = {</div><div class='del'>-			.id = CHIPID_AD9265,</div><div class='del'>-			.max_rate = 125000000UL,</div><div class='del'>-			.scale_table = ad9265_scale_table,</div><div class='del'>-			.num_scales = ARRAY_SIZE(ad9265_scale_table),</div><div class='del'>-			.channels = ad9467_channels,</div><div class='del'>-			.num_channels = ARRAY_SIZE(ad9467_channels),</div><div class='del'>-		},</div><div class='del'>-		.default_output_mode = AD9265_DEF_OUTPUT_MODE,</div><div class='del'>-		.vref_mask = AD9265_REG_VREF_MASK,</div><div class='add'>+static const struct ad9467_chip_info ad9467_chip_tbl = {</div><div class='add'>+	.axi_adc_info = {</div><div class='add'>+		.name = "ad9467",</div><div class='add'>+		.id = CHIPID_AD9467,</div><div class='add'>+		.max_rate = 250000000UL,</div><div class='add'>+		.scale_table = ad9467_scale_table,</div><div class='add'>+		.num_scales = ARRAY_SIZE(ad9467_scale_table),</div><div class='add'>+		.channels = ad9467_channels,</div><div class='add'>+		.num_channels = ARRAY_SIZE(ad9467_channels),</div><div class='ctx'> 	},</div><div class='del'>-	[ID_AD9434] = {</div><div class='del'>-		.axi_adc_info = {</div><div class='del'>-			.id = CHIPID_AD9434,</div><div class='del'>-			.max_rate = 500000000UL,</div><div class='del'>-			.scale_table = ad9434_scale_table,</div><div class='del'>-			.num_scales = ARRAY_SIZE(ad9434_scale_table),</div><div class='del'>-			.channels = ad9434_channels,</div><div class='del'>-			.num_channels = ARRAY_SIZE(ad9434_channels),</div><div class='del'>-		},</div><div class='del'>-		.default_output_mode = AD9434_DEF_OUTPUT_MODE,</div><div class='del'>-		.vref_mask = AD9434_REG_VREF_MASK,</div><div class='add'>+	.default_output_mode = AD9467_DEF_OUTPUT_MODE,</div><div class='add'>+	.vref_mask = AD9467_REG_VREF_MASK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ad9467_chip_info ad9434_chip_tbl = {</div><div class='add'>+	.axi_adc_info = {</div><div class='add'>+		.name = "ad9434",</div><div class='add'>+		.id = CHIPID_AD9434,</div><div class='add'>+		.max_rate = 500000000UL,</div><div class='add'>+		.scale_table = ad9434_scale_table,</div><div class='add'>+		.num_scales = ARRAY_SIZE(ad9434_scale_table),</div><div class='add'>+		.channels = ad9434_channels,</div><div class='add'>+		.num_channels = ARRAY_SIZE(ad9434_channels),</div><div class='ctx'> 	},</div><div class='del'>-	[ID_AD9467] = {</div><div class='del'>-		.axi_adc_info = {</div><div class='del'>-			.id = CHIPID_AD9467,</div><div class='del'>-			.max_rate = 250000000UL,</div><div class='del'>-			.scale_table = ad9467_scale_table,</div><div class='del'>-			.num_scales = ARRAY_SIZE(ad9467_scale_table),</div><div class='del'>-			.channels = ad9467_channels,</div><div class='del'>-			.num_channels = ARRAY_SIZE(ad9467_channels),</div><div class='del'>-		},</div><div class='del'>-		.default_output_mode = AD9467_DEF_OUTPUT_MODE,</div><div class='del'>-		.vref_mask = AD9467_REG_VREF_MASK,</div><div class='add'>+	.default_output_mode = AD9434_DEF_OUTPUT_MODE,</div><div class='add'>+	.vref_mask = AD9434_REG_VREF_MASK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ad9467_chip_info ad9265_chip_tbl = {</div><div class='add'>+	.axi_adc_info = {</div><div class='add'>+		.name = "ad9265",</div><div class='add'>+		.id = CHIPID_AD9265,</div><div class='add'>+		.max_rate = 125000000UL,</div><div class='add'>+		.scale_table = ad9265_scale_table,</div><div class='add'>+		.num_scales = ARRAY_SIZE(ad9265_scale_table),</div><div class='add'>+		.channels = ad9467_channels,</div><div class='add'>+		.num_channels = ARRAY_SIZE(ad9467_channels),</div><div class='ctx'> 	},</div><div class='add'>+	.default_output_mode = AD9265_DEF_OUTPUT_MODE,</div><div class='add'>+	.vref_mask = AD9265_REG_VREF_MASK,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)</div><div class='hunk'>@@ -273,10 +276,13 @@ static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)</div><div class='ctx'> 	const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);</div><div class='ctx'> 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);</div><div class='ctx'> 	unsigned int i, vref_val;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	vref_val = ad9467_spi_read(st-&gt;spi, AN877_ADC_REG_VREF);</div><div class='add'>+	ret = ad9467_spi_read(st-&gt;spi, AN877_ADC_REG_VREF);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-	vref_val &amp;= info1-&gt;vref_mask;</div><div class='add'>+	vref_val = ret &amp; info1-&gt;vref_mask;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; info-&gt;num_scales; i++) {</div><div class='ctx'> 		if (vref_val == info-&gt;scale_table[i][1])</div><div class='hunk'>@@ -297,6 +303,7 @@ static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)</div><div class='ctx'> 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);</div><div class='ctx'> 	unsigned int scale_val[2];</div><div class='ctx'> 	unsigned int i;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (val != 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -306,11 +313,14 @@ static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)</div><div class='ctx'> 		if (scale_val[0] != val || scale_val[1] != val2)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		ad9467_spi_write(st-&gt;spi, AN877_ADC_REG_VREF,</div><div class='del'>-				 info-&gt;scale_table[i][1]);</div><div class='del'>-		ad9467_spi_write(st-&gt;spi, AN877_ADC_REG_TRANSFER,</div><div class='del'>-				 AN877_ADC_TRANSFER_SYNC);</div><div class='del'>-		return 0;</div><div class='add'>+		guard(mutex)(&amp;st-&gt;lock);</div><div class='add'>+		ret = ad9467_spi_write(st-&gt;spi, AN877_ADC_REG_VREF,</div><div class='add'>+				       info-&gt;scale_table[i][1]);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		return ad9467_spi_write(st-&gt;spi, AN877_ADC_REG_TRANSFER,</div><div class='add'>+					AN877_ADC_TRANSFER_SYNC);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return -EINVAL;</div><div class='hunk'>@@ -359,6 +369,26 @@ static int ad9467_write_raw(struct adi_axi_adc_conv *conv,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ad9467_read_avail(struct adi_axi_adc_conv *conv,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     const int **vals, int *type, int *length,</div><div class='add'>+			     long mask)</div><div class='add'>+{</div><div class='add'>+	const struct adi_axi_adc_chip_info *info = conv-&gt;chip_info;</div><div class='add'>+	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		*vals = (const int *)st-&gt;scales;</div><div class='add'>+		*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		/* Values are stored in a 2D matrix */</div><div class='add'>+		*length = info-&gt;num_scales * 2;</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -371,6 +401,26 @@ static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)</div><div class='ctx'> 				AN877_ADC_TRANSFER_SYNC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ad9467_scale_fill(struct adi_axi_adc_conv *conv)</div><div class='add'>+{</div><div class='add'>+	const struct adi_axi_adc_chip_info *info = conv-&gt;chip_info;</div><div class='add'>+	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);</div><div class='add'>+	unsigned int i, val1, val2;</div><div class='add'>+</div><div class='add'>+	st-&gt;scales = devm_kmalloc_array(&amp;st-&gt;spi-&gt;dev, info-&gt;num_scales,</div><div class='add'>+					sizeof(*st-&gt;scales), GFP_KERNEL);</div><div class='add'>+	if (!st-&gt;scales)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; info-&gt;num_scales; i++) {</div><div class='add'>+		__ad9467_get_scale(conv, i, &amp;val1, &amp;val2);</div><div class='add'>+		st-&gt;scales[i][0] = val1;</div><div class='add'>+		st-&gt;scales[i][1] = val2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)</div><div class='ctx'> {</div><div class='ctx'> 	struct ad9467_state *st = adi_axi_adc_conv_priv(conv);</div><div class='hunk'>@@ -378,6 +428,21 @@ static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)</div><div class='ctx'> 	return ad9467_outputmode_set(st-&gt;spi, st-&gt;output_mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ad9467_reset(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct gpio_desc *gpio;</div><div class='add'>+</div><div class='add'>+	gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR_OR_NULL(gpio))</div><div class='add'>+		return PTR_ERR_OR_ZERO(gpio);</div><div class='add'>+</div><div class='add'>+	fsleep(1);</div><div class='add'>+	gpiod_set_value_cansleep(gpio, 0);</div><div class='add'>+	fsleep(10 * USEC_PER_MSEC);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ad9467_probe(struct spi_device *spi)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ad9467_chip_info *info;</div><div class='hunk'>@@ -386,9 +451,7 @@ static int ad9467_probe(struct spi_device *spi)</div><div class='ctx'> 	unsigned int id;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	info = of_device_get_match_data(&amp;spi-&gt;dev);</div><div class='del'>-	if (!info)</div><div class='del'>-		info = (void *)spi_get_device_id(spi)-&gt;driver_data;</div><div class='add'>+	info = spi_get_device_match_data(spi);</div><div class='ctx'> 	if (!info)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='hunk'>@@ -408,21 +471,16 @@ static int ad9467_probe(struct spi_device *spi)</div><div class='ctx'> 	if (IS_ERR(st-&gt;pwrdown_gpio))</div><div class='ctx'> 		return PTR_ERR(st-&gt;pwrdown_gpio);</div><div class='ctx'> </div><div class='del'>-	st-&gt;reset_gpio = devm_gpiod_get_optional(&amp;spi-&gt;dev, "reset",</div><div class='del'>-						 GPIOD_OUT_LOW);</div><div class='del'>-	if (IS_ERR(st-&gt;reset_gpio))</div><div class='del'>-		return PTR_ERR(st-&gt;reset_gpio);</div><div class='del'>-</div><div class='del'>-	if (st-&gt;reset_gpio) {</div><div class='del'>-		udelay(1);</div><div class='del'>-		ret = gpiod_direction_output(st-&gt;reset_gpio, 1);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-		mdelay(10);</div><div class='del'>-	}</div><div class='add'>+	ret = ad9467_reset(&amp;spi-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	conv-&gt;chip_info = &amp;info-&gt;axi_adc_info;</div><div class='ctx'> </div><div class='add'>+	ret = ad9467_scale_fill(conv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);</div><div class='ctx'> 	if (id != conv-&gt;chip_info-&gt;id) {</div><div class='ctx'> 		dev_err(&amp;spi-&gt;dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",</div><div class='hunk'>@@ -433,6 +491,7 @@ static int ad9467_probe(struct spi_device *spi)</div><div class='ctx'> 	conv-&gt;reg_access = ad9467_reg_access;</div><div class='ctx'> 	conv-&gt;write_raw = ad9467_write_raw;</div><div class='ctx'> 	conv-&gt;read_raw = ad9467_read_raw;</div><div class='add'>+	conv-&gt;read_avail = ad9467_read_avail;</div><div class='ctx'> 	conv-&gt;preenable_setup = ad9467_preenable_setup;</div><div class='ctx'> </div><div class='ctx'> 	st-&gt;output_mode = info-&gt;default_output_mode |</div><div class='hunk'>@@ -442,17 +501,17 @@ static int ad9467_probe(struct spi_device *spi)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ad9467_of_match[] = {</div><div class='del'>-	{ .compatible = "adi,ad9265", .data = &amp;ad9467_chip_tbl[ID_AD9265], },</div><div class='del'>-	{ .compatible = "adi,ad9434", .data = &amp;ad9467_chip_tbl[ID_AD9434], },</div><div class='del'>-	{ .compatible = "adi,ad9467", .data = &amp;ad9467_chip_tbl[ID_AD9467], },</div><div class='add'>+	{ .compatible = "adi,ad9265", .data = &amp;ad9265_chip_tbl, },</div><div class='add'>+	{ .compatible = "adi,ad9434", .data = &amp;ad9434_chip_tbl, },</div><div class='add'>+	{ .compatible = "adi,ad9467", .data = &amp;ad9467_chip_tbl, },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, ad9467_of_match);</div><div class='ctx'> </div><div class='ctx'> static const struct spi_device_id ad9467_ids[] = {</div><div class='del'>-	{ "ad9265", (kernel_ulong_t)&amp;ad9467_chip_tbl[ID_AD9265] },</div><div class='del'>-	{ "ad9434", (kernel_ulong_t)&amp;ad9467_chip_tbl[ID_AD9434] },</div><div class='del'>-	{ "ad9467", (kernel_ulong_t)&amp;ad9467_chip_tbl[ID_AD9467] },</div><div class='add'>+	{ "ad9265", (kernel_ulong_t)&amp;ad9265_chip_tbl },</div><div class='add'>+	{ "ad9434", (kernel_ulong_t)&amp;ad9434_chip_tbl },</div><div class='add'>+	{ "ad9467", (kernel_ulong_t)&amp;ad9467_chip_tbl },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(spi, ad9467_ids);</div><div class='head'>diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c<br/>index aff0532a974a..c247ff1541d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/adi-axi-adc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/adi-axi-adc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/adi-axi-adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/adi-axi-adc.c</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/iio/iio.h&gt;</div><div class='hunk'>@@ -62,7 +63,7 @@ struct adi_axi_adc_state {</div><div class='ctx'> 	struct mutex				lock;</div><div class='ctx'> </div><div class='ctx'> 	struct adi_axi_adc_client		*client;</div><div class='del'>-	void __iomem				*regs;</div><div class='add'>+	struct regmap				*regmap;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct adi_axi_adc_client {</div><div class='hunk'>@@ -90,19 +91,6 @@ void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);</div><div class='ctx'> </div><div class='del'>-static void adi_axi_adc_write(struct adi_axi_adc_state *st,</div><div class='del'>-			      unsigned int reg,</div><div class='del'>-			      unsigned int val)</div><div class='del'>-{</div><div class='del'>-	iowrite32(val, st-&gt;regs + reg);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,</div><div class='del'>-				     unsigned int reg)</div><div class='del'>-{</div><div class='del'>-	return ioread32(st-&gt;regs + reg);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int adi_axi_adc_config_dma_buffer(struct device *dev,</div><div class='ctx'> 					 struct iio_dev *indio_dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -144,22 +132,39 @@ static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 	return conv-&gt;write_raw(conv, chan, val, val2, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,</div><div class='add'>+				  struct iio_chan_spec const *chan,</div><div class='add'>+				  const int **vals, int *type, int *length,</div><div class='add'>+				  long mask)</div><div class='add'>+{</div><div class='add'>+	struct adi_axi_adc_state *st = iio_priv(indio_dev);</div><div class='add'>+	struct adi_axi_adc_conv *conv = &amp;st-&gt;client-&gt;conv;</div><div class='add'>+</div><div class='add'>+	if (!conv-&gt;read_avail)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return conv-&gt;read_avail(conv, chan, vals, type, length, mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,</div><div class='ctx'> 					const unsigned long *scan_mask)</div><div class='ctx'> {</div><div class='ctx'> 	struct adi_axi_adc_state *st = iio_priv(indio_dev);</div><div class='ctx'> 	struct adi_axi_adc_conv *conv = &amp;st-&gt;client-&gt;conv;</div><div class='del'>-	unsigned int i, ctrl;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; conv-&gt;chip_info-&gt;num_channels; i++) {</div><div class='del'>-		ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));</div><div class='del'>-</div><div class='ctx'> 		if (test_bit(i, scan_mask))</div><div class='del'>-			ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;</div><div class='add'>+			ret = regmap_set_bits(st-&gt;regmap,</div><div class='add'>+					      ADI_AXI_REG_CHAN_CTRL(i),</div><div class='add'>+					      ADI_AXI_REG_CHAN_CTRL_ENABLE);</div><div class='ctx'> 		else</div><div class='del'>-			ctrl &amp;= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;</div><div class='del'>-</div><div class='del'>-		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);</div><div class='add'>+			ret = regmap_clear_bits(st-&gt;regmap,</div><div class='add'>+						ADI_AXI_REG_CHAN_CTRL(i),</div><div class='add'>+						ADI_AXI_REG_CHAN_CTRL_ENABLE);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -228,69 +233,11 @@ struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);</div><div class='ctx'> </div><div class='del'>-static ssize_t in_voltage_scale_available_show(struct device *dev,</div><div class='del'>-					       struct device_attribute *attr,</div><div class='del'>-					       char *buf)</div><div class='del'>-{</div><div class='del'>-	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='del'>-	struct adi_axi_adc_state *st = iio_priv(indio_dev);</div><div class='del'>-	struct adi_axi_adc_conv *conv = &amp;st-&gt;client-&gt;conv;</div><div class='del'>-	size_t len = 0;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; conv-&gt;chip_info-&gt;num_scales; i++) {</div><div class='del'>-		const unsigned int *s = conv-&gt;chip_info-&gt;scale_table[i];</div><div class='del'>-</div><div class='del'>-		len += scnprintf(buf + len, PAGE_SIZE - len,</div><div class='del'>-				 "%u.%06u ", s[0], s[1]);</div><div class='del'>-	}</div><div class='del'>-	buf[len - 1] = '\n';</div><div class='del'>-</div><div class='del'>-	return len;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);</div><div class='del'>-</div><div class='del'>-enum {</div><div class='del'>-	ADI_AXI_ATTR_SCALE_AVAIL,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define ADI_AXI_ATTR(_en_, _file_)			\</div><div class='del'>-	[ADI_AXI_ATTR_##_en_] = &amp;iio_dev_attr_##_file_.dev_attr.attr</div><div class='del'>-</div><div class='del'>-static struct attribute *adi_axi_adc_attributes[] = {</div><div class='del'>-	ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),</div><div class='del'>-	NULL</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static umode_t axi_adc_attr_is_visible(struct kobject *kobj,</div><div class='del'>-				       struct attribute *attr, int n)</div><div class='del'>-{</div><div class='del'>-	struct device *dev = kobj_to_dev(kobj);</div><div class='del'>-	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='del'>-	struct adi_axi_adc_state *st = iio_priv(indio_dev);</div><div class='del'>-	struct adi_axi_adc_conv *conv = &amp;st-&gt;client-&gt;conv;</div><div class='del'>-</div><div class='del'>-	switch (n) {</div><div class='del'>-	case ADI_AXI_ATTR_SCALE_AVAIL:</div><div class='del'>-		if (!conv-&gt;chip_info-&gt;num_scales)</div><div class='del'>-			return 0;</div><div class='del'>-		return attr-&gt;mode;</div><div class='del'>-	default:</div><div class='del'>-		return attr-&gt;mode;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct attribute_group adi_axi_adc_attribute_group = {</div><div class='del'>-	.attrs = adi_axi_adc_attributes,</div><div class='del'>-	.is_visible = axi_adc_attr_is_visible,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct iio_info adi_axi_adc_info = {</div><div class='ctx'> 	.read_raw = &amp;adi_axi_adc_read_raw,</div><div class='ctx'> 	.write_raw = &amp;adi_axi_adc_write_raw,</div><div class='del'>-	.attrs = &amp;adi_axi_adc_attribute_group,</div><div class='ctx'> 	.update_scan_mode = &amp;adi_axi_adc_update_scan_mode,</div><div class='add'>+	.read_avail = &amp;adi_axi_adc_read_avail,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {</div><div class='hunk'>@@ -354,21 +301,32 @@ static int adi_axi_adc_setup_channels(struct device *dev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; conv-&gt;chip_info-&gt;num_channels; i++) {</div><div class='del'>-		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),</div><div class='del'>-				  ADI_AXI_REG_CHAN_CTRL_DEFAULTS);</div><div class='add'>+		ret = regmap_write(st-&gt;regmap, ADI_AXI_REG_CHAN_CTRL(i),</div><div class='add'>+				   ADI_AXI_REG_CHAN_CTRL_DEFAULTS);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void axi_adc_reset(struct adi_axi_adc_state *st)</div><div class='add'>+static int axi_adc_reset(struct adi_axi_adc_state *st)</div><div class='ctx'> {</div><div class='del'>-	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(st-&gt;regmap, ADI_AXI_REG_RSTN, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	mdelay(10);</div><div class='del'>-	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);</div><div class='add'>+	ret = regmap_write(st-&gt;regmap, ADI_AXI_REG_RSTN,</div><div class='add'>+			   ADI_AXI_REG_RSTN_MMCM_RSTN);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	mdelay(10);</div><div class='del'>-	adi_axi_adc_write(st, ADI_AXI_REG_RSTN,</div><div class='del'>-			  ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);</div><div class='add'>+	return regmap_write(st-&gt;regmap, ADI_AXI_REG_RSTN,</div><div class='add'>+			    ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void adi_axi_adc_cleanup(void *data)</div><div class='hunk'>@@ -379,12 +337,20 @@ static void adi_axi_adc_cleanup(void *data)</div><div class='ctx'> 	module_put(cl-&gt;dev-&gt;driver-&gt;owner);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct regmap_config axi_adc_regmap_config = {</div><div class='add'>+	.val_bits = 32,</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.reg_stride = 4,</div><div class='add'>+	.max_register = 0x0800,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int adi_axi_adc_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct adi_axi_adc_conv *conv;</div><div class='ctx'> 	struct iio_dev *indio_dev;</div><div class='ctx'> 	struct adi_axi_adc_client *cl;</div><div class='ctx'> 	struct adi_axi_adc_state *st;</div><div class='add'>+	void __iomem *base;</div><div class='ctx'> 	unsigned int ver;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -405,15 +371,24 @@ static int adi_axi_adc_probe(struct platform_device *pdev)</div><div class='ctx'> 	cl-&gt;state = st;</div><div class='ctx'> 	mutex_init(&amp;st-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	st-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='del'>-	if (IS_ERR(st-&gt;regs))</div><div class='del'>-		return PTR_ERR(st-&gt;regs);</div><div class='add'>+	base = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(base))</div><div class='add'>+		return PTR_ERR(base);</div><div class='add'>+</div><div class='add'>+	st-&gt;regmap = devm_regmap_init_mmio(&amp;pdev-&gt;dev, base,</div><div class='add'>+					   &amp;axi_adc_regmap_config);</div><div class='add'>+	if (IS_ERR(st-&gt;regmap))</div><div class='add'>+		return PTR_ERR(st-&gt;regmap);</div><div class='ctx'> </div><div class='ctx'> 	conv = &amp;st-&gt;client-&gt;conv;</div><div class='ctx'> </div><div class='del'>-	axi_adc_reset(st);</div><div class='add'>+	ret = axi_adc_reset(st);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-	ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);</div><div class='add'>+	ret = regmap_read(st-&gt;regmap, ADI_AXI_REG_VERSION, &amp;ver);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (cl-&gt;info-&gt;version &gt; ver) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev,</div><div class='head'>diff --git a/drivers/iio/adc/imx93_adc.c b/drivers/iio/adc/imx93_adc.c<br/>index 9bb1e4ba1aee..4ccf4819f1f1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/imx93_adc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/imx93_adc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/imx93_adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/imx93_adc.c</a></div><div class='hunk'>@@ -93,6 +93,10 @@ static const struct iio_chan_spec imx93_adc_iio_channels[] = {</div><div class='ctx'> 	IMX93_ADC_CHAN(1),</div><div class='ctx'> 	IMX93_ADC_CHAN(2),</div><div class='ctx'> 	IMX93_ADC_CHAN(3),</div><div class='add'>+	IMX93_ADC_CHAN(4),</div><div class='add'>+	IMX93_ADC_CHAN(5),</div><div class='add'>+	IMX93_ADC_CHAN(6),</div><div class='add'>+	IMX93_ADC_CHAN(7),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void imx93_adc_power_down(struct imx93_adc *adc)</div><div class='head'>diff --git a/drivers/iio/adc/max34408.c b/drivers/iio/adc/max34408.c<br/>new file mode 100644<br/>index 000000000000..6c2ea2bc52c6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/max34408.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/max34408.c</a></div><div class='hunk'>@@ -0,0 +1,276 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * IIO driver for Maxim MAX34409/34408 ADC, 4-Channels/2-Channels, 8bits, I2C</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX34408-MAX34409.pdf</div><div class='add'>+ *</div><div class='add'>+ * TODO: ALERT interrupt, Overcurrent delay, Shutdown delay</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+#include &lt;linux/iio/types.h&gt;</div><div class='add'>+</div><div class='add'>+#define MAX34408_STATUS_REG		0x0</div><div class='add'>+#define MAX34408_CONTROL_REG		0x1</div><div class='add'>+#define MAX34408_OCDELAY_REG		0x2</div><div class='add'>+#define MAX34408_SDDELAY_REG		0x3</div><div class='add'>+</div><div class='add'>+#define MAX34408_ADC1_REG		0x4</div><div class='add'>+#define MAX34408_ADC2_REG		0x5</div><div class='add'>+/* ADC3 &amp; ADC4 always returns 0x0 on 34408 */</div><div class='add'>+#define MAX34409_ADC3_REG		0x6</div><div class='add'>+#define MAX34409_ADC4_REG		0x7</div><div class='add'>+</div><div class='add'>+#define MAX34408_OCT1_REG		0x8</div><div class='add'>+#define MAX34408_OCT2_REG		0x9</div><div class='add'>+#define MAX34409_OCT3_REG		0xA</div><div class='add'>+#define MAX34409_OCT4_REG		0xB</div><div class='add'>+</div><div class='add'>+#define MAX34408_DID_REG		0xC</div><div class='add'>+#define MAX34408_DCYY_REG		0xD</div><div class='add'>+#define MAX34408_DCWW_REG		0xE</div><div class='add'>+</div><div class='add'>+/* Bit masks for status register */</div><div class='add'>+#define MAX34408_STATUS_OC_MSK		GENMASK(1, 0)</div><div class='add'>+#define MAX34409_STATUS_OC_MSK		GENMASK(3, 0)</div><div class='add'>+#define MAX34408_STATUS_SHTDN		BIT(4)</div><div class='add'>+#define MAX34408_STATUS_ENA		BIT(5)</div><div class='add'>+</div><div class='add'>+/* Bit masks for control register */</div><div class='add'>+#define MAX34408_CONTROL_AVG0		BIT(0)</div><div class='add'>+#define MAX34408_CONTROL_AVG1		BIT(1)</div><div class='add'>+#define MAX34408_CONTROL_AVG2		BIT(2)</div><div class='add'>+#define MAX34408_CONTROL_ALERT		BIT(3)</div><div class='add'>+</div><div class='add'>+#define MAX34408_DEFAULT_AVG		0x4</div><div class='add'>+</div><div class='add'>+/* Bit masks for over current delay */</div><div class='add'>+#define MAX34408_OCDELAY_OCD_MSK	GENMASK(6, 0)</div><div class='add'>+#define MAX34408_OCDELAY_RESET		BIT(7)</div><div class='add'>+</div><div class='add'>+/* Bit masks for shutdown delay */</div><div class='add'>+#define MAX34408_SDDELAY_SHD_MSK	GENMASK(6, 0)</div><div class='add'>+#define MAX34408_SDDELAY_RESET		BIT(7)</div><div class='add'>+</div><div class='add'>+#define MAX34408_DEFAULT_RSENSE		1000</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct max34408_data - max34408/max34409 specific data.</div><div class='add'>+ * @regmap:	device register map.</div><div class='add'>+ * @dev:	max34408 device.</div><div class='add'>+ * @lock:	lock for protecting access to device hardware registers, mostly</div><div class='add'>+ *		for read modify write cycles for control registers.</div><div class='add'>+ * @input_rsense:	Rsense values in uOhm, will be overwritten by</div><div class='add'>+ *			values from channel nodes.</div><div class='add'>+ */</div><div class='add'>+struct max34408_data {</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	u32 input_rsense[4];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config max34408_regmap_config = {</div><div class='add'>+	.reg_bits	= 8,</div><div class='add'>+	.val_bits	= 8,</div><div class='add'>+	.max_register	= MAX34408_DCWW_REG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct max34408_adc_model_data {</div><div class='add'>+	const char *model_name;</div><div class='add'>+	const struct iio_chan_spec *channels;</div><div class='add'>+	const int num_channels;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MAX34008_CHANNEL(_index, _address)			\</div><div class='add'>+	{							\</div><div class='add'>+		.type = IIO_CURRENT,				\</div><div class='add'>+		.info_mask_separate	= BIT(IIO_CHAN_INFO_RAW) | \</div><div class='add'>+					  BIT(IIO_CHAN_INFO_SCALE) | \</div><div class='add'>+					  BIT(IIO_CHAN_INFO_OFFSET), \</div><div class='add'>+		.channel = (_index),				\</div><div class='add'>+		.address = (_address),				\</div><div class='add'>+		.indexed = 1,					\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec max34408_channels[] = {</div><div class='add'>+	MAX34008_CHANNEL(0, MAX34408_ADC1_REG),</div><div class='add'>+	MAX34008_CHANNEL(1, MAX34408_ADC2_REG),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec max34409_channels[] = {</div><div class='add'>+	MAX34008_CHANNEL(0, MAX34408_ADC1_REG),</div><div class='add'>+	MAX34008_CHANNEL(1, MAX34408_ADC2_REG),</div><div class='add'>+	MAX34008_CHANNEL(2, MAX34409_ADC3_REG),</div><div class='add'>+	MAX34008_CHANNEL(3, MAX34409_ADC4_REG),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int max34408_read_adc_avg(struct max34408_data *max34408,</div><div class='add'>+				 const struct iio_chan_spec *chan, int *val)</div><div class='add'>+{</div><div class='add'>+	unsigned int ctrl;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;max34408-&gt;lock);</div><div class='add'>+	rc = regmap_read(max34408-&gt;regmap, MAX34408_CONTROL_REG, (u32 *)&amp;ctrl);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	/* set averaging (0b100) default values*/</div><div class='add'>+	rc = regmap_write(max34408-&gt;regmap, MAX34408_CONTROL_REG,</div><div class='add'>+			  MAX34408_DEFAULT_AVG);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_err(max34408-&gt;dev,</div><div class='add'>+			"Error (%d) writing control register\n", rc);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = regmap_read(max34408-&gt;regmap, chan-&gt;address, val);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	/* back to old values */</div><div class='add'>+	rc = regmap_write(max34408-&gt;regmap, MAX34408_CONTROL_REG, ctrl);</div><div class='add'>+	if (rc)</div><div class='add'>+		dev_err(max34408-&gt;dev,</div><div class='add'>+			"Error (%d) writing control register\n", rc);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int max34408_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     int *val, int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct max34408_data *max34408 = iio_priv(indio_dev);</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		rc = max34408_read_adc_avg(max34408, chan, val);</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		/*</div><div class='add'>+		 * calcluate current for 8bit ADC with Rsense</div><div class='add'>+		 * value.</div><div class='add'>+		 * 10 mV * 1000 / Rsense uOhm = max current</div><div class='add'>+		 * (max current * adc val * 1000) / (2^8 - 1) mA</div><div class='add'>+		 */</div><div class='add'>+		*val = 10000 / max34408-&gt;input_rsense[chan-&gt;channel];</div><div class='add'>+		*val2 = 8;</div><div class='add'>+		return IIO_VAL_FRACTIONAL_LOG2;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info max34408_info = {</div><div class='add'>+	.read_raw	= max34408_read_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct max34408_adc_model_data max34408_model_data = {</div><div class='add'>+	.model_name = "max34408",</div><div class='add'>+	.channels = max34408_channels,</div><div class='add'>+	.num_channels = 2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct max34408_adc_model_data max34409_model_data = {</div><div class='add'>+	.model_name = "max34409",</div><div class='add'>+	.channels = max34409_channels,</div><div class='add'>+	.num_channels = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int max34408_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	const struct max34408_adc_model_data *model_data;</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct max34408_data *max34408;</div><div class='add'>+	struct fwnode_handle *node;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int rc, i = 0;</div><div class='add'>+</div><div class='add'>+	model_data = i2c_get_match_data(client);</div><div class='add'>+	if (!model_data)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	regmap = devm_regmap_init_i2c(client, &amp;max34408_regmap_config);</div><div class='add'>+	if (IS_ERR(regmap)) {</div><div class='add'>+		dev_err_probe(dev, PTR_ERR(regmap),</div><div class='add'>+			      "regmap_init failed\n");</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(dev, sizeof(*max34408));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	max34408 = iio_priv(indio_dev);</div><div class='add'>+	max34408-&gt;regmap = regmap;</div><div class='add'>+	max34408-&gt;dev = dev;</div><div class='add'>+	mutex_init(&amp;max34408-&gt;lock);</div><div class='add'>+</div><div class='add'>+	device_for_each_child_node(dev, node) {</div><div class='add'>+		fwnode_property_read_u32(node, "maxim,rsense-val-micro-ohms",</div><div class='add'>+					 &amp;max34408-&gt;input_rsense[i]);</div><div class='add'>+		i++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* disable ALERT and averaging */</div><div class='add'>+	rc = regmap_write(max34408-&gt;regmap, MAX34408_CONTROL_REG, 0x0);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;channels = model_data-&gt;channels;</div><div class='add'>+	indio_dev-&gt;num_channels = model_data-&gt;num_channels;</div><div class='add'>+	indio_dev-&gt;name = model_data-&gt;model_name;</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;info = &amp;max34408_info;</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id max34408_of_match[] = {</div><div class='add'>+	{</div><div class='add'>+		.compatible = "maxim,max34408",</div><div class='add'>+		.data = &amp;max34408_model_data,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "maxim,max34409",</div><div class='add'>+		.data = &amp;max34409_model_data,</div><div class='add'>+	},</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, max34408_of_match);</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id max34408_id[] = {</div><div class='add'>+	{ "max34408", (kernel_ulong_t)&amp;max34408_model_data },</div><div class='add'>+	{ "max34409", (kernel_ulong_t)&amp;max34409_model_data },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, max34408_id);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver max34408_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name   = "max34408",</div><div class='add'>+		.of_match_table = max34408_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = max34408_probe,</div><div class='add'>+	.id_table = max34408_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(max34408_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Ivan Mikhaylov &lt;fr0st61te@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Maxim MAX34408/34409 ADC driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/adc/mcp3564.c b/drivers/iio/adc/mcp3564.c<br/>index e3f1de5fcc5a..311b613b6057 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/mcp3564.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/mcp3564.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/mcp3564.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/mcp3564.c</a></div><div class='hunk'>@@ -918,7 +918,7 @@ static int mcp3564_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 		mutex_unlock(&amp;adc-&gt;lock);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	case IIO_CHAN_INFO_CALIBBIAS:</div><div class='del'>-		if (val &lt; mcp3564_calib_bias[0] &amp;&amp; val &gt; mcp3564_calib_bias[2])</div><div class='add'>+		if (val &lt; mcp3564_calib_bias[0] || val &gt; mcp3564_calib_bias[2])</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;adc-&gt;lock);</div><div class='hunk'>@@ -928,7 +928,7 @@ static int mcp3564_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 		mutex_unlock(&amp;adc-&gt;lock);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	case IIO_CHAN_INFO_CALIBSCALE:</div><div class='del'>-		if (val &lt; mcp3564_calib_scale[0] &amp;&amp; val &gt; mcp3564_calib_scale[2])</div><div class='add'>+		if (val &lt; mcp3564_calib_scale[0] || val &gt; mcp3564_calib_scale[2])</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		if (adc-&gt;calib_scale == val)</div><div class='hunk'>@@ -1122,7 +1122,7 @@ static int mcp3564_config(struct iio_dev *indio_dev)</div><div class='ctx'> 	enum mcp3564_ids ids;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	unsigned int tmp = 0x01;</div><div class='del'>-	bool err = true;</div><div class='add'>+	bool err = false;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The address is set on a per-device basis by fuses in the factory,</div><div class='hunk'>@@ -1509,5 +1509,5 @@ static struct spi_driver mcp3564_driver = {</div><div class='ctx'> module_spi_driver(mcp3564_driver);</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Marius Cristea &lt;marius.cristea@microchip.com&gt;");</div><div class='del'>-MODULE_DESCRIPTION("Microchip MCP346x/MCP346xR and MCP356x/MCP346xR ADCs");</div><div class='add'>+MODULE_DESCRIPTION("Microchip MCP346x/MCP346xR and MCP356x/MCP356xR ADCs");</div><div class='ctx'> MODULE_LICENSE("GPL v2");</div><div class='head'>diff --git a/drivers/iio/adc/mcp3911.c b/drivers/iio/adc/mcp3911.c<br/>index d864558bc087..7a32e7a1be9d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/mcp3911.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/mcp3911.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/mcp3911.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/mcp3911.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='hunk'>@@ -316,47 +317,37 @@ static int mcp3911_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 			    int *val2, long mask)</div><div class='ctx'> {</div><div class='ctx'> 	struct mcp3911 *adc = iio_priv(indio_dev);</div><div class='del'>-	int ret = -EINVAL;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adc-&gt;lock);</div><div class='add'>+	guard(mutex)(&amp;adc-&gt;lock);</div><div class='ctx'> 	switch (mask) {</div><div class='ctx'> 	case IIO_CHAN_INFO_RAW:</div><div class='ctx'> 		ret = mcp3911_read(adc,</div><div class='ctx'> 				   MCP3911_CHANNEL(channel-&gt;channel), val, 3);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			goto out;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='ctx'> 		*val = sign_extend32(*val, 23);</div><div class='del'>-</div><div class='del'>-		ret = IIO_VAL_INT;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='add'>+		return IIO_VAL_INT;</div><div class='ctx'> 	case IIO_CHAN_INFO_OFFSET:</div><div class='del'>-</div><div class='ctx'> 		ret = adc-&gt;chip-&gt;get_offset(adc, channel-&gt;channel, val);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			goto out;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='del'>-		ret = IIO_VAL_INT;</div><div class='del'>-		break;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='ctx'> 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:</div><div class='ctx'> 		ret = adc-&gt;chip-&gt;get_osr(adc, val);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			goto out;</div><div class='del'>-</div><div class='del'>-		ret = IIO_VAL_INT;</div><div class='del'>-		break;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='add'>+		return IIO_VAL_INT;</div><div class='ctx'> 	case IIO_CHAN_INFO_SCALE:</div><div class='ctx'> 		*val = mcp3911_scale_table[ilog2(adc-&gt;gain[channel-&gt;channel])][0];</div><div class='ctx'> 		*val2 = mcp3911_scale_table[ilog2(adc-&gt;gain[channel-&gt;channel])][1];</div><div class='del'>-		ret = IIO_VAL_INT_PLUS_NANO;</div><div class='del'>-		break;</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;adc-&gt;lock);</div><div class='del'>-	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mcp3911_write_raw(struct iio_dev *indio_dev,</div><div class='hunk'>@@ -364,9 +355,8 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 			     int val2, long mask)</div><div class='ctx'> {</div><div class='ctx'> 	struct mcp3911 *adc = iio_priv(indio_dev);</div><div class='del'>-	int ret = -EINVAL;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adc-&gt;lock);</div><div class='add'>+	guard(mutex)(&amp;adc-&gt;lock);</div><div class='ctx'> 	switch (mask) {</div><div class='ctx'> 	case IIO_CHAN_INFO_SCALE:</div><div class='ctx'> 		for (int i = 0; i &lt; MCP3911_NUM_SCALES; i++) {</div><div class='hunk'>@@ -374,32 +364,25 @@ static int mcp3911_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 			    val2 == mcp3911_scale_table[i][1]) {</div><div class='ctx'> </div><div class='ctx'> 				adc-&gt;gain[channel-&gt;channel] = BIT(i);</div><div class='del'>-				ret = adc-&gt;chip-&gt;set_scale(adc, channel-&gt;channel, i);</div><div class='add'>+				return adc-&gt;chip-&gt;set_scale(adc, channel-&gt;channel, i);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		break;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	case IIO_CHAN_INFO_OFFSET:</div><div class='del'>-		if (val2 != 0) {</div><div class='del'>-			ret = -EINVAL;</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		ret = adc-&gt;chip-&gt;set_offset(adc, channel-&gt;channel, val);</div><div class='del'>-		break;</div><div class='add'>+		if (val2 != 0)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> </div><div class='add'>+		return adc-&gt;chip-&gt;set_offset(adc, channel-&gt;channel, val);</div><div class='ctx'> 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:</div><div class='ctx'> 		for (int i = 0; i &lt; ARRAY_SIZE(mcp3911_osr_table); i++) {</div><div class='ctx'> 			if (val == mcp3911_osr_table[i]) {</div><div class='del'>-				ret = adc-&gt;chip-&gt;set_osr(adc, i);</div><div class='del'>-				break;</div><div class='add'>+				return adc-&gt;chip-&gt;set_osr(adc, i);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		break;</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;adc-&gt;lock);</div><div class='del'>-	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mcp3911_calc_scale_table(struct mcp3911 *adc)</div><div class='hunk'>@@ -532,7 +515,7 @@ static irqreturn_t mcp3911_trigger_handler(int irq, void *p)</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;adc-&gt;lock);</div><div class='add'>+	guard(mutex)(&amp;adc-&gt;lock);</div><div class='ctx'> 	adc-&gt;tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc-&gt;dev_addr);</div><div class='ctx'> 	ret = spi_sync_transfer(adc-&gt;spi, xfer, ARRAY_SIZE(xfer));</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='hunk'>@@ -549,7 +532,6 @@ static irqreturn_t mcp3911_trigger_handler(int irq, void *p)</div><div class='ctx'> 	iio_push_to_buffers_with_timestamp(indio_dev, &amp;adc-&gt;scan,</div><div class='ctx'> 					   iio_get_time_ns(indio_dev));</div><div class='ctx'> out:</div><div class='del'>-	mutex_unlock(&amp;adc-&gt;lock);</div><div class='ctx'> 	iio_trigger_notify_done(indio_dev-&gt;trig);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='head'>diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c<br/>index 950ff13e6dde..13b473d8c6c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/meson_saradc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/meson_saradc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/meson_saradc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/meson_saradc.c</a></div><div class='hunk'>@@ -1241,6 +1241,20 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {</div><div class='ctx'> 	.cmv_select = 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct meson_sar_adc_param meson_sar_adc_axg_param = {</div><div class='add'>+	.has_bl30_integration = true,</div><div class='add'>+	.clock_rate = 1200000,</div><div class='add'>+	.bandgap_reg = MESON_SAR_ADC_REG11,</div><div class='add'>+	.regmap_config = &amp;meson_sar_adc_regmap_config_gxbb,</div><div class='add'>+	.resolution = 12,</div><div class='add'>+	.disable_ring_counter = 1,</div><div class='add'>+	.has_reg11 = true,</div><div class='add'>+	.vref_volatge = 1,</div><div class='add'>+	.has_vref_select = true,</div><div class='add'>+	.vref_select = VREF_VDDA,</div><div class='add'>+	.cmv_select = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {</div><div class='ctx'> 	.has_bl30_integration = false,</div><div class='ctx'> 	.clock_rate = 1200000,</div><div class='hunk'>@@ -1285,7 +1299,7 @@ static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct meson_sar_adc_data meson_sar_adc_axg_data = {</div><div class='del'>-	.param = &amp;meson_sar_adc_gxl_param,</div><div class='add'>+	.param = &amp;meson_sar_adc_axg_param,</div><div class='ctx'> 	.name = "meson-axg-saradc",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c<br/>index c755e8cd5220..95fa857e8aad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/adc/ti_am335x_adc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/adc/ti_am335x_adc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/adc/ti_am335x_adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/adc/ti_am335x_adc.c</a></div><div class='hunk'>@@ -670,8 +670,10 @@ static int tiadc_probe(struct platform_device *pdev)</div><div class='ctx'> 	platform_set_drvdata(pdev, indio_dev);</div><div class='ctx'> </div><div class='ctx'> 	err = tiadc_request_dma(pdev, adc_dev);</div><div class='del'>-	if (err &amp;&amp; err == -EPROBE_DEFER)</div><div class='add'>+	if (err &amp;&amp; err != -ENODEV) {</div><div class='add'>+		dev_err_probe(&amp;pdev-&gt;dev, err, "DMA request failed\n");</div><div class='ctx'> 		goto err_dma;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/amplifiers/hmc425a.c b/drivers/iio/amplifiers/hmc425a.c<br/>index e87d35d50a95..ed4d72922696 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/amplifiers/hmc425a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/amplifiers/hmc425a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/amplifiers/hmc425a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/amplifiers/hmc425a.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'>  * Copyright 2020 Analog Devices Inc.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitops.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/gpio/consumer.h&gt;</div><div class='hunk'>@@ -22,6 +23,7 @@</div><div class='ctx'> enum hmc425a_type {</div><div class='ctx'> 	ID_HMC425A,</div><div class='ctx'> 	ID_HMC540S,</div><div class='add'>+	ID_ADRF5740</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct hmc425a_chip_info {</div><div class='hunk'>@@ -74,6 +76,10 @@ static int hmc425a_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 		case ID_HMC540S:</div><div class='ctx'> 			gain = ~code * -1000;</div><div class='ctx'> 			break;</div><div class='add'>+		case ID_ADRF5740:</div><div class='add'>+			code = code &amp; BIT(3) ? code &amp; ~BIT(2) : code;</div><div class='add'>+			gain = code * -2000;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		*val = gain / 1000;</div><div class='hunk'>@@ -113,6 +119,10 @@ static int hmc425a_write_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 	case ID_HMC540S:</div><div class='ctx'> 		code = ~((abs(gain) / 1000) &amp; 0xF);</div><div class='ctx'> 		break;</div><div class='add'>+	case ID_ADRF5740:</div><div class='add'>+		code = (abs(gain) / 2000) &amp; 0xF;</div><div class='add'>+		code = code &amp; BIT(3) ? code | BIT(2) : code;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;st-&gt;lock);</div><div class='hunk'>@@ -165,6 +175,7 @@ static const struct iio_chan_spec hmc425a_channels[] = {</div><div class='ctx'> static const struct of_device_id hmc425a_of_match[] = {</div><div class='ctx'> 	{ .compatible = "adi,hmc425a", .data = (void *)ID_HMC425A },</div><div class='ctx'> 	{ .compatible = "adi,hmc540s", .data = (void *)ID_HMC540S },</div><div class='add'>+	{ .compatible = "adi,adrf5740", .data = (void *)ID_ADRF5740 },</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, hmc425a_of_match);</div><div class='hunk'>@@ -188,6 +199,15 @@ static struct hmc425a_chip_info hmc425a_chip_info_tbl[] = {</div><div class='ctx'> 		.gain_max = 0,</div><div class='ctx'> 		.default_gain = -0x10, /* set default gain -15.0db*/</div><div class='ctx'> 	},</div><div class='add'>+	[ID_ADRF5740] = {</div><div class='add'>+		.name = "adrf5740",</div><div class='add'>+		.channels = hmc425a_channels,</div><div class='add'>+		.num_channels = ARRAY_SIZE(hmc425a_channels),</div><div class='add'>+		.num_gpios = 4,</div><div class='add'>+		.gain_min = -22000,</div><div class='add'>+		.gain_max = 0,</div><div class='add'>+		.default_gain = 0xF, /* set default gain -22.0db*/</div><div class='add'>+	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int hmc425a_probe(struct platform_device *pdev)</div><div class='hunk'>@@ -229,6 +249,9 @@ static int hmc425a_probe(struct platform_device *pdev)</div><div class='ctx'> 	indio_dev-&gt;info = &amp;hmc425a_info;</div><div class='ctx'> 	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='ctx'> </div><div class='add'>+	/* Set default gain */</div><div class='add'>+	hmc425a_write(indio_dev, st-&gt;gain);</div><div class='add'>+</div><div class='ctx'> 	return devm_iio_device_register(&amp;pdev-&gt;dev, indio_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/buffer/industrialio-buffer-dma.c b/drivers/iio/buffer/industrialio-buffer-dma.c<br/>index d348af8b9705..5610ba67925e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/buffer/industrialio-buffer-dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/buffer/industrialio-buffer-dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/buffer/industrialio-buffer-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/buffer/industrialio-buffer-dma.c</a></div><div class='hunk'>@@ -179,7 +179,7 @@ static struct iio_dma_buffer_block *iio_dma_buffer_alloc_block(</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	block-&gt;size = size;</div><div class='del'>-	block-&gt;state = IIO_BLOCK_STATE_DEQUEUED;</div><div class='add'>+	block-&gt;state = IIO_BLOCK_STATE_DONE;</div><div class='ctx'> 	block-&gt;queue = queue;</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;block-&gt;head);</div><div class='ctx'> 	kref_init(&amp;block-&gt;kref);</div><div class='hunk'>@@ -191,16 +191,8 @@ static struct iio_dma_buffer_block *iio_dma_buffer_alloc_block(</div><div class='ctx'> </div><div class='ctx'> static void _iio_dma_buffer_block_done(struct iio_dma_buffer_block *block)</div><div class='ctx'> {</div><div class='del'>-	struct iio_dma_buffer_queue *queue = block-&gt;queue;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * The buffer has already been freed by the application, just drop the</div><div class='del'>-	 * reference.</div><div class='del'>-	 */</div><div class='del'>-	if (block-&gt;state != IIO_BLOCK_STATE_DEAD) {</div><div class='add'>+	if (block-&gt;state != IIO_BLOCK_STATE_DEAD)</div><div class='ctx'> 		block-&gt;state = IIO_BLOCK_STATE_DONE;</div><div class='del'>-		list_add_tail(&amp;block-&gt;head, &amp;queue-&gt;outgoing);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -261,7 +253,6 @@ static bool iio_dma_block_reusable(struct iio_dma_buffer_block *block)</div><div class='ctx'> 	 * not support abort and has not given back the block yet.</div><div class='ctx'> 	 */</div><div class='ctx'> 	switch (block-&gt;state) {</div><div class='del'>-	case IIO_BLOCK_STATE_DEQUEUED:</div><div class='ctx'> 	case IIO_BLOCK_STATE_QUEUED:</div><div class='ctx'> 	case IIO_BLOCK_STATE_DONE:</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -317,7 +308,6 @@ int iio_dma_buffer_request_update(struct iio_buffer *buffer)</div><div class='ctx'> 	 * dead. This means we can reset the lists without having to fear</div><div class='ctx'> 	 * corrution.</div><div class='ctx'> 	 */</div><div class='del'>-	INIT_LIST_HEAD(&amp;queue-&gt;outgoing);</div><div class='ctx'> 	spin_unlock_irq(&amp;queue-&gt;list_lock);</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;queue-&gt;incoming);</div><div class='hunk'>@@ -356,6 +346,29 @@ out_unlock:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iio_dma_buffer_request_update);</div><div class='ctx'> </div><div class='add'>+static void iio_dma_buffer_fileio_free(struct iio_dma_buffer_queue *queue)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;queue-&gt;list_lock);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(queue-&gt;fileio.blocks); i++) {</div><div class='add'>+		if (!queue-&gt;fileio.blocks[i])</div><div class='add'>+			continue;</div><div class='add'>+		queue-&gt;fileio.blocks[i]-&gt;state = IIO_BLOCK_STATE_DEAD;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irq(&amp;queue-&gt;list_lock);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;queue-&gt;incoming);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(queue-&gt;fileio.blocks); i++) {</div><div class='add'>+		if (!queue-&gt;fileio.blocks[i])</div><div class='add'>+			continue;</div><div class='add'>+		iio_buffer_block_put(queue-&gt;fileio.blocks[i]);</div><div class='add'>+		queue-&gt;fileio.blocks[i] = NULL;</div><div class='add'>+	}</div><div class='add'>+	queue-&gt;fileio.active_block = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void iio_dma_buffer_submit_block(struct iio_dma_buffer_queue *queue,</div><div class='ctx'> 	struct iio_dma_buffer_block *block)</div><div class='ctx'> {</div><div class='hunk'>@@ -456,14 +469,20 @@ static struct iio_dma_buffer_block *iio_dma_buffer_dequeue(</div><div class='ctx'> 	struct iio_dma_buffer_queue *queue)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dma_buffer_block *block;</div><div class='add'>+	unsigned int idx;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;queue-&gt;list_lock);</div><div class='del'>-	block = list_first_entry_or_null(&amp;queue-&gt;outgoing, struct</div><div class='del'>-		iio_dma_buffer_block, head);</div><div class='del'>-	if (block != NULL) {</div><div class='del'>-		list_del(&amp;block-&gt;head);</div><div class='del'>-		block-&gt;state = IIO_BLOCK_STATE_DEQUEUED;</div><div class='add'>+</div><div class='add'>+	idx = queue-&gt;fileio.next_dequeue;</div><div class='add'>+	block = queue-&gt;fileio.blocks[idx];</div><div class='add'>+</div><div class='add'>+	if (block-&gt;state == IIO_BLOCK_STATE_DONE) {</div><div class='add'>+		idx = (idx + 1) % ARRAY_SIZE(queue-&gt;fileio.blocks);</div><div class='add'>+		queue-&gt;fileio.next_dequeue = idx;</div><div class='add'>+	} else {</div><div class='add'>+		block = NULL;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	spin_unlock_irq(&amp;queue-&gt;list_lock);</div><div class='ctx'> </div><div class='ctx'> 	return block;</div><div class='hunk'>@@ -539,6 +558,7 @@ size_t iio_dma_buffer_data_available(struct iio_buffer *buf)</div><div class='ctx'> 	struct iio_dma_buffer_queue *queue = iio_buffer_to_queue(buf);</div><div class='ctx'> 	struct iio_dma_buffer_block *block;</div><div class='ctx'> 	size_t data_available = 0;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * For counting the available bytes we'll use the size of the block not</div><div class='hunk'>@@ -552,8 +572,15 @@ size_t iio_dma_buffer_data_available(struct iio_buffer *buf)</div><div class='ctx'> 		data_available += queue-&gt;fileio.active_block-&gt;size;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;queue-&gt;list_lock);</div><div class='del'>-	list_for_each_entry(block, &amp;queue-&gt;outgoing, head)</div><div class='del'>-		data_available += block-&gt;size;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(queue-&gt;fileio.blocks); i++) {</div><div class='add'>+		block = queue-&gt;fileio.blocks[i];</div><div class='add'>+</div><div class='add'>+		if (block != queue-&gt;fileio.active_block</div><div class='add'>+		    &amp;&amp; block-&gt;state == IIO_BLOCK_STATE_DONE)</div><div class='add'>+			data_available += block-&gt;size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	spin_unlock_irq(&amp;queue-&gt;list_lock);</div><div class='ctx'> 	mutex_unlock(&amp;queue-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -617,7 +644,6 @@ int iio_dma_buffer_init(struct iio_dma_buffer_queue *queue,</div><div class='ctx'> 	queue-&gt;ops = ops;</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;queue-&gt;incoming);</div><div class='del'>-	INIT_LIST_HEAD(&amp;queue-&gt;outgoing);</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;queue-&gt;lock);</div><div class='ctx'> 	spin_lock_init(&amp;queue-&gt;list_lock);</div><div class='hunk'>@@ -635,28 +661,9 @@ EXPORT_SYMBOL_GPL(iio_dma_buffer_init);</div><div class='ctx'>  */</div><div class='ctx'> void iio_dma_buffer_exit(struct iio_dma_buffer_queue *queue)</div><div class='ctx'> {</div><div class='del'>-	unsigned int i;</div><div class='del'>-</div><div class='ctx'> 	mutex_lock(&amp;queue-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;queue-&gt;list_lock);</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(queue-&gt;fileio.blocks); i++) {</div><div class='del'>-		if (!queue-&gt;fileio.blocks[i])</div><div class='del'>-			continue;</div><div class='del'>-		queue-&gt;fileio.blocks[i]-&gt;state = IIO_BLOCK_STATE_DEAD;</div><div class='del'>-	}</div><div class='del'>-	INIT_LIST_HEAD(&amp;queue-&gt;outgoing);</div><div class='del'>-	spin_unlock_irq(&amp;queue-&gt;list_lock);</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;queue-&gt;incoming);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(queue-&gt;fileio.blocks); i++) {</div><div class='del'>-		if (!queue-&gt;fileio.blocks[i])</div><div class='del'>-			continue;</div><div class='del'>-		iio_buffer_block_put(queue-&gt;fileio.blocks[i]);</div><div class='del'>-		queue-&gt;fileio.blocks[i] = NULL;</div><div class='del'>-	}</div><div class='del'>-	queue-&gt;fileio.active_block = NULL;</div><div class='add'>+	iio_dma_buffer_fileio_free(queue);</div><div class='ctx'> 	queue-&gt;ops = NULL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;queue-&gt;lock);</div><div class='head'>diff --git a/drivers/iio/buffer/industrialio-triggered-buffer.c b/drivers/iio/buffer/industrialio-triggered-buffer.c<br/>index c7671b1f5ead..c06515987e7a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/buffer/industrialio-triggered-buffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/buffer/industrialio-triggered-buffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/buffer/industrialio-triggered-buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/buffer/industrialio-triggered-buffer.c</a></div><div class='hunk'>@@ -46,6 +46,16 @@ int iio_triggered_buffer_setup_ext(struct iio_dev *indio_dev,</div><div class='ctx'> 	struct iio_buffer *buffer;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * iio_triggered_buffer_cleanup() assumes that the buffer allocated here</div><div class='add'>+	 * is assigned to indio_dev-&gt;buffer but this is only the case if this</div><div class='add'>+	 * function is the first caller to iio_device_attach_buffer(). If</div><div class='add'>+	 * indio_dev-&gt;buffer is already set then we can't proceed otherwise the</div><div class='add'>+	 * cleanup function will try to free a buffer that was not allocated here.</div><div class='add'>+	 */</div><div class='add'>+	if (indio_dev-&gt;buffer)</div><div class='add'>+		return -EADDRINUSE;</div><div class='add'>+</div><div class='ctx'> 	buffer = iio_kfifo_allocate();</div><div class='ctx'> 	if (!buffer) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='head'>diff --git a/drivers/iio/chemical/Kconfig b/drivers/iio/chemical/Kconfig<br/>index c30657e10ee1..02649ab81b3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/chemical/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/chemical/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/Kconfig</a></div><div class='hunk'>@@ -5,6 +5,17 @@</div><div class='ctx'> </div><div class='ctx'> menu "Chemical Sensors"</div><div class='ctx'> </div><div class='add'>+config AOSONG_AGS02MA</div><div class='add'>+	tristate "Aosong AGS02MA TVOC sensor driver"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select CRC8</div><div class='add'>+	help</div><div class='add'>+	  Say Y here to build support for Aosong AGS02MA TVOC (Total Volatile</div><div class='add'>+	  Organic Compounds) sensor.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as module, choose M here: the module will be</div><div class='add'>+	  called ags02ma.</div><div class='add'>+</div><div class='ctx'> config ATLAS_PH_SENSOR</div><div class='ctx'> 	tristate "Atlas Scientific OEM SM sensors"</div><div class='ctx'> 	depends on I2C</div><div class='head'>diff --git a/drivers/iio/chemical/Makefile b/drivers/iio/chemical/Makefile<br/>index a11e777a7a00..2f3dee8bb779 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/chemical/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/chemical/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/Makefile</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'> #</div><div class='ctx'> </div><div class='ctx'> # When adding new entries keep the list in alphabetical order</div><div class='add'>+obj-$(CONFIG_AOSONG_AGS02MA)	+= ags02ma.o</div><div class='ctx'> obj-$(CONFIG_ATLAS_PH_SENSOR)	+= atlas-sensor.o</div><div class='ctx'> obj-$(CONFIG_ATLAS_EZO_SENSOR)	+= atlas-ezo-sensor.o</div><div class='ctx'> obj-$(CONFIG_BME680) += bme680_core.o</div><div class='head'>diff --git a/drivers/iio/chemical/ags02ma.c b/drivers/iio/chemical/ags02ma.c<br/>new file mode 100644<br/>index 000000000000..8fcd80946543<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/ags02ma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/ags02ma.c</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Anshul Dalal &lt;anshulusr@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Driver for Aosong AGS02MA</div><div class='add'>+ *</div><div class='add'>+ * Datasheet:</div><div class='add'>+ *   https://asairsensors.com/wp-content/uploads/2021/09/AGS02MA.pdf</div><div class='add'>+ * Product Page:</div><div class='add'>+ *   http://www.aosong.com/m/en/products-33.html</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/crc8.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#define AGS02MA_TVOC_READ_REG		   0x00</div><div class='add'>+#define AGS02MA_VERSION_REG		   0x11</div><div class='add'>+</div><div class='add'>+#define AGS02MA_VERSION_PROCESSING_DELAY   30</div><div class='add'>+#define AGS02MA_TVOC_READ_PROCESSING_DELAY 1500</div><div class='add'>+</div><div class='add'>+#define AGS02MA_CRC8_INIT		   0xff</div><div class='add'>+#define AGS02MA_CRC8_POLYNOMIAL		   0x31</div><div class='add'>+</div><div class='add'>+DECLARE_CRC8_TABLE(ags02ma_crc8_table);</div><div class='add'>+</div><div class='add'>+struct ags02ma_data {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ags02ma_reading {</div><div class='add'>+	__be32 data;</div><div class='add'>+	u8 crc;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+static int ags02ma_register_read(struct i2c_client *client, u8 reg, u16 delay,</div><div class='add'>+				 u32 *val)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u8 crc;</div><div class='add'>+	struct ags02ma_reading read_buffer;</div><div class='add'>+</div><div class='add'>+	ret = i2c_master_send(client, &amp;reg, sizeof(reg));</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev,</div><div class='add'>+			"Failed to send data to register 0x%x: %d", reg, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Processing Delay, Check Table 7.7 in the datasheet */</div><div class='add'>+	msleep_interruptible(delay);</div><div class='add'>+</div><div class='add'>+	ret = i2c_master_recv(client, (u8 *)&amp;read_buffer, sizeof(read_buffer));</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev,</div><div class='add'>+			"Failed to receive from register 0x%x: %d", reg, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	crc = crc8(ags02ma_crc8_table, (u8 *)&amp;read_buffer.data,</div><div class='add'>+		   sizeof(read_buffer.data), AGS02MA_CRC8_INIT);</div><div class='add'>+	if (crc != read_buffer.crc) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "CRC error\n");</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = be32_to_cpu(read_buffer.data);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ags02ma_read_raw(struct iio_dev *iio_device,</div><div class='add'>+			    struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			    int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct ags02ma_data *data = iio_priv(iio_device);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		ret = ags02ma_register_read(data-&gt;client, AGS02MA_TVOC_READ_REG,</div><div class='add'>+					    AGS02MA_TVOC_READ_PROCESSING_DELAY,</div><div class='add'>+					    val);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		/* The sensor reads data as ppb */</div><div class='add'>+		*val = 0;</div><div class='add'>+		*val2 = 100;</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info ags02ma_info = {</div><div class='add'>+	.read_raw = ags02ma_read_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ags02ma_channel = {</div><div class='add'>+	.type = IIO_CONCENTRATION,</div><div class='add'>+	.channel2 = IIO_MOD_VOC,</div><div class='add'>+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+		BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ags02ma_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct ags02ma_data *data;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	u32 version;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	crc8_populate_msb(ags02ma_crc8_table, AGS02MA_CRC8_POLYNOMIAL);</div><div class='add'>+</div><div class='add'>+	ret = ags02ma_register_read(client, AGS02MA_VERSION_REG,</div><div class='add'>+				    AGS02MA_VERSION_PROCESSING_DELAY, &amp;version);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+			      "Failed to read device version\n");</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "Aosong AGS02MA, Version: 0x%x", version);</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+	data-&gt;client = client;</div><div class='add'>+	indio_dev-&gt;info = &amp;ags02ma_info;</div><div class='add'>+	indio_dev-&gt;channels = &amp;ags02ma_channel;</div><div class='add'>+	indio_dev-&gt;num_channels = 1;</div><div class='add'>+	indio_dev-&gt;name = "ags02ma";</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(&amp;client-&gt;dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id ags02ma_id_table[] = {</div><div class='add'>+	{ "ags02ma" },</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, ags02ma_id_table);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ags02ma_of_table[] = {</div><div class='add'>+	{ .compatible = "aosong,ags02ma" },</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ags02ma_of_table);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver ags02ma_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "ags02ma",</div><div class='add'>+		.of_match_table = ags02ma_of_table,</div><div class='add'>+	},</div><div class='add'>+	.id_table = ags02ma_id_table,</div><div class='add'>+	.probe = ags02ma_probe,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(ags02ma_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Anshul Dalal &lt;anshulusr@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Aosong AGS02MA TVOC Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/chemical/pms7003.c b/drivers/iio/chemical/pms7003.c<br/>index e9857d93b307..b5cf15a515d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/chemical/pms7003.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/chemical/pms7003.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/pms7003.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/pms7003.c</a></div><div class='hunk'>@@ -211,13 +211,13 @@ static bool pms7003_frame_is_okay(struct pms7003_frame *frame)</div><div class='ctx'> 	return checksum == pms7003_calc_checksum(frame);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pms7003_receive_buf(struct serdev_device *serdev,</div><div class='del'>-			       const unsigned char *buf, size_t size)</div><div class='add'>+static ssize_t pms7003_receive_buf(struct serdev_device *serdev, const u8 *buf,</div><div class='add'>+				   size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dev *indio_dev = serdev_device_get_drvdata(serdev);</div><div class='ctx'> 	struct pms7003_state *state = iio_priv(indio_dev);</div><div class='ctx'> 	struct pms7003_frame *frame = &amp;state-&gt;frame;</div><div class='del'>-	int num;</div><div class='add'>+	size_t num;</div><div class='ctx'> </div><div class='ctx'> 	if (!frame-&gt;expected_length) {</div><div class='ctx'> 		u16 magic;</div><div class='head'>diff --git a/drivers/iio/chemical/scd30_serial.c b/drivers/iio/chemical/scd30_serial.c<br/>index 3c519103d30b..a47654591e55 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/chemical/scd30_serial.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/chemical/scd30_serial.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/scd30_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/scd30_serial.c</a></div><div class='hunk'>@@ -174,13 +174,13 @@ static int scd30_serdev_command(struct scd30_state *state, enum scd30_cmd cmd, u</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int scd30_serdev_receive_buf(struct serdev_device *serdev,</div><div class='del'>-				    const unsigned char *buf, size_t size)</div><div class='add'>+static ssize_t scd30_serdev_receive_buf(struct serdev_device *serdev,</div><div class='add'>+					const u8 *buf, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dev *indio_dev = serdev_device_get_drvdata(serdev);</div><div class='ctx'> 	struct scd30_serdev_priv *priv;</div><div class='ctx'> 	struct scd30_state *state;</div><div class='del'>-	int num;</div><div class='add'>+	size_t num;</div><div class='ctx'> </div><div class='ctx'> 	if (!indio_dev)</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/iio/chemical/sps30_serial.c b/drivers/iio/chemical/sps30_serial.c<br/>index 164f4b3e025c..3afa89f8acc3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/chemical/sps30_serial.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/chemical/sps30_serial.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/chemical/sps30_serial.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/chemical/sps30_serial.c</a></div><div class='hunk'>@@ -74,8 +74,8 @@ static int sps30_serial_xfer(struct sps30_state *state, const unsigned char *buf</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct {</div><div class='del'>-	unsigned char byte;</div><div class='del'>-	unsigned char byte2;</div><div class='add'>+	u8 byte;</div><div class='add'>+	u8 byte2;</div><div class='ctx'> } sps30_serial_bytes[] = {</div><div class='ctx'> 	{ 0x11, 0x31 },</div><div class='ctx'> 	{ 0x13, 0x33 },</div><div class='hunk'>@@ -83,7 +83,7 @@ static const struct {</div><div class='ctx'> 	{ 0x7d, 0x5d },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int sps30_serial_put_byte(unsigned char *buf, unsigned char byte)</div><div class='add'>+static int sps30_serial_put_byte(u8 *buf, u8 byte)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -102,7 +102,7 @@ static int sps30_serial_put_byte(unsigned char *buf, unsigned char byte)</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static char sps30_serial_get_byte(bool escaped, unsigned char byte2)</div><div class='add'>+static u8 sps30_serial_get_byte(bool escaped, u8 byte2)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -130,8 +130,8 @@ static unsigned char sps30_serial_calc_chksum(const unsigned char *buf, size_t n</div><div class='ctx'> 	return ~chksum;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sps30_serial_prep_frame(unsigned char *buf, unsigned char cmd,</div><div class='del'>-				   const unsigned char *arg, size_t arg_size)</div><div class='add'>+static int sps30_serial_prep_frame(u8 *buf, u8 cmd, const u8 *arg,</div><div class='add'>+				   size_t arg_size)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned char chksum;</div><div class='ctx'> 	int num = 0;</div><div class='hunk'>@@ -210,14 +210,14 @@ static int sps30_serial_command(struct sps30_state *state, unsigned char cmd,</div><div class='ctx'> 	return rsp_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sps30_serial_receive_buf(struct serdev_device *serdev,</div><div class='del'>-				    const unsigned char *buf, size_t size)</div><div class='add'>+static ssize_t sps30_serial_receive_buf(struct serdev_device *serdev,</div><div class='add'>+					const u8 *buf, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dev *indio_dev = dev_get_drvdata(&amp;serdev-&gt;dev);</div><div class='ctx'> 	struct sps30_serial_priv *priv;</div><div class='ctx'> 	struct sps30_state *state;</div><div class='del'>-	unsigned char byte;</div><div class='ctx'> 	size_t i;</div><div class='add'>+	u8 byte;</div><div class='ctx'> </div><div class='ctx'> 	if (!indio_dev)</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/iio/common/ms_sensors/ms_sensors_i2c.c b/drivers/iio/common/ms_sensors/ms_sensors_i2c.c<br/>index 6633b35a94e6..9c9bc77003c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/common/ms_sensors/ms_sensors_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/common/ms_sensors/ms_sensors_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/common/ms_sensors/ms_sensors_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/common/ms_sensors/ms_sensors_i2c.c</a></div><div class='hunk'>@@ -15,8 +15,8 @@</div><div class='ctx'> /* Conversion times in us */</div><div class='ctx'> static const u16 ms_sensors_ht_t_conversion_time[] = { 50000, 25000,</div><div class='ctx'> 						       13000, 7000 };</div><div class='del'>-static const u16 ms_sensors_ht_h_conversion_time[] = { 16000, 3000,</div><div class='del'>-						       5000, 8000 };</div><div class='add'>+static const u16 ms_sensors_ht_h_conversion_time[] = { 16000, 5000,</div><div class='add'>+						       3000, 8000 };</div><div class='ctx'> static const u16 ms_sensors_tp_conversion_time[] = { 500, 1100, 2100,</div><div class='ctx'> 						     4100, 8220, 16440 };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig<br/>index 93b8be183de6..34eb40bb9529 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/dac/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/dac/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/dac/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/Kconfig</a></div><div class='hunk'>@@ -400,6 +400,16 @@ config MCP4728</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module</div><div class='ctx'> 	  will be called mcp4728.</div><div class='ctx'> </div><div class='add'>+config MCP4821</div><div class='add'>+	tristate "MCP4801/02/11/12/21/22 DAC driver"</div><div class='add'>+	depends on SPI</div><div class='add'>+	help</div><div class='add'>+	  Say yes here to build the driver for the Microchip MCP4801</div><div class='add'>+	  MCP4802, MCP4811, MCP4812, MCP4821 and MCP4822 DAC devices.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module</div><div class='add'>+	  will be called mcp4821.</div><div class='add'>+</div><div class='ctx'> config MCP4922</div><div class='ctx'> 	tristate "MCP4902, MCP4912, MCP4922 DAC driver"</div><div class='ctx'> 	depends on SPI</div><div class='head'>diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile<br/>index 5b2bac900d5a..55bf89739d14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/dac/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/dac/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/dac/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/Makefile</a></div><div class='hunk'>@@ -42,6 +42,7 @@ obj-$(CONFIG_MAX5522) += max5522.o</div><div class='ctx'> obj-$(CONFIG_MAX5821) += max5821.o</div><div class='ctx'> obj-$(CONFIG_MCP4725) += mcp4725.o</div><div class='ctx'> obj-$(CONFIG_MCP4728) += mcp4728.o</div><div class='add'>+obj-$(CONFIG_MCP4821) += mcp4821.o</div><div class='ctx'> obj-$(CONFIG_MCP4922) += mcp4922.o</div><div class='ctx'> obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o</div><div class='ctx'> obj-$(CONFIG_STM32_DAC) += stm32-dac.o</div><div class='head'>diff --git a/drivers/iio/dac/ad5791.c b/drivers/iio/dac/ad5791.c<br/>index a4167454da81..75b549827e15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/dac/ad5791.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/dac/ad5791.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/dac/ad5791.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/ad5791.c</a></div><div class='hunk'>@@ -345,6 +345,7 @@ static int ad5791_probe(struct spi_device *spi)</div><div class='ctx'> 	struct iio_dev *indio_dev;</div><div class='ctx'> 	struct ad5791_state *st;</div><div class='ctx'> 	int ret, pos_voltage_uv = 0, neg_voltage_uv = 0;</div><div class='add'>+	bool use_rbuf_gain2;</div><div class='ctx'> </div><div class='ctx'> 	indio_dev = devm_iio_device_alloc(&amp;spi-&gt;dev, sizeof(*st));</div><div class='ctx'> 	if (!indio_dev)</div><div class='hunk'>@@ -379,6 +380,12 @@ static int ad5791_probe(struct spi_device *spi)</div><div class='ctx'> 	st-&gt;pwr_down = true;</div><div class='ctx'> 	st-&gt;spi = spi;</div><div class='ctx'> </div><div class='add'>+	if (pdata)</div><div class='add'>+		use_rbuf_gain2 = pdata-&gt;use_rbuf_gain2;</div><div class='add'>+	else</div><div class='add'>+		use_rbuf_gain2 = device_property_read_bool(&amp;spi-&gt;dev,</div><div class='add'>+							   "adi,rbuf-gain2-en");</div><div class='add'>+</div><div class='ctx'> 	if (!IS_ERR(st-&gt;reg_vss) &amp;&amp; !IS_ERR(st-&gt;reg_vdd)) {</div><div class='ctx'> 		st-&gt;vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000;</div><div class='ctx'> 		st-&gt;vref_neg_mv = neg_voltage_uv / 1000;</div><div class='hunk'>@@ -398,7 +405,7 @@ static int ad5791_probe(struct spi_device *spi)</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	st-&gt;ctrl = AD5761_CTRL_LINCOMP(st-&gt;chip_info-&gt;get_lin_comp(st-&gt;vref_mv))</div><div class='del'>-		  | ((pdata &amp;&amp; pdata-&gt;use_rbuf_gain2) ? 0 : AD5791_CTRL_RBUF) |</div><div class='add'>+		  | (use_rbuf_gain2 ? 0 : AD5791_CTRL_RBUF) |</div><div class='ctx'> 		  AD5791_CTRL_BIN2SC;</div><div class='ctx'> </div><div class='ctx'> 	ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st-&gt;ctrl |</div><div class='head'>diff --git a/drivers/iio/dac/mcp4821.c b/drivers/iio/dac/mcp4821.c<br/>new file mode 100644<br/>index 000000000000..8a0480d33845<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/dac/mcp4821.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/dac/mcp4821.c</a></div><div class='hunk'>@@ -0,0 +1,236 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Anshul Dalal &lt;anshulusr@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Driver for Microchip MCP4801, MCP4802, MCP4811, MCP4812, MCP4821 and MCP4822</div><div class='add'>+ *</div><div class='add'>+ * Based on the work of:</div><div class='add'>+ *	Michael Welling (MCP4922 Driver)</div><div class='add'>+ *</div><div class='add'>+ * Datasheet:</div><div class='add'>+ *	MCP48x1: https://ww1.microchip.com/downloads/en/DeviceDoc/22244B.pdf</div><div class='add'>+ *	MCP48x2: https://ww1.microchip.com/downloads/en/DeviceDoc/20002249B.pdf</div><div class='add'>+ *</div><div class='add'>+ * TODO:</div><div class='add'>+ *	- Configurable gain</div><div class='add'>+ *	- Regulator control</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/spi/spi.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+#include &lt;linux/iio/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#define MCP4821_ACTIVE_MODE BIT(12)</div><div class='add'>+#define MCP4802_SECOND_CHAN BIT(15)</div><div class='add'>+</div><div class='add'>+/* DAC uses an internal Voltage reference of 4.096V at a gain of 2x */</div><div class='add'>+#define MCP4821_2X_GAIN_VREF_MV 4096</div><div class='add'>+</div><div class='add'>+enum mcp4821_supported_drvice_ids {</div><div class='add'>+	ID_MCP4801,</div><div class='add'>+	ID_MCP4802,</div><div class='add'>+	ID_MCP4811,</div><div class='add'>+	ID_MCP4812,</div><div class='add'>+	ID_MCP4821,</div><div class='add'>+	ID_MCP4822,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcp4821_state {</div><div class='add'>+	struct spi_device *spi;</div><div class='add'>+	u16 dac_value[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcp4821_chip_info {</div><div class='add'>+	const char *name;</div><div class='add'>+	int num_channels;</div><div class='add'>+	const struct iio_chan_spec channels[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MCP4821_CHAN(channel_id, resolution)                          \</div><div class='add'>+	{                                                             \</div><div class='add'>+		.type = IIO_VOLTAGE, .output = 1, .indexed = 1,       \</div><div class='add'>+		.channel = (channel_id),                              \</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),         \</div><div class='add'>+		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \</div><div class='add'>+		.scan_type = {                                        \</div><div class='add'>+			.realbits = (resolution),                     \</div><div class='add'>+			.shift = 12 - (resolution),                   \</div><div class='add'>+		},                                                    \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct mcp4821_chip_info mcp4821_chip_info_table[6] = {</div><div class='add'>+	[ID_MCP4801] = {</div><div class='add'>+			.name = "mcp4801",</div><div class='add'>+			.num_channels = 1,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 8),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+	[ID_MCP4802] = {</div><div class='add'>+			.name = "mcp4802",</div><div class='add'>+			.num_channels = 2,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 8),</div><div class='add'>+				MCP4821_CHAN(1, 8),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+	[ID_MCP4811] = {</div><div class='add'>+			.name = "mcp4811",</div><div class='add'>+			.num_channels = 1,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 10),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+	[ID_MCP4812] = {</div><div class='add'>+			.name = "mcp4812",</div><div class='add'>+			.num_channels = 2,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 10),</div><div class='add'>+				MCP4821_CHAN(1, 10),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+	[ID_MCP4821] = {</div><div class='add'>+			.name = "mcp4821",</div><div class='add'>+			.num_channels = 1,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 12),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+	[ID_MCP4822] = {</div><div class='add'>+			.name = "mcp4822",</div><div class='add'>+			.num_channels = 2,</div><div class='add'>+			.channels = {</div><div class='add'>+				MCP4821_CHAN(0, 12),</div><div class='add'>+				MCP4821_CHAN(1, 12),</div><div class='add'>+			},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mcp4821_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			    struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			    int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct mcp4821_state *state;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		state = iio_priv(indio_dev);</div><div class='add'>+		*val = state-&gt;dac_value[chan-&gt;channel];</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		*val = MCP4821_2X_GAIN_VREF_MV;</div><div class='add'>+		*val2 = chan-&gt;scan_type.realbits;</div><div class='add'>+		return IIO_VAL_FRACTIONAL_LOG2;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp4821_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan, int val,</div><div class='add'>+			     int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct mcp4821_state *state = iio_priv(indio_dev);</div><div class='add'>+	u16 write_val;</div><div class='add'>+	__be16 write_buffer;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (val2 != 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (val &lt; 0 || val &gt;= BIT(chan-&gt;scan_type.realbits))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (mask != IIO_CHAN_INFO_RAW)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	write_val = MCP4821_ACTIVE_MODE | val &lt;&lt; chan-&gt;scan_type.shift;</div><div class='add'>+	if (chan-&gt;channel)</div><div class='add'>+		write_val |= MCP4802_SECOND_CHAN;</div><div class='add'>+</div><div class='add'>+	write_buffer = cpu_to_be16(write_val);</div><div class='add'>+	ret = spi_write(state-&gt;spi, &amp;write_buffer, sizeof(write_buffer));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;state-&gt;spi-&gt;dev, "Failed to write to device: %d", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;dac_value[chan-&gt;channel] = val;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info mcp4821_info = {</div><div class='add'>+	.read_raw = &amp;mcp4821_read_raw,</div><div class='add'>+	.write_raw = &amp;mcp4821_write_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mcp4821_probe(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct mcp4821_state *state;</div><div class='add'>+	const struct mcp4821_chip_info *info;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;spi-&gt;dev, sizeof(*state));</div><div class='add'>+	if (indio_dev == NULL)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	state = iio_priv(indio_dev);</div><div class='add'>+	state-&gt;spi = spi;</div><div class='add'>+</div><div class='add'>+	info = spi_get_device_match_data(spi);</div><div class='add'>+	indio_dev-&gt;name = info-&gt;name;</div><div class='add'>+	indio_dev-&gt;info = &amp;mcp4821_info;</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+	indio_dev-&gt;channels = info-&gt;channels;</div><div class='add'>+	indio_dev-&gt;num_channels = info-&gt;num_channels;</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(&amp;spi-&gt;dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MCP4821_COMPATIBLE(of_compatible, id)        \</div><div class='add'>+	{                                            \</div><div class='add'>+		.compatible = of_compatible,         \</div><div class='add'>+		.data = &amp;mcp4821_chip_info_table[id] \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id mcp4821_of_table[] = {</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4801", ID_MCP4801),</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4802", ID_MCP4802),</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4811", ID_MCP4811),</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4812", ID_MCP4812),</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4821", ID_MCP4821),</div><div class='add'>+	MCP4821_COMPATIBLE("microchip,mcp4822", ID_MCP4822),</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, mcp4821_of_table);</div><div class='add'>+</div><div class='add'>+static const struct spi_device_id mcp4821_id_table[] = {</div><div class='add'>+	{ "mcp4801", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4801]},</div><div class='add'>+	{ "mcp4802", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4802]},</div><div class='add'>+	{ "mcp4811", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4811]},</div><div class='add'>+	{ "mcp4812", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4812]},</div><div class='add'>+	{ "mcp4821", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4821]},</div><div class='add'>+	{ "mcp4822", (kernel_ulong_t)&amp;mcp4821_chip_info_table[ID_MCP4822]},</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, mcp4821_id_table);</div><div class='add'>+</div><div class='add'>+static struct spi_driver mcp4821_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "mcp4821",</div><div class='add'>+		.of_match_table = mcp4821_of_table,</div><div class='add'>+	},</div><div class='add'>+	.probe = mcp4821_probe,</div><div class='add'>+	.id_table = mcp4821_id_table,</div><div class='add'>+};</div><div class='add'>+module_spi_driver(mcp4821_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Anshul Dalal &lt;anshulusr@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Microchip MCP4821 DAC Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/frequency/adf4377.c b/drivers/iio/frequency/adf4377.c<br/>index 26abecbd51e0..9284c13f1abb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/frequency/adf4377.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/frequency/adf4377.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/frequency/adf4377.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/frequency/adf4377.c</a></div><div class='hunk'>@@ -870,7 +870,6 @@ static const struct iio_chan_spec adf4377_channels[] = {</div><div class='ctx'> static int adf4377_properties_parse(struct adf4377_state *st)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_device *spi = st-&gt;spi;</div><div class='del'>-	const char *str;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	st-&gt;clkin = devm_clk_get_enabled(&amp;spi-&gt;dev, "ref_in");</div><div class='hunk'>@@ -896,16 +895,13 @@ static int adf4377_properties_parse(struct adf4377_state *st)</div><div class='ctx'> 		return dev_err_probe(&amp;spi-&gt;dev, PTR_ERR(st-&gt;gpio_enclk2),</div><div class='ctx'> 				     "failed to get the CE GPIO\n");</div><div class='ctx'> </div><div class='del'>-	ret = device_property_read_string(&amp;spi-&gt;dev, "adi,muxout-select", &amp;str);</div><div class='del'>-	if (ret) {</div><div class='del'>-		st-&gt;muxout_select = ADF4377_MUXOUT_HIGH_Z;</div><div class='del'>-	} else {</div><div class='del'>-		ret = match_string(adf4377_muxout_modes, ARRAY_SIZE(adf4377_muxout_modes), str);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='add'>+	ret = device_property_match_property_string(&amp;spi-&gt;dev, "adi,muxout-select",</div><div class='add'>+						    adf4377_muxout_modes,</div><div class='add'>+						    ARRAY_SIZE(adf4377_muxout_modes));</div><div class='add'>+	if (ret &gt;= 0)</div><div class='ctx'> 		st-&gt;muxout_select = ret;</div><div class='del'>-	}</div><div class='add'>+	else</div><div class='add'>+		st-&gt;muxout_select = ADF4377_MUXOUT_HIGH_Z;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c<br/>index bb5e1feef42b..b46b73b89eb7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/frequency/admv1014.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/frequency/admv1014.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/frequency/admv1014.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/frequency/admv1014.c</a></div><div class='hunk'>@@ -710,7 +710,6 @@ static int admv1014_init(struct admv1014_state *st)</div><div class='ctx'> </div><div class='ctx'> static int admv1014_properties_parse(struct admv1014_state *st)</div><div class='ctx'> {</div><div class='del'>-	const char *str;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	struct spi_device *spi = st-&gt;spi;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -719,27 +718,21 @@ static int admv1014_properties_parse(struct admv1014_state *st)</div><div class='ctx'> </div><div class='ctx'> 	st-&gt;p1db_comp = device_property_read_bool(&amp;spi-&gt;dev, "adi,p1db-compensation-enable");</div><div class='ctx'> </div><div class='del'>-	ret = device_property_read_string(&amp;spi-&gt;dev, "adi,input-mode", &amp;str);</div><div class='del'>-	if (ret) {</div><div class='del'>-		st-&gt;input_mode = ADMV1014_IQ_MODE;</div><div class='del'>-	} else {</div><div class='del'>-		ret = match_string(input_mode_names, ARRAY_SIZE(input_mode_names), str);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='add'>+	ret = device_property_match_property_string(&amp;spi-&gt;dev, "adi,input-mode",</div><div class='add'>+						    input_mode_names,</div><div class='add'>+						    ARRAY_SIZE(input_mode_names));</div><div class='add'>+	if (ret &gt;= 0)</div><div class='ctx'> 		st-&gt;input_mode = ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = device_property_read_string(&amp;spi-&gt;dev, "adi,quad-se-mode", &amp;str);</div><div class='del'>-	if (ret) {</div><div class='del'>-		st-&gt;quad_se_mode = ADMV1014_SE_MODE_POS;</div><div class='del'>-	} else {</div><div class='del'>-		ret = match_string(quad_se_mode_names, ARRAY_SIZE(quad_se_mode_names), str);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='add'>+	else</div><div class='add'>+		st-&gt;input_mode = ADMV1014_IQ_MODE;</div><div class='ctx'> </div><div class='add'>+	ret = device_property_match_property_string(&amp;spi-&gt;dev, "adi,quad-se-mode",</div><div class='add'>+						    quad_se_mode_names,</div><div class='add'>+						    ARRAY_SIZE(quad_se_mode_names));</div><div class='add'>+	if (ret &gt;= 0)</div><div class='ctx'> 		st-&gt;quad_se_mode = ADMV1014_SE_MODE_POS + (ret * 3);</div><div class='del'>-	}</div><div class='add'>+	else</div><div class='add'>+		st-&gt;quad_se_mode = ADMV1014_SE_MODE_POS;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ADMV1014_NUM_REGULATORS; ++i)</div><div class='ctx'> 		st-&gt;regulators[i].supply = admv1014_reg_name[i];</div><div class='head'>diff --git a/drivers/iio/humidity/hdc3020.c b/drivers/iio/humidity/hdc3020.c<br/>new file mode 100644<br/>index 000000000000..4e3311170725<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/humidity/hdc3020.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/humidity/hdc3020.c</a></div><div class='hunk'>@@ -0,0 +1,473 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * hdc3020.c - Support for the TI HDC3020,HDC3021 and HDC3022</div><div class='add'>+ * temperature + relative humidity sensors</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://www.ti.com/lit/ds/symlink/hdc3020.pdf</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitops.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/crc8.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#define HDC3020_HEATER_CMD_MSB		0x30 /* shared by all heater commands */</div><div class='add'>+#define HDC3020_HEATER_ENABLE		0x6D</div><div class='add'>+#define HDC3020_HEATER_DISABLE		0x66</div><div class='add'>+#define HDC3020_HEATER_CONFIG		0x6E</div><div class='add'>+</div><div class='add'>+#define HDC3020_READ_RETRY_TIMES	10</div><div class='add'>+#define HDC3020_BUSY_DELAY_MS		10</div><div class='add'>+</div><div class='add'>+#define HDC3020_CRC8_POLYNOMIAL		0x31</div><div class='add'>+</div><div class='add'>+static const u8 HDC3020_S_AUTO_10HZ_MOD0[2] = { 0x27, 0x37 };</div><div class='add'>+</div><div class='add'>+static const u8 HDC3020_EXIT_AUTO[2] = { 0x30, 0x93 };</div><div class='add'>+</div><div class='add'>+static const u8 HDC3020_R_T_RH_AUTO[2] = { 0xE0, 0x00 };</div><div class='add'>+static const u8 HDC3020_R_T_LOW_AUTO[2] = { 0xE0, 0x02 };</div><div class='add'>+static const u8 HDC3020_R_T_HIGH_AUTO[2] = { 0xE0, 0x03 };</div><div class='add'>+static const u8 HDC3020_R_RH_LOW_AUTO[2] = { 0xE0, 0x04 };</div><div class='add'>+static const u8 HDC3020_R_RH_HIGH_AUTO[2] = { 0xE0, 0x05 };</div><div class='add'>+</div><div class='add'>+struct hdc3020_data {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+	/*</div><div class='add'>+	 * Ensure that the sensor configuration (currently only heater is</div><div class='add'>+	 * supported) will not be changed during the process of reading</div><div class='add'>+	 * sensor data (this driver will try HDC3020_READ_RETRY_TIMES times</div><div class='add'>+	 * if the device does not respond).</div><div class='add'>+	 */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int hdc3020_heater_vals[] = {0, 1, 0x3FFF};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec hdc3020_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_PEAK) |</div><div class='add'>+		BIT(IIO_CHAN_INFO_TROUGH) | BIT(IIO_CHAN_INFO_OFFSET),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_HUMIDITYRELATIVE,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_PEAK) |</div><div class='add'>+		BIT(IIO_CHAN_INFO_TROUGH),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		/*</div><div class='add'>+		 * For setting the internal heater, which can be switched on to</div><div class='add'>+		 * prevent or remove any condensation that may develop when the</div><div class='add'>+		 * ambient environment approaches its dew point temperature.</div><div class='add'>+		 */</div><div class='add'>+		.type = IIO_CURRENT,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),</div><div class='add'>+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW),</div><div class='add'>+		.output = 1,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+DECLARE_CRC8_TABLE(hdc3020_crc8_table);</div><div class='add'>+</div><div class='add'>+static int hdc3020_write_bytes(struct hdc3020_data *data, const u8 *buf, u8 len)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = data-&gt;client;</div><div class='add'>+	struct i2c_msg msg;</div><div class='add'>+	int ret, cnt;</div><div class='add'>+</div><div class='add'>+	msg.addr = client-&gt;addr;</div><div class='add'>+	msg.flags = 0;</div><div class='add'>+	msg.buf = (char *)buf;</div><div class='add'>+	msg.len = len;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * During the measurement process, HDC3020 will not return data.</div><div class='add'>+	 * So wait for a while and try again</div><div class='add'>+	 */</div><div class='add'>+	for (cnt = 0; cnt &lt; HDC3020_READ_RETRY_TIMES; cnt++) {</div><div class='add'>+		ret = i2c_transfer(client-&gt;adapter, &amp;msg, 1);</div><div class='add'>+		if (ret == 1)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		mdelay(HDC3020_BUSY_DELAY_MS);</div><div class='add'>+	}</div><div class='add'>+	dev_err(&amp;client-&gt;dev, "Could not write sensor command\n");</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_read_bytes(struct hdc3020_data *data, const u8 *buf,</div><div class='add'>+			      void *val, int len)</div><div class='add'>+{</div><div class='add'>+	int ret, cnt;</div><div class='add'>+	struct i2c_client *client = data-&gt;client;</div><div class='add'>+	struct i2c_msg msg[2] = {</div><div class='add'>+		[0] = {</div><div class='add'>+			.addr = client-&gt;addr,</div><div class='add'>+			.flags = 0,</div><div class='add'>+			.buf = (char *)buf,</div><div class='add'>+			.len = 2,</div><div class='add'>+		},</div><div class='add'>+		[1] = {</div><div class='add'>+			.addr = client-&gt;addr,</div><div class='add'>+			.flags = I2C_M_RD,</div><div class='add'>+			.buf = val,</div><div class='add'>+			.len = len,</div><div class='add'>+		},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * During the measurement process, HDC3020 will not return data.</div><div class='add'>+	 * So wait for a while and try again</div><div class='add'>+	 */</div><div class='add'>+	for (cnt = 0; cnt &lt; HDC3020_READ_RETRY_TIMES; cnt++) {</div><div class='add'>+		ret = i2c_transfer(client-&gt;adapter, msg, 2);</div><div class='add'>+		if (ret == 2)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		mdelay(HDC3020_BUSY_DELAY_MS);</div><div class='add'>+	}</div><div class='add'>+	dev_err(&amp;client-&gt;dev, "Could not read sensor data\n");</div><div class='add'>+</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_read_measurement(struct hdc3020_data *data,</div><div class='add'>+				    enum iio_chan_type type, int *val)</div><div class='add'>+{</div><div class='add'>+	u8 crc, buf[6];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_read_bytes(data, HDC3020_R_T_RH_AUTO, buf, 6);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* CRC check of the temperature measurement */</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* CRC check of the relative humidity measurement */</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf + 3, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[5])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (type == IIO_TEMP)</div><div class='add'>+		*val = get_unaligned_be16(buf);</div><div class='add'>+	else if (type == IIO_HUMIDITYRELATIVE)</div><div class='add'>+		*val = get_unaligned_be16(&amp;buf[3]);</div><div class='add'>+	else</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * After exiting the automatic measurement mode or resetting, the peak</div><div class='add'>+ * value will be reset to the default value</div><div class='add'>+ * This method is used to get the highest temp measured during automatic</div><div class='add'>+ * measurement</div><div class='add'>+ */</div><div class='add'>+static int hdc3020_read_high_peak_t(struct hdc3020_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	u8 crc, buf[3];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_read_bytes(data, HDC3020_R_T_HIGH_AUTO, buf, 3);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*val = get_unaligned_be16(buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This method is used to get the lowest temp measured during automatic</div><div class='add'>+ * measurement</div><div class='add'>+ */</div><div class='add'>+static int hdc3020_read_low_peak_t(struct hdc3020_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	u8 crc, buf[3];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_read_bytes(data, HDC3020_R_T_LOW_AUTO, buf, 3);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*val = get_unaligned_be16(buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This method is used to get the highest humidity measured during automatic</div><div class='add'>+ * measurement</div><div class='add'>+ */</div><div class='add'>+static int hdc3020_read_high_peak_rh(struct hdc3020_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	u8 crc, buf[3];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_read_bytes(data, HDC3020_R_RH_HIGH_AUTO, buf, 3);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*val = get_unaligned_be16(buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This method is used to get the lowest humidity measured during automatic</div><div class='add'>+ * measurement</div><div class='add'>+ */</div><div class='add'>+static int hdc3020_read_low_peak_rh(struct hdc3020_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	u8 crc, buf[3];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_read_bytes(data, HDC3020_R_RH_LOW_AUTO, buf, 3);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	crc = crc8(hdc3020_crc8_table, buf, 2, CRC8_INIT_VALUE);</div><div class='add'>+	if (crc != buf[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*val = get_unaligned_be16(buf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			    struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			    int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct hdc3020_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (chan-&gt;type != IIO_TEMP &amp;&amp; chan-&gt;type != IIO_HUMIDITYRELATIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW: {</div><div class='add'>+		guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+		ret = hdc3020_read_measurement(data, chan-&gt;type, val);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	}</div><div class='add'>+	case IIO_CHAN_INFO_PEAK: {</div><div class='add'>+		guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+		if (chan-&gt;type == IIO_TEMP) {</div><div class='add'>+			ret = hdc3020_read_high_peak_t(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		} else {</div><div class='add'>+			ret = hdc3020_read_high_peak_rh(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	}</div><div class='add'>+	case IIO_CHAN_INFO_TROUGH: {</div><div class='add'>+		guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+		if (chan-&gt;type == IIO_TEMP) {</div><div class='add'>+			ret = hdc3020_read_low_peak_t(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		} else {</div><div class='add'>+			ret = hdc3020_read_low_peak_rh(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+		}</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	}</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		*val2 = 65536;</div><div class='add'>+		if (chan-&gt;type == IIO_TEMP)</div><div class='add'>+			*val = 175;</div><div class='add'>+		else</div><div class='add'>+			*val = 100;</div><div class='add'>+		return IIO_VAL_FRACTIONAL;</div><div class='add'>+</div><div class='add'>+	case IIO_CHAN_INFO_OFFSET:</div><div class='add'>+		if (chan-&gt;type != IIO_TEMP)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		*val = 16852;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_read_available(struct iio_dev *indio_dev,</div><div class='add'>+				  struct iio_chan_spec const *chan,</div><div class='add'>+				  const int **vals,</div><div class='add'>+				  int *type, int *length, long mask)</div><div class='add'>+{</div><div class='add'>+	if (mask != IIO_CHAN_INFO_RAW || chan-&gt;type != IIO_CURRENT)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*vals = hdc3020_heater_vals;</div><div class='add'>+	*type = IIO_VAL_INT;</div><div class='add'>+</div><div class='add'>+	return IIO_AVAIL_RANGE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_update_heater(struct hdc3020_data *data, int val)</div><div class='add'>+{</div><div class='add'>+	u8 buf[5];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (val &lt; hdc3020_heater_vals[0] || val &gt; hdc3020_heater_vals[2])</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	buf[0] = HDC3020_HEATER_CMD_MSB;</div><div class='add'>+</div><div class='add'>+	if (!val) {</div><div class='add'>+		buf[1] = HDC3020_HEATER_DISABLE;</div><div class='add'>+		return hdc3020_write_bytes(data, buf, 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	buf[1] = HDC3020_HEATER_CONFIG;</div><div class='add'>+	put_unaligned_be16(val &amp; GENMASK(13, 0), &amp;buf[2]);</div><div class='add'>+	buf[4] = crc8(hdc3020_crc8_table, buf + 2, 2, CRC8_INIT_VALUE);</div><div class='add'>+	ret = hdc3020_write_bytes(data, buf, 5);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	buf[1] = HDC3020_HEATER_ENABLE;</div><div class='add'>+</div><div class='add'>+	return hdc3020_write_bytes(data, buf, 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     int val, int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct hdc3020_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		if (chan-&gt;type != IIO_CURRENT)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+		return hdc3020_update_heater(data, val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info hdc3020_info = {</div><div class='add'>+	.read_raw = hdc3020_read_raw,</div><div class='add'>+	.write_raw = hdc3020_write_raw,</div><div class='add'>+	.read_avail = hdc3020_read_available,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void hdc3020_stop(void *data)</div><div class='add'>+{</div><div class='add'>+	hdc3020_write_bytes((struct hdc3020_data *)data, HDC3020_EXIT_AUTO, 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hdc3020_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct hdc3020_data *data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!i2c_check_functionality(client-&gt;adapter, I2C_FUNC_I2C))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+	data-&gt;client = client;</div><div class='add'>+	mutex_init(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	crc8_populate_msb(hdc3020_crc8_table, HDC3020_CRC8_POLYNOMIAL);</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;name = "hdc3020";</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+	indio_dev-&gt;info = &amp;hdc3020_info;</div><div class='add'>+	indio_dev-&gt;channels = hdc3020_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(hdc3020_channels);</div><div class='add'>+</div><div class='add'>+	ret = hdc3020_write_bytes(data, HDC3020_S_AUTO_10HZ_MOD0, 2);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "Unable to set up measurement\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_add_action_or_reset(&amp;data-&gt;client-&gt;dev, hdc3020_stop, data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_iio_device_register(&amp;data-&gt;client-&gt;dev, indio_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret, "Failed to add device");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id hdc3020_id[] = {</div><div class='add'>+	{ "hdc3020" },</div><div class='add'>+	{ "hdc3021" },</div><div class='add'>+	{ "hdc3022" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, hdc3020_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id hdc3020_dt_ids[] = {</div><div class='add'>+	{ .compatible = "ti,hdc3020" },</div><div class='add'>+	{ .compatible = "ti,hdc3021" },</div><div class='add'>+	{ .compatible = "ti,hdc3022" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, hdc3020_dt_ids);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver hdc3020_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "hdc3020",</div><div class='add'>+		.of_match_table = hdc3020_dt_ids,</div><div class='add'>+	},</div><div class='add'>+	.probe = hdc3020_probe,</div><div class='add'>+	.id_table = hdc3020_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(hdc3020_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Javier Carrasco &lt;javier.carrasco.cruz@gmail.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Li peiyu &lt;579lpy@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("TI HDC3020 humidity and temperature sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig<br/>index c2f97629e9cd..52a155ff3250 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/Kconfig</a></div><div class='hunk'>@@ -53,6 +53,7 @@ config ADIS16480</div><div class='ctx'> 	  ADIS16485, ADIS16488 inertial sensors.</div><div class='ctx'> </div><div class='ctx'> source "drivers/iio/imu/bmi160/Kconfig"</div><div class='add'>+source "drivers/iio/imu/bmi323/Kconfig"</div><div class='ctx'> source "drivers/iio/imu/bno055/Kconfig"</div><div class='ctx'> </div><div class='ctx'> config FXOS8700</div><div class='head'>diff --git a/drivers/iio/imu/Makefile b/drivers/iio/imu/Makefile<br/>index 6eb612034722..7e2d7d5c3b7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/Makefile</a></div><div class='hunk'>@@ -15,6 +15,7 @@ adis_lib-$(CONFIG_IIO_ADIS_LIB_BUFFER) += adis_buffer.o</div><div class='ctx'> obj-$(CONFIG_IIO_ADIS_LIB) += adis_lib.o</div><div class='ctx'> </div><div class='ctx'> obj-y += bmi160/</div><div class='add'>+obj-y += bmi323/</div><div class='ctx'> obj-y += bno055/</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_FXOS8700) += fxos8700_core.o</div><div class='head'>diff --git a/drivers/iio/imu/adis.c b/drivers/iio/imu/adis.c<br/>index bc40240b29e2..495caf4ce87a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/adis.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/adis.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/adis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/adis.c</a></div><div class='hunk'>@@ -44,8 +44,6 @@ int __adis_write_reg(struct adis *adis, unsigned int reg, unsigned int value,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;write_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.tx_buf = adis-&gt;tx + 2,</div><div class='ctx'> 			.bits_per_word = 8,</div><div class='hunk'>@@ -53,8 +51,6 @@ int __adis_write_reg(struct adis *adis, unsigned int reg, unsigned int value,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;write_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.tx_buf = adis-&gt;tx + 4,</div><div class='ctx'> 			.bits_per_word = 8,</div><div class='hunk'>@@ -62,8 +58,6 @@ int __adis_write_reg(struct adis *adis, unsigned int reg, unsigned int value,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;write_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.tx_buf = adis-&gt;tx + 6,</div><div class='ctx'> 			.bits_per_word = 8,</div><div class='hunk'>@@ -144,8 +138,6 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, unsigned int *val,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;write_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.tx_buf = adis-&gt;tx + 2,</div><div class='ctx'> 			.bits_per_word = 8,</div><div class='hunk'>@@ -153,8 +145,6 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, unsigned int *val,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;read_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.tx_buf = adis-&gt;tx + 4,</div><div class='ctx'> 			.rx_buf = adis-&gt;rx,</div><div class='hunk'>@@ -163,8 +153,6 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, unsigned int *val,</div><div class='ctx'> 			.cs_change = 1,</div><div class='ctx'> 			.delay.value = adis-&gt;data-&gt;read_delay,</div><div class='ctx'> 			.delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='del'>-			.cs_change_delay.value = adis-&gt;data-&gt;cs_change_delay,</div><div class='del'>-			.cs_change_delay.unit = SPI_DELAY_UNIT_USECS,</div><div class='ctx'> 		}, {</div><div class='ctx'> 			.rx_buf = adis-&gt;rx + 2,</div><div class='ctx'> 			.bits_per_word = 8,</div><div class='hunk'>@@ -524,6 +512,12 @@ int adis_init(struct adis *adis, struct iio_dev *indio_dev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;adis-&gt;state_lock);</div><div class='add'>+</div><div class='add'>+	if (!spi-&gt;cs_inactive.value) {</div><div class='add'>+		spi-&gt;cs_inactive.value = data-&gt;cs_change_delay;</div><div class='add'>+		spi-&gt;cs_inactive.unit = SPI_DELAY_UNIT_USECS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	adis-&gt;spi = spi;</div><div class='ctx'> 	adis-&gt;data = data;</div><div class='ctx'> 	iio_device_set_drvdata(indio_dev, adis);</div><div class='head'>diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c<br/>index b7cbe1565aee..64be656f0b80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/adis16475.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/adis16475.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/adis16475.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/adis16475.c</a></div><div class='hunk'>@@ -70,8 +70,8 @@</div><div class='ctx'> #define ADIS16475_MAX_SCAN_DATA		20</div><div class='ctx'> /* spi max speed in brust mode */</div><div class='ctx'> #define ADIS16475_BURST_MAX_SPEED	1000000</div><div class='del'>-#define ADIS16475_LSB_DEC_MASK		BIT(0)</div><div class='del'>-#define ADIS16475_LSB_FIR_MASK		BIT(1)</div><div class='add'>+#define ADIS16475_LSB_DEC_MASK		0</div><div class='add'>+#define ADIS16475_LSB_FIR_MASK		1</div><div class='ctx'> #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK	GENMASK(5, 0)</div><div class='ctx'> #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK	GENMASK(12, 7)</div><div class='ctx'> </div><div class='hunk'>@@ -1406,50 +1406,6 @@ static int adis16475_config_irq_pin(struct adis16475 *st)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct of_device_id adis16475_of_match[] = {</div><div class='del'>-	{ .compatible = "adi,adis16470",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16470] },</div><div class='del'>-	{ .compatible = "adi,adis16475-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16475_1] },</div><div class='del'>-	{ .compatible = "adi,adis16475-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16475_2] },</div><div class='del'>-	{ .compatible = "adi,adis16475-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16475_3] },</div><div class='del'>-	{ .compatible = "adi,adis16477-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16477_1] },</div><div class='del'>-	{ .compatible = "adi,adis16477-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16477_2] },</div><div class='del'>-	{ .compatible = "adi,adis16477-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16477_3] },</div><div class='del'>-	{ .compatible = "adi,adis16465-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16465_1] },</div><div class='del'>-	{ .compatible = "adi,adis16465-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16465_2] },</div><div class='del'>-	{ .compatible = "adi,adis16465-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16465_3] },</div><div class='del'>-	{ .compatible = "adi,adis16467-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16467_1] },</div><div class='del'>-	{ .compatible = "adi,adis16467-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16467_2] },</div><div class='del'>-	{ .compatible = "adi,adis16467-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16467_3] },</div><div class='del'>-	{ .compatible = "adi,adis16500",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16500] },</div><div class='del'>-	{ .compatible = "adi,adis16505-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16505_1] },</div><div class='del'>-	{ .compatible = "adi,adis16505-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16505_2] },</div><div class='del'>-	{ .compatible = "adi,adis16505-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16505_3] },</div><div class='del'>-	{ .compatible = "adi,adis16507-1",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16507_1] },</div><div class='del'>-	{ .compatible = "adi,adis16507-2",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16507_2] },</div><div class='del'>-	{ .compatible = "adi,adis16507-3",</div><div class='del'>-		.data = &amp;adis16475_chip_info[ADIS16507_3] },</div><div class='del'>-	{ },</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(of, adis16475_of_match);</div><div class='ctx'> </div><div class='ctx'> static int adis16475_probe(struct spi_device *spi)</div><div class='ctx'> {</div><div class='hunk'>@@ -1463,7 +1419,7 @@ static int adis16475_probe(struct spi_device *spi)</div><div class='ctx'> </div><div class='ctx'> 	st = iio_priv(indio_dev);</div><div class='ctx'> </div><div class='del'>-	st-&gt;info = device_get_match_data(&amp;spi-&gt;dev);</div><div class='add'>+	st-&gt;info = spi_get_device_match_data(spi);</div><div class='ctx'> 	if (!st-&gt;info)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1503,12 +1459,83 @@ static int adis16475_probe(struct spi_device *spi)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct of_device_id adis16475_of_match[] = {</div><div class='add'>+	{ .compatible = "adi,adis16470",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16470] },</div><div class='add'>+	{ .compatible = "adi,adis16475-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16475_1] },</div><div class='add'>+	{ .compatible = "adi,adis16475-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16475_2] },</div><div class='add'>+	{ .compatible = "adi,adis16475-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16475_3] },</div><div class='add'>+	{ .compatible = "adi,adis16477-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16477_1] },</div><div class='add'>+	{ .compatible = "adi,adis16477-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16477_2] },</div><div class='add'>+	{ .compatible = "adi,adis16477-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16477_3] },</div><div class='add'>+	{ .compatible = "adi,adis16465-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16465_1] },</div><div class='add'>+	{ .compatible = "adi,adis16465-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16465_2] },</div><div class='add'>+	{ .compatible = "adi,adis16465-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16465_3] },</div><div class='add'>+	{ .compatible = "adi,adis16467-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16467_1] },</div><div class='add'>+	{ .compatible = "adi,adis16467-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16467_2] },</div><div class='add'>+	{ .compatible = "adi,adis16467-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16467_3] },</div><div class='add'>+	{ .compatible = "adi,adis16500",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16500] },</div><div class='add'>+	{ .compatible = "adi,adis16505-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16505_1] },</div><div class='add'>+	{ .compatible = "adi,adis16505-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16505_2] },</div><div class='add'>+	{ .compatible = "adi,adis16505-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16505_3] },</div><div class='add'>+	{ .compatible = "adi,adis16507-1",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16507_1] },</div><div class='add'>+	{ .compatible = "adi,adis16507-2",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16507_2] },</div><div class='add'>+	{ .compatible = "adi,adis16507-3",</div><div class='add'>+		.data = &amp;adis16475_chip_info[ADIS16507_3] },</div><div class='add'>+	{ },</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, adis16475_of_match);</div><div class='add'>+</div><div class='add'>+static const struct spi_device_id adis16475_ids[] = {</div><div class='add'>+	{ "adis16470", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16470] },</div><div class='add'>+	{ "adis16475-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16475_1] },</div><div class='add'>+	{ "adis16475-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16475_2] },</div><div class='add'>+	{ "adis16475-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16475_3] },</div><div class='add'>+	{ "adis16477-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16477_1] },</div><div class='add'>+	{ "adis16477-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16477_2] },</div><div class='add'>+	{ "adis16477-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16477_3] },</div><div class='add'>+	{ "adis16465-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16465_1] },</div><div class='add'>+	{ "adis16465-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16465_2] },</div><div class='add'>+	{ "adis16465-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16465_3] },</div><div class='add'>+	{ "adis16467-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16467_1] },</div><div class='add'>+	{ "adis16467-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16467_2] },</div><div class='add'>+	{ "adis16467-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16467_3] },</div><div class='add'>+	{ "adis16500", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16500] },</div><div class='add'>+	{ "adis16505-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16505_1] },</div><div class='add'>+	{ "adis16505-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16505_2] },</div><div class='add'>+	{ "adis16505-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16505_3] },</div><div class='add'>+	{ "adis16507-1", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16507_1] },</div><div class='add'>+	{ "adis16507-2", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16507_2] },</div><div class='add'>+	{ "adis16507-3", (kernel_ulong_t)&amp;adis16475_chip_info[ADIS16507_3] },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, adis16475_ids);</div><div class='add'>+</div><div class='ctx'> static struct spi_driver adis16475_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "adis16475",</div><div class='ctx'> 		.of_match_table = adis16475_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = adis16475_probe,</div><div class='add'>+	.id_table = adis16475_ids,</div><div class='ctx'> };</div><div class='ctx'> module_spi_driver(adis16475_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/imu/bmi323/Kconfig b/drivers/iio/imu/bmi323/Kconfig<br/>new file mode 100644<br/>index 000000000000..ab37b285393c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# BMI323 IMU driver</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+config BMI323</div><div class='add'>+	tristate</div><div class='add'>+	select IIO_BUFFER</div><div class='add'>+	select IIO_TRIGGERED_BUFFER</div><div class='add'>+</div><div class='add'>+config BMI323_I2C</div><div class='add'>+	tristate "Bosch BMI323 I2C driver"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select BMI323</div><div class='add'>+	select REGMAP_I2C</div><div class='add'>+	help</div><div class='add'>+	  Enable support for the Bosch BMI323 6-Axis IMU connected to I2C</div><div class='add'>+	  interface.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module will be</div><div class='add'>+	  called bmi323_i2c.</div><div class='add'>+</div><div class='add'>+config BMI323_SPI</div><div class='add'>+	tristate "Bosch BMI323 SPI driver"</div><div class='add'>+	depends on SPI</div><div class='add'>+	select BMI323</div><div class='add'>+	select REGMAP_SPI</div><div class='add'>+	help</div><div class='add'>+	  Enable support for the Bosch BMI323 6-Axis IMU connected to SPI</div><div class='add'>+	  interface.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module will be</div><div class='add'>+	  called bmi323_spi.</div><div class='head'>diff --git a/drivers/iio/imu/bmi323/Makefile b/drivers/iio/imu/bmi323/Makefile<br/>new file mode 100644<br/>index 000000000000..a6a6dc0207c9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/Makefile</a></div><div class='hunk'>@@ -0,0 +1,7 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# Makefile for Bosch BMI323 IMU</div><div class='add'>+#</div><div class='add'>+obj-$(CONFIG_BMI323) += bmi323_core.o</div><div class='add'>+obj-$(CONFIG_BMI323_I2C) += bmi323_i2c.o</div><div class='add'>+obj-$(CONFIG_BMI323_SPI) += bmi323_spi.o</div><div class='head'>diff --git a/drivers/iio/imu/bmi323/bmi323.h b/drivers/iio/imu/bmi323/bmi323.h<br/>new file mode 100644<br/>index 000000000000..dff126d41658<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/bmi323.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323.h</a></div><div class='hunk'>@@ -0,0 +1,209 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * IIO driver for Bosch BMI323 6-Axis IMU</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023, Jagath Jog J &lt;jagathjog1996@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _BMI323_H_</div><div class='add'>+#define _BMI323_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#define BMI323_I2C_DUMMY			2</div><div class='add'>+#define BMI323_SPI_DUMMY			1</div><div class='add'>+</div><div class='add'>+/* Register map */</div><div class='add'>+</div><div class='add'>+#define BMI323_CHIP_ID_REG			0x00</div><div class='add'>+#define BMI323_CHIP_ID_VAL			0x0043</div><div class='add'>+#define BMI323_CHIP_ID_MSK			GENMASK(7, 0)</div><div class='add'>+#define BMI323_ERR_REG				0x01</div><div class='add'>+#define BMI323_STATUS_REG			0x02</div><div class='add'>+#define BMI323_STATUS_POR_MSK			BIT(0)</div><div class='add'>+</div><div class='add'>+/* Accelero/Gyro/Temp data registers */</div><div class='add'>+#define BMI323_ACCEL_X_REG			0x03</div><div class='add'>+#define BMI323_GYRO_X_REG			0x06</div><div class='add'>+#define BMI323_TEMP_REG				0x09</div><div class='add'>+#define BMI323_ALL_CHAN_MSK			GENMASK(5, 0)</div><div class='add'>+</div><div class='add'>+/* Status registers */</div><div class='add'>+#define BMI323_STATUS_INT1_REG			0x0D</div><div class='add'>+#define BMI323_STATUS_INT2_REG			0x0E</div><div class='add'>+#define BMI323_STATUS_NOMOTION_MSK		BIT(0)</div><div class='add'>+#define BMI323_STATUS_MOTION_MSK		BIT(1)</div><div class='add'>+#define BMI323_STATUS_STP_WTR_MSK		BIT(5)</div><div class='add'>+#define BMI323_STATUS_TAP_MSK			BIT(8)</div><div class='add'>+#define BMI323_STATUS_ERROR_MSK			BIT(10)</div><div class='add'>+#define BMI323_STATUS_TMP_DRDY_MSK		BIT(11)</div><div class='add'>+#define BMI323_STATUS_GYR_DRDY_MSK		BIT(12)</div><div class='add'>+#define BMI323_STATUS_ACC_DRDY_MSK		BIT(13)</div><div class='add'>+#define BMI323_STATUS_ACC_GYR_DRDY_MSK		GENMASK(13, 12)</div><div class='add'>+#define BMI323_STATUS_FIFO_WTRMRK_MSK		BIT(14)</div><div class='add'>+#define BMI323_STATUS_FIFO_FULL_MSK		BIT(15)</div><div class='add'>+</div><div class='add'>+/* Feature registers */</div><div class='add'>+#define BMI323_FEAT_IO0_REG			0x10</div><div class='add'>+#define BMI323_FEAT_IO0_XYZ_NOMOTION_MSK	GENMASK(2, 0)</div><div class='add'>+#define BMI323_FEAT_IO0_XYZ_MOTION_MSK		GENMASK(5, 3)</div><div class='add'>+#define BMI323_FEAT_XYZ_MSK			GENMASK(2, 0)</div><div class='add'>+#define BMI323_FEAT_IO0_STP_CNT_MSK		BIT(9)</div><div class='add'>+#define BMI323_FEAT_IO0_S_TAP_MSK		BIT(12)</div><div class='add'>+#define BMI323_FEAT_IO0_D_TAP_MSK		BIT(13)</div><div class='add'>+#define BMI323_FEAT_IO1_REG			0x11</div><div class='add'>+#define BMI323_FEAT_IO1_ERR_MSK			GENMASK(3, 0)</div><div class='add'>+#define BMI323_FEAT_IO2_REG			0x12</div><div class='add'>+#define BMI323_FEAT_IO_STATUS_REG		0x14</div><div class='add'>+#define BMI323_FEAT_IO_STATUS_MSK		BIT(0)</div><div class='add'>+#define BMI323_FEAT_ENG_POLL			2000</div><div class='add'>+#define BMI323_FEAT_ENG_TIMEOUT			10000</div><div class='add'>+</div><div class='add'>+/* FIFO registers */</div><div class='add'>+#define BMI323_FIFO_FILL_LEVEL_REG		0x15</div><div class='add'>+#define BMI323_FIFO_DATA_REG			0x16</div><div class='add'>+</div><div class='add'>+/* Accelero/Gyro config registers */</div><div class='add'>+#define BMI323_ACC_CONF_REG			0x20</div><div class='add'>+#define BMI323_GYRO_CONF_REG			0x21</div><div class='add'>+#define BMI323_ACC_GYRO_CONF_MODE_MSK		GENMASK(14, 12)</div><div class='add'>+#define BMI323_ACC_GYRO_CONF_ODR_MSK		GENMASK(3, 0)</div><div class='add'>+#define BMI323_ACC_GYRO_CONF_SCL_MSK		GENMASK(6, 4)</div><div class='add'>+#define BMI323_ACC_GYRO_CONF_BW_MSK		BIT(7)</div><div class='add'>+#define BMI323_ACC_GYRO_CONF_AVG_MSK		GENMASK(10, 8)</div><div class='add'>+</div><div class='add'>+/* FIFO registers */</div><div class='add'>+#define BMI323_FIFO_WTRMRK_REG			0x35</div><div class='add'>+#define BMI323_FIFO_CONF_REG			0x36</div><div class='add'>+#define BMI323_FIFO_CONF_STP_FUL_MSK		BIT(0)</div><div class='add'>+#define BMI323_FIFO_CONF_ACC_GYR_EN_MSK		GENMASK(10, 9)</div><div class='add'>+#define BMI323_FIFO_ACC_GYR_MSK			GENMASK(1, 0)</div><div class='add'>+#define BMI323_FIFO_CTRL_REG			0x37</div><div class='add'>+#define BMI323_FIFO_FLUSH_MSK			BIT(0)</div><div class='add'>+</div><div class='add'>+/* Interrupt pin config registers */</div><div class='add'>+#define BMI323_IO_INT_CTR_REG			0x38</div><div class='add'>+#define BMI323_IO_INT1_LVL_MSK			BIT(0)</div><div class='add'>+#define BMI323_IO_INT1_OD_MSK			BIT(1)</div><div class='add'>+#define BMI323_IO_INT1_OP_EN_MSK		BIT(2)</div><div class='add'>+#define BMI323_IO_INT1_LVL_OD_OP_MSK		GENMASK(2, 0)</div><div class='add'>+#define BMI323_IO_INT2_LVL_MSK			BIT(8)</div><div class='add'>+#define BMI323_IO_INT2_OD_MSK			BIT(9)</div><div class='add'>+#define BMI323_IO_INT2_OP_EN_MSK		BIT(10)</div><div class='add'>+#define BMI323_IO_INT2_LVL_OD_OP_MSK		GENMASK(10, 8)</div><div class='add'>+#define BMI323_IO_INT_CONF_REG			0x39</div><div class='add'>+#define BMI323_IO_INT_LTCH_MSK			BIT(0)</div><div class='add'>+#define BMI323_INT_MAP1_REG			0x3A</div><div class='add'>+#define BMI323_INT_MAP2_REG			0x3B</div><div class='add'>+#define BMI323_NOMOTION_MSK			GENMASK(1, 0)</div><div class='add'>+#define BMI323_MOTION_MSK			GENMASK(3, 2)</div><div class='add'>+#define BMI323_STEP_CNT_MSK			GENMASK(11, 10)</div><div class='add'>+#define BMI323_TAP_MSK				GENMASK(1, 0)</div><div class='add'>+#define BMI323_TMP_DRDY_MSK			GENMASK(7, 6)</div><div class='add'>+#define BMI323_GYR_DRDY_MSK			GENMASK(9, 8)</div><div class='add'>+#define BMI323_ACC_DRDY_MSK			GENMASK(11, 10)</div><div class='add'>+#define BMI323_FIFO_WTRMRK_MSK			GENMASK(13, 12)</div><div class='add'>+#define BMI323_FIFO_FULL_MSK			GENMASK(15, 14)</div><div class='add'>+</div><div class='add'>+/* Feature registers */</div><div class='add'>+#define BMI323_FEAT_CTRL_REG			0x40</div><div class='add'>+#define BMI323_FEAT_ENG_EN_MSK			BIT(0)</div><div class='add'>+#define BMI323_FEAT_DATA_ADDR			0x41</div><div class='add'>+#define BMI323_FEAT_DATA_TX			0x42</div><div class='add'>+#define BMI323_FEAT_DATA_STATUS			0x43</div><div class='add'>+#define BMI323_FEAT_DATA_TX_RDY_MSK		BIT(1)</div><div class='add'>+#define BMI323_FEAT_EVNT_EXT_REG		0x47</div><div class='add'>+#define BMI323_FEAT_EVNT_EXT_S_MSK		BIT(3)</div><div class='add'>+#define BMI323_FEAT_EVNT_EXT_D_MSK		BIT(4)</div><div class='add'>+</div><div class='add'>+#define BMI323_CMD_REG				0x7E</div><div class='add'>+#define BMI323_RST_VAL				0xDEAF</div><div class='add'>+#define BMI323_CFG_RES_REG			0x7F</div><div class='add'>+</div><div class='add'>+/* Extended registers */</div><div class='add'>+#define BMI323_GEN_SET1_REG			0x02</div><div class='add'>+#define BMI323_GEN_SET1_MODE_MSK		BIT(0)</div><div class='add'>+#define BMI323_GEN_HOLD_DUR_MSK			GENMASK(4, 1)</div><div class='add'>+</div><div class='add'>+/* Any Motion/No Motion config registers */</div><div class='add'>+#define BMI323_ANYMO1_REG			0x05</div><div class='add'>+#define BMI323_NOMO1_REG			0x08</div><div class='add'>+#define BMI323_MO2_OFFSET			0x01</div><div class='add'>+#define BMI323_MO3_OFFSET			0x02</div><div class='add'>+#define BMI323_MO1_REF_UP_MSK			BIT(12)</div><div class='add'>+#define BMI323_MO1_SLOPE_TH_MSK			GENMASK(11, 0)</div><div class='add'>+#define BMI323_MO2_HYSTR_MSK			GENMASK(9, 0)</div><div class='add'>+#define BMI323_MO3_DURA_MSK			GENMASK(12, 0)</div><div class='add'>+</div><div class='add'>+/* Step counter config registers */</div><div class='add'>+#define BMI323_STEP_SC1_REG			0x10</div><div class='add'>+#define BMI323_STEP_SC1_WTRMRK_MSK		GENMASK(9, 0)</div><div class='add'>+#define BMI323_STEP_SC1_RST_CNT_MSK		BIT(10)</div><div class='add'>+#define BMI323_STEP_SC1_REG			0x10</div><div class='add'>+#define BMI323_STEP_LEN				2</div><div class='add'>+</div><div class='add'>+/* Tap gesture config registers */</div><div class='add'>+#define BMI323_TAP1_REG				0x1E</div><div class='add'>+#define BMI323_TAP1_AXIS_SEL_MSK		GENMASK(1, 0)</div><div class='add'>+#define BMI323_AXIS_XYZ_MSK			GENMASK(1, 0)</div><div class='add'>+#define BMI323_TAP1_TIMOUT_MSK			BIT(2)</div><div class='add'>+#define BMI323_TAP1_MAX_PEAKS_MSK		GENMASK(5, 3)</div><div class='add'>+#define BMI323_TAP1_MODE_MSK			GENMASK(7, 6)</div><div class='add'>+#define BMI323_TAP2_REG				0x1F</div><div class='add'>+#define BMI323_TAP2_THRES_MSK			GENMASK(9, 0)</div><div class='add'>+#define BMI323_TAP2_MAX_DUR_MSK			GENMASK(15, 10)</div><div class='add'>+#define BMI323_TAP3_REG				0x20</div><div class='add'>+#define BMI323_TAP3_QUIET_TIM_MSK		GENMASK(15, 12)</div><div class='add'>+#define BMI323_TAP3_QT_BW_TAP_MSK		GENMASK(11, 8)</div><div class='add'>+#define BMI323_TAP3_QT_AFT_GES_MSK		GENMASK(15, 12)</div><div class='add'>+</div><div class='add'>+#define BMI323_MOTION_THRES_SCALE		512</div><div class='add'>+#define BMI323_MOTION_HYSTR_SCALE		512</div><div class='add'>+#define BMI323_MOTION_DURAT_SCALE		50</div><div class='add'>+#define BMI323_TAP_THRES_SCALE			512</div><div class='add'>+#define BMI323_DUR_BW_TAP_SCALE			200</div><div class='add'>+#define BMI323_QUITE_TIM_GES_SCALE		25</div><div class='add'>+#define BMI323_MAX_GES_DUR_SCALE		25</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The formula to calculate temperature in C.</div><div class='add'>+ * See datasheet section 6.1.1, Register Map Overview</div><div class='add'>+ *</div><div class='add'>+ * T_C = (temp_raw / 512) + 23</div><div class='add'>+ */</div><div class='add'>+#define BMI323_TEMP_OFFSET			11776</div><div class='add'>+#define BMI323_TEMP_SCALE			1953125</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The BMI323 features a FIFO with a capacity of 2048 bytes. Each frame</div><div class='add'>+ * consists of accelerometer (X, Y, Z) data and gyroscope (X, Y, Z) data,</div><div class='add'>+ * totaling 6 words or 12 bytes. The FIFO buffer can hold a total of</div><div class='add'>+ * 170 frames.</div><div class='add'>+ *</div><div class='add'>+ * If a watermark interrupt is configured for 170 frames, the interrupt will</div><div class='add'>+ * trigger when the FIFO reaches 169 frames, so limit the maximum watermark</div><div class='add'>+ * level to 169 frames. In terms of data, 169 frames would equal 1014 bytes,</div><div class='add'>+ * which is approximately 2 frames before the FIFO reaches its full capacity.</div><div class='add'>+ * See datasheet section 5.7.3 FIFO Buffer Interrupts</div><div class='add'>+ */</div><div class='add'>+#define BMI323_BYTES_PER_SAMPLE			2</div><div class='add'>+#define BMI323_FIFO_LENGTH_IN_BYTES		2048</div><div class='add'>+#define BMI323_FIFO_FRAME_LENGTH		6</div><div class='add'>+#define BMI323_FIFO_FULL_IN_FRAMES		\</div><div class='add'>+	((BMI323_FIFO_LENGTH_IN_BYTES /		\</div><div class='add'>+	(BMI323_BYTES_PER_SAMPLE * BMI323_FIFO_FRAME_LENGTH)) - 1)</div><div class='add'>+#define BMI323_FIFO_FULL_IN_WORDS		\</div><div class='add'>+	(BMI323_FIFO_FULL_IN_FRAMES * BMI323_FIFO_FRAME_LENGTH)</div><div class='add'>+</div><div class='add'>+#define BMI323_INT_MICRO_TO_RAW(val, val2, scale) ((val) * (scale) + \</div><div class='add'>+						  ((val2) * (scale)) / MEGA)</div><div class='add'>+</div><div class='add'>+#define BMI323_RAW_TO_MICRO(raw, scale) ((((raw) % (scale)) * MEGA) / scale)</div><div class='add'>+</div><div class='add'>+struct device;</div><div class='add'>+int bmi323_core_probe(struct device *dev);</div><div class='add'>+extern const struct regmap_config bmi323_regmap_config;</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/iio/imu/bmi323/bmi323_core.c b/drivers/iio/imu/bmi323/bmi323_core.c<br/>new file mode 100644<br/>index 000000000000..183af482828f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/bmi323_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_core.c</a></div><div class='hunk'>@@ -0,0 +1,2139 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * IIO core driver for Bosch BMI323 6-Axis IMU.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023, Jagath Jog J &lt;jagathjog1996@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi323-ds000.pdf</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/minmax.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/buffer.h&gt;</div><div class='add'>+#include &lt;linux/iio/events.h&gt;</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+#include &lt;linux/iio/sysfs.h&gt;</div><div class='add'>+#include &lt;linux/iio/trigger.h&gt;</div><div class='add'>+#include &lt;linux/iio/trigger_consumer.h&gt;</div><div class='add'>+#include &lt;linux/iio/triggered_buffer.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bmi323.h"</div><div class='add'>+</div><div class='add'>+enum bmi323_sensor_type {</div><div class='add'>+	BMI323_ACCEL,</div><div class='add'>+	BMI323_GYRO,</div><div class='add'>+	BMI323_SENSORS_CNT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bmi323_opr_mode {</div><div class='add'>+	ACC_GYRO_MODE_DISABLE = 0x00,</div><div class='add'>+	GYRO_DRIVE_MODE_ENABLED = 0x01,</div><div class='add'>+	ACC_GYRO_MODE_DUTYCYCLE = 0x03,</div><div class='add'>+	ACC_GYRO_MODE_CONTINOUS = 0x04,</div><div class='add'>+	ACC_GYRO_MODE_HIGH_PERF = 0x07,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bmi323_state {</div><div class='add'>+	BMI323_IDLE,</div><div class='add'>+	BMI323_BUFFER_DRDY_TRIGGERED,</div><div class='add'>+	BMI323_BUFFER_FIFO,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bmi323_irq_pin {</div><div class='add'>+	BMI323_IRQ_DISABLED,</div><div class='add'>+	BMI323_IRQ_INT1,</div><div class='add'>+	BMI323_IRQ_INT2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bmi323_3db_bw {</div><div class='add'>+	BMI323_BW_ODR_BY_2,</div><div class='add'>+	BMI323_BW_ODR_BY_4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bmi323_scan {</div><div class='add'>+	BMI323_ACCEL_X,</div><div class='add'>+	BMI323_ACCEL_Y,</div><div class='add'>+	BMI323_ACCEL_Z,</div><div class='add'>+	BMI323_GYRO_X,</div><div class='add'>+	BMI323_GYRO_Y,</div><div class='add'>+	BMI323_GYRO_Z,</div><div class='add'>+	BMI323_CHAN_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bmi323_hw {</div><div class='add'>+	u8 data;</div><div class='add'>+	u8 config;</div><div class='add'>+	const int (*scale_table)[2];</div><div class='add'>+	int scale_table_len;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The accelerometer supports +-2G/4G/8G/16G ranges, and the resolution of</div><div class='add'>+ * each sample is 16 bits, signed.</div><div class='add'>+ * At +-8G the scale can calculated by</div><div class='add'>+ * ((8 + 8) * 9.80665 / (2^16 - 1)) * 10^6 = 2394.23819 scale in micro</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static const int bmi323_accel_scale[][2] = {</div><div class='add'>+	{ 0, 598 },</div><div class='add'>+	{ 0, 1197 },</div><div class='add'>+	{ 0, 2394 },</div><div class='add'>+	{ 0, 4788 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int bmi323_gyro_scale[][2] = {</div><div class='add'>+	{ 0, 66 },</div><div class='add'>+	{ 0, 133 },</div><div class='add'>+	{ 0, 266 },</div><div class='add'>+	{ 0, 532 },</div><div class='add'>+	{ 0, 1065 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int bmi323_accel_gyro_avrg[] = {0, 2, 4, 8, 16, 32, 64};</div><div class='add'>+</div><div class='add'>+static const struct bmi323_hw bmi323_hw[2] = {</div><div class='add'>+	[BMI323_ACCEL] = {</div><div class='add'>+		.data = BMI323_ACCEL_X_REG,</div><div class='add'>+		.config = BMI323_ACC_CONF_REG,</div><div class='add'>+		.scale_table = bmi323_accel_scale,</div><div class='add'>+		.scale_table_len = ARRAY_SIZE(bmi323_accel_scale),</div><div class='add'>+	},</div><div class='add'>+	[BMI323_GYRO] = {</div><div class='add'>+		.data = BMI323_GYRO_X_REG,</div><div class='add'>+		.config = BMI323_GYRO_CONF_REG,</div><div class='add'>+		.scale_table = bmi323_gyro_scale,</div><div class='add'>+		.scale_table_len = ARRAY_SIZE(bmi323_gyro_scale),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bmi323_data {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct iio_mount_matrix orientation;</div><div class='add'>+	enum bmi323_irq_pin irq_pin;</div><div class='add'>+	struct iio_trigger *trig;</div><div class='add'>+	bool drdy_trigger_enabled;</div><div class='add'>+	enum bmi323_state state;</div><div class='add'>+	s64 fifo_tstamp, old_fifo_tstamp;</div><div class='add'>+	u32 odrns[BMI323_SENSORS_CNT];</div><div class='add'>+	u32 odrhz[BMI323_SENSORS_CNT];</div><div class='add'>+	unsigned int feature_events;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Lock to protect the members of device's private data from concurrent</div><div class='add'>+	 * access and also to serialize the access of extended registers.</div><div class='add'>+	 * See bmi323_write_ext_reg(..) for more info.</div><div class='add'>+	 */</div><div class='add'>+	struct mutex mutex;</div><div class='add'>+	int watermark;</div><div class='add'>+	__le16 fifo_buff[BMI323_FIFO_FULL_IN_WORDS] __aligned(IIO_DMA_MINALIGN);</div><div class='add'>+	struct {</div><div class='add'>+		__le16 channels[BMI323_CHAN_MAX];</div><div class='add'>+		s64 ts __aligned(8);</div><div class='add'>+	} buffer;</div><div class='add'>+	__le16 steps_count[BMI323_STEP_LEN];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_mount_matrix *</div><div class='add'>+bmi323_get_mount_matrix(const struct iio_dev *idev,</div><div class='add'>+			const struct iio_chan_spec *chan)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(idev);</div><div class='add'>+</div><div class='add'>+	return &amp;data-&gt;orientation;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec_ext_info bmi323_ext_info[] = {</div><div class='add'>+	IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, bmi323_get_mount_matrix),</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_event_spec bmi323_step_wtrmrk_event = {</div><div class='add'>+	.type = IIO_EV_TYPE_CHANGE,</div><div class='add'>+	.dir = IIO_EV_DIR_NONE,</div><div class='add'>+	.mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |</div><div class='add'>+			       BIT(IIO_EV_INFO_VALUE),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_event_spec bmi323_accel_event[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_MAG,</div><div class='add'>+		.dir = IIO_EV_DIR_FALLING,</div><div class='add'>+		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_PERIOD) |</div><div class='add'>+				       BIT(IIO_EV_INFO_HYSTERESIS) |</div><div class='add'>+				       BIT(IIO_EV_INFO_ENABLE),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_MAG,</div><div class='add'>+		.dir = IIO_EV_DIR_RISING,</div><div class='add'>+		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_PERIOD) |</div><div class='add'>+				       BIT(IIO_EV_INFO_HYSTERESIS) |</div><div class='add'>+				       BIT(IIO_EV_INFO_ENABLE),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_GESTURE,</div><div class='add'>+		.dir = IIO_EV_DIR_SINGLETAP,</div><div class='add'>+		.mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_RESET_TIMEOUT),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_EV_TYPE_GESTURE,</div><div class='add'>+		.dir = IIO_EV_DIR_DOUBLETAP,</div><div class='add'>+		.mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_VALUE) |</div><div class='add'>+				       BIT(IIO_EV_INFO_RESET_TIMEOUT) |</div><div class='add'>+				       BIT(IIO_EV_INFO_TAP2_MIN_DELAY),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define BMI323_ACCEL_CHANNEL(_type, _axis, _index) {			\</div><div class='add'>+	.type = _type,							\</div><div class='add'>+	.modified = 1,							\</div><div class='add'>+	.channel2 = IIO_MOD_##_axis,					\</div><div class='add'>+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\</div><div class='add'>+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SCALE) |		\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \</div><div class='add'>+	.info_mask_shared_by_type_available =				\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SCALE) |		\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \</div><div class='add'>+	.scan_index = _index,						\</div><div class='add'>+	.scan_type = {							\</div><div class='add'>+		.sign = 's',						\</div><div class='add'>+		.realbits = 16,						\</div><div class='add'>+		.storagebits = 16,					\</div><div class='add'>+		.endianness = IIO_LE,					\</div><div class='add'>+	},								\</div><div class='add'>+	.ext_info = bmi323_ext_info,					\</div><div class='add'>+	.event_spec = bmi323_accel_event,				\</div><div class='add'>+	.num_event_specs = ARRAY_SIZE(bmi323_accel_event),		\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define BMI323_GYRO_CHANNEL(_type, _axis, _index) {			\</div><div class='add'>+	.type = _type,							\</div><div class='add'>+	.modified = 1,							\</div><div class='add'>+	.channel2 = IIO_MOD_##_axis,					\</div><div class='add'>+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\</div><div class='add'>+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SCALE) |		\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \</div><div class='add'>+	.info_mask_shared_by_type_available =				\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_SCALE) |		\</div><div class='add'>+				    BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \</div><div class='add'>+	.scan_index = _index,						\</div><div class='add'>+	.scan_type = {							\</div><div class='add'>+		.sign = 's',						\</div><div class='add'>+		.realbits = 16,						\</div><div class='add'>+		.storagebits = 16,					\</div><div class='add'>+		.endianness = IIO_LE,					\</div><div class='add'>+	},								\</div><div class='add'>+	.ext_info = bmi323_ext_info,					\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec bmi323_channels[] = {</div><div class='add'>+	BMI323_ACCEL_CHANNEL(IIO_ACCEL, X, BMI323_ACCEL_X),</div><div class='add'>+	BMI323_ACCEL_CHANNEL(IIO_ACCEL, Y, BMI323_ACCEL_Y),</div><div class='add'>+	BMI323_ACCEL_CHANNEL(IIO_ACCEL, Z, BMI323_ACCEL_Z),</div><div class='add'>+	BMI323_GYRO_CHANNEL(IIO_ANGL_VEL, X, BMI323_GYRO_X),</div><div class='add'>+	BMI323_GYRO_CHANNEL(IIO_ANGL_VEL, Y, BMI323_GYRO_Y),</div><div class='add'>+	BMI323_GYRO_CHANNEL(IIO_ANGL_VEL, Z, BMI323_GYRO_Z),</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_OFFSET) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.scan_index = -1,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_STEPS,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_ENABLE),</div><div class='add'>+		.scan_index = -1,</div><div class='add'>+		.event_spec = &amp;bmi323_step_wtrmrk_event,</div><div class='add'>+		.num_event_specs = 1,</div><div class='add'>+</div><div class='add'>+	},</div><div class='add'>+	IIO_CHAN_SOFT_TIMESTAMP(BMI323_CHAN_MAX),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int bmi323_acc_gyro_odr[][2] = {</div><div class='add'>+	{ 0, 781250 },</div><div class='add'>+	{ 1, 562500 },</div><div class='add'>+	{ 3, 125000 },</div><div class='add'>+	{ 6, 250000 },</div><div class='add'>+	{ 12, 500000 },</div><div class='add'>+	{ 25, 0 },</div><div class='add'>+	{ 50, 0 },</div><div class='add'>+	{ 100, 0 },</div><div class='add'>+	{ 200, 0 },</div><div class='add'>+	{ 400, 0 },</div><div class='add'>+	{ 800, 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int bmi323_acc_gyro_odrns[] = {</div><div class='add'>+	1280 * MEGA,</div><div class='add'>+	640 * MEGA,</div><div class='add'>+	320 * MEGA,</div><div class='add'>+	160 * MEGA,</div><div class='add'>+	80 * MEGA,</div><div class='add'>+	40 * MEGA,</div><div class='add'>+	20 * MEGA,</div><div class='add'>+	10 * MEGA,</div><div class='add'>+	5 * MEGA,</div><div class='add'>+	2500 * KILO,</div><div class='add'>+	1250 * KILO,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static enum bmi323_sensor_type bmi323_iio_to_sensor(enum iio_chan_type iio_type)</div><div class='add'>+{</div><div class='add'>+	switch (iio_type) {</div><div class='add'>+	case IIO_ACCEL:</div><div class='add'>+		return BMI323_ACCEL;</div><div class='add'>+	case IIO_ANGL_VEL:</div><div class='add'>+		return BMI323_GYRO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_mode(struct bmi323_data *data,</div><div class='add'>+			   enum bmi323_sensor_type sensor,</div><div class='add'>+			   enum bmi323_opr_mode mode)</div><div class='add'>+{</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				  BMI323_ACC_GYRO_CONF_MODE_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_ACC_GYRO_CONF_MODE_MSK,</div><div class='add'>+					     mode));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * When writing data to extended register there must be no communication to</div><div class='add'>+ * any other register before write transaction is complete.</div><div class='add'>+ * See datasheet section 6.2 Extended Register Map Description.</div><div class='add'>+ */</div><div class='add'>+static int bmi323_write_ext_reg(struct bmi323_data *data, unsigned int ext_addr,</div><div class='add'>+				unsigned int ext_data)</div><div class='add'>+{</div><div class='add'>+	int ret, feature_status;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_FEAT_DATA_STATUS,</div><div class='add'>+			  &amp;feature_status);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!FIELD_GET(BMI323_FEAT_DATA_TX_RDY_MSK, feature_status))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_DATA_ADDR, ext_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_write(data-&gt;regmap, BMI323_FEAT_DATA_TX, ext_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * When reading data from extended register there must be no communication to</div><div class='add'>+ * any other register before read transaction is complete.</div><div class='add'>+ * See datasheet section 6.2 Extended Register Map Description.</div><div class='add'>+ */</div><div class='add'>+static int bmi323_read_ext_reg(struct bmi323_data *data, unsigned int ext_addr,</div><div class='add'>+			       unsigned int *ext_data)</div><div class='add'>+{</div><div class='add'>+	int ret, feature_status;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_FEAT_DATA_STATUS,</div><div class='add'>+			  &amp;feature_status);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!FIELD_GET(BMI323_FEAT_DATA_TX_RDY_MSK, feature_status))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_DATA_ADDR, ext_addr);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_read(data-&gt;regmap, BMI323_FEAT_DATA_TX, ext_data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_update_ext_reg(struct bmi323_data *data,</div><div class='add'>+				 unsigned int ext_addr,</div><div class='add'>+				 unsigned int mask, unsigned int ext_data)</div><div class='add'>+{</div><div class='add'>+	unsigned int value;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_read_ext_reg(data, ext_addr, &amp;value);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	set_mask_bits(&amp;value, mask, ext_data);</div><div class='add'>+</div><div class='add'>+	return bmi323_write_ext_reg(data, ext_addr, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_get_error_status(struct bmi323_data *data)</div><div class='add'>+{</div><div class='add'>+	int error, ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_ERR_REG, &amp;error);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (error)</div><div class='add'>+		dev_err(data-&gt;dev, "Sensor error 0x%x\n", error);</div><div class='add'>+</div><div class='add'>+	return error;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_feature_engine_events(struct bmi323_data *data,</div><div class='add'>+					const unsigned int event_mask,</div><div class='add'>+					bool state)</div><div class='add'>+{</div><div class='add'>+	unsigned int value;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_FEAT_IO0_REG, &amp;value);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Register must be cleared before changing an active config */</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_IO0_REG, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (state)</div><div class='add'>+		value |= event_mask;</div><div class='add'>+	else</div><div class='add'>+		value &amp;= ~event_mask;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_IO0_REG, value);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_write(data-&gt;regmap, BMI323_FEAT_IO_STATUS_REG,</div><div class='add'>+			    BMI323_FEAT_IO_STATUS_MSK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_step_wtrmrk_en(struct bmi323_data *data, int state)</div><div class='add'>+{</div><div class='add'>+	enum bmi323_irq_pin step_irq;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	if (!FIELD_GET(BMI323_FEAT_IO0_STP_CNT_MSK, data-&gt;feature_events))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (state)</div><div class='add'>+		step_irq = data-&gt;irq_pin;</div><div class='add'>+	else</div><div class='add'>+		step_irq = BMI323_IRQ_DISABLED;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_STEP_SC1_REG,</div><div class='add'>+				    BMI323_STEP_SC1_WTRMRK_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_STEP_SC1_WTRMRK_MSK,</div><div class='add'>+					       state ? 1 : 0));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP1_REG,</div><div class='add'>+				  BMI323_STEP_CNT_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_STEP_CNT_MSK, step_irq));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_motion_config_reg(enum iio_event_direction dir)</div><div class='add'>+{</div><div class='add'>+	switch (dir) {</div><div class='add'>+	case IIO_EV_DIR_RISING:</div><div class='add'>+		return BMI323_ANYMO1_REG;</div><div class='add'>+	case IIO_EV_DIR_FALLING:</div><div class='add'>+		return BMI323_NOMO1_REG;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_motion_event_en(struct bmi323_data *data,</div><div class='add'>+				  enum iio_event_direction dir, int state)</div><div class='add'>+{</div><div class='add'>+	unsigned int state_value = state ? BMI323_FEAT_XYZ_MSK : 0;</div><div class='add'>+	int config, ret, msk, raw, field_value;</div><div class='add'>+	enum bmi323_irq_pin motion_irq;</div><div class='add'>+	int irq_msk, irq_field_val;</div><div class='add'>+</div><div class='add'>+	if (state)</div><div class='add'>+		motion_irq = data-&gt;irq_pin;</div><div class='add'>+	else</div><div class='add'>+		motion_irq = BMI323_IRQ_DISABLED;</div><div class='add'>+</div><div class='add'>+	switch (dir) {</div><div class='add'>+	case IIO_EV_DIR_RISING:</div><div class='add'>+		msk = BMI323_FEAT_IO0_XYZ_MOTION_MSK;</div><div class='add'>+		raw = 512;</div><div class='add'>+		config = BMI323_ANYMO1_REG;</div><div class='add'>+		irq_msk = BMI323_MOTION_MSK;</div><div class='add'>+		irq_field_val = FIELD_PREP(BMI323_MOTION_MSK, motion_irq);</div><div class='add'>+		field_value = FIELD_PREP(BMI323_FEAT_IO0_XYZ_MOTION_MSK,</div><div class='add'>+					 state_value);</div><div class='add'>+		break;</div><div class='add'>+	case IIO_EV_DIR_FALLING:</div><div class='add'>+		msk = BMI323_FEAT_IO0_XYZ_NOMOTION_MSK;</div><div class='add'>+		raw = 0;</div><div class='add'>+		config = BMI323_NOMO1_REG;</div><div class='add'>+		irq_msk = BMI323_NOMOTION_MSK;</div><div class='add'>+		irq_field_val = FIELD_PREP(BMI323_NOMOTION_MSK, motion_irq);</div><div class='add'>+		field_value = FIELD_PREP(BMI323_FEAT_IO0_XYZ_NOMOTION_MSK,</div><div class='add'>+					 state_value);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = bmi323_feature_engine_events(data, msk, state);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_ext_reg(data, config,</div><div class='add'>+				    BMI323_MO1_REF_UP_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_MO1_REF_UP_MSK, 0));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Set initial value to avoid interrupts while enabling*/</div><div class='add'>+	ret = bmi323_update_ext_reg(data, config,</div><div class='add'>+				    BMI323_MO1_SLOPE_TH_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_MO1_SLOPE_TH_MSK, raw));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP1_REG, irq_msk,</div><div class='add'>+				 irq_field_val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	set_mask_bits(&amp;data-&gt;feature_events, msk, field_value);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_tap_event_en(struct bmi323_data *data,</div><div class='add'>+			       enum iio_event_direction dir, int state)</div><div class='add'>+{</div><div class='add'>+	enum bmi323_irq_pin tap_irq;</div><div class='add'>+	int ret, tap_enabled;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (data-&gt;odrhz[BMI323_ACCEL] &lt; 200) {</div><div class='add'>+		dev_err(data-&gt;dev, "Invalid accelerometer parameter\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (dir) {</div><div class='add'>+	case IIO_EV_DIR_SINGLETAP:</div><div class='add'>+		ret = bmi323_feature_engine_events(data,</div><div class='add'>+						   BMI323_FEAT_IO0_S_TAP_MSK,</div><div class='add'>+						   state);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		set_mask_bits(&amp;data-&gt;feature_events, BMI323_FEAT_IO0_S_TAP_MSK,</div><div class='add'>+			      FIELD_PREP(BMI323_FEAT_IO0_S_TAP_MSK, state));</div><div class='add'>+		break;</div><div class='add'>+	case IIO_EV_DIR_DOUBLETAP:</div><div class='add'>+		ret = bmi323_feature_engine_events(data,</div><div class='add'>+						   BMI323_FEAT_IO0_D_TAP_MSK,</div><div class='add'>+						   state);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		set_mask_bits(&amp;data-&gt;feature_events, BMI323_FEAT_IO0_D_TAP_MSK,</div><div class='add'>+			      FIELD_PREP(BMI323_FEAT_IO0_D_TAP_MSK, state));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tap_enabled = FIELD_GET(BMI323_FEAT_IO0_S_TAP_MSK |</div><div class='add'>+				BMI323_FEAT_IO0_D_TAP_MSK,</div><div class='add'>+				data-&gt;feature_events);</div><div class='add'>+</div><div class='add'>+	if (tap_enabled)</div><div class='add'>+		tap_irq = data-&gt;irq_pin;</div><div class='add'>+	else</div><div class='add'>+		tap_irq = BMI323_IRQ_DISABLED;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP2_REG,</div><div class='add'>+				 BMI323_TAP_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_TAP_MSK, tap_irq));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!state)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_TAP1_REG,</div><div class='add'>+				    BMI323_TAP1_MAX_PEAKS_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_TAP1_MAX_PEAKS_MSK,</div><div class='add'>+					       0x04));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_TAP1_REG,</div><div class='add'>+				    BMI323_TAP1_AXIS_SEL_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_TAP1_AXIS_SEL_MSK,</div><div class='add'>+					       BMI323_AXIS_XYZ_MSK));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return bmi323_update_ext_reg(data, BMI323_TAP1_REG,</div><div class='add'>+				     BMI323_TAP1_TIMOUT_MSK,</div><div class='add'>+				     FIELD_PREP(BMI323_TAP1_TIMOUT_MSK,</div><div class='add'>+						0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t in_accel_gesture_tap_wait_dur_show(struct device *dev,</div><div class='add'>+						  struct device_attribute *attr,</div><div class='add'>+						  char *buf)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	unsigned int reg_value, raw;</div><div class='add'>+	int ret, val[2];</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = bmi323_read_ext_reg(data, BMI323_TAP2_REG, &amp;reg_value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	raw = FIELD_GET(BMI323_TAP2_MAX_DUR_MSK, reg_value);</div><div class='add'>+	val[0] = raw / BMI323_MAX_GES_DUR_SCALE;</div><div class='add'>+	val[1] = BMI323_RAW_TO_MICRO(raw, BMI323_MAX_GES_DUR_SCALE);</div><div class='add'>+</div><div class='add'>+	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(val),</div><div class='add'>+				val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t in_accel_gesture_tap_wait_dur_store(struct device *dev,</div><div class='add'>+						   struct device_attribute *attr,</div><div class='add'>+						   const char *buf, size_t len)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret, val_int, val_fract, raw;</div><div class='add'>+</div><div class='add'>+	ret = iio_str_to_fixpoint(buf, 100000, &amp;val_int, &amp;val_fract);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	raw = BMI323_INT_MICRO_TO_RAW(val_int, val_fract,</div><div class='add'>+				      BMI323_MAX_GES_DUR_SCALE);</div><div class='add'>+	if (!in_range(raw, 0, 64))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_TAP2_REG,</div><div class='add'>+				    BMI323_TAP2_MAX_DUR_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_TAP2_MAX_DUR_MSK, raw));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Maximum duration from first tap within the second tap is expected to happen.</div><div class='add'>+ * This timeout is applicable only if gesture_tap_wait_timeout is enabled.</div><div class='add'>+ */</div><div class='add'>+static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_wait_dur, 0);</div><div class='add'>+</div><div class='add'>+static ssize_t in_accel_gesture_tap_wait_timeout_show(struct device *dev,</div><div class='add'>+						      struct device_attribute *attr,</div><div class='add'>+						      char *buf)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	unsigned int reg_value, raw;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = bmi323_read_ext_reg(data, BMI323_TAP1_REG, &amp;reg_value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	raw = FIELD_GET(BMI323_TAP1_TIMOUT_MSK, reg_value);</div><div class='add'>+</div><div class='add'>+	return iio_format_value(buf, IIO_VAL_INT, 1, &amp;raw);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t in_accel_gesture_tap_wait_timeout_store(struct device *dev,</div><div class='add'>+						       struct device_attribute *attr,</div><div class='add'>+						       const char *buf,</div><div class='add'>+						       size_t len)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	bool val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtobool(buf, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_TAP1_REG,</div><div class='add'>+				    BMI323_TAP1_TIMOUT_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_TAP1_TIMOUT_MSK, val));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable/disable gesture confirmation with wait time */</div><div class='add'>+static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_wait_timeout, 0);</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_gesture_tap_wait_dur_available,</div><div class='add'>+		      "[0.0 0.04 2.52]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available,</div><div class='add'>+		      "[0.005 0.005 0.075]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available,</div><div class='add'>+		      "[0.04 0.04 0.6]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_gesture_tap_value_available, "[0.0 0.002 1.99]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_mag_value_available, "[0.0 0.002 7.99]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_mag_period_available, "[0.0 0.02 162.0]");</div><div class='add'>+</div><div class='add'>+static IIO_CONST_ATTR(in_accel_mag_hysteresis_available, "[0.0 0.002 1.99]");</div><div class='add'>+</div><div class='add'>+static struct attribute *bmi323_event_attributes[] = {</div><div class='add'>+	&amp;iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_gesture_tap_wait_dur_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_dev_attr_in_accel_gesture_tap_wait_timeout.dev_attr.attr,</div><div class='add'>+	&amp;iio_dev_attr_in_accel_gesture_tap_wait_dur.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_mag_value_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_mag_period_available.dev_attr.attr,</div><div class='add'>+	&amp;iio_const_attr_in_accel_mag_hysteresis_available.dev_attr.attr,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct attribute_group bmi323_event_attribute_group = {</div><div class='add'>+	.attrs = bmi323_event_attributes,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int bmi323_write_event_config(struct iio_dev *indio_dev,</div><div class='add'>+				     const struct iio_chan_spec *chan,</div><div class='add'>+				     enum iio_event_type type,</div><div class='add'>+				     enum iio_event_direction dir, int state)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case IIO_EV_TYPE_MAG:</div><div class='add'>+		return bmi323_motion_event_en(data, dir, state);</div><div class='add'>+	case IIO_EV_TYPE_GESTURE:</div><div class='add'>+		return bmi323_tap_event_en(data, dir, state);</div><div class='add'>+	case IIO_EV_TYPE_CHANGE:</div><div class='add'>+		return bmi323_step_wtrmrk_en(data, state);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_event_config(struct iio_dev *indio_dev,</div><div class='add'>+				    const struct iio_chan_spec *chan,</div><div class='add'>+				    enum iio_event_type type,</div><div class='add'>+				    enum iio_event_direction dir)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret, value, reg_val;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	switch (chan-&gt;type) {</div><div class='add'>+	case IIO_ACCEL:</div><div class='add'>+		switch (dir) {</div><div class='add'>+		case IIO_EV_DIR_SINGLETAP:</div><div class='add'>+			ret = FIELD_GET(BMI323_FEAT_IO0_S_TAP_MSK,</div><div class='add'>+					data-&gt;feature_events);</div><div class='add'>+			break;</div><div class='add'>+		case IIO_EV_DIR_DOUBLETAP:</div><div class='add'>+			ret = FIELD_GET(BMI323_FEAT_IO0_D_TAP_MSK,</div><div class='add'>+					data-&gt;feature_events);</div><div class='add'>+			break;</div><div class='add'>+		case IIO_EV_DIR_RISING:</div><div class='add'>+			value = FIELD_GET(BMI323_FEAT_IO0_XYZ_MOTION_MSK,</div><div class='add'>+					  data-&gt;feature_events);</div><div class='add'>+			ret = value ? 1 : 0;</div><div class='add'>+			break;</div><div class='add'>+		case IIO_EV_DIR_FALLING:</div><div class='add'>+			value = FIELD_GET(BMI323_FEAT_IO0_XYZ_NOMOTION_MSK,</div><div class='add'>+					  data-&gt;feature_events);</div><div class='add'>+			ret = value ? 1 : 0;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		return ret;</div><div class='add'>+	case IIO_STEPS:</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, BMI323_INT_MAP1_REG, &amp;reg_val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		return FIELD_GET(BMI323_STEP_CNT_MSK, reg_val) ? 1 : 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_write_event_value(struct iio_dev *indio_dev,</div><div class='add'>+				    const struct iio_chan_spec *chan,</div><div class='add'>+				    enum iio_event_type type,</div><div class='add'>+				    enum iio_event_direction dir,</div><div class='add'>+				    enum iio_event_info info,</div><div class='add'>+				    int val, int val2)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	unsigned int raw;</div><div class='add'>+	int reg;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case IIO_EV_TYPE_GESTURE:</div><div class='add'>+		switch (info) {</div><div class='add'>+		case IIO_EV_INFO_VALUE:</div><div class='add'>+			if (!in_range(val, 0, 2))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_TAP_THRES_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data, BMI323_TAP2_REG,</div><div class='add'>+						     BMI323_TAP2_THRES_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_TAP2_THRES_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		case IIO_EV_INFO_RESET_TIMEOUT:</div><div class='add'>+			if (val || !in_range(val2, 40000, 560001))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_QUITE_TIM_GES_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data, BMI323_TAP3_REG,</div><div class='add'>+						     BMI323_TAP3_QT_AFT_GES_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_TAP3_QT_AFT_GES_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		case IIO_EV_INFO_TAP2_MIN_DELAY:</div><div class='add'>+			if (val || !in_range(val2, 5000, 70001))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_DUR_BW_TAP_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data, BMI323_TAP3_REG,</div><div class='add'>+						     BMI323_TAP3_QT_BW_TAP_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_TAP3_QT_BW_TAP_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_TYPE_MAG:</div><div class='add'>+		reg = bmi323_motion_config_reg(dir);</div><div class='add'>+		if (reg &lt; 0)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		switch (info) {</div><div class='add'>+		case IIO_EV_INFO_VALUE:</div><div class='add'>+			if (!in_range(val, 0, 8))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_MOTION_THRES_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data, reg,</div><div class='add'>+						     BMI323_MO1_SLOPE_TH_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_MO1_SLOPE_TH_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		case IIO_EV_INFO_PERIOD:</div><div class='add'>+			if (!in_range(val, 0, 163))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_MOTION_DURAT_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data,</div><div class='add'>+						     reg + BMI323_MO3_OFFSET,</div><div class='add'>+						     BMI323_MO3_DURA_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_MO3_DURA_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		case IIO_EV_INFO_HYSTERESIS:</div><div class='add'>+			if (!in_range(val, 0, 2))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			raw = BMI323_INT_MICRO_TO_RAW(val, val2,</div><div class='add'>+						      BMI323_MOTION_HYSTR_SCALE);</div><div class='add'>+</div><div class='add'>+			return bmi323_update_ext_reg(data,</div><div class='add'>+						     reg + BMI323_MO2_OFFSET,</div><div class='add'>+						     BMI323_MO2_HYSTR_MSK,</div><div class='add'>+						     FIELD_PREP(BMI323_MO2_HYSTR_MSK,</div><div class='add'>+								raw));</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_TYPE_CHANGE:</div><div class='add'>+		if (!in_range(val, 0, 20461))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		raw = val / 20;</div><div class='add'>+		return bmi323_update_ext_reg(data, BMI323_STEP_SC1_REG,</div><div class='add'>+					     BMI323_STEP_SC1_WTRMRK_MSK,</div><div class='add'>+					     FIELD_PREP(BMI323_STEP_SC1_WTRMRK_MSK,</div><div class='add'>+							raw));</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_event_value(struct iio_dev *indio_dev,</div><div class='add'>+				   const struct iio_chan_spec *chan,</div><div class='add'>+				   enum iio_event_type type,</div><div class='add'>+				   enum iio_event_direction dir,</div><div class='add'>+				   enum iio_event_info info,</div><div class='add'>+				   int *val, int *val2)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	unsigned int raw, reg_value;</div><div class='add'>+	int ret, reg;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	switch (type) {</div><div class='add'>+	case IIO_EV_TYPE_GESTURE:</div><div class='add'>+		switch (info) {</div><div class='add'>+		case IIO_EV_INFO_VALUE:</div><div class='add'>+			ret = bmi323_read_ext_reg(data, BMI323_TAP2_REG,</div><div class='add'>+						  &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_TAP2_THRES_MSK, reg_value);</div><div class='add'>+			*val = raw / BMI323_TAP_THRES_SCALE;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw, BMI323_TAP_THRES_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		case IIO_EV_INFO_RESET_TIMEOUT:</div><div class='add'>+			ret = bmi323_read_ext_reg(data, BMI323_TAP3_REG,</div><div class='add'>+						  &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_TAP3_QT_AFT_GES_MSK, reg_value);</div><div class='add'>+			*val = 0;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw,</div><div class='add'>+						    BMI323_QUITE_TIM_GES_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		case IIO_EV_INFO_TAP2_MIN_DELAY:</div><div class='add'>+			ret = bmi323_read_ext_reg(data, BMI323_TAP3_REG,</div><div class='add'>+						  &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_TAP3_QT_BW_TAP_MSK, reg_value);</div><div class='add'>+			*val = 0;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw,</div><div class='add'>+						    BMI323_DUR_BW_TAP_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_TYPE_MAG:</div><div class='add'>+		reg = bmi323_motion_config_reg(dir);</div><div class='add'>+		if (reg &lt; 0)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		switch (info) {</div><div class='add'>+		case IIO_EV_INFO_VALUE:</div><div class='add'>+			ret = bmi323_read_ext_reg(data, reg, &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_MO1_SLOPE_TH_MSK, reg_value);</div><div class='add'>+			*val = raw / BMI323_MOTION_THRES_SCALE;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw,</div><div class='add'>+						    BMI323_MOTION_THRES_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		case IIO_EV_INFO_PERIOD:</div><div class='add'>+			ret = bmi323_read_ext_reg(data,</div><div class='add'>+						  reg + BMI323_MO3_OFFSET,</div><div class='add'>+						  &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_MO3_DURA_MSK, reg_value);</div><div class='add'>+			*val = raw / BMI323_MOTION_DURAT_SCALE;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw,</div><div class='add'>+						    BMI323_MOTION_DURAT_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		case IIO_EV_INFO_HYSTERESIS:</div><div class='add'>+			ret = bmi323_read_ext_reg(data,</div><div class='add'>+						  reg + BMI323_MO2_OFFSET,</div><div class='add'>+						  &amp;reg_value);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			raw = FIELD_GET(BMI323_MO2_HYSTR_MSK, reg_value);</div><div class='add'>+			*val = raw / BMI323_MOTION_HYSTR_SCALE;</div><div class='add'>+			*val2 = BMI323_RAW_TO_MICRO(raw,</div><div class='add'>+						    BMI323_MOTION_HYSTR_SCALE);</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_EV_TYPE_CHANGE:</div><div class='add'>+		ret = bmi323_read_ext_reg(data, BMI323_STEP_SC1_REG,</div><div class='add'>+					  &amp;reg_value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		raw = FIELD_GET(BMI323_STEP_SC1_WTRMRK_MSK, reg_value);</div><div class='add'>+		*val = raw * 20;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __bmi323_fifo_flush(struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int i, ret, fifo_lvl, frame_count, bit, index;</div><div class='add'>+	__le16 *frame, *pchannels;</div><div class='add'>+	u64 sample_period;</div><div class='add'>+	s64 tstamp;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_FIFO_FILL_LEVEL_REG, &amp;fifo_lvl);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	fifo_lvl = min(fifo_lvl, BMI323_FIFO_FULL_IN_WORDS);</div><div class='add'>+</div><div class='add'>+	frame_count = fifo_lvl / BMI323_FIFO_FRAME_LENGTH;</div><div class='add'>+	if (!frame_count)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (fifo_lvl % BMI323_FIFO_FRAME_LENGTH)</div><div class='add'>+		dev_warn(data-&gt;dev, "Bad FIFO alignment\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Approximate timestamps for each of the sample based on the sampling</div><div class='add'>+	 * frequency, timestamp for last sample and number of samples.</div><div class='add'>+	 */</div><div class='add'>+	if (data-&gt;old_fifo_tstamp) {</div><div class='add'>+		sample_period = data-&gt;fifo_tstamp - data-&gt;old_fifo_tstamp;</div><div class='add'>+		do_div(sample_period, frame_count);</div><div class='add'>+	} else {</div><div class='add'>+		sample_period = data-&gt;odrns[BMI323_ACCEL];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tstamp = data-&gt;fifo_tstamp - (frame_count - 1) * sample_period;</div><div class='add'>+</div><div class='add'>+	ret = regmap_noinc_read(data-&gt;regmap, BMI323_FIFO_DATA_REG,</div><div class='add'>+				&amp;data-&gt;fifo_buff[0],</div><div class='add'>+				fifo_lvl * BMI323_BYTES_PER_SAMPLE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; frame_count; i++) {</div><div class='add'>+		frame = &amp;data-&gt;fifo_buff[i * BMI323_FIFO_FRAME_LENGTH];</div><div class='add'>+		pchannels = &amp;data-&gt;buffer.channels[0];</div><div class='add'>+</div><div class='add'>+		index = 0;</div><div class='add'>+		for_each_set_bit(bit, indio_dev-&gt;active_scan_mask,</div><div class='add'>+				 BMI323_CHAN_MAX)</div><div class='add'>+			pchannels[index++] = frame[bit];</div><div class='add'>+</div><div class='add'>+		iio_push_to_buffers_with_timestamp(indio_dev, &amp;data-&gt;buffer,</div><div class='add'>+						   tstamp);</div><div class='add'>+</div><div class='add'>+		tstamp += sample_period;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return frame_count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_watermark(struct iio_dev *indio_dev, unsigned int val)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	val = min(val, (u32)BMI323_FIFO_FULL_IN_FRAMES);</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	data-&gt;watermark = val;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_fifo_disable(struct bmi323_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FIFO_CONF_REG, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP2_REG,</div><div class='add'>+				 BMI323_FIFO_WTRMRK_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_FIFO_WTRMRK_MSK, 0));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;fifo_tstamp = 0;</div><div class='add'>+	data-&gt;state = BMI323_IDLE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_buffer_predisable(struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return bmi323_fifo_disable(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_update_watermark(struct bmi323_data *data)</div><div class='add'>+{</div><div class='add'>+	int wtrmrk;</div><div class='add'>+</div><div class='add'>+	wtrmrk = data-&gt;watermark * BMI323_FIFO_FRAME_LENGTH;</div><div class='add'>+</div><div class='add'>+	return regmap_write(data-&gt;regmap, BMI323_FIFO_WTRMRK_REG, wtrmrk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_fifo_enable(struct bmi323_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_FIFO_CONF_REG,</div><div class='add'>+				 BMI323_FIFO_CONF_ACC_GYR_EN_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_FIFO_CONF_ACC_GYR_EN_MSK,</div><div class='add'>+					    BMI323_FIFO_ACC_GYR_MSK));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP2_REG,</div><div class='add'>+				 BMI323_FIFO_WTRMRK_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_FIFO_WTRMRK_MSK,</div><div class='add'>+					    data-&gt;irq_pin));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_watermark(data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FIFO_CTRL_REG,</div><div class='add'>+			   BMI323_FIFO_FLUSH_MSK);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;state = BMI323_BUFFER_FIFO;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_buffer_preenable(struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	/*</div><div class='add'>+	 * When the ODR of the accelerometer and gyroscope do not match, the</div><div class='add'>+	 * maximum ODR value between the accelerometer and gyroscope is used</div><div class='add'>+	 * for FIFO and the signal with lower ODR will insert dummy frame.</div><div class='add'>+	 * So allow buffer read only when ODR's of accelero and gyro are equal.</div><div class='add'>+	 * See datasheet section 5.7 "FIFO Data Buffering".</div><div class='add'>+	 */</div><div class='add'>+	if (data-&gt;odrns[BMI323_ACCEL] != data-&gt;odrns[BMI323_GYRO]) {</div><div class='add'>+		dev_err(data-&gt;dev, "Accelero and Gyro ODR doesn't match\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_buffer_postenable(struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	if (iio_device_get_current_mode(indio_dev) == INDIO_BUFFER_TRIGGERED)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return bmi323_fifo_enable(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t hwfifo_watermark_show(struct device *dev,</div><div class='add'>+				     struct device_attribute *attr, char *buf)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int wm;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex)</div><div class='add'>+		wm = data-&gt;watermark;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", wm);</div><div class='add'>+}</div><div class='add'>+static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);</div><div class='add'>+</div><div class='add'>+static ssize_t hwfifo_enabled_show(struct device *dev,</div><div class='add'>+				   struct device_attribute *attr,</div><div class='add'>+				   char *buf)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = dev_to_iio_dev(dev);</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	bool state;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex)</div><div class='add'>+		state = data-&gt;state == BMI323_BUFFER_FIFO;</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%d\n", state);</div><div class='add'>+}</div><div class='add'>+static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);</div><div class='add'>+</div><div class='add'>+static const struct iio_dev_attr *bmi323_fifo_attributes[] = {</div><div class='add'>+	&amp;iio_dev_attr_hwfifo_watermark,</div><div class='add'>+	&amp;iio_dev_attr_hwfifo_enabled,</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_buffer_setup_ops bmi323_buffer_ops = {</div><div class='add'>+	.preenable = bmi323_buffer_preenable,</div><div class='add'>+	.postenable = bmi323_buffer_postenable,</div><div class='add'>+	.predisable = bmi323_buffer_predisable,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static irqreturn_t bmi323_irq_thread_handler(int irq, void *private)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev = private;</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	unsigned int status_addr, status, feature_event;</div><div class='add'>+	s64 timestamp = iio_get_time_ns(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;irq_pin == BMI323_IRQ_INT1)</div><div class='add'>+		status_addr = BMI323_STATUS_INT1_REG;</div><div class='add'>+	else</div><div class='add'>+		status_addr = BMI323_STATUS_INT2_REG;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, status_addr, &amp;status);</div><div class='add'>+		if (ret)</div><div class='add'>+			return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!status || FIELD_GET(BMI323_STATUS_ERROR_MSK, status))</div><div class='add'>+		return IRQ_NONE;</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_FIFO_WTRMRK_MSK, status)) {</div><div class='add'>+		data-&gt;old_fifo_tstamp = data-&gt;fifo_tstamp;</div><div class='add'>+		data-&gt;fifo_tstamp = iio_get_time_ns(indio_dev);</div><div class='add'>+		ret = __bmi323_fifo_flush(indio_dev);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return IRQ_NONE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_ACC_GYR_DRDY_MSK, status))</div><div class='add'>+		iio_trigger_poll_nested(data-&gt;trig);</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_MOTION_MSK, status))</div><div class='add'>+		iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,</div><div class='add'>+							     IIO_MOD_X_OR_Y_OR_Z,</div><div class='add'>+							     IIO_EV_TYPE_MAG,</div><div class='add'>+							     IIO_EV_DIR_RISING),</div><div class='add'>+			       timestamp);</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_NOMOTION_MSK, status))</div><div class='add'>+		iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,</div><div class='add'>+							     IIO_MOD_X_OR_Y_OR_Z,</div><div class='add'>+							     IIO_EV_TYPE_MAG,</div><div class='add'>+							     IIO_EV_DIR_FALLING),</div><div class='add'>+			       timestamp);</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_STP_WTR_MSK, status))</div><div class='add'>+		iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_STEPS, 0,</div><div class='add'>+							     IIO_NO_MOD,</div><div class='add'>+							     IIO_EV_TYPE_CHANGE,</div><div class='add'>+							     IIO_EV_DIR_NONE),</div><div class='add'>+			       timestamp);</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_STATUS_TAP_MSK, status)) {</div><div class='add'>+		scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+			ret = regmap_read(data-&gt;regmap,</div><div class='add'>+					  BMI323_FEAT_EVNT_EXT_REG,</div><div class='add'>+					  &amp;feature_event);</div><div class='add'>+			if (ret)</div><div class='add'>+				return IRQ_NONE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (FIELD_GET(BMI323_FEAT_EVNT_EXT_S_MSK, feature_event)) {</div><div class='add'>+			iio_push_event(indio_dev,</div><div class='add'>+				       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,</div><div class='add'>+							  IIO_MOD_X_OR_Y_OR_Z,</div><div class='add'>+							  IIO_EV_TYPE_GESTURE,</div><div class='add'>+							  IIO_EV_DIR_SINGLETAP),</div><div class='add'>+				       timestamp);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (FIELD_GET(BMI323_FEAT_EVNT_EXT_D_MSK, feature_event))</div><div class='add'>+			iio_push_event(indio_dev,</div><div class='add'>+				       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,</div><div class='add'>+							  IIO_MOD_X_OR_Y_OR_Z,</div><div class='add'>+							  IIO_EV_TYPE_GESTURE,</div><div class='add'>+							  IIO_EV_DIR_DOUBLETAP),</div><div class='add'>+				       timestamp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_drdy_irq(struct bmi323_data *data,</div><div class='add'>+			       enum bmi323_irq_pin irq_pin)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP2_REG,</div><div class='add'>+				 BMI323_GYR_DRDY_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_GYR_DRDY_MSK, irq_pin));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, BMI323_INT_MAP2_REG,</div><div class='add'>+				  BMI323_ACC_DRDY_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_ACC_DRDY_MSK, irq_pin));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_data_rdy_trigger_set_state(struct iio_trigger *trig,</div><div class='add'>+					     bool state)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_trigger_get_drvdata(trig);</div><div class='add'>+	enum bmi323_irq_pin irq_pin;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (data-&gt;state == BMI323_BUFFER_FIFO) {</div><div class='add'>+		dev_warn(data-&gt;dev, "Can't set trigger when FIFO enabled\n");</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (state) {</div><div class='add'>+		data-&gt;state = BMI323_BUFFER_DRDY_TRIGGERED;</div><div class='add'>+		irq_pin = data-&gt;irq_pin;</div><div class='add'>+	} else {</div><div class='add'>+		data-&gt;state = BMI323_IDLE;</div><div class='add'>+		irq_pin = BMI323_IRQ_DISABLED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return bmi323_set_drdy_irq(data, irq_pin);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_trigger_ops bmi323_trigger_ops = {</div><div class='add'>+	.set_trigger_state = &amp;bmi323_data_rdy_trigger_set_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static irqreturn_t bmi323_trigger_handler(int irq, void *p)</div><div class='add'>+{</div><div class='add'>+	struct iio_poll_func *pf = p;</div><div class='add'>+	struct iio_dev *indio_dev = pf-&gt;indio_dev;</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret, bit, index = 0;</div><div class='add'>+</div><div class='add'>+	/* Lock to protect the data-&gt;buffer */</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (*indio_dev-&gt;active_scan_mask == BMI323_ALL_CHAN_MSK) {</div><div class='add'>+		ret = regmap_bulk_read(data-&gt;regmap, BMI323_ACCEL_X_REG,</div><div class='add'>+				       &amp;data-&gt;buffer.channels,</div><div class='add'>+				       ARRAY_SIZE(data-&gt;buffer.channels));</div><div class='add'>+		if (ret)</div><div class='add'>+			return IRQ_NONE;</div><div class='add'>+	} else {</div><div class='add'>+		for_each_set_bit(bit, indio_dev-&gt;active_scan_mask,</div><div class='add'>+				 BMI323_CHAN_MAX) {</div><div class='add'>+			ret = regmap_raw_read(data-&gt;regmap,</div><div class='add'>+					      BMI323_ACCEL_X_REG + bit,</div><div class='add'>+					      &amp;data-&gt;buffer.channels[index++],</div><div class='add'>+					      BMI323_BYTES_PER_SAMPLE);</div><div class='add'>+			if (ret)</div><div class='add'>+				return IRQ_NONE;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iio_push_to_buffers_with_timestamp(indio_dev, &amp;data-&gt;buffer,</div><div class='add'>+					   iio_get_time_ns(indio_dev));</div><div class='add'>+</div><div class='add'>+	iio_trigger_notify_done(indio_dev-&gt;trig);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_average(struct bmi323_data *data,</div><div class='add'>+			      enum bmi323_sensor_type sensor, int avg)</div><div class='add'>+{</div><div class='add'>+	int raw = ARRAY_SIZE(bmi323_accel_gyro_avrg);</div><div class='add'>+</div><div class='add'>+	while (raw--)</div><div class='add'>+		if (avg == bmi323_accel_gyro_avrg[raw])</div><div class='add'>+			break;</div><div class='add'>+	if (raw &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				 BMI323_ACC_GYRO_CONF_AVG_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_ACC_GYRO_CONF_AVG_MSK,</div><div class='add'>+					    raw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_get_average(struct bmi323_data *data,</div><div class='add'>+			      enum bmi323_sensor_type sensor, int *avg)</div><div class='add'>+{</div><div class='add'>+	int ret, value, raw;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, bmi323_hw[sensor].config, &amp;value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	raw = FIELD_GET(BMI323_ACC_GYRO_CONF_AVG_MSK, value);</div><div class='add'>+	*avg = bmi323_accel_gyro_avrg[raw];</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_enable_steps(struct bmi323_data *data, int val)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	if (data-&gt;odrhz[BMI323_ACCEL] &lt; 200) {</div><div class='add'>+		dev_err(data-&gt;dev, "Invalid accelerometer parameter\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = bmi323_feature_engine_events(data, BMI323_FEAT_IO0_STP_CNT_MSK,</div><div class='add'>+					   val ? 1 : 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	set_mask_bits(&amp;data-&gt;feature_events, BMI323_FEAT_IO0_STP_CNT_MSK,</div><div class='add'>+		      FIELD_PREP(BMI323_FEAT_IO0_STP_CNT_MSK, val ? 1 : 0));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_steps(struct bmi323_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	if (!FIELD_GET(BMI323_FEAT_IO0_STP_CNT_MSK, data-&gt;feature_events))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = regmap_bulk_read(data-&gt;regmap, BMI323_FEAT_IO2_REG,</div><div class='add'>+			       data-&gt;steps_count,</div><div class='add'>+			       ARRAY_SIZE(data-&gt;steps_count));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*val = get_unaligned_le32(data-&gt;steps_count);</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_axis(struct bmi323_data *data,</div><div class='add'>+			    struct iio_chan_spec const *chan, int *val)</div><div class='add'>+{</div><div class='add'>+	enum bmi323_sensor_type sensor;</div><div class='add'>+	unsigned int value;</div><div class='add'>+	u8 addr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_get_error_status(data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	sensor = bmi323_iio_to_sensor(chan-&gt;type);</div><div class='add'>+	addr = bmi323_hw[sensor].data + (chan-&gt;channel2 - IIO_MOD_X);</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, addr, &amp;value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = sign_extend32(value, chan-&gt;scan_type.realbits - 1);</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_get_temp_data(struct bmi323_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	unsigned int value;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_get_error_status(data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, BMI323_TEMP_REG, &amp;value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*val = sign_extend32(value, 15);</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_get_odr(struct bmi323_data *data,</div><div class='add'>+			  enum bmi323_sensor_type sensor, int *odr, int *uodr)</div><div class='add'>+{</div><div class='add'>+	int ret, value, odr_raw;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, bmi323_hw[sensor].config, &amp;value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	odr_raw = FIELD_GET(BMI323_ACC_GYRO_CONF_ODR_MSK, value);</div><div class='add'>+	*odr = bmi323_acc_gyro_odr[odr_raw - 1][0];</div><div class='add'>+	*uodr = bmi323_acc_gyro_odr[odr_raw - 1][1];</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_configure_power_mode(struct bmi323_data *data,</div><div class='add'>+				       enum bmi323_sensor_type sensor,</div><div class='add'>+				       int odr_index)</div><div class='add'>+{</div><div class='add'>+	enum bmi323_opr_mode mode;</div><div class='add'>+</div><div class='add'>+	if (bmi323_acc_gyro_odr[odr_index][0] &gt; 25)</div><div class='add'>+		mode = ACC_GYRO_MODE_CONTINOUS;</div><div class='add'>+	else</div><div class='add'>+		mode = ACC_GYRO_MODE_DUTYCYCLE;</div><div class='add'>+</div><div class='add'>+	return bmi323_set_mode(data, sensor, mode);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_odr(struct bmi323_data *data,</div><div class='add'>+			  enum bmi323_sensor_type sensor, int odr, int uodr)</div><div class='add'>+{</div><div class='add'>+	int odr_raw, ret;</div><div class='add'>+</div><div class='add'>+	odr_raw = ARRAY_SIZE(bmi323_acc_gyro_odr);</div><div class='add'>+</div><div class='add'>+	while (odr_raw--)</div><div class='add'>+		if (odr == bmi323_acc_gyro_odr[odr_raw][0] &amp;&amp;</div><div class='add'>+		    uodr == bmi323_acc_gyro_odr[odr_raw][1])</div><div class='add'>+			break;</div><div class='add'>+	if (odr_raw &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_configure_power_mode(data, sensor, odr_raw);</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	data-&gt;odrhz[sensor] = bmi323_acc_gyro_odr[odr_raw][0];</div><div class='add'>+	data-&gt;odrns[sensor] = bmi323_acc_gyro_odrns[odr_raw];</div><div class='add'>+</div><div class='add'>+	odr_raw++;</div><div class='add'>+</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				  BMI323_ACC_GYRO_CONF_ODR_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_ACC_GYRO_CONF_ODR_MSK,</div><div class='add'>+					     odr_raw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_get_scale(struct bmi323_data *data,</div><div class='add'>+			    enum bmi323_sensor_type sensor, int *val2)</div><div class='add'>+{</div><div class='add'>+	int ret, value, scale_raw;</div><div class='add'>+</div><div class='add'>+	scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				  &amp;value);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	scale_raw = FIELD_GET(BMI323_ACC_GYRO_CONF_SCL_MSK, value);</div><div class='add'>+	*val2 = bmi323_hw[sensor].scale_table[scale_raw][1];</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_scale(struct bmi323_data *data,</div><div class='add'>+			    enum bmi323_sensor_type sensor, int val, int val2)</div><div class='add'>+{</div><div class='add'>+	int scale_raw;</div><div class='add'>+</div><div class='add'>+	scale_raw = bmi323_hw[sensor].scale_table_len;</div><div class='add'>+</div><div class='add'>+	while (scale_raw--)</div><div class='add'>+		if (val == bmi323_hw[sensor].scale_table[scale_raw][0] &amp;&amp;</div><div class='add'>+		    val2 == bmi323_hw[sensor].scale_table[scale_raw][1])</div><div class='add'>+			break;</div><div class='add'>+	if (scale_raw &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;mutex);</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				  BMI323_ACC_GYRO_CONF_SCL_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_ACC_GYRO_CONF_SCL_MSK,</div><div class='add'>+					     scale_raw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_avail(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     const int **vals, int *type, int *length,</div><div class='add'>+			     long mask)</div><div class='add'>+{</div><div class='add'>+	enum bmi323_sensor_type sensor;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		*vals = (const int *)bmi323_acc_gyro_odr;</div><div class='add'>+		*length = ARRAY_SIZE(bmi323_acc_gyro_odr) * 2;</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		sensor = bmi323_iio_to_sensor(chan-&gt;type);</div><div class='add'>+		*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		*vals = (const int *)bmi323_hw[sensor].scale_table;</div><div class='add'>+		*length = bmi323_hw[sensor].scale_table_len * 2;</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:</div><div class='add'>+		*type = IIO_VAL_INT;</div><div class='add'>+		*vals = (const int *)bmi323_accel_gyro_avrg;</div><div class='add'>+		*length = ARRAY_SIZE(bmi323_accel_gyro_avrg);</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			    struct iio_chan_spec const *chan, int val,</div><div class='add'>+			    int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		ret = iio_device_claim_direct_mode(indio_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = bmi323_set_odr(data, bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+				     val, val2);</div><div class='add'>+		iio_device_release_direct_mode(indio_dev);</div><div class='add'>+		return ret;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		ret = iio_device_claim_direct_mode(indio_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = bmi323_set_scale(data, bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+				       val, val2);</div><div class='add'>+		iio_device_release_direct_mode(indio_dev);</div><div class='add'>+		return ret;</div><div class='add'>+	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:</div><div class='add'>+		ret = iio_device_claim_direct_mode(indio_dev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = bmi323_set_average(data, bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+					 val);</div><div class='add'>+</div><div class='add'>+		iio_device_release_direct_mode(indio_dev);</div><div class='add'>+		return ret;</div><div class='add'>+	case IIO_CHAN_INFO_ENABLE:</div><div class='add'>+		return bmi323_enable_steps(data, val);</div><div class='add'>+	case IIO_CHAN_INFO_PROCESSED:</div><div class='add'>+		scoped_guard(mutex, &amp;data-&gt;mutex) {</div><div class='add'>+			if (val || !FIELD_GET(BMI323_FEAT_IO0_STP_CNT_MSK,</div><div class='add'>+					      data-&gt;feature_events))</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+			/* Clear step counter value */</div><div class='add'>+			ret = bmi323_update_ext_reg(data, BMI323_STEP_SC1_REG,</div><div class='add'>+						    BMI323_STEP_SC1_RST_CNT_MSK,</div><div class='add'>+						    FIELD_PREP(BMI323_STEP_SC1_RST_CNT_MSK,</div><div class='add'>+							       1));</div><div class='add'>+		}</div><div class='add'>+		return ret;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			   struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			   int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_PROCESSED:</div><div class='add'>+		return bmi323_read_steps(data, val);</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_ACCEL:</div><div class='add'>+		case IIO_ANGL_VEL:</div><div class='add'>+			ret = iio_device_claim_direct_mode(indio_dev);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			ret = bmi323_read_axis(data, chan, val);</div><div class='add'>+</div><div class='add'>+			iio_device_release_direct_mode(indio_dev);</div><div class='add'>+			return ret;</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			return bmi323_get_temp_data(data, val);</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		return bmi323_get_odr(data, bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+				      val, val2);</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_ACCEL:</div><div class='add'>+		case IIO_ANGL_VEL:</div><div class='add'>+			*val = 0;</div><div class='add'>+			return bmi323_get_scale(data,</div><div class='add'>+						bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+						val2);</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			*val = BMI323_TEMP_SCALE / MEGA;</div><div class='add'>+			*val2 = BMI323_TEMP_SCALE % MEGA;</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:</div><div class='add'>+		return bmi323_get_average(data,</div><div class='add'>+					  bmi323_iio_to_sensor(chan-&gt;type),</div><div class='add'>+					  val);</div><div class='add'>+	case IIO_CHAN_INFO_OFFSET:</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			*val = BMI323_TEMP_OFFSET;</div><div class='add'>+			return IIO_VAL_INT;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_CHAN_INFO_ENABLE:</div><div class='add'>+		scoped_guard(mutex, &amp;data-&gt;mutex)</div><div class='add'>+			*val = FIELD_GET(BMI323_FEAT_IO0_STP_CNT_MSK,</div><div class='add'>+					 data-&gt;feature_events);</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info bmi323_info = {</div><div class='add'>+	.read_raw = bmi323_read_raw,</div><div class='add'>+	.write_raw = bmi323_write_raw,</div><div class='add'>+	.read_avail = bmi323_read_avail,</div><div class='add'>+	.hwfifo_set_watermark = bmi323_set_watermark,</div><div class='add'>+	.write_event_config = bmi323_write_event_config,</div><div class='add'>+	.read_event_config = bmi323_read_event_config,</div><div class='add'>+	.write_event_value = bmi323_write_event_value,</div><div class='add'>+	.read_event_value = bmi323_read_event_value,</div><div class='add'>+	.event_attrs = &amp;bmi323_event_attribute_group,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define BMI323_SCAN_MASK_ACCEL_3AXIS		\</div><div class='add'>+	(BIT(BMI323_ACCEL_X) | BIT(BMI323_ACCEL_Y) | BIT(BMI323_ACCEL_Z))</div><div class='add'>+</div><div class='add'>+#define BMI323_SCAN_MASK_GYRO_3AXIS		\</div><div class='add'>+	(BIT(BMI323_GYRO_X) | BIT(BMI323_GYRO_Y) | BIT(BMI323_GYRO_Z))</div><div class='add'>+</div><div class='add'>+static const unsigned long bmi323_avail_scan_masks[] = {</div><div class='add'>+	/* 3-axis accel */</div><div class='add'>+	BMI323_SCAN_MASK_ACCEL_3AXIS,</div><div class='add'>+	/* 3-axis gyro */</div><div class='add'>+	BMI323_SCAN_MASK_GYRO_3AXIS,</div><div class='add'>+	/* 3-axis accel + 3-axis gyro */</div><div class='add'>+	BMI323_SCAN_MASK_ACCEL_3AXIS | BMI323_SCAN_MASK_GYRO_3AXIS,</div><div class='add'>+	0</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int bmi323_int_pin_config(struct bmi323_data *data,</div><div class='add'>+				 enum bmi323_irq_pin irq_pin,</div><div class='add'>+				 bool active_high, bool open_drain, bool latch)</div><div class='add'>+{</div><div class='add'>+	unsigned int mask, field_value;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, BMI323_IO_INT_CONF_REG,</div><div class='add'>+				 BMI323_IO_INT_LTCH_MSK,</div><div class='add'>+				 FIELD_PREP(BMI323_IO_INT_LTCH_MSK, latch));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_update_ext_reg(data, BMI323_GEN_SET1_REG,</div><div class='add'>+				    BMI323_GEN_HOLD_DUR_MSK,</div><div class='add'>+				    FIELD_PREP(BMI323_GEN_HOLD_DUR_MSK, 0));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (irq_pin) {</div><div class='add'>+	case BMI323_IRQ_INT1:</div><div class='add'>+		mask = BMI323_IO_INT1_LVL_OD_OP_MSK;</div><div class='add'>+</div><div class='add'>+		field_value = FIELD_PREP(BMI323_IO_INT1_LVL_MSK, active_high) |</div><div class='add'>+			      FIELD_PREP(BMI323_IO_INT1_OD_MSK, open_drain) |</div><div class='add'>+			      FIELD_PREP(BMI323_IO_INT1_OP_EN_MSK, 1);</div><div class='add'>+		break;</div><div class='add'>+	case BMI323_IRQ_INT2:</div><div class='add'>+		mask = BMI323_IO_INT2_LVL_OD_OP_MSK;</div><div class='add'>+</div><div class='add'>+		field_value = FIELD_PREP(BMI323_IO_INT2_LVL_MSK, active_high) |</div><div class='add'>+			      FIELD_PREP(BMI323_IO_INT2_OD_MSK, open_drain) |</div><div class='add'>+			      FIELD_PREP(BMI323_IO_INT2_OP_EN_MSK, 1);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, BMI323_IO_INT_CTR_REG, mask,</div><div class='add'>+				  field_value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_trigger_probe(struct bmi323_data *data,</div><div class='add'>+				struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	bool open_drain, active_high, latch;</div><div class='add'>+	struct fwnode_handle *fwnode;</div><div class='add'>+	enum bmi323_irq_pin irq_pin;</div><div class='add'>+	int ret, irq, irq_type;</div><div class='add'>+	struct irq_data *desc;</div><div class='add'>+</div><div class='add'>+	fwnode = dev_fwnode(data-&gt;dev);</div><div class='add'>+	if (!fwnode)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	irq = fwnode_irq_get_byname(fwnode, "INT1");</div><div class='add'>+	if (irq &gt; 0) {</div><div class='add'>+		irq_pin = BMI323_IRQ_INT1;</div><div class='add'>+	} else {</div><div class='add'>+		irq = fwnode_irq_get_byname(fwnode, "INT2");</div><div class='add'>+		if (irq &lt; 0)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		irq_pin = BMI323_IRQ_INT2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	desc = irq_get_irq_data(irq);</div><div class='add'>+	if (!desc)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL,</div><div class='add'>+				     "Could not find IRQ %d\n", irq);</div><div class='add'>+</div><div class='add'>+	irq_type = irqd_get_trigger_type(desc);</div><div class='add'>+	switch (irq_type) {</div><div class='add'>+	case IRQF_TRIGGER_RISING:</div><div class='add'>+		latch = false;</div><div class='add'>+		active_high = true;</div><div class='add'>+		break;</div><div class='add'>+	case IRQF_TRIGGER_HIGH:</div><div class='add'>+		latch = true;</div><div class='add'>+		active_high = true;</div><div class='add'>+		break;</div><div class='add'>+	case IRQF_TRIGGER_FALLING:</div><div class='add'>+		latch = false;</div><div class='add'>+		active_high = false;</div><div class='add'>+		break;</div><div class='add'>+	case IRQF_TRIGGER_LOW:</div><div class='add'>+		latch = true;</div><div class='add'>+		active_high = false;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL,</div><div class='add'>+				     "Invalid interrupt type 0x%x specified\n",</div><div class='add'>+				     irq_type);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	open_drain = fwnode_property_read_bool(fwnode, "drive-open-drain");</div><div class='add'>+</div><div class='add'>+	ret = bmi323_int_pin_config(data, irq_pin, active_high, open_drain,</div><div class='add'>+				    latch);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, ret,</div><div class='add'>+				     "Failed to configure irq line\n");</div><div class='add'>+</div><div class='add'>+	data-&gt;trig = devm_iio_trigger_alloc(data-&gt;dev, "%s-trig-%d",</div><div class='add'>+					    indio_dev-&gt;name, irq_pin);</div><div class='add'>+	if (!data-&gt;trig)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	data-&gt;trig-&gt;ops = &amp;bmi323_trigger_ops;</div><div class='add'>+	iio_trigger_set_drvdata(data-&gt;trig, data);</div><div class='add'>+</div><div class='add'>+	ret = devm_request_threaded_irq(data-&gt;dev, irq, NULL,</div><div class='add'>+					bmi323_irq_thread_handler,</div><div class='add'>+					IRQF_ONESHOT, "bmi323-int", indio_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, ret, "Failed to request IRQ\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_iio_trigger_register(data-&gt;dev, data-&gt;trig);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, ret,</div><div class='add'>+				     "Trigger registration failed\n");</div><div class='add'>+</div><div class='add'>+	data-&gt;irq_pin = irq_pin;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_feature_engine_enable(struct bmi323_data *data, bool en)</div><div class='add'>+{</div><div class='add'>+	unsigned int feature_status;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!en)</div><div class='add'>+		return regmap_write(data-&gt;regmap, BMI323_FEAT_CTRL_REG, 0);</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_IO2_REG, 0x012c);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_IO_STATUS_REG,</div><div class='add'>+			   BMI323_FEAT_IO_STATUS_MSK);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_FEAT_CTRL_REG,</div><div class='add'>+			   BMI323_FEAT_ENG_EN_MSK);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * It takes around 4 msec to enable the Feature engine, so check</div><div class='add'>+	 * the status of the feature engine every 2 msec for a maximum</div><div class='add'>+	 * of 5 trials.</div><div class='add'>+	 */</div><div class='add'>+	ret = regmap_read_poll_timeout(data-&gt;regmap, BMI323_FEAT_IO1_REG,</div><div class='add'>+				       feature_status,</div><div class='add'>+				       FIELD_GET(BMI323_FEAT_IO1_ERR_MSK,</div><div class='add'>+						 feature_status) == 1,</div><div class='add'>+				       BMI323_FEAT_ENG_POLL,</div><div class='add'>+				       BMI323_FEAT_ENG_TIMEOUT);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL,</div><div class='add'>+				"Failed to enable feature engine\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void bmi323_disable(void *data_ptr)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_data *data = data_ptr;</div><div class='add'>+</div><div class='add'>+	bmi323_set_mode(data, BMI323_ACCEL, ACC_GYRO_MODE_DISABLE);</div><div class='add'>+	bmi323_set_mode(data, BMI323_GYRO, ACC_GYRO_MODE_DISABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_set_bw(struct bmi323_data *data,</div><div class='add'>+			 enum bmi323_sensor_type sensor, enum bmi323_3db_bw bw)</div><div class='add'>+{</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, bmi323_hw[sensor].config,</div><div class='add'>+				  BMI323_ACC_GYRO_CONF_BW_MSK,</div><div class='add'>+				  FIELD_PREP(BMI323_ACC_GYRO_CONF_BW_MSK, bw));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_init(struct bmi323_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret, val;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Perform soft reset to make sure the device is in a known state after</div><div class='add'>+	 * start up. A delay of 1.5 ms is required after reset.</div><div class='add'>+	 * See datasheet section 5.17 "Soft Reset".</div><div class='add'>+	 */</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, BMI323_CMD_REG, BMI323_RST_VAL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	usleep_range(1500, 2000);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Dummy read is required to enable SPI interface after reset.</div><div class='add'>+	 * See datasheet section 7.2.1 "Protocol Selection".</div><div class='add'>+	 */</div><div class='add'>+	regmap_read(data-&gt;regmap, BMI323_CHIP_ID_REG, &amp;val);</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_STATUS_REG, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!FIELD_GET(BMI323_STATUS_POR_MSK, val))</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL,</div><div class='add'>+				     "Sensor initialization error\n");</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_CHIP_ID_REG, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(BMI323_CHIP_ID_MSK, val) != BMI323_CHIP_ID_VAL)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL, "Chip ID mismatch\n");</div><div class='add'>+</div><div class='add'>+	ret = bmi323_feature_engine_enable(data, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, BMI323_ERR_REG, &amp;val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (val)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, -EINVAL,</div><div class='add'>+				     "Sensor power error = 0x%x\n", val);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set the Bandwidth coefficient which defines the 3 dB cutoff</div><div class='add'>+	 * frequency in relation to the ODR.</div><div class='add'>+	 */</div><div class='add'>+	ret = bmi323_set_bw(data, BMI323_ACCEL, BMI323_BW_ODR_BY_2);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_set_bw(data, BMI323_GYRO, BMI323_BW_ODR_BY_2);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_set_odr(data, BMI323_ACCEL, 25, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bmi323_set_odr(data, BMI323_GYRO, 25, 0);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return devm_add_action_or_reset(data-&gt;dev, bmi323_disable, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bmi323_core_probe(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	static const char * const regulator_names[] = { "vdd", "vddio" };</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct bmi323_data *data;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	regmap = dev_get_regmap(dev, NULL);</div><div class='add'>+	if (!regmap)</div><div class='add'>+		return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n");</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return dev_err_probe(dev, -ENOMEM,</div><div class='add'>+				     "Failed to allocate device\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),</div><div class='add'>+					     regulator_names);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "Failed to enable regulators\n");</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+	data-&gt;dev = dev;</div><div class='add'>+	data-&gt;regmap = regmap;</div><div class='add'>+	mutex_init(&amp;data-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = bmi323_init(data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = iio_read_mount_matrix(dev, &amp;data-&gt;orientation);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;name = "bmi323-imu";</div><div class='add'>+	indio_dev-&gt;info = &amp;bmi323_info;</div><div class='add'>+	indio_dev-&gt;channels = bmi323_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(bmi323_channels);</div><div class='add'>+	indio_dev-&gt;available_scan_masks = bmi323_avail_scan_masks;</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;</div><div class='add'>+	dev_set_drvdata(data-&gt;dev, indio_dev);</div><div class='add'>+</div><div class='add'>+	ret = bmi323_trigger_probe(data, indio_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = devm_iio_triggered_buffer_setup_ext(data-&gt;dev, indio_dev,</div><div class='add'>+						  &amp;iio_pollfunc_store_time,</div><div class='add'>+						  bmi323_trigger_handler,</div><div class='add'>+						  IIO_BUFFER_DIRECTION_IN,</div><div class='add'>+						  &amp;bmi323_buffer_ops,</div><div class='add'>+						  bmi323_fifo_attributes);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, ret,</div><div class='add'>+				     "Failed to setup trigger buffer\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_iio_device_register(data-&gt;dev, indio_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(data-&gt;dev, ret,</div><div class='add'>+				     "Unable to register iio device\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(bmi323_core_probe, IIO_BMI323);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Bosch BMI323 IMU driver");</div><div class='add'>+MODULE_AUTHOR("Jagath Jog J &lt;jagathjog1996@gmail.com&gt;");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/imu/bmi323/bmi323_i2c.c b/drivers/iio/imu/bmi323/bmi323_i2c.c<br/>new file mode 100644<br/>index 000000000000..20a8001b9956<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/bmi323_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_i2c.c</a></div><div class='hunk'>@@ -0,0 +1,121 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * I2C driver for Bosch BMI323 6-Axis IMU.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023, Jagath Jog J &lt;jagathjog1996@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bmi323.h"</div><div class='add'>+</div><div class='add'>+struct bmi323_i2c_priv {</div><div class='add'>+	struct i2c_client *i2c;</div><div class='add'>+	u8 i2c_rx_buffer[BMI323_FIFO_LENGTH_IN_BYTES + BMI323_I2C_DUMMY];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * From BMI323 datasheet section 4: Notes on the Serial Interface Support.</div><div class='add'>+ * Each I2C register read operation requires to read two dummy bytes before</div><div class='add'>+ * the actual payload.</div><div class='add'>+ */</div><div class='add'>+static int bmi323_regmap_i2c_read(void *context, const void *reg_buf,</div><div class='add'>+				  size_t reg_size, void *val_buf,</div><div class='add'>+				  size_t val_size)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_i2c_priv *priv = context;</div><div class='add'>+	struct i2c_msg msgs[2];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	msgs[0].addr = priv-&gt;i2c-&gt;addr;</div><div class='add'>+	msgs[0].flags = priv-&gt;i2c-&gt;flags;</div><div class='add'>+	msgs[0].len = reg_size;</div><div class='add'>+	msgs[0].buf = (u8 *)reg_buf;</div><div class='add'>+</div><div class='add'>+	msgs[1].addr = priv-&gt;i2c-&gt;addr;</div><div class='add'>+	msgs[1].len = val_size + BMI323_I2C_DUMMY;</div><div class='add'>+	msgs[1].buf = priv-&gt;i2c_rx_buffer;</div><div class='add'>+	msgs[1].flags = priv-&gt;i2c-&gt;flags | I2C_M_RD;</div><div class='add'>+</div><div class='add'>+	ret = i2c_transfer(priv-&gt;i2c-&gt;adapter, msgs, ARRAY_SIZE(msgs));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	memcpy(val_buf, priv-&gt;i2c_rx_buffer + BMI323_I2C_DUMMY, val_size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_regmap_i2c_write(void *context, const void *data,</div><div class='add'>+				   size_t count)</div><div class='add'>+{</div><div class='add'>+	struct bmi323_i2c_priv *priv = context;</div><div class='add'>+	u8 reg;</div><div class='add'>+</div><div class='add'>+	reg = *(u8 *)data;</div><div class='add'>+	return i2c_smbus_write_i2c_block_data(priv-&gt;i2c, reg,</div><div class='add'>+					      count - sizeof(u8),</div><div class='add'>+					      data + sizeof(u8));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct regmap_bus bmi323_regmap_bus = {</div><div class='add'>+	.read = bmi323_regmap_i2c_read,</div><div class='add'>+	.write = bmi323_regmap_i2c_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config bmi323_i2c_regmap_config = {</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+	.max_register = BMI323_CFG_RES_REG,</div><div class='add'>+	.val_format_endian = REGMAP_ENDIAN_LITTLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int bmi323_i2c_probe(struct i2c_client *i2c)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;i2c-&gt;dev;</div><div class='add'>+	struct bmi323_i2c_priv *priv;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;i2c = i2c;</div><div class='add'>+	regmap = devm_regmap_init(dev, &amp;bmi323_regmap_bus, priv,</div><div class='add'>+				  &amp;bmi323_i2c_regmap_config);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(regmap),</div><div class='add'>+				     "Failed to initialize I2C Regmap\n");</div><div class='add'>+</div><div class='add'>+	return bmi323_core_probe(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id bmi323_i2c_ids[] = {</div><div class='add'>+	{ "bmi323" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, bmi323_i2c_ids);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id bmi323_of_i2c_match[] = {</div><div class='add'>+	{ .compatible = "bosch,bmi323" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, bmi323_of_i2c_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver bmi323_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "bmi323",</div><div class='add'>+		.of_match_table = bmi323_of_i2c_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = bmi323_i2c_probe,</div><div class='add'>+	.id_table = bmi323_i2c_ids,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(bmi323_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Bosch BMI323 IMU driver");</div><div class='add'>+MODULE_AUTHOR("Jagath Jog J &lt;jagathjog1996@gmail.com&gt;");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(IIO_BMI323);</div><div class='head'>diff --git a/drivers/iio/imu/bmi323/bmi323_spi.c b/drivers/iio/imu/bmi323/bmi323_spi.c<br/>new file mode 100644<br/>index 000000000000..7b1e8127d0dd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bmi323/bmi323_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bmi323/bmi323_spi.c</a></div><div class='hunk'>@@ -0,0 +1,92 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * SPI driver for Bosch BMI323 6-Axis IMU.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023, Jagath Jog J &lt;jagathjog1996@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/spi/spi.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bmi323.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * From BMI323 datasheet section 4: Notes on the Serial Interface Support.</div><div class='add'>+ * Each SPI register read operation requires to read one dummy byte before</div><div class='add'>+ * the actual payload.</div><div class='add'>+ */</div><div class='add'>+static int bmi323_regmap_spi_read(void *context, const void *reg_buf,</div><div class='add'>+				  size_t reg_size, void *val_buf,</div><div class='add'>+				  size_t val_size)</div><div class='add'>+{</div><div class='add'>+	struct spi_device *spi = context;</div><div class='add'>+</div><div class='add'>+	return spi_write_then_read(spi, reg_buf, reg_size, val_buf, val_size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bmi323_regmap_spi_write(void *context, const void *data,</div><div class='add'>+				   size_t count)</div><div class='add'>+{</div><div class='add'>+	struct spi_device *spi = context;</div><div class='add'>+	u8 *data_buff = (u8 *)data;</div><div class='add'>+</div><div class='add'>+	data_buff[1] = data_buff[0];</div><div class='add'>+	return spi_write(spi, data_buff + 1, count - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct regmap_bus bmi323_regmap_bus = {</div><div class='add'>+	.read = bmi323_regmap_spi_read,</div><div class='add'>+	.write = bmi323_regmap_spi_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config bmi323_spi_regmap_config = {</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+	.pad_bits = 8,</div><div class='add'>+	.read_flag_mask = BIT(7),</div><div class='add'>+	.max_register = BMI323_CFG_RES_REG,</div><div class='add'>+	.val_format_endian = REGMAP_ENDIAN_LITTLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int bmi323_spi_probe(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;spi-&gt;dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	regmap = devm_regmap_init(dev, &amp;bmi323_regmap_bus, dev,</div><div class='add'>+				  &amp;bmi323_spi_regmap_config);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(regmap),</div><div class='add'>+				     "Failed to initialize SPI Regmap\n");</div><div class='add'>+</div><div class='add'>+	return bmi323_core_probe(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct spi_device_id bmi323_spi_ids[] = {</div><div class='add'>+	{ "bmi323" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, bmi323_spi_ids);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id bmi323_of_spi_match[] = {</div><div class='add'>+	{ .compatible = "bosch,bmi323" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, bmi323_of_spi_match);</div><div class='add'>+</div><div class='add'>+static struct spi_driver bmi323_spi_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "bmi323",</div><div class='add'>+		.of_match_table = bmi323_of_spi_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = bmi323_spi_probe,</div><div class='add'>+	.id_table = bmi323_spi_ids,</div><div class='add'>+};</div><div class='add'>+module_spi_driver(bmi323_spi_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Bosch BMI323 IMU driver");</div><div class='add'>+MODULE_AUTHOR("Jagath Jog J &lt;jagathjog1996@gmail.com&gt;");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(IIO_BMI323);</div><div class='head'>diff --git a/drivers/iio/imu/bno055/bno055_ser_core.c b/drivers/iio/imu/bno055/bno055_ser_core.c<br/>index 57728a568471..5677bdf4f846 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/bno055/bno055_ser_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/bno055/bno055_ser_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/bno055/bno055_ser_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/bno055/bno055_ser_core.c</a></div><div class='hunk'>@@ -378,12 +378,12 @@ static void bno055_ser_handle_rx(struct bno055_ser_priv *priv, int status)</div><div class='ctx'>  * Also, we assume to RX one pkt per time (i.e. the HW doesn't send anything</div><div class='ctx'>  * unless we require to AND we don't queue more than one request per time).</div><div class='ctx'>  */</div><div class='del'>-static int bno055_ser_receive_buf(struct serdev_device *serdev,</div><div class='del'>-				  const unsigned char *buf, size_t size)</div><div class='add'>+static ssize_t bno055_ser_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				      const u8 *buf, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	int status;</div><div class='ctx'> 	struct bno055_ser_priv *priv = serdev_device_get_drvdata(serdev);</div><div class='del'>-	int remaining = size;</div><div class='add'>+	size_t remaining = size;</div><div class='ctx'> </div><div class='ctx'> 	if (size == 0)</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c<br/>index b1e4fde27d25..f67bd5a39beb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c</a></div><div class='hunk'>@@ -137,10 +137,7 @@ static int inv_icm42600_accel_update_scan_mode(struct iio_dev *indio_dev,</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;st-&gt;lock);</div><div class='ctx'> 	/* sleep maximum required time */</div><div class='del'>-	if (sleep_accel &gt; sleep_temp)</div><div class='del'>-		sleep = sleep_accel;</div><div class='del'>-	else</div><div class='del'>-		sleep = sleep_temp;</div><div class='add'>+	sleep = max(sleep_accel, sleep_temp);</div><div class='ctx'> 	if (sleep)</div><div class='ctx'> 		msleep(sleep);</div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c<br/>index 6ef1df9d60b7..b52f328fd26c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c</a></div><div class='hunk'>@@ -424,10 +424,7 @@ out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;st-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	/* sleep maximum required time */</div><div class='del'>-	if (sleep_sensor &gt; sleep_temp)</div><div class='del'>-		sleep = sleep_sensor;</div><div class='del'>-	else</div><div class='del'>-		sleep = sleep_temp;</div><div class='add'>+	sleep = max(sleep_sensor, sleep_temp);</div><div class='ctx'> 	if (sleep)</div><div class='ctx'> 		msleep(sleep);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c<br/>index 3bf946e56e1d..3df0a715e885 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c</a></div><div class='hunk'>@@ -137,10 +137,7 @@ static int inv_icm42600_gyro_update_scan_mode(struct iio_dev *indio_dev,</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;st-&gt;lock);</div><div class='ctx'> 	/* sleep maximum required time */</div><div class='del'>-	if (sleep_gyro &gt; sleep_temp)</div><div class='del'>-		sleep = sleep_gyro;</div><div class='del'>-	else</div><div class='del'>-		sleep = sleep_temp;</div><div class='add'>+	sleep = max(sleep_gyro, sleep_temp);</div><div class='ctx'> 	if (sleep)</div><div class='ctx'> 		msleep(sleep);</div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c<br/>index 3fbeef1a7018..0e94e5335e93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/imu/inv_mpu6050/inv_mpu_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/imu/inv_mpu6050/inv_mpu_core.c</a></div><div class='hunk'>@@ -567,15 +567,12 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev)</div><div class='ctx'> static int inv_mpu6050_sensor_set(struct inv_mpu6050_state  *st, int reg,</div><div class='ctx'> 				int axis, int val)</div><div class='ctx'> {</div><div class='del'>-	int ind, result;</div><div class='add'>+	int ind;</div><div class='ctx'> 	__be16 d = cpu_to_be16(val);</div><div class='ctx'> </div><div class='ctx'> 	ind = (axis - IIO_MOD_X) * 2;</div><div class='del'>-	result = regmap_bulk_write(st-&gt;map, reg + ind, &amp;d, sizeof(d));</div><div class='del'>-	if (result)</div><div class='del'>-		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return regmap_bulk_write(st-&gt;map, reg + ind, &amp;d, sizeof(d));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int inv_mpu6050_sensor_show(struct inv_mpu6050_state  *st, int reg,</div><div class='hunk'>@@ -587,7 +584,7 @@ static int inv_mpu6050_sensor_show(struct inv_mpu6050_state  *st, int reg,</div><div class='ctx'> 	ind = (axis - IIO_MOD_X) * 2;</div><div class='ctx'> 	result = regmap_bulk_read(st-&gt;map, reg + ind, &amp;d, sizeof(d));</div><div class='ctx'> 	if (result)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return result;</div><div class='ctx'> 	*val = (short)be16_to_cpup(&amp;d);</div><div class='ctx'> </div><div class='ctx'> 	return IIO_VAL_INT;</div><div class='hunk'>@@ -750,13 +747,13 @@ inv_mpu6050_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 			ret = inv_mpu6050_sensor_show(st, st-&gt;reg-&gt;gyro_offset,</div><div class='ctx'> 						chan-&gt;channel2, val);</div><div class='ctx'> 			mutex_unlock(&amp;st-&gt;lock);</div><div class='del'>-			return IIO_VAL_INT;</div><div class='add'>+			return ret;</div><div class='ctx'> 		case IIO_ACCEL:</div><div class='ctx'> 			mutex_lock(&amp;st-&gt;lock);</div><div class='ctx'> 			ret = inv_mpu6050_sensor_show(st, st-&gt;reg-&gt;accl_offset,</div><div class='ctx'> 						chan-&gt;channel2, val);</div><div class='ctx'> 			mutex_unlock(&amp;st-&gt;lock);</div><div class='del'>-			return IIO_VAL_INT;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='ctx'> 		default:</div><div class='ctx'> 			return -EINVAL;</div><div class='head'>diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c<br/>index 176d31d9f9d8..b581a7e80566 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/industrialio-buffer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/industrialio-buffer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/industrialio-buffer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/industrialio-buffer.c</a></div><div class='hunk'>@@ -413,6 +413,22 @@ static const unsigned long *iio_scan_mask_match(const unsigned long *av_masks,</div><div class='ctx'> {</div><div class='ctx'> 	if (bitmap_empty(mask, masklength))</div><div class='ctx'> 		return NULL;</div><div class='add'>+	/*</div><div class='add'>+	 * The condition here do not handle multi-long masks correctly.</div><div class='add'>+	 * It only checks the first long to be zero, and will use such mask</div><div class='add'>+	 * as a terminator even if there was bits set after the first long.</div><div class='add'>+	 *</div><div class='add'>+	 * Correct check would require using:</div><div class='add'>+	 * while (!bitmap_empty(av_masks, masklength))</div><div class='add'>+	 * instead. This is potentially hazardous because the</div><div class='add'>+	 * avaliable_scan_masks is a zero terminated array of longs - and</div><div class='add'>+	 * using the proper bitmap_empty() check for multi-long wide masks</div><div class='add'>+	 * would require the array to be terminated with multiple zero longs -</div><div class='add'>+	 * which is not such an usual pattern.</div><div class='add'>+	 *</div><div class='add'>+	 * As writing of this no multi-long wide masks were found in-tree, so</div><div class='add'>+	 * the simple while (*av_masks) check is working.</div><div class='add'>+	 */</div><div class='ctx'> 	while (*av_masks) {</div><div class='ctx'> 		if (strict) {</div><div class='ctx'> 			if (bitmap_equal(mask, av_masks, masklength))</div><div class='hunk'>@@ -600,7 +616,7 @@ static int iio_buffer_add_channel_sysfs(struct iio_dev *indio_dev,</div><div class='ctx'> 				     &amp;iio_show_fixed_type,</div><div class='ctx'> 				     NULL,</div><div class='ctx'> 				     0,</div><div class='del'>-				     0,</div><div class='add'>+				     IIO_SEPARATE,</div><div class='ctx'> 				     &amp;indio_dev-&gt;dev,</div><div class='ctx'> 				     buffer,</div><div class='ctx'> 				     &amp;buffer-&gt;buffer_attr_list);</div><div class='hunk'>@@ -613,7 +629,7 @@ static int iio_buffer_add_channel_sysfs(struct iio_dev *indio_dev,</div><div class='ctx'> 					     &amp;iio_scan_el_show,</div><div class='ctx'> 					     &amp;iio_scan_el_store,</div><div class='ctx'> 					     chan-&gt;scan_index,</div><div class='del'>-					     0,</div><div class='add'>+					     IIO_SEPARATE,</div><div class='ctx'> 					     &amp;indio_dev-&gt;dev,</div><div class='ctx'> 					     buffer,</div><div class='ctx'> 					     &amp;buffer-&gt;buffer_attr_list);</div><div class='hunk'>@@ -623,7 +639,7 @@ static int iio_buffer_add_channel_sysfs(struct iio_dev *indio_dev,</div><div class='ctx'> 					     &amp;iio_scan_el_ts_show,</div><div class='ctx'> 					     &amp;iio_scan_el_ts_store,</div><div class='ctx'> 					     chan-&gt;scan_index,</div><div class='del'>-					     0,</div><div class='add'>+					     IIO_SEPARATE,</div><div class='ctx'> 					     &amp;indio_dev-&gt;dev,</div><div class='ctx'> 					     buffer,</div><div class='ctx'> 					     &amp;buffer-&gt;buffer_attr_list);</div><div class='head'>diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c<br/>index c77745b594bd..9a85752124dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/industrialio-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/industrialio-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/industrialio-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/industrialio-core.c</a></div><div class='hunk'>@@ -117,6 +117,8 @@ static const char * const iio_modifier_names[] = {</div><div class='ctx'> 	[IIO_MOD_LIGHT_GREEN] = "green",</div><div class='ctx'> 	[IIO_MOD_LIGHT_BLUE] = "blue",</div><div class='ctx'> 	[IIO_MOD_LIGHT_UV] = "uv",</div><div class='add'>+	[IIO_MOD_LIGHT_UVA] = "uva",</div><div class='add'>+	[IIO_MOD_LIGHT_UVB] = "uvb",</div><div class='ctx'> 	[IIO_MOD_LIGHT_DUV] = "duv",</div><div class='ctx'> 	[IIO_MOD_QUATERNION] = "quaternion",</div><div class='ctx'> 	[IIO_MOD_TEMP_AMBIENT] = "ambient",</div><div class='hunk'>@@ -182,6 +184,7 @@ static const char * const iio_chan_info_postfix[] = {</div><div class='ctx'> 	[IIO_CHAN_INFO_THERMOCOUPLE_TYPE] = "thermocouple_type",</div><div class='ctx'> 	[IIO_CHAN_INFO_CALIBAMBIENT] = "calibambient",</div><div class='ctx'> 	[IIO_CHAN_INFO_ZEROPOINT] = "zeropoint",</div><div class='add'>+	[IIO_CHAN_INFO_TROUGH] = "trough_raw",</div><div class='ctx'> };</div><div class='ctx'> /**</div><div class='ctx'>  * iio_device_id() - query the unique ID for the device</div><div class='hunk'>@@ -1896,6 +1899,66 @@ static int iio_check_extended_name(const struct iio_dev *indio_dev)</div><div class='ctx'> </div><div class='ctx'> static const struct iio_buffer_setup_ops noop_ring_setup_ops;</div><div class='ctx'> </div><div class='add'>+static void iio_sanity_check_avail_scan_masks(struct iio_dev *indio_dev)</div><div class='add'>+{</div><div class='add'>+	unsigned int num_masks, masklength, longs_per_mask;</div><div class='add'>+	const unsigned long *av_masks;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	av_masks = indio_dev-&gt;available_scan_masks;</div><div class='add'>+	masklength = indio_dev-&gt;masklength;</div><div class='add'>+	longs_per_mask = BITS_TO_LONGS(masklength);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The code determining how many available_scan_masks is in the array</div><div class='add'>+	 * will be assuming the end of masks when first long with all bits</div><div class='add'>+	 * zeroed is encountered. This is incorrect for masks where mask</div><div class='add'>+	 * consists of more than one long, and where some of the available masks</div><div class='add'>+	 * has long worth of bits zeroed (but has subsequent bit(s) set). This</div><div class='add'>+	 * is a safety measure against bug where array of masks is terminated by</div><div class='add'>+	 * a single zero while mask width is greater than width of a long.</div><div class='add'>+	 */</div><div class='add'>+	if (longs_per_mask &gt; 1)</div><div class='add'>+		dev_warn(indio_dev-&gt;dev.parent,</div><div class='add'>+			 "multi long available scan masks not fully supported\n");</div><div class='add'>+</div><div class='add'>+	if (bitmap_empty(av_masks, masklength))</div><div class='add'>+		dev_warn(indio_dev-&gt;dev.parent, "empty scan mask\n");</div><div class='add'>+</div><div class='add'>+	for (num_masks = 0; *av_masks; num_masks++)</div><div class='add'>+		av_masks += longs_per_mask;</div><div class='add'>+</div><div class='add'>+	if (num_masks &lt; 2)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	av_masks = indio_dev-&gt;available_scan_masks;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Go through all the masks from first to one before the last, and see</div><div class='add'>+	 * that no mask found later from the available_scan_masks array is a</div><div class='add'>+	 * subset of mask found earlier. If this happens, then the mask found</div><div class='add'>+	 * later will never get used because scanning the array is stopped when</div><div class='add'>+	 * the first suitable mask is found. Drivers should order the array of</div><div class='add'>+	 * available masks in the order of preference (presumably the least</div><div class='add'>+	 * costy to access masks first).</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; num_masks - 1; i++) {</div><div class='add'>+		const unsigned long *mask1;</div><div class='add'>+		int j;</div><div class='add'>+</div><div class='add'>+		mask1 = av_masks + i * longs_per_mask;</div><div class='add'>+		for (j = i + 1; j &lt; num_masks; j++) {</div><div class='add'>+			const unsigned long *mask2;</div><div class='add'>+</div><div class='add'>+			mask2 = av_masks + j * longs_per_mask;</div><div class='add'>+			if (bitmap_subset(mask2, mask1, masklength))</div><div class='add'>+				dev_warn(indio_dev-&gt;dev.parent,</div><div class='add'>+					 "available_scan_mask %d subset of %d. Never used\n",</div><div class='add'>+					 j, i);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod)</div><div class='ctx'> {</div><div class='ctx'> 	struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);</div><div class='hunk'>@@ -1934,6 +1997,9 @@ int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod)</div><div class='ctx'> 		goto error_unreg_debugfs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (indio_dev-&gt;available_scan_masks)</div><div class='add'>+		iio_sanity_check_avail_scan_masks(indio_dev);</div><div class='add'>+</div><div class='ctx'> 	ret = iio_device_register_sysfs(indio_dev);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(indio_dev-&gt;dev.parent,</div><div class='head'>diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig<br/>index 45edba797e4c..143003232d1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/Kconfig</a></div><div class='hunk'>@@ -252,6 +252,21 @@ config ISL29125</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module will be</div><div class='ctx'> 	  called isl29125.</div><div class='ctx'> </div><div class='add'>+config ISL76682</div><div class='add'>+	tristate "Intersil ISL76682 Light Sensor"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select REGMAP_I2C</div><div class='add'>+	help</div><div class='add'>+	  Say Y here if you want to build a driver for the Intersil ISL76682</div><div class='add'>+	  Ambient Light Sensor and IR Intensity sensor. This driver provides</div><div class='add'>+	  the readouts via standard IIO sysfs and device interface. Both ALS</div><div class='add'>+	  illuminance and IR illuminance are provided raw with separate scale</div><div class='add'>+	  setting which can be configured via sysfs, the default scale is 1000</div><div class='add'>+	  lux, other options are 4000/16000/64000 lux.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module will be</div><div class='add'>+	  called isl76682.</div><div class='add'>+</div><div class='ctx'> config HID_SENSOR_ALS</div><div class='ctx'> 	depends on HID_SENSOR_HUB</div><div class='ctx'> 	select IIO_BUFFER</div><div class='hunk'>@@ -347,6 +362,17 @@ config SENSORS_LM3533</div><div class='ctx'> 	  changes. The ALS-control output values can be set per zone for the</div><div class='ctx'> 	  three current output channels.</div><div class='ctx'> </div><div class='add'>+config LTR390</div><div class='add'>+	tristate "LTR-390UV-01 ambient light and UV sensor"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select REGMAP_I2C</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get support for the Lite-On LTR-390UV-01</div><div class='add'>+	  ambient light and UV sensor.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module.  If so, the module</div><div class='add'>+	  will be called ltr390.</div><div class='add'>+</div><div class='ctx'> config LTR501</div><div class='ctx'> 	tristate "LTR-501ALS-01 light sensor"</div><div class='ctx'> 	depends on I2C</div><div class='hunk'>@@ -637,6 +663,17 @@ config VEML6070</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the</div><div class='ctx'> 	  module will be called veml6070.</div><div class='ctx'> </div><div class='add'>+config VEML6075</div><div class='add'>+	tristate "VEML6075 UVA and UVB light sensor"</div><div class='add'>+	select REGMAP_I2C</div><div class='add'>+	depends on I2C</div><div class='add'>+	help</div><div class='add'>+	  Say Y here if you want to build a driver for the Vishay VEML6075 UVA</div><div class='add'>+	  and UVB light sensor.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called veml6075.</div><div class='add'>+</div><div class='ctx'> config VL6180</div><div class='ctx'> 	tristate "VL6180 ALS, range and proximity sensor"</div><div class='ctx'> 	depends on I2C</div><div class='head'>diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile<br/>index c0db4c4c36ec..2e5fdb33e0e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/Makefile</a></div><div class='hunk'>@@ -28,8 +28,10 @@ obj-$(CONFIG_IQS621_ALS)	+= iqs621-als.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_ISL29018)	+= isl29018.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_ISL29028)	+= isl29028.o</div><div class='ctx'> obj-$(CONFIG_ISL29125)		+= isl29125.o</div><div class='add'>+obj-$(CONFIG_ISL76682)		+= isl76682.o</div><div class='ctx'> obj-$(CONFIG_JSA1212)		+= jsa1212.o</div><div class='ctx'> obj-$(CONFIG_SENSORS_LM3533)	+= lm3533-als.o</div><div class='add'>+obj-$(CONFIG_LTR390)		+= ltr390.o</div><div class='ctx'> obj-$(CONFIG_LTR501)		+= ltr501.o</div><div class='ctx'> obj-$(CONFIG_LTRF216A)		+= ltrf216a.o</div><div class='ctx'> obj-$(CONFIG_LV0104CS)		+= lv0104cs.o</div><div class='hunk'>@@ -60,5 +62,6 @@ obj-$(CONFIG_VCNL4000)		+= vcnl4000.o</div><div class='ctx'> obj-$(CONFIG_VCNL4035)		+= vcnl4035.o</div><div class='ctx'> obj-$(CONFIG_VEML6030)		+= veml6030.o</div><div class='ctx'> obj-$(CONFIG_VEML6070)		+= veml6070.o</div><div class='add'>+obj-$(CONFIG_VEML6075)		+= veml6075.o</div><div class='ctx'> obj-$(CONFIG_VL6180)		+= vl6180.o</div><div class='ctx'> obj-$(CONFIG_ZOPT2201)		+= zopt2201.o</div><div class='head'>diff --git a/drivers/iio/light/hid-sensor-als.c b/drivers/iio/light/hid-sensor-als.c<br/>index f17304b54468..5cd27f04b45e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/hid-sensor-als.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/hid-sensor-als.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/hid-sensor-als.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/hid-sensor-als.c</a></div><div class='hunk'>@@ -14,11 +14,8 @@</div><div class='ctx'> #include "../common/hid-sensors/hid-sensor-trigger.h"</div><div class='ctx'> </div><div class='ctx'> enum {</div><div class='del'>-	CHANNEL_SCAN_INDEX_INTENSITY,</div><div class='del'>-	CHANNEL_SCAN_INDEX_ILLUM,</div><div class='del'>-	CHANNEL_SCAN_INDEX_COLOR_TEMP,</div><div class='del'>-	CHANNEL_SCAN_INDEX_CHROMATICITY_X,</div><div class='del'>-	CHANNEL_SCAN_INDEX_CHROMATICITY_Y,</div><div class='add'>+	CHANNEL_SCAN_INDEX_INTENSITY = 0,</div><div class='add'>+	CHANNEL_SCAN_INDEX_ILLUM = 1,</div><div class='ctx'> 	CHANNEL_SCAN_INDEX_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -68,40 +65,6 @@ static const struct iio_chan_spec als_channels[] = {</div><div class='ctx'> 		BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),</div><div class='ctx'> 		.scan_index = CHANNEL_SCAN_INDEX_ILLUM,</div><div class='ctx'> 	},</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_COLORTEMP,</div><div class='del'>-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),</div><div class='del'>-		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SCALE) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SAMP_FREQ) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),</div><div class='del'>-		.scan_index = CHANNEL_SCAN_INDEX_COLOR_TEMP,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_CHROMATICITY,</div><div class='del'>-		.modified = 1,</div><div class='del'>-		.channel2 = IIO_MOD_X,</div><div class='del'>-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),</div><div class='del'>-		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SCALE) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SAMP_FREQ) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),</div><div class='del'>-		.scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_X,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='del'>-		.type = IIO_CHROMATICITY,</div><div class='del'>-		.modified = 1,</div><div class='del'>-		.channel2 = IIO_MOD_Y,</div><div class='del'>-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),</div><div class='del'>-		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SCALE) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_SAMP_FREQ) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS) |</div><div class='del'>-		BIT(IIO_CHAN_INFO_HYSTERESIS_RELATIVE),</div><div class='del'>-		.scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_Y,</div><div class='del'>-	},</div><div class='ctx'> 	IIO_CHAN_SOFT_TIMESTAMP(CHANNEL_SCAN_INDEX_TIMESTAMP)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -140,21 +103,6 @@ static int als_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 			min = als_state-&gt;als[chan-&gt;scan_index].logical_minimum;</div><div class='ctx'> 			address = HID_USAGE_SENSOR_LIGHT_ILLUM;</div><div class='ctx'> 			break;</div><div class='del'>-		case  CHANNEL_SCAN_INDEX_COLOR_TEMP:</div><div class='del'>-			report_id = als_state-&gt;als[chan-&gt;scan_index].report_id;</div><div class='del'>-			min = als_state-&gt;als[chan-&gt;scan_index].logical_minimum;</div><div class='del'>-			address = HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE;</div><div class='del'>-			break;</div><div class='del'>-		case  CHANNEL_SCAN_INDEX_CHROMATICITY_X:</div><div class='del'>-			report_id = als_state-&gt;als[chan-&gt;scan_index].report_id;</div><div class='del'>-			min = als_state-&gt;als[chan-&gt;scan_index].logical_minimum;</div><div class='del'>-			address = HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X;</div><div class='del'>-			break;</div><div class='del'>-		case  CHANNEL_SCAN_INDEX_CHROMATICITY_Y:</div><div class='del'>-			report_id = als_state-&gt;als[chan-&gt;scan_index].report_id;</div><div class='del'>-			min = als_state-&gt;als[chan-&gt;scan_index].logical_minimum;</div><div class='del'>-			address = HID_USAGE_SENSOR_LIGHT_CHROMATICITY_Y;</div><div class='del'>-			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			report_id = -1;</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -275,18 +223,6 @@ static int als_capture_sample(struct hid_sensor_hub_device *hsdev,</div><div class='ctx'> 		als_state-&gt;scan.illum[CHANNEL_SCAN_INDEX_ILLUM] = sample_data;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 		break;</div><div class='del'>-	case HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE:</div><div class='del'>-		als_state-&gt;scan.illum[CHANNEL_SCAN_INDEX_COLOR_TEMP] = sample_data;</div><div class='del'>-		ret = 0;</div><div class='del'>-		break;</div><div class='del'>-	case HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X:</div><div class='del'>-		als_state-&gt;scan.illum[CHANNEL_SCAN_INDEX_CHROMATICITY_X] = sample_data;</div><div class='del'>-		ret = 0;</div><div class='del'>-		break;</div><div class='del'>-	case HID_USAGE_SENSOR_LIGHT_CHROMATICITY_Y:</div><div class='del'>-		als_state-&gt;scan.illum[CHANNEL_SCAN_INDEX_CHROMATICITY_Y] = sample_data;</div><div class='del'>-		ret = 0;</div><div class='del'>-		break;</div><div class='ctx'> 	case HID_USAGE_SENSOR_TIME_TIMESTAMP:</div><div class='ctx'> 		als_state-&gt;timestamp = hid_sensor_convert_timestamp(&amp;als_state-&gt;common_attributes,</div><div class='ctx'> 								    *(s64 *)raw_data);</div><div class='hunk'>@@ -322,38 +258,6 @@ static int als_parse_report(struct platform_device *pdev,</div><div class='ctx'> 			st-&gt;als[i].report_id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = sensor_hub_input_get_attribute_info(hsdev, HID_INPUT_REPORT,</div><div class='del'>-				usage_id,</div><div class='del'>-				HID_USAGE_SENSOR_LIGHT_COLOR_TEMPERATURE,</div><div class='del'>-				&amp;st-&gt;als[CHANNEL_SCAN_INDEX_COLOR_TEMP]);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='del'>-	als_adjust_channel_bit_mask(channels, CHANNEL_SCAN_INDEX_COLOR_TEMP,</div><div class='del'>-				st-&gt;als[CHANNEL_SCAN_INDEX_COLOR_TEMP].size);</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;pdev-&gt;dev, "als %x:%x\n",</div><div class='del'>-		st-&gt;als[CHANNEL_SCAN_INDEX_COLOR_TEMP].index,</div><div class='del'>-		st-&gt;als[CHANNEL_SCAN_INDEX_COLOR_TEMP].report_id);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 2; i++) {</div><div class='del'>-		int next_scan_index = CHANNEL_SCAN_INDEX_CHROMATICITY_X + i;</div><div class='del'>-</div><div class='del'>-		ret = sensor_hub_input_get_attribute_info(hsdev,</div><div class='del'>-				HID_INPUT_REPORT, usage_id,</div><div class='del'>-				HID_USAGE_SENSOR_LIGHT_CHROMATICITY_X + i,</div><div class='del'>-				&amp;st-&gt;als[next_scan_index]);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		als_adjust_channel_bit_mask(channels,</div><div class='del'>-					CHANNEL_SCAN_INDEX_CHROMATICITY_X + i,</div><div class='del'>-					st-&gt;als[next_scan_index].size);</div><div class='del'>-</div><div class='del'>-		dev_dbg(&amp;pdev-&gt;dev, "als %x:%x\n",</div><div class='del'>-			st-&gt;als[next_scan_index].index,</div><div class='del'>-			st-&gt;als[next_scan_index].report_id);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	st-&gt;scale_precision = hid_sensor_format_scale(usage_id,</div><div class='ctx'> 				&amp;st-&gt;als[CHANNEL_SCAN_INDEX_INTENSITY],</div><div class='ctx'> 				&amp;st-&gt;scale_pre_decml, &amp;st-&gt;scale_post_decml);</div><div class='head'>diff --git a/drivers/iio/light/isl76682.c b/drivers/iio/light/isl76682.c<br/>new file mode 100644<br/>index 000000000000..cf6ddee44ffc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/isl76682.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/isl76682.c</a></div><div class='hunk'>@@ -0,0 +1,345 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * IIO driver for the light sensor ISL76682.</div><div class='add'>+ * ISL76682 is Ambient Light Sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Marek Vasut &lt;marex@denx.de&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/array_size.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#define ISL76682_REG_COMMAND			0x00</div><div class='add'>+</div><div class='add'>+#define ISL76682_COMMAND_EN			BIT(7)</div><div class='add'>+#define ISL76682_COMMAND_MODE_CONTINUOUS	BIT(6)</div><div class='add'>+#define ISL76682_COMMAND_LIGHT_IR		BIT(5)</div><div class='add'>+</div><div class='add'>+#define ISL76682_COMMAND_RANGE_LUX_1K		0x0</div><div class='add'>+#define ISL76682_COMMAND_RANGE_LUX_4K		0x1</div><div class='add'>+#define ISL76682_COMMAND_RANGE_LUX_16K		0x2</div><div class='add'>+#define ISL76682_COMMAND_RANGE_LUX_64K		0x3</div><div class='add'>+#define ISL76682_COMMAND_RANGE_LUX_MASK		GENMASK(1, 0)</div><div class='add'>+</div><div class='add'>+#define ISL76682_REG_ALSIR_L			0x01</div><div class='add'>+</div><div class='add'>+#define ISL76682_REG_ALSIR_U			0x02</div><div class='add'>+</div><div class='add'>+#define ISL76682_NUM_REGS			(ISL76682_REG_ALSIR_U + 1)</div><div class='add'>+</div><div class='add'>+#define ISL76682_CONV_TIME_MS			100</div><div class='add'>+#define ISL76682_INT_TIME_US			90000</div><div class='add'>+</div><div class='add'>+#define ISL76682_ADC_MAX			(BIT(16) - 1)</div><div class='add'>+</div><div class='add'>+struct isl76682_chip {</div><div class='add'>+	/*</div><div class='add'>+	 * Lock to synchronize access to device command register</div><div class='add'>+	 * and the content of range variable below.</div><div class='add'>+	 */</div><div class='add'>+	struct mutex			lock;</div><div class='add'>+	struct regmap			*regmap;</div><div class='add'>+	u8				range;</div><div class='add'>+	u8				command;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct isl76682_range {</div><div class='add'>+	u8				range;</div><div class='add'>+	u32				als;</div><div class='add'>+	u32				ir;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct isl76682_range isl76682_range_table[] = {</div><div class='add'>+	{ ISL76682_COMMAND_RANGE_LUX_1K, 15000, 10500 },</div><div class='add'>+	{ ISL76682_COMMAND_RANGE_LUX_4K, 60000, 42000 },</div><div class='add'>+	{ ISL76682_COMMAND_RANGE_LUX_16K, 240000, 168000 },</div><div class='add'>+	{ ISL76682_COMMAND_RANGE_LUX_64K, 960000, 673000 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isl76682_get(struct isl76682_chip *chip, bool mode_ir, int *data)</div><div class='add'>+{</div><div class='add'>+	u8 command;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	command = ISL76682_COMMAND_EN | ISL76682_COMMAND_MODE_CONTINUOUS |</div><div class='add'>+		  chip-&gt;range;</div><div class='add'>+</div><div class='add'>+	if (mode_ir)</div><div class='add'>+		command |= ISL76682_COMMAND_LIGHT_IR;</div><div class='add'>+</div><div class='add'>+	if (command != chip-&gt;command) {</div><div class='add'>+		ret = regmap_write(chip-&gt;regmap, ISL76682_REG_COMMAND, command);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/* Need to wait for conversion time if ALS/IR mode enabled */</div><div class='add'>+		msleep(ISL76682_CONV_TIME_MS);</div><div class='add'>+</div><div class='add'>+		chip-&gt;command = command;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = regmap_bulk_read(chip-&gt;regmap, ISL76682_REG_ALSIR_L, data, 2);</div><div class='add'>+	*data &amp;= ISL76682_ADC_MAX;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isl76682_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			      struct iio_chan_spec const *chan,</div><div class='add'>+			      int val, int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct isl76682_chip *chip = iio_priv(indio_dev);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (mask != IIO_CHAN_INFO_SCALE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (val != 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(isl76682_range_table); i++) {</div><div class='add'>+		if (chan-&gt;type == IIO_LIGHT &amp;&amp; val2 != isl76682_range_table[i].als)</div><div class='add'>+			continue;</div><div class='add'>+		if (chan-&gt;type == IIO_INTENSITY &amp;&amp; val2 != isl76682_range_table[i].ir)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		scoped_guard(mutex, &amp;chip-&gt;lock)</div><div class='add'>+			chip-&gt;range = isl76682_range_table[i].range;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int isl76682_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     int *val, int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct isl76682_chip *chip = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;chip-&gt;lock);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_LIGHT:</div><div class='add'>+			ret = isl76682_get(chip, false, val);</div><div class='add'>+			return (ret &lt; 0) ? ret : IIO_VAL_INT;</div><div class='add'>+		case IIO_INTENSITY:</div><div class='add'>+			ret = isl76682_get(chip, true, val);</div><div class='add'>+			return (ret &lt; 0) ? ret : IIO_VAL_INT;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(isl76682_range_table); i++) {</div><div class='add'>+			if (chip-&gt;range != isl76682_range_table[i].range)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			*val = 0;</div><div class='add'>+			switch (chan-&gt;type) {</div><div class='add'>+			case IIO_LIGHT:</div><div class='add'>+				*val2 = isl76682_range_table[i].als;</div><div class='add'>+				return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+			case IIO_INTENSITY:</div><div class='add'>+				*val2 = isl76682_range_table[i].ir;</div><div class='add'>+				return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+			default:</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	case IIO_CHAN_INFO_INT_TIME:</div><div class='add'>+		*val = 0;</div><div class='add'>+		*val2 = ISL76682_INT_TIME_US;</div><div class='add'>+		return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int illuminance_scale_available[] = {</div><div class='add'>+	0, 15000,</div><div class='add'>+	0, 60000,</div><div class='add'>+	0, 240000,</div><div class='add'>+	0, 960000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int intensity_scale_available[] = {</div><div class='add'>+	0, 10500,</div><div class='add'>+	0, 42000,</div><div class='add'>+	0, 168000,</div><div class='add'>+	0, 673000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isl76682_read_avail(struct iio_dev *indio_dev,</div><div class='add'>+			       struct iio_chan_spec const *chan,</div><div class='add'>+			       const int **vals, int *type,</div><div class='add'>+			       int *length, long mask)</div><div class='add'>+{</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_LIGHT:</div><div class='add'>+			*vals = illuminance_scale_available;</div><div class='add'>+			*length = ARRAY_SIZE(illuminance_scale_available);</div><div class='add'>+			*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+			return IIO_AVAIL_LIST;</div><div class='add'>+		case IIO_INTENSITY:</div><div class='add'>+			*vals = intensity_scale_available;</div><div class='add'>+			*length = ARRAY_SIZE(intensity_scale_available);</div><div class='add'>+			*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+			return IIO_AVAIL_LIST;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec isl76682_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_LIGHT,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+	}, {</div><div class='add'>+		.type = IIO_INTENSITY,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_info isl76682_info = {</div><div class='add'>+	.read_avail	= isl76682_read_avail,</div><div class='add'>+	.read_raw	= isl76682_read_raw,</div><div class='add'>+	.write_raw	= isl76682_write_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isl76682_clear_configure_reg(struct isl76682_chip *chip)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = regmap_get_device(chip-&gt;regmap);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write(chip-&gt;regmap, ISL76682_REG_COMMAND, 0x0);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(dev, "Error %d clearing the CONFIGURE register\n", ret);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * In the success case, the command register was zeroed out.</div><div class='add'>+	 *</div><div class='add'>+	 * In the error case, we do not know in which state the command</div><div class='add'>+	 * register is, so we assume it is zeroed out, so that it would</div><div class='add'>+	 * be reprogrammed at the next data read out, and at that time</div><div class='add'>+	 * we hope it would be reprogrammed successfully. That is very</div><div class='add'>+	 * much a best effort approach.</div><div class='add'>+	 */</div><div class='add'>+	chip-&gt;command = 0;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void isl76682_reset_action(void *chip)</div><div class='add'>+{</div><div class='add'>+	isl76682_clear_configure_reg(chip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool isl76682_is_volatile_reg(struct device *dev, unsigned int reg)</div><div class='add'>+{</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case ISL76682_REG_ALSIR_L:</div><div class='add'>+	case ISL76682_REG_ALSIR_U:</div><div class='add'>+		return true;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct regmap_config isl76682_regmap_config = {</div><div class='add'>+	.reg_bits		= 8,</div><div class='add'>+	.val_bits		= 8,</div><div class='add'>+	.volatile_reg		= isl76682_is_volatile_reg,</div><div class='add'>+	.max_register		= ISL76682_NUM_REGS - 1,</div><div class='add'>+	.num_reg_defaults_raw	= ISL76682_NUM_REGS,</div><div class='add'>+	.cache_type		= REGCACHE_FLAT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int isl76682_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct isl76682_chip *chip;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*chip));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	chip = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;chip-&gt;lock);</div><div class='add'>+</div><div class='add'>+	chip-&gt;regmap = devm_regmap_init_i2c(client, &amp;isl76682_regmap_config);</div><div class='add'>+	ret = PTR_ERR_OR_ZERO(chip-&gt;regmap);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "Error initializing regmap\n");</div><div class='add'>+</div><div class='add'>+	chip-&gt;range = ISL76682_COMMAND_RANGE_LUX_1K;</div><div class='add'>+</div><div class='add'>+	ret = isl76682_clear_configure_reg(chip);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_add_action_or_reset(dev, isl76682_reset_action, chip);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;info = &amp;isl76682_info;</div><div class='add'>+	indio_dev-&gt;channels = isl76682_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(isl76682_channels);</div><div class='add'>+	indio_dev-&gt;name = "isl76682";</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id isl76682_id[] = {</div><div class='add'>+	{ "isl76682" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, isl76682_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id isl76682_of_match[] = {</div><div class='add'>+	{ .compatible = "isil,isl76682" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, isl76682_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver isl76682_driver = {</div><div class='add'>+	.driver  = {</div><div class='add'>+		.name		= "isl76682",</div><div class='add'>+		.of_match_table	= isl76682_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe		= isl76682_probe,</div><div class='add'>+	.id_table	= isl76682_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(isl76682_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("ISL76682 Ambient Light Sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_AUTHOR("Marek Vasut &lt;marex@denx.de&gt;");</div><div class='head'>diff --git a/drivers/iio/light/ltr390.c b/drivers/iio/light/ltr390.c<br/>new file mode 100644<br/>index 000000000000..fff1e899097d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/ltr390.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/ltr390.c</a></div><div class='hunk'>@@ -0,0 +1,196 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * IIO driver for Lite-On LTR390 ALS and UV sensor</div><div class='add'>+ * (7-bit I2C slave address 0x53)</div><div class='add'>+ *</div><div class='add'>+ * Based on the work of:</div><div class='add'>+ *   Shreeya Patel and Shi Zhigang (LTRF216 Driver)</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Anshul Dalal &lt;anshulusr@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet:</div><div class='add'>+ *   https://optoelectronics.liteon.com/upload/download/DS86-2015-0004/LTR-390UV_Final_%20DS_V1%201.pdf</div><div class='add'>+ *</div><div class='add'>+ * TODO:</div><div class='add'>+ *   - Support for configurable gain and resolution</div><div class='add'>+ *   - Sensor suspend/resume support</div><div class='add'>+ *   - Add support for reading the ALS</div><div class='add'>+ *   - Interrupt support</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/math.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#define LTR390_MAIN_CTRL      0x00</div><div class='add'>+#define LTR390_PART_ID	      0x06</div><div class='add'>+#define LTR390_UVS_DATA	      0x10</div><div class='add'>+</div><div class='add'>+#define LTR390_SW_RESET	      BIT(4)</div><div class='add'>+#define LTR390_UVS_MODE	      BIT(3)</div><div class='add'>+#define LTR390_SENSOR_ENABLE  BIT(1)</div><div class='add'>+</div><div class='add'>+#define LTR390_PART_NUMBER_ID 0xb</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * At 20-bit resolution (integration time: 400ms) and 18x gain, 2300 counts of</div><div class='add'>+ * the sensor are equal to 1 UV Index [Datasheet Page#8].</div><div class='add'>+ *</div><div class='add'>+ * For the default resolution of 18-bit (integration time: 100ms) and default</div><div class='add'>+ * gain of 3x, the counts/uvi are calculated as follows:</div><div class='add'>+ * 2300 / ((3/18) * (100/400)) = 95.83</div><div class='add'>+ */</div><div class='add'>+#define LTR390_COUNTS_PER_UVI 96</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Window Factor is needed when the device is under Window glass with coated</div><div class='add'>+ * tinted ink. This is to compensate for the light loss due to the lower</div><div class='add'>+ * transmission rate of the window glass and helps * in calculating lux.</div><div class='add'>+ */</div><div class='add'>+#define LTR390_WINDOW_FACTOR 1</div><div class='add'>+</div><div class='add'>+struct ltr390_data {</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+	/* Protects device from simulataneous reads */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config ltr390_regmap_config = {</div><div class='add'>+	.name = "ltr390",</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.reg_stride = 1,</div><div class='add'>+	.val_bits = 8,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ltr390_register_read(struct ltr390_data *data, u8 register_address)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;data-&gt;client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+	u8 recieve_buffer[3];</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ret = regmap_bulk_read(data-&gt;regmap, register_address, recieve_buffer,</div><div class='add'>+			       sizeof(recieve_buffer));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to read measurement data");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return get_unaligned_le24(recieve_buffer);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ltr390_read_raw(struct iio_dev *iio_device,</div><div class='add'>+			   struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			   int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct ltr390_data *data = iio_priv(iio_device);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		ret = ltr390_register_read(data, LTR390_UVS_DATA);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+		*val = ret;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		*val = LTR390_WINDOW_FACTOR;</div><div class='add'>+		*val2 = LTR390_COUNTS_PER_UVI;</div><div class='add'>+		return IIO_VAL_FRACTIONAL;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info ltr390_info = {</div><div class='add'>+	.read_raw = ltr390_read_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec ltr390_channel = {</div><div class='add'>+	.type = IIO_UVINDEX,</div><div class='add'>+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ltr390_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct ltr390_data *data;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	int ret, part_number;</div><div class='add'>+</div><div class='add'>+	dev = &amp;client-&gt;dev;</div><div class='add'>+	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	data-&gt;regmap = devm_regmap_init_i2c(client, &amp;ltr390_regmap_config);</div><div class='add'>+	if (IS_ERR(data-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(data-&gt;regmap),</div><div class='add'>+				     "regmap initialization failed\n");</div><div class='add'>+</div><div class='add'>+	data-&gt;client = client;</div><div class='add'>+	mutex_init(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;info = &amp;ltr390_info;</div><div class='add'>+	indio_dev-&gt;channels = &amp;ltr390_channel;</div><div class='add'>+	indio_dev-&gt;num_channels = 1;</div><div class='add'>+	indio_dev-&gt;name = "ltr390";</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, LTR390_PART_ID, &amp;part_number);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+				     "failed to get sensor's part id\n");</div><div class='add'>+	/* Lower 4 bits of `part_number` change with hardware revisions */</div><div class='add'>+	if (part_number &gt;&gt; 4 != LTR390_PART_NUMBER_ID)</div><div class='add'>+		dev_info(dev, "received invalid product id: 0x%x", part_number);</div><div class='add'>+	dev_dbg(dev, "LTR390, product id: 0x%x\n", part_number);</div><div class='add'>+</div><div class='add'>+	/* reset sensor, chip fails to respond to this, so ignore any errors */</div><div class='add'>+	regmap_set_bits(data-&gt;regmap, LTR390_MAIN_CTRL, LTR390_SW_RESET);</div><div class='add'>+</div><div class='add'>+	/* Wait for the registers to reset before proceeding */</div><div class='add'>+	usleep_range(1000, 2000);</div><div class='add'>+</div><div class='add'>+	ret = regmap_set_bits(data-&gt;regmap, LTR390_MAIN_CTRL,</div><div class='add'>+			      LTR390_SENSOR_ENABLE | LTR390_UVS_MODE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "failed to enable the sensor\n");</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id ltr390_id[] = {</div><div class='add'>+	{ "ltr390" },</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, ltr390_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ltr390_of_table[] = {</div><div class='add'>+	{ .compatible = "liteon,ltr390" },</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ltr390_of_table);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver ltr390_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "ltr390",</div><div class='add'>+		.of_match_table = ltr390_of_table,</div><div class='add'>+	},</div><div class='add'>+	.probe = ltr390_probe,</div><div class='add'>+	.id_table = ltr390_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(ltr390_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Anshul Dalal &lt;anshulusr@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Lite-On LTR390 ALS and UV sensor Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/light/ltrf216a.c b/drivers/iio/light/ltrf216a.c<br/>index 8de4dd849936..68dc48420a88 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/ltrf216a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/ltrf216a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/ltrf216a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/ltrf216a.c</a></div><div class='hunk'>@@ -234,7 +234,7 @@ static int ltrf216a_read_data(struct ltrf216a_data *data, u8 addr)</div><div class='ctx'> static int ltrf216a_get_lux(struct ltrf216a_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	int ret, greendata;</div><div class='del'>-	u64 lux, div;</div><div class='add'>+	u64 lux;</div><div class='ctx'> </div><div class='ctx'> 	ret = ltrf216a_set_power_state(data, true);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -246,10 +246,9 @@ static int ltrf216a_get_lux(struct ltrf216a_data *data)</div><div class='ctx'> </div><div class='ctx'> 	ltrf216a_set_power_state(data, false);</div><div class='ctx'> </div><div class='del'>-	lux = greendata * 45 * LTRF216A_WIN_FAC * 100;</div><div class='del'>-	div = data-&gt;als_gain_fac * data-&gt;int_time_fac * 100;</div><div class='add'>+	lux = greendata * 45 * LTRF216A_WIN_FAC;</div><div class='ctx'> </div><div class='del'>-	return div_u64(lux, div);</div><div class='add'>+	return lux;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ltrf216a_read_raw(struct iio_dev *indio_dev,</div><div class='hunk'>@@ -279,7 +278,8 @@ static int ltrf216a_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		*val = ret;</div><div class='del'>-		return IIO_VAL_INT;</div><div class='add'>+		*val2 = data-&gt;als_gain_fac * data-&gt;int_time_fac;</div><div class='add'>+		return IIO_VAL_FRACTIONAL;</div><div class='ctx'> 	case IIO_CHAN_INFO_INT_TIME:</div><div class='ctx'> 		mutex_lock(&amp;data-&gt;lock);</div><div class='ctx'> 		ret = ltrf216a_get_int_time(data, val, val2);</div><div class='head'>diff --git a/drivers/iio/light/pa12203001.c b/drivers/iio/light/pa12203001.c<br/>index ed241598aefb..636432c45651 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/pa12203001.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/pa12203001.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/pa12203001.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/pa12203001.c</a></div><div class='hunk'>@@ -472,7 +472,7 @@ static struct i2c_driver pa12203001_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = PA12203001_DRIVER_NAME,</div><div class='ctx'> 		.pm = &amp;pa12203001_pm_ops,</div><div class='del'>-		.acpi_match_table = ACPI_PTR(pa12203001_acpi_match),</div><div class='add'>+		.acpi_match_table = pa12203001_acpi_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = pa12203001_probe,</div><div class='ctx'> 	.remove = pa12203001_remove,</div><div class='head'>diff --git a/drivers/iio/light/rohm-bu27008.c b/drivers/iio/light/rohm-bu27008.c<br/>index 6a6d77805091..0f010eff1981 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/light/rohm-bu27008.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/light/rohm-bu27008.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/rohm-bu27008.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/rohm-bu27008.c</a></div><div class='hunk'>@@ -130,6 +130,7 @@</div><div class='ctx'>  * @BU27008_BLUE:	Blue channel. Via data2 (when used).</div><div class='ctx'>  * @BU27008_CLEAR:	Clear channel. Via data2 or data3 (when used).</div><div class='ctx'>  * @BU27008_IR:		IR channel. Via data3 (when used).</div><div class='add'>+ * @BU27008_LUX:	Illuminance channel, computed using RGB and IR.</div><div class='ctx'>  * @BU27008_NUM_CHANS:	Number of channel types.</div><div class='ctx'>  */</div><div class='ctx'> enum bu27008_chan_type {</div><div class='hunk'>@@ -138,6 +139,7 @@ enum bu27008_chan_type {</div><div class='ctx'> 	BU27008_BLUE,</div><div class='ctx'> 	BU27008_CLEAR,</div><div class='ctx'> 	BU27008_IR,</div><div class='add'>+	BU27008_LUX,</div><div class='ctx'> 	BU27008_NUM_CHANS</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -172,6 +174,8 @@ static const unsigned long bu27008_scan_masks[] = {</div><div class='ctx'> 	ALWAYS_SCANNABLE | BIT(BU27008_CLEAR) | BIT(BU27008_IR),</div><div class='ctx'> 	/* buffer is R, G, B, IR */</div><div class='ctx'> 	ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_IR),</div><div class='add'>+	/* buffer is R, G, B, IR, LUX */</div><div class='add'>+	ALWAYS_SCANNABLE | BIT(BU27008_BLUE) | BIT(BU27008_IR) | BIT(BU27008_LUX),</div><div class='ctx'> 	0</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -331,6 +335,19 @@ static const struct iio_chan_spec bu27008_channels[] = {</div><div class='ctx'> 	 * Hence we don't advertise available ones either.</div><div class='ctx'> 	 */</div><div class='ctx'> 	BU27008_CHAN(IR, DATA3, 0),</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_LIGHT,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.channel = BU27008_LUX,</div><div class='add'>+		.scan_index = BU27008_LUX,</div><div class='add'>+		.scan_type = {</div><div class='add'>+			.sign = 'u',</div><div class='add'>+			.realbits = 64,</div><div class='add'>+			.storagebits = 64,</div><div class='add'>+			.endianness = IIO_CPU,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='ctx'> 	IIO_CHAN_SOFT_TIMESTAMP(BU27008_NUM_CHANS),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1004,6 +1021,169 @@ static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define BU27008_LUX_DATA_RED	0</div><div class='add'>+#define BU27008_LUX_DATA_GREEN	1</div><div class='add'>+#define BU27008_LUX_DATA_BLUE	2</div><div class='add'>+#define BU27008_LUX_DATA_IR	3</div><div class='add'>+#define LUX_DATA_SIZE (BU27008_NUM_HW_CHANS * sizeof(__le16))</div><div class='add'>+</div><div class='add'>+static int bu27008_read_lux_chans(struct bu27008_data *data, unsigned int time,</div><div class='add'>+				  __le16 *chan_data)</div><div class='add'>+{</div><div class='add'>+	int ret, chan_sel, tmpret, valid;</div><div class='add'>+</div><div class='add'>+	chan_sel = BU27008_BLUE2_IR3 &lt;&lt; (ffs(data-&gt;cd-&gt;chan_sel_mask) - 1);</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(data-&gt;regmap, data-&gt;cd-&gt;chan_sel_reg,</div><div class='add'>+				 data-&gt;cd-&gt;chan_sel_mask, chan_sel);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_meas_set(data, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	msleep(time / USEC_PER_MSEC);</div><div class='add'>+</div><div class='add'>+	ret = regmap_read_poll_timeout(data-&gt;regmap, data-&gt;cd-&gt;valid_reg,</div><div class='add'>+				       valid, (valid &amp; BU27008_MASK_VALID),</div><div class='add'>+				       BU27008_VALID_RESULT_WAIT_QUANTA_US,</div><div class='add'>+				       BU27008_MAX_VALID_RESULT_WAIT_US);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	ret = regmap_bulk_read(data-&gt;regmap, BU27008_REG_DATA0_LO, chan_data,</div><div class='add'>+			       LUX_DATA_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out;</div><div class='add'>+out:</div><div class='add'>+	tmpret = bu27008_meas_set(data, false);</div><div class='add'>+	if (tmpret)</div><div class='add'>+		dev_warn(data-&gt;dev, "Stopping measurement failed\n");</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Following equation for computing lux out of register values was given by</div><div class='add'>+ * ROHM HW colleagues;</div><div class='add'>+ *</div><div class='add'>+ * Red = RedData*1024 / Gain * 20 / meas_mode</div><div class='add'>+ * Green = GreenData* 1024 / Gain * 20 / meas_mode</div><div class='add'>+ * Blue = BlueData* 1024 / Gain * 20 / meas_mode</div><div class='add'>+ * IR = IrData* 1024 / Gain * 20 / meas_mode</div><div class='add'>+ *</div><div class='add'>+ * where meas_mode is the integration time in mS / 10</div><div class='add'>+ *</div><div class='add'>+ * IRratio = (IR &gt; 0.18 * Green) ? 0 : 1</div><div class='add'>+ *</div><div class='add'>+ * Lx = max(c1*Red + c2*Green + c3*Blue,0)</div><div class='add'>+ *</div><div class='add'>+ * for</div><div class='add'>+ * IRratio 0: c1 = -0.00002237, c2 = 0.0003219, c3 = -0.000120371</div><div class='add'>+ * IRratio 1: c1 = -0.00001074, c2 = 0.000305415, c3 = -0.000129367</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The max chan data is 0xffff. When we multiply it by 1024 * 20, we'll get</div><div class='add'>+ * 0x4FFFB000 which still fits in 32-bit integer. This won't overflow.</div><div class='add'>+ */</div><div class='add'>+#define NORM_CHAN_DATA_FOR_LX_CALC(chan, gain, time) (le16_to_cpu(chan) * \</div><div class='add'>+				   1024 * 20 / (gain) / (time))</div><div class='add'>+static u64 bu27008_calc_nlux(struct bu27008_data *data, __le16 *lux_data,</div><div class='add'>+		unsigned int gain, unsigned int gain_ir, unsigned int time)</div><div class='add'>+{</div><div class='add'>+	unsigned int red, green, blue, ir;</div><div class='add'>+	s64 c1, c2, c3, nlux;</div><div class='add'>+</div><div class='add'>+	time /= 10000;</div><div class='add'>+	ir = NORM_CHAN_DATA_FOR_LX_CALC(lux_data[BU27008_LUX_DATA_IR], gain_ir, time);</div><div class='add'>+	red = NORM_CHAN_DATA_FOR_LX_CALC(lux_data[BU27008_LUX_DATA_RED], gain, time);</div><div class='add'>+	green = NORM_CHAN_DATA_FOR_LX_CALC(lux_data[BU27008_LUX_DATA_GREEN], gain, time);</div><div class='add'>+	blue = NORM_CHAN_DATA_FOR_LX_CALC(lux_data[BU27008_LUX_DATA_BLUE], gain, time);</div><div class='add'>+</div><div class='add'>+	if ((u64)ir * 100LLU &gt; (u64)green * 18LLU) {</div><div class='add'>+		c1 = -22370;</div><div class='add'>+		c2 = 321900;</div><div class='add'>+		c3 = -120371;</div><div class='add'>+	} else {</div><div class='add'>+		c1 = -10740;</div><div class='add'>+		c2 = 305415;</div><div class='add'>+		c3 = -129367;</div><div class='add'>+	}</div><div class='add'>+	nlux = c1 * red + c2 * green + c3 * blue;</div><div class='add'>+</div><div class='add'>+	return max_t(s64, 0, nlux);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bu27008_get_time_n_gains(struct bu27008_data *data,</div><div class='add'>+		unsigned int *gain, unsigned int *gain_ir, unsigned int *time)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_get_gain(data, &amp;data-&gt;gts, gain);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_get_gain(data, &amp;data-&gt;gts_ir, gain_ir);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_get_int_time_us(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Max integration time is 400000. Fits in signed int. */</div><div class='add'>+	*time = ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct bu27008_buf {</div><div class='add'>+	__le16 chan[BU27008_NUM_HW_CHANS];</div><div class='add'>+	u64 lux __aligned(8);</div><div class='add'>+	s64 ts __aligned(8);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int bu27008_buffer_fill_lux(struct bu27008_data *data,</div><div class='add'>+				   struct bu27008_buf *raw)</div><div class='add'>+{</div><div class='add'>+	unsigned int gain, gain_ir, time;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_get_time_n_gains(data, &amp;gain, &amp;gain_ir, &amp;time);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	raw-&gt;lux = bu27008_calc_nlux(data, raw-&gt;chan, gain, gain_ir, time);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bu27008_read_lux(struct bu27008_data *data, struct iio_dev *idev,</div><div class='add'>+			    struct iio_chan_spec const *chan,</div><div class='add'>+			    int *val, int *val2)</div><div class='add'>+{</div><div class='add'>+	__le16 lux_data[BU27008_NUM_HW_CHANS];</div><div class='add'>+	unsigned int gain, gain_ir, time;</div><div class='add'>+	u64 nlux;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_get_time_n_gains(data, &amp;gain, &amp;gain_ir, &amp;time);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = bu27008_read_lux_chans(data, time, lux_data);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	nlux = bu27008_calc_nlux(data, lux_data, gain, gain_ir, time);</div><div class='add'>+	*val = (int)nlux;</div><div class='add'>+	*val2 = nlux &gt;&gt; 32LLU;</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT_64;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int bu27008_read_raw(struct iio_dev *idev,</div><div class='ctx'> 			   struct iio_chan_spec const *chan,</div><div class='ctx'> 			   int *val, int *val2, long mask)</div><div class='hunk'>@@ -1018,7 +1198,10 @@ static int bu27008_read_raw(struct iio_dev *idev,</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;data-&gt;mutex);</div><div class='del'>-		ret = bu27008_read_one(data, idev, chan, val, val2);</div><div class='add'>+		if (chan-&gt;type == IIO_LIGHT)</div><div class='add'>+			ret = bu27008_read_lux(data, idev, chan, val, val2);</div><div class='add'>+		else</div><div class='add'>+			ret = bu27008_read_one(data, idev, chan, val, val2);</div><div class='ctx'> 		mutex_unlock(&amp;data-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 		iio_device_release_direct_mode(idev);</div><div class='hunk'>@@ -1026,6 +1209,11 @@ static int bu27008_read_raw(struct iio_dev *idev,</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		if (chan-&gt;type == IIO_LIGHT) {</div><div class='add'>+			*val = 0;</div><div class='add'>+			*val2 = 1;</div><div class='add'>+			return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+		}</div><div class='ctx'> 		ret = bu27008_get_scale(data, chan-&gt;scan_index == BU27008_IR,</div><div class='ctx'> 					val, val2);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -1236,10 +1424,7 @@ static irqreturn_t bu27008_trigger_handler(int irq, void *p)</div><div class='ctx'> 	struct iio_poll_func *pf = p;</div><div class='ctx'> 	struct iio_dev *idev = pf-&gt;indio_dev;</div><div class='ctx'> 	struct bu27008_data *data = iio_priv(idev);</div><div class='del'>-	struct {</div><div class='del'>-		__le16 chan[BU27008_NUM_HW_CHANS];</div><div class='del'>-		s64 ts __aligned(8);</div><div class='del'>-	} raw;</div><div class='add'>+	struct bu27008_buf raw;</div><div class='ctx'> 	int ret, dummy;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;raw, 0, sizeof(raw));</div><div class='hunk'>@@ -1257,6 +1442,12 @@ static irqreturn_t bu27008_trigger_handler(int irq, void *p)</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto err_read;</div><div class='ctx'> </div><div class='add'>+	if (test_bit(BU27008_LUX, idev-&gt;active_scan_mask)) {</div><div class='add'>+		ret = bu27008_buffer_fill_lux(data, &amp;raw);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_read;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	iio_push_to_buffers_with_timestamp(idev, &amp;raw, pf-&gt;timestamp);</div><div class='ctx'> err_read:</div><div class='ctx'> 	iio_trigger_notify_done(idev-&gt;trig);</div><div class='head'>diff --git a/drivers/iio/light/veml6075.c b/drivers/iio/light/veml6075.c<br/>new file mode 100644<br/>index 000000000000..05d4c0e9015d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/light/veml6075.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/light/veml6075.c</a></div><div class='hunk'>@@ -0,0 +1,474 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Vishay VEML6075 UVA and UVB light sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 Javier Carrasco &lt;javier.carrasco.cruz@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * 7-bit I2C slave, address 0x10</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#define VEML6075_CMD_CONF	0x00 /* configuration register */</div><div class='add'>+#define VEML6075_CMD_UVA	0x07 /* UVA channel */</div><div class='add'>+#define VEML6075_CMD_UVB	0x09 /* UVB channel */</div><div class='add'>+#define VEML6075_CMD_COMP1	0x0A /* visible light compensation */</div><div class='add'>+#define VEML6075_CMD_COMP2	0x0B /* infrarred light compensation */</div><div class='add'>+#define VEML6075_CMD_ID		0x0C /* device ID */</div><div class='add'>+</div><div class='add'>+#define VEML6075_CONF_IT	GENMASK(6, 4) /* intregration time */</div><div class='add'>+#define VEML6075_CONF_HD	BIT(3) /* dynamic setting */</div><div class='add'>+#define VEML6075_CONF_TRIG	BIT(2) /* trigger */</div><div class='add'>+#define VEML6075_CONF_AF	BIT(1) /* active force enable */</div><div class='add'>+#define VEML6075_CONF_SD	BIT(0) /* shutdown */</div><div class='add'>+</div><div class='add'>+#define VEML6075_IT_50_MS	0x00</div><div class='add'>+#define VEML6075_IT_100_MS	0x01</div><div class='add'>+#define VEML6075_IT_200_MS	0x02</div><div class='add'>+#define VEML6075_IT_400_MS	0x03</div><div class='add'>+#define VEML6075_IT_800_MS	0x04</div><div class='add'>+</div><div class='add'>+#define VEML6075_AF_DISABLE	0x00</div><div class='add'>+#define VEML6075_AF_ENABLE	0x01</div><div class='add'>+</div><div class='add'>+#define VEML6075_SD_DISABLE	0x00</div><div class='add'>+#define VEML6075_SD_ENABLE	0x01</div><div class='add'>+</div><div class='add'>+/* Open-air coefficients and responsivity */</div><div class='add'>+#define VEML6075_A_COEF		2220</div><div class='add'>+#define VEML6075_B_COEF		1330</div><div class='add'>+#define VEML6075_C_COEF		2950</div><div class='add'>+#define VEML6075_D_COEF		1740</div><div class='add'>+#define VEML6075_UVA_RESP	1461</div><div class='add'>+#define VEML6075_UVB_RESP	2591</div><div class='add'>+</div><div class='add'>+static const int veml6075_it_ms[] = { 50, 100, 200, 400, 800 };</div><div class='add'>+</div><div class='add'>+struct veml6075_data {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	/*</div><div class='add'>+	 * prevent integration time modification and triggering</div><div class='add'>+	 * measurements while a measurement is underway.</div><div class='add'>+	 */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* channel number */</div><div class='add'>+enum veml6075_chan {</div><div class='add'>+	CH_UVA,</div><div class='add'>+	CH_UVB,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec veml6075_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_INTENSITY,</div><div class='add'>+		.channel = CH_UVA,</div><div class='add'>+		.modified = 1,</div><div class='add'>+		.channel2 = IIO_MOD_LIGHT_UVA,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+			BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_INTENSITY,</div><div class='add'>+		.channel = CH_UVB,</div><div class='add'>+		.modified = 1,</div><div class='add'>+		.channel2 = IIO_MOD_LIGHT_UVB,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+			BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_UVINDEX,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int veml6075_request_measurement(struct veml6075_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret, conf, int_time;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, VEML6075_CMD_CONF, &amp;conf);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* disable shutdown and trigger measurement */</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, VEML6075_CMD_CONF,</div><div class='add'>+			   (conf | VEML6075_CONF_TRIG) &amp; ~VEML6075_CONF_SD);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * A measurement requires between 1.30 and 1.40 times the integration</div><div class='add'>+	 * time for all possible configurations. Using a 1.50 factor simplifies</div><div class='add'>+	 * operations and ensures reliability under all circumstances.</div><div class='add'>+	 */</div><div class='add'>+	int_time = veml6075_it_ms[FIELD_GET(VEML6075_CONF_IT, conf)];</div><div class='add'>+	msleep(int_time + (int_time / 2));</div><div class='add'>+</div><div class='add'>+	/* shutdown again, data registers are still accessible */</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, VEML6075_CMD_CONF,</div><div class='add'>+				  VEML6075_CONF_SD, VEML6075_CONF_SD);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_uva_comp(int raw_uva, int comp1, int comp2)</div><div class='add'>+{</div><div class='add'>+	int comp1a_c, comp2a_c, uva_comp;</div><div class='add'>+</div><div class='add'>+	comp1a_c = (comp1 * VEML6075_A_COEF) / 1000U;</div><div class='add'>+	comp2a_c = (comp2 * VEML6075_B_COEF) / 1000U;</div><div class='add'>+	uva_comp = raw_uva - comp1a_c - comp2a_c;</div><div class='add'>+</div><div class='add'>+	return clamp_val(uva_comp, 0, U16_MAX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_uvb_comp(int raw_uvb, int comp1, int comp2)</div><div class='add'>+{</div><div class='add'>+	int comp1b_c, comp2b_c, uvb_comp;</div><div class='add'>+</div><div class='add'>+	comp1b_c = (comp1 * VEML6075_C_COEF) / 1000U;</div><div class='add'>+	comp2b_c = (comp2 * VEML6075_D_COEF) / 1000U;</div><div class='add'>+	uvb_comp = raw_uvb - comp1b_c - comp2b_c;</div><div class='add'>+</div><div class='add'>+	return clamp_val(uvb_comp, 0, U16_MAX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_comp(struct veml6075_data *data, int *c1, int *c2)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, VEML6075_CMD_COMP1, c1);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return regmap_read(data-&gt;regmap, VEML6075_CMD_COMP2, c2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_uv_direct(struct veml6075_data *data, int chan,</div><div class='add'>+				   int *val)</div><div class='add'>+{</div><div class='add'>+	int c1, c2, ret;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ret = veml6075_request_measurement(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = veml6075_read_comp(data, &amp;c1, &amp;c2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (chan) {</div><div class='add'>+	case CH_UVA:</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, VEML6075_CMD_UVA, val);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		*val = veml6075_uva_comp(*val, c1, c2);</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case CH_UVB:</div><div class='add'>+		ret = regmap_read(data-&gt;regmap, VEML6075_CMD_UVB, val);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		*val = veml6075_uvb_comp(*val, c1, c2);</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_int_time_index(struct veml6075_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret, conf;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, VEML6075_CMD_CONF, &amp;conf);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return FIELD_GET(VEML6075_CONF_IT, conf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_int_time_ms(struct veml6075_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	int int_index;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+	int_index = veml6075_read_int_time_index(data);</div><div class='add'>+	if (int_index &lt; 0)</div><div class='add'>+		return int_index;</div><div class='add'>+</div><div class='add'>+	*val = veml6075_it_ms[int_index];</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_get_uvi_micro(struct veml6075_data *data, int uva_comp,</div><div class='add'>+				  int uvb_comp)</div><div class='add'>+{</div><div class='add'>+	int uvia_micro = uva_comp * VEML6075_UVA_RESP;</div><div class='add'>+	int uvib_micro = uvb_comp * VEML6075_UVB_RESP;</div><div class='add'>+	int int_index;</div><div class='add'>+</div><div class='add'>+	int_index = veml6075_read_int_time_index(data);</div><div class='add'>+	if (int_index &lt; 0)</div><div class='add'>+		return int_index;</div><div class='add'>+</div><div class='add'>+	switch (int_index) {</div><div class='add'>+	case VEML6075_IT_50_MS:</div><div class='add'>+		return uvia_micro + uvib_micro;</div><div class='add'>+	case VEML6075_IT_100_MS:</div><div class='add'>+	case VEML6075_IT_200_MS:</div><div class='add'>+	case VEML6075_IT_400_MS:</div><div class='add'>+	case VEML6075_IT_800_MS:</div><div class='add'>+		return (uvia_micro + uvib_micro) / (2 &lt;&lt; int_index);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_uvi(struct veml6075_data *data, int *val, int *val2)</div><div class='add'>+{</div><div class='add'>+	int ret, c1, c2, uva, uvb, uvi_micro;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	ret = veml6075_request_measurement(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = veml6075_read_comp(data, &amp;c1, &amp;c2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, VEML6075_CMD_UVA, &amp;uva);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, VEML6075_CMD_UVB, &amp;uvb);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	uvi_micro = veml6075_get_uvi_micro(data, veml6075_uva_comp(uva, c1, c2),</div><div class='add'>+					   veml6075_uvb_comp(uvb, c1, c2));</div><div class='add'>+	if (uvi_micro &lt; 0)</div><div class='add'>+		return uvi_micro;</div><div class='add'>+</div><div class='add'>+	*val = uvi_micro / MICRO;</div><div class='add'>+	*val2 = uvi_micro % MICRO;</div><div class='add'>+</div><div class='add'>+	return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_responsivity(int chan, int *val, int *val2)</div><div class='add'>+{</div><div class='add'>+	/* scale = 1 / resp */</div><div class='add'>+	switch (chan) {</div><div class='add'>+	case CH_UVA:</div><div class='add'>+		/* resp = 0.93 c/uW/cm2: scale = 1.75268817 */</div><div class='add'>+		*val = 1;</div><div class='add'>+		*val2 = 75268817;</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+	case CH_UVB:</div><div class='add'>+		/* resp = 2.1 c/uW/cm2: scale = 0.476190476 */</div><div class='add'>+		*val = 0;</div><div class='add'>+		*val2 = 476190476;</div><div class='add'>+		return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_avail(struct iio_dev *indio_dev,</div><div class='add'>+			       struct iio_chan_spec const *chan,</div><div class='add'>+			       const int **vals, int *type, int *length,</div><div class='add'>+			       long mask)</div><div class='add'>+{</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_INT_TIME:</div><div class='add'>+		*length = ARRAY_SIZE(veml6075_it_ms);</div><div class='add'>+		*vals = veml6075_it_ms;</div><div class='add'>+		*type = IIO_VAL_INT;</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *chan,</div><div class='add'>+			     int *val, int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct veml6075_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		return veml6075_read_uv_direct(data, chan-&gt;channel, val);</div><div class='add'>+	case IIO_CHAN_INFO_PROCESSED:</div><div class='add'>+		return veml6075_read_uvi(data, val, val2);</div><div class='add'>+	case IIO_CHAN_INFO_INT_TIME:</div><div class='add'>+		return veml6075_read_int_time_ms(data, val);</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		return veml6075_read_responsivity(chan-&gt;channel, val, val2);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_write_int_time_ms(struct veml6075_data *data, int val)</div><div class='add'>+{</div><div class='add'>+	int i = ARRAY_SIZE(veml6075_it_ms);</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	while (i-- &gt; 0) {</div><div class='add'>+		if (val == veml6075_it_ms[i])</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	if (i &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return regmap_update_bits(data-&gt;regmap, VEML6075_CMD_CONF,</div><div class='add'>+				  VEML6075_CONF_IT,</div><div class='add'>+				  FIELD_PREP(VEML6075_CONF_IT, i));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int veml6075_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			      struct iio_chan_spec const *chan,</div><div class='add'>+			      int val, int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct veml6075_data *data = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_INT_TIME:</div><div class='add'>+		return veml6075_write_int_time_ms(data, val);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info veml6075_info = {</div><div class='add'>+	.read_avail = veml6075_read_avail,</div><div class='add'>+	.read_raw = veml6075_read_raw,</div><div class='add'>+	.write_raw = veml6075_write_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool veml6075_readable_reg(struct device *dev, unsigned int reg)</div><div class='add'>+{</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case VEML6075_CMD_CONF:</div><div class='add'>+	case VEML6075_CMD_UVA:</div><div class='add'>+	case VEML6075_CMD_UVB:</div><div class='add'>+	case VEML6075_CMD_COMP1:</div><div class='add'>+	case VEML6075_CMD_COMP2:</div><div class='add'>+	case VEML6075_CMD_ID:</div><div class='add'>+		return true;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool veml6075_writable_reg(struct device *dev, unsigned int reg)</div><div class='add'>+{</div><div class='add'>+	switch (reg) {</div><div class='add'>+	case VEML6075_CMD_CONF:</div><div class='add'>+		return true;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct regmap_config veml6075_regmap_config = {</div><div class='add'>+	.name = "veml6075",</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+	.max_register = VEML6075_CMD_ID,</div><div class='add'>+	.readable_reg = veml6075_readable_reg,</div><div class='add'>+	.writeable_reg = veml6075_writable_reg,</div><div class='add'>+	.val_format_endian = REGMAP_ENDIAN_LITTLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int veml6075_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct veml6075_data *data;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	int config, ret;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	regmap = devm_regmap_init_i2c(client, &amp;veml6075_regmap_config);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return PTR_ERR(regmap);</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+	data-&gt;client = client;</div><div class='add'>+	data-&gt;regmap = regmap;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;data-&gt;lock);</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;name = "veml6075";</div><div class='add'>+	indio_dev-&gt;info = &amp;veml6075_info;</div><div class='add'>+	indio_dev-&gt;channels = veml6075_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(veml6075_channels);</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+</div><div class='add'>+	ret = devm_regulator_get_enable(&amp;client-&gt;dev, "vdd");</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* default: 100ms integration time, active force enable, shutdown */</div><div class='add'>+	config = FIELD_PREP(VEML6075_CONF_IT, VEML6075_IT_100_MS) |</div><div class='add'>+		FIELD_PREP(VEML6075_CONF_AF, VEML6075_AF_ENABLE) |</div><div class='add'>+		FIELD_PREP(VEML6075_CONF_SD, VEML6075_SD_ENABLE);</div><div class='add'>+	ret = regmap_write(data-&gt;regmap, VEML6075_CMD_CONF, config);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(&amp;client-&gt;dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id veml6075_id[] = {</div><div class='add'>+	{ "veml6075" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, veml6075_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id veml6075_of_match[] = {</div><div class='add'>+	{ .compatible = "vishay,veml6075" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, veml6075_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver veml6075_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name   = "veml6075",</div><div class='add'>+		.of_match_table = veml6075_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = veml6075_probe,</div><div class='add'>+	.id_table = veml6075_id,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(veml6075_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Javier Carrasco &lt;javier.carrasco.cruz@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Vishay VEML6075 UVA and UVB light sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/magnetometer/tmag5273.c b/drivers/iio/magnetometer/tmag5273.c<br/>index c5e5c4ad681e..218b1ce076c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/magnetometer/tmag5273.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/magnetometer/tmag5273.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/magnetometer/tmag5273.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/magnetometer/tmag5273.c</a></div><div class='hunk'>@@ -356,7 +356,7 @@ static int tmag5273_read_raw(struct iio_dev *indio_dev,</div><div class='ctx'> 	case IIO_CHAN_INFO_OFFSET:</div><div class='ctx'> 		switch (chan-&gt;type) {</div><div class='ctx'> 		case IIO_TEMP:</div><div class='del'>-			*val = -266314;</div><div class='add'>+			*val = -16005;</div><div class='ctx'> 			return IIO_VAL_INT;</div><div class='ctx'> 		default:</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -497,17 +497,13 @@ static int tmag5273_set_operating_mode(struct tmag5273_data *data,</div><div class='ctx'> static void tmag5273_read_device_property(struct tmag5273_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = data-&gt;dev;</div><div class='del'>-	const char *str;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;angle_measurement = TMAG5273_ANGLE_EN_X_Y;</div><div class='ctx'> </div><div class='del'>-	ret = device_property_read_string(dev, "ti,angle-measurement", &amp;str);</div><div class='del'>-	if (ret)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	ret = match_string(tmag5273_angle_names,</div><div class='del'>-			   ARRAY_SIZE(tmag5273_angle_names), str);</div><div class='add'>+	ret = device_property_match_property_string(dev, "ti,angle-measurement",</div><div class='add'>+						    tmag5273_angle_names,</div><div class='add'>+						    ARRAY_SIZE(tmag5273_angle_names));</div><div class='ctx'> 	if (ret &gt;= 0)</div><div class='ctx'> 		data-&gt;angle_measurement = ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig<br/>index 95efa32e4289..79adfd059c3a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/Kconfig</a></div><div class='hunk'>@@ -109,6 +109,28 @@ config HP03</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module</div><div class='ctx'> 	  will be called hp03.</div><div class='ctx'> </div><div class='add'>+config HSC030PA</div><div class='add'>+	tristate "Honeywell HSC/SSC TruStability pressure sensor series"</div><div class='add'>+	depends on (I2C || SPI_MASTER)</div><div class='add'>+	select HSC030PA_I2C if I2C</div><div class='add'>+	select HSC030PA_SPI if SPI_MASTER</div><div class='add'>+	help</div><div class='add'>+	  Say Y here to build support for the Honeywell TruStability</div><div class='add'>+	  HSC and SSC pressure and temperature sensor series.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module</div><div class='add'>+	  will be called hsc030pa.</div><div class='add'>+</div><div class='add'>+config HSC030PA_I2C</div><div class='add'>+	tristate</div><div class='add'>+	depends on HSC030PA</div><div class='add'>+	depends on I2C</div><div class='add'>+</div><div class='add'>+config HSC030PA_SPI</div><div class='add'>+	tristate</div><div class='add'>+	depends on HSC030PA</div><div class='add'>+	depends on SPI_MASTER</div><div class='add'>+</div><div class='ctx'> config ICP10100</div><div class='ctx'> 	tristate "InvenSense ICP-101xx pressure and temperature sensor"</div><div class='ctx'> 	depends on I2C</div><div class='head'>diff --git a/drivers/iio/pressure/Makefile b/drivers/iio/pressure/Makefile<br/>index 436aec7e65f3..b0f8b94662f2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/Makefile</a></div><div class='hunk'>@@ -15,6 +15,9 @@ obj-$(CONFIG_DPS310) += dps310.o</div><div class='ctx'> obj-$(CONFIG_IIO_CROS_EC_BARO) += cros_ec_baro.o</div><div class='ctx'> obj-$(CONFIG_HID_SENSOR_PRESS)   += hid-sensor-press.o</div><div class='ctx'> obj-$(CONFIG_HP03) += hp03.o</div><div class='add'>+obj-$(CONFIG_HSC030PA) += hsc030pa.o</div><div class='add'>+obj-$(CONFIG_HSC030PA_I2C) += hsc030pa_i2c.o</div><div class='add'>+obj-$(CONFIG_HSC030PA_SPI) += hsc030pa_spi.o</div><div class='ctx'> obj-$(CONFIG_ICP10100) += icp10100.o</div><div class='ctx'> obj-$(CONFIG_MPL115) += mpl115.o</div><div class='ctx'> obj-$(CONFIG_MPL115_I2C) += mpl115_i2c.o</div><div class='head'>diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c<br/>index a2ef1373a274..fe8734468ed3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/bmp280-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-core.c</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'>  * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp280-ds001.pdf</div><div class='ctx'>  * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme280-ds002.pdf</div><div class='ctx'>  * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp388-ds001.pdf</div><div class='add'>+ * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp390-ds002.pdf</div><div class='ctx'>  * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp581-ds004.pdf</div><div class='ctx'>  *</div><div class='ctx'>  * Notice:</div><div class='hunk'>@@ -794,10 +795,12 @@ static int bmp280_chip_config(struct bmp280_data *data)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const int bmp280_oversampling_avail[] = { 1, 2, 4, 8, 16 };</div><div class='add'>+static const u8 bmp280_chip_ids[] = { BMP280_CHIP_ID };</div><div class='ctx'> </div><div class='ctx'> const struct bmp280_chip_info bmp280_chip_info = {</div><div class='ctx'> 	.id_reg = BMP280_REG_ID,</div><div class='del'>-	.chip_id = BMP280_CHIP_ID,</div><div class='add'>+	.chip_id = bmp280_chip_ids,</div><div class='add'>+	.num_chip_id = ARRAY_SIZE(bmp280_chip_ids),</div><div class='ctx'> 	.regmap_config = &amp;bmp280_regmap_config,</div><div class='ctx'> 	.start_up_time = 2000,</div><div class='ctx'> 	.channels = bmp280_channels,</div><div class='hunk'>@@ -846,9 +849,12 @@ static int bme280_chip_config(struct bmp280_data *data)</div><div class='ctx'> 	return bmp280_chip_config(data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const u8 bme280_chip_ids[] = { BME280_CHIP_ID };</div><div class='add'>+</div><div class='ctx'> const struct bmp280_chip_info bme280_chip_info = {</div><div class='ctx'> 	.id_reg = BMP280_REG_ID,</div><div class='del'>-	.chip_id = BME280_CHIP_ID,</div><div class='add'>+	.chip_id = bme280_chip_ids,</div><div class='add'>+	.num_chip_id = ARRAY_SIZE(bme280_chip_ids),</div><div class='ctx'> 	.regmap_config = &amp;bmp280_regmap_config,</div><div class='ctx'> 	.start_up_time = 2000,</div><div class='ctx'> 	.channels = bmp280_channels,</div><div class='hunk'>@@ -920,7 +926,7 @@ static int bmp380_cmd(struct bmp280_data *data, u8 cmd)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Returns temperature in Celsius dregrees, resolution is 0.01º C. Output value of</div><div class='add'>+ * Returns temperature in Celsius degrees, resolution is 0.01º C. Output value of</div><div class='ctx'>  * "5123" equals 51.2º C. t_fine carries fine temperature as global value.</div><div class='ctx'>  *</div><div class='ctx'>  * Taken from datasheet, Section Appendix 9, "Compensation formula" and repo</div><div class='hunk'>@@ -1220,10 +1226,12 @@ static int bmp380_chip_config(struct bmp280_data *data)</div><div class='ctx'> </div><div class='ctx'> static const int bmp380_oversampling_avail[] = { 1, 2, 4, 8, 16, 32 };</div><div class='ctx'> static const int bmp380_iir_filter_coeffs_avail[] = { 1, 2, 4, 8, 16, 32, 64, 128};</div><div class='add'>+static const u8 bmp380_chip_ids[] = { BMP380_CHIP_ID, BMP390_CHIP_ID };</div><div class='ctx'> </div><div class='ctx'> const struct bmp280_chip_info bmp380_chip_info = {</div><div class='ctx'> 	.id_reg = BMP380_REG_ID,</div><div class='del'>-	.chip_id = BMP380_CHIP_ID,</div><div class='add'>+	.chip_id = bmp380_chip_ids,</div><div class='add'>+	.num_chip_id = ARRAY_SIZE(bmp380_chip_ids),</div><div class='ctx'> 	.regmap_config = &amp;bmp380_regmap_config,</div><div class='ctx'> 	.start_up_time = 2000,</div><div class='ctx'> 	.channels = bmp380_channels,</div><div class='hunk'>@@ -1385,7 +1393,7 @@ static int bmp580_read_temp(struct bmp280_data *data, int *val, int *val2)</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Temperature is returned in Celsius degrees in fractional</div><div class='del'>-	 * form down 2^16. We reescale by x1000 to return milli Celsius</div><div class='add'>+	 * form down 2^16. We rescale by x1000 to return milli Celsius</div><div class='ctx'> 	 * to respect IIO ABI.</div><div class='ctx'> 	 */</div><div class='ctx'> 	*val = raw_temp * 1000;</div><div class='hunk'>@@ -1412,7 +1420,7 @@ static int bmp580_read_press(struct bmp280_data *data, int *val, int *val2)</div><div class='ctx'> 	}</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Pressure is returned in Pascals in fractional form down 2^16.</div><div class='del'>-	 * We reescale /1000 to convert to kilopascal to respect IIO ABI.</div><div class='add'>+	 * We rescale /1000 to convert to kilopascal to respect IIO ABI.</div><div class='ctx'> 	 */</div><div class='ctx'> 	*val = raw_press;</div><div class='ctx'> 	*val2 = 64000; /* 2^6 * 1000 */</div><div class='hunk'>@@ -1720,10 +1728,12 @@ static int bmp580_chip_config(struct bmp280_data *data)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const int bmp580_oversampling_avail[] = { 1, 2, 4, 8, 16, 32, 64, 128 };</div><div class='add'>+static const u8 bmp580_chip_ids[] = { BMP580_CHIP_ID, BMP580_CHIP_ID_ALT };</div><div class='ctx'> </div><div class='ctx'> const struct bmp280_chip_info bmp580_chip_info = {</div><div class='ctx'> 	.id_reg = BMP580_REG_CHIP_ID,</div><div class='del'>-	.chip_id = BMP580_CHIP_ID,</div><div class='add'>+	.chip_id = bmp580_chip_ids,</div><div class='add'>+	.num_chip_id = ARRAY_SIZE(bmp580_chip_ids),</div><div class='ctx'> 	.regmap_config = &amp;bmp580_regmap_config,</div><div class='ctx'> 	.start_up_time = 2000,</div><div class='ctx'> 	.channels = bmp380_channels,</div><div class='hunk'>@@ -1983,10 +1993,12 @@ static int bmp180_chip_config(struct bmp280_data *data)</div><div class='ctx'> </div><div class='ctx'> static const int bmp180_oversampling_temp_avail[] = { 1 };</div><div class='ctx'> static const int bmp180_oversampling_press_avail[] = { 1, 2, 4, 8 };</div><div class='add'>+static const u8 bmp180_chip_ids[] = { BMP180_CHIP_ID };</div><div class='ctx'> </div><div class='ctx'> const struct bmp280_chip_info bmp180_chip_info = {</div><div class='ctx'> 	.id_reg = BMP280_REG_ID,</div><div class='del'>-	.chip_id = BMP180_CHIP_ID,</div><div class='add'>+	.chip_id = bmp180_chip_ids,</div><div class='add'>+	.num_chip_id = ARRAY_SIZE(bmp180_chip_ids),</div><div class='ctx'> 	.regmap_config = &amp;bmp180_regmap_config,</div><div class='ctx'> 	.start_up_time = 2000,</div><div class='ctx'> 	.channels = bmp280_channels,</div><div class='hunk'>@@ -2077,6 +2089,7 @@ int bmp280_common_probe(struct device *dev,</div><div class='ctx'> 	struct bmp280_data *data;</div><div class='ctx'> 	struct gpio_desc *gpiod;</div><div class='ctx'> 	unsigned int chip_id;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));</div><div class='hunk'>@@ -2142,12 +2155,17 @@ int bmp280_common_probe(struct device *dev,</div><div class='ctx'> 	ret = regmap_read(regmap, data-&gt;chip_info-&gt;id_reg, &amp;chip_id);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='del'>-	if (chip_id != data-&gt;chip_info-&gt;chip_id) {</div><div class='del'>-		dev_err(dev, "bad chip id: expected %x got %x\n",</div><div class='del'>-			data-&gt;chip_info-&gt;chip_id, chip_id);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; data-&gt;chip_info-&gt;num_chip_id; i++) {</div><div class='add'>+		if (chip_id == data-&gt;chip_info-&gt;chip_id[i]) {</div><div class='add'>+			dev_info(dev, "0x%x is a known chip id for %s\n", chip_id, name);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (i == data-&gt;chip_info-&gt;num_chip_id)</div><div class='add'>+		dev_warn(dev, "bad chip id: 0x%x is not a known chip id\n", chip_id);</div><div class='add'>+</div><div class='ctx'> 	if (data-&gt;chip_info-&gt;preinit) {</div><div class='ctx'> 		ret = data-&gt;chip_info-&gt;preinit(data);</div><div class='ctx'> 		if (ret)</div><div class='head'>diff --git a/drivers/iio/pressure/bmp280-i2c.c b/drivers/iio/pressure/bmp280-i2c.c<br/>index dbe630ad05b5..34e3bc758493 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/bmp280-i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-i2c.c</a></div><div class='hunk'>@@ -7,13 +7,11 @@</div><div class='ctx'> </div><div class='ctx'> static int bmp280_i2c_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='del'>-	struct regmap *regmap;</div><div class='del'>-	const struct bmp280_chip_info *chip_info;</div><div class='ctx'> 	const struct i2c_device_id *id = i2c_client_get_device_id(client);</div><div class='add'>+	const struct bmp280_chip_info *chip_info;</div><div class='add'>+	struct regmap *regmap;</div><div class='ctx'> </div><div class='del'>-	chip_info = device_get_match_data(&amp;client-&gt;dev);</div><div class='del'>-	if (!chip_info)</div><div class='del'>-		chip_info = (const struct bmp280_chip_info *) id-&gt;driver_data;</div><div class='add'>+	chip_info = i2c_get_match_data(client);</div><div class='ctx'> </div><div class='ctx'> 	regmap = devm_regmap_init_i2c(client, chip_info-&gt;regmap_config);</div><div class='ctx'> 	if (IS_ERR(regmap)) {</div><div class='head'>diff --git a/drivers/iio/pressure/bmp280-spi.c b/drivers/iio/pressure/bmp280-spi.c<br/>index 1dff9bb7c4e9..433d6fac83c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/bmp280-spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280-spi.c</a></div><div class='hunk'>@@ -14,8 +14,7 @@</div><div class='ctx'> static int bmp280_regmap_spi_write(void *context, const void *data,</div><div class='ctx'>                                    size_t count)</div><div class='ctx'> {</div><div class='del'>-	struct device *dev = context;</div><div class='del'>-	struct spi_device *spi = to_spi_device(dev);</div><div class='add'>+	struct spi_device *spi = to_spi_device(context);</div><div class='ctx'> 	u8 buf[2];</div><div class='ctx'> </div><div class='ctx'> 	memcpy(buf, data, 2);</div><div class='hunk'>@@ -31,8 +30,7 @@ static int bmp280_regmap_spi_write(void *context, const void *data,</div><div class='ctx'> static int bmp280_regmap_spi_read(void *context, const void *reg,</div><div class='ctx'>                                   size_t reg_size, void *val, size_t val_size)</div><div class='ctx'> {</div><div class='del'>-	struct device *dev = context;</div><div class='del'>-	struct spi_device *spi = to_spi_device(dev);</div><div class='add'>+	struct spi_device *spi = to_spi_device(context);</div><div class='ctx'> </div><div class='ctx'> 	return spi_write_then_read(spi, reg, reg_size, val, val_size);</div><div class='ctx'> }</div><div class='hunk'>@@ -58,9 +56,7 @@ static int bmp280_spi_probe(struct spi_device *spi)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	chip_info = device_get_match_data(&amp;spi-&gt;dev);</div><div class='del'>-	if (!chip_info)</div><div class='del'>-		chip_info = (const struct bmp280_chip_info *) id-&gt;driver_data;</div><div class='add'>+	chip_info = spi_get_device_match_data(spi);</div><div class='ctx'> </div><div class='ctx'> 	regmap = devm_regmap_init(&amp;spi-&gt;dev,</div><div class='ctx'> 				  &amp;bmp280_regmap_bus,</div><div class='head'>diff --git a/drivers/iio/pressure/bmp280.h b/drivers/iio/pressure/bmp280.h<br/>index 5c0563ce7572..4012387d7956 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/pressure/bmp280.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/bmp280.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/bmp280.h</a></div><div class='hunk'>@@ -292,6 +292,7 @@</div><div class='ctx'> #define BMP580_CHIP_ID_ALT		0x51</div><div class='ctx'> #define BMP180_CHIP_ID			0x55</div><div class='ctx'> #define BMP280_CHIP_ID			0x58</div><div class='add'>+#define BMP390_CHIP_ID			0x60</div><div class='ctx'> #define BME280_CHIP_ID			0x60</div><div class='ctx'> #define BMP280_SOFT_RESET_VAL		0xB6</div><div class='ctx'> </div><div class='hunk'>@@ -410,7 +411,7 @@ struct bmp280_data {</div><div class='ctx'> 		__le16 bmp280_cal_buf[BMP280_CONTIGUOUS_CALIB_REGS / 2];</div><div class='ctx'> 		__be16 bmp180_cal_buf[BMP180_REG_CALIB_COUNT / 2];</div><div class='ctx'> 		u8 bmp380_cal_buf[BMP380_CALIB_REG_COUNT];</div><div class='del'>-		/* Miscellaneous, endianess-aware data buffers */</div><div class='add'>+		/* Miscellaneous, endianness-aware data buffers */</div><div class='ctx'> 		__le16 le16;</div><div class='ctx'> 		__be16 be16;</div><div class='ctx'> 	} __aligned(IIO_DMA_MINALIGN);</div><div class='hunk'>@@ -418,7 +419,8 @@ struct bmp280_data {</div><div class='ctx'> </div><div class='ctx'> struct bmp280_chip_info {</div><div class='ctx'> 	unsigned int id_reg;</div><div class='del'>-	const unsigned int chip_id;</div><div class='add'>+	const u8 *chip_id;</div><div class='add'>+	int num_chip_id;</div><div class='ctx'> </div><div class='ctx'> 	const struct regmap_config *regmap_config;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/pressure/hsc030pa.c b/drivers/iio/pressure/hsc030pa.c<br/>new file mode 100644<br/>index 000000000000..d6a51f0c335f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/hsc030pa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa.c</a></div><div class='hunk'>@@ -0,0 +1,494 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Honeywell TruStability HSC Series pressure/temperature sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Petre Rodan &lt;petre.rodan@subdimension.ro&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/trustability-hsc-series/documents/sps-siot-trustability-hsc-series-high-accuracy-board-mount-pressure-sensors-50099148-a-en-ciid-151133.pdf</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/array_size.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/math64.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/printk.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+#include &lt;linux/iio/sysfs.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include "hsc030pa.h"</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * HSC_PRESSURE_TRIPLET_LEN - length for the string that defines the</div><div class='add'>+ * pressure range, measurement unit and type as per the part nomenclature.</div><div class='add'>+ * Consult honeywell,pressure-triplet in the bindings file for details.</div><div class='add'>+ */</div><div class='add'>+#define HSC_PRESSURE_TRIPLET_LEN 6</div><div class='add'>+#define HSC_STATUS_MASK          GENMASK(7, 6)</div><div class='add'>+#define HSC_TEMPERATURE_MASK     GENMASK(15, 5)</div><div class='add'>+#define HSC_PRESSURE_MASK        GENMASK(29, 16)</div><div class='add'>+</div><div class='add'>+struct hsc_func_spec {</div><div class='add'>+	u32 output_min;</div><div class='add'>+	u32 output_max;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * function A: 10% - 90% of 2^14</div><div class='add'>+ * function B:  5% - 95% of 2^14</div><div class='add'>+ * function C:  5% - 85% of 2^14</div><div class='add'>+ * function F:  4% - 94% of 2^14</div><div class='add'>+ */</div><div class='add'>+static const struct hsc_func_spec hsc_func_spec[] = {</div><div class='add'>+	[HSC_FUNCTION_A] = { .output_min = 1638, .output_max = 14746 },</div><div class='add'>+	[HSC_FUNCTION_B] = { .output_min =  819, .output_max = 15565 },</div><div class='add'>+	[HSC_FUNCTION_C] = { .output_min =  819, .output_max = 13926 },</div><div class='add'>+	[HSC_FUNCTION_F] = { .output_min =  655, .output_max = 15401 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hsc_variants {</div><div class='add'>+	HSC001BA = 0x00, HSC1_6BA = 0x01, HSC2_5BA = 0x02, HSC004BA = 0x03,</div><div class='add'>+	HSC006BA = 0x04, HSC010BA = 0x05, HSC1_6MD = 0x06, HSC2_5MD = 0x07,</div><div class='add'>+	HSC004MD = 0x08, HSC006MD = 0x09, HSC010MD = 0x0a, HSC016MD = 0x0b,</div><div class='add'>+	HSC025MD = 0x0c, HSC040MD = 0x0d, HSC060MD = 0x0e, HSC100MD = 0x0f,</div><div class='add'>+	HSC160MD = 0x10, HSC250MD = 0x11, HSC400MD = 0x12, HSC600MD = 0x13,</div><div class='add'>+	HSC001BD = 0x14, HSC1_6BD = 0x15, HSC2_5BD = 0x16, HSC004BD = 0x17,</div><div class='add'>+	HSC2_5MG = 0x18, HSC004MG = 0x19, HSC006MG = 0x1a, HSC010MG = 0x1b,</div><div class='add'>+	HSC016MG = 0x1c, HSC025MG = 0x1d, HSC040MG = 0x1e, HSC060MG = 0x1f,</div><div class='add'>+	HSC100MG = 0x20, HSC160MG = 0x21, HSC250MG = 0x22, HSC400MG = 0x23,</div><div class='add'>+	HSC600MG = 0x24, HSC001BG = 0x25, HSC1_6BG = 0x26, HSC2_5BG = 0x27,</div><div class='add'>+	HSC004BG = 0x28, HSC006BG = 0x29, HSC010BG = 0x2a, HSC100KA = 0x2b,</div><div class='add'>+	HSC160KA = 0x2c, HSC250KA = 0x2d, HSC400KA = 0x2e, HSC600KA = 0x2f,</div><div class='add'>+	HSC001GA = 0x30, HSC160LD = 0x31, HSC250LD = 0x32, HSC400LD = 0x33,</div><div class='add'>+	HSC600LD = 0x34, HSC001KD = 0x35, HSC1_6KD = 0x36, HSC2_5KD = 0x37,</div><div class='add'>+	HSC004KD = 0x38, HSC006KD = 0x39, HSC010KD = 0x3a, HSC016KD = 0x3b,</div><div class='add'>+	HSC025KD = 0x3c, HSC040KD = 0x3d, HSC060KD = 0x3e, HSC100KD = 0x3f,</div><div class='add'>+	HSC160KD = 0x40, HSC250KD = 0x41, HSC400KD = 0x42, HSC250LG = 0x43,</div><div class='add'>+	HSC400LG = 0x44, HSC600LG = 0x45, HSC001KG = 0x46, HSC1_6KG = 0x47,</div><div class='add'>+	HSC2_5KG = 0x48, HSC004KG = 0x49, HSC006KG = 0x4a, HSC010KG = 0x4b,</div><div class='add'>+	HSC016KG = 0x4c, HSC025KG = 0x4d, HSC040KG = 0x4e, HSC060KG = 0x4f,</div><div class='add'>+	HSC100KG = 0x50, HSC160KG = 0x51, HSC250KG = 0x52, HSC400KG = 0x53,</div><div class='add'>+	HSC600KG = 0x54, HSC001GG = 0x55, HSC015PA = 0x56, HSC030PA = 0x57,</div><div class='add'>+	HSC060PA = 0x58, HSC100PA = 0x59, HSC150PA = 0x5a, HSC0_5ND = 0x5b,</div><div class='add'>+	HSC001ND = 0x5c, HSC002ND = 0x5d, HSC004ND = 0x5e, HSC005ND = 0x5f,</div><div class='add'>+	HSC010ND = 0x60, HSC020ND = 0x61, HSC030ND = 0x62, HSC001PD = 0x63,</div><div class='add'>+	HSC005PD = 0x64, HSC015PD = 0x65, HSC030PD = 0x66, HSC060PD = 0x67,</div><div class='add'>+	HSC001NG = 0x68, HSC002NG = 0x69, HSC004NG = 0x6a, HSC005NG = 0x6b,</div><div class='add'>+	HSC010NG = 0x6c, HSC020NG = 0x6d, HSC030NG = 0x6e, HSC001PG = 0x6f,</div><div class='add'>+	HSC005PG = 0x70, HSC015PG = 0x71, HSC030PG = 0x72, HSC060PG = 0x73,</div><div class='add'>+	HSC100PG = 0x74, HSC150PG = 0x75, HSC_VARIANTS_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char * const hsc_triplet_variants[HSC_VARIANTS_MAX] = {</div><div class='add'>+	[HSC001BA] = "001BA", [HSC1_6BA] = "1.6BA", [HSC2_5BA] = "2.5BA",</div><div class='add'>+	[HSC004BA] = "004BA", [HSC006BA] = "006BA", [HSC010BA] = "010BA",</div><div class='add'>+	[HSC1_6MD] = "1.6MD", [HSC2_5MD] = "2.5MD", [HSC004MD] = "004MD",</div><div class='add'>+	[HSC006MD] = "006MD", [HSC010MD] = "010MD", [HSC016MD] = "016MD",</div><div class='add'>+	[HSC025MD] = "025MD", [HSC040MD] = "040MD", [HSC060MD] = "060MD",</div><div class='add'>+	[HSC100MD] = "100MD", [HSC160MD] = "160MD", [HSC250MD] = "250MD",</div><div class='add'>+	[HSC400MD] = "400MD", [HSC600MD] = "600MD", [HSC001BD] = "001BD",</div><div class='add'>+	[HSC1_6BD] = "1.6BD", [HSC2_5BD] = "2.5BD", [HSC004BD] = "004BD",</div><div class='add'>+	[HSC2_5MG] = "2.5MG", [HSC004MG] = "004MG", [HSC006MG] = "006MG",</div><div class='add'>+	[HSC010MG] = "010MG", [HSC016MG] = "016MG", [HSC025MG] = "025MG",</div><div class='add'>+	[HSC040MG] = "040MG", [HSC060MG] = "060MG", [HSC100MG] = "100MG",</div><div class='add'>+	[HSC160MG] = "160MG", [HSC250MG] = "250MG", [HSC400MG] = "400MG",</div><div class='add'>+	[HSC600MG] = "600MG", [HSC001BG] = "001BG", [HSC1_6BG] = "1.6BG",</div><div class='add'>+	[HSC2_5BG] = "2.5BG", [HSC004BG] = "004BG", [HSC006BG] = "006BG",</div><div class='add'>+	[HSC010BG] = "010BG", [HSC100KA] = "100KA", [HSC160KA] = "160KA",</div><div class='add'>+	[HSC250KA] = "250KA", [HSC400KA] = "400KA", [HSC600KA] = "600KA",</div><div class='add'>+	[HSC001GA] = "001GA", [HSC160LD] = "160LD", [HSC250LD] = "250LD",</div><div class='add'>+	[HSC400LD] = "400LD", [HSC600LD] = "600LD", [HSC001KD] = "001KD",</div><div class='add'>+	[HSC1_6KD] = "1.6KD", [HSC2_5KD] = "2.5KD", [HSC004KD] = "004KD",</div><div class='add'>+	[HSC006KD] = "006KD", [HSC010KD] = "010KD", [HSC016KD] = "016KD",</div><div class='add'>+	[HSC025KD] = "025KD", [HSC040KD] = "040KD", [HSC060KD] = "060KD",</div><div class='add'>+	[HSC100KD] = "100KD", [HSC160KD] = "160KD", [HSC250KD] = "250KD",</div><div class='add'>+	[HSC400KD] = "400KD", [HSC250LG] = "250LG", [HSC400LG] = "400LG",</div><div class='add'>+	[HSC600LG] = "600LG", [HSC001KG] = "001KG", [HSC1_6KG] = "1.6KG",</div><div class='add'>+	[HSC2_5KG] = "2.5KG", [HSC004KG] = "004KG", [HSC006KG] = "006KG",</div><div class='add'>+	[HSC010KG] = "010KG", [HSC016KG] = "016KG", [HSC025KG] = "025KG",</div><div class='add'>+	[HSC040KG] = "040KG", [HSC060KG] = "060KG", [HSC100KG] = "100KG",</div><div class='add'>+	[HSC160KG] = "160KG", [HSC250KG] = "250KG", [HSC400KG] = "400KG",</div><div class='add'>+	[HSC600KG] = "600KG", [HSC001GG] = "001GG", [HSC015PA] = "015PA",</div><div class='add'>+	[HSC030PA] = "030PA", [HSC060PA] = "060PA", [HSC100PA] = "100PA",</div><div class='add'>+	[HSC150PA] = "150PA", [HSC0_5ND] = "0.5ND", [HSC001ND] = "001ND",</div><div class='add'>+	[HSC002ND] = "002ND", [HSC004ND] = "004ND", [HSC005ND] = "005ND",</div><div class='add'>+	[HSC010ND] = "010ND", [HSC020ND] = "020ND", [HSC030ND] = "030ND",</div><div class='add'>+	[HSC001PD] = "001PD", [HSC005PD] = "005PD", [HSC015PD] = "015PD",</div><div class='add'>+	[HSC030PD] = "030PD", [HSC060PD] = "060PD", [HSC001NG] = "001NG",</div><div class='add'>+	[HSC002NG] = "002NG", [HSC004NG] = "004NG", [HSC005NG] = "005NG",</div><div class='add'>+	[HSC010NG] = "010NG", [HSC020NG] = "020NG", [HSC030NG] = "030NG",</div><div class='add'>+	[HSC001PG] = "001PG", [HSC005PG] = "005PG", [HSC015PG] = "015PG",</div><div class='add'>+	[HSC030PG] = "030PG", [HSC060PG] = "060PG", [HSC100PG] = "100PG",</div><div class='add'>+	[HSC150PG] = "150PG",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct hsc_range_config - list of pressure ranges based on nomenclature</div><div class='add'>+ * @pmin: lowest pressure that can be measured</div><div class='add'>+ * @pmax: highest pressure that can be measured</div><div class='add'>+ */</div><div class='add'>+struct hsc_range_config {</div><div class='add'>+	const s32 pmin;</div><div class='add'>+	const s32 pmax;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* All min max limits have been converted to pascals */</div><div class='add'>+static const struct hsc_range_config hsc_range_config[HSC_VARIANTS_MAX] = {</div><div class='add'>+	[HSC001BA] = { .pmin =       0, .pmax =  100000 },</div><div class='add'>+	[HSC1_6BA] = { .pmin =       0, .pmax =  160000 },</div><div class='add'>+	[HSC2_5BA] = { .pmin =       0, .pmax =  250000 },</div><div class='add'>+	[HSC004BA] = { .pmin =       0, .pmax =  400000 },</div><div class='add'>+	[HSC006BA] = { .pmin =       0, .pmax =  600000 },</div><div class='add'>+	[HSC010BA] = { .pmin =       0, .pmax = 1000000 },</div><div class='add'>+	[HSC1_6MD] = { .pmin =    -160, .pmax =     160 },</div><div class='add'>+	[HSC2_5MD] = { .pmin =    -250, .pmax =     250 },</div><div class='add'>+	[HSC004MD] = { .pmin =    -400, .pmax =     400 },</div><div class='add'>+	[HSC006MD] = { .pmin =    -600, .pmax =     600 },</div><div class='add'>+	[HSC010MD] = { .pmin =   -1000, .pmax =    1000 },</div><div class='add'>+	[HSC016MD] = { .pmin =   -1600, .pmax =    1600 },</div><div class='add'>+	[HSC025MD] = { .pmin =   -2500, .pmax =    2500 },</div><div class='add'>+	[HSC040MD] = { .pmin =   -4000, .pmax =    4000 },</div><div class='add'>+	[HSC060MD] = { .pmin =   -6000, .pmax =    6000 },</div><div class='add'>+	[HSC100MD] = { .pmin =  -10000, .pmax =   10000 },</div><div class='add'>+	[HSC160MD] = { .pmin =  -16000, .pmax =   16000 },</div><div class='add'>+	[HSC250MD] = { .pmin =  -25000, .pmax =   25000 },</div><div class='add'>+	[HSC400MD] = { .pmin =  -40000, .pmax =   40000 },</div><div class='add'>+	[HSC600MD] = { .pmin =  -60000, .pmax =   60000 },</div><div class='add'>+	[HSC001BD] = { .pmin = -100000, .pmax =  100000 },</div><div class='add'>+	[HSC1_6BD] = { .pmin = -160000, .pmax =  160000 },</div><div class='add'>+	[HSC2_5BD] = { .pmin = -250000, .pmax =  250000 },</div><div class='add'>+	[HSC004BD] = { .pmin = -400000, .pmax =  400000 },</div><div class='add'>+	[HSC2_5MG] = { .pmin =       0, .pmax =     250 },</div><div class='add'>+	[HSC004MG] = { .pmin =       0, .pmax =     400 },</div><div class='add'>+	[HSC006MG] = { .pmin =       0, .pmax =     600 },</div><div class='add'>+	[HSC010MG] = { .pmin =       0, .pmax =    1000 },</div><div class='add'>+	[HSC016MG] = { .pmin =       0, .pmax =    1600 },</div><div class='add'>+	[HSC025MG] = { .pmin =       0, .pmax =    2500 },</div><div class='add'>+	[HSC040MG] = { .pmin =       0, .pmax =    4000 },</div><div class='add'>+	[HSC060MG] = { .pmin =       0, .pmax =    6000 },</div><div class='add'>+	[HSC100MG] = { .pmin =       0, .pmax =   10000 },</div><div class='add'>+	[HSC160MG] = { .pmin =       0, .pmax =   16000 },</div><div class='add'>+	[HSC250MG] = { .pmin =       0, .pmax =   25000 },</div><div class='add'>+	[HSC400MG] = { .pmin =       0, .pmax =   40000 },</div><div class='add'>+	[HSC600MG] = { .pmin =       0, .pmax =   60000 },</div><div class='add'>+	[HSC001BG] = { .pmin =       0, .pmax =  100000 },</div><div class='add'>+	[HSC1_6BG] = { .pmin =       0, .pmax =  160000 },</div><div class='add'>+	[HSC2_5BG] = { .pmin =       0, .pmax =  250000 },</div><div class='add'>+	[HSC004BG] = { .pmin =       0, .pmax =  400000 },</div><div class='add'>+	[HSC006BG] = { .pmin =       0, .pmax =  600000 },</div><div class='add'>+	[HSC010BG] = { .pmin =       0, .pmax = 1000000 },</div><div class='add'>+	[HSC100KA] = { .pmin =       0, .pmax =  100000 },</div><div class='add'>+	[HSC160KA] = { .pmin =       0, .pmax =  160000 },</div><div class='add'>+	[HSC250KA] = { .pmin =       0, .pmax =  250000 },</div><div class='add'>+	[HSC400KA] = { .pmin =       0, .pmax =  400000 },</div><div class='add'>+	[HSC600KA] = { .pmin =       0, .pmax =  600000 },</div><div class='add'>+	[HSC001GA] = { .pmin =       0, .pmax = 1000000 },</div><div class='add'>+	[HSC160LD] = { .pmin =    -160, .pmax =     160 },</div><div class='add'>+	[HSC250LD] = { .pmin =    -250, .pmax =     250 },</div><div class='add'>+	[HSC400LD] = { .pmin =    -400, .pmax =     400 },</div><div class='add'>+	[HSC600LD] = { .pmin =    -600, .pmax =     600 },</div><div class='add'>+	[HSC001KD] = { .pmin =   -1000, .pmax =    1000 },</div><div class='add'>+	[HSC1_6KD] = { .pmin =   -1600, .pmax =    1600 },</div><div class='add'>+	[HSC2_5KD] = { .pmin =   -2500, .pmax =    2500 },</div><div class='add'>+	[HSC004KD] = { .pmin =   -4000, .pmax =    4000 },</div><div class='add'>+	[HSC006KD] = { .pmin =   -6000, .pmax =    6000 },</div><div class='add'>+	[HSC010KD] = { .pmin =  -10000, .pmax =   10000 },</div><div class='add'>+	[HSC016KD] = { .pmin =  -16000, .pmax =   16000 },</div><div class='add'>+	[HSC025KD] = { .pmin =  -25000, .pmax =   25000 },</div><div class='add'>+	[HSC040KD] = { .pmin =  -40000, .pmax =   40000 },</div><div class='add'>+	[HSC060KD] = { .pmin =  -60000, .pmax =   60000 },</div><div class='add'>+	[HSC100KD] = { .pmin = -100000, .pmax =  100000 },</div><div class='add'>+	[HSC160KD] = { .pmin = -160000, .pmax =  160000 },</div><div class='add'>+	[HSC250KD] = { .pmin = -250000, .pmax =  250000 },</div><div class='add'>+	[HSC400KD] = { .pmin = -400000, .pmax =  400000 },</div><div class='add'>+	[HSC250LG] = { .pmin =       0, .pmax =     250 },</div><div class='add'>+	[HSC400LG] = { .pmin =       0, .pmax =     400 },</div><div class='add'>+	[HSC600LG] = { .pmin =       0, .pmax =     600 },</div><div class='add'>+	[HSC001KG] = { .pmin =       0, .pmax =    1000 },</div><div class='add'>+	[HSC1_6KG] = { .pmin =       0, .pmax =    1600 },</div><div class='add'>+	[HSC2_5KG] = { .pmin =       0, .pmax =    2500 },</div><div class='add'>+	[HSC004KG] = { .pmin =       0, .pmax =    4000 },</div><div class='add'>+	[HSC006KG] = { .pmin =       0, .pmax =    6000 },</div><div class='add'>+	[HSC010KG] = { .pmin =       0, .pmax =   10000 },</div><div class='add'>+	[HSC016KG] = { .pmin =       0, .pmax =   16000 },</div><div class='add'>+	[HSC025KG] = { .pmin =       0, .pmax =   25000 },</div><div class='add'>+	[HSC040KG] = { .pmin =       0, .pmax =   40000 },</div><div class='add'>+	[HSC060KG] = { .pmin =       0, .pmax =   60000 },</div><div class='add'>+	[HSC100KG] = { .pmin =       0, .pmax =  100000 },</div><div class='add'>+	[HSC160KG] = { .pmin =       0, .pmax =  160000 },</div><div class='add'>+	[HSC250KG] = { .pmin =       0, .pmax =  250000 },</div><div class='add'>+	[HSC400KG] = { .pmin =       0, .pmax =  400000 },</div><div class='add'>+	[HSC600KG] = { .pmin =       0, .pmax =  600000 },</div><div class='add'>+	[HSC001GG] = { .pmin =       0, .pmax = 1000000 },</div><div class='add'>+	[HSC015PA] = { .pmin =       0, .pmax =  103421 },</div><div class='add'>+	[HSC030PA] = { .pmin =       0, .pmax =  206843 },</div><div class='add'>+	[HSC060PA] = { .pmin =       0, .pmax =  413685 },</div><div class='add'>+	[HSC100PA] = { .pmin =       0, .pmax =  689476 },</div><div class='add'>+	[HSC150PA] = { .pmin =       0, .pmax = 1034214 },</div><div class='add'>+	[HSC0_5ND] = { .pmin =    -125, .pmax =     125 },</div><div class='add'>+	[HSC001ND] = { .pmin =    -249, .pmax =     249 },</div><div class='add'>+	[HSC002ND] = { .pmin =    -498, .pmax =     498 },</div><div class='add'>+	[HSC004ND] = { .pmin =    -996, .pmax =     996 },</div><div class='add'>+	[HSC005ND] = { .pmin =   -1245, .pmax =    1245 },</div><div class='add'>+	[HSC010ND] = { .pmin =   -2491, .pmax =    2491 },</div><div class='add'>+	[HSC020ND] = { .pmin =   -4982, .pmax =    4982 },</div><div class='add'>+	[HSC030ND] = { .pmin =   -7473, .pmax =    7473 },</div><div class='add'>+	[HSC001PD] = { .pmin =   -6895, .pmax =    6895 },</div><div class='add'>+	[HSC005PD] = { .pmin =  -34474, .pmax =   34474 },</div><div class='add'>+	[HSC015PD] = { .pmin = -103421, .pmax =  103421 },</div><div class='add'>+	[HSC030PD] = { .pmin = -206843, .pmax =  206843 },</div><div class='add'>+	[HSC060PD] = { .pmin = -413685, .pmax =  413685 },</div><div class='add'>+	[HSC001NG] = { .pmin =       0, .pmax =     249 },</div><div class='add'>+	[HSC002NG] = { .pmin =       0, .pmax =     498 },</div><div class='add'>+	[HSC004NG] = { .pmin =       0, .pmax =     996 },</div><div class='add'>+	[HSC005NG] = { .pmin =       0, .pmax =    1245 },</div><div class='add'>+	[HSC010NG] = { .pmin =       0, .pmax =    2491 },</div><div class='add'>+	[HSC020NG] = { .pmin =       0, .pmax =    4982 },</div><div class='add'>+	[HSC030NG] = { .pmin =       0, .pmax =    7473 },</div><div class='add'>+	[HSC001PG] = { .pmin =       0, .pmax =    6895 },</div><div class='add'>+	[HSC005PG] = { .pmin =       0, .pmax =   34474 },</div><div class='add'>+	[HSC015PG] = { .pmin =       0, .pmax =  103421 },</div><div class='add'>+	[HSC030PG] = { .pmin =       0, .pmax =  206843 },</div><div class='add'>+	[HSC060PG] = { .pmin =       0, .pmax =  413685 },</div><div class='add'>+	[HSC100PG] = { .pmin =       0, .pmax =  689476 },</div><div class='add'>+	[HSC150PG] = { .pmin =       0, .pmax = 1034214 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * hsc_measurement_is_valid() - validate last conversion via status bits</div><div class='add'>+ * @data: structure containing instantiated sensor data</div><div class='add'>+ * Return: true only if both status bits are zero</div><div class='add'>+ *</div><div class='add'>+ * the two MSB from the first transfered byte contain a status code</div><div class='add'>+ *   00 - normal operation, valid data</div><div class='add'>+ *   01 - device in factory programming mode</div><div class='add'>+ *   10 - stale data</div><div class='add'>+ *   11 - diagnostic condition</div><div class='add'>+ */</div><div class='add'>+static bool hsc_measurement_is_valid(struct hsc_data *data)</div><div class='add'>+{</div><div class='add'>+	return !(data-&gt;buffer[0] &amp; HSC_STATUS_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hsc_get_measurement(struct hsc_data *data)</div><div class='add'>+{</div><div class='add'>+	const struct hsc_chip_data *chip = data-&gt;chip;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = data-&gt;recv_cb(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;is_valid = chip-&gt;valid(data);</div><div class='add'>+	if (!data-&gt;is_valid)</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * IIO ABI expects</div><div class='add'>+ * value = (conv + offset) * scale</div><div class='add'>+ *</div><div class='add'>+ * datasheet provides the following formula for determining the temperature</div><div class='add'>+ * temp[C] = conv * a + b</div><div class='add'>+ *   where a = 200/2047; b = -50</div><div class='add'>+ *</div><div class='add'>+ *  temp[C] = (conv + (b/a)) * a * (1000)</div><div class='add'>+ *  =&gt;</div><div class='add'>+ *  scale = a * 1000 = .097703957 * 1000 = 97.703957</div><div class='add'>+ *  offset = b/a = -50 / .097703957 = -50000000 / 97704</div><div class='add'>+ *</div><div class='add'>+ *  based on the datasheet</div><div class='add'>+ *  pressure = (conv - Omin) * Q + Pmin =</div><div class='add'>+ *          ((conv - Omin) + Pmin/Q) * Q</div><div class='add'>+ *  =&gt;</div><div class='add'>+ *  scale = Q = (Pmax - Pmin) / (Omax - Omin)</div><div class='add'>+ *  offset = Pmin/Q - Omin = Pmin * (Omax - Omin) / (Pmax - Pmin) - Omin</div><div class='add'>+ */</div><div class='add'>+static int hsc_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			struct iio_chan_spec const *channel, int *val,</div><div class='add'>+			int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct hsc_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+	u32 recvd;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		ret = hsc_get_measurement(data);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		recvd = get_unaligned_be32(data-&gt;buffer);</div><div class='add'>+		switch (channel-&gt;type) {</div><div class='add'>+		case IIO_PRESSURE:</div><div class='add'>+			*val = FIELD_GET(HSC_PRESSURE_MASK, recvd);</div><div class='add'>+			return IIO_VAL_INT;</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			*val = FIELD_GET(HSC_TEMPERATURE_MASK, recvd);</div><div class='add'>+			return IIO_VAL_INT;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		switch (channel-&gt;type) {</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			*val = 97;</div><div class='add'>+			*val2 = 703957;</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		case IIO_PRESSURE:</div><div class='add'>+			*val = data-&gt;p_scale;</div><div class='add'>+			*val2 = data-&gt;p_scale_dec;</div><div class='add'>+			return IIO_VAL_INT_PLUS_NANO;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	case IIO_CHAN_INFO_OFFSET:</div><div class='add'>+		switch (channel-&gt;type) {</div><div class='add'>+		case IIO_TEMP:</div><div class='add'>+			*val = -50000000;</div><div class='add'>+			*val2 = 97704;</div><div class='add'>+			return IIO_VAL_FRACTIONAL;</div><div class='add'>+		case IIO_PRESSURE:</div><div class='add'>+			*val = data-&gt;p_offset;</div><div class='add'>+			*val2 = data-&gt;p_offset_dec;</div><div class='add'>+			return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec hsc_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_PRESSURE,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_OFFSET),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_SCALE) |</div><div class='add'>+				      BIT(IIO_CHAN_INFO_OFFSET),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_info hsc_info = {</div><div class='add'>+	.read_raw = hsc_read_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hsc_chip_data hsc_chip = {</div><div class='add'>+	.valid = hsc_measurement_is_valid,</div><div class='add'>+	.channels = hsc_channels,</div><div class='add'>+	.num_channels = ARRAY_SIZE(hsc_channels),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int hsc_common_probe(struct device *dev, hsc_recv_fn recv)</div><div class='add'>+{</div><div class='add'>+	struct hsc_data *hsc;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	const char *triplet;</div><div class='add'>+	u64 tmp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(dev, sizeof(*hsc));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	hsc = iio_priv(indio_dev);</div><div class='add'>+</div><div class='add'>+	hsc-&gt;chip = &amp;hsc_chip;</div><div class='add'>+	hsc-&gt;recv_cb = recv;</div><div class='add'>+	hsc-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	ret = device_property_read_u32(dev, "honeywell,transfer-function",</div><div class='add'>+				       &amp;hsc-&gt;function);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+			    "honeywell,transfer-function could not be read\n");</div><div class='add'>+	if (hsc-&gt;function &gt; HSC_FUNCTION_F)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				     "honeywell,transfer-function %d invalid\n",</div><div class='add'>+				     hsc-&gt;function);</div><div class='add'>+</div><div class='add'>+	ret = device_property_read_string(dev, "honeywell,pressure-triplet",</div><div class='add'>+					  &amp;triplet);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+			     "honeywell,pressure-triplet could not be read\n");</div><div class='add'>+</div><div class='add'>+	if (str_has_prefix(triplet, "NA")) {</div><div class='add'>+		ret = device_property_read_u32(dev, "honeywell,pmin-pascal",</div><div class='add'>+					       &amp;hsc-&gt;pmin);</div><div class='add'>+		if (ret)</div><div class='add'>+			return dev_err_probe(dev, ret,</div><div class='add'>+				  "honeywell,pmin-pascal could not be read\n");</div><div class='add'>+</div><div class='add'>+		ret = device_property_read_u32(dev, "honeywell,pmax-pascal",</div><div class='add'>+					       &amp;hsc-&gt;pmax);</div><div class='add'>+		if (ret)</div><div class='add'>+			return dev_err_probe(dev, ret,</div><div class='add'>+				  "honeywell,pmax-pascal could not be read\n");</div><div class='add'>+	} else {</div><div class='add'>+		ret = device_property_match_property_string(dev,</div><div class='add'>+						  "honeywell,pressure-triplet",</div><div class='add'>+						  hsc_triplet_variants,</div><div class='add'>+						  HSC_VARIANTS_MAX);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				    "honeywell,pressure-triplet is invalid\n");</div><div class='add'>+</div><div class='add'>+		hsc-&gt;pmin = hsc_range_config[ret].pmin;</div><div class='add'>+		hsc-&gt;pmax = hsc_range_config[ret].pmax;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (hsc-&gt;pmin &gt;= hsc-&gt;pmax)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				     "pressure limits are invalid\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_regulator_get_enable(dev, "vdd");</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "can't get vdd supply\n");</div><div class='add'>+</div><div class='add'>+	hsc-&gt;outmin = hsc_func_spec[hsc-&gt;function].output_min;</div><div class='add'>+	hsc-&gt;outmax = hsc_func_spec[hsc-&gt;function].output_max;</div><div class='add'>+</div><div class='add'>+	tmp = div_s64(((s64)(hsc-&gt;pmax - hsc-&gt;pmin)) * MICRO,</div><div class='add'>+		      hsc-&gt;outmax - hsc-&gt;outmin);</div><div class='add'>+	hsc-&gt;p_scale = div_s64_rem(tmp, NANO, &amp;hsc-&gt;p_scale_dec);</div><div class='add'>+	tmp = div_s64(((s64)hsc-&gt;pmin * (s64)(hsc-&gt;outmax - hsc-&gt;outmin)) * MICRO,</div><div class='add'>+		      hsc-&gt;pmax - hsc-&gt;pmin);</div><div class='add'>+	tmp -= (s64)hsc-&gt;outmin * MICRO;</div><div class='add'>+	hsc-&gt;p_offset = div_s64_rem(tmp, MICRO, &amp;hsc-&gt;p_offset_dec);</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;name = "hsc030pa";</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+	indio_dev-&gt;info = &amp;hsc_info;</div><div class='add'>+	indio_dev-&gt;channels = hsc-&gt;chip-&gt;channels;</div><div class='add'>+	indio_dev-&gt;num_channels = hsc-&gt;chip-&gt;num_channels;</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS(hsc_common_probe, IIO_HONEYWELL_HSC030PA);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Petre Rodan &lt;petre.rodan@subdimension.ro&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Honeywell HSC and SSC pressure sensor core driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/pressure/hsc030pa.h b/drivers/iio/pressure/hsc030pa.h<br/>new file mode 100644<br/>index 000000000000..d20420dba4f6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/hsc030pa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa.h</a></div><div class='hunk'>@@ -0,0 +1,74 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Honeywell TruStability HSC Series pressure/temperature sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Petre Rodan &lt;petre.rodan@subdimension.ro&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _HSC030PA_H</div><div class='add'>+#define _HSC030PA_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#define HSC_REG_MEASUREMENT_RD_SIZE 4</div><div class='add'>+</div><div class='add'>+struct device;</div><div class='add'>+</div><div class='add'>+struct iio_chan_spec;</div><div class='add'>+struct iio_dev;</div><div class='add'>+</div><div class='add'>+struct hsc_data;</div><div class='add'>+struct hsc_chip_data;</div><div class='add'>+</div><div class='add'>+typedef int (*hsc_recv_fn)(struct hsc_data *);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct hsc_data</div><div class='add'>+ * @dev: current device structure</div><div class='add'>+ * @chip: structure containing chip's channel properties</div><div class='add'>+ * @recv_cb: function that implements the chip reads</div><div class='add'>+ * @is_valid: true if last transfer has been validated</div><div class='add'>+ * @pmin: minimum measurable pressure limit</div><div class='add'>+ * @pmax: maximum measurable pressure limit</div><div class='add'>+ * @outmin: minimum raw pressure in counts (based on transfer function)</div><div class='add'>+ * @outmax: maximum raw pressure in counts (based on transfer function)</div><div class='add'>+ * @function: transfer function</div><div class='add'>+ * @p_scale: pressure scale</div><div class='add'>+ * @p_scale_dec: pressure scale, decimal places</div><div class='add'>+ * @p_offset: pressure offset</div><div class='add'>+ * @p_offset_dec: pressure offset, decimal places</div><div class='add'>+ * @buffer: raw conversion data</div><div class='add'>+ */</div><div class='add'>+struct hsc_data {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	const struct hsc_chip_data *chip;</div><div class='add'>+	hsc_recv_fn recv_cb;</div><div class='add'>+	bool is_valid;</div><div class='add'>+	s32 pmin;</div><div class='add'>+	s32 pmax;</div><div class='add'>+	u32 outmin;</div><div class='add'>+	u32 outmax;</div><div class='add'>+	u32 function;</div><div class='add'>+	s64 p_scale;</div><div class='add'>+	s32 p_scale_dec;</div><div class='add'>+	s64 p_offset;</div><div class='add'>+	s32 p_offset_dec;</div><div class='add'>+	u8 buffer[HSC_REG_MEASUREMENT_RD_SIZE] __aligned(IIO_DMA_MINALIGN);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hsc_chip_data {</div><div class='add'>+	bool (*valid)(struct hsc_data *data);</div><div class='add'>+	const struct iio_chan_spec *channels;</div><div class='add'>+	u8 num_channels;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum hsc_func_id {</div><div class='add'>+	HSC_FUNCTION_A,</div><div class='add'>+	HSC_FUNCTION_B,</div><div class='add'>+	HSC_FUNCTION_C,</div><div class='add'>+	HSC_FUNCTION_F,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int hsc_common_probe(struct device *dev, hsc_recv_fn recv);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/iio/pressure/hsc030pa_i2c.c b/drivers/iio/pressure/hsc030pa_i2c.c<br/>new file mode 100644<br/>index 000000000000..e2b524b36417<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/hsc030pa_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa_i2c.c</a></div><div class='hunk'>@@ -0,0 +1,69 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Honeywell TruStability HSC Series pressure/temperature sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Petre Rodan &lt;petre.rodan@subdimension.ro&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/trustability-hsc-series/documents/sps-siot-trustability-hsc-series-high-accuracy-board-mount-pressure-sensors-50099148-a-en-ciid-151133.pdf [hsc]</div><div class='add'>+ * Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/common/documents/sps-siot-i2c-comms-digital-output-pressure-sensors-tn-008201-3-en-ciid-45841.pdf [i2c related]</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "hsc030pa.h"</div><div class='add'>+</div><div class='add'>+static int hsc_i2c_recv(struct hsc_data *data)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = to_i2c_client(data-&gt;dev);</div><div class='add'>+	struct i2c_msg msg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	msg.addr = client-&gt;addr;</div><div class='add'>+	msg.flags = client-&gt;flags | I2C_M_RD;</div><div class='add'>+	msg.len = HSC_REG_MEASUREMENT_RD_SIZE;</div><div class='add'>+	msg.buf = data-&gt;buffer;</div><div class='add'>+</div><div class='add'>+	ret = i2c_transfer(client-&gt;adapter, &amp;msg, 1);</div><div class='add'>+</div><div class='add'>+	return (ret == 2) ? 0 : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hsc_i2c_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	if (!i2c_check_functionality(client-&gt;adapter, I2C_FUNC_I2C))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return hsc_common_probe(&amp;client-&gt;dev, hsc_i2c_recv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id hsc_i2c_match[] = {</div><div class='add'>+	{ .compatible = "honeywell,hsc030pa" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, hsc_i2c_match);</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id hsc_i2c_id[] = {</div><div class='add'>+	{ "hsc030pa" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, hsc_i2c_id);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver hsc_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "hsc030pa",</div><div class='add'>+		.of_match_table = hsc_i2c_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = hsc_i2c_probe,</div><div class='add'>+	.id_table = hsc_i2c_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(hsc_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Petre Rodan &lt;petre.rodan@subdimension.ro&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Honeywell HSC and SSC pressure sensor i2c driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(IIO_HONEYWELL_HSC030PA);</div><div class='head'>diff --git a/drivers/iio/pressure/hsc030pa_spi.c b/drivers/iio/pressure/hsc030pa_spi.c<br/>new file mode 100644<br/>index 000000000000..a719bade8326<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/pressure/hsc030pa_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/pressure/hsc030pa_spi.c</a></div><div class='hunk'>@@ -0,0 +1,61 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Honeywell TruStability HSC Series pressure/temperature sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Petre Rodan &lt;petre.rodan@subdimension.ro&gt;</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/trustability-hsc-series/documents/sps-siot-trustability-hsc-series-high-accuracy-board-mount-pressure-sensors-50099148-a-en-ciid-151133.pdf</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/spi/spi.h&gt;</div><div class='add'>+#include &lt;linux/stddef.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+#include "hsc030pa.h"</div><div class='add'>+</div><div class='add'>+static int hsc_spi_recv(struct hsc_data *data)</div><div class='add'>+{</div><div class='add'>+	struct spi_device *spi = to_spi_device(data-&gt;dev);</div><div class='add'>+	struct spi_transfer xfer = {</div><div class='add'>+		.tx_buf = NULL,</div><div class='add'>+		.rx_buf = data-&gt;buffer,</div><div class='add'>+		.len = HSC_REG_MEASUREMENT_RD_SIZE,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return spi_sync_transfer(spi, &amp;xfer, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hsc_spi_probe(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	return hsc_common_probe(&amp;spi-&gt;dev, hsc_spi_recv);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id hsc_spi_match[] = {</div><div class='add'>+	{ .compatible = "honeywell,hsc030pa" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, hsc_spi_match);</div><div class='add'>+</div><div class='add'>+static const struct spi_device_id hsc_spi_id[] = {</div><div class='add'>+	{ "hsc030pa" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(spi, hsc_spi_id);</div><div class='add'>+</div><div class='add'>+static struct spi_driver hsc_spi_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "hsc030pa",</div><div class='add'>+		.of_match_table = hsc_spi_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = hsc_spi_probe,</div><div class='add'>+	.id_table = hsc_spi_id,</div><div class='add'>+};</div><div class='add'>+module_spi_driver(hsc_spi_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Petre Rodan &lt;petre.rodan@subdimension.ro&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Honeywell HSC and SSC pressure sensor spi driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(IIO_HONEYWELL_HSC030PA);</div><div class='head'>diff --git a/drivers/iio/proximity/irsd200.c b/drivers/iio/proximity/irsd200.c<br/>index bdff91f6b1a3..323ac6dac90e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/proximity/irsd200.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/proximity/irsd200.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/proximity/irsd200.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/proximity/irsd200.c</a></div><div class='hunk'>@@ -7,7 +7,6 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/unaligned.h&gt;</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='del'>-#include &lt;linux/gpio.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='head'>diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c<br/>index 438f9c9aba6e..ac2ed2da21cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/proximity/sx9324.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/proximity/sx9324.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/proximity/sx9324.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/proximity/sx9324.c</a></div><div class='hunk'>@@ -888,7 +888,6 @@ sx9324_get_default_reg(struct device *dev, int idx,</div><div class='ctx'> 	char prop[] = SX9324_PROXRAW_DEF;</div><div class='ctx'> 	u32 start = 0, raw = 0, pos = 0;</div><div class='ctx'> 	int ret, count, ph, pin;</div><div class='del'>-	const char *res;</div><div class='ctx'> </div><div class='ctx'> 	memcpy(reg_def, &amp;sx9324_default_regs[idx], sizeof(*reg_def));</div><div class='ctx'> </div><div class='hunk'>@@ -915,24 +914,21 @@ sx9324_get_default_reg(struct device *dev, int idx,</div><div class='ctx'> 		reg_def-&gt;def = raw;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SX9324_REG_AFE_CTRL0:</div><div class='del'>-		ret = device_property_read_string(dev,</div><div class='del'>-				"semtech,cs-idle-sleep", &amp;res);</div><div class='del'>-		if (!ret)</div><div class='del'>-			ret = match_string(sx9324_csidle, ARRAY_SIZE(sx9324_csidle), res);</div><div class='add'>+		ret = device_property_match_property_string(dev, "semtech,cs-idle-sleep",</div><div class='add'>+							    sx9324_csidle,</div><div class='add'>+							    ARRAY_SIZE(sx9324_csidle));</div><div class='ctx'> 		if (ret &gt;= 0) {</div><div class='ctx'> 			reg_def-&gt;def &amp;= ~SX9324_REG_AFE_CTRL0_CSIDLE_MASK;</div><div class='ctx'> 			reg_def-&gt;def |= ret &lt;&lt; SX9324_REG_AFE_CTRL0_CSIDLE_SHIFT;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ret = device_property_read_string(dev,</div><div class='del'>-				"semtech,int-comp-resistor", &amp;res);</div><div class='del'>-		if (ret)</div><div class='del'>-			break;</div><div class='del'>-		ret = match_string(sx9324_rints, ARRAY_SIZE(sx9324_rints), res);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			break;</div><div class='del'>-		reg_def-&gt;def &amp;= ~SX9324_REG_AFE_CTRL0_RINT_MASK;</div><div class='del'>-		reg_def-&gt;def |= ret &lt;&lt; SX9324_REG_AFE_CTRL0_RINT_SHIFT;</div><div class='add'>+		ret = device_property_match_property_string(dev, "semtech,int-comp-resistor",</div><div class='add'>+							    sx9324_rints,</div><div class='add'>+							    ARRAY_SIZE(sx9324_rints));</div><div class='add'>+		if (ret &gt;= 0) {</div><div class='add'>+			reg_def-&gt;def &amp;= ~SX9324_REG_AFE_CTRL0_RINT_MASK;</div><div class='add'>+			reg_def-&gt;def |= ret &lt;&lt; SX9324_REG_AFE_CTRL0_RINT_SHIFT;</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SX9324_REG_AFE_CTRL4:</div><div class='ctx'> 	case SX9324_REG_AFE_CTRL7:</div><div class='head'>diff --git a/drivers/iio/resolver/ad2s1210.c b/drivers/iio/resolver/ad2s1210.c<br/>index 1bd1b950e7cc..a414eef12e5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/resolver/ad2s1210.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/resolver/ad2s1210.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/resolver/ad2s1210.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/resolver/ad2s1210.c</a></div><div class='hunk'>@@ -141,7 +141,7 @@ struct ad2s1210_state {</div><div class='ctx'> 	struct spi_device *sdev;</div><div class='ctx'> 	/** GPIO pin connected to SAMPLE line. */</div><div class='ctx'> 	struct gpio_desc *sample_gpio;</div><div class='del'>-	/** GPIO pins connected to A0 and A1 lines. */</div><div class='add'>+	/** GPIO pins connected to A0 and A1 lines (optional). */</div><div class='ctx'> 	struct gpio_descs *mode_gpios;</div><div class='ctx'> 	/** Used to access config registers. */</div><div class='ctx'> 	struct regmap *regmap;</div><div class='hunk'>@@ -149,6 +149,8 @@ struct ad2s1210_state {</div><div class='ctx'> 	unsigned long clkin_hz;</div><div class='ctx'> 	/** Available raw hysteresis values based on resolution. */</div><div class='ctx'> 	int hysteresis_available[2];</div><div class='add'>+	/* adi,fixed-mode property - only valid when mode_gpios == NULL. */</div><div class='add'>+	enum ad2s1210_mode fixed_mode;</div><div class='ctx'> 	/** The selected resolution */</div><div class='ctx'> 	enum ad2s1210_resolution resolution;</div><div class='ctx'> 	/** Copy of fault register from the previous read. */</div><div class='hunk'>@@ -175,6 +177,9 @@ static int ad2s1210_set_mode(struct ad2s1210_state *st, enum ad2s1210_mode mode)</div><div class='ctx'> 	struct gpio_descs *gpios = st-&gt;mode_gpios;</div><div class='ctx'> 	DECLARE_BITMAP(bitmap, 2);</div><div class='ctx'> </div><div class='add'>+	if (!gpios)</div><div class='add'>+		return mode == st-&gt;fixed_mode ? 0 : -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	bitmap[0] = mode;</div><div class='ctx'> </div><div class='ctx'> 	return gpiod_set_array_value(gpios-&gt;ndescs, gpios-&gt;desc, gpios-&gt;info,</div><div class='hunk'>@@ -276,7 +281,8 @@ static int ad2s1210_regmap_reg_read(void *context, unsigned int reg,</div><div class='ctx'> 	 * parity error. The fault register is read-only and the D7 bit means</div><div class='ctx'> 	 * something else there.</div><div class='ctx'> 	 */</div><div class='del'>-	if (reg != AD2S1210_REG_FAULT &amp;&amp; st-&gt;rx[1] &amp; AD2S1210_ADDRESS_DATA)</div><div class='add'>+	if ((reg &gt; AD2S1210_REG_VELOCITY_LSB &amp;&amp; reg != AD2S1210_REG_FAULT)</div><div class='add'>+	     &amp;&amp; st-&gt;rx[1] &amp; AD2S1210_ADDRESS_DATA)</div><div class='ctx'> 		return -EBADMSG;</div><div class='ctx'> </div><div class='ctx'> 	*val = st-&gt;rx[1];</div><div class='hunk'>@@ -450,21 +456,53 @@ static int ad2s1210_single_conversion(struct iio_dev *indio_dev,</div><div class='ctx'> 	ad2s1210_toggle_sample_line(st);</div><div class='ctx'> 	timestamp = iio_get_time_ns(indio_dev);</div><div class='ctx'> </div><div class='del'>-	switch (chan-&gt;type) {</div><div class='del'>-	case IIO_ANGL:</div><div class='del'>-		ret = ad2s1210_set_mode(st, MOD_POS);</div><div class='del'>-		break;</div><div class='del'>-	case IIO_ANGL_VEL:</div><div class='del'>-		ret = ad2s1210_set_mode(st, MOD_VEL);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	if (st-&gt;fixed_mode == MOD_CONFIG) {</div><div class='add'>+		unsigned int reg_val;</div><div class='add'>+</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_ANGL:</div><div class='add'>+			ret = regmap_bulk_read(st-&gt;regmap,</div><div class='add'>+					       AD2S1210_REG_POSITION_MSB,</div><div class='add'>+					       &amp;st-&gt;sample.raw, 2);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		case IIO_ANGL_VEL:</div><div class='add'>+			ret = regmap_bulk_read(st-&gt;regmap,</div><div class='add'>+					       AD2S1210_REG_VELOCITY_MSB,</div><div class='add'>+					       &amp;st-&gt;sample.raw, 2);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = regmap_read(st-&gt;regmap, AD2S1210_REG_FAULT, &amp;reg_val);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		st-&gt;sample.fault = reg_val;</div><div class='add'>+	} else {</div><div class='add'>+		switch (chan-&gt;type) {</div><div class='add'>+		case IIO_ANGL:</div><div class='add'>+			ret = ad2s1210_set_mode(st, MOD_POS);</div><div class='add'>+			break;</div><div class='add'>+		case IIO_ANGL_VEL:</div><div class='add'>+			ret = ad2s1210_set_mode(st, MOD_VEL);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='ctx'> 	}</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='del'>-	ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='ctx'> </div><div class='ctx'> 	switch (chan-&gt;type) {</div><div class='ctx'> 	case IIO_ANGL:</div><div class='hunk'>@@ -1252,27 +1290,53 @@ static irqreturn_t ad2s1210_trigger_handler(int irq, void *p)</div><div class='ctx'> 	ad2s1210_toggle_sample_line(st);</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(0, indio_dev-&gt;active_scan_mask)) {</div><div class='del'>-		ret = ad2s1210_set_mode(st, MOD_POS);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			goto error_ret;</div><div class='del'>-</div><div class='del'>-		ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			goto error_ret;</div><div class='add'>+		if (st-&gt;fixed_mode == MOD_CONFIG) {</div><div class='add'>+			ret = regmap_bulk_read(st-&gt;regmap,</div><div class='add'>+					       AD2S1210_REG_POSITION_MSB,</div><div class='add'>+					       &amp;st-&gt;sample.raw, 2);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+		} else {</div><div class='add'>+			ret = ad2s1210_set_mode(st, MOD_POS);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+</div><div class='add'>+			ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		memcpy(&amp;st-&gt;scan.chan[chan++], &amp;st-&gt;sample.raw, 2);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(1, indio_dev-&gt;active_scan_mask)) {</div><div class='del'>-		ret = ad2s1210_set_mode(st, MOD_VEL);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			goto error_ret;</div><div class='add'>+		if (st-&gt;fixed_mode == MOD_CONFIG) {</div><div class='add'>+			ret = regmap_bulk_read(st-&gt;regmap,</div><div class='add'>+					       AD2S1210_REG_VELOCITY_MSB,</div><div class='add'>+					       &amp;st-&gt;sample.raw, 2);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+		} else {</div><div class='add'>+			ret = ad2s1210_set_mode(st, MOD_VEL);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+</div><div class='add'>+			ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto error_ret;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		ret = spi_read(st-&gt;sdev, &amp;st-&gt;sample, 3);</div><div class='add'>+		memcpy(&amp;st-&gt;scan.chan[chan++], &amp;st-&gt;sample.raw, 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (st-&gt;fixed_mode == MOD_CONFIG) {</div><div class='add'>+		unsigned int reg_val;</div><div class='add'>+</div><div class='add'>+		ret = regmap_read(st-&gt;regmap, AD2S1210_REG_FAULT, &amp;reg_val);</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='del'>-			goto error_ret;</div><div class='add'>+			return ret;</div><div class='ctx'> </div><div class='del'>-		memcpy(&amp;st-&gt;scan.chan[chan++], &amp;st-&gt;sample.raw, 2);</div><div class='add'>+		st-&gt;sample.fault = reg_val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ad2s1210_push_events(indio_dev, st-&gt;sample.fault, pf-&gt;timestamp);</div><div class='hunk'>@@ -1299,9 +1363,24 @@ static const struct iio_info ad2s1210_info = {</div><div class='ctx'> static int ad2s1210_setup_properties(struct ad2s1210_state *st)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;st-&gt;sdev-&gt;dev;</div><div class='add'>+	const char *str_val;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	ret = device_property_read_string(dev, "adi,fixed-mode", &amp;str_val);</div><div class='add'>+	if (ret == -EINVAL)</div><div class='add'>+		st-&gt;fixed_mode = -1;</div><div class='add'>+	else if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+			"failed to read adi,fixed-mode property\n");</div><div class='add'>+	else {</div><div class='add'>+		if (strcmp(str_val, "config"))</div><div class='add'>+			return dev_err_probe(dev, -EINVAL,</div><div class='add'>+				"only adi,fixed-mode=\"config\" is supported\n");</div><div class='add'>+</div><div class='add'>+		st-&gt;fixed_mode = MOD_CONFIG;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = device_property_read_u32(dev, "assigned-resolution-bits", &amp;val);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return dev_err_probe(dev, ret,</div><div class='hunk'>@@ -1347,6 +1426,7 @@ static int ad2s1210_setup_gpios(struct ad2s1210_state *st)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;st-&gt;sdev-&gt;dev;</div><div class='ctx'> 	struct gpio_descs *resolution_gpios;</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='ctx'> 	DECLARE_BITMAP(bitmap, 2);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1357,12 +1437,21 @@ static int ad2s1210_setup_gpios(struct ad2s1210_state *st)</div><div class='ctx'> 				     "failed to request sample GPIO\n");</div><div class='ctx'> </div><div class='ctx'> 	/* both pins high means that we start in config mode */</div><div class='del'>-	st-&gt;mode_gpios = devm_gpiod_get_array(dev, "mode", GPIOD_OUT_HIGH);</div><div class='add'>+	st-&gt;mode_gpios = devm_gpiod_get_array_optional(dev, "mode",</div><div class='add'>+						       GPIOD_OUT_HIGH);</div><div class='ctx'> 	if (IS_ERR(st-&gt;mode_gpios))</div><div class='ctx'> 		return dev_err_probe(dev, PTR_ERR(st-&gt;mode_gpios),</div><div class='ctx'> 				     "failed to request mode GPIOs\n");</div><div class='ctx'> </div><div class='del'>-	if (st-&gt;mode_gpios-&gt;ndescs != 2)</div><div class='add'>+	if (!st-&gt;mode_gpios &amp;&amp; st-&gt;fixed_mode == -1)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+			"must specify either adi,fixed-mode or mode-gpios\n");</div><div class='add'>+</div><div class='add'>+	if (st-&gt;mode_gpios &amp;&amp; st-&gt;fixed_mode != -1)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL,</div><div class='add'>+			"must specify only one of adi,fixed-mode or mode-gpios\n");</div><div class='add'>+</div><div class='add'>+	if (st-&gt;mode_gpios &amp;&amp; st-&gt;mode_gpios-&gt;ndescs != 2)</div><div class='ctx'> 		return dev_err_probe(dev, -EINVAL,</div><div class='ctx'> 				     "requires exactly 2 mode-gpios\n");</div><div class='ctx'> </div><div class='hunk'>@@ -1393,6 +1482,17 @@ static int ad2s1210_setup_gpios(struct ad2s1210_state *st)</div><div class='ctx'> 					     "failed to set resolution gpios\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* If the optional reset GPIO is present, toggle it to do a hard reset. */</div><div class='add'>+	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(reset_gpio),</div><div class='add'>+				     "failed to request reset GPIO\n");</div><div class='add'>+</div><div class='add'>+	if (reset_gpio) {</div><div class='add'>+		udelay(10);</div><div class='add'>+		gpiod_set_value(reset_gpio, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iio/temperature/Kconfig b/drivers/iio/temperature/Kconfig<br/>index ed384f33e0c7..ed0e4963362f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/temperature/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/temperature/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/temperature/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/Kconfig</a></div><div class='hunk'>@@ -76,6 +76,18 @@ config MLX90632</div><div class='ctx'> 	  This driver can also be built as a module. If so, the module will</div><div class='ctx'> 	  be called mlx90632.</div><div class='ctx'> </div><div class='add'>+config MLX90635</div><div class='add'>+	tristate "MLX90635 contact-less infrared sensor with medical accuracy"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select REGMAP_I2C</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get support for the Melexis</div><div class='add'>+	  MLX90635 contact-less infrared sensor with medical accuracy</div><div class='add'>+	  connected with I2C.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module will</div><div class='add'>+	  be called mlx90635.</div><div class='add'>+</div><div class='ctx'> config TMP006</div><div class='ctx'> 	tristate "TMP006 infrared thermopile sensor"</div><div class='ctx'> 	depends on I2C</div><div class='hunk'>@@ -158,4 +170,14 @@ config MAX31865</div><div class='ctx'> 	  This driver can also be build as a module. If so, the module</div><div class='ctx'> 	  will be called max31865.</div><div class='ctx'> </div><div class='add'>+config MCP9600</div><div class='add'>+	tristate "MCP9600 thermocouple EMF converter"</div><div class='add'>+	depends on I2C</div><div class='add'>+	help</div><div class='add'>+	  If you say yes here you get support for MCP9600</div><div class='add'>+	  thermocouple EMF converter connected via I2C.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module</div><div class='add'>+	  will be called mcp9600.</div><div class='add'>+</div><div class='ctx'> endmenu</div><div class='head'>diff --git a/drivers/iio/temperature/Makefile b/drivers/iio/temperature/Makefile<br/>index dfec8c6d3019..07d6e65709f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iio/temperature/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iio/temperature/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/temperature/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/Makefile</a></div><div class='hunk'>@@ -10,8 +10,10 @@ obj-$(CONFIG_MAXIM_THERMOCOUPLE) += maxim_thermocouple.o</div><div class='ctx'> obj-$(CONFIG_MAX30208) += max30208.o</div><div class='ctx'> obj-$(CONFIG_MAX31856) += max31856.o</div><div class='ctx'> obj-$(CONFIG_MAX31865) += max31865.o</div><div class='add'>+obj-$(CONFIG_MCP9600) += mcp9600.o</div><div class='ctx'> obj-$(CONFIG_MLX90614) += mlx90614.o</div><div class='ctx'> obj-$(CONFIG_MLX90632) += mlx90632.o</div><div class='add'>+obj-$(CONFIG_MLX90632) += mlx90635.o</div><div class='ctx'> obj-$(CONFIG_TMP006) += tmp006.o</div><div class='ctx'> obj-$(CONFIG_TMP007) += tmp007.o</div><div class='ctx'> obj-$(CONFIG_TMP117) += tmp117.o</div><div class='head'>diff --git a/drivers/iio/temperature/mcp9600.c b/drivers/iio/temperature/mcp9600.c<br/>new file mode 100644<br/>index 000000000000..46845804292b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/temperature/mcp9600.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/mcp9600.c</a></div><div class='hunk'>@@ -0,0 +1,139 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * mcp9600.c - Support for Microchip MCP9600 thermocouple EMF converter</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022 Andrew Hepp</div><div class='add'>+ * Author: &lt;andrew.hepp@ahepp.dev&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+/* MCP9600 registers */</div><div class='add'>+#define MCP9600_HOT_JUNCTION 0x0</div><div class='add'>+#define MCP9600_COLD_JUNCTION 0x2</div><div class='add'>+#define MCP9600_DEVICE_ID 0x20</div><div class='add'>+</div><div class='add'>+/* MCP9600 device id value */</div><div class='add'>+#define MCP9600_DEVICE_ID_MCP9600 0x40</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec mcp9600_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.address = MCP9600_HOT_JUNCTION,</div><div class='add'>+		.info_mask_separate =</div><div class='add'>+			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.address = MCP9600_COLD_JUNCTION,</div><div class='add'>+		.channel2 = IIO_MOD_TEMP_AMBIENT,</div><div class='add'>+		.modified = 1,</div><div class='add'>+		.info_mask_separate =</div><div class='add'>+			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mcp9600_data {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mcp9600_read(struct mcp9600_data *data,</div><div class='add'>+			struct iio_chan_spec const *chan, int *val)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_word_swapped(data-&gt;client, chan-&gt;address);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*val = ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mcp9600_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			    struct iio_chan_spec const *chan, int *val,</div><div class='add'>+			    int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct mcp9600_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_RAW:</div><div class='add'>+		ret = mcp9600_read(data, chan, val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		return IIO_VAL_INT;</div><div class='add'>+	case IIO_CHAN_INFO_SCALE:</div><div class='add'>+		*val = 62;</div><div class='add'>+		*val2 = 500000;</div><div class='add'>+		return IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_info mcp9600_info = {</div><div class='add'>+	.read_raw = mcp9600_read_raw,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mcp9600_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	struct mcp9600_data *data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_byte_data(client, MCP9600_DEVICE_ID);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret, "Failed to read device ID\n");</div><div class='add'>+	if (ret != MCP9600_DEVICE_ID_MCP9600)</div><div class='add'>+		dev_warn(&amp;client-&gt;dev, "Expected ID %x, got %x\n",</div><div class='add'>+				MCP9600_DEVICE_ID_MCP9600, ret);</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*data));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	data = iio_priv(indio_dev);</div><div class='add'>+	data-&gt;client = client;</div><div class='add'>+</div><div class='add'>+	indio_dev-&gt;info = &amp;mcp9600_info;</div><div class='add'>+	indio_dev-&gt;name = "mcp9600";</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+	indio_dev-&gt;channels = mcp9600_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(mcp9600_channels);</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(&amp;client-&gt;dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id mcp9600_id[] = {</div><div class='add'>+	{ "mcp9600" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, mcp9600_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id mcp9600_of_match[] = {</div><div class='add'>+	{ .compatible = "microchip,mcp9600" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, mcp9600_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver mcp9600_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "mcp9600",</div><div class='add'>+		.of_match_table = mcp9600_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe = mcp9600_probe,</div><div class='add'>+	.id_table = mcp9600_id</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(mcp9600_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Andrew Hepp &lt;andrew.hepp@ahepp.dev&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Microchip MCP9600 thermocouple EMF converter driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/iio/temperature/mlx90635.c b/drivers/iio/temperature/mlx90635.c<br/>new file mode 100644<br/>index 000000000000..1f5c962c1818<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iio/temperature/mlx90635.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iio/temperature/mlx90635.c</a></div><div class='hunk'>@@ -0,0 +1,1097 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * mlx90635.c - Melexis MLX90635 contactless IR temperature sensor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Melexis &lt;cmo@melexis.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Driver for the Melexis MLX90635 I2C 16-bit IR thermopile sensor</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/jiffies.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/limits.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/math64.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iio/iio.h&gt;</div><div class='add'>+</div><div class='add'>+/* Memory sections addresses */</div><div class='add'>+#define MLX90635_ADDR_RAM	0x0000 /* Start address of ram */</div><div class='add'>+#define MLX90635_ADDR_EEPROM	0x0018 /* Start address of user eeprom */</div><div class='add'>+</div><div class='add'>+/* EEPROM addresses - used at startup */</div><div class='add'>+#define MLX90635_EE_I2C_CFG	0x0018 /* I2C address register initial value */</div><div class='add'>+#define MLX90635_EE_CTRL1	0x001A /* Control register1 initial value */</div><div class='add'>+#define MLX90635_EE_CTRL2	0x001C /* Control register2 initial value */</div><div class='add'>+</div><div class='add'>+#define MLX90635_EE_Ha		0x001E /* Ha customer calib value reg 16bit */</div><div class='add'>+#define MLX90635_EE_Hb		0x0020 /* Hb customer calib value reg 16bit */</div><div class='add'>+#define MLX90635_EE_Fa		0x0026 /* Fa calibration register 32bit */</div><div class='add'>+#define MLX90635_EE_FASCALE	0x002A /* Scaling coefficient for Fa register 16bit */</div><div class='add'>+#define MLX90635_EE_Ga		0x002C /* Ga calibration register 16bit */</div><div class='add'>+#define MLX90635_EE_Fb		0x002E /* Fb calibration register 16bit */</div><div class='add'>+#define MLX90635_EE_Ea		0x0030 /* Ea calibration register 32bit */</div><div class='add'>+#define MLX90635_EE_Eb		0x0034 /* Eb calibration register 32bit */</div><div class='add'>+#define MLX90635_EE_P_G		0x0038 /* P_G calibration register 16bit */</div><div class='add'>+#define MLX90635_EE_P_O		0x003A /* P_O calibration register 16bit */</div><div class='add'>+#define MLX90635_EE_Aa		0x003C /* Aa calibration register 16bit */</div><div class='add'>+#define MLX90635_EE_VERSION	0x003E /* Version bits 4:7 and 12:15 */</div><div class='add'>+#define MLX90635_EE_Gb		0x0040 /* Gb calibration register 16bit */</div><div class='add'>+</div><div class='add'>+/* Device status register - volatile */</div><div class='add'>+#define MLX90635_REG_STATUS	0x0000</div><div class='add'>+#define   MLX90635_STAT_BUSY BIT(6) /* Device busy indicator */</div><div class='add'>+#define   MLX90635_STAT_BRST BIT(5) /* Brown out reset indicator */</div><div class='add'>+#define   MLX90635_STAT_CYCLE_POS GENMASK(4, 2) /* Data position */</div><div class='add'>+#define   MLX90635_STAT_END_CONV BIT(1) /* End of conversion indicator */</div><div class='add'>+#define   MLX90635_STAT_DATA_RDY BIT(0) /* Data ready indicator */</div><div class='add'>+</div><div class='add'>+/* EEPROM control register address - volatile */</div><div class='add'>+#define MLX90635_REG_EE		0x000C</div><div class='add'>+#define   MLX90635_EE_ACTIVE BIT(4) /* Power-on EEPROM */</div><div class='add'>+#define   MLX90635_EE_BUSY_MASK	BIT(15)</div><div class='add'>+</div><div class='add'>+#define MLX90635_REG_CMD	0x0010 /* Command register address */</div><div class='add'>+</div><div class='add'>+/* Control register1 address - volatile */</div><div class='add'>+#define MLX90635_REG_CTRL1	0x0014</div><div class='add'>+#define   MLX90635_CTRL1_REFRESH_RATE_MASK GENMASK(2, 0)</div><div class='add'>+#define   MLX90635_CTRL1_RES_CTRL_MASK GENMASK(4, 3)</div><div class='add'>+#define   MLX90635_CTRL1_TABLE_MASK BIT(15) /* Table select */</div><div class='add'>+</div><div class='add'>+/* Control register2 address - volatile */</div><div class='add'>+#define   MLX90635_REG_CTRL2	0x0016</div><div class='add'>+#define   MLX90635_CTRL2_BURST_CNT_MASK GENMASK(10, 6) /* Burst count */</div><div class='add'>+#define   MLX90635_CTRL2_MODE_MASK GENMASK(12, 11) /* Power mode */</div><div class='add'>+#define   MLX90635_CTRL2_SOB_MASK BIT(15)</div><div class='add'>+</div><div class='add'>+/* PowerModes statuses */</div><div class='add'>+#define MLX90635_PWR_STATUS_HALT 0</div><div class='add'>+#define MLX90635_PWR_STATUS_SLEEP_STEP 1</div><div class='add'>+#define MLX90635_PWR_STATUS_STEP 2</div><div class='add'>+#define MLX90635_PWR_STATUS_CONTINUOUS 3</div><div class='add'>+</div><div class='add'>+/* Measurement data addresses */</div><div class='add'>+#define MLX90635_RESULT_1   0x0002</div><div class='add'>+#define MLX90635_RESULT_2   0x0004</div><div class='add'>+#define MLX90635_RESULT_3   0x0006</div><div class='add'>+#define MLX90635_RESULT_4   0x0008</div><div class='add'>+#define MLX90635_RESULT_5   0x000A</div><div class='add'>+</div><div class='add'>+/* Timings (ms) */</div><div class='add'>+#define MLX90635_TIMING_RST_MIN 200 /* Minimum time after addressed reset command */</div><div class='add'>+#define MLX90635_TIMING_RST_MAX 250 /* Maximum time after addressed reset command */</div><div class='add'>+#define MLX90635_TIMING_POLLING 10000 /* Time between bit polling*/</div><div class='add'>+#define MLX90635_TIMING_EE_ACTIVE_MIN 100 /* Minimum time after activating the EEPROM for read */</div><div class='add'>+#define MLX90635_TIMING_EE_ACTIVE_MAX 150 /* Maximum time after activating the EEPROM for read */</div><div class='add'>+</div><div class='add'>+/* Magic constants */</div><div class='add'>+#define MLX90635_ID_DSPv1 0x01 /* EEPROM DSP version */</div><div class='add'>+#define MLX90635_RESET_CMD  0x0006 /* Reset sensor (address or global) */</div><div class='add'>+#define MLX90635_MAX_MEAS_NUM   31 /* Maximum number of measurements in list */</div><div class='add'>+#define MLX90635_PTAT_DIV 12   /* Used to divide the PTAT value in pre-processing */</div><div class='add'>+#define MLX90635_IR_DIV 24   /* Used to divide the IR value in pre-processing */</div><div class='add'>+#define MLX90635_SLEEP_DELAY_MS 6000 /* Autosleep delay */</div><div class='add'>+#define MLX90635_MEAS_MAX_TIME 2000 /* Max measurement time in ms for the lowest refresh rate */</div><div class='add'>+#define MLX90635_READ_RETRIES 100 /* Number of read retries before quitting with timeout error */</div><div class='add'>+#define MLX90635_VERSION_MASK (GENMASK(15, 12) | GENMASK(7, 4))</div><div class='add'>+#define MLX90635_DSP_VERSION(reg) (((reg &amp; GENMASK(14, 12)) &gt;&gt; 9) | ((reg &amp; GENMASK(6, 4)) &gt;&gt; 4))</div><div class='add'>+#define MLX90635_DSP_FIXED BIT(15)</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct mlx90635_data - private data for the MLX90635 device</div><div class='add'>+ * @client: I2C client of the device</div><div class='add'>+ * @lock: Internal mutex because multiple reads are needed for single triggered</div><div class='add'>+ *	  measurement to ensure data consistency</div><div class='add'>+ * @regmap: Regmap of the device registers</div><div class='add'>+ * @regmap_ee: Regmap of the device EEPROM which can be cached</div><div class='add'>+ * @emissivity: Object emissivity from 0 to 1000 where 1000 = 1</div><div class='add'>+ * @regulator: Regulator of the device</div><div class='add'>+ * @powerstatus: Current POWER status of the device</div><div class='add'>+ * @interaction_ts: Timestamp of the last temperature read that is used</div><div class='add'>+ *		    for power management in jiffies</div><div class='add'>+ */</div><div class='add'>+struct mlx90635_data {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct regmap *regmap_ee;</div><div class='add'>+	u16 emissivity;</div><div class='add'>+	struct regulator *regulator;</div><div class='add'>+	int powerstatus;</div><div class='add'>+	unsigned long interaction_ts;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_range mlx90635_volatile_reg_range[] = {</div><div class='add'>+	regmap_reg_range(MLX90635_REG_STATUS, MLX90635_REG_STATUS),</div><div class='add'>+	regmap_reg_range(MLX90635_RESULT_1, MLX90635_RESULT_5),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_EE, MLX90635_REG_EE),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_CMD, MLX90635_REG_CMD),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_CTRL1, MLX90635_REG_CTRL2),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_access_table mlx90635_volatile_regs_tbl = {</div><div class='add'>+	.yes_ranges = mlx90635_volatile_reg_range,</div><div class='add'>+	.n_yes_ranges = ARRAY_SIZE(mlx90635_volatile_reg_range),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_range mlx90635_read_reg_range[] = {</div><div class='add'>+	regmap_reg_range(MLX90635_REG_STATUS, MLX90635_REG_STATUS),</div><div class='add'>+	regmap_reg_range(MLX90635_RESULT_1, MLX90635_RESULT_5),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_EE, MLX90635_REG_EE),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_CMD, MLX90635_REG_CMD),</div><div class='add'>+	regmap_reg_range(MLX90635_REG_CTRL1, MLX90635_REG_CTRL2),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_access_table mlx90635_readable_regs_tbl = {</div><div class='add'>+	.yes_ranges = mlx90635_read_reg_range,</div><div class='add'>+	.n_yes_ranges = ARRAY_SIZE(mlx90635_read_reg_range),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_range mlx90635_no_write_reg_range[] = {</div><div class='add'>+	regmap_reg_range(MLX90635_RESULT_1, MLX90635_RESULT_5),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_access_table mlx90635_writeable_regs_tbl = {</div><div class='add'>+	.no_ranges = mlx90635_no_write_reg_range,</div><div class='add'>+	.n_no_ranges = ARRAY_SIZE(mlx90635_no_write_reg_range),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config mlx90635_regmap = {</div><div class='add'>+	.name = "mlx90635-registers",</div><div class='add'>+	.reg_stride = 1,</div><div class='add'>+	.reg_bits = 16,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+</div><div class='add'>+	.volatile_table = &amp;mlx90635_volatile_regs_tbl,</div><div class='add'>+	.rd_table = &amp;mlx90635_readable_regs_tbl,</div><div class='add'>+	.wr_table = &amp;mlx90635_writeable_regs_tbl,</div><div class='add'>+</div><div class='add'>+	.use_single_read = true,</div><div class='add'>+	.use_single_write = true,</div><div class='add'>+	.can_multi_write = false,</div><div class='add'>+	.reg_format_endian = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.val_format_endian = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.cache_type = REGCACHE_RBTREE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_range mlx90635_read_ee_range[] = {</div><div class='add'>+	regmap_reg_range(MLX90635_EE_I2C_CFG, MLX90635_EE_CTRL2),</div><div class='add'>+	regmap_reg_range(MLX90635_EE_Ha, MLX90635_EE_Gb),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_access_table mlx90635_readable_ees_tbl = {</div><div class='add'>+	.yes_ranges = mlx90635_read_ee_range,</div><div class='add'>+	.n_yes_ranges = ARRAY_SIZE(mlx90635_read_ee_range),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_range mlx90635_no_write_ee_range[] = {</div><div class='add'>+	regmap_reg_range(MLX90635_ADDR_EEPROM, MLX90635_EE_Gb),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_access_table mlx90635_writeable_ees_tbl = {</div><div class='add'>+	.no_ranges = mlx90635_no_write_ee_range,</div><div class='add'>+	.n_no_ranges = ARRAY_SIZE(mlx90635_no_write_ee_range),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config mlx90635_regmap_ee = {</div><div class='add'>+	.name = "mlx90635-eeprom",</div><div class='add'>+	.reg_stride = 1,</div><div class='add'>+	.reg_bits = 16,</div><div class='add'>+	.val_bits = 16,</div><div class='add'>+</div><div class='add'>+	.volatile_table = NULL,</div><div class='add'>+	.rd_table = &amp;mlx90635_readable_ees_tbl,</div><div class='add'>+	.wr_table = &amp;mlx90635_writeable_ees_tbl,</div><div class='add'>+</div><div class='add'>+	.use_single_read = true,</div><div class='add'>+	.use_single_write = true,</div><div class='add'>+	.can_multi_write = false,</div><div class='add'>+	.reg_format_endian = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.val_format_endian = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.cache_type = REGCACHE_RBTREE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * mlx90635_reset_delay() - Give the mlx90635 some time to reset properly</div><div class='add'>+ * If this is not done, the following I2C command(s) will not be accepted.</div><div class='add'>+ */</div><div class='add'>+static void mlx90635_reset_delay(void)</div><div class='add'>+{</div><div class='add'>+	usleep_range(MLX90635_TIMING_RST_MIN, MLX90635_TIMING_RST_MAX);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_pwr_sleep_step(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;powerstatus == MLX90635_PWR_STATUS_SLEEP_STEP)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_CTRL2, MLX90635_CTRL2_MODE_MASK,</div><div class='add'>+				FIELD_PREP(MLX90635_CTRL2_MODE_MASK, MLX90635_PWR_STATUS_SLEEP_STEP));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;powerstatus = MLX90635_PWR_STATUS_SLEEP_STEP;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_pwr_continuous(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (data-&gt;powerstatus == MLX90635_PWR_STATUS_CONTINUOUS)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_CTRL2, MLX90635_CTRL2_MODE_MASK,</div><div class='add'>+				FIELD_PREP(MLX90635_CTRL2_MODE_MASK, MLX90635_PWR_STATUS_CONTINUOUS));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	data-&gt;powerstatus = MLX90635_PWR_STATUS_CONTINUOUS;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_ee_register(struct regmap *regmap, u16 reg_lsb,</div><div class='add'>+				     s32 *reg_value)</div><div class='add'>+{</div><div class='add'>+	unsigned int read;</div><div class='add'>+	u32 value;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, reg_lsb + 2, &amp;read);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	value = read;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, reg_lsb, &amp;read);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*reg_value = (read &lt;&lt; 16) | (value &amp; 0xffff);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_ee_ambient(struct regmap *regmap, s16 *PG, s16 *PO, s16 *Gb)</div><div class='add'>+{</div><div class='add'>+	unsigned int read_tmp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_P_O, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*PO = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_P_G, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*PG = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Gb, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Gb = (u16)read_tmp;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_ee_object(struct regmap *regmap, u32 *Ea, u32 *Eb, u32 *Fa, s16 *Fb,</div><div class='add'>+				   s16 *Ga, s16 *Gb, s16 *Ha, s16 *Hb, u16 *Fa_scale)</div><div class='add'>+{</div><div class='add'>+	unsigned int read_tmp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_register(regmap, MLX90635_EE_Ea, Ea);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_register(regmap, MLX90635_EE_Eb, Eb);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_register(regmap, MLX90635_EE_Fa, Fa);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Ha, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Ha = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Hb, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Hb = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Ga, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Ga = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Gb, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Gb = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_Fb, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Fb = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_EE_FASCALE, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*Fa_scale = (u16)read_tmp;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_calculate_dataset_ready_time(struct mlx90635_data *data, int *refresh_time)</div><div class='add'>+{</div><div class='add'>+	unsigned int reg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, MLX90635_REG_CTRL1, &amp;reg);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*refresh_time = 2 * (MLX90635_MEAS_MAX_TIME &gt;&gt; FIELD_GET(MLX90635_CTRL1_REFRESH_RATE_MASK, reg)) + 80;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_perform_measurement_burst(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	unsigned int reg_status;</div><div class='add'>+	int refresh_time;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_STATUS,</div><div class='add'>+				MLX90635_STAT_END_CONV, MLX90635_STAT_END_CONV);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_calculate_dataset_ready_time(data, &amp;refresh_time);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_CTRL2,</div><div class='add'>+				FIELD_PREP(MLX90635_CTRL2_SOB_MASK, 1),</div><div class='add'>+				FIELD_PREP(MLX90635_CTRL2_SOB_MASK, 1));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	msleep(refresh_time); /* Wait minimum time for dataset to be ready */</div><div class='add'>+</div><div class='add'>+	ret = regmap_read_poll_timeout(data-&gt;regmap, MLX90635_REG_STATUS, reg_status,</div><div class='add'>+				       (!(reg_status &amp; MLX90635_STAT_END_CONV)) == 0,</div><div class='add'>+				       MLX90635_TIMING_POLLING, MLX90635_READ_RETRIES * 10000);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev, "data not ready");</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_ambient_raw(struct regmap *regmap,</div><div class='add'>+				     s16 *ambient_new_raw, s16 *ambient_old_raw)</div><div class='add'>+{</div><div class='add'>+	unsigned int read_tmp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_RESULT_2, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*ambient_new_raw = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_RESULT_3, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*ambient_old_raw = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_object_raw(struct regmap *regmap, s16 *object_raw)</div><div class='add'>+{</div><div class='add'>+	unsigned int read_tmp;</div><div class='add'>+	s16 read;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_RESULT_1, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	read = (s16)read_tmp;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(regmap, MLX90635_RESULT_4, &amp;read_tmp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+	*object_raw = (read - (s16)read_tmp) / 2;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_all_channel(struct mlx90635_data *data,</div><div class='add'>+				     s16 *ambient_new_raw, s16 *ambient_old_raw,</div><div class='add'>+				     s16 *object_raw)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;data-&gt;lock);</div><div class='add'>+	if (data-&gt;powerstatus == MLX90635_PWR_STATUS_SLEEP_STEP) {</div><div class='add'>+		/* Trigger measurement in Sleep Step mode */</div><div class='add'>+		ret = mlx90635_perform_measurement_burst(data);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto read_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ambient_raw(data-&gt;regmap, ambient_new_raw,</div><div class='add'>+					ambient_old_raw);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto read_unlock;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_object_raw(data-&gt;regmap, object_raw);</div><div class='add'>+read_unlock:</div><div class='add'>+	mutex_unlock(&amp;data-&gt;lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s64 mlx90635_preprocess_temp_amb(s16 ambient_new_raw,</div><div class='add'>+					s16 ambient_old_raw, s16 Gb)</div><div class='add'>+{</div><div class='add'>+	s64 VR_Ta, kGb, tmp;</div><div class='add'>+</div><div class='add'>+	kGb = ((s64)Gb * 1000LL) &gt;&gt; 10ULL;</div><div class='add'>+	VR_Ta = (s64)ambient_old_raw * 1000000LL +</div><div class='add'>+		kGb * div64_s64(((s64)ambient_new_raw * 1000LL),</div><div class='add'>+			(MLX90635_PTAT_DIV));</div><div class='add'>+	tmp = div64_s64(</div><div class='add'>+			 div64_s64(((s64)ambient_new_raw * 1000000000000LL),</div><div class='add'>+				   (MLX90635_PTAT_DIV)), VR_Ta);</div><div class='add'>+	return div64_s64(tmp &lt;&lt; 19ULL, 1000LL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s64 mlx90635_preprocess_temp_obj(s16 object_raw,</div><div class='add'>+					s16 ambient_new_raw,</div><div class='add'>+					s16 ambient_old_raw, s16 Gb)</div><div class='add'>+{</div><div class='add'>+	s64 VR_IR, kGb, tmp;</div><div class='add'>+</div><div class='add'>+	kGb = ((s64)Gb * 1000LL) &gt;&gt; 10ULL;</div><div class='add'>+	VR_IR = (s64)ambient_old_raw * 1000000LL +</div><div class='add'>+		kGb * (div64_s64((s64)ambient_new_raw * 1000LL,</div><div class='add'>+			MLX90635_PTAT_DIV));</div><div class='add'>+	tmp = div64_s64(</div><div class='add'>+			div64_s64((s64)(object_raw * 1000000LL),</div><div class='add'>+				   MLX90635_IR_DIV) * 1000000LL,</div><div class='add'>+			VR_IR);</div><div class='add'>+	return div64_s64((tmp &lt;&lt; 19ULL), 1000LL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s32 mlx90635_calc_temp_ambient(s16 ambient_new_raw, s16 ambient_old_raw,</div><div class='add'>+				      u16 P_G, u16 P_O, s16 Gb)</div><div class='add'>+{</div><div class='add'>+	s64 kPG, kPO, AMB;</div><div class='add'>+</div><div class='add'>+	AMB = mlx90635_preprocess_temp_amb(ambient_new_raw, ambient_old_raw,</div><div class='add'>+					   Gb);</div><div class='add'>+	kPG = ((s64)P_G * 1000000LL) &gt;&gt; 9ULL;</div><div class='add'>+	kPO = AMB - (((s64)P_O * 1000LL) &gt;&gt; 1ULL);</div><div class='add'>+</div><div class='add'>+	return 30 * 1000LL + div64_s64(kPO * 1000000LL, kPG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s32 mlx90635_calc_temp_object_iteration(s32 prev_object_temp, s64 object,</div><div class='add'>+					       s64 TAdut, s64 TAdut4, s16 Ga,</div><div class='add'>+					       u32 Fa, u16 Fa_scale, s16 Fb,</div><div class='add'>+					       s16 Ha, s16 Hb, u16 emissivity)</div><div class='add'>+{</div><div class='add'>+	s64 calcedGa, calcedGb, calcedFa, Alpha_corr;</div><div class='add'>+	s64 Ha_customer, Hb_customer;</div><div class='add'>+</div><div class='add'>+	Ha_customer = ((s64)Ha * 1000000LL) &gt;&gt; 14ULL;</div><div class='add'>+	Hb_customer = ((s64)Hb * 100) &gt;&gt; 10ULL;</div><div class='add'>+</div><div class='add'>+	calcedGa = ((s64)((s64)Ga * (prev_object_temp - 35 * 1000LL)</div><div class='add'>+			     * 1000LL)) &gt;&gt; 24LL;</div><div class='add'>+	calcedGb = ((s64)(Fb * (TAdut - 30 * 1000000LL))) &gt;&gt; 24LL;</div><div class='add'>+</div><div class='add'>+	Alpha_corr = ((s64)((s64)Fa * Ha_customer * 10000LL) &gt;&gt; Fa_scale);</div><div class='add'>+	Alpha_corr *= ((s64)(1 * 1000000LL + calcedGa + calcedGb));</div><div class='add'>+</div><div class='add'>+	Alpha_corr = div64_s64(Alpha_corr, 1000LL);</div><div class='add'>+	Alpha_corr *= emissivity;</div><div class='add'>+	Alpha_corr = div64_s64(Alpha_corr, 100LL);</div><div class='add'>+	calcedFa = div64_s64((s64)object * 100000000000LL, Alpha_corr);</div><div class='add'>+</div><div class='add'>+	return (int_sqrt64(int_sqrt64(calcedFa * 100000000LL + TAdut4))</div><div class='add'>+		- 27315 - Hb_customer) * 10;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s64 mlx90635_calc_ta4(s64 TAdut, s64 scale)</div><div class='add'>+{</div><div class='add'>+	return (div64_s64(TAdut, scale) + 27315) *</div><div class='add'>+		(div64_s64(TAdut, scale) + 27315) *</div><div class='add'>+		(div64_s64(TAdut, scale) + 27315) *</div><div class='add'>+		(div64_s64(TAdut, scale) + 27315);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s32 mlx90635_calc_temp_object(s64 object, s64 ambient, u32 Ea, u32 Eb,</div><div class='add'>+				     s16 Ga, u32 Fa, u16 Fa_scale, s16 Fb, s16 Ha, s16 Hb,</div><div class='add'>+				     u16 tmp_emi)</div><div class='add'>+{</div><div class='add'>+	s64 kTA, kTA0, TAdut, TAdut4;</div><div class='add'>+	s64 temp = 35000;</div><div class='add'>+	s8 i;</div><div class='add'>+</div><div class='add'>+	kTA = (Ea * 1000LL) &gt;&gt; 16LL;</div><div class='add'>+	kTA0 = (Eb * 1000LL) &gt;&gt; 8LL;</div><div class='add'>+	TAdut = div64_s64(((ambient - kTA0) * 1000000LL), kTA) + 30 * 1000000LL;</div><div class='add'>+	TAdut4 = mlx90635_calc_ta4(TAdut, 10000LL);</div><div class='add'>+</div><div class='add'>+	/* Iterations of calculation as described in datasheet */</div><div class='add'>+	for (i = 0; i &lt; 5; ++i) {</div><div class='add'>+		temp = mlx90635_calc_temp_object_iteration(temp, object, TAdut, TAdut4,</div><div class='add'>+							   Ga, Fa, Fa_scale, Fb, Ha, Hb,</div><div class='add'>+							   tmp_emi);</div><div class='add'>+	}</div><div class='add'>+	return temp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_calc_object(struct mlx90635_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	s16 ambient_new_raw, ambient_old_raw, object_raw;</div><div class='add'>+	s16 Fb, Ga, Gb, Ha, Hb;</div><div class='add'>+	s64 object, ambient;</div><div class='add'>+	u32 Ea, Eb, Fa;</div><div class='add'>+	u16 Fa_scale;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_object(data-&gt;regmap_ee, &amp;Ea, &amp;Eb, &amp;Fa, &amp;Fb, &amp;Ga, &amp;Gb, &amp;Ha, &amp;Hb, &amp;Fa_scale);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_all_channel(data,</div><div class='add'>+					&amp;ambient_new_raw, &amp;ambient_old_raw,</div><div class='add'>+					&amp;object_raw);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ambient = mlx90635_preprocess_temp_amb(ambient_new_raw,</div><div class='add'>+					       ambient_old_raw, Gb);</div><div class='add'>+	object = mlx90635_preprocess_temp_obj(object_raw,</div><div class='add'>+					      ambient_new_raw,</div><div class='add'>+					      ambient_old_raw, Gb);</div><div class='add'>+</div><div class='add'>+	*val = mlx90635_calc_temp_object(object, ambient, Ea, Eb, Ga, Fa, Fa_scale, Fb,</div><div class='add'>+					 Ha, Hb, data-&gt;emissivity);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_calc_ambient(struct mlx90635_data *data, int *val)</div><div class='add'>+{</div><div class='add'>+	s16 ambient_new_raw, ambient_old_raw;</div><div class='add'>+	s16 PG, PO, Gb;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_ambient(data-&gt;regmap_ee, &amp;PG, &amp;PO, &amp;Gb);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;data-&gt;lock);</div><div class='add'>+	if (data-&gt;powerstatus == MLX90635_PWR_STATUS_SLEEP_STEP) {</div><div class='add'>+		ret = mlx90635_perform_measurement_burst(data);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto read_ambient_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ambient_raw(data-&gt;regmap, &amp;ambient_new_raw,</div><div class='add'>+					&amp;ambient_old_raw);</div><div class='add'>+read_ambient_unlock:</div><div class='add'>+	mutex_unlock(&amp;data-&gt;lock);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*val = mlx90635_calc_temp_ambient(ambient_new_raw, ambient_old_raw,</div><div class='add'>+					  PG, PO, Gb);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_get_refresh_rate(struct mlx90635_data *data,</div><div class='add'>+				     unsigned int *refresh_rate)</div><div class='add'>+{</div><div class='add'>+	unsigned int reg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap, MLX90635_REG_CTRL1, &amp;reg);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*refresh_rate = FIELD_GET(MLX90635_CTRL1_REFRESH_RATE_MASK, reg);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct {</div><div class='add'>+	int val;</div><div class='add'>+	int val2;</div><div class='add'>+} mlx90635_freqs[] = {</div><div class='add'>+	{ 0, 200000 },</div><div class='add'>+	{ 0, 500000 },</div><div class='add'>+	{ 0, 900000 },</div><div class='add'>+	{ 1, 700000 },</div><div class='add'>+	{ 3, 0 },</div><div class='add'>+	{ 4, 800000 },</div><div class='add'>+	{ 6, 900000 },</div><div class='add'>+	{ 8, 900000 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * mlx90635_pm_interaction_wakeup() - Measure time between user interactions to change powermode</div><div class='add'>+ * @data: pointer to mlx90635_data object containing interaction_ts information</div><div class='add'>+ *</div><div class='add'>+ * Switch to continuous mode when interaction is faster than MLX90635_MEAS_MAX_TIME. Update the</div><div class='add'>+ * interaction_ts for each function call with the jiffies to enable measurement between function</div><div class='add'>+ * calls. Initial value of the interaction_ts needs to be set before this function call.</div><div class='add'>+ */</div><div class='add'>+static int mlx90635_pm_interaction_wakeup(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	unsigned long now;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	now = jiffies;</div><div class='add'>+	if (time_in_range(now, data-&gt;interaction_ts,</div><div class='add'>+			  data-&gt;interaction_ts +</div><div class='add'>+			  msecs_to_jiffies(MLX90635_MEAS_MAX_TIME + 100))) {</div><div class='add'>+		ret = mlx90635_pwr_continuous(data);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	data-&gt;interaction_ts = now;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_raw(struct iio_dev *indio_dev,</div><div class='add'>+			     struct iio_chan_spec const *channel, int *val,</div><div class='add'>+			     int *val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+	int cr;</div><div class='add'>+</div><div class='add'>+	pm_runtime_get_sync(&amp;data-&gt;client-&gt;dev);</div><div class='add'>+	ret = mlx90635_pm_interaction_wakeup(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto mlx90635_read_raw_pm;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_PROCESSED:</div><div class='add'>+		switch (channel-&gt;channel2) {</div><div class='add'>+		case IIO_MOD_TEMP_AMBIENT:</div><div class='add'>+			ret = mlx90635_calc_ambient(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto mlx90635_read_raw_pm;</div><div class='add'>+</div><div class='add'>+			ret = IIO_VAL_INT;</div><div class='add'>+			break;</div><div class='add'>+		case IIO_MOD_TEMP_OBJECT:</div><div class='add'>+			ret = mlx90635_calc_object(data, val);</div><div class='add'>+			if (ret &lt; 0)</div><div class='add'>+				goto mlx90635_read_raw_pm;</div><div class='add'>+</div><div class='add'>+			ret = IIO_VAL_INT;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case IIO_CHAN_INFO_CALIBEMISSIVITY:</div><div class='add'>+		if (data-&gt;emissivity == 1000) {</div><div class='add'>+			*val = 1;</div><div class='add'>+			*val2 = 0;</div><div class='add'>+		} else {</div><div class='add'>+			*val = 0;</div><div class='add'>+			*val2 = data-&gt;emissivity * 1000;</div><div class='add'>+		}</div><div class='add'>+		ret = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		break;</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		ret = mlx90635_get_refresh_rate(data, &amp;cr);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto mlx90635_read_raw_pm;</div><div class='add'>+</div><div class='add'>+		*val = mlx90635_freqs[cr].val;</div><div class='add'>+		*val2 = mlx90635_freqs[cr].val2;</div><div class='add'>+		ret = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+mlx90635_read_raw_pm:</div><div class='add'>+	pm_runtime_mark_last_busy(&amp;data-&gt;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;data-&gt;client-&gt;dev);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_write_raw(struct iio_dev *indio_dev,</div><div class='add'>+			      struct iio_chan_spec const *channel, int val,</div><div class='add'>+			      int val2, long mask)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = iio_priv(indio_dev);</div><div class='add'>+	int ret;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_CALIBEMISSIVITY:</div><div class='add'>+		/* Confirm we are within 0 and 1.0 */</div><div class='add'>+		if (val &lt; 0 || val2 &lt; 0 || val &gt; 1 ||</div><div class='add'>+		    (val == 1 &amp;&amp; val2 != 0))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		data-&gt;emissivity = val * 1000 + val2 / 1000;</div><div class='add'>+		return 0;</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(mlx90635_freqs); i++) {</div><div class='add'>+			if (val == mlx90635_freqs[i].val &amp;&amp;</div><div class='add'>+			    val2 == mlx90635_freqs[i].val2)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+		if (i == ARRAY_SIZE(mlx90635_freqs))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_CTRL1,</div><div class='add'>+					MLX90635_CTRL1_REFRESH_RATE_MASK, i);</div><div class='add'>+</div><div class='add'>+		return ret;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_read_avail(struct iio_dev *indio_dev,</div><div class='add'>+			       struct iio_chan_spec const *chan,</div><div class='add'>+			       const int **vals, int *type, int *length,</div><div class='add'>+			       long mask)</div><div class='add'>+{</div><div class='add'>+	switch (mask) {</div><div class='add'>+	case IIO_CHAN_INFO_SAMP_FREQ:</div><div class='add'>+		*vals = (int *)mlx90635_freqs;</div><div class='add'>+		*type = IIO_VAL_INT_PLUS_MICRO;</div><div class='add'>+		*length = 2 * ARRAY_SIZE(mlx90635_freqs);</div><div class='add'>+		return IIO_AVAIL_LIST;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iio_chan_spec mlx90635_channels[] = {</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.modified = 1,</div><div class='add'>+		.channel2 = IIO_MOD_TEMP_AMBIENT,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),</div><div class='add'>+		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.type = IIO_TEMP,</div><div class='add'>+		.modified = 1,</div><div class='add'>+		.channel2 = IIO_MOD_TEMP_OBJECT,</div><div class='add'>+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |</div><div class='add'>+			BIT(IIO_CHAN_INFO_CALIBEMISSIVITY),</div><div class='add'>+		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),</div><div class='add'>+		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct iio_info mlx90635_info = {</div><div class='add'>+	.read_raw = mlx90635_read_raw,</div><div class='add'>+	.write_raw = mlx90635_write_raw,</div><div class='add'>+	.read_avail = mlx90635_read_avail,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void mlx90635_sleep(void *_data)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = _data;</div><div class='add'>+</div><div class='add'>+	mlx90635_pwr_sleep_step(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_suspend(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	return mlx90635_pwr_sleep_step(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_wakeup(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	s16 Fb, Ga, Gb, Ha, Hb, PG, PO;</div><div class='add'>+	unsigned int dsp_version;</div><div class='add'>+	u32 Ea, Eb, Fa;</div><div class='add'>+	u16 Fa_scale;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	regcache_cache_bypass(data-&gt;regmap_ee, false);</div><div class='add'>+	regcache_cache_only(data-&gt;regmap_ee, false);</div><div class='add'>+	regcache_cache_only(data-&gt;regmap, false);</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_pwr_continuous(data);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev, "Switch to continuous mode failed\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	ret = regmap_write_bits(data-&gt;regmap, MLX90635_REG_EE,</div><div class='add'>+				MLX90635_EE_ACTIVE, MLX90635_EE_ACTIVE);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev, "Powering EEPROM failed\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	usleep_range(MLX90635_TIMING_EE_ACTIVE_MIN, MLX90635_TIMING_EE_ACTIVE_MAX);</div><div class='add'>+</div><div class='add'>+	regcache_mark_dirty(data-&gt;regmap_ee);</div><div class='add'>+</div><div class='add'>+	ret = regcache_sync(data-&gt;regmap_ee);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev,</div><div class='add'>+			"Failed to sync cache: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_ambient(data-&gt;regmap_ee, &amp;PG, &amp;PO, &amp;Gb);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev,</div><div class='add'>+			"Failed to read to cache Ambient coefficients EEPROM region: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_read_ee_object(data-&gt;regmap_ee, &amp;Ea, &amp;Eb, &amp;Fa, &amp;Fb, &amp;Ga, &amp;Gb, &amp;Ha, &amp;Hb, &amp;Fa_scale);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev,</div><div class='add'>+			"Failed to read to cache Object coefficients EEPROM region: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(data-&gt;regmap_ee, MLX90635_EE_VERSION, &amp;dsp_version);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;data-&gt;client-&gt;dev,</div><div class='add'>+			"Failed to read to cache of EEPROM version: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	regcache_cache_only(data-&gt;regmap_ee, true);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlx90635_disable_regulator(void *_data)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = _data;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_disable(data-&gt;regulator);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(regmap_get_device(data-&gt;regmap),</div><div class='add'>+			"Failed to disable power regulator: %d\n", ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_enable_regulator(struct mlx90635_data *data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_enable(data-&gt;regulator);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(regmap_get_device(data-&gt;regmap), "Failed to enable power regulator!\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mlx90635_reset_delay();</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *mlx90635;</div><div class='add'>+	struct iio_dev *indio_dev;</div><div class='add'>+	unsigned int dsp_version;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct regmap *regmap_ee;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	indio_dev = devm_iio_device_alloc(&amp;client-&gt;dev, sizeof(*mlx90635));</div><div class='add'>+	if (!indio_dev)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, -ENOMEM, "failed to allocate device\n");</div><div class='add'>+</div><div class='add'>+	regmap = devm_regmap_init_i2c(client, &amp;mlx90635_regmap);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(regmap),</div><div class='add'>+				     "failed to allocate regmap\n");</div><div class='add'>+</div><div class='add'>+	regmap_ee = devm_regmap_init_i2c(client, &amp;mlx90635_regmap_ee);</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(regmap),</div><div class='add'>+				     "failed to allocate regmap\n");</div><div class='add'>+</div><div class='add'>+	mlx90635 = iio_priv(indio_dev);</div><div class='add'>+	i2c_set_clientdata(client, indio_dev);</div><div class='add'>+	mlx90635-&gt;client = client;</div><div class='add'>+	mlx90635-&gt;regmap = regmap;</div><div class='add'>+	mlx90635-&gt;regmap_ee = regmap_ee;</div><div class='add'>+	mlx90635-&gt;powerstatus = MLX90635_PWR_STATUS_SLEEP_STEP;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;mlx90635-&gt;lock);</div><div class='add'>+	indio_dev-&gt;name = "mlx90635";</div><div class='add'>+	indio_dev-&gt;modes = INDIO_DIRECT_MODE;</div><div class='add'>+	indio_dev-&gt;info = &amp;mlx90635_info;</div><div class='add'>+	indio_dev-&gt;channels = mlx90635_channels;</div><div class='add'>+	indio_dev-&gt;num_channels = ARRAY_SIZE(mlx90635_channels);</div><div class='add'>+</div><div class='add'>+	mlx90635-&gt;regulator = devm_regulator_get(&amp;client-&gt;dev, "vdd");</div><div class='add'>+	if (IS_ERR(mlx90635-&gt;regulator))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(mlx90635-&gt;regulator),</div><div class='add'>+				     "failed to get vdd regulator");</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_enable_regulator(mlx90635);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_add_action_or_reset(&amp;client-&gt;dev, mlx90635_disable_regulator,</div><div class='add'>+				       mlx90635);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "failed to setup regulator cleanup action\n");</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_wakeup(mlx90635);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret, "wakeup failed\n");</div><div class='add'>+</div><div class='add'>+	ret = devm_add_action_or_reset(&amp;client-&gt;dev, mlx90635_sleep, mlx90635);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "failed to setup low power cleanup\n");</div><div class='add'>+</div><div class='add'>+	ret = regmap_read(mlx90635-&gt;regmap_ee, MLX90635_EE_VERSION, &amp;dsp_version);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret, "read of version failed\n");</div><div class='add'>+</div><div class='add'>+	dsp_version = dsp_version &amp; MLX90635_VERSION_MASK;</div><div class='add'>+</div><div class='add'>+	if (FIELD_GET(MLX90635_DSP_FIXED, dsp_version)) {</div><div class='add'>+		if (MLX90635_DSP_VERSION(dsp_version) == MLX90635_ID_DSPv1) {</div><div class='add'>+			dev_dbg(&amp;client-&gt;dev,</div><div class='add'>+				"Detected DSP v1 calibration %x\n", dsp_version);</div><div class='add'>+		} else {</div><div class='add'>+			dev_dbg(&amp;client-&gt;dev,</div><div class='add'>+				"Detected Unknown EEPROM calibration %lx\n",</div><div class='add'>+				MLX90635_DSP_VERSION(dsp_version));</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, -EPROTONOSUPPORT,</div><div class='add'>+			"Wrong fixed top bit %x (expected 0x8X0X)\n",</div><div class='add'>+			dsp_version);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mlx90635-&gt;emissivity = 1000;</div><div class='add'>+	mlx90635-&gt;interaction_ts = jiffies; /* Set initial value */</div><div class='add'>+</div><div class='add'>+	pm_runtime_get_noresume(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_active(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	ret = devm_pm_runtime_enable(&amp;client-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, ret,</div><div class='add'>+				     "failed to enable powermanagement\n");</div><div class='add'>+</div><div class='add'>+	pm_runtime_set_autosuspend_delay(&amp;client-&gt;dev, MLX90635_SLEEP_DELAY_MS);</div><div class='add'>+	pm_runtime_use_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return devm_iio_device_register(&amp;client-&gt;dev, indio_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id mlx90635_id[] = {</div><div class='add'>+	{ "mlx90635" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, mlx90635_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id mlx90635_of_match[] = {</div><div class='add'>+	{ .compatible = "melexis,mlx90635" },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, mlx90635_of_match);</div><div class='add'>+</div><div class='add'>+static int mlx90635_pm_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = iio_priv(dev_get_drvdata(dev));</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_suspend(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_disable(data-&gt;regulator);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(regmap_get_device(data-&gt;regmap),</div><div class='add'>+			"Failed to disable power regulator: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_pm_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = iio_priv(dev_get_drvdata(dev));</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mlx90635_enable_regulator(data);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return mlx90635_wakeup(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx90635_pm_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mlx90635_data *data = iio_priv(dev_get_drvdata(dev));</div><div class='add'>+</div><div class='add'>+	return mlx90635_pwr_sleep_step(data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops mlx90635_pm_ops = {</div><div class='add'>+	SYSTEM_SLEEP_PM_OPS(mlx90635_pm_suspend, mlx90635_pm_resume)</div><div class='add'>+	RUNTIME_PM_OPS(mlx90635_pm_runtime_suspend, NULL, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct i2c_driver mlx90635_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name	= "mlx90635",</div><div class='add'>+		.of_match_table = mlx90635_of_match,</div><div class='add'>+		.pm	= pm_ptr(&amp;mlx90635_pm_ops),</div><div class='add'>+	},</div><div class='add'>+	.probe = mlx90635_probe,</div><div class='add'>+	.id_table = mlx90635_id,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(mlx90635_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Crt Mori &lt;cmo@melexis.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Melexis MLX90635 contactless Infra Red temperature sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c<br/>index f9ab671c8eda..07c571c7b699 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/core/umem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/core/umem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/core/umem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/core/umem.c</a></div><div class='hunk'>@@ -96,12 +96,6 @@ unsigned long ib_umem_find_best_pgsz(struct ib_umem *umem,</div><div class='ctx'> 		return page_size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* rdma_for_each_block() has a bug if the page size is smaller than the</div><div class='del'>-	 * page size used to build the umem. For now prevent smaller page sizes</div><div class='del'>-	 * from being returned.</div><div class='del'>-	 */</div><div class='del'>-	pgsz_bitmap &amp;= GENMASK(BITS_PER_LONG - 1, PAGE_SHIFT);</div><div class='del'>-</div><div class='ctx'> 	/* The best result is the smallest page size that results in the minimum</div><div class='ctx'> 	 * number of required pages. Compute the largest page size that could</div><div class='ctx'> 	 * work based on VA address bits that don't change.</div><div class='head'>diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c<br/>index 8a6da87f464b..94a7f3b0c71c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/core/verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/core/verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/core/verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/core/verbs.c</a></div><div class='hunk'>@@ -1971,7 +1971,7 @@ int ib_get_eth_speed(struct ib_device *dev, u32 port_num, u16 *speed, u8 *width)</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	u32 netdev_speed;</div><div class='ctx'> 	struct net_device *netdev;</div><div class='del'>-	struct ethtool_link_ksettings lksettings;</div><div class='add'>+	struct ethtool_link_ksettings lksettings = {};</div><div class='ctx'> </div><div class='ctx'> 	if (rdma_port_get_link_layer(dev, port_num) != IB_LINK_LAYER_ETHERNET)</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/bnxt_re.h b/drivers/infiniband/hw/bnxt_re/bnxt_re.h<br/>index 9fd9849ebdd1..9dca451ed522 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/bnxt_re.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/bnxt_re.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/bnxt_re.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/bnxt_re.h</a></div><div class='hunk'>@@ -41,6 +41,7 @@</div><div class='ctx'> #define __BNXT_RE_H__</div><div class='ctx'> #include &lt;rdma/uverbs_ioctl.h&gt;</div><div class='ctx'> #include "hw_counters.h"</div><div class='add'>+#include &lt;linux/hashtable.h&gt;</div><div class='ctx'> #define ROCE_DRV_MODULE_NAME		"bnxt_re"</div><div class='ctx'> </div><div class='ctx'> #define BNXT_RE_DESC	"Broadcom NetXtreme-C/E RoCE Driver"</div><div class='hunk'>@@ -135,6 +136,7 @@ struct bnxt_re_pacing {</div><div class='ctx'> #define BNXT_RE_DB_FIFO_ROOM_SHIFT 15</div><div class='ctx'> #define BNXT_RE_GRC_FIFO_REG_BASE 0x2000</div><div class='ctx'> </div><div class='add'>+#define MAX_CQ_HASH_BITS		(16)</div><div class='ctx'> struct bnxt_re_dev {</div><div class='ctx'> 	struct ib_device		ibdev;</div><div class='ctx'> 	struct list_head		list;</div><div class='hunk'>@@ -189,6 +191,7 @@ struct bnxt_re_dev {</div><div class='ctx'> 	struct bnxt_re_pacing pacing;</div><div class='ctx'> 	struct work_struct dbq_fifo_check_work;</div><div class='ctx'> 	struct delayed_work dbq_pacing_work;</div><div class='add'>+	DECLARE_HASHTABLE(cq_hash, MAX_CQ_HASH_BITS);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define to_bnxt_re_dev(ptr, member)	\</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/hw_counters.c b/drivers/infiniband/hw/bnxt_re/hw_counters.c<br/>index 93572405d6fa..128651c01595 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/hw_counters.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/hw_counters.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/hw_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/hw_counters.c</a></div><div class='hunk'>@@ -371,7 +371,7 @@ int bnxt_re_ib_get_hw_stats(struct ib_device *ibdev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> done:</div><div class='del'>-	return bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx) ?</div><div class='add'>+	return bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx) ?</div><div class='ctx'> 		BNXT_RE_NUM_EXT_COUNTERS : BNXT_RE_NUM_STD_COUNTERS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -381,7 +381,7 @@ struct rdma_hw_stats *bnxt_re_ib_alloc_hw_port_stats(struct ib_device *ibdev,</div><div class='ctx'> 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);</div><div class='ctx'> 	int num_counters = 0;</div><div class='ctx'> </div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx))</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx))</div><div class='ctx'> 		num_counters = BNXT_RE_NUM_EXT_COUNTERS;</div><div class='ctx'> 	else</div><div class='ctx'> 		num_counters = BNXT_RE_NUM_STD_COUNTERS;</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c<br/>index faa88d12ee86..824349659d69 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/ib_verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/ib_verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/ib_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/ib_verbs.c</a></div><div class='hunk'>@@ -50,6 +50,7 @@</div><div class='ctx'> #include &lt;rdma/ib_mad.h&gt;</div><div class='ctx'> #include &lt;rdma/ib_cache.h&gt;</div><div class='ctx'> #include &lt;rdma/uverbs_ioctl.h&gt;</div><div class='add'>+#include &lt;linux/hashtable.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "bnxt_ulp.h"</div><div class='ctx'> </div><div class='hunk'>@@ -567,6 +568,7 @@ bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,</div><div class='ctx'> 	case BNXT_RE_MMAP_WC_DB:</div><div class='ctx'> 	case BNXT_RE_MMAP_DBR_BAR:</div><div class='ctx'> 	case BNXT_RE_MMAP_DBR_PAGE:</div><div class='add'>+	case BNXT_RE_MMAP_TOGGLE_PAGE:</div><div class='ctx'> 		ret = rdma_user_mmap_entry_insert(&amp;uctx-&gt;ib_uctx,</div><div class='ctx'> 						  &amp;entry-&gt;rdma_entry, PAGE_SIZE);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1023,7 +1025,7 @@ static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,</div><div class='ctx'> 	bytes = (qplib_qp-&gt;sq.max_wqe * qplib_qp-&gt;sq.wqe_size);</div><div class='ctx'> 	/* Consider mapping PSN search memory only for RC QPs. */</div><div class='ctx'> 	if (qplib_qp-&gt;type == CMDQ_CREATE_QP_TYPE_RC) {</div><div class='del'>-		psn_sz = bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx) ?</div><div class='add'>+		psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx) ?</div><div class='ctx'> 						   sizeof(struct sq_psn_search_ext) :</div><div class='ctx'> 						   sizeof(struct sq_psn_search);</div><div class='ctx'> 		psn_nume = (qplib_qp-&gt;wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?</div><div class='hunk'>@@ -1184,7 +1186,8 @@ fail:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,</div><div class='del'>-				struct ib_qp_init_attr *init_attr)</div><div class='add'>+				struct ib_qp_init_attr *init_attr,</div><div class='add'>+				struct bnxt_re_ucontext *uctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr;</div><div class='ctx'> 	struct bnxt_qplib_qp *qplqp;</div><div class='hunk'>@@ -1213,7 +1216,7 @@ static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,</div><div class='ctx'> 		/* Allocate 1 more than what's provided so posting max doesn't</div><div class='ctx'> 		 * mean empty.</div><div class='ctx'> 		 */</div><div class='del'>-		entries = roundup_pow_of_two(init_attr-&gt;cap.max_recv_wr + 1);</div><div class='add'>+		entries = bnxt_re_init_depth(init_attr-&gt;cap.max_recv_wr + 1, uctx);</div><div class='ctx'> 		rq-&gt;max_wqe = min_t(u32, entries, dev_attr-&gt;max_qp_wqes + 1);</div><div class='ctx'> 		rq-&gt;q_full_delta = 0;</div><div class='ctx'> 		rq-&gt;sg_info.pgsize = PAGE_SIZE;</div><div class='hunk'>@@ -1233,7 +1236,7 @@ static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)</div><div class='ctx'> 	qplqp = &amp;qp-&gt;qplib_qp;</div><div class='ctx'> 	dev_attr = &amp;rdev-&gt;dev_attr;</div><div class='ctx'> </div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx)) {</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx)) {</div><div class='ctx'> 		qplqp-&gt;rq.max_sge = dev_attr-&gt;max_qp_sges;</div><div class='ctx'> 		if (qplqp-&gt;rq.max_sge &gt; dev_attr-&gt;max_qp_sges)</div><div class='ctx'> 			qplqp-&gt;rq.max_sge = dev_attr-&gt;max_qp_sges;</div><div class='hunk'>@@ -1243,7 +1246,7 @@ static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)</div><div class='ctx'> </div><div class='ctx'> static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,</div><div class='ctx'> 				struct ib_qp_init_attr *init_attr,</div><div class='del'>-				struct ib_udata *udata)</div><div class='add'>+				struct bnxt_re_ucontext *uctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr;</div><div class='ctx'> 	struct bnxt_qplib_qp *qplqp;</div><div class='hunk'>@@ -1272,7 +1275,7 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,</div><div class='ctx'> 	/* Allocate 128 + 1 more than what's provided */</div><div class='ctx'> 	diff = (qplqp-&gt;wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?</div><div class='ctx'> 		0 : BNXT_QPLIB_RESERVED_QP_WRS;</div><div class='del'>-	entries = roundup_pow_of_two(entries + diff + 1);</div><div class='add'>+	entries = bnxt_re_init_depth(entries + diff + 1, uctx);</div><div class='ctx'> 	sq-&gt;max_wqe = min_t(u32, entries, dev_attr-&gt;max_qp_wqes + diff + 1);</div><div class='ctx'> 	sq-&gt;q_full_delta = diff + 1;</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1288,7 +1291,8 @@ static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,</div><div class='del'>-				       struct ib_qp_init_attr *init_attr)</div><div class='add'>+				       struct ib_qp_init_attr *init_attr,</div><div class='add'>+				       struct bnxt_re_ucontext *uctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr;</div><div class='ctx'> 	struct bnxt_qplib_qp *qplqp;</div><div class='hunk'>@@ -1299,8 +1303,8 @@ static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,</div><div class='ctx'> 	qplqp = &amp;qp-&gt;qplib_qp;</div><div class='ctx'> 	dev_attr = &amp;rdev-&gt;dev_attr;</div><div class='ctx'> </div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx)) {</div><div class='del'>-		entries = roundup_pow_of_two(init_attr-&gt;cap.max_send_wr + 1);</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx)) {</div><div class='add'>+		entries = bnxt_re_init_depth(init_attr-&gt;cap.max_send_wr + 1, uctx);</div><div class='ctx'> 		qplqp-&gt;sq.max_wqe = min_t(u32, entries,</div><div class='ctx'> 					  dev_attr-&gt;max_qp_wqes + 1);</div><div class='ctx'> 		qplqp-&gt;sq.q_full_delta = qplqp-&gt;sq.max_wqe -</div><div class='hunk'>@@ -1326,7 +1330,7 @@ static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &amp;&amp;</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &amp;&amp;</div><div class='ctx'> 	    init_attr-&gt;qp_type == IB_QPT_GSI)</div><div class='ctx'> 		qptype = CMDQ_CREATE_QP_TYPE_GSI;</div><div class='ctx'> out:</div><div class='hunk'>@@ -1338,6 +1342,7 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,</div><div class='ctx'> 				struct ib_udata *udata)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr;</div><div class='add'>+	struct bnxt_re_ucontext *uctx;</div><div class='ctx'> 	struct bnxt_qplib_qp *qplqp;</div><div class='ctx'> 	struct bnxt_re_dev *rdev;</div><div class='ctx'> 	struct bnxt_re_cq *cq;</div><div class='hunk'>@@ -1347,6 +1352,7 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,</div><div class='ctx'> 	qplqp = &amp;qp-&gt;qplib_qp;</div><div class='ctx'> 	dev_attr = &amp;rdev-&gt;dev_attr;</div><div class='ctx'> </div><div class='add'>+	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='ctx'> 	/* Setup misc params */</div><div class='ctx'> 	ether_addr_copy(qplqp-&gt;smac, rdev-&gt;netdev-&gt;dev_addr);</div><div class='ctx'> 	qplqp-&gt;pd = &amp;pd-&gt;qplib_pd;</div><div class='hunk'>@@ -1388,18 +1394,18 @@ static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Setup RQ/SRQ */</div><div class='del'>-	rc = bnxt_re_init_rq_attr(qp, init_attr);</div><div class='add'>+	rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	if (init_attr-&gt;qp_type == IB_QPT_GSI)</div><div class='ctx'> 		bnxt_re_adjust_gsi_rq_attr(qp);</div><div class='ctx'> </div><div class='ctx'> 	/* Setup SQ */</div><div class='del'>-	rc = bnxt_re_init_sq_attr(qp, init_attr, udata);</div><div class='add'>+	rc = bnxt_re_init_sq_attr(qp, init_attr, uctx);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	if (init_attr-&gt;qp_type == IB_QPT_GSI)</div><div class='del'>-		bnxt_re_adjust_gsi_sq_attr(qp, init_attr);</div><div class='add'>+		bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);</div><div class='ctx'> </div><div class='ctx'> 	if (udata) /* This will update DPI and qp_handle */</div><div class='ctx'> 		rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);</div><div class='hunk'>@@ -1523,7 +1529,7 @@ int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> </div><div class='ctx'> 	if (qp_init_attr-&gt;qp_type == IB_QPT_GSI &amp;&amp;</div><div class='del'>-	    !(bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx))) {</div><div class='add'>+	    !(bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx))) {</div><div class='ctx'> 		rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);</div><div class='ctx'> 		if (rc == -ENODEV)</div><div class='ctx'> 			goto qp_destroy;</div><div class='hunk'>@@ -1715,6 +1721,7 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq,</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr;</div><div class='ctx'> 	struct bnxt_qplib_nq *nq = NULL;</div><div class='add'>+	struct bnxt_re_ucontext *uctx;</div><div class='ctx'> 	struct bnxt_re_dev *rdev;</div><div class='ctx'> 	struct bnxt_re_srq *srq;</div><div class='ctx'> 	struct bnxt_re_pd *pd;</div><div class='hunk'>@@ -1739,13 +1746,14 @@ int bnxt_re_create_srq(struct ib_srq *ib_srq,</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='ctx'> 	srq-&gt;rdev = rdev;</div><div class='ctx'> 	srq-&gt;qplib_srq.pd = &amp;pd-&gt;qplib_pd;</div><div class='ctx'> 	srq-&gt;qplib_srq.dpi = &amp;rdev-&gt;dpi_privileged;</div><div class='ctx'> 	/* Allocate 1 more than what's provided so posting max doesn't</div><div class='ctx'> 	 * mean empty</div><div class='ctx'> 	 */</div><div class='del'>-	entries = roundup_pow_of_two(srq_init_attr-&gt;attr.max_wr + 1);</div><div class='add'>+	entries = bnxt_re_init_depth(srq_init_attr-&gt;attr.max_wr + 1, uctx);</div><div class='ctx'> 	if (entries &gt; dev_attr-&gt;max_srq_wqes + 1)</div><div class='ctx'> 		entries = dev_attr-&gt;max_srq_wqes + 1;</div><div class='ctx'> 	srq-&gt;qplib_srq.max_wqe = entries;</div><div class='hunk'>@@ -2103,6 +2111,9 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,</div><div class='ctx'> 		qp-&gt;qplib_qp.max_dest_rd_atomic = qp_attr-&gt;max_dest_rd_atomic;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (qp_attr_mask &amp; IB_QP_CAP) {</div><div class='add'>+		struct bnxt_re_ucontext *uctx =</div><div class='add'>+			rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='add'>+</div><div class='ctx'> 		qp-&gt;qplib_qp.modify_flags |=</div><div class='ctx'> 				CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |</div><div class='ctx'> 				CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |</div><div class='hunk'>@@ -2119,7 +2130,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,</div><div class='ctx'> 				  "Create QP failed - max exceeded");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='del'>-		entries = roundup_pow_of_two(qp_attr-&gt;cap.max_send_wr);</div><div class='add'>+		entries = bnxt_re_init_depth(qp_attr-&gt;cap.max_send_wr, uctx);</div><div class='ctx'> 		qp-&gt;qplib_qp.sq.max_wqe = min_t(u32, entries,</div><div class='ctx'> 						dev_attr-&gt;max_qp_wqes + 1);</div><div class='ctx'> 		qp-&gt;qplib_qp.sq.q_full_delta = qp-&gt;qplib_qp.sq.max_wqe -</div><div class='hunk'>@@ -2132,7 +2143,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,</div><div class='ctx'> 		qp-&gt;qplib_qp.sq.q_full_delta -= 1;</div><div class='ctx'> 		qp-&gt;qplib_qp.sq.max_sge = qp_attr-&gt;cap.max_send_sge;</div><div class='ctx'> 		if (qp-&gt;qplib_qp.rq.max_wqe) {</div><div class='del'>-			entries = roundup_pow_of_two(qp_attr-&gt;cap.max_recv_wr);</div><div class='add'>+			entries = bnxt_re_init_depth(qp_attr-&gt;cap.max_recv_wr, uctx);</div><div class='ctx'> 			qp-&gt;qplib_qp.rq.max_wqe =</div><div class='ctx'> 				min_t(u32, entries, dev_attr-&gt;max_qp_wqes + 1);</div><div class='ctx'> 			qp-&gt;qplib_qp.rq.q_full_delta = qp-&gt;qplib_qp.rq.max_wqe -</div><div class='hunk'>@@ -2900,14 +2911,20 @@ int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,</div><div class='ctx'> /* Completion Queues */</div><div class='ctx'> int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_re_cq *cq;</div><div class='add'>+	struct bnxt_qplib_chip_ctx *cctx;</div><div class='ctx'> 	struct bnxt_qplib_nq *nq;</div><div class='ctx'> 	struct bnxt_re_dev *rdev;</div><div class='add'>+	struct bnxt_re_cq *cq;</div><div class='ctx'> </div><div class='ctx'> 	cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);</div><div class='ctx'> 	rdev = cq-&gt;rdev;</div><div class='ctx'> 	nq = cq-&gt;qplib_cq.nq;</div><div class='add'>+	cctx = rdev-&gt;chip_ctx;</div><div class='ctx'> </div><div class='add'>+	if (cctx-&gt;modes.toggle_bits &amp; BNXT_QPLIB_CQ_TOGGLE_BIT) {</div><div class='add'>+		free_page((unsigned long)cq-&gt;uctx_cq_page);</div><div class='add'>+		hash_del(&amp;cq-&gt;hash_entry);</div><div class='add'>+	}</div><div class='ctx'> 	bnxt_qplib_destroy_cq(&amp;rdev-&gt;qplib_res, &amp;cq-&gt;qplib_cq);</div><div class='ctx'> 	ib_umem_release(cq-&gt;umem);</div><div class='ctx'> </div><div class='hunk'>@@ -2920,13 +2937,16 @@ int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)</div><div class='ctx'> int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 		      struct ib_udata *udata)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);</div><div class='ctx'> 	struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq-&gt;device, ibdev);</div><div class='add'>+	struct bnxt_re_ucontext *uctx =</div><div class='add'>+		rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr = &amp;rdev-&gt;dev_attr;</div><div class='del'>-	struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);</div><div class='del'>-	int rc, entries;</div><div class='del'>-	int cqe = attr-&gt;cqe;</div><div class='add'>+	struct bnxt_qplib_chip_ctx *cctx;</div><div class='ctx'> 	struct bnxt_qplib_nq *nq = NULL;</div><div class='ctx'> 	unsigned int nq_alloc_cnt;</div><div class='add'>+	int cqe = attr-&gt;cqe;</div><div class='add'>+	int rc, entries;</div><div class='ctx'> 	u32 active_cqs;</div><div class='ctx'> </div><div class='ctx'> 	if (attr-&gt;flags)</div><div class='hunk'>@@ -2939,9 +2959,10 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cq-&gt;rdev = rdev;</div><div class='add'>+	cctx = rdev-&gt;chip_ctx;</div><div class='ctx'> 	cq-&gt;qplib_cq.cq_handle = (u64)(unsigned long)(&amp;cq-&gt;qplib_cq);</div><div class='ctx'> </div><div class='del'>-	entries = roundup_pow_of_two(cqe + 1);</div><div class='add'>+	entries = bnxt_re_init_depth(cqe + 1, uctx);</div><div class='ctx'> 	if (entries &gt; dev_attr-&gt;max_cq_wqes + 1)</div><div class='ctx'> 		entries = dev_attr-&gt;max_cq_wqes + 1;</div><div class='ctx'> </div><div class='hunk'>@@ -2949,8 +2970,6 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	cq-&gt;qplib_cq.sg_info.pgshft = PAGE_SHIFT;</div><div class='ctx'> 	if (udata) {</div><div class='ctx'> 		struct bnxt_re_cq_req req;</div><div class='del'>-		struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(</div><div class='del'>-			udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='ctx'> 		if (ib_copy_from_udata(&amp;req, udata, sizeof(req))) {</div><div class='ctx'> 			rc = -EFAULT;</div><div class='ctx'> 			goto fail;</div><div class='hunk'>@@ -3002,22 +3021,34 @@ int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	spin_lock_init(&amp;cq-&gt;cq_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (udata) {</div><div class='del'>-		struct bnxt_re_cq_resp resp;</div><div class='add'>+		struct bnxt_re_cq_resp resp = {};</div><div class='ctx'> </div><div class='add'>+		if (cctx-&gt;modes.toggle_bits &amp; BNXT_QPLIB_CQ_TOGGLE_BIT) {</div><div class='add'>+			hash_add(rdev-&gt;cq_hash, &amp;cq-&gt;hash_entry, cq-&gt;qplib_cq.id);</div><div class='add'>+			/* Allocate a page */</div><div class='add'>+			cq-&gt;uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);</div><div class='add'>+			if (!cq-&gt;uctx_cq_page) {</div><div class='add'>+				rc = -ENOMEM;</div><div class='add'>+				goto c2fail;</div><div class='add'>+			}</div><div class='add'>+			resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;</div><div class='add'>+		}</div><div class='ctx'> 		resp.cqid = cq-&gt;qplib_cq.id;</div><div class='ctx'> 		resp.tail = cq-&gt;qplib_cq.hwq.cons;</div><div class='ctx'> 		resp.phase = cq-&gt;qplib_cq.period;</div><div class='ctx'> 		resp.rsvd = 0;</div><div class='del'>-		rc = ib_copy_to_udata(udata, &amp;resp, sizeof(resp));</div><div class='add'>+		rc = ib_copy_to_udata(udata, &amp;resp, min(sizeof(resp), udata-&gt;outlen));</div><div class='ctx'> 		if (rc) {</div><div class='ctx'> 			ibdev_err(&amp;rdev-&gt;ibdev, "Failed to copy CQ udata");</div><div class='ctx'> 			bnxt_qplib_destroy_cq(&amp;rdev-&gt;qplib_res, &amp;cq-&gt;qplib_cq);</div><div class='del'>-			goto c2fail;</div><div class='add'>+			goto free_mem;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+free_mem:</div><div class='add'>+	free_page((unsigned long)cq-&gt;uctx_cq_page);</div><div class='ctx'> c2fail:</div><div class='ctx'> 	ib_umem_release(cq-&gt;umem);</div><div class='ctx'> fail:</div><div class='hunk'>@@ -3072,12 +3103,11 @@ int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	entries = roundup_pow_of_two(cqe + 1);</div><div class='add'>+	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);</div><div class='add'>+	entries = bnxt_re_init_depth(cqe + 1, uctx);</div><div class='ctx'> 	if (entries &gt; dev_attr-&gt;max_cq_wqes + 1)</div><div class='ctx'> 		entries = dev_attr-&gt;max_cq_wqes + 1;</div><div class='ctx'> </div><div class='del'>-	uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,</div><div class='del'>-					 ib_uctx);</div><div class='ctx'> 	/* uverbs consumer */</div><div class='ctx'> 	if (ib_copy_from_udata(&amp;req, udata, sizeof(req))) {</div><div class='ctx'> 		rc = -EFAULT;</div><div class='hunk'>@@ -4108,6 +4138,7 @@ int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)</div><div class='ctx'> 	struct bnxt_qplib_dev_attr *dev_attr = &amp;rdev-&gt;dev_attr;</div><div class='ctx'> 	struct bnxt_re_user_mmap_entry *entry;</div><div class='ctx'> 	struct bnxt_re_uctx_resp resp = {};</div><div class='add'>+	struct bnxt_re_uctx_req ureq = {};</div><div class='ctx'> 	u32 chip_met_rev_num = 0;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='hunk'>@@ -4157,6 +4188,16 @@ int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)</div><div class='ctx'> 	if (rdev-&gt;pacing.dbr_pacing)</div><div class='ctx'> 		resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;</div><div class='ctx'> </div><div class='add'>+	if (udata-&gt;inlen &gt;= sizeof(ureq)) {</div><div class='add'>+		rc = ib_copy_from_udata(&amp;ureq, udata, min(udata-&gt;inlen, sizeof(ureq)));</div><div class='add'>+		if (rc)</div><div class='add'>+			goto cfail;</div><div class='add'>+		if (ureq.comp_mask &amp; BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {</div><div class='add'>+			resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;</div><div class='add'>+			uctx-&gt;cmask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rc = ib_copy_to_udata(udata, &amp;resp, min(udata-&gt;outlen, sizeof(resp)));</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		ibdev_err(ibdev, "Failed to copy user context");</div><div class='hunk'>@@ -4194,6 +4235,19 @@ void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_re_cq *cq = NULL, *tmp_cq;</div><div class='add'>+</div><div class='add'>+	hash_for_each_possible(rdev-&gt;cq_hash, tmp_cq, hash_entry, cq_id) {</div><div class='add'>+		if (tmp_cq-&gt;qplib_cq.id == cq_id) {</div><div class='add'>+			cq = tmp_cq;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return cq;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Helper function to mmap the virtual memory from user app */</div><div class='ctx'> int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)</div><div class='ctx'> {</div><div class='hunk'>@@ -4235,6 +4289,7 @@ int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)</div><div class='ctx'> 					rdma_entry);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case BNXT_RE_MMAP_DBR_PAGE:</div><div class='add'>+	case BNXT_RE_MMAP_TOGGLE_PAGE:</div><div class='ctx'> 		/* Driver doesn't expect write access for user space */</div><div class='ctx'> 		if (vma-&gt;vm_flags &amp; VM_WRITE)</div><div class='ctx'> 			return -EFAULT;</div><div class='hunk'>@@ -4411,8 +4466,126 @@ DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);</div><div class='ctx'> DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,</div><div class='ctx'> 			      &amp;UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));</div><div class='ctx'> </div><div class='add'>+/* Toggle MEM */</div><div class='add'>+static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)</div><div class='add'>+{</div><div class='add'>+	struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);</div><div class='add'>+	enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;</div><div class='add'>+	enum bnxt_re_get_toggle_mem_type res_type;</div><div class='add'>+	struct bnxt_re_user_mmap_entry *entry;</div><div class='add'>+	struct bnxt_re_ucontext *uctx;</div><div class='add'>+	struct ib_ucontext *ib_uctx;</div><div class='add'>+	struct bnxt_re_dev *rdev;</div><div class='add'>+	struct bnxt_re_cq *cq;</div><div class='add'>+	u64 mem_offset;</div><div class='add'>+	u64 addr = 0;</div><div class='add'>+	u32 length;</div><div class='add'>+	u32 offset;</div><div class='add'>+	u32 cq_id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	ib_uctx = ib_uverbs_get_ucontext(attrs);</div><div class='add'>+	if (IS_ERR(ib_uctx))</div><div class='add'>+		return PTR_ERR(ib_uctx);</div><div class='add'>+</div><div class='add'>+	err = uverbs_get_const(&amp;res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);</div><div class='add'>+	rdev = uctx-&gt;rdev;</div><div class='add'>+</div><div class='add'>+	switch (res_type) {</div><div class='add'>+	case BNXT_RE_CQ_TOGGLE_MEM:</div><div class='add'>+		err = uverbs_copy_from(&amp;cq_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		cq = bnxt_re_search_for_cq(rdev, cq_id);</div><div class='add'>+		if (!cq)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		length = PAGE_SIZE;</div><div class='add'>+		addr = (u64)cq-&gt;uctx_cq_page;</div><div class='add'>+		mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;</div><div class='add'>+		offset = 0;</div><div class='add'>+		break;</div><div class='add'>+	case BNXT_RE_SRQ_TOGGLE_MEM:</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &amp;mem_offset);</div><div class='add'>+	if (!entry)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	uobj-&gt;object = entry;</div><div class='add'>+	uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);</div><div class='add'>+	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,</div><div class='add'>+			     &amp;mem_offset, sizeof(mem_offset));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,</div><div class='add'>+			     &amp;length, sizeof(length));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,</div><div class='add'>+			     &amp;offset, sizeof(length));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,</div><div class='add'>+				      enum rdma_remove_reason why,</div><div class='add'>+				      struct uverbs_attr_bundle *attrs)</div><div class='add'>+{</div><div class='add'>+	struct  bnxt_re_user_mmap_entry *entry = uobject-&gt;object;</div><div class='add'>+</div><div class='add'>+	rdma_user_mmap_entry_remove(&amp;entry-&gt;rdma_entry);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,</div><div class='add'>+			    UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,</div><div class='add'>+					    BNXT_RE_OBJECT_GET_TOGGLE_MEM,</div><div class='add'>+					    UVERBS_ACCESS_NEW,</div><div class='add'>+					    UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,</div><div class='add'>+						 enum bnxt_re_get_toggle_mem_type,</div><div class='add'>+						 UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,</div><div class='add'>+					       UVERBS_ATTR_TYPE(u32),</div><div class='add'>+					       UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,</div><div class='add'>+						UVERBS_ATTR_TYPE(u64),</div><div class='add'>+						UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,</div><div class='add'>+						UVERBS_ATTR_TYPE(u32),</div><div class='add'>+						UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,</div><div class='add'>+						UVERBS_ATTR_TYPE(u32),</div><div class='add'>+						UA_MANDATORY));</div><div class='add'>+</div><div class='add'>+DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,</div><div class='add'>+				    UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,</div><div class='add'>+						    BNXT_RE_OBJECT_GET_TOGGLE_MEM,</div><div class='add'>+						    UVERBS_ACCESS_DESTROY,</div><div class='add'>+						    UA_MANDATORY));</div><div class='add'>+</div><div class='add'>+DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,</div><div class='add'>+			    UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),</div><div class='add'>+			    &amp;UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),</div><div class='add'>+			    &amp;UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));</div><div class='add'>+</div><div class='ctx'> const struct uapi_definition bnxt_re_uapi_defs[] = {</div><div class='ctx'> 	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),</div><div class='ctx'> 	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),</div><div class='add'>+	UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.h b/drivers/infiniband/hw/bnxt_re/ib_verbs.h<br/>index 84715b7e7a4e..b267d6d5975f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/ib_verbs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/ib_verbs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/ib_verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/ib_verbs.h</a></div><div class='hunk'>@@ -108,6 +108,8 @@ struct bnxt_re_cq {</div><div class='ctx'> 	struct ib_umem		*umem;</div><div class='ctx'> 	struct ib_umem		*resize_umem;</div><div class='ctx'> 	int			resize_cqe;</div><div class='add'>+	void			*uctx_cq_page;</div><div class='add'>+	struct hlist_node	hash_entry;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bnxt_re_mr {</div><div class='hunk'>@@ -140,6 +142,7 @@ struct bnxt_re_ucontext {</div><div class='ctx'> 	void			*shpg;</div><div class='ctx'> 	spinlock_t		sh_lock;	/* protect shpg */</div><div class='ctx'> 	struct rdma_user_mmap_entry *shpage_mmap;</div><div class='add'>+	u64 cmask;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum bnxt_re_mmap_flag {</div><div class='hunk'>@@ -148,6 +151,7 @@ enum bnxt_re_mmap_flag {</div><div class='ctx'> 	BNXT_RE_MMAP_WC_DB,</div><div class='ctx'> 	BNXT_RE_MMAP_DBR_PAGE,</div><div class='ctx'> 	BNXT_RE_MMAP_DBR_BAR,</div><div class='add'>+	BNXT_RE_MMAP_TOGGLE_PAGE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bnxt_re_user_mmap_entry {</div><div class='hunk'>@@ -167,6 +171,12 @@ static inline u16 bnxt_re_get_rwqe_size(int nsge)</div><div class='ctx'> 	return sizeof(struct rq_wqe_hdr) + (nsge * sizeof(struct sq_sge));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline u32 bnxt_re_init_depth(u32 ent, struct bnxt_re_ucontext *uctx)</div><div class='add'>+{</div><div class='add'>+	return uctx ? (uctx-&gt;cmask &amp; BNXT_RE_UCNTX_CMASK_POW2_DISABLED) ?</div><div class='add'>+		ent : roundup_pow_of_two(ent) : ent;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int bnxt_re_query_device(struct ib_device *ibdev,</div><div class='ctx'> 			 struct ib_device_attr *ib_attr,</div><div class='ctx'> 			 struct ib_udata *udata);</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/main.c b/drivers/infiniband/hw/bnxt_re/main.c<br/>index f79369c8360a..f022c922fae5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/main.c</a></div><div class='hunk'>@@ -54,6 +54,7 @@</div><div class='ctx'> #include &lt;rdma/ib_user_verbs.h&gt;</div><div class='ctx'> #include &lt;rdma/ib_umem.h&gt;</div><div class='ctx'> #include &lt;rdma/ib_addr.h&gt;</div><div class='add'>+#include &lt;linux/hashtable.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "bnxt_ulp.h"</div><div class='ctx'> #include "roce_hsi.h"</div><div class='hunk'>@@ -71,7 +72,7 @@ static char version[] =</div><div class='ctx'> 		BNXT_RE_DESC "\n";</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Eddie Wai &lt;eddie.wai@broadcom.com&gt;");</div><div class='del'>-MODULE_DESCRIPTION(BNXT_RE_DESC " Driver");</div><div class='add'>+MODULE_DESCRIPTION(BNXT_RE_DESC);</div><div class='ctx'> MODULE_LICENSE("Dual BSD/GPL");</div><div class='ctx'> </div><div class='ctx'> /* globals */</div><div class='hunk'>@@ -107,9 +108,14 @@ static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev)</div><div class='ctx'> 		dev_info(rdev_to_dev(rdev),</div><div class='ctx'> 			 "Couldn't get DB bar size, Low latency framework is disabled\n");</div><div class='ctx'> 	/* set register offsets for both UC and WC */</div><div class='del'>-	res-&gt;dpi_tbl.ucreg.offset = res-&gt;is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :</div><div class='del'>-						 BNXT_QPLIB_DBR_PF_DB_OFFSET;</div><div class='del'>-	res-&gt;dpi_tbl.wcreg.offset = res-&gt;dpi_tbl.ucreg.offset;</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p7(cctx)) {</div><div class='add'>+		res-&gt;dpi_tbl.ucreg.offset = offset;</div><div class='add'>+		res-&gt;dpi_tbl.wcreg.offset = en_dev-&gt;l2_db_size;</div><div class='add'>+	} else {</div><div class='add'>+		res-&gt;dpi_tbl.ucreg.offset = res-&gt;is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET :</div><div class='add'>+							 BNXT_QPLIB_DBR_PF_DB_OFFSET;</div><div class='add'>+		res-&gt;dpi_tbl.wcreg.offset = res-&gt;dpi_tbl.ucreg.offset;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* If WC mapping is disabled by L2 driver then en_dev-&gt;l2_db_size</div><div class='ctx'> 	 * is equal to the DB-Bar actual size. This indicates that L2</div><div class='hunk'>@@ -128,11 +134,13 @@ static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode)</div><div class='ctx'> 	struct bnxt_qplib_chip_ctx *cctx;</div><div class='ctx'> </div><div class='ctx'> 	cctx = rdev-&gt;chip_ctx;</div><div class='del'>-	cctx-&gt;modes.wqe_mode = bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx) ?</div><div class='add'>+	cctx-&gt;modes.wqe_mode = bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx) ?</div><div class='ctx'> 			       mode : BNXT_QPLIB_WQE_MODE_STATIC;</div><div class='ctx'> 	if (bnxt_re_hwrm_qcaps(rdev))</div><div class='ctx'> 		dev_err(rdev_to_dev(rdev),</div><div class='ctx'> 			"Failed to query hwrm qcaps\n");</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p7(rdev-&gt;chip_ctx))</div><div class='add'>+		cctx-&gt;modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev)</div><div class='hunk'>@@ -215,7 +223,7 @@ static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev)</div><div class='ctx'> 	ctx-&gt;srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT,</div><div class='ctx'> 				attr-&gt;max_srq);</div><div class='ctx'> 	ctx-&gt;cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr-&gt;max_cq);</div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx))</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx))</div><div class='ctx'> 		for (i = 0; i &lt; MAX_TQM_ALLOC_REQ; i++)</div><div class='ctx'> 			rdev-&gt;qplib_ctx.tqm_ctx.qcount[i] =</div><div class='ctx'> 			rdev-&gt;dev_attr.tqm_alloc_reqs[i];</div><div class='hunk'>@@ -264,7 +272,7 @@ static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev)</div><div class='ctx'> 	memset(&amp;rdev-&gt;qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res));</div><div class='ctx'> 	bnxt_re_limit_pf_res(rdev);</div><div class='ctx'> </div><div class='del'>-	num_vfs =  bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx) ?</div><div class='add'>+	num_vfs =  bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx) ?</div><div class='ctx'> 			BNXT_RE_GEN_P5_MAX_VF : rdev-&gt;num_vfs;</div><div class='ctx'> 	if (num_vfs)</div><div class='ctx'> 		bnxt_re_limit_vf_res(&amp;rdev-&gt;qplib_ctx, num_vfs);</div><div class='hunk'>@@ -276,7 +284,7 @@ static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev)</div><div class='ctx'> 	if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &amp;rdev-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> 	rdev-&gt;num_vfs = pci_sriov_get_totalvfs(rdev-&gt;en_dev-&gt;pdev);</div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx)) {</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx)) {</div><div class='ctx'> 		bnxt_re_set_resource_limits(rdev);</div><div class='ctx'> 		bnxt_qplib_set_func_resources(&amp;rdev-&gt;qplib_res, &amp;rdev-&gt;rcfw,</div><div class='ctx'> 					      &amp;rdev-&gt;qplib_ctx);</div><div class='hunk'>@@ -1203,25 +1211,19 @@ static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq,</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq,</div><div class='ctx'> 					     qplib_cq);</div><div class='add'>+	u32 *cq_ptr;</div><div class='ctx'> </div><div class='ctx'> 	if (cq-&gt;ib_cq.comp_handler) {</div><div class='del'>-		/* Lock comp_handler? */</div><div class='add'>+		if (cq-&gt;uctx_cq_page) {</div><div class='add'>+			cq_ptr = (u32 *)cq-&gt;uctx_cq_page;</div><div class='add'>+			*cq_ptr = cq-&gt;qplib_cq.toggle;</div><div class='add'>+		}</div><div class='ctx'> 		(*cq-&gt;ib_cq.comp_handler)(&amp;cq-&gt;ib_cq, cq-&gt;ib_cq.cq_context);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define BNXT_RE_GEN_P5_PF_NQ_DB		0x10000</div><div class='del'>-#define BNXT_RE_GEN_P5_VF_NQ_DB		0x4000</div><div class='del'>-static u32 bnxt_re_get_nqdb_offset(struct bnxt_re_dev *rdev, u16 indx)</div><div class='del'>-{</div><div class='del'>-	return bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx) ?</div><div class='del'>-		(rdev-&gt;is_virtfn ? BNXT_RE_GEN_P5_VF_NQ_DB :</div><div class='del'>-				   BNXT_RE_GEN_P5_PF_NQ_DB) :</div><div class='del'>-				   rdev-&gt;en_dev-&gt;msix_entries[indx].db_offset;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1242,7 +1244,7 @@ static int bnxt_re_init_res(struct bnxt_re_dev *rdev)</div><div class='ctx'> 	bnxt_qplib_init_res(&amp;rdev-&gt;qplib_res);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; rdev-&gt;num_msix ; i++) {</div><div class='del'>-		db_offt = bnxt_re_get_nqdb_offset(rdev, i);</div><div class='add'>+		db_offt = rdev-&gt;en_dev-&gt;msix_entries[i].db_offset;</div><div class='ctx'> 		rc = bnxt_qplib_enable_nq(rdev-&gt;en_dev-&gt;pdev, &amp;rdev-&gt;nq[i - 1],</div><div class='ctx'> 					  i - 1, rdev-&gt;en_dev-&gt;msix_entries[i].vector,</div><div class='ctx'> 					  db_offt, &amp;bnxt_re_cqn_handler,</div><div class='hunk'>@@ -1653,7 +1655,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)</div><div class='ctx'> 		ibdev_err(&amp;rdev-&gt;ibdev, "Failed to allocate CREQ: %#x\n", rc);</div><div class='ctx'> 		goto free_rcfw;</div><div class='ctx'> 	}</div><div class='del'>-	db_offt = bnxt_re_get_nqdb_offset(rdev, BNXT_RE_AEQ_IDX);</div><div class='add'>+	db_offt = rdev-&gt;en_dev-&gt;msix_entries[BNXT_RE_AEQ_IDX].db_offset;</div><div class='ctx'> 	vid = rdev-&gt;en_dev-&gt;msix_entries[BNXT_RE_AEQ_IDX].vector;</div><div class='ctx'> 	rc = bnxt_qplib_enable_rcfw_channel(&amp;rdev-&gt;rcfw,</div><div class='ctx'> 					    vid, db_offt,</div><div class='hunk'>@@ -1681,7 +1683,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)</div><div class='ctx'> 	bnxt_re_set_resource_limits(rdev);</div><div class='ctx'> </div><div class='ctx'> 	rc = bnxt_qplib_alloc_ctx(&amp;rdev-&gt;qplib_res, &amp;rdev-&gt;qplib_ctx, 0,</div><div class='del'>-				  bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx));</div><div class='add'>+				  bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx));</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		ibdev_err(&amp;rdev-&gt;ibdev,</div><div class='ctx'> 			  "Failed to allocate QPLIB context: %#x\n", rc);</div><div class='hunk'>@@ -1737,6 +1739,7 @@ static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode)</div><div class='ctx'> 		 */</div><div class='ctx'> 		bnxt_re_vf_res_config(rdev);</div><div class='ctx'> 	}</div><div class='add'>+	hash_init(rdev-&gt;cq_hash);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> free_sctx:</div><div class='hunk'>@@ -1804,7 +1807,7 @@ static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* Currently enabling only for GenP5 adapters */</div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rdev-&gt;chip_ctx))</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rdev-&gt;chip_ctx))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.c b/drivers/infiniband/hw/bnxt_re/qplib_fp.c<br/>index abbabea7f5fa..c98e04fe2ddd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_fp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_fp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_fp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_fp.c</a></div><div class='hunk'>@@ -237,18 +237,15 @@ static void clean_nq(struct bnxt_qplib_nq *nq, struct bnxt_qplib_cq *cq)</div><div class='ctx'> 	struct bnxt_qplib_hwq *hwq = &amp;nq-&gt;hwq;</div><div class='ctx'> 	struct nq_base *nqe, **nq_ptr;</div><div class='ctx'> 	int budget = nq-&gt;budget;</div><div class='del'>-	u32 sw_cons, raw_cons;</div><div class='ctx'> 	uintptr_t q_handle;</div><div class='ctx'> 	u16 type;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;hwq-&gt;lock);</div><div class='ctx'> 	/* Service the NQ until empty */</div><div class='del'>-	raw_cons = hwq-&gt;cons;</div><div class='ctx'> 	while (budget--) {</div><div class='del'>-		sw_cons = HWQ_CMP(raw_cons, hwq);</div><div class='ctx'> 		nq_ptr = (struct nq_base **)hwq-&gt;pbl_ptr;</div><div class='del'>-		nqe = &amp;nq_ptr[NQE_PG(sw_cons)][NQE_IDX(sw_cons)];</div><div class='del'>-		if (!NQE_CMP_VALID(nqe, raw_cons, hwq-&gt;max_elements))</div><div class='add'>+		nqe = &amp;nq_ptr[NQE_PG(hwq-&gt;cons)][NQE_IDX(hwq-&gt;cons)];</div><div class='add'>+		if (!NQE_CMP_VALID(nqe, nq-&gt;nq_db.dbinfo.flags))</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -276,7 +273,8 @@ static void clean_nq(struct bnxt_qplib_nq *nq, struct bnxt_qplib_cq *cq)</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		raw_cons++;</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(hwq-&gt;max_elements, &amp;hwq-&gt;cons,</div><div class='add'>+					 1, &amp;nq-&gt;nq_db.dbinfo.flags);</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_bh(&amp;hwq-&gt;lock);</div><div class='ctx'> }</div><div class='hunk'>@@ -302,18 +300,16 @@ static void bnxt_qplib_service_nq(struct tasklet_struct *t)</div><div class='ctx'> 	struct bnxt_qplib_hwq *hwq = &amp;nq-&gt;hwq;</div><div class='ctx'> 	struct bnxt_qplib_cq *cq;</div><div class='ctx'> 	int budget = nq-&gt;budget;</div><div class='del'>-	u32 sw_cons, raw_cons;</div><div class='ctx'> 	struct nq_base *nqe;</div><div class='ctx'> 	uintptr_t q_handle;</div><div class='add'>+	u32 hw_polled = 0;</div><div class='ctx'> 	u16 type;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;hwq-&gt;lock);</div><div class='ctx'> 	/* Service the NQ until empty */</div><div class='del'>-	raw_cons = hwq-&gt;cons;</div><div class='ctx'> 	while (budget--) {</div><div class='del'>-		sw_cons = HWQ_CMP(raw_cons, hwq);</div><div class='del'>-		nqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);</div><div class='del'>-		if (!NQE_CMP_VALID(nqe, raw_cons, hwq-&gt;max_elements))</div><div class='add'>+		nqe = bnxt_qplib_get_qe(hwq, hwq-&gt;cons, NULL);</div><div class='add'>+		if (!NQE_CMP_VALID(nqe, nq-&gt;nq_db.dbinfo.flags))</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -334,6 +330,9 @@ static void bnxt_qplib_service_nq(struct tasklet_struct *t)</div><div class='ctx'> 			cq = (struct bnxt_qplib_cq *)(unsigned long)q_handle;</div><div class='ctx'> 			if (!cq)</div><div class='ctx'> 				break;</div><div class='add'>+			cq-&gt;toggle = (le16_to_cpu(nqe-&gt;info10_type) &amp;</div><div class='add'>+					NQ_CN_TOGGLE_MASK) &gt;&gt; NQ_CN_TOGGLE_SFT;</div><div class='add'>+			cq-&gt;dbinfo.toggle = cq-&gt;toggle;</div><div class='ctx'> 			bnxt_qplib_armen_db(&amp;cq-&gt;dbinfo,</div><div class='ctx'> 					    DBC_DBC_TYPE_CQ_ARMENA);</div><div class='ctx'> 			spin_lock_bh(&amp;cq-&gt;compl_lock);</div><div class='hunk'>@@ -372,12 +371,12 @@ static void bnxt_qplib_service_nq(struct tasklet_struct *t)</div><div class='ctx'> 				 "nqe with type = 0x%x not handled\n", type);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		raw_cons++;</div><div class='add'>+		hw_polled++;</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(hwq-&gt;max_elements, &amp;hwq-&gt;cons,</div><div class='add'>+					 1, &amp;nq-&gt;nq_db.dbinfo.flags);</div><div class='ctx'> 	}</div><div class='del'>-	if (hwq-&gt;cons != raw_cons) {</div><div class='del'>-		hwq-&gt;cons = raw_cons;</div><div class='add'>+	if (hw_polled)</div><div class='ctx'> 		bnxt_qplib_ring_nq_db(&amp;nq-&gt;nq_db.dbinfo, nq-&gt;res-&gt;cctx, true);</div><div class='del'>-	}</div><div class='ctx'> 	spin_unlock_bh(&amp;hwq-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -505,6 +504,7 @@ static int bnxt_qplib_map_nq_db(struct bnxt_qplib_nq *nq,  u32 reg_offt)</div><div class='ctx'> 	pdev = nq-&gt;pdev;</div><div class='ctx'> 	nq_db = &amp;nq-&gt;nq_db;</div><div class='ctx'> </div><div class='add'>+	nq_db-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	nq_db-&gt;reg.bar_id = NQ_CONS_PCI_BAR_REGION;</div><div class='ctx'> 	nq_db-&gt;reg.bar_base = pci_resource_start(pdev, nq_db-&gt;reg.bar_id);</div><div class='ctx'> 	if (!nq_db-&gt;reg.bar_base) {</div><div class='hunk'>@@ -649,7 +649,7 @@ int bnxt_qplib_create_srq(struct bnxt_qplib_res *res,</div><div class='ctx'> 		rc = -ENOMEM;</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	srq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&amp;req,</div><div class='ctx'> 				 CMDQ_BASE_OPCODE_CREATE_SRQ,</div><div class='ctx'> 				 sizeof(req));</div><div class='hunk'>@@ -703,13 +703,9 @@ int bnxt_qplib_modify_srq(struct bnxt_qplib_res *res,</div><div class='ctx'> 			  struct bnxt_qplib_srq *srq)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_hwq *srq_hwq = &amp;srq-&gt;hwq;</div><div class='del'>-	u32 sw_prod, sw_cons, count = 0;</div><div class='del'>-</div><div class='del'>-	sw_prod = HWQ_CMP(srq_hwq-&gt;prod, srq_hwq);</div><div class='del'>-	sw_cons = HWQ_CMP(srq_hwq-&gt;cons, srq_hwq);</div><div class='add'>+	u32 count;</div><div class='ctx'> </div><div class='del'>-	count = sw_prod &gt; sw_cons ? sw_prod - sw_cons :</div><div class='del'>-				    srq_hwq-&gt;max_elements - sw_cons + sw_prod;</div><div class='add'>+	count = __bnxt_qplib_get_avail(srq_hwq);</div><div class='ctx'> 	if (count &gt; srq-&gt;threshold) {</div><div class='ctx'> 		srq-&gt;arm_req = false;</div><div class='ctx'> 		bnxt_qplib_srq_arm_db(&amp;srq-&gt;dbinfo, srq-&gt;threshold);</div><div class='hunk'>@@ -761,7 +757,7 @@ int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,</div><div class='ctx'> 	struct bnxt_qplib_hwq *srq_hwq = &amp;srq-&gt;hwq;</div><div class='ctx'> 	struct rq_wqe *srqe;</div><div class='ctx'> 	struct sq_sge *hw_sge;</div><div class='del'>-	u32 sw_prod, sw_cons, count = 0;</div><div class='add'>+	u32 count = 0;</div><div class='ctx'> 	int i, next;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;srq_hwq-&gt;lock);</div><div class='hunk'>@@ -775,8 +771,7 @@ int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,</div><div class='ctx'> 	srq-&gt;start_idx = srq-&gt;swq[next].next_idx;</div><div class='ctx'> 	spin_unlock(&amp;srq_hwq-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	sw_prod = HWQ_CMP(srq_hwq-&gt;prod, srq_hwq);</div><div class='del'>-	srqe = bnxt_qplib_get_qe(srq_hwq, sw_prod, NULL);</div><div class='add'>+	srqe = bnxt_qplib_get_qe(srq_hwq, srq_hwq-&gt;prod, NULL);</div><div class='ctx'> 	memset(srqe, 0, srq-&gt;wqe_size);</div><div class='ctx'> 	/* Calculate wqe_size16 and data_len */</div><div class='ctx'> 	for (i = 0, hw_sge = (struct sq_sge *)srqe-&gt;data;</div><div class='hunk'>@@ -792,17 +787,10 @@ int bnxt_qplib_post_srq_recv(struct bnxt_qplib_srq *srq,</div><div class='ctx'> 	srqe-&gt;wr_id[0] = cpu_to_le32((u32)next);</div><div class='ctx'> 	srq-&gt;swq[next].wr_id = wqe-&gt;wr_id;</div><div class='ctx'> </div><div class='del'>-	srq_hwq-&gt;prod++;</div><div class='add'>+	bnxt_qplib_hwq_incr_prod(&amp;srq-&gt;dbinfo, srq_hwq, srq-&gt;dbinfo.max_slot);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;srq_hwq-&gt;lock);</div><div class='del'>-	sw_prod = HWQ_CMP(srq_hwq-&gt;prod, srq_hwq);</div><div class='del'>-	/* retaining srq_hwq-&gt;cons for this logic</div><div class='del'>-	 * actually the lock is only required to</div><div class='del'>-	 * read srq_hwq-&gt;cons.</div><div class='del'>-	 */</div><div class='del'>-	sw_cons = HWQ_CMP(srq_hwq-&gt;cons, srq_hwq);</div><div class='del'>-	count = sw_prod &gt; sw_cons ? sw_prod - sw_cons :</div><div class='del'>-				    srq_hwq-&gt;max_elements - sw_cons + sw_prod;</div><div class='add'>+	count = __bnxt_qplib_get_avail(srq_hwq);</div><div class='ctx'> 	spin_unlock(&amp;srq_hwq-&gt;lock);</div><div class='ctx'> 	/* Ring DB */</div><div class='ctx'> 	bnxt_qplib_ring_prod_db(&amp;srq-&gt;dbinfo, DBC_DBC_TYPE_SRQ);</div><div class='hunk'>@@ -849,6 +837,7 @@ int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> 	u32 tbl_indx;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='add'>+	sq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&amp;req,</div><div class='ctx'> 				 CMDQ_BASE_OPCODE_CREATE_QP1,</div><div class='ctx'> 				 sizeof(req));</div><div class='hunk'>@@ -885,6 +874,7 @@ int bnxt_qplib_create_qp1(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> </div><div class='ctx'> 	/* RQ */</div><div class='ctx'> 	if (rq-&gt;max_wqe) {</div><div class='add'>+		rq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 		hwq_attr.res = res;</div><div class='ctx'> 		hwq_attr.sginfo = &amp;rq-&gt;sg_info;</div><div class='ctx'> 		hwq_attr.stride = sizeof(struct sq_sge);</div><div class='hunk'>@@ -992,6 +982,10 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> 	u32 tbl_indx;</div><div class='ctx'> 	u16 nsge;</div><div class='ctx'> </div><div class='add'>+	if (res-&gt;dattr)</div><div class='add'>+		qp-&gt;dev_cap_flags = res-&gt;dattr-&gt;dev_cap_flags;</div><div class='add'>+</div><div class='add'>+	sq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&amp;req,</div><div class='ctx'> 				 CMDQ_BASE_OPCODE_CREATE_QP,</div><div class='ctx'> 				 sizeof(req));</div><div class='hunk'>@@ -1003,9 +997,14 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> </div><div class='ctx'> 	/* SQ */</div><div class='ctx'> 	if (qp-&gt;type == CMDQ_CREATE_QP_TYPE_RC) {</div><div class='del'>-		psn_sz = bnxt_qplib_is_chip_gen_p5(res-&gt;cctx) ?</div><div class='add'>+		psn_sz = bnxt_qplib_is_chip_gen_p5_p7(res-&gt;cctx) ?</div><div class='ctx'> 			 sizeof(struct sq_psn_search_ext) :</div><div class='ctx'> 			 sizeof(struct sq_psn_search);</div><div class='add'>+</div><div class='add'>+		if (BNXT_RE_HW_RETX(qp-&gt;dev_cap_flags)) {</div><div class='add'>+			psn_sz = sizeof(struct sq_msn_search);</div><div class='add'>+			qp-&gt;msn = 0;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	hwq_attr.res = res;</div><div class='hunk'>@@ -1014,6 +1013,13 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> 	hwq_attr.depth = bnxt_qplib_get_depth(sq);</div><div class='ctx'> 	hwq_attr.aux_stride = psn_sz;</div><div class='ctx'> 	hwq_attr.aux_depth = bnxt_qplib_set_sq_size(sq, qp-&gt;wqe_mode);</div><div class='add'>+	/* Update msn tbl size */</div><div class='add'>+	if (BNXT_RE_HW_RETX(qp-&gt;dev_cap_flags) &amp;&amp; psn_sz) {</div><div class='add'>+		hwq_attr.aux_depth = roundup_pow_of_two(bnxt_qplib_set_sq_size(sq, qp-&gt;wqe_mode));</div><div class='add'>+		qp-&gt;msn_tbl_sz = hwq_attr.aux_depth;</div><div class='add'>+		qp-&gt;msn = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	hwq_attr.type = HWQ_TYPE_QUEUE;</div><div class='ctx'> 	rc = bnxt_qplib_alloc_init_hwq(&amp;sq-&gt;hwq, &amp;hwq_attr);</div><div class='ctx'> 	if (rc)</div><div class='hunk'>@@ -1040,6 +1046,7 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp)</div><div class='ctx'> </div><div class='ctx'> 	/* RQ */</div><div class='ctx'> 	if (!qp-&gt;srq) {</div><div class='add'>+		rq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 		hwq_attr.res = res;</div><div class='ctx'> 		hwq_attr.sginfo = &amp;rq-&gt;sg_info;</div><div class='ctx'> 		hwq_attr.stride = sizeof(struct sq_sge);</div><div class='hunk'>@@ -1454,12 +1461,15 @@ bail:</div><div class='ctx'> static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_hwq *cq_hwq = &amp;cq-&gt;hwq;</div><div class='add'>+	u32 peek_flags, peek_cons;</div><div class='ctx'> 	struct cq_base *hw_cqe;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	peek_flags = cq-&gt;dbinfo.flags;</div><div class='add'>+	peek_cons = cq_hwq-&gt;cons;</div><div class='ctx'> 	for (i = 0; i &lt; cq_hwq-&gt;max_elements; i++) {</div><div class='del'>-		hw_cqe = bnxt_qplib_get_qe(cq_hwq, i, NULL);</div><div class='del'>-		if (!CQE_CMP_VALID(hw_cqe, i, cq_hwq-&gt;max_elements))</div><div class='add'>+		hw_cqe = bnxt_qplib_get_qe(cq_hwq, peek_cons, NULL);</div><div class='add'>+		if (!CQE_CMP_VALID(hw_cqe, peek_flags))</div><div class='ctx'> 			continue;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The valid test of the entry must be done first before</div><div class='hunk'>@@ -1489,6 +1499,8 @@ static void __clean_cq(struct bnxt_qplib_cq *cq, u64 qp)</div><div class='ctx'> 		default:</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(cq_hwq-&gt;max_elements, &amp;peek_cons,</div><div class='add'>+					 1, &amp;peek_flags);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1590,6 +1602,27 @@ void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* Fil the MSN table into the next psn row */</div><div class='add'>+static void bnxt_qplib_fill_msn_search(struct bnxt_qplib_qp *qp,</div><div class='add'>+				       struct bnxt_qplib_swqe *wqe,</div><div class='add'>+				       struct bnxt_qplib_swq *swq)</div><div class='add'>+{</div><div class='add'>+	struct sq_msn_search *msns;</div><div class='add'>+	u32 start_psn, next_psn;</div><div class='add'>+	u16 start_idx;</div><div class='add'>+</div><div class='add'>+	msns = (struct sq_msn_search *)swq-&gt;psn_search;</div><div class='add'>+	msns-&gt;start_idx_next_psn_start_psn = 0;</div><div class='add'>+</div><div class='add'>+	start_psn = swq-&gt;start_psn;</div><div class='add'>+	next_psn = swq-&gt;next_psn;</div><div class='add'>+	start_idx = swq-&gt;slot_idx;</div><div class='add'>+	msns-&gt;start_idx_next_psn_start_psn |=</div><div class='add'>+		bnxt_re_update_msn_tbl(start_idx, next_psn, start_psn);</div><div class='add'>+	qp-&gt;msn++;</div><div class='add'>+	qp-&gt;msn %= qp-&gt;msn_tbl_sz;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void bnxt_qplib_fill_psn_search(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 				       struct bnxt_qplib_swqe *wqe,</div><div class='ctx'> 				       struct bnxt_qplib_swq *swq)</div><div class='hunk'>@@ -1601,6 +1634,12 @@ static void bnxt_qplib_fill_psn_search(struct bnxt_qplib_qp *qp,</div><div class='ctx'> </div><div class='ctx'> 	if (!swq-&gt;psn_search)</div><div class='ctx'> 		return;</div><div class='add'>+	/* Handle MSN differently on cap flags  */</div><div class='add'>+	if (BNXT_RE_HW_RETX(qp-&gt;dev_cap_flags)) {</div><div class='add'>+		bnxt_qplib_fill_msn_search(qp, wqe, swq);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	psns = (struct sq_psn_search *)swq-&gt;psn_search;</div><div class='ctx'> 	psns = swq-&gt;psn_search;</div><div class='ctx'> 	psns_ext = swq-&gt;psn_ext;</div><div class='ctx'> </div><div class='hunk'>@@ -1611,7 +1650,7 @@ static void bnxt_qplib_fill_psn_search(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	flg_npsn = ((swq-&gt;next_psn &lt;&lt; SQ_PSN_SEARCH_NEXT_PSN_SFT) &amp;</div><div class='ctx'> 		     SQ_PSN_SEARCH_NEXT_PSN_MASK);</div><div class='ctx'> </div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(qp-&gt;cctx)) {</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(qp-&gt;cctx)) {</div><div class='ctx'> 		psns_ext-&gt;opcode_start_psn = cpu_to_le32(op_spsn);</div><div class='ctx'> 		psns_ext-&gt;flags_next_psn = cpu_to_le32(flg_npsn);</div><div class='ctx'> 		psns_ext-&gt;start_slot_idx = cpu_to_le16(swq-&gt;slot_idx);</div><div class='hunk'>@@ -1709,8 +1748,8 @@ static u16 bnxt_qplib_required_slots(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	return slot;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bnxt_qplib_pull_psn_buff(struct bnxt_qplib_q *sq,</div><div class='del'>-				     struct bnxt_qplib_swq *swq)</div><div class='add'>+static void bnxt_qplib_pull_psn_buff(struct bnxt_qplib_qp *qp, struct bnxt_qplib_q *sq,</div><div class='add'>+				     struct bnxt_qplib_swq *swq, bool hw_retx)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_qplib_hwq *hwq;</div><div class='ctx'> 	u32 pg_num, pg_indx;</div><div class='hunk'>@@ -1721,6 +1760,11 @@ static void bnxt_qplib_pull_psn_buff(struct bnxt_qplib_q *sq,</div><div class='ctx'> 	if (!hwq-&gt;pad_pg)</div><div class='ctx'> 		return;</div><div class='ctx'> 	tail = swq-&gt;slot_idx / sq-&gt;dbinfo.max_slot;</div><div class='add'>+	if (hw_retx) {</div><div class='add'>+		/* For HW retx use qp msn index */</div><div class='add'>+		tail = qp-&gt;msn;</div><div class='add'>+		tail %= qp-&gt;msn_tbl_sz;</div><div class='add'>+	}</div><div class='ctx'> 	pg_num = (tail + hwq-&gt;pad_pgofft) / (PAGE_SIZE / hwq-&gt;pad_stride);</div><div class='ctx'> 	pg_indx = (tail + hwq-&gt;pad_pgofft) % (PAGE_SIZE / hwq-&gt;pad_stride);</div><div class='ctx'> 	buff = (void *)(hwq-&gt;pad_pg[pg_num] + pg_indx * hwq-&gt;pad_stride);</div><div class='hunk'>@@ -1745,6 +1789,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	struct bnxt_qplib_swq *swq;</div><div class='ctx'> 	bool sch_handler = false;</div><div class='ctx'> 	u16 wqe_sz, qdf = 0;</div><div class='add'>+	bool msn_update;</div><div class='ctx'> 	void *base_hdr;</div><div class='ctx'> 	void *ext_hdr;</div><div class='ctx'> 	__le32 temp32;</div><div class='hunk'>@@ -1772,7 +1817,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	swq = bnxt_qplib_get_swqe(sq, &amp;wqe_idx);</div><div class='del'>-	bnxt_qplib_pull_psn_buff(sq, swq);</div><div class='add'>+	bnxt_qplib_pull_psn_buff(qp, sq, swq, BNXT_RE_HW_RETX(qp-&gt;dev_cap_flags));</div><div class='ctx'> </div><div class='ctx'> 	idx = 0;</div><div class='ctx'> 	swq-&gt;slot_idx = hwq-&gt;prod;</div><div class='hunk'>@@ -1804,6 +1849,8 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 					       &amp;idx);</div><div class='ctx'> 	if (data_len &lt; 0)</div><div class='ctx'> 		goto queue_err;</div><div class='add'>+	/* Make sure we update MSN table only for wired wqes */</div><div class='add'>+	msn_update = true;</div><div class='ctx'> 	/* Specifics */</div><div class='ctx'> 	switch (wqe-&gt;type) {</div><div class='ctx'> 	case BNXT_QPLIB_SWQE_TYPE_SEND:</div><div class='hunk'>@@ -1844,6 +1891,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 						      SQ_SEND_DST_QP_MASK);</div><div class='ctx'> 			ext_sqe-&gt;avid = cpu_to_le32(wqe-&gt;send.avid &amp;</div><div class='ctx'> 						    SQ_SEND_AVID_MASK);</div><div class='add'>+			msn_update = false;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			sqe-&gt;length = cpu_to_le32(data_len);</div><div class='ctx'> 			if (qp-&gt;mtu)</div><div class='hunk'>@@ -1901,7 +1949,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 		sqe-&gt;wqe_type = wqe-&gt;type;</div><div class='ctx'> 		sqe-&gt;flags = wqe-&gt;flags;</div><div class='ctx'> 		sqe-&gt;inv_l_key = cpu_to_le32(wqe-&gt;local_inv.inv_l_key);</div><div class='del'>-</div><div class='add'>+		msn_update = false;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	case BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR:</div><div class='hunk'>@@ -1933,6 +1981,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 						PTU_PTE_VALID);</div><div class='ctx'> 		ext_sqe-&gt;pblptr = cpu_to_le64(wqe-&gt;frmr.pbl_dma_ptr);</div><div class='ctx'> 		ext_sqe-&gt;va = cpu_to_le64(wqe-&gt;frmr.va);</div><div class='add'>+		msn_update = false;</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1950,6 +1999,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 		sqe-&gt;l_key = cpu_to_le32(wqe-&gt;bind.r_key);</div><div class='ctx'> 		ext_sqe-&gt;va = cpu_to_le64(wqe-&gt;bind.va);</div><div class='ctx'> 		ext_sqe-&gt;length_lo = cpu_to_le32(wqe-&gt;bind.length);</div><div class='add'>+		msn_update = false;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1957,11 +2007,13 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 		rc = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='del'>-	swq-&gt;next_psn = sq-&gt;psn &amp; BTH_PSN_MASK;</div><div class='del'>-	bnxt_qplib_fill_psn_search(qp, wqe, swq);</div><div class='add'>+	if (!BNXT_RE_HW_RETX(qp-&gt;dev_cap_flags) || msn_update) {</div><div class='add'>+		swq-&gt;next_psn = sq-&gt;psn &amp; BTH_PSN_MASK;</div><div class='add'>+		bnxt_qplib_fill_psn_search(qp, wqe, swq);</div><div class='add'>+	}</div><div class='ctx'> queue_err:</div><div class='ctx'> 	bnxt_qplib_swq_mod_start(sq, wqe_idx);</div><div class='del'>-	bnxt_qplib_hwq_incr_prod(hwq, swq-&gt;slots);</div><div class='add'>+	bnxt_qplib_hwq_incr_prod(&amp;sq-&gt;dbinfo, hwq, swq-&gt;slots);</div><div class='ctx'> 	qp-&gt;wqe_cnt++;</div><div class='ctx'> done:</div><div class='ctx'> 	if (sch_handler) {</div><div class='hunk'>@@ -2049,7 +2101,7 @@ int bnxt_qplib_post_recv(struct bnxt_qplib_qp *qp,</div><div class='ctx'> 	base_hdr-&gt;wr_id[0] = cpu_to_le32(wqe_idx);</div><div class='ctx'> queue_err:</div><div class='ctx'> 	bnxt_qplib_swq_mod_start(rq, wqe_idx);</div><div class='del'>-	bnxt_qplib_hwq_incr_prod(hwq, swq-&gt;slots);</div><div class='add'>+	bnxt_qplib_hwq_incr_prod(&amp;rq-&gt;dbinfo, hwq, swq-&gt;slots);</div><div class='ctx'> done:</div><div class='ctx'> 	if (sch_handler) {</div><div class='ctx'> 		nq_work = kzalloc(sizeof(*nq_work), GFP_ATOMIC);</div><div class='hunk'>@@ -2086,6 +2138,7 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	cq-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	hwq_attr.res = res;</div><div class='ctx'> 	hwq_attr.depth = cq-&gt;max_wqe;</div><div class='ctx'> 	hwq_attr.stride = sizeof(struct cq_base);</div><div class='hunk'>@@ -2101,7 +2154,7 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)</div><div class='ctx'> </div><div class='ctx'> 	req.dpi = cpu_to_le32(cq-&gt;dpi-&gt;dpi);</div><div class='ctx'> 	req.cq_handle = cpu_to_le64(cq-&gt;cq_handle);</div><div class='del'>-	req.cq_size = cpu_to_le32(cq-&gt;hwq.max_elements);</div><div class='add'>+	req.cq_size = cpu_to_le32(cq-&gt;max_wqe);</div><div class='ctx'> 	pbl = &amp;cq-&gt;hwq.pbl[PBL_LVL_0];</div><div class='ctx'> 	pg_sz_lvl = (bnxt_qplib_base_pg_size(&amp;cq-&gt;hwq) &lt;&lt;</div><div class='ctx'> 		     CMDQ_CREATE_CQ_PG_SIZE_SFT);</div><div class='hunk'>@@ -2129,6 +2182,8 @@ int bnxt_qplib_create_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq)</div><div class='ctx'> 	cq-&gt;dbinfo.xid = cq-&gt;id;</div><div class='ctx'> 	cq-&gt;dbinfo.db = cq-&gt;dpi-&gt;dbr;</div><div class='ctx'> 	cq-&gt;dbinfo.priv_db = res-&gt;dpi_tbl.priv_db;</div><div class='add'>+	cq-&gt;dbinfo.flags = 0;</div><div class='add'>+	cq-&gt;dbinfo.toggle = 0;</div><div class='ctx'> </div><div class='ctx'> 	bnxt_qplib_armen_db(&amp;cq-&gt;dbinfo, DBC_DBC_TYPE_CQ_ARMENA);</div><div class='ctx'> </div><div class='hunk'>@@ -2144,6 +2199,8 @@ void bnxt_qplib_resize_cq_complete(struct bnxt_qplib_res *res,</div><div class='ctx'> {</div><div class='ctx'> 	bnxt_qplib_free_hwq(res, &amp;cq-&gt;hwq);</div><div class='ctx'> 	memcpy(&amp;cq-&gt;hwq, &amp;cq-&gt;resize_hwq, sizeof(cq-&gt;hwq));</div><div class='add'>+       /* Reset only the cons bit in the flags */</div><div class='add'>+	cq-&gt;dbinfo.flags &amp;= ~(1UL &lt;&lt; BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int bnxt_qplib_resize_cq(struct bnxt_qplib_res *res, struct bnxt_qplib_cq *cq,</div><div class='hunk'>@@ -2240,7 +2297,8 @@ static int __flush_sq(struct bnxt_qplib_q *sq, struct bnxt_qplib_qp *qp,</div><div class='ctx'> 		cqe++;</div><div class='ctx'> 		(*budget)--;</div><div class='ctx'> skip_compl:</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;sq-&gt;hwq, sq-&gt;swq[last].slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(sq-&gt;hwq.max_elements, &amp;sq-&gt;hwq.cons,</div><div class='add'>+					 sq-&gt;swq[last].slots, &amp;sq-&gt;dbinfo.flags);</div><div class='ctx'> 		sq-&gt;swq_last = sq-&gt;swq[last].next_idx;</div><div class='ctx'> 	}</div><div class='ctx'> 	*pcqe = cqe;</div><div class='hunk'>@@ -2287,7 +2345,8 @@ static int __flush_rq(struct bnxt_qplib_q *rq, struct bnxt_qplib_qp *qp,</div><div class='ctx'> 		cqe-&gt;wr_id = rq-&gt;swq[last].wr_id;</div><div class='ctx'> 		cqe++;</div><div class='ctx'> 		(*budget)--;</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;rq-&gt;hwq, rq-&gt;swq[last].slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(rq-&gt;hwq.max_elements, &amp;rq-&gt;hwq.cons,</div><div class='add'>+					 rq-&gt;swq[last].slots, &amp;rq-&gt;dbinfo.flags);</div><div class='ctx'> 		rq-&gt;swq_last = rq-&gt;swq[last].next_idx;</div><div class='ctx'> 	}</div><div class='ctx'> 	*pcqe = cqe;</div><div class='hunk'>@@ -2316,7 +2375,7 @@ void bnxt_qplib_mark_qp_error(void *qp_handle)</div><div class='ctx'> static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq,</div><div class='ctx'> 		     u32 cq_cons, u32 swq_last, u32 cqe_sq_cons)</div><div class='ctx'> {</div><div class='del'>-	u32 peek_sw_cq_cons, peek_raw_cq_cons, peek_sq_cons_idx;</div><div class='add'>+	u32 peek_sw_cq_cons, peek_sq_cons_idx, peek_flags;</div><div class='ctx'> 	struct bnxt_qplib_q *sq = &amp;qp-&gt;sq;</div><div class='ctx'> 	struct cq_req *peek_req_hwcqe;</div><div class='ctx'> 	struct bnxt_qplib_qp *peek_qp;</div><div class='hunk'>@@ -2347,16 +2406,14 @@ static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (sq-&gt;condition) {</div><div class='ctx'> 		/* Peek at the completions */</div><div class='del'>-		peek_raw_cq_cons = cq-&gt;hwq.cons;</div><div class='add'>+		peek_flags = cq-&gt;dbinfo.flags;</div><div class='ctx'> 		peek_sw_cq_cons = cq_cons;</div><div class='ctx'> 		i = cq-&gt;hwq.max_elements;</div><div class='ctx'> 		while (i--) {</div><div class='del'>-			peek_sw_cq_cons = HWQ_CMP((peek_sw_cq_cons), &amp;cq-&gt;hwq);</div><div class='ctx'> 			peek_hwcqe = bnxt_qplib_get_qe(&amp;cq-&gt;hwq,</div><div class='ctx'> 						       peek_sw_cq_cons, NULL);</div><div class='ctx'> 			/* If the next hwcqe is VALID */</div><div class='del'>-			if (CQE_CMP_VALID(peek_hwcqe, peek_raw_cq_cons,</div><div class='del'>-					  cq-&gt;hwq.max_elements)) {</div><div class='add'>+			if (CQE_CMP_VALID(peek_hwcqe, peek_flags)) {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * The valid test of the entry must be done first before</div><div class='ctx'> 			 * reading any further.</div><div class='hunk'>@@ -2399,8 +2456,9 @@ static int do_wa9060(struct bnxt_qplib_qp *qp, struct bnxt_qplib_cq *cq,</div><div class='ctx'> 				rc = -EINVAL;</div><div class='ctx'> 				goto out;</div><div class='ctx'> 			}</div><div class='del'>-			peek_sw_cq_cons++;</div><div class='del'>-			peek_raw_cq_cons++;</div><div class='add'>+			bnxt_qplib_hwq_incr_cons(cq-&gt;hwq.max_elements,</div><div class='add'>+						 &amp;peek_sw_cq_cons,</div><div class='add'>+						 1, &amp;peek_flags);</div><div class='ctx'> 		}</div><div class='ctx'> 		dev_err(&amp;cq-&gt;hwq.pdev-&gt;dev,</div><div class='ctx'> 			"Should not have come here! cq_cons=0x%x qp=0x%x sq cons sw=0x%x hw=0x%x\n",</div><div class='hunk'>@@ -2487,7 +2545,8 @@ static int bnxt_qplib_cq_process_req(struct bnxt_qplib_cq *cq,</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> skip:</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;sq-&gt;hwq, swq-&gt;slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(sq-&gt;hwq.max_elements, &amp;sq-&gt;hwq.cons,</div><div class='add'>+					 swq-&gt;slots, &amp;sq-&gt;dbinfo.flags);</div><div class='ctx'> 		sq-&gt;swq_last = swq-&gt;next_idx;</div><div class='ctx'> 		if (sq-&gt;single)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -2514,7 +2573,8 @@ static void bnxt_qplib_release_srqe(struct bnxt_qplib_srq *srq, u32 tag)</div><div class='ctx'> 	srq-&gt;swq[srq-&gt;last_idx].next_idx = (int)tag;</div><div class='ctx'> 	srq-&gt;last_idx = (int)tag;</div><div class='ctx'> 	srq-&gt;swq[srq-&gt;last_idx].next_idx = -1;</div><div class='del'>-	srq-&gt;hwq.cons++; /* Support for SRQE counter */</div><div class='add'>+	bnxt_qplib_hwq_incr_cons(srq-&gt;hwq.max_elements, &amp;srq-&gt;hwq.cons,</div><div class='add'>+				 srq-&gt;dbinfo.max_slot, &amp;srq-&gt;dbinfo.flags);</div><div class='ctx'> 	spin_unlock(&amp;srq-&gt;hwq.lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2583,7 +2643,8 @@ static int bnxt_qplib_cq_process_res_rc(struct bnxt_qplib_cq *cq,</div><div class='ctx'> 		cqe-&gt;wr_id = swq-&gt;wr_id;</div><div class='ctx'> 		cqe++;</div><div class='ctx'> 		(*budget)--;</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;rq-&gt;hwq, swq-&gt;slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(rq-&gt;hwq.max_elements, &amp;rq-&gt;hwq.cons,</div><div class='add'>+					 swq-&gt;slots, &amp;rq-&gt;dbinfo.flags);</div><div class='ctx'> 		rq-&gt;swq_last = swq-&gt;next_idx;</div><div class='ctx'> 		*pcqe = cqe;</div><div class='ctx'> </div><div class='hunk'>@@ -2669,7 +2730,8 @@ static int bnxt_qplib_cq_process_res_ud(struct bnxt_qplib_cq *cq,</div><div class='ctx'> 		cqe-&gt;wr_id = swq-&gt;wr_id;</div><div class='ctx'> 		cqe++;</div><div class='ctx'> 		(*budget)--;</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;rq-&gt;hwq, swq-&gt;slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(rq-&gt;hwq.max_elements, &amp;rq-&gt;hwq.cons,</div><div class='add'>+					 swq-&gt;slots, &amp;rq-&gt;dbinfo.flags);</div><div class='ctx'> 		rq-&gt;swq_last = swq-&gt;next_idx;</div><div class='ctx'> 		*pcqe = cqe;</div><div class='ctx'> </div><div class='hunk'>@@ -2686,14 +2748,11 @@ static int bnxt_qplib_cq_process_res_ud(struct bnxt_qplib_cq *cq,</div><div class='ctx'> bool bnxt_qplib_is_cq_empty(struct bnxt_qplib_cq *cq)</div><div class='ctx'> {</div><div class='ctx'> 	struct cq_base *hw_cqe;</div><div class='del'>-	u32 sw_cons, raw_cons;</div><div class='ctx'> 	bool rc = true;</div><div class='ctx'> </div><div class='del'>-	raw_cons = cq-&gt;hwq.cons;</div><div class='del'>-	sw_cons = HWQ_CMP(raw_cons, &amp;cq-&gt;hwq);</div><div class='del'>-	hw_cqe = bnxt_qplib_get_qe(&amp;cq-&gt;hwq, sw_cons, NULL);</div><div class='add'>+	hw_cqe = bnxt_qplib_get_qe(&amp;cq-&gt;hwq, cq-&gt;hwq.cons, NULL);</div><div class='ctx'> 	 /* Check for Valid bit. If the CQE is valid, return false */</div><div class='del'>-	rc = !CQE_CMP_VALID(hw_cqe, raw_cons, cq-&gt;hwq.max_elements);</div><div class='add'>+	rc = !CQE_CMP_VALID(hw_cqe, cq-&gt;dbinfo.flags);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2775,7 +2834,8 @@ static int bnxt_qplib_cq_process_res_raweth_qp1(struct bnxt_qplib_cq *cq,</div><div class='ctx'> 		cqe-&gt;wr_id = swq-&gt;wr_id;</div><div class='ctx'> 		cqe++;</div><div class='ctx'> 		(*budget)--;</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;rq-&gt;hwq, swq-&gt;slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(rq-&gt;hwq.max_elements, &amp;rq-&gt;hwq.cons,</div><div class='add'>+					 swq-&gt;slots, &amp;rq-&gt;dbinfo.flags);</div><div class='ctx'> 		rq-&gt;swq_last = swq-&gt;next_idx;</div><div class='ctx'> 		*pcqe = cqe;</div><div class='ctx'> </div><div class='hunk'>@@ -2848,7 +2908,8 @@ static int bnxt_qplib_cq_process_terminal(struct bnxt_qplib_cq *cq,</div><div class='ctx'> 			cqe++;</div><div class='ctx'> 			(*budget)--;</div><div class='ctx'> 		}</div><div class='del'>-		bnxt_qplib_hwq_incr_cons(&amp;sq-&gt;hwq, sq-&gt;swq[swq_last].slots);</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(sq-&gt;hwq.max_elements, &amp;sq-&gt;hwq.cons,</div><div class='add'>+					 sq-&gt;swq[swq_last].slots, &amp;sq-&gt;dbinfo.flags);</div><div class='ctx'> 		sq-&gt;swq_last = sq-&gt;swq[swq_last].next_idx;</div><div class='ctx'> 	}</div><div class='ctx'> 	*pcqe = cqe;</div><div class='hunk'>@@ -2933,19 +2994,17 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,</div><div class='ctx'> 		       int num_cqes, struct bnxt_qplib_qp **lib_qp)</div><div class='ctx'> {</div><div class='ctx'> 	struct cq_base *hw_cqe;</div><div class='del'>-	u32 sw_cons, raw_cons;</div><div class='ctx'> 	int budget, rc = 0;</div><div class='add'>+	u32 hw_polled = 0;</div><div class='ctx'> 	u8 type;</div><div class='ctx'> </div><div class='del'>-	raw_cons = cq-&gt;hwq.cons;</div><div class='ctx'> 	budget = num_cqes;</div><div class='ctx'> </div><div class='ctx'> 	while (budget) {</div><div class='del'>-		sw_cons = HWQ_CMP(raw_cons, &amp;cq-&gt;hwq);</div><div class='del'>-		hw_cqe = bnxt_qplib_get_qe(&amp;cq-&gt;hwq, sw_cons, NULL);</div><div class='add'>+		hw_cqe = bnxt_qplib_get_qe(&amp;cq-&gt;hwq, cq-&gt;hwq.cons, NULL);</div><div class='ctx'> </div><div class='ctx'> 		/* Check for Valid bit */</div><div class='del'>-		if (!CQE_CMP_VALID(hw_cqe, raw_cons, cq-&gt;hwq.max_elements))</div><div class='add'>+		if (!CQE_CMP_VALID(hw_cqe, cq-&gt;dbinfo.flags))</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -2960,7 +3019,7 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,</div><div class='ctx'> 			rc = bnxt_qplib_cq_process_req(cq,</div><div class='ctx'> 						       (struct cq_req *)hw_cqe,</div><div class='ctx'> 						       &amp;cqe, &amp;budget,</div><div class='del'>-						       sw_cons, lib_qp);</div><div class='add'>+						       cq-&gt;hwq.cons, lib_qp);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case CQ_BASE_CQE_TYPE_RES_RC:</div><div class='ctx'> 			rc = bnxt_qplib_cq_process_res_rc(cq,</div><div class='hunk'>@@ -3006,18 +3065,20 @@ int bnxt_qplib_poll_cq(struct bnxt_qplib_cq *cq, struct bnxt_qplib_cqe *cqe,</div><div class='ctx'> 				dev_err(&amp;cq-&gt;hwq.pdev-&gt;dev,</div><div class='ctx'> 					"process_cqe error rc = 0x%x\n", rc);</div><div class='ctx'> 		}</div><div class='del'>-		raw_cons++;</div><div class='add'>+		hw_polled++;</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(cq-&gt;hwq.max_elements, &amp;cq-&gt;hwq.cons,</div><div class='add'>+					 1, &amp;cq-&gt;dbinfo.flags);</div><div class='add'>+</div><div class='ctx'> 	}</div><div class='del'>-	if (cq-&gt;hwq.cons != raw_cons) {</div><div class='del'>-		cq-&gt;hwq.cons = raw_cons;</div><div class='add'>+	if (hw_polled)</div><div class='ctx'> 		bnxt_qplib_ring_db(&amp;cq-&gt;dbinfo, DBC_DBC_TYPE_CQ);</div><div class='del'>-	}</div><div class='ctx'> exit:</div><div class='ctx'> 	return num_cqes - budget;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type)</div><div class='ctx'> {</div><div class='add'>+	cq-&gt;dbinfo.toggle = cq-&gt;toggle;</div><div class='ctx'> 	if (arm_type)</div><div class='ctx'> 		bnxt_qplib_ring_db(&amp;cq-&gt;dbinfo, arm_type);</div><div class='ctx'> 	/* Using cq-&gt;arm_state variable to track whether to issue cq handler */</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.h b/drivers/infiniband/hw/bnxt_re/qplib_fp.h<br/>index 404b851091ca..7fd4506b3584 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_fp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_fp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_fp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_fp.h</a></div><div class='hunk'>@@ -338,6 +338,9 @@ struct bnxt_qplib_qp {</div><div class='ctx'> 	dma_addr_t			rq_hdr_buf_map;</div><div class='ctx'> 	struct list_head		sq_flush;</div><div class='ctx'> 	struct list_head		rq_flush;</div><div class='add'>+	u32				msn;</div><div class='add'>+	u32				msn_tbl_sz;</div><div class='add'>+	u16				dev_cap_flags;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE	sizeof(struct cq_base)</div><div class='hunk'>@@ -348,9 +351,21 @@ struct bnxt_qplib_qp {</div><div class='ctx'> #define CQE_IDX(x)		((x) &amp; CQE_MAX_IDX_PER_PG)</div><div class='ctx'> </div><div class='ctx'> #define ROCE_CQE_CMP_V			0</div><div class='del'>-#define CQE_CMP_VALID(hdr, raw_cons, cp_bit)			\</div><div class='add'>+#define CQE_CMP_VALID(hdr, pass)			\</div><div class='ctx'> 	(!!((hdr)-&gt;cqe_type_toggle &amp; CQ_BASE_TOGGLE) ==		\</div><div class='del'>-	   !((raw_cons) &amp; (cp_bit)))</div><div class='add'>+	   !((pass) &amp; BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))</div><div class='add'>+</div><div class='add'>+static inline u32 __bnxt_qplib_get_avail(struct bnxt_qplib_hwq *hwq)</div><div class='add'>+{</div><div class='add'>+	int cons, prod, avail;</div><div class='add'>+</div><div class='add'>+	cons = hwq-&gt;cons;</div><div class='add'>+	prod = hwq-&gt;prod;</div><div class='add'>+	avail = cons - prod;</div><div class='add'>+	if (cons &lt;= prod)</div><div class='add'>+		avail += hwq-&gt;depth;</div><div class='add'>+	return avail;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static inline bool bnxt_qplib_queue_full(struct bnxt_qplib_q *que,</div><div class='ctx'> 					 u8 slots)</div><div class='hunk'>@@ -406,6 +421,7 @@ struct bnxt_qplib_cq {</div><div class='ctx'> 	bool				resize_in_progress;</div><div class='ctx'> 	struct bnxt_qplib_sg_info	sg_info;</div><div class='ctx'> 	u64				cq_handle;</div><div class='add'>+	u8				toggle;</div><div class='ctx'> </div><div class='ctx'> #define CQ_RESIZE_WAIT_TIME_MS		500</div><div class='ctx'> 	unsigned long			flags;</div><div class='hunk'>@@ -443,9 +459,9 @@ struct bnxt_qplib_cq {</div><div class='ctx'> #define NQE_PG(x)		(((x) &amp; ~NQE_MAX_IDX_PER_PG) / NQE_CNT_PER_PG)</div><div class='ctx'> #define NQE_IDX(x)		((x) &amp; NQE_MAX_IDX_PER_PG)</div><div class='ctx'> </div><div class='del'>-#define NQE_CMP_VALID(hdr, raw_cons, cp_bit)			\</div><div class='add'>+#define NQE_CMP_VALID(hdr, pass)			\</div><div class='ctx'> 	(!!(le32_to_cpu((hdr)-&gt;info63_v[0]) &amp; NQ_BASE_V) ==	\</div><div class='del'>-	   !((raw_cons) &amp; (cp_bit)))</div><div class='add'>+	   !((pass) &amp; BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))</div><div class='ctx'> </div><div class='ctx'> #define BNXT_QPLIB_NQE_MAX_CNT		(128 * 1024)</div><div class='ctx'> </div><div class='hunk'>@@ -614,4 +630,15 @@ static inline u16 bnxt_qplib_calc_ilsize(struct bnxt_qplib_swqe *wqe, u16 max)</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/* MSN table update inlin */</div><div class='add'>+static inline __le64 bnxt_re_update_msn_tbl(u32 st_idx, u32 npsn, u32 start_psn)</div><div class='add'>+{</div><div class='add'>+	return cpu_to_le64((((u64)(st_idx) &lt;&lt; SQ_MSN_SEARCH_START_IDX_SFT) &amp;</div><div class='add'>+		SQ_MSN_SEARCH_START_IDX_MASK) |</div><div class='add'>+		(((u64)(npsn) &lt;&lt; SQ_MSN_SEARCH_NEXT_PSN_SFT) &amp;</div><div class='add'>+		SQ_MSN_SEARCH_NEXT_PSN_MASK) |</div><div class='add'>+		(((start_psn) &lt;&lt; SQ_MSN_SEARCH_START_PSN_SFT) &amp;</div><div class='add'>+		SQ_MSN_SEARCH_START_PSN_MASK));</div><div class='add'>+}</div><div class='ctx'> #endif /* __BNXT_QPLIB_FP_H__ */</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c<br/>index e47b4ca64d33..3ffaef0c2651 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_rcfw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.c</a></div><div class='hunk'>@@ -734,17 +734,15 @@ static void bnxt_qplib_service_creq(struct tasklet_struct *t)</div><div class='ctx'> 	u32 type, budget = CREQ_ENTRY_POLL_BUDGET;</div><div class='ctx'> 	struct bnxt_qplib_hwq *hwq = &amp;creq-&gt;hwq;</div><div class='ctx'> 	struct creq_base *creqe;</div><div class='del'>-	u32 sw_cons, raw_cons;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 num_wakeup = 0;</div><div class='add'>+	u32 hw_polled = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Service the CREQ until budget is over */</div><div class='ctx'> 	spin_lock_irqsave(&amp;hwq-&gt;lock, flags);</div><div class='del'>-	raw_cons = hwq-&gt;cons;</div><div class='ctx'> 	while (budget &gt; 0) {</div><div class='del'>-		sw_cons = HWQ_CMP(raw_cons, hwq);</div><div class='del'>-		creqe = bnxt_qplib_get_qe(hwq, sw_cons, NULL);</div><div class='del'>-		if (!CREQ_CMP_VALID(creqe, raw_cons, hwq-&gt;max_elements))</div><div class='add'>+		creqe = bnxt_qplib_get_qe(hwq, hwq-&gt;cons, NULL);</div><div class='add'>+		if (!CREQ_CMP_VALID(creqe, creq-&gt;creq_db.dbinfo.flags))</div><div class='ctx'> 			break;</div><div class='ctx'> 		/* The valid test of the entry must be done first before</div><div class='ctx'> 		 * reading any further.</div><div class='hunk'>@@ -775,15 +773,15 @@ static void bnxt_qplib_service_creq(struct tasklet_struct *t)</div><div class='ctx'> 					 type);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		raw_cons++;</div><div class='ctx'> 		budget--;</div><div class='add'>+		hw_polled++;</div><div class='add'>+		bnxt_qplib_hwq_incr_cons(hwq-&gt;max_elements, &amp;hwq-&gt;cons,</div><div class='add'>+					 1, &amp;creq-&gt;creq_db.dbinfo.flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hwq-&gt;cons != raw_cons) {</div><div class='del'>-		hwq-&gt;cons = raw_cons;</div><div class='add'>+	if (hw_polled)</div><div class='ctx'> 		bnxt_qplib_ring_nq_db(&amp;creq-&gt;creq_db.dbinfo,</div><div class='ctx'> 				      rcfw-&gt;res-&gt;cctx, true);</div><div class='del'>-	}</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;hwq-&gt;lock, flags);</div><div class='ctx'> 	if (num_wakeup)</div><div class='ctx'> 		wake_up_nr(&amp;rcfw-&gt;cmdq.waitq, num_wakeup);</div><div class='hunk'>@@ -854,7 +852,7 @@ int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (is_virtfn)</div><div class='ctx'> 		goto skip_ctx_setup;</div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(rcfw-&gt;res-&gt;cctx))</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(rcfw-&gt;res-&gt;cctx))</div><div class='ctx'> 		goto config_vf_res;</div><div class='ctx'> </div><div class='ctx'> 	lvl = ctx-&gt;qpc_tbl.level;</div><div class='hunk'>@@ -907,6 +905,8 @@ config_vf_res:</div><div class='ctx'> 	req.max_gid_per_vf = cpu_to_le32(ctx-&gt;vf_res.max_gid_per_vf);</div><div class='ctx'> </div><div class='ctx'> skip_ctx_setup:</div><div class='add'>+	if (BNXT_RE_HW_RETX(rcfw-&gt;res-&gt;dattr-&gt;dev_cap_flags))</div><div class='add'>+		req.flags |= cpu_to_le16(CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED);</div><div class='ctx'> 	req.stat_ctx_id = cpu_to_le32(ctx-&gt;stats.fw_id);</div><div class='ctx'> 	bnxt_qplib_fill_cmdqmsg(&amp;msg, &amp;req, &amp;resp, NULL, sizeof(req), sizeof(resp), 0);</div><div class='ctx'> 	rc = bnxt_qplib_rcfw_send_message(rcfw, &amp;msg);</div><div class='hunk'>@@ -1113,6 +1113,7 @@ static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt)</div><div class='ctx'> 	pdev = rcfw-&gt;pdev;</div><div class='ctx'> 	creq_db = &amp;rcfw-&gt;creq.creq_db;</div><div class='ctx'> </div><div class='add'>+	creq_db-&gt;dbinfo.flags = 0;</div><div class='ctx'> 	creq_db-&gt;reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION;</div><div class='ctx'> 	creq_db-&gt;reg.bar_base = pci_resource_start(pdev, creq_db-&gt;reg.bar_id);</div><div class='ctx'> 	if (!creq_db-&gt;reg.bar_id)</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h b/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h<br/>index 7b31bee3e000..45996e60a0d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_rcfw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_rcfw.h</a></div><div class='hunk'>@@ -141,9 +141,9 @@ struct bnxt_qplib_crsbe {</div><div class='ctx'> /* Allocate 1 per QP for async error notification for now */</div><div class='ctx'> #define BNXT_QPLIB_CREQE_MAX_CNT	(64 * 1024)</div><div class='ctx'> #define BNXT_QPLIB_CREQE_UNITS		16	/* 16-Bytes per prod unit */</div><div class='del'>-#define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)			\</div><div class='add'>+#define CREQ_CMP_VALID(hdr, pass)			\</div><div class='ctx'> 	(!!((hdr)-&gt;v &amp; CREQ_BASE_V) ==				\</div><div class='del'>-	   !((raw_cons) &amp; (cp_bit)))</div><div class='add'>+	   !((pass) &amp; BNXT_QPLIB_FLAG_EPOCH_CONS_MASK))</div><div class='ctx'> #define CREQ_ENTRY_POLL_BUDGET		0x100</div><div class='ctx'> </div><div class='ctx'> /* HWQ */</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.c b/drivers/infiniband/hw/bnxt_re/qplib_res.c<br/>index 157db6b7e119..dfc943fab87b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_res.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_res.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_res.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_res.c</a></div><div class='hunk'>@@ -343,7 +343,7 @@ done:</div><div class='ctx'> 	hwq-&gt;cons = 0;</div><div class='ctx'> 	hwq-&gt;pdev = pdev;</div><div class='ctx'> 	hwq-&gt;depth = hwq_attr-&gt;depth;</div><div class='del'>-	hwq-&gt;max_elements = depth;</div><div class='add'>+	hwq-&gt;max_elements = hwq-&gt;depth;</div><div class='ctx'> 	hwq-&gt;element_size = stride;</div><div class='ctx'> 	hwq-&gt;qe_ppg = pg_size / stride;</div><div class='ctx'> 	/* For direct access to the elements */</div><div class='hunk'>@@ -805,7 +805,7 @@ static int bnxt_qplib_alloc_dpi_tbl(struct bnxt_qplib_res *res,</div><div class='ctx'> 	dpit = &amp;res-&gt;dpi_tbl;</div><div class='ctx'> 	reg = &amp;dpit-&gt;wcreg;</div><div class='ctx'> </div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(res-&gt;cctx)) {</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(res-&gt;cctx)) {</div><div class='ctx'> 		/* Offest should come from L2 driver */</div><div class='ctx'> 		dbr_offset = dev_attr-&gt;l2_db_size;</div><div class='ctx'> 		dpit-&gt;ucreg.offset = dbr_offset;</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.h b/drivers/infiniband/hw/bnxt_re/qplib_res.h<br/>index 5949f004f785..61628f7f1253 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_res.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_res.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_res.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_res.h</a></div><div class='hunk'>@@ -44,11 +44,23 @@ extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;</div><div class='ctx'> #define CHIP_NUM_57508		0x1750</div><div class='ctx'> #define CHIP_NUM_57504		0x1751</div><div class='ctx'> #define CHIP_NUM_57502		0x1752</div><div class='add'>+#define CHIP_NUM_58818          0xd818</div><div class='add'>+#define CHIP_NUM_57608          0x1760</div><div class='add'>+</div><div class='add'>+#define BNXT_QPLIB_DBR_VALID		(0x1UL &lt;&lt; 26)</div><div class='add'>+#define BNXT_QPLIB_DBR_EPOCH_SHIFT	24</div><div class='add'>+#define BNXT_QPLIB_DBR_TOGGLE_SHIFT	25</div><div class='ctx'> </div><div class='ctx'> struct bnxt_qplib_drv_modes {</div><div class='ctx'> 	u8	wqe_mode;</div><div class='ctx'> 	bool db_push;</div><div class='ctx'> 	bool dbr_pacing;</div><div class='add'>+	u32 toggle_bits;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bnxt_re_toggle_modes {</div><div class='add'>+	BNXT_QPLIB_CQ_TOGGLE_BIT = 0x1,</div><div class='add'>+	BNXT_QPLIB_SRQ_TOGGLE_BIT = 0x2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bnxt_qplib_chip_ctx {</div><div class='hunk'>@@ -186,6 +198,20 @@ struct bnxt_qplib_db_info {</div><div class='ctx'> 	struct bnxt_qplib_hwq	*hwq;</div><div class='ctx'> 	u32			xid;</div><div class='ctx'> 	u32			max_slot;</div><div class='add'>+	u32                     flags;</div><div class='add'>+	u8			toggle;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bnxt_qplib_db_info_flags_mask {</div><div class='add'>+	BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT        = 0x0UL,</div><div class='add'>+	BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT        = 0x1UL,</div><div class='add'>+	BNXT_QPLIB_FLAG_EPOCH_CONS_MASK         = 0x1UL,</div><div class='add'>+	BNXT_QPLIB_FLAG_EPOCH_PROD_MASK         = 0x2UL,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum bnxt_qplib_db_epoch_flag_shift {</div><div class='add'>+	BNXT_QPLIB_DB_EPOCH_CONS_SHIFT  = BNXT_QPLIB_DBR_EPOCH_SHIFT,</div><div class='add'>+	BNXT_QPLIB_DB_EPOCH_PROD_SHIFT  = (BNXT_QPLIB_DBR_EPOCH_SHIFT - 1),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Tables */</div><div class='hunk'>@@ -288,6 +314,12 @@ struct bnxt_qplib_res {</div><div class='ctx'> 	struct bnxt_qplib_db_pacing_data *pacing_data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx)</div><div class='add'>+{</div><div class='add'>+	return (cctx-&gt;chip_num == CHIP_NUM_58818 ||</div><div class='add'>+		cctx-&gt;chip_num == CHIP_NUM_57608);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)</div><div class='ctx'> {</div><div class='ctx'> 	return (cctx-&gt;chip_num == CHIP_NUM_57508 ||</div><div class='hunk'>@@ -295,15 +327,20 @@ static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)</div><div class='ctx'> 		cctx-&gt;chip_num == CHIP_NUM_57502);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx)</div><div class='add'>+{</div><div class='add'>+	return bnxt_qplib_is_chip_gen_p5(cctx) || bnxt_qplib_is_chip_gen_p7(cctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)</div><div class='ctx'> {</div><div class='del'>-	return bnxt_qplib_is_chip_gen_p5(res-&gt;cctx) ?</div><div class='add'>+	return bnxt_qplib_is_chip_gen_p5_p7(res-&gt;cctx) ?</div><div class='ctx'> 					HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)</div><div class='ctx'> {</div><div class='del'>-	return bnxt_qplib_is_chip_gen_p5(cctx) ?</div><div class='add'>+	return bnxt_qplib_is_chip_gen_p5_p7(cctx) ?</div><div class='ctx'> 	       RING_ALLOC_REQ_RING_TYPE_NQ :</div><div class='ctx'> 	       RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;</div><div class='ctx'> }</div><div class='hunk'>@@ -396,39 +433,61 @@ void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res);</div><div class='ctx'> </div><div class='ctx'> int bnxt_qplib_determine_atomics(struct pci_dev *dev);</div><div class='ctx'> </div><div class='del'>-static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)</div><div class='add'>+static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo,</div><div class='add'>+					    struct bnxt_qplib_hwq *hwq, u32 cnt)</div><div class='ctx'> {</div><div class='del'>-	hwq-&gt;prod = (hwq-&gt;prod + cnt) % hwq-&gt;depth;</div><div class='add'>+	/* move prod and update toggle/epoch if wrap around */</div><div class='add'>+	hwq-&gt;prod += cnt;</div><div class='add'>+	if (hwq-&gt;prod &gt;= hwq-&gt;depth) {</div><div class='add'>+		hwq-&gt;prod %= hwq-&gt;depth;</div><div class='add'>+		dbinfo-&gt;flags ^= 1UL &lt;&lt; BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,</div><div class='del'>-					    u32 cnt)</div><div class='add'>+static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt,</div><div class='add'>+					    u32 *dbinfo_flags)</div><div class='ctx'> {</div><div class='del'>-	hwq-&gt;cons = (hwq-&gt;cons + cnt) % hwq-&gt;depth;</div><div class='add'>+	/* move cons and update toggle/epoch if wrap around */</div><div class='add'>+	*cons += cnt;</div><div class='add'>+	if (*cons &gt;= max_elements) {</div><div class='add'>+		*cons %= max_elements;</div><div class='add'>+		*dbinfo_flags ^= 1UL &lt;&lt; BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,</div><div class='ctx'> 					bool arm)</div><div class='ctx'> {</div><div class='del'>-	u32 key;</div><div class='add'>+	u32 key = 0;</div><div class='ctx'> </div><div class='del'>-	key = info-&gt;hwq-&gt;cons &amp; (info-&gt;hwq-&gt;max_elements - 1);</div><div class='del'>-	key |= (CMPL_DOORBELL_IDX_VALID |</div><div class='add'>+	key |= info-&gt;hwq-&gt;cons | (CMPL_DOORBELL_IDX_VALID |</div><div class='ctx'> 		(CMPL_DOORBELL_KEY_CMPL &amp; CMPL_DOORBELL_KEY_MASK));</div><div class='ctx'> 	if (!arm)</div><div class='ctx'> 		key |= CMPL_DOORBELL_MASK;</div><div class='ctx'> 	writel(key, info-&gt;db);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define BNXT_QPLIB_INIT_DBHDR(xid, type, indx, toggle) \</div><div class='add'>+	(((u64)(((xid) &amp; DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE |  \</div><div class='add'>+		(type) | BNXT_QPLIB_DBR_VALID) &lt;&lt; 32) | (indx) |  \</div><div class='add'>+	 (((u32)(toggle)) &lt;&lt; (BNXT_QPLIB_DBR_TOGGLE_SHIFT)))</div><div class='add'>+</div><div class='ctx'> static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,</div><div class='ctx'> 				      u32 type)</div><div class='ctx'> {</div><div class='ctx'> 	u64 key = 0;</div><div class='add'>+	u32 indx;</div><div class='add'>+	u8 toggle = 0;</div><div class='add'>+</div><div class='add'>+	if (type == DBC_DBC_TYPE_CQ_ARMALL ||</div><div class='add'>+	    type == DBC_DBC_TYPE_CQ_ARMSE)</div><div class='add'>+		toggle = info-&gt;toggle;</div><div class='add'>+</div><div class='add'>+	indx = (info-&gt;hwq-&gt;cons &amp; DBC_DBC_INDEX_MASK) |</div><div class='add'>+	       ((info-&gt;flags &amp; BNXT_QPLIB_FLAG_EPOCH_CONS_MASK) &lt;&lt;</div><div class='add'>+		 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT);</div><div class='ctx'> </div><div class='del'>-	key = (info-&gt;xid &amp; DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;</div><div class='del'>-	key &lt;&lt;= 32;</div><div class='del'>-	key |= (info-&gt;hwq-&gt;cons &amp; (info-&gt;hwq-&gt;max_elements - 1)) &amp;</div><div class='del'>-		DBC_DBC_INDEX_MASK;</div><div class='add'>+	key =  BNXT_QPLIB_INIT_DBHDR(info-&gt;xid, type, indx, toggle);</div><div class='ctx'> 	writeq(key, info-&gt;db);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -436,10 +495,12 @@ static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,</div><div class='ctx'> 					   u32 type)</div><div class='ctx'> {</div><div class='ctx'> 	u64 key = 0;</div><div class='add'>+	u32 indx;</div><div class='ctx'> </div><div class='del'>-	key = (info-&gt;xid &amp; DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;</div><div class='del'>-	key &lt;&lt;= 32;</div><div class='del'>-	key |= ((info-&gt;hwq-&gt;prod / info-&gt;max_slot)) &amp; DBC_DBC_INDEX_MASK;</div><div class='add'>+	indx = (((info-&gt;hwq-&gt;prod / info-&gt;max_slot) &amp; DBC_DBC_INDEX_MASK) |</div><div class='add'>+		((info-&gt;flags &amp; BNXT_QPLIB_FLAG_EPOCH_PROD_MASK) &lt;&lt;</div><div class='add'>+		 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT));</div><div class='add'>+	key = BNXT_QPLIB_INIT_DBHDR(info-&gt;xid, type, indx, 0);</div><div class='ctx'> 	writeq(key, info-&gt;db);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -447,9 +508,12 @@ static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,</div><div class='ctx'> 				       u32 type)</div><div class='ctx'> {</div><div class='ctx'> 	u64 key = 0;</div><div class='add'>+	u8 toggle = 0;</div><div class='ctx'> </div><div class='del'>-	key = (info-&gt;xid &amp; DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;</div><div class='del'>-	key &lt;&lt;= 32;</div><div class='add'>+	if (type == DBC_DBC_TYPE_CQ_ARMENA || type == DBC_DBC_TYPE_SRQ_ARMENA)</div><div class='add'>+		toggle = info-&gt;toggle;</div><div class='add'>+	/* Index always at 0 */</div><div class='add'>+	key = BNXT_QPLIB_INIT_DBHDR(info-&gt;xid, type, 0, toggle);</div><div class='ctx'> 	writeq(key, info-&gt;priv_db);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -458,9 +522,7 @@ static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,</div><div class='ctx'> {</div><div class='ctx'> 	u64 key = 0;</div><div class='ctx'> </div><div class='del'>-	key = (info-&gt;xid &amp; DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;</div><div class='del'>-	key &lt;&lt;= 32;</div><div class='del'>-	key |=  th &amp; DBC_DBC_INDEX_MASK;</div><div class='add'>+	key = BNXT_QPLIB_INIT_DBHDR(info-&gt;xid, DBC_DBC_TYPE_SRQ_ARM, th, info-&gt;toggle);</div><div class='ctx'> 	writeq(key, info-&gt;priv_db);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -471,7 +533,7 @@ static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,</div><div class='ctx'> 	u32 type;</div><div class='ctx'> </div><div class='ctx'> 	type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;</div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(cctx))</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(cctx))</div><div class='ctx'> 		bnxt_qplib_ring_db(info, type);</div><div class='ctx'> 	else</div><div class='ctx'> 		bnxt_qplib_ring_db32(info, arm);</div><div class='hunk'>@@ -483,6 +545,15 @@ static inline bool _is_ext_stats_supported(u16 dev_cap_flags)</div><div class='ctx'> 		CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool _is_hw_retx_supported(u16 dev_cap_flags)</div><div class='add'>+{</div><div class='add'>+	return dev_cap_flags &amp;</div><div class='add'>+		(CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED |</div><div class='add'>+		 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a))</div><div class='add'>+</div><div class='ctx'> static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx)</div><div class='ctx'> {</div><div class='ctx'> 	return cctx-&gt;modes.dbr_pacing;</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c<br/>index a27b68515164..8beeedd15061 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_sp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/qplib_sp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/qplib_sp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/qplib_sp.c</a></div><div class='hunk'>@@ -59,7 +59,7 @@ static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)</div><div class='ctx'> {</div><div class='ctx'> 	u16 pcie_ctl2 = 0;</div><div class='ctx'> </div><div class='del'>-	if (!bnxt_qplib_is_chip_gen_p5(rcfw-&gt;res-&gt;cctx))</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw-&gt;res-&gt;cctx))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	pcie_capability_read_word(rcfw-&gt;pdev, PCI_EXP_DEVCTL2, &amp;pcie_ctl2);</div><div class='hunk'>@@ -133,7 +133,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,</div><div class='ctx'> 	 * reporting the max number</div><div class='ctx'> 	 */</div><div class='ctx'> 	attr-&gt;max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1;</div><div class='del'>-	attr-&gt;max_qp_sges = bnxt_qplib_is_chip_gen_p5(rcfw-&gt;res-&gt;cctx) ?</div><div class='add'>+	attr-&gt;max_qp_sges = bnxt_qplib_is_chip_gen_p5_p7(rcfw-&gt;res-&gt;cctx) ?</div><div class='ctx'> 			    6 : sb-&gt;max_sge;</div><div class='ctx'> 	attr-&gt;max_cq = le32_to_cpu(sb-&gt;max_cq);</div><div class='ctx'> 	attr-&gt;max_cq_wqes = le32_to_cpu(sb-&gt;max_cqe);</div><div class='hunk'>@@ -151,8 +151,9 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,</div><div class='ctx'> 	attr-&gt;max_srq_sges = sb-&gt;max_srq_sge;</div><div class='ctx'> 	attr-&gt;max_pkey = 1;</div><div class='ctx'> 	attr-&gt;max_inline_data = le32_to_cpu(sb-&gt;max_inline_data);</div><div class='del'>-	attr-&gt;l2_db_size = (sb-&gt;l2_db_space_size + 1) *</div><div class='del'>-			    (0x01 &lt;&lt; RCFW_DBR_BASE_PAGE_SHIFT);</div><div class='add'>+	if (!bnxt_qplib_is_chip_gen_p7(rcfw-&gt;res-&gt;cctx))</div><div class='add'>+		attr-&gt;l2_db_size = (sb-&gt;l2_db_space_size + 1) *</div><div class='add'>+				    (0x01 &lt;&lt; RCFW_DBR_BASE_PAGE_SHIFT);</div><div class='ctx'> 	attr-&gt;max_sgid = BNXT_QPLIB_NUM_GIDS_SUPPORTED;</div><div class='ctx'> 	attr-&gt;dev_cap_flags = le16_to_cpu(sb-&gt;dev_cap_flags);</div><div class='ctx'> </div><div class='hunk'>@@ -934,7 +935,7 @@ int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res,</div><div class='ctx'> 	req-&gt;inactivity_th = cpu_to_le16(cc_param-&gt;inact_th);</div><div class='ctx'> </div><div class='ctx'> 	/* For chip gen P5 onwards fill extended cmd and header */</div><div class='del'>-	if (bnxt_qplib_is_chip_gen_p5(res-&gt;cctx)) {</div><div class='add'>+	if (bnxt_qplib_is_chip_gen_p5_p7(res-&gt;cctx)) {</div><div class='ctx'> 		struct roce_tlv *hdr;</div><div class='ctx'> 		u32 payload;</div><div class='ctx'> 		u32 chunks;</div><div class='head'>diff --git a/drivers/infiniband/hw/bnxt_re/roce_hsi.h b/drivers/infiniband/hw/bnxt_re/roce_hsi.h<br/>index 84b5acd7f7a2..605c9463c408 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/roce_hsi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/bnxt_re/roce_hsi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/bnxt_re/roce_hsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/bnxt_re/roce_hsi.h</a></div><div class='hunk'>@@ -555,7 +555,12 @@ struct cmdq_modify_qp {</div><div class='ctx'> 	__le16	flags;</div><div class='ctx'> 	__le16	cookie;</div><div class='ctx'> 	u8	resp_size;</div><div class='del'>-	u8	reserved8;</div><div class='add'>+	u8	qp_type;</div><div class='add'>+	#define CMDQ_MODIFY_QP_QP_TYPE_RC            0x2UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_QP_TYPE_UD            0x4UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_QP_TYPE_GSI           0x7UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_QP_TYPE_LAST         CMDQ_MODIFY_QP_QP_TYPE_GSI</div><div class='ctx'> 	__le64	resp_addr;</div><div class='ctx'> 	__le32	modify_mask;</div><div class='ctx'> 	#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE                   0x1UL</div><div class='hunk'>@@ -611,14 +616,12 @@ struct cmdq_modify_qp {</div><div class='ctx'> 	#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6  (0x3UL &lt;&lt; 6)</div><div class='ctx'> 	#define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST        CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6</div><div class='ctx'> 	u8	access;</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK \</div><div class='del'>-		0xffUL</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT	\</div><div class='del'>-		0</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE	0x1UL</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE	0x2UL</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ	0x4UL</div><div class='del'>-	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC	0x8UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE   0x1UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE  0x2UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ   0x4UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL</div><div class='ctx'> 	__le16	pkey;</div><div class='ctx'> 	__le32	qkey;</div><div class='ctx'> 	__le32	dgid[4];</div><div class='hunk'>@@ -673,6 +676,13 @@ struct cmdq_modify_qp {</div><div class='ctx'> 	#define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13</div><div class='ctx'> 	__le64	irrq_addr;</div><div class='ctx'> 	__le64	orrq_addr;</div><div class='add'>+	__le32	ext_modify_mask;</div><div class='add'>+	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX     0x1UL</div><div class='add'>+	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID     0x2UL</div><div class='add'>+	__le32	ext_stats_ctx_id;</div><div class='add'>+	__le16	schq_id;</div><div class='add'>+	__le16	unused_0;</div><div class='add'>+	__le32	reserved32;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* creq_modify_qp_resp (size:128b/16B) */</div><div class='hunk'>@@ -3075,6 +3085,17 @@ struct sq_psn_search_ext {</div><div class='ctx'> 	__le32	reserved32;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* sq_msn_search (size:64b/8B) */</div><div class='add'>+struct sq_msn_search {</div><div class='add'>+	__le64	start_idx_next_psn_start_psn;</div><div class='add'>+	#define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL</div><div class='add'>+	#define SQ_MSN_SEARCH_START_PSN_SFT 0</div><div class='add'>+	#define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL</div><div class='add'>+	#define SQ_MSN_SEARCH_NEXT_PSN_SFT  24</div><div class='add'>+	#define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL</div><div class='add'>+	#define SQ_MSN_SEARCH_START_IDX_SFT 48</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* sq_send (size:1024b/128B) */</div><div class='ctx'> struct sq_send {</div><div class='ctx'> 	u8	wqe_type;</div><div class='hunk'>@@ -3763,13 +3784,35 @@ struct cq_base {</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_RES_UD          (0x2UL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1  (0x3UL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_RES_UD_CFA      (0x4UL &lt;&lt; 1)</div><div class='add'>+	#define CQ_BASE_CQE_TYPE_REQ_V3             (0x8UL &lt;&lt; 1)</div><div class='add'>+	#define CQ_BASE_CQE_TYPE_RES_RC_V3          (0x9UL &lt;&lt; 1)</div><div class='add'>+	#define CQ_BASE_CQE_TYPE_RES_UD_V3          (0xaUL &lt;&lt; 1)</div><div class='add'>+	#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3  (0xbUL &lt;&lt; 1)</div><div class='add'>+	#define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3      (0xcUL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_NO_OP           (0xdUL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_TERMINAL        (0xeUL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_CUT_OFF         (0xfUL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_BASE_CQE_TYPE_LAST           CQ_BASE_CQE_TYPE_CUT_OFF</div><div class='ctx'> 	u8	status;</div><div class='add'>+	#define CQ_BASE_STATUS_OK                         0x0UL</div><div class='add'>+	#define CQ_BASE_STATUS_BAD_RESPONSE_ERR           0x1UL</div><div class='add'>+	#define CQ_BASE_STATUS_LOCAL_LENGTH_ERR           0x2UL</div><div class='add'>+	#define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR        0x3UL</div><div class='add'>+	#define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR     0x4UL</div><div class='add'>+	#define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR       0x5UL</div><div class='add'>+	#define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR         0x6UL</div><div class='add'>+	#define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR   0x7UL</div><div class='add'>+	#define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL</div><div class='add'>+	#define CQ_BASE_STATUS_REMOTE_ACCESS_ERR          0x9UL</div><div class='add'>+	#define CQ_BASE_STATUS_REMOTE_OPERATION_ERR       0xaUL</div><div class='add'>+	#define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR      0xbUL</div><div class='add'>+	#define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR    0xcUL</div><div class='add'>+	#define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR   0xdUL</div><div class='add'>+	#define CQ_BASE_STATUS_HW_FLUSH_ERR               0xeUL</div><div class='add'>+	#define CQ_BASE_STATUS_OVERFLOW_ERR               0xfUL</div><div class='add'>+	#define CQ_BASE_STATUS_LAST                      CQ_BASE_STATUS_OVERFLOW_ERR</div><div class='ctx'> 	__le16	reserved16;</div><div class='del'>-	__le32	reserved32;</div><div class='add'>+	__le32	opaque;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* cq_req (size:256b/32B) */</div><div class='hunk'>@@ -4384,6 +4427,8 @@ struct cq_cutoff {</div><div class='ctx'> 	#define CQ_CUTOFF_CQE_TYPE_SFT    1</div><div class='ctx'> 	#define CQ_CUTOFF_CQE_TYPE_CUT_OFF  (0xfUL &lt;&lt; 1)</div><div class='ctx'> 	#define CQ_CUTOFF_CQE_TYPE_LAST    CQ_CUTOFF_CQE_TYPE_CUT_OFF</div><div class='add'>+	#define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL</div><div class='add'>+	#define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5</div><div class='ctx'> 	u8	status;</div><div class='ctx'> 	#define CQ_CUTOFF_STATUS_OK 0x0UL</div><div class='ctx'> 	#define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK</div><div class='hunk'>@@ -4435,6 +4480,8 @@ struct nq_srq_event {</div><div class='ctx'> 	#define NQ_SRQ_EVENT_TYPE_SFT      0</div><div class='ctx'> 	#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT  0x32UL</div><div class='ctx'> 	#define NQ_SRQ_EVENT_TYPE_LAST      NQ_SRQ_EVENT_TYPE_SRQ_EVENT</div><div class='add'>+	#define NQ_SRQ_EVENT_TOGGLE_MASK   0xc0UL</div><div class='add'>+	#define NQ_SRQ_EVENT_TOGGLE_SFT    6</div><div class='ctx'> 	u8	event;</div><div class='ctx'> 	#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL</div><div class='ctx'> 	#define NQ_SRQ_EVENT_EVENT_LAST               NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa.h b/drivers/infiniband/hw/efa/efa.h<br/>index 7352a1f5d811..e2bdec32ae80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa.h</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _EFA_H_</div><div class='hunk'>@@ -80,9 +80,19 @@ struct efa_pd {</div><div class='ctx'> 	u16 pdn;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct efa_mr_interconnect_info {</div><div class='add'>+	u16 recv_ic_id;</div><div class='add'>+	u16 rdma_read_ic_id;</div><div class='add'>+	u16 rdma_recv_ic_id;</div><div class='add'>+	u8 recv_ic_id_valid : 1;</div><div class='add'>+	u8 rdma_read_ic_id_valid : 1;</div><div class='add'>+	u8 rdma_recv_ic_id_valid : 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct efa_mr {</div><div class='ctx'> 	struct ib_mr ibmr;</div><div class='ctx'> 	struct ib_umem *umem;</div><div class='add'>+	struct efa_mr_interconnect_info ic_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct efa_cq {</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa_admin_cmds_defs.h b/drivers/infiniband/hw/efa/efa_admin_cmds_defs.h<br/>index 9c65bd27bae0..7377c8a9f4d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_admin_cmds_defs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa_admin_cmds_defs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_admin_cmds_defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_admin_cmds_defs.h</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _EFA_ADMIN_CMDS_H_</div><div class='hunk'>@@ -415,6 +415,32 @@ struct efa_admin_reg_mr_resp {</div><div class='ctx'> 	 * memory region</div><div class='ctx'> 	 */</div><div class='ctx'> 	u32 r_key;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Mask indicating which fields have valid values</div><div class='add'>+	 * 0 : recv_ic_id</div><div class='add'>+	 * 1 : rdma_read_ic_id</div><div class='add'>+	 * 2 : rdma_recv_ic_id</div><div class='add'>+	 */</div><div class='add'>+	u8 validity;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Physical interconnect used by the device to reach the MR for receive</div><div class='add'>+	 * operation</div><div class='add'>+	 */</div><div class='add'>+	u8 recv_ic_id;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Physical interconnect used by the device to reach the MR for RDMA</div><div class='add'>+	 * read operation</div><div class='add'>+	 */</div><div class='add'>+	u8 rdma_read_ic_id;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Physical interconnect used by the device to reach the MR for RDMA</div><div class='add'>+	 * write receive</div><div class='add'>+	 */</div><div class='add'>+	u8 rdma_recv_ic_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct efa_admin_dereg_mr_cmd {</div><div class='hunk'>@@ -999,6 +1025,11 @@ struct efa_admin_host_info {</div><div class='ctx'> #define EFA_ADMIN_REG_MR_CMD_REMOTE_WRITE_ENABLE_MASK       BIT(1)</div><div class='ctx'> #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK        BIT(2)</div><div class='ctx'> </div><div class='add'>+/* reg_mr_resp */</div><div class='add'>+#define EFA_ADMIN_REG_MR_RESP_RECV_IC_ID_MASK               BIT(0)</div><div class='add'>+#define EFA_ADMIN_REG_MR_RESP_RDMA_READ_IC_ID_MASK          BIT(1)</div><div class='add'>+#define EFA_ADMIN_REG_MR_RESP_RDMA_RECV_IC_ID_MASK          BIT(2)</div><div class='add'>+</div><div class='ctx'> /* create_cq_cmd */</div><div class='ctx'> #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)</div><div class='ctx'> #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK                   BIT(6)</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa_com_cmd.c b/drivers/infiniband/hw/efa/efa_com_cmd.c<br/>index 576811885d59..d3398c7b0bd0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_com_cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa_com_cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_com_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_com_cmd.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "efa_com.h"</div><div class='hunk'>@@ -270,6 +270,15 @@ int efa_com_register_mr(struct efa_com_dev *edev,</div><div class='ctx'> </div><div class='ctx'> 	result-&gt;l_key = cmd_completion.l_key;</div><div class='ctx'> 	result-&gt;r_key = cmd_completion.r_key;</div><div class='add'>+	result-&gt;ic_info.recv_ic_id = cmd_completion.recv_ic_id;</div><div class='add'>+	result-&gt;ic_info.rdma_read_ic_id = cmd_completion.rdma_read_ic_id;</div><div class='add'>+	result-&gt;ic_info.rdma_recv_ic_id = cmd_completion.rdma_recv_ic_id;</div><div class='add'>+	result-&gt;ic_info.recv_ic_id_valid = EFA_GET(&amp;cmd_completion.validity,</div><div class='add'>+						   EFA_ADMIN_REG_MR_RESP_RECV_IC_ID);</div><div class='add'>+	result-&gt;ic_info.rdma_read_ic_id_valid = EFA_GET(&amp;cmd_completion.validity,</div><div class='add'>+							EFA_ADMIN_REG_MR_RESP_RDMA_READ_IC_ID);</div><div class='add'>+	result-&gt;ic_info.rdma_recv_ic_id_valid = EFA_GET(&amp;cmd_completion.validity,</div><div class='add'>+							EFA_ADMIN_REG_MR_RESP_RDMA_RECV_IC_ID);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa_com_cmd.h b/drivers/infiniband/hw/efa/efa_com_cmd.h<br/>index fc97f37bb39b..720a99ba0f7d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_com_cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa_com_cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_com_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_com_cmd.h</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _EFA_COM_CMD_H_</div><div class='hunk'>@@ -199,6 +199,15 @@ struct efa_com_reg_mr_params {</div><div class='ctx'> 	u8 indirect;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct efa_com_mr_interconnect_info {</div><div class='add'>+	u16 recv_ic_id;</div><div class='add'>+	u16 rdma_read_ic_id;</div><div class='add'>+	u16 rdma_recv_ic_id;</div><div class='add'>+	u8 recv_ic_id_valid : 1;</div><div class='add'>+	u8 rdma_read_ic_id_valid : 1;</div><div class='add'>+	u8 rdma_recv_ic_id_valid : 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct efa_com_reg_mr_result {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * To be used in conjunction with local buffers references in SQ and</div><div class='hunk'>@@ -210,6 +219,7 @@ struct efa_com_reg_mr_result {</div><div class='ctx'> 	 * accessed memory region</div><div class='ctx'> 	 */</div><div class='ctx'> 	u32 r_key;</div><div class='add'>+	struct efa_com_mr_interconnect_info ic_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct efa_com_dereg_mr_params {</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa_main.c b/drivers/infiniband/hw/efa/efa_main.c<br/>index 15ee92081118..7b1910a86216 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_main.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2022 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> #include &lt;linux/version.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;rdma/ib_user_verbs.h&gt;</div><div class='add'>+#include &lt;rdma/uverbs_ioctl.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "efa.h"</div><div class='ctx'> </div><div class='hunk'>@@ -36,6 +37,8 @@ MODULE_DEVICE_TABLE(pci, efa_pci_tbl);</div><div class='ctx'> 	(BIT(EFA_ADMIN_FATAL_ERROR) | BIT(EFA_ADMIN_WARNING) | \</div><div class='ctx'> 	 BIT(EFA_ADMIN_NOTIFICATION) | BIT(EFA_ADMIN_KEEP_ALIVE))</div><div class='ctx'> </div><div class='add'>+extern const struct uapi_definition efa_uapi_defs[];</div><div class='add'>+</div><div class='ctx'> /* This handler will called for unknown event group or unimplemented handlers */</div><div class='ctx'> static void unimplemented_aenq_handler(void *data,</div><div class='ctx'> 				       struct efa_admin_aenq_entry *aenq_e)</div><div class='hunk'>@@ -432,6 +435,8 @@ static int efa_ib_device_add(struct efa_dev *dev)</div><div class='ctx'> </div><div class='ctx'> 	ib_set_device_ops(&amp;dev-&gt;ibdev, &amp;efa_dev_ops);</div><div class='ctx'> </div><div class='add'>+	dev-&gt;ibdev.driver_def = efa_uapi_defs;</div><div class='add'>+</div><div class='ctx'> 	err = ib_register_device(&amp;dev-&gt;ibdev, "efa_%d", &amp;pdev-&gt;dev);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_destroy_eqs;</div><div class='head'>diff --git a/drivers/infiniband/hw/efa/efa_verbs.c b/drivers/infiniband/hw/efa/efa_verbs.c<br/>index 0f8ca99d0827..2f412db2edcd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/efa/efa_verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/efa/efa_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/efa/efa_verbs.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB</div><div class='ctx'> /*</div><div class='del'>- * Copyright 2018-2023 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-buf.h&gt;</div><div class='hunk'>@@ -13,6 +13,9 @@</div><div class='ctx'> #include &lt;rdma/ib_user_verbs.h&gt;</div><div class='ctx'> #include &lt;rdma/ib_verbs.h&gt;</div><div class='ctx'> #include &lt;rdma/uverbs_ioctl.h&gt;</div><div class='add'>+#define UVERBS_MODULE_NAME efa_ib</div><div class='add'>+#include &lt;rdma/uverbs_named_ioctl.h&gt;</div><div class='add'>+#include &lt;rdma/ib_user_ioctl_cmds.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "efa.h"</div><div class='ctx'> #include "efa_io_defs.h"</div><div class='hunk'>@@ -1653,6 +1656,12 @@ static int efa_register_mr(struct ib_pd *ibpd, struct efa_mr *mr, u64 start,</div><div class='ctx'> 	mr-&gt;ibmr.lkey = result.l_key;</div><div class='ctx'> 	mr-&gt;ibmr.rkey = result.r_key;</div><div class='ctx'> 	mr-&gt;ibmr.length = length;</div><div class='add'>+	mr-&gt;ic_info.recv_ic_id = result.ic_info.recv_ic_id;</div><div class='add'>+	mr-&gt;ic_info.rdma_read_ic_id = result.ic_info.rdma_read_ic_id;</div><div class='add'>+	mr-&gt;ic_info.rdma_recv_ic_id = result.ic_info.rdma_recv_ic_id;</div><div class='add'>+	mr-&gt;ic_info.recv_ic_id_valid = result.ic_info.recv_ic_id_valid;</div><div class='add'>+	mr-&gt;ic_info.rdma_read_ic_id_valid = result.ic_info.rdma_read_ic_id_valid;</div><div class='add'>+	mr-&gt;ic_info.rdma_recv_ic_id_valid = result.ic_info.rdma_recv_ic_id_valid;</div><div class='ctx'> 	ibdev_dbg(&amp;dev-&gt;ibdev, "Registered mr[%d]\n", mr-&gt;ibmr.lkey);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1735,6 +1744,39 @@ err_out:</div><div class='ctx'> 	return ERR_PTR(err);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int UVERBS_HANDLER(EFA_IB_METHOD_MR_QUERY)(struct uverbs_attr_bundle *attrs)</div><div class='add'>+{</div><div class='add'>+	struct ib_mr *ibmr = uverbs_attr_get_obj(attrs, EFA_IB_ATTR_QUERY_MR_HANDLE);</div><div class='add'>+	struct efa_mr *mr = to_emr(ibmr);</div><div class='add'>+	u16 ic_id_validity = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = uverbs_copy_to(attrs, EFA_IB_ATTR_QUERY_MR_RESP_RECV_IC_ID,</div><div class='add'>+			     &amp;mr-&gt;ic_info.recv_ic_id, sizeof(mr-&gt;ic_info.recv_ic_id));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = uverbs_copy_to(attrs, EFA_IB_ATTR_QUERY_MR_RESP_RDMA_READ_IC_ID,</div><div class='add'>+			     &amp;mr-&gt;ic_info.rdma_read_ic_id, sizeof(mr-&gt;ic_info.rdma_read_ic_id));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = uverbs_copy_to(attrs, EFA_IB_ATTR_QUERY_MR_RESP_RDMA_RECV_IC_ID,</div><div class='add'>+			     &amp;mr-&gt;ic_info.rdma_recv_ic_id, sizeof(mr-&gt;ic_info.rdma_recv_ic_id));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (mr-&gt;ic_info.recv_ic_id_valid)</div><div class='add'>+		ic_id_validity |= EFA_QUERY_MR_VALIDITY_RECV_IC_ID;</div><div class='add'>+	if (mr-&gt;ic_info.rdma_read_ic_id_valid)</div><div class='add'>+		ic_id_validity |= EFA_QUERY_MR_VALIDITY_RDMA_READ_IC_ID;</div><div class='add'>+	if (mr-&gt;ic_info.rdma_recv_ic_id_valid)</div><div class='add'>+		ic_id_validity |= EFA_QUERY_MR_VALIDITY_RDMA_RECV_IC_ID;</div><div class='add'>+</div><div class='add'>+	return uverbs_copy_to(attrs, EFA_IB_ATTR_QUERY_MR_RESP_IC_ID_VALIDITY,</div><div class='add'>+			      &amp;ic_id_validity, sizeof(ic_id_validity));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int efa_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)</div><div class='ctx'> {</div><div class='ctx'> 	struct efa_dev *dev = to_edev(ibmr-&gt;device);</div><div class='hunk'>@@ -2157,3 +2199,30 @@ enum rdma_link_layer efa_port_link_layer(struct ib_device *ibdev,</div><div class='ctx'> 	return IB_LINK_LAYER_UNSPECIFIED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+DECLARE_UVERBS_NAMED_METHOD(EFA_IB_METHOD_MR_QUERY,</div><div class='add'>+			    UVERBS_ATTR_IDR(EFA_IB_ATTR_QUERY_MR_HANDLE,</div><div class='add'>+					    UVERBS_OBJECT_MR,</div><div class='add'>+					    UVERBS_ACCESS_READ,</div><div class='add'>+					    UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(EFA_IB_ATTR_QUERY_MR_RESP_IC_ID_VALIDITY,</div><div class='add'>+						UVERBS_ATTR_TYPE(u16),</div><div class='add'>+						UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(EFA_IB_ATTR_QUERY_MR_RESP_RECV_IC_ID,</div><div class='add'>+						UVERBS_ATTR_TYPE(u16),</div><div class='add'>+						UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(EFA_IB_ATTR_QUERY_MR_RESP_RDMA_READ_IC_ID,</div><div class='add'>+						UVERBS_ATTR_TYPE(u16),</div><div class='add'>+						UA_MANDATORY),</div><div class='add'>+			    UVERBS_ATTR_PTR_OUT(EFA_IB_ATTR_QUERY_MR_RESP_RDMA_RECV_IC_ID,</div><div class='add'>+						UVERBS_ATTR_TYPE(u16),</div><div class='add'>+						UA_MANDATORY));</div><div class='add'>+</div><div class='add'>+ADD_UVERBS_METHODS(efa_mr,</div><div class='add'>+		   UVERBS_OBJECT_MR,</div><div class='add'>+		   &amp;UVERBS_METHOD(EFA_IB_METHOD_MR_QUERY));</div><div class='add'>+</div><div class='add'>+const struct uapi_definition efa_uapi_defs[] = {</div><div class='add'>+	UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR,</div><div class='add'>+				&amp;efa_mr),</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/infiniband/hw/erdma/erdma.h b/drivers/infiniband/hw/erdma/erdma.h<br/>index f190111840e9..5df401a30cb9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/erdma/erdma.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma.h</a></div><div class='hunk'>@@ -212,6 +212,8 @@ struct erdma_dev {</div><div class='ctx'> </div><div class='ctx'> 	atomic_t num_ctx;</div><div class='ctx'> 	struct list_head cep_list;</div><div class='add'>+</div><div class='add'>+	struct dma_pool *resp_pool;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline void *get_queue_entry(void *qbuf, u32 idx, u32 depth, u32 shift)</div><div class='head'>diff --git a/drivers/infiniband/hw/erdma/erdma_hw.h b/drivers/infiniband/hw/erdma/erdma_hw.h<br/>index 9d316fdc6f9a..3212a1222760 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/erdma/erdma_hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_hw.h</a></div><div class='hunk'>@@ -11,8 +11,6 @@</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='ctx'> /* PCIe device related definition. */</div><div class='del'>-#define PCI_VENDOR_ID_ALIBABA 0x1ded</div><div class='del'>-</div><div class='ctx'> #define ERDMA_PCI_WIDTH 64</div><div class='ctx'> #define ERDMA_FUNC_BAR 0</div><div class='ctx'> #define ERDMA_MISX_BAR 2</div><div class='hunk'>@@ -146,6 +144,7 @@ enum CMDQ_COMMON_OPCODE {</div><div class='ctx'> 	CMDQ_OPCODE_DESTROY_EQ = 1,</div><div class='ctx'> 	CMDQ_OPCODE_QUERY_FW_INFO = 2,</div><div class='ctx'> 	CMDQ_OPCODE_CONF_MTU = 3,</div><div class='add'>+	CMDQ_OPCODE_GET_STATS = 4,</div><div class='ctx'> 	CMDQ_OPCODE_CONF_DEVICE = 5,</div><div class='ctx'> 	CMDQ_OPCODE_ALLOC_DB = 8,</div><div class='ctx'> 	CMDQ_OPCODE_FREE_DB = 9,</div><div class='hunk'>@@ -357,6 +356,44 @@ struct erdma_cmdq_reflush_req {</div><div class='ctx'> 	u32 rq_pi;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define ERDMA_HW_RESP_SIZE 256</div><div class='add'>+</div><div class='add'>+struct erdma_cmdq_query_req {</div><div class='add'>+	u64 hdr;</div><div class='add'>+	u32 rsvd;</div><div class='add'>+	u32 index;</div><div class='add'>+</div><div class='add'>+	u64 target_addr;</div><div class='add'>+	u32 target_length;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ERDMA_HW_RESP_MAGIC 0x5566</div><div class='add'>+</div><div class='add'>+struct erdma_cmdq_query_resp_hdr {</div><div class='add'>+	u16 magic;</div><div class='add'>+	u8 ver;</div><div class='add'>+	u8 length;</div><div class='add'>+</div><div class='add'>+	u32 index;</div><div class='add'>+	u32 rsvd[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct erdma_cmdq_query_stats_resp {</div><div class='add'>+	struct erdma_cmdq_query_resp_hdr hdr;</div><div class='add'>+</div><div class='add'>+	u64 tx_req_cnt;</div><div class='add'>+	u64 tx_packets_cnt;</div><div class='add'>+	u64 tx_bytes_cnt;</div><div class='add'>+	u64 tx_drop_packets_cnt;</div><div class='add'>+	u64 tx_bps_meter_drop_packets_cnt;</div><div class='add'>+	u64 tx_pps_meter_drop_packets_cnt;</div><div class='add'>+	u64 rx_packets_cnt;</div><div class='add'>+	u64 rx_bytes_cnt;</div><div class='add'>+	u64 rx_drop_packets_cnt;</div><div class='add'>+	u64 rx_bps_meter_drop_packets_cnt;</div><div class='add'>+	u64 rx_pps_meter_drop_packets_cnt;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* cap qword 0 definition */</div><div class='ctx'> #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40)</div><div class='ctx'> #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24)</div><div class='head'>diff --git a/drivers/infiniband/hw/erdma/erdma_main.c b/drivers/infiniband/hw/erdma/erdma_main.c<br/>index 0880c79a978c..472939172f0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/erdma/erdma_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_main.c</a></div><div class='hunk'>@@ -172,14 +172,30 @@ static int erdma_device_init(struct erdma_dev *dev, struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	dev-&gt;resp_pool = dma_pool_create("erdma_resp_pool", &amp;pdev-&gt;dev,</div><div class='add'>+					 ERDMA_HW_RESP_SIZE, ERDMA_HW_RESP_SIZE,</div><div class='add'>+					 0);</div><div class='add'>+	if (!dev-&gt;resp_pool)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	ret = dma_set_mask_and_coherent(&amp;pdev-&gt;dev,</div><div class='ctx'> 					DMA_BIT_MASK(ERDMA_PCI_WIDTH));</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto destroy_pool;</div><div class='ctx'> </div><div class='ctx'> 	dma_set_max_seg_size(&amp;pdev-&gt;dev, UINT_MAX);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+destroy_pool:</div><div class='add'>+	dma_pool_destroy(dev-&gt;resp_pool);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void erdma_device_uninit(struct erdma_dev *dev)</div><div class='add'>+{</div><div class='add'>+	dma_pool_destroy(dev-&gt;resp_pool);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void erdma_hw_reset(struct erdma_dev *dev)</div><div class='hunk'>@@ -273,7 +289,7 @@ static int erdma_probe_dev(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	err = erdma_request_vectors(dev);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto err_iounmap_func_bar;</div><div class='add'>+		goto err_uninit_device;</div><div class='ctx'> </div><div class='ctx'> 	err = erdma_comm_irq_init(dev);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -314,6 +330,9 @@ err_uninit_comm_irq:</div><div class='ctx'> err_free_vectors:</div><div class='ctx'> 	pci_free_irq_vectors(dev-&gt;pdev);</div><div class='ctx'> </div><div class='add'>+err_uninit_device:</div><div class='add'>+	erdma_device_uninit(dev);</div><div class='add'>+</div><div class='ctx'> err_iounmap_func_bar:</div><div class='ctx'> 	devm_iounmap(&amp;pdev-&gt;dev, dev-&gt;func_bar);</div><div class='ctx'> </div><div class='hunk'>@@ -339,6 +358,7 @@ static void erdma_remove_dev(struct pci_dev *pdev)</div><div class='ctx'> 	erdma_aeq_destroy(dev);</div><div class='ctx'> 	erdma_comm_irq_uninit(dev);</div><div class='ctx'> 	pci_free_irq_vectors(dev-&gt;pdev);</div><div class='add'>+	erdma_device_uninit(dev);</div><div class='ctx'> </div><div class='ctx'> 	devm_iounmap(&amp;pdev-&gt;dev, dev-&gt;func_bar);</div><div class='ctx'> 	pci_release_selected_regions(pdev, ERDMA_BAR_MASK);</div><div class='hunk'>@@ -448,6 +468,7 @@ static const struct ib_device_ops erdma_device_ops = {</div><div class='ctx'> 	.driver_id = RDMA_DRIVER_ERDMA,</div><div class='ctx'> 	.uverbs_abi_ver = ERDMA_ABI_VERSION,</div><div class='ctx'> </div><div class='add'>+	.alloc_hw_port_stats = erdma_alloc_hw_port_stats,</div><div class='ctx'> 	.alloc_mr = erdma_ib_alloc_mr,</div><div class='ctx'> 	.alloc_pd = erdma_alloc_pd,</div><div class='ctx'> 	.alloc_ucontext = erdma_alloc_ucontext,</div><div class='hunk'>@@ -459,6 +480,7 @@ static const struct ib_device_ops erdma_device_ops = {</div><div class='ctx'> 	.destroy_cq = erdma_destroy_cq,</div><div class='ctx'> 	.destroy_qp = erdma_destroy_qp,</div><div class='ctx'> 	.get_dma_mr = erdma_get_dma_mr,</div><div class='add'>+	.get_hw_stats = erdma_get_hw_stats,</div><div class='ctx'> 	.get_port_immutable = erdma_get_port_immutable,</div><div class='ctx'> 	.iw_accept = erdma_accept,</div><div class='ctx'> 	.iw_add_ref = erdma_qp_get_ref,</div><div class='head'>diff --git a/drivers/infiniband/hw/erdma/erdma_verbs.c b/drivers/infiniband/hw/erdma/erdma_verbs.c<br/>index c317947563fb..23dfc01603f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/erdma/erdma_verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_verbs.c</a></div><div class='hunk'>@@ -1708,3 +1708,93 @@ void erdma_port_event(struct erdma_dev *dev, enum ib_event_type reason)</div><div class='ctx'> </div><div class='ctx'> 	ib_dispatch_event(&amp;event);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+enum counters {</div><div class='add'>+	ERDMA_STATS_TX_REQS_CNT,</div><div class='add'>+	ERDMA_STATS_TX_PACKETS_CNT,</div><div class='add'>+	ERDMA_STATS_TX_BYTES_CNT,</div><div class='add'>+	ERDMA_STATS_TX_DISABLE_DROP_CNT,</div><div class='add'>+	ERDMA_STATS_TX_BPS_METER_DROP_CNT,</div><div class='add'>+	ERDMA_STATS_TX_PPS_METER_DROP_CNT,</div><div class='add'>+</div><div class='add'>+	ERDMA_STATS_RX_PACKETS_CNT,</div><div class='add'>+	ERDMA_STATS_RX_BYTES_CNT,</div><div class='add'>+	ERDMA_STATS_RX_DISABLE_DROP_CNT,</div><div class='add'>+	ERDMA_STATS_RX_BPS_METER_DROP_CNT,</div><div class='add'>+	ERDMA_STATS_RX_PPS_METER_DROP_CNT,</div><div class='add'>+</div><div class='add'>+	ERDMA_STATS_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct rdma_stat_desc erdma_descs[] = {</div><div class='add'>+	[ERDMA_STATS_TX_REQS_CNT].name = "tx_reqs_cnt",</div><div class='add'>+	[ERDMA_STATS_TX_PACKETS_CNT].name = "tx_packets_cnt",</div><div class='add'>+	[ERDMA_STATS_TX_BYTES_CNT].name = "tx_bytes_cnt",</div><div class='add'>+	[ERDMA_STATS_TX_DISABLE_DROP_CNT].name = "tx_disable_drop_cnt",</div><div class='add'>+	[ERDMA_STATS_TX_BPS_METER_DROP_CNT].name = "tx_bps_limit_drop_cnt",</div><div class='add'>+	[ERDMA_STATS_TX_PPS_METER_DROP_CNT].name = "tx_pps_limit_drop_cnt",</div><div class='add'>+	[ERDMA_STATS_RX_PACKETS_CNT].name = "rx_packets_cnt",</div><div class='add'>+	[ERDMA_STATS_RX_BYTES_CNT].name = "rx_bytes_cnt",</div><div class='add'>+	[ERDMA_STATS_RX_DISABLE_DROP_CNT].name = "rx_disable_drop_cnt",</div><div class='add'>+	[ERDMA_STATS_RX_BPS_METER_DROP_CNT].name = "rx_bps_limit_drop_cnt",</div><div class='add'>+	[ERDMA_STATS_RX_PPS_METER_DROP_CNT].name = "rx_pps_limit_drop_cnt",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct rdma_hw_stats *erdma_alloc_hw_port_stats(struct ib_device *device,</div><div class='add'>+						u32 port_num)</div><div class='add'>+{</div><div class='add'>+	return rdma_alloc_hw_stats_struct(erdma_descs, ERDMA_STATS_MAX,</div><div class='add'>+					  RDMA_HW_STATS_DEFAULT_LIFESPAN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int erdma_query_hw_stats(struct erdma_dev *dev,</div><div class='add'>+				struct rdma_hw_stats *stats)</div><div class='add'>+{</div><div class='add'>+	struct erdma_cmdq_query_stats_resp *resp;</div><div class='add'>+	struct erdma_cmdq_query_req req;</div><div class='add'>+	dma_addr_t dma_addr;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	erdma_cmdq_build_reqhdr(&amp;req.hdr, CMDQ_SUBMOD_COMMON,</div><div class='add'>+				CMDQ_OPCODE_GET_STATS);</div><div class='add'>+</div><div class='add'>+	resp = dma_pool_zalloc(dev-&gt;resp_pool, GFP_KERNEL, &amp;dma_addr);</div><div class='add'>+	if (!resp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	req.target_addr = dma_addr;</div><div class='add'>+	req.target_length = ERDMA_HW_RESP_SIZE;</div><div class='add'>+</div><div class='add'>+	err = erdma_post_cmd_wait(&amp;dev-&gt;cmdq, &amp;req, sizeof(req), NULL, NULL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	if (resp-&gt;hdr.magic != ERDMA_HW_RESP_MAGIC) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;stats-&gt;value[0], &amp;resp-&gt;tx_req_cnt,</div><div class='add'>+	       sizeof(u64) * stats-&gt;num_counters);</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	dma_pool_free(dev-&gt;resp_pool, resp, dma_addr);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int erdma_get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,</div><div class='add'>+		       u32 port, int index)</div><div class='add'>+{</div><div class='add'>+	struct erdma_dev *dev = to_edev(ibdev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (port == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = erdma_query_hw_stats(dev, stats);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return stats-&gt;num_counters;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/infiniband/hw/erdma/erdma_verbs.h b/drivers/infiniband/hw/erdma/erdma_verbs.h<br/>index eb9c0f92fb6f..db6018529ccc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_verbs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/erdma/erdma_verbs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/erdma/erdma_verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/erdma/erdma_verbs.h</a></div><div class='hunk'>@@ -361,5 +361,9 @@ int erdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,</div><div class='ctx'> 		    unsigned int *sg_offset);</div><div class='ctx'> void erdma_port_event(struct erdma_dev *dev, enum ib_event_type reason);</div><div class='ctx'> void erdma_set_mtu(struct erdma_dev *dev, u32 mtu);</div><div class='add'>+struct rdma_hw_stats *erdma_alloc_hw_port_stats(struct ib_device *device,</div><div class='add'>+						u32 port_num);</div><div class='add'>+int erdma_get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,</div><div class='add'>+		       u32 port, int index);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/infiniband/hw/hfi1/user_exp_rcv.c b/drivers/infiniband/hw/hfi1/user_exp_rcv.c<br/>index 6419872f95cf..cf2d29098406 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hfi1/user_exp_rcv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hfi1/user_exp_rcv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hfi1/user_exp_rcv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hfi1/user_exp_rcv.c</a></div><div class='hunk'>@@ -491,8 +491,8 @@ int hfi1_user_exp_rcv_clear(struct hfi1_filedata *fd,</div><div class='ctx'> 	if (unlikely(tinfo-&gt;tidcnt &gt; fd-&gt;tid_used))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	tidinfo = memdup_user(u64_to_user_ptr(tinfo-&gt;tidlist),</div><div class='del'>-			      sizeof(tidinfo[0]) * tinfo-&gt;tidcnt);</div><div class='add'>+	tidinfo = memdup_array_user(u64_to_user_ptr(tinfo-&gt;tidlist),</div><div class='add'>+				    tinfo-&gt;tidcnt, sizeof(tidinfo[0]));</div><div class='ctx'> 	if (IS_ERR(tidinfo))</div><div class='ctx'> 		return PTR_ERR(tidinfo);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c<br/>index 6a4aa59c0cbc..b72625283fcf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hfi1/user_sdma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hfi1/user_sdma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hfi1/user_sdma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hfi1/user_sdma.c</a></div><div class='hunk'>@@ -494,8 +494,8 @@ int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,</div><div class='ctx'> 		 * equal to the pkt count. However, there is no way to</div><div class='ctx'> 		 * tell at this point.</div><div class='ctx'> 		 */</div><div class='del'>-		tmp = memdup_user(iovec[idx].iov_base,</div><div class='del'>-				  ntids * sizeof(*req-&gt;tids));</div><div class='add'>+		tmp = memdup_array_user(iovec[idx].iov_base,</div><div class='add'>+					ntids, sizeof(*req-&gt;tids));</div><div class='ctx'> 		if (IS_ERR(tmp)) {</div><div class='ctx'> 			ret = PTR_ERR(tmp);</div><div class='ctx'> 			SDMA_DBG(req, "Failed to copy %d TIDs (%d)",</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/Makefile b/drivers/infiniband/hw/hns/Makefile<br/>index a7d259238305..be1e1cdbcfa8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/Makefile</a></div><div class='hunk'>@@ -7,7 +7,8 @@ ccflags-y :=  -I $(srctree)/drivers/net/ethernet/hisilicon/hns3</div><div class='ctx'> </div><div class='ctx'> hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \</div><div class='ctx'> 	hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \</div><div class='del'>-	hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o</div><div class='add'>+	hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o \</div><div class='add'>+	hns_roce_debugfs.o</div><div class='ctx'> </div><div class='ctx'> ifdef CONFIG_INFINIBAND_HNS_HIP08</div><div class='ctx'> hns-roce-hw-v2-objs := hns_roce_hw_v2.o $(hns-roce-objs)</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_ah.c b/drivers/infiniband/hw/hns/hns_roce_ah.c<br/>index 3df032ddda18..b4209b6aed8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_ah.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_ah.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_ah.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_ah.c</a></div><div class='hunk'>@@ -57,6 +57,7 @@ int hns_roce_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr,</div><div class='ctx'> 	struct rdma_ah_attr *ah_attr = init_attr-&gt;ah_attr;</div><div class='ctx'> 	const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);</div><div class='ctx'> 	struct hns_roce_dev *hr_dev = to_hr_dev(ibah-&gt;device);</div><div class='add'>+	struct hns_roce_ib_create_ah_resp resp = {};</div><div class='ctx'> 	struct hns_roce_ah *ah = to_hr_ah(ibah);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	u32 max_sl;</div><div class='hunk'>@@ -92,11 +93,21 @@ int hns_roce_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr,</div><div class='ctx'> 		ret = rdma_read_gid_l2_fields(ah_attr-&gt;grh.sgid_attr,</div><div class='ctx'> 					      &amp;ah-&gt;av.vlan_id, NULL);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto err_out;</div><div class='ctx'> </div><div class='ctx'> 		ah-&gt;av.vlan_en = ah-&gt;av.vlan_id &lt; VLAN_N_VID;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (udata) {</div><div class='add'>+		memcpy(resp.dmac, ah_attr-&gt;roce.dmac, ETH_ALEN);</div><div class='add'>+		ret = ib_copy_to_udata(udata, &amp;resp,</div><div class='add'>+				       min(udata-&gt;outlen, sizeof(resp)));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_AH_CREATE_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_cmd.c b/drivers/infiniband/hw/hns/hns_roce_cmd.c<br/>index 864413607571..873e8a69a1b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_cmd.c</a></div><div class='hunk'>@@ -41,7 +41,15 @@</div><div class='ctx'> static int hns_roce_cmd_mbox_post_hw(struct hns_roce_dev *hr_dev,</div><div class='ctx'> 				     struct hns_roce_mbox_msg *mbox_msg)</div><div class='ctx'> {</div><div class='del'>-	return hr_dev-&gt;hw-&gt;post_mbox(hr_dev, mbox_msg);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = hr_dev-&gt;hw-&gt;post_mbox(hr_dev, mbox_msg);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MBX_POSTED_CNT]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* this should be called with "poll_sem" */</div><div class='hunk'>@@ -58,7 +66,13 @@ static int __hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return hr_dev-&gt;hw-&gt;poll_mbox_done(hr_dev);</div><div class='add'>+	ret = hr_dev-&gt;hw-&gt;poll_mbox_done(hr_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MBX_POLLED_CNT]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hns_roce_cmd_mbox_poll(struct hns_roce_dev *hr_dev,</div><div class='hunk'>@@ -89,6 +103,7 @@ void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,</div><div class='ctx'> 	context-&gt;result = (status == HNS_ROCE_CMD_SUCCESS) ? 0 : (-EIO);</div><div class='ctx'> 	context-&gt;out_param = out_param;</div><div class='ctx'> 	complete(&amp;context-&gt;done);</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MBX_EVENT_CNT]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev,</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c<br/>index 736dc2f993b4..1b6d16af8c12 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_cq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_cq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_cq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_cq.c</a></div><div class='hunk'>@@ -363,29 +363,31 @@ int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	struct hns_roce_ib_create_cq ucmd = {};</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (attr-&gt;flags)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='add'>+	if (attr-&gt;flags) {</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = verify_cq_create_attr(hr_dev, attr);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	if (udata) {</div><div class='ctx'> 		ret = get_cq_ucmd(hr_cq, udata, &amp;ucmd);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto err_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	set_cq_param(hr_cq, attr-&gt;cqe, attr-&gt;comp_vector, &amp;ucmd);</div><div class='ctx'> </div><div class='ctx'> 	ret = set_cqe_size(hr_cq, udata, &amp;ucmd);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	ret = alloc_cq_buf(hr_dev, hr_cq, udata, ucmd.buf_addr);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ibdev_err(ibdev, "failed to alloc CQ buf, ret = %d.\n", ret);</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = alloc_cq_db(hr_dev, hr_cq, udata, ucmd.db_addr, &amp;resp);</div><div class='hunk'>@@ -430,6 +432,9 @@ err_cq_db:</div><div class='ctx'> 	free_cq_db(hr_dev, hr_cq, udata);</div><div class='ctx'> err_cq_buf:</div><div class='ctx'> 	free_cq_buf(hr_dev, hr_cq);</div><div class='add'>+err_out:</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_CQ_CREATE_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_debugfs.c b/drivers/infiniband/hw/hns/hns_roce_debugfs.c<br/>new file mode 100644<br/>index 000000000000..e8febb40f645<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,110 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0+</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Hisilicon Limited.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+</div><div class='add'>+#include "hns_roce_device.h"</div><div class='add'>+</div><div class='add'>+static struct dentry *hns_roce_dbgfs_root;</div><div class='add'>+</div><div class='add'>+static int hns_debugfs_seqfile_open(struct inode *inode, struct file *f)</div><div class='add'>+{</div><div class='add'>+	struct hns_debugfs_seqfile *seqfile = inode-&gt;i_private;</div><div class='add'>+</div><div class='add'>+	return single_open(f, seqfile-&gt;read, seqfile-&gt;data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations hns_debugfs_seqfile_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = hns_debugfs_seqfile_open,</div><div class='add'>+	.release = single_release,</div><div class='add'>+	.read = seq_read,</div><div class='add'>+	.llseek = seq_lseek</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void init_debugfs_seqfile(struct hns_debugfs_seqfile *seq,</div><div class='add'>+				 const char *name, struct dentry *parent,</div><div class='add'>+				 int (*read_fn)(struct seq_file *, void *),</div><div class='add'>+				 void *data)</div><div class='add'>+{</div><div class='add'>+	debugfs_create_file(name, 0400, parent, seq, &amp;hns_debugfs_seqfile_fops);</div><div class='add'>+</div><div class='add'>+	seq-&gt;read = read_fn;</div><div class='add'>+	seq-&gt;data = data;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char * const sw_stat_info[] = {</div><div class='add'>+	[HNS_ROCE_DFX_AEQE_CNT] = "aeqe",</div><div class='add'>+	[HNS_ROCE_DFX_CEQE_CNT] = "ceqe",</div><div class='add'>+	[HNS_ROCE_DFX_CMDS_CNT] = "cmds",</div><div class='add'>+	[HNS_ROCE_DFX_CMDS_ERR_CNT] = "cmds_err",</div><div class='add'>+	[HNS_ROCE_DFX_MBX_POSTED_CNT] = "posted_mbx",</div><div class='add'>+	[HNS_ROCE_DFX_MBX_POLLED_CNT] = "polled_mbx",</div><div class='add'>+	[HNS_ROCE_DFX_MBX_EVENT_CNT] = "mbx_event",</div><div class='add'>+	[HNS_ROCE_DFX_QP_CREATE_ERR_CNT] = "qp_create_err",</div><div class='add'>+	[HNS_ROCE_DFX_QP_MODIFY_ERR_CNT] = "qp_modify_err",</div><div class='add'>+	[HNS_ROCE_DFX_CQ_CREATE_ERR_CNT] = "cq_create_err",</div><div class='add'>+	[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT] = "cq_modify_err",</div><div class='add'>+	[HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT] = "srq_create_err",</div><div class='add'>+	[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT] = "srq_modify_err",</div><div class='add'>+	[HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT] = "xrcd_alloc_err",</div><div class='add'>+	[HNS_ROCE_DFX_MR_REG_ERR_CNT] = "mr_reg_err",</div><div class='add'>+	[HNS_ROCE_DFX_MR_REREG_ERR_CNT] = "mr_rereg_err",</div><div class='add'>+	[HNS_ROCE_DFX_AH_CREATE_ERR_CNT] = "ah_create_err",</div><div class='add'>+	[HNS_ROCE_DFX_MMAP_ERR_CNT] = "mmap_err",</div><div class='add'>+	[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT] = "uctx_alloc_err",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sw_stat_debugfs_show(struct seq_file *file, void *offset)</div><div class='add'>+{</div><div class='add'>+	struct hns_roce_dev *hr_dev = file-&gt;private;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; HNS_ROCE_DFX_CNT_TOTAL; i++)</div><div class='add'>+		seq_printf(file, "%-20s --- %lld\n", sw_stat_info[i],</div><div class='add'>+			   atomic64_read(&amp;hr_dev-&gt;dfx_cnt[i]));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void create_sw_stat_debugfs(struct hns_roce_dev *hr_dev,</div><div class='add'>+				   struct dentry *parent)</div><div class='add'>+{</div><div class='add'>+	struct hns_sw_stat_debugfs *dbgfs = &amp;hr_dev-&gt;dbgfs.sw_stat_root;</div><div class='add'>+</div><div class='add'>+	dbgfs-&gt;root = debugfs_create_dir("sw_stat", parent);</div><div class='add'>+</div><div class='add'>+	init_debugfs_seqfile(&amp;dbgfs-&gt;sw_stat, "sw_stat", dbgfs-&gt;root,</div><div class='add'>+			     sw_stat_debugfs_show, hr_dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* debugfs for device */</div><div class='add'>+void hns_roce_register_debugfs(struct hns_roce_dev *hr_dev)</div><div class='add'>+{</div><div class='add'>+	struct hns_roce_dev_debugfs *dbgfs = &amp;hr_dev-&gt;dbgfs;</div><div class='add'>+</div><div class='add'>+	dbgfs-&gt;root = debugfs_create_dir(dev_name(&amp;hr_dev-&gt;ib_dev.dev),</div><div class='add'>+					 hns_roce_dbgfs_root);</div><div class='add'>+</div><div class='add'>+	create_sw_stat_debugfs(hr_dev, dbgfs-&gt;root);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hns_roce_unregister_debugfs(struct hns_roce_dev *hr_dev)</div><div class='add'>+{</div><div class='add'>+	debugfs_remove_recursive(hr_dev-&gt;dbgfs.root);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* debugfs for hns module */</div><div class='add'>+void hns_roce_init_debugfs(void)</div><div class='add'>+{</div><div class='add'>+	hns_roce_dbgfs_root = debugfs_create_dir("hns_roce", NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void hns_roce_cleanup_debugfs(void)</div><div class='add'>+{</div><div class='add'>+	debugfs_remove_recursive(hns_roce_dbgfs_root);</div><div class='add'>+	hns_roce_dbgfs_root = NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_debugfs.h b/drivers/infiniband/hw/hns/hns_roce_debugfs.h<br/>new file mode 100644<br/>index 000000000000..98e87bd3161e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_debugfs.h</a></div><div class='hunk'>@@ -0,0 +1,33 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0+ */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Hisilicon Limited.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __HNS_ROCE_DEBUGFS_H</div><div class='add'>+#define __HNS_ROCE_DEBUGFS_H</div><div class='add'>+</div><div class='add'>+/* debugfs seqfile */</div><div class='add'>+struct hns_debugfs_seqfile {</div><div class='add'>+	int (*read)(struct seq_file *seq, void *data);</div><div class='add'>+	void *data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hns_sw_stat_debugfs {</div><div class='add'>+	struct dentry *root;</div><div class='add'>+	struct hns_debugfs_seqfile sw_stat;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Debugfs for device */</div><div class='add'>+struct hns_roce_dev_debugfs {</div><div class='add'>+	struct dentry *root;</div><div class='add'>+	struct hns_sw_stat_debugfs sw_stat_root;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct hns_roce_dev;</div><div class='add'>+</div><div class='add'>+void hns_roce_init_debugfs(void);</div><div class='add'>+void hns_roce_cleanup_debugfs(void);</div><div class='add'>+void hns_roce_register_debugfs(struct hns_roce_dev *hr_dev);</div><div class='add'>+void hns_roce_unregister_debugfs(struct hns_roce_dev *hr_dev);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h<br/>index 1627f3b0ef28..b1fce5ddf631 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_device.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_device.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_device.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_device.h</a></div><div class='hunk'>@@ -35,6 +35,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;rdma/ib_verbs.h&gt;</div><div class='ctx'> #include &lt;rdma/hns-abi.h&gt;</div><div class='add'>+#include "hns_roce_debugfs.h"</div><div class='ctx'> </div><div class='ctx'> #define PCI_REVISION_ID_HIP08			0x21</div><div class='ctx'> #define PCI_REVISION_ID_HIP09			0x30</div><div class='hunk'>@@ -869,6 +870,29 @@ enum hns_roce_hw_pkt_stat_index {</div><div class='ctx'> 	HNS_ROCE_HW_CNT_TOTAL</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum hns_roce_sw_dfx_stat_index {</div><div class='add'>+	HNS_ROCE_DFX_AEQE_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CEQE_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CMDS_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CMDS_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MBX_POSTED_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MBX_POLLED_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MBX_EVENT_CNT,</div><div class='add'>+	HNS_ROCE_DFX_QP_CREATE_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_QP_MODIFY_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CQ_CREATE_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MR_REG_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MR_REREG_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_AH_CREATE_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_MMAP_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT,</div><div class='add'>+	HNS_ROCE_DFX_CNT_TOTAL</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct hns_roce_hw {</div><div class='ctx'> 	int (*cmq_init)(struct hns_roce_dev *hr_dev);</div><div class='ctx'> 	void (*cmq_exit)(struct hns_roce_dev *hr_dev);</div><div class='hunk'>@@ -979,6 +1003,8 @@ struct hns_roce_dev {</div><div class='ctx'> 	u32 is_vf;</div><div class='ctx'> 	u32 cong_algo_tmpl_id;</div><div class='ctx'> 	u64 dwqe_page;</div><div class='add'>+	struct hns_roce_dev_debugfs dbgfs;</div><div class='add'>+	atomic64_t *dfx_cnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c<br/>index 0cd2612a4987..8206daea6767 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_hw_v2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_hw_v2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_hw_v2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_hw_v2.c</a></div><div class='hunk'>@@ -1297,6 +1297,8 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,</div><div class='ctx'> 	/* Write to hardware */</div><div class='ctx'> 	roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq-&gt;head);</div><div class='ctx'> </div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);</div><div class='add'>+</div><div class='ctx'> 	do {</div><div class='ctx'> 		if (hns_roce_cmq_csq_done(hr_dev))</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1334,6 +1336,9 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock_bh(&amp;csq-&gt;lock);</div><div class='ctx'> </div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2055,6 +2060,7 @@ static void set_hem_page_size(struct hns_roce_dev *hr_dev)</div><div class='ctx'> /* Apply all loaded caps before setting to hardware */</div><div class='ctx'> static void apply_func_caps(struct hns_roce_dev *hr_dev)</div><div class='ctx'> {</div><div class='add'>+#define MAX_GID_TBL_LEN 256</div><div class='ctx'> 	struct hns_roce_caps *caps = &amp;hr_dev-&gt;caps;</div><div class='ctx'> 	struct hns_roce_v2_priv *priv = hr_dev-&gt;priv;</div><div class='ctx'> </div><div class='hunk'>@@ -2090,8 +2096,14 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev)</div><div class='ctx'> 		caps-&gt;gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ;</div><div class='ctx'> </div><div class='ctx'> 		caps-&gt;gmv_hop_num = HNS_ROCE_HOP_NUM_0;</div><div class='del'>-		caps-&gt;gid_table_len[0] = caps-&gt;gmv_bt_num *</div><div class='del'>-					(HNS_HW_PAGE_SIZE / caps-&gt;gmv_entry_sz);</div><div class='add'>+</div><div class='add'>+		/* It's meaningless to support excessively large gid_table_len,</div><div class='add'>+		 * as the type of sgid_index in kernel struct ib_global_route</div><div class='add'>+		 * and userspace struct ibv_global_route are u8/uint8_t (0-255).</div><div class='add'>+		 */</div><div class='add'>+		caps-&gt;gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN,</div><div class='add'>+					 caps-&gt;gmv_bt_num *</div><div class='add'>+					 (HNS_HW_PAGE_SIZE / caps-&gt;gmv_entry_sz));</div><div class='ctx'> </div><div class='ctx'> 		caps-&gt;gmv_entry_num = caps-&gt;gmv_bt_num * (PAGE_SIZE /</div><div class='ctx'> 							  caps-&gt;gmv_entry_sz);</div><div class='hunk'>@@ -2698,6 +2710,10 @@ static int free_mr_alloc_res(struct hns_roce_dev *hr_dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> create_failed_qp:</div><div class='add'>+	for (i--; i &gt;= 0; i--) {</div><div class='add'>+		hns_roce_v2_destroy_qp(&amp;free_mr-&gt;rsv_qp[i]-&gt;ibqp, NULL);</div><div class='add'>+		kfree(free_mr-&gt;rsv_qp[i]);</div><div class='add'>+	}</div><div class='ctx'> 	hns_roce_destroy_cq(cq, NULL);</div><div class='ctx'> 	kfree(cq);</div><div class='ctx'> </div><div class='hunk'>@@ -4760,10 +4776,15 @@ static int check_cong_type(struct ib_qp *ibqp,</div><div class='ctx'> 		cong_alg-&gt;wnd_mode_sel = WND_LIMIT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		ibdev_err(&amp;hr_dev-&gt;ib_dev,</div><div class='del'>-			  "error type(%u) for congestion selection.\n",</div><div class='del'>-			  hr_dev-&gt;caps.cong_type);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		ibdev_warn(&amp;hr_dev-&gt;ib_dev,</div><div class='add'>+			   "invalid type(%u) for congestion selection.\n",</div><div class='add'>+			   hr_dev-&gt;caps.cong_type);</div><div class='add'>+		hr_dev-&gt;caps.cong_type = CONG_TYPE_DCQCN;</div><div class='add'>+		cong_alg-&gt;alg_sel = CONG_DCQCN;</div><div class='add'>+		cong_alg-&gt;alg_sub_sel = UNSUPPORT_CONG_LEVEL;</div><div class='add'>+		cong_alg-&gt;dip_vld = DIP_INVALID;</div><div class='add'>+		cong_alg-&gt;wnd_mode_sel = WND_LIMIT;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -5662,19 +5683,25 @@ static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,</div><div class='ctx'> 	struct hns_roce_srq_context *srq_context;</div><div class='ctx'> 	struct hns_roce_srq_context *srqc_mask;</div><div class='ctx'> 	struct hns_roce_cmd_mailbox *mailbox;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Resizing SRQs is not supported yet */</div><div class='del'>-	if (srq_attr_mask &amp; IB_SRQ_MAX_WR)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	if (srq_attr_mask &amp; IB_SRQ_MAX_WR) {</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (srq_attr_mask &amp; IB_SRQ_LIMIT) {</div><div class='del'>-		if (srq_attr-&gt;srq_limit &gt; srq-&gt;wqe_cnt)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		if (srq_attr-&gt;srq_limit &gt; srq-&gt;wqe_cnt) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);</div><div class='del'>-		if (IS_ERR(mailbox))</div><div class='del'>-			return PTR_ERR(mailbox);</div><div class='add'>+		if (IS_ERR(mailbox)) {</div><div class='add'>+			ret = PTR_ERR(mailbox);</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		srq_context = mailbox-&gt;buf;</div><div class='ctx'> 		srqc_mask = (struct hns_roce_srq_context *)mailbox-&gt;buf + 1;</div><div class='hunk'>@@ -5687,15 +5714,17 @@ static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,</div><div class='ctx'> 		ret = hns_roce_cmd_mbox(hr_dev, mailbox-&gt;dma, 0,</div><div class='ctx'> 					HNS_ROCE_CMD_MODIFY_SRQC, srq-&gt;srqn);</div><div class='ctx'> 		hns_roce_free_cmd_mailbox(hr_dev, mailbox);</div><div class='del'>-		if (ret) {</div><div class='add'>+		if (ret)</div><div class='ctx'> 			ibdev_err(&amp;hr_dev-&gt;ib_dev,</div><div class='ctx'> 				  "failed to handle cmd of modifying SRQ, ret = %d.\n",</div><div class='ctx'> 				  ret);</div><div class='del'>-			return ret;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+out:</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)</div><div class='hunk'>@@ -5739,8 +5768,9 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);</div><div class='del'>-	if (IS_ERR(mailbox))</div><div class='del'>-		return PTR_ERR(mailbox);</div><div class='add'>+	ret = PTR_ERR_OR_ZERO(mailbox);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	cq_context = mailbox-&gt;buf;</div><div class='ctx'> 	cqc_mask = (struct hns_roce_v2_cq_context *)mailbox-&gt;buf + 1;</div><div class='hunk'>@@ -5770,6 +5800,10 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)</div><div class='ctx'> 			  "failed to process cmd when modifying CQ, ret = %d.\n",</div><div class='ctx'> 			  ret);</div><div class='ctx'> </div><div class='add'>+err_out:</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6009,6 +6043,8 @@ static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,</div><div class='ctx'> 		++eq-&gt;cons_index;</div><div class='ctx'> 		aeqe_found = IRQ_HANDLED;</div><div class='ctx'> </div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]);</div><div class='add'>+</div><div class='ctx'> 		hns_roce_v2_init_irq_work(hr_dev, eq, queue_num);</div><div class='ctx'> </div><div class='ctx'> 		aeqe = next_aeqe_sw_v2(eq);</div><div class='hunk'>@@ -6050,6 +6086,7 @@ static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,</div><div class='ctx'> </div><div class='ctx'> 		++eq-&gt;cons_index;</div><div class='ctx'> 		ceqe_found = IRQ_HANDLED;</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]);</div><div class='ctx'> </div><div class='ctx'> 		ceqe = next_ceqe_sw_v2(eq);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -6452,15 +6489,16 @@ static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,</div><div class='ctx'> 	/* irq contains: abnormal + AEQ + CEQ */</div><div class='ctx'> 	for (j = 0; j &lt; other_num; j++)</div><div class='ctx'> 		snprintf((char *)hr_dev-&gt;irq_names[j], HNS_ROCE_INT_NAME_LEN,</div><div class='del'>-			 "hns-abn-%d", j);</div><div class='add'>+			 "hns-%s-abn-%d", pci_name(hr_dev-&gt;pci_dev), j);</div><div class='ctx'> </div><div class='ctx'> 	for (j = other_num; j &lt; (other_num + aeq_num); j++)</div><div class='ctx'> 		snprintf((char *)hr_dev-&gt;irq_names[j], HNS_ROCE_INT_NAME_LEN,</div><div class='del'>-			 "hns-aeq-%d", j - other_num);</div><div class='add'>+			 "hns-%s-aeq-%d", pci_name(hr_dev-&gt;pci_dev), j - other_num);</div><div class='ctx'> </div><div class='ctx'> 	for (j = (other_num + aeq_num); j &lt; irq_num; j++)</div><div class='ctx'> 		snprintf((char *)hr_dev-&gt;irq_names[j], HNS_ROCE_INT_NAME_LEN,</div><div class='del'>-			 "hns-ceq-%d", j - other_num - aeq_num);</div><div class='add'>+			 "hns-%s-ceq-%d", pci_name(hr_dev-&gt;pci_dev),</div><div class='add'>+			 j - other_num - aeq_num);</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; irq_num; j++) {</div><div class='ctx'> 		if (j &lt; other_num)</div><div class='hunk'>@@ -6958,12 +6996,14 @@ static struct hnae3_client hns_roce_hw_v2_client = {</div><div class='ctx'> </div><div class='ctx'> static int __init hns_roce_hw_v2_init(void)</div><div class='ctx'> {</div><div class='add'>+	hns_roce_init_debugfs();</div><div class='ctx'> 	return hnae3_register_client(&amp;hns_roce_hw_v2_client);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __exit hns_roce_hw_v2_exit(void)</div><div class='ctx'> {</div><div class='ctx'> 	hnae3_unregister_client(&amp;hns_roce_hw_v2_client);</div><div class='add'>+	hns_roce_cleanup_debugfs();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> module_init(hns_roce_hw_v2_init);</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c<br/>index a4a10a4e1aab..b55fe6911f9f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_main.c</a></div><div class='hunk'>@@ -361,10 +361,10 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,</div><div class='ctx'> 	struct hns_roce_dev *hr_dev = to_hr_dev(uctx-&gt;device);</div><div class='ctx'> 	struct hns_roce_ib_alloc_ucontext_resp resp = {};</div><div class='ctx'> 	struct hns_roce_ib_alloc_ucontext ucmd = {};</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = -EAGAIN;</div><div class='ctx'> </div><div class='ctx'> 	if (!hr_dev-&gt;active)</div><div class='del'>-		return -EAGAIN;</div><div class='add'>+		goto error_out;</div><div class='ctx'> </div><div class='ctx'> 	resp.qp_tab_size = hr_dev-&gt;caps.num_qps;</div><div class='ctx'> 	resp.srq_tab_size = hr_dev-&gt;caps.num_srqs;</div><div class='hunk'>@@ -372,7 +372,7 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,</div><div class='ctx'> 	ret = ib_copy_from_udata(&amp;ucmd, udata,</div><div class='ctx'> 				 min(udata-&gt;inlen, sizeof(ucmd)));</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto error_out;</div><div class='ctx'> </div><div class='ctx'> 	if (hr_dev-&gt;pci_dev-&gt;revision &gt;= PCI_REVISION_ID_HIP09)</div><div class='ctx'> 		context-&gt;config = ucmd.config &amp; HNS_ROCE_EXSGE_FLAGS;</div><div class='hunk'>@@ -396,7 +396,7 @@ static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,</div><div class='ctx'> </div><div class='ctx'> 	ret = hns_roce_uar_alloc(hr_dev, &amp;context-&gt;uar);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto error_fail_uar_alloc;</div><div class='add'>+		goto error_out;</div><div class='ctx'> </div><div class='ctx'> 	ret = hns_roce_alloc_uar_entry(uctx);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -423,7 +423,9 @@ error_fail_copy_to_udata:</div><div class='ctx'> error_fail_uar_entry:</div><div class='ctx'> 	ida_free(&amp;hr_dev-&gt;uar_ida.ida, (int)context-&gt;uar.logic_idx);</div><div class='ctx'> </div><div class='del'>-error_fail_uar_alloc:</div><div class='add'>+error_out:</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -439,6 +441,7 @@ static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)</div><div class='ctx'> </div><div class='ctx'> static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)</div><div class='ctx'> {</div><div class='add'>+	struct hns_roce_dev *hr_dev = to_hr_dev(uctx-&gt;device);</div><div class='ctx'> 	struct rdma_user_mmap_entry *rdma_entry;</div><div class='ctx'> 	struct hns_user_mmap_entry *entry;</div><div class='ctx'> 	phys_addr_t pfn;</div><div class='hunk'>@@ -446,8 +449,10 @@ static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma-&gt;vm_pgoff);</div><div class='del'>-	if (!rdma_entry)</div><div class='add'>+	if (!rdma_entry) {</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	entry = to_hns_mmap(rdma_entry);</div><div class='ctx'> 	pfn = entry-&gt;address &gt;&gt; PAGE_SHIFT;</div><div class='hunk'>@@ -467,6 +472,9 @@ static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	rdma_user_mmap_entry_put(rdma_entry);</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1009,6 +1017,21 @@ void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;hr_dev-&gt;qp_list_lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int hns_roce_alloc_dfx_cnt(struct hns_roce_dev *hr_dev)</div><div class='add'>+{</div><div class='add'>+	hr_dev-&gt;dfx_cnt = kvcalloc(HNS_ROCE_DFX_CNT_TOTAL, sizeof(atomic64_t),</div><div class='add'>+				   GFP_KERNEL);</div><div class='add'>+	if (!hr_dev-&gt;dfx_cnt)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void hns_roce_dealloc_dfx_cnt(struct hns_roce_dev *hr_dev)</div><div class='add'>+{</div><div class='add'>+	kvfree(hr_dev-&gt;dfx_cnt);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int hns_roce_init(struct hns_roce_dev *hr_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = hr_dev-&gt;dev;</div><div class='hunk'>@@ -1016,11 +1039,15 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)</div><div class='ctx'> </div><div class='ctx'> 	hr_dev-&gt;is_reset = false;</div><div class='ctx'> </div><div class='add'>+	ret = hns_roce_alloc_dfx_cnt(hr_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	if (hr_dev-&gt;hw-&gt;cmq_init) {</div><div class='ctx'> 		ret = hr_dev-&gt;hw-&gt;cmq_init(hr_dev);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "init RoCE Command Queue failed!\n");</div><div class='del'>-			return ret;</div><div class='add'>+			goto error_failed_alloc_dfx_cnt;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1079,6 +1106,8 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error_failed_register_device;</div><div class='ctx'> </div><div class='add'>+	hns_roce_register_debugfs(hr_dev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_failed_register_device:</div><div class='hunk'>@@ -1103,11 +1132,15 @@ error_failed_cmd_init:</div><div class='ctx'> 	if (hr_dev-&gt;hw-&gt;cmq_exit)</div><div class='ctx'> 		hr_dev-&gt;hw-&gt;cmq_exit(hr_dev);</div><div class='ctx'> </div><div class='add'>+error_failed_alloc_dfx_cnt:</div><div class='add'>+	hns_roce_dealloc_dfx_cnt(hr_dev);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void hns_roce_exit(struct hns_roce_dev *hr_dev)</div><div class='ctx'> {</div><div class='add'>+	hns_roce_unregister_debugfs(hr_dev);</div><div class='ctx'> 	hns_roce_unregister_device(hr_dev);</div><div class='ctx'> </div><div class='ctx'> 	if (hr_dev-&gt;hw-&gt;hw_exit)</div><div class='hunk'>@@ -1122,6 +1155,7 @@ void hns_roce_exit(struct hns_roce_dev *hr_dev)</div><div class='ctx'> 	hns_roce_cmd_cleanup(hr_dev);</div><div class='ctx'> 	if (hr_dev-&gt;hw-&gt;cmq_exit)</div><div class='ctx'> 		hr_dev-&gt;hw-&gt;cmq_exit(hr_dev);</div><div class='add'>+	hns_roce_dealloc_dfx_cnt(hr_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> MODULE_LICENSE("Dual BSD/GPL");</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c<br/>index 14376490ac22..91cd580480fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_mr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_mr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_mr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_mr.c</a></div><div class='hunk'>@@ -228,8 +228,10 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	mr = kzalloc(sizeof(*mr), GFP_KERNEL);</div><div class='del'>-	if (!mr)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='add'>+	if (!mr) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mr-&gt;iova = virt_addr;</div><div class='ctx'> 	mr-&gt;size = length;</div><div class='hunk'>@@ -259,6 +261,9 @@ err_alloc_key:</div><div class='ctx'> 	free_mr_key(hr_dev, mr);</div><div class='ctx'> err_alloc_mr:</div><div class='ctx'> 	kfree(mr);</div><div class='add'>+err_out:</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MR_REG_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -274,12 +279,15 @@ struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start,</div><div class='ctx'> 	unsigned long mtpt_idx;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!mr-&gt;enabled)</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='add'>+	if (!mr-&gt;enabled) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);</div><div class='del'>-	if (IS_ERR(mailbox))</div><div class='del'>-		return ERR_CAST(mailbox);</div><div class='add'>+	ret = PTR_ERR_OR_ZERO(mailbox);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	mtpt_idx = key_to_hw_index(mr-&gt;key) &amp; (hr_dev-&gt;caps.num_mtpts - 1);</div><div class='ctx'> </div><div class='hunk'>@@ -331,8 +339,12 @@ struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start,</div><div class='ctx'> free_cmd_mbox:</div><div class='ctx'> 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);</div><div class='ctx'> </div><div class='del'>-	if (ret)</div><div class='add'>+err_out:</div><div class='add'>+	if (ret) {</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_MR_REREG_ERR_CNT]);</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -674,7 +686,7 @@ static int mtr_alloc_bufs(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,</div><div class='ctx'> 		mtr-&gt;kmem = NULL;</div><div class='ctx'> 		mtr-&gt;umem = ib_umem_get(ibdev, user_addr, total_size,</div><div class='ctx'> 					buf_attr-&gt;user_access);</div><div class='del'>-		if (IS_ERR_OR_NULL(mtr-&gt;umem)) {</div><div class='add'>+		if (IS_ERR(mtr-&gt;umem)) {</div><div class='ctx'> 			ibdev_err(ibdev, "failed to get umem, ret = %ld.\n",</div><div class='ctx'> 				  PTR_ERR(mtr-&gt;umem));</div><div class='ctx'> 			return -ENOMEM;</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c<br/>index 783e71852c50..d35cf59d0f43 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_pd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_pd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_pd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_pd.c</a></div><div class='hunk'>@@ -149,14 +149,18 @@ int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata)</div><div class='ctx'> 	struct hns_roce_xrcd *xrcd = to_hr_xrcd(ib_xrcd);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!(hr_dev-&gt;caps.flags &amp; HNS_ROCE_CAP_FLAG_XRC))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	if (!(hr_dev-&gt;caps.flags &amp; HNS_ROCE_CAP_FLAG_XRC)) {</div><div class='add'>+		ret = -EOPNOTSUPP;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = hns_roce_xrcd_alloc(hr_dev, &amp;xrcd-&gt;xrcdn);</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_XRCD_ALLOC_ERR_CNT]);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata)</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c<br/>index 828b58534aa9..31b147210688 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_qp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_qp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_qp.c</a></div><div class='hunk'>@@ -1216,7 +1216,7 @@ int hns_roce_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,</div><div class='ctx'> </div><div class='ctx'> 	ret = check_qp_type(hr_dev, init_attr-&gt;qp_type, !!udata);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	if (init_attr-&gt;qp_type == IB_QPT_XRC_TGT)</div><div class='ctx'> 		hr_qp-&gt;xrcdn = to_hr_xrcd(init_attr-&gt;xrcd)-&gt;xrcdn;</div><div class='hunk'>@@ -1231,6 +1231,10 @@ int hns_roce_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,</div><div class='ctx'> 		ibdev_err(ibdev, "create QP type 0x%x failed(%d)\n",</div><div class='ctx'> 			  init_attr-&gt;qp_type, ret);</div><div class='ctx'> </div><div class='add'>+err_out:</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_QP_CREATE_ERR_CNT]);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1366,6 +1370,8 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;hr_qp-&gt;mutex);</div><div class='add'>+	if (ret)</div><div class='add'>+		atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_QP_MODIFY_ERR_CNT]);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/hw/hns/hns_roce_srq.c b/drivers/infiniband/hw/hns/hns_roce_srq.c<br/>index 4e2d1c8e164a..4abae9477854 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_srq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/hns/hns_roce_srq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/hns/hns_roce_srq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/hns/hns_roce_srq.c</a></div><div class='hunk'>@@ -475,11 +475,11 @@ int hns_roce_create_srq(struct ib_srq *ib_srq,</div><div class='ctx'> </div><div class='ctx'> 	ret = set_srq_param(srq, init_attr, udata);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	ret = alloc_srq_buf(hr_dev, srq, udata);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		goto err_out;</div><div class='ctx'> </div><div class='ctx'> 	ret = alloc_srq_db(hr_dev, srq, udata, &amp;resp);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -517,6 +517,8 @@ err_srq_db:</div><div class='ctx'> 	free_srq_db(hr_dev, srq, udata);</div><div class='ctx'> err_srq_buf:</div><div class='ctx'> 	free_srq_buf(hr_dev, srq);</div><div class='add'>+err_out:</div><div class='add'>+	atomic64_inc(&amp;hr_dev-&gt;dfx_cnt[HNS_ROCE_DFX_SRQ_CREATE_ERR_CNT]);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/hw.c b/drivers/infiniband/hw/irdma/hw.c<br/>index 8fa7e4a18e73..bd4b2b896444 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/hw.c</a></div><div class='hunk'>@@ -321,7 +321,11 @@ static void irdma_process_aeq(struct irdma_pci_f *rf)</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IRDMA_AE_QP_SUSPEND_COMPLETE:</div><div class='ctx'> 			if (iwqp-&gt;iwdev-&gt;vsi.tc_change_pending) {</div><div class='del'>-				atomic_dec(&amp;iwqp-&gt;sc_qp.vsi-&gt;qp_suspend_reqs);</div><div class='add'>+				if (!atomic_dec_return(&amp;qp-&gt;vsi-&gt;qp_suspend_reqs))</div><div class='add'>+					wake_up(&amp;iwqp-&gt;iwdev-&gt;suspend_wq);</div><div class='add'>+			}</div><div class='add'>+			if (iwqp-&gt;suspend_pending) {</div><div class='add'>+				iwqp-&gt;suspend_pending = false;</div><div class='ctx'> 				wake_up(&amp;iwqp-&gt;iwdev-&gt;suspend_wq);</div><div class='ctx'> 			}</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -581,9 +585,6 @@ static void irdma_destroy_cqp(struct irdma_pci_f *rf)</div><div class='ctx'> 	struct irdma_cqp *cqp = &amp;rf-&gt;cqp;</div><div class='ctx'> 	int status = 0;</div><div class='ctx'> </div><div class='del'>-	if (rf-&gt;cqp_cmpl_wq)</div><div class='del'>-		destroy_workqueue(rf-&gt;cqp_cmpl_wq);</div><div class='del'>-</div><div class='ctx'> 	status = irdma_sc_cqp_destroy(dev-&gt;cqp);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status);</div><div class='hunk'>@@ -748,6 +749,9 @@ static void irdma_destroy_ccq(struct irdma_pci_f *rf)</div><div class='ctx'> 	struct irdma_ccq *ccq = &amp;rf-&gt;ccq;</div><div class='ctx'> 	int status = 0;</div><div class='ctx'> </div><div class='add'>+	if (rf-&gt;cqp_cmpl_wq)</div><div class='add'>+		destroy_workqueue(rf-&gt;cqp_cmpl_wq);</div><div class='add'>+</div><div class='ctx'> 	if (!rf-&gt;reset)</div><div class='ctx'> 		status = irdma_sc_ccq_destroy(dev-&gt;ccq, 0, true);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -1180,7 +1184,6 @@ static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,</div><div class='ctx'> 	int status;</div><div class='ctx'> 	struct irdma_ceq_init_info info = {};</div><div class='ctx'> 	struct irdma_sc_dev *dev = &amp;rf-&gt;sc_dev;</div><div class='del'>-	u64 scratch;</div><div class='ctx'> 	u32 ceq_size;</div><div class='ctx'> </div><div class='ctx'> 	info.ceq_id = ceq_id;</div><div class='hunk'>@@ -1201,14 +1204,13 @@ static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,</div><div class='ctx'> 	iwceq-&gt;sc_ceq.ceq_id = ceq_id;</div><div class='ctx'> 	info.dev = dev;</div><div class='ctx'> 	info.vsi = vsi;</div><div class='del'>-	scratch = (uintptr_t)&amp;rf-&gt;cqp.sc_cqp;</div><div class='ctx'> 	status = irdma_sc_ceq_init(&amp;iwceq-&gt;sc_ceq, &amp;info);</div><div class='ctx'> 	if (!status) {</div><div class='ctx'> 		if (dev-&gt;ceq_valid)</div><div class='ctx'> 			status = irdma_cqp_ceq_cmd(&amp;rf-&gt;sc_dev, &amp;iwceq-&gt;sc_ceq,</div><div class='ctx'> 						   IRDMA_OP_CEQ_CREATE);</div><div class='ctx'> 		else</div><div class='del'>-			status = irdma_sc_cceq_create(&amp;iwceq-&gt;sc_ceq, scratch);</div><div class='add'>+			status = irdma_sc_cceq_create(&amp;iwceq-&gt;sc_ceq, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (status) {</div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/main.c b/drivers/infiniband/hw/irdma/main.c<br/>index 9ac48b4dab41..3f13200ff71b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/main.c</a></div><div class='hunk'>@@ -48,7 +48,7 @@ static void irdma_prep_tc_change(struct irdma_device *iwdev)</div><div class='ctx'> 	/* Wait for all qp's to suspend */</div><div class='ctx'> 	wait_event_timeout(iwdev-&gt;suspend_wq,</div><div class='ctx'> 			   !atomic_read(&amp;iwdev-&gt;vsi.qp_suspend_reqs),</div><div class='del'>-			   IRDMA_EVENT_TIMEOUT);</div><div class='add'>+			   msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS));</div><div class='ctx'> 	irdma_ws_reset(&amp;iwdev-&gt;vsi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/main.h b/drivers/infiniband/hw/irdma/main.h<br/>index d66d87bb8bc4..b65bc2ea542f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/main.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/main.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/main.h</a></div><div class='hunk'>@@ -78,7 +78,7 @@ extern struct auxiliary_driver i40iw_auxiliary_drv;</div><div class='ctx'> </div><div class='ctx'> #define MAX_DPC_ITERATIONS	128</div><div class='ctx'> </div><div class='del'>-#define IRDMA_EVENT_TIMEOUT		50000</div><div class='add'>+#define IRDMA_EVENT_TIMEOUT_MS		5000</div><div class='ctx'> #define IRDMA_VCHNL_EVENT_TIMEOUT	100000</div><div class='ctx'> #define IRDMA_RST_TIMEOUT_HZ		4</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/utils.c b/drivers/infiniband/hw/irdma/utils.c<br/>index 916bfe2a91eb..0422787592d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/utils.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/utils.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/utils.c</a></div><div class='hunk'>@@ -1393,17 +1393,12 @@ int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len,</div><div class='ctx'> 			   u32 val)</div><div class='ctx'> {</div><div class='ctx'> 	u32 crc = 0;</div><div class='del'>-	int ret;</div><div class='del'>-	int ret_code = 0;</div><div class='ctx'> </div><div class='del'>-	crypto_shash_init(desc);</div><div class='del'>-	ret = crypto_shash_update(desc, addr, len);</div><div class='del'>-	if (!ret)</div><div class='del'>-		crypto_shash_final(desc, (u8 *)&amp;crc);</div><div class='add'>+	crypto_shash_digest(desc, addr, len, (u8 *)&amp;crc);</div><div class='ctx'> 	if (crc != val)</div><div class='del'>-		ret_code = -EINVAL;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return ret_code;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c<br/>index 2138f0a2ff85..b5eb8d421988 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/verbs.c</a></div><div class='hunk'>@@ -1157,6 +1157,21 @@ exit:</div><div class='ctx'> 	return prio;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int irdma_wait_for_suspend(struct irdma_qp *iwqp)</div><div class='add'>+{</div><div class='add'>+	if (!wait_event_timeout(iwqp-&gt;iwdev-&gt;suspend_wq,</div><div class='add'>+				!iwqp-&gt;suspend_pending,</div><div class='add'>+				msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) {</div><div class='add'>+		iwqp-&gt;suspend_pending = false;</div><div class='add'>+		ibdev_warn(&amp;iwqp-&gt;iwdev-&gt;ibdev,</div><div class='add'>+			   "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n",</div><div class='add'>+			   iwqp-&gt;ibqp.qp_num, iwqp-&gt;last_aeq);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * irdma_modify_qp_roce - modify qp request</div><div class='ctx'>  * @ibqp: qp's pointer for modify</div><div class='hunk'>@@ -1420,17 +1435,11 @@ int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,</div><div class='ctx'> </div><div class='ctx'> 			info.next_iwarp_state = IRDMA_QP_STATE_SQD;</div><div class='ctx'> 			issue_modify_qp = 1;</div><div class='add'>+			iwqp-&gt;suspend_pending = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case IB_QPS_SQE:</div><div class='ctx'> 		case IB_QPS_ERR:</div><div class='ctx'> 		case IB_QPS_RESET:</div><div class='del'>-			if (iwqp-&gt;iwarp_state == IRDMA_QP_STATE_RTS) {</div><div class='del'>-				spin_unlock_irqrestore(&amp;iwqp-&gt;lock, flags);</div><div class='del'>-				info.next_iwarp_state = IRDMA_QP_STATE_SQD;</div><div class='del'>-				irdma_hw_modify_qp(iwdev, iwqp, &amp;info, true);</div><div class='del'>-				spin_lock_irqsave(&amp;iwqp-&gt;lock, flags);</div><div class='del'>-			}</div><div class='del'>-</div><div class='ctx'> 			if (iwqp-&gt;iwarp_state == IRDMA_QP_STATE_ERROR) {</div><div class='ctx'> 				spin_unlock_irqrestore(&amp;iwqp-&gt;lock, flags);</div><div class='ctx'> 				if (udata &amp;&amp; udata-&gt;inlen) {</div><div class='hunk'>@@ -1467,6 +1476,11 @@ int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,</div><div class='ctx'> 			ctx_info-&gt;rem_endpoint_idx = udp_info-&gt;arp_idx;</div><div class='ctx'> 			if (irdma_hw_modify_qp(iwdev, iwqp, &amp;info, true))</div><div class='ctx'> 				return -EINVAL;</div><div class='add'>+			if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) {</div><div class='add'>+				ret = irdma_wait_for_suspend(iwqp);</div><div class='add'>+				if (ret)</div><div class='add'>+					return ret;</div><div class='add'>+			}</div><div class='ctx'> 			spin_lock_irqsave(&amp;iwqp-&gt;lock, flags);</div><div class='ctx'> 			if (iwqp-&gt;iwarp_state == info.curr_iwarp_state) {</div><div class='ctx'> 				iwqp-&gt;iwarp_state = info.next_iwarp_state;</div><div class='hunk'>@@ -2900,7 +2914,7 @@ static struct irdma_mr *irdma_alloc_iwmr(struct ib_umem *region,</div><div class='ctx'> 	iwmr-&gt;type = reg_type;</div><div class='ctx'> </div><div class='ctx'> 	pgsz_bitmap = (reg_type == IRDMA_MEMREG_TYPE_MEM) ?</div><div class='del'>-		iwdev-&gt;rf-&gt;sc_dev.hw_attrs.page_size_cap : PAGE_SIZE;</div><div class='add'>+		iwdev-&gt;rf-&gt;sc_dev.hw_attrs.page_size_cap : SZ_4K;</div><div class='ctx'> </div><div class='ctx'> 	iwmr-&gt;page_size = ib_umem_find_best_pgsz(region, pgsz_bitmap, virt);</div><div class='ctx'> 	if (unlikely(!iwmr-&gt;page_size)) {</div><div class='hunk'>@@ -2932,6 +2946,11 @@ static int irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u8 lvl;</div><div class='ctx'> </div><div class='add'>+	/* iWarp: Catch page not starting on OS page boundary */</div><div class='add'>+	if (!rdma_protocol_roce(&amp;iwdev-&gt;ibdev, 1) &amp;&amp;</div><div class='add'>+	    ib_umem_offset(iwmr-&gt;region))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	total = req.sq_pages + req.rq_pages + 1;</div><div class='ctx'> 	if (total &gt; iwmr-&gt;page_cnt)</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/infiniband/hw/irdma/verbs.h b/drivers/infiniband/hw/irdma/verbs.h<br/>index c42ac22de00e..cfa140b36395 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/verbs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/irdma/verbs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/irdma/verbs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/irdma/verbs.h</a></div><div class='hunk'>@@ -198,6 +198,7 @@ struct irdma_qp {</div><div class='ctx'> 	u8 flush_issued : 1;</div><div class='ctx'> 	u8 sig_all : 1;</div><div class='ctx'> 	u8 pau_mode : 1;</div><div class='add'>+	u8 suspend_pending : 1;</div><div class='ctx'> 	u8 rsvd : 1;</div><div class='ctx'> 	u8 iwarp_state;</div><div class='ctx'> 	u16 term_sq_flush_code;</div><div class='head'>diff --git a/drivers/infiniband/hw/mana/cq.c b/drivers/infiniband/hw/mana/cq.c<br/>index d141cab8a1e6..83ebd070535a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/cq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mana/cq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/cq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/cq.c</a></div><div class='hunk'>@@ -12,13 +12,20 @@ int mana_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	struct ib_device *ibdev = ibcq-&gt;device;</div><div class='ctx'> 	struct mana_ib_create_cq ucmd = {};</div><div class='ctx'> 	struct mana_ib_dev *mdev;</div><div class='add'>+	struct gdma_context *gc;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	mdev = container_of(ibdev, struct mana_ib_dev, ib_dev);</div><div class='add'>+	gc = mdev-&gt;gdma_dev-&gt;gdma_context;</div><div class='ctx'> </div><div class='ctx'> 	if (udata-&gt;inlen &lt; sizeof(ucmd))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (attr-&gt;comp_vector &gt; gc-&gt;max_num_queues)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cq-&gt;comp_vector = attr-&gt;comp_vector;</div><div class='add'>+</div><div class='ctx'> 	err = ib_copy_from_udata(&amp;ucmd, udata, min(sizeof(ucmd), udata-&gt;inlen));</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ibdev_dbg(ibdev,</div><div class='hunk'>@@ -26,7 +33,7 @@ int mana_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (attr-&gt;cqe &gt; MAX_SEND_BUFFERS_PER_QUEUE) {</div><div class='add'>+	if (attr-&gt;cqe &gt; mdev-&gt;adapter_caps.max_qp_wr) {</div><div class='ctx'> 		ibdev_dbg(ibdev, "CQE %d exceeding limit\n", attr-&gt;cqe);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -56,6 +63,7 @@ int mana_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The CQ ID is not known at this time. The ID is generated at create_qp</div><div class='ctx'> 	 */</div><div class='add'>+	cq-&gt;id = INVALID_QUEUE_ID;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -69,11 +77,33 @@ int mana_ib_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)</div><div class='ctx'> 	struct mana_ib_cq *cq = container_of(ibcq, struct mana_ib_cq, ibcq);</div><div class='ctx'> 	struct ib_device *ibdev = ibcq-&gt;device;</div><div class='ctx'> 	struct mana_ib_dev *mdev;</div><div class='add'>+	struct gdma_context *gc;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	mdev = container_of(ibdev, struct mana_ib_dev, ib_dev);</div><div class='add'>+	gc = mdev-&gt;gdma_dev-&gt;gdma_context;</div><div class='add'>+</div><div class='add'>+	err = mana_ib_gd_destroy_dma_region(mdev, cq-&gt;gdma_region);</div><div class='add'>+	if (err) {</div><div class='add'>+		ibdev_dbg(ibdev,</div><div class='add'>+			  "Failed to destroy dma region, %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cq-&gt;id != INVALID_QUEUE_ID) {</div><div class='add'>+		kfree(gc-&gt;cq_table[cq-&gt;id]);</div><div class='add'>+		gc-&gt;cq_table[cq-&gt;id] = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	mana_ib_gd_destroy_dma_region(mdev, cq-&gt;gdma_region);</div><div class='ctx'> 	ib_umem_release(cq-&gt;umem);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void mana_ib_cq_handler(void *ctx, struct gdma_queue *gdma_cq)</div><div class='add'>+{</div><div class='add'>+	struct mana_ib_cq *cq = ctx;</div><div class='add'>+</div><div class='add'>+	if (cq-&gt;ibcq.comp_handler)</div><div class='add'>+		cq-&gt;ibcq.comp_handler(&amp;cq-&gt;ibcq, cq-&gt;ibcq.cq_context);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/infiniband/hw/mana/device.c b/drivers/infiniband/hw/mana/device.c<br/>index d4541b8707e4..6fa902ee80a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mana/device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/device.c</a></div><div class='hunk'>@@ -68,7 +68,6 @@ static int mana_ib_probe(struct auxiliary_device *adev,</div><div class='ctx'> 	ibdev_dbg(&amp;dev-&gt;ib_dev, "mdev=%p id=%d num_ports=%d\n", mdev,</div><div class='ctx'> 		  mdev-&gt;dev_id.as_uint32, dev-&gt;ib_dev.phys_port_cnt);</div><div class='ctx'> </div><div class='del'>-	dev-&gt;gdma_dev = mdev;</div><div class='ctx'> 	dev-&gt;ib_dev.node_type = RDMA_NODE_IB_CA;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -78,16 +77,35 @@ static int mana_ib_probe(struct auxiliary_device *adev,</div><div class='ctx'> 	dev-&gt;ib_dev.num_comp_vectors = 1;</div><div class='ctx'> 	dev-&gt;ib_dev.dev.parent = mdev-&gt;gdma_context-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	ret = ib_register_device(&amp;dev-&gt;ib_dev, "mana_%d",</div><div class='del'>-				 mdev-&gt;gdma_context-&gt;dev);</div><div class='add'>+	ret = mana_gd_register_device(&amp;mdev-&gt;gdma_context-&gt;mana_ib);</div><div class='add'>+	if (ret) {</div><div class='add'>+		ibdev_err(&amp;dev-&gt;ib_dev, "Failed to register device, ret %d",</div><div class='add'>+			  ret);</div><div class='add'>+		goto free_ib_device;</div><div class='add'>+	}</div><div class='add'>+	dev-&gt;gdma_dev = &amp;mdev-&gt;gdma_context-&gt;mana_ib;</div><div class='add'>+</div><div class='add'>+	ret = mana_ib_gd_query_adapter_caps(dev);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		ib_dealloc_device(&amp;dev-&gt;ib_dev);</div><div class='del'>-		return ret;</div><div class='add'>+		ibdev_err(&amp;dev-&gt;ib_dev, "Failed to query device caps, ret %d",</div><div class='add'>+			  ret);</div><div class='add'>+		goto deregister_device;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = ib_register_device(&amp;dev-&gt;ib_dev, "mana_%d",</div><div class='add'>+				 mdev-&gt;gdma_context-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto deregister_device;</div><div class='add'>+</div><div class='ctx'> 	dev_set_drvdata(&amp;adev-&gt;dev, dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+deregister_device:</div><div class='add'>+	mana_gd_deregister_device(dev-&gt;gdma_dev);</div><div class='add'>+free_ib_device:</div><div class='add'>+	ib_dealloc_device(&amp;dev-&gt;ib_dev);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mana_ib_remove(struct auxiliary_device *adev)</div><div class='hunk'>@@ -95,6 +113,9 @@ static void mana_ib_remove(struct auxiliary_device *adev)</div><div class='ctx'> 	struct mana_ib_dev *dev = dev_get_drvdata(&amp;adev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	ib_unregister_device(&amp;dev-&gt;ib_dev);</div><div class='add'>+</div><div class='add'>+	mana_gd_deregister_device(dev-&gt;gdma_dev);</div><div class='add'>+</div><div class='ctx'> 	ib_dealloc_device(&amp;dev-&gt;ib_dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/mana/main.c b/drivers/infiniband/hw/mana/main.c<br/>index 7be4c3adb4e2..faca092456fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mana/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/main.c</a></div><div class='hunk'>@@ -8,7 +8,7 @@</div><div class='ctx'> void mana_ib_uncfg_vport(struct mana_ib_dev *dev, struct mana_ib_pd *pd,</div><div class='ctx'> 			 u32 port)</div><div class='ctx'> {</div><div class='del'>-	struct gdma_dev *gd = dev-&gt;gdma_dev;</div><div class='add'>+	struct gdma_dev *gd = &amp;dev-&gt;gdma_dev-&gt;gdma_context-&gt;mana;</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='ctx'> 	struct net_device *ndev;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='hunk'>@@ -31,7 +31,7 @@ void mana_ib_uncfg_vport(struct mana_ib_dev *dev, struct mana_ib_pd *pd,</div><div class='ctx'> int mana_ib_cfg_vport(struct mana_ib_dev *dev, u32 port, struct mana_ib_pd *pd,</div><div class='ctx'> 		      u32 doorbell_id)</div><div class='ctx'> {</div><div class='del'>-	struct gdma_dev *mdev = dev-&gt;gdma_dev;</div><div class='add'>+	struct gdma_dev *mdev = &amp;dev-&gt;gdma_dev-&gt;gdma_context-&gt;mana;</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='ctx'> 	struct net_device *ndev;</div><div class='hunk'>@@ -486,20 +486,17 @@ int mana_ib_get_port_immutable(struct ib_device *ibdev, u32 port_num,</div><div class='ctx'> int mana_ib_query_device(struct ib_device *ibdev, struct ib_device_attr *props,</div><div class='ctx'> 			 struct ib_udata *uhw)</div><div class='ctx'> {</div><div class='del'>-	props-&gt;max_qp = MANA_MAX_NUM_QUEUES;</div><div class='del'>-	props-&gt;max_qp_wr = MAX_SEND_BUFFERS_PER_QUEUE;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * max_cqe could be potentially much bigger.</div><div class='del'>-	 * As this version of driver only support RAW QP, set it to the same</div><div class='del'>-	 * value as max_qp_wr</div><div class='del'>-	 */</div><div class='del'>-	props-&gt;max_cqe = MAX_SEND_BUFFERS_PER_QUEUE;</div><div class='del'>-</div><div class='add'>+	struct mana_ib_dev *dev = container_of(ibdev,</div><div class='add'>+			struct mana_ib_dev, ib_dev);</div><div class='add'>+</div><div class='add'>+	props-&gt;max_qp = dev-&gt;adapter_caps.max_qp_count;</div><div class='add'>+	props-&gt;max_qp_wr = dev-&gt;adapter_caps.max_qp_wr;</div><div class='add'>+	props-&gt;max_cq = dev-&gt;adapter_caps.max_cq_count;</div><div class='add'>+	props-&gt;max_cqe = dev-&gt;adapter_caps.max_qp_wr;</div><div class='add'>+	props-&gt;max_mr = dev-&gt;adapter_caps.max_mr_count;</div><div class='ctx'> 	props-&gt;max_mr_size = MANA_IB_MAX_MR_SIZE;</div><div class='del'>-	props-&gt;max_mr = MANA_IB_MAX_MR;</div><div class='del'>-	props-&gt;max_send_sge = MAX_TX_WQE_SGL_ENTRIES;</div><div class='del'>-	props-&gt;max_recv_sge = MAX_RX_WQE_SGL_ENTRIES;</div><div class='add'>+	props-&gt;max_send_sge = dev-&gt;adapter_caps.max_send_sge_count;</div><div class='add'>+	props-&gt;max_recv_sge = dev-&gt;adapter_caps.max_recv_sge_count;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -521,3 +518,45 @@ int mana_ib_query_gid(struct ib_device *ibdev, u32 port, int index,</div><div class='ctx'> void mana_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)</div><div class='ctx'> {</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int mana_ib_gd_query_adapter_caps(struct mana_ib_dev *dev)</div><div class='add'>+{</div><div class='add'>+	struct mana_ib_adapter_caps *caps = &amp;dev-&gt;adapter_caps;</div><div class='add'>+	struct mana_ib_query_adapter_caps_resp resp = {};</div><div class='add'>+	struct mana_ib_query_adapter_caps_req req = {};</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	mana_gd_init_req_hdr(&amp;req.hdr, MANA_IB_GET_ADAPTER_CAP, sizeof(req),</div><div class='add'>+			     sizeof(resp));</div><div class='add'>+	req.hdr.resp.msg_version = GDMA_MESSAGE_V3;</div><div class='add'>+	req.hdr.dev_id = dev-&gt;gdma_dev-&gt;dev_id;</div><div class='add'>+</div><div class='add'>+	err = mana_gd_send_request(dev-&gt;gdma_dev-&gt;gdma_context, sizeof(req),</div><div class='add'>+				   &amp;req, sizeof(resp), &amp;resp);</div><div class='add'>+</div><div class='add'>+	if (err) {</div><div class='add'>+		ibdev_err(&amp;dev-&gt;ib_dev,</div><div class='add'>+			  "Failed to query adapter caps err %d", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	caps-&gt;max_sq_id = resp.max_sq_id;</div><div class='add'>+	caps-&gt;max_rq_id = resp.max_rq_id;</div><div class='add'>+	caps-&gt;max_cq_id = resp.max_cq_id;</div><div class='add'>+	caps-&gt;max_qp_count = resp.max_qp_count;</div><div class='add'>+	caps-&gt;max_cq_count = resp.max_cq_count;</div><div class='add'>+	caps-&gt;max_mr_count = resp.max_mr_count;</div><div class='add'>+	caps-&gt;max_pd_count = resp.max_pd_count;</div><div class='add'>+	caps-&gt;max_inbound_read_limit = resp.max_inbound_read_limit;</div><div class='add'>+	caps-&gt;max_outbound_read_limit = resp.max_outbound_read_limit;</div><div class='add'>+	caps-&gt;mw_count = resp.mw_count;</div><div class='add'>+	caps-&gt;max_srq_count = resp.max_srq_count;</div><div class='add'>+	caps-&gt;max_qp_wr = min_t(u32,</div><div class='add'>+				resp.max_requester_sq_size / GDMA_MAX_SQE_SIZE,</div><div class='add'>+				resp.max_requester_rq_size / GDMA_MAX_RQE_SIZE);</div><div class='add'>+	caps-&gt;max_inline_data_size = resp.max_inline_data_size;</div><div class='add'>+	caps-&gt;max_send_sge_count = resp.max_send_sge_count;</div><div class='add'>+	caps-&gt;max_recv_sge_count = resp.max_recv_sge_count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/infiniband/hw/mana/mana_ib.h b/drivers/infiniband/hw/mana/mana_ib.h<br/>index 502cc8672eef..6bdc0f5498d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/mana_ib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mana/mana_ib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/mana_ib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/mana_ib.h</a></div><div class='hunk'>@@ -27,9 +27,28 @@</div><div class='ctx'>  */</div><div class='ctx'> #define MANA_IB_MAX_MR		0xFFFFFFu</div><div class='ctx'> </div><div class='add'>+struct mana_ib_adapter_caps {</div><div class='add'>+	u32 max_sq_id;</div><div class='add'>+	u32 max_rq_id;</div><div class='add'>+	u32 max_cq_id;</div><div class='add'>+	u32 max_qp_count;</div><div class='add'>+	u32 max_cq_count;</div><div class='add'>+	u32 max_mr_count;</div><div class='add'>+	u32 max_pd_count;</div><div class='add'>+	u32 max_inbound_read_limit;</div><div class='add'>+	u32 max_outbound_read_limit;</div><div class='add'>+	u32 mw_count;</div><div class='add'>+	u32 max_srq_count;</div><div class='add'>+	u32 max_qp_wr;</div><div class='add'>+	u32 max_send_sge_count;</div><div class='add'>+	u32 max_recv_sge_count;</div><div class='add'>+	u32 max_inline_data_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mana_ib_dev {</div><div class='ctx'> 	struct ib_device ib_dev;</div><div class='ctx'> 	struct gdma_dev *gdma_dev;</div><div class='add'>+	struct mana_ib_adapter_caps adapter_caps;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mana_ib_wq {</div><div class='hunk'>@@ -67,6 +86,7 @@ struct mana_ib_cq {</div><div class='ctx'> 	int cqe;</div><div class='ctx'> 	u64 gdma_region;</div><div class='ctx'> 	u64 id;</div><div class='add'>+	u32 comp_vector;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mana_ib_qp {</div><div class='hunk'>@@ -92,6 +112,36 @@ struct mana_ib_rwq_ind_table {</div><div class='ctx'> 	struct ib_rwq_ind_table ib_ind_table;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum mana_ib_command_code {</div><div class='add'>+	MANA_IB_GET_ADAPTER_CAP = 0x30001,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mana_ib_query_adapter_caps_req {</div><div class='add'>+	struct gdma_req_hdr hdr;</div><div class='add'>+}; /*HW Data */</div><div class='add'>+</div><div class='add'>+struct mana_ib_query_adapter_caps_resp {</div><div class='add'>+	struct gdma_resp_hdr hdr;</div><div class='add'>+	u32 max_sq_id;</div><div class='add'>+	u32 max_rq_id;</div><div class='add'>+	u32 max_cq_id;</div><div class='add'>+	u32 max_qp_count;</div><div class='add'>+	u32 max_cq_count;</div><div class='add'>+	u32 max_mr_count;</div><div class='add'>+	u32 max_pd_count;</div><div class='add'>+	u32 max_inbound_read_limit;</div><div class='add'>+	u32 max_outbound_read_limit;</div><div class='add'>+	u32 mw_count;</div><div class='add'>+	u32 max_srq_count;</div><div class='add'>+	u32 max_requester_sq_size;</div><div class='add'>+	u32 max_responder_sq_size;</div><div class='add'>+	u32 max_requester_rq_size;</div><div class='add'>+	u32 max_responder_rq_size;</div><div class='add'>+	u32 max_send_sge_count;</div><div class='add'>+	u32 max_recv_sge_count;</div><div class='add'>+	u32 max_inline_data_size;</div><div class='add'>+}; /* HW Data */</div><div class='add'>+</div><div class='ctx'> int mana_ib_gd_create_dma_region(struct mana_ib_dev *dev, struct ib_umem *umem,</div><div class='ctx'> 				 mana_handle_t *gdma_region);</div><div class='ctx'> </div><div class='hunk'>@@ -159,4 +209,7 @@ int mana_ib_query_gid(struct ib_device *ibdev, u32 port, int index,</div><div class='ctx'> </div><div class='ctx'> void mana_ib_disassociate_ucontext(struct ib_ucontext *ibcontext);</div><div class='ctx'> </div><div class='add'>+int mana_ib_gd_query_adapter_caps(struct mana_ib_dev *mdev);</div><div class='add'>+</div><div class='add'>+void mana_ib_cq_handler(void *ctx, struct gdma_queue *gdma_cq);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/infiniband/hw/mana/qp.c b/drivers/infiniband/hw/mana/qp.c<br/>index 4b3b5b274e84..21ac9fcadf3f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/qp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mana/qp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mana/qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mana/qp.c</a></div><div class='hunk'>@@ -21,8 +21,8 @@ static int mana_ib_cfg_vport_steering(struct mana_ib_dev *dev,</div><div class='ctx'> 	u32 req_buf_size;</div><div class='ctx'> 	int i, err;</div><div class='ctx'> </div><div class='del'>-	mdev = dev-&gt;gdma_dev;</div><div class='del'>-	gc = mdev-&gt;gdma_context;</div><div class='add'>+	gc = dev-&gt;gdma_dev-&gt;gdma_context;</div><div class='add'>+	mdev = &amp;gc-&gt;mana;</div><div class='ctx'> </div><div class='ctx'> 	req_buf_size =</div><div class='ctx'> 		sizeof(*req) + sizeof(mana_handle_t) * MANA_INDIRECT_TABLE_SIZE;</div><div class='hunk'>@@ -102,20 +102,26 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 	struct ib_rwq_ind_table *ind_tbl = attr-&gt;rwq_ind_tbl;</div><div class='ctx'> 	struct mana_ib_create_qp_rss_resp resp = {};</div><div class='ctx'> 	struct mana_ib_create_qp_rss ucmd = {};</div><div class='del'>-	struct gdma_dev *gd = mdev-&gt;gdma_dev;</div><div class='add'>+	struct gdma_queue **gdma_cq_allocated;</div><div class='ctx'> 	mana_handle_t *mana_ind_table;</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='add'>+	struct gdma_queue *gdma_cq;</div><div class='add'>+	unsigned int ind_tbl_size;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='ctx'> 	struct net_device *ndev;</div><div class='add'>+	struct gdma_context *gc;</div><div class='ctx'> 	struct mana_ib_cq *cq;</div><div class='ctx'> 	struct mana_ib_wq *wq;</div><div class='del'>-	unsigned int ind_tbl_size;</div><div class='add'>+	struct gdma_dev *gd;</div><div class='add'>+	struct mana_eq *eq;</div><div class='ctx'> 	struct ib_cq *ibcq;</div><div class='ctx'> 	struct ib_wq *ibwq;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> 	u32 port;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	gc = mdev-&gt;gdma_dev-&gt;gdma_context;</div><div class='add'>+	gd = &amp;gc-&gt;mana;</div><div class='ctx'> 	mc = gd-&gt;driver_data;</div><div class='ctx'> </div><div class='ctx'> 	if (!udata || udata-&gt;inlen &lt; sizeof(ucmd))</div><div class='hunk'>@@ -129,7 +135,7 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (attr-&gt;cap.max_recv_wr &gt; MAX_SEND_BUFFERS_PER_QUEUE) {</div><div class='add'>+	if (attr-&gt;cap.max_recv_wr &gt; mdev-&gt;adapter_caps.max_qp_wr) {</div><div class='ctx'> 		ibdev_dbg(&amp;mdev-&gt;ib_dev,</div><div class='ctx'> 			  "Requested max_recv_wr %d exceeding limit\n",</div><div class='ctx'> 			  attr-&gt;cap.max_recv_wr);</div><div class='hunk'>@@ -178,6 +184,13 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gdma_cq_allocated = kcalloc(ind_tbl_size, sizeof(*gdma_cq_allocated),</div><div class='add'>+				    GFP_KERNEL);</div><div class='add'>+	if (!gdma_cq_allocated) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto fail;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	qp-&gt;port = port;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ind_tbl_size; i++) {</div><div class='hunk'>@@ -196,12 +209,16 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 		cq_spec.gdma_region = cq-&gt;gdma_region;</div><div class='ctx'> 		cq_spec.queue_size = cq-&gt;cqe * COMP_ENTRY_SIZE;</div><div class='ctx'> 		cq_spec.modr_ctx_id = 0;</div><div class='del'>-		cq_spec.attached_eq = GDMA_CQ_NO_EQ;</div><div class='add'>+		eq = &amp;mc-&gt;eqs[cq-&gt;comp_vector % gc-&gt;max_num_queues];</div><div class='add'>+		cq_spec.attached_eq = eq-&gt;eq-&gt;id;</div><div class='ctx'> </div><div class='ctx'> 		ret = mana_create_wq_obj(mpc, mpc-&gt;port_handle, GDMA_RQ,</div><div class='ctx'> 					 &amp;wq_spec, &amp;cq_spec, &amp;wq-&gt;rx_object);</div><div class='del'>-		if (ret)</div><div class='add'>+		if (ret) {</div><div class='add'>+			/* Do cleanup starting with index i-1 */</div><div class='add'>+			i--;</div><div class='ctx'> 			goto fail;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		/* The GDMA regions are now owned by the WQ object */</div><div class='ctx'> 		wq-&gt;gdma_region = GDMA_INVALID_DMA_REGION;</div><div class='hunk'>@@ -218,6 +235,21 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 		resp.entries[i].wqid = wq-&gt;id;</div><div class='ctx'> </div><div class='ctx'> 		mana_ind_table[i] = wq-&gt;rx_object;</div><div class='add'>+</div><div class='add'>+		/* Create CQ table entry */</div><div class='add'>+		WARN_ON(gc-&gt;cq_table[cq-&gt;id]);</div><div class='add'>+		gdma_cq = kzalloc(sizeof(*gdma_cq), GFP_KERNEL);</div><div class='add'>+		if (!gdma_cq) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto fail;</div><div class='add'>+		}</div><div class='add'>+		gdma_cq_allocated[i] = gdma_cq;</div><div class='add'>+</div><div class='add'>+		gdma_cq-&gt;cq.context = cq;</div><div class='add'>+		gdma_cq-&gt;type = GDMA_CQ;</div><div class='add'>+		gdma_cq-&gt;cq.callback = mana_ib_cq_handler;</div><div class='add'>+		gdma_cq-&gt;id = cq-&gt;id;</div><div class='add'>+		gc-&gt;cq_table[cq-&gt;id] = gdma_cq;</div><div class='ctx'> 	}</div><div class='ctx'> 	resp.num_entries = i;</div><div class='ctx'> </div><div class='hunk'>@@ -237,6 +269,7 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(gdma_cq_allocated);</div><div class='ctx'> 	kfree(mana_ind_table);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -244,10 +277,17 @@ static int mana_ib_create_qp_rss(struct ib_qp *ibqp, struct ib_pd *pd,</div><div class='ctx'> fail:</div><div class='ctx'> 	while (i-- &gt; 0) {</div><div class='ctx'> 		ibwq = ind_tbl-&gt;ind_tbl[i];</div><div class='add'>+		ibcq = ibwq-&gt;cq;</div><div class='ctx'> 		wq = container_of(ibwq, struct mana_ib_wq, ibwq);</div><div class='add'>+		cq = container_of(ibcq, struct mana_ib_cq, ibcq);</div><div class='add'>+</div><div class='add'>+		gc-&gt;cq_table[cq-&gt;id] = NULL;</div><div class='add'>+		kfree(gdma_cq_allocated[i]);</div><div class='add'>+</div><div class='ctx'> 		mana_destroy_wq_obj(mpc, GDMA_RQ, wq-&gt;rx_object);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	kfree(gdma_cq_allocated);</div><div class='ctx'> 	kfree(mana_ind_table);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -266,17 +306,20 @@ static int mana_ib_create_qp_raw(struct ib_qp *ibqp, struct ib_pd *ibpd,</div><div class='ctx'> 	struct mana_ib_ucontext *mana_ucontext =</div><div class='ctx'> 		rdma_udata_to_drv_context(udata, struct mana_ib_ucontext,</div><div class='ctx'> 					  ibucontext);</div><div class='add'>+	struct gdma_dev *gd = &amp;mdev-&gt;gdma_dev-&gt;gdma_context-&gt;mana;</div><div class='ctx'> 	struct mana_ib_create_qp_resp resp = {};</div><div class='del'>-	struct gdma_dev *gd = mdev-&gt;gdma_dev;</div><div class='ctx'> 	struct mana_ib_create_qp ucmd = {};</div><div class='add'>+	struct gdma_queue *gdma_cq = NULL;</div><div class='ctx'> 	struct mana_obj_spec wq_spec = {};</div><div class='ctx'> 	struct mana_obj_spec cq_spec = {};</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='ctx'> 	struct net_device *ndev;</div><div class='ctx'> 	struct ib_umem *umem;</div><div class='del'>-	int err;</div><div class='add'>+	struct mana_eq *eq;</div><div class='add'>+	int eq_vec;</div><div class='ctx'> 	u32 port;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	mc = gd-&gt;driver_data;</div><div class='ctx'> </div><div class='hunk'>@@ -295,7 +338,7 @@ static int mana_ib_create_qp_raw(struct ib_qp *ibqp, struct ib_pd *ibpd,</div><div class='ctx'> 	if (port &lt; 1 || port &gt; mc-&gt;num_ports)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (attr-&gt;cap.max_send_wr &gt; MAX_SEND_BUFFERS_PER_QUEUE) {</div><div class='add'>+	if (attr-&gt;cap.max_send_wr &gt; mdev-&gt;adapter_caps.max_qp_wr) {</div><div class='ctx'> 		ibdev_dbg(&amp;mdev-&gt;ib_dev,</div><div class='ctx'> 			  "Requested max_send_wr %d exceeding limit\n",</div><div class='ctx'> 			  attr-&gt;cap.max_send_wr);</div><div class='hunk'>@@ -353,7 +396,9 @@ static int mana_ib_create_qp_raw(struct ib_qp *ibqp, struct ib_pd *ibpd,</div><div class='ctx'> 	cq_spec.gdma_region = send_cq-&gt;gdma_region;</div><div class='ctx'> 	cq_spec.queue_size = send_cq-&gt;cqe * COMP_ENTRY_SIZE;</div><div class='ctx'> 	cq_spec.modr_ctx_id = 0;</div><div class='del'>-	cq_spec.attached_eq = GDMA_CQ_NO_EQ;</div><div class='add'>+	eq_vec = send_cq-&gt;comp_vector % gd-&gt;gdma_context-&gt;max_num_queues;</div><div class='add'>+	eq = &amp;mc-&gt;eqs[eq_vec];</div><div class='add'>+	cq_spec.attached_eq = eq-&gt;eq-&gt;id;</div><div class='ctx'> </div><div class='ctx'> 	err = mana_create_wq_obj(mpc, mpc-&gt;port_handle, GDMA_SQ, &amp;wq_spec,</div><div class='ctx'> 				 &amp;cq_spec, &amp;qp-&gt;tx_object);</div><div class='hunk'>@@ -371,6 +416,20 @@ static int mana_ib_create_qp_raw(struct ib_qp *ibqp, struct ib_pd *ibpd,</div><div class='ctx'> 	qp-&gt;sq_id = wq_spec.queue_index;</div><div class='ctx'> 	send_cq-&gt;id = cq_spec.queue_index;</div><div class='ctx'> </div><div class='add'>+	/* Create CQ table entry */</div><div class='add'>+	WARN_ON(gd-&gt;gdma_context-&gt;cq_table[send_cq-&gt;id]);</div><div class='add'>+	gdma_cq = kzalloc(sizeof(*gdma_cq), GFP_KERNEL);</div><div class='add'>+	if (!gdma_cq) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto err_destroy_wq_obj;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gdma_cq-&gt;cq.context = send_cq;</div><div class='add'>+	gdma_cq-&gt;type = GDMA_CQ;</div><div class='add'>+	gdma_cq-&gt;cq.callback = mana_ib_cq_handler;</div><div class='add'>+	gdma_cq-&gt;id = send_cq-&gt;id;</div><div class='add'>+	gd-&gt;gdma_context-&gt;cq_table[send_cq-&gt;id] = gdma_cq;</div><div class='add'>+</div><div class='ctx'> 	ibdev_dbg(&amp;mdev-&gt;ib_dev,</div><div class='ctx'> 		  "ret %d qp-&gt;tx_object 0x%llx sq id %llu cq id %llu\n", err,</div><div class='ctx'> 		  qp-&gt;tx_object, qp-&gt;sq_id, send_cq-&gt;id);</div><div class='hunk'>@@ -384,11 +443,15 @@ static int mana_ib_create_qp_raw(struct ib_qp *ibqp, struct ib_pd *ibpd,</div><div class='ctx'> 		ibdev_dbg(&amp;mdev-&gt;ib_dev,</div><div class='ctx'> 			  "Failed copy udata for create qp-raw, %d\n",</div><div class='ctx'> 			  err);</div><div class='del'>-		goto err_destroy_wq_obj;</div><div class='add'>+		goto err_release_gdma_cq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+err_release_gdma_cq:</div><div class='add'>+	kfree(gdma_cq);</div><div class='add'>+	gd-&gt;gdma_context-&gt;cq_table[send_cq-&gt;id] = NULL;</div><div class='add'>+</div><div class='ctx'> err_destroy_wq_obj:</div><div class='ctx'> 	mana_destroy_wq_obj(mpc, GDMA_SQ, qp-&gt;tx_object);</div><div class='ctx'> </div><div class='hunk'>@@ -437,7 +500,7 @@ static int mana_ib_destroy_qp_rss(struct mana_ib_qp *qp,</div><div class='ctx'> {</div><div class='ctx'> 	struct mana_ib_dev *mdev =</div><div class='ctx'> 		container_of(qp-&gt;ibqp.device, struct mana_ib_dev, ib_dev);</div><div class='del'>-	struct gdma_dev *gd = mdev-&gt;gdma_dev;</div><div class='add'>+	struct gdma_dev *gd = &amp;mdev-&gt;gdma_dev-&gt;gdma_context-&gt;mana;</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='ctx'> 	struct net_device *ndev;</div><div class='hunk'>@@ -464,7 +527,7 @@ static int mana_ib_destroy_qp_raw(struct mana_ib_qp *qp, struct ib_udata *udata)</div><div class='ctx'> {</div><div class='ctx'> 	struct mana_ib_dev *mdev =</div><div class='ctx'> 		container_of(qp-&gt;ibqp.device, struct mana_ib_dev, ib_dev);</div><div class='del'>-	struct gdma_dev *gd = mdev-&gt;gdma_dev;</div><div class='add'>+	struct gdma_dev *gd = &amp;mdev-&gt;gdma_dev-&gt;gdma_context-&gt;mana;</div><div class='ctx'> 	struct ib_pd *ibpd = qp-&gt;ibqp.pd;</div><div class='ctx'> 	struct mana_port_context *mpc;</div><div class='ctx'> 	struct mana_context *mc;</div><div class='head'>diff --git a/drivers/infiniband/hw/mlx5/devx.c b/drivers/infiniband/hw/mlx5/devx.c<br/>index 8ba53edf2311..869369cb5b5f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/devx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mlx5/devx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/devx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/devx.c</a></div><div class='hunk'>@@ -2498,7 +2498,7 @@ static void dispatch_event_fd(struct list_head *fd_list,</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_rcu(item, fd_list, xa_list) {</div><div class='ctx'> 		if (item-&gt;eventfd)</div><div class='del'>-			eventfd_signal(item-&gt;eventfd, 1);</div><div class='add'>+			eventfd_signal(item-&gt;eventfd);</div><div class='ctx'> 		else</div><div class='ctx'> 			deliver_event(item, data);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/infiniband/hw/mlx5/dm.c b/drivers/infiniband/hw/mlx5/dm.c<br/>index 3669c90b2dad..b4c97fb62abf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/dm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mlx5/dm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/dm.c</a></div><div class='hunk'>@@ -341,6 +341,8 @@ static enum mlx5_sw_icm_type get_icm_type(int uapi_type)</div><div class='ctx'> 		return MLX5_SW_ICM_TYPE_HEADER_MODIFY;</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM:</div><div class='ctx'> 		return MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN;</div><div class='add'>+	case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM:</div><div class='add'>+		return MLX5_SW_ICM_TYPE_SW_ENCAP;</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return MLX5_SW_ICM_TYPE_STEERING;</div><div class='hunk'>@@ -364,6 +366,7 @@ static struct ib_dm *handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,</div><div class='ctx'> 	switch (type) {</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:</div><div class='add'>+	case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM:</div><div class='ctx'> 		if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev, sw_owner) ||</div><div class='ctx'> 		      MLX5_CAP_FLOWTABLE_NIC_TX(dev, sw_owner) ||</div><div class='ctx'> 		      MLX5_CAP_FLOWTABLE_NIC_RX(dev, sw_owner_v2) ||</div><div class='hunk'>@@ -438,6 +441,7 @@ struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM:</div><div class='add'>+	case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM:</div><div class='ctx'> 		return handle_alloc_dm_sw_icm(context, attr, attrs, type);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return ERR_PTR(-EOPNOTSUPP);</div><div class='hunk'>@@ -491,6 +495,7 @@ static int mlx5_ib_dealloc_dm(struct ib_dm *ibdm,</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM:</div><div class='add'>+	case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM:</div><div class='ctx'> 		return mlx5_dm_icm_dealloc(ctx, to_icm(ibdm));</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='head'>diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c<br/>index 650a15b6cfbc..c2b557e64290 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mlx5/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/main.c</a></div><div class='hunk'>@@ -818,6 +818,17 @@ static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)</div><div class='ctx'> 				    MLX5_REG_NODE_DESC, 0, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev,</div><div class='add'>+				struct mlx5_ib_query_device_resp *resp)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_eswitch *esw = mdev-&gt;priv.eswitch;</div><div class='add'>+	u16 vport = mlx5_eswitch_manager_vport(mdev);</div><div class='add'>+</div><div class='add'>+	resp-&gt;reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw,</div><div class='add'>+								      vport);</div><div class='add'>+	resp-&gt;reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask();</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mlx5_ib_query_device(struct ib_device *ibdev,</div><div class='ctx'> 				struct ib_device_attr *props,</div><div class='ctx'> 				struct ib_udata *uhw)</div><div class='hunk'>@@ -1209,6 +1220,19 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,</div><div class='ctx'> 			MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (offsetofend(typeof(resp), reserved) &lt;= uhw_outlen)</div><div class='add'>+		resp.response_length += sizeof(resp.reserved);</div><div class='add'>+</div><div class='add'>+	if (offsetofend(typeof(resp), reg_c0) &lt;= uhw_outlen) {</div><div class='add'>+		struct mlx5_eswitch *esw = mdev-&gt;priv.eswitch;</div><div class='add'>+</div><div class='add'>+		resp.response_length += sizeof(resp.reg_c0);</div><div class='add'>+</div><div class='add'>+		if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS &amp;&amp;</div><div class='add'>+		    mlx5_eswitch_vport_match_metadata_enabled(esw))</div><div class='add'>+			fill_esw_mgr_reg_c0(mdev, &amp;resp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (uhw_outlen) {</div><div class='ctx'> 		err = ib_copy_to_udata(uhw, &amp;resp, resp.response_length);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c<br/>index 18e459b55746..a8ee2ca1f4a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/mr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mlx5/mr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mlx5/mr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mlx5/mr.c</a></div><div class='hunk'>@@ -1347,6 +1347,7 @@ struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:</div><div class='ctx'> 	case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM:</div><div class='add'>+	case MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM:</div><div class='ctx'> 		if (attr-&gt;access_flags &amp; ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS)</div><div class='ctx'> 			return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/hw/mthca/mthca_cmd.c b/drivers/infiniband/hw/mthca/mthca_cmd.c<br/>index f330ce895d88..8fe0cef7e2be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mthca/mthca_cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mthca/mthca_cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mthca/mthca_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mthca/mthca_cmd.c</a></div><div class='hunk'>@@ -635,7 +635,7 @@ void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)</div><div class='ctx'> </div><div class='ctx'> int mthca_SYS_EN(struct mthca_dev *dev)</div><div class='ctx'> {</div><div class='del'>-	u64 out;</div><div class='add'>+	u64 out = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = mthca_cmd_imm(dev, 0, &amp;out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);</div><div class='hunk'>@@ -1955,7 +1955,7 @@ int mthca_WRITE_MGM(struct mthca_dev *dev, int index,</div><div class='ctx'> int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,</div><div class='ctx'> 		    u16 *hash)</div><div class='ctx'> {</div><div class='del'>-	u64 imm;</div><div class='add'>+	u64 imm = 0;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = mthca_cmd_imm(dev, mailbox-&gt;dma, &amp;imm, 0, 0, CMD_MGID_HASH,</div><div class='head'>diff --git a/drivers/infiniband/hw/mthca/mthca_main.c b/drivers/infiniband/hw/mthca/mthca_main.c<br/>index b54bc8865dae..1ab268b77096 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mthca/mthca_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/hw/mthca/mthca_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/hw/mthca/mthca_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/hw/mthca/mthca_main.c</a></div><div class='hunk'>@@ -382,7 +382,7 @@ static int mthca_init_icm(struct mthca_dev *mdev,</div><div class='ctx'> 			  struct mthca_init_hca_param *init_hca,</div><div class='ctx'> 			  u64 icm_size)</div><div class='ctx'> {</div><div class='del'>-	u64 aux_pages;</div><div class='add'>+	u64 aux_pages = 0;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = mthca_SET_ICM_SIZE(mdev, icm_size, &amp;aux_pages);</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw.h b/drivers/infiniband/sw/siw/siw.h<br/>index cec5cccd2e75..75253f2b3e3d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw.h</a></div><div class='hunk'>@@ -121,11 +121,10 @@ struct siw_page_chunk {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct siw_umem {</div><div class='add'>+	struct ib_umem *base_mem;</div><div class='ctx'> 	struct siw_page_chunk *page_chunk;</div><div class='ctx'> 	int num_pages;</div><div class='del'>-	bool writable;</div><div class='ctx'> 	u64 fp_addr; /* First page base address */</div><div class='del'>-	struct mm_struct *owning_mm;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct siw_pble {</div><div class='hunk'>@@ -289,10 +288,11 @@ struct siw_rx_stream {</div><div class='ctx'> 	int skb_offset; /* offset in skb */</div><div class='ctx'> 	int skb_copied; /* processed bytes in skb */</div><div class='ctx'> </div><div class='add'>+	enum siw_rx_state state;</div><div class='add'>+</div><div class='ctx'> 	union iwarp_hdr hdr;</div><div class='ctx'> 	struct mpa_trailer trailer;</div><div class='del'>-</div><div class='del'>-	enum siw_rx_state state;</div><div class='add'>+	struct shash_desc *mpa_crc_hd;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * For each FPDU, main RX loop runs through 3 stages:</div><div class='hunk'>@@ -314,7 +314,6 @@ struct siw_rx_stream {</div><div class='ctx'> 	u64 ddp_to;</div><div class='ctx'> 	u32 inval_stag; /* Stag to be invalidated */</div><div class='ctx'> </div><div class='del'>-	struct shash_desc *mpa_crc_hd;</div><div class='ctx'> 	u8 rx_suspend : 1;</div><div class='ctx'> 	u8 pad : 2; /* # of pad bytes expected */</div><div class='ctx'> 	u8 rdmap_op : 4; /* opcode of current frame */</div><div class='hunk'>@@ -418,10 +417,10 @@ struct siw_iwarp_tx {</div><div class='ctx'> struct siw_qp {</div><div class='ctx'> 	struct ib_qp base_qp;</div><div class='ctx'> 	struct siw_device *sdev;</div><div class='add'>+	int tx_cpu;</div><div class='ctx'> 	struct kref ref;</div><div class='ctx'> 	struct completion qp_free;</div><div class='ctx'> 	struct list_head devq;</div><div class='del'>-	int tx_cpu;</div><div class='ctx'> 	struct siw_qp_attrs attrs;</div><div class='ctx'> </div><div class='ctx'> 	struct siw_cep *cep;</div><div class='hunk'>@@ -466,7 +465,6 @@ struct siw_qp {</div><div class='ctx'> 	} term_info;</div><div class='ctx'> 	struct rdma_user_mmap_entry *sq_entry; /* mmap info for SQE array */</div><div class='ctx'> 	struct rdma_user_mmap_entry *rq_entry; /* mmap info for RQE array */</div><div class='del'>-	struct rcu_head rcu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* helper macros */</div><div class='hunk'>@@ -659,7 +657,7 @@ static inline struct siw_sqe *orq_get_free(struct siw_qp *qp)</div><div class='ctx'> </div><div class='ctx'> static inline int siw_orq_empty(struct siw_qp *qp)</div><div class='ctx'> {</div><div class='del'>-	return qp-&gt;orq[qp-&gt;orq_get % qp-&gt;attrs.orq_size].flags == 0 ? 1 : 0;</div><div class='add'>+	return orq_get_current(qp)-&gt;flags == 0 ? 1 : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp)</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_cm.c b/drivers/infiniband/sw/siw/siw_cm.c<br/>index 7de651cb44e8..86323918a570 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_cm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_cm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_cm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_cm.c</a></div><div class='hunk'>@@ -41,16 +41,6 @@ static int siw_cm_upcall(struct siw_cep *cep, enum iw_cm_event_type reason,</div><div class='ctx'> </div><div class='ctx'> static void siw_sk_assign_cm_upcalls(struct sock *sk)</div><div class='ctx'> {</div><div class='del'>-	write_lock_bh(&amp;sk-&gt;sk_callback_lock);</div><div class='del'>-	sk-&gt;sk_state_change = siw_cm_llp_state_change;</div><div class='del'>-	sk-&gt;sk_data_ready = siw_cm_llp_data_ready;</div><div class='del'>-	sk-&gt;sk_write_space = siw_cm_llp_write_space;</div><div class='del'>-	sk-&gt;sk_error_report = siw_cm_llp_error_report;</div><div class='del'>-	write_unlock_bh(&amp;sk-&gt;sk_callback_lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void siw_sk_save_upcalls(struct sock *sk)</div><div class='del'>-{</div><div class='ctx'> 	struct siw_cep *cep = sk_to_cep(sk);</div><div class='ctx'> </div><div class='ctx'> 	write_lock_bh(&amp;sk-&gt;sk_callback_lock);</div><div class='hunk'>@@ -58,6 +48,11 @@ static void siw_sk_save_upcalls(struct sock *sk)</div><div class='ctx'> 	cep-&gt;sk_data_ready = sk-&gt;sk_data_ready;</div><div class='ctx'> 	cep-&gt;sk_write_space = sk-&gt;sk_write_space;</div><div class='ctx'> 	cep-&gt;sk_error_report = sk-&gt;sk_error_report;</div><div class='add'>+</div><div class='add'>+	sk-&gt;sk_state_change = siw_cm_llp_state_change;</div><div class='add'>+	sk-&gt;sk_data_ready = siw_cm_llp_data_ready;</div><div class='add'>+	sk-&gt;sk_write_space = siw_cm_llp_write_space;</div><div class='add'>+	sk-&gt;sk_error_report = siw_cm_llp_error_report;</div><div class='ctx'> 	write_unlock_bh(&amp;sk-&gt;sk_callback_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -156,7 +151,6 @@ static void siw_cep_socket_assoc(struct siw_cep *cep, struct socket *s)</div><div class='ctx'> 	siw_cep_get(cep);</div><div class='ctx'> 	s-&gt;sk-&gt;sk_user_data = cep;</div><div class='ctx'> </div><div class='del'>-	siw_sk_save_upcalls(s-&gt;sk);</div><div class='ctx'> 	siw_sk_assign_cm_upcalls(s-&gt;sk);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -364,6 +358,24 @@ static int siw_cm_upcall(struct siw_cep *cep, enum iw_cm_event_type reason,</div><div class='ctx'> 	return id-&gt;event_handler(id, &amp;event);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void siw_free_cm_id(struct siw_cep *cep)</div><div class='add'>+{</div><div class='add'>+	if (!cep-&gt;cm_id)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cep-&gt;cm_id-&gt;rem_ref(cep-&gt;cm_id);</div><div class='add'>+	cep-&gt;cm_id = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void siw_destroy_cep_sock(struct siw_cep *cep)</div><div class='add'>+{</div><div class='add'>+	if (cep-&gt;sock) {</div><div class='add'>+		siw_socket_disassoc(cep-&gt;sock);</div><div class='add'>+		sock_release(cep-&gt;sock);</div><div class='add'>+		cep-&gt;sock = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * siw_qp_cm_drop()</div><div class='ctx'>  *</div><div class='hunk'>@@ -393,8 +405,7 @@ void siw_qp_cm_drop(struct siw_qp *qp, int schedule)</div><div class='ctx'> 		}</div><div class='ctx'> 		siw_dbg_cep(cep, "immediate close, state %d\n", cep-&gt;state);</div><div class='ctx'> </div><div class='del'>-		if (qp-&gt;term_info.valid)</div><div class='del'>-			siw_send_terminate(qp);</div><div class='add'>+		siw_send_terminate(qp);</div><div class='ctx'> </div><div class='ctx'> 		if (cep-&gt;cm_id) {</div><div class='ctx'> 			switch (cep-&gt;state) {</div><div class='hunk'>@@ -416,20 +427,12 @@ void siw_qp_cm_drop(struct siw_qp *qp, int schedule)</div><div class='ctx'> 			default:</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='del'>-			cep-&gt;cm_id-&gt;rem_ref(cep-&gt;cm_id);</div><div class='del'>-			cep-&gt;cm_id = NULL;</div><div class='add'>+			siw_free_cm_id(cep);</div><div class='ctx'> 			siw_cep_put(cep);</div><div class='ctx'> 		}</div><div class='ctx'> 		cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='ctx'> </div><div class='del'>-		if (cep-&gt;sock) {</div><div class='del'>-			siw_socket_disassoc(cep-&gt;sock);</div><div class='del'>-			/*</div><div class='del'>-			 * Immediately close socket</div><div class='del'>-			 */</div><div class='del'>-			sock_release(cep-&gt;sock);</div><div class='del'>-			cep-&gt;sock = NULL;</div><div class='del'>-		}</div><div class='add'>+		siw_destroy_cep_sock(cep);</div><div class='ctx'> 		if (cep-&gt;qp) {</div><div class='ctx'> 			cep-&gt;qp = NULL;</div><div class='ctx'> 			siw_qp_put(qp);</div><div class='hunk'>@@ -445,6 +448,12 @@ void siw_cep_put(struct siw_cep *cep)</div><div class='ctx'> 	kref_put(&amp;cep-&gt;ref, __siw_cep_dealloc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void siw_cep_set_free_and_put(struct siw_cep *cep)</div><div class='add'>+{</div><div class='add'>+	siw_cep_set_free(cep);</div><div class='add'>+	siw_cep_put(cep);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void siw_cep_get(struct siw_cep *cep)</div><div class='ctx'> {</div><div class='ctx'> 	kref_get(&amp;cep-&gt;ref);</div><div class='hunk'>@@ -1061,7 +1070,7 @@ static void siw_cm_work_handler(struct work_struct *w)</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * QP scheduled LLP close</div><div class='ctx'> 		 */</div><div class='del'>-		if (cep-&gt;qp &amp;&amp; cep-&gt;qp-&gt;term_info.valid)</div><div class='add'>+		if (cep-&gt;qp)</div><div class='ctx'> 			siw_send_terminate(cep-&gt;qp);</div><div class='ctx'> </div><div class='ctx'> 		if (cep-&gt;cm_id)</div><div class='hunk'>@@ -1175,8 +1184,7 @@ static void siw_cm_work_handler(struct work_struct *w)</div><div class='ctx'> 			cep-&gt;sock = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (cep-&gt;cm_id) {</div><div class='del'>-			cep-&gt;cm_id-&gt;rem_ref(cep-&gt;cm_id);</div><div class='del'>-			cep-&gt;cm_id = NULL;</div><div class='add'>+			siw_free_cm_id(cep);</div><div class='ctx'> 			siw_cep_put(cep);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1515,9 +1523,7 @@ error:</div><div class='ctx'> </div><div class='ctx'> 		cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='ctx'> </div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-</div><div class='del'>-		siw_cep_put(cep);</div><div class='add'>+		siw_cep_set_free_and_put(cep);</div><div class='ctx'> </div><div class='ctx'> 	} else if (s) {</div><div class='ctx'> 		sock_release(s);</div><div class='hunk'>@@ -1548,7 +1554,7 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 	struct siw_cep *cep = (struct siw_cep *)id-&gt;provider_data;</div><div class='ctx'> 	struct siw_qp *qp;</div><div class='ctx'> 	struct siw_qp_attrs qp_attrs;</div><div class='del'>-	int rv, max_priv_data = MPA_MAX_PRIVDATA;</div><div class='add'>+	int rv = -EINVAL, max_priv_data = MPA_MAX_PRIVDATA;</div><div class='ctx'> 	bool wait_for_peer_rts = false;</div><div class='ctx'> </div><div class='ctx'> 	siw_cep_set_inuse(cep);</div><div class='hunk'>@@ -1564,26 +1570,17 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> </div><div class='ctx'> 	if (cep-&gt;state != SIW_EPSTATE_RECVD_MPAREQ) {</div><div class='ctx'> 		siw_dbg_cep(cep, "out of state\n");</div><div class='del'>-</div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-		siw_cep_put(cep);</div><div class='del'>-</div><div class='del'>-		return -ECONNRESET;</div><div class='add'>+		rv = -ECONNRESET;</div><div class='add'>+		goto free_cep;</div><div class='ctx'> 	}</div><div class='ctx'> 	qp = siw_qp_id2obj(sdev, params-&gt;qpn);</div><div class='ctx'> 	if (!qp) {</div><div class='ctx'> 		WARN(1, "[QP %d] does not exist\n", params-&gt;qpn);</div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-		siw_cep_put(cep);</div><div class='del'>-</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		goto free_cep;</div><div class='ctx'> 	}</div><div class='ctx'> 	down_write(&amp;qp-&gt;state_lock);</div><div class='del'>-	if (qp-&gt;attrs.state &gt; SIW_QP_STATE_RTR) {</div><div class='del'>-		rv = -EINVAL;</div><div class='del'>-		up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-		goto error;</div><div class='del'>-	}</div><div class='add'>+	if (qp-&gt;attrs.state &gt; SIW_QP_STATE_RTR)</div><div class='add'>+		goto error_unlock;</div><div class='ctx'> 	siw_dbg_cep(cep, "[QP %d]\n", params-&gt;qpn);</div><div class='ctx'> </div><div class='ctx'> 	if (try_gso &amp;&amp; cep-&gt;mpa.hdr.params.bits &amp; MPA_RR_FLAG_GSO_EXP) {</div><div class='hunk'>@@ -1597,9 +1594,7 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 			"[QP %u]: ord %d (max %d), ird %d (max %d)\n",</div><div class='ctx'> 			qp_id(qp), params-&gt;ord, sdev-&gt;attrs.max_ord,</div><div class='ctx'> 			params-&gt;ird, sdev-&gt;attrs.max_ird);</div><div class='del'>-		rv = -EINVAL;</div><div class='del'>-		up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-		goto error;</div><div class='add'>+		goto error_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (cep-&gt;enhanced_rdma_conn_est)</div><div class='ctx'> 		max_priv_data -= sizeof(struct mpa_v2_data);</div><div class='hunk'>@@ -1609,9 +1604,7 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 			cep,</div><div class='ctx'> 			"[QP %u]: private data length: %d (max %d)\n",</div><div class='ctx'> 			qp_id(qp), params-&gt;private_data_len, max_priv_data);</div><div class='del'>-		rv = -EINVAL;</div><div class='del'>-		up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-		goto error;</div><div class='add'>+		goto error_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (cep-&gt;enhanced_rdma_conn_est) {</div><div class='ctx'> 		if (params-&gt;ord &gt; cep-&gt;ord) {</div><div class='hunk'>@@ -1620,9 +1613,7 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 			} else {</div><div class='ctx'> 				cep-&gt;ird = params-&gt;ird;</div><div class='ctx'> 				cep-&gt;ord = params-&gt;ord;</div><div class='del'>-				rv = -EINVAL;</div><div class='del'>-				up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-				goto error;</div><div class='add'>+				goto error_unlock;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (params-&gt;ird &lt; cep-&gt;ird) {</div><div class='hunk'>@@ -1631,8 +1622,7 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 				params-&gt;ird = cep-&gt;ird;</div><div class='ctx'> 			else {</div><div class='ctx'> 				rv = -ENOMEM;</div><div class='del'>-				up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-				goto error;</div><div class='add'>+				goto error_unlock;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		if (cep-&gt;mpa.v2_ctrl.ord &amp;</div><div class='hunk'>@@ -1679,7 +1669,6 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 				   SIW_QP_ATTR_ORD | SIW_QP_ATTR_IRD |</div><div class='ctx'> 				   SIW_QP_ATTR_MPA);</div><div class='ctx'> 	up_write(&amp;qp-&gt;state_lock);</div><div class='del'>-</div><div class='ctx'> 	if (rv)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -1702,27 +1691,23 @@ int siw_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params)</div><div class='ctx'> 	siw_cep_set_free(cep);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+error_unlock:</div><div class='add'>+	up_write(&amp;qp-&gt;state_lock);</div><div class='ctx'> error:</div><div class='del'>-	siw_socket_disassoc(cep-&gt;sock);</div><div class='del'>-	sock_release(cep-&gt;sock);</div><div class='del'>-	cep-&gt;sock = NULL;</div><div class='add'>+	siw_destroy_cep_sock(cep);</div><div class='ctx'> </div><div class='ctx'> 	cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='ctx'> </div><div class='del'>-	if (cep-&gt;cm_id) {</div><div class='del'>-		cep-&gt;cm_id-&gt;rem_ref(id);</div><div class='del'>-		cep-&gt;cm_id = NULL;</div><div class='del'>-	}</div><div class='add'>+	siw_free_cm_id(cep);</div><div class='ctx'> 	if (qp-&gt;cep) {</div><div class='ctx'> 		siw_cep_put(cep);</div><div class='ctx'> 		qp-&gt;cep = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	cep-&gt;qp = NULL;</div><div class='ctx'> 	siw_qp_put(qp);</div><div class='del'>-</div><div class='del'>-	siw_cep_set_free(cep);</div><div class='del'>-	siw_cep_put(cep);</div><div class='del'>-</div><div class='add'>+free_cep:</div><div class='add'>+	siw_cep_set_free_and_put(cep);</div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1744,8 +1729,7 @@ int siw_reject(struct iw_cm_id *id, const void *pdata, u8 pd_len)</div><div class='ctx'> 	if (cep-&gt;state != SIW_EPSTATE_RECVD_MPAREQ) {</div><div class='ctx'> 		siw_dbg_cep(cep, "out of state\n");</div><div class='ctx'> </div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-		siw_cep_put(cep); /* put last reference */</div><div class='add'>+		siw_cep_set_free_and_put(cep); /* put last reference */</div><div class='ctx'> </div><div class='ctx'> 		return -ECONNRESET;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1756,14 +1740,11 @@ int siw_reject(struct iw_cm_id *id, const void *pdata, u8 pd_len)</div><div class='ctx'> 		cep-&gt;mpa.hdr.params.bits |= MPA_RR_FLAG_REJECT; /* reject */</div><div class='ctx'> 		siw_send_mpareqrep(cep, pdata, pd_len);</div><div class='ctx'> 	}</div><div class='del'>-	siw_socket_disassoc(cep-&gt;sock);</div><div class='del'>-	sock_release(cep-&gt;sock);</div><div class='del'>-	cep-&gt;sock = NULL;</div><div class='add'>+	siw_destroy_cep_sock(cep);</div><div class='ctx'> </div><div class='ctx'> 	cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='ctx'> </div><div class='del'>-	siw_cep_set_free(cep);</div><div class='del'>-	siw_cep_put(cep);</div><div class='add'>+	siw_cep_set_free_and_put(cep);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1890,16 +1871,12 @@ error:</div><div class='ctx'> 	if (cep) {</div><div class='ctx'> 		siw_cep_set_inuse(cep);</div><div class='ctx'> </div><div class='del'>-		if (cep-&gt;cm_id) {</div><div class='del'>-			cep-&gt;cm_id-&gt;rem_ref(cep-&gt;cm_id);</div><div class='del'>-			cep-&gt;cm_id = NULL;</div><div class='del'>-		}</div><div class='add'>+		siw_free_cm_id(cep);</div><div class='ctx'> 		cep-&gt;sock = NULL;</div><div class='ctx'> 		siw_socket_disassoc(s);</div><div class='ctx'> 		cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='ctx'> </div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-		siw_cep_put(cep);</div><div class='add'>+		siw_cep_set_free_and_put(cep);</div><div class='ctx'> 	}</div><div class='ctx'> 	sock_release(s);</div><div class='ctx'> </div><div class='hunk'>@@ -1923,18 +1900,14 @@ static void siw_drop_listeners(struct iw_cm_id *id)</div><div class='ctx'> </div><div class='ctx'> 		siw_cep_set_inuse(cep);</div><div class='ctx'> </div><div class='del'>-		if (cep-&gt;cm_id) {</div><div class='del'>-			cep-&gt;cm_id-&gt;rem_ref(cep-&gt;cm_id);</div><div class='del'>-			cep-&gt;cm_id = NULL;</div><div class='del'>-		}</div><div class='add'>+		siw_free_cm_id(cep);</div><div class='ctx'> 		if (cep-&gt;sock) {</div><div class='ctx'> 			siw_socket_disassoc(cep-&gt;sock);</div><div class='ctx'> 			sock_release(cep-&gt;sock);</div><div class='ctx'> 			cep-&gt;sock = NULL;</div><div class='ctx'> 		}</div><div class='ctx'> 		cep-&gt;state = SIW_EPSTATE_CLOSED;</div><div class='del'>-		siw_cep_set_free(cep);</div><div class='del'>-		siw_cep_put(cep);</div><div class='add'>+		siw_cep_set_free_and_put(cep);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_main.c b/drivers/infiniband/sw/siw/siw_main.c<br/>index 1ab62982df74..61ad8ca3d1a2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_main.c</a></div><div class='hunk'>@@ -109,6 +109,17 @@ static struct {</div><div class='ctx'> 	int num_nodes;</div><div class='ctx'> } siw_cpu_info;</div><div class='ctx'> </div><div class='add'>+static void siw_destroy_cpulist(int number)</div><div class='add'>+{</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	while (i &lt; number)</div><div class='add'>+		kfree(siw_cpu_info.tx_valid_cpus[i++]);</div><div class='add'>+</div><div class='add'>+	kfree(siw_cpu_info.tx_valid_cpus);</div><div class='add'>+	siw_cpu_info.tx_valid_cpus = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int siw_init_cpulist(void)</div><div class='ctx'> {</div><div class='ctx'> 	int i, num_nodes = nr_node_ids;</div><div class='hunk'>@@ -138,24 +149,11 @@ static int siw_init_cpulist(void)</div><div class='ctx'> </div><div class='ctx'> out_err:</div><div class='ctx'> 	siw_cpu_info.num_nodes = 0;</div><div class='del'>-	while (--i &gt;= 0)</div><div class='del'>-		kfree(siw_cpu_info.tx_valid_cpus[i]);</div><div class='del'>-	kfree(siw_cpu_info.tx_valid_cpus);</div><div class='del'>-	siw_cpu_info.tx_valid_cpus = NULL;</div><div class='add'>+	siw_destroy_cpulist(i);</div><div class='ctx'> </div><div class='ctx'> 	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void siw_destroy_cpulist(void)</div><div class='del'>-{</div><div class='del'>-	int i = 0;</div><div class='del'>-</div><div class='del'>-	while (i &lt; siw_cpu_info.num_nodes)</div><div class='del'>-		kfree(siw_cpu_info.tx_valid_cpus[i++]);</div><div class='del'>-</div><div class='del'>-	kfree(siw_cpu_info.tx_valid_cpus);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Choose CPU with least number of active QP's from NUMA node of</div><div class='ctx'>  * TX interface.</div><div class='hunk'>@@ -558,7 +556,7 @@ out_error:</div><div class='ctx'> 	pr_info("SoftIWARP attach failed. Error: %d\n", rv);</div><div class='ctx'> </div><div class='ctx'> 	siw_cm_exit();</div><div class='del'>-	siw_destroy_cpulist();</div><div class='add'>+	siw_destroy_cpulist(siw_cpu_info.num_nodes);</div><div class='ctx'> </div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='hunk'>@@ -573,7 +571,7 @@ static void __exit siw_exit_module(void)</div><div class='ctx'> </div><div class='ctx'> 	siw_cm_exit();</div><div class='ctx'> </div><div class='del'>-	siw_destroy_cpulist();</div><div class='add'>+	siw_destroy_cpulist(siw_cpu_info.num_nodes);</div><div class='ctx'> </div><div class='ctx'> 	if (siw_crypto_shash)</div><div class='ctx'> 		crypto_free_shash(siw_crypto_shash);</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_mem.c b/drivers/infiniband/sw/siw/siw_mem.c<br/>index c5f7f1669d09..dcb963607c8b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_mem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_mem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_mem.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/gfp.h&gt;</div><div class='ctx'> #include &lt;rdma/ib_verbs.h&gt;</div><div class='add'>+#include &lt;rdma/ib_umem.h&gt;</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/sched/mm.h&gt;</div><div class='hunk'>@@ -13,18 +14,20 @@</div><div class='ctx'> #include "siw.h"</div><div class='ctx'> #include "siw_mem.h"</div><div class='ctx'> </div><div class='add'>+/* Stag lookup is based on its index part only (24 bits). */</div><div class='add'>+#define SIW_STAG_MAX_INDEX	0x00ffffff</div><div class='add'>+</div><div class='ctx'> /*</div><div class='del'>- * Stag lookup is based on its index part only (24 bits).</div><div class='ctx'>  * The code avoids special Stag of zero and tries to randomize</div><div class='ctx'>  * STag values between 1 and SIW_STAG_MAX_INDEX.</div><div class='ctx'>  */</div><div class='ctx'> int siw_mem_add(struct siw_device *sdev, struct siw_mem *m)</div><div class='ctx'> {</div><div class='del'>-	struct xa_limit limit = XA_LIMIT(1, 0x00ffffff);</div><div class='add'>+	struct xa_limit limit = XA_LIMIT(1, SIW_STAG_MAX_INDEX);</div><div class='ctx'> 	u32 id, next;</div><div class='ctx'> </div><div class='ctx'> 	get_random_bytes(&amp;next, 4);</div><div class='del'>-	next &amp;= 0x00ffffff;</div><div class='add'>+	next &amp;= SIW_STAG_MAX_INDEX;</div><div class='ctx'> </div><div class='ctx'> 	if (xa_alloc_cyclic(&amp;sdev-&gt;mem_xa, &amp;id, m, limit, &amp;next,</div><div class='ctx'> 	    GFP_KERNEL) &lt; 0)</div><div class='hunk'>@@ -60,28 +63,17 @@ struct siw_mem *siw_mem_id2obj(struct siw_device *sdev, int stag_index)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void siw_free_plist(struct siw_page_chunk *chunk, int num_pages,</div><div class='del'>-			   bool dirty)</div><div class='del'>-{</div><div class='del'>-	unpin_user_pages_dirty_lock(chunk-&gt;plist, num_pages, dirty);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void siw_umem_release(struct siw_umem *umem, bool dirty)</div><div class='add'>+void siw_umem_release(struct siw_umem *umem)</div><div class='ctx'> {</div><div class='del'>-	struct mm_struct *mm_s = umem-&gt;owning_mm;</div><div class='ctx'> 	int i, num_pages = umem-&gt;num_pages;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; num_pages; i++) {</div><div class='del'>-		int to_free = min_t(int, PAGES_PER_CHUNK, num_pages);</div><div class='add'>+	if (umem-&gt;base_mem)</div><div class='add'>+		ib_umem_release(umem-&gt;base_mem);</div><div class='ctx'> </div><div class='del'>-		siw_free_plist(&amp;umem-&gt;page_chunk[i], to_free,</div><div class='del'>-			       umem-&gt;writable &amp;&amp; dirty);</div><div class='add'>+	for (i = 0; num_pages &gt; 0; i++) {</div><div class='ctx'> 		kfree(umem-&gt;page_chunk[i].plist);</div><div class='del'>-		num_pages -= to_free;</div><div class='add'>+		num_pages -= PAGES_PER_CHUNK;</div><div class='ctx'> 	}</div><div class='del'>-	atomic64_sub(umem-&gt;num_pages, &amp;mm_s-&gt;pinned_vm);</div><div class='del'>-</div><div class='del'>-	mmdrop(mm_s);</div><div class='ctx'> 	kfree(umem-&gt;page_chunk);</div><div class='ctx'> 	kfree(umem);</div><div class='ctx'> }</div><div class='hunk'>@@ -91,7 +83,7 @@ int siw_mr_add_mem(struct siw_mr *mr, struct ib_pd *pd, void *mem_obj,</div><div class='ctx'> {</div><div class='ctx'> 	struct siw_device *sdev = to_siw_dev(pd-&gt;device);</div><div class='ctx'> 	struct siw_mem *mem = kzalloc(sizeof(*mem), GFP_KERNEL);</div><div class='del'>-	struct xa_limit limit = XA_LIMIT(1, 0x00ffffff);</div><div class='add'>+	struct xa_limit limit = XA_LIMIT(1, SIW_STAG_MAX_INDEX);</div><div class='ctx'> 	u32 id, next;</div><div class='ctx'> </div><div class='ctx'> 	if (!mem)</div><div class='hunk'>@@ -107,7 +99,7 @@ int siw_mr_add_mem(struct siw_mr *mr, struct ib_pd *pd, void *mem_obj,</div><div class='ctx'> 	kref_init(&amp;mem-&gt;ref);</div><div class='ctx'> </div><div class='ctx'> 	get_random_bytes(&amp;next, 4);</div><div class='del'>-	next &amp;= 0x00ffffff;</div><div class='add'>+	next &amp;= SIW_STAG_MAX_INDEX;</div><div class='ctx'> </div><div class='ctx'> 	if (xa_alloc_cyclic(&amp;sdev-&gt;mem_xa, &amp;id, mem, limit, &amp;next,</div><div class='ctx'> 	    GFP_KERNEL) &lt; 0) {</div><div class='hunk'>@@ -145,7 +137,7 @@ void siw_free_mem(struct kref *ref)</div><div class='ctx'> </div><div class='ctx'> 	if (!mem-&gt;is_mw &amp;&amp; mem-&gt;mem_obj) {</div><div class='ctx'> 		if (mem-&gt;is_pbl == 0)</div><div class='del'>-			siw_umem_release(mem-&gt;umem, true);</div><div class='add'>+			siw_umem_release(mem-&gt;umem);</div><div class='ctx'> 		else</div><div class='ctx'> 			kfree(mem-&gt;pbl);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -362,18 +354,16 @@ struct siw_pbl *siw_pbl_alloc(u32 num_buf)</div><div class='ctx'> 	return pbl;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct siw_umem *siw_umem_get(u64 start, u64 len, bool writable)</div><div class='add'>+struct siw_umem *siw_umem_get(struct ib_device *base_dev, u64 start,</div><div class='add'>+			      u64 len, int rights)</div><div class='ctx'> {</div><div class='ctx'> 	struct siw_umem *umem;</div><div class='del'>-	struct mm_struct *mm_s;</div><div class='add'>+	struct ib_umem *base_mem;</div><div class='add'>+	struct sg_page_iter sg_iter;</div><div class='add'>+	struct sg_table *sgt;</div><div class='ctx'> 	u64 first_page_va;</div><div class='del'>-	unsigned long mlock_limit;</div><div class='del'>-	unsigned int foll_flags = FOLL_LONGTERM;</div><div class='ctx'> 	int num_pages, num_chunks, i, rv = 0;</div><div class='ctx'> </div><div class='del'>-	if (!can_do_mlock())</div><div class='del'>-		return ERR_PTR(-EPERM);</div><div class='del'>-</div><div class='ctx'> 	if (!len)</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> </div><div class='hunk'>@@ -385,65 +375,50 @@ struct siw_umem *siw_umem_get(u64 start, u64 len, bool writable)</div><div class='ctx'> 	if (!umem)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	mm_s = current-&gt;mm;</div><div class='del'>-	umem-&gt;owning_mm = mm_s;</div><div class='del'>-	umem-&gt;writable = writable;</div><div class='del'>-</div><div class='del'>-	mmgrab(mm_s);</div><div class='del'>-</div><div class='del'>-	if (writable)</div><div class='del'>-		foll_flags |= FOLL_WRITE;</div><div class='del'>-</div><div class='del'>-	mmap_read_lock(mm_s);</div><div class='del'>-</div><div class='del'>-	mlock_limit = rlimit(RLIMIT_MEMLOCK) &gt;&gt; PAGE_SHIFT;</div><div class='del'>-</div><div class='del'>-	if (atomic64_add_return(num_pages, &amp;mm_s-&gt;pinned_vm) &gt; mlock_limit) {</div><div class='del'>-		rv = -ENOMEM;</div><div class='del'>-		goto out_sem_up;</div><div class='del'>-	}</div><div class='del'>-	umem-&gt;fp_addr = first_page_va;</div><div class='del'>-</div><div class='ctx'> 	umem-&gt;page_chunk =</div><div class='ctx'> 		kcalloc(num_chunks, sizeof(struct siw_page_chunk), GFP_KERNEL);</div><div class='ctx'> 	if (!umem-&gt;page_chunk) {</div><div class='ctx'> 		rv = -ENOMEM;</div><div class='del'>-		goto out_sem_up;</div><div class='add'>+		goto err_out;</div><div class='ctx'> 	}</div><div class='del'>-	for (i = 0; num_pages; i++) {</div><div class='add'>+	base_mem = ib_umem_get(base_dev, start, len, rights);</div><div class='add'>+	if (IS_ERR(base_mem)) {</div><div class='add'>+		rv = PTR_ERR(base_mem);</div><div class='add'>+		siw_dbg(base_dev, "Cannot pin user memory: %d\n", rv);</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+	umem-&gt;fp_addr = first_page_va;</div><div class='add'>+	umem-&gt;base_mem = base_mem;</div><div class='add'>+</div><div class='add'>+	sgt = &amp;base_mem-&gt;sgt_append.sgt;</div><div class='add'>+	__sg_page_iter_start(&amp;sg_iter, sgt-&gt;sgl, sgt-&gt;orig_nents, 0);</div><div class='add'>+</div><div class='add'>+	if (!__sg_page_iter_next(&amp;sg_iter)) {</div><div class='add'>+		rv = -EINVAL;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; num_pages &gt; 0; i++) {</div><div class='ctx'> 		int nents = min_t(int, num_pages, PAGES_PER_CHUNK);</div><div class='ctx'> 		struct page **plist =</div><div class='ctx'> 			kcalloc(nents, sizeof(struct page *), GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 		if (!plist) {</div><div class='ctx'> 			rv = -ENOMEM;</div><div class='del'>-			goto out_sem_up;</div><div class='add'>+			goto err_out;</div><div class='ctx'> 		}</div><div class='ctx'> 		umem-&gt;page_chunk[i].plist = plist;</div><div class='del'>-		while (nents) {</div><div class='del'>-			rv = pin_user_pages(first_page_va, nents, foll_flags,</div><div class='del'>-					    plist);</div><div class='del'>-			if (rv &lt; 0)</div><div class='del'>-				goto out_sem_up;</div><div class='del'>-</div><div class='del'>-			umem-&gt;num_pages += rv;</div><div class='del'>-			first_page_va += rv * PAGE_SIZE;</div><div class='del'>-			plist += rv;</div><div class='del'>-			nents -= rv;</div><div class='del'>-			num_pages -= rv;</div><div class='add'>+		while (nents--) {</div><div class='add'>+			*plist = sg_page_iter_page(&amp;sg_iter);</div><div class='add'>+			umem-&gt;num_pages++;</div><div class='add'>+			num_pages--;</div><div class='add'>+			plist++;</div><div class='add'>+			if (!__sg_page_iter_next(&amp;sg_iter))</div><div class='add'>+				break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-out_sem_up:</div><div class='del'>-	mmap_read_unlock(mm_s);</div><div class='del'>-</div><div class='del'>-	if (rv &gt; 0)</div><div class='del'>-		return umem;</div><div class='del'>-</div><div class='del'>-	/* Adjust accounting for pages not pinned */</div><div class='del'>-	if (num_pages)</div><div class='del'>-		atomic64_sub(num_pages, &amp;mm_s-&gt;pinned_vm);</div><div class='del'>-</div><div class='del'>-	siw_umem_release(umem, false);</div><div class='add'>+	return umem;</div><div class='add'>+err_out:</div><div class='add'>+	siw_umem_release(umem);</div><div class='ctx'> </div><div class='ctx'> 	return ERR_PTR(rv);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_mem.h b/drivers/infiniband/sw/siw/siw_mem.h<br/>index a2835284fe5b..e74cfcd6dbc1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_mem.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_mem.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_mem.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_mem.h</a></div><div class='hunk'>@@ -6,8 +6,9 @@</div><div class='ctx'> #ifndef _SIW_MEM_H</div><div class='ctx'> #define _SIW_MEM_H</div><div class='ctx'> </div><div class='del'>-struct siw_umem *siw_umem_get(u64 start, u64 len, bool writable);</div><div class='del'>-void siw_umem_release(struct siw_umem *umem, bool dirty);</div><div class='add'>+struct siw_umem *siw_umem_get(struct ib_device *base_dave, u64 start,</div><div class='add'>+			      u64 len, int rights);</div><div class='add'>+void siw_umem_release(struct siw_umem *umem);</div><div class='ctx'> struct siw_pbl *siw_pbl_alloc(u32 num_buf);</div><div class='ctx'> dma_addr_t siw_pbl_get_buffer(struct siw_pbl *pbl, u64 off, int *len, int *idx);</div><div class='ctx'> struct siw_mem *siw_mem_id2obj(struct siw_device *sdev, int stag_index);</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_qp.c b/drivers/infiniband/sw/siw/siw_qp.c<br/>index 26e3904d2f41..da92cfa2073d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_qp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp.c</a></div><div class='hunk'>@@ -1183,7 +1183,7 @@ int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes,</div><div class='ctx'> /*</div><div class='ctx'>  * siw_sq_flush()</div><div class='ctx'>  *</div><div class='del'>- * Flush SQ and ORRQ entries to CQ.</div><div class='add'>+ * Flush SQ and ORQ entries to CQ.</div><div class='ctx'>  *</div><div class='ctx'>  * Must be called with QP state write lock held.</div><div class='ctx'>  * Therefore, SQ and ORQ lock must not be taken.</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_qp_rx.c b/drivers/infiniband/sw/siw/siw_qp_rx.c<br/>index 33e0fdb362ff..ed4fc39718b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_qp_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp_rx.c</a></div><div class='hunk'>@@ -405,6 +405,20 @@ out:</div><div class='ctx'> 	return wqe;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int siw_rx_data(struct siw_mem *mem_p, struct siw_rx_stream *srx,</div><div class='add'>+		       unsigned int *pbl_idx, u64 addr, int bytes)</div><div class='add'>+{</div><div class='add'>+	int rv;</div><div class='add'>+</div><div class='add'>+	if (mem_p-&gt;mem_obj == NULL)</div><div class='add'>+		rv = siw_rx_kva(srx, ib_virt_dma_to_ptr(addr), bytes);</div><div class='add'>+	else if (!mem_p-&gt;is_pbl)</div><div class='add'>+		rv = siw_rx_umem(srx, mem_p-&gt;umem, addr, bytes);</div><div class='add'>+	else</div><div class='add'>+		rv = siw_rx_pbl(srx, pbl_idx, mem_p, addr, bytes);</div><div class='add'>+	return rv;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * siw_proc_send:</div><div class='ctx'>  *</div><div class='hunk'>@@ -485,17 +499,8 @@ int siw_proc_send(struct siw_qp *qp)</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		mem_p = *mem;</div><div class='del'>-		if (mem_p-&gt;mem_obj == NULL)</div><div class='del'>-			rv = siw_rx_kva(srx,</div><div class='del'>-				ib_virt_dma_to_ptr(sge-&gt;laddr + frx-&gt;sge_off),</div><div class='del'>-				sge_bytes);</div><div class='del'>-		else if (!mem_p-&gt;is_pbl)</div><div class='del'>-			rv = siw_rx_umem(srx, mem_p-&gt;umem,</div><div class='del'>-					 sge-&gt;laddr + frx-&gt;sge_off, sge_bytes);</div><div class='del'>-		else</div><div class='del'>-			rv = siw_rx_pbl(srx, &amp;frx-&gt;pbl_idx, mem_p,</div><div class='del'>-					sge-&gt;laddr + frx-&gt;sge_off, sge_bytes);</div><div class='del'>-</div><div class='add'>+		rv = siw_rx_data(mem_p, srx, &amp;frx-&gt;pbl_idx,</div><div class='add'>+				 sge-&gt;laddr + frx-&gt;sge_off, sge_bytes);</div><div class='ctx'> 		if (unlikely(rv != sge_bytes)) {</div><div class='ctx'> 			wqe-&gt;processed += rcvd_bytes;</div><div class='ctx'> </div><div class='hunk'>@@ -598,17 +603,8 @@ int siw_proc_write(struct siw_qp *qp)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (mem-&gt;mem_obj == NULL)</div><div class='del'>-		rv = siw_rx_kva(srx,</div><div class='del'>-			(void *)(uintptr_t)(srx-&gt;ddp_to + srx-&gt;fpdu_part_rcvd),</div><div class='del'>-			bytes);</div><div class='del'>-	else if (!mem-&gt;is_pbl)</div><div class='del'>-		rv = siw_rx_umem(srx, mem-&gt;umem,</div><div class='del'>-				 srx-&gt;ddp_to + srx-&gt;fpdu_part_rcvd, bytes);</div><div class='del'>-	else</div><div class='del'>-		rv = siw_rx_pbl(srx, &amp;frx-&gt;pbl_idx, mem,</div><div class='del'>-				srx-&gt;ddp_to + srx-&gt;fpdu_part_rcvd, bytes);</div><div class='del'>-</div><div class='add'>+	rv = siw_rx_data(mem, srx, &amp;frx-&gt;pbl_idx,</div><div class='add'>+			 srx-&gt;ddp_to + srx-&gt;fpdu_part_rcvd, bytes);</div><div class='ctx'> 	if (unlikely(rv != bytes)) {</div><div class='ctx'> 		siw_init_terminate(qp, TERM_ERROR_LAYER_DDP,</div><div class='ctx'> 				   DDP_ETYPE_CATASTROPHIC,</div><div class='hunk'>@@ -849,17 +845,8 @@ int siw_proc_rresp(struct siw_qp *qp)</div><div class='ctx'> 	mem_p = *mem;</div><div class='ctx'> </div><div class='ctx'> 	bytes = min(srx-&gt;fpdu_part_rem, srx-&gt;skb_new);</div><div class='del'>-</div><div class='del'>-	if (mem_p-&gt;mem_obj == NULL)</div><div class='del'>-		rv = siw_rx_kva(srx,</div><div class='del'>-			ib_virt_dma_to_ptr(sge-&gt;laddr + wqe-&gt;processed),</div><div class='del'>-			bytes);</div><div class='del'>-	else if (!mem_p-&gt;is_pbl)</div><div class='del'>-		rv = siw_rx_umem(srx, mem_p-&gt;umem, sge-&gt;laddr + wqe-&gt;processed,</div><div class='del'>-				 bytes);</div><div class='del'>-	else</div><div class='del'>-		rv = siw_rx_pbl(srx, &amp;frx-&gt;pbl_idx, mem_p,</div><div class='del'>-				sge-&gt;laddr + wqe-&gt;processed, bytes);</div><div class='add'>+	rv = siw_rx_data(mem_p, srx, &amp;frx-&gt;pbl_idx,</div><div class='add'>+			 sge-&gt;laddr + wqe-&gt;processed, bytes);</div><div class='ctx'> 	if (rv != bytes) {</div><div class='ctx'> 		wqe-&gt;wc_status = SIW_WC_GENERAL_ERR;</div><div class='ctx'> 		rv = -EINVAL;</div><div class='hunk'>@@ -881,6 +868,13 @@ error_term:</div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void siw_update_skb_rcvd(struct siw_rx_stream *srx, u16 length)</div><div class='add'>+{</div><div class='add'>+	srx-&gt;skb_offset += length;</div><div class='add'>+	srx-&gt;skb_new -= length;</div><div class='add'>+	srx-&gt;skb_copied += length;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int siw_proc_terminate(struct siw_qp *qp)</div><div class='ctx'> {</div><div class='ctx'> 	struct siw_rx_stream *srx = &amp;qp-&gt;rx_stream;</div><div class='hunk'>@@ -925,9 +919,7 @@ int siw_proc_terminate(struct siw_qp *qp)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	infop += to_copy;</div><div class='del'>-	srx-&gt;skb_offset += to_copy;</div><div class='del'>-	srx-&gt;skb_new -= to_copy;</div><div class='del'>-	srx-&gt;skb_copied += to_copy;</div><div class='add'>+	siw_update_skb_rcvd(srx, to_copy);</div><div class='ctx'> 	srx-&gt;fpdu_part_rcvd += to_copy;</div><div class='ctx'> 	srx-&gt;fpdu_part_rem -= to_copy;</div><div class='ctx'> </div><div class='hunk'>@@ -949,9 +941,7 @@ int siw_proc_terminate(struct siw_qp *qp)</div><div class='ctx'> 			   term-&gt;flag_m ? "valid" : "invalid");</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='del'>-	srx-&gt;skb_new -= to_copy;</div><div class='del'>-	srx-&gt;skb_offset += to_copy;</div><div class='del'>-	srx-&gt;skb_copied += to_copy;</div><div class='add'>+	siw_update_skb_rcvd(srx, to_copy);</div><div class='ctx'> 	srx-&gt;fpdu_part_rcvd += to_copy;</div><div class='ctx'> 	srx-&gt;fpdu_part_rem -= to_copy;</div><div class='ctx'> </div><div class='hunk'>@@ -970,9 +960,7 @@ static int siw_get_trailer(struct siw_qp *qp, struct siw_rx_stream *srx)</div><div class='ctx'> </div><div class='ctx'> 	skb_copy_bits(skb, srx-&gt;skb_offset, tbuf, avail);</div><div class='ctx'> </div><div class='del'>-	srx-&gt;skb_new -= avail;</div><div class='del'>-	srx-&gt;skb_offset += avail;</div><div class='del'>-	srx-&gt;skb_copied += avail;</div><div class='add'>+	siw_update_skb_rcvd(srx, avail);</div><div class='ctx'> 	srx-&gt;fpdu_part_rem -= avail;</div><div class='ctx'> </div><div class='ctx'> 	if (srx-&gt;fpdu_part_rem)</div><div class='hunk'>@@ -1023,12 +1011,8 @@ static int siw_get_hdr(struct siw_rx_stream *srx)</div><div class='ctx'> 		skb_copy_bits(skb, srx-&gt;skb_offset,</div><div class='ctx'> 			      (char *)c_hdr + srx-&gt;fpdu_part_rcvd, bytes);</div><div class='ctx'> </div><div class='add'>+		siw_update_skb_rcvd(srx, bytes);</div><div class='ctx'> 		srx-&gt;fpdu_part_rcvd += bytes;</div><div class='del'>-</div><div class='del'>-		srx-&gt;skb_new -= bytes;</div><div class='del'>-		srx-&gt;skb_offset += bytes;</div><div class='del'>-		srx-&gt;skb_copied += bytes;</div><div class='del'>-</div><div class='ctx'> 		if (srx-&gt;fpdu_part_rcvd &lt; MIN_DDP_HDR)</div><div class='ctx'> 			return -EAGAIN;</div><div class='ctx'> </div><div class='hunk'>@@ -1091,12 +1075,8 @@ static int siw_get_hdr(struct siw_rx_stream *srx)</div><div class='ctx'> 		skb_copy_bits(skb, srx-&gt;skb_offset,</div><div class='ctx'> 			      (char *)c_hdr + srx-&gt;fpdu_part_rcvd, bytes);</div><div class='ctx'> </div><div class='add'>+		siw_update_skb_rcvd(srx, bytes);</div><div class='ctx'> 		srx-&gt;fpdu_part_rcvd += bytes;</div><div class='del'>-</div><div class='del'>-		srx-&gt;skb_new -= bytes;</div><div class='del'>-		srx-&gt;skb_offset += bytes;</div><div class='del'>-		srx-&gt;skb_copied += bytes;</div><div class='del'>-</div><div class='ctx'> 		if (srx-&gt;fpdu_part_rcvd &lt; hdrlen)</div><div class='ctx'> 			return -EAGAIN;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_qp_tx.c b/drivers/infiniband/sw/siw/siw_qp_tx.c<br/>index b2c06100cf01..64ad9e0895bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_qp_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_qp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_qp_tx.c</a></div><div class='hunk'>@@ -34,6 +34,15 @@ static struct page *siw_get_pblpage(struct siw_mem *mem, u64 addr, int *idx)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct page *siw_get_page(struct siw_mem *mem, struct siw_sge *sge,</div><div class='add'>+				 unsigned long offset, int *pbl_idx)</div><div class='add'>+{</div><div class='add'>+	if (!mem-&gt;is_pbl)</div><div class='add'>+		return siw_get_upage(mem-&gt;umem, sge-&gt;laddr + offset);</div><div class='add'>+	else</div><div class='add'>+		return siw_get_pblpage(mem, sge-&gt;laddr + offset, pbl_idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Copy short payload at provided destination payload address</div><div class='ctx'>  */</div><div class='hunk'>@@ -67,11 +76,7 @@ static int siw_try_1seg(struct siw_iwarp_tx *c_tx, void *paddr)</div><div class='ctx'> 			char *buffer;</div><div class='ctx'> 			int pbl_idx = 0;</div><div class='ctx'> </div><div class='del'>-			if (!mem-&gt;is_pbl)</div><div class='del'>-				p = siw_get_upage(mem-&gt;umem, sge-&gt;laddr);</div><div class='del'>-			else</div><div class='del'>-				p = siw_get_pblpage(mem, sge-&gt;laddr, &amp;pbl_idx);</div><div class='del'>-</div><div class='add'>+			p = siw_get_page(mem, sge, 0, &amp;pbl_idx);</div><div class='ctx'> 			if (unlikely(!p))</div><div class='ctx'> 				return -EFAULT;</div><div class='ctx'> </div><div class='hunk'>@@ -85,13 +90,7 @@ static int siw_try_1seg(struct siw_iwarp_tx *c_tx, void *paddr)</div><div class='ctx'> 				memcpy(paddr, buffer + off, part);</div><div class='ctx'> 				kunmap_local(buffer);</div><div class='ctx'> </div><div class='del'>-				if (!mem-&gt;is_pbl)</div><div class='del'>-					p = siw_get_upage(mem-&gt;umem,</div><div class='del'>-							  sge-&gt;laddr + part);</div><div class='del'>-				else</div><div class='del'>-					p = siw_get_pblpage(mem,</div><div class='del'>-							    sge-&gt;laddr + part,</div><div class='del'>-							    &amp;pbl_idx);</div><div class='add'>+				p = siw_get_page(mem, sge, part, &amp;pbl_idx);</div><div class='ctx'> 				if (unlikely(!p))</div><div class='ctx'> 					return -EFAULT;</div><div class='ctx'> </div><div class='hunk'>@@ -249,14 +248,10 @@ static int siw_qp_prepare_tx(struct siw_iwarp_tx *c_tx)</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Do complete CRC if enabled and short packet</div><div class='ctx'> 		 */</div><div class='del'>-		if (c_tx-&gt;mpa_crc_hd) {</div><div class='del'>-			crypto_shash_init(c_tx-&gt;mpa_crc_hd);</div><div class='del'>-			if (crypto_shash_update(c_tx-&gt;mpa_crc_hd,</div><div class='del'>-						(u8 *)&amp;c_tx-&gt;pkt,</div><div class='del'>-						c_tx-&gt;ctrl_len))</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			crypto_shash_final(c_tx-&gt;mpa_crc_hd, (u8 *)crc);</div><div class='del'>-		}</div><div class='add'>+		if (c_tx-&gt;mpa_crc_hd &amp;&amp;</div><div class='add'>+		    crypto_shash_digest(c_tx-&gt;mpa_crc_hd, (u8 *)&amp;c_tx-&gt;pkt,</div><div class='add'>+					c_tx-&gt;ctrl_len, (u8 *)crc) != 0)</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		c_tx-&gt;ctrl_len += MPA_CRC_SIZE;</div><div class='ctx'> </div><div class='ctx'> 		return PKT_COMPLETE;</div><div class='hunk'>@@ -297,8 +292,7 @@ static int siw_tx_ctrl(struct siw_iwarp_tx *c_tx, struct socket *s,</div><div class='ctx'> 				    (char *)&amp;c_tx-&gt;pkt.ctrl + c_tx-&gt;ctrl_sent,</div><div class='ctx'> 			    .iov_len = c_tx-&gt;ctrl_len - c_tx-&gt;ctrl_sent };</div><div class='ctx'> </div><div class='del'>-	int rv = kernel_sendmsg(s, &amp;msg, &amp;iov, 1,</div><div class='del'>-				c_tx-&gt;ctrl_len - c_tx-&gt;ctrl_sent);</div><div class='add'>+	int rv = kernel_sendmsg(s, &amp;msg, &amp;iov, 1, iov.iov_len);</div><div class='ctx'> </div><div class='ctx'> 	if (rv &gt;= 0) {</div><div class='ctx'> 		c_tx-&gt;ctrl_sent += rv;</div><div class='hunk'>@@ -502,13 +496,7 @@ static int siw_tx_hdt(struct siw_iwarp_tx *c_tx, struct socket *s)</div><div class='ctx'> 			if (!is_kva) {</div><div class='ctx'> 				struct page *p;</div><div class='ctx'> </div><div class='del'>-				if (mem-&gt;is_pbl)</div><div class='del'>-					p = siw_get_pblpage(</div><div class='del'>-						mem, sge-&gt;laddr + sge_off,</div><div class='del'>-						&amp;pbl_idx);</div><div class='del'>-				else</div><div class='del'>-					p = siw_get_upage(mem-&gt;umem,</div><div class='del'>-							  sge-&gt;laddr + sge_off);</div><div class='add'>+				p = siw_get_page(mem, sge, sge_off, &amp;pbl_idx);</div><div class='ctx'> 				if (unlikely(!p)) {</div><div class='ctx'> 					siw_unmap_pages(iov, kmap_mask, seg);</div><div class='ctx'> 					wqe-&gt;processed -= c_tx-&gt;bytes_unsent;</div><div class='hunk'>@@ -1009,13 +997,12 @@ static int siw_qp_sq_proc_local(struct siw_qp *qp, struct siw_wqe *wqe)</div><div class='ctx'>  * MPA FPDUs, each containing a DDP segment.</div><div class='ctx'>  *</div><div class='ctx'>  * SQ processing may occur in user context as a result of posting</div><div class='del'>- * new WQE's or from siw_sq_work_handler() context. Processing in</div><div class='add'>+ * new WQE's or from siw_tx_thread context. Processing in</div><div class='ctx'>  * user context is limited to non-kernel verbs users.</div><div class='ctx'>  *</div><div class='ctx'>  * SQ processing may get paused anytime, possibly in the middle of a WR</div><div class='ctx'>  * or FPDU, if insufficient send space is available. SQ processing</div><div class='del'>- * gets resumed from siw_sq_work_handler(), if send space becomes</div><div class='del'>- * available again.</div><div class='add'>+ * gets resumed from siw_tx_thread, if send space becomes available again.</div><div class='ctx'>  *</div><div class='ctx'>  * Must be called with the QP state read-locked.</div><div class='ctx'>  *</div><div class='head'>diff --git a/drivers/infiniband/sw/siw/siw_verbs.c b/drivers/infiniband/sw/siw/siw_verbs.c<br/>index c5c27db9c2fe..ecf0444666b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/sw/siw/siw_verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/sw/siw/siw_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/sw/siw/siw_verbs.c</a></div><div class='hunk'>@@ -19,6 +19,15 @@</div><div class='ctx'> #include "siw_verbs.h"</div><div class='ctx'> #include "siw_mem.h"</div><div class='ctx'> </div><div class='add'>+static int siw_qp_state_to_ib_qp_state[SIW_QP_STATE_COUNT] = {</div><div class='add'>+	[SIW_QP_STATE_IDLE] = IB_QPS_INIT,</div><div class='add'>+	[SIW_QP_STATE_RTR] = IB_QPS_RTR,</div><div class='add'>+	[SIW_QP_STATE_RTS] = IB_QPS_RTS,</div><div class='add'>+	[SIW_QP_STATE_CLOSING] = IB_QPS_SQD,</div><div class='add'>+	[SIW_QP_STATE_TERMINATE] = IB_QPS_SQE,</div><div class='add'>+	[SIW_QP_STATE_ERROR] = IB_QPS_ERR</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ib_qp_state_to_siw_qp_state[IB_QPS_ERR + 1] = {</div><div class='ctx'> 	[IB_QPS_RESET] = SIW_QP_STATE_IDLE,</div><div class='ctx'> 	[IB_QPS_INIT] = SIW_QP_STATE_IDLE,</div><div class='hunk'>@@ -66,12 +75,9 @@ int siw_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma)</div><div class='ctx'> 	entry = to_siw_mmap_entry(rdma_entry);</div><div class='ctx'> </div><div class='ctx'> 	rv = remap_vmalloc_range(vma, entry-&gt;address, 0);</div><div class='del'>-	if (rv) {</div><div class='add'>+	if (rv)</div><div class='ctx'> 		pr_warn("remap_vmalloc_range failed: %lu, %zu\n", vma-&gt;vm_pgoff,</div><div class='ctx'> 			size);</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-out:</div><div class='ctx'> 	rdma_user_mmap_entry_put(rdma_entry);</div><div class='ctx'> </div><div class='ctx'> 	return rv;</div><div class='hunk'>@@ -336,11 +342,10 @@ int siw_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,</div><div class='ctx'> 		goto err_atomic;</div><div class='ctx'> 	}</div><div class='ctx'> 	/*</div><div class='del'>-	 * NOTE: we allow for zero element SQ and RQ WQE's SGL's</div><div class='del'>-	 * but not for a QP unable to hold any WQE (SQ + RQ)</div><div class='add'>+	 * NOTE: we don't allow for a QP unable to hold any SQ WQE</div><div class='ctx'> 	 */</div><div class='del'>-	if (attrs-&gt;cap.max_send_wr + attrs-&gt;cap.max_recv_wr == 0) {</div><div class='del'>-		siw_dbg(base_dev, "QP must have send or receive queue\n");</div><div class='add'>+	if (attrs-&gt;cap.max_send_wr == 0) {</div><div class='add'>+		siw_dbg(base_dev, "QP must have send queue\n");</div><div class='ctx'> 		rv = -EINVAL;</div><div class='ctx'> 		goto err_atomic;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -360,21 +365,14 @@ int siw_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,</div><div class='ctx'> 	if (rv)</div><div class='ctx'> 		goto err_atomic;</div><div class='ctx'> </div><div class='del'>-	num_sqe = attrs-&gt;cap.max_send_wr;</div><div class='del'>-	num_rqe = attrs-&gt;cap.max_recv_wr;</div><div class='ctx'> </div><div class='ctx'> 	/* All queue indices are derived from modulo operations</div><div class='ctx'> 	 * on a free running 'get' (consumer) and 'put' (producer)</div><div class='ctx'> 	 * unsigned counter. Having queue sizes at power of two</div><div class='ctx'> 	 * avoids handling counter wrap around.</div><div class='ctx'> 	 */</div><div class='del'>-	if (num_sqe)</div><div class='del'>-		num_sqe = roundup_pow_of_two(num_sqe);</div><div class='del'>-	else {</div><div class='del'>-		/* Zero sized SQ is not supported */</div><div class='del'>-		rv = -EINVAL;</div><div class='del'>-		goto err_out_xa;</div><div class='del'>-	}</div><div class='add'>+	num_sqe = roundup_pow_of_two(attrs-&gt;cap.max_send_wr);</div><div class='add'>+	num_rqe = attrs-&gt;cap.max_recv_wr;</div><div class='ctx'> 	if (num_rqe)</div><div class='ctx'> 		num_rqe = roundup_pow_of_two(num_rqe);</div><div class='ctx'> </div><div class='hunk'>@@ -515,6 +513,7 @@ int siw_query_qp(struct ib_qp *base_qp, struct ib_qp_attr *qp_attr,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='add'>+	qp_attr-&gt;qp_state = siw_qp_state_to_ib_qp_state[qp-&gt;attrs.state];</div><div class='ctx'> 	qp_attr-&gt;cap.max_inline_data = SIW_MAX_INLINE;</div><div class='ctx'> 	qp_attr-&gt;cap.max_send_wr = qp-&gt;attrs.sq_size;</div><div class='ctx'> 	qp_attr-&gt;cap.max_send_sge = qp-&gt;attrs.sq_max_sges;</div><div class='hunk'>@@ -1321,8 +1320,6 @@ struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,</div><div class='ctx'> 	struct siw_umem *umem = NULL;</div><div class='ctx'> 	struct siw_ureq_reg_mr ureq;</div><div class='ctx'> 	struct siw_device *sdev = to_siw_dev(pd-&gt;device);</div><div class='del'>-</div><div class='del'>-	unsigned long mem_limit = rlimit(RLIMIT_MEMLOCK);</div><div class='ctx'> 	int rv;</div><div class='ctx'> </div><div class='ctx'> 	siw_dbg_pd(pd, "start: 0x%pK, va: 0x%pK, len: %llu\n",</div><div class='hunk'>@@ -1338,20 +1335,7 @@ struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,</div><div class='ctx'> 		rv = -EINVAL;</div><div class='ctx'> 		goto err_out;</div><div class='ctx'> 	}</div><div class='del'>-	if (mem_limit != RLIM_INFINITY) {</div><div class='del'>-		unsigned long num_pages =</div><div class='del'>-			(PAGE_ALIGN(len + (start &amp; ~PAGE_MASK))) &gt;&gt; PAGE_SHIFT;</div><div class='del'>-		mem_limit &gt;&gt;= PAGE_SHIFT;</div><div class='del'>-</div><div class='del'>-		if (num_pages &gt; mem_limit - current-&gt;mm-&gt;locked_vm) {</div><div class='del'>-			siw_dbg_pd(pd, "pages req %lu, max %lu, lock %lu\n",</div><div class='del'>-				   num_pages, mem_limit,</div><div class='del'>-				   current-&gt;mm-&gt;locked_vm);</div><div class='del'>-			rv = -ENOMEM;</div><div class='del'>-			goto err_out;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	umem = siw_umem_get(start, len, ib_access_writable(rights));</div><div class='add'>+	umem = siw_umem_get(pd-&gt;device, start, len, rights);</div><div class='ctx'> 	if (IS_ERR(umem)) {</div><div class='ctx'> 		rv = PTR_ERR(umem);</div><div class='ctx'> 		siw_dbg_pd(pd, "getting user memory failed: %d\n", rv);</div><div class='hunk'>@@ -1404,7 +1388,7 @@ err_out:</div><div class='ctx'> 		kfree_rcu(mr, rcu);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (umem)</div><div class='del'>-			siw_umem_release(umem, false);</div><div class='add'>+			siw_umem_release(umem);</div><div class='ctx'> 	}</div><div class='ctx'> 	return ERR_PTR(rv);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/ulp/ipoib/ipoib.h b/drivers/infiniband/ulp/ipoib/ipoib.h<br/>index 35e9c8a330e2..963e936da5e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/ipoib/ipoib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib.h</a></div><div class='hunk'>@@ -351,10 +351,12 @@ struct ipoib_dev_priv {</div><div class='ctx'> 	struct workqueue_struct *wq;</div><div class='ctx'> 	struct delayed_work mcast_task;</div><div class='ctx'> 	struct work_struct carrier_on_task;</div><div class='add'>+	struct work_struct reschedule_napi_work;</div><div class='ctx'> 	struct work_struct flush_light;</div><div class='ctx'> 	struct work_struct flush_normal;</div><div class='ctx'> 	struct work_struct flush_heavy;</div><div class='ctx'> 	struct work_struct restart_task;</div><div class='add'>+	struct work_struct tx_timeout_work;</div><div class='ctx'> 	struct delayed_work ah_reap_task;</div><div class='ctx'> 	struct delayed_work neigh_reap_task;</div><div class='ctx'> 	struct ib_device *ca;</div><div class='hunk'>@@ -499,6 +501,7 @@ int ipoib_send(struct net_device *dev, struct sk_buff *skb,</div><div class='ctx'> 	       struct ib_ah *address, u32 dqpn);</div><div class='ctx'> void ipoib_reap_ah(struct work_struct *work);</div><div class='ctx'> </div><div class='add'>+void ipoib_napi_schedule_work(struct work_struct *work);</div><div class='ctx'> struct ipoib_path *__path_find(struct net_device *dev, void *gid);</div><div class='ctx'> void ipoib_mark_paths_invalid(struct net_device *dev);</div><div class='ctx'> void ipoib_flush_paths(struct net_device *dev);</div><div class='hunk'>@@ -510,6 +513,7 @@ void ipoib_ib_tx_timer_func(struct timer_list *t);</div><div class='ctx'> void ipoib_ib_dev_flush_light(struct work_struct *work);</div><div class='ctx'> void ipoib_ib_dev_flush_normal(struct work_struct *work);</div><div class='ctx'> void ipoib_ib_dev_flush_heavy(struct work_struct *work);</div><div class='add'>+void ipoib_ib_tx_timeout_work(struct work_struct *work);</div><div class='ctx'> void ipoib_pkey_event(struct work_struct *work);</div><div class='ctx'> void ipoib_ib_dev_cleanup(struct net_device *dev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c<br/>index 7f84d9866cef..5cde275daa94 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_ib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/ipoib/ipoib_ib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_ib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_ib.c</a></div><div class='hunk'>@@ -531,11 +531,35 @@ void ipoib_ib_rx_completion(struct ib_cq *cq, void *ctx_ptr)</div><div class='ctx'> 	napi_schedule(&amp;priv-&gt;recv_napi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* The function will force napi_schedule */</div><div class='add'>+void ipoib_napi_schedule_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct ipoib_dev_priv *priv =</div><div class='add'>+		container_of(work, struct ipoib_dev_priv, reschedule_napi_work);</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = napi_schedule(&amp;priv-&gt;send_napi);</div><div class='add'>+		if (!ret)</div><div class='add'>+			msleep(3);</div><div class='add'>+	} while (!ret &amp;&amp; netif_queue_stopped(priv-&gt;dev) &amp;&amp;</div><div class='add'>+		 test_bit(IPOIB_FLAG_INITIALIZED, &amp;priv-&gt;flags));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void ipoib_ib_tx_completion(struct ib_cq *cq, void *ctx_ptr)</div><div class='ctx'> {</div><div class='ctx'> 	struct ipoib_dev_priv *priv = ctx_ptr;</div><div class='add'>+	bool ret;</div><div class='ctx'> </div><div class='del'>-	napi_schedule(&amp;priv-&gt;send_napi);</div><div class='add'>+	ret = napi_schedule(&amp;priv-&gt;send_napi);</div><div class='add'>+	/*</div><div class='add'>+	 * if the queue is closed the driver must be able to schedule napi,</div><div class='add'>+	 * otherwise we can end with closed queue forever, because no new</div><div class='add'>+	 * packets to send and napi callback might not get new event after</div><div class='add'>+	 * its re-arm of the napi.</div><div class='add'>+	 */</div><div class='add'>+	if (!ret &amp;&amp; netif_queue_stopped(priv-&gt;dev))</div><div class='add'>+		schedule_work(&amp;priv-&gt;reschedule_napi_work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int post_send(struct ipoib_dev_priv *priv,</div><div class='head'>diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c<br/>index 967004ccad98..7a5be705d718 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/ipoib/ipoib_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_main.c</a></div><div class='hunk'>@@ -1200,7 +1200,34 @@ static void ipoib_timeout(struct net_device *dev, unsigned int txqueue)</div><div class='ctx'> 		   netif_queue_stopped(dev), priv-&gt;tx_head, priv-&gt;tx_tail,</div><div class='ctx'> 		   priv-&gt;global_tx_head, priv-&gt;global_tx_tail);</div><div class='ctx'> </div><div class='del'>-	/* XXX reset QP, etc. */</div><div class='add'>+</div><div class='add'>+	schedule_work(&amp;priv-&gt;tx_timeout_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ipoib_ib_tx_timeout_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct ipoib_dev_priv *priv = container_of(work,</div><div class='add'>+						   struct ipoib_dev_priv,</div><div class='add'>+						   tx_timeout_work);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	rtnl_lock();</div><div class='add'>+</div><div class='add'>+	if (!test_bit(IPOIB_FLAG_ADMIN_UP, &amp;priv-&gt;flags))</div><div class='add'>+		goto unlock;</div><div class='add'>+</div><div class='add'>+	ipoib_stop(priv-&gt;dev);</div><div class='add'>+	err = ipoib_open(priv-&gt;dev);</div><div class='add'>+	if (err) {</div><div class='add'>+		ipoib_warn(priv, "ipoib_open failed recovering from a tx_timeout, err(%d).\n",</div><div class='add'>+				err);</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	netif_tx_wake_all_queues(priv-&gt;dev);</div><div class='add'>+unlock:</div><div class='add'>+	rtnl_unlock();</div><div class='add'>+</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ipoib_hard_header(struct sk_buff *skb,</div><div class='hunk'>@@ -2112,7 +2139,7 @@ void ipoib_setup_common(struct net_device *dev)</div><div class='ctx'> </div><div class='ctx'> 	ipoib_set_ethtool_ops(dev);</div><div class='ctx'> </div><div class='del'>-	dev-&gt;watchdog_timeo	 = HZ;</div><div class='add'>+	dev-&gt;watchdog_timeo	 = 10 * HZ;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;flags		|= IFF_BROADCAST | IFF_MULTICAST;</div><div class='ctx'> </div><div class='hunk'>@@ -2150,10 +2177,12 @@ static void ipoib_build_priv(struct net_device *dev)</div><div class='ctx'> </div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;priv-&gt;mcast_task,   ipoib_mcast_join_task);</div><div class='ctx'> 	INIT_WORK(&amp;priv-&gt;carrier_on_task, ipoib_mcast_carrier_on_task);</div><div class='add'>+	INIT_WORK(&amp;priv-&gt;reschedule_napi_work, ipoib_napi_schedule_work);</div><div class='ctx'> 	INIT_WORK(&amp;priv-&gt;flush_light,   ipoib_ib_dev_flush_light);</div><div class='ctx'> 	INIT_WORK(&amp;priv-&gt;flush_normal,   ipoib_ib_dev_flush_normal);</div><div class='ctx'> 	INIT_WORK(&amp;priv-&gt;flush_heavy,   ipoib_ib_dev_flush_heavy);</div><div class='ctx'> 	INIT_WORK(&amp;priv-&gt;restart_task, ipoib_mcast_restart_task);</div><div class='add'>+	INIT_WORK(&amp;priv-&gt;tx_timeout_work, ipoib_ib_tx_timeout_work);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;priv-&gt;ah_reap_task, ipoib_reap_ah);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;priv-&gt;neigh_reap_task, ipoib_reap_neigh);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c<br/>index 5b3154503bf4..319d4288eddd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_multicast.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/ipoib/ipoib_multicast.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/ipoib/ipoib_multicast.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/ipoib/ipoib_multicast.c</a></div><div class='hunk'>@@ -531,21 +531,18 @@ static int ipoib_mcast_join(struct net_device *dev, struct ipoib_mcast *mcast)</div><div class='ctx'> 		if (test_bit(IPOIB_MCAST_FLAG_SENDONLY, &amp;mcast-&gt;flags))</div><div class='ctx'> 			rec.join_state = SENDONLY_FULLMEMBER_JOIN;</div><div class='ctx'> 	}</div><div class='del'>-	spin_unlock_irq(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	multicast = ib_sa_join_multicast(&amp;ipoib_sa_client, priv-&gt;ca, priv-&gt;port,</div><div class='del'>-					 &amp;rec, comp_mask, GFP_KERNEL,</div><div class='add'>+					 &amp;rec, comp_mask, GFP_ATOMIC,</div><div class='ctx'> 					 ipoib_mcast_join_complete, mcast);</div><div class='del'>-	spin_lock_irq(&amp;priv-&gt;lock);</div><div class='ctx'> 	if (IS_ERR(multicast)) {</div><div class='ctx'> 		ret = PTR_ERR(multicast);</div><div class='ctx'> 		ipoib_warn(priv, "ib_sa_join_multicast failed, status %d\n", ret);</div><div class='ctx'> 		/* Requeue this join task with a backoff delay */</div><div class='ctx'> 		__ipoib_mcast_schedule_join_thread(priv, mcast, 1);</div><div class='ctx'> 		clear_bit(IPOIB_MCAST_FLAG_BUSY, &amp;mcast-&gt;flags);</div><div class='del'>-		spin_unlock_irq(&amp;priv-&gt;lock);</div><div class='ctx'> 		complete(&amp;mcast-&gt;done);</div><div class='del'>-		spin_lock_irq(&amp;priv-&gt;lock);</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h<br/>index dee8c97ff056..68429a5f796d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iscsi_iser.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/iser/iscsi_iser.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iscsi_iser.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iscsi_iser.h</a></div><div class='hunk'>@@ -182,7 +182,7 @@ enum iser_data_dir {</div><div class='ctx'>  *</div><div class='ctx'>  * @sg:           pointer to the sg list</div><div class='ctx'>  * @size:         num entries of this sg</div><div class='del'>- * @data_len:     total beffer byte len</div><div class='add'>+ * @data_len:     total buffer byte len</div><div class='ctx'>  * @dma_nents:    returned by dma_map_sg</div><div class='ctx'>  */</div><div class='ctx'> struct iser_data_buf {</div><div class='hunk'>@@ -299,7 +299,6 @@ struct ib_conn;</div><div class='ctx'>  *</div><div class='ctx'>  * @ib_device:     RDMA device</div><div class='ctx'>  * @pd:            Protection Domain for this device</div><div class='del'>- * @mr:            Global DMA memory region</div><div class='ctx'>  * @event_handler: IB events handle routine</div><div class='ctx'>  * @ig_list:	   entry in devices list</div><div class='ctx'>  * @refcount:      Reference counter, dominated by open iser connections</div><div class='hunk'>@@ -317,12 +316,10 @@ struct iser_device {</div><div class='ctx'>  *</div><div class='ctx'>  * @mr:         memory region</div><div class='ctx'>  * @sig_mr:     signature memory region</div><div class='del'>- * @mr_valid:   is mr valid indicator</div><div class='ctx'>  */</div><div class='ctx'> struct iser_reg_resources {</div><div class='ctx'> 	struct ib_mr                     *mr;</div><div class='ctx'> 	struct ib_mr                     *sig_mr;</div><div class='del'>-	u8				  mr_valid:1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -389,7 +386,7 @@ struct ib_conn {</div><div class='ctx'>  *                    to max number of post recvs</div><div class='ctx'>  * @max_cmds:         maximum cmds allowed for this connection</div><div class='ctx'>  * @name:             connection peer portal</div><div class='del'>- * @release_work:     deffered work for release job</div><div class='add'>+ * @release_work:     deferred work for release job</div><div class='ctx'>  * @state_mutex:      protects iser onnection state</div><div class='ctx'>  * @stop_completion:  conn_stop completion</div><div class='ctx'>  * @ib_completion:    RDMA cleanup completion</div><div class='head'>diff --git a/drivers/infiniband/ulp/iser/iser_initiator.c b/drivers/infiniband/ulp/iser/iser_initiator.c<br/>index 39ea73f69016..f5f090dc4f1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_initiator.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/iser/iser_initiator.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_initiator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_initiator.c</a></div><div class='hunk'>@@ -581,7 +581,10 @@ static inline int iser_inv_desc(struct iser_fr_desc *desc, u32 rkey)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	desc-&gt;rsc.mr_valid = 0;</div><div class='add'>+	if (desc-&gt;sig_protected)</div><div class='add'>+		desc-&gt;rsc.sig_mr-&gt;need_inval = false;</div><div class='add'>+	else</div><div class='add'>+		desc-&gt;rsc.mr-&gt;need_inval = false;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/infiniband/ulp/iser/iser_memory.c b/drivers/infiniband/ulp/iser/iser_memory.c<br/>index 29ae2c6a250a..6efcb79c8efe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_memory.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/iser/iser_memory.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_memory.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_memory.c</a></div><div class='hunk'>@@ -264,7 +264,7 @@ static int iser_reg_sig_mr(struct iscsi_iser_task *iser_task,</div><div class='ctx'> </div><div class='ctx'> 	iser_set_prot_checks(iser_task-&gt;sc, &amp;sig_attrs-&gt;check_mask);</div><div class='ctx'> </div><div class='del'>-	if (rsc-&gt;mr_valid)</div><div class='add'>+	if (rsc-&gt;sig_mr-&gt;need_inval)</div><div class='ctx'> 		iser_inv_rkey(&amp;tx_desc-&gt;inv_wr, mr, cqe, &amp;wr-&gt;wr);</div><div class='ctx'> </div><div class='ctx'> 	ib_update_fast_reg_key(mr, ib_inc_rkey(mr-&gt;rkey));</div><div class='hunk'>@@ -288,7 +288,7 @@ static int iser_reg_sig_mr(struct iscsi_iser_task *iser_task,</div><div class='ctx'> 	wr-&gt;access = IB_ACCESS_LOCAL_WRITE |</div><div class='ctx'> 		     IB_ACCESS_REMOTE_READ |</div><div class='ctx'> 		     IB_ACCESS_REMOTE_WRITE;</div><div class='del'>-	rsc-&gt;mr_valid = 1;</div><div class='add'>+	rsc-&gt;sig_mr-&gt;need_inval = true;</div><div class='ctx'> </div><div class='ctx'> 	sig_reg-&gt;sge.lkey = mr-&gt;lkey;</div><div class='ctx'> 	sig_reg-&gt;rkey = mr-&gt;rkey;</div><div class='hunk'>@@ -313,7 +313,7 @@ static int iser_fast_reg_mr(struct iscsi_iser_task *iser_task,</div><div class='ctx'> 	struct ib_reg_wr *wr = &amp;tx_desc-&gt;reg_wr;</div><div class='ctx'> 	int n;</div><div class='ctx'> </div><div class='del'>-	if (rsc-&gt;mr_valid)</div><div class='add'>+	if (rsc-&gt;mr-&gt;need_inval)</div><div class='ctx'> 		iser_inv_rkey(&amp;tx_desc-&gt;inv_wr, mr, cqe, &amp;wr-&gt;wr);</div><div class='ctx'> </div><div class='ctx'> 	ib_update_fast_reg_key(mr, ib_inc_rkey(mr-&gt;rkey));</div><div class='hunk'>@@ -336,7 +336,7 @@ static int iser_fast_reg_mr(struct iscsi_iser_task *iser_task,</div><div class='ctx'> 		     IB_ACCESS_REMOTE_WRITE |</div><div class='ctx'> 		     IB_ACCESS_REMOTE_READ;</div><div class='ctx'> </div><div class='del'>-	rsc-&gt;mr_valid = 1;</div><div class='add'>+	rsc-&gt;mr-&gt;need_inval = true;</div><div class='ctx'> </div><div class='ctx'> 	reg-&gt;sge.lkey = mr-&gt;lkey;</div><div class='ctx'> 	reg-&gt;rkey = mr-&gt;rkey;</div><div class='head'>diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c<br/>index 95b8eebf7e04..6801b70dc9e0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_verbs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/iser/iser_verbs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/iser/iser_verbs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/iser/iser_verbs.c</a></div><div class='hunk'>@@ -129,7 +129,6 @@ iser_create_fastreg_desc(struct iser_device *device,</div><div class='ctx'> 			goto err_alloc_mr_integrity;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	desc-&gt;rsc.mr_valid = 0;</div><div class='ctx'> </div><div class='ctx'> 	return desc;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/ulp/rtrs/rtrs-clt.c b/drivers/infiniband/ulp/rtrs/rtrs-clt.c<br/>index 07261523c554..88106cf5ce55 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs-clt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/rtrs/rtrs-clt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs-clt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs-clt.c</a></div><div class='hunk'>@@ -384,7 +384,7 @@ static void complete_rdma_req(struct rtrs_clt_io_req *req, int errno,</div><div class='ctx'> 	struct rtrs_clt_path *clt_path;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON(!req-&gt;in_use))</div><div class='add'>+	if (!req-&gt;in_use)</div><div class='ctx'> 		return;</div><div class='ctx'> 	if (WARN_ON(!req-&gt;con))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -1391,9 +1391,9 @@ static int alloc_path_reqs(struct rtrs_clt_path *clt_path)</div><div class='ctx'> 				      clt_path-&gt;max_pages_per_mr);</div><div class='ctx'> 		if (IS_ERR(req-&gt;mr)) {</div><div class='ctx'> 			err = PTR_ERR(req-&gt;mr);</div><div class='add'>+			pr_err("Failed to alloc clt_path-&gt;max_pages_per_mr %d: %pe\n",</div><div class='add'>+			       clt_path-&gt;max_pages_per_mr, req-&gt;mr);</div><div class='ctx'> 			req-&gt;mr = NULL;</div><div class='del'>-			pr_err("Failed to alloc clt_path-&gt;max_pages_per_mr %d\n",</div><div class='del'>-			       clt_path-&gt;max_pages_per_mr);</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1699,7 +1699,7 @@ static int create_con_cq_qp(struct rtrs_clt_con *con)</div><div class='ctx'> 		clt_path-&gt;s.dev_ref++;</div><div class='ctx'> 		max_send_wr = min_t(int, wr_limit,</div><div class='ctx'> 			      /* QD * (REQ + RSP + FR REGS or INVS) + drain */</div><div class='del'>-			      clt_path-&gt;queue_depth * 3 + 1);</div><div class='add'>+			      clt_path-&gt;queue_depth * 4 + 1);</div><div class='ctx'> 		max_recv_wr = min_t(int, wr_limit,</div><div class='ctx'> 			      clt_path-&gt;queue_depth * 3 + 1);</div><div class='ctx'> 		max_send_sge = 2;</div><div class='hunk'>@@ -2025,6 +2025,8 @@ static int rtrs_clt_rdma_cm_handler(struct rdma_cm_id *cm_id,</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Device removal is a special case.  Queue close and return 0.</div><div class='ctx'> 		 */</div><div class='add'>+		rtrs_wrn_rl(s, "CM event: %s, status: %d\n", rdma_event_msg(ev-&gt;event),</div><div class='add'>+			    ev-&gt;status);</div><div class='ctx'> 		rtrs_clt_close_conns(clt_path, false);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -2058,10 +2060,8 @@ static int create_cm(struct rtrs_clt_con *con)</div><div class='ctx'> 			       clt_path-&gt;s.dst_addr.ss_family == AF_IB ?</div><div class='ctx'> 			       RDMA_PS_IB : RDMA_PS_TCP, IB_QPT_RC);</div><div class='ctx'> 	if (IS_ERR(cm_id)) {</div><div class='del'>-		err = PTR_ERR(cm_id);</div><div class='del'>-		rtrs_err(s, "Failed to create CM ID, err: %d\n", err);</div><div class='del'>-</div><div class='del'>-		return err;</div><div class='add'>+		rtrs_err(s, "Failed to create CM ID, err: %pe\n", cm_id);</div><div class='add'>+		return PTR_ERR(cm_id);</div><div class='ctx'> 	}</div><div class='ctx'> 	con-&gt;c.cm_id = cm_id;</div><div class='ctx'> 	con-&gt;cm_err = 0;</div><div class='hunk'>@@ -2350,8 +2350,6 @@ static int init_conns(struct rtrs_clt_path *clt_path)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto destroy;</div><div class='ctx'> </div><div class='del'>-	rtrs_start_hb(&amp;clt_path-&gt;s);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> destroy:</div><div class='hunk'>@@ -2625,6 +2623,7 @@ static int init_path(struct rtrs_clt_path *clt_path)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	rtrs_clt_path_up(clt_path);</div><div class='add'>+	rtrs_start_hb(&amp;clt_path-&gt;s);</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;clt_path-&gt;init_mutex);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/ulp/rtrs/rtrs-srv.c b/drivers/infiniband/ulp/rtrs/rtrs-srv.c<br/>index 75e56604e462..1d33efb8fb03 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs-srv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/rtrs/rtrs-srv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs-srv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs-srv.c</a></div><div class='hunk'>@@ -65,8 +65,9 @@ static bool rtrs_srv_change_state(struct rtrs_srv_path *srv_path,</div><div class='ctx'> {</div><div class='ctx'> 	enum rtrs_srv_state old_state;</div><div class='ctx'> 	bool changed = false;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irq(&amp;srv_path-&gt;state_lock);</div><div class='add'>+	spin_lock_irqsave(&amp;srv_path-&gt;state_lock, flags);</div><div class='ctx'> 	old_state = srv_path-&gt;state;</div><div class='ctx'> 	switch (new_state) {</div><div class='ctx'> 	case RTRS_SRV_CONNECTED:</div><div class='hunk'>@@ -87,7 +88,7 @@ static bool rtrs_srv_change_state(struct rtrs_srv_path *srv_path,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (changed)</div><div class='ctx'> 		srv_path-&gt;state = new_state;</div><div class='del'>-	spin_unlock_irq(&amp;srv_path-&gt;state_lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;srv_path-&gt;state_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	return changed;</div><div class='ctx'> }</div><div class='hunk'>@@ -550,7 +551,10 @@ static void unmap_cont_bufs(struct rtrs_srv_path *srv_path)</div><div class='ctx'> 		struct rtrs_srv_mr *srv_mr;</div><div class='ctx'> </div><div class='ctx'> 		srv_mr = &amp;srv_path-&gt;mrs[i];</div><div class='del'>-		rtrs_iu_free(srv_mr-&gt;iu, srv_path-&gt;s.dev-&gt;ib_dev, 1);</div><div class='add'>+</div><div class='add'>+		if (always_invalidate)</div><div class='add'>+			rtrs_iu_free(srv_mr-&gt;iu, srv_path-&gt;s.dev-&gt;ib_dev, 1);</div><div class='add'>+</div><div class='ctx'> 		ib_dereg_mr(srv_mr-&gt;mr);</div><div class='ctx'> 		ib_dma_unmap_sg(srv_path-&gt;s.dev-&gt;ib_dev, srv_mr-&gt;sgt.sgl,</div><div class='ctx'> 				srv_mr-&gt;sgt.nents, DMA_BIDIRECTIONAL);</div><div class='hunk'>@@ -709,20 +713,23 @@ static void rtrs_srv_info_rsp_done(struct ib_cq *cq, struct ib_wc *wc)</div><div class='ctx'> 	WARN_ON(wc-&gt;opcode != IB_WC_SEND);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rtrs_srv_path_up(struct rtrs_srv_path *srv_path)</div><div class='add'>+static int rtrs_srv_path_up(struct rtrs_srv_path *srv_path)</div><div class='ctx'> {</div><div class='ctx'> 	struct rtrs_srv_sess *srv = srv_path-&gt;srv;</div><div class='ctx'> 	struct rtrs_srv_ctx *ctx = srv-&gt;ctx;</div><div class='del'>-	int up;</div><div class='add'>+	int up, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;srv-&gt;paths_ev_mutex);</div><div class='ctx'> 	up = ++srv-&gt;paths_up;</div><div class='ctx'> 	if (up == 1)</div><div class='del'>-		ctx-&gt;ops.link_ev(srv, RTRS_SRV_LINK_EV_CONNECTED, NULL);</div><div class='add'>+		ret = ctx-&gt;ops.link_ev(srv, RTRS_SRV_LINK_EV_CONNECTED, NULL);</div><div class='ctx'> 	mutex_unlock(&amp;srv-&gt;paths_ev_mutex);</div><div class='ctx'> </div><div class='ctx'> 	/* Mark session as established */</div><div class='del'>-	srv_path-&gt;established = true;</div><div class='add'>+	if (!ret)</div><div class='add'>+		srv_path-&gt;established = true;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rtrs_srv_path_down(struct rtrs_srv_path *srv_path)</div><div class='hunk'>@@ -851,7 +858,12 @@ static int process_info_req(struct rtrs_srv_con *con,</div><div class='ctx'> 		goto iu_free;</div><div class='ctx'> 	kobject_get(&amp;srv_path-&gt;kobj);</div><div class='ctx'> 	get_device(&amp;srv_path-&gt;srv-&gt;dev);</div><div class='del'>-	rtrs_srv_change_state(srv_path, RTRS_SRV_CONNECTED);</div><div class='add'>+	err = rtrs_srv_change_state(srv_path, RTRS_SRV_CONNECTED);</div><div class='add'>+	if (!err) {</div><div class='add'>+		rtrs_err(s, "rtrs_srv_change_state(), err: %d\n", err);</div><div class='add'>+		goto iu_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rtrs_srv_start_hb(srv_path);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -860,7 +872,11 @@ static int process_info_req(struct rtrs_srv_con *con,</div><div class='ctx'> 	 * all connections are successfully established.  Thus, simply notify</div><div class='ctx'> 	 * listener with a proper event if we are the first path.</div><div class='ctx'> 	 */</div><div class='del'>-	rtrs_srv_path_up(srv_path);</div><div class='add'>+	err = rtrs_srv_path_up(srv_path);</div><div class='add'>+	if (err) {</div><div class='add'>+		rtrs_err(s, "rtrs_srv_path_up(), err: %d\n", err);</div><div class='add'>+		goto iu_free;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ib_dma_sync_single_for_device(srv_path-&gt;s.dev-&gt;ib_dev,</div><div class='ctx'> 				      tx_iu-&gt;dma_addr,</div><div class='hunk'>@@ -1516,7 +1532,6 @@ static void rtrs_srv_close_work(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	srv_path = container_of(work, typeof(*srv_path), close_work);</div><div class='ctx'> </div><div class='del'>-	rtrs_srv_destroy_path_files(srv_path);</div><div class='ctx'> 	rtrs_srv_stop_hb(srv_path);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; srv_path-&gt;s.con_num; i++) {</div><div class='hunk'>@@ -1536,6 +1551,8 @@ static void rtrs_srv_close_work(struct work_struct *work)</div><div class='ctx'> 	/* Wait for all completion */</div><div class='ctx'> 	wait_for_completion(&amp;srv_path-&gt;complete_done);</div><div class='ctx'> </div><div class='add'>+	rtrs_srv_destroy_path_files(srv_path);</div><div class='add'>+</div><div class='ctx'> 	/* Notify upper layer if we are the last path */</div><div class='ctx'> 	rtrs_srv_path_down(srv_path);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/infiniband/ulp/rtrs/rtrs.c b/drivers/infiniband/ulp/rtrs/rtrs.c<br/>index d80edfffd2e4..4e17d546d4cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/infiniband/ulp/rtrs/rtrs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/infiniband/ulp/rtrs/rtrs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/infiniband/ulp/rtrs/rtrs.c</a></div><div class='hunk'>@@ -242,8 +242,8 @@ static int create_cq(struct rtrs_con *con, int cq_vector, int nr_cqe,</div><div class='ctx'> 		cq = ib_cq_pool_get(cm_id-&gt;device, nr_cqe, cq_vector, poll_ctx);</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ERR(cq)) {</div><div class='del'>-		rtrs_err(con-&gt;path, "Creating completion queue failed, errno: %ld\n",</div><div class='del'>-			  PTR_ERR(cq));</div><div class='add'>+		rtrs_err(con-&gt;path, "Creating completion queue failed, errno: %pe\n",</div><div class='add'>+			  cq);</div><div class='ctx'> 		return PTR_ERR(cq);</div><div class='ctx'> 	}</div><div class='ctx'> 	con-&gt;cq = cq;</div><div class='head'>diff --git a/drivers/input/input.c b/drivers/input/input.c<br/>index 8c5fdb0f858a..f71ea4fb173f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/input.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/input.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/input.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/input.c</a></div><div class='hunk'>@@ -1365,8 +1365,8 @@ static ssize_t input_dev_show_##name(struct device *dev,		\</div><div class='ctx'> {									\</div><div class='ctx'> 	struct input_dev *input_dev = to_input_dev(dev);		\</div><div class='ctx'> 									\</div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%s\n",			\</div><div class='del'>-			 input_dev-&gt;name ? input_dev-&gt;name : "");	\</div><div class='add'>+	return sysfs_emit(buf, "%s\n",					\</div><div class='add'>+			  input_dev-&gt;name ? input_dev-&gt;name : "");	\</div><div class='ctx'> }									\</div><div class='ctx'> static DEVICE_ATTR(name, S_IRUGO, input_dev_show_##name, NULL)</div><div class='ctx'> </div><div class='hunk'>@@ -1458,7 +1458,7 @@ static ssize_t inhibited_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct input_dev *input_dev = to_input_dev(dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%d\n", input_dev-&gt;inhibited);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", input_dev-&gt;inhibited);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t inhibited_store(struct device *dev,</div><div class='hunk'>@@ -1505,7 +1505,7 @@ static ssize_t input_dev_show_id_##name(struct device *dev,		\</div><div class='ctx'> 					char *buf)			\</div><div class='ctx'> {									\</div><div class='ctx'> 	struct input_dev *input_dev = to_input_dev(dev);		\</div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%04x\n", input_dev-&gt;id.name);	\</div><div class='add'>+	return sysfs_emit(buf, "%04x\n", input_dev-&gt;id.name);		\</div><div class='ctx'> }									\</div><div class='ctx'> static DEVICE_ATTR(name, S_IRUGO, input_dev_show_id_##name, NULL)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/joystick/Kconfig b/drivers/input/joystick/Kconfig<br/>index ac6925ce8366..7755e5b454d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/joystick/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/joystick/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/Kconfig</a></div><div class='hunk'>@@ -412,4 +412,14 @@ config JOYSTICK_SENSEHAT</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the</div><div class='ctx'> 	  module will be called sensehat_joystick.</div><div class='ctx'> </div><div class='add'>+config JOYSTICK_SEESAW</div><div class='add'>+	tristate "Adafruit Mini I2C Gamepad with Seesaw"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select INPUT_SPARSEKMAP</div><div class='add'>+	help</div><div class='add'>+	  Say Y here if you want to use the Adafruit Mini I2C Gamepad.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module will be</div><div class='add'>+	  called adafruit-seesaw.</div><div class='add'>+</div><div class='ctx'> endif</div><div class='head'>diff --git a/drivers/input/joystick/Makefile b/drivers/input/joystick/Makefile<br/>index 3937535f0098..9976f596a920 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/joystick/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/joystick/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/Makefile</a></div><div class='hunk'>@@ -28,6 +28,7 @@ obj-$(CONFIG_JOYSTICK_N64)		+= n64joy.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_PSXPAD_SPI)	+= psxpad-spi.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_PXRC)		+= pxrc.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_QWIIC)		+= qwiic-joystick.o</div><div class='add'>+obj-$(CONFIG_JOYSTICK_SEESAW)		+= adafruit-seesaw.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_SENSEHAT)	+= sensehat-joystick.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_SIDEWINDER)	+= sidewinder.o</div><div class='ctx'> obj-$(CONFIG_JOYSTICK_SPACEBALL)	+= spaceball.o</div><div class='head'>diff --git a/drivers/input/joystick/adafruit-seesaw.c b/drivers/input/joystick/adafruit-seesaw.c<br/>new file mode 100644<br/>index 000000000000..1b9279f024cc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/adafruit-seesaw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/adafruit-seesaw.c</a></div><div class='hunk'>@@ -0,0 +1,315 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023 Anshul Dalal &lt;anshulusr@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * Driver for Adafruit Mini I2C Gamepad</div><div class='add'>+ *</div><div class='add'>+ * Based on the work of:</div><div class='add'>+ *	Oleh Kravchenko (Sparkfun Qwiic Joystick driver)</div><div class='add'>+ *</div><div class='add'>+ * Datasheet: https://cdn-learn.adafruit.com/downloads/pdf/gamepad-qt.pdf</div><div class='add'>+ * Product page: https://www.adafruit.com/product/5743</div><div class='add'>+ * Firmware and hardware sources: https://github.com/adafruit/Adafruit_Seesaw</div><div class='add'>+ *</div><div class='add'>+ * TODO:</div><div class='add'>+ *	- Add interrupt support</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/input.h&gt;</div><div class='add'>+#include &lt;linux/input/sparse-keymap.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#define SEESAW_DEVICE_NAME		"seesaw-gamepad"</div><div class='add'>+</div><div class='add'>+#define SEESAW_ADC_BASE			0x0900</div><div class='add'>+</div><div class='add'>+#define SEESAW_GPIO_DIRCLR_BULK		0x0103</div><div class='add'>+#define SEESAW_GPIO_BULK		0x0104</div><div class='add'>+#define SEESAW_GPIO_BULK_SET		0x0105</div><div class='add'>+#define SEESAW_GPIO_PULLENSET		0x010b</div><div class='add'>+</div><div class='add'>+#define SEESAW_STATUS_HW_ID		0x0001</div><div class='add'>+#define SEESAW_STATUS_SWRST		0x007f</div><div class='add'>+</div><div class='add'>+#define SEESAW_ADC_OFFSET		0x07</div><div class='add'>+</div><div class='add'>+#define SEESAW_BUTTON_A			0x05</div><div class='add'>+#define SEESAW_BUTTON_B			0x01</div><div class='add'>+#define SEESAW_BUTTON_X			0x06</div><div class='add'>+#define SEESAW_BUTTON_Y			0x02</div><div class='add'>+#define SEESAW_BUTTON_START		0x10</div><div class='add'>+#define SEESAW_BUTTON_SELECT		0x00</div><div class='add'>+</div><div class='add'>+#define SEESAW_ANALOG_X			0x0e</div><div class='add'>+#define SEESAW_ANALOG_Y			0x0f</div><div class='add'>+</div><div class='add'>+#define SEESAW_JOYSTICK_MAX_AXIS	1023</div><div class='add'>+#define SEESAW_JOYSTICK_FUZZ		2</div><div class='add'>+#define SEESAW_JOYSTICK_FLAT		4</div><div class='add'>+</div><div class='add'>+#define SEESAW_GAMEPAD_POLL_INTERVAL_MS	16</div><div class='add'>+#define SEESAW_GAMEPAD_POLL_MIN		8</div><div class='add'>+#define SEESAW_GAMEPAD_POLL_MAX		32</div><div class='add'>+</div><div class='add'>+static const unsigned long SEESAW_BUTTON_MASK =</div><div class='add'>+	BIT(SEESAW_BUTTON_A) | BIT(SEESAW_BUTTON_B) | BIT(SEESAW_BUTTON_X) |</div><div class='add'>+	BIT(SEESAW_BUTTON_Y) | BIT(SEESAW_BUTTON_START) |</div><div class='add'>+	BIT(SEESAW_BUTTON_SELECT);</div><div class='add'>+</div><div class='add'>+struct seesaw_gamepad {</div><div class='add'>+	struct input_dev *input_dev;</div><div class='add'>+	struct i2c_client *i2c_client;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct seesaw_data {</div><div class='add'>+	u16 x;</div><div class='add'>+	u16 y;</div><div class='add'>+	u32 button_state;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct key_entry seesaw_buttons_new[] = {</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_A, .keycode = BTN_SOUTH },</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_B, .keycode = BTN_EAST },</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_X, .keycode = BTN_NORTH },</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_Y, .keycode = BTN_WEST },</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_START, .keycode = BTN_START },</div><div class='add'>+	{ KE_KEY, SEESAW_BUTTON_SELECT, .keycode = BTN_SELECT },</div><div class='add'>+	{ KE_END, 0 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int seesaw_register_read(struct i2c_client *client, u16 reg, void *buf,</div><div class='add'>+				int count)</div><div class='add'>+{</div><div class='add'>+	__be16 register_buf = cpu_to_be16(reg);</div><div class='add'>+	struct i2c_msg message_buf[2] = {</div><div class='add'>+		{</div><div class='add'>+			.addr = client-&gt;addr,</div><div class='add'>+			.flags = client-&gt;flags,</div><div class='add'>+			.len = sizeof(register_buf),</div><div class='add'>+			.buf = (u8 *)&amp;register_buf,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.addr = client-&gt;addr,</div><div class='add'>+			.flags = client-&gt;flags | I2C_M_RD,</div><div class='add'>+			.len = count,</div><div class='add'>+			.buf = (u8 *)buf,</div><div class='add'>+		},</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_transfer(client-&gt;adapter, message_buf,</div><div class='add'>+			   ARRAY_SIZE(message_buf));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int seesaw_register_write_u8(struct i2c_client *client, u16 reg,</div><div class='add'>+				    u8 value)</div><div class='add'>+{</div><div class='add'>+	u8 write_buf[sizeof(reg) + sizeof(value)];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	put_unaligned_be16(reg, write_buf);</div><div class='add'>+	write_buf[sizeof(reg)] = value;</div><div class='add'>+</div><div class='add'>+	ret = i2c_master_send(client, write_buf, sizeof(write_buf));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int seesaw_register_write_u32(struct i2c_client *client, u16 reg,</div><div class='add'>+				     u32 value)</div><div class='add'>+{</div><div class='add'>+	u8 write_buf[sizeof(reg) + sizeof(value)];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	put_unaligned_be16(reg, write_buf);</div><div class='add'>+	put_unaligned_be32(value, write_buf + sizeof(reg));</div><div class='add'>+	ret = i2c_master_send(client, write_buf, sizeof(write_buf));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int seesaw_read_data(struct i2c_client *client, struct seesaw_data *data)</div><div class='add'>+{</div><div class='add'>+	__be16 adc_data;</div><div class='add'>+	__be32 read_buf;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = seesaw_register_read(client, SEESAW_GPIO_BULK,</div><div class='add'>+				   &amp;read_buf, sizeof(read_buf));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	data-&gt;button_state = ~be32_to_cpu(read_buf);</div><div class='add'>+</div><div class='add'>+	err = seesaw_register_read(client,</div><div class='add'>+				   SEESAW_ADC_BASE |</div><div class='add'>+					(SEESAW_ADC_OFFSET + SEESAW_ANALOG_X),</div><div class='add'>+				   &amp;adc_data, sizeof(adc_data));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+	/*</div><div class='add'>+	 * ADC reads left as max and right as 0, must be reversed since kernel</div><div class='add'>+	 * expects reports in opposite order.</div><div class='add'>+	 */</div><div class='add'>+	data-&gt;x = SEESAW_JOYSTICK_MAX_AXIS - be16_to_cpu(adc_data);</div><div class='add'>+</div><div class='add'>+	err = seesaw_register_read(client,</div><div class='add'>+				   SEESAW_ADC_BASE |</div><div class='add'>+					(SEESAW_ADC_OFFSET + SEESAW_ANALOG_Y),</div><div class='add'>+				   &amp;adc_data, sizeof(adc_data));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	data-&gt;y = be16_to_cpu(adc_data);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void seesaw_poll(struct input_dev *input)</div><div class='add'>+{</div><div class='add'>+	struct seesaw_gamepad *private = input_get_drvdata(input);</div><div class='add'>+	struct seesaw_data data;</div><div class='add'>+	int err, i;</div><div class='add'>+</div><div class='add'>+	err = seesaw_read_data(private-&gt;i2c_client, &amp;data);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err_ratelimited(&amp;input-&gt;dev,</div><div class='add'>+				    "failed to read joystick state: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	input_report_abs(input, ABS_X, data.x);</div><div class='add'>+	input_report_abs(input, ABS_Y, data.y);</div><div class='add'>+</div><div class='add'>+	for_each_set_bit(i, &amp;SEESAW_BUTTON_MASK,</div><div class='add'>+			 BITS_PER_TYPE(SEESAW_BUTTON_MASK)) {</div><div class='add'>+		if (!sparse_keymap_report_event(input, i,</div><div class='add'>+						data.button_state &amp; BIT(i),</div><div class='add'>+						false))</div><div class='add'>+			dev_err_ratelimited(&amp;input-&gt;dev,</div><div class='add'>+					    "failed to report keymap event");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	input_sync(input);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int seesaw_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct seesaw_gamepad *seesaw;</div><div class='add'>+	u8 hardware_id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = seesaw_register_write_u8(client, SEESAW_STATUS_SWRST, 0xFF);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* Wait for the registers to reset before proceeding */</div><div class='add'>+	usleep_range(10000, 15000);</div><div class='add'>+</div><div class='add'>+	seesaw = devm_kzalloc(&amp;client-&gt;dev, sizeof(*seesaw), GFP_KERNEL);</div><div class='add'>+	if (!seesaw)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	err = seesaw_register_read(client, SEESAW_STATUS_HW_ID,</div><div class='add'>+				   &amp;hardware_id, sizeof(hardware_id));</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "Adafruit Seesaw Gamepad, Hardware ID: %02x\n",</div><div class='add'>+		hardware_id);</div><div class='add'>+</div><div class='add'>+	/* Set Pin Mode to input and enable pull-up resistors */</div><div class='add'>+	err = seesaw_register_write_u32(client, SEESAW_GPIO_DIRCLR_BULK,</div><div class='add'>+					SEESAW_BUTTON_MASK);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+	err = seesaw_register_write_u32(client, SEESAW_GPIO_PULLENSET,</div><div class='add'>+					SEESAW_BUTTON_MASK);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+	err = seesaw_register_write_u32(client, SEESAW_GPIO_BULK_SET,</div><div class='add'>+					SEESAW_BUTTON_MASK);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	seesaw-&gt;i2c_client = client;</div><div class='add'>+	seesaw-&gt;input_dev = devm_input_allocate_device(&amp;client-&gt;dev);</div><div class='add'>+	if (!seesaw-&gt;input_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	seesaw-&gt;input_dev-&gt;id.bustype = BUS_I2C;</div><div class='add'>+	seesaw-&gt;input_dev-&gt;name = "Adafruit Seesaw Gamepad";</div><div class='add'>+	seesaw-&gt;input_dev-&gt;phys = "i2c/" SEESAW_DEVICE_NAME;</div><div class='add'>+	input_set_drvdata(seesaw-&gt;input_dev, seesaw);</div><div class='add'>+	input_set_abs_params(seesaw-&gt;input_dev, ABS_X,</div><div class='add'>+			     0, SEESAW_JOYSTICK_MAX_AXIS,</div><div class='add'>+			     SEESAW_JOYSTICK_FUZZ, SEESAW_JOYSTICK_FLAT);</div><div class='add'>+	input_set_abs_params(seesaw-&gt;input_dev, ABS_Y,</div><div class='add'>+			     0, SEESAW_JOYSTICK_MAX_AXIS,</div><div class='add'>+			     SEESAW_JOYSTICK_FUZZ, SEESAW_JOYSTICK_FLAT);</div><div class='add'>+</div><div class='add'>+	err = sparse_keymap_setup(seesaw-&gt;input_dev, seesaw_buttons_new, NULL);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev,</div><div class='add'>+			"failed to set up input device keymap: %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = input_setup_polling(seesaw-&gt;input_dev, seesaw_poll);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to set up polling: %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	input_set_poll_interval(seesaw-&gt;input_dev,</div><div class='add'>+				SEESAW_GAMEPAD_POLL_INTERVAL_MS);</div><div class='add'>+	input_set_max_poll_interval(seesaw-&gt;input_dev, SEESAW_GAMEPAD_POLL_MAX);</div><div class='add'>+	input_set_min_poll_interval(seesaw-&gt;input_dev, SEESAW_GAMEPAD_POLL_MIN);</div><div class='add'>+</div><div class='add'>+	err = input_register_device(seesaw-&gt;input_dev);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to register joystick: %d\n", err);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id seesaw_id_table[] = {</div><div class='add'>+	{ SEESAW_DEVICE_NAME },</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, seesaw_id_table);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id seesaw_of_table[] = {</div><div class='add'>+	{ .compatible = "adafruit,seesaw-gamepad"},</div><div class='add'>+	{ /* Sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, seesaw_of_table);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver seesaw_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = SEESAW_DEVICE_NAME,</div><div class='add'>+		.of_match_table = seesaw_of_table,</div><div class='add'>+	},</div><div class='add'>+	.id_table = seesaw_id_table,</div><div class='add'>+	.probe = seesaw_probe,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(seesaw_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Anshul Dalal &lt;anshulusr@gmail.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Adafruit Mini I2C Gamepad driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/input/joystick/as5011.c b/drivers/input/joystick/as5011.c<br/>index bf8b1cc0ea9c..f1822c19a289 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/joystick/as5011.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/joystick/as5011.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/as5011.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/as5011.c</a></div><div class='hunk'>@@ -13,7 +13,7 @@</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/input.h&gt;</div><div class='del'>-#include &lt;linux/gpio.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/input/as5011.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='hunk'>@@ -61,7 +61,7 @@ MODULE_LICENSE("GPL");</div><div class='ctx'> struct as5011_device {</div><div class='ctx'> 	struct input_dev *input_dev;</div><div class='ctx'> 	struct i2c_client *i2c_client;</div><div class='del'>-	unsigned int button_gpio;</div><div class='add'>+	struct gpio_desc *button_gpiod;</div><div class='ctx'> 	unsigned int button_irq;</div><div class='ctx'> 	unsigned int axis_irq;</div><div class='ctx'> };</div><div class='hunk'>@@ -114,7 +114,7 @@ static int as5011_i2c_read(struct i2c_client *client,</div><div class='ctx'> static irqreturn_t as5011_button_interrupt(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct as5011_device *as5011 = dev_id;</div><div class='del'>-	int val = gpio_get_value_cansleep(as5011-&gt;button_gpio);</div><div class='add'>+	int val = gpiod_get_value_cansleep(as5011-&gt;button_gpiod);</div><div class='ctx'> </div><div class='ctx'> 	input_report_key(as5011-&gt;input_dev, BTN_JOYSTICK, !val);</div><div class='ctx'> 	input_sync(as5011-&gt;input_dev);</div><div class='hunk'>@@ -248,7 +248,6 @@ static int as5011_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	as5011-&gt;i2c_client = client;</div><div class='ctx'> 	as5011-&gt;input_dev = input_dev;</div><div class='del'>-	as5011-&gt;button_gpio = plat_data-&gt;button_gpio;</div><div class='ctx'> 	as5011-&gt;axis_irq = plat_data-&gt;axis_irq;</div><div class='ctx'> </div><div class='ctx'> 	input_dev-&gt;name = "Austria Microsystem as5011 joystick";</div><div class='hunk'>@@ -262,18 +261,20 @@ static int as5011_probe(struct i2c_client *client)</div><div class='ctx'> 	input_set_abs_params(as5011-&gt;input_dev, ABS_Y,</div><div class='ctx'> 		AS5011_MIN_AXIS, AS5011_MAX_AXIS, AS5011_FUZZ, AS5011_FLAT);</div><div class='ctx'> </div><div class='del'>-	error = gpio_request(as5011-&gt;button_gpio, "AS5011 button");</div><div class='del'>-	if (error &lt; 0) {</div><div class='del'>-		dev_err(&amp;client-&gt;dev, "Failed to request button gpio\n");</div><div class='add'>+	as5011-&gt;button_gpiod = devm_gpiod_get(&amp;client-&gt;dev, NULL, GPIOD_IN);</div><div class='add'>+	if (IS_ERR(as5011-&gt;button_gpiod)) {</div><div class='add'>+		error = PTR_ERR(as5011-&gt;button_gpiod);</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Failed to request button GPIO\n");</div><div class='ctx'> 		goto err_free_mem;</div><div class='ctx'> 	}</div><div class='add'>+	gpiod_set_consumer_name(as5011-&gt;button_gpiod, "AS5011 button");</div><div class='ctx'> </div><div class='del'>-	irq = gpio_to_irq(as5011-&gt;button_gpio);</div><div class='add'>+	irq = gpiod_to_irq(as5011-&gt;button_gpiod);</div><div class='ctx'> 	if (irq &lt; 0) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev,</div><div class='ctx'> 			"Failed to get irq number for button gpio\n");</div><div class='ctx'> 		error = irq;</div><div class='del'>-		goto err_free_button_gpio;</div><div class='add'>+		goto err_free_mem;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	as5011-&gt;button_irq = irq;</div><div class='hunk'>@@ -286,7 +287,7 @@ static int as5011_probe(struct i2c_client *client)</div><div class='ctx'> 	if (error &lt; 0) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev,</div><div class='ctx'> 			"Can't allocate button irq %d\n", as5011-&gt;button_irq);</div><div class='del'>-		goto err_free_button_gpio;</div><div class='add'>+		goto err_free_mem;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	error = as5011_configure_chip(as5011, plat_data);</div><div class='hunk'>@@ -317,8 +318,6 @@ err_free_axis_irq:</div><div class='ctx'> 	free_irq(as5011-&gt;axis_irq, as5011);</div><div class='ctx'> err_free_button_irq:</div><div class='ctx'> 	free_irq(as5011-&gt;button_irq, as5011);</div><div class='del'>-err_free_button_gpio:</div><div class='del'>-	gpio_free(as5011-&gt;button_gpio);</div><div class='ctx'> err_free_mem:</div><div class='ctx'> 	input_free_device(input_dev);</div><div class='ctx'> 	kfree(as5011);</div><div class='hunk'>@@ -332,7 +331,6 @@ static void as5011_remove(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	free_irq(as5011-&gt;axis_irq, as5011);</div><div class='ctx'> 	free_irq(as5011-&gt;button_irq, as5011);</div><div class='del'>-	gpio_free(as5011-&gt;button_gpio);</div><div class='ctx'> </div><div class='ctx'> 	input_unregister_device(as5011-&gt;input_dev);</div><div class='ctx'> 	kfree(as5011);</div><div class='head'>diff --git a/drivers/input/joystick/pxrc.c b/drivers/input/joystick/pxrc.c<br/>index ea2bf5951d67..52d9eab667b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/joystick/pxrc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/joystick/pxrc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/pxrc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/pxrc.c</a></div><div class='hunk'>@@ -5,15 +5,17 @@</div><div class='ctx'>  * Copyright (C) 2018 Marcus Folkesson &lt;marcus.folkesson@gmail.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/input.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/usb.h&gt;</div><div class='ctx'> #include &lt;linux/usb/input.h&gt;</div><div class='del'>-#include &lt;linux/mutex.h&gt;</div><div class='del'>-#include &lt;linux/input.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define PXRC_VENDOR_ID		0x1781</div><div class='ctx'> #define PXRC_PRODUCT_ID		0x0898</div><div class='hunk'>@@ -81,33 +83,28 @@ exit:</div><div class='ctx'> static int pxrc_open(struct input_dev *input)</div><div class='ctx'> {</div><div class='ctx'> 	struct pxrc *pxrc = input_get_drvdata(input);</div><div class='del'>-	int retval;</div><div class='add'>+	int error;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;pxrc-&gt;pm_mutex);</div><div class='del'>-	retval = usb_submit_urb(pxrc-&gt;urb, GFP_KERNEL);</div><div class='del'>-	if (retval) {</div><div class='add'>+	guard(mutex)(&amp;pxrc-&gt;pm_mutex);</div><div class='add'>+	error = usb_submit_urb(pxrc-&gt;urb, GFP_KERNEL);</div><div class='add'>+	if (error) {</div><div class='ctx'> 		dev_err(&amp;pxrc-&gt;intf-&gt;dev,</div><div class='ctx'> 			"%s - usb_submit_urb failed, error: %d\n",</div><div class='del'>-			__func__, retval);</div><div class='del'>-		retval = -EIO;</div><div class='del'>-		goto out;</div><div class='add'>+			__func__, error);</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pxrc-&gt;is_open = true;</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;pxrc-&gt;pm_mutex);</div><div class='del'>-	return retval;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void pxrc_close(struct input_dev *input)</div><div class='ctx'> {</div><div class='ctx'> 	struct pxrc *pxrc = input_get_drvdata(input);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;pxrc-&gt;pm_mutex);</div><div class='add'>+	guard(mutex)(&amp;pxrc-&gt;pm_mutex);</div><div class='ctx'> 	usb_kill_urb(pxrc-&gt;urb);</div><div class='ctx'> 	pxrc-&gt;is_open = false;</div><div class='del'>-	mutex_unlock(&amp;pxrc-&gt;pm_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void pxrc_free_urb(void *_pxrc)</div><div class='hunk'>@@ -208,10 +205,9 @@ static int pxrc_suspend(struct usb_interface *intf, pm_message_t message)</div><div class='ctx'> {</div><div class='ctx'> 	struct pxrc *pxrc = usb_get_intfdata(intf);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;pxrc-&gt;pm_mutex);</div><div class='add'>+	guard(mutex)(&amp;pxrc-&gt;pm_mutex);</div><div class='ctx'> 	if (pxrc-&gt;is_open)</div><div class='ctx'> 		usb_kill_urb(pxrc-&gt;urb);</div><div class='del'>-	mutex_unlock(&amp;pxrc-&gt;pm_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -219,14 +215,12 @@ static int pxrc_suspend(struct usb_interface *intf, pm_message_t message)</div><div class='ctx'> static int pxrc_resume(struct usb_interface *intf)</div><div class='ctx'> {</div><div class='ctx'> 	struct pxrc *pxrc = usb_get_intfdata(intf);</div><div class='del'>-	int retval = 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;pxrc-&gt;pm_mutex);</div><div class='add'>+	guard(mutex)(&amp;pxrc-&gt;pm_mutex);</div><div class='ctx'> 	if (pxrc-&gt;is_open &amp;&amp; usb_submit_urb(pxrc-&gt;urb, GFP_KERNEL) &lt; 0)</div><div class='del'>-		retval = -EIO;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;pxrc-&gt;pm_mutex);</div><div class='del'>-	return retval;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int pxrc_pre_reset(struct usb_interface *intf)</div><div class='head'>diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c<br/>index f5c21565bb3c..b1244d7df6cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/joystick/xpad.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/joystick/xpad.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/joystick/xpad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/joystick/xpad.c</a></div><div class='hunk'>@@ -286,6 +286,7 @@ static const struct xpad_device {</div><div class='ctx'> 	{ 0x146b, 0x0604, "Bigben Interactive DAIJA Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 },</div><div class='ctx'> 	{ 0x1532, 0x0a00, "Razer Atrox Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE },</div><div class='ctx'> 	{ 0x1532, 0x0a03, "Razer Wildcat", 0, XTYPE_XBOXONE },</div><div class='add'>+	{ 0x1532, 0x0a29, "Razer Wolverine V2", 0, XTYPE_XBOXONE },</div><div class='ctx'> 	{ 0x15e4, 0x3f00, "Power A Mini Pro Elite", 0, XTYPE_XBOX360 },</div><div class='ctx'> 	{ 0x15e4, 0x3f0a, "Xbox Airflo wired controller", 0, XTYPE_XBOX360 },</div><div class='ctx'> 	{ 0x15e4, 0x3f10, "Batarang Xbox 360 controller", 0, XTYPE_XBOX360 },</div><div class='hunk'>@@ -1669,7 +1670,7 @@ static int xpad_led_probe(struct usb_xpad *xpad)</div><div class='ctx'> 	if (!led)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	xpad-&gt;pad_nr = ida_simple_get(&amp;xpad_pad_seq, 0, 0, GFP_KERNEL);</div><div class='add'>+	xpad-&gt;pad_nr = ida_alloc(&amp;xpad_pad_seq, GFP_KERNEL);</div><div class='ctx'> 	if (xpad-&gt;pad_nr &lt; 0) {</div><div class='ctx'> 		error = xpad-&gt;pad_nr;</div><div class='ctx'> 		goto err_free_mem;</div><div class='hunk'>@@ -1692,7 +1693,7 @@ static int xpad_led_probe(struct usb_xpad *xpad)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_free_id:</div><div class='del'>-	ida_simple_remove(&amp;xpad_pad_seq, xpad-&gt;pad_nr);</div><div class='add'>+	ida_free(&amp;xpad_pad_seq, xpad-&gt;pad_nr);</div><div class='ctx'> err_free_mem:</div><div class='ctx'> 	kfree(led);</div><div class='ctx'> 	xpad-&gt;led = NULL;</div><div class='hunk'>@@ -1705,7 +1706,7 @@ static void xpad_led_disconnect(struct usb_xpad *xpad)</div><div class='ctx'> </div><div class='ctx'> 	if (xpad_led) {</div><div class='ctx'> 		led_classdev_unregister(&amp;xpad_led-&gt;led_cdev);</div><div class='del'>-		ida_simple_remove(&amp;xpad_pad_seq, xpad-&gt;pad_nr);</div><div class='add'>+		ida_free(&amp;xpad_pad_seq, xpad-&gt;pad_nr);</div><div class='ctx'> 		kfree(xpad_led);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c<br/>index c92e544c792d..13ef6284223d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/atkbd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/atkbd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/atkbd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/atkbd.c</a></div><div class='hunk'>@@ -765,6 +765,44 @@ static void atkbd_deactivate(struct atkbd *atkbd)</div><div class='ctx'> 			ps2dev-&gt;serio-&gt;phys);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_X86</div><div class='add'>+static bool atkbd_is_portable_device(void)</div><div class='add'>+{</div><div class='add'>+	static const char * const chassis_types[] = {</div><div class='add'>+		"8",	/* Portable */</div><div class='add'>+		"9",	/* Laptop */</div><div class='add'>+		"10",	/* Notebook */</div><div class='add'>+		"14",	/* Sub-Notebook */</div><div class='add'>+		"31",	/* Convertible */</div><div class='add'>+		"32",	/* Detachable */</div><div class='add'>+	};</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(chassis_types); i++)</div><div class='add'>+		if (dmi_match(DMI_CHASSIS_TYPE, chassis_types[i]))</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * On many modern laptops ATKBD_CMD_GETID may cause problems, on these laptops</div><div class='add'>+ * the controller is always in translated mode. In this mode mice/touchpads will</div><div class='add'>+ * not work. So in this case simply assume a keyboard is connected to avoid</div><div class='add'>+ * confusing some laptop keyboards.</div><div class='add'>+ *</div><div class='add'>+ * Skipping ATKBD_CMD_GETID ends up using a fake keyboard id. Using the standard</div><div class='add'>+ * 0xab83 id is ok in translated mode, only atkbd_select_set() checks atkbd-&gt;id</div><div class='add'>+ * and in translated mode that is a no-op.</div><div class='add'>+ */</div><div class='add'>+static bool atkbd_skip_getid(struct atkbd *atkbd)</div><div class='add'>+{</div><div class='add'>+	return atkbd-&gt;translated &amp;&amp; atkbd_is_portable_device();</div><div class='add'>+}</div><div class='add'>+#else</div><div class='add'>+static inline bool atkbd_skip_getid(struct atkbd *atkbd) { return false; }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * atkbd_probe() probes for an AT keyboard on a serio port.</div><div class='ctx'>  */</div><div class='hunk'>@@ -773,6 +811,7 @@ static int atkbd_probe(struct atkbd *atkbd)</div><div class='ctx'> {</div><div class='ctx'> 	struct ps2dev *ps2dev = &amp;atkbd-&gt;ps2dev;</div><div class='ctx'> 	unsigned char param[2];</div><div class='add'>+	bool skip_getid;</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Some systems, where the bit-twiddling when testing the io-lines of the</div><div class='hunk'>@@ -794,17 +833,18 @@ static int atkbd_probe(struct atkbd *atkbd)</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> 	param[0] = param[1] = 0xa5;	/* initialize with invalid values */</div><div class='del'>-	if (ps2_command(ps2dev, param, ATKBD_CMD_GETID)) {</div><div class='add'>+	skip_getid = atkbd_skip_getid(atkbd);</div><div class='add'>+	if (skip_getid || ps2_command(ps2dev, param, ATKBD_CMD_GETID)) {</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * If the get ID command failed, we check if we can at least set the LEDs on</div><div class='del'>- * the keyboard. This should work on every keyboard out there. It also turns</div><div class='del'>- * the LEDs off, which we want anyway.</div><div class='add'>+ * If the get ID command was skipped or failed, we check if we can at least set</div><div class='add'>+ * the LEDs on the keyboard. This should work on every keyboard out there.</div><div class='add'>+ * It also turns the LEDs off, which we want anyway.</div><div class='ctx'>  */</div><div class='ctx'> 		param[0] = 0;</div><div class='ctx'> 		if (ps2_command(ps2dev, param, ATKBD_CMD_SETLEDS))</div><div class='ctx'> 			return -1;</div><div class='del'>-		atkbd-&gt;id = 0xabba;</div><div class='add'>+		atkbd-&gt;id = skip_getid ? 0xab83 : 0xabba;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/keyboard/cap11xx.c b/drivers/input/keyboard/cap11xx.c<br/>index 1b4937dce672..52fba9ee7c1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/cap11xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/cap11xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/cap11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/cap11xx.c</a></div><div class='hunk'>@@ -10,10 +10,11 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/input.h&gt;</div><div class='ctx'> #include &lt;linux/leds.h&gt;</div><div class='del'>-#include &lt;linux/of_irq.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define CAP11XX_REG_MAIN_CONTROL	0x00</div><div class='ctx'> #define CAP11XX_REG_MAIN_CONTROL_GAIN_SHIFT	(6)</div><div class='hunk'>@@ -24,6 +25,7 @@</div><div class='ctx'> #define CAP11XX_REG_NOISE_FLAG_STATUS	0x0a</div><div class='ctx'> #define CAP11XX_REG_SENOR_DELTA(X)	(0x10 + (X))</div><div class='ctx'> #define CAP11XX_REG_SENSITIVITY_CONTROL	0x1f</div><div class='add'>+#define CAP11XX_REG_SENSITIVITY_CONTROL_DELTA_SENSE_MASK	0x70</div><div class='ctx'> #define CAP11XX_REG_CONFIG		0x20</div><div class='ctx'> #define CAP11XX_REG_SENSOR_ENABLE	0x21</div><div class='ctx'> #define CAP11XX_REG_SENSOR_CONFIG	0x22</div><div class='hunk'>@@ -32,6 +34,7 @@</div><div class='ctx'> #define CAP11XX_REG_CALIBRATION		0x26</div><div class='ctx'> #define CAP11XX_REG_INT_ENABLE		0x27</div><div class='ctx'> #define CAP11XX_REG_REPEAT_RATE		0x28</div><div class='add'>+#define CAP11XX_REG_SIGNAL_GUARD_ENABLE	0x29</div><div class='ctx'> #define CAP11XX_REG_MT_CONFIG		0x2a</div><div class='ctx'> #define CAP11XX_REG_MT_PATTERN_CONFIG	0x2b</div><div class='ctx'> #define CAP11XX_REG_MT_PATTERN		0x2d</div><div class='hunk'>@@ -47,6 +50,8 @@</div><div class='ctx'> #define CAP11XX_REG_SENSOR_BASE_CNT(X)	(0x50 + (X))</div><div class='ctx'> #define CAP11XX_REG_LED_POLARITY	0x73</div><div class='ctx'> #define CAP11XX_REG_LED_OUTPUT_CONTROL	0x74</div><div class='add'>+#define CAP11XX_REG_CALIB_SENSITIVITY_CONFIG	0x80</div><div class='add'>+#define CAP11XX_REG_CALIB_SENSITIVITY_CONFIG2	0x81</div><div class='ctx'> </div><div class='ctx'> #define CAP11XX_REG_LED_DUTY_CYCLE_1	0x90</div><div class='ctx'> #define CAP11XX_REG_LED_DUTY_CYCLE_2	0x91</div><div class='hunk'>@@ -78,12 +83,20 @@ struct cap11xx_led {</div><div class='ctx'> </div><div class='ctx'> struct cap11xx_priv {</div><div class='ctx'> 	struct regmap *regmap;</div><div class='add'>+	struct device *dev;</div><div class='ctx'> 	struct input_dev *idev;</div><div class='add'>+	const struct cap11xx_hw_model *model;</div><div class='add'>+	u8 id;</div><div class='ctx'> </div><div class='ctx'> 	struct cap11xx_led *leds;</div><div class='ctx'> 	int num_leds;</div><div class='ctx'> </div><div class='ctx'> 	/* config */</div><div class='add'>+	u8 analog_gain;</div><div class='add'>+	u8 sensitivity_delta_sense;</div><div class='add'>+	u8 signal_guard_inputs_mask;</div><div class='add'>+	u32 thresholds[8];</div><div class='add'>+	u32 calib_sensitivities[8];</div><div class='ctx'> 	u32 keycodes[];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -160,9 +173,6 @@ static bool cap11xx_volatile_reg(struct device *dev, unsigned int reg)</div><div class='ctx'> 	case CAP11XX_REG_SENOR_DELTA(3):</div><div class='ctx'> 	case CAP11XX_REG_SENOR_DELTA(4):</div><div class='ctx'> 	case CAP11XX_REG_SENOR_DELTA(5):</div><div class='del'>-	case CAP11XX_REG_PRODUCT_ID:</div><div class='del'>-	case CAP11XX_REG_MANUFACTURER_ID:</div><div class='del'>-	case CAP11XX_REG_REVISION:</div><div class='ctx'> 		return true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -177,10 +187,179 @@ static const struct regmap_config cap11xx_regmap_config = {</div><div class='ctx'> 	.reg_defaults = cap11xx_reg_defaults,</div><div class='ctx'> </div><div class='ctx'> 	.num_reg_defaults = ARRAY_SIZE(cap11xx_reg_defaults),</div><div class='del'>-	.cache_type = REGCACHE_RBTREE,</div><div class='add'>+	.cache_type = REGCACHE_MAPLE,</div><div class='ctx'> 	.volatile_reg = cap11xx_volatile_reg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int cap11xx_write_calib_sens_config_1(struct cap11xx_priv *priv)</div><div class='add'>+{</div><div class='add'>+	return regmap_write(priv-&gt;regmap,</div><div class='add'>+			    CAP11XX_REG_CALIB_SENSITIVITY_CONFIG,</div><div class='add'>+			    (priv-&gt;calib_sensitivities[3] &lt;&lt; 6) |</div><div class='add'>+			    (priv-&gt;calib_sensitivities[2] &lt;&lt; 4) |</div><div class='add'>+			    (priv-&gt;calib_sensitivities[1] &lt;&lt; 2) |</div><div class='add'>+			    priv-&gt;calib_sensitivities[0]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cap11xx_write_calib_sens_config_2(struct cap11xx_priv *priv)</div><div class='add'>+{</div><div class='add'>+	return regmap_write(priv-&gt;regmap,</div><div class='add'>+			    CAP11XX_REG_CALIB_SENSITIVITY_CONFIG2,</div><div class='add'>+			    (priv-&gt;calib_sensitivities[7] &lt;&lt; 6) |</div><div class='add'>+			    (priv-&gt;calib_sensitivities[6] &lt;&lt; 4) |</div><div class='add'>+			    (priv-&gt;calib_sensitivities[5] &lt;&lt; 2) |</div><div class='add'>+			    priv-&gt;calib_sensitivities[4]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cap11xx_init_keys(struct cap11xx_priv *priv)</div><div class='add'>+{</div><div class='add'>+	struct device_node *node = priv-&gt;dev-&gt;of_node;</div><div class='add'>+	struct device *dev = priv-&gt;dev;</div><div class='add'>+	int i, error;</div><div class='add'>+	u32 u32_val;</div><div class='add'>+</div><div class='add'>+	if (!node) {</div><div class='add'>+		dev_err(dev, "Corresponding DT entry is not available\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!of_property_read_u32(node, "microchip,sensor-gain", &amp;u32_val)) {</div><div class='add'>+		if (priv-&gt;model-&gt;no_gain) {</div><div class='add'>+			dev_warn(dev,</div><div class='add'>+				 "This model doesn't support 'sensor-gain'\n");</div><div class='add'>+		} else if (is_power_of_2(u32_val) &amp;&amp; u32_val &lt;= 8) {</div><div class='add'>+			priv-&gt;analog_gain = (u8)ilog2(u32_val);</div><div class='add'>+</div><div class='add'>+			error = regmap_update_bits(priv-&gt;regmap,</div><div class='add'>+				CAP11XX_REG_MAIN_CONTROL,</div><div class='add'>+				CAP11XX_REG_MAIN_CONTROL_GAIN_MASK,</div><div class='add'>+				priv-&gt;analog_gain &lt;&lt; CAP11XX_REG_MAIN_CONTROL_GAIN_SHIFT);</div><div class='add'>+			if (error)</div><div class='add'>+				return error;</div><div class='add'>+		} else {</div><div class='add'>+			dev_err(dev, "Invalid sensor-gain value %u\n", u32_val);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (of_property_read_bool(node, "microchip,irq-active-high")) {</div><div class='add'>+		if (priv-&gt;id == CAP1106 ||</div><div class='add'>+		    priv-&gt;id == CAP1126 ||</div><div class='add'>+		    priv-&gt;id == CAP1188) {</div><div class='add'>+			error = regmap_update_bits(priv-&gt;regmap,</div><div class='add'>+						   CAP11XX_REG_CONFIG2,</div><div class='add'>+						   CAP11XX_REG_CONFIG2_ALT_POL,</div><div class='add'>+						   0);</div><div class='add'>+			if (error)</div><div class='add'>+				return error;</div><div class='add'>+		} else {</div><div class='add'>+			dev_warn(dev,</div><div class='add'>+				 "This model doesn't support 'irq-active-high'\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!of_property_read_u32(node, "microchip,sensitivity-delta-sense", &amp;u32_val)) {</div><div class='add'>+		if (!is_power_of_2(u32_val) || u32_val &gt; 128) {</div><div class='add'>+			dev_err(dev, "Invalid sensitivity-delta-sense value %u\n", u32_val);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		priv-&gt;sensitivity_delta_sense = (u8)ilog2(u32_val);</div><div class='add'>+		u32_val = ~(FIELD_PREP(CAP11XX_REG_SENSITIVITY_CONTROL_DELTA_SENSE_MASK,</div><div class='add'>+					priv-&gt;sensitivity_delta_sense));</div><div class='add'>+</div><div class='add'>+		error = regmap_update_bits(priv-&gt;regmap,</div><div class='add'>+					   CAP11XX_REG_SENSITIVITY_CONTROL,</div><div class='add'>+					   CAP11XX_REG_SENSITIVITY_CONTROL_DELTA_SENSE_MASK,</div><div class='add'>+					   u32_val);</div><div class='add'>+		if (error)</div><div class='add'>+			return error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!of_property_read_u32_array(node, "microchip,input-threshold",</div><div class='add'>+					priv-&gt;thresholds, priv-&gt;model-&gt;num_channels)) {</div><div class='add'>+		for (i = 0; i &lt; priv-&gt;model-&gt;num_channels; i++) {</div><div class='add'>+			if (priv-&gt;thresholds[i] &gt; 127) {</div><div class='add'>+				dev_err(dev, "Invalid input-threshold value %u\n",</div><div class='add'>+					priv-&gt;thresholds[i]);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			error = regmap_write(priv-&gt;regmap,</div><div class='add'>+					     CAP11XX_REG_SENSOR_THRESH(i),</div><div class='add'>+					     priv-&gt;thresholds[i]);</div><div class='add'>+			if (error)</div><div class='add'>+				return error;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!of_property_read_u32_array(node, "microchip,calib-sensitivity",</div><div class='add'>+					priv-&gt;calib_sensitivities,</div><div class='add'>+					priv-&gt;model-&gt;num_channels)) {</div><div class='add'>+		if (priv-&gt;id == CAP1293 || priv-&gt;id == CAP1298) {</div><div class='add'>+			for (i = 0; i &lt; priv-&gt;model-&gt;num_channels; i++) {</div><div class='add'>+				if (!is_power_of_2(priv-&gt;calib_sensitivities[i]) ||</div><div class='add'>+				    priv-&gt;calib_sensitivities[i] &gt; 4) {</div><div class='add'>+					dev_err(dev, "Invalid calib-sensitivity value %u\n",</div><div class='add'>+						priv-&gt;calib_sensitivities[i]);</div><div class='add'>+					return -EINVAL;</div><div class='add'>+				}</div><div class='add'>+				priv-&gt;calib_sensitivities[i] = ilog2(priv-&gt;calib_sensitivities[i]);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			error = cap11xx_write_calib_sens_config_1(priv);</div><div class='add'>+			if (error)</div><div class='add'>+				return error;</div><div class='add'>+</div><div class='add'>+			if (priv-&gt;id == CAP1298) {</div><div class='add'>+				error = cap11xx_write_calib_sens_config_2(priv);</div><div class='add'>+				if (error)</div><div class='add'>+					return error;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			dev_warn(dev,</div><div class='add'>+				 "This model doesn't support 'calib-sensitivity'\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; priv-&gt;model-&gt;num_channels; i++) {</div><div class='add'>+		if (!of_property_read_u32_index(node, "microchip,signal-guard",</div><div class='add'>+						i, &amp;u32_val)) {</div><div class='add'>+			if (u32_val &gt; 1)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			if (u32_val)</div><div class='add'>+				priv-&gt;signal_guard_inputs_mask |= 0x01 &lt;&lt; i;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;signal_guard_inputs_mask) {</div><div class='add'>+		if (priv-&gt;id == CAP1293 || priv-&gt;id == CAP1298) {</div><div class='add'>+			error = regmap_write(priv-&gt;regmap,</div><div class='add'>+					     CAP11XX_REG_SIGNAL_GUARD_ENABLE,</div><div class='add'>+					     priv-&gt;signal_guard_inputs_mask);</div><div class='add'>+			if (error)</div><div class='add'>+				return error;</div><div class='add'>+		} else {</div><div class='add'>+			dev_warn(dev,</div><div class='add'>+				 "This model doesn't support 'signal-guard'\n");</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Provide some useful defaults */</div><div class='add'>+	for (i = 0; i &lt; priv-&gt;model-&gt;num_channels; i++)</div><div class='add'>+		priv-&gt;keycodes[i] = KEY_A + i;</div><div class='add'>+</div><div class='add'>+	of_property_read_u32_array(node, "linux,keycodes",</div><div class='add'>+				   priv-&gt;keycodes, priv-&gt;model-&gt;num_channels);</div><div class='add'>+</div><div class='add'>+	/* Disable autorepeat. The Linux input system has its own handling. */</div><div class='add'>+	error = regmap_write(priv-&gt;regmap, CAP11XX_REG_REPEAT_RATE, 0);</div><div class='add'>+	if (error)</div><div class='add'>+		return error;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static irqreturn_t cap11xx_thread_func(int irq_num, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct cap11xx_priv *priv = data;</div><div class='hunk'>@@ -332,11 +511,9 @@ static int cap11xx_i2c_probe(struct i2c_client *i2c_client)</div><div class='ctx'> 	const struct i2c_device_id *id = i2c_client_get_device_id(i2c_client);</div><div class='ctx'> 	struct device *dev = &amp;i2c_client-&gt;dev;</div><div class='ctx'> 	struct cap11xx_priv *priv;</div><div class='del'>-	struct device_node *node;</div><div class='ctx'> 	const struct cap11xx_hw_model *cap;</div><div class='del'>-	int i, error, irq, gain = 0;</div><div class='add'>+	int i, error;</div><div class='ctx'> 	unsigned int val, rev;</div><div class='del'>-	u32 gain32;</div><div class='ctx'> </div><div class='ctx'> 	if (id-&gt;driver_data &gt;= ARRAY_SIZE(cap11xx_devices)) {</div><div class='ctx'> 		dev_err(dev, "Invalid device ID %lu\n", id-&gt;driver_data);</div><div class='hunk'>@@ -355,6 +532,8 @@ static int cap11xx_i2c_probe(struct i2c_client *i2c_client)</div><div class='ctx'> 	if (!priv)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	priv-&gt;dev = dev;</div><div class='add'>+</div><div class='ctx'> 	priv-&gt;regmap = devm_regmap_init_i2c(i2c_client, &amp;cap11xx_regmap_config);</div><div class='ctx'> 	if (IS_ERR(priv-&gt;regmap))</div><div class='ctx'> 		return PTR_ERR(priv-&gt;regmap);</div><div class='hunk'>@@ -384,50 +563,15 @@ static int cap11xx_i2c_probe(struct i2c_client *i2c_client)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='ctx'> 	dev_info(dev, "CAP11XX detected, model %s, revision 0x%02x\n",</div><div class='del'>-		 id-&gt;name, rev);</div><div class='del'>-	node = dev-&gt;of_node;</div><div class='del'>-</div><div class='del'>-	if (!of_property_read_u32(node, "microchip,sensor-gain", &amp;gain32)) {</div><div class='del'>-		if (cap-&gt;no_gain)</div><div class='del'>-			dev_warn(dev,</div><div class='del'>-				 "This version doesn't support sensor gain\n");</div><div class='del'>-		else if (is_power_of_2(gain32) &amp;&amp; gain32 &lt;= 8)</div><div class='del'>-			gain = ilog2(gain32);</div><div class='del'>-		else</div><div class='del'>-			dev_err(dev, "Invalid sensor-gain value %d\n", gain32);</div><div class='del'>-	}</div><div class='add'>+			 id-&gt;name, rev);</div><div class='ctx'> </div><div class='del'>-	if (id-&gt;driver_data == CAP1106 ||</div><div class='del'>-	    id-&gt;driver_data == CAP1126 ||</div><div class='del'>-	    id-&gt;driver_data == CAP1188) {</div><div class='del'>-		if (of_property_read_bool(node, "microchip,irq-active-high")) {</div><div class='del'>-			error = regmap_update_bits(priv-&gt;regmap,</div><div class='del'>-						   CAP11XX_REG_CONFIG2,</div><div class='del'>-						   CAP11XX_REG_CONFIG2_ALT_POL,</div><div class='del'>-						   0);</div><div class='del'>-			if (error)</div><div class='del'>-				return error;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Provide some useful defaults */</div><div class='del'>-	for (i = 0; i &lt; cap-&gt;num_channels; i++)</div><div class='del'>-		priv-&gt;keycodes[i] = KEY_A + i;</div><div class='del'>-</div><div class='del'>-	of_property_read_u32_array(node, "linux,keycodes",</div><div class='del'>-				   priv-&gt;keycodes, cap-&gt;num_channels);</div><div class='add'>+	priv-&gt;model = cap;</div><div class='add'>+	priv-&gt;id = id-&gt;driver_data;</div><div class='ctx'> </div><div class='del'>-	if (!cap-&gt;no_gain) {</div><div class='del'>-		error = regmap_update_bits(priv-&gt;regmap,</div><div class='del'>-				CAP11XX_REG_MAIN_CONTROL,</div><div class='del'>-				CAP11XX_REG_MAIN_CONTROL_GAIN_MASK,</div><div class='del'>-				gain &lt;&lt; CAP11XX_REG_MAIN_CONTROL_GAIN_SHIFT);</div><div class='del'>-		if (error)</div><div class='del'>-			return error;</div><div class='del'>-	}</div><div class='add'>+	dev_info(dev, "CAP11XX device detected, model %s, revision 0x%02x\n",</div><div class='add'>+		 id-&gt;name, rev);</div><div class='ctx'> </div><div class='del'>-	/* Disable autorepeat. The Linux input system has its own handling. */</div><div class='del'>-	error = regmap_write(priv-&gt;regmap, CAP11XX_REG_REPEAT_RATE, 0);</div><div class='add'>+	error = cap11xx_init_keys(priv);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='hunk'>@@ -439,7 +583,7 @@ static int cap11xx_i2c_probe(struct i2c_client *i2c_client)</div><div class='ctx'> 	priv-&gt;idev-&gt;id.bustype = BUS_I2C;</div><div class='ctx'> 	priv-&gt;idev-&gt;evbit[0] = BIT_MASK(EV_KEY);</div><div class='ctx'> </div><div class='del'>-	if (of_property_read_bool(node, "autorepeat"))</div><div class='add'>+	if (of_property_read_bool(dev-&gt;of_node, "autorepeat"))</div><div class='ctx'> 		__set_bit(EV_REP, priv-&gt;idev-&gt;evbit);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; cap-&gt;num_channels; i++)</div><div class='hunk'>@@ -474,13 +618,8 @@ static int cap11xx_i2c_probe(struct i2c_client *i2c_client)</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	irq = irq_of_parse_and_map(node, 0);</div><div class='del'>-	if (!irq) {</div><div class='del'>-		dev_err(dev, "Unable to parse or map IRQ\n");</div><div class='del'>-		return -ENXIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	error = devm_request_threaded_irq(dev, irq, NULL, cap11xx_thread_func,</div><div class='add'>+	error = devm_request_threaded_irq(dev, i2c_client-&gt;irq,</div><div class='add'>+					  NULL, cap11xx_thread_func,</div><div class='ctx'> 					  IRQF_ONESHOT, dev_name(dev), priv);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='head'>diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c<br/>index 2e7c2c046e67..9f3bcd41cf67 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/gpio_keys.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/gpio_keys.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/gpio_keys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/gpio_keys.c</a></div><div class='hunk'>@@ -45,7 +45,9 @@ struct gpio_button_data {</div><div class='ctx'> 	unsigned int software_debounce;	/* in msecs, for GPIO-driven buttons */</div><div class='ctx'> </div><div class='ctx'> 	unsigned int irq;</div><div class='add'>+	unsigned int wakeirq;</div><div class='ctx'> 	unsigned int wakeup_trigger_type;</div><div class='add'>+</div><div class='ctx'> 	spinlock_t lock;</div><div class='ctx'> 	bool disabled;</div><div class='ctx'> 	bool key_pressed;</div><div class='hunk'>@@ -511,6 +513,7 @@ static int gpio_keys_setup_key(struct platform_device *pdev,</div><div class='ctx'> 	struct gpio_button_data *bdata = &amp;ddata-&gt;data[idx];</div><div class='ctx'> 	irq_handler_t isr;</div><div class='ctx'> 	unsigned long irqflags;</div><div class='add'>+	const char *wakedesc;</div><div class='ctx'> 	int irq;</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='hunk'>@@ -575,15 +578,23 @@ static int gpio_keys_setup_key(struct platform_device *pdev,</div><div class='ctx'> 					!gpiod_cansleep(bdata-&gt;gpiod);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		/*</div><div class='add'>+		 * If an interrupt was specified, use it instead of the gpio</div><div class='add'>+		 * interrupt and use the gpio for reading the state. A separate</div><div class='add'>+		 * interrupt may be used as the main button interrupt for</div><div class='add'>+		 * runtime PM to detect events also in deeper idle states. If a</div><div class='add'>+		 * dedicated wakeirq is used for system suspend only, see below</div><div class='add'>+		 * for bdata-&gt;wakeirq setup.</div><div class='add'>+		 */</div><div class='ctx'> 		if (button-&gt;irq) {</div><div class='ctx'> 			bdata-&gt;irq = button-&gt;irq;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			irq = gpiod_to_irq(bdata-&gt;gpiod);</div><div class='ctx'> 			if (irq &lt; 0) {</div><div class='ctx'> 				error = irq;</div><div class='del'>-				dev_err(dev,</div><div class='del'>-					"Unable to get irq number for GPIO %d, error %d\n",</div><div class='del'>-					button-&gt;gpio, error);</div><div class='add'>+				dev_err_probe(dev, error,</div><div class='add'>+					      "Unable to get irq number for GPIO %d\n",</div><div class='add'>+					      button-&gt;gpio);</div><div class='ctx'> 				return error;</div><div class='ctx'> 			}</div><div class='ctx'> 			bdata-&gt;irq = irq;</div><div class='hunk'>@@ -672,6 +683,36 @@ static int gpio_keys_setup_key(struct platform_device *pdev,</div><div class='ctx'> 		return error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!button-&gt;wakeirq)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* Use :wakeup suffix like drivers/base/power/wakeirq.c does */</div><div class='add'>+	wakedesc = devm_kasprintf(dev, GFP_KERNEL, "%s:wakeup", desc);</div><div class='add'>+	if (!wakedesc)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	bdata-&gt;wakeirq = button-&gt;wakeirq;</div><div class='add'>+	irqflags |= IRQF_NO_SUSPEND;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wakeirq shares the handler with the main interrupt, it's only</div><div class='add'>+	 * active during system suspend. See gpio_keys_button_enable_wakeup()</div><div class='add'>+	 * and gpio_keys_button_disable_wakeup().</div><div class='add'>+	 */</div><div class='add'>+	error = devm_request_any_context_irq(dev, bdata-&gt;wakeirq, isr,</div><div class='add'>+					     irqflags, wakedesc, bdata);</div><div class='add'>+	if (error &lt; 0) {</div><div class='add'>+		dev_err(dev, "Unable to claim wakeirq %d; error %d\n",</div><div class='add'>+			bdata-&gt;irq, error);</div><div class='add'>+		return error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Disable wakeirq until suspend. IRQF_NO_AUTOEN won't work if</div><div class='add'>+	 * IRQF_SHARED was set based on !button-&gt;can_disable.</div><div class='add'>+	 */</div><div class='add'>+	disable_irq(bdata-&gt;wakeirq);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -728,7 +769,7 @@ gpio_keys_get_devtree_pdata(struct device *dev)</div><div class='ctx'> 	struct gpio_keys_platform_data *pdata;</div><div class='ctx'> 	struct gpio_keys_button *button;</div><div class='ctx'> 	struct fwnode_handle *child;</div><div class='del'>-	int nbuttons;</div><div class='add'>+	int nbuttons, irq;</div><div class='ctx'> </div><div class='ctx'> 	nbuttons = device_get_child_node_count(dev);</div><div class='ctx'> 	if (nbuttons == 0)</div><div class='hunk'>@@ -750,9 +791,19 @@ gpio_keys_get_devtree_pdata(struct device *dev)</div><div class='ctx'> 	device_property_read_string(dev, "label", &amp;pdata-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 	device_for_each_child_node(dev, child) {</div><div class='del'>-		if (is_of_node(child))</div><div class='del'>-			button-&gt;irq =</div><div class='del'>-				irq_of_parse_and_map(to_of_node(child), 0);</div><div class='add'>+		if (is_of_node(child)) {</div><div class='add'>+			irq = of_irq_get_byname(to_of_node(child), "irq");</div><div class='add'>+			if (irq &gt; 0)</div><div class='add'>+				button-&gt;irq = irq;</div><div class='add'>+</div><div class='add'>+			irq = of_irq_get_byname(to_of_node(child), "wakeup");</div><div class='add'>+			if (irq &gt; 0)</div><div class='add'>+				button-&gt;wakeirq = irq;</div><div class='add'>+</div><div class='add'>+			if (!button-&gt;irq &amp;&amp; !button-&gt;wakeirq)</div><div class='add'>+				button-&gt;irq =</div><div class='add'>+					irq_of_parse_and_map(to_of_node(child), 0);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (fwnode_property_read_u32(child, "linux,code",</div><div class='ctx'> 					     &amp;button-&gt;code)) {</div><div class='hunk'>@@ -921,6 +972,11 @@ gpio_keys_button_enable_wakeup(struct gpio_button_data *bdata)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (bdata-&gt;wakeirq) {</div><div class='add'>+		enable_irq(bdata-&gt;wakeirq);</div><div class='add'>+		disable_irq(bdata-&gt;irq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -929,6 +985,11 @@ gpio_keys_button_disable_wakeup(struct gpio_button_data *bdata)</div><div class='ctx'> {</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='add'>+	if (bdata-&gt;wakeirq) {</div><div class='add'>+		enable_irq(bdata-&gt;irq);</div><div class='add'>+		disable_irq(bdata-&gt;wakeirq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The trigger type is always both edges for gpio-based keys and we do</div><div class='ctx'> 	 * not support changing wakeup trigger for interrupt-based keys.</div><div class='head'>diff --git a/drivers/input/keyboard/ipaq-micro-keys.c b/drivers/input/keyboard/ipaq-micro-keys.c<br/>index 7b509bce2b33..1d71dd79ffd2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/ipaq-micro-keys.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/ipaq-micro-keys.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/ipaq-micro-keys.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/ipaq-micro-keys.c</a></div><div class='hunk'>@@ -105,6 +105,9 @@ static int micro_key_probe(struct platform_device *pdev)</div><div class='ctx'> 	keys-&gt;codes = devm_kmemdup(&amp;pdev-&gt;dev, micro_keycodes,</div><div class='ctx'> 			   keys-&gt;input-&gt;keycodesize * keys-&gt;input-&gt;keycodemax,</div><div class='ctx'> 			   GFP_KERNEL);</div><div class='add'>+	if (!keys-&gt;codes)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	keys-&gt;input-&gt;keycode = keys-&gt;codes;</div><div class='ctx'> </div><div class='ctx'> 	__set_bit(EV_KEY, keys-&gt;input-&gt;evbit);</div><div class='head'>diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c<br/>index 454fb8675657..16f936db7305 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/omap-keypad.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/omap-keypad.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/omap-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/omap-keypad.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/gpio.h&gt;</div><div class='ctx'> #include &lt;linux/platform_data/gpio-omap.h&gt;</div><div class='ctx'> #include &lt;linux/platform_data/keypad-omap.h&gt;</div><div class='ctx'> #include &lt;linux/soc/ti/omap1-io.h&gt;</div><div class='hunk'>@@ -49,9 +48,6 @@ struct omap_kp {</div><div class='ctx'> </div><div class='ctx'> static DECLARE_TASKLET_DISABLED_OLD(kp_tasklet, omap_kp_tasklet);</div><div class='ctx'> </div><div class='del'>-static unsigned int *row_gpios;</div><div class='del'>-static unsigned int *col_gpios;</div><div class='del'>-</div><div class='ctx'> static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	/* disable keyboard interrupt and schedule for handling */</div><div class='hunk'>@@ -180,7 +176,7 @@ static int omap_kp_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct omap_kp *omap_kp;</div><div class='ctx'> 	struct input_dev *input_dev;</div><div class='ctx'> 	struct omap_kp_platform_data *pdata = dev_get_platdata(&amp;pdev-&gt;dev);</div><div class='del'>-	int i, col_idx, row_idx, ret;</div><div class='add'>+	int ret;</div><div class='ctx'> 	unsigned int row_shift, keycodemax;</div><div class='ctx'> </div><div class='ctx'> 	if (!pdata-&gt;rows || !pdata-&gt;cols || !pdata-&gt;keymap_data) {</div><div class='hunk'>@@ -209,17 +205,9 @@ static int omap_kp_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (pdata-&gt;delay)</div><div class='ctx'> 		omap_kp-&gt;delay = pdata-&gt;delay;</div><div class='ctx'> </div><div class='del'>-	if (pdata-&gt;row_gpios &amp;&amp; pdata-&gt;col_gpios) {</div><div class='del'>-		row_gpios = pdata-&gt;row_gpios;</div><div class='del'>-		col_gpios = pdata-&gt;col_gpios;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	omap_kp-&gt;rows = pdata-&gt;rows;</div><div class='ctx'> 	omap_kp-&gt;cols = pdata-&gt;cols;</div><div class='ctx'> </div><div class='del'>-	col_idx = 0;</div><div class='del'>-	row_idx = 0;</div><div class='del'>-</div><div class='ctx'> 	timer_setup(&amp;omap_kp-&gt;timer, omap_kp_timer, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* get the irq and init timer*/</div><div class='hunk'>@@ -276,11 +264,6 @@ err4:</div><div class='ctx'> err3:</div><div class='ctx'> 	device_remove_file(&amp;pdev-&gt;dev, &amp;dev_attr_enable);</div><div class='ctx'> err2:</div><div class='del'>-	for (i = row_idx - 1; i &gt;= 0; i--)</div><div class='del'>-		gpio_free(row_gpios[i]);</div><div class='del'>-	for (i = col_idx - 1; i &gt;= 0; i--)</div><div class='del'>-		gpio_free(col_gpios[i]);</div><div class='del'>-</div><div class='ctx'> 	kfree(omap_kp);</div><div class='ctx'> 	input_free_device(input_dev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c<br/>index d3f8688fdd9c..040b340995d8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/omap4-keypad.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/omap4-keypad.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/omap4-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/omap4-keypad.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='hunk'>@@ -83,6 +84,7 @@ struct omap4_keypad {</div><div class='ctx'> 	bool no_autorepeat;</div><div class='ctx'> 	u64 keys;</div><div class='ctx'> 	unsigned short *keymap;</div><div class='add'>+	struct clk *fck;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)</div><div class='hunk'>@@ -209,6 +211,10 @@ static int omap4_keypad_open(struct input_dev *input)</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='add'>+	error = clk_prepare_enable(keypad_data-&gt;fck);</div><div class='add'>+	if (error)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='ctx'> 	disable_irq(keypad_data-&gt;irq);</div><div class='ctx'> </div><div class='ctx'> 	kbd_writel(keypad_data, OMAP4_KBD_CTRL,</div><div class='hunk'>@@ -226,10 +232,11 @@ static int omap4_keypad_open(struct input_dev *input)</div><div class='ctx'> </div><div class='ctx'> 	enable_irq(keypad_data-&gt;irq);</div><div class='ctx'> </div><div class='add'>+out:</div><div class='ctx'> 	pm_runtime_mark_last_busy(dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void omap4_keypad_stop(struct omap4_keypad *keypad_data)</div><div class='hunk'>@@ -258,6 +265,7 @@ static void omap4_keypad_close(struct input_dev *input)</div><div class='ctx'> 	disable_irq(keypad_data-&gt;irq);</div><div class='ctx'> 	omap4_keypad_stop(keypad_data);</div><div class='ctx'> 	enable_irq(keypad_data-&gt;irq);</div><div class='add'>+	clk_disable_unprepare(keypad_data-&gt;fck);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_mark_last_busy(dev);</div><div class='ctx'> 	pm_runtime_put_autosuspend(dev);</div><div class='hunk'>@@ -356,6 +364,11 @@ static int omap4_keypad_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	keypad_data-&gt;irq = irq;</div><div class='add'>+	keypad_data-&gt;fck = devm_clk_get(&amp;pdev-&gt;dev, "fck");</div><div class='add'>+	if (IS_ERR(keypad_data-&gt;fck))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(keypad_data-&gt;fck),</div><div class='add'>+				     "unable to get fck");</div><div class='add'>+</div><div class='ctx'> 	mutex_init(&amp;keypad_data-&gt;lock);</div><div class='ctx'> 	platform_set_drvdata(pdev, keypad_data);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/keyboard/qt1050.c b/drivers/input/keyboard/qt1050.c<br/>index 6953097db445..b51dfcd76038 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/qt1050.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/qt1050.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/qt1050.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/qt1050.c</a></div><div class='hunk'>@@ -213,7 +213,7 @@ static struct regmap_config qt1050_regmap_config = {</div><div class='ctx'> 	.val_bits = 8,</div><div class='ctx'> 	.max_register = QT1050_RES_CAL,</div><div class='ctx'> </div><div class='del'>-	.cache_type = REGCACHE_RBTREE,</div><div class='add'>+	.cache_type = REGCACHE_MAPLE,</div><div class='ctx'> </div><div class='ctx'> 	.wr_table = &amp;qt1050_writeable_table,</div><div class='ctx'> 	.rd_table = &amp;qt1050_readable_table,</div><div class='head'>diff --git a/drivers/input/keyboard/tca6416-keypad.c b/drivers/input/keyboard/tca6416-keypad.c<br/>index 8af59ced1ec2..677bc4baa5d1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/keyboard/tca6416-keypad.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/keyboard/tca6416-keypad.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/keyboard/tca6416-keypad.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/keyboard/tca6416-keypad.c</a></div><div class='hunk'>@@ -14,7 +14,6 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='del'>-#include &lt;linux/gpio.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/input.h&gt;</div><div class='ctx'> #include &lt;linux/tca6416_keypad.h&gt;</div><div class='head'>diff --git a/drivers/input/misc/da7280.c b/drivers/input/misc/da7280.c<br/>index ce82548916bb..c1fa75c0f970 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/da7280.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/da7280.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/da7280.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/da7280.c</a></div><div class='hunk'>@@ -352,7 +352,7 @@ static int da7280_haptic_set_pwm(struct da7280_haptic *haptics, bool enabled)</div><div class='ctx'> 		state.duty_cycle = period_mag_multi;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	error = pwm_apply_state(haptics-&gt;pwm_dev, &amp;state);</div><div class='add'>+	error = pwm_apply_might_sleep(haptics-&gt;pwm_dev, &amp;state);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		dev_err(haptics-&gt;dev, "Failed to apply pwm state: %d\n", error);</div><div class='ctx'> </div><div class='hunk'>@@ -1175,7 +1175,7 @@ static int da7280_probe(struct i2c_client *client)</div><div class='ctx'> 		/* Sync up PWM state and ensure it is off. */</div><div class='ctx'> 		pwm_init_state(haptics-&gt;pwm_dev, &amp;state);</div><div class='ctx'> 		state.enabled = false;</div><div class='del'>-		error = pwm_apply_state(haptics-&gt;pwm_dev, &amp;state);</div><div class='add'>+		error = pwm_apply_might_sleep(haptics-&gt;pwm_dev, &amp;state);</div><div class='ctx'> 		if (error) {</div><div class='ctx'> 			dev_err(dev, "Failed to apply PWM state: %d\n", error);</div><div class='ctx'> 			return error;</div><div class='head'>diff --git a/drivers/input/misc/da9063_onkey.c b/drivers/input/misc/da9063_onkey.c<br/>index 74808bae326a..c338765e0ecd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/da9063_onkey.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/da9063_onkey.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/da9063_onkey.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/da9063_onkey.c</a></div><div class='hunk'>@@ -9,11 +9,12 @@</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/input.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/pm_wakeirq.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='del'>-#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/da9063/core.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/da9063/registers.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/da9062/core.h&gt;</div><div class='hunk'>@@ -74,13 +75,6 @@ static const struct da906x_chip_config da9062_regs = {</div><div class='ctx'> 	.name = "da9062-onkey",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct of_device_id da9063_compatible_reg_id_table[] = {</div><div class='del'>-	{ .compatible = "dlg,da9063-onkey", .data = &amp;da9063_regs },</div><div class='del'>-	{ .compatible = "dlg,da9062-onkey", .data = &amp;da9062_regs },</div><div class='del'>-	{ },</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(of, da9063_compatible_reg_id_table);</div><div class='del'>-</div><div class='ctx'> static void da9063_poll_on(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct da9063_onkey *onkey = container_of(work,</div><div class='hunk'>@@ -187,56 +181,43 @@ static irqreturn_t da9063_onkey_irq_handler(int irq, void *data)</div><div class='ctx'> static int da9063_onkey_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct da9063_onkey *onkey;</div><div class='del'>-	const struct of_device_id *match;</div><div class='del'>-	int irq;</div><div class='ctx'> 	int error;</div><div class='del'>-</div><div class='del'>-	match = of_match_node(da9063_compatible_reg_id_table,</div><div class='del'>-			      pdev-&gt;dev.of_node);</div><div class='del'>-	if (!match)</div><div class='del'>-		return -ENXIO;</div><div class='add'>+	int irq;</div><div class='ctx'> </div><div class='ctx'> 	onkey = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(struct da9063_onkey),</div><div class='ctx'> 			     GFP_KERNEL);</div><div class='del'>-	if (!onkey) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to allocate memory.\n");</div><div class='add'>+	if (!onkey)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	onkey-&gt;config = match-&gt;data;</div><div class='add'>+	onkey-&gt;config = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (!onkey-&gt;config)</div><div class='add'>+		return -ENXIO;</div><div class='add'>+</div><div class='ctx'> 	onkey-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	onkey-&gt;regmap = dev_get_regmap(pdev-&gt;dev.parent, NULL);</div><div class='del'>-	if (!onkey-&gt;regmap) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Parent regmap unavailable.\n");</div><div class='del'>-		return -ENXIO;</div><div class='del'>-	}</div><div class='add'>+	if (!onkey-&gt;regmap)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, -ENXIO,</div><div class='add'>+				     "Parent regmap unavailable.\n");</div><div class='ctx'> </div><div class='del'>-	onkey-&gt;key_power = !of_property_read_bool(pdev-&gt;dev.of_node,</div><div class='del'>-						  "dlg,disable-key-power");</div><div class='add'>+	onkey-&gt;key_power = !device_property_read_bool(&amp;pdev-&gt;dev,</div><div class='add'>+						      "dlg,disable-key-power");</div><div class='ctx'> </div><div class='ctx'> 	onkey-&gt;input = devm_input_allocate_device(&amp;pdev-&gt;dev);</div><div class='del'>-	if (!onkey-&gt;input) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Failed to allocated input device.\n");</div><div class='add'>+	if (!onkey-&gt;input)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	onkey-&gt;input-&gt;name = onkey-&gt;config-&gt;name;</div><div class='ctx'> 	snprintf(onkey-&gt;phys, sizeof(onkey-&gt;phys), "%s/input0",</div><div class='ctx'> 		 onkey-&gt;config-&gt;name);</div><div class='ctx'> 	onkey-&gt;input-&gt;phys = onkey-&gt;phys;</div><div class='del'>-	onkey-&gt;input-&gt;dev.parent = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	input_set_capability(onkey-&gt;input, EV_KEY, KEY_POWER);</div><div class='ctx'> </div><div class='ctx'> 	error = devm_delayed_work_autocancel(&amp;pdev-&gt;dev, &amp;onkey-&gt;work,</div><div class='ctx'> 					     da9063_poll_on);</div><div class='del'>-	if (error) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev,</div><div class='del'>-			"Failed to add cancel poll action: %d\n",</div><div class='del'>-			error);</div><div class='add'>+	if (error)</div><div class='ctx'> 		return error;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	irq = platform_get_irq_byname(pdev, "ONKEY");</div><div class='ctx'> 	if (irq &lt; 0)</div><div class='hunk'>@@ -246,11 +227,9 @@ static int da9063_onkey_probe(struct platform_device *pdev)</div><div class='ctx'> 					  NULL, da9063_onkey_irq_handler,</div><div class='ctx'> 					  IRQF_TRIGGER_LOW | IRQF_ONESHOT,</div><div class='ctx'> 					  "ONKEY", onkey);</div><div class='del'>-	if (error) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev,</div><div class='del'>-			"Failed to request IRQ %d: %d\n", irq, error);</div><div class='del'>-		return error;</div><div class='del'>-	}</div><div class='add'>+	if (error)</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, error,</div><div class='add'>+				     "Failed to allocate onkey IRQ\n");</div><div class='ctx'> </div><div class='ctx'> 	error = dev_pm_set_wake_irq(&amp;pdev-&gt;dev, irq);</div><div class='ctx'> 	if (error)</div><div class='hunk'>@@ -261,15 +240,19 @@ static int da9063_onkey_probe(struct platform_device *pdev)</div><div class='ctx'> 		device_init_wakeup(&amp;pdev-&gt;dev, true);</div><div class='ctx'> </div><div class='ctx'> 	error = input_register_device(onkey-&gt;input);</div><div class='del'>-	if (error) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev,</div><div class='del'>-			"Failed to register input device: %d\n", error);</div><div class='add'>+	if (error)</div><div class='ctx'> 		return error;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct of_device_id da9063_compatible_reg_id_table[] = {</div><div class='add'>+	{ .compatible = "dlg,da9063-onkey", .data = &amp;da9063_regs },</div><div class='add'>+	{ .compatible = "dlg,da9062-onkey", .data = &amp;da9062_regs },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, da9063_compatible_reg_id_table);</div><div class='add'>+</div><div class='ctx'> static struct platform_driver da9063_onkey_driver = {</div><div class='ctx'> 	.probe	= da9063_onkey_probe,</div><div class='ctx'> 	.driver	= {</div><div class='head'>diff --git a/drivers/input/misc/ims-pcu.c b/drivers/input/misc/ims-pcu.c<br/>index b2f1292e27ef..6e8cc28debd9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/ims-pcu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/ims-pcu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/ims-pcu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/ims-pcu.c</a></div><div class='hunk'>@@ -1050,7 +1050,7 @@ static ssize_t ims_pcu_attribute_show(struct device *dev,</div><div class='ctx'> 			container_of(dattr, struct ims_pcu_attribute, dattr);</div><div class='ctx'> 	char *field = (char *)pcu + attr-&gt;field_offset;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%.*s\n", attr-&gt;field_length, field);</div><div class='add'>+	return sysfs_emit(buf, "%.*s\n", attr-&gt;field_length, field);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ims_pcu_attribute_store(struct device *dev,</div><div class='hunk'>@@ -1206,7 +1206,7 @@ ims_pcu_update_firmware_status_show(struct device *dev,</div><div class='ctx'> 	struct usb_interface *intf = to_usb_interface(dev);</div><div class='ctx'> 	struct ims_pcu *pcu = usb_get_intfdata(intf);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%d\n", pcu-&gt;update_firmware_status);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", pcu-&gt;update_firmware_status);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(update_firmware_status, S_IRUGO,</div><div class='hunk'>@@ -1309,7 +1309,7 @@ static ssize_t ims_pcu_ofn_reg_data_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%x\n", data);</div><div class='add'>+	return sysfs_emit(buf, "%x\n", data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ims_pcu_ofn_reg_data_store(struct device *dev,</div><div class='hunk'>@@ -1344,7 +1344,7 @@ static ssize_t ims_pcu_ofn_reg_addr_show(struct device *dev,</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;pcu-&gt;cmd_mutex);</div><div class='del'>-	error = scnprintf(buf, PAGE_SIZE, "%x\n", pcu-&gt;ofn_reg_addr);</div><div class='add'>+	error = sysfs_emit(buf, "%x\n", pcu-&gt;ofn_reg_addr);</div><div class='ctx'> 	mutex_unlock(&amp;pcu-&gt;cmd_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return error;</div><div class='hunk'>@@ -1397,7 +1397,7 @@ static ssize_t ims_pcu_ofn_bit_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%d\n", !!(data &amp; (1 &lt;&lt; attr-&gt;nr)));</div><div class='add'>+	return sysfs_emit(buf, "%d\n", !!(data &amp; (1 &lt;&lt; attr-&gt;nr)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ims_pcu_ofn_bit_store(struct device *dev,</div><div class='head'>diff --git a/drivers/input/misc/iqs269a.c b/drivers/input/misc/iqs269a.c<br/>index 3c636c75e8a1..cd14ff9f57cf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/iqs269a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/iqs269a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/iqs269a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/iqs269a.c</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'>  * axial sliders presented by the device.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='ctx'> #include &lt;linux/completion.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='hunk'>@@ -26,6 +27,8 @@</div><div class='ctx'> </div><div class='ctx'> #define IQS269_VER_INFO				0x00</div><div class='ctx'> #define IQS269_VER_INFO_PROD_NUM		0x4F</div><div class='add'>+#define IQS269_VER_INFO_FW_NUM_2		0x03</div><div class='add'>+#define IQS269_VER_INFO_FW_NUM_3		0x10</div><div class='ctx'> </div><div class='ctx'> #define IQS269_SYS_FLAGS			0x02</div><div class='ctx'> #define IQS269_SYS_FLAGS_SHOW_RESET		BIT(15)</div><div class='hunk'>@@ -53,6 +56,7 @@</div><div class='ctx'> #define IQS269_SYS_SETTINGS_ULP_UPDATE_MASK	GENMASK(10, 8)</div><div class='ctx'> #define IQS269_SYS_SETTINGS_ULP_UPDATE_SHIFT	8</div><div class='ctx'> #define IQS269_SYS_SETTINGS_ULP_UPDATE_MAX	7</div><div class='add'>+#define IQS269_SYS_SETTINGS_SLIDER_SWIPE	BIT(7)</div><div class='ctx'> #define IQS269_SYS_SETTINGS_RESEED_OFFSET	BIT(6)</div><div class='ctx'> #define IQS269_SYS_SETTINGS_EVENT_MODE		BIT(5)</div><div class='ctx'> #define IQS269_SYS_SETTINGS_EVENT_MODE_LP	BIT(4)</div><div class='hunk'>@@ -69,6 +73,7 @@</div><div class='ctx'> #define IQS269_FILT_STR_MAX			3</div><div class='ctx'> </div><div class='ctx'> #define IQS269_EVENT_MASK_SYS			BIT(6)</div><div class='add'>+#define IQS269_EVENT_MASK_GESTURE		BIT(3)</div><div class='ctx'> #define IQS269_EVENT_MASK_DEEP			BIT(2)</div><div class='ctx'> #define IQS269_EVENT_MASK_TOUCH			BIT(1)</div><div class='ctx'> #define IQS269_EVENT_MASK_PROX			BIT(0)</div><div class='hunk'>@@ -97,6 +102,15 @@</div><div class='ctx'> #define IQS269_MISC_B_TRACKING_UI_ENABLE	BIT(4)</div><div class='ctx'> #define IQS269_MISC_B_FILT_STR_SLIDER		GENMASK(1, 0)</div><div class='ctx'> </div><div class='add'>+#define IQS269_TOUCH_HOLD_SLIDER_SEL		0x89</div><div class='add'>+#define IQS269_TOUCH_HOLD_DEFAULT		0x14</div><div class='add'>+#define IQS269_TOUCH_HOLD_MS_MIN		256</div><div class='add'>+#define IQS269_TOUCH_HOLD_MS_MAX		65280</div><div class='add'>+</div><div class='add'>+#define IQS269_TIMEOUT_TAP_MS_MAX		4080</div><div class='add'>+#define IQS269_TIMEOUT_SWIPE_MS_MAX		4080</div><div class='add'>+#define IQS269_THRESH_SWIPE_MAX			255</div><div class='add'>+</div><div class='ctx'> #define IQS269_CHx_ENG_A_MEAS_CAP_SIZE		BIT(15)</div><div class='ctx'> #define IQS269_CHx_ENG_A_RX_GND_INACTIVE	BIT(13)</div><div class='ctx'> #define IQS269_CHx_ENG_A_LOCAL_CAP_SIZE		BIT(12)</div><div class='hunk'>@@ -142,6 +156,10 @@</div><div class='ctx'> </div><div class='ctx'> #define IQS269_MAX_REG				0xFF</div><div class='ctx'> </div><div class='add'>+#define IQS269_OTP_OPTION_DEFAULT		0x00</div><div class='add'>+#define IQS269_OTP_OPTION_TWS			0xD0</div><div class='add'>+#define IQS269_OTP_OPTION_HOLD			BIT(7)</div><div class='add'>+</div><div class='ctx'> #define IQS269_NUM_CH				8</div><div class='ctx'> #define IQS269_NUM_SL				2</div><div class='ctx'> </div><div class='hunk'>@@ -175,6 +193,20 @@ enum iqs269_event_id {</div><div class='ctx'> 	IQS269_EVENT_DEEP_UP,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum iqs269_slider_id {</div><div class='add'>+	IQS269_SLIDER_NONE,</div><div class='add'>+	IQS269_SLIDER_KEY,</div><div class='add'>+	IQS269_SLIDER_RAW,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum iqs269_gesture_id {</div><div class='add'>+	IQS269_GESTURE_TAP,</div><div class='add'>+	IQS269_GESTURE_HOLD,</div><div class='add'>+	IQS269_GESTURE_FLICK_POS,</div><div class='add'>+	IQS269_GESTURE_FLICK_NEG,</div><div class='add'>+	IQS269_NUM_GESTURES,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct iqs269_switch_desc {</div><div class='ctx'> 	unsigned int code;</div><div class='ctx'> 	bool enabled;</div><div class='hunk'>@@ -234,7 +266,7 @@ struct iqs269_ver_info {</div><div class='ctx'> 	u8 prod_num;</div><div class='ctx'> 	u8 sw_num;</div><div class='ctx'> 	u8 hw_num;</div><div class='del'>-	u8 padding;</div><div class='add'>+	u8 fw_num;</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='ctx'> struct iqs269_ch_reg {</div><div class='hunk'>@@ -285,16 +317,42 @@ struct iqs269_private {</div><div class='ctx'> 	struct regmap *regmap;</div><div class='ctx'> 	struct mutex lock;</div><div class='ctx'> 	struct iqs269_switch_desc switches[ARRAY_SIZE(iqs269_events)];</div><div class='add'>+	struct iqs269_ver_info ver_info;</div><div class='ctx'> 	struct iqs269_sys_reg sys_reg;</div><div class='ctx'> 	struct completion ati_done;</div><div class='ctx'> 	struct input_dev *keypad;</div><div class='ctx'> 	struct input_dev *slider[IQS269_NUM_SL];</div><div class='ctx'> 	unsigned int keycode[ARRAY_SIZE(iqs269_events) * IQS269_NUM_CH];</div><div class='add'>+	unsigned int sl_code[IQS269_NUM_SL][IQS269_NUM_GESTURES];</div><div class='add'>+	unsigned int otp_option;</div><div class='ctx'> 	unsigned int ch_num;</div><div class='ctx'> 	bool hall_enable;</div><div class='ctx'> 	bool ati_current;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static enum iqs269_slider_id iqs269_slider_type(struct iqs269_private *iqs269,</div><div class='add'>+						int slider_num)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Slider 1 is unavailable if the touch-and-hold option is enabled via</div><div class='add'>+	 * OTP. In that case, the channel selection register is repurposed for</div><div class='add'>+	 * the touch-and-hold timer ceiling.</div><div class='add'>+	 */</div><div class='add'>+	if (slider_num &amp;&amp; (iqs269-&gt;otp_option &amp; IQS269_OTP_OPTION_HOLD))</div><div class='add'>+		return IQS269_SLIDER_NONE;</div><div class='add'>+</div><div class='add'>+	if (!iqs269-&gt;sys_reg.slider_select[slider_num])</div><div class='add'>+		return IQS269_SLIDER_NONE;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; IQS269_NUM_GESTURES; i++)</div><div class='add'>+		if (iqs269-&gt;sl_code[slider_num][i] != KEY_RESERVED)</div><div class='add'>+			return IQS269_SLIDER_KEY;</div><div class='add'>+</div><div class='add'>+	return IQS269_SLIDER_RAW;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int iqs269_ati_mode_set(struct iqs269_private *iqs269,</div><div class='ctx'> 			       unsigned int ch_num, unsigned int mode)</div><div class='ctx'> {</div><div class='hunk'>@@ -525,7 +583,8 @@ static int iqs269_parse_chan(struct iqs269_private *iqs269,</div><div class='ctx'> 	if (fwnode_property_present(ch_node, "azoteq,slider0-select"))</div><div class='ctx'> 		iqs269-&gt;sys_reg.slider_select[0] |= BIT(reg);</div><div class='ctx'> </div><div class='del'>-	if (fwnode_property_present(ch_node, "azoteq,slider1-select"))</div><div class='add'>+	if (fwnode_property_present(ch_node, "azoteq,slider1-select") &amp;&amp;</div><div class='add'>+	    !(iqs269-&gt;otp_option &amp; IQS269_OTP_OPTION_HOLD))</div><div class='ctx'> 		iqs269-&gt;sys_reg.slider_select[1] |= BIT(reg);</div><div class='ctx'> </div><div class='ctx'> 	ch_reg = &amp;iqs269-&gt;sys_reg.ch_reg[reg];</div><div class='hunk'>@@ -950,7 +1009,43 @@ static int iqs269_parse_prop(struct iqs269_private *iqs269)</div><div class='ctx'> 	sys_reg-&gt;blocking = 0;</div><div class='ctx'> </div><div class='ctx'> 	sys_reg-&gt;slider_select[0] = 0;</div><div class='del'>-	sys_reg-&gt;slider_select[1] = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If configured via OTP to do so, the device asserts a pulse on the</div><div class='add'>+	 * GPIO4 pin for approximately 60 ms once a selected channel is held</div><div class='add'>+	 * in a state of touch for a configurable length of time.</div><div class='add'>+	 *</div><div class='add'>+	 * In that case, the register used for slider 1 channel selection is</div><div class='add'>+	 * repurposed for the touch-and-hold timer ceiling.</div><div class='add'>+	 */</div><div class='add'>+	if (iqs269-&gt;otp_option &amp; IQS269_OTP_OPTION_HOLD) {</div><div class='add'>+		if (!device_property_read_u32(&amp;client-&gt;dev,</div><div class='add'>+					      "azoteq,touch-hold-ms", &amp;val)) {</div><div class='add'>+			if (val &lt; IQS269_TOUCH_HOLD_MS_MIN ||</div><div class='add'>+			    val &gt; IQS269_TOUCH_HOLD_MS_MAX) {</div><div class='add'>+				dev_err(&amp;client-&gt;dev,</div><div class='add'>+					"Invalid touch-and-hold ceiling: %u\n",</div><div class='add'>+					val);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			sys_reg-&gt;slider_select[1] = val / 256;</div><div class='add'>+		} else if (iqs269-&gt;ver_info.fw_num &lt; IQS269_VER_INFO_FW_NUM_3) {</div><div class='add'>+			/*</div><div class='add'>+			 * The default touch-and-hold timer ceiling initially</div><div class='add'>+			 * read from early revisions of silicon is invalid if</div><div class='add'>+			 * the device experienced a soft reset between power-</div><div class='add'>+			 * on and the read operation.</div><div class='add'>+			 *</div><div class='add'>+			 * To protect against this case, explicitly cache the</div><div class='add'>+			 * default value so that it is restored each time the</div><div class='add'>+			 * device is re-initialized.</div><div class='add'>+			 */</div><div class='add'>+			sys_reg-&gt;slider_select[1] = IQS269_TOUCH_HOLD_DEFAULT;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		sys_reg-&gt;slider_select[1] = 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	sys_reg-&gt;event_mask = ~((u8)IQS269_EVENT_MASK_SYS);</div><div class='ctx'> </div><div class='hunk'>@@ -1004,6 +1099,76 @@ static int iqs269_parse_prop(struct iqs269_private *iqs269)</div><div class='ctx'> 		general |= (val &lt;&lt; IQS269_SYS_SETTINGS_ULP_UPDATE_SHIFT);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (device_property_present(&amp;client-&gt;dev, "linux,keycodes")) {</div><div class='add'>+		int scale = 1;</div><div class='add'>+		int count = device_property_count_u32(&amp;client-&gt;dev,</div><div class='add'>+						      "linux,keycodes");</div><div class='add'>+		if (count &gt; IQS269_NUM_GESTURES * IQS269_NUM_SL) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev, "Too many keycodes present\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		} else if (count &lt; 0) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev, "Failed to count keycodes: %d\n",</div><div class='add'>+				count);</div><div class='add'>+			return count;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		error = device_property_read_u32_array(&amp;client-&gt;dev,</div><div class='add'>+						       "linux,keycodes",</div><div class='add'>+						       *iqs269-&gt;sl_code, count);</div><div class='add'>+		if (error) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev, "Failed to read keycodes: %d\n",</div><div class='add'>+				error);</div><div class='add'>+			return error;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (device_property_present(&amp;client-&gt;dev,</div><div class='add'>+					    "azoteq,gesture-swipe"))</div><div class='add'>+			general |= IQS269_SYS_SETTINGS_SLIDER_SWIPE;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Early revisions of silicon use a more granular step size for</div><div class='add'>+		 * tap and swipe gesture timeouts; scale them appropriately.</div><div class='add'>+		 */</div><div class='add'>+		if (iqs269-&gt;ver_info.fw_num &lt; IQS269_VER_INFO_FW_NUM_3)</div><div class='add'>+			scale = 4;</div><div class='add'>+</div><div class='add'>+		if (!device_property_read_u32(&amp;client-&gt;dev,</div><div class='add'>+					      "azoteq,timeout-tap-ms", &amp;val)) {</div><div class='add'>+			if (val &gt; IQS269_TIMEOUT_TAP_MS_MAX / scale) {</div><div class='add'>+				dev_err(&amp;client-&gt;dev, "Invalid timeout: %u\n",</div><div class='add'>+					val);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			sys_reg-&gt;timeout_tap = val / (16 / scale);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!device_property_read_u32(&amp;client-&gt;dev,</div><div class='add'>+					      "azoteq,timeout-swipe-ms",</div><div class='add'>+					      &amp;val)) {</div><div class='add'>+			if (val &gt; IQS269_TIMEOUT_SWIPE_MS_MAX / scale) {</div><div class='add'>+				dev_err(&amp;client-&gt;dev, "Invalid timeout: %u\n",</div><div class='add'>+					val);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			sys_reg-&gt;timeout_swipe = val / (16 / scale);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!device_property_read_u32(&amp;client-&gt;dev,</div><div class='add'>+					      "azoteq,thresh-swipe", &amp;val)) {</div><div class='add'>+			if (val &gt; IQS269_THRESH_SWIPE_MAX) {</div><div class='add'>+				dev_err(&amp;client-&gt;dev, "Invalid threshold: %u\n",</div><div class='add'>+					val);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			sys_reg-&gt;thresh_swipe = val;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		sys_reg-&gt;event_mask &amp;= ~IQS269_EVENT_MASK_GESTURE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	general &amp;= ~IQS269_SYS_SETTINGS_RESEED_OFFSET;</div><div class='ctx'> 	if (device_property_present(&amp;client-&gt;dev, "azoteq,reseed-offset"))</div><div class='ctx'> 		general |= IQS269_SYS_SETTINGS_RESEED_OFFSET;</div><div class='hunk'>@@ -1012,10 +1177,11 @@ static int iqs269_parse_prop(struct iqs269_private *iqs269)</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * As per the datasheet, enable streaming during normal-power mode if</div><div class='del'>-	 * either slider is in use. In that case, the device returns to event</div><div class='del'>-	 * mode during low-power mode.</div><div class='add'>+	 * raw coordinates will be read from either slider. In that case, the</div><div class='add'>+	 * device returns to event mode during low-power mode.</div><div class='ctx'> 	 */</div><div class='del'>-	if (sys_reg-&gt;slider_select[0] || sys_reg-&gt;slider_select[1])</div><div class='add'>+	if (iqs269_slider_type(iqs269, 0) == IQS269_SLIDER_RAW ||</div><div class='add'>+	    iqs269_slider_type(iqs269, 1) == IQS269_SLIDER_RAW)</div><div class='ctx'> 		general |= IQS269_SYS_SETTINGS_EVENT_MODE_LP;</div><div class='ctx'> </div><div class='ctx'> 	general |= IQS269_SYS_SETTINGS_REDO_ATI;</div><div class='hunk'>@@ -1026,12 +1192,30 @@ static int iqs269_parse_prop(struct iqs269_private *iqs269)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct reg_sequence iqs269_tws_init[] = {</div><div class='add'>+	{ IQS269_TOUCH_HOLD_SLIDER_SEL, IQS269_TOUCH_HOLD_DEFAULT },</div><div class='add'>+	{ 0xF0, 0x580F },</div><div class='add'>+	{ 0xF0, 0x59EF },</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int iqs269_dev_init(struct iqs269_private *iqs269)</div><div class='ctx'> {</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;iqs269-&gt;lock);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Early revisions of silicon require the following workaround in order</div><div class='add'>+	 * to restore any OTP-enabled functionality after a soft reset.</div><div class='add'>+	 */</div><div class='add'>+	if (iqs269-&gt;otp_option == IQS269_OTP_OPTION_TWS &amp;&amp;</div><div class='add'>+	    iqs269-&gt;ver_info.fw_num &lt; IQS269_VER_INFO_FW_NUM_3) {</div><div class='add'>+		error = regmap_multi_reg_write(iqs269-&gt;regmap, iqs269_tws_init,</div><div class='add'>+					       ARRAY_SIZE(iqs269_tws_init));</div><div class='add'>+		if (error)</div><div class='add'>+			goto err_mutex;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	error = regmap_update_bits(iqs269-&gt;regmap, IQS269_HALL_UI,</div><div class='ctx'> 				   IQS269_HALL_UI_ENABLE,</div><div class='ctx'> 				   iqs269-&gt;hall_enable ? ~0 : 0);</div><div class='hunk'>@@ -1106,19 +1290,37 @@ static int iqs269_input_init(struct iqs269_private *iqs269)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IQS269_NUM_SL; i++) {</div><div class='del'>-		if (!iqs269-&gt;sys_reg.slider_select[i])</div><div class='add'>+		if (iqs269_slider_type(iqs269, i) == IQS269_SLIDER_NONE)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		iqs269-&gt;slider[i] = devm_input_allocate_device(&amp;client-&gt;dev);</div><div class='ctx'> 		if (!iqs269-&gt;slider[i])</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+		iqs269-&gt;slider[i]-&gt;keycodemax = ARRAY_SIZE(iqs269-&gt;sl_code[i]);</div><div class='add'>+		iqs269-&gt;slider[i]-&gt;keycode = iqs269-&gt;sl_code[i];</div><div class='add'>+		iqs269-&gt;slider[i]-&gt;keycodesize = sizeof(**iqs269-&gt;sl_code);</div><div class='add'>+</div><div class='ctx'> 		iqs269-&gt;slider[i]-&gt;name = i ? "iqs269a_slider_1"</div><div class='ctx'> 					    : "iqs269a_slider_0";</div><div class='ctx'> 		iqs269-&gt;slider[i]-&gt;id.bustype = BUS_I2C;</div><div class='ctx'> </div><div class='del'>-		input_set_capability(iqs269-&gt;slider[i], EV_KEY, BTN_TOUCH);</div><div class='del'>-		input_set_abs_params(iqs269-&gt;slider[i], ABS_X, 0, 255, 0, 0);</div><div class='add'>+		for (j = 0; j &lt; IQS269_NUM_GESTURES; j++)</div><div class='add'>+			if (iqs269-&gt;sl_code[i][j] != KEY_RESERVED)</div><div class='add'>+				input_set_capability(iqs269-&gt;slider[i], EV_KEY,</div><div class='add'>+						     iqs269-&gt;sl_code[i][j]);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Present the slider as a narrow trackpad if one or more chan-</div><div class='add'>+		 * nels have been selected to participate, but no gestures have</div><div class='add'>+		 * been mapped to a keycode.</div><div class='add'>+		 */</div><div class='add'>+		if (iqs269_slider_type(iqs269, i) == IQS269_SLIDER_RAW) {</div><div class='add'>+			input_set_capability(iqs269-&gt;slider[i],</div><div class='add'>+					     EV_KEY, BTN_TOUCH);</div><div class='add'>+			input_set_abs_params(iqs269-&gt;slider[i],</div><div class='add'>+					     ABS_X, 0, 255, 0, 0);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		error = input_register_device(iqs269-&gt;slider[i]);</div><div class='ctx'> 		if (error) {</div><div class='hunk'>@@ -1167,28 +1369,62 @@ static int iqs269_report(struct iqs269_private *iqs269)</div><div class='ctx'> 	if (be16_to_cpu(flags.system) &amp; IQS269_SYS_FLAGS_IN_ATI)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	error = regmap_raw_read(iqs269-&gt;regmap, IQS269_SLIDER_X, slider_x,</div><div class='del'>-				sizeof(slider_x));</div><div class='del'>-	if (error) {</div><div class='del'>-		dev_err(&amp;client-&gt;dev, "Failed to read slider position: %d\n",</div><div class='del'>-			error);</div><div class='del'>-		return error;</div><div class='add'>+	if (iqs269_slider_type(iqs269, 0) == IQS269_SLIDER_RAW ||</div><div class='add'>+	    iqs269_slider_type(iqs269, 1) == IQS269_SLIDER_RAW) {</div><div class='add'>+		error = regmap_raw_read(iqs269-&gt;regmap, IQS269_SLIDER_X,</div><div class='add'>+					slider_x, sizeof(slider_x));</div><div class='add'>+		if (error) {</div><div class='add'>+			dev_err(&amp;client-&gt;dev,</div><div class='add'>+				"Failed to read slider position: %d\n", error);</div><div class='add'>+			return error;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IQS269_NUM_SL; i++) {</div><div class='del'>-		if (!iqs269-&gt;sys_reg.slider_select[i])</div><div class='add'>+		flags.gesture &gt;&gt;= (i * IQS269_NUM_GESTURES);</div><div class='add'>+</div><div class='add'>+		switch (iqs269_slider_type(iqs269, i)) {</div><div class='add'>+		case IQS269_SLIDER_NONE:</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * Report BTN_TOUCH if any channel that participates in the</div><div class='del'>-		 * slider is in a state of touch.</div><div class='del'>-		 */</div><div class='del'>-		if (flags.states[IQS269_ST_OFFS_TOUCH] &amp;</div><div class='del'>-		    iqs269-&gt;sys_reg.slider_select[i]) {</div><div class='del'>-			input_report_key(iqs269-&gt;slider[i], BTN_TOUCH, 1);</div><div class='del'>-			input_report_abs(iqs269-&gt;slider[i], ABS_X, slider_x[i]);</div><div class='del'>-		} else {</div><div class='del'>-			input_report_key(iqs269-&gt;slider[i], BTN_TOUCH, 0);</div><div class='add'>+		case IQS269_SLIDER_KEY:</div><div class='add'>+			for (j = 0; j &lt; IQS269_NUM_GESTURES; j++)</div><div class='add'>+				input_report_key(iqs269-&gt;slider[i],</div><div class='add'>+						 iqs269-&gt;sl_code[i][j],</div><div class='add'>+						 flags.gesture &amp; BIT(j));</div><div class='add'>+</div><div class='add'>+			if (!(flags.gesture &amp; (BIT(IQS269_GESTURE_FLICK_NEG) |</div><div class='add'>+					       BIT(IQS269_GESTURE_FLICK_POS) |</div><div class='add'>+					       BIT(IQS269_GESTURE_TAP))))</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			input_sync(iqs269-&gt;slider[i]);</div><div class='add'>+</div><div class='add'>+			/*</div><div class='add'>+			 * Momentary gestures are followed by a complementary</div><div class='add'>+			 * release cycle so as to emulate a full keystroke.</div><div class='add'>+			 */</div><div class='add'>+			for (j = 0; j &lt; IQS269_NUM_GESTURES; j++)</div><div class='add'>+				if (j != IQS269_GESTURE_HOLD)</div><div class='add'>+					input_report_key(iqs269-&gt;slider[i],</div><div class='add'>+							 iqs269-&gt;sl_code[i][j],</div><div class='add'>+							 0);</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		case IQS269_SLIDER_RAW:</div><div class='add'>+			/*</div><div class='add'>+			 * The slider is considered to be in a state of touch</div><div class='add'>+			 * if any selected channels are in a state of touch.</div><div class='add'>+			 */</div><div class='add'>+			state = flags.states[IQS269_ST_OFFS_TOUCH];</div><div class='add'>+			state &amp;= iqs269-&gt;sys_reg.slider_select[i];</div><div class='add'>+</div><div class='add'>+			input_report_key(iqs269-&gt;slider[i], BTN_TOUCH, state);</div><div class='add'>+</div><div class='add'>+			if (state)</div><div class='add'>+				input_report_abs(iqs269-&gt;slider[i],</div><div class='add'>+						 ABS_X, slider_x[i]);</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		input_sync(iqs269-&gt;slider[i]);</div><div class='hunk'>@@ -1286,7 +1522,7 @@ static ssize_t counts_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", le16_to_cpu(counts));</div><div class='add'>+	return sysfs_emit(buf, "%u\n", le16_to_cpu(counts));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t hall_bin_show(struct device *dev,</div><div class='hunk'>@@ -1324,7 +1560,7 @@ static ssize_t hall_bin_show(struct device *dev,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", val);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t hall_enable_show(struct device *dev,</div><div class='hunk'>@@ -1332,7 +1568,7 @@ static ssize_t hall_enable_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct iqs269_private *iqs269 = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", iqs269-&gt;hall_enable);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", iqs269-&gt;hall_enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t hall_enable_store(struct device *dev,</div><div class='hunk'>@@ -1362,7 +1598,7 @@ static ssize_t ch_number_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct iqs269_private *iqs269 = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", iqs269-&gt;ch_num);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", iqs269-&gt;ch_num);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ch_number_store(struct device *dev,</div><div class='hunk'>@@ -1391,8 +1627,7 @@ static ssize_t rx_enable_show(struct device *dev,</div><div class='ctx'> 	struct iqs269_private *iqs269 = dev_get_drvdata(dev);</div><div class='ctx'> 	struct iqs269_ch_reg *ch_reg = iqs269-&gt;sys_reg.ch_reg;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n",</div><div class='del'>-			 ch_reg[iqs269-&gt;ch_num].rx_enable);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", ch_reg[iqs269-&gt;ch_num].rx_enable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t rx_enable_store(struct device *dev,</div><div class='hunk'>@@ -1432,7 +1667,7 @@ static ssize_t ati_mode_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", val);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ati_mode_store(struct device *dev,</div><div class='hunk'>@@ -1465,7 +1700,7 @@ static ssize_t ati_base_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", val);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ati_base_store(struct device *dev,</div><div class='hunk'>@@ -1498,7 +1733,7 @@ static ssize_t ati_target_show(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n", val);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ati_target_store(struct device *dev,</div><div class='hunk'>@@ -1525,9 +1760,9 @@ static ssize_t ati_trigger_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct iqs269_private *iqs269 = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n",</div><div class='del'>-			 iqs269-&gt;ati_current &amp;&amp;</div><div class='del'>-			 completion_done(&amp;iqs269-&gt;ati_done));</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			  iqs269-&gt;ati_current &amp;&amp;</div><div class='add'>+			  completion_done(&amp;iqs269-&gt;ati_done));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ati_trigger_store(struct device *dev,</div><div class='hunk'>@@ -1596,7 +1831,6 @@ static const struct regmap_config iqs269_regmap_config = {</div><div class='ctx'> </div><div class='ctx'> static int iqs269_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='del'>-	struct iqs269_ver_info ver_info;</div><div class='ctx'> 	struct iqs269_private *iqs269;</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='hunk'>@@ -1618,14 +1852,16 @@ static int iqs269_probe(struct i2c_client *client)</div><div class='ctx'> 	mutex_init(&amp;iqs269-&gt;lock);</div><div class='ctx'> 	init_completion(&amp;iqs269-&gt;ati_done);</div><div class='ctx'> </div><div class='del'>-	error = regmap_raw_read(iqs269-&gt;regmap, IQS269_VER_INFO, &amp;ver_info,</div><div class='del'>-				sizeof(ver_info));</div><div class='add'>+	iqs269-&gt;otp_option = (uintptr_t)device_get_match_data(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	error = regmap_raw_read(iqs269-&gt;regmap, IQS269_VER_INFO,</div><div class='add'>+				&amp;iqs269-&gt;ver_info, sizeof(iqs269-&gt;ver_info));</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	if (ver_info.prod_num != IQS269_VER_INFO_PROD_NUM) {</div><div class='add'>+	if (iqs269-&gt;ver_info.prod_num != IQS269_VER_INFO_PROD_NUM) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev, "Unrecognized product number: 0x%02X\n",</div><div class='del'>-			ver_info.prod_num);</div><div class='add'>+			iqs269-&gt;ver_info.prod_num);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1728,7 +1964,18 @@ static int iqs269_resume(struct device *dev)</div><div class='ctx'> static DEFINE_SIMPLE_DEV_PM_OPS(iqs269_pm, iqs269_suspend, iqs269_resume);</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id iqs269_of_match[] = {</div><div class='del'>-	{ .compatible = "azoteq,iqs269a" },</div><div class='add'>+	{</div><div class='add'>+		.compatible = "azoteq,iqs269a",</div><div class='add'>+		.data = (void *)IQS269_OTP_OPTION_DEFAULT,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "azoteq,iqs269a-00",</div><div class='add'>+		.data = (void *)IQS269_OTP_OPTION_DEFAULT,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "azoteq,iqs269a-d0",</div><div class='add'>+		.data = (void *)IQS269_OTP_OPTION_TWS,</div><div class='add'>+	},</div><div class='ctx'> 	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, iqs269_of_match);</div><div class='head'>diff --git a/drivers/input/misc/max77693-haptic.c b/drivers/input/misc/max77693-haptic.c<br/>index 80f4416ffe2f..0e646f1b257b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/max77693-haptic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/max77693-haptic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/max77693-haptic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/max77693-haptic.c</a></div><div class='hunk'>@@ -307,7 +307,7 @@ static int max77693_haptic_probe(struct platform_device *pdev)</div><div class='ctx'> 	haptic-&gt;suspend_state = false;</div><div class='ctx'> </div><div class='ctx'> 	/* Variant-specific init */</div><div class='del'>-	haptic-&gt;dev_type = platform_get_device_id(pdev)-&gt;driver_data;</div><div class='add'>+	haptic-&gt;dev_type = max77693-&gt;type;</div><div class='ctx'> 	switch (haptic-&gt;dev_type) {</div><div class='ctx'> 	case TYPE_MAX77693:</div><div class='ctx'> 		haptic-&gt;regmap_haptic = max77693-&gt;regmap_haptic;</div><div class='hunk'>@@ -406,16 +406,24 @@ static DEFINE_SIMPLE_DEV_PM_OPS(max77693_haptic_pm_ops,</div><div class='ctx'> 				max77693_haptic_resume);</div><div class='ctx'> </div><div class='ctx'> static const struct platform_device_id max77693_haptic_id[] = {</div><div class='del'>-	{ "max77693-haptic", TYPE_MAX77693 },</div><div class='del'>-	{ "max77843-haptic", TYPE_MAX77843 },</div><div class='add'>+	{ "max77693-haptic", },</div><div class='add'>+	{ "max77843-haptic", },</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(platform, max77693_haptic_id);</div><div class='ctx'> </div><div class='add'>+static const struct of_device_id of_max77693_haptic_dt_match[] = {</div><div class='add'>+	{ .compatible = "maxim,max77693-haptic", },</div><div class='add'>+	{ .compatible = "maxim,max77843-haptic", },</div><div class='add'>+	{ /* sentinel */ },</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, of_max77693_haptic_dt_match);</div><div class='add'>+</div><div class='ctx'> static struct platform_driver max77693_haptic_driver = {</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "max77693-haptic",</div><div class='ctx'> 		.pm	= pm_sleep_ptr(&amp;max77693_haptic_pm_ops),</div><div class='add'>+		.of_match_table = of_max77693_haptic_dt_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= max77693_haptic_probe,</div><div class='ctx'> 	.id_table	= max77693_haptic_id,</div><div class='head'>diff --git a/drivers/input/misc/pwm-beeper.c b/drivers/input/misc/pwm-beeper.c<br/>index 1e731d8397c6..5b9aedf4362f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/pwm-beeper.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/pwm-beeper.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/pwm-beeper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/pwm-beeper.c</a></div><div class='hunk'>@@ -39,7 +39,7 @@ static int pwm_beeper_on(struct pwm_beeper *beeper, unsigned long period)</div><div class='ctx'> 	state.period = period;</div><div class='ctx'> 	pwm_set_relative_duty_cycle(&amp;state, 50, 100);</div><div class='ctx'> </div><div class='del'>-	error = pwm_apply_state(beeper-&gt;pwm, &amp;state);</div><div class='add'>+	error = pwm_apply_might_sleep(beeper-&gt;pwm, &amp;state);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='hunk'>@@ -138,7 +138,7 @@ static int pwm_beeper_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* Sync up PWM state and ensure it is off. */</div><div class='ctx'> 	pwm_init_state(beeper-&gt;pwm, &amp;state);</div><div class='ctx'> 	state.enabled = false;</div><div class='del'>-	error = pwm_apply_state(beeper-&gt;pwm, &amp;state);</div><div class='add'>+	error = pwm_apply_might_sleep(beeper-&gt;pwm, &amp;state);</div><div class='ctx'> 	if (error) {</div><div class='ctx'> 		dev_err(dev, "failed to apply initial PWM state: %d\n",</div><div class='ctx'> 			error);</div><div class='head'>diff --git a/drivers/input/misc/pwm-vibra.c b/drivers/input/misc/pwm-vibra.c<br/>index acac79c488aa..3e5ed685ed8f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/pwm-vibra.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/pwm-vibra.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/pwm-vibra.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/pwm-vibra.c</a></div><div class='hunk'>@@ -56,7 +56,7 @@ static int pwm_vibrator_start(struct pwm_vibrator *vibrator)</div><div class='ctx'> 	pwm_set_relative_duty_cycle(&amp;state, vibrator-&gt;level, 0xffff);</div><div class='ctx'> 	state.enabled = true;</div><div class='ctx'> </div><div class='del'>-	err = pwm_apply_state(vibrator-&gt;pwm, &amp;state);</div><div class='add'>+	err = pwm_apply_might_sleep(vibrator-&gt;pwm, &amp;state);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(pdev, "failed to apply pwm state: %d\n", err);</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -67,7 +67,7 @@ static int pwm_vibrator_start(struct pwm_vibrator *vibrator)</div><div class='ctx'> 		state.duty_cycle = vibrator-&gt;direction_duty_cycle;</div><div class='ctx'> 		state.enabled = true;</div><div class='ctx'> </div><div class='del'>-		err = pwm_apply_state(vibrator-&gt;pwm_dir, &amp;state);</div><div class='add'>+		err = pwm_apply_might_sleep(vibrator-&gt;pwm_dir, &amp;state);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			dev_err(pdev, "failed to apply dir-pwm state: %d\n", err);</div><div class='ctx'> 			pwm_disable(vibrator-&gt;pwm);</div><div class='hunk'>@@ -160,7 +160,7 @@ static int pwm_vibrator_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* Sync up PWM state and ensure it is off. */</div><div class='ctx'> 	pwm_init_state(vibrator-&gt;pwm, &amp;state);</div><div class='ctx'> 	state.enabled = false;</div><div class='del'>-	err = pwm_apply_state(vibrator-&gt;pwm, &amp;state);</div><div class='add'>+	err = pwm_apply_might_sleep(vibrator-&gt;pwm, &amp;state);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "failed to apply initial PWM state: %d\n",</div><div class='ctx'> 			err);</div><div class='hunk'>@@ -174,7 +174,7 @@ static int pwm_vibrator_probe(struct platform_device *pdev)</div><div class='ctx'> 		/* Sync up PWM state and ensure it is off. */</div><div class='ctx'> 		pwm_init_state(vibrator-&gt;pwm_dir, &amp;state);</div><div class='ctx'> 		state.enabled = false;</div><div class='del'>-		err = pwm_apply_state(vibrator-&gt;pwm_dir, &amp;state);</div><div class='add'>+		err = pwm_apply_might_sleep(vibrator-&gt;pwm_dir, &amp;state);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			dev_err(&amp;pdev-&gt;dev, "failed to apply initial PWM state: %d\n",</div><div class='ctx'> 				err);</div><div class='head'>diff --git a/drivers/input/misc/soc_button_array.c b/drivers/input/misc/soc_button_array.c<br/>index 08bcee3d6bcc..f6d060377d18 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/misc/soc_button_array.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/misc/soc_button_array.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/misc/soc_button_array.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/misc/soc_button_array.c</a></div><div class='hunk'>@@ -299,6 +299,11 @@ static int soc_button_parse_btn_desc(struct device *dev,</div><div class='ctx'> 		info-&gt;name = "power";</div><div class='ctx'> 		info-&gt;event_code = KEY_POWER;</div><div class='ctx'> 		info-&gt;wakeup = true;</div><div class='add'>+	} else if (upage == 0x01 &amp;&amp; usage == 0xc6) {</div><div class='add'>+		info-&gt;name = "airplane mode switch";</div><div class='add'>+		info-&gt;event_type = EV_SW;</div><div class='add'>+		info-&gt;event_code = SW_RFKILL_ALL;</div><div class='add'>+		info-&gt;active_low = false;</div><div class='ctx'> 	} else if (upage == 0x01 &amp;&amp; usage == 0xca) {</div><div class='ctx'> 		info-&gt;name = "rotation lock switch";</div><div class='ctx'> 		info-&gt;event_type = EV_SW;</div><div class='head'>diff --git a/drivers/input/mouse/amimouse.c b/drivers/input/mouse/amimouse.c<br/>index a50e50354832..cda0c3ff5a28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/amimouse.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/amimouse.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/amimouse.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/amimouse.c</a></div><div class='hunk'>@@ -125,16 +125,15 @@ static int __init amimouse_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit amimouse_remove(struct platform_device *pdev)</div><div class='add'>+static void __exit amimouse_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct input_dev *dev = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	input_unregister_device(dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver amimouse_driver = {</div><div class='del'>-	.remove = __exit_p(amimouse_remove),</div><div class='add'>+	.remove_new = __exit_p(amimouse_remove),</div><div class='ctx'> 	.driver   = {</div><div class='ctx'> 		.name	= "amiga-mouse",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/input/mouse/cyapa.c b/drivers/input/mouse/cyapa.c<br/>index a84098448f5b..5979deabe23d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/cyapa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa.c</a></div><div class='hunk'>@@ -756,16 +756,16 @@ static ssize_t cyapa_show_suspend_scanrate(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	switch (pwr_cmd) {</div><div class='ctx'> 	case PWR_MODE_BTN_ONLY:</div><div class='del'>-		len = scnprintf(buf, PAGE_SIZE, "%s\n", BTN_ONLY_MODE_NAME);</div><div class='add'>+		len = sysfs_emit(buf, "%s\n", BTN_ONLY_MODE_NAME);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case PWR_MODE_OFF:</div><div class='del'>-		len = scnprintf(buf, PAGE_SIZE, "%s\n", OFF_MODE_NAME);</div><div class='add'>+		len = sysfs_emit(buf, "%s\n", OFF_MODE_NAME);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		len = scnprintf(buf, PAGE_SIZE, "%u\n",</div><div class='del'>-				cyapa-&gt;gen == CYAPA_GEN3 ?</div><div class='add'>+		len = sysfs_emit(buf, "%u\n",</div><div class='add'>+				 cyapa-&gt;gen == CYAPA_GEN3 ?</div><div class='ctx'> 					cyapa_pwr_cmd_to_sleep_time(pwr_cmd) :</div><div class='ctx'> 					sleep_time);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -877,8 +877,8 @@ static ssize_t cyapa_show_rt_suspend_scanrate(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u\n",</div><div class='del'>-			 cyapa-&gt;gen == CYAPA_GEN3 ?</div><div class='add'>+	return sysfs_emit(buf, "%u\n",</div><div class='add'>+			  cyapa-&gt;gen == CYAPA_GEN3 ?</div><div class='ctx'> 				cyapa_pwr_cmd_to_sleep_time(pwr_cmd) :</div><div class='ctx'> 				sleep_time);</div><div class='ctx'> }</div><div class='hunk'>@@ -988,8 +988,8 @@ static ssize_t cyapa_show_fm_ver(struct device *dev,</div><div class='ctx'> 	error = mutex_lock_interruptible(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='del'>-	error = scnprintf(buf, PAGE_SIZE, "%d.%d\n", cyapa-&gt;fw_maj_ver,</div><div class='del'>-			 cyapa-&gt;fw_min_ver);</div><div class='add'>+	error = sysfs_emit(buf, "%d.%d\n",</div><div class='add'>+			   cyapa-&gt;fw_maj_ver, cyapa-&gt;fw_min_ver);</div><div class='ctx'> 	mutex_unlock(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='hunk'>@@ -1004,7 +1004,7 @@ static ssize_t cyapa_show_product_id(struct device *dev,</div><div class='ctx'> 	error = mutex_lock_interruptible(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='del'>-	size = scnprintf(buf, PAGE_SIZE, "%s\n", cyapa-&gt;product_id);</div><div class='add'>+	size = sysfs_emit(buf, "%s\n", cyapa-&gt;product_id);</div><div class='ctx'> 	mutex_unlock(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='hunk'>@@ -1209,8 +1209,8 @@ static ssize_t cyapa_show_mode(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	size = scnprintf(buf, PAGE_SIZE, "gen%d %s\n",</div><div class='del'>-			cyapa-&gt;gen, cyapa_state_to_string(cyapa));</div><div class='add'>+	size = sysfs_emit(buf, "gen%d %s\n",</div><div class='add'>+			  cyapa-&gt;gen, cyapa_state_to_string(cyapa));</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;cyapa-&gt;state_sync_lock);</div><div class='ctx'> 	return size;</div><div class='head'>diff --git a/drivers/input/mouse/cyapa_gen3.c b/drivers/input/mouse/cyapa_gen3.c<br/>index a97f4acb6452..60c83bc71d84 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/cyapa_gen3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen3.c</a></div><div class='hunk'>@@ -860,7 +860,7 @@ static ssize_t cyapa_gen3_show_baseline(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(dev, "Baseline report successful. Max: %d Min: %d\n",</div><div class='ctx'> 		max_baseline, min_baseline);</div><div class='del'>-	ret = scnprintf(buf, PAGE_SIZE, "%d %d\n", max_baseline, min_baseline);</div><div class='add'>+	ret = sysfs_emit(buf, "%d %d\n", max_baseline, min_baseline);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/input/mouse/cyapa_gen5.c b/drivers/input/mouse/cyapa_gen5.c<br/>index abf42f77b4c5..2e6bcb07257e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/cyapa_gen5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen5.c</a></div><div class='hunk'>@@ -2418,12 +2418,12 @@ resume_scanning:</div><div class='ctx'> 		return resume_error ? resume_error : error;</div><div class='ctx'> </div><div class='ctx'> 	/* 12. Output data strings */</div><div class='del'>-	size = scnprintf(buf, PAGE_SIZE, "%d %d %d %d %d %d %d %d %d %d %d ",</div><div class='add'>+	size = sysfs_emit(buf, "%d %d %d %d %d %d %d %d %d %d %d ",</div><div class='ctx'> 		gidac_mutual_min, gidac_mutual_max, gidac_mutual_ave,</div><div class='ctx'> 		lidac_mutual_min, lidac_mutual_max, lidac_mutual_ave,</div><div class='ctx'> 		gidac_self_rx, gidac_self_tx,</div><div class='ctx'> 		lidac_self_min, lidac_self_max, lidac_self_ave);</div><div class='del'>-	size += scnprintf(buf + size, PAGE_SIZE - size,</div><div class='add'>+	size += sysfs_emit_at(buf, size,</div><div class='ctx'> 		"%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d\n",</div><div class='ctx'> 		raw_cap_mutual_min, raw_cap_mutual_max, raw_cap_mutual_ave,</div><div class='ctx'> 		raw_cap_self_min, raw_cap_self_max, raw_cap_self_ave,</div><div class='head'>diff --git a/drivers/input/mouse/cyapa_gen6.c b/drivers/input/mouse/cyapa_gen6.c<br/>index 0caaf3e64215..4ffe08fee10c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen6.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/cyapa_gen6.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/cyapa_gen6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/cyapa_gen6.c</a></div><div class='hunk'>@@ -629,14 +629,14 @@ static ssize_t cyapa_gen6_show_baseline(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		goto resume_scanning;</div><div class='ctx'> </div><div class='del'>-	size = scnprintf(buf, PAGE_SIZE, "%d %d %d %d %d %d ",</div><div class='del'>-			data[0],  /* RX Attenuator Mutual */</div><div class='del'>-			data[1],  /* IDAC Mutual */</div><div class='del'>-			data[2],  /* RX Attenuator Self RX */</div><div class='del'>-			data[3],  /* IDAC Self RX */</div><div class='del'>-			data[4],  /* RX Attenuator Self TX */</div><div class='del'>-			data[5]	  /* IDAC Self TX */</div><div class='del'>-			);</div><div class='add'>+	size = sysfs_emit(buf, "%d %d %d %d %d %d ",</div><div class='add'>+			  data[0],  /* RX Attenuator Mutual */</div><div class='add'>+			  data[1],  /* IDAC Mutual */</div><div class='add'>+			  data[2],  /* RX Attenuator Self RX */</div><div class='add'>+			  data[3],  /* IDAC Self RX */</div><div class='add'>+			  data[4],  /* RX Attenuator Self TX */</div><div class='add'>+			  data[5]   /* IDAC Self TX */</div><div class='add'>+			 );</div><div class='ctx'> </div><div class='ctx'> 	/* 3. Read Attenuator Trim. */</div><div class='ctx'> 	data_len = sizeof(data);</div><div class='hunk'>@@ -648,8 +648,8 @@ static ssize_t cyapa_gen6_show_baseline(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	/* set attenuator trim values. */</div><div class='ctx'> 	for (i = 0; i &lt; data_len; i++)</div><div class='del'>-		size += scnprintf(buf + size, PAGE_SIZE - size,	"%d ", data[i]);</div><div class='del'>-	size += scnprintf(buf + size, PAGE_SIZE - size, "\n");</div><div class='add'>+		size += sysfs_emit_at(buf, size, "%d ", data[i]);</div><div class='add'>+	size += sysfs_emit_at(buf, size, "\n");</div><div class='ctx'> </div><div class='ctx'> resume_scanning:</div><div class='ctx'> 	/* 4. Resume Scanning*/</div><div class='head'>diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c<br/>index 148a601396f9..8a72c200ccb5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/elan_i2c_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/elan_i2c_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/elan_i2c_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/elan_i2c_core.c</a></div><div class='hunk'>@@ -572,7 +572,7 @@ static ssize_t elan_sysfs_read_fw_checksum(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct elan_tp_data *data = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "0x%04x\n", data-&gt;fw_checksum);</div><div class='add'>+	return sysfs_emit(buf, "0x%04x\n", data-&gt;fw_checksum);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t elan_sysfs_read_product_id(struct device *dev,</div><div class='hunk'>@@ -582,8 +582,8 @@ static ssize_t elan_sysfs_read_product_id(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct elan_tp_data *data = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, ETP_PRODUCT_ID_FORMAT_STRING "\n",</div><div class='del'>-		       data-&gt;product_id);</div><div class='add'>+	return sysfs_emit(buf, ETP_PRODUCT_ID_FORMAT_STRING "\n",</div><div class='add'>+			  data-&gt;product_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t elan_sysfs_read_fw_ver(struct device *dev,</div><div class='hunk'>@@ -593,7 +593,7 @@ static ssize_t elan_sysfs_read_fw_ver(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct elan_tp_data *data = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d.0\n", data-&gt;fw_version);</div><div class='add'>+	return sysfs_emit(buf, "%d.0\n", data-&gt;fw_version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t elan_sysfs_read_sm_ver(struct device *dev,</div><div class='hunk'>@@ -603,7 +603,7 @@ static ssize_t elan_sysfs_read_sm_ver(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct elan_tp_data *data = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d.0\n", data-&gt;sm_version);</div><div class='add'>+	return sysfs_emit(buf, "%d.0\n", data-&gt;sm_version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t elan_sysfs_read_iap_ver(struct device *dev,</div><div class='hunk'>@@ -613,7 +613,7 @@ static ssize_t elan_sysfs_read_iap_ver(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct elan_tp_data *data = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d.0\n", data-&gt;iap_version);</div><div class='add'>+	return sysfs_emit(buf, "%d.0\n", data-&gt;iap_version);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t elan_sysfs_update_fw(struct device *dev,</div><div class='hunk'>@@ -754,7 +754,7 @@ static ssize_t elan_sysfs_read_mode(struct device *dev,</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%d\n", (int)mode);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", (int)mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(product_id, S_IRUGO, elan_sysfs_read_product_id, NULL);</div><div class='hunk'>@@ -858,7 +858,7 @@ static ssize_t min_show(struct device *dev,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	retval = snprintf(buf, PAGE_SIZE, "%d", data-&gt;min_baseline);</div><div class='add'>+	retval = sysfs_emit(buf, "%d", data-&gt;min_baseline);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;data-&gt;sysfs_mutex);</div><div class='hunk'>@@ -881,7 +881,7 @@ static ssize_t max_show(struct device *dev,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	retval = snprintf(buf, PAGE_SIZE, "%d", data-&gt;max_baseline);</div><div class='add'>+	retval = sysfs_emit(buf, "%d", data-&gt;max_baseline);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;data-&gt;sysfs_mutex);</div><div class='head'>diff --git a/drivers/input/mouse/navpoint.c b/drivers/input/mouse/navpoint.c<br/>index c00dc1275da2..ba757783c258 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/navpoint.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/navpoint.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/navpoint.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/navpoint.c</a></div><div class='hunk'>@@ -10,7 +10,7 @@</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/gpio.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/input.h&gt;</div><div class='ctx'> #include &lt;linux/input/navpoint.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='hunk'>@@ -32,7 +32,7 @@ struct navpoint {</div><div class='ctx'> 	struct ssp_device	*ssp;</div><div class='ctx'> 	struct input_dev	*input;</div><div class='ctx'> 	struct device		*dev;</div><div class='del'>-	int			gpio;</div><div class='add'>+	struct gpio_desc	*gpiod;</div><div class='ctx'> 	int			index;</div><div class='ctx'> 	u8			data[1 + HEADER_LENGTH(0xff)];</div><div class='ctx'> };</div><div class='hunk'>@@ -170,16 +170,14 @@ static void navpoint_up(struct navpoint *navpoint)</div><div class='ctx'> 		dev_err(navpoint-&gt;dev,</div><div class='ctx'> 			"timeout waiting for SSSR[CSS] to clear\n");</div><div class='ctx'> </div><div class='del'>-	if (gpio_is_valid(navpoint-&gt;gpio))</div><div class='del'>-		gpio_set_value(navpoint-&gt;gpio, 1);</div><div class='add'>+	gpiod_set_value(navpoint-&gt;gpiod, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void navpoint_down(struct navpoint *navpoint)</div><div class='ctx'> {</div><div class='ctx'> 	struct ssp_device *ssp = navpoint-&gt;ssp;</div><div class='ctx'> </div><div class='del'>-	if (gpio_is_valid(navpoint-&gt;gpio))</div><div class='del'>-		gpio_set_value(navpoint-&gt;gpio, 0);</div><div class='add'>+	gpiod_set_value(navpoint-&gt;gpiod, 0);</div><div class='ctx'> </div><div class='ctx'> 	pxa_ssp_write_reg(ssp, SSCR0, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -216,18 +214,9 @@ static int navpoint_probe(struct platform_device *pdev)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (gpio_is_valid(pdata-&gt;gpio)) {</div><div class='del'>-		error = gpio_request_one(pdata-&gt;gpio, GPIOF_OUT_INIT_LOW,</div><div class='del'>-					 "SYNAPTICS_ON");</div><div class='del'>-		if (error)</div><div class='del'>-			return error;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	ssp = pxa_ssp_request(pdata-&gt;port, pdev-&gt;name);</div><div class='del'>-	if (!ssp) {</div><div class='del'>-		error = -ENODEV;</div><div class='del'>-		goto err_free_gpio;</div><div class='del'>-	}</div><div class='add'>+	if (!ssp)</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	/* HaRET does not disable devices before jumping into Linux */</div><div class='ctx'> 	if (pxa_ssp_read_reg(ssp, SSCR0) &amp; SSCR0_SSE) {</div><div class='hunk'>@@ -242,10 +231,18 @@ static int navpoint_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_free_mem;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	navpoint-&gt;gpiod = gpiod_get_optional(&amp;pdev-&gt;dev,</div><div class='add'>+					     NULL, GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(navpoint-&gt;gpiod)) {</div><div class='add'>+		error = PTR_ERR(navpoint-&gt;gpiod);</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "error getting GPIO\n");</div><div class='add'>+		goto err_free_mem;</div><div class='add'>+	}</div><div class='add'>+	gpiod_set_consumer_name(navpoint-&gt;gpiod, "SYNAPTICS_ON");</div><div class='add'>+</div><div class='ctx'> 	navpoint-&gt;ssp = ssp;</div><div class='ctx'> 	navpoint-&gt;input = input;</div><div class='ctx'> 	navpoint-&gt;dev = &amp;pdev-&gt;dev;</div><div class='del'>-	navpoint-&gt;gpio = pdata-&gt;gpio;</div><div class='ctx'> </div><div class='ctx'> 	input-&gt;name = pdev-&gt;name;</div><div class='ctx'> 	input-&gt;dev.parent = &amp;pdev-&gt;dev;</div><div class='hunk'>@@ -288,17 +285,12 @@ err_free_mem:</div><div class='ctx'> 	input_free_device(input);</div><div class='ctx'> 	kfree(navpoint);</div><div class='ctx'> 	pxa_ssp_free(ssp);</div><div class='del'>-err_free_gpio:</div><div class='del'>-	if (gpio_is_valid(pdata-&gt;gpio))</div><div class='del'>-		gpio_free(pdata-&gt;gpio);</div><div class='ctx'> </div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void navpoint_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct navpoint_platform_data *pdata =</div><div class='del'>-					dev_get_platdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct navpoint *navpoint = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct ssp_device *ssp = navpoint-&gt;ssp;</div><div class='ctx'> </div><div class='hunk'>@@ -308,9 +300,6 @@ static void navpoint_remove(struct platform_device *pdev)</div><div class='ctx'> 	kfree(navpoint);</div><div class='ctx'> </div><div class='ctx'> 	pxa_ssp_free(ssp);</div><div class='del'>-</div><div class='del'>-	if (gpio_is_valid(pdata-&gt;gpio))</div><div class='del'>-		gpio_free(pdata-&gt;gpio);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int navpoint_suspend(struct device *dev)</div><div class='head'>diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c<br/>index 22d16d80efb9..7a303a9d6bf7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/mouse/synaptics.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/mouse/synaptics.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/mouse/synaptics.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/mouse/synaptics.c</a></div><div class='hunk'>@@ -183,6 +183,7 @@ static const char * const smbus_pnp_ids[] = {</div><div class='ctx'> 	"LEN009b", /* T580 */</div><div class='ctx'> 	"LEN0402", /* X1 Extreme Gen 2 / P1 Gen 2 */</div><div class='ctx'> 	"LEN040f", /* P1 Gen 3 */</div><div class='add'>+	"LEN0411", /* L14 Gen 1 */</div><div class='ctx'> 	"LEN200f", /* T450s */</div><div class='ctx'> 	"LEN2044", /* L470  */</div><div class='ctx'> 	"LEN2054", /* E480 */</div><div class='head'>diff --git a/drivers/input/rmi4/rmi_f01.c b/drivers/input/rmi4/rmi_f01.c<br/>index d7603c50f864..cc1d4b424640 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/rmi4/rmi_f01.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/rmi4/rmi_f01.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/rmi4/rmi_f01.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/rmi4/rmi_f01.c</a></div><div class='hunk'>@@ -267,8 +267,7 @@ static ssize_t rmi_driver_manufacturer_id_show(struct device *dev,</div><div class='ctx'> 	struct rmi_driver_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct f01_data *f01 = dev_get_drvdata(&amp;data-&gt;f01_container-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%d\n",</div><div class='del'>-			 f01-&gt;properties.manufacturer_id);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", f01-&gt;properties.manufacturer_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(manufacturer_id, 0444,</div><div class='hunk'>@@ -280,7 +279,7 @@ static ssize_t rmi_driver_dom_show(struct device *dev,</div><div class='ctx'> 	struct rmi_driver_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct f01_data *f01 = dev_get_drvdata(&amp;data-&gt;f01_container-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%s\n", f01-&gt;properties.dom);</div><div class='add'>+	return sysfs_emit(buf, "%s\n", f01-&gt;properties.dom);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(date_of_manufacture, 0444, rmi_driver_dom_show, NULL);</div><div class='hunk'>@@ -292,7 +291,7 @@ static ssize_t rmi_driver_product_id_show(struct device *dev,</div><div class='ctx'> 	struct rmi_driver_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct f01_data *f01 = dev_get_drvdata(&amp;data-&gt;f01_container-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%s\n", f01-&gt;properties.product_id);</div><div class='add'>+	return sysfs_emit(buf, "%s\n", f01-&gt;properties.product_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(product_id, 0444, rmi_driver_product_id_show, NULL);</div><div class='hunk'>@@ -304,7 +303,7 @@ static ssize_t rmi_driver_firmware_id_show(struct device *dev,</div><div class='ctx'> 	struct rmi_driver_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct f01_data *f01 = dev_get_drvdata(&amp;data-&gt;f01_container-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%d\n", f01-&gt;properties.firmware_id);</div><div class='add'>+	return sysfs_emit(buf, "%d\n", f01-&gt;properties.firmware_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(firmware_id, 0444, rmi_driver_firmware_id_show, NULL);</div><div class='hunk'>@@ -318,8 +317,8 @@ static ssize_t rmi_driver_package_id_show(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	u32 package_id = f01-&gt;properties.package_id;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%04x.%04x\n",</div><div class='del'>-			 package_id &amp; 0xffff, (package_id &gt;&gt; 16) &amp; 0xffff);</div><div class='add'>+	return sysfs_emit(buf, "%04x.%04x\n",</div><div class='add'>+			  package_id &amp; 0xffff, (package_id &gt;&gt; 16) &amp; 0xffff);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR(package_id, 0444, rmi_driver_package_id_show, NULL);</div><div class='head'>diff --git a/drivers/input/rmi4/rmi_spi.c b/drivers/input/rmi4/rmi_spi.c<br/>index 852aeb0b2c07..07c866f42296 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/rmi4/rmi_spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/rmi4/rmi_spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/rmi4/rmi_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/rmi4/rmi_spi.c</a></div><div class='hunk'>@@ -375,7 +375,7 @@ static int rmi_spi_probe(struct spi_device *spi)</div><div class='ctx'> 	struct rmi_device_platform_data *spi_pdata = spi-&gt;dev.platform_data;</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='del'>-	if (spi-&gt;master-&gt;flags &amp; SPI_MASTER_HALF_DUPLEX)</div><div class='add'>+	if (spi-&gt;master-&gt;flags &amp; SPI_CONTROLLER_HALF_DUPLEX)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	rmi_spi = devm_kzalloc(&amp;spi-&gt;dev, sizeof(struct rmi_spi_xport),</div><div class='head'>diff --git a/drivers/input/serio/i8042-acpipnpio.h b/drivers/input/serio/i8042-acpipnpio.h<br/>index 9c39553d30fa..b585b1dab870 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/serio/i8042-acpipnpio.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/serio/i8042-acpipnpio.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/serio/i8042-acpipnpio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/serio/i8042-acpipnpio.h</a></div><div class='hunk'>@@ -361,6 +361,14 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = {</div><div class='ctx'> 		.driver_data = (void *)(SERIO_QUIRK_DRITEK)</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		/* Acer TravelMate P459-G2-M */</div><div class='add'>+		.matches = {</div><div class='add'>+			DMI_MATCH(DMI_SYS_VENDOR, "Acer"),</div><div class='add'>+			DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate P459-G2-M"),</div><div class='add'>+		},</div><div class='add'>+		.driver_data = (void *)(SERIO_QUIRK_NOMUX)</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		/* Amoi M636/A737 */</div><div class='ctx'> 		.matches = {</div><div class='ctx'> 			DMI_MATCH(DMI_SYS_VENDOR, "Amoi Electronics CO.,LTD."),</div><div class='head'>diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c<br/>index 20094b9899f0..542a31448c8f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/atmel_mxt_ts.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/atmel_mxt_ts.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/atmel_mxt_ts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/atmel_mxt_ts.c</a></div><div class='hunk'>@@ -2546,7 +2546,7 @@ static const struct vb2_queue mxt_queue = {</div><div class='ctx'> 	.ops = &amp;mxt_queue_ops,</div><div class='ctx'> 	.mem_ops = &amp;vb2_vmalloc_memops,</div><div class='ctx'> 	.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC,</div><div class='del'>-	.min_buffers_needed = 1,</div><div class='add'>+	.min_queued_buffers = 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int mxt_vidioc_querycap(struct file *file, void *priv,</div><div class='hunk'>@@ -2818,8 +2818,8 @@ static ssize_t mxt_fw_version_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct mxt_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct mxt_info *info = data-&gt;info;</div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u.%u.%02X\n",</div><div class='del'>-			 info-&gt;version &gt;&gt; 4, info-&gt;version &amp; 0xf, info-&gt;build);</div><div class='add'>+	return sysfs_emit(buf, "%u.%u.%02X\n",</div><div class='add'>+			  info-&gt;version &gt;&gt; 4, info-&gt;version &amp; 0xf, info-&gt;build);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Hardware Version is returned as FamilyID.VariantID */</div><div class='hunk'>@@ -2828,8 +2828,7 @@ static ssize_t mxt_hw_version_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct mxt_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct mxt_info *info = data-&gt;info;</div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u.%u\n",</div><div class='del'>-			 info-&gt;family_id, info-&gt;variant_id);</div><div class='add'>+	return sysfs_emit(buf, "%u.%u\n", info-&gt;family_id, info-&gt;variant_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t mxt_show_instance(char *buf, int count,</div><div class='hunk'>@@ -2839,19 +2838,18 @@ static ssize_t mxt_show_instance(char *buf, int count,</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (mxt_obj_instances(object) &gt; 1)</div><div class='del'>-		count += scnprintf(buf + count, PAGE_SIZE - count,</div><div class='del'>-				   "Instance %u\n", instance);</div><div class='add'>+		count += sysfs_emit_at(buf, count, "Instance %u\n", instance);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; mxt_obj_size(object); i++)</div><div class='del'>-		count += scnprintf(buf + count, PAGE_SIZE - count,</div><div class='del'>-				"\t[%2u]: %02x (%d)\n", i, val[i], val[i]);</div><div class='del'>-	count += scnprintf(buf + count, PAGE_SIZE - count, "\n");</div><div class='add'>+		count += sysfs_emit_at(buf, count, "\t[%2u]: %02x (%d)\n",</div><div class='add'>+				       i, val[i], val[i]);</div><div class='add'>+	count += sysfs_emit_at(buf, count, "\n");</div><div class='ctx'> </div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t mxt_object_show(struct device *dev,</div><div class='del'>-				    struct device_attribute *attr, char *buf)</div><div class='add'>+			       struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct mxt_data *data = dev_get_drvdata(dev);</div><div class='ctx'> 	struct mxt_object *object;</div><div class='hunk'>@@ -2872,8 +2870,7 @@ static ssize_t mxt_object_show(struct device *dev,</div><div class='ctx'> 		if (!mxt_object_readable(object-&gt;type))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		count += scnprintf(buf + count, PAGE_SIZE - count,</div><div class='del'>-				"T%u:\n", object-&gt;type);</div><div class='add'>+		count += sysfs_emit_at(buf, count, "T%u:\n", object-&gt;type);</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; mxt_obj_instances(object); j++) {</div><div class='ctx'> 			u16 size = mxt_obj_size(object);</div><div class='head'>diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c<br/>index 3e102bcc4a1c..2a1db1134476 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/edt-ft5x06.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/edt-ft5x06.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/edt-ft5x06.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/edt-ft5x06.c</a></div><div class='hunk'>@@ -431,7 +431,7 @@ static ssize_t edt_ft5x06_setting_show(struct device *dev,</div><div class='ctx'> 		*field = val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	count = scnprintf(buf, PAGE_SIZE, "%d\n", val);</div><div class='add'>+	count = sysfs_emit(buf, "%d\n", val);</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;tsdata-&gt;mutex);</div><div class='ctx'> 	return error ?: count;</div><div class='head'>diff --git a/drivers/input/touchscreen/hideep.c b/drivers/input/touchscreen/hideep.c<br/>index 0f58258306bf..eae90676f4e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/hideep.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/hideep.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/hideep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/hideep.c</a></div><div class='hunk'>@@ -928,8 +928,7 @@ static ssize_t hideep_fw_version_show(struct device *dev,</div><div class='ctx'> 	ssize_t len;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ts-&gt;dev_mutex);</div><div class='del'>-	len = scnprintf(buf, PAGE_SIZE, "%04x\n",</div><div class='del'>-			be16_to_cpu(ts-&gt;dwz_info.release_ver));</div><div class='add'>+	len = sysfs_emit(buf, "%04x\n", be16_to_cpu(ts-&gt;dwz_info.release_ver));</div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;dev_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return len;</div><div class='hunk'>@@ -943,8 +942,7 @@ static ssize_t hideep_product_id_show(struct device *dev,</div><div class='ctx'> 	ssize_t len;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ts-&gt;dev_mutex);</div><div class='del'>-	len = scnprintf(buf, PAGE_SIZE, "%04x\n",</div><div class='del'>-			be16_to_cpu(ts-&gt;dwz_info.product_id));</div><div class='add'>+	len = sysfs_emit(buf, "%04x\n", be16_to_cpu(ts-&gt;dwz_info.product_id));</div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;dev_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return len;</div><div class='head'>diff --git a/drivers/input/touchscreen/hycon-hy46xx.c b/drivers/input/touchscreen/hycon-hy46xx.c<br/>index d0f257989fd6..2e01d87977c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/hycon-hy46xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/hycon-hy46xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/hycon-hy46xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/hycon-hy46xx.c</a></div><div class='hunk'>@@ -202,7 +202,7 @@ static ssize_t hycon_hy46xx_setting_show(struct device *dev,</div><div class='ctx'> 		*field = val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	count = scnprintf(buf, PAGE_SIZE, "%d\n", val);</div><div class='add'>+	count = sysfs_emit(buf, "%d\n", val);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;tsdata-&gt;mutex);</div><div class='head'>diff --git a/drivers/input/touchscreen/ilitek_ts_i2c.c b/drivers/input/touchscreen/ilitek_ts_i2c.c<br/>index 90c4934e750a..fc4e39b6651a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/ilitek_ts_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/ilitek_ts_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/ilitek_ts_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/ilitek_ts_i2c.c</a></div><div class='hunk'>@@ -512,12 +512,12 @@ static ssize_t firmware_version_show(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct ilitek_ts_data *ts = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE,</div><div class='del'>-			 "fw version: [%02X%02X.%02X%02X.%02X%02X.%02X%02X]\n",</div><div class='del'>-			 ts-&gt;firmware_ver[0], ts-&gt;firmware_ver[1],</div><div class='del'>-			 ts-&gt;firmware_ver[2], ts-&gt;firmware_ver[3],</div><div class='del'>-			 ts-&gt;firmware_ver[4], ts-&gt;firmware_ver[5],</div><div class='del'>-			 ts-&gt;firmware_ver[6], ts-&gt;firmware_ver[7]);</div><div class='add'>+	return sysfs_emit(buf,</div><div class='add'>+			  "fw version: [%02X%02X.%02X%02X.%02X%02X.%02X%02X]\n",</div><div class='add'>+			  ts-&gt;firmware_ver[0], ts-&gt;firmware_ver[1],</div><div class='add'>+			  ts-&gt;firmware_ver[2], ts-&gt;firmware_ver[3],</div><div class='add'>+			  ts-&gt;firmware_ver[4], ts-&gt;firmware_ver[5],</div><div class='add'>+			  ts-&gt;firmware_ver[6], ts-&gt;firmware_ver[7]);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(firmware_version);</div><div class='ctx'> </div><div class='hunk'>@@ -527,8 +527,8 @@ static ssize_t product_id_show(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct ilitek_ts_data *ts = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "product id: [%04X], module: [%s]\n",</div><div class='del'>-			 ts-&gt;mcu_ver, ts-&gt;product_id);</div><div class='add'>+	return sysfs_emit(buf, "product id: [%04X], module: [%s]\n",</div><div class='add'>+			  ts-&gt;mcu_ver, ts-&gt;product_id);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(product_id);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/touchscreen/iqs5xx.c b/drivers/input/touchscreen/iqs5xx.c<br/>index a3f4fb85bee5..4d226118f3cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/iqs5xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/iqs5xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/iqs5xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/iqs5xx.c</a></div><div class='hunk'>@@ -943,12 +943,12 @@ static ssize_t fw_info_show(struct device *dev,</div><div class='ctx'> 	if (!iqs5xx-&gt;dev_id_info.bl_status)</div><div class='ctx'> 		return -ENODATA;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u.%u.%u.%u:%u.%u\n",</div><div class='del'>-			 be16_to_cpu(iqs5xx-&gt;dev_id_info.prod_num),</div><div class='del'>-			 be16_to_cpu(iqs5xx-&gt;dev_id_info.proj_num),</div><div class='del'>-			 iqs5xx-&gt;dev_id_info.major_ver,</div><div class='del'>-			 iqs5xx-&gt;dev_id_info.minor_ver,</div><div class='del'>-			 iqs5xx-&gt;exp_file[0], iqs5xx-&gt;exp_file[1]);</div><div class='add'>+	return sysfs_emit(buf, "%u.%u.%u.%u:%u.%u\n",</div><div class='add'>+			  be16_to_cpu(iqs5xx-&gt;dev_id_info.prod_num),</div><div class='add'>+			  be16_to_cpu(iqs5xx-&gt;dev_id_info.proj_num),</div><div class='add'>+			  iqs5xx-&gt;dev_id_info.major_ver,</div><div class='add'>+			  iqs5xx-&gt;dev_id_info.minor_ver,</div><div class='add'>+			  iqs5xx-&gt;exp_file[0], iqs5xx-&gt;exp_file[1]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR_WO(fw_file);</div><div class='head'>diff --git a/drivers/input/touchscreen/iqs7211.c b/drivers/input/touchscreen/iqs7211.c<br/>index dc084f873762..f0a56cde899e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/iqs7211.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/iqs7211.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/iqs7211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/iqs7211.c</a></div><div class='hunk'>@@ -2401,12 +2401,12 @@ static ssize_t fw_info_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct iqs7211_private *iqs7211 = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%u.%u.%u.%u:%u.%u\n",</div><div class='del'>-			 le16_to_cpu(iqs7211-&gt;ver_info.prod_num),</div><div class='del'>-			 le32_to_cpu(iqs7211-&gt;ver_info.patch),</div><div class='del'>-			 le16_to_cpu(iqs7211-&gt;ver_info.major),</div><div class='del'>-			 le16_to_cpu(iqs7211-&gt;ver_info.minor),</div><div class='del'>-			 iqs7211-&gt;exp_file[1], iqs7211-&gt;exp_file[0]);</div><div class='add'>+	return sysfs_emit(buf, "%u.%u.%u.%u:%u.%u\n",</div><div class='add'>+			  le16_to_cpu(iqs7211-&gt;ver_info.prod_num),</div><div class='add'>+			  le32_to_cpu(iqs7211-&gt;ver_info.patch),</div><div class='add'>+			  le16_to_cpu(iqs7211-&gt;ver_info.major),</div><div class='add'>+			  le16_to_cpu(iqs7211-&gt;ver_info.minor),</div><div class='add'>+			  iqs7211-&gt;exp_file[1], iqs7211-&gt;exp_file[0]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEVICE_ATTR_RO(fw_info);</div><div class='head'>diff --git a/drivers/input/touchscreen/melfas_mip4.c b/drivers/input/touchscreen/melfas_mip4.c<br/>index aa325486f618..78e1c63e530e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/melfas_mip4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/melfas_mip4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/melfas_mip4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/melfas_mip4.c</a></div><div class='hunk'>@@ -1336,9 +1336,9 @@ static ssize_t mip4_sysfs_read_fw_version(struct device *dev,</div><div class='ctx'> 	/* Take lock to prevent racing with firmware update */</div><div class='ctx'> 	mutex_lock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	count = snprintf(buf, PAGE_SIZE, "%04X %04X %04X %04X\n",</div><div class='del'>-			 ts-&gt;fw_version.boot, ts-&gt;fw_version.core,</div><div class='del'>-			 ts-&gt;fw_version.app, ts-&gt;fw_version.param);</div><div class='add'>+	count = sysfs_emit(buf, "%04X %04X %04X %04X\n",</div><div class='add'>+			   ts-&gt;fw_version.boot, ts-&gt;fw_version.core,</div><div class='add'>+			   ts-&gt;fw_version.app, ts-&gt;fw_version.param);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1362,8 +1362,8 @@ static ssize_t mip4_sysfs_read_hw_version(struct device *dev,</div><div class='ctx'> 	 * product_name shows the name or version of the hardware</div><div class='ctx'> 	 * paired with current firmware in the chip.</div><div class='ctx'> 	 */</div><div class='del'>-	count = snprintf(buf, PAGE_SIZE, "%.*s\n",</div><div class='del'>-			 (int)sizeof(ts-&gt;product_name), ts-&gt;product_name);</div><div class='add'>+	count = sysfs_emit(buf, "%.*s\n",</div><div class='add'>+			   (int)sizeof(ts-&gt;product_name), ts-&gt;product_name);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1382,7 +1382,7 @@ static ssize_t mip4_sysfs_read_product_id(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	count = snprintf(buf, PAGE_SIZE, "%04X\n", ts-&gt;product_id);</div><div class='add'>+	count = sysfs_emit(buf, "%04X\n", ts-&gt;product_id);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1401,8 +1401,8 @@ static ssize_t mip4_sysfs_read_ic_name(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	count = snprintf(buf, PAGE_SIZE, "%.*s\n",</div><div class='del'>-			 (int)sizeof(ts-&gt;ic_name), ts-&gt;ic_name);</div><div class='add'>+	count = sysfs_emit(buf, "%.*s\n",</div><div class='add'>+			   (int)sizeof(ts-&gt;ic_name), ts-&gt;ic_name);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;ts-&gt;input-&gt;mutex);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/touchscreen/sur40.c b/drivers/input/touchscreen/sur40.c<br/>index 8ddb3f7d307a..ae3aab428337 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/sur40.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/sur40.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/sur40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/sur40.c</a></div><div class='hunk'>@@ -847,9 +847,10 @@ static int sur40_queue_setup(struct vb2_queue *q,</div><div class='ctx'> 		       unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct sur40_state *sur40 = vb2_get_drv_priv(q);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(q);</div><div class='ctx'> </div><div class='del'>-	if (q-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - q-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes)</div><div class='ctx'> 		return sizes[0] &lt; sur40-&gt;pix_fmt.sizeimage ? -EINVAL : 0;</div><div class='hunk'>@@ -1123,7 +1124,7 @@ static const struct vb2_queue sur40_queue = {</div><div class='ctx'> 	.ops = &amp;sur40_queue_ops,</div><div class='ctx'> 	.mem_ops = &amp;vb2_dma_sg_memops,</div><div class='ctx'> 	.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC,</div><div class='del'>-	.min_buffers_needed = 3,</div><div class='add'>+	.min_queued_buffers = 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_file_operations sur40_video_fops = {</div><div class='head'>diff --git a/drivers/input/touchscreen/usbtouchscreen.c b/drivers/input/touchscreen/usbtouchscreen.c<br/>index d6d04b9f04fc..60354ebc7242 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/usbtouchscreen.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/usbtouchscreen.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/usbtouchscreen.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/usbtouchscreen.c</a></div><div class='hunk'>@@ -456,8 +456,8 @@ static ssize_t mtouch_firmware_rev_show(struct device *dev,</div><div class='ctx'> 	struct usbtouch_usb *usbtouch = usb_get_intfdata(intf);</div><div class='ctx'> 	struct mtouch_priv *priv = usbtouch-&gt;priv;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(output, PAGE_SIZE, "%1x.%1x\n",</div><div class='del'>-			 priv-&gt;fw_rev_major, priv-&gt;fw_rev_minor);</div><div class='add'>+	return sysfs_emit(output, "%1x.%1x\n",</div><div class='add'>+			  priv-&gt;fw_rev_major, priv-&gt;fw_rev_minor);</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR(firmware_rev, 0444, mtouch_firmware_rev_show, NULL);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/input/touchscreen/wdt87xx_i2c.c b/drivers/input/touchscreen/wdt87xx_i2c.c<br/>index 128341a6696b..32c7be54434c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/wdt87xx_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/wdt87xx_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/wdt87xx_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/wdt87xx_i2c.c</a></div><div class='hunk'>@@ -887,7 +887,7 @@ static ssize_t config_csum_show(struct device *dev,</div><div class='ctx'> 	cfg_csum = wdt-&gt;param.xmls_id1;</div><div class='ctx'> 	cfg_csum = (cfg_csum &lt;&lt; 16) | wdt-&gt;param.xmls_id2;</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%x\n", cfg_csum);</div><div class='add'>+	return sysfs_emit(buf, "%x\n", cfg_csum);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t fw_version_show(struct device *dev,</div><div class='hunk'>@@ -896,7 +896,7 @@ static ssize_t fw_version_show(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct wdt87xx_data *wdt = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%x\n", wdt-&gt;param.fw_id);</div><div class='add'>+	return sysfs_emit(buf, "%x\n", wdt-&gt;param.fw_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t plat_id_show(struct device *dev,</div><div class='hunk'>@@ -905,7 +905,7 @@ static ssize_t plat_id_show(struct device *dev,</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(dev);</div><div class='ctx'> 	struct wdt87xx_data *wdt = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='del'>-	return scnprintf(buf, PAGE_SIZE, "%x\n", wdt-&gt;param.plat_id);</div><div class='add'>+	return sysfs_emit(buf, "%x\n", wdt-&gt;param.plat_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t update_config_store(struct device *dev,</div><div class='head'>diff --git a/drivers/input/touchscreen/zforce_ts.c b/drivers/input/touchscreen/zforce_ts.c<br/>index 5be5112845e1..5680075f0bb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/zforce_ts.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/touchscreen/zforce_ts.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/touchscreen/zforce_ts.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/touchscreen/zforce_ts.c</a></div><div class='hunk'>@@ -20,6 +20,7 @@</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/sysfs.h&gt;</div><div class='ctx'> #include &lt;linux/input/mt.h&gt;</div><div class='add'>+#include &lt;linux/input/touchscreen.h&gt;</div><div class='ctx'> #include &lt;linux/platform_data/zforce_ts.h&gt;</div><div class='ctx'> #include &lt;linux/regulator/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='hunk'>@@ -106,6 +107,7 @@ struct zforce_point {</div><div class='ctx'> struct zforce_ts {</div><div class='ctx'> 	struct i2c_client	*client;</div><div class='ctx'> 	struct input_dev	*input;</div><div class='add'>+	struct touchscreen_properties prop;</div><div class='ctx'> 	const struct zforce_ts_platdata *pdata;</div><div class='ctx'> 	char			phys[32];</div><div class='ctx'> </div><div class='hunk'>@@ -266,7 +268,6 @@ static int zforce_setconfig(struct zforce_ts *ts, char b1)</div><div class='ctx'> static int zforce_start(struct zforce_ts *ts)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = ts-&gt;client;</div><div class='del'>-	const struct zforce_ts_platdata *pdata = ts-&gt;pdata;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;client-&gt;dev, "starting device\n");</div><div class='hunk'>@@ -277,7 +278,7 @@ static int zforce_start(struct zforce_ts *ts)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = zforce_resolution(ts, pdata-&gt;x_max, pdata-&gt;y_max);</div><div class='add'>+	ret = zforce_resolution(ts, ts-&gt;prop.max_x, ts-&gt;prop.max_y);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev, "Unable to set resolution, %d\n", ret);</div><div class='ctx'> 		goto error;</div><div class='hunk'>@@ -337,7 +338,6 @@ static int zforce_stop(struct zforce_ts *ts)</div><div class='ctx'> static int zforce_touch_event(struct zforce_ts *ts, u8 *payload)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = ts-&gt;client;</div><div class='del'>-	const struct zforce_ts_platdata *pdata = ts-&gt;pdata;</div><div class='ctx'> 	struct zforce_point point;</div><div class='ctx'> 	int count, i, num = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -355,8 +355,8 @@ static int zforce_touch_event(struct zforce_ts *ts, u8 *payload)</div><div class='ctx'> 		point.coord_y =</div><div class='ctx'> 			payload[9 * i + 4] &lt;&lt; 8 | payload[9 * i + 3];</div><div class='ctx'> </div><div class='del'>-		if (point.coord_x &gt; pdata-&gt;x_max ||</div><div class='del'>-		    point.coord_y &gt; pdata-&gt;y_max) {</div><div class='add'>+		if (point.coord_x &gt; ts-&gt;prop.max_x ||</div><div class='add'>+		    point.coord_y &gt; ts-&gt;prop.max_y) {</div><div class='ctx'> 			dev_warn(&amp;client-&gt;dev, "coordinates (%d,%d) invalid\n",</div><div class='ctx'> 				point.coord_x, point.coord_y);</div><div class='ctx'> 			point.coord_x = point.coord_y = 0;</div><div class='hunk'>@@ -390,10 +390,9 @@ static int zforce_touch_event(struct zforce_ts *ts, u8 *payload)</div><div class='ctx'> 						point.state != STATE_UP);</div><div class='ctx'> </div><div class='ctx'> 		if (point.state != STATE_UP) {</div><div class='del'>-			input_report_abs(ts-&gt;input, ABS_MT_POSITION_X,</div><div class='del'>-					 point.coord_x);</div><div class='del'>-			input_report_abs(ts-&gt;input, ABS_MT_POSITION_Y,</div><div class='del'>-					 point.coord_y);</div><div class='add'>+			touchscreen_report_pos(ts-&gt;input, &amp;ts-&gt;prop,</div><div class='add'>+					       point.coord_x, point.coord_y,</div><div class='add'>+					       true);</div><div class='ctx'> 			input_report_abs(ts-&gt;input, ABS_MT_TOUCH_MAJOR,</div><div class='ctx'> 					 point.area_major);</div><div class='ctx'> 			input_report_abs(ts-&gt;input, ABS_MT_TOUCH_MINOR,</div><div class='hunk'>@@ -719,15 +718,8 @@ static struct zforce_ts_platdata *zforce_parse_dt(struct device *dev)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (of_property_read_u32(np, "x-size", &amp;pdata-&gt;x_max)) {</div><div class='del'>-		dev_err(dev, "failed to get x-size property\n");</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (of_property_read_u32(np, "y-size", &amp;pdata-&gt;y_max)) {</div><div class='del'>-		dev_err(dev, "failed to get y-size property\n");</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-	}</div><div class='add'>+	of_property_read_u32(np, "x-size", &amp;pdata-&gt;x_max);</div><div class='add'>+	of_property_read_u32(np, "y-size", &amp;pdata-&gt;y_max);</div><div class='ctx'> </div><div class='ctx'> 	return pdata;</div><div class='ctx'> }</div><div class='hunk'>@@ -856,6 +848,12 @@ static int zforce_probe(struct i2c_client *client)</div><div class='ctx'> 	input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0,</div><div class='ctx'> 			     pdata-&gt;y_max, 0, 0);</div><div class='ctx'> </div><div class='add'>+	touchscreen_parse_properties(input_dev, true, &amp;ts-&gt;prop);</div><div class='add'>+	if (ts-&gt;prop.max_x == 0 || ts-&gt;prop.max_y == 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "no size specified\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0,</div><div class='ctx'> 			     ZFORCE_MAX_AREA, 0, 0);</div><div class='ctx'> 	input_set_abs_params(input_dev, ABS_MT_TOUCH_MINOR, 0,</div><div class='head'>diff --git a/drivers/input/vivaldi-fmap.c b/drivers/input/vivaldi-fmap.c<br/>index 6dae83d96806..0d29ec014e2f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/input/vivaldi-fmap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/input/vivaldi-fmap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/input/vivaldi-fmap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/input/vivaldi-fmap.c</a></div><div class='hunk'>@@ -27,10 +27,10 @@ ssize_t vivaldi_function_row_physmap_show(const struct vivaldi_data *data,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; data-&gt;num_function_row_keys; i++)</div><div class='del'>-		size += scnprintf(buf + size, PAGE_SIZE - size,</div><div class='del'>-				  "%s%02X", size ? " " : "", physmap[i]);</div><div class='add'>+		size += sysfs_emit_at(buf, size,</div><div class='add'>+				      "%s%02X", size ? " " : "", physmap[i]);</div><div class='ctx'> 	if (size)</div><div class='del'>-		size += scnprintf(buf + size, PAGE_SIZE - size, "\n");</div><div class='add'>+		size += sysfs_emit_at(buf, size, "\n");</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c<br/>index dfab160ca529..50bac2d79d9b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/core.c</a></div><div class='hunk'>@@ -395,6 +395,9 @@ struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;icc_lock);</div><div class='ctx'> </div><div class='add'>+	if (!node)</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='ctx'> 	if (IS_ERR(node))</div><div class='ctx'> 		return ERR_CAST(node);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c<br/>index b43325364aa3..8c40f4182263 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/imx/imx8mm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mm.c</a></div><div class='hunk'>@@ -86,16 +86,9 @@ static int imx8mm_icc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx8mm_icc_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	imx_icc_unregister(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct platform_driver imx8mm_icc_driver = {</div><div class='ctx'> 	.probe = imx8mm_icc_probe,</div><div class='del'>-	.remove = imx8mm_icc_remove,</div><div class='add'>+	.remove_new = imx_icc_unregister,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "imx8mm-interconnect",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c<br/>index 8ce6d8e4bf5e..fa3d4f97dfa4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mn.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/imx/imx8mn.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mn.c</a></div><div class='hunk'>@@ -75,16 +75,9 @@ static int imx8mn_icc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx8mn_icc_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	imx_icc_unregister(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct platform_driver imx8mn_icc_driver = {</div><div class='ctx'> 	.probe = imx8mn_icc_probe,</div><div class='del'>-	.remove = imx8mn_icc_remove,</div><div class='add'>+	.remove_new = imx_icc_unregister,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "imx8mn-interconnect",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/interconnect/imx/imx8mp.c b/drivers/interconnect/imx/imx8mp.c<br/>index a66ae3638b18..d218bb47757a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/imx/imx8mp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mp.c</a></div><div class='hunk'>@@ -239,16 +239,9 @@ static int imx8mp_icc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx8mp_icc_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	imx_icc_unregister(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct platform_driver imx8mp_icc_driver = {</div><div class='ctx'> 	.probe = imx8mp_icc_probe,</div><div class='del'>-	.remove = imx8mp_icc_remove,</div><div class='add'>+	.remove_new = imx_icc_unregister,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "imx8mp-interconnect",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c<br/>index b6fb71305c99..8bbd672b346e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/imx/imx8mq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/imx/imx8mq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/imx/imx8mq.c</a></div><div class='hunk'>@@ -85,16 +85,9 @@ static int imx8mq_icc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx8mq_icc_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	imx_icc_unregister(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct platform_driver imx8mq_icc_driver = {</div><div class='ctx'> 	.probe = imx8mq_icc_probe,</div><div class='del'>-	.remove = imx8mq_icc_remove,</div><div class='add'>+	.remove_new = imx_icc_unregister,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "imx8mq-interconnect",</div><div class='ctx'> 		.sync_state = icc_sync_state,</div><div class='head'>diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig<br/>index 62b516d38d03..697f96c49f6f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/Kconfig</a></div><div class='hunk'>@@ -191,6 +191,15 @@ config INTERCONNECT_QCOM_SDX75</div><div class='ctx'> 	  This is a driver for the Qualcomm Network-on-Chip on sdx75-based</div><div class='ctx'> 	  platforms.</div><div class='ctx'> </div><div class='add'>+config INTERCONNECT_QCOM_SM6115</div><div class='add'>+	tristate "Qualcomm SM6115 interconnect driver"</div><div class='add'>+	depends on INTERCONNECT_QCOM</div><div class='add'>+	depends on QCOM_SMD_RPM</div><div class='add'>+	select INTERCONNECT_QCOM_SMD_RPM</div><div class='add'>+	help</div><div class='add'>+	  This is a driver for the Qualcomm Network-on-Chip on sm6115-based</div><div class='add'>+	  platforms.</div><div class='add'>+</div><div class='ctx'> config INTERCONNECT_QCOM_SM6350</div><div class='ctx'> 	tristate "Qualcomm SM6350 interconnect driver"</div><div class='ctx'> 	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE</div><div class='hunk'>@@ -245,5 +254,23 @@ config INTERCONNECT_QCOM_SM8550</div><div class='ctx'> 	  This is a driver for the Qualcomm Network-on-Chip on SM8550-based</div><div class='ctx'> 	  platforms.</div><div class='ctx'> </div><div class='add'>+config INTERCONNECT_QCOM_SM8650</div><div class='add'>+	tristate "Qualcomm SM8650 interconnect driver"</div><div class='add'>+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE</div><div class='add'>+	select INTERCONNECT_QCOM_RPMH</div><div class='add'>+	select INTERCONNECT_QCOM_BCM_VOTER</div><div class='add'>+	help</div><div class='add'>+	  This is a driver for the Qualcomm Network-on-Chip on SM8650-based</div><div class='add'>+	  platforms.</div><div class='add'>+</div><div class='add'>+config INTERCONNECT_QCOM_X1E80100</div><div class='add'>+	tristate "Qualcomm X1E80100 interconnect driver"</div><div class='add'>+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE</div><div class='add'>+	select INTERCONNECT_QCOM_RPMH</div><div class='add'>+	select INTERCONNECT_QCOM_BCM_VOTER</div><div class='add'>+	help</div><div class='add'>+	  This is a driver for the Qualcomm Network-on-Chip on X1E80100-based</div><div class='add'>+	  platforms.</div><div class='add'>+</div><div class='ctx'> config INTERCONNECT_QCOM_SMD_RPM</div><div class='ctx'> 	tristate</div><div class='head'>diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile<br/>index c5320e293960..704846165022 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/Makefile</a></div><div class='hunk'>@@ -24,12 +24,15 @@ qnoc-sdm845-objs			:= sdm845.o</div><div class='ctx'> qnoc-sdx55-objs				:= sdx55.o</div><div class='ctx'> qnoc-sdx65-objs				:= sdx65.o</div><div class='ctx'> qnoc-sdx75-objs				:= sdx75.o</div><div class='add'>+qnoc-sm6115-objs			:= sm6115.o</div><div class='ctx'> qnoc-sm6350-objs			:= sm6350.o</div><div class='ctx'> qnoc-sm8150-objs			:= sm8150.o</div><div class='ctx'> qnoc-sm8250-objs			:= sm8250.o</div><div class='ctx'> qnoc-sm8350-objs			:= sm8350.o</div><div class='ctx'> qnoc-sm8450-objs			:= sm8450.o</div><div class='ctx'> qnoc-sm8550-objs			:= sm8550.o</div><div class='add'>+qnoc-sm8650-objs			:= sm8650.o</div><div class='add'>+qnoc-x1e80100-objs			:= x1e80100.o</div><div class='ctx'> icc-smd-rpm-objs			:= smd-rpm.o icc-rpm.o icc-rpm-clocks.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o</div><div class='hunk'>@@ -53,10 +56,13 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o</div><div class='add'>+obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o</div><div class='add'>+obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o</div><div class='add'>+obj-$(CONFIG_INTERCONNECT_QCOM_X1E80100) += qnoc-x1e80100.o</div><div class='ctx'> obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o</div><div class='head'>diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c<br/>index 628e651c555c..a8ed435f696c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/icc-rpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/icc-rpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/icc-rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/icc-rpm.c</a></div><div class='hunk'>@@ -307,7 +307,7 @@ static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node</div><div class='ctx'> </div><div class='ctx'> 	if (qn-&gt;ib_coeff) {</div><div class='ctx'> 		agg_peak_rate = qn-&gt;max_peak[ctx] * 100;</div><div class='del'>-		agg_peak_rate = div_u64(qn-&gt;max_peak[ctx], qn-&gt;ib_coeff);</div><div class='add'>+		agg_peak_rate = div_u64(agg_peak_rate, qn-&gt;ib_coeff);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		agg_peak_rate = qn-&gt;max_peak[ctx];</div><div class='ctx'> 	}</div><div class='hunk'>@@ -627,14 +627,12 @@ err_disable_unprepare_clk:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(qnoc_probe);</div><div class='ctx'> </div><div class='del'>-int qnoc_remove(struct platform_device *pdev)</div><div class='add'>+void qnoc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_icc_provider *qp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	icc_provider_deregister(&amp;qp-&gt;provider);</div><div class='ctx'> 	icc_nodes_remove(&amp;qp-&gt;provider);</div><div class='ctx'> 	clk_disable_unprepare(qp-&gt;bus_clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(qnoc_remove);</div><div class='head'>diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h<br/>index a13768cfd231..f4883d43eae4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/icc-rpm.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/icc-rpm.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/icc-rpm.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/icc-rpm.h</a></div><div class='hunk'>@@ -161,7 +161,7 @@ extern const struct rpm_clk_resource aggre1_branch_clk;</div><div class='ctx'> extern const struct rpm_clk_resource aggre2_branch_clk;</div><div class='ctx'> </div><div class='ctx'> int qnoc_probe(struct platform_device *pdev);</div><div class='del'>-int qnoc_remove(struct platform_device *pdev);</div><div class='add'>+void qnoc_remove(struct platform_device *pdev);</div><div class='ctx'> </div><div class='ctx'> bool qcom_icc_rpm_smd_available(void);</div><div class='ctx'> int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);</div><div class='head'>diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c<br/>index 35148880b3e8..499b1a9ac413 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8916.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/msm8916.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8916.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8916.c</a></div><div class='hunk'>@@ -1344,7 +1344,7 @@ MODULE_DEVICE_TABLE(of, msm8916_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver msm8916_noc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-msm8916",</div><div class='ctx'> 		.of_match_table = msm8916_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c<br/>index b52c5ac1175c..8ff2c23b1ca0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8939.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/msm8939.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8939.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8939.c</a></div><div class='hunk'>@@ -1421,7 +1421,7 @@ MODULE_DEVICE_TABLE(of, msm8939_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver msm8939_noc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-msm8939",</div><div class='ctx'> 		.of_match_table = msm8939_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c<br/>index 21f6c852141e..241076b5f36b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8974.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/msm8974.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8974.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8974.c</a></div><div class='hunk'>@@ -740,15 +740,13 @@ err_remove_nodes:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int msm8974_icc_remove(struct platform_device *pdev)</div><div class='add'>+static void msm8974_icc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct msm8974_icc_provider *qp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	icc_provider_deregister(&amp;qp-&gt;provider);</div><div class='ctx'> 	icc_nodes_remove(&amp;qp-&gt;provider);</div><div class='ctx'> 	clk_bulk_disable_unprepare(qp-&gt;num_clks, qp-&gt;bus_clks);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id msm8974_noc_of_match[] = {</div><div class='hunk'>@@ -764,7 +762,7 @@ MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver msm8974_noc_driver = {</div><div class='ctx'> 	.probe = msm8974_icc_probe,</div><div class='del'>-	.remove = msm8974_icc_remove,</div><div class='add'>+	.remove_new = msm8974_icc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-msm8974",</div><div class='ctx'> 		.of_match_table = msm8974_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c<br/>index b73566c9b21f..788131400cd1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8996.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/msm8996.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/msm8996.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/msm8996.c</a></div><div class='hunk'>@@ -2108,7 +2108,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qnoc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-msm8996",</div><div class='ctx'> 		.of_match_table = qnoc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c<br/>index e97478bbc282..61a8695a9adc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/osm-l3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/osm-l3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/osm-l3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/osm-l3.c</a></div><div class='hunk'>@@ -148,14 +148,12 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qcom_osm_l3_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_osm_l3_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	icc_provider_deregister(&amp;qp-&gt;provider);</div><div class='ctx'> 	icc_nodes_remove(&amp;qp-&gt;provider);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qcom_osm_l3_probe(struct platform_device *pdev)</div><div class='hunk'>@@ -292,7 +290,7 @@ MODULE_DEVICE_TABLE(of, osm_l3_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver osm_l3_driver = {</div><div class='ctx'> 	.probe = qcom_osm_l3_probe,</div><div class='del'>-	.remove = qcom_osm_l3_remove,</div><div class='add'>+	.remove_new = qcom_osm_l3_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "osm-l3",</div><div class='ctx'> 		.of_match_table = osm_l3_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c<br/>index b88cf9a022e0..96735800b13c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/qcm2290.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/qcm2290.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/qcm2290.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/qcm2290.c</a></div><div class='hunk'>@@ -1367,7 +1367,7 @@ MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcm2290_noc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-qcm2290",</div><div class='ctx'> 		.of_match_table = qcm2290_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c<br/>index 9fa1da70c843..11b49a89c03d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/qcs404.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/qcs404.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/qcs404.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/qcs404.c</a></div><div class='hunk'>@@ -1083,7 +1083,7 @@ MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcs404_noc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-qcs404",</div><div class='ctx'> 		.of_match_table = qcs404_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c<br/>index 7392bebba334..ab91de446da8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sdm660.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/sdm660.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sdm660.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sdm660.c</a></div><div class='hunk'>@@ -1714,7 +1714,7 @@ MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sdm660_noc_driver = {</div><div class='ctx'> 	.probe = qnoc_probe,</div><div class='del'>-	.remove = qnoc_remove,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-sdm660",</div><div class='ctx'> 		.of_match_table = sdm660_noc_of_match,</div><div class='head'>diff --git a/drivers/interconnect/qcom/sm6115.c b/drivers/interconnect/qcom/sm6115.c<br/>new file mode 100644<br/>index 000000000000..88b67634aa2f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sm6115.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm6115.c</a></div><div class='hunk'>@@ -0,0 +1,1423 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,sm6115.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/interconnect-provider.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#include "icc-rpm.h"</div><div class='add'>+</div><div class='add'>+static const char * const snoc_intf_clocks[] = {</div><div class='add'>+	"cpu_axi",</div><div class='add'>+	"ufs_axi",</div><div class='add'>+	"usb_axi",</div><div class='add'>+	"ipa", /* Required by qxm_ipa */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char * const cnoc_intf_clocks[] = {</div><div class='add'>+	"usb_axi",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	SM6115_MASTER_AMPSS_M0,</div><div class='add'>+	SM6115_MASTER_ANOC_SNOC,</div><div class='add'>+	SM6115_MASTER_BIMC_SNOC,</div><div class='add'>+	SM6115_MASTER_CAMNOC_HF,</div><div class='add'>+	SM6115_MASTER_CAMNOC_SF,</div><div class='add'>+	SM6115_MASTER_CRYPTO_CORE0,</div><div class='add'>+	SM6115_MASTER_GRAPHICS_3D,</div><div class='add'>+	SM6115_MASTER_IPA,</div><div class='add'>+	SM6115_MASTER_MDP_PORT0,</div><div class='add'>+	SM6115_MASTER_PIMEM,</div><div class='add'>+	SM6115_MASTER_QDSS_BAM,</div><div class='add'>+	SM6115_MASTER_QDSS_DAP,</div><div class='add'>+	SM6115_MASTER_QDSS_ETR,</div><div class='add'>+	SM6115_MASTER_QPIC,</div><div class='add'>+	SM6115_MASTER_QUP_0,</div><div class='add'>+	SM6115_MASTER_QUP_CORE_0,</div><div class='add'>+	SM6115_MASTER_SDCC_1,</div><div class='add'>+	SM6115_MASTER_SDCC_2,</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC_NRT,</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC_RT,</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC,</div><div class='add'>+	SM6115_MASTER_SNOC_CFG,</div><div class='add'>+	SM6115_MASTER_SNOC_CNOC,</div><div class='add'>+	SM6115_MASTER_TCU_0,</div><div class='add'>+	SM6115_MASTER_TIC,</div><div class='add'>+	SM6115_MASTER_USB3,</div><div class='add'>+	SM6115_MASTER_VIDEO_P0,</div><div class='add'>+	SM6115_MASTER_VIDEO_PROC,</div><div class='add'>+</div><div class='add'>+	SM6115_SLAVE_AHB2PHY_USB,</div><div class='add'>+	SM6115_SLAVE_ANOC_SNOC,</div><div class='add'>+	SM6115_SLAVE_APPSS,</div><div class='add'>+	SM6115_SLAVE_APSS_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_BIMC_CFG,</div><div class='add'>+	SM6115_SLAVE_BIMC_SNOC,</div><div class='add'>+	SM6115_SLAVE_BOOT_ROM,</div><div class='add'>+	SM6115_SLAVE_CAMERA_CFG,</div><div class='add'>+	SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_CLK_CTL,</div><div class='add'>+	SM6115_SLAVE_CNOC_MSS,</div><div class='add'>+	SM6115_SLAVE_CRYPTO_0_CFG,</div><div class='add'>+	SM6115_SLAVE_DCC_CFG,</div><div class='add'>+	SM6115_SLAVE_DDR_PHY_CFG,</div><div class='add'>+	SM6115_SLAVE_DDR_SS_CFG,</div><div class='add'>+	SM6115_SLAVE_DISPLAY_CFG,</div><div class='add'>+	SM6115_SLAVE_DISPLAY_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_EBI_CH0,</div><div class='add'>+	SM6115_SLAVE_GPU_CFG,</div><div class='add'>+	SM6115_SLAVE_GPU_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_HWKM_CORE,</div><div class='add'>+	SM6115_SLAVE_IMEM_CFG,</div><div class='add'>+	SM6115_SLAVE_IPA_CFG,</div><div class='add'>+	SM6115_SLAVE_LPASS,</div><div class='add'>+	SM6115_SLAVE_MAPSS,</div><div class='add'>+	SM6115_SLAVE_MDSP_MPU_CFG,</div><div class='add'>+	SM6115_SLAVE_MESSAGE_RAM,</div><div class='add'>+	SM6115_SLAVE_OCIMEM,</div><div class='add'>+	SM6115_SLAVE_PDM,</div><div class='add'>+	SM6115_SLAVE_PIMEM_CFG,</div><div class='add'>+	SM6115_SLAVE_PIMEM,</div><div class='add'>+	SM6115_SLAVE_PKA_CORE,</div><div class='add'>+	SM6115_SLAVE_PMIC_ARB,</div><div class='add'>+	SM6115_SLAVE_QDSS_CFG,</div><div class='add'>+	SM6115_SLAVE_QDSS_STM,</div><div class='add'>+	SM6115_SLAVE_QM_CFG,</div><div class='add'>+	SM6115_SLAVE_QM_MPU_CFG,</div><div class='add'>+	SM6115_SLAVE_QPIC,</div><div class='add'>+	SM6115_SLAVE_QUP_0,</div><div class='add'>+	SM6115_SLAVE_QUP_CORE_0,</div><div class='add'>+	SM6115_SLAVE_RBCPR_CX_CFG,</div><div class='add'>+	SM6115_SLAVE_RBCPR_MX_CFG,</div><div class='add'>+	SM6115_SLAVE_RPM,</div><div class='add'>+	SM6115_SLAVE_SDCC_1,</div><div class='add'>+	SM6115_SLAVE_SDCC_2,</div><div class='add'>+	SM6115_SLAVE_SECURITY,</div><div class='add'>+	SM6115_SLAVE_SERVICE_CNOC,</div><div class='add'>+	SM6115_SLAVE_SERVICE_SNOC,</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC_NRT,</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC_RT,</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC,</div><div class='add'>+	SM6115_SLAVE_SNOC_CFG,</div><div class='add'>+	SM6115_SLAVE_SNOC_CNOC,</div><div class='add'>+	SM6115_SLAVE_TCSR,</div><div class='add'>+	SM6115_SLAVE_TCU,</div><div class='add'>+	SM6115_SLAVE_TLMM,</div><div class='add'>+	SM6115_SLAVE_USB3,</div><div class='add'>+	SM6115_SLAVE_VENUS_CFG,</div><div class='add'>+	SM6115_SLAVE_VENUS_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_VSENSE_CTRL_CFG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_ebi_slv_bimc_snoc_links[] = {</div><div class='add'>+	SM6115_SLAVE_EBI_CH0,</div><div class='add'>+	SM6115_SLAVE_BIMC_SNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node apps_proc = {</div><div class='add'>+	.name = "apps_proc",</div><div class='add'>+	.id = SM6115_MASTER_AMPSS_M0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 0,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.prio_level = 0,</div><div class='add'>+	.qos.areq_prio = 0,</div><div class='add'>+	.mas_rpm_id = 0,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links),</div><div class='add'>+	.links = slv_ebi_slv_bimc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 link_slv_ebi[] = {</div><div class='add'>+	SM6115_SLAVE_EBI_CH0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_snoc_bimc_rt = {</div><div class='add'>+	.name = "mas_snoc_bimc_rt",</div><div class='add'>+	.id = SM6115_MASTER_SNOC_BIMC_RT,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 2,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,</div><div class='add'>+	.qos.areq_prio = 0,</div><div class='add'>+	.qos.prio_level = 0,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_ebi),</div><div class='add'>+	.links = link_slv_ebi,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_snoc_bimc_nrt = {</div><div class='add'>+	.name = "mas_snoc_bimc_nrt",</div><div class='add'>+	.id = SM6115_MASTER_SNOC_BIMC_NRT,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 3,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,</div><div class='add'>+	.qos.areq_prio = 0,</div><div class='add'>+	.qos.prio_level = 0,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_ebi),</div><div class='add'>+	.links = link_slv_ebi,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_snoc_bimc = {</div><div class='add'>+	.name = "mas_snoc_bimc",</div><div class='add'>+	.id = SM6115_MASTER_SNOC_BIMC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 6,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_BYPASS,</div><div class='add'>+	.qos.areq_prio = 0,</div><div class='add'>+	.qos.prio_level = 0,</div><div class='add'>+	.mas_rpm_id = 3,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_ebi),</div><div class='add'>+	.links = link_slv_ebi,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gpu = {</div><div class='add'>+	.name = "qnm_gpu",</div><div class='add'>+	.id = SM6115_MASTER_GRAPHICS_3D,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.qos.qos_port = 1,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.prio_level = 0,</div><div class='add'>+	.qos.areq_prio = 0,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links),</div><div class='add'>+	.links = slv_ebi_slv_bimc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node tcu_0 = {</div><div class='add'>+	.name = "tcu_0",</div><div class='add'>+	.id = SM6115_MASTER_TCU_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 4,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.prio_level = 6,</div><div class='add'>+	.qos.areq_prio = 6,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links),</div><div class='add'>+	.links = slv_ebi_slv_bimc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 qup_core_0_links[] = {</div><div class='add'>+	SM6115_SLAVE_QUP_CORE_0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_master = {</div><div class='add'>+	.name = "qup0_core_master",</div><div class='add'>+	.id = SM6115_MASTER_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = 170,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(qup_core_0_links),</div><div class='add'>+	.links = qup_core_0_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 link_slv_anoc_snoc[] = {</div><div class='add'>+	SM6115_SLAVE_ANOC_SNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node crypto_c0 = {</div><div class='add'>+	.name = "crypto_c0",</div><div class='add'>+	.id = SM6115_MASTER_CRYPTO_CORE0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 43,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = 23,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 mas_snoc_cnoc_links[] = {</div><div class='add'>+	SM6115_SLAVE_AHB2PHY_USB,</div><div class='add'>+	SM6115_SLAVE_APSS_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_BIMC_CFG,</div><div class='add'>+	SM6115_SLAVE_BOOT_ROM,</div><div class='add'>+	SM6115_SLAVE_CAMERA_CFG,</div><div class='add'>+	SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_CLK_CTL,</div><div class='add'>+	SM6115_SLAVE_CNOC_MSS,</div><div class='add'>+	SM6115_SLAVE_CRYPTO_0_CFG,</div><div class='add'>+	SM6115_SLAVE_DCC_CFG,</div><div class='add'>+	SM6115_SLAVE_DDR_PHY_CFG,</div><div class='add'>+	SM6115_SLAVE_DDR_SS_CFG,</div><div class='add'>+	SM6115_SLAVE_DISPLAY_CFG,</div><div class='add'>+	SM6115_SLAVE_DISPLAY_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_GPU_CFG,</div><div class='add'>+	SM6115_SLAVE_GPU_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_HWKM_CORE,</div><div class='add'>+	SM6115_SLAVE_IMEM_CFG,</div><div class='add'>+	SM6115_SLAVE_IPA_CFG,</div><div class='add'>+	SM6115_SLAVE_LPASS,</div><div class='add'>+	SM6115_SLAVE_MAPSS,</div><div class='add'>+	SM6115_SLAVE_MDSP_MPU_CFG,</div><div class='add'>+	SM6115_SLAVE_MESSAGE_RAM,</div><div class='add'>+	SM6115_SLAVE_PDM,</div><div class='add'>+	SM6115_SLAVE_PIMEM_CFG,</div><div class='add'>+	SM6115_SLAVE_PKA_CORE,</div><div class='add'>+	SM6115_SLAVE_PMIC_ARB,</div><div class='add'>+	SM6115_SLAVE_QDSS_CFG,</div><div class='add'>+	SM6115_SLAVE_QM_CFG,</div><div class='add'>+	SM6115_SLAVE_QM_MPU_CFG,</div><div class='add'>+	SM6115_SLAVE_QPIC,</div><div class='add'>+	SM6115_SLAVE_QUP_0,</div><div class='add'>+	SM6115_SLAVE_RBCPR_CX_CFG,</div><div class='add'>+	SM6115_SLAVE_RBCPR_MX_CFG,</div><div class='add'>+	SM6115_SLAVE_RPM,</div><div class='add'>+	SM6115_SLAVE_SDCC_1,</div><div class='add'>+	SM6115_SLAVE_SDCC_2,</div><div class='add'>+	SM6115_SLAVE_SECURITY,</div><div class='add'>+	SM6115_SLAVE_SERVICE_CNOC,</div><div class='add'>+	SM6115_SLAVE_SNOC_CFG,</div><div class='add'>+	SM6115_SLAVE_TCSR,</div><div class='add'>+	SM6115_SLAVE_TLMM,</div><div class='add'>+	SM6115_SLAVE_USB3,</div><div class='add'>+	SM6115_SLAVE_VENUS_CFG,</div><div class='add'>+	SM6115_SLAVE_VENUS_THROTTLE_CFG,</div><div class='add'>+	SM6115_SLAVE_VSENSE_CTRL_CFG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_snoc_cnoc = {</div><div class='add'>+	.name = "mas_snoc_cnoc",</div><div class='add'>+	.id = SM6115_MASTER_SNOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_snoc_cnoc_links),</div><div class='add'>+	.links = mas_snoc_cnoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_dap = {</div><div class='add'>+	.name = "xm_dap",</div><div class='add'>+	.id = SM6115_MASTER_QDSS_DAP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_snoc_cnoc_links),</div><div class='add'>+	.links = mas_snoc_cnoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 link_slv_snoc_bimc_nrt[] = {</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC_NRT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camera_nrt = {</div><div class='add'>+	.name = "qnm_camera_nrt",</div><div class='add'>+	.id = SM6115_MASTER_CAMNOC_SF,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.qos.qos_port = 25,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 3,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt),</div><div class='add'>+	.links = link_slv_snoc_bimc_nrt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_venus0 = {</div><div class='add'>+	.name = "qxm_venus0",</div><div class='add'>+	.id = SM6115_MASTER_VIDEO_P0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 30,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 3,</div><div class='add'>+	.qos.urg_fwd_en = true,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt),</div><div class='add'>+	.links = link_slv_snoc_bimc_nrt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_venus_cpu = {</div><div class='add'>+	.name = "qxm_venus_cpu",</div><div class='add'>+	.id = SM6115_MASTER_VIDEO_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 34,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt),</div><div class='add'>+	.links = link_slv_snoc_bimc_nrt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 link_slv_snoc_bimc_rt[] = {</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC_RT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camera_rt = {</div><div class='add'>+	.name = "qnm_camera_rt",</div><div class='add'>+	.id = SM6115_MASTER_CAMNOC_HF,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.qos.qos_port = 31,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 3,</div><div class='add'>+	.qos.urg_fwd_en = true,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt),</div><div class='add'>+	.links = link_slv_snoc_bimc_rt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_mdp0 = {</div><div class='add'>+	.name = "qxm_mdp0",</div><div class='add'>+	.id = SM6115_MASTER_MDP_PORT0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.qos.qos_port = 26,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 3,</div><div class='add'>+	.qos.urg_fwd_en = true,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt),</div><div class='add'>+	.links = link_slv_snoc_bimc_rt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_service_snoc_links[] = {</div><div class='add'>+	SM6115_SLAVE_SERVICE_SNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_snoc_cfg = {</div><div class='add'>+	.name = "qhm_snoc_cfg",</div><div class='add'>+	.id = SM6115_MASTER_SNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_service_snoc_links),</div><div class='add'>+	.links = slv_service_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 mas_tic_links[] = {</div><div class='add'>+	SM6115_SLAVE_APPSS,</div><div class='add'>+	SM6115_SLAVE_OCIMEM,</div><div class='add'>+	SM6115_SLAVE_PIMEM,</div><div class='add'>+	SM6115_SLAVE_QDSS_STM,</div><div class='add'>+	SM6115_SLAVE_TCU,</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC,</div><div class='add'>+	SM6115_SLAVE_SNOC_CNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_tic = {</div><div class='add'>+	.name = "qhm_tic",</div><div class='add'>+	.id = SM6115_MASTER_TIC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.qos.qos_port = 29,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_tic_links),</div><div class='add'>+	.links = mas_tic_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_anoc_snoc = {</div><div class='add'>+	.name = "mas_anoc_snoc",</div><div class='add'>+	.id = SM6115_MASTER_ANOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_tic_links),</div><div class='add'>+	.links = mas_tic_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 mas_bimc_snoc_links[] = {</div><div class='add'>+	SM6115_SLAVE_APPSS,</div><div class='add'>+	SM6115_SLAVE_SNOC_CNOC,</div><div class='add'>+	SM6115_SLAVE_OCIMEM,</div><div class='add'>+	SM6115_SLAVE_PIMEM,</div><div class='add'>+	SM6115_SLAVE_QDSS_STM,</div><div class='add'>+	SM6115_SLAVE_TCU,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node mas_bimc_snoc = {</div><div class='add'>+	.name = "mas_bimc_snoc",</div><div class='add'>+	.id = SM6115_MASTER_BIMC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = 21,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_bimc_snoc_links),</div><div class='add'>+	.links = mas_bimc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 mas_pimem_links[] = {</div><div class='add'>+	SM6115_SLAVE_OCIMEM,</div><div class='add'>+	SM6115_SLAVE_SNOC_BIMC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_pimem = {</div><div class='add'>+	.name = "qxm_pimem",</div><div class='add'>+	.id = SM6115_MASTER_PIMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 41,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(mas_pimem_links),</div><div class='add'>+	.links = mas_pimem_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qdss_bam = {</div><div class='add'>+	.name = "qhm_qdss_bam",</div><div class='add'>+	.id = SM6115_MASTER_QDSS_BAM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.qos.qos_port = 23,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qpic = {</div><div class='add'>+	.name = "qhm_qpic",</div><div class='add'>+	.id = SM6115_MASTER_QPIC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup0 = {</div><div class='add'>+	.name = "qhm_qup0",</div><div class='add'>+	.id = SM6115_MASTER_QUP_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.qos.qos_port = 21,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = 166,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_ipa = {</div><div class='add'>+	.name = "qxm_ipa",</div><div class='add'>+	.id = SM6115_MASTER_IPA,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 24,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = 59,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_qdss_etr = {</div><div class='add'>+	.name = "xm_qdss_etr",</div><div class='add'>+	.id = SM6115_MASTER_QDSS_ETR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 33,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc1 = {</div><div class='add'>+	.name = "xm_sdc1",</div><div class='add'>+	.id = SM6115_MASTER_SDCC_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 38,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = 33,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc2 = {</div><div class='add'>+	.name = "xm_sdc2",</div><div class='add'>+	.id = SM6115_MASTER_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 44,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = 35,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_0 = {</div><div class='add'>+	.name = "xm_usb3_0",</div><div class='add'>+	.id = SM6115_MASTER_USB3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.qos.qos_port = 45,</div><div class='add'>+	.qos.qos_mode = NOC_QOS_MODE_FIXED,</div><div class='add'>+	.qos.areq_prio = 2,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(link_slv_anoc_snoc),</div><div class='add'>+	.links = link_slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ebi = {</div><div class='add'>+	.name = "ebi",</div><div class='add'>+	.id = SM6115_SLAVE_EBI_CH0,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_bimc_snoc_links[] = {</div><div class='add'>+	SM6115_MASTER_BIMC_SNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_bimc_snoc = {</div><div class='add'>+	.name = "slv_bimc_snoc",</div><div class='add'>+	.id = SM6115_SLAVE_BIMC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 2,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_bimc_snoc_links),</div><div class='add'>+	.links = slv_bimc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_slave = {</div><div class='add'>+	.name = "qup0_core_slave",</div><div class='add'>+	.id = SM6115_SLAVE_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy_usb = {</div><div class='add'>+	.name = "qhs_ahb2phy_usb",</div><div class='add'>+	.id = SM6115_SLAVE_AHB2PHY_USB,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_apss_throttle_cfg = {</div><div class='add'>+	.name = "qhs_apss_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_APSS_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_bimc_cfg = {</div><div class='add'>+	.name = "qhs_bimc_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_BIMC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_boot_rom = {</div><div class='add'>+	.name = "qhs_boot_rom",</div><div class='add'>+	.id = SM6115_SLAVE_BOOT_ROM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {</div><div class='add'>+	.name = "qhs_camera_nrt_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {</div><div class='add'>+	.name = "qhs_camera_rt_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_camera_ss_cfg = {</div><div class='add'>+	.name = "qhs_camera_ss_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_CAMERA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_clk_ctl = {</div><div class='add'>+	.name = "qhs_clk_ctl",</div><div class='add'>+	.id = SM6115_SLAVE_CLK_CTL,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_cx = {</div><div class='add'>+	.name = "qhs_cpr_cx",</div><div class='add'>+	.id = SM6115_SLAVE_RBCPR_CX_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_mx = {</div><div class='add'>+	.name = "qhs_cpr_mx",</div><div class='add'>+	.id = SM6115_SLAVE_RBCPR_MX_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_crypto0_cfg = {</div><div class='add'>+	.name = "qhs_crypto0_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_CRYPTO_0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_dcc_cfg = {</div><div class='add'>+	.name = "qhs_dcc_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_DCC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ddr_phy_cfg = {</div><div class='add'>+	.name = "qhs_ddr_phy_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_DDR_PHY_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ddr_ss_cfg = {</div><div class='add'>+	.name = "qhs_ddr_ss_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_DDR_SS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_disp_ss_cfg = {</div><div class='add'>+	.name = "qhs_disp_ss_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_DISPLAY_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_display_throttle_cfg = {</div><div class='add'>+	.name = "qhs_display_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_DISPLAY_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_gpu_cfg = {</div><div class='add'>+	.name = "qhs_gpu_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_GPU_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_gpu_throttle_cfg = {</div><div class='add'>+	.name = "qhs_gpu_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_GPU_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_hwkm = {</div><div class='add'>+	.name = "qhs_hwkm",</div><div class='add'>+	.id = SM6115_SLAVE_HWKM_CORE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_imem_cfg = {</div><div class='add'>+	.name = "qhs_imem_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_IMEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ipa_cfg = {</div><div class='add'>+	.name = "qhs_ipa_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_IPA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_lpass = {</div><div class='add'>+	.name = "qhs_lpass",</div><div class='add'>+	.id = SM6115_SLAVE_LPASS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mapss = {</div><div class='add'>+	.name = "qhs_mapss",</div><div class='add'>+	.id = SM6115_SLAVE_MAPSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mdsp_mpu_cfg = {</div><div class='add'>+	.name = "qhs_mdsp_mpu_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_MDSP_MPU_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mesg_ram = {</div><div class='add'>+	.name = "qhs_mesg_ram",</div><div class='add'>+	.id = SM6115_SLAVE_MESSAGE_RAM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mss = {</div><div class='add'>+	.name = "qhs_mss",</div><div class='add'>+	.id = SM6115_SLAVE_CNOC_MSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pdm = {</div><div class='add'>+	.name = "qhs_pdm",</div><div class='add'>+	.id = SM6115_SLAVE_PDM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pimem_cfg = {</div><div class='add'>+	.name = "qhs_pimem_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_PIMEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pka_wrapper = {</div><div class='add'>+	.name = "qhs_pka_wrapper",</div><div class='add'>+	.id = SM6115_SLAVE_PKA_CORE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pmic_arb = {</div><div class='add'>+	.name = "qhs_pmic_arb",</div><div class='add'>+	.id = SM6115_SLAVE_PMIC_ARB,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qdss_cfg = {</div><div class='add'>+	.name = "qhs_qdss_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_QDSS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qm_cfg = {</div><div class='add'>+	.name = "qhs_qm_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_QM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qm_mpu_cfg = {</div><div class='add'>+	.name = "qhs_qm_mpu_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_QM_MPU_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qpic = {</div><div class='add'>+	.name = "qhs_qpic",</div><div class='add'>+	.id = SM6115_SLAVE_QPIC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup0 = {</div><div class='add'>+	.name = "qhs_qup0",</div><div class='add'>+	.id = SM6115_SLAVE_QUP_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_rpm = {</div><div class='add'>+	.name = "qhs_rpm",</div><div class='add'>+	.id = SM6115_SLAVE_RPM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc1 = {</div><div class='add'>+	.name = "qhs_sdc1",</div><div class='add'>+	.id = SM6115_SLAVE_SDCC_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc2 = {</div><div class='add'>+	.name = "qhs_sdc2",</div><div class='add'>+	.id = SM6115_SLAVE_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_security = {</div><div class='add'>+	.name = "qhs_security",</div><div class='add'>+	.id = SM6115_SLAVE_SECURITY,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_snoc_cfg_links[] = {</div><div class='add'>+	SM6115_MASTER_SNOC_CFG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_snoc_cfg = {</div><div class='add'>+	.name = "qhs_snoc_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_SNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_snoc_cfg_links),</div><div class='add'>+	.links = slv_snoc_cfg_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tcsr = {</div><div class='add'>+	.name = "qhs_tcsr",</div><div class='add'>+	.id = SM6115_SLAVE_TCSR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tlmm = {</div><div class='add'>+	.name = "qhs_tlmm",</div><div class='add'>+	.id = SM6115_SLAVE_TLMM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3 = {</div><div class='add'>+	.name = "qhs_usb3",</div><div class='add'>+	.id = SM6115_SLAVE_USB3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_venus_cfg = {</div><div class='add'>+	.name = "qhs_venus_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_VENUS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_venus_throttle_cfg = {</div><div class='add'>+	.name = "qhs_venus_throttle_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_VENUS_THROTTLE_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {</div><div class='add'>+	.name = "qhs_vsense_ctrl_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_VSENSE_CTRL_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_cnoc = {</div><div class='add'>+	.name = "srvc_cnoc",</div><div class='add'>+	.id = SM6115_SLAVE_SERVICE_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_snoc_bimc_nrt_links[] = {</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC_NRT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_snoc_bimc_nrt = {</div><div class='add'>+	.name = "slv_snoc_bimc_nrt",</div><div class='add'>+	.id = SM6115_SLAVE_SNOC_BIMC_NRT,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links),</div><div class='add'>+	.links = slv_snoc_bimc_nrt_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_snoc_bimc_rt_links[] = {</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC_RT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_snoc_bimc_rt = {</div><div class='add'>+	.name = "slv_snoc_bimc_rt",</div><div class='add'>+	.id = SM6115_SLAVE_SNOC_BIMC_RT,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links),</div><div class='add'>+	.links = slv_snoc_bimc_rt_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_apss = {</div><div class='add'>+	.name = "qhs_apss",</div><div class='add'>+	.id = SM6115_SLAVE_APPSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_snoc_cnoc_links[] = {</div><div class='add'>+	SM6115_MASTER_SNOC_CNOC</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_snoc_cnoc = {</div><div class='add'>+	.name = "slv_snoc_cnoc",</div><div class='add'>+	.id = SM6115_SLAVE_SNOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 25,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_snoc_cnoc_links),</div><div class='add'>+	.links = slv_snoc_cnoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxs_imem = {</div><div class='add'>+	.name = "qxs_imem",</div><div class='add'>+	.id = SM6115_SLAVE_OCIMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 26,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxs_pimem = {</div><div class='add'>+	.name = "qxs_pimem",</div><div class='add'>+	.id = SM6115_SLAVE_PIMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_snoc_bimc_links[] = {</div><div class='add'>+	SM6115_MASTER_SNOC_BIMC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_snoc_bimc = {</div><div class='add'>+	.name = "slv_snoc_bimc",</div><div class='add'>+	.id = SM6115_SLAVE_SNOC_BIMC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 24,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_snoc_bimc_links),</div><div class='add'>+	.links = slv_snoc_bimc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_snoc = {</div><div class='add'>+	.name = "srvc_snoc",</div><div class='add'>+	.id = SM6115_SLAVE_SERVICE_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_qdss_stm = {</div><div class='add'>+	.name = "xs_qdss_stm",</div><div class='add'>+	.id = SM6115_SLAVE_QDSS_STM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = 30,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_sys_tcu_cfg = {</div><div class='add'>+	.name = "xs_sys_tcu_cfg",</div><div class='add'>+	.id = SM6115_SLAVE_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 slv_anoc_snoc_links[] = {</div><div class='add'>+	SM6115_MASTER_ANOC_SNOC,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node slv_anoc_snoc = {</div><div class='add'>+	.name = "slv_anoc_snoc",</div><div class='add'>+	.id = SM6115_SLAVE_ANOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.mas_rpm_id = -1,</div><div class='add'>+	.slv_rpm_id = -1,</div><div class='add'>+	.num_links = ARRAY_SIZE(slv_anoc_snoc_links),</div><div class='add'>+	.links = slv_anoc_snoc_links,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *bimc_nodes[] = {</div><div class='add'>+	[MASTER_AMPSS_M0] = &amp;apps_proc,</div><div class='add'>+	[MASTER_SNOC_BIMC_RT] = &amp;mas_snoc_bimc_rt,</div><div class='add'>+	[MASTER_SNOC_BIMC_NRT] = &amp;mas_snoc_bimc_nrt,</div><div class='add'>+	[SNOC_BIMC_MAS] = &amp;mas_snoc_bimc,</div><div class='add'>+	[MASTER_GRAPHICS_3D] = &amp;qnm_gpu,</div><div class='add'>+	[MASTER_TCU_0] = &amp;tcu_0,</div><div class='add'>+	[SLAVE_EBI_CH0] = &amp;ebi,</div><div class='add'>+	[BIMC_SNOC_SLV] = &amp;slv_bimc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config bimc_regmap_config = {</div><div class='add'>+	.reg_bits	= 32,</div><div class='add'>+	.reg_stride	= 4,</div><div class='add'>+	.val_bits	= 32,</div><div class='add'>+	.max_register	= 0x80000,</div><div class='add'>+	.fast_io	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_bimc = {</div><div class='add'>+	.type = QCOM_ICC_BIMC,</div><div class='add'>+	.nodes = bimc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(bimc_nodes),</div><div class='add'>+	.regmap_cfg = &amp;bimc_regmap_config,</div><div class='add'>+	.bus_clk_desc = &amp;bimc_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+	.qos_offset = 0x8000,</div><div class='add'>+	.ab_coeff = 153,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *config_noc_nodes[] = {</div><div class='add'>+	[SNOC_CNOC_MAS] = &amp;mas_snoc_cnoc,</div><div class='add'>+	[MASTER_QDSS_DAP] = &amp;xm_dap,</div><div class='add'>+	[SLAVE_AHB2PHY_USB] = &amp;qhs_ahb2phy_usb,</div><div class='add'>+	[SLAVE_APSS_THROTTLE_CFG] = &amp;qhs_apss_throttle_cfg,</div><div class='add'>+	[SLAVE_BIMC_CFG] = &amp;qhs_bimc_cfg,</div><div class='add'>+	[SLAVE_BOOT_ROM] = &amp;qhs_boot_rom,</div><div class='add'>+	[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &amp;qhs_camera_nrt_throttle_cfg,</div><div class='add'>+	[SLAVE_CAMERA_RT_THROTTLE_CFG] = &amp;qhs_camera_rt_throttle_cfg,</div><div class='add'>+	[SLAVE_CAMERA_CFG] = &amp;qhs_camera_ss_cfg,</div><div class='add'>+	[SLAVE_CLK_CTL] = &amp;qhs_clk_ctl,</div><div class='add'>+	[SLAVE_RBCPR_CX_CFG] = &amp;qhs_cpr_cx,</div><div class='add'>+	[SLAVE_RBCPR_MX_CFG] = &amp;qhs_cpr_mx,</div><div class='add'>+	[SLAVE_CRYPTO_0_CFG] = &amp;qhs_crypto0_cfg,</div><div class='add'>+	[SLAVE_DCC_CFG] = &amp;qhs_dcc_cfg,</div><div class='add'>+	[SLAVE_DDR_PHY_CFG] = &amp;qhs_ddr_phy_cfg,</div><div class='add'>+	[SLAVE_DDR_SS_CFG] = &amp;qhs_ddr_ss_cfg,</div><div class='add'>+	[SLAVE_DISPLAY_CFG] = &amp;qhs_disp_ss_cfg,</div><div class='add'>+	[SLAVE_DISPLAY_THROTTLE_CFG] = &amp;qhs_display_throttle_cfg,</div><div class='add'>+	[SLAVE_GPU_CFG] = &amp;qhs_gpu_cfg,</div><div class='add'>+	[SLAVE_GPU_THROTTLE_CFG] = &amp;qhs_gpu_throttle_cfg,</div><div class='add'>+	[SLAVE_HWKM_CORE] = &amp;qhs_hwkm,</div><div class='add'>+	[SLAVE_IMEM_CFG] = &amp;qhs_imem_cfg,</div><div class='add'>+	[SLAVE_IPA_CFG] = &amp;qhs_ipa_cfg,</div><div class='add'>+	[SLAVE_LPASS] = &amp;qhs_lpass,</div><div class='add'>+	[SLAVE_MAPSS] = &amp;qhs_mapss,</div><div class='add'>+	[SLAVE_MDSP_MPU_CFG] = &amp;qhs_mdsp_mpu_cfg,</div><div class='add'>+	[SLAVE_MESSAGE_RAM] = &amp;qhs_mesg_ram,</div><div class='add'>+	[SLAVE_CNOC_MSS] = &amp;qhs_mss,</div><div class='add'>+	[SLAVE_PDM] = &amp;qhs_pdm,</div><div class='add'>+	[SLAVE_PIMEM_CFG] = &amp;qhs_pimem_cfg,</div><div class='add'>+	[SLAVE_PKA_CORE] = &amp;qhs_pka_wrapper,</div><div class='add'>+	[SLAVE_PMIC_ARB] = &amp;qhs_pmic_arb,</div><div class='add'>+	[SLAVE_QDSS_CFG] = &amp;qhs_qdss_cfg,</div><div class='add'>+	[SLAVE_QM_CFG] = &amp;qhs_qm_cfg,</div><div class='add'>+	[SLAVE_QM_MPU_CFG] = &amp;qhs_qm_mpu_cfg,</div><div class='add'>+	[SLAVE_QPIC] = &amp;qhs_qpic,</div><div class='add'>+	[SLAVE_QUP_0] = &amp;qhs_qup0,</div><div class='add'>+	[SLAVE_RPM] = &amp;qhs_rpm,</div><div class='add'>+	[SLAVE_SDCC_1] = &amp;qhs_sdc1,</div><div class='add'>+	[SLAVE_SDCC_2] = &amp;qhs_sdc2,</div><div class='add'>+	[SLAVE_SECURITY] = &amp;qhs_security,</div><div class='add'>+	[SLAVE_SNOC_CFG] = &amp;qhs_snoc_cfg,</div><div class='add'>+	[SLAVE_TCSR] = &amp;qhs_tcsr,</div><div class='add'>+	[SLAVE_TLMM] = &amp;qhs_tlmm,</div><div class='add'>+	[SLAVE_USB3] = &amp;qhs_usb3,</div><div class='add'>+	[SLAVE_VENUS_CFG] = &amp;qhs_venus_cfg,</div><div class='add'>+	[SLAVE_VENUS_THROTTLE_CFG] = &amp;qhs_venus_throttle_cfg,</div><div class='add'>+	[SLAVE_VSENSE_CTRL_CFG] = &amp;qhs_vsense_ctrl_cfg,</div><div class='add'>+	[SLAVE_SERVICE_CNOC] = &amp;srvc_cnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config cnoc_regmap_config = {</div><div class='add'>+	.reg_bits	= 32,</div><div class='add'>+	.reg_stride	= 4,</div><div class='add'>+	.val_bits	= 32,</div><div class='add'>+	.max_register	= 0x6200,</div><div class='add'>+	.fast_io	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_config_noc = {</div><div class='add'>+	.type = QCOM_ICC_QNOC,</div><div class='add'>+	.nodes = config_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(config_noc_nodes),</div><div class='add'>+	.regmap_cfg = &amp;cnoc_regmap_config,</div><div class='add'>+	.intf_clocks = cnoc_intf_clocks,</div><div class='add'>+	.num_intf_clocks = ARRAY_SIZE(cnoc_intf_clocks),</div><div class='add'>+	.bus_clk_desc = &amp;bus_1_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *sys_noc_nodes[] = {</div><div class='add'>+	[MASTER_CRYPTO_CORE0] = &amp;crypto_c0,</div><div class='add'>+	[MASTER_SNOC_CFG] = &amp;qhm_snoc_cfg,</div><div class='add'>+	[MASTER_TIC] = &amp;qhm_tic,</div><div class='add'>+	[MASTER_ANOC_SNOC] = &amp;mas_anoc_snoc,</div><div class='add'>+	[BIMC_SNOC_MAS] = &amp;mas_bimc_snoc,</div><div class='add'>+	[MASTER_PIMEM] = &amp;qxm_pimem,</div><div class='add'>+	[MASTER_QDSS_BAM] = &amp;qhm_qdss_bam,</div><div class='add'>+	[MASTER_QPIC] = &amp;qhm_qpic,</div><div class='add'>+	[MASTER_QUP_0] = &amp;qhm_qup0,</div><div class='add'>+	[MASTER_IPA] = &amp;qxm_ipa,</div><div class='add'>+	[MASTER_QDSS_ETR] = &amp;xm_qdss_etr,</div><div class='add'>+	[MASTER_SDCC_1] = &amp;xm_sdc1,</div><div class='add'>+	[MASTER_SDCC_2] = &amp;xm_sdc2,</div><div class='add'>+	[MASTER_USB3] = &amp;xm_usb3_0,</div><div class='add'>+	[SLAVE_APPSS] = &amp;qhs_apss,</div><div class='add'>+	[SNOC_CNOC_SLV] = &amp;slv_snoc_cnoc,</div><div class='add'>+	[SLAVE_OCIMEM] = &amp;qxs_imem,</div><div class='add'>+	[SLAVE_PIMEM] = &amp;qxs_pimem,</div><div class='add'>+	[SNOC_BIMC_SLV] = &amp;slv_snoc_bimc,</div><div class='add'>+	[SLAVE_SERVICE_SNOC] = &amp;srvc_snoc,</div><div class='add'>+	[SLAVE_QDSS_STM] = &amp;xs_qdss_stm,</div><div class='add'>+	[SLAVE_TCU] = &amp;xs_sys_tcu_cfg,</div><div class='add'>+	[SLAVE_ANOC_SNOC] = &amp;slv_anoc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config sys_noc_regmap_config = {</div><div class='add'>+	.reg_bits	= 32,</div><div class='add'>+	.reg_stride	= 4,</div><div class='add'>+	.val_bits	= 32,</div><div class='add'>+	.max_register	= 0x5f080,</div><div class='add'>+	.fast_io	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_sys_noc = {</div><div class='add'>+	.type = QCOM_ICC_QNOC,</div><div class='add'>+	.nodes = sys_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(sys_noc_nodes),</div><div class='add'>+	.regmap_cfg = &amp;sys_noc_regmap_config,</div><div class='add'>+	.intf_clocks = snoc_intf_clocks,</div><div class='add'>+	.num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks),</div><div class='add'>+	.bus_clk_desc = &amp;bus_2_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *clk_virt_nodes[] = {</div><div class='add'>+	[MASTER_QUP_CORE_0] = &amp;qup0_core_master,</div><div class='add'>+	[SLAVE_QUP_CORE_0] = &amp;qup0_core_slave,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_clk_virt = {</div><div class='add'>+	.type = QCOM_ICC_QNOC,</div><div class='add'>+	.nodes = clk_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(clk_virt_nodes),</div><div class='add'>+	.regmap_cfg = &amp;sys_noc_regmap_config,</div><div class='add'>+	.bus_clk_desc = &amp;qup_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *mmnrt_virt_nodes[] = {</div><div class='add'>+	[MASTER_CAMNOC_SF] = &amp;qnm_camera_nrt,</div><div class='add'>+	[MASTER_VIDEO_P0] = &amp;qxm_venus0,</div><div class='add'>+	[MASTER_VIDEO_PROC] = &amp;qxm_venus_cpu,</div><div class='add'>+	[SLAVE_SNOC_BIMC_NRT] = &amp;slv_snoc_bimc_nrt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_mmnrt_virt = {</div><div class='add'>+	.type = QCOM_ICC_QNOC,</div><div class='add'>+	.nodes = mmnrt_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mmnrt_virt_nodes),</div><div class='add'>+	.regmap_cfg = &amp;sys_noc_regmap_config,</div><div class='add'>+	.bus_clk_desc = &amp;mmaxi_0_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+	.ab_coeff = 142,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node *mmrt_virt_nodes[] = {</div><div class='add'>+	[MASTER_CAMNOC_HF] = &amp;qnm_camera_rt,</div><div class='add'>+	[MASTER_MDP_PORT0] = &amp;qxm_mdp0,</div><div class='add'>+	[SLAVE_SNOC_BIMC_RT] = &amp;slv_snoc_bimc_rt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm6115_mmrt_virt = {</div><div class='add'>+	.type = QCOM_ICC_QNOC,</div><div class='add'>+	.nodes = mmrt_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mmrt_virt_nodes),</div><div class='add'>+	.regmap_cfg = &amp;sys_noc_regmap_config,</div><div class='add'>+	.bus_clk_desc = &amp;mmaxi_1_clk,</div><div class='add'>+	.keep_alive = true,</div><div class='add'>+	.ab_coeff = 139,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id qnoc_of_match[] = {</div><div class='add'>+	{ .compatible = "qcom,sm6115-bimc", .data = &amp;sm6115_bimc },</div><div class='add'>+	{ .compatible = "qcom,sm6115-clk-virt", .data = &amp;sm6115_clk_virt },</div><div class='add'>+	{ .compatible = "qcom,sm6115-cnoc", .data = &amp;sm6115_config_noc },</div><div class='add'>+	{ .compatible = "qcom,sm6115-mmrt-virt", .data = &amp;sm6115_mmrt_virt },</div><div class='add'>+	{ .compatible = "qcom,sm6115-mmnrt-virt", .data = &amp;sm6115_mmnrt_virt },</div><div class='add'>+	{ .compatible = "qcom,sm6115-snoc", .data = &amp;sm6115_sys_noc },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, qnoc_of_match);</div><div class='add'>+</div><div class='add'>+static struct platform_driver qnoc_driver = {</div><div class='add'>+	.probe = qnoc_probe,</div><div class='add'>+	.remove_new = qnoc_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "qnoc-sm6115",</div><div class='add'>+		.of_match_table = qnoc_of_match,</div><div class='add'>+		.sync_state = icc_sync_state,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init qnoc_driver_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+core_initcall(qnoc_driver_init);</div><div class='add'>+</div><div class='add'>+static void __exit qnoc_driver_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(qnoc_driver_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("SM6115 NoC driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c<br/>index 83aeb3eedc19..02d40eea0d69 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sm8250.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/sm8250.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sm8250.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8250.c</a></div><div class='hunk'>@@ -1995,6 +1995,7 @@ static struct platform_driver qnoc_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qnoc-sm8250",</div><div class='ctx'> 		.of_match_table = qnoc_of_match,</div><div class='add'>+		.sync_state = icc_sync_state,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(qnoc_driver);</div><div class='head'>diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c<br/>new file mode 100644<br/>index 000000000000..b83de54577b6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sm8650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8650.c</a></div><div class='hunk'>@@ -0,0 +1,1674 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/interconnect.h&gt;</div><div class='add'>+#include &lt;linux/interconnect-provider.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,sm8650-rpmh.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm-voter.h"</div><div class='add'>+#include "icc-common.h"</div><div class='add'>+#include "icc-rpmh.h"</div><div class='add'>+#include "sm8650.h"</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qspi = {</div><div class='add'>+	.name = "qhm_qspi",</div><div class='add'>+	.id = SM8650_MASTER_QSPI_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup1 = {</div><div class='add'>+	.name = "qhm_qup1",</div><div class='add'>+	.id = SM8650_MASTER_QUP_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_qup02 = {</div><div class='add'>+	.name = "qxm_qup02",</div><div class='add'>+	.id = SM8650_MASTER_QUP_3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc4 = {</div><div class='add'>+	.name = "xm_sdc4",</div><div class='add'>+	.id = SM8650_MASTER_SDCC_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_ufs_mem = {</div><div class='add'>+	.name = "xm_ufs_mem",</div><div class='add'>+	.id = SM8650_MASTER_UFS_MEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_0 = {</div><div class='add'>+	.name = "xm_usb3_0",</div><div class='add'>+	.id = SM8650_MASTER_USB3_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qdss_bam = {</div><div class='add'>+	.name = "qhm_qdss_bam",</div><div class='add'>+	.id = SM8650_MASTER_QDSS_BAM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup2 = {</div><div class='add'>+	.name = "qhm_qup2",</div><div class='add'>+	.id = SM8650_MASTER_QUP_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_crypto = {</div><div class='add'>+	.name = "qxm_crypto",</div><div class='add'>+	.id = SM8650_MASTER_CRYPTO,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_ipa = {</div><div class='add'>+	.name = "qxm_ipa",</div><div class='add'>+	.id = SM8650_MASTER_IPA,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_sp = {</div><div class='add'>+	.name = "qxm_sp",</div><div class='add'>+	.id = SM8650_MASTER_SP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_qdss_etr_0 = {</div><div class='add'>+	.name = "xm_qdss_etr_0",</div><div class='add'>+	.id = SM8650_MASTER_QDSS_ETR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_qdss_etr_1 = {</div><div class='add'>+	.name = "xm_qdss_etr_1",</div><div class='add'>+	.id = SM8650_MASTER_QDSS_ETR_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc2 = {</div><div class='add'>+	.name = "xm_sdc2",</div><div class='add'>+	.id = SM8650_MASTER_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_master = {</div><div class='add'>+	.name = "qup0_core_master",</div><div class='add'>+	.id = SM8650_MASTER_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_QUP_CORE_0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup1_core_master = {</div><div class='add'>+	.name = "qup1_core_master",</div><div class='add'>+	.id = SM8650_MASTER_QUP_CORE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_QUP_CORE_1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup2_core_master = {</div><div class='add'>+	.name = "qup2_core_master",</div><div class='add'>+	.id = SM8650_MASTER_QUP_CORE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_QUP_CORE_2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qsm_cfg = {</div><div class='add'>+	.name = "qsm_cfg",</div><div class='add'>+	.id = SM8650_MASTER_CNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 46,</div><div class='add'>+	.links = { SM8650_SLAVE_AHB2PHY_SOUTH, SM8650_SLAVE_AHB2PHY_NORTH,</div><div class='add'>+		   SM8650_SLAVE_CAMERA_CFG, SM8650_SLAVE_CLK_CTL,</div><div class='add'>+		   SM8650_SLAVE_RBCPR_CX_CFG, SM8650_SLAVE_CPR_HMX,</div><div class='add'>+		   SM8650_SLAVE_RBCPR_MMCX_CFG, SM8650_SLAVE_RBCPR_MXA_CFG,</div><div class='add'>+		   SM8650_SLAVE_RBCPR_MXC_CFG, SM8650_SLAVE_CPR_NSPCX,</div><div class='add'>+		   SM8650_SLAVE_CRYPTO_0_CFG, SM8650_SLAVE_CX_RDPM,</div><div class='add'>+		   SM8650_SLAVE_DISPLAY_CFG, SM8650_SLAVE_GFX3D_CFG,</div><div class='add'>+		   SM8650_SLAVE_I2C, SM8650_SLAVE_I3C_IBI0_CFG,</div><div class='add'>+		   SM8650_SLAVE_I3C_IBI1_CFG, SM8650_SLAVE_IMEM_CFG,</div><div class='add'>+		   SM8650_SLAVE_CNOC_MSS, SM8650_SLAVE_MX_2_RDPM,</div><div class='add'>+		   SM8650_SLAVE_MX_RDPM, SM8650_SLAVE_PCIE_0_CFG,</div><div class='add'>+		   SM8650_SLAVE_PCIE_1_CFG, SM8650_SLAVE_PCIE_RSCC,</div><div class='add'>+		   SM8650_SLAVE_PDM, SM8650_SLAVE_PRNG,</div><div class='add'>+		   SM8650_SLAVE_QDSS_CFG, SM8650_SLAVE_QSPI_0,</div><div class='add'>+		   SM8650_SLAVE_QUP_3, SM8650_SLAVE_QUP_1,</div><div class='add'>+		   SM8650_SLAVE_QUP_2, SM8650_SLAVE_SDCC_2,</div><div class='add'>+		   SM8650_SLAVE_SDCC_4, SM8650_SLAVE_SPSS_CFG,</div><div class='add'>+		   SM8650_SLAVE_TCSR, SM8650_SLAVE_TLMM,</div><div class='add'>+		   SM8650_SLAVE_UFS_MEM_CFG, SM8650_SLAVE_USB3_0,</div><div class='add'>+		   SM8650_SLAVE_VENUS_CFG, SM8650_SLAVE_VSENSE_CTRL_CFG,</div><div class='add'>+		   SM8650_SLAVE_CNOC_MNOC_CFG, SM8650_SLAVE_NSP_QTB_CFG,</div><div class='add'>+		   SM8650_SLAVE_PCIE_ANOC_CFG, SM8650_SLAVE_SERVICE_CNOC_CFG,</div><div class='add'>+		   SM8650_SLAVE_QDSS_STM, SM8650_SLAVE_TCU },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gemnoc_cnoc = {</div><div class='add'>+	.name = "qnm_gemnoc_cnoc",</div><div class='add'>+	.id = SM8650_MASTER_GEM_NOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 9,</div><div class='add'>+	.links = { SM8650_SLAVE_AOSS, SM8650_SLAVE_IPA_CFG,</div><div class='add'>+		   SM8650_SLAVE_IPC_ROUTER_CFG, SM8650_SLAVE_TME_CFG,</div><div class='add'>+		   SM8650_SLAVE_APPSS, SM8650_SLAVE_CNOC_CFG,</div><div class='add'>+		   SM8650_SLAVE_DDRSS_CFG, SM8650_SLAVE_IMEM,</div><div class='add'>+		   SM8650_SLAVE_SERVICE_CNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gemnoc_pcie = {</div><div class='add'>+	.name = "qnm_gemnoc_pcie",</div><div class='add'>+	.id = SM8650_MASTER_GEM_NOC_PCIE_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_gpu_tcu = {</div><div class='add'>+	.name = "alm_gpu_tcu",</div><div class='add'>+	.id = SM8650_MASTER_GPU_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_sys_tcu = {</div><div class='add'>+	.name = "alm_sys_tcu",</div><div class='add'>+	.id = SM8650_MASTER_SYS_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_ubwc_p_tcu = {</div><div class='add'>+	.name = "alm_ubwc_p_tcu",</div><div class='add'>+	.id = SM8650_MASTER_UBWC_P_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node chm_apps = {</div><div class='add'>+	.name = "chm_apps",</div><div class='add'>+	.id = SM8650_MASTER_APPSS_PROC,</div><div class='add'>+	.channels = 3,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,</div><div class='add'>+		   SM8650_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gpu = {</div><div class='add'>+	.name = "qnm_gpu",</div><div class='add'>+	.id = SM8650_MASTER_GFX3D,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpass_gemnoc = {</div><div class='add'>+	.name = "qnm_lpass_gemnoc",</div><div class='add'>+	.id = SM8650_MASTER_LPASS_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,</div><div class='add'>+		   SM8650_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mdsp = {</div><div class='add'>+	.name = "qnm_mdsp",</div><div class='add'>+	.id = SM8650_MASTER_MSS_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,</div><div class='add'>+		   SM8650_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mnoc_hf = {</div><div class='add'>+	.name = "qnm_mnoc_hf",</div><div class='add'>+	.id = SM8650_MASTER_MNOC_HF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mnoc_sf = {</div><div class='add'>+	.name = "qnm_mnoc_sf",</div><div class='add'>+	.id = SM8650_MASTER_MNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_nsp_gemnoc = {</div><div class='add'>+	.name = "qnm_nsp_gemnoc",</div><div class='add'>+	.id = SM8650_MASTER_COMPUTE_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,</div><div class='add'>+		   SM8650_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie = {</div><div class='add'>+	.name = "qnm_pcie",</div><div class='add'>+	.id = SM8650_MASTER_ANOC_PCIE_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_snoc_sf = {</div><div class='add'>+	.name = "qnm_snoc_sf",</div><div class='add'>+	.id = SM8650_MASTER_SNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,</div><div class='add'>+		   SM8650_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_ubwc_p = {</div><div class='add'>+	.name = "qnm_ubwc_p",</div><div class='add'>+	.id = SM8650_MASTER_UBWC_P,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_gic = {</div><div class='add'>+	.name = "xm_gic",</div><div class='add'>+	.id = SM8650_MASTER_GIC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpiaon_noc = {</div><div class='add'>+	.name = "qnm_lpiaon_noc",</div><div class='add'>+	.id = SM8650_MASTER_LPIAON_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_LPASS_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpass_lpinoc = {</div><div class='add'>+	.name = "qnm_lpass_lpinoc",</div><div class='add'>+	.id = SM8650_MASTER_LPASS_LPINOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_lpinoc_dsp_axim = {</div><div class='add'>+	.name = "qxm_lpinoc_dsp_axim",</div><div class='add'>+	.id = SM8650_MASTER_LPASS_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_LPICX_NOC_LPIAON_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node llcc_mc = {</div><div class='add'>+	.name = "llcc_mc",</div><div class='add'>+	.id = SM8650_MASTER_LLCC,</div><div class='add'>+	.channels = 4,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_EBI1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_hf = {</div><div class='add'>+	.name = "qnm_camnoc_hf",</div><div class='add'>+	.id = SM8650_MASTER_CAMNOC_HF,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_icp = {</div><div class='add'>+	.name = "qnm_camnoc_icp",</div><div class='add'>+	.id = SM8650_MASTER_CAMNOC_ICP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_sf = {</div><div class='add'>+	.name = "qnm_camnoc_sf",</div><div class='add'>+	.id = SM8650_MASTER_CAMNOC_SF,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mdp = {</div><div class='add'>+	.name = "qnm_mdp",</div><div class='add'>+	.id = SM8650_MASTER_MDP,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_vapss_hcp = {</div><div class='add'>+	.name = "qnm_vapss_hcp",</div><div class='add'>+	.id = SM8650_MASTER_CDSP_HCP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video = {</div><div class='add'>+	.name = "qnm_video",</div><div class='add'>+	.id = SM8650_MASTER_VIDEO,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video_cv_cpu = {</div><div class='add'>+	.name = "qnm_video_cv_cpu",</div><div class='add'>+	.id = SM8650_MASTER_VIDEO_CV_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video_cvp = {</div><div class='add'>+	.name = "qnm_video_cvp",</div><div class='add'>+	.id = SM8650_MASTER_VIDEO_PROC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video_v_cpu = {</div><div class='add'>+	.name = "qnm_video_v_cpu",</div><div class='add'>+	.id = SM8650_MASTER_VIDEO_V_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qsm_mnoc_cfg = {</div><div class='add'>+	.name = "qsm_mnoc_cfg",</div><div class='add'>+	.id = SM8650_MASTER_CNOC_MNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_SERVICE_MNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_nsp = {</div><div class='add'>+	.name = "qnm_nsp",</div><div class='add'>+	.id = SM8650_MASTER_CDSP_PROC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_CDSP_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qsm_pcie_anoc_cfg = {</div><div class='add'>+	.name = "qsm_pcie_anoc_cfg",</div><div class='add'>+	.id = SM8650_MASTER_PCIE_ANOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_SERVICE_PCIE_ANOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie3_0 = {</div><div class='add'>+	.name = "xm_pcie3_0",</div><div class='add'>+	.id = SM8650_MASTER_PCIE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie3_1 = {</div><div class='add'>+	.name = "xm_pcie3_1",</div><div class='add'>+	.id = SM8650_MASTER_PCIE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre1_noc = {</div><div class='add'>+	.name = "qnm_aggre1_noc",</div><div class='add'>+	.id = SM8650_MASTER_A1NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre2_noc = {</div><div class='add'>+	.name = "qnm_aggre2_noc",</div><div class='add'>+	.id = SM8650_MASTER_A2NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_a1noc_snoc = {</div><div class='add'>+	.name = "qns_a1noc_snoc",</div><div class='add'>+	.id = SM8650_SLAVE_A1NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_a2noc_snoc = {</div><div class='add'>+	.name = "qns_a2noc_snoc",</div><div class='add'>+	.id = SM8650_SLAVE_A2NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_slave = {</div><div class='add'>+	.name = "qup0_core_slave",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup1_core_slave = {</div><div class='add'>+	.name = "qup1_core_slave",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_CORE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup2_core_slave = {</div><div class='add'>+	.name = "qup2_core_slave",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_CORE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy0 = {</div><div class='add'>+	.name = "qhs_ahb2phy0",</div><div class='add'>+	.id = SM8650_SLAVE_AHB2PHY_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy1 = {</div><div class='add'>+	.name = "qhs_ahb2phy1",</div><div class='add'>+	.id = SM8650_SLAVE_AHB2PHY_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_camera_cfg = {</div><div class='add'>+	.name = "qhs_camera_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_CAMERA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_clk_ctl = {</div><div class='add'>+	.name = "qhs_clk_ctl",</div><div class='add'>+	.id = SM8650_SLAVE_CLK_CTL,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_cx = {</div><div class='add'>+	.name = "qhs_cpr_cx",</div><div class='add'>+	.id = SM8650_SLAVE_RBCPR_CX_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_hmx = {</div><div class='add'>+	.name = "qhs_cpr_hmx",</div><div class='add'>+	.id = SM8650_SLAVE_CPR_HMX,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_mmcx = {</div><div class='add'>+	.name = "qhs_cpr_mmcx",</div><div class='add'>+	.id = SM8650_SLAVE_RBCPR_MMCX_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_mxa = {</div><div class='add'>+	.name = "qhs_cpr_mxa",</div><div class='add'>+	.id = SM8650_SLAVE_RBCPR_MXA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_mxc = {</div><div class='add'>+	.name = "qhs_cpr_mxc",</div><div class='add'>+	.id = SM8650_SLAVE_RBCPR_MXC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cpr_nspcx = {</div><div class='add'>+	.name = "qhs_cpr_nspcx",</div><div class='add'>+	.id = SM8650_SLAVE_CPR_NSPCX,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_crypto0_cfg = {</div><div class='add'>+	.name = "qhs_crypto0_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_CRYPTO_0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_cx_rdpm = {</div><div class='add'>+	.name = "qhs_cx_rdpm",</div><div class='add'>+	.id = SM8650_SLAVE_CX_RDPM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_display_cfg = {</div><div class='add'>+	.name = "qhs_display_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_DISPLAY_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_gpuss_cfg = {</div><div class='add'>+	.name = "qhs_gpuss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_GFX3D_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_i2c = {</div><div class='add'>+	.name = "qhs_i2c",</div><div class='add'>+	.id = SM8650_SLAVE_I2C,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_i3c_ibi0_cfg = {</div><div class='add'>+	.name = "qhs_i3c_ibi0_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_I3C_IBI0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_i3c_ibi1_cfg = {</div><div class='add'>+	.name = "qhs_i3c_ibi1_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_I3C_IBI1_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_imem_cfg = {</div><div class='add'>+	.name = "qhs_imem_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_IMEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mss_cfg = {</div><div class='add'>+	.name = "qhs_mss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_CNOC_MSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mx_2_rdpm = {</div><div class='add'>+	.name = "qhs_mx_2_rdpm",</div><div class='add'>+	.id = SM8650_SLAVE_MX_2_RDPM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_mx_rdpm = {</div><div class='add'>+	.name = "qhs_mx_rdpm",</div><div class='add'>+	.id = SM8650_SLAVE_MX_RDPM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie0_cfg = {</div><div class='add'>+	.name = "qhs_pcie0_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie1_cfg = {</div><div class='add'>+	.name = "qhs_pcie1_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_1_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie_rscc = {</div><div class='add'>+	.name = "qhs_pcie_rscc",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_RSCC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pdm = {</div><div class='add'>+	.name = "qhs_pdm",</div><div class='add'>+	.id = SM8650_SLAVE_PDM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_prng = {</div><div class='add'>+	.name = "qhs_prng",</div><div class='add'>+	.id = SM8650_SLAVE_PRNG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qdss_cfg = {</div><div class='add'>+	.name = "qhs_qdss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_QDSS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qspi = {</div><div class='add'>+	.name = "qhs_qspi",</div><div class='add'>+	.id = SM8650_SLAVE_QSPI_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup02 = {</div><div class='add'>+	.name = "qhs_qup02",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup1 = {</div><div class='add'>+	.name = "qhs_qup1",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup2 = {</div><div class='add'>+	.name = "qhs_qup2",</div><div class='add'>+	.id = SM8650_SLAVE_QUP_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc2 = {</div><div class='add'>+	.name = "qhs_sdc2",</div><div class='add'>+	.id = SM8650_SLAVE_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc4 = {</div><div class='add'>+	.name = "qhs_sdc4",</div><div class='add'>+	.id = SM8650_SLAVE_SDCC_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_spss_cfg = {</div><div class='add'>+	.name = "qhs_spss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_SPSS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tcsr = {</div><div class='add'>+	.name = "qhs_tcsr",</div><div class='add'>+	.id = SM8650_SLAVE_TCSR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tlmm = {</div><div class='add'>+	.name = "qhs_tlmm",</div><div class='add'>+	.id = SM8650_SLAVE_TLMM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ufs_mem_cfg = {</div><div class='add'>+	.name = "qhs_ufs_mem_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_UFS_MEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3_0 = {</div><div class='add'>+	.name = "qhs_usb3_0",</div><div class='add'>+	.id = SM8650_SLAVE_USB3_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_venus_cfg = {</div><div class='add'>+	.name = "qhs_venus_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_VENUS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {</div><div class='add'>+	.name = "qhs_vsense_ctrl_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_VSENSE_CTRL_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_mnoc_cfg = {</div><div class='add'>+	.name = "qss_mnoc_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_CNOC_MNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_CNOC_MNOC_CFG },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_nsp_qtb_cfg = {</div><div class='add'>+	.name = "qss_nsp_qtb_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_NSP_QTB_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_pcie_anoc_cfg = {</div><div class='add'>+	.name = "qss_pcie_anoc_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_ANOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_PCIE_ANOC_CFG },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_cnoc_cfg = {</div><div class='add'>+	.name = "srvc_cnoc_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_SERVICE_CNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_qdss_stm = {</div><div class='add'>+	.name = "xs_qdss_stm",</div><div class='add'>+	.id = SM8650_SLAVE_QDSS_STM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_sys_tcu_cfg = {</div><div class='add'>+	.name = "xs_sys_tcu_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_aoss = {</div><div class='add'>+	.name = "qhs_aoss",</div><div class='add'>+	.id = SM8650_SLAVE_AOSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ipa = {</div><div class='add'>+	.name = "qhs_ipa",</div><div class='add'>+	.id = SM8650_SLAVE_IPA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ipc_router = {</div><div class='add'>+	.name = "qhs_ipc_router",</div><div class='add'>+	.id = SM8650_SLAVE_IPC_ROUTER_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tme_cfg = {</div><div class='add'>+	.name = "qhs_tme_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_TME_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_apss = {</div><div class='add'>+	.name = "qss_apss",</div><div class='add'>+	.id = SM8650_SLAVE_APPSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_cfg = {</div><div class='add'>+	.name = "qss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_CNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_CNOC_CFG },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_ddrss_cfg = {</div><div class='add'>+	.name = "qss_ddrss_cfg",</div><div class='add'>+	.id = SM8650_SLAVE_DDRSS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxs_imem = {</div><div class='add'>+	.name = "qxs_imem",</div><div class='add'>+	.id = SM8650_SLAVE_IMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_cnoc_main = {</div><div class='add'>+	.name = "srvc_cnoc_main",</div><div class='add'>+	.id = SM8650_SLAVE_SERVICE_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_0 = {</div><div class='add'>+	.name = "xs_pcie_0",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_1 = {</div><div class='add'>+	.name = "xs_pcie_1",</div><div class='add'>+	.id = SM8650_SLAVE_PCIE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_gem_noc_cnoc = {</div><div class='add'>+	.name = "qns_gem_noc_cnoc",</div><div class='add'>+	.id = SM8650_SLAVE_GEM_NOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_GEM_NOC_CNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_llcc = {</div><div class='add'>+	.name = "qns_llcc",</div><div class='add'>+	.id = SM8650_SLAVE_LLCC,</div><div class='add'>+	.channels = 4,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie = {</div><div class='add'>+	.name = "qns_pcie",</div><div class='add'>+	.id = SM8650_SLAVE_MEM_NOC_PCIE_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_GEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {</div><div class='add'>+	.name = "qns_lpass_ag_noc_gemnoc",</div><div class='add'>+	.id = SM8650_SLAVE_LPASS_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_LPASS_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpass_aggnoc = {</div><div class='add'>+	.name = "qns_lpass_aggnoc",</div><div class='add'>+	.id = SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_LPIAON_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpi_aon_noc = {</div><div class='add'>+	.name = "qns_lpi_aon_noc",</div><div class='add'>+	.id = SM8650_SLAVE_LPICX_NOC_LPIAON_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_LPASS_LPINOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ebi = {</div><div class='add'>+	.name = "ebi",</div><div class='add'>+	.id = SM8650_SLAVE_EBI1,</div><div class='add'>+	.channels = 4,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_mem_noc_hf = {</div><div class='add'>+	.name = "qns_mem_noc_hf",</div><div class='add'>+	.id = SM8650_SLAVE_MNOC_HF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_mem_noc_sf = {</div><div class='add'>+	.name = "qns_mem_noc_sf",</div><div class='add'>+	.id = SM8650_SLAVE_MNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_mnoc = {</div><div class='add'>+	.name = "srvc_mnoc",</div><div class='add'>+	.id = SM8650_SLAVE_SERVICE_MNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_nsp_gemnoc = {</div><div class='add'>+	.name = "qns_nsp_gemnoc",</div><div class='add'>+	.id = SM8650_SLAVE_CDSP_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_COMPUTE_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_mem_noc = {</div><div class='add'>+	.name = "qns_pcie_mem_noc",</div><div class='add'>+	.id = SM8650_SLAVE_ANOC_PCIE_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_pcie_aggre_noc = {</div><div class='add'>+	.name = "srvc_pcie_aggre_noc",</div><div class='add'>+	.id = SM8650_SLAVE_SERVICE_PCIE_ANOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_gemnoc_sf = {</div><div class='add'>+	.name = "qns_gemnoc_sf",</div><div class='add'>+	.id = SM8650_SLAVE_SNOC_GEM_NOC_SF,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { SM8650_MASTER_SNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_acv = {</div><div class='add'>+	.name = "ACV",</div><div class='add'>+	.enable_mask = BIT(3),</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_ce0 = {</div><div class='add'>+	.name = "CE0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qxm_crypto },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_cn0 = {</div><div class='add'>+	.name = "CN0",</div><div class='add'>+	.enable_mask = BIT(0),</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 59,</div><div class='add'>+	.nodes = { &amp;qsm_cfg, &amp;qhs_ahb2phy0,</div><div class='add'>+		   &amp;qhs_ahb2phy1, &amp;qhs_camera_cfg,</div><div class='add'>+		   &amp;qhs_clk_ctl, &amp;qhs_cpr_cx,</div><div class='add'>+		   &amp;qhs_cpr_hmx, &amp;qhs_cpr_mmcx,</div><div class='add'>+		   &amp;qhs_cpr_mxa, &amp;qhs_cpr_mxc,</div><div class='add'>+		   &amp;qhs_cpr_nspcx, &amp;qhs_crypto0_cfg,</div><div class='add'>+		   &amp;qhs_cx_rdpm, &amp;qhs_display_cfg,</div><div class='add'>+		   &amp;qhs_gpuss_cfg, &amp;qhs_i2c,</div><div class='add'>+		   &amp;qhs_i3c_ibi0_cfg, &amp;qhs_i3c_ibi1_cfg,</div><div class='add'>+		   &amp;qhs_imem_cfg, &amp;qhs_mss_cfg,</div><div class='add'>+		   &amp;qhs_mx_2_rdpm, &amp;qhs_mx_rdpm,</div><div class='add'>+		   &amp;qhs_pcie0_cfg, &amp;qhs_pcie1_cfg,</div><div class='add'>+		   &amp;qhs_pcie_rscc, &amp;qhs_pdm,</div><div class='add'>+		   &amp;qhs_prng, &amp;qhs_qdss_cfg,</div><div class='add'>+		   &amp;qhs_qspi, &amp;qhs_qup02,</div><div class='add'>+		   &amp;qhs_qup1, &amp;qhs_qup2,</div><div class='add'>+		   &amp;qhs_sdc2, &amp;qhs_sdc4,</div><div class='add'>+		   &amp;qhs_spss_cfg, &amp;qhs_tcsr,</div><div class='add'>+		   &amp;qhs_tlmm, &amp;qhs_ufs_mem_cfg,</div><div class='add'>+		   &amp;qhs_usb3_0, &amp;qhs_venus_cfg,</div><div class='add'>+		   &amp;qhs_vsense_ctrl_cfg, &amp;qss_mnoc_cfg,</div><div class='add'>+		   &amp;qss_nsp_qtb_cfg, &amp;qss_pcie_anoc_cfg,</div><div class='add'>+		   &amp;srvc_cnoc_cfg, &amp;xs_qdss_stm,</div><div class='add'>+		   &amp;xs_sys_tcu_cfg, &amp;qnm_gemnoc_cnoc,</div><div class='add'>+		   &amp;qnm_gemnoc_pcie, &amp;qhs_aoss,</div><div class='add'>+		   &amp;qhs_ipa, &amp;qhs_ipc_router,</div><div class='add'>+		   &amp;qhs_tme_cfg, &amp;qss_apss,</div><div class='add'>+		   &amp;qss_cfg, &amp;qss_ddrss_cfg,</div><div class='add'>+		   &amp;qxs_imem, &amp;srvc_cnoc_main,</div><div class='add'>+		   &amp;xs_pcie_0, &amp;xs_pcie_1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_co0 = {</div><div class='add'>+	.name = "CO0",</div><div class='add'>+	.enable_mask = BIT(0),</div><div class='add'>+	.num_nodes = 2,</div><div class='add'>+	.nodes = { &amp;qnm_nsp, &amp;qns_nsp_gemnoc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_lp0 = {</div><div class='add'>+	.name = "LP0",</div><div class='add'>+	.num_nodes = 2,</div><div class='add'>+	.nodes = { &amp;qnm_lpass_lpinoc, &amp;qns_lpass_aggnoc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mc0 = {</div><div class='add'>+	.name = "MC0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm0 = {</div><div class='add'>+	.name = "MM0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_mem_noc_hf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm1 = {</div><div class='add'>+	.name = "MM1",</div><div class='add'>+	.enable_mask = BIT(0),</div><div class='add'>+	.num_nodes = 8,</div><div class='add'>+	.nodes = { &amp;qnm_camnoc_hf, &amp;qnm_camnoc_icp,</div><div class='add'>+		   &amp;qnm_camnoc_sf, &amp;qnm_vapss_hcp,</div><div class='add'>+		   &amp;qnm_video_cv_cpu, &amp;qnm_video_cvp,</div><div class='add'>+		   &amp;qnm_video_v_cpu, &amp;qns_mem_noc_sf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup0 = {</div><div class='add'>+	.name = "QUP0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup0_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup1 = {</div><div class='add'>+	.name = "QUP1",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup1_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup2 = {</div><div class='add'>+	.name = "QUP2",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup2_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh0 = {</div><div class='add'>+	.name = "SH0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_llcc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh1 = {</div><div class='add'>+	.name = "SH1",</div><div class='add'>+	.enable_mask = BIT(0),</div><div class='add'>+	.num_nodes = 15,</div><div class='add'>+	.nodes = { &amp;alm_gpu_tcu, &amp;alm_sys_tcu,</div><div class='add'>+		   &amp;alm_ubwc_p_tcu, &amp;chm_apps,</div><div class='add'>+		   &amp;qnm_gpu, &amp;qnm_mdsp,</div><div class='add'>+		   &amp;qnm_mnoc_hf, &amp;qnm_mnoc_sf,</div><div class='add'>+		   &amp;qnm_nsp_gemnoc, &amp;qnm_pcie,</div><div class='add'>+		   &amp;qnm_snoc_sf, &amp;qnm_ubwc_p,</div><div class='add'>+		   &amp;xm_gic, &amp;qns_gem_noc_cnoc,</div><div class='add'>+		   &amp;qns_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn0 = {</div><div class='add'>+	.name = "SN0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_gemnoc_sf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn2 = {</div><div class='add'>+	.name = "SN2",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_aggre1_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn3 = {</div><div class='add'>+	.name = "SN3",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_aggre2_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn4 = {</div><div class='add'>+	.name = "SN4",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_pcie_mem_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const aggre1_noc_nodes[] = {</div><div class='add'>+	[MASTER_QSPI_0] = &amp;qhm_qspi,</div><div class='add'>+	[MASTER_QUP_1] = &amp;qhm_qup1,</div><div class='add'>+	[MASTER_QUP_3] = &amp;qxm_qup02,</div><div class='add'>+	[MASTER_SDCC_4] = &amp;xm_sdc4,</div><div class='add'>+	[MASTER_UFS_MEM] = &amp;xm_ufs_mem,</div><div class='add'>+	[MASTER_USB3_0] = &amp;xm_usb3_0,</div><div class='add'>+	[SLAVE_A1NOC_SNOC] = &amp;qns_a1noc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_aggre1_noc = {</div><div class='add'>+	.nodes = aggre1_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_ce0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const aggre2_noc_nodes[] = {</div><div class='add'>+	[MASTER_QDSS_BAM] = &amp;qhm_qdss_bam,</div><div class='add'>+	[MASTER_QUP_2] = &amp;qhm_qup2,</div><div class='add'>+	[MASTER_CRYPTO] = &amp;qxm_crypto,</div><div class='add'>+	[MASTER_IPA] = &amp;qxm_ipa,</div><div class='add'>+	[MASTER_SP] = &amp;qxm_sp,</div><div class='add'>+	[MASTER_QDSS_ETR] = &amp;xm_qdss_etr_0,</div><div class='add'>+	[MASTER_QDSS_ETR_1] = &amp;xm_qdss_etr_1,</div><div class='add'>+	[MASTER_SDCC_2] = &amp;xm_sdc2,</div><div class='add'>+	[SLAVE_A2NOC_SNOC] = &amp;qns_a2noc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_aggre2_noc = {</div><div class='add'>+	.nodes = aggre2_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),</div><div class='add'>+	.bcms = aggre2_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const clk_virt_bcms[] = {</div><div class='add'>+	&amp;bcm_qup0,</div><div class='add'>+	&amp;bcm_qup1,</div><div class='add'>+	&amp;bcm_qup2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const clk_virt_nodes[] = {</div><div class='add'>+	[MASTER_QUP_CORE_0] = &amp;qup0_core_master,</div><div class='add'>+	[MASTER_QUP_CORE_1] = &amp;qup1_core_master,</div><div class='add'>+	[MASTER_QUP_CORE_2] = &amp;qup2_core_master,</div><div class='add'>+	[SLAVE_QUP_CORE_0] = &amp;qup0_core_slave,</div><div class='add'>+	[SLAVE_QUP_CORE_1] = &amp;qup1_core_slave,</div><div class='add'>+	[SLAVE_QUP_CORE_2] = &amp;qup2_core_slave,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_clk_virt = {</div><div class='add'>+	.nodes = clk_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(clk_virt_nodes),</div><div class='add'>+	.bcms = clk_virt_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(clk_virt_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const config_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_cn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const config_noc_nodes[] = {</div><div class='add'>+	[MASTER_CNOC_CFG] = &amp;qsm_cfg,</div><div class='add'>+	[SLAVE_AHB2PHY_SOUTH] = &amp;qhs_ahb2phy0,</div><div class='add'>+	[SLAVE_AHB2PHY_NORTH] = &amp;qhs_ahb2phy1,</div><div class='add'>+	[SLAVE_CAMERA_CFG] = &amp;qhs_camera_cfg,</div><div class='add'>+	[SLAVE_CLK_CTL] = &amp;qhs_clk_ctl,</div><div class='add'>+	[SLAVE_RBCPR_CX_CFG] = &amp;qhs_cpr_cx,</div><div class='add'>+	[SLAVE_CPR_HMX] = &amp;qhs_cpr_hmx,</div><div class='add'>+	[SLAVE_RBCPR_MMCX_CFG] = &amp;qhs_cpr_mmcx,</div><div class='add'>+	[SLAVE_RBCPR_MXA_CFG] = &amp;qhs_cpr_mxa,</div><div class='add'>+	[SLAVE_RBCPR_MXC_CFG] = &amp;qhs_cpr_mxc,</div><div class='add'>+	[SLAVE_CPR_NSPCX] = &amp;qhs_cpr_nspcx,</div><div class='add'>+	[SLAVE_CRYPTO_0_CFG] = &amp;qhs_crypto0_cfg,</div><div class='add'>+	[SLAVE_CX_RDPM] = &amp;qhs_cx_rdpm,</div><div class='add'>+	[SLAVE_DISPLAY_CFG] = &amp;qhs_display_cfg,</div><div class='add'>+	[SLAVE_GFX3D_CFG] = &amp;qhs_gpuss_cfg,</div><div class='add'>+	[SLAVE_I2C] = &amp;qhs_i2c,</div><div class='add'>+	[SLAVE_I3C_IBI0_CFG] = &amp;qhs_i3c_ibi0_cfg,</div><div class='add'>+	[SLAVE_I3C_IBI1_CFG] = &amp;qhs_i3c_ibi1_cfg,</div><div class='add'>+	[SLAVE_IMEM_CFG] = &amp;qhs_imem_cfg,</div><div class='add'>+	[SLAVE_CNOC_MSS] = &amp;qhs_mss_cfg,</div><div class='add'>+	[SLAVE_MX_2_RDPM] = &amp;qhs_mx_2_rdpm,</div><div class='add'>+	[SLAVE_MX_RDPM] = &amp;qhs_mx_rdpm,</div><div class='add'>+	[SLAVE_PCIE_0_CFG] = &amp;qhs_pcie0_cfg,</div><div class='add'>+	[SLAVE_PCIE_1_CFG] = &amp;qhs_pcie1_cfg,</div><div class='add'>+	[SLAVE_PCIE_RSCC] = &amp;qhs_pcie_rscc,</div><div class='add'>+	[SLAVE_PDM] = &amp;qhs_pdm,</div><div class='add'>+	[SLAVE_PRNG] = &amp;qhs_prng,</div><div class='add'>+	[SLAVE_QDSS_CFG] = &amp;qhs_qdss_cfg,</div><div class='add'>+	[SLAVE_QSPI_0] = &amp;qhs_qspi,</div><div class='add'>+	[SLAVE_QUP_3] = &amp;qhs_qup02,</div><div class='add'>+	[SLAVE_QUP_1] = &amp;qhs_qup1,</div><div class='add'>+	[SLAVE_QUP_2] = &amp;qhs_qup2,</div><div class='add'>+	[SLAVE_SDCC_2] = &amp;qhs_sdc2,</div><div class='add'>+	[SLAVE_SDCC_4] = &amp;qhs_sdc4,</div><div class='add'>+	[SLAVE_SPSS_CFG] = &amp;qhs_spss_cfg,</div><div class='add'>+	[SLAVE_TCSR] = &amp;qhs_tcsr,</div><div class='add'>+	[SLAVE_TLMM] = &amp;qhs_tlmm,</div><div class='add'>+	[SLAVE_UFS_MEM_CFG] = &amp;qhs_ufs_mem_cfg,</div><div class='add'>+	[SLAVE_USB3_0] = &amp;qhs_usb3_0,</div><div class='add'>+	[SLAVE_VENUS_CFG] = &amp;qhs_venus_cfg,</div><div class='add'>+	[SLAVE_VSENSE_CTRL_CFG] = &amp;qhs_vsense_ctrl_cfg,</div><div class='add'>+	[SLAVE_CNOC_MNOC_CFG] = &amp;qss_mnoc_cfg,</div><div class='add'>+	[SLAVE_NSP_QTB_CFG] = &amp;qss_nsp_qtb_cfg,</div><div class='add'>+	[SLAVE_PCIE_ANOC_CFG] = &amp;qss_pcie_anoc_cfg,</div><div class='add'>+	[SLAVE_SERVICE_CNOC_CFG] = &amp;srvc_cnoc_cfg,</div><div class='add'>+	[SLAVE_QDSS_STM] = &amp;xs_qdss_stm,</div><div class='add'>+	[SLAVE_TCU] = &amp;xs_sys_tcu_cfg,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_config_noc = {</div><div class='add'>+	.nodes = config_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(config_noc_nodes),</div><div class='add'>+	.bcms = config_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(config_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {</div><div class='add'>+	&amp;bcm_cn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const cnoc_main_nodes[] = {</div><div class='add'>+	[MASTER_GEM_NOC_CNOC] = &amp;qnm_gemnoc_cnoc,</div><div class='add'>+	[MASTER_GEM_NOC_PCIE_SNOC] = &amp;qnm_gemnoc_pcie,</div><div class='add'>+	[SLAVE_AOSS] = &amp;qhs_aoss,</div><div class='add'>+	[SLAVE_IPA_CFG] = &amp;qhs_ipa,</div><div class='add'>+	[SLAVE_IPC_ROUTER_CFG] = &amp;qhs_ipc_router,</div><div class='add'>+	[SLAVE_TME_CFG] = &amp;qhs_tme_cfg,</div><div class='add'>+	[SLAVE_APPSS] = &amp;qss_apss,</div><div class='add'>+	[SLAVE_CNOC_CFG] = &amp;qss_cfg,</div><div class='add'>+	[SLAVE_DDRSS_CFG] = &amp;qss_ddrss_cfg,</div><div class='add'>+	[SLAVE_IMEM] = &amp;qxs_imem,</div><div class='add'>+	[SLAVE_SERVICE_CNOC] = &amp;srvc_cnoc_main,</div><div class='add'>+	[SLAVE_PCIE_0] = &amp;xs_pcie_0,</div><div class='add'>+	[SLAVE_PCIE_1] = &amp;xs_pcie_1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_cnoc_main = {</div><div class='add'>+	.nodes = cnoc_main_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),</div><div class='add'>+	.bcms = cnoc_main_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(cnoc_main_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const gem_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_sh0,</div><div class='add'>+	&amp;bcm_sh1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const gem_noc_nodes[] = {</div><div class='add'>+	[MASTER_GPU_TCU] = &amp;alm_gpu_tcu,</div><div class='add'>+	[MASTER_SYS_TCU] = &amp;alm_sys_tcu,</div><div class='add'>+	[MASTER_UBWC_P_TCU] = &amp;alm_ubwc_p_tcu,</div><div class='add'>+	[MASTER_APPSS_PROC] = &amp;chm_apps,</div><div class='add'>+	[MASTER_GFX3D] = &amp;qnm_gpu,</div><div class='add'>+	[MASTER_LPASS_GEM_NOC] = &amp;qnm_lpass_gemnoc,</div><div class='add'>+	[MASTER_MSS_PROC] = &amp;qnm_mdsp,</div><div class='add'>+	[MASTER_MNOC_HF_MEM_NOC] = &amp;qnm_mnoc_hf,</div><div class='add'>+	[MASTER_MNOC_SF_MEM_NOC] = &amp;qnm_mnoc_sf,</div><div class='add'>+	[MASTER_COMPUTE_NOC] = &amp;qnm_nsp_gemnoc,</div><div class='add'>+	[MASTER_ANOC_PCIE_GEM_NOC] = &amp;qnm_pcie,</div><div class='add'>+	[MASTER_SNOC_SF_MEM_NOC] = &amp;qnm_snoc_sf,</div><div class='add'>+	[MASTER_UBWC_P] = &amp;qnm_ubwc_p,</div><div class='add'>+	[MASTER_GIC] = &amp;xm_gic,</div><div class='add'>+	[SLAVE_GEM_NOC_CNOC] = &amp;qns_gem_noc_cnoc,</div><div class='add'>+	[SLAVE_LLCC] = &amp;qns_llcc,</div><div class='add'>+	[SLAVE_MEM_NOC_PCIE_SNOC] = &amp;qns_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_gem_noc = {</div><div class='add'>+	.nodes = gem_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(gem_noc_nodes),</div><div class='add'>+	.bcms = gem_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(gem_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPIAON_NOC] = &amp;qnm_lpiaon_noc,</div><div class='add'>+	[SLAVE_LPASS_GEM_NOC] = &amp;qns_lpass_ag_noc_gemnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_lpass_ag_noc = {</div><div class='add'>+	.nodes = lpass_ag_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_lp0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPASS_LPINOC] = &amp;qnm_lpass_lpinoc,</div><div class='add'>+	[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &amp;qns_lpass_aggnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = {</div><div class='add'>+	.nodes = lpass_lpiaon_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),</div><div class='add'>+	.bcms = lpass_lpiaon_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPASS_PROC] = &amp;qxm_lpinoc_dsp_axim,</div><div class='add'>+	[SLAVE_LPICX_NOC_LPIAON_NOC] = &amp;qns_lpi_aon_noc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = {</div><div class='add'>+	.nodes = lpass_lpicx_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const mc_virt_bcms[] = {</div><div class='add'>+	&amp;bcm_acv,</div><div class='add'>+	&amp;bcm_mc0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const mc_virt_nodes[] = {</div><div class='add'>+	[MASTER_LLCC] = &amp;llcc_mc,</div><div class='add'>+	[SLAVE_EBI1] = &amp;ebi,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_mc_virt = {</div><div class='add'>+	.nodes = mc_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mc_virt_nodes),</div><div class='add'>+	.bcms = mc_virt_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(mc_virt_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_mm0,</div><div class='add'>+	&amp;bcm_mm1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const mmss_noc_nodes[] = {</div><div class='add'>+	[MASTER_CAMNOC_HF] = &amp;qnm_camnoc_hf,</div><div class='add'>+	[MASTER_CAMNOC_ICP] = &amp;qnm_camnoc_icp,</div><div class='add'>+	[MASTER_CAMNOC_SF] = &amp;qnm_camnoc_sf,</div><div class='add'>+	[MASTER_MDP] = &amp;qnm_mdp,</div><div class='add'>+	[MASTER_CDSP_HCP] = &amp;qnm_vapss_hcp,</div><div class='add'>+	[MASTER_VIDEO] = &amp;qnm_video,</div><div class='add'>+	[MASTER_VIDEO_CV_PROC] = &amp;qnm_video_cv_cpu,</div><div class='add'>+	[MASTER_VIDEO_PROC] = &amp;qnm_video_cvp,</div><div class='add'>+	[MASTER_VIDEO_V_PROC] = &amp;qnm_video_v_cpu,</div><div class='add'>+	[MASTER_CNOC_MNOC_CFG] = &amp;qsm_mnoc_cfg,</div><div class='add'>+	[SLAVE_MNOC_HF_MEM_NOC] = &amp;qns_mem_noc_hf,</div><div class='add'>+	[SLAVE_MNOC_SF_MEM_NOC] = &amp;qns_mem_noc_sf,</div><div class='add'>+	[SLAVE_SERVICE_MNOC] = &amp;srvc_mnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_mmss_noc = {</div><div class='add'>+	.nodes = mmss_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),</div><div class='add'>+	.bcms = mmss_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_co0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const nsp_noc_nodes[] = {</div><div class='add'>+	[MASTER_CDSP_PROC] = &amp;qnm_nsp,</div><div class='add'>+	[SLAVE_CDSP_MEM_NOC] = &amp;qns_nsp_gemnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_nsp_noc = {</div><div class='add'>+	.nodes = nsp_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),</div><div class='add'>+	.bcms = nsp_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {</div><div class='add'>+	&amp;bcm_sn4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const pcie_anoc_nodes[] = {</div><div class='add'>+	[MASTER_PCIE_ANOC_CFG] = &amp;qsm_pcie_anoc_cfg,</div><div class='add'>+	[MASTER_PCIE_0] = &amp;xm_pcie3_0,</div><div class='add'>+	[MASTER_PCIE_1] = &amp;xm_pcie3_1,</div><div class='add'>+	[SLAVE_ANOC_PCIE_GEM_NOC] = &amp;qns_pcie_mem_noc,</div><div class='add'>+	[SLAVE_SERVICE_PCIE_ANOC] = &amp;srvc_pcie_aggre_noc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_pcie_anoc = {</div><div class='add'>+	.nodes = pcie_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),</div><div class='add'>+	.bcms = pcie_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const system_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_sn0,</div><div class='add'>+	&amp;bcm_sn2,</div><div class='add'>+	&amp;bcm_sn3,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const system_noc_nodes[] = {</div><div class='add'>+	[MASTER_A1NOC_SNOC] = &amp;qnm_aggre1_noc,</div><div class='add'>+	[MASTER_A2NOC_SNOC] = &amp;qnm_aggre2_noc,</div><div class='add'>+	[SLAVE_SNOC_GEM_NOC_SF] = &amp;qns_gemnoc_sf,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc sm8650_system_noc = {</div><div class='add'>+	.nodes = system_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(system_noc_nodes),</div><div class='add'>+	.bcms = system_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(system_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id qnoc_of_match[] = {</div><div class='add'>+	{ .compatible = "qcom,sm8650-aggre1-noc", .data = &amp;sm8650_aggre1_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-aggre2-noc", .data = &amp;sm8650_aggre2_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-clk-virt", .data = &amp;sm8650_clk_virt },</div><div class='add'>+	{ .compatible = "qcom,sm8650-config-noc", .data = &amp;sm8650_config_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-cnoc-main", .data = &amp;sm8650_cnoc_main },</div><div class='add'>+	{ .compatible = "qcom,sm8650-gem-noc", .data = &amp;sm8650_gem_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-lpass-ag-noc", .data = &amp;sm8650_lpass_ag_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &amp;sm8650_lpass_lpiaon_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-lpass-lpicx-noc", .data = &amp;sm8650_lpass_lpicx_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-mc-virt", .data = &amp;sm8650_mc_virt },</div><div class='add'>+	{ .compatible = "qcom,sm8650-mmss-noc", .data = &amp;sm8650_mmss_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-nsp-noc", .data = &amp;sm8650_nsp_noc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-pcie-anoc", .data = &amp;sm8650_pcie_anoc },</div><div class='add'>+	{ .compatible = "qcom,sm8650-system-noc", .data = &amp;sm8650_system_noc },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, qnoc_of_match);</div><div class='add'>+</div><div class='add'>+static struct platform_driver qnoc_driver = {</div><div class='add'>+	.probe = qcom_icc_rpmh_probe,</div><div class='add'>+	.remove_new = qcom_icc_rpmh_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "qnoc-sm8650",</div><div class='add'>+		.of_match_table = qnoc_of_match,</div><div class='add'>+		.sync_state = icc_sync_state,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init qnoc_driver_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+core_initcall(qnoc_driver_init);</div><div class='add'>+</div><div class='add'>+static void __exit qnoc_driver_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(qnoc_driver_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("sm8650 NoC driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/interconnect/qcom/sm8650.h b/drivers/interconnect/qcom/sm8650.h<br/>new file mode 100644<br/>index 000000000000..de35c956fe49<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/sm8650.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/sm8650.h</a></div><div class='hunk'>@@ -0,0 +1,143 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * SM8650 interconnect IDs</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H</div><div class='add'>+#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H</div><div class='add'>+</div><div class='add'>+#define SM8650_MASTER_A1NOC_SNOC		0</div><div class='add'>+#define SM8650_MASTER_A2NOC_SNOC		1</div><div class='add'>+#define SM8650_MASTER_ANOC_PCIE_GEM_NOC		2</div><div class='add'>+#define SM8650_MASTER_APPSS_PROC		3</div><div class='add'>+#define SM8650_MASTER_CAMNOC_HF			4</div><div class='add'>+#define SM8650_MASTER_CAMNOC_ICP		5</div><div class='add'>+#define SM8650_MASTER_CAMNOC_SF			6</div><div class='add'>+#define SM8650_MASTER_CDSP_HCP			7</div><div class='add'>+#define SM8650_MASTER_CDSP_PROC			8</div><div class='add'>+#define SM8650_MASTER_CNOC_CFG			9</div><div class='add'>+#define SM8650_MASTER_CNOC_MNOC_CFG		10</div><div class='add'>+#define SM8650_MASTER_COMPUTE_NOC		11</div><div class='add'>+#define SM8650_MASTER_CRYPTO			12</div><div class='add'>+#define SM8650_MASTER_GEM_NOC_CNOC		13</div><div class='add'>+#define SM8650_MASTER_GEM_NOC_PCIE_SNOC		14</div><div class='add'>+#define SM8650_MASTER_GFX3D			15</div><div class='add'>+#define SM8650_MASTER_GIC			16</div><div class='add'>+#define SM8650_MASTER_GPU_TCU			17</div><div class='add'>+#define SM8650_MASTER_IPA			18</div><div class='add'>+#define SM8650_MASTER_LLCC			19</div><div class='add'>+#define SM8650_MASTER_LPASS_GEM_NOC		20</div><div class='add'>+#define SM8650_MASTER_LPASS_LPINOC		21</div><div class='add'>+#define SM8650_MASTER_LPASS_PROC		22</div><div class='add'>+#define SM8650_MASTER_LPIAON_NOC		23</div><div class='add'>+#define SM8650_MASTER_MDP			24</div><div class='add'>+#define SM8650_MASTER_MNOC_HF_MEM_NOC		25</div><div class='add'>+#define SM8650_MASTER_MNOC_SF_MEM_NOC		26</div><div class='add'>+#define SM8650_MASTER_MSS_PROC			27</div><div class='add'>+#define SM8650_MASTER_PCIE_0			28</div><div class='add'>+#define SM8650_MASTER_PCIE_1			29</div><div class='add'>+#define SM8650_MASTER_PCIE_ANOC_CFG		30</div><div class='add'>+#define SM8650_MASTER_QDSS_BAM			31</div><div class='add'>+#define SM8650_MASTER_QDSS_ETR			32</div><div class='add'>+#define SM8650_MASTER_QDSS_ETR_1		33</div><div class='add'>+#define SM8650_MASTER_QSPI_0			34</div><div class='add'>+#define SM8650_MASTER_QUP_1			35</div><div class='add'>+#define SM8650_MASTER_QUP_2			36</div><div class='add'>+#define SM8650_MASTER_QUP_3			37</div><div class='add'>+#define SM8650_MASTER_QUP_CORE_0		38</div><div class='add'>+#define SM8650_MASTER_QUP_CORE_1		39</div><div class='add'>+#define SM8650_MASTER_QUP_CORE_2		40</div><div class='add'>+#define SM8650_MASTER_SDCC_2			41</div><div class='add'>+#define SM8650_MASTER_SDCC_4			42</div><div class='add'>+#define SM8650_MASTER_SNOC_SF_MEM_NOC		43</div><div class='add'>+#define SM8650_MASTER_SP			44</div><div class='add'>+#define SM8650_MASTER_SYS_TCU			45</div><div class='add'>+#define SM8650_MASTER_UBWC_P			46</div><div class='add'>+#define SM8650_MASTER_UBWC_P_TCU		47</div><div class='add'>+#define SM8650_MASTER_UFS_MEM			48</div><div class='add'>+#define SM8650_MASTER_USB3_0			49</div><div class='add'>+#define SM8650_MASTER_VIDEO			50</div><div class='add'>+#define SM8650_MASTER_VIDEO_CV_PROC		51</div><div class='add'>+#define SM8650_MASTER_VIDEO_PROC		52</div><div class='add'>+#define SM8650_MASTER_VIDEO_V_PROC		53</div><div class='add'>+#define SM8650_SLAVE_A1NOC_SNOC			54</div><div class='add'>+#define SM8650_SLAVE_A2NOC_SNOC			55</div><div class='add'>+#define SM8650_SLAVE_AHB2PHY_NORTH		56</div><div class='add'>+#define SM8650_SLAVE_AHB2PHY_SOUTH		57</div><div class='add'>+#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC		58</div><div class='add'>+#define SM8650_SLAVE_AOSS			59</div><div class='add'>+#define SM8650_SLAVE_APPSS			60</div><div class='add'>+#define SM8650_SLAVE_CAMERA_CFG			61</div><div class='add'>+#define SM8650_SLAVE_CDSP_MEM_NOC		62</div><div class='add'>+#define SM8650_SLAVE_CLK_CTL			63</div><div class='add'>+#define SM8650_SLAVE_CNOC_CFG			64</div><div class='add'>+#define SM8650_SLAVE_CNOC_MNOC_CFG		65</div><div class='add'>+#define SM8650_SLAVE_CNOC_MSS			66</div><div class='add'>+#define SM8650_SLAVE_CPR_HMX			67</div><div class='add'>+#define SM8650_SLAVE_CPR_NSPCX			68</div><div class='add'>+#define SM8650_SLAVE_CRYPTO_0_CFG		69</div><div class='add'>+#define SM8650_SLAVE_CX_RDPM			70</div><div class='add'>+#define SM8650_SLAVE_DDRSS_CFG			71</div><div class='add'>+#define SM8650_SLAVE_DISPLAY_CFG		72</div><div class='add'>+#define SM8650_SLAVE_EBI1			73</div><div class='add'>+#define SM8650_SLAVE_GEM_NOC_CNOC		74</div><div class='add'>+#define SM8650_SLAVE_GFX3D_CFG			75</div><div class='add'>+#define SM8650_SLAVE_I2C			76</div><div class='add'>+#define SM8650_SLAVE_I3C_IBI0_CFG		77</div><div class='add'>+#define SM8650_SLAVE_I3C_IBI1_CFG		78</div><div class='add'>+#define SM8650_SLAVE_IMEM			79</div><div class='add'>+#define SM8650_SLAVE_IMEM_CFG			80</div><div class='add'>+#define SM8650_SLAVE_IPA_CFG			81</div><div class='add'>+#define SM8650_SLAVE_IPC_ROUTER_CFG		82</div><div class='add'>+#define SM8650_SLAVE_LLCC			83</div><div class='add'>+#define SM8650_SLAVE_LPASS_GEM_NOC		84</div><div class='add'>+#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC	85</div><div class='add'>+#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC	86</div><div class='add'>+#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC		87</div><div class='add'>+#define SM8650_SLAVE_MNOC_HF_MEM_NOC		88</div><div class='add'>+#define SM8650_SLAVE_MNOC_SF_MEM_NOC		89</div><div class='add'>+#define SM8650_SLAVE_MX_2_RDPM			90</div><div class='add'>+#define SM8650_SLAVE_MX_RDPM			91</div><div class='add'>+#define SM8650_SLAVE_NSP_QTB_CFG		92</div><div class='add'>+#define SM8650_SLAVE_PCIE_0			93</div><div class='add'>+#define SM8650_SLAVE_PCIE_1			94</div><div class='add'>+#define SM8650_SLAVE_PCIE_0_CFG			95</div><div class='add'>+#define SM8650_SLAVE_PCIE_1_CFG			96</div><div class='add'>+#define SM8650_SLAVE_PCIE_ANOC_CFG		97</div><div class='add'>+#define SM8650_SLAVE_PCIE_RSCC			98</div><div class='add'>+#define SM8650_SLAVE_PDM			99</div><div class='add'>+#define SM8650_SLAVE_PRNG			100</div><div class='add'>+#define SM8650_SLAVE_QDSS_CFG			101</div><div class='add'>+#define SM8650_SLAVE_QDSS_STM			102</div><div class='add'>+#define SM8650_SLAVE_QSPI_0			103</div><div class='add'>+#define SM8650_SLAVE_QUP_1			104</div><div class='add'>+#define SM8650_SLAVE_QUP_2			105</div><div class='add'>+#define SM8650_SLAVE_QUP_3			106</div><div class='add'>+#define SM8650_SLAVE_QUP_CORE_0			107</div><div class='add'>+#define SM8650_SLAVE_QUP_CORE_1			108</div><div class='add'>+#define SM8650_SLAVE_QUP_CORE_2			109</div><div class='add'>+#define SM8650_SLAVE_RBCPR_CX_CFG		110</div><div class='add'>+#define SM8650_SLAVE_RBCPR_MMCX_CFG		111</div><div class='add'>+#define SM8650_SLAVE_RBCPR_MXA_CFG		112</div><div class='add'>+#define SM8650_SLAVE_RBCPR_MXC_CFG		113</div><div class='add'>+#define SM8650_SLAVE_SDCC_2			114</div><div class='add'>+#define SM8650_SLAVE_SDCC_4			115</div><div class='add'>+#define SM8650_SLAVE_SERVICE_CNOC		116</div><div class='add'>+#define SM8650_SLAVE_SERVICE_CNOC_CFG		117</div><div class='add'>+#define SM8650_SLAVE_SERVICE_MNOC		118</div><div class='add'>+#define SM8650_SLAVE_SERVICE_PCIE_ANOC		119</div><div class='add'>+#define SM8650_SLAVE_SNOC_GEM_NOC_SF		120</div><div class='add'>+#define SM8650_SLAVE_SPSS_CFG			121</div><div class='add'>+#define SM8650_SLAVE_TCSR			122</div><div class='add'>+#define SM8650_SLAVE_TCU			123</div><div class='add'>+#define SM8650_SLAVE_TLMM			124</div><div class='add'>+#define SM8650_SLAVE_TME_CFG			125</div><div class='add'>+#define SM8650_SLAVE_UFS_MEM_CFG		126</div><div class='add'>+#define SM8650_SLAVE_USB3_0			127</div><div class='add'>+#define SM8650_SLAVE_VENUS_CFG			128</div><div class='add'>+#define SM8650_SLAVE_VSENSE_CTRL_CFG		129</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c<br/>index 16a145a3c914..3816bfb4e2f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/smd-rpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/qcom/smd-rpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/smd-rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/smd-rpm.c</a></div><div class='hunk'>@@ -63,11 +63,9 @@ int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 r</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate);</div><div class='ctx'> </div><div class='del'>-static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_icc_rpm_smd_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	icc_smd_rpm = NULL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)</div><div class='hunk'>@@ -87,7 +85,7 @@ static struct platform_driver qcom_interconnect_rpm_smd_driver = {</div><div class='ctx'> 		.name		= "icc_smd_rpm",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = qcom_icc_rpm_smd_probe,</div><div class='del'>-	.remove = qcom_icc_rpm_smd_remove,</div><div class='add'>+	.remove_new = qcom_icc_rpm_smd_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(qcom_interconnect_rpm_smd_driver);</div><div class='ctx'> MODULE_AUTHOR("Georgi Djakov &lt;georgi.djakov@linaro.org&gt;");</div><div class='head'>diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c<br/>new file mode 100644<br/>index 000000000000..d19501d913b3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/x1e80100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/x1e80100.c</a></div><div class='hunk'>@@ -0,0 +1,2328 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/interconnect.h&gt;</div><div class='add'>+#include &lt;linux/interconnect-provider.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;dt-bindings/interconnect/qcom,x1e80100-rpmh.h&gt;</div><div class='add'>+</div><div class='add'>+#include "bcm-voter.h"</div><div class='add'>+#include "icc-common.h"</div><div class='add'>+#include "icc-rpmh.h"</div><div class='add'>+#include "x1e80100.h"</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qspi = {</div><div class='add'>+	.name = "qhm_qspi",</div><div class='add'>+	.id = X1E80100_MASTER_QSPI_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup1 = {</div><div class='add'>+	.name = "qhm_qup1",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc4 = {</div><div class='add'>+	.name = "xm_sdc4",</div><div class='add'>+	.id = X1E80100_MASTER_SDCC_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_ufs_mem = {</div><div class='add'>+	.name = "xm_ufs_mem",</div><div class='add'>+	.id = X1E80100_MASTER_UFS_MEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup0 = {</div><div class='add'>+	.name = "qhm_qup0",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhm_qup2 = {</div><div class='add'>+	.name = "qhm_qup2",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_crypto = {</div><div class='add'>+	.name = "qxm_crypto",</div><div class='add'>+	.id = X1E80100_MASTER_CRYPTO,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_sp = {</div><div class='add'>+	.name = "qxm_sp",</div><div class='add'>+	.id = X1E80100_MASTER_SP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_qdss_etr_0 = {</div><div class='add'>+	.name = "xm_qdss_etr_0",</div><div class='add'>+	.id = X1E80100_MASTER_QDSS_ETR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_qdss_etr_1 = {</div><div class='add'>+	.name = "xm_qdss_etr_1",</div><div class='add'>+	.id = X1E80100_MASTER_QDSS_ETR_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_sdc2 = {</div><div class='add'>+	.name = "xm_sdc2",</div><div class='add'>+	.id = X1E80100_MASTER_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ddr_perf_mode_master = {</div><div class='add'>+	.name = "ddr_perf_mode_master",</div><div class='add'>+	.id = X1E80100_MASTER_DDR_PERF_MODE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_DDR_PERF_MODE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_master = {</div><div class='add'>+	.name = "qup0_core_master",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_QUP_CORE_0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup1_core_master = {</div><div class='add'>+	.name = "qup1_core_master",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_CORE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_QUP_CORE_1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup2_core_master = {</div><div class='add'>+	.name = "qup2_core_master",</div><div class='add'>+	.id = X1E80100_MASTER_QUP_CORE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_QUP_CORE_2 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qsm_cfg = {</div><div class='add'>+	.name = "qsm_cfg",</div><div class='add'>+	.id = X1E80100_MASTER_CNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 47,</div><div class='add'>+	.links = { X1E80100_SLAVE_AHB2PHY_SOUTH, X1E80100_SLAVE_AHB2PHY_NORTH,</div><div class='add'>+		   X1E80100_SLAVE_AHB2PHY_2, X1E80100_SLAVE_AV1_ENC_CFG,</div><div class='add'>+		   X1E80100_SLAVE_CAMERA_CFG, X1E80100_SLAVE_CLK_CTL,</div><div class='add'>+		   X1E80100_SLAVE_CRYPTO_0_CFG, X1E80100_SLAVE_DISPLAY_CFG,</div><div class='add'>+		   X1E80100_SLAVE_GFX3D_CFG, X1E80100_SLAVE_IMEM_CFG,</div><div class='add'>+		   X1E80100_SLAVE_IPC_ROUTER_CFG, X1E80100_SLAVE_PCIE_0_CFG,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_1_CFG, X1E80100_SLAVE_PCIE_2_CFG,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_3_CFG, X1E80100_SLAVE_PCIE_4_CFG,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_5_CFG, X1E80100_SLAVE_PCIE_6A_CFG,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_6B_CFG, X1E80100_SLAVE_PCIE_RSC_CFG,</div><div class='add'>+		   X1E80100_SLAVE_PDM, X1E80100_SLAVE_PRNG,</div><div class='add'>+		   X1E80100_SLAVE_QDSS_CFG, X1E80100_SLAVE_QSPI_0,</div><div class='add'>+		   X1E80100_SLAVE_QUP_0, X1E80100_SLAVE_QUP_1,</div><div class='add'>+		   X1E80100_SLAVE_QUP_2, X1E80100_SLAVE_SDCC_2,</div><div class='add'>+		   X1E80100_SLAVE_SDCC_4, X1E80100_SLAVE_SMMUV3_CFG,</div><div class='add'>+		   X1E80100_SLAVE_TCSR, X1E80100_SLAVE_TLMM,</div><div class='add'>+		   X1E80100_SLAVE_UFS_MEM_CFG, X1E80100_SLAVE_USB2,</div><div class='add'>+		   X1E80100_SLAVE_USB3_0, X1E80100_SLAVE_USB3_1,</div><div class='add'>+		   X1E80100_SLAVE_USB3_2, X1E80100_SLAVE_USB3_MP,</div><div class='add'>+		   X1E80100_SLAVE_USB4_0, X1E80100_SLAVE_USB4_1,</div><div class='add'>+		   X1E80100_SLAVE_USB4_2, X1E80100_SLAVE_VENUS_CFG,</div><div class='add'>+		   X1E80100_SLAVE_LPASS_QTB_CFG, X1E80100_SLAVE_CNOC_MNOC_CFG,</div><div class='add'>+		   X1E80100_SLAVE_NSP_QTB_CFG, X1E80100_SLAVE_QDSS_STM,</div><div class='add'>+		   X1E80100_SLAVE_TCU },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gemnoc_cnoc = {</div><div class='add'>+	.name = "qnm_gemnoc_cnoc",</div><div class='add'>+	.id = X1E80100_MASTER_GEM_NOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 6,</div><div class='add'>+	.links = { X1E80100_SLAVE_AOSS, X1E80100_SLAVE_TME_CFG,</div><div class='add'>+		   X1E80100_SLAVE_APPSS, X1E80100_SLAVE_CNOC_CFG,</div><div class='add'>+		   X1E80100_SLAVE_BOOT_IMEM, X1E80100_SLAVE_IMEM },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gemnoc_pcie = {</div><div class='add'>+	.name = "qnm_gemnoc_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_GEM_NOC_PCIE_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 8,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_0, X1E80100_SLAVE_PCIE_1,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_2, X1E80100_SLAVE_PCIE_3,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_4, X1E80100_SLAVE_PCIE_5,</div><div class='add'>+		   X1E80100_SLAVE_PCIE_6A, X1E80100_SLAVE_PCIE_6B },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_gpu_tcu = {</div><div class='add'>+	.name = "alm_gpu_tcu",</div><div class='add'>+	.id = X1E80100_MASTER_GPU_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_pcie_tcu = {</div><div class='add'>+	.name = "alm_pcie_tcu",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node alm_sys_tcu = {</div><div class='add'>+	.name = "alm_sys_tcu",</div><div class='add'>+	.id = X1E80100_MASTER_SYS_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node chm_apps = {</div><div class='add'>+	.name = "chm_apps",</div><div class='add'>+	.id = X1E80100_MASTER_APPSS_PROC,</div><div class='add'>+	.channels = 6,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,</div><div class='add'>+		   X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gpu = {</div><div class='add'>+	.name = "qnm_gpu",</div><div class='add'>+	.id = X1E80100_MASTER_GFX3D,</div><div class='add'>+	.channels = 4,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpass = {</div><div class='add'>+	.name = "qnm_lpass",</div><div class='add'>+	.id = X1E80100_MASTER_LPASS_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,</div><div class='add'>+		   X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mnoc_hf = {</div><div class='add'>+	.name = "qnm_mnoc_hf",</div><div class='add'>+	.id = X1E80100_MASTER_MNOC_HF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mnoc_sf = {</div><div class='add'>+	.name = "qnm_mnoc_sf",</div><div class='add'>+	.id = X1E80100_MASTER_MNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_nsp_noc = {</div><div class='add'>+	.name = "qnm_nsp_noc",</div><div class='add'>+	.id = X1E80100_MASTER_COMPUTE_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,</div><div class='add'>+		   X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie = {</div><div class='add'>+	.name = "qnm_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 2,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_snoc_sf = {</div><div class='add'>+	.name = "qnm_snoc_sf",</div><div class='add'>+	.id = X1E80100_MASTER_SNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 3,</div><div class='add'>+	.links = { X1E80100_SLAVE_GEM_NOC_CNOC, X1E80100_SLAVE_LLCC,</div><div class='add'>+		   X1E80100_SLAVE_MEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_gic = {</div><div class='add'>+	.name = "xm_gic",</div><div class='add'>+	.id = X1E80100_MASTER_GIC2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpiaon_noc = {</div><div class='add'>+	.name = "qnm_lpiaon_noc",</div><div class='add'>+	.id = X1E80100_MASTER_LPIAON_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LPASS_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_lpass_lpinoc = {</div><div class='add'>+	.name = "qnm_lpass_lpinoc",</div><div class='add'>+	.id = X1E80100_MASTER_LPASS_LPINOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_lpinoc_dsp_axim = {</div><div class='add'>+	.name = "qxm_lpinoc_dsp_axim",</div><div class='add'>+	.id = X1E80100_MASTER_LPASS_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node llcc_mc = {</div><div class='add'>+	.name = "llcc_mc",</div><div class='add'>+	.id = X1E80100_MASTER_LLCC,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_EBI1 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_av1_enc = {</div><div class='add'>+	.name = "qnm_av1_enc",</div><div class='add'>+	.id = X1E80100_MASTER_AV1_ENC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_hf = {</div><div class='add'>+	.name = "qnm_camnoc_hf",</div><div class='add'>+	.id = X1E80100_MASTER_CAMNOC_HF,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_icp = {</div><div class='add'>+	.name = "qnm_camnoc_icp",</div><div class='add'>+	.id = X1E80100_MASTER_CAMNOC_ICP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_camnoc_sf = {</div><div class='add'>+	.name = "qnm_camnoc_sf",</div><div class='add'>+	.id = X1E80100_MASTER_CAMNOC_SF,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_eva = {</div><div class='add'>+	.name = "qnm_eva",</div><div class='add'>+	.id = X1E80100_MASTER_EVA,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mdp = {</div><div class='add'>+	.name = "qnm_mdp",</div><div class='add'>+	.id = X1E80100_MASTER_MDP,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video = {</div><div class='add'>+	.name = "qnm_video",</div><div class='add'>+	.id = X1E80100_MASTER_VIDEO,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video_cv_cpu = {</div><div class='add'>+	.name = "qnm_video_cv_cpu",</div><div class='add'>+	.id = X1E80100_MASTER_VIDEO_CV_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_video_v_cpu = {</div><div class='add'>+	.name = "qnm_video_v_cpu",</div><div class='add'>+	.id = X1E80100_MASTER_VIDEO_V_PROC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qsm_mnoc_cfg = {</div><div class='add'>+	.name = "qsm_mnoc_cfg",</div><div class='add'>+	.id = X1E80100_MASTER_CNOC_MNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_SERVICE_MNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxm_nsp = {</div><div class='add'>+	.name = "qxm_nsp",</div><div class='add'>+	.id = X1E80100_MASTER_CDSP_PROC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_CDSP_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_north_gem_noc = {</div><div class='add'>+	.name = "qnm_pcie_north_gem_noc",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_south_gem_noc = {</div><div class='add'>+	.name = "qnm_pcie_south_gem_noc",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_3 = {</div><div class='add'>+	.name = "xm_pcie_3",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_4 = {</div><div class='add'>+	.name = "xm_pcie_4",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_5 = {</div><div class='add'>+	.name = "xm_pcie_5",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_5,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_0 = {</div><div class='add'>+	.name = "xm_pcie_0",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_1 = {</div><div class='add'>+	.name = "xm_pcie_1",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_2 = {</div><div class='add'>+	.name = "xm_pcie_2",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_6a = {</div><div class='add'>+	.name = "xm_pcie_6a",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_6A,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_6b = {</div><div class='add'>+	.name = "xm_pcie_6b",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_6B,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre1_noc = {</div><div class='add'>+	.name = "qnm_aggre1_noc",</div><div class='add'>+	.id = X1E80100_MASTER_A1NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre2_noc = {</div><div class='add'>+	.name = "qnm_aggre2_noc",</div><div class='add'>+	.id = X1E80100_MASTER_A2NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_gic = {</div><div class='add'>+	.name = "qnm_gic",</div><div class='add'>+	.id = X1E80100_MASTER_GIC1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_usb_anoc = {</div><div class='add'>+	.name = "qnm_usb_anoc",</div><div class='add'>+	.id = X1E80100_MASTER_USB_NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_SNOC_GEM_NOC_SF },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre_usb_north_snoc = {</div><div class='add'>+	.name = "qnm_aggre_usb_north_snoc",</div><div class='add'>+	.id = X1E80100_MASTER_AGGRE_USB_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_USB_NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_aggre_usb_south_snoc = {</div><div class='add'>+	.name = "qnm_aggre_usb_south_snoc",</div><div class='add'>+	.id = X1E80100_MASTER_AGGRE_USB_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_USB_NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb2_0 = {</div><div class='add'>+	.name = "xm_usb2_0",</div><div class='add'>+	.id = X1E80100_MASTER_USB2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_mp = {</div><div class='add'>+	.name = "xm_usb3_mp",</div><div class='add'>+	.id = X1E80100_MASTER_USB3_MP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_0 = {</div><div class='add'>+	.name = "xm_usb3_0",</div><div class='add'>+	.id = X1E80100_MASTER_USB3_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_1 = {</div><div class='add'>+	.name = "xm_usb3_1",</div><div class='add'>+	.id = X1E80100_MASTER_USB3_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb3_2 = {</div><div class='add'>+	.name = "xm_usb3_2",</div><div class='add'>+	.id = X1E80100_MASTER_USB3_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb4_0 = {</div><div class='add'>+	.name = "xm_usb4_0",</div><div class='add'>+	.id = X1E80100_MASTER_USB4_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb4_1 = {</div><div class='add'>+	.name = "xm_usb4_1",</div><div class='add'>+	.id = X1E80100_MASTER_USB4_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_usb4_2 = {</div><div class='add'>+	.name = "xm_usb4_2",</div><div class='add'>+	.id = X1E80100_MASTER_USB4_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mnoc_hf_disp = {</div><div class='add'>+	.name = "qnm_mnoc_hf_disp",</div><div class='add'>+	.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LLCC_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_disp = {</div><div class='add'>+	.name = "qnm_pcie_disp",</div><div class='add'>+	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LLCC_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node llcc_mc_disp = {</div><div class='add'>+	.name = "llcc_mc_disp",</div><div class='add'>+	.id = X1E80100_MASTER_LLCC_DISP,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_EBI1_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_mdp_disp = {</div><div class='add'>+	.name = "qnm_mdp_disp",</div><div class='add'>+	.id = X1E80100_MASTER_MDP_DISP,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_pcie = {</div><div class='add'>+	.name = "qnm_pcie_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_LLCC_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node llcc_mc_pcie = {</div><div class='add'>+	.name = "llcc_mc_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_LLCC_PCIE,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_EBI1_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {</div><div class='add'>+	.name = "qnm_pcie_north_gem_noc_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_NORTH_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {</div><div class='add'>+	.name = "qnm_pcie_south_gem_noc_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_3_pcie = {</div><div class='add'>+	.name = "xm_pcie_3_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_3_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_4_pcie = {</div><div class='add'>+	.name = "xm_pcie_4_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_4_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_5_pcie = {</div><div class='add'>+	.name = "xm_pcie_5_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_5_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_0_pcie = {</div><div class='add'>+	.name = "xm_pcie_0_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_0_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_1_pcie = {</div><div class='add'>+	.name = "xm_pcie_1_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_1_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_2_pcie = {</div><div class='add'>+	.name = "xm_pcie_2_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_2_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_6a_pcie = {</div><div class='add'>+	.name = "xm_pcie_6a_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_6A_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xm_pcie_6b_pcie = {</div><div class='add'>+	.name = "xm_pcie_6b_pcie",</div><div class='add'>+	.id = X1E80100_MASTER_PCIE_6B_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_a1noc_snoc = {</div><div class='add'>+	.name = "qns_a1noc_snoc",</div><div class='add'>+	.id = X1E80100_SLAVE_A1NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_A1NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_a2noc_snoc = {</div><div class='add'>+	.name = "qns_a2noc_snoc",</div><div class='add'>+	.id = X1E80100_SLAVE_A2NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_A2NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ddr_perf_mode_slave = {</div><div class='add'>+	.name = "ddr_perf_mode_slave",</div><div class='add'>+	.id = X1E80100_SLAVE_DDR_PERF_MODE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup0_core_slave = {</div><div class='add'>+	.name = "qup0_core_slave",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_CORE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup1_core_slave = {</div><div class='add'>+	.name = "qup1_core_slave",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_CORE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qup2_core_slave = {</div><div class='add'>+	.name = "qup2_core_slave",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_CORE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy0 = {</div><div class='add'>+	.name = "qhs_ahb2phy0",</div><div class='add'>+	.id = X1E80100_SLAVE_AHB2PHY_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy1 = {</div><div class='add'>+	.name = "qhs_ahb2phy1",</div><div class='add'>+	.id = X1E80100_SLAVE_AHB2PHY_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ahb2phy2 = {</div><div class='add'>+	.name = "qhs_ahb2phy2",</div><div class='add'>+	.id = X1E80100_SLAVE_AHB2PHY_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_av1_enc_cfg = {</div><div class='add'>+	.name = "qhs_av1_enc_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_AV1_ENC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_camera_cfg = {</div><div class='add'>+	.name = "qhs_camera_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_CAMERA_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_clk_ctl = {</div><div class='add'>+	.name = "qhs_clk_ctl",</div><div class='add'>+	.id = X1E80100_SLAVE_CLK_CTL,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_crypto0_cfg = {</div><div class='add'>+	.name = "qhs_crypto0_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_CRYPTO_0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_display_cfg = {</div><div class='add'>+	.name = "qhs_display_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_DISPLAY_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_gpuss_cfg = {</div><div class='add'>+	.name = "qhs_gpuss_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_GFX3D_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_imem_cfg = {</div><div class='add'>+	.name = "qhs_imem_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_IMEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ipc_router = {</div><div class='add'>+	.name = "qhs_ipc_router",</div><div class='add'>+	.id = X1E80100_SLAVE_IPC_ROUTER_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie0_cfg = {</div><div class='add'>+	.name = "qhs_pcie0_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_0_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie1_cfg = {</div><div class='add'>+	.name = "qhs_pcie1_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_1_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie2_cfg = {</div><div class='add'>+	.name = "qhs_pcie2_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_2_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie3_cfg = {</div><div class='add'>+	.name = "qhs_pcie3_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_3_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie4_cfg = {</div><div class='add'>+	.name = "qhs_pcie4_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_4_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie5_cfg = {</div><div class='add'>+	.name = "qhs_pcie5_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_5_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie6a_cfg = {</div><div class='add'>+	.name = "qhs_pcie6a_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_6A_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie6b_cfg = {</div><div class='add'>+	.name = "qhs_pcie6b_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_6B_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pcie_rsc_cfg = {</div><div class='add'>+	.name = "qhs_pcie_rsc_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_RSC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_pdm = {</div><div class='add'>+	.name = "qhs_pdm",</div><div class='add'>+	.id = X1E80100_SLAVE_PDM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_prng = {</div><div class='add'>+	.name = "qhs_prng",</div><div class='add'>+	.id = X1E80100_SLAVE_PRNG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qdss_cfg = {</div><div class='add'>+	.name = "qhs_qdss_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_QDSS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qspi = {</div><div class='add'>+	.name = "qhs_qspi",</div><div class='add'>+	.id = X1E80100_SLAVE_QSPI_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup0 = {</div><div class='add'>+	.name = "qhs_qup0",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup1 = {</div><div class='add'>+	.name = "qhs_qup1",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_qup2 = {</div><div class='add'>+	.name = "qhs_qup2",</div><div class='add'>+	.id = X1E80100_SLAVE_QUP_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc2 = {</div><div class='add'>+	.name = "qhs_sdc2",</div><div class='add'>+	.id = X1E80100_SLAVE_SDCC_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_sdc4 = {</div><div class='add'>+	.name = "qhs_sdc4",</div><div class='add'>+	.id = X1E80100_SLAVE_SDCC_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_smmuv3_cfg = {</div><div class='add'>+	.name = "qhs_smmuv3_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_SMMUV3_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tcsr = {</div><div class='add'>+	.name = "qhs_tcsr",</div><div class='add'>+	.id = X1E80100_SLAVE_TCSR,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tlmm = {</div><div class='add'>+	.name = "qhs_tlmm",</div><div class='add'>+	.id = X1E80100_SLAVE_TLMM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_ufs_mem_cfg = {</div><div class='add'>+	.name = "qhs_ufs_mem_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_UFS_MEM_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb2_0_cfg = {</div><div class='add'>+	.name = "qhs_usb2_0_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3_0_cfg = {</div><div class='add'>+	.name = "qhs_usb3_0_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB3_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3_1_cfg = {</div><div class='add'>+	.name = "qhs_usb3_1_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB3_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3_2_cfg = {</div><div class='add'>+	.name = "qhs_usb3_2_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB3_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb3_mp_cfg = {</div><div class='add'>+	.name = "qhs_usb3_mp_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB3_MP,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb4_0_cfg = {</div><div class='add'>+	.name = "qhs_usb4_0_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB4_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb4_1_cfg = {</div><div class='add'>+	.name = "qhs_usb4_1_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB4_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_usb4_2_cfg = {</div><div class='add'>+	.name = "qhs_usb4_2_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_USB4_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_venus_cfg = {</div><div class='add'>+	.name = "qhs_venus_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_VENUS_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_lpass_qtb_cfg = {</div><div class='add'>+	.name = "qss_lpass_qtb_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_LPASS_QTB_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_mnoc_cfg = {</div><div class='add'>+	.name = "qss_mnoc_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_CNOC_MNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_CNOC_MNOC_CFG },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_nsp_qtb_cfg = {</div><div class='add'>+	.name = "qss_nsp_qtb_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_NSP_QTB_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_qdss_stm = {</div><div class='add'>+	.name = "xs_qdss_stm",</div><div class='add'>+	.id = X1E80100_SLAVE_QDSS_STM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_sys_tcu_cfg = {</div><div class='add'>+	.name = "xs_sys_tcu_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_TCU,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_aoss = {</div><div class='add'>+	.name = "qhs_aoss",</div><div class='add'>+	.id = X1E80100_SLAVE_AOSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qhs_tme_cfg = {</div><div class='add'>+	.name = "qhs_tme_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_TME_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_apss = {</div><div class='add'>+	.name = "qns_apss",</div><div class='add'>+	.id = X1E80100_SLAVE_APPSS,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qss_cfg = {</div><div class='add'>+	.name = "qss_cfg",</div><div class='add'>+	.id = X1E80100_SLAVE_CNOC_CFG,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_CNOC_CFG },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxs_boot_imem = {</div><div class='add'>+	.name = "qxs_boot_imem",</div><div class='add'>+	.id = X1E80100_SLAVE_BOOT_IMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qxs_imem = {</div><div class='add'>+	.name = "qxs_imem",</div><div class='add'>+	.id = X1E80100_SLAVE_IMEM,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_0 = {</div><div class='add'>+	.name = "xs_pcie_0",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_0,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_1 = {</div><div class='add'>+	.name = "xs_pcie_1",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_1,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_2 = {</div><div class='add'>+	.name = "xs_pcie_2",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_2,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_3 = {</div><div class='add'>+	.name = "xs_pcie_3",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_3,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_4 = {</div><div class='add'>+	.name = "xs_pcie_4",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_4,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_5 = {</div><div class='add'>+	.name = "xs_pcie_5",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_5,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 8,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_6a = {</div><div class='add'>+	.name = "xs_pcie_6a",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_6A,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node xs_pcie_6b = {</div><div class='add'>+	.name = "xs_pcie_6b",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_6B,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_gem_noc_cnoc = {</div><div class='add'>+	.name = "qns_gem_noc_cnoc",</div><div class='add'>+	.id = X1E80100_SLAVE_GEM_NOC_CNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_GEM_NOC_CNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_llcc = {</div><div class='add'>+	.name = "qns_llcc",</div><div class='add'>+	.id = X1E80100_SLAVE_LLCC,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LLCC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie = {</div><div class='add'>+	.name = "qns_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_MEM_NOC_PCIE_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_GEM_NOC_PCIE_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {</div><div class='add'>+	.name = "qns_lpass_ag_noc_gemnoc",</div><div class='add'>+	.id = X1E80100_SLAVE_LPASS_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LPASS_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpass_aggnoc = {</div><div class='add'>+	.name = "qns_lpass_aggnoc",</div><div class='add'>+	.id = X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LPIAON_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_lpi_aon_noc = {</div><div class='add'>+	.name = "qns_lpi_aon_noc",</div><div class='add'>+	.id = X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LPASS_LPINOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ebi = {</div><div class='add'>+	.name = "ebi",</div><div class='add'>+	.id = X1E80100_SLAVE_EBI1,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_mem_noc_hf = {</div><div class='add'>+	.name = "qns_mem_noc_hf",</div><div class='add'>+	.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_mem_noc_sf = {</div><div class='add'>+	.name = "qns_mem_noc_sf",</div><div class='add'>+	.id = X1E80100_SLAVE_MNOC_SF_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_MNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node srvc_mnoc = {</div><div class='add'>+	.name = "srvc_mnoc",</div><div class='add'>+	.id = X1E80100_SLAVE_SERVICE_MNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_nsp_gemnoc = {</div><div class='add'>+	.name = "qns_nsp_gemnoc",</div><div class='add'>+	.id = X1E80100_SLAVE_CDSP_MEM_NOC,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_COMPUTE_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_mem_noc = {</div><div class='add'>+	.name = "qns_pcie_mem_noc",</div><div class='add'>+	.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_north_gem_noc = {</div><div class='add'>+	.name = "qns_pcie_north_gem_noc",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_PCIE_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_south_gem_noc = {</div><div class='add'>+	.name = "qns_pcie_south_gem_noc",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_PCIE_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_gemnoc_sf = {</div><div class='add'>+	.name = "qns_gemnoc_sf",</div><div class='add'>+	.id = X1E80100_SLAVE_SNOC_GEM_NOC_SF,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_SNOC_SF_MEM_NOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_aggre_usb_snoc = {</div><div class='add'>+	.name = "qns_aggre_usb_snoc",</div><div class='add'>+	.id = X1E80100_SLAVE_USB_NOC_SNOC,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_USB_NOC_SNOC },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_aggre_usb_north_snoc = {</div><div class='add'>+	.name = "qns_aggre_usb_north_snoc",</div><div class='add'>+	.id = X1E80100_SLAVE_AGGRE_USB_NORTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_AGGRE_USB_NORTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_aggre_usb_south_snoc = {</div><div class='add'>+	.name = "qns_aggre_usb_south_snoc",</div><div class='add'>+	.id = X1E80100_SLAVE_AGGRE_USB_SOUTH,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_llcc_disp = {</div><div class='add'>+	.name = "qns_llcc_disp",</div><div class='add'>+	.id = X1E80100_SLAVE_LLCC_DISP,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LLCC_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ebi_disp = {</div><div class='add'>+	.name = "ebi_disp",</div><div class='add'>+	.id = X1E80100_SLAVE_EBI1_DISP,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_mem_noc_hf_disp = {</div><div class='add'>+	.name = "qns_mem_noc_hf_disp",</div><div class='add'>+	.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,</div><div class='add'>+	.channels = 2,</div><div class='add'>+	.buswidth = 32,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_llcc_pcie = {</div><div class='add'>+	.name = "qns_llcc_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_LLCC_PCIE,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 16,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_LLCC_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node ebi_pcie = {</div><div class='add'>+	.name = "ebi_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_EBI1_PCIE,</div><div class='add'>+	.channels = 8,</div><div class='add'>+	.buswidth = 4,</div><div class='add'>+	.num_links = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_mem_noc_pcie = {</div><div class='add'>+	.name = "qns_pcie_mem_noc_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {</div><div class='add'>+	.name = "qns_pcie_north_gem_noc_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {</div><div class='add'>+	.name = "qns_pcie_south_gem_noc_pcie",</div><div class='add'>+	.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,</div><div class='add'>+	.channels = 1,</div><div class='add'>+	.buswidth = 64,</div><div class='add'>+	.num_links = 1,</div><div class='add'>+	.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_acv = {</div><div class='add'>+	.name = "ACV",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_acv_perf = {</div><div class='add'>+	.name = "ACV_PERF",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ddr_perf_mode_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_ce0 = {</div><div class='add'>+	.name = "CE0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qxm_crypto },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_cn0 = {</div><div class='add'>+	.name = "CN0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 63,</div><div class='add'>+	.nodes = { &amp;qsm_cfg, &amp;qhs_ahb2phy0,</div><div class='add'>+		   &amp;qhs_ahb2phy1, &amp;qhs_ahb2phy2,</div><div class='add'>+		   &amp;qhs_av1_enc_cfg, &amp;qhs_camera_cfg,</div><div class='add'>+		   &amp;qhs_clk_ctl, &amp;qhs_crypto0_cfg,</div><div class='add'>+		   &amp;qhs_gpuss_cfg, &amp;qhs_imem_cfg,</div><div class='add'>+		   &amp;qhs_ipc_router, &amp;qhs_pcie0_cfg,</div><div class='add'>+		   &amp;qhs_pcie1_cfg, &amp;qhs_pcie2_cfg,</div><div class='add'>+		   &amp;qhs_pcie3_cfg, &amp;qhs_pcie4_cfg,</div><div class='add'>+		   &amp;qhs_pcie5_cfg, &amp;qhs_pcie6a_cfg,</div><div class='add'>+		   &amp;qhs_pcie6b_cfg, &amp;qhs_pcie_rsc_cfg,</div><div class='add'>+		   &amp;qhs_pdm, &amp;qhs_prng,</div><div class='add'>+		   &amp;qhs_qdss_cfg, &amp;qhs_qspi,</div><div class='add'>+		   &amp;qhs_qup0, &amp;qhs_qup1,</div><div class='add'>+		   &amp;qhs_qup2, &amp;qhs_sdc2,</div><div class='add'>+		   &amp;qhs_sdc4, &amp;qhs_smmuv3_cfg,</div><div class='add'>+		   &amp;qhs_tcsr, &amp;qhs_tlmm,</div><div class='add'>+		   &amp;qhs_ufs_mem_cfg, &amp;qhs_usb2_0_cfg,</div><div class='add'>+		   &amp;qhs_usb3_0_cfg, &amp;qhs_usb3_1_cfg,</div><div class='add'>+		   &amp;qhs_usb3_2_cfg, &amp;qhs_usb3_mp_cfg,</div><div class='add'>+		   &amp;qhs_usb4_0_cfg, &amp;qhs_usb4_1_cfg,</div><div class='add'>+		   &amp;qhs_usb4_2_cfg, &amp;qhs_venus_cfg,</div><div class='add'>+		   &amp;qss_lpass_qtb_cfg, &amp;qss_mnoc_cfg,</div><div class='add'>+		   &amp;qss_nsp_qtb_cfg, &amp;xs_qdss_stm,</div><div class='add'>+		   &amp;xs_sys_tcu_cfg, &amp;qnm_gemnoc_cnoc,</div><div class='add'>+		   &amp;qnm_gemnoc_pcie, &amp;qhs_aoss,</div><div class='add'>+		   &amp;qhs_tme_cfg, &amp;qns_apss,</div><div class='add'>+		   &amp;qss_cfg, &amp;qxs_boot_imem,</div><div class='add'>+		   &amp;qxs_imem, &amp;xs_pcie_0,</div><div class='add'>+		   &amp;xs_pcie_1, &amp;xs_pcie_2,</div><div class='add'>+		   &amp;xs_pcie_3, &amp;xs_pcie_4,</div><div class='add'>+		   &amp;xs_pcie_5, &amp;xs_pcie_6a,</div><div class='add'>+		   &amp;xs_pcie_6b },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_cn1 = {</div><div class='add'>+	.name = "CN1",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qhs_display_cfg },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_co0 = {</div><div class='add'>+	.name = "CO0",</div><div class='add'>+	.num_nodes = 2,</div><div class='add'>+	.nodes = { &amp;qxm_nsp, &amp;qns_nsp_gemnoc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_lp0 = {</div><div class='add'>+	.name = "LP0",</div><div class='add'>+	.num_nodes = 2,</div><div class='add'>+	.nodes = { &amp;qnm_lpass_lpinoc, &amp;qns_lpass_aggnoc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mc0 = {</div><div class='add'>+	.name = "MC0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm0 = {</div><div class='add'>+	.name = "MM0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_mem_noc_hf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm1 = {</div><div class='add'>+	.name = "MM1",</div><div class='add'>+	.num_nodes = 10,</div><div class='add'>+	.nodes = { &amp;qnm_av1_enc, &amp;qnm_camnoc_hf,</div><div class='add'>+		   &amp;qnm_camnoc_icp, &amp;qnm_camnoc_sf,</div><div class='add'>+		   &amp;qnm_eva, &amp;qnm_mdp,</div><div class='add'>+		   &amp;qnm_video, &amp;qnm_video_cv_cpu,</div><div class='add'>+		   &amp;qnm_video_v_cpu, &amp;qns_mem_noc_sf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_pc0 = {</div><div class='add'>+	.name = "PC0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_pcie_mem_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup0 = {</div><div class='add'>+	.name = "QUP0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup0_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup1 = {</div><div class='add'>+	.name = "QUP1",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup1_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_qup2 = {</div><div class='add'>+	.name = "QUP2",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.vote_scale = 1,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qup2_core_slave },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh0 = {</div><div class='add'>+	.name = "SH0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_llcc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh1 = {</div><div class='add'>+	.name = "SH1",</div><div class='add'>+	.num_nodes = 13,</div><div class='add'>+	.nodes = { &amp;alm_gpu_tcu, &amp;alm_pcie_tcu,</div><div class='add'>+		   &amp;alm_sys_tcu, &amp;chm_apps,</div><div class='add'>+		   &amp;qnm_gpu, &amp;qnm_lpass,</div><div class='add'>+		   &amp;qnm_mnoc_hf, &amp;qnm_mnoc_sf,</div><div class='add'>+		   &amp;qnm_nsp_noc, &amp;qnm_pcie,</div><div class='add'>+		   &amp;xm_gic, &amp;qns_gem_noc_cnoc,</div><div class='add'>+		   &amp;qns_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn0 = {</div><div class='add'>+	.name = "SN0",</div><div class='add'>+	.keepalive = true,</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_gemnoc_sf },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn2 = {</div><div class='add'>+	.name = "SN2",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_aggre1_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn3 = {</div><div class='add'>+	.name = "SN3",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_aggre2_noc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sn4 = {</div><div class='add'>+	.name = "SN4",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_usb_anoc },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_acv_disp = {</div><div class='add'>+	.name = "ACV",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mc0_disp = {</div><div class='add'>+	.name = "MC0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm0_disp = {</div><div class='add'>+	.name = "MM0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_mem_noc_hf_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mm1_disp = {</div><div class='add'>+	.name = "MM1",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_mdp_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh0_disp = {</div><div class='add'>+	.name = "SH0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_llcc_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh1_disp = {</div><div class='add'>+	.name = "SH1",</div><div class='add'>+	.num_nodes = 2,</div><div class='add'>+	.nodes = { &amp;qnm_mnoc_hf_disp, &amp;qnm_pcie_disp },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_acv_pcie = {</div><div class='add'>+	.name = "ACV",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_mc0_pcie = {</div><div class='add'>+	.name = "MC0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;ebi_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_pc0_pcie = {</div><div class='add'>+	.name = "PC0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_pcie_mem_noc_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh0_pcie = {</div><div class='add'>+	.name = "SH0",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qns_llcc_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm bcm_sh1_pcie = {</div><div class='add'>+	.name = "SH1",</div><div class='add'>+	.num_nodes = 1,</div><div class='add'>+	.nodes = { &amp;qnm_pcie_pcie },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *aggre1_noc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const aggre1_noc_nodes[] = {</div><div class='add'>+	[MASTER_QSPI_0] = &amp;qhm_qspi,</div><div class='add'>+	[MASTER_QUP_1] = &amp;qhm_qup1,</div><div class='add'>+	[MASTER_SDCC_4] = &amp;xm_sdc4,</div><div class='add'>+	[MASTER_UFS_MEM] = &amp;xm_ufs_mem,</div><div class='add'>+	[SLAVE_A1NOC_SNOC] = &amp;qns_a1noc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_aggre1_noc = {</div><div class='add'>+	.nodes = aggre1_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),</div><div class='add'>+	.bcms = aggre1_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_ce0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const aggre2_noc_nodes[] = {</div><div class='add'>+	[MASTER_QUP_0] = &amp;qhm_qup0,</div><div class='add'>+	[MASTER_QUP_2] = &amp;qhm_qup2,</div><div class='add'>+	[MASTER_CRYPTO] = &amp;qxm_crypto,</div><div class='add'>+	[MASTER_SP] = &amp;qxm_sp,</div><div class='add'>+	[MASTER_QDSS_ETR] = &amp;xm_qdss_etr_0,</div><div class='add'>+	[MASTER_QDSS_ETR_1] = &amp;xm_qdss_etr_1,</div><div class='add'>+	[MASTER_SDCC_2] = &amp;xm_sdc2,</div><div class='add'>+	[SLAVE_A2NOC_SNOC] = &amp;qns_a2noc_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_aggre2_noc = {</div><div class='add'>+	.nodes = aggre2_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),</div><div class='add'>+	.bcms = aggre2_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const clk_virt_bcms[] = {</div><div class='add'>+	&amp;bcm_acv_perf,</div><div class='add'>+	&amp;bcm_qup0,</div><div class='add'>+	&amp;bcm_qup1,</div><div class='add'>+	&amp;bcm_qup2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const clk_virt_nodes[] = {</div><div class='add'>+	[MASTER_DDR_PERF_MODE] = &amp;ddr_perf_mode_master,</div><div class='add'>+	[MASTER_QUP_CORE_0] = &amp;qup0_core_master,</div><div class='add'>+	[MASTER_QUP_CORE_1] = &amp;qup1_core_master,</div><div class='add'>+	[MASTER_QUP_CORE_2] = &amp;qup2_core_master,</div><div class='add'>+	[SLAVE_DDR_PERF_MODE] = &amp;ddr_perf_mode_slave,</div><div class='add'>+	[SLAVE_QUP_CORE_0] = &amp;qup0_core_slave,</div><div class='add'>+	[SLAVE_QUP_CORE_1] = &amp;qup1_core_slave,</div><div class='add'>+	[SLAVE_QUP_CORE_2] = &amp;qup2_core_slave,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_clk_virt = {</div><div class='add'>+	.nodes = clk_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(clk_virt_nodes),</div><div class='add'>+	.bcms = clk_virt_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(clk_virt_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {</div><div class='add'>+	&amp;bcm_cn0,</div><div class='add'>+	&amp;bcm_cn1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const cnoc_cfg_nodes[] = {</div><div class='add'>+	[MASTER_CNOC_CFG] = &amp;qsm_cfg,</div><div class='add'>+	[SLAVE_AHB2PHY_SOUTH] = &amp;qhs_ahb2phy0,</div><div class='add'>+	[SLAVE_AHB2PHY_NORTH] = &amp;qhs_ahb2phy1,</div><div class='add'>+	[SLAVE_AHB2PHY_2] = &amp;qhs_ahb2phy2,</div><div class='add'>+	[SLAVE_AV1_ENC_CFG] = &amp;qhs_av1_enc_cfg,</div><div class='add'>+	[SLAVE_CAMERA_CFG] = &amp;qhs_camera_cfg,</div><div class='add'>+	[SLAVE_CLK_CTL] = &amp;qhs_clk_ctl,</div><div class='add'>+	[SLAVE_CRYPTO_0_CFG] = &amp;qhs_crypto0_cfg,</div><div class='add'>+	[SLAVE_DISPLAY_CFG] = &amp;qhs_display_cfg,</div><div class='add'>+	[SLAVE_GFX3D_CFG] = &amp;qhs_gpuss_cfg,</div><div class='add'>+	[SLAVE_IMEM_CFG] = &amp;qhs_imem_cfg,</div><div class='add'>+	[SLAVE_IPC_ROUTER_CFG] = &amp;qhs_ipc_router,</div><div class='add'>+	[SLAVE_PCIE_0_CFG] = &amp;qhs_pcie0_cfg,</div><div class='add'>+	[SLAVE_PCIE_1_CFG] = &amp;qhs_pcie1_cfg,</div><div class='add'>+	[SLAVE_PCIE_2_CFG] = &amp;qhs_pcie2_cfg,</div><div class='add'>+	[SLAVE_PCIE_3_CFG] = &amp;qhs_pcie3_cfg,</div><div class='add'>+	[SLAVE_PCIE_4_CFG] = &amp;qhs_pcie4_cfg,</div><div class='add'>+	[SLAVE_PCIE_5_CFG] = &amp;qhs_pcie5_cfg,</div><div class='add'>+	[SLAVE_PCIE_6A_CFG] = &amp;qhs_pcie6a_cfg,</div><div class='add'>+	[SLAVE_PCIE_6B_CFG] = &amp;qhs_pcie6b_cfg,</div><div class='add'>+	[SLAVE_PCIE_RSC_CFG] = &amp;qhs_pcie_rsc_cfg,</div><div class='add'>+	[SLAVE_PDM] = &amp;qhs_pdm,</div><div class='add'>+	[SLAVE_PRNG] = &amp;qhs_prng,</div><div class='add'>+	[SLAVE_QDSS_CFG] = &amp;qhs_qdss_cfg,</div><div class='add'>+	[SLAVE_QSPI_0] = &amp;qhs_qspi,</div><div class='add'>+	[SLAVE_QUP_0] = &amp;qhs_qup0,</div><div class='add'>+	[SLAVE_QUP_1] = &amp;qhs_qup1,</div><div class='add'>+	[SLAVE_QUP_2] = &amp;qhs_qup2,</div><div class='add'>+	[SLAVE_SDCC_2] = &amp;qhs_sdc2,</div><div class='add'>+	[SLAVE_SDCC_4] = &amp;qhs_sdc4,</div><div class='add'>+	[SLAVE_SMMUV3_CFG] = &amp;qhs_smmuv3_cfg,</div><div class='add'>+	[SLAVE_TCSR] = &amp;qhs_tcsr,</div><div class='add'>+	[SLAVE_TLMM] = &amp;qhs_tlmm,</div><div class='add'>+	[SLAVE_UFS_MEM_CFG] = &amp;qhs_ufs_mem_cfg,</div><div class='add'>+	[SLAVE_USB2] = &amp;qhs_usb2_0_cfg,</div><div class='add'>+	[SLAVE_USB3_0] = &amp;qhs_usb3_0_cfg,</div><div class='add'>+	[SLAVE_USB3_1] = &amp;qhs_usb3_1_cfg,</div><div class='add'>+	[SLAVE_USB3_2] = &amp;qhs_usb3_2_cfg,</div><div class='add'>+	[SLAVE_USB3_MP] = &amp;qhs_usb3_mp_cfg,</div><div class='add'>+	[SLAVE_USB4_0] = &amp;qhs_usb4_0_cfg,</div><div class='add'>+	[SLAVE_USB4_1] = &amp;qhs_usb4_1_cfg,</div><div class='add'>+	[SLAVE_USB4_2] = &amp;qhs_usb4_2_cfg,</div><div class='add'>+	[SLAVE_VENUS_CFG] = &amp;qhs_venus_cfg,</div><div class='add'>+	[SLAVE_LPASS_QTB_CFG] = &amp;qss_lpass_qtb_cfg,</div><div class='add'>+	[SLAVE_CNOC_MNOC_CFG] = &amp;qss_mnoc_cfg,</div><div class='add'>+	[SLAVE_NSP_QTB_CFG] = &amp;qss_nsp_qtb_cfg,</div><div class='add'>+	[SLAVE_QDSS_STM] = &amp;xs_qdss_stm,</div><div class='add'>+	[SLAVE_TCU] = &amp;xs_sys_tcu_cfg,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_cnoc_cfg = {</div><div class='add'>+	.nodes = cnoc_cfg_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),</div><div class='add'>+	.bcms = cnoc_cfg_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {</div><div class='add'>+	&amp;bcm_cn0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const cnoc_main_nodes[] = {</div><div class='add'>+	[MASTER_GEM_NOC_CNOC] = &amp;qnm_gemnoc_cnoc,</div><div class='add'>+	[MASTER_GEM_NOC_PCIE_SNOC] = &amp;qnm_gemnoc_pcie,</div><div class='add'>+	[SLAVE_AOSS] = &amp;qhs_aoss,</div><div class='add'>+	[SLAVE_TME_CFG] = &amp;qhs_tme_cfg,</div><div class='add'>+	[SLAVE_APPSS] = &amp;qns_apss,</div><div class='add'>+	[SLAVE_CNOC_CFG] = &amp;qss_cfg,</div><div class='add'>+	[SLAVE_BOOT_IMEM] = &amp;qxs_boot_imem,</div><div class='add'>+	[SLAVE_IMEM] = &amp;qxs_imem,</div><div class='add'>+	[SLAVE_PCIE_0] = &amp;xs_pcie_0,</div><div class='add'>+	[SLAVE_PCIE_1] = &amp;xs_pcie_1,</div><div class='add'>+	[SLAVE_PCIE_2] = &amp;xs_pcie_2,</div><div class='add'>+	[SLAVE_PCIE_3] = &amp;xs_pcie_3,</div><div class='add'>+	[SLAVE_PCIE_4] = &amp;xs_pcie_4,</div><div class='add'>+	[SLAVE_PCIE_5] = &amp;xs_pcie_5,</div><div class='add'>+	[SLAVE_PCIE_6A] = &amp;xs_pcie_6a,</div><div class='add'>+	[SLAVE_PCIE_6B] = &amp;xs_pcie_6b,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_cnoc_main = {</div><div class='add'>+	.nodes = cnoc_main_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(cnoc_main_nodes),</div><div class='add'>+	.bcms = cnoc_main_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(cnoc_main_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const gem_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_sh0,</div><div class='add'>+	&amp;bcm_sh1,</div><div class='add'>+	&amp;bcm_sh0_disp,</div><div class='add'>+	&amp;bcm_sh1_disp,</div><div class='add'>+	&amp;bcm_sh0_pcie,</div><div class='add'>+	&amp;bcm_sh1_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const gem_noc_nodes[] = {</div><div class='add'>+	[MASTER_GPU_TCU] = &amp;alm_gpu_tcu,</div><div class='add'>+	[MASTER_PCIE_TCU] = &amp;alm_pcie_tcu,</div><div class='add'>+	[MASTER_SYS_TCU] = &amp;alm_sys_tcu,</div><div class='add'>+	[MASTER_APPSS_PROC] = &amp;chm_apps,</div><div class='add'>+	[MASTER_GFX3D] = &amp;qnm_gpu,</div><div class='add'>+	[MASTER_LPASS_GEM_NOC] = &amp;qnm_lpass,</div><div class='add'>+	[MASTER_MNOC_HF_MEM_NOC] = &amp;qnm_mnoc_hf,</div><div class='add'>+	[MASTER_MNOC_SF_MEM_NOC] = &amp;qnm_mnoc_sf,</div><div class='add'>+	[MASTER_COMPUTE_NOC] = &amp;qnm_nsp_noc,</div><div class='add'>+	[MASTER_ANOC_PCIE_GEM_NOC] = &amp;qnm_pcie,</div><div class='add'>+	[MASTER_SNOC_SF_MEM_NOC] = &amp;qnm_snoc_sf,</div><div class='add'>+	[MASTER_GIC2] = &amp;xm_gic,</div><div class='add'>+	[SLAVE_GEM_NOC_CNOC] = &amp;qns_gem_noc_cnoc,</div><div class='add'>+	[SLAVE_LLCC] = &amp;qns_llcc,</div><div class='add'>+	[SLAVE_MEM_NOC_PCIE_SNOC] = &amp;qns_pcie,</div><div class='add'>+	[MASTER_MNOC_HF_MEM_NOC_DISP] = &amp;qnm_mnoc_hf_disp,</div><div class='add'>+	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &amp;qnm_pcie_disp,</div><div class='add'>+	[SLAVE_LLCC_DISP] = &amp;qns_llcc_disp,</div><div class='add'>+	[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &amp;qnm_pcie_pcie,</div><div class='add'>+	[SLAVE_LLCC_PCIE] = &amp;qns_llcc_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_gem_noc = {</div><div class='add'>+	.nodes = gem_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(gem_noc_nodes),</div><div class='add'>+	.bcms = gem_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(gem_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPIAON_NOC] = &amp;qnm_lpiaon_noc,</div><div class='add'>+	[SLAVE_LPASS_GEM_NOC] = &amp;qns_lpass_ag_noc_gemnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_lpass_ag_noc = {</div><div class='add'>+	.nodes = lpass_ag_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),</div><div class='add'>+	.bcms = lpass_ag_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_lp0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPASS_LPINOC] = &amp;qnm_lpass_lpinoc,</div><div class='add'>+	[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &amp;qns_lpass_aggnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_lpass_lpiaon_noc = {</div><div class='add'>+	.nodes = lpass_lpiaon_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),</div><div class='add'>+	.bcms = lpass_lpiaon_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {</div><div class='add'>+	[MASTER_LPASS_PROC] = &amp;qxm_lpinoc_dsp_axim,</div><div class='add'>+	[SLAVE_LPICX_NOC_LPIAON_NOC] = &amp;qns_lpi_aon_noc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {</div><div class='add'>+	.nodes = lpass_lpicx_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),</div><div class='add'>+	.bcms = lpass_lpicx_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const mc_virt_bcms[] = {</div><div class='add'>+	&amp;bcm_acv,</div><div class='add'>+	&amp;bcm_mc0,</div><div class='add'>+	&amp;bcm_acv_disp,</div><div class='add'>+	&amp;bcm_mc0_disp,</div><div class='add'>+	&amp;bcm_acv_pcie,</div><div class='add'>+	&amp;bcm_mc0_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const mc_virt_nodes[] = {</div><div class='add'>+	[MASTER_LLCC] = &amp;llcc_mc,</div><div class='add'>+	[SLAVE_EBI1] = &amp;ebi,</div><div class='add'>+	[MASTER_LLCC_DISP] = &amp;llcc_mc_disp,</div><div class='add'>+	[SLAVE_EBI1_DISP] = &amp;ebi_disp,</div><div class='add'>+	[MASTER_LLCC_PCIE] = &amp;llcc_mc_pcie,</div><div class='add'>+	[SLAVE_EBI1_PCIE] = &amp;ebi_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_mc_virt = {</div><div class='add'>+	.nodes = mc_virt_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mc_virt_nodes),</div><div class='add'>+	.bcms = mc_virt_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(mc_virt_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_mm0,</div><div class='add'>+	&amp;bcm_mm1,</div><div class='add'>+	&amp;bcm_mm0_disp,</div><div class='add'>+	&amp;bcm_mm1_disp,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const mmss_noc_nodes[] = {</div><div class='add'>+	[MASTER_AV1_ENC] = &amp;qnm_av1_enc,</div><div class='add'>+	[MASTER_CAMNOC_HF] = &amp;qnm_camnoc_hf,</div><div class='add'>+	[MASTER_CAMNOC_ICP] = &amp;qnm_camnoc_icp,</div><div class='add'>+	[MASTER_CAMNOC_SF] = &amp;qnm_camnoc_sf,</div><div class='add'>+	[MASTER_EVA] = &amp;qnm_eva,</div><div class='add'>+	[MASTER_MDP] = &amp;qnm_mdp,</div><div class='add'>+	[MASTER_VIDEO] = &amp;qnm_video,</div><div class='add'>+	[MASTER_VIDEO_CV_PROC] = &amp;qnm_video_cv_cpu,</div><div class='add'>+	[MASTER_VIDEO_V_PROC] = &amp;qnm_video_v_cpu,</div><div class='add'>+	[MASTER_CNOC_MNOC_CFG] = &amp;qsm_mnoc_cfg,</div><div class='add'>+	[SLAVE_MNOC_HF_MEM_NOC] = &amp;qns_mem_noc_hf,</div><div class='add'>+	[SLAVE_MNOC_SF_MEM_NOC] = &amp;qns_mem_noc_sf,</div><div class='add'>+	[SLAVE_SERVICE_MNOC] = &amp;srvc_mnoc,</div><div class='add'>+	[MASTER_MDP_DISP] = &amp;qnm_mdp_disp,</div><div class='add'>+	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &amp;qns_mem_noc_hf_disp,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_mmss_noc = {</div><div class='add'>+	.nodes = mmss_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),</div><div class='add'>+	.bcms = mmss_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_co0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const nsp_noc_nodes[] = {</div><div class='add'>+	[MASTER_CDSP_PROC] = &amp;qxm_nsp,</div><div class='add'>+	[SLAVE_CDSP_MEM_NOC] = &amp;qns_nsp_gemnoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_nsp_noc = {</div><div class='add'>+	.nodes = nsp_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),</div><div class='add'>+	.bcms = nsp_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {</div><div class='add'>+	&amp;bcm_pc0,</div><div class='add'>+	&amp;bcm_pc0_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {</div><div class='add'>+	[MASTER_PCIE_NORTH] = &amp;qnm_pcie_north_gem_noc,</div><div class='add'>+	[MASTER_PCIE_SOUTH] = &amp;qnm_pcie_south_gem_noc,</div><div class='add'>+	[SLAVE_ANOC_PCIE_GEM_NOC] = &amp;qns_pcie_mem_noc,</div><div class='add'>+	[MASTER_PCIE_NORTH_PCIE] = &amp;qnm_pcie_north_gem_noc_pcie,</div><div class='add'>+	[MASTER_PCIE_SOUTH_PCIE] = &amp;qnm_pcie_south_gem_noc_pcie,</div><div class='add'>+	[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &amp;qns_pcie_mem_noc_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {</div><div class='add'>+	.nodes = pcie_center_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(pcie_center_anoc_nodes),</div><div class='add'>+	.bcms = pcie_center_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(pcie_center_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const pcie_north_anoc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {</div><div class='add'>+	[MASTER_PCIE_3] = &amp;xm_pcie_3,</div><div class='add'>+	[MASTER_PCIE_4] = &amp;xm_pcie_4,</div><div class='add'>+	[MASTER_PCIE_5] = &amp;xm_pcie_5,</div><div class='add'>+	[SLAVE_PCIE_NORTH] = &amp;qns_pcie_north_gem_noc,</div><div class='add'>+	[MASTER_PCIE_3_PCIE] = &amp;xm_pcie_3_pcie,</div><div class='add'>+	[MASTER_PCIE_4_PCIE] = &amp;xm_pcie_4_pcie,</div><div class='add'>+	[MASTER_PCIE_5_PCIE] = &amp;xm_pcie_5_pcie,</div><div class='add'>+	[SLAVE_PCIE_NORTH_PCIE] = &amp;qns_pcie_north_gem_noc_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {</div><div class='add'>+	.nodes = pcie_north_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(pcie_north_anoc_nodes),</div><div class='add'>+	.bcms = pcie_north_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {</div><div class='add'>+	[MASTER_PCIE_0] = &amp;xm_pcie_0,</div><div class='add'>+	[MASTER_PCIE_1] = &amp;xm_pcie_1,</div><div class='add'>+	[MASTER_PCIE_2] = &amp;xm_pcie_2,</div><div class='add'>+	[MASTER_PCIE_6A] = &amp;xm_pcie_6a,</div><div class='add'>+	[MASTER_PCIE_6B] = &amp;xm_pcie_6b,</div><div class='add'>+	[SLAVE_PCIE_SOUTH] = &amp;qns_pcie_south_gem_noc,</div><div class='add'>+	[MASTER_PCIE_0_PCIE] = &amp;xm_pcie_0_pcie,</div><div class='add'>+	[MASTER_PCIE_1_PCIE] = &amp;xm_pcie_1_pcie,</div><div class='add'>+	[MASTER_PCIE_2_PCIE] = &amp;xm_pcie_2_pcie,</div><div class='add'>+	[MASTER_PCIE_6A_PCIE] = &amp;xm_pcie_6a_pcie,</div><div class='add'>+	[MASTER_PCIE_6B_PCIE] = &amp;xm_pcie_6b_pcie,</div><div class='add'>+	[SLAVE_PCIE_SOUTH_PCIE] = &amp;qns_pcie_south_gem_noc_pcie,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {</div><div class='add'>+	.nodes = pcie_south_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(pcie_south_anoc_nodes),</div><div class='add'>+	.bcms = pcie_south_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *system_noc_bcms[] = {</div><div class='add'>+	&amp;bcm_sn0,</div><div class='add'>+	&amp;bcm_sn2,</div><div class='add'>+	&amp;bcm_sn3,</div><div class='add'>+	&amp;bcm_sn4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const system_noc_nodes[] = {</div><div class='add'>+	[MASTER_A1NOC_SNOC] = &amp;qnm_aggre1_noc,</div><div class='add'>+	[MASTER_A2NOC_SNOC] = &amp;qnm_aggre2_noc,</div><div class='add'>+	[MASTER_GIC1] = &amp;qnm_gic,</div><div class='add'>+	[MASTER_USB_NOC_SNOC] = &amp;qnm_usb_anoc,</div><div class='add'>+	[SLAVE_SNOC_GEM_NOC_SF] = &amp;qns_gemnoc_sf,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_system_noc = {</div><div class='add'>+	.nodes = system_noc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(system_noc_nodes),</div><div class='add'>+	.bcms = system_noc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(system_noc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm * const usb_center_anoc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const usb_center_anoc_nodes[] = {</div><div class='add'>+	[MASTER_AGGRE_USB_NORTH] = &amp;qnm_aggre_usb_north_snoc,</div><div class='add'>+	[MASTER_AGGRE_USB_SOUTH] = &amp;qnm_aggre_usb_south_snoc,</div><div class='add'>+	[SLAVE_USB_NOC_SNOC] = &amp;qns_aggre_usb_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_usb_center_anoc = {</div><div class='add'>+	.nodes = usb_center_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(usb_center_anoc_nodes),</div><div class='add'>+	.bcms = usb_center_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *usb_north_anoc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const usb_north_anoc_nodes[] = {</div><div class='add'>+	[MASTER_USB2] = &amp;xm_usb2_0,</div><div class='add'>+	[MASTER_USB3_MP] = &amp;xm_usb3_mp,</div><div class='add'>+	[SLAVE_AGGRE_USB_NORTH] = &amp;qns_aggre_usb_north_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_usb_north_anoc = {</div><div class='add'>+	.nodes = usb_north_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(usb_north_anoc_nodes),</div><div class='add'>+	.bcms = usb_north_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_bcm *usb_south_anoc_bcms[] = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct qcom_icc_node * const usb_south_anoc_nodes[] = {</div><div class='add'>+	[MASTER_USB3_0] = &amp;xm_usb3_0,</div><div class='add'>+	[MASTER_USB3_1] = &amp;xm_usb3_1,</div><div class='add'>+	[MASTER_USB3_2] = &amp;xm_usb3_2,</div><div class='add'>+	[MASTER_USB4_0] = &amp;xm_usb4_0,</div><div class='add'>+	[MASTER_USB4_1] = &amp;xm_usb4_1,</div><div class='add'>+	[MASTER_USB4_2] = &amp;xm_usb4_2,</div><div class='add'>+	[SLAVE_AGGRE_USB_SOUTH] = &amp;qns_aggre_usb_south_snoc,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct qcom_icc_desc x1e80100_usb_south_anoc = {</div><div class='add'>+	.nodes = usb_south_anoc_nodes,</div><div class='add'>+	.num_nodes = ARRAY_SIZE(usb_south_anoc_nodes),</div><div class='add'>+	.bcms = usb_south_anoc_bcms,</div><div class='add'>+	.num_bcms = ARRAY_SIZE(usb_south_anoc_bcms),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id qnoc_of_match[] = {</div><div class='add'>+	{ .compatible = "qcom,x1e80100-aggre1-noc", .data = &amp;x1e80100_aggre1_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-aggre2-noc", .data = &amp;x1e80100_aggre2_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-clk-virt", .data = &amp;x1e80100_clk_virt},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-cnoc-cfg", .data = &amp;x1e80100_cnoc_cfg},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-cnoc-main", .data = &amp;x1e80100_cnoc_main},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-gem-noc", .data = &amp;x1e80100_gem_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-lpass-ag-noc", .data = &amp;x1e80100_lpass_ag_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-lpass-lpiaon-noc", .data = &amp;x1e80100_lpass_lpiaon_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-lpass-lpicx-noc", .data = &amp;x1e80100_lpass_lpicx_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-mc-virt", .data = &amp;x1e80100_mc_virt},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-mmss-noc", .data = &amp;x1e80100_mmss_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-nsp-noc", .data = &amp;x1e80100_nsp_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-pcie-center-anoc", .data = &amp;x1e80100_pcie_center_anoc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-pcie-north-anoc", .data = &amp;x1e80100_pcie_north_anoc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-pcie-south-anoc", .data = &amp;x1e80100_pcie_south_anoc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-system-noc", .data = &amp;x1e80100_system_noc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-usb-center-anoc", .data = &amp;x1e80100_usb_center_anoc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-usb-north-anoc", .data = &amp;x1e80100_usb_north_anoc},</div><div class='add'>+	{ .compatible = "qcom,x1e80100-usb-south-anoc", .data = &amp;x1e80100_usb_south_anoc},</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, qnoc_of_match);</div><div class='add'>+</div><div class='add'>+static struct platform_driver qnoc_driver = {</div><div class='add'>+	.probe = qcom_icc_rpmh_probe,</div><div class='add'>+	.remove_new = qcom_icc_rpmh_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "qnoc-x1e80100",</div><div class='add'>+		.of_match_table = qnoc_of_match,</div><div class='add'>+		.sync_state = icc_sync_state,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int __init qnoc_driver_init(void)</div><div class='add'>+{</div><div class='add'>+	return platform_driver_register(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+core_initcall(qnoc_driver_init);</div><div class='add'>+</div><div class='add'>+static void __exit qnoc_driver_exit(void)</div><div class='add'>+{</div><div class='add'>+	platform_driver_unregister(&amp;qnoc_driver);</div><div class='add'>+}</div><div class='add'>+module_exit(qnoc_driver_exit);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("x1e80100 NoC driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/interconnect/qcom/x1e80100.h b/drivers/interconnect/qcom/x1e80100.h<br/>new file mode 100644<br/>index 000000000000..2e14264f4c2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/qcom/x1e80100.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/qcom/x1e80100.h</a></div><div class='hunk'>@@ -0,0 +1,192 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * X1E80100 interconnect IDs</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023, Linaro Limited</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H</div><div class='add'>+#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H</div><div class='add'>+</div><div class='add'>+#define X1E80100_MASTER_A1NOC_SNOC			0</div><div class='add'>+#define X1E80100_MASTER_A2NOC_SNOC			1</div><div class='add'>+#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC		2</div><div class='add'>+#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP		3</div><div class='add'>+#define X1E80100_MASTER_APPSS_PROC			4</div><div class='add'>+#define X1E80100_MASTER_CAMNOC_HF			5</div><div class='add'>+#define X1E80100_MASTER_CAMNOC_ICP			6</div><div class='add'>+#define X1E80100_MASTER_CAMNOC_SF			7</div><div class='add'>+#define X1E80100_MASTER_CDSP_PROC			8</div><div class='add'>+#define X1E80100_MASTER_CNOC_CFG			9</div><div class='add'>+#define X1E80100_MASTER_CNOC_MNOC_CFG			10</div><div class='add'>+#define X1E80100_MASTER_COMPUTE_NOC			11</div><div class='add'>+#define X1E80100_MASTER_CRYPTO				12</div><div class='add'>+#define X1E80100_MASTER_GEM_NOC_CNOC			13</div><div class='add'>+#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC		14</div><div class='add'>+#define X1E80100_MASTER_GFX3D				15</div><div class='add'>+#define X1E80100_MASTER_GPU_TCU				16</div><div class='add'>+#define X1E80100_MASTER_IPA				17</div><div class='add'>+#define X1E80100_MASTER_LLCC				18</div><div class='add'>+#define X1E80100_MASTER_LLCC_DISP			19</div><div class='add'>+#define X1E80100_MASTER_LPASS_GEM_NOC			20</div><div class='add'>+#define X1E80100_MASTER_LPASS_LPINOC			21</div><div class='add'>+#define X1E80100_MASTER_LPASS_PROC			22</div><div class='add'>+#define X1E80100_MASTER_LPIAON_NOC			23</div><div class='add'>+#define X1E80100_MASTER_MDP				24</div><div class='add'>+#define X1E80100_MASTER_MDP_DISP			25</div><div class='add'>+#define X1E80100_MASTER_MNOC_HF_MEM_NOC			26</div><div class='add'>+#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP		27</div><div class='add'>+#define X1E80100_MASTER_MNOC_SF_MEM_NOC			28</div><div class='add'>+#define X1E80100_MASTER_PCIE_0				29</div><div class='add'>+#define X1E80100_MASTER_PCIE_1				30</div><div class='add'>+#define X1E80100_MASTER_QDSS_ETR			31</div><div class='add'>+#define X1E80100_MASTER_QDSS_ETR_1			32</div><div class='add'>+#define X1E80100_MASTER_QSPI_0				33</div><div class='add'>+#define X1E80100_MASTER_QUP_0				34</div><div class='add'>+#define X1E80100_MASTER_QUP_1				35</div><div class='add'>+#define X1E80100_MASTER_QUP_2				36</div><div class='add'>+#define X1E80100_MASTER_QUP_CORE_0			37</div><div class='add'>+#define X1E80100_MASTER_QUP_CORE_1			38</div><div class='add'>+#define X1E80100_MASTER_SDCC_2				39</div><div class='add'>+#define X1E80100_MASTER_SDCC_4				40</div><div class='add'>+#define X1E80100_MASTER_SNOC_SF_MEM_NOC			41</div><div class='add'>+#define X1E80100_MASTER_SP				42</div><div class='add'>+#define X1E80100_MASTER_SYS_TCU				43</div><div class='add'>+#define X1E80100_MASTER_UFS_MEM				44</div><div class='add'>+#define X1E80100_MASTER_USB3_0				45</div><div class='add'>+#define X1E80100_MASTER_VIDEO				46</div><div class='add'>+#define X1E80100_MASTER_VIDEO_CV_PROC			47</div><div class='add'>+#define X1E80100_MASTER_VIDEO_V_PROC			48</div><div class='add'>+#define X1E80100_SLAVE_A1NOC_SNOC			49</div><div class='add'>+#define X1E80100_SLAVE_A2NOC_SNOC			50</div><div class='add'>+#define X1E80100_SLAVE_AHB2PHY_NORTH			51</div><div class='add'>+#define X1E80100_SLAVE_AHB2PHY_SOUTH			52</div><div class='add'>+#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC		53</div><div class='add'>+#define X1E80100_SLAVE_AOSS				54</div><div class='add'>+#define X1E80100_SLAVE_APPSS				55</div><div class='add'>+#define X1E80100_SLAVE_BOOT_IMEM			56</div><div class='add'>+#define X1E80100_SLAVE_CAMERA_CFG			57</div><div class='add'>+#define X1E80100_SLAVE_CDSP_MEM_NOC			58</div><div class='add'>+#define X1E80100_SLAVE_CLK_CTL				59</div><div class='add'>+#define X1E80100_SLAVE_CNOC_CFG				60</div><div class='add'>+#define X1E80100_SLAVE_CNOC_MNOC_CFG			61</div><div class='add'>+#define X1E80100_SLAVE_CRYPTO_0_CFG			62</div><div class='add'>+#define X1E80100_SLAVE_DISPLAY_CFG			63</div><div class='add'>+#define X1E80100_SLAVE_EBI1				64</div><div class='add'>+#define X1E80100_SLAVE_EBI1_DISP			65</div><div class='add'>+#define X1E80100_SLAVE_GEM_NOC_CNOC			66</div><div class='add'>+#define X1E80100_SLAVE_GFX3D_CFG			67</div><div class='add'>+#define X1E80100_SLAVE_IMEM				68</div><div class='add'>+#define X1E80100_SLAVE_IMEM_CFG				69</div><div class='add'>+#define X1E80100_SLAVE_IPC_ROUTER_CFG			70</div><div class='add'>+#define X1E80100_SLAVE_LLCC				71</div><div class='add'>+#define X1E80100_SLAVE_LLCC_DISP			72</div><div class='add'>+#define X1E80100_SLAVE_LPASS_GEM_NOC			73</div><div class='add'>+#define X1E80100_SLAVE_LPASS_QTB_CFG			74</div><div class='add'>+#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC		75</div><div class='add'>+#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC		76</div><div class='add'>+#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC		77</div><div class='add'>+#define X1E80100_SLAVE_MNOC_HF_MEM_NOC			78</div><div class='add'>+#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP		79</div><div class='add'>+#define X1E80100_SLAVE_MNOC_SF_MEM_NOC			80</div><div class='add'>+#define X1E80100_SLAVE_NSP_QTB_CFG			81</div><div class='add'>+#define X1E80100_SLAVE_PCIE_0				82</div><div class='add'>+#define X1E80100_SLAVE_PCIE_0_CFG			83</div><div class='add'>+#define X1E80100_SLAVE_PCIE_1				84</div><div class='add'>+#define X1E80100_SLAVE_PCIE_1_CFG			85</div><div class='add'>+#define X1E80100_SLAVE_PDM				86</div><div class='add'>+#define X1E80100_SLAVE_PRNG				87</div><div class='add'>+#define X1E80100_SLAVE_QDSS_CFG				88</div><div class='add'>+#define X1E80100_SLAVE_QDSS_STM				89</div><div class='add'>+#define X1E80100_SLAVE_QSPI_0				90</div><div class='add'>+#define X1E80100_SLAVE_QUP_1				91</div><div class='add'>+#define X1E80100_SLAVE_QUP_2				92</div><div class='add'>+#define X1E80100_SLAVE_QUP_CORE_0			93</div><div class='add'>+#define X1E80100_SLAVE_QUP_CORE_1			94</div><div class='add'>+#define X1E80100_SLAVE_QUP_CORE_2			95</div><div class='add'>+#define X1E80100_SLAVE_SDCC_2				96</div><div class='add'>+#define X1E80100_SLAVE_SDCC_4				97</div><div class='add'>+#define X1E80100_SLAVE_SERVICE_MNOC			98</div><div class='add'>+#define X1E80100_SLAVE_SNOC_GEM_NOC_SF			99</div><div class='add'>+#define X1E80100_SLAVE_TCSR				100</div><div class='add'>+#define X1E80100_SLAVE_TCU				101</div><div class='add'>+#define X1E80100_SLAVE_TLMM				102</div><div class='add'>+#define X1E80100_SLAVE_TME_CFG				103</div><div class='add'>+#define X1E80100_SLAVE_UFS_MEM_CFG			104</div><div class='add'>+#define X1E80100_SLAVE_USB3_0				105</div><div class='add'>+#define X1E80100_SLAVE_VENUS_CFG			106</div><div class='add'>+#define X1E80100_MASTER_DDR_PERF_MODE			107</div><div class='add'>+#define X1E80100_MASTER_QUP_CORE_2			108</div><div class='add'>+#define X1E80100_MASTER_PCIE_TCU			109</div><div class='add'>+#define X1E80100_MASTER_GIC2				110</div><div class='add'>+#define X1E80100_MASTER_AV1_ENC				111</div><div class='add'>+#define X1E80100_MASTER_EVA				112</div><div class='add'>+#define X1E80100_MASTER_PCIE_NORTH			113</div><div class='add'>+#define X1E80100_MASTER_PCIE_SOUTH			114</div><div class='add'>+#define X1E80100_MASTER_PCIE_3				115</div><div class='add'>+#define X1E80100_MASTER_PCIE_4				116</div><div class='add'>+#define X1E80100_MASTER_PCIE_5				117</div><div class='add'>+#define X1E80100_MASTER_PCIE_2				118</div><div class='add'>+#define X1E80100_MASTER_PCIE_6A				119</div><div class='add'>+#define X1E80100_MASTER_PCIE_6B				120</div><div class='add'>+#define X1E80100_MASTER_GIC1				121</div><div class='add'>+#define X1E80100_MASTER_USB_NOC_SNOC			122</div><div class='add'>+#define X1E80100_MASTER_AGGRE_USB_NORTH			123</div><div class='add'>+#define X1E80100_MASTER_AGGRE_USB_SOUTH			124</div><div class='add'>+#define X1E80100_MASTER_USB2				125</div><div class='add'>+#define X1E80100_MASTER_USB3_MP				126</div><div class='add'>+#define X1E80100_MASTER_USB3_1				127</div><div class='add'>+#define X1E80100_MASTER_USB3_2				128</div><div class='add'>+#define X1E80100_MASTER_USB4_0				129</div><div class='add'>+#define X1E80100_MASTER_USB4_1				130</div><div class='add'>+#define X1E80100_MASTER_USB4_2				131</div><div class='add'>+#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE		132</div><div class='add'>+#define X1E80100_MASTER_LLCC_PCIE			133</div><div class='add'>+#define X1E80100_MASTER_PCIE_NORTH_PCIE			134</div><div class='add'>+#define X1E80100_MASTER_PCIE_SOUTH_PCIE			135</div><div class='add'>+#define X1E80100_MASTER_PCIE_3_PCIE			136</div><div class='add'>+#define X1E80100_MASTER_PCIE_4_PCIE			137</div><div class='add'>+#define X1E80100_MASTER_PCIE_5_PCIE			138</div><div class='add'>+#define X1E80100_MASTER_PCIE_0_PCIE			139</div><div class='add'>+#define X1E80100_MASTER_PCIE_1_PCIE			140</div><div class='add'>+#define X1E80100_MASTER_PCIE_2_PCIE			141</div><div class='add'>+#define X1E80100_MASTER_PCIE_6A_PCIE			142</div><div class='add'>+#define X1E80100_MASTER_PCIE_6B_PCIE			143</div><div class='add'>+#define X1E80100_SLAVE_AHB2PHY_2			144</div><div class='add'>+#define X1E80100_SLAVE_AV1_ENC_CFG			145</div><div class='add'>+#define X1E80100_SLAVE_PCIE_2_CFG			146</div><div class='add'>+#define X1E80100_SLAVE_PCIE_3_CFG			147</div><div class='add'>+#define X1E80100_SLAVE_PCIE_4_CFG			148</div><div class='add'>+#define X1E80100_SLAVE_PCIE_5_CFG			149</div><div class='add'>+#define X1E80100_SLAVE_PCIE_6A_CFG			150</div><div class='add'>+#define X1E80100_SLAVE_PCIE_6B_CFG			151</div><div class='add'>+#define X1E80100_SLAVE_PCIE_RSC_CFG			152</div><div class='add'>+#define X1E80100_SLAVE_QUP_0				153</div><div class='add'>+#define X1E80100_SLAVE_SMMUV3_CFG			154</div><div class='add'>+#define X1E80100_SLAVE_USB2				155</div><div class='add'>+#define X1E80100_SLAVE_USB3_1				156</div><div class='add'>+#define X1E80100_SLAVE_USB3_2				157</div><div class='add'>+#define X1E80100_SLAVE_USB3_MP				158</div><div class='add'>+#define X1E80100_SLAVE_USB4_0				159</div><div class='add'>+#define X1E80100_SLAVE_USB4_1				160</div><div class='add'>+#define X1E80100_SLAVE_USB4_2				161</div><div class='add'>+#define X1E80100_SLAVE_PCIE_2				162</div><div class='add'>+#define X1E80100_SLAVE_PCIE_3				163</div><div class='add'>+#define X1E80100_SLAVE_PCIE_4				164</div><div class='add'>+#define X1E80100_SLAVE_PCIE_5				165</div><div class='add'>+#define X1E80100_SLAVE_PCIE_6A				166</div><div class='add'>+#define X1E80100_SLAVE_PCIE_6B				167</div><div class='add'>+#define X1E80100_SLAVE_DDR_PERF_MODE			168</div><div class='add'>+#define X1E80100_SLAVE_PCIE_NORTH			169</div><div class='add'>+#define X1E80100_SLAVE_PCIE_SOUTH			170</div><div class='add'>+#define X1E80100_SLAVE_USB_NOC_SNOC			171</div><div class='add'>+#define X1E80100_SLAVE_AGGRE_USB_NORTH			172</div><div class='add'>+#define X1E80100_SLAVE_AGGRE_USB_SOUTH			173</div><div class='add'>+#define X1E80100_SLAVE_LLCC_PCIE			174</div><div class='add'>+#define X1E80100_SLAVE_EBI1_PCIE			175</div><div class='add'>+#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE		176</div><div class='add'>+#define X1E80100_SLAVE_PCIE_NORTH_PCIE			177</div><div class='add'>+#define X1E80100_SLAVE_PCIE_SOUTH_PCIE			178</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/interconnect/samsung/exynos.c b/drivers/interconnect/samsung/exynos.c<br/>index ebf09bbf725b..1ba14cb45d5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/interconnect/samsung/exynos.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/interconnect/samsung/exynos.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/interconnect/samsung/exynos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/interconnect/samsung/exynos.c</a></div><div class='hunk'>@@ -93,14 +93,12 @@ static struct icc_node *exynos_generic_icc_xlate(struct of_phandle_args *spec,</div><div class='ctx'> 	return priv-&gt;node;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_generic_icc_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_generic_icc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos_icc_priv *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	icc_provider_deregister(&amp;priv-&gt;provider);</div><div class='ctx'> 	icc_nodes_remove(&amp;priv-&gt;provider);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int exynos_generic_icc_probe(struct platform_device *pdev)</div><div class='hunk'>@@ -182,7 +180,7 @@ static struct platform_driver exynos_generic_icc_driver = {</div><div class='ctx'> 		.sync_state = icc_sync_state,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = exynos_generic_icc_probe,</div><div class='del'>-	.remove = exynos_generic_icc_remove,</div><div class='add'>+	.remove_new = exynos_generic_icc_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(exynos_generic_icc_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig<br/>index 7673bb82945b..9a29d742617e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/Kconfig</a></div><div class='hunk'>@@ -160,6 +160,7 @@ config IOMMU_DMA</div><div class='ctx'> </div><div class='ctx'> # Shared Virtual Addressing</div><div class='ctx'> config IOMMU_SVA</div><div class='add'>+	select IOMMU_MM_DATA</div><div class='ctx'> 	bool</div><div class='ctx'> </div><div class='ctx'> config FSL_PAMU</div><div class='head'>diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h<br/>index 86be1edd50ee..8b3601f285fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/amd_iommu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/amd_iommu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/amd_iommu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/amd_iommu.h</a></div><div class='hunk'>@@ -53,10 +53,16 @@ int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev);</div><div class='ctx'> void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev);</div><div class='ctx'> </div><div class='ctx'> int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);</div><div class='add'>+/*</div><div class='add'>+ * This function flushes all internal caches of</div><div class='add'>+ * the IOMMU used by this driver.</div><div class='add'>+ */</div><div class='add'>+void amd_iommu_flush_all_caches(struct amd_iommu *iommu);</div><div class='ctx'> void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);</div><div class='ctx'> void amd_iommu_domain_update(struct protection_domain *domain);</div><div class='ctx'> void amd_iommu_domain_flush_complete(struct protection_domain *domain);</div><div class='del'>-void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);</div><div class='add'>+void amd_iommu_domain_flush_pages(struct protection_domain *domain,</div><div class='add'>+				  u64 address, size_t size);</div><div class='ctx'> int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);</div><div class='ctx'> int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,</div><div class='ctx'> 			      unsigned long cr3);</div><div class='head'>diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h<br/>index 90b7d7950a9e..809d74faa1a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/amd_iommu_types.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/amd_iommu_types.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/amd_iommu_types.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/amd_iommu_types.h</a></div><div class='hunk'>@@ -902,12 +902,6 @@ extern int amd_iommu_max_glx_val;</div><div class='ctx'> extern u64 amd_iommu_efr;</div><div class='ctx'> extern u64 amd_iommu_efr2;</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * This function flushes all internal caches of</div><div class='del'>- * the IOMMU used by this driver.</div><div class='del'>- */</div><div class='del'>-void iommu_flush_all_caches(struct amd_iommu *iommu);</div><div class='del'>-</div><div class='ctx'> static inline int get_ioapic_devid(int id)</div><div class='ctx'> {</div><div class='ctx'> 	struct devid_map *entry;</div><div class='head'>diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c<br/>index 64bcf3df37ee..c83bd0c2a1c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/init.c</a></div><div class='hunk'>@@ -2223,7 +2223,7 @@ static int __init amd_iommu_init_pci(void)</div><div class='ctx'> 		init_device_table_dma(pci_seg);</div><div class='ctx'> </div><div class='ctx'> 	for_each_iommu(iommu)</div><div class='del'>-		iommu_flush_all_caches(iommu);</div><div class='add'>+		amd_iommu_flush_all_caches(iommu);</div><div class='ctx'> </div><div class='ctx'> 	print_iommu_info();</div><div class='ctx'> </div><div class='hunk'>@@ -2773,7 +2773,7 @@ static void early_enable_iommu(struct amd_iommu *iommu)</div><div class='ctx'> 	iommu_enable_xt(iommu);</div><div class='ctx'> 	iommu_enable_irtcachedis(iommu);</div><div class='ctx'> 	iommu_enable(iommu);</div><div class='del'>-	iommu_flush_all_caches(iommu);</div><div class='add'>+	amd_iommu_flush_all_caches(iommu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -2829,7 +2829,7 @@ static void early_enable_iommus(void)</div><div class='ctx'> 			iommu_enable_xt(iommu);</div><div class='ctx'> 			iommu_enable_irtcachedis(iommu);</div><div class='ctx'> 			iommu_set_device_table(iommu);</div><div class='del'>-			iommu_flush_all_caches(iommu);</div><div class='add'>+			amd_iommu_flush_all_caches(iommu);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -3293,7 +3293,7 @@ static int __init state_next(void)</div><div class='ctx'> 				uninit_device_table_dma(pci_seg);</div><div class='ctx'> </div><div class='ctx'> 			for_each_iommu(iommu)</div><div class='del'>-				iommu_flush_all_caches(iommu);</div><div class='add'>+				amd_iommu_flush_all_caches(iommu);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c<br/>index 6c0621f6f572..2a0d1e97e52f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/io_pgtable.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/io_pgtable.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/io_pgtable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/io_pgtable.c</a></div><div class='hunk'>@@ -369,6 +369,8 @@ static int iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long iova,</div><div class='ctx'> 	bool updated = false;</div><div class='ctx'> 	u64 __pte, *pte;</div><div class='ctx'> 	int ret, i, count;</div><div class='add'>+	size_t size = pgcount &lt;&lt; __ffs(pgsize);</div><div class='add'>+	unsigned long o_iova = iova;</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(!IS_ALIGNED(iova, pgsize));</div><div class='ctx'> 	BUG_ON(!IS_ALIGNED(paddr, pgsize));</div><div class='hunk'>@@ -424,8 +426,7 @@ out:</div><div class='ctx'> 		 * Updates and flushing already happened in</div><div class='ctx'> 		 * increase_address_space().</div><div class='ctx'> 		 */</div><div class='del'>-		amd_iommu_domain_flush_tlb_pde(dom);</div><div class='del'>-		amd_iommu_domain_flush_complete(dom);</div><div class='add'>+		amd_iommu_domain_flush_pages(dom, o_iova, size);</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;dom-&gt;lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtable_v2.c<br/>index f818a7e254d4..6d69ba60744f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/io_pgtable_v2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/io_pgtable_v2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/io_pgtable_v2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/io_pgtable_v2.c</a></div><div class='hunk'>@@ -244,7 +244,6 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova,</div><div class='ctx'> 	unsigned long mapped_size = 0;</div><div class='ctx'> 	unsigned long o_iova = iova;</div><div class='ctx'> 	size_t size = pgcount &lt;&lt; __ffs(pgsize);</div><div class='del'>-	int count = 0;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	bool updated = false;</div><div class='ctx'> </div><div class='hunk'>@@ -265,19 +264,14 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova,</div><div class='ctx'> </div><div class='ctx'> 		*pte = set_pte_attr(paddr, map_size, prot);</div><div class='ctx'> </div><div class='del'>-		count++;</div><div class='ctx'> 		iova += map_size;</div><div class='ctx'> 		paddr += map_size;</div><div class='ctx'> 		mapped_size += map_size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	if (updated) {</div><div class='del'>-		if (count &gt; 1)</div><div class='del'>-			amd_iommu_flush_tlb(&amp;pdom-&gt;domain, 0);</div><div class='del'>-		else</div><div class='del'>-			amd_iommu_flush_page(&amp;pdom-&gt;domain, 0, o_iova);</div><div class='del'>-	}</div><div class='add'>+	if (updated)</div><div class='add'>+		amd_iommu_domain_flush_pages(pdom, o_iova, size);</div><div class='ctx'> </div><div class='ctx'> 	if (mapped)</div><div class='ctx'> 		*mapped += mapped_size;</div><div class='head'>diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c<br/>index fcc987f5d4ed..4283dd8191f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/amd/iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/amd/iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/amd/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/amd/iommu.c</a></div><div class='hunk'>@@ -64,7 +64,7 @@ LIST_HEAD(hpet_map);</div><div class='ctx'> LIST_HEAD(acpihid_map);</div><div class='ctx'> </div><div class='ctx'> const struct iommu_ops amd_iommu_ops;</div><div class='del'>-const struct iommu_dirty_ops amd_dirty_ops;</div><div class='add'>+static const struct iommu_dirty_ops amd_dirty_ops;</div><div class='ctx'> </div><div class='ctx'> int amd_iommu_max_glx_val = -1;</div><div class='ctx'> </div><div class='hunk'>@@ -85,6 +85,11 @@ static void detach_device(struct device *dev);</div><div class='ctx'>  *</div><div class='ctx'>  ****************************************************************************/</div><div class='ctx'> </div><div class='add'>+static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom)</div><div class='add'>+{</div><div class='add'>+	return (pdom &amp;&amp; (pdom-&gt;flags &amp; PD_IOMMUV2_MASK));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline int get_acpihid_device_id(struct device *dev,</div><div class='ctx'> 					struct acpihid_map_entry **entry)</div><div class='ctx'> {</div><div class='hunk'>@@ -551,8 +556,6 @@ static void amd_iommu_uninit_device(struct device *dev)</div><div class='ctx'> 	if (dev_data-&gt;domain)</div><div class='ctx'> 		detach_device(dev);</div><div class='ctx'> </div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We keep dev_data around for unplugged devices and reuse it when the</div><div class='ctx'> 	 * device is re-plugged - not doing so would introduce a ton of races.</div><div class='hunk'>@@ -1124,68 +1127,44 @@ static inline u64 build_inv_address(u64 address, size_t size)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,</div><div class='del'>-				  size_t size, u16 domid, int pde)</div><div class='add'>+				  size_t size, u16 domid,</div><div class='add'>+				  ioasid_t pasid, bool gn)</div><div class='ctx'> {</div><div class='ctx'> 	u64 inv_address = build_inv_address(address, size);</div><div class='ctx'> </div><div class='ctx'> 	memset(cmd, 0, sizeof(*cmd));</div><div class='add'>+</div><div class='ctx'> 	cmd-&gt;data[1] |= domid;</div><div class='ctx'> 	cmd-&gt;data[2]  = lower_32_bits(inv_address);</div><div class='ctx'> 	cmd-&gt;data[3]  = upper_32_bits(inv_address);</div><div class='add'>+	/* PDE bit - we want to flush everything, not only the PTEs */</div><div class='add'>+	cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;</div><div class='add'>+	if (gn) {</div><div class='add'>+		cmd-&gt;data[0] |= pasid;</div><div class='add'>+		cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;</div><div class='add'>+	}</div><div class='ctx'> 	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);</div><div class='del'>-	if (pde) /* PDE bit - we want to flush everything, not only the PTEs */</div><div class='del'>-		cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,</div><div class='del'>-				  u64 address, size_t size)</div><div class='add'>+				  u64 address, size_t size,</div><div class='add'>+				  ioasid_t pasid, bool gn)</div><div class='ctx'> {</div><div class='ctx'> 	u64 inv_address = build_inv_address(address, size);</div><div class='ctx'> </div><div class='ctx'> 	memset(cmd, 0, sizeof(*cmd));</div><div class='add'>+</div><div class='ctx'> 	cmd-&gt;data[0]  = devid;</div><div class='ctx'> 	cmd-&gt;data[0] |= (qdep &amp; 0xff) &lt;&lt; 24;</div><div class='ctx'> 	cmd-&gt;data[1]  = devid;</div><div class='ctx'> 	cmd-&gt;data[2]  = lower_32_bits(inv_address);</div><div class='ctx'> 	cmd-&gt;data[3]  = upper_32_bits(inv_address);</div><div class='del'>-	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,</div><div class='del'>-				  u64 address, bool size)</div><div class='del'>-{</div><div class='del'>-	memset(cmd, 0, sizeof(*cmd));</div><div class='del'>-</div><div class='del'>-	address &amp;= ~(0xfffULL);</div><div class='del'>-</div><div class='del'>-	cmd-&gt;data[0]  = pasid;</div><div class='del'>-	cmd-&gt;data[1]  = domid;</div><div class='del'>-	cmd-&gt;data[2]  = lower_32_bits(address);</div><div class='del'>-	cmd-&gt;data[3]  = upper_32_bits(address);</div><div class='del'>-	cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;</div><div class='del'>-	cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;</div><div class='del'>-	if (size)</div><div class='del'>-		cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;</div><div class='del'>-	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,</div><div class='del'>-				  int qdep, u64 address, bool size)</div><div class='del'>-{</div><div class='del'>-	memset(cmd, 0, sizeof(*cmd));</div><div class='del'>-</div><div class='del'>-	address &amp;= ~(0xfffULL);</div><div class='add'>+	if (gn) {</div><div class='add'>+		cmd-&gt;data[0] |= ((pasid &gt;&gt; 8) &amp; 0xff) &lt;&lt; 16;</div><div class='add'>+		cmd-&gt;data[1] |= (pasid &amp; 0xff) &lt;&lt; 16;</div><div class='add'>+		cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	cmd-&gt;data[0]  = devid;</div><div class='del'>-	cmd-&gt;data[0] |= ((pasid &gt;&gt; 8) &amp; 0xff) &lt;&lt; 16;</div><div class='del'>-	cmd-&gt;data[0] |= (qdep  &amp; 0xff) &lt;&lt; 24;</div><div class='del'>-	cmd-&gt;data[1]  = devid;</div><div class='del'>-	cmd-&gt;data[1] |= (pasid &amp; 0xff) &lt;&lt; 16;</div><div class='del'>-	cmd-&gt;data[2]  = lower_32_bits(address);</div><div class='del'>-	cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;</div><div class='del'>-	cmd-&gt;data[3]  = upper_32_bits(address);</div><div class='del'>-	if (size)</div><div class='del'>-		cmd-&gt;data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;</div><div class='ctx'> 	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1341,7 +1320,7 @@ static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)</div><div class='ctx'> 	for (dom_id = 0; dom_id &lt;= last_bdf; ++dom_id) {</div><div class='ctx'> 		struct iommu_cmd cmd;</div><div class='ctx'> 		build_inv_iommu_pages(&amp;cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,</div><div class='del'>-				      dom_id, 1);</div><div class='add'>+				      dom_id, IOMMU_NO_PASID, false);</div><div class='ctx'> 		iommu_queue_command(iommu, &amp;cmd);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1353,7 +1332,7 @@ static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)</div><div class='ctx'> 	struct iommu_cmd cmd;</div><div class='ctx'> </div><div class='ctx'> 	build_inv_iommu_pages(&amp;cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,</div><div class='del'>-			      dom_id, 1);</div><div class='add'>+			      dom_id, IOMMU_NO_PASID, false);</div><div class='ctx'> 	iommu_queue_command(iommu, &amp;cmd);</div><div class='ctx'> </div><div class='ctx'> 	iommu_completion_wait(iommu);</div><div class='hunk'>@@ -1392,7 +1371,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)</div><div class='ctx'> 	iommu_completion_wait(iommu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void iommu_flush_all_caches(struct amd_iommu *iommu)</div><div class='add'>+void amd_iommu_flush_all_caches(struct amd_iommu *iommu)</div><div class='ctx'> {</div><div class='ctx'> 	if (check_feature(FEATURE_IA)) {</div><div class='ctx'> 		amd_iommu_flush_all(iommu);</div><div class='hunk'>@@ -1406,8 +1385,8 @@ void iommu_flush_all_caches(struct amd_iommu *iommu)</div><div class='ctx'> /*</div><div class='ctx'>  * Command send function for flushing on-device TLB</div><div class='ctx'>  */</div><div class='del'>-static int device_flush_iotlb(struct iommu_dev_data *dev_data,</div><div class='del'>-			      u64 address, size_t size)</div><div class='add'>+static int device_flush_iotlb(struct iommu_dev_data *dev_data, u64 address,</div><div class='add'>+			      size_t size, ioasid_t pasid, bool gn)</div><div class='ctx'> {</div><div class='ctx'> 	struct amd_iommu *iommu;</div><div class='ctx'> 	struct iommu_cmd cmd;</div><div class='hunk'>@@ -1418,7 +1397,8 @@ static int device_flush_iotlb(struct iommu_dev_data *dev_data,</div><div class='ctx'> 	if (!iommu)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	build_inv_iotlb_pages(&amp;cmd, dev_data-&gt;devid, qdep, address, size);</div><div class='add'>+	build_inv_iotlb_pages(&amp;cmd, dev_data-&gt;devid, qdep, address,</div><div class='add'>+			      size, pasid, gn);</div><div class='ctx'> </div><div class='ctx'> 	return iommu_queue_command(iommu, &amp;cmd);</div><div class='ctx'> }</div><div class='hunk'>@@ -1464,8 +1444,11 @@ static int device_flush_dte(struct iommu_dev_data *dev_data)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dev_data-&gt;ats_enabled)</div><div class='del'>-		ret = device_flush_iotlb(dev_data, 0, ~0UL);</div><div class='add'>+	if (dev_data-&gt;ats_enabled) {</div><div class='add'>+		/* Invalidate the entire contents of an IOTLB */</div><div class='add'>+		ret = device_flush_iotlb(dev_data, 0, ~0UL,</div><div class='add'>+					 IOMMU_NO_PASID, false);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1476,13 +1459,18 @@ static int device_flush_dte(struct iommu_dev_data *dev_data)</div><div class='ctx'>  * page. Otherwise it flushes the whole TLB of the IOMMU.</div><div class='ctx'>  */</div><div class='ctx'> static void __domain_flush_pages(struct protection_domain *domain,</div><div class='del'>-				 u64 address, size_t size, int pde)</div><div class='add'>+				 u64 address, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_dev_data *dev_data;</div><div class='ctx'> 	struct iommu_cmd cmd;</div><div class='ctx'> 	int ret = 0, i;</div><div class='add'>+	ioasid_t pasid = IOMMU_NO_PASID;</div><div class='add'>+	bool gn = false;</div><div class='add'>+</div><div class='add'>+	if (pdom_is_v2_pgtbl_mode(domain))</div><div class='add'>+		gn = true;</div><div class='ctx'> </div><div class='del'>-	build_inv_iommu_pages(&amp;cmd, address, size, domain-&gt;id, pde);</div><div class='add'>+	build_inv_iommu_pages(&amp;cmd, address, size, domain-&gt;id, pasid, gn);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; amd_iommu_get_num_iommus(); ++i) {</div><div class='ctx'> 		if (!domain-&gt;dev_iommu[i])</div><div class='hunk'>@@ -1500,17 +1488,21 @@ static void __domain_flush_pages(struct protection_domain *domain,</div><div class='ctx'> 		if (!dev_data-&gt;ats_enabled)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		ret |= device_flush_iotlb(dev_data, address, size);</div><div class='add'>+		ret |= device_flush_iotlb(dev_data, address, size, pasid, gn);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	WARN_ON(ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void domain_flush_pages(struct protection_domain *domain,</div><div class='del'>-			       u64 address, size_t size, int pde)</div><div class='add'>+void amd_iommu_domain_flush_pages(struct protection_domain *domain,</div><div class='add'>+				  u64 address, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	if (likely(!amd_iommu_np_cache)) {</div><div class='del'>-		__domain_flush_pages(domain, address, size, pde);</div><div class='add'>+		__domain_flush_pages(domain, address, size);</div><div class='add'>+</div><div class='add'>+		/* Wait until IOMMU TLB and all device IOTLB flushes are complete */</div><div class='add'>+		amd_iommu_domain_flush_complete(domain);</div><div class='add'>+</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1543,16 +1535,20 @@ static void domain_flush_pages(struct protection_domain *domain,</div><div class='ctx'> </div><div class='ctx'> 		flush_size = 1ul &lt;&lt; min_alignment;</div><div class='ctx'> </div><div class='del'>-		__domain_flush_pages(domain, address, flush_size, pde);</div><div class='add'>+		__domain_flush_pages(domain, address, flush_size);</div><div class='ctx'> 		address += flush_size;</div><div class='ctx'> 		size -= flush_size;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/* Wait until IOMMU TLB and all device IOTLB flushes are complete */</div><div class='add'>+	amd_iommu_domain_flush_complete(domain);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Flush the whole IO/TLB for a given protection domain - including PDE */</div><div class='del'>-void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)</div><div class='add'>+static void amd_iommu_domain_flush_all(struct protection_domain *domain)</div><div class='ctx'> {</div><div class='del'>-	domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);</div><div class='add'>+	amd_iommu_domain_flush_pages(domain, 0,</div><div class='add'>+				     CMD_INV_IOMMU_ALL_PAGES_ADDRESS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void amd_iommu_domain_flush_complete(struct protection_domain *domain)</div><div class='hunk'>@@ -1579,8 +1575,7 @@ static void domain_flush_np_cache(struct protection_domain *domain,</div><div class='ctx'> 		unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 		spin_lock_irqsave(&amp;domain-&gt;lock, flags);</div><div class='del'>-		domain_flush_pages(domain, iova, size, 1);</div><div class='del'>-		amd_iommu_domain_flush_complete(domain);</div><div class='add'>+		amd_iommu_domain_flush_pages(domain, iova, size);</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;domain-&gt;lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1858,11 +1853,8 @@ static void do_detach(struct iommu_dev_data *dev_data)</div><div class='ctx'> 	/* Flush the DTE entry */</div><div class='ctx'> 	device_flush_dte(dev_data);</div><div class='ctx'> </div><div class='del'>-	/* Flush IOTLB */</div><div class='del'>-	amd_iommu_domain_flush_tlb_pde(domain);</div><div class='del'>-</div><div class='del'>-	/* Wait for the flushes to finish */</div><div class='del'>-	amd_iommu_domain_flush_complete(domain);</div><div class='add'>+	/* Flush IOTLB and wait for the flushes to finish */</div><div class='add'>+	amd_iommu_domain_flush_all(domain);</div><div class='ctx'> </div><div class='ctx'> 	/* decrease reference counters - needs to happen after the flushes */</div><div class='ctx'> 	domain-&gt;dev_iommu[iommu-&gt;index] -= 1;</div><div class='hunk'>@@ -1896,15 +1888,6 @@ static int attach_device(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	do_attach(dev_data, domain);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * We might boot into a crash-kernel here. The crashed kernel</div><div class='del'>-	 * left the caches in the IOMMU dirty. So we have to flush</div><div class='del'>-	 * here to evict all dirty stuff.</div><div class='del'>-	 */</div><div class='del'>-	amd_iommu_domain_flush_tlb_pde(domain);</div><div class='del'>-</div><div class='del'>-	amd_iommu_domain_flush_complete(domain);</div><div class='del'>-</div><div class='ctx'> out:</div><div class='ctx'> 	spin_unlock(&amp;dev_data-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -2048,8 +2031,7 @@ void amd_iommu_domain_update(struct protection_domain *domain)</div><div class='ctx'> 	amd_iommu_update_and_flush_device_table(domain);</div><div class='ctx'> </div><div class='ctx'> 	/* Flush domain TLB(s) and wait for completion */</div><div class='del'>-	amd_iommu_domain_flush_tlb_pde(domain);</div><div class='del'>-	amd_iommu_domain_flush_complete(domain);</div><div class='add'>+	amd_iommu_domain_flush_all(domain);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*****************************************************************************</div><div class='hunk'>@@ -2482,10 +2464,9 @@ static int amd_iommu_set_dirty_tracking(struct iommu_domain *domain,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Flush IOTLB to mark IOPTE dirty on the next translation(s) */</div><div class='del'>-	if (domain_flush) {</div><div class='del'>-		amd_iommu_domain_flush_tlb_pde(pdomain);</div><div class='del'>-		amd_iommu_domain_flush_complete(pdomain);</div><div class='del'>-	}</div><div class='add'>+	if (domain_flush)</div><div class='add'>+		amd_iommu_domain_flush_all(pdomain);</div><div class='add'>+</div><div class='ctx'> 	pdomain-&gt;dirty_tracking = enable;</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;pdomain-&gt;lock, flags);</div><div class='ctx'> </div><div class='hunk'>@@ -2588,8 +2569,7 @@ static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;dom-&gt;lock, flags);</div><div class='del'>-	amd_iommu_domain_flush_tlb_pde(dom);</div><div class='del'>-	amd_iommu_domain_flush_complete(dom);</div><div class='add'>+	amd_iommu_domain_flush_all(dom);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;dom-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2600,8 +2580,8 @@ static void amd_iommu_iotlb_sync(struct iommu_domain *domain,</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;dom-&gt;lock, flags);</div><div class='del'>-	domain_flush_pages(dom, gather-&gt;start, gather-&gt;end - gather-&gt;start + 1, 1);</div><div class='del'>-	amd_iommu_domain_flush_complete(dom);</div><div class='add'>+	amd_iommu_domain_flush_pages(dom, gather-&gt;start,</div><div class='add'>+				     gather-&gt;end - gather-&gt;start + 1);</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;dom-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2635,7 +2615,7 @@ static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct iommu_dirty_ops amd_dirty_ops = {</div><div class='add'>+static const struct iommu_dirty_ops amd_dirty_ops = {</div><div class='ctx'> 	.set_dirty_tracking = amd_iommu_set_dirty_tracking,</div><div class='ctx'> 	.read_and_clear_dirty = amd_iommu_read_and_clear_dirty,</div><div class='ctx'> };</div><div class='hunk'>@@ -2666,7 +2646,7 @@ const struct iommu_ops amd_iommu_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __flush_pasid(struct protection_domain *domain, u32 pasid,</div><div class='del'>-			 u64 address, bool size)</div><div class='add'>+			 u64 address, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_dev_data *dev_data;</div><div class='ctx'> 	struct iommu_cmd cmd;</div><div class='hunk'>@@ -2675,7 +2655,7 @@ static int __flush_pasid(struct protection_domain *domain, u32 pasid,</div><div class='ctx'> 	if (!(domain-&gt;flags &amp; PD_IOMMUV2_MASK))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	build_inv_iommu_pasid(&amp;cmd, domain-&gt;id, pasid, address, size);</div><div class='add'>+	build_inv_iommu_pages(&amp;cmd, address, size, domain-&gt;id, pasid, true);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * IOMMU TLB needs to be flushed before Device TLB to</div><div class='hunk'>@@ -2709,8 +2689,8 @@ static int __flush_pasid(struct protection_domain *domain, u32 pasid,</div><div class='ctx'> 		iommu = rlookup_amd_iommu(dev_data-&gt;dev);</div><div class='ctx'> 		if (!iommu)</div><div class='ctx'> 			continue;</div><div class='del'>-		build_inv_iotlb_pasid(&amp;cmd, dev_data-&gt;devid, pasid,</div><div class='del'>-				      qdep, address, size);</div><div class='add'>+		build_inv_iotlb_pages(&amp;cmd, dev_data-&gt;devid, qdep,</div><div class='add'>+				      address, size, pasid, true);</div><div class='ctx'> </div><div class='ctx'> 		ret = iommu_queue_command(iommu, &amp;cmd);</div><div class='ctx'> 		if (ret != 0)</div><div class='hunk'>@@ -2730,7 +2710,7 @@ out:</div><div class='ctx'> static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,</div><div class='ctx'> 				  u64 address)</div><div class='ctx'> {</div><div class='del'>-	return __flush_pasid(domain, pasid, address, false);</div><div class='add'>+	return __flush_pasid(domain, pasid, address, PAGE_SIZE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,</div><div class='hunk'>@@ -2749,8 +2729,7 @@ int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,</div><div class='ctx'> </div><div class='ctx'> static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)</div><div class='ctx'> {</div><div class='del'>-	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,</div><div class='del'>-			     true);</div><div class='add'>+	return __flush_pasid(domain, pasid, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)</div><div class='hunk'>@@ -3111,8 +3090,8 @@ out:</div><div class='ctx'> 	return index;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,</div><div class='del'>-			  struct irte_ga *irte)</div><div class='add'>+static int __modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,</div><div class='add'>+			    struct irte_ga *irte)</div><div class='ctx'> {</div><div class='ctx'> 	struct irq_remap_table *table;</div><div class='ctx'> 	struct irte_ga *entry;</div><div class='hunk'>@@ -3139,6 +3118,18 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,</div><div class='ctx'> </div><div class='ctx'> 	raw_spin_unlock_irqrestore(&amp;table-&gt;lock, flags);</div><div class='ctx'> </div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,</div><div class='add'>+			  struct irte_ga *irte)</div><div class='add'>+{</div><div class='add'>+	bool ret;</div><div class='add'>+</div><div class='add'>+	ret = __modify_irte_ga(iommu, devid, index, irte);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	iommu_flush_irt_and_complete(iommu, devid);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3357,7 +3348,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data,</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;irq_2_irte.devid = devid;</div><div class='ctx'> 	data-&gt;irq_2_irte.index = index + sub_handle;</div><div class='del'>-	iommu-&gt;irte_ops-&gt;prepare(data-&gt;entry, apic-&gt;delivery_mode,</div><div class='add'>+	iommu-&gt;irte_ops-&gt;prepare(data-&gt;entry, APIC_DELIVERY_MODE_FIXED,</div><div class='ctx'> 				 apic-&gt;dest_mode_logical, irq_cfg-&gt;vector,</div><div class='ctx'> 				 irq_cfg-&gt;dest_apicid, devid);</div><div class='ctx'> </div><div class='hunk'>@@ -3634,7 +3625,7 @@ int amd_iommu_deactivate_guest_mode(void *data)</div><div class='ctx'> </div><div class='ctx'> 	entry-&gt;lo.fields_remap.valid       = valid;</div><div class='ctx'> 	entry-&gt;lo.fields_remap.dm          = apic-&gt;dest_mode_logical;</div><div class='del'>-	entry-&gt;lo.fields_remap.int_type    = apic-&gt;delivery_mode;</div><div class='add'>+	entry-&gt;lo.fields_remap.int_type    = APIC_DELIVERY_MODE_FIXED;</div><div class='ctx'> 	entry-&gt;hi.fields.vector            = cfg-&gt;vector;</div><div class='ctx'> 	entry-&gt;lo.fields_remap.destination =</div><div class='ctx'> 				APICID_TO_IRTE_DEST_LO(cfg-&gt;dest_apicid);</div><div class='hunk'>@@ -3822,8 +3813,8 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *data)</div><div class='ctx'> 	}</div><div class='ctx'> 	entry-&gt;lo.fields_vapic.is_run = is_run;</div><div class='ctx'> </div><div class='del'>-	return modify_irte_ga(ir_data-&gt;iommu, ir_data-&gt;irq_2_irte.devid,</div><div class='del'>-			      ir_data-&gt;irq_2_irte.index, entry);</div><div class='add'>+	return __modify_irte_ga(ir_data-&gt;iommu, ir_data-&gt;irq_2_irte.devid,</div><div class='add'>+				ir_data-&gt;irq_2_irte.index, entry);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(amd_iommu_update_ga);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c<br/>index ee05f4824bfa..ef3ee95706da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/apple-dart.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/apple-dart.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/apple-dart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/apple-dart.c</a></div><div class='hunk'>@@ -81,6 +81,7 @@</div><div class='ctx'> #define DART_T8020_TCR_BYPASS_DAPF      BIT(12)</div><div class='ctx'> </div><div class='ctx'> #define DART_T8020_TTBR       0x200</div><div class='add'>+#define DART_T8020_USB4_TTBR  0x400</div><div class='ctx'> #define DART_T8020_TTBR_VALID BIT(31)</div><div class='ctx'> #define DART_T8020_TTBR_ADDR_FIELD_SHIFT 0</div><div class='ctx'> #define DART_T8020_TTBR_SHIFT 12</div><div class='hunk'>@@ -368,12 +369,14 @@ apple_dart_t8020_hw_stream_command(struct apple_dart_stream_map *stream_map,</div><div class='ctx'> 			     u32 command)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret, i;</div><div class='ctx'> 	u32 command_reg;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;stream_map-&gt;dart-&gt;lock, flags);</div><div class='ctx'> </div><div class='del'>-	writel(stream_map-&gt;sidmap[0], stream_map-&gt;dart-&gt;regs + DART_T8020_STREAM_SELECT);</div><div class='add'>+	for (i = 0; i &lt; BITS_TO_U32(stream_map-&gt;dart-&gt;num_streams); i++)</div><div class='add'>+		writel(stream_map-&gt;sidmap[i],</div><div class='add'>+		       stream_map-&gt;dart-&gt;regs + DART_T8020_STREAM_SELECT + 4 * i);</div><div class='ctx'> 	writel(command, stream_map-&gt;dart-&gt;regs + DART_T8020_STREAM_COMMAND);</div><div class='ctx'> </div><div class='ctx'> 	ret = readl_poll_timeout_atomic(</div><div class='hunk'>@@ -740,7 +743,6 @@ static void apple_dart_release_device(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev);</div><div class='ctx'> </div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 	kfree(cfg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -908,7 +910,7 @@ static struct iommu_group *apple_dart_device_group(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 		ret = apple_dart_merge_master_cfg(group_master_cfg, cfg);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			dev_err(dev, "Failed to merge DART IOMMU grups.\n");</div><div class='add'>+			dev_err(dev, "Failed to merge DART IOMMU groups.\n");</div><div class='ctx'> 			iommu_group_put(group);</div><div class='ctx'> 			res = ERR_PTR(ret);</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -1215,6 +1217,33 @@ static const struct apple_dart_hw apple_dart_hw_t8103 = {</div><div class='ctx'> 	.ttbr_shift = DART_T8020_TTBR_SHIFT,</div><div class='ctx'> 	.ttbr_count = 4,</div><div class='ctx'> };</div><div class='add'>+</div><div class='add'>+static const struct apple_dart_hw apple_dart_hw_t8103_usb4 = {</div><div class='add'>+	.type = DART_T8020,</div><div class='add'>+	.irq_handler = apple_dart_t8020_irq,</div><div class='add'>+	.invalidate_tlb = apple_dart_t8020_hw_invalidate_tlb,</div><div class='add'>+	.oas = 36,</div><div class='add'>+	.fmt = APPLE_DART,</div><div class='add'>+	.max_sid_count = 64,</div><div class='add'>+</div><div class='add'>+	.enable_streams = DART_T8020_STREAMS_ENABLE,</div><div class='add'>+	.lock = DART_T8020_CONFIG,</div><div class='add'>+	.lock_bit = DART_T8020_CONFIG_LOCK,</div><div class='add'>+</div><div class='add'>+	.error = DART_T8020_ERROR,</div><div class='add'>+</div><div class='add'>+	.tcr = DART_T8020_TCR,</div><div class='add'>+	.tcr_enabled = DART_T8020_TCR_TRANSLATE_ENABLE,</div><div class='add'>+	.tcr_disabled = 0,</div><div class='add'>+	.tcr_bypass = 0,</div><div class='add'>+</div><div class='add'>+	.ttbr = DART_T8020_USB4_TTBR,</div><div class='add'>+	.ttbr_valid = DART_T8020_TTBR_VALID,</div><div class='add'>+	.ttbr_addr_field_shift = DART_T8020_TTBR_ADDR_FIELD_SHIFT,</div><div class='add'>+	.ttbr_shift = DART_T8020_TTBR_SHIFT,</div><div class='add'>+	.ttbr_count = 4,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct apple_dart_hw apple_dart_hw_t6000 = {</div><div class='ctx'> 	.type = DART_T6000,</div><div class='ctx'> 	.irq_handler = apple_dart_t8020_irq,</div><div class='hunk'>@@ -1272,7 +1301,7 @@ static __maybe_unused int apple_dart_suspend(struct device *dev)</div><div class='ctx'> 	unsigned int sid, idx;</div><div class='ctx'> </div><div class='ctx'> 	for (sid = 0; sid &lt; dart-&gt;num_streams; sid++) {</div><div class='del'>-		dart-&gt;save_tcr[sid] = readl_relaxed(dart-&gt;regs + DART_TCR(dart, sid));</div><div class='add'>+		dart-&gt;save_tcr[sid] = readl(dart-&gt;regs + DART_TCR(dart, sid));</div><div class='ctx'> 		for (idx = 0; idx &lt; dart-&gt;hw-&gt;ttbr_count; idx++)</div><div class='ctx'> 			dart-&gt;save_ttbr[sid][idx] =</div><div class='ctx'> 				readl(dart-&gt;regs + DART_TTBR(dart, sid, idx));</div><div class='hunk'>@@ -1307,6 +1336,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(apple_dart_pm_ops, apple_dart_suspend, apple_dar</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id apple_dart_of_match[] = {</div><div class='ctx'> 	{ .compatible = "apple,t8103-dart", .data = &amp;apple_dart_hw_t8103 },</div><div class='add'>+	{ .compatible = "apple,t8103-usb4-dart", .data = &amp;apple_dart_hw_t8103_usb4 },</div><div class='ctx'> 	{ .compatible = "apple,t8110-dart", .data = &amp;apple_dart_hw_t8110 },</div><div class='ctx'> 	{ .compatible = "apple,t6000-dart", .data = &amp;apple_dart_hw_t6000 },</div><div class='ctx'> 	{},</div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c<br/>index 353248ab18e7..05722121f00e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c</a></div><div class='hunk'>@@ -246,7 +246,8 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn,</div><div class='ctx'> 						    smmu_domain);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	arm_smmu_atc_inv_domain(smmu_domain, mm-&gt;pasid, start, size);</div><div class='add'>+	arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), start,</div><div class='add'>+				size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)</div><div class='hunk'>@@ -264,10 +265,11 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)</div><div class='ctx'> 	 * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events,</div><div class='ctx'> 	 * but disable translation.</div><div class='ctx'> 	 */</div><div class='del'>-	arm_smmu_update_ctx_desc_devices(smmu_domain, mm-&gt;pasid, &amp;quiet_cd);</div><div class='add'>+	arm_smmu_update_ctx_desc_devices(smmu_domain, mm_get_enqcmd_pasid(mm),</div><div class='add'>+					 &amp;quiet_cd);</div><div class='ctx'> </div><div class='ctx'> 	arm_smmu_tlb_inv_asid(smmu_domain-&gt;smmu, smmu_mn-&gt;cd-&gt;asid);</div><div class='del'>-	arm_smmu_atc_inv_domain(smmu_domain, mm-&gt;pasid, 0, 0);</div><div class='add'>+	arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), 0, 0);</div><div class='ctx'> </div><div class='ctx'> 	smmu_mn-&gt;cleared = true;</div><div class='ctx'> 	mutex_unlock(&amp;sva_lock);</div><div class='hunk'>@@ -325,10 +327,13 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain,</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;smmu_domain-&gt;devices_lock, flags);</div><div class='ctx'> 	list_for_each_entry(master, &amp;smmu_domain-&gt;devices, domain_head) {</div><div class='del'>-		ret = arm_smmu_write_ctx_desc(master, mm-&gt;pasid, cd);</div><div class='add'>+		ret = arm_smmu_write_ctx_desc(master, mm_get_enqcmd_pasid(mm),</div><div class='add'>+					      cd);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			list_for_each_entry_from_reverse(master, &amp;smmu_domain-&gt;devices, domain_head)</div><div class='del'>-				arm_smmu_write_ctx_desc(master, mm-&gt;pasid, NULL);</div><div class='add'>+			list_for_each_entry_from_reverse(</div><div class='add'>+				master, &amp;smmu_domain-&gt;devices, domain_head)</div><div class='add'>+				arm_smmu_write_ctx_desc(</div><div class='add'>+					master, mm_get_enqcmd_pasid(mm), NULL);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -358,7 +363,8 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_mmu_notifier *smmu_mn)</div><div class='ctx'> </div><div class='ctx'> 	list_del(&amp;smmu_mn-&gt;list);</div><div class='ctx'> </div><div class='del'>-	arm_smmu_update_ctx_desc_devices(smmu_domain, mm-&gt;pasid, NULL);</div><div class='add'>+	arm_smmu_update_ctx_desc_devices(smmu_domain, mm_get_enqcmd_pasid(mm),</div><div class='add'>+					 NULL);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we went through clear(), we've already invalidated, and no</div><div class='hunk'>@@ -366,7 +372,8 @@ static void arm_smmu_mmu_notifier_put(struct arm_smmu_mmu_notifier *smmu_mn)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!smmu_mn-&gt;cleared) {</div><div class='ctx'> 		arm_smmu_tlb_inv_asid(smmu_domain-&gt;smmu, cd-&gt;asid);</div><div class='del'>-		arm_smmu_atc_inv_domain(smmu_domain, mm-&gt;pasid, 0, 0);</div><div class='add'>+		arm_smmu_atc_inv_domain(smmu_domain, mm_get_enqcmd_pasid(mm), 0,</div><div class='add'>+					0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Frees smmu_mn */</div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c<br/>index 7445454c2af2..0ffb1cf17e0b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c</a></div><div class='hunk'>@@ -1063,6 +1063,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,</div><div class='ctx'> 	bool cd_live;</div><div class='ctx'> 	__le64 *cdptr;</div><div class='ctx'> 	struct arm_smmu_ctx_desc_cfg *cd_table = &amp;master-&gt;cd_table;</div><div class='add'>+	struct arm_smmu_device *smmu = master-&gt;smmu;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(ssid &gt;= (1 &lt;&lt; cd_table-&gt;s1cdmax)))</div><div class='ctx'> 		return -E2BIG;</div><div class='hunk'>@@ -1077,6 +1078,8 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid,</div><div class='ctx'> 	if (!cd) { /* (5) */</div><div class='ctx'> 		val = 0;</div><div class='ctx'> 	} else if (cd == &amp;quiet_cd) { /* (4) */</div><div class='add'>+		if (!(smmu-&gt;features &amp; ARM_SMMU_FEAT_STALL_FORCE))</div><div class='add'>+			val &amp;= ~(CTXDESC_CD_0_S | CTXDESC_CD_0_R);</div><div class='ctx'> 		val |= CTXDESC_CD_0_TCR_EPD0;</div><div class='ctx'> 	} else if (cd_live) { /* (3) */</div><div class='ctx'> 		val &amp;= ~CTXDESC_CD_0_ASID;</div><div class='hunk'>@@ -1249,7 +1252,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='del'>-				      __le64 *dst)</div><div class='add'>+				      struct arm_smmu_ste *dst)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * This is hideously complicated, but we only really care about</div><div class='hunk'>@@ -1267,12 +1270,12 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 	 * 2. Write everything apart from dword 0, sync, write dword 0, sync</div><div class='ctx'> 	 * 3. Update Config, sync</div><div class='ctx'> 	 */</div><div class='del'>-	u64 val = le64_to_cpu(dst[0]);</div><div class='add'>+	u64 val = le64_to_cpu(dst-&gt;data[0]);</div><div class='ctx'> 	bool ste_live = false;</div><div class='del'>-	struct arm_smmu_device *smmu = NULL;</div><div class='add'>+	struct arm_smmu_device *smmu = master-&gt;smmu;</div><div class='ctx'> 	struct arm_smmu_ctx_desc_cfg *cd_table = NULL;</div><div class='ctx'> 	struct arm_smmu_s2_cfg *s2_cfg = NULL;</div><div class='del'>-	struct arm_smmu_domain *smmu_domain = NULL;</div><div class='add'>+	struct arm_smmu_domain *smmu_domain = master-&gt;domain;</div><div class='ctx'> 	struct arm_smmu_cmdq_ent prefetch_cmd = {</div><div class='ctx'> 		.opcode		= CMDQ_OP_PREFETCH_CFG,</div><div class='ctx'> 		.prefetch	= {</div><div class='hunk'>@@ -1280,18 +1283,12 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 		},</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	if (master) {</div><div class='del'>-		smmu_domain = master-&gt;domain;</div><div class='del'>-		smmu = master-&gt;smmu;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (smmu_domain) {</div><div class='ctx'> 		switch (smmu_domain-&gt;stage) {</div><div class='ctx'> 		case ARM_SMMU_DOMAIN_S1:</div><div class='ctx'> 			cd_table = &amp;master-&gt;cd_table;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case ARM_SMMU_DOMAIN_S2:</div><div class='del'>-		case ARM_SMMU_DOMAIN_NESTED:</div><div class='ctx'> 			s2_cfg = &amp;smmu_domain-&gt;s2_cfg;</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='hunk'>@@ -1325,10 +1322,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 		else</div><div class='ctx'> 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);</div><div class='ctx'> </div><div class='del'>-		dst[0] = cpu_to_le64(val);</div><div class='del'>-		dst[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,</div><div class='add'>+		dst-&gt;data[0] = cpu_to_le64(val);</div><div class='add'>+		dst-&gt;data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,</div><div class='ctx'> 						STRTAB_STE_1_SHCFG_INCOMING));</div><div class='del'>-		dst[2] = 0; /* Nuke the VMID */</div><div class='add'>+		dst-&gt;data[2] = 0; /* Nuke the VMID */</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The SMMU can perform negative caching, so we must sync</div><div class='ctx'> 		 * the STE regardless of whether the old value was live.</div><div class='hunk'>@@ -1343,7 +1340,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 			STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1;</div><div class='ctx'> </div><div class='ctx'> 		BUG_ON(ste_live);</div><div class='del'>-		dst[1] = cpu_to_le64(</div><div class='add'>+		dst-&gt;data[1] = cpu_to_le64(</div><div class='ctx'> 			 FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |</div><div class='ctx'> 			 FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |</div><div class='ctx'> 			 FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |</div><div class='hunk'>@@ -1352,7 +1349,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> </div><div class='ctx'> 		if (smmu-&gt;features &amp; ARM_SMMU_FEAT_STALLS &amp;&amp;</div><div class='ctx'> 		    !master-&gt;stall_enabled)</div><div class='del'>-			dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);</div><div class='add'>+			dst-&gt;data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);</div><div class='ctx'> </div><div class='ctx'> 		val |= (cd_table-&gt;cdtab_dma &amp; STRTAB_STE_0_S1CTXPTR_MASK) |</div><div class='ctx'> 			FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |</div><div class='hunk'>@@ -1362,7 +1359,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> </div><div class='ctx'> 	if (s2_cfg) {</div><div class='ctx'> 		BUG_ON(ste_live);</div><div class='del'>-		dst[2] = cpu_to_le64(</div><div class='add'>+		dst-&gt;data[2] = cpu_to_le64(</div><div class='ctx'> 			 FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg-&gt;vmid) |</div><div class='ctx'> 			 FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg-&gt;vtcr) |</div><div class='ctx'> #ifdef __BIG_ENDIAN</div><div class='hunk'>@@ -1371,18 +1368,18 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 			 STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |</div><div class='ctx'> 			 STRTAB_STE_2_S2R);</div><div class='ctx'> </div><div class='del'>-		dst[3] = cpu_to_le64(s2_cfg-&gt;vttbr &amp; STRTAB_STE_3_S2TTB_MASK);</div><div class='add'>+		dst-&gt;data[3] = cpu_to_le64(s2_cfg-&gt;vttbr &amp; STRTAB_STE_3_S2TTB_MASK);</div><div class='ctx'> </div><div class='ctx'> 		val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (master-&gt;ats_enabled)</div><div class='del'>-		dst[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,</div><div class='add'>+		dst-&gt;data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS,</div><div class='ctx'> 						 STRTAB_STE_1_EATS_TRANS));</div><div class='ctx'> </div><div class='ctx'> 	arm_smmu_sync_ste_for_sid(smmu, sid);</div><div class='ctx'> 	/* See comment in arm_smmu_write_ctx_desc() */</div><div class='del'>-	WRITE_ONCE(dst[0], cpu_to_le64(val));</div><div class='add'>+	WRITE_ONCE(dst-&gt;data[0], cpu_to_le64(val));</div><div class='ctx'> 	arm_smmu_sync_ste_for_sid(smmu, sid);</div><div class='ctx'> </div><div class='ctx'> 	/* It's likely that we'll want to use the new STE soon */</div><div class='hunk'>@@ -1390,7 +1387,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,</div><div class='ctx'> 		arm_smmu_cmdq_issue_cmd(smmu, &amp;prefetch_cmd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool force)</div><div class='add'>+static void arm_smmu_init_bypass_stes(struct arm_smmu_ste *strtab,</div><div class='add'>+				      unsigned int nent, bool force)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	u64 val = STRTAB_STE_0_V;</div><div class='hunk'>@@ -1401,11 +1399,11 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool fo</div><div class='ctx'> 		val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; nent; ++i) {</div><div class='del'>-		strtab[0] = cpu_to_le64(val);</div><div class='del'>-		strtab[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,</div><div class='del'>-						   STRTAB_STE_1_SHCFG_INCOMING));</div><div class='del'>-		strtab[2] = 0;</div><div class='del'>-		strtab += STRTAB_STE_DWORDS;</div><div class='add'>+		strtab-&gt;data[0] = cpu_to_le64(val);</div><div class='add'>+		strtab-&gt;data[1] = cpu_to_le64(FIELD_PREP(</div><div class='add'>+			STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));</div><div class='add'>+		strtab-&gt;data[2] = 0;</div><div class='add'>+		strtab++;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2171,7 +2169,6 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)</div><div class='ctx'> 		fmt = ARM_64_LPAE_S1;</div><div class='ctx'> 		finalise_stage_fn = arm_smmu_domain_finalise_s1;</div><div class='ctx'> 		break;</div><div class='del'>-	case ARM_SMMU_DOMAIN_NESTED:</div><div class='ctx'> 	case ARM_SMMU_DOMAIN_S2:</div><div class='ctx'> 		ias = smmu-&gt;ias;</div><div class='ctx'> 		oas = smmu-&gt;oas;</div><div class='hunk'>@@ -2209,26 +2206,23 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)</div><div class='add'>+static struct arm_smmu_ste *</div><div class='add'>+arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)</div><div class='ctx'> {</div><div class='del'>-	__le64 *step;</div><div class='ctx'> 	struct arm_smmu_strtab_cfg *cfg = &amp;smmu-&gt;strtab_cfg;</div><div class='ctx'> </div><div class='ctx'> 	if (smmu-&gt;features &amp; ARM_SMMU_FEAT_2_LVL_STRTAB) {</div><div class='del'>-		struct arm_smmu_strtab_l1_desc *l1_desc;</div><div class='del'>-		int idx;</div><div class='add'>+		unsigned int idx1, idx2;</div><div class='ctx'> </div><div class='ctx'> 		/* Two-level walk */</div><div class='del'>-		idx = (sid &gt;&gt; STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;</div><div class='del'>-		l1_desc = &amp;cfg-&gt;l1_desc[idx];</div><div class='del'>-		idx = (sid &amp; ((1 &lt;&lt; STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS;</div><div class='del'>-		step = &amp;l1_desc-&gt;l2ptr[idx];</div><div class='add'>+		idx1 = (sid &gt;&gt; STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;</div><div class='add'>+		idx2 = sid &amp; ((1 &lt;&lt; STRTAB_SPLIT) - 1);</div><div class='add'>+		return &amp;cfg-&gt;l1_desc[idx1].l2ptr[idx2];</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Simple linear lookup */</div><div class='del'>-		step = &amp;cfg-&gt;strtab[sid * STRTAB_STE_DWORDS];</div><div class='add'>+		return (struct arm_smmu_ste *)&amp;cfg</div><div class='add'>+			       -&gt;strtab[sid * STRTAB_STE_DWORDS];</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return step;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)</div><div class='hunk'>@@ -2238,7 +2232,8 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; master-&gt;num_streams; ++i) {</div><div class='ctx'> 		u32 sid = master-&gt;streams[i].id;</div><div class='del'>-		__le64 *step = arm_smmu_get_step_for_sid(smmu, sid);</div><div class='add'>+		struct arm_smmu_ste *step =</div><div class='add'>+			arm_smmu_get_step_for_sid(smmu, sid);</div><div class='ctx'> </div><div class='ctx'> 		/* Bridged PCI devices may end up with duplicated IDs */</div><div class='ctx'> 		for (j = 0; j &lt; i; j++)</div><div class='hunk'>@@ -2649,9 +2644,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)</div><div class='ctx'> 	struct arm_smmu_master *master;</div><div class='ctx'> 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='ctx'> </div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;arm_smmu_ops)</div><div class='del'>-		return ERR_PTR(-ENODEV);</div><div class='del'>-</div><div class='ctx'> 	if (WARN_ON_ONCE(dev_iommu_priv_get(dev)))</div><div class='ctx'> 		return ERR_PTR(-EBUSY);</div><div class='ctx'> </div><div class='hunk'>@@ -2698,7 +2690,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> err_free_master:</div><div class='ctx'> 	kfree(master);</div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2742,7 +2733,7 @@ static int arm_smmu_enable_nesting(struct iommu_domain *domain)</div><div class='ctx'> 	if (smmu_domain-&gt;smmu)</div><div class='ctx'> 		ret = -EPERM;</div><div class='ctx'> 	else</div><div class='del'>-		smmu_domain-&gt;stage = ARM_SMMU_DOMAIN_NESTED;</div><div class='add'>+		smmu_domain-&gt;stage = ARM_SMMU_DOMAIN_S2;</div><div class='ctx'> 	mutex_unlock(&amp;smmu_domain-&gt;init_mutex);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -3769,7 +3760,7 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu)</div><div class='ctx'> 	iort_get_rmr_sids(dev_fwnode(smmu-&gt;dev), &amp;rmr_list);</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(e, &amp;rmr_list, list) {</div><div class='del'>-		__le64 *step;</div><div class='add'>+		struct arm_smmu_ste *step;</div><div class='ctx'> 		struct iommu_iort_rmr_data *rmr;</div><div class='ctx'> 		int ret, i;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h<br/>index 961205ba86d2..65fb388d5173 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h</a></div><div class='hunk'>@@ -188,7 +188,7 @@</div><div class='ctx'> #ifdef CONFIG_CMA_ALIGNMENT</div><div class='ctx'> #define Q_MAX_SZ_SHIFT			(PAGE_SHIFT + CONFIG_CMA_ALIGNMENT)</div><div class='ctx'> #else</div><div class='del'>-#define Q_MAX_SZ_SHIFT			(PAGE_SHIFT + MAX_ORDER)</div><div class='add'>+#define Q_MAX_SZ_SHIFT			(PAGE_SHIFT + MAX_PAGE_ORDER)</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -206,6 +206,11 @@</div><div class='ctx'> #define STRTAB_L1_DESC_L2PTR_MASK	GENMASK_ULL(51, 6)</div><div class='ctx'> </div><div class='ctx'> #define STRTAB_STE_DWORDS		8</div><div class='add'>+</div><div class='add'>+struct arm_smmu_ste {</div><div class='add'>+	__le64 data[STRTAB_STE_DWORDS];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define STRTAB_STE_0_V			(1UL &lt;&lt; 0)</div><div class='ctx'> #define STRTAB_STE_0_CFG		GENMASK_ULL(3, 1)</div><div class='ctx'> #define STRTAB_STE_0_CFG_ABORT		0</div><div class='hunk'>@@ -571,7 +576,7 @@ struct arm_smmu_priq {</div><div class='ctx'> struct arm_smmu_strtab_l1_desc {</div><div class='ctx'> 	u8				span;</div><div class='ctx'> </div><div class='del'>-	__le64				*l2ptr;</div><div class='add'>+	struct arm_smmu_ste		*l2ptr;</div><div class='ctx'> 	dma_addr_t			l2ptr_dma;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -710,7 +715,6 @@ struct arm_smmu_master {</div><div class='ctx'> enum arm_smmu_domain_stage {</div><div class='ctx'> 	ARM_SMMU_DOMAIN_S1 = 0,</div><div class='ctx'> 	ARM_SMMU_DOMAIN_S2,</div><div class='del'>-	ARM_SMMU_DOMAIN_NESTED,</div><div class='ctx'> 	ARM_SMMU_DOMAIN_BYPASS,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c<br/>index 549ae4dba3a6..8b04ece00420 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c</a></div><div class='hunk'>@@ -243,8 +243,10 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {</div><div class='ctx'> 	{ .compatible = "qcom,adreno" },</div><div class='add'>+	{ .compatible = "qcom,adreno-gmu" },</div><div class='ctx'> 	{ .compatible = "qcom,mdp4" },</div><div class='ctx'> 	{ .compatible = "qcom,mdss" },</div><div class='add'>+	{ .compatible = "qcom,qcm2290-mdss" },</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-mdss" },</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-mss-pil" },</div><div class='ctx'> 	{ .compatible = "qcom,sc7280-mdss" },</div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c<br/>index d6d1a2a55cc0..68b6bc5e7c71 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu/arm-smmu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu.c</a></div><div class='hunk'>@@ -82,6 +82,23 @@ static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu)</div><div class='ctx'> 		pm_runtime_put_autosuspend(smmu-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * Setup an autosuspend delay to avoid bouncing runpm state.</div><div class='add'>+	 * Otherwise, if a driver for a suspended consumer device</div><div class='add'>+	 * unmaps buffers, it will runpm resume/suspend for each one.</div><div class='add'>+	 *</div><div class='add'>+	 * For example, when used by a GPU device, when an application</div><div class='add'>+	 * or game exits, it can trigger unmapping 100s or 1000s of</div><div class='add'>+	 * buffers.  With a runpm cycle for each buffer, that adds up</div><div class='add'>+	 * to 5-10sec worth of reprogramming the context bank, while</div><div class='add'>+	 * the system appears to be locked up to the user.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_set_autosuspend_delay(smmu-&gt;dev, 20);</div><div class='add'>+	pm_runtime_use_autosuspend(smmu-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)</div><div class='ctx'> {</div><div class='ctx'> 	return container_of(dom, struct arm_smmu_domain, domain);</div><div class='hunk'>@@ -392,8 +409,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 fsr, fsynr, cbfrsynra;</div><div class='ctx'> 	unsigned long iova;</div><div class='del'>-	struct iommu_domain *domain = dev;</div><div class='del'>-	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);</div><div class='add'>+	struct arm_smmu_domain *smmu_domain = dev;</div><div class='ctx'> 	struct arm_smmu_device *smmu = smmu_domain-&gt;smmu;</div><div class='ctx'> 	int idx = smmu_domain-&gt;cfg.cbndx;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -406,7 +422,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)</div><div class='ctx'> 	iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);</div><div class='ctx'> 	cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));</div><div class='ctx'> </div><div class='del'>-	ret = report_iommu_fault(domain, NULL, iova,</div><div class='add'>+	ret = report_iommu_fault(&amp;smmu_domain-&gt;domain, NULL, iova,</div><div class='ctx'> 		fsynr &amp; ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);</div><div class='ctx'> </div><div class='ctx'> 	if (ret == -ENOSYS)</div><div class='hunk'>@@ -607,7 +623,7 @@ static int arm_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,</div><div class='ctx'> 	return __arm_smmu_alloc_bitmap(smmu-&gt;context_map, start, smmu-&gt;num_context_banks);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int arm_smmu_init_domain_context(struct iommu_domain *domain,</div><div class='add'>+static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domain,</div><div class='ctx'> 					struct arm_smmu_device *smmu,</div><div class='ctx'> 					struct device *dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -616,7 +632,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,</div><div class='ctx'> 	struct io_pgtable_ops *pgtbl_ops;</div><div class='ctx'> 	struct io_pgtable_cfg pgtbl_cfg;</div><div class='ctx'> 	enum io_pgtable_fmt fmt;</div><div class='del'>-	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);</div><div class='add'>+	struct iommu_domain *domain = &amp;smmu_domain-&gt;domain;</div><div class='ctx'> 	struct arm_smmu_cfg *cfg = &amp;smmu_domain-&gt;cfg;</div><div class='ctx'> 	irqreturn_t (*context_fault)(int irq, void *dev);</div><div class='ctx'> </div><div class='hunk'>@@ -624,12 +640,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,</div><div class='ctx'> 	if (smmu_domain-&gt;smmu)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='del'>-	if (domain-&gt;type == IOMMU_DOMAIN_IDENTITY) {</div><div class='del'>-		smmu_domain-&gt;stage = ARM_SMMU_DOMAIN_BYPASS;</div><div class='del'>-		smmu_domain-&gt;smmu = smmu;</div><div class='del'>-		goto out_unlock;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Mapping the requested stage onto what we support is surprisingly</div><div class='ctx'> 	 * complicated, mainly because the spec allows S1+S2 SMMUs without</div><div class='hunk'>@@ -796,8 +806,8 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,</div><div class='ctx'> 	else</div><div class='ctx'> 		context_fault = arm_smmu_context_fault;</div><div class='ctx'> </div><div class='del'>-	ret = devm_request_irq(smmu-&gt;dev, irq, context_fault,</div><div class='del'>-			       IRQF_SHARED, "arm-smmu-context-fault", domain);</div><div class='add'>+	ret = devm_request_irq(smmu-&gt;dev, irq, context_fault, IRQF_SHARED,</div><div class='add'>+			       "arm-smmu-context-fault", smmu_domain);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(smmu-&gt;dev, "failed to request context IRQ %d (%u)\n",</div><div class='ctx'> 			cfg-&gt;irptndx, irq);</div><div class='hunk'>@@ -818,14 +828,13 @@ out_unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)</div><div class='add'>+static void arm_smmu_destroy_domain_context(struct arm_smmu_domain *smmu_domain)</div><div class='ctx'> {</div><div class='del'>-	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);</div><div class='ctx'> 	struct arm_smmu_device *smmu = smmu_domain-&gt;smmu;</div><div class='ctx'> 	struct arm_smmu_cfg *cfg = &amp;smmu_domain-&gt;cfg;</div><div class='ctx'> 	int ret, irq;</div><div class='ctx'> </div><div class='del'>-	if (!smmu || domain-&gt;type == IOMMU_DOMAIN_IDENTITY)</div><div class='add'>+	if (!smmu)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	ret = arm_smmu_rpm_get(smmu);</div><div class='hunk'>@@ -841,7 +850,7 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)</div><div class='ctx'> </div><div class='ctx'> 	if (cfg-&gt;irptndx != ARM_SMMU_INVALID_IRPTNDX) {</div><div class='ctx'> 		irq = smmu-&gt;irqs[cfg-&gt;irptndx];</div><div class='del'>-		devm_free_irq(smmu-&gt;dev, irq, domain);</div><div class='add'>+		devm_free_irq(smmu-&gt;dev, irq, smmu_domain);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	free_io_pgtable_ops(smmu_domain-&gt;pgtbl_ops);</div><div class='hunk'>@@ -850,14 +859,10 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)</div><div class='ctx'> 	arm_smmu_rpm_put(smmu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)</div><div class='add'>+static struct iommu_domain *arm_smmu_domain_alloc_paging(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct arm_smmu_domain *smmu_domain;</div><div class='ctx'> </div><div class='del'>-	if (type != IOMMU_DOMAIN_UNMANAGED &amp;&amp; type != IOMMU_DOMAIN_IDENTITY) {</div><div class='del'>-		if (using_legacy_binding || type != IOMMU_DOMAIN_DMA)</div><div class='del'>-			return NULL;</div><div class='del'>-	}</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Allocate the domain and initialise some of its data structures.</div><div class='ctx'> 	 * We can't really do anything meaningful until we've added a</div><div class='hunk'>@@ -870,6 +875,15 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)</div><div class='ctx'> 	mutex_init(&amp;smmu_domain-&gt;init_mutex);</div><div class='ctx'> 	spin_lock_init(&amp;smmu_domain-&gt;cb_lock);</div><div class='ctx'> </div><div class='add'>+	if (dev) {</div><div class='add'>+		struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);</div><div class='add'>+</div><div class='add'>+		if (arm_smmu_init_domain_context(smmu_domain, cfg-&gt;smmu, dev)) {</div><div class='add'>+			kfree(smmu_domain);</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return &amp;smmu_domain-&gt;domain;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -881,7 +895,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain)</div><div class='ctx'> 	 * Free the domain resources. We assume that all devices have</div><div class='ctx'> 	 * already been detached.</div><div class='ctx'> 	 */</div><div class='del'>-	arm_smmu_destroy_domain_context(domain);</div><div class='add'>+	arm_smmu_destroy_domain_context(smmu_domain);</div><div class='ctx'> 	kfree(smmu_domain);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1081,21 +1095,14 @@ static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg,</div><div class='ctx'> 	mutex_unlock(&amp;smmu-&gt;stream_map_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,</div><div class='del'>-				      struct arm_smmu_master_cfg *cfg,</div><div class='del'>-				      struct iommu_fwspec *fwspec)</div><div class='add'>+static void arm_smmu_master_install_s2crs(struct arm_smmu_master_cfg *cfg,</div><div class='add'>+					  enum arm_smmu_s2cr_type type,</div><div class='add'>+					  u8 cbndx, struct iommu_fwspec *fwspec)</div><div class='ctx'> {</div><div class='del'>-	struct arm_smmu_device *smmu = smmu_domain-&gt;smmu;</div><div class='add'>+	struct arm_smmu_device *smmu = cfg-&gt;smmu;</div><div class='ctx'> 	struct arm_smmu_s2cr *s2cr = smmu-&gt;s2crs;</div><div class='del'>-	u8 cbndx = smmu_domain-&gt;cfg.cbndx;</div><div class='del'>-	enum arm_smmu_s2cr_type type;</div><div class='ctx'> 	int i, idx;</div><div class='ctx'> </div><div class='del'>-	if (smmu_domain-&gt;stage == ARM_SMMU_DOMAIN_BYPASS)</div><div class='del'>-		type = S2CR_TYPE_BYPASS;</div><div class='del'>-	else</div><div class='del'>-		type = S2CR_TYPE_TRANS;</div><div class='del'>-</div><div class='ctx'> 	for_each_cfg_sme(cfg, fwspec, i, idx) {</div><div class='ctx'> 		if (type == s2cr[idx].type &amp;&amp; cbndx == s2cr[idx].cbndx)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -1105,7 +1112,6 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,</div><div class='ctx'> 		s2cr[idx].cbndx = cbndx;</div><div class='ctx'> 		arm_smmu_write_s2cr(smmu, idx);</div><div class='ctx'> 	}</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)</div><div class='hunk'>@@ -1116,11 +1122,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)</div><div class='ctx'> 	struct arm_smmu_device *smmu;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;arm_smmu_ops) {</div><div class='del'>-		dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");</div><div class='del'>-		return -ENXIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * FIXME: The arch/arm DMA API code tries to attach devices to its own</div><div class='ctx'> 	 * domains between of_xlate() and probe_device() - we have no way to cope</div><div class='hunk'>@@ -1139,7 +1140,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Ensure that the domain is finalised */</div><div class='del'>-	ret = arm_smmu_init_domain_context(domain, smmu, dev);</div><div class='add'>+	ret = arm_smmu_init_domain_context(smmu_domain, smmu, dev);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto rpm_put;</div><div class='ctx'> </div><div class='hunk'>@@ -1153,27 +1154,66 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Looks ok, so add the device to the domain */</div><div class='del'>-	ret = arm_smmu_domain_add_master(smmu_domain, cfg, fwspec);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Setup an autosuspend delay to avoid bouncing runpm state.</div><div class='del'>-	 * Otherwise, if a driver for a suspended consumer device</div><div class='del'>-	 * unmaps buffers, it will runpm resume/suspend for each one.</div><div class='del'>-	 *</div><div class='del'>-	 * For example, when used by a GPU device, when an application</div><div class='del'>-	 * or game exits, it can trigger unmapping 100s or 1000s of</div><div class='del'>-	 * buffers.  With a runpm cycle for each buffer, that adds up</div><div class='del'>-	 * to 5-10sec worth of reprogramming the context bank, while</div><div class='del'>-	 * the system appears to be locked up to the user.</div><div class='del'>-	 */</div><div class='del'>-	pm_runtime_set_autosuspend_delay(smmu-&gt;dev, 20);</div><div class='del'>-	pm_runtime_use_autosuspend(smmu-&gt;dev);</div><div class='del'>-</div><div class='add'>+	arm_smmu_master_install_s2crs(cfg, S2CR_TYPE_TRANS,</div><div class='add'>+				      smmu_domain-&gt;cfg.cbndx, fwspec);</div><div class='add'>+	arm_smmu_rpm_use_autosuspend(smmu);</div><div class='ctx'> rpm_put:</div><div class='ctx'> 	arm_smmu_rpm_put(smmu);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int arm_smmu_attach_dev_type(struct device *dev,</div><div class='add'>+				    enum arm_smmu_s2cr_type type)</div><div class='add'>+{</div><div class='add'>+	struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);</div><div class='add'>+	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='add'>+	struct arm_smmu_device *smmu;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!cfg)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	smmu = cfg-&gt;smmu;</div><div class='add'>+</div><div class='add'>+	ret = arm_smmu_rpm_get(smmu);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	arm_smmu_master_install_s2crs(cfg, type, 0, fwspec);</div><div class='add'>+	arm_smmu_rpm_use_autosuspend(smmu);</div><div class='add'>+	arm_smmu_rpm_put(smmu);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int arm_smmu_attach_dev_identity(struct iommu_domain *domain,</div><div class='add'>+					struct device *dev)</div><div class='add'>+{</div><div class='add'>+	return arm_smmu_attach_dev_type(dev, S2CR_TYPE_BYPASS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iommu_domain_ops arm_smmu_identity_ops = {</div><div class='add'>+	.attach_dev = arm_smmu_attach_dev_identity,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct iommu_domain arm_smmu_identity_domain = {</div><div class='add'>+	.type = IOMMU_DOMAIN_IDENTITY,</div><div class='add'>+	.ops = &amp;arm_smmu_identity_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int arm_smmu_attach_dev_blocked(struct iommu_domain *domain,</div><div class='add'>+				       struct device *dev)</div><div class='add'>+{</div><div class='add'>+	return arm_smmu_attach_dev_type(dev, S2CR_TYPE_FAULT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct iommu_domain_ops arm_smmu_blocked_ops = {</div><div class='add'>+	.attach_dev = arm_smmu_attach_dev_blocked,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct iommu_domain arm_smmu_blocked_domain = {</div><div class='add'>+	.type = IOMMU_DOMAIN_BLOCKED,</div><div class='add'>+	.ops = &amp;arm_smmu_blocked_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int arm_smmu_map_pages(struct iommu_domain *domain, unsigned long iova,</div><div class='ctx'> 			      phys_addr_t paddr, size_t pgsize, size_t pgcount,</div><div class='ctx'> 			      int prot, gfp_t gfp, size_t *mapped)</div><div class='hunk'>@@ -1357,10 +1397,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)</div><div class='ctx'> 		fwspec = dev_iommu_fwspec_get(dev);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto out_free;</div><div class='del'>-	} else if (fwspec &amp;&amp; fwspec-&gt;ops == &amp;arm_smmu_ops) {</div><div class='del'>-		smmu = arm_smmu_get_by_fwnode(fwspec-&gt;iommu_fwnode);</div><div class='ctx'> 	} else {</div><div class='del'>-		return ERR_PTR(-ENODEV);</div><div class='add'>+		smmu = arm_smmu_get_by_fwnode(fwspec-&gt;iommu_fwnode);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = -EINVAL;</div><div class='hunk'>@@ -1427,7 +1465,6 @@ static void arm_smmu_release_device(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	arm_smmu_rpm_put(cfg-&gt;smmu);</div><div class='ctx'> </div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 	kfree(cfg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1560,8 +1597,10 @@ static int arm_smmu_def_domain_type(struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct iommu_ops arm_smmu_ops = {</div><div class='add'>+	.identity_domain	= &amp;arm_smmu_identity_domain,</div><div class='add'>+	.blocked_domain		= &amp;arm_smmu_blocked_domain,</div><div class='ctx'> 	.capable		= arm_smmu_capable,</div><div class='del'>-	.domain_alloc		= arm_smmu_domain_alloc,</div><div class='add'>+	.domain_alloc_paging	= arm_smmu_domain_alloc_paging,</div><div class='ctx'> 	.probe_device		= arm_smmu_probe_device,</div><div class='ctx'> 	.release_device		= arm_smmu_release_device,</div><div class='ctx'> 	.probe_finalize		= arm_smmu_probe_finalize,</div><div class='hunk'>@@ -2161,7 +2200,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = iommu_device_register(&amp;smmu-&gt;iommu, &amp;arm_smmu_ops, dev);</div><div class='add'>+	err = iommu_device_register(&amp;smmu-&gt;iommu, &amp;arm_smmu_ops,</div><div class='add'>+				    using_legacy_binding ? NULL : dev);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(dev, "Failed to register iommu\n");</div><div class='ctx'> 		iommu_device_sysfs_remove(&amp;smmu-&gt;iommu);</div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h<br/>index 703fd5817ec1..836ed6799a80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu/arm-smmu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/arm-smmu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/arm-smmu.h</a></div><div class='hunk'>@@ -361,7 +361,6 @@ enum arm_smmu_domain_stage {</div><div class='ctx'> 	ARM_SMMU_DOMAIN_S1 = 0,</div><div class='ctx'> 	ARM_SMMU_DOMAIN_S2,</div><div class='ctx'> 	ARM_SMMU_DOMAIN_NESTED,</div><div class='del'>-	ARM_SMMU_DOMAIN_BYPASS,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct arm_smmu_domain {</div><div class='head'>diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c<br/>index 97b2122032b2..17a1c163fef6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/qcom_iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/arm/arm-smmu/qcom_iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/arm/arm-smmu/qcom_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/arm/arm-smmu/qcom_iommu.c</a></div><div class='hunk'>@@ -79,16 +79,6 @@ static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)</div><div class='ctx'> </div><div class='ctx'> static const struct iommu_ops qcom_iommu_ops;</div><div class='ctx'> </div><div class='del'>-static struct qcom_iommu_dev * to_iommu(struct device *dev)</div><div class='del'>-{</div><div class='del'>-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-</div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;qcom_iommu_ops)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	return dev_iommu_priv_get(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_iommu_dev *qcom_iommu = d-&gt;iommu;</div><div class='hunk'>@@ -372,7 +362,7 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain)</div><div class='ctx'> </div><div class='ctx'> static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);</div><div class='add'>+	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -404,7 +394,7 @@ static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain,</div><div class='ctx'> 	struct iommu_domain *domain = iommu_get_domain_for_dev(dev);</div><div class='ctx'> 	struct qcom_iommu_domain *qcom_domain;</div><div class='ctx'> 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-	struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);</div><div class='add'>+	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	if (domain == identity_domain || !domain)</div><div class='hunk'>@@ -535,7 +525,7 @@ static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)</div><div class='ctx'> </div><div class='ctx'> static struct iommu_device *qcom_iommu_probe_device(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct qcom_iommu_dev *qcom_iommu = to_iommu(dev);</div><div class='add'>+	struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct device_link *link;</div><div class='ctx'> </div><div class='ctx'> 	if (!qcom_iommu)</div><div class='hunk'>@@ -900,8 +890,16 @@ static void qcom_iommu_device_remove(struct platform_device *pdev)</div><div class='ctx'> static int __maybe_unused qcom_iommu_resume(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_bulk_prepare_enable(CLK_NUM, qcom_iommu-&gt;clks);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;pm_domain)</div><div class='add'>+		return qcom_scm_restore_sec_cfg(qcom_iommu-&gt;sec_id, 0);</div><div class='ctx'> </div><div class='del'>-	return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu-&gt;clks);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused qcom_iommu_suspend(struct device *dev)</div><div class='head'>diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c<br/>index 85163a83df2f..50ccc4f1ef81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/dma-iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/dma-iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/dma-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/dma-iommu.c</a></div><div class='hunk'>@@ -29,6 +29,7 @@</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/swiotlb.h&gt;</div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='add'>+#include &lt;trace/events/swiotlb.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "dma-iommu.h"</div><div class='ctx'> </div><div class='hunk'>@@ -884,7 +885,7 @@ static struct page **__iommu_dma_alloc_pages(struct device *dev,</div><div class='ctx'> 	struct page **pages;</div><div class='ctx'> 	unsigned int i = 0, nid = dev_to_node(dev);</div><div class='ctx'> </div><div class='del'>-	order_mask &amp;= GENMASK(MAX_ORDER, 0);</div><div class='add'>+	order_mask &amp;= GENMASK(MAX_PAGE_ORDER, 0);</div><div class='ctx'> 	if (!order_mask)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -1156,6 +1157,8 @@ static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,</div><div class='ctx'> 			return DMA_MAPPING_ERROR;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		trace_swiotlb_bounced(dev, phys, size);</div><div class='add'>+</div><div class='ctx'> 		aligned_size = iova_align(iovad, size);</div><div class='ctx'> 		phys = swiotlb_tbl_map_single(dev, phys, size, aligned_size,</div><div class='ctx'> 					      iova_mask(iovad), dir, attrs);</div><div class='head'>diff --git a/drivers/iommu/intel/debugfs.c b/drivers/iommu/intel/debugfs.c<br/>index dee61e513be6..86b506af7daa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/debugfs.c</a></div><div class='hunk'>@@ -106,9 +106,6 @@ static const struct iommu_regset iommu_regs_64[] = {</div><div class='ctx'> 	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),</div><div class='ctx'> 	IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),</div><div class='ctx'> 	IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),</div><div class='del'>-	IOMMU_REGSET_ENTRY(VCCAP),</div><div class='del'>-	IOMMU_REGSET_ENTRY(VCMD),</div><div class='del'>-	IOMMU_REGSET_ENTRY(VCRSP),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct dentry *intel_iommu_debug;</div><div class='head'>diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c<br/>index a3414afe11b0..23cb80d62a9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/dmar.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/dmar.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/dmar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/dmar.c</a></div><div class='hunk'>@@ -1522,6 +1522,15 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,</div><div class='ctx'> {</div><div class='ctx'> 	struct qi_desc desc;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * VT-d spec, section 4.3:</div><div class='add'>+	 *</div><div class='add'>+	 * Software is recommended to not submit any Device-TLB invalidation</div><div class='add'>+	 * requests while address remapping hardware is disabled.</div><div class='add'>+	 */</div><div class='add'>+	if (!(iommu-&gt;gcmd &amp; DMA_GCMD_TE))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (mask) {</div><div class='ctx'> 		addr |= (1ULL &lt;&lt; (VTD_PAGE_SHIFT + mask - 1)) - 1;</div><div class='ctx'> 		desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;</div><div class='hunk'>@@ -1587,6 +1596,15 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,</div><div class='ctx'> 	unsigned long mask = 1UL &lt;&lt; (VTD_PAGE_SHIFT + size_order - 1);</div><div class='ctx'> 	struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * VT-d spec, section 4.3:</div><div class='add'>+	 *</div><div class='add'>+	 * Software is recommended to not submit any Device-TLB invalidation</div><div class='add'>+	 * requests while address remapping hardware is disabled.</div><div class='add'>+	 */</div><div class='add'>+	if (!(iommu-&gt;gcmd &amp; DMA_GCMD_TE))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |</div><div class='ctx'> 		QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |</div><div class='ctx'> 		QI_DEV_IOTLB_PFSID(pfsid);</div><div class='head'>diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c<br/>index 3531b956556c..6fb5f6fceea1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/iommu.c</a></div><div class='hunk'>@@ -46,9 +46,6 @@</div><div class='ctx'> </div><div class='ctx'> #define DEFAULT_DOMAIN_ADDRESS_WIDTH 57</div><div class='ctx'> </div><div class='del'>-#define MAX_AGAW_WIDTH 64</div><div class='del'>-#define MAX_AGAW_PFN_WIDTH	(MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)</div><div class='del'>-</div><div class='ctx'> #define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) &lt;&lt; ((gaw) - VTD_PAGE_SHIFT)) - 1)</div><div class='ctx'> #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) &lt;&lt; (gaw)) - 1)</div><div class='ctx'> </div><div class='hunk'>@@ -63,74 +60,6 @@</div><div class='ctx'> </div><div class='ctx'> #define IOVA_PFN(addr)		((addr) &gt;&gt; PAGE_SHIFT)</div><div class='ctx'> </div><div class='del'>-/* page table handling */</div><div class='del'>-#define LEVEL_STRIDE		(9)</div><div class='del'>-#define LEVEL_MASK		(((u64)1 &lt;&lt; LEVEL_STRIDE) - 1)</div><div class='del'>-</div><div class='del'>-static inline int agaw_to_level(int agaw)</div><div class='del'>-{</div><div class='del'>-	return agaw + 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline int agaw_to_width(int agaw)</div><div class='del'>-{</div><div class='del'>-	return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline int width_to_agaw(int width)</div><div class='del'>-{</div><div class='del'>-	return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline unsigned int level_to_offset_bits(int level)</div><div class='del'>-{</div><div class='del'>-	return (level - 1) * LEVEL_STRIDE;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline int pfn_level_offset(u64 pfn, int level)</div><div class='del'>-{</div><div class='del'>-	return (pfn &gt;&gt; level_to_offset_bits(level)) &amp; LEVEL_MASK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u64 level_mask(int level)</div><div class='del'>-{</div><div class='del'>-	return -1ULL &lt;&lt; level_to_offset_bits(level);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u64 level_size(int level)</div><div class='del'>-{</div><div class='del'>-	return 1ULL &lt;&lt; level_to_offset_bits(level);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u64 align_to_level(u64 pfn, int level)</div><div class='del'>-{</div><div class='del'>-	return (pfn + level_size(level) - 1) &amp; level_mask(level);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline unsigned long lvl_to_nr_pages(unsigned int lvl)</div><div class='del'>-{</div><div class='del'>-	return 1UL &lt;&lt; min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* VT-d pages must always be _smaller_ than MM pages. Otherwise things</div><div class='del'>-   are never going to work. */</div><div class='del'>-static inline unsigned long mm_to_dma_pfn_start(unsigned long mm_pfn)</div><div class='del'>-{</div><div class='del'>-	return mm_pfn &lt;&lt; (PAGE_SHIFT - VTD_PAGE_SHIFT);</div><div class='del'>-}</div><div class='del'>-static inline unsigned long mm_to_dma_pfn_end(unsigned long mm_pfn)</div><div class='del'>-{</div><div class='del'>-	return ((mm_pfn + 1) &lt;&lt; (PAGE_SHIFT - VTD_PAGE_SHIFT)) - 1;</div><div class='del'>-}</div><div class='del'>-static inline unsigned long page_to_dma_pfn(struct page *pg)</div><div class='del'>-{</div><div class='del'>-	return mm_to_dma_pfn_start(page_to_pfn(pg));</div><div class='del'>-}</div><div class='del'>-static inline unsigned long virt_to_dma_pfn(void *p)</div><div class='del'>-{</div><div class='del'>-	return page_to_dma_pfn(virt_to_page(p));</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void __init check_tylersburg_isoch(void);</div><div class='ctx'> static int rwbf_quirk;</div><div class='ctx'> </div><div class='hunk'>@@ -168,78 +97,6 @@ static phys_addr_t root_entry_uctp(struct root_entry *re)</div><div class='ctx'> 	return re-&gt;hi &amp; VTD_PAGE_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void context_set_present(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo |= 1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_fault_enable(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo &amp;= (((u64)-1) &lt;&lt; 2) | 1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_translation_type(struct context_entry *context,</div><div class='del'>-						unsigned long value)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo &amp;= (((u64)-1) &lt;&lt; 4) | 3;</div><div class='del'>-	context-&gt;lo |= (value &amp; 3) &lt;&lt; 2;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_address_root(struct context_entry *context,</div><div class='del'>-					    unsigned long value)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo &amp;= ~VTD_PAGE_MASK;</div><div class='del'>-	context-&gt;lo |= value &amp; VTD_PAGE_MASK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_address_width(struct context_entry *context,</div><div class='del'>-					     unsigned long value)</div><div class='del'>-{</div><div class='del'>-	context-&gt;hi |= value &amp; 7;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_domain_id(struct context_entry *context,</div><div class='del'>-					 unsigned long value)</div><div class='del'>-{</div><div class='del'>-	context-&gt;hi |= (value &amp; ((1 &lt;&lt; 16) - 1)) &lt;&lt; 8;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_set_pasid(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo |= CONTEXT_PASIDE;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline int context_domain_id(struct context_entry *c)</div><div class='del'>-{</div><div class='del'>-	return((c-&gt;hi &gt;&gt; 8) &amp; 0xffff);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void context_clear_entry(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo = 0;</div><div class='del'>-	context-&gt;hi = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='del'>-{</div><div class='del'>-	if (!iommu-&gt;copied_tables)</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-	return test_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void</div><div class='del'>-set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='del'>-{</div><div class='del'>-	set_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void</div><div class='del'>-clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='del'>-{</div><div class='del'>-	clear_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * This domain is a statically identity mapping domain.</div><div class='ctx'>  *	1. This domain creats a static 1:1 mapping to all usable memory.</div><div class='hunk'>@@ -299,7 +156,7 @@ static int iommu_skip_te_disable;</div><div class='ctx'> #define IDENTMAP_AZALIA		4</div><div class='ctx'> </div><div class='ctx'> const struct iommu_ops intel_iommu_ops;</div><div class='del'>-const struct iommu_dirty_ops intel_dirty_ops;</div><div class='add'>+static const struct iommu_dirty_ops intel_dirty_ops;</div><div class='ctx'> </div><div class='ctx'> static bool translation_pre_enabled(struct intel_iommu *iommu)</div><div class='ctx'> {</div><div class='hunk'>@@ -383,13 +240,12 @@ void free_pgtable_page(void *vaddr)</div><div class='ctx'> 	free_page((unsigned long)vaddr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int domain_type_is_si(struct dmar_domain *domain)</div><div class='add'>+static int domain_type_is_si(struct dmar_domain *domain)</div><div class='ctx'> {</div><div class='ctx'> 	return domain-&gt;domain.type == IOMMU_DOMAIN_IDENTITY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int domain_pfn_supported(struct dmar_domain *domain,</div><div class='del'>-				       unsigned long pfn)</div><div class='add'>+static int domain_pfn_supported(struct dmar_domain *domain, unsigned long pfn)</div><div class='ctx'> {</div><div class='ctx'> 	int addr_width = agaw_to_width(domain-&gt;agaw) - VTD_PAGE_SHIFT;</div><div class='ctx'> </div><div class='hunk'>@@ -451,7 +307,7 @@ int iommu_calculate_agaw(struct intel_iommu *iommu)</div><div class='ctx'> 	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline bool iommu_paging_structure_coherency(struct intel_iommu *iommu)</div><div class='add'>+static bool iommu_paging_structure_coherency(struct intel_iommu *iommu)</div><div class='ctx'> {</div><div class='ctx'> 	return sm_supported(iommu) ?</div><div class='ctx'> 			ecap_smpwc(iommu-&gt;ecap) : ecap_coherent(iommu-&gt;ecap);</div><div class='hunk'>@@ -703,7 +559,7 @@ static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)</div><div class='add'>+static struct intel_iommu *device_lookup_iommu(struct device *dev, u8 *bus, u8 *devfn)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmar_drhd_unit *drhd = NULL;</div><div class='ctx'> 	struct pci_dev *pdev = NULL;</div><div class='hunk'>@@ -1574,9 +1430,8 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Notification for newly created mappings */</div><div class='del'>-static inline void __mapping_notify_one(struct intel_iommu *iommu,</div><div class='del'>-					struct dmar_domain *domain,</div><div class='del'>-					unsigned long pfn, unsigned int pages)</div><div class='add'>+static void __mapping_notify_one(struct intel_iommu *iommu, struct dmar_domain *domain,</div><div class='add'>+				 unsigned long pfn, unsigned int pages)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * It's a non-present to present mapping. Only flush if caching mode</div><div class='hunk'>@@ -1843,7 +1698,7 @@ void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu)</div><div class='ctx'> 	spin_unlock(&amp;iommu-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int guestwidth_to_adjustwidth(int gaw)</div><div class='add'>+static int guestwidth_to_adjustwidth(int gaw)</div><div class='ctx'> {</div><div class='ctx'> 	int agaw;</div><div class='ctx'> 	int r = (gaw - 12) % 9;</div><div class='hunk'>@@ -1877,7 +1732,7 @@ static void domain_exit(struct dmar_domain *domain)</div><div class='ctx'>  * Value of X in the PDTS field of a scalable mode context entry</div><div class='ctx'>  * indicates PASID directory with 2^(X + 7) entries.</div><div class='ctx'>  */</div><div class='del'>-static inline unsigned long context_get_sm_pds(struct pasid_table *table)</div><div class='add'>+static unsigned long context_get_sm_pds(struct pasid_table *table)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long pds, max_pde;</div><div class='ctx'> </div><div class='hunk'>@@ -1889,38 +1744,6 @@ static inline unsigned long context_get_sm_pds(struct pasid_table *table)</div><div class='ctx'> 	return pds - 7;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Set the RID_PASID field of a scalable mode context entry. The</div><div class='del'>- * IOMMU hardware will use the PASID value set in this field for</div><div class='del'>- * DMA translations of DMA requests without PASID.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid)</div><div class='del'>-{</div><div class='del'>-	context-&gt;hi |= pasid &amp; ((1 &lt;&lt; 20) - 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Set the DTE(Device-TLB Enable) field of a scalable mode context</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void context_set_sm_dte(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo |= BIT_ULL(2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Set the PRE(Page Request Enable) field of a scalable mode context</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void context_set_sm_pre(struct context_entry *context)</div><div class='del'>-{</div><div class='del'>-	context-&gt;lo |= BIT_ULL(4);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Convert value to context PASID directory size field coding. */</div><div class='del'>-#define context_pdts(pds)	(((pds) &amp; 0x7) &lt;&lt; 9)</div><div class='del'>-</div><div class='ctx'> static int domain_context_mapping_one(struct dmar_domain *domain,</div><div class='ctx'> 				      struct intel_iommu *iommu,</div><div class='ctx'> 				      struct pasid_table *table,</div><div class='hunk'>@@ -2081,14 +1904,11 @@ static int domain_context_mapping_cb(struct pci_dev *pdev,</div><div class='ctx'> static int</div><div class='ctx'> domain_context_mapping(struct dmar_domain *domain, struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct domain_context_mapping_data data;</div><div class='add'>+	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='add'>+	u8 bus = info-&gt;bus, devfn = info-&gt;devfn;</div><div class='ctx'> 	struct pasid_table *table;</div><div class='del'>-	struct intel_iommu *iommu;</div><div class='del'>-	u8 bus, devfn;</div><div class='del'>-</div><div class='del'>-	iommu = device_to_iommu(dev, &amp;bus, &amp;devfn);</div><div class='del'>-	if (!iommu)</div><div class='del'>-		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	table = intel_pasid_get_table(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -2105,18 +1925,15 @@ domain_context_mapping(struct dmar_domain *domain, struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Returns a number of VTD pages, but aligned to MM page size */</div><div class='del'>-static inline unsigned long aligned_nrpages(unsigned long host_addr,</div><div class='del'>-					    size_t size)</div><div class='add'>+static unsigned long aligned_nrpages(unsigned long host_addr, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	host_addr &amp;= ~PAGE_MASK;</div><div class='ctx'> 	return PAGE_ALIGN(host_addr + size) &gt;&gt; VTD_PAGE_SHIFT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Return largest possible superpage level for a given mapping */</div><div class='del'>-static inline int hardware_largepage_caps(struct dmar_domain *domain,</div><div class='del'>-					  unsigned long iov_pfn,</div><div class='del'>-					  unsigned long phy_pfn,</div><div class='del'>-					  unsigned long pages)</div><div class='add'>+static int hardware_largepage_caps(struct dmar_domain *domain, unsigned long iov_pfn,</div><div class='add'>+				   unsigned long phy_pfn, unsigned long pages)</div><div class='ctx'> {</div><div class='ctx'> 	int support, level = 1;</div><div class='ctx'> 	unsigned long pfnmerge;</div><div class='hunk'>@@ -2207,6 +2024,8 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,</div><div class='ctx'> 			attr |= DMA_FL_PTE_DIRTY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	domain-&gt;has_mappings = true;</div><div class='add'>+</div><div class='ctx'> 	pteval = ((phys_addr_t)phys_pfn &lt;&lt; VTD_PAGE_SHIFT) | attr;</div><div class='ctx'> </div><div class='ctx'> 	while (nr_pages &gt; 0) {</div><div class='hunk'>@@ -2447,15 +2266,10 @@ static int dmar_domain_attach_device(struct dmar_domain *domain,</div><div class='ctx'> 				     struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='del'>-	struct intel_iommu *iommu;</div><div class='add'>+	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	u8 bus, devfn;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	iommu = device_to_iommu(dev, &amp;bus, &amp;devfn);</div><div class='del'>-	if (!iommu)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='ctx'> 	ret = domain_attach_iommu(domain, iommu);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -2468,7 +2282,7 @@ static int dmar_domain_attach_device(struct dmar_domain *domain,</div><div class='ctx'> 	if (sm_supported(iommu) &amp;&amp; !dev_is_real_dma_subdevice(dev)) {</div><div class='ctx'> 		/* Setup the PASID entry for requests without PASID: */</div><div class='ctx'> 		if (hw_pass_through &amp;&amp; domain_type_is_si(domain))</div><div class='del'>-			ret = intel_pasid_setup_pass_through(iommu, domain,</div><div class='add'>+			ret = intel_pasid_setup_pass_through(iommu,</div><div class='ctx'> 					dev, IOMMU_NO_PASID);</div><div class='ctx'> 		else if (domain-&gt;use_first_level)</div><div class='ctx'> 			ret = domain_setup_first_level(iommu, domain, dev,</div><div class='hunk'>@@ -2490,7 +2304,8 @@ static int dmar_domain_attach_device(struct dmar_domain *domain,</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	iommu_enable_pci_caps(info);</div><div class='add'>+	if (sm_supported(info-&gt;iommu) || !domain_type_is_si(info-&gt;domain))</div><div class='add'>+		iommu_enable_pci_caps(info);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3612,7 +3427,7 @@ void intel_iommu_shutdown(void)</div><div class='ctx'> 	up_write(&amp;dmar_global_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline struct intel_iommu *dev_to_intel_iommu(struct device *dev)</div><div class='add'>+static struct intel_iommu *dev_to_intel_iommu(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_device *iommu_dev = dev_to_iommu_device(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -3691,7 +3506,7 @@ const struct attribute_group *intel_iommu_groups[] = {</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static inline bool has_external_pci(void)</div><div class='add'>+static bool has_external_pci(void)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -3925,8 +3740,8 @@ static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *op</div><div class='ctx'>  */</div><div class='ctx'> static void domain_context_clear(struct device_domain_info *info)</div><div class='ctx'> {</div><div class='del'>-	if (!info-&gt;iommu || !info-&gt;dev || !dev_is_pci(info-&gt;dev))</div><div class='del'>-		return;</div><div class='add'>+	if (!dev_is_pci(info-&gt;dev))</div><div class='add'>+		domain_context_clear_one(info, info-&gt;bus, info-&gt;devfn);</div><div class='ctx'> </div><div class='ctx'> 	pci_for_each_dma_alias(to_pci_dev(info-&gt;dev),</div><div class='ctx'> 			       &amp;domain_context_clear_one_cb, info);</div><div class='hunk'>@@ -4116,14 +3931,11 @@ static void intel_iommu_domain_free(struct iommu_domain *domain)</div><div class='ctx'> int prepare_domain_attach_device(struct iommu_domain *domain,</div><div class='ctx'> 				 struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct dmar_domain *dmar_domain = to_dmar_domain(domain);</div><div class='del'>-	struct intel_iommu *iommu;</div><div class='add'>+	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='ctx'> 	int addr_width;</div><div class='ctx'> </div><div class='del'>-	iommu = device_to_iommu(dev, NULL, NULL);</div><div class='del'>-	if (!iommu)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='ctx'> 	if (dmar_domain-&gt;force_snooping &amp;&amp; !ecap_sc_support(iommu-&gt;ecap))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -4360,7 +4172,8 @@ static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;dmar_domain-&gt;lock, flags);</div><div class='del'>-	if (!domain_support_force_snooping(dmar_domain)) {</div><div class='add'>+	if (!domain_support_force_snooping(dmar_domain) ||</div><div class='add'>+	    (!dmar_domain-&gt;use_first_level &amp;&amp; dmar_domain-&gt;has_mappings)) {</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;dmar_domain-&gt;lock, flags);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4399,7 +4212,7 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev)</div><div class='ctx'> 	u8 bus, devfn;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	iommu = device_to_iommu(dev, &amp;bus, &amp;devfn);</div><div class='add'>+	iommu = device_lookup_iommu(dev, &amp;bus, &amp;devfn);</div><div class='ctx'> 	if (!iommu || !iommu-&gt;iommu.ops)</div><div class='ctx'> 		return ERR_PTR(-ENODEV);</div><div class='ctx'> </div><div class='hunk'>@@ -4457,7 +4270,6 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev)</div><div class='ctx'> 		ret = intel_pasid_alloc_table(dev);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "PASID table allocation failed\n");</div><div class='del'>-			dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 			kfree(info);</div><div class='ctx'> 			return ERR_PTR(ret);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4475,7 +4287,6 @@ static void intel_iommu_release_device(struct device *dev)</div><div class='ctx'> 	dmar_remove_one_dev_info(dev);</div><div class='ctx'> 	intel_pasid_free_table(dev);</div><div class='ctx'> 	intel_iommu_debugfs_remove_dev(info);</div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 	kfree(info);</div><div class='ctx'> 	set_dma_ops(dev, NULL);</div><div class='ctx'> }</div><div class='hunk'>@@ -4735,8 +4546,9 @@ static int intel_iommu_iotlb_sync_map(struct iommu_domain *domain,</div><div class='ctx'> </div><div class='ctx'> static void intel_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid)</div><div class='ctx'> {</div><div class='del'>-	struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL);</div><div class='add'>+	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct dev_pasid_info *curr, *dev_pasid = NULL;</div><div class='add'>+	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='ctx'> 	struct dmar_domain *dmar_domain;</div><div class='ctx'> 	struct iommu_domain *domain;</div><div class='ctx'> 	unsigned long flags;</div><div class='hunk'>@@ -4807,8 +4619,7 @@ static int intel_iommu_set_dev_pasid(struct iommu_domain *domain,</div><div class='ctx'> 		goto out_free;</div><div class='ctx'> </div><div class='ctx'> 	if (domain_type_is_si(dmar_domain))</div><div class='del'>-		ret = intel_pasid_setup_pass_through(iommu, dmar_domain,</div><div class='del'>-						     dev, pasid);</div><div class='add'>+		ret = intel_pasid_setup_pass_through(iommu, dev, pasid);</div><div class='ctx'> 	else if (dmar_domain-&gt;use_first_level)</div><div class='ctx'> 		ret = domain_setup_first_level(iommu, dmar_domain,</div><div class='ctx'> 					       dev, pasid);</div><div class='hunk'>@@ -4925,7 +4736,7 @@ static int intel_iommu_read_and_clear_dirty(struct iommu_domain *domain,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct iommu_dirty_ops intel_dirty_ops = {</div><div class='add'>+static const struct iommu_dirty_ops intel_dirty_ops = {</div><div class='ctx'> 	.set_dirty_tracking = intel_iommu_set_dirty_tracking,</div><div class='ctx'> 	.read_and_clear_dirty = intel_iommu_read_and_clear_dirty,</div><div class='ctx'> };</div><div class='hunk'>@@ -5073,7 +4884,7 @@ static void quirk_igfx_skip_te_disable(struct pci_dev *dev)</div><div class='ctx'> 	ver = (dev-&gt;device &gt;&gt; 8) &amp; 0xff;</div><div class='ctx'> 	if (ver != 0x45 &amp;&amp; ver != 0x46 &amp;&amp; ver != 0x4c &amp;&amp;</div><div class='ctx'> 	    ver != 0x4e &amp;&amp; ver != 0x8a &amp;&amp; ver != 0x98 &amp;&amp;</div><div class='del'>-	    ver != 0x9a &amp;&amp; ver != 0xa7)</div><div class='add'>+	    ver != 0x9a &amp;&amp; ver != 0xa7 &amp;&amp; ver != 0x7d)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (risky_device(dev))</div><div class='head'>diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h<br/>index 65d37a138c75..d02f916d8e59 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/iommu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/iommu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/iommu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/iommu.h</a></div><div class='hunk'>@@ -140,9 +140,6 @@</div><div class='ctx'> #define DMAR_ECEO_REG		0x408</div><div class='ctx'> #define DMAR_ECRSP_REG		0x410</div><div class='ctx'> #define DMAR_ECCAP_REG		0x430</div><div class='del'>-#define DMAR_VCCAP_REG		0xe30 /* Virtual command capability register */</div><div class='del'>-#define DMAR_VCMD_REG		0xe00 /* Virtual command register */</div><div class='del'>-#define DMAR_VCRSP_REG		0xe10 /* Virtual command response register */</div><div class='ctx'> </div><div class='ctx'> #define DMAR_IQER_REG_IQEI(reg)		FIELD_GET(GENMASK_ULL(3, 0), reg)</div><div class='ctx'> #define DMAR_IQER_REG_ITESID(reg)	FIELD_GET(GENMASK_ULL(47, 32), reg)</div><div class='hunk'>@@ -602,6 +599,9 @@ struct dmar_domain {</div><div class='ctx'> 					 */</div><div class='ctx'> 	u8 dirty_tracking:1;		/* Dirty tracking is enabled */</div><div class='ctx'> 	u8 nested_parent:1;		/* Has other domains nested on it */</div><div class='add'>+	u8 has_mappings:1;		/* Has mappings configured through</div><div class='add'>+					 * iommu_map() interface.</div><div class='add'>+					 */</div><div class='ctx'> </div><div class='ctx'> 	spinlock_t lock;		/* Protect device tracking lists */</div><div class='ctx'> 	struct list_head devices;	/* all devices' list */</div><div class='hunk'>@@ -851,6 +851,181 @@ static inline bool context_present(struct context_entry *context)</div><div class='ctx'> 	return (context-&gt;lo &amp; 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define LEVEL_STRIDE		(9)</div><div class='add'>+#define LEVEL_MASK		(((u64)1 &lt;&lt; LEVEL_STRIDE) - 1)</div><div class='add'>+#define MAX_AGAW_WIDTH		(64)</div><div class='add'>+#define MAX_AGAW_PFN_WIDTH	(MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)</div><div class='add'>+</div><div class='add'>+static inline int agaw_to_level(int agaw)</div><div class='add'>+{</div><div class='add'>+	return agaw + 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int agaw_to_width(int agaw)</div><div class='add'>+{</div><div class='add'>+	return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int width_to_agaw(int width)</div><div class='add'>+{</div><div class='add'>+	return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline unsigned int level_to_offset_bits(int level)</div><div class='add'>+{</div><div class='add'>+	return (level - 1) * LEVEL_STRIDE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int pfn_level_offset(u64 pfn, int level)</div><div class='add'>+{</div><div class='add'>+	return (pfn &gt;&gt; level_to_offset_bits(level)) &amp; LEVEL_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 level_mask(int level)</div><div class='add'>+{</div><div class='add'>+	return -1ULL &lt;&lt; level_to_offset_bits(level);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 level_size(int level)</div><div class='add'>+{</div><div class='add'>+	return 1ULL &lt;&lt; level_to_offset_bits(level);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 align_to_level(u64 pfn, int level)</div><div class='add'>+{</div><div class='add'>+	return (pfn + level_size(level) - 1) &amp; level_mask(level);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline unsigned long lvl_to_nr_pages(unsigned int lvl)</div><div class='add'>+{</div><div class='add'>+	return 1UL &lt;&lt; min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* VT-d pages must always be _smaller_ than MM pages. Otherwise things</div><div class='add'>+   are never going to work. */</div><div class='add'>+static inline unsigned long mm_to_dma_pfn_start(unsigned long mm_pfn)</div><div class='add'>+{</div><div class='add'>+	return mm_pfn &lt;&lt; (PAGE_SHIFT - VTD_PAGE_SHIFT);</div><div class='add'>+}</div><div class='add'>+static inline unsigned long mm_to_dma_pfn_end(unsigned long mm_pfn)</div><div class='add'>+{</div><div class='add'>+	return ((mm_pfn + 1) &lt;&lt; (PAGE_SHIFT - VTD_PAGE_SHIFT)) - 1;</div><div class='add'>+}</div><div class='add'>+static inline unsigned long page_to_dma_pfn(struct page *pg)</div><div class='add'>+{</div><div class='add'>+	return mm_to_dma_pfn_start(page_to_pfn(pg));</div><div class='add'>+}</div><div class='add'>+static inline unsigned long virt_to_dma_pfn(void *p)</div><div class='add'>+{</div><div class='add'>+	return page_to_dma_pfn(virt_to_page(p));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_present(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo |= 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_fault_enable(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo &amp;= (((u64)-1) &lt;&lt; 2) | 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_translation_type(struct context_entry *context,</div><div class='add'>+						unsigned long value)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo &amp;= (((u64)-1) &lt;&lt; 4) | 3;</div><div class='add'>+	context-&gt;lo |= (value &amp; 3) &lt;&lt; 2;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_address_root(struct context_entry *context,</div><div class='add'>+					    unsigned long value)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo &amp;= ~VTD_PAGE_MASK;</div><div class='add'>+	context-&gt;lo |= value &amp; VTD_PAGE_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_address_width(struct context_entry *context,</div><div class='add'>+					     unsigned long value)</div><div class='add'>+{</div><div class='add'>+	context-&gt;hi |= value &amp; 7;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_domain_id(struct context_entry *context,</div><div class='add'>+					 unsigned long value)</div><div class='add'>+{</div><div class='add'>+	context-&gt;hi |= (value &amp; ((1 &lt;&lt; 16) - 1)) &lt;&lt; 8;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_set_pasid(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo |= CONTEXT_PASIDE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int context_domain_id(struct context_entry *c)</div><div class='add'>+{</div><div class='add'>+	return((c-&gt;hi &gt;&gt; 8) &amp; 0xffff);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void context_clear_entry(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo = 0;</div><div class='add'>+	context-&gt;hi = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_INTEL_IOMMU</div><div class='add'>+static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='add'>+{</div><div class='add'>+	if (!iommu-&gt;copied_tables)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return test_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='add'>+{</div><div class='add'>+	set_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn)</div><div class='add'>+{</div><div class='add'>+	clear_bit(((long)bus &lt;&lt; 8) | devfn, iommu-&gt;copied_tables);</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_INTEL_IOMMU */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Set the RID_PASID field of a scalable mode context entry. The</div><div class='add'>+ * IOMMU hardware will use the PASID value set in this field for</div><div class='add'>+ * DMA translations of DMA requests without PASID.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+context_set_sm_rid2pasid(struct context_entry *context, unsigned long pasid)</div><div class='add'>+{</div><div class='add'>+	context-&gt;hi |= pasid &amp; ((1 &lt;&lt; 20) - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Set the DTE(Device-TLB Enable) field of a scalable mode context</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void context_set_sm_dte(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo |= BIT_ULL(2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Set the PRE(Page Request Enable) field of a scalable mode context</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void context_set_sm_pre(struct context_entry *context)</div><div class='add'>+{</div><div class='add'>+	context-&gt;lo |= BIT_ULL(4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Convert value to context PASID directory size field coding. */</div><div class='add'>+#define context_pdts(pds)	(((pds) &amp; 0x7) &lt;&lt; 9)</div><div class='add'>+</div><div class='ctx'> struct dmar_drhd_unit *dmar_find_matched_drhd_unit(struct pci_dev *dev);</div><div class='ctx'> </div><div class='ctx'> int dmar_enable_qi(struct intel_iommu *iommu);</div><div class='hunk'>@@ -897,7 +1072,6 @@ int dmar_ir_support(void);</div><div class='ctx'> void *alloc_pgtable_page(int node, gfp_t gfp);</div><div class='ctx'> void free_pgtable_page(void *vaddr);</div><div class='ctx'> void iommu_flush_write_buffer(struct intel_iommu *iommu);</div><div class='del'>-struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn);</div><div class='ctx'> struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,</div><div class='ctx'> 					       const struct iommu_user_data *user_data);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c<br/>index 29b9e55dcf26..566297bc87dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/irq_remapping.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/irq_remapping.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/irq_remapping.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/irq_remapping.c</a></div><div class='hunk'>@@ -1112,7 +1112,7 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest)</div><div class='ctx'> 	 * irq migration in the presence of interrupt-remapping.</div><div class='ctx'> 	*/</div><div class='ctx'> 	irte-&gt;trigger_mode = 0;</div><div class='del'>-	irte-&gt;dlvry_mode = apic-&gt;delivery_mode;</div><div class='add'>+	irte-&gt;dlvry_mode = APIC_DELIVERY_MODE_FIXED;</div><div class='ctx'> 	irte-&gt;vector = vector;</div><div class='ctx'> 	irte-&gt;dest_id = IRTE_DEST(dest);</div><div class='ctx'> 	irte-&gt;redir_hint = 1;</div><div class='head'>diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c<br/>index b5a5563ab32c..f26c7f1c46cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/nested.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/nested.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/nested.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/nested.c</a></div><div class='hunk'>@@ -73,9 +73,97 @@ static void intel_nested_domain_free(struct iommu_domain *domain)</div><div class='ctx'> 	kfree(to_dmar_domain(domain));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nested_flush_dev_iotlb(struct dmar_domain *domain, u64 addr,</div><div class='add'>+				   unsigned int mask)</div><div class='add'>+{</div><div class='add'>+	struct device_domain_info *info;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	u16 sid, qdep;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;domain-&gt;lock, flags);</div><div class='add'>+	list_for_each_entry(info, &amp;domain-&gt;devices, link) {</div><div class='add'>+		if (!info-&gt;ats_enabled)</div><div class='add'>+			continue;</div><div class='add'>+		sid = info-&gt;bus &lt;&lt; 8 | info-&gt;devfn;</div><div class='add'>+		qdep = info-&gt;ats_qdep;</div><div class='add'>+		qi_flush_dev_iotlb(info-&gt;iommu, sid, info-&gt;pfsid,</div><div class='add'>+				   qdep, addr, mask);</div><div class='add'>+		quirk_extra_dev_tlb_flush(info, addr, mask,</div><div class='add'>+					  IOMMU_NO_PASID, qdep);</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;domain-&gt;lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void intel_nested_flush_cache(struct dmar_domain *domain, u64 addr,</div><div class='add'>+				     unsigned long npages, bool ih)</div><div class='add'>+{</div><div class='add'>+	struct iommu_domain_info *info;</div><div class='add'>+	unsigned int mask;</div><div class='add'>+	unsigned long i;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;domain-&gt;iommu_array, i, info)</div><div class='add'>+		qi_flush_piotlb(info-&gt;iommu,</div><div class='add'>+				domain_id_iommu(domain, info-&gt;iommu),</div><div class='add'>+				IOMMU_NO_PASID, addr, npages, ih);</div><div class='add'>+</div><div class='add'>+	if (!domain-&gt;has_iotlb_device)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (npages == U64_MAX)</div><div class='add'>+		mask = 64 - VTD_PAGE_SHIFT;</div><div class='add'>+	else</div><div class='add'>+		mask = ilog2(__roundup_pow_of_two(npages));</div><div class='add'>+</div><div class='add'>+	nested_flush_dev_iotlb(domain, addr, mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int intel_nested_cache_invalidate_user(struct iommu_domain *domain,</div><div class='add'>+					      struct iommu_user_data_array *array)</div><div class='add'>+{</div><div class='add'>+	struct dmar_domain *dmar_domain = to_dmar_domain(domain);</div><div class='add'>+	struct iommu_hwpt_vtd_s1_invalidate inv_entry;</div><div class='add'>+	u32 index, processed = 0;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (array-&gt;type != IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (index = 0; index &lt; array-&gt;entry_num; index++) {</div><div class='add'>+		ret = iommu_copy_struct_from_user_array(&amp;inv_entry, array,</div><div class='add'>+							IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,</div><div class='add'>+							index, __reserved);</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if ((inv_entry.flags &amp; ~IOMMU_VTD_INV_FLAGS_LEAF) ||</div><div class='add'>+		    inv_entry.__reserved) {</div><div class='add'>+			ret = -EOPNOTSUPP;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!IS_ALIGNED(inv_entry.addr, VTD_PAGE_SIZE) ||</div><div class='add'>+		    ((inv_entry.npages == U64_MAX) &amp;&amp; inv_entry.addr)) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		intel_nested_flush_cache(dmar_domain, inv_entry.addr,</div><div class='add'>+					 inv_entry.npages,</div><div class='add'>+					 inv_entry.flags &amp; IOMMU_VTD_INV_FLAGS_LEAF);</div><div class='add'>+		processed++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	array-&gt;entry_num = processed;</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct iommu_domain_ops intel_nested_domain_ops = {</div><div class='ctx'> 	.attach_dev		= intel_nested_attach_dev,</div><div class='ctx'> 	.free			= intel_nested_domain_free,</div><div class='add'>+	.cache_invalidate_user	= intel_nested_cache_invalidate_user,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,</div><div class='head'>diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c<br/>index 74e8e4c17e81..3239cefa4c33 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/pasid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/pasid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/pasid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/pasid.c</a></div><div class='hunk'>@@ -26,63 +26,6 @@</div><div class='ctx'>  */</div><div class='ctx'> u32 intel_pasid_max_id = PASID_MAX;</div><div class='ctx'> </div><div class='del'>-int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	u8 status_code;</div><div class='del'>-	int ret = 0;</div><div class='del'>-	u64 res;</div><div class='del'>-</div><div class='del'>-	raw_spin_lock_irqsave(&amp;iommu-&gt;register_lock, flags);</div><div class='del'>-	dmar_writeq(iommu-&gt;reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC);</div><div class='del'>-	IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,</div><div class='del'>-		      !(res &amp; VCMD_VRSP_IP), res);</div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;iommu-&gt;register_lock, flags);</div><div class='del'>-</div><div class='del'>-	status_code = VCMD_VRSP_SC(res);</div><div class='del'>-	switch (status_code) {</div><div class='del'>-	case VCMD_VRSP_SC_SUCCESS:</div><div class='del'>-		*pasid = VCMD_VRSP_RESULT_PASID(res);</div><div class='del'>-		break;</div><div class='del'>-	case VCMD_VRSP_SC_NO_PASID_AVAIL:</div><div class='del'>-		pr_info("IOMMU: %s: No PASID available\n", iommu-&gt;name);</div><div class='del'>-		ret = -ENOSPC;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		ret = -ENODEV;</div><div class='del'>-		pr_warn("IOMMU: %s: Unexpected error code %d\n",</div><div class='del'>-			iommu-&gt;name, status_code);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	u8 status_code;</div><div class='del'>-	u64 res;</div><div class='del'>-</div><div class='del'>-	raw_spin_lock_irqsave(&amp;iommu-&gt;register_lock, flags);</div><div class='del'>-	dmar_writeq(iommu-&gt;reg + DMAR_VCMD_REG,</div><div class='del'>-		    VCMD_CMD_OPERAND(pasid) | VCMD_CMD_FREE);</div><div class='del'>-	IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,</div><div class='del'>-		      !(res &amp; VCMD_VRSP_IP), res);</div><div class='del'>-	raw_spin_unlock_irqrestore(&amp;iommu-&gt;register_lock, flags);</div><div class='del'>-</div><div class='del'>-	status_code = VCMD_VRSP_SC(res);</div><div class='del'>-	switch (status_code) {</div><div class='del'>-	case VCMD_VRSP_SC_SUCCESS:</div><div class='del'>-		break;</div><div class='del'>-	case VCMD_VRSP_SC_INVALID_PASID:</div><div class='del'>-		pr_info("IOMMU: %s: Invalid PASID\n", iommu-&gt;name);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		pr_warn("IOMMU: %s: Unexpected error code %d\n",</div><div class='del'>-			iommu-&gt;name, status_code);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Per device pasid table management:</div><div class='ctx'>  */</div><div class='hunk'>@@ -230,30 +173,6 @@ retry:</div><div class='ctx'> /*</div><div class='ctx'>  * Interfaces for PASID table entry manipulation:</div><div class='ctx'>  */</div><div class='del'>-static inline void pasid_clear_entry(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[0], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[1], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[2], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[3], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[4], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[5], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[6], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[7], 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[0], PASID_PTE_FPD);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[1], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[2], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[3], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[4], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[5], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[6], 0);</div><div class='del'>-	WRITE_ONCE(pe-&gt;val[7], 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void</div><div class='ctx'> intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore)</div><div class='ctx'> {</div><div class='hunk'>@@ -269,192 +188,6 @@ intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore)</div><div class='ctx'> 		pasid_clear_entry(pe);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)</div><div class='del'>-{</div><div class='del'>-	u64 old;</div><div class='del'>-</div><div class='del'>-	old = READ_ONCE(*ptr);</div><div class='del'>-	WRITE_ONCE(*ptr, (old &amp; ~mask) | bits);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u64 pasid_get_bits(u64 *ptr)</div><div class='del'>-{</div><div class='del'>-	return READ_ONCE(*ptr);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode</div><div class='del'>- * PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_domain_id(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[1], GENMASK_ULL(15, 0), value);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Get domain ID value of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline u16</div><div class='del'>-pasid_get_domain_id(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	return (u16)(READ_ONCE(pe-&gt;val[1]) &amp; GENMASK_ULL(15, 0));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)</div><div class='del'>- * of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_slptr(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], VTD_PAGE_MASK, value);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_address_width(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], GENMASK_ULL(4, 2), value &lt;&lt; 2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)</div><div class='del'>- * of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_translation_type(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], GENMASK_ULL(8, 6), value &lt;&lt; 6);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Enable fault processing by clearing the FPD(Fault Processing</div><div class='del'>- * Disable) field (Bit 1) of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_fault_enable(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 1, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Enable second level A/D bits by setting the SLADE (Second Level</div><div class='del'>- * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_ssade(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 9, 1 &lt;&lt; 9);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Disable second level A/D bits by clearing the SLADE (Second Level</div><div class='del'>- * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_clear_ssade(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 9, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Checks if second level A/D bits specifically the SLADE (Second Level</div><div class='del'>- * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='del'>- * entry is set.</div><div class='del'>- */</div><div class='del'>-static inline bool pasid_get_ssade(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	return pasid_get_bits(&amp;pe-&gt;val[0]) &amp; (1 &lt;&lt; 9);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a</div><div class='del'>- * scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_sre(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 0, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the WPE(Write Protect Enable) field (Bit 132) of a</div><div class='del'>- * scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_wpe(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 4, 1 &lt;&lt; 4);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the P(Present) field (Bit 0) of a scalable mode PASID</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_present(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 0, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID</div><div class='del'>- * entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[1], 1 &lt;&lt; 23, value &lt;&lt; 23);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID</div><div class='del'>- * entry. It is required when XD bit of the first level page table</div><div class='del'>- * entry is about to be set.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_nxe(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 5, 1 &lt;&lt; 5);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode</div><div class='del'>- * PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_pgsnp(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[1], 1ULL &lt;&lt; 24, 1ULL &lt;&lt; 24);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the First Level Page table Pointer field (Bit 140~191)</div><div class='del'>- * of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_flptr(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], VTD_PAGE_MASK, value);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the First Level Paging Mode field (Bit 130~131) of a</div><div class='del'>- * scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void</div><div class='del'>-pasid_set_flpm(struct pasid_entry *pe, u64 value)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], GENMASK_ULL(3, 2), value &lt;&lt; 2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Setup the Extended Access Flag Enable (EAFE) field (Bit 135)</div><div class='del'>- * of a scalable mode PASID entry.</div><div class='del'>- */</div><div class='del'>-static inline void pasid_set_eafe(struct pasid_entry *pe)</div><div class='del'>-{</div><div class='del'>-	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 7, 1 &lt;&lt; 7);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void</div><div class='ctx'> pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,</div><div class='ctx'> 				    u16 did, u32 pasid)</div><div class='hunk'>@@ -613,9 +346,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,</div><div class='ctx'>  * Skip top levels of page tables for iommu which has less agaw</div><div class='ctx'>  * than default. Unnecessary for PT mode.</div><div class='ctx'>  */</div><div class='del'>-static inline int iommu_skip_agaw(struct dmar_domain *domain,</div><div class='del'>-				  struct intel_iommu *iommu,</div><div class='del'>-				  struct dma_pte **pgd)</div><div class='add'>+static int iommu_skip_agaw(struct dmar_domain *domain,</div><div class='add'>+			   struct intel_iommu *iommu,</div><div class='add'>+			   struct dma_pte **pgd)</div><div class='ctx'> {</div><div class='ctx'> 	int agaw;</div><div class='ctx'> </div><div class='hunk'>@@ -767,7 +500,6 @@ int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu,</div><div class='ctx'>  * Set up the scalable mode pasid entry for passthrough translation type.</div><div class='ctx'>  */</div><div class='ctx'> int intel_pasid_setup_pass_through(struct intel_iommu *iommu,</div><div class='del'>-				   struct dmar_domain *domain,</div><div class='ctx'> 				   struct device *dev, u32 pasid)</div><div class='ctx'> {</div><div class='ctx'> 	u16 did = FLPT_DEFAULT_DID;</div><div class='head'>diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h<br/>index dd37611175cc..8d40d4c66e31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/pasid.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/pasid.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/pasid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/pasid.h</a></div><div class='hunk'>@@ -22,16 +22,6 @@</div><div class='ctx'> #define is_pasid_enabled(entry)		(((entry)-&gt;lo &gt;&gt; 3) &amp; 0x1)</div><div class='ctx'> #define get_pasid_dir_size(entry)	(1 &lt;&lt; ((((entry)-&gt;lo &gt;&gt; 9) &amp; 0x7) + 7))</div><div class='ctx'> </div><div class='del'>-/* Virtual command interface for enlightened pasid management. */</div><div class='del'>-#define VCMD_CMD_ALLOC			0x1</div><div class='del'>-#define VCMD_CMD_FREE			0x2</div><div class='del'>-#define VCMD_VRSP_IP			0x1</div><div class='del'>-#define VCMD_VRSP_SC(e)			(((e) &amp; 0xff) &gt;&gt; 1)</div><div class='del'>-#define VCMD_VRSP_SC_SUCCESS		0</div><div class='del'>-#define VCMD_VRSP_SC_NO_PASID_AVAIL	16</div><div class='del'>-#define VCMD_VRSP_SC_INVALID_PASID	16</div><div class='del'>-#define VCMD_VRSP_RESULT_PASID(e)	(((e) &gt;&gt; 16) &amp; 0xfffff)</div><div class='del'>-#define VCMD_CMD_OPERAND(e)		((e) &lt;&lt; 16)</div><div class='ctx'> /*</div><div class='ctx'>  * Domain ID reserved for pasid entries programmed for first-level</div><div class='ctx'>  * only and pass-through transfer modes.</div><div class='hunk'>@@ -96,6 +86,216 @@ static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte)</div><div class='ctx'> 	return (u16)((READ_ONCE(pte-&gt;val[0]) &gt;&gt; 6) &amp; 0x7);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void pasid_clear_entry(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[0], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[1], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[2], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[3], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[4], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[5], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[6], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[7], 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[0], PASID_PTE_FPD);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[1], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[2], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[3], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[4], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[5], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[6], 0);</div><div class='add'>+	WRITE_ONCE(pe-&gt;val[7], 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)</div><div class='add'>+{</div><div class='add'>+	u64 old;</div><div class='add'>+</div><div class='add'>+	old = READ_ONCE(*ptr);</div><div class='add'>+	WRITE_ONCE(*ptr, (old &amp; ~mask) | bits);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u64 pasid_get_bits(u64 *ptr)</div><div class='add'>+{</div><div class='add'>+	return READ_ONCE(*ptr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode</div><div class='add'>+ * PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_domain_id(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[1], GENMASK_ULL(15, 0), value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Get domain ID value of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline u16</div><div class='add'>+pasid_get_domain_id(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	return (u16)(READ_ONCE(pe-&gt;val[1]) &amp; GENMASK_ULL(15, 0));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)</div><div class='add'>+ * of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_slptr(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], VTD_PAGE_MASK, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_address_width(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], GENMASK_ULL(4, 2), value &lt;&lt; 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)</div><div class='add'>+ * of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_translation_type(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], GENMASK_ULL(8, 6), value &lt;&lt; 6);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Enable fault processing by clearing the FPD(Fault Processing</div><div class='add'>+ * Disable) field (Bit 1) of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_fault_enable(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 1, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Enable second level A/D bits by setting the SLADE (Second Level</div><div class='add'>+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_ssade(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 9, 1 &lt;&lt; 9);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Disable second level A/D bits by clearing the SLADE (Second Level</div><div class='add'>+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_clear_ssade(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 9, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Checks if second level A/D bits specifically the SLADE (Second Level</div><div class='add'>+ * Access Dirty Enable) field (Bit 9) of a scalable mode PASID</div><div class='add'>+ * entry is set.</div><div class='add'>+ */</div><div class='add'>+static inline bool pasid_get_ssade(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	return pasid_get_bits(&amp;pe-&gt;val[0]) &amp; (1 &lt;&lt; 9);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a</div><div class='add'>+ * scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_sre(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 0, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the WPE(Write Protect Enable) field (Bit 132) of a</div><div class='add'>+ * scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_wpe(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 4, 1 &lt;&lt; 4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the P(Present) field (Bit 0) of a scalable mode PASID</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_present(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[0], 1 &lt;&lt; 0, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID</div><div class='add'>+ * entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[1], 1 &lt;&lt; 23, value &lt;&lt; 23);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID</div><div class='add'>+ * entry. It is required when XD bit of the first level page table</div><div class='add'>+ * entry is about to be set.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_nxe(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 5, 1 &lt;&lt; 5);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode</div><div class='add'>+ * PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_pgsnp(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[1], 1ULL &lt;&lt; 24, 1ULL &lt;&lt; 24);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the First Level Page table Pointer field (Bit 140~191)</div><div class='add'>+ * of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_flptr(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], VTD_PAGE_MASK, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the First Level Paging Mode field (Bit 130~131) of a</div><div class='add'>+ * scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+pasid_set_flpm(struct pasid_entry *pe, u64 value)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], GENMASK_ULL(3, 2), value &lt;&lt; 2);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Setup the Extended Access Flag Enable (EAFE) field (Bit 135)</div><div class='add'>+ * of a scalable mode PASID entry.</div><div class='add'>+ */</div><div class='add'>+static inline void pasid_set_eafe(struct pasid_entry *pe)</div><div class='add'>+{</div><div class='add'>+	pasid_set_bits(&amp;pe-&gt;val[2], 1 &lt;&lt; 7, 1 &lt;&lt; 7);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> extern unsigned int intel_pasid_max_id;</div><div class='ctx'> int intel_pasid_alloc_table(struct device *dev);</div><div class='ctx'> void intel_pasid_free_table(struct device *dev);</div><div class='hunk'>@@ -111,15 +311,12 @@ int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu,</div><div class='ctx'> 				     struct device *dev, u32 pasid,</div><div class='ctx'> 				     bool enabled);</div><div class='ctx'> int intel_pasid_setup_pass_through(struct intel_iommu *iommu,</div><div class='del'>-				   struct dmar_domain *domain,</div><div class='ctx'> 				   struct device *dev, u32 pasid);</div><div class='ctx'> int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,</div><div class='ctx'> 			     u32 pasid, struct dmar_domain *domain);</div><div class='ctx'> void intel_pasid_tear_down_entry(struct intel_iommu *iommu,</div><div class='ctx'> 				 struct device *dev, u32 pasid,</div><div class='ctx'> 				 bool fault_ignore);</div><div class='del'>-int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid);</div><div class='del'>-void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid);</div><div class='ctx'> void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,</div><div class='ctx'> 					  struct device *dev, u32 pasid);</div><div class='ctx'> #endif /* __INTEL_PASID_H */</div><div class='head'>diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c<br/>index 50a481c895b8..40edd282903f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/intel/svm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/intel/svm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/intel/svm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/intel/svm.c</a></div><div class='hunk'>@@ -216,6 +216,27 @@ static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,</div><div class='ctx'> 	rcu_read_unlock();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void intel_flush_svm_all(struct intel_svm *svm)</div><div class='add'>+{</div><div class='add'>+	struct device_domain_info *info;</div><div class='add'>+	struct intel_svm_dev *sdev;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	list_for_each_entry_rcu(sdev, &amp;svm-&gt;devs, list) {</div><div class='add'>+		info = dev_iommu_priv_get(sdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+		qi_flush_piotlb(sdev-&gt;iommu, sdev-&gt;did, svm-&gt;pasid, 0, -1UL, 0);</div><div class='add'>+		if (info-&gt;ats_enabled) {</div><div class='add'>+			qi_flush_dev_iotlb_pasid(sdev-&gt;iommu, sdev-&gt;sid, info-&gt;pfsid,</div><div class='add'>+						 svm-&gt;pasid, sdev-&gt;qdep,</div><div class='add'>+						 0, 64 - VTD_PAGE_SHIFT);</div><div class='add'>+			quirk_extra_dev_tlb_flush(info, 0, 64 - VTD_PAGE_SHIFT,</div><div class='add'>+						  svm-&gt;pasid, sdev-&gt;qdep);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Pages have been freed at this point */</div><div class='ctx'> static void intel_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn,</div><div class='ctx'> 					struct mm_struct *mm,</div><div class='hunk'>@@ -223,6 +244,11 @@ static void intel_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn,</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);</div><div class='ctx'> </div><div class='add'>+	if (start == 0 &amp;&amp; end == -1UL) {</div><div class='add'>+		intel_flush_svm_all(svm);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	intel_flush_svm_range(svm, start,</div><div class='ctx'> 			      (end - start + PAGE_SIZE - 1) &gt;&gt; VTD_PAGE_SHIFT, 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -290,21 +316,22 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int intel_svm_bind_mm(struct intel_iommu *iommu, struct device *dev,</div><div class='del'>-			     struct mm_struct *mm)</div><div class='add'>+			     struct iommu_domain *domain, ioasid_t pasid)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='add'>+	struct mm_struct *mm = domain-&gt;mm;</div><div class='ctx'> 	struct intel_svm_dev *sdev;</div><div class='ctx'> 	struct intel_svm *svm;</div><div class='ctx'> 	unsigned long sflags;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	svm = pasid_private_find(mm-&gt;pasid);</div><div class='add'>+	svm = pasid_private_find(pasid);</div><div class='ctx'> 	if (!svm) {</div><div class='ctx'> 		svm = kzalloc(sizeof(*svm), GFP_KERNEL);</div><div class='ctx'> 		if (!svm)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-		svm-&gt;pasid = mm-&gt;pasid;</div><div class='add'>+		svm-&gt;pasid = pasid;</div><div class='ctx'> 		svm-&gt;mm = mm;</div><div class='ctx'> 		INIT_LIST_HEAD_RCU(&amp;svm-&gt;devs);</div><div class='ctx'> </div><div class='hunk'>@@ -342,7 +369,7 @@ static int intel_svm_bind_mm(struct intel_iommu *iommu, struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	/* Setup the pasid table: */</div><div class='ctx'> 	sflags = cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0;</div><div class='del'>-	ret = intel_pasid_setup_first_level(iommu, dev, mm-&gt;pgd, mm-&gt;pasid,</div><div class='add'>+	ret = intel_pasid_setup_first_level(iommu, dev, mm-&gt;pgd, pasid,</div><div class='ctx'> 					    FLPT_DEFAULT_DID, sflags);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto free_sdev;</div><div class='hunk'>@@ -356,7 +383,7 @@ free_sdev:</div><div class='ctx'> free_svm:</div><div class='ctx'> 	if (list_empty(&amp;svm-&gt;devs)) {</div><div class='ctx'> 		mmu_notifier_unregister(&amp;svm-&gt;notifier, mm);</div><div class='del'>-		pasid_private_remove(mm-&gt;pasid);</div><div class='add'>+		pasid_private_remove(pasid);</div><div class='ctx'> 		kfree(svm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -366,14 +393,9 @@ free_svm:</div><div class='ctx'> void intel_svm_remove_dev_pasid(struct device *dev, u32 pasid)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_svm_dev *sdev;</div><div class='del'>-	struct intel_iommu *iommu;</div><div class='ctx'> 	struct intel_svm *svm;</div><div class='ctx'> 	struct mm_struct *mm;</div><div class='ctx'> </div><div class='del'>-	iommu = device_to_iommu(dev, NULL, NULL);</div><div class='del'>-	if (!iommu)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (pasid_to_svm_sdev(dev, pasid, &amp;svm, &amp;sdev))</div><div class='ctx'> 		return;</div><div class='ctx'> 	mm = svm-&gt;mm;</div><div class='hunk'>@@ -724,25 +746,16 @@ int intel_svm_page_response(struct device *dev,</div><div class='ctx'> 			    struct iommu_fault_event *evt,</div><div class='ctx'> 			    struct iommu_page_response *msg)</div><div class='ctx'> {</div><div class='add'>+	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='add'>+	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='add'>+	u8 bus = info-&gt;bus, devfn = info-&gt;devfn;</div><div class='ctx'> 	struct iommu_fault_page_request *prm;</div><div class='del'>-	struct intel_iommu *iommu;</div><div class='ctx'> 	bool private_present;</div><div class='ctx'> 	bool pasid_present;</div><div class='ctx'> 	bool last_page;</div><div class='del'>-	u8 bus, devfn;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> 	u16 sid;</div><div class='ctx'> </div><div class='del'>-	if (!dev || !dev_is_pci(dev))</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	iommu = device_to_iommu(dev, &amp;bus, &amp;devfn);</div><div class='del'>-	if (!iommu)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	if (!msg || !evt)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	prm = &amp;evt-&gt;fault.prm;</div><div class='ctx'> 	sid = PCI_DEVID(bus, devfn);</div><div class='ctx'> 	pasid_present = prm-&gt;flags &amp; IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;</div><div class='hunk'>@@ -796,9 +809,8 @@ static int intel_svm_set_dev_pasid(struct iommu_domain *domain,</div><div class='ctx'> {</div><div class='ctx'> 	struct device_domain_info *info = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct intel_iommu *iommu = info-&gt;iommu;</div><div class='del'>-	struct mm_struct *mm = domain-&gt;mm;</div><div class='ctx'> </div><div class='del'>-	return intel_svm_bind_mm(iommu, dev, mm);</div><div class='add'>+	return intel_svm_bind_mm(iommu, dev, domain, pasid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void intel_svm_domain_free(struct iommu_domain *domain)</div><div class='head'>diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c<br/>index 72dcdd468cf3..f7828a7aad41 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/io-pgtable-arm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/io-pgtable-arm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/io-pgtable-arm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/io-pgtable-arm.c</a></div><div class='hunk'>@@ -188,20 +188,28 @@ static dma_addr_t __arm_lpae_dma_addr(void *pages)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,</div><div class='del'>-				    struct io_pgtable_cfg *cfg)</div><div class='add'>+				    struct io_pgtable_cfg *cfg,</div><div class='add'>+				    void *cookie)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = cfg-&gt;iommu_dev;</div><div class='ctx'> 	int order = get_order(size);</div><div class='del'>-	struct page *p;</div><div class='ctx'> 	dma_addr_t dma;</div><div class='ctx'> 	void *pages;</div><div class='ctx'> </div><div class='ctx'> 	VM_BUG_ON((gfp &amp; __GFP_HIGHMEM));</div><div class='del'>-	p = alloc_pages_node(dev_to_node(dev), gfp | __GFP_ZERO, order);</div><div class='del'>-	if (!p)</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;alloc) {</div><div class='add'>+		pages = cfg-&gt;alloc(cookie, size, gfp);</div><div class='add'>+	} else {</div><div class='add'>+		struct page *p;</div><div class='add'>+</div><div class='add'>+		p = alloc_pages_node(dev_to_node(dev), gfp | __GFP_ZERO, order);</div><div class='add'>+		pages = p ? page_address(p) : NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!pages)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	pages = page_address(p);</div><div class='ctx'> 	if (!cfg-&gt;coherent_walk) {</div><div class='ctx'> 		dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);</div><div class='ctx'> 		if (dma_mapping_error(dev, dma))</div><div class='hunk'>@@ -220,18 +228,28 @@ static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,</div><div class='ctx'> out_unmap:</div><div class='ctx'> 	dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");</div><div class='ctx'> 	dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);</div><div class='add'>+</div><div class='ctx'> out_free:</div><div class='del'>-	__free_pages(p, order);</div><div class='add'>+	if (cfg-&gt;free)</div><div class='add'>+		cfg-&gt;free(cookie, pages, size);</div><div class='add'>+	else</div><div class='add'>+		free_pages((unsigned long)pages, order);</div><div class='add'>+</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __arm_lpae_free_pages(void *pages, size_t size,</div><div class='del'>-				  struct io_pgtable_cfg *cfg)</div><div class='add'>+				  struct io_pgtable_cfg *cfg,</div><div class='add'>+				  void *cookie)</div><div class='ctx'> {</div><div class='ctx'> 	if (!cfg-&gt;coherent_walk)</div><div class='ctx'> 		dma_unmap_single(cfg-&gt;iommu_dev, __arm_lpae_dma_addr(pages),</div><div class='ctx'> 				 size, DMA_TO_DEVICE);</div><div class='del'>-	free_pages((unsigned long)pages, get_order(size));</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;free)</div><div class='add'>+		cfg-&gt;free(cookie, pages, size);</div><div class='add'>+	else</div><div class='add'>+		free_pages((unsigned long)pages, get_order(size));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries,</div><div class='hunk'>@@ -373,13 +391,13 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,</div><div class='ctx'> 	/* Grab a pointer to the next level */</div><div class='ctx'> 	pte = READ_ONCE(*ptep);</div><div class='ctx'> 	if (!pte) {</div><div class='del'>-		cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg);</div><div class='add'>+		cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg, data-&gt;iop.cookie);</div><div class='ctx'> 		if (!cptep)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 		pte = arm_lpae_install_table(cptep, ptep, 0, data);</div><div class='ctx'> 		if (pte)</div><div class='del'>-			__arm_lpae_free_pages(cptep, tblsz, cfg);</div><div class='add'>+			__arm_lpae_free_pages(cptep, tblsz, cfg, data-&gt;iop.cookie);</div><div class='ctx'> 	} else if (!cfg-&gt;coherent_walk &amp;&amp; !(pte &amp; ARM_LPAE_PTE_SW_SYNC)) {</div><div class='ctx'> 		__arm_lpae_sync_pte(ptep, 1, cfg);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -524,7 +542,7 @@ static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,</div><div class='ctx'> 		__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	__arm_lpae_free_pages(start, table_size, &amp;data-&gt;iop.cfg);</div><div class='add'>+	__arm_lpae_free_pages(start, table_size, &amp;data-&gt;iop.cfg, data-&gt;iop.cookie);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void arm_lpae_free_pgtable(struct io_pgtable *iop)</div><div class='hunk'>@@ -552,7 +570,7 @@ static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,</div><div class='ctx'> 	if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg);</div><div class='add'>+	tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg, data-&gt;iop.cookie);</div><div class='ctx'> 	if (!tablep)</div><div class='ctx'> 		return 0; /* Bytes unmapped */</div><div class='ctx'> </div><div class='hunk'>@@ -575,7 +593,7 @@ static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,</div><div class='ctx'> </div><div class='ctx'> 	pte = arm_lpae_install_table(tablep, ptep, blk_pte, data);</div><div class='ctx'> 	if (pte != blk_pte) {</div><div class='del'>-		__arm_lpae_free_pages(tablep, tablesz, cfg);</div><div class='add'>+		__arm_lpae_free_pages(tablep, tablesz, cfg, data-&gt;iop.cookie);</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * We may race against someone unmapping another part of this</div><div class='ctx'> 		 * block, but anything else is invalid. We can't misinterpret</div><div class='hunk'>@@ -882,7 +900,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)</div><div class='ctx'> </div><div class='ctx'> 	/* Looking good; allocate a pgd */</div><div class='ctx'> 	data-&gt;pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),</div><div class='del'>-					   GFP_KERNEL, cfg);</div><div class='add'>+					   GFP_KERNEL, cfg, cookie);</div><div class='ctx'> 	if (!data-&gt;pgd)</div><div class='ctx'> 		goto out_free_data;</div><div class='ctx'> </div><div class='hunk'>@@ -984,7 +1002,7 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate pgd pages */</div><div class='ctx'> 	data-&gt;pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data),</div><div class='del'>-					   GFP_KERNEL, cfg);</div><div class='add'>+					   GFP_KERNEL, cfg, cookie);</div><div class='ctx'> 	if (!data-&gt;pgd)</div><div class='ctx'> 		goto out_free_data;</div><div class='ctx'> </div><div class='hunk'>@@ -1059,7 +1077,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)</div><div class='ctx'> 		 &lt;&lt; ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), GFP_KERNEL,</div><div class='del'>-					   cfg);</div><div class='add'>+					   cfg, cookie);</div><div class='ctx'> 	if (!data-&gt;pgd)</div><div class='ctx'> 		goto out_free_data;</div><div class='ctx'> </div><div class='hunk'>@@ -1080,26 +1098,31 @@ out_free_data:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {</div><div class='add'>+	.caps	= IO_PGTABLE_CAP_CUSTOM_ALLOCATOR,</div><div class='ctx'> 	.alloc	= arm_64_lpae_alloc_pgtable_s1,</div><div class='ctx'> 	.free	= arm_lpae_free_pgtable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {</div><div class='add'>+	.caps	= IO_PGTABLE_CAP_CUSTOM_ALLOCATOR,</div><div class='ctx'> 	.alloc	= arm_64_lpae_alloc_pgtable_s2,</div><div class='ctx'> 	.free	= arm_lpae_free_pgtable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {</div><div class='add'>+	.caps	= IO_PGTABLE_CAP_CUSTOM_ALLOCATOR,</div><div class='ctx'> 	.alloc	= arm_32_lpae_alloc_pgtable_s1,</div><div class='ctx'> 	.free	= arm_lpae_free_pgtable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {</div><div class='add'>+	.caps	= IO_PGTABLE_CAP_CUSTOM_ALLOCATOR,</div><div class='ctx'> 	.alloc	= arm_32_lpae_alloc_pgtable_s2,</div><div class='ctx'> 	.free	= arm_lpae_free_pgtable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = {</div><div class='add'>+	.caps	= IO_PGTABLE_CAP_CUSTOM_ALLOCATOR,</div><div class='ctx'> 	.alloc	= arm_mali_lpae_alloc_pgtable,</div><div class='ctx'> 	.free	= arm_lpae_free_pgtable,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/iommu/io-pgtable.c b/drivers/iommu/io-pgtable.c<br/>index b843fcd365d2..8841c1487f00 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/io-pgtable.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/io-pgtable.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/io-pgtable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/io-pgtable.c</a></div><div class='hunk'>@@ -34,6 +34,26 @@ io_pgtable_init_table[IO_PGTABLE_NUM_FMTS] = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int check_custom_allocator(enum io_pgtable_fmt fmt,</div><div class='add'>+				  struct io_pgtable_cfg *cfg)</div><div class='add'>+{</div><div class='add'>+	/* No custom allocator, no need to check the format. */</div><div class='add'>+	if (!cfg-&gt;alloc &amp;&amp; !cfg-&gt;free)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* When passing a custom allocator, both the alloc and free</div><div class='add'>+	 * functions should be provided.</div><div class='add'>+	 */</div><div class='add'>+	if (!cfg-&gt;alloc || !cfg-&gt;free)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Make sure the format supports custom allocators. */</div><div class='add'>+	if (io_pgtable_init_table[fmt]-&gt;caps &amp; IO_PGTABLE_CAP_CUSTOM_ALLOCATOR)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,</div><div class='ctx'> 					    struct io_pgtable_cfg *cfg,</div><div class='ctx'> 					    void *cookie)</div><div class='hunk'>@@ -44,6 +64,9 @@ struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,</div><div class='ctx'> 	if (fmt &gt;= IO_PGTABLE_NUM_FMTS)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='add'>+	if (check_custom_allocator(fmt, cfg))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='ctx'> 	fns = io_pgtable_init_table[fmt];</div><div class='ctx'> 	if (!fns)</div><div class='ctx'> 		return NULL;</div><div class='head'>diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c<br/>index b78671a8a914..c3fc9201d0be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommu-sva.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommu-sva.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommu-sva.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommu-sva.c</a></div><div class='hunk'>@@ -12,32 +12,42 @@</div><div class='ctx'> static DEFINE_MUTEX(iommu_sva_lock);</div><div class='ctx'> </div><div class='ctx'> /* Allocate a PASID for the mm within range (inclusive) */</div><div class='del'>-static int iommu_sva_alloc_pasid(struct mm_struct *mm, struct device *dev)</div><div class='add'>+static struct iommu_mm_data *iommu_alloc_mm_data(struct mm_struct *mm, struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	struct iommu_mm_data *iommu_mm;</div><div class='ctx'> 	ioasid_t pasid;</div><div class='del'>-	int ret = 0;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;iommu_sva_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (!arch_pgtable_dma_compat(mm))</div><div class='del'>-		return -EBUSY;</div><div class='add'>+		return ERR_PTR(-EBUSY);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;iommu_sva_lock);</div><div class='add'>+	iommu_mm = mm-&gt;iommu_mm;</div><div class='ctx'> 	/* Is a PASID already associated with this mm? */</div><div class='del'>-	if (mm_valid_pasid(mm)) {</div><div class='del'>-		if (mm-&gt;pasid &gt;= dev-&gt;iommu-&gt;max_pasids)</div><div class='del'>-			ret = -EOVERFLOW;</div><div class='del'>-		goto out;</div><div class='add'>+	if (iommu_mm) {</div><div class='add'>+		if (iommu_mm-&gt;pasid &gt;= dev-&gt;iommu-&gt;max_pasids)</div><div class='add'>+			return ERR_PTR(-EOVERFLOW);</div><div class='add'>+		return iommu_mm;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	iommu_mm = kzalloc(sizeof(struct iommu_mm_data), GFP_KERNEL);</div><div class='add'>+	if (!iommu_mm)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='ctx'> 	pasid = iommu_alloc_global_pasid(dev);</div><div class='ctx'> 	if (pasid == IOMMU_PASID_INVALID) {</div><div class='del'>-		ret = -ENOSPC;</div><div class='del'>-		goto out;</div><div class='add'>+		kfree(iommu_mm);</div><div class='add'>+		return ERR_PTR(-ENOSPC);</div><div class='ctx'> 	}</div><div class='del'>-	mm-&gt;pasid = pasid;</div><div class='del'>-	ret = 0;</div><div class='del'>-out:</div><div class='del'>-	mutex_unlock(&amp;iommu_sva_lock);</div><div class='del'>-	return ret;</div><div class='add'>+	iommu_mm-&gt;pasid = pasid;</div><div class='add'>+	INIT_LIST_HEAD(&amp;iommu_mm-&gt;sva_domains);</div><div class='add'>+	/*</div><div class='add'>+	 * Make sure the write to mm-&gt;iommu_mm is not reordered in front of</div><div class='add'>+	 * initialization to iommu_mm fields. If it does, readers may see a</div><div class='add'>+	 * valid iommu_mm with uninitialized values.</div><div class='add'>+	 */</div><div class='add'>+	smp_store_release(&amp;mm-&gt;iommu_mm, iommu_mm);</div><div class='add'>+	return iommu_mm;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -58,57 +68,60 @@ out:</div><div class='ctx'>  */</div><div class='ctx'> struct iommu_sva *iommu_sva_bind_device(struct device *dev, struct mm_struct *mm)</div><div class='ctx'> {</div><div class='add'>+	struct iommu_mm_data *iommu_mm;</div><div class='ctx'> 	struct iommu_domain *domain;</div><div class='ctx'> 	struct iommu_sva *handle;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;iommu_sva_lock);</div><div class='add'>+</div><div class='ctx'> 	/* Allocate mm-&gt;pasid if necessary. */</div><div class='del'>-	ret = iommu_sva_alloc_pasid(mm, dev);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ERR_PTR(ret);</div><div class='add'>+	iommu_mm = iommu_alloc_mm_data(mm, dev);</div><div class='add'>+	if (IS_ERR(iommu_mm)) {</div><div class='add'>+		ret = PTR_ERR(iommu_mm);</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	handle = kzalloc(sizeof(*handle), GFP_KERNEL);</div><div class='del'>-	if (!handle)</div><div class='del'>-		return ERR_PTR(-ENOMEM);</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;iommu_sva_lock);</div><div class='del'>-	/* Search for an existing domain. */</div><div class='del'>-	domain = iommu_get_domain_for_dev_pasid(dev, mm-&gt;pasid,</div><div class='del'>-						IOMMU_DOMAIN_SVA);</div><div class='del'>-	if (IS_ERR(domain)) {</div><div class='del'>-		ret = PTR_ERR(domain);</div><div class='add'>+	if (!handle) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (domain) {</div><div class='del'>-		domain-&gt;users++;</div><div class='del'>-		goto out;</div><div class='add'>+	/* Search for an existing domain. */</div><div class='add'>+	list_for_each_entry(domain, &amp;mm-&gt;iommu_mm-&gt;sva_domains, next) {</div><div class='add'>+		ret = iommu_attach_device_pasid(domain, dev, iommu_mm-&gt;pasid);</div><div class='add'>+		if (!ret) {</div><div class='add'>+			domain-&gt;users++;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate a new domain and set it on device pasid. */</div><div class='ctx'> 	domain = iommu_sva_domain_alloc(dev, mm);</div><div class='ctx'> 	if (!domain) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='del'>-		goto out_unlock;</div><div class='add'>+		goto out_free_handle;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = iommu_attach_device_pasid(domain, dev, mm-&gt;pasid);</div><div class='add'>+	ret = iommu_attach_device_pasid(domain, dev, iommu_mm-&gt;pasid);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out_free_domain;</div><div class='ctx'> 	domain-&gt;users = 1;</div><div class='add'>+	list_add(&amp;domain-&gt;next, &amp;mm-&gt;iommu_mm-&gt;sva_domains);</div><div class='add'>+</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;iommu_sva_lock);</div><div class='ctx'> 	handle-&gt;dev = dev;</div><div class='ctx'> 	handle-&gt;domain = domain;</div><div class='del'>-</div><div class='ctx'> 	return handle;</div><div class='ctx'> </div><div class='ctx'> out_free_domain:</div><div class='ctx'> 	iommu_domain_free(domain);</div><div class='add'>+out_free_handle:</div><div class='add'>+	kfree(handle);</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;iommu_sva_lock);</div><div class='del'>-	kfree(handle);</div><div class='del'>-</div><div class='ctx'> 	return ERR_PTR(ret);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iommu_sva_bind_device);</div><div class='hunk'>@@ -124,12 +137,13 @@ EXPORT_SYMBOL_GPL(iommu_sva_bind_device);</div><div class='ctx'> void iommu_sva_unbind_device(struct iommu_sva *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_domain *domain = handle-&gt;domain;</div><div class='del'>-	ioasid_t pasid = domain-&gt;mm-&gt;pasid;</div><div class='add'>+	struct iommu_mm_data *iommu_mm = domain-&gt;mm-&gt;iommu_mm;</div><div class='ctx'> 	struct device *dev = handle-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;iommu_sva_lock);</div><div class='add'>+	iommu_detach_device_pasid(domain, dev, iommu_mm-&gt;pasid);</div><div class='ctx'> 	if (--domain-&gt;users == 0) {</div><div class='del'>-		iommu_detach_device_pasid(domain, dev, pasid);</div><div class='add'>+		list_del(&amp;domain-&gt;next);</div><div class='ctx'> 		iommu_domain_free(domain);</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;iommu_sva_lock);</div><div class='hunk'>@@ -141,7 +155,7 @@ u32 iommu_sva_get_pasid(struct iommu_sva *handle)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_domain *domain = handle-&gt;domain;</div><div class='ctx'> </div><div class='del'>-	return domain-&gt;mm-&gt;pasid;</div><div class='add'>+	return mm_get_enqcmd_pasid(domain-&gt;mm);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iommu_sva_get_pasid);</div><div class='ctx'> </div><div class='hunk'>@@ -205,8 +219,11 @@ out_put_mm:</div><div class='ctx'> </div><div class='ctx'> void mm_pasid_drop(struct mm_struct *mm)</div><div class='ctx'> {</div><div class='del'>-	if (likely(!mm_valid_pasid(mm)))</div><div class='add'>+	struct iommu_mm_data *iommu_mm = mm-&gt;iommu_mm;</div><div class='add'>+</div><div class='add'>+	if (!iommu_mm)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	iommu_free_global_pasid(mm-&gt;pasid);</div><div class='add'>+	iommu_free_global_pasid(iommu_mm-&gt;pasid);</div><div class='add'>+	kfree(iommu_mm);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c<br/>index f17a1113f3d6..68e648b55767 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommu.c</a></div><div class='hunk'>@@ -148,7 +148,7 @@ struct iommu_group_attribute iommu_group_attr_##_name =		\</div><div class='ctx'> static LIST_HEAD(iommu_device_list);</div><div class='ctx'> static DEFINE_SPINLOCK(iommu_device_lock);</div><div class='ctx'> </div><div class='del'>-static struct bus_type * const iommu_buses[] = {</div><div class='add'>+static const struct bus_type * const iommu_buses[] = {</div><div class='ctx'> 	&amp;platform_bus_type,</div><div class='ctx'> #ifdef CONFIG_PCI</div><div class='ctx'> 	&amp;pci_bus_type,</div><div class='hunk'>@@ -257,13 +257,6 @@ int iommu_device_register(struct iommu_device *iommu,</div><div class='ctx'> 	/* We need to be able to take module references appropriately */</div><div class='ctx'> 	if (WARN_ON(is_module_address((unsigned long)ops) &amp;&amp; !ops-&gt;owner))</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	/*</div><div class='del'>-	 * Temporarily enforce global restriction to a single driver. This was</div><div class='del'>-	 * already the de-facto behaviour, since any possible combination of</div><div class='del'>-	 * existing drivers would compete for at least the PCI or platform bus.</div><div class='del'>-	 */</div><div class='del'>-	if (iommu_buses[0]-&gt;iommu_ops &amp;&amp; iommu_buses[0]-&gt;iommu_ops != ops)</div><div class='del'>-		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	iommu-&gt;ops = ops;</div><div class='ctx'> 	if (hwdev)</div><div class='hunk'>@@ -273,10 +266,8 @@ int iommu_device_register(struct iommu_device *iommu,</div><div class='ctx'> 	list_add_tail(&amp;iommu-&gt;list, &amp;iommu_device_list);</div><div class='ctx'> 	spin_unlock(&amp;iommu_device_lock);</div><div class='ctx'> </div><div class='del'>-	for (int i = 0; i &lt; ARRAY_SIZE(iommu_buses) &amp;&amp; !err; i++) {</div><div class='del'>-		iommu_buses[i]-&gt;iommu_ops = ops;</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(iommu_buses) &amp;&amp; !err; i++)</div><div class='ctx'> 		err = bus_iommu_probe(iommu_buses[i]);</div><div class='del'>-	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		iommu_device_unregister(iommu);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -329,7 +320,6 @@ int iommu_device_register_bus(struct iommu_device *iommu,</div><div class='ctx'> 	list_add_tail(&amp;iommu-&gt;list, &amp;iommu_device_list);</div><div class='ctx'> 	spin_unlock(&amp;iommu_device_lock);</div><div class='ctx'> </div><div class='del'>-	bus-&gt;iommu_ops = ops;</div><div class='ctx'> 	err = bus_iommu_probe(bus);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		iommu_device_unregister_bus(iommu, bus, nb);</div><div class='hunk'>@@ -344,6 +334,8 @@ static struct dev_iommu *dev_iommu_get(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct dev_iommu *param = dev-&gt;iommu;</div><div class='ctx'> </div><div class='add'>+	lockdep_assert_held(&amp;iommu_probe_device_lock);</div><div class='add'>+</div><div class='ctx'> 	if (param)</div><div class='ctx'> 		return param;</div><div class='ctx'> </div><div class='hunk'>@@ -368,6 +360,15 @@ static void dev_iommu_free(struct device *dev)</div><div class='ctx'> 	kfree(param);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * Internal equivalent of device_iommu_mapped() for when we care that a device</div><div class='add'>+ * actually has API ops, and don't want false positives from VFIO-only groups.</div><div class='add'>+ */</div><div class='add'>+static bool dev_has_iommu(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	return dev-&gt;iommu &amp;&amp; dev-&gt;iommu-&gt;iommu_dev;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static u32 dev_iommu_get_max_pasids(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	u32 max_pasids = 0, bits = 0;</div><div class='hunk'>@@ -386,6 +387,15 @@ static u32 dev_iommu_get_max_pasids(struct device *dev)</div><div class='ctx'> 	return min_t(u32, max_pasids, dev-&gt;iommu-&gt;iommu_dev-&gt;max_pasids);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void dev_iommu_priv_set(struct device *dev, void *priv)</div><div class='add'>+{</div><div class='add'>+	/* FSL_PAMU does something weird */</div><div class='add'>+	if (!IS_ENABLED(CONFIG_FSL_PAMU))</div><div class='add'>+		lockdep_assert_held(&amp;iommu_probe_device_lock);</div><div class='add'>+	dev-&gt;iommu-&gt;priv = priv;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(dev_iommu_priv_set);</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Init the dev-&gt;iommu and dev-&gt;iommu_group in the struct device and get the</div><div class='ctx'>  * driver probed</div><div class='hunk'>@@ -485,14 +495,30 @@ static void iommu_deinit_device(struct device *dev)</div><div class='ctx'> 	dev_iommu_free(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+DEFINE_MUTEX(iommu_probe_device_lock);</div><div class='add'>+</div><div class='ctx'> static int __iommu_probe_device(struct device *dev, struct list_head *group_list)</div><div class='ctx'> {</div><div class='del'>-	const struct iommu_ops *ops = dev-&gt;bus-&gt;iommu_ops;</div><div class='add'>+	const struct iommu_ops *ops;</div><div class='add'>+	struct iommu_fwspec *fwspec;</div><div class='ctx'> 	struct iommu_group *group;</div><div class='del'>-	static DEFINE_MUTEX(iommu_probe_device_lock);</div><div class='ctx'> 	struct group_device *gdev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * For FDT-based systems and ACPI IORT/VIOT, drivers register IOMMU</div><div class='add'>+	 * instances with non-NULL fwnodes, and client devices should have been</div><div class='add'>+	 * identified with a fwspec by this point. Otherwise, we can currently</div><div class='add'>+	 * assume that only one of Intel, AMD, s390, PAMU or legacy SMMUv2 can</div><div class='add'>+	 * be present, and that any of their registered instances has suitable</div><div class='add'>+	 * ops for probing, and thus cheekily co-opt the same mechanism.</div><div class='add'>+	 */</div><div class='add'>+	fwspec = dev_iommu_fwspec_get(dev);</div><div class='add'>+	if (fwspec &amp;&amp; fwspec-&gt;ops)</div><div class='add'>+		ops = fwspec-&gt;ops;</div><div class='add'>+	else</div><div class='add'>+		ops = iommu_ops_from_fwnode(NULL);</div><div class='add'>+</div><div class='ctx'> 	if (!ops)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -502,17 +528,15 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list</div><div class='ctx'> 	 * probably be able to use device_lock() here to minimise the scope,</div><div class='ctx'> 	 * but for now enforcing a simple global ordering is fine.</div><div class='ctx'> 	 */</div><div class='del'>-	mutex_lock(&amp;iommu_probe_device_lock);</div><div class='add'>+	lockdep_assert_held(&amp;iommu_probe_device_lock);</div><div class='ctx'> </div><div class='ctx'> 	/* Device is probed already if in a group */</div><div class='del'>-	if (dev-&gt;iommu_group) {</div><div class='del'>-		ret = 0;</div><div class='del'>-		goto out_unlock;</div><div class='del'>-	}</div><div class='add'>+	if (dev-&gt;iommu_group)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	ret = iommu_init_device(dev, ops);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto out_unlock;</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	group = dev-&gt;iommu_group;</div><div class='ctx'> 	gdev = iommu_group_alloc_device(group, dev);</div><div class='hunk'>@@ -548,7 +572,6 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list</div><div class='ctx'> 			list_add_tail(&amp;group-&gt;entry, group_list);</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;group-&gt;mutex);</div><div class='del'>-	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (dev_is_pci(dev))</div><div class='ctx'> 		iommu_dma_set_pci_32bit_workaround(dev);</div><div class='hunk'>@@ -562,8 +585,6 @@ err_put_group:</div><div class='ctx'> 	iommu_deinit_device(dev);</div><div class='ctx'> 	mutex_unlock(&amp;group-&gt;mutex);</div><div class='ctx'> 	iommu_group_put(group);</div><div class='del'>-out_unlock:</div><div class='del'>-	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -573,7 +594,9 @@ int iommu_probe_device(struct device *dev)</div><div class='ctx'> 	const struct iommu_ops *ops;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;iommu_probe_device_lock);</div><div class='ctx'> 	ret = __iommu_probe_device(dev, NULL);</div><div class='add'>+	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -620,7 +643,7 @@ static void __iommu_group_remove_device(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 		list_del(&amp;device-&gt;list);</div><div class='ctx'> 		__iommu_group_free_device(group, device);</div><div class='del'>-		if (dev-&gt;iommu &amp;&amp; dev-&gt;iommu-&gt;iommu_dev)</div><div class='add'>+		if (dev_has_iommu(dev))</div><div class='ctx'> 			iommu_deinit_device(dev);</div><div class='ctx'> 		else</div><div class='ctx'> 			dev-&gt;iommu_group = NULL;</div><div class='hunk'>@@ -819,7 +842,7 @@ int iommu_get_group_resv_regions(struct iommu_group *group,</div><div class='ctx'> 		 * Non-API groups still expose reserved_regions in sysfs,</div><div class='ctx'> 		 * so filter out calls that get here that way.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!device-&gt;dev-&gt;iommu)</div><div class='add'>+		if (!dev_has_iommu(device-&gt;dev))</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		INIT_LIST_HEAD(&amp;dev_resv_regions);</div><div class='hunk'>@@ -1225,6 +1248,12 @@ void iommu_group_remove_device(struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iommu_group_remove_device);</div><div class='ctx'> </div><div class='add'>+static struct device *iommu_group_first_dev(struct iommu_group *group)</div><div class='add'>+{</div><div class='add'>+	lockdep_assert_held(&amp;group-&gt;mutex);</div><div class='add'>+	return list_first_entry(&amp;group-&gt;devices, struct group_device, list)-&gt;dev;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * iommu_group_for_each_dev - iterate over each device in the group</div><div class='ctx'>  * @group: the group</div><div class='hunk'>@@ -1753,30 +1782,13 @@ __iommu_group_alloc_default_domain(struct iommu_group *group, int req_type)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * Returns the iommu_ops for the devices in an iommu group.</div><div class='del'>- *</div><div class='del'>- * It is assumed that all devices in an iommu group are managed by a single</div><div class='del'>- * IOMMU unit. Therefore, this returns the dev_iommu_ops of the first device</div><div class='del'>- * in the group.</div><div class='del'>- */</div><div class='del'>-static const struct iommu_ops *group_iommu_ops(struct iommu_group *group)</div><div class='del'>-{</div><div class='del'>-	struct group_device *device =</div><div class='del'>-		list_first_entry(&amp;group-&gt;devices, struct group_device, list);</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;group-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	return dev_iommu_ops(device-&gt;dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='ctx'>  * req_type of 0 means "auto" which means to select a domain based on</div><div class='ctx'>  * iommu_def_domain_type or what the driver actually supports.</div><div class='ctx'>  */</div><div class='ctx'> static struct iommu_domain *</div><div class='ctx'> iommu_group_alloc_default_domain(struct iommu_group *group, int req_type)</div><div class='ctx'> {</div><div class='del'>-	const struct iommu_ops *ops = group_iommu_ops(group);</div><div class='add'>+	const struct iommu_ops *ops = dev_iommu_ops(iommu_group_first_dev(group));</div><div class='ctx'> 	struct iommu_domain *dom;</div><div class='ctx'> </div><div class='ctx'> 	lockdep_assert_held(&amp;group-&gt;mutex);</div><div class='hunk'>@@ -1788,7 +1800,7 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ops-&gt;default_domain) {</div><div class='ctx'> 		if (req_type)</div><div class='del'>-			return NULL;</div><div class='add'>+			return ERR_PTR(-EINVAL);</div><div class='ctx'> 		return ops-&gt;default_domain;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1797,15 +1809,15 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type)</div><div class='ctx'> </div><div class='ctx'> 	/* The driver gave no guidance on what type to use, try the default */</div><div class='ctx'> 	dom = __iommu_group_alloc_default_domain(group, iommu_def_domain_type);</div><div class='del'>-	if (dom)</div><div class='add'>+	if (!IS_ERR(dom))</div><div class='ctx'> 		return dom;</div><div class='ctx'> </div><div class='ctx'> 	/* Otherwise IDENTITY and DMA_FQ defaults will try DMA */</div><div class='ctx'> 	if (iommu_def_domain_type == IOMMU_DOMAIN_DMA)</div><div class='del'>-		return NULL;</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	dom = __iommu_group_alloc_default_domain(group, IOMMU_DOMAIN_DMA);</div><div class='del'>-	if (!dom)</div><div class='del'>-		return NULL;</div><div class='add'>+	if (IS_ERR(dom))</div><div class='add'>+		return dom;</div><div class='ctx'> </div><div class='ctx'> 	pr_warn("Failed to allocate default IOMMU domain of type %u for group %s - Falling back to IOMMU_DOMAIN_DMA",</div><div class='ctx'> 		iommu_def_domain_type, group-&gt;name);</div><div class='hunk'>@@ -1822,7 +1834,9 @@ static int probe_iommu_group(struct device *dev, void *data)</div><div class='ctx'> 	struct list_head *group_list = data;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;iommu_probe_device_lock);</div><div class='ctx'> 	ret = __iommu_probe_device(dev, group_list);</div><div class='add'>+	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> 	if (ret == -ENODEV)</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1854,7 +1868,7 @@ static int iommu_bus_notifier(struct notifier_block *nb,</div><div class='ctx'> static int iommu_get_def_domain_type(struct iommu_group *group,</div><div class='ctx'> 				     struct device *dev, int cur_type)</div><div class='ctx'> {</div><div class='del'>-	const struct iommu_ops *ops = group_iommu_ops(group);</div><div class='add'>+	const struct iommu_ops *ops = dev_iommu_ops(dev);</div><div class='ctx'> 	int type;</div><div class='ctx'> </div><div class='ctx'> 	if (!ops-&gt;def_domain_type)</div><div class='hunk'>@@ -2003,9 +2017,28 @@ int bus_iommu_probe(const struct bus_type *bus)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * iommu_present() - make platform-specific assumptions about an IOMMU</div><div class='add'>+ * @bus: bus to check</div><div class='add'>+ *</div><div class='add'>+ * Do not use this function. You want device_iommu_mapped() instead.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if some IOMMU is present and aware of devices on the given bus;</div><div class='add'>+ * in general it may not be the only IOMMU, and it may not have anything to do</div><div class='add'>+ * with whatever device you are ultimately interested in.</div><div class='add'>+ */</div><div class='ctx'> bool iommu_present(const struct bus_type *bus)</div><div class='ctx'> {</div><div class='del'>-	return bus-&gt;iommu_ops != NULL;</div><div class='add'>+	bool ret = false;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; ARRAY_SIZE(iommu_buses); i++) {</div><div class='add'>+		if (iommu_buses[i] == bus) {</div><div class='add'>+			spin_lock(&amp;iommu_device_lock);</div><div class='add'>+			ret = !list_empty(&amp;iommu_device_list);</div><div class='add'>+			spin_unlock(&amp;iommu_device_lock);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iommu_present);</div><div class='ctx'> </div><div class='hunk'>@@ -2021,7 +2054,7 @@ bool device_iommu_capable(struct device *dev, enum iommu_cap cap)</div><div class='ctx'> {</div><div class='ctx'> 	const struct iommu_ops *ops;</div><div class='ctx'> </div><div class='del'>-	if (!dev-&gt;iommu || !dev-&gt;iommu-&gt;iommu_dev)</div><div class='add'>+	if (!dev_has_iommu(dev))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	ops = dev_iommu_ops(dev);</div><div class='hunk'>@@ -2094,12 +2127,20 @@ static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops,</div><div class='ctx'> 	else if (ops-&gt;domain_alloc)</div><div class='ctx'> 		domain = ops-&gt;domain_alloc(alloc_type);</div><div class='ctx'> 	else</div><div class='del'>-		return NULL;</div><div class='add'>+		return ERR_PTR(-EOPNOTSUPP);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Many domain_alloc ops now return ERR_PTR, make things easier for the</div><div class='add'>+	 * driver by accepting ERR_PTR from all domain_alloc ops instead of</div><div class='add'>+	 * having two rules.</div><div class='add'>+	 */</div><div class='add'>+	if (IS_ERR(domain))</div><div class='add'>+		return domain;</div><div class='ctx'> 	if (!domain)</div><div class='del'>-		return NULL;</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='ctx'> 	domain-&gt;type = type;</div><div class='add'>+	domain-&gt;owner = ops;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If not already set, assume all sizes by default; the driver</div><div class='ctx'> 	 * may override this later</div><div class='hunk'>@@ -2110,9 +2151,14 @@ static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops,</div><div class='ctx'> 	if (!domain-&gt;ops)</div><div class='ctx'> 		domain-&gt;ops = ops-&gt;default_domain_ops;</div><div class='ctx'> </div><div class='del'>-	if (iommu_is_dma_domain(domain) &amp;&amp; iommu_get_dma_cookie(domain)) {</div><div class='del'>-		iommu_domain_free(domain);</div><div class='del'>-		domain = NULL;</div><div class='add'>+	if (iommu_is_dma_domain(domain)) {</div><div class='add'>+		int rc;</div><div class='add'>+</div><div class='add'>+		rc = iommu_get_dma_cookie(domain);</div><div class='add'>+		if (rc) {</div><div class='add'>+			iommu_domain_free(domain);</div><div class='add'>+			return ERR_PTR(rc);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	return domain;</div><div class='ctx'> }</div><div class='hunk'>@@ -2120,19 +2166,40 @@ static struct iommu_domain *__iommu_domain_alloc(const struct iommu_ops *ops,</div><div class='ctx'> static struct iommu_domain *</div><div class='ctx'> __iommu_group_domain_alloc(struct iommu_group *group, unsigned int type)</div><div class='ctx'> {</div><div class='del'>-	struct device *dev =</div><div class='del'>-		list_first_entry(&amp;group-&gt;devices, struct group_device, list)</div><div class='del'>-			-&gt;dev;</div><div class='add'>+	struct device *dev = iommu_group_first_dev(group);</div><div class='ctx'> </div><div class='del'>-	return __iommu_domain_alloc(group_iommu_ops(group), dev, type);</div><div class='add'>+	return __iommu_domain_alloc(dev_iommu_ops(dev), dev, type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __iommu_domain_alloc_dev(struct device *dev, void *data)</div><div class='add'>+{</div><div class='add'>+	const struct iommu_ops **ops = data;</div><div class='add'>+</div><div class='add'>+	if (!dev_has_iommu(dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (WARN_ONCE(*ops &amp;&amp; *ops != dev_iommu_ops(dev),</div><div class='add'>+		      "Multiple IOMMU drivers present for bus %s, which the public IOMMU API can't fully support yet. You will still need to disable one or more for this to work, sorry!\n",</div><div class='add'>+		      dev_bus_name(dev)))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	*ops = dev_iommu_ops(dev);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct iommu_domain *iommu_domain_alloc(const struct bus_type *bus)</div><div class='ctx'> {</div><div class='del'>-	if (bus == NULL || bus-&gt;iommu_ops == NULL)</div><div class='add'>+	const struct iommu_ops *ops = NULL;</div><div class='add'>+	int err = bus_for_each_dev(bus, NULL, &amp;ops, __iommu_domain_alloc_dev);</div><div class='add'>+	struct iommu_domain *domain;</div><div class='add'>+</div><div class='add'>+	if (err || !ops)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	domain = __iommu_domain_alloc(ops, NULL, IOMMU_DOMAIN_UNMANAGED);</div><div class='add'>+	if (IS_ERR(domain))</div><div class='ctx'> 		return NULL;</div><div class='del'>-	return __iommu_domain_alloc(bus-&gt;iommu_ops, NULL,</div><div class='del'>-				    IOMMU_DOMAIN_UNMANAGED);</div><div class='add'>+	return domain;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(iommu_domain_alloc);</div><div class='ctx'> </div><div class='hunk'>@@ -2267,10 +2334,16 @@ struct iommu_domain *iommu_get_dma_domain(struct device *dev)</div><div class='ctx'> static int __iommu_attach_group(struct iommu_domain *domain,</div><div class='ctx'> 				struct iommu_group *group)</div><div class='ctx'> {</div><div class='add'>+	struct device *dev;</div><div class='add'>+</div><div class='ctx'> 	if (group-&gt;domain &amp;&amp; group-&gt;domain != group-&gt;default_domain &amp;&amp;</div><div class='ctx'> 	    group-&gt;domain != group-&gt;blocking_domain)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='add'>+	dev = iommu_group_first_dev(group);</div><div class='add'>+	if (!dev_has_iommu(dev) || dev_iommu_ops(dev) != domain-&gt;owner)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	return __iommu_group_set_domain(group, domain);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2987,8 +3060,8 @@ EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids);</div><div class='ctx'>  */</div><div class='ctx'> int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat)</div><div class='ctx'> {</div><div class='del'>-	if (dev-&gt;iommu &amp;&amp; dev-&gt;iommu-&gt;iommu_dev) {</div><div class='del'>-		const struct iommu_ops *ops = dev-&gt;iommu-&gt;iommu_dev-&gt;ops;</div><div class='add'>+	if (dev_has_iommu(dev)) {</div><div class='add'>+		const struct iommu_ops *ops = dev_iommu_ops(dev);</div><div class='ctx'> </div><div class='ctx'> 		if (ops-&gt;dev_enable_feat)</div><div class='ctx'> 			return ops-&gt;dev_enable_feat(dev, feat);</div><div class='hunk'>@@ -3003,8 +3076,8 @@ EXPORT_SYMBOL_GPL(iommu_dev_enable_feature);</div><div class='ctx'>  */</div><div class='ctx'> int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat)</div><div class='ctx'> {</div><div class='del'>-	if (dev-&gt;iommu &amp;&amp; dev-&gt;iommu-&gt;iommu_dev) {</div><div class='del'>-		const struct iommu_ops *ops = dev-&gt;iommu-&gt;iommu_dev-&gt;ops;</div><div class='add'>+	if (dev_has_iommu(dev)) {</div><div class='add'>+		const struct iommu_ops *ops = dev_iommu_ops(dev);</div><div class='ctx'> </div><div class='ctx'> 		if (ops-&gt;dev_disable_feat)</div><div class='ctx'> 			return ops-&gt;dev_disable_feat(dev, feat);</div><div class='hunk'>@@ -3041,8 +3114,8 @@ static int iommu_setup_default_domain(struct iommu_group *group,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	dom = iommu_group_alloc_default_domain(group, req_type);</div><div class='del'>-	if (!dom)</div><div class='del'>-		return -ENODEV;</div><div class='add'>+	if (IS_ERR(dom))</div><div class='add'>+		return PTR_ERR(dom);</div><div class='ctx'> </div><div class='ctx'> 	if (group-&gt;default_domain == dom)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -3243,21 +3316,23 @@ void iommu_device_unuse_default_domain(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> static int __iommu_group_alloc_blocking_domain(struct iommu_group *group)</div><div class='ctx'> {</div><div class='add'>+	struct iommu_domain *domain;</div><div class='add'>+</div><div class='ctx'> 	if (group-&gt;blocking_domain)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	group-&gt;blocking_domain =</div><div class='del'>-		__iommu_group_domain_alloc(group, IOMMU_DOMAIN_BLOCKED);</div><div class='del'>-	if (!group-&gt;blocking_domain) {</div><div class='add'>+	domain = __iommu_group_domain_alloc(group, IOMMU_DOMAIN_BLOCKED);</div><div class='add'>+	if (IS_ERR(domain)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * For drivers that do not yet understand IOMMU_DOMAIN_BLOCKED</div><div class='ctx'> 		 * create an empty domain instead.</div><div class='ctx'> 		 */</div><div class='del'>-		group-&gt;blocking_domain = __iommu_group_domain_alloc(</div><div class='del'>-			group, IOMMU_DOMAIN_UNMANAGED);</div><div class='del'>-		if (!group-&gt;blocking_domain)</div><div class='del'>-			return -EINVAL;</div><div class='add'>+		domain = __iommu_group_domain_alloc(group,</div><div class='add'>+						    IOMMU_DOMAIN_UNMANAGED);</div><div class='add'>+		if (IS_ERR(domain))</div><div class='add'>+			return PTR_ERR(domain);</div><div class='ctx'> 	}</div><div class='add'>+	group-&gt;blocking_domain = domain;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3462,6 +3537,9 @@ int iommu_attach_device_pasid(struct iommu_domain *domain,</div><div class='ctx'> 	if (!group)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='add'>+	if (!dev_has_iommu(dev) || dev_iommu_ops(dev) != domain-&gt;owner)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;group-&gt;mutex);</div><div class='ctx'> 	curr = xa_cmpxchg(&amp;group-&gt;pasid_array, pasid, NULL, domain, GFP_KERNEL);</div><div class='ctx'> 	if (curr) {</div><div class='hunk'>@@ -3550,6 +3628,7 @@ struct iommu_domain *iommu_sva_domain_alloc(struct device *dev,</div><div class='ctx'> 	domain-&gt;type = IOMMU_DOMAIN_SVA;</div><div class='ctx'> 	mmgrab(mm);</div><div class='ctx'> 	domain-&gt;mm = mm;</div><div class='add'>+	domain-&gt;owner = ops;</div><div class='ctx'> 	domain-&gt;iopf_handler = iommu_sva_handle_iopf;</div><div class='ctx'> 	domain-&gt;fault_data = mm;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c<br/>index 59d3a07300d9..873630c111c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/device.c</a></div><div class='hunk'>@@ -571,7 +571,7 @@ iommufd_device_auto_get_domain(struct iommufd_device *idev,</div><div class='ctx'> 			continue;</div><div class='ctx'> 		destroy_hwpt = (*do_attach)(idev, hwpt);</div><div class='ctx'> 		if (IS_ERR(destroy_hwpt)) {</div><div class='del'>-			iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+			iommufd_put_object(idev-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * -EINVAL means the domain is incompatible with the</div><div class='ctx'> 			 * device. Other error codes should propagate to</div><div class='hunk'>@@ -583,7 +583,7 @@ iommufd_device_auto_get_domain(struct iommufd_device *idev,</div><div class='ctx'> 			goto out_unlock;</div><div class='ctx'> 		}</div><div class='ctx'> 		*pt_id = hwpt-&gt;obj.id;</div><div class='del'>-		iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+		iommufd_put_object(idev-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -652,7 +652,7 @@ static int iommufd_device_change_pt(struct iommufd_device *idev, u32 *pt_id,</div><div class='ctx'> 		destroy_hwpt = ERR_PTR(-EINVAL);</div><div class='ctx'> 		goto out_put_pt_obj;</div><div class='ctx'> 	}</div><div class='del'>-	iommufd_put_object(pt_obj);</div><div class='add'>+	iommufd_put_object(idev-&gt;ictx, pt_obj);</div><div class='ctx'> </div><div class='ctx'> 	/* This destruction has to be after we unlock everything */</div><div class='ctx'> 	if (destroy_hwpt)</div><div class='hunk'>@@ -660,7 +660,7 @@ static int iommufd_device_change_pt(struct iommufd_device *idev, u32 *pt_id,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_put_pt_obj:</div><div class='del'>-	iommufd_put_object(pt_obj);</div><div class='add'>+	iommufd_put_object(idev-&gt;ictx, pt_obj);</div><div class='ctx'> 	return PTR_ERR(destroy_hwpt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -792,7 +792,7 @@ static int iommufd_access_change_ioas_id(struct iommufd_access *access, u32 id)</div><div class='ctx'> 	if (IS_ERR(ioas))</div><div class='ctx'> 		return PTR_ERR(ioas);</div><div class='ctx'> 	rc = iommufd_access_change_ioas(access, ioas);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(access-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -941,7 +941,7 @@ void iommufd_access_notify_unmap(struct io_pagetable *iopt, unsigned long iova,</div><div class='ctx'> </div><div class='ctx'> 		access-&gt;ops-&gt;unmap(access-&gt;data, iova, length);</div><div class='ctx'> </div><div class='del'>-		iommufd_put_object(&amp;access-&gt;obj);</div><div class='add'>+		iommufd_put_object(access-&gt;ictx, &amp;access-&gt;obj);</div><div class='ctx'> 		xa_lock(&amp;ioas-&gt;iopt.access_list);</div><div class='ctx'> 	}</div><div class='ctx'> 	xa_unlock(&amp;ioas-&gt;iopt.access_list);</div><div class='hunk'>@@ -1243,6 +1243,6 @@ int iommufd_get_hw_info(struct iommufd_ucmd *ucmd)</div><div class='ctx'> out_free:</div><div class='ctx'> 	kfree(data);</div><div class='ctx'> out_put:</div><div class='del'>-	iommufd_put_object(&amp;idev-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;idev-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c<br/>index 2abbeafdbd22..3f3f1fa1a0a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/hw_pagetable.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/hw_pagetable.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/hw_pagetable.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/hw_pagetable.c</a></div><div class='hunk'>@@ -135,6 +135,7 @@ iommufd_hwpt_paging_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas,</div><div class='ctx'> 			hwpt-&gt;domain = NULL;</div><div class='ctx'> 			goto out_abort;</div><div class='ctx'> 		}</div><div class='add'>+		hwpt-&gt;domain-&gt;owner = ops;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		hwpt-&gt;domain = iommu_domain_alloc(idev-&gt;dev-&gt;bus);</div><div class='ctx'> 		if (!hwpt-&gt;domain) {</div><div class='hunk'>@@ -233,6 +234,7 @@ iommufd_hwpt_nested_alloc(struct iommufd_ctx *ictx,</div><div class='ctx'> 		hwpt-&gt;domain = NULL;</div><div class='ctx'> 		goto out_abort;</div><div class='ctx'> 	}</div><div class='add'>+	hwpt-&gt;domain-&gt;owner = ops;</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON_ONCE(hwpt-&gt;domain-&gt;type != IOMMU_DOMAIN_NESTED)) {</div><div class='ctx'> 		rc = -EINVAL;</div><div class='hunk'>@@ -318,9 +320,9 @@ out_unlock:</div><div class='ctx'> 	if (ioas)</div><div class='ctx'> 		mutex_unlock(&amp;ioas-&gt;mutex);</div><div class='ctx'> out_put_pt:</div><div class='del'>-	iommufd_put_object(pt_obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, pt_obj);</div><div class='ctx'> out_put_idev:</div><div class='del'>-	iommufd_put_object(&amp;idev-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;idev-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -345,7 +347,7 @@ int iommufd_hwpt_set_dirty_tracking(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 	rc = iopt_set_dirty_tracking(&amp;ioas-&gt;iopt, hwpt_paging-&gt;common.domain,</div><div class='ctx'> 				     enable);</div><div class='ctx'> </div><div class='del'>-	iommufd_put_object(&amp;hwpt_paging-&gt;common.obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt_paging-&gt;common.obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -368,6 +370,47 @@ int iommufd_hwpt_get_dirty_bitmap(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 	rc = iopt_read_and_clear_dirty_data(</div><div class='ctx'> 		&amp;ioas-&gt;iopt, hwpt_paging-&gt;common.domain, cmd-&gt;flags, cmd);</div><div class='ctx'> </div><div class='del'>-	iommufd_put_object(&amp;hwpt_paging-&gt;common.obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt_paging-&gt;common.obj);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd)</div><div class='add'>+{</div><div class='add'>+	struct iommu_hwpt_invalidate *cmd = ucmd-&gt;cmd;</div><div class='add'>+	struct iommu_user_data_array data_array = {</div><div class='add'>+		.type = cmd-&gt;data_type,</div><div class='add'>+		.uptr = u64_to_user_ptr(cmd-&gt;data_uptr),</div><div class='add'>+		.entry_len = cmd-&gt;entry_len,</div><div class='add'>+		.entry_num = cmd-&gt;entry_num,</div><div class='add'>+	};</div><div class='add'>+	struct iommufd_hw_pagetable *hwpt;</div><div class='add'>+	u32 done_num = 0;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (cmd-&gt;__reserved) {</div><div class='add'>+		rc = -EOPNOTSUPP;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cmd-&gt;entry_num &amp;&amp; (!cmd-&gt;data_uptr || !cmd-&gt;entry_len)) {</div><div class='add'>+		rc = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hwpt = iommufd_get_hwpt_nested(ucmd, cmd-&gt;hwpt_id);</div><div class='add'>+	if (IS_ERR(hwpt)) {</div><div class='add'>+		rc = PTR_ERR(hwpt);</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = hwpt-&gt;domain-&gt;ops-&gt;cache_invalidate_user(hwpt-&gt;domain,</div><div class='add'>+						      &amp;data_array);</div><div class='add'>+	done_num = data_array.entry_num;</div><div class='add'>+</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='add'>+out:</div><div class='add'>+	cmd-&gt;entry_num = done_num;</div><div class='add'>+	if (iommufd_ucmd_respond(ucmd, sizeof(*cmd)))</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/iommufd/ioas.c b/drivers/iommu/iommufd/ioas.c<br/>index d5624577f79f..742248276548 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/ioas.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/ioas.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/ioas.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/ioas.c</a></div><div class='hunk'>@@ -105,7 +105,7 @@ int iommufd_ioas_iova_ranges(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		rc = -EMSGSIZE;</div><div class='ctx'> out_put:</div><div class='ctx'> 	up_read(&amp;ioas-&gt;iopt.iova_rwsem);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -175,7 +175,7 @@ out_free:</div><div class='ctx'> 		interval_tree_remove(node, &amp;allowed_iova);</div><div class='ctx'> 		kfree(container_of(node, struct iopt_allowed, node));</div><div class='ctx'> 	}</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -228,7 +228,7 @@ int iommufd_ioas_map(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 	cmd-&gt;iova = iova;</div><div class='ctx'> 	rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd));</div><div class='ctx'> out_put:</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -258,7 +258,7 @@ int iommufd_ioas_copy(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		return PTR_ERR(src_ioas);</div><div class='ctx'> 	rc = iopt_get_pages(&amp;src_ioas-&gt;iopt, cmd-&gt;src_iova, cmd-&gt;length,</div><div class='ctx'> 			    &amp;pages_list);</div><div class='del'>-	iommufd_put_object(&amp;src_ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;src_ioas-&gt;obj);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -279,7 +279,7 @@ int iommufd_ioas_copy(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 	cmd-&gt;dst_iova = iova;</div><div class='ctx'> 	rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd));</div><div class='ctx'> out_put_dst:</div><div class='del'>-	iommufd_put_object(&amp;dst_ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;dst_ioas-&gt;obj);</div><div class='ctx'> out_pages:</div><div class='ctx'> 	iopt_free_pages_list(&amp;pages_list);</div><div class='ctx'> 	return rc;</div><div class='hunk'>@@ -315,7 +315,7 @@ int iommufd_ioas_unmap(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 	rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd));</div><div class='ctx'> </div><div class='ctx'> out_put:</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -393,6 +393,6 @@ int iommufd_ioas_option(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		rc = -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h<br/>index a74cfefffbc6..991f864d1f9b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/iommufd_private.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/iommufd_private.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/iommufd_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/iommufd_private.h</a></div><div class='hunk'>@@ -21,6 +21,7 @@ struct iommufd_ctx {</div><div class='ctx'> 	struct file *file;</div><div class='ctx'> 	struct xarray objects;</div><div class='ctx'> 	struct xarray groups;</div><div class='add'>+	wait_queue_head_t destroy_wait;</div><div class='ctx'> </div><div class='ctx'> 	u8 account_mode;</div><div class='ctx'> 	/* Compatibility with VFIO no iommu */</div><div class='hunk'>@@ -135,7 +136,7 @@ enum iommufd_object_type {</div><div class='ctx'> </div><div class='ctx'> /* Base struct for all objects with a userspace ID handle. */</div><div class='ctx'> struct iommufd_object {</div><div class='del'>-	struct rw_semaphore destroy_rwsem;</div><div class='add'>+	refcount_t shortterm_users;</div><div class='ctx'> 	refcount_t users;</div><div class='ctx'> 	enum iommufd_object_type type;</div><div class='ctx'> 	unsigned int id;</div><div class='hunk'>@@ -143,10 +144,15 @@ struct iommufd_object {</div><div class='ctx'> </div><div class='ctx'> static inline bool iommufd_lock_obj(struct iommufd_object *obj)</div><div class='ctx'> {</div><div class='del'>-	if (!down_read_trylock(&amp;obj-&gt;destroy_rwsem))</div><div class='add'>+	if (!refcount_inc_not_zero(&amp;obj-&gt;users))</div><div class='ctx'> 		return false;</div><div class='del'>-	if (!refcount_inc_not_zero(&amp;obj-&gt;users)) {</div><div class='del'>-		up_read(&amp;obj-&gt;destroy_rwsem);</div><div class='add'>+	if (!refcount_inc_not_zero(&amp;obj-&gt;shortterm_users)) {</div><div class='add'>+		/*</div><div class='add'>+		 * If the caller doesn't already have a ref on obj this must be</div><div class='add'>+		 * called under the xa_lock. Otherwise the caller is holding a</div><div class='add'>+		 * ref on users. Thus it cannot be one before this decrement.</div><div class='add'>+		 */</div><div class='add'>+		refcount_dec(&amp;obj-&gt;users);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -154,10 +160,16 @@ static inline bool iommufd_lock_obj(struct iommufd_object *obj)</div><div class='ctx'> </div><div class='ctx'> struct iommufd_object *iommufd_get_object(struct iommufd_ctx *ictx, u32 id,</div><div class='ctx'> 					  enum iommufd_object_type type);</div><div class='del'>-static inline void iommufd_put_object(struct iommufd_object *obj)</div><div class='add'>+static inline void iommufd_put_object(struct iommufd_ctx *ictx,</div><div class='add'>+				      struct iommufd_object *obj)</div><div class='ctx'> {</div><div class='add'>+	/*</div><div class='add'>+	 * Users first, then shortterm so that REMOVE_WAIT_SHORTTERM never sees</div><div class='add'>+	 * a spurious !0 users with a 0 shortterm_users.</div><div class='add'>+	 */</div><div class='ctx'> 	refcount_dec(&amp;obj-&gt;users);</div><div class='del'>-	up_read(&amp;obj-&gt;destroy_rwsem);</div><div class='add'>+	if (refcount_dec_and_test(&amp;obj-&gt;shortterm_users))</div><div class='add'>+		wake_up_interruptible_all(&amp;ictx-&gt;destroy_wait);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void iommufd_object_abort(struct iommufd_ctx *ictx, struct iommufd_object *obj);</div><div class='hunk'>@@ -165,17 +177,49 @@ void iommufd_object_abort_and_destroy(struct iommufd_ctx *ictx,</div><div class='ctx'> 				      struct iommufd_object *obj);</div><div class='ctx'> void iommufd_object_finalize(struct iommufd_ctx *ictx,</div><div class='ctx'> 			     struct iommufd_object *obj);</div><div class='del'>-void __iommufd_object_destroy_user(struct iommufd_ctx *ictx,</div><div class='del'>-				   struct iommufd_object *obj, bool allow_fail);</div><div class='add'>+</div><div class='add'>+enum {</div><div class='add'>+	REMOVE_WAIT_SHORTTERM = 1,</div><div class='add'>+};</div><div class='add'>+int iommufd_object_remove(struct iommufd_ctx *ictx,</div><div class='add'>+			  struct iommufd_object *to_destroy, u32 id,</div><div class='add'>+			  unsigned int flags);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The caller holds a users refcount and wants to destroy the object. At this</div><div class='add'>+ * point the caller has no shortterm_users reference and at least the xarray</div><div class='add'>+ * will be holding one.</div><div class='add'>+ */</div><div class='ctx'> static inline void iommufd_object_destroy_user(struct iommufd_ctx *ictx,</div><div class='ctx'> 					       struct iommufd_object *obj)</div><div class='ctx'> {</div><div class='del'>-	__iommufd_object_destroy_user(ictx, obj, false);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = iommufd_object_remove(ictx, obj, obj-&gt;id, REMOVE_WAIT_SHORTTERM);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If there is a bug and we couldn't destroy the object then we did put</div><div class='add'>+	 * back the caller's users refcount and will eventually try to free it</div><div class='add'>+	 * again during close.</div><div class='add'>+	 */</div><div class='add'>+	WARN_ON(ret);</div><div class='ctx'> }</div><div class='del'>-static inline void iommufd_object_deref_user(struct iommufd_ctx *ictx,</div><div class='del'>-					     struct iommufd_object *obj)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The HWPT allocated by autodomains is used in possibly many devices and</div><div class='add'>+ * is automatically destroyed when its refcount reaches zero.</div><div class='add'>+ *</div><div class='add'>+ * If userspace uses the HWPT manually, even for a short term, then it will</div><div class='add'>+ * disrupt this refcounting and the auto-free in the kernel will not work.</div><div class='add'>+ * Userspace that tries to use the automatically allocated HWPT must be careful</div><div class='add'>+ * to ensure that it is consistently destroyed, eg by not racing accesses</div><div class='add'>+ * and by not attaching an automatic HWPT to a device manually.</div><div class='add'>+ */</div><div class='add'>+static inline void</div><div class='add'>+iommufd_object_put_and_try_destroy(struct iommufd_ctx *ictx,</div><div class='add'>+				   struct iommufd_object *obj)</div><div class='ctx'> {</div><div class='del'>-	__iommufd_object_destroy_user(ictx, obj, true);</div><div class='add'>+	iommufd_object_remove(ictx, obj, obj-&gt;id, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,</div><div class='hunk'>@@ -284,6 +328,15 @@ iommufd_get_hwpt_paging(struct iommufd_ucmd *ucmd, u32 id)</div><div class='ctx'> 					       IOMMUFD_OBJ_HWPT_PAGING),</div><div class='ctx'> 			    struct iommufd_hwpt_paging, common.obj);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static inline struct iommufd_hw_pagetable *</div><div class='add'>+iommufd_get_hwpt_nested(struct iommufd_ucmd *ucmd, u32 id)</div><div class='add'>+{</div><div class='add'>+	return container_of(iommufd_get_object(ucmd-&gt;ictx, id,</div><div class='add'>+					       IOMMUFD_OBJ_HWPT_NESTED),</div><div class='add'>+			    struct iommufd_hw_pagetable, obj);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int iommufd_hwpt_set_dirty_tracking(struct iommufd_ucmd *ucmd);</div><div class='ctx'> int iommufd_hwpt_get_dirty_bitmap(struct iommufd_ucmd *ucmd);</div><div class='ctx'> </div><div class='hunk'>@@ -301,6 +354,7 @@ void iommufd_hwpt_paging_abort(struct iommufd_object *obj);</div><div class='ctx'> void iommufd_hwpt_nested_destroy(struct iommufd_object *obj);</div><div class='ctx'> void iommufd_hwpt_nested_abort(struct iommufd_object *obj);</div><div class='ctx'> int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd);</div><div class='add'>+int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd);</div><div class='ctx'> </div><div class='ctx'> static inline void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx,</div><div class='ctx'> 					    struct iommufd_hw_pagetable *hwpt)</div><div class='hunk'>@@ -311,7 +365,7 @@ static inline void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx,</div><div class='ctx'> 		lockdep_assert_not_held(&amp;hwpt_paging-&gt;ioas-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 		if (hwpt_paging-&gt;auto_domain) {</div><div class='del'>-			iommufd_object_deref_user(ictx, &amp;hwpt-&gt;obj);</div><div class='add'>+			iommufd_object_put_and_try_destroy(ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h<br/>index 7910fbe1962d..482d4059f5db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/iommufd_test.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/iommufd_test.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/iommufd_test.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/iommufd_test.h</a></div><div class='hunk'>@@ -21,6 +21,7 @@ enum {</div><div class='ctx'> 	IOMMU_TEST_OP_ACCESS_REPLACE_IOAS,</div><div class='ctx'> 	IOMMU_TEST_OP_MOCK_DOMAIN_FLAGS,</div><div class='ctx'> 	IOMMU_TEST_OP_DIRTY,</div><div class='add'>+	IOMMU_TEST_OP_MD_CHECK_IOTLB,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum {</div><div class='hunk'>@@ -121,6 +122,10 @@ struct iommu_test_cmd {</div><div class='ctx'> 			__aligned_u64 uptr;</div><div class='ctx'> 			__aligned_u64 out_nr_dirty;</div><div class='ctx'> 		} dirty;</div><div class='add'>+		struct {</div><div class='add'>+			__u32 id;</div><div class='add'>+			__u32 iotlb;</div><div class='add'>+		} check_iotlb;</div><div class='ctx'> 	};</div><div class='ctx'> 	__u32 last;</div><div class='ctx'> };</div><div class='hunk'>@@ -148,4 +153,22 @@ struct iommu_hwpt_selftest {</div><div class='ctx'> 	__u32 iotlb;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Should not be equal to any defined value in enum iommu_hwpt_invalidate_data_type */</div><div class='add'>+#define IOMMU_HWPT_INVALIDATE_DATA_SELFTEST 0xdeadbeef</div><div class='add'>+#define IOMMU_HWPT_INVALIDATE_DATA_SELFTEST_INVALID 0xdadbeef</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct iommu_hwpt_invalidate_selftest - Invalidation data for Mock driver</div><div class='add'>+ *                                         (IOMMU_HWPT_INVALIDATE_DATA_SELFTEST)</div><div class='add'>+ * @flags: Invalidate flags</div><div class='add'>+ * @iotlb_id: Invalidate iotlb entry index</div><div class='add'>+ *</div><div class='add'>+ * If IOMMU_TEST_INVALIDATE_ALL is set in @flags, @iotlb_id will be ignored</div><div class='add'>+ */</div><div class='add'>+struct iommu_hwpt_invalidate_selftest {</div><div class='add'>+#define IOMMU_TEST_INVALIDATE_FLAG_ALL	(1 &lt;&lt; 0)</div><div class='add'>+	__u32 flags;</div><div class='add'>+	__u32 iotlb_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c<br/>index 45b9d40773b1..39b32932c61e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/main.c</a></div><div class='hunk'>@@ -33,7 +33,6 @@ struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,</div><div class='ctx'> 					     size_t size,</div><div class='ctx'> 					     enum iommufd_object_type type)</div><div class='ctx'> {</div><div class='del'>-	static struct lock_class_key obj_keys[IOMMUFD_OBJ_MAX];</div><div class='ctx'> 	struct iommufd_object *obj;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='hunk'>@@ -41,15 +40,8 @@ struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,</div><div class='ctx'> 	if (!obj)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	obj-&gt;type = type;</div><div class='del'>-	/*</div><div class='del'>-	 * In most cases the destroy_rwsem is obtained with try so it doesn't</div><div class='del'>-	 * interact with lockdep, however on destroy we have to sleep. This</div><div class='del'>-	 * means if we have to destroy an object while holding a get on another</div><div class='del'>-	 * object it triggers lockdep. Using one locking class per object type</div><div class='del'>-	 * is a simple and reasonable way to avoid this.</div><div class='del'>-	 */</div><div class='del'>-	__init_rwsem(&amp;obj-&gt;destroy_rwsem, "iommufd_object::destroy_rwsem",</div><div class='del'>-		     &amp;obj_keys[type]);</div><div class='add'>+	/* Starts out bias'd by 1 until it is removed from the xarray */</div><div class='add'>+	refcount_set(&amp;obj-&gt;shortterm_users, 1);</div><div class='ctx'> 	refcount_set(&amp;obj-&gt;users, 1);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -129,92 +121,113 @@ struct iommufd_object *iommufd_get_object(struct iommufd_ctx *ictx, u32 id,</div><div class='ctx'> 	return obj;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int iommufd_object_dec_wait_shortterm(struct iommufd_ctx *ictx,</div><div class='add'>+					     struct iommufd_object *to_destroy)</div><div class='add'>+{</div><div class='add'>+	if (refcount_dec_and_test(&amp;to_destroy-&gt;shortterm_users))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (wait_event_timeout(ictx-&gt;destroy_wait,</div><div class='add'>+				refcount_read(&amp;to_destroy-&gt;shortterm_users) ==</div><div class='add'>+					0,</div><div class='add'>+				msecs_to_jiffies(10000)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	pr_crit("Time out waiting for iommufd object to become free\n");</div><div class='add'>+	refcount_inc(&amp;to_destroy-&gt;shortterm_users);</div><div class='add'>+	return -EBUSY;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Remove the given object id from the xarray if the only reference to the</div><div class='del'>- * object is held by the xarray. The caller must call ops destroy().</div><div class='add'>+ * object is held by the xarray.</div><div class='ctx'>  */</div><div class='del'>-static struct iommufd_object *iommufd_object_remove(struct iommufd_ctx *ictx,</div><div class='del'>-						    u32 id, bool extra_put)</div><div class='add'>+int iommufd_object_remove(struct iommufd_ctx *ictx,</div><div class='add'>+			  struct iommufd_object *to_destroy, u32 id,</div><div class='add'>+			  unsigned int flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommufd_object *obj;</div><div class='ctx'> 	XA_STATE(xas, &amp;ictx-&gt;objects, id);</div><div class='del'>-</div><div class='del'>-	xa_lock(&amp;ictx-&gt;objects);</div><div class='del'>-	obj = xas_load(&amp;xas);</div><div class='del'>-	if (xa_is_zero(obj) || !obj) {</div><div class='del'>-		obj = ERR_PTR(-ENOENT);</div><div class='del'>-		goto out_xa;</div><div class='del'>-	}</div><div class='add'>+	bool zerod_shortterm = false;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * If the caller is holding a ref on obj we put it here under the</div><div class='del'>-	 * spinlock.</div><div class='add'>+	 * The purpose of the shortterm_users is to ensure deterministic</div><div class='add'>+	 * destruction of objects used by external drivers and destroyed by this</div><div class='add'>+	 * function. Any temporary increment of the refcount must increment</div><div class='add'>+	 * shortterm_users, such as during ioctl execution.</div><div class='ctx'> 	 */</div><div class='del'>-	if (extra_put)</div><div class='add'>+	if (flags &amp; REMOVE_WAIT_SHORTTERM) {</div><div class='add'>+		ret = iommufd_object_dec_wait_shortterm(ictx, to_destroy);</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * We have a bug. Put back the callers reference and</div><div class='add'>+			 * defer cleaning this object until close.</div><div class='add'>+			 */</div><div class='add'>+			refcount_dec(&amp;to_destroy-&gt;users);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+		zerod_shortterm = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xa_lock(&amp;ictx-&gt;objects);</div><div class='add'>+	obj = xas_load(&amp;xas);</div><div class='add'>+	if (to_destroy) {</div><div class='add'>+		/*</div><div class='add'>+		 * If the caller is holding a ref on obj we put it here under</div><div class='add'>+		 * the spinlock.</div><div class='add'>+		 */</div><div class='ctx'> 		refcount_dec(&amp;obj-&gt;users);</div><div class='ctx'> </div><div class='add'>+		if (WARN_ON(obj != to_destroy)) {</div><div class='add'>+			ret = -ENOENT;</div><div class='add'>+			goto err_xa;</div><div class='add'>+		}</div><div class='add'>+	} else if (xa_is_zero(obj) || !obj) {</div><div class='add'>+		ret = -ENOENT;</div><div class='add'>+		goto err_xa;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!refcount_dec_if_one(&amp;obj-&gt;users)) {</div><div class='del'>-		obj = ERR_PTR(-EBUSY);</div><div class='del'>-		goto out_xa;</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+		goto err_xa;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	xas_store(&amp;xas, NULL);</div><div class='ctx'> 	if (ictx-&gt;vfio_ioas == container_of(obj, struct iommufd_ioas, obj))</div><div class='ctx'> 		ictx-&gt;vfio_ioas = NULL;</div><div class='del'>-</div><div class='del'>-out_xa:</div><div class='ctx'> 	xa_unlock(&amp;ictx-&gt;objects);</div><div class='ctx'> </div><div class='del'>-	/* The returned object reference count is zero */</div><div class='del'>-	return obj;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * The caller holds a users refcount and wants to destroy the object. Returns</div><div class='del'>- * true if the object was destroyed. In all cases the caller no longer has a</div><div class='del'>- * reference on obj.</div><div class='del'>- */</div><div class='del'>-void __iommufd_object_destroy_user(struct iommufd_ctx *ictx,</div><div class='del'>-				   struct iommufd_object *obj, bool allow_fail)</div><div class='del'>-{</div><div class='del'>-	struct iommufd_object *ret;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='del'>-	 * The purpose of the destroy_rwsem is to ensure deterministic</div><div class='del'>-	 * destruction of objects used by external drivers and destroyed by this</div><div class='del'>-	 * function. Any temporary increment of the refcount must hold the read</div><div class='del'>-	 * side of this, such as during ioctl execution.</div><div class='del'>-	 */</div><div class='del'>-	down_write(&amp;obj-&gt;destroy_rwsem);</div><div class='del'>-	ret = iommufd_object_remove(ictx, obj-&gt;id, true);</div><div class='del'>-	up_write(&amp;obj-&gt;destroy_rwsem);</div><div class='del'>-</div><div class='del'>-	if (allow_fail &amp;&amp; IS_ERR(ret))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * If there is a bug and we couldn't destroy the object then we did put</div><div class='del'>-	 * back the caller's refcount and will eventually try to free it again</div><div class='del'>-	 * during close.</div><div class='add'>+	 * Since users is zero any positive users_shortterm must be racing</div><div class='add'>+	 * iommufd_put_object(), or we have a bug.</div><div class='ctx'> 	 */</div><div class='del'>-	if (WARN_ON(IS_ERR(ret)))</div><div class='del'>-		return;</div><div class='add'>+	if (!zerod_shortterm) {</div><div class='add'>+		ret = iommufd_object_dec_wait_shortterm(ictx, obj);</div><div class='add'>+		if (WARN_ON(ret))</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	iommufd_object_ops[obj-&gt;type].destroy(obj);</div><div class='ctx'> 	kfree(obj);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_xa:</div><div class='add'>+	if (zerod_shortterm) {</div><div class='add'>+		/* Restore the xarray owned reference */</div><div class='add'>+		refcount_set(&amp;obj-&gt;shortterm_users, 1);</div><div class='add'>+	}</div><div class='add'>+	xa_unlock(&amp;ictx-&gt;objects);</div><div class='add'>+</div><div class='add'>+	/* The returned object reference count is zero */</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int iommufd_destroy(struct iommufd_ucmd *ucmd)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_destroy *cmd = ucmd-&gt;cmd;</div><div class='del'>-	struct iommufd_object *obj;</div><div class='ctx'> </div><div class='del'>-	obj = iommufd_object_remove(ucmd-&gt;ictx, cmd-&gt;id, false);</div><div class='del'>-	if (IS_ERR(obj))</div><div class='del'>-		return PTR_ERR(obj);</div><div class='del'>-	iommufd_object_ops[obj-&gt;type].destroy(obj);</div><div class='del'>-	kfree(obj);</div><div class='del'>-	return 0;</div><div class='add'>+	return iommufd_object_remove(ucmd-&gt;ictx, NULL, cmd-&gt;id, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int iommufd_fops_open(struct inode *inode, struct file *filp)</div><div class='hunk'>@@ -238,6 +251,7 @@ static int iommufd_fops_open(struct inode *inode, struct file *filp)</div><div class='ctx'> 	xa_init_flags(&amp;ictx-&gt;objects, XA_FLAGS_ALLOC1 | XA_FLAGS_ACCOUNT);</div><div class='ctx'> 	xa_init(&amp;ictx-&gt;groups);</div><div class='ctx'> 	ictx-&gt;file = filp;</div><div class='add'>+	init_waitqueue_head(&amp;ictx-&gt;destroy_wait);</div><div class='ctx'> 	filp-&gt;private_data = ictx;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -308,6 +322,7 @@ union ucmd_buffer {</div><div class='ctx'> 	struct iommu_hw_info info;</div><div class='ctx'> 	struct iommu_hwpt_alloc hwpt;</div><div class='ctx'> 	struct iommu_hwpt_get_dirty_bitmap get_dirty_bitmap;</div><div class='add'>+	struct iommu_hwpt_invalidate cache;</div><div class='ctx'> 	struct iommu_hwpt_set_dirty_tracking set_dirty_tracking;</div><div class='ctx'> 	struct iommu_ioas_alloc alloc;</div><div class='ctx'> 	struct iommu_ioas_allow_iovas allow_iovas;</div><div class='hunk'>@@ -346,6 +361,8 @@ static const struct iommufd_ioctl_op iommufd_ioctl_ops[] = {</div><div class='ctx'> 		 __reserved),</div><div class='ctx'> 	IOCTL_OP(IOMMU_HWPT_GET_DIRTY_BITMAP, iommufd_hwpt_get_dirty_bitmap,</div><div class='ctx'> 		 struct iommu_hwpt_get_dirty_bitmap, data),</div><div class='add'>+	IOCTL_OP(IOMMU_HWPT_INVALIDATE, iommufd_hwpt_invalidate,</div><div class='add'>+		 struct iommu_hwpt_invalidate, __reserved),</div><div class='ctx'> 	IOCTL_OP(IOMMU_HWPT_SET_DIRTY_TRACKING, iommufd_hwpt_set_dirty_tracking,</div><div class='ctx'> 		 struct iommu_hwpt_set_dirty_tracking, __reserved),</div><div class='ctx'> 	IOCTL_OP(IOMMU_IOAS_ALLOC, iommufd_ioas_alloc_ioctl,</div><div class='head'>diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c<br/>index 5d93434003d8..d9e9920c7eba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/selftest.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/selftest.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/selftest.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/selftest.c</a></div><div class='hunk'>@@ -25,6 +25,19 @@ static struct iommu_domain_ops domain_nested_ops;</div><div class='ctx'> </div><div class='ctx'> size_t iommufd_test_memory_limit = 65536;</div><div class='ctx'> </div><div class='add'>+struct mock_bus_type {</div><div class='add'>+	struct bus_type bus;</div><div class='add'>+	struct notifier_block nb;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct mock_bus_type iommufd_mock_bus_type = {</div><div class='add'>+	.bus = {</div><div class='add'>+		.name = "iommufd_mock",</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static atomic_t mock_dev_num;</div><div class='add'>+</div><div class='ctx'> enum {</div><div class='ctx'> 	MOCK_DIRTY_TRACK = 1,</div><div class='ctx'> 	MOCK_IO_PAGE_SIZE = PAGE_SIZE / 2,</div><div class='hunk'>@@ -86,7 +99,7 @@ void iommufd_test_syz_conv_iova_id(struct iommufd_ucmd *ucmd,</div><div class='ctx'> 	if (IS_ERR(ioas))</div><div class='ctx'> 		return;</div><div class='ctx'> 	*iova = iommufd_test_syz_conv_iova(&amp;ioas-&gt;iopt, iova);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct mock_iommu_domain {</div><div class='hunk'>@@ -437,6 +450,8 @@ static struct iommu_device mock_iommu_device = {</div><div class='ctx'> </div><div class='ctx'> static struct iommu_device *mock_probe_device(struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	if (dev-&gt;bus != &amp;iommufd_mock_bus_type.bus)</div><div class='add'>+		return ERR_PTR(-ENODEV);</div><div class='ctx'> 	return &amp;mock_iommu_device;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -473,9 +488,59 @@ static void mock_domain_free_nested(struct iommu_domain *domain)</div><div class='ctx'> 	kfree(mock_nested);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+mock_domain_cache_invalidate_user(struct iommu_domain *domain,</div><div class='add'>+				  struct iommu_user_data_array *array)</div><div class='add'>+{</div><div class='add'>+	struct mock_iommu_domain_nested *mock_nested =</div><div class='add'>+		container_of(domain, struct mock_iommu_domain_nested, domain);</div><div class='add'>+	struct iommu_hwpt_invalidate_selftest inv;</div><div class='add'>+	u32 processed = 0;</div><div class='add'>+	int i = 0, j;</div><div class='add'>+	int rc = 0;</div><div class='add'>+</div><div class='add'>+	if (array-&gt;type != IOMMU_HWPT_INVALIDATE_DATA_SELFTEST) {</div><div class='add'>+		rc = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for ( ; i &lt; array-&gt;entry_num; i++) {</div><div class='add'>+		rc = iommu_copy_struct_from_user_array(&amp;inv, array,</div><div class='add'>+						       IOMMU_HWPT_INVALIDATE_DATA_SELFTEST,</div><div class='add'>+						       i, iotlb_id);</div><div class='add'>+		if (rc)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (inv.flags &amp; ~IOMMU_TEST_INVALIDATE_FLAG_ALL) {</div><div class='add'>+			rc = -EOPNOTSUPP;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (inv.iotlb_id &gt; MOCK_NESTED_DOMAIN_IOTLB_ID_MAX) {</div><div class='add'>+			rc = -EINVAL;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (inv.flags &amp; IOMMU_TEST_INVALIDATE_FLAG_ALL) {</div><div class='add'>+			/* Invalidate all mock iotlb entries and ignore iotlb_id */</div><div class='add'>+			for (j = 0; j &lt; MOCK_NESTED_DOMAIN_IOTLB_NUM; j++)</div><div class='add'>+				mock_nested-&gt;iotlb[j] = 0;</div><div class='add'>+		} else {</div><div class='add'>+			mock_nested-&gt;iotlb[inv.iotlb_id] = 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		processed++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	array-&gt;entry_num = processed;</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct iommu_domain_ops domain_nested_ops = {</div><div class='ctx'> 	.free = mock_domain_free_nested,</div><div class='ctx'> 	.attach_dev = mock_domain_nop_attach,</div><div class='add'>+	.cache_invalidate_user = mock_domain_cache_invalidate_user,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct iommufd_hw_pagetable *</div><div class='hunk'>@@ -500,7 +565,7 @@ get_md_pagetable(struct iommufd_ucmd *ucmd, u32 mockpt_id,</div><div class='ctx'> 		return hwpt;</div><div class='ctx'> 	if (hwpt-&gt;domain-&gt;type != IOMMU_DOMAIN_UNMANAGED ||</div><div class='ctx'> 	    hwpt-&gt;domain-&gt;ops != mock_ops.default_domain_ops) {</div><div class='del'>-		iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+		iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> 	*mock = container_of(hwpt-&gt;domain, struct mock_iommu_domain, domain);</div><div class='hunk'>@@ -518,7 +583,7 @@ get_md_pagetable_nested(struct iommufd_ucmd *ucmd, u32 mockpt_id,</div><div class='ctx'> 		return hwpt;</div><div class='ctx'> 	if (hwpt-&gt;domain-&gt;type != IOMMU_DOMAIN_NESTED ||</div><div class='ctx'> 	    hwpt-&gt;domain-&gt;ops != &amp;domain_nested_ops) {</div><div class='del'>-		iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+		iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> 	*mock_nested = container_of(hwpt-&gt;domain,</div><div class='hunk'>@@ -526,19 +591,6 @@ get_md_pagetable_nested(struct iommufd_ucmd *ucmd, u32 mockpt_id,</div><div class='ctx'> 	return hwpt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct mock_bus_type {</div><div class='del'>-	struct bus_type bus;</div><div class='del'>-	struct notifier_block nb;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct mock_bus_type iommufd_mock_bus_type = {</div><div class='del'>-	.bus = {</div><div class='del'>-		.name = "iommufd_mock",</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static atomic_t mock_dev_num;</div><div class='del'>-</div><div class='ctx'> static void mock_dev_release(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mock_dev *mdev = container_of(dev, struct mock_dev, dev);</div><div class='hunk'>@@ -681,7 +733,7 @@ static int iommufd_test_mock_domain_replace(struct iommufd_ucmd *ucmd,</div><div class='ctx'> 	rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd));</div><div class='ctx'> </div><div class='ctx'> out_dev_obj:</div><div class='del'>-	iommufd_put_object(dev_obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, dev_obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -699,7 +751,7 @@ static int iommufd_test_add_reserved(struct iommufd_ucmd *ucmd,</div><div class='ctx'> 	down_write(&amp;ioas-&gt;iopt.iova_rwsem);</div><div class='ctx'> 	rc = iopt_reserve_iova(&amp;ioas-&gt;iopt, start, start + length - 1, NULL);</div><div class='ctx'> 	up_write(&amp;ioas-&gt;iopt.iova_rwsem);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -754,7 +806,7 @@ static int iommufd_test_md_check_pa(struct iommufd_ucmd *ucmd,</div><div class='ctx'> 	rc = 0;</div><div class='ctx'> </div><div class='ctx'> out_put:</div><div class='del'>-	iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -793,6 +845,28 @@ static int iommufd_test_md_check_refs(struct iommufd_ucmd *ucmd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int iommufd_test_md_check_iotlb(struct iommufd_ucmd *ucmd,</div><div class='add'>+				       u32 mockpt_id, unsigned int iotlb_id,</div><div class='add'>+				       u32 iotlb)</div><div class='add'>+{</div><div class='add'>+	struct mock_iommu_domain_nested *mock_nested;</div><div class='add'>+	struct iommufd_hw_pagetable *hwpt;</div><div class='add'>+	int rc = 0;</div><div class='add'>+</div><div class='add'>+	hwpt = get_md_pagetable_nested(ucmd, mockpt_id, &amp;mock_nested);</div><div class='add'>+	if (IS_ERR(hwpt))</div><div class='add'>+		return PTR_ERR(hwpt);</div><div class='add'>+</div><div class='add'>+	mock_nested = container_of(hwpt-&gt;domain,</div><div class='add'>+				   struct mock_iommu_domain_nested, domain);</div><div class='add'>+</div><div class='add'>+	if (iotlb_id &gt; MOCK_NESTED_DOMAIN_IOTLB_ID_MAX ||</div><div class='add'>+	    mock_nested-&gt;iotlb[iotlb_id] != iotlb)</div><div class='add'>+		rc = -EINVAL;</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct selftest_access {</div><div class='ctx'> 	struct iommufd_access *access;</div><div class='ctx'> 	struct file *file;</div><div class='hunk'>@@ -1233,7 +1307,7 @@ static int iommufd_test_dirty(struct iommufd_ucmd *ucmd, unsigned int mockpt_id,</div><div class='ctx'> out_free:</div><div class='ctx'> 	kvfree(tmp);</div><div class='ctx'> out_put:</div><div class='del'>-	iommufd_put_object(&amp;hwpt-&gt;obj);</div><div class='add'>+	iommufd_put_object(ucmd-&gt;ictx, &amp;hwpt-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1274,6 +1348,10 @@ int iommufd_test(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		return iommufd_test_md_check_refs(</div><div class='ctx'> 			ucmd, u64_to_user_ptr(cmd-&gt;check_refs.uptr),</div><div class='ctx'> 			cmd-&gt;check_refs.length, cmd-&gt;check_refs.refs);</div><div class='add'>+	case IOMMU_TEST_OP_MD_CHECK_IOTLB:</div><div class='add'>+		return iommufd_test_md_check_iotlb(ucmd, cmd-&gt;id,</div><div class='add'>+						   cmd-&gt;check_iotlb.id,</div><div class='add'>+						   cmd-&gt;check_iotlb.iotlb);</div><div class='ctx'> 	case IOMMU_TEST_OP_CREATE_ACCESS:</div><div class='ctx'> 		return iommufd_test_create_access(ucmd, cmd-&gt;id,</div><div class='ctx'> 						  cmd-&gt;create_access.flags);</div><div class='head'>diff --git a/drivers/iommu/iommufd/vfio_compat.c b/drivers/iommu/iommufd/vfio_compat.c<br/>index 538fbf76354d..a3ad5f0b6c59 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/vfio_compat.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/iommufd/vfio_compat.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/iommufd/vfio_compat.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/iommufd/vfio_compat.c</a></div><div class='hunk'>@@ -41,7 +41,7 @@ int iommufd_vfio_compat_ioas_get_id(struct iommufd_ctx *ictx, u32 *out_ioas_id)</div><div class='ctx'> 	if (IS_ERR(ioas))</div><div class='ctx'> 		return PTR_ERR(ioas);</div><div class='ctx'> 	*out_ioas_id = ioas-&gt;obj.id;</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(iommufd_vfio_compat_ioas_get_id, IOMMUFD_VFIO);</div><div class='hunk'>@@ -98,7 +98,7 @@ int iommufd_vfio_compat_ioas_create(struct iommufd_ctx *ictx)</div><div class='ctx'> </div><div class='ctx'> 	if (ictx-&gt;vfio_ioas &amp;&amp; iommufd_lock_obj(&amp;ictx-&gt;vfio_ioas-&gt;obj)) {</div><div class='ctx'> 		ret = 0;</div><div class='del'>-		iommufd_put_object(&amp;ictx-&gt;vfio_ioas-&gt;obj);</div><div class='add'>+		iommufd_put_object(ictx, &amp;ictx-&gt;vfio_ioas-&gt;obj);</div><div class='ctx'> 		goto out_abort;</div><div class='ctx'> 	}</div><div class='ctx'> 	ictx-&gt;vfio_ioas = ioas;</div><div class='hunk'>@@ -133,7 +133,7 @@ int iommufd_vfio_ioas(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		if (IS_ERR(ioas))</div><div class='ctx'> 			return PTR_ERR(ioas);</div><div class='ctx'> 		cmd-&gt;ioas_id = ioas-&gt;obj.id;</div><div class='del'>-		iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+		iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 		return iommufd_ucmd_respond(ucmd, sizeof(*cmd));</div><div class='ctx'> </div><div class='ctx'> 	case IOMMU_VFIO_IOAS_SET:</div><div class='hunk'>@@ -143,7 +143,7 @@ int iommufd_vfio_ioas(struct iommufd_ucmd *ucmd)</div><div class='ctx'> 		xa_lock(&amp;ucmd-&gt;ictx-&gt;objects);</div><div class='ctx'> 		ucmd-&gt;ictx-&gt;vfio_ioas = ioas;</div><div class='ctx'> 		xa_unlock(&amp;ucmd-&gt;ictx-&gt;objects);</div><div class='del'>-		iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+		iommufd_put_object(ucmd-&gt;ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	case IOMMU_VFIO_IOAS_CLEAR:</div><div class='hunk'>@@ -190,7 +190,7 @@ static int iommufd_vfio_map_dma(struct iommufd_ctx *ictx, unsigned int cmd,</div><div class='ctx'> 	iova = map.iova;</div><div class='ctx'> 	rc = iopt_map_user_pages(ictx, &amp;ioas-&gt;iopt, &amp;iova, u64_to_user_ptr(map.vaddr),</div><div class='ctx'> 				 map.size, iommu_prot, 0);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -249,7 +249,7 @@ static int iommufd_vfio_unmap_dma(struct iommufd_ctx *ictx, unsigned int cmd,</div><div class='ctx'> 		rc = -EFAULT;</div><div class='ctx'> </div><div class='ctx'> err_put:</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -272,7 +272,7 @@ static int iommufd_vfio_cc_iommu(struct iommufd_ctx *ictx)</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;ioas-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -349,7 +349,7 @@ static int iommufd_vfio_set_iommu(struct iommufd_ctx *ictx, unsigned long type)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (type == VFIO_TYPE1_IOMMU)</div><div class='ctx'> 		rc = iopt_disable_large_pages(&amp;ioas-&gt;iopt);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -511,7 +511,7 @@ static int iommufd_vfio_iommu_get_info(struct iommufd_ctx *ictx,</div><div class='ctx'> </div><div class='ctx'> out_put:</div><div class='ctx'> 	up_read(&amp;ioas-&gt;iopt.iova_rwsem);</div><div class='del'>-	iommufd_put_object(&amp;ioas-&gt;obj);</div><div class='add'>+	iommufd_put_object(ictx, &amp;ioas-&gt;obj);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c<br/>index 75279500a4a8..7abe9e85a570 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/mtk_iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/mtk_iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/mtk_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/mtk_iommu.c</a></div><div class='hunk'>@@ -863,16 +863,11 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,</div><div class='ctx'> static struct iommu_device *mtk_iommu_probe_device(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-	struct mtk_iommu_data *data;</div><div class='add'>+	struct mtk_iommu_data *data = dev_iommu_priv_get(dev);</div><div class='ctx'> 	struct device_link *link;</div><div class='ctx'> 	struct device *larbdev;</div><div class='ctx'> 	unsigned int larbid, larbidx, i;</div><div class='ctx'> </div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;mtk_iommu_ops)</div><div class='del'>-		return ERR_PTR(-ENODEV); /* Not a iommu client device */</div><div class='del'>-</div><div class='del'>-	data = dev_iommu_priv_get(dev);</div><div class='del'>-</div><div class='ctx'> 	if (!MTK_IOMMU_IS_TYPE(data-&gt;plat_data, MTK_IOMMU_TYPE_MM))</div><div class='ctx'> 		return &amp;data-&gt;iommu;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c<br/>index 67e044c1a7d9..25b41222abae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/mtk_iommu_v1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/mtk_iommu_v1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/mtk_iommu_v1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/mtk_iommu_v1.c</a></div><div class='hunk'>@@ -481,9 +481,6 @@ static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)</div><div class='ctx'> 		idx++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;mtk_iommu_v1_ops)</div><div class='del'>-		return ERR_PTR(-ENODEV); /* Not a iommu client device */</div><div class='del'>-</div><div class='ctx'> 	data = dev_iommu_priv_get(dev);</div><div class='ctx'> </div><div class='ctx'> 	/* Link the consumer device with the smi-larb device(supplier) */</div><div class='head'>diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c<br/>index 157b286e36bf..719652b60840 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/of_iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/of_iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/of_iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/of_iommu.c</a></div><div class='hunk'>@@ -17,8 +17,6 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/fsl/mc.h&gt;</div><div class='ctx'> </div><div class='del'>-#define NO_IOMMU	1</div><div class='del'>-</div><div class='ctx'> static int of_iommu_xlate(struct device *dev,</div><div class='ctx'> 			  struct of_phandle_args *iommu_spec)</div><div class='ctx'> {</div><div class='hunk'>@@ -29,7 +27,7 @@ static int of_iommu_xlate(struct device *dev,</div><div class='ctx'> 	ops = iommu_ops_from_fwnode(fwnode);</div><div class='ctx'> 	if ((ops &amp;&amp; !ops-&gt;of_xlate) ||</div><div class='ctx'> 	    !of_device_is_available(iommu_spec-&gt;np))</div><div class='del'>-		return NO_IOMMU;</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	ret = iommu_fwspec_init(dev, &amp;iommu_spec-&gt;np-&gt;fwnode, ops);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -61,7 +59,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np,</div><div class='ctx'> 			 "iommu-map-mask", &amp;iommu_spec.np,</div><div class='ctx'> 			 iommu_spec.args);</div><div class='ctx'> 	if (err)</div><div class='del'>-		return err == -ENODEV ? NO_IOMMU : err;</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='ctx'> 	err = of_iommu_xlate(dev, &amp;iommu_spec);</div><div class='ctx'> 	of_node_put(iommu_spec.np);</div><div class='hunk'>@@ -72,7 +70,7 @@ static int of_iommu_configure_dev(struct device_node *master_np,</div><div class='ctx'> 				  struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct of_phandle_args iommu_spec;</div><div class='del'>-	int err = NO_IOMMU, idx = 0;</div><div class='add'>+	int err = -ENODEV, idx = 0;</div><div class='ctx'> </div><div class='ctx'> 	while (!of_parse_phandle_with_args(master_np, "iommus",</div><div class='ctx'> 					   "#iommu-cells",</div><div class='hunk'>@@ -107,21 +105,30 @@ static int of_iommu_configure_device(struct device_node *master_np,</div><div class='ctx'> 		      of_iommu_configure_dev(master_np, dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct iommu_ops *of_iommu_configure(struct device *dev,</div><div class='del'>-					   struct device_node *master_np,</div><div class='del'>-					   const u32 *id)</div><div class='add'>+/*</div><div class='add'>+ * Returns:</div><div class='add'>+ *  0 on success, an iommu was configured</div><div class='add'>+ *  -ENODEV if the device does not have any IOMMU</div><div class='add'>+ *  -EPROBEDEFER if probing should be tried again</div><div class='add'>+ *  -errno fatal errors</div><div class='add'>+ */</div><div class='add'>+int of_iommu_configure(struct device *dev, struct device_node *master_np,</div><div class='add'>+		       const u32 *id)</div><div class='ctx'> {</div><div class='del'>-	const struct iommu_ops *ops = NULL;</div><div class='del'>-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-	int err = NO_IOMMU;</div><div class='add'>+	struct iommu_fwspec *fwspec;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!master_np)</div><div class='del'>-		return NULL;</div><div class='add'>+		return -ENODEV;</div><div class='ctx'> </div><div class='add'>+	/* Serialise to make dev-&gt;iommu stable under our potential fwspec */</div><div class='add'>+	mutex_lock(&amp;iommu_probe_device_lock);</div><div class='add'>+	fwspec = dev_iommu_fwspec_get(dev);</div><div class='ctx'> 	if (fwspec) {</div><div class='del'>-		if (fwspec-&gt;ops)</div><div class='del'>-			return fwspec-&gt;ops;</div><div class='del'>-</div><div class='add'>+		if (fwspec-&gt;ops) {</div><div class='add'>+			mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='ctx'> 		/* In the deferred case, start again from scratch */</div><div class='ctx'> 		iommu_fwspec_free(dev);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -143,34 +150,21 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		err = of_iommu_configure_device(master_np, dev, id);</div><div class='ctx'> 	}</div><div class='add'>+	mutex_unlock(&amp;iommu_probe_device_lock);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Two success conditions can be represented by non-negative err here:</div><div class='del'>-	 * &gt;0 : there is no IOMMU, or one was unavailable for non-fatal reasons</div><div class='del'>-	 *  0 : we found an IOMMU, and dev-&gt;fwspec is initialised appropriately</div><div class='del'>-	 * &lt;0 : any actual error</div><div class='del'>-	 */</div><div class='del'>-	if (!err) {</div><div class='del'>-		/* The fwspec pointer changed, read it again */</div><div class='del'>-		fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-		ops    = fwspec-&gt;ops;</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * If we have reason to believe the IOMMU driver missed the initial</div><div class='del'>-	 * probe for dev, replay it to get things in order.</div><div class='del'>-	 */</div><div class='del'>-	if (!err &amp;&amp; dev-&gt;bus)</div><div class='del'>-		err = iommu_probe_device(dev);</div><div class='del'>-</div><div class='del'>-	/* Ignore all other errors apart from EPROBE_DEFER */</div><div class='del'>-	if (err == -EPROBE_DEFER) {</div><div class='del'>-		ops = ERR_PTR(err);</div><div class='del'>-	} else if (err &lt; 0) {</div><div class='del'>-		dev_dbg(dev, "Adding to IOMMU failed: %d\n", err);</div><div class='del'>-		ops = NULL;</div><div class='del'>-	}</div><div class='add'>+	if (err == -ENODEV || err == -EPROBE_DEFER)</div><div class='add'>+		return err;</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_log;</div><div class='ctx'> </div><div class='del'>-	return ops;</div><div class='add'>+	err = iommu_probe_device(dev);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_log;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_log:</div><div class='add'>+	dev_dbg(dev, "Adding to IOMMU failed: %pe\n", ERR_PTR(err));</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum iommu_resv_type __maybe_unused</div><div class='hunk'>@@ -191,7 +185,7 @@ iommu_resv_region_get_type(struct device *dev,</div><div class='ctx'> 	if (start == phys-&gt;start &amp;&amp; end == phys-&gt;end)</div><div class='ctx'> 		return IOMMU_RESV_DIRECT;</div><div class='ctx'> </div><div class='del'>-	dev_warn(dev, "treating non-direct mapping [%pr] -&gt; [%pap-%pap] as reservation\n", &amp;phys,</div><div class='add'>+	dev_warn(dev, "treating non-direct mapping [%pr] -&gt; [%pap-%pap] as reservation\n", phys,</div><div class='ctx'> 		 &amp;start, &amp;end);</div><div class='ctx'> 	return IOMMU_RESV_RESERVED;</div><div class='ctx'> }</div><div class='hunk'>@@ -254,7 +248,14 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list)</div><div class='ctx'> 				phys_addr_t iova;</div><div class='ctx'> 				size_t length;</div><div class='ctx'> </div><div class='add'>+				if (of_dma_is_coherent(dev-&gt;of_node))</div><div class='add'>+					prot |= IOMMU_CACHE;</div><div class='add'>+</div><div class='ctx'> 				maps = of_translate_dma_region(np, maps, &amp;iova, &amp;length);</div><div class='add'>+				if (length == 0) {</div><div class='add'>+					dev_warn(dev, "Cannot reserve IOVA region of 0 size\n");</div><div class='add'>+					continue;</div><div class='add'>+				}</div><div class='ctx'> 				type = iommu_resv_region_get_type(dev, &amp;phys, iova, length);</div><div class='ctx'> </div><div class='ctx'> 				region = iommu_alloc_resv_region(iova, length, prot, type,</div><div class='head'>diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c<br/>index c66b070841dd..c9528065a59a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/omap-iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/omap-iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/omap-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/omap-iommu.c</a></div><div class='hunk'>@@ -1719,7 +1719,6 @@ static void omap_iommu_release_device(struct device *dev)</div><div class='ctx'> 	if (!dev-&gt;of_node || !arch_data)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	dev_iommu_priv_set(dev, NULL);</div><div class='ctx'> 	kfree(arch_data);</div><div class='ctx'> </div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c<br/>index 2eb9fb46703b..537359f10997 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/sprd-iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/sprd-iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/sprd-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/sprd-iommu.c</a></div><div class='hunk'>@@ -385,13 +385,7 @@ static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,</div><div class='ctx'> </div><div class='ctx'> static struct iommu_device *sprd_iommu_probe_device(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='del'>-	struct sprd_iommu_device *sdev;</div><div class='del'>-</div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;sprd_iommu_ops)</div><div class='del'>-		return ERR_PTR(-ENODEV);</div><div class='del'>-</div><div class='del'>-	sdev = dev_iommu_priv_get(dev);</div><div class='add'>+	struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;sdev-&gt;iommu;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c<br/>index 379ebe03efb6..34db37fd9675 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/iommu/virtio-iommu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/iommu/virtio-iommu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/iommu/virtio-iommu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/iommu/virtio-iommu.c</a></div><div class='hunk'>@@ -843,7 +843,7 @@ static int viommu_map_pages(struct iommu_domain *domain, unsigned long iova,</div><div class='ctx'> 			.flags		= cpu_to_le32(flags),</div><div class='ctx'> 		};</div><div class='ctx'> </div><div class='del'>-		ret = viommu_send_req_sync(vdomain-&gt;viommu, &amp;map, sizeof(map));</div><div class='add'>+		ret = viommu_add_req(vdomain-&gt;viommu, &amp;map, sizeof(map));</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			viommu_del_mappings(vdomain, iova, end);</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -912,6 +912,33 @@ static void viommu_iotlb_sync(struct iommu_domain *domain,</div><div class='ctx'> 	viommu_sync_req(vdomain-&gt;viommu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int viommu_iotlb_sync_map(struct iommu_domain *domain,</div><div class='add'>+				 unsigned long iova, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct viommu_domain *vdomain = to_viommu_domain(domain);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * May be called before the viommu is initialized including</div><div class='add'>+	 * while creating direct mapping</div><div class='add'>+	 */</div><div class='add'>+	if (!vdomain-&gt;nr_endpoints)</div><div class='add'>+		return 0;</div><div class='add'>+	return viommu_sync_req(vdomain-&gt;viommu);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void viommu_flush_iotlb_all(struct iommu_domain *domain)</div><div class='add'>+{</div><div class='add'>+	struct viommu_domain *vdomain = to_viommu_domain(domain);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * May be called before the viommu is initialized including</div><div class='add'>+	 * while creating direct mapping</div><div class='add'>+	 */</div><div class='add'>+	if (!vdomain-&gt;nr_endpoints)</div><div class='add'>+		return;</div><div class='add'>+	viommu_sync_req(vdomain-&gt;viommu);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void viommu_get_resv_regions(struct device *dev, struct list_head *head)</div><div class='ctx'> {</div><div class='ctx'> 	struct iommu_resv_region *entry, *new_entry, *msi = NULL;</div><div class='hunk'>@@ -969,9 +996,6 @@ static struct iommu_device *viommu_probe_device(struct device *dev)</div><div class='ctx'> 	struct viommu_dev *viommu = NULL;</div><div class='ctx'> 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='ctx'> </div><div class='del'>-	if (!fwspec || fwspec-&gt;ops != &amp;viommu_ops)</div><div class='del'>-		return ERR_PTR(-ENODEV);</div><div class='del'>-</div><div class='ctx'> 	viommu = viommu_get_by_fwnode(fwspec-&gt;iommu_fwnode);</div><div class='ctx'> 	if (!viommu)</div><div class='ctx'> 		return ERR_PTR(-ENODEV);</div><div class='hunk'>@@ -1037,6 +1061,8 @@ static bool viommu_capable(struct device *dev, enum iommu_cap cap)</div><div class='ctx'> 	switch (cap) {</div><div class='ctx'> 	case IOMMU_CAP_CACHE_COHERENCY:</div><div class='ctx'> 		return true;</div><div class='add'>+	case IOMMU_CAP_DEFERRED_FLUSH:</div><div class='add'>+		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1057,7 +1083,9 @@ static struct iommu_ops viommu_ops = {</div><div class='ctx'> 		.map_pages		= viommu_map_pages,</div><div class='ctx'> 		.unmap_pages		= viommu_unmap_pages,</div><div class='ctx'> 		.iova_to_phys		= viommu_iova_to_phys,</div><div class='add'>+		.flush_iotlb_all	= viommu_flush_iotlb_all,</div><div class='ctx'> 		.iotlb_sync		= viommu_iotlb_sync,</div><div class='add'>+		.iotlb_sync_map		= viommu_iotlb_sync_map,</div><div class='ctx'> 		.free			= viommu_domain_free,</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/ipack/devices/ipoctal.c b/drivers/ipack/devices/ipoctal.c<br/>index da308be6c487..ba2e9e52d72b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/ipack/devices/ipoctal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/ipack/devices/ipoctal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/ipack/devices/ipoctal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ipack/devices/ipoctal.c</a></div><div class='hunk'>@@ -158,9 +158,7 @@ static int ipoctal_get_icount(struct tty_struct *tty,</div><div class='ctx'> static void ipoctal_irq_rx(struct ipoctal_channel *channel, u8 sr)</div><div class='ctx'> {</div><div class='ctx'> 	struct tty_port *port = &amp;channel-&gt;tty_port;</div><div class='del'>-	unsigned char value;</div><div class='del'>-	unsigned char flag;</div><div class='del'>-	u8 isr;</div><div class='add'>+	u8 isr, value, flag;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		value = ioread8(&amp;channel-&gt;regs-&gt;r.rhr);</div><div class='hunk'>@@ -202,8 +200,8 @@ static void ipoctal_irq_rx(struct ipoctal_channel *channel, u8 sr)</div><div class='ctx'> </div><div class='ctx'> static void ipoctal_irq_tx(struct ipoctal_channel *channel)</div><div class='ctx'> {</div><div class='del'>-	unsigned char value;</div><div class='ctx'> 	unsigned int *pointer_write = &amp;channel-&gt;pointer_write;</div><div class='add'>+	u8 value;</div><div class='ctx'> </div><div class='ctx'> 	if (channel-&gt;nb_bytes == 0)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -436,11 +434,11 @@ err_put_driver:</div><div class='ctx'> 	return res;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int ipoctal_copy_write_buffer(struct ipoctal_channel *channel,</div><div class='del'>-					    const u8 *buf, int count)</div><div class='add'>+static inline size_t ipoctal_copy_write_buffer(struct ipoctal_channel *channel,</div><div class='add'>+					       const u8 *buf, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	int i;</div><div class='add'>+	size_t i;</div><div class='ctx'> 	unsigned int *pointer_read = &amp;channel-&gt;pointer_read;</div><div class='ctx'> </div><div class='ctx'> 	/* Copy the bytes from the user buffer to the internal one */</div><div class='hunk'>@@ -462,7 +460,7 @@ static ssize_t ipoctal_write_tty(struct tty_struct *tty, const u8 *buf,</div><div class='ctx'> 				 size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ipoctal_channel *channel = tty-&gt;driver_data;</div><div class='del'>-	unsigned int char_copied;</div><div class='add'>+	size_t char_copied;</div><div class='ctx'> </div><div class='ctx'> 	char_copied = ipoctal_copy_write_buffer(channel, buf, count);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/ipack/ipack.c b/drivers/ipack/ipack.c<br/>index cc1ecfd49928..b1471ba016a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/ipack/ipack.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/ipack/ipack.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/ipack/ipack.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/ipack/ipack.c</a></div><div class='hunk'>@@ -207,7 +207,7 @@ struct ipack_bus_device *ipack_bus_register(struct device *parent, int slots,</div><div class='ctx'> 	if (!bus)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	bus_nr = ida_simple_get(&amp;ipack_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	bus_nr = ida_alloc(&amp;ipack_ida, GFP_KERNEL);</div><div class='ctx'> 	if (bus_nr &lt; 0) {</div><div class='ctx'> 		kfree(bus);</div><div class='ctx'> 		return NULL;</div><div class='hunk'>@@ -237,7 +237,7 @@ int ipack_bus_unregister(struct ipack_bus_device *bus)</div><div class='ctx'> {</div><div class='ctx'> 	bus_for_each_dev(&amp;ipack_bus_type, NULL, bus,</div><div class='ctx'> 		ipack_unregister_bus_member);</div><div class='del'>-	ida_simple_remove(&amp;ipack_ida, bus-&gt;bus_nr);</div><div class='add'>+	ida_free(&amp;ipack_ida, bus-&gt;bus_nr);</div><div class='ctx'> 	kfree(bus);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c<br/>index 9a7a74239eab..d097001c1e3e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-gic-v3-its.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/irqchip/irq-gic-v3-its.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-gic-v3-its.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-gic-v3-its.c</a></div><div class='hunk'>@@ -2465,8 +2465,8 @@ static bool its_parse_indirect_baser(struct its_node *its,</div><div class='ctx'> 	 * feature is not supported by hardware.</div><div class='ctx'> 	 */</div><div class='ctx'> 	new_order = max_t(u32, get_order(esz &lt;&lt; ids), new_order);</div><div class='del'>-	if (new_order &gt; MAX_ORDER) {</div><div class='del'>-		new_order = MAX_ORDER;</div><div class='add'>+	if (new_order &gt; MAX_PAGE_ORDER) {</div><div class='add'>+		new_order = MAX_PAGE_ORDER;</div><div class='ctx'> 		ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);</div><div class='ctx'> 		pr_warn("ITS@%pa: %s Table too large, reduce ids %llu-&gt;%u\n",</div><div class='ctx'> 			&amp;its-&gt;phys_base, its_base_type_string[type],</div><div class='head'>diff --git a/drivers/irqchip/irq-gic-v4.c b/drivers/irqchip/irq-gic-v4.c<br/>index 94d56a03b175..ca32ac19d284 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-gic-v4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/irqchip/irq-gic-v4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-gic-v4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-gic-v4.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='ctx'> #include &lt;linux/irqdomain.h&gt;</div><div class='ctx'> #include &lt;linux/msi.h&gt;</div><div class='add'>+#include &lt;linux/pid.h&gt;</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/irqchip/arm-gic-v4.h&gt;</div><div class='head'>diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c<br/>index 7124565234a5..cda5838d2232 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-qcom-mpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/irqchip/irq-qcom-mpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-qcom-mpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-qcom-mpm.c</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include &lt;linux/mailbox_client.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_address.h&gt;</div><div class='ctx'> #include &lt;linux/of_platform.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/pm_domain.h&gt;</div><div class='hunk'>@@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct irq_domain *parent_domain;</div><div class='ctx'> 	struct generic_pm_domain *genpd;</div><div class='add'>+	struct device_node *msgram_np;</div><div class='ctx'> 	struct qcom_mpm_priv *priv;</div><div class='ctx'> 	unsigned int pin_cnt;</div><div class='add'>+	struct resource res;</div><div class='ctx'> 	int i, irq;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -374,9 +377,26 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)</div><div class='ctx'> </div><div class='ctx'> 	raw_spin_lock_init(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	priv-&gt;base = devm_platform_ioremap_resource(pdev, 0);</div><div class='del'>-	if (IS_ERR(priv-&gt;base))</div><div class='del'>-		return PTR_ERR(priv-&gt;base);</div><div class='add'>+	/* If we have a handle to an RPM message ram partition, use it. */</div><div class='add'>+	msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0);</div><div class='add'>+	if (msgram_np) {</div><div class='add'>+		ret = of_address_to_resource(msgram_np, 0, &amp;res);</div><div class='add'>+		if (ret) {</div><div class='add'>+			of_node_put(msgram_np);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Don't use devm_ioremap_resource, as we're accessing a shared region. */</div><div class='add'>+		priv-&gt;base = devm_ioremap(dev, res.start, resource_size(&amp;res));</div><div class='add'>+		of_node_put(msgram_np);</div><div class='add'>+		if (IS_ERR(priv-&gt;base))</div><div class='add'>+			return PTR_ERR(priv-&gt;base);</div><div class='add'>+	} else {</div><div class='add'>+		/* Otherwise, fall back to simple MMIO. */</div><div class='add'>+		priv-&gt;base = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+		if (IS_ERR(priv-&gt;base))</div><div class='add'>+			return PTR_ERR(priv-&gt;base);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;reg_stride; i++) {</div><div class='ctx'> 		qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);</div><div class='head'>diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c<br/>index fe8d516f3614..9494fc26259c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/irqchip/irq-renesas-rzg2l.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-renesas-rzg2l.c</a></div><div class='hunk'>@@ -18,6 +18,7 @@</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/reset.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/syscore_ops.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define IRQC_IRQ_START			1</div><div class='ctx'> #define IRQC_IRQ_COUNT			8</div><div class='hunk'>@@ -28,8 +29,7 @@</div><div class='ctx'> #define ISCR				0x10</div><div class='ctx'> #define IITSR				0x14</div><div class='ctx'> #define TSCR				0x20</div><div class='del'>-#define TITSR0				0x24</div><div class='del'>-#define TITSR1				0x28</div><div class='add'>+#define TITSR(n)			(0x24 + (n) * 4)</div><div class='ctx'> #define TITSR0_MAX_INT			16</div><div class='ctx'> #define TITSEL_WIDTH			0x2</div><div class='ctx'> #define TSSR(n)				(0x30 + ((n) * 4))</div><div class='hunk'>@@ -53,15 +53,33 @@</div><div class='ctx'> #define IITSR_IITSEL_EDGE_BOTH		3</div><div class='ctx'> #define IITSR_IITSEL_MASK(n)		IITSR_IITSEL((n), 3)</div><div class='ctx'> </div><div class='del'>-#define TINT_EXTRACT_HWIRQ(x)           FIELD_GET(GENMASK(15, 0), (x))</div><div class='del'>-#define TINT_EXTRACT_GPIOINT(x)         FIELD_GET(GENMASK(31, 16), (x))</div><div class='add'>+#define TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))</div><div class='add'>+#define TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))</div><div class='ctx'> </div><div class='del'>-struct rzg2l_irqc_priv {</div><div class='del'>-	void __iomem *base;</div><div class='del'>-	struct irq_fwspec fwspec[IRQC_NUM_IRQ];</div><div class='del'>-	raw_spinlock_t lock;</div><div class='add'>+/**</div><div class='add'>+ * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)</div><div class='add'>+ * @iitsr: IITSR register</div><div class='add'>+ * @titsr: TITSR registers</div><div class='add'>+ */</div><div class='add'>+struct rzg2l_irqc_reg_cache {</div><div class='add'>+	u32	iitsr;</div><div class='add'>+	u32	titsr[2];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct rzg2l_irqc_priv - IRQ controller private data structure</div><div class='add'>+ * @base:	Controller's base address</div><div class='add'>+ * @fwspec:	IRQ firmware specific data</div><div class='add'>+ * @lock:	Lock to serialize access to hardware registers</div><div class='add'>+ * @cache:	Registers cache for suspend/resume</div><div class='add'>+ */</div><div class='add'>+static struct rzg2l_irqc_priv {</div><div class='add'>+	void __iomem			*base;</div><div class='add'>+	struct irq_fwspec		fwspec[IRQC_NUM_IRQ];</div><div class='add'>+	raw_spinlock_t			lock;</div><div class='add'>+	struct rzg2l_irqc_reg_cache	cache;</div><div class='add'>+} *rzg2l_irqc_data;</div><div class='add'>+</div><div class='ctx'> static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)</div><div class='ctx'> {</div><div class='ctx'> 	return data-&gt;domain-&gt;host_data;</div><div class='hunk'>@@ -72,11 +90,17 @@ static void rzg2l_irq_eoi(struct irq_data *d)</div><div class='ctx'> 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;</div><div class='ctx'> 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);</div><div class='ctx'> 	u32 bit = BIT(hw_irq);</div><div class='del'>-	u32 reg;</div><div class='add'>+	u32 iitsr, iscr;</div><div class='ctx'> </div><div class='del'>-	reg = readl_relaxed(priv-&gt;base + ISCR);</div><div class='del'>-	if (reg &amp; bit)</div><div class='del'>-		writel_relaxed(reg &amp; ~bit, priv-&gt;base + ISCR);</div><div class='add'>+	iscr = readl_relaxed(priv-&gt;base + ISCR);</div><div class='add'>+	iitsr = readl_relaxed(priv-&gt;base + IITSR);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * ISCR can only be cleared if the type is falling-edge, rising-edge or</div><div class='add'>+	 * falling/rising-edge.</div><div class='add'>+	 */</div><div class='add'>+	if ((iscr &amp; bit) &amp;&amp; (iitsr &amp; IITSR_IITSEL_MASK(hw_irq)))</div><div class='add'>+		writel_relaxed(iscr &amp; ~bit, priv-&gt;base + ISCR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rzg2l_tint_eoi(struct irq_data *d)</div><div class='hunk'>@@ -188,8 +212,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)</div><div class='ctx'> 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);</div><div class='ctx'> 	unsigned int hwirq = irqd_to_hwirq(d);</div><div class='ctx'> 	u32 titseln = hwirq - IRQC_TINT_START;</div><div class='del'>-	u32 offset;</div><div class='del'>-	u8 sense;</div><div class='add'>+	u8 index, sense;</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	switch (type &amp; IRQ_TYPE_SENSE_MASK) {</div><div class='hunk'>@@ -205,17 +228,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	offset = TITSR0;</div><div class='add'>+	index = 0;</div><div class='ctx'> 	if (titseln &gt;= TITSR0_MAX_INT) {</div><div class='ctx'> 		titseln -= TITSR0_MAX_INT;</div><div class='del'>-		offset = TITSR1;</div><div class='add'>+		index = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	raw_spin_lock(&amp;priv-&gt;lock);</div><div class='del'>-	reg = readl_relaxed(priv-&gt;base + offset);</div><div class='add'>+	reg = readl_relaxed(priv-&gt;base + TITSR(index));</div><div class='ctx'> 	reg &amp;= ~(IRQ_MASK &lt;&lt; (titseln * TITSEL_WIDTH));</div><div class='ctx'> 	reg |= sense &lt;&lt; (titseln * TITSEL_WIDTH);</div><div class='del'>-	writel_relaxed(reg, priv-&gt;base + offset);</div><div class='add'>+	writel_relaxed(reg, priv-&gt;base + TITSR(index));</div><div class='ctx'> 	raw_spin_unlock(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -236,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)</div><div class='ctx'> 	return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int rzg2l_irqc_irq_suspend(void)</div><div class='add'>+{</div><div class='add'>+	struct rzg2l_irqc_reg_cache *cache = &amp;rzg2l_irqc_data-&gt;cache;</div><div class='add'>+	void __iomem *base = rzg2l_irqc_data-&gt;base;</div><div class='add'>+</div><div class='add'>+	cache-&gt;iitsr = readl_relaxed(base + IITSR);</div><div class='add'>+	for (u8 i = 0; i &lt; 2; i++)</div><div class='add'>+		cache-&gt;titsr[i] = readl_relaxed(base + TITSR(i));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rzg2l_irqc_irq_resume(void)</div><div class='add'>+{</div><div class='add'>+	struct rzg2l_irqc_reg_cache *cache = &amp;rzg2l_irqc_data-&gt;cache;</div><div class='add'>+	void __iomem *base = rzg2l_irqc_data-&gt;base;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Restore only interrupt type. TSSRx will be restored at the</div><div class='add'>+	 * request of pin controller to avoid spurious interrupts due</div><div class='add'>+	 * to invalid PIN states.</div><div class='add'>+	 */</div><div class='add'>+	for (u8 i = 0; i &lt; 2; i++)</div><div class='add'>+		writel_relaxed(cache-&gt;titsr[i], base + TITSR(i));</div><div class='add'>+	writel_relaxed(cache-&gt;iitsr, base + IITSR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct syscore_ops rzg2l_irqc_syscore_ops = {</div><div class='add'>+	.suspend	= rzg2l_irqc_irq_suspend,</div><div class='add'>+	.resume		= rzg2l_irqc_irq_resume,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct irq_chip irqc_chip = {</div><div class='ctx'> 	.name			= "rzg2l-irqc",</div><div class='ctx'> 	.irq_eoi		= rzg2l_irqc_eoi,</div><div class='hunk'>@@ -321,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)</div><div class='ctx'> 	struct irq_domain *irq_domain, *parent_domain;</div><div class='ctx'> 	struct platform_device *pdev;</div><div class='ctx'> 	struct reset_control *resetn;</div><div class='del'>-	struct rzg2l_irqc_priv *priv;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	pdev = of_find_device_by_node(node);</div><div class='hunk'>@@ -334,15 +388,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	priv = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*priv), GFP_KERNEL);</div><div class='del'>-	if (!priv)</div><div class='add'>+	rzg2l_irqc_data = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL);</div><div class='add'>+	if (!rzg2l_irqc_data)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	priv-&gt;base = devm_of_iomap(&amp;pdev-&gt;dev, pdev-&gt;dev.of_node, 0, NULL);</div><div class='del'>-	if (IS_ERR(priv-&gt;base))</div><div class='del'>-		return PTR_ERR(priv-&gt;base);</div><div class='add'>+	rzg2l_irqc_data-&gt;base = devm_of_iomap(&amp;pdev-&gt;dev, pdev-&gt;dev.of_node, 0, NULL);</div><div class='add'>+	if (IS_ERR(rzg2l_irqc_data-&gt;base))</div><div class='add'>+		return PTR_ERR(rzg2l_irqc_data-&gt;base);</div><div class='ctx'> </div><div class='del'>-	ret = rzg2l_irqc_parse_interrupts(priv, node);</div><div class='add'>+	ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "cannot parse interrupts: %d\n", ret);</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -365,17 +419,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)</div><div class='ctx'> 		goto pm_disable;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	raw_spin_lock_init(&amp;priv-&gt;lock);</div><div class='add'>+	raw_spin_lock_init(&amp;rzg2l_irqc_data-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,</div><div class='ctx'> 					      node, &amp;rzg2l_irqc_domain_ops,</div><div class='del'>-					      priv);</div><div class='add'>+					      rzg2l_irqc_data);</div><div class='ctx'> 	if (!irq_domain) {</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "failed to add irq domain\n");</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='ctx'> 		goto pm_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	register_syscore_ops(&amp;rzg2l_irqc_syscore_ops);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> pm_put:</div><div class='head'>diff --git a/drivers/irqchip/irq-xtensa-pic.c b/drivers/irqchip/irq-xtensa-pic.c<br/>index 0c18d1f1e264..f9d6fce4da33 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-xtensa-pic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/irqchip/irq-xtensa-pic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/irqchip/irq-xtensa-pic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/irqchip/irq-xtensa-pic.c</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'>  * Kevin Chea</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/irqdomain.h&gt;</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='hunk'>@@ -19,8 +20,6 @@</div><div class='ctx'> #include &lt;linux/irqchip/xtensa-pic.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> </div><div class='del'>-unsigned int cached_irq_mask;</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Device Tree IRQ specifier translation function which works with one or</div><div class='ctx'>  * two cell bindings. First cell value maps directly to the hwirq number.</div><div class='hunk'>@@ -44,34 +43,30 @@ static const struct irq_domain_ops xtensa_irq_domain_ops = {</div><div class='ctx'> </div><div class='ctx'> static void xtensa_irq_mask(struct irq_data *d)</div><div class='ctx'> {</div><div class='del'>-	cached_irq_mask &amp;= ~(1 &lt;&lt; d-&gt;hwirq);</div><div class='del'>-	xtensa_set_sr(cached_irq_mask, intenable);</div><div class='del'>-}</div><div class='add'>+	u32 irq_mask;</div><div class='ctx'> </div><div class='del'>-static void xtensa_irq_unmask(struct irq_data *d)</div><div class='del'>-{</div><div class='del'>-	cached_irq_mask |= 1 &lt;&lt; d-&gt;hwirq;</div><div class='del'>-	xtensa_set_sr(cached_irq_mask, intenable);</div><div class='add'>+	irq_mask = xtensa_get_sr(intenable);</div><div class='add'>+	irq_mask &amp;= ~BIT(d-&gt;hwirq);</div><div class='add'>+	xtensa_set_sr(irq_mask, intenable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void xtensa_irq_enable(struct irq_data *d)</div><div class='add'>+static void xtensa_irq_unmask(struct irq_data *d)</div><div class='ctx'> {</div><div class='del'>-	xtensa_irq_unmask(d);</div><div class='del'>-}</div><div class='add'>+	u32 irq_mask;</div><div class='ctx'> </div><div class='del'>-static void xtensa_irq_disable(struct irq_data *d)</div><div class='del'>-{</div><div class='del'>-	xtensa_irq_mask(d);</div><div class='add'>+	irq_mask = xtensa_get_sr(intenable);</div><div class='add'>+	irq_mask |= BIT(d-&gt;hwirq);</div><div class='add'>+	xtensa_set_sr(irq_mask, intenable);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void xtensa_irq_ack(struct irq_data *d)</div><div class='ctx'> {</div><div class='del'>-	xtensa_set_sr(1 &lt;&lt; d-&gt;hwirq, intclear);</div><div class='add'>+	xtensa_set_sr(BIT(d-&gt;hwirq), intclear);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int xtensa_irq_retrigger(struct irq_data *d)</div><div class='ctx'> {</div><div class='del'>-	unsigned int mask = 1u &lt;&lt; d-&gt;hwirq;</div><div class='add'>+	unsigned int mask = BIT(d-&gt;hwirq);</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(mask &amp; ~XCHAL_INTTYPE_MASK_SOFTWARE))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -81,8 +76,6 @@ static int xtensa_irq_retrigger(struct irq_data *d)</div><div class='ctx'> </div><div class='ctx'> static struct irq_chip xtensa_irq_chip = {</div><div class='ctx'> 	.name		= "xtensa",</div><div class='del'>-	.irq_enable	= xtensa_irq_enable,</div><div class='del'>-	.irq_disable	= xtensa_irq_disable,</div><div class='ctx'> 	.irq_mask	= xtensa_irq_mask,</div><div class='ctx'> 	.irq_unmask	= xtensa_irq_unmask,</div><div class='ctx'> 	.irq_ack	= xtensa_irq_ack,</div><div class='head'>diff --git a/drivers/isdn/capi/capi.c b/drivers/isdn/capi/capi.c<br/>index 2f3789515445..6e80d7bd3c4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/isdn/capi/capi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/isdn/capi/capi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/isdn/capi/capi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/isdn/capi/capi.c</a></div><div class='hunk'>@@ -1231,9 +1231,9 @@ static void capinc_tty_hangup(struct tty_struct *tty)</div><div class='ctx'> 	tty_port_hangup(&amp;mp-&gt;port);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void capinc_tty_send_xchar(struct tty_struct *tty, char ch)</div><div class='add'>+static void capinc_tty_send_xchar(struct tty_struct *tty, u8 ch)</div><div class='ctx'> {</div><div class='del'>-	pr_debug("capinc_tty_send_xchar(%d)\n", ch);</div><div class='add'>+	pr_debug("capinc_tty_send_xchar(%u)\n", ch);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct tty_operations capinc_ops = {</div><div class='head'>diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig<br/>index 6292fddcc55c..d721b254e1e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/Kconfig</a></div><div class='hunk'>@@ -95,14 +95,18 @@ config LEDS_ARIEL</div><div class='ctx'> 	  Say Y to if your machine is a Dell Wyse 3020 thin client.</div><div class='ctx'> </div><div class='ctx'> config LEDS_AW200XX</div><div class='del'>-	tristate "LED support for Awinic AW20036/AW20054/AW20072"</div><div class='add'>+	tristate "LED support for Awinic AW20036/AW20054/AW20072/AW20108"</div><div class='ctx'> 	depends on LEDS_CLASS</div><div class='ctx'> 	depends on I2C</div><div class='ctx'> 	help</div><div class='del'>-	  This option enables support for the AW20036/AW20054/AW20072 LED driver.</div><div class='del'>-	  It is a 3x12/6x9/6x12 matrix LED driver programmed via</div><div class='del'>-	  an I2C interface, up to 36/54/72 LEDs or 12/18/24 RGBs,</div><div class='del'>-	  3 pattern controllers for auto breathing or group dimming control.</div><div class='add'>+	  This option enables support for the Awinic AW200XX LED controllers.</div><div class='add'>+	  It is a matrix LED driver programmed via an I2C interface. Devices have</div><div class='add'>+	  a set of individually controlled LEDs and support 3 pattern controllers</div><div class='add'>+	  for auto breathing or group dimming control. Supported devices:</div><div class='add'>+	    - AW20036 (3x12) 36 LEDs</div><div class='add'>+	    - AW20054 (6x9)  54 LEDs</div><div class='add'>+	    - AW20072 (6x12) 72 LEDs</div><div class='add'>+	    - AW20108 (9x12) 108 LEDs</div><div class='ctx'> </div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module</div><div class='ctx'> 	  will be called leds-aw200xx.</div><div class='hunk'>@@ -110,6 +114,7 @@ config LEDS_AW200XX</div><div class='ctx'> config LEDS_AW2013</div><div class='ctx'> 	tristate "LED support for Awinic AW2013"</div><div class='ctx'> 	depends on LEDS_CLASS &amp;&amp; I2C &amp;&amp; OF</div><div class='add'>+	select REGMAP_I2C</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option enables support for the AW2013 3-channel</div><div class='ctx'> 	  LED driver.</div><div class='hunk'>@@ -298,6 +303,15 @@ config LEDS_COBALT_RAQ</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option enables support for the Cobalt Raq series LEDs.</div><div class='ctx'> </div><div class='add'>+config LEDS_SUN50I_A100</div><div class='add'>+	tristate "LED support for Allwinner A100 RGB LED controller"</div><div class='add'>+	depends on LEDS_CLASS_MULTICOLOR</div><div class='add'>+	depends on ARCH_SUNXI || COMPILE_TEST</div><div class='add'>+	help</div><div class='add'>+	  This option enables support for the RGB LED controller found</div><div class='add'>+	  in some Allwinner sunxi SoCs, including A100, R329, and D1.</div><div class='add'>+	  It uses a one-wire interface to control up to 1024 LEDs.</div><div class='add'>+</div><div class='ctx'> config LEDS_SUNFIRE</div><div class='ctx'> 	tristate "LED support for SunFire servers."</div><div class='ctx'> 	depends on LEDS_CLASS</div><div class='hunk'>@@ -638,6 +652,17 @@ config LEDS_ADP5520</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module will</div><div class='ctx'> 	  be called leds-adp5520.</div><div class='ctx'> </div><div class='add'>+config LEDS_MAX5970</div><div class='add'>+	tristate "LED Support for Maxim 5970"</div><div class='add'>+	depends on LEDS_CLASS</div><div class='add'>+	depends on MFD_MAX5970</div><div class='add'>+	help</div><div class='add'>+	  This option enables support for the Maxim MAX5970 &amp; MAX5978 smart</div><div class='add'>+	  switch indication LEDs via the I2C bus.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module will</div><div class='add'>+	  be called leds-max5970.</div><div class='add'>+</div><div class='ctx'> config LEDS_MC13783</div><div class='ctx'> 	tristate "LED Support for MC13XXX PMIC"</div><div class='ctx'> 	depends on LEDS_CLASS</div><div class='head'>diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile<br/>index d7348e8bc019..ce07dc295ff0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/Makefile</a></div><div class='hunk'>@@ -56,6 +56,7 @@ obj-$(CONFIG_LEDS_LP8501)		+= leds-lp8501.o</div><div class='ctx'> obj-$(CONFIG_LEDS_LP8788)		+= leds-lp8788.o</div><div class='ctx'> obj-$(CONFIG_LEDS_LP8860)		+= leds-lp8860.o</div><div class='ctx'> obj-$(CONFIG_LEDS_LT3593)		+= leds-lt3593.o</div><div class='add'>+obj-$(CONFIG_LEDS_MAX5970)		+= leds-max5970.o</div><div class='ctx'> obj-$(CONFIG_LEDS_MAX77650)		+= leds-max77650.o</div><div class='ctx'> obj-$(CONFIG_LEDS_MAX8997)		+= leds-max8997.o</div><div class='ctx'> obj-$(CONFIG_LEDS_MC13783)		+= leds-mc13783.o</div><div class='hunk'>@@ -78,6 +79,7 @@ obj-$(CONFIG_LEDS_POWERNV)		+= leds-powernv.o</div><div class='ctx'> obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o</div><div class='ctx'> obj-$(CONFIG_LEDS_REGULATOR)		+= leds-regulator.o</div><div class='ctx'> obj-$(CONFIG_LEDS_SC27XX_BLTC)		+= leds-sc27xx-bltc.o</div><div class='add'>+obj-$(CONFIG_LEDS_SUN50I_A100)		+= leds-sun50i-a100.o</div><div class='ctx'> obj-$(CONFIG_LEDS_SUNFIRE)		+= leds-sunfire.o</div><div class='ctx'> obj-$(CONFIG_LEDS_SYSCON)		+= leds-syscon.o</div><div class='ctx'> obj-$(CONFIG_LEDS_TCA6507)		+= leds-tca6507.o</div><div class='head'>diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c<br/>index 974b84f6bd6a..ba1be15cfd8e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/led-class.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/led-class.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/led-class.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/led-class.c</a></div><div class='hunk'>@@ -75,19 +75,6 @@ static ssize_t max_brightness_show(struct device *dev,</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RO(max_brightness);</div><div class='ctx'> </div><div class='del'>-static ssize_t color_show(struct device *dev,</div><div class='del'>-		struct device_attribute *attr, char *buf)</div><div class='del'>-{</div><div class='del'>-	const char *color_text = "invalid";</div><div class='del'>-	struct led_classdev *led_cdev = dev_get_drvdata(dev);</div><div class='del'>-</div><div class='del'>-	if (led_cdev-&gt;color &lt; LED_COLOR_ID_MAX)</div><div class='del'>-		color_text = led_colors[led_cdev-&gt;color];</div><div class='del'>-</div><div class='del'>-	return sysfs_emit(buf, "%s\n", color_text);</div><div class='del'>-}</div><div class='del'>-static DEVICE_ATTR_RO(color);</div><div class='del'>-</div><div class='ctx'> #ifdef CONFIG_LEDS_TRIGGERS</div><div class='ctx'> static BIN_ATTR(trigger, 0644, led_trigger_read, led_trigger_write, 0);</div><div class='ctx'> static struct bin_attribute *led_trigger_bin_attrs[] = {</div><div class='hunk'>@@ -102,7 +89,6 @@ static const struct attribute_group led_trigger_group = {</div><div class='ctx'> static struct attribute *led_class_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_brightness.attr,</div><div class='ctx'> 	&amp;dev_attr_max_brightness.attr,</div><div class='del'>-	&amp;dev_attr_color.attr,</div><div class='ctx'> 	NULL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c<br/>index 6a5e1f41f9a4..bd59a14a4a90 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/led-triggers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/led-triggers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/led-triggers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/led-triggers.c</a></div><div class='hunk'>@@ -269,19 +269,6 @@ void led_trigger_set_default(struct led_classdev *led_cdev)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(led_trigger_set_default);</div><div class='ctx'> </div><div class='del'>-void led_trigger_rename_static(const char *name, struct led_trigger *trig)</div><div class='del'>-{</div><div class='del'>-	/* new name must be on a temporary string to prevent races */</div><div class='del'>-	BUG_ON(name == trig-&gt;name);</div><div class='del'>-</div><div class='del'>-	down_write(&amp;triggers_list_lock);</div><div class='del'>-	/* this assumes that trig-&gt;name was originaly allocated to</div><div class='del'>-	 * non constant storage */</div><div class='del'>-	strcpy((char *)trig-&gt;name, name);</div><div class='del'>-	up_write(&amp;triggers_list_lock);</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(led_trigger_rename_static);</div><div class='del'>-</div><div class='ctx'> /* LED Trigger Interface */</div><div class='ctx'> </div><div class='ctx'> int led_trigger_register(struct led_trigger *trig)</div><div class='head'>diff --git a/drivers/leds/leds-aw200xx.c b/drivers/leds/leds-aw200xx.c<br/>index 14ca236ce29e..f584a7f98fc5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/leds-aw200xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/leds-aw200xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-aw200xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-aw200xx.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /*</div><div class='del'>- * Awinic AW20036/AW20054/AW20072 LED driver</div><div class='add'>+ * Awinic AW20036/AW20054/AW20072/AW20108 LED driver</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (c) 2023, SberDevices. All Rights Reserved.</div><div class='ctx'>  *</div><div class='hunk'>@@ -10,6 +10,7 @@</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/bits.h&gt;</div><div class='ctx'> #include &lt;linux/container_of.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/leds.h&gt;</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='hunk'>@@ -74,6 +75,10 @@</div><div class='ctx'> #define AW200XX_LED2REG(x, columns) \</div><div class='ctx'> 	((x) + (((x) / (columns)) * (AW200XX_DSIZE_COLUMNS_MAX - (columns))))</div><div class='ctx'> </div><div class='add'>+/* DIM current configuration register on page 1 */</div><div class='add'>+#define AW200XX_REG_DIM_PAGE1(x, columns) \</div><div class='add'>+	AW200XX_REG(AW200XX_PAGE1, AW200XX_LED2REG(x, columns))</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * DIM current configuration register (page 4).</div><div class='ctx'>  * The even address for current DIM configuration.</div><div class='hunk'>@@ -82,6 +87,8 @@</div><div class='ctx'> #define AW200XX_REG_DIM(x, columns) \</div><div class='ctx'> 	AW200XX_REG(AW200XX_PAGE4, AW200XX_LED2REG(x, columns) * 2)</div><div class='ctx'> #define AW200XX_REG_DIM2FADE(x) ((x) + 1)</div><div class='add'>+#define AW200XX_REG_FADE2DIM(fade) \</div><div class='add'>+	DIV_ROUND_UP((fade) * AW200XX_DIM_MAX, AW200XX_FADE_MAX)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Duty ratio of display scan (see p.15 of datasheet for formula):</div><div class='hunk'>@@ -112,6 +119,7 @@ struct aw200xx {</div><div class='ctx'> 	struct mutex mutex;</div><div class='ctx'> 	u32 num_leds;</div><div class='ctx'> 	u32 display_rows;</div><div class='add'>+	struct gpio_desc *hwen;</div><div class='ctx'> 	struct aw200xx_led leds[] __counted_by(num_leds);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -153,7 +161,8 @@ static ssize_t dim_store(struct device *dev, struct device_attribute *devattr,</div><div class='ctx'> </div><div class='ctx'> 	if (dim &gt;= 0) {</div><div class='ctx'> 		ret = regmap_write(chip-&gt;regmap,</div><div class='del'>-				   AW200XX_REG_DIM(led-&gt;num, columns), dim);</div><div class='add'>+				   AW200XX_REG_DIM_PAGE1(led-&gt;num, columns),</div><div class='add'>+				   dim);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto out_unlock;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -188,9 +197,7 @@ static int aw200xx_brightness_set(struct led_classdev *cdev,</div><div class='ctx'> </div><div class='ctx'> 	dim = led-&gt;dim;</div><div class='ctx'> 	if (dim &lt; 0)</div><div class='del'>-		dim = max_t(int,</div><div class='del'>-			    brightness / (AW200XX_FADE_MAX / AW200XX_DIM_MAX),</div><div class='del'>-			    1);</div><div class='add'>+		dim = AW200XX_REG_FADE2DIM(brightness);</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_write(chip-&gt;regmap, reg, dim);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -314,6 +321,9 @@ static int aw200xx_chip_reset(const struct aw200xx *const chip)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	/* According to the datasheet software reset takes at least 1ms */</div><div class='add'>+	fsleep(1000);</div><div class='add'>+</div><div class='ctx'> 	regcache_mark_dirty(chip-&gt;regmap);</div><div class='ctx'> 	return regmap_write(chip-&gt;regmap, AW200XX_REG_FCD, AW200XX_FCD_CLEAR);</div><div class='ctx'> }</div><div class='hunk'>@@ -353,6 +363,50 @@ static int aw200xx_chip_check(const struct aw200xx *const chip)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void aw200xx_enable(const struct aw200xx *const chip)</div><div class='add'>+{</div><div class='add'>+	gpiod_set_value_cansleep(chip-&gt;hwen, 1);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * After HWEN pin set high the chip begins to load the OTP information,</div><div class='add'>+	 * which takes 200us to complete. About 200us wait time is needed for</div><div class='add'>+	 * internal oscillator startup and display SRAM initialization. After</div><div class='add'>+	 * display SRAM initialization, the registers in page1 to page5 can be</div><div class='add'>+	 * configured via i2c interface.</div><div class='add'>+	 */</div><div class='add'>+	fsleep(400);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void aw200xx_disable(const struct aw200xx *const chip)</div><div class='add'>+{</div><div class='add'>+	return gpiod_set_value_cansleep(chip-&gt;hwen, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aw200xx_probe_get_display_rows(struct device *dev,</div><div class='add'>+					  struct aw200xx *chip)</div><div class='add'>+{</div><div class='add'>+	struct fwnode_handle *child;</div><div class='add'>+	u32 max_source = 0;</div><div class='add'>+</div><div class='add'>+	device_for_each_child_node(dev, child) {</div><div class='add'>+		u32 source;</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		ret = fwnode_property_read_u32(child, "reg", &amp;source);</div><div class='add'>+		if (ret || source &gt;= chip-&gt;cdef-&gt;channels)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		max_source = max(max_source, source);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (max_source == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	chip-&gt;display_rows = max_source / chip-&gt;cdef-&gt;display_size_columns + 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int aw200xx_probe_fw(struct device *dev, struct aw200xx *chip)</div><div class='ctx'> {</div><div class='ctx'> 	struct fwnode_handle *child;</div><div class='hunk'>@@ -360,18 +414,10 @@ static int aw200xx_probe_fw(struct device *dev, struct aw200xx *chip)</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	ret = device_property_read_u32(dev, "awinic,display-rows",</div><div class='del'>-				       &amp;chip-&gt;display_rows);</div><div class='add'>+	ret = aw200xx_probe_get_display_rows(dev, chip);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return dev_err_probe(dev, ret,</div><div class='del'>-				     "Failed to read 'display-rows' property\n");</div><div class='del'>-</div><div class='del'>-	if (!chip-&gt;display_rows ||</div><div class='del'>-	    chip-&gt;display_rows &gt; chip-&gt;cdef-&gt;display_size_rows_max) {</div><div class='del'>-		return dev_err_probe(dev, -EINVAL,</div><div class='del'>-				     "Invalid leds display size %u\n",</div><div class='del'>-				     chip-&gt;display_rows);</div><div class='del'>-	}</div><div class='add'>+				     "No valid led definitions found\n");</div><div class='ctx'> </div><div class='ctx'> 	current_max = aw200xx_imax_from_global(chip, AW200XX_IMAX_MAX_uA);</div><div class='ctx'> 	current_min = aw200xx_imax_from_global(chip, AW200XX_IMAX_MIN_uA);</div><div class='hunk'>@@ -416,6 +462,7 @@ static int aw200xx_probe_fw(struct device *dev, struct aw200xx *chip)</div><div class='ctx'> 		led-&gt;num = source;</div><div class='ctx'> 		led-&gt;chip = chip;</div><div class='ctx'> 		led-&gt;cdev.brightness_set_blocking = aw200xx_brightness_set;</div><div class='add'>+		led-&gt;cdev.max_brightness = AW200XX_FADE_MAX;</div><div class='ctx'> 		led-&gt;cdev.groups = dim_groups;</div><div class='ctx'> 		init_data.fwnode = child;</div><div class='ctx'> </div><div class='hunk'>@@ -480,6 +527,7 @@ static const struct regmap_config aw200xx_regmap_config = {</div><div class='ctx'> 	.rd_table = &amp;aw200xx_readable_table,</div><div class='ctx'> 	.wr_table = &amp;aw200xx_writeable_table,</div><div class='ctx'> 	.cache_type = REGCACHE_MAPLE,</div><div class='add'>+	.disable_locking = true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int aw200xx_probe(struct i2c_client *client)</div><div class='hunk'>@@ -512,6 +560,14 @@ static int aw200xx_probe(struct i2c_client *client)</div><div class='ctx'> 	if (IS_ERR(chip-&gt;regmap))</div><div class='ctx'> 		return PTR_ERR(chip-&gt;regmap);</div><div class='ctx'> </div><div class='add'>+	chip-&gt;hwen = devm_gpiod_get_optional(&amp;client-&gt;dev, "enable",</div><div class='add'>+					     GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(chip-&gt;hwen))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(chip-&gt;hwen),</div><div class='add'>+				     "Cannot get enable GPIO");</div><div class='add'>+</div><div class='add'>+	aw200xx_enable(chip);</div><div class='add'>+</div><div class='ctx'> 	ret = aw200xx_chip_check(chip);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -532,6 +588,9 @@ static int aw200xx_probe(struct i2c_client *client)</div><div class='ctx'> 	ret = aw200xx_chip_init(chip);</div><div class='ctx'> </div><div class='ctx'> out_unlock:</div><div class='add'>+	if (ret)</div><div class='add'>+		aw200xx_disable(chip);</div><div class='add'>+</div><div class='ctx'> 	mutex_unlock(&amp;chip-&gt;mutex);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -541,6 +600,7 @@ static void aw200xx_remove(struct i2c_client *client)</div><div class='ctx'> 	struct aw200xx *chip = i2c_get_clientdata(client);</div><div class='ctx'> </div><div class='ctx'> 	aw200xx_chip_reset(chip);</div><div class='add'>+	aw200xx_disable(chip);</div><div class='ctx'> 	mutex_destroy(&amp;chip-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -562,10 +622,17 @@ static const struct aw200xx_chipdef aw20072_cdef = {</div><div class='ctx'> 	.display_size_columns = 12,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct aw200xx_chipdef aw20108_cdef = {</div><div class='add'>+	.channels = 108,</div><div class='add'>+	.display_size_rows_max = 9,</div><div class='add'>+	.display_size_columns = 12,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct i2c_device_id aw200xx_id[] = {</div><div class='ctx'> 	{ "aw20036" },</div><div class='ctx'> 	{ "aw20054" },</div><div class='ctx'> 	{ "aw20072" },</div><div class='add'>+	{ "aw20108" },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, aw200xx_id);</div><div class='hunk'>@@ -574,6 +641,7 @@ static const struct of_device_id aw200xx_match_table[] = {</div><div class='ctx'> 	{ .compatible = "awinic,aw20036", .data = &amp;aw20036_cdef, },</div><div class='ctx'> 	{ .compatible = "awinic,aw20054", .data = &amp;aw20054_cdef, },</div><div class='ctx'> 	{ .compatible = "awinic,aw20072", .data = &amp;aw20072_cdef, },</div><div class='add'>+	{ .compatible = "awinic,aw20108", .data = &amp;aw20108_cdef, },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, aw200xx_match_table);</div><div class='head'>diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c<br/>index 710c319ad312..83fcd7b6afff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/leds-gpio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/leds-gpio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-gpio.c</a></div><div class='hunk'>@@ -172,6 +172,8 @@ static struct gpio_leds_priv *gpio_leds_create(struct device *dev)</div><div class='ctx'> 		led.gpiod = devm_fwnode_gpiod_get(dev, child, NULL, GPIOD_ASIS,</div><div class='ctx'> 						  NULL);</div><div class='ctx'> 		if (IS_ERR(led.gpiod)) {</div><div class='add'>+			dev_err_probe(dev, PTR_ERR(led.gpiod), "Failed to get GPIO '%pfw'\n",</div><div class='add'>+				      child);</div><div class='ctx'> 			fwnode_handle_put(child);</div><div class='ctx'> 			return ERR_CAST(led.gpiod);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/leds/leds-max5970.c b/drivers/leds/leds-max5970.c<br/>new file mode 100644<br/>index 000000000000..56a584311581<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-max5970.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-max5970.c</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Device driver for leds in MAX5970 and MAX5978 IC</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2022 9elements GmbH</div><div class='add'>+ *</div><div class='add'>+ * Author: Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/container_of.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/leds.h&gt;</div><div class='add'>+#include &lt;linux/mfd/max5970.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+</div><div class='add'>+#define ldev_to_maxled(c)       container_of(c, struct max5970_led, cdev)</div><div class='add'>+</div><div class='add'>+struct max5970_led {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct led_classdev cdev;</div><div class='add'>+	unsigned int index;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int max5970_led_set_brightness(struct led_classdev *cdev,</div><div class='add'>+				      enum led_brightness brightness)</div><div class='add'>+{</div><div class='add'>+	struct max5970_led *ddata = ldev_to_maxled(cdev);</div><div class='add'>+	int ret, val;</div><div class='add'>+</div><div class='add'>+	/* Set/clear corresponding bit for given led index */</div><div class='add'>+	val = !brightness ? BIT(ddata-&gt;index) : 0;</div><div class='add'>+</div><div class='add'>+	ret = regmap_update_bits(ddata-&gt;regmap, MAX5970_REG_LED_FLASH, BIT(ddata-&gt;index), val);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(cdev-&gt;dev, "failed to set brightness %d", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int max5970_led_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct fwnode_handle *led_node, *child;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct max5970_led *ddata;</div><div class='add'>+	int ret = -ENODEV;</div><div class='add'>+</div><div class='add'>+	regmap = dev_get_regmap(dev-&gt;parent, NULL);</div><div class='add'>+	if (!regmap)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	led_node = device_get_named_child_node(dev-&gt;parent, "leds");</div><div class='add'>+	if (!led_node)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	fwnode_for_each_available_child_node(led_node, child) {</div><div class='add'>+		u32 reg;</div><div class='add'>+</div><div class='add'>+		if (fwnode_property_read_u32(child, "reg", &amp;reg))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (reg &gt;= MAX5970_NUM_LEDS) {</div><div class='add'>+			dev_err_probe(dev, -EINVAL, "invalid LED (%u &gt;= %d)\n", reg, MAX5970_NUM_LEDS);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);</div><div class='add'>+		if (!ddata) {</div><div class='add'>+			fwnode_handle_put(child);</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ddata-&gt;index = reg;</div><div class='add'>+		ddata-&gt;regmap = regmap;</div><div class='add'>+		ddata-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+		if (fwnode_property_read_string(child, "label", &amp;ddata-&gt;cdev.name))</div><div class='add'>+			ddata-&gt;cdev.name = fwnode_get_name(child);</div><div class='add'>+</div><div class='add'>+		ddata-&gt;cdev.max_brightness = 1;</div><div class='add'>+		ddata-&gt;cdev.brightness_set_blocking = max5970_led_set_brightness;</div><div class='add'>+		ddata-&gt;cdev.default_trigger = "none";</div><div class='add'>+</div><div class='add'>+		ret = devm_led_classdev_register(dev, &amp;ddata-&gt;cdev);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			fwnode_handle_put(child);</div><div class='add'>+			return dev_err_probe(dev, ret, "Failed to initialize LED %u\n", reg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct platform_driver max5970_led_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "max5970-led",</div><div class='add'>+	},</div><div class='add'>+	.probe = max5970_led_probe,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(max5970_led_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Naresh Solanki &lt;Naresh.Solanki@9elements.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("MAX5970_hot-swap controller LED driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c<br/>index 2b3bf1353b70..4e3936a39d0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/leds-pwm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/leds-pwm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-pwm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-pwm.c</a></div><div class='hunk'>@@ -54,7 +54,7 @@ static int led_pwm_set(struct led_classdev *led_cdev,</div><div class='ctx'> </div><div class='ctx'> 	led_dat-&gt;pwmstate.duty_cycle = duty;</div><div class='ctx'> 	led_dat-&gt;pwmstate.enabled = true;</div><div class='del'>-	return pwm_apply_state(led_dat-&gt;pwm, &amp;led_dat-&gt;pwmstate);</div><div class='add'>+	return pwm_apply_might_sleep(led_dat-&gt;pwm, &amp;led_dat-&gt;pwmstate);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> __attribute__((nonnull))</div><div class='head'>diff --git a/drivers/leds/leds-sun50i-a100.c b/drivers/leds/leds-sun50i-a100.c<br/>new file mode 100644<br/>index 000000000000..62d21c3a3575<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-sun50i-a100.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-sun50i-a100.c</a></div><div class='hunk'>@@ -0,0 +1,584 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021-2023 Samuel Holland &lt;samuel@sholland.org&gt;</div><div class='add'>+ *</div><div class='add'>+ * Partly based on drivers/leds/leds-turris-omnia.c, which is:</div><div class='add'>+ *     Copyright (c) 2020 by Marek Behún &lt;kabel@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/dmaengine.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/led-class-multicolor.h&gt;</div><div class='add'>+#include &lt;linux/leds.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/reset.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+</div><div class='add'>+#define LEDC_CTRL_REG			0x0000</div><div class='add'>+#define LEDC_CTRL_REG_DATA_LENGTH		GENMASK(28, 16)</div><div class='add'>+#define LEDC_CTRL_REG_RGB_MODE			GENMASK(8, 6)</div><div class='add'>+#define LEDC_CTRL_REG_LEDC_EN			BIT(0)</div><div class='add'>+#define LEDC_T01_TIMING_CTRL_REG	0x0004</div><div class='add'>+#define LEDC_T01_TIMING_CTRL_REG_T1H		GENMASK(26, 21)</div><div class='add'>+#define LEDC_T01_TIMING_CTRL_REG_T1L		GENMASK(20, 16)</div><div class='add'>+#define LEDC_T01_TIMING_CTRL_REG_T0H		GENMASK(10, 6)</div><div class='add'>+#define LEDC_T01_TIMING_CTRL_REG_T0L		GENMASK(5, 0)</div><div class='add'>+#define LEDC_RESET_TIMING_CTRL_REG	0x000c</div><div class='add'>+#define LEDC_RESET_TIMING_CTRL_REG_TR		GENMASK(28, 16)</div><div class='add'>+#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM	GENMASK(9, 0)</div><div class='add'>+#define LEDC_DATA_REG			0x0014</div><div class='add'>+#define LEDC_DMA_CTRL_REG		0x0018</div><div class='add'>+#define LEDC_DMA_CTRL_REG_DMA_EN		BIT(5)</div><div class='add'>+#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL	GENMASK(4, 0)</div><div class='add'>+#define LEDC_INT_CTRL_REG		0x001c</div><div class='add'>+#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN		BIT(5)</div><div class='add'>+#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN	BIT(1)</div><div class='add'>+#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN	BIT(0)</div><div class='add'>+#define LEDC_INT_STS_REG		0x0020</div><div class='add'>+#define LEDC_INT_STS_REG_FIFO_WLW		GENMASK(15, 10)</div><div class='add'>+#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT	BIT(1)</div><div class='add'>+#define LEDC_INT_STS_REG_TRANS_FINISH_INT	BIT(0)</div><div class='add'>+</div><div class='add'>+#define LEDC_FIFO_DEPTH			32U</div><div class='add'>+#define LEDC_MAX_LEDS			1024</div><div class='add'>+#define LEDC_CHANNELS_PER_LED		3 /* RGB */</div><div class='add'>+</div><div class='add'>+#define LEDS_TO_BYTES(n)		((n) * sizeof(u32))</div><div class='add'>+</div><div class='add'>+struct sun50i_a100_ledc_led {</div><div class='add'>+	struct led_classdev_mc mc_cdev;</div><div class='add'>+	struct mc_subled subled_info[LEDC_CHANNELS_PER_LED];</div><div class='add'>+	u32 addr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)</div><div class='add'>+</div><div class='add'>+struct sun50i_a100_ledc_timing {</div><div class='add'>+	u32 t0h_ns;</div><div class='add'>+	u32 t0l_ns;</div><div class='add'>+	u32 t1h_ns;</div><div class='add'>+	u32 t1l_ns;</div><div class='add'>+	u32 treset_ns;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct sun50i_a100_ledc {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	void __iomem *base;</div><div class='add'>+	struct clk *bus_clk;</div><div class='add'>+	struct clk *mod_clk;</div><div class='add'>+	struct reset_control *reset;</div><div class='add'>+</div><div class='add'>+	u32 *buffer;</div><div class='add'>+	struct dma_chan *dma_chan;</div><div class='add'>+	dma_addr_t dma_handle;</div><div class='add'>+	unsigned int pio_length;</div><div class='add'>+	unsigned int pio_offset;</div><div class='add'>+</div><div class='add'>+	spinlock_t lock;</div><div class='add'>+	unsigned int next_length;</div><div class='add'>+	bool xfer_active;</div><div class='add'>+</div><div class='add'>+	u32 format;</div><div class='add'>+	struct sun50i_a100_ledc_timing timing;</div><div class='add'>+</div><div class='add'>+	u32 max_addr;</div><div class='add'>+	u32 num_leds;</div><div class='add'>+	struct sun50i_a100_ledc_led leds[] __counted_by(num_leds);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length)</div><div class='add'>+{</div><div class='add'>+	struct dma_async_tx_descriptor *desc;</div><div class='add'>+	dma_cookie_t cookie;</div><div class='add'>+</div><div class='add'>+	desc = dmaengine_prep_slave_single(priv-&gt;dma_chan, priv-&gt;dma_handle,</div><div class='add'>+					   LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0);</div><div class='add'>+	if (!desc)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	cookie = dmaengine_submit(desc);</div><div class='add'>+	if (dma_submit_error(cookie))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	dma_async_issue_pending(priv-&gt;dma_chan);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, unsigned int fifo_used)</div><div class='add'>+{</div><div class='add'>+	unsigned int burst, length, offset;</div><div class='add'>+	u32 control;</div><div class='add'>+</div><div class='add'>+	length = priv-&gt;pio_length;</div><div class='add'>+	offset = priv-&gt;pio_offset;</div><div class='add'>+	burst  = min(length, LEDC_FIFO_DEPTH - fifo_used);</div><div class='add'>+</div><div class='add'>+	iowrite32_rep(priv-&gt;base + LEDC_DATA_REG, priv-&gt;buffer + offset, burst);</div><div class='add'>+</div><div class='add'>+	if (burst &lt; length) {</div><div class='add'>+		priv-&gt;pio_length = length - burst;</div><div class='add'>+		priv-&gt;pio_offset = offset + burst;</div><div class='add'>+</div><div class='add'>+		if (!offset) {</div><div class='add'>+			control = readl(priv-&gt;base + LEDC_INT_CTRL_REG);</div><div class='add'>+			control |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;</div><div class='add'>+			writel(control, priv-&gt;base + LEDC_INT_CTRL_REG);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		/* Disable the request IRQ once all data is written. */</div><div class='add'>+		control = readl(priv-&gt;base + LEDC_INT_CTRL_REG);</div><div class='add'>+		control &amp;= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;</div><div class='add'>+		writel(control, priv-&gt;base + LEDC_INT_CTRL_REG);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv, unsigned int length)</div><div class='add'>+{</div><div class='add'>+	bool use_dma = false;</div><div class='add'>+	u32 control;</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;dma_chan &amp;&amp; length &gt; LEDC_FIFO_DEPTH) {</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		ret = sun50i_a100_ledc_dma_xfer(priv, length);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_warn(priv-&gt;dev, "Failed to set up DMA (%d), using PIO\n", ret);</div><div class='add'>+		else</div><div class='add'>+			use_dma = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* The DMA trigger level must be at least the burst length. */</div><div class='add'>+	control = FIELD_PREP(LEDC_DMA_CTRL_REG_DMA_EN, use_dma) |</div><div class='add'>+		  FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2);</div><div class='add'>+	writel(control, priv-&gt;base + LEDC_DMA_CTRL_REG);</div><div class='add'>+</div><div class='add'>+	control = readl(priv-&gt;base + LEDC_CTRL_REG);</div><div class='add'>+	control &amp;= ~LEDC_CTRL_REG_DATA_LENGTH;</div><div class='add'>+	control |= FIELD_PREP(LEDC_CTRL_REG_DATA_LENGTH, length) | LEDC_CTRL_REG_LEDC_EN;</div><div class='add'>+	writel(control, priv-&gt;base + LEDC_CTRL_REG);</div><div class='add'>+</div><div class='add'>+	if (!use_dma) {</div><div class='add'>+		/* The FIFO is empty when starting a new transfer. */</div><div class='add'>+		unsigned int fifo_used = 0;</div><div class='add'>+</div><div class='add'>+		priv-&gt;pio_length = length;</div><div class='add'>+		priv-&gt;pio_offset = 0;</div><div class='add'>+</div><div class='add'>+		sun50i_a100_ledc_pio_xfer(priv, fifo_used);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t sun50i_a100_ledc_irq(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = data;</div><div class='add'>+	u32 status;</div><div class='add'>+</div><div class='add'>+	status = readl(priv-&gt;base + LEDC_INT_STS_REG);</div><div class='add'>+</div><div class='add'>+	if (status &amp; LEDC_INT_STS_REG_TRANS_FINISH_INT) {</div><div class='add'>+		unsigned int next_length;</div><div class='add'>+</div><div class='add'>+		spin_lock(&amp;priv-&gt;lock);</div><div class='add'>+</div><div class='add'>+		/* If another transfer is queued, dequeue and start it. */</div><div class='add'>+		next_length = priv-&gt;next_length;</div><div class='add'>+		if (next_length)</div><div class='add'>+			priv-&gt;next_length = 0;</div><div class='add'>+		else</div><div class='add'>+			priv-&gt;xfer_active = false;</div><div class='add'>+</div><div class='add'>+		spin_unlock(&amp;priv-&gt;lock);</div><div class='add'>+</div><div class='add'>+		if (next_length)</div><div class='add'>+			sun50i_a100_ledc_start_xfer(priv, next_length);</div><div class='add'>+	} else if (status &amp; LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {</div><div class='add'>+		/* Continue the current transfer. */</div><div class='add'>+		sun50i_a100_ledc_pio_xfer(priv, FIELD_GET(LEDC_INT_STS_REG_FIFO_WLW, status));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Clear the W1C status bits. */</div><div class='add'>+	writel(status, priv-&gt;base + LEDC_INT_STS_REG);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,</div><div class='add'>+					    enum led_brightness brightness)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev-&gt;dev-&gt;parent);</div><div class='add'>+	struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);</div><div class='add'>+	struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);</div><div class='add'>+	unsigned int next_length;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	bool xfer_active;</div><div class='add'>+</div><div class='add'>+	led_mc_calc_color_components(mc_cdev, brightness);</div><div class='add'>+</div><div class='add'>+	priv-&gt;buffer[led-&gt;addr] = led-&gt;subled_info[0].brightness &lt;&lt; 16 |</div><div class='add'>+				  led-&gt;subled_info[1].brightness &lt;&lt;  8 |</div><div class='add'>+				  led-&gt;subled_info[2].brightness;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	/* Start, enqueue, or extend an enqueued transfer, as appropriate. */</div><div class='add'>+	next_length = max(priv-&gt;next_length, led-&gt;addr + 1);</div><div class='add'>+	xfer_active = priv-&gt;xfer_active;</div><div class='add'>+	if (xfer_active)</div><div class='add'>+		priv-&gt;next_length = next_length;</div><div class='add'>+	else</div><div class='add'>+		priv-&gt;xfer_active = true;</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	if (!xfer_active)</div><div class='add'>+		sun50i_a100_ledc_start_xfer(priv, next_length);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char *const sun50i_a100_ledc_formats[] = {</div><div class='add'>+	"rgb", "rbg", "grb", "gbr", "brg", "bgr",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_parse_format(struct device *dev,</div><div class='add'>+					 struct sun50i_a100_ledc *priv)</div><div class='add'>+{</div><div class='add'>+	const char *format = "grb";</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	device_property_read_string(dev, "allwinner,pixel-format", &amp;format);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(sun50i_a100_ledc_formats); i++) {</div><div class='add'>+		if (!strcmp(format, sun50i_a100_ledc_formats[i])) {</div><div class='add'>+			priv-&gt;format = i;</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return dev_err_probe(dev, -EINVAL, "Bad pixel format '%s'\n", format);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)</div><div class='add'>+{</div><div class='add'>+	u32 control;</div><div class='add'>+</div><div class='add'>+	control = readl(priv-&gt;base + LEDC_CTRL_REG);</div><div class='add'>+	control &amp;= ~LEDC_CTRL_REG_RGB_MODE;</div><div class='add'>+	control |= FIELD_PREP(LEDC_CTRL_REG_RGB_MODE, priv-&gt;format);</div><div class='add'>+	writel(control, priv-&gt;base + LEDC_CTRL_REG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {</div><div class='add'>+	.t0h_ns = 336,</div><div class='add'>+	.t0l_ns = 840,</div><div class='add'>+	.t1h_ns = 882,</div><div class='add'>+	.t1l_ns = 294,</div><div class='add'>+	.treset_ns = 300000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_parse_timing(struct device *dev,</div><div class='add'>+					 struct sun50i_a100_ledc *priv)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc_timing *timing = &amp;priv-&gt;timing;</div><div class='add'>+</div><div class='add'>+	*timing = sun50i_a100_ledc_default_timing;</div><div class='add'>+</div><div class='add'>+	device_property_read_u32(dev, "allwinner,t0h-ns", &amp;timing-&gt;t0h_ns);</div><div class='add'>+	device_property_read_u32(dev, "allwinner,t0l-ns", &amp;timing-&gt;t0l_ns);</div><div class='add'>+	device_property_read_u32(dev, "allwinner,t1h-ns", &amp;timing-&gt;t1h_ns);</div><div class='add'>+	device_property_read_u32(dev, "allwinner,t1l-ns", &amp;timing-&gt;t1l_ns);</div><div class='add'>+	device_property_read_u32(dev, "allwinner,treset-ns", &amp;timing-&gt;treset_ns);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)</div><div class='add'>+{</div><div class='add'>+	const struct sun50i_a100_ledc_timing *timing = &amp;priv-&gt;timing;</div><div class='add'>+	unsigned long mod_freq = clk_get_rate(priv-&gt;mod_clk);</div><div class='add'>+	u32 cycle_ns;</div><div class='add'>+	u32 control;</div><div class='add'>+</div><div class='add'>+	if (!mod_freq)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	cycle_ns = NSEC_PER_SEC / mod_freq;</div><div class='add'>+	control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing-&gt;t1h_ns / cycle_ns) |</div><div class='add'>+		  FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1L, timing-&gt;t1l_ns / cycle_ns) |</div><div class='add'>+		  FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0H, timing-&gt;t0h_ns / cycle_ns) |</div><div class='add'>+		  FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0L, timing-&gt;t0l_ns / cycle_ns);</div><div class='add'>+	writel(control, priv-&gt;base + LEDC_T01_TIMING_CTRL_REG);</div><div class='add'>+</div><div class='add'>+	control = FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_TR, timing-&gt;treset_ns / cycle_ns) |</div><div class='add'>+		  FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_LED_NUM, priv-&gt;max_addr);</div><div class='add'>+	writel(control, priv-&gt;base + LEDC_RESET_TIMING_CTRL_REG);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = reset_control_deassert(priv-&gt;reset);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(priv-&gt;bus_clk);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_assert_reset;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(priv-&gt;mod_clk);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_disable_bus_clk;</div><div class='add'>+</div><div class='add'>+	sun50i_a100_ledc_set_format(priv);</div><div class='add'>+	sun50i_a100_ledc_set_timing(priv);</div><div class='add'>+</div><div class='add'>+	writel(LEDC_INT_CTRL_REG_GLOBAL_INT_EN | LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN,</div><div class='add'>+	       priv-&gt;base + LEDC_INT_CTRL_REG);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_disable_bus_clk:</div><div class='add'>+	clk_disable_unprepare(priv-&gt;bus_clk);</div><div class='add'>+err_assert_reset:</div><div class='add'>+	reset_control_assert(priv-&gt;reset);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	/* Wait for all transfers to complete. */</div><div class='add'>+	for (;;) {</div><div class='add'>+		unsigned long flags;</div><div class='add'>+		bool xfer_active;</div><div class='add'>+</div><div class='add'>+		spin_lock_irqsave(&amp;priv-&gt;lock, flags);</div><div class='add'>+		xfer_active = priv-&gt;xfer_active;</div><div class='add'>+		spin_unlock_irqrestore(&amp;priv-&gt;lock, flags);</div><div class='add'>+		if (!xfer_active)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		msleep(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	clk_disable_unprepare(priv-&gt;mod_clk);</div><div class='add'>+	clk_disable_unprepare(priv-&gt;bus_clk);</div><div class='add'>+	reset_control_assert(priv-&gt;reset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_dma_cleanup(void *data)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = data;</div><div class='add'>+</div><div class='add'>+	dma_release_channel(priv-&gt;dma_chan);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int sun50i_a100_ledc_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct dma_slave_config dma_cfg = {};</div><div class='add'>+	struct led_init_data init_data = {};</div><div class='add'>+	struct sun50i_a100_ledc_led *led;</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct sun50i_a100_ledc *priv;</div><div class='add'>+	struct fwnode_handle *child;</div><div class='add'>+	struct resource *mem;</div><div class='add'>+	u32 max_addr = 0;</div><div class='add'>+	u32 num_leds = 0;</div><div class='add'>+	int irq, ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The maximum LED address must be known in sun50i_a100_ledc_resume() before</div><div class='add'>+	 * class device registration, so parse and validate the subnodes up front.</div><div class='add'>+	 */</div><div class='add'>+	device_for_each_child_node(dev, child) {</div><div class='add'>+		u32 addr, color;</div><div class='add'>+</div><div class='add'>+		ret = fwnode_property_read_u32(child, "reg", &amp;addr);</div><div class='add'>+		if (ret || addr &gt;= LEDC_MAX_LEDS) {</div><div class='add'>+			fwnode_handle_put(child);</div><div class='add'>+			return dev_err_probe(dev, -EINVAL, "'reg' must be between 0 and %d\n",</div><div class='add'>+					     LEDC_MAX_LEDS - 1);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = fwnode_property_read_u32(child, "color", &amp;color);</div><div class='add'>+		if (ret || color != LED_COLOR_ID_RGB) {</div><div class='add'>+			fwnode_handle_put(child);</div><div class='add'>+			return dev_err_probe(dev, -EINVAL, "'color' must be LED_COLOR_ID_RGB\n");</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		max_addr = max(max_addr, addr);</div><div class='add'>+		num_leds++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!num_leds)</div><div class='add'>+		return -ENODEV;</div><div class='add'>+</div><div class='add'>+	priv = devm_kzalloc(dev, struct_size(priv, leds, num_leds), GFP_KERNEL);</div><div class='add'>+	if (!priv)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	priv-&gt;dev = dev;</div><div class='add'>+	priv-&gt;max_addr = max_addr;</div><div class='add'>+	priv-&gt;num_leds = num_leds;</div><div class='add'>+	spin_lock_init(&amp;priv-&gt;lock);</div><div class='add'>+	dev_set_drvdata(dev, priv);</div><div class='add'>+</div><div class='add'>+	ret = sun50i_a100_ledc_parse_format(dev, priv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = sun50i_a100_ledc_parse_timing(dev, priv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	priv-&gt;base = devm_platform_get_and_ioremap_resource(pdev, 0, &amp;mem);</div><div class='add'>+	if (IS_ERR(priv-&gt;base))</div><div class='add'>+		return PTR_ERR(priv-&gt;base);</div><div class='add'>+</div><div class='add'>+	priv-&gt;bus_clk = devm_clk_get(dev, "bus");</div><div class='add'>+	if (IS_ERR(priv-&gt;bus_clk))</div><div class='add'>+		return PTR_ERR(priv-&gt;bus_clk);</div><div class='add'>+</div><div class='add'>+	priv-&gt;mod_clk = devm_clk_get(dev, "mod");</div><div class='add'>+	if (IS_ERR(priv-&gt;mod_clk))</div><div class='add'>+		return PTR_ERR(priv-&gt;mod_clk);</div><div class='add'>+</div><div class='add'>+	priv-&gt;reset = devm_reset_control_get_exclusive(dev, NULL);</div><div class='add'>+	if (IS_ERR(priv-&gt;reset))</div><div class='add'>+		return PTR_ERR(priv-&gt;reset);</div><div class='add'>+</div><div class='add'>+	priv-&gt;dma_chan = dma_request_chan(dev, "tx");</div><div class='add'>+	if (IS_ERR(priv-&gt;dma_chan)) {</div><div class='add'>+		if (PTR_ERR(priv-&gt;dma_chan) != -ENODEV)</div><div class='add'>+			return PTR_ERR(priv-&gt;dma_chan);</div><div class='add'>+</div><div class='add'>+		priv-&gt;dma_chan = NULL;</div><div class='add'>+</div><div class='add'>+		priv-&gt;buffer = devm_kzalloc(dev, LEDS_TO_BYTES(LEDC_MAX_LEDS), GFP_KERNEL);</div><div class='add'>+		if (!priv-&gt;buffer)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	} else {</div><div class='add'>+		ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		dma_cfg.dst_addr	= mem-&gt;start + LEDC_DATA_REG;</div><div class='add'>+		dma_cfg.dst_addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES;</div><div class='add'>+		dma_cfg.dst_maxburst	= LEDC_FIFO_DEPTH / 2;</div><div class='add'>+</div><div class='add'>+		ret = dmaengine_slave_config(priv-&gt;dma_chan, &amp;dma_cfg);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		priv-&gt;buffer = dmam_alloc_attrs(dmaengine_get_dma_device(priv-&gt;dma_chan),</div><div class='add'>+						LEDS_TO_BYTES(LEDC_MAX_LEDS), &amp;priv-&gt;dma_handle,</div><div class='add'>+						GFP_KERNEL, DMA_ATTR_WRITE_COMBINE);</div><div class='add'>+		if (!priv-&gt;buffer)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (irq &lt; 0)</div><div class='add'>+		return irq;</div><div class='add'>+</div><div class='add'>+	ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq, 0, dev_name(dev), priv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = sun50i_a100_ledc_resume(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	led = priv-&gt;leds;</div><div class='add'>+	device_for_each_child_node(dev, child) {</div><div class='add'>+		struct led_classdev *cdev;</div><div class='add'>+</div><div class='add'>+		/* The node was already validated above. */</div><div class='add'>+		fwnode_property_read_u32(child, "reg", &amp;led-&gt;addr);</div><div class='add'>+</div><div class='add'>+		led-&gt;subled_info[0].color_index = LED_COLOR_ID_RED;</div><div class='add'>+		led-&gt;subled_info[0].channel = 0;</div><div class='add'>+		led-&gt;subled_info[1].color_index = LED_COLOR_ID_GREEN;</div><div class='add'>+		led-&gt;subled_info[1].channel = 1;</div><div class='add'>+		led-&gt;subled_info[2].color_index = LED_COLOR_ID_BLUE;</div><div class='add'>+		led-&gt;subled_info[2].channel = 2;</div><div class='add'>+</div><div class='add'>+		led-&gt;mc_cdev.num_colors = ARRAY_SIZE(led-&gt;subled_info);</div><div class='add'>+		led-&gt;mc_cdev.subled_info = led-&gt;subled_info;</div><div class='add'>+</div><div class='add'>+		cdev = &amp;led-&gt;mc_cdev.led_cdev;</div><div class='add'>+		cdev-&gt;max_brightness = U8_MAX;</div><div class='add'>+		cdev-&gt;brightness_set = sun50i_a100_ledc_brightness_set;</div><div class='add'>+</div><div class='add'>+		init_data.fwnode = child;</div><div class='add'>+</div><div class='add'>+		ret = led_classdev_multicolor_register_ext(dev, &amp;led-&gt;mc_cdev, &amp;init_data);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err_probe(dev, ret, "Failed to register multicolor LED %u", led-&gt;addr);</div><div class='add'>+			goto err_put_child;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		led++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "Registered %u LEDs\n", num_leds);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_put_child:</div><div class='add'>+	fwnode_handle_put(child);</div><div class='add'>+	while (led-- &gt; priv-&gt;leds)</div><div class='add'>+		led_classdev_multicolor_unregister(&amp;led-&gt;mc_cdev);</div><div class='add'>+	sun50i_a100_ledc_suspend(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void sun50i_a100_ledc_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct sun50i_a100_ledc *priv = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	for (u32 i = 0; i &lt; priv-&gt;num_leds; i++)</div><div class='add'>+		led_classdev_multicolor_unregister(&amp;priv-&gt;leds[i].mc_cdev);</div><div class='add'>+	sun50i_a100_ledc_suspend(&amp;pdev-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id sun50i_a100_ledc_of_match[] = {</div><div class='add'>+	{ .compatible = "allwinner,sun50i-a100-ledc" },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);</div><div class='add'>+</div><div class='add'>+static DEFINE_SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,</div><div class='add'>+				sun50i_a100_ledc_suspend,</div><div class='add'>+				sun50i_a100_ledc_resume);</div><div class='add'>+</div><div class='add'>+static struct platform_driver sun50i_a100_ledc_driver = {</div><div class='add'>+	.probe		= sun50i_a100_ledc_probe,</div><div class='add'>+	.remove_new	= sun50i_a100_ledc_remove,</div><div class='add'>+	.shutdown	= sun50i_a100_ledc_remove,</div><div class='add'>+	.driver		= {</div><div class='add'>+		.name		= "sun50i-a100-ledc",</div><div class='add'>+		.of_match_table	= sun50i_a100_ledc_of_match,</div><div class='add'>+		.pm		= pm_ptr(&amp;sun50i_a100_ledc_pm),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_platform_driver(sun50i_a100_ledc_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Samuel Holland &lt;samuel@sholland.org&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Allwinner A100 LED controller driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/leds/leds-syscon.c b/drivers/leds/leds-syscon.c<br/>index 360a376fa738..d633ad519d0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/leds-syscon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/leds-syscon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-syscon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-syscon.c</a></div><div class='hunk'>@@ -81,7 +81,8 @@ static int syscon_led_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	sled-&gt;map = map;</div><div class='ctx'> </div><div class='del'>-	if (of_property_read_u32(np, "offset", &amp;sled-&gt;offset))</div><div class='add'>+	if (of_property_read_u32(np, "reg", &amp;sled-&gt;offset) &amp;&amp;</div><div class='add'>+	    of_property_read_u32(np, "offset", &amp;sled-&gt;offset))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	if (of_property_read_u32(np, "mask", &amp;sled-&gt;mask))</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/leds/leds-tca6507.c b/drivers/leds/leds-tca6507.c<br/>index e19074614095..4f22f4224946 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/leds-tca6507.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/leds-tca6507.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/leds-tca6507.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/leds-tca6507.c</a></div><div class='hunk'>@@ -638,19 +638,13 @@ static int tca6507_probe_gpios(struct device *dev,</div><div class='ctx'> 	tca-&gt;gpio.direction_output = tca6507_gpio_direction_output;</div><div class='ctx'> 	tca-&gt;gpio.set = tca6507_gpio_set_value;</div><div class='ctx'> 	tca-&gt;gpio.parent = dev;</div><div class='del'>-	err = gpiochip_add_data(&amp;tca-&gt;gpio, tca);</div><div class='add'>+	err = devm_gpiochip_add_data(dev, &amp;tca-&gt;gpio, tca);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		tca-&gt;gpio.ngpio = 0;</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-</div><div class='del'>-static void tca6507_remove_gpio(struct tca6507_chip *tca)</div><div class='del'>-{</div><div class='del'>-	if (tca-&gt;gpio.ngpio)</div><div class='del'>-		gpiochip_remove(&amp;tca-&gt;gpio);</div><div class='del'>-}</div><div class='ctx'> #else /* CONFIG_GPIOLIB */</div><div class='ctx'> static int tca6507_probe_gpios(struct device *dev,</div><div class='ctx'> 			       struct tca6507_chip *tca,</div><div class='hunk'>@@ -658,9 +652,6 @@ static int tca6507_probe_gpios(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-static void tca6507_remove_gpio(struct tca6507_chip *tca)</div><div class='del'>-{</div><div class='del'>-}</div><div class='ctx'> #endif /* CONFIG_GPIOLIB */</div><div class='ctx'> </div><div class='ctx'> static struct tca6507_platform_data *</div><div class='hunk'>@@ -762,38 +753,25 @@ static int tca6507_probe(struct i2c_client *client)</div><div class='ctx'> 			l-&gt;led_cdev.brightness_set = tca6507_brightness_set;</div><div class='ctx'> 			l-&gt;led_cdev.blink_set = tca6507_blink_set;</div><div class='ctx'> 			l-&gt;bank = -1;</div><div class='del'>-			err = led_classdev_register(dev, &amp;l-&gt;led_cdev);</div><div class='add'>+			err = devm_led_classdev_register(dev, &amp;l-&gt;led_cdev);</div><div class='ctx'> 			if (err &lt; 0)</div><div class='del'>-				goto exit;</div><div class='add'>+				return err;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	err = tca6507_probe_gpios(dev, tca, pdata);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto exit;</div><div class='add'>+		return err;</div><div class='ctx'> 	/* set all registers to known state - zero */</div><div class='ctx'> 	tca-&gt;reg_set = 0x7f;</div><div class='ctx'> 	schedule_work(&amp;tca-&gt;work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-exit:</div><div class='del'>-	while (i--) {</div><div class='del'>-		if (tca-&gt;leds[i].led_cdev.name)</div><div class='del'>-			led_classdev_unregister(&amp;tca-&gt;leds[i].led_cdev);</div><div class='del'>-	}</div><div class='del'>-	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void tca6507_remove(struct i2c_client *client)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='ctx'> 	struct tca6507_chip *tca = i2c_get_clientdata(client);</div><div class='del'>-	struct tca6507_led *tca_leds = tca-&gt;leds;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; NUM_LEDS; i++) {</div><div class='del'>-		if (tca_leds[i].led_cdev.name)</div><div class='del'>-			led_classdev_unregister(&amp;tca_leds[i].led_cdev);</div><div class='del'>-	}</div><div class='del'>-	tca6507_remove_gpio(tca);</div><div class='ctx'> 	cancel_work_sync(&amp;tca-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig<br/>index a6a21f564673..e66bd21b9852 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/rgb/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/rgb/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/rgb/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/Kconfig</a></div><div class='hunk'>@@ -4,7 +4,7 @@ if LEDS_CLASS_MULTICOLOR</div><div class='ctx'> </div><div class='ctx'> config LEDS_GROUP_MULTICOLOR</div><div class='ctx'> 	tristate "LEDs group multi-color support"</div><div class='del'>-	depends on OF || COMPILE_TEST</div><div class='add'>+	depends on OF</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option enables support for monochrome LEDs that are grouped</div><div class='ctx'> 	  into multicolor LEDs which is useful in the case where LEDs of</div><div class='head'>diff --git a/drivers/leds/rgb/leds-pwm-multicolor.c b/drivers/leds/rgb/leds-pwm-multicolor.c<br/>index 46cd062b8b24..e1a81e0109e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/rgb/leds-pwm-multicolor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/rgb/leds-pwm-multicolor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/rgb/leds-pwm-multicolor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/leds-pwm-multicolor.c</a></div><div class='hunk'>@@ -51,8 +51,8 @@ static int led_pwm_mc_set(struct led_classdev *cdev,</div><div class='ctx'> </div><div class='ctx'> 		priv-&gt;leds[i].state.duty_cycle = duty;</div><div class='ctx'> 		priv-&gt;leds[i].state.enabled = duty &gt; 0;</div><div class='del'>-		ret = pwm_apply_state(priv-&gt;leds[i].pwm,</div><div class='del'>-				      &amp;priv-&gt;leds[i].state);</div><div class='add'>+		ret = pwm_apply_might_sleep(priv-&gt;leds[i].pwm,</div><div class='add'>+					    &amp;priv-&gt;leds[i].state);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c<br/>index 68d82a682bf6..156b73d1f4a2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/rgb/leds-qcom-lpg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/rgb/leds-qcom-lpg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/rgb/leds-qcom-lpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/rgb/leds-qcom-lpg.c</a></div><div class='hunk'>@@ -552,9 +552,9 @@ static int lpg_parse_dtest(struct lpg *lpg)</div><div class='ctx'> 		ret = count;</div><div class='ctx'> 		goto err_malformed;</div><div class='ctx'> 	} else if (count != lpg-&gt;data-&gt;num_channels * 2) {</div><div class='del'>-		dev_err(lpg-&gt;dev, "qcom,dtest needs to be %d items\n",</div><div class='del'>-			lpg-&gt;data-&gt;num_channels * 2);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return dev_err_probe(lpg-&gt;dev, -EINVAL,</div><div class='add'>+				     "qcom,dtest needs to be %d items\n",</div><div class='add'>+				     lpg-&gt;data-&gt;num_channels * 2);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; lpg-&gt;data-&gt;num_channels; i++) {</div><div class='hunk'>@@ -574,8 +574,7 @@ static int lpg_parse_dtest(struct lpg *lpg)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_malformed:</div><div class='del'>-	dev_err(lpg-&gt;dev, "malformed qcom,dtest\n");</div><div class='del'>-	return ret;</div><div class='add'>+	return dev_err_probe(lpg-&gt;dev, ret, "malformed qcom,dtest\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void lpg_apply_dtest(struct lpg_channel *chan)</div><div class='hunk'>@@ -977,9 +976,14 @@ static int lpg_pattern_mc_clear(struct led_classdev *cdev)</div><div class='ctx'> 	return lpg_pattern_clear(led);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline struct lpg *lpg_pwm_from_chip(struct pwm_chip *chip)</div><div class='add'>+{</div><div class='add'>+	return container_of(chip, struct lpg, pwm);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)</div><div class='ctx'> {</div><div class='del'>-	struct lpg *lpg = container_of(chip, struct lpg, pwm);</div><div class='add'>+	struct lpg *lpg = lpg_pwm_from_chip(chip);</div><div class='ctx'> 	struct lpg_channel *chan = &amp;lpg-&gt;channels[pwm-&gt;hwpwm];</div><div class='ctx'> </div><div class='ctx'> 	return chan-&gt;in_use ? -EBUSY : 0;</div><div class='hunk'>@@ -995,7 +999,7 @@ static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)</div><div class='ctx'> static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,</div><div class='ctx'> 			 const struct pwm_state *state)</div><div class='ctx'> {</div><div class='del'>-	struct lpg *lpg = container_of(chip, struct lpg, pwm);</div><div class='add'>+	struct lpg *lpg = lpg_pwm_from_chip(chip);</div><div class='ctx'> 	struct lpg_channel *chan = &amp;lpg-&gt;channels[pwm-&gt;hwpwm];</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1026,7 +1030,7 @@ out_unlock:</div><div class='ctx'> static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,</div><div class='ctx'> 			     struct pwm_state *state)</div><div class='ctx'> {</div><div class='del'>-	struct lpg *lpg = container_of(chip, struct lpg, pwm);</div><div class='add'>+	struct lpg *lpg = lpg_pwm_from_chip(chip);</div><div class='ctx'> 	struct lpg_channel *chan = &amp;lpg-&gt;channels[pwm-&gt;hwpwm];</div><div class='ctx'> 	unsigned int resolution;</div><div class='ctx'> 	unsigned int pre_div;</div><div class='hunk'>@@ -1095,9 +1099,9 @@ static int lpg_add_pwm(struct lpg *lpg)</div><div class='ctx'> 	lpg-&gt;pwm.npwm = lpg-&gt;num_channels;</div><div class='ctx'> 	lpg-&gt;pwm.ops = &amp;lpg_pwm_ops;</div><div class='ctx'> </div><div class='del'>-	ret = pwmchip_add(&amp;lpg-&gt;pwm);</div><div class='add'>+	ret = devm_pwmchip_add(lpg-&gt;dev, &amp;lpg-&gt;pwm);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		dev_err(lpg-&gt;dev, "failed to add PWM chip: ret %d\n", ret);</div><div class='add'>+		dev_err_probe(lpg-&gt;dev, ret, "failed to add PWM chip\n");</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1111,19 +1115,16 @@ static int lpg_parse_channel(struct lpg *lpg, struct device_node *np,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = of_property_read_u32(np, "reg", &amp;reg);</div><div class='del'>-	if (ret || !reg || reg &gt; lpg-&gt;num_channels) {</div><div class='del'>-		dev_err(lpg-&gt;dev, "invalid \"reg\" of %pOFn\n", np);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='add'>+	if (ret || !reg || reg &gt; lpg-&gt;num_channels)</div><div class='add'>+		return dev_err_probe(lpg-&gt;dev, -EINVAL, "invalid \"reg\" of %pOFn\n", np);</div><div class='ctx'> </div><div class='ctx'> 	chan = &amp;lpg-&gt;channels[reg - 1];</div><div class='ctx'> 	chan-&gt;in_use = true;</div><div class='ctx'> </div><div class='ctx'> 	ret = of_property_read_u32(np, "color", &amp;color);</div><div class='del'>-	if (ret &lt; 0 &amp;&amp; ret != -EINVAL) {</div><div class='del'>-		dev_err(lpg-&gt;dev, "failed to parse \"color\" of %pOF\n", np);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EINVAL)</div><div class='add'>+		return dev_err_probe(lpg-&gt;dev, ret,</div><div class='add'>+				     "failed to parse \"color\" of %pOF\n", np);</div><div class='ctx'> </div><div class='ctx'> 	chan-&gt;color = color;</div><div class='ctx'> </div><div class='hunk'>@@ -1146,10 +1147,9 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	ret = of_property_read_u32(np, "color", &amp;color);</div><div class='del'>-	if (ret &lt; 0 &amp;&amp; ret != -EINVAL) {</div><div class='del'>-		dev_err(lpg-&gt;dev, "failed to parse \"color\" of %pOF\n", np);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EINVAL)</div><div class='add'>+		return dev_err_probe(lpg-&gt;dev, ret,</div><div class='add'>+			      "failed to parse \"color\" of %pOF\n", np);</div><div class='ctx'> </div><div class='ctx'> 	if (color == LED_COLOR_ID_RGB)</div><div class='ctx'> 		num_channels = of_get_available_child_count(np);</div><div class='hunk'>@@ -1226,7 +1226,7 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np)</div><div class='ctx'> 	else</div><div class='ctx'> 		ret = devm_led_classdev_register_ext(lpg-&gt;dev, &amp;led-&gt;cdev, &amp;init_data);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		dev_err(lpg-&gt;dev, "unable to register %s\n", cdev-&gt;name);</div><div class='add'>+		dev_err_probe(lpg-&gt;dev, ret, "unable to register %s\n", cdev-&gt;name);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1272,10 +1272,9 @@ static int lpg_init_triled(struct lpg *lpg)</div><div class='ctx'> </div><div class='ctx'> 	if (lpg-&gt;triled_has_src_sel) {</div><div class='ctx'> 		ret = of_property_read_u32(np, "qcom,power-source", &amp;lpg-&gt;triled_src);</div><div class='del'>-		if (ret || lpg-&gt;triled_src == 2 || lpg-&gt;triled_src &gt; 3) {</div><div class='del'>-			dev_err(lpg-&gt;dev, "invalid power source\n");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+		if (ret || lpg-&gt;triled_src == 2 || lpg-&gt;triled_src &gt; 3)</div><div class='add'>+			return dev_err_probe(lpg-&gt;dev, -EINVAL,</div><div class='add'>+					     "invalid power source\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Disable automatic trickle charge LED */</div><div class='hunk'>@@ -1324,8 +1323,6 @@ static int lpg_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (!lpg-&gt;data)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	platform_set_drvdata(pdev, lpg);</div><div class='del'>-</div><div class='ctx'> 	lpg-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	mutex_init(&amp;lpg-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -1363,13 +1360,6 @@ static int lpg_probe(struct platform_device *pdev)</div><div class='ctx'> 	return lpg_add_pwm(lpg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void lpg_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	struct lpg *lpg = platform_get_drvdata(pdev);</div><div class='del'>-</div><div class='del'>-	pwmchip_remove(&amp;lpg-&gt;pwm);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct lpg_data pm8916_pwm_data = {</div><div class='ctx'> 	.num_channels = 1,</div><div class='ctx'> 	.channels = (const struct lpg_channel_data[]) {</div><div class='hunk'>@@ -1529,7 +1519,6 @@ MODULE_DEVICE_TABLE(of, lpg_of_table);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver lpg_driver = {</div><div class='ctx'> 	.probe = lpg_probe,</div><div class='del'>-	.remove_new = lpg_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom-spmi-lpg",</div><div class='ctx'> 		.of_match_table = lpg_of_table,</div><div class='head'>diff --git a/drivers/leds/trigger/ledtrig-gpio.c b/drivers/leds/trigger/ledtrig-gpio.c<br/>index 9b7fe5dd5208..7f6a2352b0ac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-gpio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/trigger/ledtrig-gpio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-gpio.c</a></div><div class='hunk'>@@ -41,33 +41,30 @@ static irqreturn_t gpio_trig_irq(int irq, void *_led)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static ssize_t gpio_trig_brightness_show(struct device *dev,</div><div class='add'>+static ssize_t desired_brightness_show(struct device *dev,</div><div class='ctx'> 		struct device_attribute *attr, char *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_trig_data *gpio_data = led_trigger_get_drvdata(dev);</div><div class='ctx'> </div><div class='del'>-	return sprintf(buf, "%u\n", gpio_data-&gt;desired_brightness);</div><div class='add'>+	return sysfs_emit(buf, "%u\n", gpio_data-&gt;desired_brightness);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static ssize_t gpio_trig_brightness_store(struct device *dev,</div><div class='add'>+static ssize_t desired_brightness_store(struct device *dev,</div><div class='ctx'> 		struct device_attribute *attr, const char *buf, size_t n)</div><div class='ctx'> {</div><div class='ctx'> 	struct gpio_trig_data *gpio_data = led_trigger_get_drvdata(dev);</div><div class='del'>-	unsigned desired_brightness;</div><div class='add'>+	u8 desired_brightness;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = sscanf(buf, "%u", &amp;desired_brightness);</div><div class='del'>-	if (ret &lt; 1 || desired_brightness &gt; 255) {</div><div class='del'>-		dev_err(dev, "invalid value\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='add'>+	ret = kstrtou8(buf, 10, &amp;desired_brightness);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	gpio_data-&gt;desired_brightness = desired_brightness;</div><div class='ctx'> </div><div class='ctx'> 	return n;</div><div class='ctx'> }</div><div class='del'>-static DEVICE_ATTR(desired_brightness, 0644, gpio_trig_brightness_show,</div><div class='del'>-		gpio_trig_brightness_store);</div><div class='add'>+static DEVICE_ATTR_RW(desired_brightness);</div><div class='ctx'> </div><div class='ctx'> static struct attribute *gpio_trig_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_desired_brightness.attr,</div><div class='hunk'>@@ -89,10 +86,7 @@ static int gpio_trig_activate(struct led_classdev *led)</div><div class='ctx'> 	 * The generic property "trigger-sources" is followed,</div><div class='ctx'> 	 * and we hope that this is a GPIO.</div><div class='ctx'> 	 */</div><div class='del'>-	gpio_data-&gt;gpiod = fwnode_gpiod_get_index(dev-&gt;fwnode,</div><div class='del'>-						  "trigger-sources",</div><div class='del'>-						  0, GPIOD_IN,</div><div class='del'>-						  "led-trigger");</div><div class='add'>+	gpio_data-&gt;gpiod = gpiod_get_optional(dev, "trigger-sources", GPIOD_IN);</div><div class='ctx'> 	if (IS_ERR(gpio_data-&gt;gpiod)) {</div><div class='ctx'> 		ret = PTR_ERR(gpio_data-&gt;gpiod);</div><div class='ctx'> 		kfree(gpio_data);</div><div class='hunk'>@@ -104,6 +98,8 @@ static int gpio_trig_activate(struct led_classdev *led)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	gpiod_set_consumer_name(gpio_data-&gt;gpiod, "led-trigger");</div><div class='add'>+</div><div class='ctx'> 	gpio_data-&gt;led = led;</div><div class='ctx'> 	led_set_trigger_data(led, gpio_data);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/leds/trigger/ledtrig-netdev.c b/drivers/leds/trigger/ledtrig-netdev.c<br/>index e358e77e4b38..8e5475819590 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-netdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/trigger/ledtrig-netdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-netdev.c</a></div><div class='hunk'>@@ -38,6 +38,16 @@</div><div class='ctx'>  * tx -  LED blinks on transmitted data</div><div class='ctx'>  * rx -  LED blinks on receive data</div><div class='ctx'>  *</div><div class='add'>+ * Note: If the user selects a mode that is not supported by hw, default</div><div class='add'>+ * behavior is to fall back to software control of the LED. However not every</div><div class='add'>+ * hw supports software control. LED callbacks brightness_set() and</div><div class='add'>+ * brightness_set_blocking() are NULL in this case. hw_control_is_supported()</div><div class='add'>+ * should use available means supported by hw to inform the user that selected</div><div class='add'>+ * mode isn't supported by hw. This could be switching off the LED or any</div><div class='add'>+ * hw blink mode. If software control fallback isn't possible, we return</div><div class='add'>+ * -EOPNOTSUPP to the user, but still store the selected mode. This is needed</div><div class='add'>+ * in case an intermediate unsupported mode is necessary to switch from one</div><div class='add'>+ * supported mode to another.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> struct led_netdev_data {</div><div class='hunk'>@@ -99,6 +109,18 @@ static void set_baseline_state(struct led_netdev_data *trigger_data)</div><div class='ctx'> 		    trigger_data-&gt;link_speed == SPEED_1000)</div><div class='ctx'> 			blink_on = true;</div><div class='ctx'> </div><div class='add'>+		if (test_bit(TRIGGER_NETDEV_LINK_2500, &amp;trigger_data-&gt;mode) &amp;&amp;</div><div class='add'>+		    trigger_data-&gt;link_speed == SPEED_2500)</div><div class='add'>+			blink_on = true;</div><div class='add'>+</div><div class='add'>+		if (test_bit(TRIGGER_NETDEV_LINK_5000, &amp;trigger_data-&gt;mode) &amp;&amp;</div><div class='add'>+		    trigger_data-&gt;link_speed == SPEED_5000)</div><div class='add'>+			blink_on = true;</div><div class='add'>+</div><div class='add'>+		if (test_bit(TRIGGER_NETDEV_LINK_10000, &amp;trigger_data-&gt;mode) &amp;&amp;</div><div class='add'>+		    trigger_data-&gt;link_speed == SPEED_10000)</div><div class='add'>+			blink_on = true;</div><div class='add'>+</div><div class='ctx'> 		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &amp;trigger_data-&gt;mode) &amp;&amp;</div><div class='ctx'> 		    trigger_data-&gt;duplex == DUPLEX_HALF)</div><div class='ctx'> 			blink_on = true;</div><div class='hunk'>@@ -226,6 +248,11 @@ static int set_device_name(struct led_netdev_data *trigger_data,</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;trigger_data-&gt;work);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Take RTNL lock before trigger_data lock to prevent potential</div><div class='add'>+	 * deadlock with netdev notifier registration.</div><div class='add'>+	 */</div><div class='add'>+	rtnl_lock();</div><div class='ctx'> 	mutex_lock(&amp;trigger_data-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (trigger_data-&gt;net_dev) {</div><div class='hunk'>@@ -245,16 +272,14 @@ static int set_device_name(struct led_netdev_data *trigger_data,</div><div class='ctx'> 	trigger_data-&gt;carrier_link_up = false;</div><div class='ctx'> 	trigger_data-&gt;link_speed = SPEED_UNKNOWN;</div><div class='ctx'> 	trigger_data-&gt;duplex = DUPLEX_UNKNOWN;</div><div class='del'>-	if (trigger_data-&gt;net_dev != NULL) {</div><div class='del'>-		rtnl_lock();</div><div class='add'>+	if (trigger_data-&gt;net_dev)</div><div class='ctx'> 		get_device_state(trigger_data);</div><div class='del'>-		rtnl_unlock();</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	trigger_data-&gt;last_activity = 0;</div><div class='ctx'> </div><div class='ctx'> 	set_baseline_state(trigger_data);</div><div class='ctx'> 	mutex_unlock(&amp;trigger_data-&gt;lock);</div><div class='add'>+	rtnl_unlock();</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -286,6 +311,9 @@ static ssize_t netdev_led_attr_show(struct device *dev, char *buf,</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_10:</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_100:</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_1000:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_2500:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_5000:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_10000:</div><div class='ctx'> 	case TRIGGER_NETDEV_HALF_DUPLEX:</div><div class='ctx'> 	case TRIGGER_NETDEV_FULL_DUPLEX:</div><div class='ctx'> 	case TRIGGER_NETDEV_TX:</div><div class='hunk'>@@ -303,6 +331,7 @@ static ssize_t netdev_led_attr_store(struct device *dev, const char *buf,</div><div class='ctx'> 				     size_t size, enum led_trigger_netdev_modes attr)</div><div class='ctx'> {</div><div class='ctx'> 	struct led_netdev_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='add'>+	struct led_classdev *led_cdev = trigger_data-&gt;led_cdev;</div><div class='ctx'> 	unsigned long state, mode = trigger_data-&gt;mode;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int bit;</div><div class='hunk'>@@ -316,6 +345,9 @@ static ssize_t netdev_led_attr_store(struct device *dev, const char *buf,</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_10:</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_100:</div><div class='ctx'> 	case TRIGGER_NETDEV_LINK_1000:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_2500:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_5000:</div><div class='add'>+	case TRIGGER_NETDEV_LINK_10000:</div><div class='ctx'> 	case TRIGGER_NETDEV_HALF_DUPLEX:</div><div class='ctx'> 	case TRIGGER_NETDEV_FULL_DUPLEX:</div><div class='ctx'> 	case TRIGGER_NETDEV_TX:</div><div class='hunk'>@@ -334,7 +366,10 @@ static ssize_t netdev_led_attr_store(struct device *dev, const char *buf,</div><div class='ctx'> 	if (test_bit(TRIGGER_NETDEV_LINK, &amp;mode) &amp;&amp;</div><div class='ctx'> 	    (test_bit(TRIGGER_NETDEV_LINK_10, &amp;mode) ||</div><div class='ctx'> 	     test_bit(TRIGGER_NETDEV_LINK_100, &amp;mode) ||</div><div class='del'>-	     test_bit(TRIGGER_NETDEV_LINK_1000, &amp;mode)))</div><div class='add'>+	     test_bit(TRIGGER_NETDEV_LINK_1000, &amp;mode) ||</div><div class='add'>+	     test_bit(TRIGGER_NETDEV_LINK_2500, &amp;mode) ||</div><div class='add'>+	     test_bit(TRIGGER_NETDEV_LINK_5000, &amp;mode) ||</div><div class='add'>+	     test_bit(TRIGGER_NETDEV_LINK_10000, &amp;mode)))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;trigger_data-&gt;work);</div><div class='hunk'>@@ -342,6 +377,10 @@ static ssize_t netdev_led_attr_store(struct device *dev, const char *buf,</div><div class='ctx'> 	trigger_data-&gt;mode = mode;</div><div class='ctx'> 	trigger_data-&gt;hw_control = can_hw_control(trigger_data);</div><div class='ctx'> </div><div class='add'>+	if (!led_cdev-&gt;brightness_set &amp;&amp; !led_cdev-&gt;brightness_set_blocking &amp;&amp;</div><div class='add'>+	    !trigger_data-&gt;hw_control)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 	set_baseline_state(trigger_data);</div><div class='ctx'> </div><div class='ctx'> 	return size;</div><div class='hunk'>@@ -364,6 +403,9 @@ DEFINE_NETDEV_TRIGGER(link, TRIGGER_NETDEV_LINK);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(link_10, TRIGGER_NETDEV_LINK_10);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(link_100, TRIGGER_NETDEV_LINK_100);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(link_1000, TRIGGER_NETDEV_LINK_1000);</div><div class='add'>+DEFINE_NETDEV_TRIGGER(link_2500, TRIGGER_NETDEV_LINK_2500);</div><div class='add'>+DEFINE_NETDEV_TRIGGER(link_5000, TRIGGER_NETDEV_LINK_5000);</div><div class='add'>+DEFINE_NETDEV_TRIGGER(link_10000, TRIGGER_NETDEV_LINK_10000);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(half_duplex, TRIGGER_NETDEV_HALF_DUPLEX);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(full_duplex, TRIGGER_NETDEV_FULL_DUPLEX);</div><div class='ctx'> DEFINE_NETDEV_TRIGGER(tx, TRIGGER_NETDEV_TX);</div><div class='hunk'>@@ -422,6 +464,9 @@ static struct attribute *netdev_trig_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_link_10.attr,</div><div class='ctx'> 	&amp;dev_attr_link_100.attr,</div><div class='ctx'> 	&amp;dev_attr_link_1000.attr,</div><div class='add'>+	&amp;dev_attr_link_2500.attr,</div><div class='add'>+	&amp;dev_attr_link_5000.attr,</div><div class='add'>+	&amp;dev_attr_link_10000.attr,</div><div class='ctx'> 	&amp;dev_attr_full_duplex.attr,</div><div class='ctx'> 	&amp;dev_attr_half_duplex.attr,</div><div class='ctx'> 	&amp;dev_attr_rx.attr,</div><div class='hunk'>@@ -519,6 +564,9 @@ static void netdev_trig_work(struct work_struct *work)</div><div class='ctx'> 			 test_bit(TRIGGER_NETDEV_LINK_10, &amp;trigger_data-&gt;mode) ||</div><div class='ctx'> 			 test_bit(TRIGGER_NETDEV_LINK_100, &amp;trigger_data-&gt;mode) ||</div><div class='ctx'> 			 test_bit(TRIGGER_NETDEV_LINK_1000, &amp;trigger_data-&gt;mode) ||</div><div class='add'>+			 test_bit(TRIGGER_NETDEV_LINK_2500, &amp;trigger_data-&gt;mode) ||</div><div class='add'>+			 test_bit(TRIGGER_NETDEV_LINK_5000, &amp;trigger_data-&gt;mode) ||</div><div class='add'>+			 test_bit(TRIGGER_NETDEV_LINK_10000, &amp;trigger_data-&gt;mode) ||</div><div class='ctx'> 			 test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &amp;trigger_data-&gt;mode) ||</div><div class='ctx'> 			 test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &amp;trigger_data-&gt;mode);</div><div class='ctx'> 		interval = jiffies_to_msecs(</div><div class='head'>diff --git a/drivers/leds/trigger/ledtrig-panic.c b/drivers/leds/trigger/ledtrig-panic.c<br/>index 64abf2e91608..5a6b21bfeb9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-panic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/trigger/ledtrig-panic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-panic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-panic.c</a></div><div class='hunk'>@@ -64,10 +64,13 @@ static long led_panic_blink(int state)</div><div class='ctx'> </div><div class='ctx'> static int __init ledtrig_panic_init(void)</div><div class='ctx'> {</div><div class='add'>+	led_trigger_register_simple("panic", &amp;trigger);</div><div class='add'>+	if (!trigger)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	atomic_notifier_chain_register(&amp;panic_notifier_list,</div><div class='ctx'> 				       &amp;led_trigger_panic_nb);</div><div class='ctx'> </div><div class='del'>-	led_trigger_register_simple("panic", &amp;trigger);</div><div class='ctx'> 	panic_blink = led_panic_blink;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/leds/trigger/ledtrig-tty.c b/drivers/leds/trigger/ledtrig-tty.c<br/>index 8ae0d2d284af..8cf1485e8165 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-tty.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/leds/trigger/ledtrig-tty.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/leds/trigger/ledtrig-tty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/leds/trigger/ledtrig-tty.c</a></div><div class='hunk'>@@ -1,5 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/completion.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/leds.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -12,15 +13,45 @@</div><div class='ctx'> struct ledtrig_tty_data {</div><div class='ctx'> 	struct led_classdev *led_cdev;</div><div class='ctx'> 	struct delayed_work dwork;</div><div class='del'>-	struct mutex mutex;</div><div class='add'>+	struct completion sysfs;</div><div class='ctx'> 	const char *ttyname;</div><div class='ctx'> 	struct tty_struct *tty;</div><div class='ctx'> 	int rx, tx;</div><div class='add'>+	bool mode_rx;</div><div class='add'>+	bool mode_tx;</div><div class='add'>+	bool mode_cts;</div><div class='add'>+	bool mode_dsr;</div><div class='add'>+	bool mode_dcd;</div><div class='add'>+	bool mode_rng;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void ledtrig_tty_restart(struct ledtrig_tty_data *trigger_data)</div><div class='add'>+/* Indicates which state the LED should now display */</div><div class='add'>+enum led_trigger_tty_state {</div><div class='add'>+	TTY_LED_BLINK,</div><div class='add'>+	TTY_LED_ENABLE,</div><div class='add'>+	TTY_LED_DISABLE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum led_trigger_tty_modes {</div><div class='add'>+	TRIGGER_TTY_RX = 0,</div><div class='add'>+	TRIGGER_TTY_TX,</div><div class='add'>+	TRIGGER_TTY_CTS,</div><div class='add'>+	TRIGGER_TTY_DSR,</div><div class='add'>+	TRIGGER_TTY_DCD,</div><div class='add'>+	TRIGGER_TTY_RNG,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ledtrig_tty_wait_for_completion(struct device *dev)</div><div class='ctx'> {</div><div class='del'>-	schedule_delayed_work(&amp;trigger_data-&gt;dwork, 0);</div><div class='add'>+	struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wait_for_completion_timeout(&amp;trigger_data-&gt;sysfs,</div><div class='add'>+					  msecs_to_jiffies(LEDTRIG_TTY_INTERVAL * 20));</div><div class='add'>+	if (ret == 0)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static ssize_t ttyname_show(struct device *dev,</div><div class='hunk'>@@ -28,14 +59,16 @@ static ssize_t ttyname_show(struct device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='ctx'> 	ssize_t len = 0;</div><div class='add'>+	int completion;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;trigger_data-&gt;mutex);</div><div class='add'>+	reinit_completion(&amp;trigger_data-&gt;sysfs);</div><div class='add'>+	completion = ledtrig_tty_wait_for_completion(dev);</div><div class='add'>+	if (completion &lt; 0)</div><div class='add'>+		return completion;</div><div class='ctx'> </div><div class='ctx'> 	if (trigger_data-&gt;ttyname)</div><div class='ctx'> 		len = sprintf(buf, "%s\n", trigger_data-&gt;ttyname);</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-</div><div class='ctx'> 	return len;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -46,7 +79,7 @@ static ssize_t ttyname_store(struct device *dev,</div><div class='ctx'> 	struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='ctx'> 	char *ttyname;</div><div class='ctx'> 	ssize_t ret = size;</div><div class='del'>-	bool running;</div><div class='add'>+	int completion;</div><div class='ctx'> </div><div class='ctx'> 	if (size &gt; 0 &amp;&amp; buf[size - 1] == '\n')</div><div class='ctx'> 		size -= 1;</div><div class='hunk'>@@ -59,9 +92,10 @@ static ssize_t ttyname_store(struct device *dev,</div><div class='ctx'> 		ttyname = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	running = trigger_data-&gt;ttyname != NULL;</div><div class='add'>+	reinit_completion(&amp;trigger_data-&gt;sysfs);</div><div class='add'>+	completion = ledtrig_tty_wait_for_completion(dev);</div><div class='add'>+	if (completion &lt; 0)</div><div class='add'>+		return completion;</div><div class='ctx'> </div><div class='ctx'> 	kfree(trigger_data-&gt;ttyname);</div><div class='ctx'> 	tty_kref_put(trigger_data-&gt;tty);</div><div class='hunk'>@@ -69,29 +103,107 @@ static ssize_t ttyname_store(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	trigger_data-&gt;ttyname = ttyname;</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	if (ttyname &amp;&amp; !running)</div><div class='del'>-		ledtrig_tty_restart(trigger_data);</div><div class='del'>-</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> static DEVICE_ATTR_RW(ttyname);</div><div class='ctx'> </div><div class='add'>+static ssize_t ledtrig_tty_attr_show(struct device *dev, char *buf,</div><div class='add'>+				     enum led_trigger_tty_modes attr)</div><div class='add'>+{</div><div class='add'>+	struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='add'>+	bool state;</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case TRIGGER_TTY_RX:</div><div class='add'>+		state = trigger_data-&gt;mode_rx;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_TX:</div><div class='add'>+		state = trigger_data-&gt;mode_tx;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_CTS:</div><div class='add'>+		state = trigger_data-&gt;mode_cts;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_DSR:</div><div class='add'>+		state = trigger_data-&gt;mode_dsr;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_DCD:</div><div class='add'>+		state = trigger_data-&gt;mode_dcd;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_RNG:</div><div class='add'>+		state = trigger_data-&gt;mode_rng;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return sysfs_emit(buf, "%u\n", state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static ssize_t ledtrig_tty_attr_store(struct device *dev, const char *buf,</div><div class='add'>+				      size_t size, enum led_trigger_tty_modes attr)</div><div class='add'>+{</div><div class='add'>+	struct ledtrig_tty_data *trigger_data = led_trigger_get_drvdata(dev);</div><div class='add'>+	bool state;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = kstrtobool(buf, &amp;state);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case TRIGGER_TTY_RX:</div><div class='add'>+		trigger_data-&gt;mode_rx = state;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_TX:</div><div class='add'>+		trigger_data-&gt;mode_tx = state;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_CTS:</div><div class='add'>+		trigger_data-&gt;mode_cts = state;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_DSR:</div><div class='add'>+		trigger_data-&gt;mode_dsr = state;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_DCD:</div><div class='add'>+		trigger_data-&gt;mode_dcd = state;</div><div class='add'>+		break;</div><div class='add'>+	case TRIGGER_TTY_RNG:</div><div class='add'>+		trigger_data-&gt;mode_rng = state;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define DEFINE_TTY_TRIGGER(trigger_name, trigger) \</div><div class='add'>+	static ssize_t trigger_name##_show(struct device *dev, \</div><div class='add'>+		struct device_attribute *attr, char *buf) \</div><div class='add'>+	{ \</div><div class='add'>+		return ledtrig_tty_attr_show(dev, buf, trigger); \</div><div class='add'>+	} \</div><div class='add'>+	static ssize_t trigger_name##_store(struct device *dev, \</div><div class='add'>+		struct device_attribute *attr, const char *buf, size_t size) \</div><div class='add'>+	{ \</div><div class='add'>+		return ledtrig_tty_attr_store(dev, buf, size, trigger); \</div><div class='add'>+	} \</div><div class='add'>+	static DEVICE_ATTR_RW(trigger_name)</div><div class='add'>+</div><div class='add'>+DEFINE_TTY_TRIGGER(rx, TRIGGER_TTY_RX);</div><div class='add'>+DEFINE_TTY_TRIGGER(tx, TRIGGER_TTY_TX);</div><div class='add'>+DEFINE_TTY_TRIGGER(cts, TRIGGER_TTY_CTS);</div><div class='add'>+DEFINE_TTY_TRIGGER(dsr, TRIGGER_TTY_DSR);</div><div class='add'>+DEFINE_TTY_TRIGGER(dcd, TRIGGER_TTY_DCD);</div><div class='add'>+DEFINE_TTY_TRIGGER(rng, TRIGGER_TTY_RNG);</div><div class='add'>+</div><div class='ctx'> static void ledtrig_tty_work(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct ledtrig_tty_data *trigger_data =</div><div class='ctx'> 		container_of(work, struct ledtrig_tty_data, dwork.work);</div><div class='del'>-	struct serial_icounter_struct icount;</div><div class='add'>+	enum led_trigger_tty_state state = TTY_LED_DISABLE;</div><div class='add'>+	unsigned long interval = LEDTRIG_TTY_INTERVAL;</div><div class='add'>+	bool invert = false;</div><div class='add'>+	int status;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	if (!trigger_data-&gt;ttyname) {</div><div class='del'>-		/* exit without rescheduling */</div><div class='del'>-		mutex_unlock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='add'>+	if (!trigger_data-&gt;ttyname)</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> 	/* try to get the tty corresponding to $ttyname */</div><div class='ctx'> 	if (!trigger_data-&gt;tty) {</div><div class='hunk'>@@ -115,32 +227,83 @@ static void ledtrig_tty_work(struct work_struct *work)</div><div class='ctx'> 		trigger_data-&gt;tty = tty;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = tty_get_icount(trigger_data-&gt;tty, &amp;icount);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_info(trigger_data-&gt;tty-&gt;dev, "Failed to get icount, stopped polling\n");</div><div class='del'>-		mutex_unlock(&amp;trigger_data-&gt;mutex);</div><div class='del'>-		return;</div><div class='add'>+	status = tty_get_tiocm(trigger_data-&gt;tty);</div><div class='add'>+	if (status &gt; 0) {</div><div class='add'>+		if (trigger_data-&gt;mode_cts) {</div><div class='add'>+			if (status &amp; TIOCM_CTS)</div><div class='add'>+				state = TTY_LED_ENABLE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (trigger_data-&gt;mode_dsr) {</div><div class='add'>+			if (status &amp; TIOCM_DSR)</div><div class='add'>+				state = TTY_LED_ENABLE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (trigger_data-&gt;mode_dcd) {</div><div class='add'>+			if (status &amp; TIOCM_CAR)</div><div class='add'>+				state = TTY_LED_ENABLE;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (trigger_data-&gt;mode_rng) {</div><div class='add'>+			if (status &amp; TIOCM_RNG)</div><div class='add'>+				state = TTY_LED_ENABLE;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (icount.rx != trigger_data-&gt;rx ||</div><div class='del'>-	    icount.tx != trigger_data-&gt;tx) {</div><div class='del'>-		unsigned long interval = LEDTRIG_TTY_INTERVAL;</div><div class='add'>+	/*</div><div class='add'>+	 * The evaluation of rx/tx must be done after the evaluation</div><div class='add'>+	 * of TIOCM_*, because rx/tx has priority.</div><div class='add'>+	 */</div><div class='add'>+	if (trigger_data-&gt;mode_rx || trigger_data-&gt;mode_tx) {</div><div class='add'>+		struct serial_icounter_struct icount;</div><div class='ctx'> </div><div class='del'>-		led_blink_set_oneshot(trigger_data-&gt;led_cdev, &amp;interval,</div><div class='del'>-				      &amp;interval, 0);</div><div class='add'>+		ret = tty_get_icount(trigger_data-&gt;tty, &amp;icount);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='del'>-		trigger_data-&gt;rx = icount.rx;</div><div class='del'>-		trigger_data-&gt;tx = icount.tx;</div><div class='add'>+		if (trigger_data-&gt;mode_tx &amp;&amp; (icount.tx != trigger_data-&gt;tx)) {</div><div class='add'>+			trigger_data-&gt;tx = icount.tx;</div><div class='add'>+			invert = state == TTY_LED_ENABLE;</div><div class='add'>+			state = TTY_LED_BLINK;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (trigger_data-&gt;mode_rx &amp;&amp; (icount.rx != trigger_data-&gt;rx)) {</div><div class='add'>+			trigger_data-&gt;rx = icount.rx;</div><div class='add'>+			invert = state == TTY_LED_ENABLE;</div><div class='add'>+			state = TTY_LED_BLINK;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='del'>-	mutex_unlock(&amp;trigger_data-&gt;mutex);</div><div class='add'>+	switch (state) {</div><div class='add'>+	case TTY_LED_BLINK:</div><div class='add'>+		led_blink_set_oneshot(trigger_data-&gt;led_cdev, &amp;interval,</div><div class='add'>+				&amp;interval, invert);</div><div class='add'>+		break;</div><div class='add'>+	case TTY_LED_ENABLE:</div><div class='add'>+		led_set_brightness(trigger_data-&gt;led_cdev,</div><div class='add'>+				trigger_data-&gt;led_cdev-&gt;blink_brightness);</div><div class='add'>+		break;</div><div class='add'>+	case TTY_LED_DISABLE:</div><div class='add'>+		fallthrough;</div><div class='add'>+	default:</div><div class='add'>+		led_set_brightness(trigger_data-&gt;led_cdev, LED_OFF);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	complete_all(&amp;trigger_data-&gt;sysfs);</div><div class='ctx'> 	schedule_delayed_work(&amp;trigger_data-&gt;dwork,</div><div class='ctx'> 			      msecs_to_jiffies(LEDTRIG_TTY_INTERVAL * 2));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct attribute *ledtrig_tty_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_ttyname.attr,</div><div class='add'>+	&amp;dev_attr_rx.attr,</div><div class='add'>+	&amp;dev_attr_tx.attr,</div><div class='add'>+	&amp;dev_attr_cts.attr,</div><div class='add'>+	&amp;dev_attr_dsr.attr,</div><div class='add'>+	&amp;dev_attr_dcd.attr,</div><div class='add'>+	&amp;dev_attr_rng.attr,</div><div class='ctx'> 	NULL</div><div class='ctx'> };</div><div class='ctx'> ATTRIBUTE_GROUPS(ledtrig_tty);</div><div class='hunk'>@@ -153,11 +316,17 @@ static int ledtrig_tty_activate(struct led_classdev *led_cdev)</div><div class='ctx'> 	if (!trigger_data)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	/* Enable default rx/tx mode */</div><div class='add'>+	trigger_data-&gt;mode_rx = true;</div><div class='add'>+	trigger_data-&gt;mode_tx = true;</div><div class='add'>+</div><div class='ctx'> 	led_set_trigger_data(led_cdev, trigger_data);</div><div class='ctx'> </div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;trigger_data-&gt;dwork, ledtrig_tty_work);</div><div class='ctx'> 	trigger_data-&gt;led_cdev = led_cdev;</div><div class='del'>-	mutex_init(&amp;trigger_data-&gt;mutex);</div><div class='add'>+	init_completion(&amp;trigger_data-&gt;sysfs);</div><div class='add'>+</div><div class='add'>+	schedule_delayed_work(&amp;trigger_data-&gt;dwork, 0);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -168,6 +337,10 @@ static void ledtrig_tty_deactivate(struct led_classdev *led_cdev)</div><div class='ctx'> </div><div class='ctx'> 	cancel_delayed_work_sync(&amp;trigger_data-&gt;dwork);</div><div class='ctx'> </div><div class='add'>+	kfree(trigger_data-&gt;ttyname);</div><div class='add'>+	tty_kref_put(trigger_data-&gt;tty);</div><div class='add'>+	trigger_data-&gt;tty = NULL;</div><div class='add'>+</div><div class='ctx'> 	kfree(trigger_data);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig<br/>index bc2e265cb02d..42940108a187 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/Kconfig</a></div><div class='hunk'>@@ -8,18 +8,6 @@ menuconfig MAILBOX</div><div class='ctx'> </div><div class='ctx'> if MAILBOX</div><div class='ctx'> </div><div class='del'>-config APPLE_MAILBOX</div><div class='del'>-	tristate "Apple Mailbox driver"</div><div class='del'>-	depends on ARCH_APPLE || (ARM64 &amp;&amp; COMPILE_TEST)</div><div class='del'>-	default ARCH_APPLE</div><div class='del'>-	help</div><div class='del'>-	  Apple SoCs have various co-processors required for certain</div><div class='del'>-	  peripherals to work (NVMe, display controller, etc.). This</div><div class='del'>-	  driver adds support for the mailbox controller used to</div><div class='del'>-	  communicate with those.</div><div class='del'>-</div><div class='del'>-	  Say Y here if you have a Apple SoC.</div><div class='del'>-</div><div class='ctx'> config ARM_MHU</div><div class='ctx'> 	tristate "ARM MHU Mailbox"</div><div class='ctx'> 	depends on ARM_AMBA</div><div class='head'>diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile<br/>index fc9376117111..18793e6caa2f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/Makefile</a></div><div class='hunk'>@@ -60,5 +60,3 @@ obj-$(CONFIG_SUN6I_MSGBOX)	+= sun6i-msgbox.o</div><div class='ctx'> obj-$(CONFIG_SPRD_MBOX)		+= sprd-mailbox.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_QCOM_IPCC)		+= qcom-ipcc.o</div><div class='del'>-</div><div class='del'>-obj-$(CONFIG_APPLE_MAILBOX)	+= apple-mailbox.o</div><div class='head'>diff --git a/drivers/mailbox/apple-mailbox.c b/drivers/mailbox/apple-mailbox.c<br/>deleted file mode 100644<br/>index 2a3e8d8ff8b5..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/apple-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/apple-mailbox.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,441 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-only OR MIT</div><div class='del'>-/*</div><div class='del'>- * Apple mailbox driver</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 2021 The Asahi Linux Contributors</div><div class='del'>- *</div><div class='del'>- * This driver adds support for two mailbox variants (called ASC and M3 by</div><div class='del'>- * Apple) found in Apple SoCs such as the M1. It consists of two FIFOs used to</div><div class='del'>- * exchange 64+32 bit messages between the main CPU and a co-processor.</div><div class='del'>- * Various coprocessors implement different IPC protocols based on these simple</div><div class='del'>- * messages and shared memory buffers.</div><div class='del'>- *</div><div class='del'>- * Both the main CPU and the co-processor see the same set of registers but</div><div class='del'>- * the first FIFO (A2I) is always used to transfer messages from the application</div><div class='del'>- * processor (us) to the I/O processor and the second one (I2A) for the</div><div class='del'>- * other direction.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;linux/apple-mailbox.h&gt;</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/gfp.h&gt;</div><div class='del'>-#include &lt;linux/interrupt.h&gt;</div><div class='del'>-#include &lt;linux/io.h&gt;</div><div class='del'>-#include &lt;linux/mailbox_controller.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/platform_device.h&gt;</div><div class='del'>-#include &lt;linux/spinlock.h&gt;</div><div class='del'>-#include &lt;linux/types.h&gt;</div><div class='del'>-</div><div class='del'>-#define APPLE_ASC_MBOX_CONTROL_FULL  BIT(16)</div><div class='del'>-#define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17)</div><div class='del'>-</div><div class='del'>-#define APPLE_ASC_MBOX_A2I_CONTROL 0x110</div><div class='del'>-#define APPLE_ASC_MBOX_A2I_SEND0   0x800</div><div class='del'>-#define APPLE_ASC_MBOX_A2I_SEND1   0x808</div><div class='del'>-#define APPLE_ASC_MBOX_A2I_RECV0   0x810</div><div class='del'>-#define APPLE_ASC_MBOX_A2I_RECV1   0x818</div><div class='del'>-</div><div class='del'>-#define APPLE_ASC_MBOX_I2A_CONTROL 0x114</div><div class='del'>-#define APPLE_ASC_MBOX_I2A_SEND0   0x820</div><div class='del'>-#define APPLE_ASC_MBOX_I2A_SEND1   0x828</div><div class='del'>-#define APPLE_ASC_MBOX_I2A_RECV0   0x830</div><div class='del'>-#define APPLE_ASC_MBOX_I2A_RECV1   0x838</div><div class='del'>-</div><div class='del'>-#define APPLE_M3_MBOX_CONTROL_FULL  BIT(16)</div><div class='del'>-#define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17)</div><div class='del'>-</div><div class='del'>-#define APPLE_M3_MBOX_A2I_CONTROL 0x50</div><div class='del'>-#define APPLE_M3_MBOX_A2I_SEND0	  0x60</div><div class='del'>-#define APPLE_M3_MBOX_A2I_SEND1	  0x68</div><div class='del'>-#define APPLE_M3_MBOX_A2I_RECV0	  0x70</div><div class='del'>-#define APPLE_M3_MBOX_A2I_RECV1	  0x78</div><div class='del'>-</div><div class='del'>-#define APPLE_M3_MBOX_I2A_CONTROL 0x80</div><div class='del'>-#define APPLE_M3_MBOX_I2A_SEND0	  0x90</div><div class='del'>-#define APPLE_M3_MBOX_I2A_SEND1	  0x98</div><div class='del'>-#define APPLE_M3_MBOX_I2A_RECV0	  0xa0</div><div class='del'>-#define APPLE_M3_MBOX_I2A_RECV1	  0xa8</div><div class='del'>-</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_ENABLE	0x48</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_ACK		0x4c</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_A2I_EMPTY	BIT(0)</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_A2I_NOT_EMPTY BIT(1)</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_I2A_EMPTY	BIT(2)</div><div class='del'>-#define APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY BIT(3)</div><div class='del'>-</div><div class='del'>-#define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52)</div><div class='del'>-#define APPLE_MBOX_MSG1_INCNT  GENMASK(51, 48)</div><div class='del'>-#define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44)</div><div class='del'>-#define APPLE_MBOX_MSG1_INPTR  GENMASK(43, 40)</div><div class='del'>-#define APPLE_MBOX_MSG1_MSG    GENMASK(31, 0)</div><div class='del'>-</div><div class='del'>-struct apple_mbox_hw {</div><div class='del'>-	unsigned int control_full;</div><div class='del'>-	unsigned int control_empty;</div><div class='del'>-</div><div class='del'>-	unsigned int a2i_control;</div><div class='del'>-	unsigned int a2i_send0;</div><div class='del'>-	unsigned int a2i_send1;</div><div class='del'>-</div><div class='del'>-	unsigned int i2a_control;</div><div class='del'>-	unsigned int i2a_recv0;</div><div class='del'>-	unsigned int i2a_recv1;</div><div class='del'>-</div><div class='del'>-	bool has_irq_controls;</div><div class='del'>-	unsigned int irq_enable;</div><div class='del'>-	unsigned int irq_ack;</div><div class='del'>-	unsigned int irq_bit_recv_not_empty;</div><div class='del'>-	unsigned int irq_bit_send_empty;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct apple_mbox {</div><div class='del'>-	void __iomem *regs;</div><div class='del'>-	const struct apple_mbox_hw *hw;</div><div class='del'>-</div><div class='del'>-	int irq_recv_not_empty;</div><div class='del'>-	int irq_send_empty;</div><div class='del'>-</div><div class='del'>-	struct mbox_chan chan;</div><div class='del'>-</div><div class='del'>-	struct device *dev;</div><div class='del'>-	struct mbox_controller controller;</div><div class='del'>-	spinlock_t rx_lock;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct of_device_id apple_mbox_of_match[];</div><div class='del'>-</div><div class='del'>-static bool apple_mbox_hw_can_send(struct apple_mbox *apple_mbox)</div><div class='del'>-{</div><div class='del'>-	u32 mbox_ctrl =</div><div class='del'>-		readl_relaxed(apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;a2i_control);</div><div class='del'>-</div><div class='del'>-	return !(mbox_ctrl &amp; apple_mbox-&gt;hw-&gt;control_full);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool apple_mbox_hw_send_empty(struct apple_mbox *apple_mbox)</div><div class='del'>-{</div><div class='del'>-	u32 mbox_ctrl =</div><div class='del'>-		readl_relaxed(apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;a2i_control);</div><div class='del'>-</div><div class='del'>-	return mbox_ctrl &amp; apple_mbox-&gt;hw-&gt;control_empty;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_hw_send(struct apple_mbox *apple_mbox,</div><div class='del'>-			      struct apple_mbox_msg *msg)</div><div class='del'>-{</div><div class='del'>-	if (!apple_mbox_hw_can_send(apple_mbox))</div><div class='del'>-		return -EBUSY;</div><div class='del'>-</div><div class='del'>-	dev_dbg(apple_mbox-&gt;dev, "&gt; TX %016llx %08x\n", msg-&gt;msg0, msg-&gt;msg1);</div><div class='del'>-</div><div class='del'>-	writeq_relaxed(msg-&gt;msg0, apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;a2i_send0);</div><div class='del'>-	writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg-&gt;msg1),</div><div class='del'>-		       apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;a2i_send1);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool apple_mbox_hw_can_recv(struct apple_mbox *apple_mbox)</div><div class='del'>-{</div><div class='del'>-	u32 mbox_ctrl =</div><div class='del'>-		readl_relaxed(apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;i2a_control);</div><div class='del'>-</div><div class='del'>-	return !(mbox_ctrl &amp; apple_mbox-&gt;hw-&gt;control_empty);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_hw_recv(struct apple_mbox *apple_mbox,</div><div class='del'>-			      struct apple_mbox_msg *msg)</div><div class='del'>-{</div><div class='del'>-	if (!apple_mbox_hw_can_recv(apple_mbox))</div><div class='del'>-		return -ENOMSG;</div><div class='del'>-</div><div class='del'>-	msg-&gt;msg0 = readq_relaxed(apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;i2a_recv0);</div><div class='del'>-	msg-&gt;msg1 = FIELD_GET(</div><div class='del'>-		APPLE_MBOX_MSG1_MSG,</div><div class='del'>-		readq_relaxed(apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;i2a_recv1));</div><div class='del'>-</div><div class='del'>-	dev_dbg(apple_mbox-&gt;dev, "&lt; RX %016llx %08x\n", msg-&gt;msg0, msg-&gt;msg1);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_chan_send_data(struct mbox_chan *chan, void *data)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = chan-&gt;con_priv;</div><div class='del'>-	struct apple_mbox_msg *msg = data;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = apple_mbox_hw_send(apple_mbox, msg);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * The interrupt is level triggered and will keep firing as long as the</div><div class='del'>-	 * FIFO is empty. It will also keep firing if the FIFO was empty</div><div class='del'>-	 * at any point in the past until it has been acknowledged at the</div><div class='del'>-	 * mailbox level. By acknowledging it here we can ensure that we will</div><div class='del'>-	 * only get the interrupt once the FIFO has been cleared again.</div><div class='del'>-	 * If the FIFO is already empty before the ack it will fire again</div><div class='del'>-	 * immediately after the ack.</div><div class='del'>-	 */</div><div class='del'>-	if (apple_mbox-&gt;hw-&gt;has_irq_controls) {</div><div class='del'>-		writel_relaxed(apple_mbox-&gt;hw-&gt;irq_bit_send_empty,</div><div class='del'>-			       apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;irq_ack);</div><div class='del'>-	}</div><div class='del'>-	enable_irq(apple_mbox-&gt;irq_send_empty);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static irqreturn_t apple_mbox_send_empty_irq(int irq, void *data)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = data;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * We don't need to acknowledge the interrupt at the mailbox level</div><div class='del'>-	 * here even if supported by the hardware. It will keep firing but that</div><div class='del'>-	 * doesn't matter since it's disabled at the main interrupt controller.</div><div class='del'>-	 * apple_mbox_chan_send_data will acknowledge it before enabling</div><div class='del'>-	 * it at the main controller again.</div><div class='del'>-	 */</div><div class='del'>-	disable_irq_nosync(apple_mbox-&gt;irq_send_empty);</div><div class='del'>-	mbox_chan_txdone(&amp;apple_mbox-&gt;chan, 0);</div><div class='del'>-	return IRQ_HANDLED;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_poll(struct apple_mbox *apple_mbox)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox_msg msg;</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	while (apple_mbox_hw_recv(apple_mbox, &amp;msg) == 0) {</div><div class='del'>-		mbox_chan_received_data(&amp;apple_mbox-&gt;chan, (void *)&amp;msg);</div><div class='del'>-		ret++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * The interrupt will keep firing even if there are no more messages</div><div class='del'>-	 * unless we also acknowledge it at the mailbox level here.</div><div class='del'>-	 * There's no race if a message comes in between the check in the while</div><div class='del'>-	 * loop above and the ack below: If a new messages arrives inbetween</div><div class='del'>-	 * those two the interrupt will just fire again immediately after the</div><div class='del'>-	 * ack since it's level triggered.</div><div class='del'>-	 */</div><div class='del'>-	if (apple_mbox-&gt;hw-&gt;has_irq_controls) {</div><div class='del'>-		writel_relaxed(apple_mbox-&gt;hw-&gt;irq_bit_recv_not_empty,</div><div class='del'>-			       apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;irq_ack);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static irqreturn_t apple_mbox_recv_irq(int irq, void *data)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = data;</div><div class='del'>-</div><div class='del'>-	spin_lock(&amp;apple_mbox-&gt;rx_lock);</div><div class='del'>-	apple_mbox_poll(apple_mbox);</div><div class='del'>-	spin_unlock(&amp;apple_mbox-&gt;rx_lock);</div><div class='del'>-</div><div class='del'>-	return IRQ_HANDLED;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool apple_mbox_chan_peek_data(struct mbox_chan *chan)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = chan-&gt;con_priv;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;apple_mbox-&gt;rx_lock, flags);</div><div class='del'>-	ret = apple_mbox_poll(apple_mbox);</div><div class='del'>-	spin_unlock_irqrestore(&amp;apple_mbox-&gt;rx_lock, flags);</div><div class='del'>-</div><div class='del'>-	return ret &gt; 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_chan_flush(struct mbox_chan *chan, unsigned long timeout)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = chan-&gt;con_priv;</div><div class='del'>-	unsigned long deadline = jiffies + msecs_to_jiffies(timeout);</div><div class='del'>-</div><div class='del'>-	while (time_before(jiffies, deadline)) {</div><div class='del'>-		if (apple_mbox_hw_send_empty(apple_mbox)) {</div><div class='del'>-			mbox_chan_txdone(&amp;apple_mbox-&gt;chan, 0);</div><div class='del'>-			return 0;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		udelay(1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -ETIME;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_chan_startup(struct mbox_chan *chan)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = chan-&gt;con_priv;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Only some variants of this mailbox HW provide interrupt control</div><div class='del'>-	 * at the mailbox level. We therefore need to handle enabling/disabling</div><div class='del'>-	 * interrupts at the main interrupt controller anyway for hardware that</div><div class='del'>-	 * doesn't. Just always keep the interrupts we care about enabled at</div><div class='del'>-	 * the mailbox level so that both hardware revisions behave almost</div><div class='del'>-	 * the same.</div><div class='del'>-	 */</div><div class='del'>-	if (apple_mbox-&gt;hw-&gt;has_irq_controls) {</div><div class='del'>-		writel_relaxed(apple_mbox-&gt;hw-&gt;irq_bit_recv_not_empty |</div><div class='del'>-				       apple_mbox-&gt;hw-&gt;irq_bit_send_empty,</div><div class='del'>-			       apple_mbox-&gt;regs + apple_mbox-&gt;hw-&gt;irq_enable);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	enable_irq(apple_mbox-&gt;irq_recv_not_empty);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void apple_mbox_chan_shutdown(struct mbox_chan *chan)</div><div class='del'>-{</div><div class='del'>-	struct apple_mbox *apple_mbox = chan-&gt;con_priv;</div><div class='del'>-</div><div class='del'>-	disable_irq(apple_mbox-&gt;irq_recv_not_empty);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct mbox_chan_ops apple_mbox_ops = {</div><div class='del'>-	.send_data = apple_mbox_chan_send_data,</div><div class='del'>-	.peek_data = apple_mbox_chan_peek_data,</div><div class='del'>-	.flush = apple_mbox_chan_flush,</div><div class='del'>-	.startup = apple_mbox_chan_startup,</div><div class='del'>-	.shutdown = apple_mbox_chan_shutdown,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct mbox_chan *apple_mbox_of_xlate(struct mbox_controller *mbox,</div><div class='del'>-					     const struct of_phandle_args *args)</div><div class='del'>-{</div><div class='del'>-	if (args-&gt;args_count != 0)</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-</div><div class='del'>-	return &amp;mbox-&gt;chans[0];</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int apple_mbox_probe(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-	const struct of_device_id *match;</div><div class='del'>-	char *irqname;</div><div class='del'>-	struct apple_mbox *mbox;</div><div class='del'>-	struct device *dev = &amp;pdev-&gt;dev;</div><div class='del'>-</div><div class='del'>-	match = of_match_node(apple_mbox_of_match, pdev-&gt;dev.of_node);</div><div class='del'>-	if (!match)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	if (!match-&gt;data)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);</div><div class='del'>-	if (!mbox)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	platform_set_drvdata(pdev, mbox);</div><div class='del'>-</div><div class='del'>-	mbox-&gt;dev = dev;</div><div class='del'>-	mbox-&gt;regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='del'>-	if (IS_ERR(mbox-&gt;regs))</div><div class='del'>-		return PTR_ERR(mbox-&gt;regs);</div><div class='del'>-</div><div class='del'>-	mbox-&gt;hw = match-&gt;data;</div><div class='del'>-	mbox-&gt;irq_recv_not_empty =</div><div class='del'>-		platform_get_irq_byname(pdev, "recv-not-empty");</div><div class='del'>-	if (mbox-&gt;irq_recv_not_empty &lt; 0)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	mbox-&gt;irq_send_empty = platform_get_irq_byname(pdev, "send-empty");</div><div class='del'>-	if (mbox-&gt;irq_send_empty &lt; 0)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	mbox-&gt;controller.dev = mbox-&gt;dev;</div><div class='del'>-	mbox-&gt;controller.num_chans = 1;</div><div class='del'>-	mbox-&gt;controller.chans = &amp;mbox-&gt;chan;</div><div class='del'>-	mbox-&gt;controller.ops = &amp;apple_mbox_ops;</div><div class='del'>-	mbox-&gt;controller.txdone_irq = true;</div><div class='del'>-	mbox-&gt;controller.of_xlate = apple_mbox_of_xlate;</div><div class='del'>-	mbox-&gt;chan.con_priv = mbox;</div><div class='del'>-	spin_lock_init(&amp;mbox-&gt;rx_lock);</div><div class='del'>-</div><div class='del'>-	irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-recv", dev_name(dev));</div><div class='del'>-	if (!irqname)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	ret = devm_request_threaded_irq(dev, mbox-&gt;irq_recv_not_empty, NULL,</div><div class='del'>-					apple_mbox_recv_irq,</div><div class='del'>-					IRQF_NO_AUTOEN | IRQF_ONESHOT, irqname,</div><div class='del'>-					mbox);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-send", dev_name(dev));</div><div class='del'>-	if (!irqname)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	ret = devm_request_irq(dev, mbox-&gt;irq_send_empty,</div><div class='del'>-			       apple_mbox_send_empty_irq, IRQF_NO_AUTOEN,</div><div class='del'>-			       irqname, mbox);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	return devm_mbox_controller_register(dev, &amp;mbox-&gt;controller);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct apple_mbox_hw apple_mbox_asc_hw = {</div><div class='del'>-	.control_full = APPLE_ASC_MBOX_CONTROL_FULL,</div><div class='del'>-	.control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY,</div><div class='del'>-</div><div class='del'>-	.a2i_control = APPLE_ASC_MBOX_A2I_CONTROL,</div><div class='del'>-	.a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0,</div><div class='del'>-	.a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1,</div><div class='del'>-</div><div class='del'>-	.i2a_control = APPLE_ASC_MBOX_I2A_CONTROL,</div><div class='del'>-	.i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0,</div><div class='del'>-	.i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1,</div><div class='del'>-</div><div class='del'>-	.has_irq_controls = false,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct apple_mbox_hw apple_mbox_m3_hw = {</div><div class='del'>-	.control_full = APPLE_M3_MBOX_CONTROL_FULL,</div><div class='del'>-	.control_empty = APPLE_M3_MBOX_CONTROL_EMPTY,</div><div class='del'>-</div><div class='del'>-	.a2i_control = APPLE_M3_MBOX_A2I_CONTROL,</div><div class='del'>-	.a2i_send0 = APPLE_M3_MBOX_A2I_SEND0,</div><div class='del'>-	.a2i_send1 = APPLE_M3_MBOX_A2I_SEND1,</div><div class='del'>-</div><div class='del'>-	.i2a_control = APPLE_M3_MBOX_I2A_CONTROL,</div><div class='del'>-	.i2a_recv0 = APPLE_M3_MBOX_I2A_RECV0,</div><div class='del'>-	.i2a_recv1 = APPLE_M3_MBOX_I2A_RECV1,</div><div class='del'>-</div><div class='del'>-	.has_irq_controls = true,</div><div class='del'>-	.irq_enable = APPLE_M3_MBOX_IRQ_ENABLE,</div><div class='del'>-	.irq_ack = APPLE_M3_MBOX_IRQ_ACK,</div><div class='del'>-	.irq_bit_recv_not_empty = APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY,</div><div class='del'>-	.irq_bit_send_empty = APPLE_M3_MBOX_IRQ_A2I_EMPTY,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct of_device_id apple_mbox_of_match[] = {</div><div class='del'>-	{ .compatible = "apple,asc-mailbox-v4", .data = &amp;apple_mbox_asc_hw },</div><div class='del'>-	{ .compatible = "apple,m3-mailbox-v2", .data = &amp;apple_mbox_m3_hw },</div><div class='del'>-	{}</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(of, apple_mbox_of_match);</div><div class='del'>-</div><div class='del'>-static struct platform_driver apple_mbox_driver = {</div><div class='del'>-	.driver = {</div><div class='del'>-		.name = "apple-mailbox",</div><div class='del'>-		.of_match_table = apple_mbox_of_match,</div><div class='del'>-	},</div><div class='del'>-	.probe = apple_mbox_probe,</div><div class='del'>-};</div><div class='del'>-module_platform_driver(apple_mbox_driver);</div><div class='del'>-</div><div class='del'>-MODULE_LICENSE("Dual MIT/GPL");</div><div class='del'>-MODULE_AUTHOR("Sven Peter &lt;sven@svenpeter.dev&gt;");</div><div class='del'>-MODULE_DESCRIPTION("Apple Mailbox driver");</div><div class='head'>diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c<br/>index c6d4957c4da8..0ec21dcdbde7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/arm_mhuv2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/arm_mhuv2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/arm_mhuv2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/arm_mhuv2.c</a></div><div class='hunk'>@@ -553,7 +553,8 @@ static irqreturn_t mhuv2_sender_interrupt(int irq, void *data)</div><div class='ctx'> 	priv = chan-&gt;con_priv;</div><div class='ctx'> </div><div class='ctx'> 	if (!IS_PROTOCOL_DOORBELL(priv)) {</div><div class='del'>-		writel_relaxed(1, &amp;mhu-&gt;send-&gt;ch_wn[priv-&gt;ch_wn_idx + priv-&gt;windows - 1].int_clr);</div><div class='add'>+		for (i = 0; i &lt; priv-&gt;windows; i++)</div><div class='add'>+			writel_relaxed(1, &amp;mhu-&gt;send-&gt;ch_wn[priv-&gt;ch_wn_idx + i].int_clr);</div><div class='ctx'> </div><div class='ctx'> 		if (chan-&gt;cl) {</div><div class='ctx'> 			mbox_chan_txdone(chan, 0);</div><div class='head'>diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c<br/>index a2b8839d4e7c..e3e28a4f7d01 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/bcm-flexrm-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/bcm-flexrm-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/bcm-flexrm-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/bcm-flexrm-mailbox.c</a></div><div class='hunk'>@@ -1650,7 +1650,7 @@ fail:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int flexrm_mbox_remove(struct platform_device *pdev)</div><div class='add'>+static void flexrm_mbox_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct flexrm_mbox *mbox = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -1661,8 +1661,6 @@ static int flexrm_mbox_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dma_pool_destroy(mbox-&gt;cmpl_pool);</div><div class='ctx'> 	dma_pool_destroy(mbox-&gt;bd_pool);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id flexrm_mbox_of_match[] = {</div><div class='hunk'>@@ -1677,7 +1675,7 @@ static struct platform_driver flexrm_mbox_driver = {</div><div class='ctx'> 		.of_match_table = flexrm_mbox_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= flexrm_mbox_probe,</div><div class='del'>-	.remove		= flexrm_mbox_remove,</div><div class='add'>+	.remove_new	= flexrm_mbox_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(flexrm_mbox_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mailbox/bcm-pdc-mailbox.c b/drivers/mailbox/bcm-pdc-mailbox.c<br/>index 778faeced81e..1768d3d5aaa0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/bcm-pdc-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/bcm-pdc-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/bcm-pdc-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/bcm-pdc-mailbox.c</a></div><div class='hunk'>@@ -1605,7 +1605,7 @@ cleanup:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pdc_remove(struct platform_device *pdev)</div><div class='add'>+static void pdc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pdc_state *pdcs = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1617,12 +1617,11 @@ static int pdc_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dma_pool_destroy(pdcs-&gt;rx_buf_pool);</div><div class='ctx'> 	dma_pool_destroy(pdcs-&gt;ring_pool);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver pdc_mbox_driver = {</div><div class='ctx'> 	.probe = pdc_probe,</div><div class='del'>-	.remove = pdc_remove,</div><div class='add'>+	.remove_new = pdc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "brcm-iproc-pdc-mbox",</div><div class='ctx'> 		   .of_match_table = pdc_mbox_of_match,</div><div class='head'>diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c<br/>index 0af739ab571c..656171362fe9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/imx-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/imx-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/imx-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/imx-mailbox.c</a></div><div class='hunk'>@@ -903,13 +903,11 @@ disable_runtime_pm:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx_mu_remove(struct platform_device *pdev)</div><div class='add'>+static void imx_mu_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx_mu_priv *priv = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(priv-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {</div><div class='hunk'>@@ -1070,7 +1068,7 @@ static const struct dev_pm_ops imx_mu_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver imx_mu_driver = {</div><div class='ctx'> 	.probe		= imx_mu_probe,</div><div class='del'>-	.remove		= imx_mu_remove,</div><div class='add'>+	.remove_new	= imx_mu_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "imx_mu",</div><div class='ctx'> 		.of_match_table = imx_mu_dt_ids,</div><div class='head'>diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c<br/>index 22d6018ceec3..3386b4e72551 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/mailbox-test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/mailbox-test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/mailbox-test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/mailbox-test.c</a></div><div class='hunk'>@@ -418,7 +418,7 @@ static int mbox_test_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mbox_test_remove(struct platform_device *pdev)</div><div class='add'>+static void mbox_test_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mbox_test_device *tdev = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -428,8 +428,6 @@ static int mbox_test_remove(struct platform_device *pdev)</div><div class='ctx'> 		mbox_free_channel(tdev-&gt;tx_channel);</div><div class='ctx'> 	if (tdev-&gt;rx_channel)</div><div class='ctx'> 		mbox_free_channel(tdev-&gt;rx_channel);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mbox_test_match[] = {</div><div class='hunk'>@@ -444,7 +442,7 @@ static struct platform_driver mbox_test_driver = {</div><div class='ctx'> 		.of_match_table = mbox_test_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe  = mbox_test_probe,</div><div class='del'>-	.remove = mbox_test_remove,</div><div class='add'>+	.remove_new = mbox_test_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(mbox_test_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c<br/>index de862e9137d5..ead2200f39ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/mtk-cmdq-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/mtk-cmdq-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/mtk-cmdq-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/mtk-cmdq-mailbox.c</a></div><div class='hunk'>@@ -367,7 +367,7 @@ static int cmdq_resume(struct device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cmdq_remove(struct platform_device *pdev)</div><div class='add'>+static void cmdq_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct cmdq *cmdq = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -378,7 +378,6 @@ static int cmdq_remove(struct platform_device *pdev)</div><div class='ctx'> 		cmdq_runtime_suspend(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	clk_bulk_unprepare(cmdq-&gt;pdata-&gt;gce_num, cmdq-&gt;clocks);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)</div><div class='hunk'>@@ -706,62 +705,70 @@ static const struct dev_pm_ops cmdq_pm_ops = {</div><div class='ctx'> 			   cmdq_runtime_resume, NULL)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v2 = {</div><div class='del'>-	.thread_nr = 16,</div><div class='del'>-	.shift = 0,</div><div class='add'>+static const struct gce_plat gce_plat_mt6779 = {</div><div class='add'>+	.thread_nr = 24,</div><div class='add'>+	.shift = 3,</div><div class='ctx'> 	.control_by_sw = false,</div><div class='ctx'> 	.gce_num = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v3 = {</div><div class='del'>-	.thread_nr = 24,</div><div class='add'>+static const struct gce_plat gce_plat_mt8173 = {</div><div class='add'>+	.thread_nr = 16,</div><div class='ctx'> 	.shift = 0,</div><div class='ctx'> 	.control_by_sw = false,</div><div class='ctx'> 	.gce_num = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v4 = {</div><div class='add'>+static const struct gce_plat gce_plat_mt8183 = {</div><div class='ctx'> 	.thread_nr = 24,</div><div class='del'>-	.shift = 3,</div><div class='add'>+	.shift = 0,</div><div class='ctx'> 	.control_by_sw = false,</div><div class='ctx'> 	.gce_num = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v5 = {</div><div class='add'>+static const struct gce_plat gce_plat_mt8186 = {</div><div class='ctx'> 	.thread_nr = 24,</div><div class='ctx'> 	.shift = 3,</div><div class='ctx'> 	.control_by_sw = true,</div><div class='add'>+	.sw_ddr_en = true,</div><div class='ctx'> 	.gce_num = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v6 = {</div><div class='del'>-	.thread_nr = 24,</div><div class='add'>+static const struct gce_plat gce_plat_mt8188 = {</div><div class='add'>+	.thread_nr = 32,</div><div class='ctx'> 	.shift = 3,</div><div class='ctx'> 	.control_by_sw = true,</div><div class='ctx'> 	.gce_num = 2</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct gce_plat gce_plat_v7 = {</div><div class='add'>+static const struct gce_plat gce_plat_mt8192 = {</div><div class='ctx'> 	.thread_nr = 24,</div><div class='ctx'> 	.shift = 3,</div><div class='ctx'> 	.control_by_sw = true,</div><div class='del'>-	.sw_ddr_en = true,</div><div class='ctx'> 	.gce_num = 1</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct gce_plat gce_plat_mt8195 = {</div><div class='add'>+	.thread_nr = 24,</div><div class='add'>+	.shift = 3,</div><div class='add'>+	.control_by_sw = true,</div><div class='add'>+	.gce_num = 2</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id cmdq_of_ids[] = {</div><div class='del'>-	{.compatible = "mediatek,mt8173-gce", .data = (void *)&amp;gce_plat_v2},</div><div class='del'>-	{.compatible = "mediatek,mt8183-gce", .data = (void *)&amp;gce_plat_v3},</div><div class='del'>-	{.compatible = "mediatek,mt8186-gce", .data = (void *)&amp;gce_plat_v7},</div><div class='del'>-	{.compatible = "mediatek,mt6779-gce", .data = (void *)&amp;gce_plat_v4},</div><div class='del'>-	{.compatible = "mediatek,mt8192-gce", .data = (void *)&amp;gce_plat_v5},</div><div class='del'>-	{.compatible = "mediatek,mt8195-gce", .data = (void *)&amp;gce_plat_v6},</div><div class='add'>+	{.compatible = "mediatek,mt6779-gce", .data = (void *)&amp;gce_plat_mt6779},</div><div class='add'>+	{.compatible = "mediatek,mt8173-gce", .data = (void *)&amp;gce_plat_mt8173},</div><div class='add'>+	{.compatible = "mediatek,mt8183-gce", .data = (void *)&amp;gce_plat_mt8183},</div><div class='add'>+	{.compatible = "mediatek,mt8186-gce", .data = (void *)&amp;gce_plat_mt8186},</div><div class='add'>+	{.compatible = "mediatek,mt8188-gce", .data = (void *)&amp;gce_plat_mt8188},</div><div class='add'>+	{.compatible = "mediatek,mt8192-gce", .data = (void *)&amp;gce_plat_mt8192},</div><div class='add'>+	{.compatible = "mediatek,mt8195-gce", .data = (void *)&amp;gce_plat_mt8195},</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver cmdq_drv = {</div><div class='ctx'> 	.probe = cmdq_probe,</div><div class='del'>-	.remove = cmdq_remove,</div><div class='add'>+	.remove_new = cmdq_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "mtk_cmdq",</div><div class='ctx'> 		.pm = &amp;cmdq_pm_ops,</div><div class='head'>diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c<br/>index 792bcaebbc9b..c961706fe61d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/omap-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/omap-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/omap-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/omap-mailbox.c</a></div><div class='hunk'>@@ -865,19 +865,17 @@ unregister:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int omap_mbox_remove(struct platform_device *pdev)</div><div class='add'>+static void omap_mbox_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct omap_mbox_device *mdev = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(mdev-&gt;dev);</div><div class='ctx'> 	omap_mbox_unregister(mdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver omap_mbox_driver = {</div><div class='ctx'> 	.probe	= omap_mbox_probe,</div><div class='del'>-	.remove	= omap_mbox_remove,</div><div class='add'>+	.remove_new = omap_mbox_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = "omap-mailbox",</div><div class='ctx'> 		.pm = &amp;omap_mbox_pm_ops,</div><div class='head'>diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c<br/>index 002a135ee868..7d91e7c016ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/qcom-apcs-ipc-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/qcom-apcs-ipc-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/qcom-apcs-ipc-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/qcom-apcs-ipc-mailbox.c</a></div><div class='hunk'>@@ -129,14 +129,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qcom_apcs_ipc_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_apcs_ipc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_apcs_ipc *apcs = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct platform_device *clk = apcs-&gt;clk;</div><div class='ctx'> </div><div class='ctx'> 	platform_device_unregister(clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* .data is the offset of the ipc register within the global block */</div><div class='hunk'>@@ -145,19 +143,19 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {</div><div class='ctx'> 	{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &amp;msm8916_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &amp;msm8916_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &amp;msm8994_apcs_data },</div><div class='del'>-	{ .compatible = "qcom,msm8976-apcs-kpss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,msm8994-apcs-kpss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = &amp;msm8996_apcs_data },</div><div class='del'>-	{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,qcm2290-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='add'>+	{ .compatible = "qcom,sdm845-apss-shared", .data = &amp;apps_shared_apcs_data },</div><div class='add'>+	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &amp;sdx55_apcs_data },</div><div class='add'>+	/* Do not add any more entries using existing driver data */</div><div class='add'>+	{ .compatible = "qcom,msm8976-apcs-kpss-global", .data = &amp;msm8994_apcs_data },</div><div class='add'>+	{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &amp;msm8916_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='del'>-	{ .compatible = "qcom,sdm845-apss-shared", .data = &amp;apps_shared_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm4250-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm6125-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,sm6115-apcs-hmss-global", .data = &amp;msm8994_apcs_data },</div><div class='del'>-	{ .compatible = "qcom,sdx55-apcs-gcc", .data = &amp;sdx55_apcs_data },</div><div class='del'>-	/* Do not add any more entries using existing driver data */</div><div class='ctx'> 	{ .compatible = "qcom,ipq5332-apcs-apps-global", .data = &amp;ipq6018_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &amp;ipq6018_apcs_data },</div><div class='ctx'> 	{ .compatible = "qcom,sc7180-apss-shared", .data = &amp;apps_shared_apcs_data },</div><div class='hunk'>@@ -169,7 +167,7 @@ MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcom_apcs_ipc_driver = {</div><div class='ctx'> 	.probe = qcom_apcs_ipc_probe,</div><div class='del'>-	.remove = qcom_apcs_ipc_remove,</div><div class='add'>+	.remove_new = qcom_apcs_ipc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom_apcs_ipc",</div><div class='ctx'> 		.of_match_table = qcom_apcs_ipc_of_match,</div><div class='head'>diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c<br/>index f597a1bd5684..d537cc9c4d4b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/qcom-ipcc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/qcom-ipcc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/qcom-ipcc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/qcom-ipcc.c</a></div><div class='hunk'>@@ -326,14 +326,12 @@ err_mbox:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qcom_ipcc_remove(struct platform_device *pdev)</div><div class='add'>+static void qcom_ipcc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	disable_irq_wake(ipcc-&gt;irq);</div><div class='ctx'> 	irq_domain_remove(ipcc-&gt;irq_domain);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id qcom_ipcc_of_match[] = {</div><div class='hunk'>@@ -348,7 +346,7 @@ static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver qcom_ipcc_driver = {</div><div class='ctx'> 	.probe = qcom_ipcc_probe,</div><div class='del'>-	.remove = qcom_ipcc_remove,</div><div class='add'>+	.remove_new = qcom_ipcc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "qcom-ipcc",</div><div class='ctx'> 		.of_match_table = qcom_ipcc_of_match,</div><div class='head'>diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c<br/>index 4ad3653f3866..1442f275782b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/stm32-ipcc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/stm32-ipcc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/stm32-ipcc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/stm32-ipcc.c</a></div><div class='hunk'>@@ -331,7 +331,7 @@ err_clk:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stm32_ipcc_remove(struct platform_device *pdev)</div><div class='add'>+static void stm32_ipcc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='hunk'>@@ -339,8 +339,6 @@ static int stm32_ipcc_remove(struct platform_device *pdev)</div><div class='ctx'> 		dev_pm_clear_wake_irq(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	device_set_wakeup_capable(dev, false);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM_SLEEP</div><div class='hunk'>@@ -381,7 +379,7 @@ static struct platform_driver stm32_ipcc_driver = {</div><div class='ctx'> 		.of_match_table = stm32_ipcc_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= stm32_ipcc_probe,</div><div class='del'>-	.remove		= stm32_ipcc_remove,</div><div class='add'>+	.remove_new	= stm32_ipcc_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(stm32_ipcc_driver);</div><div class='head'>diff --git a/drivers/mailbox/sun6i-msgbox.c b/drivers/mailbox/sun6i-msgbox.c<br/>index 7f8d931042d3..3dcc54dc83b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/sun6i-msgbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/sun6i-msgbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/sun6i-msgbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/sun6i-msgbox.c</a></div><div class='hunk'>@@ -287,15 +287,13 @@ err_disable_unprepare:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sun6i_msgbox_remove(struct platform_device *pdev)</div><div class='add'>+static void sun6i_msgbox_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sun6i_msgbox *mbox = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	mbox_controller_unregister(&amp;mbox-&gt;controller);</div><div class='ctx'> 	/* See the comment in sun6i_msgbox_probe about the reset line. */</div><div class='ctx'> 	clk_disable_unprepare(mbox-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id sun6i_msgbox_of_match[] = {</div><div class='hunk'>@@ -310,7 +308,7 @@ static struct platform_driver sun6i_msgbox_driver = {</div><div class='ctx'> 		.of_match_table = sun6i_msgbox_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe  = sun6i_msgbox_probe,</div><div class='del'>-	.remove = sun6i_msgbox_remove,</div><div class='add'>+	.remove_new = sun6i_msgbox_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(sun6i_msgbox_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c<br/>index fe29fc2ca526..19ef56cbcfd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/tegra-hsp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/tegra-hsp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/tegra-hsp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/tegra-hsp.c</a></div><div class='hunk'>@@ -868,13 +868,11 @@ static int tegra_hsp_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tegra_hsp_remove(struct platform_device *pdev)</div><div class='add'>+static void tegra_hsp_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tegra_hsp *hsp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	lockdep_unregister_key(&amp;hsp-&gt;lock_key);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused tegra_hsp_resume(struct device *dev)</div><div class='hunk'>@@ -953,7 +951,7 @@ static struct platform_driver tegra_hsp_driver = {</div><div class='ctx'> 		.pm = &amp;tegra_hsp_pm_ops,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = tegra_hsp_probe,</div><div class='del'>-	.remove = tegra_hsp_remove,</div><div class='add'>+	.remove_new = tegra_hsp_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init tegra_hsp_init(void)</div><div class='head'>diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c b/drivers/mailbox/zynqmp-ipi-mailbox.c<br/>index 7fa533e80dd9..25c65afc030a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mailbox/zynqmp-ipi-mailbox.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mailbox/zynqmp-ipi-mailbox.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mailbox/zynqmp-ipi-mailbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mailbox/zynqmp-ipi-mailbox.c</a></div><div class='hunk'>@@ -81,7 +81,6 @@ struct zynqmp_ipi_mchan {</div><div class='ctx'>  * @remote_id:            remote IPI agent ID</div><div class='ctx'>  * @mbox:                 mailbox Controller</div><div class='ctx'>  * @mchans:               array for channels, tx channel and rx channel.</div><div class='del'>- * @irq:                  IPI agent interrupt ID</div><div class='ctx'>  */</div><div class='ctx'> struct zynqmp_ipi_mbox {</div><div class='ctx'> 	struct zynqmp_ipi_pdata *pdata;</div><div class='hunk'>@@ -688,19 +687,17 @@ free_mbox_dev:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int zynqmp_ipi_remove(struct platform_device *pdev)</div><div class='add'>+static void zynqmp_ipi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct zynqmp_ipi_pdata *pdata;</div><div class='ctx'> </div><div class='ctx'> 	pdata = platform_get_drvdata(pdev);</div><div class='ctx'> 	zynqmp_ipi_free_mboxes(pdata);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver zynqmp_ipi_driver = {</div><div class='ctx'> 	.probe = zynqmp_ipi_probe,</div><div class='del'>-	.remove = zynqmp_ipi_remove,</div><div class='add'>+	.remove_new = zynqmp_ipi_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		   .name = "zynqmp-ipi",</div><div class='ctx'> 		   .of_match_table = of_match_ptr(zynqmp_ipi_of_match),</div><div class='head'>diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c<br/>index ba4530459de8..61994da7bad0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mcb/mcb-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mcb/mcb-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mcb/mcb-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mcb/mcb-core.c</a></div><div class='hunk'>@@ -263,6 +263,7 @@ static void mcb_free_bus(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * mcb_alloc_bus() - Allocate a new @mcb_bus</div><div class='add'>+ * @carrier: generic &amp;struct device for the carrier device</div><div class='ctx'>  *</div><div class='ctx'>  * Allocate a new @mcb_bus.</div><div class='ctx'>  */</div><div class='hunk'>@@ -327,7 +328,7 @@ void mcb_release_bus(struct mcb_bus *bus)</div><div class='ctx'> EXPORT_SYMBOL_NS_GPL(mcb_release_bus, MCB);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * mcb_bus_put() - Increment refcnt</div><div class='add'>+ * mcb_bus_get() - Increment refcnt</div><div class='ctx'>  * @bus: The @mcb_bus</div><div class='ctx'>  *</div><div class='ctx'>  * Get a @mcb_bus' ref</div><div class='hunk'>@@ -455,7 +456,7 @@ EXPORT_SYMBOL_NS_GPL(mcb_request_mem, MCB);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * mcb_release_mem() - Release memory requested by device</div><div class='del'>- * @dev: The @mcb_device that requested the memory</div><div class='add'>+ * @mem: The memory resource to be released</div><div class='ctx'>  *</div><div class='ctx'>  * Release memory that was prior requested via @mcb_request_mem().</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig<br/>index 2a8b081bce7d..a743e2c572fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/Kconfig</a></div><div class='hunk'>@@ -61,19 +61,6 @@ config MD_BITMAP_FILE</div><div class='ctx'> 	  various kernel APIs and can only work with files on a file system not</div><div class='ctx'> 	  actually sitting on the MD device.</div><div class='ctx'> </div><div class='del'>-config MD_LINEAR</div><div class='del'>-	tristate "Linear (append) mode (deprecated)"</div><div class='del'>-	depends on BLK_DEV_MD</div><div class='del'>-	help</div><div class='del'>-	  If you say Y here, then your multiple devices driver will be able to</div><div class='del'>-	  use the so-called linear mode, i.e. it will combine the hard disk</div><div class='del'>-	  partitions by simply appending one to the other.</div><div class='del'>-</div><div class='del'>-	  To compile this as a module, choose M here: the module</div><div class='del'>-	  will be called linear.</div><div class='del'>-</div><div class='del'>-	  If unsure, say Y.</div><div class='del'>-</div><div class='ctx'> config MD_RAID0</div><div class='ctx'> 	tristate "RAID-0 (striping) mode"</div><div class='ctx'> 	depends on BLK_DEV_MD</div><div class='hunk'>@@ -172,27 +159,6 @@ config MD_RAID456</div><div class='ctx'> </div><div class='ctx'> 	  If unsure, say Y.</div><div class='ctx'> </div><div class='del'>-config MD_MULTIPATH</div><div class='del'>-	tristate "Multipath I/O support (deprecated)"</div><div class='del'>-	depends on BLK_DEV_MD</div><div class='del'>-	help</div><div class='del'>-	  MD_MULTIPATH provides a simple multi-path personality for use</div><div class='del'>-	  the MD framework.  It is not under active development.  New</div><div class='del'>-	  projects should consider using DM_MULTIPATH which has more</div><div class='del'>-	  features and more testing.</div><div class='del'>-</div><div class='del'>-	  If unsure, say N.</div><div class='del'>-</div><div class='del'>-config MD_FAULTY</div><div class='del'>-	tristate "Faulty test module for MD (deprecated)"</div><div class='del'>-	depends on BLK_DEV_MD</div><div class='del'>-	help</div><div class='del'>-	  The "faulty" module allows for a block device that occasionally returns</div><div class='del'>-	  read or write errors.  It is useful for testing.</div><div class='del'>-</div><div class='del'>-	  In unsure, say N.</div><div class='del'>-</div><div class='del'>-</div><div class='ctx'> config MD_CLUSTER</div><div class='ctx'> 	tristate "Cluster Support for MD"</div><div class='ctx'> 	depends on BLK_DEV_MD</div><div class='hunk'>@@ -660,6 +626,7 @@ config DM_ZONED</div><div class='ctx'> </div><div class='ctx'> config DM_AUDIT</div><div class='ctx'> 	bool "DM audit events"</div><div class='add'>+	depends on BLK_DEV_DM</div><div class='ctx'> 	depends on AUDIT</div><div class='ctx'> 	help</div><div class='ctx'> 	  Generate audit events for device-mapper.</div><div class='head'>diff --git a/drivers/md/Makefile b/drivers/md/Makefile<br/>index 84291e38dca8..027d7cfeca3f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/Makefile</a></div><div class='hunk'>@@ -29,22 +29,16 @@ dm-zoned-y	+= dm-zoned-target.o dm-zoned-metadata.o dm-zoned-reclaim.o</div><div class='ctx'> </div><div class='ctx'> md-mod-y	+= md.o md-bitmap.o</div><div class='ctx'> raid456-y	+= raid5.o raid5-cache.o raid5-ppl.o</div><div class='del'>-linear-y	+= md-linear.o</div><div class='del'>-multipath-y	+= md-multipath.o</div><div class='del'>-faulty-y	+= md-faulty.o</div><div class='ctx'> </div><div class='ctx'> # Note: link order is important.  All raid personalities</div><div class='del'>-# and must come before md.o, as they each initialise </div><div class='del'>-# themselves, and md.o may use the personalities when it </div><div class='add'>+# and must come before md.o, as they each initialise</div><div class='add'>+# themselves, and md.o may use the personalities when it</div><div class='ctx'> # auto-initialised.</div><div class='ctx'> </div><div class='del'>-obj-$(CONFIG_MD_LINEAR)		+= linear.o</div><div class='ctx'> obj-$(CONFIG_MD_RAID0)		+= raid0.o</div><div class='ctx'> obj-$(CONFIG_MD_RAID1)		+= raid1.o</div><div class='ctx'> obj-$(CONFIG_MD_RAID10)		+= raid10.o</div><div class='ctx'> obj-$(CONFIG_MD_RAID456)	+= raid456.o</div><div class='del'>-obj-$(CONFIG_MD_MULTIPATH)	+= multipath.o</div><div class='del'>-obj-$(CONFIG_MD_FAULTY)		+= faulty.o</div><div class='ctx'> obj-$(CONFIG_MD_CLUSTER)	+= md-cluster.o</div><div class='ctx'> obj-$(CONFIG_BCACHE)		+= bcache/</div><div class='ctx'> obj-$(CONFIG_BLK_DEV_MD)	+= md-mod.o</div><div class='head'>diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c<br/>index de3019972b35..196cdacce38f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/btree.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/btree.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/btree.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/btree.c</a></div><div class='hunk'>@@ -293,16 +293,16 @@ static void btree_complete_write(struct btree *b, struct btree_write *w)</div><div class='ctx'> 	w-&gt;journal	= NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void btree_node_write_unlock(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(btree_node_write_unlock)</div><div class='ctx'> {</div><div class='del'>-	struct btree *b = container_of(cl, struct btree, io);</div><div class='add'>+	closure_type(b, struct btree, io);</div><div class='ctx'> </div><div class='ctx'> 	up(&amp;b-&gt;io_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __btree_node_write_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(__btree_node_write_done)</div><div class='ctx'> {</div><div class='del'>-	struct btree *b = container_of(cl, struct btree, io);</div><div class='add'>+	closure_type(b, struct btree, io);</div><div class='ctx'> 	struct btree_write *w = btree_prev_write(b);</div><div class='ctx'> </div><div class='ctx'> 	bch_bbio_free(b-&gt;bio, b-&gt;c);</div><div class='hunk'>@@ -315,12 +315,12 @@ static void __btree_node_write_done(struct closure *cl)</div><div class='ctx'> 	closure_return_with_destructor(cl, btree_node_write_unlock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void btree_node_write_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(btree_node_write_done)</div><div class='ctx'> {</div><div class='del'>-	struct btree *b = container_of(cl, struct btree, io);</div><div class='add'>+	closure_type(b, struct btree, io);</div><div class='ctx'> </div><div class='ctx'> 	bio_free_pages(b-&gt;bio);</div><div class='del'>-	__btree_node_write_done(cl);</div><div class='add'>+	__btree_node_write_done(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void btree_node_write_endio(struct bio *bio)</div><div class='hunk'>@@ -1522,7 +1522,7 @@ out_nocoalesce:</div><div class='ctx'> 	bch_keylist_free(&amp;keylist);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; nodes; i++)</div><div class='del'>-		if (!IS_ERR(new_nodes[i])) {</div><div class='add'>+		if (!IS_ERR_OR_NULL(new_nodes[i])) {</div><div class='ctx'> 			btree_node_free(new_nodes[i]);</div><div class='ctx'> 			rw_unlock(true, new_nodes[i]);</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/md/bcache/journal.c b/drivers/md/bcache/journal.c<br/>index c182c21de2e8..7ff14bd2feb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/journal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/journal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/journal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/journal.c</a></div><div class='hunk'>@@ -723,11 +723,11 @@ static void journal_write_endio(struct bio *bio)</div><div class='ctx'> 	closure_put(&amp;w-&gt;c-&gt;journal.io);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void journal_write(struct closure *cl);</div><div class='add'>+static CLOSURE_CALLBACK(journal_write);</div><div class='ctx'> </div><div class='del'>-static void journal_write_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(journal_write_done)</div><div class='ctx'> {</div><div class='del'>-	struct journal *j = container_of(cl, struct journal, io);</div><div class='add'>+	closure_type(j, struct journal, io);</div><div class='ctx'> 	struct journal_write *w = (j-&gt;cur == j-&gt;w)</div><div class='ctx'> 		? &amp;j-&gt;w[1]</div><div class='ctx'> 		: &amp;j-&gt;w[0];</div><div class='hunk'>@@ -736,19 +736,19 @@ static void journal_write_done(struct closure *cl)</div><div class='ctx'> 	continue_at_nobarrier(cl, journal_write, bch_journal_wq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void journal_write_unlock(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(journal_write_unlock)</div><div class='ctx'> 	__releases(&amp;c-&gt;journal.lock)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, journal.io);</div><div class='add'>+	closure_type(c, struct cache_set, journal.io);</div><div class='ctx'> </div><div class='ctx'> 	c-&gt;journal.io_in_flight = 0;</div><div class='ctx'> 	spin_unlock(&amp;c-&gt;journal.lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void journal_write_unlocked(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(journal_write_unlocked)</div><div class='ctx'> 	__releases(c-&gt;journal.lock)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, journal.io);</div><div class='add'>+	closure_type(c, struct cache_set, journal.io);</div><div class='ctx'> 	struct cache *ca = c-&gt;cache;</div><div class='ctx'> 	struct journal_write *w = c-&gt;journal.cur;</div><div class='ctx'> 	struct bkey *k = &amp;c-&gt;journal.key;</div><div class='hunk'>@@ -823,12 +823,12 @@ static void journal_write_unlocked(struct closure *cl)</div><div class='ctx'> 	continue_at(cl, journal_write_done, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void journal_write(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(journal_write)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, journal.io);</div><div class='add'>+	closure_type(c, struct cache_set, journal.io);</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;c-&gt;journal.lock);</div><div class='del'>-	journal_write_unlocked(cl);</div><div class='add'>+	journal_write_unlocked(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void journal_try_write(struct cache_set *c)</div><div class='head'>diff --git a/drivers/md/bcache/movinggc.c b/drivers/md/bcache/movinggc.c<br/>index 9f32901fdad1..ebd500bdf0b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/movinggc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/movinggc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/movinggc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/movinggc.c</a></div><div class='hunk'>@@ -35,16 +35,16 @@ static bool moving_pred(struct keybuf *buf, struct bkey *k)</div><div class='ctx'> </div><div class='ctx'> /* Moving GC - IO loop */</div><div class='ctx'> </div><div class='del'>-static void moving_io_destructor(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(moving_io_destructor)</div><div class='ctx'> {</div><div class='del'>-	struct moving_io *io = container_of(cl, struct moving_io, cl);</div><div class='add'>+	closure_type(io, struct moving_io, cl);</div><div class='ctx'> </div><div class='ctx'> 	kfree(io);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void write_moving_finish(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(write_moving_finish)</div><div class='ctx'> {</div><div class='del'>-	struct moving_io *io = container_of(cl, struct moving_io, cl);</div><div class='add'>+	closure_type(io, struct moving_io, cl);</div><div class='ctx'> 	struct bio *bio = &amp;io-&gt;bio.bio;</div><div class='ctx'> </div><div class='ctx'> 	bio_free_pages(bio);</div><div class='hunk'>@@ -89,9 +89,9 @@ static void moving_init(struct moving_io *io)</div><div class='ctx'> 	bch_bio_map(bio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void write_moving(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(write_moving)</div><div class='ctx'> {</div><div class='del'>-	struct moving_io *io = container_of(cl, struct moving_io, cl);</div><div class='add'>+	closure_type(io, struct moving_io, cl);</div><div class='ctx'> 	struct data_insert_op *op = &amp;io-&gt;op;</div><div class='ctx'> </div><div class='ctx'> 	if (!op-&gt;status) {</div><div class='hunk'>@@ -113,9 +113,9 @@ static void write_moving(struct closure *cl)</div><div class='ctx'> 	continue_at(cl, write_moving_finish, op-&gt;wq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void read_moving_submit(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(read_moving_submit)</div><div class='ctx'> {</div><div class='del'>-	struct moving_io *io = container_of(cl, struct moving_io, cl);</div><div class='add'>+	closure_type(io, struct moving_io, cl);</div><div class='ctx'> 	struct bio *bio = &amp;io-&gt;bio.bio;</div><div class='ctx'> </div><div class='ctx'> 	bch_submit_bbio(bio, io-&gt;op.c, &amp;io-&gt;w-&gt;key, 0);</div><div class='head'>diff --git a/drivers/md/bcache/request.c b/drivers/md/bcache/request.c<br/>index a9b1f3896249..83d112bd2b1c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/request.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/request.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/request.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/request.c</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> </div><div class='ctx'> struct kmem_cache *bch_search_cache;</div><div class='ctx'> </div><div class='del'>-static void bch_data_insert_start(struct closure *cl);</div><div class='add'>+static CLOSURE_CALLBACK(bch_data_insert_start);</div><div class='ctx'> </div><div class='ctx'> static unsigned int cache_mode(struct cached_dev *dc)</div><div class='ctx'> {</div><div class='hunk'>@@ -55,9 +55,9 @@ static void bio_csum(struct bio *bio, struct bkey *k)</div><div class='ctx'> </div><div class='ctx'> /* Insert data into cache */</div><div class='ctx'> </div><div class='del'>-static void bch_data_insert_keys(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(bch_data_insert_keys)</div><div class='ctx'> {</div><div class='del'>-	struct data_insert_op *op = container_of(cl, struct data_insert_op, cl);</div><div class='add'>+	closure_type(op, struct data_insert_op, cl);</div><div class='ctx'> 	atomic_t *journal_ref = NULL;</div><div class='ctx'> 	struct bkey *replace_key = op-&gt;replace ? &amp;op-&gt;replace_key : NULL;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -136,9 +136,9 @@ out:</div><div class='ctx'> 	continue_at(cl, bch_data_insert_keys, op-&gt;wq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bch_data_insert_error(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(bch_data_insert_error)</div><div class='ctx'> {</div><div class='del'>-	struct data_insert_op *op = container_of(cl, struct data_insert_op, cl);</div><div class='add'>+	closure_type(op, struct data_insert_op, cl);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Our data write just errored, which means we've got a bunch of keys to</div><div class='hunk'>@@ -163,7 +163,7 @@ static void bch_data_insert_error(struct closure *cl)</div><div class='ctx'> </div><div class='ctx'> 	op-&gt;insert_keys.top = dst;</div><div class='ctx'> </div><div class='del'>-	bch_data_insert_keys(cl);</div><div class='add'>+	bch_data_insert_keys(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bch_data_insert_endio(struct bio *bio)</div><div class='hunk'>@@ -184,9 +184,9 @@ static void bch_data_insert_endio(struct bio *bio)</div><div class='ctx'> 	bch_bbio_endio(op-&gt;c, bio, bio-&gt;bi_status, "writing data to cache");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bch_data_insert_start(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(bch_data_insert_start)</div><div class='ctx'> {</div><div class='del'>-	struct data_insert_op *op = container_of(cl, struct data_insert_op, cl);</div><div class='add'>+	closure_type(op, struct data_insert_op, cl);</div><div class='ctx'> 	struct bio *bio = op-&gt;bio, *n;</div><div class='ctx'> </div><div class='ctx'> 	if (op-&gt;bypass)</div><div class='hunk'>@@ -305,16 +305,16 @@ err:</div><div class='ctx'>  * If op-&gt;bypass is true, instead of inserting the data it invalidates the</div><div class='ctx'>  * region of the cache represented by op-&gt;bio and op-&gt;inode.</div><div class='ctx'>  */</div><div class='del'>-void bch_data_insert(struct closure *cl)</div><div class='add'>+CLOSURE_CALLBACK(bch_data_insert)</div><div class='ctx'> {</div><div class='del'>-	struct data_insert_op *op = container_of(cl, struct data_insert_op, cl);</div><div class='add'>+	closure_type(op, struct data_insert_op, cl);</div><div class='ctx'> </div><div class='ctx'> 	trace_bcache_write(op-&gt;c, op-&gt;inode, op-&gt;bio,</div><div class='ctx'> 			   op-&gt;writeback, op-&gt;bypass);</div><div class='ctx'> </div><div class='ctx'> 	bch_keylist_init(&amp;op-&gt;insert_keys);</div><div class='ctx'> 	bio_get(op-&gt;bio);</div><div class='del'>-	bch_data_insert_start(cl);</div><div class='add'>+	bch_data_insert_start(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -575,9 +575,9 @@ static int cache_lookup_fn(struct btree_op *op, struct btree *b, struct bkey *k)</div><div class='ctx'> 	return n == bio ? MAP_DONE : MAP_CONTINUE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cache_lookup(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cache_lookup)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, iop.cl);</div><div class='add'>+	closure_type(s, struct search, iop.cl);</div><div class='ctx'> 	struct bio *bio = &amp;s-&gt;bio.bio;</div><div class='ctx'> 	struct cached_dev *dc;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -698,9 +698,9 @@ static void do_bio_hook(struct search *s,</div><div class='ctx'> 	bio_cnt_set(bio, 3);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void search_free(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(search_free)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> </div><div class='ctx'> 	atomic_dec(&amp;s-&gt;iop.c-&gt;search_inflight);</div><div class='ctx'> </div><div class='hunk'>@@ -749,20 +749,20 @@ static inline struct search *search_alloc(struct bio *bio,</div><div class='ctx'> </div><div class='ctx'> /* Cached devices */</div><div class='ctx'> </div><div class='del'>-static void cached_dev_bio_complete(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_bio_complete)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct cached_dev *dc = container_of(s-&gt;d, struct cached_dev, disk);</div><div class='ctx'> </div><div class='ctx'> 	cached_dev_put(dc);</div><div class='del'>-	search_free(cl);</div><div class='add'>+	search_free(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Process reads */</div><div class='ctx'> </div><div class='del'>-static void cached_dev_read_error_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_read_error_done)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> </div><div class='ctx'> 	if (s-&gt;iop.replace_collision)</div><div class='ctx'> 		bch_mark_cache_miss_collision(s-&gt;iop.c, s-&gt;d);</div><div class='hunk'>@@ -770,12 +770,12 @@ static void cached_dev_read_error_done(struct closure *cl)</div><div class='ctx'> 	if (s-&gt;iop.bio)</div><div class='ctx'> 		bio_free_pages(s-&gt;iop.bio);</div><div class='ctx'> </div><div class='del'>-	cached_dev_bio_complete(cl);</div><div class='add'>+	cached_dev_bio_complete(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_read_error(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_read_error)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct bio *bio = &amp;s-&gt;bio.bio;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -801,9 +801,9 @@ static void cached_dev_read_error(struct closure *cl)</div><div class='ctx'> 	continue_at(cl, cached_dev_read_error_done, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_cache_miss_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_cache_miss_done)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct bcache_device *d = s-&gt;d;</div><div class='ctx'> </div><div class='ctx'> 	if (s-&gt;iop.replace_collision)</div><div class='hunk'>@@ -812,13 +812,13 @@ static void cached_dev_cache_miss_done(struct closure *cl)</div><div class='ctx'> 	if (s-&gt;iop.bio)</div><div class='ctx'> 		bio_free_pages(s-&gt;iop.bio);</div><div class='ctx'> </div><div class='del'>-	cached_dev_bio_complete(cl);</div><div class='add'>+	cached_dev_bio_complete(&amp;cl-&gt;work);</div><div class='ctx'> 	closure_put(&amp;d-&gt;cl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_read_done(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_read_done)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct cached_dev *dc = container_of(s-&gt;d, struct cached_dev, disk);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -858,9 +858,9 @@ static void cached_dev_read_done(struct closure *cl)</div><div class='ctx'> 	continue_at(cl, cached_dev_cache_miss_done, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_read_done_bh(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_read_done_bh)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct cached_dev *dc = container_of(s-&gt;d, struct cached_dev, disk);</div><div class='ctx'> </div><div class='ctx'> 	bch_mark_cache_accounting(s-&gt;iop.c, s-&gt;d,</div><div class='hunk'>@@ -955,13 +955,13 @@ static void cached_dev_read(struct cached_dev *dc, struct search *s)</div><div class='ctx'> </div><div class='ctx'> /* Process writes */</div><div class='ctx'> </div><div class='del'>-static void cached_dev_write_complete(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_write_complete)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct cached_dev *dc = container_of(s-&gt;d, struct cached_dev, disk);</div><div class='ctx'> </div><div class='ctx'> 	up_read_non_owner(&amp;dc-&gt;writeback_lock);</div><div class='del'>-	cached_dev_bio_complete(cl);</div><div class='add'>+	cached_dev_bio_complete(&amp;cl-&gt;work);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void cached_dev_write(struct cached_dev *dc, struct search *s)</div><div class='hunk'>@@ -1048,9 +1048,9 @@ insert_data:</div><div class='ctx'> 	continue_at(cl, cached_dev_write_complete, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_nodata(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_nodata)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> 	struct bio *bio = &amp;s-&gt;bio.bio;</div><div class='ctx'> </div><div class='ctx'> 	if (s-&gt;iop.flush_journal)</div><div class='hunk'>@@ -1265,9 +1265,9 @@ static int flash_dev_cache_miss(struct btree *b, struct search *s,</div><div class='ctx'> 	return MAP_CONTINUE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void flash_dev_nodata(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(flash_dev_nodata)</div><div class='ctx'> {</div><div class='del'>-	struct search *s = container_of(cl, struct search, cl);</div><div class='add'>+	closure_type(s, struct search, cl);</div><div class='ctx'> </div><div class='ctx'> 	if (s-&gt;iop.flush_journal)</div><div class='ctx'> 		bch_journal_meta(s-&gt;iop.c, cl);</div><div class='head'>diff --git a/drivers/md/bcache/request.h b/drivers/md/bcache/request.h<br/>index 38ab4856eaab..46bbef00aebb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/request.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/request.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/request.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/request.h</a></div><div class='hunk'>@@ -34,7 +34,7 @@ struct data_insert_op {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> unsigned int bch_get_congested(const struct cache_set *c);</div><div class='del'>-void bch_data_insert(struct closure *cl);</div><div class='add'>+CLOSURE_CALLBACK(bch_data_insert);</div><div class='ctx'> </div><div class='ctx'> void bch_cached_dev_request_init(struct cached_dev *dc);</div><div class='ctx'> void cached_dev_submit_bio(struct bio *bio);</div><div class='head'>diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c<br/>index bfe1685dbae5..dc3f50f69714 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/super.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/super.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/super.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/super.c</a></div><div class='hunk'>@@ -327,9 +327,9 @@ static void __write_super(struct cache_sb *sb, struct cache_sb_disk *out,</div><div class='ctx'> 	submit_bio(bio);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bch_write_bdev_super_unlock(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(bch_write_bdev_super_unlock)</div><div class='ctx'> {</div><div class='del'>-	struct cached_dev *dc = container_of(cl, struct cached_dev, sb_write);</div><div class='add'>+	closure_type(dc, struct cached_dev, sb_write);</div><div class='ctx'> </div><div class='ctx'> 	up(&amp;dc-&gt;sb_write_mutex);</div><div class='ctx'> }</div><div class='hunk'>@@ -363,9 +363,9 @@ static void write_super_endio(struct bio *bio)</div><div class='ctx'> 	closure_put(&amp;ca-&gt;set-&gt;sb_write);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bcache_write_super_unlock(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(bcache_write_super_unlock)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, sb_write);</div><div class='add'>+	closure_type(c, struct cache_set, sb_write);</div><div class='ctx'> </div><div class='ctx'> 	up(&amp;c-&gt;sb_write_mutex);</div><div class='ctx'> }</div><div class='hunk'>@@ -407,9 +407,9 @@ static void uuid_endio(struct bio *bio)</div><div class='ctx'> 	closure_put(cl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void uuid_io_unlock(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(uuid_io_unlock)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, uuid_write);</div><div class='add'>+	closure_type(c, struct cache_set, uuid_write);</div><div class='ctx'> </div><div class='ctx'> 	up(&amp;c-&gt;uuid_write_mutex);</div><div class='ctx'> }</div><div class='hunk'>@@ -954,7 +954,6 @@ static int bcache_device_init(struct bcache_device *d, unsigned int block_size,</div><div class='ctx'> 	q-&gt;limits.max_segment_size	= UINT_MAX;</div><div class='ctx'> 	q-&gt;limits.max_segments		= BIO_MAX_VECS;</div><div class='ctx'> 	blk_queue_max_discard_sectors(q, UINT_MAX);</div><div class='del'>-	q-&gt;limits.discard_granularity	= 512;</div><div class='ctx'> 	q-&gt;limits.io_min		= block_size;</div><div class='ctx'> 	q-&gt;limits.logical_block_size	= block_size;</div><div class='ctx'> 	q-&gt;limits.physical_block_size	= block_size;</div><div class='hunk'>@@ -1344,9 +1343,9 @@ void bch_cached_dev_release(struct kobject *kobj)</div><div class='ctx'> 	module_put(THIS_MODULE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_free(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_free)</div><div class='ctx'> {</div><div class='del'>-	struct cached_dev *dc = container_of(cl, struct cached_dev, disk.cl);</div><div class='add'>+	closure_type(dc, struct cached_dev, disk.cl);</div><div class='ctx'> </div><div class='ctx'> 	if (test_and_clear_bit(BCACHE_DEV_WB_RUNNING, &amp;dc-&gt;disk.flags))</div><div class='ctx'> 		cancel_writeback_rate_update_dwork(dc);</div><div class='hunk'>@@ -1378,9 +1377,9 @@ static void cached_dev_free(struct closure *cl)</div><div class='ctx'> 	kobject_put(&amp;dc-&gt;disk.kobj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cached_dev_flush(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cached_dev_flush)</div><div class='ctx'> {</div><div class='del'>-	struct cached_dev *dc = container_of(cl, struct cached_dev, disk.cl);</div><div class='add'>+	closure_type(dc, struct cached_dev, disk.cl);</div><div class='ctx'> 	struct bcache_device *d = &amp;dc-&gt;disk;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;bch_register_lock);</div><div class='hunk'>@@ -1499,9 +1498,9 @@ void bch_flash_dev_release(struct kobject *kobj)</div><div class='ctx'> 	kfree(d);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void flash_dev_free(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(flash_dev_free)</div><div class='ctx'> {</div><div class='del'>-	struct bcache_device *d = container_of(cl, struct bcache_device, cl);</div><div class='add'>+	closure_type(d, struct bcache_device, cl);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;bch_register_lock);</div><div class='ctx'> 	atomic_long_sub(bcache_dev_sectors_dirty(d),</div><div class='hunk'>@@ -1512,9 +1511,9 @@ static void flash_dev_free(struct closure *cl)</div><div class='ctx'> 	kobject_put(&amp;d-&gt;kobj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void flash_dev_flush(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(flash_dev_flush)</div><div class='ctx'> {</div><div class='del'>-	struct bcache_device *d = container_of(cl, struct bcache_device, cl);</div><div class='add'>+	closure_type(d, struct bcache_device, cl);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;bch_register_lock);</div><div class='ctx'> 	bcache_device_unlink(d);</div><div class='hunk'>@@ -1670,9 +1669,9 @@ void bch_cache_set_release(struct kobject *kobj)</div><div class='ctx'> 	module_put(THIS_MODULE);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cache_set_free(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cache_set_free)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, cl);</div><div class='add'>+	closure_type(c, struct cache_set, cl);</div><div class='ctx'> 	struct cache *ca;</div><div class='ctx'> </div><div class='ctx'> 	debugfs_remove(c-&gt;debug);</div><div class='hunk'>@@ -1711,9 +1710,9 @@ static void cache_set_free(struct closure *cl)</div><div class='ctx'> 	kobject_put(&amp;c-&gt;kobj);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void cache_set_flush(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(cache_set_flush)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, caching);</div><div class='add'>+	closure_type(c, struct cache_set, caching);</div><div class='ctx'> 	struct cache *ca = c-&gt;cache;</div><div class='ctx'> 	struct btree *b;</div><div class='ctx'> </div><div class='hunk'>@@ -1808,9 +1807,9 @@ static void conditional_stop_bcache_device(struct cache_set *c,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void __cache_set_unregister(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(__cache_set_unregister)</div><div class='ctx'> {</div><div class='del'>-	struct cache_set *c = container_of(cl, struct cache_set, caching);</div><div class='add'>+	closure_type(c, struct cache_set, caching);</div><div class='ctx'> 	struct cached_dev *dc;</div><div class='ctx'> 	struct bcache_device *d;</div><div class='ctx'> 	size_t i;</div><div class='head'>diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c<br/>index 3accfdaee6b1..8827a6f130ad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/bcache/writeback.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/bcache/writeback.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/bcache/writeback.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/bcache/writeback.c</a></div><div class='hunk'>@@ -341,16 +341,16 @@ static void dirty_init(struct keybuf_key *w)</div><div class='ctx'> 	bch_bio_map(bio, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void dirty_io_destructor(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(dirty_io_destructor)</div><div class='ctx'> {</div><div class='del'>-	struct dirty_io *io = container_of(cl, struct dirty_io, cl);</div><div class='add'>+	closure_type(io, struct dirty_io, cl);</div><div class='ctx'> </div><div class='ctx'> 	kfree(io);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void write_dirty_finish(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(write_dirty_finish)</div><div class='ctx'> {</div><div class='del'>-	struct dirty_io *io = container_of(cl, struct dirty_io, cl);</div><div class='add'>+	closure_type(io, struct dirty_io, cl);</div><div class='ctx'> 	struct keybuf_key *w = io-&gt;bio.bi_private;</div><div class='ctx'> 	struct cached_dev *dc = io-&gt;dc;</div><div class='ctx'> </div><div class='hunk'>@@ -400,9 +400,9 @@ static void dirty_endio(struct bio *bio)</div><div class='ctx'> 	closure_put(&amp;io-&gt;cl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void write_dirty(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(write_dirty)</div><div class='ctx'> {</div><div class='del'>-	struct dirty_io *io = container_of(cl, struct dirty_io, cl);</div><div class='add'>+	closure_type(io, struct dirty_io, cl);</div><div class='ctx'> 	struct keybuf_key *w = io-&gt;bio.bi_private;</div><div class='ctx'> 	struct cached_dev *dc = io-&gt;dc;</div><div class='ctx'> </div><div class='hunk'>@@ -462,9 +462,9 @@ static void read_dirty_endio(struct bio *bio)</div><div class='ctx'> 	dirty_endio(bio);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void read_dirty_submit(struct closure *cl)</div><div class='add'>+static CLOSURE_CALLBACK(read_dirty_submit)</div><div class='ctx'> {</div><div class='del'>-	struct dirty_io *io = container_of(cl, struct dirty_io, cl);</div><div class='add'>+	closure_type(io, struct dirty_io, cl);</div><div class='ctx'> </div><div class='ctx'> 	closure_bio_submit(io-&gt;dc-&gt;disk.c, &amp;io-&gt;bio, cl);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c<br/>index f03d7dba270c..13c65b7e1ed6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-bufio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-bufio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-bufio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-bufio.c</a></div><div class='hunk'>@@ -1170,7 +1170,7 @@ static void __cache_size_refresh(void)</div><div class='ctx'>  * If the allocation may fail we use __get_free_pages. Memory fragmentation</div><div class='ctx'>  * won't have a fatal effect here, but it just causes flushes of some other</div><div class='ctx'>  * buffers and more I/O will be performed. Don't use __get_free_pages if it</div><div class='del'>- * always fails (i.e. order &gt; MAX_ORDER).</div><div class='add'>+ * always fails (i.e. order &gt; MAX_PAGE_ORDER).</div><div class='ctx'>  *</div><div class='ctx'>  * If the allocation shouldn't fail we use __vmalloc. This is only for the</div><div class='ctx'>  * initial reserve allocation, so there's no risk of wasting all vmalloc</div><div class='head'>diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c<br/>index 2ae8560b6a14..855b482cbff1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-crypt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-crypt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-crypt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-crypt.c</a></div><div class='hunk'>@@ -1673,7 +1673,7 @@ static struct bio *crypt_alloc_buffer(struct dm_crypt_io *io, unsigned int size)</div><div class='ctx'> 	unsigned int nr_iovecs = (size + PAGE_SIZE - 1) &gt;&gt; PAGE_SHIFT;</div><div class='ctx'> 	gfp_t gfp_mask = GFP_NOWAIT | __GFP_HIGHMEM;</div><div class='ctx'> 	unsigned int remaining_size;</div><div class='del'>-	unsigned int order = MAX_ORDER;</div><div class='add'>+	unsigned int order = MAX_PAGE_ORDER;</div><div class='ctx'> </div><div class='ctx'> retry:</div><div class='ctx'> 	if (unlikely(gfp_mask &amp; __GFP_DIRECT_RECLAIM))</div><div class='head'>diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c<br/>index 120153e44ae0..7916ed9f10e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-flakey.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-flakey.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-flakey.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-flakey.c</a></div><div class='hunk'>@@ -434,7 +434,7 @@ static struct bio *clone_bio(struct dm_target *ti, struct flakey_c *fc, struct b</div><div class='ctx'> </div><div class='ctx'> 	remaining_size = size;</div><div class='ctx'> </div><div class='del'>-	order = MAX_ORDER - 1;</div><div class='add'>+	order = MAX_PAGE_ORDER;</div><div class='ctx'> 	while (remaining_size) {</div><div class='ctx'> 		struct page *pages;</div><div class='ctx'> 		unsigned size_to_add, to_copy;</div><div class='head'>diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c<br/>index e85c688fd91e..c5f03aab4552 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-integrity.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-integrity.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-integrity.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-integrity.c</a></div><div class='hunk'>@@ -1755,11 +1755,12 @@ static void integrity_metadata(struct work_struct *w)</div><div class='ctx'> 		sectors_to_process = dio-&gt;range.n_sectors;</div><div class='ctx'> </div><div class='ctx'> 		__bio_for_each_segment(bv, bio, iter, dio-&gt;bio_details.bi_iter) {</div><div class='add'>+			struct bio_vec bv_copy = bv;</div><div class='ctx'> 			unsigned int pos;</div><div class='ctx'> 			char *mem, *checksums_ptr;</div><div class='ctx'> </div><div class='ctx'> again:</div><div class='del'>-			mem = bvec_kmap_local(&amp;bv);</div><div class='add'>+			mem = bvec_kmap_local(&amp;bv_copy);</div><div class='ctx'> 			pos = 0;</div><div class='ctx'> 			checksums_ptr = checksums;</div><div class='ctx'> 			do {</div><div class='hunk'>@@ -1768,7 +1769,7 @@ again:</div><div class='ctx'> 				sectors_to_process -= ic-&gt;sectors_per_block;</div><div class='ctx'> 				pos += ic-&gt;sectors_per_block &lt;&lt; SECTOR_SHIFT;</div><div class='ctx'> 				sector += ic-&gt;sectors_per_block;</div><div class='del'>-			} while (pos &lt; bv.bv_len &amp;&amp; sectors_to_process &amp;&amp; checksums != checksums_onstack);</div><div class='add'>+			} while (pos &lt; bv_copy.bv_len &amp;&amp; sectors_to_process &amp;&amp; checksums != checksums_onstack);</div><div class='ctx'> 			kunmap_local(mem);</div><div class='ctx'> </div><div class='ctx'> 			r = dm_integrity_rw_tag(ic, checksums, &amp;dio-&gt;metadata_block, &amp;dio-&gt;metadata_offset,</div><div class='hunk'>@@ -1793,9 +1794,9 @@ again:</div><div class='ctx'> 			if (!sectors_to_process)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='del'>-			if (unlikely(pos &lt; bv.bv_len)) {</div><div class='del'>-				bv.bv_offset += pos;</div><div class='del'>-				bv.bv_len -= pos;</div><div class='add'>+			if (unlikely(pos &lt; bv_copy.bv_len)) {</div><div class='add'>+				bv_copy.bv_offset += pos;</div><div class='add'>+				bv_copy.bv_len -= pos;</div><div class='ctx'> 				goto again;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/md/dm-kcopyd.c b/drivers/md/dm-kcopyd.c<br/>index d01807c50f20..36bcfdccae04 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-kcopyd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-kcopyd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-kcopyd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-kcopyd.c</a></div><div class='hunk'>@@ -807,7 +807,7 @@ void dm_kcopyd_copy(struct dm_kcopyd_client *kc, struct dm_io_region *from,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!(job-&gt;flags &amp; BIT(DM_KCOPYD_WRITE_SEQ))) {</div><div class='ctx'> 		for (i = 0; i &lt; job-&gt;num_dests; i++) {</div><div class='del'>-			if (bdev_zoned_model(dests[i].bdev) == BLK_ZONED_HM) {</div><div class='add'>+			if (bdev_is_zoned(dests[i].bdev)) {</div><div class='ctx'> 				job-&gt;flags |= BIT(DM_KCOPYD_WRITE_SEQ);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c<br/>index 91ebdcc6e9a8..eb009d6bb03a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-raid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-raid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-raid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-raid.c</a></div><div class='hunk'>@@ -3317,6 +3317,9 @@ static void raid_dtr(struct dm_target *ti)</div><div class='ctx'> 	mddev_lock_nointr(&amp;rs-&gt;md);</div><div class='ctx'> 	md_stop(&amp;rs-&gt;md);</div><div class='ctx'> 	mddev_unlock(&amp;rs-&gt;md);</div><div class='add'>+</div><div class='add'>+	if (work_pending(&amp;rs-&gt;md.event_work))</div><div class='add'>+		flush_work(&amp;rs-&gt;md.event_work);</div><div class='ctx'> 	raid_set_free(rs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c<br/>index 198d38b53322..260b5b8f2b0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-table.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-table.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-table.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-table.c</a></div><div class='hunk'>@@ -1579,21 +1579,18 @@ bool dm_table_has_no_data_devices(struct dm_table *t)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int device_not_zoned_model(struct dm_target *ti, struct dm_dev *dev,</div><div class='del'>-				  sector_t start, sector_t len, void *data)</div><div class='add'>+static int device_not_zoned(struct dm_target *ti, struct dm_dev *dev,</div><div class='add'>+			    sector_t start, sector_t len, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct request_queue *q = bdev_get_queue(dev-&gt;bdev);</div><div class='del'>-	enum blk_zoned_model *zoned_model = data;</div><div class='add'>+	bool *zoned = data;</div><div class='ctx'> </div><div class='del'>-	return blk_queue_zoned_model(q) != *zoned_model;</div><div class='add'>+	return bdev_is_zoned(dev-&gt;bdev) != *zoned;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int device_is_zoned_model(struct dm_target *ti, struct dm_dev *dev,</div><div class='ctx'> 				 sector_t start, sector_t len, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct request_queue *q = bdev_get_queue(dev-&gt;bdev);</div><div class='del'>-</div><div class='del'>-	return blk_queue_zoned_model(q) != BLK_ZONED_NONE;</div><div class='add'>+	return bdev_is_zoned(dev-&gt;bdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1603,8 +1600,7 @@ static int device_is_zoned_model(struct dm_target *ti, struct dm_dev *dev,</div><div class='ctx'>  * has the DM_TARGET_MIXED_ZONED_MODEL feature set, the devices can have any</div><div class='ctx'>  * zoned model with all zoned devices having the same zone size.</div><div class='ctx'>  */</div><div class='del'>-static bool dm_table_supports_zoned_model(struct dm_table *t,</div><div class='del'>-					  enum blk_zoned_model zoned_model)</div><div class='add'>+static bool dm_table_supports_zoned(struct dm_table *t, bool zoned)</div><div class='ctx'> {</div><div class='ctx'> 	for (unsigned int i = 0; i &lt; t-&gt;num_targets; i++) {</div><div class='ctx'> 		struct dm_target *ti = dm_table_get_target(t, i);</div><div class='hunk'>@@ -1623,11 +1619,11 @@ static bool dm_table_supports_zoned_model(struct dm_table *t,</div><div class='ctx'> </div><div class='ctx'> 		if (dm_target_supports_zoned_hm(ti-&gt;type)) {</div><div class='ctx'> 			if (!ti-&gt;type-&gt;iterate_devices ||</div><div class='del'>-			    ti-&gt;type-&gt;iterate_devices(ti, device_not_zoned_model,</div><div class='del'>-						      &amp;zoned_model))</div><div class='add'>+			    ti-&gt;type-&gt;iterate_devices(ti, device_not_zoned,</div><div class='add'>+						      &amp;zoned))</div><div class='ctx'> 				return false;</div><div class='ctx'> 		} else if (!dm_target_supports_mixed_zoned_model(ti-&gt;type)) {</div><div class='del'>-			if (zoned_model == BLK_ZONED_HM)</div><div class='add'>+			if (zoned)</div><div class='ctx'> 				return false;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1650,14 +1646,13 @@ static int device_not_matches_zone_sectors(struct dm_target *ti, struct dm_dev *</div><div class='ctx'>  * zone sectors, if the destination device is a zoned block device, it shall</div><div class='ctx'>  * have the specified zone_sectors.</div><div class='ctx'>  */</div><div class='del'>-static int validate_hardware_zoned_model(struct dm_table *t,</div><div class='del'>-					 enum blk_zoned_model zoned_model,</div><div class='del'>-					 unsigned int zone_sectors)</div><div class='add'>+static int validate_hardware_zoned(struct dm_table *t, bool zoned,</div><div class='add'>+				   unsigned int zone_sectors)</div><div class='ctx'> {</div><div class='del'>-	if (zoned_model == BLK_ZONED_NONE)</div><div class='add'>+	if (!zoned)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (!dm_table_supports_zoned_model(t, zoned_model)) {</div><div class='add'>+	if (!dm_table_supports_zoned(t, zoned)) {</div><div class='ctx'> 		DMERR("%s: zoned model is not consistent across all devices",</div><div class='ctx'> 		      dm_device_name(t-&gt;md));</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1683,8 +1678,8 @@ int dm_calculate_queue_limits(struct dm_table *t,</div><div class='ctx'> 			      struct queue_limits *limits)</div><div class='ctx'> {</div><div class='ctx'> 	struct queue_limits ti_limits;</div><div class='del'>-	enum blk_zoned_model zoned_model = BLK_ZONED_NONE;</div><div class='ctx'> 	unsigned int zone_sectors = 0;</div><div class='add'>+	bool zoned = false;</div><div class='ctx'> </div><div class='ctx'> 	blk_set_stacking_limits(limits);</div><div class='ctx'> </div><div class='hunk'>@@ -1706,12 +1701,12 @@ int dm_calculate_queue_limits(struct dm_table *t,</div><div class='ctx'> 		ti-&gt;type-&gt;iterate_devices(ti, dm_set_device_limits,</div><div class='ctx'> 					  &amp;ti_limits);</div><div class='ctx'> </div><div class='del'>-		if (zoned_model == BLK_ZONED_NONE &amp;&amp; ti_limits.zoned != BLK_ZONED_NONE) {</div><div class='add'>+		if (!zoned &amp;&amp; ti_limits.zoned) {</div><div class='ctx'> 			/*</div><div class='ctx'> 			 * After stacking all limits, validate all devices</div><div class='ctx'> 			 * in table support this zoned model and zone sectors.</div><div class='ctx'> 			 */</div><div class='del'>-			zoned_model = ti_limits.zoned;</div><div class='add'>+			zoned = ti_limits.zoned;</div><div class='ctx'> 			zone_sectors = ti_limits.chunk_sectors;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1744,18 +1739,18 @@ combine_limits:</div><div class='ctx'> 	 * Verify that the zoned model and zone sectors, as determined before</div><div class='ctx'> 	 * any .io_hints override, are the same across all devices in the table.</div><div class='ctx'> 	 * - this is especially relevant if .io_hints is emulating a disk-managed</div><div class='del'>-	 *   zoned model (aka BLK_ZONED_NONE) on host-managed zoned block devices.</div><div class='add'>+	 *   zoned model on host-managed zoned block devices.</div><div class='ctx'> 	 * BUT...</div><div class='ctx'> 	 */</div><div class='del'>-	if (limits-&gt;zoned != BLK_ZONED_NONE) {</div><div class='add'>+	if (limits-&gt;zoned) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * ...IF the above limits stacking determined a zoned model</div><div class='ctx'> 		 * validate that all of the table's devices conform to it.</div><div class='ctx'> 		 */</div><div class='del'>-		zoned_model = limits-&gt;zoned;</div><div class='add'>+		zoned = limits-&gt;zoned;</div><div class='ctx'> 		zone_sectors = limits-&gt;chunk_sectors;</div><div class='ctx'> 	}</div><div class='del'>-	if (validate_hardware_zoned_model(t, zoned_model, zone_sectors))</div><div class='add'>+	if (validate_hardware_zoned(t, zoned, zone_sectors))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return validate_hardware_logical_block_alignment(t, limits);</div><div class='head'>diff --git a/drivers/md/dm-verity-fec.c b/drivers/md/dm-verity-fec.c<br/>index 2099c755119e..b475200d8586 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-verity-fec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-verity-fec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-verity-fec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity-fec.c</a></div><div class='hunk'>@@ -24,7 +24,8 @@ bool verity_fec_is_enabled(struct dm_verity *v)</div><div class='ctx'>  */</div><div class='ctx'> static inline struct dm_verity_fec_io *fec_io(struct dm_verity_io *io)</div><div class='ctx'> {</div><div class='del'>-	return (struct dm_verity_fec_io *) verity_io_digest_end(io-&gt;v, io);</div><div class='add'>+	return (struct dm_verity_fec_io *)</div><div class='add'>+		((char *)io + io-&gt;v-&gt;ti-&gt;per_io_data_size - sizeof(struct dm_verity_fec_io));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c<br/>index e115fcfe723c..14e58ae70521 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-verity-target.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-verity-target.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-verity-target.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity-target.c</a></div><div class='hunk'>@@ -642,7 +642,6 @@ static void verity_work(struct work_struct *w)</div><div class='ctx'> </div><div class='ctx'> 	io-&gt;in_tasklet = false;</div><div class='ctx'> </div><div class='del'>-	verity_fec_init_io(io);</div><div class='ctx'> 	verity_finish_io(io, errno_to_blk_status(verity_verify_io(io)));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -668,7 +667,9 @@ static void verity_end_io(struct bio *bio)</div><div class='ctx'> 	struct dm_verity_io *io = bio-&gt;bi_private;</div><div class='ctx'> </div><div class='ctx'> 	if (bio-&gt;bi_status &amp;&amp;</div><div class='del'>-	    (!verity_fec_is_enabled(io-&gt;v) || verity_is_system_shutting_down())) {</div><div class='add'>+	    (!verity_fec_is_enabled(io-&gt;v) ||</div><div class='add'>+	     verity_is_system_shutting_down() ||</div><div class='add'>+	     (bio-&gt;bi_opf &amp; REQ_RAHEAD))) {</div><div class='ctx'> 		verity_finish_io(io, bio-&gt;bi_status);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -792,6 +793,8 @@ static int verity_map(struct dm_target *ti, struct bio *bio)</div><div class='ctx'> 	bio-&gt;bi_private = io;</div><div class='ctx'> 	io-&gt;iter = bio-&gt;bi_iter;</div><div class='ctx'> </div><div class='add'>+	verity_fec_init_io(io);</div><div class='add'>+</div><div class='ctx'> 	verity_submit_prefetch(v, io);</div><div class='ctx'> </div><div class='ctx'> 	submit_bio_noacct(bio);</div><div class='head'>diff --git a/drivers/md/dm-verity.h b/drivers/md/dm-verity.h<br/>index f96f4e281ee4..f9d522c870e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-verity.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-verity.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-verity.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-verity.h</a></div><div class='hunk'>@@ -115,12 +115,6 @@ static inline u8 *verity_io_want_digest(struct dm_verity *v,</div><div class='ctx'> 	return (u8 *)(io + 1) + v-&gt;ahash_reqsize + v-&gt;digest_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline u8 *verity_io_digest_end(struct dm_verity *v,</div><div class='del'>-				       struct dm_verity_io *io)</div><div class='del'>-{</div><div class='del'>-	return verity_io_want_digest(v, io) + v-&gt;digest_size;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> extern int verity_for_bv_block(struct dm_verity *v, struct dm_verity_io *io,</div><div class='ctx'> 			       struct bvec_iter *iter,</div><div class='ctx'> 			       int (*process)(struct dm_verity *v,</div><div class='head'>diff --git a/drivers/md/dm-zoned-metadata.c b/drivers/md/dm-zoned-metadata.c<br/>index 60a4dc01ea18..fdfe30f7b697 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-zoned-metadata.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-zoned-metadata.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-zoned-metadata.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-zoned-metadata.c</a></div><div class='hunk'>@@ -2836,12 +2836,11 @@ static void dmz_print_dev(struct dmz_metadata *zmd, int num)</div><div class='ctx'> {</div><div class='ctx'> 	struct dmz_dev *dev = &amp;zmd-&gt;dev[num];</div><div class='ctx'> </div><div class='del'>-	if (bdev_zoned_model(dev-&gt;bdev) == BLK_ZONED_NONE)</div><div class='add'>+	if (!bdev_is_zoned(dev-&gt;bdev))</div><div class='ctx'> 		dmz_dev_info(dev, "Regular block device");</div><div class='ctx'> 	else</div><div class='del'>-		dmz_dev_info(dev, "Host-%s zoned block device",</div><div class='del'>-			     bdev_zoned_model(dev-&gt;bdev) == BLK_ZONED_HA ?</div><div class='del'>-			     "aware" : "managed");</div><div class='add'>+		dmz_dev_info(dev, "Host-managed zoned block device");</div><div class='add'>+</div><div class='ctx'> 	if (zmd-&gt;sb_version &gt; 1) {</div><div class='ctx'> 		sector_t sector_offset =</div><div class='ctx'> 			dev-&gt;zone_offset &lt;&lt; zmd-&gt;zone_nr_sectors_shift;</div><div class='head'>diff --git a/drivers/md/dm-zoned-target.c b/drivers/md/dm-zoned-target.c<br/>index b487f7acc860..621794a9edd6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm-zoned-target.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm-zoned-target.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm-zoned-target.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm-zoned-target.c</a></div><div class='hunk'>@@ -702,7 +702,7 @@ static int dmz_get_zoned_device(struct dm_target *ti, char *path,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	bdev = ddev-&gt;bdev;</div><div class='del'>-	if (bdev_zoned_model(bdev) == BLK_ZONED_NONE) {</div><div class='add'>+	if (!bdev_is_zoned(bdev)) {</div><div class='ctx'> 		if (nr_devs == 1) {</div><div class='ctx'> 			ti-&gt;error = "Invalid regular device";</div><div class='ctx'> 			goto err;</div><div class='hunk'>@@ -1010,7 +1010,7 @@ static void dmz_io_hints(struct dm_target *ti, struct queue_limits *limits)</div><div class='ctx'> 	limits-&gt;max_sectors = chunk_sectors;</div><div class='ctx'> </div><div class='ctx'> 	/* We are exposing a drive-managed zoned block device */</div><div class='del'>-	limits-&gt;zoned = BLK_ZONED_NONE;</div><div class='add'>+	limits-&gt;zoned = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/md/dm.c b/drivers/md/dm.c<br/>index 23c32cd1f1d8..8dcabf84d866 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/dm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/dm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/dm.c</a></div><div class='hunk'>@@ -2675,7 +2675,7 @@ static int lock_fs(struct mapped_device *md)</div><div class='ctx'> </div><div class='ctx'> 	WARN_ON(test_bit(DMF_FROZEN, &amp;md-&gt;flags));</div><div class='ctx'> </div><div class='del'>-	r = freeze_bdev(md-&gt;disk-&gt;part0);</div><div class='add'>+	r = bdev_freeze(md-&gt;disk-&gt;part0);</div><div class='ctx'> 	if (!r)</div><div class='ctx'> 		set_bit(DMF_FROZEN, &amp;md-&gt;flags);</div><div class='ctx'> 	return r;</div><div class='hunk'>@@ -2685,7 +2685,7 @@ static void unlock_fs(struct mapped_device *md)</div><div class='ctx'> {</div><div class='ctx'> 	if (!test_bit(DMF_FROZEN, &amp;md-&gt;flags))</div><div class='ctx'> 		return;</div><div class='del'>-	thaw_bdev(md-&gt;disk-&gt;part0);</div><div class='add'>+	bdev_thaw(md-&gt;disk-&gt;part0);</div><div class='ctx'> 	clear_bit(DMF_FROZEN, &amp;md-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/md/md-autodetect.c b/drivers/md/md-autodetect.c<br/>index 4b80165afd23..b2a00f213c2c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md-autodetect.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md-autodetect.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/md-autodetect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md-autodetect.c</a></div><div class='hunk'>@@ -49,7 +49,6 @@ static int md_setup_ents __initdata;</div><div class='ctx'>  *             instead of just one.  -- KTK</div><div class='ctx'>  * 18May2000: Added support for persistent-superblock arrays:</div><div class='ctx'>  *             md=n,0,factor,fault,device-list   uses RAID0 for device n</div><div class='del'>- *             md=n,-1,factor,fault,device-list  uses LINEAR for device n</div><div class='ctx'>  *             md=n,device-list      reads a RAID superblock from the devices</div><div class='ctx'>  *             elements in device-list are read by name_to_kdev_t so can be</div><div class='ctx'>  *             a hex number or something like /dev/hda1 /dev/sdb</div><div class='hunk'>@@ -88,7 +87,7 @@ static int __init md_setup(char *str)</div><div class='ctx'> 		md_setup_ents++;</div><div class='ctx'> 	switch (get_option(&amp;str, &amp;level)) {	/* RAID level */</div><div class='ctx'> 	case 2: /* could be 0 or -1.. */</div><div class='del'>-		if (level == 0 || level == LEVEL_LINEAR) {</div><div class='add'>+		if (level == 0) {</div><div class='ctx'> 			if (get_option(&amp;str, &amp;factor) != 2 ||	/* Chunk Size */</div><div class='ctx'> 					get_option(&amp;str, &amp;fault) != 2) {</div><div class='ctx'> 				printk(KERN_WARNING "md: Too few arguments supplied to md=.\n");</div><div class='hunk'>@@ -96,10 +95,7 @@ static int __init md_setup(char *str)</div><div class='ctx'> 			}</div><div class='ctx'> 			md_setup_args[ent].level = level;</div><div class='ctx'> 			md_setup_args[ent].chunk = 1 &lt;&lt; (factor+12);</div><div class='del'>-			if (level ==  LEVEL_LINEAR)</div><div class='del'>-				pername = "linear";</div><div class='del'>-			else</div><div class='del'>-				pername = "raid0";</div><div class='add'>+			pername = "raid0";</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		fallthrough;</div><div class='head'>diff --git a/drivers/md/md-faulty.c b/drivers/md/md-faulty.c<br/>deleted file mode 100644<br/>index a039e8e20f55..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md-faulty.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md-faulty.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,365 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='del'>-/*</div><div class='del'>- * faulty.c : Multiple Devices driver for Linux</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 2004 Neil Brown</div><div class='del'>- *</div><div class='del'>- * fautly-device-simulator personality for md</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * The "faulty" personality causes some requests to fail.</div><div class='del'>- *</div><div class='del'>- * Possible failure modes are:</div><div class='del'>- *   reads fail "randomly" but succeed on retry</div><div class='del'>- *   writes fail "randomly" but succeed on retry</div><div class='del'>- *   reads for some address fail and then persist until a write</div><div class='del'>- *   reads for some address fail and then persist irrespective of write</div><div class='del'>- *   writes for some address fail and persist</div><div class='del'>- *   all writes fail</div><div class='del'>- *</div><div class='del'>- * Different modes can be active at a time, but only</div><div class='del'>- * one can be set at array creation.  Others can be added later.</div><div class='del'>- * A mode can be one-shot or recurrent with the recurrence being</div><div class='del'>- * once in every N requests.</div><div class='del'>- * The bottom 5 bits of the "layout" indicate the mode.  The</div><div class='del'>- * remainder indicate a period, or 0 for one-shot.</div><div class='del'>- *</div><div class='del'>- * There is an implementation limit on the number of concurrently</div><div class='del'>- * persisting-faulty blocks. When a new fault is requested that would</div><div class='del'>- * exceed the limit, it is ignored.</div><div class='del'>- * All current faults can be clear using a layout of "0".</div><div class='del'>- *</div><div class='del'>- * Requests are always sent to the device.  If they are to fail,</div><div class='del'>- * we clone the bio and insert a new b_end_io into the chain.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define	WriteTransient	0</div><div class='del'>-#define	ReadTransient	1</div><div class='del'>-#define	WritePersistent	2</div><div class='del'>-#define	ReadPersistent	3</div><div class='del'>-#define	WriteAll	4 /* doesn't go to device */</div><div class='del'>-#define	ReadFixable	5</div><div class='del'>-#define	Modes	6</div><div class='del'>-</div><div class='del'>-#define	ClearErrors	31</div><div class='del'>-#define	ClearFaults	30</div><div class='del'>-</div><div class='del'>-#define AllPersist	100 /* internal use only */</div><div class='del'>-#define	NoPersist	101</div><div class='del'>-</div><div class='del'>-#define	ModeMask	0x1f</div><div class='del'>-#define	ModeShift	5</div><div class='del'>-</div><div class='del'>-#define MaxFault	50</div><div class='del'>-#include &lt;linux/blkdev.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/raid/md_u.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include "md.h"</div><div class='del'>-#include &lt;linux/seq_file.h&gt;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static void faulty_fail(struct bio *bio)</div><div class='del'>-{</div><div class='del'>-	struct bio *b = bio-&gt;bi_private;</div><div class='del'>-</div><div class='del'>-	b-&gt;bi_iter.bi_size = bio-&gt;bi_iter.bi_size;</div><div class='del'>-	b-&gt;bi_iter.bi_sector = bio-&gt;bi_iter.bi_sector;</div><div class='del'>-</div><div class='del'>-	bio_put(bio);</div><div class='del'>-</div><div class='del'>-	bio_io_error(b);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct faulty_conf {</div><div class='del'>-	int period[Modes];</div><div class='del'>-	atomic_t counters[Modes];</div><div class='del'>-	sector_t faults[MaxFault];</div><div class='del'>-	int	modes[MaxFault];</div><div class='del'>-	int nfaults;</div><div class='del'>-	struct md_rdev *rdev;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int check_mode(struct faulty_conf *conf, int mode)</div><div class='del'>-{</div><div class='del'>-	if (conf-&gt;period[mode] == 0 &amp;&amp;</div><div class='del'>-	    atomic_read(&amp;conf-&gt;counters[mode]) &lt;= 0)</div><div class='del'>-		return 0; /* no failure, no decrement */</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	if (atomic_dec_and_test(&amp;conf-&gt;counters[mode])) {</div><div class='del'>-		if (conf-&gt;period[mode])</div><div class='del'>-			atomic_set(&amp;conf-&gt;counters[mode], conf-&gt;period[mode]);</div><div class='del'>-		return 1;</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int check_sector(struct faulty_conf *conf, sector_t start, sector_t end, int dir)</div><div class='del'>-{</div><div class='del'>-	/* If we find a ReadFixable sector, we fix it ... */</div><div class='del'>-	int i;</div><div class='del'>-	for (i=0; i&lt;conf-&gt;nfaults; i++)</div><div class='del'>-		if (conf-&gt;faults[i] &gt;= start &amp;&amp;</div><div class='del'>-		    conf-&gt;faults[i] &lt; end) {</div><div class='del'>-			/* found it ... */</div><div class='del'>-			switch (conf-&gt;modes[i] * 2 + dir) {</div><div class='del'>-			case WritePersistent*2+WRITE: return 1;</div><div class='del'>-			case ReadPersistent*2+READ: return 1;</div><div class='del'>-			case ReadFixable*2+READ: return 1;</div><div class='del'>-			case ReadFixable*2+WRITE:</div><div class='del'>-				conf-&gt;modes[i] = NoPersist;</div><div class='del'>-				return 0;</div><div class='del'>-			case AllPersist*2+READ:</div><div class='del'>-			case AllPersist*2+WRITE: return 1;</div><div class='del'>-			default:</div><div class='del'>-				return 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void add_sector(struct faulty_conf *conf, sector_t start, int mode)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	int n = conf-&gt;nfaults;</div><div class='del'>-	for (i=0; i&lt;conf-&gt;nfaults; i++)</div><div class='del'>-		if (conf-&gt;faults[i] == start) {</div><div class='del'>-			switch(mode) {</div><div class='del'>-			case NoPersist: conf-&gt;modes[i] = mode; return;</div><div class='del'>-			case WritePersistent:</div><div class='del'>-				if (conf-&gt;modes[i] == ReadPersistent ||</div><div class='del'>-				    conf-&gt;modes[i] == ReadFixable)</div><div class='del'>-					conf-&gt;modes[i] = AllPersist;</div><div class='del'>-				else</div><div class='del'>-					conf-&gt;modes[i] = WritePersistent;</div><div class='del'>-				return;</div><div class='del'>-			case ReadPersistent:</div><div class='del'>-				if (conf-&gt;modes[i] == WritePersistent)</div><div class='del'>-					conf-&gt;modes[i] = AllPersist;</div><div class='del'>-				else</div><div class='del'>-					conf-&gt;modes[i] = ReadPersistent;</div><div class='del'>-				return;</div><div class='del'>-			case ReadFixable:</div><div class='del'>-				if (conf-&gt;modes[i] == WritePersistent ||</div><div class='del'>-				    conf-&gt;modes[i] == ReadPersistent)</div><div class='del'>-					conf-&gt;modes[i] = AllPersist;</div><div class='del'>-				else</div><div class='del'>-					conf-&gt;modes[i] = ReadFixable;</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		} else if (conf-&gt;modes[i] == NoPersist)</div><div class='del'>-			n = i;</div><div class='del'>-</div><div class='del'>-	if (n &gt;= MaxFault)</div><div class='del'>-		return;</div><div class='del'>-	conf-&gt;faults[n] = start;</div><div class='del'>-	conf-&gt;modes[n] = mode;</div><div class='del'>-	if (conf-&gt;nfaults == n)</div><div class='del'>-		conf-&gt;nfaults = n+1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool faulty_make_request(struct mddev *mddev, struct bio *bio)</div><div class='del'>-{</div><div class='del'>-	struct faulty_conf *conf = mddev-&gt;private;</div><div class='del'>-	int failit = 0;</div><div class='del'>-</div><div class='del'>-	if (bio_data_dir(bio) == WRITE) {</div><div class='del'>-		/* write request */</div><div class='del'>-		if (atomic_read(&amp;conf-&gt;counters[WriteAll])) {</div><div class='del'>-			/* special case - don't decrement, don't submit_bio_noacct,</div><div class='del'>-			 * just fail immediately</div><div class='del'>-			 */</div><div class='del'>-			bio_io_error(bio);</div><div class='del'>-			return true;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (check_sector(conf, bio-&gt;bi_iter.bi_sector,</div><div class='del'>-				 bio_end_sector(bio), WRITE))</div><div class='del'>-			failit = 1;</div><div class='del'>-		if (check_mode(conf, WritePersistent)) {</div><div class='del'>-			add_sector(conf, bio-&gt;bi_iter.bi_sector,</div><div class='del'>-				   WritePersistent);</div><div class='del'>-			failit = 1;</div><div class='del'>-		}</div><div class='del'>-		if (check_mode(conf, WriteTransient))</div><div class='del'>-			failit = 1;</div><div class='del'>-	} else {</div><div class='del'>-		/* read request */</div><div class='del'>-		if (check_sector(conf, bio-&gt;bi_iter.bi_sector,</div><div class='del'>-				 bio_end_sector(bio), READ))</div><div class='del'>-			failit = 1;</div><div class='del'>-		if (check_mode(conf, ReadTransient))</div><div class='del'>-			failit = 1;</div><div class='del'>-		if (check_mode(conf, ReadPersistent)) {</div><div class='del'>-			add_sector(conf, bio-&gt;bi_iter.bi_sector,</div><div class='del'>-				   ReadPersistent);</div><div class='del'>-			failit = 1;</div><div class='del'>-		}</div><div class='del'>-		if (check_mode(conf, ReadFixable)) {</div><div class='del'>-			add_sector(conf, bio-&gt;bi_iter.bi_sector,</div><div class='del'>-				   ReadFixable);</div><div class='del'>-			failit = 1;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	md_account_bio(mddev, &amp;bio);</div><div class='del'>-	if (failit) {</div><div class='del'>-		struct bio *b = bio_alloc_clone(conf-&gt;rdev-&gt;bdev, bio, GFP_NOIO,</div><div class='del'>-						&amp;mddev-&gt;bio_set);</div><div class='del'>-</div><div class='del'>-		b-&gt;bi_private = bio;</div><div class='del'>-		b-&gt;bi_end_io = faulty_fail;</div><div class='del'>-		bio = b;</div><div class='del'>-	} else</div><div class='del'>-		bio_set_dev(bio, conf-&gt;rdev-&gt;bdev);</div><div class='del'>-</div><div class='del'>-	submit_bio_noacct(bio);</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void faulty_status(struct seq_file *seq, struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	struct faulty_conf *conf = mddev-&gt;private;</div><div class='del'>-	int n;</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[WriteTransient])) != 0)</div><div class='del'>-		seq_printf(seq, " WriteTransient=%d(%d)",</div><div class='del'>-			   n, conf-&gt;period[WriteTransient]);</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[ReadTransient])) != 0)</div><div class='del'>-		seq_printf(seq, " ReadTransient=%d(%d)",</div><div class='del'>-			   n, conf-&gt;period[ReadTransient]);</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[WritePersistent])) != 0)</div><div class='del'>-		seq_printf(seq, " WritePersistent=%d(%d)",</div><div class='del'>-			   n, conf-&gt;period[WritePersistent]);</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[ReadPersistent])) != 0)</div><div class='del'>-		seq_printf(seq, " ReadPersistent=%d(%d)",</div><div class='del'>-			   n, conf-&gt;period[ReadPersistent]);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[ReadFixable])) != 0)</div><div class='del'>-		seq_printf(seq, " ReadFixable=%d(%d)",</div><div class='del'>-			   n, conf-&gt;period[ReadFixable]);</div><div class='del'>-</div><div class='del'>-	if ((n=atomic_read(&amp;conf-&gt;counters[WriteAll])) != 0)</div><div class='del'>-		seq_printf(seq, " WriteAll");</div><div class='del'>-</div><div class='del'>-	seq_printf(seq, " nfaults=%d", conf-&gt;nfaults);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static int faulty_reshape(struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	int mode = mddev-&gt;new_layout &amp; ModeMask;</div><div class='del'>-	int count = mddev-&gt;new_layout &gt;&gt; ModeShift;</div><div class='del'>-	struct faulty_conf *conf = mddev-&gt;private;</div><div class='del'>-</div><div class='del'>-	if (mddev-&gt;new_layout &lt; 0)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* new layout */</div><div class='del'>-	if (mode == ClearFaults)</div><div class='del'>-		conf-&gt;nfaults = 0;</div><div class='del'>-	else if (mode == ClearErrors) {</div><div class='del'>-		int i;</div><div class='del'>-		for (i=0 ; i &lt; Modes ; i++) {</div><div class='del'>-			conf-&gt;period[i] = 0;</div><div class='del'>-			atomic_set(&amp;conf-&gt;counters[i], 0);</div><div class='del'>-		}</div><div class='del'>-	} else if (mode &lt; Modes) {</div><div class='del'>-		conf-&gt;period[mode] = count;</div><div class='del'>-		if (!count) count++;</div><div class='del'>-		atomic_set(&amp;conf-&gt;counters[mode], count);</div><div class='del'>-	} else</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	mddev-&gt;new_layout = -1;</div><div class='del'>-	mddev-&gt;layout = -1; /* makes sure further changes come through */</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static sector_t faulty_size(struct mddev *mddev, sector_t sectors, int raid_disks)</div><div class='del'>-{</div><div class='del'>-	WARN_ONCE(raid_disks,</div><div class='del'>-		  "%s does not support generic reshape\n", __func__);</div><div class='del'>-</div><div class='del'>-	if (sectors == 0)</div><div class='del'>-		return mddev-&gt;dev_sectors;</div><div class='del'>-</div><div class='del'>-	return sectors;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int faulty_run(struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	struct md_rdev *rdev;</div><div class='del'>-	int i;</div><div class='del'>-	struct faulty_conf *conf;</div><div class='del'>-</div><div class='del'>-	if (md_check_no_bitmap(mddev))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	conf = kmalloc(sizeof(*conf), GFP_KERNEL);</div><div class='del'>-	if (!conf)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	for (i=0; i&lt;Modes; i++) {</div><div class='del'>-		atomic_set(&amp;conf-&gt;counters[i], 0);</div><div class='del'>-		conf-&gt;period[i] = 0;</div><div class='del'>-	}</div><div class='del'>-	conf-&gt;nfaults = 0;</div><div class='del'>-</div><div class='del'>-	rdev_for_each(rdev, mddev) {</div><div class='del'>-		conf-&gt;rdev = rdev;</div><div class='del'>-		disk_stack_limits(mddev-&gt;gendisk, rdev-&gt;bdev,</div><div class='del'>-				  rdev-&gt;data_offset &lt;&lt; 9);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	md_set_array_sectors(mddev, faulty_size(mddev, 0, 0));</div><div class='del'>-	mddev-&gt;private = conf;</div><div class='del'>-</div><div class='del'>-	faulty_reshape(mddev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void faulty_free(struct mddev *mddev, void *priv)</div><div class='del'>-{</div><div class='del'>-	struct faulty_conf *conf = priv;</div><div class='del'>-</div><div class='del'>-	kfree(conf);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct md_personality faulty_personality =</div><div class='del'>-{</div><div class='del'>-	.name		= "faulty",</div><div class='del'>-	.level		= LEVEL_FAULTY,</div><div class='del'>-	.owner		= THIS_MODULE,</div><div class='del'>-	.make_request	= faulty_make_request,</div><div class='del'>-	.run		= faulty_run,</div><div class='del'>-	.free		= faulty_free,</div><div class='del'>-	.status		= faulty_status,</div><div class='del'>-	.check_reshape	= faulty_reshape,</div><div class='del'>-	.size		= faulty_size,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int __init raid_init(void)</div><div class='del'>-{</div><div class='del'>-	return register_md_personality(&amp;faulty_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void raid_exit(void)</div><div class='del'>-{</div><div class='del'>-	unregister_md_personality(&amp;faulty_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-module_init(raid_init);</div><div class='del'>-module_exit(raid_exit);</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-MODULE_DESCRIPTION("Fault injection personality for MD (deprecated)");</div><div class='del'>-MODULE_ALIAS("md-personality-10"); /* faulty */</div><div class='del'>-MODULE_ALIAS("md-faulty");</div><div class='del'>-MODULE_ALIAS("md-level--5");</div><div class='head'>diff --git a/drivers/md/md-linear.c b/drivers/md/md-linear.c<br/>deleted file mode 100644<br/>index 8eca7693b793..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md-linear.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md-linear.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,318 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='del'>-/*</div><div class='del'>-   linear.c : Multiple Devices driver for Linux</div><div class='del'>-	      Copyright (C) 1994-96 Marc ZYNGIER</div><div class='del'>-	      &lt;zyngier@ufr-info-p7.ibp.fr&gt; or</div><div class='del'>-	      &lt;maz@gloups.fdn.fr&gt;</div><div class='del'>-</div><div class='del'>-   Linear mode management functions.</div><div class='del'>-</div><div class='del'>-*/</div><div class='del'>-</div><div class='del'>-#include &lt;linux/blkdev.h&gt;</div><div class='del'>-#include &lt;linux/raid/md_u.h&gt;</div><div class='del'>-#include &lt;linux/seq_file.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;trace/events/block.h&gt;</div><div class='del'>-#include "md.h"</div><div class='del'>-#include "md-linear.h"</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * find which device holds a particular offset</div><div class='del'>- */</div><div class='del'>-static inline struct dev_info *which_dev(struct mddev *mddev, sector_t sector)</div><div class='del'>-{</div><div class='del'>-	int lo, mid, hi;</div><div class='del'>-	struct linear_conf *conf;</div><div class='del'>-</div><div class='del'>-	lo = 0;</div><div class='del'>-	hi = mddev-&gt;raid_disks - 1;</div><div class='del'>-	conf = mddev-&gt;private;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Binary Search</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	while (hi &gt; lo) {</div><div class='del'>-</div><div class='del'>-		mid = (hi + lo) / 2;</div><div class='del'>-		if (sector &lt; conf-&gt;disks[mid].end_sector)</div><div class='del'>-			hi = mid;</div><div class='del'>-		else</div><div class='del'>-			lo = mid + 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return conf-&gt;disks + lo;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static sector_t linear_size(struct mddev *mddev, sector_t sectors, int raid_disks)</div><div class='del'>-{</div><div class='del'>-	struct linear_conf *conf;</div><div class='del'>-	sector_t array_sectors;</div><div class='del'>-</div><div class='del'>-	conf = mddev-&gt;private;</div><div class='del'>-	WARN_ONCE(sectors || raid_disks,</div><div class='del'>-		  "%s does not support generic reshape\n", __func__);</div><div class='del'>-	array_sectors = conf-&gt;array_sectors;</div><div class='del'>-</div><div class='del'>-	return array_sectors;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct linear_conf *linear_conf(struct mddev *mddev, int raid_disks)</div><div class='del'>-{</div><div class='del'>-	struct linear_conf *conf;</div><div class='del'>-	struct md_rdev *rdev;</div><div class='del'>-	int i, cnt;</div><div class='del'>-</div><div class='del'>-	conf = kzalloc(struct_size(conf, disks, raid_disks), GFP_KERNEL);</div><div class='del'>-	if (!conf)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * conf-&gt;raid_disks is copy of mddev-&gt;raid_disks. The reason to</div><div class='del'>-	 * keep a copy of mddev-&gt;raid_disks in struct linear_conf is,</div><div class='del'>-	 * mddev-&gt;raid_disks may not be consistent with pointers number of</div><div class='del'>-	 * conf-&gt;disks[] when it is updated in linear_add() and used to</div><div class='del'>-	 * iterate old conf-&gt;disks[] earray in linear_congested().</div><div class='del'>-	 * Here conf-&gt;raid_disks is always consitent with number of</div><div class='del'>-	 * pointers in conf-&gt;disks[] array, and mddev-&gt;private is updated</div><div class='del'>-	 * with rcu_assign_pointer() in linear_addr(), such race can be</div><div class='del'>-	 * avoided.</div><div class='del'>-	 */</div><div class='del'>-	conf-&gt;raid_disks = raid_disks;</div><div class='del'>-</div><div class='del'>-	cnt = 0;</div><div class='del'>-	conf-&gt;array_sectors = 0;</div><div class='del'>-</div><div class='del'>-	rdev_for_each(rdev, mddev) {</div><div class='del'>-		int j = rdev-&gt;raid_disk;</div><div class='del'>-		struct dev_info *disk = conf-&gt;disks + j;</div><div class='del'>-		sector_t sectors;</div><div class='del'>-</div><div class='del'>-		if (j &lt; 0 || j &gt;= raid_disks || disk-&gt;rdev) {</div><div class='del'>-			pr_warn("md/linear:%s: disk numbering problem. Aborting!\n",</div><div class='del'>-				mdname(mddev));</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		disk-&gt;rdev = rdev;</div><div class='del'>-		if (mddev-&gt;chunk_sectors) {</div><div class='del'>-			sectors = rdev-&gt;sectors;</div><div class='del'>-			sector_div(sectors, mddev-&gt;chunk_sectors);</div><div class='del'>-			rdev-&gt;sectors = sectors * mddev-&gt;chunk_sectors;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		disk_stack_limits(mddev-&gt;gendisk, rdev-&gt;bdev,</div><div class='del'>-				  rdev-&gt;data_offset &lt;&lt; 9);</div><div class='del'>-</div><div class='del'>-		conf-&gt;array_sectors += rdev-&gt;sectors;</div><div class='del'>-		cnt++;</div><div class='del'>-	}</div><div class='del'>-	if (cnt != raid_disks) {</div><div class='del'>-		pr_warn("md/linear:%s: not enough drives present. Aborting!\n",</div><div class='del'>-			mdname(mddev));</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Here we calculate the device offsets.</div><div class='del'>-	 */</div><div class='del'>-	conf-&gt;disks[0].end_sector = conf-&gt;disks[0].rdev-&gt;sectors;</div><div class='del'>-</div><div class='del'>-	for (i = 1; i &lt; raid_disks; i++)</div><div class='del'>-		conf-&gt;disks[i].end_sector =</div><div class='del'>-			conf-&gt;disks[i-1].end_sector +</div><div class='del'>-			conf-&gt;disks[i].rdev-&gt;sectors;</div><div class='del'>-</div><div class='del'>-	return conf;</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	kfree(conf);</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int linear_run (struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	struct linear_conf *conf;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (md_check_no_bitmap(mddev))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	conf = linear_conf(mddev, mddev-&gt;raid_disks);</div><div class='del'>-</div><div class='del'>-	if (!conf)</div><div class='del'>-		return 1;</div><div class='del'>-	mddev-&gt;private = conf;</div><div class='del'>-	md_set_array_sectors(mddev, linear_size(mddev, 0, 0));</div><div class='del'>-</div><div class='del'>-	ret =  md_integrity_register(mddev);</div><div class='del'>-	if (ret) {</div><div class='del'>-		kfree(conf);</div><div class='del'>-		mddev-&gt;private = NULL;</div><div class='del'>-	}</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int linear_add(struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	/* Adding a drive to a linear array allows the array to grow.</div><div class='del'>-	 * It is permitted if the new drive has a matching superblock</div><div class='del'>-	 * already on it, with raid_disk equal to raid_disks.</div><div class='del'>-	 * It is achieved by creating a new linear_private_data structure</div><div class='del'>-	 * and swapping it in in-place of the current one.</div><div class='del'>-	 * The current one is never freed until the array is stopped.</div><div class='del'>-	 * This avoids races.</div><div class='del'>-	 */</div><div class='del'>-	struct linear_conf *newconf, *oldconf;</div><div class='del'>-</div><div class='del'>-	if (rdev-&gt;saved_raid_disk != mddev-&gt;raid_disks)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	rdev-&gt;raid_disk = rdev-&gt;saved_raid_disk;</div><div class='del'>-	rdev-&gt;saved_raid_disk = -1;</div><div class='del'>-</div><div class='del'>-	newconf = linear_conf(mddev,mddev-&gt;raid_disks+1);</div><div class='del'>-</div><div class='del'>-	if (!newconf)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	/* newconf-&gt;raid_disks already keeps a copy of * the increased</div><div class='del'>-	 * value of mddev-&gt;raid_disks, WARN_ONCE() is just used to make</div><div class='del'>-	 * sure of this. It is possible that oldconf is still referenced</div><div class='del'>-	 * in linear_congested(), therefore kfree_rcu() is used to free</div><div class='del'>-	 * oldconf until no one uses it anymore.</div><div class='del'>-	 */</div><div class='del'>-	oldconf = rcu_dereference_protected(mddev-&gt;private,</div><div class='del'>-			lockdep_is_held(&amp;mddev-&gt;reconfig_mutex));</div><div class='del'>-	mddev-&gt;raid_disks++;</div><div class='del'>-	WARN_ONCE(mddev-&gt;raid_disks != newconf-&gt;raid_disks,</div><div class='del'>-		"copied raid_disks doesn't match mddev-&gt;raid_disks");</div><div class='del'>-	rcu_assign_pointer(mddev-&gt;private, newconf);</div><div class='del'>-	md_set_array_sectors(mddev, linear_size(mddev, 0, 0));</div><div class='del'>-	set_capacity_and_notify(mddev-&gt;gendisk, mddev-&gt;array_sectors);</div><div class='del'>-	kfree_rcu(oldconf, rcu);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void linear_free(struct mddev *mddev, void *priv)</div><div class='del'>-{</div><div class='del'>-	struct linear_conf *conf = priv;</div><div class='del'>-</div><div class='del'>-	kfree(conf);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool linear_make_request(struct mddev *mddev, struct bio *bio)</div><div class='del'>-{</div><div class='del'>-	struct dev_info *tmp_dev;</div><div class='del'>-	sector_t start_sector, end_sector, data_offset;</div><div class='del'>-	sector_t bio_sector = bio-&gt;bi_iter.bi_sector;</div><div class='del'>-</div><div class='del'>-	if (unlikely(bio-&gt;bi_opf &amp; REQ_PREFLUSH)</div><div class='del'>-	    &amp;&amp; md_flush_request(mddev, bio))</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	tmp_dev = which_dev(mddev, bio_sector);</div><div class='del'>-	start_sector = tmp_dev-&gt;end_sector - tmp_dev-&gt;rdev-&gt;sectors;</div><div class='del'>-	end_sector = tmp_dev-&gt;end_sector;</div><div class='del'>-	data_offset = tmp_dev-&gt;rdev-&gt;data_offset;</div><div class='del'>-</div><div class='del'>-	if (unlikely(bio_sector &gt;= end_sector ||</div><div class='del'>-		     bio_sector &lt; start_sector))</div><div class='del'>-		goto out_of_bounds;</div><div class='del'>-</div><div class='del'>-	if (unlikely(is_rdev_broken(tmp_dev-&gt;rdev))) {</div><div class='del'>-		md_error(mddev, tmp_dev-&gt;rdev);</div><div class='del'>-		bio_io_error(bio);</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (unlikely(bio_end_sector(bio) &gt; end_sector)) {</div><div class='del'>-		/* This bio crosses a device boundary, so we have to split it */</div><div class='del'>-		struct bio *split = bio_split(bio, end_sector - bio_sector,</div><div class='del'>-					      GFP_NOIO, &amp;mddev-&gt;bio_set);</div><div class='del'>-		bio_chain(split, bio);</div><div class='del'>-		submit_bio_noacct(bio);</div><div class='del'>-		bio = split;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	md_account_bio(mddev, &amp;bio);</div><div class='del'>-	bio_set_dev(bio, tmp_dev-&gt;rdev-&gt;bdev);</div><div class='del'>-	bio-&gt;bi_iter.bi_sector = bio-&gt;bi_iter.bi_sector -</div><div class='del'>-		start_sector + data_offset;</div><div class='del'>-</div><div class='del'>-	if (unlikely((bio_op(bio) == REQ_OP_DISCARD) &amp;&amp;</div><div class='del'>-		     !bdev_max_discard_sectors(bio-&gt;bi_bdev))) {</div><div class='del'>-		/* Just ignore it */</div><div class='del'>-		bio_endio(bio);</div><div class='del'>-	} else {</div><div class='del'>-		if (mddev-&gt;gendisk)</div><div class='del'>-			trace_block_bio_remap(bio, disk_devt(mddev-&gt;gendisk),</div><div class='del'>-					      bio_sector);</div><div class='del'>-		mddev_check_write_zeroes(mddev, bio);</div><div class='del'>-		submit_bio_noacct(bio);</div><div class='del'>-	}</div><div class='del'>-	return true;</div><div class='del'>-</div><div class='del'>-out_of_bounds:</div><div class='del'>-	pr_err("md/linear:%s: make_request: Sector %llu out of bounds on dev %pg: %llu sectors, offset %llu\n",</div><div class='del'>-	       mdname(mddev),</div><div class='del'>-	       (unsigned long long)bio-&gt;bi_iter.bi_sector,</div><div class='del'>-	       tmp_dev-&gt;rdev-&gt;bdev,</div><div class='del'>-	       (unsigned long long)tmp_dev-&gt;rdev-&gt;sectors,</div><div class='del'>-	       (unsigned long long)start_sector);</div><div class='del'>-	bio_io_error(bio);</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void linear_status (struct seq_file *seq, struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	seq_printf(seq, " %dk rounding", mddev-&gt;chunk_sectors / 2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void linear_error(struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	if (!test_and_set_bit(MD_BROKEN, &amp;mddev-&gt;flags)) {</div><div class='del'>-		char *md_name = mdname(mddev);</div><div class='del'>-</div><div class='del'>-		pr_crit("md/linear%s: Disk failure on %pg detected, failing array.\n",</div><div class='del'>-			md_name, rdev-&gt;bdev);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void linear_quiesce(struct mddev *mddev, int state)</div><div class='del'>-{</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct md_personality linear_personality =</div><div class='del'>-{</div><div class='del'>-	.name		= "linear",</div><div class='del'>-	.level		= LEVEL_LINEAR,</div><div class='del'>-	.owner		= THIS_MODULE,</div><div class='del'>-	.make_request	= linear_make_request,</div><div class='del'>-	.run		= linear_run,</div><div class='del'>-	.free		= linear_free,</div><div class='del'>-	.status		= linear_status,</div><div class='del'>-	.hot_add_disk	= linear_add,</div><div class='del'>-	.size		= linear_size,</div><div class='del'>-	.quiesce	= linear_quiesce,</div><div class='del'>-	.error_handler	= linear_error,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int __init linear_init (void)</div><div class='del'>-{</div><div class='del'>-	return register_md_personality (&amp;linear_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void linear_exit (void)</div><div class='del'>-{</div><div class='del'>-	unregister_md_personality (&amp;linear_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-module_init(linear_init);</div><div class='del'>-module_exit(linear_exit);</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-MODULE_DESCRIPTION("Linear device concatenation personality for MD (deprecated)");</div><div class='del'>-MODULE_ALIAS("md-personality-1"); /* LINEAR - deprecated*/</div><div class='del'>-MODULE_ALIAS("md-linear");</div><div class='del'>-MODULE_ALIAS("md-level--1");</div><div class='head'>diff --git a/drivers/md/md-multipath.c b/drivers/md/md-multipath.c<br/>deleted file mode 100644<br/>index d22276870283..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md-multipath.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md-multipath.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,471 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='del'>-/*</div><div class='del'>- * multipath.c : Multiple Devices driver for Linux</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 1999, 2000, 2001 Ingo Molnar, Red Hat</div><div class='del'>- *</div><div class='del'>- * Copyright (C) 1996, 1997, 1998 Ingo Molnar, Miguel de Icaza, Gadi Oxman</div><div class='del'>- *</div><div class='del'>- * MULTIPATH management functions.</div><div class='del'>- *</div><div class='del'>- * derived from raid1.c.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;linux/blkdev.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/raid/md_u.h&gt;</div><div class='del'>-#include &lt;linux/seq_file.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include "md.h"</div><div class='del'>-#include "md-multipath.h"</div><div class='del'>-</div><div class='del'>-#define MAX_WORK_PER_DISK 128</div><div class='del'>-</div><div class='del'>-#define	NR_RESERVED_BUFS	32</div><div class='del'>-</div><div class='del'>-static int multipath_map (struct mpconf *conf)</div><div class='del'>-{</div><div class='del'>-	int i, disks = conf-&gt;raid_disks;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Later we do read balancing on the read side</div><div class='del'>-	 * now we use the first available disk.</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	rcu_read_lock();</div><div class='del'>-	for (i = 0; i &lt; disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;multipaths[i].rdev);</div><div class='del'>-		if (rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='del'>-		    !test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='del'>-			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='del'>-			return i;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	rcu_read_unlock();</div><div class='del'>-</div><div class='del'>-	pr_crit_ratelimited("multipath_map(): no more operational IO paths?\n");</div><div class='del'>-	return (-1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void multipath_reschedule_retry (struct multipath_bh *mp_bh)</div><div class='del'>-{</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	struct mddev *mddev = mp_bh-&gt;mddev;</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-	list_add(&amp;mp_bh-&gt;retry_list, &amp;conf-&gt;retry_list);</div><div class='del'>-	spin_unlock_irqrestore(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-	md_wakeup_thread(mddev-&gt;thread);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * multipath_end_bh_io() is called when we have finished servicing a multipathed</div><div class='del'>- * operation and are ready to return a success/failure code to the buffer</div><div class='del'>- * cache layer.</div><div class='del'>- */</div><div class='del'>-static void multipath_end_bh_io(struct multipath_bh *mp_bh, blk_status_t status)</div><div class='del'>-{</div><div class='del'>-	struct bio *bio = mp_bh-&gt;master_bio;</div><div class='del'>-	struct mpconf *conf = mp_bh-&gt;mddev-&gt;private;</div><div class='del'>-</div><div class='del'>-	bio-&gt;bi_status = status;</div><div class='del'>-	bio_endio(bio);</div><div class='del'>-	mempool_free(mp_bh, &amp;conf-&gt;pool);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void multipath_end_request(struct bio *bio)</div><div class='del'>-{</div><div class='del'>-	struct multipath_bh *mp_bh = bio-&gt;bi_private;</div><div class='del'>-	struct mpconf *conf = mp_bh-&gt;mddev-&gt;private;</div><div class='del'>-	struct md_rdev *rdev = conf-&gt;multipaths[mp_bh-&gt;path].rdev;</div><div class='del'>-</div><div class='del'>-	if (!bio-&gt;bi_status)</div><div class='del'>-		multipath_end_bh_io(mp_bh, 0);</div><div class='del'>-	else if (!(bio-&gt;bi_opf &amp; REQ_RAHEAD)) {</div><div class='del'>-		/*</div><div class='del'>-		 * oops, IO error:</div><div class='del'>-		 */</div><div class='del'>-		md_error (mp_bh-&gt;mddev, rdev);</div><div class='del'>-		pr_info("multipath: %pg: rescheduling sector %llu\n",</div><div class='del'>-			rdev-&gt;bdev,</div><div class='del'>-			(unsigned long long)bio-&gt;bi_iter.bi_sector);</div><div class='del'>-		multipath_reschedule_retry(mp_bh);</div><div class='del'>-	} else</div><div class='del'>-		multipath_end_bh_io(mp_bh, bio-&gt;bi_status);</div><div class='del'>-	rdev_dec_pending(rdev, conf-&gt;mddev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool multipath_make_request(struct mddev *mddev, struct bio * bio)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-	struct multipath_bh * mp_bh;</div><div class='del'>-	struct multipath_info *multipath;</div><div class='del'>-</div><div class='del'>-	if (unlikely(bio-&gt;bi_opf &amp; REQ_PREFLUSH)</div><div class='del'>-	    &amp;&amp; md_flush_request(mddev, bio))</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	md_account_bio(mddev, &amp;bio);</div><div class='del'>-	mp_bh = mempool_alloc(&amp;conf-&gt;pool, GFP_NOIO);</div><div class='del'>-</div><div class='del'>-	mp_bh-&gt;master_bio = bio;</div><div class='del'>-	mp_bh-&gt;mddev = mddev;</div><div class='del'>-</div><div class='del'>-	mp_bh-&gt;path = multipath_map(conf);</div><div class='del'>-	if (mp_bh-&gt;path &lt; 0) {</div><div class='del'>-		bio_io_error(bio);</div><div class='del'>-		mempool_free(mp_bh, &amp;conf-&gt;pool);</div><div class='del'>-		return true;</div><div class='del'>-	}</div><div class='del'>-	multipath = conf-&gt;multipaths + mp_bh-&gt;path;</div><div class='del'>-</div><div class='del'>-	bio_init_clone(multipath-&gt;rdev-&gt;bdev, &amp;mp_bh-&gt;bio, bio, GFP_NOIO);</div><div class='del'>-</div><div class='del'>-	mp_bh-&gt;bio.bi_iter.bi_sector += multipath-&gt;rdev-&gt;data_offset;</div><div class='del'>-	mp_bh-&gt;bio.bi_opf |= REQ_FAILFAST_TRANSPORT;</div><div class='del'>-	mp_bh-&gt;bio.bi_end_io = multipath_end_request;</div><div class='del'>-	mp_bh-&gt;bio.bi_private = mp_bh;</div><div class='del'>-	mddev_check_write_zeroes(mddev, &amp;mp_bh-&gt;bio);</div><div class='del'>-	submit_bio_noacct(&amp;mp_bh-&gt;bio);</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void multipath_status(struct seq_file *seq, struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	seq_printf (seq, " [%d/%d] [", conf-&gt;raid_disks,</div><div class='del'>-		    conf-&gt;raid_disks - mddev-&gt;degraded);</div><div class='del'>-	rcu_read_lock();</div><div class='del'>-	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;multipaths[i].rdev);</div><div class='del'>-		seq_printf (seq, "%s", rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) ? "U" : "_");</div><div class='del'>-	}</div><div class='del'>-	rcu_read_unlock();</div><div class='del'>-	seq_putc(seq, ']');</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Careful, this can execute in IRQ contexts as well!</div><div class='del'>- */</div><div class='del'>-static void multipath_error (struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-</div><div class='del'>-	if (conf-&gt;raid_disks - mddev-&gt;degraded &lt;= 1) {</div><div class='del'>-		/*</div><div class='del'>-		 * Uh oh, we can do nothing if this is our last path, but</div><div class='del'>-		 * first check if this is a queued request for a device</div><div class='del'>-		 * which has just failed.</div><div class='del'>-		 */</div><div class='del'>-		pr_warn("multipath: only one IO path left and IO error.\n");</div><div class='del'>-		/* leave it active... it's all we have */</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * Mark disk as unusable</div><div class='del'>-	 */</div><div class='del'>-	if (test_and_clear_bit(In_sync, &amp;rdev-&gt;flags)) {</div><div class='del'>-		unsigned long flags;</div><div class='del'>-		spin_lock_irqsave(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-		mddev-&gt;degraded++;</div><div class='del'>-		spin_unlock_irqrestore(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-	}</div><div class='del'>-	set_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='del'>-	set_bit(MD_SB_CHANGE_DEVS, &amp;mddev-&gt;sb_flags);</div><div class='del'>-	pr_err("multipath: IO failure on %pg, disabling IO path.\n"</div><div class='del'>-	       "multipath: Operation continuing on %d IO paths.\n",</div><div class='del'>-	       rdev-&gt;bdev,</div><div class='del'>-	       conf-&gt;raid_disks - mddev-&gt;degraded);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void print_multipath_conf (struct mpconf *conf)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct multipath_info *tmp;</div><div class='del'>-</div><div class='del'>-	pr_debug("MULTIPATH conf printout:\n");</div><div class='del'>-	if (!conf) {</div><div class='del'>-		pr_debug("(conf==NULL)\n");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	pr_debug(" --- wd:%d rd:%d\n", conf-&gt;raid_disks - conf-&gt;mddev-&gt;degraded,</div><div class='del'>-		 conf-&gt;raid_disks);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		tmp = conf-&gt;multipaths + i;</div><div class='del'>-		if (tmp-&gt;rdev)</div><div class='del'>-			pr_debug(" disk%d, o:%d, dev:%pg\n",</div><div class='del'>-				 i,!test_bit(Faulty, &amp;tmp-&gt;rdev-&gt;flags),</div><div class='del'>-				 tmp-&gt;rdev-&gt;bdev);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int multipath_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-	int err = -EEXIST;</div><div class='del'>-	int path;</div><div class='del'>-	struct multipath_info *p;</div><div class='del'>-	int first = 0;</div><div class='del'>-	int last = mddev-&gt;raid_disks - 1;</div><div class='del'>-</div><div class='del'>-	if (rdev-&gt;raid_disk &gt;= 0)</div><div class='del'>-		first = last = rdev-&gt;raid_disk;</div><div class='del'>-</div><div class='del'>-	print_multipath_conf(conf);</div><div class='del'>-</div><div class='del'>-	for (path = first; path &lt;= last; path++)</div><div class='del'>-		if ((p=conf-&gt;multipaths+path)-&gt;rdev == NULL) {</div><div class='del'>-			disk_stack_limits(mddev-&gt;gendisk, rdev-&gt;bdev,</div><div class='del'>-					  rdev-&gt;data_offset &lt;&lt; 9);</div><div class='del'>-</div><div class='del'>-			err = md_integrity_add_rdev(rdev, mddev);</div><div class='del'>-			if (err)</div><div class='del'>-				break;</div><div class='del'>-			spin_lock_irq(&amp;conf-&gt;device_lock);</div><div class='del'>-			mddev-&gt;degraded--;</div><div class='del'>-			rdev-&gt;raid_disk = path;</div><div class='del'>-			set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='del'>-			spin_unlock_irq(&amp;conf-&gt;device_lock);</div><div class='del'>-			rcu_assign_pointer(p-&gt;rdev, rdev);</div><div class='del'>-			err = 0;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	print_multipath_conf(conf);</div><div class='del'>-</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int multipath_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-	int err = 0;</div><div class='del'>-	int number = rdev-&gt;raid_disk;</div><div class='del'>-	struct multipath_info *p = conf-&gt;multipaths + number;</div><div class='del'>-</div><div class='del'>-	print_multipath_conf(conf);</div><div class='del'>-</div><div class='del'>-	if (rdev == p-&gt;rdev) {</div><div class='del'>-		if (test_bit(In_sync, &amp;rdev-&gt;flags) ||</div><div class='del'>-		    atomic_read(&amp;rdev-&gt;nr_pending)) {</div><div class='del'>-			pr_warn("hot-remove-disk, slot %d is identified but is still operational!\n", number);</div><div class='del'>-			err = -EBUSY;</div><div class='del'>-			goto abort;</div><div class='del'>-		}</div><div class='del'>-		p-&gt;rdev = NULL;</div><div class='del'>-		if (!test_bit(RemoveSynchronized, &amp;rdev-&gt;flags)) {</div><div class='del'>-			synchronize_rcu();</div><div class='del'>-			if (atomic_read(&amp;rdev-&gt;nr_pending)) {</div><div class='del'>-				/* lost the race, try later */</div><div class='del'>-				err = -EBUSY;</div><div class='del'>-				p-&gt;rdev = rdev;</div><div class='del'>-				goto abort;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		err = md_integrity_register(mddev);</div><div class='del'>-	}</div><div class='del'>-abort:</div><div class='del'>-</div><div class='del'>-	print_multipath_conf(conf);</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * This is a kernel thread which:</div><div class='del'>- *</div><div class='del'>- *	1.	Retries failed read operations on working multipaths.</div><div class='del'>- *	2.	Updates the raid superblock when problems encounter.</div><div class='del'>- *	3.	Performs writes following reads for array syncronising.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static void multipathd(struct md_thread *thread)</div><div class='del'>-{</div><div class='del'>-	struct mddev *mddev = thread-&gt;mddev;</div><div class='del'>-	struct multipath_bh *mp_bh;</div><div class='del'>-	struct bio *bio;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	struct mpconf *conf = mddev-&gt;private;</div><div class='del'>-	struct list_head *head = &amp;conf-&gt;retry_list;</div><div class='del'>-</div><div class='del'>-	md_check_recovery(mddev);</div><div class='del'>-	for (;;) {</div><div class='del'>-		spin_lock_irqsave(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-		if (list_empty(head))</div><div class='del'>-			break;</div><div class='del'>-		mp_bh = list_entry(head-&gt;prev, struct multipath_bh, retry_list);</div><div class='del'>-		list_del(head-&gt;prev);</div><div class='del'>-		spin_unlock_irqrestore(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-</div><div class='del'>-		bio = &amp;mp_bh-&gt;bio;</div><div class='del'>-		bio-&gt;bi_iter.bi_sector = mp_bh-&gt;master_bio-&gt;bi_iter.bi_sector;</div><div class='del'>-</div><div class='del'>-		if ((mp_bh-&gt;path = multipath_map (conf))&lt;0) {</div><div class='del'>-			pr_err("multipath: %pg: unrecoverable IO read error for block %llu\n",</div><div class='del'>-			       bio-&gt;bi_bdev,</div><div class='del'>-			       (unsigned long long)bio-&gt;bi_iter.bi_sector);</div><div class='del'>-			multipath_end_bh_io(mp_bh, BLK_STS_IOERR);</div><div class='del'>-		} else {</div><div class='del'>-			pr_err("multipath: %pg: redirecting sector %llu to another IO path\n",</div><div class='del'>-			       bio-&gt;bi_bdev,</div><div class='del'>-			       (unsigned long long)bio-&gt;bi_iter.bi_sector);</div><div class='del'>-			*bio = *(mp_bh-&gt;master_bio);</div><div class='del'>-			bio-&gt;bi_iter.bi_sector +=</div><div class='del'>-				conf-&gt;multipaths[mp_bh-&gt;path].rdev-&gt;data_offset;</div><div class='del'>-			bio_set_dev(bio, conf-&gt;multipaths[mp_bh-&gt;path].rdev-&gt;bdev);</div><div class='del'>-			bio-&gt;bi_opf |= REQ_FAILFAST_TRANSPORT;</div><div class='del'>-			bio-&gt;bi_end_io = multipath_end_request;</div><div class='del'>-			bio-&gt;bi_private = mp_bh;</div><div class='del'>-			submit_bio_noacct(bio);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;conf-&gt;device_lock, flags);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static sector_t multipath_size(struct mddev *mddev, sector_t sectors, int raid_disks)</div><div class='del'>-{</div><div class='del'>-	WARN_ONCE(sectors || raid_disks,</div><div class='del'>-		  "%s does not support generic reshape\n", __func__);</div><div class='del'>-</div><div class='del'>-	return mddev-&gt;dev_sectors;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int multipath_run (struct mddev *mddev)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf;</div><div class='del'>-	int disk_idx;</div><div class='del'>-	struct multipath_info *disk;</div><div class='del'>-	struct md_rdev *rdev;</div><div class='del'>-	int working_disks;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	if (md_check_no_bitmap(mddev))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if (mddev-&gt;level != LEVEL_MULTIPATH) {</div><div class='del'>-		pr_warn("multipath: %s: raid level not set to multipath IO (%d)\n",</div><div class='del'>-			mdname(mddev), mddev-&gt;level);</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * copy the already verified devices into our private MULTIPATH</div><div class='del'>-	 * bookkeeping area. [whatever we allocate in multipath_run(),</div><div class='del'>-	 * should be freed in multipath_free()]</div><div class='del'>-	 */</div><div class='del'>-</div><div class='del'>-	conf = kzalloc(sizeof(struct mpconf), GFP_KERNEL);</div><div class='del'>-	mddev-&gt;private = conf;</div><div class='del'>-	if (!conf)</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	conf-&gt;multipaths = kcalloc(mddev-&gt;raid_disks,</div><div class='del'>-				   sizeof(struct multipath_info),</div><div class='del'>-				   GFP_KERNEL);</div><div class='del'>-	if (!conf-&gt;multipaths)</div><div class='del'>-		goto out_free_conf;</div><div class='del'>-</div><div class='del'>-	working_disks = 0;</div><div class='del'>-	rdev_for_each(rdev, mddev) {</div><div class='del'>-		disk_idx = rdev-&gt;raid_disk;</div><div class='del'>-		if (disk_idx &lt; 0 ||</div><div class='del'>-		    disk_idx &gt;= mddev-&gt;raid_disks)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		disk = conf-&gt;multipaths + disk_idx;</div><div class='del'>-		disk-&gt;rdev = rdev;</div><div class='del'>-		disk_stack_limits(mddev-&gt;gendisk, rdev-&gt;bdev,</div><div class='del'>-				  rdev-&gt;data_offset &lt;&lt; 9);</div><div class='del'>-</div><div class='del'>-		if (!test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='del'>-			working_disks++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	conf-&gt;raid_disks = mddev-&gt;raid_disks;</div><div class='del'>-	conf-&gt;mddev = mddev;</div><div class='del'>-	spin_lock_init(&amp;conf-&gt;device_lock);</div><div class='del'>-	INIT_LIST_HEAD(&amp;conf-&gt;retry_list);</div><div class='del'>-</div><div class='del'>-	if (!working_disks) {</div><div class='del'>-		pr_warn("multipath: no operational IO paths for %s\n",</div><div class='del'>-			mdname(mddev));</div><div class='del'>-		goto out_free_conf;</div><div class='del'>-	}</div><div class='del'>-	mddev-&gt;degraded = conf-&gt;raid_disks - working_disks;</div><div class='del'>-</div><div class='del'>-	ret = mempool_init_kmalloc_pool(&amp;conf-&gt;pool, NR_RESERVED_BUFS,</div><div class='del'>-					sizeof(struct multipath_bh));</div><div class='del'>-	if (ret)</div><div class='del'>-		goto out_free_conf;</div><div class='del'>-</div><div class='del'>-	rcu_assign_pointer(mddev-&gt;thread,</div><div class='del'>-			   md_register_thread(multipathd, mddev, "multipath"));</div><div class='del'>-	if (!mddev-&gt;thread)</div><div class='del'>-		goto out_free_conf;</div><div class='del'>-</div><div class='del'>-	pr_info("multipath: array %s active with %d out of %d IO paths\n",</div><div class='del'>-		mdname(mddev), conf-&gt;raid_disks - mddev-&gt;degraded,</div><div class='del'>-		mddev-&gt;raid_disks);</div><div class='del'>-	/*</div><div class='del'>-	 * Ok, everything is just fine now</div><div class='del'>-	 */</div><div class='del'>-	md_set_array_sectors(mddev, multipath_size(mddev, 0, 0));</div><div class='del'>-</div><div class='del'>-	if (md_integrity_register(mddev))</div><div class='del'>-		goto out_free_conf;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-out_free_conf:</div><div class='del'>-	mempool_exit(&amp;conf-&gt;pool);</div><div class='del'>-	kfree(conf-&gt;multipaths);</div><div class='del'>-	kfree(conf);</div><div class='del'>-	mddev-&gt;private = NULL;</div><div class='del'>-out:</div><div class='del'>-	return -EIO;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void multipath_free(struct mddev *mddev, void *priv)</div><div class='del'>-{</div><div class='del'>-	struct mpconf *conf = priv;</div><div class='del'>-</div><div class='del'>-	mempool_exit(&amp;conf-&gt;pool);</div><div class='del'>-	kfree(conf-&gt;multipaths);</div><div class='del'>-	kfree(conf);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct md_personality multipath_personality =</div><div class='del'>-{</div><div class='del'>-	.name		= "multipath",</div><div class='del'>-	.level		= LEVEL_MULTIPATH,</div><div class='del'>-	.owner		= THIS_MODULE,</div><div class='del'>-	.make_request	= multipath_make_request,</div><div class='del'>-	.run		= multipath_run,</div><div class='del'>-	.free		= multipath_free,</div><div class='del'>-	.status		= multipath_status,</div><div class='del'>-	.error_handler	= multipath_error,</div><div class='del'>-	.hot_add_disk	= multipath_add_disk,</div><div class='del'>-	.hot_remove_disk= multipath_remove_disk,</div><div class='del'>-	.size		= multipath_size,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int __init multipath_init (void)</div><div class='del'>-{</div><div class='del'>-	return register_md_personality (&amp;multipath_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void __exit multipath_exit (void)</div><div class='del'>-{</div><div class='del'>-	unregister_md_personality (&amp;multipath_personality);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-module_init(multipath_init);</div><div class='del'>-module_exit(multipath_exit);</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-MODULE_DESCRIPTION("simple multi-path personality for MD (deprecated)");</div><div class='del'>-MODULE_ALIAS("md-personality-7"); /* MULTIPATH */</div><div class='del'>-MODULE_ALIAS("md-multipath");</div><div class='del'>-MODULE_ALIAS("md-level--4");</div><div class='head'>diff --git a/drivers/md/md.c b/drivers/md/md.c<br/>index c94373d64f2c..2266358d8074 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/md.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md.c</a></div><div class='hunk'>@@ -82,6 +82,14 @@ static struct module *md_cluster_mod;</div><div class='ctx'> </div><div class='ctx'> static DECLARE_WAIT_QUEUE_HEAD(resync_wait);</div><div class='ctx'> static struct workqueue_struct *md_wq;</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This workqueue is used for sync_work to register new sync_thread, and for</div><div class='add'>+ * del_work to remove rdev, and for event_work that is only set by dm-raid.</div><div class='add'>+ *</div><div class='add'>+ * Noted that sync_work will grab reconfig_mutex, hence never flush this</div><div class='add'>+ * workqueue whith reconfig_mutex grabbed.</div><div class='add'>+ */</div><div class='ctx'> static struct workqueue_struct *md_misc_wq;</div><div class='ctx'> struct workqueue_struct *md_bitmap_wq;</div><div class='ctx'> </div><div class='hunk'>@@ -490,7 +498,7 @@ int mddev_suspend(struct mddev *mddev, bool interruptible)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mddev_suspend);</div><div class='ctx'> </div><div class='del'>-void mddev_resume(struct mddev *mddev)</div><div class='add'>+static void __mddev_resume(struct mddev *mddev, bool recovery_needed)</div><div class='ctx'> {</div><div class='ctx'> 	lockdep_assert_not_held(&amp;mddev-&gt;reconfig_mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -507,12 +515,18 @@ void mddev_resume(struct mddev *mddev)</div><div class='ctx'> 	percpu_ref_resurrect(&amp;mddev-&gt;active_io);</div><div class='ctx'> 	wake_up(&amp;mddev-&gt;sb_wait);</div><div class='ctx'> </div><div class='del'>-	set_bit(MD_RECOVERY_NEEDED, &amp;mddev-&gt;recovery);</div><div class='add'>+	if (recovery_needed)</div><div class='add'>+		set_bit(MD_RECOVERY_NEEDED, &amp;mddev-&gt;recovery);</div><div class='ctx'> 	md_wakeup_thread(mddev-&gt;thread);</div><div class='ctx'> 	md_wakeup_thread(mddev-&gt;sync_thread); /* possibly kick off a reshape */</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;mddev-&gt;suspend_mutex);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void mddev_resume(struct mddev *mddev)</div><div class='add'>+{</div><div class='add'>+	return __mddev_resume(mddev, true);</div><div class='add'>+}</div><div class='ctx'> EXPORT_SYMBOL_GPL(mddev_resume);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -529,6 +543,9 @@ static void md_end_flush(struct bio *bio)</div><div class='ctx'> 	rdev_dec_pending(rdev, mddev);</div><div class='ctx'> </div><div class='ctx'> 	if (atomic_dec_and_test(&amp;mddev-&gt;flush_pending)) {</div><div class='add'>+		/* The pair is percpu_ref_get() from md_flush_request() */</div><div class='add'>+		percpu_ref_put(&amp;mddev-&gt;active_io);</div><div class='add'>+</div><div class='ctx'> 		/* The pre-request flush has finished */</div><div class='ctx'> 		queue_work(md_wq, &amp;mddev-&gt;flush_work);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -548,12 +565,8 @@ static void submit_flushes(struct work_struct *ws)</div><div class='ctx'> 	rdev_for_each_rcu(rdev, mddev)</div><div class='ctx'> 		if (rdev-&gt;raid_disk &gt;= 0 &amp;&amp;</div><div class='ctx'> 		    !test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='del'>-			/* Take two references, one is dropped</div><div class='del'>-			 * when request finishes, one after</div><div class='del'>-			 * we reclaim rcu_read_lock</div><div class='del'>-			 */</div><div class='ctx'> 			struct bio *bi;</div><div class='del'>-			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='add'>+</div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='ctx'> 			rcu_read_unlock();</div><div class='ctx'> 			bi = bio_alloc_bioset(rdev-&gt;bdev, 0,</div><div class='hunk'>@@ -564,7 +577,6 @@ static void submit_flushes(struct work_struct *ws)</div><div class='ctx'> 			atomic_inc(&amp;mddev-&gt;flush_pending);</div><div class='ctx'> 			submit_bio(bi);</div><div class='ctx'> 			rcu_read_lock();</div><div class='del'>-			rdev_dec_pending(rdev, mddev);</div><div class='ctx'> 		}</div><div class='ctx'> 	rcu_read_unlock();</div><div class='ctx'> 	if (atomic_dec_and_test(&amp;mddev-&gt;flush_pending))</div><div class='hunk'>@@ -617,6 +629,18 @@ bool md_flush_request(struct mddev *mddev, struct bio *bio)</div><div class='ctx'> 	/* new request after previous flush is completed */</div><div class='ctx'> 	if (ktime_after(req_start, mddev-&gt;prev_flush_start)) {</div><div class='ctx'> 		WARN_ON(mddev-&gt;flush_bio);</div><div class='add'>+		/*</div><div class='add'>+		 * Grab a reference to make sure mddev_suspend() will wait for</div><div class='add'>+		 * this flush to be done.</div><div class='add'>+		 *</div><div class='add'>+		 * md_flush_reqeust() is called under md_handle_request() and</div><div class='add'>+		 * 'active_io' is already grabbed, hence percpu_ref_is_zero()</div><div class='add'>+		 * won't pass, percpu_ref_tryget_live() can't be used because</div><div class='add'>+		 * percpu_ref_kill() can be called by mddev_suspend()</div><div class='add'>+		 * concurrently.</div><div class='add'>+		 */</div><div class='add'>+		WARN_ON(percpu_ref_is_zero(&amp;mddev-&gt;active_io));</div><div class='add'>+		percpu_ref_get(&amp;mddev-&gt;active_io);</div><div class='ctx'> 		mddev-&gt;flush_bio = bio;</div><div class='ctx'> 		bio = NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1013,9 +1037,10 @@ void md_super_write(struct mddev *mddev, struct md_rdev *rdev,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	bio = bio_alloc_bioset(rdev-&gt;meta_bdev ? rdev-&gt;meta_bdev : rdev-&gt;bdev,</div><div class='del'>-			       1,</div><div class='del'>-			       REQ_OP_WRITE | REQ_SYNC | REQ_PREFLUSH | REQ_FUA,</div><div class='del'>-			       GFP_NOIO, &amp;mddev-&gt;sync_set);</div><div class='add'>+			      1,</div><div class='add'>+			      REQ_OP_WRITE | REQ_SYNC | REQ_IDLE | REQ_META</div><div class='add'>+				  | REQ_PREFLUSH | REQ_FUA,</div><div class='add'>+			      GFP_NOIO, &amp;mddev-&gt;sync_set);</div><div class='ctx'> </div><div class='ctx'> 	atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='ctx'> </div><div class='hunk'>@@ -1195,6 +1220,7 @@ struct super_type  {</div><div class='ctx'> 					  struct md_rdev *refdev,</div><div class='ctx'> 					  int minor_version);</div><div class='ctx'> 	int		    (*validate_super)(struct mddev *mddev,</div><div class='add'>+					      struct md_rdev *freshest,</div><div class='ctx'> 					      struct md_rdev *rdev);</div><div class='ctx'> 	void		    (*sync_super)(struct mddev *mddev,</div><div class='ctx'> 					  struct md_rdev *rdev);</div><div class='hunk'>@@ -1275,17 +1301,11 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor</div><div class='ctx'> 	rdev-&gt;sb_size = MD_SB_BYTES;</div><div class='ctx'> 	rdev-&gt;badblocks.shift = -1;</div><div class='ctx'> </div><div class='del'>-	if (sb-&gt;level == LEVEL_MULTIPATH)</div><div class='del'>-		rdev-&gt;desc_nr = -1;</div><div class='del'>-	else</div><div class='del'>-		rdev-&gt;desc_nr = sb-&gt;this_disk.number;</div><div class='del'>-</div><div class='del'>-	/* not spare disk, or LEVEL_MULTIPATH */</div><div class='del'>-	if (sb-&gt;level == LEVEL_MULTIPATH ||</div><div class='del'>-		(rdev-&gt;desc_nr &gt;= 0 &amp;&amp;</div><div class='del'>-		 rdev-&gt;desc_nr &lt; MD_SB_DISKS &amp;&amp;</div><div class='del'>-		 sb-&gt;disks[rdev-&gt;desc_nr].state &amp;</div><div class='del'>-		 ((1&lt;&lt;MD_DISK_SYNC) | (1 &lt;&lt; MD_DISK_ACTIVE))))</div><div class='add'>+	rdev-&gt;desc_nr = sb-&gt;this_disk.number;</div><div class='add'>+</div><div class='add'>+	/* not spare disk */</div><div class='add'>+	if (rdev-&gt;desc_nr &gt;= 0 &amp;&amp; rdev-&gt;desc_nr &lt; MD_SB_DISKS &amp;&amp;</div><div class='add'>+	    sb-&gt;disks[rdev-&gt;desc_nr].state &amp; ((1&lt;&lt;MD_DISK_SYNC) | (1 &lt;&lt; MD_DISK_ACTIVE)))</div><div class='ctx'> 		spare_disk = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!refdev) {</div><div class='hunk'>@@ -1332,8 +1352,9 @@ static int super_90_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * validate_super for 0.90.0</div><div class='add'>+ * note: we are not using "freshest" for 0.9 superblock</div><div class='ctx'>  */</div><div class='del'>-static int super_90_validate(struct mddev *mddev, struct md_rdev *rdev)</div><div class='add'>+static int super_90_validate(struct mddev *mddev, struct md_rdev *freshest, struct md_rdev *rdev)</div><div class='ctx'> {</div><div class='ctx'> 	mdp_disk_t *desc;</div><div class='ctx'> 	mdp_super_t *sb = page_address(rdev-&gt;sb_page);</div><div class='hunk'>@@ -1431,31 +1452,28 @@ static int super_90_validate(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (mddev-&gt;level != LEVEL_MULTIPATH) {</div><div class='del'>-		desc = sb-&gt;disks + rdev-&gt;desc_nr;</div><div class='add'>+	desc = sb-&gt;disks + rdev-&gt;desc_nr;</div><div class='ctx'> </div><div class='del'>-		if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_FAULTY))</div><div class='del'>-			set_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='del'>-		else if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_SYNC) /* &amp;&amp;</div><div class='del'>-			    desc-&gt;raid_disk &lt; mddev-&gt;raid_disks */) {</div><div class='del'>-			set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='add'>+	if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_FAULTY))</div><div class='add'>+		set_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='add'>+	else if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_SYNC)) {</div><div class='add'>+		set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='add'>+		rdev-&gt;raid_disk = desc-&gt;raid_disk;</div><div class='add'>+		rdev-&gt;saved_raid_disk = desc-&gt;raid_disk;</div><div class='add'>+	} else if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_ACTIVE)) {</div><div class='add'>+		/* active but not in sync implies recovery up to</div><div class='add'>+		 * reshape position.  We don't know exactly where</div><div class='add'>+		 * that is, so set to zero for now</div><div class='add'>+		 */</div><div class='add'>+		if (mddev-&gt;minor_version &gt;= 91) {</div><div class='add'>+			rdev-&gt;recovery_offset = 0;</div><div class='ctx'> 			rdev-&gt;raid_disk = desc-&gt;raid_disk;</div><div class='del'>-			rdev-&gt;saved_raid_disk = desc-&gt;raid_disk;</div><div class='del'>-		} else if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_ACTIVE)) {</div><div class='del'>-			/* active but not in sync implies recovery up to</div><div class='del'>-			 * reshape position.  We don't know exactly where</div><div class='del'>-			 * that is, so set to zero for now */</div><div class='del'>-			if (mddev-&gt;minor_version &gt;= 91) {</div><div class='del'>-				rdev-&gt;recovery_offset = 0;</div><div class='del'>-				rdev-&gt;raid_disk = desc-&gt;raid_disk;</div><div class='del'>-			}</div><div class='ctx'> 		}</div><div class='del'>-		if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_WRITEMOSTLY))</div><div class='del'>-			set_bit(WriteMostly, &amp;rdev-&gt;flags);</div><div class='del'>-		if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_FAILFAST))</div><div class='del'>-			set_bit(FailFast, &amp;rdev-&gt;flags);</div><div class='del'>-	} else /* MULTIPATH are always insync */</div><div class='del'>-		set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='add'>+	}</div><div class='add'>+	if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_WRITEMOSTLY))</div><div class='add'>+		set_bit(WriteMostly, &amp;rdev-&gt;flags);</div><div class='add'>+	if (desc-&gt;state &amp; (1&lt;&lt;MD_DISK_FAILFAST))</div><div class='add'>+		set_bit(FailFast, &amp;rdev-&gt;flags);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1745,10 +1763,7 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_</div><div class='ctx'> 	    &amp;&amp; rdev-&gt;new_data_offset &lt; sb_start + (rdev-&gt;sb_size/512))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (sb-&gt;level == cpu_to_le32(LEVEL_MULTIPATH))</div><div class='del'>-		rdev-&gt;desc_nr = -1;</div><div class='del'>-	else</div><div class='del'>-		rdev-&gt;desc_nr = le32_to_cpu(sb-&gt;dev_number);</div><div class='add'>+	rdev-&gt;desc_nr = le32_to_cpu(sb-&gt;dev_number);</div><div class='ctx'> </div><div class='ctx'> 	if (!rdev-&gt;bb_page) {</div><div class='ctx'> 		rdev-&gt;bb_page = alloc_page(GFP_KERNEL);</div><div class='hunk'>@@ -1801,12 +1816,10 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_</div><div class='ctx'> 	    sb-&gt;level != 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	/* not spare disk, or LEVEL_MULTIPATH */</div><div class='del'>-	if (sb-&gt;level == cpu_to_le32(LEVEL_MULTIPATH) ||</div><div class='del'>-		(rdev-&gt;desc_nr &gt;= 0 &amp;&amp;</div><div class='del'>-		rdev-&gt;desc_nr &lt; le32_to_cpu(sb-&gt;max_dev) &amp;&amp;</div><div class='del'>-		(le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) &lt; MD_DISK_ROLE_MAX ||</div><div class='del'>-		 le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) == MD_DISK_ROLE_JOURNAL)))</div><div class='add'>+	/* not spare disk */</div><div class='add'>+	if (rdev-&gt;desc_nr &gt;= 0 &amp;&amp; rdev-&gt;desc_nr &lt; le32_to_cpu(sb-&gt;max_dev) &amp;&amp;</div><div class='add'>+	    (le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) &lt; MD_DISK_ROLE_MAX ||</div><div class='add'>+	     le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) == MD_DISK_ROLE_JOURNAL))</div><div class='ctx'> 		spare_disk = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!refdev) {</div><div class='hunk'>@@ -1845,10 +1858,11 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int super_1_validate(struct mddev *mddev, struct md_rdev *rdev)</div><div class='add'>+static int super_1_validate(struct mddev *mddev, struct md_rdev *freshest, struct md_rdev *rdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mdp_superblock_1 *sb = page_address(rdev-&gt;sb_page);</div><div class='ctx'> 	__u64 ev1 = le64_to_cpu(sb-&gt;events);</div><div class='add'>+	int role;</div><div class='ctx'> </div><div class='ctx'> 	rdev-&gt;raid_disk = -1;</div><div class='ctx'> 	clear_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='hunk'>@@ -1941,13 +1955,15 @@ static int super_1_validate(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (mddev-&gt;pers == NULL) {</div><div class='ctx'> 		/* Insist of good event counter while assembling, except for</div><div class='del'>-		 * spares (which don't need an event count) */</div><div class='del'>-		++ev1;</div><div class='add'>+		 * spares (which don't need an event count).</div><div class='add'>+		 * Similar to mdadm, we allow event counter difference of 1</div><div class='add'>+		 * from the freshest device.</div><div class='add'>+		 */</div><div class='ctx'> 		if (rdev-&gt;desc_nr &gt;= 0 &amp;&amp;</div><div class='ctx'> 		    rdev-&gt;desc_nr &lt; le32_to_cpu(sb-&gt;max_dev) &amp;&amp;</div><div class='ctx'> 		    (le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) &lt; MD_DISK_ROLE_MAX ||</div><div class='ctx'> 		     le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]) == MD_DISK_ROLE_JOURNAL))</div><div class='del'>-			if (ev1 &lt; mddev-&gt;events)</div><div class='add'>+			if (ev1 + 1 &lt; mddev-&gt;events)</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> 	} else if (mddev-&gt;bitmap) {</div><div class='ctx'> 		/* If adding to array with a bitmap, then we can accept an</div><div class='hunk'>@@ -1962,58 +1978,85 @@ static int super_1_validate(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			/* just a hot-add of a new device, leave raid_disk at -1 */</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='del'>-	if (mddev-&gt;level != LEVEL_MULTIPATH) {</div><div class='del'>-		int role;</div><div class='del'>-		if (rdev-&gt;desc_nr &lt; 0 ||</div><div class='del'>-		    rdev-&gt;desc_nr &gt;= le32_to_cpu(sb-&gt;max_dev)) {</div><div class='del'>-			role = MD_DISK_ROLE_SPARE;</div><div class='del'>-			rdev-&gt;desc_nr = -1;</div><div class='del'>-		} else</div><div class='del'>-			role = le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]);</div><div class='del'>-		switch(role) {</div><div class='del'>-		case MD_DISK_ROLE_SPARE: /* spare */</div><div class='del'>-			break;</div><div class='del'>-		case MD_DISK_ROLE_FAULTY: /* faulty */</div><div class='del'>-			set_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='del'>-			break;</div><div class='del'>-		case MD_DISK_ROLE_JOURNAL: /* journal device */</div><div class='del'>-			if (!(le32_to_cpu(sb-&gt;feature_map) &amp; MD_FEATURE_JOURNAL)) {</div><div class='del'>-				/* journal device without journal feature */</div><div class='del'>-				pr_warn("md: journal device provided without journal feature, ignoring the device\n");</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			}</div><div class='del'>-			set_bit(Journal, &amp;rdev-&gt;flags);</div><div class='del'>-			rdev-&gt;journal_tail = le64_to_cpu(sb-&gt;journal_tail);</div><div class='del'>-			rdev-&gt;raid_disk = 0;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			rdev-&gt;saved_raid_disk = role;</div><div class='del'>-			if ((le32_to_cpu(sb-&gt;feature_map) &amp;</div><div class='del'>-			     MD_FEATURE_RECOVERY_OFFSET)) {</div><div class='del'>-				rdev-&gt;recovery_offset = le64_to_cpu(sb-&gt;recovery_offset);</div><div class='del'>-				if (!(le32_to_cpu(sb-&gt;feature_map) &amp;</div><div class='del'>-				      MD_FEATURE_RECOVERY_BITMAP))</div><div class='del'>-					rdev-&gt;saved_raid_disk = -1;</div><div class='del'>-			} else {</div><div class='del'>-				/*</div><div class='del'>-				 * If the array is FROZEN, then the device can't</div><div class='del'>-				 * be in_sync with rest of array.</div><div class='del'>-				 */</div><div class='del'>-				if (!test_bit(MD_RECOVERY_FROZEN,</div><div class='del'>-					      &amp;mddev-&gt;recovery))</div><div class='del'>-					set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='del'>-			}</div><div class='del'>-			rdev-&gt;raid_disk = role;</div><div class='del'>-			break;</div><div class='add'>+</div><div class='add'>+	if (rdev-&gt;desc_nr &lt; 0 ||</div><div class='add'>+	    rdev-&gt;desc_nr &gt;= le32_to_cpu(sb-&gt;max_dev)) {</div><div class='add'>+		role = MD_DISK_ROLE_SPARE;</div><div class='add'>+		rdev-&gt;desc_nr = -1;</div><div class='add'>+	} else if (mddev-&gt;pers == NULL &amp;&amp; freshest &amp;&amp; ev1 &lt; mddev-&gt;events) {</div><div class='add'>+		/*</div><div class='add'>+		 * If we are assembling, and our event counter is smaller than the</div><div class='add'>+		 * highest event counter, we cannot trust our superblock about the role.</div><div class='add'>+		 * It could happen that our rdev was marked as Faulty, and all other</div><div class='add'>+		 * superblocks were updated with +1 event counter.</div><div class='add'>+		 * Then, before the next superblock update, which typically happens when</div><div class='add'>+		 * remove_and_add_spares() removes the device from the array, there was</div><div class='add'>+		 * a crash or reboot.</div><div class='add'>+		 * If we allow current rdev without consulting the freshest superblock,</div><div class='add'>+		 * we could cause data corruption.</div><div class='add'>+		 * Note that in this case our event counter is smaller by 1 than the</div><div class='add'>+		 * highest, otherwise, this rdev would not be allowed into array;</div><div class='add'>+		 * both kernel and mdadm allow event counter difference of 1.</div><div class='add'>+		 */</div><div class='add'>+		struct mdp_superblock_1 *freshest_sb = page_address(freshest-&gt;sb_page);</div><div class='add'>+		u32 freshest_max_dev = le32_to_cpu(freshest_sb-&gt;max_dev);</div><div class='add'>+</div><div class='add'>+		if (rdev-&gt;desc_nr &gt;= freshest_max_dev) {</div><div class='add'>+			/* this is unexpected, better not proceed */</div><div class='add'>+			pr_warn("md: %s: rdev[%pg]: desc_nr(%d) &gt;= freshest(%pg)-&gt;sb-&gt;max_dev(%u)\n",</div><div class='add'>+				mdname(mddev), rdev-&gt;bdev, rdev-&gt;desc_nr,</div><div class='add'>+				freshest-&gt;bdev, freshest_max_dev);</div><div class='add'>+			return -EUCLEAN;</div><div class='ctx'> 		}</div><div class='del'>-		if (sb-&gt;devflags &amp; WriteMostly1)</div><div class='del'>-			set_bit(WriteMostly, &amp;rdev-&gt;flags);</div><div class='del'>-		if (sb-&gt;devflags &amp; FailFast1)</div><div class='del'>-			set_bit(FailFast, &amp;rdev-&gt;flags);</div><div class='del'>-		if (le32_to_cpu(sb-&gt;feature_map) &amp; MD_FEATURE_REPLACEMENT)</div><div class='del'>-			set_bit(Replacement, &amp;rdev-&gt;flags);</div><div class='del'>-	} else /* MULTIPATH are always insync */</div><div class='del'>-		set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='add'>+</div><div class='add'>+		role = le16_to_cpu(freshest_sb-&gt;dev_roles[rdev-&gt;desc_nr]);</div><div class='add'>+		pr_debug("md: %s: rdev[%pg]: role=%d(0x%x) according to freshest %pg\n",</div><div class='add'>+			 mdname(mddev), rdev-&gt;bdev, role, role, freshest-&gt;bdev);</div><div class='add'>+	} else {</div><div class='add'>+		role = le16_to_cpu(sb-&gt;dev_roles[rdev-&gt;desc_nr]);</div><div class='add'>+	}</div><div class='add'>+	switch (role) {</div><div class='add'>+	case MD_DISK_ROLE_SPARE: /* spare */</div><div class='add'>+		break;</div><div class='add'>+	case MD_DISK_ROLE_FAULTY: /* faulty */</div><div class='add'>+		set_bit(Faulty, &amp;rdev-&gt;flags);</div><div class='add'>+		break;</div><div class='add'>+	case MD_DISK_ROLE_JOURNAL: /* journal device */</div><div class='add'>+		if (!(le32_to_cpu(sb-&gt;feature_map) &amp; MD_FEATURE_JOURNAL)) {</div><div class='add'>+			/* journal device without journal feature */</div><div class='add'>+			pr_warn("md: journal device provided without journal feature, ignoring the device\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		set_bit(Journal, &amp;rdev-&gt;flags);</div><div class='add'>+		rdev-&gt;journal_tail = le64_to_cpu(sb-&gt;journal_tail);</div><div class='add'>+		rdev-&gt;raid_disk = 0;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		rdev-&gt;saved_raid_disk = role;</div><div class='add'>+		if ((le32_to_cpu(sb-&gt;feature_map) &amp;</div><div class='add'>+		     MD_FEATURE_RECOVERY_OFFSET)) {</div><div class='add'>+			rdev-&gt;recovery_offset = le64_to_cpu(sb-&gt;recovery_offset);</div><div class='add'>+			if (!(le32_to_cpu(sb-&gt;feature_map) &amp;</div><div class='add'>+			      MD_FEATURE_RECOVERY_BITMAP))</div><div class='add'>+				rdev-&gt;saved_raid_disk = -1;</div><div class='add'>+		} else {</div><div class='add'>+			/*</div><div class='add'>+			 * If the array is FROZEN, then the device can't</div><div class='add'>+			 * be in_sync with rest of array.</div><div class='add'>+			 */</div><div class='add'>+			if (!test_bit(MD_RECOVERY_FROZEN,</div><div class='add'>+				      &amp;mddev-&gt;recovery))</div><div class='add'>+				set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='add'>+		}</div><div class='add'>+		rdev-&gt;raid_disk = role;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	if (sb-&gt;devflags &amp; WriteMostly1)</div><div class='add'>+		set_bit(WriteMostly, &amp;rdev-&gt;flags);</div><div class='add'>+	if (sb-&gt;devflags &amp; FailFast1)</div><div class='add'>+		set_bit(FailFast, &amp;rdev-&gt;flags);</div><div class='add'>+	if (le32_to_cpu(sb-&gt;feature_map) &amp; MD_FEATURE_REPLACEMENT)</div><div class='add'>+		set_bit(Replacement, &amp;rdev-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2831,10 +2874,6 @@ rewrite:</div><div class='ctx'> 		} else</div><div class='ctx'> 			pr_debug("md: %pg (skipping faulty)\n",</div><div class='ctx'> 				 rdev-&gt;bdev);</div><div class='del'>-</div><div class='del'>-		if (mddev-&gt;level == LEVEL_MULTIPATH)</div><div class='del'>-			/* only need to write one superblock... */</div><div class='del'>-			break;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (md_super_wait(mddev) &lt; 0)</div><div class='ctx'> 		goto rewrite;</div><div class='hunk'>@@ -2876,7 +2915,7 @@ static int add_bound_rdev(struct md_rdev *rdev)</div><div class='ctx'> 		 * and should be added immediately.</div><div class='ctx'> 		 */</div><div class='ctx'> 		super_types[mddev-&gt;major_version].</div><div class='del'>-			validate_super(mddev, rdev);</div><div class='add'>+			validate_super(mddev, NULL/*freshest*/, rdev);</div><div class='ctx'> 		err = mddev-&gt;pers-&gt;hot_add_disk(mddev, rdev);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			md_kick_rdev_from_array(rdev);</div><div class='hunk'>@@ -3813,7 +3852,7 @@ static int analyze_sbs(struct mddev *mddev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	super_types[mddev-&gt;major_version].</div><div class='del'>-		validate_super(mddev, freshest);</div><div class='add'>+		validate_super(mddev, NULL/*freshest*/, freshest);</div><div class='ctx'> </div><div class='ctx'> 	i = 0;</div><div class='ctx'> 	rdev_for_each_safe(rdev, tmp, mddev) {</div><div class='hunk'>@@ -3828,20 +3867,15 @@ static int analyze_sbs(struct mddev *mddev)</div><div class='ctx'> 		}</div><div class='ctx'> 		if (rdev != freshest) {</div><div class='ctx'> 			if (super_types[mddev-&gt;major_version].</div><div class='del'>-			    validate_super(mddev, rdev)) {</div><div class='add'>+			    validate_super(mddev, freshest, rdev)) {</div><div class='ctx'> 				pr_warn("md: kicking non-fresh %pg from array!\n",</div><div class='ctx'> 					rdev-&gt;bdev);</div><div class='ctx'> 				md_kick_rdev_from_array(rdev);</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='del'>-		if (mddev-&gt;level == LEVEL_MULTIPATH) {</div><div class='del'>-			rdev-&gt;desc_nr = i++;</div><div class='del'>-			rdev-&gt;raid_disk = rdev-&gt;desc_nr;</div><div class='del'>-			set_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='del'>-		} else if (rdev-&gt;raid_disk &gt;=</div><div class='del'>-			    (mddev-&gt;raid_disks - min(0, mddev-&gt;delta_disks)) &amp;&amp;</div><div class='del'>-			   !test_bit(Journal, &amp;rdev-&gt;flags)) {</div><div class='add'>+		if (rdev-&gt;raid_disk &gt;= (mddev-&gt;raid_disks - min(0, mddev-&gt;delta_disks)) &amp;&amp;</div><div class='add'>+		    !test_bit(Journal, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 			rdev-&gt;raid_disk = -1;</div><div class='ctx'> 			clear_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -4840,25 +4874,29 @@ action_show(struct mddev *mddev, char *page)</div><div class='ctx'> 	return sprintf(page, "%s\n", type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void stop_sync_thread(struct mddev *mddev)</div><div class='add'>+/**</div><div class='add'>+ * stop_sync_thread() - wait for sync_thread to stop if it's running.</div><div class='add'>+ * @mddev:	the array.</div><div class='add'>+ * @locked:	if set, reconfig_mutex will still be held after this function</div><div class='add'>+ *		return; if not set, reconfig_mutex will be released after this</div><div class='add'>+ *		function return.</div><div class='add'>+ * @check_seq:	if set, only wait for curent running sync_thread to stop, noted</div><div class='add'>+ *		that new sync_thread can still start.</div><div class='add'>+ */</div><div class='add'>+static void stop_sync_thread(struct mddev *mddev, bool locked, bool check_seq)</div><div class='ctx'> {</div><div class='del'>-	if (!test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery))</div><div class='del'>-		return;</div><div class='add'>+	int sync_seq;</div><div class='ctx'> </div><div class='del'>-	if (mddev_lock(mddev))</div><div class='del'>-		return;</div><div class='add'>+	if (check_seq)</div><div class='add'>+		sync_seq = atomic_read(&amp;mddev-&gt;sync_seq);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Check again in case MD_RECOVERY_RUNNING is cleared before lock is</div><div class='del'>-	 * held.</div><div class='del'>-	 */</div><div class='ctx'> 	if (!test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery)) {</div><div class='del'>-		mddev_unlock(mddev);</div><div class='add'>+		if (!locked)</div><div class='add'>+			mddev_unlock(mddev);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (work_pending(&amp;mddev-&gt;del_work))</div><div class='del'>-		flush_workqueue(md_misc_wq);</div><div class='add'>+	mddev_unlock(mddev);</div><div class='ctx'> </div><div class='ctx'> 	set_bit(MD_RECOVERY_INTR, &amp;mddev-&gt;recovery);</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -4866,21 +4904,28 @@ static void stop_sync_thread(struct mddev *mddev)</div><div class='ctx'> 	 * never happen</div><div class='ctx'> 	 */</div><div class='ctx'> 	md_wakeup_thread_directly(mddev-&gt;sync_thread);</div><div class='add'>+	if (work_pending(&amp;mddev-&gt;sync_work))</div><div class='add'>+		flush_work(&amp;mddev-&gt;sync_work);</div><div class='ctx'> </div><div class='del'>-	mddev_unlock(mddev);</div><div class='add'>+	wait_event(resync_wait,</div><div class='add'>+		   !test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery) ||</div><div class='add'>+		   (check_seq &amp;&amp; sync_seq != atomic_read(&amp;mddev-&gt;sync_seq)));</div><div class='add'>+</div><div class='add'>+	if (locked)</div><div class='add'>+		mddev_lock_nointr(mddev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void idle_sync_thread(struct mddev *mddev)</div><div class='ctx'> {</div><div class='del'>-	int sync_seq = atomic_read(&amp;mddev-&gt;sync_seq);</div><div class='del'>-</div><div class='ctx'> 	mutex_lock(&amp;mddev-&gt;sync_mutex);</div><div class='ctx'> 	clear_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='del'>-	stop_sync_thread(mddev);</div><div class='ctx'> </div><div class='del'>-	wait_event(resync_wait, sync_seq != atomic_read(&amp;mddev-&gt;sync_seq) ||</div><div class='del'>-			!test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery));</div><div class='add'>+	if (mddev_lock(mddev)) {</div><div class='add'>+		mutex_unlock(&amp;mddev-&gt;sync_mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	stop_sync_thread(mddev, false, true);</div><div class='ctx'> 	mutex_unlock(&amp;mddev-&gt;sync_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4888,11 +4933,13 @@ static void frozen_sync_thread(struct mddev *mddev)</div><div class='ctx'> {</div><div class='ctx'> 	mutex_lock(&amp;mddev-&gt;sync_mutex);</div><div class='ctx'> 	set_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='del'>-	stop_sync_thread(mddev);</div><div class='ctx'> </div><div class='del'>-	wait_event(resync_wait, mddev-&gt;sync_thread == NULL &amp;&amp;</div><div class='del'>-			!test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery));</div><div class='add'>+	if (mddev_lock(mddev)) {</div><div class='add'>+		mutex_unlock(&amp;mddev-&gt;sync_mutex);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	stop_sync_thread(mddev, false, false);</div><div class='ctx'> 	mutex_unlock(&amp;mddev-&gt;sync_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6264,14 +6311,7 @@ static void md_clean(struct mddev *mddev)</div><div class='ctx'> </div><div class='ctx'> static void __md_stop_writes(struct mddev *mddev)</div><div class='ctx'> {</div><div class='del'>-	set_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='del'>-	if (work_pending(&amp;mddev-&gt;del_work))</div><div class='del'>-		flush_workqueue(md_misc_wq);</div><div class='del'>-	if (mddev-&gt;sync_thread) {</div><div class='del'>-		set_bit(MD_RECOVERY_INTR, &amp;mddev-&gt;recovery);</div><div class='del'>-		md_reap_sync_thread(mddev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='add'>+	stop_sync_thread(mddev, true, false);</div><div class='ctx'> 	del_timer_sync(&amp;mddev-&gt;safemode_timer);</div><div class='ctx'> </div><div class='ctx'> 	if (mddev-&gt;pers &amp;&amp; mddev-&gt;pers-&gt;quiesce) {</div><div class='hunk'>@@ -6318,9 +6358,6 @@ static void __md_stop(struct mddev *mddev)</div><div class='ctx'> 	struct md_personality *pers = mddev-&gt;pers;</div><div class='ctx'> 	md_bitmap_destroy(mddev);</div><div class='ctx'> 	mddev_detach(mddev);</div><div class='del'>-	/* Ensure -&gt;event_work is done */</div><div class='del'>-	if (mddev-&gt;event_work.func)</div><div class='del'>-		flush_workqueue(md_misc_wq);</div><div class='ctx'> 	spin_lock(&amp;mddev-&gt;lock);</div><div class='ctx'> 	mddev-&gt;pers = NULL;</div><div class='ctx'> 	spin_unlock(&amp;mddev-&gt;lock);</div><div class='hunk'>@@ -6355,25 +6392,16 @@ static int md_set_readonly(struct mddev *mddev, struct block_device *bdev)</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> 	int did_freeze = 0;</div><div class='ctx'> </div><div class='add'>+	if (mddev-&gt;external &amp;&amp; test_bit(MD_SB_CHANGE_PENDING, &amp;mddev-&gt;sb_flags))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='ctx'> 	if (!test_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery)) {</div><div class='ctx'> 		did_freeze = 1;</div><div class='ctx'> 		set_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='ctx'> 		md_wakeup_thread(mddev-&gt;thread);</div><div class='ctx'> 	}</div><div class='del'>-	if (test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery))</div><div class='del'>-		set_bit(MD_RECOVERY_INTR, &amp;mddev-&gt;recovery);</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Thread might be blocked waiting for metadata update which will now</div><div class='del'>-	 * never happen</div><div class='del'>-	 */</div><div class='del'>-	md_wakeup_thread_directly(mddev-&gt;sync_thread);</div><div class='ctx'> </div><div class='del'>-	if (mddev-&gt;external &amp;&amp; test_bit(MD_SB_CHANGE_PENDING, &amp;mddev-&gt;sb_flags))</div><div class='del'>-		return -EBUSY;</div><div class='del'>-	mddev_unlock(mddev);</div><div class='del'>-	wait_event(resync_wait, !test_bit(MD_RECOVERY_RUNNING,</div><div class='del'>-					  &amp;mddev-&gt;recovery));</div><div class='add'>+	stop_sync_thread(mddev, false, false);</div><div class='ctx'> 	wait_event(mddev-&gt;sb_wait,</div><div class='ctx'> 		   !test_bit(MD_SB_CHANGE_PENDING, &amp;mddev-&gt;sb_flags));</div><div class='ctx'> 	mddev_lock_nointr(mddev);</div><div class='hunk'>@@ -6383,29 +6411,30 @@ static int md_set_readonly(struct mddev *mddev, struct block_device *bdev)</div><div class='ctx'> 	    mddev-&gt;sync_thread ||</div><div class='ctx'> 	    test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery)) {</div><div class='ctx'> 		pr_warn("md: %s still in use.\n",mdname(mddev));</div><div class='del'>-		if (did_freeze) {</div><div class='del'>-			clear_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='del'>-			set_bit(MD_RECOVERY_NEEDED, &amp;mddev-&gt;recovery);</div><div class='del'>-			md_wakeup_thread(mddev-&gt;thread);</div><div class='del'>-		}</div><div class='ctx'> 		err = -EBUSY;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	if (mddev-&gt;pers) {</div><div class='ctx'> 		__md_stop_writes(mddev);</div><div class='ctx'> </div><div class='del'>-		err  = -ENXIO;</div><div class='del'>-		if (mddev-&gt;ro == MD_RDONLY)</div><div class='add'>+		if (mddev-&gt;ro == MD_RDONLY) {</div><div class='add'>+			err  = -ENXIO;</div><div class='ctx'> 			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		mddev-&gt;ro = MD_RDONLY;</div><div class='ctx'> 		set_disk_ro(mddev-&gt;gendisk, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	if ((mddev-&gt;pers &amp;&amp; !err) || did_freeze) {</div><div class='ctx'> 		clear_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='ctx'> 		set_bit(MD_RECOVERY_NEEDED, &amp;mddev-&gt;recovery);</div><div class='ctx'> 		md_wakeup_thread(mddev-&gt;thread);</div><div class='ctx'> 		sysfs_notify_dirent_safe(mddev-&gt;sysfs_state);</div><div class='del'>-		err = 0;</div><div class='ctx'> 	}</div><div class='del'>-out:</div><div class='add'>+</div><div class='ctx'> 	mutex_unlock(&amp;mddev-&gt;open_mutex);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -6426,20 +6455,8 @@ static int do_md_stop(struct mddev *mddev, int mode,</div><div class='ctx'> 		set_bit(MD_RECOVERY_FROZEN, &amp;mddev-&gt;recovery);</div><div class='ctx'> 		md_wakeup_thread(mddev-&gt;thread);</div><div class='ctx'> 	}</div><div class='del'>-	if (test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery))</div><div class='del'>-		set_bit(MD_RECOVERY_INTR, &amp;mddev-&gt;recovery);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Thread might be blocked waiting for metadata update which will now</div><div class='del'>-	 * never happen</div><div class='del'>-	 */</div><div class='del'>-	md_wakeup_thread_directly(mddev-&gt;sync_thread);</div><div class='del'>-</div><div class='del'>-	mddev_unlock(mddev);</div><div class='del'>-	wait_event(resync_wait, (mddev-&gt;sync_thread == NULL &amp;&amp;</div><div class='del'>-				 !test_bit(MD_RECOVERY_RUNNING,</div><div class='del'>-					   &amp;mddev-&gt;recovery)));</div><div class='del'>-	mddev_lock_nointr(mddev);</div><div class='add'>+	stop_sync_thread(mddev, true, false);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;mddev-&gt;open_mutex);</div><div class='ctx'> 	if ((mddev-&gt;pers &amp;&amp; atomic_read(&amp;mddev-&gt;openers) &gt; !!bdev) ||</div><div class='hunk'>@@ -6836,7 +6853,7 @@ int md_add_new_disk(struct mddev *mddev, struct mdu_disk_info_s *info)</div><div class='ctx'> 			rdev-&gt;saved_raid_disk = rdev-&gt;raid_disk;</div><div class='ctx'> 		} else</div><div class='ctx'> 			super_types[mddev-&gt;major_version].</div><div class='del'>-				validate_super(mddev, rdev);</div><div class='add'>+				validate_super(mddev, NULL/*freshest*/, rdev);</div><div class='ctx'> 		if ((info-&gt;state &amp; (1&lt;&lt;MD_DISK_SYNC)) &amp;&amp;</div><div class='ctx'> 		     rdev-&gt;raid_disk != info-&gt;raid_disk) {</div><div class='ctx'> 			/* This was a hot-add request, but events doesn't</div><div class='hunk'>@@ -8079,7 +8096,7 @@ void md_error(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 		return;</div><div class='ctx'> 	mddev-&gt;pers-&gt;error_handler(mddev, rdev);</div><div class='ctx'> </div><div class='del'>-	if (mddev-&gt;pers-&gt;level == 0 || mddev-&gt;pers-&gt;level == LEVEL_LINEAR)</div><div class='add'>+	if (mddev-&gt;pers-&gt;level == 0)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (mddev-&gt;degraded &amp;&amp; !test_bit(MD_BROKEN, &amp;mddev-&gt;flags))</div><div class='hunk'>@@ -8115,6 +8132,19 @@ static void status_unused(struct seq_file *seq)</div><div class='ctx'> 	seq_printf(seq, "\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void status_personalities(struct seq_file *seq)</div><div class='add'>+{</div><div class='add'>+	struct md_personality *pers;</div><div class='add'>+</div><div class='add'>+	seq_puts(seq, "Personalities : ");</div><div class='add'>+	spin_lock(&amp;pers_lock);</div><div class='add'>+	list_for_each_entry(pers, &amp;pers_list, list)</div><div class='add'>+		seq_printf(seq, "[%s] ", pers-&gt;name);</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;pers_lock);</div><div class='add'>+	seq_puts(seq, "\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int status_resync(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> {</div><div class='ctx'> 	sector_t max_sectors, resync, res;</div><div class='hunk'>@@ -8256,20 +8286,10 @@ static int status_resync(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> static void *md_seq_start(struct seq_file *seq, loff_t *pos)</div><div class='ctx'> 	__acquires(&amp;all_mddevs_lock)</div><div class='ctx'> {</div><div class='del'>-	struct md_personality *pers;</div><div class='del'>-</div><div class='del'>-	seq_puts(seq, "Personalities : ");</div><div class='del'>-	spin_lock(&amp;pers_lock);</div><div class='del'>-	list_for_each_entry(pers, &amp;pers_list, list)</div><div class='del'>-		seq_printf(seq, "[%s] ", pers-&gt;name);</div><div class='del'>-</div><div class='del'>-	spin_unlock(&amp;pers_lock);</div><div class='del'>-	seq_puts(seq, "\n");</div><div class='ctx'> 	seq-&gt;poll_event = atomic_read(&amp;md_event_count);</div><div class='del'>-</div><div class='ctx'> 	spin_lock(&amp;all_mddevs_lock);</div><div class='ctx'> </div><div class='del'>-	return seq_list_start(&amp;all_mddevs, *pos);</div><div class='add'>+	return seq_list_start_head(&amp;all_mddevs, *pos);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void *md_seq_next(struct seq_file *seq, void *v, loff_t *pos)</div><div class='hunk'>@@ -8280,16 +8300,23 @@ static void *md_seq_next(struct seq_file *seq, void *v, loff_t *pos)</div><div class='ctx'> static void md_seq_stop(struct seq_file *seq, void *v)</div><div class='ctx'> 	__releases(&amp;all_mddevs_lock)</div><div class='ctx'> {</div><div class='del'>-	status_unused(seq);</div><div class='ctx'> 	spin_unlock(&amp;all_mddevs_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int md_seq_show(struct seq_file *seq, void *v)</div><div class='ctx'> {</div><div class='del'>-	struct mddev *mddev = list_entry(v, struct mddev, all_mddevs);</div><div class='add'>+	struct mddev *mddev;</div><div class='ctx'> 	sector_t sectors;</div><div class='ctx'> 	struct md_rdev *rdev;</div><div class='ctx'> </div><div class='add'>+	if (v == &amp;all_mddevs) {</div><div class='add'>+		status_personalities(seq);</div><div class='add'>+		if (list_empty(&amp;all_mddevs))</div><div class='add'>+			status_unused(seq);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mddev = list_entry(v, struct mddev, all_mddevs);</div><div class='ctx'> 	if (!mddev_get(mddev))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -8365,6 +8392,10 @@ static int md_seq_show(struct seq_file *seq, void *v)</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock(&amp;mddev-&gt;lock);</div><div class='ctx'> 	spin_lock(&amp;all_mddevs_lock);</div><div class='add'>+</div><div class='add'>+	if (mddev == list_last_entry(&amp;all_mddevs, struct mddev, all_mddevs))</div><div class='add'>+		status_unused(seq);</div><div class='add'>+</div><div class='ctx'> 	if (atomic_dec_and_test(&amp;mddev-&gt;active))</div><div class='ctx'> 		__mddev_put(mddev);</div><div class='ctx'> </div><div class='hunk'>@@ -9243,44 +9274,19 @@ static int remove_and_add_spares(struct mddev *mddev,</div><div class='ctx'> 	struct md_rdev *rdev;</div><div class='ctx'> 	int spares = 0;</div><div class='ctx'> 	int removed = 0;</div><div class='del'>-	bool remove_some = false;</div><div class='ctx'> </div><div class='ctx'> 	if (this &amp;&amp; test_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery))</div><div class='ctx'> 		/* Mustn't remove devices when resync thread is running */</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	rdev_for_each(rdev, mddev) {</div><div class='del'>-		if ((this == NULL || rdev == this) &amp;&amp;</div><div class='del'>-		    rdev-&gt;raid_disk &gt;= 0 &amp;&amp;</div><div class='del'>-		    !test_bit(Blocked, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='del'>-		    test_bit(Faulty, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='del'>-		    atomic_read(&amp;rdev-&gt;nr_pending)==0) {</div><div class='del'>-			/* Faulty non-Blocked devices with nr_pending == 0</div><div class='del'>-			 * never get nr_pending incremented,</div><div class='del'>-			 * never get Faulty cleared, and never get Blocked set.</div><div class='del'>-			 * So we can synchronize_rcu now rather than once per device</div><div class='del'>-			 */</div><div class='del'>-			remove_some = true;</div><div class='del'>-			set_bit(RemoveSynchronized, &amp;rdev-&gt;flags);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (remove_some)</div><div class='del'>-		synchronize_rcu();</div><div class='del'>-	rdev_for_each(rdev, mddev) {</div><div class='del'>-		if ((this == NULL || rdev == this) &amp;&amp;</div><div class='del'>-		    (test_bit(RemoveSynchronized, &amp;rdev-&gt;flags) ||</div><div class='del'>-		     rdev_removeable(rdev))) {</div><div class='del'>-			if (mddev-&gt;pers-&gt;hot_remove_disk(</div><div class='del'>-				    mddev, rdev) == 0) {</div><div class='del'>-				sysfs_unlink_rdev(mddev, rdev);</div><div class='del'>-				rdev-&gt;saved_raid_disk = rdev-&gt;raid_disk;</div><div class='del'>-				rdev-&gt;raid_disk = -1;</div><div class='del'>-				removed++;</div><div class='del'>-			}</div><div class='add'>+		if ((this == NULL || rdev == this) &amp;&amp; rdev_removeable(rdev) &amp;&amp;</div><div class='add'>+		    !mddev-&gt;pers-&gt;hot_remove_disk(mddev, rdev)) {</div><div class='add'>+			sysfs_unlink_rdev(mddev, rdev);</div><div class='add'>+			rdev-&gt;saved_raid_disk = rdev-&gt;raid_disk;</div><div class='add'>+			rdev-&gt;raid_disk = -1;</div><div class='add'>+			removed++;</div><div class='ctx'> 		}</div><div class='del'>-		if (remove_some &amp;&amp; test_bit(RemoveSynchronized, &amp;rdev-&gt;flags))</div><div class='del'>-			clear_bit(RemoveSynchronized, &amp;rdev-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (removed &amp;&amp; mddev-&gt;kobj.sd)</div><div class='hunk'>@@ -9403,7 +9409,15 @@ static void md_start_sync(struct work_struct *ws)</div><div class='ctx'> 		goto not_running;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	suspend ? mddev_unlock_and_resume(mddev) : mddev_unlock(mddev);</div><div class='add'>+	mddev_unlock(mddev);</div><div class='add'>+	/*</div><div class='add'>+	 * md_start_sync was triggered by MD_RECOVERY_NEEDED, so we should</div><div class='add'>+	 * not set it again. Otherwise, we may cause issue like this one:</div><div class='add'>+	 *     https://bugzilla.kernel.org/show_bug.cgi?id=218200</div><div class='add'>+	 * Therefore, use __mddev_resume(mddev, false).</div><div class='add'>+	 */</div><div class='add'>+	if (suspend)</div><div class='add'>+		__mddev_resume(mddev, false);</div><div class='ctx'> 	md_wakeup_thread(mddev-&gt;sync_thread);</div><div class='ctx'> 	sysfs_notify_dirent_safe(mddev-&gt;sysfs_action);</div><div class='ctx'> 	md_new_event();</div><div class='hunk'>@@ -9415,7 +9429,15 @@ not_running:</div><div class='ctx'> 	clear_bit(MD_RECOVERY_REQUESTED, &amp;mddev-&gt;recovery);</div><div class='ctx'> 	clear_bit(MD_RECOVERY_CHECK, &amp;mddev-&gt;recovery);</div><div class='ctx'> 	clear_bit(MD_RECOVERY_RUNNING, &amp;mddev-&gt;recovery);</div><div class='del'>-	suspend ? mddev_unlock_and_resume(mddev) : mddev_unlock(mddev);</div><div class='add'>+	mddev_unlock(mddev);</div><div class='add'>+	/*</div><div class='add'>+	 * md_start_sync was triggered by MD_RECOVERY_NEEDED, so we should</div><div class='add'>+	 * not set it again. Otherwise, we may cause issue like this one:</div><div class='add'>+	 *     https://bugzilla.kernel.org/show_bug.cgi?id=218200</div><div class='add'>+	 * Therefore, use __mddev_resume(mddev, false).</div><div class='add'>+	 */</div><div class='add'>+	if (suspend)</div><div class='add'>+		__mddev_resume(mddev, false);</div><div class='ctx'> </div><div class='ctx'> 	wake_up(&amp;resync_wait);</div><div class='ctx'> 	if (test_and_clear_bit(MD_RECOVERY_RECOVER, &amp;mddev-&gt;recovery) &amp;&amp;</div><div class='head'>diff --git a/drivers/md/md.h b/drivers/md/md.h<br/>index ade83af123a2..8d881cc59799 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/md.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/md.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/md.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/md.h</a></div><div class='hunk'>@@ -190,11 +190,6 @@ enum flag_bits {</div><div class='ctx'> 				 * than other devices in the array</div><div class='ctx'> 				 */</div><div class='ctx'> 	ClusterRemove,</div><div class='del'>-	RemoveSynchronized,	/* synchronize_rcu() was called after</div><div class='del'>-				 * this device was known to be faulty,</div><div class='del'>-				 * so it is safe to remove without</div><div class='del'>-				 * another synchronize_rcu() call.</div><div class='del'>-				 */</div><div class='ctx'> 	ExternalBbl,            /* External metadata provides bad</div><div class='ctx'> 				 * block management for a disk</div><div class='ctx'> 				 */</div><div class='head'>diff --git a/drivers/md/raid1-10.c b/drivers/md/raid1-10.c<br/>index 3f22edec70e7..512746551f36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid1-10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid1-10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid1-10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid1-10.c</a></div><div class='hunk'>@@ -173,3 +173,57 @@ static inline void raid1_prepare_flush_writes(struct bitmap *bitmap)</div><div class='ctx'> 	else</div><div class='ctx'> 		md_bitmap_unplug(bitmap);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Used by fix_read_error() to decay the per rdev read_errors.</div><div class='add'>+ * We halve the read error count for every hour that has elapsed</div><div class='add'>+ * since the last recorded read error.</div><div class='add'>+ */</div><div class='add'>+static inline void check_decay_read_errors(struct mddev *mddev, struct md_rdev *rdev)</div><div class='add'>+{</div><div class='add'>+	long cur_time_mon;</div><div class='add'>+	unsigned long hours_since_last;</div><div class='add'>+	unsigned int read_errors = atomic_read(&amp;rdev-&gt;read_errors);</div><div class='add'>+</div><div class='add'>+	cur_time_mon = ktime_get_seconds();</div><div class='add'>+</div><div class='add'>+	if (rdev-&gt;last_read_error == 0) {</div><div class='add'>+		/* first time we've seen a read error */</div><div class='add'>+		rdev-&gt;last_read_error = cur_time_mon;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hours_since_last = (long)(cur_time_mon -</div><div class='add'>+			    rdev-&gt;last_read_error) / 3600;</div><div class='add'>+</div><div class='add'>+	rdev-&gt;last_read_error = cur_time_mon;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * if hours_since_last is &gt; the number of bits in read_errors</div><div class='add'>+	 * just set read errors to 0. We do this to avoid</div><div class='add'>+	 * overflowing the shift of read_errors by hours_since_last.</div><div class='add'>+	 */</div><div class='add'>+	if (hours_since_last &gt;= 8 * sizeof(read_errors))</div><div class='add'>+		atomic_set(&amp;rdev-&gt;read_errors, 0);</div><div class='add'>+	else</div><div class='add'>+		atomic_set(&amp;rdev-&gt;read_errors, read_errors &gt;&gt; hours_since_last);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool exceed_read_errors(struct mddev *mddev, struct md_rdev *rdev)</div><div class='add'>+{</div><div class='add'>+	int max_read_errors = atomic_read(&amp;mddev-&gt;max_corr_read_errors);</div><div class='add'>+	int read_errors;</div><div class='add'>+</div><div class='add'>+	check_decay_read_errors(mddev, rdev);</div><div class='add'>+	read_errors =  atomic_inc_return(&amp;rdev-&gt;read_errors);</div><div class='add'>+	if (read_errors &gt; max_read_errors) {</div><div class='add'>+		pr_notice("md/"RAID_1_10_NAME":%s: %pg: Raid device exceeded read_error threshold [cur %d:max %d]\n",</div><div class='add'>+			  mdname(mddev), rdev-&gt;bdev, read_errors, max_read_errors);</div><div class='add'>+		pr_notice("md/"RAID_1_10_NAME":%s: %pg: Failing raid device\n",</div><div class='add'>+			  mdname(mddev), rdev-&gt;bdev);</div><div class='add'>+		md_error(mddev, rdev);</div><div class='add'>+		return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c<br/>index 35d12948e0a9..24f0d799fd98 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid1.c</a></div><div class='hunk'>@@ -49,6 +49,7 @@ static void lower_barrier(struct r1conf *conf, sector_t sector_nr);</div><div class='ctx'> #define raid1_log(md, fmt, args...)				\</div><div class='ctx'> 	do { if ((md)-&gt;queue) blk_add_trace_msg((md)-&gt;queue, "raid1 " fmt, ##args); } while (0)</div><div class='ctx'> </div><div class='add'>+#define RAID_1_10_NAME "raid1"</div><div class='ctx'> #include "raid1-10.c"</div><div class='ctx'> </div><div class='ctx'> #define START(node) ((node)-&gt;start)</div><div class='hunk'>@@ -609,7 +610,6 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect</div><div class='ctx'> 	int choose_first;</div><div class='ctx'> 	int choose_next_idle;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Check if we can balance. We can balance on the whole</div><div class='ctx'> 	 * device if no resync is going on, or below the resync window.</div><div class='hunk'>@@ -642,7 +642,7 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect</div><div class='ctx'> 		unsigned int pending;</div><div class='ctx'> 		bool nonrot;</div><div class='ctx'> </div><div class='del'>-		rdev = rcu_dereference(conf-&gt;mirrors[disk].rdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[disk].rdev;</div><div class='ctx'> 		if (r1_bio-&gt;bios[disk] == IO_BLOCKED</div><div class='ctx'> 		    || rdev == NULL</div><div class='ctx'> 		    || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -773,7 +773,7 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (best_disk &gt;= 0) {</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;mirrors[best_disk].rdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[best_disk].rdev;</div><div class='ctx'> 		if (!rdev)</div><div class='ctx'> 			goto retry;</div><div class='ctx'> 		atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='hunk'>@@ -784,7 +784,6 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect</div><div class='ctx'> </div><div class='ctx'> 		conf-&gt;mirrors[best_disk].next_seq_sect = this_sector + sectors;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	*max_sectors = sectors;</div><div class='ctx'> </div><div class='ctx'> 	return best_disk;</div><div class='hunk'>@@ -1126,8 +1125,6 @@ static void alloc_behind_master_bio(struct r1bio *r1_bio,</div><div class='ctx'> </div><div class='ctx'> 	behind_bio = bio_alloc_bioset(NULL, vcnt, 0, GFP_NOIO,</div><div class='ctx'> 				      &amp;r1_bio-&gt;mddev-&gt;bio_set);</div><div class='del'>-	if (!behind_bio)</div><div class='del'>-		return;</div><div class='ctx'> </div><div class='ctx'> 	/* discard op, we don't support writezero/writesame yet */</div><div class='ctx'> 	if (!bio_has_data(bio)) {</div><div class='hunk'>@@ -1235,14 +1232,12 @@ static void raid1_read_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> </div><div class='ctx'> 	if (r1bio_existed) {</div><div class='ctx'> 		/* Need to get the block device name carefully */</div><div class='del'>-		struct md_rdev *rdev;</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;mirrors[r1_bio-&gt;read_disk].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;mirrors[r1_bio-&gt;read_disk].rdev;</div><div class='add'>+</div><div class='ctx'> 		if (rdev)</div><div class='ctx'> 			snprintf(b, sizeof(b), "%pg", rdev-&gt;bdev);</div><div class='ctx'> 		else</div><div class='ctx'> 			strcpy(b, "???");</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1396,10 +1391,9 @@ static void raid1_write_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> </div><div class='ctx'> 	disks = conf-&gt;raid_disks * 2;</div><div class='ctx'> 	blocked_rdev = NULL;</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	max_sectors = r1_bio-&gt;sectors;</div><div class='ctx'> 	for (i = 0;  i &lt; disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;mirrors[i].rdev;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The write-behind io is only attempted on drives marked as</div><div class='hunk'>@@ -1465,7 +1459,6 @@ static void raid1_write_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> 		}</div><div class='ctx'> 		r1_bio-&gt;bios[i] = bio;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(blocked_rdev)) {</div><div class='ctx'> 		/* Wait for this device to become unblocked */</div><div class='hunk'>@@ -1617,15 +1610,16 @@ static void raid1_status(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> 	struct r1conf *conf = mddev-&gt;private;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	lockdep_assert_held(&amp;mddev-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	seq_printf(seq, " [%d/%d] [", conf-&gt;raid_disks,</div><div class='ctx'> 		   conf-&gt;raid_disks - mddev-&gt;degraded);</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = READ_ONCE(conf-&gt;mirrors[i].rdev);</div><div class='add'>+</div><div class='ctx'> 		seq_printf(seq, "%s",</div><div class='ctx'> 			   rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) ? "U" : "_");</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	seq_printf(seq, "]");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1691,16 +1685,15 @@ static void print_conf(struct r1conf *conf)</div><div class='ctx'> 	pr_debug(" --- wd:%d rd:%d\n", conf-&gt;raid_disks - conf-&gt;mddev-&gt;degraded,</div><div class='ctx'> 		 conf-&gt;raid_disks);</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='add'>+	lockdep_assert_held(&amp;conf-&gt;mddev-&gt;reconfig_mutex);</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;mirrors[i].rdev;</div><div class='ctx'> 		if (rdev)</div><div class='ctx'> 			pr_debug(" disk %d, wo:%d, o:%d, dev:%pg\n",</div><div class='ctx'> 				 i, !test_bit(In_sync, &amp;rdev-&gt;flags),</div><div class='ctx'> 				 !test_bit(Faulty, &amp;rdev-&gt;flags),</div><div class='ctx'> 				 rdev-&gt;bdev);</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void close_sync(struct r1conf *conf)</div><div class='hunk'>@@ -1810,7 +1803,7 @@ static int raid1_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (rdev-&gt;saved_raid_disk &lt; 0)</div><div class='ctx'> 				conf-&gt;fullsync = 1;</div><div class='del'>-			rcu_assign_pointer(p-&gt;rdev, rdev);</div><div class='add'>+			WRITE_ONCE(p-&gt;rdev, rdev);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (test_bit(WantReplacement, &amp;p-&gt;rdev-&gt;flags) &amp;&amp;</div><div class='hunk'>@@ -1826,7 +1819,7 @@ static int raid1_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 		rdev-&gt;raid_disk = repl_slot;</div><div class='ctx'> 		err = 0;</div><div class='ctx'> 		conf-&gt;fullsync = 1;</div><div class='del'>-		rcu_assign_pointer(p[conf-&gt;raid_disks].rdev, rdev);</div><div class='add'>+		WRITE_ONCE(p[conf-&gt;raid_disks].rdev, rdev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	print_conf(conf);</div><div class='hunk'>@@ -1862,16 +1855,7 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			err = -EBUSY;</div><div class='ctx'> 			goto abort;</div><div class='ctx'> 		}</div><div class='del'>-		p-&gt;rdev = NULL;</div><div class='del'>-		if (!test_bit(RemoveSynchronized, &amp;rdev-&gt;flags)) {</div><div class='del'>-			synchronize_rcu();</div><div class='del'>-			if (atomic_read(&amp;rdev-&gt;nr_pending)) {</div><div class='del'>-				/* lost the race, try later */</div><div class='del'>-				err = -EBUSY;</div><div class='del'>-				p-&gt;rdev = rdev;</div><div class='del'>-				goto abort;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+		WRITE_ONCE(p-&gt;rdev, NULL);</div><div class='ctx'> 		if (conf-&gt;mirrors[conf-&gt;raid_disks + number].rdev) {</div><div class='ctx'> 			/* We just removed a device that is being replaced.</div><div class='ctx'> 			 * Move down the replacement.  We drain all IO before</div><div class='hunk'>@@ -1892,7 +1876,7 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 				goto abort;</div><div class='ctx'> 			}</div><div class='ctx'> 			clear_bit(Replacement, &amp;repl-&gt;flags);</div><div class='del'>-			p-&gt;rdev = repl;</div><div class='add'>+			WRITE_ONCE(p-&gt;rdev, repl);</div><div class='ctx'> 			conf-&gt;mirrors[conf-&gt;raid_disks + number].rdev = NULL;</div><div class='ctx'> 			unfreeze_array(conf);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1984,12 +1968,12 @@ static void end_sync_write(struct bio *bio)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int r1_sync_page_io(struct md_rdev *rdev, sector_t sector,</div><div class='del'>-			   int sectors, struct page *page, int rw)</div><div class='add'>+			   int sectors, struct page *page, blk_opf_t rw)</div><div class='ctx'> {</div><div class='ctx'> 	if (sync_page_io(rdev, sector, sectors &lt;&lt; 9, page, rw, false))</div><div class='ctx'> 		/* success */</div><div class='ctx'> 		return 1;</div><div class='del'>-	if (rw == WRITE) {</div><div class='add'>+	if (rw == REQ_OP_WRITE) {</div><div class='ctx'> 		set_bit(WriteErrorSeen, &amp;rdev-&gt;flags);</div><div class='ctx'> 		if (!test_and_set_bit(WantReplacement,</div><div class='ctx'> 				      &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -2106,7 +2090,7 @@ static int fix_sync_read_error(struct r1bio *r1_bio)</div><div class='ctx'> 			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (r1_sync_page_io(rdev, sect, s,</div><div class='ctx'> 					    pages[idx],</div><div class='del'>-					    WRITE) == 0) {</div><div class='add'>+					    REQ_OP_WRITE) == 0) {</div><div class='ctx'> 				r1_bio-&gt;bios[d]-&gt;bi_end_io = NULL;</div><div class='ctx'> 				rdev_dec_pending(rdev, mddev);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -2121,7 +2105,7 @@ static int fix_sync_read_error(struct r1bio *r1_bio)</div><div class='ctx'> 			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (r1_sync_page_io(rdev, sect, s,</div><div class='ctx'> 					    pages[idx],</div><div class='del'>-					    READ) != 0)</div><div class='add'>+					    REQ_OP_READ) != 0)</div><div class='ctx'> 				atomic_add(s, &amp;rdev-&gt;corrected_errors);</div><div class='ctx'> 		}</div><div class='ctx'> 		sectors -= s;</div><div class='hunk'>@@ -2272,16 +2256,24 @@ static void sync_request_write(struct mddev *mddev, struct r1bio *r1_bio)</div><div class='ctx'>  *	3.	Performs writes following reads for array synchronising.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static void fix_read_error(struct r1conf *conf, int read_disk,</div><div class='del'>-			   sector_t sect, int sectors)</div><div class='add'>+static void fix_read_error(struct r1conf *conf, struct r1bio *r1_bio)</div><div class='ctx'> {</div><div class='add'>+	sector_t sect = r1_bio-&gt;sector;</div><div class='add'>+	int sectors = r1_bio-&gt;sectors;</div><div class='add'>+	int read_disk = r1_bio-&gt;read_disk;</div><div class='ctx'> 	struct mddev *mddev = conf-&gt;mddev;</div><div class='add'>+	struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[read_disk].rdev);</div><div class='add'>+</div><div class='add'>+	if (exceed_read_errors(mddev, rdev)) {</div><div class='add'>+		r1_bio-&gt;bios[r1_bio-&gt;read_disk] = IO_BLOCKED;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	while(sectors) {</div><div class='ctx'> 		int s = sectors;</div><div class='ctx'> 		int d = read_disk;</div><div class='ctx'> 		int success = 0;</div><div class='ctx'> 		int start;</div><div class='del'>-		struct md_rdev *rdev;</div><div class='ctx'> </div><div class='ctx'> 		if (s &gt; (PAGE_SIZE&gt;&gt;9))</div><div class='ctx'> 			s = PAGE_SIZE &gt;&gt; 9;</div><div class='hunk'>@@ -2290,8 +2282,7 @@ static void fix_read_error(struct r1conf *conf, int read_disk,</div><div class='ctx'> 			sector_t first_bad;</div><div class='ctx'> 			int bad_sectors;</div><div class='ctx'> </div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (rdev &amp;&amp;</div><div class='ctx'> 			    (test_bit(In_sync, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 			     (!test_bit(Faulty, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='hunk'>@@ -2299,15 +2290,14 @@ static void fix_read_error(struct r1conf *conf, int read_disk,</div><div class='ctx'> 			    is_badblock(rdev, sect, s,</div><div class='ctx'> 					&amp;first_bad, &amp;bad_sectors) == 0) {</div><div class='ctx'> 				atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				if (sync_page_io(rdev, sect, s&lt;&lt;9,</div><div class='ctx'> 					 conf-&gt;tmppage, REQ_OP_READ, false))</div><div class='ctx'> 					success = 1;</div><div class='ctx'> 				rdev_dec_pending(rdev, mddev);</div><div class='ctx'> 				if (success)</div><div class='ctx'> 					break;</div><div class='del'>-			} else</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			d++;</div><div class='ctx'> 			if (d == conf-&gt;raid_disks * 2)</div><div class='ctx'> 				d = 0;</div><div class='hunk'>@@ -2326,31 +2316,26 @@ static void fix_read_error(struct r1conf *conf, int read_disk,</div><div class='ctx'> 			if (d==0)</div><div class='ctx'> 				d = conf-&gt;raid_disks * 2;</div><div class='ctx'> 			d--;</div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (rdev &amp;&amp;</div><div class='ctx'> 			    !test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 				atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				r1_sync_page_io(rdev, sect, s,</div><div class='del'>-						conf-&gt;tmppage, WRITE);</div><div class='add'>+						conf-&gt;tmppage, REQ_OP_WRITE);</div><div class='ctx'> 				rdev_dec_pending(rdev, mddev);</div><div class='del'>-			} else</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		d = start;</div><div class='ctx'> 		while (d != read_disk) {</div><div class='ctx'> 			if (d==0)</div><div class='ctx'> 				d = conf-&gt;raid_disks * 2;</div><div class='ctx'> 			d--;</div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (rdev &amp;&amp;</div><div class='ctx'> 			    !test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 				atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				if (r1_sync_page_io(rdev, sect, s,</div><div class='del'>-						    conf-&gt;tmppage, READ)) {</div><div class='add'>+						conf-&gt;tmppage, REQ_OP_READ)) {</div><div class='ctx'> 					atomic_add(s, &amp;rdev-&gt;corrected_errors);</div><div class='ctx'> 					pr_info("md/raid1:%s: read error corrected (%d sectors at %llu on %pg)\n",</div><div class='ctx'> 						mdname(mddev), s,</div><div class='hunk'>@@ -2359,8 +2344,7 @@ static void fix_read_error(struct r1conf *conf, int read_disk,</div><div class='ctx'> 						rdev-&gt;bdev);</div><div class='ctx'> 				}</div><div class='ctx'> 				rdev_dec_pending(rdev, mddev);</div><div class='del'>-			} else</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 		sectors -= s;</div><div class='ctx'> 		sect += s;</div><div class='hunk'>@@ -2530,8 +2514,7 @@ static void handle_read_error(struct r1conf *conf, struct r1bio *r1_bio)</div><div class='ctx'> 	if (mddev-&gt;ro == 0</div><div class='ctx'> 	    &amp;&amp; !test_bit(FailFast, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 		freeze_array(conf, 1);</div><div class='del'>-		fix_read_error(conf, r1_bio-&gt;read_disk,</div><div class='del'>-			       r1_bio-&gt;sector, r1_bio-&gt;sectors);</div><div class='add'>+		fix_read_error(conf, r1_bio);</div><div class='ctx'> 		unfreeze_array(conf);</div><div class='ctx'> 	} else if (mddev-&gt;ro == 0 &amp;&amp; test_bit(FailFast, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 		md_error(mddev, rdev);</div><div class='hunk'>@@ -2741,7 +2724,6 @@ static sector_t raid1_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> </div><div class='ctx'> 	r1_bio = raid1_alloc_init_r1buf(conf);</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If we get a correctably read error during resync or recovery,</div><div class='ctx'> 	 * we might want to read from a different device.  So we</div><div class='hunk'>@@ -2762,7 +2744,7 @@ static sector_t raid1_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 		struct md_rdev *rdev;</div><div class='ctx'> 		bio = r1_bio-&gt;bios[i];</div><div class='ctx'> </div><div class='del'>-		rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[i].rdev;</div><div class='ctx'> 		if (rdev == NULL ||</div><div class='ctx'> 		    test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 			if (i &lt; conf-&gt;raid_disks)</div><div class='hunk'>@@ -2820,7 +2802,6 @@ static sector_t raid1_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 				bio-&gt;bi_opf |= MD_FAILFAST;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	if (disk &lt; 0)</div><div class='ctx'> 		disk = wonly;</div><div class='ctx'> 	r1_bio-&gt;read_disk = disk;</div><div class='head'>diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c<br/>index a5927e98dc67..7412066ea22c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid10.c</a></div><div class='hunk'>@@ -19,6 +19,8 @@</div><div class='ctx'> #include &lt;linux/raid/md_p.h&gt;</div><div class='ctx'> #include &lt;trace/events/block.h&gt;</div><div class='ctx'> #include "md.h"</div><div class='add'>+</div><div class='add'>+#define RAID_1_10_NAME "raid10"</div><div class='ctx'> #include "raid10.h"</div><div class='ctx'> #include "raid0.h"</div><div class='ctx'> #include "md-bitmap.h"</div><div class='hunk'>@@ -743,7 +745,6 @@ static struct md_rdev *read_balance(struct r10conf *conf,</div><div class='ctx'> 	struct geom *geo = &amp;conf-&gt;geo;</div><div class='ctx'> </div><div class='ctx'> 	raid10_find_phys(conf, r10_bio);</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	best_dist_slot = -1;</div><div class='ctx'> 	min_pending = UINT_MAX;</div><div class='ctx'> 	best_dist_rdev = NULL;</div><div class='hunk'>@@ -775,18 +776,11 @@ static struct md_rdev *read_balance(struct r10conf *conf,</div><div class='ctx'> 		if (r10_bio-&gt;devs[slot].bio == IO_BLOCKED)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		disk = r10_bio-&gt;devs[slot].devnum;</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;mirrors[disk].replacement);</div><div class='add'>+		rdev = conf-&gt;mirrors[disk].replacement;</div><div class='ctx'> 		if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 		    r10_bio-&gt;devs[slot].addr + sectors &gt;</div><div class='del'>-		    rdev-&gt;recovery_offset) {</div><div class='del'>-			/*</div><div class='del'>-			 * Read replacement first to prevent reading both rdev</div><div class='del'>-			 * and replacement as NULL during replacement replace</div><div class='del'>-			 * rdev.</div><div class='del'>-			 */</div><div class='del'>-			smp_mb();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[disk].rdev);</div><div class='del'>-		}</div><div class='add'>+		    rdev-&gt;recovery_offset)</div><div class='add'>+			rdev = conf-&gt;mirrors[disk].rdev;</div><div class='ctx'> 		if (rdev == NULL ||</div><div class='ctx'> 		    test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -876,7 +870,6 @@ static struct md_rdev *read_balance(struct r10conf *conf,</div><div class='ctx'> 		r10_bio-&gt;read_slot = slot;</div><div class='ctx'> 	} else</div><div class='ctx'> 		rdev = NULL;</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	*max_sectors = best_good_sectors;</div><div class='ctx'> </div><div class='ctx'> 	return rdev;</div><div class='hunk'>@@ -1198,9 +1191,8 @@ static void raid10_read_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> 		 */</div><div class='ctx'> 		gfp = GFP_NOIO | __GFP_HIGH;</div><div class='ctx'> </div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		disk = r10_bio-&gt;devs[slot].devnum;</div><div class='del'>-		err_rdev = rcu_dereference(conf-&gt;mirrors[disk].rdev);</div><div class='add'>+		err_rdev = conf-&gt;mirrors[disk].rdev;</div><div class='ctx'> 		if (err_rdev)</div><div class='ctx'> 			snprintf(b, sizeof(b), "%pg", err_rdev-&gt;bdev);</div><div class='ctx'> 		else {</div><div class='hunk'>@@ -1208,7 +1200,6 @@ static void raid10_read_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> 			/* This never gets dereferenced */</div><div class='ctx'> 			err_rdev = r10_bio-&gt;devs[slot].rdev;</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!regular_request_wait(mddev, conf, bio, r10_bio-&gt;sectors))</div><div class='hunk'>@@ -1279,15 +1270,8 @@ static void raid10_write_one_disk(struct mddev *mddev, struct r10bio *r10_bio,</div><div class='ctx'> 	int devnum = r10_bio-&gt;devs[n_copy].devnum;</div><div class='ctx'> 	struct bio *mbio;</div><div class='ctx'> </div><div class='del'>-	if (replacement) {</div><div class='del'>-		rdev = conf-&gt;mirrors[devnum].replacement;</div><div class='del'>-		if (rdev == NULL) {</div><div class='del'>-			/* Replacement just got moved to main 'rdev' */</div><div class='del'>-			smp_mb();</div><div class='del'>-			rdev = conf-&gt;mirrors[devnum].rdev;</div><div class='del'>-		}</div><div class='del'>-	} else</div><div class='del'>-		rdev = conf-&gt;mirrors[devnum].rdev;</div><div class='add'>+	rdev = replacement ? conf-&gt;mirrors[devnum].replacement :</div><div class='add'>+			     conf-&gt;mirrors[devnum].rdev;</div><div class='ctx'> </div><div class='ctx'> 	mbio = bio_alloc_clone(rdev-&gt;bdev, bio, GFP_NOIO, &amp;mddev-&gt;bio_set);</div><div class='ctx'> 	if (replacement)</div><div class='hunk'>@@ -1321,25 +1305,6 @@ static void raid10_write_one_disk(struct mddev *mddev, struct r10bio *r10_bio,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct md_rdev *dereference_rdev_and_rrdev(struct raid10_info *mirror,</div><div class='del'>-						  struct md_rdev **prrdev)</div><div class='del'>-{</div><div class='del'>-	struct md_rdev *rdev, *rrdev;</div><div class='del'>-</div><div class='del'>-	rrdev = rcu_dereference(mirror-&gt;replacement);</div><div class='del'>-	/*</div><div class='del'>-	 * Read replacement first to prevent reading both rdev and</div><div class='del'>-	 * replacement as NULL during replacement replace rdev.</div><div class='del'>-	 */</div><div class='del'>-	smp_mb();</div><div class='del'>-	rdev = rcu_dereference(mirror-&gt;rdev);</div><div class='del'>-	if (rdev == rrdev)</div><div class='del'>-		rrdev = NULL;</div><div class='del'>-</div><div class='del'>-	*prrdev = rrdev;</div><div class='del'>-	return rdev;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void wait_blocked_dev(struct mddev *mddev, struct r10bio *r10_bio)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1348,11 +1313,11 @@ static void wait_blocked_dev(struct mddev *mddev, struct r10bio *r10_bio)</div><div class='ctx'> </div><div class='ctx'> retry_wait:</div><div class='ctx'> 	blocked_rdev = NULL;</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;copies; i++) {</div><div class='ctx'> 		struct md_rdev *rdev, *rrdev;</div><div class='ctx'> </div><div class='del'>-		rdev = dereference_rdev_and_rrdev(&amp;conf-&gt;mirrors[i], &amp;rrdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[i].rdev;</div><div class='add'>+		rrdev = conf-&gt;mirrors[i].replacement;</div><div class='ctx'> 		if (rdev &amp;&amp; unlikely(test_bit(Blocked, &amp;rdev-&gt;flags))) {</div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='ctx'> 			blocked_rdev = rdev;</div><div class='hunk'>@@ -1391,7 +1356,6 @@ retry_wait:</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(blocked_rdev)) {</div><div class='ctx'> 		/* Have to wait for this device to get unblocked, then retry */</div><div class='hunk'>@@ -1474,14 +1438,14 @@ static void raid10_write_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> </div><div class='ctx'> 	wait_blocked_dev(mddev, r10_bio);</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	max_sectors = r10_bio-&gt;sectors;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0;  i &lt; conf-&gt;copies; i++) {</div><div class='ctx'> 		int d = r10_bio-&gt;devs[i].devnum;</div><div class='ctx'> 		struct md_rdev *rdev, *rrdev;</div><div class='ctx'> </div><div class='del'>-		rdev = dereference_rdev_and_rrdev(&amp;conf-&gt;mirrors[d], &amp;rrdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[d].rdev;</div><div class='add'>+		rrdev = conf-&gt;mirrors[d].replacement;</div><div class='ctx'> 		if (rdev &amp;&amp; (test_bit(Faulty, &amp;rdev-&gt;flags)))</div><div class='ctx'> 			rdev = NULL;</div><div class='ctx'> 		if (rrdev &amp;&amp; (test_bit(Faulty, &amp;rrdev-&gt;flags)))</div><div class='hunk'>@@ -1535,7 +1499,6 @@ static void raid10_write_request(struct mddev *mddev, struct bio *bio,</div><div class='ctx'> 			atomic_inc(&amp;rrdev-&gt;nr_pending);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	if (max_sectors &lt; r10_bio-&gt;sectors)</div><div class='ctx'> 		r10_bio-&gt;sectors = max_sectors;</div><div class='hunk'>@@ -1625,17 +1588,8 @@ static void raid10_end_discard_request(struct bio *bio)</div><div class='ctx'> 		set_bit(R10BIO_Uptodate, &amp;r10_bio-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 	dev = find_bio_disk(conf, r10_bio, bio, &amp;slot, &amp;repl);</div><div class='del'>-	if (repl)</div><div class='del'>-		rdev = conf-&gt;mirrors[dev].replacement;</div><div class='del'>-	if (!rdev) {</div><div class='del'>-		/*</div><div class='del'>-		 * raid10_remove_disk uses smp_mb to make sure rdev is set to</div><div class='del'>-		 * replacement before setting replacement to NULL. It can read</div><div class='del'>-		 * rdev first without barrier protect even replacement is NULL</div><div class='del'>-		 */</div><div class='del'>-		smp_rmb();</div><div class='del'>-		rdev = conf-&gt;mirrors[dev].rdev;</div><div class='del'>-	}</div><div class='add'>+	rdev = repl ? conf-&gt;mirrors[dev].replacement :</div><div class='add'>+		      conf-&gt;mirrors[dev].rdev;</div><div class='ctx'> </div><div class='ctx'> 	raid_end_discard_bio(r10_bio);</div><div class='ctx'> 	rdev_dec_pending(rdev, conf-&gt;mddev);</div><div class='hunk'>@@ -1785,11 +1739,11 @@ retry_discard:</div><div class='ctx'> 	 * inc refcount on their rdev.  Record them by setting</div><div class='ctx'> 	 * bios[x] to bio</div><div class='ctx'> 	 */</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (disk = 0; disk &lt; geo-&gt;raid_disks; disk++) {</div><div class='ctx'> 		struct md_rdev *rdev, *rrdev;</div><div class='ctx'> </div><div class='del'>-		rdev = dereference_rdev_and_rrdev(&amp;conf-&gt;mirrors[disk], &amp;rrdev);</div><div class='add'>+		rdev = conf-&gt;mirrors[disk].rdev;</div><div class='add'>+		rrdev = conf-&gt;mirrors[disk].replacement;</div><div class='ctx'> 		r10_bio-&gt;devs[disk].bio = NULL;</div><div class='ctx'> 		r10_bio-&gt;devs[disk].repl_bio = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -1809,7 +1763,6 @@ retry_discard:</div><div class='ctx'> 			atomic_inc(&amp;rrdev-&gt;nr_pending);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	atomic_set(&amp;r10_bio-&gt;remaining, 1);</div><div class='ctx'> 	for (disk = 0; disk &lt; geo-&gt;raid_disks; disk++) {</div><div class='hunk'>@@ -1939,6 +1892,8 @@ static void raid10_status(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> 	struct r10conf *conf = mddev-&gt;private;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	lockdep_assert_held(&amp;mddev-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	if (conf-&gt;geo.near_copies &lt; conf-&gt;geo.raid_disks)</div><div class='ctx'> 		seq_printf(seq, " %dK chunks", mddev-&gt;chunk_sectors / 2);</div><div class='ctx'> 	if (conf-&gt;geo.near_copies &gt; 1)</div><div class='hunk'>@@ -1953,12 +1908,11 @@ static void raid10_status(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> 	}</div><div class='ctx'> 	seq_printf(seq, " [%d/%d] [", conf-&gt;geo.raid_disks,</div><div class='ctx'> 					conf-&gt;geo.raid_disks - mddev-&gt;degraded);</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;geo.raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = READ_ONCE(conf-&gt;mirrors[i].rdev);</div><div class='add'>+</div><div class='ctx'> 		seq_printf(seq, "%s", rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) ? "U" : "_");</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	seq_printf(seq, "]");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1980,7 +1934,6 @@ static int _enough(struct r10conf *conf, int previous, int ignore)</div><div class='ctx'> 		ncopies = conf-&gt;geo.near_copies;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	do {</div><div class='ctx'> 		int n = conf-&gt;copies;</div><div class='ctx'> 		int cnt = 0;</div><div class='hunk'>@@ -1988,7 +1941,7 @@ static int _enough(struct r10conf *conf, int previous, int ignore)</div><div class='ctx'> 		while (n--) {</div><div class='ctx'> 			struct md_rdev *rdev;</div><div class='ctx'> 			if (this != ignore &amp;&amp;</div><div class='del'>-			    (rdev = rcu_dereference(conf-&gt;mirrors[this].rdev)) &amp;&amp;</div><div class='add'>+			    (rdev = conf-&gt;mirrors[this].rdev) &amp;&amp;</div><div class='ctx'> 			    test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='ctx'> 				cnt++;</div><div class='ctx'> 			this = (this+1) % disks;</div><div class='hunk'>@@ -1999,7 +1952,6 @@ static int _enough(struct r10conf *conf, int previous, int ignore)</div><div class='ctx'> 	} while (first != 0);</div><div class='ctx'> 	has_enough = 1;</div><div class='ctx'> out:</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	return has_enough;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2072,8 +2024,7 @@ static void print_conf(struct r10conf *conf)</div><div class='ctx'> 	pr_debug(" --- wd:%d rd:%d\n", conf-&gt;geo.raid_disks - conf-&gt;mddev-&gt;degraded,</div><div class='ctx'> 		 conf-&gt;geo.raid_disks);</div><div class='ctx'> </div><div class='del'>-	/* This is only called with -&gt;reconfix_mutex held, so</div><div class='del'>-	 * rcu protection of rdev is not needed */</div><div class='add'>+	lockdep_assert_held(&amp;conf-&gt;mddev-&gt;reconfig_mutex);</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;geo.raid_disks; i++) {</div><div class='ctx'> 		rdev = conf-&gt;mirrors[i].rdev;</div><div class='ctx'> 		if (rdev)</div><div class='hunk'>@@ -2190,7 +2141,7 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 		err = 0;</div><div class='ctx'> 		if (rdev-&gt;saved_raid_disk != mirror)</div><div class='ctx'> 			conf-&gt;fullsync = 1;</div><div class='del'>-		rcu_assign_pointer(p-&gt;rdev, rdev);</div><div class='add'>+		WRITE_ONCE(p-&gt;rdev, rdev);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2204,7 +2155,7 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			disk_stack_limits(mddev-&gt;gendisk, rdev-&gt;bdev,</div><div class='ctx'> 					  rdev-&gt;data_offset &lt;&lt; 9);</div><div class='ctx'> 		conf-&gt;fullsync = 1;</div><div class='del'>-		rcu_assign_pointer(p-&gt;replacement, rdev);</div><div class='add'>+		WRITE_ONCE(p-&gt;replacement, rdev);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	print_conf(conf);</div><div class='hunk'>@@ -2246,24 +2197,12 @@ static int raid10_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 		err = -EBUSY;</div><div class='ctx'> 		goto abort;</div><div class='ctx'> 	}</div><div class='del'>-	*rdevp = NULL;</div><div class='del'>-	if (!test_bit(RemoveSynchronized, &amp;rdev-&gt;flags)) {</div><div class='del'>-		synchronize_rcu();</div><div class='del'>-		if (atomic_read(&amp;rdev-&gt;nr_pending)) {</div><div class='del'>-			/* lost the race, try later */</div><div class='del'>-			err = -EBUSY;</div><div class='del'>-			*rdevp = rdev;</div><div class='del'>-			goto abort;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	WRITE_ONCE(*rdevp, NULL);</div><div class='ctx'> 	if (p-&gt;replacement) {</div><div class='ctx'> 		/* We must have just cleared 'rdev' */</div><div class='del'>-		p-&gt;rdev = p-&gt;replacement;</div><div class='add'>+		WRITE_ONCE(p-&gt;rdev, p-&gt;replacement);</div><div class='ctx'> 		clear_bit(Replacement, &amp;p-&gt;replacement-&gt;flags);</div><div class='del'>-		smp_mb(); /* Make sure other CPUs may see both as identical</div><div class='del'>-			   * but will never see neither -- if they are careful.</div><div class='del'>-			   */</div><div class='del'>-		p-&gt;replacement = NULL;</div><div class='add'>+		WRITE_ONCE(p-&gt;replacement, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	clear_bit(WantReplacement, &amp;rdev-&gt;flags);</div><div class='hunk'>@@ -2655,42 +2594,6 @@ static void recovery_request_write(struct mddev *mddev, struct r10bio *r10_bio)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Used by fix_read_error() to decay the per rdev read_errors.</div><div class='del'>- * We halve the read error count for every hour that has elapsed</div><div class='del'>- * since the last recorded read error.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-static void check_decay_read_errors(struct mddev *mddev, struct md_rdev *rdev)</div><div class='del'>-{</div><div class='del'>-	long cur_time_mon;</div><div class='del'>-	unsigned long hours_since_last;</div><div class='del'>-	unsigned int read_errors = atomic_read(&amp;rdev-&gt;read_errors);</div><div class='del'>-</div><div class='del'>-	cur_time_mon = ktime_get_seconds();</div><div class='del'>-</div><div class='del'>-	if (rdev-&gt;last_read_error == 0) {</div><div class='del'>-		/* first time we've seen a read error */</div><div class='del'>-		rdev-&gt;last_read_error = cur_time_mon;</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	hours_since_last = (long)(cur_time_mon -</div><div class='del'>-			    rdev-&gt;last_read_error) / 3600;</div><div class='del'>-</div><div class='del'>-	rdev-&gt;last_read_error = cur_time_mon;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * if hours_since_last is &gt; the number of bits in read_errors</div><div class='del'>-	 * just set read errors to 0. We do this to avoid</div><div class='del'>-	 * overflowing the shift of read_errors by hours_since_last.</div><div class='del'>-	 */</div><div class='del'>-	if (hours_since_last &gt;= 8 * sizeof(read_errors))</div><div class='del'>-		atomic_set(&amp;rdev-&gt;read_errors, 0);</div><div class='del'>-	else</div><div class='del'>-		atomic_set(&amp;rdev-&gt;read_errors, read_errors &gt;&gt; hours_since_last);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int r10_sync_page_io(struct md_rdev *rdev, sector_t sector,</div><div class='ctx'> 			    int sectors, struct page *page, enum req_op op)</div><div class='ctx'> {</div><div class='hunk'>@@ -2728,7 +2631,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 	int sect = 0; /* Offset from r10_bio-&gt;sector */</div><div class='ctx'> 	int sectors = r10_bio-&gt;sectors, slot = r10_bio-&gt;read_slot;</div><div class='ctx'> 	struct md_rdev *rdev;</div><div class='del'>-	int max_read_errors = atomic_read(&amp;mddev-&gt;max_corr_read_errors);</div><div class='ctx'> 	int d = r10_bio-&gt;devs[slot].devnum;</div><div class='ctx'> </div><div class='ctx'> 	/* still own a reference to this rdev, so it cannot</div><div class='hunk'>@@ -2741,15 +2643,7 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 		   more fix_read_error() attempts */</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	check_decay_read_errors(mddev, rdev);</div><div class='del'>-	atomic_inc(&amp;rdev-&gt;read_errors);</div><div class='del'>-	if (atomic_read(&amp;rdev-&gt;read_errors) &gt; max_read_errors) {</div><div class='del'>-		pr_notice("md/raid10:%s: %pg: Raid device exceeded read_error threshold [cur %d:max %d]\n",</div><div class='del'>-			  mdname(mddev), rdev-&gt;bdev,</div><div class='del'>-			  atomic_read(&amp;rdev-&gt;read_errors), max_read_errors);</div><div class='del'>-		pr_notice("md/raid10:%s: %pg: Failing raid device\n",</div><div class='del'>-			  mdname(mddev), rdev-&gt;bdev);</div><div class='del'>-		md_error(mddev, rdev);</div><div class='add'>+	if (exceed_read_errors(mddev, rdev)) {</div><div class='ctx'> 		r10_bio-&gt;devs[slot].bio = IO_BLOCKED;</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2763,20 +2657,18 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 		if (s &gt; (PAGE_SIZE&gt;&gt;9))</div><div class='ctx'> 			s = PAGE_SIZE &gt;&gt; 9;</div><div class='ctx'> </div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		do {</div><div class='ctx'> 			sector_t first_bad;</div><div class='ctx'> 			int bad_sectors;</div><div class='ctx'> </div><div class='ctx'> 			d = r10_bio-&gt;devs[sl].devnum;</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (rdev &amp;&amp;</div><div class='ctx'> 			    test_bit(In_sync, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 			    !test_bit(Faulty, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 			    is_badblock(rdev, r10_bio-&gt;devs[sl].addr + sect, s,</div><div class='ctx'> 					&amp;first_bad, &amp;bad_sectors) == 0) {</div><div class='ctx'> 				atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				success = sync_page_io(rdev,</div><div class='ctx'> 						       r10_bio-&gt;devs[sl].addr +</div><div class='ctx'> 						       sect,</div><div class='hunk'>@@ -2784,7 +2676,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 						       conf-&gt;tmppage,</div><div class='ctx'> 						       REQ_OP_READ, false);</div><div class='ctx'> 				rdev_dec_pending(rdev, mddev);</div><div class='del'>-				rcu_read_lock();</div><div class='ctx'> 				if (success)</div><div class='ctx'> 					break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -2792,7 +2683,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 			if (sl == conf-&gt;copies)</div><div class='ctx'> 				sl = 0;</div><div class='ctx'> 		} while (sl != slot);</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 		if (!success) {</div><div class='ctx'> 			/* Cannot read from anywhere, just mark the block</div><div class='hunk'>@@ -2816,20 +2706,18 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> </div><div class='ctx'> 		start = sl;</div><div class='ctx'> 		/* write it back and re-read */</div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		while (sl != slot) {</div><div class='ctx'> 			if (sl==0)</div><div class='ctx'> 				sl = conf-&gt;copies;</div><div class='ctx'> 			sl--;</div><div class='ctx'> 			d = r10_bio-&gt;devs[sl].devnum;</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (!rdev ||</div><div class='ctx'> 			    test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 			    !test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			if (r10_sync_page_io(rdev,</div><div class='ctx'> 					     r10_bio-&gt;devs[sl].addr +</div><div class='ctx'> 					     sect,</div><div class='hunk'>@@ -2848,7 +2736,6 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 					  rdev-&gt;bdev);</div><div class='ctx'> 			}</div><div class='ctx'> 			rdev_dec_pending(rdev, mddev);</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 		}</div><div class='ctx'> 		sl = start;</div><div class='ctx'> 		while (sl != slot) {</div><div class='hunk'>@@ -2856,14 +2743,13 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 				sl = conf-&gt;copies;</div><div class='ctx'> 			sl--;</div><div class='ctx'> 			d = r10_bio-&gt;devs[sl].devnum;</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (!rdev ||</div><div class='ctx'> 			    test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 			    !test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			switch (r10_sync_page_io(rdev,</div><div class='ctx'> 					     r10_bio-&gt;devs[sl].addr +</div><div class='ctx'> 					     sect,</div><div class='hunk'>@@ -2891,9 +2777,7 @@ static void fix_read_error(struct r10conf *conf, struct mddev *mddev, struct r10</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			rdev_dec_pending(rdev, mddev);</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 		sectors -= s;</div><div class='ctx'> 		sect += s;</div><div class='hunk'>@@ -3367,14 +3251,13 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 				/* Completed a full sync so the replacements</div><div class='ctx'> 				 * are now fully recovered.</div><div class='ctx'> 				 */</div><div class='del'>-				rcu_read_lock();</div><div class='ctx'> 				for (i = 0; i &lt; conf-&gt;geo.raid_disks; i++) {</div><div class='ctx'> 					struct md_rdev *rdev =</div><div class='del'>-						rcu_dereference(conf-&gt;mirrors[i].replacement);</div><div class='add'>+						conf-&gt;mirrors[i].replacement;</div><div class='add'>+</div><div class='ctx'> 					if (rdev)</div><div class='ctx'> 						rdev-&gt;recovery_offset = MaxSector;</div><div class='ctx'> 				}</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 			}</div><div class='ctx'> 			conf-&gt;fullsync = 0;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3455,9 +3338,8 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 			struct raid10_info *mirror = &amp;conf-&gt;mirrors[i];</div><div class='ctx'> 			struct md_rdev *mrdev, *mreplace;</div><div class='ctx'> </div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			mrdev = rcu_dereference(mirror-&gt;rdev);</div><div class='del'>-			mreplace = rcu_dereference(mirror-&gt;replacement);</div><div class='add'>+			mrdev = mirror-&gt;rdev;</div><div class='add'>+			mreplace = mirror-&gt;replacement;</div><div class='ctx'> </div><div class='ctx'> 			if (mrdev &amp;&amp; (test_bit(Faulty, &amp;mrdev-&gt;flags) ||</div><div class='ctx'> 			    test_bit(In_sync, &amp;mrdev-&gt;flags)))</div><div class='hunk'>@@ -3465,22 +3347,18 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 			if (mreplace &amp;&amp; test_bit(Faulty, &amp;mreplace-&gt;flags))</div><div class='ctx'> 				mreplace = NULL;</div><div class='ctx'> </div><div class='del'>-			if (!mrdev &amp;&amp; !mreplace) {</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			if (!mrdev &amp;&amp; !mreplace)</div><div class='ctx'> 				continue;</div><div class='del'>-			}</div><div class='ctx'> </div><div class='ctx'> 			still_degraded = 0;</div><div class='ctx'> 			/* want to reconstruct this device */</div><div class='ctx'> 			rb2 = r10_bio;</div><div class='ctx'> 			sect = raid10_find_virt(conf, sector_nr, i);</div><div class='del'>-			if (sect &gt;= mddev-&gt;resync_max_sectors) {</div><div class='add'>+			if (sect &gt;= mddev-&gt;resync_max_sectors)</div><div class='ctx'> 				/* last stripe is not complete - don't</div><div class='ctx'> 				 * try to recover this sector.</div><div class='ctx'> 				 */</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				continue;</div><div class='del'>-			}</div><div class='ctx'> 			/* Unless we are doing a full sync, or a replacement</div><div class='ctx'> 			 * we only need to recover the block if it is set in</div><div class='ctx'> 			 * the bitmap</div><div class='hunk'>@@ -3496,14 +3374,12 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 				 * that there will never be anything to do here</div><div class='ctx'> 				 */</div><div class='ctx'> 				chunks_skipped = -1;</div><div class='del'>-				rcu_read_unlock();</div><div class='ctx'> 				continue;</div><div class='ctx'> 			}</div><div class='ctx'> 			if (mrdev)</div><div class='ctx'> 				atomic_inc(&amp;mrdev-&gt;nr_pending);</div><div class='ctx'> 			if (mreplace)</div><div class='ctx'> 				atomic_inc(&amp;mreplace-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 			r10_bio = raid10_alloc_init_r10buf(conf);</div><div class='ctx'> 			r10_bio-&gt;state = 0;</div><div class='hunk'>@@ -3522,10 +3398,9 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 			/* Need to check if the array will still be</div><div class='ctx'> 			 * degraded</div><div class='ctx'> 			 */</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 			for (j = 0; j &lt; conf-&gt;geo.raid_disks; j++) {</div><div class='del'>-				struct md_rdev *rdev = rcu_dereference(</div><div class='del'>-					conf-&gt;mirrors[j].rdev);</div><div class='add'>+				struct md_rdev *rdev = conf-&gt;mirrors[j].rdev;</div><div class='add'>+</div><div class='ctx'> 				if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='ctx'> 					still_degraded = 1;</div><div class='ctx'> 					break;</div><div class='hunk'>@@ -3540,8 +3415,7 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 				int k;</div><div class='ctx'> 				int d = r10_bio-&gt;devs[j].devnum;</div><div class='ctx'> 				sector_t from_addr, to_addr;</div><div class='del'>-				struct md_rdev *rdev =</div><div class='del'>-					rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+				struct md_rdev *rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 				sector_t sector, first_bad;</div><div class='ctx'> 				int bad_sectors;</div><div class='ctx'> 				if (!rdev ||</div><div class='hunk'>@@ -3620,7 +3494,6 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 				atomic_inc(&amp;r10_bio-&gt;remaining);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			if (j == conf-&gt;copies) {</div><div class='ctx'> 				/* Cannot recover, so abort the recovery or</div><div class='ctx'> 				 * record a bad block */</div><div class='hunk'>@@ -3747,12 +3620,10 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> </div><div class='ctx'> 			bio = r10_bio-&gt;devs[i].bio;</div><div class='ctx'> 			bio-&gt;bi_status = BLK_STS_IOERR;</div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='del'>-			if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='add'>+			if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 				continue;</div><div class='del'>-			}</div><div class='add'>+</div><div class='ctx'> 			sector = r10_bio-&gt;devs[i].addr;</div><div class='ctx'> 			if (is_badblock(rdev, sector, max_sync,</div><div class='ctx'> 					&amp;first_bad, &amp;bad_sectors)) {</div><div class='hunk'>@@ -3762,7 +3633,6 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 					bad_sectors -= (sector - first_bad);</div><div class='ctx'> 					if (max_sync &gt; bad_sectors)</div><div class='ctx'> 						max_sync = bad_sectors;</div><div class='del'>-					rcu_read_unlock();</div><div class='ctx'> 					continue;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -3778,11 +3648,10 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 			bio_set_dev(bio, rdev-&gt;bdev);</div><div class='ctx'> 			count++;</div><div class='ctx'> </div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].replacement);</div><div class='del'>-			if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='del'>-				rcu_read_unlock();</div><div class='add'>+			rdev = conf-&gt;mirrors[d].replacement;</div><div class='add'>+			if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 				continue;</div><div class='del'>-			}</div><div class='add'>+</div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='ctx'> </div><div class='ctx'> 			/* Need to set up for writing to the replacement */</div><div class='hunk'>@@ -3799,7 +3668,6 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr,</div><div class='ctx'> 			bio-&gt;bi_iter.bi_sector = sector + rdev-&gt;data_offset;</div><div class='ctx'> 			bio_set_dev(bio, rdev-&gt;bdev);</div><div class='ctx'> 			count++;</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (count &lt; 2) {</div><div class='hunk'>@@ -4509,11 +4377,11 @@ static int calc_degraded(struct r10conf *conf)</div><div class='ctx'> 	int degraded, degraded2;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	degraded = 0;</div><div class='ctx'> 	/* 'prev' section first */</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;prev.raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;mirrors[i].rdev;</div><div class='add'>+</div><div class='ctx'> 		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			degraded++;</div><div class='ctx'> 		else if (!test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -4523,13 +4391,12 @@ static int calc_degraded(struct r10conf *conf)</div><div class='ctx'> 			 */</div><div class='ctx'> 			degraded++;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	if (conf-&gt;geo.raid_disks == conf-&gt;prev.raid_disks)</div><div class='ctx'> 		return degraded;</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	degraded2 = 0;</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;geo.raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;mirrors[i].rdev;</div><div class='add'>+</div><div class='ctx'> 		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			degraded2++;</div><div class='ctx'> 		else if (!test_bit(In_sync, &amp;rdev-&gt;flags)) {</div><div class='hunk'>@@ -4542,7 +4409,6 @@ static int calc_degraded(struct r10conf *conf)</div><div class='ctx'> 				degraded2++;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	if (degraded2 &gt; degraded)</div><div class='ctx'> 		return degraded2;</div><div class='ctx'> 	return degraded;</div><div class='hunk'>@@ -4974,16 +4840,15 @@ read_more:</div><div class='ctx'> 	blist = read_bio;</div><div class='ctx'> 	read_bio-&gt;bi_next = NULL;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (s = 0; s &lt; conf-&gt;copies*2; s++) {</div><div class='ctx'> 		struct bio *b;</div><div class='ctx'> 		int d = r10_bio-&gt;devs[s/2].devnum;</div><div class='ctx'> 		struct md_rdev *rdev2;</div><div class='ctx'> 		if (s&amp;1) {</div><div class='del'>-			rdev2 = rcu_dereference(conf-&gt;mirrors[d].replacement);</div><div class='add'>+			rdev2 = conf-&gt;mirrors[d].replacement;</div><div class='ctx'> 			b = r10_bio-&gt;devs[s/2].repl_bio;</div><div class='ctx'> 		} else {</div><div class='del'>-			rdev2 = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev2 = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			b = r10_bio-&gt;devs[s/2].bio;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (!rdev2 || test_bit(Faulty, &amp;rdev2-&gt;flags))</div><div class='hunk'>@@ -5017,7 +4882,6 @@ read_more:</div><div class='ctx'> 		sector_nr += len &gt;&gt; 9;</div><div class='ctx'> 		nr_sectors += len &gt;&gt; 9;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	r10_bio-&gt;sectors = nr_sectors;</div><div class='ctx'> </div><div class='ctx'> 	/* Now submit the read */</div><div class='hunk'>@@ -5070,20 +4934,17 @@ static void reshape_request_write(struct mddev *mddev, struct r10bio *r10_bio)</div><div class='ctx'> 		struct bio *b;</div><div class='ctx'> 		int d = r10_bio-&gt;devs[s/2].devnum;</div><div class='ctx'> 		struct md_rdev *rdev;</div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		if (s&amp;1) {</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].replacement);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].replacement;</div><div class='ctx'> 			b = r10_bio-&gt;devs[s/2].repl_bio;</div><div class='ctx'> 		} else {</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			b = r10_bio-&gt;devs[s/2].bio;</div><div class='ctx'> 		}</div><div class='del'>-		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags)) {</div><div class='del'>-			rcu_read_unlock();</div><div class='add'>+		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			continue;</div><div class='del'>-		}</div><div class='add'>+</div><div class='ctx'> 		atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 		md_sync_acct_bio(b, r10_bio-&gt;sectors);</div><div class='ctx'> 		atomic_inc(&amp;r10_bio-&gt;remaining);</div><div class='ctx'> 		b-&gt;bi_next = NULL;</div><div class='hunk'>@@ -5154,10 +5015,9 @@ static int handle_reshape_read_error(struct mddev *mddev,</div><div class='ctx'> 		if (s &gt; (PAGE_SIZE &gt;&gt; 9))</div><div class='ctx'> 			s = PAGE_SIZE &gt;&gt; 9;</div><div class='ctx'> </div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		while (!success) {</div><div class='ctx'> 			int d = r10b-&gt;devs[slot].devnum;</div><div class='del'>-			struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			struct md_rdev *rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			sector_t addr;</div><div class='ctx'> 			if (rdev == NULL ||</div><div class='ctx'> 			    test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='hunk'>@@ -5166,14 +5026,12 @@ static int handle_reshape_read_error(struct mddev *mddev,</div><div class='ctx'> </div><div class='ctx'> 			addr = r10b-&gt;devs[slot].addr + idx * PAGE_SIZE;</div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			success = sync_page_io(rdev,</div><div class='ctx'> 					       addr,</div><div class='ctx'> 					       s &lt;&lt; 9,</div><div class='ctx'> 					       pages[idx],</div><div class='ctx'> 					       REQ_OP_READ, false);</div><div class='ctx'> 			rdev_dec_pending(rdev, mddev);</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 			if (success)</div><div class='ctx'> 				break;</div><div class='ctx'> 		failed:</div><div class='hunk'>@@ -5183,7 +5041,6 @@ static int handle_reshape_read_error(struct mddev *mddev,</div><div class='ctx'> 			if (slot == first_slot)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 		if (!success) {</div><div class='ctx'> 			/* couldn't read this block, must give up */</div><div class='ctx'> 			set_bit(MD_RECOVERY_INTR,</div><div class='hunk'>@@ -5209,12 +5066,8 @@ static void end_reshape_write(struct bio *bio)</div><div class='ctx'> 	struct md_rdev *rdev = NULL;</div><div class='ctx'> </div><div class='ctx'> 	d = find_bio_disk(conf, r10_bio, bio, &amp;slot, &amp;repl);</div><div class='del'>-	if (repl)</div><div class='del'>-		rdev = conf-&gt;mirrors[d].replacement;</div><div class='del'>-	if (!rdev) {</div><div class='del'>-		smp_mb();</div><div class='del'>-		rdev = conf-&gt;mirrors[d].rdev;</div><div class='del'>-	}</div><div class='add'>+	rdev = repl ? conf-&gt;mirrors[d].replacement :</div><div class='add'>+		      conf-&gt;mirrors[d].rdev;</div><div class='ctx'> </div><div class='ctx'> 	if (bio-&gt;bi_status) {</div><div class='ctx'> 		/* FIXME should record badblock */</div><div class='hunk'>@@ -5249,18 +5102,16 @@ static void raid10_finish_reshape(struct mddev *mddev)</div><div class='ctx'> 		mddev-&gt;resync_max_sectors = mddev-&gt;array_sectors;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		int d;</div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		for (d = conf-&gt;geo.raid_disks ;</div><div class='ctx'> 		     d &lt; conf-&gt;geo.raid_disks - mddev-&gt;delta_disks;</div><div class='ctx'> 		     d++) {</div><div class='del'>-			struct md_rdev *rdev = rcu_dereference(conf-&gt;mirrors[d].rdev);</div><div class='add'>+			struct md_rdev *rdev = conf-&gt;mirrors[d].rdev;</div><div class='ctx'> 			if (rdev)</div><div class='ctx'> 				clear_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;mirrors[d].replacement);</div><div class='add'>+			rdev = conf-&gt;mirrors[d].replacement;</div><div class='ctx'> 			if (rdev)</div><div class='ctx'> 				clear_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 	}</div><div class='ctx'> 	mddev-&gt;layout = mddev-&gt;new_layout;</div><div class='ctx'> 	mddev-&gt;chunk_sectors = 1 &lt;&lt; conf-&gt;geo.chunk_shift;</div><div class='head'>diff --git a/drivers/md/raid5-cache.c b/drivers/md/raid5-cache.c<br/>index 6157f5beb9fe..874874fe4fa1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid5-cache.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid5-cache.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid5-cache.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5-cache.c</a></div><div class='hunk'>@@ -1890,28 +1890,22 @@ r5l_recovery_replay_one_stripe(struct r5conf *conf,</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* in case device is broken */</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;disks[disk_index].rdev);</div><div class='add'>+		rdev = conf-&gt;disks[disk_index].rdev;</div><div class='ctx'> 		if (rdev) {</div><div class='ctx'> 			atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			sync_page_io(rdev, sh-&gt;sector, PAGE_SIZE,</div><div class='ctx'> 				     sh-&gt;dev[disk_index].page, REQ_OP_WRITE,</div><div class='ctx'> 				     false);</div><div class='ctx'> 			rdev_dec_pending(rdev, rdev-&gt;mddev);</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 		}</div><div class='del'>-		rrdev = rcu_dereference(conf-&gt;disks[disk_index].replacement);</div><div class='add'>+		rrdev = conf-&gt;disks[disk_index].replacement;</div><div class='ctx'> 		if (rrdev) {</div><div class='ctx'> 			atomic_inc(&amp;rrdev-&gt;nr_pending);</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			sync_page_io(rrdev, sh-&gt;sector, PAGE_SIZE,</div><div class='ctx'> 				     sh-&gt;dev[disk_index].page, REQ_OP_WRITE,</div><div class='ctx'> 				     false);</div><div class='ctx'> 			rdev_dec_pending(rrdev, rrdev-&gt;mddev);</div><div class='del'>-			rcu_read_lock();</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 	}</div><div class='ctx'> 	ctx-&gt;data_parity_stripes++;</div><div class='ctx'> out:</div><div class='hunk'>@@ -2948,7 +2942,6 @@ bool r5c_big_stripe_cached(struct r5conf *conf, sector_t sect)</div><div class='ctx'> 	if (!log)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='del'>-	WARN_ON_ONCE(!rcu_read_lock_held());</div><div class='ctx'> 	tree_index = r5c_tree_index(conf, sect);</div><div class='ctx'> 	slot = radix_tree_lookup(&amp;log-&gt;big_stripe_tree, tree_index);</div><div class='ctx'> 	return slot != NULL;</div><div class='head'>diff --git a/drivers/md/raid5-ppl.c b/drivers/md/raid5-ppl.c<br/>index eaea57aee602..da4ba736c4f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid5-ppl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid5-ppl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid5-ppl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5-ppl.c</a></div><div class='hunk'>@@ -620,11 +620,9 @@ static void ppl_do_flush(struct ppl_io_unit *io)</div><div class='ctx'> 		struct md_rdev *rdev;</div><div class='ctx'> 		struct block_device *bdev = NULL;</div><div class='ctx'> </div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+		rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 		if (rdev &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			bdev = rdev-&gt;bdev;</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 		if (bdev) {</div><div class='ctx'> 			struct bio *bio;</div><div class='hunk'>@@ -882,9 +880,7 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e,</div><div class='ctx'> 				 (unsigned long long)r_sector, dd_idx,</div><div class='ctx'> 				 (unsigned long long)sector);</div><div class='ctx'> </div><div class='del'>-			/* Array has not started so rcu dereference is safe */</div><div class='del'>-			rdev = rcu_dereference_protected(</div><div class='del'>-					conf-&gt;disks[dd_idx].rdev, 1);</div><div class='add'>+			rdev = conf-&gt;disks[dd_idx].rdev;</div><div class='ctx'> 			if (!rdev || (!test_bit(In_sync, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 				      sector &gt;= rdev-&gt;recovery_offset)) {</div><div class='ctx'> 				pr_debug("%s:%*s data member disk %d missing\n",</div><div class='hunk'>@@ -936,9 +932,7 @@ static int ppl_recover_entry(struct ppl_log *log, struct ppl_header_entry *e,</div><div class='ctx'> 				0, &amp;disk, &amp;sh);</div><div class='ctx'> 		BUG_ON(sh.pd_idx != le32_to_cpu(e-&gt;parity_disk));</div><div class='ctx'> </div><div class='del'>-		/* Array has not started so rcu dereference is safe */</div><div class='del'>-		parity_rdev = rcu_dereference_protected(</div><div class='del'>-					conf-&gt;disks[sh.pd_idx].rdev, 1);</div><div class='add'>+		parity_rdev = conf-&gt;disks[sh.pd_idx].rdev;</div><div class='ctx'> </div><div class='ctx'> 		BUG_ON(parity_rdev-&gt;bdev-&gt;bd_dev != log-&gt;rdev-&gt;bdev-&gt;bd_dev);</div><div class='ctx'> 		pr_debug("%s:%*s write parity at sector %llu, disk %pg\n",</div><div class='hunk'>@@ -1404,9 +1398,7 @@ int ppl_init_log(struct r5conf *conf)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ppl_conf-&gt;count; i++) {</div><div class='ctx'> 		struct ppl_log *log = &amp;ppl_conf-&gt;child_logs[i];</div><div class='del'>-		/* Array has not started so rcu dereference is safe */</div><div class='del'>-		struct md_rdev *rdev =</div><div class='del'>-			rcu_dereference_protected(conf-&gt;disks[i].rdev, 1);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> </div><div class='ctx'> 		mutex_init(&amp;log-&gt;io_mutex);</div><div class='ctx'> 		spin_lock_init(&amp;log-&gt;io_list_lock);</div><div class='head'>diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c<br/>index dc031d42f53b..8497880135ee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5.c</a></div><div class='hunk'>@@ -36,7 +36,6 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/blkdev.h&gt;</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/kthread.h&gt;</div><div class='ctx'> #include &lt;linux/raid/pq.h&gt;</div><div class='ctx'> #include &lt;linux/async_tx.h&gt;</div><div class='hunk'>@@ -694,12 +693,12 @@ int raid5_calc_degraded(struct r5conf *conf)</div><div class='ctx'> 	int degraded, degraded2;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	degraded = 0;</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;previous_raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = READ_ONCE(conf-&gt;disks[i].rdev);</div><div class='add'>+</div><div class='ctx'> 		if (rdev &amp;&amp; test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;disks[i].replacement);</div><div class='add'>+			rdev = READ_ONCE(conf-&gt;disks[i].replacement);</div><div class='ctx'> 		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			degraded++;</div><div class='ctx'> 		else if (test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -717,15 +716,14 @@ int raid5_calc_degraded(struct r5conf *conf)</div><div class='ctx'> 			if (conf-&gt;raid_disks &gt;= conf-&gt;previous_raid_disks)</div><div class='ctx'> 				degraded++;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	if (conf-&gt;raid_disks == conf-&gt;previous_raid_disks)</div><div class='ctx'> 		return degraded;</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	degraded2 = 0;</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = READ_ONCE(conf-&gt;disks[i].rdev);</div><div class='add'>+</div><div class='ctx'> 		if (rdev &amp;&amp; test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;disks[i].replacement);</div><div class='add'>+			rdev = READ_ONCE(conf-&gt;disks[i].replacement);</div><div class='ctx'> 		if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			degraded2++;</div><div class='ctx'> 		else if (test_bit(In_sync, &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -739,7 +737,6 @@ int raid5_calc_degraded(struct r5conf *conf)</div><div class='ctx'> 			if (conf-&gt;raid_disks &lt;= conf-&gt;previous_raid_disks)</div><div class='ctx'> 				degraded2++;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	if (degraded2 &gt; degraded)</div><div class='ctx'> 		return degraded2;</div><div class='ctx'> 	return degraded;</div><div class='hunk'>@@ -1184,14 +1181,8 @@ again:</div><div class='ctx'> 		bi = &amp;dev-&gt;req;</div><div class='ctx'> 		rbi = &amp;dev-&gt;rreq; /* For writing to replacement */</div><div class='ctx'> </div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		rrdev = rcu_dereference(conf-&gt;disks[i].replacement);</div><div class='del'>-		smp_mb(); /* Ensure that if rrdev is NULL, rdev won't be */</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='del'>-		if (!rdev) {</div><div class='del'>-			rdev = rrdev;</div><div class='del'>-			rrdev = NULL;</div><div class='del'>-		}</div><div class='add'>+		rdev = conf-&gt;disks[i].rdev;</div><div class='add'>+		rrdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 		if (op_is_write(op)) {</div><div class='ctx'> 			if (replace_only)</div><div class='ctx'> 				rdev = NULL;</div><div class='hunk'>@@ -1212,7 +1203,6 @@ again:</div><div class='ctx'> 			rrdev = NULL;</div><div class='ctx'> 		if (rrdev)</div><div class='ctx'> 			atomic_inc(&amp;rrdev-&gt;nr_pending);</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 		/* We have already checked bad blocks for reads.  Now</div><div class='ctx'> 		 * need to check for writes.  We never accept write errors</div><div class='hunk'>@@ -2731,28 +2721,6 @@ static void shrink_stripes(struct r5conf *conf)</div><div class='ctx'> 	conf-&gt;slab_cache = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * This helper wraps rcu_dereference_protected() and can be used when</div><div class='del'>- * it is known that the nr_pending of the rdev is elevated.</div><div class='del'>- */</div><div class='del'>-static struct md_rdev *rdev_pend_deref(struct md_rdev __rcu *rdev)</div><div class='del'>-{</div><div class='del'>-	return rcu_dereference_protected(rdev,</div><div class='del'>-			atomic_read(&amp;rcu_access_pointer(rdev)-&gt;nr_pending));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * This helper wraps rcu_dereference_protected() and should be used</div><div class='del'>- * when it is known that the mddev_lock() is held. This is safe</div><div class='del'>- * seeing raid5_remove_disk() has the same lock held.</div><div class='del'>- */</div><div class='del'>-static struct md_rdev *rdev_mdlock_deref(struct mddev *mddev,</div><div class='del'>-					 struct md_rdev __rcu *rdev)</div><div class='del'>-{</div><div class='del'>-	return rcu_dereference_protected(rdev,</div><div class='del'>-			lockdep_is_held(&amp;mddev-&gt;reconfig_mutex));</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void raid5_end_read_request(struct bio * bi)</div><div class='ctx'> {</div><div class='ctx'> 	struct stripe_head *sh = bi-&gt;bi_private;</div><div class='hunk'>@@ -2778,9 +2746,9 @@ static void raid5_end_read_request(struct bio * bi)</div><div class='ctx'> 		 * In that case it moved down to 'rdev'.</div><div class='ctx'> 		 * rdev is not removed until all requests are finished.</div><div class='ctx'> 		 */</div><div class='del'>-		rdev = rdev_pend_deref(conf-&gt;disks[i].replacement);</div><div class='add'>+		rdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 	if (!rdev)</div><div class='del'>-		rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+		rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> </div><div class='ctx'> 	if (use_new_offset(conf, sh))</div><div class='ctx'> 		s = sh-&gt;sector + rdev-&gt;new_data_offset;</div><div class='hunk'>@@ -2893,11 +2861,11 @@ static void raid5_end_write_request(struct bio *bi)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0 ; i &lt; disks; i++) {</div><div class='ctx'> 		if (bi == &amp;sh-&gt;dev[i].req) {</div><div class='del'>-			rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+			rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		if (bi == &amp;sh-&gt;dev[i].rreq) {</div><div class='del'>-			rdev = rdev_pend_deref(conf-&gt;disks[i].replacement);</div><div class='add'>+			rdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 			if (rdev)</div><div class='ctx'> 				replacement = 1;</div><div class='ctx'> 			else</div><div class='hunk'>@@ -2905,7 +2873,7 @@ static void raid5_end_write_request(struct bio *bi)</div><div class='ctx'> 				 * replaced it.  rdev is not removed</div><div class='ctx'> 				 * until all requests are finished.</div><div class='ctx'> 				 */</div><div class='del'>-				rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+				rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3667,15 +3635,13 @@ handle_failed_stripe(struct r5conf *conf, struct stripe_head *sh,</div><div class='ctx'> 		int bitmap_end = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (test_bit(R5_ReadError, &amp;sh-&gt;dev[i].flags)) {</div><div class='del'>-			struct md_rdev *rdev;</div><div class='del'>-			rcu_read_lock();</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+			struct md_rdev *rdev = conf-&gt;disks[i].rdev;</div><div class='add'>+</div><div class='ctx'> 			if (rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 			    !test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 				atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='ctx'> 			else</div><div class='ctx'> 				rdev = NULL;</div><div class='del'>-			rcu_read_unlock();</div><div class='ctx'> 			if (rdev) {</div><div class='ctx'> 				if (!rdev_set_badblocks(</div><div class='ctx'> 					    rdev,</div><div class='hunk'>@@ -3793,16 +3759,17 @@ handle_failed_sync(struct r5conf *conf, struct stripe_head *sh,</div><div class='ctx'> 		/* During recovery devices cannot be removed, so</div><div class='ctx'> 		 * locking and refcounting of rdevs is not needed</div><div class='ctx'> 		 */</div><div class='del'>-		rcu_read_lock();</div><div class='ctx'> 		for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-			struct md_rdev *rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+			struct md_rdev *rdev = conf-&gt;disks[i].rdev;</div><div class='add'>+</div><div class='ctx'> 			if (rdev</div><div class='ctx'> 			    &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags)</div><div class='ctx'> 			    &amp;&amp; !test_bit(In_sync, &amp;rdev-&gt;flags)</div><div class='ctx'> 			    &amp;&amp; !rdev_set_badblocks(rdev, sh-&gt;sector,</div><div class='ctx'> 						   RAID5_STRIPE_SECTORS(conf), 0))</div><div class='ctx'> 				abort = 1;</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;disks[i].replacement);</div><div class='add'>+			rdev = conf-&gt;disks[i].replacement;</div><div class='add'>+</div><div class='ctx'> 			if (rdev</div><div class='ctx'> 			    &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags)</div><div class='ctx'> 			    &amp;&amp; !test_bit(In_sync, &amp;rdev-&gt;flags)</div><div class='hunk'>@@ -3810,7 +3777,6 @@ handle_failed_sync(struct r5conf *conf, struct stripe_head *sh,</div><div class='ctx'> 						   RAID5_STRIPE_SECTORS(conf), 0))</div><div class='ctx'> 				abort = 1;</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='ctx'> 		if (abort)</div><div class='ctx'> 			conf-&gt;recovery_disabled =</div><div class='ctx'> 				conf-&gt;mddev-&gt;recovery_disabled;</div><div class='hunk'>@@ -3823,15 +3789,13 @@ static int want_replace(struct stripe_head *sh, int disk_idx)</div><div class='ctx'> 	struct md_rdev *rdev;</div><div class='ctx'> 	int rv = 0;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='del'>-	rdev = rcu_dereference(sh-&gt;raid_conf-&gt;disks[disk_idx].replacement);</div><div class='add'>+	rdev = sh-&gt;raid_conf-&gt;disks[disk_idx].replacement;</div><div class='ctx'> 	if (rdev</div><div class='ctx'> 	    &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags)</div><div class='ctx'> 	    &amp;&amp; !test_bit(In_sync, &amp;rdev-&gt;flags)</div><div class='ctx'> 	    &amp;&amp; (rdev-&gt;recovery_offset &lt;= sh-&gt;sector</div><div class='ctx'> 		|| rdev-&gt;mddev-&gt;recovery_cp &lt;= sh-&gt;sector))</div><div class='ctx'> 		rv = 1;</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	return rv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4708,7 +4672,6 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 	s-&gt;log_failed = r5l_log_disk_error(conf);</div><div class='ctx'> </div><div class='ctx'> 	/* Now to look around and see what can be done */</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i=disks; i--; ) {</div><div class='ctx'> 		struct md_rdev *rdev;</div><div class='ctx'> 		sector_t first_bad;</div><div class='hunk'>@@ -4753,7 +4716,7 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 		/* Prefer to use the replacement for reads, but only</div><div class='ctx'> 		 * if it is recovered enough and has no bad blocks.</div><div class='ctx'> 		 */</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;disks[i].replacement);</div><div class='add'>+		rdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 		if (rdev &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    rdev-&gt;recovery_offset &gt;= sh-&gt;sector + RAID5_STRIPE_SECTORS(conf) &amp;&amp;</div><div class='ctx'> 		    !is_badblock(rdev, sh-&gt;sector, RAID5_STRIPE_SECTORS(conf),</div><div class='hunk'>@@ -4764,7 +4727,7 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 				set_bit(R5_NeedReplace, &amp;dev-&gt;flags);</div><div class='ctx'> 			else</div><div class='ctx'> 				clear_bit(R5_NeedReplace, &amp;dev-&gt;flags);</div><div class='del'>-			rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+			rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 			clear_bit(R5_ReadRepl, &amp;dev-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (rdev &amp;&amp; test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='hunk'>@@ -4811,8 +4774,8 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 		if (test_bit(R5_WriteError, &amp;dev-&gt;flags)) {</div><div class='ctx'> 			/* This flag does not apply to '.replacement'</div><div class='ctx'> 			 * only to .rdev, so make sure to check that*/</div><div class='del'>-			struct md_rdev *rdev2 = rcu_dereference(</div><div class='del'>-				conf-&gt;disks[i].rdev);</div><div class='add'>+			struct md_rdev *rdev2 = conf-&gt;disks[i].rdev;</div><div class='add'>+</div><div class='ctx'> 			if (rdev2 == rdev)</div><div class='ctx'> 				clear_bit(R5_Insync, &amp;dev-&gt;flags);</div><div class='ctx'> 			if (rdev2 &amp;&amp; !test_bit(Faulty, &amp;rdev2-&gt;flags)) {</div><div class='hunk'>@@ -4824,8 +4787,8 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 		if (test_bit(R5_MadeGood, &amp;dev-&gt;flags)) {</div><div class='ctx'> 			/* This flag does not apply to '.replacement'</div><div class='ctx'> 			 * only to .rdev, so make sure to check that*/</div><div class='del'>-			struct md_rdev *rdev2 = rcu_dereference(</div><div class='del'>-				conf-&gt;disks[i].rdev);</div><div class='add'>+			struct md_rdev *rdev2 = conf-&gt;disks[i].rdev;</div><div class='add'>+</div><div class='ctx'> 			if (rdev2 &amp;&amp; !test_bit(Faulty, &amp;rdev2-&gt;flags)) {</div><div class='ctx'> 				s-&gt;handle_bad_blocks = 1;</div><div class='ctx'> 				atomic_inc(&amp;rdev2-&gt;nr_pending);</div><div class='hunk'>@@ -4833,8 +4796,8 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 				clear_bit(R5_MadeGood, &amp;dev-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (test_bit(R5_MadeGoodRepl, &amp;dev-&gt;flags)) {</div><div class='del'>-			struct md_rdev *rdev2 = rcu_dereference(</div><div class='del'>-				conf-&gt;disks[i].replacement);</div><div class='add'>+			struct md_rdev *rdev2 = conf-&gt;disks[i].replacement;</div><div class='add'>+</div><div class='ctx'> 			if (rdev2 &amp;&amp; !test_bit(Faulty, &amp;rdev2-&gt;flags)) {</div><div class='ctx'> 				s-&gt;handle_bad_blocks = 1;</div><div class='ctx'> 				atomic_inc(&amp;rdev2-&gt;nr_pending);</div><div class='hunk'>@@ -4855,8 +4818,7 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 			if (rdev &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 				do_recovery = 1;</div><div class='ctx'> 			else if (!rdev) {</div><div class='del'>-				rdev = rcu_dereference(</div><div class='del'>-				    conf-&gt;disks[i].replacement);</div><div class='add'>+				rdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 				if (rdev &amp;&amp; !test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 					do_recovery = 1;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -4883,7 +4845,6 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)</div><div class='ctx'> 		else</div><div class='ctx'> 			s-&gt;replacing = 1;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -5340,23 +5301,23 @@ finish:</div><div class='ctx'> 			struct r5dev *dev = &amp;sh-&gt;dev[i];</div><div class='ctx'> 			if (test_and_clear_bit(R5_WriteError, &amp;dev-&gt;flags)) {</div><div class='ctx'> 				/* We own a safe reference to the rdev */</div><div class='del'>-				rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+				rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 				if (!rdev_set_badblocks(rdev, sh-&gt;sector,</div><div class='ctx'> 							RAID5_STRIPE_SECTORS(conf), 0))</div><div class='ctx'> 					md_error(conf-&gt;mddev, rdev);</div><div class='ctx'> 				rdev_dec_pending(rdev, conf-&gt;mddev);</div><div class='ctx'> 			}</div><div class='ctx'> 			if (test_and_clear_bit(R5_MadeGood, &amp;dev-&gt;flags)) {</div><div class='del'>-				rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+				rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 				rdev_clear_badblocks(rdev, sh-&gt;sector,</div><div class='ctx'> 						     RAID5_STRIPE_SECTORS(conf), 0);</div><div class='ctx'> 				rdev_dec_pending(rdev, conf-&gt;mddev);</div><div class='ctx'> 			}</div><div class='ctx'> 			if (test_and_clear_bit(R5_MadeGoodRepl, &amp;dev-&gt;flags)) {</div><div class='del'>-				rdev = rdev_pend_deref(conf-&gt;disks[i].replacement);</div><div class='add'>+				rdev = conf-&gt;disks[i].replacement;</div><div class='ctx'> 				if (!rdev)</div><div class='ctx'> 					/* rdev have been moved down */</div><div class='del'>-					rdev = rdev_pend_deref(conf-&gt;disks[i].rdev);</div><div class='add'>+					rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 				rdev_clear_badblocks(rdev, sh-&gt;sector,</div><div class='ctx'> 						     RAID5_STRIPE_SECTORS(conf), 0);</div><div class='ctx'> 				rdev_dec_pending(rdev, conf-&gt;mddev);</div><div class='hunk'>@@ -5515,24 +5476,22 @@ static int raid5_read_one_chunk(struct mddev *mddev, struct bio *raid_bio)</div><div class='ctx'> 				      &amp;dd_idx, NULL);</div><div class='ctx'> 	end_sector = sector + bio_sectors(raid_bio);</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	if (r5c_big_stripe_cached(conf, sector))</div><div class='del'>-		goto out_rcu_unlock;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	rdev = rcu_dereference(conf-&gt;disks[dd_idx].replacement);</div><div class='add'>+	rdev = conf-&gt;disks[dd_idx].replacement;</div><div class='ctx'> 	if (!rdev || test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 	    rdev-&gt;recovery_offset &lt; end_sector) {</div><div class='del'>-		rdev = rcu_dereference(conf-&gt;disks[dd_idx].rdev);</div><div class='add'>+		rdev = conf-&gt;disks[dd_idx].rdev;</div><div class='ctx'> 		if (!rdev)</div><div class='del'>-			goto out_rcu_unlock;</div><div class='add'>+			return 0;</div><div class='ctx'> 		if (test_bit(Faulty, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 		    !(test_bit(In_sync, &amp;rdev-&gt;flags) ||</div><div class='ctx'> 		      rdev-&gt;recovery_offset &gt;= end_sector))</div><div class='del'>-			goto out_rcu_unlock;</div><div class='add'>+			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	atomic_inc(&amp;rdev-&gt;nr_pending);</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	if (is_badblock(rdev, sector, bio_sectors(raid_bio), &amp;first_bad,</div><div class='ctx'> 			&amp;bad_sectors)) {</div><div class='hunk'>@@ -5576,10 +5535,6 @@ static int raid5_read_one_chunk(struct mddev *mddev, struct bio *raid_bio)</div><div class='ctx'> 				      raid_bio-&gt;bi_iter.bi_sector);</div><div class='ctx'> 	submit_bio_noacct(align_bio);</div><div class='ctx'> 	return 1;</div><div class='del'>-</div><div class='del'>-out_rcu_unlock:</div><div class='del'>-	rcu_read_unlock();</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct bio *chunk_aligned_read(struct mddev *mddev, struct bio *raid_bio)</div><div class='hunk'>@@ -5892,11 +5847,11 @@ static bool stripe_ahead_of_reshape(struct mddev *mddev, struct r5conf *conf,</div><div class='ctx'> 	int dd_idx;</div><div class='ctx'> </div><div class='ctx'> 	for (dd_idx = 0; dd_idx &lt; sh-&gt;disks; dd_idx++) {</div><div class='del'>-		if (dd_idx == sh-&gt;pd_idx)</div><div class='add'>+		if (dd_idx == sh-&gt;pd_idx || dd_idx == sh-&gt;qd_idx)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		min_sector = min(min_sector, sh-&gt;dev[dd_idx].sector);</div><div class='del'>-		max_sector = min(max_sector, sh-&gt;dev[dd_idx].sector);</div><div class='add'>+		max_sector = max(max_sector, sh-&gt;dev[dd_idx].sector);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irq(&amp;conf-&gt;device_lock);</div><div class='hunk'>@@ -6582,14 +6537,12 @@ static inline sector_t raid5_sync_request(struct mddev *mddev, sector_t sector_n</div><div class='ctx'> 	 * Note in case of &gt; 1 drive failures it's possible we're rebuilding</div><div class='ctx'> 	 * one drive while leaving another faulty drive in array.</div><div class='ctx'> 	 */</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> </div><div class='ctx'> 		if (rdev == NULL || test_bit(Faulty, &amp;rdev-&gt;flags))</div><div class='ctx'> 			still_degraded = 1;</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	md_bitmap_start_sync(mddev-&gt;bitmap, sector_nr, &amp;sync_blocks, still_degraded);</div><div class='ctx'> </div><div class='hunk'>@@ -6820,18 +6773,7 @@ static void raid5d(struct md_thread *thread)</div><div class='ctx'> 			spin_unlock_irq(&amp;conf-&gt;device_lock);</div><div class='ctx'> 			md_check_recovery(mddev);</div><div class='ctx'> 			spin_lock_irq(&amp;conf-&gt;device_lock);</div><div class='del'>-</div><div class='del'>-			/*</div><div class='del'>-			 * Waiting on MD_SB_CHANGE_PENDING below may deadlock</div><div class='del'>-			 * seeing md_check_recovery() is needed to clear</div><div class='del'>-			 * the flag when using mdmon.</div><div class='del'>-			 */</div><div class='del'>-			continue;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		wait_event_lock_irq(mddev-&gt;sb_wait,</div><div class='del'>-			!test_bit(MD_SB_CHANGE_PENDING, &amp;mddev-&gt;sb_flags),</div><div class='del'>-			conf-&gt;device_lock);</div><div class='ctx'> 	}</div><div class='ctx'> 	pr_debug("%d stripes handled\n", handled);</div><div class='ctx'> </div><div class='hunk'>@@ -7911,18 +7853,10 @@ static int raid5_run(struct mddev *mddev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks &amp;&amp; conf-&gt;previous_raid_disks;</div><div class='ctx'> 	     i++) {</div><div class='del'>-		rdev = rdev_mdlock_deref(mddev, conf-&gt;disks[i].rdev);</div><div class='del'>-		if (!rdev &amp;&amp; conf-&gt;disks[i].replacement) {</div><div class='del'>-			/* The replacement is all we have yet */</div><div class='del'>-			rdev = rdev_mdlock_deref(mddev,</div><div class='del'>-						 conf-&gt;disks[i].replacement);</div><div class='del'>-			conf-&gt;disks[i].replacement = NULL;</div><div class='del'>-			clear_bit(Replacement, &amp;rdev-&gt;flags);</div><div class='del'>-			rcu_assign_pointer(conf-&gt;disks[i].rdev, rdev);</div><div class='del'>-		}</div><div class='add'>+		rdev = conf-&gt;disks[i].rdev;</div><div class='ctx'> 		if (!rdev)</div><div class='ctx'> 			continue;</div><div class='del'>-		if (rcu_access_pointer(conf-&gt;disks[i].replacement) &amp;&amp;</div><div class='add'>+		if (conf-&gt;disks[i].replacement &amp;&amp;</div><div class='ctx'> 		    conf-&gt;reshape_progress != MaxSector) {</div><div class='ctx'> 			/* replacements and reshape simply do not mix. */</div><div class='ctx'> 			pr_warn("md: cannot handle concurrent replacement and reshape.\n");</div><div class='hunk'>@@ -8106,15 +8040,16 @@ static void raid5_status(struct seq_file *seq, struct mddev *mddev)</div><div class='ctx'> 	struct r5conf *conf = mddev-&gt;private;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	lockdep_assert_held(&amp;mddev-&gt;lock);</div><div class='add'>+</div><div class='ctx'> 	seq_printf(seq, " level %d, %dk chunk, algorithm %d", mddev-&gt;level,</div><div class='ctx'> 		conf-&gt;chunk_sectors / 2, mddev-&gt;layout);</div><div class='ctx'> 	seq_printf (seq, " [%d/%d] [", conf-&gt;raid_disks, conf-&gt;raid_disks - mddev-&gt;degraded);</div><div class='del'>-	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		struct md_rdev *rdev = rcu_dereference(conf-&gt;disks[i].rdev);</div><div class='add'>+		struct md_rdev *rdev = READ_ONCE(conf-&gt;disks[i].rdev);</div><div class='add'>+</div><div class='ctx'> 		seq_printf (seq, "%s", rdev &amp;&amp; test_bit(In_sync, &amp;rdev-&gt;flags) ? "U" : "_");</div><div class='ctx'> 	}</div><div class='del'>-	rcu_read_unlock();</div><div class='ctx'> 	seq_printf (seq, "]");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -8152,9 +8087,8 @@ static int raid5_spare_active(struct mddev *mddev)</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++) {</div><div class='del'>-		rdev = rdev_mdlock_deref(mddev, conf-&gt;disks[i].rdev);</div><div class='del'>-		replacement = rdev_mdlock_deref(mddev,</div><div class='del'>-						conf-&gt;disks[i].replacement);</div><div class='add'>+		rdev = conf-&gt;disks[i].rdev;</div><div class='add'>+		replacement = conf-&gt;disks[i].replacement;</div><div class='ctx'> 		if (replacement</div><div class='ctx'> 		    &amp;&amp; replacement-&gt;recovery_offset == MaxSector</div><div class='ctx'> 		    &amp;&amp; !test_bit(Faulty, &amp;replacement-&gt;flags)</div><div class='hunk'>@@ -8193,7 +8127,7 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 	struct r5conf *conf = mddev-&gt;private;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> 	int number = rdev-&gt;raid_disk;</div><div class='del'>-	struct md_rdev __rcu **rdevp;</div><div class='add'>+	struct md_rdev **rdevp;</div><div class='ctx'> 	struct disk_info *p;</div><div class='ctx'> 	struct md_rdev *tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -8216,9 +8150,9 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 	if (unlikely(number &gt;= conf-&gt;pool_size))</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	p = conf-&gt;disks + number;</div><div class='del'>-	if (rdev == rcu_access_pointer(p-&gt;rdev))</div><div class='add'>+	if (rdev == p-&gt;rdev)</div><div class='ctx'> 		rdevp = &amp;p-&gt;rdev;</div><div class='del'>-	else if (rdev == rcu_access_pointer(p-&gt;replacement))</div><div class='add'>+	else if (rdev == p-&gt;replacement)</div><div class='ctx'> 		rdevp = &amp;p-&gt;replacement;</div><div class='ctx'> 	else</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -8238,37 +8172,24 @@ static int raid5_remove_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 	if (!test_bit(Faulty, &amp;rdev-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    mddev-&gt;recovery_disabled != conf-&gt;recovery_disabled &amp;&amp;</div><div class='ctx'> 	    !has_failed(conf) &amp;&amp;</div><div class='del'>-	    (!rcu_access_pointer(p-&gt;replacement) ||</div><div class='del'>-	     rcu_access_pointer(p-&gt;replacement) == rdev) &amp;&amp;</div><div class='add'>+	    (!p-&gt;replacement || p-&gt;replacement == rdev) &amp;&amp;</div><div class='ctx'> 	    number &lt; conf-&gt;raid_disks) {</div><div class='ctx'> 		err = -EBUSY;</div><div class='ctx'> 		goto abort;</div><div class='ctx'> 	}</div><div class='del'>-	*rdevp = NULL;</div><div class='del'>-	if (!test_bit(RemoveSynchronized, &amp;rdev-&gt;flags)) {</div><div class='del'>-		lockdep_assert_held(&amp;mddev-&gt;reconfig_mutex);</div><div class='del'>-		synchronize_rcu();</div><div class='del'>-		if (atomic_read(&amp;rdev-&gt;nr_pending)) {</div><div class='del'>-			/* lost the race, try later */</div><div class='del'>-			err = -EBUSY;</div><div class='del'>-			rcu_assign_pointer(*rdevp, rdev);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	WRITE_ONCE(*rdevp, NULL);</div><div class='ctx'> 	if (!err) {</div><div class='ctx'> 		err = log_modify(conf, rdev, false);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto abort;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	tmp = rcu_access_pointer(p-&gt;replacement);</div><div class='add'>+	tmp = p-&gt;replacement;</div><div class='ctx'> 	if (tmp) {</div><div class='ctx'> 		/* We must have just cleared 'rdev' */</div><div class='del'>-		rcu_assign_pointer(p-&gt;rdev, tmp);</div><div class='add'>+		WRITE_ONCE(p-&gt;rdev, tmp);</div><div class='ctx'> 		clear_bit(Replacement, &amp;tmp-&gt;flags);</div><div class='del'>-		smp_mb(); /* Make sure other CPUs may see both as identical</div><div class='del'>-			   * but will never see neither - if they are careful</div><div class='del'>-			   */</div><div class='del'>-		rcu_assign_pointer(p-&gt;replacement, NULL);</div><div class='add'>+		WRITE_ONCE(p-&gt;replacement, NULL);</div><div class='ctx'> </div><div class='ctx'> 		if (!err)</div><div class='ctx'> 			err = log_modify(conf, tmp, true);</div><div class='hunk'>@@ -8336,7 +8257,7 @@ static int raid5_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			rdev-&gt;raid_disk = disk;</div><div class='ctx'> 			if (rdev-&gt;saved_raid_disk != disk)</div><div class='ctx'> 				conf-&gt;fullsync = 1;</div><div class='del'>-			rcu_assign_pointer(p-&gt;rdev, rdev);</div><div class='add'>+			WRITE_ONCE(p-&gt;rdev, rdev);</div><div class='ctx'> </div><div class='ctx'> 			err = log_modify(conf, rdev, true);</div><div class='ctx'> </div><div class='hunk'>@@ -8345,7 +8266,7 @@ static int raid5_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 	}</div><div class='ctx'> 	for (disk = first; disk &lt;= last; disk++) {</div><div class='ctx'> 		p = conf-&gt;disks + disk;</div><div class='del'>-		tmp = rdev_mdlock_deref(mddev, p-&gt;rdev);</div><div class='add'>+		tmp = p-&gt;rdev;</div><div class='ctx'> 		if (test_bit(WantReplacement, &amp;tmp-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    mddev-&gt;reshape_position == MaxSector &amp;&amp;</div><div class='ctx'> 		    p-&gt;replacement == NULL) {</div><div class='hunk'>@@ -8354,7 +8275,7 @@ static int raid5_add_disk(struct mddev *mddev, struct md_rdev *rdev)</div><div class='ctx'> 			rdev-&gt;raid_disk = disk;</div><div class='ctx'> 			err = 0;</div><div class='ctx'> 			conf-&gt;fullsync = 1;</div><div class='del'>-			rcu_assign_pointer(p-&gt;replacement, rdev);</div><div class='add'>+			WRITE_ONCE(p-&gt;replacement, rdev);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -8487,7 +8408,7 @@ static int raid5_start_reshape(struct mddev *mddev)</div><div class='ctx'> 	if (mddev-&gt;recovery_cp &lt; MaxSector)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	for (i = 0; i &lt; conf-&gt;raid_disks; i++)</div><div class='del'>-		if (rdev_mdlock_deref(mddev, conf-&gt;disks[i].replacement))</div><div class='add'>+		if (conf-&gt;disks[i].replacement)</div><div class='ctx'> 			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	rdev_for_each(rdev, mddev) {</div><div class='hunk'>@@ -8658,12 +8579,10 @@ static void raid5_finish_reshape(struct mddev *mddev)</div><div class='ctx'> 			for (d = conf-&gt;raid_disks ;</div><div class='ctx'> 			     d &lt; conf-&gt;raid_disks - mddev-&gt;delta_disks;</div><div class='ctx'> 			     d++) {</div><div class='del'>-				rdev = rdev_mdlock_deref(mddev,</div><div class='del'>-							 conf-&gt;disks[d].rdev);</div><div class='add'>+				rdev = conf-&gt;disks[d].rdev;</div><div class='ctx'> 				if (rdev)</div><div class='ctx'> 					clear_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='del'>-				rdev = rdev_mdlock_deref(mddev,</div><div class='del'>-						conf-&gt;disks[d].replacement);</div><div class='add'>+				rdev = conf-&gt;disks[d].replacement;</div><div class='ctx'> 				if (rdev)</div><div class='ctx'> 					clear_bit(In_sync, &amp;rdev-&gt;flags);</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h<br/>index 22bea20eccbd..9b5a7dc3f2a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/md/raid5.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/md/raid5.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/md/raid5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/md/raid5.h</a></div><div class='hunk'>@@ -473,8 +473,8 @@ enum {</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> struct disk_info {</div><div class='del'>-	struct md_rdev	__rcu *rdev;</div><div class='del'>-	struct md_rdev  __rcu *replacement;</div><div class='add'>+	struct md_rdev	*rdev;</div><div class='add'>+	struct md_rdev	*replacement;</div><div class='ctx'> 	struct page	*extra_page; /* extra page to use in prexor */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c<br/>index 6bb49bb3f98c..5741adf09a2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/cec/core/cec-adap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/cec/core/cec-adap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/cec/core/cec-adap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/cec/core/cec-adap.c</a></div><div class='hunk'>@@ -511,7 +511,7 @@ int cec_thread_func(void *_adap)</div><div class='ctx'> 				pr_warn("cec-%s: transmit timed out\n", adap-&gt;name);</div><div class='ctx'> 			}</div><div class='ctx'> 			adap-&gt;transmit_in_progress = false;</div><div class='del'>-			adap-&gt;tx_timeouts++;</div><div class='add'>+			adap-&gt;tx_timeout_cnt++;</div><div class='ctx'> 			goto unlock;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -625,6 +625,33 @@ void cec_transmit_done_ts(struct cec_adapter *adap, u8 status,</div><div class='ctx'> 	msg-&gt;tx_low_drive_cnt += low_drive_cnt;</div><div class='ctx'> 	msg-&gt;tx_error_cnt += error_cnt;</div><div class='ctx'> </div><div class='add'>+	adap-&gt;tx_arb_lost_cnt += arb_lost_cnt;</div><div class='add'>+	adap-&gt;tx_low_drive_cnt += low_drive_cnt;</div><div class='add'>+	adap-&gt;tx_error_cnt += error_cnt;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Low Drive transmission errors should really not happen for</div><div class='add'>+	 * well-behaved CEC devices and proper HDMI cables.</div><div class='add'>+	 *</div><div class='add'>+	 * Ditto for the 'Error' status.</div><div class='add'>+	 *</div><div class='add'>+	 * For the first few times that this happens, log this.</div><div class='add'>+	 * Stop logging after that, since that will not add any more</div><div class='add'>+	 * useful information and instead it will just flood the kernel log.</div><div class='add'>+	 */</div><div class='add'>+	if (done &amp;&amp; adap-&gt;tx_low_drive_log_cnt &lt; 8 &amp;&amp; msg-&gt;tx_low_drive_cnt) {</div><div class='add'>+		adap-&gt;tx_low_drive_log_cnt++;</div><div class='add'>+		dprintk(0, "low drive counter: %u (seq %u: %*ph)\n",</div><div class='add'>+			msg-&gt;tx_low_drive_cnt, msg-&gt;sequence,</div><div class='add'>+			msg-&gt;len, msg-&gt;msg);</div><div class='add'>+	}</div><div class='add'>+	if (done &amp;&amp; adap-&gt;tx_error_log_cnt &lt; 8 &amp;&amp; msg-&gt;tx_error_cnt) {</div><div class='add'>+		adap-&gt;tx_error_log_cnt++;</div><div class='add'>+		dprintk(0, "error counter: %u (seq %u: %*ph)\n",</div><div class='add'>+			msg-&gt;tx_error_cnt, msg-&gt;sequence,</div><div class='add'>+			msg-&gt;len, msg-&gt;msg);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Mark that we're done with this transmit */</div><div class='ctx'> 	adap-&gt;transmitting = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -1607,6 +1634,8 @@ int cec_adap_enable(struct cec_adapter *adap)</div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		adap-&gt;last_initiator = 0xff;</div><div class='ctx'> 		adap-&gt;transmit_in_progress = false;</div><div class='add'>+		adap-&gt;tx_low_drive_log_cnt = 0;</div><div class='add'>+		adap-&gt;tx_error_log_cnt = 0;</div><div class='ctx'> 		ret = adap-&gt;ops-&gt;adap_enable(adap, true);</div><div class='ctx'> 		if (!ret) {</div><div class='ctx'> 			/*</div><div class='hunk'>@@ -2265,10 +2294,25 @@ int cec_adap_status(struct seq_file *file, void *priv)</div><div class='ctx'> 	if (adap-&gt;monitor_pin_cnt)</div><div class='ctx'> 		seq_printf(file, "file handles in Monitor Pin mode: %u\n",</div><div class='ctx'> 			   adap-&gt;monitor_pin_cnt);</div><div class='del'>-	if (adap-&gt;tx_timeouts) {</div><div class='del'>-		seq_printf(file, "transmit timeouts: %u\n",</div><div class='del'>-			   adap-&gt;tx_timeouts);</div><div class='del'>-		adap-&gt;tx_timeouts = 0;</div><div class='add'>+	if (adap-&gt;tx_timeout_cnt) {</div><div class='add'>+		seq_printf(file, "transmit timeout count: %u\n",</div><div class='add'>+			   adap-&gt;tx_timeout_cnt);</div><div class='add'>+		adap-&gt;tx_timeout_cnt = 0;</div><div class='add'>+	}</div><div class='add'>+	if (adap-&gt;tx_low_drive_cnt) {</div><div class='add'>+		seq_printf(file, "transmit low drive count: %u\n",</div><div class='add'>+			   adap-&gt;tx_low_drive_cnt);</div><div class='add'>+		adap-&gt;tx_low_drive_cnt = 0;</div><div class='add'>+	}</div><div class='add'>+	if (adap-&gt;tx_arb_lost_cnt) {</div><div class='add'>+		seq_printf(file, "transmit arbitration lost count: %u\n",</div><div class='add'>+			   adap-&gt;tx_arb_lost_cnt);</div><div class='add'>+		adap-&gt;tx_arb_lost_cnt = 0;</div><div class='add'>+	}</div><div class='add'>+	if (adap-&gt;tx_error_cnt) {</div><div class='add'>+		seq_printf(file, "transmit error count: %u\n",</div><div class='add'>+			   adap-&gt;tx_error_cnt);</div><div class='add'>+		adap-&gt;tx_error_cnt = 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	data = adap-&gt;transmitting;</div><div class='ctx'> 	if (data)</div><div class='head'>diff --git a/drivers/media/cec/platform/cros-ec/cros-ec-cec.c b/drivers/media/cec/platform/cros-ec/cros-ec-cec.c<br/>index 42dde3f0dbde..52ec0ba4b339 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/cec/platform/cros-ec/cros-ec-cec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/cec/platform/cros-ec/cros-ec-cec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/cec/platform/cros-ec/cros-ec-cec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/cec/platform/cros-ec/cros-ec-cec.c</a></div><div class='hunk'>@@ -324,6 +324,8 @@ static const struct cec_dmi_match cec_dmi_match_table[] = {</div><div class='ctx'> 	{ "Google", "Boxy", "0000:00:02.0", port_d_conns },</div><div class='ctx'> 	/* Google Taranza */</div><div class='ctx'> 	{ "Google", "Taranza", "0000:00:02.0", port_db_conns },</div><div class='add'>+	/* Google Dexi */</div><div class='add'>+	{ "Google", "Dexi", "0000:00:02.0", port_db_conns },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct device *cros_ec_cec_find_hdmi_dev(struct device *dev,</div><div class='head'>diff --git a/drivers/media/common/saa7146/saa7146_fops.c b/drivers/media/common/saa7146/saa7146_fops.c<br/>index 79214459387a..a7047e548245 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/common/saa7146/saa7146_fops.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/common/saa7146/saa7146_fops.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/common/saa7146/saa7146_fops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/saa7146/saa7146_fops.c</a></div><div class='hunk'>@@ -387,7 +387,7 @@ int saa7146_register_device(struct video_device *vfd, struct saa7146_dev *dev,</div><div class='ctx'> 	q-&gt;gfp_flags = __GFP_DMA32;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct saa7146_buf);</div><div class='ctx'> 	q-&gt;lock = &amp;dev-&gt;v4l2_lock;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;dev = &amp;dev-&gt;pci-&gt;dev;</div><div class='ctx'> 	err = vb2_queue_init(q);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c<br/>index 27aee92f3eea..41a832dd1426 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/common/videobuf2/videobuf2-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-core.c</a></div><div class='hunk'>@@ -31,6 +31,16 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;trace/events/vb2.h&gt;</div><div class='ctx'> </div><div class='add'>+#define PLANE_INDEX_BITS	3</div><div class='add'>+#define PLANE_INDEX_SHIFT	(PAGE_SHIFT + PLANE_INDEX_BITS)</div><div class='add'>+#define PLANE_INDEX_MASK	(BIT_MASK(PLANE_INDEX_BITS) - 1)</div><div class='add'>+#define MAX_BUFFER_INDEX	BIT_MASK(30 - PLANE_INDEX_SHIFT)</div><div class='add'>+#define BUFFER_INDEX_MASK	(MAX_BUFFER_INDEX - 1)</div><div class='add'>+</div><div class='add'>+#if BIT(PLANE_INDEX_BITS) != VIDEO_MAX_PLANES</div><div class='add'>+#error PLANE_INDEX_BITS order must be equal to VIDEO_MAX_PLANES</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> static int debug;</div><div class='ctx'> module_param(debug, int, 0644);</div><div class='ctx'> </div><div class='hunk'>@@ -356,23 +366,29 @@ static void __setup_offsets(struct vb2_buffer *vb)</div><div class='ctx'> {</div><div class='ctx'> 	struct vb2_queue *q = vb-&gt;vb2_queue;</div><div class='ctx'> 	unsigned int plane;</div><div class='del'>-	unsigned long off = 0;</div><div class='del'>-</div><div class='del'>-	if (vb-&gt;index) {</div><div class='del'>-		struct vb2_buffer *prev = q-&gt;bufs[vb-&gt;index - 1];</div><div class='del'>-		struct vb2_plane *p = &amp;prev-&gt;planes[prev-&gt;num_planes - 1];</div><div class='add'>+	unsigned long offset = 0;</div><div class='ctx'> </div><div class='del'>-		off = PAGE_ALIGN(p-&gt;m.offset + p-&gt;length);</div><div class='del'>-	}</div><div class='add'>+	/*</div><div class='add'>+	 * The offset "cookie" value has the following constraints:</div><div class='add'>+	 * - a buffer can have up to 8 planes.</div><div class='add'>+	 * - v4l2 mem2mem uses bit 30 to distinguish between</div><div class='add'>+	 *   OUTPUT (aka "source", bit 30 is 0) and</div><div class='add'>+	 *   CAPTURE (aka "destination", bit 30 is 1) buffers.</div><div class='add'>+	 * - must be page aligned</div><div class='add'>+	 * That led to this bit mapping when PAGE_SHIFT = 12:</div><div class='add'>+	 * |30                |29        15|14       12|11 0|</div><div class='add'>+	 * |DST_QUEUE_OFF_BASE|buffer index|plane index| 0  |</div><div class='add'>+	 * where there are 15 bits to store the buffer index.</div><div class='add'>+	 * Depending on PAGE_SHIFT value we can have fewer bits</div><div class='add'>+	 * to store the buffer index.</div><div class='add'>+	 */</div><div class='add'>+	offset = vb-&gt;index &lt;&lt; PLANE_INDEX_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	for (plane = 0; plane &lt; vb-&gt;num_planes; ++plane) {</div><div class='del'>-		vb-&gt;planes[plane].m.offset = off;</div><div class='add'>+		vb-&gt;planes[plane].m.offset = offset + (plane &lt;&lt; PAGE_SHIFT);</div><div class='ctx'> </div><div class='ctx'> 		dprintk(q, 3, "buffer %d, plane %d offset 0x%08lx\n",</div><div class='del'>-				vb-&gt;index, plane, off);</div><div class='del'>-</div><div class='del'>-		off += vb-&gt;planes[plane].length;</div><div class='del'>-		off = PAGE_ALIGN(off);</div><div class='add'>+				vb-&gt;index, plane, offset);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -397,6 +413,31 @@ static void init_buffer_cache_hints(struct vb2_queue *q, struct vb2_buffer *vb)</div><div class='ctx'> 		vb-&gt;skip_cache_sync_on_finish = 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * vb2_queue_add_buffer() - add a buffer to a queue</div><div class='add'>+ * @q:	pointer to &amp;struct vb2_queue with videobuf2 queue.</div><div class='add'>+ * @vb:	pointer to &amp;struct vb2_buffer to be added to the queue.</div><div class='add'>+ * @index: index where add vb2_buffer in the queue</div><div class='add'>+ */</div><div class='add'>+static void vb2_queue_add_buffer(struct vb2_queue *q, struct vb2_buffer *vb, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	WARN_ON(index &gt;= q-&gt;max_num_buffers || q-&gt;bufs[index] || vb-&gt;vb2_queue);</div><div class='add'>+</div><div class='add'>+	q-&gt;bufs[index] = vb;</div><div class='add'>+	vb-&gt;index = index;</div><div class='add'>+	vb-&gt;vb2_queue = q;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vb2_queue_remove_buffer() - remove a buffer from a queue</div><div class='add'>+ * @vb:	pointer to &amp;struct vb2_buffer to be removed from the queue.</div><div class='add'>+ */</div><div class='add'>+static void vb2_queue_remove_buffer(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	vb-&gt;vb2_queue-&gt;bufs[vb-&gt;index] = NULL;</div><div class='add'>+	vb-&gt;vb2_queue = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * __vb2_queue_alloc() - allocate vb2 buffer structures and (for MMAP type)</div><div class='ctx'>  * video buffer memory for all buffers/planes on the queue and initializes the</div><div class='hunk'>@@ -408,13 +449,17 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 			     unsigned int num_buffers, unsigned int num_planes,</div><div class='ctx'> 			     const unsigned plane_sizes[VB2_MAX_PLANES])</div><div class='ctx'> {</div><div class='add'>+	unsigned int q_num_buffers = vb2_get_num_buffers(q);</div><div class='ctx'> 	unsigned int buffer, plane;</div><div class='ctx'> 	struct vb2_buffer *vb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	/* Ensure that q-&gt;num_buffers+num_buffers is below VB2_MAX_FRAME */</div><div class='add'>+	/*</div><div class='add'>+	 * Ensure that the number of already queue + the number of buffers already</div><div class='add'>+	 * in the queue is below q-&gt;max_num_buffers</div><div class='add'>+	 */</div><div class='ctx'> 	num_buffers = min_t(unsigned int, num_buffers,</div><div class='del'>-			    VB2_MAX_FRAME - q-&gt;num_buffers);</div><div class='add'>+			    q-&gt;max_num_buffers - q_num_buffers);</div><div class='ctx'> </div><div class='ctx'> 	for (buffer = 0; buffer &lt; num_buffers; ++buffer) {</div><div class='ctx'> 		/* Allocate vb2 buffer structures */</div><div class='hunk'>@@ -425,9 +470,7 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		vb-&gt;state = VB2_BUF_STATE_DEQUEUED;</div><div class='del'>-		vb-&gt;vb2_queue = q;</div><div class='ctx'> 		vb-&gt;num_planes = num_planes;</div><div class='del'>-		vb-&gt;index = q-&gt;num_buffers + buffer;</div><div class='ctx'> 		vb-&gt;type = q-&gt;type;</div><div class='ctx'> 		vb-&gt;memory = memory;</div><div class='ctx'> 		init_buffer_cache_hints(q, vb);</div><div class='hunk'>@@ -435,9 +478,9 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 			vb-&gt;planes[plane].length = plane_sizes[plane];</div><div class='ctx'> 			vb-&gt;planes[plane].min_length = plane_sizes[plane];</div><div class='ctx'> 		}</div><div class='del'>-		call_void_bufop(q, init_buffer, vb);</div><div class='ctx'> </div><div class='del'>-		q-&gt;bufs[vb-&gt;index] = vb;</div><div class='add'>+		vb2_queue_add_buffer(q, vb, q_num_buffers + buffer);</div><div class='add'>+		call_void_bufop(q, init_buffer, vb);</div><div class='ctx'> </div><div class='ctx'> 		/* Allocate video buffer memory for the MMAP type */</div><div class='ctx'> 		if (memory == VB2_MEMORY_MMAP) {</div><div class='hunk'>@@ -445,7 +488,7 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 			if (ret) {</div><div class='ctx'> 				dprintk(q, 1, "failed allocating memory for buffer %d\n",</div><div class='ctx'> 					buffer);</div><div class='del'>-				q-&gt;bufs[vb-&gt;index] = NULL;</div><div class='add'>+				vb2_queue_remove_buffer(vb);</div><div class='ctx'> 				kfree(vb);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -460,7 +503,7 @@ static int __vb2_queue_alloc(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 				dprintk(q, 1, "buffer %d %p initialization failed\n",</div><div class='ctx'> 					buffer, vb);</div><div class='ctx'> 				__vb2_buf_mem_free(vb);</div><div class='del'>-				q-&gt;bufs[vb-&gt;index] = NULL;</div><div class='add'>+				vb2_queue_remove_buffer(vb);</div><div class='ctx'> 				kfree(vb);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -480,10 +523,11 @@ static void __vb2_free_mem(struct vb2_queue *q, unsigned int buffers)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int buffer;</div><div class='ctx'> 	struct vb2_buffer *vb;</div><div class='add'>+	unsigned int q_num_buffers = vb2_get_num_buffers(q);</div><div class='ctx'> </div><div class='del'>-	for (buffer = q-&gt;num_buffers - buffers; buffer &lt; q-&gt;num_buffers;</div><div class='add'>+	for (buffer = q_num_buffers - buffers; buffer &lt; q_num_buffers;</div><div class='ctx'> 	     ++buffer) {</div><div class='del'>-		vb = q-&gt;bufs[buffer];</div><div class='add'>+		vb = vb2_get_buffer(q, buffer);</div><div class='ctx'> 		if (!vb)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -505,13 +549,14 @@ static void __vb2_free_mem(struct vb2_queue *q, unsigned int buffers)</div><div class='ctx'> static void __vb2_queue_free(struct vb2_queue *q, unsigned int buffers)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int buffer;</div><div class='add'>+	unsigned int q_num_buffers = vb2_get_num_buffers(q);</div><div class='ctx'> </div><div class='ctx'> 	lockdep_assert_held(&amp;q-&gt;mmap_lock);</div><div class='ctx'> </div><div class='ctx'> 	/* Call driver-provided cleanup function for each buffer, if provided */</div><div class='del'>-	for (buffer = q-&gt;num_buffers - buffers; buffer &lt; q-&gt;num_buffers;</div><div class='add'>+	for (buffer = q_num_buffers - buffers; buffer &lt; q_num_buffers;</div><div class='ctx'> 	     ++buffer) {</div><div class='del'>-		struct vb2_buffer *vb = q-&gt;bufs[buffer];</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(q, buffer);</div><div class='ctx'> </div><div class='ctx'> 		if (vb &amp;&amp; vb-&gt;planes[0].mem_priv)</div><div class='ctx'> 			call_void_vb_qop(vb, buf_cleanup, vb);</div><div class='hunk'>@@ -522,25 +567,26 @@ static void __vb2_queue_free(struct vb2_queue *q, unsigned int buffers)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_VIDEO_ADV_DEBUG</div><div class='ctx'> 	/*</div><div class='del'>-	 * Check that all the calls were balances during the life-time of this</div><div class='del'>-	 * queue. If not (or if the debug level is 1 or up), then dump the</div><div class='del'>-	 * counters to the kernel log.</div><div class='add'>+	 * Check that all the calls were balanced during the life-time of this</div><div class='add'>+	 * queue. If not then dump the counters to the kernel log.</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;num_buffers) {</div><div class='add'>+	if (q_num_buffers) {</div><div class='ctx'> 		bool unbalanced = q-&gt;cnt_start_streaming != q-&gt;cnt_stop_streaming ||</div><div class='ctx'> 				  q-&gt;cnt_prepare_streaming != q-&gt;cnt_unprepare_streaming ||</div><div class='ctx'> 				  q-&gt;cnt_wait_prepare != q-&gt;cnt_wait_finish;</div><div class='ctx'> </div><div class='del'>-		if (unbalanced || debug) {</div><div class='del'>-			pr_info("counters for queue %p:%s\n", q,</div><div class='del'>-				unbalanced ? " UNBALANCED!" : "");</div><div class='del'>-			pr_info("     setup: %u start_streaming: %u stop_streaming: %u\n",</div><div class='del'>-				q-&gt;cnt_queue_setup, q-&gt;cnt_start_streaming,</div><div class='del'>-				q-&gt;cnt_stop_streaming);</div><div class='del'>-			pr_info("     prepare_streaming: %u unprepare_streaming: %u\n",</div><div class='del'>-				q-&gt;cnt_prepare_streaming, q-&gt;cnt_unprepare_streaming);</div><div class='del'>-			pr_info("     wait_prepare: %u wait_finish: %u\n",</div><div class='del'>-				q-&gt;cnt_wait_prepare, q-&gt;cnt_wait_finish);</div><div class='add'>+		if (unbalanced) {</div><div class='add'>+			pr_info("unbalanced counters for queue %p:\n", q);</div><div class='add'>+			if (q-&gt;cnt_start_streaming != q-&gt;cnt_stop_streaming)</div><div class='add'>+				pr_info("     setup: %u start_streaming: %u stop_streaming: %u\n",</div><div class='add'>+					q-&gt;cnt_queue_setup, q-&gt;cnt_start_streaming,</div><div class='add'>+					q-&gt;cnt_stop_streaming);</div><div class='add'>+			if (q-&gt;cnt_prepare_streaming != q-&gt;cnt_unprepare_streaming)</div><div class='add'>+				pr_info("     prepare_streaming: %u unprepare_streaming: %u\n",</div><div class='add'>+					q-&gt;cnt_prepare_streaming, q-&gt;cnt_unprepare_streaming);</div><div class='add'>+			if (q-&gt;cnt_wait_prepare != q-&gt;cnt_wait_finish)</div><div class='add'>+				pr_info("     wait_prepare: %u wait_finish: %u\n",</div><div class='add'>+					q-&gt;cnt_wait_prepare, q-&gt;cnt_wait_finish);</div><div class='ctx'> 		}</div><div class='ctx'> 		q-&gt;cnt_queue_setup = 0;</div><div class='ctx'> 		q-&gt;cnt_wait_prepare = 0;</div><div class='hunk'>@@ -550,53 +596,71 @@ static void __vb2_queue_free(struct vb2_queue *q, unsigned int buffers)</div><div class='ctx'> 		q-&gt;cnt_stop_streaming = 0;</div><div class='ctx'> 		q-&gt;cnt_unprepare_streaming = 0;</div><div class='ctx'> 	}</div><div class='del'>-	for (buffer = 0; buffer &lt; q-&gt;num_buffers; ++buffer) {</div><div class='del'>-		struct vb2_buffer *vb = q-&gt;bufs[buffer];</div><div class='del'>-		bool unbalanced = vb-&gt;cnt_mem_alloc != vb-&gt;cnt_mem_put ||</div><div class='del'>-				  vb-&gt;cnt_mem_prepare != vb-&gt;cnt_mem_finish ||</div><div class='del'>-				  vb-&gt;cnt_mem_get_userptr != vb-&gt;cnt_mem_put_userptr ||</div><div class='del'>-				  vb-&gt;cnt_mem_attach_dmabuf != vb-&gt;cnt_mem_detach_dmabuf ||</div><div class='del'>-				  vb-&gt;cnt_mem_map_dmabuf != vb-&gt;cnt_mem_unmap_dmabuf ||</div><div class='del'>-				  vb-&gt;cnt_buf_queue != vb-&gt;cnt_buf_done ||</div><div class='del'>-				  vb-&gt;cnt_buf_prepare != vb-&gt;cnt_buf_finish ||</div><div class='del'>-				  vb-&gt;cnt_buf_init != vb-&gt;cnt_buf_cleanup;</div><div class='del'>-</div><div class='del'>-		if (unbalanced || debug) {</div><div class='del'>-			pr_info("   counters for queue %p, buffer %d:%s\n",</div><div class='del'>-				q, buffer, unbalanced ? " UNBALANCED!" : "");</div><div class='del'>-			pr_info("     buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\n",</div><div class='del'>-				vb-&gt;cnt_buf_init, vb-&gt;cnt_buf_cleanup,</div><div class='del'>-				vb-&gt;cnt_buf_prepare, vb-&gt;cnt_buf_finish);</div><div class='del'>-			pr_info("     buf_out_validate: %u buf_queue: %u buf_done: %u buf_request_complete: %u\n",</div><div class='del'>-				vb-&gt;cnt_buf_out_validate, vb-&gt;cnt_buf_queue,</div><div class='del'>-				vb-&gt;cnt_buf_done, vb-&gt;cnt_buf_request_complete);</div><div class='del'>-			pr_info("     alloc: %u put: %u prepare: %u finish: %u mmap: %u\n",</div><div class='del'>-				vb-&gt;cnt_mem_alloc, vb-&gt;cnt_mem_put,</div><div class='del'>-				vb-&gt;cnt_mem_prepare, vb-&gt;cnt_mem_finish,</div><div class='del'>-				vb-&gt;cnt_mem_mmap);</div><div class='del'>-			pr_info("     get_userptr: %u put_userptr: %u\n",</div><div class='del'>-				vb-&gt;cnt_mem_get_userptr, vb-&gt;cnt_mem_put_userptr);</div><div class='del'>-			pr_info("     attach_dmabuf: %u detach_dmabuf: %u map_dmabuf: %u unmap_dmabuf: %u\n",</div><div class='del'>-				vb-&gt;cnt_mem_attach_dmabuf, vb-&gt;cnt_mem_detach_dmabuf,</div><div class='del'>-				vb-&gt;cnt_mem_map_dmabuf, vb-&gt;cnt_mem_unmap_dmabuf);</div><div class='del'>-			pr_info("     get_dmabuf: %u num_users: %u vaddr: %u cookie: %u\n",</div><div class='add'>+	for (buffer = 0; buffer &lt; vb2_get_num_buffers(q); buffer++) {</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(q, buffer);</div><div class='add'>+		bool unbalanced;</div><div class='add'>+</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		unbalanced = vb-&gt;cnt_mem_alloc != vb-&gt;cnt_mem_put ||</div><div class='add'>+			     vb-&gt;cnt_mem_prepare != vb-&gt;cnt_mem_finish ||</div><div class='add'>+			     vb-&gt;cnt_mem_get_userptr != vb-&gt;cnt_mem_put_userptr ||</div><div class='add'>+			     vb-&gt;cnt_mem_attach_dmabuf != vb-&gt;cnt_mem_detach_dmabuf ||</div><div class='add'>+			     vb-&gt;cnt_mem_map_dmabuf != vb-&gt;cnt_mem_unmap_dmabuf ||</div><div class='add'>+			     vb-&gt;cnt_buf_queue != vb-&gt;cnt_buf_done ||</div><div class='add'>+			     vb-&gt;cnt_buf_prepare != vb-&gt;cnt_buf_finish ||</div><div class='add'>+			     vb-&gt;cnt_buf_init != vb-&gt;cnt_buf_cleanup;</div><div class='add'>+</div><div class='add'>+		if (unbalanced) {</div><div class='add'>+			pr_info("unbalanced counters for queue %p, buffer %d:\n",</div><div class='add'>+				q, buffer);</div><div class='add'>+			if (vb-&gt;cnt_buf_init != vb-&gt;cnt_buf_cleanup)</div><div class='add'>+				pr_info("     buf_init: %u buf_cleanup: %u\n",</div><div class='add'>+					vb-&gt;cnt_buf_init, vb-&gt;cnt_buf_cleanup);</div><div class='add'>+			if (vb-&gt;cnt_buf_prepare != vb-&gt;cnt_buf_finish)</div><div class='add'>+				pr_info("     buf_prepare: %u buf_finish: %u\n",</div><div class='add'>+					vb-&gt;cnt_buf_prepare, vb-&gt;cnt_buf_finish);</div><div class='add'>+			if (vb-&gt;cnt_buf_queue != vb-&gt;cnt_buf_done)</div><div class='add'>+				pr_info("     buf_out_validate: %u buf_queue: %u buf_done: %u buf_request_complete: %u\n",</div><div class='add'>+					vb-&gt;cnt_buf_out_validate, vb-&gt;cnt_buf_queue,</div><div class='add'>+					vb-&gt;cnt_buf_done, vb-&gt;cnt_buf_request_complete);</div><div class='add'>+			if (vb-&gt;cnt_mem_alloc != vb-&gt;cnt_mem_put)</div><div class='add'>+				pr_info("     alloc: %u put: %u\n",</div><div class='add'>+					vb-&gt;cnt_mem_alloc, vb-&gt;cnt_mem_put);</div><div class='add'>+			if (vb-&gt;cnt_mem_prepare != vb-&gt;cnt_mem_finish)</div><div class='add'>+				pr_info("     prepare: %u finish: %u\n",</div><div class='add'>+					vb-&gt;cnt_mem_prepare, vb-&gt;cnt_mem_finish);</div><div class='add'>+			if (vb-&gt;cnt_mem_get_userptr != vb-&gt;cnt_mem_put_userptr)</div><div class='add'>+				pr_info("     get_userptr: %u put_userptr: %u\n",</div><div class='add'>+					vb-&gt;cnt_mem_get_userptr, vb-&gt;cnt_mem_put_userptr);</div><div class='add'>+			if (vb-&gt;cnt_mem_attach_dmabuf != vb-&gt;cnt_mem_detach_dmabuf)</div><div class='add'>+				pr_info("     attach_dmabuf: %u detach_dmabuf: %u\n",</div><div class='add'>+					vb-&gt;cnt_mem_attach_dmabuf, vb-&gt;cnt_mem_detach_dmabuf);</div><div class='add'>+			if (vb-&gt;cnt_mem_map_dmabuf != vb-&gt;cnt_mem_unmap_dmabuf)</div><div class='add'>+				pr_info("     map_dmabuf: %u unmap_dmabuf: %u\n",</div><div class='add'>+					vb-&gt;cnt_mem_map_dmabuf, vb-&gt;cnt_mem_unmap_dmabuf);</div><div class='add'>+			pr_info("     get_dmabuf: %u num_users: %u\n",</div><div class='ctx'> 				vb-&gt;cnt_mem_get_dmabuf,</div><div class='del'>-				vb-&gt;cnt_mem_num_users,</div><div class='del'>-				vb-&gt;cnt_mem_vaddr,</div><div class='del'>-				vb-&gt;cnt_mem_cookie);</div><div class='add'>+				vb-&gt;cnt_mem_num_users);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> 	/* Free vb2 buffers */</div><div class='del'>-	for (buffer = q-&gt;num_buffers - buffers; buffer &lt; q-&gt;num_buffers;</div><div class='add'>+	for (buffer = q_num_buffers - buffers; buffer &lt; q_num_buffers;</div><div class='ctx'> 	     ++buffer) {</div><div class='del'>-		kfree(q-&gt;bufs[buffer]);</div><div class='del'>-		q-&gt;bufs[buffer] = NULL;</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(q, buffer);</div><div class='add'>+</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vb2_queue_remove_buffer(vb);</div><div class='add'>+		kfree(vb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	q-&gt;num_buffers -= buffers;</div><div class='del'>-	if (!q-&gt;num_buffers) {</div><div class='add'>+	if (!vb2_get_num_buffers(q)) {</div><div class='ctx'> 		q-&gt;memory = VB2_MEMORY_UNKNOWN;</div><div class='ctx'> 		INIT_LIST_HEAD(&amp;q-&gt;queued_list);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -627,16 +691,21 @@ EXPORT_SYMBOL(vb2_buffer_in_use);</div><div class='ctx'> static bool __buffers_in_use(struct vb2_queue *q)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int buffer;</div><div class='del'>-	for (buffer = 0; buffer &lt; q-&gt;num_buffers; ++buffer) {</div><div class='del'>-		if (vb2_buffer_in_use(q, q-&gt;bufs[buffer]))</div><div class='add'>+	for (buffer = 0; buffer &lt; vb2_get_num_buffers(q); ++buffer) {</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(q, buffer);</div><div class='add'>+</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (vb2_buffer_in_use(q, vb))</div><div class='ctx'> 			return true;</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void vb2_core_querybuf(struct vb2_queue *q, unsigned int index, void *pb)</div><div class='add'>+void vb2_core_querybuf(struct vb2_queue *q, struct vb2_buffer *vb, void *pb)</div><div class='ctx'> {</div><div class='del'>-	call_void_bufop(q, fill_user_buffer, q-&gt;bufs[index], pb);</div><div class='add'>+	call_void_bufop(q, fill_user_buffer, vb, pb);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_core_querybuf);</div><div class='ctx'> </div><div class='hunk'>@@ -748,10 +817,11 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		     unsigned int flags, unsigned int *count)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int num_buffers, allocated_buffers, num_planes = 0;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(q);</div><div class='ctx'> 	unsigned plane_sizes[VB2_MAX_PLANES] = { };</div><div class='ctx'> 	bool non_coherent_mem = flags &amp; V4L2_MEMORY_FLAG_NON_COHERENT;</div><div class='ctx'> 	unsigned int i;</div><div class='del'>-	int ret;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (q-&gt;streaming) {</div><div class='ctx'> 		dprintk(q, 1, "streaming active\n");</div><div class='hunk'>@@ -763,7 +833,7 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (*count == 0 || q-&gt;num_buffers != 0 ||</div><div class='add'>+	if (*count == 0 || q_num_bufs != 0 ||</div><div class='ctx'> 	    (q-&gt;memory != VB2_MEMORY_UNKNOWN &amp;&amp; q-&gt;memory != memory) ||</div><div class='ctx'> 	    !verify_coherency_flags(q, non_coherent_mem)) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -781,7 +851,7 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		 * queued without ever calling STREAMON.</div><div class='ctx'> 		 */</div><div class='ctx'> 		__vb2_queue_cancel(q);</div><div class='del'>-		__vb2_queue_free(q, q-&gt;num_buffers);</div><div class='add'>+		__vb2_queue_free(q, q_num_bufs);</div><div class='ctx'> 		mutex_unlock(&amp;q-&gt;mmap_lock);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -795,17 +865,22 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Make sure the requested values and current defaults are sane.</div><div class='ctx'> 	 */</div><div class='del'>-	WARN_ON(q-&gt;min_buffers_needed &gt; VB2_MAX_FRAME);</div><div class='del'>-	num_buffers = max_t(unsigned int, *count, q-&gt;min_buffers_needed);</div><div class='del'>-	num_buffers = min_t(unsigned int, num_buffers, VB2_MAX_FRAME);</div><div class='add'>+	num_buffers = max_t(unsigned int, *count, q-&gt;min_queued_buffers);</div><div class='add'>+	num_buffers = min_t(unsigned int, num_buffers, q-&gt;max_num_buffers);</div><div class='ctx'> 	memset(q-&gt;alloc_devs, 0, sizeof(q-&gt;alloc_devs));</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Set this now to ensure that drivers see the correct q-&gt;memory value</div><div class='ctx'> 	 * in the queue_setup op.</div><div class='ctx'> 	 */</div><div class='ctx'> 	mutex_lock(&amp;q-&gt;mmap_lock);</div><div class='add'>+	if (!q-&gt;bufs)</div><div class='add'>+		q-&gt;bufs = kcalloc(q-&gt;max_num_buffers, sizeof(*q-&gt;bufs), GFP_KERNEL);</div><div class='add'>+	if (!q-&gt;bufs)</div><div class='add'>+		ret = -ENOMEM;</div><div class='ctx'> 	q-&gt;memory = memory;</div><div class='ctx'> 	mutex_unlock(&amp;q-&gt;mmap_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> 	set_queue_coherency(q, non_coherent_mem);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -842,7 +917,7 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 	 * There is no point in continuing if we can't allocate the minimum</div><div class='ctx'> 	 * number of buffers needed by this vb2_queue.</div><div class='ctx'> 	 */</div><div class='del'>-	if (allocated_buffers &lt; q-&gt;min_buffers_needed)</div><div class='add'>+	if (allocated_buffers &lt; q-&gt;min_queued_buffers)</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -876,7 +951,7 @@ int vb2_core_reqbufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Note: __vb2_queue_free() will subtract 'allocated_buffers'</div><div class='del'>-		 * from q-&gt;num_buffers and it will reset q-&gt;memory to</div><div class='add'>+		 * from already queued buffers and it will reset q-&gt;memory to</div><div class='ctx'> 		 * VB2_MEMORY_UNKNOWN.</div><div class='ctx'> 		 */</div><div class='ctx'> 		__vb2_queue_free(q, allocated_buffers);</div><div class='hunk'>@@ -910,10 +985,11 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 	unsigned int num_planes = 0, num_buffers, allocated_buffers;</div><div class='ctx'> 	unsigned plane_sizes[VB2_MAX_PLANES] = { };</div><div class='ctx'> 	bool non_coherent_mem = flags &amp; V4L2_MEMORY_FLAG_NON_COHERENT;</div><div class='del'>-	bool no_previous_buffers = !q-&gt;num_buffers;</div><div class='del'>-	int ret;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(q);</div><div class='add'>+	bool no_previous_buffers = !q_num_bufs;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (q-&gt;num_buffers == VB2_MAX_FRAME) {</div><div class='add'>+	if (q-&gt;num_buffers == q-&gt;max_num_buffers) {</div><div class='ctx'> 		dprintk(q, 1, "maximum number of buffers already allocated\n");</div><div class='ctx'> 		return -ENOBUFS;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -930,7 +1006,13 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		 */</div><div class='ctx'> 		mutex_lock(&amp;q-&gt;mmap_lock);</div><div class='ctx'> 		q-&gt;memory = memory;</div><div class='add'>+		if (!q-&gt;bufs)</div><div class='add'>+			q-&gt;bufs = kcalloc(q-&gt;max_num_buffers, sizeof(*q-&gt;bufs), GFP_KERNEL);</div><div class='add'>+		if (!q-&gt;bufs)</div><div class='add'>+			ret = -ENOMEM;</div><div class='ctx'> 		mutex_unlock(&amp;q-&gt;mmap_lock);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> 		q-&gt;waiting_for_buffers = !q-&gt;is_output;</div><div class='ctx'> 		set_queue_coherency(q, non_coherent_mem);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -942,7 +1024,7 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	num_buffers = min(*count, VB2_MAX_FRAME - q-&gt;num_buffers);</div><div class='add'>+	num_buffers = min(*count, q-&gt;max_num_buffers - q_num_bufs);</div><div class='ctx'> </div><div class='ctx'> 	if (requested_planes &amp;&amp; requested_sizes) {</div><div class='ctx'> 		num_planes = requested_planes;</div><div class='hunk'>@@ -974,7 +1056,7 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 		num_buffers = allocated_buffers;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * q-&gt;num_buffers contains the total number of buffers, that the</div><div class='add'>+		 * num_buffers contains the total number of buffers, that the</div><div class='ctx'> 		 * queue driver has set up</div><div class='ctx'> 		 */</div><div class='ctx'> 		ret = call_qop(q, queue_setup, q, &amp;num_buffers,</div><div class='hunk'>@@ -995,7 +1077,7 @@ int vb2_core_create_bufs(struct vb2_queue *q, enum vb2_memory memory,</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Note: __vb2_queue_free() will subtract 'allocated_buffers'</div><div class='del'>-		 * from q-&gt;num_buffers and it will reset q-&gt;memory to</div><div class='add'>+		 * from already queued buffers and it will reset q-&gt;memory to</div><div class='ctx'> 		 * VB2_MEMORY_UNKNOWN.</div><div class='ctx'> 		 */</div><div class='ctx'> 		__vb2_queue_free(q, allocated_buffers);</div><div class='hunk'>@@ -1470,9 +1552,6 @@ static void vb2_req_unprepare(struct media_request_object *obj)</div><div class='ctx'> 	WARN_ON(!vb-&gt;req_obj.req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb,</div><div class='del'>-		  struct media_request *req);</div><div class='del'>-</div><div class='ctx'> static void vb2_req_queue(struct media_request_object *obj)</div><div class='ctx'> {</div><div class='ctx'> 	struct vb2_buffer *vb = container_of(obj, struct vb2_buffer, req_obj);</div><div class='hunk'>@@ -1487,7 +1566,7 @@ static void vb2_req_queue(struct media_request_object *obj)</div><div class='ctx'> 	 * set. We just ignore that, and expect this will be caught the</div><div class='ctx'> 	 * next time vb2_req_prepare() is called.</div><div class='ctx'> 	 */</div><div class='del'>-	err = vb2_core_qbuf(vb-&gt;vb2_queue, vb-&gt;index, NULL, NULL);</div><div class='add'>+	err = vb2_core_qbuf(vb-&gt;vb2_queue, vb, NULL, NULL);</div><div class='ctx'> 	WARN_ON_ONCE(err &amp;&amp; err != -EIO);</div><div class='ctx'> 	mutex_unlock(vb-&gt;vb2_queue-&gt;lock);</div><div class='ctx'> }</div><div class='hunk'>@@ -1542,12 +1621,10 @@ unsigned int vb2_request_buffer_cnt(struct media_request *req)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_request_buffer_cnt);</div><div class='ctx'> </div><div class='del'>-int vb2_core_prepare_buf(struct vb2_queue *q, unsigned int index, void *pb)</div><div class='add'>+int vb2_core_prepare_buf(struct vb2_queue *q, struct vb2_buffer *vb, void *pb)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_buffer *vb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	vb = q-&gt;bufs[index];</div><div class='ctx'> 	if (vb-&gt;state != VB2_BUF_STATE_DEQUEUED) {</div><div class='ctx'> 		dprintk(q, 1, "invalid buffer state %s\n",</div><div class='ctx'> 			vb2_state_name(vb-&gt;state));</div><div class='hunk'>@@ -1576,7 +1653,7 @@ EXPORT_SYMBOL_GPL(vb2_core_prepare_buf);</div><div class='ctx'>  * @q:		videobuf2 queue</div><div class='ctx'>  *</div><div class='ctx'>  * Attempt to start streaming. When this function is called there must be</div><div class='del'>- * at least q-&gt;min_buffers_needed buffers queued up (i.e. the minimum</div><div class='add'>+ * at least q-&gt;min_queued_buffers queued up (i.e. the minimum</div><div class='ctx'>  * number of buffers required for the DMA engine to function). If the</div><div class='ctx'>  * @start_streaming op fails it is supposed to return all the driver-owned</div><div class='ctx'>  * buffers back to vb2 in state QUEUED. Check if that happened and if</div><div class='hunk'>@@ -1617,8 +1694,12 @@ static int vb2_start_streaming(struct vb2_queue *q)</div><div class='ctx'> 		 * Forcefully reclaim buffers if the driver did not</div><div class='ctx'> 		 * correctly return them to vb2.</div><div class='ctx'> 		 */</div><div class='del'>-		for (i = 0; i &lt; q-&gt;num_buffers; ++i) {</div><div class='del'>-			vb = q-&gt;bufs[i];</div><div class='add'>+		for (i = 0; i &lt; vb2_get_num_buffers(q); ++i) {</div><div class='add'>+			vb = vb2_get_buffer(q, i);</div><div class='add'>+</div><div class='add'>+			if (!vb)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			if (vb-&gt;state == VB2_BUF_STATE_ACTIVE)</div><div class='ctx'> 				vb2_buffer_done(vb, VB2_BUF_STATE_QUEUED);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1634,10 +1715,9 @@ static int vb2_start_streaming(struct vb2_queue *q)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb,</div><div class='add'>+int vb2_core_qbuf(struct vb2_queue *q, struct vb2_buffer *vb, void *pb,</div><div class='ctx'> 		  struct media_request *req)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_buffer *vb;</div><div class='ctx'> 	enum vb2_buffer_state orig_state;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1646,8 +1726,6 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb,</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	vb = q-&gt;bufs[index];</div><div class='del'>-</div><div class='ctx'> 	if (!req &amp;&amp; vb-&gt;state != VB2_BUF_STATE_IN_REQUEST &amp;&amp;</div><div class='ctx'> 	    q-&gt;requires_requests) {</div><div class='ctx'> 		dprintk(q, 1, "qbuf requires a request\n");</div><div class='hunk'>@@ -1768,7 +1846,7 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb,</div><div class='ctx'> 	 * then we can finally call start_streaming().</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (q-&gt;streaming &amp;&amp; !q-&gt;start_streaming_called &amp;&amp;</div><div class='del'>-	    q-&gt;queued_count &gt;= q-&gt;min_buffers_needed) {</div><div class='add'>+	    q-&gt;queued_count &gt;= q-&gt;min_queued_buffers) {</div><div class='ctx'> 		ret = vb2_start_streaming(q);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			/*</div><div class='hunk'>@@ -2022,12 +2100,18 @@ static void __vb2_queue_cancel(struct vb2_queue *q)</div><div class='ctx'> 	 * to vb2 in stop_streaming().</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (WARN_ON(atomic_read(&amp;q-&gt;owned_by_drv_count))) {</div><div class='del'>-		for (i = 0; i &lt; q-&gt;num_buffers; ++i)</div><div class='del'>-			if (q-&gt;bufs[i]-&gt;state == VB2_BUF_STATE_ACTIVE) {</div><div class='del'>-				pr_warn("driver bug: stop_streaming operation is leaving buf %p in active state\n",</div><div class='del'>-					q-&gt;bufs[i]);</div><div class='del'>-				vb2_buffer_done(q-&gt;bufs[i], VB2_BUF_STATE_ERROR);</div><div class='add'>+		for (i = 0; i &lt; vb2_get_num_buffers(q); i++) {</div><div class='add'>+			struct vb2_buffer *vb = vb2_get_buffer(q, i);</div><div class='add'>+</div><div class='add'>+			if (!vb)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (vb-&gt;state == VB2_BUF_STATE_ACTIVE) {</div><div class='add'>+				pr_warn("driver bug: stop_streaming operation is leaving buffer %u in active state\n",</div><div class='add'>+					vb-&gt;index);</div><div class='add'>+				vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);</div><div class='ctx'> 			}</div><div class='add'>+		}</div><div class='ctx'> 		/* Must be zero now */</div><div class='ctx'> 		WARN_ON(atomic_read(&amp;q-&gt;owned_by_drv_count));</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2060,10 +2144,15 @@ static void __vb2_queue_cancel(struct vb2_queue *q)</div><div class='ctx'> 	 * call to __fill_user_buffer() after buf_finish(). That order can't</div><div class='ctx'> 	 * be changed, so we can't move the buf_finish() to __vb2_dqbuf().</div><div class='ctx'> 	 */</div><div class='del'>-	for (i = 0; i &lt; q-&gt;num_buffers; ++i) {</div><div class='del'>-		struct vb2_buffer *vb = q-&gt;bufs[i];</div><div class='del'>-		struct media_request *req = vb-&gt;req_obj.req;</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(q); i++) {</div><div class='add'>+		struct vb2_buffer *vb;</div><div class='add'>+		struct media_request *req;</div><div class='add'>+</div><div class='add'>+		vb = vb2_get_buffer(q, i);</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='add'>+		req = vb-&gt;req_obj.req;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If a request is associated with this buffer, then</div><div class='ctx'> 		 * call buf_request_cancel() to give the driver to complete()</div><div class='hunk'>@@ -2103,6 +2192,7 @@ static void __vb2_queue_cancel(struct vb2_queue *q)</div><div class='ctx'> </div><div class='ctx'> int vb2_core_streamon(struct vb2_queue *q, unsigned int type)</div><div class='ctx'> {</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(q);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (type != q-&gt;type) {</div><div class='hunk'>@@ -2115,14 +2205,14 @@ int vb2_core_streamon(struct vb2_queue *q, unsigned int type)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!q-&gt;num_buffers) {</div><div class='add'>+	if (!q_num_bufs) {</div><div class='ctx'> 		dprintk(q, 1, "no buffers have been allocated\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (q-&gt;num_buffers &lt; q-&gt;min_buffers_needed) {</div><div class='del'>-		dprintk(q, 1, "need at least %u allocated buffers\n",</div><div class='del'>-				q-&gt;min_buffers_needed);</div><div class='add'>+	if (q_num_bufs &lt; q-&gt;min_queued_buffers) {</div><div class='add'>+		dprintk(q, 1, "need at least %u queued buffers\n",</div><div class='add'>+			q-&gt;min_queued_buffers);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2134,7 +2224,7 @@ int vb2_core_streamon(struct vb2_queue *q, unsigned int type)</div><div class='ctx'> 	 * Tell driver to start streaming provided sufficient buffers</div><div class='ctx'> 	 * are available.</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;queued_count &gt;= q-&gt;min_buffers_needed) {</div><div class='add'>+	if (q-&gt;queued_count &gt;= q-&gt;min_queued_buffers) {</div><div class='ctx'> 		ret = vb2_start_streaming(q);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto unprepare;</div><div class='hunk'>@@ -2185,13 +2275,12 @@ int vb2_core_streamoff(struct vb2_queue *q, unsigned int type)</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_core_streamoff);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * __find_plane_by_offset() - find plane associated with the given offset off</div><div class='add'>+ * __find_plane_by_offset() - find plane associated with the given offset</div><div class='ctx'>  */</div><div class='del'>-static int __find_plane_by_offset(struct vb2_queue *q, unsigned long off,</div><div class='del'>-			unsigned int *_buffer, unsigned int *_plane)</div><div class='add'>+static int __find_plane_by_offset(struct vb2_queue *q, unsigned long offset,</div><div class='add'>+			struct vb2_buffer **vb, unsigned int *plane)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_buffer *vb;</div><div class='del'>-	unsigned int buffer, plane;</div><div class='add'>+	unsigned int buffer;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Sanity checks to ensure the lock is held, MEMORY_MMAP is</div><div class='hunk'>@@ -2209,30 +2298,22 @@ static int __find_plane_by_offset(struct vb2_queue *q, unsigned long off,</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Go over all buffers and their planes, comparing the given offset</div><div class='del'>-	 * with an offset assigned to each plane. If a match is found,</div><div class='del'>-	 * return its buffer and plane numbers.</div><div class='del'>-	 */</div><div class='del'>-	for (buffer = 0; buffer &lt; q-&gt;num_buffers; ++buffer) {</div><div class='del'>-		vb = q-&gt;bufs[buffer];</div><div class='add'>+	/* Get buffer and plane from the offset */</div><div class='add'>+	buffer = (offset &gt;&gt; PLANE_INDEX_SHIFT) &amp; BUFFER_INDEX_MASK;</div><div class='add'>+	*plane = (offset &gt;&gt; PAGE_SHIFT) &amp; PLANE_INDEX_MASK;</div><div class='ctx'> </div><div class='del'>-		for (plane = 0; plane &lt; vb-&gt;num_planes; ++plane) {</div><div class='del'>-			if (vb-&gt;planes[plane].m.offset == off) {</div><div class='del'>-				*_buffer = buffer;</div><div class='del'>-				*_plane = plane;</div><div class='del'>-				return 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	*vb = vb2_get_buffer(q, buffer);</div><div class='add'>+	if (!*vb)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	if (*plane &gt;= (*vb)-&gt;num_planes)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	return -EINVAL;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int vb2_core_expbuf(struct vb2_queue *q, int *fd, unsigned int type,</div><div class='del'>-		unsigned int index, unsigned int plane, unsigned int flags)</div><div class='add'>+		    struct vb2_buffer *vb, unsigned int plane, unsigned int flags)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_buffer *vb = NULL;</div><div class='ctx'> 	struct vb2_plane *vb_plane;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	struct dma_buf *dbuf;</div><div class='hunk'>@@ -2257,13 +2338,6 @@ int vb2_core_expbuf(struct vb2_queue *q, int *fd, unsigned int type,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (index &gt;= q-&gt;num_buffers) {</div><div class='del'>-		dprintk(q, 1, "buffer index out of range\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	vb = q-&gt;bufs[index];</div><div class='del'>-</div><div class='ctx'> 	if (plane &gt;= vb-&gt;num_planes) {</div><div class='ctx'> 		dprintk(q, 1, "buffer plane out of range\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2282,20 +2356,20 @@ int vb2_core_expbuf(struct vb2_queue *q, int *fd, unsigned int type,</div><div class='ctx'> 			      flags &amp; O_ACCMODE);</div><div class='ctx'> 	if (IS_ERR_OR_NULL(dbuf)) {</div><div class='ctx'> 		dprintk(q, 1, "failed to export buffer %d, plane %d\n",</div><div class='del'>-			index, plane);</div><div class='add'>+			vb-&gt;index, plane);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = dma_buf_fd(dbuf, flags &amp; ~O_ACCMODE);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dprintk(q, 3, "buffer %d, plane %d failed to export (%d)\n",</div><div class='del'>-			index, plane, ret);</div><div class='add'>+			vb-&gt;index, plane, ret);</div><div class='ctx'> 		dma_buf_put(dbuf);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dprintk(q, 3, "buffer %d, plane %d exported as %d descriptor\n",</div><div class='del'>-		index, plane, ret);</div><div class='add'>+		vb-&gt;index, plane, ret);</div><div class='ctx'> 	*fd = ret;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2304,9 +2378,9 @@ EXPORT_SYMBOL_GPL(vb2_core_expbuf);</div><div class='ctx'> </div><div class='ctx'> int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma)</div><div class='ctx'> {</div><div class='del'>-	unsigned long off = vma-&gt;vm_pgoff &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	unsigned long offset = vma-&gt;vm_pgoff &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	struct vb2_buffer *vb;</div><div class='del'>-	unsigned int buffer = 0, plane = 0;</div><div class='add'>+	unsigned int plane = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	unsigned long length;</div><div class='ctx'> </div><div class='hunk'>@@ -2335,12 +2409,10 @@ int vb2_mmap(struct vb2_queue *q, struct vm_area_struct *vma)</div><div class='ctx'> 	 * Find the plane corresponding to the offset passed by userspace. This</div><div class='ctx'> 	 * will return an error if not MEMORY_MMAP or file I/O is in progress.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = __find_plane_by_offset(q, off, &amp;buffer, &amp;plane);</div><div class='add'>+	ret = __find_plane_by_offset(q, offset, &amp;vb, &amp;plane);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='del'>-	vb = q-&gt;bufs[buffer];</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * MMAP requires page_aligned buffers.</div><div class='ctx'> 	 * The buffer length was page_aligned at __vb2_buf_mem_alloc(),</div><div class='hunk'>@@ -2368,7 +2440,7 @@ unlock:</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	dprintk(q, 3, "buffer %d, plane %d successfully mapped\n", buffer, plane);</div><div class='add'>+	dprintk(q, 3, "buffer %u, plane %d successfully mapped\n", vb-&gt;index, plane);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_mmap);</div><div class='hunk'>@@ -2380,9 +2452,9 @@ unsigned long vb2_get_unmapped_area(struct vb2_queue *q,</div><div class='ctx'> 				    unsigned long pgoff,</div><div class='ctx'> 				    unsigned long flags)</div><div class='ctx'> {</div><div class='del'>-	unsigned long off = pgoff &lt;&lt; PAGE_SHIFT;</div><div class='add'>+	unsigned long offset = pgoff &lt;&lt; PAGE_SHIFT;</div><div class='ctx'> 	struct vb2_buffer *vb;</div><div class='del'>-	unsigned int buffer, plane;</div><div class='add'>+	unsigned int plane;</div><div class='ctx'> 	void *vaddr;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -2392,12 +2464,10 @@ unsigned long vb2_get_unmapped_area(struct vb2_queue *q,</div><div class='ctx'> 	 * Find the plane corresponding to the offset passed by userspace. This</div><div class='ctx'> 	 * will return an error if not MEMORY_MMAP or file I/O is in progress.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = __find_plane_by_offset(q, off, &amp;buffer, &amp;plane);</div><div class='add'>+	ret = __find_plane_by_offset(q, offset, &amp;vb, &amp;plane);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> </div><div class='del'>-	vb = q-&gt;bufs[buffer];</div><div class='del'>-</div><div class='ctx'> 	vaddr = vb2_plane_vaddr(vb, plane);</div><div class='ctx'> 	mutex_unlock(&amp;q-&gt;mmap_lock);</div><div class='ctx'> 	return vaddr ? (unsigned long)vaddr : -EINVAL;</div><div class='hunk'>@@ -2414,6 +2484,16 @@ int vb2_core_queue_init(struct vb2_queue *q)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Sanity check</div><div class='ctx'> 	 */</div><div class='add'>+	/*</div><div class='add'>+	 * For drivers who don't support max_num_buffers ensure</div><div class='add'>+	 * a backward compatibility.</div><div class='add'>+	 */</div><div class='add'>+	if (!q-&gt;max_num_buffers)</div><div class='add'>+		q-&gt;max_num_buffers = VB2_MAX_FRAME;</div><div class='add'>+</div><div class='add'>+	/* The maximum is limited by offset cookie encoding pattern */</div><div class='add'>+	q-&gt;max_num_buffers = min_t(unsigned int, q-&gt;max_num_buffers, MAX_BUFFER_INDEX);</div><div class='add'>+</div><div class='ctx'> 	if (WARN_ON(!q)			  ||</div><div class='ctx'> 	    WARN_ON(!q-&gt;ops)		  ||</div><div class='ctx'> 	    WARN_ON(!q-&gt;mem_ops)	  ||</div><div class='hunk'>@@ -2423,18 +2503,22 @@ int vb2_core_queue_init(struct vb2_queue *q)</div><div class='ctx'> 	    WARN_ON(!q-&gt;ops-&gt;buf_queue))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (WARN_ON(q-&gt;max_num_buffers &gt; MAX_BUFFER_INDEX) ||</div><div class='add'>+	    WARN_ON(q-&gt;min_queued_buffers &gt; q-&gt;max_num_buffers))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (WARN_ON(q-&gt;requires_requests &amp;&amp; !q-&gt;supports_requests))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * This combination is not allowed since a non-zero value of</div><div class='del'>-	 * q-&gt;min_buffers_needed can cause vb2_core_qbuf() to fail if</div><div class='add'>+	 * q-&gt;min_queued_buffers can cause vb2_core_qbuf() to fail if</div><div class='ctx'> 	 * it has to call start_streaming(), and the Request API expects</div><div class='ctx'> 	 * that queueing a request (and thus queueing a buffer contained</div><div class='ctx'> 	 * in that request) will always succeed. There is no method of</div><div class='ctx'> 	 * propagating an error back to userspace.</div><div class='ctx'> 	 */</div><div class='del'>-	if (WARN_ON(q-&gt;supports_requests &amp;&amp; q-&gt;min_buffers_needed))</div><div class='add'>+	if (WARN_ON(q-&gt;supports_requests &amp;&amp; q-&gt;min_queued_buffers))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;q-&gt;queued_list);</div><div class='hunk'>@@ -2468,7 +2552,9 @@ void vb2_core_queue_release(struct vb2_queue *q)</div><div class='ctx'> 	__vb2_cleanup_fileio(q);</div><div class='ctx'> 	__vb2_queue_cancel(q);</div><div class='ctx'> 	mutex_lock(&amp;q-&gt;mmap_lock);</div><div class='del'>-	__vb2_queue_free(q, q-&gt;num_buffers);</div><div class='add'>+	__vb2_queue_free(q, vb2_get_num_buffers(q));</div><div class='add'>+	kfree(q-&gt;bufs);</div><div class='add'>+	q-&gt;bufs = NULL;</div><div class='ctx'> 	mutex_unlock(&amp;q-&gt;mmap_lock);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_core_queue_release);</div><div class='hunk'>@@ -2497,7 +2583,7 @@ __poll_t vb2_core_poll(struct vb2_queue *q, struct file *file,</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Start file I/O emulator only if streaming API has not been used yet.</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;num_buffers == 0 &amp;&amp; !vb2_fileio_is_active(q)) {</div><div class='add'>+	if (vb2_get_num_buffers(q) == 0 &amp;&amp; !vb2_fileio_is_active(q)) {</div><div class='ctx'> 		if (!q-&gt;is_output &amp;&amp; (q-&gt;io_modes &amp; VB2_READ) &amp;&amp;</div><div class='ctx'> 				(req_events &amp; (EPOLLIN | EPOLLRDNORM))) {</div><div class='ctx'> 			if (__vb2_init_fileio(q, 1))</div><div class='hunk'>@@ -2535,7 +2621,7 @@ __poll_t vb2_core_poll(struct vb2_queue *q, struct file *file,</div><div class='ctx'> 	 * For output streams you can call write() as long as there are fewer</div><div class='ctx'> 	 * buffers queued than there are buffers available.</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;is_output &amp;&amp; q-&gt;fileio &amp;&amp; q-&gt;queued_count &lt; q-&gt;num_buffers)</div><div class='add'>+	if (q-&gt;is_output &amp;&amp; q-&gt;fileio &amp;&amp; q-&gt;queued_count &lt; vb2_get_num_buffers(q))</div><div class='ctx'> 		return EPOLLOUT | EPOLLWRNORM;</div><div class='ctx'> </div><div class='ctx'> 	if (list_empty(&amp;q-&gt;done_list)) {</div><div class='hunk'>@@ -2584,8 +2670,8 @@ struct vb2_fileio_buf {</div><div class='ctx'>  * struct vb2_fileio_data - queue context used by file io emulator</div><div class='ctx'>  *</div><div class='ctx'>  * @cur_index:	the index of the buffer currently being read from or</div><div class='del'>- *		written to. If equal to q-&gt;num_buffers then a new buffer</div><div class='del'>- *		must be dequeued.</div><div class='add'>+ *		written to. If equal to number of buffers in the vb2_queue</div><div class='add'>+ *		then a new buffer must be dequeued.</div><div class='ctx'>  * @initial_index: in the read() case all buffers are queued up immediately</div><div class='ctx'>  *		in __vb2_init_fileio() and __vb2_perform_fileio() just cycles</div><div class='ctx'>  *		buffers. However, in the write() case no buffers are initially</div><div class='hunk'>@@ -2595,9 +2681,9 @@ struct vb2_fileio_buf {</div><div class='ctx'>  *		buffers. This means that initially __vb2_perform_fileio()</div><div class='ctx'>  *		needs to know what buffer index to use when it is queuing up</div><div class='ctx'>  *		the buffers for the first time. That initial index is stored</div><div class='del'>- *		in this field. Once it is equal to q-&gt;num_buffers all</div><div class='del'>- *		available buffers have been queued and __vb2_perform_fileio()</div><div class='del'>- *		should start the normal dequeue/queue cycle.</div><div class='add'>+ *		in this field. Once it is equal to number of buffers in the</div><div class='add'>+ *		vb2_queue all available buffers have been queued and</div><div class='add'>+ *		__vb2_perform_fileio() should start the normal dequeue/queue cycle.</div><div class='ctx'>  *</div><div class='ctx'>  * vb2 provides a compatibility layer and emulator of file io (read and</div><div class='ctx'>  * write) calls on top of streaming API. For proper operation it required</div><div class='hunk'>@@ -2625,6 +2711,7 @@ struct vb2_fileio_data {</div><div class='ctx'> static int __vb2_init_fileio(struct vb2_queue *q, int read)</div><div class='ctx'> {</div><div class='ctx'> 	struct vb2_fileio_data *fileio;</div><div class='add'>+	struct vb2_buffer *vb;</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> 	unsigned int count = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2644,13 +2731,18 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Check if streaming api has not been already activated.</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;streaming || q-&gt;num_buffers &gt; 0)</div><div class='add'>+	if (q-&gt;streaming || vb2_get_num_buffers(q) &gt; 0)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Start with count 1, driver can increase it in queue_setup()</div><div class='add'>+	 * Start with q-&gt;min_queued_buffers + 1, driver can increase it in</div><div class='add'>+	 * queue_setup()</div><div class='add'>+	 *</div><div class='add'>+	 * 'min_queued_buffers' buffers need to be queued up before you</div><div class='add'>+	 * can start streaming, plus 1 for userspace (or in this case,</div><div class='add'>+	 * kernelspace) processing.</div><div class='ctx'> 	 */</div><div class='del'>-	count = 1;</div><div class='add'>+	count = max(2, q-&gt;min_queued_buffers + 1);</div><div class='ctx'> </div><div class='ctx'> 	dprintk(q, 3, "setting up file io: mode %s, count %d, read_once %d, write_immediately %d\n",</div><div class='ctx'> 		(read) ? "read" : "write", count, q-&gt;fileio_read_once,</div><div class='hunk'>@@ -2676,10 +2768,17 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read)</div><div class='ctx'> 		goto err_kfree;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='add'>+	 * Userspace can never add or delete buffers later, so there</div><div class='add'>+	 * will never be holes. It is safe to assume that vb2_get_buffer(q, 0)</div><div class='add'>+	 * will always return a valid vb pointer</div><div class='add'>+	 */</div><div class='add'>+	vb = vb2_get_buffer(q, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='ctx'> 	 * Check if plane_count is correct</div><div class='ctx'> 	 * (multiplane buffers are not supported).</div><div class='ctx'> 	 */</div><div class='del'>-	if (q-&gt;bufs[0]-&gt;num_planes != 1) {</div><div class='add'>+	if (vb-&gt;num_planes != 1) {</div><div class='ctx'> 		ret = -EBUSY;</div><div class='ctx'> 		goto err_reqbufs;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2687,13 +2786,16 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read)</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Get kernel address of each buffer.</div><div class='ctx'> 	 */</div><div class='del'>-	for (i = 0; i &lt; q-&gt;num_buffers; i++) {</div><div class='del'>-		fileio-&gt;bufs[i].vaddr = vb2_plane_vaddr(q-&gt;bufs[i], 0);</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(q); i++) {</div><div class='add'>+		/* vb can never be NULL when using fileio. */</div><div class='add'>+		vb = vb2_get_buffer(q, i);</div><div class='add'>+</div><div class='add'>+		fileio-&gt;bufs[i].vaddr = vb2_plane_vaddr(vb, 0);</div><div class='ctx'> 		if (fileio-&gt;bufs[i].vaddr == NULL) {</div><div class='ctx'> 			ret = -EINVAL;</div><div class='ctx'> 			goto err_reqbufs;</div><div class='ctx'> 		}</div><div class='del'>-		fileio-&gt;bufs[i].size = vb2_plane_size(q-&gt;bufs[i], 0);</div><div class='add'>+		fileio-&gt;bufs[i].size = vb2_plane_size(vb, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2703,18 +2805,23 @@ static int __vb2_init_fileio(struct vb2_queue *q, int read)</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Queue all buffers.</div><div class='ctx'> 		 */</div><div class='del'>-		for (i = 0; i &lt; q-&gt;num_buffers; i++) {</div><div class='del'>-			ret = vb2_core_qbuf(q, i, NULL, NULL);</div><div class='add'>+		for (i = 0; i &lt; vb2_get_num_buffers(q); i++) {</div><div class='add'>+			struct vb2_buffer *vb2 = vb2_get_buffer(q, i);</div><div class='add'>+</div><div class='add'>+			if (!vb2)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			ret = vb2_core_qbuf(q, vb2, NULL, NULL);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				goto err_reqbufs;</div><div class='ctx'> 			fileio-&gt;bufs[i].queued = 1;</div><div class='ctx'> 		}</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * All buffers have been queued, so mark that by setting</div><div class='del'>-		 * initial_index to q-&gt;num_buffers</div><div class='add'>+		 * initial_index to the number of buffers in the vb2_queue</div><div class='ctx'> 		 */</div><div class='del'>-		fileio-&gt;initial_index = q-&gt;num_buffers;</div><div class='del'>-		fileio-&gt;cur_index = q-&gt;num_buffers;</div><div class='add'>+		fileio-&gt;initial_index = vb2_get_num_buffers(q);</div><div class='add'>+		fileio-&gt;cur_index = fileio-&gt;initial_index;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2807,7 +2914,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_</div><div class='ctx'> 	 * Check if we need to dequeue the buffer.</div><div class='ctx'> 	 */</div><div class='ctx'> 	index = fileio-&gt;cur_index;</div><div class='del'>-	if (index &gt;= q-&gt;num_buffers) {</div><div class='add'>+	if (index &gt;= vb2_get_num_buffers(q)) {</div><div class='ctx'> 		struct vb2_buffer *b;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -2821,15 +2928,17 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_</div><div class='ctx'> </div><div class='ctx'> 		fileio-&gt;cur_index = index;</div><div class='ctx'> 		buf = &amp;fileio-&gt;bufs[index];</div><div class='del'>-		b = q-&gt;bufs[index];</div><div class='add'>+</div><div class='add'>+		/* b can never be NULL when using fileio. */</div><div class='add'>+		b = vb2_get_buffer(q, index);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Get number of bytes filled by the driver</div><div class='ctx'> 		 */</div><div class='ctx'> 		buf-&gt;pos = 0;</div><div class='ctx'> 		buf-&gt;queued = 0;</div><div class='del'>-		buf-&gt;size = read ? vb2_get_plane_payload(q-&gt;bufs[index], 0)</div><div class='del'>-				 : vb2_plane_size(q-&gt;bufs[index], 0);</div><div class='add'>+		buf-&gt;size = read ? vb2_get_plane_payload(b, 0)</div><div class='add'>+				 : vb2_plane_size(b, 0);</div><div class='ctx'> 		/* Compensate for data_offset on read in the multiplanar case. */</div><div class='ctx'> 		if (is_multiplanar &amp;&amp; read &amp;&amp;</div><div class='ctx'> 				b-&gt;planes[0].data_offset &lt; buf-&gt;size) {</div><div class='hunk'>@@ -2872,7 +2981,8 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_</div><div class='ctx'> 	 * Queue next buffer if required.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (buf-&gt;pos == buf-&gt;size || (!read &amp;&amp; fileio-&gt;write_immediately)) {</div><div class='del'>-		struct vb2_buffer *b = q-&gt;bufs[index];</div><div class='add'>+		/* b can never be NULL when using fileio. */</div><div class='add'>+		struct vb2_buffer *b = vb2_get_buffer(q, index);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Check if this is the last buffer to read.</div><div class='hunk'>@@ -2889,7 +2999,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_</div><div class='ctx'> </div><div class='ctx'> 		if (copy_timestamp)</div><div class='ctx'> 			b-&gt;timestamp = ktime_get_ns();</div><div class='del'>-		ret = vb2_core_qbuf(q, index, NULL, NULL);</div><div class='add'>+		ret = vb2_core_qbuf(q, b, NULL, NULL);</div><div class='ctx'> 		dprintk(q, 5, "vb2_qbuf result: %d\n", ret);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -2899,20 +3009,20 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_</div><div class='ctx'> 		 */</div><div class='ctx'> 		buf-&gt;pos = 0;</div><div class='ctx'> 		buf-&gt;queued = 1;</div><div class='del'>-		buf-&gt;size = vb2_plane_size(q-&gt;bufs[index], 0);</div><div class='add'>+		buf-&gt;size = vb2_plane_size(b, 0);</div><div class='ctx'> 		fileio-&gt;q_count += 1;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If we are queuing up buffers for the first time, then</div><div class='ctx'> 		 * increase initial_index by one.</div><div class='ctx'> 		 */</div><div class='del'>-		if (fileio-&gt;initial_index &lt; q-&gt;num_buffers)</div><div class='add'>+		if (fileio-&gt;initial_index &lt; vb2_get_num_buffers(q))</div><div class='ctx'> 			fileio-&gt;initial_index++;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The next buffer to use is either a buffer that's going to be</div><div class='del'>-		 * queued for the first time (initial_index &lt; q-&gt;num_buffers)</div><div class='del'>-		 * or it is equal to q-&gt;num_buffers, meaning that the next</div><div class='del'>-		 * time we need to dequeue a buffer since we've now queued up</div><div class='del'>-		 * all the 'first time' buffers.</div><div class='add'>+		 * queued for the first time (initial_index &lt; number of buffers in the vb2_queue)</div><div class='add'>+		 * or it is equal to the number of buffers in the vb2_queue,</div><div class='add'>+		 * meaning that the next time we need to dequeue a buffer since</div><div class='add'>+		 * we've now queued up all the 'first time' buffers.</div><div class='ctx'> 		 */</div><div class='ctx'> 		fileio-&gt;cur_index = fileio-&gt;initial_index;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2957,7 +3067,7 @@ static int vb2_thread(void *data)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (q-&gt;is_output) {</div><div class='del'>-		prequeue = q-&gt;num_buffers;</div><div class='add'>+		prequeue = vb2_get_num_buffers(q);</div><div class='ctx'> 		copy_timestamp = q-&gt;copy_timestamp;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2970,7 +3080,9 @@ static int vb2_thread(void *data)</div><div class='ctx'> 		 * Call vb2_dqbuf to get buffer back.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (prequeue) {</div><div class='del'>-			vb = q-&gt;bufs[index++];</div><div class='add'>+			vb = vb2_get_buffer(q, index++);</div><div class='add'>+			if (!vb)</div><div class='add'>+				continue;</div><div class='ctx'> 			prequeue--;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			call_void_qop(q, wait_finish, q);</div><div class='hunk'>@@ -2979,7 +3091,7 @@ static int vb2_thread(void *data)</div><div class='ctx'> 			call_void_qop(q, wait_prepare, q);</div><div class='ctx'> 			dprintk(q, 5, "file io: vb2_dqbuf result: %d\n", ret);</div><div class='ctx'> 			if (!ret)</div><div class='del'>-				vb = q-&gt;bufs[index];</div><div class='add'>+				vb = vb2_get_buffer(q, index);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (ret || threadio-&gt;stop)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -2992,7 +3104,7 @@ static int vb2_thread(void *data)</div><div class='ctx'> 		if (copy_timestamp)</div><div class='ctx'> 			vb-&gt;timestamp = ktime_get_ns();</div><div class='ctx'> 		if (!threadio-&gt;stop)</div><div class='del'>-			ret = vb2_core_qbuf(q, vb-&gt;index, NULL, NULL);</div><div class='add'>+			ret = vb2_core_qbuf(q, vb, NULL, NULL);</div><div class='ctx'> 		call_void_qop(q, wait_prepare, q);</div><div class='ctx'> 		if (ret || threadio-&gt;stop)</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/media/common/videobuf2/videobuf2-dma-sg.c b/drivers/media/common/videobuf2/videobuf2-dma-sg.c<br/>index 28f3fdfe23a2..6975a71d740f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-dma-sg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/common/videobuf2/videobuf2-dma-sg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-dma-sg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-dma-sg.c</a></div><div class='hunk'>@@ -487,9 +487,15 @@ vb2_dma_sg_dmabuf_ops_end_cpu_access(struct dma_buf *dbuf,</div><div class='ctx'> static int vb2_dma_sg_dmabuf_ops_vmap(struct dma_buf *dbuf,</div><div class='ctx'> 				      struct iosys_map *map)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_dma_sg_buf *buf = dbuf-&gt;priv;</div><div class='add'>+	struct vb2_dma_sg_buf *buf;</div><div class='add'>+	void *vaddr;</div><div class='add'>+</div><div class='add'>+	buf = dbuf-&gt;priv;</div><div class='add'>+	vaddr = vb2_dma_sg_vaddr(buf-&gt;vb, buf);</div><div class='add'>+	if (!vaddr)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	iosys_map_set_vaddr(map, buf-&gt;vaddr);</div><div class='add'>+	iosys_map_set_vaddr(map, vaddr);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c<br/>index c7a54d82a55e..54d572c3b515 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/common/videobuf2/videobuf2-v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/common/videobuf2/videobuf2-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/common/videobuf2/videobuf2-v4l2.c</a></div><div class='hunk'>@@ -364,13 +364,12 @@ static void set_buffer_cache_hints(struct vb2_queue *q,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct media_device *mdev,</div><div class='del'>-				    struct v4l2_buffer *b, bool is_prepare,</div><div class='del'>-				    struct media_request **p_req)</div><div class='add'>+				    struct vb2_buffer *vb, struct v4l2_buffer *b,</div><div class='add'>+				    bool is_prepare, struct media_request **p_req)</div><div class='ctx'> {</div><div class='ctx'> 	const char *opname = is_prepare ? "prepare_buf" : "qbuf";</div><div class='ctx'> 	struct media_request *req;</div><div class='ctx'> 	struct vb2_v4l2_buffer *vbuf;</div><div class='del'>-	struct vb2_buffer *vb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (b-&gt;type != q-&gt;type) {</div><div class='hunk'>@@ -378,23 +377,11 @@ static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct media_device *md</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (b-&gt;index &gt;= q-&gt;num_buffers) {</div><div class='del'>-		dprintk(q, 1, "%s: buffer index out of range\n", opname);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (q-&gt;bufs[b-&gt;index] == NULL) {</div><div class='del'>-		/* Should never happen */</div><div class='del'>-		dprintk(q, 1, "%s: buffer is NULL\n", opname);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (b-&gt;memory != q-&gt;memory) {</div><div class='ctx'> 		dprintk(q, 1, "%s: invalid memory type\n", opname);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	vb = q-&gt;bufs[b-&gt;index];</div><div class='ctx'> 	vbuf = to_vb2_v4l2_buffer(vb);</div><div class='ctx'> 	ret = __verify_planes_array(vb, b);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -628,11 +615,22 @@ static const struct vb2_buf_ops v4l2_buf_ops = {</div><div class='ctx'> struct vb2_buffer *vb2_find_buffer(struct vb2_queue *q, u64 timestamp)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='add'>+	struct vb2_buffer *vb2;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; q-&gt;num_buffers; i++)</div><div class='del'>-		if (q-&gt;bufs[i]-&gt;copied_timestamp &amp;&amp;</div><div class='del'>-		    q-&gt;bufs[i]-&gt;timestamp == timestamp)</div><div class='del'>-			return vb2_get_buffer(q, i);</div><div class='add'>+	/*</div><div class='add'>+	 * This loop doesn't scale if there is a really large number of buffers.</div><div class='add'>+	 * Maybe something more efficient will be needed in this case.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; q-&gt;max_num_buffers; i++) {</div><div class='add'>+		vb2 = vb2_get_buffer(q, i);</div><div class='add'>+</div><div class='add'>+		if (!vb2)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (vb2-&gt;copied_timestamp &amp;&amp;</div><div class='add'>+		    vb2-&gt;timestamp == timestamp)</div><div class='add'>+			return vb2;</div><div class='add'>+	}</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_find_buffer);</div><div class='hunk'>@@ -660,14 +658,15 @@ int vb2_querybuf(struct vb2_queue *q, struct v4l2_buffer *b)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (b-&gt;index &gt;= q-&gt;num_buffers) {</div><div class='del'>-		dprintk(q, 1, "buffer index out of range\n");</div><div class='add'>+	vb = vb2_get_buffer(q, b-&gt;index);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		dprintk(q, 1, "can't find the requested buffer %u\n", b-&gt;index);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	vb = q-&gt;bufs[b-&gt;index];</div><div class='add'>+</div><div class='ctx'> 	ret = __verify_planes_array(vb, b);</div><div class='ctx'> 	if (!ret)</div><div class='del'>-		vb2_core_querybuf(q, b-&gt;index, b);</div><div class='add'>+		vb2_core_querybuf(q, vb, b);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(vb2_querybuf);</div><div class='hunk'>@@ -685,10 +684,8 @@ static void fill_buf_caps(struct vb2_queue *q, u32 *caps)</div><div class='ctx'> 		*caps |= V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF;</div><div class='ctx'> 	if (q-&gt;allow_cache_hints &amp;&amp; q-&gt;io_modes &amp; VB2_MMAP)</div><div class='ctx'> 		*caps |= V4L2_BUF_CAP_SUPPORTS_MMAP_CACHE_HINTS;</div><div class='del'>-#ifdef CONFIG_MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	if (q-&gt;supports_requests)</div><div class='ctx'> 		*caps |= V4L2_BUF_CAP_SUPPORTS_REQUESTS;</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void validate_memory_flags(struct vb2_queue *q,</div><div class='hunk'>@@ -723,6 +720,7 @@ EXPORT_SYMBOL_GPL(vb2_reqbufs);</div><div class='ctx'> int vb2_prepare_buf(struct vb2_queue *q, struct media_device *mdev,</div><div class='ctx'> 		    struct v4l2_buffer *b)</div><div class='ctx'> {</div><div class='add'>+	struct vb2_buffer *vb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (vb2_fileio_is_active(q)) {</div><div class='hunk'>@@ -733,9 +731,15 @@ int vb2_prepare_buf(struct vb2_queue *q, struct media_device *mdev,</div><div class='ctx'> 	if (b-&gt;flags &amp; V4L2_BUF_FLAG_REQUEST_FD)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = vb2_queue_or_prepare_buf(q, mdev, b, true, NULL);</div><div class='add'>+	vb = vb2_get_buffer(q, b-&gt;index);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		dprintk(q, 1, "can't find the requested buffer %u\n", b-&gt;index);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return ret ? ret : vb2_core_prepare_buf(q, b-&gt;index, b);</div><div class='add'>+	ret = vb2_queue_or_prepare_buf(q, mdev, vb, b, true, NULL);</div><div class='add'>+</div><div class='add'>+	return ret ? ret : vb2_core_prepare_buf(q, vb, b);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_prepare_buf);</div><div class='ctx'> </div><div class='hunk'>@@ -749,7 +753,9 @@ int vb2_create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create)</div><div class='ctx'> </div><div class='ctx'> 	fill_buf_caps(q, &amp;create-&gt;capabilities);</div><div class='ctx'> 	validate_memory_flags(q, create-&gt;memory, &amp;create-&gt;flags);</div><div class='del'>-	create-&gt;index = q-&gt;num_buffers;</div><div class='add'>+	create-&gt;index = vb2_get_num_buffers(q);</div><div class='add'>+	create-&gt;max_num_buffers = q-&gt;max_num_buffers;</div><div class='add'>+	create-&gt;capabilities |= V4L2_BUF_CAP_SUPPORTS_MAX_NUM_BUFFERS;</div><div class='ctx'> 	if (create-&gt;count == 0)</div><div class='ctx'> 		return ret != -EBUSY ? ret : 0;</div><div class='ctx'> </div><div class='hunk'>@@ -803,6 +809,7 @@ int vb2_qbuf(struct vb2_queue *q, struct media_device *mdev,</div><div class='ctx'> 	     struct v4l2_buffer *b)</div><div class='ctx'> {</div><div class='ctx'> 	struct media_request *req = NULL;</div><div class='add'>+	struct vb2_buffer *vb;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (vb2_fileio_is_active(q)) {</div><div class='hunk'>@@ -810,10 +817,16 @@ int vb2_qbuf(struct vb2_queue *q, struct media_device *mdev,</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = vb2_queue_or_prepare_buf(q, mdev, b, false, &amp;req);</div><div class='add'>+	vb = vb2_get_buffer(q, b-&gt;index);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		dprintk(q, 1, "can't find the requested buffer %u\n", b-&gt;index);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = vb2_queue_or_prepare_buf(q, mdev, vb, b, false, &amp;req);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='del'>-	ret = vb2_core_qbuf(q, b-&gt;index, b, req);</div><div class='add'>+	ret = vb2_core_qbuf(q, vb, b, req);</div><div class='ctx'> 	if (req)</div><div class='ctx'> 		media_request_put(req);</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -873,7 +886,15 @@ EXPORT_SYMBOL_GPL(vb2_streamoff);</div><div class='ctx'> </div><div class='ctx'> int vb2_expbuf(struct vb2_queue *q, struct v4l2_exportbuffer *eb)</div><div class='ctx'> {</div><div class='del'>-	return vb2_core_expbuf(q, &amp;eb-&gt;fd, eb-&gt;type, eb-&gt;index,</div><div class='add'>+	struct vb2_buffer *vb;</div><div class='add'>+</div><div class='add'>+	vb = vb2_get_buffer(q, eb-&gt;index);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		dprintk(q, 1, "can't find the requested buffer %u\n", eb-&gt;index);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return vb2_core_expbuf(q, &amp;eb-&gt;fd, eb-&gt;type, vb,</div><div class='ctx'> 				eb-&gt;plane, eb-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(vb2_expbuf);</div><div class='hunk'>@@ -1115,7 +1136,7 @@ int _vb2_fop_release(struct file *file, struct mutex *lock)</div><div class='ctx'> </div><div class='ctx'> 	if (lock)</div><div class='ctx'> 		mutex_lock(lock);</div><div class='del'>-	if (file-&gt;private_data == vdev-&gt;queue-&gt;owner) {</div><div class='add'>+	if (!vdev-&gt;queue-&gt;owner || file-&gt;private_data == vdev-&gt;queue-&gt;owner) {</div><div class='ctx'> 		vb2_queue_release(vdev-&gt;queue);</div><div class='ctx'> 		vdev-&gt;queue-&gt;owner = NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1243,7 +1264,7 @@ void vb2_video_unregister_device(struct video_device *vdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	get_device(&amp;vdev-&gt;dev);</div><div class='ctx'> 	video_unregister_device(vdev);</div><div class='del'>-	if (vdev-&gt;queue &amp;&amp; vdev-&gt;queue-&gt;owner) {</div><div class='add'>+	if (vdev-&gt;queue) {</div><div class='ctx'> 		struct mutex *lock = vdev-&gt;queue-&gt;lock ?</div><div class='ctx'> 			vdev-&gt;queue-&gt;lock : vdev-&gt;lock;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/dvb-core/dvb_vb2.c b/drivers/media/dvb-core/dvb_vb2.c<br/>index 909df82fed33..192a8230c4aa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/dvb-core/dvb_vb2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/dvb-core/dvb_vb2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/dvb-core/dvb_vb2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-core/dvb_vb2.c</a></div><div class='hunk'>@@ -167,17 +167,14 @@ int dvb_vb2_init(struct dvb_vb2_ctx *ctx, const char *name, int nonblocking)</div><div class='ctx'> </div><div class='ctx'> 	memset(ctx, 0, sizeof(struct dvb_vb2_ctx));</div><div class='ctx'> 	q-&gt;type = DVB_BUF_TYPE_CAPTURE;</div><div class='del'>-	/**capture type*/</div><div class='del'>-	q-&gt;is_output = 0;</div><div class='ctx'> 	/**only mmap is supported currently*/</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP;</div><div class='ctx'> 	q-&gt;drv_priv = ctx;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct dvb_buffer);</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	q-&gt;ops = &amp;dvb_vb2_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;buf_ops = &amp;dvb_vb2_buf_ops;</div><div class='del'>-	q-&gt;num_buffers = 0;</div><div class='ctx'> 	ret = vb2_core_queue_init(q);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ctx-&gt;state = DVB_VB2_STATE_NONE;</div><div class='hunk'>@@ -355,12 +352,13 @@ int dvb_vb2_reqbufs(struct dvb_vb2_ctx *ctx, struct dmx_requestbuffers *req)</div><div class='ctx'> int dvb_vb2_querybuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)</div><div class='ctx'> {</div><div class='ctx'> 	struct vb2_queue *q = &amp;ctx-&gt;vb_q;</div><div class='add'>+	struct vb2_buffer *vb2 = vb2_get_buffer(q, b-&gt;index);</div><div class='ctx'> </div><div class='del'>-	if (b-&gt;index &gt;= q-&gt;num_buffers) {</div><div class='del'>-		dprintk(1, "[%s] buffer index out of range\n", ctx-&gt;name);</div><div class='add'>+	if (!vb2) {</div><div class='add'>+		dprintk(1, "[%s] invalid buffer index\n", ctx-&gt;name);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	vb2_core_querybuf(&amp;ctx-&gt;vb_q, b-&gt;index, b);</div><div class='add'>+	vb2_core_querybuf(&amp;ctx-&gt;vb_q, vb2, b);</div><div class='ctx'> 	dprintk(3, "[%s] index=%d\n", ctx-&gt;name, b-&gt;index);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -370,7 +368,7 @@ int dvb_vb2_expbuf(struct dvb_vb2_ctx *ctx, struct dmx_exportbuffer *exp)</div><div class='ctx'> 	struct vb2_queue *q = &amp;ctx-&gt;vb_q;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = vb2_core_expbuf(&amp;ctx-&gt;vb_q, &amp;exp-&gt;fd, q-&gt;type, exp-&gt;index,</div><div class='add'>+	ret = vb2_core_expbuf(&amp;ctx-&gt;vb_q, &amp;exp-&gt;fd, q-&gt;type, q-&gt;bufs[exp-&gt;index],</div><div class='ctx'> 			      0, exp-&gt;flags);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dprintk(1, "[%s] index=%d errno=%d\n", ctx-&gt;name,</div><div class='hunk'>@@ -385,13 +383,14 @@ int dvb_vb2_expbuf(struct dvb_vb2_ctx *ctx, struct dmx_exportbuffer *exp)</div><div class='ctx'> int dvb_vb2_qbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)</div><div class='ctx'> {</div><div class='ctx'> 	struct vb2_queue *q = &amp;ctx-&gt;vb_q;</div><div class='add'>+	struct vb2_buffer *vb2 = vb2_get_buffer(q, b-&gt;index);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (b-&gt;index &gt;= q-&gt;num_buffers) {</div><div class='del'>-		dprintk(1, "[%s] buffer index out of range\n", ctx-&gt;name);</div><div class='add'>+	if (!vb2) {</div><div class='add'>+		dprintk(1, "[%s] invalid buffer index\n", ctx-&gt;name);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-	ret = vb2_core_qbuf(&amp;ctx-&gt;vb_q, b-&gt;index, b, NULL);</div><div class='add'>+	ret = vb2_core_qbuf(&amp;ctx-&gt;vb_q, vb2, b, NULL);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dprintk(1, "[%s] index=%d errno=%d\n", ctx-&gt;name,</div><div class='ctx'> 			b-&gt;index, ret);</div><div class='head'>diff --git a/drivers/media/dvb-core/dvbdev.c b/drivers/media/dvb-core/dvbdev.c<br/>index 305bb21d843c..49f0eb7d0b9d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/dvb-core/dvbdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/dvb-core/dvbdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/dvb-core/dvbdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-core/dvbdev.c</a></div><div class='hunk'>@@ -104,6 +104,8 @@ static int dvb_device_open(struct inode *inode, struct file *file)</div><div class='ctx'> 			err = file-&gt;f_op-&gt;open(inode, file);</div><div class='ctx'> 		up_read(&amp;minor_rwsem);</div><div class='ctx'> 		mutex_unlock(&amp;dvbdev_mutex);</div><div class='add'>+		if (err)</div><div class='add'>+			dvb_device_put(dvbdev);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> fail:</div><div class='head'>diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c<br/>index 26c67ef05d13..e0272054fca5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/dvb-frontends/m88ds3103.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/dvb-frontends/m88ds3103.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/dvb-frontends/m88ds3103.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-frontends/m88ds3103.c</a></div><div class='hunk'>@@ -1894,7 +1894,7 @@ static int m88ds3103_probe(struct i2c_client *client)</div><div class='ctx'> 		/* get frontend address */</div><div class='ctx'> 		ret = regmap_read(dev-&gt;regmap, 0x29, &amp;utmp);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			goto err_kfree;</div><div class='add'>+			goto err_del_adapters;</div><div class='ctx'> 		dev-&gt;dt_addr = ((utmp &amp; 0x80) == 0) ? 0x42 &gt;&gt; 1 : 0x40 &gt;&gt; 1;</div><div class='ctx'> 		dev_dbg(&amp;client-&gt;dev, "dt addr is 0x%02x\n", dev-&gt;dt_addr);</div><div class='ctx'> </div><div class='hunk'>@@ -1902,11 +1902,14 @@ static int m88ds3103_probe(struct i2c_client *client)</div><div class='ctx'> 						      dev-&gt;dt_addr);</div><div class='ctx'> 		if (IS_ERR(dev-&gt;dt_client)) {</div><div class='ctx'> 			ret = PTR_ERR(dev-&gt;dt_client);</div><div class='del'>-			goto err_kfree;</div><div class='add'>+			goto err_del_adapters;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+err_del_adapters:</div><div class='add'>+	i2c_mux_del_adapters(dev-&gt;muxc);</div><div class='ctx'> err_kfree:</div><div class='ctx'> 	kfree(dev);</div><div class='ctx'> err:</div><div class='head'>diff --git a/drivers/media/dvb-frontends/rtl2832_sdr.c b/drivers/media/dvb-frontends/rtl2832_sdr.c<br/>index 02c619e51641..023db6e793f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/dvb-frontends/rtl2832_sdr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/dvb-frontends/rtl2832_sdr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/dvb-frontends/rtl2832_sdr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/dvb-frontends/rtl2832_sdr.c</a></div><div class='hunk'>@@ -439,12 +439,13 @@ static int rtl2832_sdr_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct rtl2832_sdr_dev *dev = vb2_get_drv_priv(vq);</div><div class='ctx'> 	struct platform_device *pdev = dev-&gt;pdev;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "nbuffers=%d\n", *nbuffers);</div><div class='ctx'> </div><div class='ctx'> 	/* Need at least 8 buffers */</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 8)</div><div class='del'>-		*nbuffers = 8 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 8)</div><div class='add'>+		*nbuffers = 8 - q_num_bufs;</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	sizes[0] = PAGE_ALIGN(dev-&gt;buffersize);</div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "nbuffers=%d sizes[0]=%d\n", *nbuffers, sizes[0]);</div><div class='head'>diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig<br/>index 59ee0ca2c978..4c3435921f19 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/Kconfig</a></div><div class='hunk'>@@ -41,6 +41,16 @@ config VIDEO_APTINA_PLL</div><div class='ctx'> config VIDEO_CCS_PLL</div><div class='ctx'> 	tristate</div><div class='ctx'> </div><div class='add'>+config VIDEO_ALVIUM_CSI2</div><div class='add'>+	tristate "Allied Vision ALVIUM MIPI CSI-2 camera support"</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='add'>+	help</div><div class='add'>+	  This is a Video4Linux2 sensor-level driver for the Allied Vision</div><div class='add'>+	  ALVIUM camera connected via MIPI CSI-2 interface.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called alvium-csi2.</div><div class='add'>+</div><div class='ctx'> config VIDEO_AR0521</div><div class='ctx'> 	tristate "ON Semiconductor AR0521 sensor support"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -50,6 +60,26 @@ config VIDEO_AR0521</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the</div><div class='ctx'> 	  module will be called ar0521.</div><div class='ctx'> </div><div class='add'>+config VIDEO_GC0308</div><div class='add'>+	tristate "GalaxyCore GC0308 sensor support"</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='add'>+	help</div><div class='add'>+	  This is a Video4Linux2 sensor driver for the GalaxyCore</div><div class='add'>+	  GC0308 camera.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called gc0308.</div><div class='add'>+</div><div class='add'>+config VIDEO_GC2145</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='add'>+	tristate "GalaxyCore GC2145 sensor support"</div><div class='add'>+	help</div><div class='add'>+	  This is a V4L2 sensor-level driver for GalaxyCore GC2145</div><div class='add'>+	  2 Mpixel camera.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called gc2145.</div><div class='add'>+</div><div class='ctx'> config VIDEO_HI556</div><div class='ctx'> 	tristate "Hynix Hi-556 sensor support"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -455,6 +485,16 @@ config VIDEO_OV5695</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the</div><div class='ctx'> 	  module will be called ov5695.</div><div class='ctx'> </div><div class='add'>+config VIDEO_OV64A40</div><div class='add'>+	tristate "OmniVision OV64A40 sensor support"</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='add'>+	help</div><div class='add'>+	  This is a Video4Linux2 sensor driver for the OmniVision</div><div class='add'>+	  OV64A40 camera.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called ov64a40.</div><div class='add'>+</div><div class='ctx'> config VIDEO_OV6650</div><div class='ctx'> 	tristate "OmniVision OV6650 sensor support"</div><div class='ctx'> 	help</div><div class='hunk'>@@ -628,6 +668,23 @@ source "drivers/media/i2c/et8ek8/Kconfig"</div><div class='ctx'> </div><div class='ctx'> endif</div><div class='ctx'> </div><div class='add'>+menu "Camera ISPs"</div><div class='add'>+	visible if MEDIA_CAMERA_SUPPORT</div><div class='add'>+</div><div class='add'>+config VIDEO_THP7312</div><div class='add'>+	tristate "THine THP7312 support"</div><div class='add'>+	depends on I2C</div><div class='add'>+	select FW_LOADER</div><div class='add'>+	select MEDIA_CONTROLLER</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='add'>+	select V4L2_FWNODE</div><div class='add'>+	select VIDEO_V4L2_SUBDEV_API</div><div class='add'>+	help</div><div class='add'>+	  This is a Video4Linux2 sensor-level driver for the THine</div><div class='add'>+	  THP7312 ISP.</div><div class='add'>+</div><div class='add'>+endmenu</div><div class='add'>+</div><div class='ctx'> menu "Lens drivers"</div><div class='ctx'> 	visible if MEDIA_CAMERA_SUPPORT</div><div class='ctx'> </div><div class='hunk'>@@ -1186,6 +1243,21 @@ config VIDEO_TW2804</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the</div><div class='ctx'> 	  module will be called tw2804.</div><div class='ctx'> </div><div class='add'>+config VIDEO_TW9900</div><div class='add'>+	tristate "Techwell TW9900 video decoder"</div><div class='add'>+	depends on GPIOLIB</div><div class='add'>+	depends on VIDEO_DEV &amp;&amp; I2C</div><div class='add'>+	depends on PM</div><div class='add'>+	select MEDIA_CONTROLLER</div><div class='add'>+	select VIDEO_V4L2_SUBDEV_API</div><div class='add'>+	select V4L2_ASYNC</div><div class='add'>+	help</div><div class='add'>+	  Support for the Techwell TW9900 multi-standard video decoder.</div><div class='add'>+	  It supports NTSC, PAL standards with auto-detection features.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called tw9900.</div><div class='add'>+</div><div class='ctx'> config VIDEO_TW9903</div><div class='ctx'> 	tristate "Techwell TW9903 video decoder"</div><div class='ctx'> 	depends on VIDEO_DEV &amp;&amp; I2C</div><div class='hunk'>@@ -1432,6 +1504,7 @@ config VIDEO_ST_MIPID02</div><div class='ctx'> 	depends on I2C &amp;&amp; VIDEO_DEV</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='ctx'> 	select VIDEO_V4L2_SUBDEV_API</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='ctx'> 	select V4L2_FWNODE</div><div class='ctx'> 	help</div><div class='ctx'> 	  Support for STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge.</div><div class='head'>diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile<br/>index f5010f80a21f..dfbe6448b549 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/Makefile</a></div><div class='hunk'>@@ -17,6 +17,7 @@ obj-$(CONFIG_VIDEO_ADV7604) += adv7604.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_ADV7842) += adv7842.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_AK7375) += ak7375.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_AK881X) += ak881x.o</div><div class='add'>+obj-$(CONFIG_VIDEO_ALVIUM_CSI2) += alvium-csi2.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_AR0521) += ar0521.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_BT819) += bt819.o</div><div class='hunk'>@@ -36,6 +37,8 @@ obj-$(CONFIG_VIDEO_DW9719) += dw9719.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_DW9768) += dw9768.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_DW9807_VCM) += dw9807-vcm.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/</div><div class='add'>+obj-$(CONFIG_VIDEO_GC0308) += gc0308.o</div><div class='add'>+obj-$(CONFIG_VIDEO_GC2145) += gc2145.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_HI556) += hi556.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_HI846) += hi846.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_HI847) += hi847.o</div><div class='hunk'>@@ -92,6 +95,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV5675) += ov5675.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV5693) += ov5693.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV5695) += ov5695.o</div><div class='add'>+obj-$(CONFIG_VIDEO_OV64A40) += ov64a40.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV6650) += ov6650.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV7251) += ov7251.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_OV7640) += ov7640.o</div><div class='hunk'>@@ -128,6 +132,7 @@ obj-$(CONFIG_VIDEO_TDA7432) += tda7432.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TDA9840) += tda9840.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TEA6415C) += tea6415c.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TEA6420) += tea6420.o</div><div class='add'>+obj-$(CONFIG_VIDEO_THP7312) += thp7312.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_THS7303) += ths7303.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_THS8200) += ths8200.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TLV320AIC23B) += tlv320aic23b.o</div><div class='hunk'>@@ -136,6 +141,7 @@ obj-$(CONFIG_VIDEO_TVP514X) += tvp514x.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TVP5150) += tvp5150.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TVP7002) += tvp7002.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TW2804) += tw2804.o</div><div class='add'>+obj-$(CONFIG_VIDEO_TW9900) += tw9900.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TW9903) += tw9903.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TW9906) += tw9906.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_TW9910) += tw9910.o</div><div class='head'>diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c<br/>index 54134473186b..409b9a37f018 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7180.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv7180.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7180.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7180.c</a></div><div class='hunk'>@@ -463,11 +463,19 @@ static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int adv7180_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int adv7180_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct adv7180_state *state = to_state(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (state-&gt;curr_norm &amp; V4L2_STD_525_60) {</div><div class='ctx'> 		fi-&gt;interval.numerator = 1001;</div><div class='ctx'> 		fi-&gt;interval.denominator = 30000;</div><div class='hunk'>@@ -769,7 +777,7 @@ static int adv7180_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct adv7180_state *state = to_state(sd);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		format-&gt;format = *v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		adv7180_mbus_fmt(sd, &amp;format-&gt;format);</div><div class='ctx'> 		format-&gt;format.field = state-&gt;field;</div><div class='hunk'>@@ -806,15 +814,15 @@ static int adv7180_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 			adv7180_set_power(state, true);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*framefmt = format-&gt;format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int adv7180_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int adv7180_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY</div><div class='hunk'>@@ -913,7 +921,6 @@ static int adv7180_subscribe_event(struct v4l2_subdev *sd,</div><div class='ctx'> static const struct v4l2_subdev_video_ops adv7180_video_ops = {</div><div class='ctx'> 	.s_std = adv7180_s_std,</div><div class='ctx'> 	.g_std = adv7180_g_std,</div><div class='del'>-	.g_frame_interval = adv7180_g_frame_interval,</div><div class='ctx'> 	.querystd = adv7180_querystd,</div><div class='ctx'> 	.g_input_status = adv7180_g_input_status,</div><div class='ctx'> 	.s_routing = adv7180_s_routing,</div><div class='hunk'>@@ -929,10 +936,10 @@ static const struct v4l2_subdev_core_ops adv7180_core_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {</div><div class='del'>-	.init_cfg = adv7180_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = adv7180_enum_mbus_code,</div><div class='ctx'> 	.set_fmt = adv7180_set_pad_format,</div><div class='ctx'> 	.get_fmt = adv7180_get_pad_format,</div><div class='add'>+	.get_frame_interval = adv7180_get_frame_interval,</div><div class='ctx'> 	.get_mbus_config = adv7180_get_mbus_config,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -947,6 +954,10 @@ static const struct v4l2_subdev_ops adv7180_ops = {</div><div class='ctx'> 	.sensor = &amp;adv7180_sensor_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops adv7180_internal_ops = {</div><div class='add'>+	.init_state = adv7180_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static irqreturn_t adv7180_irq(int irq, void *devid)</div><div class='ctx'> {</div><div class='ctx'> 	struct adv7180_state *state = devid;</div><div class='hunk'>@@ -1458,6 +1469,7 @@ static int adv7180_probe(struct i2c_client *client)</div><div class='ctx'> 	state-&gt;input = 0;</div><div class='ctx'> 	sd = &amp;state-&gt;sd;</div><div class='ctx'> 	v4l2_i2c_subdev_init(sd, client, &amp;adv7180_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;adv7180_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> </div><div class='ctx'> 	ret = adv7180_init_controls(state);</div><div class='head'>diff --git a/drivers/media/i2c/adv7183.c b/drivers/media/i2c/adv7183.c<br/>index 3659feafac69..2a2cace4a153 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7183.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv7183.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7183.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7183.c</a></div><div class='hunk'>@@ -442,8 +442,6 @@ static int adv7183_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		decoder-&gt;fmt = *fmt;</div><div class='del'>-	else</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *fmt;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/adv748x/adv748x-afe.c b/drivers/media/i2c/adv748x/adv748x-afe.c<br/>index 00095c7762c2..50d9fbadbe38 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-afe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv748x/adv748x-afe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-afe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-afe.c</a></div><div class='hunk'>@@ -354,8 +354,8 @@ static int adv748x_afe_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (sdformat-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mbusformat = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							sdformat-&gt;pad);</div><div class='add'>+		mbusformat = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							  sdformat-&gt;pad);</div><div class='ctx'> 		sdformat-&gt;format = *mbusformat;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		adv748x_afe_fill_format(afe, &amp;sdformat-&gt;format);</div><div class='hunk'>@@ -378,7 +378,7 @@ static int adv748x_afe_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (sdformat-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return adv748x_afe_get_format(sd, sd_state, sdformat);</div><div class='ctx'> </div><div class='del'>-	mbusformat = v4l2_subdev_get_try_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	mbusformat = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> 	*mbusformat = sdformat-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/adv748x/adv748x-csi2.c b/drivers/media/i2c/adv748x/adv748x-csi2.c<br/>index a5a7cb228896..5b265b722394 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv748x/adv748x-csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-csi2.c</a></div><div class='hunk'>@@ -147,7 +147,7 @@ adv748x_csi2_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct adv748x_csi2 *tx = adv748x_sd_to_csi2(sd);</div><div class='ctx'> </div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;tx-&gt;format;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/i2c/adv748x/adv748x-hdmi.c b/drivers/media/i2c/adv748x/adv748x-hdmi.c<br/>index 400d71c2745c..ec151dc69c23 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-hdmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv748x/adv748x-hdmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv748x/adv748x-hdmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv748x/adv748x-hdmi.c</a></div><div class='hunk'>@@ -441,8 +441,8 @@ static int adv748x_hdmi_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (sdformat-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mbusformat = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							sdformat-&gt;pad);</div><div class='add'>+		mbusformat = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							  sdformat-&gt;pad);</div><div class='ctx'> 		sdformat-&gt;format = *mbusformat;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		adv748x_hdmi_fill_format(hdmi, &amp;sdformat-&gt;format);</div><div class='hunk'>@@ -464,7 +464,7 @@ static int adv748x_hdmi_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (sdformat-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return adv748x_hdmi_get_format(sd, sd_state, sdformat);</div><div class='ctx'> </div><div class='del'>-	mbusformat = v4l2_subdev_get_try_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	mbusformat = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> 	*mbusformat = sdformat-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/adv7511-v4l2.c b/drivers/media/i2c/adv7511-v4l2.c<br/>index a9183d9282fd..0f780eb6ef63 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7511-v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv7511-v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7511-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7511-v4l2.c</a></div><div class='hunk'>@@ -1238,7 +1238,7 @@ static int adv7511_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		format-&gt;format.code = fmt-&gt;code;</div><div class='ctx'> 		format-&gt;format.colorspace = fmt-&gt;colorspace;</div><div class='ctx'> 		format-&gt;format.ycbcr_enc = fmt-&gt;ycbcr_enc;</div><div class='hunk'>@@ -1293,7 +1293,7 @@ static int adv7511_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		fmt-&gt;code = format-&gt;format.code;</div><div class='ctx'> 		fmt-&gt;colorspace = format-&gt;format.colorspace;</div><div class='ctx'> 		fmt-&gt;ycbcr_enc = format-&gt;format.ycbcr_enc;</div><div class='head'>diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c<br/>index b202a85fbeaa..810fa8826f30 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7604.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv7604.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7604.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7604.c</a></div><div class='hunk'>@@ -1929,7 +1929,7 @@ static int adv76xx_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		format-&gt;format.code = fmt-&gt;code;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		format-&gt;format.code = state-&gt;format-&gt;code;</div><div class='hunk'>@@ -1978,7 +1978,7 @@ static int adv76xx_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		fmt-&gt;code = format-&gt;format.code;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		state-&gt;format = info;</div><div class='head'>diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c<br/>index c1664a3620c8..2ad0f9f5503d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7842.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/adv7842.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/adv7842.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/adv7842.c</a></div><div class='hunk'>@@ -2087,7 +2087,7 @@ static int adv7842_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		format-&gt;format.code = fmt-&gt;code;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		format-&gt;format.code = state-&gt;format-&gt;code;</div><div class='hunk'>@@ -2119,7 +2119,7 @@ static int adv7842_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		fmt-&gt;code = format-&gt;format.code;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		state-&gt;format = info;</div><div class='head'>diff --git a/drivers/media/i2c/ak7375.c b/drivers/media/i2c/ak7375.c<br/>index 463b51d46320..9a2432cea3ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ak7375.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ak7375.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ak7375.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ak7375.c</a></div><div class='hunk'>@@ -10,30 +10,60 @@</div><div class='ctx'> #include &lt;media/v4l2-ctrls.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='ctx'> </div><div class='del'>-#define AK7375_MAX_FOCUS_POS	4095</div><div class='del'>-/*</div><div class='del'>- * This sets the minimum granularity for the focus positions.</div><div class='del'>- * A value of 1 gives maximum accuracy for a desired focus position</div><div class='del'>- */</div><div class='del'>-#define AK7375_FOCUS_STEPS	1</div><div class='del'>-/*</div><div class='del'>- * This acts as the minimum granularity of lens movement.</div><div class='del'>- * Keep this value power of 2, so the control steps can be</div><div class='del'>- * uniformly adjusted for gradual lens movement, with desired</div><div class='del'>- * number of control steps.</div><div class='del'>- */</div><div class='del'>-#define AK7375_CTRL_STEPS	64</div><div class='del'>-#define AK7375_CTRL_DELAY_US	1000</div><div class='del'>-/*</div><div class='del'>- * The vcm may take up 10 ms (tDELAY) to power on and start taking</div><div class='del'>- * I2C messages. Based on AK7371 datasheet.</div><div class='del'>- */</div><div class='del'>-#define AK7375_POWER_DELAY_US	10000</div><div class='add'>+struct ak73xx_chipdef {</div><div class='add'>+	u8 reg_position;</div><div class='add'>+	u8 reg_cont;</div><div class='add'>+	u8 shift_pos;</div><div class='add'>+	u8 mode_active;</div><div class='add'>+	u8 mode_standby;</div><div class='add'>+	bool has_standby;	/* Some chips may not have standby mode */</div><div class='add'>+	u16 focus_pos_max;</div><div class='add'>+	/*</div><div class='add'>+	 * This sets the minimum granularity for the focus positions.</div><div class='add'>+	 * A value of 1 gives maximum accuracy for a desired focus position</div><div class='add'>+	 */</div><div class='add'>+	u16 focus_steps;</div><div class='add'>+	/*</div><div class='add'>+	 * This acts as the minimum granularity of lens movement.</div><div class='add'>+	 * Keep this value power of 2, so the control steps can be</div><div class='add'>+	 * uniformly adjusted for gradual lens movement, with desired</div><div class='add'>+	 * number of control steps.</div><div class='add'>+	 */</div><div class='add'>+	u16 ctrl_steps;</div><div class='add'>+	u16 ctrl_delay_us;</div><div class='add'>+	/*</div><div class='add'>+	 * The vcm may take time (tDELAY) to power on and start taking</div><div class='add'>+	 * I2C messages.</div><div class='add'>+	 */</div><div class='add'>+	u16 power_delay_us;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-#define AK7375_REG_POSITION	0x0</div><div class='del'>-#define AK7375_REG_CONT		0x2</div><div class='del'>-#define AK7375_MODE_ACTIVE	0x0</div><div class='del'>-#define AK7375_MODE_STANDBY	0x40</div><div class='add'>+static const struct ak73xx_chipdef ak7345_cdef = {</div><div class='add'>+	.reg_position	= 0x0,</div><div class='add'>+	.reg_cont	= 0x2,</div><div class='add'>+	.shift_pos	= 7,	/* 9 bits position values, need to &lt;&lt; 7 */</div><div class='add'>+	.mode_active	= 0x0,</div><div class='add'>+	.has_standby	= false,</div><div class='add'>+	.focus_pos_max	= 511,</div><div class='add'>+	.focus_steps	= 1,</div><div class='add'>+	.ctrl_steps	= 16,</div><div class='add'>+	.ctrl_delay_us	= 1000,</div><div class='add'>+	.power_delay_us	= 20000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ak73xx_chipdef ak7375_cdef = {</div><div class='add'>+	.reg_position	= 0x0,</div><div class='add'>+	.reg_cont	= 0x2,</div><div class='add'>+	.shift_pos	= 4,	/* 12 bits position values, need to &lt;&lt; 4 */</div><div class='add'>+	.mode_active	= 0x0,</div><div class='add'>+	.mode_standby	= 0x40,</div><div class='add'>+	.has_standby	= true,</div><div class='add'>+	.focus_pos_max	= 4095,</div><div class='add'>+	.focus_steps	= 1,</div><div class='add'>+	.ctrl_steps	= 64,</div><div class='add'>+	.ctrl_delay_us	= 1000,</div><div class='add'>+	.power_delay_us	= 10000,</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> static const char * const ak7375_supply_names[] = {</div><div class='ctx'> 	"vdd",</div><div class='hunk'>@@ -42,6 +72,7 @@ static const char * const ak7375_supply_names[] = {</div><div class='ctx'> </div><div class='ctx'> /* ak7375 device structure */</div><div class='ctx'> struct ak7375_device {</div><div class='add'>+	const struct ak73xx_chipdef *cdef;</div><div class='ctx'> 	struct v4l2_ctrl_handler ctrls_vcm;</div><div class='ctx'> 	struct v4l2_subdev sd;</div><div class='ctx'> 	struct v4l2_ctrl *focus;</div><div class='hunk'>@@ -86,10 +117,11 @@ static int ak7375_i2c_write(struct ak7375_device *ak7375,</div><div class='ctx'> static int ak7375_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> {</div><div class='ctx'> 	struct ak7375_device *dev_vcm = to_ak7375_vcm(ctrl);</div><div class='add'>+	const struct ak73xx_chipdef *cdef = dev_vcm-&gt;cdef;</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl-&gt;id == V4L2_CID_FOCUS_ABSOLUTE)</div><div class='del'>-		return ak7375_i2c_write(dev_vcm, AK7375_REG_POSITION,</div><div class='del'>-					ctrl-&gt;val &lt;&lt; 4, 2);</div><div class='add'>+		return ak7375_i2c_write(dev_vcm, cdef-&gt;reg_position,</div><div class='add'>+					ctrl-&gt;val &lt;&lt; cdef-&gt;shift_pos, 2);</div><div class='ctx'> </div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='hunk'>@@ -128,11 +160,12 @@ static int ak7375_init_controls(struct ak7375_device *dev_vcm)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_ctrl_handler *hdl = &amp;dev_vcm-&gt;ctrls_vcm;</div><div class='ctx'> 	const struct v4l2_ctrl_ops *ops = &amp;ak7375_vcm_ctrl_ops;</div><div class='add'>+	const struct ak73xx_chipdef *cdef = dev_vcm-&gt;cdef;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_ctrl_handler_init(hdl, 1);</div><div class='ctx'> </div><div class='ctx'> 	dev_vcm-&gt;focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE,</div><div class='del'>-		0, AK7375_MAX_FOCUS_POS, AK7375_FOCUS_STEPS, 0);</div><div class='add'>+		0, cdef-&gt;focus_pos_max, cdef-&gt;focus_steps, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (hdl-&gt;error)</div><div class='ctx'> 		dev_err(dev_vcm-&gt;sd.dev, "%s fail error: 0x%x\n",</div><div class='hunk'>@@ -153,6 +186,8 @@ static int ak7375_probe(struct i2c_client *client)</div><div class='ctx'> 	if (!ak7375_dev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	ak7375_dev-&gt;cdef = device_get_match_data(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(ak7375_supply_names); i++)</div><div class='ctx'> 		ak7375_dev-&gt;supplies[i].supply = ak7375_supply_names[i];</div><div class='ctx'> </div><div class='hunk'>@@ -206,32 +241,35 @@ static void ak7375_remove(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * This function sets the vcm position, so it consumes least current</div><div class='del'>- * The lens position is gradually moved in units of AK7375_CTRL_STEPS,</div><div class='add'>+ * The lens position is gradually moved in units of ctrl_steps,</div><div class='ctx'>  * to make the movements smoothly.</div><div class='ctx'>  */</div><div class='ctx'> static int __maybe_unused ak7375_vcm_suspend(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='ctx'> 	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);</div><div class='add'>+	const struct ak73xx_chipdef *cdef = ak7375_dev-&gt;cdef;</div><div class='ctx'> 	int ret, val;</div><div class='ctx'> </div><div class='ctx'> 	if (!ak7375_dev-&gt;active)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	for (val = ak7375_dev-&gt;focus-&gt;val &amp; ~(AK7375_CTRL_STEPS - 1);</div><div class='del'>-	     val &gt;= 0; val -= AK7375_CTRL_STEPS) {</div><div class='del'>-		ret = ak7375_i2c_write(ak7375_dev, AK7375_REG_POSITION,</div><div class='del'>-				       val &lt;&lt; 4, 2);</div><div class='add'>+	for (val = ak7375_dev-&gt;focus-&gt;val &amp; ~(cdef-&gt;ctrl_steps - 1);</div><div class='add'>+	     val &gt;= 0; val -= cdef-&gt;ctrl_steps) {</div><div class='add'>+		ret = ak7375_i2c_write(ak7375_dev, cdef-&gt;reg_position,</div><div class='add'>+				       val &lt;&lt; cdef-&gt;shift_pos, 2);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			dev_err_once(dev, "%s I2C failure: %d\n",</div><div class='ctx'> 				     __func__, ret);</div><div class='del'>-		usleep_range(AK7375_CTRL_DELAY_US, AK7375_CTRL_DELAY_US + 10);</div><div class='add'>+		usleep_range(cdef-&gt;ctrl_delay_us, cdef-&gt;ctrl_delay_us + 10);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = ak7375_i2c_write(ak7375_dev, AK7375_REG_CONT,</div><div class='del'>-			       AK7375_MODE_STANDBY, 1);</div><div class='del'>-	if (ret)</div><div class='del'>-		dev_err(dev, "%s I2C failure: %d\n", __func__, ret);</div><div class='add'>+	if (cdef-&gt;has_standby) {</div><div class='add'>+		ret = ak7375_i2c_write(ak7375_dev, cdef-&gt;reg_cont,</div><div class='add'>+				       cdef-&gt;mode_standby, 1);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_err(dev, "%s I2C failure: %d\n", __func__, ret);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = regulator_bulk_disable(ARRAY_SIZE(ak7375_supply_names),</div><div class='ctx'> 				     ak7375_dev-&gt;supplies);</div><div class='hunk'>@@ -246,13 +284,14 @@ static int __maybe_unused ak7375_vcm_suspend(struct device *dev)</div><div class='ctx'> /*</div><div class='ctx'>  * This function sets the vcm position to the value set by the user</div><div class='ctx'>  * through v4l2_ctrl_ops s_ctrl handler</div><div class='del'>- * The lens position is gradually moved in units of AK7375_CTRL_STEPS,</div><div class='add'>+ * The lens position is gradually moved in units of ctrl_steps,</div><div class='ctx'>  * to make the movements smoothly.</div><div class='ctx'>  */</div><div class='ctx'> static int __maybe_unused ak7375_vcm_resume(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='ctx'> 	struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);</div><div class='add'>+	const struct ak73xx_chipdef *cdef = ak7375_dev-&gt;cdef;</div><div class='ctx'> 	int ret, val;</div><div class='ctx'> </div><div class='ctx'> 	if (ak7375_dev-&gt;active)</div><div class='hunk'>@@ -264,24 +303,24 @@ static int __maybe_unused ak7375_vcm_resume(struct device *dev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Wait for vcm to become ready */</div><div class='del'>-	usleep_range(AK7375_POWER_DELAY_US, AK7375_POWER_DELAY_US + 500);</div><div class='add'>+	usleep_range(cdef-&gt;power_delay_us, cdef-&gt;power_delay_us + 500);</div><div class='ctx'> </div><div class='del'>-	ret = ak7375_i2c_write(ak7375_dev, AK7375_REG_CONT,</div><div class='del'>-		AK7375_MODE_ACTIVE, 1);</div><div class='add'>+	ret = ak7375_i2c_write(ak7375_dev, cdef-&gt;reg_cont,</div><div class='add'>+			       cdef-&gt;mode_active, 1);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "%s I2C failure: %d\n", __func__, ret);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (val = ak7375_dev-&gt;focus-&gt;val % AK7375_CTRL_STEPS;</div><div class='add'>+	for (val = ak7375_dev-&gt;focus-&gt;val % cdef-&gt;ctrl_steps;</div><div class='ctx'> 	     val &lt;= ak7375_dev-&gt;focus-&gt;val;</div><div class='del'>-	     val += AK7375_CTRL_STEPS) {</div><div class='del'>-		ret = ak7375_i2c_write(ak7375_dev, AK7375_REG_POSITION,</div><div class='del'>-				       val &lt;&lt; 4, 2);</div><div class='add'>+	     val += cdef-&gt;ctrl_steps) {</div><div class='add'>+		ret = ak7375_i2c_write(ak7375_dev, cdef-&gt;reg_position,</div><div class='add'>+				       val &lt;&lt; cdef-&gt;shift_pos, 2);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			dev_err_ratelimited(dev, "%s I2C failure: %d\n",</div><div class='ctx'> 						__func__, ret);</div><div class='del'>-		usleep_range(AK7375_CTRL_DELAY_US, AK7375_CTRL_DELAY_US + 10);</div><div class='add'>+		usleep_range(cdef-&gt;ctrl_delay_us, cdef-&gt;ctrl_delay_us + 10);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ak7375_dev-&gt;active = true;</div><div class='hunk'>@@ -290,7 +329,8 @@ static int __maybe_unused ak7375_vcm_resume(struct device *dev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ak7375_of_table[] = {</div><div class='del'>-	{ .compatible = "asahi-kasei,ak7375" },</div><div class='add'>+	{ .compatible = "asahi-kasei,ak7345", .data = &amp;ak7345_cdef, },</div><div class='add'>+	{ .compatible = "asahi-kasei,ak7375", .data = &amp;ak7375_cdef, },</div><div class='ctx'> 	{ /* sentinel */ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, ak7375_of_table);</div><div class='head'>diff --git a/drivers/media/i2c/alvium-csi2.c b/drivers/media/i2c/alvium-csi2.c<br/>new file mode 100644<br/>index 000000000000..34ff7fad3877<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/alvium-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/alvium-csi2.c</a></div><div class='hunk'>@@ -0,0 +1,2558 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Allied Vision Technologies GmbH Alvium camera driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Tommaso Merciai</div><div class='add'>+ * Copyright (C) 2023 Martin Hecht</div><div class='add'>+ * Copyright (C) 2023 Avnet EMG GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;media/mipi-csi2.h&gt;</div><div class='add'>+#include &lt;media/v4l2-async.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#include "alvium-csi2.h"</div><div class='add'>+</div><div class='add'>+static const struct v4l2_mbus_framefmt alvium_csi2_default_fmt = {</div><div class='add'>+	.code = MEDIA_BUS_FMT_UYVY8_1X16,</div><div class='add'>+	.width = 640,</div><div class='add'>+	.height = 480,</div><div class='add'>+	.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+	.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB),</div><div class='add'>+	.quantization = V4L2_QUANTIZATION_FULL_RANGE,</div><div class='add'>+	.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB),</div><div class='add'>+	.field = V4L2_FIELD_NONE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct alvium_pixfmt alvium_csi2_fmts[] = {</div><div class='add'>+	{</div><div class='add'>+		/* UYVY8_2X8 */</div><div class='add'>+		.id = ALVIUM_FMT_UYVY8_2X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_UYVY8_2X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_YUV422_8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* UYVY8_1X16 */</div><div class='add'>+		.id = ALVIUM_FMT_UYVY8_1X16,</div><div class='add'>+		.code = MEDIA_BUS_FMT_UYVY8_1X16,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_YUV422_8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* YUYV8_1X16 */</div><div class='add'>+		.id = ALVIUM_FMT_YUYV8_1X16,</div><div class='add'>+		.code = MEDIA_BUS_FMT_YUYV8_1X16,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_YUV422_8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* YUYV8_2X8 */</div><div class='add'>+		.id = ALVIUM_FMT_YUYV8_2X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_YUYV8_2X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_YUV422_8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* YUYV10_1X20 */</div><div class='add'>+		.id = ALVIUM_FMT_YUYV10_1X20,</div><div class='add'>+		.code = MEDIA_BUS_FMT_YUYV10_1X20,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_YUV422_10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_YUV422_10B,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* RGB888_1X24 */</div><div class='add'>+		.id = ALVIUM_FMT_RGB888_1X24,</div><div class='add'>+		.code = MEDIA_BUS_FMT_RGB888_1X24,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RGB888,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RGB888,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* RBG888_1X24 */</div><div class='add'>+		.id = ALVIUM_FMT_RBG888_1X24,</div><div class='add'>+		.code = MEDIA_BUS_FMT_RBG888_1X24,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RGB888,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RGB888,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* BGR888_1X24 */</div><div class='add'>+		.id = ALVIUM_FMT_BGR888_1X24,</div><div class='add'>+		.code = MEDIA_BUS_FMT_BGR888_1X24,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RGB888,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RGB888,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* RGB888_3X8 */</div><div class='add'>+		.id = ALVIUM_FMT_RGB888_3X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_RGB888_3X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RGB888,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_NONE,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RGB888,</div><div class='add'>+		.bay_fmt_regval = -1,</div><div class='add'>+		.is_raw = 0,</div><div class='add'>+	}, {</div><div class='add'>+		/* Y8_1X8 */</div><div class='add'>+		.id = ALVIUM_FMT_Y8_1X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_Y8_1X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_MONO,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW8,</div><div class='add'>+		.bay_fmt_regval = 0x00,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGRBG8_1X8 */</div><div class='add'>+		.id = ALVIUM_FMT_SGRBG8_1X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGRBG8_1X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GR,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW8,</div><div class='add'>+		.bay_fmt_regval = 0x01,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SRGGB8_1X8 */</div><div class='add'>+		.id = ALVIUM_FMT_SRGGB8_1X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SRGGB8_1X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_RG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW8,</div><div class='add'>+		.bay_fmt_regval = 0x02,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGBRG8_1X8 */</div><div class='add'>+		.id = ALVIUM_FMT_SGBRG8_1X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGBRG8_1X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GB,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW8,</div><div class='add'>+		.bay_fmt_regval = 0x03,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SBGGR8_1X8 */</div><div class='add'>+		.id = ALVIUM_FMT_SBGGR8_1X8,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SBGGR8_1X8,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW8,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_BG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW8,</div><div class='add'>+		.bay_fmt_regval = 0x04,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* Y10_1X10 */</div><div class='add'>+		.id = ALVIUM_FMT_Y10_1X10,</div><div class='add'>+		.code = MEDIA_BUS_FMT_Y10_1X10,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_MONO,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW10,</div><div class='add'>+		.bay_fmt_regval = 0x00,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGRBG10_1X10 */</div><div class='add'>+		.id = ALVIUM_FMT_SGRBG10_1X10,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGRBG10_1X10,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GR,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW10,</div><div class='add'>+		.bay_fmt_regval = 0x01,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SRGGB10_1X10 */</div><div class='add'>+		.id = ALVIUM_FMT_SRGGB10_1X10,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SRGGB10_1X10,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_RG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW10,</div><div class='add'>+		.bay_fmt_regval = 0x02,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGBRG10_1X10 */</div><div class='add'>+		.id = ALVIUM_FMT_SGBRG10_1X10,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGBRG10_1X10,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GB,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW10,</div><div class='add'>+		.bay_fmt_regval = 0x03,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SBGGR10_1X10 */</div><div class='add'>+		.id = ALVIUM_FMT_SBGGR10_1X10,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SBGGR10_1X10,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW10,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_BG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW10,</div><div class='add'>+		.bay_fmt_regval = 0x04,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* Y12_1X12 */</div><div class='add'>+		.id = ALVIUM_FMT_Y12_1X12,</div><div class='add'>+		.code = MEDIA_BUS_FMT_Y12_1X12,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW12,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_MONO,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW12,</div><div class='add'>+		.bay_fmt_regval = 0x00,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGRBG12_1X12 */</div><div class='add'>+		.id = ALVIUM_FMT_SGRBG12_1X12,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGRBG12_1X12,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW12,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GR,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW12,</div><div class='add'>+		.bay_fmt_regval = 0x01,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SRGGB12_1X12 */</div><div class='add'>+		.id = ALVIUM_FMT_SRGGB12_1X12,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SRGGB12_1X12,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW12,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_RG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW12,</div><div class='add'>+		.bay_fmt_regval = 0x02,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGBRG12_1X12 */</div><div class='add'>+		.id = ALVIUM_FMT_SGBRG12_1X12,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGBRG12_1X12,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW12,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GB,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW12,</div><div class='add'>+		.bay_fmt_regval = 0x03,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SBGGR12_1X12 */</div><div class='add'>+		.id = ALVIUM_FMT_SBGGR12_1X12,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SBGGR12_1X12,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW12,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_BG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW12,</div><div class='add'>+		.bay_fmt_regval = 0x04,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SBGGR14_1X14 */</div><div class='add'>+		.id = ALVIUM_FMT_SBGGR14_1X14,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SBGGR14_1X14,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW14,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GR,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW14,</div><div class='add'>+		.bay_fmt_regval = 0x01,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGBRG14_1X14 */</div><div class='add'>+		.id = ALVIUM_FMT_SGBRG14_1X14,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGBRG14_1X14,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW14,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_RG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW14,</div><div class='add'>+		.bay_fmt_regval = 0x02,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SRGGB14_1X14 */</div><div class='add'>+		.id = ALVIUM_FMT_SRGGB14_1X14,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SRGGB14_1X14,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW14,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_GB,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW14,</div><div class='add'>+		.bay_fmt_regval = 0x03,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	}, {</div><div class='add'>+		/* SGRBG14_1X14 */</div><div class='add'>+		.id = ALVIUM_FMT_SGRBG14_1X14,</div><div class='add'>+		.code = MEDIA_BUS_FMT_SGRBG14_1X14,</div><div class='add'>+		.colorspace = V4L2_COLORSPACE_RAW,</div><div class='add'>+		.fmt_av_bit = ALVIUM_BIT_RAW14,</div><div class='add'>+		.bay_av_bit = ALVIUM_BIT_BAY_BG,</div><div class='add'>+		.mipi_fmt_regval = MIPI_CSI2_DT_RAW14,</div><div class='add'>+		.bay_fmt_regval = 0x04,</div><div class='add'>+		.is_raw = 1,</div><div class='add'>+	},</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int alvium_read(struct alvium_dev *alvium, u32 reg, u64 *val, int *err)</div><div class='add'>+{</div><div class='add'>+	if (reg &amp; REG_BCRM_V4L2) {</div><div class='add'>+		reg &amp;= ~REG_BCRM_V4L2;</div><div class='add'>+		reg += alvium-&gt;bcrm_addr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cci_read(alvium-&gt;regmap, reg, val, err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_write(struct alvium_dev *alvium, u32 reg, u64 val, int *err)</div><div class='add'>+{</div><div class='add'>+	if (reg &amp; REG_BCRM_V4L2) {</div><div class='add'>+		reg &amp;= ~REG_BCRM_V4L2;</div><div class='add'>+		reg += alvium-&gt;bcrm_addr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cci_write(alvium-&gt;regmap, reg, val, err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_write_hshake(struct alvium_dev *alvium, u32 reg, u64 val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 hshake_bit;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* reset handshake bit and write alvium reg */</div><div class='add'>+	alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, 0, &amp;ret);</div><div class='add'>+	alvium_write(alvium, reg, val, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to write reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* poll handshake bit since bit0 = 1 */</div><div class='add'>+	read_poll_timeout(alvium_read, hshake_bit,</div><div class='add'>+			  ((hshake_bit &amp; BCRM_HANDSHAKE_W_DONE_EN_BIT) == 1),</div><div class='add'>+			  15000, 45000, true,</div><div class='add'>+			  alvium, REG_BCRM_WRITE_HANDSHAKE_RW,</div><div class='add'>+			  &amp;hshake_bit, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "poll bit[0] = 1, hshake reg fail\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* reset handshake bit, write 0 to bit0 */</div><div class='add'>+	alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, 0, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to reset hshake reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* poll handshake bit since bit0 = 0 */</div><div class='add'>+	read_poll_timeout(alvium_read, hshake_bit,</div><div class='add'>+			  ((hshake_bit &amp; BCRM_HANDSHAKE_W_DONE_EN_BIT) == 0),</div><div class='add'>+			  15000, 45000, true,</div><div class='add'>+			  alvium, REG_BCRM_WRITE_HANDSHAKE_RW,</div><div class='add'>+			  &amp;hshake_bit, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "poll bit[0] = 0, hshake reg fail\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_bcrm_vers(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 min, maj;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, &amp;min, &amp;ret);</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_MAJOR_VERSION_R, &amp;maj, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "bcrm version: %llu.%llu\n", min, maj);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_fw_version(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 spec, maj, min, pat;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_SPEC_VERSION_R,</div><div class='add'>+			  &amp;spec, &amp;ret);</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MAJOR_VERSION_R,</div><div class='add'>+			  &amp;maj, &amp;ret);</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MINOR_VERSION_R,</div><div class='add'>+			  &amp;min, &amp;ret);</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_PATCH_VERSION_R,</div><div class='add'>+			  &amp;pat, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "fw version: %llu.%llu.%llu.%llu\n", spec, maj, min, pat);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_bcrm_addr(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_REG_ADDR_R, &amp;val, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;bcrm_addr = val;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_is_alive(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 bcrm, hbeat;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, &amp;bcrm, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_HEARTBEAT_RW, &amp;hbeat, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return hbeat;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void alvium_print_avail_mipi_fmt(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv420_8_leg: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv420_8: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv420_10: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv420_8_csps: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv420_10_csps: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv422_8: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt yuv422_10: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt rgb888: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB888]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt rgb666: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB666]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt rgb565: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB565]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt rgb555: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB555]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt rgb444: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB444]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw6: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW6]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw7: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW7]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw8: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW8]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw10: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW10]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw12: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW12]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt raw14: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW14]);</div><div class='add'>+	dev_dbg(dev, "avail mipi_fmt jpeg: %u\n",</div><div class='add'>+		alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_JPEG]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void alvium_print_avail_feat(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "feature rev_x: %u\n", alvium-&gt;avail_ft.rev_x);</div><div class='add'>+	dev_dbg(dev, "feature rev_y: %u\n", alvium-&gt;avail_ft.rev_y);</div><div class='add'>+	dev_dbg(dev, "feature int_autop: %u\n", alvium-&gt;avail_ft.int_autop);</div><div class='add'>+	dev_dbg(dev, "feature black_lvl: %u\n", alvium-&gt;avail_ft.black_lvl);</div><div class='add'>+	dev_dbg(dev, "feature gain: %u\n", alvium-&gt;avail_ft.gain);</div><div class='add'>+	dev_dbg(dev, "feature gamma: %u\n", alvium-&gt;avail_ft.gamma);</div><div class='add'>+	dev_dbg(dev, "feature contrast: %u\n", alvium-&gt;avail_ft.contrast);</div><div class='add'>+	dev_dbg(dev, "feature sat: %u\n", alvium-&gt;avail_ft.sat);</div><div class='add'>+	dev_dbg(dev, "feature hue: %u\n", alvium-&gt;avail_ft.hue);</div><div class='add'>+	dev_dbg(dev, "feature whiteb: %u\n", alvium-&gt;avail_ft.whiteb);</div><div class='add'>+	dev_dbg(dev, "feature sharp: %u\n", alvium-&gt;avail_ft.sharp);</div><div class='add'>+	dev_dbg(dev, "feature auto_exp: %u\n", alvium-&gt;avail_ft.auto_exp);</div><div class='add'>+	dev_dbg(dev, "feature auto_gain: %u\n", alvium-&gt;avail_ft.auto_gain);</div><div class='add'>+	dev_dbg(dev, "feature auto_whiteb: %u\n", alvium-&gt;avail_ft.auto_whiteb);</div><div class='add'>+	dev_dbg(dev, "feature dev_temp: %u\n", alvium-&gt;avail_ft.dev_temp);</div><div class='add'>+	dev_dbg(dev, "feature acq_abort: %u\n", alvium-&gt;avail_ft.acq_abort);</div><div class='add'>+	dev_dbg(dev, "feature acq_fr: %u\n", alvium-&gt;avail_ft.acq_fr);</div><div class='add'>+	dev_dbg(dev, "feature fr_trigger: %u\n", alvium-&gt;avail_ft.fr_trigger);</div><div class='add'>+	dev_dbg(dev, "feature exp_acq_line: %u\n",</div><div class='add'>+		alvium-&gt;avail_ft.exp_acq_line);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void alvium_print_avail_bayer(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "avail bayer mono: %u\n",</div><div class='add'>+		alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_MONO]);</div><div class='add'>+	dev_dbg(dev, "avail bayer gr: %u\n",</div><div class='add'>+		alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_GR]);</div><div class='add'>+	dev_dbg(dev, "avail bayer rg: %u\n",</div><div class='add'>+		alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_RG]);</div><div class='add'>+	dev_dbg(dev, "avail bayer gb: %u\n",</div><div class='add'>+		alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_GB]);</div><div class='add'>+	dev_dbg(dev, "avail bayer bg: %u\n",</div><div class='add'>+		alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_BG]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_feat_inq(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct alvium_avail_feat *f;</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_FEATURE_INQUIRY_R, &amp;val, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	f = (struct alvium_avail_feat *)&amp;val;</div><div class='add'>+	alvium-&gt;avail_ft = *f;</div><div class='add'>+	alvium_print_avail_feat(alvium);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_host_supp_csi_lanes(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_CSI2_LANE_COUNT_RW, &amp;val, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;h_sup_csi_lanes = val;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_csi_lanes(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 num_lanes;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	num_lanes = alvium-&gt;ep.bus.mipi_csi2.num_data_lanes;</div><div class='add'>+</div><div class='add'>+	if (num_lanes &gt; alvium-&gt;h_sup_csi_lanes)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_LANE_COUNT_RW,</div><div class='add'>+				  num_lanes);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set csi lanes reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_lp2hs_delay(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The purpose of this reg is force a DPhy reset</div><div class='add'>+	 * for the period described by the millisecond on</div><div class='add'>+	 * the reg, before it starts streaming.</div><div class='add'>+	 *</div><div class='add'>+	 * To be clear, with that value bigger than 0 the</div><div class='add'>+	 * Alvium forces a dphy-reset on all lanes for that period.</div><div class='add'>+	 * That means all lanes go up into low power state.</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	alvium_write(alvium, REG_BCRM_LP2HS_DELAY_RW,</div><div class='add'>+		     ALVIUM_LP2HS_DELAY_MS, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set lp2hs delay reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_csi_clk_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 min_csi_clk, max_csi_clk;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MIN_R, &amp;min_csi_clk, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MAX_R, &amp;max_csi_clk, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;min_csi_clk = min_csi_clk;</div><div class='add'>+	alvium-&gt;max_csi_clk = max_csi_clk;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_csi_clk(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 csi_clk;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	csi_clk = clamp(alvium-&gt;ep.link_frequencies[0],</div><div class='add'>+			(u64)alvium-&gt;min_csi_clk, (u64)alvium-&gt;max_csi_clk);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;ep.link_frequencies[0] != (u64)csi_clk) {</div><div class='add'>+		dev_warn(dev,</div><div class='add'>+			 "requested csi clock (%llu MHz) out of range [%u, %u] Adjusted to %llu\n",</div><div class='add'>+			 alvium-&gt;ep.link_frequencies[0],</div><div class='add'>+			 alvium-&gt;min_csi_clk, alvium-&gt;max_csi_clk, csi_clk);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_CLOCK_RW, csi_clk);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set csi clock reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alvium-&gt;link_freq = csi_clk;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_img_width_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 imgw, imgw_min, imgw_max, imgw_inc;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_WIDTH_RW, &amp;imgw, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_WIDTH_MIN_R, &amp;imgw_min, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_WIDTH_MAX_R, &amp;imgw_max, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_WIDTH_INC_R, &amp;imgw_inc, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_img_width = imgw;</div><div class='add'>+	alvium-&gt;img_min_width = imgw_min;</div><div class='add'>+	alvium-&gt;img_max_width = imgw_max;</div><div class='add'>+	alvium-&gt;img_inc_width = imgw_inc;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_img_height_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 imgh, imgh_min, imgh_max, imgh_inc;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_HEIGHT_RW, &amp;imgh, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MIN_R, &amp;imgh_min, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MAX_R, &amp;imgh_max, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_HEIGHT_INC_R, &amp;imgh_inc, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_img_height = imgh;</div><div class='add'>+	alvium-&gt;img_min_height = imgh_min;</div><div class='add'>+	alvium-&gt;img_max_height = imgh_max;</div><div class='add'>+	alvium-&gt;img_inc_height = imgh_inc;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_img_width(struct alvium_dev *alvium, u32 width)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_WIDTH_RW, width);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set img width\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_img_height(struct alvium_dev *alvium, u32 height)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_HEIGHT_RW, height);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set img height\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_img_offx(struct alvium_dev *alvium, u32 offx)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_X_RW, offx);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set img offx\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_img_offy(struct alvium_dev *alvium, u32 offy)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_Y_RW, offy);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set img offy\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_offx_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 min_offx, max_offx, inc_offx;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MIN_R, &amp;min_offx, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MAX_R, &amp;max_offx, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_INC_R, &amp;inc_offx, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;min_offx = min_offx;</div><div class='add'>+	alvium-&gt;max_offx = max_offx;</div><div class='add'>+	alvium-&gt;inc_offx = inc_offx;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_offy_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 min_offy, max_offy, inc_offy;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MIN_R, &amp;min_offy, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MAX_R, &amp;max_offy, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_INC_R, &amp;inc_offy, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;min_offy = min_offy;</div><div class='add'>+	alvium-&gt;max_offy = max_offy;</div><div class='add'>+	alvium-&gt;inc_offy = inc_offy;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_gain_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_gain, min_gain, max_gain, inc_gain;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAIN_RW, &amp;dft_gain, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAIN_MIN_R, &amp;min_gain, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAIN_MAX_R, &amp;max_gain, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAIN_INC_R, &amp;inc_gain, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_gain = dft_gain;</div><div class='add'>+	alvium-&gt;min_gain = min_gain;</div><div class='add'>+	alvium-&gt;max_gain = max_gain;</div><div class='add'>+	alvium-&gt;inc_gain = inc_gain;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_exposure_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_exp, min_exp, max_exp, inc_exp;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, &amp;dft_exp, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MIN_R, &amp;min_exp, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MAX_R, &amp;max_exp, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_INC_R, &amp;inc_exp, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_exp = dft_exp;</div><div class='add'>+	alvium-&gt;min_exp = min_exp;</div><div class='add'>+	alvium-&gt;max_exp = max_exp;</div><div class='add'>+	alvium-&gt;inc_exp = inc_exp;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_red_balance_ratio_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_rb, min_rb, max_rb, inc_rb;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_RW, &amp;dft_rb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MIN_R, &amp;min_rb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MAX_R, &amp;max_rb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_INC_R, &amp;inc_rb, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_rbalance = dft_rb;</div><div class='add'>+	alvium-&gt;min_rbalance = min_rb;</div><div class='add'>+	alvium-&gt;max_rbalance = max_rb;</div><div class='add'>+	alvium-&gt;inc_rbalance = inc_rb;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_blue_balance_ratio_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_bb, min_bb, max_bb, inc_bb;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW, &amp;dft_bb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MIN_R, &amp;min_bb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MAX_R, &amp;max_bb, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_INC_R, &amp;inc_bb, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_bbalance = dft_bb;</div><div class='add'>+	alvium-&gt;min_bbalance = min_bb;</div><div class='add'>+	alvium-&gt;max_bbalance = max_bb;</div><div class='add'>+	alvium-&gt;inc_bbalance = inc_bb;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_hue_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_hue, min_hue, max_hue, inc_hue;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_HUE_RW, &amp;dft_hue, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_HUE_MIN_R, &amp;min_hue, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_HUE_MAX_R, &amp;max_hue, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_HUE_INC_R, &amp;inc_hue, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_hue = (s32)dft_hue;</div><div class='add'>+	alvium-&gt;min_hue = (s32)min_hue;</div><div class='add'>+	alvium-&gt;max_hue = (s32)max_hue;</div><div class='add'>+	alvium-&gt;inc_hue = (s32)inc_hue;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_black_lvl_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_blvl, min_blvl, max_blvl, inc_blvl;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLACK_LEVEL_RW, &amp;dft_blvl, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MIN_R, &amp;min_blvl, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, &amp;max_blvl, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLACK_LEVEL_INC_R, &amp;inc_blvl, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_black_lvl = (s32)dft_blvl;</div><div class='add'>+	alvium-&gt;min_black_lvl = (s32)min_blvl;</div><div class='add'>+	alvium-&gt;max_black_lvl = (s32)max_blvl;</div><div class='add'>+	alvium-&gt;inc_black_lvl = (s32)inc_blvl;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_gamma_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_g, min_g, max_g, inc_g;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAMMA_RW, &amp;dft_g, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAMMA_MIN_R, &amp;min_g, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAMMA_MAX_R, &amp;max_g, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_GAMMA_INC_R, &amp;inc_g, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_gamma = dft_g;</div><div class='add'>+	alvium-&gt;min_gamma = min_g;</div><div class='add'>+	alvium-&gt;max_gamma = max_g;</div><div class='add'>+	alvium-&gt;inc_gamma = inc_g;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_sharpness_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_sh, min_sh, max_sh, inc_sh;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SHARPNESS_RW, &amp;dft_sh, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SHARPNESS_MIN_R, &amp;min_sh, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, &amp;max_sh, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SHARPNESS_INC_R, &amp;inc_sh, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_sharp = (s32)dft_sh;</div><div class='add'>+	alvium-&gt;min_sharp = (s32)min_sh;</div><div class='add'>+	alvium-&gt;max_sharp = (s32)max_sh;</div><div class='add'>+	alvium-&gt;inc_sharp = (s32)inc_sh;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_contrast_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_c, min_c, max_c, inc_c;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_RW, &amp;dft_c, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MIN_R, &amp;min_c, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MAX_R, &amp;max_c, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_INC_R, &amp;inc_c, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_contrast = dft_c;</div><div class='add'>+	alvium-&gt;min_contrast = min_c;</div><div class='add'>+	alvium-&gt;max_contrast = max_c;</div><div class='add'>+	alvium-&gt;inc_contrast = inc_c;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_saturation_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_sat, min_sat, max_sat, inc_sat;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SATURATION_RW, &amp;dft_sat, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SATURATION_MIN_R, &amp;min_sat, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SATURATION_MAX_R, &amp;max_sat, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_SATURATION_INC_R, &amp;inc_sat, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_sat = dft_sat;</div><div class='add'>+	alvium-&gt;min_sat = min_sat;</div><div class='add'>+	alvium-&gt;max_sat = max_sat;</div><div class='add'>+	alvium-&gt;inc_sat = inc_sat;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_bcm_mode(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_write(alvium, REG_GENCP_CHANGEMODE_W, ALVIUM_BCM_MODE, &amp;ret);</div><div class='add'>+	alvium-&gt;bcrm_mode = ALVIUM_BCM_MODE;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_mode(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 bcrm_mode;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_GENCP_CURRENTMODE_R, &amp;bcrm_mode, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (bcrm_mode) {</div><div class='add'>+	case ALVIUM_BCM_MODE:</div><div class='add'>+		alvium-&gt;bcrm_mode = ALVIUM_BCM_MODE;</div><div class='add'>+		break;</div><div class='add'>+	case ALVIUM_GENCP_MODE:</div><div class='add'>+		alvium-&gt;bcrm_mode = ALVIUM_GENCP_MODE;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_avail_mipi_data_format(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct alvium_avail_mipi_fmt *avail_fmt;</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R,</div><div class='add'>+			  &amp;val, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	avail_fmt = (struct alvium_avail_mipi_fmt *)&amp;val;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG] =</div><div class='add'>+				  avail_fmt-&gt;yuv420_8_leg;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8] =</div><div class='add'>+				  avail_fmt-&gt;yuv420_8;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10] =</div><div class='add'>+				  avail_fmt-&gt;yuv420_10;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS] =</div><div class='add'>+				  avail_fmt-&gt;yuv420_8_csps;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS] =</div><div class='add'>+				  avail_fmt-&gt;yuv420_10_csps;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8] =</div><div class='add'>+				  avail_fmt-&gt;yuv422_8;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10] =</div><div class='add'>+				  avail_fmt-&gt;yuv422_10;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB888] =</div><div class='add'>+				  avail_fmt-&gt;rgb888;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB666] =</div><div class='add'>+				  avail_fmt-&gt;rgb666;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB565] =</div><div class='add'>+				  avail_fmt-&gt;rgb565;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB555] =</div><div class='add'>+				  avail_fmt-&gt;rgb555;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RGB444] =</div><div class='add'>+				  avail_fmt-&gt;rgb444;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW6] =</div><div class='add'>+				  avail_fmt-&gt;raw6;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW7] =</div><div class='add'>+				  avail_fmt-&gt;raw7;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW8] =</div><div class='add'>+				  avail_fmt-&gt;raw8;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW10] =</div><div class='add'>+				  avail_fmt-&gt;raw10;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW12] =</div><div class='add'>+				  avail_fmt-&gt;raw12;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_RAW14] =</div><div class='add'>+				  avail_fmt-&gt;raw14;</div><div class='add'>+	alvium-&gt;is_mipi_fmt_avail[ALVIUM_BIT_JPEG] =</div><div class='add'>+				  avail_fmt-&gt;jpeg;</div><div class='add'>+</div><div class='add'>+	alvium_print_avail_mipi_fmt(alvium);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_setup_mipi_fmt(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	unsigned int avail_fmt_cnt = 0;</div><div class='add'>+	unsigned int fmt = 0;</div><div class='add'>+	size_t sz = 0;</div><div class='add'>+</div><div class='add'>+	/* calculate fmt array size */</div><div class='add'>+	for (fmt = 0; fmt &lt; ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) {</div><div class='add'>+		if (!alvium-&gt;is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!alvium_csi2_fmts[fmt].is_raw ||</div><div class='add'>+		    alvium-&gt;is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit])</div><div class='add'>+			sz++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* init alvium_csi2_fmt array */</div><div class='add'>+	alvium-&gt;alvium_csi2_fmt_n = sz;</div><div class='add'>+	alvium-&gt;alvium_csi2_fmt =</div><div class='add'>+		kmalloc_array(sz, sizeof(struct alvium_pixfmt), GFP_KERNEL);</div><div class='add'>+	if (!alvium-&gt;alvium_csi2_fmt)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Create the alvium_csi2 fmt array from formats available */</div><div class='add'>+	for (fmt = 0; fmt &lt; ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) {</div><div class='add'>+		if (!alvium-&gt;is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!alvium_csi2_fmts[fmt].is_raw ||</div><div class='add'>+		    alvium-&gt;is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit]) {</div><div class='add'>+			alvium-&gt;alvium_csi2_fmt[avail_fmt_cnt] =</div><div class='add'>+				alvium_csi2_fmts[fmt];</div><div class='add'>+			avail_fmt_cnt++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_mipi_fmt(struct alvium_dev *alvium,</div><div class='add'>+			       const struct alvium_pixfmt *pixfmt)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_MIPI_DATA_FORMAT_RW,</div><div class='add'>+				  pixfmt-&gt;mipi_fmt_regval);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set mipi fmt\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_avail_bayer(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct alvium_avail_bayer *avail_bay;</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R,</div><div class='add'>+			  &amp;val, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	avail_bay = (struct alvium_avail_bayer *)&amp;val;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_MONO] = avail_bay-&gt;mono;</div><div class='add'>+	alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_GR] = avail_bay-&gt;gr;</div><div class='add'>+	alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_RG] = avail_bay-&gt;rg;</div><div class='add'>+	alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_GB] = avail_bay-&gt;gb;</div><div class='add'>+	alvium-&gt;is_bay_avail[ALVIUM_BIT_BAY_BG] = avail_bay-&gt;bg;</div><div class='add'>+</div><div class='add'>+	alvium_print_avail_bayer(alvium);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_bayer_pattern(struct alvium_dev *alvium,</div><div class='add'>+				    const struct alvium_pixfmt *pixfmt)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_BAYER_PATTERN_RW,</div><div class='add'>+				  pixfmt-&gt;bay_fmt_regval);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set bayer pattern\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_frame_interval(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 dft_fr, min_fr, max_fr;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_RW,</div><div class='add'>+		    &amp;dft_fr, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R,</div><div class='add'>+		    &amp;min_fr, &amp;ret);</div><div class='add'>+	alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R,</div><div class='add'>+		    &amp;max_fr, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;dft_fr = dft_fr;</div><div class='add'>+	alvium-&gt;min_fr = min_fr;</div><div class='add'>+	alvium-&gt;max_fr = max_fr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_frame_rate(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_RW,</div><div class='add'>+				  alvium-&gt;fr);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set frame rate lanes reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "set frame rate: %llu us\n", alvium-&gt;fr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_stream_mipi(struct alvium_dev *alvium, bool on)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, on ? REG_BCRM_ACQUISITION_START_RW :</div><div class='add'>+				  REG_BCRM_ACQUISITION_STOP_RW, 0x01);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail set_stream_mipi\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_gain(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 gain;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* The unit is millibel (1 mB = 0.01 dB) */</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_GAIN_RW, &amp;gain, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return gain;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_gain(struct alvium_dev *alvium, int gain)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* The unit is millibel (1 mB = 0.01 dB) */</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_RW, (u64)gain);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set gain value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_auto_gain(struct alvium_dev *alvium, bool on)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_AUTO_RW,</div><div class='add'>+				  on ? 0x02 : 0x00);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set autogain reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_exposure(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	u64 exp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Exposure time in ns */</div><div class='add'>+	ret = alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, &amp;exp, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return exp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_auto_exposure(struct alvium_dev *alvium, bool on)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW,</div><div class='add'>+				  on ? 0x02 : 0x00);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set autoexposure reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_exposure(struct alvium_dev *alvium, int exposure_ns)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_EXPOSURE_TIME_RW,</div><div class='add'>+				  (u64)exposure_ns);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set exposure value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_blue_balance_ratio(struct alvium_dev *alvium,</div><div class='add'>+					      int blue)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW,</div><div class='add'>+				  (u64)blue);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set blue ratio value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_red_balance_ratio(struct alvium_dev *alvium, int red)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_RED_BALANCE_RATIO_RW,</div><div class='add'>+				  (u64)red);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set red ratio value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_awb(struct alvium_dev *alvium, bool on)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW,</div><div class='add'>+				  on ? 0x02 : 0x00);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set awb reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_hue(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_HUE_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set hue value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_contrast(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_CONTRAST_VALUE_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set contrast value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_saturation(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_SATURATION_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set contrast value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_gamma(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_GAMMA_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set gamma value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_sharpness(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_SHARPNESS_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set sharpness value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_hflip(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_X_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set reverse_x value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_ctrl_vflip(struct alvium_dev *alvium, int val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_Y_RW, (u64)val);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set reverse_y value reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_hw_features_params(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_csi_clk_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read min/max csi clock regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_img_width_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read img width regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_img_height_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read img heigth regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_offx_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read offx regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_offy_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read offy regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_gain_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read gain regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_exposure_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read min/max exp regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_red_balance_ratio_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read red balance ratio regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_blue_balance_ratio_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read blue balance ratio regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_hue_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read hue regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_contrast_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read contrast regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_saturation_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read saturation regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_black_lvl_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read black lvl regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_gamma_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read gamma regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_sharpness_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read sharpness regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_hw_info(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_bcrm_vers(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read bcrm version reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_bcrm_addr(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to bcrm address reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_fw_version(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read fw version reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_host_supp_csi_lanes(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read host supported csi lanes reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_feat_inq(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read bcrm feature inquiry reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_hw_features_params(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read features params regs\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_avail_mipi_data_format(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read available mipi data formats reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_avail_bayer(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to read available Bayer patterns reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_mode(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to get current mode reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_hw_init(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Set Alvium BCM mode*/</div><div class='add'>+	ret = alvium_set_bcm_mode(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set BCM mode\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_csi_lanes(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set csi lanes\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_csi_clk(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set csi clk\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_lp2hs_delay(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to set lp2hs reg\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* --------------- Subdev Operations --------------- */</div><div class='add'>+</div><div class='add'>+static int alvium_g_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state,</div><div class='add'>+				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fi-&gt;interval = alvium-&gt;frame_interval;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_frame_interval(struct alvium_dev *alvium,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	u64 req_fr, min_fr, max_fr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (fi-&gt;interval.denominator == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_frame_interval(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Fail to get frame interval\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_fr = alvium-&gt;min_fr;</div><div class='add'>+	max_fr = alvium-&gt;max_fr;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "fi-&gt;interval.numerator = %d\n",</div><div class='add'>+		fi-&gt;interval.numerator);</div><div class='add'>+	dev_dbg(dev, "fi-&gt;interval.denominator = %d\n",</div><div class='add'>+		fi-&gt;interval.denominator);</div><div class='add'>+</div><div class='add'>+	req_fr = (u64)((fi-&gt;interval.denominator * USEC_PER_SEC) /</div><div class='add'>+		       fi-&gt;interval.numerator);</div><div class='add'>+</div><div class='add'>+	if (req_fr &gt;= max_fr &amp;&amp; req_fr &lt;= min_fr)</div><div class='add'>+		req_fr = alvium-&gt;dft_fr;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;fr = req_fr;</div><div class='add'>+	alvium-&gt;frame_interval.numerator = fi-&gt;interval.numerator;</div><div class='add'>+	alvium-&gt;frame_interval.denominator = fi-&gt;interval.denominator;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_s_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state,</div><div class='add'>+				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;streaming)</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_frame_interval(alvium, fi);</div><div class='add'>+	if (!ret)</div><div class='add'>+		ret = alvium_set_frame_rate(alvium);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state,</div><div class='add'>+				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+</div><div class='add'>+	if (code-&gt;index &gt;= alvium-&gt;alvium_csi2_fmt_n)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = alvium-&gt;alvium_csi2_fmt[code-&gt;index].code;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct alvium_pixfmt *</div><div class='add'>+alvium_code_to_pixfmt(struct alvium_dev *alvium, u32 code)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; alvium-&gt;alvium_csi2_fmt[i].code; ++i)</div><div class='add'>+		if (alvium-&gt;alvium_csi2_fmt[i].code == code)</div><div class='add'>+			return &amp;alvium-&gt;alvium_csi2_fmt[i];</div><div class='add'>+</div><div class='add'>+	return &amp;alvium-&gt;alvium_csi2_fmt[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_mode(struct alvium_dev *alvium,</div><div class='add'>+			   struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+</div><div class='add'>+	v4l_bound_align_image(&amp;fmt-&gt;width, alvium-&gt;img_min_width,</div><div class='add'>+			      alvium-&gt;img_max_width, 0,</div><div class='add'>+			      &amp;fmt-&gt;height, alvium-&gt;img_min_height,</div><div class='add'>+			      alvium-&gt;img_max_height, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* alvium don't accept negative crop left/top */</div><div class='add'>+	crop-&gt;left = clamp((u32)max(0, crop-&gt;left), alvium-&gt;min_offx,</div><div class='add'>+			   (u32)(alvium-&gt;img_max_width - fmt-&gt;width));</div><div class='add'>+	crop-&gt;top = clamp((u32)max(0, crop-&gt;top), alvium-&gt;min_offy,</div><div class='add'>+			  (u32)(alvium-&gt;img_max_height - fmt-&gt;height));</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_img_width(alvium, fmt-&gt;width);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_img_height(alvium, fmt-&gt;height);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_img_offx(alvium, crop-&gt;left);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_img_offy(alvium, crop-&gt;top);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_framefmt(struct alvium_dev *alvium,</div><div class='add'>+			       struct v4l2_mbus_framefmt *format)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	const struct alvium_pixfmt *alvium_csi2_fmt;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, format-&gt;code);</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_mipi_fmt(alvium, alvium_csi2_fmt);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (alvium_csi2_fmt-&gt;is_raw) {</div><div class='add'>+		ret = alvium_set_bayer_pattern(alvium, alvium_csi2_fmt);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "start: %s, mipi_fmt_regval regval = 0x%llx",</div><div class='add'>+		__func__, alvium_csi2_fmt-&gt;mipi_fmt_regval);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;alvium-&gt;sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		ret = pm_runtime_resume_and_get(&amp;client-&gt;dev);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		ret = __v4l2_ctrl_handler_setup(&amp;alvium-&gt;ctrls.handler);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		ret = alvium_set_mode(alvium, state);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+		ret = alvium_set_framefmt(alvium, fmt);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+		ret = alvium_set_stream_mipi(alvium, enable);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		alvium_set_stream_mipi(alvium, enable);</div><div class='add'>+		pm_runtime_mark_last_busy(&amp;client-&gt;dev);</div><div class='add'>+		pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alvium-&gt;streaming = !!enable;</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	pm_runtime_put(&amp;client-&gt;dev);</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	struct alvium_mode *mode = &amp;alvium-&gt;mode;</div><div class='add'>+	struct v4l2_subdev_format sd_fmt = {</div><div class='add'>+		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='add'>+		.format = alvium_csi2_default_fmt,</div><div class='add'>+	};</div><div class='add'>+	struct v4l2_subdev_crop sd_crop = {</div><div class='add'>+		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='add'>+		.rect = {</div><div class='add'>+			.left = mode-&gt;crop.left,</div><div class='add'>+			.top = mode-&gt;crop.top,</div><div class='add'>+			.width = mode-&gt;crop.width,</div><div class='add'>+			.height = mode-&gt;crop.height,</div><div class='add'>+		},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	*v4l2_subdev_state_get_crop(state, 0) = sd_crop.rect;</div><div class='add'>+	*v4l2_subdev_state_get_format(state, 0) = sd_fmt.format;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_fmt(struct v4l2_subdev *sd,</div><div class='add'>+			  struct v4l2_subdev_state *sd_state,</div><div class='add'>+			  struct v4l2_subdev_format *format)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	const struct alvium_pixfmt *alvium_csi2_fmt;</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	v4l_bound_align_image(&amp;format-&gt;format.width, alvium-&gt;img_min_width,</div><div class='add'>+			      alvium-&gt;img_max_width, 0,</div><div class='add'>+			      &amp;format-&gt;format.height, alvium-&gt;img_min_height,</div><div class='add'>+			      alvium-&gt;img_max_height, 0, 0);</div><div class='add'>+</div><div class='add'>+	/* Adjust left and top to prevent roll over sensor area */</div><div class='add'>+	crop-&gt;left = clamp((u32)crop-&gt;left, (u32)0,</div><div class='add'>+			   (alvium-&gt;img_max_width - fmt-&gt;width));</div><div class='add'>+	crop-&gt;top = clamp((u32)crop-&gt;top, (u32)0,</div><div class='add'>+			  (alvium-&gt;img_max_height - fmt-&gt;height));</div><div class='add'>+</div><div class='add'>+	/* Set also the crop width and height when set a new fmt */</div><div class='add'>+	crop-&gt;width = fmt-&gt;width;</div><div class='add'>+	crop-&gt;height = fmt-&gt;height;</div><div class='add'>+</div><div class='add'>+	alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, format-&gt;format.code);</div><div class='add'>+	fmt-&gt;code = alvium_csi2_fmt-&gt;code;</div><div class='add'>+</div><div class='add'>+	*fmt = format-&gt;format;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_selection(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state,</div><div class='add'>+				struct v4l2_subdev_selection *sel)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+</div><div class='add'>+	if (sel-&gt;target != V4L2_SEL_TGT_CROP)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Alvium can only shift the origin of the img</div><div class='add'>+	 * then we accept only value with the same value of the actual fmt</div><div class='add'>+	 */</div><div class='add'>+	if (sel-&gt;r.width != fmt-&gt;width)</div><div class='add'>+		sel-&gt;r.width = fmt-&gt;width;</div><div class='add'>+</div><div class='add'>+	if (sel-&gt;r.height != fmt-&gt;height)</div><div class='add'>+		sel-&gt;r.height = fmt-&gt;height;</div><div class='add'>+</div><div class='add'>+	/* alvium don't accept negative crop left/top */</div><div class='add'>+	crop-&gt;left = clamp((u32)max(0, sel-&gt;r.left), alvium-&gt;min_offx,</div><div class='add'>+			   alvium-&gt;img_max_width - sel-&gt;r.width);</div><div class='add'>+	crop-&gt;top = clamp((u32)max(0, sel-&gt;r.top), alvium-&gt;min_offy,</div><div class='add'>+			  alvium-&gt;img_max_height - sel-&gt;r.height);</div><div class='add'>+</div><div class='add'>+	sel-&gt;r = *crop;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_selection(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state,</div><div class='add'>+				struct v4l2_subdev_selection *sel)</div><div class='add'>+{</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+</div><div class='add'>+	switch (sel-&gt;target) {</div><div class='add'>+	/* Current cropping area */</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+		break;</div><div class='add'>+	/* Cropping bounds */</div><div class='add'>+	case V4L2_SEL_TGT_NATIVE_SIZE:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = alvium-&gt;img_max_width;</div><div class='add'>+		sel-&gt;r.height = alvium-&gt;img_max_height;</div><div class='add'>+		break;</div><div class='add'>+	/* Default cropping area */</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+		sel-&gt;r.top = alvium-&gt;min_offy;</div><div class='add'>+		sel-&gt;r.left = alvium-&gt;min_offx;</div><div class='add'>+		sel-&gt;r.width = alvium-&gt;img_max_width;</div><div class='add'>+		sel-&gt;r.height = alvium-&gt;img_max_height;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_g_volatile_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_GAIN:</div><div class='add'>+		val = alvium_get_gain(alvium);</div><div class='add'>+		if (val &lt; 0)</div><div class='add'>+			return val;</div><div class='add'>+		alvium-&gt;ctrls.gain-&gt;val = val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_EXPOSURE:</div><div class='add'>+		val = alvium_get_exposure(alvium);</div><div class='add'>+		if (val &lt; 0)</div><div class='add'>+			return val;</div><div class='add'>+		alvium-&gt;ctrls.exposure-&gt;val = val;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;alvium-&gt;sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Applying V4L2 control value only happens</div><div class='add'>+	 * when power is up for streaming</div><div class='add'>+	 */</div><div class='add'>+	if (!pm_runtime_get_if_in_use(&amp;client-&gt;dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_GAIN:</div><div class='add'>+		ret = alvium_set_ctrl_gain(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_AUTOGAIN:</div><div class='add'>+		ret = alvium_set_ctrl_auto_gain(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_EXPOSURE:</div><div class='add'>+		ret = alvium_set_ctrl_exposure(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_EXPOSURE_AUTO:</div><div class='add'>+		ret = alvium_set_ctrl_auto_exposure(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_RED_BALANCE:</div><div class='add'>+		ret = alvium_set_ctrl_red_balance_ratio(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_BLUE_BALANCE:</div><div class='add'>+		ret = alvium_set_ctrl_blue_balance_ratio(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_AUTO_WHITE_BALANCE:</div><div class='add'>+		ret = alvium_set_ctrl_awb(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_HUE:</div><div class='add'>+		ret = alvium_set_ctrl_hue(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_CONTRAST:</div><div class='add'>+		ret = alvium_set_ctrl_contrast(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_SATURATION:</div><div class='add'>+		ret = alvium_set_ctrl_saturation(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_GAMMA:</div><div class='add'>+		ret = alvium_set_ctrl_gamma(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_SHARPNESS:</div><div class='add'>+		ret = alvium_set_ctrl_sharpness(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+		ret = alvium_set_ctrl_hflip(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+		ret = alvium_set_ctrl_vflip(alvium, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops alvium_ctrl_ops = {</div><div class='add'>+	.g_volatile_ctrl = alvium_g_volatile_ctrl,</div><div class='add'>+	.s_ctrl = alvium_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int alvium_ctrl_init(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	const struct v4l2_ctrl_ops *ops = &amp;alvium_ctrl_ops;</div><div class='add'>+	struct alvium_ctrls *ctrls = &amp;alvium-&gt;ctrls;</div><div class='add'>+	struct v4l2_ctrl_handler *hdl = &amp;ctrls-&gt;handler;</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_handler_init(hdl, 32);</div><div class='add'>+</div><div class='add'>+	/* Pixel rate is fixed */</div><div class='add'>+	ctrls-&gt;pixel_rate = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+					      V4L2_CID_PIXEL_RATE, 0,</div><div class='add'>+					      ALVIUM_DEFAULT_PIXEL_RATE_MHZ, 1,</div><div class='add'>+					      ALVIUM_DEFAULT_PIXEL_RATE_MHZ);</div><div class='add'>+	ctrls-&gt;pixel_rate-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	/* Link freq is fixed */</div><div class='add'>+	ctrls-&gt;link_freq = v4l2_ctrl_new_int_menu(hdl, ops,</div><div class='add'>+						  V4L2_CID_LINK_FREQ,</div><div class='add'>+						  0, 0, &amp;alvium-&gt;link_freq);</div><div class='add'>+	ctrls-&gt;link_freq-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	/* Auto/manual white balance */</div><div class='add'>+	if (alvium-&gt;avail_ft.auto_whiteb) {</div><div class='add'>+		ctrls-&gt;auto_wb = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						   V4L2_CID_AUTO_WHITE_BALANCE,</div><div class='add'>+						   0, 1, 1, 1);</div><div class='add'>+		v4l2_ctrl_auto_cluster(3, &amp;ctrls-&gt;auto_wb, 0, false);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;blue_balance = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						V4L2_CID_BLUE_BALANCE,</div><div class='add'>+						alvium-&gt;min_bbalance,</div><div class='add'>+						alvium-&gt;max_bbalance,</div><div class='add'>+						alvium-&gt;inc_bbalance,</div><div class='add'>+						alvium-&gt;dft_bbalance);</div><div class='add'>+	ctrls-&gt;red_balance = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+					       V4L2_CID_RED_BALANCE,</div><div class='add'>+					       alvium-&gt;min_rbalance,</div><div class='add'>+					       alvium-&gt;max_rbalance,</div><div class='add'>+					       alvium-&gt;inc_rbalance,</div><div class='add'>+					       alvium-&gt;dft_rbalance);</div><div class='add'>+</div><div class='add'>+	/* Auto/manual exposure */</div><div class='add'>+	if (alvium-&gt;avail_ft.auto_exp) {</div><div class='add'>+		ctrls-&gt;auto_exp =</div><div class='add'>+			v4l2_ctrl_new_std_menu(hdl, ops,</div><div class='add'>+					       V4L2_CID_EXPOSURE_AUTO,</div><div class='add'>+					       V4L2_EXPOSURE_MANUAL, 0,</div><div class='add'>+					       V4L2_EXPOSURE_AUTO);</div><div class='add'>+		v4l2_ctrl_auto_cluster(2, &amp;ctrls-&gt;auto_exp, 1, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;exposure = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+					    V4L2_CID_EXPOSURE,</div><div class='add'>+					    alvium-&gt;min_exp,</div><div class='add'>+					    alvium-&gt;max_exp,</div><div class='add'>+					    alvium-&gt;inc_exp,</div><div class='add'>+					    alvium-&gt;dft_exp);</div><div class='add'>+	ctrls-&gt;exposure-&gt;flags |= V4L2_CTRL_FLAG_VOLATILE;</div><div class='add'>+</div><div class='add'>+	/* Auto/manual gain */</div><div class='add'>+	if (alvium-&gt;avail_ft.auto_gain) {</div><div class='add'>+		ctrls-&gt;auto_gain = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						     V4L2_CID_AUTOGAIN,</div><div class='add'>+						     0, 1, 1, 1);</div><div class='add'>+		v4l2_ctrl_auto_cluster(2, &amp;ctrls-&gt;auto_gain, 0, true);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.gain) {</div><div class='add'>+		ctrls-&gt;gain = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						V4L2_CID_GAIN,</div><div class='add'>+						alvium-&gt;min_gain,</div><div class='add'>+						alvium-&gt;max_gain,</div><div class='add'>+						alvium-&gt;inc_gain,</div><div class='add'>+						alvium-&gt;dft_gain);</div><div class='add'>+		ctrls-&gt;gain-&gt;flags |= V4L2_CTRL_FLAG_VOLATILE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.sat)</div><div class='add'>+		ctrls-&gt;saturation = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						      V4L2_CID_SATURATION,</div><div class='add'>+						      alvium-&gt;min_sat,</div><div class='add'>+						      alvium-&gt;max_sat,</div><div class='add'>+						      alvium-&gt;inc_sat,</div><div class='add'>+						      alvium-&gt;dft_sat);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.hue)</div><div class='add'>+		ctrls-&gt;hue = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+					       V4L2_CID_HUE,</div><div class='add'>+					       alvium-&gt;min_hue,</div><div class='add'>+					       alvium-&gt;max_hue,</div><div class='add'>+					       alvium-&gt;inc_hue,</div><div class='add'>+					       alvium-&gt;dft_hue);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.contrast)</div><div class='add'>+		ctrls-&gt;contrast = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						    V4L2_CID_CONTRAST,</div><div class='add'>+						    alvium-&gt;min_contrast,</div><div class='add'>+						    alvium-&gt;max_contrast,</div><div class='add'>+						    alvium-&gt;inc_contrast,</div><div class='add'>+						    alvium-&gt;dft_contrast);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.gamma)</div><div class='add'>+		ctrls-&gt;gamma = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						 V4L2_CID_GAMMA,</div><div class='add'>+						 alvium-&gt;min_gamma,</div><div class='add'>+						 alvium-&gt;max_gamma,</div><div class='add'>+						 alvium-&gt;inc_gamma,</div><div class='add'>+						 alvium-&gt;dft_gamma);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.sharp)</div><div class='add'>+		ctrls-&gt;sharpness = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						     V4L2_CID_SHARPNESS,</div><div class='add'>+						     alvium-&gt;min_sharp,</div><div class='add'>+						     alvium-&gt;max_sharp,</div><div class='add'>+						     alvium-&gt;inc_sharp,</div><div class='add'>+						     alvium-&gt;dft_sharp);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.rev_x)</div><div class='add'>+		ctrls-&gt;hflip = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						 V4L2_CID_HFLIP,</div><div class='add'>+						 0, 1, 1, 0);</div><div class='add'>+</div><div class='add'>+	if (alvium-&gt;avail_ft.rev_y)</div><div class='add'>+		ctrls-&gt;vflip = v4l2_ctrl_new_std(hdl, ops,</div><div class='add'>+						 V4L2_CID_VFLIP,</div><div class='add'>+						 0, 1, 1, 0);</div><div class='add'>+</div><div class='add'>+	if (hdl-&gt;error) {</div><div class='add'>+		ret = hdl-&gt;error;</div><div class='add'>+		goto free_ctrls;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_device_parse(&amp;alvium-&gt;i2c_client-&gt;dev, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_ctrls;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_new_fwnode_properties(hdl, ops, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_ctrls;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;sd.ctrl_handler = hdl;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_ctrls:</div><div class='add'>+	v4l2_ctrl_handler_free(hdl);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops alvium_core_ops = {</div><div class='add'>+	.log_status = v4l2_ctrl_subdev_log_status,</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops alvium_video_ops = {</div><div class='add'>+	.s_stream		= alvium_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops alvium_pad_ops = {</div><div class='add'>+	.enum_mbus_code = alvium_enum_mbus_code,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt = alvium_set_fmt,</div><div class='add'>+	.get_selection = alvium_get_selection,</div><div class='add'>+	.set_selection = alvium_set_selection,</div><div class='add'>+	.get_frame_interval = alvium_g_frame_interval,</div><div class='add'>+	.set_frame_interval = alvium_s_frame_interval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops alvium_internal_ops = {</div><div class='add'>+	.init_state = alvium_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops alvium_subdev_ops = {</div><div class='add'>+	.core	= &amp;alvium_core_ops,</div><div class='add'>+	.pad	= &amp;alvium_pad_ops,</div><div class='add'>+	.video	= &amp;alvium_video_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int alvium_subdev_init(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = alvium-&gt;i2c_client;</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	struct v4l2_subdev *sd = &amp;alvium-&gt;sd;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Setup initial frame interval*/</div><div class='add'>+	alvium-&gt;frame_interval.numerator = 1;</div><div class='add'>+	alvium-&gt;frame_interval.denominator = ALVIUM_DEFAULT_FR_HZ;</div><div class='add'>+	alvium-&gt;fr = ALVIUM_DEFAULT_FR_HZ;</div><div class='add'>+</div><div class='add'>+	/* Setup the initial mode */</div><div class='add'>+	alvium-&gt;mode.fmt = alvium_csi2_default_fmt;</div><div class='add'>+	alvium-&gt;mode.width = alvium_csi2_default_fmt.width;</div><div class='add'>+	alvium-&gt;mode.height = alvium_csi2_default_fmt.height;</div><div class='add'>+	alvium-&gt;mode.crop.left = alvium-&gt;min_offx;</div><div class='add'>+	alvium-&gt;mode.crop.top = alvium-&gt;min_offy;</div><div class='add'>+	alvium-&gt;mode.crop.width = alvium_csi2_default_fmt.width;</div><div class='add'>+	alvium-&gt;mode.crop.height = alvium_csi2_default_fmt.height;</div><div class='add'>+</div><div class='add'>+	/* init alvium sd */</div><div class='add'>+	v4l2_i2c_subdev_init(sd, client, &amp;alvium_subdev_ops);</div><div class='add'>+</div><div class='add'>+	sd-&gt;internal_ops = &amp;alvium_internal_ops;</div><div class='add'>+	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='add'>+	alvium-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+	sd-&gt;entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='add'>+</div><div class='add'>+	ret = media_entity_pads_init(&amp;sd-&gt;entity, 1, &amp;alvium-&gt;pad);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Could not register media entity\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_ctrl_init(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Control initialization error %d\n", ret);</div><div class='add'>+		goto entity_cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	alvium-&gt;sd.state_lock = alvium-&gt;ctrls.handler.lock;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_init_finalize(sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "subdev initialization error %d\n", ret);</div><div class='add'>+		goto err_ctrls;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_ctrls:</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;alvium-&gt;ctrls.handler);</div><div class='add'>+entity_cleanup:</div><div class='add'>+	media_entity_cleanup(&amp;alvium-&gt;sd.entity);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void alvium_subdev_cleanup(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	v4l2_fwnode_endpoint_free(&amp;alvium-&gt;ep);</div><div class='add'>+	v4l2_subdev_cleanup(&amp;alvium-&gt;sd);</div><div class='add'>+	media_entity_cleanup(&amp;alvium-&gt;sd.entity);</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;alvium-&gt;ctrls.handler);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_get_dt_data(struct alvium_dev *alvium)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+	struct fwnode_handle *fwnode = dev_fwnode(dev);</div><div class='add'>+	struct fwnode_handle *endpoint;</div><div class='add'>+</div><div class='add'>+	if (!fwnode)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Only CSI2 is supported for now: */</div><div class='add'>+	alvium-&gt;ep.bus_type = V4L2_MBUS_CSI2_DPHY;</div><div class='add'>+</div><div class='add'>+	endpoint = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0);</div><div class='add'>+	if (!endpoint) {</div><div class='add'>+		dev_err(dev, "endpoint node not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &amp;alvium-&gt;ep)) {</div><div class='add'>+		dev_err(dev, "could not parse endpoint\n");</div><div class='add'>+		goto error_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!alvium-&gt;ep.nr_of_link_frequencies) {</div><div class='add'>+		dev_err(dev, "no link frequencies defined");</div><div class='add'>+		goto error_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_out:</div><div class='add'>+	v4l2_fwnode_endpoint_free(&amp;alvium-&gt;ep);</div><div class='add'>+	fwnode_handle_put(endpoint);</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_set_power(struct alvium_dev *alvium, bool on)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!on)</div><div class='add'>+		return regulator_disable(alvium-&gt;reg_vcc);</div><div class='add'>+</div><div class='add'>+	ret = regulator_enable(alvium-&gt;reg_vcc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* alvium boot time 7s */</div><div class='add'>+	msleep(7000);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_runtime_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_power(alvium, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = alvium_hw_init(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		alvium_set_power(alvium, false);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int alvium_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+</div><div class='add'>+	alvium_set_power(alvium, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops alvium_pm_ops = {</div><div class='add'>+	RUNTIME_PM_OPS(alvium_runtime_suspend, alvium_runtime_resume, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int alvium_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct alvium_dev *alvium;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	alvium = devm_kzalloc(dev, sizeof(*alvium), GFP_KERNEL);</div><div class='add'>+	if (!alvium)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;i2c_client = client;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;regmap = devm_cci_regmap_init_i2c(client, 16);</div><div class='add'>+	if (IS_ERR(alvium-&gt;regmap))</div><div class='add'>+		return PTR_ERR(alvium-&gt;regmap);</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_dt_data(alvium);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	alvium-&gt;reg_vcc = devm_regulator_get_optional(dev, "vcc-ext-in");</div><div class='add'>+	if (IS_ERR(alvium-&gt;reg_vcc))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(alvium-&gt;reg_vcc),</div><div class='add'>+				     "no vcc-ext-in regulator provided\n");</div><div class='add'>+</div><div class='add'>+	ret = alvium_set_power(alvium, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_powerdown;</div><div class='add'>+</div><div class='add'>+	if (!alvium_is_alive(alvium)) {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		dev_err_probe(dev, ret, "Device detection failed\n");</div><div class='add'>+		goto err_powerdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_get_hw_info(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "get_hw_info fail\n");</div><div class='add'>+		goto err_powerdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_hw_init(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "hw_init fail\n");</div><div class='add'>+		goto err_powerdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = alvium_setup_mipi_fmt(alvium);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "setup_mipi_fmt fail\n");</div><div class='add'>+		goto err_powerdown;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enable runtime PM without autosuspend:</div><div class='add'>+	 *</div><div class='add'>+	 * Don't use pm autosuspend (alvium have ~7s boot time).</div><div class='add'>+	 * Alvium has been powered manually:</div><div class='add'>+	 *  - mark it as active</div><div class='add'>+	 *  - increase the usage count without resuming the device.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_set_active(dev);</div><div class='add'>+	pm_runtime_get_noresume(dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+</div><div class='add'>+	/* Initialize the V4L2 subdev. */</div><div class='add'>+	ret = alvium_subdev_init(alvium);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_pm;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev(&amp;alvium-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err_probe(dev, ret, "Could not register v4l2 device\n");</div><div class='add'>+		goto err_subdev;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_subdev:</div><div class='add'>+	alvium_subdev_cleanup(alvium);</div><div class='add'>+err_pm:</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	pm_runtime_put_noidle(dev);</div><div class='add'>+	kfree(alvium-&gt;alvium_csi2_fmt);</div><div class='add'>+err_powerdown:</div><div class='add'>+	alvium_set_power(alvium, false);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void alvium_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct alvium_dev *alvium = sd_to_alvium(sd);</div><div class='add'>+	struct device *dev = &amp;alvium-&gt;i2c_client-&gt;dev;</div><div class='add'>+</div><div class='add'>+	v4l2_async_unregister_subdev(sd);</div><div class='add'>+	alvium_subdev_cleanup(alvium);</div><div class='add'>+	kfree(alvium-&gt;alvium_csi2_fmt);</div><div class='add'>+	/*</div><div class='add'>+	 * Disable runtime PM. In case runtime PM is disabled in the kernel,</div><div class='add'>+	 * make sure to turn power off manually.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	if (!pm_runtime_status_suspended(dev))</div><div class='add'>+		alvium_set_power(alvium, false);</div><div class='add'>+	pm_runtime_set_suspended(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id alvium_of_ids[] = {</div><div class='add'>+	{ .compatible = "alliedvision,alvium-csi2", },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, alvium_of_ids);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver alvium_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "alvium-csi2",</div><div class='add'>+		.pm = pm_ptr(&amp;alvium_pm_ops),</div><div class='add'>+		.of_match_table = alvium_of_ids,</div><div class='add'>+	},</div><div class='add'>+	.probe = alvium_probe,</div><div class='add'>+	.remove = alvium_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(alvium_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Allied Vision's Alvium Camera Driver");</div><div class='add'>+MODULE_AUTHOR("Tommaso Merciai &lt;tomm.merciai@gmail.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Martin Hecht &lt;martin.hecht@avnet.eu&gt;");</div><div class='add'>+MODULE_AUTHOR("Avnet Silica Software &amp; Services EMEA");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/alvium-csi2.h b/drivers/media/i2c/alvium-csi2.h<br/>new file mode 100644<br/>index 000000000000..b85a25169e79<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/alvium-csi2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/alvium-csi2.h</a></div><div class='hunk'>@@ -0,0 +1,475 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * Allied Vision Technologies GmbH Alvium camera driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Tommaso Merciai</div><div class='add'>+ * Copyright (C) 2023 Martin Hecht</div><div class='add'>+ * Copyright (C) 2023 Avnet EMG GmbH</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef ALVIUM_CSI2_H_</div><div class='add'>+#define ALVIUM_CSI2_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+#include &lt;media/v4l2-common.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_V4L2					BIT(31)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_V4L2_8BIT(n)				(REG_BCRM_V4L2 | CCI_REG8(n))</div><div class='add'>+#define REG_BCRM_V4L2_16BIT(n)				(REG_BCRM_V4L2 | CCI_REG16(n))</div><div class='add'>+#define REG_BCRM_V4L2_32BIT(n)				(REG_BCRM_V4L2 | CCI_REG32(n))</div><div class='add'>+#define REG_BCRM_V4L2_64BIT(n)				(REG_BCRM_V4L2 | CCI_REG64(n))</div><div class='add'>+</div><div class='add'>+/* Basic Control Register Map register offsets (BCRM) */</div><div class='add'>+#define REG_BCRM_MINOR_VERSION_R			CCI_REG16(0x0000)</div><div class='add'>+#define REG_BCRM_MAJOR_VERSION_R			CCI_REG16(0x0002)</div><div class='add'>+#define REG_BCRM_REG_ADDR_R				CCI_REG16(0x0014)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_FEATURE_INQUIRY_R			REG_BCRM_V4L2_64BIT(0x0008)</div><div class='add'>+#define REG_BCRM_DEVICE_FW_SPEC_VERSION_R		REG_BCRM_V4L2_8BIT(0x0010)</div><div class='add'>+#define REG_BCRM_DEVICE_FW_MAJOR_VERSION_R		REG_BCRM_V4L2_8BIT(0x0011)</div><div class='add'>+#define REG_BCRM_DEVICE_FW_MINOR_VERSION_R		REG_BCRM_V4L2_16BIT(0x0012)</div><div class='add'>+#define REG_BCRM_DEVICE_FW_PATCH_VERSION_R		REG_BCRM_V4L2_32BIT(0x0014)</div><div class='add'>+#define REG_BCRM_WRITE_HANDSHAKE_RW			REG_BCRM_V4L2_8BIT(0x0018)</div><div class='add'>+</div><div class='add'>+/* Streaming Control Registers */</div><div class='add'>+#define REG_BCRM_SUPPORTED_CSI2_LANE_COUNTS_R		REG_BCRM_V4L2_8BIT(0x0040)</div><div class='add'>+#define REG_BCRM_CSI2_LANE_COUNT_RW			REG_BCRM_V4L2_8BIT(0x0044)</div><div class='add'>+#define REG_BCRM_CSI2_CLOCK_MIN_R			REG_BCRM_V4L2_32BIT(0x0048)</div><div class='add'>+#define REG_BCRM_CSI2_CLOCK_MAX_R			REG_BCRM_V4L2_32BIT(0x004c)</div><div class='add'>+#define REG_BCRM_CSI2_CLOCK_RW				REG_BCRM_V4L2_32BIT(0x0050)</div><div class='add'>+#define REG_BCRM_BUFFER_SIZE_R				REG_BCRM_V4L2_32BIT(0x0054)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IPU_X_MIN_W				REG_BCRM_V4L2_32BIT(0x0058)</div><div class='add'>+#define REG_BCRM_IPU_X_MAX_W				REG_BCRM_V4L2_32BIT(0x005c)</div><div class='add'>+#define REG_BCRM_IPU_X_INC_W				REG_BCRM_V4L2_32BIT(0x0060)</div><div class='add'>+#define REG_BCRM_IPU_Y_MIN_W				REG_BCRM_V4L2_32BIT(0x0064)</div><div class='add'>+#define REG_BCRM_IPU_Y_MAX_W				REG_BCRM_V4L2_32BIT(0x0068)</div><div class='add'>+#define REG_BCRM_IPU_Y_INC_W				REG_BCRM_V4L2_32BIT(0x006c)</div><div class='add'>+#define REG_BCRM_IPU_X_R				REG_BCRM_V4L2_32BIT(0x0070)</div><div class='add'>+#define REG_BCRM_IPU_Y_R				REG_BCRM_V4L2_32BIT(0x0074)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_PHY_RESET_RW				REG_BCRM_V4L2_8BIT(0x0078)</div><div class='add'>+#define REG_BCRM_LP2HS_DELAY_RW				REG_BCRM_V4L2_32BIT(0x007c)</div><div class='add'>+</div><div class='add'>+/* Acquisition Control Registers */</div><div class='add'>+#define REG_BCRM_ACQUISITION_START_RW			REG_BCRM_V4L2_8BIT(0x0080)</div><div class='add'>+#define REG_BCRM_ACQUISITION_STOP_RW			REG_BCRM_V4L2_8BIT(0x0084)</div><div class='add'>+#define REG_BCRM_ACQUISITION_ABORT_RW			REG_BCRM_V4L2_8BIT(0x0088)</div><div class='add'>+#define REG_BCRM_ACQUISITION_STATUS_R			REG_BCRM_V4L2_8BIT(0x008c)</div><div class='add'>+#define REG_BCRM_ACQUISITION_FRAME_RATE_RW		REG_BCRM_V4L2_64BIT(0x0090)</div><div class='add'>+#define REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R		REG_BCRM_V4L2_64BIT(0x0098)</div><div class='add'>+#define REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R		REG_BCRM_V4L2_64BIT(0x00a0)</div><div class='add'>+#define REG_BCRM_ACQUISITION_FRAME_RATE_INC_R		REG_BCRM_V4L2_64BIT(0x00a8)</div><div class='add'>+#define REG_BCRM_ACQUISITION_FRAME_RATE_ENABLE_RW	REG_BCRM_V4L2_8BIT(0x00b0)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_FRAME_START_TRIGGER_MODE_RW		REG_BCRM_V4L2_8BIT(0x00b4)</div><div class='add'>+#define REG_BCRM_FRAME_START_TRIGGER_SOURCE_RW		REG_BCRM_V4L2_8BIT(0x00b8)</div><div class='add'>+#define REG_BCRM_FRAME_START_TRIGGER_ACTIVATION_RW	REG_BCRM_V4L2_8BIT(0x00bc)</div><div class='add'>+#define REG_BCRM_FRAME_START_TRIGGER_SOFTWARE_W		REG_BCRM_V4L2_8BIT(0x00c0)</div><div class='add'>+#define REG_BCRM_FRAME_START_TRIGGER_DELAY_RW		REG_BCRM_V4L2_32BIT(0x00c4)</div><div class='add'>+#define REG_BCRM_EXPOSURE_ACTIVE_LINE_MODE_RW		REG_BCRM_V4L2_8BIT(0x00c8)</div><div class='add'>+#define REG_BCRM_EXPOSURE_ACTIVE_LINE_SELECTOR_RW	REG_BCRM_V4L2_8BIT(0x00cc)</div><div class='add'>+#define REG_BCRM_LINE_CONFIGURATION_RW			REG_BCRM_V4L2_32BIT(0x00d0)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IMG_WIDTH_RW				REG_BCRM_V4L2_32BIT(0x0100)</div><div class='add'>+#define REG_BCRM_IMG_WIDTH_MIN_R			REG_BCRM_V4L2_32BIT(0x0104)</div><div class='add'>+#define REG_BCRM_IMG_WIDTH_MAX_R			REG_BCRM_V4L2_32BIT(0x0108)</div><div class='add'>+#define REG_BCRM_IMG_WIDTH_INC_R			REG_BCRM_V4L2_32BIT(0x010c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IMG_HEIGHT_RW				REG_BCRM_V4L2_32BIT(0x0110)</div><div class='add'>+#define REG_BCRM_IMG_HEIGHT_MIN_R			REG_BCRM_V4L2_32BIT(0x0114)</div><div class='add'>+#define REG_BCRM_IMG_HEIGHT_MAX_R			REG_BCRM_V4L2_32BIT(0x0118)</div><div class='add'>+#define REG_BCRM_IMG_HEIGHT_INC_R			REG_BCRM_V4L2_32BIT(0x011c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_X_RW			REG_BCRM_V4L2_32BIT(0x0120)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_X_MIN_R			REG_BCRM_V4L2_32BIT(0x0124)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_X_MAX_R			REG_BCRM_V4L2_32BIT(0x0128)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_X_INC_R			REG_BCRM_V4L2_32BIT(0x012c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_Y_RW			REG_BCRM_V4L2_32BIT(0x0130)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_Y_MIN_R			REG_BCRM_V4L2_32BIT(0x0134)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_Y_MAX_R			REG_BCRM_V4L2_32BIT(0x0138)</div><div class='add'>+#define REG_BCRM_IMG_OFFSET_Y_INC_R			REG_BCRM_V4L2_32BIT(0x013c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_IMG_MIPI_DATA_FORMAT_RW		REG_BCRM_V4L2_32BIT(0x0140)</div><div class='add'>+#define REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R	REG_BCRM_V4L2_64BIT(0x0148)</div><div class='add'>+#define REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R		REG_BCRM_V4L2_8BIT(0x0150)</div><div class='add'>+#define REG_BCRM_IMG_BAYER_PATTERN_RW			REG_BCRM_V4L2_8BIT(0x0154)</div><div class='add'>+#define REG_BCRM_IMG_REVERSE_X_RW			REG_BCRM_V4L2_8BIT(0x0158)</div><div class='add'>+#define REG_BCRM_IMG_REVERSE_Y_RW			REG_BCRM_V4L2_8BIT(0x015c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_SENSOR_WIDTH_R				REG_BCRM_V4L2_32BIT(0x0160)</div><div class='add'>+#define REG_BCRM_SENSOR_HEIGHT_R			REG_BCRM_V4L2_32BIT(0x0164)</div><div class='add'>+#define REG_BCRM_WIDTH_MAX_R				REG_BCRM_V4L2_32BIT(0x0168)</div><div class='add'>+#define REG_BCRM_HEIGHT_MAX_R				REG_BCRM_V4L2_32BIT(0x016c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_EXPOSURE_TIME_RW			REG_BCRM_V4L2_64BIT(0x0180)</div><div class='add'>+#define REG_BCRM_EXPOSURE_TIME_MIN_R			REG_BCRM_V4L2_64BIT(0x0188)</div><div class='add'>+#define REG_BCRM_EXPOSURE_TIME_MAX_R			REG_BCRM_V4L2_64BIT(0x0190)</div><div class='add'>+#define REG_BCRM_EXPOSURE_TIME_INC_R			REG_BCRM_V4L2_64BIT(0x0198)</div><div class='add'>+#define REG_BCRM_EXPOSURE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x01a0)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_RW		REG_BCRM_V4L2_8BIT(0x01a4)</div><div class='add'>+#define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_VALUE_RW	REG_BCRM_V4L2_32BIT(0x01a8)</div><div class='add'>+#define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MIN_R	REG_BCRM_V4L2_32BIT(0x01ac)</div><div class='add'>+#define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_MAX_R	REG_BCRM_V4L2_32BIT(0x01b0)</div><div class='add'>+#define REG_BCRM_INTENSITY_AUTO_PRECEDENCE_INC_R	REG_BCRM_V4L2_32BIT(0x01b4)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_BLACK_LEVEL_RW				REG_BCRM_V4L2_32BIT(0x01b8)</div><div class='add'>+#define REG_BCRM_BLACK_LEVEL_MIN_R			REG_BCRM_V4L2_32BIT(0x01bc)</div><div class='add'>+#define REG_BCRM_BLACK_LEVEL_MAX_R			REG_BCRM_V4L2_32BIT(0x01c0)</div><div class='add'>+#define REG_BCRM_BLACK_LEVEL_INC_R			REG_BCRM_V4L2_32BIT(0x01c4)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_GAIN_RW				REG_BCRM_V4L2_64BIT(0x01c8)</div><div class='add'>+#define REG_BCRM_GAIN_MIN_R				REG_BCRM_V4L2_64BIT(0x01d0)</div><div class='add'>+#define REG_BCRM_GAIN_MAX_R				REG_BCRM_V4L2_64BIT(0x01d8)</div><div class='add'>+#define REG_BCRM_GAIN_INC_R				REG_BCRM_V4L2_64BIT(0x01e0)</div><div class='add'>+#define REG_BCRM_GAIN_AUTO_RW				REG_BCRM_V4L2_8BIT(0x01e8)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_GAMMA_RW				REG_BCRM_V4L2_64BIT(0x01f0)</div><div class='add'>+#define REG_BCRM_GAMMA_MIN_R				REG_BCRM_V4L2_64BIT(0x01f8)</div><div class='add'>+#define REG_BCRM_GAMMA_MAX_R				REG_BCRM_V4L2_64BIT(0x0200)</div><div class='add'>+#define REG_BCRM_GAMMA_INC_R				REG_BCRM_V4L2_64BIT(0x0208)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_CONTRAST_VALUE_RW			REG_BCRM_V4L2_32BIT(0x0214)</div><div class='add'>+#define REG_BCRM_CONTRAST_VALUE_MIN_R			REG_BCRM_V4L2_32BIT(0x0218)</div><div class='add'>+#define REG_BCRM_CONTRAST_VALUE_MAX_R			REG_BCRM_V4L2_32BIT(0x021c)</div><div class='add'>+#define REG_BCRM_CONTRAST_VALUE_INC_R			REG_BCRM_V4L2_32BIT(0x0220)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_SATURATION_RW				REG_BCRM_V4L2_32BIT(0x0240)</div><div class='add'>+#define REG_BCRM_SATURATION_MIN_R			REG_BCRM_V4L2_32BIT(0x0244)</div><div class='add'>+#define REG_BCRM_SATURATION_MAX_R			REG_BCRM_V4L2_32BIT(0x0248)</div><div class='add'>+#define REG_BCRM_SATURATION_INC_R			REG_BCRM_V4L2_32BIT(0x024c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_HUE_RW					REG_BCRM_V4L2_32BIT(0x0250)</div><div class='add'>+#define REG_BCRM_HUE_MIN_R				REG_BCRM_V4L2_32BIT(0x0254)</div><div class='add'>+#define REG_BCRM_HUE_MAX_R				REG_BCRM_V4L2_32BIT(0x0258)</div><div class='add'>+#define REG_BCRM_HUE_INC_R				REG_BCRM_V4L2_32BIT(0x025c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_ALL_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0260)</div><div class='add'>+#define REG_BCRM_ALL_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0268)</div><div class='add'>+#define REG_BCRM_ALL_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0270)</div><div class='add'>+#define REG_BCRM_ALL_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0278)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_RED_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x0280)</div><div class='add'>+#define REG_BCRM_RED_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x0288)</div><div class='add'>+#define REG_BCRM_RED_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x0290)</div><div class='add'>+#define REG_BCRM_RED_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x0298)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_GREEN_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02a0)</div><div class='add'>+#define REG_BCRM_GREEN_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02a8)</div><div class='add'>+#define REG_BCRM_GREEN_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02b0)</div><div class='add'>+#define REG_BCRM_GREEN_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02b8)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_BLUE_BALANCE_RATIO_RW			REG_BCRM_V4L2_64BIT(0x02c0)</div><div class='add'>+#define REG_BCRM_BLUE_BALANCE_RATIO_MIN_R		REG_BCRM_V4L2_64BIT(0x02c8)</div><div class='add'>+#define REG_BCRM_BLUE_BALANCE_RATIO_MAX_R		REG_BCRM_V4L2_64BIT(0x02d0)</div><div class='add'>+#define REG_BCRM_BLUE_BALANCE_RATIO_INC_R		REG_BCRM_V4L2_64BIT(0x02d8)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_WHITE_BALANCE_AUTO_RW			REG_BCRM_V4L2_8BIT(0x02e0)</div><div class='add'>+#define REG_BCRM_SHARPNESS_RW				REG_BCRM_V4L2_32BIT(0x0300)</div><div class='add'>+#define REG_BCRM_SHARPNESS_MIN_R			REG_BCRM_V4L2_32BIT(0x0304)</div><div class='add'>+#define REG_BCRM_SHARPNESS_MAX_R			REG_BCRM_V4L2_32BIT(0x0308)</div><div class='add'>+#define REG_BCRM_SHARPNESS_INC_R			REG_BCRM_V4L2_32BIT(0x030c)</div><div class='add'>+</div><div class='add'>+#define REG_BCRM_DEVICE_TEMPERATURE_R			REG_BCRM_V4L2_32BIT(0x0310)</div><div class='add'>+#define REG_BCRM_EXPOSURE_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0330)</div><div class='add'>+#define REG_BCRM_EXPOSURE_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0338)</div><div class='add'>+#define REG_BCRM_GAIN_AUTO_MIN_RW			REG_BCRM_V4L2_64BIT(0x0340)</div><div class='add'>+#define REG_BCRM_GAIN_AUTO_MAX_RW			REG_BCRM_V4L2_64BIT(0x0348)</div><div class='add'>+</div><div class='add'>+/* Heartbeat reg*/</div><div class='add'>+#define REG_BCRM_HEARTBEAT_RW				CCI_REG8(0x021f)</div><div class='add'>+</div><div class='add'>+/* GenCP Registers */</div><div class='add'>+#define REG_GENCP_CHANGEMODE_W				CCI_REG8(0x021c)</div><div class='add'>+#define REG_GENCP_CURRENTMODE_R				CCI_REG8(0x021d)</div><div class='add'>+#define REG_GENCP_IN_HANDSHAKE_RW			CCI_REG8(0x001c)</div><div class='add'>+#define REG_GENCP_OUT_SIZE_W				CCI_REG16(0x0020)</div><div class='add'>+#define REG_GENCP_IN_SIZE_R				CCI_REG16(0x0024)</div><div class='add'>+</div><div class='add'>+/* defines */</div><div class='add'>+#define REG_BCRM_HANDSHAKE_STATUS_MASK			0x01</div><div class='add'>+#define REG_BCRM_HANDSHAKE_AVAILABLE_MASK		0x80</div><div class='add'>+</div><div class='add'>+#define BCRM_HANDSHAKE_W_DONE_EN_BIT			BIT(0)</div><div class='add'>+</div><div class='add'>+#define ALVIUM_DEFAULT_FR_HZ				10</div><div class='add'>+#define ALVIUM_DEFAULT_PIXEL_RATE_MHZ			148000000</div><div class='add'>+</div><div class='add'>+#define ALVIUM_LP2HS_DELAY_MS				100</div><div class='add'>+</div><div class='add'>+enum alvium_bcrm_mode {</div><div class='add'>+	ALVIUM_BCM_MODE,</div><div class='add'>+	ALVIUM_GENCP_MODE,</div><div class='add'>+	ALVIUM_NUM_MODE</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum alvium_mipi_fmt {</div><div class='add'>+	ALVIUM_FMT_UYVY8_2X8 = 0,</div><div class='add'>+	ALVIUM_FMT_UYVY8_1X16,</div><div class='add'>+	ALVIUM_FMT_YUYV8_1X16,</div><div class='add'>+	ALVIUM_FMT_YUYV8_2X8,</div><div class='add'>+	ALVIUM_FMT_YUYV10_1X20,</div><div class='add'>+	ALVIUM_FMT_RGB888_1X24,</div><div class='add'>+	ALVIUM_FMT_RBG888_1X24,</div><div class='add'>+	ALVIUM_FMT_BGR888_1X24,</div><div class='add'>+	ALVIUM_FMT_RGB888_3X8,</div><div class='add'>+	ALVIUM_FMT_Y8_1X8,</div><div class='add'>+	ALVIUM_FMT_SGRBG8_1X8,</div><div class='add'>+	ALVIUM_FMT_SRGGB8_1X8,</div><div class='add'>+	ALVIUM_FMT_SGBRG8_1X8,</div><div class='add'>+	ALVIUM_FMT_SBGGR8_1X8,</div><div class='add'>+	ALVIUM_FMT_Y10_1X10,</div><div class='add'>+	ALVIUM_FMT_SGRBG10_1X10,</div><div class='add'>+	ALVIUM_FMT_SRGGB10_1X10,</div><div class='add'>+	ALVIUM_FMT_SGBRG10_1X10,</div><div class='add'>+	ALVIUM_FMT_SBGGR10_1X10,</div><div class='add'>+	ALVIUM_FMT_Y12_1X12,</div><div class='add'>+	ALVIUM_FMT_SGRBG12_1X12,</div><div class='add'>+	ALVIUM_FMT_SRGGB12_1X12,</div><div class='add'>+	ALVIUM_FMT_SGBRG12_1X12,</div><div class='add'>+	ALVIUM_FMT_SBGGR12_1X12,</div><div class='add'>+	ALVIUM_FMT_SBGGR14_1X14,</div><div class='add'>+	ALVIUM_FMT_SGBRG14_1X14,</div><div class='add'>+	ALVIUM_FMT_SRGGB14_1X14,</div><div class='add'>+	ALVIUM_FMT_SGRBG14_1X14,</div><div class='add'>+	ALVIUM_NUM_SUPP_MIPI_DATA_FMT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum alvium_av_bayer_bit {</div><div class='add'>+	ALVIUM_BIT_BAY_NONE = -1,</div><div class='add'>+	ALVIUM_BIT_BAY_MONO = 0,</div><div class='add'>+	ALVIUM_BIT_BAY_GR,</div><div class='add'>+	ALVIUM_BIT_BAY_RG,</div><div class='add'>+	ALVIUM_BIT_BAY_GB,</div><div class='add'>+	ALVIUM_BIT_BAY_BG,</div><div class='add'>+	ALVIUM_NUM_BAY_AV_BIT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum alvium_av_mipi_bit {</div><div class='add'>+	ALVIUM_BIT_YUV420_8_LEG = 0,</div><div class='add'>+	ALVIUM_BIT_YUV420_8,</div><div class='add'>+	ALVIUM_BIT_YUV420_10,</div><div class='add'>+	ALVIUM_BIT_YUV420_8_CSPS,</div><div class='add'>+	ALVIUM_BIT_YUV420_10_CSPS,</div><div class='add'>+	ALVIUM_BIT_YUV422_8,</div><div class='add'>+	ALVIUM_BIT_YUV422_10,</div><div class='add'>+	ALVIUM_BIT_RGB888,</div><div class='add'>+	ALVIUM_BIT_RGB666,</div><div class='add'>+	ALVIUM_BIT_RGB565,</div><div class='add'>+	ALVIUM_BIT_RGB555,</div><div class='add'>+	ALVIUM_BIT_RGB444,</div><div class='add'>+	ALVIUM_BIT_RAW6,</div><div class='add'>+	ALVIUM_BIT_RAW7,</div><div class='add'>+	ALVIUM_BIT_RAW8,</div><div class='add'>+	ALVIUM_BIT_RAW10,</div><div class='add'>+	ALVIUM_BIT_RAW12,</div><div class='add'>+	ALVIUM_BIT_RAW14,</div><div class='add'>+	ALVIUM_BIT_JPEG,</div><div class='add'>+	ALVIUM_NUM_SUPP_MIPI_DATA_BIT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_avail_feat {</div><div class='add'>+	u64 rev_x:1;</div><div class='add'>+	u64 rev_y:1;</div><div class='add'>+	u64 int_autop:1;</div><div class='add'>+	u64 black_lvl:1;</div><div class='add'>+	u64 gain:1;</div><div class='add'>+	u64 gamma:1;</div><div class='add'>+	u64 contrast:1;</div><div class='add'>+	u64 sat:1;</div><div class='add'>+	u64 hue:1;</div><div class='add'>+	u64 whiteb:1;</div><div class='add'>+	u64 sharp:1;</div><div class='add'>+	u64 auto_exp:1;</div><div class='add'>+	u64 auto_gain:1;</div><div class='add'>+	u64 auto_whiteb:1;</div><div class='add'>+	u64 dev_temp:1;</div><div class='add'>+	u64 acq_abort:1;</div><div class='add'>+	u64 acq_fr:1;</div><div class='add'>+	u64 fr_trigger:1;</div><div class='add'>+	u64 exp_acq_line:1;</div><div class='add'>+	u64 reserved:45;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_avail_mipi_fmt {</div><div class='add'>+	u64 yuv420_8_leg:1;</div><div class='add'>+	u64 yuv420_8:1;</div><div class='add'>+	u64 yuv420_10:1;</div><div class='add'>+	u64 yuv420_8_csps:1;</div><div class='add'>+	u64 yuv420_10_csps:1;</div><div class='add'>+	u64 yuv422_8:1;</div><div class='add'>+	u64 yuv422_10:1;</div><div class='add'>+	u64 rgb888:1;</div><div class='add'>+	u64 rgb666:1;</div><div class='add'>+	u64 rgb565:1;</div><div class='add'>+	u64 rgb555:1;</div><div class='add'>+	u64 rgb444:1;</div><div class='add'>+	u64 raw6:1;</div><div class='add'>+	u64 raw7:1;</div><div class='add'>+	u64 raw8:1;</div><div class='add'>+	u64 raw10:1;</div><div class='add'>+	u64 raw12:1;</div><div class='add'>+	u64 raw14:1;</div><div class='add'>+	u64 jpeg:1;</div><div class='add'>+	u64 reserved:45;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_avail_bayer {</div><div class='add'>+	u8 mono:1;</div><div class='add'>+	u8 gr:1;</div><div class='add'>+	u8 rg:1;</div><div class='add'>+	u8 gb:1;</div><div class='add'>+	u8 bg:1;</div><div class='add'>+	u8 reserved:3;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_mode {</div><div class='add'>+	struct v4l2_rect crop;</div><div class='add'>+	struct v4l2_mbus_framefmt fmt;</div><div class='add'>+	u32 width;</div><div class='add'>+	u32 height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_pixfmt {</div><div class='add'>+	u32 code;</div><div class='add'>+	u32 colorspace;</div><div class='add'>+	u64 mipi_fmt_regval;</div><div class='add'>+	u64 bay_fmt_regval;</div><div class='add'>+	u8 id;</div><div class='add'>+	u8 is_raw;</div><div class='add'>+	u8 fmt_av_bit;</div><div class='add'>+	u8 bay_av_bit;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_ctrls {</div><div class='add'>+	struct v4l2_ctrl_handler handler;</div><div class='add'>+	struct v4l2_ctrl *pixel_rate;</div><div class='add'>+	struct v4l2_ctrl *link_freq;</div><div class='add'>+	struct v4l2_ctrl *auto_exp;</div><div class='add'>+	struct v4l2_ctrl *exposure;</div><div class='add'>+	struct v4l2_ctrl *auto_wb;</div><div class='add'>+	struct v4l2_ctrl *blue_balance;</div><div class='add'>+	struct v4l2_ctrl *red_balance;</div><div class='add'>+	struct v4l2_ctrl *auto_gain;</div><div class='add'>+	struct v4l2_ctrl *gain;</div><div class='add'>+	struct v4l2_ctrl *saturation;</div><div class='add'>+	struct v4l2_ctrl *hue;</div><div class='add'>+	struct v4l2_ctrl *contrast;</div><div class='add'>+	struct v4l2_ctrl *gamma;</div><div class='add'>+	struct v4l2_ctrl *sharpness;</div><div class='add'>+	struct v4l2_ctrl *hflip;</div><div class='add'>+	struct v4l2_ctrl *vflip;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct alvium_dev {</div><div class='add'>+	struct i2c_client *i2c_client;</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct v4l2_fwnode_endpoint ep;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	struct regulator *reg_vcc;</div><div class='add'>+</div><div class='add'>+	u16 bcrm_addr;</div><div class='add'>+</div><div class='add'>+	struct alvium_avail_feat avail_ft;</div><div class='add'>+	u8 is_mipi_fmt_avail[ALVIUM_NUM_SUPP_MIPI_DATA_BIT];</div><div class='add'>+	u8 is_bay_avail[ALVIUM_NUM_BAY_AV_BIT];</div><div class='add'>+</div><div class='add'>+	u32 min_csi_clk;</div><div class='add'>+	u32 max_csi_clk;</div><div class='add'>+	u32 dft_img_width;</div><div class='add'>+	u32 img_min_width;</div><div class='add'>+	u32 img_max_width;</div><div class='add'>+	u32 img_inc_width;</div><div class='add'>+	u32 dft_img_height;</div><div class='add'>+	u32 img_min_height;</div><div class='add'>+	u32 img_max_height;</div><div class='add'>+	u32 img_inc_height;</div><div class='add'>+	u32 min_offx;</div><div class='add'>+	u32 max_offx;</div><div class='add'>+	u32 inc_offx;</div><div class='add'>+	u32 min_offy;</div><div class='add'>+	u32 max_offy;</div><div class='add'>+	u32 inc_offy;</div><div class='add'>+	u64 dft_gain;</div><div class='add'>+	u64 min_gain;</div><div class='add'>+	u64 max_gain;</div><div class='add'>+	u64 inc_gain;</div><div class='add'>+	u64 dft_exp;</div><div class='add'>+	u64 min_exp;</div><div class='add'>+	u64 max_exp;</div><div class='add'>+	u64 inc_exp;</div><div class='add'>+	u64 dft_rbalance;</div><div class='add'>+	u64 min_rbalance;</div><div class='add'>+	u64 max_rbalance;</div><div class='add'>+	u64 inc_rbalance;</div><div class='add'>+	u64 dft_bbalance;</div><div class='add'>+	u64 min_bbalance;</div><div class='add'>+	u64 max_bbalance;</div><div class='add'>+	u64 inc_bbalance;</div><div class='add'>+	s32 dft_hue;</div><div class='add'>+	s32 min_hue;</div><div class='add'>+	s32 max_hue;</div><div class='add'>+	s32 inc_hue;</div><div class='add'>+	u32 dft_contrast;</div><div class='add'>+	u32 min_contrast;</div><div class='add'>+	u32 max_contrast;</div><div class='add'>+	u32 inc_contrast;</div><div class='add'>+	u32 dft_sat;</div><div class='add'>+	u32 min_sat;</div><div class='add'>+	u32 max_sat;</div><div class='add'>+	u32 inc_sat;</div><div class='add'>+	s32 dft_black_lvl;</div><div class='add'>+	s32 min_black_lvl;</div><div class='add'>+	s32 max_black_lvl;</div><div class='add'>+	s32 inc_black_lvl;</div><div class='add'>+	u64 dft_gamma;</div><div class='add'>+	u64 min_gamma;</div><div class='add'>+	u64 max_gamma;</div><div class='add'>+	u64 inc_gamma;</div><div class='add'>+	s32 dft_sharp;</div><div class='add'>+	s32 min_sharp;</div><div class='add'>+	s32 max_sharp;</div><div class='add'>+	s32 inc_sharp;</div><div class='add'>+</div><div class='add'>+	struct alvium_mode mode;</div><div class='add'>+	struct v4l2_fract frame_interval;</div><div class='add'>+	u64 dft_fr;</div><div class='add'>+	u64 min_fr;</div><div class='add'>+	u64 max_fr;</div><div class='add'>+	u64 fr;</div><div class='add'>+</div><div class='add'>+	u8 h_sup_csi_lanes;</div><div class='add'>+	u64 link_freq;</div><div class='add'>+</div><div class='add'>+	struct alvium_ctrls ctrls;</div><div class='add'>+</div><div class='add'>+	u8 bcrm_mode;</div><div class='add'>+</div><div class='add'>+	struct alvium_pixfmt *alvium_csi2_fmt;</div><div class='add'>+	u8 alvium_csi2_fmt_n;</div><div class='add'>+</div><div class='add'>+	u8 streaming;</div><div class='add'>+	u8 apply_fiv;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct alvium_dev *sd_to_alvium(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	return container_of_const(sd, struct alvium_dev, sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	return &amp;container_of_const(ctrl-&gt;handler, struct alvium_dev,</div><div class='add'>+					  ctrls.handler)-&gt;sd;</div><div class='add'>+}</div><div class='add'>+#endif /* ALVIUM_CSI2_H_ */</div><div class='head'>diff --git a/drivers/media/i2c/ar0521.c b/drivers/media/i2c/ar0521.c<br/>index 701f36345f1e..c7d5fa532ae1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ar0521.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ar0521.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ar0521.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ar0521.c</a></div><div class='hunk'>@@ -446,8 +446,7 @@ static int ar0521_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(&amp;sensor-&gt;sd, sd_state, 0</div><div class='del'>-						 /* pad */);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		fmt = &amp;sensor-&gt;fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -472,7 +471,7 @@ static int ar0521_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*fmt = format-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 		mutex_unlock(&amp;sensor-&gt;lock);</div><div class='head'>diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig<br/>index b55c93a2e204..710a729ae42d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/Kconfig</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> config VIDEO_CCS</div><div class='ctx'> 	tristate "MIPI CCS/SMIA++/SMIA sensor support"</div><div class='ctx'> 	depends on HAVE_CLK</div><div class='add'>+	select V4L2_CCI_I2C</div><div class='ctx'> 	select VIDEO_CCS_PLL</div><div class='ctx'> 	help</div><div class='ctx'> 	  This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant</div><div class='head'>diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c<br/>index 12e6f0a26fc8..e21287d50c15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/ccs-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-core.c</a></div><div class='hunk'>@@ -25,8 +25,9 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/smiapp.h&gt;</div><div class='ctx'> #include &lt;linux/v4l2-mediabus.h&gt;</div><div class='del'>-#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='ctx'> #include &lt;uapi/linux/ccs.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "ccs.h"</div><div class='hunk'>@@ -98,7 +99,7 @@ static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,</div><div class='ctx'> 	linfo = &amp;ccs_limits[ccs_limit_offsets[limit].info];</div><div class='ctx'> </div><div class='ctx'> 	if (WARN_ON(!sensor-&gt;ccs_limits) ||</div><div class='del'>-	    WARN_ON(offset + ccs_reg_width(linfo-&gt;reg) &gt;</div><div class='add'>+	    WARN_ON(offset + CCI_REG_WIDTH_BYTES(linfo-&gt;reg) &gt;</div><div class='ctx'> 		    ccs_limit_offsets[limit + 1].lim))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -124,7 +125,7 @@ void ccs_replace_limit(struct ccs_sensor *sensor,</div><div class='ctx'> 	dev_dbg(&amp;client-&gt;dev, "quirk: 0x%8.8x \"%s\" %u = %u, 0x%x\n",</div><div class='ctx'> 		linfo-&gt;reg, linfo-&gt;name, offset, val, val);</div><div class='ctx'> </div><div class='del'>-	ccs_assign_limit(ptr, ccs_reg_width(linfo-&gt;reg), val);</div><div class='add'>+	ccs_assign_limit(ptr, CCI_REG_WIDTH_BYTES(linfo-&gt;reg), val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,</div><div class='hunk'>@@ -138,7 +139,7 @@ u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {</div><div class='add'>+	switch (CCI_REG_WIDTH_BYTES(ccs_limits[ccs_limit_offsets[limit].info].reg)) {</div><div class='ctx'> 	case sizeof(u8):</div><div class='ctx'> 		val = *(u8 *)ptr;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -172,9 +173,11 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)</div><div class='ctx'> </div><div class='ctx'> 	end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;</div><div class='ctx'> </div><div class='add'>+	sensor-&gt;ccs_limits = alloc;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {</div><div class='ctx'> 		u32 reg = ccs_limits[i].reg;</div><div class='del'>-		unsigned int width = ccs_reg_width(reg);</div><div class='add'>+		unsigned int width = CCI_REG_WIDTH_BYTES(reg);</div><div class='ctx'> 		unsigned int j;</div><div class='ctx'> </div><div class='ctx'> 		if (l == CCS_L_LAST) {</div><div class='hunk'>@@ -186,6 +189,7 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; ccs_limits[i].size / width;</div><div class='ctx'> 		     j++, reg += width, ptr += width) {</div><div class='add'>+			char str[16] = "";</div><div class='ctx'> 			u32 val;</div><div class='ctx'> </div><div class='ctx'> 			ret = ccs_read_addr_noconv(sensor, reg, &amp;val);</div><div class='hunk'>@@ -204,8 +208,15 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)</div><div class='ctx'> </div><div class='ctx'> 			ccs_assign_limit(ptr, width, val);</div><div class='ctx'> </div><div class='del'>-			dev_dbg(&amp;client-&gt;dev, "0x%8.8x \"%s\" = %u, 0x%x\n",</div><div class='del'>-				reg, ccs_limits[i].name, val, val);</div><div class='add'>+#ifdef CONFIG_DYNAMIC_DEBUG</div><div class='add'>+			if (reg &amp; (CCS_FL_FLOAT_IREAL | CCS_FL_IREAL))</div><div class='add'>+				snprintf(str, sizeof(str), ", %u",</div><div class='add'>+					 ccs_reg_conv(sensor, reg, val));</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+			dev_dbg(&amp;client-&gt;dev,</div><div class='add'>+				"0x%8.8x \"%s\" = %u, 0x%x%s\n",</div><div class='add'>+				reg, ccs_limits[i].name, val, val, str);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (ccs_limits[i].flags &amp; CCS_L_FL_SAME_REG)</div><div class='hunk'>@@ -222,14 +233,13 @@ static int ccs_read_all_limits(struct ccs_sensor *sensor)</div><div class='ctx'> 		goto out_err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sensor-&gt;ccs_limits = alloc;</div><div class='del'>-</div><div class='ctx'> 	if (CCS_LIM(sensor, SCALER_N_MIN) &lt; 16)</div><div class='ctx'> 		ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_err:</div><div class='add'>+	sensor-&gt;ccs_limits = NULL;</div><div class='ctx'> 	kfree(alloc);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -1878,9 +1888,11 @@ static int ccs_pm_get_init(struct ccs_sensor *sensor)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='ctx'> 	/* Device was already active, so don't set controls */</div><div class='del'>-	if (rval == 1)</div><div class='add'>+	if (rval == 1 &amp;&amp; !sensor-&gt;handler_setup_needed)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	sensor-&gt;handler_setup_needed = false;</div><div class='add'>+</div><div class='ctx'> 	/* Restore V4L2 controls to the previously suspended device */</div><div class='ctx'> 	rval = v4l2_ctrl_handler_setup(&amp;sensor-&gt;pixel_array-&gt;ctrl_handler);</div><div class='ctx'> 	if (rval)</div><div class='hunk'>@@ -2030,7 +2042,7 @@ static int __ccs_get_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			    struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 			    struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='del'>-	fmt-&gt;format = *v4l2_subdev_get_pad_format(subdev, sd_state, fmt-&gt;pad);</div><div class='add'>+	fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 	fmt-&gt;format.code = __ccs_get_mbus_code(subdev, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2061,10 +2073,10 @@ static void ccs_get_crop_compose(struct v4l2_subdev *subdev,</div><div class='ctx'> 	if (crops)</div><div class='ctx'> 		for (i = 0; i &lt; subdev-&gt;entity.num_pads; i++)</div><div class='ctx'> 			crops[i] =</div><div class='del'>-				v4l2_subdev_get_pad_crop(subdev, sd_state, i);</div><div class='add'>+				v4l2_subdev_state_get_crop(sd_state, i);</div><div class='ctx'> 	if (comps)</div><div class='del'>-		*comps = v4l2_subdev_get_pad_compose(subdev, sd_state,</div><div class='del'>-						     ssd-&gt;sink_pad);</div><div class='add'>+		*comps = v4l2_subdev_state_get_compose(sd_state,</div><div class='add'>+						       ssd-&gt;sink_pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Changes require propagation only on sink pad. */</div><div class='hunk'>@@ -2097,7 +2109,7 @@ static void ccs_propagate(struct v4l2_subdev *subdev,</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='ctx'> 		*crops[CCS_PAD_SRC] = *comp;</div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(subdev, sd_state, CCS_PAD_SRC);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, CCS_PAD_SRC);</div><div class='ctx'> 		fmt-&gt;width = comp-&gt;width;</div><div class='ctx'> 		fmt-&gt;height = comp-&gt;height;</div><div class='ctx'> 		if (which == V4L2_SUBDEV_FORMAT_ACTIVE &amp;&amp; ssd == sensor-&gt;src)</div><div class='hunk'>@@ -2507,7 +2519,7 @@ static int ccs_set_crop(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;pad == ssd-&gt;sink_pad) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *mfmt =</div><div class='del'>-			v4l2_subdev_get_pad_format(subdev, sd_state, sel-&gt;pad);</div><div class='add'>+			v4l2_subdev_state_get_format(sd_state, sel-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 		src_size.width = mfmt-&gt;width;</div><div class='ctx'> 		src_size.height = mfmt-&gt;height;</div><div class='hunk'>@@ -2567,8 +2579,8 @@ static int ccs_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			ccs_get_native_size(ssd, &amp;sel-&gt;r);</div><div class='ctx'> 		} else if (sel-&gt;pad == ssd-&gt;sink_pad) {</div><div class='ctx'> 			struct v4l2_mbus_framefmt *sink_fmt =</div><div class='del'>-				v4l2_subdev_get_pad_format(subdev, sd_state,</div><div class='del'>-							   ssd-&gt;sink_pad);</div><div class='add'>+				v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							     ssd-&gt;sink_pad);</div><div class='ctx'> 			sel-&gt;r.top = sel-&gt;r.left = 0;</div><div class='ctx'> 			sel-&gt;r.width = sink_fmt-&gt;width;</div><div class='ctx'> 			sel-&gt;r.height = sink_fmt-&gt;height;</div><div class='hunk'>@@ -2714,66 +2726,54 @@ static int ccs_identify_module(struct ccs_sensor *sensor)</div><div class='ctx'> 	rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,</div><div class='ctx'> 			&amp;minfo-&gt;mipi_manufacturer_id);</div><div class='ctx'> 	if (!rval &amp;&amp; !minfo-&gt;mipi_manufacturer_id)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   SMIAPP_REG_U8_MANUFACTURER_ID,</div><div class='del'>-					   &amp;minfo-&gt;smia_manufacturer_id);</div><div class='add'>+		rval = ccs_read_addr(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,</div><div class='add'>+				     &amp;minfo-&gt;smia_manufacturer_id);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,</div><div class='del'>-					   &amp;minfo-&gt;model_id);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_MODEL_ID, &amp;minfo-&gt;model_id);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_MODULE_REVISION_NUMBER_MAJOR,</div><div class='del'>-					   &amp;rev);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_REVISION_NUMBER_MAJOR, &amp;rev);</div><div class='ctx'> 	if (!rval) {</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_MODULE_REVISION_NUMBER_MINOR,</div><div class='del'>-					   &amp;minfo-&gt;revision_number);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_REVISION_NUMBER_MINOR,</div><div class='add'>+				&amp;minfo-&gt;revision_number);</div><div class='ctx'> 		minfo-&gt;revision_number |= rev &lt;&lt; 8;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,</div><div class='del'>-					   &amp;minfo-&gt;module_year);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_DATE_YEAR, &amp;minfo-&gt;module_year);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,</div><div class='del'>-					   &amp;minfo-&gt;module_month);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_DATE_MONTH,</div><div class='add'>+				&amp;minfo-&gt;module_month);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,</div><div class='del'>-					   &amp;minfo-&gt;module_day);</div><div class='add'>+		rval = ccs_read(sensor, MODULE_DATE_DAY, &amp;minfo-&gt;module_day);</div><div class='ctx'> </div><div class='ctx'> 	/* Sensor info */</div><div class='ctx'> 	if (!rval)</div><div class='ctx'> 		rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,</div><div class='ctx'> 				&amp;minfo-&gt;sensor_mipi_manufacturer_id);</div><div class='ctx'> 	if (!rval &amp;&amp; !minfo-&gt;sensor_mipi_manufacturer_id)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_SENSOR_MANUFACTURER_ID,</div><div class='del'>-					   &amp;minfo-&gt;sensor_smia_manufacturer_id);</div><div class='add'>+		rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,</div><div class='add'>+				&amp;minfo-&gt;sensor_smia_manufacturer_id);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_SENSOR_MODEL_ID,</div><div class='del'>-					   &amp;minfo-&gt;sensor_model_id);</div><div class='add'>+		rval = ccs_read(sensor, SENSOR_MODEL_ID,</div><div class='add'>+				&amp;minfo-&gt;sensor_model_id);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_SENSOR_REVISION_NUMBER,</div><div class='del'>-					   &amp;minfo-&gt;sensor_revision_number);</div><div class='add'>+		rval = ccs_read(sensor, SENSOR_REVISION_NUMBER,</div><div class='add'>+				&amp;minfo-&gt;sensor_revision_number);</div><div class='ctx'> 	if (!rval &amp;&amp; !minfo-&gt;sensor_revision_number)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_SENSOR_REVISION_NUMBER_16,</div><div class='del'>-					   &amp;minfo-&gt;sensor_revision_number);</div><div class='add'>+		rval = ccs_read(sensor, SENSOR_REVISION_NUMBER_16,</div><div class='add'>+				&amp;minfo-&gt;sensor_revision_number);</div><div class='ctx'> 	if (!rval)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor,</div><div class='del'>-					   CCS_R_SENSOR_FIRMWARE_VERSION,</div><div class='del'>-					   &amp;minfo-&gt;sensor_firmware_version);</div><div class='add'>+		rval = ccs_read(sensor, SENSOR_FIRMWARE_VERSION,</div><div class='add'>+				&amp;minfo-&gt;sensor_firmware_version);</div><div class='ctx'> </div><div class='ctx'> 	/* SMIA */</div><div class='ctx'> 	if (!rval)</div><div class='ctx'> 		rval = ccs_read(sensor, MIPI_CCS_VERSION, &amp;minfo-&gt;ccs_version);</div><div class='ctx'> 	if (!rval &amp;&amp; !minfo-&gt;ccs_version)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,</div><div class='del'>-					   &amp;minfo-&gt;smia_version);</div><div class='add'>+		rval = ccs_read_addr(sensor, SMIAPP_REG_U8_SMIA_VERSION,</div><div class='add'>+				     &amp;minfo-&gt;smia_version);</div><div class='ctx'> 	if (!rval &amp;&amp; !minfo-&gt;ccs_version)</div><div class='del'>-		rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,</div><div class='del'>-					   &amp;minfo-&gt;smiapp_version);</div><div class='add'>+		rval = ccs_read_addr(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,</div><div class='add'>+				     &amp;minfo-&gt;smiapp_version);</div><div class='ctx'> </div><div class='ctx'> 	if (rval) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev, "sensor detection failed\n");</div><div class='hunk'>@@ -3004,17 +3004,17 @@ static int ccs_init_subdev(struct ccs_sensor *sensor,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ccs_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ccs_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			  struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct ccs_subdev *ssd = to_ccs_subdev(sd);</div><div class='ctx'> 	struct ccs_sensor *sensor = ssd-&gt;sensor;</div><div class='ctx'> 	unsigned int pad = ssd == sensor-&gt;pixel_array ?</div><div class='ctx'> 		CCS_PA_PAD_SRC : CCS_PAD_SINK;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt =</div><div class='del'>-		v4l2_subdev_get_pad_format(sd, sd_state, pad);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	struct v4l2_rect *crop =</div><div class='del'>-		v4l2_subdev_get_pad_crop(sd, sd_state, pad);</div><div class='add'>+		v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	bool is_active = !sd-&gt;active_state || sd-&gt;active_state == sd_state;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='hunk'>@@ -3034,7 +3034,7 @@ static int ccs_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, CCS_PAD_SRC);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, CCS_PAD_SRC);</div><div class='ctx'> 	fmt-&gt;code = ssd == sensor-&gt;src ?</div><div class='ctx'> 		sensor-&gt;csi_format-&gt;code : sensor-&gt;internal_csi_format-&gt;code;</div><div class='ctx'> 	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='hunk'>@@ -3053,7 +3053,6 @@ static const struct v4l2_subdev_video_ops ccs_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ccs_pad_ops = {</div><div class='del'>-	.init_cfg = ccs_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ccs_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = ccs_get_format,</div><div class='ctx'> 	.set_fmt = ccs_set_format,</div><div class='hunk'>@@ -3077,6 +3076,7 @@ static const struct media_entity_operations ccs_entity_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {</div><div class='add'>+	.init_state = ccs_init_state,</div><div class='ctx'> 	.registered = ccs_registered,</div><div class='ctx'> 	.unregistered = ccs_unregistered,</div><div class='ctx'> };</div><div class='hunk'>@@ -3307,6 +3307,13 @@ static int ccs_probe(struct i2c_client *client)</div><div class='ctx'> 	if (IS_ERR(sensor-&gt;xshutdown))</div><div class='ctx'> 		return PTR_ERR(sensor-&gt;xshutdown);</div><div class='ctx'> </div><div class='add'>+	sensor-&gt;regmap = devm_cci_regmap_init_i2c(client, 16);</div><div class='add'>+	if (IS_ERR(sensor-&gt;regmap)) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "can't initialise CCI (%ld)\n",</div><div class='add'>+			PTR_ERR(sensor-&gt;regmap));</div><div class='add'>+		return PTR_ERR(sensor-&gt;regmap);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rval = ccs_power_on(&amp;client-&gt;dev);</div><div class='ctx'> 	if (rval &lt; 0)</div><div class='ctx'> 		return rval;</div><div class='hunk'>@@ -3532,6 +3539,7 @@ static int ccs_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	sensor-&gt;streaming = false;</div><div class='ctx'> 	sensor-&gt;dev_init_done = true;</div><div class='add'>+	sensor-&gt;handler_setup_needed = true;</div><div class='ctx'> </div><div class='ctx'> 	rval = ccs_write_msr_regs(sensor);</div><div class='ctx'> 	if (rval)</div><div class='hunk'>@@ -3636,12 +3644,16 @@ static int ccs_module_init(void)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i, l;</div><div class='ctx'> </div><div class='add'>+	CCS_BUILD_BUG;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0, l = 0; ccs_limits[i].size &amp;&amp; l &lt; CCS_L_LAST; i++) {</div><div class='ctx'> 		if (!(ccs_limits[i].flags &amp; CCS_L_FL_SAME_REG)) {</div><div class='ctx'> 			ccs_limit_offsets[l + 1].lim =</div><div class='ctx'> 				ALIGN(ccs_limit_offsets[l].lim +</div><div class='ctx'> 				      ccs_limits[i].size,</div><div class='del'>-				      ccs_reg_width(ccs_limits[i + 1].reg));</div><div class='add'>+				      ccs_limits[i + 1].reg ?</div><div class='add'>+				      CCI_REG_WIDTH_BYTES(ccs_limits[i + 1].reg) :</div><div class='add'>+				      1U);</div><div class='ctx'> 			ccs_limit_offsets[l].info = i;</div><div class='ctx'> 			l++;</div><div class='ctx'> 		} else {</div><div class='head'>diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c<br/>index 25993445f4fe..ed79075505e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-reg-access.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/ccs-reg-access.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-reg-access.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-reg-access.c</a></div><div class='hunk'>@@ -62,87 +62,6 @@ static u32 float_to_u32_mul_1000000(struct i2c_client *client, u32 phloat)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Read a 8/16/32-bit i2c register.  The value is returned in 'val'.</div><div class='del'>- * Returns zero if successful, or non-zero otherwise.</div><div class='del'>- */</div><div class='del'>-static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,</div><div class='del'>-			     u32 *val)</div><div class='del'>-{</div><div class='del'>-	struct i2c_client *client = v4l2_get_subdevdata(&amp;sensor-&gt;src-&gt;sd);</div><div class='del'>-	struct i2c_msg msg;</div><div class='del'>-	unsigned char data_buf[sizeof(u32)] = { 0 };</div><div class='del'>-	unsigned char offset_buf[sizeof(u16)];</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	if (len &gt; sizeof(data_buf))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	msg.addr = client-&gt;addr;</div><div class='del'>-	msg.flags = 0;</div><div class='del'>-	msg.len = sizeof(offset_buf);</div><div class='del'>-	msg.buf = offset_buf;</div><div class='del'>-	put_unaligned_be16(reg, offset_buf);</div><div class='del'>-</div><div class='del'>-	r = i2c_transfer(client-&gt;adapter, &amp;msg, 1);</div><div class='del'>-	if (r != 1) {</div><div class='del'>-		if (r &gt;= 0)</div><div class='del'>-			r = -EBUSY;</div><div class='del'>-		goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	msg.len = len;</div><div class='del'>-	msg.flags = I2C_M_RD;</div><div class='del'>-	msg.buf = &amp;data_buf[sizeof(data_buf) - len];</div><div class='del'>-</div><div class='del'>-	r = i2c_transfer(client-&gt;adapter, &amp;msg, 1);</div><div class='del'>-	if (r != 1) {</div><div class='del'>-		if (r &gt;= 0)</div><div class='del'>-			r = -EBUSY;</div><div class='del'>-		goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	*val = get_unaligned_be32(data_buf);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err:</div><div class='del'>-	dev_err(&amp;client-&gt;dev, "read from offset 0x%x error %d\n", reg, r);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Read a register using 8-bit access only. */</div><div class='del'>-static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,</div><div class='del'>-				   u16 len, u32 *val)</div><div class='del'>-{</div><div class='del'>-	unsigned int i;</div><div class='del'>-	int rval;</div><div class='del'>-</div><div class='del'>-	*val = 0;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; len; i++) {</div><div class='del'>-		u32 val8;</div><div class='del'>-</div><div class='del'>-		rval = ____ccs_read_addr(sensor, reg + i, 1, &amp;val8);</div><div class='del'>-		if (rval &lt; 0)</div><div class='del'>-			return rval;</div><div class='del'>-		*val |= val8 &lt;&lt; ((len - i - 1) &lt;&lt; 3);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-unsigned int ccs_reg_width(u32 reg)</div><div class='del'>-{</div><div class='del'>-	if (reg &amp; CCS_FL_16BIT)</div><div class='del'>-		return sizeof(u16);</div><div class='del'>-	if (reg &amp; CCS_FL_32BIT)</div><div class='del'>-		return sizeof(u32);</div><div class='del'>-</div><div class='del'>-	return sizeof(u8);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val)</div><div class='ctx'> {</div><div class='ctx'> 	if (val &gt;&gt; 10 &gt; U32_MAX / 15625) {</div><div class='hunk'>@@ -178,29 +97,22 @@ u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)</div><div class='ctx'> static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,</div><div class='ctx'> 			   bool only8, bool conv)</div><div class='ctx'> {</div><div class='del'>-	unsigned int len = ccs_reg_width(reg);</div><div class='add'>+	u64 __val;</div><div class='ctx'> 	int rval;</div><div class='ctx'> </div><div class='del'>-	if (!only8)</div><div class='del'>-		rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);</div><div class='del'>-	else</div><div class='del'>-		rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,</div><div class='del'>-					       val);</div><div class='add'>+	rval = cci_read(sensor-&gt;regmap, reg, &amp;__val, NULL);</div><div class='ctx'> 	if (rval &lt; 0)</div><div class='ctx'> 		return rval;</div><div class='ctx'> </div><div class='del'>-	if (!conv)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	*val = ccs_reg_conv(sensor, reg, *val);</div><div class='add'>+	*val = conv ? ccs_reg_conv(sensor, reg, __val) : __val;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,</div><div class='del'>-			   u32 reg, u32 *val)</div><div class='add'>+static int __ccs_static_data_read_ro_reg(struct ccs_reg *regs, size_t num_regs,</div><div class='add'>+					 u32 reg, u32 *val)</div><div class='ctx'> {</div><div class='del'>-	unsigned int width = ccs_reg_width(reg);</div><div class='add'>+	unsigned int width = CCI_REG_WIDTH_BYTES(reg);</div><div class='ctx'> 	size_t i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_regs; i++, regs++) {</div><div class='hunk'>@@ -235,16 +147,17 @@ static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,</div><div class='ctx'> 	return -ENOENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val)</div><div class='add'>+static int</div><div class='add'>+ccs_static_data_read_ro_reg(struct ccs_sensor *sensor, u32 reg, u32 *val)</div><div class='ctx'> {</div><div class='del'>-	if (!__ccs_read_data(sensor-&gt;sdata.sensor_read_only_regs,</div><div class='del'>-			     sensor-&gt;sdata.num_sensor_read_only_regs,</div><div class='del'>-			     reg, val))</div><div class='add'>+	if (!__ccs_static_data_read_ro_reg(sensor-&gt;sdata.sensor_read_only_regs,</div><div class='add'>+					   sensor-&gt;sdata.num_sensor_read_only_regs,</div><div class='add'>+					   reg, val))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return __ccs_read_data(sensor-&gt;mdata.module_read_only_regs,</div><div class='del'>-			       sensor-&gt;mdata.num_module_read_only_regs,</div><div class='del'>-			       reg, val);</div><div class='add'>+	return __ccs_static_data_read_ro_reg(sensor-&gt;mdata.module_read_only_regs,</div><div class='add'>+					     sensor-&gt;mdata.num_module_read_only_regs,</div><div class='add'>+					     reg, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,</div><div class='hunk'>@@ -253,7 +166,7 @@ static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,</div><div class='ctx'> 	int rval;</div><div class='ctx'> </div><div class='ctx'> 	if (data) {</div><div class='del'>-		rval = ccs_read_data(sensor, reg, val);</div><div class='add'>+		rval = ccs_static_data_read_ro_reg(sensor, reg, val);</div><div class='ctx'> 		if (!rval)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -291,71 +204,13 @@ int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)</div><div class='ctx'> 	return ccs_read_addr_raw(sensor, reg, val, false, true, false, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)</div><div class='del'>-{</div><div class='del'>-	unsigned int retries;</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	for (retries = 0; retries &lt; 10; retries++) {</div><div class='del'>-		/*</div><div class='del'>-		 * Due to unknown reason sensor stops responding. This</div><div class='del'>-		 * loop is a temporaty solution until the root cause</div><div class='del'>-		 * is found.</div><div class='del'>-		 */</div><div class='del'>-		r = i2c_transfer(client-&gt;adapter, msg, 1);</div><div class='del'>-		if (r != 1) {</div><div class='del'>-			usleep_range(1000, 2000);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (retries)</div><div class='del'>-			dev_err(&amp;client-&gt;dev,</div><div class='del'>-				"sensor i2c stall encountered. retries: %d\n",</div><div class='del'>-				retries);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)</div><div class='del'>-{</div><div class='del'>-	struct i2c_client *client = v4l2_get_subdevdata(&amp;sensor-&gt;src-&gt;sd);</div><div class='del'>-	struct i2c_msg msg;</div><div class='del'>-	unsigned char data[6];</div><div class='del'>-	unsigned int len = ccs_reg_width(reg);</div><div class='del'>-	int r;</div><div class='del'>-</div><div class='del'>-	if (len &gt; sizeof(data) - 2)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	msg.addr = client-&gt;addr;</div><div class='del'>-	msg.flags = 0; /* Write */</div><div class='del'>-	msg.len = 2 + len;</div><div class='del'>-	msg.buf = data;</div><div class='del'>-</div><div class='del'>-	put_unaligned_be16(CCS_REG_ADDR(reg), data);</div><div class='del'>-	put_unaligned_be32(val &lt;&lt; (8 * (sizeof(val) - len)), data + 2);</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "writing reg 0x%4.4x value 0x%*.*x (%u)\n",</div><div class='del'>-		CCS_REG_ADDR(reg), ccs_reg_width(reg) &lt;&lt; 1,</div><div class='del'>-		ccs_reg_width(reg) &lt;&lt; 1, val, val);</div><div class='del'>-</div><div class='del'>-	r = ccs_write_retry(client, &amp;msg);</div><div class='del'>-	if (r)</div><div class='del'>-		dev_err(&amp;client-&gt;dev,</div><div class='del'>-			"wrote 0x%x to offset 0x%x error %d\n", val,</div><div class='del'>-			CCS_REG_ADDR(reg), r);</div><div class='del'>-</div><div class='del'>-	return r;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  * Write to a 8/16-bit register.</div><div class='ctx'>  * Returns zero if successful, or non-zero otherwise.</div><div class='ctx'>  */</div><div class='ctx'> int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)</div><div class='ctx'> {</div><div class='add'>+	unsigned int retries = 10;</div><div class='ctx'> 	int rval;</div><div class='ctx'> </div><div class='ctx'> 	rval = ccs_call_quirk(sensor, reg_access, true, &amp;reg, &amp;val);</div><div class='hunk'>@@ -364,7 +219,13 @@ int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)</div><div class='ctx'> 	if (rval &lt; 0)</div><div class='ctx'> 		return rval;</div><div class='ctx'> </div><div class='del'>-	return ccs_write_addr_no_quirk(sensor, reg, val);</div><div class='add'>+	rval = 0;</div><div class='add'>+	do {</div><div class='add'>+		if (cci_write(sensor-&gt;regmap, reg, val, &amp;rval))</div><div class='add'>+			fsleep(1000);</div><div class='add'>+	} while (rval &amp;&amp; --retries);</div><div class='add'>+</div><div class='add'>+	return rval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define MAX_WRITE_LEN	32U</div><div class='hunk'>@@ -373,40 +234,38 @@ int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,</div><div class='ctx'> 			size_t num_regs)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(&amp;sensor-&gt;src-&gt;sd);</div><div class='del'>-	unsigned char buf[2 + MAX_WRITE_LEN];</div><div class='del'>-	struct i2c_msg msg = {</div><div class='del'>-		.addr = client-&gt;addr,</div><div class='del'>-		.buf = buf,</div><div class='del'>-	};</div><div class='ctx'> 	size_t i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_regs; i++, regs++) {</div><div class='ctx'> 		unsigned char *regdata = regs-&gt;value;</div><div class='ctx'> 		unsigned int j;</div><div class='add'>+		int len;</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; regs-&gt;len;</div><div class='del'>-		     j += msg.len - 2, regdata += msg.len - 2) {</div><div class='add'>+		for (j = 0; j &lt; regs-&gt;len; j += len, regdata += len) {</div><div class='ctx'> 			char printbuf[(MAX_WRITE_LEN &lt;&lt; 1) +</div><div class='ctx'> 				      1 /* \0 */] = { 0 };</div><div class='add'>+			unsigned int retries = 10;</div><div class='ctx'> 			int rval;</div><div class='ctx'> </div><div class='del'>-			msg.len = min(regs-&gt;len - j, MAX_WRITE_LEN);</div><div class='add'>+			len = min(regs-&gt;len - j, MAX_WRITE_LEN);</div><div class='ctx'> </div><div class='del'>-			bin2hex(printbuf, regdata, msg.len);</div><div class='add'>+			bin2hex(printbuf, regdata, len);</div><div class='ctx'> 			dev_dbg(&amp;client-&gt;dev,</div><div class='ctx'> 				"writing msr reg 0x%4.4x value 0x%s\n",</div><div class='ctx'> 				regs-&gt;addr + j, printbuf);</div><div class='ctx'> </div><div class='del'>-			put_unaligned_be16(regs-&gt;addr + j, buf);</div><div class='del'>-			memcpy(buf + 2, regdata, msg.len);</div><div class='del'>-</div><div class='del'>-			msg.len += 2;</div><div class='add'>+			do {</div><div class='add'>+				rval = regmap_bulk_write(sensor-&gt;regmap,</div><div class='add'>+							 regs-&gt;addr + j,</div><div class='add'>+							 regdata, len);</div><div class='add'>+				if (rval)</div><div class='add'>+					fsleep(1000);</div><div class='add'>+			} while (rval &amp;&amp; --retries);</div><div class='ctx'> </div><div class='del'>-			rval = ccs_write_retry(client, &amp;msg);</div><div class='ctx'> 			if (rval) {</div><div class='ctx'> 				dev_err(&amp;client-&gt;dev,</div><div class='ctx'> 					"error writing %u octets to address 0x%4.4x\n",</div><div class='del'>-					msg.len, regs-&gt;addr + j);</div><div class='add'>+					len, regs-&gt;addr + j);</div><div class='ctx'> 				return rval;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/media/i2c/ccs/ccs-regs.h b/drivers/media/i2c/ccs/ccs-regs.h<br/>index 6ce84c5ecf20..7b5dbc86e4cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/ccs-regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs-regs.h</a></div><div class='hunk'>@@ -10,59 +10,59 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/bits.h&gt;</div><div class='ctx'> </div><div class='del'>-#define CCS_FL_BASE		16</div><div class='del'>-#define CCS_FL_16BIT		BIT(CCS_FL_BASE)</div><div class='del'>-#define CCS_FL_32BIT		BIT(CCS_FL_BASE + 1)</div><div class='del'>-#define CCS_FL_FLOAT_IREAL	BIT(CCS_FL_BASE + 2)</div><div class='del'>-#define CCS_FL_IREAL		BIT(CCS_FL_BASE + 3)</div><div class='del'>-#define CCS_R_ADDR(r)		((r) &amp; 0xffff)</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='ctx'> </div><div class='del'>-#define CCS_R_MODULE_MODEL_ID					(0x0000 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MODULE_REVISION_NUMBER_MAJOR			0x0002</div><div class='del'>-#define CCS_R_FRAME_COUNT					0x0005</div><div class='del'>-#define CCS_R_PIXEL_ORDER					0x0006</div><div class='add'>+#define CCS_FL_BASE		CCI_REG_PRIVATE_SHIFT</div><div class='add'>+#define CCS_FL_FLOAT_IREAL	BIT(CCS_FL_BASE)</div><div class='add'>+#define CCS_FL_IREAL		BIT(CCS_FL_BASE + 1)</div><div class='add'>+#define CCS_BUILD_BUG \</div><div class='add'>+	BUILD_BUG_ON(~CCI_REG_PRIVATE_MASK &amp; (BIT(CCS_FL_BASE) | BIT(CCS_FL_BASE + 1)))</div><div class='add'>+#define CCS_R_MODULE_MODEL_ID					CCI_REG16(0x0000)</div><div class='add'>+#define CCS_R_MODULE_REVISION_NUMBER_MAJOR			CCI_REG8(0x0002)</div><div class='add'>+#define CCS_R_FRAME_COUNT					CCI_REG8(0x0005)</div><div class='add'>+#define CCS_R_PIXEL_ORDER					CCI_REG8(0x0006)</div><div class='ctx'> #define CCS_PIXEL_ORDER_GRBG					0U</div><div class='ctx'> #define CCS_PIXEL_ORDER_RGGB					1U</div><div class='ctx'> #define CCS_PIXEL_ORDER_BGGR					2U</div><div class='ctx'> #define CCS_PIXEL_ORDER_GBRG					3U</div><div class='del'>-#define CCS_R_MIPI_CCS_VERSION					0x0007</div><div class='add'>+#define CCS_R_MIPI_CCS_VERSION					CCI_REG8(0x0007)</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_V1_0				0x10</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_V1_1				0x11</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT			4U</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_MAJOR_MASK				0xf0</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_MINOR_SHIFT			0U</div><div class='ctx'> #define CCS_MIPI_CCS_VERSION_MINOR_MASK				0xf</div><div class='del'>-#define CCS_R_DATA_PEDESTAL					(0x0008 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MODULE_MANUFACTURER_ID				(0x000e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MODULE_REVISION_NUMBER_MINOR			0x0010</div><div class='del'>-#define CCS_R_MODULE_DATE_YEAR					0x0012</div><div class='del'>-#define CCS_R_MODULE_DATE_MONTH					0x0013</div><div class='del'>-#define CCS_R_MODULE_DATE_DAY					0x0014</div><div class='del'>-#define CCS_R_MODULE_DATE_PHASE					0x0015</div><div class='add'>+#define CCS_R_DATA_PEDESTAL					CCI_REG16(0x0008)</div><div class='add'>+#define CCS_R_MODULE_MANUFACTURER_ID				CCI_REG16(0x000e)</div><div class='add'>+#define CCS_R_MODULE_REVISION_NUMBER_MINOR			CCI_REG8(0x0010)</div><div class='add'>+#define CCS_R_MODULE_DATE_YEAR					CCI_REG8(0x0012)</div><div class='add'>+#define CCS_R_MODULE_DATE_MONTH					CCI_REG8(0x0013)</div><div class='add'>+#define CCS_R_MODULE_DATE_DAY					CCI_REG8(0x0014)</div><div class='add'>+#define CCS_R_MODULE_DATE_PHASE					CCI_REG8(0x0015)</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_SHIFT				0U</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_MASK				0x7</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_TS				0U</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_ES				1U</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_CS				2U</div><div class='ctx'> #define CCS_MODULE_DATE_PHASE_MP				3U</div><div class='del'>-#define CCS_R_SENSOR_MODEL_ID					(0x0016 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SENSOR_REVISION_NUMBER				0x0018</div><div class='del'>-#define CCS_R_SENSOR_FIRMWARE_VERSION				0x001a</div><div class='del'>-#define CCS_R_SERIAL_NUMBER					(0x001c | CCS_FL_32BIT)</div><div class='del'>-#define CCS_R_SENSOR_MANUFACTURER_ID				(0x0020 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SENSOR_REVISION_NUMBER_16				(0x0022 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FRAME_FORMAT_MODEL_TYPE				0x0040</div><div class='add'>+#define CCS_R_SENSOR_MODEL_ID					CCI_REG16(0x0016)</div><div class='add'>+#define CCS_R_SENSOR_REVISION_NUMBER				CCI_REG8(0x0018)</div><div class='add'>+#define CCS_R_SENSOR_FIRMWARE_VERSION				CCI_REG8(0x001a)</div><div class='add'>+#define CCS_R_SERIAL_NUMBER					CCI_REG32(0x001c)</div><div class='add'>+#define CCS_R_SENSOR_MANUFACTURER_ID				CCI_REG16(0x0020)</div><div class='add'>+#define CCS_R_SENSOR_REVISION_NUMBER_16				CCI_REG16(0x0022)</div><div class='add'>+#define CCS_R_FRAME_FORMAT_MODEL_TYPE				CCI_REG8(0x0040)</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE			1U</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE			2U</div><div class='del'>-#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE			0x0041</div><div class='add'>+#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE			CCI_REG8(0x0041)</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT		0U</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK		0xf</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT		4U</div><div class='ctx'> #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK		0xf0</div><div class='del'>-#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n)			((0x0042 | CCS_FL_16BIT) + (n) * 2)</div><div class='add'>+#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n)			CCI_REG16(0x0042 + (n) * 2)</div><div class='ctx'> #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N			0U</div><div class='ctx'> #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N			14U</div><div class='del'>-#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n)			((0x0060 | CCS_FL_32BIT) + (n) * 4)</div><div class='add'>+#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n)			CCI_REG32(0x0060 + (n) * 4)</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT		0U</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK			0xfff</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT			12U</div><div class='hunk'>@@ -97,91 +97,91 @@</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4	12U</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5	13U</div><div class='ctx'> #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6	14U</div><div class='del'>-#define CCS_R_ANALOG_GAIN_CAPABILITY				(0x0080 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_CAPABILITY				CCI_REG16(0x0080)</div><div class='ctx'> #define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL			0U</div><div class='ctx'> #define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL		2U</div><div class='del'>-#define CCS_R_ANALOG_GAIN_CODE_MIN				(0x0084 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_CODE_MAX				(0x0086 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_CODE_STEP				(0x0088 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_TYPE					(0x008a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_M0					(0x008c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_C0					(0x008e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_M1					(0x0090 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_C1					(0x0092 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_LINEAR_GAIN_MIN				(0x0094 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_LINEAR_GAIN_MAX				(0x0096 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE			(0x0098 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN			(0x009a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX			(0x009c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE			(0x009e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DATA_FORMAT_MODEL_TYPE				0x00c0</div><div class='add'>+#define CCS_R_ANALOG_GAIN_CODE_MIN				CCI_REG16(0x0084)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_CODE_MAX				CCI_REG16(0x0086)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_CODE_STEP				CCI_REG16(0x0088)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_TYPE					CCI_REG16(0x008a)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_M0					CCI_REG16(0x008c)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_C0					CCI_REG16(0x008e)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_M1					CCI_REG16(0x0090)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_C1					CCI_REG16(0x0092)</div><div class='add'>+#define CCS_R_ANALOG_LINEAR_GAIN_MIN				CCI_REG16(0x0094)</div><div class='add'>+#define CCS_R_ANALOG_LINEAR_GAIN_MAX				CCI_REG16(0x0096)</div><div class='add'>+#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE			CCI_REG16(0x0098)</div><div class='add'>+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN			CCI_REG16(0x009a)</div><div class='add'>+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX			CCI_REG16(0x009c)</div><div class='add'>+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE			CCI_REG16(0x009e)</div><div class='add'>+#define CCS_R_DATA_FORMAT_MODEL_TYPE				CCI_REG8(0x00c0)</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL			1U</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED			2U</div><div class='del'>-#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE				0x00c1</div><div class='add'>+#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE				CCI_REG8(0x00c1)</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT		0U</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK			0xf</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT		4U</div><div class='ctx'> #define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK		0xf0</div><div class='del'>-#define CCS_R_DATA_FORMAT_DESCRIPTOR(n)				((0x00c2 | CCS_FL_16BIT) + (n) * 2)</div><div class='add'>+#define CCS_R_DATA_FORMAT_DESCRIPTOR(n)				CCI_REG16(0x00c2 + (n) * 2)</div><div class='ctx'> #define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N			0U</div><div class='ctx'> #define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N			15U</div><div class='ctx'> #define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT		0U</div><div class='ctx'> #define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK		0xff</div><div class='ctx'> #define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT		8U</div><div class='ctx'> #define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK		0xff00</div><div class='del'>-#define CCS_R_MODE_SELECT					0x0100</div><div class='add'>+#define CCS_R_MODE_SELECT					CCI_REG8(0x0100)</div><div class='ctx'> #define CCS_MODE_SELECT_SOFTWARE_STANDBY			0U</div><div class='ctx'> #define CCS_MODE_SELECT_STREAMING				1U</div><div class='del'>-#define CCS_R_IMAGE_ORIENTATION					0x0101</div><div class='add'>+#define CCS_R_IMAGE_ORIENTATION					CCI_REG8(0x0101)</div><div class='ctx'> #define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR			BIT(0)</div><div class='ctx'> #define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP			BIT(1)</div><div class='del'>-#define CCS_R_SOFTWARE_RESET					0x0103</div><div class='add'>+#define CCS_R_SOFTWARE_RESET					CCI_REG8(0x0103)</div><div class='ctx'> #define CCS_SOFTWARE_RESET_OFF					0U</div><div class='ctx'> #define CCS_SOFTWARE_RESET_ON					1U</div><div class='del'>-#define CCS_R_GROUPED_PARAMETER_HOLD				0x0104</div><div class='del'>-#define CCS_R_MASK_CORRUPTED_FRAMES				0x0105</div><div class='add'>+#define CCS_R_GROUPED_PARAMETER_HOLD				CCI_REG8(0x0104)</div><div class='add'>+#define CCS_R_MASK_CORRUPTED_FRAMES				CCI_REG8(0x0105)</div><div class='ctx'> #define CCS_MASK_CORRUPTED_FRAMES_ALLOW				0U</div><div class='ctx'> #define CCS_MASK_CORRUPTED_FRAMES_MASK				1U</div><div class='del'>-#define CCS_R_FAST_STANDBY_CTRL					0x0106</div><div class='add'>+#define CCS_R_FAST_STANDBY_CTRL					CCI_REG8(0x0106)</div><div class='ctx'> #define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES			0U</div><div class='ctx'> #define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION			1U</div><div class='del'>-#define CCS_R_CCI_ADDRESS_CTRL					0x0107</div><div class='del'>-#define CCS_R_2ND_CCI_IF_CTRL					0x0108</div><div class='add'>+#define CCS_R_CCI_ADDRESS_CTRL					CCI_REG8(0x0107)</div><div class='add'>+#define CCS_R_2ND_CCI_IF_CTRL					CCI_REG8(0x0108)</div><div class='ctx'> #define CCS_2ND_CCI_IF_CTRL_ENABLE				BIT(0)</div><div class='ctx'> #define CCS_2ND_CCI_IF_CTRL_ACK					BIT(1)</div><div class='del'>-#define CCS_R_2ND_CCI_ADDRESS_CTRL				0x0109</div><div class='del'>-#define CCS_R_CSI_CHANNEL_IDENTIFIER				0x0110</div><div class='del'>-#define CCS_R_CSI_SIGNALING_MODE				0x0111</div><div class='add'>+#define CCS_R_2ND_CCI_ADDRESS_CTRL				CCI_REG8(0x0109)</div><div class='add'>+#define CCS_R_CSI_CHANNEL_IDENTIFIER				CCI_REG8(0x0110)</div><div class='add'>+#define CCS_R_CSI_SIGNALING_MODE				CCI_REG8(0x0111)</div><div class='ctx'> #define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY			2U</div><div class='ctx'> #define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY			3U</div><div class='del'>-#define CCS_R_CSI_DATA_FORMAT					(0x0112 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_CSI_LANE_MODE					0x0114</div><div class='del'>-#define CCS_R_DPCM_FRAME_DT					0x011d</div><div class='del'>-#define CCS_R_BOTTOM_EMBEDDED_DATA_DT				0x011e</div><div class='del'>-#define CCS_R_BOTTOM_EMBEDDED_DATA_VC				0x011f</div><div class='del'>-#define CCS_R_GAIN_MODE						0x0120</div><div class='add'>+#define CCS_R_CSI_DATA_FORMAT					CCI_REG16(0x0112)</div><div class='add'>+#define CCS_R_CSI_LANE_MODE					CCI_REG8(0x0114)</div><div class='add'>+#define CCS_R_DPCM_FRAME_DT					CCI_REG8(0x011d)</div><div class='add'>+#define CCS_R_BOTTOM_EMBEDDED_DATA_DT				CCI_REG8(0x011e)</div><div class='add'>+#define CCS_R_BOTTOM_EMBEDDED_DATA_VC				CCI_REG8(0x011f)</div><div class='add'>+#define CCS_R_GAIN_MODE						CCI_REG8(0x0120)</div><div class='ctx'> #define CCS_GAIN_MODE_GLOBAL					0U</div><div class='ctx'> #define CCS_GAIN_MODE_ALTERNATE					1U</div><div class='del'>-#define CCS_R_ADC_BIT_DEPTH					0x0121</div><div class='del'>-#define CCS_R_EMB_DATA_CTRL					0x0122</div><div class='add'>+#define CCS_R_ADC_BIT_DEPTH					CCI_REG8(0x0121)</div><div class='add'>+#define CCS_R_EMB_DATA_CTRL					CCI_REG8(0x0122)</div><div class='ctx'> #define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16		BIT(0)</div><div class='ctx'> #define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20		BIT(1)</div><div class='ctx'> #define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24		BIT(2)</div><div class='del'>-#define CCS_R_GPIO_TRIG_MODE					0x0130</div><div class='del'>-#define CCS_R_EXTCLK_FREQUENCY_MHZ				(0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL))</div><div class='del'>-#define CCS_R_TEMP_SENSOR_CTRL					0x0138</div><div class='add'>+#define CCS_R_GPIO_TRIG_MODE					CCI_REG8(0x0130)</div><div class='add'>+#define CCS_R_EXTCLK_FREQUENCY_MHZ				(CCI_REG16(0x0136) | CCS_FL_IREAL)</div><div class='add'>+#define CCS_R_TEMP_SENSOR_CTRL					CCI_REG8(0x0138)</div><div class='ctx'> #define CCS_TEMP_SENSOR_CTRL_ENABLE				BIT(0)</div><div class='del'>-#define CCS_R_TEMP_SENSOR_MODE					0x0139</div><div class='del'>-#define CCS_R_TEMP_SENSOR_OUTPUT				0x013a</div><div class='del'>-#define CCS_R_FINE_INTEGRATION_TIME				(0x0200 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_COARSE_INTEGRATION_TIME				(0x0202 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_GAIN_CODE_GLOBAL				(0x0204 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL				(0x0206 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL			(0x0208 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_GAIN_GLOBAL				(0x020e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL				(0x0216 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL				(0x0218 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_HDR_MODE						0x0220</div><div class='add'>+#define CCS_R_TEMP_SENSOR_MODE					CCI_REG8(0x0139)</div><div class='add'>+#define CCS_R_TEMP_SENSOR_OUTPUT				CCI_REG8(0x013a)</div><div class='add'>+#define CCS_R_FINE_INTEGRATION_TIME				CCI_REG16(0x0200)</div><div class='add'>+#define CCS_R_COARSE_INTEGRATION_TIME				CCI_REG16(0x0202)</div><div class='add'>+#define CCS_R_ANALOG_GAIN_CODE_GLOBAL				CCI_REG16(0x0204)</div><div class='add'>+#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL				CCI_REG16(0x0206)</div><div class='add'>+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL			CCI_REG16(0x0208)</div><div class='add'>+#define CCS_R_DIGITAL_GAIN_GLOBAL				CCI_REG16(0x020e)</div><div class='add'>+#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL				CCI_REG16(0x0216)</div><div class='add'>+#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL				CCI_REG16(0x0218)</div><div class='add'>+#define CCS_R_HDR_MODE						CCI_REG8(0x0220)</div><div class='ctx'> #define CCS_HDR_MODE_ENABLED					BIT(0)</div><div class='ctx'> #define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN			BIT(1)</div><div class='ctx'> #define CCS_HDR_MODE_UPSCALING					BIT(2)</div><div class='hunk'>@@ -189,421 +189,421 @@</div><div class='ctx'> #define CCS_HDR_MODE_TIMING_MODE				BIT(4)</div><div class='ctx'> #define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT			BIT(5)</div><div class='ctx'> #define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN			BIT(6)</div><div class='del'>-#define CCS_R_HDR_RESOLUTION_REDUCTION				0x0221</div><div class='add'>+#define CCS_R_HDR_RESOLUTION_REDUCTION				CCI_REG8(0x0221)</div><div class='ctx'> #define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT			0U</div><div class='ctx'> #define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK			0xf</div><div class='ctx'> #define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT		4U</div><div class='ctx'> #define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK		0xf0</div><div class='del'>-#define CCS_R_EXPOSURE_RATIO					0x0222</div><div class='del'>-#define CCS_R_HDR_INTERNAL_BIT_DEPTH				0x0223</div><div class='del'>-#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME			(0x0224 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL			(0x0226 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL		(0x0228 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_VT_PIX_CLK_DIV					(0x0300 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_VT_SYS_CLK_DIV					(0x0302 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PRE_PLL_CLK_DIV					(0x0304 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PLL_MULTIPLIER					(0x0306 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_OP_PIX_CLK_DIV					(0x0308 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_OP_SYS_CLK_DIV					(0x030a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_OP_PRE_PLL_CLK_DIV				(0x030c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_OP_PLL_MULTIPLIER					(0x030e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PLL_MODE						0x0310</div><div class='add'>+#define CCS_R_EXPOSURE_RATIO					CCI_REG8(0x0222)</div><div class='add'>+#define CCS_R_HDR_INTERNAL_BIT_DEPTH				CCI_REG8(0x0223)</div><div class='add'>+#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME			CCI_REG16(0x0224)</div><div class='add'>+#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL			CCI_REG16(0x0226)</div><div class='add'>+#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL		CCI_REG16(0x0228)</div><div class='add'>+#define CCS_R_VT_PIX_CLK_DIV					CCI_REG16(0x0300)</div><div class='add'>+#define CCS_R_VT_SYS_CLK_DIV					CCI_REG16(0x0302)</div><div class='add'>+#define CCS_R_PRE_PLL_CLK_DIV					CCI_REG16(0x0304)</div><div class='add'>+#define CCS_R_PLL_MULTIPLIER					CCI_REG16(0x0306)</div><div class='add'>+#define CCS_R_OP_PIX_CLK_DIV					CCI_REG16(0x0308)</div><div class='add'>+#define CCS_R_OP_SYS_CLK_DIV					CCI_REG16(0x030a)</div><div class='add'>+#define CCS_R_OP_PRE_PLL_CLK_DIV				CCI_REG16(0x030c)</div><div class='add'>+#define CCS_R_OP_PLL_MULTIPLIER					CCI_REG16(0x030e)</div><div class='add'>+#define CCS_R_PLL_MODE						CCI_REG8(0x0310)</div><div class='ctx'> #define CCS_PLL_MODE_SHIFT					0U</div><div class='ctx'> #define CCS_PLL_MODE_MASK					0x1</div><div class='ctx'> #define CCS_PLL_MODE_SINGLE					0U</div><div class='ctx'> #define CCS_PLL_MODE_DUAL					1U</div><div class='del'>-#define CCS_R_OP_PIX_CLK_DIV_REV				(0x0312 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_OP_SYS_CLK_DIV_REV				(0x0314 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FRAME_LENGTH_LINES				(0x0340 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_LINE_LENGTH_PCK					(0x0342 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_ADDR_START					(0x0344 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_ADDR_START					(0x0346 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_ADDR_END					(0x0348 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_ADDR_END					(0x034a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_OUTPUT_SIZE					(0x034c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_OUTPUT_SIZE					(0x034e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FRAME_LENGTH_CTRL					0x0350</div><div class='add'>+#define CCS_R_OP_PIX_CLK_DIV_REV				CCI_REG16(0x0312)</div><div class='add'>+#define CCS_R_OP_SYS_CLK_DIV_REV				CCI_REG16(0x0314)</div><div class='add'>+#define CCS_R_FRAME_LENGTH_LINES				CCI_REG16(0x0340)</div><div class='add'>+#define CCS_R_LINE_LENGTH_PCK					CCI_REG16(0x0342)</div><div class='add'>+#define CCS_R_X_ADDR_START					CCI_REG16(0x0344)</div><div class='add'>+#define CCS_R_Y_ADDR_START					CCI_REG16(0x0346)</div><div class='add'>+#define CCS_R_X_ADDR_END					CCI_REG16(0x0348)</div><div class='add'>+#define CCS_R_Y_ADDR_END					CCI_REG16(0x034a)</div><div class='add'>+#define CCS_R_X_OUTPUT_SIZE					CCI_REG16(0x034c)</div><div class='add'>+#define CCS_R_Y_OUTPUT_SIZE					CCI_REG16(0x034e)</div><div class='add'>+#define CCS_R_FRAME_LENGTH_CTRL					CCI_REG8(0x0350)</div><div class='ctx'> #define CCS_FRAME_LENGTH_CTRL_AUTOMATIC				BIT(0)</div><div class='del'>-#define CCS_R_TIMING_MODE_CTRL					0x0352</div><div class='add'>+#define CCS_R_TIMING_MODE_CTRL					CCI_REG8(0x0352)</div><div class='ctx'> #define CCS_TIMING_MODE_CTRL_MANUAL_READOUT			BIT(0)</div><div class='ctx'> #define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE			BIT(1)</div><div class='del'>-#define CCS_R_START_READOUT_RS					0x0353</div><div class='add'>+#define CCS_R_START_READOUT_RS					CCI_REG8(0x0353)</div><div class='ctx'> #define CCS_START_READOUT_RS_MANUAL_READOUT_START		BIT(0)</div><div class='del'>-#define CCS_R_FRAME_MARGIN					(0x0354 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_EVEN_INC					(0x0380 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_ODD_INC						(0x0382 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_EVEN_INC					(0x0384 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_ODD_INC						(0x0386 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MONOCHROME_EN					0x0390</div><div class='add'>+#define CCS_R_FRAME_MARGIN					CCI_REG16(0x0354)</div><div class='add'>+#define CCS_R_X_EVEN_INC					CCI_REG16(0x0380)</div><div class='add'>+#define CCS_R_X_ODD_INC						CCI_REG16(0x0382)</div><div class='add'>+#define CCS_R_Y_EVEN_INC					CCI_REG16(0x0384)</div><div class='add'>+#define CCS_R_Y_ODD_INC						CCI_REG16(0x0386)</div><div class='add'>+#define CCS_R_MONOCHROME_EN					CCI_REG8(0x0390)</div><div class='ctx'> #define CCS_MONOCHROME_EN_ENABLED				0U</div><div class='del'>-#define CCS_R_SCALING_MODE					(0x0400 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_SCALING_MODE					CCI_REG16(0x0400)</div><div class='ctx'> #define CCS_SCALING_MODE_NO_SCALING				0U</div><div class='ctx'> #define CCS_SCALING_MODE_HORIZONTAL				1U</div><div class='del'>-#define CCS_R_SCALE_M						(0x0404 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SCALE_N						(0x0406 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_CROP_X_OFFSET				(0x0408 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_CROP_Y_OFFSET				(0x040a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH				(0x040c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT				(0x040e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_COMPRESSION_MODE					(0x0500 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_SCALE_M						CCI_REG16(0x0404)</div><div class='add'>+#define CCS_R_SCALE_N						CCI_REG16(0x0406)</div><div class='add'>+#define CCS_R_DIGITAL_CROP_X_OFFSET				CCI_REG16(0x0408)</div><div class='add'>+#define CCS_R_DIGITAL_CROP_Y_OFFSET				CCI_REG16(0x040a)</div><div class='add'>+#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH				CCI_REG16(0x040c)</div><div class='add'>+#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT				CCI_REG16(0x040e)</div><div class='add'>+#define CCS_R_COMPRESSION_MODE					CCI_REG16(0x0500)</div><div class='ctx'> #define CCS_COMPRESSION_MODE_NONE				0U</div><div class='ctx'> #define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE			1U</div><div class='del'>-#define CCS_R_TEST_PATTERN_MODE					(0x0600 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_TEST_PATTERN_MODE					CCI_REG16(0x0600)</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_NONE				0U</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_SOLID_COLOR			1U</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_COLOR_BARS			2U</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_FADE_TO_GREY			3U</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_PN9				4U</div><div class='ctx'> #define CCS_TEST_PATTERN_MODE_COLOR_TILE			5U</div><div class='del'>-#define CCS_R_TEST_DATA_RED					(0x0602 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TEST_DATA_GREENR					(0x0604 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TEST_DATA_BLUE					(0x0606 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TEST_DATA_GREENB					(0x0608 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_VALUE_STEP_SIZE_SMOOTH				0x060a</div><div class='del'>-#define CCS_R_VALUE_STEP_SIZE_QUANTISED				0x060b</div><div class='del'>-#define CCS_R_TCLK_POST						0x0800</div><div class='del'>-#define CCS_R_THS_PREPARE					0x0801</div><div class='del'>-#define CCS_R_THS_ZERO_MIN					0x0802</div><div class='del'>-#define CCS_R_THS_TRAIL						0x0803</div><div class='del'>-#define CCS_R_TCLK_TRAIL_MIN					0x0804</div><div class='del'>-#define CCS_R_TCLK_PREPARE					0x0805</div><div class='del'>-#define CCS_R_TCLK_ZERO						0x0806</div><div class='del'>-#define CCS_R_TLPX						0x0807</div><div class='del'>-#define CCS_R_PHY_CTRL						0x0808</div><div class='add'>+#define CCS_R_TEST_DATA_RED					CCI_REG16(0x0602)</div><div class='add'>+#define CCS_R_TEST_DATA_GREENR					CCI_REG16(0x0604)</div><div class='add'>+#define CCS_R_TEST_DATA_BLUE					CCI_REG16(0x0606)</div><div class='add'>+#define CCS_R_TEST_DATA_GREENB					CCI_REG16(0x0608)</div><div class='add'>+#define CCS_R_VALUE_STEP_SIZE_SMOOTH				CCI_REG8(0x060a)</div><div class='add'>+#define CCS_R_VALUE_STEP_SIZE_QUANTISED				CCI_REG8(0x060b)</div><div class='add'>+#define CCS_R_TCLK_POST						CCI_REG8(0x0800)</div><div class='add'>+#define CCS_R_THS_PREPARE					CCI_REG8(0x0801)</div><div class='add'>+#define CCS_R_THS_ZERO_MIN					CCI_REG8(0x0802)</div><div class='add'>+#define CCS_R_THS_TRAIL						CCI_REG8(0x0803)</div><div class='add'>+#define CCS_R_TCLK_TRAIL_MIN					CCI_REG8(0x0804)</div><div class='add'>+#define CCS_R_TCLK_PREPARE					CCI_REG8(0x0805)</div><div class='add'>+#define CCS_R_TCLK_ZERO						CCI_REG8(0x0806)</div><div class='add'>+#define CCS_R_TLPX						CCI_REG8(0x0807)</div><div class='add'>+#define CCS_R_PHY_CTRL						CCI_REG8(0x0808)</div><div class='ctx'> #define CCS_PHY_CTRL_AUTO					0U</div><div class='ctx'> #define CCS_PHY_CTRL_UI						1U</div><div class='ctx'> #define CCS_PHY_CTRL_MANUAL					2U</div><div class='del'>-#define CCS_R_TCLK_POST_EX					(0x080a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_THS_PREPARE_EX					(0x080c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_THS_ZERO_MIN_EX					(0x080e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_THS_TRAIL_EX					(0x0810 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TCLK_TRAIL_MIN_EX					(0x0812 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TCLK_PREPARE_EX					(0x0814 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TCLK_ZERO_EX					(0x0816 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TLPX_EX						(0x0818 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_REQUESTED_LINK_RATE				(0x0820 | CCS_FL_32BIT)</div><div class='del'>-#define CCS_R_DPHY_EQUALIZATION_MODE				0x0824</div><div class='add'>+#define CCS_R_TCLK_POST_EX					CCI_REG16(0x080a)</div><div class='add'>+#define CCS_R_THS_PREPARE_EX					CCI_REG16(0x080c)</div><div class='add'>+#define CCS_R_THS_ZERO_MIN_EX					CCI_REG16(0x080e)</div><div class='add'>+#define CCS_R_THS_TRAIL_EX					CCI_REG16(0x0810)</div><div class='add'>+#define CCS_R_TCLK_TRAIL_MIN_EX					CCI_REG16(0x0812)</div><div class='add'>+#define CCS_R_TCLK_PREPARE_EX					CCI_REG16(0x0814)</div><div class='add'>+#define CCS_R_TCLK_ZERO_EX					CCI_REG16(0x0816)</div><div class='add'>+#define CCS_R_TLPX_EX						CCI_REG16(0x0818)</div><div class='add'>+#define CCS_R_REQUESTED_LINK_RATE				CCI_REG32(0x0820)</div><div class='add'>+#define CCS_R_DPHY_EQUALIZATION_MODE				CCI_REG8(0x0824)</div><div class='ctx'> #define CCS_DPHY_EQUALIZATION_MODE_EQ2				BIT(0)</div><div class='del'>-#define CCS_R_PHY_EQUALIZATION_CTRL				0x0825</div><div class='add'>+#define CCS_R_PHY_EQUALIZATION_CTRL				CCI_REG8(0x0825)</div><div class='ctx'> #define CCS_PHY_EQUALIZATION_CTRL_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_DPHY_PREAMBLE_CTRL				0x0826</div><div class='add'>+#define CCS_R_DPHY_PREAMBLE_CTRL				CCI_REG8(0x0826)</div><div class='ctx'> #define CCS_DPHY_PREAMBLE_CTRL_ENABLE				BIT(0)</div><div class='del'>-#define CCS_R_DPHY_PREAMBLE_LENGTH				0x0826</div><div class='del'>-#define CCS_R_PHY_SSC_CTRL					0x0828</div><div class='add'>+#define CCS_R_DPHY_PREAMBLE_LENGTH				CCI_REG8(0x0826)</div><div class='add'>+#define CCS_R_PHY_SSC_CTRL					CCI_REG8(0x0828)</div><div class='ctx'> #define CCS_PHY_SSC_CTRL_ENABLE					BIT(0)</div><div class='del'>-#define CCS_R_MANUAL_LP_CTRL					0x0829</div><div class='add'>+#define CCS_R_MANUAL_LP_CTRL					CCI_REG8(0x0829)</div><div class='ctx'> #define CCS_MANUAL_LP_CTRL_ENABLE				BIT(0)</div><div class='del'>-#define CCS_R_TWAKEUP						0x082a</div><div class='del'>-#define CCS_R_TINIT						0x082b</div><div class='del'>-#define CCS_R_THS_EXIT						0x082c</div><div class='del'>-#define CCS_R_THS_EXIT_EX					(0x082e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL			0x0830</div><div class='add'>+#define CCS_R_TWAKEUP						CCI_REG8(0x082a)</div><div class='add'>+#define CCS_R_TINIT						CCI_REG8(0x082b)</div><div class='add'>+#define CCS_R_THS_EXIT						CCI_REG8(0x082c)</div><div class='add'>+#define CCS_R_THS_EXIT_EX					CCI_REG16(0x082e)</div><div class='add'>+#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL			CCI_REG8(0x0830)</div><div class='ctx'> #define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING	BIT(0)</div><div class='del'>-#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL			0x0831</div><div class='del'>-#define CCS_R_PHY_INIT_CALIBRATION_CTRL				0x0832</div><div class='add'>+#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL			CCI_REG8(0x0831)</div><div class='add'>+#define CCS_R_PHY_INIT_CALIBRATION_CTRL				CCI_REG8(0x0832)</div><div class='ctx'> #define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START		BIT(0)</div><div class='del'>-#define CCS_R_DPHY_CALIBRATION_MODE				0x0833</div><div class='add'>+#define CCS_R_DPHY_CALIBRATION_MODE				CCI_REG8(0x0833)</div><div class='ctx'> #define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE		BIT(0)</div><div class='del'>-#define CCS_R_CPHY_CALIBRATION_MODE				0x0834</div><div class='add'>+#define CCS_R_CPHY_CALIBRATION_MODE				CCI_REG8(0x0834)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_MODE_FORMAT_1			0U</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_MODE_FORMAT_2			1U</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_MODE_FORMAT_3			2U</div><div class='del'>-#define CCS_R_T3_CALPREAMBLE_LENGTH				0x0835</div><div class='del'>-#define CCS_R_T3_CALPREAMBLE_LENGTH_PER				0x0836</div><div class='del'>-#define CCS_R_T3_CALALTSEQ_LENGTH				0x0837</div><div class='del'>-#define CCS_R_T3_CALALTSEQ_LENGTH_PER				0x0838</div><div class='del'>-#define CCS_R_FM2_INIT_SEED					(0x083a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_T3_CALUDEFSEQ_LENGTH				(0x083c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER				(0x083e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TGR_PREAMBLE_LENGTH				0x0841</div><div class='add'>+#define CCS_R_T3_CALPREAMBLE_LENGTH				CCI_REG8(0x0835)</div><div class='add'>+#define CCS_R_T3_CALPREAMBLE_LENGTH_PER				CCI_REG8(0x0836)</div><div class='add'>+#define CCS_R_T3_CALALTSEQ_LENGTH				CCI_REG8(0x0837)</div><div class='add'>+#define CCS_R_T3_CALALTSEQ_LENGTH_PER				CCI_REG8(0x0838)</div><div class='add'>+#define CCS_R_FM2_INIT_SEED					CCI_REG16(0x083a)</div><div class='add'>+#define CCS_R_T3_CALUDEFSEQ_LENGTH				CCI_REG16(0x083c)</div><div class='add'>+#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER				CCI_REG16(0x083e)</div><div class='add'>+#define CCS_R_TGR_PREAMBLE_LENGTH				CCI_REG8(0x0841)</div><div class='ctx'> #define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ		BIT(7)</div><div class='ctx'> #define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT	0U</div><div class='ctx'> #define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK	0x3f</div><div class='del'>-#define CCS_R_TGR_POST_LENGTH					0x0842</div><div class='add'>+#define CCS_R_TGR_POST_LENGTH					CCI_REG8(0x0842)</div><div class='ctx'> #define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT			0U</div><div class='ctx'> #define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK			0x1f</div><div class='del'>-#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2)			(0x0843 + (n2))</div><div class='add'>+#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2)			CCI_REG8(0x0843 + (n2))</div><div class='ctx'> #define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2		0U</div><div class='ctx'> #define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2		6U</div><div class='ctx'> #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT		3U</div><div class='ctx'> #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK		0x38</div><div class='ctx'> #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT		0U</div><div class='ctx'> #define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK		0x7</div><div class='del'>-#define CCS_R_T3_PREPARE					(0x084e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_T3_LPX						(0x0850 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ALPS_CTRL						0x085a</div><div class='add'>+#define CCS_R_T3_PREPARE					CCI_REG16(0x084e)</div><div class='add'>+#define CCS_R_T3_LPX						CCI_REG16(0x0850)</div><div class='add'>+#define CCS_R_ALPS_CTRL						CCI_REG8(0x085a)</div><div class='ctx'> #define CCS_ALPS_CTRL_LVLP_DPHY					BIT(0)</div><div class='ctx'> #define CCS_ALPS_CTRL_LVLP_CPHY					BIT(1)</div><div class='ctx'> #define CCS_ALPS_CTRL_ALP_CPHY					BIT(2)</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY			(0x0860 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY			(0x0862 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY			(0x0864 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY			(0x0866 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY			0x0868</div><div class='del'>-#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY			0x0869</div><div class='del'>-#define CCS_R_SCRAMBLING_CTRL					0x0870</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY			CCI_REG16(0x0860)</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY			CCI_REG16(0x0862)</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY			CCI_REG16(0x0864)</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY			CCI_REG16(0x0866)</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY			CCI_REG8(0x0868)</div><div class='add'>+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY			CCI_REG8(0x0869)</div><div class='add'>+#define CCS_R_SCRAMBLING_CTRL					CCI_REG8(0x0870)</div><div class='ctx'> #define CCS_SCRAMBLING_CTRL_ENABLED				BIT(0)</div><div class='ctx'> #define CCS_SCRAMBLING_CTRL_SHIFT				2U</div><div class='ctx'> #define CCS_SCRAMBLING_CTRL_MASK				0xc</div><div class='ctx'> #define CCS_SCRAMBLING_CTRL_1_SEED_CPHY				0U</div><div class='ctx'> #define CCS_SCRAMBLING_CTRL_4_SEED_CPHY				3U</div><div class='del'>-#define CCS_R_LANE_SEED_VALUE(seed, lane)			((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)</div><div class='add'>+#define CCS_R_LANE_SEED_VALUE(seed, lane)			CCI_REG16(0x0872 + (seed) * 16 + (lane) * 2)</div><div class='ctx'> #define CCS_LIM_LANE_SEED_VALUE_MIN_SEED			0U</div><div class='ctx'> #define CCS_LIM_LANE_SEED_VALUE_MAX_SEED			3U</div><div class='ctx'> #define CCS_LIM_LANE_SEED_VALUE_MIN_LANE			0U</div><div class='ctx'> #define CCS_LIM_LANE_SEED_VALUE_MAX_LANE			7U</div><div class='del'>-#define CCS_R_TX_USL_REV_ENTRY					(0x08c0 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_REV_CLOCK_COUNTER				(0x08c2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_REV_LP_COUNTER				(0x08c4 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_REV_FRAME_COUNTER				(0x08c6 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER			(0x08c8 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_FWD_ENTRY					(0x08ca | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_GPIO					(0x08cc | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_OPERATION					(0x08ce | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_TX_USL_REV_ENTRY					CCI_REG16(0x08c0)</div><div class='add'>+#define CCS_R_TX_USL_REV_CLOCK_COUNTER				CCI_REG16(0x08c2)</div><div class='add'>+#define CCS_R_TX_USL_REV_LP_COUNTER				CCI_REG16(0x08c4)</div><div class='add'>+#define CCS_R_TX_USL_REV_FRAME_COUNTER				CCI_REG16(0x08c6)</div><div class='add'>+#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER			CCI_REG16(0x08c8)</div><div class='add'>+#define CCS_R_TX_USL_FWD_ENTRY					CCI_REG16(0x08ca)</div><div class='add'>+#define CCS_R_TX_USL_GPIO					CCI_REG16(0x08cc)</div><div class='add'>+#define CCS_R_TX_USL_OPERATION					CCI_REG16(0x08ce)</div><div class='ctx'> #define CCS_TX_USL_OPERATION_RESET				BIT(0)</div><div class='del'>-#define CCS_R_TX_USL_ALP_CTRL					(0x08d0 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_TX_USL_ALP_CTRL					CCI_REG16(0x08d0)</div><div class='ctx'> #define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE				BIT(0)</div><div class='del'>-#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT			(0x08d2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT			(0x08d2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_USL_CLOCK_MODE_D_CTRL				0x08d2</div><div class='add'>+#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT			CCI_REG16(0x08d2)</div><div class='add'>+#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT			CCI_REG16(0x08d2)</div><div class='add'>+#define CCS_R_USL_CLOCK_MODE_D_CTRL				CCI_REG8(0x08d2)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY		BIT(0)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK		BIT(1)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK		BIT(2)</div><div class='del'>-#define CCS_R_BINNING_MODE					0x0900</div><div class='del'>-#define CCS_R_BINNING_TYPE					0x0901</div><div class='del'>-#define CCS_R_BINNING_WEIGHTING					0x0902</div><div class='del'>-#define CCS_R_DATA_TRANSFER_IF_1_CTRL				0x0a00</div><div class='add'>+#define CCS_R_BINNING_MODE					CCI_REG8(0x0900)</div><div class='add'>+#define CCS_R_BINNING_TYPE					CCI_REG8(0x0901)</div><div class='add'>+#define CCS_R_BINNING_WEIGHTING					CCI_REG8(0x0902)</div><div class='add'>+#define CCS_R_DATA_TRANSFER_IF_1_CTRL				CCI_REG8(0x0a00)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE			BIT(0)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE			BIT(1)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR			BIT(2)</div><div class='del'>-#define CCS_R_DATA_TRANSFER_IF_1_STATUS				0x0a01</div><div class='add'>+#define CCS_R_DATA_TRANSFER_IF_1_STATUS				CCI_REG8(0x0a01)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY		BIT(0)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY		BIT(1)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED		BIT(2)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE		BIT(3)</div><div class='del'>-#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT			0x0a02</div><div class='del'>-#define CCS_R_DATA_TRANSFER_IF_1_DATA(p)			(0x0a04 + (p))</div><div class='add'>+#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT			CCI_REG8(0x0a02)</div><div class='add'>+#define CCS_R_DATA_TRANSFER_IF_1_DATA(p)			CCI_REG8(0x0a04 + (p))</div><div class='ctx'> #define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P			0U</div><div class='ctx'> #define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P			63U</div><div class='del'>-#define CCS_R_SHADING_CORRECTION_EN				0x0b00</div><div class='add'>+#define CCS_R_SHADING_CORRECTION_EN				CCI_REG8(0x0b00)</div><div class='ctx'> #define CCS_SHADING_CORRECTION_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_LUMINANCE_CORRECTION_LEVEL			0x0b01</div><div class='del'>-#define CCS_R_GREEN_IMBALANCE_FILTER_EN				0x0b02</div><div class='add'>+#define CCS_R_LUMINANCE_CORRECTION_LEVEL			CCI_REG8(0x0b01)</div><div class='add'>+#define CCS_R_GREEN_IMBALANCE_FILTER_EN				CCI_REG8(0x0b02)</div><div class='ctx'> #define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_MAPPED_DEFECT_CORRECT_EN				0x0b05</div><div class='add'>+#define CCS_R_MAPPED_DEFECT_CORRECT_EN				CCI_REG8(0x0b05)</div><div class='ctx'> #define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_SINGLE_DEFECT_CORRECT_EN				0x0b06</div><div class='add'>+#define CCS_R_SINGLE_DEFECT_CORRECT_EN				CCI_REG8(0x0b06)</div><div class='ctx'> #define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN			0x0b08</div><div class='add'>+#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN			CCI_REG8(0x0b08)</div><div class='ctx'> #define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_COMBINED_DEFECT_CORRECT_EN			0x0b0a</div><div class='add'>+#define CCS_R_COMBINED_DEFECT_CORRECT_EN			CCI_REG8(0x0b0a)</div><div class='ctx'> #define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE			BIT(0)</div><div class='del'>-#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN			0x0b0c</div><div class='add'>+#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN			CCI_REG8(0x0b0c)</div><div class='ctx'> #define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE		BIT(0)</div><div class='del'>-#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN			0x0b13</div><div class='add'>+#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN			CCI_REG8(0x0b13)</div><div class='ctx'> #define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE		BIT(0)</div><div class='del'>-#define CCS_R_NF_CTRL						0x0b15</div><div class='add'>+#define CCS_R_NF_CTRL						CCI_REG8(0x0b15)</div><div class='ctx'> #define CCS_NF_CTRL_LUMA					BIT(0)</div><div class='ctx'> #define CCS_NF_CTRL_CHROMA					BIT(1)</div><div class='ctx'> #define CCS_NF_CTRL_COMBINED					BIT(2)</div><div class='del'>-#define CCS_R_OB_READOUT_CONTROL				0x0b30</div><div class='add'>+#define CCS_R_OB_READOUT_CONTROL				CCI_REG8(0x0b30)</div><div class='ctx'> #define CCS_OB_READOUT_CONTROL_ENABLE				BIT(0)</div><div class='ctx'> #define CCS_OB_READOUT_CONTROL_INTERLEAVING			BIT(1)</div><div class='del'>-#define CCS_R_OB_VIRTUAL_CHANNEL				0x0b31</div><div class='del'>-#define CCS_R_OB_DT						0x0b32</div><div class='del'>-#define CCS_R_OB_DATA_FORMAT					0x0b33</div><div class='del'>-#define CCS_R_COLOR_TEMPERATURE					(0x0b8c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ABSOLUTE_GAIN_GREENR				(0x0b8e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ABSOLUTE_GAIN_RED					(0x0b90 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ABSOLUTE_GAIN_BLUE				(0x0b92 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_ABSOLUTE_GAIN_GREENB				(0x0b94 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_CFA_CONVERSION_CTRL				0x0ba0</div><div class='add'>+#define CCS_R_OB_VIRTUAL_CHANNEL				CCI_REG8(0x0b31)</div><div class='add'>+#define CCS_R_OB_DT						CCI_REG8(0x0b32)</div><div class='add'>+#define CCS_R_OB_DATA_FORMAT					CCI_REG8(0x0b33)</div><div class='add'>+#define CCS_R_COLOR_TEMPERATURE					CCI_REG16(0x0b8c)</div><div class='add'>+#define CCS_R_ABSOLUTE_GAIN_GREENR				CCI_REG16(0x0b8e)</div><div class='add'>+#define CCS_R_ABSOLUTE_GAIN_RED					CCI_REG16(0x0b90)</div><div class='add'>+#define CCS_R_ABSOLUTE_GAIN_BLUE				CCI_REG16(0x0b92)</div><div class='add'>+#define CCS_R_ABSOLUTE_GAIN_GREENB				CCI_REG16(0x0b94)</div><div class='add'>+#define CCS_R_CFA_CONVERSION_CTRL				CCI_REG8(0x0ba0)</div><div class='ctx'> #define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE		BIT(0)</div><div class='del'>-#define CCS_R_FLASH_STROBE_ADJUSTMENT				0x0c12</div><div class='del'>-#define CCS_R_FLASH_STROBE_START_POINT				(0x0c14 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL			(0x0c16 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL			(0x0c18 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FLASH_MODE_RS					0x0c1a</div><div class='add'>+#define CCS_R_FLASH_STROBE_ADJUSTMENT				CCI_REG8(0x0c12)</div><div class='add'>+#define CCS_R_FLASH_STROBE_START_POINT				CCI_REG16(0x0c14)</div><div class='add'>+#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL			CCI_REG16(0x0c16)</div><div class='add'>+#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL			CCI_REG16(0x0c18)</div><div class='add'>+#define CCS_R_FLASH_MODE_RS					CCI_REG8(0x0c1a)</div><div class='ctx'> #define CCS_FLASH_MODE_RS_CONTINUOUS				BIT(0)</div><div class='ctx'> #define CCS_FLASH_MODE_RS_TRUNCATE				BIT(1)</div><div class='ctx'> #define CCS_FLASH_MODE_RS_ASYNC					BIT(3)</div><div class='del'>-#define CCS_R_FLASH_TRIGGER_RS					0x0c1b</div><div class='del'>-#define CCS_R_FLASH_STATUS					0x0c1c</div><div class='add'>+#define CCS_R_FLASH_TRIGGER_RS					CCI_REG8(0x0c1b)</div><div class='add'>+#define CCS_R_FLASH_STATUS					CCI_REG8(0x0c1c)</div><div class='ctx'> #define CCS_FLASH_STATUS_RETIMED				BIT(0)</div><div class='del'>-#define CCS_R_SA_STROBE_MODE					0x0c1d</div><div class='add'>+#define CCS_R_SA_STROBE_MODE					CCI_REG8(0x0c1d)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_CONTINUOUS				BIT(0)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_TRUNCATE				BIT(1)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_ASYNC				BIT(3)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_ADJUST_EDGE				BIT(4)</div><div class='del'>-#define CCS_R_SA_STROBE_START_POINT				(0x0c1e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TSA_STROBE_DELAY_CTRL				(0x0c20 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TSA_STROBE_WIDTH_CTRL				(0x0c22 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SA_STROBE_TRIGGER					0x0c24</div><div class='del'>-#define CCS_R_SA_STROBE_STATUS					0x0c25</div><div class='add'>+#define CCS_R_SA_STROBE_START_POINT				CCI_REG16(0x0c1e)</div><div class='add'>+#define CCS_R_TSA_STROBE_DELAY_CTRL				CCI_REG16(0x0c20)</div><div class='add'>+#define CCS_R_TSA_STROBE_WIDTH_CTRL				CCI_REG16(0x0c22)</div><div class='add'>+#define CCS_R_SA_STROBE_TRIGGER					CCI_REG8(0x0c24)</div><div class='add'>+#define CCS_R_SA_STROBE_STATUS					CCI_REG8(0x0c25)</div><div class='ctx'> #define CCS_SA_STROBE_STATUS_RETIMED				BIT(0)</div><div class='del'>-#define CCS_R_TSA_STROBE_RE_DELAY_CTRL				(0x0c30 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_TSA_STROBE_FE_DELAY_CTRL				(0x0c32 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PDAF_CTRL						(0x0d00 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_TSA_STROBE_RE_DELAY_CTRL				CCI_REG16(0x0c30)</div><div class='add'>+#define CCS_R_TSA_STROBE_FE_DELAY_CTRL				CCI_REG16(0x0c32)</div><div class='add'>+#define CCS_R_PDAF_CTRL						CCI_REG16(0x0d00)</div><div class='ctx'> #define CCS_PDAF_CTRL_ENABLE					BIT(0)</div><div class='ctx'> #define CCS_PDAF_CTRL_PROCESSED					BIT(1)</div><div class='ctx'> #define CCS_PDAF_CTRL_INTERLEAVED				BIT(2)</div><div class='ctx'> #define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION			BIT(3)</div><div class='del'>-#define CCS_R_PDAF_VC						0x0d02</div><div class='del'>-#define CCS_R_PDAF_DT						0x0d03</div><div class='del'>-#define CCS_R_PD_X_ADDR_START					(0x0d04 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PD_Y_ADDR_START					(0x0d06 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PD_X_ADDR_END					(0x0d08 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PD_Y_ADDR_END					(0x0d0a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_BRACKETING_LUT_CTRL				0x0e00</div><div class='del'>-#define CCS_R_BRACKETING_LUT_MODE				0x0e01</div><div class='add'>+#define CCS_R_PDAF_VC						CCI_REG8(0x0d02)</div><div class='add'>+#define CCS_R_PDAF_DT						CCI_REG8(0x0d03)</div><div class='add'>+#define CCS_R_PD_X_ADDR_START					CCI_REG16(0x0d04)</div><div class='add'>+#define CCS_R_PD_Y_ADDR_START					CCI_REG16(0x0d06)</div><div class='add'>+#define CCS_R_PD_X_ADDR_END					CCI_REG16(0x0d08)</div><div class='add'>+#define CCS_R_PD_Y_ADDR_END					CCI_REG16(0x0d0a)</div><div class='add'>+#define CCS_R_BRACKETING_LUT_CTRL				CCI_REG8(0x0e00)</div><div class='add'>+#define CCS_R_BRACKETING_LUT_MODE				CCI_REG8(0x0e01)</div><div class='ctx'> #define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING		BIT(0)</div><div class='ctx'> #define CCS_BRACKETING_LUT_MODE_LOOP_MODE			BIT(1)</div><div class='del'>-#define CCS_R_BRACKETING_LUT_ENTRY_CTRL				0x0e02</div><div class='del'>-#define CCS_R_BRACKETING_LUT_FRAME(n)				(0x0e10 + (n))</div><div class='add'>+#define CCS_R_BRACKETING_LUT_ENTRY_CTRL				CCI_REG8(0x0e02)</div><div class='add'>+#define CCS_R_BRACKETING_LUT_FRAME(n)				CCI_REG8(0x0e10 + (n))</div><div class='ctx'> #define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N			0U</div><div class='ctx'> #define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N			239U</div><div class='del'>-#define CCS_R_INTEGRATION_TIME_CAPABILITY			(0x1000 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_INTEGRATION_TIME_CAPABILITY			CCI_REG16(0x1000)</div><div class='ctx'> #define CCS_INTEGRATION_TIME_CAPABILITY_FINE			BIT(0)</div><div class='del'>-#define CCS_R_COARSE_INTEGRATION_TIME_MIN			(0x1004 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN		(0x1006 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FINE_INTEGRATION_TIME_MIN				(0x1008 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN			(0x100a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_GAIN_CAPABILITY				0x1081</div><div class='add'>+#define CCS_R_COARSE_INTEGRATION_TIME_MIN			CCI_REG16(0x1004)</div><div class='add'>+#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN		CCI_REG16(0x1006)</div><div class='add'>+#define CCS_R_FINE_INTEGRATION_TIME_MIN				CCI_REG16(0x1008)</div><div class='add'>+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN			CCI_REG16(0x100a)</div><div class='add'>+#define CCS_R_DIGITAL_GAIN_CAPABILITY				CCI_REG8(0x1081)</div><div class='ctx'> #define CCS_DIGITAL_GAIN_CAPABILITY_NONE			0U</div><div class='ctx'> #define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL			2U</div><div class='del'>-#define CCS_R_DIGITAL_GAIN_MIN					(0x1084 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_GAIN_MAX					(0x1086 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_GAIN_STEP_SIZE				(0x1088 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_PEDESTAL_CAPABILITY				0x10e0</div><div class='del'>-#define CCS_R_ADC_CAPABILITY					0x10f0</div><div class='add'>+#define CCS_R_DIGITAL_GAIN_MIN					CCI_REG16(0x1084)</div><div class='add'>+#define CCS_R_DIGITAL_GAIN_MAX					CCI_REG16(0x1086)</div><div class='add'>+#define CCS_R_DIGITAL_GAIN_STEP_SIZE				CCI_REG16(0x1088)</div><div class='add'>+#define CCS_R_PEDESTAL_CAPABILITY				CCI_REG8(0x10e0)</div><div class='add'>+#define CCS_R_ADC_CAPABILITY					CCI_REG8(0x10f0)</div><div class='ctx'> #define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL			BIT(0)</div><div class='del'>-#define CCS_R_ADC_BIT_DEPTH_CAPABILITY				(0x10f4 | CCS_FL_32BIT)</div><div class='del'>-#define CCS_R_MIN_EXT_CLK_FREQ_MHZ				(0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_EXT_CLK_FREQ_MHZ				(0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_PRE_PLL_CLK_DIV				(0x1108 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_PRE_PLL_CLK_DIV				(0x110a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ				(0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ				(0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_PLL_MULTIPLIER				(0x1114 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_PLL_MULTIPLIER				(0x1116 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ				(0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ				(0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_VT_SYS_CLK_DIV				(0x1120 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_VT_SYS_CLK_DIV				(0x1122 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ				(0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ				(0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ				(0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ				(0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_VT_PIX_CLK_DIV				(0x1134 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_VT_PIX_CLK_DIV				(0x1136 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_CLOCK_CALCULATION					0x1138</div><div class='add'>+#define CCS_R_ADC_BIT_DEPTH_CAPABILITY				CCI_REG32(0x10f4)</div><div class='add'>+#define CCS_R_MIN_EXT_CLK_FREQ_MHZ				(CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_EXT_CLK_FREQ_MHZ				(CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_PRE_PLL_CLK_DIV				CCI_REG16(0x1108)</div><div class='add'>+#define CCS_R_MAX_PRE_PLL_CLK_DIV				CCI_REG16(0x110a)</div><div class='add'>+#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ				(CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ				(CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_PLL_MULTIPLIER				CCI_REG16(0x1114)</div><div class='add'>+#define CCS_R_MAX_PLL_MULTIPLIER				CCI_REG16(0x1116)</div><div class='add'>+#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ				(CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ				(CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_VT_SYS_CLK_DIV				CCI_REG16(0x1120)</div><div class='add'>+#define CCS_R_MAX_VT_SYS_CLK_DIV				CCI_REG16(0x1122)</div><div class='add'>+#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ				(CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ				(CCI_REG32(0x1128) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ				(CCI_REG32(0x112c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ				(CCI_REG32(0x1130) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_VT_PIX_CLK_DIV				CCI_REG16(0x1134)</div><div class='add'>+#define CCS_R_MAX_VT_PIX_CLK_DIV				CCI_REG16(0x1136)</div><div class='add'>+#define CCS_R_CLOCK_CALCULATION					CCI_REG8(0x1138)</div><div class='ctx'> #define CCS_CLOCK_CALCULATION_LANE_SPEED			BIT(0)</div><div class='ctx'> #define CCS_CLOCK_CALCULATION_LINK_DECOUPLED			BIT(1)</div><div class='ctx'> #define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR		BIT(2)</div><div class='ctx'> #define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR		BIT(3)</div><div class='del'>-#define CCS_R_NUM_OF_VT_LANES					0x1139</div><div class='del'>-#define CCS_R_NUM_OF_OP_LANES					0x113a</div><div class='del'>-#define CCS_R_OP_BITS_PER_LANE					0x113b</div><div class='del'>-#define CCS_R_MIN_FRAME_LENGTH_LINES				(0x1140 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_FRAME_LENGTH_LINES				(0x1142 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_LINE_LENGTH_PCK				(0x1144 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_LINE_LENGTH_PCK				(0x1146 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_LINE_BLANKING_PCK				(0x1148 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_FRAME_BLANKING_LINES				(0x114a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE			0x114c</div><div class='del'>-#define CCS_R_TIMING_MODE_CAPABILITY				0x114d</div><div class='add'>+#define CCS_R_NUM_OF_VT_LANES					CCI_REG8(0x1139)</div><div class='add'>+#define CCS_R_NUM_OF_OP_LANES					CCI_REG8(0x113a)</div><div class='add'>+#define CCS_R_OP_BITS_PER_LANE					CCI_REG8(0x113b)</div><div class='add'>+#define CCS_R_MIN_FRAME_LENGTH_LINES				CCI_REG16(0x1140)</div><div class='add'>+#define CCS_R_MAX_FRAME_LENGTH_LINES				CCI_REG16(0x1142)</div><div class='add'>+#define CCS_R_MIN_LINE_LENGTH_PCK				CCI_REG16(0x1144)</div><div class='add'>+#define CCS_R_MAX_LINE_LENGTH_PCK				CCI_REG16(0x1146)</div><div class='add'>+#define CCS_R_MIN_LINE_BLANKING_PCK				CCI_REG16(0x1148)</div><div class='add'>+#define CCS_R_MIN_FRAME_BLANKING_LINES				CCI_REG16(0x114a)</div><div class='add'>+#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE			CCI_REG8(0x114c)</div><div class='add'>+#define CCS_R_TIMING_MODE_CAPABILITY				CCI_REG8(0x114d)</div><div class='ctx'> #define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH		BIT(0)</div><div class='ctx'> #define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT      BIT(2)</div><div class='ctx'> #define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START	BIT(3)</div><div class='ctx'> #define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA       BIT(4)</div><div class='del'>-#define CCS_R_FRAME_MARGIN_MAX_VALUE				(0x114e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FRAME_MARGIN_MIN_VALUE				0x1150</div><div class='del'>-#define CCS_R_GAIN_DELAY_TYPE					0x1151</div><div class='add'>+#define CCS_R_FRAME_MARGIN_MAX_VALUE				CCI_REG16(0x114e)</div><div class='add'>+#define CCS_R_FRAME_MARGIN_MIN_VALUE				CCI_REG8(0x1150)</div><div class='add'>+#define CCS_R_GAIN_DELAY_TYPE					CCI_REG8(0x1151)</div><div class='ctx'> #define CCS_GAIN_DELAY_TYPE_FIXED				0U</div><div class='ctx'> #define CCS_GAIN_DELAY_TYPE_VARIABLE				1U</div><div class='del'>-#define CCS_R_MIN_OP_SYS_CLK_DIV				(0x1160 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_OP_SYS_CLK_DIV				(0x1162 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ				(0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ				(0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_OP_PIX_CLK_DIV				(0x116c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_OP_PIX_CLK_DIV				(0x116e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ				(0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ				(0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_X_ADDR_MIN					(0x1180 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_ADDR_MIN					(0x1182 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_ADDR_MAX					(0x1184 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_Y_ADDR_MAX					(0x1186 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_X_OUTPUT_SIZE					(0x1188 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_Y_OUTPUT_SIZE					(0x118a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_X_OUTPUT_SIZE					(0x118c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_Y_OUTPUT_SIZE					(0x118e | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_X_ADDR_START_DIV_CONSTANT				0x1190</div><div class='del'>-#define CCS_R_Y_ADDR_START_DIV_CONSTANT				0x1191</div><div class='del'>-#define CCS_R_X_ADDR_END_DIV_CONSTANT				0x1192</div><div class='del'>-#define CCS_R_Y_ADDR_END_DIV_CONSTANT				0x1193</div><div class='del'>-#define CCS_R_X_SIZE_DIV					0x1194</div><div class='del'>-#define CCS_R_Y_SIZE_DIV					0x1195</div><div class='del'>-#define CCS_R_X_OUTPUT_DIV					0x1196</div><div class='del'>-#define CCS_R_Y_OUTPUT_DIV					0x1197</div><div class='del'>-#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT			0x1198</div><div class='add'>+#define CCS_R_MIN_OP_SYS_CLK_DIV				CCI_REG16(0x1160)</div><div class='add'>+#define CCS_R_MAX_OP_SYS_CLK_DIV				CCI_REG16(0x1162)</div><div class='add'>+#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ				(CCI_REG32(0x1164) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ				(CCI_REG32(0x1168) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_OP_PIX_CLK_DIV				CCI_REG16(0x116c)</div><div class='add'>+#define CCS_R_MAX_OP_PIX_CLK_DIV				CCI_REG16(0x116e)</div><div class='add'>+#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ				(CCI_REG32(0x1170) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ				(CCI_REG32(0x1174) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_X_ADDR_MIN					CCI_REG16(0x1180)</div><div class='add'>+#define CCS_R_Y_ADDR_MIN					CCI_REG16(0x1182)</div><div class='add'>+#define CCS_R_X_ADDR_MAX					CCI_REG16(0x1184)</div><div class='add'>+#define CCS_R_Y_ADDR_MAX					CCI_REG16(0x1186)</div><div class='add'>+#define CCS_R_MIN_X_OUTPUT_SIZE					CCI_REG16(0x1188)</div><div class='add'>+#define CCS_R_MIN_Y_OUTPUT_SIZE					CCI_REG16(0x118a)</div><div class='add'>+#define CCS_R_MAX_X_OUTPUT_SIZE					CCI_REG16(0x118c)</div><div class='add'>+#define CCS_R_MAX_Y_OUTPUT_SIZE					CCI_REG16(0x118e)</div><div class='add'>+#define CCS_R_X_ADDR_START_DIV_CONSTANT				CCI_REG8(0x1190)</div><div class='add'>+#define CCS_R_Y_ADDR_START_DIV_CONSTANT				CCI_REG8(0x1191)</div><div class='add'>+#define CCS_R_X_ADDR_END_DIV_CONSTANT				CCI_REG8(0x1192)</div><div class='add'>+#define CCS_R_Y_ADDR_END_DIV_CONSTANT				CCI_REG8(0x1193)</div><div class='add'>+#define CCS_R_X_SIZE_DIV					CCI_REG8(0x1194)</div><div class='add'>+#define CCS_R_Y_SIZE_DIV					CCI_REG8(0x1195)</div><div class='add'>+#define CCS_R_X_OUTPUT_DIV					CCI_REG8(0x1196)</div><div class='add'>+#define CCS_R_Y_OUTPUT_DIV					CCI_REG8(0x1197)</div><div class='add'>+#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT			CCI_REG8(0x1198)</div><div class='ctx'> #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR	BIT(0)</div><div class='ctx'> #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES	BIT(1)</div><div class='ctx'> #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD	BIT(2)</div><div class='ctx'> #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP       BIT(3)</div><div class='del'>-#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV				(0x11a0 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV				(0x11a2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ			(0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ			(0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_OP_PLL_MULTIPLIER				(0x11ac | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_OP_PLL_MULTIPLIER				(0x11ae | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ			(0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ			(0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_CLOCK_TREE_PLL_CAPABILITY				0x11b8</div><div class='add'>+#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV				CCI_REG16(0x11a0)</div><div class='add'>+#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV				CCI_REG16(0x11a2)</div><div class='add'>+#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ			(CCI_REG32(0x11a4) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ			(CCI_REG32(0x11a8) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_OP_PLL_MULTIPLIER				CCI_REG16(0x11ac)</div><div class='add'>+#define CCS_R_MAX_OP_PLL_MULTIPLIER				CCI_REG16(0x11ae)</div><div class='add'>+#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ			(CCI_REG32(0x11b0) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ			(CCI_REG32(0x11b4) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_CLOCK_TREE_PLL_CAPABILITY				CCI_REG8(0x11b8)</div><div class='ctx'> #define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL			BIT(0)</div><div class='ctx'> #define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL		BIT(1)</div><div class='ctx'> #define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER		BIT(2)</div><div class='ctx'> #define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV	BIT(3)</div><div class='del'>-#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY			0x11b9</div><div class='add'>+#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY			CCI_REG8(0x11b9)</div><div class='ctx'> #define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL			BIT(0)</div><div class='del'>-#define CCS_R_MIN_EVEN_INC					(0x11c0 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_ODD_INC					(0x11c2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_EVEN_INC					(0x11c4 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_ODD_INC					(0x11c6 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_AUX_SUBSAMP_CAPABILITY				0x11c8</div><div class='add'>+#define CCS_R_MIN_EVEN_INC					CCI_REG16(0x11c0)</div><div class='add'>+#define CCS_R_MIN_ODD_INC					CCI_REG16(0x11c2)</div><div class='add'>+#define CCS_R_MAX_EVEN_INC					CCI_REG16(0x11c4)</div><div class='add'>+#define CCS_R_MAX_ODD_INC					CCI_REG16(0x11c6)</div><div class='add'>+#define CCS_R_AUX_SUBSAMP_CAPABILITY				CCI_REG8(0x11c8)</div><div class='ctx'> #define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2		BIT(1)</div><div class='del'>-#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY			0x11c9</div><div class='add'>+#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY			CCI_REG8(0x11c9)</div><div class='ctx'> #define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2	BIT(1)</div><div class='del'>-#define CCS_R_MONOCHROME_CAPABILITY				0x11ca</div><div class='add'>+#define CCS_R_MONOCHROME_CAPABILITY				CCI_REG8(0x11ca)</div><div class='ctx'> #define CCS_MONOCHROME_CAPABILITY_INC_ODD			0U</div><div class='ctx'> #define CCS_MONOCHROME_CAPABILITY_INC_EVEN			1U</div><div class='del'>-#define CCS_R_PIXEL_READOUT_CAPABILITY				0x11cb</div><div class='add'>+#define CCS_R_PIXEL_READOUT_CAPABILITY				CCI_REG8(0x11cb)</div><div class='ctx'> #define CCS_PIXEL_READOUT_CAPABILITY_BAYER			0U</div><div class='ctx'> #define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME			1U</div><div class='ctx'> #define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO		2U</div><div class='del'>-#define CCS_R_MIN_EVEN_INC_MONO					(0x11cc | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_EVEN_INC_MONO					(0x11ce | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_ODD_INC_MONO					(0x11d0 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_ODD_INC_MONO					(0x11d2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_EVEN_INC_BC2					(0x11d4 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_EVEN_INC_BC2					(0x11d6 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_ODD_INC_BC2					(0x11d8 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_ODD_INC_BC2					(0x11da | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_EVEN_INC_MONO_BC2				(0x11dc | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_EVEN_INC_MONO_BC2				(0x11de | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_ODD_INC_MONO_BC2				(0x11f0 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_ODD_INC_MONO_BC2				(0x11f2 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SCALING_CAPABILITY				(0x1200 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_MIN_EVEN_INC_MONO					CCI_REG16(0x11cc)</div><div class='add'>+#define CCS_R_MAX_EVEN_INC_MONO					CCI_REG16(0x11ce)</div><div class='add'>+#define CCS_R_MIN_ODD_INC_MONO					CCI_REG16(0x11d0)</div><div class='add'>+#define CCS_R_MAX_ODD_INC_MONO					CCI_REG16(0x11d2)</div><div class='add'>+#define CCS_R_MIN_EVEN_INC_BC2					CCI_REG16(0x11d4)</div><div class='add'>+#define CCS_R_MAX_EVEN_INC_BC2					CCI_REG16(0x11d6)</div><div class='add'>+#define CCS_R_MIN_ODD_INC_BC2					CCI_REG16(0x11d8)</div><div class='add'>+#define CCS_R_MAX_ODD_INC_BC2					CCI_REG16(0x11da)</div><div class='add'>+#define CCS_R_MIN_EVEN_INC_MONO_BC2				CCI_REG16(0x11dc)</div><div class='add'>+#define CCS_R_MAX_EVEN_INC_MONO_BC2				CCI_REG16(0x11de)</div><div class='add'>+#define CCS_R_MIN_ODD_INC_MONO_BC2				CCI_REG16(0x11f0)</div><div class='add'>+#define CCS_R_MAX_ODD_INC_MONO_BC2				CCI_REG16(0x11f2)</div><div class='add'>+#define CCS_R_SCALING_CAPABILITY				CCI_REG16(0x1200)</div><div class='ctx'> #define CCS_SCALING_CAPABILITY_NONE				0U</div><div class='ctx'> #define CCS_SCALING_CAPABILITY_HORIZONTAL			1U</div><div class='ctx'> #define CCS_SCALING_CAPABILITY_RESERVED				2U</div><div class='del'>-#define CCS_R_SCALER_M_MIN					(0x1204 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SCALER_M_MAX					(0x1206 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SCALER_N_MIN					(0x1208 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_SCALER_N_MAX					(0x120a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_DIGITAL_CROP_CAPABILITY				0x120e</div><div class='add'>+#define CCS_R_SCALER_M_MIN					CCI_REG16(0x1204)</div><div class='add'>+#define CCS_R_SCALER_M_MAX					CCI_REG16(0x1206)</div><div class='add'>+#define CCS_R_SCALER_N_MIN					CCI_REG16(0x1208)</div><div class='add'>+#define CCS_R_SCALER_N_MAX					CCI_REG16(0x120a)</div><div class='add'>+#define CCS_R_DIGITAL_CROP_CAPABILITY				CCI_REG8(0x120e)</div><div class='ctx'> #define CCS_DIGITAL_CROP_CAPABILITY_NONE			0U</div><div class='ctx'> #define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP			1U</div><div class='del'>-#define CCS_R_HDR_CAPABILITY_1					0x1210</div><div class='add'>+#define CCS_R_HDR_CAPABILITY_1					CCI_REG8(0x1210)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_2X2_BINNING			BIT(0)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN		BIT(1)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN		BIT(2)</div><div class='hunk'>@@ -611,66 +611,66 @@</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_RESET_SYNC				BIT(4)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING		BIT(5)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS		BIT(6)</div><div class='del'>-#define CCS_R_MIN_HDR_BIT_DEPTH					0x1211</div><div class='del'>-#define CCS_R_HDR_RESOLUTION_SUB_TYPES				0x1212</div><div class='del'>-#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n)			(0x1213 + (n))</div><div class='add'>+#define CCS_R_MIN_HDR_BIT_DEPTH					CCI_REG8(0x1211)</div><div class='add'>+#define CCS_R_HDR_RESOLUTION_SUB_TYPES				CCI_REG8(0x1212)</div><div class='add'>+#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n)			CCI_REG8(0x1213 + (n))</div><div class='ctx'> #define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N			0U</div><div class='ctx'> #define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N			1U</div><div class='ctx'> #define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT			0U</div><div class='ctx'> #define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK			0xf</div><div class='ctx'> #define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT		4U</div><div class='ctx'> #define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK			0xf0</div><div class='del'>-#define CCS_R_HDR_CAPABILITY_2					0x121b</div><div class='add'>+#define CCS_R_HDR_CAPABILITY_2					CCI_REG8(0x121b)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN		BIT(0)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN		BIT(1)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_2_TIMING_MODE			BIT(3)</div><div class='ctx'> #define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE			BIT(4)</div><div class='del'>-#define CCS_R_MAX_HDR_BIT_DEPTH					0x121c</div><div class='del'>-#define CCS_R_USL_SUPPORT_CAPABILITY				0x1230</div><div class='add'>+#define CCS_R_MAX_HDR_BIT_DEPTH					CCI_REG8(0x121c)</div><div class='add'>+#define CCS_R_USL_SUPPORT_CAPABILITY				CCI_REG8(0x1230)</div><div class='ctx'> #define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE			BIT(0)</div><div class='ctx'> #define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE		BIT(1)</div><div class='ctx'> #define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC		BIT(2)</div><div class='del'>-#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY			0x1231</div><div class='add'>+#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY			CCI_REG8(0x1231)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY	BIT(0)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK	BIT(1)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK	BIT(2)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY	BIT(3)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK	BIT(4)</div><div class='ctx'> #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK	BIT(5)</div><div class='del'>-#define CCS_R_MIN_OP_SYS_CLK_DIV_REV				0x1234</div><div class='del'>-#define CCS_R_MAX_OP_SYS_CLK_DIV_REV				0x1236</div><div class='del'>-#define CCS_R_MIN_OP_PIX_CLK_DIV_REV				0x1238</div><div class='del'>-#define CCS_R_MAX_OP_PIX_CLK_DIV_REV				0x123a</div><div class='del'>-#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ			(0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ			(0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ			(0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ			(0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))</div><div class='del'>-#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS			(0x124c | (CCS_FL_32BIT | CCS_FL_IREAL))</div><div class='del'>-#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS			(0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL))</div><div class='del'>-#define CCS_R_COMPRESSION_CAPABILITY				0x1300</div><div class='add'>+#define CCS_R_MIN_OP_SYS_CLK_DIV_REV				CCI_REG8(0x1234)</div><div class='add'>+#define CCS_R_MAX_OP_SYS_CLK_DIV_REV				CCI_REG8(0x1236)</div><div class='add'>+#define CCS_R_MIN_OP_PIX_CLK_DIV_REV				CCI_REG8(0x1238)</div><div class='add'>+#define CCS_R_MAX_OP_PIX_CLK_DIV_REV				CCI_REG8(0x123a)</div><div class='add'>+#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ			(CCI_REG32(0x123c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ			(CCI_REG32(0x1240) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ			(CCI_REG32(0x1244) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ			(CCI_REG32(0x1248) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS			(CCI_REG32(0x124c) | CCS_FL_IREAL)</div><div class='add'>+#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS			(CCI_REG32(0x1250) | CCS_FL_IREAL)</div><div class='add'>+#define CCS_R_COMPRESSION_CAPABILITY				CCI_REG8(0x1300)</div><div class='ctx'> #define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE		BIT(0)</div><div class='del'>-#define CCS_R_TEST_MODE_CAPABILITY				(0x1310 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_TEST_MODE_CAPABILITY				CCI_REG16(0x1310)</div><div class='ctx'> #define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR			BIT(0)</div><div class='ctx'> #define CCS_TEST_MODE_CAPABILITY_COLOR_BARS			BIT(1)</div><div class='ctx'> #define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY			BIT(2)</div><div class='ctx'> #define CCS_TEST_MODE_CAPABILITY_PN9				BIT(3)</div><div class='ctx'> #define CCS_TEST_MODE_CAPABILITY_COLOR_TILE			BIT(5)</div><div class='del'>-#define CCS_R_PN9_DATA_FORMAT1					0x1312</div><div class='del'>-#define CCS_R_PN9_DATA_FORMAT2					0x1313</div><div class='del'>-#define CCS_R_PN9_DATA_FORMAT3					0x1314</div><div class='del'>-#define CCS_R_PN9_DATA_FORMAT4					0x1315</div><div class='del'>-#define CCS_R_PN9_MISC_CAPABILITY				0x1316</div><div class='add'>+#define CCS_R_PN9_DATA_FORMAT1					CCI_REG8(0x1312)</div><div class='add'>+#define CCS_R_PN9_DATA_FORMAT2					CCI_REG8(0x1313)</div><div class='add'>+#define CCS_R_PN9_DATA_FORMAT3					CCI_REG8(0x1314)</div><div class='add'>+#define CCS_R_PN9_DATA_FORMAT4					CCI_REG8(0x1315)</div><div class='add'>+#define CCS_R_PN9_MISC_CAPABILITY				CCI_REG8(0x1316)</div><div class='ctx'> #define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT		0U</div><div class='ctx'> #define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK			0x7</div><div class='ctx'> #define CCS_PN9_MISC_CAPABILITY_COMPRESSION			BIT(3)</div><div class='del'>-#define CCS_R_TEST_PATTERN_CAPABILITY				0x1317</div><div class='add'>+#define CCS_R_TEST_PATTERN_CAPABILITY				CCI_REG8(0x1317)</div><div class='ctx'> #define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT			BIT(1)</div><div class='del'>-#define CCS_R_PATTERN_SIZE_DIV_M1				0x1318</div><div class='del'>-#define CCS_R_FIFO_SUPPORT_CAPABILITY				0x1502</div><div class='add'>+#define CCS_R_PATTERN_SIZE_DIV_M1				CCI_REG8(0x1318)</div><div class='add'>+#define CCS_R_FIFO_SUPPORT_CAPABILITY				CCI_REG8(0x1502)</div><div class='ctx'> #define CCS_FIFO_SUPPORT_CAPABILITY_NONE			0U</div><div class='ctx'> #define CCS_FIFO_SUPPORT_CAPABILITY_DERATING			1U</div><div class='ctx'> #define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING		2U</div><div class='del'>-#define CCS_R_PHY_CTRL_CAPABILITY				0x1600</div><div class='add'>+#define CCS_R_PHY_CTRL_CAPABILITY				CCI_REG8(0x1600)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL			BIT(0)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL			BIT(1)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL		BIT(2)</div><div class='hunk'>@@ -679,7 +679,7 @@</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL	BIT(5)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL	BIT(6)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL		BIT(7)</div><div class='del'>-#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY			0x1601</div><div class='add'>+#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY			CCI_REG8(0x1601)</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE		BIT(0)</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE		BIT(1)</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE		BIT(2)</div><div class='hunk'>@@ -688,22 +688,22 @@</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE		BIT(5)</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE		BIT(6)</div><div class='ctx'> #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE		BIT(7)</div><div class='del'>-#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY			0x1602</div><div class='add'>+#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY			CCI_REG8(0x1602)</div><div class='ctx'> #define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY		BIT(2)</div><div class='ctx'> #define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY		BIT(3)</div><div class='del'>-#define CCS_R_FAST_STANDBY_CAPABILITY				0x1603</div><div class='add'>+#define CCS_R_FAST_STANDBY_CAPABILITY				CCI_REG8(0x1603)</div><div class='ctx'> #define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION		0U</div><div class='ctx'> #define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION		1U</div><div class='del'>-#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY			0x1604</div><div class='add'>+#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY			CCI_REG8(0x1604)</div><div class='ctx'> #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE	BIT(0)</div><div class='ctx'> #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR		BIT(1)</div><div class='ctx'> #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR  BIT(2)</div><div class='del'>-#define CCS_R_DATA_TYPE_CAPABILITY				0x1605</div><div class='add'>+#define CCS_R_DATA_TYPE_CAPABILITY				CCI_REG8(0x1605)</div><div class='ctx'> #define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE		BIT(0)</div><div class='ctx'> #define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE       BIT(1)</div><div class='ctx'> #define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE       BIT(2)</div><div class='ctx'> #define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE			BIT(3)</div><div class='del'>-#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY			0x1606</div><div class='add'>+#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY			CCI_REG8(0x1606)</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE		BIT(0)</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE		BIT(1)</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE		BIT(2)</div><div class='hunk'>@@ -712,44 +712,44 @@</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE		BIT(5)</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE		BIT(6)</div><div class='ctx'> #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE		BIT(7)</div><div class='del'>-#define CCS_R_EMB_DATA_CAPABILITY				0x1607</div><div class='add'>+#define CCS_R_EMB_DATA_CAPABILITY				CCI_REG8(0x1607)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16		BIT(0)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20		BIT(1)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24		BIT(2)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16		BIT(3)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20		BIT(4)</div><div class='ctx'> #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24		BIT(5)</div><div class='del'>-#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n)		((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) &lt; 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))</div><div class='add'>+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n)		(CCI_REG32(0x1608 + ((n) &lt; 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4)) | CCS_FL_IREAL)</div><div class='ctx'> #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N	0U</div><div class='ctx'> #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N	7U</div><div class='del'>-#define CCS_R_TEMP_SENSOR_CAPABILITY				0x1618</div><div class='add'>+#define CCS_R_TEMP_SENSOR_CAPABILITY				CCI_REG8(0x1618)</div><div class='ctx'> #define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED			BIT(0)</div><div class='ctx'> #define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT			BIT(1)</div><div class='ctx'> #define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80			BIT(2)</div><div class='del'>-#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n)		((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) &lt; 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))</div><div class='add'>+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n)		(CCI_REG32(0x161a + ((n) &lt; 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4)) | CCS_FL_IREAL)</div><div class='ctx'> #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N	0U</div><div class='ctx'> #define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N	7U</div><div class='del'>-#define CCS_R_DPHY_EQUALIZATION_CAPABILITY			0x162b</div><div class='add'>+#define CCS_R_DPHY_EQUALIZATION_CAPABILITY			CCI_REG8(0x162b)</div><div class='ctx'> #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL	BIT(0)</div><div class='ctx'> #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1			BIT(1)</div><div class='ctx'> #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2			BIT(2)</div><div class='del'>-#define CCS_R_CPHY_EQUALIZATION_CAPABILITY			0x162c</div><div class='add'>+#define CCS_R_CPHY_EQUALIZATION_CAPABILITY			CCI_REG8(0x162c)</div><div class='ctx'> #define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL	BIT(0)</div><div class='del'>-#define CCS_R_DPHY_PREAMBLE_CAPABILITY				0x162d</div><div class='add'>+#define CCS_R_DPHY_PREAMBLE_CAPABILITY				CCI_REG8(0x162d)</div><div class='ctx'> #define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL		BIT(0)</div><div class='del'>-#define CCS_R_DPHY_SSC_CAPABILITY				0x162e</div><div class='add'>+#define CCS_R_DPHY_SSC_CAPABILITY				CCI_REG8(0x162e)</div><div class='ctx'> #define CCS_DPHY_SSC_CAPABILITY_SUPPORTED			BIT(0)</div><div class='del'>-#define CCS_R_CPHY_CALIBRATION_CAPABILITY			0x162f</div><div class='add'>+#define CCS_R_CPHY_CALIBRATION_CAPABILITY			CCI_REG8(0x162f)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL			BIT(0)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING	BIT(1)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL		BIT(2)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL		BIT(3)</div><div class='ctx'> #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL		BIT(4)</div><div class='del'>-#define CCS_R_DPHY_CALIBRATION_CAPABILITY			0x1630</div><div class='add'>+#define CCS_R_DPHY_CALIBRATION_CAPABILITY			CCI_REG8(0x1630)</div><div class='ctx'> #define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL			BIT(0)</div><div class='ctx'> #define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING	BIT(1)</div><div class='ctx'> #define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ		BIT(2)</div><div class='del'>-#define CCS_R_PHY_CTRL_CAPABILITY_2				0x1631</div><div class='add'>+#define CCS_R_PHY_CTRL_CAPABILITY_2				CCI_REG8(0x1631)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH			BIT(0)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ		BIT(1)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING	BIT(2)</div><div class='hunk'>@@ -758,13 +758,13 @@</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY	BIT(5)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY		BIT(6)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY		BIT(7)</div><div class='del'>-#define CCS_R_LRTE_CPHY_CAPABILITY				0x1632</div><div class='add'>+#define CCS_R_LRTE_CPHY_CAPABILITY				CCI_REG8(0x1632)</div><div class='ctx'> #define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT			BIT(0)</div><div class='ctx'> #define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT			BIT(1)</div><div class='ctx'> #define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG			BIT(2)</div><div class='ctx'> #define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG			BIT(3)</div><div class='ctx'> #define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ			BIT(4)</div><div class='del'>-#define CCS_R_LRTE_DPHY_CAPABILITY				0x1633</div><div class='add'>+#define CCS_R_LRTE_DPHY_CAPABILITY				CCI_REG8(0x1633)</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1			BIT(0)</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1		BIT(1)</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1			BIT(2)</div><div class='hunk'>@@ -773,18 +773,18 @@</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2		BIT(5)</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1		BIT(6)</div><div class='ctx'> #define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2		BIT(7)</div><div class='del'>-#define CCS_R_ALPS_CAPABILITY_DPHY				0x1634</div><div class='add'>+#define CCS_R_ALPS_CAPABILITY_DPHY				CCI_REG8(0x1634)</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED		0U</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED			1U</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP		2U</div><div class='del'>-#define CCS_R_ALPS_CAPABILITY_CPHY				0x1635</div><div class='add'>+#define CCS_R_ALPS_CAPABILITY_CPHY				CCI_REG8(0x1635)</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED		0U</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED			1U</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP		2U</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED		0xc</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED			0xd</div><div class='ctx'> #define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP		0xe</div><div class='del'>-#define CCS_R_SCRAMBLING_CAPABILITY				0x1636</div><div class='add'>+#define CCS_R_SCRAMBLING_CAPABILITY				CCI_REG8(0x1636)</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED		BIT(0)</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT	1U</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK	0x6</div><div class='hunk'>@@ -796,11 +796,11 @@</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1		1U</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4		4U</div><div class='ctx'> #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE		BIT(6)</div><div class='del'>-#define CCS_R_DPHY_MANUAL_CONSTANT				0x1637</div><div class='del'>-#define CCS_R_CPHY_MANUAL_CONSTANT				0x1638</div><div class='del'>-#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC			0x1639</div><div class='add'>+#define CCS_R_DPHY_MANUAL_CONSTANT				CCI_REG8(0x1637)</div><div class='add'>+#define CCS_R_CPHY_MANUAL_CONSTANT				CCI_REG8(0x1638)</div><div class='add'>+#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC			CCI_REG8(0x1639)</div><div class='ctx'> #define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2	BIT(0)</div><div class='del'>-#define CCS_R_PHY_CTRL_CAPABILITY_3				0x165c</div><div class='add'>+#define CCS_R_PHY_CTRL_CAPABILITY_3				CCI_REG8(0x165c)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE	BIT(0)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1	BIT(1)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED		BIT(2)</div><div class='hunk'>@@ -808,130 +808,130 @@</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED		BIT(4)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE	BIT(5)</div><div class='ctx'> #define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1	BIT(6)</div><div class='del'>-#define CCS_R_DPHY_SF						0x165d</div><div class='del'>-#define CCS_R_CPHY_SF						0x165e</div><div class='add'>+#define CCS_R_DPHY_SF						CCI_REG8(0x165d)</div><div class='add'>+#define CCS_R_CPHY_SF						CCI_REG8(0x165e)</div><div class='ctx'> #define CCS_CPHY_SF_TWAKEUP_SHIFT				0U</div><div class='ctx'> #define CCS_CPHY_SF_TWAKEUP_MASK				0xf</div><div class='ctx'> #define CCS_CPHY_SF_TINIT_SHIFT					4U</div><div class='ctx'> #define CCS_CPHY_SF_TINIT_MASK					0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_1					0x165f</div><div class='add'>+#define CCS_R_DPHY_LIMITS_1					CCI_REG8(0x165f)</div><div class='ctx'> #define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT			0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK			0xf</div><div class='ctx'> #define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT			4U</div><div class='ctx'> #define CCS_DPHY_LIMITS_1_THS_ZERO_MASK				0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_2					0x1660</div><div class='add'>+#define CCS_R_DPHY_LIMITS_2					CCI_REG8(0x1660)</div><div class='ctx'> #define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT			0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK			0xf</div><div class='ctx'> #define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT			4U</div><div class='ctx'> #define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK			0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_3					0x1661</div><div class='add'>+#define CCS_R_DPHY_LIMITS_3					CCI_REG8(0x1661)</div><div class='ctx'> #define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT			0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK			0xf</div><div class='ctx'> #define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT			4U</div><div class='ctx'> #define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK			0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_4					0x1662</div><div class='add'>+#define CCS_R_DPHY_LIMITS_4					CCI_REG8(0x1662)</div><div class='ctx'> #define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT			0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_4_TCLK_POST_MASK			0xf</div><div class='ctx'> #define CCS_DPHY_LIMITS_4_TLPX_SHIFT				4U</div><div class='ctx'> #define CCS_DPHY_LIMITS_4_TLPX_MASK				0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_5					0x1663</div><div class='add'>+#define CCS_R_DPHY_LIMITS_5					CCI_REG8(0x1663)</div><div class='ctx'> #define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT			0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_5_THS_EXIT_MASK				0xf</div><div class='ctx'> #define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT				4U</div><div class='ctx'> #define CCS_DPHY_LIMITS_5_TWAKEUP_MASK				0xf0</div><div class='del'>-#define CCS_R_DPHY_LIMITS_6					0x1664</div><div class='add'>+#define CCS_R_DPHY_LIMITS_6					CCI_REG8(0x1664)</div><div class='ctx'> #define CCS_DPHY_LIMITS_6_TINIT_SHIFT				0U</div><div class='ctx'> #define CCS_DPHY_LIMITS_6_TINIT_MASK				0xf</div><div class='del'>-#define CCS_R_CPHY_LIMITS_1					0x1665</div><div class='add'>+#define CCS_R_CPHY_LIMITS_1					CCI_REG8(0x1665)</div><div class='ctx'> #define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT			0U</div><div class='ctx'> #define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK			0xf</div><div class='ctx'> #define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT			4U</div><div class='ctx'> #define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK			0xf0</div><div class='del'>-#define CCS_R_CPHY_LIMITS_2					0x1666</div><div class='add'>+#define CCS_R_CPHY_LIMITS_2					CCI_REG8(0x1666)</div><div class='ctx'> #define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT			0U</div><div class='ctx'> #define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK			0xf</div><div class='ctx'> #define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT			4U</div><div class='ctx'> #define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK			0xf0</div><div class='del'>-#define CCS_R_CPHY_LIMITS_3					0x1667</div><div class='add'>+#define CCS_R_CPHY_LIMITS_3					CCI_REG8(0x1667)</div><div class='ctx'> #define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT			0U</div><div class='ctx'> #define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK			0xf</div><div class='del'>-#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN			(0x1700 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN			(0x1702 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_LINE_LENGTH_PCK_BIN				(0x1704 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MAX_LINE_LENGTH_PCK_BIN				(0x1706 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_MIN_LINE_BLANKING_PCK_BIN				(0x1708 | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN			(0x170a | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN		(0x170c | CCS_FL_16BIT)</div><div class='del'>-#define CCS_R_BINNING_CAPABILITY				0x1710</div><div class='add'>+#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN			CCI_REG16(0x1700)</div><div class='add'>+#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN			CCI_REG16(0x1702)</div><div class='add'>+#define CCS_R_MIN_LINE_LENGTH_PCK_BIN				CCI_REG16(0x1704)</div><div class='add'>+#define CCS_R_MAX_LINE_LENGTH_PCK_BIN				CCI_REG16(0x1706)</div><div class='add'>+#define CCS_R_MIN_LINE_BLANKING_PCK_BIN				CCI_REG16(0x1708)</div><div class='add'>+#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN			CCI_REG16(0x170a)</div><div class='add'>+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN		CCI_REG16(0x170c)</div><div class='add'>+#define CCS_R_BINNING_CAPABILITY				CCI_REG8(0x1710)</div><div class='ctx'> #define CCS_BINNING_CAPABILITY_UNSUPPORTED			0U</div><div class='ctx'> #define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING		1U</div><div class='ctx'> #define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING		2U</div><div class='del'>-#define CCS_R_BINNING_WEIGHTING_CAPABILITY			0x1711</div><div class='add'>+#define CCS_R_BINNING_WEIGHTING_CAPABILITY			CCI_REG8(0x1711)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED		BIT(0)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED			BIT(1)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED	BIT(2)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT	BIT(3)</div><div class='del'>-#define CCS_R_BINNING_SUB_TYPES					0x1712</div><div class='del'>-#define CCS_R_BINNING_SUB_TYPE(n)				(0x1713 + (n))</div><div class='add'>+#define CCS_R_BINNING_SUB_TYPES					CCI_REG8(0x1712)</div><div class='add'>+#define CCS_R_BINNING_SUB_TYPE(n)				CCI_REG8(0x1713 + (n))</div><div class='ctx'> #define CCS_LIM_BINNING_SUB_TYPE_MIN_N				0U</div><div class='ctx'> #define CCS_LIM_BINNING_SUB_TYPE_MAX_N				63U</div><div class='ctx'> #define CCS_BINNING_SUB_TYPE_ROW_SHIFT				0U</div><div class='ctx'> #define CCS_BINNING_SUB_TYPE_ROW_MASK				0xf</div><div class='ctx'> #define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT			4U</div><div class='ctx'> #define CCS_BINNING_SUB_TYPE_COLUMN_MASK			0xf0</div><div class='del'>-#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY			0x1771</div><div class='add'>+#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY			CCI_REG8(0x1771)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED		BIT(0)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED		BIT(1)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED	BIT(2)</div><div class='ctx'> #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT   BIT(3)</div><div class='del'>-#define CCS_R_BINNING_SUB_TYPES_MONO				0x1772</div><div class='del'>-#define CCS_R_BINNING_SUB_TYPE_MONO(n)				(0x1773 + (n))</div><div class='add'>+#define CCS_R_BINNING_SUB_TYPES_MONO				CCI_REG8(0x1772)</div><div class='add'>+#define CCS_R_BINNING_SUB_TYPE_MONO(n)				CCI_REG8(0x1773 + (n))</div><div class='ctx'> #define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N			0U</div><div class='ctx'> #define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N			63U</div><div class='del'>-#define CCS_R_DATA_TRANSFER_IF_CAPABILITY			0x1800</div><div class='add'>+#define CCS_R_DATA_TRANSFER_IF_CAPABILITY			CCI_REG8(0x1800)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED		BIT(0)</div><div class='ctx'> #define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING			BIT(2)</div><div class='del'>-#define CCS_R_SHADING_CORRECTION_CAPABILITY			0x1900</div><div class='add'>+#define CCS_R_SHADING_CORRECTION_CAPABILITY			CCI_REG8(0x1900)</div><div class='ctx'> #define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING		BIT(0)</div><div class='ctx'> #define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION	BIT(1)</div><div class='del'>-#define CCS_R_GREEN_IMBALANCE_CAPABILITY			0x1901</div><div class='add'>+#define CCS_R_GREEN_IMBALANCE_CAPABILITY			CCI_REG8(0x1901)</div><div class='ctx'> #define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED		BIT(0)</div><div class='del'>-#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY		0x1903</div><div class='del'>-#define CCS_R_DEFECT_CORRECTION_CAPABILITY			(0x1904 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY		CCI_REG8(0x1903)</div><div class='add'>+#define CCS_R_DEFECT_CORRECTION_CAPABILITY			CCI_REG16(0x1904)</div><div class='ctx'> #define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT		BIT(0)</div><div class='ctx'> #define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET	BIT(2)</div><div class='ctx'> #define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE		BIT(5)</div><div class='ctx'> #define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC	BIT(8)</div><div class='del'>-#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2			(0x1906 | CCS_FL_16BIT)</div><div class='add'>+#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2			CCI_REG16(0x1906)</div><div class='ctx'> #define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET	BIT(3)</div><div class='del'>-#define CCS_R_NF_CAPABILITY					0x1908</div><div class='add'>+#define CCS_R_NF_CAPABILITY					CCI_REG8(0x1908)</div><div class='ctx'> #define CCS_NF_CAPABILITY_LUMA					BIT(0)</div><div class='ctx'> #define CCS_NF_CAPABILITY_CHROMA				BIT(1)</div><div class='ctx'> #define CCS_NF_CAPABILITY_COMBINED				BIT(2)</div><div class='del'>-#define CCS_R_OB_READOUT_CAPABILITY				0x1980</div><div class='add'>+#define CCS_R_OB_READOUT_CAPABILITY				CCI_REG8(0x1980)</div><div class='ctx'> #define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT		BIT(0)</div><div class='ctx'> #define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT		BIT(1)</div><div class='ctx'> #define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT		BIT(2)</div><div class='ctx'> #define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT		BIT(3)</div><div class='ctx'> #define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT		BIT(4)</div><div class='del'>-#define CCS_R_COLOR_FEEDBACK_CAPABILITY				0x1987</div><div class='add'>+#define CCS_R_COLOR_FEEDBACK_CAPABILITY				CCI_REG8(0x1987)</div><div class='ctx'> #define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN			BIT(0)</div><div class='ctx'> #define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN			BIT(1)</div><div class='del'>-#define CCS_R_CFA_PATTERN_CAPABILITY				0x1990</div><div class='add'>+#define CCS_R_CFA_PATTERN_CAPABILITY				CCI_REG8(0x1990)</div><div class='ctx'> #define CCS_CFA_PATTERN_CAPABILITY_BAYER			0U</div><div class='ctx'> #define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME			1U</div><div class='ctx'> #define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER		2U</div><div class='ctx'> #define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC		3U</div><div class='del'>-#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY			0x1991</div><div class='add'>+#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY			CCI_REG8(0x1991)</div><div class='ctx'> #define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER		BIT(0)</div><div class='del'>-#define CCS_R_FLASH_MODE_CAPABILITY				0x1a02</div><div class='add'>+#define CCS_R_FLASH_MODE_CAPABILITY				CCI_REG8(0x1a02)</div><div class='ctx'> #define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE			BIT(0)</div><div class='del'>-#define CCS_R_SA_STROBE_MODE_CAPABILITY				0x1a03</div><div class='add'>+#define CCS_R_SA_STROBE_MODE_CAPABILITY				CCI_REG8(0x1a03)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH		BIT(0)</div><div class='ctx'> #define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL			BIT(1)</div><div class='del'>-#define CCS_R_RESET_MAX_DELAY					0x1a10</div><div class='del'>-#define CCS_R_RESET_MIN_TIME					0x1a11</div><div class='del'>-#define CCS_R_PDAF_CAPABILITY_1					0x1b80</div><div class='add'>+#define CCS_R_RESET_MAX_DELAY					CCI_REG8(0x1a10)</div><div class='add'>+#define CCS_R_RESET_MIN_TIME					CCI_REG8(0x1a11)</div><div class='add'>+#define CCS_R_PDAF_CAPABILITY_1					CCI_REG8(0x1b80)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_SUPPORTED				BIT(0)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED		BIT(1)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED		BIT(2)</div><div class='hunk'>@@ -940,19 +940,19 @@</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION		BIT(5)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING			BIT(6)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING			BIT(7)</div><div class='del'>-#define CCS_R_PDAF_CAPABILITY_2					0x1b81</div><div class='add'>+#define CCS_R_PDAF_CAPABILITY_2					CCI_REG8(0x1b81)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_2_ROI				BIT(0)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP		BIT(1)</div><div class='ctx'> #define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED			BIT(2)</div><div class='del'>-#define CCS_R_BRACKETING_LUT_CAPABILITY_1			0x1c00</div><div class='add'>+#define CCS_R_BRACKETING_LUT_CAPABILITY_1			CCI_REG8(0x1c00)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION	BIT(0)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN	BIT(1)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH			BIT(4)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN	BIT(5)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN   BIT(6)</div><div class='del'>-#define CCS_R_BRACKETING_LUT_CAPABILITY_2			0x1c01</div><div class='add'>+#define CCS_R_BRACKETING_LUT_CAPABILITY_2			CCI_REG8(0x1c01)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE	BIT(0)</div><div class='ctx'> #define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE	BIT(1)</div><div class='del'>-#define CCS_R_BRACKETING_LUT_SIZE				0x1c02</div><div class='add'>+#define CCS_R_BRACKETING_LUT_SIZE				CCI_REG8(0x1c02)</div><div class='ctx'> </div><div class='ctx'> #endif /* __CCS_REGS_H__ */</div><div class='head'>diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h<br/>index 9c3587b2fbe7..096573845a10 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/ccs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/ccs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/ccs.h</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #define __CCS_H__</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-ctrls.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-subdev.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -211,6 +212,7 @@ struct ccs_sensor {</div><div class='ctx'> 	struct clk *ext_clk;</div><div class='ctx'> 	struct gpio_desc *xshutdown;</div><div class='ctx'> 	struct gpio_desc *reset;</div><div class='add'>+	struct regmap *regmap;</div><div class='ctx'> 	void *ccs_limits;</div><div class='ctx'> 	u8 nbinning_subtypes;</div><div class='ctx'> 	struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];</div><div class='hunk'>@@ -236,6 +238,7 @@ struct ccs_sensor {</div><div class='ctx'> </div><div class='ctx'> 	bool streaming;</div><div class='ctx'> 	bool dev_init_done;</div><div class='add'>+	bool handler_setup_needed;</div><div class='ctx'> 	u8 compressed_min_bpp;</div><div class='ctx'> </div><div class='ctx'> 	struct ccs_module_info minfo;</div><div class='head'>diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h<br/>index 177e3e51207a..ebd0f90e1092 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/smiapp-reg-defs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ccs/smiapp-reg-defs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ccs/smiapp-reg-defs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ccs/smiapp-reg-defs.h</a></div><div class='hunk'>@@ -12,481 +12,484 @@</div><div class='ctx'> #ifndef __SMIAPP_REG_DEFS_H__</div><div class='ctx'> #define __SMIAPP_REG_DEFS_H__</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+</div><div class='ctx'> /* Register addresses */</div><div class='del'>-#define SMIAPP_REG_U16_MODEL_ID					(0x0000 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR			0x0002</div><div class='del'>-#define SMIAPP_REG_U8_MANUFACTURER_ID				0x0003</div><div class='del'>-#define SMIAPP_REG_U8_SMIA_VERSION				0x0004</div><div class='del'>-#define SMIAPP_REG_U8_FRAME_COUNT				0x0005</div><div class='del'>-#define SMIAPP_REG_U8_PIXEL_ORDER				0x0006</div><div class='del'>-#define SMIAPP_REG_U16_DATA_PEDESTAL				(0x0008 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_PIXEL_DEPTH				0x000c</div><div class='del'>-#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR			0x0010</div><div class='del'>-#define SMIAPP_REG_U8_SMIAPP_VERSION				0x0011</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_DATE_YEAR				0x0012</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_DATE_MONTH				0x0013</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_DATE_DAY				0x0014</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_DATE_PHASE				0x0015</div><div class='del'>-#define SMIAPP_REG_U16_SENSOR_MODEL_ID				(0x0016 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER			0x0018</div><div class='del'>-#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID			0x0019</div><div class='del'>-#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION			0x001a</div><div class='del'>-#define SMIAPP_REG_U32_SERIAL_NUMBER				(0x001c | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE			0x0040</div><div class='del'>-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE		0x0041</div><div class='del'>-#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n)		((0x0042 + ((n) &lt;&lt; 1)) | CCS_FL_16BIT) /* 0 &lt;= n &lt;= 14 */</div><div class='del'>-#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n)		((0x0060 + ((n) &lt;&lt; 2)) | CCS_FL_32BIT) /* 0 &lt;= n &lt;= 7 */</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY			(0x0080 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN			(0x0084 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX			(0x0086 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP			(0x0088 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE			(0x008a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0				(0x008c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0				(0x008e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1				(0x0090 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1				(0x0092 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE			0x00c0</div><div class='del'>-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE			0x00c1</div><div class='del'>-#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n)		((0x00c2 + ((n) &lt;&lt; 1)) | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_MODE_SELECT				0x0100</div><div class='del'>-#define SMIAPP_REG_U8_IMAGE_ORIENTATION				0x0101</div><div class='del'>-#define SMIAPP_REG_U8_SOFTWARE_RESET				0x0103</div><div class='del'>-#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD			0x0104</div><div class='del'>-#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES			0x0105</div><div class='del'>-#define SMIAPP_REG_U8_FAST_STANDBY_CTRL				0x0106</div><div class='del'>-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL			0x0107</div><div class='del'>-#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL			0x0108</div><div class='del'>-#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL			0x0109</div><div class='del'>-#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER			0x0110</div><div class='del'>-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE			0x0111</div><div class='del'>-#define SMIAPP_REG_U16_CSI_DATA_FORMAT				(0x0112 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_CSI_LANE_MODE				0x0114</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_10_TO_8_DT				0x0115</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_10_TO_7_DT				0x0116</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_10_TO_6_DT				0x0117</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_12_TO_8_DT				0x0118</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_12_TO_7_DT				0x0119</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_12_TO_6_DT				0x011a</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_14_TO_10_DT				0x011b</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_14_TO_8_DT				0x011c</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_16_TO_10_DT				0x011d</div><div class='del'>-#define SMIAPP_REG_U8_CSI2_16_TO_8_DT				0x011e</div><div class='del'>-#define SMIAPP_REG_U8_GAIN_MODE					0x0120</div><div class='del'>-#define SMIAPP_REG_U16_VANA_VOLTAGE				(0x0130 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VDIG_VOLTAGE				(0x0132 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VIO_VOLTAGE				(0x0134 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ			(0x0136 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL			0x0138</div><div class='del'>-#define SMIAPP_REG_U8_TEMP_SENSOR_MODE				0x0139</div><div class='del'>-#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT			0x013a</div><div class='del'>-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME			(0x0200 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME			(0x0202 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL		(0x0204 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR		(0x0206 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED			(0x0208 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE			(0x020a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB		(0x020c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR			(0x020e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_RED				(0x0210 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE			(0x0212 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB			(0x0214 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VT_PIX_CLK_DIV				(0x0300 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VT_SYS_CLK_DIV				(0x0302 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV				(0x0304 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_PLL_MULTIPLIER				(0x0306 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_OP_PIX_CLK_DIV				(0x0308 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_OP_SYS_CLK_DIV				(0x030a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FRAME_LENGTH_LINES			(0x0340 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_LINE_LENGTH_PCK				(0x0342 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_ADDR_START				(0x0344 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_ADDR_START				(0x0346 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_ADDR_END				(0x0348 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_ADDR_END				(0x034a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_OUTPUT_SIZE				(0x034c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_OUTPUT_SIZE				(0x034e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_EVEN_INC				(0x0380 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_ODD_INC				(0x0382 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_EVEN_INC				(0x0384 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_ODD_INC				(0x0386 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALING_MODE				(0x0400 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SPATIAL_SAMPLING				(0x0402 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALE_M					(0x0404 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALE_N					(0x0406 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET			(0x0408 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET			(0x040a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH			(0x040c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT		(0x040e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_COMPRESSION_MODE				(0x0500 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TEST_PATTERN_MODE			(0x0600 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TEST_DATA_RED				(0x0602 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TEST_DATA_GREENR				(0x0604 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TEST_DATA_BLUE				(0x0606 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TEST_DATA_GREENB				(0x0608 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH			(0x060a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION		(0x060c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH			(0x060e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION			(0x0610 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS			(0x0700 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_TCLK_POST					0x0800</div><div class='del'>-#define SMIAPP_REG_U8_THS_PREPARE				0x0801</div><div class='del'>-#define SMIAPP_REG_U8_THS_ZERO_MIN				0x0802</div><div class='del'>-#define SMIAPP_REG_U8_THS_TRAIL					0x0803</div><div class='del'>-#define SMIAPP_REG_U8_TCLK_TRAIL_MIN				0x0804</div><div class='del'>-#define SMIAPP_REG_U8_TCLK_PREPARE				0x0805</div><div class='del'>-#define SMIAPP_REG_U8_TCLK_ZERO					0x0806</div><div class='del'>-#define SMIAPP_REG_U8_TLPX					0x0807</div><div class='del'>-#define SMIAPP_REG_U8_DPHY_CTRL					0x0808</div><div class='del'>-#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS		(0x0820 | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_MODE				0x0900</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_TYPE				0x0901</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_WEIGHTING				0x0902</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL			0x0a00</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS			0x0a01</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT		0x0a02</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0			0x0a04</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1			0x0a05</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2			0x0a06</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3			0x0a07</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4			0x0a08</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5			0x0a09</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12		0x0a10</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13		0x0a11</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14		0x0a12</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15		0x0a13</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16		0x0a14</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17		0x0a15</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18		0x0a16</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19		0x0a17</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20		0x0a18</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21		0x0a19</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22		0x0a1a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23		0x0a1b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24		0x0a1c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25		0x0a1d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26		0x0a1e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27		0x0a1f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28		0x0a20</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29		0x0a21</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30		0x0a22</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31		0x0a23</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32		0x0a24</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33		0x0a25</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34		0x0a26</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35		0x0a27</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36		0x0a28</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37		0x0a29</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38		0x0a2a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39		0x0a2b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40		0x0a2c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41		0x0a2d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42		0x0a2e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43		0x0a2f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44		0x0a30</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45		0x0a31</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46		0x0a32</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47		0x0a33</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48		0x0a34</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49		0x0a35</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50		0x0a36</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51		0x0a37</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52		0x0a38</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53		0x0a39</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54		0x0a3a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55		0x0a3b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56		0x0a3c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57		0x0a3d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58		0x0a3e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59		0x0a3f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60		0x0a40</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61		0x0a41</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62		0x0a42</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63		0x0a43</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL			0x0a44</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS			0x0a45</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT		0x0a46</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0			0x0a48</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1			0x0a49</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2			0x0a4a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3			0x0a4b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4			0x0a4c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5			0x0a4d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6			0x0a4e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7			0x0a4f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8			0x0a50</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9			0x0a51</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10		0x0a52</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11		0x0a53</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12		0x0a54</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13		0x0a55</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14		0x0a56</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15		0x0a57</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16		0x0a58</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17		0x0a59</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18		0x0a5a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19		0x0a5b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20		0x0a5c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21		0x0a5d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22		0x0a5e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23		0x0a5f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24		0x0a60</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25		0x0a61</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26		0x0a62</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27		0x0a63</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28		0x0a64</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29		0x0a65</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30		0x0a66</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31		0x0a67</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32		0x0a68</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33		0x0a69</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34		0x0a6a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35		0x0a6b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36		0x0a6c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37		0x0a6d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38		0x0a6e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39		0x0a6f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40		0x0a70</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41		0x0a71</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42		0x0a72</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43		0x0a73</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44		0x0a74</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45		0x0a75</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46		0x0a76</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47		0x0a77</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48		0x0a78</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49		0x0a79</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50		0x0a7a</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51		0x0a7b</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52		0x0a7c</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53		0x0a7d</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54		0x0a7e</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55		0x0a7f</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56		0x0a80</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57		0x0a81</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58		0x0a82</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59		0x0a83</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60		0x0a84</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61		0x0a85</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62		0x0a86</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63		0x0a87</div><div class='del'>-#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE			0x0b00</div><div class='del'>-#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL		0x0b01</div><div class='del'>-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE		0x0b02</div><div class='del'>-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT		0x0b03</div><div class='del'>-#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE		0x0b04</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE		0x0b05</div><div class='del'>-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE		0x0b06</div><div class='del'>-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT		0x0b07</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE		0x0b08</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT		0x0b09</div><div class='del'>-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE		0x0b0a</div><div class='del'>-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT		0x0b0b</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE		0x0b0c</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT		0x0b0d</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE		0x0b0e</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST		0x0b0f</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST		0x0b10</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE	0x0b11</div><div class='del'>-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST	0x0b12</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE	0x0b13</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST	0x0b14</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE	0x0b15</div><div class='del'>-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST	0x0b16</div><div class='del'>-#define SMIAPP_REG_U8_EDOF_MODE					0x0b80</div><div class='del'>-#define SMIAPP_REG_U8_SHARPNESS					0x0b83</div><div class='del'>-#define SMIAPP_REG_U8_DENOISING					0x0b84</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_SPECIFIC				0x0b85</div><div class='del'>-#define SMIAPP_REG_U16_DEPTH_OF_FIELD				(0x0b86 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_DISTANCE				(0x0b88 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL			0x0b8a</div><div class='del'>-#define SMIAPP_REG_U16_COLOUR_TEMPERATURE			(0x0b8c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR			(0x0b8e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED			(0x0b90 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE			(0x0b92 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB			(0x0b94 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE			0x0bc0</div><div class='del'>-#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING			(0x0bc2 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START			(0x0bc4 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START			(0x0bc6 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH			(0x0bc8 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT			(0x0bca | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1			0x0c00</div><div class='del'>-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2			0x0c01</div><div class='del'>-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1		0x0c02</div><div class='del'>-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2		0x0c03</div><div class='del'>-#define SMIAPP_REG_U16_TRDY_CTRL				(0x0c04 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TRDOUT_CTRL				(0x0c06 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL		(0x0c08 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL		(0x0c0a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL			(0x0c0c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL		(0x0c0e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL			(0x0c10 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT			0x0c12</div><div class='del'>-#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT			(0x0c14 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL		(0x0c16 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL		(0x0c18 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_FLASH_MODE_RS				0x0c1a</div><div class='del'>-#define SMIAPP_REG_U8_FLASH_TRIGGER_RS				0x0c1b</div><div class='del'>-#define SMIAPP_REG_U8_FLASH_STATUS				0x0c1c</div><div class='del'>-#define SMIAPP_REG_U8_SA_STROBE_MODE				0x0c1d</div><div class='del'>-#define SMIAPP_REG_U16_SA_STROBE_START_POINT			(0x0c1e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL			(0x0c20 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL			(0x0c22 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_SA_STROBE_TRIGGER				0x0c24</div><div class='del'>-#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS			0x0c25</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL	(0x0c26 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL		(0x0c28 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL		0x0c2a</div><div class='del'>-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL			0x0c2b</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL		(0x0c2c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL		(0x0c2e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_LOW_LEVEL_CTRL				0x0c80</div><div class='del'>-#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT			(0x0c82 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAIN_TRIGGER_T3				(0x0c84 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT			0x0c86</div><div class='del'>-#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3			(0x0c88 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT			0x0c8a</div><div class='del'>-#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3			(0x0c8c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT			0x0c8e</div><div class='del'>-#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL				0x0d00</div><div class='del'>-#define SMIAPP_REG_U8_OPERATION_MODE				0x0d01</div><div class='del'>-#define SMIAPP_REG_U8_ACT_STATE1				0x0d02</div><div class='del'>-#define SMIAPP_REG_U8_ACT_STATE2				0x0d03</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_CHANGE				(0x0d80 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL			(0x0d82 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1		(0x0d84 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2		(0x0d86 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1			0x0d88</div><div class='del'>-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2			0x0d89</div><div class='del'>-#define SMIAPP_REG_U8_POSITION					0x0d8a</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL			0x0e00</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_MODE			0x0e01</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL		0x0e02</div><div class='del'>-#define SMIAPP_REG_U8_LUT_PARAMETERS_START			0x0e10</div><div class='del'>-#define SMIAPP_REG_U8_LUT_PARAMETERS_END			0x0eff</div><div class='del'>-#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY		(0x1000 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN		(0x1004 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN	(0x1006 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN		(0x1008 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN		(0x100a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY			(0x1080 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN				(0x1084 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX				(0x1086 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE			(0x1088 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ			(0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ			(0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV			(0x1108 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV			(0x110a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ			(0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ			(0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER			(0x1114 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER			(0x1116 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ			(0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ			(0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV			(0x1120 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV			(0x1122 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ			(0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ			(0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ			(0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ			(0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV			(0x1134 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV			(0x1136 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES			(0x1140 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES			(0x1142 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK			(0x1144 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK			(0x1146 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK			(0x1148 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES			(0x114a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE		0x114c</div><div class='del'>-#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV			(0x1160 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV			(0x1162 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ			(0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ			(0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV			(0x116c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV			(0x116e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ			(0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ			(0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_ADDR_MIN				(0x1180 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_ADDR_MIN				(0x1182 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_X_ADDR_MAX				(0x1184 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_Y_ADDR_MAX				(0x1186 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE			(0x1188 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE			(0x118a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE			(0x118c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE			(0x118e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_EVEN_INC				(0x11c0 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_EVEN_INC				(0x11c2 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_ODD_INC				(0x11c4 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_ODD_INC				(0x11c6 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALING_CAPABILITY			(0x1200 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALER_M_MIN				(0x1204 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALER_M_MAX				(0x1206 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALER_N_MIN				(0x1208 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SCALER_N_MAX				(0x120a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY		(0x120c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY			0x120e</div><div class='del'>-#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY			(0x1300 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED			(0x1400 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED		(0x1402 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED			(0x1404 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN		(0x1406 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN		(0x1408 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN		(0x140a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE			(0x140c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE		(0x140e | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE		(0x1410 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS				(0x1500 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY			0x1502</div><div class='del'>-#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY			0x1600</div><div class='del'>-#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY			0x1601</div><div class='del'>-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY		0x1602</div><div class='del'>-#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY			0x1603</div><div class='del'>-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY		0x1604</div><div class='del'>-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS	(0x1608 | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS	(0x160c | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS	(0x1610 | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS	(0x1614 | CCS_FL_32BIT)</div><div class='del'>-#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY			0x1618</div><div class='del'>-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN		(0x1700 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN		(0x1702 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN			(0x1704 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN			(0x1706 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN		(0x1708 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN		(0x170a | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN	(0x170c | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_CAPABILITY			0x1710</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY		0x1711</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_SUBTYPES				0x1712</div><div class='del'>-#define SMIAPP_REG_U8_BINNING_TYPE_n(n)				(0x1713 + (n)) /* 1 &lt;= n &lt;= 237 */</div><div class='del'>-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY		0x1800</div><div class='del'>-#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY		0x1900</div><div class='del'>-#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY		0x1901</div><div class='del'>-#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY			0x1902</div><div class='del'>-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY	0x1903</div><div class='del'>-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY		(0x1904 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2		(0x1906 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_EDOF_CAPABILITY				0x1980</div><div class='del'>-#define SMIAPP_REG_U8_ESTIMATION_FRAMES				0x1981</div><div class='del'>-#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ			0x1982</div><div class='del'>-#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ			0x1983</div><div class='del'>-#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ		0x1984</div><div class='del'>-#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ		0x1985</div><div class='del'>-#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ		0x1986</div><div class='del'>-#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY		0x1987</div><div class='del'>-#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM			0x1988</div><div class='del'>-#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY		0x19c0</div><div class='del'>-#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY		0x19c1</div><div class='del'>-#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD			(0x19c2 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE			(0x19c4 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN			(0x1a00 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY			0x1a02</div><div class='del'>-#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR		(0x1b02 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY			0x1b04</div><div class='del'>-#define SMIAPP_REG_U16_ACTUATOR_TYPE				(0x1b40 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS				0x1b42</div><div class='del'>-#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS			(0x1b44 | CCS_FL_16BIT)</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1		0x1c00</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2		0x1c01</div><div class='del'>-#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE			0x1c02</div><div class='add'>+#define SMIAPP_REG_U16_MODEL_ID					CCI_REG16(0x0000)</div><div class='add'>+#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR			CCI_REG8(0x0002)</div><div class='add'>+#define SMIAPP_REG_U8_MANUFACTURER_ID				CCI_REG8(0x0003)</div><div class='add'>+#define SMIAPP_REG_U8_SMIA_VERSION				CCI_REG8(0x0004)</div><div class='add'>+#define SMIAPP_REG_U8_FRAME_COUNT				CCI_REG8(0x0005)</div><div class='add'>+#define SMIAPP_REG_U8_PIXEL_ORDER				CCI_REG8(0x0006)</div><div class='add'>+#define SMIAPP_REG_U16_DATA_PEDESTAL				CCI_REG16(0x0008)</div><div class='add'>+#define SMIAPP_REG_U8_PIXEL_DEPTH				CCI_REG8(0x000c)</div><div class='add'>+#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR			CCI_REG8(0x0010)</div><div class='add'>+#define SMIAPP_REG_U8_SMIAPP_VERSION				CCI_REG8(0x0011)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_DATE_YEAR				CCI_REG8(0x0012)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_DATE_MONTH				CCI_REG8(0x0013)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_DATE_DAY				CCI_REG8(0x0014)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_DATE_PHASE				CCI_REG8(0x0015)</div><div class='add'>+#define SMIAPP_REG_U16_SENSOR_MODEL_ID				CCI_REG16(0x0016)</div><div class='add'>+#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER			CCI_REG8(0x0018)</div><div class='add'>+#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID			CCI_REG8(0x0019)</div><div class='add'>+#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION			CCI_REG8(0x001a)</div><div class='add'>+#define SMIAPP_REG_U32_SERIAL_NUMBER				CCI_REG32(0x001c)</div><div class='add'>+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE			CCI_REG8(0x0040)</div><div class='add'>+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE		CCI_REG8(0x0041)</div><div class='add'>+#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n)		CCI_REG16(0x0042 + ((n) &lt;&lt; 1)) /* 0 &lt;= n &lt;= 14 */</div><div class='add'>+#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n)		CCI_REG32(0x0060 + ((n) &lt;&lt; 2)) /* 0 &lt;= n &lt;= 7 */</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY			CCI_REG16(0x0080)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN			CCI_REG16(0x0084)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX			CCI_REG16(0x0086)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP			CCI_REG16(0x0088)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE			CCI_REG16(0x008a)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0				CCI_REG16(0x008c)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0				CCI_REG16(0x008e)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1				CCI_REG16(0x0090)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1				CCI_REG16(0x0092)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE			CCI_REG8(0x00c0)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE			CCI_REG8(0x00c1)</div><div class='add'>+#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n)		CCI_REG16(0x00c2 + ((n) &lt;&lt; 1))</div><div class='add'>+#define SMIAPP_REG_U8_MODE_SELECT				CCI_REG8(0x0100)</div><div class='add'>+#define SMIAPP_REG_U8_IMAGE_ORIENTATION				CCI_REG8(0x0101)</div><div class='add'>+#define SMIAPP_REG_U8_SOFTWARE_RESET				CCI_REG8(0x0103)</div><div class='add'>+#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD			CCI_REG8(0x0104)</div><div class='add'>+#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES			CCI_REG8(0x0105)</div><div class='add'>+#define SMIAPP_REG_U8_FAST_STANDBY_CTRL				CCI_REG8(0x0106)</div><div class='add'>+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL			CCI_REG8(0x0107)</div><div class='add'>+#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL			CCI_REG8(0x0108)</div><div class='add'>+#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL			CCI_REG8(0x0109)</div><div class='add'>+#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER			CCI_REG8(0x0110)</div><div class='add'>+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE			CCI_REG8(0x0111)</div><div class='add'>+#define SMIAPP_REG_U16_CSI_DATA_FORMAT				CCI_REG16(0x0112)</div><div class='add'>+#define SMIAPP_REG_U8_CSI_LANE_MODE				CCI_REG8(0x0114)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_10_TO_8_DT				CCI_REG8(0x0115)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_10_TO_7_DT				CCI_REG8(0x0116)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_10_TO_6_DT				CCI_REG8(0x0117)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_12_TO_8_DT				CCI_REG8(0x0118)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_12_TO_7_DT				CCI_REG8(0x0119)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_12_TO_6_DT				CCI_REG8(0x011a)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_14_TO_10_DT				CCI_REG8(0x011b)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_14_TO_8_DT				CCI_REG8(0x011c)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_16_TO_10_DT				CCI_REG8(0x011d)</div><div class='add'>+#define SMIAPP_REG_U8_CSI2_16_TO_8_DT				CCI_REG8(0x011e)</div><div class='add'>+#define SMIAPP_REG_U8_GAIN_MODE					CCI_REG8(0x0120)</div><div class='add'>+#define SMIAPP_REG_U16_VANA_VOLTAGE				CCI_REG16(0x0130)</div><div class='add'>+#define SMIAPP_REG_U16_VDIG_VOLTAGE				CCI_REG16(0x0132)</div><div class='add'>+#define SMIAPP_REG_U16_VIO_VOLTAGE				CCI_REG16(0x0134)</div><div class='add'>+#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ			CCI_REG16(0x0136)</div><div class='add'>+#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL			CCI_REG8(0x0138)</div><div class='add'>+#define SMIAPP_REG_U8_TEMP_SENSOR_MODE				CCI_REG8(0x0139)</div><div class='add'>+#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT			CCI_REG8(0x013a)</div><div class='add'>+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME			CCI_REG16(0x0200)</div><div class='add'>+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME			CCI_REG16(0x0202)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL		CCI_REG16(0x0204)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR		CCI_REG16(0x0206)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED			CCI_REG16(0x0208)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE			CCI_REG16(0x020a)</div><div class='add'>+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB		CCI_REG16(0x020c)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR			CCI_REG16(0x020e)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_RED				CCI_REG16(0x0210)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE			CCI_REG16(0x0212)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB			CCI_REG16(0x0214)</div><div class='add'>+#define SMIAPP_REG_U16_VT_PIX_CLK_DIV				CCI_REG16(0x0300)</div><div class='add'>+#define SMIAPP_REG_U16_VT_SYS_CLK_DIV				CCI_REG16(0x0302)</div><div class='add'>+#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV				CCI_REG16(0x0304)</div><div class='add'>+#define SMIAPP_REG_U16_PLL_MULTIPLIER				CCI_REG16(0x0306)</div><div class='add'>+#define SMIAPP_REG_U16_OP_PIX_CLK_DIV				CCI_REG16(0x0308)</div><div class='add'>+#define SMIAPP_REG_U16_OP_SYS_CLK_DIV				CCI_REG16(0x030a)</div><div class='add'>+#define SMIAPP_REG_U16_FRAME_LENGTH_LINES			CCI_REG16(0x0340)</div><div class='add'>+#define SMIAPP_REG_U16_LINE_LENGTH_PCK				CCI_REG16(0x0342)</div><div class='add'>+#define SMIAPP_REG_U16_X_ADDR_START				CCI_REG16(0x0344)</div><div class='add'>+#define SMIAPP_REG_U16_Y_ADDR_START				CCI_REG16(0x0346)</div><div class='add'>+#define SMIAPP_REG_U16_X_ADDR_END				CCI_REG16(0x0348)</div><div class='add'>+#define SMIAPP_REG_U16_Y_ADDR_END				CCI_REG16(0x034a)</div><div class='add'>+#define SMIAPP_REG_U16_X_OUTPUT_SIZE				CCI_REG16(0x034c)</div><div class='add'>+#define SMIAPP_REG_U16_Y_OUTPUT_SIZE				CCI_REG16(0x034e)</div><div class='add'>+#define SMIAPP_REG_U16_X_EVEN_INC				CCI_REG16(0x0380)</div><div class='add'>+#define SMIAPP_REG_U16_X_ODD_INC				CCI_REG16(0x0382)</div><div class='add'>+#define SMIAPP_REG_U16_Y_EVEN_INC				CCI_REG16(0x0384)</div><div class='add'>+#define SMIAPP_REG_U16_Y_ODD_INC				CCI_REG16(0x0386)</div><div class='add'>+#define SMIAPP_REG_U16_SCALING_MODE				CCI_REG16(0x0400)</div><div class='add'>+#define SMIAPP_REG_U16_SPATIAL_SAMPLING				CCI_REG16(0x0402)</div><div class='add'>+#define SMIAPP_REG_U16_SCALE_M					CCI_REG16(0x0404)</div><div class='add'>+#define SMIAPP_REG_U16_SCALE_N					CCI_REG16(0x0406)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET			CCI_REG16(0x0408)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET			CCI_REG16(0x040a)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH			CCI_REG16(0x040c)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT		CCI_REG16(0x040e)</div><div class='add'>+#define SMIAPP_REG_U16_COMPRESSION_MODE				CCI_REG16(0x0500)</div><div class='add'>+#define SMIAPP_REG_U16_TEST_PATTERN_MODE			CCI_REG16(0x0600)</div><div class='add'>+#define SMIAPP_REG_U16_TEST_DATA_RED				CCI_REG16(0x0602)</div><div class='add'>+#define SMIAPP_REG_U16_TEST_DATA_GREENR				CCI_REG16(0x0604)</div><div class='add'>+#define SMIAPP_REG_U16_TEST_DATA_BLUE				CCI_REG16(0x0606)</div><div class='add'>+#define SMIAPP_REG_U16_TEST_DATA_GREENB				CCI_REG16(0x0608)</div><div class='add'>+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH			CCI_REG16(0x060a)</div><div class='add'>+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION		CCI_REG16(0x060c)</div><div class='add'>+#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH			CCI_REG16(0x060e)</div><div class='add'>+#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION			CCI_REG16(0x0610)</div><div class='add'>+#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS			CCI_REG16(0x0700)</div><div class='add'>+#define SMIAPP_REG_U8_TCLK_POST					CCI_REG8(0x0800)</div><div class='add'>+#define SMIAPP_REG_U8_THS_PREPARE				CCI_REG8(0x0801)</div><div class='add'>+#define SMIAPP_REG_U8_THS_ZERO_MIN				CCI_REG8(0x0802)</div><div class='add'>+#define SMIAPP_REG_U8_THS_TRAIL					CCI_REG8(0x0803)</div><div class='add'>+#define SMIAPP_REG_U8_TCLK_TRAIL_MIN				CCI_REG8(0x0804)</div><div class='add'>+#define SMIAPP_REG_U8_TCLK_PREPARE				CCI_REG8(0x0805)</div><div class='add'>+#define SMIAPP_REG_U8_TCLK_ZERO					CCI_REG8(0x0806)</div><div class='add'>+#define SMIAPP_REG_U8_TLPX					CCI_REG8(0x0807)</div><div class='add'>+#define SMIAPP_REG_U8_DPHY_CTRL					CCI_REG8(0x0808)</div><div class='add'>+#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS		CCI_REG32(0x0820)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_MODE				CCI_REG8(0x0900)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_TYPE				CCI_REG8(0x0901)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_WEIGHTING				CCI_REG8(0x0902)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL			CCI_REG8(0x0a00)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS			CCI_REG8(0x0a01)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT		CCI_REG8(0x0a02)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0			CCI_REG8(0x0a04)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1			CCI_REG8(0x0a05)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2			CCI_REG8(0x0a06)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3			CCI_REG8(0x0a07)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4			CCI_REG8(0x0a08)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5			CCI_REG8(0x0a09)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12		CCI_REG8(0x0a10)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13		CCI_REG8(0x0a11)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14		CCI_REG8(0x0a12)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15		CCI_REG8(0x0a13)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16		CCI_REG8(0x0a14)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17		CCI_REG8(0x0a15)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18		CCI_REG8(0x0a16)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19		CCI_REG8(0x0a17)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20		CCI_REG8(0x0a18)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21		CCI_REG8(0x0a19)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22		CCI_REG8(0x0a1a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23		CCI_REG8(0x0a1b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24		CCI_REG8(0x0a1c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25		CCI_REG8(0x0a1d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26		CCI_REG8(0x0a1e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27		CCI_REG8(0x0a1f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28		CCI_REG8(0x0a20)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29		CCI_REG8(0x0a21)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30		CCI_REG8(0x0a22)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31		CCI_REG8(0x0a23)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32		CCI_REG8(0x0a24)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33		CCI_REG8(0x0a25)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34		CCI_REG8(0x0a26)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35		CCI_REG8(0x0a27)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36		CCI_REG8(0x0a28)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37		CCI_REG8(0x0a29)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38		CCI_REG8(0x0a2a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39		CCI_REG8(0x0a2b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40		CCI_REG8(0x0a2c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41		CCI_REG8(0x0a2d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42		CCI_REG8(0x0a2e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43		CCI_REG8(0x0a2f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44		CCI_REG8(0x0a30)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45		CCI_REG8(0x0a31)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46		CCI_REG8(0x0a32)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47		CCI_REG8(0x0a33)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48		CCI_REG8(0x0a34)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49		CCI_REG8(0x0a35)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50		CCI_REG8(0x0a36)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51		CCI_REG8(0x0a37)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52		CCI_REG8(0x0a38)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53		CCI_REG8(0x0a39)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54		CCI_REG8(0x0a3a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55		CCI_REG8(0x0a3b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56		CCI_REG8(0x0a3c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57		CCI_REG8(0x0a3d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58		CCI_REG8(0x0a3e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59		CCI_REG8(0x0a3f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60		CCI_REG8(0x0a40)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61		CCI_REG8(0x0a41)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62		CCI_REG8(0x0a42)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63		CCI_REG8(0x0a43)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL			CCI_REG8(0x0a44)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS			CCI_REG8(0x0a45)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT		CCI_REG8(0x0a46)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0			CCI_REG8(0x0a48)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1			CCI_REG8(0x0a49)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2			CCI_REG8(0x0a4a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3			CCI_REG8(0x0a4b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4			CCI_REG8(0x0a4c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5			CCI_REG8(0x0a4d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6			CCI_REG8(0x0a4e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7			CCI_REG8(0x0a4f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8			CCI_REG8(0x0a50)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9			CCI_REG8(0x0a51)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10		CCI_REG8(0x0a52)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11		CCI_REG8(0x0a53)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12		CCI_REG8(0x0a54)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13		CCI_REG8(0x0a55)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14		CCI_REG8(0x0a56)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15		CCI_REG8(0x0a57)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16		CCI_REG8(0x0a58)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17		CCI_REG8(0x0a59)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18		CCI_REG8(0x0a5a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19		CCI_REG8(0x0a5b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20		CCI_REG8(0x0a5c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21		CCI_REG8(0x0a5d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22		CCI_REG8(0x0a5e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23		CCI_REG8(0x0a5f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24		CCI_REG8(0x0a60)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25		CCI_REG8(0x0a61)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26		CCI_REG8(0x0a62)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27		CCI_REG8(0x0a63)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28		CCI_REG8(0x0a64)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29		CCI_REG8(0x0a65)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30		CCI_REG8(0x0a66)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31		CCI_REG8(0x0a67)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32		CCI_REG8(0x0a68)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33		CCI_REG8(0x0a69)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34		CCI_REG8(0x0a6a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35		CCI_REG8(0x0a6b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36		CCI_REG8(0x0a6c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37		CCI_REG8(0x0a6d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38		CCI_REG8(0x0a6e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39		CCI_REG8(0x0a6f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40		CCI_REG8(0x0a70)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41		CCI_REG8(0x0a71)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42		CCI_REG8(0x0a72)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43		CCI_REG8(0x0a73)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44		CCI_REG8(0x0a74)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45		CCI_REG8(0x0a75)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46		CCI_REG8(0x0a76)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47		CCI_REG8(0x0a77)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48		CCI_REG8(0x0a78)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49		CCI_REG8(0x0a79)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50		CCI_REG8(0x0a7a)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51		CCI_REG8(0x0a7b)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52		CCI_REG8(0x0a7c)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53		CCI_REG8(0x0a7d)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54		CCI_REG8(0x0a7e)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55		CCI_REG8(0x0a7f)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56		CCI_REG8(0x0a80)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57		CCI_REG8(0x0a81)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58		CCI_REG8(0x0a82)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59		CCI_REG8(0x0a83)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60		CCI_REG8(0x0a84)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61		CCI_REG8(0x0a85)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62		CCI_REG8(0x0a86)</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63		CCI_REG8(0x0a87)</div><div class='add'>+#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE			CCI_REG8(0x0b00)</div><div class='add'>+#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL		CCI_REG8(0x0b01)</div><div class='add'>+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE		CCI_REG8(0x0b02)</div><div class='add'>+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT		CCI_REG8(0x0b03)</div><div class='add'>+#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE		CCI_REG8(0x0b04)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE		CCI_REG8(0x0b05)</div><div class='add'>+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE		CCI_REG8(0x0b06)</div><div class='add'>+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT		CCI_REG8(0x0b07)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE		CCI_REG8(0x0b08)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT		CCI_REG8(0x0b09)</div><div class='add'>+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE		CCI_REG8(0x0b0a)</div><div class='add'>+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT		CCI_REG8(0x0b0b)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE		CCI_REG8(0x0b0c)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT		CCI_REG8(0x0b0d)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE		CCI_REG8(0x0b0e)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST		CCI_REG8(0x0b0f)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST		CCI_REG8(0x0b10)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE	CCI_REG8(0x0b11)</div><div class='add'>+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST	CCI_REG8(0x0b12)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE	CCI_REG8(0x0b13)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST	CCI_REG8(0x0b14)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE	CCI_REG8(0x0b15)</div><div class='add'>+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST	CCI_REG8(0x0b16)</div><div class='add'>+#define SMIAPP_REG_U8_EDOF_MODE					CCI_REG8(0x0b80)</div><div class='add'>+#define SMIAPP_REG_U8_SHARPNESS					CCI_REG8(0x0b83)</div><div class='add'>+#define SMIAPP_REG_U8_DENOISING					CCI_REG8(0x0b84)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_SPECIFIC				CCI_REG8(0x0b85)</div><div class='add'>+#define SMIAPP_REG_U16_DEPTH_OF_FIELD				CCI_REG16(0x0b86)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_DISTANCE				CCI_REG16(0x0b88)</div><div class='add'>+#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL			CCI_REG8(0x0b8a)</div><div class='add'>+#define SMIAPP_REG_U16_COLOUR_TEMPERATURE			CCI_REG16(0x0b8c)</div><div class='add'>+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR			CCI_REG16(0x0b8e)</div><div class='add'>+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED			CCI_REG16(0x0b90)</div><div class='add'>+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE			CCI_REG16(0x0b92)</div><div class='add'>+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB			CCI_REG16(0x0b94)</div><div class='add'>+#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE			CCI_REG8(0x0bc0)</div><div class='add'>+#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING			CCI_REG16(0x0bc2)</div><div class='add'>+#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START			CCI_REG16(0x0bc4)</div><div class='add'>+#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START			CCI_REG16(0x0bc6)</div><div class='add'>+#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH			CCI_REG16(0x0bc8)</div><div class='add'>+#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT			CCI_REG16(0x0bca)</div><div class='add'>+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1			CCI_REG8(0x0c00)</div><div class='add'>+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2			CCI_REG8(0x0c01)</div><div class='add'>+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1		CCI_REG8(0x0c02)</div><div class='add'>+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2		CCI_REG8(0x0c03)</div><div class='add'>+#define SMIAPP_REG_U16_TRDY_CTRL				CCI_REG16(0x0c04)</div><div class='add'>+#define SMIAPP_REG_U16_TRDOUT_CTRL				CCI_REG16(0x0c06)</div><div class='add'>+#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL		CCI_REG16(0x0c08)</div><div class='add'>+#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL		CCI_REG16(0x0c0a)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL			CCI_REG16(0x0c0c)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL		CCI_REG16(0x0c0e)</div><div class='add'>+#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL			CCI_REG16(0x0c10)</div><div class='add'>+#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT			CCI_REG8(0x0c12)</div><div class='add'>+#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT			CCI_REG16(0x0c14)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL		CCI_REG16(0x0c16)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL		CCI_REG16(0x0c18)</div><div class='add'>+#define SMIAPP_REG_U8_FLASH_MODE_RS				CCI_REG8(0x0c1a)</div><div class='add'>+#define SMIAPP_REG_U8_FLASH_TRIGGER_RS				CCI_REG8(0x0c1b)</div><div class='add'>+#define SMIAPP_REG_U8_FLASH_STATUS				CCI_REG8(0x0c1c)</div><div class='add'>+#define SMIAPP_REG_U8_SA_STROBE_MODE				CCI_REG8(0x0c1d)</div><div class='add'>+#define SMIAPP_REG_U16_SA_STROBE_START_POINT			CCI_REG16(0x0c1e)</div><div class='add'>+#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL			CCI_REG16(0x0c20)</div><div class='add'>+#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL			CCI_REG16(0x0c22)</div><div class='add'>+#define SMIAPP_REG_U8_SA_STROBE_TRIGGER				CCI_REG8(0x0c24)</div><div class='add'>+#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS			CCI_REG8(0x0c25)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL	CCI_REG16(0x0c26)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL		CCI_REG16(0x0c28)</div><div class='add'>+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL		CCI_REG8(0x0c2a)</div><div class='add'>+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL			CCI_REG8(0x0c2b)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL		CCI_REG16(0x0c2c)</div><div class='add'>+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL		CCI_REG16(0x0c2e)</div><div class='add'>+#define SMIAPP_REG_U8_LOW_LEVEL_CTRL				CCI_REG8(0x0c80)</div><div class='add'>+#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT			CCI_REG16(0x0c82)</div><div class='add'>+#define SMIAPP_REG_U16_MAIN_TRIGGER_T3				CCI_REG16(0x0c84)</div><div class='add'>+#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT			CCI_REG8(0x0c86)</div><div class='add'>+#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3			CCI_REG16(0x0c88)</div><div class='add'>+#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT			CCI_REG8(0x0c8a)</div><div class='add'>+#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3			CCI_REG16(0x0c8c)</div><div class='add'>+#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT			CCI_REG8(0x0c8e)</div><div class='add'>+#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL				CCI_REG8(0x0d00)</div><div class='add'>+#define SMIAPP_REG_U8_OPERATION_MODE				CCI_REG8(0x0d01)</div><div class='add'>+#define SMIAPP_REG_U8_ACT_STATE1				CCI_REG8(0x0d02)</div><div class='add'>+#define SMIAPP_REG_U8_ACT_STATE2				CCI_REG8(0x0d03)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_CHANGE				CCI_REG16(0x0d80)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL			CCI_REG16(0x0d82)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1		CCI_REG16(0x0d84)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2		CCI_REG16(0x0d86)</div><div class='add'>+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1			CCI_REG8(0x0d88)</div><div class='add'>+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2			CCI_REG8(0x0d89)</div><div class='add'>+#define SMIAPP_REG_U8_POSITION					CCI_REG8(0x0d8a)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL			CCI_REG8(0x0e00)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_MODE			CCI_REG8(0x0e01)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL		CCI_REG8(0x0e02)</div><div class='add'>+#define SMIAPP_REG_U8_LUT_PARAMETERS_START			CCI_REG8(0x0e10)</div><div class='add'>+#define SMIAPP_REG_U8_LUT_PARAMETERS_END			CCI_REG8(0x0eff)</div><div class='add'>+#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY		CCI_REG16(0x1000)</div><div class='add'>+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN		CCI_REG16(0x1004)</div><div class='add'>+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN	CCI_REG16(0x1006)</div><div class='add'>+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN		CCI_REG16(0x1008)</div><div class='add'>+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN		CCI_REG16(0x100a)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY			CCI_REG16(0x1080)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN				CCI_REG16(0x1084)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX				CCI_REG16(0x1086)</div><div class='add'>+#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE			CCI_REG16(0x1088)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ			(CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ			(CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV			CCI_REG16(0x1108)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV			CCI_REG16(0x110a)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ			(CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ			(CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER			CCI_REG16(0x1114)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER			CCI_REG16(0x1116)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ			(CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ			(CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV			CCI_REG16(0x1120)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV			CCI_REG16(0x1122)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ			(CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ			(CCI_REG32(0x1128) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ			(CCI_REG32(0x112c) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ			(CCI_REG32(0x1130) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV			CCI_REG16(0x1134)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV			CCI_REG16(0x1136)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES			CCI_REG16(0x1140)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES			CCI_REG16(0x1142)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK			CCI_REG16(0x1144)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK			CCI_REG16(0x1146)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK			CCI_REG16(0x1148)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES			CCI_REG16(0x114a)</div><div class='add'>+#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE		CCI_REG8(0x114c)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV			CCI_REG16(0x1160)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV			CCI_REG16(0x1162)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ			(CCI_REG32(0x1164) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ			(CCI_REG32(0x1168) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV			CCI_REG16(0x116c)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV			CCI_REG16(0x116e)</div><div class='add'>+#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ			(CCI_REG32(0x1170) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ			(CCI_REG32(0x1174) | CCS_FL_FLOAT_IREAL)</div><div class='add'>+#define SMIAPP_REG_U16_X_ADDR_MIN				CCI_REG16(0x1180)</div><div class='add'>+#define SMIAPP_REG_U16_Y_ADDR_MIN				CCI_REG16(0x1182)</div><div class='add'>+#define SMIAPP_REG_U16_X_ADDR_MAX				CCI_REG16(0x1184)</div><div class='add'>+#define SMIAPP_REG_U16_Y_ADDR_MAX				CCI_REG16(0x1186)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE			CCI_REG16(0x1188)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE			CCI_REG16(0x118a)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE			CCI_REG16(0x118c)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE			CCI_REG16(0x118e)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_EVEN_INC				CCI_REG16(0x11c0)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_EVEN_INC				CCI_REG16(0x11c2)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_ODD_INC				CCI_REG16(0x11c4)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_ODD_INC				CCI_REG16(0x11c6)</div><div class='add'>+#define SMIAPP_REG_U16_SCALING_CAPABILITY			CCI_REG16(0x1200)</div><div class='add'>+#define SMIAPP_REG_U16_SCALER_M_MIN				CCI_REG16(0x1204)</div><div class='add'>+#define SMIAPP_REG_U16_SCALER_M_MAX				CCI_REG16(0x1206)</div><div class='add'>+#define SMIAPP_REG_U16_SCALER_N_MIN				CCI_REG16(0x1208)</div><div class='add'>+#define SMIAPP_REG_U16_SCALER_N_MAX				CCI_REG16(0x120a)</div><div class='add'>+#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY		CCI_REG16(0x120c)</div><div class='add'>+#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY			CCI_REG8(0x120e)</div><div class='add'>+#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY			CCI_REG16(0x1300)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED			CCI_REG16(0x1400)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED		CCI_REG16(0x1402)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED			CCI_REG16(0x1404)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN		CCI_REG16(0x1406)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN		CCI_REG16(0x1408)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN		CCI_REG16(0x140a)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE			CCI_REG16(0x140c)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE		CCI_REG16(0x140e)</div><div class='add'>+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE		CCI_REG16(0x1410)</div><div class='add'>+#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS				CCI_REG16(0x1500)</div><div class='add'>+#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY			CCI_REG8(0x1502)</div><div class='add'>+#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY			CCI_REG8(0x1600)</div><div class='add'>+#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY			CCI_REG8(0x1601)</div><div class='add'>+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY		CCI_REG8(0x1602)</div><div class='add'>+#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY			CCI_REG8(0x1603)</div><div class='add'>+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY		CCI_REG8(0x1604)</div><div class='add'>+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS	CCI_REG32(0x1608)</div><div class='add'>+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS	CCI_REG32(0x160c)</div><div class='add'>+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS	CCI_REG32(0x1610)</div><div class='add'>+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS	CCI_REG32(0x1614)</div><div class='add'>+#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY			CCI_REG8(0x1618)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN		CCI_REG16(0x1700)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN		CCI_REG16(0x1702)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN			CCI_REG16(0x1704)</div><div class='add'>+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN			CCI_REG16(0x1706)</div><div class='add'>+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN		CCI_REG16(0x1708)</div><div class='add'>+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN		CCI_REG16(0x170a)</div><div class='add'>+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN	CCI_REG16(0x170c)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_CAPABILITY			CCI_REG8(0x1710)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY		CCI_REG8(0x1711)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_SUBTYPES				CCI_REG8(0x1712)</div><div class='add'>+#define SMIAPP_REG_U8_BINNING_TYPE_n(n)				CCI_REG8(0x1713 + (n)) /* 1 &lt;= n &lt;= 237 */</div><div class='add'>+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY		CCI_REG8(0x1800)</div><div class='add'>+#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY		CCI_REG8(0x1900)</div><div class='add'>+#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY		CCI_REG8(0x1901)</div><div class='add'>+#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY			CCI_REG8(0x1902)</div><div class='add'>+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY	CCI_REG8(0x1903)</div><div class='add'>+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY		CCI_REG16(0x1904)</div><div class='add'>+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2		CCI_REG16(0x1906)</div><div class='add'>+#define SMIAPP_REG_U8_EDOF_CAPABILITY				CCI_REG8(0x1980)</div><div class='add'>+#define SMIAPP_REG_U8_ESTIMATION_FRAMES				CCI_REG8(0x1981)</div><div class='add'>+#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ			CCI_REG8(0x1982)</div><div class='add'>+#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ			CCI_REG8(0x1983)</div><div class='add'>+#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ		CCI_REG8(0x1984)</div><div class='add'>+#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ		CCI_REG8(0x1985)</div><div class='add'>+#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ		CCI_REG8(0x1986)</div><div class='add'>+#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY		CCI_REG8(0x1987)</div><div class='add'>+#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM			CCI_REG8(0x1988)</div><div class='add'>+#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY		CCI_REG8(0x19c0)</div><div class='add'>+#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY		CCI_REG8(0x19c1)</div><div class='add'>+#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD			CCI_REG16(0x19c2)</div><div class='add'>+#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE			CCI_REG16(0x19c4)</div><div class='add'>+#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN			CCI_REG16(0x1a00)</div><div class='add'>+#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY			CCI_REG8(0x1a02)</div><div class='add'>+#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR		CCI_REG16(0x1b02)</div><div class='add'>+#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY			CCI_REG8(0x1b04)</div><div class='add'>+#define SMIAPP_REG_U16_ACTUATOR_TYPE				CCI_REG16(0x1b40)</div><div class='add'>+#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS				CCI_REG8(0x1b42)</div><div class='add'>+#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS			CCI_REG16(0x1b44)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1		CCI_REG8(0x1c00)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2		CCI_REG8(0x1c01)</div><div class='add'>+#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE			CCI_REG8(0x1c02)</div><div class='ctx'> </div><div class='ctx'> /* Register bit definitions */</div><div class='ctx'> #define SMIAPP_IMAGE_ORIENTATION_HFLIP			BIT(0)</div><div class='head'>diff --git a/drivers/media/i2c/ds90ub913.c b/drivers/media/i2c/ds90ub913.c<br/>index 8e9ebed09f64..ca9bb29dab89 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub913.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ds90ub913.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub913.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub913.c</a></div><div class='hunk'>@@ -424,8 +424,7 @@ static int ub913_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set sink format */</div><div class='del'>-	fmt = v4l2_subdev_state_get_stream_format(state, format-&gt;pad,</div><div class='del'>-						  format-&gt;stream);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, format-&gt;pad, format-&gt;stream);</div><div class='ctx'> 	if (!fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -444,8 +443,8 @@ static int ub913_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ub913_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			  struct v4l2_subdev_state *state)</div><div class='add'>+static int ub913_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			    struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_route routes[] = {</div><div class='ctx'> 		{</div><div class='hunk'>@@ -504,7 +503,6 @@ static const struct v4l2_subdev_pad_ops ub913_pad_ops = {</div><div class='ctx'> 	.get_frame_desc = ub913_get_frame_desc,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = ub913_set_fmt,</div><div class='del'>-	.init_cfg = ub913_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ub913_subdev_ops = {</div><div class='hunk'>@@ -512,6 +510,10 @@ static const struct v4l2_subdev_ops ub913_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ub913_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ub913_internal_ops = {</div><div class='add'>+	.init_state = ub913_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ub913_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -745,6 +747,7 @@ static int ub913_subdev_init(struct ub913_data *priv)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;priv-&gt;sd, priv-&gt;client, &amp;ub913_subdev_ops);</div><div class='add'>+	priv-&gt;sd.internal_ops = &amp;ub913_internal_ops;</div><div class='ctx'> 	priv-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;</div><div class='ctx'> 	priv-&gt;sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='ctx'> 	priv-&gt;sd.entity.ops = &amp;ub913_entity_ops;</div><div class='head'>diff --git a/drivers/media/i2c/ds90ub953.c b/drivers/media/i2c/ds90ub953.c<br/>index 644022312833..16f88db14981 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub953.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ds90ub953.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub953.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub953.c</a></div><div class='hunk'>@@ -558,8 +558,7 @@ static int ub953_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		return v4l2_subdev_get_fmt(sd, state, format);</div><div class='ctx'> </div><div class='ctx'> 	/* Set sink format */</div><div class='del'>-	fmt = v4l2_subdev_state_get_stream_format(state, format-&gt;pad,</div><div class='del'>-						  format-&gt;stream);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, format-&gt;pad, format-&gt;stream);</div><div class='ctx'> 	if (!fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -576,8 +575,8 @@ static int ub953_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ub953_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			  struct v4l2_subdev_state *state)</div><div class='add'>+static int ub953_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			    struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_route routes[] = {</div><div class='ctx'> 		{</div><div class='hunk'>@@ -714,7 +713,6 @@ static const struct v4l2_subdev_pad_ops ub953_pad_ops = {</div><div class='ctx'> 	.get_frame_desc = ub953_get_frame_desc,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = ub953_set_fmt,</div><div class='del'>-	.init_cfg = ub953_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_core_ops ub953_subdev_core_ops = {</div><div class='hunk'>@@ -728,6 +726,10 @@ static const struct v4l2_subdev_ops ub953_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ub953_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ub953_internal_ops = {</div><div class='add'>+	.init_state = ub953_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ub953_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -1241,6 +1243,7 @@ static int ub953_subdev_init(struct ub953_data *priv)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;priv-&gt;sd, priv-&gt;client, &amp;ub953_subdev_ops);</div><div class='add'>+	priv-&gt;sd.internal_ops = &amp;ub953_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	priv-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 			  V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS;</div><div class='head'>diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c<br/>index b8f3e5ca03ef..ffe5f25f8647 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub960.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ds90ub960.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ds90ub960.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ds90ub960.c</a></div><div class='hunk'>@@ -2451,9 +2451,8 @@ static int ub960_configure_ports_for_streaming(struct ub960_data *priv,</div><div class='ctx'> 		if (rx_data[nport].num_streams &gt; 2)</div><div class='ctx'> 			return -EPIPE;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_state_get_stream_format(state,</div><div class='del'>-							  route-&gt;sink_pad,</div><div class='del'>-							  route-&gt;sink_stream);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(state, route-&gt;sink_pad,</div><div class='add'>+						   route-&gt;sink_stream);</div><div class='ctx'> 		if (!fmt)</div><div class='ctx'> 			return -EPIPE;</div><div class='ctx'> </div><div class='hunk'>@@ -2842,8 +2841,8 @@ static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,</div><div class='ctx'> 			const struct ub960_format_info *ub960_fmt;</div><div class='ctx'> 			struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-			fmt = v4l2_subdev_state_get_stream_format(state, pad,</div><div class='del'>-								  route-&gt;source_stream);</div><div class='add'>+			fmt = v4l2_subdev_state_get_format(state, pad,</div><div class='add'>+							   route-&gt;source_stream);</div><div class='ctx'> </div><div class='ctx'> 			if (!fmt) {</div><div class='ctx'> 				ret = -EINVAL;</div><div class='hunk'>@@ -2891,8 +2890,7 @@ static int ub960_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (!ub960_find_format(format-&gt;format.code))</div><div class='ctx'> 		format-&gt;format.code = ub960_formats[0].code;</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_state_get_stream_format(state, format-&gt;pad,</div><div class='del'>-						  format-&gt;stream);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, format-&gt;pad, format-&gt;stream);</div><div class='ctx'> 	if (!fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -2908,8 +2906,8 @@ static int ub960_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ub960_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			  struct v4l2_subdev_state *state)</div><div class='add'>+static int ub960_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			    struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct ub960_data *priv = sd_to_ub960(sd);</div><div class='ctx'> </div><div class='hunk'>@@ -2940,8 +2938,6 @@ static const struct v4l2_subdev_pad_ops ub960_pad_ops = {</div><div class='ctx'> </div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = ub960_set_fmt,</div><div class='del'>-</div><div class='del'>-	.init_cfg = ub960_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int ub960_log_status(struct v4l2_subdev *sd)</div><div class='hunk'>@@ -3093,6 +3089,10 @@ static const struct v4l2_subdev_core_ops ub960_subdev_core_ops = {</div><div class='ctx'> 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ub960_internal_ops = {</div><div class='add'>+	.init_state = ub960_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct v4l2_subdev_ops ub960_subdev_ops = {</div><div class='ctx'> 	.core = &amp;ub960_subdev_core_ops,</div><div class='ctx'> 	.pad = &amp;ub960_pad_ops,</div><div class='hunk'>@@ -3652,6 +3652,7 @@ static int ub960_create_subdev(struct ub960_data *priv)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;priv-&gt;sd, priv-&gt;client, &amp;ub960_subdev_ops);</div><div class='add'>+	priv-&gt;sd.internal_ops = &amp;ub960_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_ctrl_handler_init(&amp;priv-&gt;ctrl_handler, 1);</div><div class='ctx'> 	priv-&gt;sd.ctrl_handler = &amp;priv-&gt;ctrl_handler;</div><div class='head'>diff --git a/drivers/media/i2c/et8ek8/et8ek8_driver.c b/drivers/media/i2c/et8ek8/et8ek8_driver.c<br/>index d6fc843f9368..f548b1bb75fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/et8ek8/et8ek8_driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/et8ek8/et8ek8_driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/et8ek8/et8ek8_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/et8ek8/et8ek8_driver.c</a></div><div class='hunk'>@@ -995,8 +995,7 @@ __et8ek8_get_pad_format(struct et8ek8_sensor *sensor,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;sensor-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;sensor-&gt;format;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1047,10 +1046,18 @@ static int et8ek8_set_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int et8ek8_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct et8ek8_sensor *sensor = to_et8ek8_sensor(subdev);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	memset(fi, 0, sizeof(*fi));</div><div class='ctx'> 	fi-&gt;interval = sensor-&gt;current_reglist-&gt;mode.timeperframe;</div><div class='ctx'> </div><div class='hunk'>@@ -1058,11 +1065,19 @@ static int et8ek8_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int et8ek8_set_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct et8ek8_sensor *sensor = to_et8ek8_sensor(subdev);</div><div class='ctx'> 	struct et8ek8_reglist *reglist;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	reglist = et8ek8_reglist_find_mode_ival(&amp;meta_reglist,</div><div class='ctx'> 						sensor-&gt;current_reglist,</div><div class='ctx'> 						&amp;fi-&gt;interval);</div><div class='hunk'>@@ -1343,8 +1358,6 @@ static int et8ek8_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops et8ek8_video_ops = {</div><div class='ctx'> 	.s_stream = et8ek8_s_stream,</div><div class='del'>-	.g_frame_interval = et8ek8_get_frame_interval,</div><div class='del'>-	.s_frame_interval = et8ek8_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_core_ops et8ek8_core_ops = {</div><div class='hunk'>@@ -1357,6 +1370,8 @@ static const struct v4l2_subdev_pad_ops et8ek8_pad_ops = {</div><div class='ctx'> 	.enum_frame_interval = et8ek8_enum_frame_ival,</div><div class='ctx'> 	.get_fmt = et8ek8_get_pad_format,</div><div class='ctx'> 	.set_fmt = et8ek8_set_pad_format,</div><div class='add'>+	.get_frame_interval = et8ek8_get_frame_interval,</div><div class='add'>+	.set_frame_interval = et8ek8_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops et8ek8_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/gc0308.c b/drivers/media/i2c/gc0308.c<br/>new file mode 100644<br/>index 000000000000..fa754a8a39a6<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/gc0308.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/gc0308.c</a></div><div class='hunk'>@@ -0,0 +1,1451 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for the GalaxyCore GC0308 camera sensor.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Sebastian Reichel &lt;sre@kernel.org&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+/* Analog &amp; CISCTL*/</div><div class='add'>+#define GC0308_CHIP_ID			CCI_REG8(0x000)</div><div class='add'>+#define GC0308_HBLANK			CCI_REG8(0x001)</div><div class='add'>+#define GC0308_VBLANK			CCI_REG8(0x002)</div><div class='add'>+#define GC0308_EXP			CCI_REG16(0x003)</div><div class='add'>+#define GC0308_ROW_START		CCI_REG16(0x005)</div><div class='add'>+#define GC0308_COL_START		CCI_REG16(0x007)</div><div class='add'>+#define GC0308_WIN_HEIGHT		CCI_REG16(0x009)</div><div class='add'>+#define GC0308_WIN_WIDTH		CCI_REG16(0x00b)</div><div class='add'>+#define GC0308_VS_START_TIME		CCI_REG8(0x00d) /* in rows */</div><div class='add'>+#define GC0308_VS_END_TIME		CCI_REG8(0x00e) /* in rows */</div><div class='add'>+#define GC0308_VB_HB			CCI_REG8(0x00f)</div><div class='add'>+#define GC0308_RSH_WIDTH		CCI_REG8(0x010)</div><div class='add'>+#define GC0308_TSP_WIDTH		CCI_REG8(0x011)</div><div class='add'>+#define GC0308_SAMPLE_HOLD_DELAY	CCI_REG8(0x012)</div><div class='add'>+#define GC0308_ROW_TAIL_WIDTH		CCI_REG8(0x013)</div><div class='add'>+#define GC0308_CISCTL_MODE1		CCI_REG8(0x014)</div><div class='add'>+#define GC0308_CISCTL_MODE2		CCI_REG8(0x015)</div><div class='add'>+#define GC0308_CISCTL_MODE3		CCI_REG8(0x016)</div><div class='add'>+#define GC0308_CISCTL_MODE4		CCI_REG8(0x017)</div><div class='add'>+#define GC0308_ANALOG_MODE1		CCI_REG8(0x01a)</div><div class='add'>+#define GC0308_ANALOG_MODE2		CCI_REG8(0x01b)</div><div class='add'>+#define GC0308_HRST_RSG_V18		CCI_REG8(0x01c)</div><div class='add'>+#define GC0308_VREF_V25			CCI_REG8(0x01d)</div><div class='add'>+#define GC0308_ADC_R			CCI_REG8(0x01e)</div><div class='add'>+#define GC0308_PAD_DRV			CCI_REG8(0x01f)</div><div class='add'>+#define GC0308_SOFT_RESET		CCI_REG8(0x0fe)</div><div class='add'>+</div><div class='add'>+/* ISP */</div><div class='add'>+#define GC0308_BLOCK_EN1		CCI_REG8(0x020)</div><div class='add'>+#define GC0308_BLOCK_EN2		CCI_REG8(0x021)</div><div class='add'>+#define GC0308_AAAA_EN			CCI_REG8(0x022)</div><div class='add'>+#define GC0308_SPECIAL_EFFECT		CCI_REG8(0x023)</div><div class='add'>+#define GC0308_OUT_FORMAT		CCI_REG8(0x024)</div><div class='add'>+#define GC0308_OUT_EN			CCI_REG8(0x025)</div><div class='add'>+#define GC0308_SYNC_MODE		CCI_REG8(0x026)</div><div class='add'>+#define GC0308_CLK_DIV_MODE		CCI_REG8(0x028)</div><div class='add'>+#define GC0308_BYPASS_MODE		CCI_REG8(0x029)</div><div class='add'>+#define GC0308_CLK_GATING		CCI_REG8(0x02a)</div><div class='add'>+#define GC0308_DITHER_MODE		CCI_REG8(0x02b)</div><div class='add'>+#define GC0308_DITHER_BIT		CCI_REG8(0x02c)</div><div class='add'>+#define GC0308_DEBUG_MODE1		CCI_REG8(0x02d)</div><div class='add'>+#define GC0308_DEBUG_MODE2		CCI_REG8(0x02e)</div><div class='add'>+#define GC0308_DEBUG_MODE3		CCI_REG8(0x02f)</div><div class='add'>+#define GC0308_CROP_WIN_MODE		CCI_REG8(0x046)</div><div class='add'>+#define GC0308_CROP_WIN_Y1		CCI_REG8(0x047)</div><div class='add'>+#define GC0308_CROP_WIN_X1		CCI_REG8(0x048)</div><div class='add'>+#define GC0308_CROP_WIN_HEIGHT		CCI_REG16(0x049)</div><div class='add'>+#define GC0308_CROP_WIN_WIDTH		CCI_REG16(0x04b)</div><div class='add'>+</div><div class='add'>+/* BLK */</div><div class='add'>+#define GC0308_BLK_MODE			CCI_REG8(0x030)</div><div class='add'>+#define GC0308_BLK_LIMIT_VAL		CCI_REG8(0x031)</div><div class='add'>+#define GC0308_GLOBAL_OFF		CCI_REG8(0x032)</div><div class='add'>+#define GC0308_CURRENT_R_OFF		CCI_REG8(0x033)</div><div class='add'>+#define GC0308_CURRENT_G_OFF		CCI_REG8(0x034)</div><div class='add'>+#define GC0308_CURRENT_B_OFF		CCI_REG8(0x035)</div><div class='add'>+#define GC0308_CURRENT_R_DARK_CURRENT	CCI_REG8(0x036)</div><div class='add'>+#define GC0308_CURRENT_G_DARK_CURRENT	CCI_REG8(0x037)</div><div class='add'>+#define GC0308_CURRENT_B_DARK_CURRENT	CCI_REG8(0x038)</div><div class='add'>+#define GC0308_EXP_RATE_DARKC		CCI_REG8(0x039)</div><div class='add'>+#define GC0308_OFF_SUBMODE		CCI_REG8(0x03a)</div><div class='add'>+#define GC0308_DARKC_SUBMODE		CCI_REG8(0x03b)</div><div class='add'>+#define GC0308_MANUAL_G1_OFF		CCI_REG8(0x03c)</div><div class='add'>+#define GC0308_MANUAL_R1_OFF		CCI_REG8(0x03d)</div><div class='add'>+#define GC0308_MANUAL_B2_OFF		CCI_REG8(0x03e)</div><div class='add'>+#define GC0308_MANUAL_G2_OFF		CCI_REG8(0x03f)</div><div class='add'>+</div><div class='add'>+/* PREGAIN */</div><div class='add'>+#define GC0308_GLOBAL_GAIN		CCI_REG8(0x050)</div><div class='add'>+#define GC0308_AUTO_PREGAIN		CCI_REG8(0x051)</div><div class='add'>+#define GC0308_AUTO_POSTGAIN		CCI_REG8(0x052)</div><div class='add'>+#define GC0308_CHANNEL_GAIN_G1		CCI_REG8(0x053)</div><div class='add'>+#define GC0308_CHANNEL_GAIN_R		CCI_REG8(0x054)</div><div class='add'>+#define GC0308_CHANNEL_GAIN_B		CCI_REG8(0x055)</div><div class='add'>+#define GC0308_CHANNEL_GAIN_G2		CCI_REG8(0x056)</div><div class='add'>+#define GC0308_R_RATIO			CCI_REG8(0x057)</div><div class='add'>+#define GC0308_G_RATIO			CCI_REG8(0x058)</div><div class='add'>+#define GC0308_B_RATIO			CCI_REG8(0x059)</div><div class='add'>+#define GC0308_AWB_R_GAIN		CCI_REG8(0x05a)</div><div class='add'>+#define GC0308_AWB_G_GAIN		CCI_REG8(0x05b)</div><div class='add'>+#define GC0308_AWB_B_GAIN		CCI_REG8(0x05c)</div><div class='add'>+#define GC0308_LSC_DEC_LVL1		CCI_REG8(0x05d)</div><div class='add'>+#define GC0308_LSC_DEC_LVL2		CCI_REG8(0x05e)</div><div class='add'>+#define GC0308_LSC_DEC_LVL3		CCI_REG8(0x05f)</div><div class='add'>+</div><div class='add'>+/* DNDD */</div><div class='add'>+#define GC0308_DN_MODE_EN		CCI_REG8(0x060)</div><div class='add'>+#define GC0308_DN_MODE_RATIO		CCI_REG8(0x061)</div><div class='add'>+#define GC0308_DN_BILAT_B_BASE		CCI_REG8(0x062)</div><div class='add'>+#define GC0308_DN_B_INCR		CCI_REG8(0x063)</div><div class='add'>+#define GC0308_DN_BILAT_N_BASE		CCI_REG8(0x064)</div><div class='add'>+#define GC0308_DN_N_INCR		CCI_REG8(0x065)</div><div class='add'>+#define GC0308_DD_DARK_BRIGHT_TH	CCI_REG8(0x066)</div><div class='add'>+#define GC0308_DD_FLAT_TH		CCI_REG8(0x067)</div><div class='add'>+#define GC0308_DD_LIMIT			CCI_REG8(0x068)</div><div class='add'>+</div><div class='add'>+/* ASDE - Auto Saturation De-noise and Edge-Enhancement */</div><div class='add'>+#define GC0308_ASDE_GAIN_TRESH		CCI_REG8(0x069)</div><div class='add'>+#define GC0308_ASDE_GAIN_MODE		CCI_REG8(0x06a)</div><div class='add'>+#define GC0308_ASDE_DN_SLOPE		CCI_REG8(0x06b)</div><div class='add'>+#define GC0308_ASDE_DD_BRIGHT		CCI_REG8(0x06c)</div><div class='add'>+#define GC0308_ASDE_DD_LIMIT		CCI_REG8(0x06d)</div><div class='add'>+#define GC0308_ASDE_AUTO_EE1		CCI_REG8(0x06e)</div><div class='add'>+#define GC0308_ASDE_AUTO_EE2		CCI_REG8(0x06f)</div><div class='add'>+#define GC0308_ASDE_AUTO_SAT_DEC_SLOPE	CCI_REG8(0x070)</div><div class='add'>+#define GC0308_ASDE_AUTO_SAT_LOW_LIMIT	CCI_REG8(0x071)</div><div class='add'>+</div><div class='add'>+/* INTPEE - Interpolation and Edge-Enhancement */</div><div class='add'>+#define GC0308_EEINTP_MODE_1		CCI_REG8(0x072)</div><div class='add'>+#define GC0308_EEINTP_MODE_2		CCI_REG8(0x073)</div><div class='add'>+#define GC0308_DIRECTION_TH1		CCI_REG8(0x074)</div><div class='add'>+#define GC0308_DIRECTION_TH2		CCI_REG8(0x075)</div><div class='add'>+#define GC0308_DIFF_HV_TI_TH		CCI_REG8(0x076)</div><div class='add'>+#define GC0308_EDGE12_EFFECT		CCI_REG8(0x077)</div><div class='add'>+#define GC0308_EDGE_POS_RATIO		CCI_REG8(0x078)</div><div class='add'>+#define GC0308_EDGE1_MINMAX		CCI_REG8(0x079)</div><div class='add'>+#define GC0308_EDGE2_MINMAX		CCI_REG8(0x07a)</div><div class='add'>+#define GC0308_EDGE12_TH		CCI_REG8(0x07b)</div><div class='add'>+#define GC0308_EDGE_MAX			CCI_REG8(0x07c)</div><div class='add'>+</div><div class='add'>+/* ABB - Auto Black Balance */</div><div class='add'>+#define GC0308_ABB_MODE			CCI_REG8(0x080)</div><div class='add'>+#define GC0308_ABB_TARGET_AVGH		CCI_REG8(0x081)</div><div class='add'>+#define GC0308_ABB_TARGET_AVGL		CCI_REG8(0x082)</div><div class='add'>+#define GC0308_ABB_LIMIT_VAL		CCI_REG8(0x083)</div><div class='add'>+#define GC0308_ABB_SPEED		CCI_REG8(0x084)</div><div class='add'>+#define GC0308_CURR_R_BLACK_LVL		CCI_REG8(0x085)</div><div class='add'>+#define GC0308_CURR_G_BLACK_LVL		CCI_REG8(0x086)</div><div class='add'>+#define GC0308_CURR_B_BLACK_LVL		CCI_REG8(0x087)</div><div class='add'>+#define GC0308_CURR_R_BLACK_FACTOR	CCI_REG8(0x088)</div><div class='add'>+#define GC0308_CURR_G_BLACK_FACTOR	CCI_REG8(0x089)</div><div class='add'>+#define GC0308_CURR_B_BLACK_FACTOR	CCI_REG8(0x08a)</div><div class='add'>+</div><div class='add'>+/* LSC - Lens Shading Correction */</div><div class='add'>+#define GC0308_LSC_RED_B2		CCI_REG8(0x08b)</div><div class='add'>+#define GC0308_LSC_GREEN_B2		CCI_REG8(0x08c)</div><div class='add'>+#define GC0308_LSC_BLUE_B2		CCI_REG8(0x08d)</div><div class='add'>+#define GC0308_LSC_RED_B4		CCI_REG8(0x08e)</div><div class='add'>+#define GC0308_LSC_GREEN_B4		CCI_REG8(0x08f)</div><div class='add'>+#define GC0308_LSC_BLUE_B4		CCI_REG8(0x090)</div><div class='add'>+#define GC0308_LSC_ROW_CENTER		CCI_REG8(0x091)</div><div class='add'>+#define GC0308_LSC_COL_CENTER		CCI_REG8(0x092)</div><div class='add'>+</div><div class='add'>+/* CC - Channel Coefficient */</div><div class='add'>+#define GC0308_CC_MATRIX_C11		CCI_REG8(0x093)</div><div class='add'>+#define GC0308_CC_MATRIX_C12		CCI_REG8(0x094)</div><div class='add'>+#define GC0308_CC_MATRIX_C13		CCI_REG8(0x095)</div><div class='add'>+#define GC0308_CC_MATRIX_C21		CCI_REG8(0x096)</div><div class='add'>+#define GC0308_CC_MATRIX_C22		CCI_REG8(0x097)</div><div class='add'>+#define GC0308_CC_MATRIX_C23		CCI_REG8(0x098)</div><div class='add'>+#define GC0308_CC_MATRIX_C41		CCI_REG8(0x09c)</div><div class='add'>+#define GC0308_CC_MATRIX_C42		CCI_REG8(0x09d)</div><div class='add'>+#define GC0308_CC_MATRIX_C43		CCI_REG8(0x09e)</div><div class='add'>+</div><div class='add'>+/* GAMMA */</div><div class='add'>+#define GC0308_GAMMA_OUT0		CCI_REG8(0x09f)</div><div class='add'>+#define GC0308_GAMMA_OUT1		CCI_REG8(0x0a0)</div><div class='add'>+#define GC0308_GAMMA_OUT2		CCI_REG8(0x0a1)</div><div class='add'>+#define GC0308_GAMMA_OUT3		CCI_REG8(0x0a2)</div><div class='add'>+#define GC0308_GAMMA_OUT4		CCI_REG8(0x0a3)</div><div class='add'>+#define GC0308_GAMMA_OUT5		CCI_REG8(0x0a4)</div><div class='add'>+#define GC0308_GAMMA_OUT6		CCI_REG8(0x0a5)</div><div class='add'>+#define GC0308_GAMMA_OUT7		CCI_REG8(0x0a6)</div><div class='add'>+#define GC0308_GAMMA_OUT8		CCI_REG8(0x0a7)</div><div class='add'>+#define GC0308_GAMMA_OUT9		CCI_REG8(0x0a8)</div><div class='add'>+#define GC0308_GAMMA_OUT10		CCI_REG8(0x0a9)</div><div class='add'>+#define GC0308_GAMMA_OUT11		CCI_REG8(0x0aa)</div><div class='add'>+#define GC0308_GAMMA_OUT12		CCI_REG8(0x0ab)</div><div class='add'>+#define GC0308_GAMMA_OUT13		CCI_REG8(0x0ac)</div><div class='add'>+#define GC0308_GAMMA_OUT14		CCI_REG8(0x0ad)</div><div class='add'>+#define GC0308_GAMMA_OUT15		CCI_REG8(0x0ae)</div><div class='add'>+#define GC0308_GAMMA_OUT16		CCI_REG8(0x0af)</div><div class='add'>+</div><div class='add'>+/* YCP */</div><div class='add'>+#define GC0308_GLOBAL_SATURATION	CCI_REG8(0x0b0)</div><div class='add'>+#define GC0308_SATURATION_CB		CCI_REG8(0x0b1)</div><div class='add'>+#define GC0308_SATURATION_CR		CCI_REG8(0x0b2)</div><div class='add'>+#define GC0308_LUMA_CONTRAST		CCI_REG8(0x0b3)</div><div class='add'>+#define GC0308_CONTRAST_CENTER		CCI_REG8(0x0b4)</div><div class='add'>+#define GC0308_LUMA_OFFSET		CCI_REG8(0x0b5)</div><div class='add'>+#define GC0308_SKIN_CB_CENTER		CCI_REG8(0x0b6)</div><div class='add'>+#define GC0308_SKIN_CR_CENTER		CCI_REG8(0x0b7)</div><div class='add'>+#define GC0308_SKIN_RADIUS_SQUARE	CCI_REG8(0x0b8)</div><div class='add'>+#define GC0308_SKIN_BRIGHTNESS		CCI_REG8(0x0b9)</div><div class='add'>+#define GC0308_FIXED_CB			CCI_REG8(0x0ba)</div><div class='add'>+#define GC0308_FIXED_CR			CCI_REG8(0x0bb)</div><div class='add'>+#define GC0308_EDGE_DEC_SA		CCI_REG8(0x0bd)</div><div class='add'>+#define GC0308_AUTO_GRAY_MODE		CCI_REG8(0x0be)</div><div class='add'>+#define GC0308_SATURATION_SUB_STRENGTH	CCI_REG8(0x0bf)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT0		CCI_REG8(0x0c0)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT1		CCI_REG8(0x0c1)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT2		CCI_REG8(0x0c2)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT3		CCI_REG8(0x0c3)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT4		CCI_REG8(0x0c4)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT5		CCI_REG8(0x0c5)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT6		CCI_REG8(0x0c6)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT7		CCI_REG8(0x0c7)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT8		CCI_REG8(0x0c8)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT9		CCI_REG8(0x0c9)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT10		CCI_REG8(0x0ca)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT11		CCI_REG8(0x0cb)</div><div class='add'>+#define GC0308_Y_GAMMA_OUT12		CCI_REG8(0x0cc)</div><div class='add'>+</div><div class='add'>+/* AEC - Automatic Exposure Control */</div><div class='add'>+#define GC0308_AEC_MODE1		CCI_REG8(0x0d0)</div><div class='add'>+#define GC0308_AEC_MODE2		CCI_REG8(0x0d1)</div><div class='add'>+#define GC0308_AEC_MODE3		CCI_REG8(0x0d2)</div><div class='add'>+#define GC0308_AEC_TARGET_Y		CCI_REG8(0x0d3)</div><div class='add'>+#define GC0308_Y_AVG			CCI_REG8(0x0d4)</div><div class='add'>+#define GC0308_AEC_HIGH_LOW_RANGE	CCI_REG8(0x0d5)</div><div class='add'>+#define GC0308_AEC_IGNORE		CCI_REG8(0x0d6)</div><div class='add'>+#define GC0308_AEC_LIMIT_HIGH_RANGE	CCI_REG8(0x0d7)</div><div class='add'>+#define GC0308_AEC_R_OFFSET		CCI_REG8(0x0d9)</div><div class='add'>+#define GC0308_AEC_GB_OFFSET		CCI_REG8(0x0da)</div><div class='add'>+#define GC0308_AEC_SLOW_MARGIN		CCI_REG8(0x0db)</div><div class='add'>+#define GC0308_AEC_FAST_MARGIN		CCI_REG8(0x0dc)</div><div class='add'>+#define GC0308_AEC_EXP_CHANGE_GAIN	CCI_REG8(0x0dd)</div><div class='add'>+#define GC0308_AEC_STEP2_SUNLIGHT	CCI_REG8(0x0de)</div><div class='add'>+#define GC0308_AEC_I_FRAMES		CCI_REG8(0x0df)</div><div class='add'>+#define GC0308_AEC_I_STOP_L_MARGIN	CCI_REG8(0x0e0)</div><div class='add'>+#define GC0308_AEC_I_STOP_MARGIN	CCI_REG8(0x0e1)</div><div class='add'>+#define GC0308_ANTI_FLICKER_STEP	CCI_REG16(0x0e2)</div><div class='add'>+#define GC0308_EXP_LVL_1		CCI_REG16(0x0e4)</div><div class='add'>+#define GC0308_EXP_LVL_2		CCI_REG16(0x0e6)</div><div class='add'>+#define GC0308_EXP_LVL_3		CCI_REG16(0x0e8)</div><div class='add'>+#define GC0308_EXP_LVL_4		CCI_REG16(0x0ea)</div><div class='add'>+#define GC0308_MAX_EXP_LVL		CCI_REG8(0x0ec)</div><div class='add'>+#define GC0308_EXP_MIN_L		CCI_REG8(0x0ed)</div><div class='add'>+#define GC0308_MAX_POST_DF_GAIN		CCI_REG8(0x0ee)</div><div class='add'>+#define GC0308_MAX_PRE_DG_GAIN		CCI_REG8(0x0ef)</div><div class='add'>+</div><div class='add'>+/* ABS */</div><div class='add'>+#define GC0308_ABS_RANGE_COMP		CCI_REG8(0x0f0)</div><div class='add'>+#define GC0308_ABS_STOP_MARGIN		CCI_REG8(0x0f1)</div><div class='add'>+#define GC0308_Y_S_COMP			CCI_REG8(0x0f2)</div><div class='add'>+#define GC0308_Y_STRETCH_LIMIT		CCI_REG8(0x0f3)</div><div class='add'>+#define GC0308_Y_TILT			CCI_REG8(0x0f4)</div><div class='add'>+#define GC0308_Y_STRETCH		CCI_REG8(0x0f5)</div><div class='add'>+</div><div class='add'>+/* Measure Window */</div><div class='add'>+#define GC0308_BIG_WIN_X0		CCI_REG8(0x0f7)</div><div class='add'>+#define GC0308_BIG_WIN_Y0		CCI_REG8(0x0f8)</div><div class='add'>+#define GC0308_BIG_WIN_X1		CCI_REG8(0x0f9)</div><div class='add'>+#define GC0308_BIG_WIN_Y1		CCI_REG8(0x0fa)</div><div class='add'>+#define GC0308_DIFF_Y_BIG_THD		CCI_REG8(0x0fb)</div><div class='add'>+</div><div class='add'>+/* OUT Module (P1) */</div><div class='add'>+#define GC0308_CLOSE_FRAME_EN		CCI_REG8(0x150)</div><div class='add'>+#define GC0308_CLOSE_FRAME_NUM1		CCI_REG8(0x151)</div><div class='add'>+#define GC0308_CLOSE_FRAME_NUM2		CCI_REG8(0x152)</div><div class='add'>+#define GC0308_BAYER_MODE		CCI_REG8(0x153)</div><div class='add'>+#define GC0308_SUBSAMPLE		CCI_REG8(0x154)</div><div class='add'>+#define GC0308_SUBMODE			CCI_REG8(0x155)</div><div class='add'>+#define GC0308_SUB_ROW_N1		CCI_REG8(0x156)</div><div class='add'>+#define GC0308_SUB_ROW_N2		CCI_REG8(0x157)</div><div class='add'>+#define GC0308_SUB_COL_N1		CCI_REG8(0x158)</div><div class='add'>+#define GC0308_SUB_COL_N2		CCI_REG8(0x159)</div><div class='add'>+</div><div class='add'>+/* AWB (P1) - Auto White Balance */</div><div class='add'>+#define GC0308_AWB_RGB_HIGH_LOW		CCI_REG8(0x100)</div><div class='add'>+#define GC0308_AWB_Y_TO_C_DIFF2		CCI_REG8(0x102)</div><div class='add'>+#define GC0308_AWB_C_MAX		CCI_REG8(0x104)</div><div class='add'>+#define GC0308_AWB_C_INTER		CCI_REG8(0x105)</div><div class='add'>+#define GC0308_AWB_C_INTER2		CCI_REG8(0x106)</div><div class='add'>+#define GC0308_AWB_C_MAX_BIG		CCI_REG8(0x108)</div><div class='add'>+#define GC0308_AWB_Y_HIGH		CCI_REG8(0x109)</div><div class='add'>+#define GC0308_AWB_NUMBER_LIMIT		CCI_REG8(0x10a)</div><div class='add'>+#define GC0308_KWIN_RATIO		CCI_REG8(0x10b)</div><div class='add'>+#define GC0308_KWIN_THD			CCI_REG8(0x10c)</div><div class='add'>+#define GC0308_LIGHT_GAIN_RANGE		CCI_REG8(0x10d)</div><div class='add'>+#define GC0308_SMALL_WIN_WIDTH_STEP	CCI_REG8(0x10e)</div><div class='add'>+#define GC0308_SMALL_WIN_HEIGHT_STEP	CCI_REG8(0x10f)</div><div class='add'>+#define GC0308_AWB_YELLOW_TH		CCI_REG8(0x110)</div><div class='add'>+#define GC0308_AWB_MODE			CCI_REG8(0x111)</div><div class='add'>+#define GC0308_AWB_ADJUST_SPEED		CCI_REG8(0x112)</div><div class='add'>+#define GC0308_AWB_EVERY_N		CCI_REG8(0x113)</div><div class='add'>+#define GC0308_R_AVG_USE		CCI_REG8(0x1d0)</div><div class='add'>+#define GC0308_G_AVG_USE		CCI_REG8(0x1d1)</div><div class='add'>+#define GC0308_B_AVG_USE		CCI_REG8(0x1d2)</div><div class='add'>+</div><div class='add'>+#define GC0308_HBLANK_MIN		0x021</div><div class='add'>+#define GC0308_HBLANK_MAX		0xfff</div><div class='add'>+#define GC0308_HBLANK_DEF		0x040</div><div class='add'>+</div><div class='add'>+#define GC0308_VBLANK_MIN		0x000</div><div class='add'>+#define GC0308_VBLANK_MAX		0xfff</div><div class='add'>+#define GC0308_VBLANK_DEF		0x020</div><div class='add'>+</div><div class='add'>+#define GC0308_PIXEL_RATE		24000000</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * frame_time = (BT + height + 8) * row_time</div><div class='add'>+ * width = 640 (driver does not change window size)</div><div class='add'>+ * height = 480 (driver does not change window size)</div><div class='add'>+ * row_time = HBLANK + SAMPLE_HOLD_DELAY + width + 8 + 4</div><div class='add'>+ *</div><div class='add'>+ * When EXP_TIME &gt; (BT + height):</div><div class='add'>+ *     BT = EXP_TIME - height - 8 - VS_START_TIME + VS_END_TIME</div><div class='add'>+ * else:</div><div class='add'>+ *     BT = VBLANK + VS_START_TIME + VS_END_TIME</div><div class='add'>+ *</div><div class='add'>+ * max is 30 FPS</div><div class='add'>+ *</div><div class='add'>+ * In my tests frame rate mostly depends on exposure time. Unfortuantely</div><div class='add'>+ * it's unclear how this is calculated exactly. Also since we enable AEC,</div><div class='add'>+ * the frame times vary depending on ambient light conditions.</div><div class='add'>+ */</div><div class='add'>+#define GC0308_FRAME_RATE_MAX		30</div><div class='add'>+</div><div class='add'>+enum gc0308_exp_val {</div><div class='add'>+	GC0308_EXP_M4 = 0,</div><div class='add'>+	GC0308_EXP_M3,</div><div class='add'>+	GC0308_EXP_M2,</div><div class='add'>+	GC0308_EXP_M1,</div><div class='add'>+	GC0308_EXP_0,</div><div class='add'>+	GC0308_EXP_P1,</div><div class='add'>+	GC0308_EXP_P2,</div><div class='add'>+	GC0308_EXP_P3,</div><div class='add'>+	GC0308_EXP_P4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const s64 gc0308_exposure_menu[] = {</div><div class='add'>+	-4, -3, -2, -1, 0, 1, 2, 3, 4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_exposure {</div><div class='add'>+	u8 luma_offset;</div><div class='add'>+	u8 aec_target_y;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC0308_EXPOSURE(luma_offset_reg, aec_target_y_reg) \</div><div class='add'>+	{ .luma_offset = luma_offset_reg, .aec_target_y = aec_target_y_reg }</div><div class='add'>+</div><div class='add'>+static const struct gc0308_exposure gc0308_exposure_values[] = {</div><div class='add'>+	[GC0308_EXP_M4] = GC0308_EXPOSURE(0xc0, 0x30),</div><div class='add'>+	[GC0308_EXP_M3] = GC0308_EXPOSURE(0xd0, 0x38),</div><div class='add'>+	[GC0308_EXP_M2] = GC0308_EXPOSURE(0xe0, 0x40),</div><div class='add'>+	[GC0308_EXP_M1] = GC0308_EXPOSURE(0xf0, 0x48),</div><div class='add'>+	[GC0308_EXP_0]  = GC0308_EXPOSURE(0x08, 0x50),</div><div class='add'>+	[GC0308_EXP_P1] = GC0308_EXPOSURE(0x10, 0x5c),</div><div class='add'>+	[GC0308_EXP_P2] = GC0308_EXPOSURE(0x20, 0x60),</div><div class='add'>+	[GC0308_EXP_P3] = GC0308_EXPOSURE(0x30, 0x68),</div><div class='add'>+	[GC0308_EXP_P4] = GC0308_EXPOSURE(0x40, 0x70),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_awb_gains {</div><div class='add'>+	u8 r;</div><div class='add'>+	u8 g;</div><div class='add'>+	u8 b;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC0308_AWB_GAINS(red, green, blue) \</div><div class='add'>+	{ .r = red, .g = green, .b = blue }</div><div class='add'>+</div><div class='add'>+static const struct gc0308_awb_gains gc0308_awb_gains[] = {</div><div class='add'>+	[V4L2_WHITE_BALANCE_AUTO]         = GC0308_AWB_GAINS(0x56, 0x40, 0x4a),</div><div class='add'>+	[V4L2_WHITE_BALANCE_CLOUDY]       = GC0308_AWB_GAINS(0x8c, 0x50, 0x40),</div><div class='add'>+	[V4L2_WHITE_BALANCE_DAYLIGHT]     = GC0308_AWB_GAINS(0x74, 0x52, 0x40),</div><div class='add'>+	[V4L2_WHITE_BALANCE_INCANDESCENT] = GC0308_AWB_GAINS(0x48, 0x40, 0x5c),</div><div class='add'>+	[V4L2_WHITE_BALANCE_FLUORESCENT]  = GC0308_AWB_GAINS(0x40, 0x42, 0x50),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_format {</div><div class='add'>+	u32 code;</div><div class='add'>+	u8 regval;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC0308_FORMAT(v4l2_code, gc0308_regval) \</div><div class='add'>+	{ .code = v4l2_code, .regval = gc0308_regval }</div><div class='add'>+</div><div class='add'>+static const struct gc0308_format gc0308_formats[] = {</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_UYVY8_2X8, 0x00),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_VYUY8_2X8, 0x01),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_YUYV8_2X8, 0x02),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_YVYU8_2X8, 0x03),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_RGB565_2X8_BE, 0x06),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 0x07),</div><div class='add'>+	GC0308_FORMAT(MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE, 0x09),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_frame_size {</div><div class='add'>+	u8 subsample;</div><div class='add'>+	u32 width;</div><div class='add'>+	u32 height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC0308_FRAME_SIZE(s, w, h) \</div><div class='add'>+	{ .subsample = s, .width = w, .height = h }</div><div class='add'>+</div><div class='add'>+static const struct gc0308_frame_size gc0308_frame_sizes[] = {</div><div class='add'>+	GC0308_FRAME_SIZE(0x11, 640, 480),</div><div class='add'>+	GC0308_FRAME_SIZE(0x22, 320, 240),</div><div class='add'>+	GC0308_FRAME_SIZE(0x44, 160, 120),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_mode_registers {</div><div class='add'>+	u8 out_format;</div><div class='add'>+	u8 subsample;</div><div class='add'>+	u16 width;</div><div class='add'>+	u16 height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308 {</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct v4l2_ctrl_handler hdl;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct clk *clk;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct regulator *vdd;</div><div class='add'>+	struct gpio_desc *pwdn_gpio;</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	unsigned int mbus_config;</div><div class='add'>+	struct gc0308_mode_registers mode;</div><div class='add'>+	struct {</div><div class='add'>+		/* mirror cluster */</div><div class='add'>+		struct v4l2_ctrl *hflip;</div><div class='add'>+		struct v4l2_ctrl *vflip;</div><div class='add'>+	};</div><div class='add'>+	struct {</div><div class='add'>+		/* blanking cluster */</div><div class='add'>+		struct v4l2_ctrl *hblank;</div><div class='add'>+		struct v4l2_ctrl *vblank;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct gc0308 *to_gc0308(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	return container_of(sd, struct gc0308, sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct regmap_range_cfg gc0308_ranges[] = {</div><div class='add'>+	{</div><div class='add'>+		.range_min	= 0x0000,</div><div class='add'>+		.range_max	= 0x01ff,</div><div class='add'>+		.selector_reg	= 0xfe,</div><div class='add'>+		.selector_mask	= 0x01,</div><div class='add'>+		.selector_shift	= 0x00,</div><div class='add'>+		.window_start	= 0x00,</div><div class='add'>+		.window_len	= 0x100,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regmap_config gc0308_regmap_config = {</div><div class='add'>+	.reg_bits = 8,</div><div class='add'>+	.val_bits = 8,</div><div class='add'>+	.reg_format_endian = REGMAP_ENDIAN_BIG,</div><div class='add'>+	.max_register = 0x1ff,</div><div class='add'>+	.ranges = gc0308_ranges,</div><div class='add'>+	.num_ranges = ARRAY_SIZE(gc0308_ranges),</div><div class='add'>+	.disable_locking = true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence sensor_default_regs[] = {</div><div class='add'>+	{GC0308_VB_HB, 0x00},</div><div class='add'>+	{GC0308_HBLANK, 0x40},</div><div class='add'>+	{GC0308_VBLANK, 0x20},</div><div class='add'>+	{GC0308_EXP, 0x0258},</div><div class='add'>+	{GC0308_AWB_R_GAIN, 0x56},</div><div class='add'>+	{GC0308_AWB_G_GAIN, 0x40},</div><div class='add'>+	{GC0308_AWB_B_GAIN, 0x4a},</div><div class='add'>+	{GC0308_ANTI_FLICKER_STEP, 0x0078},</div><div class='add'>+	{GC0308_EXP_LVL_1, 0x0258},</div><div class='add'>+	{GC0308_EXP_LVL_2, 0x0258},</div><div class='add'>+	{GC0308_EXP_LVL_3, 0x0258},</div><div class='add'>+	{GC0308_EXP_LVL_4, 0x0ea6},</div><div class='add'>+	{GC0308_MAX_EXP_LVL, 0x20},</div><div class='add'>+	{GC0308_ROW_START, 0x0000},</div><div class='add'>+	{GC0308_COL_START, 0x0000},</div><div class='add'>+	{GC0308_WIN_HEIGHT, 488},</div><div class='add'>+	{GC0308_WIN_WIDTH, 648},</div><div class='add'>+	{GC0308_VS_START_TIME, 0x02},</div><div class='add'>+	{GC0308_VS_END_TIME, 0x02},</div><div class='add'>+	{GC0308_RSH_WIDTH, 0x22},</div><div class='add'>+	{GC0308_TSP_WIDTH, 0x0d},</div><div class='add'>+	{GC0308_SAMPLE_HOLD_DELAY, 0x50},</div><div class='add'>+	{GC0308_ROW_TAIL_WIDTH, 0x0f},</div><div class='add'>+	{GC0308_CISCTL_MODE1, 0x10},</div><div class='add'>+	{GC0308_CISCTL_MODE2, 0x0a},</div><div class='add'>+	{GC0308_CISCTL_MODE3, 0x05},</div><div class='add'>+	{GC0308_CISCTL_MODE4, 0x01},</div><div class='add'>+	{CCI_REG8(0x018), 0x44}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x019), 0x44}, /* undocumented */</div><div class='add'>+	{GC0308_ANALOG_MODE1, 0x2a},</div><div class='add'>+	{GC0308_ANALOG_MODE2, 0x00},</div><div class='add'>+	{GC0308_HRST_RSG_V18, 0x49},</div><div class='add'>+	{GC0308_VREF_V25, 0x9a},</div><div class='add'>+	{GC0308_ADC_R, 0x61},</div><div class='add'>+	{GC0308_PAD_DRV, 0x01}, /* drv strength: pclk=4mA */</div><div class='add'>+	{GC0308_BLOCK_EN1, 0x7f},</div><div class='add'>+	{GC0308_BLOCK_EN2, 0xfa},</div><div class='add'>+	{GC0308_AAAA_EN, 0x57},</div><div class='add'>+	{GC0308_OUT_FORMAT, 0xa2}, /* YCbYCr */</div><div class='add'>+	{GC0308_OUT_EN, 0x0f},</div><div class='add'>+	{GC0308_SYNC_MODE, 0x03},</div><div class='add'>+	{GC0308_CLK_DIV_MODE, 0x00},</div><div class='add'>+	{GC0308_DEBUG_MODE1, 0x0a},</div><div class='add'>+	{GC0308_DEBUG_MODE2, 0x00},</div><div class='add'>+	{GC0308_DEBUG_MODE3, 0x01},</div><div class='add'>+	{GC0308_BLK_MODE, 0xf7},</div><div class='add'>+	{GC0308_BLK_LIMIT_VAL, 0x50},</div><div class='add'>+	{GC0308_GLOBAL_OFF, 0x00},</div><div class='add'>+	{GC0308_CURRENT_R_OFF, 0x28},</div><div class='add'>+	{GC0308_CURRENT_G_OFF, 0x2a},</div><div class='add'>+	{GC0308_CURRENT_B_OFF, 0x28},</div><div class='add'>+	{GC0308_EXP_RATE_DARKC, 0x04},</div><div class='add'>+	{GC0308_OFF_SUBMODE, 0x20},</div><div class='add'>+	{GC0308_DARKC_SUBMODE, 0x20},</div><div class='add'>+	{GC0308_MANUAL_G1_OFF, 0x00},</div><div class='add'>+	{GC0308_MANUAL_R1_OFF, 0x00},</div><div class='add'>+	{GC0308_MANUAL_B2_OFF, 0x00},</div><div class='add'>+	{GC0308_MANUAL_G2_OFF, 0x00},</div><div class='add'>+	{GC0308_GLOBAL_GAIN, 0x14},</div><div class='add'>+	{GC0308_AUTO_POSTGAIN, 0x41},</div><div class='add'>+	{GC0308_CHANNEL_GAIN_G1, 0x80},</div><div class='add'>+	{GC0308_CHANNEL_GAIN_R, 0x80},</div><div class='add'>+	{GC0308_CHANNEL_GAIN_B, 0x80},</div><div class='add'>+	{GC0308_CHANNEL_GAIN_G2, 0x80},</div><div class='add'>+	{GC0308_LSC_RED_B2, 0x20},</div><div class='add'>+	{GC0308_LSC_GREEN_B2, 0x20},</div><div class='add'>+	{GC0308_LSC_BLUE_B2, 0x20},</div><div class='add'>+	{GC0308_LSC_RED_B4, 0x14},</div><div class='add'>+	{GC0308_LSC_GREEN_B4, 0x10},</div><div class='add'>+	{GC0308_LSC_BLUE_B4, 0x14},</div><div class='add'>+	{GC0308_LSC_ROW_CENTER, 0x3c},</div><div class='add'>+	{GC0308_LSC_COL_CENTER, 0x50},</div><div class='add'>+	{GC0308_LSC_DEC_LVL1, 0x12},</div><div class='add'>+	{GC0308_LSC_DEC_LVL2, 0x1a},</div><div class='add'>+	{GC0308_LSC_DEC_LVL3, 0x24},</div><div class='add'>+	{GC0308_DN_MODE_EN, 0x07},</div><div class='add'>+	{GC0308_DN_MODE_RATIO, 0x15},</div><div class='add'>+	{GC0308_DN_BILAT_B_BASE, 0x08},</div><div class='add'>+	{GC0308_DN_BILAT_N_BASE, 0x03},</div><div class='add'>+	{GC0308_DD_DARK_BRIGHT_TH, 0xe8},</div><div class='add'>+	{GC0308_DD_FLAT_TH, 0x86},</div><div class='add'>+	{GC0308_DD_LIMIT, 0x82},</div><div class='add'>+	{GC0308_ASDE_GAIN_TRESH, 0x18},</div><div class='add'>+	{GC0308_ASDE_GAIN_MODE, 0x0f},</div><div class='add'>+	{GC0308_ASDE_DN_SLOPE, 0x00},</div><div class='add'>+	{GC0308_ASDE_DD_BRIGHT, 0x5f},</div><div class='add'>+	{GC0308_ASDE_DD_LIMIT, 0x8f},</div><div class='add'>+	{GC0308_ASDE_AUTO_EE1, 0x55},</div><div class='add'>+	{GC0308_ASDE_AUTO_EE2, 0x38},</div><div class='add'>+	{GC0308_ASDE_AUTO_SAT_DEC_SLOPE, 0x15},</div><div class='add'>+	{GC0308_ASDE_AUTO_SAT_LOW_LIMIT, 0x33},</div><div class='add'>+	{GC0308_EEINTP_MODE_1, 0xdc},</div><div class='add'>+	{GC0308_EEINTP_MODE_2, 0x00},</div><div class='add'>+	{GC0308_DIRECTION_TH1, 0x02},</div><div class='add'>+	{GC0308_DIRECTION_TH2, 0x3f},</div><div class='add'>+	{GC0308_DIFF_HV_TI_TH, 0x02},</div><div class='add'>+	{GC0308_EDGE12_EFFECT, 0x38},</div><div class='add'>+	{GC0308_EDGE_POS_RATIO, 0x88},</div><div class='add'>+	{GC0308_EDGE1_MINMAX, 0x81},</div><div class='add'>+	{GC0308_EDGE2_MINMAX, 0x81},</div><div class='add'>+	{GC0308_EDGE12_TH, 0x22},</div><div class='add'>+	{GC0308_EDGE_MAX, 0xff},</div><div class='add'>+	{GC0308_CC_MATRIX_C11, 0x48},</div><div class='add'>+	{GC0308_CC_MATRIX_C12, 0x02},</div><div class='add'>+	{GC0308_CC_MATRIX_C13, 0x07},</div><div class='add'>+	{GC0308_CC_MATRIX_C21, 0xe0},</div><div class='add'>+	{GC0308_CC_MATRIX_C22, 0x40},</div><div class='add'>+	{GC0308_CC_MATRIX_C23, 0xf0},</div><div class='add'>+	{GC0308_SATURATION_CB, 0x40},</div><div class='add'>+	{GC0308_SATURATION_CR, 0x40},</div><div class='add'>+	{GC0308_LUMA_CONTRAST, 0x40},</div><div class='add'>+	{GC0308_SKIN_CB_CENTER, 0xe0},</div><div class='add'>+	{GC0308_EDGE_DEC_SA, 0x38},</div><div class='add'>+	{GC0308_AUTO_GRAY_MODE, 0x36},</div><div class='add'>+	{GC0308_AEC_MODE1, 0xcb},</div><div class='add'>+	{GC0308_AEC_MODE2, 0x10},</div><div class='add'>+	{GC0308_AEC_MODE3, 0x90},</div><div class='add'>+	{GC0308_AEC_TARGET_Y, 0x48},</div><div class='add'>+	{GC0308_AEC_HIGH_LOW_RANGE, 0xf2},</div><div class='add'>+	{GC0308_AEC_IGNORE, 0x16},</div><div class='add'>+	{GC0308_AEC_SLOW_MARGIN, 0x92},</div><div class='add'>+	{GC0308_AEC_FAST_MARGIN, 0xa5},</div><div class='add'>+	{GC0308_AEC_I_FRAMES, 0x23},</div><div class='add'>+	{GC0308_AEC_R_OFFSET, 0x00},</div><div class='add'>+	{GC0308_AEC_GB_OFFSET, 0x00},</div><div class='add'>+	{GC0308_AEC_I_STOP_L_MARGIN, 0x09},</div><div class='add'>+	{GC0308_EXP_MIN_L, 0x04},</div><div class='add'>+	{GC0308_MAX_POST_DF_GAIN, 0xa0},</div><div class='add'>+	{GC0308_MAX_PRE_DG_GAIN, 0x40},</div><div class='add'>+	{GC0308_ABB_MODE, 0x03},</div><div class='add'>+	{GC0308_GAMMA_OUT0, 0x10},</div><div class='add'>+	{GC0308_GAMMA_OUT1, 0x20},</div><div class='add'>+	{GC0308_GAMMA_OUT2, 0x38},</div><div class='add'>+	{GC0308_GAMMA_OUT3, 0x4e},</div><div class='add'>+	{GC0308_GAMMA_OUT4, 0x63},</div><div class='add'>+	{GC0308_GAMMA_OUT5, 0x76},</div><div class='add'>+	{GC0308_GAMMA_OUT6, 0x87},</div><div class='add'>+	{GC0308_GAMMA_OUT7, 0xa2},</div><div class='add'>+	{GC0308_GAMMA_OUT8, 0xb8},</div><div class='add'>+	{GC0308_GAMMA_OUT9, 0xca},</div><div class='add'>+	{GC0308_GAMMA_OUT10, 0xd8},</div><div class='add'>+	{GC0308_GAMMA_OUT11, 0xe3},</div><div class='add'>+	{GC0308_GAMMA_OUT12, 0xeb},</div><div class='add'>+	{GC0308_GAMMA_OUT13, 0xf0},</div><div class='add'>+	{GC0308_GAMMA_OUT14, 0xf8},</div><div class='add'>+	{GC0308_GAMMA_OUT15, 0xfd},</div><div class='add'>+	{GC0308_GAMMA_OUT16, 0xff},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT0, 0x00},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT1, 0x10},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT2, 0x1c},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT3, 0x30},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT4, 0x43},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT5, 0x54},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT6, 0x65},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT7, 0x75},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT8, 0x93},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT9, 0xb0},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT10, 0xcb},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT11, 0xe6},</div><div class='add'>+	{GC0308_Y_GAMMA_OUT12, 0xff},</div><div class='add'>+	{GC0308_ABS_RANGE_COMP, 0x02},</div><div class='add'>+	{GC0308_ABS_STOP_MARGIN, 0x01},</div><div class='add'>+	{GC0308_Y_S_COMP, 0x02},</div><div class='add'>+	{GC0308_Y_STRETCH_LIMIT, 0x30},</div><div class='add'>+	{GC0308_BIG_WIN_X0, 0x12},</div><div class='add'>+	{GC0308_BIG_WIN_Y0, 0x0a},</div><div class='add'>+	{GC0308_BIG_WIN_X1, 0x9f},</div><div class='add'>+	{GC0308_BIG_WIN_Y1, 0x78},</div><div class='add'>+	{GC0308_AWB_RGB_HIGH_LOW, 0xf5},</div><div class='add'>+	{GC0308_AWB_Y_TO_C_DIFF2, 0x20},</div><div class='add'>+	{GC0308_AWB_C_MAX, 0x10},</div><div class='add'>+	{GC0308_AWB_C_INTER, 0x08},</div><div class='add'>+	{GC0308_AWB_C_INTER2, 0x20},</div><div class='add'>+	{GC0308_AWB_C_MAX_BIG, 0x0a},</div><div class='add'>+	{GC0308_AWB_NUMBER_LIMIT, 0xa0},</div><div class='add'>+	{GC0308_KWIN_RATIO, 0x60},</div><div class='add'>+	{GC0308_KWIN_THD, 0x08},</div><div class='add'>+	{GC0308_SMALL_WIN_WIDTH_STEP, 0x44},</div><div class='add'>+	{GC0308_SMALL_WIN_HEIGHT_STEP, 0x32},</div><div class='add'>+	{GC0308_AWB_YELLOW_TH, 0x41},</div><div class='add'>+	{GC0308_AWB_MODE, 0x37},</div><div class='add'>+	{GC0308_AWB_ADJUST_SPEED, 0x22},</div><div class='add'>+	{GC0308_AWB_EVERY_N, 0x19},</div><div class='add'>+	{CCI_REG8(0x114), 0x44}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x115), 0x44}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x116), 0xc2}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x117), 0xa8}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x118), 0x18}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x119), 0x50}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x11a), 0xd8}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x11b), 0xf5}, /* AWB set1 */</div><div class='add'>+	{CCI_REG8(0x170), 0x40}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x171), 0x58}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x172), 0x30}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x173), 0x48}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x174), 0x20}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x175), 0x60}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x177), 0x20}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x178), 0x32}, /* AWB set2 */</div><div class='add'>+	{CCI_REG8(0x130), 0x03}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x131), 0x40}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x132), 0x10}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x133), 0xe0}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x134), 0xe0}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x135), 0x00}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x136), 0x80}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x137), 0x00}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x138), 0x04}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x139), 0x09}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13a), 0x12}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13b), 0x1c}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13c), 0x28}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13d), 0x31}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13e), 0x44}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x13f), 0x57}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x140), 0x6c}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x141), 0x81}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x142), 0x94}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x143), 0xa7}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x144), 0xb8}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x145), 0xd6}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x146), 0xee}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x147), 0x0d}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x162), 0xf7}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x163), 0x68}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x164), 0xd3}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x165), 0xd3}, /* undocumented */</div><div class='add'>+	{CCI_REG8(0x166), 0x60}, /* undocumented */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc0308_colormode {</div><div class='add'>+	u8 special_effect;</div><div class='add'>+	u8 dbg_mode1;</div><div class='add'>+	u8 block_en1;</div><div class='add'>+	u8 aec_mode3;</div><div class='add'>+	u8 eeintp_mode_2;</div><div class='add'>+	u8 edge12_effect;</div><div class='add'>+	u8 luma_contrast;</div><div class='add'>+	u8 contrast_center;</div><div class='add'>+	u8 fixed_cb;</div><div class='add'>+	u8 fixed_cr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC0308_COLOR_FX(reg_special_effect, reg_dbg_mode1, reg_block_en1, \</div><div class='add'>+			reg_aec_mode3, reg_eeintp_mode_2, reg_edge12_effect, \</div><div class='add'>+			reg_luma_contrast, reg_contrast_center, \</div><div class='add'>+			reg_fixed_cb, reg_fixed_cr) \</div><div class='add'>+	{ \</div><div class='add'>+		.special_effect = reg_special_effect, \</div><div class='add'>+		.dbg_mode1 = reg_dbg_mode1, \</div><div class='add'>+		.block_en1 = reg_block_en1, \</div><div class='add'>+		.aec_mode3 = reg_aec_mode3, \</div><div class='add'>+		.eeintp_mode_2 = reg_eeintp_mode_2, \</div><div class='add'>+		.edge12_effect = reg_edge12_effect, \</div><div class='add'>+		.luma_contrast = reg_luma_contrast, \</div><div class='add'>+		.contrast_center = reg_contrast_center, \</div><div class='add'>+		.fixed_cb = reg_fixed_cb, \</div><div class='add'>+		.fixed_cr = reg_fixed_cr, \</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct gc0308_colormode gc0308_colormodes[] = {</div><div class='add'>+	[V4L2_COLORFX_NONE] =</div><div class='add'>+		GC0308_COLOR_FX(0x00, 0x0a, 0xff, 0x90, 0x00,</div><div class='add'>+				0x54, 0x3c, 0x80, 0x00, 0x00),</div><div class='add'>+	[V4L2_COLORFX_BW] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,</div><div class='add'>+				0x54, 0x40, 0x80, 0x00, 0x00),</div><div class='add'>+	[V4L2_COLORFX_SEPIA] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,</div><div class='add'>+				0x38, 0x40, 0x80, 0xd0, 0x28),</div><div class='add'>+	[V4L2_COLORFX_NEGATIVE] =</div><div class='add'>+		GC0308_COLOR_FX(0x01, 0x0a, 0xff, 0x90, 0x00,</div><div class='add'>+				0x38, 0x40, 0x80, 0x00, 0x00),</div><div class='add'>+	[V4L2_COLORFX_EMBOSS] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,</div><div class='add'>+				0x38, 0x40, 0x80, 0x00, 0x00),</div><div class='add'>+	[V4L2_COLORFX_SKETCH] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x10, 0x80,</div><div class='add'>+				0x38, 0x80, 0x90, 0x00, 0x00),</div><div class='add'>+	[V4L2_COLORFX_SKY_BLUE] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x00,</div><div class='add'>+				0x38, 0x40, 0x80, 0x50, 0xe0),</div><div class='add'>+	[V4L2_COLORFX_GRASS_GREEN] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xff, 0x90, 0x01,</div><div class='add'>+				0x38, 0x40, 0x80, 0xc0, 0xc0),</div><div class='add'>+	[V4L2_COLORFX_SKIN_WHITEN] =</div><div class='add'>+		GC0308_COLOR_FX(0x02, 0x0a, 0xbf, 0x10, 0x01,</div><div class='add'>+				0x38, 0x60, 0x40, 0x00, 0x00),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc0308_power_on(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_enable(gc0308-&gt;vdd);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(gc0308-&gt;clk);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto clk_fail;</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(gc0308-&gt;pwdn_gpio, 0);</div><div class='add'>+	usleep_range(10000, 20000);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(gc0308-&gt;reset_gpio, 1);</div><div class='add'>+	usleep_range(10000, 20000);</div><div class='add'>+	gpiod_set_value_cansleep(gc0308-&gt;reset_gpio, 0);</div><div class='add'>+	msleep(30);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+clk_fail:</div><div class='add'>+	regulator_disable(gc0308-&gt;vdd);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_power_off(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(gc0308-&gt;pwdn_gpio, 1);</div><div class='add'>+	clk_disable_unprepare(gc0308-&gt;clk);</div><div class='add'>+	regulator_disable(gc0308-&gt;vdd);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_VIDEO_ADV_DEBUG</div><div class='add'>+static int gc0308_g_register(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_dbg_register *reg)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = to_gc0308(sd);</div><div class='add'>+</div><div class='add'>+	return cci_read(gc0308-&gt;regmap, CCI_REG8(reg-&gt;reg), &amp;reg-&gt;val, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_s_register(struct v4l2_subdev *sd,</div><div class='add'>+			     const struct v4l2_dbg_register *reg)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = to_gc0308(sd);</div><div class='add'>+</div><div class='add'>+	return cci_write(gc0308-&gt;regmap, CCI_REG8(reg-&gt;reg), reg-&gt;val, NULL);</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static int gc0308_set_exposure(struct gc0308 *gc0308, enum gc0308_exp_val exp)</div><div class='add'>+{</div><div class='add'>+	const struct gc0308_exposure *regs = &amp;gc0308_exposure_values[exp];</div><div class='add'>+	struct cci_reg_sequence exposure_reg_seq[] = {</div><div class='add'>+		{GC0308_LUMA_OFFSET, regs-&gt;luma_offset},</div><div class='add'>+		{GC0308_AEC_TARGET_Y, regs-&gt;aec_target_y},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return cci_multi_reg_write(gc0308-&gt;regmap, exposure_reg_seq,</div><div class='add'>+				   ARRAY_SIZE(exposure_reg_seq), NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_set_awb_mode(struct gc0308 *gc0308,</div><div class='add'>+			       enum v4l2_auto_n_preset_white_balance val)</div><div class='add'>+{</div><div class='add'>+	const struct gc0308_awb_gains *regs = &amp;gc0308_awb_gains[val];</div><div class='add'>+	struct cci_reg_sequence awb_reg_seq[] = {</div><div class='add'>+		{GC0308_AWB_R_GAIN, regs-&gt;r},</div><div class='add'>+		{GC0308_AWB_G_GAIN, regs-&gt;g},</div><div class='add'>+		{GC0308_AWB_B_GAIN, regs-&gt;b},</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = cci_update_bits(gc0308-&gt;regmap, GC0308_AAAA_EN,</div><div class='add'>+			      BIT(1), val == V4L2_WHITE_BALANCE_AUTO, NULL);</div><div class='add'>+	ret = cci_multi_reg_write(gc0308-&gt;regmap, awb_reg_seq,</div><div class='add'>+				  ARRAY_SIZE(awb_reg_seq), &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_set_colormode(struct gc0308 *gc0308, enum v4l2_colorfx mode)</div><div class='add'>+{</div><div class='add'>+	const struct gc0308_colormode *regs = &amp;gc0308_colormodes[mode];</div><div class='add'>+	struct cci_reg_sequence colormode_reg_seq[] = {</div><div class='add'>+		{GC0308_SPECIAL_EFFECT, regs-&gt;special_effect},</div><div class='add'>+		{GC0308_DEBUG_MODE1, regs-&gt;dbg_mode1},</div><div class='add'>+		{GC0308_BLOCK_EN1, regs-&gt;block_en1},</div><div class='add'>+		{GC0308_AEC_MODE3, regs-&gt;aec_mode3},</div><div class='add'>+		{GC0308_EEINTP_MODE_2, regs-&gt;eeintp_mode_2},</div><div class='add'>+		{GC0308_EDGE12_EFFECT, regs-&gt;edge12_effect},</div><div class='add'>+		{GC0308_LUMA_CONTRAST, regs-&gt;luma_contrast},</div><div class='add'>+		{GC0308_CONTRAST_CENTER, regs-&gt;contrast_center},</div><div class='add'>+		{GC0308_FIXED_CB, regs-&gt;fixed_cb},</div><div class='add'>+		{GC0308_FIXED_CR, regs-&gt;fixed_cr},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return cci_multi_reg_write(gc0308-&gt;regmap, colormode_reg_seq,</div><div class='add'>+				   ARRAY_SIZE(colormode_reg_seq), NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_set_power_line_freq(struct gc0308 *gc0308, int frequency)</div><div class='add'>+{</div><div class='add'>+	static const struct cci_reg_sequence pwr_line_50hz[] = {</div><div class='add'>+		{GC0308_ANTI_FLICKER_STEP, 0x0078},</div><div class='add'>+		{GC0308_EXP_LVL_1, 0x0258},</div><div class='add'>+		{GC0308_EXP_LVL_2, 0x0348},</div><div class='add'>+		{GC0308_EXP_LVL_3, 0x04b0},</div><div class='add'>+		{GC0308_EXP_LVL_4, 0x05a0},</div><div class='add'>+	};</div><div class='add'>+	static const struct cci_reg_sequence pwr_line_60hz[] = {</div><div class='add'>+		{GC0308_ANTI_FLICKER_STEP, 0x0064},</div><div class='add'>+		{GC0308_EXP_LVL_1, 0x0258},</div><div class='add'>+		{GC0308_EXP_LVL_2, 0x0384},</div><div class='add'>+		{GC0308_EXP_LVL_3, 0x04b0},</div><div class='add'>+		{GC0308_EXP_LVL_4, 0x05dc},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	switch (frequency) {</div><div class='add'>+	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:</div><div class='add'>+		return cci_multi_reg_write(gc0308-&gt;regmap, pwr_line_60hz,</div><div class='add'>+					   ARRAY_SIZE(pwr_line_60hz), NULL);</div><div class='add'>+	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:</div><div class='add'>+		return cci_multi_reg_write(gc0308-&gt;regmap, pwr_line_50hz,</div><div class='add'>+					   ARRAY_SIZE(pwr_line_50hz), NULL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_update_mirror(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	u8 regval = 0x00;</div><div class='add'>+</div><div class='add'>+	if (gc0308-&gt;vflip-&gt;val)</div><div class='add'>+		regval |= BIT(1);</div><div class='add'>+</div><div class='add'>+	if (gc0308-&gt;hflip-&gt;val)</div><div class='add'>+		regval |= BIT(0);</div><div class='add'>+</div><div class='add'>+	return cci_update_bits(gc0308-&gt;regmap, GC0308_CISCTL_MODE1,</div><div class='add'>+			       GENMASK(1, 0), regval, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_update_blanking(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	u16 vblank = gc0308-&gt;vblank-&gt;val;</div><div class='add'>+	u16 hblank = gc0308-&gt;hblank-&gt;val;</div><div class='add'>+	u8 vbhb = ((vblank &gt;&gt; 4) &amp; 0xf0) | ((hblank &gt;&gt; 8) &amp; 0x0f);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	cci_write(gc0308-&gt;regmap, GC0308_VB_HB, vbhb, &amp;ret);</div><div class='add'>+	cci_write(gc0308-&gt;regmap, GC0308_HBLANK, hblank &amp; 0xff, &amp;ret);</div><div class='add'>+	cci_write(gc0308-&gt;regmap, GC0308_VBLANK, vblank &amp; 0xff, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int _gc0308_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = container_of(ctrl-&gt;handler, struct gc0308, hdl);</div><div class='add'>+	u8 flipval = ctrl-&gt;val ? 0xff : 0x00;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_HBLANK:</div><div class='add'>+	case V4L2_CID_VBLANK:</div><div class='add'>+		return gc0308_update_blanking(gc0308);</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+		return gc0308_update_mirror(gc0308);</div><div class='add'>+	case V4L2_CID_AUTO_WHITE_BALANCE:</div><div class='add'>+		return cci_update_bits(gc0308-&gt;regmap, GC0308_AAAA_EN,</div><div class='add'>+				       BIT(1), flipval, NULL);</div><div class='add'>+	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:</div><div class='add'>+		return gc0308_set_awb_mode(gc0308, ctrl-&gt;val);</div><div class='add'>+	case V4L2_CID_POWER_LINE_FREQUENCY:</div><div class='add'>+		return gc0308_set_power_line_freq(gc0308, ctrl-&gt;val);</div><div class='add'>+	case V4L2_CID_COLORFX:</div><div class='add'>+		return gc0308_set_colormode(gc0308, ctrl-&gt;val);</div><div class='add'>+	case V4L2_CID_TEST_PATTERN:</div><div class='add'>+		return cci_update_bits(gc0308-&gt;regmap, GC0308_DEBUG_MODE2,</div><div class='add'>+				       GENMASK(1, 0), ctrl-&gt;val, NULL);</div><div class='add'>+	case V4L2_CID_AUTO_EXPOSURE_BIAS:</div><div class='add'>+		return gc0308_set_exposure(gc0308, ctrl-&gt;val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = container_of(ctrl-&gt;handler, struct gc0308, hdl);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pm_runtime_get_if_in_use(gc0308-&gt;dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = _gc0308_s_ctrl(ctrl);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(gc0308-&gt;dev, "failed to set control: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(gc0308-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(gc0308-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops gc0308_ctrl_ops = {</div><div class='add'>+	.s_ctrl = gc0308_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops gc0308_core_ops = {</div><div class='add'>+	.log_status = v4l2_ctrl_subdev_log_status,</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+#ifdef CONFIG_VIDEO_ADV_DEBUG</div><div class='add'>+	.g_register	= gc0308_g_register,</div><div class='add'>+	.s_register	= gc0308_s_register,</div><div class='add'>+#endif</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc0308_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state,</div><div class='add'>+				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	if (code-&gt;index &gt;= ARRAY_SIZE(gc0308_formats))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = gc0308_formats[code-&gt;index].code;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_get_format_idx(u32 code)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(gc0308_formats); i++) {</div><div class='add'>+		if (gc0308_formats[i].code == code)</div><div class='add'>+			return i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state,</div><div class='add'>+				  struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	if (fse-&gt;index &gt;= ARRAY_SIZE(gc0308_frame_sizes))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (gc0308_get_format_idx(fse-&gt;code) &lt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fse-&gt;min_width = gc0308_frame_sizes[fse-&gt;index].width;</div><div class='add'>+	fse-&gt;max_width = gc0308_frame_sizes[fse-&gt;index].width;</div><div class='add'>+	fse-&gt;min_height = gc0308_frame_sizes[fse-&gt;index].height;</div><div class='add'>+	fse-&gt;max_height = gc0308_frame_sizes[fse-&gt;index].height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gc0308_update_pad_format(const struct gc0308_frame_size *mode,</div><div class='add'>+				     struct v4l2_mbus_framefmt *fmt, u32 code)</div><div class='add'>+{</div><div class='add'>+	fmt-&gt;width = mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = mode-&gt;height;</div><div class='add'>+	fmt-&gt;code = code;</div><div class='add'>+	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_set_format(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state,</div><div class='add'>+			     struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = to_gc0308(sd);</div><div class='add'>+	const struct gc0308_frame_size *mode;</div><div class='add'>+	int i = gc0308_get_format_idx(fmt-&gt;format.code);</div><div class='add'>+</div><div class='add'>+	if (i &lt; 0)</div><div class='add'>+		i = 0;</div><div class='add'>+</div><div class='add'>+	mode = v4l2_find_nearest_size(gc0308_frame_sizes,</div><div class='add'>+				      ARRAY_SIZE(gc0308_frame_sizes), width,</div><div class='add'>+				      height, fmt-&gt;format.width,</div><div class='add'>+				      fmt-&gt;format.height);</div><div class='add'>+</div><div class='add'>+	gc0308_update_pad_format(mode, &amp;fmt-&gt;format, gc0308_formats[i].code);</div><div class='add'>+	*v4l2_subdev_state_get_format(sd_state, 0) = fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;mode.out_format = gc0308_formats[i].regval;</div><div class='add'>+	gc0308-&gt;mode.subsample = mode-&gt;subsample;</div><div class='add'>+	gc0308-&gt;mode.width = mode-&gt;width;</div><div class='add'>+	gc0308-&gt;mode.height = mode-&gt;height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_mbus_framefmt *format =</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	format-&gt;width		= 640;</div><div class='add'>+	format-&gt;height		= 480;</div><div class='add'>+	format-&gt;code		= gc0308_formats[0].code;</div><div class='add'>+	format-&gt;colorspace	= V4L2_COLORSPACE_SRGB;</div><div class='add'>+	format-&gt;field		= V4L2_FIELD_NONE;</div><div class='add'>+	format-&gt;ycbcr_enc	= V4L2_YCBCR_ENC_DEFAULT;</div><div class='add'>+	format-&gt;quantization	= V4L2_QUANTIZATION_DEFAULT;</div><div class='add'>+	format-&gt;xfer_func	= V4L2_XFER_FUNC_DEFAULT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops gc0308_pad_ops = {</div><div class='add'>+	.enum_mbus_code = gc0308_enum_mbus_code,</div><div class='add'>+	.enum_frame_size = gc0308_enum_frame_size,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt = gc0308_set_format,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc0308_set_resolution(struct gc0308 *gc0308, int *ret)</div><div class='add'>+{</div><div class='add'>+	struct cci_reg_sequence resolution_regs[] = {</div><div class='add'>+		{GC0308_SUBSAMPLE, gc0308-&gt;mode.subsample},</div><div class='add'>+		{GC0308_SUBMODE, 0x03},</div><div class='add'>+		{GC0308_SUB_ROW_N1, 0x00},</div><div class='add'>+		{GC0308_SUB_ROW_N2, 0x00},</div><div class='add'>+		{GC0308_SUB_COL_N1, 0x00},</div><div class='add'>+		{GC0308_SUB_COL_N2, 0x00},</div><div class='add'>+		{GC0308_CROP_WIN_MODE, 0x80},</div><div class='add'>+		{GC0308_CROP_WIN_Y1, 0x00},</div><div class='add'>+		{GC0308_CROP_WIN_X1, 0x00},</div><div class='add'>+		{GC0308_CROP_WIN_HEIGHT, gc0308-&gt;mode.height},</div><div class='add'>+		{GC0308_CROP_WIN_WIDTH, gc0308-&gt;mode.width},</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return cci_multi_reg_write(gc0308-&gt;regmap, resolution_regs,</div><div class='add'>+				   ARRAY_SIZE(resolution_regs), ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_start_stream(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	int ret, sync_mode;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(gc0308-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	cci_multi_reg_write(gc0308-&gt;regmap, sensor_default_regs,</div><div class='add'>+			    ARRAY_SIZE(sensor_default_regs), &amp;ret);</div><div class='add'>+	cci_update_bits(gc0308-&gt;regmap, GC0308_OUT_FORMAT,</div><div class='add'>+			GENMASK(4, 0), gc0308-&gt;mode.out_format, &amp;ret);</div><div class='add'>+	gc0308_set_resolution(gc0308, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(gc0308-&gt;dev, "failed to update registers: %d\n", ret);</div><div class='add'>+		goto disable_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = __v4l2_ctrl_handler_setup(&amp;gc0308-&gt;hdl);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(gc0308-&gt;dev, "failed to setup controls\n");</div><div class='add'>+		goto disable_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* HSYNC/VSYNC polarity */</div><div class='add'>+	sync_mode = 0x3;</div><div class='add'>+	if (gc0308-&gt;mbus_config &amp; V4L2_MBUS_VSYNC_ACTIVE_LOW)</div><div class='add'>+		sync_mode &amp;= ~BIT(0);</div><div class='add'>+	if (gc0308-&gt;mbus_config &amp; V4L2_MBUS_HSYNC_ACTIVE_LOW)</div><div class='add'>+		sync_mode &amp;= ~BIT(1);</div><div class='add'>+	ret = cci_write(gc0308-&gt;regmap, GC0308_SYNC_MODE, sync_mode, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto disable_pm;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+disable_pm:</div><div class='add'>+	pm_runtime_mark_last_busy(gc0308-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(gc0308-&gt;dev);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_stop_stream(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	pm_runtime_mark_last_busy(gc0308-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(gc0308-&gt;dev);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = to_gc0308(sd);</div><div class='add'>+	struct v4l2_subdev_state *sd_state;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	sd_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		ret = gc0308_start_stream(gc0308);</div><div class='add'>+	else</div><div class='add'>+		ret = gc0308_stop_stream(gc0308);</div><div class='add'>+</div><div class='add'>+	v4l2_subdev_unlock_state(sd_state);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops gc0308_video_ops = {</div><div class='add'>+	.s_stream		= gc0308_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops gc0308_subdev_ops = {</div><div class='add'>+	.core	= &amp;gc0308_core_ops,</div><div class='add'>+	.pad	= &amp;gc0308_pad_ops,</div><div class='add'>+	.video	= &amp;gc0308_video_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops gc0308_internal_ops = {</div><div class='add'>+	.init_state = gc0308_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc0308_bus_config(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = gc0308-&gt;dev;</div><div class='add'>+	struct v4l2_fwnode_endpoint bus_cfg = {</div><div class='add'>+		.bus_type = V4L2_MBUS_PARALLEL</div><div class='add'>+	};</div><div class='add'>+	struct fwnode_handle *ep;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);</div><div class='add'>+	if (!ep)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_endpoint_parse(ep, &amp;bus_cfg);</div><div class='add'>+	fwnode_handle_put(ep);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;mbus_config = bus_cfg.bus.parallel.flags;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char * const gc0308_test_pattern_menu[] = {</div><div class='add'>+	"Disabled",</div><div class='add'>+	"Test Image 1",</div><div class='add'>+	"Test Image 2",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc0308_init_controls(struct gc0308 *gc0308)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_handler_init(&amp;gc0308-&gt;hdl, 11);</div><div class='add'>+	gc0308-&gt;hblank = v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+					   V4L2_CID_HBLANK, GC0308_HBLANK_MIN,</div><div class='add'>+					   GC0308_HBLANK_MAX, 1,</div><div class='add'>+					   GC0308_HBLANK_DEF);</div><div class='add'>+	gc0308-&gt;vblank = v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+					   V4L2_CID_VBLANK, GC0308_VBLANK_MIN,</div><div class='add'>+					   GC0308_VBLANK_MAX, 1,</div><div class='add'>+					   GC0308_VBLANK_DEF);</div><div class='add'>+	gc0308-&gt;hflip = v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+					  V4L2_CID_HFLIP, 0, 1, 1, 0);</div><div class='add'>+	gc0308-&gt;vflip = v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+					  V4L2_CID_VFLIP, 0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops, V4L2_CID_PIXEL_RATE,</div><div class='add'>+			  GC0308_PIXEL_RATE, GC0308_PIXEL_RATE, 1,</div><div class='add'>+			  GC0308_PIXEL_RATE);</div><div class='add'>+	v4l2_ctrl_new_std(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+			  V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);</div><div class='add'>+	v4l2_ctrl_new_std_menu_items(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+				     V4L2_CID_TEST_PATTERN,</div><div class='add'>+				     ARRAY_SIZE(gc0308_test_pattern_menu) - 1,</div><div class='add'>+				     0, 0, gc0308_test_pattern_menu);</div><div class='add'>+	v4l2_ctrl_new_std_menu(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+			       V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,</div><div class='add'>+			       8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);</div><div class='add'>+	v4l2_ctrl_new_std_menu(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+			       V4L2_CID_COLORFX, 8, 0, V4L2_COLORFX_NONE);</div><div class='add'>+	v4l2_ctrl_new_std_menu(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+			       V4L2_CID_POWER_LINE_FREQUENCY,</div><div class='add'>+			       V4L2_CID_POWER_LINE_FREQUENCY_60HZ,</div><div class='add'>+			       ~0x6, V4L2_CID_POWER_LINE_FREQUENCY_50HZ);</div><div class='add'>+	v4l2_ctrl_new_int_menu(&amp;gc0308-&gt;hdl, &amp;gc0308_ctrl_ops,</div><div class='add'>+			       V4L2_CID_AUTO_EXPOSURE_BIAS,</div><div class='add'>+			       ARRAY_SIZE(gc0308_exposure_menu) - 1,</div><div class='add'>+			       ARRAY_SIZE(gc0308_exposure_menu) / 2,</div><div class='add'>+			       gc0308_exposure_menu);</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;sd.ctrl_handler = &amp;gc0308-&gt;hdl;</div><div class='add'>+	if (gc0308-&gt;hdl.error) {</div><div class='add'>+		ret = gc0308-&gt;hdl.error;</div><div class='add'>+		v4l2_ctrl_handler_free(&amp;gc0308-&gt;hdl);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_cluster(2, &amp;gc0308-&gt;hflip);</div><div class='add'>+	v4l2_ctrl_cluster(2, &amp;gc0308-&gt;hblank);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc0308_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct gc0308 *gc0308;</div><div class='add'>+	unsigned long clkrate;</div><div class='add'>+	u64 regval;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	gc0308 = devm_kzalloc(dev, sizeof(*gc0308), GFP_KERNEL);</div><div class='add'>+	if (!gc0308)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;dev = dev;</div><div class='add'>+	dev_set_drvdata(dev, gc0308);</div><div class='add'>+</div><div class='add'>+	ret = gc0308_bus_config(gc0308);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "failed to get bus config\n");</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;clk = devm_clk_get_optional(dev, NULL);</div><div class='add'>+	if (IS_ERR(gc0308-&gt;clk))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc0308-&gt;clk),</div><div class='add'>+				     "could not get clk\n");</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;vdd = devm_regulator_get(dev, "vdd28");</div><div class='add'>+	if (IS_ERR(gc0308-&gt;vdd))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc0308-&gt;vdd),</div><div class='add'>+				     "failed to get vdd28 regulator\n");</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;pwdn_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(gc0308-&gt;pwdn_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc0308-&gt;pwdn_gpio),</div><div class='add'>+				     "failed to get powerdown gpio\n");</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(gc0308-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc0308-&gt;reset_gpio),</div><div class='add'>+				     "failed to get reset gpio\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is not using devm_cci_regmap_init_i2c(), because the driver</div><div class='add'>+	 * makes use of regmap's pagination feature. The chosen settings are</div><div class='add'>+	 * compatible with the CCI helpers.</div><div class='add'>+	 */</div><div class='add'>+	gc0308-&gt;regmap = devm_regmap_init_i2c(client, &amp;gc0308_regmap_config);</div><div class='add'>+	if (IS_ERR(gc0308-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc0308-&gt;regmap),</div><div class='add'>+				     "failed to init regmap\n");</div><div class='add'>+</div><div class='add'>+	v4l2_i2c_subdev_init(&amp;gc0308-&gt;sd, client, &amp;gc0308_subdev_ops);</div><div class='add'>+	gc0308-&gt;sd.internal_ops = &amp;gc0308_internal_ops;</div><div class='add'>+	gc0308-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='add'>+	gc0308-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+</div><div class='add'>+	ret = gc0308_init_controls(gc0308);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "failed to init controls\n");</div><div class='add'>+</div><div class='add'>+	gc0308-&gt;sd.state_lock = gc0308-&gt;hdl.lock;</div><div class='add'>+	gc0308-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+	gc0308-&gt;sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='add'>+	ret = media_entity_pads_init(&amp;gc0308-&gt;sd.entity, 1, &amp;gc0308-&gt;pad);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto fail_ctrl_hdl_cleanup;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_init_finalize(&amp;gc0308-&gt;sd);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fail_media_entity_cleanup;</div><div class='add'>+</div><div class='add'>+	ret = gc0308_power_on(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fail_subdev_cleanup;</div><div class='add'>+</div><div class='add'>+	if (gc0308-&gt;clk) {</div><div class='add'>+		clkrate = clk_get_rate(gc0308-&gt;clk);</div><div class='add'>+		if (clkrate != 24000000)</div><div class='add'>+			dev_warn(dev, "unexpected clock rate: %lu\n", clkrate);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = cci_read(gc0308-&gt;regmap, GC0308_CHIP_ID, &amp;regval, NULL);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err_probe(dev, ret, "failed to read chip ID\n");</div><div class='add'>+		goto fail_power_off;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (regval != 0x9b) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		dev_err_probe(dev, ret, "invalid chip ID (%02llx)\n", regval);</div><div class='add'>+		goto fail_power_off;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enable runtime PM with autosuspend. As the device has been powered</div><div class='add'>+	 * manually, mark it as active, and increase the usage count without</div><div class='add'>+	 * resuming the device.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_set_active(dev);</div><div class='add'>+	pm_runtime_get_noresume(dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+	pm_runtime_set_autosuspend_delay(dev, 1000);</div><div class='add'>+	pm_runtime_use_autosuspend(dev);</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev(&amp;gc0308-&gt;sd);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "failed to register v4l subdev\n");</div><div class='add'>+		goto fail_rpm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+fail_rpm:</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	pm_runtime_put_noidle(dev);</div><div class='add'>+fail_power_off:</div><div class='add'>+	gc0308_power_off(dev);</div><div class='add'>+fail_subdev_cleanup:</div><div class='add'>+	v4l2_subdev_cleanup(&amp;gc0308-&gt;sd);</div><div class='add'>+fail_media_entity_cleanup:</div><div class='add'>+	media_entity_cleanup(&amp;gc0308-&gt;sd.entity);</div><div class='add'>+fail_ctrl_hdl_cleanup:</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;gc0308-&gt;hdl);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gc0308_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct gc0308 *gc0308 = i2c_get_clientdata(client);</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+</div><div class='add'>+	v4l2_async_unregister_subdev(&amp;gc0308-&gt;sd);</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;gc0308-&gt;hdl);</div><div class='add'>+	media_entity_cleanup(&amp;gc0308-&gt;sd.entity);</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	if (!pm_runtime_status_suspended(dev))</div><div class='add'>+		gc0308_power_off(dev);</div><div class='add'>+	pm_runtime_set_suspended(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops gc0308_pm_ops = {</div><div class='add'>+	SET_RUNTIME_PM_OPS(gc0308_power_off, gc0308_power_on, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gc0308_of_match[] = {</div><div class='add'>+	{ .compatible = "galaxycore,gc0308" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, gc0308_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver gc0308_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name  = "gc0308",</div><div class='add'>+		.pm = &amp;gc0308_pm_ops,</div><div class='add'>+		.of_match_table = gc0308_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe  = gc0308_probe,</div><div class='add'>+	.remove = gc0308_remove,</div><div class='add'>+};</div><div class='add'>+module_i2c_driver(gc0308_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("GalaxyCore GC0308 Camera Driver");</div><div class='add'>+MODULE_AUTHOR("Sebastian Reichel &lt;sre@kernel.org&gt;");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c<br/>new file mode 100644<br/>index 000000000000..bef7b0e056a8<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/gc2145.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/gc2145.c</a></div><div class='hunk'>@@ -0,0 +1,1450 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * A V4L2 driver for Galaxycore GC2145 camera.</div><div class='add'>+ * Copyright (C) 2023, STMicroelectronics SA</div><div class='add'>+ *</div><div class='add'>+ * Inspired by the imx219.c driver</div><div class='add'>+ *</div><div class='add'>+ * Datasheet v1.0 available at http://files.pine64.org/doc/datasheet/PinebookPro/GC2145%20CSP%20DataSheet%20release%20V1.0_20131201.pdf</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;media/mipi-csi2.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-mediabus.h&gt;</div><div class='add'>+</div><div class='add'>+/* Chip ID */</div><div class='add'>+#define GC2145_CHIP_ID		0x2145</div><div class='add'>+</div><div class='add'>+/* Page 0 */</div><div class='add'>+#define GC2145_REG_EXPOSURE	CCI_REG16(0x03)</div><div class='add'>+#define GC2145_REG_HBLANK	CCI_REG16(0x05)</div><div class='add'>+#define GC2145_REG_VBLANK	CCI_REG16(0x07)</div><div class='add'>+#define GC2145_REG_ROW_START	CCI_REG16(0x09)</div><div class='add'>+#define GC2145_REG_COL_START	CCI_REG16(0x0b)</div><div class='add'>+#define GC2145_REG_WIN_HEIGHT	CCI_REG16(0x0d)</div><div class='add'>+#define GC2145_REG_WIN_WIDTH	CCI_REG16(0x0f)</div><div class='add'>+#define GC2145_REG_ANALOG_MODE1	CCI_REG8(0x17)</div><div class='add'>+#define GC2145_REG_OUTPUT_FMT	CCI_REG8(0x84)</div><div class='add'>+#define GC2145_REG_SYNC_MODE	CCI_REG8(0x86)</div><div class='add'>+#define GC2145_SYNC_MODE_COL_SWITCH	BIT(4)</div><div class='add'>+#define GC2145_SYNC_MODE_ROW_SWITCH	BIT(5)</div><div class='add'>+#define GC2145_REG_BYPASS_MODE	CCI_REG8(0x89)</div><div class='add'>+#define GC2145_BYPASS_MODE_SWITCH	BIT(5)</div><div class='add'>+#define GC2145_REG_DEBUG_MODE2	CCI_REG8(0x8c)</div><div class='add'>+#define GC2145_REG_DEBUG_MODE3	CCI_REG8(0x8d)</div><div class='add'>+#define GC2145_REG_CROP_ENABLE	CCI_REG8(0x90)</div><div class='add'>+#define GC2145_REG_CROP_Y	CCI_REG16(0x91)</div><div class='add'>+#define GC2145_REG_CROP_X	CCI_REG16(0x93)</div><div class='add'>+#define GC2145_REG_CROP_HEIGHT	CCI_REG16(0x95)</div><div class='add'>+#define GC2145_REG_CROP_WIDTH	CCI_REG16(0x97)</div><div class='add'>+#define GC2145_REG_GLOBAL_GAIN	CCI_REG8(0xb0)</div><div class='add'>+#define GC2145_REG_CHIP_ID	CCI_REG16(0xf0)</div><div class='add'>+#define GC2145_REG_PAD_IO	CCI_REG8(0xf2)</div><div class='add'>+#define GC2145_REG_PAGE_SELECT	CCI_REG8(0xfe)</div><div class='add'>+/* Page 3 */</div><div class='add'>+#define GC2145_REG_DPHY_ANALOG_MODE1	CCI_REG8(0x01)</div><div class='add'>+#define GC2145_DPHY_MODE_PHY_CLK_EN	BIT(0)</div><div class='add'>+#define GC2145_DPHY_MODE_PHY_LANE0_EN	BIT(1)</div><div class='add'>+#define GC2145_DPHY_MODE_PHY_LANE1_EN	BIT(2)</div><div class='add'>+#define GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL	BIT(7)</div><div class='add'>+#define GC2145_REG_DPHY_ANALOG_MODE2	CCI_REG8(0x02)</div><div class='add'>+#define GC2145_DPHY_CLK_DIFF(a)		((a) &amp; 0x07)</div><div class='add'>+#define GC2145_DPHY_LANE0_DIFF(a)	(((a) &amp; 0x07) &lt;&lt; 4)</div><div class='add'>+#define GC2145_REG_DPHY_ANALOG_MODE3	CCI_REG8(0x03)</div><div class='add'>+#define GC2145_DPHY_LANE1_DIFF(a)	((a) &amp; 0x07)</div><div class='add'>+#define GC2145_DPHY_CLK_DELAY		BIT(4)</div><div class='add'>+#define GC2145_DPHY_LANE0_DELAY		BIT(5)</div><div class='add'>+#define GC2145_DPHY_LANE1_DELAY		BIT(6)</div><div class='add'>+#define GC2145_REG_FIFO_FULL_LVL_LOW	CCI_REG8(0x04)</div><div class='add'>+#define GC2145_REG_FIFO_FULL_LVL_HIGH	CCI_REG8(0x05)</div><div class='add'>+#define GC2145_REG_FIFO_MODE		CCI_REG8(0x06)</div><div class='add'>+#define GC2145_FIFO_MODE_READ_GATE	BIT(3)</div><div class='add'>+#define GC2145_FIFO_MODE_MIPI_CLK_MODULE	BIT(7)</div><div class='add'>+#define GC2145_REG_BUF_CSI2_MODE	CCI_REG8(0x10)</div><div class='add'>+#define GC2145_CSI2_MODE_DOUBLE		BIT(0)</div><div class='add'>+#define GC2145_CSI2_MODE_RAW8		BIT(2)</div><div class='add'>+#define GC2145_CSI2_MODE_MIPI_EN	BIT(4)</div><div class='add'>+#define GC2145_CSI2_MODE_EN		BIT(7)</div><div class='add'>+#define GC2145_REG_MIPI_DT	CCI_REG8(0x11)</div><div class='add'>+#define GC2145_REG_LWC_LOW	CCI_REG8(0x12)</div><div class='add'>+#define GC2145_REG_LWC_HIGH	CCI_REG8(0x13)</div><div class='add'>+#define GC2145_REG_DPHY_MODE	CCI_REG8(0x15)</div><div class='add'>+#define GC2145_DPHY_MODE_TRIGGER_PROG	BIT(4)</div><div class='add'>+#define GC2145_REG_FIFO_GATE_MODE	CCI_REG8(0x17)</div><div class='add'>+#define GC2145_REG_T_LPX	CCI_REG8(0x21)</div><div class='add'>+#define GC2145_REG_T_CLK_HS_PREPARE	CCI_REG8(0x22)</div><div class='add'>+#define GC2145_REG_T_CLK_ZERO	CCI_REG8(0x23)</div><div class='add'>+#define GC2145_REG_T_CLK_PRE	CCI_REG8(0x24)</div><div class='add'>+#define GC2145_REG_T_CLK_POST	CCI_REG8(0x25)</div><div class='add'>+#define GC2145_REG_T_CLK_TRAIL	CCI_REG8(0x26)</div><div class='add'>+#define GC2145_REG_T_HS_EXIT	CCI_REG8(0x27)</div><div class='add'>+#define GC2145_REG_T_WAKEUP	CCI_REG8(0x28)</div><div class='add'>+#define GC2145_REG_T_HS_PREPARE	CCI_REG8(0x29)</div><div class='add'>+#define GC2145_REG_T_HS_ZERO	CCI_REG8(0x2a)</div><div class='add'>+#define GC2145_REG_T_HS_TRAIL	CCI_REG8(0x2b)</div><div class='add'>+</div><div class='add'>+/* External clock frequency is 24.0MHz */</div><div class='add'>+#define GC2145_XCLK_FREQ	(24 * HZ_PER_MHZ)</div><div class='add'>+</div><div class='add'>+#define GC2145_NATIVE_WIDTH	1616U</div><div class='add'>+#define GC2145_NATIVE_HEIGHT	1232U</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct gc2145_mode - GC2145 mode description</div><div class='add'>+ * @width: frame width (in pixels)</div><div class='add'>+ * @height: frame height (in pixels)</div><div class='add'>+ * @reg_seq: registers config sequence to enter into the mode</div><div class='add'>+ * @reg_seq_size: size of the sequence</div><div class='add'>+ * @pixel_rate: pixel rate associated with the mode</div><div class='add'>+ * @crop: window area captured</div><div class='add'>+ * @hblank: default horizontal blanking</div><div class='add'>+ * @vblank: default vertical blanking</div><div class='add'>+ * @link_freq_index: index within the link frequency menu</div><div class='add'>+ */</div><div class='add'>+struct gc2145_mode {</div><div class='add'>+	unsigned int width;</div><div class='add'>+	unsigned int height;</div><div class='add'>+	const struct cci_reg_sequence *reg_seq;</div><div class='add'>+	size_t reg_seq_size;</div><div class='add'>+	unsigned long pixel_rate;</div><div class='add'>+	struct v4l2_rect crop;</div><div class='add'>+	unsigned int hblank;</div><div class='add'>+	unsigned int vblank;</div><div class='add'>+	unsigned int link_freq_index;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_DEFAULT_EXPOSURE	0x04e2</div><div class='add'>+#define GC2145_DEFAULT_GLOBAL_GAIN	0x55</div><div class='add'>+static const struct cci_reg_sequence gc2145_common_regs[] = {</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	/* SH Delay */</div><div class='add'>+	{CCI_REG8(0x12), 0x2e},</div><div class='add'>+	/* Flip */</div><div class='add'>+	{GC2145_REG_ANALOG_MODE1, 0x14},</div><div class='add'>+	/* Analog Conf */</div><div class='add'>+	{CCI_REG8(0x18), 0x22}, {CCI_REG8(0x19), 0x0e}, {CCI_REG8(0x1a), 0x01},</div><div class='add'>+	{CCI_REG8(0x1b), 0x4b}, {CCI_REG8(0x1c), 0x07}, {CCI_REG8(0x1d), 0x10},</div><div class='add'>+	{CCI_REG8(0x1e), 0x88}, {CCI_REG8(0x1f), 0x78}, {CCI_REG8(0x20), 0x03},</div><div class='add'>+	{CCI_REG8(0x21), 0x40}, {CCI_REG8(0x22), 0xa0}, {CCI_REG8(0x24), 0x16},</div><div class='add'>+	{CCI_REG8(0x25), 0x01}, {CCI_REG8(0x26), 0x10}, {CCI_REG8(0x2d), 0x60},</div><div class='add'>+	{CCI_REG8(0x30), 0x01}, {CCI_REG8(0x31), 0x90}, {CCI_REG8(0x33), 0x06},</div><div class='add'>+	{CCI_REG8(0x34), 0x01},</div><div class='add'>+	/* ISP related */</div><div class='add'>+	{CCI_REG8(0x80), 0x7f}, {CCI_REG8(0x81), 0x26}, {CCI_REG8(0x82), 0xfa},</div><div class='add'>+	{CCI_REG8(0x83), 0x00}, {CCI_REG8(0x84), 0x02}, {CCI_REG8(0x86), 0x02},</div><div class='add'>+	{CCI_REG8(0x88), 0x03},</div><div class='add'>+	{GC2145_REG_BYPASS_MODE, 0x03},</div><div class='add'>+	{CCI_REG8(0x85), 0x08}, {CCI_REG8(0x8a), 0x00}, {CCI_REG8(0x8b), 0x00},</div><div class='add'>+	{GC2145_REG_GLOBAL_GAIN, GC2145_DEFAULT_GLOBAL_GAIN},</div><div class='add'>+	{CCI_REG8(0xc3), 0x00}, {CCI_REG8(0xc4), 0x80}, {CCI_REG8(0xc5), 0x90},</div><div class='add'>+	{CCI_REG8(0xc6), 0x3b}, {CCI_REG8(0xc7), 0x46},</div><div class='add'>+	/* BLK */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	{CCI_REG8(0x40), 0x42}, {CCI_REG8(0x41), 0x00}, {CCI_REG8(0x43), 0x5b},</div><div class='add'>+	{CCI_REG8(0x5e), 0x00}, {CCI_REG8(0x5f), 0x00}, {CCI_REG8(0x60), 0x00},</div><div class='add'>+	{CCI_REG8(0x61), 0x00}, {CCI_REG8(0x62), 0x00}, {CCI_REG8(0x63), 0x00},</div><div class='add'>+	{CCI_REG8(0x64), 0x00}, {CCI_REG8(0x65), 0x00}, {CCI_REG8(0x66), 0x20},</div><div class='add'>+	{CCI_REG8(0x67), 0x20}, {CCI_REG8(0x68), 0x20}, {CCI_REG8(0x69), 0x20},</div><div class='add'>+	{CCI_REG8(0x76), 0x00}, {CCI_REG8(0x6a), 0x08}, {CCI_REG8(0x6b), 0x08},</div><div class='add'>+	{CCI_REG8(0x6c), 0x08}, {CCI_REG8(0x6d), 0x08}, {CCI_REG8(0x6e), 0x08},</div><div class='add'>+	{CCI_REG8(0x6f), 0x08}, {CCI_REG8(0x70), 0x08}, {CCI_REG8(0x71), 0x08},</div><div class='add'>+	{CCI_REG8(0x76), 0x00}, {CCI_REG8(0x72), 0xf0}, {CCI_REG8(0x7e), 0x3c},</div><div class='add'>+	{CCI_REG8(0x7f), 0x00},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x48), 0x15}, {CCI_REG8(0x49), 0x00}, {CCI_REG8(0x4b), 0x0b},</div><div class='add'>+	/* AEC */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	{GC2145_REG_EXPOSURE, GC2145_DEFAULT_EXPOSURE},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x01), 0x04}, {CCI_REG8(0x02), 0xc0}, {CCI_REG8(0x03), 0x04},</div><div class='add'>+	{CCI_REG8(0x04), 0x90}, {CCI_REG8(0x05), 0x30}, {CCI_REG8(0x06), 0x90},</div><div class='add'>+	{CCI_REG8(0x07), 0x30}, {CCI_REG8(0x08), 0x80}, {CCI_REG8(0x09), 0x00},</div><div class='add'>+	{CCI_REG8(0x0a), 0x82}, {CCI_REG8(0x0b), 0x11}, {CCI_REG8(0x0c), 0x10},</div><div class='add'>+	{CCI_REG8(0x11), 0x10}, {CCI_REG8(0x13), 0x7b}, {CCI_REG8(0x17), 0x00},</div><div class='add'>+	{CCI_REG8(0x1c), 0x11}, {CCI_REG8(0x1e), 0x61}, {CCI_REG8(0x1f), 0x35},</div><div class='add'>+	{CCI_REG8(0x20), 0x40}, {CCI_REG8(0x22), 0x40}, {CCI_REG8(0x23), 0x20},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x0f), 0x04},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x12), 0x35}, {CCI_REG8(0x15), 0xb0}, {CCI_REG8(0x10), 0x31},</div><div class='add'>+	{CCI_REG8(0x3e), 0x28}, {CCI_REG8(0x3f), 0xb0}, {CCI_REG8(0x40), 0x90},</div><div class='add'>+	{CCI_REG8(0x41), 0x0f},</div><div class='add'>+	/* INTPEE */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x90), 0x6c}, {CCI_REG8(0x91), 0x03}, {CCI_REG8(0x92), 0xcb},</div><div class='add'>+	{CCI_REG8(0x94), 0x33}, {CCI_REG8(0x95), 0x84}, {CCI_REG8(0x97), 0x65},</div><div class='add'>+	{CCI_REG8(0xa2), 0x11},</div><div class='add'>+	/* DNDD */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x80), 0xc1}, {CCI_REG8(0x81), 0x08}, {CCI_REG8(0x82), 0x05},</div><div class='add'>+	{CCI_REG8(0x83), 0x08}, {CCI_REG8(0x84), 0x0a}, {CCI_REG8(0x86), 0xf0},</div><div class='add'>+	{CCI_REG8(0x87), 0x50}, {CCI_REG8(0x88), 0x15}, {CCI_REG8(0x89), 0xb0},</div><div class='add'>+	{CCI_REG8(0x8a), 0x30}, {CCI_REG8(0x8b), 0x10},</div><div class='add'>+	/* ASDE */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x21), 0x04},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0xa3), 0x50}, {CCI_REG8(0xa4), 0x20}, {CCI_REG8(0xa5), 0x40},</div><div class='add'>+	{CCI_REG8(0xa6), 0x80}, {CCI_REG8(0xab), 0x40}, {CCI_REG8(0xae), 0x0c},</div><div class='add'>+	{CCI_REG8(0xb3), 0x46}, {CCI_REG8(0xb4), 0x64}, {CCI_REG8(0xb6), 0x38},</div><div class='add'>+	{CCI_REG8(0xb7), 0x01}, {CCI_REG8(0xb9), 0x2b}, {CCI_REG8(0x3c), 0x04},</div><div class='add'>+	{CCI_REG8(0x3d), 0x15}, {CCI_REG8(0x4b), 0x06}, {CCI_REG8(0x4c), 0x20},</div><div class='add'>+	/* Gamma */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x10), 0x09}, {CCI_REG8(0x11), 0x0d}, {CCI_REG8(0x12), 0x13},</div><div class='add'>+	{CCI_REG8(0x13), 0x19}, {CCI_REG8(0x14), 0x27}, {CCI_REG8(0x15), 0x37},</div><div class='add'>+	{CCI_REG8(0x16), 0x45}, {CCI_REG8(0x17), 0x53}, {CCI_REG8(0x18), 0x69},</div><div class='add'>+	{CCI_REG8(0x19), 0x7d}, {CCI_REG8(0x1a), 0x8f}, {CCI_REG8(0x1b), 0x9d},</div><div class='add'>+	{CCI_REG8(0x1c), 0xa9}, {CCI_REG8(0x1d), 0xbd}, {CCI_REG8(0x1e), 0xcd},</div><div class='add'>+	{CCI_REG8(0x1f), 0xd9}, {CCI_REG8(0x20), 0xe3}, {CCI_REG8(0x21), 0xea},</div><div class='add'>+	{CCI_REG8(0x22), 0xef}, {CCI_REG8(0x23), 0xf5}, {CCI_REG8(0x24), 0xf9},</div><div class='add'>+	{CCI_REG8(0x25), 0xff},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	{CCI_REG8(0xc6), 0x20}, {CCI_REG8(0xc7), 0x2b},</div><div class='add'>+	/* Gamma 2 */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x26), 0x0f}, {CCI_REG8(0x27), 0x14}, {CCI_REG8(0x28), 0x19},</div><div class='add'>+	{CCI_REG8(0x29), 0x1e}, {CCI_REG8(0x2a), 0x27}, {CCI_REG8(0x2b), 0x33},</div><div class='add'>+	{CCI_REG8(0x2c), 0x3b}, {CCI_REG8(0x2d), 0x45}, {CCI_REG8(0x2e), 0x59},</div><div class='add'>+	{CCI_REG8(0x2f), 0x69}, {CCI_REG8(0x30), 0x7c}, {CCI_REG8(0x31), 0x89},</div><div class='add'>+	{CCI_REG8(0x32), 0x98}, {CCI_REG8(0x33), 0xae}, {CCI_REG8(0x34), 0xc0},</div><div class='add'>+	{CCI_REG8(0x35), 0xcf}, {CCI_REG8(0x36), 0xda}, {CCI_REG8(0x37), 0xe2},</div><div class='add'>+	{CCI_REG8(0x38), 0xe9}, {CCI_REG8(0x39), 0xf3}, {CCI_REG8(0x3a), 0xf9},</div><div class='add'>+	{CCI_REG8(0x3b), 0xff},</div><div class='add'>+	/* YCP */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0xd1), 0x32}, {CCI_REG8(0xd2), 0x32}, {CCI_REG8(0xd3), 0x40},</div><div class='add'>+	{CCI_REG8(0xd6), 0xf0}, {CCI_REG8(0xd7), 0x10}, {CCI_REG8(0xd8), 0xda},</div><div class='add'>+	{CCI_REG8(0xdd), 0x14}, {CCI_REG8(0xde), 0x86}, {CCI_REG8(0xed), 0x80},</div><div class='add'>+	{CCI_REG8(0xee), 0x00}, {CCI_REG8(0xef), 0x3f}, {CCI_REG8(0xd8), 0xd8},</div><div class='add'>+	/* ABS */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x9f), 0x40},</div><div class='add'>+	/* LSC */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0xc2), 0x14}, {CCI_REG8(0xc3), 0x0d}, {CCI_REG8(0xc4), 0x0c},</div><div class='add'>+	{CCI_REG8(0xc8), 0x15}, {CCI_REG8(0xc9), 0x0d}, {CCI_REG8(0xca), 0x0a},</div><div class='add'>+	{CCI_REG8(0xbc), 0x24}, {CCI_REG8(0xbd), 0x10}, {CCI_REG8(0xbe), 0x0b},</div><div class='add'>+	{CCI_REG8(0xb6), 0x25}, {CCI_REG8(0xb7), 0x16}, {CCI_REG8(0xb8), 0x15},</div><div class='add'>+	{CCI_REG8(0xc5), 0x00}, {CCI_REG8(0xc6), 0x00}, {CCI_REG8(0xc7), 0x00},</div><div class='add'>+	{CCI_REG8(0xcb), 0x00}, {CCI_REG8(0xcc), 0x00}, {CCI_REG8(0xcd), 0x00},</div><div class='add'>+	{CCI_REG8(0xbf), 0x07}, {CCI_REG8(0xc0), 0x00}, {CCI_REG8(0xc1), 0x00},</div><div class='add'>+	{CCI_REG8(0xb9), 0x00}, {CCI_REG8(0xba), 0x00}, {CCI_REG8(0xbb), 0x00},</div><div class='add'>+	{CCI_REG8(0xaa), 0x01}, {CCI_REG8(0xab), 0x01}, {CCI_REG8(0xac), 0x00},</div><div class='add'>+	{CCI_REG8(0xad), 0x05}, {CCI_REG8(0xae), 0x06}, {CCI_REG8(0xaf), 0x0e},</div><div class='add'>+	{CCI_REG8(0xb0), 0x0b}, {CCI_REG8(0xb1), 0x07}, {CCI_REG8(0xb2), 0x06},</div><div class='add'>+	{CCI_REG8(0xb3), 0x17}, {CCI_REG8(0xb4), 0x0e}, {CCI_REG8(0xb5), 0x0e},</div><div class='add'>+	{CCI_REG8(0xd0), 0x09}, {CCI_REG8(0xd1), 0x00}, {CCI_REG8(0xd2), 0x00},</div><div class='add'>+	{CCI_REG8(0xd6), 0x08}, {CCI_REG8(0xd7), 0x00}, {CCI_REG8(0xd8), 0x00},</div><div class='add'>+	{CCI_REG8(0xd9), 0x00}, {CCI_REG8(0xda), 0x00}, {CCI_REG8(0xdb), 0x00},</div><div class='add'>+	{CCI_REG8(0xd3), 0x0a}, {CCI_REG8(0xd4), 0x00}, {CCI_REG8(0xd5), 0x00},</div><div class='add'>+	{CCI_REG8(0xa4), 0x00}, {CCI_REG8(0xa5), 0x00}, {CCI_REG8(0xa6), 0x77},</div><div class='add'>+	{CCI_REG8(0xa7), 0x77}, {CCI_REG8(0xa8), 0x77}, {CCI_REG8(0xa9), 0x77},</div><div class='add'>+	{CCI_REG8(0xa1), 0x80}, {CCI_REG8(0xa2), 0x80},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0xdf), 0x0d}, {CCI_REG8(0xdc), 0x25}, {CCI_REG8(0xdd), 0x30},</div><div class='add'>+	{CCI_REG8(0xe0), 0x77}, {CCI_REG8(0xe1), 0x80}, {CCI_REG8(0xe2), 0x77},</div><div class='add'>+	{CCI_REG8(0xe3), 0x90}, {CCI_REG8(0xe6), 0x90}, {CCI_REG8(0xe7), 0xa0},</div><div class='add'>+	{CCI_REG8(0xe8), 0x90}, {CCI_REG8(0xe9), 0xa0},</div><div class='add'>+	/* AWB */</div><div class='add'>+	/* measure window */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	{CCI_REG8(0xec), 0x06}, {CCI_REG8(0xed), 0x04}, {CCI_REG8(0xee), 0x60},</div><div class='add'>+	{CCI_REG8(0xef), 0x90}, {CCI_REG8(0xb6), 0x01},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4b), 0x01},</div><div class='add'>+	{CCI_REG8(0x4f), 0x00},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x71}, {CCI_REG8(0x4e), 0x01},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x91}, {CCI_REG8(0x4e), 0x01},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x70}, {CCI_REG8(0x4e), 0x01},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x90}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xb0}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8f}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6f}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaf}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xd0}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xf0}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcf}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xef}, {CCI_REG8(0x4e), 0x02},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6e}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8e}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xae}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xce}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4d}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6d}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8d}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xad}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcd}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4c}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6c}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8c}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xac}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcc}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcb}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4b}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6b}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8b}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xab}, {CCI_REG8(0x4e), 0x03},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaa}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x04},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0b}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0a}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xeb}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xea}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x29}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x2a}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x4a}, {CCI_REG8(0x4e), 0x05},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x49}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x48}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x68}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe9}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc8}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe8}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa7}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc7}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe7}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x07}, {CCI_REG8(0x4e), 0x07},</div><div class='add'>+	{CCI_REG8(0x4f), 0x01},</div><div class='add'>+	{CCI_REG8(0x50), 0x80}, {CCI_REG8(0x51), 0xa8}, {CCI_REG8(0x52), 0x47},</div><div class='add'>+	{CCI_REG8(0x53), 0x38}, {CCI_REG8(0x54), 0xc7}, {CCI_REG8(0x56), 0x0e},</div><div class='add'>+	{CCI_REG8(0x58), 0x08}, {CCI_REG8(0x5b), 0x00}, {CCI_REG8(0x5c), 0x74},</div><div class='add'>+	{CCI_REG8(0x5d), 0x8b}, {CCI_REG8(0x61), 0xdb}, {CCI_REG8(0x62), 0xb8},</div><div class='add'>+	{CCI_REG8(0x63), 0x86}, {CCI_REG8(0x64), 0xc0}, {CCI_REG8(0x65), 0x04},</div><div class='add'>+	{CCI_REG8(0x67), 0xa8}, {CCI_REG8(0x68), 0xb0}, {CCI_REG8(0x69), 0x00},</div><div class='add'>+	{CCI_REG8(0x6a), 0xa8}, {CCI_REG8(0x6b), 0xb0}, {CCI_REG8(0x6c), 0xaf},</div><div class='add'>+	{CCI_REG8(0x6d), 0x8b}, {CCI_REG8(0x6e), 0x50}, {CCI_REG8(0x6f), 0x18},</div><div class='add'>+	{CCI_REG8(0x73), 0xf0}, {CCI_REG8(0x70), 0x0d}, {CCI_REG8(0x71), 0x60},</div><div class='add'>+	{CCI_REG8(0x72), 0x80}, {CCI_REG8(0x74), 0x01}, {CCI_REG8(0x75), 0x01},</div><div class='add'>+	{CCI_REG8(0x7f), 0x0c}, {CCI_REG8(0x76), 0x70}, {CCI_REG8(0x77), 0x58},</div><div class='add'>+	{CCI_REG8(0x78), 0xa0}, {CCI_REG8(0x79), 0x5e}, {CCI_REG8(0x7a), 0x54},</div><div class='add'>+	{CCI_REG8(0x7b), 0x58},</div><div class='add'>+	/* CC */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0xc0), 0x01}, {CCI_REG8(0xc1), 0x44}, {CCI_REG8(0xc2), 0xfd},</div><div class='add'>+	{CCI_REG8(0xc3), 0x04}, {CCI_REG8(0xc4), 0xf0}, {CCI_REG8(0xc5), 0x48},</div><div class='add'>+	{CCI_REG8(0xc6), 0xfd}, {CCI_REG8(0xc7), 0x46}, {CCI_REG8(0xc8), 0xfd},</div><div class='add'>+	{CCI_REG8(0xc9), 0x02}, {CCI_REG8(0xca), 0xe0}, {CCI_REG8(0xcb), 0x45},</div><div class='add'>+	{CCI_REG8(0xcc), 0xec}, {CCI_REG8(0xcd), 0x48}, {CCI_REG8(0xce), 0xf0},</div><div class='add'>+	{CCI_REG8(0xcf), 0xf0}, {CCI_REG8(0xe3), 0x0c}, {CCI_REG8(0xe4), 0x4b},</div><div class='add'>+	{CCI_REG8(0xe5), 0xe0},</div><div class='add'>+	/* ABS */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	{CCI_REG8(0x9f), 0x40},</div><div class='add'>+	/* Dark sun */</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x02},</div><div class='add'>+	{CCI_REG8(0x40), 0xbf}, {CCI_REG8(0x46), 0xcf},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_640_480_PIXELRATE	30000000</div><div class='add'>+#define GC2145_640_480_LINKFREQ		120000000</div><div class='add'>+#define GC2145_640_480_HBLANK		0x0130</div><div class='add'>+#define GC2145_640_480_VBLANK		0x000c</div><div class='add'>+static const struct cci_reg_sequence gc2145_mode_640_480_regs[] = {</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},</div><div class='add'>+	{CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x86},</div><div class='add'>+	{CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},</div><div class='add'>+	/* Disable PAD IO */</div><div class='add'>+	{GC2145_REG_PAD_IO, 0x00},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	/* Row/Col start - 0/0 */</div><div class='add'>+	{GC2145_REG_ROW_START, 0x0000},</div><div class='add'>+	{GC2145_REG_COL_START, 0x0000},</div><div class='add'>+	/* Window size 1216/1618 */</div><div class='add'>+	{GC2145_REG_WIN_HEIGHT, 0x04c0},</div><div class='add'>+	{GC2145_REG_WIN_WIDTH, 0x0652},</div><div class='add'>+	/* Scalar more */</div><div class='add'>+	{CCI_REG8(0xfd), 0x01}, {CCI_REG8(0xfa), 0x00},</div><div class='add'>+	/* Crop 640-480@0-0 */</div><div class='add'>+	{GC2145_REG_CROP_ENABLE, 0x01},</div><div class='add'>+	{GC2145_REG_CROP_Y, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_X, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_HEIGHT, 0x01e0},</div><div class='add'>+	{GC2145_REG_CROP_WIDTH, 0x0280},</div><div class='add'>+	/* Subsampling configuration */</div><div class='add'>+	{CCI_REG8(0x99), 0x55}, {CCI_REG8(0x9a), 0x06}, {CCI_REG8(0x9b), 0x01},</div><div class='add'>+	{CCI_REG8(0x9c), 0x23}, {CCI_REG8(0x9d), 0x00}, {CCI_REG8(0x9e), 0x00},</div><div class='add'>+	{CCI_REG8(0x9f), 0x01}, {CCI_REG8(0xa0), 0x23}, {CCI_REG8(0xa1), 0x00},</div><div class='add'>+	{CCI_REG8(0xa2), 0x00},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	/* AEC anti-flicker */</div><div class='add'>+	{CCI_REG16(0x25), 0x0175},</div><div class='add'>+	/* AEC exposure level 1-5 */</div><div class='add'>+	{CCI_REG16(0x27), 0x045f}, {CCI_REG16(0x29), 0x045f},</div><div class='add'>+	{CCI_REG16(0x2b), 0x045f}, {CCI_REG16(0x2d), 0x045f},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_1280_720_PIXELRATE	48000000</div><div class='add'>+#define GC2145_1280_720_LINKFREQ	192000000</div><div class='add'>+#define GC2145_1280_720_HBLANK		0x0156</div><div class='add'>+#define GC2145_1280_720_VBLANK		0x0011</div><div class='add'>+static const struct cci_reg_sequence gc2145_mode_1280_720_regs[] = {</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},</div><div class='add'>+	{CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x83},</div><div class='add'>+	{CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},</div><div class='add'>+	/* Disable PAD IO */</div><div class='add'>+	{GC2145_REG_PAD_IO, 0x00},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	/* Row/Col start - 240/160 */</div><div class='add'>+	{GC2145_REG_ROW_START, 0x00f0},</div><div class='add'>+	{GC2145_REG_COL_START, 0x00a0},</div><div class='add'>+	/* Window size 736/1296 */</div><div class='add'>+	{GC2145_REG_WIN_HEIGHT, 0x02e0},</div><div class='add'>+	{GC2145_REG_WIN_WIDTH, 0x0510},</div><div class='add'>+	/* Crop 1280-720@0-0 */</div><div class='add'>+	{GC2145_REG_CROP_ENABLE, 0x01},</div><div class='add'>+	{GC2145_REG_CROP_Y, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_X, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_HEIGHT, 0x02d0},</div><div class='add'>+	{GC2145_REG_CROP_WIDTH, 0x0500},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	/* AEC anti-flicker */</div><div class='add'>+	{CCI_REG16(0x25), 0x00e6},</div><div class='add'>+	/* AEC exposure level 1-5 */</div><div class='add'>+	{CCI_REG16(0x27), 0x02b2}, {CCI_REG16(0x29), 0x02b2},</div><div class='add'>+	{CCI_REG16(0x2b), 0x02b2}, {CCI_REG16(0x2d), 0x02b2},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_1600_1200_PIXELRATE	60000000</div><div class='add'>+#define GC2145_1600_1200_LINKFREQ	240000000</div><div class='add'>+#define GC2145_1600_1200_HBLANK		0x0156</div><div class='add'>+#define GC2145_1600_1200_VBLANK		0x0010</div><div class='add'>+static const struct cci_reg_sequence gc2145_mode_1600_1200_regs[] = {</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},</div><div class='add'>+	{CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x84},</div><div class='add'>+	{CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},</div><div class='add'>+	/* Disable PAD IO */</div><div class='add'>+	{GC2145_REG_PAD_IO, 0x00},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x00},</div><div class='add'>+	/* Row/Col start - 0/0 */</div><div class='add'>+	{GC2145_REG_ROW_START, 0x0000},</div><div class='add'>+	{GC2145_REG_COL_START, 0x0000},</div><div class='add'>+	/* Window size: 1216/1618 */</div><div class='add'>+	{GC2145_REG_WIN_HEIGHT, 0x04c0},</div><div class='add'>+	{GC2145_REG_WIN_WIDTH, 0x0652},</div><div class='add'>+	/* Crop 1600-1200@0-0 */</div><div class='add'>+	{GC2145_REG_CROP_ENABLE, 0x01},</div><div class='add'>+	{GC2145_REG_CROP_Y, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_X, 0x0000},</div><div class='add'>+	{GC2145_REG_CROP_HEIGHT, 0x04b0},</div><div class='add'>+	{GC2145_REG_CROP_WIDTH, 0x0640},</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x01},</div><div class='add'>+	/* AEC anti-flicker */</div><div class='add'>+	{CCI_REG16(0x25), 0x00fa},</div><div class='add'>+	/* AEC exposure level 1-5 */</div><div class='add'>+	{CCI_REG16(0x27), 0x04e2}, {CCI_REG16(0x29), 0x04e2},</div><div class='add'>+	{CCI_REG16(0x2b), 0x04e2}, {CCI_REG16(0x2d), 0x04e2},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const s64 gc2145_link_freq_menu[] = {</div><div class='add'>+	GC2145_640_480_LINKFREQ,</div><div class='add'>+	GC2145_1280_720_LINKFREQ,</div><div class='add'>+	GC2145_1600_1200_LINKFREQ,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Regulators supplies */</div><div class='add'>+static const char * const gc2145_supply_name[] = {</div><div class='add'>+	"iovdd", /* Digital I/O (1.7-3V) suppply */</div><div class='add'>+	"avdd",  /* Analog (2.7-3V) supply */</div><div class='add'>+	"dvdd",  /* Digital Core (1.7-1.9V) supply */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name)</div><div class='add'>+</div><div class='add'>+/* Mode configs */</div><div class='add'>+#define GC2145_MODE_640X480	0</div><div class='add'>+#define GC2145_MODE_1280X720	1</div><div class='add'>+#define GC2145_MODE_1600X1200	2</div><div class='add'>+static const struct gc2145_mode supported_modes[] = {</div><div class='add'>+	{</div><div class='add'>+		/* 640x480 30fps mode */</div><div class='add'>+		.width = 640,</div><div class='add'>+		.height = 480,</div><div class='add'>+		.reg_seq = gc2145_mode_640_480_regs,</div><div class='add'>+		.reg_seq_size = ARRAY_SIZE(gc2145_mode_640_480_regs),</div><div class='add'>+		.pixel_rate = GC2145_640_480_PIXELRATE,</div><div class='add'>+		.crop = {</div><div class='add'>+			.top = 0,</div><div class='add'>+			.left = 0,</div><div class='add'>+			.width = 640,</div><div class='add'>+			.height = 480,</div><div class='add'>+		},</div><div class='add'>+		.hblank = GC2145_640_480_HBLANK,</div><div class='add'>+		.vblank = GC2145_640_480_VBLANK,</div><div class='add'>+		.link_freq_index = GC2145_MODE_640X480,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		/* 1280x720 30fps mode */</div><div class='add'>+		.width = 1280,</div><div class='add'>+		.height = 720,</div><div class='add'>+		.reg_seq = gc2145_mode_1280_720_regs,</div><div class='add'>+		.reg_seq_size = ARRAY_SIZE(gc2145_mode_1280_720_regs),</div><div class='add'>+		.pixel_rate = GC2145_1280_720_PIXELRATE,</div><div class='add'>+		.crop = {</div><div class='add'>+			.top = 160,</div><div class='add'>+			.left = 240,</div><div class='add'>+			.width = 1280,</div><div class='add'>+			.height = 720,</div><div class='add'>+		},</div><div class='add'>+		.hblank = GC2145_1280_720_HBLANK,</div><div class='add'>+		.vblank = GC2145_1280_720_VBLANK,</div><div class='add'>+		.link_freq_index = GC2145_MODE_1280X720,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		/* 1600x1200 20fps mode */</div><div class='add'>+		.width = 1600,</div><div class='add'>+		.height = 1200,</div><div class='add'>+		.reg_seq = gc2145_mode_1600_1200_regs,</div><div class='add'>+		.reg_seq_size = ARRAY_SIZE(gc2145_mode_1600_1200_regs),</div><div class='add'>+		.pixel_rate = GC2145_1600_1200_PIXELRATE,</div><div class='add'>+		.crop = {</div><div class='add'>+			.top = 0,</div><div class='add'>+			.left = 0,</div><div class='add'>+			.width = 1600,</div><div class='add'>+			.height = 1200,</div><div class='add'>+		},</div><div class='add'>+		.hblank = GC2145_1600_1200_HBLANK,</div><div class='add'>+		.vblank = GC2145_1600_1200_VBLANK,</div><div class='add'>+		.link_freq_index = GC2145_MODE_1600X1200,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct gc2145_format - GC2145 pixel format description</div><div class='add'>+ * @code: media bus (MBUS) associated code</div><div class='add'>+ * @datatype: MIPI CSI2 data type</div><div class='add'>+ * @output_fmt: GC2145 output format</div><div class='add'>+ * @switch_bit: GC2145 first/second switch</div><div class='add'>+ */</div><div class='add'>+struct gc2145_format {</div><div class='add'>+	unsigned int code;</div><div class='add'>+	unsigned char datatype;</div><div class='add'>+	unsigned char output_fmt;</div><div class='add'>+	bool switch_bit;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* All supported formats */</div><div class='add'>+static const struct gc2145_format supported_formats[] = {</div><div class='add'>+	{</div><div class='add'>+		.code		= MEDIA_BUS_FMT_UYVY8_1X16,</div><div class='add'>+		.datatype	= MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.output_fmt	= 0x00,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.code		= MEDIA_BUS_FMT_VYUY8_1X16,</div><div class='add'>+		.datatype	= MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.output_fmt	= 0x01,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.code		= MEDIA_BUS_FMT_YUYV8_1X16,</div><div class='add'>+		.datatype	= MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.output_fmt	= 0x02,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.code		= MEDIA_BUS_FMT_YVYU8_1X16,</div><div class='add'>+		.datatype	= MIPI_CSI2_DT_YUV422_8B,</div><div class='add'>+		.output_fmt	= 0x03,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.code		= MEDIA_BUS_FMT_RGB565_1X16,</div><div class='add'>+		.datatype	= MIPI_CSI2_DT_RGB565,</div><div class='add'>+		.output_fmt	= 0x06,</div><div class='add'>+		.switch_bit	= true,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc2145_ctrls {</div><div class='add'>+	struct v4l2_ctrl_handler handler;</div><div class='add'>+	struct v4l2_ctrl *pixel_rate;</div><div class='add'>+	struct v4l2_ctrl *link_freq;</div><div class='add'>+	struct v4l2_ctrl *test_pattern;</div><div class='add'>+	struct v4l2_ctrl *hflip;</div><div class='add'>+	struct v4l2_ctrl *vflip;</div><div class='add'>+	struct v4l2_ctrl *hblank;</div><div class='add'>+	struct v4l2_ctrl *vblank;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct gc2145 {</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	struct clk *xclk;</div><div class='add'>+</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct gpio_desc *powerdown_gpio;</div><div class='add'>+	struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES];</div><div class='add'>+</div><div class='add'>+	/* V4L2 controls */</div><div class='add'>+	struct gc2145_ctrls ctrls;</div><div class='add'>+</div><div class='add'>+	/* Current mode */</div><div class='add'>+	const struct gc2145_mode *mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct gc2145 *to_gc2145(struct v4l2_subdev *_sd)</div><div class='add'>+{</div><div class='add'>+	return container_of(_sd, struct gc2145, sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct v4l2_subdev *gc2145_ctrl_to_sd(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	return &amp;container_of(ctrl-&gt;handler, struct gc2145,</div><div class='add'>+			     ctrls.handler)-&gt;sd;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct gc2145_format *</div><div class='add'>+gc2145_get_format_code(struct gc2145 *gc2145, u32 code)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(supported_formats); i++) {</div><div class='add'>+		if (supported_formats[i].code == code)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= ARRAY_SIZE(supported_formats))</div><div class='add'>+		i = 0;</div><div class='add'>+</div><div class='add'>+	return &amp;supported_formats[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gc2145_update_pad_format(struct gc2145 *gc2145,</div><div class='add'>+				     const struct gc2145_mode *mode,</div><div class='add'>+				     struct v4l2_mbus_framefmt *fmt, u32 code)</div><div class='add'>+{</div><div class='add'>+	fmt-&gt;code = code;</div><div class='add'>+	fmt-&gt;width = mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = mode-&gt;height;</div><div class='add'>+	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='add'>+	fmt-&gt;ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;</div><div class='add'>+	fmt-&gt;quantization = V4L2_QUANTIZATION_DEFAULT;</div><div class='add'>+	fmt-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *format;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+</div><div class='add'>+	/* Initialize pad format */</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	gc2145_update_pad_format(gc2145, &amp;supported_modes[0], format,</div><div class='add'>+				 MEDIA_BUS_FMT_RGB565_1X16);</div><div class='add'>+</div><div class='add'>+	/* Initialize crop rectangle. */</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='add'>+	*crop = supported_modes[0].crop;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_get_selection(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state,</div><div class='add'>+				struct v4l2_subdev_selection *sel)</div><div class='add'>+{</div><div class='add'>+	switch (sel-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_NATIVE_SIZE:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = GC2145_NATIVE_WIDTH;</div><div class='add'>+		sel-&gt;r.height = GC2145_NATIVE_HEIGHT;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = 1600;</div><div class='add'>+		sel-&gt;r.height = 1200;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state,</div><div class='add'>+				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	if (code-&gt;index &gt;= ARRAY_SIZE(supported_formats))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = supported_formats[code-&gt;index].code;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_enum_frame_size(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state,</div><div class='add'>+				  struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	const struct gc2145_format *gc2145_format;</div><div class='add'>+	u32 code;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index &gt;= ARRAY_SIZE(supported_modes))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	gc2145_format = gc2145_get_format_code(gc2145, fse-&gt;code);</div><div class='add'>+	code = gc2145_format-&gt;code;</div><div class='add'>+	if (fse-&gt;code != code)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fse-&gt;min_width = supported_modes[fse-&gt;index].width;</div><div class='add'>+	fse-&gt;max_width = fse-&gt;min_width;</div><div class='add'>+	fse-&gt;min_height = supported_modes[fse-&gt;index].height;</div><div class='add'>+	fse-&gt;max_height = fse-&gt;min_height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_set_pad_format(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state,</div><div class='add'>+				 struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	const struct gc2145_mode *mode;</div><div class='add'>+	const struct gc2145_format *gc2145_fmt;</div><div class='add'>+	struct v4l2_mbus_framefmt *framefmt;</div><div class='add'>+	struct gc2145_ctrls *ctrls = &amp;gc2145-&gt;ctrls;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+</div><div class='add'>+	gc2145_fmt = gc2145_get_format_code(gc2145, fmt-&gt;format.code);</div><div class='add'>+	mode = v4l2_find_nearest_size(supported_modes,</div><div class='add'>+				      ARRAY_SIZE(supported_modes),</div><div class='add'>+				      width, height,</div><div class='add'>+				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='add'>+</div><div class='add'>+	gc2145_update_pad_format(gc2145, mode, &amp;fmt-&gt;format, gc2145_fmt-&gt;code);</div><div class='add'>+	framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='add'>+	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE) {</div><div class='add'>+		gc2145-&gt;mode = mode;</div><div class='add'>+		/* Update pixel_rate based on the mode */</div><div class='add'>+		__v4l2_ctrl_s_ctrl_int64(ctrls-&gt;pixel_rate, mode-&gt;pixel_rate);</div><div class='add'>+		/* Update link_freq based on the mode */</div><div class='add'>+		__v4l2_ctrl_s_ctrl(ctrls-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='add'>+		/* Update hblank/vblank based on the mode */</div><div class='add'>+		__v4l2_ctrl_s_ctrl(ctrls-&gt;hblank, mode-&gt;hblank);</div><div class='add'>+		__v4l2_ctrl_s_ctrl(ctrls-&gt;vblank, mode-&gt;vblank);</div><div class='add'>+	}</div><div class='add'>+	*framefmt = fmt-&gt;format;</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, fmt-&gt;pad);</div><div class='add'>+	*crop = mode-&gt;crop;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence gc2145_common_mipi_regs[] = {</div><div class='add'>+	{GC2145_REG_PAGE_SELECT, 0x03},</div><div class='add'>+	{GC2145_REG_DPHY_ANALOG_MODE1, GC2145_DPHY_MODE_PHY_CLK_EN |</div><div class='add'>+				       GC2145_DPHY_MODE_PHY_LANE0_EN |</div><div class='add'>+				       GC2145_DPHY_MODE_PHY_LANE1_EN |</div><div class='add'>+				       GC2145_DPHY_MODE_PHY_CLK_LANE_P2S_SEL},</div><div class='add'>+	{GC2145_REG_DPHY_ANALOG_MODE2, GC2145_DPHY_CLK_DIFF(2) |</div><div class='add'>+				       GC2145_DPHY_LANE0_DIFF(2)},</div><div class='add'>+	{GC2145_REG_DPHY_ANALOG_MODE3, GC2145_DPHY_LANE1_DIFF(0) |</div><div class='add'>+				       GC2145_DPHY_CLK_DELAY},</div><div class='add'>+	{GC2145_REG_FIFO_MODE, GC2145_FIFO_MODE_READ_GATE |</div><div class='add'>+			       GC2145_FIFO_MODE_MIPI_CLK_MODULE},</div><div class='add'>+	{GC2145_REG_DPHY_MODE, GC2145_DPHY_MODE_TRIGGER_PROG},</div><div class='add'>+	/* Clock &amp; Data lanes timing */</div><div class='add'>+	{GC2145_REG_T_LPX, 0x10},</div><div class='add'>+	{GC2145_REG_T_CLK_HS_PREPARE, 0x04}, {GC2145_REG_T_CLK_ZERO, 0x10},</div><div class='add'>+	{GC2145_REG_T_CLK_PRE, 0x10}, {GC2145_REG_T_CLK_POST, 0x10},</div><div class='add'>+	{GC2145_REG_T_CLK_TRAIL, 0x05},</div><div class='add'>+	{GC2145_REG_T_HS_PREPARE, 0x03}, {GC2145_REG_T_HS_ZERO, 0x0a},</div><div class='add'>+	{GC2145_REG_T_HS_TRAIL, 0x06},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc2145_config_mipi_mode(struct gc2145 *gc2145,</div><div class='add'>+				   const struct gc2145_format *gc2145_format)</div><div class='add'>+{</div><div class='add'>+	u16 lwc, fifo_full_lvl;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Common MIPI settings */</div><div class='add'>+	cci_multi_reg_write(gc2145-&gt;regmap, gc2145_common_mipi_regs,</div><div class='add'>+			    ARRAY_SIZE(gc2145_common_mipi_regs), &amp;ret);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Adjust the MIPI buffer settings.</div><div class='add'>+	 * For YUV/RGB, LWC = image width * 2</div><div class='add'>+	 * For RAW8, LWC = image width</div><div class='add'>+	 * For RAW10, LWC = image width * 1.25</div><div class='add'>+	 */</div><div class='add'>+	lwc = gc2145-&gt;mode-&gt;width * 2;</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_LWC_HIGH, lwc &gt;&gt; 8, &amp;ret);</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_LWC_LOW, lwc &amp; 0xff, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Adjust the MIPI FIFO Full Level</div><div class='add'>+	 * 640x480 RGB: 0x0190</div><div class='add'>+	 * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0001</div><div class='add'>+	 * 1600x1200 RAW: 0x0190</div><div class='add'>+	 */</div><div class='add'>+	if (gc2145-&gt;mode-&gt;width == 1280 || gc2145-&gt;mode-&gt;width == 1600)</div><div class='add'>+		fifo_full_lvl = 0x0001;</div><div class='add'>+	else</div><div class='add'>+		fifo_full_lvl = 0x0190;</div><div class='add'>+</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_FIFO_FULL_LVL_HIGH,</div><div class='add'>+		  fifo_full_lvl &gt;&gt; 8, &amp;ret);</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_FIFO_FULL_LVL_LOW,</div><div class='add'>+		  fifo_full_lvl &amp; 0xff, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set the FIFO gate mode / MIPI wdiv set:</div><div class='add'>+	 * 0xf1 in case of RAW mode and 0xf0 otherwise</div><div class='add'>+	 */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_FIFO_GATE_MODE, 0xf0, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Set the MIPI data type */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_MIPI_DT,</div><div class='add'>+		  gc2145_format-&gt;datatype, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Configure mode and enable CSI */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_BUF_CSI2_MODE,</div><div class='add'>+		  GC2145_CSI2_MODE_RAW8 | GC2145_CSI2_MODE_DOUBLE |</div><div class='add'>+		  GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_start_streaming(struct gc2145 *gc2145,</div><div class='add'>+				  struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;gc2145-&gt;sd);</div><div class='add'>+	const struct gc2145_format *gc2145_format;</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;client-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Apply default values of current mode */</div><div class='add'>+	cci_multi_reg_write(gc2145-&gt;regmap, gc2145-&gt;mode-&gt;reg_seq,</div><div class='add'>+			    gc2145-&gt;mode-&gt;reg_seq_size, &amp;ret);</div><div class='add'>+	cci_multi_reg_write(gc2145-&gt;regmap, gc2145_common_regs,</div><div class='add'>+			    ARRAY_SIZE(gc2145_common_regs), &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "%s failed to write regs\n", __func__);</div><div class='add'>+		goto err_rpm_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	gc2145_format = gc2145_get_format_code(gc2145, fmt-&gt;code);</div><div class='add'>+</div><div class='add'>+	/* Set the output format */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_PAGE_SELECT, 0x00, &amp;ret);</div><div class='add'>+</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_OUTPUT_FMT,</div><div class='add'>+		  gc2145_format-&gt;output_fmt, &amp;ret);</div><div class='add'>+	cci_update_bits(gc2145-&gt;regmap, GC2145_REG_BYPASS_MODE,</div><div class='add'>+			GC2145_BYPASS_MODE_SWITCH,</div><div class='add'>+			gc2145_format-&gt;switch_bit ? GC2145_BYPASS_MODE_SWITCH</div><div class='add'>+						  : 0, &amp;ret);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "%s failed to write regs\n", __func__);</div><div class='add'>+		goto err_rpm_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Apply customized values from user */</div><div class='add'>+	ret =  __v4l2_ctrl_handler_setup(&amp;gc2145-&gt;ctrls.handler);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "%s failed to apply ctrls\n", __func__);</div><div class='add'>+		goto err_rpm_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Perform MIPI specific configuration */</div><div class='add'>+	ret = gc2145_config_mipi_mode(gc2145, gc2145_format);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "%s failed to write mipi conf\n",</div><div class='add'>+			__func__);</div><div class='add'>+		goto err_rpm_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_PAGE_SELECT, 0x00, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_rpm_put:</div><div class='add'>+	pm_runtime_mark_last_busy(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gc2145_stop_streaming(struct gc2145 *gc2145)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;gc2145-&gt;sd);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Disable lanes &amp; mipi streaming */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_PAGE_SELECT, 0x03, &amp;ret);</div><div class='add'>+	cci_update_bits(gc2145-&gt;regmap, GC2145_REG_BUF_CSI2_MODE,</div><div class='add'>+			GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, 0,</div><div class='add'>+			&amp;ret);</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_PAGE_SELECT, 0x00, &amp;ret);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "%s failed to write regs\n", __func__);</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		ret = gc2145_start_streaming(gc2145, state);</div><div class='add'>+	else</div><div class='add'>+		gc2145_stop_streaming(gc2145);</div><div class='add'>+</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Power/clock management functions */</div><div class='add'>+static int gc2145_power_on(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES, gc2145-&gt;supplies);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to enable regulators\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(gc2145-&gt;xclk);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to enable clock\n");</div><div class='add'>+		goto reg_off;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(gc2145-&gt;powerdown_gpio, 0);</div><div class='add'>+	gpiod_set_value_cansleep(gc2145-&gt;reset_gpio, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Datasheet doesn't mention timing between PWDN/RESETB control and</div><div class='add'>+	 * i2c access however, experimentation shows that a rather big delay is</div><div class='add'>+	 * needed.</div><div class='add'>+	 */</div><div class='add'>+	msleep(41);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+reg_off:</div><div class='add'>+	regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145-&gt;supplies);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_power_off(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(gc2145-&gt;powerdown_gpio, 1);</div><div class='add'>+	gpiod_set_value_cansleep(gc2145-&gt;reset_gpio, 1);</div><div class='add'>+	clk_disable_unprepare(gc2145-&gt;xclk);</div><div class='add'>+	regulator_bulk_disable(GC2145_NUM_SUPPLIES, gc2145-&gt;supplies);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_get_regulators(struct gc2145 *gc2145)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;gc2145-&gt;sd);</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; GC2145_NUM_SUPPLIES; i++)</div><div class='add'>+		gc2145-&gt;supplies[i].supply = gc2145_supply_name[i];</div><div class='add'>+</div><div class='add'>+	return devm_regulator_bulk_get(&amp;client-&gt;dev, GC2145_NUM_SUPPLIES,</div><div class='add'>+				       gc2145-&gt;supplies);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Verify chip ID */</div><div class='add'>+static int gc2145_identify_module(struct gc2145 *gc2145)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;gc2145-&gt;sd);</div><div class='add'>+	int ret;</div><div class='add'>+	u64 chip_id;</div><div class='add'>+</div><div class='add'>+	ret = cci_read(gc2145-&gt;regmap, GC2145_REG_CHIP_ID, &amp;chip_id, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to read chip id (%d)\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (chip_id != GC2145_CHIP_ID) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "chip id mismatch: %x!=%llx\n",</div><div class='add'>+			GC2145_CHIP_ID, chip_id);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const char * const test_pattern_menu[] = {</div><div class='add'>+	"Disabled",</div><div class='add'>+	"Colored patterns",</div><div class='add'>+	"Uniform white",</div><div class='add'>+	"Uniform yellow",</div><div class='add'>+	"Uniform cyan",</div><div class='add'>+	"Uniform green",</div><div class='add'>+	"Uniform magenta",</div><div class='add'>+	"Uniform red",</div><div class='add'>+	"Uniform black",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define GC2145_TEST_PATTERN_ENABLE	BIT(0)</div><div class='add'>+#define GC2145_TEST_PATTERN_UXGA	BIT(3)</div><div class='add'>+</div><div class='add'>+#define GC2145_TEST_UNIFORM		BIT(3)</div><div class='add'>+#define GC2145_TEST_WHITE		(4 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_YELLOW		(8 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_CYAN		(9 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_GREEN		(6 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_MAGENTA		(10 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_RED			(5 &lt;&lt; 4)</div><div class='add'>+#define GC2145_TEST_BLACK		(0)</div><div class='add'>+</div><div class='add'>+static const u8 test_pattern_val[] = {</div><div class='add'>+	0,</div><div class='add'>+	GC2145_TEST_PATTERN_ENABLE,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_WHITE,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_YELLOW,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_CYAN,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_GREEN,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_MAGENTA,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_RED,</div><div class='add'>+	GC2145_TEST_UNIFORM | GC2145_TEST_BLACK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops gc2145_core_ops = {</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops gc2145_video_ops = {</div><div class='add'>+	.s_stream = gc2145_set_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops gc2145_pad_ops = {</div><div class='add'>+	.enum_mbus_code = gc2145_enum_mbus_code,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt = gc2145_set_pad_format,</div><div class='add'>+	.get_selection = gc2145_get_selection,</div><div class='add'>+	.enum_frame_size = gc2145_enum_frame_size,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops gc2145_subdev_ops = {</div><div class='add'>+	.core = &amp;gc2145_core_ops,</div><div class='add'>+	.video = &amp;gc2145_video_ops,</div><div class='add'>+	.pad = &amp;gc2145_pad_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops gc2145_subdev_internal_ops = {</div><div class='add'>+	.init_state = gc2145_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int gc2145_set_ctrl_test_pattern(struct gc2145 *gc2145, int value)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (!value) {</div><div class='add'>+		/* Disable test pattern */</div><div class='add'>+		cci_write(gc2145-&gt;regmap, GC2145_REG_DEBUG_MODE2, 0, &amp;ret);</div><div class='add'>+		return cci_write(gc2145-&gt;regmap, GC2145_REG_DEBUG_MODE3, 0,</div><div class='add'>+				 &amp;ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Enable test pattern, colored or uniform */</div><div class='add'>+	cci_write(gc2145-&gt;regmap, GC2145_REG_DEBUG_MODE2,</div><div class='add'>+		  GC2145_TEST_PATTERN_ENABLE | GC2145_TEST_PATTERN_UXGA, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (!(test_pattern_val[value] &amp; GC2145_TEST_UNIFORM))</div><div class='add'>+		return cci_write(gc2145-&gt;regmap, GC2145_REG_DEBUG_MODE3, 0,</div><div class='add'>+				 &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Uniform */</div><div class='add'>+	return cci_write(gc2145-&gt;regmap, GC2145_REG_DEBUG_MODE3,</div><div class='add'>+			 test_pattern_val[value], &amp;ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = gc2145_ctrl_to_sd(ctrl);</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (pm_runtime_get_if_in_use(&amp;client-&gt;dev) == 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_HBLANK:</div><div class='add'>+		ret = cci_write(gc2145-&gt;regmap, GC2145_REG_HBLANK, ctrl-&gt;val,</div><div class='add'>+				NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_VBLANK:</div><div class='add'>+		ret = cci_write(gc2145-&gt;regmap, GC2145_REG_VBLANK, ctrl-&gt;val,</div><div class='add'>+				NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_TEST_PATTERN:</div><div class='add'>+		ret = gc2145_set_ctrl_test_pattern(gc2145, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+		ret = cci_update_bits(gc2145-&gt;regmap, GC2145_REG_ANALOG_MODE1,</div><div class='add'>+				      BIT(0), (ctrl-&gt;val ? BIT(0) : 0), NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+		ret = cci_update_bits(gc2145-&gt;regmap, GC2145_REG_ANALOG_MODE1,</div><div class='add'>+				      BIT(1), (ctrl-&gt;val ? BIT(1) : 0), NULL);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops gc2145_ctrl_ops = {</div><div class='add'>+	.s_ctrl = gc2145_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Initialize control handlers */</div><div class='add'>+static int gc2145_init_controls(struct gc2145 *gc2145)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;gc2145-&gt;sd);</div><div class='add'>+	const struct v4l2_ctrl_ops *ops = &amp;gc2145_ctrl_ops;</div><div class='add'>+	struct gc2145_ctrls *ctrls = &amp;gc2145-&gt;ctrls;</div><div class='add'>+	struct v4l2_ctrl_handler *hdl = &amp;ctrls-&gt;handler;</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_handler_init(hdl, 12);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,</div><div class='add'>+					      GC2145_640_480_PIXELRATE,</div><div class='add'>+					      GC2145_1600_1200_PIXELRATE, 1,</div><div class='add'>+					      supported_modes[0].pixel_rate);</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ,</div><div class='add'>+						  ARRAY_SIZE(gc2145_link_freq_menu) - 1,</div><div class='add'>+						  0, gc2145_link_freq_menu);</div><div class='add'>+	if (ctrls-&gt;link_freq)</div><div class='add'>+		ctrls-&gt;link_freq-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,</div><div class='add'>+					  0, 0xfff, 1, GC2145_640_480_HBLANK);</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,</div><div class='add'>+					  0, 0x1fff, 1, GC2145_640_480_VBLANK);</div><div class='add'>+</div><div class='add'>+	ctrls-&gt;test_pattern =</div><div class='add'>+		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,</div><div class='add'>+					     ARRAY_SIZE(test_pattern_menu) - 1,</div><div class='add'>+					     0, 0, test_pattern_menu);</div><div class='add'>+	ctrls-&gt;hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP,</div><div class='add'>+					 0, 1, 1, 0);</div><div class='add'>+	ctrls-&gt;vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP,</div><div class='add'>+					 0, 1, 1, 0);</div><div class='add'>+</div><div class='add'>+	if (hdl-&gt;error) {</div><div class='add'>+		ret = hdl-&gt;error;</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "control init failed (%d)\n", ret);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_device_parse(&amp;client-&gt;dev, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_new_fwnode_properties(hdl, &amp;gc2145_ctrl_ops,</div><div class='add'>+					      &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error;</div><div class='add'>+</div><div class='add'>+	gc2145-&gt;sd.ctrl_handler = hdl;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	v4l2_ctrl_handler_free(hdl);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_check_hwcfg(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct fwnode_handle *endpoint;</div><div class='add'>+	struct v4l2_fwnode_endpoint ep_cfg = {</div><div class='add'>+		.bus_type = V4L2_MBUS_CSI2_DPHY</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);</div><div class='add'>+	if (!endpoint) {</div><div class='add'>+		dev_err(dev, "endpoint node not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &amp;ep_cfg);</div><div class='add'>+	fwnode_handle_put(endpoint);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Check the number of MIPI CSI2 data lanes */</div><div class='add'>+	if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) {</div><div class='add'>+		dev_err(dev, "only 2 data lanes are currently supported\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check the link frequency set in device tree */</div><div class='add'>+	if (!ep_cfg.nr_of_link_frequencies) {</div><div class='add'>+		dev_err(dev, "link-frequency property not found in DT\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ep_cfg.nr_of_link_frequencies != 3 ||</div><div class='add'>+	    ep_cfg.link_frequencies[0] != GC2145_640_480_LINKFREQ ||</div><div class='add'>+	    ep_cfg.link_frequencies[1] != GC2145_1280_720_LINKFREQ ||</div><div class='add'>+	    ep_cfg.link_frequencies[2] != GC2145_1600_1200_LINKFREQ) {</div><div class='add'>+		dev_err(dev, "Invalid link-frequencies provided\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	v4l2_fwnode_endpoint_free(&amp;ep_cfg);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int gc2145_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	unsigned int xclk_freq;</div><div class='add'>+	struct gc2145 *gc2145;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	gc2145 = devm_kzalloc(&amp;client-&gt;dev, sizeof(*gc2145), GFP_KERNEL);</div><div class='add'>+	if (!gc2145)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	v4l2_i2c_subdev_init(&amp;gc2145-&gt;sd, client, &amp;gc2145_subdev_ops);</div><div class='add'>+	gc2145-&gt;sd.internal_ops = &amp;gc2145_subdev_internal_ops;</div><div class='add'>+</div><div class='add'>+	/* Check the hardware configuration in device tree */</div><div class='add'>+	if (gc2145_check_hwcfg(dev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Get system clock (xclk) */</div><div class='add'>+	gc2145-&gt;xclk = devm_clk_get(dev, NULL);</div><div class='add'>+	if (IS_ERR(gc2145-&gt;xclk))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc2145-&gt;xclk),</div><div class='add'>+				     "failed to get xclk\n");</div><div class='add'>+</div><div class='add'>+	xclk_freq = clk_get_rate(gc2145-&gt;xclk);</div><div class='add'>+	if (xclk_freq != GC2145_XCLK_FREQ) {</div><div class='add'>+		dev_err(dev, "xclk frequency not supported: %d Hz\n",</div><div class='add'>+			xclk_freq);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = gc2145_get_regulators(gc2145);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+				     "failed to get regulators\n");</div><div class='add'>+</div><div class='add'>+	/* Request optional reset pin */</div><div class='add'>+	gc2145-&gt;reset_gpio = devm_gpiod_get_optional(dev, "reset",</div><div class='add'>+						     GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(gc2145-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc2145-&gt;reset_gpio),</div><div class='add'>+				     "failed to get reset_gpio\n");</div><div class='add'>+</div><div class='add'>+	/* Request optional powerdown pin */</div><div class='add'>+	gc2145-&gt;powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown",</div><div class='add'>+							 GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(gc2145-&gt;powerdown_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc2145-&gt;powerdown_gpio),</div><div class='add'>+				     "failed to get powerdown_gpio\n");</div><div class='add'>+</div><div class='add'>+	/* Initialise the regmap for further cci access */</div><div class='add'>+	gc2145-&gt;regmap = devm_cci_regmap_init_i2c(client, 8);</div><div class='add'>+	if (IS_ERR(gc2145-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(gc2145-&gt;regmap),</div><div class='add'>+				     "failed to get cci regmap\n");</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The sensor must be powered for gc2145_identify_module()</div><div class='add'>+	 * to be able to read the CHIP_ID register</div><div class='add'>+	 */</div><div class='add'>+	ret = gc2145_power_on(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = gc2145_identify_module(gc2145);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	/* Set default mode */</div><div class='add'>+	gc2145-&gt;mode = &amp;supported_modes[0];</div><div class='add'>+</div><div class='add'>+	ret = gc2145_init_controls(gc2145);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	/* Initialize subdev */</div><div class='add'>+	gc2145-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='add'>+			    V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+	gc2145-&gt;sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='add'>+</div><div class='add'>+	/* Initialize source pad */</div><div class='add'>+	gc2145-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+</div><div class='add'>+	ret = media_entity_pads_init(&amp;gc2145-&gt;sd.entity, 1, &amp;gc2145-&gt;pad);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "failed to init entity pads: %d\n", ret);</div><div class='add'>+		goto error_handler_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gc2145-&gt;sd.state_lock = gc2145-&gt;ctrls.handler.lock;</div><div class='add'>+	ret = v4l2_subdev_init_finalize(&amp;gc2145-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "subdev init error: %d\n", ret);</div><div class='add'>+		goto error_media_entity;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Enable runtime PM and turn off the device */</div><div class='add'>+	pm_runtime_set_active(dev);</div><div class='add'>+	pm_runtime_get_noresume(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+</div><div class='add'>+	pm_runtime_set_autosuspend_delay(&amp;client-&gt;dev, 1000);</div><div class='add'>+	pm_runtime_use_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;gc2145-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "failed to register sensor sub-device: %d\n", ret);</div><div class='add'>+		goto error_subdev_cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_subdev_cleanup:</div><div class='add'>+	v4l2_subdev_cleanup(&amp;gc2145-&gt;sd);</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+error_media_entity:</div><div class='add'>+	media_entity_cleanup(&amp;gc2145-&gt;sd.entity);</div><div class='add'>+</div><div class='add'>+error_handler_free:</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;gc2145-&gt;ctrls.handler);</div><div class='add'>+</div><div class='add'>+error_power_off:</div><div class='add'>+	gc2145_power_off(dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void gc2145_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct gc2145 *gc2145 = to_gc2145(sd);</div><div class='add'>+</div><div class='add'>+	v4l2_subdev_cleanup(sd);</div><div class='add'>+	v4l2_async_unregister_subdev(sd);</div><div class='add'>+	media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;gc2145-&gt;ctrls.handler);</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	if (!pm_runtime_status_suspended(&amp;client-&gt;dev))</div><div class='add'>+		gc2145_power_off(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id gc2145_dt_ids[] = {</div><div class='add'>+	{ .compatible = "galaxycore,gc2145" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, gc2145_dt_ids);</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops gc2145_pm_ops = {</div><div class='add'>+	RUNTIME_PM_OPS(gc2145_power_off, gc2145_power_on, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct i2c_driver gc2145_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "gc2145",</div><div class='add'>+		.of_match_table	= gc2145_dt_ids,</div><div class='add'>+		.pm = pm_ptr(&amp;gc2145_pm_ops),</div><div class='add'>+	},</div><div class='add'>+	.probe = gc2145_probe,</div><div class='add'>+	.remove = gc2145_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(gc2145_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Alain Volmat &lt;alain.volmat@foss.st.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("GalaxyCore GC2145 sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/hi556.c b/drivers/media/i2c/hi556.c<br/>index f6ea9b7b9700..38c77d515786 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi556.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/hi556.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi556.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi556.c</a></div><div class='hunk'>@@ -935,7 +935,7 @@ __hi556_get_pad_crop(struct hi556 *hi556,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;hi556-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;hi556-&gt;cur_mode-&gt;crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1075,7 +1075,7 @@ static int hi556_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;hi556-&gt;mutex);</div><div class='ctx'> 	hi556_assign_pad_format(mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		hi556-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(hi556-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -1109,9 +1109,8 @@ static int hi556_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hi556-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;hi556-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		hi556_assign_pad_format(hi556-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -1157,10 +1156,10 @@ static int hi556_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hi556-&gt;mutex);</div><div class='ctx'> 	hi556_assign_pad_format(&amp;supported_modes[0],</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize try_crop rectangle. */</div><div class='del'>-	try_crop = v4l2_subdev_get_try_crop(sd, fh-&gt;state, 0);</div><div class='add'>+	try_crop = v4l2_subdev_state_get_crop(fh-&gt;state, 0);</div><div class='ctx'> 	try_crop-&gt;top = HI556_PIXEL_ARRAY_TOP;</div><div class='ctx'> 	try_crop-&gt;left = HI556_PIXEL_ARRAY_LEFT;</div><div class='ctx'> 	try_crop-&gt;width = HI556_PIXEL_ARRAY_WIDTH;</div><div class='head'>diff --git a/drivers/media/i2c/hi846.c b/drivers/media/i2c/hi846.c<br/>index 825fc8dc48f5..9c565ec033d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi846.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/hi846.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi846.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi846.c</a></div><div class='hunk'>@@ -1705,7 +1705,7 @@ static int hi846_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad) = *mf;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, format-&gt;pad) = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1783,9 +1783,8 @@ static int hi846_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(&amp;hi846-&gt;sd,</div><div class='del'>-							sd_state,</div><div class='del'>-							format-&gt;pad);</div><div class='add'>+		format-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							       format-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1852,7 +1851,7 @@ static int hi846_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		mutex_lock(&amp;hi846-&gt;mutex);</div><div class='ctx'> 		switch (sel-&gt;which) {</div><div class='ctx'> 		case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-			v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+			v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 			sel-&gt;r = hi846-&gt;cur_mode-&gt;crop;</div><div class='hunk'>@@ -1872,13 +1871,13 @@ static int hi846_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hi846_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int hi846_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			    struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct hi846 *hi846 = to_hi846(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hi846-&gt;mutex);</div><div class='ctx'> 	mf-&gt;code        = HI846_MEDIA_BUS_FORMAT;</div><div class='hunk'>@@ -1896,7 +1895,6 @@ static const struct v4l2_subdev_video_ops hi846_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops hi846_pad_ops = {</div><div class='del'>-	.init_cfg = hi846_init_cfg,</div><div class='ctx'> 	.enum_frame_size = hi846_enum_frame_size,</div><div class='ctx'> 	.enum_mbus_code = hi846_enum_mbus_code,</div><div class='ctx'> 	.set_fmt = hi846_set_format,</div><div class='hunk'>@@ -1909,6 +1907,10 @@ static const struct v4l2_subdev_ops hi846_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;hi846_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops hi846_internal_ops = {</div><div class='add'>+	.init_state = hi846_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations hi846_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -2072,6 +2074,7 @@ static int hi846_probe(struct i2c_client *client)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;hi846-&gt;sd, client, &amp;hi846_subdev_ops);</div><div class='add'>+	hi846-&gt;sd.internal_ops = &amp;hi846_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;hi846-&gt;mutex);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/hi847.c b/drivers/media/i2c/hi847.c<br/>index 4075c389804c..72c60747a839 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi847.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/hi847.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/hi847.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/hi847.c</a></div><div class='hunk'>@@ -2655,7 +2655,7 @@ static int hi847_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;hi847-&gt;mutex);</div><div class='ctx'> 	hi847_assign_pad_format(mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) =</div><div class='ctx'> 			fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		hi847-&gt;cur_mode = mode;</div><div class='hunk'>@@ -2690,9 +2690,8 @@ static int hi847_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hi847-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;hi847-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		hi847_assign_pad_format(hi847-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -2737,7 +2736,7 @@ static int hi847_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hi847-&gt;mutex);</div><div class='ctx'> 	hi847_assign_pad_format(&amp;supported_modes[0],</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;hi847-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/imx208.c b/drivers/media/i2c/imx208.c<br/>index a9b0aea1ae3b..639e05340dbb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx208.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx208.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx208.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx208.c</a></div><div class='hunk'>@@ -395,7 +395,7 @@ static int imx208_write_regs(struct imx208 *imx208,</div><div class='ctx'> static int imx208_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize try_fmt */</div><div class='ctx'> 	try_fmt-&gt;width = supported_modes[0].width;</div><div class='hunk'>@@ -548,9 +548,8 @@ static int __imx208_get_pad_format(struct imx208 *imx208,</div><div class='ctx'> 				   struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;imx208-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		imx208_mode_to_pad_format(imx208, imx208-&gt;cur_mode, fmt);</div><div class='ctx'> </div><div class='hunk'>@@ -591,7 +590,7 @@ static int imx208_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	imx208_mode_to_pad_format(imx208, mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx208-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(imx208-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='head'>diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c<br/>index 4f77ea02cc27..b148b1bd2bc3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx214.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx214.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx214.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx214.c</a></div><div class='hunk'>@@ -19,12 +19,31 @@</div><div class='ctx'> #include &lt;media/v4l2-fwnode.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-subdev.h&gt;</div><div class='ctx'> </div><div class='add'>+#define IMX214_REG_MODE_SELECT		0x0100</div><div class='add'>+#define IMX214_MODE_STANDBY		0x00</div><div class='add'>+#define IMX214_MODE_STREAMING		0x01</div><div class='add'>+</div><div class='ctx'> #define IMX214_DEFAULT_CLK_FREQ	24000000</div><div class='ctx'> #define IMX214_DEFAULT_LINK_FREQ 480000000</div><div class='ctx'> #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)</div><div class='ctx'> #define IMX214_FPS 30</div><div class='ctx'> #define IMX214_MBUS_CODE MEDIA_BUS_FMT_SRGGB10_1X10</div><div class='ctx'> </div><div class='add'>+/* Exposure control */</div><div class='add'>+#define IMX214_REG_EXPOSURE		0x0202</div><div class='add'>+#define IMX214_EXPOSURE_MIN		0</div><div class='add'>+#define IMX214_EXPOSURE_MAX		3184</div><div class='add'>+#define IMX214_EXPOSURE_STEP		1</div><div class='add'>+#define IMX214_EXPOSURE_DEFAULT		3184</div><div class='add'>+</div><div class='add'>+/* IMX214 native and active pixel array size */</div><div class='add'>+#define IMX214_NATIVE_WIDTH		4224U</div><div class='add'>+#define IMX214_NATIVE_HEIGHT		3136U</div><div class='add'>+#define IMX214_PIXEL_ARRAY_LEFT		8U</div><div class='add'>+#define IMX214_PIXEL_ARRAY_TOP		8U</div><div class='add'>+#define IMX214_PIXEL_ARRAY_WIDTH	4208U</div><div class='add'>+#define IMX214_PIXEL_ARRAY_HEIGHT	3120U</div><div class='add'>+</div><div class='ctx'> static const char * const imx214_supply_name[] = {</div><div class='ctx'> 	"vdda",</div><div class='ctx'> 	"vddd",</div><div class='hunk'>@@ -538,7 +557,7 @@ __imx214_get_pad_format(struct imx214 *imx214,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;imx214-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;imx214-&gt;fmt;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -568,7 +587,7 @@ __imx214_get_pad_crop(struct imx214 *imx214,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;imx214-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;imx214-&gt;crop;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -623,18 +642,35 @@ static int imx214_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	struct imx214 *imx214 = to_imx214(sd);</div><div class='ctx'> </div><div class='del'>-	if (sel-&gt;target != V4L2_SEL_TGT_CROP)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	switch (sel-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		mutex_lock(&amp;imx214-&gt;mutex);</div><div class='add'>+		sel-&gt;r = *__imx214_get_pad_crop(imx214, sd_state, sel-&gt;pad,</div><div class='add'>+						sel-&gt;which);</div><div class='add'>+		mutex_unlock(&amp;imx214-&gt;mutex);</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;imx214-&gt;mutex);</div><div class='del'>-	sel-&gt;r = *__imx214_get_pad_crop(imx214, sd_state, sel-&gt;pad,</div><div class='del'>-					sel-&gt;which);</div><div class='del'>-	mutex_unlock(&amp;imx214-&gt;mutex);</div><div class='del'>-	return 0;</div><div class='add'>+	case V4L2_SEL_TGT_NATIVE_SIZE:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = IMX214_NATIVE_WIDTH;</div><div class='add'>+		sel-&gt;r.height = IMX214_NATIVE_HEIGHT;</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+		sel-&gt;r.top = IMX214_PIXEL_ARRAY_TOP;</div><div class='add'>+		sel-&gt;r.left = IMX214_PIXEL_ARRAY_LEFT;</div><div class='add'>+		sel-&gt;r.width = IMX214_PIXEL_ARRAY_WIDTH;</div><div class='add'>+		sel-&gt;r.height = IMX214_PIXEL_ARRAY_HEIGHT;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx214_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx214_entity_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				    struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { };</div><div class='ctx'> </div><div class='hunk'>@@ -665,7 +701,7 @@ static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 	case V4L2_CID_EXPOSURE:</div><div class='ctx'> 		vals[1] = ctrl-&gt;val;</div><div class='ctx'> 		vals[0] = ctrl-&gt;val &gt;&gt; 8;</div><div class='del'>-		ret = regmap_bulk_write(imx214-&gt;regmap, 0x202, vals, 2);</div><div class='add'>+		ret = regmap_bulk_write(imx214-&gt;regmap, IMX214_REG_EXPOSURE, vals, 2);</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='ctx'> 			dev_err(imx214-&gt;dev, "Error %d\n", ret);</div><div class='ctx'> 		ret = 0;</div><div class='hunk'>@@ -684,6 +720,76 @@ static const struct v4l2_ctrl_ops imx214_ctrl_ops = {</div><div class='ctx'> 	.s_ctrl = imx214_set_ctrl,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int imx214_ctrls_init(struct imx214 *imx214)</div><div class='add'>+{</div><div class='add'>+	static const s64 link_freq[] = {</div><div class='add'>+		IMX214_DEFAULT_LINK_FREQ</div><div class='add'>+	};</div><div class='add'>+	static const struct v4l2_area unit_size = {</div><div class='add'>+		.width = 1120,</div><div class='add'>+		.height = 1120,</div><div class='add'>+	};</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='add'>+	struct v4l2_ctrl_handler *ctrl_hdlr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_device_parse(imx214-&gt;dev, &amp;props);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ctrl_hdlr = &amp;imx214-&gt;ctrls;</div><div class='add'>+	ret = v4l2_ctrl_handler_init(&amp;imx214-&gt;ctrls, 6);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	imx214-&gt;pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL,</div><div class='add'>+					       V4L2_CID_PIXEL_RATE, 0,</div><div class='add'>+					       IMX214_DEFAULT_PIXEL_RATE, 1,</div><div class='add'>+					       IMX214_DEFAULT_PIXEL_RATE);</div><div class='add'>+</div><div class='add'>+	imx214-&gt;link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL,</div><div class='add'>+						   V4L2_CID_LINK_FREQ,</div><div class='add'>+						   ARRAY_SIZE(link_freq) - 1,</div><div class='add'>+						   0, link_freq);</div><div class='add'>+	if (imx214-&gt;link_freq)</div><div class='add'>+		imx214-&gt;link_freq-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * WARNING!</div><div class='add'>+	 * Values obtained reverse engineering blobs and/or devices.</div><div class='add'>+	 * Ranges and functionality might be wrong.</div><div class='add'>+	 *</div><div class='add'>+	 * Sony, please release some register set documentation for the</div><div class='add'>+	 * device.</div><div class='add'>+	 *</div><div class='add'>+	 * Yours sincerely, Ricardo.</div><div class='add'>+	 */</div><div class='add'>+	imx214-&gt;exposure = v4l2_ctrl_new_std(ctrl_hdlr, &amp;imx214_ctrl_ops,</div><div class='add'>+					     V4L2_CID_EXPOSURE,</div><div class='add'>+					     IMX214_EXPOSURE_MIN,</div><div class='add'>+					     IMX214_EXPOSURE_MAX,</div><div class='add'>+					     IMX214_EXPOSURE_STEP,</div><div class='add'>+					     IMX214_EXPOSURE_DEFAULT);</div><div class='add'>+</div><div class='add'>+	imx214-&gt;unit_size = v4l2_ctrl_new_std_compound(ctrl_hdlr,</div><div class='add'>+				NULL,</div><div class='add'>+				V4L2_CID_UNIT_CELL_SIZE,</div><div class='add'>+				v4l2_ctrl_ptr_create((void *)&amp;unit_size));</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &amp;imx214_ctrl_ops, &amp;props);</div><div class='add'>+</div><div class='add'>+	ret = ctrl_hdlr-&gt;error;</div><div class='add'>+	if (ret) {</div><div class='add'>+		v4l2_ctrl_handler_free(ctrl_hdlr);</div><div class='add'>+		dev_err(imx214-&gt;dev, "failed to add controls: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	imx214-&gt;sd.ctrl_handler = ctrl_hdlr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define MAX_CMD 4</div><div class='ctx'> static int imx214_write_table(struct imx214 *imx214,</div><div class='ctx'> 			      const struct reg_8 table[])</div><div class='hunk'>@@ -743,7 +849,7 @@ static int imx214_start_streaming(struct imx214 *imx214)</div><div class='ctx'> 		dev_err(imx214-&gt;dev, "could not sync v4l2 controls\n");</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	}</div><div class='del'>-	ret = regmap_write(imx214-&gt;regmap, 0x100, 1);</div><div class='add'>+	ret = regmap_write(imx214-&gt;regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_STREAMING);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(imx214-&gt;dev, "could not sent start table %d\n", ret);</div><div class='ctx'> 		goto error;</div><div class='hunk'>@@ -761,7 +867,7 @@ static int imx214_stop_streaming(struct imx214 *imx214)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = regmap_write(imx214-&gt;regmap, 0x100, 0);</div><div class='add'>+	ret = regmap_write(imx214-&gt;regmap, IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		dev_err(imx214-&gt;dev, "could not sent stop table %d\n",	ret);</div><div class='ctx'> </div><div class='hunk'>@@ -795,9 +901,17 @@ err_rpm_put:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx214_g_frame_interval(struct v4l2_subdev *subdev,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fival)</div><div class='add'>+static int imx214_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fival)</div><div class='ctx'> {</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	fival-&gt;interval.numerator = 1;</div><div class='ctx'> 	fival-&gt;interval.denominator = IMX214_FPS;</div><div class='ctx'> </div><div class='hunk'>@@ -828,8 +942,6 @@ static int imx214_enum_frame_interval(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops imx214_video_ops = {</div><div class='ctx'> 	.s_stream = imx214_s_stream,</div><div class='del'>-	.g_frame_interval = imx214_g_frame_interval,</div><div class='del'>-	.s_frame_interval = imx214_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = {</div><div class='hunk'>@@ -839,7 +951,8 @@ static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = {</div><div class='ctx'> 	.get_fmt = imx214_get_format,</div><div class='ctx'> 	.set_fmt = imx214_set_format,</div><div class='ctx'> 	.get_selection = imx214_get_selection,</div><div class='del'>-	.init_cfg = imx214_entity_init_cfg,</div><div class='add'>+	.get_frame_interval = imx214_get_frame_interval,</div><div class='add'>+	.set_frame_interval = imx214_get_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops imx214_subdev_ops = {</div><div class='hunk'>@@ -848,6 +961,10 @@ static const struct v4l2_subdev_ops imx214_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx214_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx214_internal_ops = {</div><div class='add'>+	.init_state = imx214_entity_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct regmap_config sensor_regmap_config = {</div><div class='ctx'> 	.reg_bits = 16,</div><div class='ctx'> 	.val_bits = 8,</div><div class='hunk'>@@ -907,13 +1024,6 @@ static int imx214_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='ctx'> 	struct imx214 *imx214;</div><div class='del'>-	static const s64 link_freq[] = {</div><div class='del'>-		IMX214_DEFAULT_LINK_FREQ,</div><div class='del'>-	};</div><div class='del'>-	static const struct v4l2_area unit_size = {</div><div class='del'>-		.width = 1120,</div><div class='del'>-		.height = 1120,</div><div class='del'>-	};</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx214_parse_fwnode(dev);</div><div class='hunk'>@@ -957,6 +1067,7 @@ static int imx214_probe(struct i2c_client *client)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx214-&gt;sd, client, &amp;imx214_subdev_ops);</div><div class='add'>+	imx214-&gt;sd.internal_ops = &amp;imx214_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Enable power initially, to avoid warnings</div><div class='hunk'>@@ -968,45 +1079,10 @@ static int imx214_probe(struct i2c_client *client)</div><div class='ctx'> 	pm_runtime_enable(imx214-&gt;dev);</div><div class='ctx'> 	pm_runtime_idle(imx214-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	v4l2_ctrl_handler_init(&amp;imx214-&gt;ctrls, 3);</div><div class='del'>-</div><div class='del'>-	imx214-&gt;pixel_rate = v4l2_ctrl_new_std(&amp;imx214-&gt;ctrls, NULL,</div><div class='del'>-					       V4L2_CID_PIXEL_RATE, 0,</div><div class='del'>-					       IMX214_DEFAULT_PIXEL_RATE, 1,</div><div class='del'>-					       IMX214_DEFAULT_PIXEL_RATE);</div><div class='del'>-	imx214-&gt;link_freq = v4l2_ctrl_new_int_menu(&amp;imx214-&gt;ctrls, NULL,</div><div class='del'>-						   V4L2_CID_LINK_FREQ,</div><div class='del'>-						   ARRAY_SIZE(link_freq) - 1,</div><div class='del'>-						   0, link_freq);</div><div class='del'>-	if (imx214-&gt;link_freq)</div><div class='del'>-		imx214-&gt;link_freq-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * WARNING!</div><div class='del'>-	 * Values obtained reverse engineering blobs and/or devices.</div><div class='del'>-	 * Ranges and functionality might be wrong.</div><div class='del'>-	 *</div><div class='del'>-	 * Sony, please release some register set documentation for the</div><div class='del'>-	 * device.</div><div class='del'>-	 *</div><div class='del'>-	 * Yours sincerely, Ricardo.</div><div class='del'>-	 */</div><div class='del'>-	imx214-&gt;exposure = v4l2_ctrl_new_std(&amp;imx214-&gt;ctrls, &amp;imx214_ctrl_ops,</div><div class='del'>-					     V4L2_CID_EXPOSURE,</div><div class='del'>-					     0, 3184, 1, 0x0c70);</div><div class='del'>-</div><div class='del'>-	imx214-&gt;unit_size = v4l2_ctrl_new_std_compound(&amp;imx214-&gt;ctrls,</div><div class='del'>-				NULL,</div><div class='del'>-				V4L2_CID_UNIT_CELL_SIZE,</div><div class='del'>-				v4l2_ctrl_ptr_create((void *)&amp;unit_size));</div><div class='del'>-	ret = imx214-&gt;ctrls.error;</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;client-&gt;dev, "%s control init failed (%d)\n",</div><div class='del'>-			__func__, ret);</div><div class='del'>-		goto free_ctrl;</div><div class='del'>-	}</div><div class='add'>+	ret = imx214_ctrls_init(imx214);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto error_power_off;</div><div class='ctx'> </div><div class='del'>-	imx214-&gt;sd.ctrl_handler = &amp;imx214-&gt;ctrls;</div><div class='ctx'> 	mutex_init(&amp;imx214-&gt;mutex);</div><div class='ctx'> 	imx214-&gt;ctrls.lock = &amp;imx214-&gt;mutex;</div><div class='ctx'> </div><div class='hunk'>@@ -1021,7 +1097,7 @@ static int imx214_probe(struct i2c_client *client)</div><div class='ctx'> 		goto free_ctrl;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	imx214_entity_init_cfg(&amp;imx214-&gt;sd, NULL);</div><div class='add'>+	imx214_entity_init_state(&amp;imx214-&gt;sd, NULL);</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_async_register_subdev_sensor(&amp;imx214-&gt;sd);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='hunk'>@@ -1036,6 +1112,7 @@ free_entity:</div><div class='ctx'> free_ctrl:</div><div class='ctx'> 	mutex_destroy(&amp;imx214-&gt;mutex);</div><div class='ctx'> 	v4l2_ctrl_handler_free(&amp;imx214-&gt;ctrls);</div><div class='add'>+error_power_off:</div><div class='ctx'> 	pm_runtime_disable(imx214-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='head'>diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c<br/>index 8436880dcf7a..e17ef2e9d9d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx219.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx219.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx219.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx219.c</a></div><div class='hunk'>@@ -374,7 +374,7 @@ static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;imx219-&gt;sd);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;imx219-&gt;sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl-&gt;id == V4L2_CID_VBLANK) {</div><div class='ctx'> 		int exposure_max, exposure_def;</div><div class='hunk'>@@ -593,8 +593,8 @@ static int imx219_set_framefmt(struct imx219 *imx219,</div><div class='ctx'> 	u64 bin_h, bin_v;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;imx219-&gt;sd, state, 0);</div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(&amp;imx219-&gt;sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	switch (format-&gt;code) {</div><div class='ctx'> 	case MEDIA_BUS_FMT_SRGGB8_1X8:</div><div class='hunk'>@@ -826,7 +826,7 @@ static int imx219_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	imx219_update_pad_format(imx219, mode, &amp;fmt-&gt;format, fmt-&gt;format.code);</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -836,7 +836,7 @@ static int imx219_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format-&gt;width, 2U);</div><div class='ctx'> 	bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format-&gt;height, 2U);</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> 	crop-&gt;width = format-&gt;width * bin_h;</div><div class='ctx'> 	crop-&gt;height = format-&gt;height * bin_v;</div><div class='ctx'> 	crop-&gt;left = (IMX219_NATIVE_WIDTH - crop-&gt;width) / 2;</div><div class='hunk'>@@ -880,7 +880,7 @@ static int imx219_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP: {</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -905,8 +905,8 @@ static int imx219_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx219_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int imx219_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='hunk'>@@ -933,7 +933,6 @@ static const struct v4l2_subdev_video_ops imx219_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx219_pad_ops = {</div><div class='del'>-	.init_cfg = imx219_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = imx219_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = imx219_set_pad_format,</div><div class='hunk'>@@ -947,6 +946,9 @@ static const struct v4l2_subdev_ops imx219_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx219_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx219_internal_ops = {</div><div class='add'>+	.init_state = imx219_init_state,</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Power management</div><div class='hunk'>@@ -1098,6 +1100,7 @@ static int imx219_probe(struct i2c_client *client)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx219-&gt;sd, client, &amp;imx219_subdev_ops);</div><div class='add'>+	imx219-&gt;sd.internal_ops = &amp;imx219_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	/* Check the hardware configuration in device tree */</div><div class='ctx'> 	if (imx219_check_hwcfg(dev, imx219))</div><div class='head'>diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c<br/>index b3827f4bc0eb..a577afb530b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx258.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx258.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx258.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx258.c</a></div><div class='hunk'>@@ -708,7 +708,7 @@ static int imx258_write_regs(struct imx258 *imx258,</div><div class='ctx'> static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize try_fmt */</div><div class='ctx'> 	try_fmt-&gt;width = supported_modes[0].width;</div><div class='hunk'>@@ -862,9 +862,8 @@ static int __imx258_get_pad_format(struct imx258 *imx258,</div><div class='ctx'> 				   struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;imx258-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		imx258_update_pad_format(imx258-&gt;cur_mode, fmt);</div><div class='ctx'> </div><div class='hunk'>@@ -908,7 +907,7 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 		fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	imx258_update_pad_format(mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx258-&gt;cur_mode = mode;</div><div class='head'>diff --git a/drivers/media/i2c/imx274.c b/drivers/media/i2c/imx274.c<br/>index f33b692e6951..352da68b8b41 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx274.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx274.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx274.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx274.c</a></div><div class='hunk'>@@ -594,8 +594,8 @@ static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl);</div><div class='ctx'> static int imx274_set_exposure(struct stimx274 *priv, int val);</div><div class='ctx'> static int imx274_set_vflip(struct stimx274 *priv, int val);</div><div class='ctx'> static int imx274_set_test_pattern(struct stimx274 *priv, int val);</div><div class='del'>-static int imx274_set_frame_interval(struct stimx274 *priv,</div><div class='del'>-				     struct v4l2_fract frame_interval);</div><div class='add'>+static int __imx274_set_frame_interval(struct stimx274 *priv,</div><div class='add'>+				       struct v4l2_fract frame_interval);</div><div class='ctx'> </div><div class='ctx'> static inline void msleep_range(unsigned int delay_base)</div><div class='ctx'> {</div><div class='hunk'>@@ -1018,8 +1018,8 @@ static int __imx274_change_compose(struct stimx274 *imx274,</div><div class='ctx'> 	int best_goodness = INT_MIN;</div><div class='ctx'> </div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		cur_crop = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='del'>-		tgt_fmt = &amp;sd_state-&gt;pads-&gt;try_fmt;</div><div class='add'>+		cur_crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+		tgt_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		cur_crop = &amp;imx274-&gt;crop;</div><div class='ctx'> 		tgt_fmt = &amp;imx274-&gt;format;</div><div class='hunk'>@@ -1112,7 +1112,7 @@ static int imx274_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	 */</div><div class='ctx'> 	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *fmt;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *fmt;</div><div class='ctx'> 	else</div><div class='ctx'> 		imx274-&gt;format = *fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -1143,8 +1143,8 @@ static int imx274_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		src_crop = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='del'>-		src_fmt = &amp;sd_state-&gt;pads-&gt;try_fmt;</div><div class='add'>+		src_crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+		src_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		src_crop = &amp;imx274-&gt;crop;</div><div class='ctx'> 		src_fmt = &amp;imx274-&gt;format;</div><div class='hunk'>@@ -1215,7 +1215,7 @@ static int imx274_set_selection_crop(struct stimx274 *imx274,</div><div class='ctx'> 	sel-&gt;r = new_crop;</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		tgt_crop = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='add'>+		tgt_crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		tgt_crop = &amp;imx274-&gt;crop;</div><div class='ctx'> </div><div class='hunk'>@@ -1327,20 +1327,19 @@ static int imx274_apply_trimming(struct stimx274 *imx274)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * imx274_g_frame_interval - Get the frame interval</div><div class='del'>- * @sd: Pointer to V4L2 Sub device structure</div><div class='del'>- * @fi: Pointer to V4l2 Sub device frame interval structure</div><div class='del'>- *</div><div class='del'>- * This function is used to get the frame interval.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='del'>-static int imx274_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int imx274_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct stimx274 *imx274 = to_imx274(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	fi-&gt;interval = imx274-&gt;frame_interval;</div><div class='ctx'> 	dev_dbg(&amp;imx274-&gt;client-&gt;dev, "%s frame rate = %d / %d\n",</div><div class='ctx'> 		__func__, imx274-&gt;frame_interval.numerator,</div><div class='hunk'>@@ -1349,29 +1348,28 @@ static int imx274_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * imx274_s_frame_interval - Set the frame interval</div><div class='del'>- * @sd: Pointer to V4L2 Sub device structure</div><div class='del'>- * @fi: Pointer to V4l2 Sub device frame interval structure</div><div class='del'>- *</div><div class='del'>- * This function is used to set the frame intervavl.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='del'>-static int imx274_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int imx274_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct stimx274 *imx274 = to_imx274(sd);</div><div class='ctx'> 	struct v4l2_ctrl *ctrl = imx274-&gt;ctrls.exposure;</div><div class='ctx'> 	int min, max, def;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	ret = pm_runtime_resume_and_get(&amp;imx274-&gt;client-&gt;dev);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;imx274-&gt;lock);</div><div class='del'>-	ret = imx274_set_frame_interval(imx274, fi-&gt;interval);</div><div class='add'>+	ret = __imx274_set_frame_interval(imx274, fi-&gt;interval);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		fi-&gt;interval = imx274-&gt;frame_interval;</div><div class='hunk'>@@ -1466,8 +1464,8 @@ static int imx274_s_stream(struct v4l2_subdev *sd, int on)</div><div class='ctx'> 		 * are changed.</div><div class='ctx'> 		 * gain is not affected.</div><div class='ctx'> 		 */</div><div class='del'>-		ret = imx274_set_frame_interval(imx274,</div><div class='del'>-						imx274-&gt;frame_interval);</div><div class='add'>+		ret = __imx274_set_frame_interval(imx274,</div><div class='add'>+						  imx274-&gt;frame_interval);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto fail;</div><div class='ctx'> </div><div class='hunk'>@@ -1830,7 +1828,7 @@ fail:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * imx274_set_frame_interval - Function called when setting frame interval</div><div class='add'>+ * __imx274_set_frame_interval - Function called when setting frame interval</div><div class='ctx'>  * @priv: Pointer to device structure</div><div class='ctx'>  * @frame_interval: Variable for frame interval</div><div class='ctx'>  *</div><div class='hunk'>@@ -1839,8 +1837,8 @@ fail:</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 on success</div><div class='ctx'>  */</div><div class='del'>-static int imx274_set_frame_interval(struct stimx274 *priv,</div><div class='del'>-				     struct v4l2_fract frame_interval)</div><div class='add'>+static int __imx274_set_frame_interval(struct stimx274 *priv,</div><div class='add'>+				       struct v4l2_fract frame_interval)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 frame_length, req_frame_rate;</div><div class='hunk'>@@ -1927,11 +1925,11 @@ static const struct v4l2_subdev_pad_ops imx274_pad_ops = {</div><div class='ctx'> 	.set_fmt = imx274_set_fmt,</div><div class='ctx'> 	.get_selection = imx274_get_selection,</div><div class='ctx'> 	.set_selection = imx274_set_selection,</div><div class='add'>+	.get_frame_interval = imx274_get_frame_interval,</div><div class='add'>+	.set_frame_interval = imx274_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops imx274_video_ops = {</div><div class='del'>-	.g_frame_interval = imx274_g_frame_interval,</div><div class='del'>-	.s_frame_interval = imx274_s_frame_interval,</div><div class='ctx'> 	.s_stream = imx274_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/imx290.c b/drivers/media/i2c/imx290.c<br/>index 29098612813c..9967f3477433 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx290.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx290.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx290.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx290.c</a></div><div class='hunk'>@@ -41,18 +41,18 @@</div><div class='ctx'> #define IMX290_WINMODE_720P				(1 &lt;&lt; 4)</div><div class='ctx'> #define IMX290_WINMODE_CROP				(4 &lt;&lt; 4)</div><div class='ctx'> #define IMX290_FR_FDG_SEL				CCI_REG8(0x3009)</div><div class='del'>-#define IMX290_BLKLEVEL					CCI_REG16(0x300a)</div><div class='add'>+#define IMX290_BLKLEVEL					CCI_REG16_LE(0x300a)</div><div class='ctx'> #define IMX290_GAIN					CCI_REG8(0x3014)</div><div class='del'>-#define IMX290_VMAX					CCI_REG24(0x3018)</div><div class='add'>+#define IMX290_VMAX					CCI_REG24_LE(0x3018)</div><div class='ctx'> #define IMX290_VMAX_MAX					0x3ffff</div><div class='del'>-#define IMX290_HMAX					CCI_REG16(0x301c)</div><div class='add'>+#define IMX290_HMAX					CCI_REG16_LE(0x301c)</div><div class='ctx'> #define IMX290_HMAX_MAX					0xffff</div><div class='del'>-#define IMX290_SHS1					CCI_REG24(0x3020)</div><div class='add'>+#define IMX290_SHS1					CCI_REG24_LE(0x3020)</div><div class='ctx'> #define IMX290_WINWV_OB					CCI_REG8(0x303a)</div><div class='del'>-#define IMX290_WINPV					CCI_REG16(0x303c)</div><div class='del'>-#define IMX290_WINWV					CCI_REG16(0x303e)</div><div class='del'>-#define IMX290_WINPH					CCI_REG16(0x3040)</div><div class='del'>-#define IMX290_WINWH					CCI_REG16(0x3042)</div><div class='add'>+#define IMX290_WINPV					CCI_REG16_LE(0x303c)</div><div class='add'>+#define IMX290_WINWV					CCI_REG16_LE(0x303e)</div><div class='add'>+#define IMX290_WINPH					CCI_REG16_LE(0x3040)</div><div class='add'>+#define IMX290_WINWH					CCI_REG16_LE(0x3042)</div><div class='ctx'> #define IMX290_OUT_CTRL					CCI_REG8(0x3046)</div><div class='ctx'> #define IMX290_ODBIT_10BIT				(0 &lt;&lt; 0)</div><div class='ctx'> #define IMX290_ODBIT_12BIT				(1 &lt;&lt; 0)</div><div class='hunk'>@@ -78,28 +78,28 @@</div><div class='ctx'> #define IMX290_ADBIT2					CCI_REG8(0x317c)</div><div class='ctx'> #define IMX290_ADBIT2_10BIT				0x12</div><div class='ctx'> #define IMX290_ADBIT2_12BIT				0x00</div><div class='del'>-#define IMX290_CHIP_ID					CCI_REG16(0x319a)</div><div class='add'>+#define IMX290_CHIP_ID					CCI_REG16_LE(0x319a)</div><div class='ctx'> #define IMX290_ADBIT3					CCI_REG8(0x31ec)</div><div class='ctx'> #define IMX290_ADBIT3_10BIT				0x37</div><div class='ctx'> #define IMX290_ADBIT3_12BIT				0x0e</div><div class='ctx'> #define IMX290_REPETITION				CCI_REG8(0x3405)</div><div class='ctx'> #define IMX290_PHY_LANE_NUM				CCI_REG8(0x3407)</div><div class='ctx'> #define IMX290_OPB_SIZE_V				CCI_REG8(0x3414)</div><div class='del'>-#define IMX290_Y_OUT_SIZE				CCI_REG16(0x3418)</div><div class='del'>-#define IMX290_CSI_DT_FMT				CCI_REG16(0x3441)</div><div class='add'>+#define IMX290_Y_OUT_SIZE				CCI_REG16_LE(0x3418)</div><div class='add'>+#define IMX290_CSI_DT_FMT				CCI_REG16_LE(0x3441)</div><div class='ctx'> #define IMX290_CSI_DT_FMT_RAW10				0x0a0a</div><div class='ctx'> #define IMX290_CSI_DT_FMT_RAW12				0x0c0c</div><div class='ctx'> #define IMX290_CSI_LANE_MODE				CCI_REG8(0x3443)</div><div class='del'>-#define IMX290_EXTCK_FREQ				CCI_REG16(0x3444)</div><div class='del'>-#define IMX290_TCLKPOST					CCI_REG16(0x3446)</div><div class='del'>-#define IMX290_THSZERO					CCI_REG16(0x3448)</div><div class='del'>-#define IMX290_THSPREPARE				CCI_REG16(0x344a)</div><div class='del'>-#define IMX290_TCLKTRAIL				CCI_REG16(0x344c)</div><div class='del'>-#define IMX290_THSTRAIL					CCI_REG16(0x344e)</div><div class='del'>-#define IMX290_TCLKZERO					CCI_REG16(0x3450)</div><div class='del'>-#define IMX290_TCLKPREPARE				CCI_REG16(0x3452)</div><div class='del'>-#define IMX290_TLPX					CCI_REG16(0x3454)</div><div class='del'>-#define IMX290_X_OUT_SIZE				CCI_REG16(0x3472)</div><div class='add'>+#define IMX290_EXTCK_FREQ				CCI_REG16_LE(0x3444)</div><div class='add'>+#define IMX290_TCLKPOST					CCI_REG16_LE(0x3446)</div><div class='add'>+#define IMX290_THSZERO					CCI_REG16_LE(0x3448)</div><div class='add'>+#define IMX290_THSPREPARE				CCI_REG16_LE(0x344a)</div><div class='add'>+#define IMX290_TCLKTRAIL				CCI_REG16_LE(0x344c)</div><div class='add'>+#define IMX290_THSTRAIL					CCI_REG16_LE(0x344e)</div><div class='add'>+#define IMX290_TCLKZERO					CCI_REG16_LE(0x3450)</div><div class='add'>+#define IMX290_TCLKPREPARE				CCI_REG16_LE(0x3452)</div><div class='add'>+#define IMX290_TLPX					CCI_REG16_LE(0x3454)</div><div class='add'>+#define IMX290_X_OUT_SIZE				CCI_REG16_LE(0x3472)</div><div class='ctx'> #define IMX290_INCKSEL7					CCI_REG8(0x3480)</div><div class='ctx'> </div><div class='ctx'> #define IMX290_PGCTRL_REGEN				BIT(0)</div><div class='hunk'>@@ -758,7 +758,7 @@ static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;imx290-&gt;sd);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;imx290-&gt;sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	switch (ctrl-&gt;id) {</div><div class='ctx'> 	case V4L2_CID_ANALOGUE_GAIN:</div><div class='hunk'>@@ -994,7 +994,7 @@ static int imx290_start_streaming(struct imx290 *imx290,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Apply the register values related to current frame format */</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;imx290-&gt;sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	ret = imx290_setup_format(imx290, format);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(imx290-&gt;dev, "Could not set frame format - %d\n", ret);</div><div class='hunk'>@@ -1132,7 +1132,7 @@ static int imx290_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	fmt-&gt;format.quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='ctx'> 	fmt-&gt;format.xfer_func = V4L2_XFER_FUNC_NONE;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, sd_state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE) {</div><div class='ctx'> 		imx290-&gt;current_mode = mode;</div><div class='hunk'>@@ -1155,7 +1155,7 @@ static int imx290_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP: {</div><div class='del'>-		format = v4l2_subdev_get_pad_format(sd, sd_state, 0);</div><div class='add'>+		format = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The sensor moves the readout by 1 pixel based on flips to</div><div class='hunk'>@@ -1195,8 +1195,8 @@ static int imx290_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx290_entity_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				    struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='hunk'>@@ -1221,7 +1221,6 @@ static const struct v4l2_subdev_video_ops imx290_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx290_pad_ops = {</div><div class='del'>-	.init_cfg = imx290_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = imx290_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = imx290_enum_frame_size,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -1235,6 +1234,10 @@ static const struct v4l2_subdev_ops imx290_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx290_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx290_internal_ops = {</div><div class='add'>+	.init_state = imx290_entity_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations imx290_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -1248,6 +1251,7 @@ static int imx290_subdev_init(struct imx290 *imx290)</div><div class='ctx'> 	imx290-&gt;current_mode = &amp;imx290_modes_ptr(imx290)[0];</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx290-&gt;sd, client, &amp;imx290_subdev_ops);</div><div class='add'>+	imx290-&gt;sd.internal_ops = &amp;imx290_internal_ops;</div><div class='ctx'> 	imx290-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 			    V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	imx290-&gt;sd.dev = imx290-&gt;dev;</div><div class='head'>diff --git a/drivers/media/i2c/imx296.c b/drivers/media/i2c/imx296.c<br/>index 94aac9d2732f..83149fa729c4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx296.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx296.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx296.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx296.c</a></div><div class='hunk'>@@ -323,7 +323,7 @@ static int imx296_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;sensor-&gt;subdev);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;subdev, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	switch (ctrl-&gt;id) {</div><div class='ctx'> 	case V4L2_CID_EXPOSURE:</div><div class='hunk'>@@ -511,8 +511,8 @@ static int imx296_setup(struct imx296 *sensor, struct v4l2_subdev_state *state)</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;subdev, state, 0);</div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(&amp;sensor-&gt;subdev, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(imx296_init_table); ++i)</div><div class='ctx'> 		imx296_write(sensor, imx296_init_table[i].reg,</div><div class='hunk'>@@ -662,7 +662,7 @@ static int imx296_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fse-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fse-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fse-&gt;index &gt;= 2 || fse-&gt;code != format-&gt;code)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -683,8 +683,8 @@ static int imx296_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, fmt-&gt;pad);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fmt-&gt;pad);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, fmt-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Binning is only allowed when cropping is disabled according to the</div><div class='hunk'>@@ -732,7 +732,7 @@ static int imx296_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, state, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(state, sel-&gt;pad);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='hunk'>@@ -780,14 +780,14 @@ static int imx296_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	rect.height = min_t(unsigned int, rect.height,</div><div class='ctx'> 			    IMX296_PIXEL_ARRAY_HEIGHT - rect.top);</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, sel-&gt;pad);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, sel-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (rect.width != crop-&gt;width || rect.height != crop-&gt;height) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Reset the output image size if the crop rectangle size has</div><div class='ctx'> 		 * been modified.</div><div class='ctx'> 		 */</div><div class='del'>-		format = v4l2_subdev_get_pad_format(sd, state, sel-&gt;pad);</div><div class='add'>+		format = v4l2_subdev_state_get_format(state, sel-&gt;pad);</div><div class='ctx'> 		format-&gt;width = rect.width;</div><div class='ctx'> 		format-&gt;height = rect.height;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -798,8 +798,8 @@ static int imx296_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx296_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int imx296_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_selection sel = {</div><div class='ctx'> 		.target = V4L2_SEL_TGT_CROP,</div><div class='hunk'>@@ -830,7 +830,6 @@ static const struct v4l2_subdev_pad_ops imx296_subdev_pad_ops = {</div><div class='ctx'> 	.set_fmt = imx296_set_format,</div><div class='ctx'> 	.get_selection = imx296_get_selection,</div><div class='ctx'> 	.set_selection = imx296_set_selection,</div><div class='del'>-	.init_cfg = imx296_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops imx296_subdev_ops = {</div><div class='hunk'>@@ -838,12 +837,17 @@ static const struct v4l2_subdev_ops imx296_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx296_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx296_internal_ops = {</div><div class='add'>+	.init_state = imx296_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int imx296_subdev_init(struct imx296 *sensor)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(sensor-&gt;dev);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;sensor-&gt;subdev, client, &amp;imx296_subdev_ops);</div><div class='add'>+	sensor-&gt;subdev.internal_ops = &amp;imx296_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx296_ctrls_init(sensor);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='head'>diff --git a/drivers/media/i2c/imx319.c b/drivers/media/i2c/imx319.c<br/>index 5378f607f340..e47eff672e0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx319.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx319.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx319.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx319.c</a></div><div class='hunk'>@@ -1860,7 +1860,7 @@ static int imx319_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx319 *imx319 = to_imx319(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;imx319-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -2001,10 +2001,9 @@ static int imx319_do_get_pad_format(struct imx319 *imx319,</div><div class='ctx'> 				    struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *framefmt;</div><div class='del'>-	struct v4l2_subdev *sd = &amp;imx319-&gt;sd;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx319_update_pad_format(imx319, imx319-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -2055,7 +2054,7 @@ imx319_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	imx319_update_pad_format(imx319, mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx319-&gt;cur_mode = mode;</div><div class='hunk'>@@ -2464,19 +2463,21 @@ static int imx319_probe(struct i2c_client *client)</div><div class='ctx'> 		goto error_handler_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_async_register_subdev_sensor(&amp;imx319-&gt;sd);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		goto error_media_entity;</div><div class='del'>-</div><div class='ctx'> 	/* Set the device's state to active if it's in D0 state. */</div><div class='ctx'> 	if (full_power)</div><div class='ctx'> 		pm_runtime_set_active(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_enable(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_idle(&amp;client-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;imx319-&gt;sd);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto error_media_entity_pm;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-error_media_entity:</div><div class='add'>+error_media_entity_pm:</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> 	media_entity_cleanup(&amp;imx319-&gt;sd.entity);</div><div class='ctx'> </div><div class='ctx'> error_handler_free:</div><div class='head'>diff --git a/drivers/media/i2c/imx334.c b/drivers/media/i2c/imx334.c<br/>index 1196fe93506b..6725b3e2a73e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx334.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx334.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx334.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx334.c</a></div><div class='hunk'>@@ -879,7 +879,7 @@ static int imx334_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		fmt-&gt;format.code = imx334-&gt;cur_code;</div><div class='hunk'>@@ -920,7 +920,7 @@ static int imx334_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else if (imx334-&gt;cur_mode != mode || imx334-&gt;cur_code != fmt-&gt;format.code) {</div><div class='ctx'> 		imx334-&gt;cur_code = fmt-&gt;format.code;</div><div class='hunk'>@@ -935,14 +935,14 @@ static int imx334_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * imx334_init_pad_cfg() - Initialize sub-device pad configuration</div><div class='add'>+ * imx334_init_state() - Initialize sub-device state</div><div class='ctx'>  * @sd: pointer to imx334 V4L2 sub-device structure</div><div class='ctx'>  * @sd_state: V4L2 sub-device state</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 if successful, error code otherwise.</div><div class='ctx'>  */</div><div class='del'>-static int imx334_init_pad_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx334_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx334 *imx334 = to_imx334(sd);</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='hunk'>@@ -1190,7 +1190,6 @@ static const struct v4l2_subdev_video_ops imx334_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx334_pad_ops = {</div><div class='del'>-	.init_cfg = imx334_init_pad_cfg,</div><div class='ctx'> 	.enum_mbus_code = imx334_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = imx334_enum_frame_size,</div><div class='ctx'> 	.get_fmt = imx334_get_pad_format,</div><div class='hunk'>@@ -1202,6 +1201,10 @@ static const struct v4l2_subdev_ops imx334_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx334_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx334_internal_ops = {</div><div class='add'>+	.init_state = imx334_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * imx334_power_on() - Sensor power on sequence</div><div class='ctx'>  * @dev: pointer to i2c device</div><div class='hunk'>@@ -1359,6 +1362,7 @@ static int imx334_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx334-&gt;sd, client, &amp;imx334_subdev_ops);</div><div class='add'>+	imx334-&gt;sd.internal_ops = &amp;imx334_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx334_parse_hw_config(imx334);</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c<br/>index ec729126274b..7a37eb327ff4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx335.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx335.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx335.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx335.c</a></div><div class='hunk'>@@ -55,6 +55,14 @@</div><div class='ctx'> #define IMX335_REG_MIN		0x00</div><div class='ctx'> #define IMX335_REG_MAX		0xfffff</div><div class='ctx'> </div><div class='add'>+/* IMX335 native and active pixel array size. */</div><div class='add'>+#define IMX335_NATIVE_WIDTH		2616U</div><div class='add'>+#define IMX335_NATIVE_HEIGHT		1964U</div><div class='add'>+#define IMX335_PIXEL_ARRAY_LEFT		12U</div><div class='add'>+#define IMX335_PIXEL_ARRAY_TOP		12U</div><div class='add'>+#define IMX335_PIXEL_ARRAY_WIDTH	2592U</div><div class='add'>+#define IMX335_PIXEL_ARRAY_HEIGHT	1944U</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct imx335_reg - imx335 sensor register</div><div class='ctx'>  * @address: Register address</div><div class='hunk'>@@ -75,6 +83,12 @@ struct imx335_reg_list {</div><div class='ctx'> 	const struct imx335_reg *regs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const char * const imx335_supply_name[] = {</div><div class='add'>+	"avdd", /* Analog (2.9V) supply */</div><div class='add'>+	"ovdd", /* Digital I/O (1.8V) supply */</div><div class='add'>+	"dvdd", /* Digital Core (1.2V) supply */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct imx335_mode - imx335 sensor mode structure</div><div class='ctx'>  * @width: Frame width</div><div class='hunk'>@@ -108,6 +122,7 @@ struct imx335_mode {</div><div class='ctx'>  * @sd: V4L2 sub-device</div><div class='ctx'>  * @pad: Media pad. Only one pad supported</div><div class='ctx'>  * @reset_gpio: Sensor reset gpio</div><div class='add'>+ * @supplies: Regulator supplies to handle power control</div><div class='ctx'>  * @inclk: Sensor input clock</div><div class='ctx'>  * @ctrl_handler: V4L2 control handler</div><div class='ctx'>  * @link_freq_ctrl: Pointer to link frequency control</div><div class='hunk'>@@ -119,6 +134,7 @@ struct imx335_mode {</div><div class='ctx'>  * @vblank: Vertical blanking in lines</div><div class='ctx'>  * @cur_mode: Pointer to current selected sensor mode</div><div class='ctx'>  * @mutex: Mutex for serializing sensor controls</div><div class='add'>+ * @cur_mbus_code: Currently selected media bus format code</div><div class='ctx'>  */</div><div class='ctx'> struct imx335 {</div><div class='ctx'> 	struct device *dev;</div><div class='hunk'>@@ -126,6 +142,8 @@ struct imx335 {</div><div class='ctx'> 	struct v4l2_subdev sd;</div><div class='ctx'> 	struct media_pad pad;</div><div class='ctx'> 	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct regulator_bulk_data supplies[ARRAY_SIZE(imx335_supply_name)];</div><div class='add'>+</div><div class='ctx'> 	struct clk *inclk;</div><div class='ctx'> 	struct v4l2_ctrl_handler ctrl_handler;</div><div class='ctx'> 	struct v4l2_ctrl *link_freq_ctrl;</div><div class='hunk'>@@ -139,6 +157,7 @@ struct imx335 {</div><div class='ctx'> 	u32 vblank;</div><div class='ctx'> 	const struct imx335_mode *cur_mode;</div><div class='ctx'> 	struct mutex mutex;</div><div class='add'>+	u32 cur_mbus_code;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const s64 link_freq[] = {</div><div class='hunk'>@@ -233,6 +252,25 @@ static const struct imx335_reg mode_2592x1940_regs[] = {</div><div class='ctx'> 	{0x3a00, 0x01},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct imx335_reg raw10_framefmt_regs[] = {</div><div class='add'>+	{0x3050, 0x00},</div><div class='add'>+	{0x319d, 0x00},</div><div class='add'>+	{0x341c, 0xff},</div><div class='add'>+	{0x341d, 0x01},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct imx335_reg raw12_framefmt_regs[] = {</div><div class='add'>+	{0x3050, 0x01},</div><div class='add'>+	{0x319d, 0x01},</div><div class='add'>+	{0x341c, 0x47},</div><div class='add'>+	{0x341d, 0x00},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 imx335_mbus_codes[] = {</div><div class='add'>+	MEDIA_BUS_FMT_SRGGB12_1X12,</div><div class='add'>+	MEDIA_BUS_FMT_SRGGB10_1X10,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Supported sensor mode configurations */</div><div class='ctx'> static const struct imx335_mode supported_mode = {</div><div class='ctx'> 	.width = 2592,</div><div class='hunk'>@@ -243,7 +281,6 @@ static const struct imx335_mode supported_mode = {</div><div class='ctx'> 	.vblank_max = 133060,</div><div class='ctx'> 	.pclk = 396000000,</div><div class='ctx'> 	.link_freq_idx = 0,</div><div class='del'>-	.code = MEDIA_BUS_FMT_SRGGB12_1X12,</div><div class='ctx'> 	.reg_list = {</div><div class='ctx'> 		.num_of_regs = ARRAY_SIZE(mode_2592x1940_regs),</div><div class='ctx'> 		.regs = mode_2592x1940_regs,</div><div class='hunk'>@@ -396,7 +433,7 @@ static int imx335_update_exp_gain(struct imx335 *imx335, u32 exposure, u32 gain)</div><div class='ctx'> 	lpfr = imx335-&gt;vblank + imx335-&gt;cur_mode-&gt;height;</div><div class='ctx'> 	shutter = lpfr - exposure;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(imx335-&gt;dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u",</div><div class='add'>+	dev_dbg(imx335-&gt;dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u\n",</div><div class='ctx'> 		exposure, gain, shutter, lpfr);</div><div class='ctx'> </div><div class='ctx'> 	ret = imx335_write_reg(imx335, IMX335_REG_HOLD, 1, 1);</div><div class='hunk'>@@ -443,7 +480,7 @@ static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 	case V4L2_CID_VBLANK:</div><div class='ctx'> 		imx335-&gt;vblank = imx335-&gt;vblank_ctrl-&gt;val;</div><div class='ctx'> </div><div class='del'>-		dev_dbg(imx335-&gt;dev, "Received vblank %u, new lpfr %u",</div><div class='add'>+		dev_dbg(imx335-&gt;dev, "Received vblank %u, new lpfr %u\n",</div><div class='ctx'> 			imx335-&gt;vblank,</div><div class='ctx'> 			imx335-&gt;vblank + imx335-&gt;cur_mode-&gt;height);</div><div class='ctx'> </div><div class='hunk'>@@ -462,7 +499,7 @@ static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 		exposure = ctrl-&gt;val;</div><div class='ctx'> 		analog_gain = imx335-&gt;again_ctrl-&gt;val;</div><div class='ctx'> </div><div class='del'>-		dev_dbg(imx335-&gt;dev, "Received exp %u, analog gain %u",</div><div class='add'>+		dev_dbg(imx335-&gt;dev, "Received exp %u, analog gain %u\n",</div><div class='ctx'> 			exposure, analog_gain);</div><div class='ctx'> </div><div class='ctx'> 		ret = imx335_update_exp_gain(imx335, exposure, analog_gain);</div><div class='hunk'>@@ -471,7 +508,7 @@ static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		dev_err(imx335-&gt;dev, "Invalid control %d", ctrl-&gt;id);</div><div class='add'>+		dev_err(imx335-&gt;dev, "Invalid control %d\n", ctrl-&gt;id);</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -483,6 +520,18 @@ static const struct v4l2_ctrl_ops imx335_ctrl_ops = {</div><div class='ctx'> 	.s_ctrl = imx335_set_ctrl,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int imx335_get_format_code(struct imx335 *imx335, u32 code)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(imx335_mbus_codes); i++) {</div><div class='add'>+		if (imx335_mbus_codes[i] == code)</div><div class='add'>+			return imx335_mbus_codes[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return imx335_mbus_codes[0];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * imx335_enum_mbus_code() - Enumerate V4L2 sub-device mbus codes</div><div class='ctx'>  * @sd: pointer to imx335 V4L2 sub-device structure</div><div class='hunk'>@@ -495,10 +544,10 @@ static int imx335_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 				 struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='ctx'> {</div><div class='del'>-	if (code-&gt;index &gt; 0)</div><div class='add'>+	if (code-&gt;index &gt;= ARRAY_SIZE(imx335_mbus_codes))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	code-&gt;code = supported_mode.code;</div><div class='add'>+	code-&gt;code = imx335_mbus_codes[code-&gt;index];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -515,10 +564,14 @@ static int imx335_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 				  struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				  struct v4l2_subdev_frame_size_enum *fsize)</div><div class='ctx'> {</div><div class='del'>-	if (fsize-&gt;index &gt; 0)</div><div class='add'>+	struct imx335 *imx335 = to_imx335(sd);</div><div class='add'>+	u32 code;</div><div class='add'>+</div><div class='add'>+	if (fsize-&gt;index &gt; ARRAY_SIZE(imx335_mbus_codes))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (fsize-&gt;code != supported_mode.code)</div><div class='add'>+	code = imx335_get_format_code(imx335, fsize-&gt;code);</div><div class='add'>+	if (fsize-&gt;code != code)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	fsize-&gt;min_width = supported_mode.width;</div><div class='hunk'>@@ -542,7 +595,7 @@ static void imx335_fill_pad_format(struct imx335 *imx335,</div><div class='ctx'> {</div><div class='ctx'> 	fmt-&gt;format.width = mode-&gt;width;</div><div class='ctx'> 	fmt-&gt;format.height = mode-&gt;height;</div><div class='del'>-	fmt-&gt;format.code = mode-&gt;code;</div><div class='add'>+	fmt-&gt;format.code = imx335-&gt;cur_mbus_code;</div><div class='ctx'> 	fmt-&gt;format.field = V4L2_FIELD_NONE;</div><div class='ctx'> 	fmt-&gt;format.colorspace = V4L2_COLORSPACE_RAW;</div><div class='ctx'> 	fmt-&gt;format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;</div><div class='hunk'>@@ -569,7 +622,7 @@ static int imx335_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx335_fill_pad_format(imx335, imx335-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -594,17 +647,22 @@ static int imx335_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	struct imx335 *imx335 = to_imx335(sd);</div><div class='ctx'> 	const struct imx335_mode *mode;</div><div class='del'>-	int ret = 0;</div><div class='add'>+	int i, ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;imx335-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	mode = &amp;supported_mode;</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(imx335_mbus_codes); i++) {</div><div class='add'>+		if (imx335_mbus_codes[i] == fmt-&gt;format.code)</div><div class='add'>+			imx335-&gt;cur_mbus_code = imx335_mbus_codes[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	imx335_fill_pad_format(imx335, mode, fmt);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = imx335_update_controls(imx335, mode);</div><div class='hunk'>@@ -618,14 +676,14 @@ static int imx335_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * imx335_init_pad_cfg() - Initialize sub-device pad configuration</div><div class='add'>+ * imx335_init_state() - Initialize sub-device state</div><div class='ctx'>  * @sd: pointer to imx335 V4L2 sub-device structure</div><div class='ctx'>  * @sd_state: V4L2 sub-device configuration</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 if successful, error code otherwise.</div><div class='ctx'>  */</div><div class='del'>-static int imx335_init_pad_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx335_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx335 *imx335 = to_imx335(sd);</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='hunk'>@@ -637,6 +695,56 @@ static int imx335_init_pad_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * imx335_get_selection() - Selection API</div><div class='add'>+ * @sd: pointer to imx335 V4L2 sub-device structure</div><div class='add'>+ * @sd_state: V4L2 sub-device configuration</div><div class='add'>+ * @sel: V4L2 selection info</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 if successful, error code otherwise.</div><div class='add'>+ */</div><div class='add'>+static int imx335_get_selection(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state,</div><div class='add'>+				struct v4l2_subdev_selection *sel)</div><div class='add'>+{</div><div class='add'>+	switch (sel-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_NATIVE_SIZE:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = IMX335_NATIVE_WIDTH;</div><div class='add'>+		sel-&gt;r.height = IMX335_NATIVE_HEIGHT;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+		sel-&gt;r.top = IMX335_PIXEL_ARRAY_TOP;</div><div class='add'>+		sel-&gt;r.left = IMX335_PIXEL_ARRAY_LEFT;</div><div class='add'>+		sel-&gt;r.width = IMX335_PIXEL_ARRAY_WIDTH;</div><div class='add'>+		sel-&gt;r.height = IMX335_PIXEL_ARRAY_HEIGHT;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int imx335_set_framefmt(struct imx335 *imx335)</div><div class='add'>+{</div><div class='add'>+	switch (imx335-&gt;cur_mbus_code) {</div><div class='add'>+	case MEDIA_BUS_FMT_SRGGB10_1X10:</div><div class='add'>+		return imx335_write_regs(imx335, raw10_framefmt_regs,</div><div class='add'>+					 ARRAY_SIZE(raw10_framefmt_regs));</div><div class='add'>+</div><div class='add'>+	case MEDIA_BUS_FMT_SRGGB12_1X12:</div><div class='add'>+		return imx335_write_regs(imx335, raw12_framefmt_regs,</div><div class='add'>+					 ARRAY_SIZE(raw12_framefmt_regs));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * imx335_start_streaming() - Start sensor stream</div><div class='ctx'>  * @imx335: pointer to imx335 device</div><div class='ctx'>  *</div><div class='hunk'>@@ -652,14 +760,21 @@ static int imx335_start_streaming(struct imx335 *imx335)</div><div class='ctx'> 	ret = imx335_write_regs(imx335, reg_list-&gt;regs,</div><div class='ctx'> 				reg_list-&gt;num_of_regs);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "fail to write initial registers");</div><div class='add'>+		dev_err(imx335-&gt;dev, "fail to write initial registers\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = imx335_set_framefmt(imx335);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(imx335-&gt;dev, "%s failed to set frame format: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Setup handler will write actual exposure and gain */</div><div class='ctx'> 	ret =  __v4l2_ctrl_handler_setup(imx335-&gt;sd.ctrl_handler);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "fail to setup handler");</div><div class='add'>+		dev_err(imx335-&gt;dev, "fail to setup handler\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -667,7 +782,7 @@ static int imx335_start_streaming(struct imx335 *imx335)</div><div class='ctx'> 	ret = imx335_write_reg(imx335, IMX335_REG_MODE_SELECT,</div><div class='ctx'> 			       1, IMX335_MODE_STREAMING);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "fail to start streaming");</div><div class='add'>+		dev_err(imx335-&gt;dev, "fail to start streaming\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -744,7 +859,7 @@ static int imx335_detect(struct imx335 *imx335)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (val != IMX335_ID) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "chip id mismatch: %x!=%x",</div><div class='add'>+		dev_err(imx335-&gt;dev, "chip id mismatch: %x!=%x\n",</div><div class='ctx'> 			IMX335_ID, val);</div><div class='ctx'> 		return -ENXIO;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -776,27 +891,40 @@ static int imx335_parse_hw_config(struct imx335 *imx335)</div><div class='ctx'> 	imx335-&gt;reset_gpio = devm_gpiod_get_optional(imx335-&gt;dev, "reset",</div><div class='ctx'> 						     GPIOD_OUT_LOW);</div><div class='ctx'> 	if (IS_ERR(imx335-&gt;reset_gpio)) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "failed to get reset gpio %ld",</div><div class='add'>+		dev_err(imx335-&gt;dev, "failed to get reset gpio %ld\n",</div><div class='ctx'> 			PTR_ERR(imx335-&gt;reset_gpio));</div><div class='ctx'> 		return PTR_ERR(imx335-&gt;reset_gpio);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(imx335_supply_name); i++)</div><div class='add'>+		imx335-&gt;supplies[i].supply = imx335_supply_name[i];</div><div class='add'>+</div><div class='add'>+	ret = devm_regulator_bulk_get(imx335-&gt;dev,</div><div class='add'>+				      ARRAY_SIZE(imx335_supply_name),</div><div class='add'>+				      imx335-&gt;supplies);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(imx335-&gt;dev, "Failed to get regulators\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Get sensor input clock */</div><div class='ctx'> 	imx335-&gt;inclk = devm_clk_get(imx335-&gt;dev, NULL);</div><div class='ctx'> 	if (IS_ERR(imx335-&gt;inclk)) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "could not get inclk");</div><div class='add'>+		dev_err(imx335-&gt;dev, "could not get inclk\n");</div><div class='ctx'> 		return PTR_ERR(imx335-&gt;inclk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rate = clk_get_rate(imx335-&gt;inclk);</div><div class='ctx'> 	if (rate != IMX335_INCLK_RATE) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "inclk frequency mismatch");</div><div class='add'>+		dev_err(imx335-&gt;dev, "inclk frequency mismatch\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);</div><div class='del'>-	if (!ep)</div><div class='add'>+	if (!ep) {</div><div class='add'>+		dev_err(imx335-&gt;dev, "Failed to get next endpoint\n");</div><div class='ctx'> 		return -ENXIO;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &amp;bus_cfg);</div><div class='ctx'> 	fwnode_handle_put(ep);</div><div class='hunk'>@@ -805,14 +933,14 @@ static int imx335_parse_hw_config(struct imx335 *imx335)</div><div class='ctx'> </div><div class='ctx'> 	if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX335_NUM_DATA_LANES) {</div><div class='ctx'> 		dev_err(imx335-&gt;dev,</div><div class='del'>-			"number of CSI2 data lanes %d is not supported",</div><div class='add'>+			"number of CSI2 data lanes %d is not supported\n",</div><div class='ctx'> 			bus_cfg.bus.mipi_csi2.num_data_lanes);</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done_endpoint_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!bus_cfg.nr_of_link_frequencies) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "no link frequencies defined");</div><div class='add'>+		dev_err(imx335-&gt;dev, "no link frequencies defined\n");</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done_endpoint_free;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -821,6 +949,8 @@ static int imx335_parse_hw_config(struct imx335 *imx335)</div><div class='ctx'> 		if (bus_cfg.link_frequencies[i] == IMX335_LINK_FREQ)</div><div class='ctx'> 			goto done_endpoint_free;</div><div class='ctx'> </div><div class='add'>+	dev_err(imx335-&gt;dev, "no compatible link frequencies found\n");</div><div class='add'>+</div><div class='ctx'> 	ret = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> done_endpoint_free:</div><div class='hunk'>@@ -835,9 +965,10 @@ static const struct v4l2_subdev_video_ops imx335_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx335_pad_ops = {</div><div class='del'>-	.init_cfg = imx335_init_pad_cfg,</div><div class='ctx'> 	.enum_mbus_code = imx335_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = imx335_enum_frame_size,</div><div class='add'>+	.get_selection = imx335_get_selection,</div><div class='add'>+	.set_selection = imx335_get_selection,</div><div class='ctx'> 	.get_fmt = imx335_get_pad_format,</div><div class='ctx'> 	.set_fmt = imx335_set_pad_format,</div><div class='ctx'> };</div><div class='hunk'>@@ -847,6 +978,10 @@ static const struct v4l2_subdev_ops imx335_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx335_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx335_internal_ops = {</div><div class='add'>+	.init_state = imx335_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * imx335_power_on() - Sensor power on sequence</div><div class='ctx'>  * @dev: pointer to i2c device</div><div class='hunk'>@@ -859,20 +994,32 @@ static int imx335_power_on(struct device *dev)</div><div class='ctx'> 	struct imx335 *imx335 = to_imx335(sd);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	ret = regulator_bulk_enable(ARRAY_SIZE(imx335_supply_name),</div><div class='add'>+				    imx335-&gt;supplies);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "%s: failed to enable regulators\n",</div><div class='add'>+			__func__);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usleep_range(500, 550); /* Tlow */</div><div class='add'>+</div><div class='add'>+	/* Set XCLR */</div><div class='ctx'> 	gpiod_set_value_cansleep(imx335-&gt;reset_gpio, 1);</div><div class='ctx'> </div><div class='ctx'> 	ret = clk_prepare_enable(imx335-&gt;inclk);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "fail to enable inclk");</div><div class='add'>+		dev_err(imx335-&gt;dev, "fail to enable inclk\n");</div><div class='ctx'> 		goto error_reset;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	usleep_range(20, 22);</div><div class='add'>+	usleep_range(20, 22); /* T4 */</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> error_reset:</div><div class='ctx'> 	gpiod_set_value_cansleep(imx335-&gt;reset_gpio, 0);</div><div class='add'>+	regulator_bulk_disable(ARRAY_SIZE(imx335_supply_name), imx335-&gt;supplies);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -889,8 +1036,8 @@ static int imx335_power_off(struct device *dev)</div><div class='ctx'> 	struct imx335 *imx335 = to_imx335(sd);</div><div class='ctx'> </div><div class='ctx'> 	gpiod_set_value_cansleep(imx335-&gt;reset_gpio, 0);</div><div class='del'>-</div><div class='ctx'> 	clk_disable_unprepare(imx335-&gt;inclk);</div><div class='add'>+	regulator_bulk_disable(ARRAY_SIZE(imx335_supply_name), imx335-&gt;supplies);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -962,14 +1109,14 @@ static int imx335_init_controls(struct imx335 *imx335)</div><div class='ctx'> 	imx335-&gt;hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr,</div><div class='ctx'> 						&amp;imx335_ctrl_ops,</div><div class='ctx'> 						V4L2_CID_HBLANK,</div><div class='del'>-						IMX335_REG_MIN,</div><div class='del'>-						IMX335_REG_MAX,</div><div class='add'>+						mode-&gt;hblank,</div><div class='add'>+						mode-&gt;hblank,</div><div class='ctx'> 						1, mode-&gt;hblank);</div><div class='ctx'> 	if (imx335-&gt;hblank_ctrl)</div><div class='ctx'> 		imx335-&gt;hblank_ctrl-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl_hdlr-&gt;error) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "control init failed: %d",</div><div class='add'>+		dev_err(imx335-&gt;dev, "control init failed: %d\n",</div><div class='ctx'> 			ctrl_hdlr-&gt;error);</div><div class='ctx'> 		v4l2_ctrl_handler_free(ctrl_hdlr);</div><div class='ctx'> 		return ctrl_hdlr-&gt;error;</div><div class='hunk'>@@ -999,10 +1146,11 @@ static int imx335_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx335-&gt;sd, client, &amp;imx335_subdev_ops);</div><div class='add'>+	imx335-&gt;sd.internal_ops = &amp;imx335_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx335_parse_hw_config(imx335);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "HW configuration is not supported");</div><div class='add'>+		dev_err(imx335-&gt;dev, "HW configuration is not supported\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1010,24 +1158,25 @@ static int imx335_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	ret = imx335_power_on(imx335-&gt;dev);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "failed to power-on the sensor");</div><div class='add'>+		dev_err(imx335-&gt;dev, "failed to power-on the sensor\n");</div><div class='ctx'> 		goto error_mutex_destroy;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check module identity */</div><div class='ctx'> 	ret = imx335_detect(imx335);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "failed to find sensor: %d", ret);</div><div class='add'>+		dev_err(imx335-&gt;dev, "failed to find sensor: %d\n", ret);</div><div class='ctx'> 		goto error_power_off;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set default mode to max resolution */</div><div class='ctx'> 	imx335-&gt;cur_mode = &amp;supported_mode;</div><div class='add'>+	imx335-&gt;cur_mbus_code = imx335_mbus_codes[0];</div><div class='ctx'> 	imx335-&gt;vblank = imx335-&gt;cur_mode-&gt;vblank;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx335_init_controls(imx335);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "failed to init controls: %d", ret);</div><div class='add'>+		dev_err(imx335-&gt;dev, "failed to init controls: %d\n", ret);</div><div class='ctx'> 		goto error_power_off;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1039,14 +1188,14 @@ static int imx335_probe(struct i2c_client *client)</div><div class='ctx'> 	imx335-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='ctx'> 	ret = media_entity_pads_init(&amp;imx335-&gt;sd.entity, 1, &amp;imx335-&gt;pad);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(imx335-&gt;dev, "failed to init entity pads: %d", ret);</div><div class='add'>+		dev_err(imx335-&gt;dev, "failed to init entity pads: %d\n", ret);</div><div class='ctx'> 		goto error_handler_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_async_register_subdev_sensor(&amp;imx335-&gt;sd);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(imx335-&gt;dev,</div><div class='del'>-			"failed to register async subdev: %d", ret);</div><div class='add'>+			"failed to register async subdev: %d\n", ret);</div><div class='ctx'> 		goto error_media_entity;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/imx355.c b/drivers/media/i2c/imx355.c<br/>index 9c58c1a80cba..8c995c58743a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx355.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx355.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx355.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx355.c</a></div><div class='hunk'>@@ -1158,7 +1158,7 @@ static int imx355_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx355 *imx355 = to_imx355(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;imx355-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1299,10 +1299,9 @@ static int imx355_do_get_pad_format(struct imx355 *imx355,</div><div class='ctx'> 				    struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *framefmt;</div><div class='del'>-	struct v4l2_subdev *sd = &amp;imx355-&gt;sd;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx355_update_pad_format(imx355, imx355-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -1353,7 +1352,7 @@ imx355_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	imx355_update_pad_format(imx355, mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx355-&gt;cur_mode = mode;</div><div class='hunk'>@@ -1748,10 +1747,6 @@ static int imx355_probe(struct i2c_client *client)</div><div class='ctx'> 		goto error_handler_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_async_register_subdev_sensor(&amp;imx355-&gt;sd);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		goto error_media_entity;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Device is already turned on by i2c-core with ACPI domain PM.</div><div class='ctx'> 	 * Enable runtime PM and turn off the device.</div><div class='hunk'>@@ -1760,9 +1755,15 @@ static int imx355_probe(struct i2c_client *client)</div><div class='ctx'> 	pm_runtime_enable(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_idle(&amp;client-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;imx355-&gt;sd);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto error_media_entity_runtime_pm;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-error_media_entity:</div><div class='add'>+error_media_entity_runtime_pm:</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> 	media_entity_cleanup(&amp;imx355-&gt;sd.entity);</div><div class='ctx'> </div><div class='ctx'> error_handler_free:</div><div class='head'>diff --git a/drivers/media/i2c/imx412.c b/drivers/media/i2c/imx412.c<br/>index 962b3136c31e..0efce329525e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx412.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx412.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx412.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx412.c</a></div><div class='hunk'>@@ -721,7 +721,7 @@ static int imx412_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		imx412_fill_pad_format(imx412, imx412-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -756,7 +756,7 @@ static int imx412_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = imx412_update_controls(imx412, mode);</div><div class='hunk'>@@ -770,14 +770,14 @@ static int imx412_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * imx412_init_pad_cfg() - Initialize sub-device pad configuration</div><div class='add'>+ * imx412_init_state() - Initialize sub-device state</div><div class='ctx'>  * @sd: pointer to imx412 V4L2 sub-device structure</div><div class='ctx'>  * @sd_state: V4L2 sub-device configuration</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 if successful, error code otherwise.</div><div class='ctx'>  */</div><div class='del'>-static int imx412_init_pad_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx412_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct imx412 *imx412 = to_imx412(sd);</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='hunk'>@@ -997,7 +997,6 @@ static const struct v4l2_subdev_video_ops imx412_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx412_pad_ops = {</div><div class='del'>-	.init_cfg = imx412_init_pad_cfg,</div><div class='ctx'> 	.enum_mbus_code = imx412_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = imx412_enum_frame_size,</div><div class='ctx'> 	.get_fmt = imx412_get_pad_format,</div><div class='hunk'>@@ -1009,6 +1008,10 @@ static const struct v4l2_subdev_ops imx412_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx412_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx412_internal_ops = {</div><div class='add'>+	.init_state = imx412_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * imx412_power_on() - Sensor power on sequence</div><div class='ctx'>  * @dev: pointer to i2c device</div><div class='hunk'>@@ -1177,6 +1180,7 @@ static int imx412_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;imx412-&gt;sd, client, &amp;imx412_subdev_ops);</div><div class='add'>+	imx412-&gt;sd.internal_ops = &amp;imx412_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx412_parse_hw_config(imx412);</div><div class='ctx'> 	if (ret) {</div><div class='head'>diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c<br/>index b3fa71a16839..1e5f20c3ed82 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx415.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/imx415.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/imx415.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/imx415.c</a></div><div class='hunk'>@@ -546,7 +546,7 @@ static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;sensor-&gt;subdev);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;subdev, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	switch (ctrl-&gt;id) {</div><div class='ctx'> 	case V4L2_CID_EXPOSURE:</div><div class='hunk'>@@ -828,7 +828,7 @@ static int imx415_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fse-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fse-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fse-&gt;index &gt; 0 || fse-&gt;code != format-&gt;code)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -846,7 +846,7 @@ static int imx415_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fmt-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	format-&gt;width = fmt-&gt;format.width;</div><div class='ctx'> 	format-&gt;height = fmt-&gt;format.height;</div><div class='hunk'>@@ -880,8 +880,8 @@ static int imx415_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx415_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int imx415_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format format = {</div><div class='ctx'> 		.format = {</div><div class='hunk'>@@ -905,7 +905,6 @@ static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = {</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = imx415_set_format,</div><div class='ctx'> 	.get_selection = imx415_get_selection,</div><div class='del'>-	.init_cfg = imx415_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops imx415_subdev_ops = {</div><div class='hunk'>@@ -913,12 +912,17 @@ static const struct v4l2_subdev_ops imx415_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;imx415_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx415_internal_ops = {</div><div class='add'>+	.init_state = imx415_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int imx415_subdev_init(struct imx415 *sensor)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = to_i2c_client(sensor-&gt;dev);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;sensor-&gt;subdev, client, &amp;imx415_subdev_ops);</div><div class='add'>+	sensor-&gt;subdev.internal_ops = &amp;imx415_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = imx415_ctrls_init(sensor);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/i2c/isl7998x.c b/drivers/media/i2c/isl7998x.c<br/>index 73460688c356..89e13ebbce0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/isl7998x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/isl7998x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/isl7998x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/isl7998x.c</a></div><div class='hunk'>@@ -1007,8 +1007,8 @@ static int isl7998x_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;isl7998x-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							     format-&gt;pad);</div><div class='add'>+		format-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							       format-&gt;pad);</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1044,7 +1044,7 @@ static int isl7998x_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mf-&gt;field = mode-&gt;field;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad) = format-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, format-&gt;pad) = format-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;isl7998x-&gt;lock);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c<br/>index fc1cf196ef01..d685d445cf23 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/max9286.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/max9286.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/max9286.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/max9286.c</a></div><div class='hunk'>@@ -868,11 +868,19 @@ static int max9286_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int max9286_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+static int max9286_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *interval)</div><div class='ctx'> {</div><div class='ctx'> 	struct max9286_priv *priv = sd_to_max9286(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (interval-&gt;pad != MAX9286_SRC_PAD)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -881,11 +889,19 @@ static int max9286_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int max9286_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+static int max9286_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *interval)</div><div class='ctx'> {</div><div class='ctx'> 	struct max9286_priv *priv = sd_to_max9286(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (interval-&gt;pad != MAX9286_SRC_PAD)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -913,7 +929,7 @@ max9286_get_pad_format(struct max9286_priv *priv,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;priv-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;priv-&gt;fmt[pad];</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -983,14 +999,14 @@ static int max9286_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops max9286_video_ops = {</div><div class='ctx'> 	.s_stream	= max9286_s_stream,</div><div class='del'>-	.g_frame_interval = max9286_g_frame_interval,</div><div class='del'>-	.s_frame_interval = max9286_s_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops max9286_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = max9286_enum_mbus_code,</div><div class='ctx'> 	.get_fmt	= max9286_get_fmt,</div><div class='ctx'> 	.set_fmt	= max9286_set_fmt,</div><div class='add'>+	.get_frame_interval = max9286_get_frame_interval,</div><div class='add'>+	.set_frame_interval = max9286_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops max9286_subdev_ops = {</div><div class='hunk'>@@ -1020,7 +1036,7 @@ static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MAX9286_N_SINKS; i++) {</div><div class='del'>-		format = v4l2_subdev_get_try_format(subdev, fh-&gt;state, i);</div><div class='add'>+		format = v4l2_subdev_state_get_format(fh-&gt;state, i);</div><div class='ctx'> 		max9286_init_format(format);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/mt9m001.c b/drivers/media/i2c/mt9m001.c<br/>index 79192cf79d28..ad1a3ab77411 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m001.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9m001.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m001.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m001.c</a></div><div class='hunk'>@@ -325,7 +325,7 @@ static int mt9m001_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		format-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -405,7 +405,7 @@ static int mt9m001_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return mt9m001_s_fmt(sd, fmt, mf);</div><div class='del'>-	sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='add'>+	*v4l2_subdev_state_get_format(sd_state, 0) = *mf;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -650,13 +650,13 @@ static const struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int mt9m001_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mt9m001_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='ctx'> 	struct mt9m001 *mt9m001 = to_mt9m001(client);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	try_fmt-&gt;width		= MT9M001_MAX_WIDTH;</div><div class='ctx'> 	try_fmt-&gt;height		= MT9M001_MAX_HEIGHT;</div><div class='hunk'>@@ -708,7 +708,6 @@ static const struct v4l2_subdev_sensor_ops mt9m001_subdev_sensor_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9m001_subdev_pad_ops = {</div><div class='del'>-	.init_cfg	= mt9m001_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mt9m001_enum_mbus_code,</div><div class='ctx'> 	.get_selection	= mt9m001_get_selection,</div><div class='ctx'> 	.set_selection	= mt9m001_set_selection,</div><div class='hunk'>@@ -724,6 +723,10 @@ static const struct v4l2_subdev_ops mt9m001_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;mt9m001_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mt9m001_internal_ops = {</div><div class='add'>+	.init_state	= mt9m001_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int mt9m001_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9m001 *mt9m001;</div><div class='hunk'>@@ -755,6 +758,7 @@ static int mt9m001_probe(struct i2c_client *client)</div><div class='ctx'> 		return PTR_ERR(mt9m001-&gt;reset_gpio);</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;mt9m001-&gt;subdev, client, &amp;mt9m001_subdev_ops);</div><div class='add'>+	mt9m001-&gt;subdev.internal_ops = &amp;mt9m001_internal_ops;</div><div class='ctx'> 	mt9m001-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 				 V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	v4l2_ctrl_handler_init(&amp;mt9m001-&gt;hdl, 4);</div><div class='head'>diff --git a/drivers/media/i2c/mt9m111.c b/drivers/media/i2c/mt9m111.c<br/>index 1f44b72e8a70..ceeeb94c38d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m111.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9m111.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m111.c</a></div><div class='hunk'>@@ -525,7 +525,7 @@ static int mt9m111_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		format-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -671,7 +671,7 @@ static int mt9m111_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mf-&gt;xfer_func	= V4L2_XFER_FUNC_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1045,18 +1045,27 @@ static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int mt9m111_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int mt9m111_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	fi-&gt;interval = mt9m111-&gt;frame_interval;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m111_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int mt9m111_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);</div><div class='ctx'> 	const struct mt9m111_mode_info *mode;</div><div class='hunk'>@@ -1066,6 +1075,13 @@ static int mt9m111_s_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (mt9m111-&gt;is_streaming)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (fi-&gt;pad != 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1111,11 +1127,11 @@ static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m111_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mt9m111_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	format-&gt;width	= MT9M111_MAX_WIDTH;</div><div class='ctx'> 	format-&gt;height	= MT9M111_MAX_HEIGHT;</div><div class='hunk'>@@ -1151,17 +1167,16 @@ static int mt9m111_get_mbus_config(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {</div><div class='ctx'> 	.s_stream	= mt9m111_s_stream,</div><div class='del'>-	.g_frame_interval = mt9m111_g_frame_interval,</div><div class='del'>-	.s_frame_interval = mt9m111_s_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = {</div><div class='del'>-	.init_cfg	= mt9m111_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mt9m111_enum_mbus_code,</div><div class='ctx'> 	.get_selection	= mt9m111_get_selection,</div><div class='ctx'> 	.set_selection	= mt9m111_set_selection,</div><div class='ctx'> 	.get_fmt	= mt9m111_get_fmt,</div><div class='ctx'> 	.set_fmt	= mt9m111_set_fmt,</div><div class='add'>+	.get_frame_interval = mt9m111_get_frame_interval,</div><div class='add'>+	.set_frame_interval = mt9m111_set_frame_interval,</div><div class='ctx'> 	.get_mbus_config = mt9m111_get_mbus_config,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1171,6 +1186,10 @@ static const struct v4l2_subdev_ops mt9m111_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;mt9m111_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mt9m111_internal_ops = {</div><div class='add'>+	.init_state	= mt9m111_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Interface active, can use i2c. If it fails, it can indeed mean, that</div><div class='ctx'>  * this wasn't our capture interface, so, we wait for the right one</div><div class='hunk'>@@ -1275,6 +1294,7 @@ static int mt9m111_probe(struct i2c_client *client)</div><div class='ctx'> 	mt9m111-&gt;ctx = &amp;context_b;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;mt9m111-&gt;subdev, client, &amp;mt9m111_subdev_ops);</div><div class='add'>+	mt9m111-&gt;subdev.internal_ops = &amp;mt9m111_internal_ops;</div><div class='ctx'> 	mt9m111-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 				 V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/mt9m114.c b/drivers/media/i2c/mt9m114.c<br/>index ac19078ceda3..5f0b0ad8f885 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m114.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9m114.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9m114.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9m114.c</a></div><div class='hunk'>@@ -796,13 +796,13 @@ static int mt9m114_configure(struct mt9m114 *sensor,</div><div class='ctx'> 	u64 read_mode;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	pa_format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;pa.sd, pa_state, 0);</div><div class='del'>-	pa_crop = v4l2_subdev_get_pad_crop(&amp;sensor-&gt;pa.sd, pa_state, 0);</div><div class='add'>+	pa_format = v4l2_subdev_state_get_format(pa_state, 0);</div><div class='add'>+	pa_crop = v4l2_subdev_state_get_crop(pa_state, 0);</div><div class='ctx'> </div><div class='del'>-	ifp_format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;ifp.sd, ifp_state, 1);</div><div class='add'>+	ifp_format = v4l2_subdev_state_get_format(ifp_state, 1);</div><div class='ctx'> 	ifp_info = mt9m114_format_info(sensor, 1, ifp_format-&gt;code);</div><div class='del'>-	ifp_crop = v4l2_subdev_get_pad_crop(&amp;sensor-&gt;ifp.sd, ifp_state, 0);</div><div class='del'>-	ifp_compose = v4l2_subdev_get_pad_compose(&amp;sensor-&gt;ifp.sd, ifp_state, 0);</div><div class='add'>+	ifp_crop = v4l2_subdev_state_get_crop(ifp_state, 0);</div><div class='add'>+	ifp_compose = v4l2_subdev_state_get_compose(ifp_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	ret = cci_read(sensor-&gt;regmap, MT9M114_CAM_SENSOR_CONTROL_READ_MODE,</div><div class='ctx'> 		       &amp;read_mode, NULL);</div><div class='hunk'>@@ -1045,7 +1045,7 @@ static int mt9m114_pa_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;sensor-&gt;pa.sd);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;sensor-&gt;pa.sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	switch (ctrl-&gt;id) {</div><div class='ctx'> 	case V4L2_CID_HBLANK:</div><div class='hunk'>@@ -1152,20 +1152,20 @@ static inline struct mt9m114 *pa_to_mt9m114(struct v4l2_subdev *sd)</div><div class='ctx'> 	return container_of(sd, struct mt9m114, pa.sd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m114_pa_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *state)</div><div class='add'>+static int mt9m114_pa_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	crop-&gt;left = 0;</div><div class='ctx'> 	crop-&gt;top = 0;</div><div class='ctx'> 	crop-&gt;width = MT9M114_PIXEL_ARRAY_WIDTH;</div><div class='ctx'> 	crop-&gt;height = MT9M114_PIXEL_ARRAY_HEIGHT;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	format-&gt;width = MT9M114_PIXEL_ARRAY_WIDTH;</div><div class='ctx'> 	format-&gt;height = MT9M114_PIXEL_ARRAY_HEIGHT;</div><div class='hunk'>@@ -1220,8 +1220,8 @@ static int mt9m114_pa_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	unsigned int hscale;</div><div class='ctx'> 	unsigned int vscale;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, fmt-&gt;pad);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fmt-&gt;pad);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, fmt-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	/* The sensor can bin horizontally and vertically. */</div><div class='ctx'> 	hscale = DIV_ROUND_CLOSEST(crop-&gt;width, fmt-&gt;format.width ? : 1);</div><div class='hunk'>@@ -1243,7 +1243,7 @@ static int mt9m114_pa_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, state, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(state, sel-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='hunk'>@@ -1271,8 +1271,8 @@ static int mt9m114_pa_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (sel-&gt;target != V4L2_SEL_TGT_CROP)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, sel-&gt;pad);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, sel-&gt;pad);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, sel-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, sel-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Clamp the crop rectangle. The vertical coordinates must be even, and</div><div class='hunk'>@@ -1304,7 +1304,6 @@ static int mt9m114_pa_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9m114_pa_pad_ops = {</div><div class='del'>-	.init_cfg = mt9m114_pa_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mt9m114_pa_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = mt9m114_pa_enum_framesizes,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -1317,6 +1316,10 @@ static const struct v4l2_subdev_ops mt9m114_pa_ops = {</div><div class='ctx'> 	.pad = &amp;mt9m114_pa_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mt9m114_pa_internal_ops = {</div><div class='add'>+	.init_state = mt9m114_pa_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int mt9m114_pa_init(struct mt9m114 *sensor)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_ctrl_handler *hdl = &amp;sensor-&gt;pa.hdl;</div><div class='hunk'>@@ -1329,6 +1332,7 @@ static int mt9m114_pa_init(struct mt9m114 *sensor)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize the subdev. */</div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;mt9m114_pa_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;mt9m114_pa_internal_ops;</div><div class='ctx'> 	v4l2_i2c_subdev_set_name(sd, sensor-&gt;client, NULL, " pixel array");</div><div class='ctx'> </div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='hunk'>@@ -1402,7 +1406,7 @@ static int mt9m114_pa_init(struct mt9m114 *sensor)</div><div class='ctx'> </div><div class='ctx'> 	/* Update the range of the blanking controls based on the format. */</div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	mt9m114_pa_ctrl_update_blanking(sensor, format);</div><div class='ctx'> 	v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='hunk'>@@ -1581,12 +1585,20 @@ static int mt9m114_ifp_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m114_ifp_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-					struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+static int mt9m114_ifp_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+					  struct v4l2_subdev_state *sd_state,</div><div class='add'>+					  struct v4l2_subdev_frame_interval *interval)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fract *ival = &amp;interval-&gt;interval;</div><div class='ctx'> 	struct mt9m114 *sensor = ifp_to_mt9m114(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(sensor-&gt;ifp.hdl.lock);</div><div class='ctx'> </div><div class='ctx'> 	ival-&gt;numerator = 1;</div><div class='hunk'>@@ -1597,13 +1609,21 @@ static int mt9m114_ifp_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m114_ifp_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-					struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+static int mt9m114_ifp_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+					  struct v4l2_subdev_state *sd_state,</div><div class='add'>+					  struct v4l2_subdev_frame_interval *interval)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fract *ival = &amp;interval-&gt;interval;</div><div class='ctx'> 	struct mt9m114 *sensor = ifp_to_mt9m114(sd);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(sensor-&gt;ifp.hdl.lock);</div><div class='ctx'> </div><div class='ctx'> 	if (ival-&gt;numerator != 0 &amp;&amp; ival-&gt;denominator != 0)</div><div class='hunk'>@@ -1624,15 +1644,15 @@ static int mt9m114_ifp_s_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9m114_ifp_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				struct v4l2_subdev_state *state)</div><div class='add'>+static int mt9m114_ifp_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9m114 *sensor = ifp_to_mt9m114(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> 	struct v4l2_rect *compose;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	format-&gt;width = MT9M114_PIXEL_ARRAY_WIDTH;</div><div class='ctx'> 	format-&gt;height = MT9M114_PIXEL_ARRAY_HEIGHT;</div><div class='hunk'>@@ -1643,21 +1663,21 @@ static int mt9m114_ifp_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> 	format-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='ctx'> 	format-&gt;xfer_func = V4L2_XFER_FUNC_NONE;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	crop-&gt;left = 4;</div><div class='ctx'> 	crop-&gt;top = 4;</div><div class='ctx'> 	crop-&gt;width = format-&gt;width - 8;</div><div class='ctx'> 	crop-&gt;height = format-&gt;height - 8;</div><div class='ctx'> </div><div class='del'>-	compose = v4l2_subdev_get_pad_compose(sd, state, 0);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	compose-&gt;left = 0;</div><div class='ctx'> 	compose-&gt;top = 0;</div><div class='ctx'> 	compose-&gt;width = crop-&gt;width;</div><div class='ctx'> 	compose-&gt;height = crop-&gt;height;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 1);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 1);</div><div class='ctx'> </div><div class='ctx'> 	format-&gt;width = compose-&gt;width;</div><div class='ctx'> 	format-&gt;height = compose-&gt;height;</div><div class='hunk'>@@ -1738,7 +1758,7 @@ static int mt9m114_ifp_enum_framesizes(struct v4l2_subdev *sd,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		const struct v4l2_rect *crop;</div><div class='ctx'> </div><div class='del'>-		crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+		crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 		fse-&gt;max_width = crop-&gt;width;</div><div class='ctx'> 		fse-&gt;max_height = crop-&gt;height;</div><div class='hunk'>@@ -1777,7 +1797,7 @@ static int mt9m114_ifp_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct mt9m114 *sensor = ifp_to_mt9m114(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, fmt-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == 0) {</div><div class='ctx'> 		/* Only the size can be changed on the sink pad. */</div><div class='hunk'>@@ -1797,7 +1817,7 @@ static int mt9m114_ifp_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 		/* If the output format is RAW10, bypass the scaler. */</div><div class='ctx'> 		if (format-&gt;code == MEDIA_BUS_FMT_SGRBG10_1X10)</div><div class='del'>-			*format = *v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+			*format = *v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	fmt-&gt;format = *format;</div><div class='hunk'>@@ -1819,7 +1839,7 @@ static int mt9m114_ifp_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='hunk'>@@ -1828,7 +1848,7 @@ static int mt9m114_ifp_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		 * The crop default and bounds are equal to the sink</div><div class='ctx'> 		 * format size minus 4 pixels on each side for demosaicing.</div><div class='ctx'> 		 */</div><div class='del'>-		format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='add'>+		format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 		sel-&gt;r.left = 4;</div><div class='ctx'> 		sel-&gt;r.top = 4;</div><div class='hunk'>@@ -1837,7 +1857,7 @@ static int mt9m114_ifp_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_compose(sd, state, 0);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_compose(state, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE_DEFAULT:</div><div class='hunk'>@@ -1846,7 +1866,7 @@ static int mt9m114_ifp_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		 * The compose default and bounds sizes are equal to the sink</div><div class='ctx'> 		 * crop rectangle size.</div><div class='ctx'> 		 */</div><div class='del'>-		crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='add'>+		crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='ctx'> 		sel-&gt;r.top = 0;</div><div class='ctx'> 		sel-&gt;r.width = crop-&gt;width;</div><div class='hunk'>@@ -1877,9 +1897,9 @@ static int mt9m114_ifp_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (sel-&gt;pad != 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 0);</div><div class='del'>-	crop = v4l2_subdev_get_pad_crop(sd, state, 0);</div><div class='del'>-	compose = v4l2_subdev_get_pad_compose(sd, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;target == V4L2_SEL_TGT_CROP) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -1921,7 +1941,7 @@ static int mt9m114_ifp_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the compose rectangle to the source format. */</div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, 1);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 1);</div><div class='ctx'> 	format-&gt;width = compose-&gt;width;</div><div class='ctx'> 	format-&gt;height = compose-&gt;height;</div><div class='ctx'> </div><div class='hunk'>@@ -1963,12 +1983,9 @@ static int mt9m114_ifp_registered(struct v4l2_subdev *sd)</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops mt9m114_ifp_video_ops = {</div><div class='ctx'> 	.s_stream = mt9m114_ifp_s_stream,</div><div class='del'>-	.g_frame_interval = mt9m114_ifp_g_frame_interval,</div><div class='del'>-	.s_frame_interval = mt9m114_ifp_s_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9m114_ifp_pad_ops = {</div><div class='del'>-	.init_cfg = mt9m114_ifp_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mt9m114_ifp_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = mt9m114_ifp_enum_framesizes,</div><div class='ctx'> 	.enum_frame_interval = mt9m114_ifp_enum_frameintervals,</div><div class='hunk'>@@ -1976,6 +1993,8 @@ static const struct v4l2_subdev_pad_ops mt9m114_ifp_pad_ops = {</div><div class='ctx'> 	.set_fmt = mt9m114_ifp_set_fmt,</div><div class='ctx'> 	.get_selection = mt9m114_ifp_get_selection,</div><div class='ctx'> 	.set_selection = mt9m114_ifp_set_selection,</div><div class='add'>+	.get_frame_interval = mt9m114_ifp_get_frame_interval,</div><div class='add'>+	.set_frame_interval = mt9m114_ifp_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops mt9m114_ifp_ops = {</div><div class='hunk'>@@ -1984,6 +2003,7 @@ static const struct v4l2_subdev_ops mt9m114_ifp_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_internal_ops mt9m114_ifp_internal_ops = {</div><div class='add'>+	.init_state = mt9m114_ifp_init_state,</div><div class='ctx'> 	.registered = mt9m114_ifp_registered,</div><div class='ctx'> 	.unregistered = mt9m114_ifp_unregistered,</div><div class='ctx'> };</div><div class='hunk'>@@ -2112,7 +2132,7 @@ static int mt9m114_power_on(struct mt9m114 *sensor)</div><div class='ctx'> 		duration = DIV_ROUND_UP(2 * 50 * 1000000, freq);</div><div class='ctx'> </div><div class='ctx'> 		gpiod_set_value(sensor-&gt;reset, 1);</div><div class='del'>-		udelay(duration);</div><div class='add'>+		fsleep(duration);</div><div class='ctx'> 		gpiod_set_value(sensor-&gt;reset, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/*</div><div class='head'>diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c<br/>index 348f1e1098fb..596200d0248c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9p031.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9p031.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9p031.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9p031.c</a></div><div class='hunk'>@@ -549,8 +549,7 @@ __mt9p031_get_pad_format(struct mt9p031 *mt9p031,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;mt9p031-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;mt9p031-&gt;format;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -565,8 +564,7 @@ __mt9p031_get_pad_crop(struct mt9p031 *mt9p031,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;mt9p031-&gt;subdev, sd_state,</div><div class='del'>-						pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;mt9p031-&gt;crop;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -698,8 +696,8 @@ static int mt9p031_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9p031_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mt9p031_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9p031 *mt9p031 = to_mt9p031(subdev);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='hunk'>@@ -1043,7 +1041,6 @@ static const struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {</div><div class='del'>-	.init_cfg = mt9p031_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mt9p031_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = mt9p031_enum_frame_size,</div><div class='ctx'> 	.get_fmt = mt9p031_get_format,</div><div class='hunk'>@@ -1059,6 +1056,7 @@ static const struct v4l2_subdev_ops mt9p031_subdev_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {</div><div class='add'>+	.init_state = mt9p031_init_state,</div><div class='ctx'> 	.registered = mt9p031_registered,</div><div class='ctx'> 	.open = mt9p031_open,</div><div class='ctx'> 	.close = mt9p031_close,</div><div class='hunk'>@@ -1191,7 +1189,7 @@ static int mt9p031_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	mt9p031-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> </div><div class='del'>-	ret = mt9p031_init_cfg(&amp;mt9p031-&gt;subdev, NULL);</div><div class='add'>+	ret = mt9p031_init_state(&amp;mt9p031-&gt;subdev, NULL);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/mt9t112.c b/drivers/media/i2c/mt9t112.c<br/>index 93f34b767027..fb1588c57cc8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9t112.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9t112.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9t112.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9t112.c</a></div><div class='hunk'>@@ -982,7 +982,6 @@ static int mt9t112_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return mt9t112_s_fmt(sd, mf);</div><div class='del'>-	sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/i2c/mt9v011.c b/drivers/media/i2c/mt9v011.c<br/>index 37a634b92cd5..8834ff8786e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v011.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9v011.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v011.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v011.c</a></div><div class='hunk'>@@ -356,15 +356,23 @@ static int mt9v011_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 		set_res(sd);</div><div class='ctx'> 	} else {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *fmt;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *fmt;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9v011_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int mt9v011_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	calc_fps(sd,</div><div class='ctx'> 		 &amp;ival-&gt;interval.numerator,</div><div class='ctx'> 		 &amp;ival-&gt;interval.denominator);</div><div class='hunk'>@@ -372,12 +380,20 @@ static int mt9v011_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9v011_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int mt9v011_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> 	u16 speed;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	speed = calc_speed(sd, tpf-&gt;numerator, tpf-&gt;denominator);</div><div class='ctx'> </div><div class='ctx'> 	mt9v011_write(sd, R0A_MT9V011_CLK_SPEED, speed);</div><div class='hunk'>@@ -455,19 +471,15 @@ static const struct v4l2_subdev_core_ops mt9v011_core_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct v4l2_subdev_video_ops mt9v011_video_ops = {</div><div class='del'>-	.g_frame_interval = mt9v011_g_frame_interval,</div><div class='del'>-	.s_frame_interval = mt9v011_s_frame_interval,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9v011_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = mt9v011_enum_mbus_code,</div><div class='ctx'> 	.set_fmt = mt9v011_set_fmt,</div><div class='add'>+	.get_frame_interval = mt9v011_get_frame_interval,</div><div class='add'>+	.set_frame_interval = mt9v011_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops mt9v011_ops = {</div><div class='ctx'> 	.core  = &amp;mt9v011_core_ops,</div><div class='del'>-	.video = &amp;mt9v011_video_ops,</div><div class='ctx'> 	.pad   = &amp;mt9v011_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/mt9v032.c b/drivers/media/i2c/mt9v032.c<br/>index 1c6f6cea1204..3ca76eeae7ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v032.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9v032.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v032.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v032.c</a></div><div class='hunk'>@@ -356,8 +356,7 @@ __mt9v032_get_pad_format(struct mt9v032 *mt9v032,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;mt9v032-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;mt9v032-&gt;format;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -372,8 +371,7 @@ __mt9v032_get_pad_crop(struct mt9v032 *mt9v032,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;mt9v032-&gt;subdev, sd_state,</div><div class='del'>-						pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;mt9v032-&gt;crop;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -931,13 +929,13 @@ static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> </div><div class='del'>-	crop = v4l2_subdev_get_try_crop(subdev, fh-&gt;state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(fh-&gt;state, 0);</div><div class='ctx'> 	crop-&gt;left = MT9V032_COLUMN_START_DEF;</div><div class='ctx'> 	crop-&gt;top = MT9V032_ROW_START_DEF;</div><div class='ctx'> 	crop-&gt;width = MT9V032_WINDOW_WIDTH_DEF;</div><div class='ctx'> 	crop-&gt;height = MT9V032_WINDOW_HEIGHT_DEF;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(subdev, fh-&gt;state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (mt9v032-&gt;model-&gt;color)</div><div class='ctx'> 		format-&gt;code = MEDIA_BUS_FMT_SGRBG10_1X10;</div><div class='head'>diff --git a/drivers/media/i2c/mt9v111.c b/drivers/media/i2c/mt9v111.c<br/>index f859b49e13bf..b0b98ed3c150 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v111.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/mt9v111.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/mt9v111.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/mt9v111.c</a></div><div class='hunk'>@@ -35,7 +35,7 @@</div><div class='ctx'>  * The IFP can produce several output image formats from the sensor core</div><div class='ctx'>  * output. This driver currently supports only YUYV format permutations.</div><div class='ctx'>  *</div><div class='del'>- * The driver allows manual frame rate control through s_frame_interval subdev</div><div class='add'>+ * The driver allows manual frame rate control through set_frame_interval subdev</div><div class='ctx'>  * operation or V4L2_CID_V/HBLANK controls, but it is known that the</div><div class='ctx'>  * auto-exposure algorithm might modify the programmed frame rate. While the</div><div class='ctx'>  * driver initially programs the sensor with auto-exposure and</div><div class='hunk'>@@ -719,8 +719,9 @@ error_unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9v111_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int mt9v111_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='hunk'>@@ -729,6 +730,13 @@ static int mt9v111_s_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 			   tpf-&gt;denominator;</div><div class='ctx'> 	unsigned int max_fps;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (!tpf-&gt;numerator)</div><div class='ctx'> 		tpf-&gt;numerator = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -771,12 +779,20 @@ static int mt9v111_s_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9v111_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int mt9v111_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;mt9v111-&gt;stream_mutex);</div><div class='ctx'> </div><div class='ctx'> 	tpf-&gt;numerator = 1;</div><div class='hunk'>@@ -795,7 +811,7 @@ static struct v4l2_mbus_framefmt *__mt9v111_get_pad_format(</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;mt9v111-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;mt9v111-&gt;fmt;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -948,10 +964,10 @@ done:</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mt9v111_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mt9v111_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='del'>-	sd_state-&gt;pads-&gt;try_fmt = mt9v111_def_fmt;</div><div class='add'>+	*v4l2_subdev_state_get_format(sd_state, 0) = mt9v111_def_fmt;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -962,17 +978,16 @@ static const struct v4l2_subdev_core_ops mt9v111_core_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops mt9v111_video_ops = {</div><div class='ctx'> 	.s_stream		= mt9v111_s_stream,</div><div class='del'>-	.s_frame_interval	= mt9v111_s_frame_interval,</div><div class='del'>-	.g_frame_interval	= mt9v111_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mt9v111_pad_ops = {</div><div class='del'>-	.init_cfg		= mt9v111_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= mt9v111_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size	= mt9v111_enum_frame_size,</div><div class='ctx'> 	.enum_frame_interval	= mt9v111_enum_frame_interval,</div><div class='ctx'> 	.get_fmt		= mt9v111_get_format,</div><div class='ctx'> 	.set_fmt		= mt9v111_set_format,</div><div class='add'>+	.get_frame_interval	= mt9v111_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= mt9v111_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops mt9v111_ops = {</div><div class='hunk'>@@ -981,6 +996,10 @@ static const struct v4l2_subdev_ops mt9v111_ops = {</div><div class='ctx'> 	.pad	= &amp;mt9v111_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mt9v111_internal_ops = {</div><div class='add'>+	.init_state		= mt9v111_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations mt9v111_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -1194,6 +1213,7 @@ static int mt9v111_probe(struct i2c_client *client)</div><div class='ctx'> 	mt9v111-&gt;pending	= true;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;mt9v111-&gt;sd, client, &amp;mt9v111_ops);</div><div class='add'>+	mt9v111-&gt;sd.internal_ops = &amp;mt9v111_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	mt9v111-&gt;sd.flags	|= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	mt9v111-&gt;sd.entity.ops	= &amp;mt9v111_subdev_entity_ops;</div><div class='head'>diff --git a/drivers/media/i2c/og01a1b.c b/drivers/media/i2c/og01a1b.c<br/>index 51378ba16a5d..bac9597faf68 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/og01a1b.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/og01a1b.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/og01a1b.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/og01a1b.c</a></div><div class='hunk'>@@ -769,8 +769,7 @@ static int og01a1b_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;og01a1b-&gt;mutex);</div><div class='ctx'> 	og01a1b_update_pad_format(mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-					    fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		og01a1b-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(og01a1b-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -803,9 +802,8 @@ static int og01a1b_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;og01a1b-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;og01a1b-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		og01a1b_update_pad_format(og01a1b-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -850,7 +848,7 @@ static int og01a1b_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;og01a1b-&gt;mutex);</div><div class='ctx'> 	og01a1b_update_pad_format(&amp;supported_modes[0],</div><div class='del'>-				  v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				  v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;og01a1b-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/ov01a10.c b/drivers/media/i2c/ov01a10.c<br/>index bbd5740d2280..5606437f37d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov01a10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov01a10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov01a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov01a10.c</a></div><div class='hunk'>@@ -723,14 +723,14 @@ static int ov01a10_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 					 h_blank);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, sd_state, fmt-&gt;stream);</div><div class='add'>+	format = v4l2_subdev_state_get_format(sd_state, fmt-&gt;stream);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov01a10_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *state)</div><div class='add'>+static int ov01a10_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='hunk'>@@ -813,7 +813,6 @@ static const struct v4l2_subdev_video_ops ov01a10_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov01a10_pad_ops = {</div><div class='del'>-	.init_cfg = ov01a10_init_cfg,</div><div class='ctx'> 	.set_fmt = ov01a10_set_format,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.get_selection = ov01a10_get_selection,</div><div class='hunk'>@@ -827,6 +826,10 @@ static const struct v4l2_subdev_ops ov01a10_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov01a10_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov01a10_internal_ops = {</div><div class='add'>+	.init_state = ov01a10_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ov01a10_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -859,6 +862,7 @@ static void ov01a10_remove(struct i2c_client *client)</div><div class='ctx'> 	v4l2_ctrl_handler_free(sd-&gt;ctrl_handler);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ov01a10_probe(struct i2c_client *client)</div><div class='hunk'>@@ -872,6 +876,7 @@ static int ov01a10_probe(struct i2c_client *client)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov01a10-&gt;sd, client, &amp;ov01a10_subdev_ops);</div><div class='add'>+	ov01a10-&gt;sd.internal_ops = &amp;ov01a10_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = ov01a10_identify_module(ov01a10);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -905,17 +910,26 @@ static int ov01a10_probe(struct i2c_client *client)</div><div class='ctx'> 		goto err_media_entity_cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Device is already turned on by i2c-core with ACPI domain PM.</div><div class='add'>+	 * Enable runtime PM and turn off the device.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_set_active(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+	pm_runtime_idle(dev);</div><div class='add'>+</div><div class='ctx'> 	ret = v4l2_async_register_subdev_sensor(&amp;ov01a10-&gt;sd);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='ctx'> 		dev_err(dev, "Failed to register subdev: %d\n", ret);</div><div class='del'>-		goto err_media_entity_cleanup;</div><div class='add'>+		goto err_pm_disable;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pm_runtime_enable(dev);</div><div class='del'>-	pm_runtime_idle(dev);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+err_pm_disable:</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='ctx'> err_media_entity_cleanup:</div><div class='ctx'> 	media_entity_cleanup(&amp;ov01a10-&gt;sd.entity);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c<br/>index 848e47a464ac..6c30e1a0d814 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov02a10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov02a10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov02a10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov02a10.c</a></div><div class='hunk'>@@ -315,7 +315,7 @@ static int ov02a10_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	ov02a10_fill_fmt(ov02a10-&gt;cur_mode, mbus_fmt);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		frame_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		frame_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		frame_fmt = &amp;ov02a10-&gt;fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -336,8 +336,8 @@ static int ov02a10_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov02a10-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		fmt-&gt;format = ov02a10-&gt;fmt;</div><div class='ctx'> 		mbus_fmt-&gt;code = ov02a10-&gt;fmt.code;</div><div class='hunk'>@@ -511,8 +511,8 @@ static int __ov02a10_stop_stream(struct ov02a10 *ov02a10)</div><div class='ctx'> 					 SC_CTRL_MODE_STANDBY);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov02a10_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='hunk'>@@ -709,7 +709,6 @@ static const struct v4l2_subdev_video_ops ov02a10_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = {</div><div class='del'>-	.init_cfg = ov02a10_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov02a10_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov02a10_enum_frame_sizes,</div><div class='ctx'> 	.get_fmt = ov02a10_get_fmt,</div><div class='hunk'>@@ -721,6 +720,10 @@ static const struct v4l2_subdev_ops ov02a10_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;ov02a10_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov02a10_internal_ops = {</div><div class='add'>+	.init_state = ov02a10_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ov02a10_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -869,6 +872,7 @@ static int ov02a10_probe(struct i2c_client *client)</div><div class='ctx'> 				     "failed to check HW configuration\n");</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov02a10-&gt;subdev, client, &amp;ov02a10_subdev_ops);</div><div class='add'>+	ov02a10-&gt;subdev.internal_ops = &amp;ov02a10_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ov02a10-&gt;mipi_clock_voltage = OV02A10_MIPI_TX_SPEED_DEFAULT;</div><div class='ctx'> 	ov02a10-&gt;fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10;</div><div class='head'>diff --git a/drivers/media/i2c/ov08d10.c b/drivers/media/i2c/ov08d10.c<br/>index 3d49e3fa8e56..1bacbdfa4298 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov08d10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov08d10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov08d10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov08d10.c</a></div><div class='hunk'>@@ -1145,7 +1145,7 @@ static int ov08d10_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov08d10-&gt;mutex);</div><div class='ctx'> 	ov08d10_update_pad_format(ov08d10, mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) =</div><div class='ctx'> 								fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov08d10-&gt;cur_mode = mode;</div><div class='hunk'>@@ -1184,9 +1184,8 @@ static int ov08d10_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov08d10-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;ov08d10-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov08d10_update_pad_format(ov08d10, ov08d10-&gt;cur_mode,</div><div class='ctx'> 					  &amp;fmt-&gt;format);</div><div class='hunk'>@@ -1242,7 +1241,7 @@ static int ov08d10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov08d10-&gt;mutex);</div><div class='ctx'> 	ov08d10_update_pad_format(ov08d10, &amp;ov08d10-&gt;priv_lane-&gt;sp_modes[0],</div><div class='del'>-				  v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				  v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;ov08d10-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/ov08x40.c b/drivers/media/i2c/ov08x40.c<br/>index b41b6866a0ab..abbb0b774d43 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov08x40.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov08x40.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov08x40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov08x40.c</a></div><div class='hunk'>@@ -2536,7 +2536,7 @@ static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> 	const struct ov08x40_mode *default_mode = &amp;supported_modes[0];</div><div class='ctx'> 	struct ov08x40 *ov08x = to_ov08x40(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov08x-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -2774,10 +2774,9 @@ static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x,</div><div class='ctx'> 				     struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *framefmt;</div><div class='del'>-	struct v4l2_subdev *sd = &amp;ov08x-&gt;sd;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov08x40_update_pad_format(ov08x-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -2826,7 +2825,7 @@ ov08x40_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	ov08x40_update_pad_format(mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov08x-&gt;cur_mode = mode;</div><div class='head'>diff --git a/drivers/media/i2c/ov13858.c b/drivers/media/i2c/ov13858.c<br/>index 4c419014dd7b..09387e335d80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov13858.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov13858.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov13858.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov13858.c</a></div><div class='hunk'>@@ -1147,9 +1147,8 @@ static int ov13858_write_reg_list(struct ov13858 *ov13858,</div><div class='ctx'> static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov13858 *ov13858 = to_ov13858(sd);</div><div class='del'>-	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,</div><div class='del'>-									fh-&gt;state,</div><div class='del'>-									0);</div><div class='add'>+	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_state_get_format(fh-&gt;state,</div><div class='add'>+									  0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov13858-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1317,10 +1316,9 @@ static int ov13858_do_get_pad_format(struct ov13858 *ov13858,</div><div class='ctx'> 				     struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *framefmt;</div><div class='del'>-	struct v4l2_subdev *sd = &amp;ov13858-&gt;sd;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov13858_update_pad_format(ov13858-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -1369,7 +1367,7 @@ ov13858_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	ov13858_update_pad_format(mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov13858-&gt;cur_mode = mode;</div><div class='head'>diff --git a/drivers/media/i2c/ov13b10.c b/drivers/media/i2c/ov13b10.c<br/>index 970d2caeb3d6..73c844aa5697 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov13b10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov13b10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov13b10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov13b10.c</a></div><div class='hunk'>@@ -755,9 +755,8 @@ static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ov13b10_mode *default_mode = &amp;supported_modes[0];</div><div class='ctx'> 	struct ov13b10 *ov13b = to_ov13b10(sd);</div><div class='del'>-	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,</div><div class='del'>-									fh-&gt;state,</div><div class='del'>-									0);</div><div class='add'>+	struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_state_get_format(fh-&gt;state,</div><div class='add'>+									  0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov13b-&gt;mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -1002,10 +1001,9 @@ static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,</div><div class='ctx'> 				     struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *framefmt;</div><div class='del'>-	struct v4l2_subdev *sd = &amp;ov13b-&gt;sd;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov13b10_update_pad_format(ov13b-&gt;cur_mode, fmt);</div><div class='hunk'>@@ -1054,7 +1052,7 @@ ov13b10_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	ov13b10_update_pad_format(mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov13b-&gt;cur_mode = mode;</div><div class='hunk'>@@ -1556,24 +1554,27 @@ static int ov13b10_probe(struct i2c_client *client)</div><div class='ctx'> 		goto error_handler_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_async_register_subdev_sensor(&amp;ov13b-&gt;sd);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		goto error_media_entity;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Device is already turned on by i2c-core with ACPI domain PM.</div><div class='ctx'> 	 * Enable runtime PM and turn off the device.</div><div class='ctx'> 	 */</div><div class='del'>-</div><div class='ctx'> 	/* Set the device's state to active if it's in D0 state. */</div><div class='ctx'> 	if (full_power)</div><div class='ctx'> 		pm_runtime_set_active(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_enable(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_idle(&amp;client-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;ov13b-&gt;sd);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto error_media_entity_runtime_pm;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-error_media_entity:</div><div class='add'>+error_media_entity_runtime_pm:</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	if (full_power)</div><div class='add'>+		pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> 	media_entity_cleanup(&amp;ov13b-&gt;sd.entity);</div><div class='ctx'> </div><div class='ctx'> error_handler_free:</div><div class='hunk'>@@ -1596,6 +1597,7 @@ static void ov13b10_remove(struct i2c_client *client)</div><div class='ctx'> 	ov13b10_free_controls(ov13b);</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static DEFINE_RUNTIME_DEV_PM_OPS(ov13b10_pm_ops, ov13b10_suspend,</div><div class='head'>diff --git a/drivers/media/i2c/ov2640.c b/drivers/media/i2c/ov2640.c<br/>index 28a01c6eff64..67c4bd2916e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2640.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov2640.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2640.c</a></div><div class='hunk'>@@ -920,7 +920,7 @@ static int ov2640_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		format-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -988,7 +988,7 @@ static int ov2640_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		/* select format */</div><div class='ctx'> 		priv-&gt;cfmt_code = mf-&gt;code;</div><div class='ctx'> 	} else {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *mf;</div><div class='ctx'> 	}</div><div class='ctx'> out:</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;lock);</div><div class='hunk'>@@ -996,11 +996,11 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov2640_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov2640_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	const struct ov2640_win_size *win =</div><div class='ctx'> 		ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);</div><div class='ctx'> </div><div class='hunk'>@@ -1125,7 +1125,6 @@ static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {</div><div class='del'>-	.init_cfg	= ov2640_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov2640_enum_mbus_code,</div><div class='ctx'> 	.get_selection	= ov2640_get_selection,</div><div class='ctx'> 	.get_fmt	= ov2640_get_fmt,</div><div class='hunk'>@@ -1142,6 +1141,10 @@ static const struct v4l2_subdev_ops ov2640_subdev_ops = {</div><div class='ctx'> 	.video	= &amp;ov2640_subdev_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov2640_internal_ops = {</div><div class='add'>+	.init_state	= ov2640_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ov2640_probe_dt(struct i2c_client *client,</div><div class='ctx'> 		struct ov2640_priv *priv)</div><div class='ctx'> {</div><div class='hunk'>@@ -1211,6 +1214,7 @@ static int ov2640_probe(struct i2c_client *client)</div><div class='ctx'> 	priv-&gt;cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;priv-&gt;subdev, client, &amp;ov2640_subdev_ops);</div><div class='add'>+	priv-&gt;subdev.internal_ops = &amp;ov2640_internal_ops;</div><div class='ctx'> 	priv-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 			      V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	mutex_init(&amp;priv-&gt;lock);</div><div class='head'>diff --git a/drivers/media/i2c/ov2659.c b/drivers/media/i2c/ov2659.c<br/>index 2c3dbe164eb6..1d0ef72a6403 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2659.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov2659.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2659.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2659.c</a></div><div class='hunk'>@@ -1033,7 +1033,7 @@ static int ov2659_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		mutex_lock(&amp;ov2659-&gt;lock);</div><div class='ctx'> 		fmt-&gt;format = *mf;</div><div class='ctx'> 		mutex_unlock(&amp;ov2659-&gt;lock);</div><div class='hunk'>@@ -1109,7 +1109,7 @@ static int ov2659_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov2659-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		s64 val;</div><div class='hunk'>@@ -1304,7 +1304,7 @@ static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;client-&gt;dev, "%s:\n", __func__);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c<br/>index 72bab0ff8a36..39d321e2b7f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2680.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov2680.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2680.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2680.c</a></div><div class='hunk'>@@ -309,7 +309,7 @@ __ov2680_get_pad_format(struct ov2680_dev *sensor,</div><div class='ctx'> 			enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;sensor-&gt;sd, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;sensor-&gt;mode.fmt;</div><div class='ctx'> }</div><div class='hunk'>@@ -321,7 +321,7 @@ __ov2680_get_pad_crop(struct ov2680_dev *sensor,</div><div class='ctx'> 		      enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;sensor-&gt;sd, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;sensor-&gt;mode.crop;</div><div class='ctx'> }</div><div class='hunk'>@@ -552,11 +552,19 @@ err_disable_regulators:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov2680_s_g_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+static int ov2680_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov2680_dev *sensor = to_ov2680_dev(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> 	fi-&gt;interval = sensor-&gt;mode.frame_interval;</div><div class='ctx'> 	mutex_unlock(&amp;sensor-&gt;lock);</div><div class='hunk'>@@ -650,7 +658,7 @@ static int ov2680_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	ov2680_fill_format(sensor, &amp;format-&gt;format, width, height);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		try_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		try_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*try_fmt = format-&gt;format;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -755,14 +763,14 @@ static int ov2680_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov2680_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov2680_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov2680_dev *sensor = to_ov2680_dev(sd);</div><div class='ctx'> </div><div class='del'>-	sd_state-&gt;pads[0].try_crop = ov2680_default_crop;</div><div class='add'>+	*v4l2_subdev_state_get_crop(sd_state, 0) = ov2680_default_crop;</div><div class='ctx'> </div><div class='del'>-	ov2680_fill_format(sensor, &amp;sd_state-&gt;pads[0].try_fmt,</div><div class='add'>+	ov2680_fill_format(sensor, v4l2_subdev_state_get_format(sd_state, 0),</div><div class='ctx'> 			   OV2680_DEFAULT_WIDTH, OV2680_DEFAULT_HEIGHT);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -870,13 +878,10 @@ static const struct v4l2_ctrl_ops ov2680_ctrl_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov2680_video_ops = {</div><div class='del'>-	.g_frame_interval	= ov2680_s_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= ov2680_s_g_frame_interval,</div><div class='ctx'> 	.s_stream		= ov2680_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov2680_pad_ops = {</div><div class='del'>-	.init_cfg		= ov2680_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= ov2680_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size	= ov2680_enum_frame_size,</div><div class='ctx'> 	.enum_frame_interval	= ov2680_enum_frame_interval,</div><div class='hunk'>@@ -884,6 +889,8 @@ static const struct v4l2_subdev_pad_ops ov2680_pad_ops = {</div><div class='ctx'> 	.set_fmt		= ov2680_set_fmt,</div><div class='ctx'> 	.get_selection		= ov2680_get_selection,</div><div class='ctx'> 	.set_selection		= ov2680_set_selection,</div><div class='add'>+	.get_frame_interval	= ov2680_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= ov2680_get_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov2680_subdev_ops = {</div><div class='hunk'>@@ -891,6 +898,10 @@ static const struct v4l2_subdev_ops ov2680_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;ov2680_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov2680_internal_ops = {</div><div class='add'>+	.init_state		= ov2680_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ov2680_mode_init(struct ov2680_dev *sensor)</div><div class='ctx'> {</div><div class='ctx'> 	/* set initial mode */</div><div class='hunk'>@@ -915,6 +926,7 @@ static int ov2680_v4l2_register(struct ov2680_dev *sensor)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;sensor-&gt;sd, client, &amp;ov2680_subdev_ops);</div><div class='add'>+	sensor-&gt;sd.internal_ops = &amp;ov2680_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	sensor-&gt;sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	sensor-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='head'>diff --git a/drivers/media/i2c/ov2685.c b/drivers/media/i2c/ov2685.c<br/>index 396583826ae9..9b8481b8dcd4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2685.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov2685.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2685.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2685.c</a></div><div class='hunk'>@@ -404,7 +404,7 @@ __ov2685_get_pad_crop(struct ov2685 *ov2685,</div><div class='ctx'> </div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov2685-&gt;subdev, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return mode-&gt;analog_crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -547,7 +547,7 @@ static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov2685-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	try_fmt = v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+	try_fmt = v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> 	/* Initialize try_fmt */</div><div class='ctx'> 	ov2685_fill_fmt(&amp;supported_modes[0], try_fmt);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov2740.c b/drivers/media/i2c/ov2740.c<br/>index 24e468485fbf..552935ccb4a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2740.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov2740.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov2740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov2740.c</a></div><div class='hunk'>@@ -3,7 +3,9 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;asm/unaligned.h&gt;</div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/i2c.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='hunk'>@@ -14,6 +16,7 @@</div><div class='ctx'> #include &lt;media/v4l2-fwnode.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define OV2740_LINK_FREQ_360MHZ		360000000ULL</div><div class='add'>+#define OV2740_LINK_FREQ_180MHZ		180000000ULL</div><div class='ctx'> #define OV2740_SCLK			72000000LL</div><div class='ctx'> #define OV2740_MCLK			19200000</div><div class='ctx'> #define OV2740_DATA_LANES		2</div><div class='hunk'>@@ -28,9 +31,6 @@</div><div class='ctx'> </div><div class='ctx'> /* vertical-timings from sensor */</div><div class='ctx'> #define OV2740_REG_VTS			0x380e</div><div class='del'>-#define OV2740_VTS_DEF			0x088a</div><div class='del'>-#define OV2740_VTS_MIN			0x0460</div><div class='del'>-#define OV2740_VTS_MAX			0x7fff</div><div class='ctx'> </div><div class='ctx'> /* horizontal-timings from sensor */</div><div class='ctx'> #define OV2740_REG_HTS			0x380c</div><div class='hunk'>@@ -84,6 +84,7 @@ struct nvm_data {</div><div class='ctx'> </div><div class='ctx'> enum {</div><div class='ctx'> 	OV2740_LINK_FREQ_360MHZ_INDEX,</div><div class='add'>+	OV2740_LINK_FREQ_180MHZ_INDEX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ov2740_reg {</div><div class='hunk'>@@ -116,6 +117,9 @@ struct ov2740_mode {</div><div class='ctx'> 	/* Min vertical timining size */</div><div class='ctx'> 	u32 vts_min;</div><div class='ctx'> </div><div class='add'>+	/* Max vertical timining size */</div><div class='add'>+	u32 vts_max;</div><div class='add'>+</div><div class='ctx'> 	/* Link frequency needed for this resolution */</div><div class='ctx'> 	u32 link_freq_index;</div><div class='ctx'> </div><div class='hunk'>@@ -124,7 +128,6 @@ struct ov2740_mode {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct ov2740_reg mipi_data_rate_720mbps[] = {</div><div class='del'>-	{0x0103, 0x01},</div><div class='ctx'> 	{0x0302, 0x4b},</div><div class='ctx'> 	{0x030d, 0x4b},</div><div class='ctx'> 	{0x030e, 0x02},</div><div class='hunk'>@@ -132,7 +135,17 @@ static const struct ov2740_reg mipi_data_rate_720mbps[] = {</div><div class='ctx'> 	{0x0312, 0x11},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct ov2740_reg mode_1932x1092_regs[] = {</div><div class='add'>+static const struct ov2740_reg mipi_data_rate_360mbps[] = {</div><div class='add'>+	{0x0302, 0x4b},</div><div class='add'>+	{0x0303, 0x01},</div><div class='add'>+	{0x030d, 0x4b},</div><div class='add'>+	{0x030e, 0x02},</div><div class='add'>+	{0x030a, 0x01},</div><div class='add'>+	{0x0312, 0x11},</div><div class='add'>+	{0x4837, 0x2c},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = {</div><div class='ctx'> 	{0x3000, 0x00},</div><div class='ctx'> 	{0x3018, 0x32},</div><div class='ctx'> 	{0x3031, 0x0a},</div><div class='hunk'>@@ -285,6 +298,159 @@ static const struct ov2740_reg mode_1932x1092_regs[] = {</div><div class='ctx'> 	{0x3813, 0x01},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = {</div><div class='add'>+	{0x3000, 0x00},</div><div class='add'>+	{0x3018, 0x32},	/* 0x32 for 2 lanes, 0x12 for 1 lane */</div><div class='add'>+	{0x3031, 0x0a},</div><div class='add'>+	{0x3080, 0x08},</div><div class='add'>+	{0x3083, 0xB4},</div><div class='add'>+	{0x3103, 0x00},</div><div class='add'>+	{0x3104, 0x01},</div><div class='add'>+	{0x3106, 0x01},</div><div class='add'>+	{0x3500, 0x00},</div><div class='add'>+	{0x3501, 0x44},</div><div class='add'>+	{0x3502, 0x40},</div><div class='add'>+	{0x3503, 0x88},</div><div class='add'>+	{0x3507, 0x00},</div><div class='add'>+	{0x3508, 0x00},</div><div class='add'>+	{0x3509, 0x80},</div><div class='add'>+	{0x350c, 0x00},</div><div class='add'>+	{0x350d, 0x80},</div><div class='add'>+	{0x3510, 0x00},</div><div class='add'>+	{0x3511, 0x00},</div><div class='add'>+	{0x3512, 0x20},</div><div class='add'>+	{0x3632, 0x00},</div><div class='add'>+	{0x3633, 0x10},</div><div class='add'>+	{0x3634, 0x10},</div><div class='add'>+	{0x3635, 0x10},</div><div class='add'>+	{0x3645, 0x13},</div><div class='add'>+	{0x3646, 0x81},</div><div class='add'>+	{0x3636, 0x10},</div><div class='add'>+	{0x3651, 0x0a},</div><div class='add'>+	{0x3656, 0x02},</div><div class='add'>+	{0x3659, 0x04},</div><div class='add'>+	{0x365a, 0xda},</div><div class='add'>+	{0x365b, 0xa2},</div><div class='add'>+	{0x365c, 0x04},</div><div class='add'>+	{0x365d, 0x1d},</div><div class='add'>+	{0x365e, 0x1a},</div><div class='add'>+	{0x3662, 0xd7},</div><div class='add'>+	{0x3667, 0x78},</div><div class='add'>+	{0x3669, 0x0a},</div><div class='add'>+	{0x366a, 0x92},</div><div class='add'>+	{0x3700, 0x54},</div><div class='add'>+	{0x3702, 0x10},</div><div class='add'>+	{0x3706, 0x42},</div><div class='add'>+	{0x3709, 0x30},</div><div class='add'>+	{0x370b, 0xc2},</div><div class='add'>+	{0x3714, 0x63},</div><div class='add'>+	{0x3715, 0x01},</div><div class='add'>+	{0x3716, 0x00},</div><div class='add'>+	{0x371a, 0x3e},</div><div class='add'>+	{0x3732, 0x0e},</div><div class='add'>+	{0x3733, 0x10},</div><div class='add'>+	{0x375f, 0x0e},</div><div class='add'>+	{0x3768, 0x30},</div><div class='add'>+	{0x3769, 0x44},</div><div class='add'>+	{0x376a, 0x22},</div><div class='add'>+	{0x377b, 0x20},</div><div class='add'>+	{0x377c, 0x00},</div><div class='add'>+	{0x377d, 0x0c},</div><div class='add'>+	{0x3798, 0x00},</div><div class='add'>+	{0x37a1, 0x55},</div><div class='add'>+	{0x37a8, 0x6d},</div><div class='add'>+	{0x37c2, 0x04},</div><div class='add'>+	{0x37c5, 0x00},</div><div class='add'>+	{0x37c8, 0x00},</div><div class='add'>+	{0x3800, 0x00},</div><div class='add'>+	{0x3801, 0x00},</div><div class='add'>+	{0x3802, 0x00},</div><div class='add'>+	{0x3803, 0x00},</div><div class='add'>+	{0x3804, 0x07},</div><div class='add'>+	{0x3805, 0x8f},</div><div class='add'>+	{0x3806, 0x04},</div><div class='add'>+	{0x3807, 0x47},</div><div class='add'>+	{0x3808, 0x07},</div><div class='add'>+	{0x3809, 0x88},</div><div class='add'>+	{0x380a, 0x04},</div><div class='add'>+	{0x380b, 0x40},</div><div class='add'>+	{0x380c, 0x08},</div><div class='add'>+	{0x380d, 0x70},</div><div class='add'>+	{0x380e, 0x04},</div><div class='add'>+	{0x380f, 0x56},</div><div class='add'>+	{0x3810, 0x00},</div><div class='add'>+	{0x3811, 0x04},</div><div class='add'>+	{0x3812, 0x00},</div><div class='add'>+	{0x3813, 0x04},</div><div class='add'>+	{0x3814, 0x01},</div><div class='add'>+	{0x3815, 0x01},</div><div class='add'>+	{0x3820, 0x80},</div><div class='add'>+	{0x3821, 0x46},</div><div class='add'>+	{0x3822, 0x84},</div><div class='add'>+	{0x3829, 0x00},</div><div class='add'>+	{0x382a, 0x01},</div><div class='add'>+	{0x382b, 0x01},</div><div class='add'>+	{0x3830, 0x04},</div><div class='add'>+	{0x3836, 0x01},</div><div class='add'>+	{0x3837, 0x08},</div><div class='add'>+	{0x3839, 0x01},</div><div class='add'>+	{0x383a, 0x00},</div><div class='add'>+	{0x383b, 0x08},</div><div class='add'>+	{0x383c, 0x00},</div><div class='add'>+	{0x3f0b, 0x00},</div><div class='add'>+	{0x4001, 0x20},</div><div class='add'>+	{0x4009, 0x07},</div><div class='add'>+	{0x4003, 0x10},</div><div class='add'>+	{0x4010, 0xe0},</div><div class='add'>+	{0x4016, 0x00},</div><div class='add'>+	{0x4017, 0x10},</div><div class='add'>+	{0x4044, 0x02},</div><div class='add'>+	{0x4304, 0x08},</div><div class='add'>+	{0x4307, 0x30},</div><div class='add'>+	{0x4320, 0x80},</div><div class='add'>+	{0x4322, 0x00},</div><div class='add'>+	{0x4323, 0x00},</div><div class='add'>+	{0x4324, 0x00},</div><div class='add'>+	{0x4325, 0x00},</div><div class='add'>+	{0x4326, 0x00},</div><div class='add'>+	{0x4327, 0x00},</div><div class='add'>+	{0x4328, 0x00},</div><div class='add'>+	{0x4329, 0x00},</div><div class='add'>+	{0x432c, 0x03},</div><div class='add'>+	{0x432d, 0x81},</div><div class='add'>+	{0x4501, 0x84},</div><div class='add'>+	{0x4502, 0x40},</div><div class='add'>+	{0x4503, 0x18},</div><div class='add'>+	{0x4504, 0x04},</div><div class='add'>+	{0x4508, 0x02},</div><div class='add'>+	{0x4601, 0x10},</div><div class='add'>+	{0x4800, 0x00},</div><div class='add'>+	{0x4816, 0x52},</div><div class='add'>+	{0x5000, 0x73},	/* 0x7f enable DPC */</div><div class='add'>+	{0x5001, 0x00},</div><div class='add'>+	{0x5005, 0x38},</div><div class='add'>+	{0x501e, 0x0d},</div><div class='add'>+	{0x5040, 0x00},</div><div class='add'>+	{0x5901, 0x00},</div><div class='add'>+	{0x3800, 0x00},</div><div class='add'>+	{0x3801, 0x00},</div><div class='add'>+	{0x3802, 0x00},</div><div class='add'>+	{0x3803, 0x00},</div><div class='add'>+	{0x3804, 0x07},</div><div class='add'>+	{0x3805, 0x8f},</div><div class='add'>+	{0x3806, 0x04},</div><div class='add'>+	{0x3807, 0x47},</div><div class='add'>+	{0x3808, 0x07},</div><div class='add'>+	{0x3809, 0x8c},</div><div class='add'>+	{0x380a, 0x04},</div><div class='add'>+	{0x380b, 0x44},</div><div class='add'>+	{0x3810, 0x00},</div><div class='add'>+	{0x3811, 0x00},</div><div class='add'>+	{0x3812, 0x00},</div><div class='add'>+	{0x3813, 0x01},</div><div class='add'>+	{0x4003, 0x40},	/* set Black level to 0x40 */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const char * const ov2740_test_pattern_menu[] = {</div><div class='ctx'> 	"Disabled",</div><div class='ctx'> 	"Color Bar",</div><div class='hunk'>@@ -295,6 +461,7 @@ static const char * const ov2740_test_pattern_menu[] = {</div><div class='ctx'> </div><div class='ctx'> static const s64 link_freq_menu_items[] = {</div><div class='ctx'> 	OV2740_LINK_FREQ_360MHZ,</div><div class='add'>+	OV2740_LINK_FREQ_180MHZ,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct ov2740_link_freq_config link_freq_configs[] = {</div><div class='hunk'>@@ -304,23 +471,46 @@ static const struct ov2740_link_freq_config link_freq_configs[] = {</div><div class='ctx'> 			.regs = mipi_data_rate_720mbps,</div><div class='ctx'> 		}</div><div class='ctx'> 	},</div><div class='add'>+	[OV2740_LINK_FREQ_180MHZ_INDEX] = {</div><div class='add'>+		.reg_list = {</div><div class='add'>+			.num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),</div><div class='add'>+			.regs = mipi_data_rate_360mbps,</div><div class='add'>+		}</div><div class='add'>+	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct ov2740_mode supported_modes[] = {</div><div class='add'>+static const struct ov2740_mode supported_modes_360mhz[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.width = 1932,</div><div class='ctx'> 		.height = 1092,</div><div class='del'>-		.hts = 1080,</div><div class='del'>-		.vts_def = OV2740_VTS_DEF,</div><div class='del'>-		.vts_min = OV2740_VTS_MIN,</div><div class='add'>+		.hts = 2160,</div><div class='add'>+		.vts_min = 1120,</div><div class='add'>+		.vts_def = 2186,</div><div class='add'>+		.vts_max = 32767,</div><div class='ctx'> 		.reg_list = {</div><div class='del'>-			.num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),</div><div class='del'>-			.regs = mode_1932x1092_regs,</div><div class='add'>+			.num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz),</div><div class='add'>+			.regs = mode_1932x1092_regs_360mhz,</div><div class='ctx'> 		},</div><div class='ctx'> 		.link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct ov2740_mode supported_modes_180mhz[] = {</div><div class='add'>+	{</div><div class='add'>+		.width = 1932,</div><div class='add'>+		.height = 1092,</div><div class='add'>+		.hts = 2160,</div><div class='add'>+		.vts_min = 1110,</div><div class='add'>+		.vts_def = 1110,</div><div class='add'>+		.vts_max = 2047,</div><div class='add'>+		.reg_list = {</div><div class='add'>+			.num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz),</div><div class='add'>+			.regs = mode_1932x1092_regs_180mhz,</div><div class='add'>+		},</div><div class='add'>+		.link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct ov2740 {</div><div class='ctx'> 	struct v4l2_subdev sd;</div><div class='ctx'> 	struct media_pad pad;</div><div class='hunk'>@@ -333,12 +523,20 @@ struct ov2740 {</div><div class='ctx'> 	struct v4l2_ctrl *hblank;</div><div class='ctx'> 	struct v4l2_ctrl *exposure;</div><div class='ctx'> </div><div class='add'>+	/* GPIOs, clocks */</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct clk *clk;</div><div class='add'>+</div><div class='ctx'> 	/* Current mode */</div><div class='ctx'> 	const struct ov2740_mode *cur_mode;</div><div class='ctx'> </div><div class='ctx'> 	/* NVM data inforamtion */</div><div class='ctx'> 	struct nvm_data *nvm;</div><div class='ctx'> </div><div class='add'>+	/* Supported modes */</div><div class='add'>+	const struct ov2740_mode *supported_modes;</div><div class='add'>+	int supported_modes_count;</div><div class='add'>+</div><div class='ctx'> 	/* True if the device has been identified */</div><div class='ctx'> 	bool identified;</div><div class='ctx'> };</div><div class='hunk'>@@ -357,15 +555,6 @@ static u64 to_pixel_rate(u32 f_index)</div><div class='ctx'> 	return pixel_rate;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u64 to_pixels_per_line(u32 hts, u32 f_index)</div><div class='del'>-{</div><div class='del'>-	u64 ppl = hts * to_pixel_rate(f_index);</div><div class='del'>-</div><div class='del'>-	do_div(ppl, OV2740_SCLK);</div><div class='del'>-</div><div class='del'>-	return ppl;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(&amp;ov2740-&gt;sd);</div><div class='hunk'>@@ -592,14 +781,13 @@ static int ov2740_init_controls(struct ov2740 *ov2740)</div><div class='ctx'> 					       pixel_rate, 1, pixel_rate);</div><div class='ctx'> </div><div class='ctx'> 	vblank_min = cur_mode-&gt;vts_min - cur_mode-&gt;height;</div><div class='del'>-	vblank_max = OV2740_VTS_MAX - cur_mode-&gt;height;</div><div class='add'>+	vblank_max = cur_mode-&gt;vts_max - cur_mode-&gt;height;</div><div class='ctx'> 	vblank_default = cur_mode-&gt;vts_def - cur_mode-&gt;height;</div><div class='ctx'> 	ov2740-&gt;vblank = v4l2_ctrl_new_std(ctrl_hdlr, &amp;ov2740_ctrl_ops,</div><div class='ctx'> 					   V4L2_CID_VBLANK, vblank_min,</div><div class='ctx'> 					   vblank_max, 1, vblank_default);</div><div class='ctx'> </div><div class='del'>-	h_blank = to_pixels_per_line(cur_mode-&gt;hts, cur_mode-&gt;link_freq_index);</div><div class='del'>-	h_blank -= cur_mode-&gt;width;</div><div class='add'>+	h_blank = cur_mode-&gt;hts - cur_mode-&gt;width;</div><div class='ctx'> 	ov2740-&gt;hblank = v4l2_ctrl_new_std(ctrl_hdlr, &amp;ov2740_ctrl_ops,</div><div class='ctx'> 					   V4L2_CID_HBLANK, h_blank, h_blank, 1,</div><div class='ctx'> 					   h_blank);</div><div class='hunk'>@@ -745,6 +933,15 @@ static int ov2740_start_streaming(struct ov2740 *ov2740)</div><div class='ctx'> 	if (ov2740-&gt;nvm)</div><div class='ctx'> 		ov2740_load_otp_data(ov2740-&gt;nvm);</div><div class='ctx'> </div><div class='add'>+	/* Reset the sensor */</div><div class='add'>+	ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to reset\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usleep_range(10000, 15000);</div><div class='add'>+</div><div class='ctx'> 	link_freq_index = ov2740-&gt;cur_mode-&gt;link_freq_index;</div><div class='ctx'> 	reg_list = &amp;link_freq_configs[link_freq_index].reg_list;</div><div class='ctx'> 	ret = ov2740_write_reg_list(ov2740, reg_list);</div><div class='hunk'>@@ -820,13 +1017,13 @@ static int ov2740_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	const struct ov2740_mode *mode;</div><div class='ctx'> 	s32 vblank_def, h_blank;</div><div class='ctx'> </div><div class='del'>-	mode = v4l2_find_nearest_size(supported_modes,</div><div class='del'>-				      ARRAY_SIZE(supported_modes), width,</div><div class='del'>-				      height, fmt-&gt;format.width,</div><div class='del'>-				      fmt-&gt;format.height);</div><div class='add'>+	mode = v4l2_find_nearest_size(ov2740-&gt;supported_modes,</div><div class='add'>+				      ov2740-&gt;supported_modes_count,</div><div class='add'>+				      width, height,</div><div class='add'>+				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> </div><div class='ctx'> 	ov2740_update_pad_format(mode, &amp;fmt-&gt;format);</div><div class='del'>-	*v4l2_subdev_get_pad_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+	*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -840,10 +1037,9 @@ static int ov2740_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	vblank_def = mode-&gt;vts_def - mode-&gt;height;</div><div class='ctx'> 	__v4l2_ctrl_modify_range(ov2740-&gt;vblank,</div><div class='ctx'> 				 mode-&gt;vts_min - mode-&gt;height,</div><div class='del'>-				 OV2740_VTS_MAX - mode-&gt;height, 1, vblank_def);</div><div class='add'>+				 mode-&gt;vts_max - mode-&gt;height, 1, vblank_def);</div><div class='ctx'> 	__v4l2_ctrl_s_ctrl(ov2740-&gt;vblank, vblank_def);</div><div class='del'>-	h_blank = to_pixels_per_line(mode-&gt;hts, mode-&gt;link_freq_index) -</div><div class='del'>-		mode-&gt;width;</div><div class='add'>+	h_blank = mode-&gt;hts - mode-&gt;width;</div><div class='ctx'> 	__v4l2_ctrl_modify_range(ov2740-&gt;hblank, h_blank, h_blank, 1, h_blank);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -865,7 +1061,10 @@ static int ov2740_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 				  struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				  struct v4l2_subdev_frame_size_enum *fse)</div><div class='ctx'> {</div><div class='del'>-	if (fse-&gt;index &gt;= ARRAY_SIZE(supported_modes))</div><div class='add'>+	struct ov2740 *ov2740 = to_ov2740(sd);</div><div class='add'>+	const struct ov2740_mode *supported_modes = ov2740-&gt;supported_modes;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index &gt;= ov2740-&gt;supported_modes_count)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (fse-&gt;code != MEDIA_BUS_FMT_SGRBG10_1X10)</div><div class='hunk'>@@ -879,12 +1078,13 @@ static int ov2740_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov2740_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov2740_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='del'>-	ov2740_update_pad_format(&amp;supported_modes[0],</div><div class='del'>-				 v4l2_subdev_get_pad_format(sd, sd_state, 0));</div><div class='add'>+	struct ov2740 *ov2740 = to_ov2740(sd);</div><div class='ctx'> </div><div class='add'>+	ov2740_update_pad_format(&amp;ov2740-&gt;supported_modes[0],</div><div class='add'>+				 v4l2_subdev_state_get_format(sd_state, 0));</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -897,7 +1097,6 @@ static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {</div><div class='ctx'> 	.set_fmt = ov2740_set_format,</div><div class='ctx'> 	.enum_mbus_code = ov2740_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov2740_enum_frame_size,</div><div class='del'>-	.init_cfg = ov2740_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov2740_subdev_ops = {</div><div class='hunk'>@@ -905,12 +1104,18 @@ static const struct v4l2_subdev_ops ov2740_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov2740_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {</div><div class='add'>+	.init_state = ov2740_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ov2740_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int ov2740_check_hwcfg(struct device *dev)</div><div class='ctx'> {</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct ov2740 *ov2740 = to_ov2740(sd);</div><div class='ctx'> 	struct fwnode_handle *ep;</div><div class='ctx'> 	struct fwnode_handle *fwnode = dev_fwnode(dev);</div><div class='ctx'> 	struct v4l2_fwnode_endpoint bus_cfg = {</div><div class='hunk'>@@ -920,23 +1125,32 @@ static int ov2740_check_hwcfg(struct device *dev)</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	unsigned int i, j;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Sometimes the fwnode graph is initialized by the bridge driver,</div><div class='add'>+	 * wait for this.</div><div class='add'>+	 */</div><div class='add'>+	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);</div><div class='add'>+	if (!ep)</div><div class='add'>+		return -EPROBE_DEFER;</div><div class='add'>+</div><div class='ctx'> 	ret = fwnode_property_read_u32(fwnode, "clock-frequency", &amp;mclk);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret) {</div><div class='add'>+		fwnode_handle_put(ep);</div><div class='add'>+		return dev_err_probe(dev, ret,</div><div class='add'>+				     "reading clock-frequency property\n");</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (mclk != OV2740_MCLK)</div><div class='add'>+	if (mclk != OV2740_MCLK) {</div><div class='add'>+		fwnode_handle_put(ep);</div><div class='ctx'> 		return dev_err_probe(dev, -EINVAL,</div><div class='ctx'> 				     "external clock %d is not supported\n",</div><div class='ctx'> 				     mclk);</div><div class='del'>-</div><div class='del'>-	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);</div><div class='del'>-	if (!ep)</div><div class='del'>-		return -EPROBE_DEFER;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &amp;bus_cfg);</div><div class='ctx'> 	fwnode_handle_put(ep);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		return ret;</div><div class='add'>+		return dev_err_probe(dev, ret, "parsing endpoint failed\n");</div><div class='ctx'> </div><div class='ctx'> 	if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {</div><div class='ctx'> 		ret = dev_err_probe(dev, -EINVAL,</div><div class='hunk'>@@ -957,14 +1171,29 @@ static int ov2740_check_hwcfg(struct device *dev)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (j == bus_cfg.nr_of_link_frequencies) {</div><div class='del'>-			ret = dev_err_probe(dev, -EINVAL,</div><div class='del'>-					    "no link frequency %lld supported\n",</div><div class='del'>-					    link_freq_menu_items[i]);</div><div class='del'>-			goto check_hwcfg_error;</div><div class='add'>+		if (j == bus_cfg.nr_of_link_frequencies)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		switch (i) {</div><div class='add'>+		case OV2740_LINK_FREQ_360MHZ_INDEX:</div><div class='add'>+			ov2740-&gt;supported_modes = supported_modes_360mhz;</div><div class='add'>+			ov2740-&gt;supported_modes_count =</div><div class='add'>+				ARRAY_SIZE(supported_modes_360mhz);</div><div class='add'>+			break;</div><div class='add'>+		case OV2740_LINK_FREQ_180MHZ_INDEX:</div><div class='add'>+			ov2740-&gt;supported_modes = supported_modes_180mhz;</div><div class='add'>+			ov2740-&gt;supported_modes_count =</div><div class='add'>+				ARRAY_SIZE(supported_modes_180mhz);</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		break; /* Prefer modes from first available link-freq */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!ov2740-&gt;supported_modes)</div><div class='add'>+		ret = dev_err_probe(dev, -EINVAL,</div><div class='add'>+				    "no supported link frequencies\n");</div><div class='add'>+</div><div class='ctx'> check_hwcfg_error:</div><div class='ctx'> 	v4l2_fwnode_endpoint_free(&amp;bus_cfg);</div><div class='ctx'> </div><div class='hunk'>@@ -1058,6 +1287,32 @@ static int ov2740_register_nvmem(struct i2c_client *client,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ov2740_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct ov2740 *ov2740 = to_ov2740(sd);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(ov2740-&gt;reset_gpio, 1);</div><div class='add'>+	clk_disable_unprepare(ov2740-&gt;clk);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov2740_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct ov2740 *ov2740 = to_ov2740(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(ov2740-&gt;clk);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(ov2740-&gt;reset_gpio, 0);</div><div class='add'>+	msleep(20);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ov2740_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='hunk'>@@ -1065,23 +1320,42 @@ static int ov2740_probe(struct i2c_client *client)</div><div class='ctx'> 	bool full_power;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = ov2740_check_hwcfg(&amp;client-&gt;dev);</div><div class='del'>-	if (ret)</div><div class='del'>-		return dev_err_probe(dev, ret, "failed to check HW configuration\n");</div><div class='del'>-</div><div class='ctx'> 	ov2740 = devm_kzalloc(&amp;client-&gt;dev, sizeof(*ov2740), GFP_KERNEL);</div><div class='ctx'> 	if (!ov2740)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov2740-&gt;sd, client, &amp;ov2740_subdev_ops);</div><div class='add'>+	ov2740-&gt;sd.internal_ops = &amp;ov2740_internal_ops;</div><div class='add'>+</div><div class='add'>+	ret = ov2740_check_hwcfg(dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "failed to check HW configuration\n");</div><div class='add'>+</div><div class='add'>+	ov2740-&gt;reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(ov2740-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(ov2740-&gt;reset_gpio),</div><div class='add'>+				     "failed to get reset GPIO\n");</div><div class='add'>+</div><div class='add'>+	ov2740-&gt;clk = devm_clk_get_optional(dev, "clk");</div><div class='add'>+	if (IS_ERR(ov2740-&gt;clk))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(ov2740-&gt;clk),</div><div class='add'>+				     "failed to get clock\n");</div><div class='add'>+</div><div class='ctx'> 	full_power = acpi_dev_state_d0(&amp;client-&gt;dev);</div><div class='ctx'> 	if (full_power) {</div><div class='del'>-		ret = ov2740_identify_module(ov2740);</div><div class='add'>+		/* ACPI does not always clear the reset GPIO / enable the clock */</div><div class='add'>+		ret = ov2740_resume(dev);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return dev_err_probe(dev, ret, "failed to find sensor\n");</div><div class='add'>+			return dev_err_probe(dev, ret, "failed to power on sensor\n");</div><div class='add'>+</div><div class='add'>+		ret = ov2740_identify_module(ov2740);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err_probe(dev, ret, "failed to find sensor\n");</div><div class='add'>+			goto probe_error_power_off;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ov2740-&gt;cur_mode = &amp;supported_modes[0];</div><div class='add'>+	ov2740-&gt;cur_mode = &amp;ov2740-&gt;supported_modes[0];</div><div class='ctx'> 	ret = ov2740_init_controls(ov2740);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err_probe(dev, ret, "failed to init controls\n");</div><div class='hunk'>@@ -1132,9 +1406,16 @@ probe_error_media_entity_cleanup:</div><div class='ctx'> probe_error_v4l2_ctrl_handler_free:</div><div class='ctx'> 	v4l2_ctrl_handler_free(ov2740-&gt;sd.ctrl_handler);</div><div class='ctx'> </div><div class='add'>+probe_error_power_off:</div><div class='add'>+	if (full_power)</div><div class='add'>+		ov2740_suspend(dev);</div><div class='add'>+</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume,</div><div class='add'>+				 NULL);</div><div class='add'>+</div><div class='ctx'> static const struct acpi_device_id ov2740_acpi_ids[] = {</div><div class='ctx'> 	{"INT3474"},</div><div class='ctx'> 	{}</div><div class='hunk'>@@ -1146,6 +1427,7 @@ static struct i2c_driver ov2740_i2c_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "ov2740",</div><div class='ctx'> 		.acpi_match_table = ov2740_acpi_ids,</div><div class='add'>+		.pm = pm_sleep_ptr(&amp;ov2740_pm_ops),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = ov2740_probe,</div><div class='ctx'> 	.remove = ov2740_remove,</div><div class='head'>diff --git a/drivers/media/i2c/ov4689.c b/drivers/media/i2c/ov4689.c<br/>index 3bd972a822e7..403091651885 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov4689.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov4689.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov4689.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov4689.c</a></div><div class='hunk'>@@ -570,7 +570,7 @@ static int ov4689_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov4689-&gt;mutex);</div><div class='ctx'> </div><div class='del'>-	try_fmt = v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+	try_fmt = v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> 	/* Initialize try_fmt */</div><div class='ctx'> 	ov4689_fill_fmt(&amp;supported_modes[OV4689_MODE_2688_1520], try_fmt);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c<br/>index 40532f7bcabe..5162d45fe73b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5640.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5640.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5640.c</a></div><div class='hunk'>@@ -399,7 +399,7 @@ struct ov5640_mode_info {</div><div class='ctx'> 	const struct reg_value *reg_data;</div><div class='ctx'> 	u32 reg_data_size;</div><div class='ctx'> </div><div class='del'>-	/* Used by s_frame_interval only. */</div><div class='add'>+	/* Used by set_frame_interval only. */</div><div class='ctx'> 	u32 max_fps;</div><div class='ctx'> 	u32 def_fps;</div><div class='ctx'> };</div><div class='hunk'>@@ -2797,8 +2797,7 @@ static int ov5640_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(&amp;sensor-&gt;sd, sd_state,</div><div class='del'>-						 format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		fmt = &amp;sensor-&gt;fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -2971,7 +2970,7 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, 0) = *mbus_fmt;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *mbus_fmt;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3605,11 +3604,19 @@ static int ov5640_enum_frame_interval(</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5640_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int ov5640_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov5640_dev *sensor = to_ov5640_dev(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> 	fi-&gt;interval = sensor-&gt;frame_interval;</div><div class='ctx'> 	mutex_unlock(&amp;sensor-&gt;lock);</div><div class='hunk'>@@ -3617,13 +3624,21 @@ static int ov5640_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5640_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int ov5640_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov5640_dev *sensor = to_ov5640_dev(sd);</div><div class='ctx'> 	const struct ov5640_mode_info *mode;</div><div class='ctx'> 	int frame_rate, ret = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (fi-&gt;pad != 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -3745,13 +3760,13 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5640_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int ov5640_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov5640_dev *sensor = to_ov5640_dev(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, state, 0);</div><div class='del'>-	struct v4l2_rect *crop = v4l2_subdev_get_try_crop(sd, state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	*fmt = ov5640_is_csi2(sensor) ? ov5640_csi2_default_fmt :</div><div class='ctx'> 					ov5640_dvp_default_fmt;</div><div class='hunk'>@@ -3771,17 +3786,16 @@ static const struct v4l2_subdev_core_ops ov5640_core_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov5640_video_ops = {</div><div class='del'>-	.g_frame_interval = ov5640_g_frame_interval,</div><div class='del'>-	.s_frame_interval = ov5640_s_frame_interval,</div><div class='ctx'> 	.s_stream = ov5640_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov5640_pad_ops = {</div><div class='del'>-	.init_cfg = ov5640_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov5640_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = ov5640_get_fmt,</div><div class='ctx'> 	.set_fmt = ov5640_set_fmt,</div><div class='ctx'> 	.get_selection = ov5640_get_selection,</div><div class='add'>+	.get_frame_interval = ov5640_get_frame_interval,</div><div class='add'>+	.set_frame_interval = ov5640_set_frame_interval,</div><div class='ctx'> 	.enum_frame_size = ov5640_enum_frame_size,</div><div class='ctx'> 	.enum_frame_interval = ov5640_enum_frame_interval,</div><div class='ctx'> };</div><div class='hunk'>@@ -3792,6 +3806,10 @@ static const struct v4l2_subdev_ops ov5640_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov5640_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov5640_internal_ops = {</div><div class='add'>+	.init_state = ov5640_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ov5640_get_regulators(struct ov5640_dev *sensor)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -3906,6 +3924,7 @@ static int ov5640_probe(struct i2c_client *client)</div><div class='ctx'> 		return PTR_ERR(sensor-&gt;reset_gpio);</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;sensor-&gt;sd, client, &amp;ov5640_subdev_ops);</div><div class='add'>+	sensor-&gt;sd.internal_ops = &amp;ov5640_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	sensor-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 			    V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='head'>diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c<br/>index a70db7e601a4..a26ac11c989d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5645.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5645.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5645.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5645.c</a></div><div class='hunk'>@@ -851,7 +851,7 @@ __ov5645_get_pad_format(struct ov5645 *ov5645,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;ov5645-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov5645-&gt;fmt;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -878,7 +878,7 @@ __ov5645_get_pad_crop(struct ov5645 *ov5645,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov5645-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov5645-&gt;crop;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -934,8 +934,8 @@ static int ov5645_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5645_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov5645_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='ctx'> </div><div class='hunk'>@@ -1023,7 +1023,6 @@ static const struct v4l2_subdev_video_ops ov5645_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {</div><div class='del'>-	.init_cfg = ov5645_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov5645_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov5645_enum_frame_size,</div><div class='ctx'> 	.get_fmt = ov5645_get_format,</div><div class='hunk'>@@ -1036,6 +1035,10 @@ static const struct v4l2_subdev_ops ov5645_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov5645_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov5645_internal_ops = {</div><div class='add'>+	.init_state = ov5645_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ov5645_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;client-&gt;dev;</div><div class='hunk'>@@ -1162,6 +1165,7 @@ static int ov5645_probe(struct i2c_client *client)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov5645-&gt;sd, client, &amp;ov5645_subdev_ops);</div><div class='add'>+	ov5645-&gt;sd.internal_ops = &amp;ov5645_internal_ops;</div><div class='ctx'> 	ov5645-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	ov5645-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='ctx'> 	ov5645-&gt;sd.dev = &amp;client-&gt;dev;</div><div class='hunk'>@@ -1220,7 +1224,7 @@ static int ov5645_probe(struct i2c_client *client)</div><div class='ctx'> 	pm_runtime_get_noresume(dev);</div><div class='ctx'> 	pm_runtime_enable(dev);</div><div class='ctx'> </div><div class='del'>-	ov5645_entity_init_cfg(&amp;ov5645-&gt;sd, NULL);</div><div class='add'>+	ov5645_init_state(&amp;ov5645-&gt;sd, NULL);</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_async_register_subdev(&amp;ov5645-&gt;sd);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='head'>diff --git a/drivers/media/i2c/ov5647.c b/drivers/media/i2c/ov5647.c<br/>index dcfe3129c63a..96c0fd4ff5ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5647.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5647.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5647.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5647.c</a></div><div class='hunk'>@@ -882,7 +882,7 @@ __ov5647_get_pad_crop(struct ov5647 *ov5647,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov5647-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov5647-&gt;mode-&gt;crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -975,8 +975,8 @@ static int ov5647_get_pad_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> 	switch (format-&gt;which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		sensor_format = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		sensor_format = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		sensor_format = &amp;sensor-&gt;mode-&gt;format;</div><div class='hunk'>@@ -1004,7 +1004,7 @@ static int ov5647_set_pad_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	/* Update the sensor mode and apply at it at streamon time. */</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad) = mode-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, format-&gt;pad) = mode-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		int exposure_max, exposure_def;</div><div class='ctx'> 		int hblank, vblank;</div><div class='hunk'>@@ -1121,8 +1121,8 @@ static int ov5647_detect(struct v4l2_subdev *sd)</div><div class='ctx'> static int ov5647_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='del'>-	struct v4l2_rect *crop = v4l2_subdev_get_try_crop(sd, fh-&gt;state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='add'>+	struct v4l2_rect *crop = v4l2_subdev_state_get_crop(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	crop-&gt;left = OV5647_PIXEL_ARRAY_LEFT;</div><div class='ctx'> 	crop-&gt;top = OV5647_PIXEL_ARRAY_TOP;</div><div class='head'>diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c<br/>index aa10eb4e3991..4b86d2631bd1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5648.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5648.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5648.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5648.c</a></div><div class='hunk'>@@ -2158,37 +2158,8 @@ static int ov5648_s_stream(struct v4l2_subdev *subdev, int enable)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5648_g_frame_interval(struct v4l2_subdev *subdev,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *interval)</div><div class='del'>-{</div><div class='del'>-	struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev);</div><div class='del'>-	const struct ov5648_mode *mode;</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	mode = sensor-&gt;state.mode;</div><div class='del'>-</div><div class='del'>-	switch (sensor-&gt;state.mbus_code) {</div><div class='del'>-	case MEDIA_BUS_FMT_SBGGR8_1X8:</div><div class='del'>-		interval-&gt;interval = mode-&gt;frame_interval[0];</div><div class='del'>-		break;</div><div class='del'>-	case MEDIA_BUS_FMT_SBGGR10_1X10:</div><div class='del'>-		interval-&gt;interval = mode-&gt;frame_interval[1];</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		ret = -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;sensor-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct v4l2_subdev_video_ops ov5648_subdev_video_ops = {</div><div class='ctx'> 	.s_stream		= ov5648_s_stream,</div><div class='del'>-	.g_frame_interval	= ov5648_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= ov5648_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Subdev Pad Operations */</div><div class='hunk'>@@ -2232,8 +2203,8 @@ static int ov5648_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*mbus_format = *v4l2_subdev_get_try_format(subdev, sd_state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		*mbus_format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov5648_mbus_format_fill(mbus_format, sensor-&gt;state.mbus_code,</div><div class='ctx'> 					sensor-&gt;state.mode);</div><div class='hunk'>@@ -2285,7 +2256,7 @@ static int ov5648_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	ov5648_mbus_format_fill(mbus_format, mbus_code, mode);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(subdev, sd_state, format-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, format-&gt;pad) =</div><div class='ctx'> 			*mbus_format;</div><div class='ctx'> 	else if (sensor-&gt;state.mode != mode ||</div><div class='ctx'> 		 sensor-&gt;state.mbus_code != mbus_code)</div><div class='hunk'>@@ -2297,6 +2268,41 @@ complete:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ov5648_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+{</div><div class='add'>+	struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev);</div><div class='add'>+	const struct ov5648_mode *mode;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	mode = sensor-&gt;state.mode;</div><div class='add'>+</div><div class='add'>+	switch (sensor-&gt;state.mbus_code) {</div><div class='add'>+	case MEDIA_BUS_FMT_SBGGR8_1X8:</div><div class='add'>+		interval-&gt;interval = mode-&gt;frame_interval[0];</div><div class='add'>+		break;</div><div class='add'>+	case MEDIA_BUS_FMT_SBGGR10_1X10:</div><div class='add'>+		interval-&gt;interval = mode-&gt;frame_interval[1];</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;sensor-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ov5648_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> 				  struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				  struct v4l2_subdev_frame_size_enum *size_enum)</div><div class='hunk'>@@ -2363,6 +2369,8 @@ static const struct v4l2_subdev_pad_ops ov5648_subdev_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code		= ov5648_enum_mbus_code,</div><div class='ctx'> 	.get_fmt		= ov5648_get_fmt,</div><div class='ctx'> 	.set_fmt		= ov5648_set_fmt,</div><div class='add'>+	.get_frame_interval	= ov5648_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= ov5648_get_frame_interval,</div><div class='ctx'> 	.enum_frame_size	= ov5648_enum_frame_size,</div><div class='ctx'> 	.enum_frame_interval	= ov5648_enum_frame_interval,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/media/i2c/ov5670.c b/drivers/media/i2c/ov5670.c<br/>index e80db3ecd4f8..2aee85965cf7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5670.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5670.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5670.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5670.c</a></div><div class='hunk'>@@ -2196,13 +2196,13 @@ error:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5670_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int ov5670_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	const struct ov5670_mode *default_mode = &amp;supported_modes[0];</div><div class='del'>-	struct v4l2_rect *crop = v4l2_subdev_get_try_crop(sd, state, 0);</div><div class='add'>+	struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	fmt-&gt;width = default_mode-&gt;width;</div><div class='ctx'> 	fmt-&gt;height = default_mode-&gt;height;</div><div class='hunk'>@@ -2263,9 +2263,8 @@ static int ov5670_do_get_pad_format(struct ov5670 *ov5670,</div><div class='ctx'> 				    struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;ov5670-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov5670_update_pad_format(ov5670-&gt;cur_mode, fmt);</div><div class='ctx'> </div><div class='hunk'>@@ -2310,7 +2309,7 @@ static int ov5670_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='ctx'> 	ov5670_update_pad_format(mode, fmt);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov5670-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(ov5670-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -2550,7 +2549,7 @@ __ov5670_get_pad_crop(struct ov5670 *sensor, struct v4l2_subdev_state *state,</div><div class='ctx'> </div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;sensor-&gt;sd, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return mode-&gt;analog_crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2593,7 +2592,6 @@ static const struct v4l2_subdev_video_ops ov5670_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov5670_pad_ops = {</div><div class='del'>-	.init_cfg = ov5670_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov5670_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = ov5670_get_pad_format,</div><div class='ctx'> 	.set_fmt = ov5670_set_pad_format,</div><div class='hunk'>@@ -2613,6 +2611,10 @@ static const struct v4l2_subdev_ops ov5670_subdev_ops = {</div><div class='ctx'> 	.sensor = &amp;ov5670_sensor_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov5670_internal_ops = {</div><div class='add'>+	.init_state = ov5670_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations ov5670_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -2676,6 +2678,7 @@ static int ov5670_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov5670-&gt;sd, client, &amp;ov5670_subdev_ops);</div><div class='add'>+	ov5670-&gt;sd.internal_ops = &amp;ov5670_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = ov5670_regulators_probe(ov5670);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/i2c/ov5675.c b/drivers/media/i2c/ov5675.c<br/>index e63d9d402d34..3641911bc73f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5675.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5675.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5675.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5675.c</a></div><div class='hunk'>@@ -1036,7 +1036,7 @@ static int ov5675_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov5675-&gt;mutex);</div><div class='ctx'> 	ov5675_update_pad_format(mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov5675-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(ov5675-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -1069,9 +1069,8 @@ static int ov5675_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov5675-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;ov5675-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov5675_update_pad_format(ov5675-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -1141,7 +1140,7 @@ static int ov5675_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov5675-&gt;mutex);</div><div class='ctx'> 	ov5675_update_pad_format(&amp;supported_modes[0],</div><div class='del'>-				 v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				 v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;ov5675-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c<br/>index 819425e21349..8deb28b55983 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5693.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5693.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5693.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5693.c</a></div><div class='hunk'>@@ -775,7 +775,7 @@ __ov5693_get_pad_format(struct ov5693_device *ov5693,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;ov5693-&gt;sd, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov5693-&gt;mode.format;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -790,7 +790,7 @@ __ov5693_get_pad_crop(struct ov5693_device *ov5693,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov5693-&gt;sd, state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov5693-&gt;mode.crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1004,14 +1004,22 @@ err_power_down:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov5693_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+static int ov5693_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *interval)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov5693_device *ov5693 = to_ov5693_sensor(sd);</div><div class='ctx'> 	unsigned int framesize = OV5693_FIXED_PPL * (ov5693-&gt;mode.format.height +</div><div class='ctx'> 				 ov5693-&gt;ctrls.vblank-&gt;val);</div><div class='ctx'> 	unsigned int fps = DIV_ROUND_CLOSEST(OV5693_PIXEL_RATE, framesize);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	interval-&gt;interval.numerator = 1;</div><div class='ctx'> 	interval-&gt;interval.denominator = fps;</div><div class='ctx'> </div><div class='hunk'>@@ -1054,7 +1062,6 @@ static int ov5693_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov5693_video_ops = {</div><div class='ctx'> 	.s_stream = ov5693_s_stream,</div><div class='del'>-	.g_frame_interval = ov5693_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov5693_pad_ops = {</div><div class='hunk'>@@ -1064,6 +1071,7 @@ static const struct v4l2_subdev_pad_ops ov5693_pad_ops = {</div><div class='ctx'> 	.set_fmt = ov5693_set_fmt,</div><div class='ctx'> 	.get_selection = ov5693_get_selection,</div><div class='ctx'> 	.set_selection = ov5693_set_selection,</div><div class='add'>+	.get_frame_interval = ov5693_get_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov5693_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/ov5695.c b/drivers/media/i2c/ov5695.c<br/>index c8f57ce1578d..663eccdfea6a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5695.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov5695.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov5695.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov5695.c</a></div><div class='hunk'>@@ -820,7 +820,7 @@ static int ov5695_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	fmt-&gt;format.height = mode-&gt;height;</div><div class='ctx'> 	fmt-&gt;format.field = V4L2_FIELD_NONE;</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov5695-&gt;cur_mode = mode;</div><div class='ctx'> 		h_blank = mode-&gt;hts_def - mode-&gt;width;</div><div class='hunk'>@@ -846,8 +846,8 @@ static int ov5695_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov5695-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		fmt-&gt;format.width = mode-&gt;width;</div><div class='ctx'> 		fmt-&gt;format.height = mode-&gt;height;</div><div class='hunk'>@@ -1039,7 +1039,7 @@ static int ov5695_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov5695 *ov5695 = to_ov5695(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *try_fmt =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> 	const struct ov5695_mode *def_mode = &amp;supported_modes[0];</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov5695-&gt;mutex);</div><div class='head'>diff --git a/drivers/media/i2c/ov64a40.c b/drivers/media/i2c/ov64a40.c<br/>new file mode 100644<br/>index 000000000000..4fba4c2cb064<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov64a40.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov64a40.c</a></div><div class='hunk'>@@ -0,0 +1,3690 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * V4L2 sensor driver for OmniVision OV64A40</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2023 Ideas On Board Oy</div><div class='add'>+ * Copyright (C) 2023 Arducam</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-mediabus.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#define OV64A40_XCLK_FREQ		24000000</div><div class='add'>+</div><div class='add'>+#define OV64A40_NATIVE_WIDTH		9286</div><div class='add'>+#define OV64A40_NATIVE_HEIGHT		6976</div><div class='add'>+#define OV64A40_PIXEL_ARRAY_TOP		0</div><div class='add'>+#define OV64A40_PIXEL_ARRAY_LEFT	0</div><div class='add'>+#define OV64A40_PIXEL_ARRAY_WIDTH	9248</div><div class='add'>+#define OV64A40_PIXEL_ARRAY_HEIGHT	6944</div><div class='add'>+</div><div class='add'>+#define OV64A40_PIXEL_RATE		300000000</div><div class='add'>+</div><div class='add'>+#define OV64A40_LINK_FREQ_360M		360000000</div><div class='add'>+#define OV64A40_LINK_FREQ_456M		456000000</div><div class='add'>+</div><div class='add'>+#define OV64A40_PLL1_PRE_DIV0		CCI_REG8(0x0301)</div><div class='add'>+#define OV64A40_PLL1_PRE_DIV		CCI_REG8(0x0303)</div><div class='add'>+#define OV64A40_PLL1_MULTIPLIER		CCI_REG16(0x0304)</div><div class='add'>+#define OV64A40_PLL1_M_DIV		CCI_REG8(0x0307)</div><div class='add'>+#define OV64A40_PLL2_SEL_BAK_SA1	CCI_REG8(0x0320)</div><div class='add'>+#define OV64A40_PLL2_PRE_DIV		CCI_REG8(0x0323)</div><div class='add'>+#define OV64A40_PLL2_MULTIPLIER		CCI_REG16(0x0324)</div><div class='add'>+#define OV64A40_PLL2_PRE_DIV0		CCI_REG8(0x0326)</div><div class='add'>+#define OV64A40_PLL2_DIVDAC		CCI_REG8(0x0329)</div><div class='add'>+#define OV64A40_PLL2_DIVSP		CCI_REG8(0x032d)</div><div class='add'>+#define OV64A40_PLL2_DACPREDIV		CCI_REG8(0x032e)</div><div class='add'>+</div><div class='add'>+/* TODO: validate vblank_min, it's not characterized in the datasheet. */</div><div class='add'>+#define OV64A40_VBLANK_MIN		128</div><div class='add'>+#define OV64A40_VTS_MAX			0xffffff</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_MEC_LONG_EXPO	CCI_REG24(0x3500)</div><div class='add'>+#define OV64A40_EXPOSURE_MIN		16</div><div class='add'>+#define OV64A40_EXPOSURE_MARGIN		32</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_MEC_LONG_GAIN	CCI_REG16(0x3508)</div><div class='add'>+#define OV64A40_ANA_GAIN_MIN		0x80</div><div class='add'>+#define OV64A40_ANA_GAIN_MAX		0x7ff</div><div class='add'>+#define OV64A40_ANA_GAIN_DEFAULT	0x80</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL0	CCI_REG16(0x3800)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL2	CCI_REG16(0x3802)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL4	CCI_REG16(0x3804)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL6	CCI_REG16(0x3806)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL8	CCI_REG16(0x3808)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRLA	CCI_REG16(0x380a)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRLC	CCI_REG16(0x380c)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRLE	CCI_REG16(0x380e)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL10	CCI_REG16(0x3810)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL12	CCI_REG16(0x3812)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Careful: a typo in the datasheet calls this register</div><div class='add'>+ * OV64A40_REG_TIMING_CTRL20.</div><div class='add'>+ */</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL14	CCI_REG8(0x3814)</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL15	CCI_REG8(0x3815)</div><div class='add'>+#define OV64A40_ODD_INC_SHIFT		4</div><div class='add'>+#define OV64A40_SKIPPING_CONFIG(_odd, _even) \</div><div class='add'>+				(((_odd) &lt;&lt; OV64A40_ODD_INC_SHIFT) | (_even))</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL_20	CCI_REG8(0x3820)</div><div class='add'>+#define OV64A40_TIMING_CTRL_20_VFLIP	BIT(2)</div><div class='add'>+#define OV64A40_TIMING_CTRL_20_VBIN	BIT(1)</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_TIMING_CTRL_21	CCI_REG8(0x3821)</div><div class='add'>+#define OV64A40_TIMING_CTRL_21_HBIN	BIT(4)</div><div class='add'>+#define OV64A40_TIMING_CTRL_21_HFLIP	BIT(2)</div><div class='add'>+#define OV64A40_TIMING_CTRL_21_DSPEED	BIT(0)</div><div class='add'>+#define OV64A40_TIMING_CTRL_21_HBIN_CONF \</div><div class='add'>+					(OV64A40_TIMING_CTRL_21_HBIN | \</div><div class='add'>+					 OV64A40_TIMING_CTRL_21_DSPEED)</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_TIMINGS_VTS_HIGH	CCI_REG8(0x3840)</div><div class='add'>+#define OV64A40_REG_TIMINGS_VTS_MID	CCI_REG8(0x380e)</div><div class='add'>+#define OV64A40_REG_TIMINGS_VTS_LOW	CCI_REG8(0x380f)</div><div class='add'>+</div><div class='add'>+/* The test pattern control is weirdly named PRE_ISP_2325_D2V2_TOP_1 in TRM. */</div><div class='add'>+#define OV64A40_REG_TEST_PATTERN	CCI_REG8(0x50c1)</div><div class='add'>+#define OV64A40_TEST_PATTERN_DISABLED	0x00</div><div class='add'>+#define OV64A40_TEST_PATTERN_TYPE1	BIT(0)</div><div class='add'>+#define OV64A40_TEST_PATTERN_TYPE2	(BIT(4) | BIT(0))</div><div class='add'>+#define OV64A40_TEST_PATTERN_TYPE3	(BIT(5) | BIT(0))</div><div class='add'>+#define OV64A40_TEST_PATTERN_TYPE4	(BIT(5) | BIT(4) | BIT(0))</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_CHIP_ID		CCI_REG24(0x300a)</div><div class='add'>+#define OV64A40_CHIP_ID			0x566441</div><div class='add'>+</div><div class='add'>+#define OV64A40_REG_SMIA		CCI_REG8(0x0100)</div><div class='add'>+#define OV64A40_REG_SMIA_STREAMING	BIT(0)</div><div class='add'>+</div><div class='add'>+enum ov64a40_link_freq_ids {</div><div class='add'>+	OV64A40_LINK_FREQ_456M_ID,</div><div class='add'>+	OV64A40_LINK_FREQ_360M_ID,</div><div class='add'>+	OV64A40_NUM_LINK_FREQ,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char * const ov64a40_supply_names[] = {</div><div class='add'>+	/* Supplies can be enabled in any order */</div><div class='add'>+	"avdd",		/* Analog (2.8V) supply */</div><div class='add'>+	"dovdd",	/* Digital Core (1.8V) supply */</div><div class='add'>+	"dvdd",		/* IF (1.1V) supply */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char * const ov64a40_test_pattern_menu[] = {</div><div class='add'>+	"Disabled",</div><div class='add'>+	"Type1",</div><div class='add'>+	"Type2",</div><div class='add'>+	"Type3",</div><div class='add'>+	"Type4",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int ov64a40_test_pattern_val[] = {</div><div class='add'>+	OV64A40_TEST_PATTERN_DISABLED,</div><div class='add'>+	OV64A40_TEST_PATTERN_TYPE1,</div><div class='add'>+	OV64A40_TEST_PATTERN_TYPE2,</div><div class='add'>+	OV64A40_TEST_PATTERN_TYPE3,</div><div class='add'>+	OV64A40_TEST_PATTERN_TYPE4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int ov64a40_mbus_codes[] = {</div><div class='add'>+	MEDIA_BUS_FMT_SBGGR10_1X10,</div><div class='add'>+	MEDIA_BUS_FMT_SGRBG10_1X10,</div><div class='add'>+	MEDIA_BUS_FMT_SGBRG10_1X10,</div><div class='add'>+	MEDIA_BUS_FMT_SRGGB10_1X10,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_init[] = {</div><div class='add'>+	{ CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 },</div><div class='add'>+	{ CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 },</div><div class='add'>+	{ CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 },</div><div class='add'>+	{ CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 },</div><div class='add'>+	{ CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 },</div><div class='add'>+	{ CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 },</div><div class='add'>+	{ CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3500), 0x00 }, { CCI_REG8(0x3501), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3502), 0x18 }, { CCI_REG8(0x3504), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x3508), 0x01 }, { CCI_REG8(0x3509), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x350a), 0x01 }, { CCI_REG8(0x350b), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x3540), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3541), 0x00 }, { CCI_REG8(0x3542), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3548), 0x01 }, { CCI_REG8(0x3549), 0xa0 },</div><div class='add'>+	{ CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3580), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3581), 0x00 }, { CCI_REG8(0x3582), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3588), 0x01 }, { CCI_REG8(0x3589), 0xf0 },</div><div class='add'>+	{ CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x360d), 0x83 },</div><div class='add'>+	{ CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3617), 0x31 },</div><div class='add'>+	{ CCI_REG8(0x3623), 0x10 }, { CCI_REG8(0x3633), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x3634), 0x03 }, { CCI_REG8(0x3635), 0x77 },</div><div class='add'>+	{ CCI_REG8(0x3640), 0x19 }, { CCI_REG8(0x3641), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x364d), 0x0f }, { CCI_REG8(0x3680), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x3682), 0x00 }, { CCI_REG8(0x3683), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3684), 0x07 }, { CCI_REG8(0x3688), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3689), 0x08 }, { CCI_REG8(0x368a), 0x26 },</div><div class='add'>+	{ CCI_REG8(0x368b), 0xc8 }, { CCI_REG8(0x368e), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x368f), 0x00 }, { CCI_REG8(0x3692), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3693), 0x00 }, { CCI_REG8(0x3696), 0xd1 },</div><div class='add'>+	{ CCI_REG8(0x3697), 0xe0 }, { CCI_REG8(0x3698), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x3699), 0x2b }, { CCI_REG8(0x369a), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x369d), 0x00 }, { CCI_REG8(0x369e), 0x14 },</div><div class='add'>+	{ CCI_REG8(0x369f), 0x20 }, { CCI_REG8(0x36a5), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x36a6), 0x00 }, { CCI_REG8(0x36a7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x36a8), 0x00 }, { CCI_REG8(0x36b5), 0x17 },</div><div class='add'>+	{ CCI_REG8(0x3701), 0x30 }, { CCI_REG8(0x3706), 0x2b },</div><div class='add'>+	{ CCI_REG8(0x3709), 0x8d }, { CCI_REG8(0x370b), 0x4f },</div><div class='add'>+	{ CCI_REG8(0x3711), 0x00 }, { CCI_REG8(0x3712), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3713), 0x00 }, { CCI_REG8(0x3720), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3727), 0x22 }, { CCI_REG8(0x3728), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x375e), 0x00 }, { CCI_REG8(0x3760), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3761), 0x10 }, { CCI_REG8(0x3762), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3765), 0x10 }, { CCI_REG8(0x3766), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x376a), 0x08 }, { CCI_REG8(0x376b), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x376d), 0x1b }, { CCI_REG8(0x3791), 0x2b },</div><div class='add'>+	{ CCI_REG8(0x3793), 0x2b }, { CCI_REG8(0x3795), 0x2b },</div><div class='add'>+	{ CCI_REG8(0x3797), 0x4f }, { CCI_REG8(0x3799), 0x4f },</div><div class='add'>+	{ CCI_REG8(0x379b), 0x4f }, { CCI_REG8(0x37a0), 0x22 },</div><div class='add'>+	{ CCI_REG8(0x37da), 0x04 }, { CCI_REG8(0x37f9), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x37fa), 0x02 }, { CCI_REG8(0x37fb), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3814), 0x11 }, { CCI_REG8(0x3815), 0x11 },</div><div class='add'>+	{ CCI_REG8(0x3820), 0x40 }, { CCI_REG8(0x3821), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3823), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3827), 0x08 }, { CCI_REG8(0x3828), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x382a), 0x81 }, { CCI_REG8(0x382e), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x3837), 0x10 }, { CCI_REG8(0x3839), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x383b), 0x00 }, { CCI_REG8(0x383c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x383d), 0x10 }, { CCI_REG8(0x383f), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0x8c },</div><div class='add'>+	{ CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x3857), 0x10 }, { CCI_REG8(0x3858), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x3859), 0x20 }, { CCI_REG8(0x3894), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3895), 0x00 }, { CCI_REG8(0x3896), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3897), 0x00 }, { CCI_REG8(0x3900), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aed), 0x6e }, { CCI_REG8(0x3af1), 0x73 },</div><div class='add'>+	{ CCI_REG8(0x3d86), 0x12 }, { CCI_REG8(0x3d87), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x3d8c), 0xab }, { CCI_REG8(0x3d8d), 0xb0 },</div><div class='add'>+	{ CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f01), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x4009), 0x01 }, { CCI_REG8(0x400e), 0xc6 },</div><div class='add'>+	{ CCI_REG8(0x400f), 0x00 }, { CCI_REG8(0x4010), 0x28 },</div><div class='add'>+	{ CCI_REG8(0x4011), 0x01 }, { CCI_REG8(0x4012), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x4015), 0x00 }, { CCI_REG8(0x4016), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x4017), 0x00 }, { CCI_REG8(0x4018), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x401a), 0x40 }, { CCI_REG8(0x4028), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4506), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4508), 0x00 }, { CCI_REG8(0x4509), 0x35 },</div><div class='add'>+	{ CCI_REG8(0x450a), 0x08 }, { CCI_REG8(0x450c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x450d), 0x20 }, { CCI_REG8(0x450e), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x450f), 0x20 }, { CCI_REG8(0x451e), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x451f), 0x00 }, { CCI_REG8(0x4523), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4526), 0x00 }, { CCI_REG8(0x4527), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x4580), 0x01 }, { CCI_REG8(0x4583), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4584), 0x00 }, { CCI_REG8(0x45c0), 0xa1 },</div><div class='add'>+	{ CCI_REG8(0x4602), 0x08 }, { CCI_REG8(0x4603), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x4606), 0x12 }, { CCI_REG8(0x4607), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x460b), 0x00 }, { CCI_REG8(0x460d), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4640), 0x00 }, { CCI_REG8(0x4641), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x4643), 0x08 }, { CCI_REG8(0x4645), 0x14 },</div><div class='add'>+	{ CCI_REG8(0x4648), 0x0a }, { CCI_REG8(0x4649), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x464a), 0x00 }, { CCI_REG8(0x464b), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x4800), 0x04 }, { CCI_REG8(0x4802), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x480b), 0x10 }, { CCI_REG8(0x480c), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x480e), 0x04 }, { CCI_REG8(0x480f), 0x32 },</div><div class='add'>+	{ CCI_REG8(0x481b), 0x12 }, { CCI_REG8(0x4833), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x4837), 0x08 }, { CCI_REG8(0x484b), 0x27 },</div><div class='add'>+	{ CCI_REG8(0x4850), 0x42 }, { CCI_REG8(0x4851), 0xaa },</div><div class='add'>+	{ CCI_REG8(0x4860), 0x01 }, { CCI_REG8(0x4861), 0xec },</div><div class='add'>+	{ CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x4888), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4889), 0x03 }, { CCI_REG8(0x488c), 0x60 },</div><div class='add'>+	{ CCI_REG8(0x4910), 0x28 }, { CCI_REG8(0x4911), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4912), 0x0c }, { CCI_REG8(0x491a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x4915), 0x00 }, { CCI_REG8(0x4916), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x4917), 0x00 }, { CCI_REG8(0x4918), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x4a10), 0x28 }, { CCI_REG8(0x4a11), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4a12), 0x0c }, { CCI_REG8(0x4a1a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x4a15), 0x00 }, { CCI_REG8(0x4a16), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x4a17), 0x00 }, { CCI_REG8(0x4a18), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x4d00), 0x04 }, { CCI_REG8(0x4d01), 0x5a },</div><div class='add'>+	{ CCI_REG8(0x4d02), 0xbb }, { CCI_REG8(0x4d03), 0x84 },</div><div class='add'>+	{ CCI_REG8(0x4d04), 0xd1 }, { CCI_REG8(0x4d05), 0x68 },</div><div class='add'>+	{ CCI_REG8(0xc4fa), 0x10 }, { CCI_REG8(0x3b56), 0x0a },</div><div class='add'>+	{ CCI_REG8(0x3b57), 0x0a }, { CCI_REG8(0x3b58), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x3b59), 0x10 }, { CCI_REG8(0x3a1d), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x3a1e), 0x30 }, { CCI_REG8(0x3a21), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x3a22), 0x30 }, { CCI_REG8(0x3992), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x39fb), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x39fc), 0x30 }, { CCI_REG8(0x39fd), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x39fe), 0x30 }, { CCI_REG8(0x3a6d), 0x83 },</div><div class='add'>+	{ CCI_REG8(0x3a5e), 0x83 }, { CCI_REG8(0xc500), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc501), 0x12 }, { CCI_REG8(0xc502), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc503), 0x12 }, { CCI_REG8(0xc505), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc506), 0x12 }, { CCI_REG8(0xc507), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc508), 0x12 }, { CCI_REG8(0x3a77), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x3a73), 0x12 }, { CCI_REG8(0x3a7b), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x3a7f), 0x12 }, { CCI_REG8(0x3b2e), 0x13 },</div><div class='add'>+	{ CCI_REG8(0x3b29), 0x13 }, { CCI_REG8(0xc439), 0x13 },</div><div class='add'>+	{ CCI_REG8(0xc469), 0x13 }, { CCI_REG8(0xc41c), 0x89 },</div><div class='add'>+	{ CCI_REG8(0x3618), 0x80 }, { CCI_REG8(0xc514), 0x51 },</div><div class='add'>+	{ CCI_REG8(0xc515), 0x2c }, { CCI_REG8(0xc516), 0x16 },</div><div class='add'>+	{ CCI_REG8(0xc517), 0x0d }, { CCI_REG8(0x3615), 0x7f },</div><div class='add'>+	{ CCI_REG8(0x3632), 0x99 }, { CCI_REG8(0x3642), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3645), 0x80 }, { CCI_REG8(0x3702), 0x2a },</div><div class='add'>+	{ CCI_REG8(0x3703), 0x2a }, { CCI_REG8(0x3708), 0x2f },</div><div class='add'>+	{ CCI_REG8(0x3721), 0x15 }, { CCI_REG8(0x3744), 0x28 },</div><div class='add'>+	{ CCI_REG8(0x3991), 0x0c }, { CCI_REG8(0x371d), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x371f), 0x0c }, { CCI_REG8(0x374b), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x391d), 0x55 },</div><div class='add'>+	{ CCI_REG8(0x391e), 0x52 }, { CCI_REG8(0x399d), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x3a2f), 0x01 }, { CCI_REG8(0x3a30), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a31), 0x01 }, { CCI_REG8(0x3a32), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a34), 0x01 }, { CCI_REG8(0x3a35), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a36), 0x01 }, { CCI_REG8(0x3a37), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a43), 0x01 }, { CCI_REG8(0x3a44), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a45), 0x01 }, { CCI_REG8(0x3a46), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a48), 0x01 }, { CCI_REG8(0x3a49), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a4a), 0x01 }, { CCI_REG8(0x3a4b), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3a50), 0x14 }, { CCI_REG8(0x3a54), 0x14 },</div><div class='add'>+	{ CCI_REG8(0x3a60), 0x20 }, { CCI_REG8(0x3a6f), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x3ac5), 0x01 }, { CCI_REG8(0x3ac6), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3ac7), 0x01 }, { CCI_REG8(0x3ac8), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3ac9), 0x01 }, { CCI_REG8(0x3aca), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3acb), 0x01 }, { CCI_REG8(0x3acc), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3acd), 0x01 }, { CCI_REG8(0x3ace), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3acf), 0x01 }, { CCI_REG8(0x3ad0), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3ad1), 0x01 }, { CCI_REG8(0x3ad2), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3ad3), 0x01 }, { CCI_REG8(0x3ad4), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3add), 0x1f }, { CCI_REG8(0x3adf), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x3aef), 0x1f }, { CCI_REG8(0x3af0), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x3b92), 0x08 }, { CCI_REG8(0x3b93), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3b94), 0x08 }, { CCI_REG8(0x3b95), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3be7), 0x1e }, { CCI_REG8(0x3be8), 0x26 },</div><div class='add'>+	{ CCI_REG8(0xc44a), 0x20 }, { CCI_REG8(0xc44c), 0x20 },</div><div class='add'>+	{ CCI_REG8(0xc483), 0x00 }, { CCI_REG8(0xc484), 0x00 },</div><div class='add'>+	{ CCI_REG8(0xc485), 0x00 }, { CCI_REG8(0xc486), 0x00 },</div><div class='add'>+	{ CCI_REG8(0xc487), 0x01 }, { CCI_REG8(0xc488), 0x01 },</div><div class='add'>+	{ CCI_REG8(0xc489), 0x01 }, { CCI_REG8(0xc48a), 0x01 },</div><div class='add'>+	{ CCI_REG8(0xc4c1), 0x00 }, { CCI_REG8(0xc4c2), 0x00 },</div><div class='add'>+	{ CCI_REG8(0xc4c3), 0x00 }, { CCI_REG8(0xc4c4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0xc4c6), 0x10 }, { CCI_REG8(0xc4c7), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4c8), 0x10 }, { CCI_REG8(0xc4c9), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4ca), 0x10 }, { CCI_REG8(0xc4cb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4cc), 0x10 }, { CCI_REG8(0xc4cd), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4ea), 0x07 }, { CCI_REG8(0xc4eb), 0x07 },</div><div class='add'>+	{ CCI_REG8(0xc4ec), 0x07 }, { CCI_REG8(0xc4ed), 0x07 },</div><div class='add'>+	{ CCI_REG8(0xc4ee), 0x07 }, { CCI_REG8(0xc4f6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4f7), 0x10 }, { CCI_REG8(0xc4f8), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc4f9), 0x10 }, { CCI_REG8(0xc518), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc519), 0x0e }, { CCI_REG8(0xc51a), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc51b), 0x0e }, { CCI_REG8(0xc51c), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc51d), 0x0e }, { CCI_REG8(0xc51e), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc51f), 0x0e }, { CCI_REG8(0xc520), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc521), 0x0e }, { CCI_REG8(0xc522), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc523), 0x0e }, { CCI_REG8(0xc524), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc525), 0x0e }, { CCI_REG8(0xc526), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc527), 0x0e }, { CCI_REG8(0xc528), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc529), 0x0e }, { CCI_REG8(0xc52a), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc52b), 0x0e }, { CCI_REG8(0xc52c), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc52d), 0x0e }, { CCI_REG8(0xc52e), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc52f), 0x0e }, { CCI_REG8(0xc530), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc531), 0x0e }, { CCI_REG8(0xc532), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc533), 0x0e }, { CCI_REG8(0xc534), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc535), 0x0e }, { CCI_REG8(0xc536), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc537), 0x0e }, { CCI_REG8(0xc538), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc539), 0x0e }, { CCI_REG8(0xc53a), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc53b), 0x0e }, { CCI_REG8(0xc53c), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc53d), 0x0e }, { CCI_REG8(0xc53e), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc53f), 0x0e }, { CCI_REG8(0xc540), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc541), 0x0e }, { CCI_REG8(0xc542), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc543), 0x0e }, { CCI_REG8(0xc544), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc545), 0x0e }, { CCI_REG8(0xc546), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc547), 0x0e }, { CCI_REG8(0xc548), 0x0e },</div><div class='add'>+	{ CCI_REG8(0xc549), 0x0e }, { CCI_REG8(0xc57f), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc580), 0x22 }, { CCI_REG8(0xc581), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc582), 0x22 }, { CCI_REG8(0xc583), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc584), 0x22 }, { CCI_REG8(0xc585), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc586), 0x22 }, { CCI_REG8(0xc587), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc588), 0x22 }, { CCI_REG8(0xc589), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc58a), 0x22 }, { CCI_REG8(0xc58b), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc58c), 0x22 }, { CCI_REG8(0xc58d), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc58e), 0x22 }, { CCI_REG8(0xc58f), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc590), 0x22 }, { CCI_REG8(0xc591), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc592), 0x22 }, { CCI_REG8(0xc598), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc599), 0x22 }, { CCI_REG8(0xc59a), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc59b), 0x22 }, { CCI_REG8(0xc59c), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc59d), 0x22 }, { CCI_REG8(0xc59e), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc59f), 0x22 }, { CCI_REG8(0xc5a0), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5a1), 0x22 }, { CCI_REG8(0xc5a2), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5a3), 0x22 }, { CCI_REG8(0xc5a4), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5a5), 0x22 }, { CCI_REG8(0xc5a6), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5a7), 0x22 }, { CCI_REG8(0xc5a8), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5a9), 0x22 }, { CCI_REG8(0xc5aa), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5ab), 0x22 }, { CCI_REG8(0xc5b1), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5b2), 0x2a }, { CCI_REG8(0xc5b3), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5b4), 0x2a }, { CCI_REG8(0xc5b5), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5b6), 0x2a }, { CCI_REG8(0xc5b7), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5b8), 0x2a }, { CCI_REG8(0xc5b9), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5ba), 0x2a }, { CCI_REG8(0xc5bb), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5bc), 0x2a }, { CCI_REG8(0xc5bd), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5be), 0x2a }, { CCI_REG8(0xc5bf), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5c0), 0x2a }, { CCI_REG8(0xc5c1), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5c2), 0x2a }, { CCI_REG8(0xc5c3), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5c4), 0x2a }, { CCI_REG8(0xc5ca), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5cb), 0x2a }, { CCI_REG8(0xc5cc), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5cd), 0x2a }, { CCI_REG8(0xc5ce), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5cf), 0x2a }, { CCI_REG8(0xc5d0), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5d1), 0x2a }, { CCI_REG8(0xc5d2), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5d3), 0x2a }, { CCI_REG8(0xc5d4), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5d5), 0x2a }, { CCI_REG8(0xc5d6), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5d7), 0x2a }, { CCI_REG8(0xc5d8), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5d9), 0x2a }, { CCI_REG8(0xc5da), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5db), 0x2a }, { CCI_REG8(0xc5dc), 0x2a },</div><div class='add'>+	{ CCI_REG8(0xc5dd), 0x2a }, { CCI_REG8(0xc5e8), 0x22 },</div><div class='add'>+	{ CCI_REG8(0xc5ea), 0x22 }, { CCI_REG8(0x4540), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x4541), 0x30 }, { CCI_REG8(0x3d86), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x3d87), 0x30 }, { CCI_REG8(0x4606), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x4607), 0x30 }, { CCI_REG8(0x4648), 0x0a },</div><div class='add'>+	{ CCI_REG8(0x4649), 0x06 }, { CCI_REG8(0x3220), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x3221), 0x30 }, { CCI_REG8(0x40c2), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x49c2), 0x12 }, { CCI_REG8(0x4ac2), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x40c3), 0x30 }, { CCI_REG8(0x49c3), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x4ac3), 0x30 }, { CCI_REG8(0x36b0), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x36b1), 0x30 }, { CCI_REG8(0x45cb), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x45cc), 0x30 }, { CCI_REG8(0x4585), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x4586), 0x30 }, { CCI_REG8(0x36b2), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x36b3), 0x30 }, { CCI_REG8(0x5a40), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a41), 0x75 }, { CCI_REG8(0x5a42), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a43), 0x75 }, { CCI_REG8(0x5a44), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a45), 0x75 }, { CCI_REG8(0x5a46), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a47), 0x75 }, { CCI_REG8(0x5a48), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a49), 0x75 }, { CCI_REG8(0x5a4a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a4b), 0x75 }, { CCI_REG8(0x5a4c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a4d), 0x75 }, { CCI_REG8(0x5a4e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a4f), 0x75 }, { CCI_REG8(0x5a50), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a51), 0x75 }, { CCI_REG8(0x5a52), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a53), 0x75 }, { CCI_REG8(0x5a54), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a55), 0x75 }, { CCI_REG8(0x5a56), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a57), 0x75 }, { CCI_REG8(0x5a58), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a59), 0x75 }, { CCI_REG8(0x5a5a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a5b), 0x75 }, { CCI_REG8(0x5a5c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a5d), 0x75 }, { CCI_REG8(0x5a5e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a5f), 0x75 }, { CCI_REG8(0x5a60), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a61), 0x75 }, { CCI_REG8(0x5a62), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a63), 0x75 }, { CCI_REG8(0x5a64), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a65), 0x75 }, { CCI_REG8(0x5a66), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a67), 0x75 }, { CCI_REG8(0x5a68), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a69), 0x75 }, { CCI_REG8(0x5a6a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a6b), 0x75 }, { CCI_REG8(0x5a6c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a6d), 0x75 }, { CCI_REG8(0x5a6e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a6f), 0x75 }, { CCI_REG8(0x5a70), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a71), 0x75 }, { CCI_REG8(0x5a72), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a73), 0x75 }, { CCI_REG8(0x5a74), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a75), 0x75 }, { CCI_REG8(0x5a76), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a77), 0x75 }, { CCI_REG8(0x5a78), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a79), 0x75 }, { CCI_REG8(0x5a7a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a7b), 0x75 }, { CCI_REG8(0x5a7c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a7d), 0x75 }, { CCI_REG8(0x5a7e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a7f), 0x75 }, { CCI_REG8(0x5a80), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a81), 0x75 }, { CCI_REG8(0x5a82), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a83), 0x75 }, { CCI_REG8(0x5a84), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a85), 0x75 }, { CCI_REG8(0x5a86), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a87), 0x75 }, { CCI_REG8(0x5a88), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a89), 0x75 }, { CCI_REG8(0x5a8a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a8b), 0x75 }, { CCI_REG8(0x5a8c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a8d), 0x75 }, { CCI_REG8(0x5a8e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a8f), 0x75 }, { CCI_REG8(0x5a90), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a91), 0x75 }, { CCI_REG8(0x5a92), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a93), 0x75 }, { CCI_REG8(0x5a94), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a95), 0x75 }, { CCI_REG8(0x5a96), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a97), 0x75 }, { CCI_REG8(0x5a98), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a99), 0x75 }, { CCI_REG8(0x5a9a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a9b), 0x75 }, { CCI_REG8(0x5a9c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a9d), 0x75 }, { CCI_REG8(0x5a9e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5a9f), 0x75 }, { CCI_REG8(0x5aa0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aa1), 0x75 }, { CCI_REG8(0x5aa2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aa3), 0x75 }, { CCI_REG8(0x5aa4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aa5), 0x75 }, { CCI_REG8(0x5aa6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aa7), 0x75 }, { CCI_REG8(0x5aa8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aa9), 0x75 }, { CCI_REG8(0x5aaa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aab), 0x75 }, { CCI_REG8(0x5aac), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aad), 0x75 }, { CCI_REG8(0x5aae), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aaf), 0x75 }, { CCI_REG8(0x5ab0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ab1), 0x75 }, { CCI_REG8(0x5ab2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ab3), 0x75 }, { CCI_REG8(0x5ab4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ab5), 0x75 }, { CCI_REG8(0x5ab6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ab7), 0x75 }, { CCI_REG8(0x5ab8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ab9), 0x75 }, { CCI_REG8(0x5aba), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5abb), 0x75 }, { CCI_REG8(0x5abc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5abd), 0x75 }, { CCI_REG8(0x5abe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5abf), 0x75 }, { CCI_REG8(0x5ac0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ac1), 0x75 }, { CCI_REG8(0x5ac2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ac3), 0x75 }, { CCI_REG8(0x5ac4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ac5), 0x75 }, { CCI_REG8(0x5ac6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ac7), 0x75 }, { CCI_REG8(0x5ac8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ac9), 0x75 }, { CCI_REG8(0x5aca), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5acb), 0x75 }, { CCI_REG8(0x5acc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5acd), 0x75 }, { CCI_REG8(0x5ace), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5acf), 0x75 }, { CCI_REG8(0x5ad0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ad1), 0x75 }, { CCI_REG8(0x5ad2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ad3), 0x75 }, { CCI_REG8(0x5ad4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ad5), 0x75 }, { CCI_REG8(0x5ad6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ad7), 0x75 }, { CCI_REG8(0x5ad8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ad9), 0x75 }, { CCI_REG8(0x5ada), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5adb), 0x75 }, { CCI_REG8(0x5adc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5add), 0x75 }, { CCI_REG8(0x5ade), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5adf), 0x75 }, { CCI_REG8(0x5ae0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ae1), 0x75 }, { CCI_REG8(0x5ae2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ae3), 0x75 }, { CCI_REG8(0x5ae4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ae5), 0x75 }, { CCI_REG8(0x5ae6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ae7), 0x75 }, { CCI_REG8(0x5ae8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ae9), 0x75 }, { CCI_REG8(0x5aea), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aeb), 0x75 }, { CCI_REG8(0x5aec), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aed), 0x75 }, { CCI_REG8(0x5aee), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aef), 0x75 }, { CCI_REG8(0x5af0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5af1), 0x75 }, { CCI_REG8(0x5af2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5af3), 0x75 }, { CCI_REG8(0x5af4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5af5), 0x75 }, { CCI_REG8(0x5af6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5af7), 0x75 }, { CCI_REG8(0x5af8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5af9), 0x75 }, { CCI_REG8(0x5afa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5afb), 0x75 }, { CCI_REG8(0x5afc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5afd), 0x75 }, { CCI_REG8(0x5afe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5aff), 0x75 }, { CCI_REG8(0x5b00), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b01), 0x75 }, { CCI_REG8(0x5b02), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b03), 0x75 }, { CCI_REG8(0x5b04), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b05), 0x75 }, { CCI_REG8(0x5b06), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b07), 0x75 }, { CCI_REG8(0x5b08), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b09), 0x75 }, { CCI_REG8(0x5b0a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b0b), 0x75 }, { CCI_REG8(0x5b0c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b0d), 0x75 }, { CCI_REG8(0x5b0e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b0f), 0x75 }, { CCI_REG8(0x5b10), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b11), 0x75 }, { CCI_REG8(0x5b12), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b13), 0x75 }, { CCI_REG8(0x5b14), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b15), 0x75 }, { CCI_REG8(0x5b16), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b17), 0x75 }, { CCI_REG8(0x5b18), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b19), 0x75 }, { CCI_REG8(0x5b1a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b1b), 0x75 }, { CCI_REG8(0x5b1c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b1d), 0x75 }, { CCI_REG8(0x5b1e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b1f), 0x75 }, { CCI_REG8(0x5b20), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b21), 0x75 }, { CCI_REG8(0x5b22), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b23), 0x75 }, { CCI_REG8(0x5b24), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b25), 0x75 }, { CCI_REG8(0x5b26), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b27), 0x75 }, { CCI_REG8(0x5b28), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b29), 0x75 }, { CCI_REG8(0x5b2a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b2b), 0x75 }, { CCI_REG8(0x5b2c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b2d), 0x75 }, { CCI_REG8(0x5b2e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b2f), 0x75 }, { CCI_REG8(0x5b30), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b31), 0x75 }, { CCI_REG8(0x5b32), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b33), 0x75 }, { CCI_REG8(0x5b34), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b35), 0x75 }, { CCI_REG8(0x5b36), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b37), 0x75 }, { CCI_REG8(0x5b38), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b39), 0x75 }, { CCI_REG8(0x5b3a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b3b), 0x75 }, { CCI_REG8(0x5b3c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b3d), 0x75 }, { CCI_REG8(0x5b3e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b3f), 0x75 }, { CCI_REG8(0x5b40), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b41), 0x75 }, { CCI_REG8(0x5b42), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b43), 0x75 }, { CCI_REG8(0x5b44), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b45), 0x75 }, { CCI_REG8(0x5b46), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b47), 0x75 }, { CCI_REG8(0x5b48), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b49), 0x75 }, { CCI_REG8(0x5b4a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b4b), 0x75 }, { CCI_REG8(0x5b4c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b4d), 0x75 }, { CCI_REG8(0x5b4e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b4f), 0x75 }, { CCI_REG8(0x5b50), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b51), 0x75 }, { CCI_REG8(0x5b52), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b53), 0x75 }, { CCI_REG8(0x5b54), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b55), 0x75 }, { CCI_REG8(0x5b56), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b57), 0x75 }, { CCI_REG8(0x5b58), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b59), 0x75 }, { CCI_REG8(0x5b5a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b5b), 0x75 }, { CCI_REG8(0x5b5c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b5d), 0x75 }, { CCI_REG8(0x5b5e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b5f), 0x75 }, { CCI_REG8(0x5b80), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b81), 0x75 }, { CCI_REG8(0x5b82), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b83), 0x75 }, { CCI_REG8(0x5b84), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b85), 0x75 }, { CCI_REG8(0x5b86), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b87), 0x75 }, { CCI_REG8(0x5b88), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b89), 0x75 }, { CCI_REG8(0x5b8a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b8b), 0x75 }, { CCI_REG8(0x5b8c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b8d), 0x75 }, { CCI_REG8(0x5b8e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b8f), 0x75 }, { CCI_REG8(0x5b90), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b91), 0x75 }, { CCI_REG8(0x5b92), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b93), 0x75 }, { CCI_REG8(0x5b94), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b95), 0x75 }, { CCI_REG8(0x5b96), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b97), 0x75 }, { CCI_REG8(0x5b98), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b99), 0x75 }, { CCI_REG8(0x5b9a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b9b), 0x75 }, { CCI_REG8(0x5b9c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b9d), 0x75 }, { CCI_REG8(0x5b9e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5b9f), 0x75 }, { CCI_REG8(0x5ba0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ba1), 0x75 }, { CCI_REG8(0x5ba2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ba3), 0x75 }, { CCI_REG8(0x5ba4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ba5), 0x75 }, { CCI_REG8(0x5ba6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ba7), 0x75 }, { CCI_REG8(0x5ba8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ba9), 0x75 }, { CCI_REG8(0x5baa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bab), 0x75 }, { CCI_REG8(0x5bac), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bad), 0x75 }, { CCI_REG8(0x5bae), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5baf), 0x75 }, { CCI_REG8(0x5bb0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bb1), 0x75 }, { CCI_REG8(0x5bb2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bb3), 0x75 }, { CCI_REG8(0x5bb4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bb5), 0x75 }, { CCI_REG8(0x5bb6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bb7), 0x75 }, { CCI_REG8(0x5bb8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bb9), 0x75 }, { CCI_REG8(0x5bba), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bbb), 0x75 }, { CCI_REG8(0x5bbc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bbd), 0x75 }, { CCI_REG8(0x5bbe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bbf), 0x75 }, { CCI_REG8(0x5bc0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bc1), 0x75 }, { CCI_REG8(0x5bc2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bc3), 0x75 }, { CCI_REG8(0x5bc4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bc5), 0x75 }, { CCI_REG8(0x5bc6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bc7), 0x75 }, { CCI_REG8(0x5bc8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bc9), 0x75 }, { CCI_REG8(0x5bca), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bcb), 0x75 }, { CCI_REG8(0x5bcc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bcd), 0x75 }, { CCI_REG8(0x5bce), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bcf), 0x75 }, { CCI_REG8(0x5bd0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bd1), 0x75 }, { CCI_REG8(0x5bd2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bd3), 0x75 }, { CCI_REG8(0x5bd4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bd5), 0x75 }, { CCI_REG8(0x5bd6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bd7), 0x75 }, { CCI_REG8(0x5bd8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bd9), 0x75 }, { CCI_REG8(0x5bda), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bdb), 0x75 }, { CCI_REG8(0x5bdc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bdd), 0x75 }, { CCI_REG8(0x5bde), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bdf), 0x75 }, { CCI_REG8(0x5be0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5be1), 0x75 }, { CCI_REG8(0x5be2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5be3), 0x75 }, { CCI_REG8(0x5be4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5be5), 0x75 }, { CCI_REG8(0x5be6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5be7), 0x75 }, { CCI_REG8(0x5be8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5be9), 0x75 }, { CCI_REG8(0x5bea), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5beb), 0x75 }, { CCI_REG8(0x5bec), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bed), 0x75 }, { CCI_REG8(0x5bee), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bef), 0x75 }, { CCI_REG8(0x5bf0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bf1), 0x75 }, { CCI_REG8(0x5bf2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bf3), 0x75 }, { CCI_REG8(0x5bf4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bf5), 0x75 }, { CCI_REG8(0x5bf6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bf7), 0x75 }, { CCI_REG8(0x5bf8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bf9), 0x75 }, { CCI_REG8(0x5bfa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bfb), 0x75 }, { CCI_REG8(0x5bfc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bfd), 0x75 }, { CCI_REG8(0x5bfe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5bff), 0x75 }, { CCI_REG8(0x5c00), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c01), 0x75 }, { CCI_REG8(0x5c02), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c03), 0x75 }, { CCI_REG8(0x5c04), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c05), 0x75 }, { CCI_REG8(0x5c06), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c07), 0x75 }, { CCI_REG8(0x5c08), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c09), 0x75 }, { CCI_REG8(0x5c0a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c0b), 0x75 }, { CCI_REG8(0x5c0c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c0d), 0x75 }, { CCI_REG8(0x5c0e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c0f), 0x75 }, { CCI_REG8(0x5c10), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c11), 0x75 }, { CCI_REG8(0x5c12), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c13), 0x75 }, { CCI_REG8(0x5c14), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c15), 0x75 }, { CCI_REG8(0x5c16), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c17), 0x75 }, { CCI_REG8(0x5c18), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c19), 0x75 }, { CCI_REG8(0x5c1a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c1b), 0x75 }, { CCI_REG8(0x5c1c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c1d), 0x75 }, { CCI_REG8(0x5c1e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c1f), 0x75 }, { CCI_REG8(0x5c20), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c21), 0x75 }, { CCI_REG8(0x5c22), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c23), 0x75 }, { CCI_REG8(0x5c24), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c25), 0x75 }, { CCI_REG8(0x5c26), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c27), 0x75 }, { CCI_REG8(0x5c28), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c29), 0x75 }, { CCI_REG8(0x5c2a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c2b), 0x75 }, { CCI_REG8(0x5c2c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c2d), 0x75 }, { CCI_REG8(0x5c2e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c2f), 0x75 }, { CCI_REG8(0x5c30), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c31), 0x75 }, { CCI_REG8(0x5c32), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c33), 0x75 }, { CCI_REG8(0x5c34), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c35), 0x75 }, { CCI_REG8(0x5c36), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c37), 0x75 }, { CCI_REG8(0x5c38), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c39), 0x75 }, { CCI_REG8(0x5c3a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c3b), 0x75 }, { CCI_REG8(0x5c3c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c3d), 0x75 }, { CCI_REG8(0x5c3e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c3f), 0x75 }, { CCI_REG8(0x5c40), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c41), 0x75 }, { CCI_REG8(0x5c42), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c43), 0x75 }, { CCI_REG8(0x5c44), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c45), 0x75 }, { CCI_REG8(0x5c46), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c47), 0x75 }, { CCI_REG8(0x5c48), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c49), 0x75 }, { CCI_REG8(0x5c4a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c4b), 0x75 }, { CCI_REG8(0x5c4c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c4d), 0x75 }, { CCI_REG8(0x5c4e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c4f), 0x75 }, { CCI_REG8(0x5c50), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c51), 0x75 }, { CCI_REG8(0x5c52), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c53), 0x75 }, { CCI_REG8(0x5c54), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c55), 0x75 }, { CCI_REG8(0x5c56), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c57), 0x75 }, { CCI_REG8(0x5c58), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c59), 0x75 }, { CCI_REG8(0x5c5a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c5b), 0x75 }, { CCI_REG8(0x5c5c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c5d), 0x75 }, { CCI_REG8(0x5c5e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c5f), 0x75 }, { CCI_REG8(0x5c60), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c61), 0x75 }, { CCI_REG8(0x5c62), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c63), 0x75 }, { CCI_REG8(0x5c64), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c65), 0x75 }, { CCI_REG8(0x5c66), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c67), 0x75 }, { CCI_REG8(0x5c68), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c69), 0x75 }, { CCI_REG8(0x5c6a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c6b), 0x75 }, { CCI_REG8(0x5c6c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c6d), 0x75 }, { CCI_REG8(0x5c6e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c6f), 0x75 }, { CCI_REG8(0x5c70), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c71), 0x75 }, { CCI_REG8(0x5c72), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c73), 0x75 }, { CCI_REG8(0x5c74), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c75), 0x75 }, { CCI_REG8(0x5c76), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c77), 0x75 }, { CCI_REG8(0x5c78), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c79), 0x75 }, { CCI_REG8(0x5c7a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c7b), 0x75 }, { CCI_REG8(0x5c7c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c7d), 0x75 }, { CCI_REG8(0x5c7e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c7f), 0x75 }, { CCI_REG8(0x5c80), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c81), 0x75 }, { CCI_REG8(0x5c82), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c83), 0x75 }, { CCI_REG8(0x5c84), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c85), 0x75 }, { CCI_REG8(0x5c86), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c87), 0x75 }, { CCI_REG8(0x5c88), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c89), 0x75 }, { CCI_REG8(0x5c8a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c8b), 0x75 }, { CCI_REG8(0x5c8c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c8d), 0x75 }, { CCI_REG8(0x5c8e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c8f), 0x75 }, { CCI_REG8(0x5c90), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c91), 0x75 }, { CCI_REG8(0x5c92), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c93), 0x75 }, { CCI_REG8(0x5c94), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c95), 0x75 }, { CCI_REG8(0x5c96), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c97), 0x75 }, { CCI_REG8(0x5c98), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c99), 0x75 }, { CCI_REG8(0x5c9a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c9b), 0x75 }, { CCI_REG8(0x5c9c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c9d), 0x75 }, { CCI_REG8(0x5c9e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5c9f), 0x75 }, { CCI_REG8(0x5ca0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ca1), 0x75 }, { CCI_REG8(0x5ca2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ca3), 0x75 }, { CCI_REG8(0x5ca4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ca5), 0x75 }, { CCI_REG8(0x5ca6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ca7), 0x75 }, { CCI_REG8(0x5ca8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ca9), 0x75 }, { CCI_REG8(0x5caa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cab), 0x75 }, { CCI_REG8(0x5cac), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cad), 0x75 }, { CCI_REG8(0x5cae), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5caf), 0x75 }, { CCI_REG8(0x5cb0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cb1), 0x75 }, { CCI_REG8(0x5cb2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cb3), 0x75 }, { CCI_REG8(0x5cb4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cb5), 0x75 }, { CCI_REG8(0x5cb6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cb7), 0x75 }, { CCI_REG8(0x5cb8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cb9), 0x75 }, { CCI_REG8(0x5cba), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cbb), 0x75 }, { CCI_REG8(0x5cbc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cbd), 0x75 }, { CCI_REG8(0x5cbe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cbf), 0x75 }, { CCI_REG8(0x5cc0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cc1), 0x75 }, { CCI_REG8(0x5cc2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cc3), 0x75 }, { CCI_REG8(0x5cc4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cc5), 0x75 }, { CCI_REG8(0x5cc6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cc7), 0x75 }, { CCI_REG8(0x5cc8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cc9), 0x75 }, { CCI_REG8(0x5cca), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ccb), 0x75 }, { CCI_REG8(0x5ccc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ccd), 0x75 }, { CCI_REG8(0x5cce), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ccf), 0x75 }, { CCI_REG8(0x5cd0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cd1), 0x75 }, { CCI_REG8(0x5cd2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cd3), 0x75 }, { CCI_REG8(0x5cd4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cd5), 0x75 }, { CCI_REG8(0x5cd6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cd7), 0x75 }, { CCI_REG8(0x5cd8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cd9), 0x75 }, { CCI_REG8(0x5cda), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cdb), 0x75 }, { CCI_REG8(0x5cdc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cdd), 0x75 }, { CCI_REG8(0x5cde), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cdf), 0x75 }, { CCI_REG8(0x5ce0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ce1), 0x75 }, { CCI_REG8(0x5ce2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ce3), 0x75 }, { CCI_REG8(0x5ce4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ce5), 0x75 }, { CCI_REG8(0x5ce6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ce7), 0x75 }, { CCI_REG8(0x5ce8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ce9), 0x75 }, { CCI_REG8(0x5cea), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ceb), 0x75 }, { CCI_REG8(0x5cec), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ced), 0x75 }, { CCI_REG8(0x5cee), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cef), 0x75 }, { CCI_REG8(0x5cf0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cf1), 0x75 }, { CCI_REG8(0x5cf2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cf3), 0x75 }, { CCI_REG8(0x5cf4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cf5), 0x75 }, { CCI_REG8(0x5cf6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cf7), 0x75 }, { CCI_REG8(0x5cf8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cf9), 0x75 }, { CCI_REG8(0x5cfa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cfb), 0x75 }, { CCI_REG8(0x5cfc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cfd), 0x75 }, { CCI_REG8(0x5cfe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5cff), 0x75 }, { CCI_REG8(0x5d00), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d01), 0x75 }, { CCI_REG8(0x5d02), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d03), 0x75 }, { CCI_REG8(0x5d04), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d05), 0x75 }, { CCI_REG8(0x5d06), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d07), 0x75 }, { CCI_REG8(0x5d08), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d09), 0x75 }, { CCI_REG8(0x5d0a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d0b), 0x75 }, { CCI_REG8(0x5d0c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d0d), 0x75 }, { CCI_REG8(0x5d0e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d0f), 0x75 }, { CCI_REG8(0x5d10), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d11), 0x75 }, { CCI_REG8(0x5d12), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d13), 0x75 }, { CCI_REG8(0x5d14), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d15), 0x75 }, { CCI_REG8(0x5d16), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d17), 0x75 }, { CCI_REG8(0x5d18), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d19), 0x75 }, { CCI_REG8(0x5d1a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d1b), 0x75 }, { CCI_REG8(0x5d1c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d1d), 0x75 }, { CCI_REG8(0x5d1e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d1f), 0x75 }, { CCI_REG8(0x5d20), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d21), 0x75 }, { CCI_REG8(0x5d22), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d23), 0x75 }, { CCI_REG8(0x5d24), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d25), 0x75 }, { CCI_REG8(0x5d26), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d27), 0x75 }, { CCI_REG8(0x5d28), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d29), 0x75 }, { CCI_REG8(0x5d2a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d2b), 0x75 }, { CCI_REG8(0x5d2c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d2d), 0x75 }, { CCI_REG8(0x5d2e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d2f), 0x75 }, { CCI_REG8(0x5d30), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d31), 0x75 }, { CCI_REG8(0x5d32), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d33), 0x75 }, { CCI_REG8(0x5d34), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d35), 0x75 }, { CCI_REG8(0x5d36), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d37), 0x75 }, { CCI_REG8(0x5d38), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d39), 0x75 }, { CCI_REG8(0x5d3a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d3b), 0x75 }, { CCI_REG8(0x5d3c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d3d), 0x75 }, { CCI_REG8(0x5d3e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d3f), 0x75 }, { CCI_REG8(0x5d40), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d41), 0x75 }, { CCI_REG8(0x5d42), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d43), 0x75 }, { CCI_REG8(0x5d44), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d45), 0x75 }, { CCI_REG8(0x5d46), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d47), 0x75 }, { CCI_REG8(0x5d48), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d49), 0x75 }, { CCI_REG8(0x5d4a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d4b), 0x75 }, { CCI_REG8(0x5d4c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d4d), 0x75 }, { CCI_REG8(0x5d4e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d4f), 0x75 }, { CCI_REG8(0x5d50), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d51), 0x75 }, { CCI_REG8(0x5d52), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d53), 0x75 }, { CCI_REG8(0x5d54), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d55), 0x75 }, { CCI_REG8(0x5d56), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d57), 0x75 }, { CCI_REG8(0x5d58), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d59), 0x75 }, { CCI_REG8(0x5d5a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d5b), 0x75 }, { CCI_REG8(0x5d5c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d5d), 0x75 }, { CCI_REG8(0x5d5e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d5f), 0x75 }, { CCI_REG8(0x5d60), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d61), 0x75 }, { CCI_REG8(0x5d62), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d63), 0x75 }, { CCI_REG8(0x5d64), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d65), 0x75 }, { CCI_REG8(0x5d66), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d67), 0x75 }, { CCI_REG8(0x5d68), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d69), 0x75 }, { CCI_REG8(0x5d6a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d6b), 0x75 }, { CCI_REG8(0x5d6c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d6d), 0x75 }, { CCI_REG8(0x5d6e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d6f), 0x75 }, { CCI_REG8(0x5d70), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d71), 0x75 }, { CCI_REG8(0x5d72), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d73), 0x75 }, { CCI_REG8(0x5d74), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d75), 0x75 }, { CCI_REG8(0x5d76), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d77), 0x75 }, { CCI_REG8(0x5d78), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d79), 0x75 }, { CCI_REG8(0x5d7a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d7b), 0x75 }, { CCI_REG8(0x5d7c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d7d), 0x75 }, { CCI_REG8(0x5d7e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d7f), 0x75 }, { CCI_REG8(0x5d80), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d81), 0x75 }, { CCI_REG8(0x5d82), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d83), 0x75 }, { CCI_REG8(0x5d84), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d85), 0x75 }, { CCI_REG8(0x5d86), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d87), 0x75 }, { CCI_REG8(0x5d88), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d89), 0x75 }, { CCI_REG8(0x5d8a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d8b), 0x75 }, { CCI_REG8(0x5d8c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d8d), 0x75 }, { CCI_REG8(0x5d8e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d8f), 0x75 }, { CCI_REG8(0x5d90), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d91), 0x75 }, { CCI_REG8(0x5d92), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d93), 0x75 }, { CCI_REG8(0x5d94), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d95), 0x75 }, { CCI_REG8(0x5d96), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d97), 0x75 }, { CCI_REG8(0x5d98), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d99), 0x75 }, { CCI_REG8(0x5d9a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d9b), 0x75 }, { CCI_REG8(0x5d9c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d9d), 0x75 }, { CCI_REG8(0x5d9e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5d9f), 0x75 }, { CCI_REG8(0x5da0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5da1), 0x75 }, { CCI_REG8(0x5da2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5da3), 0x75 }, { CCI_REG8(0x5da4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5da5), 0x75 }, { CCI_REG8(0x5da6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5da7), 0x75 }, { CCI_REG8(0x5da8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5da9), 0x75 }, { CCI_REG8(0x5daa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dab), 0x75 }, { CCI_REG8(0x5dac), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dad), 0x75 }, { CCI_REG8(0x5dae), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5daf), 0x75 }, { CCI_REG8(0x5db0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5db1), 0x75 }, { CCI_REG8(0x5db2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5db3), 0x75 }, { CCI_REG8(0x5db4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5db5), 0x75 }, { CCI_REG8(0x5db6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5db7), 0x75 }, { CCI_REG8(0x5db8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5db9), 0x75 }, { CCI_REG8(0x5dba), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dbb), 0x75 }, { CCI_REG8(0x5dbc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dbd), 0x75 }, { CCI_REG8(0x5dbe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dbf), 0x75 }, { CCI_REG8(0x5dc0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dc1), 0x75 }, { CCI_REG8(0x5dc2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dc3), 0x75 }, { CCI_REG8(0x5dc4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dc5), 0x75 }, { CCI_REG8(0x5dc6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dc7), 0x75 }, { CCI_REG8(0x5dc8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dc9), 0x75 }, { CCI_REG8(0x5dca), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dcb), 0x75 }, { CCI_REG8(0x5dcc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dcd), 0x75 }, { CCI_REG8(0x5dce), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dcf), 0x75 }, { CCI_REG8(0x5dd0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dd1), 0x75 }, { CCI_REG8(0x5dd2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dd3), 0x75 }, { CCI_REG8(0x5dd4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dd5), 0x75 }, { CCI_REG8(0x5dd6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dd7), 0x75 }, { CCI_REG8(0x5dd8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dd9), 0x75 }, { CCI_REG8(0x5dda), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ddb), 0x75 }, { CCI_REG8(0x5ddc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ddd), 0x75 }, { CCI_REG8(0x5dde), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ddf), 0x75 }, { CCI_REG8(0x5de0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5de1), 0x75 }, { CCI_REG8(0x5de2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5de3), 0x75 }, { CCI_REG8(0x5de4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5de5), 0x75 }, { CCI_REG8(0x5de6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5de7), 0x75 }, { CCI_REG8(0x5de8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5de9), 0x75 }, { CCI_REG8(0x5dea), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5deb), 0x75 }, { CCI_REG8(0x5dec), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ded), 0x75 }, { CCI_REG8(0x5dee), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5def), 0x75 }, { CCI_REG8(0x5df0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5df1), 0x75 }, { CCI_REG8(0x5df2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5df3), 0x75 }, { CCI_REG8(0x5df4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5df5), 0x75 }, { CCI_REG8(0x5df6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5df7), 0x75 }, { CCI_REG8(0x5df8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5df9), 0x75 }, { CCI_REG8(0x5dfa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dfb), 0x75 }, { CCI_REG8(0x5dfc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dfd), 0x75 }, { CCI_REG8(0x5dfe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5dff), 0x75 }, { CCI_REG8(0x5e00), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e01), 0x75 }, { CCI_REG8(0x5e02), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e03), 0x75 }, { CCI_REG8(0x5e04), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e05), 0x75 }, { CCI_REG8(0x5e06), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e07), 0x75 }, { CCI_REG8(0x5e08), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e09), 0x75 }, { CCI_REG8(0x5e0a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e0b), 0x75 }, { CCI_REG8(0x5e0c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e0d), 0x75 }, { CCI_REG8(0x5e0e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e0f), 0x75 }, { CCI_REG8(0x5e10), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e11), 0x75 }, { CCI_REG8(0x5e12), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e13), 0x75 }, { CCI_REG8(0x5e14), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e15), 0x75 }, { CCI_REG8(0x5e16), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e17), 0x75 }, { CCI_REG8(0x5e18), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e19), 0x75 }, { CCI_REG8(0x5e1a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e1b), 0x75 }, { CCI_REG8(0x5e1c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e1d), 0x75 }, { CCI_REG8(0x5e1e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e1f), 0x75 }, { CCI_REG8(0x5e20), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e21), 0x75 }, { CCI_REG8(0x5e22), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e23), 0x75 }, { CCI_REG8(0x5e24), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e25), 0x75 }, { CCI_REG8(0x5e26), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e27), 0x75 }, { CCI_REG8(0x5e28), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e29), 0x75 }, { CCI_REG8(0x5e2a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e2b), 0x75 }, { CCI_REG8(0x5e2c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e2d), 0x75 }, { CCI_REG8(0x5e2e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e2f), 0x75 }, { CCI_REG8(0x5e30), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e31), 0x75 }, { CCI_REG8(0x5e32), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e33), 0x75 }, { CCI_REG8(0x5e34), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e35), 0x75 }, { CCI_REG8(0x5e36), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e37), 0x75 }, { CCI_REG8(0x5e38), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e39), 0x75 }, { CCI_REG8(0x5e3a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e3b), 0x75 }, { CCI_REG8(0x5e3c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e3d), 0x75 }, { CCI_REG8(0x5e3e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e3f), 0x75 }, { CCI_REG8(0x5e40), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e41), 0x75 }, { CCI_REG8(0x5e42), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e43), 0x75 }, { CCI_REG8(0x5e44), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e45), 0x75 }, { CCI_REG8(0x5e46), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e47), 0x75 }, { CCI_REG8(0x5e48), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e49), 0x75 }, { CCI_REG8(0x5e4a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e4b), 0x75 }, { CCI_REG8(0x5e4c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e4d), 0x75 }, { CCI_REG8(0x5e4e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e4f), 0x75 }, { CCI_REG8(0x5e50), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e51), 0x75 }, { CCI_REG8(0x5e52), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e53), 0x75 }, { CCI_REG8(0x5e54), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e55), 0x75 }, { CCI_REG8(0x5e56), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e57), 0x75 }, { CCI_REG8(0x5e58), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e59), 0x75 }, { CCI_REG8(0x5e5a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e5b), 0x75 }, { CCI_REG8(0x5e5c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e5d), 0x75 }, { CCI_REG8(0x5e5e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e5f), 0x75 }, { CCI_REG8(0x5e60), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e61), 0x75 }, { CCI_REG8(0x5e62), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e63), 0x75 }, { CCI_REG8(0x5e64), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e65), 0x75 }, { CCI_REG8(0x5e66), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e67), 0x75 }, { CCI_REG8(0x5e68), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e69), 0x75 }, { CCI_REG8(0x5e6a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e6b), 0x75 }, { CCI_REG8(0x5e6c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e6d), 0x75 }, { CCI_REG8(0x5e6e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e6f), 0x75 }, { CCI_REG8(0x5e70), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e71), 0x75 }, { CCI_REG8(0x5e72), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e73), 0x75 }, { CCI_REG8(0x5e74), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e75), 0x75 }, { CCI_REG8(0x5e76), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e77), 0x75 }, { CCI_REG8(0x5e78), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e79), 0x75 }, { CCI_REG8(0x5e7a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e7b), 0x75 }, { CCI_REG8(0x5e7c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e7d), 0x75 }, { CCI_REG8(0x5e7e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e7f), 0x75 }, { CCI_REG8(0x5e80), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e81), 0x75 }, { CCI_REG8(0x5e82), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e83), 0x75 }, { CCI_REG8(0x5e84), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e85), 0x75 }, { CCI_REG8(0x5e86), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e87), 0x75 }, { CCI_REG8(0x5e88), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e89), 0x75 }, { CCI_REG8(0x5e8a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e8b), 0x75 }, { CCI_REG8(0x5e8c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e8d), 0x75 }, { CCI_REG8(0x5e8e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e8f), 0x75 }, { CCI_REG8(0x5e90), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e91), 0x75 }, { CCI_REG8(0x5e92), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e93), 0x75 }, { CCI_REG8(0x5e94), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e95), 0x75 }, { CCI_REG8(0x5e96), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e97), 0x75 }, { CCI_REG8(0x5e98), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e99), 0x75 }, { CCI_REG8(0x5e9a), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e9b), 0x75 }, { CCI_REG8(0x5e9c), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e9d), 0x75 }, { CCI_REG8(0x5e9e), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5e9f), 0x75 }, { CCI_REG8(0x5ea0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ea1), 0x75 }, { CCI_REG8(0x5ea2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ea3), 0x75 }, { CCI_REG8(0x5ea4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ea5), 0x75 }, { CCI_REG8(0x5ea6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ea7), 0x75 }, { CCI_REG8(0x5ea8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ea9), 0x75 }, { CCI_REG8(0x5eaa), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eab), 0x75 }, { CCI_REG8(0x5eac), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ead), 0x75 }, { CCI_REG8(0x5eae), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eaf), 0x75 }, { CCI_REG8(0x5eb0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eb1), 0x75 }, { CCI_REG8(0x5eb2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eb3), 0x75 }, { CCI_REG8(0x5eb4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eb5), 0x75 }, { CCI_REG8(0x5eb6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eb7), 0x75 }, { CCI_REG8(0x5eb8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5eb9), 0x75 }, { CCI_REG8(0x5eba), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ebb), 0x75 }, { CCI_REG8(0x5ebc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ebd), 0x75 }, { CCI_REG8(0x5ebe), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ebf), 0x75 }, { CCI_REG8(0x5ec0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ec1), 0x75 }, { CCI_REG8(0x5ec2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ec3), 0x75 }, { CCI_REG8(0x5ec4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ec5), 0x75 }, { CCI_REG8(0x5ec6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ec7), 0x75 }, { CCI_REG8(0x5ec8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ec9), 0x75 }, { CCI_REG8(0x5eca), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ecb), 0x75 }, { CCI_REG8(0x5ecc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ecd), 0x75 }, { CCI_REG8(0x5ece), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ecf), 0x75 }, { CCI_REG8(0x5ed0), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ed1), 0x75 }, { CCI_REG8(0x5ed2), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ed3), 0x75 }, { CCI_REG8(0x5ed4), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ed5), 0x75 }, { CCI_REG8(0x5ed6), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ed7), 0x75 }, { CCI_REG8(0x5ed8), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5ed9), 0x75 }, { CCI_REG8(0x5eda), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5edb), 0x75 }, { CCI_REG8(0x5edc), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5edd), 0x75 }, { CCI_REG8(0x5ede), 0x75 },</div><div class='add'>+	{ CCI_REG8(0x5edf), 0x75 }, { CCI_REG8(0xfff9), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x1570), 0x00 }, { CCI_REG8(0x15d0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x15a0), 0x02 }, { CCI_REG8(0x15a1), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x15a2), 0x02 }, { CCI_REG8(0x15a3), 0x76 },</div><div class='add'>+	{ CCI_REG8(0x15a4), 0x03 }, { CCI_REG8(0x15a5), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x15a6), 0x00 }, { CCI_REG8(0x15a7), 0x60 },</div><div class='add'>+	{ CCI_REG8(0x15a8), 0x01 }, { CCI_REG8(0x15a9), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x15aa), 0x02 }, { CCI_REG8(0x15ab), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x1600), 0x02 }, { CCI_REG8(0x1601), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x1602), 0x02 }, { CCI_REG8(0x1603), 0x76 },</div><div class='add'>+	{ CCI_REG8(0x1604), 0x03 }, { CCI_REG8(0x1605), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x1606), 0x00 }, { CCI_REG8(0x1607), 0x60 },</div><div class='add'>+	{ CCI_REG8(0x1608), 0x01 }, { CCI_REG8(0x1609), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x160a), 0x02 }, { CCI_REG8(0x160b), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x1633), 0x03 }, { CCI_REG8(0x1634), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x163c), 0x3a }, { CCI_REG8(0x163d), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x1648), 0x32 }, { CCI_REG8(0x1658), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x1659), 0x01 }, { CCI_REG8(0x165f), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x1677), 0x01 }, { CCI_REG8(0x1690), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x1691), 0x00 }, { CCI_REG8(0x1692), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x1693), 0x00 }, { CCI_REG8(0x1694), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x1695), 0x14 }, { CCI_REG8(0x1696), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x1697), 0x0e }, { CCI_REG8(0x1730), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x1732), 0x00 }, { CCI_REG8(0x1733), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x1734), 0x01 }, { CCI_REG8(0x1735), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x1748), 0x01 }, { CCI_REG8(0xfff9), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x5000), 0xff }, { CCI_REG8(0x5001), 0x3d },</div><div class='add'>+	{ CCI_REG8(0x5002), 0xf5 }, { CCI_REG8(0x5004), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x5006), 0x04 }, { CCI_REG8(0x5061), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x5063), 0x20 }, { CCI_REG8(0x5064), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5065), 0x00 }, { CCI_REG8(0x5066), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5067), 0x00 }, { CCI_REG8(0x5068), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x5069), 0x10 }, { CCI_REG8(0x506a), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x506b), 0x04 }, { CCI_REG8(0x506c), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x506d), 0x0c }, { CCI_REG8(0x506e), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x506f), 0x04 }, { CCI_REG8(0x5070), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x5071), 0x14 }, { CCI_REG8(0x5072), 0x1c },</div><div class='add'>+	{ CCI_REG8(0x5073), 0x01 }, { CCI_REG8(0x5074), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x5075), 0xbe }, { CCI_REG8(0x5083), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5114), 0x03 }, { CCI_REG8(0x51b0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b8), 0x00 }, { CCI_REG8(0x51b9), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x51ba), 0x00 }, { CCI_REG8(0x51bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51d2), 0xff }, { CCI_REG8(0x51d3), 0x1c },</div><div class='add'>+	{ CCI_REG8(0x5250), 0x34 }, { CCI_REG8(0x5251), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x525b), 0x00 }, { CCI_REG8(0x525d), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x4b },</div><div class='add'>+	{ CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5290), 0x00 }, { CCI_REG8(0x5291), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5292), 0x00 }, { CCI_REG8(0x5293), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5294), 0x00 }, { CCI_REG8(0x5295), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5296), 0x00 }, { CCI_REG8(0x5297), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5298), 0x00 }, { CCI_REG8(0x5299), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x529a), 0x01 }, { CCI_REG8(0x529b), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x529c), 0x01 }, { CCI_REG8(0x529d), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x529e), 0x00 }, { CCI_REG8(0x529f), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52a0), 0x00 }, { CCI_REG8(0x52a1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52a2), 0x01 }, { CCI_REG8(0x52a3), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52a4), 0x01 }, { CCI_REG8(0x52a5), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52a6), 0x00 }, { CCI_REG8(0x52a7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52a8), 0x00 }, { CCI_REG8(0x52a9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52aa), 0x00 }, { CCI_REG8(0x52ab), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52ac), 0x00 }, { CCI_REG8(0x52ad), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52ae), 0x00 }, { CCI_REG8(0x52af), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52b0), 0x00 }, { CCI_REG8(0x52b1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52b2), 0x00 }, { CCI_REG8(0x52b3), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52b4), 0x00 }, { CCI_REG8(0x52b5), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52b6), 0x00 }, { CCI_REG8(0x52b7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52b8), 0x00 }, { CCI_REG8(0x52b9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52ba), 0x01 }, { CCI_REG8(0x52bb), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52bc), 0x01 }, { CCI_REG8(0x52bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52be), 0x00 }, { CCI_REG8(0x52bf), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52c0), 0x00 }, { CCI_REG8(0x52c1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52c2), 0x01 }, { CCI_REG8(0x52c3), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52c4), 0x01 }, { CCI_REG8(0x52c5), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x52c6), 0x00 }, { CCI_REG8(0x52c7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52c8), 0x00 }, { CCI_REG8(0x52c9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52ca), 0x00 }, { CCI_REG8(0x52cb), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52cc), 0x00 }, { CCI_REG8(0x52cd), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52ce), 0x00 }, { CCI_REG8(0x52cf), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x52f0), 0x04 }, { CCI_REG8(0x52f1), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x52f2), 0x02 }, { CCI_REG8(0x52f3), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x52f4), 0x08 }, { CCI_REG8(0x52f5), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x52f6), 0x06 }, { CCI_REG8(0x52f7), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x52f8), 0x0c }, { CCI_REG8(0x52f9), 0x0b },</div><div class='add'>+	{ CCI_REG8(0x52fa), 0x0a }, { CCI_REG8(0x52fb), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x52fc), 0x10 }, { CCI_REG8(0x52fd), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x52fe), 0x0e }, { CCI_REG8(0x52ff), 0x0d },</div><div class='add'>+	{ CCI_REG8(0x5300), 0x14 }, { CCI_REG8(0x5301), 0x13 },</div><div class='add'>+	{ CCI_REG8(0x5302), 0x12 }, { CCI_REG8(0x5303), 0x11 },</div><div class='add'>+	{ CCI_REG8(0x5304), 0x18 }, { CCI_REG8(0x5305), 0x17 },</div><div class='add'>+	{ CCI_REG8(0x5306), 0x16 }, { CCI_REG8(0x5307), 0x15 },</div><div class='add'>+	{ CCI_REG8(0x5308), 0x1c }, { CCI_REG8(0x5309), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x530a), 0x1a }, { CCI_REG8(0x530b), 0x19 },</div><div class='add'>+	{ CCI_REG8(0x530c), 0x20 }, { CCI_REG8(0x530d), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x530e), 0x1e }, { CCI_REG8(0x530f), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x5310), 0x03 }, { CCI_REG8(0x5311), 0xe8 },</div><div class='add'>+	{ CCI_REG8(0x5331), 0x0a }, { CCI_REG8(0x5332), 0x43 },</div><div class='add'>+	{ CCI_REG8(0x5333), 0x45 }, { CCI_REG8(0x5353), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x5354), 0x00 }, { CCI_REG8(0x5414), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x54b0), 0x10 }, { CCI_REG8(0x54b3), 0x0e },</div><div class='add'>+	{ CCI_REG8(0x54b5), 0x02 }, { CCI_REG8(0x54b6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54b7), 0x00 }, { CCI_REG8(0x54b8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54ba), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54bb), 0x10 }, { CCI_REG8(0x54bc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54bd), 0x00 }, { CCI_REG8(0x54d2), 0xff },</div><div class='add'>+	{ CCI_REG8(0x54d3), 0x1c }, { CCI_REG8(0x5510), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x5511), 0xe8 }, { CCI_REG8(0x5550), 0x6c },</div><div class='add'>+	{ CCI_REG8(0x5551), 0x00 }, { CCI_REG8(0x557a), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x557b), 0x38 }, { CCI_REG8(0x557c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x557d), 0x4b }, { CCI_REG8(0x5590), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5591), 0x50 }, { CCI_REG8(0x5592), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5593), 0x50 }, { CCI_REG8(0x5594), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5595), 0x50 }, { CCI_REG8(0x5596), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5597), 0x50 }, { CCI_REG8(0x5598), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5599), 0x50 }, { CCI_REG8(0x559a), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x559b), 0x00 }, { CCI_REG8(0x559c), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x559d), 0x00 }, { CCI_REG8(0x559e), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x559f), 0x50 }, { CCI_REG8(0x55a0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55a1), 0x50 }, { CCI_REG8(0x55a2), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55a3), 0x00 }, { CCI_REG8(0x55a4), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55a5), 0x00 }, { CCI_REG8(0x55a6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55a7), 0x50 }, { CCI_REG8(0x55a8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55a9), 0x50 }, { CCI_REG8(0x55aa), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55ab), 0x50 }, { CCI_REG8(0x55ac), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55ad), 0x50 }, { CCI_REG8(0x55ae), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55af), 0x50 }, { CCI_REG8(0x55b0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55b1), 0x50 }, { CCI_REG8(0x55b2), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55b3), 0x50 }, { CCI_REG8(0x55b4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55b5), 0x50 }, { CCI_REG8(0x55b6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55b7), 0x50 }, { CCI_REG8(0x55b8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55b9), 0x50 }, { CCI_REG8(0x55ba), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55bb), 0x00 }, { CCI_REG8(0x55bc), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55bd), 0x00 }, { CCI_REG8(0x55be), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55bf), 0x50 }, { CCI_REG8(0x55c0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55c1), 0x50 }, { CCI_REG8(0x55c2), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55c3), 0x00 }, { CCI_REG8(0x55c4), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x55c5), 0x00 }, { CCI_REG8(0x55c6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55c7), 0x50 }, { CCI_REG8(0x55c8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55c9), 0x50 }, { CCI_REG8(0x55ca), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55cb), 0x50 }, { CCI_REG8(0x55cc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55cd), 0x50 }, { CCI_REG8(0x55ce), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x55cf), 0x50 }, { CCI_REG8(0x55f0), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x55f1), 0x03 }, { CCI_REG8(0x55f2), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x55f3), 0x01 }, { CCI_REG8(0x55f4), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x55f5), 0x07 }, { CCI_REG8(0x55f6), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x55f7), 0x05 }, { CCI_REG8(0x55f8), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x55f9), 0x0b }, { CCI_REG8(0x55fa), 0x0a },</div><div class='add'>+	{ CCI_REG8(0x55fb), 0x09 }, { CCI_REG8(0x55fc), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x55fd), 0x0f }, { CCI_REG8(0x55fe), 0x0e },</div><div class='add'>+	{ CCI_REG8(0x55ff), 0x0d }, { CCI_REG8(0x5600), 0x14 },</div><div class='add'>+	{ CCI_REG8(0x5601), 0x13 }, { CCI_REG8(0x5602), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x5603), 0x11 }, { CCI_REG8(0x5604), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x5605), 0x17 }, { CCI_REG8(0x5606), 0x16 },</div><div class='add'>+	{ CCI_REG8(0x5607), 0x15 }, { CCI_REG8(0x5608), 0x1c },</div><div class='add'>+	{ CCI_REG8(0x5609), 0x1b }, { CCI_REG8(0x560a), 0x1a },</div><div class='add'>+	{ CCI_REG8(0x560b), 0x19 }, { CCI_REG8(0x560c), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x560d), 0x1f }, { CCI_REG8(0x560e), 0x1e },</div><div class='add'>+	{ CCI_REG8(0x560f), 0x1d }, { CCI_REG8(0x5631), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x5632), 0x42 }, { CCI_REG8(0x5633), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5653), 0x09 }, { CCI_REG8(0x5654), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5714), 0x03 }, { CCI_REG8(0x57b0), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x57b3), 0x0e }, { CCI_REG8(0x57b5), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x57b6), 0x00 }, { CCI_REG8(0x57b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57b8), 0x00 }, { CCI_REG8(0x57b9), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x57ba), 0x00 }, { CCI_REG8(0x57bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x57bc), 0x00 }, { CCI_REG8(0x57bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57d2), 0xff }, { CCI_REG8(0x57d3), 0x1c },</div><div class='add'>+	{ CCI_REG8(0x5810), 0x03 }, { CCI_REG8(0x5811), 0xe8 },</div><div class='add'>+	{ CCI_REG8(0x5850), 0x6c }, { CCI_REG8(0x5851), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x587a), 0x00 }, { CCI_REG8(0x587b), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x587c), 0x00 }, { CCI_REG8(0x587d), 0x4b },</div><div class='add'>+	{ CCI_REG8(0x5890), 0x00 }, { CCI_REG8(0x5891), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5892), 0x00 }, { CCI_REG8(0x5893), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5894), 0x00 }, { CCI_REG8(0x5895), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5896), 0x00 }, { CCI_REG8(0x5897), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x5898), 0x00 }, { CCI_REG8(0x5899), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x589a), 0x01 }, { CCI_REG8(0x589b), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x589c), 0x01 }, { CCI_REG8(0x589d), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x589e), 0x00 }, { CCI_REG8(0x589f), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58a0), 0x00 }, { CCI_REG8(0x58a1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58a2), 0x01 }, { CCI_REG8(0x58a3), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58a4), 0x01 }, { CCI_REG8(0x58a5), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58a6), 0x00 }, { CCI_REG8(0x58a7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58a8), 0x00 }, { CCI_REG8(0x58a9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58aa), 0x00 }, { CCI_REG8(0x58ab), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58ac), 0x00 }, { CCI_REG8(0x58ad), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58ae), 0x00 }, { CCI_REG8(0x58af), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58b0), 0x00 }, { CCI_REG8(0x58b1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58b2), 0x00 }, { CCI_REG8(0x58b3), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58b4), 0x00 }, { CCI_REG8(0x58b5), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58b6), 0x00 }, { CCI_REG8(0x58b7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58b8), 0x00 }, { CCI_REG8(0x58b9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58ba), 0x01 }, { CCI_REG8(0x58bb), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58bc), 0x01 }, { CCI_REG8(0x58bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58be), 0x00 }, { CCI_REG8(0x58bf), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58c0), 0x00 }, { CCI_REG8(0x58c1), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58c2), 0x01 }, { CCI_REG8(0x58c3), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58c4), 0x01 }, { CCI_REG8(0x58c5), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x58c6), 0x00 }, { CCI_REG8(0x58c7), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58c8), 0x00 }, { CCI_REG8(0x58c9), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58ca), 0x00 }, { CCI_REG8(0x58cb), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58cc), 0x00 }, { CCI_REG8(0x58cd), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58ce), 0x00 }, { CCI_REG8(0x58cf), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x58f0), 0x04 }, { CCI_REG8(0x58f1), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x58f2), 0x02 }, { CCI_REG8(0x58f3), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x58f4), 0x08 }, { CCI_REG8(0x58f5), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x58f6), 0x06 }, { CCI_REG8(0x58f7), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x58f8), 0x0c }, { CCI_REG8(0x58f9), 0x0b },</div><div class='add'>+	{ CCI_REG8(0x58fa), 0x0a }, { CCI_REG8(0x58fb), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x58fc), 0x10 }, { CCI_REG8(0x58fd), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x58fe), 0x0e }, { CCI_REG8(0x58ff), 0x0d },</div><div class='add'>+	{ CCI_REG8(0x5900), 0x14 }, { CCI_REG8(0x5901), 0x13 },</div><div class='add'>+	{ CCI_REG8(0x5902), 0x12 }, { CCI_REG8(0x5903), 0x11 },</div><div class='add'>+	{ CCI_REG8(0x5904), 0x18 }, { CCI_REG8(0x5905), 0x17 },</div><div class='add'>+	{ CCI_REG8(0x5906), 0x16 }, { CCI_REG8(0x5907), 0x15 },</div><div class='add'>+	{ CCI_REG8(0x5908), 0x1c }, { CCI_REG8(0x5909), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x590a), 0x1a }, { CCI_REG8(0x590b), 0x19 },</div><div class='add'>+	{ CCI_REG8(0x590c), 0x20 }, { CCI_REG8(0x590d), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x590e), 0x1e }, { CCI_REG8(0x590f), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x5931), 0x02 }, { CCI_REG8(0x5932), 0x42 },</div><div class='add'>+	{ CCI_REG8(0x5933), 0x24 }, { CCI_REG8(0x5953), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x5954), 0x00 }, { CCI_REG8(0x5989), 0x84 },</div><div class='add'>+	{ CCI_REG8(0x59c3), 0x04 }, { CCI_REG8(0x59c4), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x59c5), 0x40 }, { CCI_REG8(0x59c6), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x59c7), 0x40 }, { CCI_REG8(0x5a02), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x5f00), 0x29 }, { CCI_REG8(0x5f2d), 0x28 },</div><div class='add'>+	{ CCI_REG8(0x5f2e), 0x28 }, { CCI_REG8(0x6801), 0x11 },</div><div class='add'>+	{ CCI_REG8(0x6802), 0x3f }, { CCI_REG8(0x6803), 0xe7 },</div><div class='add'>+	{ CCI_REG8(0x6825), 0x0f }, { CCI_REG8(0x6826), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x6827), 0x00 }, { CCI_REG8(0x6829), 0x16 },</div><div class='add'>+	{ CCI_REG8(0x682b), 0xb3 }, { CCI_REG8(0x682c), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x6832), 0xff }, { CCI_REG8(0x6833), 0xff },</div><div class='add'>+	{ CCI_REG8(0x6898), 0x80 }, { CCI_REG8(0x6899), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x689b), 0x40 }, { CCI_REG8(0x689c), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x689d), 0x20 }, { CCI_REG8(0x689e), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x689f), 0x60 }, { CCI_REG8(0x68a0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x68a4), 0x40 }, { CCI_REG8(0x68a5), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x68a6), 0x00 }, { CCI_REG8(0x68b6), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x68b7), 0x80 }, { CCI_REG8(0x68b8), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x68bc), 0x80 }, { CCI_REG8(0x68bd), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x68be), 0x80 }, { CCI_REG8(0x68bf), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x68c2), 0x80 }, { CCI_REG8(0x68c3), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x68c4), 0x60 }, { CCI_REG8(0x68c5), 0x30 },</div><div class='add'>+	{ CCI_REG8(0x6918), 0x80 }, { CCI_REG8(0x6919), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x691b), 0x40 }, { CCI_REG8(0x691c), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x691d), 0x20 }, { CCI_REG8(0x691e), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x691f), 0x60 }, { CCI_REG8(0x6920), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x6924), 0x40 }, { CCI_REG8(0x6925), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x6926), 0x00 }, { CCI_REG8(0x6936), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x6937), 0x40 }, { CCI_REG8(0x6938), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x6939), 0x20 }, { CCI_REG8(0x693a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x693b), 0x10 }, { CCI_REG8(0x693c), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x693d), 0x20 }, { CCI_REG8(0x693e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x693f), 0x10 }, { CCI_REG8(0x6940), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x6941), 0x00 }, { CCI_REG8(0x6942), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x6943), 0x08 }, { CCI_REG8(0x6944), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x69c2), 0x07 }, { CCI_REG8(0x6a20), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x6a23), 0x10 }, { CCI_REG8(0x6a26), 0x3d },</div><div class='add'>+	{ CCI_REG8(0x6a27), 0x3e }, { CCI_REG8(0x6a38), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x6a39), 0x20 }, { CCI_REG8(0x6a3a), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x6a3b), 0x84 }, { CCI_REG8(0x6a3e), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x6a3f), 0x20 }, { CCI_REG8(0x6a47), 0x3b },</div><div class='add'>+	{ CCI_REG8(0x6a63), 0x04 }, { CCI_REG8(0x6a65), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x6a67), 0x0f }, { CCI_REG8(0x6b22), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x6b23), 0xc2 }, { CCI_REG8(0x6b2f), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x6b60), 0x1f }, { CCI_REG8(0x6bd2), 0x5a },</div><div class='add'>+	{ CCI_REG8(0x6c20), 0x50 }, { CCI_REG8(0x6c60), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x6c61), 0x06 }, { CCI_REG8(0x7318), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x7319), 0x01 }, { CCI_REG8(0x731a), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x731b), 0x01 }, { CCI_REG8(0x731c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x731d), 0x00 }, { CCI_REG8(0x731e), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x731f), 0x01 }, { CCI_REG8(0x7320), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x7321), 0x00 }, { CCI_REG8(0x7322), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x7323), 0x00 }, { CCI_REG8(0x7324), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x7325), 0x00 }, { CCI_REG8(0x7326), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x7327), 0x00 }, { CCI_REG8(0x7600), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7601), 0x00 }, { CCI_REG8(0x7602), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7603), 0x00 }, { CCI_REG8(0x7604), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7605), 0x00 }, { CCI_REG8(0x7606), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7607), 0x00 }, { CCI_REG8(0x7608), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7609), 0x00 }, { CCI_REG8(0x760a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x760b), 0x00 }, { CCI_REG8(0x760c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x760d), 0x00 }, { CCI_REG8(0x760e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x760f), 0x00 }, { CCI_REG8(0x7610), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7611), 0x00 }, { CCI_REG8(0x7612), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7613), 0x00 }, { CCI_REG8(0x7614), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7615), 0x00 }, { CCI_REG8(0x7616), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7617), 0x00 }, { CCI_REG8(0x7618), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7619), 0x00 }, { CCI_REG8(0x761a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x761b), 0x00 }, { CCI_REG8(0x761c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x761d), 0x00 }, { CCI_REG8(0x761e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x761f), 0x00 }, { CCI_REG8(0x7620), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7621), 0x00 }, { CCI_REG8(0x7622), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7623), 0x00 }, { CCI_REG8(0x7624), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7625), 0x00 }, { CCI_REG8(0x7626), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7627), 0x00 }, { CCI_REG8(0x7628), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7629), 0x00 }, { CCI_REG8(0x762a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x762b), 0x00 }, { CCI_REG8(0x762c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x762d), 0x00 }, { CCI_REG8(0x762e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x762f), 0x00 }, { CCI_REG8(0x7630), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7631), 0x00 }, { CCI_REG8(0x7632), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7633), 0x00 }, { CCI_REG8(0x7634), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7635), 0x00 }, { CCI_REG8(0x7636), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7637), 0x00 }, { CCI_REG8(0x7638), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7639), 0x00 }, { CCI_REG8(0x763a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x763b), 0x00 }, { CCI_REG8(0x763c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x763d), 0x00 }, { CCI_REG8(0x763e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x763f), 0x00 }, { CCI_REG8(0x7640), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7641), 0x00 }, { CCI_REG8(0x7642), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7643), 0x00 }, { CCI_REG8(0x7644), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7645), 0x00 }, { CCI_REG8(0x7646), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7647), 0x00 }, { CCI_REG8(0x7648), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7649), 0x00 }, { CCI_REG8(0x764a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x764b), 0x00 }, { CCI_REG8(0x764c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x764d), 0x00 }, { CCI_REG8(0x764e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x764f), 0x00 }, { CCI_REG8(0x7650), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7651), 0x00 }, { CCI_REG8(0x7652), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7653), 0x00 }, { CCI_REG8(0x7654), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7655), 0x00 }, { CCI_REG8(0x7656), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7657), 0x00 }, { CCI_REG8(0x7658), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7659), 0x00 }, { CCI_REG8(0x765a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x765b), 0x00 }, { CCI_REG8(0x765c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x765d), 0x00 }, { CCI_REG8(0x765e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x765f), 0x00 }, { CCI_REG8(0x7660), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7661), 0x00 }, { CCI_REG8(0x7662), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7663), 0x00 }, { CCI_REG8(0x7664), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7665), 0x00 }, { CCI_REG8(0x7666), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7667), 0x00 }, { CCI_REG8(0x7668), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7669), 0x00 }, { CCI_REG8(0x766a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x766b), 0x00 }, { CCI_REG8(0x766c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x766d), 0x00 }, { CCI_REG8(0x766e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x766f), 0x00 }, { CCI_REG8(0x7670), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7671), 0x00 }, { CCI_REG8(0x7672), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7673), 0x00 }, { CCI_REG8(0x7674), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7675), 0x00 }, { CCI_REG8(0x7676), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7677), 0x00 }, { CCI_REG8(0x7678), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7679), 0x00 }, { CCI_REG8(0x767a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x767b), 0x00 }, { CCI_REG8(0x767c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x767d), 0x00 }, { CCI_REG8(0x767e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x767f), 0x00 }, { CCI_REG8(0x7680), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7681), 0x00 }, { CCI_REG8(0x7682), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7683), 0x00 }, { CCI_REG8(0x7684), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7685), 0x00 }, { CCI_REG8(0x7686), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7687), 0x00 }, { CCI_REG8(0x7688), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7689), 0x00 }, { CCI_REG8(0x768a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x768b), 0x00 }, { CCI_REG8(0x768c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x768d), 0x00 }, { CCI_REG8(0x768e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x768f), 0x00 }, { CCI_REG8(0x7690), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7691), 0x00 }, { CCI_REG8(0x7692), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7693), 0x00 }, { CCI_REG8(0x7694), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7695), 0x00 }, { CCI_REG8(0x7696), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7697), 0x00 }, { CCI_REG8(0x7698), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7699), 0x00 }, { CCI_REG8(0x769a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x769b), 0x00 }, { CCI_REG8(0x769c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x769d), 0x00 }, { CCI_REG8(0x769e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x769f), 0x00 }, { CCI_REG8(0x76a0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76a1), 0x00 }, { CCI_REG8(0x76a2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76a3), 0x00 }, { CCI_REG8(0x76a4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76a5), 0x00 }, { CCI_REG8(0x76a6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76a7), 0x00 }, { CCI_REG8(0x76a8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76a9), 0x00 }, { CCI_REG8(0x76aa), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76ab), 0x00 }, { CCI_REG8(0x76ac), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76ad), 0x00 }, { CCI_REG8(0x76ae), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76af), 0x00 }, { CCI_REG8(0x76b0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76b1), 0x00 }, { CCI_REG8(0x76b2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76b3), 0x00 }, { CCI_REG8(0x76b4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76b5), 0x00 }, { CCI_REG8(0x76b6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76b7), 0x00 }, { CCI_REG8(0x76b8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76b9), 0x00 }, { CCI_REG8(0x76ba), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76bb), 0x00 }, { CCI_REG8(0x76bc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76bd), 0x00 }, { CCI_REG8(0x76be), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76bf), 0x00 }, { CCI_REG8(0x76c0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76c1), 0x00 }, { CCI_REG8(0x76c2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76c3), 0x00 }, { CCI_REG8(0x76c4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76c5), 0x00 }, { CCI_REG8(0x76c6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76c7), 0x00 }, { CCI_REG8(0x76c8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76c9), 0x00 }, { CCI_REG8(0x76ca), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76cb), 0x00 }, { CCI_REG8(0x76cc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76cd), 0x00 }, { CCI_REG8(0x76ce), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76cf), 0x00 }, { CCI_REG8(0x76d0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76d1), 0x00 }, { CCI_REG8(0x76d2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76d3), 0x00 }, { CCI_REG8(0x76d4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76d5), 0x00 }, { CCI_REG8(0x76d6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76d7), 0x00 }, { CCI_REG8(0x76d8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76d9), 0x00 }, { CCI_REG8(0x76da), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76db), 0x00 }, { CCI_REG8(0x76dc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76dd), 0x00 }, { CCI_REG8(0x76de), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76df), 0x00 }, { CCI_REG8(0x76e0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76e1), 0x00 }, { CCI_REG8(0x76e2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76e3), 0x00 }, { CCI_REG8(0x76e4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76e5), 0x00 }, { CCI_REG8(0x76e6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76e7), 0x00 }, { CCI_REG8(0x76e8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76e9), 0x00 }, { CCI_REG8(0x76ea), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76eb), 0x00 }, { CCI_REG8(0x76ec), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76ed), 0x00 }, { CCI_REG8(0x76ee), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76ef), 0x00 }, { CCI_REG8(0x76f0), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76f1), 0x00 }, { CCI_REG8(0x76f2), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76f3), 0x00 }, { CCI_REG8(0x76f4), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76f5), 0x00 }, { CCI_REG8(0x76f6), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76f7), 0x00 }, { CCI_REG8(0x76f8), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76f9), 0x00 }, { CCI_REG8(0x76fa), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76fb), 0x00 }, { CCI_REG8(0x76fc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x76fd), 0x00 }, { CCI_REG8(0x76fe), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x76ff), 0x00 }, { CCI_REG8(0x7700), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7701), 0x00 }, { CCI_REG8(0x7702), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7703), 0x00 }, { CCI_REG8(0x7704), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7705), 0x00 }, { CCI_REG8(0x7706), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7707), 0x00 }, { CCI_REG8(0x7708), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7709), 0x00 }, { CCI_REG8(0x770a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x770b), 0x00 }, { CCI_REG8(0x770c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x770d), 0x00 }, { CCI_REG8(0x770e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x770f), 0x00 }, { CCI_REG8(0x7710), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7711), 0x00 }, { CCI_REG8(0x7712), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7713), 0x00 }, { CCI_REG8(0x7714), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7715), 0x00 }, { CCI_REG8(0x7716), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7717), 0x00 }, { CCI_REG8(0x7718), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7719), 0x00 }, { CCI_REG8(0x771a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x771b), 0x00 }, { CCI_REG8(0x771c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x771d), 0x00 }, { CCI_REG8(0x771e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x771f), 0x00 }, { CCI_REG8(0x7720), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7721), 0x00 }, { CCI_REG8(0x7722), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7723), 0x00 }, { CCI_REG8(0x7724), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7725), 0x00 }, { CCI_REG8(0x7726), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7727), 0x00 }, { CCI_REG8(0x7728), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7729), 0x00 }, { CCI_REG8(0x772a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x772b), 0x00 }, { CCI_REG8(0x772c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x772d), 0x00 }, { CCI_REG8(0x772e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x772f), 0x00 }, { CCI_REG8(0x7730), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7731), 0x00 }, { CCI_REG8(0x7732), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7733), 0x00 }, { CCI_REG8(0x7734), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7735), 0x00 }, { CCI_REG8(0x7736), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7737), 0x00 }, { CCI_REG8(0x7738), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7739), 0x00 }, { CCI_REG8(0x773a), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x773b), 0x00 }, { CCI_REG8(0x773c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x773d), 0x00 }, { CCI_REG8(0x773e), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x773f), 0x00 }, { CCI_REG8(0x7740), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x7741), 0x00 }, { CCI_REG8(0x7742), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x7743), 0x00 }, { CCI_REG8(0x3421), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x3632), 0x99 },</div><div class='add'>+	{ CCI_REG8(0xc518), 0x1f }, { CCI_REG8(0xc519), 0x1f },</div><div class='add'>+	{ CCI_REG8(0xc51a), 0x1f }, { CCI_REG8(0xc51b), 0x1f },</div><div class='add'>+	{ CCI_REG8(0xc51c), 0x1f }, { CCI_REG8(0xc51d), 0x1f },</div><div class='add'>+	{ CCI_REG8(0xc51e), 0x1f }, { CCI_REG8(0xc51f), 0x1f },</div><div class='add'>+	{ CCI_REG8(0xc520), 0x1f }, { CCI_REG8(0xc521), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3615), 0xc5 },</div><div class='add'>+	{ CCI_REG8(0xc4c1), 0x02 }, { CCI_REG8(0xc4c2), 0x02 },</div><div class='add'>+	{ CCI_REG8(0xc4c3), 0x03 }, { CCI_REG8(0xc4c4), 0x03 },</div><div class='add'>+	{ CCI_REG8(0xc4f6), 0x0a }, { CCI_REG8(0xc4f7), 0x0a },</div><div class='add'>+	{ CCI_REG8(0xc4f8), 0x0a }, { CCI_REG8(0xc4f9), 0x0a },</div><div class='add'>+	{ CCI_REG8(0xc4fa), 0x0a }, { CCI_REG8(0xc4c6), 0x0a },</div><div class='add'>+	{ CCI_REG8(0xc4c7), 0x0a }, { CCI_REG8(0xc4c8), 0x0a },</div><div class='add'>+	{ CCI_REG8(0xc4c9), 0x0a }, { CCI_REG8(0xc4ca), 0x14 },</div><div class='add'>+	{ CCI_REG8(0xc4cb), 0x14 }, { CCI_REG8(0xc4cc), 0x14 },</div><div class='add'>+	{ CCI_REG8(0xc4cd), 0x14 }, { CCI_REG8(0x3b92), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x3b93), 0x05 }, { CCI_REG8(0x3b94), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x3b95), 0x05 }, { CCI_REG8(0x3623), 0x10 },</div><div class='add'>+	{ CCI_REG8(0xc522), 0x18 }, { CCI_REG8(0xc523), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc524), 0x0e }, { CCI_REG8(0xc525), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc526), 0x18 }, { CCI_REG8(0xc527), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc528), 0x0c }, { CCI_REG8(0xc529), 0x08 },</div><div class='add'>+	{ CCI_REG8(0xc52a), 0x18 }, { CCI_REG8(0xc52b), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc52c), 0x0e }, { CCI_REG8(0xc52d), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc52e), 0x18 }, { CCI_REG8(0xc52f), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc530), 0x0e }, { CCI_REG8(0xc531), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc532), 0x18 }, { CCI_REG8(0xc533), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc534), 0x0e }, { CCI_REG8(0xc535), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc536), 0x18 }, { CCI_REG8(0xc537), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc538), 0x0e }, { CCI_REG8(0xc539), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc53a), 0x18 }, { CCI_REG8(0xc53b), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc53c), 0x0c }, { CCI_REG8(0xc53d), 0x08 },</div><div class='add'>+	{ CCI_REG8(0xc53e), 0x18 }, { CCI_REG8(0xc53f), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc540), 0x0e }, { CCI_REG8(0xc541), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc542), 0x18 }, { CCI_REG8(0xc543), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc544), 0x0e }, { CCI_REG8(0xc545), 0x0b },</div><div class='add'>+	{ CCI_REG8(0xc546), 0x18 }, { CCI_REG8(0xc547), 0x12 },</div><div class='add'>+	{ CCI_REG8(0xc548), 0x0e }, { CCI_REG8(0xc549), 0x0b },</div><div class='add'>+	{ CCI_REG8(0x3701), 0x18 }, { CCI_REG8(0x3702), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3708), 0x26 },</div><div class='add'>+	{ CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a1d), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x3a1e), 0x18 }, { CCI_REG8(0x3a21), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x3a22), 0x18 }, { CCI_REG8(0x39fb), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x39fc), 0x18 }, { CCI_REG8(0x39fd), 0x18 },</div><div class='add'>+	{ CCI_REG8(0x39fe), 0x18 }, { CCI_REG8(0xc44a), 0x08 },</div><div class='add'>+	{ CCI_REG8(0xc44c), 0x08 }, { CCI_REG8(0xc5e8), 0x0a },</div><div class='add'>+	{ CCI_REG8(0xc5ea), 0x0a }, { CCI_REG8(0x391d), 0x54 },</div><div class='add'>+	{ CCI_REG8(0x391e), 0xca }, { CCI_REG8(0x3991), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x399d), 0x0c }, { CCI_REG8(0x3744), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x374b), 0x0c }, { CCI_REG8(0x3be7), 0x1e },</div><div class='add'>+	{ CCI_REG8(0x3be8), 0x26 }, { CCI_REG8(0x3a50), 0x14 },</div><div class='add'>+	{ CCI_REG8(0x3a54), 0x14 }, { CCI_REG8(0x3add), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x3adf), 0x24 }, { CCI_REG8(0x3aef), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x3af0), 0x24 }, { CCI_REG8(0xc57f), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc580), 0x30 }, { CCI_REG8(0xc581), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc582), 0x30 }, { CCI_REG8(0xc583), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc584), 0x30 }, { CCI_REG8(0xc585), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc586), 0x30 }, { CCI_REG8(0xc587), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc588), 0x30 }, { CCI_REG8(0xc589), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc58a), 0x30 }, { CCI_REG8(0xc58b), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc58c), 0x30 }, { CCI_REG8(0xc58d), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc58e), 0x30 }, { CCI_REG8(0xc58f), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc590), 0x30 }, { CCI_REG8(0xc591), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc592), 0x30 }, { CCI_REG8(0xc598), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc599), 0x30 }, { CCI_REG8(0xc59a), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc59b), 0x30 }, { CCI_REG8(0xc59c), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc59d), 0x30 }, { CCI_REG8(0xc59e), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc59f), 0x30 }, { CCI_REG8(0xc5a0), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5a1), 0x30 }, { CCI_REG8(0xc5a2), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5a3), 0x30 }, { CCI_REG8(0xc5a4), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5a5), 0x30 }, { CCI_REG8(0xc5a6), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5a7), 0x30 }, { CCI_REG8(0xc5a8), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5a9), 0x30 }, { CCI_REG8(0xc5aa), 0x30 },</div><div class='add'>+	{ CCI_REG8(0xc5ab), 0x30 }, { CCI_REG8(0xc5b1), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5b2), 0x38 }, { CCI_REG8(0xc5b3), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5b4), 0x38 }, { CCI_REG8(0xc5b5), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5b6), 0x38 }, { CCI_REG8(0xc5b7), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5b8), 0x38 }, { CCI_REG8(0xc5b9), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5ba), 0x38 }, { CCI_REG8(0xc5bb), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5bc), 0x38 }, { CCI_REG8(0xc5bd), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5be), 0x38 }, { CCI_REG8(0xc5bf), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5c0), 0x38 }, { CCI_REG8(0xc5c1), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5c2), 0x38 }, { CCI_REG8(0xc5c3), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5c4), 0x38 }, { CCI_REG8(0xc5ca), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5cb), 0x38 }, { CCI_REG8(0xc5cc), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5cd), 0x38 }, { CCI_REG8(0xc5ce), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5cf), 0x38 }, { CCI_REG8(0xc5d0), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5d1), 0x38 }, { CCI_REG8(0xc5d2), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5d3), 0x38 }, { CCI_REG8(0xc5d4), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5d5), 0x38 }, { CCI_REG8(0xc5d6), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5d7), 0x38 }, { CCI_REG8(0xc5d8), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5d9), 0x38 }, { CCI_REG8(0xc5da), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5db), 0x38 }, { CCI_REG8(0xc5dc), 0x38 },</div><div class='add'>+	{ CCI_REG8(0xc5dd), 0x38 }, { CCI_REG8(0x3a60), 0x68 },</div><div class='add'>+	{ CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },</div><div class='add'>+	{ CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3aed), 0x6e },</div><div class='add'>+	{ CCI_REG8(0x3af1), 0x73 }, { CCI_REG8(0x3992), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x371d), 0x17 },</div><div class='add'>+	{ CCI_REG8(0x371f), 0x08 }, { CCI_REG8(0x3721), 0xc9 },</div><div class='add'>+	{ CCI_REG8(0x401e), 0x00 }, { CCI_REG8(0x401f), 0xf8 },</div><div class='add'>+	{ CCI_REG8(0x3642), 0x00 }, { CCI_REG8(0x3641), 0x7f },</div><div class='add'>+	{ CCI_REG8(0x3ac5), 0x0c }, { CCI_REG8(0x3ac6), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3ac7), 0x06 }, { CCI_REG8(0x3ac8), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3ac9), 0x0c }, { CCI_REG8(0x3aca), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3acb), 0x06 }, { CCI_REG8(0x3acc), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3acd), 0x0c }, { CCI_REG8(0x3ace), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3acf), 0x07 }, { CCI_REG8(0x3ad0), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3ad1), 0x0c }, { CCI_REG8(0x3ad2), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3ad3), 0x07 }, { CCI_REG8(0x3ad4), 0x04 },</div><div class='add'>+	{ CCI_REG8(0xc483), 0x0c }, { CCI_REG8(0xc484), 0x0c },</div><div class='add'>+	{ CCI_REG8(0xc485), 0x0c }, { CCI_REG8(0xc486), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x3a2f), 0x0c }, { CCI_REG8(0x3a30), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3a31), 0x06 }, { CCI_REG8(0x3a32), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3a34), 0x0c }, { CCI_REG8(0x3a35), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3a36), 0x07 }, { CCI_REG8(0x3a37), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3a43), 0x0c }, { CCI_REG8(0x3a44), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3a45), 0x06 }, { CCI_REG8(0x3a46), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x3a48), 0x0c }, { CCI_REG8(0x3a49), 0x09 },</div><div class='add'>+	{ CCI_REG8(0x3a4a), 0x07 }, { CCI_REG8(0x3a4b), 0x04 },</div><div class='add'>+	{ CCI_REG8(0xc487), 0x0c }, { CCI_REG8(0xc488), 0x0c },</div><div class='add'>+	{ CCI_REG8(0xc489), 0x0c }, { CCI_REG8(0xc48a), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x3645), 0xbd }, { CCI_REG8(0x373f), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x374f), 0x10 }, { CCI_REG8(0x3743), 0xc6 },</div><div class='add'>+	{ CCI_REG8(0x3717), 0x82 }, { CCI_REG8(0x3732), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x3731), 0x16 }, { CCI_REG8(0x3730), 0x16 },</div><div class='add'>+	{ CCI_REG8(0x3828), 0x07 }, { CCI_REG8(0x3714), 0x68 },</div><div class='add'>+	{ CCI_REG8(0x371d), 0x02 }, { CCI_REG8(0x371f), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x37e0), 0x00 }, { CCI_REG8(0x37e1), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x37e2), 0x07 }, { CCI_REG8(0x3734), 0x3e },</div><div class='add'>+	{ CCI_REG8(0x3736), 0x02 }, { CCI_REG8(0x37e4), 0x36 },</div><div class='add'>+	{ CCI_REG8(0x37e9), 0x1c }, { CCI_REG8(0x37ea), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x37eb), 0x0a }, { CCI_REG8(0x37ec), 0x1c },</div><div class='add'>+	{ CCI_REG8(0x37ed), 0x01 }, { CCI_REG8(0x37ee), 0x36 },</div><div class='add'>+	{ CCI_REG8(0x373b), 0x1c }, { CCI_REG8(0x373c), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x37bb), 0x1c }, { CCI_REG8(0x37bc), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x37b8), 0x0c }, { CCI_REG8(0x371c), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x371e), 0x11 }, { CCI_REG8(0x371d), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x371f), 0x01 }, { CCI_REG8(0x3721), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3725), 0x12 }, { CCI_REG8(0x37e3), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x37dd), 0x86 }, { CCI_REG8(0x37db), 0x0a },</div><div class='add'>+	{ CCI_REG8(0x37dc), 0x14 }, { CCI_REG8(0x3727), 0x20 },</div><div class='add'>+	{ CCI_REG8(0x37b2), 0x80 }, { CCI_REG8(0x37da), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x37df), 0x01 }, { CCI_REG8(0x3731), 0x11 },</div><div class='add'>+	{ CCI_REG8(0x37dd), 0x86 }, { CCI_REG8(0x37df), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x37da), 0x03 }, { CCI_REG8(0x37b2), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x3727), 0x20 }, { CCI_REG8(0x4883), 0x26 },</div><div class='add'>+	{ CCI_REG8(0x488b), 0x88 }, { CCI_REG8(0x3d85), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x3d81), 0x01 }, { CCI_REG8(0x3d84), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d88), 0x00 }, { CCI_REG8(0x3d89), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3d8a), 0x0b }, { CCI_REG8(0x3d8b), 0xff },</div><div class='add'>+	{ CCI_REG8(0x4d00), 0x05 }, { CCI_REG8(0x4d01), 0xc4 },</div><div class='add'>+	{ CCI_REG8(0x4d02), 0xa3 }, { CCI_REG8(0x4d03), 0x8c },</div><div class='add'>+	{ CCI_REG8(0x4d04), 0xfb }, { CCI_REG8(0x4d05), 0xed },</div><div class='add'>+	{ CCI_REG8(0x4010), 0x28 }, { CCI_REG8(0x4030), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4031), 0x00 }, { CCI_REG8(0x4032), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4033), 0x00 }, { CCI_REG8(0x4034), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4035), 0x00 }, { CCI_REG8(0x4036), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4037), 0x00 }, { CCI_REG8(0x4040), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4041), 0x00 }, { CCI_REG8(0x4042), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4043), 0x00 }, { CCI_REG8(0x4044), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4045), 0x00 }, { CCI_REG8(0x4046), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4047), 0x00 }, { CCI_REG8(0x3400), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc },</div><div class='add'>+	{ CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 },</div><div class='add'>+	{ CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x3053), 0x00 }, { CCI_REG8(0x3054), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3055), 0x00 }, { CCI_REG8(0x3056), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3057), 0x00 }, { CCI_REG8(0x3058), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x305c), 0x00 }, { CCI_REG8(0x340c), 0x1f },</div><div class='add'>+	{ CCI_REG8(0x340d), 0x00 }, { CCI_REG8(0x3501), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3542), 0x48 }, { CCI_REG8(0x3582), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x3015), 0xf1 }, { CCI_REG8(0x3018), 0xf2 },</div><div class='add'>+	{ CCI_REG8(0x301c), 0xf2 }, { CCI_REG8(0x301d), 0xf6 },</div><div class='add'>+	{ CCI_REG8(0x301e), 0xf1 }, { CCI_REG8(0x0100), 0x01 },</div><div class='add'>+	{ CCI_REG8(0xfff9), 0x08 }, { CCI_REG8(0x3900), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3901), 0xcd }, { CCI_REG8(0x3902), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3903), 0xcd }, { CCI_REG8(0x3904), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3905), 0xcd }, { CCI_REG8(0x3906), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3907), 0xcd }, { CCI_REG8(0x3908), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3909), 0xcd }, { CCI_REG8(0x390a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x390b), 0xcd }, { CCI_REG8(0x390c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x390d), 0xcd }, { CCI_REG8(0x390e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x390f), 0xcd }, { CCI_REG8(0x3910), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3911), 0xcd }, { CCI_REG8(0x3912), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3913), 0xcd }, { CCI_REG8(0x3914), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3915), 0xcd }, { CCI_REG8(0x3916), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3917), 0xcd }, { CCI_REG8(0x3918), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3919), 0xcd }, { CCI_REG8(0x391a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x391b), 0xcd }, { CCI_REG8(0x391c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x391d), 0xcd }, { CCI_REG8(0x391e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x391f), 0xcd }, { CCI_REG8(0x3920), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3921), 0xcd }, { CCI_REG8(0x3922), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3923), 0xcd }, { CCI_REG8(0x3924), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3925), 0xcd }, { CCI_REG8(0x3926), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3927), 0xcd }, { CCI_REG8(0x3928), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3929), 0xcd }, { CCI_REG8(0x392a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x392b), 0xcd }, { CCI_REG8(0x392c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x392d), 0xcd }, { CCI_REG8(0x392e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x392f), 0xcd }, { CCI_REG8(0x3930), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3931), 0xcd }, { CCI_REG8(0x3932), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3933), 0xcd }, { CCI_REG8(0x3934), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3935), 0xcd }, { CCI_REG8(0x3936), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3937), 0xcd }, { CCI_REG8(0x3938), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3939), 0xcd }, { CCI_REG8(0x393a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x393b), 0xcd }, { CCI_REG8(0x393c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x393d), 0xcd }, { CCI_REG8(0x393e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x393f), 0xcd }, { CCI_REG8(0x3940), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3941), 0xcd }, { CCI_REG8(0x3942), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3943), 0xcd }, { CCI_REG8(0x3944), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3945), 0xcd }, { CCI_REG8(0x3946), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3947), 0xcd }, { CCI_REG8(0x3948), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3949), 0xcd }, { CCI_REG8(0x394a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x394b), 0xcd }, { CCI_REG8(0x394c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x394d), 0xcd }, { CCI_REG8(0x394e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x394f), 0xcd }, { CCI_REG8(0x3950), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3951), 0xcd }, { CCI_REG8(0x3952), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3953), 0xcd }, { CCI_REG8(0x3954), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3955), 0xcd }, { CCI_REG8(0x3956), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3957), 0xcd }, { CCI_REG8(0x3958), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3959), 0xcd }, { CCI_REG8(0x395a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x395b), 0xcd }, { CCI_REG8(0x395c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x395d), 0xcd }, { CCI_REG8(0x395e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x395f), 0xcd }, { CCI_REG8(0x3960), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3961), 0xcd }, { CCI_REG8(0x3962), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3963), 0xcd }, { CCI_REG8(0x3964), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3965), 0xcd }, { CCI_REG8(0x3966), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3967), 0xcd }, { CCI_REG8(0x3968), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3969), 0xcd }, { CCI_REG8(0x396a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x396b), 0xcd }, { CCI_REG8(0x396c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x396d), 0xcd }, { CCI_REG8(0x396e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x396f), 0xcd }, { CCI_REG8(0x3970), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3971), 0xcd }, { CCI_REG8(0x3972), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3973), 0xcd }, { CCI_REG8(0x3974), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3975), 0xcd }, { CCI_REG8(0x3976), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3977), 0xcd }, { CCI_REG8(0x3978), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3979), 0xcd }, { CCI_REG8(0x397a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x397b), 0xcd }, { CCI_REG8(0x397c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x397d), 0xcd }, { CCI_REG8(0x397e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x397f), 0xcd }, { CCI_REG8(0x3980), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3981), 0xcd }, { CCI_REG8(0x3982), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3983), 0xcd }, { CCI_REG8(0x3984), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3985), 0xcd }, { CCI_REG8(0x3986), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3987), 0xcd }, { CCI_REG8(0x3988), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3989), 0xcd }, { CCI_REG8(0x398a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x398b), 0xcd }, { CCI_REG8(0x398c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x398d), 0xcd }, { CCI_REG8(0x398e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x398f), 0xcd }, { CCI_REG8(0x3990), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3991), 0xcd }, { CCI_REG8(0x3992), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3993), 0xcd }, { CCI_REG8(0x3994), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3995), 0xcd }, { CCI_REG8(0x3996), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3997), 0xcd }, { CCI_REG8(0x3998), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3999), 0xcd }, { CCI_REG8(0x399a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x399b), 0xcd }, { CCI_REG8(0x399c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x399d), 0xcd }, { CCI_REG8(0x399e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x399f), 0xcd }, { CCI_REG8(0x39a0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39a1), 0xcd }, { CCI_REG8(0x39a2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39a3), 0xcd }, { CCI_REG8(0x39a4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39a5), 0xcd }, { CCI_REG8(0x39a6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39a7), 0xcd }, { CCI_REG8(0x39a8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39a9), 0xcd }, { CCI_REG8(0x39aa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39ab), 0xcd }, { CCI_REG8(0x39ac), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39ad), 0xcd }, { CCI_REG8(0x39ae), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39af), 0xcd }, { CCI_REG8(0x39b0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39b1), 0xcd }, { CCI_REG8(0x39b2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39b3), 0xcd }, { CCI_REG8(0x39b4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39b5), 0xcd }, { CCI_REG8(0x39b6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39b7), 0xcd }, { CCI_REG8(0x39b8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39b9), 0xcd }, { CCI_REG8(0x39ba), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39bb), 0xcd }, { CCI_REG8(0x39bc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39bd), 0xcd }, { CCI_REG8(0x39be), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39bf), 0xcd }, { CCI_REG8(0x39c0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39c1), 0xcd }, { CCI_REG8(0x39c2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39c3), 0xcd }, { CCI_REG8(0x39c4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39c5), 0xcd }, { CCI_REG8(0x39c6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39c7), 0xcd }, { CCI_REG8(0x39c8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39c9), 0xcd }, { CCI_REG8(0x39ca), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39cb), 0xcd }, { CCI_REG8(0x39cc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39cd), 0xcd }, { CCI_REG8(0x39ce), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39cf), 0xcd }, { CCI_REG8(0x39d0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39d1), 0xcd }, { CCI_REG8(0x39d2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39d3), 0xcd }, { CCI_REG8(0x39d4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39d5), 0xcd }, { CCI_REG8(0x39d6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39d7), 0xcd }, { CCI_REG8(0x39d8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39d9), 0xcd }, { CCI_REG8(0x39da), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39db), 0xcd }, { CCI_REG8(0x39dc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39dd), 0xcd }, { CCI_REG8(0x39de), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39df), 0xcd }, { CCI_REG8(0x39e0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x39e1), 0x40 }, { CCI_REG8(0x39e2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39e3), 0x40 }, { CCI_REG8(0x39e4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39e5), 0x40 }, { CCI_REG8(0x39e6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39e7), 0x40 }, { CCI_REG8(0x39e8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39e9), 0x40 }, { CCI_REG8(0x39ea), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39eb), 0x40 }, { CCI_REG8(0x39ec), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39ed), 0x40 }, { CCI_REG8(0x39ee), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39ef), 0x40 }, { CCI_REG8(0x39f0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39f1), 0x40 }, { CCI_REG8(0x39f2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39f3), 0x40 }, { CCI_REG8(0x39f4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39f5), 0x40 }, { CCI_REG8(0x39f6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39f7), 0x40 }, { CCI_REG8(0x39f8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39f9), 0x40 }, { CCI_REG8(0x39fa), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39fb), 0x40 }, { CCI_REG8(0x39fc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39fd), 0x40 }, { CCI_REG8(0x39fe), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x39ff), 0x40 }, { CCI_REG8(0x3a00), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a01), 0x40 }, { CCI_REG8(0x3a02), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a03), 0x40 }, { CCI_REG8(0x3a04), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a05), 0x40 }, { CCI_REG8(0x3a06), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a07), 0x40 }, { CCI_REG8(0x3a08), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a09), 0x40 }, { CCI_REG8(0x3a0a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a0b), 0x40 }, { CCI_REG8(0x3a0c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a0d), 0x40 }, { CCI_REG8(0x3a0e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a0f), 0x40 }, { CCI_REG8(0x3a10), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a11), 0x40 }, { CCI_REG8(0x3a12), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a13), 0x40 }, { CCI_REG8(0x3a14), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a15), 0x40 }, { CCI_REG8(0x3a16), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a17), 0x40 }, { CCI_REG8(0x3a18), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a19), 0x40 }, { CCI_REG8(0x3a1a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a1b), 0x40 }, { CCI_REG8(0x3a1c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a1d), 0x40 }, { CCI_REG8(0x3a1e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a1f), 0x40 }, { CCI_REG8(0x3a20), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a21), 0x40 }, { CCI_REG8(0x3a22), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a23), 0x40 }, { CCI_REG8(0x3a24), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a25), 0x40 }, { CCI_REG8(0x3a26), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a27), 0x40 }, { CCI_REG8(0x3a28), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a29), 0x40 }, { CCI_REG8(0x3a2a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a2b), 0x40 }, { CCI_REG8(0x3a2c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a2d), 0x40 }, { CCI_REG8(0x3a2e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a2f), 0x40 }, { CCI_REG8(0x3a30), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a31), 0x40 }, { CCI_REG8(0x3a32), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a33), 0x40 }, { CCI_REG8(0x3a34), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a35), 0x40 }, { CCI_REG8(0x3a36), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a37), 0x40 }, { CCI_REG8(0x3a38), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a39), 0x40 }, { CCI_REG8(0x3a3a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a3b), 0xcd }, { CCI_REG8(0x3a3c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a3d), 0xcd }, { CCI_REG8(0x3a3e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a3f), 0xcd }, { CCI_REG8(0x3a40), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a41), 0xcd }, { CCI_REG8(0x3a42), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a43), 0xcd }, { CCI_REG8(0x3a44), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a45), 0xcd }, { CCI_REG8(0x3a46), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a47), 0xcd }, { CCI_REG8(0x3a48), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a49), 0xcd }, { CCI_REG8(0x3a4a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a4b), 0xcd }, { CCI_REG8(0x3a4c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a4d), 0xcd }, { CCI_REG8(0x3a4e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a4f), 0xcd }, { CCI_REG8(0x3a50), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a51), 0xcd }, { CCI_REG8(0x3a52), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a53), 0xcd }, { CCI_REG8(0x3a54), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a55), 0xcd }, { CCI_REG8(0x3a56), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a57), 0xcd }, { CCI_REG8(0x3a58), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a59), 0xcd }, { CCI_REG8(0x3a5a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a5b), 0xcd }, { CCI_REG8(0x3a5c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a5d), 0xcd }, { CCI_REG8(0x3a5e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a5f), 0xcd }, { CCI_REG8(0x3a60), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a61), 0xcd }, { CCI_REG8(0x3a62), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a63), 0xcd }, { CCI_REG8(0x3a64), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a65), 0xcd }, { CCI_REG8(0x3a66), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a67), 0xcd }, { CCI_REG8(0x3a68), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a69), 0xcd }, { CCI_REG8(0x3a6a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a6b), 0xcd }, { CCI_REG8(0x3a6c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a6d), 0xcd }, { CCI_REG8(0x3a6e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a6f), 0xcd }, { CCI_REG8(0x3a70), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a71), 0xcd }, { CCI_REG8(0x3a72), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a73), 0xcd }, { CCI_REG8(0x3a74), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a75), 0xcd }, { CCI_REG8(0x3a76), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a77), 0xcd }, { CCI_REG8(0x3a78), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a79), 0xcd }, { CCI_REG8(0x3a7a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a7b), 0xcd }, { CCI_REG8(0x3a7c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a7d), 0xcd }, { CCI_REG8(0x3a7e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a7f), 0xcd }, { CCI_REG8(0x3a80), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a81), 0xcd }, { CCI_REG8(0x3a82), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a83), 0xcd }, { CCI_REG8(0x3a84), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a85), 0xcd }, { CCI_REG8(0x3a86), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a87), 0xcd }, { CCI_REG8(0x3a88), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a89), 0xcd }, { CCI_REG8(0x3a8a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a8b), 0xcd }, { CCI_REG8(0x3a8c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a8d), 0xcd }, { CCI_REG8(0x3a8e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a8f), 0xcd }, { CCI_REG8(0x3a90), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a91), 0xcd }, { CCI_REG8(0x3a92), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a93), 0xcd }, { CCI_REG8(0x3a94), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3a95), 0x40 }, { CCI_REG8(0x3a96), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a97), 0x40 }, { CCI_REG8(0x3a98), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a99), 0x40 }, { CCI_REG8(0x3a9a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a9b), 0x40 }, { CCI_REG8(0x3a9c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a9d), 0x40 }, { CCI_REG8(0x3a9e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3a9f), 0x40 }, { CCI_REG8(0x3aa0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aa1), 0x40 }, { CCI_REG8(0x3aa2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aa3), 0x40 }, { CCI_REG8(0x3aa4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aa5), 0x40 }, { CCI_REG8(0x3aa6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aa7), 0x40 }, { CCI_REG8(0x3aa8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aa9), 0x40 }, { CCI_REG8(0x3aaa), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aab), 0x40 }, { CCI_REG8(0x3aac), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aad), 0x40 }, { CCI_REG8(0x3aae), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aaf), 0x40 }, { CCI_REG8(0x3ab0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ab1), 0x40 }, { CCI_REG8(0x3ab2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ab3), 0x40 }, { CCI_REG8(0x3ab4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ab5), 0x40 }, { CCI_REG8(0x3ab6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ab7), 0x40 }, { CCI_REG8(0x3ab8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ab9), 0x40 }, { CCI_REG8(0x3aba), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3abb), 0x40 }, { CCI_REG8(0x3abc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3abd), 0x40 }, { CCI_REG8(0x3abe), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3abf), 0x40 }, { CCI_REG8(0x3ac0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ac1), 0x40 }, { CCI_REG8(0x3ac2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ac3), 0x40 }, { CCI_REG8(0x3ac4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ac5), 0x40 }, { CCI_REG8(0x3ac6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ac7), 0x40 }, { CCI_REG8(0x3ac8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ac9), 0x40 }, { CCI_REG8(0x3aca), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3acb), 0x40 }, { CCI_REG8(0x3acc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3acd), 0x40 }, { CCI_REG8(0x3ace), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3acf), 0x40 }, { CCI_REG8(0x3ad0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ad1), 0x40 }, { CCI_REG8(0x3ad2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ad3), 0x40 }, { CCI_REG8(0x3ad4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ad5), 0x40 }, { CCI_REG8(0x3ad6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ad7), 0x40 }, { CCI_REG8(0x3ad8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ad9), 0x40 }, { CCI_REG8(0x3ada), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3adb), 0x40 }, { CCI_REG8(0x3adc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3add), 0x40 }, { CCI_REG8(0x3ade), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3adf), 0x40 }, { CCI_REG8(0x3ae0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ae1), 0x40 }, { CCI_REG8(0x3ae2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ae3), 0x40 }, { CCI_REG8(0x3ae4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ae5), 0x40 }, { CCI_REG8(0x3ae6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ae7), 0x40 }, { CCI_REG8(0x3ae8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ae9), 0x40 }, { CCI_REG8(0x3aea), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aeb), 0x40 }, { CCI_REG8(0x3aec), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aed), 0x40 }, { CCI_REG8(0x3aee), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3aef), 0xcd }, { CCI_REG8(0x3af0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3af1), 0xcd }, { CCI_REG8(0x3af2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3af3), 0xcd }, { CCI_REG8(0x3af4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3af5), 0xcd }, { CCI_REG8(0x3af6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3af7), 0xcd }, { CCI_REG8(0x3af8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3af9), 0xcd }, { CCI_REG8(0x3afa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3afb), 0xcd }, { CCI_REG8(0x3afc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3afd), 0xcd }, { CCI_REG8(0x3afe), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3aff), 0xcd }, { CCI_REG8(0x3b00), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b01), 0xcd }, { CCI_REG8(0x3b02), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b03), 0xcd }, { CCI_REG8(0x3b04), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b05), 0xcd }, { CCI_REG8(0x3b06), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b07), 0xcd }, { CCI_REG8(0x3b08), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b09), 0xcd }, { CCI_REG8(0x3b0a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b0b), 0xcd }, { CCI_REG8(0x3b0c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b0d), 0xcd }, { CCI_REG8(0x3b0e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b0f), 0xcd }, { CCI_REG8(0x3b10), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b11), 0xcd }, { CCI_REG8(0x3b12), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b13), 0xcd }, { CCI_REG8(0x3b14), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b15), 0xcd }, { CCI_REG8(0x3b16), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b17), 0xcd }, { CCI_REG8(0x3b18), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b19), 0xcd }, { CCI_REG8(0x3b1a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b1b), 0xcd }, { CCI_REG8(0x3b1c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b1d), 0xcd }, { CCI_REG8(0x3b1e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b1f), 0xcd }, { CCI_REG8(0x3b20), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b21), 0xcd }, { CCI_REG8(0x3b22), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b23), 0xcd }, { CCI_REG8(0x3b24), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b25), 0xcd }, { CCI_REG8(0x3b26), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b27), 0xcd }, { CCI_REG8(0x3b28), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b29), 0xcd }, { CCI_REG8(0x3b2a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b2b), 0xcd }, { CCI_REG8(0x3b2c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b2d), 0xcd }, { CCI_REG8(0x3b2e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b2f), 0xcd }, { CCI_REG8(0x3b30), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b31), 0xcd }, { CCI_REG8(0x3b32), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b33), 0xcd }, { CCI_REG8(0x3b34), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b35), 0xcd }, { CCI_REG8(0x3b36), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b37), 0xcd }, { CCI_REG8(0x3b38), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b39), 0xcd }, { CCI_REG8(0x3b3a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b3b), 0xcd }, { CCI_REG8(0x3b3c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b3d), 0xcd }, { CCI_REG8(0x3b3e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b3f), 0xcd }, { CCI_REG8(0x3b40), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b41), 0xcd }, { CCI_REG8(0x3b42), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b43), 0xcd }, { CCI_REG8(0x3b44), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b45), 0xcd }, { CCI_REG8(0x3b46), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b47), 0xcd }, { CCI_REG8(0x3b48), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b49), 0xcd }, { CCI_REG8(0x3b4a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b4b), 0xcd }, { CCI_REG8(0x3b4c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b4d), 0xcd }, { CCI_REG8(0x3b4e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b4f), 0xcd }, { CCI_REG8(0x3b50), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b51), 0xcd }, { CCI_REG8(0x3b52), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b53), 0xcd }, { CCI_REG8(0x3b54), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b55), 0xcd }, { CCI_REG8(0x3b56), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b57), 0xcd }, { CCI_REG8(0x3b58), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b59), 0xcd }, { CCI_REG8(0x3b5a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b5b), 0xcd }, { CCI_REG8(0x3b5c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b5d), 0xcd }, { CCI_REG8(0x3b5e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b5f), 0xcd }, { CCI_REG8(0x3b60), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b61), 0xcd }, { CCI_REG8(0x3b62), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b63), 0xcd }, { CCI_REG8(0x3b64), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b65), 0xcd }, { CCI_REG8(0x3b66), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b67), 0xcd }, { CCI_REG8(0x3b68), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b69), 0xcd }, { CCI_REG8(0x3b6a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b6b), 0xcd }, { CCI_REG8(0x3b6c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b6d), 0xcd }, { CCI_REG8(0x3b6e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b6f), 0xcd }, { CCI_REG8(0x3b70), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b71), 0xcd }, { CCI_REG8(0x3b72), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b73), 0xcd }, { CCI_REG8(0x3b74), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b75), 0xcd }, { CCI_REG8(0x3b76), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b77), 0xcd }, { CCI_REG8(0x3b78), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b79), 0xcd }, { CCI_REG8(0x3b7a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b7b), 0xcd }, { CCI_REG8(0x3b7c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b7d), 0xcd }, { CCI_REG8(0x3b7e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b7f), 0xcd }, { CCI_REG8(0x3b80), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b81), 0xcd }, { CCI_REG8(0x3b82), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b83), 0xcd }, { CCI_REG8(0x3b84), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b85), 0xcd }, { CCI_REG8(0x3b86), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b87), 0xcd }, { CCI_REG8(0x3b88), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b89), 0xcd }, { CCI_REG8(0x3b8a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b8b), 0xcd }, { CCI_REG8(0x3b8c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b8d), 0xcd }, { CCI_REG8(0x3b8e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b8f), 0xcd }, { CCI_REG8(0x3b90), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b91), 0xcd }, { CCI_REG8(0x3b92), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b93), 0xcd }, { CCI_REG8(0x3b94), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b95), 0xcd }, { CCI_REG8(0x3b96), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b97), 0xcd }, { CCI_REG8(0x3b98), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b99), 0xcd }, { CCI_REG8(0x3b9a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b9b), 0xcd }, { CCI_REG8(0x3b9c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b9d), 0xcd }, { CCI_REG8(0x3b9e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3b9f), 0xcd }, { CCI_REG8(0x3ba0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ba1), 0xcd }, { CCI_REG8(0x3ba2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ba3), 0xcd }, { CCI_REG8(0x3ba4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ba5), 0xcd }, { CCI_REG8(0x3ba6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ba7), 0xcd }, { CCI_REG8(0x3ba8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ba9), 0xcd }, { CCI_REG8(0x3baa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bab), 0xcd }, { CCI_REG8(0x3bac), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bad), 0xcd }, { CCI_REG8(0x3bae), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3baf), 0xcd }, { CCI_REG8(0x3bb0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bb1), 0xcd }, { CCI_REG8(0x3bb2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bb3), 0xcd }, { CCI_REG8(0x3bb4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bb5), 0xcd }, { CCI_REG8(0x3bb6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bb7), 0xcd }, { CCI_REG8(0x3bb8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bb9), 0xcd }, { CCI_REG8(0x3bba), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bbb), 0xcd }, { CCI_REG8(0x3bbc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bbd), 0xcd }, { CCI_REG8(0x3bbe), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bbf), 0xcd }, { CCI_REG8(0x3bc0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bc1), 0xcd }, { CCI_REG8(0x3bc2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bc3), 0xcd }, { CCI_REG8(0x3bc4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bc5), 0xcd }, { CCI_REG8(0x3bc6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bc7), 0xcd }, { CCI_REG8(0x3bc8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bc9), 0xcd }, { CCI_REG8(0x3bca), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bcb), 0xcd }, { CCI_REG8(0x3bcc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bcd), 0xcd }, { CCI_REG8(0x3bce), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bcf), 0xcd }, { CCI_REG8(0x3bd0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bd1), 0xcd }, { CCI_REG8(0x3bd2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bd3), 0xcd }, { CCI_REG8(0x3bd4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bd5), 0xcd }, { CCI_REG8(0x3bd6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bd7), 0xcd }, { CCI_REG8(0x3bd8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bd9), 0xcd }, { CCI_REG8(0x3bda), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bdb), 0xcd }, { CCI_REG8(0x3bdc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bdd), 0xcd }, { CCI_REG8(0x3bde), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bdf), 0xcd }, { CCI_REG8(0x3be0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3be1), 0xcd }, { CCI_REG8(0x3be2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3be3), 0xcd }, { CCI_REG8(0x3be4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3be5), 0xcd }, { CCI_REG8(0x3be6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3be7), 0xcd }, { CCI_REG8(0x3be8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3be9), 0xcd }, { CCI_REG8(0x3bea), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3beb), 0xcd }, { CCI_REG8(0x3bec), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bed), 0xcd }, { CCI_REG8(0x3bee), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bef), 0xcd }, { CCI_REG8(0x3bf0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bf1), 0xcd }, { CCI_REG8(0x3bf2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bf3), 0xcd }, { CCI_REG8(0x3bf4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bf5), 0xcd }, { CCI_REG8(0x3bf6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bf7), 0xcd }, { CCI_REG8(0x3bf8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bf9), 0xcd }, { CCI_REG8(0x3bfa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bfb), 0xcd }, { CCI_REG8(0x3bfc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bfd), 0xcd }, { CCI_REG8(0x3bfe), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3bff), 0xcd }, { CCI_REG8(0x3c00), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c01), 0xcd }, { CCI_REG8(0x3c02), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c03), 0xcd }, { CCI_REG8(0x3c04), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c05), 0xcd }, { CCI_REG8(0x3c06), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c07), 0xcd }, { CCI_REG8(0x3c08), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c09), 0xcd }, { CCI_REG8(0x3c0a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c0b), 0xcd }, { CCI_REG8(0x3c0c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c0d), 0xcd }, { CCI_REG8(0x3c0e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c0f), 0xcd }, { CCI_REG8(0x3c10), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c11), 0xcd }, { CCI_REG8(0x3c12), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c13), 0xcd }, { CCI_REG8(0x3c14), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c15), 0xcd }, { CCI_REG8(0x3c16), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c17), 0xcd }, { CCI_REG8(0x3c18), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c19), 0xcd }, { CCI_REG8(0x3c1a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c1b), 0xcd }, { CCI_REG8(0x3c1c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c1d), 0xcd }, { CCI_REG8(0x3c1e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c1f), 0xcd }, { CCI_REG8(0x3c20), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c21), 0xcd }, { CCI_REG8(0x3c22), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c23), 0xcd }, { CCI_REG8(0x3c24), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c25), 0xcd }, { CCI_REG8(0x3c26), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c27), 0xcd }, { CCI_REG8(0x3c28), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c29), 0xcd }, { CCI_REG8(0x3c2a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c2b), 0xcd }, { CCI_REG8(0x3c2c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c2d), 0xcd }, { CCI_REG8(0x3c2e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c2f), 0xcd }, { CCI_REG8(0x3c30), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c31), 0xcd }, { CCI_REG8(0x3c32), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c33), 0xcd }, { CCI_REG8(0x3c34), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c35), 0xcd }, { CCI_REG8(0x3c36), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c37), 0xcd }, { CCI_REG8(0x3c38), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c39), 0xcd }, { CCI_REG8(0x3c3a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c3b), 0xcd }, { CCI_REG8(0x3c3c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c3d), 0xcd }, { CCI_REG8(0x3c3e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c3f), 0xcd }, { CCI_REG8(0x3c40), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c41), 0xcd }, { CCI_REG8(0x3c42), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c43), 0xcd }, { CCI_REG8(0x3c44), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c45), 0xcd }, { CCI_REG8(0x3c46), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c47), 0xcd }, { CCI_REG8(0x3c48), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c49), 0xcd }, { CCI_REG8(0x3c4a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c4b), 0xcd }, { CCI_REG8(0x3c4c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c4d), 0xcd }, { CCI_REG8(0x3c4e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c4f), 0xcd }, { CCI_REG8(0x3c50), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c51), 0xcd }, { CCI_REG8(0x3c52), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c53), 0xcd }, { CCI_REG8(0x3c54), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c55), 0xcd }, { CCI_REG8(0x3c56), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c57), 0xcd }, { CCI_REG8(0x3c58), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c59), 0xcd }, { CCI_REG8(0x3c5a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c5b), 0xcd }, { CCI_REG8(0x3c5c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c5d), 0xcd }, { CCI_REG8(0x3c5e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c5f), 0xcd }, { CCI_REG8(0x3c60), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c61), 0xcd }, { CCI_REG8(0x3c62), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c63), 0xcd }, { CCI_REG8(0x3c64), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c65), 0xcd }, { CCI_REG8(0x3c66), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c67), 0xcd }, { CCI_REG8(0x3c68), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c69), 0xcd }, { CCI_REG8(0x3c6a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c6b), 0xcd }, { CCI_REG8(0x3c6c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c6d), 0xcd }, { CCI_REG8(0x3c6e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c6f), 0xcd }, { CCI_REG8(0x3c70), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c71), 0xcd }, { CCI_REG8(0x3c72), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c73), 0xcd }, { CCI_REG8(0x3c74), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c75), 0xcd }, { CCI_REG8(0x3c76), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c77), 0xcd }, { CCI_REG8(0x3c78), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c79), 0xcd }, { CCI_REG8(0x3c7a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c7b), 0xcd }, { CCI_REG8(0x3c7c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c7d), 0xcd }, { CCI_REG8(0x3c7e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c7f), 0xcd }, { CCI_REG8(0x3c80), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c81), 0xcd }, { CCI_REG8(0x3c82), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c83), 0xcd }, { CCI_REG8(0x3c84), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c85), 0xcd }, { CCI_REG8(0x3c86), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c87), 0xcd }, { CCI_REG8(0x3c88), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c89), 0xcd }, { CCI_REG8(0x3c8a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c8b), 0xcd }, { CCI_REG8(0x3c8c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c8d), 0xcd }, { CCI_REG8(0x3c8e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c8f), 0xcd }, { CCI_REG8(0x3c90), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c91), 0xcd }, { CCI_REG8(0x3c92), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c93), 0xcd }, { CCI_REG8(0x3c94), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c95), 0xcd }, { CCI_REG8(0x3c96), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c97), 0xcd }, { CCI_REG8(0x3c98), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c99), 0xcd }, { CCI_REG8(0x3c9a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c9b), 0xcd }, { CCI_REG8(0x3c9c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c9d), 0xcd }, { CCI_REG8(0x3c9e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3c9f), 0xcd }, { CCI_REG8(0x3ca0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ca1), 0xcd }, { CCI_REG8(0x3ca2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ca3), 0xcd }, { CCI_REG8(0x3ca4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ca5), 0xcd }, { CCI_REG8(0x3ca6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ca7), 0xcd }, { CCI_REG8(0x3ca8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ca9), 0xcd }, { CCI_REG8(0x3caa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3cab), 0xcd }, { CCI_REG8(0x3cac), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3cad), 0xcd }, { CCI_REG8(0x3cae), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3caf), 0xcd }, { CCI_REG8(0x3cb0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3cb1), 0x40 }, { CCI_REG8(0x3cb2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cb3), 0x40 }, { CCI_REG8(0x3cb4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cb5), 0x40 }, { CCI_REG8(0x3cb6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cb7), 0x40 }, { CCI_REG8(0x3cb8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cb9), 0x40 }, { CCI_REG8(0x3cba), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cbb), 0x40 }, { CCI_REG8(0x3cbc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cbd), 0x40 }, { CCI_REG8(0x3cbe), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cbf), 0x40 }, { CCI_REG8(0x3cc0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cc1), 0x40 }, { CCI_REG8(0x3cc2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cc3), 0x40 }, { CCI_REG8(0x3cc4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cc5), 0x40 }, { CCI_REG8(0x3cc6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cc7), 0x40 }, { CCI_REG8(0x3cc8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cc9), 0x40 }, { CCI_REG8(0x3cca), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ccb), 0x40 }, { CCI_REG8(0x3ccc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ccd), 0x40 }, { CCI_REG8(0x3cce), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ccf), 0x40 }, { CCI_REG8(0x3cd0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cd1), 0x40 }, { CCI_REG8(0x3cd2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cd3), 0x40 }, { CCI_REG8(0x3cd4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cd5), 0x40 }, { CCI_REG8(0x3cd6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cd7), 0x40 }, { CCI_REG8(0x3cd8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cd9), 0x40 }, { CCI_REG8(0x3cda), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cdb), 0x40 }, { CCI_REG8(0x3cdc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cdd), 0x40 }, { CCI_REG8(0x3cde), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cdf), 0x40 }, { CCI_REG8(0x3ce0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ce1), 0x40 }, { CCI_REG8(0x3ce2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ce3), 0x40 }, { CCI_REG8(0x3ce4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ce5), 0x40 }, { CCI_REG8(0x3ce6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ce7), 0x40 }, { CCI_REG8(0x3ce8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ce9), 0x40 }, { CCI_REG8(0x3cea), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ceb), 0x40 }, { CCI_REG8(0x3cec), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3ced), 0x40 }, { CCI_REG8(0x3cee), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cef), 0x40 }, { CCI_REG8(0x3cf0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cf1), 0x40 }, { CCI_REG8(0x3cf2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cf3), 0x40 }, { CCI_REG8(0x3cf4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cf5), 0x40 }, { CCI_REG8(0x3cf6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cf7), 0x40 }, { CCI_REG8(0x3cf8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cf9), 0x40 }, { CCI_REG8(0x3cfa), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cfb), 0x40 }, { CCI_REG8(0x3cfc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cfd), 0x40 }, { CCI_REG8(0x3cfe), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3cff), 0x40 }, { CCI_REG8(0x3d00), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d01), 0x40 }, { CCI_REG8(0x3d02), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d03), 0x40 }, { CCI_REG8(0x3d04), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d05), 0x40 }, { CCI_REG8(0x3d06), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d07), 0x40 }, { CCI_REG8(0x3d08), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d09), 0x40 }, { CCI_REG8(0x3d0a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d0b), 0xcd }, { CCI_REG8(0x3d0c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d0d), 0xcd }, { CCI_REG8(0x3d0e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d0f), 0xcd }, { CCI_REG8(0x3d10), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d11), 0xcd }, { CCI_REG8(0x3d12), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d13), 0xcd }, { CCI_REG8(0x3d14), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d15), 0xcd }, { CCI_REG8(0x3d16), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d17), 0xcd }, { CCI_REG8(0x3d18), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d19), 0xcd }, { CCI_REG8(0x3d1a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d1b), 0xcd }, { CCI_REG8(0x3d1c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d1d), 0xcd }, { CCI_REG8(0x3d1e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d1f), 0xcd }, { CCI_REG8(0x3d20), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d21), 0xcd }, { CCI_REG8(0x3d22), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d23), 0xcd }, { CCI_REG8(0x3d24), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d25), 0xcd }, { CCI_REG8(0x3d26), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d27), 0xcd }, { CCI_REG8(0x3d28), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d29), 0xcd }, { CCI_REG8(0x3d2a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d2b), 0xcd }, { CCI_REG8(0x3d2c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d2d), 0xcd }, { CCI_REG8(0x3d2e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d2f), 0xcd }, { CCI_REG8(0x3d30), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d31), 0xcd }, { CCI_REG8(0x3d32), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d33), 0xcd }, { CCI_REG8(0x3d34), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d35), 0xcd }, { CCI_REG8(0x3d36), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d37), 0xcd }, { CCI_REG8(0x3d38), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d39), 0xcd }, { CCI_REG8(0x3d3a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d3b), 0xcd }, { CCI_REG8(0x3d3c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d3d), 0xcd }, { CCI_REG8(0x3d3e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d3f), 0xcd }, { CCI_REG8(0x3d40), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d41), 0xcd }, { CCI_REG8(0x3d42), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d43), 0xcd }, { CCI_REG8(0x3d44), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d45), 0xcd }, { CCI_REG8(0x3d46), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d47), 0xcd }, { CCI_REG8(0x3d48), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d49), 0xcd }, { CCI_REG8(0x3d4a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d4b), 0xcd }, { CCI_REG8(0x3d4c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d4d), 0xcd }, { CCI_REG8(0x3d4e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d4f), 0xcd }, { CCI_REG8(0x3d50), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d51), 0xcd }, { CCI_REG8(0x3d52), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d53), 0xcd }, { CCI_REG8(0x3d54), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d55), 0xcd }, { CCI_REG8(0x3d56), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d57), 0xcd }, { CCI_REG8(0x3d58), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d59), 0xcd }, { CCI_REG8(0x3d5a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d5b), 0xcd }, { CCI_REG8(0x3d5c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d5d), 0xcd }, { CCI_REG8(0x3d5e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d5f), 0xcd }, { CCI_REG8(0x3d60), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d61), 0xcd }, { CCI_REG8(0x3d62), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d63), 0xcd }, { CCI_REG8(0x3d64), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3d65), 0x40 }, { CCI_REG8(0x3d66), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d67), 0x40 }, { CCI_REG8(0x3d68), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d69), 0x40 }, { CCI_REG8(0x3d6a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d6b), 0x40 }, { CCI_REG8(0x3d6c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d6d), 0x40 }, { CCI_REG8(0x3d6e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d6f), 0x40 }, { CCI_REG8(0x3d70), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d71), 0x40 }, { CCI_REG8(0x3d72), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d73), 0x40 }, { CCI_REG8(0x3d74), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d75), 0x40 }, { CCI_REG8(0x3d76), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d77), 0x40 }, { CCI_REG8(0x3d78), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d79), 0x40 }, { CCI_REG8(0x3d7a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d7b), 0x40 }, { CCI_REG8(0x3d7c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d7d), 0x40 }, { CCI_REG8(0x3d7e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d7f), 0x40 }, { CCI_REG8(0x3d80), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d81), 0x40 }, { CCI_REG8(0x3d82), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d83), 0x40 }, { CCI_REG8(0x3d84), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d85), 0x40 }, { CCI_REG8(0x3d86), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d87), 0x40 }, { CCI_REG8(0x3d88), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d89), 0x40 }, { CCI_REG8(0x3d8a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d8b), 0x40 }, { CCI_REG8(0x3d8c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d8d), 0x40 }, { CCI_REG8(0x3d8e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d8f), 0x40 }, { CCI_REG8(0x3d90), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d91), 0x40 }, { CCI_REG8(0x3d92), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d93), 0x40 }, { CCI_REG8(0x3d94), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d95), 0x40 }, { CCI_REG8(0x3d96), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d97), 0x40 }, { CCI_REG8(0x3d98), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d99), 0x40 }, { CCI_REG8(0x3d9a), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d9b), 0x40 }, { CCI_REG8(0x3d9c), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d9d), 0x40 }, { CCI_REG8(0x3d9e), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3d9f), 0x40 }, { CCI_REG8(0x3da0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3da1), 0x40 }, { CCI_REG8(0x3da2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3da3), 0x40 }, { CCI_REG8(0x3da4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3da5), 0x40 }, { CCI_REG8(0x3da6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3da7), 0x40 }, { CCI_REG8(0x3da8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3da9), 0x40 }, { CCI_REG8(0x3daa), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3dab), 0x40 }, { CCI_REG8(0x3dac), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3dad), 0x40 }, { CCI_REG8(0x3dae), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3daf), 0x40 }, { CCI_REG8(0x3db0), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3db1), 0x40 }, { CCI_REG8(0x3db2), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3db3), 0x40 }, { CCI_REG8(0x3db4), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3db5), 0x40 }, { CCI_REG8(0x3db6), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3db7), 0x40 }, { CCI_REG8(0x3db8), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3db9), 0x40 }, { CCI_REG8(0x3dba), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3dbb), 0x40 }, { CCI_REG8(0x3dbc), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3dbd), 0x40 }, { CCI_REG8(0x3dbe), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x3dbf), 0xcd }, { CCI_REG8(0x3dc0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dc1), 0xcd }, { CCI_REG8(0x3dc2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dc3), 0xcd }, { CCI_REG8(0x3dc4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dc5), 0xcd }, { CCI_REG8(0x3dc6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dc7), 0xcd }, { CCI_REG8(0x3dc8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dc9), 0xcd }, { CCI_REG8(0x3dca), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dcb), 0xcd }, { CCI_REG8(0x3dcc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dcd), 0xcd }, { CCI_REG8(0x3dce), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dcf), 0xcd }, { CCI_REG8(0x3dd0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dd1), 0xcd }, { CCI_REG8(0x3dd2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dd3), 0xcd }, { CCI_REG8(0x3dd4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dd5), 0xcd }, { CCI_REG8(0x3dd6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dd7), 0xcd }, { CCI_REG8(0x3dd8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dd9), 0xcd }, { CCI_REG8(0x3dda), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ddb), 0xcd }, { CCI_REG8(0x3ddc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ddd), 0xcd }, { CCI_REG8(0x3dde), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ddf), 0xcd }, { CCI_REG8(0x3de0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3de1), 0xcd }, { CCI_REG8(0x3de2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3de3), 0xcd }, { CCI_REG8(0x3de4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3de5), 0xcd }, { CCI_REG8(0x3de6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3de7), 0xcd }, { CCI_REG8(0x3de8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3de9), 0xcd }, { CCI_REG8(0x3dea), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3deb), 0xcd }, { CCI_REG8(0x3dec), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3ded), 0xcd }, { CCI_REG8(0x3dee), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3def), 0xcd }, { CCI_REG8(0x3df0), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3df1), 0xcd }, { CCI_REG8(0x3df2), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3df3), 0xcd }, { CCI_REG8(0x3df4), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3df5), 0xcd }, { CCI_REG8(0x3df6), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3df7), 0xcd }, { CCI_REG8(0x3df8), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3df9), 0xcd }, { CCI_REG8(0x3dfa), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dfb), 0xcd }, { CCI_REG8(0x3dfc), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dfd), 0xcd }, { CCI_REG8(0x3dfe), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3dff), 0xcd }, { CCI_REG8(0x3e00), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e01), 0xcd }, { CCI_REG8(0x3e02), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e03), 0xcd }, { CCI_REG8(0x3e04), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e05), 0xcd }, { CCI_REG8(0x3e06), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e07), 0xcd }, { CCI_REG8(0x3e08), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e09), 0xcd }, { CCI_REG8(0x3e0a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e0b), 0xcd }, { CCI_REG8(0x3e0c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e0d), 0xcd }, { CCI_REG8(0x3e0e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e0f), 0xcd }, { CCI_REG8(0x3e10), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e11), 0xcd }, { CCI_REG8(0x3e12), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e13), 0xcd }, { CCI_REG8(0x3e14), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e15), 0xcd }, { CCI_REG8(0x3e16), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e17), 0xcd }, { CCI_REG8(0x3e18), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e19), 0xcd }, { CCI_REG8(0x3e1a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e1b), 0xcd }, { CCI_REG8(0x3e1c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e1d), 0xcd }, { CCI_REG8(0x3e1e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e1f), 0xcd }, { CCI_REG8(0x3e20), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e21), 0xcd }, { CCI_REG8(0x3e22), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e23), 0xcd }, { CCI_REG8(0x3e24), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e25), 0xcd }, { CCI_REG8(0x3e26), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e27), 0xcd }, { CCI_REG8(0x3e28), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e29), 0xcd }, { CCI_REG8(0x3e2a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e2b), 0xcd }, { CCI_REG8(0x3e2c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e2d), 0xcd }, { CCI_REG8(0x3e2e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e2f), 0xcd }, { CCI_REG8(0x3e30), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e31), 0xcd }, { CCI_REG8(0x3e32), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e33), 0xcd }, { CCI_REG8(0x3e34), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e35), 0xcd }, { CCI_REG8(0x3e36), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e37), 0xcd }, { CCI_REG8(0x3e38), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e39), 0xcd }, { CCI_REG8(0x3e3a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e3b), 0xcd }, { CCI_REG8(0x3e3c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e3d), 0xcd }, { CCI_REG8(0x3e3e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e3f), 0xcd }, { CCI_REG8(0x3e40), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e41), 0xcd }, { CCI_REG8(0x3e42), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e43), 0xcd }, { CCI_REG8(0x3e44), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e45), 0xcd }, { CCI_REG8(0x3e46), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e47), 0xcd }, { CCI_REG8(0x3e48), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e49), 0xcd }, { CCI_REG8(0x3e4a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e4b), 0xcd }, { CCI_REG8(0x3e4c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e4d), 0xcd }, { CCI_REG8(0x3e4e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e4f), 0xcd }, { CCI_REG8(0x3e50), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e51), 0xcd }, { CCI_REG8(0x3e52), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e53), 0xcd }, { CCI_REG8(0x3e54), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e55), 0xcd }, { CCI_REG8(0x3e56), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e57), 0xcd }, { CCI_REG8(0x3e58), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e59), 0xcd }, { CCI_REG8(0x3e5a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e5b), 0xcd }, { CCI_REG8(0x3e5c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e5d), 0xcd }, { CCI_REG8(0x3e5e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e5f), 0xcd }, { CCI_REG8(0x3e60), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e61), 0xcd }, { CCI_REG8(0x3e62), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e63), 0xcd }, { CCI_REG8(0x3e64), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e65), 0xcd }, { CCI_REG8(0x3e66), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e67), 0xcd }, { CCI_REG8(0x3e68), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e69), 0xcd }, { CCI_REG8(0x3e6a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e6b), 0xcd }, { CCI_REG8(0x3e6c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e6d), 0xcd }, { CCI_REG8(0x3e6e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e6f), 0xcd }, { CCI_REG8(0x3e70), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e71), 0xcd }, { CCI_REG8(0x3e72), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e73), 0xcd }, { CCI_REG8(0x3e74), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e75), 0xcd }, { CCI_REG8(0x3e76), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e77), 0xcd }, { CCI_REG8(0x3e78), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e79), 0xcd }, { CCI_REG8(0x3e7a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e7b), 0xcd }, { CCI_REG8(0x3e7c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e7d), 0xcd }, { CCI_REG8(0x3e7e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e7f), 0xcd }, { CCI_REG8(0x3e80), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e81), 0xcd }, { CCI_REG8(0x3e82), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e83), 0xcd }, { CCI_REG8(0x3e84), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e85), 0xcd }, { CCI_REG8(0x3e86), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e87), 0xcd }, { CCI_REG8(0x3e88), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e89), 0xcd }, { CCI_REG8(0x3e8a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e8b), 0xcd }, { CCI_REG8(0x3e8c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e8d), 0xcd }, { CCI_REG8(0x3e8e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e8f), 0xcd }, { CCI_REG8(0x3e90), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e91), 0xcd }, { CCI_REG8(0x3e92), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e93), 0xcd }, { CCI_REG8(0x3e94), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e95), 0xcd }, { CCI_REG8(0x3e96), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e97), 0xcd }, { CCI_REG8(0x3e98), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e99), 0xcd }, { CCI_REG8(0x3e9a), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e9b), 0xcd }, { CCI_REG8(0x3e9c), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e9d), 0xcd }, { CCI_REG8(0x3e9e), 0xcd },</div><div class='add'>+	{ CCI_REG8(0x3e9f), 0xcd }, { CCI_REG8(0xfff9), 0x06 },</div><div class='add'>+	{ CCI_REG8(0xc03f), 0x01 }, { CCI_REG8(0xc03e), 0x08 },</div><div class='add'>+	{ CCI_REG8(0xc02c), 0xff }, { CCI_REG8(0xc005), 0x06 },</div><div class='add'>+	{ CCI_REG8(0xc006), 0x30 }, { CCI_REG8(0xc007), 0xc0 },</div><div class='add'>+	{ CCI_REG8(0xc027), 0x01 }, { CCI_REG8(0x30c0), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x30c1), 0x9f }, { CCI_REG8(0x30c2), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x30c3), 0x5f }, { CCI_REG8(0x30c4), 0x80 },</div><div class='add'>+	{ CCI_REG8(0x30c5), 0x08 }, { CCI_REG8(0x30c6), 0x39 },</div><div class='add'>+	{ CCI_REG8(0x30c7), 0x00 }, { CCI_REG8(0xc046), 0x20 },</div><div class='add'>+	{ CCI_REG8(0xc043), 0x01 }, { CCI_REG8(0xc04b), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x0102), 0x01 }, { CCI_REG8(0x0100), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x0102), 0x00 }, { CCI_REG8(0x3015), 0xf0 },</div><div class='add'>+	{ CCI_REG8(0x3018), 0xf0 }, { CCI_REG8(0x301c), 0xf0 },</div><div class='add'>+	{ CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_9248x6944[] = {</div><div class='add'>+	{ CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },</div><div class='add'>+	{ CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },</div><div class='add'>+	{ CCI_REG8(0x5001), 0x21 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_8000x6000[] = {</div><div class='add'>+	{ CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },</div><div class='add'>+	{ CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },</div><div class='add'>+	{ CCI_REG8(0x5001), 0x21 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_4624_3472[] = {</div><div class='add'>+	{ CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },</div><div class='add'>+	{ CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 },</div><div class='add'>+	{ CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 },</div><div class='add'>+	{ CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 },</div><div class='add'>+	{ CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 },</div><div class='add'>+	{ CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 },</div><div class='add'>+	{ CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },</div><div class='add'>+	{ CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 },</div><div class='add'>+	{ CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 },</div><div class='add'>+	{ CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc },</div><div class='add'>+	{ CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 },</div><div class='add'>+	{ CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 },</div><div class='add'>+	{ CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 },</div><div class='add'>+	{ CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },</div><div class='add'>+	{ CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_3840x2160[] = {</div><div class='add'>+	{ CCI_REG8(0x034a), 0x05 }, { CCI_REG8(0x034b), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 },</div><div class='add'>+	{ CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 },</div><div class='add'>+	{ CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba },</div><div class='add'>+	{ CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f },</div><div class='add'>+	{ CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e },</div><div class='add'>+	{ CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c },</div><div class='add'>+	{ CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 },</div><div class='add'>+	{ CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 },</div><div class='add'>+	{ CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc },</div><div class='add'>+	{ CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 },</div><div class='add'>+	{ CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 },</div><div class='add'>+	{ CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 },</div><div class='add'>+	{ CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 },</div><div class='add'>+	{ CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 },</div><div class='add'>+	{ CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 },</div><div class='add'>+	{ CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 },</div><div class='add'>+	{ CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 },</div><div class='add'>+	{ CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x0345), 0x90 }, { CCI_REG8(0x0307), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },</div><div class='add'>+	{ CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 },</div><div class='add'>+	{ CCI_REG8(0x5000), 0x01 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_2312_1736[] = {</div><div class='add'>+	{ CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },</div><div class='add'>+	{ CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },</div><div class='add'>+	{ CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },</div><div class='add'>+	{ CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },</div><div class='add'>+	{ CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },</div><div class='add'>+	{ CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },</div><div class='add'>+	{ CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },</div><div class='add'>+	{ CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },</div><div class='add'>+	{ CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },</div><div class='add'>+	{ CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },</div><div class='add'>+	{ CCI_REG8(0x480C), 0x92 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct cci_reg_sequence ov64a40_1920x1080[] = {</div><div class='add'>+	{ CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },</div><div class='add'>+	{ CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },</div><div class='add'>+	{ CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },</div><div class='add'>+	{ CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },</div><div class='add'>+	{ CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },</div><div class='add'>+	{ CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },</div><div class='add'>+	{ CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },</div><div class='add'>+	{ CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },</div><div class='add'>+	{ CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },</div><div class='add'>+	{ CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },</div><div class='add'>+	{ CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },</div><div class='add'>+	{ CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },</div><div class='add'>+	{ CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },</div><div class='add'>+	{ CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },</div><div class='add'>+	{ CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },</div><div class='add'>+	{ CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },</div><div class='add'>+	{ CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },</div><div class='add'>+	{ CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },</div><div class='add'>+	{ CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },</div><div class='add'>+	{ CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },</div><div class='add'>+	{ CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },</div><div class='add'>+	{ CCI_REG8(0x480C), 0x92 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* 456MHz MIPI link frequency with 24MHz input clock. */</div><div class='add'>+static const struct cci_reg_sequence ov64a40_pll_config[] = {</div><div class='add'>+	{ OV64A40_PLL1_PRE_DIV0, 0x88 },</div><div class='add'>+	{ OV64A40_PLL1_PRE_DIV, 0x02 },</div><div class='add'>+	{ OV64A40_PLL1_MULTIPLIER, 0x0098 },</div><div class='add'>+	{ OV64A40_PLL1_M_DIV, 0x01 },</div><div class='add'>+	{ OV64A40_PLL2_SEL_BAK_SA1, 0x00 },</div><div class='add'>+	{ OV64A40_PLL2_PRE_DIV, 0x12 },</div><div class='add'>+	{ OV64A40_PLL2_MULTIPLIER, 0x0190 },</div><div class='add'>+	{ OV64A40_PLL2_PRE_DIV0, 0xd7 },</div><div class='add'>+	{ OV64A40_PLL2_DIVSP, 0x00 },</div><div class='add'>+	{ OV64A40_PLL2_DIVDAC, 0x00 },</div><div class='add'>+	{ OV64A40_PLL2_DACPREDIV, 0x00 }</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ov64a40_reglist {</div><div class='add'>+	unsigned int num_regs;</div><div class='add'>+	const struct cci_reg_sequence *regvals;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ov64a40_subsampling {</div><div class='add'>+	unsigned int x_odd_inc;</div><div class='add'>+	unsigned int x_even_inc;</div><div class='add'>+	unsigned int y_odd_inc;</div><div class='add'>+	unsigned int y_even_inc;</div><div class='add'>+	bool vbin;</div><div class='add'>+	bool hbin;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct ov64a40_mode {</div><div class='add'>+	unsigned int width;</div><div class='add'>+	unsigned int height;</div><div class='add'>+	struct ov64a40_timings {</div><div class='add'>+		unsigned int vts;</div><div class='add'>+		unsigned int ppl;</div><div class='add'>+	} timings_default[OV64A40_NUM_LINK_FREQ];</div><div class='add'>+	const struct ov64a40_reglist reglist;</div><div class='add'>+	struct v4l2_rect analogue_crop;</div><div class='add'>+	struct v4l2_rect digital_crop;</div><div class='add'>+	struct ov64a40_subsampling subsampling;</div><div class='add'>+} ov64a40_modes[] = {</div><div class='add'>+	/* Full resolution */</div><div class='add'>+	{</div><div class='add'>+		.width = 9248,</div><div class='add'>+		.height = 6944,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 2.6 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 7072,</div><div class='add'>+				.ppl = 4072,</div><div class='add'>+			},</div><div class='add'>+			/* 2 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 7072,</div><div class='add'>+				.ppl = 5248,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_9248x6944),</div><div class='add'>+			.regvals = ov64a40_9248x6944,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 0,</div><div class='add'>+			.top = 0,</div><div class='add'>+			.width = 9280,</div><div class='add'>+			.height = 6976,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 17,</div><div class='add'>+			.top = 16,</div><div class='add'>+			.width = 9248,</div><div class='add'>+			.height = 6944,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 1,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 1,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = false,</div><div class='add'>+			.hbin = false,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	/* Analogue crop + digital crop */</div><div class='add'>+	{</div><div class='add'>+		.width = 8000,</div><div class='add'>+		.height = 6000,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 3.0 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 6400,</div><div class='add'>+				.ppl = 3848,</div><div class='add'>+			},</div><div class='add'>+			/* 2.5 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 6304,</div><div class='add'>+				.ppl = 4736,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_8000x6000),</div><div class='add'>+			.regvals = ov64a40_8000x6000,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 624,</div><div class='add'>+			.top = 472,</div><div class='add'>+			.width = 8048,</div><div class='add'>+			.height = 6032,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 17,</div><div class='add'>+			.top = 16,</div><div class='add'>+			.width = 8000,</div><div class='add'>+			.height = 6000,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 1,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 1,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = false,</div><div class='add'>+			.hbin = false,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	/* 2x2 downscaled */</div><div class='add'>+	{</div><div class='add'>+		.width = 4624,</div><div class='add'>+		.height = 3472,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 10 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 3533,</div><div class='add'>+				.ppl = 2112,</div><div class='add'>+			},</div><div class='add'>+			/* 7 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 3939,</div><div class='add'>+				.ppl = 2720,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_4624_3472),</div><div class='add'>+			.regvals = ov64a40_4624_3472,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 0,</div><div class='add'>+			.top = 0,</div><div class='add'>+			.width = 9280,</div><div class='add'>+			.height = 6976,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 9,</div><div class='add'>+			.top = 8,</div><div class='add'>+			.width = 4624,</div><div class='add'>+			.height = 3472,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 3,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 1,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = true,</div><div class='add'>+			.hbin = false,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	/* Analogue crop + 2x2 downscale + digital crop */</div><div class='add'>+	{</div><div class='add'>+		.width = 3840,</div><div class='add'>+		.height = 2160,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 20 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 2218,</div><div class='add'>+				.ppl = 1690,</div><div class='add'>+			},</div><div class='add'>+			/* 15 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 2270,</div><div class='add'>+				.ppl = 2202,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_3840x2160),</div><div class='add'>+			.regvals = ov64a40_3840x2160,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 784,</div><div class='add'>+			.top = 1312,</div><div class='add'>+			.width = 7712,</div><div class='add'>+			.height = 4352,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 9,</div><div class='add'>+			.top = 8,</div><div class='add'>+			.width = 3840,</div><div class='add'>+			.height = 2160,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 3,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 1,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = true,</div><div class='add'>+			.hbin = false,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	/* 4x4 downscaled */</div><div class='add'>+	{</div><div class='add'>+		.width = 2312,</div><div class='add'>+		.height = 1736,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 30 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 1998,</div><div class='add'>+				.ppl = 1248,</div><div class='add'>+			},</div><div class='add'>+			/* 25 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 1994,</div><div class='add'>+				.ppl = 1504,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_2312_1736),</div><div class='add'>+			.regvals = ov64a40_2312_1736,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 0,</div><div class='add'>+			.top = 0,</div><div class='add'>+			.width = 9280,</div><div class='add'>+			.height = 6976,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 5,</div><div class='add'>+			.top = 4,</div><div class='add'>+			.width = 2312,</div><div class='add'>+			.height = 1736,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 3,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 3,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = true,</div><div class='add'>+			.hbin = true,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	/* Analogue crop + 4x4 downscale + digital crop */</div><div class='add'>+	{</div><div class='add'>+		.width = 1920,</div><div class='add'>+		.height = 1080,</div><div class='add'>+		.timings_default = {</div><div class='add'>+			/* 60 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_456M_ID] = {</div><div class='add'>+				.vts = 1397,</div><div class='add'>+				.ppl = 880,</div><div class='add'>+			},</div><div class='add'>+			/* 45 FPS */</div><div class='add'>+			[OV64A40_LINK_FREQ_360M_ID] = {</div><div class='add'>+				.vts = 1216,</div><div class='add'>+				.ppl = 1360,</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+		.reglist = {</div><div class='add'>+			.num_regs = ARRAY_SIZE(ov64a40_1920x1080),</div><div class='add'>+			.regvals = ov64a40_1920x1080,</div><div class='add'>+		},</div><div class='add'>+		.analogue_crop = {</div><div class='add'>+			.left = 784,</div><div class='add'>+			.top = 1312,</div><div class='add'>+			.width = 7712,</div><div class='add'>+			.height = 4352,</div><div class='add'>+		},</div><div class='add'>+		.digital_crop = {</div><div class='add'>+			.left = 7,</div><div class='add'>+			.top = 6,</div><div class='add'>+			.width = 1920,</div><div class='add'>+			.height = 1080,</div><div class='add'>+		},</div><div class='add'>+		.subsampling = {</div><div class='add'>+			.x_odd_inc = 3,</div><div class='add'>+			.x_even_inc = 1,</div><div class='add'>+			.y_odd_inc = 3,</div><div class='add'>+			.y_even_inc = 1,</div><div class='add'>+			.vbin = true,</div><div class='add'>+			.hbin = true,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ov64a40 {</div><div class='add'>+	struct device *dev;</div><div class='add'>+</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+</div><div class='add'>+	struct regmap *cci;</div><div class='add'>+</div><div class='add'>+	struct ov64a40_mode *mode;</div><div class='add'>+</div><div class='add'>+	struct clk *xclk;</div><div class='add'>+</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct regulator_bulk_data supplies[ARRAY_SIZE(ov64a40_supply_names)];</div><div class='add'>+</div><div class='add'>+	s64 *link_frequencies;</div><div class='add'>+	unsigned int num_link_frequencies;</div><div class='add'>+</div><div class='add'>+	struct v4l2_ctrl_handler ctrl_handler;</div><div class='add'>+	struct v4l2_ctrl *exposure;</div><div class='add'>+	struct v4l2_ctrl *link_freq;</div><div class='add'>+	struct v4l2_ctrl *vblank;</div><div class='add'>+	struct v4l2_ctrl *hblank;</div><div class='add'>+	struct v4l2_ctrl *vflip;</div><div class='add'>+	struct v4l2_ctrl *hflip;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	return container_of_const(sd, struct ov64a40, sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct ov64a40_timings *</div><div class='add'>+ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index)</div><div class='add'>+{</div><div class='add'>+	s64 link_freq = ov64a40-&gt;link_frequencies[link_freq_index];</div><div class='add'>+	unsigned int timings_index = link_freq == OV64A40_LINK_FREQ_360M</div><div class='add'>+				   ? OV64A40_LINK_FREQ_360M_ID</div><div class='add'>+				   : OV64A40_LINK_FREQ_456M_ID;</div><div class='add'>+</div><div class='add'>+	return &amp;ov64a40-&gt;mode-&gt;timings_default[timings_index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_program_geometry(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40_mode *mode = ov64a40-&gt;mode;</div><div class='add'>+	struct v4l2_rect *anacrop = &amp;mode-&gt;analogue_crop;</div><div class='add'>+	struct v4l2_rect *digicrop = &amp;mode-&gt;digital_crop;</div><div class='add'>+	const struct ov64a40_timings *timings;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Analogue crop. */</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL0,</div><div class='add'>+		  anacrop-&gt;left, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL2,</div><div class='add'>+		  anacrop-&gt;top, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL4,</div><div class='add'>+		  anacrop-&gt;width + anacrop-&gt;left - 1, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL6,</div><div class='add'>+		  anacrop-&gt;height + anacrop-&gt;top - 1, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* ISP windowing. */</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL10,</div><div class='add'>+		  digicrop-&gt;left, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL12,</div><div class='add'>+		  digicrop-&gt;top, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL8,</div><div class='add'>+		  digicrop-&gt;width, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRLA,</div><div class='add'>+		  digicrop-&gt;height, &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Total timings. */</div><div class='add'>+	timings = ov64a40_get_timings(ov64a40, ov64a40-&gt;link_freq-&gt;cur.val);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRLC, timings-&gt;ppl, &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRLE, timings-&gt;vts, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_program_subsampling(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40_subsampling *subsampling = &amp;ov64a40-&gt;mode-&gt;subsampling;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Skipping configuration */</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL14,</div><div class='add'>+		  OV64A40_SKIPPING_CONFIG(subsampling-&gt;x_odd_inc,</div><div class='add'>+					  subsampling-&gt;x_even_inc), &amp;ret);</div><div class='add'>+	cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL15,</div><div class='add'>+		  OV64A40_SKIPPING_CONFIG(subsampling-&gt;y_odd_inc,</div><div class='add'>+					  subsampling-&gt;y_even_inc), &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Binning configuration */</div><div class='add'>+	cci_update_bits(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL_20,</div><div class='add'>+			OV64A40_TIMING_CTRL_20_VBIN,</div><div class='add'>+			subsampling-&gt;vbin ? OV64A40_TIMING_CTRL_20_VBIN : 0,</div><div class='add'>+			&amp;ret);</div><div class='add'>+	cci_update_bits(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL_21,</div><div class='add'>+			OV64A40_TIMING_CTRL_21_HBIN_CONF,</div><div class='add'>+			subsampling-&gt;hbin ?</div><div class='add'>+			OV64A40_TIMING_CTRL_21_HBIN_CONF : 0, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_start_streaming(struct ov64a40 *ov64a40,</div><div class='add'>+				   struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	const struct ov64a40_reglist *reglist = &amp;ov64a40-&gt;mode-&gt;reglist;</div><div class='add'>+	const struct ov64a40_timings *timings;</div><div class='add'>+	unsigned long delay;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(ov64a40-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = cci_multi_reg_write(ov64a40-&gt;cci, ov64a40_init,</div><div class='add'>+				  ARRAY_SIZE(ov64a40_init), NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	ret = cci_multi_reg_write(ov64a40-&gt;cci, reglist-&gt;regvals,</div><div class='add'>+				  reglist-&gt;num_regs, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_program_geometry(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_program_subsampling(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	ret =  __v4l2_ctrl_handler_setup(&amp;ov64a40-&gt;ctrl_handler);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	ret = cci_write(ov64a40-&gt;cci, OV64A40_REG_SMIA,</div><div class='add'>+			OV64A40_REG_SMIA_STREAMING, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_power_off;</div><div class='add'>+</div><div class='add'>+	/* Link frequency and flips cannot change while streaming. */</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;link_freq, true);</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;vflip, true);</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;hflip, true);</div><div class='add'>+</div><div class='add'>+	/* delay: max(4096 xclk pulses, 150usec) + exposure time */</div><div class='add'>+	timings = ov64a40_get_timings(ov64a40, ov64a40-&gt;link_freq-&gt;cur.val);</div><div class='add'>+	delay = DIV_ROUND_UP(4096, OV64A40_XCLK_FREQ / 1000 / 1000);</div><div class='add'>+	delay = max(delay, 150ul);</div><div class='add'>+</div><div class='add'>+	/* The sensor has an internal x4 multiplier on the line length. */</div><div class='add'>+	delay += DIV_ROUND_UP(timings-&gt;ppl * 4 * ov64a40-&gt;exposure-&gt;cur.val,</div><div class='add'>+			      OV64A40_PIXEL_RATE / 1000 / 1000);</div><div class='add'>+	fsleep(delay);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_power_off:</div><div class='add'>+	pm_runtime_mark_last_busy(ov64a40-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(ov64a40-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_stop_streaming(struct ov64a40 *ov64a40,</div><div class='add'>+				  struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	cci_update_bits(ov64a40-&gt;cci, OV64A40_REG_SMIA, BIT(0), 0, NULL);</div><div class='add'>+	pm_runtime_mark_last_busy(ov64a40-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(ov64a40-&gt;dev);</div><div class='add'>+</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;link_freq, false);</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;vflip, false);</div><div class='add'>+	__v4l2_ctrl_grab(ov64a40-&gt;hflip, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='add'>+	if (enable)</div><div class='add'>+		ret = ov64a40_start_streaming(ov64a40, state);</div><div class='add'>+	else</div><div class='add'>+		ret = ov64a40_stop_streaming(ov64a40, state);</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops ov64a40_video_ops = {</div><div class='add'>+	.s_stream = ov64a40_set_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	unsigned int index = ov64a40-&gt;hflip-&gt;val &lt;&lt; 1 | ov64a40-&gt;vflip-&gt;val;</div><div class='add'>+</div><div class='add'>+	return ov64a40_mbus_codes[index];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40,</div><div class='add'>+				   struct ov64a40_mode *mode,</div><div class='add'>+				   struct v4l2_mbus_framefmt *fmt)</div><div class='add'>+{</div><div class='add'>+	fmt-&gt;code = ov64a40_mbus_code(ov64a40);</div><div class='add'>+	fmt-&gt;width = mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = mode-&gt;height;</div><div class='add'>+	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_RAW;</div><div class='add'>+	fmt-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='add'>+	fmt-&gt;xfer_func = V4L2_XFER_FUNC_NONE;</div><div class='add'>+	fmt-&gt;ycbcr_enc = V4L2_YCBCR_ENC_601;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *format;</div><div class='add'>+	struct v4l2_rect *crop;</div><div class='add'>+</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	ov64a40_update_pad_fmt(ov64a40, &amp;ov64a40_modes[0], format);</div><div class='add'>+</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 0);</div><div class='add'>+	crop-&gt;top = OV64A40_PIXEL_ARRAY_TOP;</div><div class='add'>+	crop-&gt;left = OV64A40_PIXEL_ARRAY_LEFT;</div><div class='add'>+	crop-&gt;width = OV64A40_PIXEL_ARRAY_WIDTH;</div><div class='add'>+	crop-&gt;height = OV64A40_PIXEL_ARRAY_HEIGHT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *state,</div><div class='add'>+				  struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+</div><div class='add'>+	if (code-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = ov64a40_mbus_code(ov64a40);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_enum_frame_size(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *state,</div><div class='add'>+				   struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+	struct ov64a40_mode *mode;</div><div class='add'>+	u32 code;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index &gt;= ARRAY_SIZE(ov64a40_modes))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code = ov64a40_mbus_code(ov64a40);</div><div class='add'>+	if (fse-&gt;code != code)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mode = &amp;ov64a40_modes[fse-&gt;index];</div><div class='add'>+	fse-&gt;min_width = mode-&gt;width;</div><div class='add'>+	fse-&gt;max_width = mode-&gt;width;</div><div class='add'>+	fse-&gt;min_height = mode-&gt;height;</div><div class='add'>+	fse-&gt;max_height = mode-&gt;height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_get_selection(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *state,</div><div class='add'>+				 struct v4l2_subdev_selection *sel)</div><div class='add'>+{</div><div class='add'>+	switch (sel-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(state, 0);</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_NATIVE_SIZE:</div><div class='add'>+		sel-&gt;r.top = 0;</div><div class='add'>+		sel-&gt;r.left = 0;</div><div class='add'>+		sel-&gt;r.width = OV64A40_NATIVE_WIDTH;</div><div class='add'>+		sel-&gt;r.height = OV64A40_NATIVE_HEIGHT;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+		sel-&gt;r.top = OV64A40_PIXEL_ARRAY_TOP;</div><div class='add'>+		sel-&gt;r.left = OV64A40_PIXEL_ARRAY_LEFT;</div><div class='add'>+		sel-&gt;r.width = OV64A40_PIXEL_ARRAY_WIDTH;</div><div class='add'>+		sel-&gt;r.height = OV64A40_PIXEL_ARRAY_HEIGHT;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_set_format(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *state,</div><div class='add'>+			      struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *format;</div><div class='add'>+	struct ov64a40_mode *mode;</div><div class='add'>+</div><div class='add'>+	mode = v4l2_find_nearest_size(ov64a40_modes,</div><div class='add'>+				      ARRAY_SIZE(ov64a40_modes),</div><div class='add'>+				      width, height,</div><div class='add'>+				      fmt-&gt;format.width, fmt-&gt;format.height);</div><div class='add'>+</div><div class='add'>+	ov64a40_update_pad_fmt(ov64a40, mode, &amp;fmt-&gt;format);</div><div class='add'>+</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	if (ov64a40-&gt;mode == mode &amp;&amp; format-&gt;code == fmt-&gt;format.code)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE) {</div><div class='add'>+		const struct ov64a40_timings *timings;</div><div class='add'>+		int vblank_max, vblank_def;</div><div class='add'>+		int hblank_val;</div><div class='add'>+		int exp_max;</div><div class='add'>+</div><div class='add'>+		ov64a40-&gt;mode = mode;</div><div class='add'>+		*v4l2_subdev_state_get_crop(state, 0) = mode-&gt;analogue_crop;</div><div class='add'>+</div><div class='add'>+		/* Update control limits according to the new mode. */</div><div class='add'>+		timings = ov64a40_get_timings(ov64a40,</div><div class='add'>+					      ov64a40-&gt;link_freq-&gt;cur.val);</div><div class='add'>+		vblank_max = OV64A40_VTS_MAX - mode-&gt;height;</div><div class='add'>+		vblank_def = timings-&gt;vts - mode-&gt;height;</div><div class='add'>+		__v4l2_ctrl_modify_range(ov64a40-&gt;vblank, OV64A40_VBLANK_MIN,</div><div class='add'>+					 vblank_max, 1, vblank_def);</div><div class='add'>+		__v4l2_ctrl_s_ctrl(ov64a40-&gt;vblank, vblank_def);</div><div class='add'>+</div><div class='add'>+		exp_max = timings-&gt;vts - OV64A40_EXPOSURE_MARGIN;</div><div class='add'>+		__v4l2_ctrl_modify_range(ov64a40-&gt;exposure,</div><div class='add'>+					 OV64A40_EXPOSURE_MIN, exp_max,</div><div class='add'>+					 1, OV64A40_EXPOSURE_MIN);</div><div class='add'>+</div><div class='add'>+		hblank_val = timings-&gt;ppl * 4 - mode-&gt;width;</div><div class='add'>+		__v4l2_ctrl_modify_range(ov64a40-&gt;hblank,</div><div class='add'>+					 hblank_val, hblank_val, 1, hblank_val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*format = fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops ov64a40_pad_ops = {</div><div class='add'>+	.enum_mbus_code = ov64a40_enum_mbus_code,</div><div class='add'>+	.enum_frame_size = ov64a40_enum_frame_size,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt = ov64a40_set_format,</div><div class='add'>+	.get_selection = ov64a40_get_selection,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops ov64a40_core_ops = {</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops ov64a40_subdev_ops = {</div><div class='add'>+	.core = &amp;ov64a40_core_ops,</div><div class='add'>+	.video = &amp;ov64a40_video_ops,</div><div class='add'>+	.pad = &amp;ov64a40_pad_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops ov64a40_internal_ops = {</div><div class='add'>+	.init_state = ov64a40_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ov64a40_power_on(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(ov64a40-&gt;xclk);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_bulk_enable(ARRAY_SIZE(ov64a40_supply_names),</div><div class='add'>+				    ov64a40-&gt;supplies);</div><div class='add'>+	if (ret) {</div><div class='add'>+		clk_disable_unprepare(ov64a40-&gt;xclk);</div><div class='add'>+		dev_err(dev, "Failed to enable regulators: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(ov64a40-&gt;reset_gpio, 0);</div><div class='add'>+</div><div class='add'>+	fsleep(5000);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_power_off(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(ov64a40-&gt;reset_gpio, 1);</div><div class='add'>+	regulator_bulk_disable(ARRAY_SIZE(ov64a40_supply_names),</div><div class='add'>+			       ov64a40-&gt;supplies);</div><div class='add'>+	clk_disable_unprepare(ov64a40-&gt;xclk);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id)</div><div class='add'>+{</div><div class='add'>+	s64 link_frequency;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Default 456MHz with 24MHz input clock. */</div><div class='add'>+	cci_multi_reg_write(ov64a40-&gt;cci, ov64a40_pll_config,</div><div class='add'>+			    ARRAY_SIZE(ov64a40_pll_config), &amp;ret);</div><div class='add'>+</div><div class='add'>+	/* Decrease the PLL1 multiplier to obtain 360MHz mipi link frequency. */</div><div class='add'>+	link_frequency = ov64a40-&gt;link_frequencies[link_freq_id];</div><div class='add'>+	if (link_frequency == OV64A40_LINK_FREQ_360M)</div><div class='add'>+		cci_write(ov64a40-&gt;cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &amp;ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40 = container_of(ctrl-&gt;handler, struct ov64a40,</div><div class='add'>+					       ctrl_handler);</div><div class='add'>+	int pm_status;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (ctrl-&gt;id == V4L2_CID_VBLANK) {</div><div class='add'>+		int exp_max = ov64a40-&gt;mode-&gt;height + ctrl-&gt;val</div><div class='add'>+			    - OV64A40_EXPOSURE_MARGIN;</div><div class='add'>+		int exp_val = min(ov64a40-&gt;exposure-&gt;cur.val, exp_max);</div><div class='add'>+</div><div class='add'>+		__v4l2_ctrl_modify_range(ov64a40-&gt;exposure,</div><div class='add'>+					 ov64a40-&gt;exposure-&gt;minimum,</div><div class='add'>+					 exp_max, 1, exp_val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_status = pm_runtime_get_if_active(ov64a40-&gt;dev, true);</div><div class='add'>+	if (!pm_status)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_EXPOSURE:</div><div class='add'>+		ret = cci_write(ov64a40-&gt;cci, OV64A40_REG_MEC_LONG_EXPO,</div><div class='add'>+				ctrl-&gt;val, NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_ANALOGUE_GAIN:</div><div class='add'>+		ret = cci_write(ov64a40-&gt;cci, OV64A40_REG_MEC_LONG_GAIN,</div><div class='add'>+				ctrl-&gt;val &lt;&lt; 1, NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_VBLANK: {</div><div class='add'>+		int vts = ctrl-&gt;val + ov64a40-&gt;mode-&gt;height;</div><div class='add'>+</div><div class='add'>+		cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &amp;ret);</div><div class='add'>+		cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMINGS_VTS_MID,</div><div class='add'>+			  (vts &gt;&gt; 8), &amp;ret);</div><div class='add'>+		cci_write(ov64a40-&gt;cci, OV64A40_REG_TIMINGS_VTS_HIGH,</div><div class='add'>+			  (vts &gt;&gt; 16), &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+		ret = cci_update_bits(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL_20,</div><div class='add'>+				      OV64A40_TIMING_CTRL_20_VFLIP,</div><div class='add'>+				      ctrl-&gt;val &lt;&lt; 2,</div><div class='add'>+				      NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+		ret = cci_update_bits(ov64a40-&gt;cci, OV64A40_REG_TIMING_CTRL_21,</div><div class='add'>+				      OV64A40_TIMING_CTRL_21_HFLIP,</div><div class='add'>+				      ctrl-&gt;val ? 0</div><div class='add'>+						: OV64A40_TIMING_CTRL_21_HFLIP,</div><div class='add'>+				      NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_TEST_PATTERN:</div><div class='add'>+		ret = cci_write(ov64a40-&gt;cci, OV64A40_REG_TEST_PATTERN,</div><div class='add'>+				ov64a40_test_pattern_val[ctrl-&gt;val], NULL);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_LINK_FREQ:</div><div class='add'>+		ret = ov64a40_link_freq_config(ov64a40, ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "Unhandled control: %#x\n", ctrl-&gt;id);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pm_status &gt; 0) {</div><div class='add'>+		pm_runtime_mark_last_busy(ov64a40-&gt;dev);</div><div class='add'>+		pm_runtime_put_autosuspend(ov64a40-&gt;dev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops ov64a40_ctrl_ops = {</div><div class='add'>+	.s_ctrl = ov64a40_set_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ov64a40_init_controls(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	int exp_max, hblank_val, vblank_max, vblank_def;</div><div class='add'>+	struct v4l2_ctrl_handler *hdlr = &amp;ov64a40-&gt;ctrl_handler;</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='add'>+	const struct ov64a40_timings *timings;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_handler_init(hdlr, 11);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops, V4L2_CID_PIXEL_RATE,</div><div class='add'>+			  OV64A40_PIXEL_RATE, OV64A40_PIXEL_RATE,  1,</div><div class='add'>+			  OV64A40_PIXEL_RATE);</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;link_freq =</div><div class='add'>+		v4l2_ctrl_new_int_menu(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+				       V4L2_CID_LINK_FREQ,</div><div class='add'>+				       ov64a40-&gt;num_link_frequencies - 1,</div><div class='add'>+				       0, ov64a40-&gt;link_frequencies);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std_menu_items(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+				     V4L2_CID_TEST_PATTERN,</div><div class='add'>+				     ARRAY_SIZE(ov64a40_test_pattern_menu) - 1,</div><div class='add'>+				     0, 0, ov64a40_test_pattern_menu);</div><div class='add'>+</div><div class='add'>+	timings = ov64a40_get_timings(ov64a40, 0);</div><div class='add'>+	exp_max = timings-&gt;vts - OV64A40_EXPOSURE_MARGIN;</div><div class='add'>+	ov64a40-&gt;exposure = v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					      V4L2_CID_EXPOSURE,</div><div class='add'>+					      OV64A40_EXPOSURE_MIN, exp_max, 1,</div><div class='add'>+					      OV64A40_EXPOSURE_MIN);</div><div class='add'>+</div><div class='add'>+	hblank_val = timings-&gt;ppl * 4 - ov64a40-&gt;mode-&gt;width;</div><div class='add'>+	ov64a40-&gt;hblank = v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					    V4L2_CID_HBLANK, hblank_val,</div><div class='add'>+					    hblank_val, 1, hblank_val);</div><div class='add'>+	if (ov64a40-&gt;hblank)</div><div class='add'>+		ov64a40-&gt;hblank-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	vblank_def = timings-&gt;vts - ov64a40-&gt;mode-&gt;height;</div><div class='add'>+	vblank_max = OV64A40_VTS_MAX - ov64a40-&gt;mode-&gt;height;</div><div class='add'>+	ov64a40-&gt;vblank = v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					    V4L2_CID_VBLANK, OV64A40_VBLANK_MIN,</div><div class='add'>+					    vblank_max, 1, vblank_def);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,</div><div class='add'>+			  OV64A40_ANA_GAIN_MIN, OV64A40_ANA_GAIN_MAX, 1,</div><div class='add'>+			  OV64A40_ANA_GAIN_DEFAULT);</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;hflip = v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					   V4L2_CID_HFLIP, 0, 1, 1, 0);</div><div class='add'>+	if (ov64a40-&gt;hflip)</div><div class='add'>+		ov64a40-&gt;hflip-&gt;flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;vflip = v4l2_ctrl_new_std(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					   V4L2_CID_VFLIP, 0, 1, 1, 0);</div><div class='add'>+	if (ov64a40-&gt;vflip)</div><div class='add'>+		ov64a40-&gt;vflip-&gt;flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;</div><div class='add'>+</div><div class='add'>+	if (hdlr-&gt;error) {</div><div class='add'>+		ret = hdlr-&gt;error;</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "control init failed: %d\n", ret);</div><div class='add'>+		goto error_free_hdlr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_device_parse(ov64a40-&gt;dev, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_free_hdlr;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_new_fwnode_properties(hdlr, &amp;ov64a40_ctrl_ops,</div><div class='add'>+					      &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_free_hdlr;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;sd.ctrl_handler = hdlr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_free_hdlr:</div><div class='add'>+	v4l2_ctrl_handler_free(hdlr);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_identify(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u64 id;</div><div class='add'>+</div><div class='add'>+	ret = cci_read(ov64a40-&gt;cci, OV64A40_REG_CHIP_ID, &amp;id, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "Failed to read chip id: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (id != OV64A40_CHIP_ID) {</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "chip id mismatch: %#llx\n", id);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(ov64a40-&gt;dev, "OV64A40 chip identified: %#llx\n", id);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_parse_dt(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_fwnode_endpoint v4l2_fwnode = {</div><div class='add'>+		.bus_type = V4L2_MBUS_CSI2_DPHY</div><div class='add'>+	};</div><div class='add'>+	struct fwnode_handle *endpoint;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40-&gt;dev),</div><div class='add'>+						  NULL);</div><div class='add'>+	if (!endpoint) {</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "Failed to find endpoint\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &amp;v4l2_fwnode);</div><div class='add'>+	fwnode_handle_put(endpoint);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "Failed to parse endpoint\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (v4l2_fwnode.bus.mipi_csi2.num_data_lanes != 2) {</div><div class='add'>+		dev_err(ov64a40-&gt;dev, "Unsupported number of data lanes: %u\n",</div><div class='add'>+			v4l2_fwnode.bus.mipi_csi2.num_data_lanes);</div><div class='add'>+		v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!v4l2_fwnode.nr_of_link_frequencies) {</div><div class='add'>+		dev_warn(ov64a40-&gt;dev, "no link frequencies defined\n");</div><div class='add'>+		v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (v4l2_fwnode.nr_of_link_frequencies &gt; 2) {</div><div class='add'>+		dev_warn(ov64a40-&gt;dev,</div><div class='add'>+			 "Unsupported number of link frequencies\n");</div><div class='add'>+		v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;link_frequencies =</div><div class='add'>+		devm_kcalloc(ov64a40-&gt;dev, v4l2_fwnode.nr_of_link_frequencies,</div><div class='add'>+			     sizeof(v4l2_fwnode.link_frequencies[0]),</div><div class='add'>+			     GFP_KERNEL);</div><div class='add'>+	if (!ov64a40-&gt;link_frequencies)  {</div><div class='add'>+		v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	ov64a40-&gt;num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; v4l2_fwnode.nr_of_link_frequencies; ++i) {</div><div class='add'>+		if (v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_360M &amp;&amp;</div><div class='add'>+		    v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_456M) {</div><div class='add'>+			dev_err(ov64a40-&gt;dev,</div><div class='add'>+				"Unsupported link frequency %lld\n",</div><div class='add'>+				v4l2_fwnode.link_frequencies[i]);</div><div class='add'>+			v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ov64a40-&gt;link_frequencies[i] = v4l2_fwnode.link_frequencies[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_fwnode_endpoint_free(&amp;v4l2_fwnode);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_get_regulators(struct ov64a40 *ov64a40)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = v4l2_get_subdevdata(&amp;ov64a40-&gt;sd);</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(ov64a40_supply_names); i++)</div><div class='add'>+		ov64a40-&gt;supplies[i].supply = ov64a40_supply_names[i];</div><div class='add'>+</div><div class='add'>+	return devm_regulator_bulk_get(&amp;client-&gt;dev,</div><div class='add'>+				       ARRAY_SIZE(ov64a40_supply_names),</div><div class='add'>+				       ov64a40-&gt;supplies);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ov64a40_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct ov64a40 *ov64a40;</div><div class='add'>+	u32 xclk_freq;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ov64a40 = devm_kzalloc(&amp;client-&gt;dev, sizeof(*ov64a40), GFP_KERNEL);</div><div class='add'>+	if (!ov64a40)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;dev = &amp;client-&gt;dev;</div><div class='add'>+	v4l2_i2c_subdev_init(&amp;ov64a40-&gt;sd, client, &amp;ov64a40_subdev_ops);</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;cci = devm_cci_regmap_init_i2c(client, 16);</div><div class='add'>+	if (IS_ERR(ov64a40-&gt;cci)) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Failed to initialize CCI\n");</div><div class='add'>+		return PTR_ERR(ov64a40-&gt;cci);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;xclk = devm_clk_get(&amp;client-&gt;dev, NULL);</div><div class='add'>+	if (IS_ERR(ov64a40-&gt;xclk))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(ov64a40-&gt;xclk),</div><div class='add'>+				     "Failed to get clock\n");</div><div class='add'>+</div><div class='add'>+	xclk_freq = clk_get_rate(ov64a40-&gt;xclk);</div><div class='add'>+	if (xclk_freq != OV64A40_XCLK_FREQ) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Unsupported xclk frequency %u\n",</div><div class='add'>+			xclk_freq);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_get_regulators(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;reset_gpio = devm_gpiod_get_optional(&amp;client-&gt;dev, "reset",</div><div class='add'>+						      GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(ov64a40-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, PTR_ERR(ov64a40-&gt;reset_gpio),</div><div class='add'>+				     "Failed to get reset gpio\n");</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_parse_dt(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_power_on(&amp;client-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_identify(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_poweroff;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;mode = &amp;ov64a40_modes[0];</div><div class='add'>+</div><div class='add'>+	pm_runtime_set_active(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_get_noresume(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_enable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_autosuspend_delay(&amp;client-&gt;dev, 1000);</div><div class='add'>+	pm_runtime_use_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	ret = ov64a40_init_controls(ov64a40);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error_poweroff;</div><div class='add'>+</div><div class='add'>+	/* Initialize subdev */</div><div class='add'>+	ov64a40-&gt;sd.internal_ops = &amp;ov64a40_internal_ops;</div><div class='add'>+	ov64a40-&gt;sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE</div><div class='add'>+			  | V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+	ov64a40-&gt;sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+	ret = media_entity_pads_init(&amp;ov64a40-&gt;sd.entity, 1, &amp;ov64a40-&gt;pad);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to init entity pads: %d\n", ret);</div><div class='add'>+		goto error_handler_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ov64a40-&gt;sd.state_lock = ov64a40-&gt;ctrl_handler.lock;</div><div class='add'>+	ret = v4l2_subdev_init_finalize(&amp;ov64a40-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "subdev init error: %d\n", ret);</div><div class='add'>+		goto error_media_entity;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;ov64a40-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev,</div><div class='add'>+			"failed to register sensor sub-device: %d\n", ret);</div><div class='add'>+		goto error_subdev_cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_subdev_cleanup:</div><div class='add'>+	v4l2_subdev_cleanup(&amp;ov64a40-&gt;sd);</div><div class='add'>+error_media_entity:</div><div class='add'>+	media_entity_cleanup(&amp;ov64a40-&gt;sd.entity);</div><div class='add'>+error_handler_free:</div><div class='add'>+	v4l2_ctrl_handler_free(ov64a40-&gt;sd.ctrl_handler);</div><div class='add'>+error_poweroff:</div><div class='add'>+	ov64a40_power_off(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ov64a40_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+</div><div class='add'>+	v4l2_async_unregister_subdev(sd);</div><div class='add'>+	v4l2_subdev_cleanup(sd);</div><div class='add'>+	media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='add'>+	v4l2_ctrl_handler_free(sd-&gt;ctrl_handler);</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	if (!pm_runtime_status_suspended(&amp;client-&gt;dev))</div><div class='add'>+		ov64a40_power_off(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id ov64a40_of_ids[] = {</div><div class='add'>+	{ .compatible = "ovti,ov64a40" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, ov64a40_of_ids);</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops ov64a40_pm_ops = {</div><div class='add'>+	SET_RUNTIME_PM_OPS(ov64a40_power_off, ov64a40_power_on, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct i2c_driver ov64a40_i2c_driver = {</div><div class='add'>+	.driver	= {</div><div class='add'>+		.name = "ov64a40",</div><div class='add'>+		.of_match_table	= ov64a40_of_ids,</div><div class='add'>+		.pm = &amp;ov64a40_pm_ops,</div><div class='add'>+	},</div><div class='add'>+	.probe	= ov64a40_probe,</div><div class='add'>+	.remove	= ov64a40_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(ov64a40_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Jacopo Mondi &lt;jacopo.mondi@ideasonboard.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("OmniVision OV64A40 sensor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/ov6650.c b/drivers/media/i2c/ov6650.c<br/>index 1ad07935f046..b65befb22a79 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov6650.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov6650.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov6650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov6650.c</a></div><div class='hunk'>@@ -197,7 +197,7 @@ struct ov6650 {</div><div class='ctx'> 	struct clk		*clk;</div><div class='ctx'> 	bool			half_scale;	/* scale down output by 2 */</div><div class='ctx'> 	struct v4l2_rect	rect;		/* sensor cropping window */</div><div class='del'>-	struct v4l2_fract	tpf;		/* as requested with s_frame_interval */</div><div class='add'>+	struct v4l2_fract	tpf;		/* as requested with set_frame_interval */</div><div class='ctx'> 	u32 code;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -476,7 +476,7 @@ static int ov6650_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		/* pre-select try crop rectangle */</div><div class='del'>-		rect = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='add'>+		rect = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* pre-select active crop rectangle */</div><div class='hunk'>@@ -531,8 +531,10 @@ static int ov6650_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	ov6650_bind_align_crop_rectangle(&amp;sel-&gt;r);</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		struct v4l2_rect *crop = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='del'>-		struct v4l2_mbus_framefmt *mf = &amp;sd_state-&gt;pads-&gt;try_fmt;</div><div class='add'>+		struct v4l2_rect *crop =</div><div class='add'>+			v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='add'>+		struct v4l2_mbus_framefmt *mf =</div><div class='add'>+			v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		/* detect current pad config scaling factor */</div><div class='ctx'> 		bool half_scale = !is_unscaled_ok(mf-&gt;width, mf-&gt;height, crop);</div><div class='ctx'> </div><div class='hunk'>@@ -588,9 +590,12 @@ static int ov6650_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	/* update media bus format code and frame size */</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf-&gt;width = sd_state-&gt;pads-&gt;try_fmt.width;</div><div class='del'>-		mf-&gt;height = sd_state-&gt;pads-&gt;try_fmt.height;</div><div class='del'>-		mf-&gt;code = sd_state-&gt;pads-&gt;try_fmt.code;</div><div class='add'>+		struct v4l2_mbus_framefmt *try_fmt =</div><div class='add'>+			v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+</div><div class='add'>+		mf-&gt;width = try_fmt-&gt;width;</div><div class='add'>+		mf-&gt;height = try_fmt-&gt;height;</div><div class='add'>+		mf-&gt;code = try_fmt-&gt;code;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		mf-&gt;width = priv-&gt;rect.width &gt;&gt; priv-&gt;half_scale;</div><div class='hunk'>@@ -717,23 +722,26 @@ static int ov6650_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		crop = &amp;sd_state-&gt;pads-&gt;try_crop;</div><div class='add'>+		crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='ctx'> 	else</div><div class='ctx'> 		crop = &amp;priv-&gt;rect;</div><div class='ctx'> </div><div class='ctx'> 	half_scale = !is_unscaled_ok(mf-&gt;width, mf-&gt;height, crop);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='add'>+		struct v4l2_mbus_framefmt *try_fmt =</div><div class='add'>+			v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+</div><div class='ctx'> 		/* store new mbus frame format code and size in pad config */</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt.width = crop-&gt;width &gt;&gt; half_scale;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt.height = crop-&gt;height &gt;&gt; half_scale;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt.code = mf-&gt;code;</div><div class='add'>+		try_fmt-&gt;width = crop-&gt;width &gt;&gt; half_scale;</div><div class='add'>+		try_fmt-&gt;height = crop-&gt;height &gt;&gt; half_scale;</div><div class='add'>+		try_fmt-&gt;code = mf-&gt;code;</div><div class='ctx'> </div><div class='ctx'> 		/* return default mbus frame format updated with pad config */</div><div class='ctx'> 		*mf = ov6650_def_fmt;</div><div class='del'>-		mf-&gt;width = sd_state-&gt;pads-&gt;try_fmt.width;</div><div class='del'>-		mf-&gt;height = sd_state-&gt;pads-&gt;try_fmt.height;</div><div class='del'>-		mf-&gt;code = sd_state-&gt;pads-&gt;try_fmt.code;</div><div class='add'>+		mf-&gt;width = try_fmt-&gt;width;</div><div class='add'>+		mf-&gt;height = try_fmt-&gt;height;</div><div class='add'>+		mf-&gt;code = try_fmt-&gt;code;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		int ret = 0;</div><div class='hunk'>@@ -791,12 +799,20 @@ static int ov6650_enum_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov6650_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov6650_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='ctx'> 	struct ov6650 *priv = to_ov6650(client);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	ival-&gt;interval = priv-&gt;tpf;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;client-&gt;dev, "Frame interval: %u/%u s\n",</div><div class='hunk'>@@ -805,14 +821,22 @@ static int ov6650_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov6650_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov6650_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = v4l2_get_subdevdata(sd);</div><div class='ctx'> 	struct ov6650 *priv = to_ov6650(client);</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> 	int div, ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (tpf-&gt;numerator == 0 || tpf-&gt;denominator == 0)</div><div class='ctx'> 		div = 1;  /* Reset to full rate */</div><div class='ctx'> 	else</div><div class='hunk'>@@ -998,8 +1022,6 @@ static int ov6650_get_mbus_config(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov6650_video_ops = {</div><div class='ctx'> 	.s_stream	= ov6650_s_stream,</div><div class='del'>-	.g_frame_interval = ov6650_g_frame_interval,</div><div class='del'>-	.s_frame_interval = ov6650_s_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {</div><div class='hunk'>@@ -1009,6 +1031,8 @@ static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {</div><div class='ctx'> 	.set_selection		= ov6650_set_selection,</div><div class='ctx'> 	.get_fmt		= ov6650_get_fmt,</div><div class='ctx'> 	.set_fmt		= ov6650_set_fmt,</div><div class='add'>+	.get_frame_interval	= ov6650_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= ov6650_set_frame_interval,</div><div class='ctx'> 	.get_mbus_config	= ov6650_get_mbus_config,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov7251.c b/drivers/media/i2c/ov7251.c<br/>index 6582cc0e2384..30f61e04ecaf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7251.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov7251.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7251.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7251.c</a></div><div class='hunk'>@@ -1139,7 +1139,7 @@ __ov7251_get_pad_format(struct ov7251 *ov7251,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;ov7251-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov7251-&gt;fmt;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1169,7 +1169,7 @@ __ov7251_get_pad_crop(struct ov7251 *ov7251,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov7251-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov7251-&gt;crop;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1282,8 +1282,8 @@ exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov7251_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov7251_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY</div><div class='hunk'>@@ -1386,10 +1386,18 @@ err_power_down:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov7251 *ov7251 = to_ov7251(subdev);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;ov7251-&gt;lock);</div><div class='ctx'> 	fi-&gt;interval = ov7251-&gt;current_mode-&gt;timeperframe;</div><div class='ctx'> 	mutex_unlock(&amp;ov7251-&gt;lock);</div><div class='hunk'>@@ -1398,12 +1406,20 @@ static int ov7251_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ov7251_set_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov7251 *ov7251 = to_ov7251(subdev);</div><div class='ctx'> 	const struct ov7251_mode_info *new_mode;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;ov7251-&gt;lock);</div><div class='ctx'> 	new_mode = ov7251_find_mode_by_ival(ov7251, &amp;fi-&gt;interval);</div><div class='ctx'> </div><div class='hunk'>@@ -1436,18 +1452,17 @@ exit:</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov7251_video_ops = {</div><div class='ctx'> 	.s_stream = ov7251_s_stream,</div><div class='del'>-	.g_frame_interval = ov7251_get_frame_interval,</div><div class='del'>-	.s_frame_interval = ov7251_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov7251_subdev_pad_ops = {</div><div class='del'>-	.init_cfg = ov7251_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov7251_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov7251_enum_frame_size,</div><div class='ctx'> 	.enum_frame_interval = ov7251_enum_frame_ival,</div><div class='ctx'> 	.get_fmt = ov7251_get_format,</div><div class='ctx'> 	.set_fmt = ov7251_set_format,</div><div class='ctx'> 	.get_selection = ov7251_get_selection,</div><div class='add'>+	.get_frame_interval = ov7251_get_frame_interval,</div><div class='add'>+	.set_frame_interval = ov7251_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov7251_subdev_ops = {</div><div class='hunk'>@@ -1455,6 +1470,10 @@ static const struct v4l2_subdev_ops ov7251_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov7251_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {</div><div class='add'>+	.init_state = ov7251_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int ov7251_check_hwcfg(struct ov7251 *ov7251)</div><div class='ctx'> {</div><div class='ctx'> 	struct fwnode_handle *fwnode = dev_fwnode(ov7251-&gt;dev);</div><div class='hunk'>@@ -1693,6 +1712,7 @@ static int ov7251_probe(struct i2c_client *client)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov7251-&gt;sd, client, &amp;ov7251_subdev_ops);</div><div class='add'>+	ov7251-&gt;sd.internal_ops = &amp;ov7251_internal_ops;</div><div class='ctx'> 	ov7251-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	ov7251-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='ctx'> 	ov7251-&gt;sd.dev = &amp;client-&gt;dev;</div><div class='hunk'>@@ -1750,7 +1770,7 @@ static int ov7251_probe(struct i2c_client *client)</div><div class='ctx'> 		goto free_entity;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ov7251_entity_init_cfg(&amp;ov7251-&gt;sd, NULL);</div><div class='add'>+	ov7251_init_state(&amp;ov7251-&gt;sd, NULL);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c<br/>index 172483597c54..0cb96b6c9990 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7670.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov7670.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7670.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7670.c</a></div><div class='hunk'>@@ -1112,8 +1112,7 @@ static int ov7670_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		ret = ov7670_try_fmt_internal(sd, &amp;format-&gt;format, NULL, NULL);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='del'>-		mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-						      format-&gt;pad);</div><div class='add'>+		mbus_fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		*mbus_fmt = format-&gt;format;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1141,7 +1140,7 @@ static int ov7670_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbus_fmt;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mbus_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		format-&gt;format = *mbus_fmt;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1155,23 +1154,37 @@ static int ov7670_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'>  * Implement G/S_PARM.  There is a "high quality" mode we could try</div><div class='ctx'>  * to do someday; for now, we just do the frame rate tweak.</div><div class='ctx'>  */</div><div class='del'>-static int ov7670_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov7670_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov7670_info *info = to_state(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;devtype-&gt;get_framerate(sd, &amp;ival-&gt;interval);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov7670_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov7670_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> 	struct ov7670_info *info = to_state(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return info-&gt;devtype-&gt;set_framerate(sd, tpf);</div><div class='ctx'> }</div><div class='hunk'>@@ -1707,7 +1720,7 @@ static void ov7670_get_default_format(struct v4l2_subdev *sd,</div><div class='ctx'> static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	ov7670_get_default_format(sd, format);</div><div class='ctx'> </div><div class='hunk'>@@ -1729,22 +1742,18 @@ static const struct v4l2_subdev_core_ops ov7670_core_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct v4l2_subdev_video_ops ov7670_video_ops = {</div><div class='del'>-	.s_frame_interval = ov7670_s_frame_interval,</div><div class='del'>-	.g_frame_interval = ov7670_g_frame_interval,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {</div><div class='ctx'> 	.enum_frame_interval = ov7670_enum_frame_interval,</div><div class='ctx'> 	.enum_frame_size = ov7670_enum_frame_size,</div><div class='ctx'> 	.enum_mbus_code = ov7670_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = ov7670_get_fmt,</div><div class='ctx'> 	.set_fmt = ov7670_set_fmt,</div><div class='add'>+	.get_frame_interval = ov7670_get_frame_interval,</div><div class='add'>+	.set_frame_interval = ov7670_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov7670_ops = {</div><div class='ctx'> 	.core = &amp;ov7670_core_ops,</div><div class='del'>-	.video = &amp;ov7670_video_ops,</div><div class='ctx'> 	.pad = &amp;ov7670_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c<br/>index 7618b58a7ad0..3e36a55274ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov772x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov772x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov772x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov772x.c</a></div><div class='hunk'>@@ -717,26 +717,42 @@ static int ov772x_set_frame_rate(struct ov772x_priv *priv,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov772x_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov772x_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov772x_priv *priv = to_ov772x(sd);</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	tpf-&gt;numerator = 1;</div><div class='ctx'> 	tpf-&gt;denominator = priv-&gt;fps;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov772x_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+static int ov772x_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov772x_priv *priv = to_ov772x(sd);</div><div class='ctx'> 	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='ctx'> 	unsigned int fps;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (priv-&gt;streaming) {</div><div class='hunk'>@@ -1220,7 +1236,7 @@ static int ov772x_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mf-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 0) = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1349,8 +1365,6 @@ static int ov772x_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {</div><div class='ctx'> 	.s_stream		= ov772x_s_stream,</div><div class='del'>-	.s_frame_interval	= ov772x_s_frame_interval,</div><div class='del'>-	.g_frame_interval	= ov772x_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {</div><div class='hunk'>@@ -1359,6 +1373,8 @@ static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {</div><div class='ctx'> 	.get_selection		= ov772x_get_selection,</div><div class='ctx'> 	.get_fmt		= ov772x_get_fmt,</div><div class='ctx'> 	.set_fmt		= ov772x_set_fmt,</div><div class='add'>+	.get_frame_interval	= ov772x_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= ov772x_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov772x_subdev_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c<br/>index 356a45e65b81..47b1b14d8796 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7740.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov7740.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov7740.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov7740.c</a></div><div class='hunk'>@@ -638,34 +638,8 @@ err_unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov7740_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	tpf-&gt;numerator = 1;</div><div class='del'>-	tpf-&gt;denominator = 60;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ov7740_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *ival)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	tpf-&gt;numerator = 1;</div><div class='del'>-	tpf-&gt;denominator = 60;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct v4l2_subdev_video_ops ov7740_subdev_video_ops = {</div><div class='ctx'> 	.s_stream = ov7740_set_stream,</div><div class='del'>-	.s_frame_interval = ov7740_s_frame_interval,</div><div class='del'>-	.g_frame_interval = ov7740_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct reg_sequence ov7740_format_yuyv[] = {</div><div class='hunk'>@@ -812,8 +786,7 @@ static int ov7740_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto error;</div><div class='ctx'> </div><div class='del'>-		mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-						      format-&gt;pad);</div><div class='add'>+		mbus_fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		*mbus_fmt = format-&gt;format;</div><div class='ctx'> 		mutex_unlock(&amp;ov7740-&gt;mutex);</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -843,7 +816,7 @@ static int ov7740_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov7740-&gt;mutex);</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mbus_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		format-&gt;format = *mbus_fmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		format-&gt;format = ov7740-&gt;format;</div><div class='hunk'>@@ -853,12 +826,26 @@ static int ov7740_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ov7740_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_fract *tpf = &amp;ival-&gt;interval;</div><div class='add'>+</div><div class='add'>+	tpf-&gt;numerator = 1;</div><div class='add'>+	tpf-&gt;denominator = 60;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = {</div><div class='ctx'> 	.enum_frame_interval = ov7740_enum_frame_interval,</div><div class='ctx'> 	.enum_frame_size = ov7740_enum_frame_size,</div><div class='ctx'> 	.enum_mbus_code = ov7740_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = ov7740_get_fmt,</div><div class='ctx'> 	.set_fmt = ov7740_set_fmt,</div><div class='add'>+	.get_frame_interval = ov7740_get_frame_interval,</div><div class='add'>+	.set_frame_interval = ov7740_get_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov7740_subdev_ops = {</div><div class='hunk'>@@ -883,7 +870,7 @@ static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format =</div><div class='del'>-				v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+				v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov7740-&gt;mutex);</div><div class='ctx'> 	ov7740_get_default_format(sd, format);</div><div class='head'>diff --git a/drivers/media/i2c/ov8856.c b/drivers/media/i2c/ov8856.c<br/>index a0f673a24e52..6ffe10e57b5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8856.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov8856.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8856.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8856.c</a></div><div class='hunk'>@@ -2134,7 +2134,7 @@ static int ov8856_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov8856-&gt;mutex);</div><div class='ctx'> 	ov8856_update_pad_format(ov8856, mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov8856-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(ov8856-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -2172,9 +2172,8 @@ static int ov8856_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov8856-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;ov8856-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov8856_update_pad_format(ov8856, ov8856-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -2225,7 +2224,7 @@ static int ov8856_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov8856-&gt;mutex);</div><div class='ctx'> 	ov8856_update_pad_format(ov8856, &amp;ov8856-&gt;priv_lane-&gt;supported_modes[0],</div><div class='del'>-				 v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				 v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;ov8856-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/i2c/ov8858.c b/drivers/media/i2c/ov8858.c<br/>index 4d9fd76e2f60..174c65f76886 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8858.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov8858.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8858.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8858.c</a></div><div class='hunk'>@@ -1333,7 +1333,7 @@ static int ov8858_start_stream(struct ov8858 *ov8858,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;ov8858-&gt;subdev, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> 	mode = v4l2_find_nearest_size(ov8858_modes, ARRAY_SIZE(ov8858_modes),</div><div class='ctx'> 				      width, height, format-&gt;width,</div><div class='ctx'> 				      format-&gt;height);</div><div class='hunk'>@@ -1428,7 +1428,7 @@ static int ov8858_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	fmt-&gt;format.field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='ctx'> 	/* Store the format in the current subdev state. */</div><div class='del'>-	*v4l2_subdev_get_pad_format(sd, state, 0) =  fmt-&gt;format;</div><div class='add'>+	*v4l2_subdev_state_get_format(state, 0) =  fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1476,8 +1476,8 @@ static int ov8858_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov8858_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov8858_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ov8858_mode *def_mode = &amp;ov8858_modes[0];</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='hunk'>@@ -1494,7 +1494,6 @@ static int ov8858_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov8858_pad_ops = {</div><div class='del'>-	.init_cfg = ov8858_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov8858_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov8858_enum_frame_sizes,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -1512,6 +1511,10 @@ static const struct v4l2_subdev_ops ov8858_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;ov8858_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov8858_internal_ops = {</div><div class='add'>+	.init_state = ov8858_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* ----------------------------------------------------------------------------</div><div class='ctx'>  * Controls handling</div><div class='ctx'>  */</div><div class='hunk'>@@ -1547,7 +1550,7 @@ static int ov8858_set_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 	 * - by the driver when s_ctrl is called in the s_stream(1) call path</div><div class='ctx'> 	 */</div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;ov8858-&gt;subdev);</div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;ov8858-&gt;subdev, state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate change of current control to all related controls */</div><div class='ctx'> 	switch (ctrl-&gt;id) {</div><div class='hunk'>@@ -1899,6 +1902,7 @@ static int ov8858_probe(struct i2c_client *client)</div><div class='ctx'> 				     "Failed to get powerdown gpio\n");</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov8858-&gt;subdev, client, &amp;ov8858_subdev_ops);</div><div class='add'>+	ov8858-&gt;subdev.internal_ops = &amp;ov8858_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	ret = ov8858_configure_regulators(ov8858);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c<br/>index f2213c6158d3..95ffe7536aa6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8865.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov8865.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov8865.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov8865.c</a></div><div class='hunk'>@@ -2640,33 +2640,8 @@ static int ov8865_s_stream(struct v4l2_subdev *subdev, int enable)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov8865_g_frame_interval(struct v4l2_subdev *subdev,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *interval)</div><div class='del'>-{</div><div class='del'>-	struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);</div><div class='del'>-	const struct ov8865_mode *mode;</div><div class='del'>-	unsigned int framesize;</div><div class='del'>-	unsigned int fps;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	mode = sensor-&gt;state.mode;</div><div class='del'>-	framesize = mode-&gt;hts * (mode-&gt;output_size_y +</div><div class='del'>-				 sensor-&gt;ctrls.vblank-&gt;val);</div><div class='del'>-	fps = DIV_ROUND_CLOSEST(sensor-&gt;ctrls.pixel_rate-&gt;val, framesize);</div><div class='del'>-</div><div class='del'>-	interval-&gt;interval.numerator = 1;</div><div class='del'>-	interval-&gt;interval.denominator = fps;</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;sensor-&gt;mutex);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct v4l2_subdev_video_ops ov8865_subdev_video_ops = {</div><div class='ctx'> 	.s_stream		= ov8865_s_stream,</div><div class='del'>-	.g_frame_interval	= ov8865_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= ov8865_g_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Subdev Pad Operations */</div><div class='hunk'>@@ -2710,8 +2685,8 @@ static int ov8865_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*mbus_format = *v4l2_subdev_get_try_format(subdev, sd_state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		*mbus_format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov8865_mbus_format_fill(mbus_format, sensor-&gt;state.mbus_code,</div><div class='ctx'> 					sensor-&gt;state.mode);</div><div class='hunk'>@@ -2765,7 +2740,7 @@ static int ov8865_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	ov8865_mbus_format_fill(mbus_format, mbus_code, mode);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(subdev, sd_state, format-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, format-&gt;pad) =</div><div class='ctx'> 			*mbus_format;</div><div class='ctx'> 	else if (sensor-&gt;state.mode != mode ||</div><div class='ctx'> 		 sensor-&gt;state.mbus_code != mbus_code)</div><div class='hunk'>@@ -2818,7 +2793,7 @@ __ov8865_get_pad_crop(struct ov8865_sensor *sensor,</div><div class='ctx'> </div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		*r = *v4l2_subdev_get_try_crop(&amp;sensor-&gt;subdev, state, pad);</div><div class='add'>+		*r = *v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		r-&gt;height = mode-&gt;output_size_y;</div><div class='hunk'>@@ -2862,6 +2837,37 @@ static int ov8865_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ov8865_get_frame_interval(struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *interval)</div><div class='add'>+{</div><div class='add'>+	struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev);</div><div class='add'>+	const struct ov8865_mode *mode;</div><div class='add'>+	unsigned int framesize;</div><div class='add'>+	unsigned int fps;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (interval-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;sensor-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	mode = sensor-&gt;state.mode;</div><div class='add'>+	framesize = mode-&gt;hts * (mode-&gt;output_size_y +</div><div class='add'>+				 sensor-&gt;ctrls.vblank-&gt;val);</div><div class='add'>+	fps = DIV_ROUND_CLOSEST(sensor-&gt;ctrls.pixel_rate-&gt;val, framesize);</div><div class='add'>+</div><div class='add'>+	interval-&gt;interval.numerator = 1;</div><div class='add'>+	interval-&gt;interval.denominator = fps;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;sensor-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov8865_subdev_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code		= ov8865_enum_mbus_code,</div><div class='ctx'> 	.get_fmt		= ov8865_get_fmt,</div><div class='hunk'>@@ -2869,6 +2875,8 @@ static const struct v4l2_subdev_pad_ops ov8865_subdev_pad_ops = {</div><div class='ctx'> 	.enum_frame_size	= ov8865_enum_frame_size,</div><div class='ctx'> 	.get_selection		= ov8865_get_selection,</div><div class='ctx'> 	.set_selection		= ov8865_get_selection,</div><div class='add'>+	.get_frame_interval	= ov8865_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= ov8865_get_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops ov8865_subdev_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/ov9282.c b/drivers/media/i2c/ov9282.c<br/>index bf6dfce1b5dd..251a4b534914 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9282.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov9282.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9282.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9282.c</a></div><div class='hunk'>@@ -814,7 +814,7 @@ static int ov9282_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *framefmt;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov9282_fill_pad_format(ov9282, ov9282-&gt;cur_mode, ov9282-&gt;code,</div><div class='hunk'>@@ -860,7 +860,7 @@ static int ov9282_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *framefmt;</div><div class='ctx'> </div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*framefmt = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = ov9282_update_controls(ov9282, mode, fmt);</div><div class='hunk'>@@ -876,14 +876,14 @@ static int ov9282_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ov9282_init_pad_cfg() - Initialize sub-device pad configuration</div><div class='add'>+ * ov9282_init_state() - Initialize sub-device state</div><div class='ctx'>  * @sd: pointer to ov9282 V4L2 sub-device structure</div><div class='ctx'>  * @sd_state: V4L2 sub-device configuration</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 if successful, error code otherwise.</div><div class='ctx'>  */</div><div class='del'>-static int ov9282_init_pad_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int ov9282_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov9282 *ov9282 = to_ov9282(sd);</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='hunk'>@@ -902,7 +902,7 @@ __ov9282_get_pad_crop(struct ov9282 *ov9282,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ov9282-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;ov9282-&gt;cur_mode-&gt;crop;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1192,7 +1192,6 @@ static const struct v4l2_subdev_video_ops ov9282_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops ov9282_pad_ops = {</div><div class='del'>-	.init_cfg = ov9282_init_pad_cfg,</div><div class='ctx'> 	.enum_mbus_code = ov9282_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = ov9282_enum_frame_size,</div><div class='ctx'> 	.get_fmt = ov9282_get_pad_format,</div><div class='hunk'>@@ -1206,6 +1205,10 @@ static const struct v4l2_subdev_ops ov9282_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;ov9282_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops ov9282_internal_ops = {</div><div class='add'>+	.init_state = ov9282_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ov9282_power_on() - Sensor power on sequence</div><div class='ctx'>  * @dev: pointer to i2c device</div><div class='hunk'>@@ -1394,6 +1397,7 @@ static int ov9282_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;ov9282-&gt;sd, client, &amp;ov9282_subdev_ops);</div><div class='add'>+	ov9282-&gt;sd.internal_ops = &amp;ov9282_internal_ops;</div><div class='ctx'> 	v4l2_i2c_subdev_set_name(&amp;ov9282-&gt;sd, client,</div><div class='ctx'> 				 device_get_match_data(ov9282-&gt;dev), NULL);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov9640.c b/drivers/media/i2c/ov9640.c<br/>index cbaea049531d..e9a52a8a9dc0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9640.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov9640.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9640.c</a></div><div class='hunk'>@@ -547,8 +547,6 @@ static int ov9640_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return ov9640_s_fmt(sd, mf);</div><div class='ctx'> </div><div class='del'>-	sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov9650.c b/drivers/media/i2c/ov9650.c<br/>index da1ab5135eaa..66cd0e9ddc9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9650.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov9650.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9650.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9650.c</a></div><div class='hunk'>@@ -1101,11 +1101,19 @@ static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov965x_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int ov965x_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov965x *ov965x = to_ov965x(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;ov965x-&gt;lock);</div><div class='ctx'> 	fi-&gt;interval = ov965x-&gt;fiv-&gt;interval;</div><div class='ctx'> 	mutex_unlock(&amp;ov965x-&gt;lock);</div><div class='hunk'>@@ -1148,12 +1156,20 @@ static int __ov965x_set_frame_interval(struct ov965x *ov965x,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ov965x_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int ov965x_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ov965x *ov965x = to_ov965x(sd);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",</div><div class='ctx'> 		 fi-&gt;interval.numerator, fi-&gt;interval.denominator);</div><div class='ctx'> </div><div class='hunk'>@@ -1172,7 +1188,7 @@ static int ov965x_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		fmt-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1233,8 +1249,7 @@ static int ov965x_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		if (sd_state) {</div><div class='del'>-			mf = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							fmt-&gt;pad);</div><div class='add'>+			mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 			*mf = fmt-&gt;format;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1363,7 +1378,7 @@ static int ov965x_s_stream(struct v4l2_subdev *sd, int on)</div><div class='ctx'> static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, fh-&gt;state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> </div><div class='ctx'> 	ov965x_get_default_format(mf);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1374,12 +1389,12 @@ static const struct v4l2_subdev_pad_ops ov965x_pad_ops = {</div><div class='ctx'> 	.enum_frame_size = ov965x_enum_frame_sizes,</div><div class='ctx'> 	.get_fmt = ov965x_get_fmt,</div><div class='ctx'> 	.set_fmt = ov965x_set_fmt,</div><div class='add'>+	.get_frame_interval = ov965x_get_frame_interval,</div><div class='add'>+	.set_frame_interval = ov965x_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops ov965x_video_ops = {</div><div class='ctx'> 	.s_stream = ov965x_s_stream,</div><div class='del'>-	.g_frame_interval = ov965x_g_frame_interval,</div><div class='del'>-	.s_frame_interval = ov965x_s_frame_interval,</div><div class='ctx'> </div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/ov9734.c b/drivers/media/i2c/ov9734.c<br/>index ee3315299605..d99728597431 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9734.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/ov9734.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/ov9734.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/ov9734.c</a></div><div class='hunk'>@@ -697,7 +697,7 @@ static int ov9734_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;ov9734-&gt;mutex);</div><div class='ctx'> 	ov9734_update_pad_format(mode, &amp;fmt-&gt;format);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ov9734-&gt;cur_mode = mode;</div><div class='ctx'> 		__v4l2_ctrl_s_ctrl(ov9734-&gt;link_freq, mode-&gt;link_freq_index);</div><div class='hunk'>@@ -730,9 +730,8 @@ static int ov9734_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov9734-&gt;mutex);</div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(&amp;ov9734-&gt;sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		ov9734_update_pad_format(ov9734-&gt;cur_mode, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='hunk'>@@ -777,7 +776,7 @@ static int ov9734_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ov9734-&gt;mutex);</div><div class='ctx'> 	ov9734_update_pad_format(&amp;supported_modes[0],</div><div class='del'>-				 v4l2_subdev_get_try_format(sd, fh-&gt;state, 0));</div><div class='add'>+				 v4l2_subdev_state_get_format(fh-&gt;state, 0));</div><div class='ctx'> 	mutex_unlock(&amp;ov9734-&gt;mutex);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -894,6 +893,7 @@ static void ov9734_remove(struct i2c_client *client)</div><div class='ctx'> 	media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='ctx'> 	v4l2_ctrl_handler_free(sd-&gt;ctrl_handler);</div><div class='ctx'> 	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> 	mutex_destroy(&amp;ov9734-&gt;mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -939,13 +939,6 @@ static int ov9734_probe(struct i2c_client *client)</div><div class='ctx'> 		goto probe_error_v4l2_ctrl_handler_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_async_register_subdev_sensor(&amp;ov9734-&gt;sd);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_err(&amp;client-&gt;dev, "failed to register V4L2 subdev: %d",</div><div class='del'>-			ret);</div><div class='del'>-		goto probe_error_media_entity_cleanup;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Device is already turned on by i2c-core with ACPI domain PM.</div><div class='ctx'> 	 * Enable runtime PM and turn off the device.</div><div class='hunk'>@@ -954,9 +947,18 @@ static int ov9734_probe(struct i2c_client *client)</div><div class='ctx'> 	pm_runtime_enable(&amp;client-&gt;dev);</div><div class='ctx'> 	pm_runtime_idle(&amp;client-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	ret = v4l2_async_register_subdev_sensor(&amp;ov9734-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to register V4L2 subdev: %d",</div><div class='add'>+			ret);</div><div class='add'>+		goto probe_error_media_entity_cleanup_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-probe_error_media_entity_cleanup:</div><div class='add'>+probe_error_media_entity_cleanup_pm:</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+	pm_runtime_set_suspended(&amp;client-&gt;dev);</div><div class='ctx'> 	media_entity_cleanup(&amp;ov9734-&gt;sd.entity);</div><div class='ctx'> </div><div class='ctx'> probe_error_v4l2_ctrl_handler_free:</div><div class='head'>diff --git a/drivers/media/i2c/rj54n1cb0c.c b/drivers/media/i2c/rj54n1cb0c.c<br/>index b430046f9e2a..a59db10153cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/rj54n1cb0c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/rj54n1cb0c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/rj54n1cb0c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/rj54n1cb0c.c</a></div><div class='hunk'>@@ -1008,10 +1008,8 @@ static int rj54n1_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	v4l_bound_align_image(&amp;mf-&gt;width, 112, RJ54N1_MAX_WIDTH, align,</div><div class='ctx'> 			      &amp;mf-&gt;height, 84, RJ54N1_MAX_HEIGHT, align, 0);</div><div class='ctx'> </div><div class='del'>-	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='add'>+	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='ctx'> 		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Verify if the sensor has just been powered on. TODO: replace this</div><div class='head'>diff --git a/drivers/media/i2c/s5c73m3/s5c73m3-core.c b/drivers/media/i2c/s5c73m3/s5c73m3-core.c<br/>index ed5b10731a14..af8d01f78c32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5c73m3/s5c73m3-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/s5c73m3/s5c73m3-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5c73m3/s5c73m3-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5c73m3/s5c73m3-core.c</a></div><div class='hunk'>@@ -819,7 +819,6 @@ static void s5c73m3_oif_try_format(struct s5c73m3 *state,</div><div class='ctx'> 				   struct v4l2_subdev_format *fmt,</div><div class='ctx'> 				   const struct s5c73m3_frame_size **fs)</div><div class='ctx'> {</div><div class='del'>-	struct v4l2_subdev *sd = &amp;state-&gt;sensor_sd;</div><div class='ctx'> 	u32 code;</div><div class='ctx'> </div><div class='ctx'> 	switch (fmt-&gt;pad) {</div><div class='hunk'>@@ -841,10 +840,8 @@ static void s5c73m3_oif_try_format(struct s5c73m3 *state,</div><div class='ctx'> 		if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 			*fs = state-&gt;oif_pix_size[RES_ISP];</div><div class='ctx'> 		else</div><div class='del'>-			*fs = s5c73m3_find_frame_size(</div><div class='del'>-						v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-									   OIF_ISP_PAD),</div><div class='del'>-						RES_ISP);</div><div class='add'>+			*fs = s5c73m3_find_frame_size(v4l2_subdev_state_get_format(sd_state, OIF_ISP_PAD),</div><div class='add'>+						      RES_ISP);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -869,11 +866,19 @@ static void s5c73m3_try_format(struct s5c73m3 *state,</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(&amp;fmt-&gt;format, *fs, code);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int s5c73m3_oif_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+					  struct v4l2_subdev_state *sd_state,</div><div class='add'>+					  struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (fi-&gt;pad != OIF_SOURCE_PAD)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -918,12 +923,20 @@ static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int s5c73m3_oif_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+					  struct v4l2_subdev_state *sd_state,</div><div class='add'>+					  struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	if (fi-&gt;pad != OIF_SOURCE_PAD)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -990,8 +1003,8 @@ static int s5c73m3_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	u32 code;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1025,8 +1038,8 @@ static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	u32 code;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1069,7 +1082,7 @@ static int s5c73m3_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	s5c73m3_try_format(state, sd_state, fmt, &amp;frame_size);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		switch (fmt-&gt;pad) {</div><div class='hunk'>@@ -1108,11 +1121,11 @@ static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	s5c73m3_oif_try_format(state, sd_state, fmt, &amp;frame_size);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> 		if (fmt-&gt;pad == OIF_ISP_PAD) {</div><div class='del'>-			mf = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							OIF_SOURCE_PAD);</div><div class='add'>+			mf = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							  OIF_SOURCE_PAD);</div><div class='ctx'> 			mf-&gt;width = fmt-&gt;format.width;</div><div class='ctx'> 			mf-&gt;height = fmt-&gt;format.height;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1260,8 +1273,8 @@ static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 			if (fse-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 				struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-				mf = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-								OIF_ISP_PAD);</div><div class='add'>+				mf = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								  OIF_ISP_PAD);</div><div class='ctx'> </div><div class='ctx'> 				w = mf-&gt;width;</div><div class='ctx'> 				h = mf-&gt;height;</div><div class='hunk'>@@ -1316,11 +1329,11 @@ static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, S5C73M3_ISP_PAD);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, S5C73M3_ISP_PAD);</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(mf, &amp;s5c73m3_isp_resolutions[1],</div><div class='ctx'> 						S5C73M3_ISP_FMT);</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, S5C73M3_JPEG_PAD);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, S5C73M3_JPEG_PAD);</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(mf, &amp;s5c73m3_jpeg_resolutions[1],</div><div class='ctx'> 					S5C73M3_JPEG_FMT);</div><div class='ctx'> </div><div class='hunk'>@@ -1331,15 +1344,15 @@ static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, OIF_ISP_PAD);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, OIF_ISP_PAD);</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(mf, &amp;s5c73m3_isp_resolutions[1],</div><div class='ctx'> 						S5C73M3_ISP_FMT);</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, OIF_JPEG_PAD);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, OIF_JPEG_PAD);</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(mf, &amp;s5c73m3_jpeg_resolutions[1],</div><div class='ctx'> 					S5C73M3_JPEG_FMT);</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, OIF_SOURCE_PAD);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, OIF_SOURCE_PAD);</div><div class='ctx'> 	s5c73m3_fill_mbus_fmt(mf, &amp;s5c73m3_isp_resolutions[1],</div><div class='ctx'> 						S5C73M3_ISP_FMT);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1500,6 +1513,8 @@ static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {</div><div class='ctx'> 	.enum_frame_interval	= s5c73m3_oif_enum_frame_interval,</div><div class='ctx'> 	.get_fmt		= s5c73m3_oif_get_fmt,</div><div class='ctx'> 	.set_fmt		= s5c73m3_oif_set_fmt,</div><div class='add'>+	.get_frame_interval	= s5c73m3_oif_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= s5c73m3_oif_set_frame_interval,</div><div class='ctx'> 	.get_frame_desc		= s5c73m3_oif_get_frame_desc,</div><div class='ctx'> 	.set_frame_desc		= s5c73m3_oif_set_frame_desc,</div><div class='ctx'> };</div><div class='hunk'>@@ -1511,8 +1526,6 @@ static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {</div><div class='ctx'> 	.s_stream		= s5c73m3_oif_s_stream,</div><div class='del'>-	.g_frame_interval	= s5c73m3_oif_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= s5c73m3_oif_s_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops oif_subdev_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/s5k5baf.c b/drivers/media/i2c/s5k5baf.c<br/>index 67da2045f543..de079d2c9282 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5k5baf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/s5k5baf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5k5baf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5k5baf.c</a></div><div class='hunk'>@@ -1118,11 +1118,19 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int s5k5baf_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5k5baf *state = to_s5k5baf(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;state-&gt;lock);</div><div class='ctx'> 	fi-&gt;interval.numerator = state-&gt;fiv;</div><div class='ctx'> 	fi-&gt;interval.denominator = 10000;</div><div class='hunk'>@@ -1131,8 +1139,8 @@ static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void s5k5baf_set_frame_interval(struct s5k5baf *state,</div><div class='del'>-				       struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static void __s5k5baf_set_frame_interval(struct s5k5baf *state,</div><div class='add'>+					 struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fract *i = &amp;fi-&gt;interval;</div><div class='ctx'> </div><div class='hunk'>@@ -1155,13 +1163,21 @@ static void s5k5baf_set_frame_interval(struct s5k5baf *state,</div><div class='ctx'> 			  state-&gt;fiv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+static int s5k5baf_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5k5baf *state = to_s5k5baf(sd);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (fi-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;state-&gt;lock);</div><div class='del'>-	s5k5baf_set_frame_interval(state, fi);</div><div class='add'>+	__s5k5baf_set_frame_interval(state, fi);</div><div class='ctx'> 	mutex_unlock(&amp;state-&gt;lock);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1273,7 +1289,7 @@ static int s5k5baf_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1307,7 +1323,7 @@ static int s5k5baf_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mf-&gt;field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) = *mf;</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1379,11 +1395,11 @@ static int s5k5baf_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		if (rtype == R_COMPOSE)</div><div class='del'>-			sel-&gt;r = *v4l2_subdev_get_try_compose(sd, sd_state,</div><div class='del'>-							      sel-&gt;pad);</div><div class='add'>+			sel-&gt;r = *v4l2_subdev_state_get_compose(sd_state,</div><div class='add'>+								sel-&gt;pad);</div><div class='ctx'> 		else</div><div class='del'>-			sel-&gt;r = *v4l2_subdev_get_try_crop(sd, sd_state,</div><div class='del'>-							   sel-&gt;pad);</div><div class='add'>+			sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+							     sel-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1472,14 +1488,11 @@ static int s5k5baf_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		rects = (struct v4l2_rect * []) {</div><div class='del'>-				&amp;s5k5baf_cis_rect,</div><div class='del'>-				v4l2_subdev_get_try_crop(sd, sd_state,</div><div class='del'>-							 PAD_CIS),</div><div class='del'>-				v4l2_subdev_get_try_compose(sd, sd_state,</div><div class='del'>-							    PAD_CIS),</div><div class='del'>-				v4l2_subdev_get_try_crop(sd, sd_state,</div><div class='del'>-							 PAD_OUT)</div><div class='del'>-			};</div><div class='add'>+			&amp;s5k5baf_cis_rect,</div><div class='add'>+			v4l2_subdev_state_get_crop(sd_state, PAD_CIS),</div><div class='add'>+			v4l2_subdev_state_get_compose(sd_state, PAD_CIS),</div><div class='add'>+			v4l2_subdev_state_get_crop(sd_state, PAD_OUT)</div><div class='add'>+		};</div><div class='ctx'> 		s5k5baf_set_rect_and_adjust(rects, rtype, &amp;sel-&gt;r);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1529,11 +1542,11 @@ static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = {</div><div class='ctx'> 	.set_fmt		= s5k5baf_set_fmt,</div><div class='ctx'> 	.get_selection		= s5k5baf_get_selection,</div><div class='ctx'> 	.set_selection		= s5k5baf_set_selection,</div><div class='add'>+	.get_frame_interval	= s5k5baf_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= s5k5baf_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops s5k5baf_video_ops = {</div><div class='del'>-	.g_frame_interval	= s5k5baf_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= s5k5baf_s_frame_interval,</div><div class='ctx'> 	.s_stream		= s5k5baf_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1696,22 +1709,22 @@ static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, PAD_CIS);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, PAD_CIS);</div><div class='ctx'> 	s5k5baf_try_cis_format(mf);</div><div class='ctx'> </div><div class='ctx'> 	if (s5k5baf_is_cis_subdev(sd))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, fh-&gt;state, PAD_OUT);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(fh-&gt;state, PAD_OUT);</div><div class='ctx'> 	mf-&gt;colorspace = s5k5baf_formats[0].colorspace;</div><div class='ctx'> 	mf-&gt;code = s5k5baf_formats[0].code;</div><div class='ctx'> 	mf-&gt;width = s5k5baf_cis_rect.width;</div><div class='ctx'> 	mf-&gt;height = s5k5baf_cis_rect.height;</div><div class='ctx'> 	mf-&gt;field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='del'>-	*v4l2_subdev_get_try_crop(sd, fh-&gt;state, PAD_CIS) = s5k5baf_cis_rect;</div><div class='del'>-	*v4l2_subdev_get_try_compose(sd, fh-&gt;state, PAD_CIS) = s5k5baf_cis_rect;</div><div class='del'>-	*v4l2_subdev_get_try_crop(sd, fh-&gt;state, PAD_OUT) = s5k5baf_cis_rect;</div><div class='add'>+	*v4l2_subdev_state_get_crop(fh-&gt;state, PAD_CIS) = s5k5baf_cis_rect;</div><div class='add'>+	*v4l2_subdev_state_get_compose(fh-&gt;state, PAD_CIS) = s5k5baf_cis_rect;</div><div class='add'>+	*v4l2_subdev_state_get_crop(fh-&gt;state, PAD_OUT) = s5k5baf_cis_rect;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/i2c/s5k6a3.c b/drivers/media/i2c/s5k6a3.c<br/>index b3560c8f8b41..0c2674115b7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5k6a3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/s5k6a3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/s5k6a3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/s5k6a3.c</a></div><div class='hunk'>@@ -127,8 +127,7 @@ static struct v4l2_mbus_framefmt *__s5k6a3_get_format(</div><div class='ctx'> 		u32 pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return sd_state ? v4l2_subdev_get_try_format(&amp;sensor-&gt;subdev,</div><div class='del'>-							     sd_state, pad) : NULL;</div><div class='add'>+		return sd_state ? v4l2_subdev_state_get_format(sd_state, pad) : NULL;</div><div class='ctx'> </div><div class='ctx'> 	return &amp;sensor-&gt;format;</div><div class='ctx'> }</div><div class='hunk'>@@ -174,9 +173,8 @@ static const struct v4l2_subdev_pad_ops s5k6a3_pad_ops = {</div><div class='ctx'> </div><div class='ctx'> static int s5k6a3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> {</div><div class='del'>-	struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(sd,</div><div class='del'>-								       fh-&gt;state,</div><div class='del'>-								       0);</div><div class='add'>+	struct v4l2_mbus_framefmt *format = v4l2_subdev_state_get_format(fh-&gt;state,</div><div class='add'>+									 0);</div><div class='ctx'> </div><div class='ctx'> 	*format		= s5k6a3_formats[0];</div><div class='ctx'> 	format-&gt;width	= S5K6A3_DEFAULT_WIDTH;</div><div class='head'>diff --git a/drivers/media/i2c/saa6752hs.c b/drivers/media/i2c/saa6752hs.c<br/>index c106e7a7d1f4..897eaa669b86 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/saa6752hs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/saa6752hs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/saa6752hs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/saa6752hs.c</a></div><div class='hunk'>@@ -594,10 +594,8 @@ static int saa6752hs_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	f-&gt;field = V4L2_FIELD_INTERLACED;</div><div class='ctx'> 	f-&gt;colorspace = V4L2_COLORSPACE_SMPTE170M;</div><div class='ctx'> </div><div class='del'>-	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_fmt = *f;</div><div class='add'>+	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='ctx'> 		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	  FIXME: translate and round width/height into EMPRESS</div><div class='head'>diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c<br/>index fa27638edc07..f250640729ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/st-mipid02.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/st-mipid02.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/st-mipid02.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/st-mipid02.c</a></div><div class='hunk'>@@ -16,25 +16,27 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of_graph.h&gt;</div><div class='ctx'> #include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;media/mipi-csi2.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-async.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-ctrls.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-fwnode.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-subdev.h&gt;</div><div class='ctx'> </div><div class='del'>-#define MIPID02_CLK_LANE_WR_REG1			0x01</div><div class='del'>-#define MIPID02_CLK_LANE_REG1				0x02</div><div class='del'>-#define MIPID02_CLK_LANE_REG3				0x04</div><div class='del'>-#define MIPID02_DATA_LANE0_REG1				0x05</div><div class='del'>-#define MIPID02_DATA_LANE0_REG2				0x06</div><div class='del'>-#define MIPID02_DATA_LANE1_REG1				0x09</div><div class='del'>-#define MIPID02_DATA_LANE1_REG2				0x0a</div><div class='del'>-#define MIPID02_MODE_REG1				0x14</div><div class='del'>-#define MIPID02_MODE_REG2				0x15</div><div class='del'>-#define MIPID02_DATA_ID_RREG				0x17</div><div class='del'>-#define MIPID02_DATA_SELECTION_CTRL			0x19</div><div class='del'>-#define MIPID02_PIX_WIDTH_CTRL				0x1e</div><div class='del'>-#define MIPID02_PIX_WIDTH_CTRL_EMB			0x1f</div><div class='add'>+#define MIPID02_CLK_LANE_WR_REG1	CCI_REG8(0x01)</div><div class='add'>+#define MIPID02_CLK_LANE_REG1		CCI_REG8(0x02)</div><div class='add'>+#define MIPID02_CLK_LANE_REG3		CCI_REG8(0x04)</div><div class='add'>+#define MIPID02_DATA_LANE0_REG1		CCI_REG8(0x05)</div><div class='add'>+#define MIPID02_DATA_LANE0_REG2		CCI_REG8(0x06)</div><div class='add'>+#define MIPID02_DATA_LANE1_REG1		CCI_REG8(0x09)</div><div class='add'>+#define MIPID02_DATA_LANE1_REG2		CCI_REG8(0x0a)</div><div class='add'>+#define MIPID02_MODE_REG1		CCI_REG8(0x14)</div><div class='add'>+#define MIPID02_MODE_REG2		CCI_REG8(0x15)</div><div class='add'>+#define MIPID02_DATA_ID_RREG		CCI_REG8(0x17)</div><div class='add'>+#define MIPID02_DATA_SELECTION_CTRL	CCI_REG8(0x19)</div><div class='add'>+#define MIPID02_PIX_WIDTH_CTRL		CCI_REG8(0x1e)</div><div class='add'>+#define MIPID02_PIX_WIDTH_CTRL_EMB	CCI_REG8(0x1f)</div><div class='ctx'> </div><div class='ctx'> /* Bits definition for MIPID02_CLK_LANE_REG1 */</div><div class='ctx'> #define CLK_ENABLE					BIT(0)</div><div class='hunk'>@@ -68,7 +70,7 @@ static const u32 mipid02_supported_fmt_codes[] = {</div><div class='ctx'> 	MEDIA_BUS_FMT_RGB565_2X8_LE, MEDIA_BUS_FMT_RGB565_2X8_BE,</div><div class='ctx'> 	MEDIA_BUS_FMT_YUYV8_2X8, MEDIA_BUS_FMT_YVYU8_2X8,</div><div class='ctx'> 	MEDIA_BUS_FMT_UYVY8_2X8, MEDIA_BUS_FMT_VYUY8_2X8,</div><div class='del'>-	MEDIA_BUS_FMT_JPEG_1X8</div><div class='add'>+	MEDIA_BUS_FMT_Y8_1X8, MEDIA_BUS_FMT_JPEG_1X8</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* regulator supplies */</div><div class='hunk'>@@ -88,12 +90,12 @@ struct mipid02_dev {</div><div class='ctx'> 	struct i2c_client *i2c_client;</div><div class='ctx'> 	struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];</div><div class='ctx'> 	struct v4l2_subdev sd;</div><div class='add'>+	struct regmap *regmap;</div><div class='ctx'> 	struct media_pad pad[MIPID02_PAD_NB];</div><div class='ctx'> 	struct clk *xclk;</div><div class='ctx'> 	struct gpio_desc *reset_gpio;</div><div class='ctx'> 	/* endpoints info */</div><div class='ctx'> 	struct v4l2_fwnode_endpoint rx;</div><div class='del'>-	u64 link_frequency;</div><div class='ctx'> 	struct v4l2_fwnode_endpoint tx;</div><div class='ctx'> 	/* remote source */</div><div class='ctx'> 	struct v4l2_async_notifier notifier;</div><div class='hunk'>@@ -110,10 +112,6 @@ struct mipid02_dev {</div><div class='ctx'> 		u8 pix_width_ctrl;</div><div class='ctx'> 		u8 pix_width_ctrl_emb;</div><div class='ctx'> 	} r;</div><div class='del'>-	/* lock to protect all members below */</div><div class='del'>-	struct mutex lock;</div><div class='del'>-	bool streaming;</div><div class='del'>-	struct v4l2_mbus_framefmt fmt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int bpp_from_code(__u32 code)</div><div class='hunk'>@@ -123,6 +121,7 @@ static int bpp_from_code(__u32 code)</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGBRG8_1X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGRBG8_1X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SRGGB8_1X8:</div><div class='add'>+	case MEDIA_BUS_FMT_Y8_1X8:</div><div class='ctx'> 		return 8;</div><div class='ctx'> 	case MEDIA_BUS_FMT_SBGGR10_1X10:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGBRG10_1X10:</div><div class='hunk'>@@ -160,17 +159,18 @@ static u8 data_type_from_code(__u32 code)</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGBRG8_1X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGRBG8_1X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SRGGB8_1X8:</div><div class='del'>-		return 0x2a;</div><div class='add'>+	case MEDIA_BUS_FMT_Y8_1X8:</div><div class='add'>+		return MIPI_CSI2_DT_RAW8;</div><div class='ctx'> 	case MEDIA_BUS_FMT_SBGGR10_1X10:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGBRG10_1X10:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGRBG10_1X10:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SRGGB10_1X10:</div><div class='del'>-		return 0x2b;</div><div class='add'>+		return MIPI_CSI2_DT_RAW10;</div><div class='ctx'> 	case MEDIA_BUS_FMT_SBGGR12_1X12:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGBRG12_1X12:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SGRBG12_1X12:</div><div class='ctx'> 	case MEDIA_BUS_FMT_SRGGB12_1X12:</div><div class='del'>-		return 0x2c;</div><div class='add'>+		return MIPI_CSI2_DT_RAW12;</div><div class='ctx'> 	case MEDIA_BUS_FMT_YUYV8_1X16:</div><div class='ctx'> 	case MEDIA_BUS_FMT_YVYU8_1X16:</div><div class='ctx'> 	case MEDIA_BUS_FMT_UYVY8_1X16:</div><div class='hunk'>@@ -179,30 +179,18 @@ static u8 data_type_from_code(__u32 code)</div><div class='ctx'> 	case MEDIA_BUS_FMT_YVYU8_2X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_UYVY8_2X8:</div><div class='ctx'> 	case MEDIA_BUS_FMT_VYUY8_2X8:</div><div class='del'>-		return 0x1e;</div><div class='add'>+		return MIPI_CSI2_DT_YUV422_8B;</div><div class='ctx'> 	case MEDIA_BUS_FMT_BGR888_1X24:</div><div class='del'>-		return 0x24;</div><div class='add'>+		return MIPI_CSI2_DT_RGB888;</div><div class='ctx'> 	case MEDIA_BUS_FMT_RGB565_1X16:</div><div class='ctx'> 	case MEDIA_BUS_FMT_RGB565_2X8_LE:</div><div class='ctx'> 	case MEDIA_BUS_FMT_RGB565_2X8_BE:</div><div class='del'>-		return 0x22;</div><div class='add'>+		return MIPI_CSI2_DT_RGB565;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void init_format(struct v4l2_mbus_framefmt *fmt)</div><div class='del'>-{</div><div class='del'>-	fmt-&gt;code = MEDIA_BUS_FMT_SBGGR8_1X8;</div><div class='del'>-	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='del'>-	fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='del'>-	fmt-&gt;ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB);</div><div class='del'>-	fmt-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='del'>-	fmt-&gt;xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB);</div><div class='del'>-	fmt-&gt;width = 640;</div><div class='del'>-	fmt-&gt;height = 480;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static __u32 get_fmt_code(__u32 code)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -238,62 +226,6 @@ static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)</div><div class='ctx'> 	return container_of(sd, struct mipid02_dev, sd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)</div><div class='del'>-{</div><div class='del'>-	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='del'>-	struct i2c_msg msg[2];</div><div class='del'>-	u8 buf[2];</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	buf[0] = reg &gt;&gt; 8;</div><div class='del'>-	buf[1] = reg &amp; 0xff;</div><div class='del'>-</div><div class='del'>-	msg[0].addr = client-&gt;addr;</div><div class='del'>-	msg[0].flags = client-&gt;flags;</div><div class='del'>-	msg[0].buf = buf;</div><div class='del'>-	msg[0].len = sizeof(buf);</div><div class='del'>-</div><div class='del'>-	msg[1].addr = client-&gt;addr;</div><div class='del'>-	msg[1].flags = client-&gt;flags | I2C_M_RD;</div><div class='del'>-	msg[1].buf = val;</div><div class='del'>-	msg[1].len = 1;</div><div class='del'>-</div><div class='del'>-	ret = i2c_transfer(client-&gt;adapter, msg, 2);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_dbg(&amp;client-&gt;dev, "%s: %x i2c_transfer, reg: %x =&gt; %d\n",</div><div class='del'>-			    __func__, client-&gt;addr, reg, ret);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)</div><div class='del'>-{</div><div class='del'>-	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='del'>-	struct i2c_msg msg;</div><div class='del'>-	u8 buf[3];</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	buf[0] = reg &gt;&gt; 8;</div><div class='del'>-	buf[1] = reg &amp; 0xff;</div><div class='del'>-	buf[2] = val;</div><div class='del'>-</div><div class='del'>-	msg.addr = client-&gt;addr;</div><div class='del'>-	msg.flags = client-&gt;flags;</div><div class='del'>-	msg.buf = buf;</div><div class='del'>-	msg.len = sizeof(buf);</div><div class='del'>-</div><div class='del'>-	ret = i2c_transfer(client-&gt;adapter, &amp;msg, 1);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_dbg(&amp;client-&gt;dev, "%s: i2c_transfer, reg: %x =&gt; %d\n",</div><div class='del'>-			    __func__, reg, ret);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int mipid02_get_regulators(struct mipid02_dev *bridge)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -358,73 +290,44 @@ static void mipid02_set_power_off(struct mipid02_dev *bridge)</div><div class='ctx'> </div><div class='ctx'> static int mipid02_detect(struct mipid02_dev *bridge)</div><div class='ctx'> {</div><div class='del'>-	u8 reg;</div><div class='add'>+	u64 reg;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * There is no version registers. Just try to read register</div><div class='ctx'> 	 * MIPID02_CLK_LANE_WR_REG1.</div><div class='ctx'> 	 */</div><div class='del'>-	return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, &amp;reg);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,</div><div class='del'>-						    struct v4l2_subdev *subdev)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };</div><div class='del'>-	struct v4l2_ctrl *ctrl;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ctrl = v4l2_ctrl_find(subdev-&gt;ctrl_handler, V4L2_CID_LINK_FREQ);</div><div class='del'>-	if (!ctrl)</div><div class='del'>-		return 0;</div><div class='del'>-	qm.index = v4l2_ctrl_g_ctrl(ctrl);</div><div class='del'>-</div><div class='del'>-	ret = v4l2_querymenu(subdev-&gt;ctrl_handler, &amp;qm);</div><div class='del'>-	if (ret)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return qm.value;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,</div><div class='del'>-						     struct v4l2_subdev *subdev)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_fwnode_endpoint *ep = &amp;bridge-&gt;rx;</div><div class='del'>-	struct v4l2_ctrl *ctrl;</div><div class='del'>-	u32 pixel_clock;</div><div class='del'>-	u32 bpp = bpp_from_code(bridge-&gt;fmt.code);</div><div class='del'>-</div><div class='del'>-	ctrl = v4l2_ctrl_find(subdev-&gt;ctrl_handler, V4L2_CID_PIXEL_RATE);</div><div class='del'>-	if (!ctrl)</div><div class='del'>-		return 0;</div><div class='del'>-	pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);</div><div class='del'>-</div><div class='del'>-	return pixel_clock * bpp / (2 * ep-&gt;bus.mipi_csi2.num_data_lanes);</div><div class='add'>+	return cci_read(bridge-&gt;regmap, MIPID02_CLK_LANE_WR_REG1, &amp;reg, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency</div><div class='del'>- * will be computed using connected device V4L2_CID_PIXEL_RATE, bit per pixel</div><div class='add'>+ * will be retrieve from connected device via v4l2_get_link_freq, bit per pixel</div><div class='ctx'>  * and number of lanes.</div><div class='ctx'>  */</div><div class='del'>-static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)</div><div class='add'>+static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge,</div><div class='add'>+					   struct v4l2_mbus_framefmt *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='ctx'> 	struct v4l2_subdev *subdev = bridge-&gt;s_subdev;</div><div class='del'>-	u32 link_freq;</div><div class='del'>-</div><div class='del'>-	link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);</div><div class='del'>-	if (!link_freq) {</div><div class='del'>-		link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,</div><div class='del'>-								      subdev);</div><div class='del'>-		if (!link_freq) {</div><div class='del'>-			dev_err(&amp;client-&gt;dev, "Failed to get link frequency");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='add'>+	struct v4l2_fwnode_endpoint *ep = &amp;bridge-&gt;rx;</div><div class='add'>+	u32 bpp = bpp_from_code(fmt-&gt;code);</div><div class='add'>+	/*</div><div class='add'>+	 * clk_lane_reg1 requires 4 times the unit interval time, and bitrate</div><div class='add'>+	 * is twice the link frequency, hence ui_4 = 1000000000 * 4 / 2</div><div class='add'>+	 */</div><div class='add'>+	u64 ui_4 = 2000000000;</div><div class='add'>+	s64 link_freq;</div><div class='add'>+</div><div class='add'>+	link_freq = v4l2_get_link_freq(subdev-&gt;ctrl_handler, bpp,</div><div class='add'>+				       2 * ep-&gt;bus.mipi_csi2.num_data_lanes);</div><div class='add'>+	if (link_freq &lt; 0) {</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Failed to get link frequency");</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "detect link_freq = %d Hz", link_freq);</div><div class='del'>-	bridge-&gt;r.clk_lane_reg1 |= (2000000000 / link_freq) &lt;&lt; 2;</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "detect link_freq = %lld Hz", link_freq);</div><div class='add'>+	do_div(ui_4, link_freq);</div><div class='add'>+	bridge-&gt;r.clk_lane_reg1 |= ui_4 &lt;&lt; 2;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -479,7 +382,8 @@ static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mipid02_configure_from_rx(struct mipid02_dev *bridge)</div><div class='add'>+static int mipid02_configure_from_rx(struct mipid02_dev *bridge,</div><div class='add'>+				     struct v4l2_mbus_framefmt *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_fwnode_endpoint *ep = &amp;bridge-&gt;rx;</div><div class='ctx'> 	bool are_lanes_swap = ep-&gt;bus.mipi_csi2.data_lanes[0] == 2;</div><div class='hunk'>@@ -504,7 +408,7 @@ static int mipid02_configure_from_rx(struct mipid02_dev *bridge)</div><div class='ctx'> 	bridge-&gt;r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;</div><div class='ctx'> 	bridge-&gt;r.mode_reg1 |= (nb - 1) &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	return mipid02_configure_from_rx_speed(bridge);</div><div class='add'>+	return mipid02_configure_from_rx_speed(bridge, fmt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mipid02_configure_from_tx(struct mipid02_dev *bridge)</div><div class='hunk'>@@ -524,16 +428,17 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mipid02_configure_from_code(struct mipid02_dev *bridge)</div><div class='add'>+static int mipid02_configure_from_code(struct mipid02_dev *bridge,</div><div class='add'>+				       struct v4l2_mbus_framefmt *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	u8 data_type;</div><div class='ctx'> </div><div class='ctx'> 	bridge-&gt;r.data_id_rreg = 0;</div><div class='ctx'> </div><div class='del'>-	if (bridge-&gt;fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {</div><div class='add'>+	if (fmt-&gt;code != MEDIA_BUS_FMT_JPEG_1X8) {</div><div class='ctx'> 		bridge-&gt;r.data_selection_ctrl |= SELECTION_MANUAL_DATA;</div><div class='ctx'> </div><div class='del'>-		data_type = data_type_from_code(bridge-&gt;fmt.code);</div><div class='add'>+		data_type = data_type_from_code(fmt-&gt;code);</div><div class='ctx'> 		if (!data_type)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		bridge-&gt;r.data_id_rreg = data_type;</div><div class='hunk'>@@ -555,13 +460,9 @@ static int mipid02_stream_disable(struct mipid02_dev *bridge)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable all lanes */</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_CLK_LANE_REG1, 0, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE0_REG1, 0, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE1_REG1, 0, &amp;ret);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error;</div><div class='ctx'> error:</div><div class='hunk'>@@ -574,69 +475,52 @@ error:</div><div class='ctx'> static int mipid02_stream_enable(struct mipid02_dev *bridge)</div><div class='ctx'> {</div><div class='ctx'> 	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> 	int ret = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (!bridge-&gt;s_subdev)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;bridge-&gt;r, 0, sizeof(bridge-&gt;r));</div><div class='add'>+</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(&amp;bridge-&gt;sd);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, MIPID02_SINK_0);</div><div class='add'>+</div><div class='ctx'> 	/* build registers content */</div><div class='del'>-	ret = mipid02_configure_from_rx(bridge);</div><div class='add'>+	ret = mipid02_configure_from_rx(bridge, fmt);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error;</div><div class='ctx'> 	ret = mipid02_configure_from_tx(bridge);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error;</div><div class='del'>-	ret = mipid02_configure_from_code(bridge);</div><div class='add'>+	ret = mipid02_configure_from_code(bridge, fmt);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='ctx'> 	/* write mipi registers */</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,</div><div class='del'>-		bridge-&gt;r.clk_lane_reg1);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,</div><div class='del'>-		bridge-&gt;r.data_lane0_reg1);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,</div><div class='del'>-		DATA_MIPI_CSI);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,</div><div class='del'>-		bridge-&gt;r.data_lane1_reg1);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,</div><div class='del'>-		DATA_MIPI_CSI);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,</div><div class='del'>-		MODE_NO_BYPASS | bridge-&gt;r.mode_reg1);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,</div><div class='del'>-		bridge-&gt;r.mode_reg2);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,</div><div class='del'>-		bridge-&gt;r.data_id_rreg);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,</div><div class='del'>-		bridge-&gt;r.data_selection_ctrl);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,</div><div class='del'>-		bridge-&gt;r.pix_width_ctrl);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto error;</div><div class='del'>-	ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,</div><div class='del'>-		bridge-&gt;r.pix_width_ctrl_emb);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_CLK_LANE_REG1,</div><div class='add'>+		  bridge-&gt;r.clk_lane_reg1, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE0_REG1,</div><div class='add'>+		  bridge-&gt;r.data_lane0_reg1, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE0_REG2, DATA_MIPI_CSI, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE1_REG1,</div><div class='add'>+		  bridge-&gt;r.data_lane1_reg1, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_LANE1_REG2, DATA_MIPI_CSI, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_MODE_REG1,</div><div class='add'>+		  MODE_NO_BYPASS | bridge-&gt;r.mode_reg1, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_MODE_REG2, bridge-&gt;r.mode_reg2, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_ID_RREG, bridge-&gt;r.data_id_rreg,</div><div class='add'>+		  &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_DATA_SELECTION_CTRL,</div><div class='add'>+		  bridge-&gt;r.data_selection_ctrl, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_PIX_WIDTH_CTRL,</div><div class='add'>+		  bridge-&gt;r.pix_width_ctrl, &amp;ret);</div><div class='add'>+	cci_write(bridge-&gt;regmap, MIPID02_PIX_WIDTH_CTRL_EMB,</div><div class='add'>+		  bridge-&gt;r.pix_width_ctrl_emb, &amp;ret);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='hunk'>@@ -659,31 +543,43 @@ static int mipid02_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> 	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "%s : requested %d / current = %d", __func__,</div><div class='del'>-		    enable, bridge-&gt;streaming);</div><div class='del'>-	mutex_lock(&amp;bridge-&gt;lock);</div><div class='del'>-</div><div class='del'>-	if (bridge-&gt;streaming == enable)</div><div class='del'>-		goto out;</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "%s : requested %d\n", __func__, enable);</div><div class='ctx'> </div><div class='ctx'> 	ret = enable ? mipid02_stream_enable(bridge) :</div><div class='ctx'> 		       mipid02_stream_disable(bridge);</div><div class='del'>-	if (!ret)</div><div class='del'>-		bridge-&gt;streaming = enable;</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "%s current now = %d / %d", __func__,</div><div class='del'>-		    bridge-&gt;streaming, ret);</div><div class='del'>-	mutex_unlock(&amp;bridge-&gt;lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "failed to stream %s (%d)\n",</div><div class='add'>+			enable ? "enable" : "disable", ret);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_mbus_framefmt default_fmt = {</div><div class='add'>+	.code = MEDIA_BUS_FMT_SBGGR8_1X8,</div><div class='add'>+	.field = V4L2_FIELD_NONE,</div><div class='add'>+	.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='add'>+	.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,</div><div class='add'>+	.quantization = V4L2_QUANTIZATION_FULL_RANGE,</div><div class='add'>+	.xfer_func = V4L2_XFER_FUNC_DEFAULT,</div><div class='add'>+	.width = 640,</div><div class='add'>+	.height = 480,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mipid02_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *state)</div><div class='add'>+{</div><div class='add'>+	*v4l2_subdev_state_get_format(state, MIPID02_SINK_0) = default_fmt;</div><div class='add'>+	/* MIPID02_SINK_1 isn't supported yet */</div><div class='add'>+	*v4l2_subdev_state_get_format(state, MIPID02_SOURCE) = default_fmt;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 				 struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='ctx'> {</div><div class='del'>-	struct mipid02_dev *bridge = to_mipid02_dev(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (code-&gt;pad) {</div><div class='hunk'>@@ -694,10 +590,13 @@ static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 			code-&gt;code = mipid02_supported_fmt_codes[code-&gt;index];</div><div class='ctx'> 		break;</div><div class='ctx'> 	case MIPID02_SOURCE:</div><div class='del'>-		if (code-&gt;index == 0)</div><div class='del'>-			code-&gt;code = serial_to_parallel_code(bridge-&gt;fmt.code);</div><div class='del'>-		else</div><div class='add'>+		if (code-&gt;index == 0) {</div><div class='add'>+			sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								MIPID02_SINK_0);</div><div class='add'>+			code-&gt;code = serial_to_parallel_code(sink_fmt-&gt;code);</div><div class='add'>+		} else {</div><div class='ctx'> 			ret = -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -706,117 +605,38 @@ static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mipid02_get_fmt(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state,</div><div class='del'>-			   struct v4l2_subdev_format *format)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_mbus_framefmt *mbus_fmt = &amp;format-&gt;format;</div><div class='del'>-	struct mipid02_dev *bridge = to_mipid02_dev(sd);</div><div class='del'>-	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='del'>-	struct v4l2_mbus_framefmt *fmt;</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "%s probe %d", __func__, format-&gt;pad);</div><div class='del'>-</div><div class='del'>-	if (format-&gt;pad &gt;= MIPID02_PAD_NB)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	/* second CSI-2 pad not yet supported */</div><div class='del'>-	if (format-&gt;pad == MIPID02_SINK_1)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(&amp;bridge-&gt;sd, sd_state,</div><div class='del'>-						 format-&gt;pad);</div><div class='del'>-	else</div><div class='del'>-		fmt = &amp;bridge-&gt;fmt;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;bridge-&gt;lock);</div><div class='del'>-</div><div class='del'>-	*mbus_fmt = *fmt;</div><div class='del'>-	/* code may need to be converted for source */</div><div class='del'>-	if (format-&gt;pad == MIPID02_SOURCE)</div><div class='del'>-		mbus_fmt-&gt;code = serial_to_parallel_code(mbus_fmt-&gt;code);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;bridge-&gt;lock);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mipid02_set_fmt_source(struct v4l2_subdev *sd,</div><div class='del'>-				   struct v4l2_subdev_state *sd_state,</div><div class='del'>-				   struct v4l2_subdev_format *format)</div><div class='del'>-{</div><div class='del'>-	struct mipid02_dev *bridge = to_mipid02_dev(sd);</div><div class='del'>-</div><div class='del'>-	/* source pad mirror sink pad */</div><div class='del'>-	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='del'>-		format-&gt;format = bridge-&gt;fmt;</div><div class='del'>-	else</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							     MIPID02_SINK_0);</div><div class='del'>-</div><div class='del'>-	/* but code may need to be converted */</div><div class='del'>-	format-&gt;format.code = serial_to_parallel_code(format-&gt;format.code);</div><div class='del'>-</div><div class='del'>-	/* only apply format for V4L2_SUBDEV_FORMAT_TRY case */</div><div class='del'>-	if (format-&gt;which != V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	*v4l2_subdev_get_try_format(sd, sd_state, MIPID02_SOURCE) =</div><div class='del'>-		format-&gt;format;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mipid02_set_fmt_sink(struct v4l2_subdev *sd,</div><div class='del'>-				 struct v4l2_subdev_state *sd_state,</div><div class='del'>-				 struct v4l2_subdev_format *format)</div><div class='del'>-{</div><div class='del'>-	struct mipid02_dev *bridge = to_mipid02_dev(sd);</div><div class='del'>-	struct v4l2_mbus_framefmt *fmt;</div><div class='del'>-</div><div class='del'>-	format-&gt;format.code = get_fmt_code(format-&gt;format.code);</div><div class='del'>-</div><div class='del'>-	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='del'>-	else</div><div class='del'>-		fmt = &amp;bridge-&gt;fmt;</div><div class='del'>-</div><div class='del'>-	*fmt = format-&gt;format;</div><div class='del'>-</div><div class='del'>-	/* Propagate the format change to the source pad */</div><div class='del'>-	mipid02_set_fmt_source(sd, sd_state, format);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int mipid02_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 			   struct v4l2_subdev_state *sd_state,</div><div class='del'>-			   struct v4l2_subdev_format *format)</div><div class='add'>+			   struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct mipid02_dev *bridge = to_mipid02_dev(sd);</div><div class='ctx'> 	struct i2c_client *client = bridge-&gt;i2c_client;</div><div class='del'>-	int ret = 0;</div><div class='add'>+	struct v4l2_mbus_framefmt *pad_fmt;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(&amp;client-&gt;dev, "%s for %d", __func__, format-&gt;pad);</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "%s for %d", __func__, fmt-&gt;pad);</div><div class='ctx'> </div><div class='del'>-	if (format-&gt;pad &gt;= MIPID02_PAD_NB)</div><div class='del'>-		return -EINVAL;</div><div class='ctx'> 	/* second CSI-2 pad not yet supported */</div><div class='del'>-	if (format-&gt;pad == MIPID02_SINK_1)</div><div class='add'>+	if (fmt-&gt;pad == MIPID02_SINK_1)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;bridge-&gt;lock);</div><div class='add'>+	pad_fmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='add'>+	fmt-&gt;format.code = get_fmt_code(fmt-&gt;format.code);</div><div class='ctx'> </div><div class='del'>-	if (bridge-&gt;streaming) {</div><div class='del'>-		ret = -EBUSY;</div><div class='del'>-		goto error;</div><div class='del'>-	}</div><div class='add'>+	/* code may need to be converted */</div><div class='add'>+	if (fmt-&gt;pad == MIPID02_SOURCE)</div><div class='add'>+		fmt-&gt;format.code = serial_to_parallel_code(fmt-&gt;format.code);</div><div class='ctx'> </div><div class='del'>-	if (format-&gt;pad == MIPID02_SOURCE)</div><div class='del'>-		mipid02_set_fmt_source(sd, sd_state, format);</div><div class='del'>-	else</div><div class='del'>-		mipid02_set_fmt_sink(sd, sd_state, format);</div><div class='add'>+	*pad_fmt = fmt-&gt;format;</div><div class='ctx'> </div><div class='del'>-error:</div><div class='del'>-	mutex_unlock(&amp;bridge-&gt;lock);</div><div class='add'>+	/* Propagate the format to the source pad in case of sink pad update */</div><div class='add'>+	if (fmt-&gt;pad == MIPID02_SINK_0) {</div><div class='add'>+		pad_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						       MIPID02_SOURCE);</div><div class='add'>+		*pad_fmt = fmt-&gt;format;</div><div class='add'>+		pad_fmt-&gt;code = serial_to_parallel_code(fmt-&gt;format.code);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops mipid02_video_ops = {</div><div class='hunk'>@@ -825,7 +645,7 @@ static const struct v4l2_subdev_video_ops mipid02_video_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = mipid02_enum_mbus_code,</div><div class='del'>-	.get_fmt = mipid02_get_fmt,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = mipid02_set_fmt,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -834,6 +654,10 @@ static const struct v4l2_subdev_ops mipid02_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;mipid02_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mipid02_subdev_internal_ops = {</div><div class='add'>+	.init_state = mipid02_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations mipid02_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -993,8 +817,6 @@ static int mipid02_probe(struct i2c_client *client)</div><div class='ctx'> 	if (!bridge)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	init_format(&amp;bridge-&gt;fmt);</div><div class='del'>-</div><div class='ctx'> 	bridge-&gt;i2c_client = client;</div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;bridge-&gt;sd, client, &amp;mipid02_subdev_ops);</div><div class='ctx'> </div><div class='hunk'>@@ -1026,9 +848,15 @@ static int mipid02_probe(struct i2c_client *client)</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mutex_init(&amp;bridge-&gt;lock);</div><div class='add'>+	/* Initialise the regmap for further cci access */</div><div class='add'>+	bridge-&gt;regmap = devm_cci_regmap_init_i2c(client, 16);</div><div class='add'>+	if (IS_ERR(bridge-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(bridge-&gt;regmap),</div><div class='add'>+				     "failed to get cci regmap\n");</div><div class='add'>+</div><div class='ctx'> 	bridge-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	bridge-&gt;sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='add'>+	bridge-&gt;sd.internal_ops = &amp;mipid02_subdev_internal_ops;</div><div class='ctx'> 	bridge-&gt;sd.entity.ops = &amp;mipid02_subdev_entity_ops;</div><div class='ctx'> 	bridge-&gt;pad[0].flags = MEDIA_PAD_FL_SINK;</div><div class='ctx'> 	bridge-&gt;pad[1].flags = MEDIA_PAD_FL_SINK;</div><div class='hunk'>@@ -1037,7 +865,13 @@ static int mipid02_probe(struct i2c_client *client)</div><div class='ctx'> 				     bridge-&gt;pad);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(&amp;client-&gt;dev, "pads init failed %d", ret);</div><div class='del'>-		goto mutex_cleanup;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_init_finalize(&amp;bridge-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "subdev init error: %d\n", ret);</div><div class='add'>+		goto entity_cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* enable clock, power and reset device if available */</div><div class='hunk'>@@ -1081,8 +915,6 @@ power_off:</div><div class='ctx'> 	mipid02_set_power_off(bridge);</div><div class='ctx'> entity_cleanup:</div><div class='ctx'> 	media_entity_cleanup(&amp;bridge-&gt;sd.entity);</div><div class='del'>-mutex_cleanup:</div><div class='del'>-	mutex_destroy(&amp;bridge-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1097,7 +929,6 @@ static void mipid02_remove(struct i2c_client *client)</div><div class='ctx'> 	v4l2_async_unregister_subdev(&amp;bridge-&gt;sd);</div><div class='ctx'> 	mipid02_set_power_off(bridge);</div><div class='ctx'> 	media_entity_cleanup(&amp;bridge-&gt;sd.entity);</div><div class='del'>-	mutex_destroy(&amp;bridge-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mipid02_dt_ids[] = {</div><div class='head'>diff --git a/drivers/media/i2c/st-vgxy61.c b/drivers/media/i2c/st-vgxy61.c<br/>index 5dbfb04b3124..e4d37a197724 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/st-vgxy61.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/st-vgxy61.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/st-vgxy61.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/st-vgxy61.c</a></div><div class='hunk'>@@ -21,6 +21,7 @@</div><div class='ctx'> #include &lt;media/v4l2-async.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-ctrls.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-fwnode.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-subdev.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -780,8 +781,7 @@ static int vgxy61_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;sensor-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(&amp;sensor-&gt;sd, sd_state,</div><div class='del'>-						 format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		fmt = &amp;sensor-&gt;fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -1289,7 +1289,7 @@ static int vgxy61_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*fmt = format-&gt;format;</div><div class='ctx'> 	} else if (sensor-&gt;current_mode != new_mode ||</div><div class='ctx'> 		   sensor-&gt;fmt.code != format-&gt;format.code) {</div><div class='hunk'>@@ -1323,8 +1323,8 @@ out:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vgxy61_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int vgxy61_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct vgxy61_dev *sensor = to_vgxy61_dev(sd);</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { 0 };</div><div class='hunk'>@@ -1403,6 +1403,7 @@ static int vgxy61_init_controls(struct vgxy61_dev *sensor)</div><div class='ctx'> 	const struct v4l2_ctrl_ops *ops = &amp;vgxy61_ctrl_ops;</div><div class='ctx'> 	struct v4l2_ctrl_handler *hdl = &amp;sensor-&gt;ctrl_handler;</div><div class='ctx'> 	const struct vgxy61_mode_info *cur_mode = sensor-&gt;current_mode;</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='ctx'> 	struct v4l2_ctrl *ctrl;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1457,6 +1458,14 @@ static int vgxy61_init_controls(struct vgxy61_dev *sensor)</div><div class='ctx'> 		goto free_ctrls;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = v4l2_fwnode_device_parse(&amp;sensor-&gt;i2c_client-&gt;dev, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_ctrls;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_new_fwnode_properties(hdl, ops, &amp;props);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_ctrls;</div><div class='add'>+</div><div class='ctx'> 	sensor-&gt;sd.ctrl_handler = hdl;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1465,12 +1474,16 @@ free_ctrls:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_core_ops vgxy61_core_ops = {</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct v4l2_subdev_video_ops vgxy61_video_ops = {</div><div class='ctx'> 	.s_stream = vgxy61_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops vgxy61_pad_ops = {</div><div class='del'>-	.init_cfg = vgxy61_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = vgxy61_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = vgxy61_get_fmt,</div><div class='ctx'> 	.set_fmt = vgxy61_set_fmt,</div><div class='hunk'>@@ -1479,10 +1492,15 @@ static const struct v4l2_subdev_pad_ops vgxy61_pad_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops vgxy61_subdev_ops = {</div><div class='add'>+	.core = &amp;vgxy61_core_ops,</div><div class='ctx'> 	.video = &amp;vgxy61_video_ops,</div><div class='ctx'> 	.pad = &amp;vgxy61_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops vgxy61_internal_ops = {</div><div class='add'>+	.init_state = vgxy61_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations vgxy61_subdev_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -1843,7 +1861,9 @@ static int vgxy61_probe(struct i2c_client *client)</div><div class='ctx'> 		device_property_read_bool(dev, "st,strobe-gpios-polarity");</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(&amp;sensor-&gt;sd, client, &amp;vgxy61_subdev_ops);</div><div class='del'>-	sensor-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='add'>+	sensor-&gt;sd.internal_ops = &amp;vgxy61_internal_ops;</div><div class='add'>+	sensor-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='add'>+			    V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	sensor-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='ctx'> 	sensor-&gt;sd.entity.ops = &amp;vgxy61_subdev_entity_ops;</div><div class='ctx'> 	sensor-&gt;sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='head'>diff --git a/drivers/media/i2c/tc358746.c b/drivers/media/i2c/tc358746.c<br/>index ce612a47ba84..106de4271d2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tc358746.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tc358746.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tc358746.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tc358746.c</a></div><div class='hunk'>@@ -427,7 +427,7 @@ static int tc358746_apply_misc_config(struct tc358746 *tc358746)</div><div class='ctx'> </div><div class='ctx'> 	sink_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='ctx'> </div><div class='del'>-	mbusfmt = v4l2_subdev_get_pad_format(sd, sink_state, TC358746_SINK);</div><div class='add'>+	mbusfmt = v4l2_subdev_state_get_format(sink_state, TC358746_SINK);</div><div class='ctx'> 	fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt-&gt;code);</div><div class='ctx'> </div><div class='ctx'> 	/* Self defined CSI user data type id's are not supported yet */</div><div class='hunk'>@@ -740,15 +740,15 @@ err_out:</div><div class='ctx'> 	return v4l2_subdev_call(src, video, s_stream, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tc358746_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			     struct v4l2_subdev_state *state)</div><div class='add'>+static int tc358746_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			       struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, state, TC358746_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, TC358746_SINK);</div><div class='ctx'> 	*fmt = tc358746_def_fmt;</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, state, TC358746_SOURCE);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, TC358746_SOURCE);</div><div class='ctx'> 	*fmt = tc358746_def_fmt;</div><div class='ctx'> 	fmt-&gt;code = tc358746_src_mbus_code(tc358746_def_fmt.code);</div><div class='ctx'> </div><div class='hunk'>@@ -781,7 +781,7 @@ static int tc358746_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;pad == TC358746_SOURCE)</div><div class='ctx'> 		return v4l2_subdev_get_fmt(sd, sd_state, format);</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, TC358746_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, TC358746_SINK);</div><div class='ctx'> </div><div class='ctx'> 	fmt = tc358746_get_format_by_code(format-&gt;pad, format-&gt;format.code);</div><div class='ctx'> 	if (IS_ERR(fmt)) {</div><div class='hunk'>@@ -800,7 +800,7 @@ static int tc358746_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	*sink_fmt = format-&gt;format;</div><div class='ctx'> </div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state, TC358746_SOURCE);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, TC358746_SOURCE);</div><div class='ctx'> 	*src_fmt = *sink_fmt;</div><div class='ctx'> 	src_fmt-&gt;code = tc358746_src_mbus_code(sink_fmt-&gt;code);</div><div class='ctx'> </div><div class='hunk'>@@ -905,7 +905,7 @@ tc358746_link_validate(struct v4l2_subdev *sd, struct media_link *link,</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	sink_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-	mbusfmt = v4l2_subdev_get_pad_format(sd, sink_state, TC358746_SINK);</div><div class='add'>+	mbusfmt = v4l2_subdev_state_get_format(sink_state, TC358746_SINK);</div><div class='ctx'> </div><div class='ctx'> 	/* Check the FIFO settings */</div><div class='ctx'> 	fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt-&gt;code);</div><div class='hunk'>@@ -1038,7 +1038,6 @@ static const struct v4l2_subdev_video_ops tc358746_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops tc358746_pad_ops = {</div><div class='del'>-	.init_cfg = tc358746_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = tc358746_enum_mbus_code,</div><div class='ctx'> 	.set_fmt = tc358746_set_fmt,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -1052,6 +1051,10 @@ static const struct v4l2_subdev_ops tc358746_ops = {</div><div class='ctx'> 	.pad = &amp;tc358746_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops tc358746_internal_ops = {</div><div class='add'>+	.init_state = tc358746_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations tc358746_entity_ops = {</div><div class='ctx'> 	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='hunk'>@@ -1282,6 +1285,7 @@ tc358746_init_subdev(struct tc358746 *tc358746, struct i2c_client *client)</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_i2c_subdev_init(sd, client, &amp;tc358746_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;tc358746_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	sd-&gt;entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='ctx'> 	sd-&gt;entity.ops = &amp;tc358746_entity_ops;</div><div class='head'>diff --git a/drivers/media/i2c/tda1997x.c b/drivers/media/i2c/tda1997x.c<br/>index 325e99125941..1ea703a9909f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tda1997x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tda1997x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tda1997x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tda1997x.c</a></div><div class='hunk'>@@ -1734,13 +1734,13 @@ static const struct v4l2_subdev_video_ops tda1997x_video_ops = {</div><div class='ctx'>  * v4l2_subdev_pad_ops</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static int tda1997x_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			     struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int tda1997x_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			       struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct tda1997x_state *state = to_state(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	mf-&gt;code = state-&gt;mbus_codes[0];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1792,7 +1792,7 @@ static int tda1997x_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		format-&gt;format.code = fmt-&gt;code;</div><div class='ctx'> 	} else</div><div class='ctx'> 		format-&gt;format.code = state-&gt;mbus_code;</div><div class='hunk'>@@ -1826,7 +1826,7 @@ static int tda1997x_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_try_format(sd, sd_state, format-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, format-&gt;pad);</div><div class='ctx'> 		*fmt = format-&gt;format;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		int ret = tda1997x_setup_format(state, format-&gt;format.code);</div><div class='hunk'>@@ -1925,7 +1925,6 @@ static int tda1997x_enum_dv_timings(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops tda1997x_pad_ops = {</div><div class='del'>-	.init_cfg = tda1997x_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = tda1997x_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = tda1997x_get_format,</div><div class='ctx'> 	.set_fmt = tda1997x_set_format,</div><div class='hunk'>@@ -2047,6 +2046,10 @@ static const struct v4l2_subdev_ops tda1997x_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;tda1997x_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops tda1997x_internal_ops = {</div><div class='add'>+	.init_state = tda1997x_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * v4l2_controls</div><div class='ctx'>  */</div><div class='hunk'>@@ -2588,6 +2591,7 @@ static int tda1997x_probe(struct i2c_client *client)</div><div class='ctx'> 	/* initialize subdev */</div><div class='ctx'> 	sd = &amp;state-&gt;sd;</div><div class='ctx'> 	v4l2_i2c_subdev_init(sd, client, &amp;tda1997x_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;tda1997x_internal_ops;</div><div class='ctx'> 	snprintf(sd-&gt;name, sizeof(sd-&gt;name), "%s %d-%04x",</div><div class='ctx'> 		 id-&gt;name, i2c_adapter_id(client-&gt;adapter),</div><div class='ctx'> 		 client-&gt;addr);</div><div class='head'>diff --git a/drivers/media/i2c/thp7312.c b/drivers/media/i2c/thp7312.c<br/>new file mode 100644<br/>index 000000000000..2806887514dc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/thp7312.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/thp7312.c</a></div><div class='hunk'>@@ -0,0 +1,2256 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2021 THine Electronics, Inc.</div><div class='add'>+ * Copyright (C) 2023 Ideas on Board Oy</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mtd/spi-nor.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;media/v4l2-async.h&gt;</div><div class='add'>+#include &lt;media/v4l2-cci.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;uapi/linux/thp7312.h&gt;</div><div class='add'>+</div><div class='add'>+/* ISP registers */</div><div class='add'>+</div><div class='add'>+#define THP7312_REG_FIRMWARE_VERSION_1			CCI_REG8(0xf000)</div><div class='add'>+#define THP7312_REG_CAMERA_STATUS			CCI_REG8(0xf001)</div><div class='add'>+#define THP7312_REG_FIRMWARE_VERSION_2			CCI_REG8(0xf005)</div><div class='add'>+#define THP7312_REG_SET_OUTPUT_ENABLE			CCI_REG8(0xf008)</div><div class='add'>+#define THP7312_OUTPUT_ENABLE				0x01</div><div class='add'>+#define THP7312_OUTPUT_DISABLE				0x00</div><div class='add'>+#define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION	CCI_REG8(0xf009)</div><div class='add'>+#define THP7312_REG_SET_OUTPUT_COLOR_UYVY		0x00</div><div class='add'>+#define THP7312_REG_SET_OUTPUT_COLOR_YUY2		0x04</div><div class='add'>+#define THP7312_REG_FLIP_MIRROR				CCI_REG8(0xf00c)</div><div class='add'>+#define THP7312_REG_FLIP_MIRROR_FLIP			BIT(0)</div><div class='add'>+#define THP7312_REG_FLIP_MIRROR_MIRROR			BIT(1)</div><div class='add'>+#define THP7312_REG_VIDEO_IMAGE_SIZE			CCI_REG8(0xf00d)</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_640x360		0x52</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_640x460		0x03</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_1280x720		0x0a</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_1920x1080		0x0b</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_3840x2160		0x0d</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_4160x3120		0x14</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_2016x1512		0x20</div><div class='add'>+#define THP7312_VIDEO_IMAGE_SIZE_2048x1536		0x21</div><div class='add'>+#define THP7312_REG_VIDEO_FRAME_RATE_MODE		CCI_REG8(0xf00f)</div><div class='add'>+#define THP7312_VIDEO_FRAME_RATE_MODE1			0x80</div><div class='add'>+#define THP7312_VIDEO_FRAME_RATE_MODE2			0x81</div><div class='add'>+#define THP7312_VIDEO_FRAME_RATE_MODE3			0x82</div><div class='add'>+#define THP7312_REG_SET_DRIVING_MODE			CCI_REG8(0xf010)</div><div class='add'>+#define THP7312_REG_DRIVING_MODE_STATUS			CCI_REG8(0xf011)</div><div class='add'>+#define THP7312_REG_JPEG_COMPRESSION_FACTOR		CCI_REG8(0xf01b)</div><div class='add'>+#define THP7312_REG_AE_EXPOSURE_COMPENSATION		CCI_REG8(0xf022)</div><div class='add'>+#define THP7312_REG_AE_FLICKER_MODE			CCI_REG8(0xf023)</div><div class='add'>+#define THP7312_AE_FLICKER_MODE_50			0x00</div><div class='add'>+#define THP7312_AE_FLICKER_MODE_60			0x01</div><div class='add'>+#define THP7312_AE_FLICKER_MODE_DISABLE			0x80</div><div class='add'>+#define THP7312_REG_AE_FIX_FRAME_RATE			CCI_REG8(0xf02e)</div><div class='add'>+#define THP7312_REG_MANUAL_WB_RED_GAIN			CCI_REG8(0xf036)</div><div class='add'>+#define THP7312_REG_MANUAL_WB_BLUE_GAIN			CCI_REG8(0xf037)</div><div class='add'>+#define THP7312_REG_WB_MODE				CCI_REG8(0xf039)</div><div class='add'>+#define THP7312_WB_MODE_AUTO				0x00</div><div class='add'>+#define THP7312_WB_MODE_MANUAL				0x11</div><div class='add'>+#define THP7312_REG_MANUAL_FOCUS_POSITION		CCI_REG16(0xf03c)</div><div class='add'>+#define THP7312_REG_AF_CONTROL				CCI_REG8(0xf040)</div><div class='add'>+#define THP7312_REG_AF_CONTROL_AF			0x01</div><div class='add'>+#define THP7312_REG_AF_CONTROL_MANUAL			0x10</div><div class='add'>+#define THP7312_REG_AF_CONTROL_LOCK			0x80</div><div class='add'>+#define THP7312_REG_AF_SETTING				CCI_REG8(0xf041)</div><div class='add'>+#define THP7312_REG_AF_SETTING_ONESHOT_CONTRAST		0x00</div><div class='add'>+#define THP7312_REG_AF_SETTING_ONESHOT_PDAF		0x40</div><div class='add'>+#define THP7312_REG_AF_SETTING_ONESHOT_HYBRID		0x80</div><div class='add'>+#define THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST	0x30</div><div class='add'>+#define THP7312_REG_AF_SETTING_CONTINUOUS_PDAF		0x70</div><div class='add'>+#define THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID	0xf0</div><div class='add'>+#define THP7312_REG_AF_SUPPORT				CCI_REG8(0xf043)</div><div class='add'>+#define THP7312_AF_SUPPORT_PDAF				BIT(1)</div><div class='add'>+#define THP7312_AF_SUPPORT_CONTRAST			BIT(0)</div><div class='add'>+#define THP7312_REG_SATURATION				CCI_REG8(0xf052)</div><div class='add'>+#define THP7312_REG_SHARPNESS				CCI_REG8(0xf053)</div><div class='add'>+#define THP7312_REG_BRIGHTNESS				CCI_REG8(0xf056)</div><div class='add'>+#define THP7312_REG_CONTRAST				CCI_REG8(0xf057)</div><div class='add'>+#define THP7312_REG_NOISE_REDUCTION			CCI_REG8(0xf059)</div><div class='add'>+#define THP7312_REG_NOISE_REDUCTION_FIXED		BIT(7)</div><div class='add'>+</div><div class='add'>+#define TH7312_REG_CUSTOM_MIPI_SET			CCI_REG8(0xf0f6)</div><div class='add'>+#define TH7312_REG_CUSTOM_MIPI_STATUS			CCI_REG8(0xf0f7)</div><div class='add'>+#define TH7312_REG_CUSTOM_MIPI_RD			CCI_REG8(0xf0f8)</div><div class='add'>+#define TH7312_REG_CUSTOM_MIPI_TD			CCI_REG8(0xf0f9)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Firmware update registers. Those use a different address space than the</div><div class='add'>+ * normal operation ISP registers.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define THP7312_REG_FW_DRIVABILITY			CCI_REG32(0xd65c)</div><div class='add'>+#define THP7312_REG_FW_DEST_BANK_ADDR			CCI_REG32(0xff08)</div><div class='add'>+#define THP7312_REG_FW_VERIFY_RESULT			CCI_REG8(0xff60)</div><div class='add'>+#define THP7312_REG_FW_RESET_FLASH			CCI_REG8(0xff61)</div><div class='add'>+#define THP7312_REG_FW_MEMORY_IO_SETTING		CCI_REG8(0xff62)</div><div class='add'>+#define THP7312_FW_MEMORY_IO_GPIO0			1</div><div class='add'>+#define THP7312_FW_MEMORY_IO_GPIO1			0</div><div class='add'>+#define THP7312_REG_FW_CRC_RESULT			CCI_REG32(0xff64)</div><div class='add'>+#define THP7312_REG_FW_STATUS				CCI_REG8(0xfffc)</div><div class='add'>+</div><div class='add'>+#define THP7312_FW_VERSION(major, minor)		(((major) &lt;&lt; 8) | (minor))</div><div class='add'>+#define THP7312_FW_VERSION_MAJOR(v)			((v) &gt;&gt; 8)</div><div class='add'>+#define THP7312_FW_VERSION_MINOR(v)			((v) &amp; 0xff)</div><div class='add'>+</div><div class='add'>+enum thp7312_focus_method {</div><div class='add'>+	THP7312_FOCUS_METHOD_CONTRAST,</div><div class='add'>+	THP7312_FOCUS_METHOD_PDAF,</div><div class='add'>+	THP7312_FOCUS_METHOD_HYBRID,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * enum thp7312_focus_state - State of the focus handler</div><div class='add'>+ *</div><div class='add'>+ * @THP7312_FOCUS_STATE_MANUAL: Manual focus, controlled through the</div><div class='add'>+ *	V4L2_CID_FOCUS_ABSOLUTE control</div><div class='add'>+ * @THP7312_FOCUS_STATE_AUTO: Continuous auto-focus</div><div class='add'>+ * @THP7312_FOCUS_STATE_LOCKED: Lock the focus to a fixed position. This state</div><div class='add'>+ *	is entered when switching from auto to manual mode.</div><div class='add'>+ * @THP7312_FOCUS_STATE_ONESHOT: One-shot auto-focus</div><div class='add'>+ *</div><div class='add'>+ * Valid transitions are as follow:</div><div class='add'>+ *</div><div class='add'>+ * digraph fsm {</div><div class='add'>+ *         node [shape=circle];</div><div class='add'>+ *</div><div class='add'>+ *         manual [label="MANUAL"];</div><div class='add'>+ *         auto [label="AUTO"];</div><div class='add'>+ *         locked [label="LOCKED"];</div><div class='add'>+ *         oneshot [label="ONESHOT"];</div><div class='add'>+ *</div><div class='add'>+ *         manual -&gt; auto [label="FOCUS_AUTO &lt;- true"]</div><div class='add'>+ *         locked -&gt; auto [label="FOCUS_AUTO &lt;- true"]</div><div class='add'>+ *         oneshot -&gt; auto [label="FOCUS_AUTO &lt;- true"]</div><div class='add'>+ *         auto -&gt; locked [label="FOCUS_AUTO &lt;- false"]</div><div class='add'>+ *</div><div class='add'>+ *         locked -&gt; manual [label="FOCUS_ABSOLUTE &lt;- *"]</div><div class='add'>+ *         oneshot -&gt; manual [label="FOCUS_ABSOLUTE &lt;- *"]</div><div class='add'>+ *</div><div class='add'>+ *         manual -&gt; oneshot [label="FOCUS_START &lt;- *"]</div><div class='add'>+ *         locked -&gt; oneshot [label="FOCUS_START &lt;- *"]</div><div class='add'>+ * }</div><div class='add'>+ */</div><div class='add'>+enum thp7312_focus_state {</div><div class='add'>+	THP7312_FOCUS_STATE_MANUAL,</div><div class='add'>+	THP7312_FOCUS_STATE_AUTO,</div><div class='add'>+	THP7312_FOCUS_STATE_LOCKED,</div><div class='add'>+	THP7312_FOCUS_STATE_ONESHOT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum thp7312_boot_mode {</div><div class='add'>+	THP7312_BOOT_MODE_2WIRE_SLAVE = 0,</div><div class='add'>+	THP7312_BOOT_MODE_SPI_MASTER = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct thp7312_frame_rate {</div><div class='add'>+	u32 fps;</div><div class='add'>+	u32 link_freq;</div><div class='add'>+	u8 reg_frame_rate_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct thp7312_mode_info {</div><div class='add'>+	u32 width;</div><div class='add'>+	u32 height;</div><div class='add'>+	u8 reg_image_size;</div><div class='add'>+	const struct thp7312_frame_rate *rates;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u32 thp7312_colour_fmts[] = {</div><div class='add'>+	MEDIA_BUS_FMT_YUYV8_1X16,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* regulator supplies */</div><div class='add'>+static const char * const thp7312_supply_name[] = {</div><div class='add'>+	"vddcore",</div><div class='add'>+	"vhtermrx",</div><div class='add'>+	"vddtx",</div><div class='add'>+	"vddhost",</div><div class='add'>+	"vddcmos",</div><div class='add'>+	"vddgpio-0",</div><div class='add'>+	"vddgpio-1",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct thp7312_mode_info thp7312_mode_info_data[] = {</div><div class='add'>+	{</div><div class='add'>+		.width = 1920,</div><div class='add'>+		.height = 1080,</div><div class='add'>+		.reg_image_size = THP7312_VIDEO_IMAGE_SIZE_1920x1080,</div><div class='add'>+		.rates = (const struct thp7312_frame_rate[]) {</div><div class='add'>+			{ 30, 300000000, 0x81 },</div><div class='add'>+			{ 60, 387500000, 0x82 },</div><div class='add'>+			{ 0 }</div><div class='add'>+		},</div><div class='add'>+	}, {</div><div class='add'>+		.width = 2048,</div><div class='add'>+		.height = 1536,</div><div class='add'>+		.reg_image_size = THP7312_VIDEO_IMAGE_SIZE_2048x1536,</div><div class='add'>+		.rates = (const struct thp7312_frame_rate[]) {</div><div class='add'>+			{ 30, 300000000, 0x81 },</div><div class='add'>+			{ 0 }</div><div class='add'>+		}</div><div class='add'>+	}, {</div><div class='add'>+		.width = 3840,</div><div class='add'>+		.height = 2160,</div><div class='add'>+		.reg_image_size = THP7312_VIDEO_IMAGE_SIZE_3840x2160,</div><div class='add'>+		.rates = (const struct thp7312_frame_rate[]) {</div><div class='add'>+			{ 30, 600000000, 0x81 },</div><div class='add'>+			{ 0 }</div><div class='add'>+		},</div><div class='add'>+	}, {</div><div class='add'>+		.width = 4160,</div><div class='add'>+		.height = 3120,</div><div class='add'>+		.reg_image_size = THP7312_VIDEO_IMAGE_SIZE_4160x3120,</div><div class='add'>+		.rates = (const struct thp7312_frame_rate[]) {</div><div class='add'>+			{ 20, 600000000, 0x81 },</div><div class='add'>+			{ 0 }</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct thp7312_device;</div><div class='add'>+</div><div class='add'>+struct thp7312_sensor_info {</div><div class='add'>+	const char *model;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct thp7312_sensor {</div><div class='add'>+	const struct thp7312_sensor_info *info;</div><div class='add'>+	u8 lane_remap;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct thp7312_device {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct regulator_bulk_data supplies[ARRAY_SIZE(thp7312_supply_name)];</div><div class='add'>+	struct clk *iclk;</div><div class='add'>+</div><div class='add'>+	u8 lane_remap;</div><div class='add'>+</div><div class='add'>+	struct thp7312_sensor sensors[1];</div><div class='add'>+</div><div class='add'>+	enum thp7312_boot_mode boot_mode;</div><div class='add'>+</div><div class='add'>+	struct v4l2_ctrl_handler ctrl_handler;</div><div class='add'>+	bool ctrls_applied;</div><div class='add'>+</div><div class='add'>+	s64 link_freq;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct v4l2_ctrl *hflip;</div><div class='add'>+		struct v4l2_ctrl *vflip;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct v4l2_ctrl *focus_auto;</div><div class='add'>+		struct v4l2_ctrl *focus_absolute;</div><div class='add'>+		struct v4l2_ctrl *focus_start;</div><div class='add'>+		struct v4l2_ctrl *focus_method;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	enum thp7312_focus_state focus_state;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		struct v4l2_ctrl *noise_reduction_auto;</div><div class='add'>+		struct v4l2_ctrl *noise_reduction_absolute;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	/* Lock to protect fw_cancel */</div><div class='add'>+	struct mutex fw_lock;</div><div class='add'>+	struct fw_upload *fwl;</div><div class='add'>+	u8 *fw_write_buf;</div><div class='add'>+	bool fw_cancel;</div><div class='add'>+</div><div class='add'>+	u16 fw_version;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct thp7312_sensor_info thp7312_sensor_info[] = {</div><div class='add'>+	{</div><div class='add'>+		.model = "sony,imx258",</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct thp7312_device *to_thp7312_dev(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	return container_of(sd, struct thp7312_device, sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct thp7312_mode_info *</div><div class='add'>+thp7312_find_mode(unsigned int width, unsigned int height, bool nearest)</div><div class='add'>+{</div><div class='add'>+	const struct thp7312_mode_info *mode;</div><div class='add'>+</div><div class='add'>+	mode = v4l2_find_nearest_size(thp7312_mode_info_data,</div><div class='add'>+				      ARRAY_SIZE(thp7312_mode_info_data),</div><div class='add'>+				      width, height, width, height);</div><div class='add'>+</div><div class='add'>+	if (!nearest &amp;&amp; (mode-&gt;width != width || mode-&gt;height != height))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct thp7312_frame_rate *</div><div class='add'>+thp7312_find_rate(const struct thp7312_mode_info *mode, unsigned int fps,</div><div class='add'>+		  bool nearest)</div><div class='add'>+{</div><div class='add'>+	const struct thp7312_frame_rate *best_rate = NULL;</div><div class='add'>+	const struct thp7312_frame_rate *rate;</div><div class='add'>+	unsigned int best_delta = UINT_MAX;</div><div class='add'>+</div><div class='add'>+	if (!mode)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	for (rate = mode-&gt;rates; rate-&gt;fps &amp;&amp; best_delta; ++rate) {</div><div class='add'>+		unsigned int delta = abs(rate-&gt;fps - fps);</div><div class='add'>+</div><div class='add'>+		if (delta &lt;= best_delta) {</div><div class='add'>+			best_delta = delta;</div><div class='add'>+			best_rate = rate;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!nearest &amp;&amp; best_delta)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return best_rate;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * Device Access &amp; Configuration</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define thp7312_read_poll_timeout(dev, addr, val, cond, sleep_us, timeout_us) \</div><div class='add'>+({ \</div><div class='add'>+	int __ret, __err; \</div><div class='add'>+	__ret = read_poll_timeout(cci_read, __err, __err || (cond), sleep_us, \</div><div class='add'>+				  timeout_us, false, (dev)-&gt;regmap, addr, \</div><div class='add'>+				  &amp;(val), NULL); \</div><div class='add'>+	__ret ? : __err; \</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+static int thp7312_map_data_lanes(u8 *lane_remap, const u8 *lanes, u8 num_lanes)</div><div class='add'>+{</div><div class='add'>+	u8 used_lanes = 0;</div><div class='add'>+	u8 val = 0;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The value that we write to the register is the index in the</div><div class='add'>+	 * data-lanes array, so we need to do a conversion. Do this in the same</div><div class='add'>+	 * pass as validating data-lanes.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; num_lanes; i++) {</div><div class='add'>+		if (lanes[i] &lt; 1 || lanes[i] &gt; 4)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		if (used_lanes &amp; (BIT(lanes[i])))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		used_lanes |= BIT(lanes[i]);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * data-lanes is 1-indexed while the field position in the</div><div class='add'>+		 * register is 0-indexed.</div><div class='add'>+		 */</div><div class='add'>+		val |= i &lt;&lt; ((lanes[i] - 1) * 2);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*lane_remap = val;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_set_mipi_lanes(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u64 val;</div><div class='add'>+</div><div class='add'>+	cci_write(thp7312-&gt;regmap, TH7312_REG_CUSTOM_MIPI_RD,</div><div class='add'>+		  thp7312-&gt;sensors[0].lane_remap, &amp;ret);</div><div class='add'>+	cci_write(thp7312-&gt;regmap, TH7312_REG_CUSTOM_MIPI_TD,</div><div class='add'>+		  thp7312-&gt;lane_remap, &amp;ret);</div><div class='add'>+	cci_write(thp7312-&gt;regmap, TH7312_REG_CUSTOM_MIPI_SET, 1, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_read_poll_timeout(thp7312, TH7312_REG_CUSTOM_MIPI_STATUS,</div><div class='add'>+					val, val == 0x00, 100000, 2000000);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to poll MIPI lane status: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_change_mode(struct thp7312_device *thp7312,</div><div class='add'>+			       const struct thp7312_mode_info *mode,</div><div class='add'>+			       const struct thp7312_frame_rate *rate)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u64 val = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_CAMERA_STATUS, val,</div><div class='add'>+					val == 0x80, 20000, 200000);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "%s(): failed to poll ISP: %d\n", __func__, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_VIDEO_IMAGE_SIZE,</div><div class='add'>+		  mode-&gt;reg_image_size, &amp;ret);</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_VIDEO_FRAME_RATE_MODE,</div><div class='add'>+		  rate-&gt;reg_frame_rate_mode, &amp;ret);</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_JPEG_COMPRESSION_FACTOR, 0x5e,</div><div class='add'>+		  &amp;ret);</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_SET_DRIVING_MODE, 0x01, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_DRIVING_MODE_STATUS,</div><div class='add'>+					val, val == 0x01, 20000, 100000);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "%s(): failed\n", __func__);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_set_framefmt(struct thp7312_device *thp7312,</div><div class='add'>+				struct v4l2_mbus_framefmt *format)</div><div class='add'>+{</div><div class='add'>+	u8 val;</div><div class='add'>+</div><div class='add'>+	switch (format-&gt;code) {</div><div class='add'>+	case MEDIA_BUS_FMT_UYVY8_1X16:</div><div class='add'>+		/* YUV422, UYVY */</div><div class='add'>+		val = THP7312_REG_SET_OUTPUT_COLOR_UYVY;</div><div class='add'>+		break;</div><div class='add'>+	case MEDIA_BUS_FMT_YUYV8_1X16:</div><div class='add'>+		/* YUV422, YUYV */</div><div class='add'>+		val = THP7312_REG_SET_OUTPUT_COLOR_YUY2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		/* Should never happen */</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return cci_write(thp7312-&gt;regmap,</div><div class='add'>+			 THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION, val, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_init_mode(struct thp7312_device *thp7312,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	const struct thp7312_mode_info *mode;</div><div class='add'>+	const struct thp7312_frame_rate *rate;</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_fract *interval;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: The mode and rate should be cached in the subdev state, once</div><div class='add'>+	 * support for extending states will be available.</div><div class='add'>+	 */</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+	interval = v4l2_subdev_state_get_interval(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	mode = thp7312_find_mode(fmt-&gt;width, fmt-&gt;height, false);</div><div class='add'>+	rate = thp7312_find_rate(mode, interval-&gt;denominator, false);</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!mode || !rate))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_set_framefmt(thp7312, fmt);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return thp7312_change_mode(thp7312, mode, rate);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_stream_enable(struct thp7312_device *thp7312, bool enable)</div><div class='add'>+{</div><div class='add'>+	return cci_write(thp7312-&gt;regmap, THP7312_REG_SET_OUTPUT_ENABLE,</div><div class='add'>+			 enable ? THP7312_OUTPUT_ENABLE : THP7312_OUTPUT_DISABLE,</div><div class='add'>+			 NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_check_status_stream_mode(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u64 status = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	while (status != 0x80) {</div><div class='add'>+		ret = cci_read(thp7312-&gt;regmap, THP7312_REG_CAMERA_STATUS,</div><div class='add'>+			       &amp;status, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		if (status == 0x80) {</div><div class='add'>+			dev_dbg(dev, "Camera initialization done\n");</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (status != 0x00) {</div><div class='add'>+			dev_err(dev, "Invalid camera status %llx\n", status);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dev_dbg(dev, "Camera initializing...\n");</div><div class='add'>+		usleep_range(70000, 80000);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void thp7312_reset(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	unsigned long rate;</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(thp7312-&gt;reset_gpio, 1);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The minimum reset duration is 8 clock cycles, make it 10 to provide</div><div class='add'>+	 * a safety margin.</div><div class='add'>+	 */</div><div class='add'>+	rate = clk_get_rate(thp7312-&gt;iclk);</div><div class='add'>+	fsleep(DIV_ROUND_UP(10 * USEC_PER_SEC, rate));</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(thp7312-&gt;reset_gpio, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * TODO: The documentation states that the device needs 2ms to</div><div class='add'>+	 * initialize after reset is deasserted. It then proceeds to load the</div><div class='add'>+	 * firmware from the flash memory, which takes an unspecified amount of</div><div class='add'>+	 * time. Check if this delay could be reduced.</div><div class='add'>+	 */</div><div class='add'>+	fsleep(300000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * Power Management</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static void __thp7312_power_off(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	regulator_bulk_disable(ARRAY_SIZE(thp7312-&gt;supplies), thp7312-&gt;supplies);</div><div class='add'>+	clk_disable_unprepare(thp7312-&gt;iclk);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void thp7312_power_off(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	__thp7312_power_off(thp7312);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __thp7312_power_on(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = regulator_bulk_enable(ARRAY_SIZE(thp7312-&gt;supplies),</div><div class='add'>+				    thp7312-&gt;supplies);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(thp7312-&gt;iclk);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "clk prepare enable failed\n");</div><div class='add'>+		regulator_bulk_disable(ARRAY_SIZE(thp7312-&gt;supplies),</div><div class='add'>+				       thp7312-&gt;supplies);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * We cannot assume that turning off and on again will reset, so do a</div><div class='add'>+	 * software reset on power up.</div><div class='add'>+	 */</div><div class='add'>+	thp7312_reset(thp7312);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_power_on(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = __thp7312_power_on(thp7312);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_check_status_stream_mode(thp7312);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto error;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_set_mipi_lanes(thp7312);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto error;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	thp7312_power_off(thp7312);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __maybe_unused thp7312_pm_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+</div><div class='add'>+	thp7312_power_off(thp7312);</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;ctrls_applied = false;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __maybe_unused thp7312_pm_runtime_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = dev_get_drvdata(dev);</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+</div><div class='add'>+	return thp7312_power_on(thp7312);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops thp7312_pm_ops = {</div><div class='add'>+	SET_RUNTIME_PM_OPS(thp7312_pm_runtime_suspend,</div><div class='add'>+			   thp7312_pm_runtime_resume, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * V4L2 Subdev Operations</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static bool thp7312_find_bus_code(u32 code)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(thp7312_colour_fmts); ++i) {</div><div class='add'>+		if (thp7312_colour_fmts[i] == code)</div><div class='add'>+			return true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state,</div><div class='add'>+				  struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	if (code-&gt;index &gt;= ARRAY_SIZE(thp7312_colour_fmts))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = thp7312_colour_fmts[code-&gt;index];</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_enum_frame_size(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state,</div><div class='add'>+				   struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	if (!thp7312_find_bus_code(fse-&gt;code))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index &gt;= ARRAY_SIZE(thp7312_mode_info_data))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fse-&gt;min_width = thp7312_mode_info_data[fse-&gt;index].width;</div><div class='add'>+	fse-&gt;max_width = fse-&gt;min_width;</div><div class='add'>+	fse-&gt;min_height = thp7312_mode_info_data[fse-&gt;index].height;</div><div class='add'>+	fse-&gt;max_height = fse-&gt;min_height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_enum_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				       struct v4l2_subdev_state *sd_state,</div><div class='add'>+				       struct v4l2_subdev_frame_interval_enum *fie)</div><div class='add'>+{</div><div class='add'>+	const struct thp7312_frame_rate *rate;</div><div class='add'>+	const struct thp7312_mode_info *mode;</div><div class='add'>+	unsigned int index = fie-&gt;index;</div><div class='add'>+</div><div class='add'>+	if (!thp7312_find_bus_code(fie-&gt;code))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mode = thp7312_find_mode(fie-&gt;width, fie-&gt;height, false);</div><div class='add'>+	if (!mode)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (rate = mode-&gt;rates; rate-&gt;fps; ++rate, --index) {</div><div class='add'>+		if (!index) {</div><div class='add'>+			fie-&gt;interval.numerator = 1;</div><div class='add'>+			fie-&gt;interval.denominator = rate-&gt;fps;</div><div class='add'>+</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_set_fmt(struct v4l2_subdev *sd,</div><div class='add'>+			   struct v4l2_subdev_state *sd_state,</div><div class='add'>+			   struct v4l2_subdev_format *format)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mbus_fmt = &amp;format-&gt;format;</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_fract *interval;</div><div class='add'>+	const struct thp7312_mode_info *mode;</div><div class='add'>+</div><div class='add'>+	if (!thp7312_find_bus_code(mbus_fmt-&gt;code))</div><div class='add'>+		mbus_fmt-&gt;code = thp7312_colour_fmts[0];</div><div class='add'>+</div><div class='add'>+	mode = thp7312_find_mode(mbus_fmt-&gt;width, mbus_fmt-&gt;height, true);</div><div class='add'>+</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	fmt-&gt;code = mbus_fmt-&gt;code;</div><div class='add'>+	fmt-&gt;width = mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = mode-&gt;height;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='add'>+	fmt-&gt;ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt-&gt;colorspace);</div><div class='add'>+	fmt-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='add'>+	fmt-&gt;xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt-&gt;colorspace);</div><div class='add'>+</div><div class='add'>+	*mbus_fmt = *fmt;</div><div class='add'>+</div><div class='add'>+	interval = v4l2_subdev_state_get_interval(sd_state, 0);</div><div class='add'>+	interval-&gt;numerator = 1;</div><div class='add'>+	interval-&gt;denominator = mode-&gt;rates[0].fps;</div><div class='add'>+</div><div class='add'>+	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		thp7312-&gt;link_freq = mode-&gt;rates[0].link_freq;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+	const struct thp7312_mode_info *mode;</div><div class='add'>+	const struct thp7312_frame_rate *rate;</div><div class='add'>+	const struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_fract *interval;</div><div class='add'>+	unsigned int fps;</div><div class='add'>+</div><div class='add'>+	/* Avoid divisions by 0, pick the highest frame if the interval is 0. */</div><div class='add'>+	fps = fi-&gt;interval.numerator</div><div class='add'>+	    ? DIV_ROUND_CLOSEST(fi-&gt;interval.denominator, fi-&gt;interval.numerator)</div><div class='add'>+	    : UINT_MAX;</div><div class='add'>+</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+	mode = thp7312_find_mode(fmt-&gt;width, fmt-&gt;height, false);</div><div class='add'>+	rate = thp7312_find_rate(mode, fps, true);</div><div class='add'>+</div><div class='add'>+	interval = v4l2_subdev_state_get_interval(sd_state, 0);</div><div class='add'>+	interval-&gt;numerator = 1;</div><div class='add'>+	interval-&gt;denominator = rate-&gt;fps;</div><div class='add'>+</div><div class='add'>+	if (fi-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		thp7312-&gt;link_freq = rate-&gt;link_freq;</div><div class='add'>+</div><div class='add'>+	fi-&gt;interval = *interval;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+	struct v4l2_subdev_state *sd_state;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	sd_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='add'>+</div><div class='add'>+	if (!enable) {</div><div class='add'>+		thp7312_stream_enable(thp7312, false);</div><div class='add'>+</div><div class='add'>+		pm_runtime_mark_last_busy(thp7312-&gt;dev);</div><div class='add'>+		pm_runtime_put_autosuspend(thp7312-&gt;dev);</div><div class='add'>+</div><div class='add'>+		v4l2_subdev_unlock_state(sd_state);</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(thp7312-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto finish_unlock;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_init_mode(thp7312, sd_state);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto finish_pm;</div><div class='add'>+</div><div class='add'>+	if (!thp7312-&gt;ctrls_applied) {</div><div class='add'>+		ret = __v4l2_ctrl_handler_setup(&amp;thp7312-&gt;ctrl_handler);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto finish_pm;</div><div class='add'>+</div><div class='add'>+		thp7312-&gt;ctrls_applied = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = thp7312_stream_enable(thp7312, true);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto finish_pm;</div><div class='add'>+</div><div class='add'>+	goto finish_unlock;</div><div class='add'>+</div><div class='add'>+finish_pm:</div><div class='add'>+	pm_runtime_mark_last_busy(thp7312-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(thp7312-&gt;dev);</div><div class='add'>+finish_unlock:</div><div class='add'>+	v4l2_subdev_unlock_state(sd_state);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	const struct thp7312_mode_info *default_mode = &amp;thp7312_mode_info_data[0];</div><div class='add'>+	struct v4l2_mbus_framefmt *fmt;</div><div class='add'>+	struct v4l2_fract *interval;</div><div class='add'>+</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+	interval = v4l2_subdev_state_get_interval(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * default init sequence initialize thp7312 to</div><div class='add'>+	 * YUV422 YUYV VGA@30fps</div><div class='add'>+	 */</div><div class='add'>+	fmt-&gt;code = MEDIA_BUS_FMT_YUYV8_1X16;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='add'>+	fmt-&gt;ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt-&gt;colorspace);</div><div class='add'>+	fmt-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='add'>+	fmt-&gt;xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt-&gt;colorspace);</div><div class='add'>+	fmt-&gt;width = default_mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = default_mode-&gt;height;</div><div class='add'>+	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+</div><div class='add'>+	interval-&gt;numerator = 1;</div><div class='add'>+	interval-&gt;denominator = default_mode-&gt;rates[0].fps;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops thp7312_core_ops = {</div><div class='add'>+	.log_status = v4l2_ctrl_subdev_log_status,</div><div class='add'>+	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,</div><div class='add'>+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops thp7312_video_ops = {</div><div class='add'>+	.s_stream = thp7312_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops thp7312_pad_ops = {</div><div class='add'>+	.enum_mbus_code = thp7312_enum_mbus_code,</div><div class='add'>+	.get_fmt = v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt = thp7312_set_fmt,</div><div class='add'>+	.get_frame_interval = v4l2_subdev_get_frame_interval,</div><div class='add'>+	.set_frame_interval = thp7312_set_frame_interval,</div><div class='add'>+	.enum_frame_size = thp7312_enum_frame_size,</div><div class='add'>+	.enum_frame_interval = thp7312_enum_frame_interval,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops thp7312_subdev_ops = {</div><div class='add'>+	.core = &amp;thp7312_core_ops,</div><div class='add'>+	.video = &amp;thp7312_video_ops,</div><div class='add'>+	.pad = &amp;thp7312_pad_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops thp7312_internal_ops = {</div><div class='add'>+	.init_state = thp7312_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * V4L2 Control Operations</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static inline struct thp7312_device *to_thp7312_from_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	return container_of(ctrl-&gt;handler, struct thp7312_device, ctrl_handler);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* 0: 3000cm, 18: 8cm */</div><div class='add'>+static const u16 thp7312_focus_values[] = {</div><div class='add'>+	3000, 1000, 600, 450, 350,</div><div class='add'>+	290,  240,  200, 170, 150,</div><div class='add'>+	140,  130,  120, 110, 100,</div><div class='add'>+	93,   87,   83,  80,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int thp7312_set_focus(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	enum thp7312_focus_state new_state = thp7312-&gt;focus_state;</div><div class='add'>+	bool continuous;</div><div class='add'>+	u8 af_control;</div><div class='add'>+	u8 af_setting;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Start by programming the manual focus position if it has changed. */</div><div class='add'>+	if (thp7312-&gt;focus_absolute-&gt;is_new) {</div><div class='add'>+		unsigned int value;</div><div class='add'>+</div><div class='add'>+		value = thp7312_focus_values[thp7312-&gt;focus_absolute-&gt;val];</div><div class='add'>+</div><div class='add'>+		ret = cci_write(thp7312-&gt;regmap,</div><div class='add'>+				THP7312_REG_MANUAL_FOCUS_POSITION, value, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Calculate the new focus state. */</div><div class='add'>+	switch (thp7312-&gt;focus_state) {</div><div class='add'>+	case THP7312_FOCUS_STATE_MANUAL:</div><div class='add'>+	default:</div><div class='add'>+		if (thp7312-&gt;focus_auto-&gt;val)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_AUTO;</div><div class='add'>+		else if (thp7312-&gt;focus_start-&gt;is_new)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_ONESHOT;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case THP7312_FOCUS_STATE_AUTO:</div><div class='add'>+		if (!thp7312-&gt;focus_auto-&gt;val)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_LOCKED;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case THP7312_FOCUS_STATE_LOCKED:</div><div class='add'>+		if (thp7312-&gt;focus_auto-&gt;val)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_AUTO;</div><div class='add'>+		else if (thp7312-&gt;focus_start-&gt;is_new)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_ONESHOT;</div><div class='add'>+		else if (thp7312-&gt;focus_absolute-&gt;is_new)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_MANUAL;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case THP7312_FOCUS_STATE_ONESHOT:</div><div class='add'>+		if (thp7312-&gt;focus_auto-&gt;val)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_AUTO;</div><div class='add'>+		else if (thp7312-&gt;focus_start-&gt;is_new)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_ONESHOT;</div><div class='add'>+		else if (thp7312-&gt;focus_absolute-&gt;is_new)</div><div class='add'>+			new_state = THP7312_FOCUS_STATE_MANUAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If neither the state nor the focus method has changed, and no new</div><div class='add'>+	 * one-shot focus is requested, there's nothing new to program to the</div><div class='add'>+	 * hardware.</div><div class='add'>+	 */</div><div class='add'>+	if (thp7312-&gt;focus_state == new_state &amp;&amp;</div><div class='add'>+	    !thp7312-&gt;focus_method-&gt;is_new &amp;&amp; !thp7312-&gt;focus_start-&gt;is_new)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	continuous = new_state == THP7312_FOCUS_STATE_MANUAL ||</div><div class='add'>+		     new_state == THP7312_FOCUS_STATE_ONESHOT;</div><div class='add'>+</div><div class='add'>+	switch (thp7312-&gt;focus_method-&gt;val) {</div><div class='add'>+	case THP7312_FOCUS_METHOD_CONTRAST:</div><div class='add'>+	default:</div><div class='add'>+		af_setting = continuous</div><div class='add'>+			   ? THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST</div><div class='add'>+			   : THP7312_REG_AF_SETTING_ONESHOT_CONTRAST;</div><div class='add'>+		break;</div><div class='add'>+	case THP7312_FOCUS_METHOD_PDAF:</div><div class='add'>+		af_setting = continuous</div><div class='add'>+			   ? THP7312_REG_AF_SETTING_CONTINUOUS_PDAF</div><div class='add'>+			   : THP7312_REG_AF_SETTING_ONESHOT_PDAF;</div><div class='add'>+		break;</div><div class='add'>+	case THP7312_FOCUS_METHOD_HYBRID:</div><div class='add'>+		af_setting = continuous</div><div class='add'>+			   ? THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID</div><div class='add'>+			   : THP7312_REG_AF_SETTING_ONESHOT_HYBRID;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (new_state) {</div><div class='add'>+	case THP7312_FOCUS_STATE_MANUAL:</div><div class='add'>+	default:</div><div class='add'>+		af_control = THP7312_REG_AF_CONTROL_MANUAL;</div><div class='add'>+		break;</div><div class='add'>+	case THP7312_FOCUS_STATE_AUTO:</div><div class='add'>+	case THP7312_FOCUS_STATE_ONESHOT:</div><div class='add'>+		af_control = THP7312_REG_AF_CONTROL_AF;</div><div class='add'>+		break;</div><div class='add'>+	case THP7312_FOCUS_STATE_LOCKED:</div><div class='add'>+		af_control = THP7312_REG_AF_CONTROL_LOCK;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_AF_SETTING, af_setting, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (new_state == THP7312_FOCUS_STATE_MANUAL &amp;&amp;</div><div class='add'>+	    (thp7312-&gt;focus_state == THP7312_FOCUS_STATE_AUTO ||</div><div class='add'>+	     thp7312-&gt;focus_state == THP7312_FOCUS_STATE_ONESHOT)) {</div><div class='add'>+		/* When switching to manual state, lock AF first. */</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_AF_CONTROL,</div><div class='add'>+			  THP7312_REG_AF_CONTROL_LOCK, &amp;ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cci_write(thp7312-&gt;regmap, THP7312_REG_AF_CONTROL, af_control, &amp;ret);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;focus_state = new_state;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_from_ctrl(ctrl);</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u8 value;</div><div class='add'>+</div><div class='add'>+	if (ctrl-&gt;flags &amp; V4L2_CTRL_FLAG_INACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!pm_runtime_get_if_active(thp7312-&gt;dev, true))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_BRIGHTNESS:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_BRIGHTNESS,</div><div class='add'>+			  ctrl-&gt;val + 10, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION:</div><div class='add'>+		/* 0 = Auto adjust frame rate, 1 = Fix frame rate */</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_AE_FIX_FRAME_RATE,</div><div class='add'>+			  ctrl-&gt;val ? 0 : 1, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_FOCUS_AUTO:</div><div class='add'>+	case V4L2_CID_FOCUS_ABSOLUTE:</div><div class='add'>+	case V4L2_CID_AUTO_FOCUS_START:</div><div class='add'>+	case V4L2_CID_THP7312_AUTO_FOCUS_METHOD:</div><div class='add'>+		ret = thp7312_set_focus(thp7312);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+		value = (thp7312-&gt;hflip-&gt;val ? THP7312_REG_FLIP_MIRROR_MIRROR : 0)</div><div class='add'>+		      | (thp7312-&gt;vflip-&gt;val ? THP7312_REG_FLIP_MIRROR_FLIP : 0);</div><div class='add'>+</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_FLIP_MIRROR, value, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_THP7312_NOISE_REDUCTION_AUTO:</div><div class='add'>+	case V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE:</div><div class='add'>+		value = thp7312-&gt;noise_reduction_auto-&gt;val ? 0</div><div class='add'>+		      : THP7312_REG_NOISE_REDUCTION_FIXED |</div><div class='add'>+			thp7312-&gt;noise_reduction_absolute-&gt;val;</div><div class='add'>+</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_NOISE_REDUCTION, value,</div><div class='add'>+			  &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_AUTO_WHITE_BALANCE:</div><div class='add'>+		value = ctrl-&gt;val ? THP7312_WB_MODE_AUTO : THP7312_WB_MODE_MANUAL;</div><div class='add'>+</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_WB_MODE, value, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_RED_BALANCE:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_MANUAL_WB_RED_GAIN,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_BLUE_BALANCE:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_MANUAL_WB_BLUE_GAIN,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_AUTO_EXPOSURE_BIAS:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_AE_EXPOSURE_COMPENSATION,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_POWER_LINE_FREQUENCY:</div><div class='add'>+		if (ctrl-&gt;val == V4L2_CID_POWER_LINE_FREQUENCY_60HZ) {</div><div class='add'>+			value = THP7312_AE_FLICKER_MODE_60;</div><div class='add'>+		} else if (ctrl-&gt;val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) {</div><div class='add'>+			value = THP7312_AE_FLICKER_MODE_50;</div><div class='add'>+		} else {</div><div class='add'>+			if (thp7312-&gt;fw_version == THP7312_FW_VERSION(40, 3)) {</div><div class='add'>+				/* THP7312_AE_FLICKER_MODE_DISABLE is not supported */</div><div class='add'>+				value = THP7312_AE_FLICKER_MODE_50;</div><div class='add'>+			} else {</div><div class='add'>+				value = THP7312_AE_FLICKER_MODE_DISABLE;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_AE_FLICKER_MODE,</div><div class='add'>+			  value, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_SATURATION:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_SATURATION,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_CONTRAST:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_CONTRAST,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case V4L2_CID_SHARPNESS:</div><div class='add'>+		cci_write(thp7312-&gt;regmap, THP7312_REG_SHARPNESS,</div><div class='add'>+			  ctrl-&gt;val, &amp;ret);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_runtime_mark_last_busy(thp7312-&gt;dev);</div><div class='add'>+	pm_runtime_put_autosuspend(thp7312-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops thp7312_ctrl_ops = {</div><div class='add'>+	.s_ctrl = thp7312_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Refer to Documentation/userspace-api/media/drivers/thp7312.rst for details.</div><div class='add'>+ */</div><div class='add'>+static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_cdaf = {</div><div class='add'>+	.ops = &amp;thp7312_ctrl_ops,</div><div class='add'>+	.id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD,</div><div class='add'>+	.name = "Auto-Focus Method",</div><div class='add'>+	.type = V4L2_CTRL_TYPE_INTEGER,</div><div class='add'>+	.min = THP7312_FOCUS_METHOD_CONTRAST,</div><div class='add'>+	.def = THP7312_FOCUS_METHOD_CONTRAST,</div><div class='add'>+	.max = THP7312_FOCUS_METHOD_CONTRAST,</div><div class='add'>+	.step = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_pdaf = {</div><div class='add'>+	.ops = &amp;thp7312_ctrl_ops,</div><div class='add'>+	.id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD,</div><div class='add'>+	.name = "Auto-Focus Method",</div><div class='add'>+	.type = V4L2_CTRL_TYPE_INTEGER,</div><div class='add'>+	.min = THP7312_FOCUS_METHOD_CONTRAST,</div><div class='add'>+	.def = THP7312_FOCUS_METHOD_HYBRID,</div><div class='add'>+	.max = THP7312_FOCUS_METHOD_HYBRID,</div><div class='add'>+	.step = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_config thp7312_v4l2_ctrls_custom[] = {</div><div class='add'>+	{</div><div class='add'>+		.ops = &amp;thp7312_ctrl_ops,</div><div class='add'>+		.id = V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION,</div><div class='add'>+		.name = "Low Light Compensation",</div><div class='add'>+		.type = V4L2_CTRL_TYPE_BOOLEAN,</div><div class='add'>+		.min = 0,</div><div class='add'>+		.def = 1,</div><div class='add'>+		.max = 1,</div><div class='add'>+		.step = 1,</div><div class='add'>+	}, {</div><div class='add'>+		.ops = &amp;thp7312_ctrl_ops,</div><div class='add'>+		.id = V4L2_CID_THP7312_NOISE_REDUCTION_AUTO,</div><div class='add'>+		.name = "Noise Reduction Auto",</div><div class='add'>+		.type = V4L2_CTRL_TYPE_BOOLEAN,</div><div class='add'>+		.min = 0,</div><div class='add'>+		.def = 1,</div><div class='add'>+		.max = 1,</div><div class='add'>+		.step = 1,</div><div class='add'>+	}, {</div><div class='add'>+		.ops = &amp;thp7312_ctrl_ops,</div><div class='add'>+		.id = V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE,</div><div class='add'>+		.name = "Noise Reduction Level",</div><div class='add'>+		.type = V4L2_CTRL_TYPE_INTEGER,</div><div class='add'>+		.min = 0,</div><div class='add'>+		.def = 0,</div><div class='add'>+		.max = 10,</div><div class='add'>+		.step = 1,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const s64 exp_bias_qmenu[] = {</div><div class='add'>+	-2000, -1667, -1333, -1000, -667, -333, 0, 333, 667, 1000, 1333, 1667, 2000</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int thp7312_init_controls(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_ctrl_handler *hdl = &amp;thp7312-&gt;ctrl_handler;</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	struct v4l2_fwnode_device_properties props;</div><div class='add'>+	struct v4l2_ctrl *link_freq;</div><div class='add'>+	unsigned int num_controls;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u8 af_support;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Check what auto-focus methods the connected sensor supports, if any.</div><div class='add'>+	 * Firmwares before v90.03 didn't expose the AF_SUPPORT register,</div><div class='add'>+	 * consider both CDAF and PDAF as supported in that case.</div><div class='add'>+	 */</div><div class='add'>+	if (thp7312-&gt;fw_version &gt;= THP7312_FW_VERSION(90, 3)) {</div><div class='add'>+		u64 val;</div><div class='add'>+</div><div class='add'>+		ret = cci_read(thp7312-&gt;regmap, THP7312_REG_AF_SUPPORT, &amp;val,</div><div class='add'>+			       NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		af_support = val &amp; (THP7312_AF_SUPPORT_PDAF |</div><div class='add'>+				    THP7312_AF_SUPPORT_CONTRAST);</div><div class='add'>+	} else {</div><div class='add'>+		af_support = THP7312_AF_SUPPORT_PDAF</div><div class='add'>+			   | THP7312_AF_SUPPORT_CONTRAST;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	num_controls = 14 + ARRAY_SIZE(thp7312_v4l2_ctrls_custom)</div><div class='add'>+		     + (af_support ? 4 : 0);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_handler_init(hdl, num_controls);</div><div class='add'>+</div><div class='add'>+	if (af_support) {</div><div class='add'>+		const struct v4l2_ctrl_config *af_method;</div><div class='add'>+</div><div class='add'>+		af_method = af_support &amp; THP7312_AF_SUPPORT_PDAF</div><div class='add'>+			  ? &amp;thp7312_ctrl_focus_method_pdaf</div><div class='add'>+			  : &amp;thp7312_ctrl_focus_method_cdaf;</div><div class='add'>+</div><div class='add'>+		thp7312-&gt;focus_state = THP7312_FOCUS_STATE_MANUAL;</div><div class='add'>+</div><div class='add'>+		thp7312-&gt;focus_auto =</div><div class='add'>+			v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					  V4L2_CID_FOCUS_AUTO,</div><div class='add'>+					  0, 1, 1, 1);</div><div class='add'>+		thp7312-&gt;focus_absolute =</div><div class='add'>+			v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					  V4L2_CID_FOCUS_ABSOLUTE,</div><div class='add'>+					  0, ARRAY_SIZE(thp7312_focus_values),</div><div class='add'>+					  1, 0);</div><div class='add'>+		thp7312-&gt;focus_method =</div><div class='add'>+			v4l2_ctrl_new_custom(hdl, af_method, NULL);</div><div class='add'>+		thp7312-&gt;focus_start =</div><div class='add'>+			v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					  V4L2_CID_AUTO_FOCUS_START,</div><div class='add'>+					  1, 1, 1, 1);</div><div class='add'>+</div><div class='add'>+		v4l2_ctrl_cluster(4, &amp;thp7312-&gt;focus_auto);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_AUTO_WHITE_BALANCE,</div><div class='add'>+			  0, 1, 1, 1);</div><div class='add'>+	/* 32: 1x, 255: 7.95x */</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_RED_BALANCE,</div><div class='add'>+			  32, 255, 1, 64);</div><div class='add'>+	/* 32: 1x, 255: 7.95x */</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_BLUE_BALANCE,</div><div class='add'>+			  32, 255, 1, 50);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_BRIGHTNESS,</div><div class='add'>+			  -10, 10, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_SATURATION,</div><div class='add'>+			  0, 31, 1, 10);</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_CONTRAST,</div><div class='add'>+			  0, 20, 1, 10);</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops, V4L2_CID_SHARPNESS,</div><div class='add'>+			  0, 31, 1, 8);</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;hflip = v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					   V4L2_CID_HFLIP, 0, 1, 1, 0);</div><div class='add'>+	thp7312-&gt;vflip = v4l2_ctrl_new_std(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					   V4L2_CID_VFLIP, 0, 1, 1, 0);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_cluster(2, &amp;thp7312-&gt;hflip);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_int_menu(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+			       V4L2_CID_AUTO_EXPOSURE_BIAS,</div><div class='add'>+			       ARRAY_SIZE(exp_bias_qmenu) - 1,</div><div class='add'>+			       ARRAY_SIZE(exp_bias_qmenu) / 2, exp_bias_qmenu);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std_menu(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+			       V4L2_CID_POWER_LINE_FREQUENCY,</div><div class='add'>+			       V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0,</div><div class='add'>+			       V4L2_CID_POWER_LINE_FREQUENCY_50HZ);</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;link_freq = thp7312_mode_info_data[0].rates[0].link_freq;</div><div class='add'>+</div><div class='add'>+	link_freq = v4l2_ctrl_new_int_menu(hdl, &amp;thp7312_ctrl_ops,</div><div class='add'>+					   V4L2_CID_LINK_FREQ, 0, 0,</div><div class='add'>+					   &amp;thp7312-&gt;link_freq);</div><div class='add'>+</div><div class='add'>+	/* Set properties from fwnode (e.g. rotation, orientation). */</div><div class='add'>+	ret = v4l2_fwnode_device_parse(dev, &amp;props);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to parse fwnode: %d\n", ret);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_new_fwnode_properties(hdl, &amp;thp7312_ctrl_ops, &amp;props);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to create new v4l2 ctrl for fwnode properties: %d\n", ret);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(thp7312_v4l2_ctrls_custom); i++) {</div><div class='add'>+		const struct v4l2_ctrl_config *ctrl_cfg =</div><div class='add'>+			&amp;thp7312_v4l2_ctrls_custom[i];</div><div class='add'>+		struct v4l2_ctrl *ctrl;</div><div class='add'>+</div><div class='add'>+		ctrl = v4l2_ctrl_new_custom(hdl, ctrl_cfg, NULL);</div><div class='add'>+</div><div class='add'>+		if (ctrl_cfg-&gt;id == V4L2_CID_THP7312_NOISE_REDUCTION_AUTO)</div><div class='add'>+			thp7312-&gt;noise_reduction_auto = ctrl;</div><div class='add'>+		else if (ctrl_cfg-&gt;id == V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE)</div><div class='add'>+			thp7312-&gt;noise_reduction_absolute = ctrl;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_cluster(2, &amp;thp7312-&gt;noise_reduction_auto);</div><div class='add'>+</div><div class='add'>+	if (hdl-&gt;error) {</div><div class='add'>+		dev_err(dev, "v4l2_ctrl_handler error\n");</div><div class='add'>+		ret = hdl-&gt;error;</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	link_freq-&gt;flags |= V4L2_CTRL_FLAG_READ_ONLY;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	v4l2_ctrl_handler_free(hdl);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * Firmware Update</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * The firmware data is made of 128kB of RAM firmware, followed by a</div><div class='add'>+ * variable-size "header". Both are stored in flash memory.</div><div class='add'>+ */</div><div class='add'>+#define THP7312_FW_RAM_SIZE			(128 * 1024)</div><div class='add'>+#define THP7312_FW_MIN_SIZE			(THP7312_FW_RAM_SIZE + 4)</div><div class='add'>+#define THP7312_FW_MAX_SIZE			(THP7312_FW_RAM_SIZE + 64 * 1024)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Data is first uploaded to the THP7312 128kB SRAM, and then written to flash.</div><div class='add'>+ * The SRAM is exposed over I2C as 32kB banks, and up to 4kB of data can be</div><div class='add'>+ * transferred in a single I2C write.</div><div class='add'>+ */</div><div class='add'>+#define THP7312_RAM_BANK_SIZE			(32 * 1024)</div><div class='add'>+#define THP7312_FW_DOWNLOAD_UNIT		(4 * 1024)</div><div class='add'>+</div><div class='add'>+#define THP7312_FLASH_MEMORY_ERASE_TIMEOUT	40</div><div class='add'>+</div><div class='add'>+#define THP7312_FLASH_MAX_REG_READ_SIZE		10</div><div class='add'>+#define THP7312_FLASH_MAX_REG_DATA_SIZE		10</div><div class='add'>+</div><div class='add'>+static const u8 thp7312_cmd_config_flash_mem_if[] = {</div><div class='add'>+	0xd5, 0x18, 0x00, 0x00, 0x00, 0x80</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 thp7312_cmd_write_to_reg[] = {</div><div class='add'>+	0xd5, 0x0c, 0x80, 0x00, 0x00, 0x00</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u8 thp7312_cmd_read_reg[] = {</div><div class='add'>+	0xd5, 0x04</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * THP7312 Write data from RAM to Flash Memory</div><div class='add'>+ * Command ID FF700F</div><div class='add'>+ * Format: FF700F AA AA AA BB BB BB</div><div class='add'>+ * AA AA AA: destination start address</div><div class='add'>+ * BB BB BB: (write size - 1)</div><div class='add'>+ * Source address always starts from 0</div><div class='add'>+ */</div><div class='add'>+static const u8 thp7312_cmd_write_ram_to_flash[] = { 0xff, 0x70, 0x0f };</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * THP7312 Calculate CRC command</div><div class='add'>+ * Command ID: FF70 09</div><div class='add'>+ * Format: FF70 09 AA AA AA BB BB BB</div><div class='add'>+ * AA AA AA: Start address of calculation</div><div class='add'>+ * BB BB BB: (calculate size - 1)</div><div class='add'>+ */</div><div class='add'>+static const u8 thp7312_cmd_calc_crc[] = { 0xff, 0x70, 0x09 };</div><div class='add'>+</div><div class='add'>+static const u8 thp7312_jedec_rdid[] = { SPINOR_OP_RDID, 0x00, 0x00, 0x00 };</div><div class='add'>+static const u8 thp7312_jedec_rdsr[] = { SPINOR_OP_RDSR, 0x00, 0x00, 0x00 };</div><div class='add'>+static const u8 thp7312_jedec_wen[] = { SPINOR_OP_WREN };</div><div class='add'>+</div><div class='add'>+static int thp7312_read_firmware_version(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	u64 val = 0;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u8 major;</div><div class='add'>+	u8 minor;</div><div class='add'>+</div><div class='add'>+	cci_read(thp7312-&gt;regmap, THP7312_REG_FIRMWARE_VERSION_1, &amp;val, &amp;ret);</div><div class='add'>+	major = val;</div><div class='add'>+</div><div class='add'>+	cci_read(thp7312-&gt;regmap, THP7312_REG_FIRMWARE_VERSION_2, &amp;val, &amp;ret);</div><div class='add'>+	minor = val;</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;fw_version = THP7312_FW_VERSION(major, minor);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_write_buf(struct thp7312_device *thp7312,</div><div class='add'>+			     const u8 *write_buf, u16 write_size)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = to_i2c_client(thp7312-&gt;dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_master_send(client, write_buf, write_size);</div><div class='add'>+	return ret &gt;= 0 ? 0 : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __thp7312_flash_reg_write(struct thp7312_device *thp7312,</div><div class='add'>+				     const u8 *write_buf, u16 write_size)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u8 temp_write_buf[THP7312_FLASH_MAX_REG_DATA_SIZE + 2];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (write_size &gt; THP7312_FLASH_MAX_REG_DATA_SIZE) {</div><div class='add'>+		dev_err(dev, "%s: Write size error size = %d\n",</div><div class='add'>+			__func__, write_size);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = thp7312_write_buf(thp7312, thp7312_cmd_config_flash_mem_if,</div><div class='add'>+				sizeof(thp7312_cmd_config_flash_mem_if));</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "%s: Failed to config flash memory IF: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	temp_write_buf[0] = 0xd5;</div><div class='add'>+	temp_write_buf[1] = 0x00;</div><div class='add'>+	memcpy((temp_write_buf + 2), write_buf, write_size);</div><div class='add'>+	ret = thp7312_write_buf(thp7312, temp_write_buf, write_size + 2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	thp7312_write_buf(thp7312, thp7312_cmd_write_to_reg,</div><div class='add'>+			  sizeof(thp7312_cmd_write_to_reg));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __thp7312_flash_reg_read(struct thp7312_device *thp7312,</div><div class='add'>+				    const u8 *write_buf, u16 write_size,</div><div class='add'>+				    u8 *read_buf, u16 read_size)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = to_i2c_client(thp7312-&gt;dev);</div><div class='add'>+	struct i2c_msg msgs[2];</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = __thp7312_flash_reg_write(thp7312, write_buf, write_size);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	msgs[0].addr = client-&gt;addr;</div><div class='add'>+	msgs[0].flags = 0;</div><div class='add'>+	msgs[0].len = sizeof(thp7312_cmd_read_reg),</div><div class='add'>+	msgs[0].buf = (u8 *)thp7312_cmd_read_reg;</div><div class='add'>+</div><div class='add'>+	msgs[1].addr = client-&gt;addr;</div><div class='add'>+	msgs[1].flags = I2C_M_RD;</div><div class='add'>+	msgs[1].len = read_size;</div><div class='add'>+	msgs[1].buf = read_buf;</div><div class='add'>+</div><div class='add'>+	ret = i2c_transfer(client-&gt;adapter, msgs, ARRAY_SIZE(msgs));</div><div class='add'>+	return ret &gt;= 0 ? 0 : ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define thp7312_flash_reg_write(thp7312, wrbuf) \</div><div class='add'>+	__thp7312_flash_reg_write(thp7312, wrbuf, sizeof(wrbuf))</div><div class='add'>+</div><div class='add'>+#define thp7312_flash_reg_read(thp7312, wrbuf, rdbuf) \</div><div class='add'>+	__thp7312_flash_reg_read(thp7312, wrbuf, sizeof(wrbuf), \</div><div class='add'>+				 rdbuf, sizeof(rdbuf))</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_prepare_config(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = cci_write(thp7312-&gt;regmap, THP7312_REG_FW_MEMORY_IO_SETTING,</div><div class='add'>+			THP7312_FW_MEMORY_IO_GPIO0, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to set flash memory I/O\n");</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set max drivability. */</div><div class='add'>+	ret = cci_write(thp7312-&gt;regmap, THP7312_REG_FW_DRIVABILITY, 0x00777777,</div><div class='add'>+			NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to set drivability: %d\n", ret);</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_prepare_check(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u8 read_buf[3] = { 0 };</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Get JEDEC ID */</div><div class='add'>+	ret = thp7312_flash_reg_read(thp7312, thp7312_jedec_rdid, read_buf);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to get JEDEC ID: %d\n", ret);</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "Flash Memory: JEDEC ID = 0x%x 0x%x 0x%x\n",</div><div class='add'>+		read_buf[0], read_buf[1], read_buf[2]);</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_prepare_reset(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = cci_write(thp7312-&gt;regmap, THP7312_REG_FW_RESET_FLASH, 0x81, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to reset flash memory: %d\n", ret);</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* TODO: Erase only the amount of blocks necessary */</div><div class='add'>+static enum fw_upload_err thp7312_flash_erase(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u8 read_buf[1] = { 0 };</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u8 block;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	for (block = 0; block &lt; 3; block++) {</div><div class='add'>+		const u8 jedec_se[] = { SPINOR_OP_SE, block, 0x00, 0x00 };</div><div class='add'>+</div><div class='add'>+		ret = thp7312_flash_reg_write(thp7312, thp7312_jedec_wen);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(dev, "Failed to enable flash for writing\n");</div><div class='add'>+			return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = thp7312_flash_reg_write(thp7312, jedec_se);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(dev, "Failed to erase flash sector\n");</div><div class='add'>+			return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; THP7312_FLASH_MEMORY_ERASE_TIMEOUT; i++) {</div><div class='add'>+			usleep_range(100000, 101000);</div><div class='add'>+			thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr,</div><div class='add'>+					       read_buf);</div><div class='add'>+</div><div class='add'>+			/* Check Busy bit. Busy == 0x0 means erase complete. */</div><div class='add'>+			if (!(read_buf[0] &amp; SR_WIP))</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (i == THP7312_FLASH_MEMORY_ERASE_TIMEOUT)</div><div class='add'>+			return FW_UPLOAD_ERR_TIMEOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr, read_buf);</div><div class='add'>+</div><div class='add'>+	/* Check WEL bit. */</div><div class='add'>+	if (read_buf[0] &amp; SR_WEL)</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err</div><div class='add'>+thp7312_write_download_data_by_unit(struct thp7312_device *thp7312,</div><div class='add'>+				    unsigned int addr, const u8 *data,</div><div class='add'>+				    unsigned int size)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u8 *write_buf = thp7312-&gt;fw_write_buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "%s: addr = 0x%04x, data = 0x%p, size = %u\n",</div><div class='add'>+		__func__, addr, data, size);</div><div class='add'>+</div><div class='add'>+	write_buf[0] = (addr &gt;&gt; 8) &amp; 0xff;</div><div class='add'>+	write_buf[1] = (addr &gt;&gt; 0) &amp; 0xff;</div><div class='add'>+	memcpy(&amp;write_buf[2], data, size);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * THP7312 Firmware download to RAM</div><div class='add'>+	 * Command ID (address to download): 0x0000 - 0x7fff</div><div class='add'>+	 * Format:: 0000 XX XX XX ........ XX</div><div class='add'>+	 */</div><div class='add'>+	ret = thp7312_write_buf(thp7312, write_buf, size + 2);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(dev, "Unit transfer ERROR %s(): ret = %d\n", __func__, ret);</div><div class='add'>+</div><div class='add'>+	return ret &gt;= 0 ? FW_UPLOAD_ERR_NONE : FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_load_to_ram(struct thp7312_device *thp7312,</div><div class='add'>+						 const u8 *data, u32 size)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	enum fw_upload_err ret;</div><div class='add'>+	unsigned int num_banks;</div><div class='add'>+	unsigned int i, j;</div><div class='add'>+</div><div class='add'>+	num_banks = DIV_ROUND_UP(size, THP7312_RAM_BANK_SIZE);</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "%s: loading %u bytes in SRAM (%u banks)\n", __func__,</div><div class='add'>+		size, num_banks);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_banks; i++) {</div><div class='add'>+		const u32 bank_addr = 0x10000000 | (i * THP7312_RAM_BANK_SIZE);</div><div class='add'>+		unsigned int bank_size;</div><div class='add'>+		unsigned int num_chunks;</div><div class='add'>+</div><div class='add'>+		ret = cci_write(thp7312-&gt;regmap, THP7312_REG_FW_DEST_BANK_ADDR,</div><div class='add'>+				bank_addr, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+</div><div class='add'>+		bank_size = min_t(u32, size, THP7312_RAM_BANK_SIZE);</div><div class='add'>+		num_chunks = DIV_ROUND_UP(bank_size, THP7312_FW_DOWNLOAD_UNIT);</div><div class='add'>+</div><div class='add'>+		dev_dbg(dev, "%s: loading %u bytes in SRAM bank %u (%u chunks)\n",</div><div class='add'>+			__func__, bank_size, i, num_chunks);</div><div class='add'>+</div><div class='add'>+		for (j = 0 ; j &lt; num_chunks; j++) {</div><div class='add'>+			unsigned int chunk_addr;</div><div class='add'>+			unsigned int chunk_size;</div><div class='add'>+</div><div class='add'>+			chunk_addr = j * THP7312_FW_DOWNLOAD_UNIT;</div><div class='add'>+			chunk_size = min_t(u32, size, THP7312_FW_DOWNLOAD_UNIT);</div><div class='add'>+</div><div class='add'>+			ret = thp7312_write_download_data_by_unit(thp7312, chunk_addr,</div><div class='add'>+								  data, chunk_size);</div><div class='add'>+			if (ret != FW_UPLOAD_ERR_NONE) {</div><div class='add'>+				dev_err(dev, "Unit transfer ERROR at bank transfer %s(): %d\n",</div><div class='add'>+					__func__, j);</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			data += chunk_size;</div><div class='add'>+			size -= chunk_size;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_write_to_flash(struct thp7312_device *thp7312,</div><div class='add'>+						    u32 dest, u32 write_size)</div><div class='add'>+{</div><div class='add'>+	u8 command[sizeof(thp7312_cmd_write_ram_to_flash) + 6];</div><div class='add'>+	static const u32 cmd_size = sizeof(thp7312_cmd_write_ram_to_flash);</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	memcpy(command, thp7312_cmd_write_ram_to_flash, cmd_size);</div><div class='add'>+</div><div class='add'>+	command[cmd_size] = (dest &amp; 0xff0000) &gt;&gt; 16;</div><div class='add'>+	command[cmd_size + 1] = (dest &amp; 0x00ff00) &gt;&gt; 8;</div><div class='add'>+	command[cmd_size + 2] = (dest &amp; 0x0000ff);</div><div class='add'>+	command[cmd_size + 3] = ((write_size - 1) &amp; 0xff0000) &gt;&gt; 16;</div><div class='add'>+	command[cmd_size + 4] = ((write_size - 1) &amp; 0x00ff00) &gt;&gt; 8;</div><div class='add'>+	command[cmd_size + 5] = ((write_size - 1) &amp; 0x0000ff);</div><div class='add'>+</div><div class='add'>+	ret = thp7312_write_buf(thp7312, command, sizeof(command));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+</div><div class='add'>+	usleep_range(8000000, 8100000);</div><div class='add'>+</div><div class='add'>+	ret = cci_read(thp7312-&gt;regmap, THP7312_REG_FW_VERIFY_RESULT, &amp;val,</div><div class='add'>+		       NULL);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+</div><div class='add'>+	return val ?  FW_UPLOAD_ERR_HW_ERROR : FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_check_crc(struct thp7312_device *thp7312,</div><div class='add'>+					       const u8 *fw_data, u32 fw_size)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u16 header_size = fw_size - THP7312_FW_RAM_SIZE;</div><div class='add'>+	u8 command[sizeof(thp7312_cmd_calc_crc) + 6];</div><div class='add'>+	static const u32 cmd_size = sizeof(thp7312_cmd_calc_crc);</div><div class='add'>+	u32 size = THP7312_FW_RAM_SIZE - 4;</div><div class='add'>+	u32 fw_crc;</div><div class='add'>+	u64 crc;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	memcpy(command, thp7312_cmd_calc_crc, cmd_size);</div><div class='add'>+</div><div class='add'>+	command[cmd_size] = 0;</div><div class='add'>+	command[cmd_size + 1] = (header_size &gt;&gt; 8) &amp; 0xff;</div><div class='add'>+	command[cmd_size + 2] = header_size &amp; 0xff;</div><div class='add'>+</div><div class='add'>+	command[cmd_size + 3] = (size &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	command[cmd_size + 4] = (size &gt;&gt; 8) &amp; 0xff;</div><div class='add'>+	command[cmd_size + 5] = size &amp; 0xff;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_write_buf(thp7312, command, sizeof(command));</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+</div><div class='add'>+	usleep_range(2000000, 2100000);</div><div class='add'>+</div><div class='add'>+	fw_crc = get_unaligned_be32(&amp;fw_data[fw_size - 4]);</div><div class='add'>+</div><div class='add'>+	ret = cci_read(thp7312-&gt;regmap, THP7312_REG_FW_CRC_RESULT, &amp;crc, NULL);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return FW_UPLOAD_ERR_RW_ERROR;</div><div class='add'>+</div><div class='add'>+	if (fw_crc != crc) {</div><div class='add'>+		dev_err(dev, "CRC mismatch: firmware 0x%08x, flash 0x%08llx\n",</div><div class='add'>+			fw_crc, crc);</div><div class='add'>+		return FW_UPLOAD_ERR_HW_ERROR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_prepare(struct fw_upload *fw_upload,</div><div class='add'>+					     const u8 *data, u32 size)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = fw_upload-&gt;dd_handle;</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	enum fw_upload_err ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+	thp7312-&gt;fw_cancel = false;</div><div class='add'>+	mutex_unlock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+</div><div class='add'>+	if (size &lt; THP7312_FW_MIN_SIZE || size &gt; THP7312_FW_MAX_SIZE) {</div><div class='add'>+		dev_err(dev, "%s: Invalid firmware size %d; must be between %d and %d\n",</div><div class='add'>+			__func__, size, THP7312_FW_MIN_SIZE, THP7312_FW_MAX_SIZE);</div><div class='add'>+		return FW_UPLOAD_ERR_INVALID_SIZE;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_prepare_config(thp7312);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_prepare_check(thp7312);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_prepare_reset(thp7312);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+	ret = thp7312-&gt;fw_cancel ? FW_UPLOAD_ERR_CANCELED : FW_UPLOAD_ERR_NONE;</div><div class='add'>+	mutex_unlock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_write(struct fw_upload *fw_upload,</div><div class='add'>+					   const u8 *data, u32 offset,</div><div class='add'>+					   u32 size, u32 *written)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = fw_upload-&gt;dd_handle;</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	u16 header_size = size - THP7312_FW_RAM_SIZE;</div><div class='add'>+	enum fw_upload_err ret;</div><div class='add'>+	bool cancel;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+	cancel = thp7312-&gt;fw_cancel;</div><div class='add'>+	mutex_unlock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+</div><div class='add'>+	if (cancel)</div><div class='add'>+		return FW_UPLOAD_ERR_CANCELED;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_flash_erase(thp7312);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_load_to_ram(thp7312, data, THP7312_FW_RAM_SIZE);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_write_to_flash(thp7312, 0, 0x1ffff);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_load_to_ram(thp7312, data + THP7312_FW_RAM_SIZE, header_size);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_write_to_flash(thp7312, 0x20000, header_size - 1);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_fw_check_crc(thp7312, data, size);</div><div class='add'>+	if (ret != FW_UPLOAD_ERR_NONE)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "Successfully wrote firmware\n");</div><div class='add'>+</div><div class='add'>+	*written = size;</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum fw_upload_err thp7312_fw_poll_complete(struct fw_upload *fw_upload)</div><div class='add'>+{</div><div class='add'>+	return FW_UPLOAD_ERR_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * This may be called asynchronously with an on-going update.  All other</div><div class='add'>+ * functions are called sequentially in a single thread. To avoid contention on</div><div class='add'>+ * register accesses, only update the cancel_request flag. Other functions will</div><div class='add'>+ * check this flag and handle the cancel request synchronously.</div><div class='add'>+ */</div><div class='add'>+static void thp7312_fw_cancel(struct fw_upload *fw_upload)</div><div class='add'>+{</div><div class='add'>+	struct thp7312_device *thp7312 = fw_upload-&gt;dd_handle;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+	thp7312-&gt;fw_cancel = true;</div><div class='add'>+	mutex_unlock(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct fw_upload_ops thp7312_fw_upload_ops = {</div><div class='add'>+	.prepare = thp7312_fw_prepare,</div><div class='add'>+	.write = thp7312_fw_write,</div><div class='add'>+	.poll_complete = thp7312_fw_poll_complete,</div><div class='add'>+	.cancel = thp7312_fw_cancel,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int thp7312_register_flash_mode(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	struct fw_upload *fwl;</div><div class='add'>+	u64 val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "booted in flash mode\n");</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;thp7312-&gt;fw_lock);</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;fw_write_buf = devm_kzalloc(dev, THP7312_FW_DOWNLOAD_UNIT + 2,</div><div class='add'>+					     GFP_KERNEL);</div><div class='add'>+	if (!thp7312-&gt;fw_write_buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = __thp7312_power_on(thp7312);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return dev_err_probe(dev, ret, "Failed to power on\n");</div><div class='add'>+</div><div class='add'>+	ret = cci_read(thp7312-&gt;regmap, THP7312_REG_FW_STATUS, &amp;val, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "Camera status read failed\n");</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fwl = firmware_upload_register(THIS_MODULE, dev, "thp7312-firmware",</div><div class='add'>+				       &amp;thp7312_fw_upload_ops, thp7312);</div><div class='add'>+	if (IS_ERR(fwl)) {</div><div class='add'>+		ret = PTR_ERR(fwl);</div><div class='add'>+		dev_err_probe(dev, ret, "Failed to register firmware upload\n");</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;fwl = fwl;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error:</div><div class='add'>+	__thp7312_power_off(thp7312);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* -----------------------------------------------------------------------------</div><div class='add'>+ * Probe &amp; Remove</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static int thp7312_get_regulators(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(thp7312-&gt;supplies); i++)</div><div class='add'>+		thp7312-&gt;supplies[i].supply = thp7312_supply_name[i];</div><div class='add'>+</div><div class='add'>+	return devm_regulator_bulk_get(thp7312-&gt;dev,</div><div class='add'>+				       ARRAY_SIZE(thp7312-&gt;supplies),</div><div class='add'>+				       thp7312-&gt;supplies);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_sensor_parse_dt(struct thp7312_device *thp7312,</div><div class='add'>+				   struct fwnode_handle *node)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	struct thp7312_sensor *sensor;</div><div class='add'>+	const char *model;</div><div class='add'>+	u8 data_lanes[4];</div><div class='add'>+	u32 values[4];</div><div class='add'>+	unsigned int i;</div><div class='add'>+	u32 reg;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Retrieve the sensor index from the reg property. */</div><div class='add'>+	ret = fwnode_property_read_u32(node, "reg", &amp;reg);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "'reg' property missing in sensor node\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (reg &gt;= ARRAY_SIZE(thp7312-&gt;sensors)) {</div><div class='add'>+		dev_err(dev, "Out-of-bounds 'reg' value %u\n", reg);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sensor = &amp;thp7312-&gt;sensors[reg];</div><div class='add'>+	if (sensor-&gt;info) {</div><div class='add'>+		dev_err(dev, "Duplicate entry for sensor %u\n", reg);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_read_string(node, "thine,model", &amp;model);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "'thine,model' property missing in sensor node\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(thp7312_sensor_info); i++) {</div><div class='add'>+		const struct thp7312_sensor_info *info =</div><div class='add'>+			&amp;thp7312_sensor_info[i];</div><div class='add'>+</div><div class='add'>+		if (!strcmp(info-&gt;model, model)) {</div><div class='add'>+			sensor-&gt;info = info;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!sensor-&gt;info) {</div><div class='add'>+		dev_err(dev, "Unsupported sensor model %s\n", model);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = fwnode_property_read_u32_array(node, "data-lanes", values,</div><div class='add'>+					     ARRAY_SIZE(values));</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "Failed to read property data-lanes: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(data_lanes); ++i)</div><div class='add'>+		data_lanes[i] = values[i];</div><div class='add'>+</div><div class='add'>+	ret = thp7312_map_data_lanes(&amp;sensor-&gt;lane_remap, data_lanes,</div><div class='add'>+				     ARRAY_SIZE(data_lanes));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Invalid sensor@%u data-lanes value\n", reg);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_parse_dt(struct thp7312_device *thp7312)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_fwnode_endpoint ep = {</div><div class='add'>+		.bus_type = V4L2_MBUS_CSI2_DPHY,</div><div class='add'>+	};</div><div class='add'>+	struct device *dev = thp7312-&gt;dev;</div><div class='add'>+	struct fwnode_handle *endpoint;</div><div class='add'>+	struct fwnode_handle *sensors;</div><div class='add'>+	unsigned int num_sensors = 0;</div><div class='add'>+	struct fwnode_handle *node;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);</div><div class='add'>+	if (!endpoint)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL, "Endpoint node not found\n");</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_endpoint_parse(endpoint, &amp;ep);</div><div class='add'>+	fwnode_handle_put(endpoint);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "Could not parse endpoint\n");</div><div class='add'>+</div><div class='add'>+	ret = thp7312_map_data_lanes(&amp;thp7312-&gt;lane_remap,</div><div class='add'>+				     ep.bus.mipi_csi2.data_lanes,</div><div class='add'>+				     ep.bus.mipi_csi2.num_data_lanes);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Invalid data-lanes value\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The thine,boot-mode property is optional and default to</div><div class='add'>+	 * THP7312_BOOT_MODE_SPI_MASTER (1).</div><div class='add'>+	 */</div><div class='add'>+	thp7312-&gt;boot_mode = THP7312_BOOT_MODE_SPI_MASTER;</div><div class='add'>+	ret = device_property_read_u32(dev, "thine,boot-mode",</div><div class='add'>+				       &amp;thp7312-&gt;boot_mode);</div><div class='add'>+	if (ret &amp;&amp; ret != -EINVAL)</div><div class='add'>+		return dev_err_probe(dev, ret, "Property '%s' is invalid\n",</div><div class='add'>+				     "thine,boot-mode");</div><div class='add'>+</div><div class='add'>+	if (thp7312-&gt;boot_mode != THP7312_BOOT_MODE_2WIRE_SLAVE &amp;&amp;</div><div class='add'>+	    thp7312-&gt;boot_mode != THP7312_BOOT_MODE_SPI_MASTER)</div><div class='add'>+		return dev_err_probe(dev, -EINVAL, "Invalid '%s' value %u\n",</div><div class='add'>+				     "thine,boot-mode", thp7312-&gt;boot_mode);</div><div class='add'>+</div><div class='add'>+	/* Sensors */</div><div class='add'>+	sensors = device_get_named_child_node(dev, "sensors");</div><div class='add'>+	if (!sensors) {</div><div class='add'>+		dev_err(dev, "'sensors' child node not found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fwnode_for_each_available_child_node(sensors, node) {</div><div class='add'>+		if (fwnode_name_eq(node, "sensor")) {</div><div class='add'>+			if (!thp7312_sensor_parse_dt(thp7312, node))</div><div class='add'>+				num_sensors++;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fwnode_handle_put(sensors);</div><div class='add'>+</div><div class='add'>+	if (!num_sensors) {</div><div class='add'>+		dev_err(dev, "No sensor found\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int thp7312_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct thp7312_device *thp7312;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	thp7312 = devm_kzalloc(dev, sizeof(*thp7312), GFP_KERNEL);</div><div class='add'>+	if (!thp7312)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;regmap = devm_cci_regmap_init_i2c(client, 16);</div><div class='add'>+	if (IS_ERR(thp7312-&gt;regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(thp7312-&gt;regmap),</div><div class='add'>+				     "Unable to initialize I2C\n");</div><div class='add'>+</div><div class='add'>+	ret = thp7312_parse_dt(thp7312);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_get_regulators(thp7312);</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "Failed to get regulators\n");</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;iclk = devm_clk_get(dev, NULL);</div><div class='add'>+	if (IS_ERR(thp7312-&gt;iclk))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(thp7312-&gt;iclk),</div><div class='add'>+				     "Failed to get iclk\n");</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(thp7312-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(thp7312-&gt;reset_gpio),</div><div class='add'>+				     "Failed to get reset gpio\n");</div><div class='add'>+</div><div class='add'>+	if (thp7312-&gt;boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE)</div><div class='add'>+		return thp7312_register_flash_mode(thp7312);</div><div class='add'>+</div><div class='add'>+	v4l2_i2c_subdev_init(&amp;thp7312-&gt;sd, client, &amp;thp7312_subdev_ops);</div><div class='add'>+	thp7312-&gt;sd.internal_ops = &amp;thp7312_internal_ops;</div><div class='add'>+	thp7312-&gt;sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+	thp7312-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+	thp7312-&gt;sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;</div><div class='add'>+</div><div class='add'>+	ret = media_entity_pads_init(&amp;thp7312-&gt;sd.entity, 1, &amp;thp7312-&gt;pad);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enable power management. The driver supports runtime PM, but needs to</div><div class='add'>+	 * work when runtime PM is disabled in the kernel. To that end, power</div><div class='add'>+	 * the device manually here.</div><div class='add'>+	 */</div><div class='add'>+	ret = thp7312_power_on(thp7312);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_entity_cleanup;</div><div class='add'>+</div><div class='add'>+	ret = thp7312_read_firmware_version(thp7312);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "Camera is not found\n");</div><div class='add'>+		goto err_power_off;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = thp7312_init_controls(thp7312);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to initialize controls\n");</div><div class='add'>+		goto err_power_off;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	thp7312-&gt;sd.ctrl_handler = &amp;thp7312-&gt;ctrl_handler;</div><div class='add'>+	thp7312-&gt;sd.state_lock = thp7312-&gt;ctrl_handler.lock;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_init_finalize(&amp;thp7312-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "Subdev active state initialization failed\n");</div><div class='add'>+		goto err_free_ctrls;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Enable runtime PM with autosuspend. As the device has been powered</div><div class='add'>+	 * manually, mark it as active, and increase the usage count without</div><div class='add'>+	 * resuming the device.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_set_active(dev);</div><div class='add'>+	pm_runtime_get_noresume(dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+	pm_runtime_set_autosuspend_delay(dev, 1000);</div><div class='add'>+	pm_runtime_use_autosuspend(dev);</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev(&amp;thp7312-&gt;sd);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "Subdev registration failed\n");</div><div class='add'>+		goto err_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Decrease the PM usage count. The device will get suspended after the</div><div class='add'>+	 * autosuspend delay, turning the power off.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_mark_last_busy(dev);</div><div class='add'>+	pm_runtime_put_autosuspend(dev);</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "THP7312 firmware version %02u.%02u\n",</div><div class='add'>+		 THP7312_FW_VERSION_MAJOR(thp7312-&gt;fw_version),</div><div class='add'>+		 THP7312_FW_VERSION_MINOR(thp7312-&gt;fw_version));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_pm:</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	pm_runtime_put_noidle(dev);</div><div class='add'>+	v4l2_subdev_cleanup(&amp;thp7312-&gt;sd);</div><div class='add'>+err_free_ctrls:</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;thp7312-&gt;ctrl_handler);</div><div class='add'>+err_power_off:</div><div class='add'>+	thp7312_power_off(thp7312);</div><div class='add'>+err_entity_cleanup:</div><div class='add'>+	media_entity_cleanup(&amp;thp7312-&gt;sd.entity);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void thp7312_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct thp7312_device *thp7312 = to_thp7312_dev(sd);</div><div class='add'>+</div><div class='add'>+	if (thp7312-&gt;boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE) {</div><div class='add'>+		firmware_upload_unregister(thp7312-&gt;fwl);</div><div class='add'>+		__thp7312_power_off(thp7312);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_async_unregister_subdev(&amp;thp7312-&gt;sd);</div><div class='add'>+	v4l2_subdev_cleanup(&amp;thp7312-&gt;sd);</div><div class='add'>+	media_entity_cleanup(&amp;thp7312-&gt;sd.entity);</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;thp7312-&gt;ctrl_handler);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Disable runtime PM. In case runtime PM is disabled in the kernel,</div><div class='add'>+	 * make sure to turn power off manually.</div><div class='add'>+	 */</div><div class='add'>+	pm_runtime_disable(thp7312-&gt;dev);</div><div class='add'>+	if (!pm_runtime_status_suspended(thp7312-&gt;dev))</div><div class='add'>+		thp7312_power_off(thp7312);</div><div class='add'>+	pm_runtime_set_suspended(thp7312-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id thp7312_dt_ids[] = {</div><div class='add'>+	{ .compatible = "thine,thp7312" },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, thp7312_dt_ids);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver thp7312_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name  = "thp7312",</div><div class='add'>+		.pm = &amp;thp7312_pm_ops,</div><div class='add'>+		.of_match_table	= thp7312_dt_ids,</div><div class='add'>+	},</div><div class='add'>+	.probe = thp7312_probe,</div><div class='add'>+	.remove = thp7312_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(thp7312_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("THP7312 MIPI Camera Subdev Driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/tvp514x.c b/drivers/media/i2c/tvp514x.c<br/>index c37f605cb75f..5a561e5bf659 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp514x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tvp514x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp514x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp514x.c</a></div><div class='hunk'>@@ -738,20 +738,20 @@ static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * tvp514x_g_frame_interval() - V4L2 decoder interface handler</div><div class='del'>- * @sd: pointer to standard V4L2 sub-device structure</div><div class='del'>- * @ival: pointer to a v4l2_subdev_frame_interval structure</div><div class='del'>- *</div><div class='del'>- * Returns the decoder's video CAPTURE parameters.</div><div class='del'>- */</div><div class='ctx'> static int</div><div class='del'>-tvp514x_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-			 struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+tvp514x_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+			   struct v4l2_subdev_state *sd_state,</div><div class='add'>+			   struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct tvp514x_decoder *decoder = to_decoder(sd);</div><div class='ctx'> 	enum tvp514x_std current_std;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* get the current standard */</div><div class='ctx'> 	current_std = decoder-&gt;current_std;</div><div class='hunk'>@@ -762,22 +762,21 @@ tvp514x_g_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * tvp514x_s_frame_interval() - V4L2 decoder interface handler</div><div class='del'>- * @sd: pointer to standard V4L2 sub-device structure</div><div class='del'>- * @ival: pointer to a v4l2_subdev_frame_interval structure</div><div class='del'>- *</div><div class='del'>- * Configures the decoder to use the input parameters, if possible. If</div><div class='del'>- * not possible, returns the appropriate error code.</div><div class='del'>- */</div><div class='ctx'> static int</div><div class='del'>-tvp514x_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-			 struct v4l2_subdev_frame_interval *ival)</div><div class='add'>+tvp514x_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+			   struct v4l2_subdev_state *sd_state,</div><div class='add'>+			   struct v4l2_subdev_frame_interval *ival)</div><div class='ctx'> {</div><div class='ctx'> 	struct tvp514x_decoder *decoder = to_decoder(sd);</div><div class='ctx'> 	struct v4l2_fract *timeperframe;</div><div class='ctx'> 	enum tvp514x_std current_std;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2</div><div class='add'>+	 * subdev active state API.</div><div class='add'>+	 */</div><div class='add'>+	if (ival-&gt;which != V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	timeperframe = &amp;ival-&gt;interval;</div><div class='ctx'> </div><div class='hunk'>@@ -940,8 +939,6 @@ static const struct v4l2_subdev_video_ops tvp514x_video_ops = {</div><div class='ctx'> 	.s_std = tvp514x_s_std,</div><div class='ctx'> 	.s_routing = tvp514x_s_routing,</div><div class='ctx'> 	.querystd = tvp514x_querystd,</div><div class='del'>-	.g_frame_interval = tvp514x_g_frame_interval,</div><div class='del'>-	.s_frame_interval = tvp514x_s_frame_interval,</div><div class='ctx'> 	.s_stream = tvp514x_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -949,6 +946,8 @@ static const struct v4l2_subdev_pad_ops tvp514x_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = tvp514x_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = tvp514x_get_pad_format,</div><div class='ctx'> 	.set_fmt = tvp514x_set_pad_format,</div><div class='add'>+	.get_frame_interval = tvp514x_get_frame_interval,</div><div class='add'>+	.set_frame_interval = tvp514x_set_frame_interval,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_ops tvp514x_ops = {</div><div class='head'>diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c<br/>index e543b3f7a4d8..9fc586cfdcd8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp5150.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tvp5150.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp5150.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp5150.c</a></div><div class='hunk'>@@ -1035,7 +1035,7 @@ tvp5150_get_pad_crop(struct tvp5150 *decoder,</div><div class='ctx'> 		return &amp;decoder-&gt;rect;</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='ctx'> #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;decoder-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> #else</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> #endif</div><div class='hunk'>@@ -1209,8 +1209,8 @@ static int tvp5150_get_mbus_config(struct v4l2_subdev *sd,</div><div class='ctx'> /****************************************************************************</div><div class='ctx'> 			V4L2 subdev pad ops</div><div class='ctx'>  ****************************************************************************/</div><div class='del'>-static int tvp5150_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int tvp5150_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct tvp5150 *decoder = to_tvp5150(sd);</div><div class='ctx'> 	v4l2_std_id std;</div><div class='hunk'>@@ -1722,7 +1722,6 @@ static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {</div><div class='del'>-	.init_cfg = tvp5150_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = tvp5150_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = tvp5150_enum_frame_size,</div><div class='ctx'> 	.set_fmt = tvp5150_fill_fmt,</div><div class='hunk'>@@ -1741,6 +1740,7 @@ static const struct v4l2_subdev_ops tvp5150_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_internal_ops tvp5150_internal_ops = {</div><div class='add'>+	.init_state = tvp5150_init_state,</div><div class='ctx'> 	.registered = tvp5150_registered,</div><div class='ctx'> 	.open = tvp5150_open,</div><div class='ctx'> 	.close = tvp5150_close,</div><div class='head'>diff --git a/drivers/media/i2c/tvp7002.c b/drivers/media/i2c/tvp7002.c<br/>index a2d7bc799849..30831b4b56d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp7002.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tvp7002.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tvp7002.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tvp7002.c</a></div><div class='hunk'>@@ -791,7 +791,7 @@ static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {</div><div class='ctx'> /*</div><div class='ctx'>  * tvp7002_enum_mbus_code() - Enum supported digital video format on pad</div><div class='ctx'>  * @sd: pointer to standard V4L2 sub-device structure</div><div class='del'>- * @cfg: pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: pointer to subdev enum mbus code struct</div><div class='ctx'>  *</div><div class='ctx'>  * Enumerate supported digital video formats for pad.</div><div class='hunk'>@@ -813,7 +813,7 @@ tvp7002_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * tvp7002_get_pad_format() - get video format on pad</div><div class='ctx'>  * @sd: pointer to standard V4L2 sub-device structure</div><div class='del'>- * @cfg: pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to subdev format struct</div><div class='ctx'>  *</div><div class='ctx'>  * get video format for pad.</div><div class='hunk'>@@ -837,7 +837,7 @@ tvp7002_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * tvp7002_set_pad_format() - set video format on pad</div><div class='ctx'>  * @sd: pointer to standard V4L2 sub-device structure</div><div class='del'>- * @cfg: pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to subdev format struct</div><div class='ctx'>  *</div><div class='ctx'>  * set video format for pad.</div><div class='head'>diff --git a/drivers/media/i2c/tw9900.c b/drivers/media/i2c/tw9900.c<br/>new file mode 100644<br/>index 000000000000..bc7623ec46e5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tw9900.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tw9900.c</a></div><div class='hunk'>@@ -0,0 +1,781 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for the Techwell TW9900 multi-standard video decoder.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.</div><div class='add'>+ * Copyright (C) 2020 Maxime Chevallier &lt;maxime.chevallier@bootlin.com&gt;</div><div class='add'>+ * Copyright (C) 2023 Mehdi Djait &lt;mehdi.djait@bootlin.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/i2c.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;media/media-entity.h&gt;</div><div class='add'>+#include &lt;media/v4l2-async.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#define TW9900_REG_CHIP_ID			0x00</div><div class='add'>+#define TW9900_REG_CHIP_STATUS			0x01</div><div class='add'>+#define TW9900_REG_CHIP_STATUS_VDLOSS		BIT(7)</div><div class='add'>+#define TW9900_REG_CHIP_STATUS_HLOCK		BIT(6)</div><div class='add'>+#define TW9900_REG_OUT_FMT_CTL			0x03</div><div class='add'>+#define TW9900_REG_OUT_FMT_CTL_STANDBY		0xA7</div><div class='add'>+#define TW9900_REG_OUT_FMT_CTL_STREAMING	0xA0</div><div class='add'>+#define TW9900_REG_CKHY_HSDLY			0x04</div><div class='add'>+#define TW9900_REG_OUT_CTRL_I			0x05</div><div class='add'>+#define TW9900_REG_ANALOG_CTL			0x06</div><div class='add'>+#define TW9900_REG_CROP_HI			0x07</div><div class='add'>+#define TW9900_REG_VDELAY_LO			0x08</div><div class='add'>+#define TW9900_REG_VACTIVE_LO			0x09</div><div class='add'>+#define TW9900_REG_HACTIVE_LO			0x0B</div><div class='add'>+#define TW9900_REG_CNTRL1			0x0C</div><div class='add'>+#define TW9900_REG_BRIGHT_CTL			0x10</div><div class='add'>+#define TW9900_REG_CONTRAST_CTL			0x11</div><div class='add'>+#define TW9900_REG_VBI_CNTL			0x19</div><div class='add'>+#define TW9900_REG_ANAL_CTL_II			0x1A</div><div class='add'>+#define TW9900_REG_OUT_CTRL_II			0x1B</div><div class='add'>+#define TW9900_REG_STD				0x1C</div><div class='add'>+#define TW9900_REG_STD_AUTO_PROGRESS		BIT(7)</div><div class='add'>+#define TW9900_STDNOW_MASK			GENMASK(6, 4)</div><div class='add'>+#define TW9900_REG_STDR				0x1D</div><div class='add'>+#define TW9900_REG_MISSCNT			0x26</div><div class='add'>+#define TW9900_REG_MISC_CTL_II			0x2F</div><div class='add'>+#define TW9900_REG_VVBI				0x55</div><div class='add'>+</div><div class='add'>+#define TW9900_CHIP_ID				0x00</div><div class='add'>+#define TW9900_STD_NTSC_M			0</div><div class='add'>+#define TW9900_STD_PAL_BDGHI			1</div><div class='add'>+#define TW9900_STD_AUTO				7</div><div class='add'>+</div><div class='add'>+#define TW9900_VIDEO_POLL_TRIES			20</div><div class='add'>+</div><div class='add'>+struct regval {</div><div class='add'>+	u8 addr;</div><div class='add'>+	u8 val;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tw9900_mode {</div><div class='add'>+	u32 width;</div><div class='add'>+	u32 height;</div><div class='add'>+	u32 std;</div><div class='add'>+	const struct regval *reg_list;</div><div class='add'>+	int n_regs;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct tw9900 {</div><div class='add'>+	struct i2c_client *client;</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	struct regulator *regulator;</div><div class='add'>+</div><div class='add'>+	struct v4l2_subdev subdev;</div><div class='add'>+	struct v4l2_ctrl_handler hdl;</div><div class='add'>+	struct media_pad pad;</div><div class='add'>+</div><div class='add'>+	/* Serialize access to hardware and global state. */</div><div class='add'>+	struct mutex mutex;</div><div class='add'>+</div><div class='add'>+	bool streaming;</div><div class='add'>+	const struct tw9900_mode *cur_mode;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define to_tw9900(sd) container_of(sd, struct tw9900, subdev)</div><div class='add'>+</div><div class='add'>+static const struct regval tw9900_init_regs[] = {</div><div class='add'>+	{ TW9900_REG_MISC_CTL_II,	0xE6 },</div><div class='add'>+	{ TW9900_REG_MISSCNT,		0x24 },</div><div class='add'>+	{ TW9900_REG_OUT_FMT_CTL,	0xA7 },</div><div class='add'>+	{ TW9900_REG_ANAL_CTL_II,	0x0A },</div><div class='add'>+	{ TW9900_REG_VDELAY_LO,		0x19 },</div><div class='add'>+	{ TW9900_REG_STD,		0x00 },</div><div class='add'>+	{ TW9900_REG_VACTIVE_LO,	0xF0 },</div><div class='add'>+	{ TW9900_REG_STD,		0x07 },</div><div class='add'>+	{ TW9900_REG_CKHY_HSDLY,	0x00 },</div><div class='add'>+	{ TW9900_REG_ANALOG_CTL,	0x80 },</div><div class='add'>+	{ TW9900_REG_CNTRL1,		0xDC },</div><div class='add'>+	{ TW9900_REG_OUT_CTRL_I,	0x98 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regval tw9900_pal_regs[] = {</div><div class='add'>+	{ TW9900_REG_STD,		0x01 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regval tw9900_ntsc_regs[] = {</div><div class='add'>+	{ TW9900_REG_OUT_FMT_CTL,	0xA4 },</div><div class='add'>+	{ TW9900_REG_VDELAY_LO,		0x12 },</div><div class='add'>+	{ TW9900_REG_VACTIVE_LO,	0xF0 },</div><div class='add'>+	{ TW9900_REG_CROP_HI,		0x02 },</div><div class='add'>+	{ TW9900_REG_HACTIVE_LO,	0xD0 },</div><div class='add'>+	{ TW9900_REG_VBI_CNTL,		0x01 },</div><div class='add'>+	{ TW9900_REG_STD,		0x00 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct tw9900_mode supported_modes[] = {</div><div class='add'>+	{</div><div class='add'>+		.width = 720,</div><div class='add'>+		.height = 480,</div><div class='add'>+		.std = V4L2_STD_NTSC,</div><div class='add'>+		.reg_list = tw9900_ntsc_regs,</div><div class='add'>+		.n_regs = ARRAY_SIZE(tw9900_ntsc_regs),</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.width = 720,</div><div class='add'>+		.height = 576,</div><div class='add'>+		.std = V4L2_STD_PAL,</div><div class='add'>+		.reg_list = tw9900_pal_regs,</div><div class='add'>+		.n_regs = ARRAY_SIZE(tw9900_pal_regs),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int tw9900_write_reg(struct i2c_client *client, u8 reg, u8 val)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_write_byte_data(client, reg, val);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "write reg error: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_write_array(struct i2c_client *client,</div><div class='add'>+			      const struct regval *regs, int n_regs)</div><div class='add'>+{</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; n_regs; i++) {</div><div class='add'>+		ret = tw9900_write_reg(client, regs[i].addr, regs[i].val);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_read_reg(struct i2c_client *client, u8 reg)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = i2c_smbus_read_byte_data(client, reg);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "read reg error: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tw9900_fill_fmt(const struct tw9900_mode *mode,</div><div class='add'>+			    struct v4l2_mbus_framefmt *fmt)</div><div class='add'>+{</div><div class='add'>+	fmt-&gt;code = MEDIA_BUS_FMT_UYVY8_2X8;</div><div class='add'>+	fmt-&gt;width = mode-&gt;width;</div><div class='add'>+	fmt-&gt;height = mode-&gt;height;</div><div class='add'>+	fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	fmt-&gt;quantization = V4L2_QUANTIZATION_DEFAULT;</div><div class='add'>+	fmt-&gt;colorspace = V4L2_COLORSPACE_SMPTE170M;</div><div class='add'>+	fmt-&gt;xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SMPTE170M);</div><div class='add'>+	fmt-&gt;ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SMPTE170M);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_get_fmt(struct v4l2_subdev *sd,</div><div class='add'>+			  struct v4l2_subdev_state *sd_state,</div><div class='add'>+			  struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mbus_fmt = &amp;fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	tw9900_fill_fmt(tw9900-&gt;cur_mode, mbus_fmt);</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_set_fmt(struct v4l2_subdev *sd,</div><div class='add'>+			  struct v4l2_subdev_state *sd_state,</div><div class='add'>+			  struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mbus_fmt = &amp;fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;streaming) {</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tw9900_fill_fmt(tw9900-&gt;cur_mode, mbus_fmt);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state,</div><div class='add'>+				 struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	if (code-&gt;index &gt; 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = MEDIA_BUS_FMT_UYVY8_2X8;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = container_of(ctrl-&gt;handler, struct tw9900, hdl);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (pm_runtime_suspended(&amp;tw9900-&gt;client-&gt;dev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* v4l2_ctrl_lock() locks tw9900-&gt;mutex. */</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_BRIGHTNESS:</div><div class='add'>+		ret = tw9900_write_reg(tw9900-&gt;client, TW9900_REG_BRIGHT_CTL,</div><div class='add'>+				       (u8)ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_CONTRAST:</div><div class='add'>+		ret = tw9900_write_reg(tw9900-&gt;client, TW9900_REG_CONTRAST_CTL,</div><div class='add'>+				       (u8)ctrl-&gt;val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_s_stream(struct v4l2_subdev *sd, int on)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	struct i2c_client *client = tw9900-&gt;client;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;streaming == on) {</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (on) {</div><div class='add'>+		ret = pm_runtime_resume_and_get(&amp;client-&gt;dev);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+		ret = __v4l2_ctrl_handler_setup(sd-&gt;ctrl_handler);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_unlock;</div><div class='add'>+</div><div class='add'>+		ret = tw9900_write_array(tw9900-&gt;client,</div><div class='add'>+					 tw9900-&gt;cur_mode-&gt;reg_list,</div><div class='add'>+					 tw9900-&gt;cur_mode-&gt;n_regs);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_unlock;</div><div class='add'>+</div><div class='add'>+		ret = tw9900_write_reg(client, TW9900_REG_OUT_FMT_CTL,</div><div class='add'>+				       TW9900_REG_OUT_FMT_CTL_STREAMING);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_unlock;</div><div class='add'>+</div><div class='add'>+		tw9900-&gt;streaming = on;</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+		ret = tw9900_write_reg(client, TW9900_REG_OUT_FMT_CTL,</div><div class='add'>+				       TW9900_REG_OUT_FMT_CTL_STANDBY);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_unlock;</div><div class='add'>+</div><div class='add'>+		tw9900-&gt;streaming = on;</div><div class='add'>+</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+		pm_runtime_put(&amp;client-&gt;dev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_unlock:</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	pm_runtime_put(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_subscribe_event(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_fh *fh,</div><div class='add'>+				  struct v4l2_event_subscription *sub)</div><div class='add'>+{</div><div class='add'>+	switch (sub-&gt;type) {</div><div class='add'>+	case V4L2_EVENT_SOURCE_CHANGE:</div><div class='add'>+		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);</div><div class='add'>+	case V4L2_EVENT_CTRL:</div><div class='add'>+		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_s_std(struct v4l2_subdev *sd, v4l2_std_id std)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	const struct tw9900_mode *mode = NULL;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!(std &amp; (V4L2_STD_NTSC | V4L2_STD_PAL)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(supported_modes); i++)</div><div class='add'>+		if (supported_modes[i].std &amp; std)</div><div class='add'>+			mode = &amp;supported_modes[i];</div><div class='add'>+	if (!mode)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	tw9900-&gt;cur_mode = mode;</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_get_stream_std(struct tw9900 *tw9900,</div><div class='add'>+				 v4l2_std_id *std)</div><div class='add'>+{</div><div class='add'>+	int cur_std, ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_read_reg(tw9900-&gt;client, TW9900_REG_STD);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		*std = V4L2_STD_UNKNOWN;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cur_std = FIELD_GET(TW9900_STDNOW_MASK, ret);</div><div class='add'>+	switch (cur_std) {</div><div class='add'>+	case TW9900_STD_NTSC_M:</div><div class='add'>+		*std = V4L2_STD_NTSC;</div><div class='add'>+		break;</div><div class='add'>+	case TW9900_STD_PAL_BDGHI:</div><div class='add'>+		*std = V4L2_STD_PAL;</div><div class='add'>+		break;</div><div class='add'>+	case TW9900_STD_AUTO:</div><div class='add'>+		*std = V4L2_STD_UNKNOWN;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		*std = V4L2_STD_UNKNOWN;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	*std = tw9900-&gt;cur_mode-&gt;std;</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_start_autodetect(struct tw9900 *tw9900)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_write_reg(tw9900-&gt;client, TW9900_REG_STDR,</div><div class='add'>+			       BIT(TW9900_STD_NTSC_M) |</div><div class='add'>+			       BIT(TW9900_STD_PAL_BDGHI));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = tw9900_write_reg(tw9900-&gt;client, TW9900_REG_STD,</div><div class='add'>+			       TW9900_STD_AUTO);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = tw9900_write_reg(tw9900-&gt;client, TW9900_REG_STDR,</div><div class='add'>+			       BIT(TW9900_STD_NTSC_M) |</div><div class='add'>+			       BIT(TW9900_STD_PAL_BDGHI) |</div><div class='add'>+			       BIT(TW9900_STD_AUTO));</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Autodetect takes a while to start, and during the starting sequence</div><div class='add'>+	 * the autodetection status is reported as done.</div><div class='add'>+	 */</div><div class='add'>+	msleep(30);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_detect_done(struct tw9900 *tw9900, bool *done)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_read_reg(tw9900-&gt;client, TW9900_REG_STD);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*done = !(ret &amp; TW9900_REG_STD_AUTO_PROGRESS);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	bool done = false;</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;streaming) {</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_start_autodetect(tw9900);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto out_unlock;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; TW9900_VIDEO_POLL_TRIES; i++) {</div><div class='add'>+		ret = tw9900_detect_done(tw9900, &amp;done);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto out_unlock;</div><div class='add'>+</div><div class='add'>+		if (done)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		msleep(20);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!done) {</div><div class='add'>+		ret = -ETIMEDOUT;</div><div class='add'>+		goto out_unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = tw9900_get_stream_std(tw9900, std);</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	pm_runtime_put(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *std)</div><div class='add'>+{</div><div class='add'>+	*std = V4L2_STD_NTSC | V4L2_STD_PAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_g_input_status(struct v4l2_subdev *sd, u32 *status)</div><div class='add'>+{</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;streaming) {</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	*status = V4L2_IN_ST_NO_SIGNAL;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	ret = tw9900_read_reg(tw9900-&gt;client, TW9900_REG_CHIP_STATUS);</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	*status = ret &amp; TW9900_REG_CHIP_STATUS_HLOCK ? 0 : V4L2_IN_ST_NO_SIGNAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_core_ops tw9900_core_ops = {</div><div class='add'>+	.subscribe_event	= tw9900_subscribe_event,</div><div class='add'>+	.unsubscribe_event	= v4l2_event_subdev_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops tw9900_video_ops = {</div><div class='add'>+	.s_std		= tw9900_s_std,</div><div class='add'>+	.g_std		= tw9900_g_std,</div><div class='add'>+	.querystd	= tw9900_querystd,</div><div class='add'>+	.g_tvnorms	= tw9900_g_tvnorms,</div><div class='add'>+	.g_input_status = tw9900_g_input_status,</div><div class='add'>+	.s_stream	= tw9900_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops tw9900_pad_ops = {</div><div class='add'>+	.enum_mbus_code	= tw9900_enum_mbus_code,</div><div class='add'>+	.get_fmt	= tw9900_get_fmt,</div><div class='add'>+	.set_fmt	= tw9900_set_fmt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops tw9900_subdev_ops = {</div><div class='add'>+	.core	= &amp;tw9900_core_ops,</div><div class='add'>+	.video	= &amp;tw9900_video_ops,</div><div class='add'>+	.pad	= &amp;tw9900_pad_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops tw9900_ctrl_ops = {</div><div class='add'>+	.s_ctrl	= tw9900_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int tw9900_check_id(struct tw9900 *tw9900,</div><div class='add'>+			   struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;tw9900-&gt;client-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+	ret = tw9900_read_reg(client, TW9900_CHIP_ID);</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(&amp;tw9900-&gt;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (ret != TW9900_CHIP_ID) {</div><div class='add'>+		dev_err(dev, "Unexpected decoder id %#x\n", ret);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_runtime_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = to_i2c_client(dev);</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;reset_gpio)</div><div class='add'>+		gpiod_set_value_cansleep(tw9900-&gt;reset_gpio, 1);</div><div class='add'>+</div><div class='add'>+	ret = regulator_enable(tw9900-&gt;regulator);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usleep_range(50000, 52000);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;reset_gpio)</div><div class='add'>+		gpiod_set_value_cansleep(tw9900-&gt;reset_gpio, 0);</div><div class='add'>+</div><div class='add'>+	usleep_range(1000, 2000);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_write_array(tw9900-&gt;client, tw9900_init_regs,</div><div class='add'>+				 ARRAY_SIZE(tw9900_init_regs));</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	/* This sleep is needed for the Horizontal Sync PLL to lock. */</div><div class='add'>+	msleep(300);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct i2c_client *client = to_i2c_client(dev);</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (tw9900-&gt;reset_gpio)</div><div class='add'>+		gpiod_set_value_cansleep(tw9900-&gt;reset_gpio, 1);</div><div class='add'>+</div><div class='add'>+	regulator_disable(tw9900-&gt;regulator);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int tw9900_probe(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;client-&gt;dev;</div><div class='add'>+	struct v4l2_ctrl_handler *hdl;</div><div class='add'>+	struct tw9900 *tw9900;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	tw9900 = devm_kzalloc(dev, sizeof(*tw9900), GFP_KERNEL);</div><div class='add'>+	if (!tw9900)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	tw9900-&gt;client = client;</div><div class='add'>+	tw9900-&gt;cur_mode = &amp;supported_modes[0];</div><div class='add'>+</div><div class='add'>+	tw9900-&gt;reset_gpio = devm_gpiod_get_optional(dev, "reset",</div><div class='add'>+						     GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(tw9900-&gt;reset_gpio))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(tw9900-&gt;reset_gpio),</div><div class='add'>+				     "Failed to get reset gpio\n");</div><div class='add'>+</div><div class='add'>+	tw9900-&gt;regulator = devm_regulator_get(&amp;tw9900-&gt;client-&gt;dev, "vdd");</div><div class='add'>+	if (IS_ERR(tw9900-&gt;regulator))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(tw9900-&gt;regulator),</div><div class='add'>+				     "Failed to get power regulator\n");</div><div class='add'>+</div><div class='add'>+	v4l2_i2c_subdev_init(&amp;tw9900-&gt;subdev, client, &amp;tw9900_subdev_ops);</div><div class='add'>+	tw9900-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='add'>+				V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	hdl = &amp;tw9900-&gt;hdl;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_ctrl_handler_init(hdl, 2);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_destory_mutex;</div><div class='add'>+</div><div class='add'>+	hdl-&gt;lock = &amp;tw9900-&gt;mutex;</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;tw9900_ctrl_ops, V4L2_CID_BRIGHTNESS,</div><div class='add'>+			  -128, 127, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(hdl, &amp;tw9900_ctrl_ops, V4L2_CID_CONTRAST,</div><div class='add'>+			  0, 255, 1, 0x60);</div><div class='add'>+</div><div class='add'>+	tw9900-&gt;subdev.ctrl_handler = hdl;</div><div class='add'>+	if (hdl-&gt;error) {</div><div class='add'>+		ret = hdl-&gt;error;</div><div class='add'>+		goto err_free_handler;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tw9900-&gt;pad.flags = MEDIA_PAD_FL_SOURCE;</div><div class='add'>+	tw9900-&gt;subdev.entity.function = MEDIA_ENT_F_DV_DECODER;</div><div class='add'>+</div><div class='add'>+	ret = media_entity_pads_init(&amp;tw9900-&gt;subdev.entity, 1, &amp;tw9900-&gt;pad);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err_free_handler;</div><div class='add'>+</div><div class='add'>+	pm_runtime_set_suspended(dev);</div><div class='add'>+	pm_runtime_enable(dev);</div><div class='add'>+</div><div class='add'>+	ret = tw9900_check_id(tw9900, client);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_disable_pm;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_register_subdev(&amp;tw9900-&gt;subdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "v4l2 async register subdev failed\n");</div><div class='add'>+		goto err_disable_pm;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_disable_pm:</div><div class='add'>+	pm_runtime_disable(dev);</div><div class='add'>+	media_entity_cleanup(&amp;tw9900-&gt;subdev.entity);</div><div class='add'>+err_free_handler:</div><div class='add'>+	v4l2_ctrl_handler_free(hdl);</div><div class='add'>+err_destory_mutex:</div><div class='add'>+	mutex_destroy(&amp;tw9900-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void tw9900_remove(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev *sd = i2c_get_clientdata(client);</div><div class='add'>+	struct tw9900 *tw9900 = to_tw9900(sd);</div><div class='add'>+</div><div class='add'>+	v4l2_async_unregister_subdev(sd);</div><div class='add'>+	media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='add'>+	v4l2_ctrl_handler_free(sd-&gt;ctrl_handler);</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(&amp;client-&gt;dev);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;tw9900-&gt;mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops tw9900_pm_ops = {</div><div class='add'>+	.runtime_suspend = tw9900_runtime_suspend,</div><div class='add'>+	.runtime_resume = tw9900_runtime_resume,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct i2c_device_id tw9900_id[] = {</div><div class='add'>+	{ "tw9900", 0 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(i2c, tw9900_id);</div><div class='add'>+</div><div class='add'>+static const struct of_device_id tw9900_of_match[] = {</div><div class='add'>+	{ .compatible = "techwell,tw9900" },</div><div class='add'>+	{},</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, tw9900_of_match);</div><div class='add'>+</div><div class='add'>+static struct i2c_driver tw9900_i2c_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name		= "tw9900",</div><div class='add'>+		.pm		= &amp;tw9900_pm_ops,</div><div class='add'>+		.of_match_table	= tw9900_of_match,</div><div class='add'>+	},</div><div class='add'>+	.probe	  = tw9900_probe,</div><div class='add'>+	.remove	  = tw9900_remove,</div><div class='add'>+	.id_table = tw9900_id,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_i2c_driver(tw9900_i2c_driver);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("tw9900 decoder driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/i2c/tw9910.c b/drivers/media/i2c/tw9910.c<br/>index 477a64d8f8ab..905af98c7d53 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/tw9910.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/tw9910.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/tw9910.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/tw9910.c</a></div><div class='hunk'>@@ -829,8 +829,6 @@ static int tw9910_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return tw9910_s_fmt(sd, mf);</div><div class='ctx'> </div><div class='del'>-	sd_state-&gt;pads-&gt;try_fmt = *mf;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/i2c/video-i2c.c b/drivers/media/i2c/video-i2c.c<br/>index 178bd06cc2ed..56dbe07a1c99 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/i2c/video-i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/i2c/video-i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/i2c/video-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/i2c/video-i2c.c</a></div><div class='hunk'>@@ -405,9 +405,10 @@ static int queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct video_i2c_data *data = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned int size = data-&gt;chip-&gt;buffer_size;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 2)</div><div class='add'>+		*nbuffers = 2 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes)</div><div class='ctx'> 		return sizes[0] &lt; size ? -EINVAL : 0;</div><div class='hunk'>@@ -794,7 +795,7 @@ static int video_i2c_probe(struct i2c_client *client)</div><div class='ctx'> 	queue-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	queue-&gt;drv_priv = data;</div><div class='ctx'> 	queue-&gt;buf_struct_size = sizeof(struct video_i2c_buffer);</div><div class='del'>-	queue-&gt;min_buffers_needed = 1;</div><div class='add'>+	queue-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	queue-&gt;ops = &amp;video_i2c_video_qops;</div><div class='ctx'> 	queue-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/mc/Kconfig b/drivers/media/mc/Kconfig<br/>index 375b09612981..c82b07d2ef36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/mc/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/mc/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/mc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/mc/Kconfig</a></div><div class='hunk'>@@ -11,10 +11,3 @@ config MEDIA_CONTROLLER_DVB</div><div class='ctx'> 	  Enable the media controller API support for DVB.</div><div class='ctx'> </div><div class='ctx'> 	  This is currently experimental.</div><div class='del'>-</div><div class='del'>-config MEDIA_CONTROLLER_REQUEST_API</div><div class='del'>-	bool</div><div class='del'>-	depends on MEDIA_CONTROLLER</div><div class='del'>-	help</div><div class='del'>-	  This option enables the Request API for the Media controller and V4L2</div><div class='del'>-	  interfaces. It is currently needed by a few stateless codec drivers.</div><div class='head'>diff --git a/drivers/media/mc/mc-device.c b/drivers/media/mc/mc-device.c<br/>index 8cee956e38d4..c0dd4ae57227 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/mc/mc-device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/mc/mc-device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/mc/mc-device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/mc/mc-device.c</a></div><div class='hunk'>@@ -372,16 +372,12 @@ static long media_device_get_topology(struct media_device *mdev, void *arg)</div><div class='ctx'> </div><div class='ctx'> static long media_device_request_alloc(struct media_device *mdev, void *arg)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	int *alloc_fd = arg;</div><div class='ctx'> </div><div class='ctx'> 	if (!mdev-&gt;ops || !mdev-&gt;ops-&gt;req_validate || !mdev-&gt;ops-&gt;req_queue)</div><div class='ctx'> 		return -ENOTTY;</div><div class='ctx'> </div><div class='ctx'> 	return media_request_alloc(mdev, alloc_fd);</div><div class='del'>-#else</div><div class='del'>-	return -ENOTTY;</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static long copy_arg_from_user(void *karg, void __user *uarg, unsigned int cmd)</div><div class='head'>diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c<br/>index 09a193bb87df..511f013cc338 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/bt8xx/bttv-driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/bt8xx/bttv-driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/bt8xx/bttv-driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/bt8xx/bttv-driver.c</a></div><div class='hunk'>@@ -1536,13 +1536,11 @@ static void buf_cleanup(struct vb2_buffer *vb)</div><div class='ctx'> </div><div class='ctx'> static int start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> {</div><div class='del'>-	int ret = 1;</div><div class='ctx'> 	int seqnr = 0;</div><div class='ctx'> 	struct bttv_buffer *buf;</div><div class='ctx'> 	struct bttv *btv = vb2_get_drv_priv(q);</div><div class='ctx'> </div><div class='del'>-	ret = check_alloc_btres_lock(btv, RESOURCE_VIDEO_STREAM);</div><div class='del'>-	if (ret == 0) {</div><div class='add'>+	if (!check_alloc_btres_lock(btv, RESOURCE_VIDEO_STREAM)) {</div><div class='ctx'> 		if (btv-&gt;field_count)</div><div class='ctx'> 			seqnr++;</div><div class='ctx'> 		while (!list_empty(&amp;btv-&gt;capture)) {</div><div class='hunk'>@@ -1553,7 +1551,7 @@ static int start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 			vb2_buffer_done(&amp;buf-&gt;vbuf.vb2_buf,</div><div class='ctx'> 					VB2_BUF_STATE_QUEUED);</div><div class='ctx'> 		}</div><div class='del'>-		return !ret;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!vb2_is_streaming(&amp;btv-&gt;vbiq)) {</div><div class='ctx'> 		init_irqreg(btv);</div><div class='hunk'>@@ -2774,6 +2772,27 @@ bttv_irq_wakeup_vbi(struct bttv *btv, struct bttv_buffer *wakeup,</div><div class='ctx'> 		return;</div><div class='ctx'> 	wakeup-&gt;vbuf.vb2_buf.timestamp = ktime_get_ns();</div><div class='ctx'> 	wakeup-&gt;vbuf.sequence = btv-&gt;field_count &gt;&gt; 1;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Ugly hack for backwards compatibility.</div><div class='add'>+	 * Some applications expect that the last 4 bytes of</div><div class='add'>+	 * the VBI data contains the sequence number.</div><div class='add'>+	 *</div><div class='add'>+	 * This makes it possible to associate the VBI data</div><div class='add'>+	 * with the video frame if you use read() to get the</div><div class='add'>+	 * VBI data.</div><div class='add'>+	 */</div><div class='add'>+	if (vb2_fileio_is_active(wakeup-&gt;vbuf.vb2_buf.vb2_queue)) {</div><div class='add'>+		u32 *vaddr = vb2_plane_vaddr(&amp;wakeup-&gt;vbuf.vb2_buf, 0);</div><div class='add'>+		unsigned long size =</div><div class='add'>+			vb2_get_plane_payload(&amp;wakeup-&gt;vbuf.vb2_buf, 0) / 4;</div><div class='add'>+</div><div class='add'>+		if (vaddr &amp;&amp; size) {</div><div class='add'>+			vaddr += size - 1;</div><div class='add'>+			*vaddr = wakeup-&gt;vbuf.sequence;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	vb2_buffer_done(&amp;wakeup-&gt;vbuf.vb2_buf, state);</div><div class='ctx'> 	if (btv-&gt;field_count == 0)</div><div class='ctx'> 		btor(BT848_INT_VSYNC, BT848_INT_MASK);</div><div class='hunk'>@@ -3094,7 +3113,7 @@ static int vdev_init(struct bttv *btv, struct video_device *vfd,</div><div class='ctx'> 	q-&gt;gfp_flags = __GFP_DMA32;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct bttv_buffer);</div><div class='ctx'> 	q-&gt;lock = &amp;btv-&gt;lock;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;dev = &amp;btv-&gt;c.pci-&gt;dev;</div><div class='ctx'> 	err = vb2_queue_init(q);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/media/pci/bt8xx/bttv-vbi.c b/drivers/media/pci/bt8xx/bttv-vbi.c<br/>index ab213e51ec95..e489a3acb4b9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/bt8xx/bttv-vbi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/bt8xx/bttv-vbi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/bt8xx/bttv-vbi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/bt8xx/bttv-vbi.c</a></div><div class='hunk'>@@ -123,14 +123,12 @@ static void buf_cleanup_vbi(struct vb2_buffer *vb)</div><div class='ctx'> </div><div class='ctx'> static int start_streaming_vbi(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='ctx'> 	int seqnr = 0;</div><div class='ctx'> 	struct bttv_buffer *buf;</div><div class='ctx'> 	struct bttv *btv = vb2_get_drv_priv(q);</div><div class='ctx'> </div><div class='ctx'> 	btv-&gt;framedrop = 0;</div><div class='del'>-	ret = check_alloc_btres_lock(btv, RESOURCE_VBI);</div><div class='del'>-	if (ret == 0) {</div><div class='add'>+	if (!check_alloc_btres_lock(btv, RESOURCE_VBI)) {</div><div class='ctx'> 		if (btv-&gt;field_count)</div><div class='ctx'> 			seqnr++;</div><div class='ctx'> 		while (!list_empty(&amp;btv-&gt;vcapture)) {</div><div class='hunk'>@@ -141,13 +139,13 @@ static int start_streaming_vbi(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 			vb2_buffer_done(&amp;buf-&gt;vbuf.vb2_buf,</div><div class='ctx'> 					VB2_BUF_STATE_QUEUED);</div><div class='ctx'> 		}</div><div class='del'>-		return !ret;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!vb2_is_streaming(&amp;btv-&gt;capq)) {</div><div class='ctx'> 		init_irqreg(btv);</div><div class='ctx'> 		btv-&gt;field_count = 0;</div><div class='ctx'> 	}</div><div class='del'>-	return !ret;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void stop_streaming_vbi(struct vb2_queue *q)</div><div class='head'>diff --git a/drivers/media/pci/cobalt/cobalt-v4l2.c b/drivers/media/pci/cobalt/cobalt-v4l2.c<br/>index 26bf58d17a3d..77ba08ace29f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cobalt/cobalt-v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cobalt/cobalt-v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cobalt/cobalt-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cobalt/cobalt-v4l2.c</a></div><div class='hunk'>@@ -1260,7 +1260,7 @@ static int cobalt_node_register(struct cobalt *cobalt, int node)</div><div class='ctx'> 	q-&gt;ops = &amp;cobalt_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_sg_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;lock = &amp;s-&gt;lock;</div><div class='ctx'> 	q-&gt;dev = &amp;cobalt-&gt;pci_dev-&gt;dev;</div><div class='ctx'> 	vdev-&gt;queue = q;</div><div class='head'>diff --git a/drivers/media/pci/cx18/cx18-streams.c b/drivers/media/pci/cx18/cx18-streams.c<br/>index 597472754c4c..acc6418db425 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx18/cx18-streams.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx18/cx18-streams.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx18/cx18-streams.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx18/cx18-streams.c</a></div><div class='hunk'>@@ -104,6 +104,7 @@ static int cx18_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 			    unsigned int *nbuffers, unsigned int *nplanes,</div><div class='ctx'> 			    unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	struct cx18_stream *s = vb2_get_drv_priv(vq);</div><div class='ctx'> 	struct cx18 *cx = s-&gt;cx;</div><div class='ctx'> 	unsigned int szimage;</div><div class='hunk'>@@ -121,8 +122,8 @@ static int cx18_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	 * Let's request at least three buffers: two for the</div><div class='ctx'> 	 * DMA engine and one for userspace.</div><div class='ctx'> 	 */</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (*nplanes != 1 || sizes[0] &lt; szimage)</div><div class='hunk'>@@ -286,7 +287,7 @@ static int cx18_stream_init(struct cx18 *cx, int type)</div><div class='ctx'> 		s-&gt;vidq.ops = &amp;cx18_vb2_qops;</div><div class='ctx'> 		s-&gt;vidq.mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 		s-&gt;vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-		s-&gt;vidq.min_buffers_needed = 2;</div><div class='add'>+		s-&gt;vidq.min_queued_buffers = 2;</div><div class='ctx'> 		s-&gt;vidq.gfp_flags = GFP_DMA32;</div><div class='ctx'> 		s-&gt;vidq.dev = &amp;cx-&gt;pci_dev-&gt;dev;</div><div class='ctx'> 		s-&gt;vidq.lock = &amp;cx-&gt;serialize_lock;</div><div class='head'>diff --git a/drivers/media/pci/cx23885/cx23885-417.c b/drivers/media/pci/cx23885/cx23885-417.c<br/>index 434677bd4ad1..fdb96f80c036 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-417.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx23885/cx23885-417.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-417.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-417.c</a></div><div class='hunk'>@@ -1525,7 +1525,7 @@ int cx23885_417_register(struct cx23885_dev *dev)</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx23885_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;cx23885_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c<br/>index 7551ca4a322a..3d01cdc4c7f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-dvb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx23885/cx23885-dvb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-dvb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-dvb.c</a></div><div class='hunk'>@@ -2667,7 +2667,7 @@ int cx23885_dvb_register(struct cx23885_tsport *port)</div><div class='ctx'> 		q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 		q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-		q-&gt;min_buffers_needed = 2;</div><div class='add'>+		q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 		q-&gt;drv_priv = port;</div><div class='ctx'> 		q-&gt;buf_struct_size = sizeof(struct cx23885_buffer);</div><div class='ctx'> 		q-&gt;ops = &amp;dvb_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx23885/cx23885-video.c b/drivers/media/pci/cx23885/cx23885-video.c<br/>index 9af2c5596121..42fdcf992e48 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx23885/cx23885-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx23885/cx23885-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx23885/cx23885-video.c</a></div><div class='hunk'>@@ -1321,7 +1321,7 @@ int cx23885_video_register(struct cx23885_dev *dev)</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx23885_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;cx23885_video_qops;</div><div class='hunk'>@@ -1338,7 +1338,7 @@ int cx23885_video_register(struct cx23885_dev *dev)</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VBI_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx23885_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;cx23885_vbi_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx25821/cx25821-video.c b/drivers/media/pci/cx25821/cx25821-video.c<br/>index 1b80c990cb94..0bee4b728a60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx25821/cx25821-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx25821/cx25821-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx25821/cx25821-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx25821/cx25821-video.c</a></div><div class='hunk'>@@ -730,7 +730,7 @@ int cx25821_video_register(struct cx25821_dev *dev)</div><div class='ctx'> 		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;</div><div class='ctx'> 		q-&gt;io_modes |= is_output ? VB2_WRITE : VB2_READ;</div><div class='ctx'> 		q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-		q-&gt;min_buffers_needed = 2;</div><div class='add'>+		q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 		q-&gt;drv_priv = chan;</div><div class='ctx'> 		q-&gt;buf_struct_size = sizeof(struct cx25821_buffer);</div><div class='ctx'> 		q-&gt;ops = &amp;cx25821_video_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx88/cx88-blackbird.c b/drivers/media/pci/cx88/cx88-blackbird.c<br/>index c1b41a9283c1..d55df8fdb3b6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-blackbird.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx88/cx88-blackbird.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-blackbird.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-blackbird.c</a></div><div class='hunk'>@@ -1195,7 +1195,7 @@ static int cx8802_blackbird_probe(struct cx8802_driver *drv)</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx88_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;blackbird_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx88/cx88-dvb.c b/drivers/media/pci/cx88/cx88-dvb.c<br/>index 2087f2491c42..b33b3a5e32ec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-dvb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx88/cx88-dvb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-dvb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-dvb.c</a></div><div class='hunk'>@@ -1776,7 +1776,7 @@ static int cx8802_dvb_probe(struct cx8802_driver *drv)</div><div class='ctx'> 		q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 		q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-		q-&gt;min_buffers_needed = 2;</div><div class='add'>+		q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 		q-&gt;drv_priv = dev;</div><div class='ctx'> 		q-&gt;buf_struct_size = sizeof(struct cx88_buffer);</div><div class='ctx'> 		q-&gt;ops = &amp;dvb_qops;</div><div class='head'>diff --git a/drivers/media/pci/cx88/cx88-video.c b/drivers/media/pci/cx88/cx88-video.c<br/>index c0ef03ed74f9..cefb6b25e921 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/cx88/cx88-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/cx88/cx88-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/cx88/cx88-video.c</a></div><div class='hunk'>@@ -1411,7 +1411,7 @@ static int cx8800_initdev(struct pci_dev *pci_dev,</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx88_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;cx8800_video_qops;</div><div class='hunk'>@@ -1428,7 +1428,7 @@ static int cx8800_initdev(struct pci_dev *pci_dev,</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VBI_CAPTURE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;</div><div class='ctx'> 	q-&gt;gfp_flags = GFP_DMA32;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct cx88_buffer);</div><div class='ctx'> 	q-&gt;ops = &amp;cx8800_vbi_qops;</div><div class='head'>diff --git a/drivers/media/pci/ddbridge/ddbridge-main.c b/drivers/media/pci/ddbridge/ddbridge-main.c<br/>index 91733ab9f58c..363badab7cf0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/ddbridge/ddbridge-main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/ddbridge/ddbridge-main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/ddbridge/ddbridge-main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ddbridge/ddbridge-main.c</a></div><div class='hunk'>@@ -238,7 +238,7 @@ fail:</div><div class='ctx'> 	ddb_unmap(dev);</div><div class='ctx'> 	pci_set_drvdata(pdev, NULL);</div><div class='ctx'> 	pci_disable_device(pdev);</div><div class='del'>-	return -1;</div><div class='add'>+	return stat;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /****************************************************************************/</div><div class='head'>diff --git a/drivers/media/pci/dt3155/dt3155.c b/drivers/media/pci/dt3155/dt3155.c<br/>index 548156b199cc..dff853e73fdc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/dt3155/dt3155.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/dt3155/dt3155.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/dt3155/dt3155.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/dt3155/dt3155.c</a></div><div class='hunk'>@@ -128,8 +128,6 @@ dt3155_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	struct dt3155_priv *pd = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned size = pd-&gt;width * pd-&gt;height;</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='ctx'> 	if (*num_planes)</div><div class='ctx'> 		return sizes[0] &lt; size ? -EINVAL : 0;</div><div class='ctx'> 	*num_planes = 1;</div><div class='hunk'>@@ -519,7 +517,7 @@ static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)</div><div class='ctx'> 	pd-&gt;vidq.ops = &amp;q_ops;</div><div class='ctx'> 	pd-&gt;vidq.mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	pd-&gt;vidq.drv_priv = pd;</div><div class='del'>-	pd-&gt;vidq.min_buffers_needed = 2;</div><div class='add'>+	pd-&gt;vidq.min_queued_buffers = 2;</div><div class='ctx'> 	pd-&gt;vidq.gfp_flags = GFP_DMA32;</div><div class='ctx'> 	pd-&gt;vidq.lock = &amp;pd-&gt;mux; /* for locking v4l2_file_operations */</div><div class='ctx'> 	pd-&gt;vidq.dev = &amp;pdev-&gt;dev;</div><div class='head'>diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel/ipu-bridge.c<br/>index e38198e259c0..f980e3125a7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ipu-bridge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/intel/ipu-bridge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ipu-bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ipu-bridge.c</a></div><div class='hunk'>@@ -53,7 +53,7 @@ static const struct ipu_sensor_config ipu_supported_sensors[] = {</div><div class='ctx'> 	/* Omnivision ov8856 */</div><div class='ctx'> 	IPU_SENSOR_CONFIG("OVTI8856", 3, 180000000, 360000000, 720000000),</div><div class='ctx'> 	/* Omnivision ov2740 */</div><div class='del'>-	IPU_SENSOR_CONFIG("INT3474", 1, 360000000),</div><div class='add'>+	IPU_SENSOR_CONFIG("INT3474", 1, 180000000),</div><div class='ctx'> 	/* Hynix hi556 */</div><div class='ctx'> 	IPU_SENSOR_CONFIG("INT3537", 1, 437000000),</div><div class='ctx'> 	/* Omnivision ov13b10 */</div><div class='head'>diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2.c<br/>index 5dd69a251b6a..ed08bf4178f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ipu3/ipu3-cio2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/intel/ipu3/ipu3-cio2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ipu3/ipu3-cio2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ipu3/ipu3-cio2.c</a></div><div class='hunk'>@@ -1205,23 +1205,16 @@ static int cio2_subdev_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize try_fmt */</div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, fh-&gt;state, CIO2_PAD_SINK);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state, CIO2_PAD_SINK);</div><div class='ctx'> 	*format = fmt_default;</div><div class='ctx'> </div><div class='ctx'> 	/* same as sink */</div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, fh-&gt;state, CIO2_PAD_SOURCE);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state, CIO2_PAD_SOURCE);</div><div class='ctx'> 	*format = fmt_default;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * cio2_subdev_get_fmt - Handle get format by pads subdev method</div><div class='del'>- * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad config</div><div class='del'>- * @fmt: pointer to v4l2 subdev format structure</div><div class='del'>- * return -EINVAL or zero on success</div><div class='del'>- */</div><div class='ctx'> static int cio2_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 			       struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 			       struct v4l2_subdev_format *fmt)</div><div class='hunk'>@@ -1231,8 +1224,8 @@ static int cio2_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;q-&gt;subdev_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		fmt-&gt;format = q-&gt;subdev_fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -1241,13 +1234,6 @@ static int cio2_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * cio2_subdev_set_fmt - Handle set format by pads subdev method</div><div class='del'>- * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad config</div><div class='del'>- * @fmt: pointer to v4l2 subdev format structure</div><div class='del'>- * return -EINVAL or zero on success</div><div class='del'>- */</div><div class='ctx'> static int cio2_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 			       struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 			       struct v4l2_subdev_format *fmt)</div><div class='hunk'>@@ -1265,7 +1251,7 @@ static int cio2_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		return cio2_subdev_get_fmt(sd, sd_state, fmt);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		mbus = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mbus = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		mbus = &amp;q-&gt;subdev_fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -1603,7 +1589,7 @@ static int cio2_queue_init(struct cio2_device *cio2, struct cio2_queue *q)</div><div class='ctx'> 	vbq-&gt;mem_ops = &amp;vb2_dma_sg_memops;</div><div class='ctx'> 	vbq-&gt;buf_struct_size = sizeof(struct cio2_buffer);</div><div class='ctx'> 	vbq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	vbq-&gt;min_buffers_needed = 1;</div><div class='add'>+	vbq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	vbq-&gt;drv_priv = cio2;</div><div class='ctx'> 	vbq-&gt;lock = &amp;q-&gt;lock;</div><div class='ctx'> 	r = vb2_queue_init(vbq);</div><div class='head'>diff --git a/drivers/media/pci/intel/ivsc/mei_csi.c b/drivers/media/pci/intel/ivsc/mei_csi.c<br/>index 2a6b828fd8dd..15b905f66ab7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ivsc/mei_csi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/intel/ivsc/mei_csi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/intel/ivsc/mei_csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/intel/ivsc/mei_csi.c</a></div><div class='hunk'>@@ -338,7 +338,7 @@ mei_csi_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;csi-&gt;format_mbus[pad];</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -346,8 +346,8 @@ mei_csi_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mei_csi_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mei_csi_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbusformat;</div><div class='ctx'> 	struct mei_csi *csi = sd_to_csi(sd);</div><div class='hunk'>@@ -356,7 +356,7 @@ static int mei_csi_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;csi-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='del'>-		mbusformat = v4l2_subdev_get_try_format(sd, sd_state, i);</div><div class='add'>+		mbusformat = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*mbusformat = mei_csi_format_mbus_default;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -554,7 +554,6 @@ static const struct v4l2_subdev_video_ops mei_csi_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mei_csi_pad_ops = {</div><div class='del'>-	.init_cfg = mei_csi_init_cfg,</div><div class='ctx'> 	.get_fmt = mei_csi_get_fmt,</div><div class='ctx'> 	.set_fmt = mei_csi_set_fmt,</div><div class='ctx'> };</div><div class='hunk'>@@ -564,6 +563,10 @@ static const struct v4l2_subdev_ops mei_csi_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;mei_csi_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mei_csi_internal_ops = {</div><div class='add'>+	.init_state = mei_csi_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations mei_csi_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -645,47 +648,66 @@ static int mei_csi_parse_firmware(struct mei_csi *csi)</div><div class='ctx'> 	};</div><div class='ctx'> 	struct device *dev = &amp;csi-&gt;cldev-&gt;dev;</div><div class='ctx'> 	struct v4l2_async_connection *asd;</div><div class='del'>-	struct fwnode_handle *fwnode;</div><div class='del'>-	struct fwnode_handle *ep;</div><div class='add'>+	struct fwnode_handle *sink_ep, *source_ep;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);</div><div class='del'>-	if (!ep) {</div><div class='del'>-		dev_err(dev, "not connected to subdevice\n");</div><div class='add'>+	sink_ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0);</div><div class='add'>+	if (!sink_ep) {</div><div class='add'>+		dev_err(dev, "can't obtain sink endpoint\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_fwnode_endpoint_parse(ep, &amp;v4l2_ep);</div><div class='add'>+	v4l2_async_subdev_nf_init(&amp;csi-&gt;notifier, &amp;csi-&gt;subdev);</div><div class='add'>+	csi-&gt;notifier.ops = &amp;mei_csi_notify_ops;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_fwnode_endpoint_parse(sink_ep, &amp;v4l2_ep);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_err(dev, "could not parse v4l2 endpoint\n");</div><div class='del'>-		fwnode_handle_put(ep);</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		dev_err(dev, "could not parse v4l2 sink endpoint\n");</div><div class='add'>+		goto out_nf_cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fwnode = fwnode_graph_get_remote_endpoint(ep);</div><div class='del'>-	fwnode_handle_put(ep);</div><div class='add'>+	csi-&gt;nr_of_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;</div><div class='ctx'> </div><div class='del'>-	v4l2_async_subdev_nf_init(&amp;csi-&gt;notifier, &amp;csi-&gt;subdev);</div><div class='del'>-	csi-&gt;notifier.ops = &amp;mei_csi_notify_ops;</div><div class='add'>+	source_ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 1, 0, 0);</div><div class='add'>+	if (!source_ep) {</div><div class='add'>+		ret = -ENOTCONN;</div><div class='add'>+		dev_err(dev, "can't obtain source endpoint\n");</div><div class='add'>+		goto out_nf_cleanup;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	asd = v4l2_async_nf_add_fwnode(&amp;csi-&gt;notifier, fwnode,</div><div class='del'>-				       struct v4l2_async_connection);</div><div class='del'>-	if (IS_ERR(asd)) {</div><div class='del'>-		fwnode_handle_put(fwnode);</div><div class='del'>-		return PTR_ERR(asd);</div><div class='add'>+	ret = v4l2_fwnode_endpoint_parse(source_ep, &amp;v4l2_ep);</div><div class='add'>+	fwnode_handle_put(source_ep);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "could not parse v4l2 source endpoint\n");</div><div class='add'>+		goto out_nf_cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = v4l2_fwnode_endpoint_alloc_parse(fwnode, &amp;v4l2_ep);</div><div class='del'>-	fwnode_handle_put(fwnode);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-	csi-&gt;nr_of_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;</div><div class='add'>+	if (csi-&gt;nr_of_lanes != v4l2_ep.bus.mipi_csi2.num_data_lanes) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		dev_err(dev,</div><div class='add'>+			"the number of lanes does not match (%u vs. %u)\n",</div><div class='add'>+			csi-&gt;nr_of_lanes, v4l2_ep.bus.mipi_csi2.num_data_lanes);</div><div class='add'>+		goto out_nf_cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	asd = v4l2_async_nf_add_fwnode_remote(&amp;csi-&gt;notifier, sink_ep,</div><div class='add'>+					      struct v4l2_async_connection);</div><div class='add'>+	if (IS_ERR(asd)) {</div><div class='add'>+		ret = PTR_ERR(asd);</div><div class='add'>+		goto out_nf_cleanup;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_async_nf_register(&amp;csi-&gt;notifier);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		v4l2_async_nf_cleanup(&amp;csi-&gt;notifier);</div><div class='add'>+		goto out_nf_cleanup;</div><div class='add'>+</div><div class='add'>+	fwnode_handle_put(sink_ep);</div><div class='ctx'> </div><div class='del'>-	v4l2_fwnode_endpoint_free(&amp;v4l2_ep);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+out_nf_cleanup:</div><div class='add'>+	v4l2_async_nf_cleanup(&amp;csi-&gt;notifier);</div><div class='add'>+	fwnode_handle_put(sink_ep);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -728,6 +750,7 @@ static int mei_csi_probe(struct mei_cl_device *cldev,</div><div class='ctx'> </div><div class='ctx'> 	csi-&gt;subdev.dev = &amp;cldev-&gt;dev;</div><div class='ctx'> 	v4l2_subdev_init(&amp;csi-&gt;subdev, &amp;mei_csi_subdev_ops);</div><div class='add'>+	csi-&gt;subdev.internal_ops = &amp;mei_csi_internal_ops;</div><div class='ctx'> 	v4l2_set_subdevdata(&amp;csi-&gt;subdev, csi);</div><div class='ctx'> 	csi-&gt;subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE |</div><div class='ctx'> 			    V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='head'>diff --git a/drivers/media/pci/ivtv/ivtv-driver.h b/drivers/media/pci/ivtv/ivtv-driver.h<br/>index ce3a7ca51736..a6ffa99e16bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/ivtv/ivtv-driver.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/ivtv/ivtv-driver.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/ivtv/ivtv-driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ivtv/ivtv-driver.h</a></div><div class='hunk'>@@ -619,6 +619,7 @@ struct ivtv {</div><div class='ctx'> 	u32 hw_flags;			/* hardware description of the board */</div><div class='ctx'> 	v4l2_std_id tuner_std;		/* the norm of the card's tuner (fixed) */</div><div class='ctx'> 	struct v4l2_subdev *sd_video;	/* controlling video decoder subdev */</div><div class='add'>+	bool sd_video_is_streaming;	/* is video already streaming? */</div><div class='ctx'> 	struct v4l2_subdev *sd_audio;	/* controlling audio subdev */</div><div class='ctx'> 	struct v4l2_subdev *sd_muxer;	/* controlling audio muxer subdev */</div><div class='ctx'> 	resource_size_t base_addr;      /* PCI resource base address */</div><div class='head'>diff --git a/drivers/media/pci/ivtv/ivtv-streams.c b/drivers/media/pci/ivtv/ivtv-streams.c<br/>index 13d7d55e6594..af9e6235c74d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/ivtv/ivtv-streams.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/ivtv/ivtv-streams.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/ivtv/ivtv-streams.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/ivtv/ivtv-streams.c</a></div><div class='hunk'>@@ -623,10 +623,12 @@ int ivtv_start_v4l2_encode_stream(struct ivtv_stream *s)</div><div class='ctx'> 		/* Avoid tinny audio problem - ensure audio clocks are going */</div><div class='ctx'> 		v4l2_subdev_call(itv-&gt;sd_audio, audio, s_stream, 1);</div><div class='ctx'> 		/* Avoid unpredictable PCI bus hang - disable video clocks */</div><div class='del'>-		v4l2_subdev_call(itv-&gt;sd_video, video, s_stream, 0);</div><div class='add'>+		if (itv-&gt;sd_video_is_streaming)</div><div class='add'>+			v4l2_subdev_call(itv-&gt;sd_video, video, s_stream, 0);</div><div class='ctx'> 		ivtv_msleep_timeout(300, 0);</div><div class='ctx'> 		ivtv_vapi(itv, CX2341X_ENC_INITIALIZE_INPUT, 0);</div><div class='ctx'> 		v4l2_subdev_call(itv-&gt;sd_video, video, s_stream, 1);</div><div class='add'>+		itv-&gt;sd_video_is_streaming = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* begin_capture */</div><div class='head'>diff --git a/drivers/media/pci/mgb4/Kconfig b/drivers/media/pci/mgb4/Kconfig<br/>index 13fad15a434c..f2a05a1c8ffa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/mgb4/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/Kconfig</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> config VIDEO_MGB4</div><div class='ctx'> 	tristate "Digiteq Automotive MGB4 support"</div><div class='ctx'> 	depends on VIDEO_DEV &amp;&amp; PCI &amp;&amp; I2C &amp;&amp; DMADEVICES &amp;&amp; SPI &amp;&amp; MTD &amp;&amp; IIO</div><div class='add'>+	depends on COMMON_CLK</div><div class='ctx'> 	select VIDEOBUF2_DMA_SG</div><div class='ctx'> 	select IIO_BUFFER</div><div class='ctx'> 	select IIO_TRIGGERED_BUFFER</div><div class='head'>diff --git a/drivers/media/pci/mgb4/mgb4_core.c b/drivers/media/pci/mgb4/mgb4_core.c<br/>index 3efb33fbf40c..5bfb8a06202e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/mgb4/mgb4_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_core.c</a></div><div class='hunk'>@@ -42,6 +42,10 @@</div><div class='ctx'> </div><div class='ctx'> #define MGB4_USER_IRQS 16</div><div class='ctx'> </div><div class='add'>+#define DIGITEQ_VID 0x1ed8</div><div class='add'>+#define T100_DID    0x0101</div><div class='add'>+#define T200_DID    0x0201</div><div class='add'>+</div><div class='ctx'> ATTRIBUTE_GROUPS(mgb4_pci);</div><div class='ctx'> </div><div class='ctx'> static int flashid;</div><div class='hunk'>@@ -151,7 +155,7 @@ static struct spi_master *get_spi_adap(struct platform_device *pdev)</div><div class='ctx'> 	return dev ? container_of(dev, struct spi_master, dev) : NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int init_spi(struct mgb4_dev *mgbdev)</div><div class='add'>+static int init_spi(struct mgb4_dev *mgbdev, u32 devid)</div><div class='ctx'> {</div><div class='ctx'> 	struct resource spi_resources[] = {</div><div class='ctx'> 		{</div><div class='hunk'>@@ -213,8 +217,13 @@ static int init_spi(struct mgb4_dev *mgbdev)</div><div class='ctx'> 	snprintf(mgbdev-&gt;fw_part_name, sizeof(mgbdev-&gt;fw_part_name),</div><div class='ctx'> 		 "mgb4-fw.%d", flashid);</div><div class='ctx'> 	mgbdev-&gt;partitions[0].name = mgbdev-&gt;fw_part_name;</div><div class='del'>-	mgbdev-&gt;partitions[0].size = 0x400000;</div><div class='del'>-	mgbdev-&gt;partitions[0].offset = 0x400000;</div><div class='add'>+	if (devid == T200_DID) {</div><div class='add'>+		mgbdev-&gt;partitions[0].size = 0x950000;</div><div class='add'>+		mgbdev-&gt;partitions[0].offset = 0x1000000;</div><div class='add'>+	} else {</div><div class='add'>+		mgbdev-&gt;partitions[0].size = 0x400000;</div><div class='add'>+		mgbdev-&gt;partitions[0].offset = 0x400000;</div><div class='add'>+	}</div><div class='ctx'> 	mgbdev-&gt;partitions[0].mask_flags = 0;</div><div class='ctx'> </div><div class='ctx'> 	snprintf(mgbdev-&gt;data_part_name, sizeof(mgbdev-&gt;data_part_name),</div><div class='hunk'>@@ -551,7 +560,7 @@ static int mgb4_probe(struct pci_dev *pdev, const struct pci_device_id *id)</div><div class='ctx'> 		goto err_video_regs;</div><div class='ctx'> </div><div class='ctx'> 	/* SPI FLASH */</div><div class='del'>-	rv = init_spi(mgbdev);</div><div class='add'>+	rv = init_spi(mgbdev, id-&gt;device);</div><div class='ctx'> 	if (rv &lt; 0)</div><div class='ctx'> 		goto err_cmt_regs;</div><div class='ctx'> </div><div class='hunk'>@@ -666,7 +675,8 @@ static void mgb4_remove(struct pci_dev *pdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id mgb4_pci_ids[] = {</div><div class='del'>-	{ PCI_DEVICE(0x1ed8, 0x0101), },</div><div class='add'>+	{ PCI_DEVICE(DIGITEQ_VID, T100_DID), },</div><div class='add'>+	{ PCI_DEVICE(DIGITEQ_VID, T200_DID), },</div><div class='ctx'> 	{ 0, }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(pci, mgb4_pci_ids);</div><div class='head'>diff --git a/drivers/media/pci/mgb4/mgb4_vin.c b/drivers/media/pci/mgb4/mgb4_vin.c<br/>index d72b07b87cd1..2cd78c539889 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_vin.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/mgb4/mgb4_vin.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_vin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_vin.c</a></div><div class='hunk'>@@ -849,7 +849,7 @@ struct mgb4_vin_dev *mgb4_vin_create(struct mgb4_dev *mgbdev, int id)</div><div class='ctx'> 	vindev-&gt;queue.mem_ops = &amp;vb2_dma_sg_memops;</div><div class='ctx'> 	vindev-&gt;queue.gfp_flags = GFP_DMA32;</div><div class='ctx'> 	vindev-&gt;queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	vindev-&gt;queue.min_buffers_needed = 2;</div><div class='add'>+	vindev-&gt;queue.min_queued_buffers = 2;</div><div class='ctx'> 	vindev-&gt;queue.drv_priv = vindev;</div><div class='ctx'> 	vindev-&gt;queue.lock = &amp;vindev-&gt;lock;</div><div class='ctx'> 	vindev-&gt;queue.dev = dev;</div><div class='head'>diff --git a/drivers/media/pci/mgb4/mgb4_vout.c b/drivers/media/pci/mgb4/mgb4_vout.c<br/>index 857fc7bbd21a..241353ee77a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_vout.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/mgb4/mgb4_vout.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/mgb4/mgb4_vout.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/mgb4/mgb4_vout.c</a></div><div class='hunk'>@@ -523,7 +523,7 @@ struct mgb4_vout_dev *mgb4_vout_create(struct mgb4_dev *mgbdev, int id)</div><div class='ctx'> 	voutdev-&gt;queue.mem_ops = &amp;vb2_dma_sg_memops;</div><div class='ctx'> 	voutdev-&gt;queue.gfp_flags = GFP_DMA32;</div><div class='ctx'> 	voutdev-&gt;queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	voutdev-&gt;queue.min_buffers_needed = 2;</div><div class='add'>+	voutdev-&gt;queue.min_queued_buffers = 2;</div><div class='ctx'> 	voutdev-&gt;queue.drv_priv = voutdev;</div><div class='ctx'> 	voutdev-&gt;queue.lock = &amp;voutdev-&gt;lock;</div><div class='ctx'> 	voutdev-&gt;queue.dev = dev;</div><div class='head'>diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c<br/>index d85bfbb77a25..557985ba25db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/netup_unidvb/netup_unidvb_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/netup_unidvb/netup_unidvb_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/netup_unidvb/netup_unidvb_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/netup_unidvb/netup_unidvb_core.c</a></div><div class='hunk'>@@ -293,12 +293,13 @@ static int netup_unidvb_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 				    struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct netup_dma *dma = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;dma-&gt;ndev-&gt;pci_dev-&gt;dev, "%s()\n", __func__);</div><div class='ctx'> </div><div class='ctx'> 	*nplanes = 1;</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; VIDEO_MAX_FRAME)</div><div class='del'>-		*nbuffers = VIDEO_MAX_FRAME - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; VIDEO_MAX_FRAME)</div><div class='add'>+		*nbuffers = VIDEO_MAX_FRAME - q_num_bufs;</div><div class='ctx'> 	sizes[0] = PAGE_ALIGN(NETUP_DMA_PACKETS_COUNT * 188);</div><div class='ctx'> 	dev_dbg(&amp;dma-&gt;ndev-&gt;pci_dev-&gt;dev, "%s() nbuffers=%d sizes[0]=%d\n",</div><div class='ctx'> 		__func__, *nbuffers, sizes[0]);</div><div class='head'>diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c b/drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c<br/>index bd38ce444232..46676f2c89c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c</a></div><div class='hunk'>@@ -289,7 +289,7 @@ static const struct i2c_algorithm netup_i2c_algorithm = {</div><div class='ctx'> static const struct i2c_adapter netup_i2c_adapter = {</div><div class='ctx'> 	.owner		= THIS_MODULE,</div><div class='ctx'> 	.name		= NETUP_UNIDVB_NAME,</div><div class='del'>-	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,</div><div class='add'>+	.class		= I2C_CLASS_HWMON,</div><div class='ctx'> 	.algo		= &amp;netup_i2c_algorithm,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/pci/solo6x10/solo6x10-offsets.h b/drivers/media/pci/solo6x10/solo6x10-offsets.h<br/>index f414ee1316f2..fdbb817e6360 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/solo6x10/solo6x10-offsets.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/solo6x10/solo6x10-offsets.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/solo6x10/solo6x10-offsets.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/solo6x10/solo6x10-offsets.h</a></div><div class='hunk'>@@ -57,16 +57,16 @@</div><div class='ctx'> #define SOLO_MP4E_EXT_ADDR(__solo) \</div><div class='ctx'> 	(SOLO_EREF_EXT_ADDR(__solo) + SOLO_EREF_EXT_AREA(__solo))</div><div class='ctx'> #define SOLO_MP4E_EXT_SIZE(__solo) \</div><div class='del'>-	max((__solo-&gt;nr_chans * 0x00080000),				\</div><div class='del'>-	    min(((__solo-&gt;sdram_size - SOLO_MP4E_EXT_ADDR(__solo)) -	\</div><div class='del'>-		 __SOLO_JPEG_MIN_SIZE(__solo)), 0x00ff0000))</div><div class='add'>+	clamp(__solo-&gt;sdram_size - SOLO_MP4E_EXT_ADDR(__solo) -	\</div><div class='add'>+	      __SOLO_JPEG_MIN_SIZE(__solo),			\</div><div class='add'>+	      __solo-&gt;nr_chans * 0x00080000, 0x00ff0000)</div><div class='ctx'> </div><div class='ctx'> #define __SOLO_JPEG_MIN_SIZE(__solo)		(__solo-&gt;nr_chans * 0x00080000)</div><div class='ctx'> #define SOLO_JPEG_EXT_ADDR(__solo) \</div><div class='ctx'> 		(SOLO_MP4E_EXT_ADDR(__solo) + SOLO_MP4E_EXT_SIZE(__solo))</div><div class='ctx'> #define SOLO_JPEG_EXT_SIZE(__solo) \</div><div class='del'>-	max(__SOLO_JPEG_MIN_SIZE(__solo),				\</div><div class='del'>-	    min((__solo-&gt;sdram_size - SOLO_JPEG_EXT_ADDR(__solo)), 0x00ff0000))</div><div class='add'>+	clamp(__solo-&gt;sdram_size - SOLO_JPEG_EXT_ADDR(__solo),	\</div><div class='add'>+	      __SOLO_JPEG_MIN_SIZE(__solo), 0x00ff0000)</div><div class='ctx'> </div><div class='ctx'> #define SOLO_SDRAM_END(__solo) \</div><div class='ctx'> 	(SOLO_JPEG_EXT_ADDR(__solo) + SOLO_JPEG_EXT_SIZE(__solo))</div><div class='head'>diff --git a/drivers/media/pci/tw5864/tw5864-video.c b/drivers/media/pci/tw5864/tw5864-video.c<br/>index 197ed8978102..8b1aae4b6319 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/tw5864/tw5864-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/tw5864/tw5864-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/tw5864/tw5864-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw5864/tw5864-video.c</a></div><div class='hunk'>@@ -1114,7 +1114,7 @@ static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)</div><div class='ctx'> 	input-&gt;vidq.gfp_flags = 0;</div><div class='ctx'> 	input-&gt;vidq.buf_struct_size = sizeof(struct tw5864_buf);</div><div class='ctx'> 	input-&gt;vidq.lock = &amp;input-&gt;lock;</div><div class='del'>-	input-&gt;vidq.min_buffers_needed = 2;</div><div class='add'>+	input-&gt;vidq.min_queued_buffers = 2;</div><div class='ctx'> 	input-&gt;vidq.dev = &amp;input-&gt;root-&gt;pci-&gt;dev;</div><div class='ctx'> 	ret = vb2_queue_init(&amp;input-&gt;vidq);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/pci/tw68/tw68-video.c b/drivers/media/pci/tw68/tw68-video.c<br/>index 773a18702d36..cdf5d733b863 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/tw68/tw68-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/tw68/tw68-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/tw68/tw68-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw68/tw68-video.c</a></div><div class='hunk'>@@ -360,13 +360,14 @@ static int tw68_queue_setup(struct vb2_queue *q,</div><div class='ctx'> 			   unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct tw68_dev *dev = vb2_get_drv_priv(q);</div><div class='del'>-	unsigned tot_bufs = q-&gt;num_buffers + *num_buffers;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(q);</div><div class='add'>+	unsigned int tot_bufs = q_num_bufs + *num_buffers;</div><div class='ctx'> 	unsigned size = (dev-&gt;fmt-&gt;depth * dev-&gt;width * dev-&gt;height) &gt;&gt; 3;</div><div class='ctx'> </div><div class='ctx'> 	if (tot_bufs &lt; 2)</div><div class='ctx'> 		tot_bufs = 2;</div><div class='ctx'> 	tot_bufs = tw68_buffer_count(size, tot_bufs);</div><div class='del'>-	*num_buffers = tot_bufs - q-&gt;num_buffers;</div><div class='add'>+	*num_buffers = tot_bufs - q_num_bufs;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We allow create_bufs, but only if the sizeimage is &gt;= as the</div><div class='ctx'> 	 * current sizeimage. The tw68_buffer_count calculation becomes quite</div><div class='hunk'>@@ -951,7 +952,7 @@ int tw68_video_init2(struct tw68_dev *dev, int video_nr)</div><div class='ctx'> 	dev-&gt;vidq.gfp_flags = __GFP_DMA32 | __GFP_KSWAPD_RECLAIM;</div><div class='ctx'> 	dev-&gt;vidq.buf_struct_size = sizeof(struct tw68_buf);</div><div class='ctx'> 	dev-&gt;vidq.lock = &amp;dev-&gt;lock;</div><div class='del'>-	dev-&gt;vidq.min_buffers_needed = 2;</div><div class='add'>+	dev-&gt;vidq.min_queued_buffers = 2;</div><div class='ctx'> 	dev-&gt;vidq.dev = &amp;dev-&gt;pci-&gt;dev;</div><div class='ctx'> 	ret = vb2_queue_init(&amp;dev-&gt;vidq);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/pci/tw686x/tw686x-video.c b/drivers/media/pci/tw686x/tw686x-video.c<br/>index 3ebf7a2c95f0..63be95fce83d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/tw686x/tw686x-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/tw686x/tw686x-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/tw686x/tw686x-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/tw686x/tw686x-video.c</a></div><div class='hunk'>@@ -423,6 +423,7 @@ static int tw686x_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 			      unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct tw686x_video_channel *vc = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	unsigned int szimage =</div><div class='ctx'> 		(vc-&gt;width * vc-&gt;height * vc-&gt;format-&gt;depth) &gt;&gt; 3;</div><div class='ctx'> </div><div class='hunk'>@@ -430,8 +431,8 @@ static int tw686x_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	 * Let's request at least three buffers: two for the</div><div class='ctx'> 	 * DMA engine and one for userspace.</div><div class='ctx'> 	 */</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (*nplanes != 1 || sizes[0] &lt; szimage)</div><div class='hunk'>@@ -1221,7 +1222,7 @@ int tw686x_video_init(struct tw686x_dev *dev)</div><div class='ctx'> 		vc-&gt;vidq.ops = &amp;tw686x_video_qops;</div><div class='ctx'> 		vc-&gt;vidq.mem_ops = dev-&gt;dma_ops-&gt;mem_ops;</div><div class='ctx'> 		vc-&gt;vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-		vc-&gt;vidq.min_buffers_needed = 2;</div><div class='add'>+		vc-&gt;vidq.min_queued_buffers = 2;</div><div class='ctx'> 		vc-&gt;vidq.lock = &amp;vc-&gt;vb_mutex;</div><div class='ctx'> 		vc-&gt;vidq.gfp_flags = dev-&gt;dma_mode != TW686X_DMA_MODE_MEMCPY ?</div><div class='ctx'> 				     GFP_DMA32 : 0;</div><div class='head'>diff --git a/drivers/media/pci/zoran/zoran_driver.c b/drivers/media/pci/zoran/zoran_driver.c<br/>index fa672cc8bc67..5c05e64c71a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/pci/zoran/zoran_driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/pci/zoran/zoran_driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/pci/zoran/zoran_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/pci/zoran/zoran_driver.c</a></div><div class='hunk'>@@ -749,8 +749,8 @@ static int zr_vb2_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, unsi</div><div class='ctx'> </div><div class='ctx'> 	zr-&gt;buf_in_reserve = 0;</div><div class='ctx'> </div><div class='del'>-	if (*nbuffers &lt; vq-&gt;min_buffers_needed)</div><div class='del'>-		*nbuffers = vq-&gt;min_buffers_needed;</div><div class='add'>+	if (*nbuffers &lt; vq-&gt;min_queued_buffers)</div><div class='add'>+		*nbuffers = vq-&gt;min_queued_buffers;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (sizes[0] &lt; size)</div><div class='hunk'>@@ -971,7 +971,7 @@ int zoran_queue_init(struct zoran *zr, struct vb2_queue *vq, int dir)</div><div class='ctx'> 	vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	vq-&gt;gfp_flags = GFP_DMA32;</div><div class='ctx'> 	vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	vq-&gt;min_buffers_needed = 9;</div><div class='add'>+	vq-&gt;min_queued_buffers = 9;</div><div class='ctx'> 	vq-&gt;lock = &amp;zr-&gt;lock;</div><div class='ctx'> 	err = vb2_queue_init(vq);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/media/platform/amphion/vpu.h b/drivers/media/platform/amphion/vpu.h<br/>index 5a701f64289e..0246cf0ac3a8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/amphion/vpu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu.h</a></div><div class='hunk'>@@ -154,7 +154,6 @@ struct vpu_core {</div><div class='ctx'> 	struct vpu_mbox tx_type;</div><div class='ctx'> 	struct vpu_mbox tx_data;</div><div class='ctx'> 	struct vpu_mbox rx;</div><div class='del'>-	unsigned long cmd_seq;</div><div class='ctx'> </div><div class='ctx'> 	wait_queue_head_t ack_wq;</div><div class='ctx'> 	struct completion cmp;</div><div class='hunk'>@@ -253,6 +252,8 @@ struct vpu_inst {</div><div class='ctx'> </div><div class='ctx'> 	struct list_head cmd_q;</div><div class='ctx'> 	void *pending;</div><div class='add'>+	unsigned long cmd_seq;</div><div class='add'>+	atomic_long_t last_response_cmd;</div><div class='ctx'> </div><div class='ctx'> 	struct vpu_inst_ops *ops;</div><div class='ctx'> 	const struct vpu_format *formats;</div><div class='head'>diff --git a/drivers/media/platform/amphion/vpu_cmds.c b/drivers/media/platform/amphion/vpu_cmds.c<br/>index c2337812573e..5695f5c1cb3e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_cmds.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/amphion/vpu_cmds.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_cmds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_cmds.c</a></div><div class='hunk'>@@ -32,6 +32,7 @@ struct vpu_cmd_t {</div><div class='ctx'> 	struct vpu_cmd_request *request;</div><div class='ctx'> 	struct vpu_rpc_event *pkt;</div><div class='ctx'> 	unsigned long key;</div><div class='add'>+	atomic_long_t *last_response_cmd;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct vpu_cmd_request vpu_cmd_requests[] = {</div><div class='hunk'>@@ -115,6 +116,8 @@ static void vpu_free_cmd(struct vpu_cmd_t *cmd)</div><div class='ctx'> {</div><div class='ctx'> 	if (!cmd)</div><div class='ctx'> 		return;</div><div class='add'>+	if (cmd-&gt;last_response_cmd)</div><div class='add'>+		atomic_long_set(cmd-&gt;last_response_cmd, cmd-&gt;key);</div><div class='ctx'> 	vfree(cmd-&gt;pkt);</div><div class='ctx'> 	vfree(cmd);</div><div class='ctx'> }</div><div class='hunk'>@@ -172,7 +175,8 @@ static int vpu_request_cmd(struct vpu_inst *inst, u32 id, void *data,</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;core-&gt;cmd_lock);</div><div class='del'>-	cmd-&gt;key = core-&gt;cmd_seq++;</div><div class='add'>+	cmd-&gt;key = ++inst-&gt;cmd_seq;</div><div class='add'>+	cmd-&gt;last_response_cmd = &amp;inst-&gt;last_response_cmd;</div><div class='ctx'> 	if (key)</div><div class='ctx'> 		*key = cmd-&gt;key;</div><div class='ctx'> 	if (sync)</div><div class='hunk'>@@ -246,26 +250,12 @@ void vpu_clear_request(struct vpu_inst *inst)</div><div class='ctx'> </div><div class='ctx'> static bool check_is_responsed(struct vpu_inst *inst, unsigned long key)</div><div class='ctx'> {</div><div class='del'>-	struct vpu_core *core = inst-&gt;core;</div><div class='del'>-	struct vpu_cmd_t *cmd;</div><div class='del'>-	bool flag = true;</div><div class='add'>+	unsigned long last_response = atomic_long_read(&amp;inst-&gt;last_response_cmd);</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;core-&gt;cmd_lock);</div><div class='del'>-	cmd = inst-&gt;pending;</div><div class='del'>-	if (cmd &amp;&amp; key == cmd-&gt;key) {</div><div class='del'>-		flag = false;</div><div class='del'>-		goto exit;</div><div class='del'>-	}</div><div class='del'>-	list_for_each_entry(cmd, &amp;inst-&gt;cmd_q, list) {</div><div class='del'>-		if (key == cmd-&gt;key) {</div><div class='del'>-			flag = false;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-exit:</div><div class='del'>-	mutex_unlock(&amp;core-&gt;cmd_lock);</div><div class='add'>+	if (key &lt;= last_response &amp;&amp; (last_response - key) &lt; (ULONG_MAX &gt;&gt; 1))</div><div class='add'>+		return true;</div><div class='ctx'> </div><div class='del'>-	return flag;</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int sync_session_response(struct vpu_inst *inst, unsigned long key, long timeout, int try)</div><div class='head'>diff --git a/drivers/media/platform/amphion/vpu_core.c b/drivers/media/platform/amphion/vpu_core.c<br/>index 1af6fc9460d4..3a2030d02e45 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/amphion/vpu_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_core.c</a></div><div class='hunk'>@@ -642,7 +642,7 @@ static int vpu_core_probe(struct platform_device *pdev)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	core-&gt;type = core-&gt;res-&gt;type;</div><div class='del'>-	core-&gt;id = of_alias_get_id(dev-&gt;of_node, "vpu_core");</div><div class='add'>+	core-&gt;id = of_alias_get_id(dev-&gt;of_node, "vpu-core");</div><div class='ctx'> 	if (core-&gt;id &lt; 0) {</div><div class='ctx'> 		dev_err(dev, "can't get vpu core id\n");</div><div class='ctx'> 		return core-&gt;id;</div><div class='head'>diff --git a/drivers/media/platform/amphion/vpu_dbg.c b/drivers/media/platform/amphion/vpu_dbg.c<br/>index 982c2c777484..940e5bda5fa3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_dbg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/amphion/vpu_dbg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_dbg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_dbg.c</a></div><div class='hunk'>@@ -87,7 +87,7 @@ static int vpu_dbg_instance(struct seq_file *s, void *data)</div><div class='ctx'> 	num = scnprintf(str, sizeof(str),</div><div class='ctx'> 			"output (%2d, %2d): fmt = %c%c%c%c %d x %d, %d;",</div><div class='ctx'> 			vb2_is_streaming(vq),</div><div class='del'>-			vq-&gt;num_buffers,</div><div class='add'>+			vb2_get_num_buffers(vq),</div><div class='ctx'> 			inst-&gt;out_format.pixfmt,</div><div class='ctx'> 			inst-&gt;out_format.pixfmt &gt;&gt; 8,</div><div class='ctx'> 			inst-&gt;out_format.pixfmt &gt;&gt; 16,</div><div class='hunk'>@@ -111,7 +111,7 @@ static int vpu_dbg_instance(struct seq_file *s, void *data)</div><div class='ctx'> 	num = scnprintf(str, sizeof(str),</div><div class='ctx'> 			"capture(%2d, %2d): fmt = %c%c%c%c %d x %d, %d;",</div><div class='ctx'> 			vb2_is_streaming(vq),</div><div class='del'>-			vq-&gt;num_buffers,</div><div class='add'>+			vb2_get_num_buffers(vq),</div><div class='ctx'> 			inst-&gt;cap_format.pixfmt,</div><div class='ctx'> 			inst-&gt;cap_format.pixfmt &gt;&gt; 8,</div><div class='ctx'> 			inst-&gt;cap_format.pixfmt &gt;&gt; 16,</div><div class='hunk'>@@ -139,12 +139,19 @@ static int vpu_dbg_instance(struct seq_file *s, void *data)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	vq = v4l2_m2m_get_src_vq(inst-&gt;fh.m2m_ctx);</div><div class='del'>-	for (i = 0; i &lt; vq-&gt;num_buffers; i++) {</div><div class='del'>-		struct vb2_buffer *vb = vq-&gt;bufs[i];</div><div class='del'>-		struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(vq); i++) {</div><div class='add'>+		struct vb2_buffer *vb;</div><div class='add'>+		struct vb2_v4l2_buffer *vbuf;</div><div class='add'>+</div><div class='add'>+		vb = vb2_get_buffer(vq, i);</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (vb-&gt;state == VB2_BUF_STATE_DEQUEUED)</div><div class='ctx'> 			continue;</div><div class='add'>+</div><div class='add'>+		vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+</div><div class='ctx'> 		num = scnprintf(str, sizeof(str),</div><div class='ctx'> 				"output [%2d] state = %10s, %8s\n",</div><div class='ctx'> 				i, vb2_stat_name[vb-&gt;state],</div><div class='hunk'>@@ -154,12 +161,19 @@ static int vpu_dbg_instance(struct seq_file *s, void *data)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	vq = v4l2_m2m_get_dst_vq(inst-&gt;fh.m2m_ctx);</div><div class='del'>-	for (i = 0; i &lt; vq-&gt;num_buffers; i++) {</div><div class='del'>-		struct vb2_buffer *vb = vq-&gt;bufs[i];</div><div class='del'>-		struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(vq); i++) {</div><div class='add'>+		struct vb2_buffer *vb;</div><div class='add'>+		struct vb2_v4l2_buffer *vbuf;</div><div class='add'>+</div><div class='add'>+		vb = vb2_get_buffer(vq, i);</div><div class='add'>+		if (!vb)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (vb-&gt;state == VB2_BUF_STATE_DEQUEUED)</div><div class='ctx'> 			continue;</div><div class='add'>+</div><div class='add'>+		vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+</div><div class='ctx'> 		num = scnprintf(str, sizeof(str),</div><div class='ctx'> 				"capture[%2d] state = %10s, %8s\n",</div><div class='ctx'> 				i, vb2_stat_name[vb-&gt;state],</div><div class='head'>diff --git a/drivers/media/platform/amphion/vpu_v4l2.c b/drivers/media/platform/amphion/vpu_v4l2.c<br/>index 0f6e4c666440..c88738e8fff7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/amphion/vpu_v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/amphion/vpu_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/amphion/vpu_v4l2.c</a></div><div class='hunk'>@@ -439,7 +439,7 @@ int vpu_get_num_buffers(struct vpu_inst *inst, u32 type)</div><div class='ctx'> 	else</div><div class='ctx'> 		q = v4l2_m2m_get_dst_vq(inst-&gt;fh.m2m_ctx);</div><div class='ctx'> </div><div class='del'>-	return q-&gt;num_buffers;</div><div class='add'>+	return vb2_get_num_buffers(q);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void vpu_m2m_device_run(void *priv)</div><div class='hunk'>@@ -587,7 +587,7 @@ static int vpu_vb2_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 		  fmt-&gt;sizeimage[0], fmt-&gt;bytesperline[0],</div><div class='ctx'> 		  fmt-&gt;sizeimage[1], fmt-&gt;bytesperline[1],</div><div class='ctx'> 		  fmt-&gt;sizeimage[2], fmt-&gt;bytesperline[2],</div><div class='del'>-		  q-&gt;num_buffers);</div><div class='add'>+		  vb2_get_num_buffers(q));</div><div class='ctx'> 	vb2_clear_last_buffer_dequeued(q);</div><div class='ctx'> 	ret = call_vop(inst, start, q-&gt;type);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -649,7 +649,7 @@ static int vpu_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_q</div><div class='ctx'> 		src_vq-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	src_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct vpu_vb2_buffer);</div><div class='del'>-	src_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	src_vq-&gt;dev = inst-&gt;vpu-&gt;dev;</div><div class='ctx'> 	src_vq-&gt;lock = &amp;inst-&gt;lock;</div><div class='ctx'> 	ret = vb2_queue_init(src_vq);</div><div class='hunk'>@@ -666,7 +666,7 @@ static int vpu_m2m_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_q</div><div class='ctx'> 		dst_vq-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	dst_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct vpu_vb2_buffer);</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	dst_vq-&gt;dev = inst-&gt;vpu-&gt;dev;</div><div class='ctx'> 	dst_vq-&gt;lock = &amp;inst-&gt;lock;</div><div class='ctx'> 	ret = vb2_queue_init(dst_vq);</div><div class='hunk'>@@ -716,6 +716,7 @@ int vpu_v4l2_open(struct file *file, struct vpu_inst *inst)</div><div class='ctx'> 		func = &amp;vpu-&gt;decoder;</div><div class='ctx'> </div><div class='ctx'> 	atomic_set(&amp;inst-&gt;ref_count, 0);</div><div class='add'>+	atomic_long_set(&amp;inst-&gt;last_response_cmd, 0);</div><div class='ctx'> 	vpu_inst_get(inst);</div><div class='ctx'> 	inst-&gt;vpu = vpu;</div><div class='ctx'> 	inst-&gt;core = vpu_request_core(vpu, inst-&gt;type);</div><div class='head'>diff --git a/drivers/media/platform/aspeed/aspeed-video.c b/drivers/media/platform/aspeed/aspeed-video.c<br/>index d08aa7f73d4f..fc6050e3be0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/aspeed/aspeed-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/aspeed/aspeed-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/aspeed/aspeed-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/aspeed/aspeed-video.c</a></div><div class='hunk'>@@ -2034,7 +2034,7 @@ static int aspeed_video_setup_video(struct aspeed_video *video)</div><div class='ctx'> 	vbq-&gt;drv_priv = video;</div><div class='ctx'> 	vbq-&gt;buf_struct_size = sizeof(struct aspeed_video_buffer);</div><div class='ctx'> 	vbq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	vbq-&gt;min_buffers_needed = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;</div><div class='add'>+	vbq-&gt;min_queued_buffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;</div><div class='ctx'> </div><div class='ctx'> 	rc = vb2_queue_init(vbq);</div><div class='ctx'> 	if (rc) {</div><div class='head'>diff --git a/drivers/media/platform/atmel/atmel-isi.c b/drivers/media/platform/atmel/atmel-isi.c<br/>index 4046212d48b4..f8450a8ccda6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/atmel/atmel-isi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/atmel/atmel-isi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/atmel/atmel-isi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/atmel/atmel-isi.c</a></div><div class='hunk'>@@ -559,11 +559,13 @@ static const struct isi_format *find_format_by_fourcc(struct atmel_isi *isi,</div><div class='ctx'> static void isi_try_fse(struct atmel_isi *isi, const struct isi_format *isi_fmt,</div><div class='ctx'> 			struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='add'>+	struct v4l2_rect *try_crop =</div><div class='add'>+		v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='ctx'> 	struct v4l2_subdev_frame_size_enum fse = {</div><div class='ctx'> 		.code = isi_fmt-&gt;mbus_code,</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='ctx'> 	};</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_subdev_call(isi-&gt;entity.subdev, pad, enum_frame_size,</div><div class='ctx'> 			       sd_state, &amp;fse);</div><div class='hunk'>@@ -572,11 +574,11 @@ static void isi_try_fse(struct atmel_isi *isi, const struct isi_format *isi_fmt,</div><div class='ctx'> 	 * just use the maximum ISI can receive.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.width = MAX_SUPPORT_WIDTH;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.height = MAX_SUPPORT_HEIGHT;</div><div class='add'>+		try_crop-&gt;width = MAX_SUPPORT_WIDTH;</div><div class='add'>+		try_crop-&gt;height = MAX_SUPPORT_HEIGHT;</div><div class='ctx'> 	} else {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.width = fse.max_width;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.height = fse.max_height;</div><div class='add'>+		try_crop-&gt;width = fse.max_width;</div><div class='add'>+		try_crop-&gt;height = fse.max_height;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -587,6 +589,7 @@ static int isi_try_fmt(struct atmel_isi *isi, struct v4l2_format *f,</div><div class='ctx'> 	struct v4l2_pix_format *pixfmt = &amp;f-&gt;fmt.pix;</div><div class='ctx'> 	struct v4l2_subdev_pad_config pad_cfg = {};</div><div class='ctx'> 	struct v4l2_subdev_state pad_state = {</div><div class='add'>+		.sd = isi-&gt;entity.subdev,</div><div class='ctx'> 		.pads = &amp;pad_cfg,</div><div class='ctx'> 	};</div><div class='ctx'> 	struct v4l2_subdev_format format = {</div><div class='hunk'>@@ -1242,7 +1245,7 @@ static int atmel_isi_probe(struct platform_device *pdev)</div><div class='ctx'> 	q-&gt;ops = &amp;isi_video_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c<br/>index 889f4fbbafb3..fead5426830e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/cadence/cdns-csi2rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/cadence/cdns-csi2rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/cadence/cdns-csi2rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/cadence/cdns-csi2rx.c</a></div><div class='hunk'>@@ -406,20 +406,20 @@ static int csi2rx_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	format-&gt;format.field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='ctx'> 	/* Set sink format */</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(subdev, state, format-&gt;pad);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, format-&gt;pad);</div><div class='ctx'> 	*fmt = format-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate to source formats */</div><div class='ctx'> 	for (i = CSI2RX_PAD_SOURCE_STREAM0; i &lt; CSI2RX_PAD_MAX; i++) {</div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(subdev, state, i);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(state, i);</div><div class='ctx'> 		*fmt = format-&gt;format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int csi2rx_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-			   struct v4l2_subdev_state *state)</div><div class='add'>+static int csi2rx_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+			     struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format format = {</div><div class='ctx'> 		.pad = CSI2RX_PAD_SINK,</div><div class='hunk'>@@ -441,7 +441,6 @@ static int csi2rx_init_cfg(struct v4l2_subdev *subdev,</div><div class='ctx'> static const struct v4l2_subdev_pad_ops csi2rx_pad_ops = {</div><div class='ctx'> 	.get_fmt	= v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt	= csi2rx_set_fmt,</div><div class='del'>-	.init_cfg	= csi2rx_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops csi2rx_video_ops = {</div><div class='hunk'>@@ -453,6 +452,10 @@ static const struct v4l2_subdev_ops csi2rx_subdev_ops = {</div><div class='ctx'> 	.pad		= &amp;csi2rx_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops csi2rx_internal_ops = {</div><div class='add'>+	.init_state	= csi2rx_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations csi2rx_media_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -663,6 +666,7 @@ static int csi2rx_probe(struct platform_device *pdev)</div><div class='ctx'> 	csi2rx-&gt;subdev.owner = THIS_MODULE;</div><div class='ctx'> 	csi2rx-&gt;subdev.dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	v4l2_subdev_init(&amp;csi2rx-&gt;subdev, &amp;csi2rx_subdev_ops);</div><div class='add'>+	csi2rx-&gt;subdev.internal_ops = &amp;csi2rx_internal_ops;</div><div class='ctx'> 	v4l2_set_subdevdata(&amp;csi2rx-&gt;subdev, &amp;pdev-&gt;dev);</div><div class='ctx'> 	snprintf(csi2rx-&gt;subdev.name, sizeof(csi2rx-&gt;subdev.name),</div><div class='ctx'> 		 "%s.%s", KBUILD_MODNAME, dev_name(&amp;pdev-&gt;dev));</div><div class='head'>diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c<br/>index c115742f347f..3d98f91f1bee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/cadence/cdns-csi2tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/cadence/cdns-csi2tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/cadence/cdns-csi2tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/cadence/cdns-csi2tx.c</a></div><div class='hunk'>@@ -176,8 +176,7 @@ __csi2tx_get_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 	struct csi2tx_priv *csi2tx = v4l2_subdev_to_csi2tx(subdev);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(subdev, sd_state,</div><div class='del'>-						  fmt-&gt;pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;csi2tx-&gt;pad_fmts[fmt-&gt;pad];</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/chips-media/Kconfig b/drivers/media/platform/chips-media/Kconfig<br/>index 57f8f8a22df8..ad350eb6b1fc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/Kconfig</a></div><div class='hunk'>@@ -2,19 +2,5 @@</div><div class='ctx'> </div><div class='ctx'> comment "Chips&amp;Media media platform drivers"</div><div class='ctx'> </div><div class='del'>-config VIDEO_CODA</div><div class='del'>-	tristate "Chips&amp;Media Coda multi-standard codec IP"</div><div class='del'>-	depends on V4L_MEM2MEM_DRIVERS</div><div class='del'>-	depends on VIDEO_DEV &amp;&amp; OF &amp;&amp; (ARCH_MXC || COMPILE_TEST)</div><div class='del'>-	select SRAM</div><div class='del'>-	select VIDEOBUF2_DMA_CONTIG</div><div class='del'>-	select VIDEOBUF2_VMALLOC</div><div class='del'>-	select V4L2_JPEG_HELPER</div><div class='del'>-	select V4L2_MEM2MEM_DEV</div><div class='del'>-	select GENERIC_ALLOCATOR</div><div class='del'>-	help</div><div class='del'>-	   Coda is a range of video codec IPs that supports</div><div class='del'>-	   H.264, MPEG-4, and other video formats.</div><div class='del'>-</div><div class='del'>-config VIDEO_IMX_VDOA</div><div class='del'>-	def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST</div><div class='add'>+source "drivers/media/platform/chips-media/coda/Kconfig"</div><div class='add'>+source "drivers/media/platform/chips-media/wave5/Kconfig"</div><div class='head'>diff --git a/drivers/media/platform/chips-media/Makefile b/drivers/media/platform/chips-media/Makefile<br/>index bbb16425a875..6b5d99de8b54 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/Makefile</a></div><div class='hunk'>@@ -1,6 +1,4 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> </div><div class='del'>-coda-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o</div><div class='del'>-</div><div class='del'>-obj-$(CONFIG_VIDEO_CODA) += coda-vpu.o</div><div class='del'>-obj-$(CONFIG_VIDEO_IMX_VDOA) += imx-vdoa.o</div><div class='add'>+obj-y += coda/</div><div class='add'>+obj-y += wave5/</div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda/Kconfig b/drivers/media/platform/chips-media/coda/Kconfig<br/>new file mode 100644<br/>index 000000000000..cb7b66c71380<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,18 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+config VIDEO_CODA</div><div class='add'>+	tristate "Chips&amp;Media Coda multi-standard codec IP"</div><div class='add'>+	depends on V4L_MEM2MEM_DRIVERS</div><div class='add'>+	depends on VIDEO_DEV &amp;&amp; OF &amp;&amp; (ARCH_MXC || COMPILE_TEST)</div><div class='add'>+	select SRAM</div><div class='add'>+	select VIDEOBUF2_DMA_CONTIG</div><div class='add'>+	select VIDEOBUF2_VMALLOC</div><div class='add'>+	select V4L2_JPEG_HELPER</div><div class='add'>+	select V4L2_MEM2MEM_DEV</div><div class='add'>+	select GENERIC_ALLOCATOR</div><div class='add'>+	help</div><div class='add'>+	   Coda is a range of video codec IPs that supports</div><div class='add'>+	   H.264, MPEG-4, and other video formats.</div><div class='add'>+</div><div class='add'>+config VIDEO_IMX_VDOA</div><div class='add'>+	def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST</div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda/Makefile b/drivers/media/platform/chips-media/coda/Makefile<br/>new file mode 100644<br/>index 000000000000..bbb16425a875<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/Makefile</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+</div><div class='add'>+coda-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_VIDEO_CODA) += coda-vpu.o</div><div class='add'>+obj-$(CONFIG_VIDEO_IMX_VDOA) += imx-vdoa.o</div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-bit.c b/drivers/media/platform/chips-media/coda/coda-bit.c<br/>index ed47d5bd8d61..ed47d5bd8d61 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-bit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-bit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-bit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-bit.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-common.c b/drivers/media/platform/chips-media/coda/coda-common.c<br/>index cc4892129aaf..7da0194ec850 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-common.c</a></div><div class='hunk'>@@ -794,7 +794,7 @@ static int coda_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f,</div><div class='ctx'> </div><div class='ctx'> 	if (vb2_is_busy(vq)) {</div><div class='ctx'> 		v4l2_err(&amp;ctx-&gt;dev-&gt;v4l2_dev, "%s: %s queue busy: %d\n",</div><div class='del'>-			 __func__, v4l2_type_names[f-&gt;type], vq-&gt;num_buffers);</div><div class='add'>+			 __func__, v4l2_type_names[f-&gt;type], vb2_get_num_buffers(vq));</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2546,7 +2546,7 @@ static int coda_queue_init(struct coda_ctx *ctx, struct vb2_queue *vq)</div><div class='ctx'> 	 * would need to be reflected in job_ready(). Currently we expect all</div><div class='ctx'> 	 * queues to have at least one buffer queued.</div><div class='ctx'> 	 */</div><div class='del'>-	vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	vq-&gt;dev = ctx-&gt;dev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	return vb2_queue_init(vq);</div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-gdi.c b/drivers/media/platform/chips-media/coda/coda-gdi.c<br/>index 59d65daca153..59d65daca153 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-gdi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-gdi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-gdi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-gdi.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-h264.c b/drivers/media/platform/chips-media/coda/coda-h264.c<br/>index 8bd0aa8af114..8bd0aa8af114 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-h264.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-h264.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-h264.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-h264.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-jpeg.c b/drivers/media/platform/chips-media/coda/coda-jpeg.c<br/>index ba8f41002917..ba8f41002917 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-jpeg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-jpeg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-jpeg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-jpeg.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-mpeg2.c b/drivers/media/platform/chips-media/coda/coda-mpeg2.c<br/>index 6f3f6721d286..6f3f6721d286 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-mpeg2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-mpeg2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-mpeg2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-mpeg2.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda-mpeg4.c b/drivers/media/platform/chips-media/coda/coda-mpeg4.c<br/>index 483a4fba1b4f..483a4fba1b4f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda-mpeg4.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda-mpeg4.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda-mpeg4.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda-mpeg4.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda.h b/drivers/media/platform/chips-media/coda/coda.h<br/>index ddfd0a32c653..ddfd0a32c653 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda.h</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/coda_regs.h b/drivers/media/platform/chips-media/coda/coda_regs.h<br/>index db81a904cf3f..db81a904cf3f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/coda_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/coda_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/coda_regs.h</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/imx-vdoa.c b/drivers/media/platform/chips-media/coda/imx-vdoa.c<br/>index c3561fcecb98..c3561fcecb98 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/imx-vdoa.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/imx-vdoa.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/imx-vdoa.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/imx-vdoa.c</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/imx-vdoa.h b/drivers/media/platform/chips-media/coda/imx-vdoa.h<br/>index a62eab476d58..a62eab476d58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/imx-vdoa.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/imx-vdoa.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/imx-vdoa.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/imx-vdoa.h</a></div><div class='head'>diff --git a/drivers/media/platform/chips-media/trace.h b/drivers/media/platform/chips-media/coda/trace.h<br/>index 19f98e6dafb9..abc6a01a74e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/trace.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/chips-media/trace.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/coda/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/coda/trace.h</a></div><div class='hunk'>@@ -167,7 +167,7 @@ DEFINE_EVENT(coda_buf_class, coda_jpeg_done,</div><div class='ctx'> #endif /* __CODA_TRACE_H__ */</div><div class='ctx'> </div><div class='ctx'> #undef TRACE_INCLUDE_PATH</div><div class='del'>-#define TRACE_INCLUDE_PATH ../../drivers/media/platform/chips-media</div><div class='add'>+#define TRACE_INCLUDE_PATH ../../drivers/media/platform/chips-media/coda</div><div class='ctx'> #undef TRACE_INCLUDE_FILE</div><div class='ctx'> #define TRACE_INCLUDE_FILE trace</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/Kconfig b/drivers/media/platform/chips-media/wave5/Kconfig<br/>new file mode 100644<br/>index 000000000000..f1bcef5177bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+config VIDEO_WAVE_VPU</div><div class='add'>+	tristate "Chips&amp;Media Wave Codec Driver"</div><div class='add'>+	depends on V4L_MEM2MEM_DRIVERS</div><div class='add'>+	depends on VIDEO_DEV &amp;&amp; OF</div><div class='add'>+	depends on ARCH_K3 || COMPILE_TEST</div><div class='add'>+	select VIDEOBUF2_DMA_CONTIG</div><div class='add'>+	select VIDEOBUF2_VMALLOC</div><div class='add'>+	select V4L2_MEM2MEM_DEV</div><div class='add'>+	select GENERIC_ALLOCATOR</div><div class='add'>+	help</div><div class='add'>+	  Chips&amp;Media stateful encoder and decoder driver.</div><div class='add'>+	  The driver supports HEVC and H264 formats.</div><div class='add'>+	  To compile this driver as modules, choose M here: the</div><div class='add'>+	  modules will be called wave5.</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/Makefile b/drivers/media/platform/chips-media/wave5/Makefile<br/>new file mode 100644<br/>index 000000000000..3d738a03bd8e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/Makefile</a></div><div class='hunk'>@@ -0,0 +1,10 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_VIDEO_WAVE_VPU) += wave5.o</div><div class='add'>+wave5-objs +=  	wave5-hw.o \</div><div class='add'>+		wave5-vpuapi.o \</div><div class='add'>+		wave5-vdi.o \</div><div class='add'>+		wave5-vpu-dec.o \</div><div class='add'>+		wave5-vpu.o \</div><div class='add'>+		wave5-vpu-enc.o \</div><div class='add'>+		wave5-helper.o</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c<br/>new file mode 100644<br/>index 000000000000..8433ecab230c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-helper.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-helper.c</a></div><div class='hunk'>@@ -0,0 +1,213 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - decoder interface</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "wave5-helper.h"</div><div class='add'>+</div><div class='add'>+const char *state_to_str(enum vpu_instance_state state)</div><div class='add'>+{</div><div class='add'>+	switch (state) {</div><div class='add'>+	case VPU_INST_STATE_NONE:</div><div class='add'>+		return "NONE";</div><div class='add'>+	case VPU_INST_STATE_OPEN:</div><div class='add'>+		return "OPEN";</div><div class='add'>+	case VPU_INST_STATE_INIT_SEQ:</div><div class='add'>+		return "INIT_SEQ";</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		return "PIC_RUN";</div><div class='add'>+	case VPU_INST_STATE_STOP:</div><div class='add'>+		return "STOP";</div><div class='add'>+	default:</div><div class='add'>+		return "UNKNOWN";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_cleanup_instance(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (list_is_singular(&amp;inst-&gt;list))</div><div class='add'>+		wave5_vdi_free_sram(inst-&gt;dev);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;fbc_buf_count; i++)</div><div class='add'>+		wave5_vpu_dec_reset_framebuffer(inst, i);</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;inst-&gt;bitstream_vbuf);</div><div class='add'>+	v4l2_ctrl_handler_free(&amp;inst-&gt;v4l2_ctrl_hdl);</div><div class='add'>+	if (inst-&gt;v4l2_fh.vdev) {</div><div class='add'>+		v4l2_fh_del(&amp;inst-&gt;v4l2_fh);</div><div class='add'>+		v4l2_fh_exit(&amp;inst-&gt;v4l2_fh);</div><div class='add'>+	}</div><div class='add'>+	list_del_init(&amp;inst-&gt;list);</div><div class='add'>+	ida_free(&amp;inst-&gt;dev-&gt;inst_ida, inst-&gt;id);</div><div class='add'>+	kfree(inst-&gt;codec_info);</div><div class='add'>+	kfree(inst);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_release_device(struct file *filp,</div><div class='add'>+			     int (*close_func)(struct vpu_instance *inst, u32 *fail_res),</div><div class='add'>+			     char *name)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(filp-&gt;private_data);</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_ctx_release(inst-&gt;v4l2_fh.m2m_ctx);</div><div class='add'>+	if (inst-&gt;state != VPU_INST_STATE_NONE) {</div><div class='add'>+		u32 fail_res;</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		ret = close_func(inst, &amp;fail_res);</div><div class='add'>+		if (fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "%s close failed, device is still running\n",</div><div class='add'>+				name);</div><div class='add'>+			return -EBUSY;</div><div class='add'>+		}</div><div class='add'>+		if (ret &amp;&amp; ret != -EIO) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "%s close, fail: %d\n", name, ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_cleanup_instance(inst);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq,</div><div class='add'>+			 const struct vb2_ops *ops)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	src_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;</div><div class='add'>+	src_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='add'>+	src_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='add'>+	src_vq-&gt;ops = ops;</div><div class='add'>+	src_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='add'>+	src_vq-&gt;buf_struct_size = sizeof(struct vpu_src_buffer);</div><div class='add'>+	src_vq-&gt;drv_priv = inst;</div><div class='add'>+	src_vq-&gt;lock = &amp;inst-&gt;dev-&gt;dev_lock;</div><div class='add'>+	src_vq-&gt;dev = inst-&gt;dev-&gt;v4l2_dev.dev;</div><div class='add'>+	ret = vb2_queue_init(src_vq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dst_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;</div><div class='add'>+	dst_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='add'>+	dst_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='add'>+	dst_vq-&gt;ops = ops;</div><div class='add'>+	dst_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='add'>+	dst_vq-&gt;buf_struct_size = sizeof(struct vpu_src_buffer);</div><div class='add'>+	dst_vq-&gt;drv_priv = inst;</div><div class='add'>+	dst_vq-&gt;lock = &amp;inst-&gt;dev-&gt;dev_lock;</div><div class='add'>+	dst_vq-&gt;dev = inst-&gt;dev-&gt;v4l2_dev.dev;</div><div class='add'>+	ret = vb2_queue_init(dst_vq);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	bool is_decoder = inst-&gt;type == VPU_INST_TYPE_DEC;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: [%s] type: %u id: %u | flags: %u\n", __func__,</div><div class='add'>+		is_decoder ? "decoder" : "encoder", sub-&gt;type, sub-&gt;id, sub-&gt;flags);</div><div class='add'>+</div><div class='add'>+	switch (sub-&gt;type) {</div><div class='add'>+	case V4L2_EVENT_EOS:</div><div class='add'>+		return v4l2_event_subscribe(fh, sub, 0, NULL);</div><div class='add'>+	case V4L2_EVENT_SOURCE_CHANGE:</div><div class='add'>+		if (is_decoder)</div><div class='add'>+			return v4l2_src_change_event_subscribe(fh, sub);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	case V4L2_EVENT_CTRL:</div><div class='add'>+		return v4l2_ctrl_subscribe_event(fh, sub);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.width = inst-&gt;src_fmt.width;</div><div class='add'>+	f-&gt;fmt.pix_mp.height = inst-&gt;src_fmt.height;</div><div class='add'>+	f-&gt;fmt.pix_mp.pixelformat = inst-&gt;src_fmt.pixelformat;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = inst-&gt;src_fmt.field;</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = inst-&gt;src_fmt.flags;</div><div class='add'>+	f-&gt;fmt.pix_mp.num_planes = inst-&gt;src_fmt.num_planes;</div><div class='add'>+	for (i = 0; i &lt; f-&gt;fmt.pix_mp.num_planes; i++) {</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline = inst-&gt;src_fmt.plane_fmt[i].bytesperline;</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage = inst-&gt;src_fmt.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.colorspace = inst-&gt;colorspace;</div><div class='add'>+	f-&gt;fmt.pix_mp.ycbcr_enc = inst-&gt;ycbcr_enc;</div><div class='add'>+	f-&gt;fmt.pix_mp.quantization = inst-&gt;quantization;</div><div class='add'>+	f-&gt;fmt.pix_mp.xfer_func = inst-&gt;xfer_func;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt,</div><div class='add'>+					    const struct vpu_format fmt_list[MAX_FMTS])</div><div class='add'>+{</div><div class='add'>+	unsigned int index;</div><div class='add'>+</div><div class='add'>+	for (index = 0; index &lt; MAX_FMTS; index++) {</div><div class='add'>+		if (fmt_list[index].v4l2_pix_fmt == v4l2_pix_fmt)</div><div class='add'>+			return &amp;fmt_list[index];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx,</div><div class='add'>+						   const struct vpu_format fmt_list[MAX_FMTS])</div><div class='add'>+{</div><div class='add'>+	if (idx &gt;= MAX_FMTS)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (!fmt_list[idx].v4l2_pix_fmt)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return &amp;fmt_list[idx];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type)</div><div class='add'>+{</div><div class='add'>+	switch (v4l2_pix_fmt) {</div><div class='add'>+	case V4L2_PIX_FMT_H264:</div><div class='add'>+		return type == VPU_INST_TYPE_DEC ? W_AVC_DEC : W_AVC_ENC;</div><div class='add'>+	case V4L2_PIX_FMT_HEVC:</div><div class='add'>+		return type == VPU_INST_TYPE_DEC ? W_HEVC_DEC : W_HEVC_ENC;</div><div class='add'>+	default:</div><div class='add'>+		return STD_UNKNOWN;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_return_bufs(struct vb2_queue *q, u32 state)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct v4l2_ctrl_handler v4l2_ctrl_hdl = inst-&gt;v4l2_ctrl_hdl;</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf;</div><div class='add'>+</div><div class='add'>+	for (;;) {</div><div class='add'>+		if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+			vbuf = v4l2_m2m_src_buf_remove(m2m_ctx);</div><div class='add'>+		else</div><div class='add'>+			vbuf = v4l2_m2m_dst_buf_remove(m2m_ctx);</div><div class='add'>+		if (!vbuf)</div><div class='add'>+			return;</div><div class='add'>+		v4l2_ctrl_request_complete(vbuf-&gt;vb2_buf.req_obj.req, &amp;v4l2_ctrl_hdl);</div><div class='add'>+		v4l2_m2m_buf_done(vbuf, state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h<br/>new file mode 100644<br/>index 000000000000..6cee1c14d3ce<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-helper.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-helper.h</a></div><div class='hunk'>@@ -0,0 +1,31 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - basic types</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __WAVE_HELPER_H__</div><div class='add'>+#define __WAVE_HELPER_H__</div><div class='add'>+</div><div class='add'>+#include "wave5-vpu.h"</div><div class='add'>+</div><div class='add'>+#define FMT_TYPES	2</div><div class='add'>+#define MAX_FMTS	12</div><div class='add'>+</div><div class='add'>+const char *state_to_str(enum vpu_instance_state state);</div><div class='add'>+void wave5_cleanup_instance(struct vpu_instance *inst);</div><div class='add'>+int wave5_vpu_release_device(struct file *filp,</div><div class='add'>+			     int (*close_func)(struct vpu_instance *inst, u32 *fail_res),</div><div class='add'>+			     char *name);</div><div class='add'>+int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq,</div><div class='add'>+			 const struct vb2_ops *ops);</div><div class='add'>+int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub);</div><div class='add'>+int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f);</div><div class='add'>+const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt,</div><div class='add'>+					    const struct vpu_format fmt_list[MAX_FMTS]);</div><div class='add'>+const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx,</div><div class='add'>+						   const struct vpu_format fmt_list[MAX_FMTS]);</div><div class='add'>+enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type);</div><div class='add'>+void wave5_return_bufs(struct vb2_queue *q, u32 state);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c<br/>new file mode 100644<br/>index 000000000000..f1e022fb148e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-hw.c</a></div><div class='hunk'>@@ -0,0 +1,2551 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - wave5 backend logic</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include "wave5-vpu.h"</div><div class='add'>+#include "wave5.h"</div><div class='add'>+#include "wave5-regdefine.h"</div><div class='add'>+</div><div class='add'>+#define FIO_TIMEOUT			10000000</div><div class='add'>+#define FIO_CTRL_READY			BIT(31)</div><div class='add'>+#define FIO_CTRL_WRITE			BIT(16)</div><div class='add'>+#define VPU_BUSY_CHECK_TIMEOUT		10000000</div><div class='add'>+#define QUEUE_REPORT_MASK		0xffff</div><div class='add'>+</div><div class='add'>+/* Encoder support fields */</div><div class='add'>+#define FEATURE_HEVC10BIT_ENC		BIT(3)</div><div class='add'>+#define FEATURE_AVC10BIT_ENC		BIT(11)</div><div class='add'>+#define FEATURE_AVC_ENCODER		BIT(1)</div><div class='add'>+#define FEATURE_HEVC_ENCODER		BIT(0)</div><div class='add'>+</div><div class='add'>+/* Decoder support fields */</div><div class='add'>+#define FEATURE_AVC_DECODER		BIT(3)</div><div class='add'>+#define FEATURE_HEVC_DECODER		BIT(2)</div><div class='add'>+</div><div class='add'>+#define FEATURE_BACKBONE		BIT(16)</div><div class='add'>+#define FEATURE_VCORE_BACKBONE		BIT(22)</div><div class='add'>+#define FEATURE_VCPU_BACKBONE		BIT(28)</div><div class='add'>+</div><div class='add'>+#define REMAP_CTRL_MAX_SIZE_BITS	((W5_REMAP_MAX_SIZE &gt;&gt; 12) &amp; 0x1ff)</div><div class='add'>+#define REMAP_CTRL_REGISTER_VALUE(index)	(			\</div><div class='add'>+	(BIT(31) | (index &lt;&lt; 12) | BIT(11) | REMAP_CTRL_MAX_SIZE_BITS)	\</div><div class='add'>+)</div><div class='add'>+</div><div class='add'>+#define FASTIO_ADDRESS_MASK		GENMASK(15, 0)</div><div class='add'>+#define SEQ_PARAM_PROFILE_MASK		GENMASK(30, 24)</div><div class='add'>+</div><div class='add'>+static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,</div><div class='add'>+				 const char *func);</div><div class='add'>+#define PRINT_REG_ERR(dev, reason)	_wave5_print_reg_err((dev), (reason), __func__)</div><div class='add'>+</div><div class='add'>+static inline const char *cmd_to_str(int cmd, bool is_dec)</div><div class='add'>+{</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case W5_INIT_VPU:</div><div class='add'>+		return "W5_INIT_VPU";</div><div class='add'>+	case W5_WAKEUP_VPU:</div><div class='add'>+		return "W5_WAKEUP_VPU";</div><div class='add'>+	case W5_SLEEP_VPU:</div><div class='add'>+		return "W5_SLEEP_VPU";</div><div class='add'>+	case W5_CREATE_INSTANCE:</div><div class='add'>+		return "W5_CREATE_INSTANCE";</div><div class='add'>+	case W5_FLUSH_INSTANCE:</div><div class='add'>+		return "W5_FLUSH_INSTANCE";</div><div class='add'>+	case W5_DESTROY_INSTANCE:</div><div class='add'>+		return "W5_DESTROY_INSTANCE";</div><div class='add'>+	case W5_INIT_SEQ:</div><div class='add'>+		return "W5_INIT_SEQ";</div><div class='add'>+	case W5_SET_FB:</div><div class='add'>+		return "W5_SET_FB";</div><div class='add'>+	case W5_DEC_ENC_PIC:</div><div class='add'>+		if (is_dec)</div><div class='add'>+			return "W5_DEC_PIC";</div><div class='add'>+		return "W5_ENC_PIC";</div><div class='add'>+	case W5_ENC_SET_PARAM:</div><div class='add'>+		return "W5_ENC_SET_PARAM";</div><div class='add'>+	case W5_QUERY:</div><div class='add'>+		return "W5_QUERY";</div><div class='add'>+	case W5_UPDATE_BS:</div><div class='add'>+		return "W5_UPDATE_BS";</div><div class='add'>+	case W5_MAX_VPU_COMD:</div><div class='add'>+		return "W5_MAX_VPU_COMD";</div><div class='add'>+	default:</div><div class='add'>+		return "UNKNOWN";</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,</div><div class='add'>+				 const char *func)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = vpu_dev-&gt;dev;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+</div><div class='add'>+	switch (reg_fail_reason) {</div><div class='add'>+	case WAVE5_SYSERR_QUEUEING_FAIL:</div><div class='add'>+		reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON);</div><div class='add'>+		dev_dbg(dev, "%s: queueing failure: 0x%x\n", func, reg_val);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_RESULT_NOT_READY:</div><div class='add'>+		dev_err(dev, "%s: result not ready: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_ACCESS_VIOLATION_HW:</div><div class='add'>+		dev_err(dev, "%s: access violation: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_WATCHDOG_TIMEOUT:</div><div class='add'>+		dev_err(dev, "%s: watchdog timeout: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_BUS_ERROR:</div><div class='add'>+		dev_err(dev, "%s: bus error: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_DOUBLE_FAULT:</div><div class='add'>+		dev_err(dev, "%s: double fault: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_VPU_STILL_RUNNING:</div><div class='add'>+		dev_err(dev, "%s: still running: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	case WAVE5_SYSERR_VLC_BUF_FULL:</div><div class='add'>+		dev_err(dev, "%s: vlc buf full: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(dev, "%s: failure:: 0x%x\n", func, reg_fail_reason);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val)</div><div class='add'>+{</div><div class='add'>+	u32 ctrl;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ctrl = addr &amp; 0xffff;</div><div class='add'>+	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl);</div><div class='add'>+	ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl &amp; FIO_CTRL_READY,</div><div class='add'>+				0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	unsigned int ctrl;</div><div class='add'>+</div><div class='add'>+	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data);</div><div class='add'>+	ctrl = FIELD_GET(FASTIO_ADDRESS_MASK, addr);</div><div class='add'>+	ctrl |= FIO_CTRL_WRITE;</div><div class='add'>+	wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl);</div><div class='add'>+	ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl &amp; FIO_CTRL_READY, 0,</div><div class='add'>+				FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_dbg_ratelimited(vpu_dev-&gt;dev, "FIO write timeout: addr=0x%x data=%x\n",</div><div class='add'>+				    ctrl, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr)</div><div class='add'>+{</div><div class='add'>+	u32 gdi_status_check_value = 0x3f;</div><div class='add'>+</div><div class='add'>+	if (vpu_dev-&gt;product_code == WAVE521C_CODE ||</div><div class='add'>+	    vpu_dev-&gt;product_code == WAVE521_CODE ||</div><div class='add'>+	    vpu_dev-&gt;product_code == WAVE521E1_CODE)</div><div class='add'>+		gdi_status_check_value = 0x00ff1f3f;</div><div class='add'>+</div><div class='add'>+	return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr)</div><div class='add'>+{</div><div class='add'>+	u32 data;</div><div class='add'>+</div><div class='add'>+	return read_poll_timeout(wave5_vdi_read_register, data, data == 0,</div><div class='add'>+				 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr)</div><div class='add'>+{</div><div class='add'>+	return wave5_wait_fio_readl(vpu_dev, addr, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool wave5_vpu_is_init(struct vpu_device *vpu_dev)</div><div class='add'>+{</div><div class='add'>+	return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev)</div><div class='add'>+{</div><div class='add'>+	u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER);</div><div class='add'>+</div><div class='add'>+	switch (val) {</div><div class='add'>+	case WAVE521C_CODE:</div><div class='add'>+		return PRODUCT_ID_521;</div><div class='add'>+	case WAVE521_CODE:</div><div class='add'>+	case WAVE521C_DUAL_CODE:</div><div class='add'>+	case WAVE521E1_CODE:</div><div class='add'>+	case WAVE511_CODE:</div><div class='add'>+	case WAVE517_CODE:</div><div class='add'>+	case WAVE537_CODE:</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "Unsupported product id (%x)\n", val);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "Invalid product id (%x)\n", val);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return PRODUCT_ID_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd)</div><div class='add'>+{</div><div class='add'>+	u32 instance_index;</div><div class='add'>+	u32 codec_mode;</div><div class='add'>+</div><div class='add'>+	if (inst) {</div><div class='add'>+		instance_index = inst-&gt;id;</div><div class='add'>+		codec_mode = inst-&gt;std;</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode &lt;&lt; 16) |</div><div class='add'>+			      (instance_index &amp; 0xffff));</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_COMMAND, cmd);</div><div class='add'>+</div><div class='add'>+	if (inst) {</div><div class='add'>+		dev_dbg(vpu_dev-&gt;dev, "%s: cmd=0x%x (%s)\n", __func__, cmd,</div><div class='add'>+			cmd_to_str(cmd, inst-&gt;type == VPU_INST_TYPE_DEC));</div><div class='add'>+	} else {</div><div class='add'>+		dev_dbg(vpu_dev-&gt;dev, "%s: cmd=0x%x\n", __func__, cmd);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_firmware_command_queue_error_check(struct vpu_device *dev, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	u32 reason = 0;</div><div class='add'>+</div><div class='add'>+	/* Check if we were able to add a command into the VCPU QUEUE */</div><div class='add'>+	if (!vpu_read_reg(dev, W5_RET_SUCCESS)) {</div><div class='add'>+		reason = vpu_read_reg(dev, W5_RET_FAIL_REASON);</div><div class='add'>+		PRINT_REG_ERR(dev, reason);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The fail_res argument will be either NULL or 0.</div><div class='add'>+		 * If the fail_res argument is NULL, then just return -EIO.</div><div class='add'>+		 * Otherwise, assign the reason to fail_res, so that the</div><div class='add'>+		 * calling function can use it.</div><div class='add'>+		 */</div><div class='add'>+		if (fail_res)</div><div class='add'>+			*fail_res = reason;</div><div class='add'>+		else</div><div class='add'>+			return -EIO;</div><div class='add'>+</div><div class='add'>+		if (reason == WAVE5_SYSERR_VPU_STILL_RUNNING)</div><div class='add'>+			return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int send_firmware_command(struct vpu_instance *inst, u32 cmd, bool check_success,</div><div class='add'>+				 u32 *queue_status, u32 *fail_result)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	wave5_bit_issue_command(inst-&gt;dev, inst, cmd);</div><div class='add'>+	ret = wave5_wait_vpu_busy(inst-&gt;dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "%s: command: '%s', timed out\n", __func__,</div><div class='add'>+			 cmd_to_str(cmd, inst-&gt;type == VPU_INST_TYPE_DEC));</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (queue_status)</div><div class='add'>+		*queue_status = vpu_read_reg(inst-&gt;dev, W5_RET_QUEUE_STATUS);</div><div class='add'>+</div><div class='add'>+	/* In some cases we want to send multiple commands before checking</div><div class='add'>+	 * whether they are queued properly</div><div class='add'>+	 */</div><div class='add'>+	if (!check_success)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return wave5_vpu_firmware_command_queue_error_check(inst-&gt;dev, fail_result);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst,</div><div class='add'>+			    enum query_opt query_opt)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+	wave5_bit_issue_command(vpu_dev, inst, W5_QUERY);</div><div class='add'>+</div><div class='add'>+	ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(vpu_dev-&gt;dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int setup_wave5_properties(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	struct vpu_attr *p_attr = &amp;vpu_dev-&gt;attr;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	u8 *str;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 hw_config_def0, hw_config_def1, hw_config_feature;</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME);</div><div class='add'>+	str = (u8 *)&amp;reg_val;</div><div class='add'>+	p_attr-&gt;product_name[0] = str[3];</div><div class='add'>+	p_attr-&gt;product_name[1] = str[2];</div><div class='add'>+	p_attr-&gt;product_name[2] = str[1];</div><div class='add'>+	p_attr-&gt;product_name[3] = str[0];</div><div class='add'>+	p_attr-&gt;product_name[4] = 0;</div><div class='add'>+</div><div class='add'>+	p_attr-&gt;product_id = wave5_vpu_get_product_id(vpu_dev);</div><div class='add'>+	p_attr-&gt;product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION);</div><div class='add'>+	p_attr-&gt;fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION);</div><div class='add'>+	p_attr-&gt;customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID);</div><div class='add'>+	hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0);</div><div class='add'>+	hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1);</div><div class='add'>+	hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE);</div><div class='add'>+</div><div class='add'>+	p_attr-&gt;support_hevc10bit_enc = FIELD_GET(FEATURE_HEVC10BIT_ENC, hw_config_feature);</div><div class='add'>+	p_attr-&gt;support_avc10bit_enc = FIELD_GET(FEATURE_AVC10BIT_ENC, hw_config_feature);</div><div class='add'>+</div><div class='add'>+	p_attr-&gt;support_decoders = FIELD_GET(FEATURE_AVC_DECODER, hw_config_def1) &lt;&lt; STD_AVC;</div><div class='add'>+	p_attr-&gt;support_decoders |= FIELD_GET(FEATURE_HEVC_DECODER, hw_config_def1) &lt;&lt; STD_HEVC;</div><div class='add'>+	p_attr-&gt;support_encoders = FIELD_GET(FEATURE_AVC_ENCODER, hw_config_def1) &lt;&lt; STD_AVC;</div><div class='add'>+	p_attr-&gt;support_encoders |= FIELD_GET(FEATURE_HEVC_ENCODER, hw_config_def1) &lt;&lt; STD_HEVC;</div><div class='add'>+</div><div class='add'>+	p_attr-&gt;support_backbone = FIELD_GET(FEATURE_BACKBONE, hw_config_def0);</div><div class='add'>+	p_attr-&gt;support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0);</div><div class='add'>+	p_attr-&gt;support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION);</div><div class='add'>+	if (revision) {</div><div class='add'>+		*revision = reg_val;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index)</div><div class='add'>+{</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index));</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_init(struct device *dev, u8 *fw, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct vpu_buf *common_vb;</div><div class='add'>+	dma_addr_t code_base, temp_base;</div><div class='add'>+	u32 code_size, temp_size;</div><div class='add'>+	u32 i, reg_val, reason_code;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	common_vb = &amp;vpu_dev-&gt;common_mem;</div><div class='add'>+</div><div class='add'>+	code_base = common_vb-&gt;daddr;</div><div class='add'>+	/* ALIGN TO 4KB */</div><div class='add'>+	code_size = (WAVE5_MAX_CODE_BUF_SIZE &amp; ~0xfff);</div><div class='add'>+	if (code_size &lt; size * 2)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	temp_base = common_vb-&gt;daddr + WAVE5_TEMPBUF_OFFSET;</div><div class='add'>+	temp_size = WAVE5_TEMPBUF_SIZE;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "VPU init, Writing firmware to common buffer, fail: %d\n",</div><div class='add'>+			ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_PO_CONF, 0);</div><div class='add'>+</div><div class='add'>+	/* clear registers */</div><div class='add'>+</div><div class='add'>+	for (i = W5_CMD_REG_BASE; i &lt; W5_CMD_REG_END; i += 4)</div><div class='add'>+		vpu_write_reg(vpu_dev, i, 0x00);</div><div class='add'>+</div><div class='add'>+	remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);</div><div class='add'>+	remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID &lt;&lt; 4) | 0);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);</div><div class='add'>+</div><div class='add'>+	/* These register must be reset explicitly */</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);</div><div class='add'>+	wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);</div><div class='add'>+	wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);</div><div class='add'>+</div><div class='add'>+	/* Encoder interrupt */</div><div class='add'>+	reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);</div><div class='add'>+	reg_val |= BIT(INT_WAVE5_ENC_PIC);</div><div class='add'>+	reg_val |= BIT(INT_WAVE5_BSBUF_FULL);</div><div class='add'>+	/* Decoder interrupt */</div><div class='add'>+	reg_val |= BIT(INT_WAVE5_INIT_SEQ);</div><div class='add'>+	reg_val |= BIT(INT_WAVE5_DEC_PIC);</div><div class='add'>+	reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);</div><div class='add'>+	if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {</div><div class='add'>+		reg_val = ((WAVE5_PROC_AXI_ID &lt;&lt; 28) |</div><div class='add'>+			   (WAVE5_PRP_AXI_ID &lt;&lt; 24) |</div><div class='add'>+			   (WAVE5_FBD_Y_AXI_ID &lt;&lt; 20) |</div><div class='add'>+			   (WAVE5_FBC_Y_AXI_ID &lt;&lt; 16) |</div><div class='add'>+			   (WAVE5_FBD_C_AXI_ID &lt;&lt; 12) |</div><div class='add'>+			   (WAVE5_FBC_C_AXI_ID &lt;&lt; 8) |</div><div class='add'>+			   (WAVE5_PRI_AXI_ID &lt;&lt; 4) |</div><div class='add'>+			   WAVE5_SEC_AXI_ID);</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);</div><div class='add'>+	ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &amp;reason_code);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return setup_wave5_properties(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_build_up_dec_param(struct vpu_instance *inst,</div><div class='add'>+				 struct dec_open_param *param)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;cycle_per_tick = 256;</div><div class='add'>+	if (vpu_dev-&gt;sram_buf.size) {</div><div class='add'>+		p_dec_info-&gt;sec_axi_info.use_bit_enable = 1;</div><div class='add'>+		p_dec_info-&gt;sec_axi_info.use_ip_enable = 1;</div><div class='add'>+		p_dec_info-&gt;sec_axi_info.use_lf_row_enable = 1;</div><div class='add'>+	}</div><div class='add'>+	switch (inst-&gt;std) {</div><div class='add'>+	case W_HEVC_DEC:</div><div class='add'>+		p_dec_info-&gt;seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC;</div><div class='add'>+		break;</div><div class='add'>+	case W_AVC_DEC:</div><div class='add'>+		p_dec_info-&gt;seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;vb_work.size = WAVE521DEC_WORKBUF_SIZE;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_work);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_VCORE_INFO, 1);</div><div class='add'>+</div><div class='add'>+	wave5_vdi_clear_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_work);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_ADDR_WORK_BASE, p_dec_info-&gt;vb_work.daddr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_WORK_SIZE, p_dec_info-&gt;vb_work.size);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ADDR_SEC_AXI, vpu_dev-&gt;sram_buf.daddr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_SEC_AXI_SIZE, vpu_dev-&gt;sram_buf.size);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info-&gt;stream_buf_start_addr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_BS_SIZE, p_dec_info-&gt;stream_buf_size);</div><div class='add'>+</div><div class='add'>+	/* NOTE: SDMA reads MSB first */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN);</div><div class='add'>+	/* This register must be reset explicitly */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_EXT_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1));</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;p_dec_info-&gt;vb_work);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;product_code = vpu_read_reg(inst-&gt;dev, W5_PRODUCT_NUMBER);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_hw_flush_instance(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	u32 instance_queue_count, report_queue_count;</div><div class='add'>+	u32 reg_val = 0;</div><div class='add'>+	u32 fail_res = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_FLUSH_INSTANCE, true, &amp;reg_val, &amp;fail_res);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+	if (instance_queue_count != 0 || report_queue_count != 0) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev,</div><div class='add'>+			 "FLUSH_INSTANCE cmd didn't reset the amount of queued commands &amp; reports");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* reset our local copy of the counts */</div><div class='add'>+	p_dec_info-&gt;instance_queue_count = 0;</div><div class='add'>+	p_dec_info-&gt;report_queue_count = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 get_bitstream_options(struct dec_info *info)</div><div class='add'>+{</div><div class='add'>+	u32 bs_option = BSOPTION_ENABLE_EXPLICIT_END;</div><div class='add'>+</div><div class='add'>+	if (info-&gt;stream_endflag)</div><div class='add'>+		bs_option |= BSOPTION_HIGHLIGHT_STREAM_END;</div><div class='add'>+	return bs_option;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_init_seq(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	u32 cmd_option = INIT_SEQ_NORMAL;</div><div class='add'>+	u32 reg_val, fail_res;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_RD_PTR, p_dec_info-&gt;stream_rd_ptr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_WR_PTR, p_dec_info-&gt;stream_wr_ptr);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_COMMAND_OPTION, cmd_option);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_USER_MASK, p_dec_info-&gt;user_data_enable);</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_INIT_SEQ, true, &amp;reg_val, &amp;fail_res);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_dec_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: init seq sent (queue %u : %u)\n", __func__,</div><div class='add'>+		p_dec_info-&gt;instance_queue_count, p_dec_info-&gt;report_queue_count);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	u32 profile_compatibility_flag;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;stream_rd_ptr = wave5_dec_get_rd_ptr(inst);</div><div class='add'>+	info-&gt;rd_ptr = p_dec_info-&gt;stream_rd_ptr;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;frame_display_flag = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DISP_IDC);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_PIC_SIZE);</div><div class='add'>+	info-&gt;pic_width = ((reg_val &gt;&gt; 16) &amp; 0xffff);</div><div class='add'>+	info-&gt;pic_height = (reg_val &amp; 0xffff);</div><div class='add'>+	info-&gt;min_frame_buffer_count = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_NUM_REQUIRED_FB);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_CROP_LEFT_RIGHT);</div><div class='add'>+	info-&gt;pic_crop_rect.left = (reg_val &gt;&gt; 16) &amp; 0xffff;</div><div class='add'>+	info-&gt;pic_crop_rect.right = reg_val &amp; 0xffff;</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_CROP_TOP_BOTTOM);</div><div class='add'>+	info-&gt;pic_crop_rect.top = (reg_val &gt;&gt; 16) &amp; 0xffff;</div><div class='add'>+	info-&gt;pic_crop_rect.bottom = reg_val &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_COLOR_SAMPLE_INFO);</div><div class='add'>+	info-&gt;luma_bitdepth = reg_val &amp; 0xf;</div><div class='add'>+	info-&gt;chroma_bitdepth = (reg_val &gt;&gt; 4) &amp; 0xf;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_SEQ_PARAM);</div><div class='add'>+	profile_compatibility_flag = (reg_val &gt;&gt; 12) &amp; 0xff;</div><div class='add'>+	info-&gt;profile = (reg_val &gt;&gt; 24) &amp; 0x1f;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_DEC) {</div><div class='add'>+		/* guessing profile */</div><div class='add'>+		if (!info-&gt;profile) {</div><div class='add'>+			if ((profile_compatibility_flag &amp; 0x06) == 0x06)</div><div class='add'>+				info-&gt;profile = HEVC_PROFILE_MAIN; /* main profile */</div><div class='add'>+			else if (profile_compatibility_flag &amp; 0x04)</div><div class='add'>+				info-&gt;profile = HEVC_PROFILE_MAIN10; /* main10 profile */</div><div class='add'>+			else if (profile_compatibility_flag &amp; 0x08)</div><div class='add'>+				/* main still picture profile */</div><div class='add'>+				info-&gt;profile = HEVC_PROFILE_STILLPICTURE;</div><div class='add'>+			else</div><div class='add'>+				info-&gt;profile = HEVC_PROFILE_MAIN; /* for old version HM */</div><div class='add'>+		}</div><div class='add'>+	} else if (inst-&gt;std == W_AVC_DEC) {</div><div class='add'>+		info-&gt;profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	info-&gt;vlc_buf_size = vpu_read_reg(inst-&gt;dev, W5_RET_VLC_BUF_SIZE);</div><div class='add'>+	info-&gt;param_buf_size = vpu_read_reg(inst-&gt;dev, W5_RET_PARAM_BUF_SIZE);</div><div class='add'>+	p_dec_info-&gt;vlc_buf_size = info-&gt;vlc_buf_size;</div><div class='add'>+	p_dec_info-&gt;param_buf_size = info-&gt;param_buf_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info-&gt;user_data_buf_addr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info-&gt;user_data_buf_size);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);</div><div class='add'>+</div><div class='add'>+	/* send QUERY cmd */</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, GET_RESULT);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_QUEUE_STATUS);</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_dec_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: init seq complete (queue %u : %u)\n", __func__,</div><div class='add'>+		p_dec_info-&gt;instance_queue_count, p_dec_info-&gt;report_queue_count);</div><div class='add'>+</div><div class='add'>+	/* this is not a fatal error, set ret to -EIO but don't return immediately */</div><div class='add'>+	if (vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DECODING_SUCCESS) != 1) {</div><div class='add'>+		info-&gt;seq_init_err_reason = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_ERR_INFO);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_get_dec_seq_result(inst, info);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr,</div><div class='add'>+				       enum tiled_map_type map_type, unsigned int count)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	struct dec_initial_info *init_info = &amp;p_dec_info-&gt;initial_info;</div><div class='add'>+	size_t remain, idx, j, i, cnt_8_chunk, size;</div><div class='add'>+	u32 start_no, end_no;</div><div class='add'>+	u32 reg_val, cbcr_interleave, nv21, pic_size;</div><div class='add'>+	u32 addr_y, addr_cb, addr_cr;</div><div class='add'>+	u32 mv_col_size, frame_width, frame_height, fbc_y_tbl_size, fbc_c_tbl_size;</div><div class='add'>+	struct vpu_buf vb_buf;</div><div class='add'>+	bool justified = WTL_RIGHT_JUSTIFIED;</div><div class='add'>+	u32 format_no = WTL_PIXEL_8BIT;</div><div class='add'>+	u32 color_format = 0;</div><div class='add'>+	u32 pixel_order = 1;</div><div class='add'>+	u32 bwb_flag = (map_type == LINEAR_FRAME_MAP) ? 1 : 0;</div><div class='add'>+</div><div class='add'>+	cbcr_interleave = inst-&gt;cbcr_interleave;</div><div class='add'>+	nv21 = inst-&gt;nv21;</div><div class='add'>+	mv_col_size = 0;</div><div class='add'>+	fbc_y_tbl_size = 0;</div><div class='add'>+	fbc_c_tbl_size = 0;</div><div class='add'>+</div><div class='add'>+	if (map_type &gt;= COMPRESSED_FRAME_MAP) {</div><div class='add'>+		cbcr_interleave = 0;</div><div class='add'>+		nv21 = 0;</div><div class='add'>+</div><div class='add'>+		switch (inst-&gt;std) {</div><div class='add'>+		case W_HEVC_DEC:</div><div class='add'>+			mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info-&gt;pic_width,</div><div class='add'>+							      init_info-&gt;pic_height);</div><div class='add'>+			break;</div><div class='add'>+		case W_AVC_DEC:</div><div class='add'>+			mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info-&gt;pic_width,</div><div class='add'>+							     init_info-&gt;pic_height);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;std == W_HEVC_DEC || inst-&gt;std == W_AVC_DEC) {</div><div class='add'>+			size = ALIGN(ALIGN(mv_col_size, 16), BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+			ret = wave5_vdi_allocate_array(inst-&gt;dev, p_dec_info-&gt;vb_mv, count, size);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto free_mv_buffers;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		frame_width = init_info-&gt;pic_width;</div><div class='add'>+		frame_height = init_info-&gt;pic_height;</div><div class='add'>+		fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(frame_width, frame_height), 16);</div><div class='add'>+		fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(frame_width, frame_height), 16);</div><div class='add'>+</div><div class='add'>+		size = ALIGN(fbc_y_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+		ret = wave5_vdi_allocate_array(inst-&gt;dev, p_dec_info-&gt;vb_fbc_y_tbl, count, size);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_fbc_y_tbl_buffers;</div><div class='add'>+</div><div class='add'>+		size = ALIGN(fbc_c_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+		ret = wave5_vdi_allocate_array(inst-&gt;dev, p_dec_info-&gt;vb_fbc_c_tbl, count, size);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_fbc_c_tbl_buffers;</div><div class='add'>+</div><div class='add'>+		pic_size = (init_info-&gt;pic_width &lt;&lt; 16) | (init_info-&gt;pic_height);</div><div class='add'>+</div><div class='add'>+		vb_buf.size = (p_dec_info-&gt;vlc_buf_size * VLC_BUF_NUM) +</div><div class='add'>+				(p_dec_info-&gt;param_buf_size * COMMAND_QUEUE_DEPTH);</div><div class='add'>+		vb_buf.daddr = 0;</div><div class='add'>+</div><div class='add'>+		if (vb_buf.size != p_dec_info-&gt;vb_task.size) {</div><div class='add'>+			wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_task);</div><div class='add'>+			ret = wave5_vdi_allocate_dma_memory(inst-&gt;dev, &amp;vb_buf);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto free_fbc_c_tbl_buffers;</div><div class='add'>+</div><div class='add'>+			p_dec_info-&gt;vb_task = vb_buf;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_SET_FB_ADDR_TASK_BUF,</div><div class='add'>+			      p_dec_info-&gt;vb_task.daddr);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size);</div><div class='add'>+	} else {</div><div class='add'>+		pic_size = (init_info-&gt;pic_width &lt;&lt; 16) | (init_info-&gt;pic_height);</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;output_format == FORMAT_422)</div><div class='add'>+			color_format = 1;</div><div class='add'>+	}</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_PIC_SIZE, pic_size);</div><div class='add'>+</div><div class='add'>+	reg_val = (bwb_flag &lt;&lt; 28) |</div><div class='add'>+		  (pixel_order &lt;&lt; 23) |</div><div class='add'>+		  (justified &lt;&lt; 22) |</div><div class='add'>+		  (format_no &lt;&lt; 20) |</div><div class='add'>+		  (color_format &lt;&lt; 19) |</div><div class='add'>+		  (nv21 &lt;&lt; 17) |</div><div class='add'>+		  (cbcr_interleave &lt;&lt; 16) |</div><div class='add'>+		  (fb_arr[0].stride);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_COMMON_PIC_INFO, reg_val);</div><div class='add'>+</div><div class='add'>+	remain = count;</div><div class='add'>+	cnt_8_chunk = DIV_ROUND_UP(count, 8);</div><div class='add'>+	idx = 0;</div><div class='add'>+	for (j = 0; j &lt; cnt_8_chunk; j++) {</div><div class='add'>+		reg_val = (j == cnt_8_chunk - 1) &lt;&lt; 4 | ((j == 0) &lt;&lt; 3);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_SFB_OPTION, reg_val);</div><div class='add'>+		start_no = j * 8;</div><div class='add'>+		end_no = start_no + ((remain &gt;= 8) ? 8 : remain) - 1;</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_SET_FB_NUM, (start_no &lt;&lt; 8) | end_no);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; 8 &amp;&amp; i &lt; remain; i++) {</div><div class='add'>+			addr_y = fb_arr[i + start_no].buf_y;</div><div class='add'>+			addr_cb = fb_arr[i + start_no].buf_cb;</div><div class='add'>+			addr_cr = fb_arr[i + start_no].buf_cr;</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_LUMA_BASE0 + (i &lt;&lt; 4), addr_y);</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_CB_BASE0 + (i &lt;&lt; 4), addr_cb);</div><div class='add'>+			if (map_type &gt;= COMPRESSED_FRAME_MAP) {</div><div class='add'>+				/* luma FBC offset table */</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_FBC_Y_OFFSET0 + (i &lt;&lt; 4),</div><div class='add'>+					      p_dec_info-&gt;vb_fbc_y_tbl[idx].daddr);</div><div class='add'>+				/* chroma FBC offset table */</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_FBC_C_OFFSET0 + (i &lt;&lt; 4),</div><div class='add'>+					      p_dec_info-&gt;vb_fbc_c_tbl[idx].daddr);</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_MV_COL0 + (i &lt;&lt; 2),</div><div class='add'>+					      p_dec_info-&gt;vb_mv[idx].daddr);</div><div class='add'>+			} else {</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_CR_BASE0 + (i &lt;&lt; 4), addr_cr);</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_FBC_C_OFFSET0 + (i &lt;&lt; 4), 0);</div><div class='add'>+				vpu_write_reg(inst-&gt;dev, W5_ADDR_MV_COL0 + (i &lt;&lt; 2), 0);</div><div class='add'>+			}</div><div class='add'>+			idx++;</div><div class='add'>+		}</div><div class='add'>+		remain -= i;</div><div class='add'>+</div><div class='add'>+		ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_buffers;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_SUCCESS);</div><div class='add'>+	if (!reg_val) {</div><div class='add'>+		ret = -EIO;</div><div class='add'>+		goto free_buffers;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_buffers:</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_task);</div><div class='add'>+free_fbc_c_tbl_buffers:</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_fbc_c_tbl[i]);</div><div class='add'>+free_fbc_y_tbl_buffers:</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_fbc_y_tbl[i]);</div><div class='add'>+free_mv_buffers:</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_mv[i]);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_RD_PTR, p_dec_info-&gt;stream_rd_ptr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_WR_PTR, p_dec_info-&gt;stream_wr_ptr);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));</div><div class='add'>+</div><div class='add'>+	/* secondary AXI */</div><div class='add'>+	reg_val = p_dec_info-&gt;sec_axi_info.use_bit_enable |</div><div class='add'>+		(p_dec_info-&gt;sec_axi_info.use_ip_enable &lt;&lt; 9) |</div><div class='add'>+		(p_dec_info-&gt;sec_axi_info.use_lf_row_enable &lt;&lt; 15);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_USE_SEC_AXI, reg_val);</div><div class='add'>+</div><div class='add'>+	/* set attributes of user buffer */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_USER_MASK, p_dec_info-&gt;user_data_enable);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1,</div><div class='add'>+		      (p_dec_info-&gt;target_spatial_id &lt;&lt; 9) |</div><div class='add'>+		      (p_dec_info-&gt;temp_id_select_mode &lt;&lt; 8) | p_dec_info-&gt;target_temp_id);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info-&gt;seq_change_mask);</div><div class='add'>+	/* When reordering is disabled we force the latency of the framebuffers */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info-&gt;reorder_enable);</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, &amp;reg_val, fail_res);</div><div class='add'>+	if (ret == -ETIMEDOUT)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_dec_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: dec pic sent (queue %u : %u)\n", __func__,</div><div class='add'>+		p_dec_info-&gt;instance_queue_count, p_dec_info-&gt;report_queue_count);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 index, nal_unit_type, reg_val, sub_layer_info;</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info-&gt;user_data_buf_addr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info-&gt;user_data_buf_size);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN);</div><div class='add'>+</div><div class='add'>+	/* send QUERY cmd */</div><div class='add'>+	ret = wave5_send_query(vpu_dev, inst, GET_RESULT);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_QUEUE_STATUS);</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_dec_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: dec pic complete (queue %u : %u)\n", __func__,</div><div class='add'>+		p_dec_info-&gt;instance_queue_count, p_dec_info-&gt;report_queue_count);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_PIC_TYPE);</div><div class='add'>+</div><div class='add'>+	nal_unit_type = (reg_val &gt;&gt; 4) &amp; 0x3f;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_DEC) {</div><div class='add'>+		if (reg_val &amp; 0x04)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_B;</div><div class='add'>+		else if (reg_val &amp; 0x02)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_P;</div><div class='add'>+		else if (reg_val &amp; 0x01)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_I;</div><div class='add'>+		else</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_MAX;</div><div class='add'>+		if ((nal_unit_type == 19 || nal_unit_type == 20) &amp;&amp; result-&gt;pic_type == PIC_TYPE_I)</div><div class='add'>+			/* IDR_W_RADL, IDR_N_LP */</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_IDR;</div><div class='add'>+	} else if (inst-&gt;std == W_AVC_DEC) {</div><div class='add'>+		if (reg_val &amp; 0x04)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_B;</div><div class='add'>+		else if (reg_val &amp; 0x02)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_P;</div><div class='add'>+		else if (reg_val &amp; 0x01)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_I;</div><div class='add'>+		else</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_MAX;</div><div class='add'>+		if (nal_unit_type == 5 &amp;&amp; result-&gt;pic_type == PIC_TYPE_I)</div><div class='add'>+			result-&gt;pic_type = PIC_TYPE_IDR;</div><div class='add'>+	}</div><div class='add'>+	index = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DISPLAY_INDEX);</div><div class='add'>+	result-&gt;index_frame_display = index;</div><div class='add'>+	index = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DECODED_INDEX);</div><div class='add'>+	result-&gt;index_frame_decoded = index;</div><div class='add'>+	result-&gt;index_frame_decoded_for_tiled = index;</div><div class='add'>+</div><div class='add'>+	sub_layer_info = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_SUB_LAYER_INFO);</div><div class='add'>+	result-&gt;temporal_id = sub_layer_info &amp; 0x7;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_DEC || inst-&gt;std == W_AVC_DEC) {</div><div class='add'>+		result-&gt;decoded_poc = -1;</div><div class='add'>+		if (result-&gt;index_frame_decoded &gt;= 0 ||</div><div class='add'>+		    result-&gt;index_frame_decoded == DECODED_IDX_FLAG_SKIP)</div><div class='add'>+			result-&gt;decoded_poc = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_PIC_POC);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	result-&gt;sequence_changed = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_NOTIFICATION);</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_PIC_SIZE);</div><div class='add'>+	result-&gt;dec_pic_width = reg_val &gt;&gt; 16;</div><div class='add'>+	result-&gt;dec_pic_height = reg_val &amp; 0xffff;</div><div class='add'>+</div><div class='add'>+	if (result-&gt;sequence_changed) {</div><div class='add'>+		memcpy((void *)&amp;p_dec_info-&gt;new_seq_info, (void *)&amp;p_dec_info-&gt;initial_info,</div><div class='add'>+		       sizeof(struct dec_initial_info));</div><div class='add'>+		wave5_get_dec_seq_result(inst, &amp;p_dec_info-&gt;new_seq_info);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	result-&gt;dec_host_cmd_tick = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_HOST_CMD_TICK);</div><div class='add'>+	result-&gt;dec_decode_end_tick = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DECODING_ENC_TICK);</div><div class='add'>+</div><div class='add'>+	if (!p_dec_info-&gt;first_cycle_check) {</div><div class='add'>+		result-&gt;frame_cycle =</div><div class='add'>+			(result-&gt;dec_decode_end_tick - result-&gt;dec_host_cmd_tick) *</div><div class='add'>+			p_dec_info-&gt;cycle_per_tick;</div><div class='add'>+		vpu_dev-&gt;last_performance_cycles = result-&gt;dec_decode_end_tick;</div><div class='add'>+		p_dec_info-&gt;first_cycle_check = true;</div><div class='add'>+	} else if (result-&gt;index_frame_decoded_for_tiled != -1) {</div><div class='add'>+		result-&gt;frame_cycle =</div><div class='add'>+			(result-&gt;dec_decode_end_tick - vpu_dev-&gt;last_performance_cycles) *</div><div class='add'>+			p_dec_info-&gt;cycle_per_tick;</div><div class='add'>+		vpu_dev-&gt;last_performance_cycles = result-&gt;dec_decode_end_tick;</div><div class='add'>+		if (vpu_dev-&gt;last_performance_cycles &lt; result-&gt;dec_host_cmd_tick)</div><div class='add'>+			result-&gt;frame_cycle =</div><div class='add'>+				(result-&gt;dec_decode_end_tick - result-&gt;dec_host_cmd_tick) *</div><div class='add'>+				p_dec_info-&gt;cycle_per_tick;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* no remaining command. reset frame cycle. */</div><div class='add'>+	if (p_dec_info-&gt;instance_queue_count == 0 &amp;&amp; p_dec_info-&gt;report_queue_count == 0)</div><div class='add'>+		p_dec_info-&gt;first_cycle_check = false;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct vpu_buf *common_vb;</div><div class='add'>+	dma_addr_t code_base, temp_base;</div><div class='add'>+	dma_addr_t old_code_base, temp_size;</div><div class='add'>+	u32 code_size, reason_code;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	common_vb = &amp;vpu_dev-&gt;common_mem;</div><div class='add'>+</div><div class='add'>+	code_base = common_vb-&gt;daddr;</div><div class='add'>+	/* ALIGN TO 4KB */</div><div class='add'>+	code_size = (WAVE5_MAX_CODE_BUF_SIZE &amp; ~0xfff);</div><div class='add'>+	if (code_size &lt; size * 2)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	temp_base = common_vb-&gt;daddr + WAVE5_TEMPBUF_OFFSET;</div><div class='add'>+	temp_size = WAVE5_TEMPBUF_SIZE;</div><div class='add'>+</div><div class='add'>+	old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR);</div><div class='add'>+</div><div class='add'>+	if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) {</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev,</div><div class='add'>+				"VPU init, Writing firmware to common buffer, fail: %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_PO_CONF, 0);</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev, "VPU init, Resetting the VPU, fail: %d\n", ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);</div><div class='add'>+		remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID &lt;&lt; 4) | 0);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size);</div><div class='add'>+</div><div class='add'>+		/* These register must be reset explicitly */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);</div><div class='add'>+</div><div class='add'>+		/* Encoder interrupt */</div><div class='add'>+		reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_ENC_PIC);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_BSBUF_FULL);</div><div class='add'>+		/* Decoder interrupt */</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_INIT_SEQ);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_DEC_PIC);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);</div><div class='add'>+</div><div class='add'>+		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);</div><div class='add'>+		if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {</div><div class='add'>+			reg_val = ((WAVE5_PROC_AXI_ID &lt;&lt; 28) |</div><div class='add'>+					(WAVE5_PRP_AXI_ID &lt;&lt; 24) |</div><div class='add'>+					(WAVE5_FBD_Y_AXI_ID &lt;&lt; 20) |</div><div class='add'>+					(WAVE5_FBC_Y_AXI_ID &lt;&lt; 16) |</div><div class='add'>+					(WAVE5_FBD_C_AXI_ID &lt;&lt; 12) |</div><div class='add'>+					(WAVE5_FBC_C_AXI_ID &lt;&lt; 8) |</div><div class='add'>+					(WAVE5_PRI_AXI_ID &lt;&lt; 4) |</div><div class='add'>+					WAVE5_SEC_AXI_ID);</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);</div><div class='add'>+</div><div class='add'>+		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &amp;reason_code);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return setup_wave5_properties(dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code,</div><div class='add'>+				size_t size)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct vpu_buf *common_vb;</div><div class='add'>+	dma_addr_t code_base;</div><div class='add'>+	u32 code_size, reason_code;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (i_sleep_wake) {</div><div class='add'>+		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * Declare who has ownership for the host interface access</div><div class='add'>+		 * 1 = VPU</div><div class='add'>+		 * 0 = Host processor</div><div class='add'>+		 */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU);</div><div class='add'>+		/* Send an interrupt named HOST to the VPU */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1);</div><div class='add'>+</div><div class='add'>+		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &amp;reason_code);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	} else { /* restore */</div><div class='add'>+		common_vb = &amp;vpu_dev-&gt;common_mem;</div><div class='add'>+</div><div class='add'>+		code_base = common_vb-&gt;daddr;</div><div class='add'>+		/* ALIGN TO 4KB */</div><div class='add'>+		code_size = (WAVE5_MAX_CODE_BUF_SIZE &amp; ~0xfff);</div><div class='add'>+		if (code_size &lt; size * 2) {</div><div class='add'>+			dev_err(dev, "size too small\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Power on without DEBUG mode */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_PO_CONF, 0);</div><div class='add'>+</div><div class='add'>+		remap_page(vpu_dev, code_base, W5_REMAP_INDEX0);</div><div class='add'>+		remap_page(vpu_dev, code_base, W5_REMAP_INDEX1);</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID &lt;&lt; 4) | 0);</div><div class='add'>+</div><div class='add'>+		/* These register must be reset explicitly */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_HW_OPTION, 0);</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0);</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);</div><div class='add'>+</div><div class='add'>+		/* Encoder interrupt */</div><div class='add'>+		reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_ENC_PIC);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_BSBUF_FULL);</div><div class='add'>+		/* Decoder interrupt */</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_INIT_SEQ);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_DEC_PIC);</div><div class='add'>+		reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);</div><div class='add'>+</div><div class='add'>+		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);</div><div class='add'>+		if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {</div><div class='add'>+			reg_val = ((WAVE5_PROC_AXI_ID &lt;&lt; 28) |</div><div class='add'>+					(WAVE5_PRP_AXI_ID &lt;&lt; 24) |</div><div class='add'>+					(WAVE5_FBD_Y_AXI_ID &lt;&lt; 20) |</div><div class='add'>+					(WAVE5_FBC_Y_AXI_ID &lt;&lt; 16) |</div><div class='add'>+					(WAVE5_FBD_C_AXI_ID &lt;&lt; 12) |</div><div class='add'>+					(WAVE5_FBC_C_AXI_ID &lt;&lt; 8) |</div><div class='add'>+					(WAVE5_PRI_AXI_ID &lt;&lt; 4) |</div><div class='add'>+					WAVE5_SEC_AXI_ID);</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1);</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU);</div><div class='add'>+		/* Start VPU after settings */</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1);</div><div class='add'>+</div><div class='add'>+		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		return wave5_vpu_firmware_command_queue_error_check(vpu_dev, &amp;reason_code);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode)</div><div class='add'>+{</div><div class='add'>+	u32 val = 0;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	struct vpu_attr *p_attr = &amp;vpu_dev-&gt;attr;</div><div class='add'>+	/* VPU doesn't send response. force to set BUSY flag to 0. */</div><div class='add'>+	vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0);</div><div class='add'>+</div><div class='add'>+	if (reset_mode == SW_RESET_SAFETY) {</div><div class='add'>+		ret = wave5_vpu_sleep_wake(dev, true, NULL, 0);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);</div><div class='add'>+	if ((val &gt;&gt; 16) &amp; 0x1)</div><div class='add'>+		p_attr-&gt;support_backbone = true;</div><div class='add'>+	if ((val &gt;&gt; 22) &amp; 0x1)</div><div class='add'>+		p_attr-&gt;support_vcore_backbone = true;</div><div class='add'>+	if ((val &gt;&gt; 28) &amp; 0x1)</div><div class='add'>+		p_attr-&gt;support_vcpu_backbone = true;</div><div class='add'>+</div><div class='add'>+	/* waiting for completion of bus transaction */</div><div class='add'>+	if (p_attr-&gt;support_backbone) {</div><div class='add'>+		dev_dbg(dev, "%s: backbone supported\n", __func__);</div><div class='add'>+</div><div class='add'>+		if (p_attr-&gt;support_vcore_backbone) {</div><div class='add'>+			if (p_attr-&gt;support_vcpu_backbone) {</div><div class='add'>+				/* step1 : disable request */</div><div class='add'>+				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF);</div><div class='add'>+</div><div class='add'>+				/* step2 : waiting for completion of bus transaction */</div><div class='add'>+				ret = wave5_wait_vcpu_bus_busy(vpu_dev,</div><div class='add'>+							       W5_BACKBONE_BUS_STATUS_VCPU);</div><div class='add'>+				if (ret) {</div><div class='add'>+					wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00);</div><div class='add'>+					return ret;</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+			/* step1 : disable request */</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7);</div><div class='add'>+</div><div class='add'>+			/* step2 : waiting for completion of bus transaction */</div><div class='add'>+			if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) {</div><div class='add'>+				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			}</div><div class='add'>+		} else {</div><div class='add'>+			/* step1 : disable request */</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7);</div><div class='add'>+</div><div class='add'>+			/* step2 : waiting for completion of bus transaction */</div><div class='add'>+			if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) {</div><div class='add'>+				wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);</div><div class='add'>+				return -EBUSY;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		dev_dbg(dev, "%s: backbone NOT supported\n", __func__);</div><div class='add'>+		/* step1 : disable request */</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100);</div><div class='add'>+</div><div class='add'>+		/* step2 : waiting for completion of bus transaction */</div><div class='add'>+		ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS);</div><div class='add'>+		if (ret) {</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (reset_mode) {</div><div class='add'>+	case SW_RESET_ON_BOOT:</div><div class='add'>+	case SW_RESET_FORCE:</div><div class='add'>+	case SW_RESET_SAFETY:</div><div class='add'>+		val = W5_RST_BLOCK_ALL;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (val) {</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val);</div><div class='add'>+</div><div class='add'>+		ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_RESET_STATUS);</div><div class='add'>+		if (ret) {</div><div class='add'>+			vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+		vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0);</div><div class='add'>+	}</div><div class='add'>+	/* step3 : must clear GDI_BUS_CTRL after done SW_RESET */</div><div class='add'>+	if (p_attr-&gt;support_backbone) {</div><div class='add'>+		if (p_attr-&gt;support_vcore_backbone) {</div><div class='add'>+			if (p_attr-&gt;support_vcpu_backbone)</div><div class='add'>+				wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00);</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00);</div><div class='add'>+		} else {</div><div class='add'>+			wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00);</div><div class='add'>+	}</div><div class='add'>+	if (reset_mode == SW_RESET_SAFETY || reset_mode == SW_RESET_FORCE)</div><div class='add'>+		ret = wave5_vpu_sleep_wake(dev, false, NULL, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;stream_endflag = eos ? 1 : 0;</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_BS_WR_PTR, p_dec_info-&gt;stream_wr_ptr);</div><div class='add'>+</div><div class='add'>+	return send_firmware_command(inst, W5_UPDATE_BS, true, NULL, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index));</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_SET_DISP_IDC, 0);</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, UPDATE_DISP_FLAG);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;frame_display_flag = vpu_read_reg(inst-&gt;dev, W5_RET_DEC_DISP_IDC);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_CLR_DISP_IDC, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index));</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, UPDATE_DISP_FLAG);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags)</div><div class='add'>+{</div><div class='add'>+	u32 interrupt_reason;</div><div class='add'>+</div><div class='add'>+	interrupt_reason = vpu_read_reg(inst-&gt;dev, W5_VPU_VINT_REASON_USR);</div><div class='add'>+	interrupt_reason &amp;= ~flags;</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_VPU_VINT_REASON_USR, interrupt_reason);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, GET_BS_RD_PTR);</div><div class='add'>+	if (ret)</div><div class='add'>+		return inst-&gt;codec_info-&gt;dec_info.stream_rd_ptr;</div><div class='add'>+</div><div class='add'>+	return vpu_read_reg(inst-&gt;dev, W5_RET_QUERY_DEC_BS_RD_PTR);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr);</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, SET_BS_RD_PTR);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER functions */</div><div class='add'>+/************************************************************************/</div><div class='add'>+</div><div class='add'>+int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,</div><div class='add'>+				 struct enc_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	dma_addr_t buffer_addr;</div><div class='add'>+	size_t buffer_size;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;cycle_per_tick = 256;</div><div class='add'>+	if (vpu_dev-&gt;sram_buf.size) {</div><div class='add'>+		p_enc_info-&gt;sec_axi_info.use_enc_rdo_enable = 1;</div><div class='add'>+		p_enc_info-&gt;sec_axi_info.use_enc_lf_enable = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;vb_work.size = WAVE521ENC_WORKBUF_SIZE;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_work);</div><div class='add'>+	if (ret) {</div><div class='add'>+		memset(&amp;p_enc_info-&gt;vb_work, 0, sizeof(p_enc_info-&gt;vb_work));</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_vdi_clear_memory(vpu_dev, &amp;p_enc_info-&gt;vb_work);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_ADDR_WORK_BASE, p_enc_info-&gt;vb_work.daddr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_WORK_SIZE, p_enc_info-&gt;vb_work.size);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ADDR_SEC_AXI, vpu_dev-&gt;sram_buf.daddr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_SEC_AXI_SIZE, vpu_dev-&gt;sram_buf.size);</div><div class='add'>+</div><div class='add'>+	reg_val = (open_param-&gt;line_buf_int_en &lt;&lt; 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN;</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_BS_PARAM, reg_val);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_EXT_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1));</div><div class='add'>+</div><div class='add'>+	/* This register must be reset explicitly */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SRC_OPTIONS, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_VCORE_INFO, 1);</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_vb_work;</div><div class='add'>+</div><div class='add'>+	buffer_addr = open_param-&gt;bitstream_buffer;</div><div class='add'>+	buffer_size = open_param-&gt;bitstream_buffer_size;</div><div class='add'>+	p_enc_info-&gt;stream_rd_ptr = buffer_addr;</div><div class='add'>+	p_enc_info-&gt;stream_wr_ptr = buffer_addr;</div><div class='add'>+	p_enc_info-&gt;line_buf_int_en = open_param-&gt;line_buf_int_en;</div><div class='add'>+	p_enc_info-&gt;stream_buf_start_addr = buffer_addr;</div><div class='add'>+	p_enc_info-&gt;stream_buf_size = buffer_size;</div><div class='add'>+	p_enc_info-&gt;stream_buf_end_addr = buffer_addr + buffer_size;</div><div class='add'>+	p_enc_info-&gt;stride = 0;</div><div class='add'>+	p_enc_info-&gt;initial_info_obtained = false;</div><div class='add'>+	p_enc_info-&gt;product_code = vpu_read_reg(inst-&gt;dev, W5_PRODUCT_NUMBER);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+free_vb_work:</div><div class='add'>+	if (wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_work))</div><div class='add'>+		memset(&amp;p_enc_info-&gt;vb_work, 0, sizeof(p_enc_info-&gt;vb_work));</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode,</div><div class='add'>+				    int src_width, int src_height)</div><div class='add'>+{</div><div class='add'>+	int aligned_width = (codec == W_HEVC_ENC) ? ALIGN(src_width, 32) : ALIGN(src_width, 16);</div><div class='add'>+	int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16);</div><div class='add'>+	int pad_right, pad_bot;</div><div class='add'>+	int crop_right, crop_left, crop_top, crop_bot;</div><div class='add'>+	int prp_mode = rot_mode &gt;&gt; 1; /* remove prp_enable bit */</div><div class='add'>+</div><div class='add'>+	if (codec == W_HEVC_ENC &amp;&amp;</div><div class='add'>+	    (!rot_mode || prp_mode == 14)) /* prp_mode 14 : hor_mir &amp;&amp; ver_mir &amp;&amp; rot_180 */</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pad_right = aligned_width - src_width;</div><div class='add'>+	pad_bot = aligned_height - src_height;</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_right &gt; 0)</div><div class='add'>+		crop_right = param-&gt;conf_win_right + pad_right;</div><div class='add'>+	else</div><div class='add'>+		crop_right = pad_right;</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_bot &gt; 0)</div><div class='add'>+		crop_bot = param-&gt;conf_win_bot + pad_bot;</div><div class='add'>+	else</div><div class='add'>+		crop_bot = pad_bot;</div><div class='add'>+</div><div class='add'>+	crop_top = param-&gt;conf_win_top;</div><div class='add'>+	crop_left = param-&gt;conf_win_left;</div><div class='add'>+</div><div class='add'>+	param-&gt;conf_win_top = crop_top;</div><div class='add'>+	param-&gt;conf_win_left = crop_left;</div><div class='add'>+	param-&gt;conf_win_bot = crop_bot;</div><div class='add'>+	param-&gt;conf_win_right = crop_right;</div><div class='add'>+</div><div class='add'>+	switch (prp_mode) {</div><div class='add'>+	case 0:</div><div class='add'>+		return;</div><div class='add'>+	case 1:</div><div class='add'>+	case 15:</div><div class='add'>+		param-&gt;conf_win_top = crop_right;</div><div class='add'>+		param-&gt;conf_win_left = crop_top;</div><div class='add'>+		param-&gt;conf_win_bot = crop_left;</div><div class='add'>+		param-&gt;conf_win_right = crop_bot;</div><div class='add'>+		break;</div><div class='add'>+	case 2:</div><div class='add'>+	case 12:</div><div class='add'>+		param-&gt;conf_win_top = crop_bot;</div><div class='add'>+		param-&gt;conf_win_left = crop_right;</div><div class='add'>+		param-&gt;conf_win_bot = crop_top;</div><div class='add'>+		param-&gt;conf_win_right = crop_left;</div><div class='add'>+		break;</div><div class='add'>+	case 3:</div><div class='add'>+	case 13:</div><div class='add'>+		param-&gt;conf_win_top = crop_left;</div><div class='add'>+		param-&gt;conf_win_left = crop_bot;</div><div class='add'>+		param-&gt;conf_win_bot = crop_right;</div><div class='add'>+		param-&gt;conf_win_right = crop_top;</div><div class='add'>+		break;</div><div class='add'>+	case 4:</div><div class='add'>+	case 10:</div><div class='add'>+		param-&gt;conf_win_top = crop_bot;</div><div class='add'>+		param-&gt;conf_win_bot = crop_top;</div><div class='add'>+		break;</div><div class='add'>+	case 8:</div><div class='add'>+	case 6:</div><div class='add'>+		param-&gt;conf_win_left = crop_right;</div><div class='add'>+		param-&gt;conf_win_right = crop_left;</div><div class='add'>+		break;</div><div class='add'>+	case 5:</div><div class='add'>+	case 11:</div><div class='add'>+		param-&gt;conf_win_top = crop_left;</div><div class='add'>+		param-&gt;conf_win_left = crop_top;</div><div class='add'>+		param-&gt;conf_win_bot = crop_right;</div><div class='add'>+		param-&gt;conf_win_right = crop_bot;</div><div class='add'>+		break;</div><div class='add'>+	case 7:</div><div class='add'>+	case 9:</div><div class='add'>+		param-&gt;conf_win_top = crop_right;</div><div class='add'>+		param-&gt;conf_win_left = crop_bot;</div><div class='add'>+		param-&gt;conf_win_bot = crop_left;</div><div class='add'>+		param-&gt;conf_win_right = crop_top;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_init_seq(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	struct enc_open_param *p_open_param = &amp;p_enc_info-&gt;open_param;</div><div class='add'>+	struct enc_wave_param *p_param = &amp;p_open_param-&gt;wave_param;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * OPT_COMMON:</div><div class='add'>+	 *	the last SET_PARAM command should be called with OPT_COMMON</div><div class='add'>+	 */</div><div class='add'>+	rot_mir_mode = 0;</div><div class='add'>+	if (p_enc_info-&gt;rotation_enable) {</div><div class='add'>+		switch (p_enc_info-&gt;rotation_angle) {</div><div class='add'>+		case 0:</div><div class='add'>+			rot_mir_mode |= NONE_ROTATE;</div><div class='add'>+			break;</div><div class='add'>+		case 90:</div><div class='add'>+			rot_mir_mode |= ROT_CLOCKWISE_90;</div><div class='add'>+			break;</div><div class='add'>+		case 180:</div><div class='add'>+			rot_mir_mode |= ROT_CLOCKWISE_180;</div><div class='add'>+			break;</div><div class='add'>+		case 270:</div><div class='add'>+			rot_mir_mode |= ROT_CLOCKWISE_270;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p_enc_info-&gt;mirror_enable) {</div><div class='add'>+		switch (p_enc_info-&gt;mirror_direction) {</div><div class='add'>+		case MIRDIR_NONE:</div><div class='add'>+			rot_mir_mode |= NONE_ROTATE;</div><div class='add'>+			break;</div><div class='add'>+		case MIRDIR_VER:</div><div class='add'>+			rot_mir_mode |= MIR_VER_FLIP;</div><div class='add'>+			break;</div><div class='add'>+		case MIRDIR_HOR:</div><div class='add'>+			rot_mir_mode |= MIR_HOR_FLIP;</div><div class='add'>+			break;</div><div class='add'>+		case MIRDIR_HOR_VER:</div><div class='add'>+			rot_mir_mode |= MIR_HOR_VER_FLIP;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_set_enc_crop_info(inst-&gt;std, p_param, rot_mir_mode, p_open_param-&gt;pic_width,</div><div class='add'>+				p_open_param-&gt;pic_height);</div><div class='add'>+</div><div class='add'>+	/* SET_PARAM + COMMON */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param-&gt;pic_height &lt;&lt; 16</div><div class='add'>+			| p_open_param-&gt;pic_width);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN);</div><div class='add'>+</div><div class='add'>+	reg_val = p_param-&gt;profile |</div><div class='add'>+		(p_param-&gt;level &lt;&lt; 3) |</div><div class='add'>+		(p_param-&gt;internal_bit_depth &lt;&lt; 14);</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC)</div><div class='add'>+		reg_val |= (p_param-&gt;tier &lt;&lt; 12) |</div><div class='add'>+			(p_param-&gt;tmvp_enable &lt;&lt; 23) |</div><div class='add'>+			(p_param-&gt;sao_enable &lt;&lt; 24) |</div><div class='add'>+			(p_param-&gt;skip_intra_trans &lt;&lt; 25) |</div><div class='add'>+			(p_param-&gt;strong_intra_smooth_enable &lt;&lt; 27) |</div><div class='add'>+			(p_param-&gt;en_still_picture &lt;&lt; 30);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val);</div><div class='add'>+</div><div class='add'>+	reg_val = (p_param-&gt;lossless_enable) |</div><div class='add'>+		(p_param-&gt;const_intra_pred_flag &lt;&lt; 1) |</div><div class='add'>+		(p_param-&gt;lf_cross_slice_boundary_enable &lt;&lt; 2) |</div><div class='add'>+		(p_param-&gt;wpp_enable &lt;&lt; 4) |</div><div class='add'>+		(p_param-&gt;disable_deblk &lt;&lt; 5) |</div><div class='add'>+		((p_param-&gt;beta_offset_div2 &amp; 0xF) &lt;&lt; 6) |</div><div class='add'>+		((p_param-&gt;tc_offset_div2 &amp; 0xF) &lt;&lt; 10) |</div><div class='add'>+		((p_param-&gt;chroma_cb_qp_offset &amp; 0x1F) &lt;&lt; 14) |</div><div class='add'>+		((p_param-&gt;chroma_cr_qp_offset &amp; 0x1F) &lt;&lt; 19) |</div><div class='add'>+		(p_param-&gt;transform8x8_enable &lt;&lt; 29) |</div><div class='add'>+		(p_param-&gt;entropy_coding_mode &lt;&lt; 30);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param-&gt;gop_preset_idx);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_AVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param-&gt;intra_qp |</div><div class='add'>+				((p_param-&gt;intra_period &amp; 0x7ff) &lt;&lt; 6) |</div><div class='add'>+				((p_param-&gt;avc_idr_period &amp; 0x7ff) &lt;&lt; 17));</div><div class='add'>+	else if (inst-&gt;std == W_HEVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INTRA_PARAM,</div><div class='add'>+			      p_param-&gt;decoding_refresh_type | (p_param-&gt;intra_qp &lt;&lt; 3) |</div><div class='add'>+				(p_param-&gt;intra_period &lt;&lt; 16));</div><div class='add'>+</div><div class='add'>+	reg_val = (p_param-&gt;rdo_skip &lt;&lt; 2) |</div><div class='add'>+		(p_param-&gt;lambda_scaling_enable &lt;&lt; 3) |</div><div class='add'>+		(fixed_cu_size_mode &lt;&lt; 5) |</div><div class='add'>+		(p_param-&gt;intra_nx_n_enable &lt;&lt; 8) |</div><div class='add'>+		(p_param-&gt;max_num_merge &lt;&lt; 18);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_AVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,</div><div class='add'>+			      p_param-&gt;intra_mb_refresh_arg &lt;&lt; 16 | p_param-&gt;intra_mb_refresh_mode);</div><div class='add'>+	else if (inst-&gt;std == W_HEVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INTRA_REFRESH,</div><div class='add'>+			      p_param-&gt;intra_refresh_arg &lt;&lt; 16 | p_param-&gt;intra_refresh_mode);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param-&gt;frame_rate_info);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param-&gt;bit_rate);</div><div class='add'>+</div><div class='add'>+	reg_val = p_open_param-&gt;rc_enable |</div><div class='add'>+		(p_param-&gt;hvs_qp_enable &lt;&lt; 2) |</div><div class='add'>+		(p_param-&gt;hvs_qp_scale &lt;&lt; 4) |</div><div class='add'>+		((p_param-&gt;initial_rc_qp &amp; 0x3F) &lt;&lt; 14) |</div><div class='add'>+		(p_open_param-&gt;vbv_buffer_size &lt;&lt; 20);</div><div class='add'>+	if (inst-&gt;std == W_AVC_ENC)</div><div class='add'>+		reg_val |= (p_param-&gt;mb_level_rc_enable &lt;&lt; 1);</div><div class='add'>+	else if (inst-&gt;std == W_HEVC_ENC)</div><div class='add'>+		reg_val |= (p_param-&gt;cu_level_rc_enable &lt;&lt; 1);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM,</div><div class='add'>+		      p_param-&gt;rc_weight_buf &lt;&lt; 8 | p_param-&gt;rc_weight_param);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param-&gt;min_qp_i |</div><div class='add'>+		      (p_param-&gt;max_qp_i &lt;&lt; 6) | (p_param-&gt;hvs_max_delta_qp &lt;&lt; 12));</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param-&gt;min_qp_p |</div><div class='add'>+		      (p_param-&gt;max_qp_p &lt;&lt; 6) | (p_param-&gt;min_qp_b &lt;&lt; 12) |</div><div class='add'>+		      (p_param-&gt;max_qp_b &lt;&lt; 18));</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_BG_PARAM, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT,</div><div class='add'>+		      p_param-&gt;conf_win_bot &lt;&lt; 16 | p_param-&gt;conf_win_top);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT,</div><div class='add'>+		      p_param-&gt;conf_win_right &lt;&lt; 16 | p_param-&gt;conf_win_left);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_AVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,</div><div class='add'>+			      p_param-&gt;avc_slice_arg &lt;&lt; 16 | p_param-&gt;avc_slice_mode);</div><div class='add'>+	else if (inst-&gt;std == W_HEVC_ENC)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE,</div><div class='add'>+			      p_param-&gt;independ_slice_mode_arg &lt;&lt; 16 |</div><div class='add'>+			      p_param-&gt;independ_slice_mode);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC) {</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE,</div><div class='add'>+			      p_param-&gt;depend_slice_mode_arg &lt;&lt; 16 | p_param-&gt;depend_slice_mode);</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_NR_PARAM, 0);</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_NR_WEIGHT,</div><div class='add'>+			      p_param-&gt;nr_intra_weight_y |</div><div class='add'>+			      (p_param-&gt;nr_intra_weight_cb &lt;&lt; 5) |</div><div class='add'>+			      (p_param-&gt;nr_intra_weight_cr &lt;&lt; 10) |</div><div class='add'>+			      (p_param-&gt;nr_inter_weight_y &lt;&lt; 15) |</div><div class='add'>+			      (p_param-&gt;nr_inter_weight_cb &lt;&lt; 20) |</div><div class='add'>+			      (p_param-&gt;nr_inter_weight_cr &lt;&lt; 25));</div><div class='add'>+	}</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0);</div><div class='add'>+</div><div class='add'>+	return send_firmware_command(inst, W5_ENC_SET_PARAM, true, NULL, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+</div><div class='add'>+	/* send QUERY cmd */</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, GET_RESULT);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: init seq\n", __func__);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_QUEUE_STATUS);</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_enc_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	if (vpu_read_reg(inst-&gt;dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) {</div><div class='add'>+		info-&gt;seq_init_err_reason = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_ERR_INFO);</div><div class='add'>+		ret = -EIO;</div><div class='add'>+	} else {</div><div class='add'>+		info-&gt;warn_info = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_WARN_INFO);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	info-&gt;min_frame_buffer_count = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_NUM_REQUIRED_FB);</div><div class='add'>+	info-&gt;min_src_frame_count = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_MIN_SRC_BUF_NUM);</div><div class='add'>+	info-&gt;vlc_buf_size = vpu_read_reg(inst-&gt;dev, W5_RET_VLC_BUF_SIZE);</div><div class='add'>+	info-&gt;param_buf_size = vpu_read_reg(inst-&gt;dev, W5_RET_PARAM_BUF_SIZE);</div><div class='add'>+	p_enc_info-&gt;vlc_buf_size = info-&gt;vlc_buf_size;</div><div class='add'>+	p_enc_info-&gt;param_buf_size = info-&gt;param_buf_size;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 calculate_luma_stride(u32 width, u32 bit_depth)</div><div class='add'>+{</div><div class='add'>+	return ALIGN(ALIGN(width, 16) * ((bit_depth &gt; 8) ? 5 : 4), 32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 calculate_chroma_stride(u32 width, u32 bit_depth)</div><div class='add'>+{</div><div class='add'>+	return ALIGN(ALIGN(width / 2, 16) * ((bit_depth &gt; 8) ? 5 : 4), 32);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,</div><div class='add'>+				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,</div><div class='add'>+				       unsigned int count)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u32 stride;</div><div class='add'>+	u32 start_no, end_no;</div><div class='add'>+	size_t remain, idx, j, i, cnt_8_chunk;</div><div class='add'>+	u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size;</div><div class='add'>+	u32 sub_sampled_size = 0;</div><div class='add'>+	u32 luma_stride, chroma_stride;</div><div class='add'>+	u32 buf_height = 0, buf_width = 0;</div><div class='add'>+	u32 bit_depth;</div><div class='add'>+	bool avc_encoding = (inst-&gt;std == W_AVC_ENC);</div><div class='add'>+	struct vpu_buf vb_mv = {0};</div><div class='add'>+	struct vpu_buf vb_fbc_y_tbl = {0};</div><div class='add'>+	struct vpu_buf vb_fbc_c_tbl = {0};</div><div class='add'>+	struct vpu_buf vb_sub_sam_buf = {0};</div><div class='add'>+	struct vpu_buf vb_task = {0};</div><div class='add'>+	struct enc_open_param *p_open_param;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+</div><div class='add'>+	p_open_param = &amp;p_enc_info-&gt;open_param;</div><div class='add'>+	mv_col_size = 0;</div><div class='add'>+	fbc_y_tbl_size = 0;</div><div class='add'>+	fbc_c_tbl_size = 0;</div><div class='add'>+	stride = p_enc_info-&gt;stride;</div><div class='add'>+	bit_depth = p_open_param-&gt;wave_param.internal_bit_depth;</div><div class='add'>+</div><div class='add'>+	if (avc_encoding) {</div><div class='add'>+		buf_width = ALIGN(p_open_param-&gt;pic_width, 16);</div><div class='add'>+		buf_height = ALIGN(p_open_param-&gt;pic_height, 16);</div><div class='add'>+</div><div class='add'>+		if ((p_enc_info-&gt;rotation_angle || p_enc_info-&gt;mirror_direction) &amp;&amp;</div><div class='add'>+		    !(p_enc_info-&gt;rotation_angle == 180 &amp;&amp;</div><div class='add'>+					p_enc_info-&gt;mirror_direction == MIRDIR_HOR_VER)) {</div><div class='add'>+			buf_width = ALIGN(p_open_param-&gt;pic_width, 16);</div><div class='add'>+			buf_height = ALIGN(p_open_param-&gt;pic_height, 16);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p_enc_info-&gt;rotation_angle == 90 || p_enc_info-&gt;rotation_angle == 270) {</div><div class='add'>+			buf_width = ALIGN(p_open_param-&gt;pic_height, 16);</div><div class='add'>+			buf_height = ALIGN(p_open_param-&gt;pic_width, 16);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		buf_width = ALIGN(p_open_param-&gt;pic_width, 8);</div><div class='add'>+		buf_height = ALIGN(p_open_param-&gt;pic_height, 8);</div><div class='add'>+</div><div class='add'>+		if ((p_enc_info-&gt;rotation_angle || p_enc_info-&gt;mirror_direction) &amp;&amp;</div><div class='add'>+		    !(p_enc_info-&gt;rotation_angle == 180 &amp;&amp;</div><div class='add'>+					p_enc_info-&gt;mirror_direction == MIRDIR_HOR_VER)) {</div><div class='add'>+			buf_width = ALIGN(p_open_param-&gt;pic_width, 32);</div><div class='add'>+			buf_height = ALIGN(p_open_param-&gt;pic_height, 32);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (p_enc_info-&gt;rotation_angle == 90 || p_enc_info-&gt;rotation_angle == 270) {</div><div class='add'>+			buf_width = ALIGN(p_open_param-&gt;pic_height, 32);</div><div class='add'>+			buf_height = ALIGN(p_open_param-&gt;pic_width, 32);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pic_size = (buf_width &lt;&lt; 16) | buf_height;</div><div class='add'>+</div><div class='add'>+	if (avc_encoding) {</div><div class='add'>+		mv_col_size = WAVE5_ENC_AVC_BUF_SIZE(buf_width, buf_height);</div><div class='add'>+		vb_mv.daddr = 0;</div><div class='add'>+		vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+	} else {</div><div class='add'>+		mv_col_size = WAVE5_ENC_HEVC_BUF_SIZE(buf_width, buf_height);</div><div class='add'>+		mv_col_size = ALIGN(mv_col_size, 16);</div><div class='add'>+		vb_mv.daddr = 0;</div><div class='add'>+		vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_mv);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;vb_mv = vb_mv;</div><div class='add'>+</div><div class='add'>+	fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(buf_width, buf_height), 16);</div><div class='add'>+	fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(buf_width, buf_height), 16);</div><div class='add'>+</div><div class='add'>+	vb_fbc_y_tbl.daddr = 0;</div><div class='add'>+	vb_fbc_y_tbl.size = ALIGN(fbc_y_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_fbc_y_tbl);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_vb_fbc_y_tbl;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;vb_fbc_y_tbl = vb_fbc_y_tbl;</div><div class='add'>+</div><div class='add'>+	vb_fbc_c_tbl.daddr = 0;</div><div class='add'>+	vb_fbc_c_tbl.size = ALIGN(fbc_c_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_fbc_c_tbl);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_vb_fbc_c_tbl;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;vb_fbc_c_tbl = vb_fbc_c_tbl;</div><div class='add'>+</div><div class='add'>+	if (avc_encoding)</div><div class='add'>+		sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE_AVC(buf_width, buf_height);</div><div class='add'>+	else</div><div class='add'>+		sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE(buf_width, buf_height);</div><div class='add'>+	vb_sub_sam_buf.size = ALIGN(sub_sampled_size * count, BUFFER_MARGIN) + BUFFER_MARGIN;</div><div class='add'>+	vb_sub_sam_buf.daddr = 0;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_sub_sam_buf);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_vb_sam_buf;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;vb_sub_sam_buf = vb_sub_sam_buf;</div><div class='add'>+</div><div class='add'>+	vb_task.size = (p_enc_info-&gt;vlc_buf_size * VLC_BUF_NUM) +</div><div class='add'>+			(p_enc_info-&gt;param_buf_size * COMMAND_QUEUE_DEPTH);</div><div class='add'>+	vb_task.daddr = 0;</div><div class='add'>+	if (p_enc_info-&gt;vb_task.size == 0) {</div><div class='add'>+		ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_task);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_vb_task;</div><div class='add'>+</div><div class='add'>+		p_enc_info-&gt;vb_task = vb_task;</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_SET_FB_ADDR_TASK_BUF,</div><div class='add'>+			      p_enc_info-&gt;vb_task.daddr);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set sub-sampled buffer base addr */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr);</div><div class='add'>+	/* set sub-sampled buffer size for one frame */</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_PIC_SIZE, pic_size);</div><div class='add'>+</div><div class='add'>+	/* set stride of luma/chroma for compressed buffer */</div><div class='add'>+	if ((p_enc_info-&gt;rotation_angle || p_enc_info-&gt;mirror_direction) &amp;&amp;</div><div class='add'>+	    !(p_enc_info-&gt;rotation_angle == 180 &amp;&amp;</div><div class='add'>+	    p_enc_info-&gt;mirror_direction == MIRDIR_HOR_VER)) {</div><div class='add'>+		luma_stride = calculate_luma_stride(buf_width, bit_depth);</div><div class='add'>+		chroma_stride = calculate_chroma_stride(buf_width / 2, bit_depth);</div><div class='add'>+	} else {</div><div class='add'>+		luma_stride = calculate_luma_stride(p_open_param-&gt;pic_width, bit_depth);</div><div class='add'>+		chroma_stride = calculate_chroma_stride(p_open_param-&gt;pic_width / 2, bit_depth);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_FBC_STRIDE, luma_stride &lt;&lt; 16 | chroma_stride);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_COMMON_PIC_INFO, stride);</div><div class='add'>+</div><div class='add'>+	remain = count;</div><div class='add'>+	cnt_8_chunk = DIV_ROUND_UP(count, 8);</div><div class='add'>+	idx = 0;</div><div class='add'>+	for (j = 0; j &lt; cnt_8_chunk; j++) {</div><div class='add'>+		reg_val = (j == cnt_8_chunk - 1) &lt;&lt; 4 | ((j == 0) &lt;&lt; 3);</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_SFB_OPTION, reg_val);</div><div class='add'>+		start_no = j * 8;</div><div class='add'>+		end_no = start_no + ((remain &gt;= 8) ? 8 : remain) - 1;</div><div class='add'>+</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_SET_FB_NUM, (start_no &lt;&lt; 8) | end_no);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; 8 &amp;&amp; i &lt; remain; i++) {</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_LUMA_BASE0 + (i &lt;&lt; 4), fb_arr[i +</div><div class='add'>+					start_no].buf_y);</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_CB_BASE0 + (i &lt;&lt; 4),</div><div class='add'>+				      fb_arr[i + start_no].buf_cb);</div><div class='add'>+			/* luma FBC offset table */</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_FBC_Y_OFFSET0 + (i &lt;&lt; 4),</div><div class='add'>+				      vb_fbc_y_tbl.daddr + idx * fbc_y_tbl_size);</div><div class='add'>+			/* chroma FBC offset table */</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_FBC_C_OFFSET0 + (i &lt;&lt; 4),</div><div class='add'>+				      vb_fbc_c_tbl.daddr + idx * fbc_c_tbl_size);</div><div class='add'>+</div><div class='add'>+			vpu_write_reg(inst-&gt;dev, W5_ADDR_MV_COL0 + (i &lt;&lt; 2),</div><div class='add'>+				      vb_mv.daddr + idx * mv_col_size);</div><div class='add'>+			idx++;</div><div class='add'>+		}</div><div class='add'>+		remain -= i;</div><div class='add'>+</div><div class='add'>+		ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_vb_mem;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto free_vb_mem;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+free_vb_mem:</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vb_task);</div><div class='add'>+free_vb_task:</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vb_sub_sam_buf);</div><div class='add'>+free_vb_sam_buf:</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vb_fbc_c_tbl);</div><div class='add'>+free_vb_fbc_c_tbl:</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vb_fbc_y_tbl);</div><div class='add'>+free_vb_fbc_y_tbl:</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vb_mv);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	u32 src_frame_format;</div><div class='add'>+	u32 reg_val = 0;</div><div class='add'>+	u32 src_stride_c = 0;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	struct frame_buffer *p_src_frame = option-&gt;source_frame;</div><div class='add'>+	struct enc_open_param *p_open_param = &amp;p_enc_info-&gt;open_param;</div><div class='add'>+	bool justified = WTL_RIGHT_JUSTIFIED;</div><div class='add'>+	u32 format_no = WTL_PIXEL_8BIT;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_BS_START_ADDR, option-&gt;pic_stream_buffer_addr);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_BS_SIZE, option-&gt;pic_stream_buffer_size);</div><div class='add'>+	p_enc_info-&gt;stream_buf_start_addr = option-&gt;pic_stream_buffer_addr;</div><div class='add'>+	p_enc_info-&gt;stream_buf_size = option-&gt;pic_stream_buffer_size;</div><div class='add'>+	p_enc_info-&gt;stream_buf_end_addr =</div><div class='add'>+		option-&gt;pic_stream_buffer_addr + option-&gt;pic_stream_buffer_size;</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI);</div><div class='add'>+	/* secondary AXI */</div><div class='add'>+	reg_val = (p_enc_info-&gt;sec_axi_info.use_enc_rdo_enable &lt;&lt; 11) |</div><div class='add'>+		(p_enc_info-&gt;sec_axi_info.use_enc_lf_enable &lt;&lt; 15);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * CODEOPT_ENC_VCL is used to implicitly encode header/headers to generate bitstream.</div><div class='add'>+	 * (use ENC_PUT_VIDEO_HEADER for give_command to encode only a header)</div><div class='add'>+	 */</div><div class='add'>+	if (option-&gt;code_option.implicit_header_encode)</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_CODE_OPTION,</div><div class='add'>+			      CODEOPT_ENC_HEADER_IMPLICIT | CODEOPT_ENC_VCL |</div><div class='add'>+			      (option-&gt;code_option.encode_aud &lt;&lt; 5) |</div><div class='add'>+			      (option-&gt;code_option.encode_eos &lt;&lt; 6) |</div><div class='add'>+			      (option-&gt;code_option.encode_eob &lt;&lt; 7));</div><div class='add'>+	else</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_CODE_OPTION,</div><div class='add'>+			      option-&gt;code_option.implicit_header_encode |</div><div class='add'>+			      (option-&gt;code_option.encode_vcl &lt;&lt; 1) |</div><div class='add'>+			      (option-&gt;code_option.encode_vps &lt;&lt; 2) |</div><div class='add'>+			      (option-&gt;code_option.encode_sps &lt;&lt; 3) |</div><div class='add'>+			      (option-&gt;code_option.encode_pps &lt;&lt; 4) |</div><div class='add'>+			      (option-&gt;code_option.encode_aud &lt;&lt; 5) |</div><div class='add'>+			      (option-&gt;code_option.encode_eos &lt;&lt; 6) |</div><div class='add'>+			      (option-&gt;code_option.encode_eob &lt;&lt; 7));</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_PIC_PARAM, 0);</div><div class='add'>+</div><div class='add'>+	if (option-&gt;src_end_flag)</div><div class='add'>+		/* no more source images. */</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF);</div><div class='add'>+	else</div><div class='add'>+		vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option-&gt;src_idx);</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame-&gt;buf_y);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame-&gt;buf_cb);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame-&gt;buf_cr);</div><div class='add'>+</div><div class='add'>+	switch (p_open_param-&gt;src_format) {</div><div class='add'>+	case FORMAT_420:</div><div class='add'>+	case FORMAT_422:</div><div class='add'>+	case FORMAT_YUYV:</div><div class='add'>+	case FORMAT_YVYU:</div><div class='add'>+	case FORMAT_UYVY:</div><div class='add'>+	case FORMAT_VYUY:</div><div class='add'>+		justified = WTL_LEFT_JUSTIFIED;</div><div class='add'>+		format_no = WTL_PIXEL_8BIT;</div><div class='add'>+		src_stride_c = inst-&gt;cbcr_interleave ? p_src_frame-&gt;stride :</div><div class='add'>+			(p_src_frame-&gt;stride / 2);</div><div class='add'>+		src_stride_c = (p_open_param-&gt;src_format == FORMAT_422) ? src_stride_c * 2 :</div><div class='add'>+			src_stride_c;</div><div class='add'>+		break;</div><div class='add'>+	case FORMAT_420_P10_16BIT_MSB:</div><div class='add'>+	case FORMAT_422_P10_16BIT_MSB:</div><div class='add'>+	case FORMAT_YUYV_P10_16BIT_MSB:</div><div class='add'>+	case FORMAT_YVYU_P10_16BIT_MSB:</div><div class='add'>+	case FORMAT_UYVY_P10_16BIT_MSB:</div><div class='add'>+	case FORMAT_VYUY_P10_16BIT_MSB:</div><div class='add'>+		justified = WTL_RIGHT_JUSTIFIED;</div><div class='add'>+		format_no = WTL_PIXEL_16BIT;</div><div class='add'>+		src_stride_c = inst-&gt;cbcr_interleave ? p_src_frame-&gt;stride :</div><div class='add'>+			(p_src_frame-&gt;stride / 2);</div><div class='add'>+		src_stride_c = (p_open_param-&gt;src_format ==</div><div class='add'>+				FORMAT_422_P10_16BIT_MSB) ? src_stride_c * 2 : src_stride_c;</div><div class='add'>+		break;</div><div class='add'>+	case FORMAT_420_P10_16BIT_LSB:</div><div class='add'>+	case FORMAT_422_P10_16BIT_LSB:</div><div class='add'>+	case FORMAT_YUYV_P10_16BIT_LSB:</div><div class='add'>+	case FORMAT_YVYU_P10_16BIT_LSB:</div><div class='add'>+	case FORMAT_UYVY_P10_16BIT_LSB:</div><div class='add'>+	case FORMAT_VYUY_P10_16BIT_LSB:</div><div class='add'>+		justified = WTL_LEFT_JUSTIFIED;</div><div class='add'>+		format_no = WTL_PIXEL_16BIT;</div><div class='add'>+		src_stride_c = inst-&gt;cbcr_interleave ? p_src_frame-&gt;stride :</div><div class='add'>+			(p_src_frame-&gt;stride / 2);</div><div class='add'>+		src_stride_c = (p_open_param-&gt;src_format ==</div><div class='add'>+				FORMAT_422_P10_16BIT_LSB) ? src_stride_c * 2 : src_stride_c;</div><div class='add'>+		break;</div><div class='add'>+	case FORMAT_420_P10_32BIT_MSB:</div><div class='add'>+	case FORMAT_422_P10_32BIT_MSB:</div><div class='add'>+	case FORMAT_YUYV_P10_32BIT_MSB:</div><div class='add'>+	case FORMAT_YVYU_P10_32BIT_MSB:</div><div class='add'>+	case FORMAT_UYVY_P10_32BIT_MSB:</div><div class='add'>+	case FORMAT_VYUY_P10_32BIT_MSB:</div><div class='add'>+		justified = WTL_RIGHT_JUSTIFIED;</div><div class='add'>+		format_no = WTL_PIXEL_32BIT;</div><div class='add'>+		src_stride_c = inst-&gt;cbcr_interleave ? p_src_frame-&gt;stride :</div><div class='add'>+			ALIGN(p_src_frame-&gt;stride / 2, 16) * BIT(inst-&gt;cbcr_interleave);</div><div class='add'>+		src_stride_c = (p_open_param-&gt;src_format ==</div><div class='add'>+				FORMAT_422_P10_32BIT_MSB) ? src_stride_c * 2 : src_stride_c;</div><div class='add'>+		break;</div><div class='add'>+	case FORMAT_420_P10_32BIT_LSB:</div><div class='add'>+	case FORMAT_422_P10_32BIT_LSB:</div><div class='add'>+	case FORMAT_YUYV_P10_32BIT_LSB:</div><div class='add'>+	case FORMAT_YVYU_P10_32BIT_LSB:</div><div class='add'>+	case FORMAT_UYVY_P10_32BIT_LSB:</div><div class='add'>+	case FORMAT_VYUY_P10_32BIT_LSB:</div><div class='add'>+		justified = WTL_LEFT_JUSTIFIED;</div><div class='add'>+		format_no = WTL_PIXEL_32BIT;</div><div class='add'>+		src_stride_c = inst-&gt;cbcr_interleave ? p_src_frame-&gt;stride :</div><div class='add'>+			ALIGN(p_src_frame-&gt;stride / 2, 16) * BIT(inst-&gt;cbcr_interleave);</div><div class='add'>+		src_stride_c = (p_open_param-&gt;src_format ==</div><div class='add'>+				FORMAT_422_P10_32BIT_LSB) ? src_stride_c * 2 : src_stride_c;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	src_frame_format = (inst-&gt;cbcr_interleave &lt;&lt; 1) | (inst-&gt;nv21);</div><div class='add'>+	switch (p_open_param-&gt;packed_format) {</div><div class='add'>+	case PACKED_YUYV:</div><div class='add'>+		src_frame_format = 4;</div><div class='add'>+		break;</div><div class='add'>+	case PACKED_YVYU:</div><div class='add'>+		src_frame_format = 5;</div><div class='add'>+		break;</div><div class='add'>+	case PACKED_UYVY:</div><div class='add'>+		src_frame_format = 6;</div><div class='add'>+		break;</div><div class='add'>+	case PACKED_VYUY:</div><div class='add'>+		src_frame_format = 7;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_STRIDE,</div><div class='add'>+		      (p_src_frame-&gt;stride &lt;&lt; 16) | src_stride_c);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format |</div><div class='add'>+		      (format_no &lt;&lt; 3) | (justified &lt;&lt; 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN &lt;&lt; 6));</div><div class='add'>+</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0);</div><div class='add'>+	vpu_write_reg(inst-&gt;dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0);</div><div class='add'>+</div><div class='add'>+	ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, &amp;reg_val, fail_res);</div><div class='add'>+	if (ret == -ETIMEDOUT)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_enc_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	u32 encoding_success;</div><div class='add'>+	u32 reg_val;</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = wave5_send_query(inst-&gt;dev, inst, GET_RESULT);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: enc pic complete\n", __func__);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_QUEUE_STATUS);</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;instance_queue_count = (reg_val &gt;&gt; 16) &amp; 0xff;</div><div class='add'>+	p_enc_info-&gt;report_queue_count = (reg_val &amp; QUEUE_REPORT_MASK);</div><div class='add'>+</div><div class='add'>+	encoding_success = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_ENCODING_SUCCESS);</div><div class='add'>+	if (!encoding_success) {</div><div class='add'>+		result-&gt;error_reason = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_ERR_INFO);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	result-&gt;warn_info = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_WARN_INFO);</div><div class='add'>+</div><div class='add'>+	reg_val = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_PIC_TYPE);</div><div class='add'>+	result-&gt;pic_type = reg_val &amp; 0xFFFF;</div><div class='add'>+</div><div class='add'>+	result-&gt;enc_vcl_nut = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_VCL_NUT);</div><div class='add'>+	/*</div><div class='add'>+	 * To get the reconstructed frame use the following index on</div><div class='add'>+	 * inst-&gt;frame_buf</div><div class='add'>+	 */</div><div class='add'>+	result-&gt;recon_frame_index = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_PIC_IDX);</div><div class='add'>+	result-&gt;enc_pic_byte = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_PIC_BYTE);</div><div class='add'>+	result-&gt;enc_src_idx = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_USED_SRC_IDX);</div><div class='add'>+	p_enc_info-&gt;stream_wr_ptr = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_WR_PTR);</div><div class='add'>+	p_enc_info-&gt;stream_rd_ptr = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_RD_PTR);</div><div class='add'>+</div><div class='add'>+	result-&gt;bitstream_buffer = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_RD_PTR);</div><div class='add'>+	result-&gt;rd_ptr = p_enc_info-&gt;stream_rd_ptr;</div><div class='add'>+	result-&gt;wr_ptr = p_enc_info-&gt;stream_wr_ptr;</div><div class='add'>+</div><div class='add'>+	/*result for header only(no vcl) encoding */</div><div class='add'>+	if (result-&gt;recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY)</div><div class='add'>+		result-&gt;bitstream_size = result-&gt;enc_pic_byte;</div><div class='add'>+	else if (result-&gt;recon_frame_index &lt; 0)</div><div class='add'>+		result-&gt;bitstream_size = 0;</div><div class='add'>+	else</div><div class='add'>+		result-&gt;bitstream_size = result-&gt;enc_pic_byte;</div><div class='add'>+</div><div class='add'>+	result-&gt;enc_host_cmd_tick = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_HOST_CMD_TICK);</div><div class='add'>+	result-&gt;enc_encode_end_tick = vpu_read_reg(inst-&gt;dev, W5_RET_ENC_ENCODING_END_TICK);</div><div class='add'>+</div><div class='add'>+	if (!p_enc_info-&gt;first_cycle_check) {</div><div class='add'>+		result-&gt;frame_cycle = (result-&gt;enc_encode_end_tick - result-&gt;enc_host_cmd_tick) *</div><div class='add'>+			p_enc_info-&gt;cycle_per_tick;</div><div class='add'>+		p_enc_info-&gt;first_cycle_check = true;</div><div class='add'>+	} else {</div><div class='add'>+		result-&gt;frame_cycle =</div><div class='add'>+			(result-&gt;enc_encode_end_tick - vpu_dev-&gt;last_performance_cycles) *</div><div class='add'>+			p_enc_info-&gt;cycle_per_tick;</div><div class='add'>+		if (vpu_dev-&gt;last_performance_cycles &lt; result-&gt;enc_host_cmd_tick)</div><div class='add'>+			result-&gt;frame_cycle = (result-&gt;enc_encode_end_tick -</div><div class='add'>+					result-&gt;enc_host_cmd_tick) * p_enc_info-&gt;cycle_per_tick;</div><div class='add'>+	}</div><div class='add'>+	vpu_dev-&gt;last_performance_cycles = result-&gt;enc_encode_end_tick;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst,</div><div class='add'>+						   struct enc_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	bool low_delay = true;</div><div class='add'>+	struct enc_wave_param *param = &amp;open_param-&gt;wave_param;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	struct device *dev = vpu_dev-&gt;dev;</div><div class='add'>+	u32 num_ctu_row = (open_param-&gt;pic_height + 64 - 1) / 64;</div><div class='add'>+	u32 num_ctu_col = (open_param-&gt;pic_width + 64 - 1) / 64;</div><div class='add'>+	u32 ctu_sz = num_ctu_col * num_ctu_row;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC &amp;&amp; low_delay &amp;&amp;</div><div class='add'>+	    param-&gt;decoding_refresh_type == DEC_REFRESH_TYPE_CRA) {</div><div class='add'>+		dev_warn(dev,</div><div class='add'>+			 "dec_refresh_type(CRA) shouldn't be used together with low delay GOP\n");</div><div class='add'>+		dev_warn(dev, "Suggested configuration parameter: decoding refresh type (IDR)\n");</div><div class='add'>+		param-&gt;decoding_refresh_type = 2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;wpp_enable &amp;&amp; param-&gt;independ_slice_mode) {</div><div class='add'>+		unsigned int num_ctb_in_width = ALIGN(open_param-&gt;pic_width, 64) &gt;&gt; 6;</div><div class='add'>+</div><div class='add'>+		if (param-&gt;independ_slice_mode_arg % num_ctb_in_width) {</div><div class='add'>+			dev_err(dev, "independ_slice_mode_arg %u must be a multiple of %u\n",</div><div class='add'>+				param-&gt;independ_slice_mode_arg, num_ctb_in_width);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* multi-slice &amp; wpp */</div><div class='add'>+	if (param-&gt;wpp_enable &amp;&amp; param-&gt;depend_slice_mode) {</div><div class='add'>+		dev_err(dev, "wpp_enable &amp;&amp; depend_slice_mode cannot be used simultaneously\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!param-&gt;independ_slice_mode &amp;&amp; param-&gt;depend_slice_mode) {</div><div class='add'>+		dev_err(dev, "depend_slice_mode requires independ_slice_mode\n");</div><div class='add'>+		return false;</div><div class='add'>+	} else if (param-&gt;independ_slice_mode &amp;&amp;</div><div class='add'>+		   param-&gt;depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED &amp;&amp;</div><div class='add'>+		   param-&gt;independ_slice_mode_arg &lt; param-&gt;depend_slice_mode_arg) {</div><div class='add'>+		dev_err(dev, "independ_slice_mode_arg: %u must be smaller than %u\n",</div><div class='add'>+			param-&gt;independ_slice_mode_arg, param-&gt;depend_slice_mode_arg);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;independ_slice_mode &amp;&amp; param-&gt;independ_slice_mode_arg &gt; 65535) {</div><div class='add'>+		dev_err(dev, "independ_slice_mode_arg: %u must be smaller than 65535\n",</div><div class='add'>+			param-&gt;independ_slice_mode_arg);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;depend_slice_mode &amp;&amp; param-&gt;depend_slice_mode_arg &gt; 65535) {</div><div class='add'>+		dev_err(dev, "depend_slice_mode_arg: %u must be smaller than 65535\n",</div><div class='add'>+			param-&gt;depend_slice_mode_arg);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_top % 2) {</div><div class='add'>+		dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param-&gt;conf_win_top);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_bot % 2) {</div><div class='add'>+		dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param-&gt;conf_win_bot);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_left % 2) {</div><div class='add'>+		dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param-&gt;conf_win_left);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;conf_win_right % 2) {</div><div class='add'>+		dev_err(dev, "conf_win_right: %u, Must be a multiple of 2\n",</div><div class='add'>+			param-&gt;conf_win_right);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;lossless_enable &amp;&amp; open_param-&gt;rc_enable) {</div><div class='add'>+		dev_err(dev, "option rate_control cannot be used with lossless_coding\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;lossless_enable &amp;&amp; !param-&gt;skip_intra_trans) {</div><div class='add'>+		dev_err(dev, "option intra_trans_skip must be enabled with lossless_coding\n");</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* intra refresh */</div><div class='add'>+	if (param-&gt;intra_refresh_mode &amp;&amp; param-&gt;intra_refresh_arg == 0) {</div><div class='add'>+		dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u must be &gt; 0\n",</div><div class='add'>+			param-&gt;intra_refresh_mode, param-&gt;intra_refresh_arg);</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+	switch (param-&gt;intra_refresh_mode) {</div><div class='add'>+	case REFRESH_MODE_CTU_ROWS:</div><div class='add'>+		if (param-&gt;intra_mb_refresh_arg &gt; num_ctu_row)</div><div class='add'>+			goto invalid_refresh_argument;</div><div class='add'>+		break;</div><div class='add'>+	case REFRESH_MODE_CTU_COLUMNS:</div><div class='add'>+		if (param-&gt;intra_refresh_arg &gt; num_ctu_col)</div><div class='add'>+			goto invalid_refresh_argument;</div><div class='add'>+		break;</div><div class='add'>+	case REFRESH_MODE_CTU_STEP_SIZE:</div><div class='add'>+		if (param-&gt;intra_refresh_arg &gt; ctu_sz)</div><div class='add'>+			goto invalid_refresh_argument;</div><div class='add'>+		break;</div><div class='add'>+	case REFRESH_MODE_CTUS:</div><div class='add'>+		if (param-&gt;intra_refresh_arg &gt; ctu_sz)</div><div class='add'>+			goto invalid_refresh_argument;</div><div class='add'>+		if (param-&gt;lossless_enable) {</div><div class='add'>+			dev_err(dev, "mode: %u cannot be used lossless_enable",</div><div class='add'>+				param-&gt;intra_refresh_mode);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	};</div><div class='add'>+	return true;</div><div class='add'>+</div><div class='add'>+invalid_refresh_argument:</div><div class='add'>+	dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u &gt; W(%u)xH(%u)\n",</div><div class='add'>+		param-&gt;intra_refresh_mode, param-&gt;intra_refresh_arg,</div><div class='add'>+		num_ctu_row, num_ctu_col);</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev,</div><div class='add'>+					    struct enc_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	struct enc_wave_param *param = &amp;open_param-&gt;wave_param;</div><div class='add'>+</div><div class='add'>+	if (open_param-&gt;rc_enable) {</div><div class='add'>+		if (param-&gt;min_qp_i &gt; param-&gt;max_qp_i || param-&gt;min_qp_p &gt; param-&gt;max_qp_p ||</div><div class='add'>+		    param-&gt;min_qp_b &gt; param-&gt;max_qp_b) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev, "Configuration failed because min_qp is greater than max_qp\n");</div><div class='add'>+			dev_err(vpu_dev-&gt;dev, "Suggested configuration parameters: min_qp = max_qp\n");</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (open_param-&gt;bit_rate &lt;= (int)open_param-&gt;frame_rate_info) {</div><div class='add'>+			dev_err(vpu_dev-&gt;dev,</div><div class='add'>+				"enc_bit_rate: %u must be greater than the frame_rate: %u\n",</div><div class='add'>+				open_param-&gt;bit_rate, (int)open_param-&gt;frame_rate_info);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	u32 pic_width;</div><div class='add'>+	u32 pic_height;</div><div class='add'>+	s32 product_id = inst-&gt;dev-&gt;product;</div><div class='add'>+	struct vpu_attr *p_attr = &amp;inst-&gt;dev-&gt;attr;</div><div class='add'>+	struct enc_wave_param *param;</div><div class='add'>+</div><div class='add'>+	if (!open_param)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	param = &amp;open_param-&gt;wave_param;</div><div class='add'>+	pic_width = open_param-&gt;pic_width;</div><div class='add'>+	pic_height = open_param-&gt;pic_height;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;id &gt;= MAX_NUM_INSTANCE) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Too many simultaneous instances: %d (max: %u)\n",</div><div class='add'>+			inst-&gt;id, MAX_NUM_INSTANCE);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std != W_HEVC_ENC &amp;&amp;</div><div class='add'>+	    !(inst-&gt;std == W_AVC_ENC &amp;&amp; product_id == PRODUCT_ID_521)) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Unsupported encoder-codec &amp; product combination\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;internal_bit_depth == 10) {</div><div class='add'>+		if (inst-&gt;std == W_HEVC_ENC &amp;&amp; !p_attr-&gt;support_hevc10bit_enc) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Flag support_hevc10bit_enc must be set to encode 10bit HEVC\n");</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		} else if (inst-&gt;std == W_AVC_ENC &amp;&amp; !p_attr-&gt;support_avc10bit_enc) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Flag support_avc10bit_enc must be set to encode 10bit AVC\n");</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!open_param-&gt;frame_rate_info) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "No frame rate information.\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (open_param-&gt;bit_rate &gt; MAX_BIT_RATE) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n",</div><div class='add'>+			open_param-&gt;bit_rate, MAX_BIT_RATE);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pic_width &lt; W5_MIN_ENC_PIC_WIDTH || pic_width &gt; W5_MAX_ENC_PIC_WIDTH ||</div><div class='add'>+	    pic_height &lt; W5_MIN_ENC_PIC_HEIGHT || pic_height &gt; W5_MAX_ENC_PIC_HEIGHT) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Invalid encoding dimension: %ux%u\n",</div><div class='add'>+			pic_width, pic_height);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;profile) {</div><div class='add'>+		if (inst-&gt;std == W_HEVC_ENC) {</div><div class='add'>+			if ((param-&gt;profile != HEVC_PROFILE_MAIN ||</div><div class='add'>+			     (param-&gt;profile == HEVC_PROFILE_MAIN &amp;&amp;</div><div class='add'>+			      param-&gt;internal_bit_depth &gt; 8)) &amp;&amp;</div><div class='add'>+			    (param-&gt;profile != HEVC_PROFILE_MAIN10 ||</div><div class='add'>+			     (param-&gt;profile == HEVC_PROFILE_MAIN10 &amp;&amp;</div><div class='add'>+			      param-&gt;internal_bit_depth &lt; 10)) &amp;&amp;</div><div class='add'>+			    param-&gt;profile != HEVC_PROFILE_STILLPICTURE) {</div><div class='add'>+				dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+					"Invalid HEVC encoding profile: %u (bit-depth: %u)\n",</div><div class='add'>+					param-&gt;profile, param-&gt;internal_bit_depth);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		} else if (inst-&gt;std == W_AVC_ENC) {</div><div class='add'>+			if ((param-&gt;internal_bit_depth &gt; 8 &amp;&amp;</div><div class='add'>+			     param-&gt;profile != H264_PROFILE_HIGH10)) {</div><div class='add'>+				dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+					"Invalid AVC encoding profile: %u (bit-depth: %u)\n",</div><div class='add'>+					param-&gt;profile, param-&gt;internal_bit_depth);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;decoding_refresh_type &gt; DEC_REFRESH_TYPE_IDR) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Invalid decoding refresh type: %u (valid: 0-2)\n",</div><div class='add'>+			param-&gt;decoding_refresh_type);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;intra_refresh_mode &gt; REFRESH_MODE_CTUS) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Invalid intra refresh mode: %d (valid: 0-4)\n",</div><div class='add'>+			param-&gt;intra_refresh_mode);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC &amp;&amp; param-&gt;independ_slice_mode &amp;&amp;</div><div class='add'>+	    param-&gt;depend_slice_mode &gt; DEPEND_SLICE_MODE_BOOST) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Can't combine slice modes: independent and fast dependent for HEVC\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!param-&gt;disable_deblk) {</div><div class='add'>+		if (param-&gt;beta_offset_div2 &lt; -6 || param-&gt;beta_offset_div2 &gt; 6) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "Invalid beta offset: %d (valid: -6-6)\n",</div><div class='add'>+				param-&gt;beta_offset_div2);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (param-&gt;tc_offset_div2 &lt; -6 || param-&gt;tc_offset_div2 &gt; 6) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "Invalid tc offset: %d (valid: -6-6)\n",</div><div class='add'>+				param-&gt;tc_offset_div2);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;intra_qp &gt; MAX_INTRA_QP) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Invalid intra quantization parameter: %u (valid: 0-%u)\n",</div><div class='add'>+			param-&gt;intra_qp, MAX_INTRA_QP);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (open_param-&gt;rc_enable) {</div><div class='add'>+		if (param-&gt;min_qp_i &gt; MAX_INTRA_QP || param-&gt;max_qp_i &gt; MAX_INTRA_QP ||</div><div class='add'>+		    param-&gt;min_qp_p &gt; MAX_INTRA_QP || param-&gt;max_qp_p &gt; MAX_INTRA_QP ||</div><div class='add'>+		    param-&gt;min_qp_b &gt; MAX_INTRA_QP || param-&gt;max_qp_b &gt; MAX_INTRA_QP) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Invalid quantization parameter min/max values: "</div><div class='add'>+				"I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n",</div><div class='add'>+				param-&gt;min_qp_i, param-&gt;max_qp_i, param-&gt;min_qp_p, param-&gt;max_qp_p,</div><div class='add'>+				param-&gt;min_qp_b, param-&gt;max_qp_b, MAX_INTRA_QP);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (param-&gt;hvs_qp_enable &amp;&amp; param-&gt;hvs_max_delta_qp &gt; MAX_HVS_MAX_DELTA_QP) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n",</div><div class='add'>+				param-&gt;hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (open_param-&gt;vbv_buffer_size &lt; MIN_VBV_BUFFER_SIZE ||</div><div class='add'>+		    open_param-&gt;vbv_buffer_size &gt; MAX_VBV_BUFFER_SIZE) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "VBV buffer size: %u (valid: %u-%u)\n",</div><div class='add'>+				open_param-&gt;vbv_buffer_size, MIN_VBV_BUFFER_SIZE,</div><div class='add'>+				MAX_VBV_BUFFER_SIZE);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_enc_check_common_param_valid(inst, open_param))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_enc_check_param_valid(inst-&gt;dev, open_param))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (param-&gt;chroma_cb_qp_offset &lt; -12 || param-&gt;chroma_cb_qp_offset &gt; 12) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n",</div><div class='add'>+			param-&gt;chroma_cb_qp_offset);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;chroma_cr_qp_offset &lt; -12 || param-&gt;chroma_cr_qp_offset &gt; 12) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n",</div><div class='add'>+			param-&gt;chroma_cr_qp_offset);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE &amp;&amp; !param-&gt;intra_refresh_arg) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Intra refresh mode CTU step-size requires an argument\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC) {</div><div class='add'>+		if (param-&gt;nr_intra_weight_y &gt; MAX_INTRA_WEIGHT ||</div><div class='add'>+		    param-&gt;nr_intra_weight_cb &gt; MAX_INTRA_WEIGHT ||</div><div class='add'>+		    param-&gt;nr_intra_weight_cr &gt; MAX_INTRA_WEIGHT) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Invalid intra weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n",</div><div class='add'>+				param-&gt;nr_intra_weight_y, param-&gt;nr_intra_weight_cb,</div><div class='add'>+				param-&gt;nr_intra_weight_cr, MAX_INTRA_WEIGHT);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (param-&gt;nr_inter_weight_y &gt; MAX_INTER_WEIGHT ||</div><div class='add'>+		    param-&gt;nr_inter_weight_cb &gt; MAX_INTER_WEIGHT ||</div><div class='add'>+		    param-&gt;nr_inter_weight_cr &gt; MAX_INTER_WEIGHT) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Invalid inter weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n",</div><div class='add'>+				param-&gt;nr_inter_weight_y, param-&gt;nr_inter_weight_cb,</div><div class='add'>+				param-&gt;nr_inter_weight_cr, MAX_INTER_WEIGHT);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h<br/>new file mode 100644<br/>index 000000000000..a15c6b2c3d8b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-regdefine.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-regdefine.h</a></div><div class='hunk'>@@ -0,0 +1,732 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - wave5 register definitions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __WAVE5_REGISTER_DEFINE_H__</div><div class='add'>+#define __WAVE5_REGISTER_DEFINE_H__</div><div class='add'>+</div><div class='add'>+enum W5_VPU_COMMAND {</div><div class='add'>+	W5_INIT_VPU		= 0x0001,</div><div class='add'>+	W5_WAKEUP_VPU		= 0x0002,</div><div class='add'>+	W5_SLEEP_VPU		= 0x0004,</div><div class='add'>+	W5_CREATE_INSTANCE	= 0x0008,       /* queuing command */</div><div class='add'>+	W5_FLUSH_INSTANCE	= 0x0010,</div><div class='add'>+	W5_DESTROY_INSTANCE	= 0x0020,       /* queuing command */</div><div class='add'>+	W5_INIT_SEQ		= 0x0040,       /* queuing command */</div><div class='add'>+	W5_SET_FB		= 0x0080,</div><div class='add'>+	W5_DEC_ENC_PIC		= 0x0100,       /* queuing command */</div><div class='add'>+	W5_ENC_SET_PARAM	= 0x0200,	/* queuing command */</div><div class='add'>+	W5_QUERY		= 0x4000,</div><div class='add'>+	W5_UPDATE_BS		= 0x8000,</div><div class='add'>+	W5_MAX_VPU_COMD		= 0x10000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum query_opt {</div><div class='add'>+	GET_VPU_INFO		= 0,</div><div class='add'>+	SET_WRITE_PROT		= 1,</div><div class='add'>+	GET_RESULT		= 2,</div><div class='add'>+	UPDATE_DISP_FLAG	= 3,</div><div class='add'>+	GET_BW_REPORT		= 4,</div><div class='add'>+	GET_BS_RD_PTR		= 5,		/* for decoder */</div><div class='add'>+	GET_BS_WR_PTR		= 6,		/* for encoder */</div><div class='add'>+	GET_SRC_BUF_FLAG	= 7,		/* for encoder */</div><div class='add'>+	SET_BS_RD_PTR		= 8,		/* for decoder */</div><div class='add'>+	GET_DEBUG_INFO		= 0x61,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define W5_REG_BASE                     0x00000000</div><div class='add'>+#define W5_CMD_REG_BASE                 0x00000100</div><div class='add'>+#define W5_CMD_REG_END                  0x00000200</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * COMMON</div><div class='add'>+ *</div><div class='add'>+ * ----</div><div class='add'>+ *</div><div class='add'>+ * Power on configuration</div><div class='add'>+ * PO_DEBUG_MODE    [0]     1 - power on with debug mode</div><div class='add'>+ * USE_PO_CONF      [3]     1 - use power-on-configuration</div><div class='add'>+ */</div><div class='add'>+#define W5_PO_CONF                     (W5_REG_BASE + 0x0000)</div><div class='add'>+#define W5_VCPU_CUR_PC                 (W5_REG_BASE + 0x0004)</div><div class='add'>+#define W5_VCPU_CUR_LR                 (W5_REG_BASE + 0x0008)</div><div class='add'>+#define W5_VPU_PDBG_STEP_MASK_V        (W5_REG_BASE + 0x000C)</div><div class='add'>+#define W5_VPU_PDBG_CTRL               (W5_REG_BASE + 0x0010) /* v_cpu debugger ctrl register */</div><div class='add'>+#define W5_VPU_PDBG_IDX_REG            (W5_REG_BASE + 0x0014) /* v_cpu debugger index register */</div><div class='add'>+#define W5_VPU_PDBG_WDATA_REG          (W5_REG_BASE + 0x0018) /* v_cpu debugger write data reg */</div><div class='add'>+#define W5_VPU_PDBG_RDATA_REG          (W5_REG_BASE + 0x001C) /* v_cpu debugger read data reg */</div><div class='add'>+</div><div class='add'>+#define W5_VPU_FIO_CTRL_ADDR           (W5_REG_BASE + 0x0020)</div><div class='add'>+#define W5_VPU_FIO_DATA                (W5_REG_BASE + 0x0024)</div><div class='add'>+#define W5_VPU_VINT_REASON_USR         (W5_REG_BASE + 0x0030)</div><div class='add'>+#define W5_VPU_VINT_REASON_CLR         (W5_REG_BASE + 0x0034)</div><div class='add'>+#define W5_VPU_HOST_INT_REQ            (W5_REG_BASE + 0x0038)</div><div class='add'>+#define W5_VPU_VINT_CLEAR              (W5_REG_BASE + 0x003C)</div><div class='add'>+#define W5_VPU_HINT_CLEAR              (W5_REG_BASE + 0x0040)</div><div class='add'>+#define W5_VPU_VPU_INT_STS             (W5_REG_BASE + 0x0044)</div><div class='add'>+#define W5_VPU_VINT_ENABLE             (W5_REG_BASE + 0x0048)</div><div class='add'>+#define W5_VPU_VINT_REASON             (W5_REG_BASE + 0x004C)</div><div class='add'>+#define W5_VPU_RESET_REQ               (W5_REG_BASE + 0x0050)</div><div class='add'>+#define W5_RST_BLOCK_CCLK(_core)       BIT((_core))</div><div class='add'>+#define W5_RST_BLOCK_CCLK_ALL          (0xff)</div><div class='add'>+#define W5_RST_BLOCK_BCLK(_core)       (0x100 &lt;&lt; (_core))</div><div class='add'>+#define W5_RST_BLOCK_BCLK_ALL          (0xff00)</div><div class='add'>+#define W5_RST_BLOCK_ACLK(_core)       (0x10000 &lt;&lt; (_core))</div><div class='add'>+#define W5_RST_BLOCK_ACLK_ALL          (0xff0000)</div><div class='add'>+#define W5_RST_BLOCK_VCPU_ALL          (0x3f000000)</div><div class='add'>+#define W5_RST_BLOCK_ALL               (0x3fffffff)</div><div class='add'>+#define W5_VPU_RESET_STATUS            (W5_REG_BASE + 0x0054)</div><div class='add'>+</div><div class='add'>+#define W5_VCPU_RESTART                (W5_REG_BASE + 0x0058)</div><div class='add'>+#define W5_VPU_CLK_MASK                (W5_REG_BASE + 0x005C)</div><div class='add'>+</div><div class='add'>+/* REMAP_CTRL</div><div class='add'>+ * PAGE SIZE:   [8:0]   0x001 - 4K</div><div class='add'>+ *                      0x002 - 8K</div><div class='add'>+ *                      0x004 - 16K</div><div class='add'>+ *                      ...</div><div class='add'>+ *                      0x100 - 1M</div><div class='add'>+ * REGION ATTR1 [10]    0     - normal</div><div class='add'>+ *                      1     - make bus error for the region</div><div class='add'>+ * REGION ATTR2 [11]    0     - normal</div><div class='add'>+ *                      1     - bypass region</div><div class='add'>+ * REMAP INDEX  [15:12]       - 0 ~ 3</div><div class='add'>+ * ENDIAN       [19:16]       - NOTE: Currently not supported in this driver</div><div class='add'>+ * AXI-ID       [23:20]       - upper AXI-ID</div><div class='add'>+ * BUS_ERROR    [29]    0     - bypass</div><div class='add'>+ *                      1     - make BUS_ERROR for unmapped region</div><div class='add'>+ * BYPASS_ALL   [30]    1     - bypass all</div><div class='add'>+ * ENABLE       [31]    1     - update control register[30:16]</div><div class='add'>+ */</div><div class='add'>+#define W5_VPU_REMAP_CTRL                       (W5_REG_BASE + 0x0060)</div><div class='add'>+#define W5_VPU_REMAP_VADDR                      (W5_REG_BASE + 0x0064)</div><div class='add'>+#define W5_VPU_REMAP_PADDR                      (W5_REG_BASE + 0x0068)</div><div class='add'>+#define W5_VPU_REMAP_CORE_START                 (W5_REG_BASE + 0x006C)</div><div class='add'>+#define W5_VPU_BUSY_STATUS                      (W5_REG_BASE + 0x0070)</div><div class='add'>+#define W5_VPU_HALT_STATUS                      (W5_REG_BASE + 0x0074)</div><div class='add'>+#define W5_VPU_VCPU_STATUS                      (W5_REG_BASE + 0x0078)</div><div class='add'>+#define W5_VPU_RET_PRODUCT_VERSION              (W5_REG_BASE + 0x0094)</div><div class='add'>+/*</div><div class='add'>+ * assign vpu_config0          = {conf_map_converter_reg,      // [31]</div><div class='add'>+ * conf_map_converter_sig,         // [30]</div><div class='add'>+ * 8'd0,                        // [29:22]</div><div class='add'>+ * conf_std_switch_en,          // [21]</div><div class='add'>+ * conf_bg_detect,              // [20]</div><div class='add'>+ * conf_3dnr_en,                // [19]</div><div class='add'>+ * conf_one_axi_en,             // [18]</div><div class='add'>+ * conf_sec_axi_en,             // [17]</div><div class='add'>+ * conf_bus_info,               // [16]</div><div class='add'>+ * conf_afbc_en,                // [15]</div><div class='add'>+ * conf_afbc_version_id,        // [14:12]</div><div class='add'>+ * conf_fbc_en,                 // [11]</div><div class='add'>+ * conf_fbc_version_id,         // [10:08]</div><div class='add'>+ * conf_scaler_en,              // [07]</div><div class='add'>+ * conf_scaler_version_id,      // [06:04]</div><div class='add'>+ * conf_bwb_en,                 // [03]</div><div class='add'>+ * 3'd0};                       // [02:00]</div><div class='add'>+ */</div><div class='add'>+#define W5_VPU_RET_VPU_CONFIG0                  (W5_REG_BASE + 0x0098)</div><div class='add'>+/*</div><div class='add'>+ * assign vpu_config1          = {4'd0,                        // [31:28]</div><div class='add'>+ * conf_perf_timer_en,          // [27]</div><div class='add'>+ * conf_multi_core_en,          // [26]</div><div class='add'>+ * conf_gcu_en,                 // [25]</div><div class='add'>+ * conf_cu_report,              // [24]</div><div class='add'>+ * 4'd0,                        // [23:20]</div><div class='add'>+ * conf_vcore_id_3,             // [19]</div><div class='add'>+ * conf_vcore_id_2,             // [18]</div><div class='add'>+ * conf_vcore_id_1,             // [17]</div><div class='add'>+ * conf_vcore_id_0,             // [16]</div><div class='add'>+ * conf_bwb_opt,                // [15]</div><div class='add'>+ * 7'd0,                        // [14:08]</div><div class='add'>+ * conf_cod_std_en_reserved_7,  // [7]</div><div class='add'>+ * conf_cod_std_en_reserved_6,  // [6]</div><div class='add'>+ * conf_cod_std_en_reserved_5,  // [5]</div><div class='add'>+ * conf_cod_std_en_reserved_4,  // [4]</div><div class='add'>+ * conf_cod_std_en_reserved_3,  // [3]</div><div class='add'>+ * conf_cod_std_en_reserved_2,  // [2]</div><div class='add'>+ * conf_cod_std_en_vp9,         // [1]</div><div class='add'>+ * conf_cod_std_en_hevc};       // [0]</div><div class='add'>+ * }</div><div class='add'>+ */</div><div class='add'>+#define W5_VPU_RET_VPU_CONFIG1                  (W5_REG_BASE + 0x009C)</div><div class='add'>+</div><div class='add'>+#define W5_VPU_DBG_REG0							(W5_REG_BASE + 0x00f0)</div><div class='add'>+#define W5_VPU_DBG_REG1							(W5_REG_BASE + 0x00f4)</div><div class='add'>+#define W5_VPU_DBG_REG2							(W5_REG_BASE + 0x00f8)</div><div class='add'>+#define W5_VPU_DBG_REG3							(W5_REG_BASE + 0x00fc)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* PRODUCT INFORMATION                                                  */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_PRODUCT_NAME                        (W5_REG_BASE + 0x1040)</div><div class='add'>+#define W5_PRODUCT_NUMBER                      (W5_REG_BASE + 0x1044)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER/ENCODER COMMON                                               */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_COMMAND                              (W5_REG_BASE + 0x0100)</div><div class='add'>+#define W5_COMMAND_OPTION                       (W5_REG_BASE + 0x0104)</div><div class='add'>+#define W5_QUERY_OPTION                         (W5_REG_BASE + 0x0104)</div><div class='add'>+#define W5_RET_SUCCESS                          (W5_REG_BASE + 0x0108)</div><div class='add'>+#define W5_RET_FAIL_REASON                      (W5_REG_BASE + 0x010C)</div><div class='add'>+#define W5_RET_QUEUE_FAIL_REASON                (W5_REG_BASE + 0x0110)</div><div class='add'>+#define W5_CMD_INSTANCE_INFO                    (W5_REG_BASE + 0x0110)</div><div class='add'>+</div><div class='add'>+#define W5_RET_QUEUE_STATUS                     (W5_REG_BASE + 0x01E0)</div><div class='add'>+#define W5_RET_BS_EMPTY_INST                    (W5_REG_BASE + 0x01E4)</div><div class='add'>+#define W5_RET_QUEUE_CMD_DONE_INST              (W5_REG_BASE + 0x01E8)</div><div class='add'>+#define W5_RET_STAGE0_INSTANCE_INFO             (W5_REG_BASE + 0x01EC)</div><div class='add'>+#define W5_RET_STAGE1_INSTANCE_INFO             (W5_REG_BASE + 0x01F0)</div><div class='add'>+#define W5_RET_STAGE2_INSTANCE_INFO             (W5_REG_BASE + 0x01F4)</div><div class='add'>+</div><div class='add'>+#define W5_RET_SEQ_DONE_INSTANCE_INFO           (W5_REG_BASE + 0x01FC)</div><div class='add'>+</div><div class='add'>+#define W5_BS_OPTION                            (W5_REG_BASE + 0x0120)</div><div class='add'>+</div><div class='add'>+/* return info when QUERY (GET_RESULT) for en/decoder */</div><div class='add'>+#define W5_RET_VLC_BUF_SIZE                     (W5_REG_BASE + 0x01B0)</div><div class='add'>+/* return info when QUERY (GET_RESULT) for en/decoder */</div><div class='add'>+#define W5_RET_PARAM_BUF_SIZE                   (W5_REG_BASE + 0x01B4)</div><div class='add'>+</div><div class='add'>+/* set when SET_FB for en/decoder */</div><div class='add'>+#define W5_CMD_SET_FB_ADDR_TASK_BUF             (W5_REG_BASE + 0x01D4)</div><div class='add'>+#define W5_CMD_SET_FB_TASK_BUF_SIZE             (W5_REG_BASE + 0x01D8)</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* INIT_VPU - COMMON                                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* note: W5_ADDR_CODE_BASE should be aligned to 4KB */</div><div class='add'>+#define W5_ADDR_CODE_BASE                       (W5_REG_BASE + 0x0110)</div><div class='add'>+#define W5_CODE_SIZE                            (W5_REG_BASE + 0x0114)</div><div class='add'>+#define W5_CODE_PARAM                           (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_ADDR_TEMP_BASE                       (W5_REG_BASE + 0x011C)</div><div class='add'>+#define W5_TEMP_SIZE                            (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_HW_OPTION                            (W5_REG_BASE + 0x012C)</div><div class='add'>+#define W5_SEC_AXI_PARAM                        (W5_REG_BASE + 0x0180)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* CREATE_INSTANCE - COMMON                                             */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_ADDR_WORK_BASE                       (W5_REG_BASE + 0x0114)</div><div class='add'>+#define W5_WORK_SIZE                            (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_CMD_DEC_BS_START_ADDR                (W5_REG_BASE + 0x011C)</div><div class='add'>+#define W5_CMD_DEC_BS_SIZE                      (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_CMD_BS_PARAM                         (W5_REG_BASE + 0x0124)</div><div class='add'>+#define W5_CMD_ADDR_SEC_AXI                     (W5_REG_BASE + 0x0130)</div><div class='add'>+#define W5_CMD_SEC_AXI_SIZE                     (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_CMD_EXT_ADDR                         (W5_REG_BASE + 0x0138)</div><div class='add'>+#define W5_CMD_NUM_CQ_DEPTH_M1                  (W5_REG_BASE + 0x013C)</div><div class='add'>+#define W5_CMD_ERR_CONCEAL                      (W5_REG_BASE + 0x0140)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - INIT_SEQ                                                   */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_BS_RD_PTR                            (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_BS_WR_PTR                            (W5_REG_BASE + 0x011C)</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* SET_FRAME_BUF                                                        */</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* SET_FB_OPTION 0x00       REGISTER FRAMEBUFFERS</div><div class='add'>+ * 0x01       UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol)</div><div class='add'>+ */</div><div class='add'>+#define W5_SFB_OPTION                           (W5_REG_BASE + 0x0104)</div><div class='add'>+#define W5_COMMON_PIC_INFO                      (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_PIC_SIZE                             (W5_REG_BASE + 0x011C)</div><div class='add'>+#define W5_SET_FB_NUM                           (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_EXTRA_PIC_INFO                       (W5_REG_BASE + 0x0124)</div><div class='add'>+</div><div class='add'>+#define W5_ADDR_LUMA_BASE0                      (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_ADDR_CB_BASE0                        (W5_REG_BASE + 0x0138)</div><div class='add'>+#define W5_ADDR_CR_BASE0                        (W5_REG_BASE + 0x013C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET0                   (W5_REG_BASE + 0x013C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET0                   (W5_REG_BASE + 0x0140)</div><div class='add'>+#define W5_ADDR_LUMA_BASE1                      (W5_REG_BASE + 0x0144)</div><div class='add'>+#define W5_ADDR_CB_ADDR1                        (W5_REG_BASE + 0x0148)</div><div class='add'>+#define W5_ADDR_CR_ADDR1                        (W5_REG_BASE + 0x014C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET1                   (W5_REG_BASE + 0x014C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET1                   (W5_REG_BASE + 0x0150)</div><div class='add'>+#define W5_ADDR_LUMA_BASE2                      (W5_REG_BASE + 0x0154)</div><div class='add'>+#define W5_ADDR_CB_ADDR2                        (W5_REG_BASE + 0x0158)</div><div class='add'>+#define W5_ADDR_CR_ADDR2                        (W5_REG_BASE + 0x015C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET2                   (W5_REG_BASE + 0x015C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET2                   (W5_REG_BASE + 0x0160)</div><div class='add'>+#define W5_ADDR_LUMA_BASE3                      (W5_REG_BASE + 0x0164)</div><div class='add'>+#define W5_ADDR_CB_ADDR3                        (W5_REG_BASE + 0x0168)</div><div class='add'>+#define W5_ADDR_CR_ADDR3                        (W5_REG_BASE + 0x016C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET3                   (W5_REG_BASE + 0x016C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET3                   (W5_REG_BASE + 0x0170)</div><div class='add'>+#define W5_ADDR_LUMA_BASE4                      (W5_REG_BASE + 0x0174)</div><div class='add'>+#define W5_ADDR_CB_ADDR4                        (W5_REG_BASE + 0x0178)</div><div class='add'>+#define W5_ADDR_CR_ADDR4                        (W5_REG_BASE + 0x017C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET4                   (W5_REG_BASE + 0x017C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET4                   (W5_REG_BASE + 0x0180)</div><div class='add'>+#define W5_ADDR_LUMA_BASE5                      (W5_REG_BASE + 0x0184)</div><div class='add'>+#define W5_ADDR_CB_ADDR5                        (W5_REG_BASE + 0x0188)</div><div class='add'>+#define W5_ADDR_CR_ADDR5                        (W5_REG_BASE + 0x018C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET5                   (W5_REG_BASE + 0x018C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET5                   (W5_REG_BASE + 0x0190)</div><div class='add'>+#define W5_ADDR_LUMA_BASE6                      (W5_REG_BASE + 0x0194)</div><div class='add'>+#define W5_ADDR_CB_ADDR6                        (W5_REG_BASE + 0x0198)</div><div class='add'>+#define W5_ADDR_CR_ADDR6                        (W5_REG_BASE + 0x019C)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET6                   (W5_REG_BASE + 0x019C)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET6                   (W5_REG_BASE + 0x01A0)</div><div class='add'>+#define W5_ADDR_LUMA_BASE7                      (W5_REG_BASE + 0x01A4)</div><div class='add'>+#define W5_ADDR_CB_ADDR7                        (W5_REG_BASE + 0x01A8)</div><div class='add'>+#define W5_ADDR_CR_ADDR7                        (W5_REG_BASE + 0x01AC)</div><div class='add'>+/* compression offset table for luma */</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET7                   (W5_REG_BASE + 0x01AC)</div><div class='add'>+/* compression offset table for chroma */</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET7                   (W5_REG_BASE + 0x01B0)</div><div class='add'>+#define W5_ADDR_MV_COL0                         (W5_REG_BASE + 0x01B4)</div><div class='add'>+#define W5_ADDR_MV_COL1                         (W5_REG_BASE + 0x01B8)</div><div class='add'>+#define W5_ADDR_MV_COL2                         (W5_REG_BASE + 0x01BC)</div><div class='add'>+#define W5_ADDR_MV_COL3                         (W5_REG_BASE + 0x01C0)</div><div class='add'>+#define W5_ADDR_MV_COL4                         (W5_REG_BASE + 0x01C4)</div><div class='add'>+#define W5_ADDR_MV_COL5                         (W5_REG_BASE + 0x01C8)</div><div class='add'>+#define W5_ADDR_MV_COL6                         (W5_REG_BASE + 0x01CC)</div><div class='add'>+#define W5_ADDR_MV_COL7                         (W5_REG_BASE + 0x01D0)</div><div class='add'>+</div><div class='add'>+/* UPDATE_FB */</div><div class='add'>+/* CMD_SET_FB_STRIDE [15:0]     - FBC framebuffer stride</div><div class='add'>+ * [31:15]    - linear framebuffer stride</div><div class='add'>+ */</div><div class='add'>+#define W5_CMD_SET_FB_STRIDE                    (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_CMD_SET_FB_INDEX                     (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_ADDR_LUMA_BASE                       (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_ADDR_CB_BASE                         (W5_REG_BASE + 0x0138)</div><div class='add'>+#define W5_ADDR_CR_BASE                         (W5_REG_BASE + 0x013C)</div><div class='add'>+#define W5_ADDR_MV_COL                          (W5_REG_BASE + 0x0140)</div><div class='add'>+#define W5_ADDR_FBC_Y_BASE                      (W5_REG_BASE + 0x0144)</div><div class='add'>+#define W5_ADDR_FBC_C_BASE                      (W5_REG_BASE + 0x0148)</div><div class='add'>+#define W5_ADDR_FBC_Y_OFFSET                    (W5_REG_BASE + 0x014C)</div><div class='add'>+#define W5_ADDR_FBC_C_OFFSET                    (W5_REG_BASE + 0x0150)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - DEC_PIC                                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_DEC_VCORE_INFO                   (W5_REG_BASE + 0x0194)</div><div class='add'>+/* sequence change enable mask register</div><div class='add'>+ * CMD_SEQ_CHANGE_ENABLE_FLAG [5]   profile_idc</div><div class='add'>+ *                            [16]  pic_width/height_in_luma_sample</div><div class='add'>+ *                            [19]  sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase</div><div class='add'>+ */</div><div class='add'>+#define W5_CMD_SEQ_CHANGE_ENABLE_FLAG           (W5_REG_BASE + 0x0128)</div><div class='add'>+#define W5_CMD_DEC_USER_MASK                    (W5_REG_BASE + 0x012C)</div><div class='add'>+#define W5_CMD_DEC_TEMPORAL_ID_PLUS1            (W5_REG_BASE + 0x0130)</div><div class='add'>+#define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1       (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_USE_SEC_AXI                          (W5_REG_BASE + 0x0150)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - QUERY : GET_VPU_INFO                                       */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_FW_VERSION                       (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_RET_PRODUCT_NAME                     (W5_REG_BASE + 0x011C)</div><div class='add'>+#define W5_RET_PRODUCT_VERSION                  (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_RET_STD_DEF0                         (W5_REG_BASE + 0x0124)</div><div class='add'>+#define W5_RET_STD_DEF1                         (W5_REG_BASE + 0x0128)</div><div class='add'>+#define W5_RET_CONF_FEATURE                     (W5_REG_BASE + 0x012C)</div><div class='add'>+#define W5_RET_CONF_DATE                        (W5_REG_BASE + 0x0130)</div><div class='add'>+#define W5_RET_CONF_REVISION                    (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_RET_CONF_TYPE                        (W5_REG_BASE + 0x0138)</div><div class='add'>+#define W5_RET_PRODUCT_ID                       (W5_REG_BASE + 0x013C)</div><div class='add'>+#define W5_RET_CUSTOMER_ID                      (W5_REG_BASE + 0x0140)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - QUERY : GET_RESULT                                         */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_DEC_ADDR_REPORT_BASE         (W5_REG_BASE + 0x0114)</div><div class='add'>+#define W5_CMD_DEC_REPORT_SIZE              (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_CMD_DEC_REPORT_PARAM             (W5_REG_BASE + 0x011C)</div><div class='add'>+</div><div class='add'>+#define W5_RET_DEC_BS_RD_PTR                (W5_REG_BASE + 0x011C)</div><div class='add'>+#define W5_RET_DEC_SEQ_PARAM                (W5_REG_BASE + 0x0120)</div><div class='add'>+#define W5_RET_DEC_COLOR_SAMPLE_INFO        (W5_REG_BASE + 0x0124)</div><div class='add'>+#define W5_RET_DEC_ASPECT_RATIO             (W5_REG_BASE + 0x0128)</div><div class='add'>+#define W5_RET_DEC_BIT_RATE                 (W5_REG_BASE + 0x012C)</div><div class='add'>+#define W5_RET_DEC_FRAME_RATE_NR            (W5_REG_BASE + 0x0130)</div><div class='add'>+#define W5_RET_DEC_FRAME_RATE_DR            (W5_REG_BASE + 0x0134)</div><div class='add'>+#define W5_RET_DEC_NUM_REQUIRED_FB          (W5_REG_BASE + 0x0138)</div><div class='add'>+#define W5_RET_DEC_NUM_REORDER_DELAY        (W5_REG_BASE + 0x013C)</div><div class='add'>+#define W5_RET_DEC_SUB_LAYER_INFO           (W5_REG_BASE + 0x0140)</div><div class='add'>+#define W5_RET_DEC_NOTIFICATION             (W5_REG_BASE + 0x0144)</div><div class='add'>+/*</div><div class='add'>+ * USER_DATA_FLAGS for HEVC/H264 only.</div><div class='add'>+ * Bits:</div><div class='add'>+ * [1] - User data buffer full boolean</div><div class='add'>+ * [2] - VUI parameter flag</div><div class='add'>+ * [4] - Pic_timing SEI flag</div><div class='add'>+ * [5] - 1st user_data_registed_itu_t_t35 prefix SEI flag</div><div class='add'>+ * [6] - user_data_unregistered prefix SEI flag</div><div class='add'>+ * [7] - 1st user_data_registed_itu_t_t35 suffix SEI flag</div><div class='add'>+ * [8] - user_data_unregistered suffix SEI flag</div><div class='add'>+ * [10]- mastering_display_color_volume prefix SEI flag</div><div class='add'>+ * [11]- chroma_resampling_display_color_volume prefix SEI flag</div><div class='add'>+ * [12]- knee_function_info SEI flag</div><div class='add'>+ * [13]- tone_mapping_info prefix SEI flag</div><div class='add'>+ * [14]- film_grain_characteristics_info prefix SEI flag</div><div class='add'>+ * [15]- content_light_level_info prefix SEI flag</div><div class='add'>+ * [16]- color_remapping_info prefix SEI flag</div><div class='add'>+ * [28]- 2nd user_data_registed_itu_t_t35 prefix SEI flag</div><div class='add'>+ * [29]- 3rd user_data_registed_itu_t_t35 prefix SEI flag</div><div class='add'>+ * [30]- 2nd user_data_registed_itu_t_t35 suffix SEI flag</div><div class='add'>+ * [31]- 3rd user_data_registed_itu_t_t35 suffix SEI flag</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_USERDATA_IDC             (W5_REG_BASE + 0x0148)</div><div class='add'>+#define W5_RET_DEC_PIC_SIZE                 (W5_REG_BASE + 0x014C)</div><div class='add'>+#define W5_RET_DEC_CROP_TOP_BOTTOM          (W5_REG_BASE + 0x0150)</div><div class='add'>+#define W5_RET_DEC_CROP_LEFT_RIGHT          (W5_REG_BASE + 0x0154)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_DEC_AU_START_POS             (W5_REG_BASE + 0x0158)</div><div class='add'>+ * =&gt; Access unit (AU) Bitstream start position</div><div class='add'>+ * #define W5_RET_DEC_AU_END_POS               (W5_REG_BASE + 0x015C)</div><div class='add'>+ * =&gt; Access unit (AU) Bitstream end position</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Decoded picture type:</div><div class='add'>+ * reg_val &amp; 0x7			=&gt; picture type</div><div class='add'>+ * (reg_val &gt;&gt; 4) &amp; 0x3f		=&gt; VCL NAL unit type</div><div class='add'>+ * (reg_val &gt;&gt; 31) &amp; 0x1		=&gt; output_flag</div><div class='add'>+ * 16 &lt;&lt; ((reg_val &gt;&gt; 10) &amp; 0x3)	=&gt; ctu_size</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_PIC_TYPE                 (W5_REG_BASE + 0x0160)</div><div class='add'>+#define W5_RET_DEC_PIC_POC                  (W5_REG_BASE + 0x0164)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_DEC_RECOVERY_POINT           (W5_REG_BASE + 0x0168)</div><div class='add'>+ * =&gt; HEVC recovery point</div><div class='add'>+ * reg_val &amp; 0xff =&gt; number of signed recovery picture order counts</div><div class='add'>+ * (reg_val &gt;&gt; 16) &amp; 0x1 =&gt; exact match flag</div><div class='add'>+ * (reg_val &gt;&gt; 17) &amp; 0x1 =&gt; broken link flag</div><div class='add'>+ * (reg_val &gt;&gt; 18) &amp; 0x1 =&gt; exist flag</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_DEBUG_INDEX              (W5_REG_BASE + 0x016C)</div><div class='add'>+#define W5_RET_DEC_DECODED_INDEX            (W5_REG_BASE + 0x0170)</div><div class='add'>+#define W5_RET_DEC_DISPLAY_INDEX            (W5_REG_BASE + 0x0174)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_DEC_REALLOC_INDEX            (W5_REG_BASE + 0x0178)</div><div class='add'>+ * =&gt; display picture index in decoded picture buffer</div><div class='add'>+ * reg_val &amp; 0xf =&gt; display picture index for FBC buffer (by reordering)</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_DISP_IDC                 (W5_REG_BASE + 0x017C)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_DEC_ERR_CTB_NUM              (W5_REG_BASE + 0x0180)</div><div class='add'>+ * =&gt; Number of error CTUs</div><div class='add'>+ * reg_val &gt;&gt; 16	=&gt; erroneous CTUs in bitstream</div><div class='add'>+ * reg_val &amp; 0xffff	=&gt; total CTUs in bitstream</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_DEC_PIC_PARAM                (W5_REG_BASE + 0x01A0)</div><div class='add'>+ * =&gt; Bitstream sequence/picture parameter information (AV1 only)</div><div class='add'>+ * reg_val &amp; 0x1 =&gt; intrabc tool enable</div><div class='add'>+ * (reg_val &gt;&gt; 1) &amp; 0x1 =&gt; screen content tools enable</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_HOST_CMD_TICK            (W5_REG_BASE + 0x01B8)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_DEC_SEEK_START_TICK          (W5_REG_BASE + 0x01BC)</div><div class='add'>+ * #define W5_RET_DEC_SEEK_END_TICK            (W5_REG_BASE + 0x01C0)</div><div class='add'>+ * =&gt; Start and end ticks for seeking slices of the picture</div><div class='add'>+ * #define W5_RET_DEC_PARSING_START_TICK       (W5_REG_BASE + 0x01C4)</div><div class='add'>+ * #define W5_RET_DEC_PARSING_END_TICK         (W5_REG_BASE + 0x01C8)</div><div class='add'>+ * =&gt; Start and end ticks for parsing slices of the picture</div><div class='add'>+ * #define W5_RET_DEC_DECODING_START_TICK      (W5_REG_BASE + 0x01CC)</div><div class='add'>+ * =&gt; Start tick for decoding slices of the picture</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_DEC_DECODING_ENC_TICK        (W5_REG_BASE + 0x01D0)</div><div class='add'>+#define W5_RET_DEC_WARN_INFO                (W5_REG_BASE + 0x01D4)</div><div class='add'>+#define W5_RET_DEC_ERR_INFO                 (W5_REG_BASE + 0x01D8)</div><div class='add'>+#define W5_RET_DEC_DECODING_SUCCESS         (W5_REG_BASE + 0x01DC)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - FLUSH_INSTANCE                                             */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_FLUSH_INST_OPT               (W5_REG_BASE + 0x104)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - QUERY : UPDATE_DISP_FLAG                                   */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_DEC_SET_DISP_IDC             (W5_REG_BASE + 0x0118)</div><div class='add'>+#define W5_CMD_DEC_CLR_DISP_IDC             (W5_REG_BASE + 0x011C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - QUERY : SET_BS_RD_PTR                                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_QUERY_DEC_SET_BS_RD_PTR      (W5_REG_BASE + 0x011C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* DECODER - QUERY : GET_BS_RD_PTR                                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_QUERY_DEC_BS_RD_PTR          (W5_REG_BASE + 0x011C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* QUERY : GET_DEBUG_INFO                                               */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_QUERY_DEBUG_PRI_REASON       (W5_REG_BASE + 0x114)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* GDI register for debugging                                           */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_GDI_BASE                         0x8800</div><div class='add'>+#define W5_GDI_BUS_CTRL                     (W5_GDI_BASE + 0x0F0)</div><div class='add'>+#define W5_GDI_BUS_STATUS                   (W5_GDI_BASE + 0x0F4)</div><div class='add'>+</div><div class='add'>+#define W5_BACKBONE_BASE_VCPU               0xFE00</div><div class='add'>+#define W5_BACKBONE_BUS_CTRL_VCPU           (W5_BACKBONE_BASE_VCPU + 0x010)</div><div class='add'>+#define W5_BACKBONE_BUS_STATUS_VCPU         (W5_BACKBONE_BASE_VCPU + 0x014)</div><div class='add'>+#define W5_BACKBONE_PROG_AXI_ID             (W5_BACKBONE_BASE_VCPU + 0x00C)</div><div class='add'>+</div><div class='add'>+#define W5_BACKBONE_PROC_EXT_ADDR           (W5_BACKBONE_BASE_VCPU + 0x0C0)</div><div class='add'>+#define W5_BACKBONE_AXI_PARAM               (W5_BACKBONE_BASE_VCPU + 0x0E0)</div><div class='add'>+</div><div class='add'>+#define W5_BACKBONE_BASE_VCORE0             0x8E00</div><div class='add'>+#define W5_BACKBONE_BUS_CTRL_VCORE0         (W5_BACKBONE_BASE_VCORE0 + 0x010)</div><div class='add'>+#define W5_BACKBONE_BUS_STATUS_VCORE0       (W5_BACKBONE_BASE_VCORE0 + 0x014)</div><div class='add'>+</div><div class='add'>+#define W5_BACKBONE_BASE_VCORE1             0x9E00  /* for dual-core product */</div><div class='add'>+#define W5_BACKBONE_BUS_CTRL_VCORE1         (W5_BACKBONE_BASE_VCORE1 + 0x010)</div><div class='add'>+#define W5_BACKBONE_BUS_STATUS_VCORE1       (W5_BACKBONE_BASE_VCORE1 + 0x014)</div><div class='add'>+</div><div class='add'>+#define W5_COMBINED_BACKBONE_BASE           0xFE00</div><div class='add'>+#define W5_COMBINED_BACKBONE_BUS_CTRL       (W5_COMBINED_BACKBONE_BASE + 0x010)</div><div class='add'>+#define W5_COMBINED_BACKBONE_BUS_STATUS     (W5_COMBINED_BACKBONE_BASE + 0x014)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/*                                                                      */</div><div class='add'>+/*               for  ENCODER                                           */</div><div class='add'>+/*                                                                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_STAGE3_INSTANCE_INFO             (W5_REG_BASE + 0x1F8)</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - CREATE_INSTANCE                                            */</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) */</div><div class='add'>+#define W5_CMD_ENC_VCORE_INFO                   (W5_REG_BASE + 0x0194)</div><div class='add'>+#define W5_CMD_ENC_SRC_OPTIONS                  (W5_REG_BASE + 0x0128)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - SET_FB                                                     */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_FBC_STRIDE                           (W5_REG_BASE + 0x128)</div><div class='add'>+#define W5_ADDR_SUB_SAMPLED_FB_BASE             (W5_REG_BASE + 0x12C)</div><div class='add'>+#define W5_SUB_SAMPLED_ONE_FB_SIZE              (W5_REG_BASE + 0x130)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - ENC_SET_PARAM (COMMON &amp; CHANGE_PARAM)                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_ENC_SEQ_SET_PARAM_OPTION         (W5_REG_BASE + 0x104)</div><div class='add'>+#define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE         (W5_REG_BASE + 0x118)</div><div class='add'>+#define W5_CMD_ENC_SEQ_SRC_SIZE                 (W5_REG_BASE + 0x11C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN        (W5_REG_BASE + 0x120)</div><div class='add'>+#define W5_CMD_ENC_SEQ_SPS_PARAM                (W5_REG_BASE + 0x124)</div><div class='add'>+#define W5_CMD_ENC_SEQ_PPS_PARAM                (W5_REG_BASE + 0x128)</div><div class='add'>+#define W5_CMD_ENC_SEQ_GOP_PARAM                (W5_REG_BASE + 0x12C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_INTRA_PARAM              (W5_REG_BASE + 0x130)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT         (W5_REG_BASE + 0x134)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT      (W5_REG_BASE + 0x138)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RDO_PARAM                (W5_REG_BASE + 0x13C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE        (W5_REG_BASE + 0x140)</div><div class='add'>+#define W5_CMD_ENC_SEQ_DEPENDENT_SLICE          (W5_REG_BASE + 0x144)</div><div class='add'>+#define W5_CMD_ENC_SEQ_INTRA_REFRESH            (W5_REG_BASE + 0x148)</div><div class='add'>+#define W5_CMD_ENC_SEQ_INPUT_SRC_PARAM          (W5_REG_BASE + 0x14C)</div><div class='add'>+</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_FRAME_RATE            (W5_REG_BASE + 0x150)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_TARGET_RATE           (W5_REG_BASE + 0x154)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_PARAM                 (W5_REG_BASE + 0x158)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP            (W5_REG_BASE + 0x15C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3   (W5_REG_BASE + 0x160)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7   (W5_REG_BASE + 0x164)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP      (W5_REG_BASE + 0x168)</div><div class='add'>+#define W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM          (W5_REG_BASE + 0x16C)</div><div class='add'>+</div><div class='add'>+#define W5_CMD_ENC_SEQ_ROT_PARAM                (W5_REG_BASE + 0x170)</div><div class='add'>+#define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK        (W5_REG_BASE + 0x174)</div><div class='add'>+#define W5_CMD_ENC_SEQ_TIME_SCALE               (W5_REG_BASE + 0x178)</div><div class='add'>+#define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE   (W5_REG_BASE + 0x17C)</div><div class='add'>+</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04           (W5_REG_BASE + 0x184)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08           (W5_REG_BASE + 0x188)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16           (W5_REG_BASE + 0x18C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32           (W5_REG_BASE + 0x190)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08           (W5_REG_BASE + 0x194)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16           (W5_REG_BASE + 0x198)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32           (W5_REG_BASE + 0x19C)</div><div class='add'>+#define W5_CMD_ENC_SEQ_NR_PARAM                 (W5_REG_BASE + 0x1A0)</div><div class='add'>+#define W5_CMD_ENC_SEQ_NR_WEIGHT                (W5_REG_BASE + 0x1A4)</div><div class='add'>+#define W5_CMD_ENC_SEQ_BG_PARAM                 (W5_REG_BASE + 0x1A8)</div><div class='add'>+#define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR       (W5_REG_BASE + 0x1AC)</div><div class='add'>+#define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR   (W5_REG_BASE + 0x1B0)</div><div class='add'>+#define W5_CMD_ENC_SEQ_VUI_HRD_PARAM            (W5_REG_BASE + 0x180)</div><div class='add'>+#define W5_CMD_ENC_SEQ_VUI_RBSP_ADDR            (W5_REG_BASE + 0x1B8)</div><div class='add'>+#define W5_CMD_ENC_SEQ_HRD_RBSP_ADDR            (W5_REG_BASE + 0x1BC)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - ENC_SET_PARAM (CUSTOM_GOP)                                 */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PARAM             (W5_REG_BASE + 0x11C)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0       (W5_REG_BASE + 0x120)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1       (W5_REG_BASE + 0x124)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2       (W5_REG_BASE + 0x128)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3       (W5_REG_BASE + 0x12C)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4       (W5_REG_BASE + 0x130)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5       (W5_REG_BASE + 0x134)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6       (W5_REG_BASE + 0x138)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7       (W5_REG_BASE + 0x13C)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_8       (W5_REG_BASE + 0x140)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_9       (W5_REG_BASE + 0x144)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_10      (W5_REG_BASE + 0x148)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_11      (W5_REG_BASE + 0x14C)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_12      (W5_REG_BASE + 0x150)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_13      (W5_REG_BASE + 0x154)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_14      (W5_REG_BASE + 0x158)</div><div class='add'>+#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_15      (W5_REG_BASE + 0x15C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - ENC_PIC                                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_CMD_ENC_BS_START_ADDR                (W5_REG_BASE + 0x118)</div><div class='add'>+#define W5_CMD_ENC_BS_SIZE                      (W5_REG_BASE + 0x11C)</div><div class='add'>+#define W5_CMD_ENC_PIC_USE_SEC_AXI              (W5_REG_BASE + 0x124)</div><div class='add'>+#define W5_CMD_ENC_PIC_REPORT_PARAM             (W5_REG_BASE + 0x128)</div><div class='add'>+</div><div class='add'>+#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM  (W5_REG_BASE + 0x138)</div><div class='add'>+#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR   (W5_REG_BASE + 0x13C)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_PIC_IDX              (W5_REG_BASE + 0x144)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_ADDR_Y               (W5_REG_BASE + 0x148)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_ADDR_U               (W5_REG_BASE + 0x14C)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_ADDR_V               (W5_REG_BASE + 0x150)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_STRIDE               (W5_REG_BASE + 0x154)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_FORMAT               (W5_REG_BASE + 0x158)</div><div class='add'>+#define W5_CMD_ENC_PIC_SRC_AXI_SEL              (W5_REG_BASE + 0x160)</div><div class='add'>+#define W5_CMD_ENC_PIC_CODE_OPTION              (W5_REG_BASE + 0x164)</div><div class='add'>+#define W5_CMD_ENC_PIC_PIC_PARAM                (W5_REG_BASE + 0x168)</div><div class='add'>+#define W5_CMD_ENC_PIC_LONGTERM_PIC             (W5_REG_BASE + 0x16C)</div><div class='add'>+#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y         (W5_REG_BASE + 0x170)</div><div class='add'>+#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C         (W5_REG_BASE + 0x174)</div><div class='add'>+#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y          (W5_REG_BASE + 0x178)</div><div class='add'>+#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C          (W5_REG_BASE + 0x17C)</div><div class='add'>+#define W5_CMD_ENC_PIC_CF50_Y_OFFSET_TABLE_ADDR  (W5_REG_BASE + 0x190)</div><div class='add'>+#define W5_CMD_ENC_PIC_CF50_CB_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x194)</div><div class='add'>+#define W5_CMD_ENC_PIC_CF50_CR_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x198)</div><div class='add'>+#define W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR       (W5_REG_BASE + 0x180)</div><div class='add'>+#define W5_CMD_ENC_PIC_PREFIX_SEI_INFO           (W5_REG_BASE + 0x184)</div><div class='add'>+#define W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR       (W5_REG_BASE + 0x188)</div><div class='add'>+#define W5_CMD_ENC_PIC_SUFFIX_SEI_INFO           (W5_REG_BASE + 0x18c)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - QUERY (GET_RESULT)                                         */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_ENC_NUM_REQUIRED_FB              (W5_REG_BASE + 0x11C)</div><div class='add'>+#define W5_RET_ENC_MIN_SRC_BUF_NUM              (W5_REG_BASE + 0x120)</div><div class='add'>+#define W5_RET_ENC_PIC_TYPE                     (W5_REG_BASE + 0x124)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_ENC_PIC_POC                      (W5_REG_BASE + 0x128)</div><div class='add'>+ * =&gt; picture order count value of current encoded picture</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_PIC_IDX                      (W5_REG_BASE + 0x12C)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_ENC_PIC_SLICE_NUM                (W5_REG_BASE + 0x130)</div><div class='add'>+ * reg_val &amp; 0xffff = total independent slice segment number (16 bits)</div><div class='add'>+ * (reg_val &gt;&gt; 16) &amp; 0xffff = total dependent slice segment number (16 bits)</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_ENC_PIC_SKIP                     (W5_REG_BASE + 0x134)</div><div class='add'>+ * reg_val &amp; 0xfe = picture skip flag (7 bits)</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_ENC_PIC_NUM_INTRA                (W5_REG_BASE + 0x138)</div><div class='add'>+ * =&gt; number of intra blocks in 8x8 (32 bits)</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_ENC_PIC_NUM_MERGE                (W5_REG_BASE + 0x13C)</div><div class='add'>+ * =&gt; number of merge blocks in 8x8 (32 bits)</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_ENC_PIC_NUM_SKIP                 (W5_REG_BASE + 0x144)</div><div class='add'>+ * =&gt; number of skip blocks in 8x8 (32 bits)</div><div class='add'>+ *</div><div class='add'>+ * #define W5_RET_ENC_PIC_AVG_CTU_QP               (W5_REG_BASE + 0x148)</div><div class='add'>+ * =&gt; Average CTU QP value (32 bits)</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_PIC_BYTE                     (W5_REG_BASE + 0x14C)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_ENC_GOP_PIC_IDX                  (W5_REG_BASE + 0x150)</div><div class='add'>+ * =&gt; picture index in group of pictures</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_USED_SRC_IDX                 (W5_REG_BASE + 0x154)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_ENC_PIC_NUM                      (W5_REG_BASE + 0x158)</div><div class='add'>+ * =&gt; encoded picture number</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_VCL_NUT                      (W5_REG_BASE + 0x15C)</div><div class='add'>+/*</div><div class='add'>+ * Only for H264:</div><div class='add'>+ * #define W5_RET_ENC_PIC_DIST_LOW                 (W5_REG_BASE + 0x164)</div><div class='add'>+ * =&gt; lower 32 bits of the sum of squared difference between source Y picture</div><div class='add'>+ *    and reconstructed Y picture</div><div class='add'>+ * #define W5_RET_ENC_PIC_DIST_HIGH                (W5_REG_BASE + 0x168)</div><div class='add'>+ * =&gt; upper 32 bits of the sum of squared difference between source Y picture</div><div class='add'>+ *    and reconstructed Y picture</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_PIC_MAX_LATENCY_PICS     (W5_REG_BASE + 0x16C)</div><div class='add'>+</div><div class='add'>+#define W5_RET_ENC_HOST_CMD_TICK                (W5_REG_BASE + 0x1B8)</div><div class='add'>+/*</div><div class='add'>+ * #define W5_RET_ENC_PREPARE_START_TICK           (W5_REG_BASE + 0x1BC)</div><div class='add'>+ * #define W5_RET_ENC_PREPARE_END_TICK             (W5_REG_BASE + 0x1C0)</div><div class='add'>+ * =&gt; Start and end ticks for preparing slices of the picture</div><div class='add'>+ * #define W5_RET_ENC_PROCESSING_START_TICK        (W5_REG_BASE + 0x1C4)</div><div class='add'>+ * #define W5_RET_ENC_PROCESSING_END_TICK          (W5_REG_BASE + 0x1C8)</div><div class='add'>+ * =&gt; Start and end ticks for processing slices of the picture</div><div class='add'>+ * #define W5_RET_ENC_ENCODING_START_TICK          (W5_REG_BASE + 0x1CC)</div><div class='add'>+ * =&gt; Start tick for encoding slices of the picture</div><div class='add'>+ */</div><div class='add'>+#define W5_RET_ENC_ENCODING_END_TICK            (W5_REG_BASE + 0x1D0)</div><div class='add'>+</div><div class='add'>+#define W5_RET_ENC_WARN_INFO                    (W5_REG_BASE + 0x1D4)</div><div class='add'>+#define W5_RET_ENC_ERR_INFO                     (W5_REG_BASE + 0x1D8)</div><div class='add'>+#define W5_RET_ENC_ENCODING_SUCCESS             (W5_REG_BASE + 0x1DC)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - QUERY (GET_BS_WR_PTR)                                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_ENC_RD_PTR                       (W5_REG_BASE + 0x114)</div><div class='add'>+#define W5_RET_ENC_WR_PTR                       (W5_REG_BASE + 0x118)</div><div class='add'>+#define W5_CMD_ENC_REASON_SEL                   (W5_REG_BASE + 0x11C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - QUERY (GET_BW_REPORT)                                      */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define RET_QUERY_BW_PRP_AXI_READ               (W5_REG_BASE + 0x118)</div><div class='add'>+#define RET_QUERY_BW_PRP_AXI_WRITE              (W5_REG_BASE + 0x11C)</div><div class='add'>+#define RET_QUERY_BW_FBD_Y_AXI_READ             (W5_REG_BASE + 0x120)</div><div class='add'>+#define RET_QUERY_BW_FBC_Y_AXI_WRITE            (W5_REG_BASE + 0x124)</div><div class='add'>+#define RET_QUERY_BW_FBD_C_AXI_READ             (W5_REG_BASE + 0x128)</div><div class='add'>+#define RET_QUERY_BW_FBC_C_AXI_WRITE            (W5_REG_BASE + 0x12C)</div><div class='add'>+#define RET_QUERY_BW_PRI_AXI_READ               (W5_REG_BASE + 0x130)</div><div class='add'>+#define RET_QUERY_BW_PRI_AXI_WRITE              (W5_REG_BASE + 0x134)</div><div class='add'>+#define RET_QUERY_BW_SEC_AXI_READ               (W5_REG_BASE + 0x138)</div><div class='add'>+#define RET_QUERY_BW_SEC_AXI_WRITE              (W5_REG_BASE + 0x13C)</div><div class='add'>+#define RET_QUERY_BW_PROC_AXI_READ              (W5_REG_BASE + 0x140)</div><div class='add'>+#define RET_QUERY_BW_PROC_AXI_WRITE             (W5_REG_BASE + 0x144)</div><div class='add'>+#define RET_QUERY_BW_BWB_AXI_WRITE              (W5_REG_BASE + 0x148)</div><div class='add'>+#define W5_CMD_BW_OPTION                        (W5_REG_BASE + 0x14C)</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* ENCODER - QUERY (GET_SRC_FLAG)                                       */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define W5_RET_RELEASED_SRC_INSTANCE            (W5_REG_BASE + 0x1EC)</div><div class='add'>+</div><div class='add'>+#define W5_ENC_PIC_SUB_FRAME_SYNC_IF            (W5_REG_BASE + 0x0300)</div><div class='add'>+</div><div class='add'>+#endif /* __WAVE5_REGISTER_DEFINE_H__ */</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c<br/>new file mode 100644<br/>index 000000000000..3809f70bc0b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vdi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vdi.c</a></div><div class='hunk'>@@ -0,0 +1,205 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - low level access functions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bug.h&gt;</div><div class='add'>+#include "wave5-vdi.h"</div><div class='add'>+#include "wave5-vpu.h"</div><div class='add'>+#include "wave5-regdefine.h"</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+</div><div class='add'>+static int wave5_vdi_allocate_common_memory(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	if (!vpu_dev-&gt;common_mem.vaddr) {</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		vpu_dev-&gt;common_mem.size = SIZE_COMMON;</div><div class='add'>+		ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vpu_dev-&gt;common_mem);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(dev, "unable to allocate common buffer\n");</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n",</div><div class='add'>+		&amp;vpu_dev-&gt;common_mem.daddr, vpu_dev-&gt;common_mem.size, vpu_dev-&gt;common_mem.vaddr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_init(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vdi_allocate_common_memory(dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!PRODUCT_CODE_W_SERIES(vpu_dev-&gt;product_code)) {</div><div class='add'>+		WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev-&gt;product_code);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* if BIT processor is not running. */</div><div class='add'>+	if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; 64; i++)</div><div class='add'>+			wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "[VDI] driver initialized successfully\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_release(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	vpu_dev-&gt;vdb_register = NULL;</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;vpu_dev-&gt;common_mem);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data)</div><div class='add'>+{</div><div class='add'>+	writel(data, vpu_dev-&gt;vdb_register + addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+unsigned int wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr)</div><div class='add'>+{</div><div class='add'>+	return readl(vpu_dev-&gt;vdb_register + addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)</div><div class='add'>+{</div><div class='add'>+	if (!vb || !vb-&gt;vaddr) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "%s: unable to clear unmapped buffer\n", __func__);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memset(vb-&gt;vaddr, 0, vb-&gt;size);</div><div class='add'>+	return vb-&gt;size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,</div><div class='add'>+			   u8 *data, size_t len)</div><div class='add'>+{</div><div class='add'>+	if (!vb || !vb-&gt;vaddr) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "%s: unable to write to unmapped buffer\n", __func__);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (offset &gt; vb-&gt;size || len &gt; vb-&gt;size || offset + len &gt; vb-&gt;size) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "%s: buffer too small\n", __func__);</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(vb-&gt;vaddr + offset, data, len);</div><div class='add'>+</div><div class='add'>+	return len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)</div><div class='add'>+{</div><div class='add'>+	void *vaddr;</div><div class='add'>+	dma_addr_t daddr;</div><div class='add'>+</div><div class='add'>+	if (!vb-&gt;size) {</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "%s: requested size==0\n", __func__);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vaddr = dma_alloc_coherent(vpu_dev-&gt;dev, vb-&gt;size, &amp;daddr, GFP_KERNEL);</div><div class='add'>+	if (!vaddr)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	vb-&gt;vaddr = vaddr;</div><div class='add'>+	vb-&gt;daddr = daddr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)</div><div class='add'>+{</div><div class='add'>+	if (vb-&gt;size == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!vb-&gt;vaddr)</div><div class='add'>+		dev_err(vpu_dev-&gt;dev, "%s: requested free of unmapped buffer\n", __func__);</div><div class='add'>+	else</div><div class='add'>+		dma_free_coherent(vpu_dev-&gt;dev, vb-&gt;size, vb-&gt;vaddr, vb-&gt;daddr);</div><div class='add'>+</div><div class='add'>+	memset(vb, 0, sizeof(*vb));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,</div><div class='add'>+			     size_t size)</div><div class='add'>+{</div><div class='add'>+	struct vpu_buf vb_buf;</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+</div><div class='add'>+	vb_buf.size = size;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		if (array[i].size == size)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (array[i].size != 0)</div><div class='add'>+			wave5_vdi_free_dma_memory(vpu_dev, &amp;array[i]);</div><div class='add'>+</div><div class='add'>+		ret = wave5_vdi_allocate_dma_memory(vpu_dev, &amp;vb_buf);</div><div class='add'>+		if (ret)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		array[i] = vb_buf;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = count; i &lt; MAX_REG_FRAME; i++)</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;array[i]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_buf *vb = &amp;vpu_dev-&gt;sram_buf;</div><div class='add'>+</div><div class='add'>+	if (!vpu_dev-&gt;sram_pool || !vpu_dev-&gt;sram_size)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!vb-&gt;vaddr) {</div><div class='add'>+		vb-&gt;size = vpu_dev-&gt;sram_size;</div><div class='add'>+		vb-&gt;vaddr = gen_pool_dma_alloc(vpu_dev-&gt;sram_pool, vb-&gt;size,</div><div class='add'>+					       &amp;vb-&gt;daddr);</div><div class='add'>+		if (!vb-&gt;vaddr)</div><div class='add'>+			vb-&gt;size = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(vpu_dev-&gt;dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n",</div><div class='add'>+		__func__, &amp;vb-&gt;daddr, vb-&gt;size, vb-&gt;vaddr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_vdi_free_sram(struct vpu_device *vpu_dev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_buf *vb = &amp;vpu_dev-&gt;sram_buf;</div><div class='add'>+</div><div class='add'>+	if (!vb-&gt;size || !vb-&gt;vaddr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (vb-&gt;vaddr)</div><div class='add'>+		gen_pool_free(vpu_dev-&gt;sram_pool, (unsigned long)vb-&gt;vaddr,</div><div class='add'>+			      vb-&gt;size);</div><div class='add'>+</div><div class='add'>+	memset(vb, 0, sizeof(*vb));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.h b/drivers/media/platform/chips-media/wave5/wave5-vdi.h<br/>new file mode 100644<br/>index 000000000000..3984ef3f1f96<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vdi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vdi.h</a></div><div class='hunk'>@@ -0,0 +1,35 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - low level access functions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _VDI_H_</div><div class='add'>+#define _VDI_H_</div><div class='add'>+</div><div class='add'>+#include "wave5-vpuconfig.h"</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* COMMON REGISTERS */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define VPU_PRODUCT_CODE_REGISTER 0x1044</div><div class='add'>+</div><div class='add'>+/* system register write */</div><div class='add'>+#define vpu_write_reg(VPU_INST, ADDR, DATA) wave5_vdi_write_register(VPU_INST, ADDR, DATA)</div><div class='add'>+/* system register read */</div><div class='add'>+#define vpu_read_reg(CORE, ADDR) wave5_vdi_read_register(CORE, ADDR)</div><div class='add'>+</div><div class='add'>+struct vpu_buf {</div><div class='add'>+	size_t size;</div><div class='add'>+	dma_addr_t daddr;</div><div class='add'>+	void *vaddr;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int wave5_vdi_init(struct device *dev);</div><div class='add'>+int wave5_vdi_release(struct device *dev);	//this function may be called only at system off.</div><div class='add'>+</div><div class='add'>+#endif //#ifndef _VDI_H_</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c<br/>new file mode 100644<br/>index 000000000000..ef227af72348<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c</a></div><div class='hunk'>@@ -0,0 +1,1932 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - decoder interface</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "wave5-helper.h"</div><div class='add'>+</div><div class='add'>+#define VPU_DEC_DEV_NAME "C&amp;M Wave5 VPU decoder"</div><div class='add'>+#define VPU_DEC_DRV_NAME "wave5-dec"</div><div class='add'>+</div><div class='add'>+#define DEFAULT_SRC_SIZE(width, height) ({			\</div><div class='add'>+	(width) * (height) / 8 * 3;					\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = {</div><div class='add'>+	[VPU_FMT_TYPE_CODEC] = {</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_HEVC,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_H264,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 32,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 32,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[VPU_FMT_TYPE_RAW] = {</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV420,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV12,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV21,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV16,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV61,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV12M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV21M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV16M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV61M,</div><div class='add'>+			.max_width = 8192,</div><div class='add'>+			.min_width = 8,</div><div class='add'>+			.max_height = 4320,</div><div class='add'>+			.min_height = 8,</div><div class='add'>+		},</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Make sure that the state switch is allowed and add logging for debugging</div><div class='add'>+ * purposes</div><div class='add'>+ */</div><div class='add'>+static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state)</div><div class='add'>+{</div><div class='add'>+	switch (state) {</div><div class='add'>+	case VPU_INST_STATE_NONE:</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_OPEN:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_NONE)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		goto valid_state_switch;</div><div class='add'>+	case VPU_INST_STATE_INIT_SEQ:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_OPEN &amp;&amp; inst-&gt;state != VPU_INST_STATE_STOP)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		goto valid_state_switch;</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_INIT_SEQ)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		goto valid_state_switch;</div><div class='add'>+	case VPU_INST_STATE_STOP:</div><div class='add'>+		goto valid_state_switch;</div><div class='add'>+	}</div><div class='add'>+invalid_state_switch:</div><div class='add'>+	WARN(1, "Invalid state switch from %s to %s.\n",</div><div class='add'>+	     state_to_str(inst-&gt;state), state_to_str(state));</div><div class='add'>+	return -EINVAL;</div><div class='add'>+valid_state_switch:</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "Switch state from %s to %s.\n",</div><div class='add'>+		state_to_str(inst-&gt;state), state_to_str(state));</div><div class='add'>+	inst-&gt;state = state;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_set_eos_on_firmware(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		/*</div><div class='add'>+		 * To set the EOS flag, a command is sent to the firmware.</div><div class='add'>+		 * That command may never return (timeout) or may report an error.</div><div class='add'>+		 */</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Setting EOS for the bitstream, fail: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool wave5_last_src_buffer_consumed(struct v4l2_m2m_ctx *m2m_ctx)</div><div class='add'>+{</div><div class='add'>+	struct vpu_src_buffer *vpu_buf;</div><div class='add'>+</div><div class='add'>+	if (!m2m_ctx-&gt;last_src_buf)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	vpu_buf = wave5_to_vpu_src_buf(m2m_ctx-&gt;last_src_buf);</div><div class='add'>+	return vpu_buf-&gt;consumed;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_handle_src_buffer(struct vpu_instance *inst, dma_addr_t rd_ptr)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct v4l2_m2m_buffer *buf, *n;</div><div class='add'>+	size_t consumed_bytes = 0;</div><div class='add'>+</div><div class='add'>+	if (rd_ptr &gt;= inst-&gt;last_rd_ptr) {</div><div class='add'>+		consumed_bytes = rd_ptr - inst-&gt;last_rd_ptr;</div><div class='add'>+	} else {</div><div class='add'>+		size_t rd_offs = rd_ptr - inst-&gt;bitstream_vbuf.daddr;</div><div class='add'>+		size_t last_rd_offs = inst-&gt;last_rd_ptr - inst-&gt;bitstream_vbuf.daddr;</div><div class='add'>+</div><div class='add'>+		consumed_bytes = rd_offs + (inst-&gt;bitstream_vbuf.size - last_rd_offs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;last_rd_ptr = rd_ptr;</div><div class='add'>+	consumed_bytes += inst-&gt;remaining_consumed_bytes;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: %zu bytes of bitstream was consumed", __func__,</div><div class='add'>+		consumed_bytes);</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buf, n) {</div><div class='add'>+		struct vb2_v4l2_buffer *src_buf = &amp;buf-&gt;vb;</div><div class='add'>+		size_t src_size = vb2_get_plane_payload(&amp;src_buf-&gt;vb2_buf, 0);</div><div class='add'>+</div><div class='add'>+		if (src_size &gt; consumed_bytes)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: removing src buffer %i",</div><div class='add'>+			__func__, src_buf-&gt;vb2_buf.index);</div><div class='add'>+		src_buf = v4l2_m2m_src_buf_remove(m2m_ctx);</div><div class='add'>+		inst-&gt;timestamp = src_buf-&gt;vb2_buf.timestamp;</div><div class='add'>+		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);</div><div class='add'>+		consumed_bytes -= src_size;</div><div class='add'>+</div><div class='add'>+		/* Handle the case the last bitstream buffer has been picked */</div><div class='add'>+		if (src_buf == m2m_ctx-&gt;last_src_buf) {</div><div class='add'>+			int ret;</div><div class='add'>+</div><div class='add'>+			m2m_ctx-&gt;last_src_buf = NULL;</div><div class='add'>+			ret = wave5_vpu_dec_set_eos_on_firmware(inst);</div><div class='add'>+			if (ret)</div><div class='add'>+				dev_warn(inst-&gt;dev-&gt;dev,</div><div class='add'>+					 "Setting EOS for the bitstream, fail: %d\n", ret);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;remaining_consumed_bytes = consumed_bytes;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width,</div><div class='add'>+				 unsigned int height)</div><div class='add'>+{</div><div class='add'>+	switch (pix_mp-&gt;pixelformat) {</div><div class='add'>+	case V4L2_PIX_FMT_YUV420:</div><div class='add'>+	case V4L2_PIX_FMT_NV12:</div><div class='add'>+	case V4L2_PIX_FMT_NV21:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height * 3 / 2;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_YUV422P:</div><div class='add'>+	case V4L2_PIX_FMT_NV16:</div><div class='add'>+	case V4L2_PIX_FMT_NV61:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height * 2;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_YUV420M:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = width * height / 4;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].sizeimage = width * height / 4;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_NV12M:</div><div class='add'>+	case V4L2_PIX_FMT_NV21M:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = width * height / 2;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_YUV422M:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = width * height / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].sizeimage = width * height / 2;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_NV16M:</div><div class='add'>+	case V4L2_PIX_FMT_NV61M:</div><div class='add'>+		pix_mp-&gt;width = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;height = round_up(height, 16);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = width * height;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		pix_mp-&gt;width = width;</div><div class='add'>+		pix_mp-&gt;height = height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = 0;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = max(DEFAULT_SRC_SIZE(width, height),</div><div class='add'>+						     pix_mp-&gt;plane_fmt[0].sizeimage);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int start_decode(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_start_one_frame(inst, fail_res);</div><div class='add'>+	if (ret) {</div><div class='add'>+		struct vb2_v4l2_buffer *src_buf;</div><div class='add'>+</div><div class='add'>+		src_buf = v4l2_m2m_src_buf_remove(m2m_ctx);</div><div class='add'>+		if (src_buf)</div><div class='add'>+			v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+		switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: pic run failed / finish job", __func__);</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void flag_last_buffer_done(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *vb;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;inst-&gt;state_spinlock);</div><div class='add'>+</div><div class='add'>+	vb = v4l2_m2m_dst_buf_remove(m2m_ctx);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		m2m_ctx-&gt;is_draining = true;</div><div class='add'>+		m2m_ctx-&gt;next_buf_last = true;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; vb-&gt;vb2_buf.num_planes; i++)</div><div class='add'>+		vb2_set_plane_payload(&amp;vb-&gt;vb2_buf, i, 0);</div><div class='add'>+	vb-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_last_buffer_done(m2m_ctx, vb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void send_eos_event(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	static const struct v4l2_event vpu_event_eos = {</div><div class='add'>+		.type = V4L2_EVENT_EOS</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;inst-&gt;state_spinlock);</div><div class='add'>+</div><div class='add'>+	v4l2_event_queue_fh(&amp;inst-&gt;v4l2_fh, &amp;vpu_event_eos);</div><div class='add'>+	inst-&gt;eos = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int handle_dynamic_resolution_change(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_fh *fh = &amp;inst-&gt;v4l2_fh;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	static const struct v4l2_event vpu_event_src_ch = {</div><div class='add'>+		.type = V4L2_EVENT_SOURCE_CHANGE,</div><div class='add'>+		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,</div><div class='add'>+	};</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	struct dec_initial_info *initial_info = &amp;inst-&gt;codec_info-&gt;dec_info.initial_info;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;inst-&gt;state_spinlock);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: rd_ptr %pad", __func__, &amp;initial_info-&gt;rd_ptr);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n",</div><div class='add'>+		__func__, initial_info-&gt;pic_width, initial_info-&gt;pic_height,</div><div class='add'>+		initial_info-&gt;profile, initial_info-&gt;min_frame_buffer_count);</div><div class='add'>+</div><div class='add'>+	inst-&gt;needs_reallocation = true;</div><div class='add'>+	inst-&gt;fbc_buf_count = initial_info-&gt;min_frame_buffer_count + 1;</div><div class='add'>+	if (inst-&gt;fbc_buf_count != v4l2_m2m_num_dst_bufs_ready(m2m_ctx)) {</div><div class='add'>+		struct v4l2_ctrl *ctrl;</div><div class='add'>+</div><div class='add'>+		ctrl = v4l2_ctrl_find(&amp;inst-&gt;v4l2_ctrl_hdl,</div><div class='add'>+				      V4L2_CID_MIN_BUFFERS_FOR_CAPTURE);</div><div class='add'>+		if (ctrl)</div><div class='add'>+			v4l2_ctrl_s_ctrl(ctrl, inst-&gt;fbc_buf_count);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p_dec_info-&gt;initial_info_obtained) {</div><div class='add'>+		inst-&gt;conf_win.left = initial_info-&gt;pic_crop_rect.left;</div><div class='add'>+		inst-&gt;conf_win.top = initial_info-&gt;pic_crop_rect.top;</div><div class='add'>+		inst-&gt;conf_win.width = initial_info-&gt;pic_width -</div><div class='add'>+			initial_info-&gt;pic_crop_rect.left - initial_info-&gt;pic_crop_rect.right;</div><div class='add'>+		inst-&gt;conf_win.height = initial_info-&gt;pic_height -</div><div class='add'>+			initial_info-&gt;pic_crop_rect.top - initial_info-&gt;pic_crop_rect.bottom;</div><div class='add'>+</div><div class='add'>+		wave5_update_pix_fmt(&amp;inst-&gt;src_fmt, initial_info-&gt;pic_width,</div><div class='add'>+				     initial_info-&gt;pic_height);</div><div class='add'>+		wave5_update_pix_fmt(&amp;inst-&gt;dst_fmt, initial_info-&gt;pic_width,</div><div class='add'>+				     initial_info-&gt;pic_height);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_event_queue_fh(fh, &amp;vpu_event_src_ch);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct dec_output_info dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vb2_v4l2_buffer *dec_buf = NULL;</div><div class='add'>+	struct vb2_v4l2_buffer *disp_buf = NULL;</div><div class='add'>+	struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx);</div><div class='add'>+	struct queue_status_info q_status;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: Fetch output info from firmware.", __func__);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_get_output_info(inst, &amp;dec_info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "%s: could not get output info.", __func__);</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &amp;dec_info.rd_ptr,</div><div class='add'>+		&amp;dec_info.wr_ptr);</div><div class='add'>+	wave5_handle_src_buffer(inst, dec_info.rd_ptr);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: dec_info dec_idx %i disp_idx %i", __func__,</div><div class='add'>+		dec_info.index_frame_decoded, dec_info.index_frame_display);</div><div class='add'>+</div><div class='add'>+	if (!vb2_is_streaming(dst_vq)) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: capture is not streaming..", __func__);</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Remove decoded buffer from the ready queue now that it has been</div><div class='add'>+	 * decoded.</div><div class='add'>+	 */</div><div class='add'>+	if (dec_info.index_frame_decoded &gt;= 0) {</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(dst_vq,</div><div class='add'>+						       dec_info.index_frame_decoded);</div><div class='add'>+		if (vb) {</div><div class='add'>+			dec_buf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+			dec_buf-&gt;vb2_buf.timestamp = inst-&gt;timestamp;</div><div class='add'>+		} else {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "%s: invalid decoded frame index %i",</div><div class='add'>+				 __func__, dec_info.index_frame_decoded);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (dec_info.index_frame_display &gt;= 0) {</div><div class='add'>+		disp_buf = v4l2_m2m_dst_buf_remove_by_idx(m2m_ctx, dec_info.index_frame_display);</div><div class='add'>+		if (!disp_buf)</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "%s: invalid display frame index %i",</div><div class='add'>+				 __func__, dec_info.index_frame_display);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If there is anything to display, do that now */</div><div class='add'>+	if (disp_buf) {</div><div class='add'>+		struct vpu_dst_buffer *dst_vpu_buf = wave5_to_vpu_dst_buf(disp_buf);</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;dst_fmt.num_planes == 1) {</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 0,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[0].sizeimage);</div><div class='add'>+		} else if (inst-&gt;dst_fmt.num_planes == 2) {</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 0,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[0].sizeimage);</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 1,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[1].sizeimage);</div><div class='add'>+		} else if (inst-&gt;dst_fmt.num_planes == 3) {</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 0,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[0].sizeimage);</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 1,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[1].sizeimage);</div><div class='add'>+			vb2_set_plane_payload(&amp;disp_buf-&gt;vb2_buf, 2,</div><div class='add'>+					      inst-&gt;dst_fmt.plane_fmt[2].sizeimage);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* TODO implement interlace support */</div><div class='add'>+		disp_buf-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+		dst_vpu_buf-&gt;display = true;</div><div class='add'>+		v4l2_m2m_buf_done(disp_buf, VB2_BUF_STATE_DONE);</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: frame_cycle %8u (payload %lu)\n",</div><div class='add'>+			__func__, dec_info.frame_cycle,</div><div class='add'>+			vb2_get_plane_payload(&amp;disp_buf-&gt;vb2_buf, 0));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if ((dec_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END ||</div><div class='add'>+	     dec_info.sequence_changed)) {</div><div class='add'>+		unsigned long flags;</div><div class='add'>+</div><div class='add'>+		spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+		if (!v4l2_m2m_has_stopped(m2m_ctx)) {</div><div class='add'>+			switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+</div><div class='add'>+			if (dec_info.sequence_changed)</div><div class='add'>+				handle_dynamic_resolution_change(inst);</div><div class='add'>+			else</div><div class='add'>+				send_eos_event(inst);</div><div class='add'>+</div><div class='add'>+			flag_last_buffer_done(inst);</div><div class='add'>+		}</div><div class='add'>+		spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * During a resolution change and while draining, the firmware may flush</div><div class='add'>+	 * the reorder queue regardless of having a matching decoding operation</div><div class='add'>+	 * pending. Only terminate the job if there are no more IRQ coming.</div><div class='add'>+	 */</div><div class='add'>+	wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &amp;q_status);</div><div class='add'>+	if (q_status.report_queue_count == 0 &amp;&amp;</div><div class='add'>+	    (q_status.instance_queue_count == 0 || dec_info.sequence_changed)) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: finishing job.\n", __func__);</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap)</div><div class='add'>+{</div><div class='add'>+	strscpy(cap-&gt;driver, VPU_DEC_DRV_NAME, sizeof(cap-&gt;driver));</div><div class='add'>+	strscpy(cap-&gt;card, VPU_DEC_DRV_NAME, sizeof(cap-&gt;card));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize)</div><div class='add'>+{</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	if (fsize-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(fsize-&gt;pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		vpu_fmt = wave5_find_vpu_fmt(fsize-&gt;pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+		if (!vpu_fmt)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fsize-&gt;type = V4L2_FRMSIZE_TYPE_CONTINUOUS;</div><div class='add'>+	fsize-&gt;stepwise.min_width = vpu_fmt-&gt;min_width;</div><div class='add'>+	fsize-&gt;stepwise.max_width = vpu_fmt-&gt;max_width;</div><div class='add'>+	fsize-&gt;stepwise.step_width = 1;</div><div class='add'>+	fsize-&gt;stepwise.min_height = vpu_fmt-&gt;min_height;</div><div class='add'>+	fsize-&gt;stepwise.max_height = vpu_fmt-&gt;max_height;</div><div class='add'>+	fsize-&gt;stepwise.step_height = 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f)</div><div class='add'>+{</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt_by_idx(f-&gt;index, dec_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+	if (!vpu_fmt)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	f-&gt;pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+	f-&gt;flags = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+	int width, height;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+		"%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.colorspace, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(f-&gt;fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		width = inst-&gt;dst_fmt.width;</div><div class='add'>+		height = inst-&gt;dst_fmt.height;</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = inst-&gt;dst_fmt.pixelformat;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = inst-&gt;dst_fmt.num_planes;</div><div class='add'>+	} else {</div><div class='add'>+		const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt-&gt;v4l2_pix_fmt);</div><div class='add'>+</div><div class='add'>+		width = clamp(f-&gt;fmt.pix_mp.width, vpu_fmt-&gt;min_width, vpu_fmt-&gt;max_width);</div><div class='add'>+		height = clamp(f-&gt;fmt.pix_mp.height, vpu_fmt-&gt;min_height, vpu_fmt-&gt;max_height);</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = info-&gt;mem_planes;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (p_dec_info-&gt;initial_info_obtained) {</div><div class='add'>+		width = inst-&gt;dst_fmt.width;</div><div class='add'>+		height = inst-&gt;dst_fmt.height;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, width, height);</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = 0;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = V4L2_FIELD_NONE;</div><div class='add'>+	f-&gt;fmt.pix_mp.colorspace = inst-&gt;colorspace;</div><div class='add'>+	f-&gt;fmt.pix_mp.ycbcr_enc = inst-&gt;ycbcr_enc;</div><div class='add'>+	f-&gt;fmt.pix_mp.quantization = inst-&gt;quantization;</div><div class='add'>+	f-&gt;fmt.pix_mp.xfer_func = inst-&gt;xfer_func;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+		"%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.colorspace, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_try_fmt_cap(file, fh, f);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	inst-&gt;dst_fmt.width = f-&gt;fmt.pix_mp.width;</div><div class='add'>+	inst-&gt;dst_fmt.height = f-&gt;fmt.pix_mp.height;</div><div class='add'>+	inst-&gt;dst_fmt.pixelformat = f-&gt;fmt.pix_mp.pixelformat;</div><div class='add'>+	inst-&gt;dst_fmt.field = f-&gt;fmt.pix_mp.field;</div><div class='add'>+	inst-&gt;dst_fmt.flags = f-&gt;fmt.pix_mp.flags;</div><div class='add'>+	inst-&gt;dst_fmt.num_planes = f-&gt;fmt.pix_mp.num_planes;</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;dst_fmt.num_planes; i++) {</div><div class='add'>+		inst-&gt;dst_fmt.plane_fmt[i].bytesperline = f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline;</div><div class='add'>+		inst-&gt;dst_fmt.plane_fmt[i].sizeimage = f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||</div><div class='add'>+	    inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+		inst-&gt;output_format = FORMAT_420;</div><div class='add'>+	} else if (inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||</div><div class='add'>+		   inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = true;</div><div class='add'>+		inst-&gt;output_format = FORMAT_420;</div><div class='add'>+	} else if (inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV16 ||</div><div class='add'>+		   inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV16M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+		inst-&gt;output_format = FORMAT_422;</div><div class='add'>+	} else if (inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV61 ||</div><div class='add'>+		   inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_NV61M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = true;</div><div class='add'>+		inst-&gt;output_format = FORMAT_422;</div><div class='add'>+	} else if (inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422P ||</div><div class='add'>+		   inst-&gt;dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = false;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+		inst-&gt;output_format = FORMAT_422;</div><div class='add'>+	} else {</div><div class='add'>+		inst-&gt;cbcr_interleave = false;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+		inst-&gt;output_format = FORMAT_420;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.width = inst-&gt;dst_fmt.width;</div><div class='add'>+	f-&gt;fmt.pix_mp.height = inst-&gt;dst_fmt.height;</div><div class='add'>+	f-&gt;fmt.pix_mp.pixelformat = inst-&gt;dst_fmt.pixelformat;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = inst-&gt;dst_fmt.field;</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = inst-&gt;dst_fmt.flags;</div><div class='add'>+	f-&gt;fmt.pix_mp.num_planes = inst-&gt;dst_fmt.num_planes;</div><div class='add'>+	for (i = 0; i &lt; f-&gt;fmt.pix_mp.num_planes; i++) {</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline = inst-&gt;dst_fmt.plane_fmt[i].bytesperline;</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage = inst-&gt;dst_fmt.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.colorspace = inst-&gt;colorspace;</div><div class='add'>+	f-&gt;fmt.pix_mp.ycbcr_enc = inst-&gt;ycbcr_enc;</div><div class='add'>+	f-&gt;fmt.pix_mp.quantization = inst-&gt;quantization;</div><div class='add'>+	f-&gt;fmt.pix_mp.xfer_func = inst-&gt;xfer_func;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: index: %u\n", __func__, f-&gt;index);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt_by_idx(f-&gt;index, dec_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	f-&gt;pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+	f-&gt;flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+		"%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.colorspace, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(f-&gt;fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = inst-&gt;src_fmt.pixelformat;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = inst-&gt;src_fmt.num_planes;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, inst-&gt;src_fmt.width, inst-&gt;src_fmt.height);</div><div class='add'>+	} else {</div><div class='add'>+		int width = clamp(f-&gt;fmt.pix_mp.width, vpu_fmt-&gt;min_width, vpu_fmt-&gt;max_width);</div><div class='add'>+		int height = clamp(f-&gt;fmt.pix_mp.height, vpu_fmt-&gt;min_height, vpu_fmt-&gt;max_height);</div><div class='add'>+</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = 1;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, width, height);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = 0;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = V4L2_FIELD_NONE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+		"%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_try_fmt_out(file, fh, f);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	inst-&gt;std = wave5_to_vpu_std(f-&gt;fmt.pix_mp.pixelformat, inst-&gt;type);</div><div class='add'>+	if (inst-&gt;std == STD_UNKNOWN) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "unsupported pixelformat: %.4s\n",</div><div class='add'>+			 (char *)&amp;f-&gt;fmt.pix_mp.pixelformat);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;src_fmt.width = f-&gt;fmt.pix_mp.width;</div><div class='add'>+	inst-&gt;src_fmt.height = f-&gt;fmt.pix_mp.height;</div><div class='add'>+	inst-&gt;src_fmt.pixelformat = f-&gt;fmt.pix_mp.pixelformat;</div><div class='add'>+	inst-&gt;src_fmt.field = f-&gt;fmt.pix_mp.field;</div><div class='add'>+	inst-&gt;src_fmt.flags = f-&gt;fmt.pix_mp.flags;</div><div class='add'>+	inst-&gt;src_fmt.num_planes = f-&gt;fmt.pix_mp.num_planes;</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;src_fmt.num_planes; i++) {</div><div class='add'>+		inst-&gt;src_fmt.plane_fmt[i].bytesperline = f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline;</div><div class='add'>+		inst-&gt;src_fmt.plane_fmt[i].sizeimage = f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;colorspace = f-&gt;fmt.pix_mp.colorspace;</div><div class='add'>+	inst-&gt;ycbcr_enc = f-&gt;fmt.pix_mp.ycbcr_enc;</div><div class='add'>+	inst-&gt;quantization = f-&gt;fmt.pix_mp.quantization;</div><div class='add'>+	inst-&gt;xfer_func = f-&gt;fmt.pix_mp.xfer_func;</div><div class='add'>+</div><div class='add'>+	wave5_update_pix_fmt(&amp;inst-&gt;dst_fmt, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u | target: %u\n", __func__, s-&gt;type, s-&gt;target);</div><div class='add'>+</div><div class='add'>+	if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	switch (s-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE_BOUNDS:</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE_PADDED:</div><div class='add'>+		s-&gt;r.left = 0;</div><div class='add'>+		s-&gt;r.top = 0;</div><div class='add'>+		s-&gt;r.width = inst-&gt;dst_fmt.width;</div><div class='add'>+		s-&gt;r.height = inst-&gt;dst_fmt.height;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE:</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE_DEFAULT:</div><div class='add'>+		s-&gt;r.left = 0;</div><div class='add'>+		s-&gt;r.top = 0;</div><div class='add'>+		if (inst-&gt;state &gt; VPU_INST_STATE_OPEN) {</div><div class='add'>+			s-&gt;r = inst-&gt;conf_win;</div><div class='add'>+		} else {</div><div class='add'>+			s-&gt;r.width = inst-&gt;src_fmt.width;</div><div class='add'>+			s-&gt;r.height = inst-&gt;src_fmt.height;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (s-&gt;target != V4L2_SEL_TGT_COMPOSE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n",</div><div class='add'>+		s-&gt;r.width, s-&gt;r.height);</div><div class='add'>+</div><div class='add'>+	s-&gt;r.left = 0;</div><div class='add'>+	s-&gt;r.top = 0;</div><div class='add'>+	s-&gt;r.width = inst-&gt;dst_fmt.width;</div><div class='add'>+	s-&gt;r.height = inst-&gt;dst_fmt.height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_stop(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+</div><div class='add'>+	if (m2m_ctx-&gt;is_draining) {</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+		goto unlock_and_return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;state != VPU_INST_STATE_NONE) {</div><div class='add'>+		/*</div><div class='add'>+		 * Temporarily release the state_spinlock so that subsequent</div><div class='add'>+		 * calls do not block on a mutex while inside this spinlock.</div><div class='add'>+		 */</div><div class='add'>+		spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+		ret = wave5_vpu_dec_set_eos_on_firmware(inst);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+		/*</div><div class='add'>+		 * TODO eliminate this check by using a separate check for</div><div class='add'>+		 * draining triggered by a resolution change.</div><div class='add'>+		 */</div><div class='add'>+		if (m2m_ctx-&gt;is_draining) {</div><div class='add'>+			ret = -EBUSY;</div><div class='add'>+			goto unlock_and_return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Used to remember the EOS state after the streamoff/on transition on</div><div class='add'>+	 * the capture queue.</div><div class='add'>+	 */</div><div class='add'>+	inst-&gt;eos = true;</div><div class='add'>+</div><div class='add'>+	if (m2m_ctx-&gt;has_stopped)</div><div class='add'>+		goto unlock_and_return;</div><div class='add'>+</div><div class='add'>+	m2m_ctx-&gt;last_src_buf = v4l2_m2m_last_src_buf(m2m_ctx);</div><div class='add'>+	m2m_ctx-&gt;is_draining = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Deferred to device run in case it wasn't in the ring buffer</div><div class='add'>+	 * yet. In other case, we have to send the EOS signal to the</div><div class='add'>+	 * firmware so that any pending PIC_RUN ends without new</div><div class='add'>+	 * bitstream buffer.</div><div class='add'>+	 */</div><div class='add'>+	if (m2m_ctx-&gt;last_src_buf)</div><div class='add'>+		goto unlock_and_return;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;state == VPU_INST_STATE_NONE) {</div><div class='add'>+		send_eos_event(inst);</div><div class='add'>+		flag_last_buffer_done(inst);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+unlock_and_return:</div><div class='add'>+	spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_start(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx);</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+</div><div class='add'>+	if (m2m_ctx-&gt;is_draining) {</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+		goto unlock_and_return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (m2m_ctx-&gt;has_stopped)</div><div class='add'>+		m2m_ctx-&gt;has_stopped = false;</div><div class='add'>+</div><div class='add'>+	vb2_clear_last_buffer_dequeued(dst_vq);</div><div class='add'>+	inst-&gt;eos = false;</div><div class='add'>+</div><div class='add'>+unlock_and_return:</div><div class='add'>+	spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "decoder command: %u\n", dc-&gt;cmd);</div><div class='add'>+</div><div class='add'>+	ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	switch (dc-&gt;cmd) {</div><div class='add'>+	case V4L2_DEC_CMD_STOP:</div><div class='add'>+		ret = wave5_vpu_dec_stop(inst);</div><div class='add'>+		/* Just in case we don't have anything to decode anymore */</div><div class='add'>+		v4l2_m2m_try_schedule(m2m_ctx);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_DEC_CMD_START:</div><div class='add'>+		ret = wave5_vpu_dec_start(inst);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = {</div><div class='add'>+	.vidioc_querycap = wave5_vpu_dec_querycap,</div><div class='add'>+	.vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes,</div><div class='add'>+</div><div class='add'>+	.vidioc_enum_fmt_vid_cap	= wave5_vpu_dec_enum_fmt_cap,</div><div class='add'>+	.vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap,</div><div class='add'>+	.vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap,</div><div class='add'>+	.vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap,</div><div class='add'>+</div><div class='add'>+	.vidioc_enum_fmt_vid_out	= wave5_vpu_dec_enum_fmt_out,</div><div class='add'>+	.vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out,</div><div class='add'>+	.vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out,</div><div class='add'>+	.vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out,</div><div class='add'>+</div><div class='add'>+	.vidioc_g_selection = wave5_vpu_dec_g_selection,</div><div class='add'>+	.vidioc_s_selection = wave5_vpu_dec_s_selection,</div><div class='add'>+</div><div class='add'>+	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,</div><div class='add'>+	/*</div><div class='add'>+	 * Firmware does not support CREATE_BUFS for CAPTURE queue. Since</div><div class='add'>+	 * there is no immediate use-case for supporting CREATE_BUFS on</div><div class='add'>+	 * just the OUTPUT queue, disable CREATE_BUFS altogether.</div><div class='add'>+	 */</div><div class='add'>+	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,</div><div class='add'>+	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,</div><div class='add'>+	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,</div><div class='add'>+	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,</div><div class='add'>+	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,</div><div class='add'>+	.vidioc_streamon = v4l2_m2m_ioctl_streamon,</div><div class='add'>+	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,</div><div class='add'>+</div><div class='add'>+	.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd,</div><div class='add'>+	.vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd,</div><div class='add'>+</div><div class='add'>+	.vidioc_subscribe_event = wave5_vpu_subscribe_event,</div><div class='add'>+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,</div><div class='add'>+				     unsigned int *num_planes, unsigned int sizes[],</div><div class='add'>+				     struct device *alloc_devs[])</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_pix_format_mplane inst_format =</div><div class='add'>+		(q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst-&gt;src_fmt : inst-&gt;dst_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__,</div><div class='add'>+		*num_buffers, *num_planes, q-&gt;type);</div><div class='add'>+</div><div class='add'>+	*num_planes = inst_format.num_planes;</div><div class='add'>+</div><div class='add'>+	if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {</div><div class='add'>+		sizes[0] = inst_format.plane_fmt[0].sizeimage;</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: size[0]: %u\n", __func__, sizes[0]);</div><div class='add'>+	} else if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='add'>+		if (*num_buffers &lt; inst-&gt;fbc_buf_count)</div><div class='add'>+			*num_buffers = inst-&gt;fbc_buf_count;</div><div class='add'>+</div><div class='add'>+		if (*num_planes == 1) {</div><div class='add'>+			if (inst-&gt;output_format == FORMAT_422)</div><div class='add'>+				sizes[0] = inst_format.width * inst_format.height * 2;</div><div class='add'>+			else</div><div class='add'>+				sizes[0] = inst_format.width * inst_format.height * 3 / 2;</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: size[0]: %u\n", __func__, sizes[0]);</div><div class='add'>+		} else if (*num_planes == 2) {</div><div class='add'>+			sizes[0] = inst_format.width * inst_format.height;</div><div class='add'>+			if (inst-&gt;output_format == FORMAT_422)</div><div class='add'>+				sizes[1] = inst_format.width * inst_format.height;</div><div class='add'>+			else</div><div class='add'>+				sizes[1] = inst_format.width * inst_format.height / 2;</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: size[0]: %u | size[1]: %u\n",</div><div class='add'>+				__func__, sizes[0], sizes[1]);</div><div class='add'>+		} else if (*num_planes == 3) {</div><div class='add'>+			sizes[0] = inst_format.width * inst_format.height;</div><div class='add'>+			if (inst-&gt;output_format == FORMAT_422) {</div><div class='add'>+				sizes[1] = inst_format.width * inst_format.height / 2;</div><div class='add'>+				sizes[2] = inst_format.width * inst_format.height / 2;</div><div class='add'>+			} else {</div><div class='add'>+				sizes[1] = inst_format.width * inst_format.height / 4;</div><div class='add'>+				sizes[2] = inst_format.width * inst_format.height / 4;</div><div class='add'>+			}</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n",</div><div class='add'>+				__func__, sizes[0], sizes[1], sizes[2]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_prepare_fb(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int linear_num;</div><div class='add'>+	int non_linear_num;</div><div class='add'>+	int fb_stride = 0, fb_height = 0;</div><div class='add'>+	int luma_size, chroma_size;</div><div class='add'>+	int ret, i;</div><div class='add'>+	struct v4l2_m2m_buffer *buf, *n;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	linear_num = v4l2_m2m_num_dst_bufs_ready(m2m_ctx);</div><div class='add'>+	non_linear_num = inst-&gt;fbc_buf_count;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; non_linear_num; i++) {</div><div class='add'>+		struct frame_buffer *frame = &amp;inst-&gt;frame_buf[i];</div><div class='add'>+		struct vpu_buf *vframe = &amp;inst-&gt;frame_vbuf[i];</div><div class='add'>+</div><div class='add'>+		fb_stride = inst-&gt;dst_fmt.width;</div><div class='add'>+		fb_height = ALIGN(inst-&gt;dst_fmt.height, 32);</div><div class='add'>+		luma_size = fb_stride * fb_height;</div><div class='add'>+</div><div class='add'>+		chroma_size = ALIGN(fb_stride / 2, 16) * fb_height;</div><div class='add'>+</div><div class='add'>+		if (vframe-&gt;size == (luma_size + chroma_size))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (vframe-&gt;size)</div><div class='add'>+			wave5_vpu_dec_reset_framebuffer(inst, i);</div><div class='add'>+</div><div class='add'>+		vframe-&gt;size = luma_size + chroma_size;</div><div class='add'>+		ret = wave5_vdi_allocate_dma_memory(inst-&gt;dev, vframe);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Allocating FBC buf of size %zu, fail: %d\n",</div><div class='add'>+				__func__, vframe-&gt;size, ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		frame-&gt;buf_y = vframe-&gt;daddr;</div><div class='add'>+		frame-&gt;buf_cb = vframe-&gt;daddr + luma_size;</div><div class='add'>+		frame-&gt;buf_cr = (dma_addr_t)-1;</div><div class='add'>+		frame-&gt;size = vframe-&gt;size;</div><div class='add'>+		frame-&gt;width = inst-&gt;src_fmt.width;</div><div class='add'>+		frame-&gt;stride = fb_stride;</div><div class='add'>+		frame-&gt;map_type = COMPRESSED_FRAME_MAP;</div><div class='add'>+		frame-&gt;update_fb_info = true;</div><div class='add'>+	}</div><div class='add'>+	/* In case the count has reduced, clean up leftover framebuffer memory */</div><div class='add'>+	for (i = non_linear_num; i &lt; MAX_REG_FRAME; i++) {</div><div class='add'>+		ret = wave5_vpu_dec_reset_framebuffer(inst, i);</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; linear_num; i++) {</div><div class='add'>+		struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+		struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx);</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(dst_vq, i);</div><div class='add'>+		struct frame_buffer *frame = &amp;inst-&gt;frame_buf[non_linear_num + i];</div><div class='add'>+		dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0;</div><div class='add'>+		u32 buf_size = 0;</div><div class='add'>+		u32 fb_stride = inst-&gt;dst_fmt.width;</div><div class='add'>+		u32 luma_size = fb_stride * inst-&gt;dst_fmt.height;</div><div class='add'>+		u32 chroma_size;</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;output_format == FORMAT_422)</div><div class='add'>+			chroma_size = fb_stride * inst-&gt;dst_fmt.height / 2;</div><div class='add'>+		else</div><div class='add'>+			chroma_size = fb_stride * inst-&gt;dst_fmt.height / 4;</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;dst_fmt.num_planes == 1) {</div><div class='add'>+			buf_size = vb2_plane_size(vb, 0);</div><div class='add'>+			buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='add'>+			buf_addr_cb = buf_addr_y + luma_size;</div><div class='add'>+			buf_addr_cr = buf_addr_cb + chroma_size;</div><div class='add'>+		} else if (inst-&gt;dst_fmt.num_planes == 2) {</div><div class='add'>+			buf_size = vb2_plane_size(vb, 0) +</div><div class='add'>+				vb2_plane_size(vb, 1);</div><div class='add'>+			buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='add'>+			buf_addr_cb = vb2_dma_contig_plane_dma_addr(vb, 1);</div><div class='add'>+			buf_addr_cr = buf_addr_cb + chroma_size;</div><div class='add'>+		} else if (inst-&gt;dst_fmt.num_planes == 3) {</div><div class='add'>+			buf_size = vb2_plane_size(vb, 0) +</div><div class='add'>+				vb2_plane_size(vb, 1) +</div><div class='add'>+				vb2_plane_size(vb, 2);</div><div class='add'>+			buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='add'>+			buf_addr_cb = vb2_dma_contig_plane_dma_addr(vb, 1);</div><div class='add'>+			buf_addr_cr = vb2_dma_contig_plane_dma_addr(vb, 2);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		frame-&gt;buf_y = buf_addr_y;</div><div class='add'>+		frame-&gt;buf_cb = buf_addr_cb;</div><div class='add'>+		frame-&gt;buf_cr = buf_addr_cr;</div><div class='add'>+		frame-&gt;size = buf_size;</div><div class='add'>+		frame-&gt;width = inst-&gt;src_fmt.width;</div><div class='add'>+		frame-&gt;stride = fb_stride;</div><div class='add'>+		frame-&gt;map_type = LINEAR_FRAME_MAP;</div><div class='add'>+		frame-&gt;update_fb_info = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num,</div><div class='add'>+						     fb_stride, inst-&gt;dst_fmt.height);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Mark all frame buffers as out of display, to avoid using them before</div><div class='add'>+	 * the application have them queued.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; v4l2_m2m_num_dst_bufs_ready(m2m_ctx); i++) {</div><div class='add'>+		ret = wave5_vpu_dec_set_disp_flag(inst, i);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Setting display flag of buf index: %u, fail: %d\n",</div><div class='add'>+				__func__, i, ret);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buf, n) {</div><div class='add'>+		struct vb2_v4l2_buffer *vbuf = &amp;buf-&gt;vb;</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_dec_clr_disp_flag(inst, vbuf-&gt;vb2_buf.index);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Clearing display flag of buf index: %u, fail: %d\n",</div><div class='add'>+				__func__, i, ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int write_to_ringbuffer(struct vpu_instance *inst, void *buffer, size_t buffer_size,</div><div class='add'>+			       struct vpu_buf *ring_buffer, dma_addr_t wr_ptr)</div><div class='add'>+{</div><div class='add'>+	size_t size;</div><div class='add'>+	size_t offset = wr_ptr - ring_buffer-&gt;daddr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (wr_ptr + buffer_size &gt; ring_buffer-&gt;daddr + ring_buffer-&gt;size) {</div><div class='add'>+		size = ring_buffer-&gt;daddr + ring_buffer-&gt;size - wr_ptr;</div><div class='add'>+		ret = wave5_vdi_write_memory(inst-&gt;dev, ring_buffer, offset, (u8 *)buffer, size);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = wave5_vdi_write_memory(inst-&gt;dev, ring_buffer, 0, (u8 *)buffer + size,</div><div class='add'>+					     buffer_size - size);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+	} else {</div><div class='add'>+		ret = wave5_vdi_write_memory(inst-&gt;dev, ring_buffer, offset, (u8 *)buffer,</div><div class='add'>+					     buffer_size);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int fill_ringbuffer(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct v4l2_m2m_buffer *buf, *n;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (m2m_ctx-&gt;last_src_buf)  {</div><div class='add'>+		struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(m2m_ctx-&gt;last_src_buf);</div><div class='add'>+</div><div class='add'>+		if (vpu_buf-&gt;consumed) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "last src buffer already written\n");</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buf, n) {</div><div class='add'>+		struct vb2_v4l2_buffer *vbuf = &amp;buf-&gt;vb;</div><div class='add'>+		struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(vbuf);</div><div class='add'>+		struct vpu_buf *ring_buffer = &amp;inst-&gt;bitstream_vbuf;</div><div class='add'>+		size_t src_size = vb2_get_plane_payload(&amp;vbuf-&gt;vb2_buf, 0);</div><div class='add'>+		void *src_buf = vb2_plane_vaddr(&amp;vbuf-&gt;vb2_buf, 0);</div><div class='add'>+		dma_addr_t rd_ptr = 0;</div><div class='add'>+		dma_addr_t wr_ptr = 0;</div><div class='add'>+		size_t remain_size = 0;</div><div class='add'>+</div><div class='add'>+		if (vpu_buf-&gt;consumed) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "already copied src buf (%u) to the ring buffer\n",</div><div class='add'>+				vbuf-&gt;vb2_buf.index);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!src_buf) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Acquiring kernel pointer to src buf (%u), fail\n",</div><div class='add'>+				__func__, vbuf-&gt;vb2_buf.index);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_dec_get_bitstream_buffer(inst, &amp;rd_ptr, &amp;wr_ptr, &amp;remain_size);</div><div class='add'>+		if (ret) {</div><div class='add'>+			/* Unable to acquire the mutex */</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "Getting the bitstream buffer, fail: %d\n",</div><div class='add'>+				ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &amp;rd_ptr, &amp;wr_ptr);</div><div class='add'>+</div><div class='add'>+		if (remain_size &lt; src_size) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: remaining size: %zu &lt; source size: %zu for src buf (%u)\n",</div><div class='add'>+				__func__, remain_size, src_size, vbuf-&gt;vb2_buf.index);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = write_to_ringbuffer(inst, src_buf, src_size, ring_buffer, wr_ptr);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "Write src buf (%u) to ring buffer, fail: %d\n",</div><div class='add'>+				vbuf-&gt;vb2_buf.index, ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"update_bitstream_buffer fail: %d for src buf (%u)\n",</div><div class='add'>+				ret, vbuf-&gt;vb2_buf.index);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vpu_buf-&gt;consumed = true;</div><div class='add'>+</div><div class='add'>+		/* Don't write buffers passed the last one while draining. */</div><div class='add'>+		if (v4l2_m2m_is_last_draining_src_buf(m2m_ctx, vbuf)) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "last src buffer written to the ring buffer\n");</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(vbuf);</div><div class='add'>+</div><div class='add'>+	vpu_buf-&gt;consumed = false;</div><div class='add'>+	vbuf-&gt;sequence = inst-&gt;queued_src_buf_num++;</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_buf_queue(m2m_ctx, vbuf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	vbuf-&gt;sequence = inst-&gt;queued_dst_buf_num++;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;state == VPU_INST_STATE_PIC_RUN) {</div><div class='add'>+		struct vpu_dst_buffer *vpu_buf = wave5_to_vpu_dst_buf(vbuf);</div><div class='add'>+		int ret;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The buffer is already registered just clear the display flag</div><div class='add'>+		 * to let the firmware know it can be used.</div><div class='add'>+		 */</div><div class='add'>+		vpu_buf-&gt;display = false;</div><div class='add'>+		ret = wave5_vpu_dec_clr_disp_flag(inst, vb-&gt;index);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Clearing the display flag of buffer index: %u, fail: %d\n",</div><div class='add'>+				__func__, vb-&gt;index, ret);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vb2_is_streaming(vb-&gt;vb2_queue) &amp;&amp; v4l2_m2m_dst_buf_is_last(m2m_ctx)) {</div><div class='add'>+		unsigned int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; vb-&gt;num_planes; i++)</div><div class='add'>+			vb2_set_plane_payload(vb, i, 0);</div><div class='add'>+</div><div class='add'>+		vbuf-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+</div><div class='add'>+		send_eos_event(inst);</div><div class='add'>+		v4l2_m2m_last_buffer_done(m2m_ctx, vbuf);</div><div class='add'>+	} else {</div><div class='add'>+		v4l2_m2m_buf_queue(m2m_ctx, vbuf);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n",</div><div class='add'>+		__func__, vb-&gt;type, vb-&gt;index, vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 0),</div><div class='add'>+		vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 1), vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 2));</div><div class='add'>+</div><div class='add'>+	if (vb-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		wave5_vpu_dec_buf_queue_src(vb);</div><div class='add'>+	else if (vb-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)</div><div class='add'>+		wave5_vpu_dec_buf_queue_dst(vb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_allocate_ring_buffer(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_buf *ring_buffer = &amp;inst-&gt;bitstream_vbuf;</div><div class='add'>+</div><div class='add'>+	ring_buffer-&gt;size = ALIGN(inst-&gt;src_fmt.plane_fmt[0].sizeimage, 1024) * 4;</div><div class='add'>+	ret = wave5_vdi_allocate_dma_memory(inst-&gt;dev, ring_buffer);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: allocate ring buffer of size %zu fail: %d\n",</div><div class='add'>+			__func__, ring_buffer-&gt;size, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;last_rd_ptr = ring_buffer-&gt;daddr;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u\n", __func__, q-&gt;type);</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_update_start_streaming_state(m2m_ctx, q);</div><div class='add'>+</div><div class='add'>+	if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &amp;&amp; inst-&gt;state == VPU_INST_STATE_NONE) {</div><div class='add'>+		struct dec_open_param open_param;</div><div class='add'>+</div><div class='add'>+		memset(&amp;open_param, 0, sizeof(struct dec_open_param));</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_dec_allocate_ring_buffer(inst);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto return_buffers;</div><div class='add'>+</div><div class='add'>+		open_param.bitstream_buffer = inst-&gt;bitstream_vbuf.daddr;</div><div class='add'>+		open_param.bitstream_buffer_size = inst-&gt;bitstream_vbuf.size;</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_dec_open(inst, &amp;open_param);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: decoder opening, fail: %d\n",</div><div class='add'>+				__func__, ret);</div><div class='add'>+			goto free_bitstream_vbuf;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = switch_state(inst, VPU_INST_STATE_OPEN);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto free_bitstream_vbuf;</div><div class='add'>+	} else if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='add'>+		struct dec_initial_info *initial_info =</div><div class='add'>+			&amp;inst-&gt;codec_info-&gt;dec_info.initial_info;</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;state == VPU_INST_STATE_STOP)</div><div class='add'>+			ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto return_buffers;</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;state == VPU_INST_STATE_INIT_SEQ) {</div><div class='add'>+			if (initial_info-&gt;luma_bitdepth != 8) {</div><div class='add'>+				dev_info(inst-&gt;dev-&gt;dev, "%s: no support for %d bit depth",</div><div class='add'>+					 __func__, initial_info-&gt;luma_bitdepth);</div><div class='add'>+				ret = -EINVAL;</div><div class='add'>+				goto return_buffers;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+</div><div class='add'>+free_bitstream_vbuf:</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;inst-&gt;bitstream_vbuf);</div><div class='add'>+return_buffers:</div><div class='add'>+	wave5_return_bufs(q, VB2_BUF_STATE_QUEUED);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int streamoff_output(struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *buf;</div><div class='add'>+	int ret;</div><div class='add'>+	dma_addr_t new_rd_ptr;</div><div class='add'>+</div><div class='add'>+	while ((buf = v4l2_m2m_src_buf_remove(m2m_ctx))) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: (Multiplanar) buf type %4u | index %4u\n",</div><div class='add'>+			__func__, buf-&gt;vb2_buf.type, buf-&gt;vb2_buf.index);</div><div class='add'>+		v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_flush_instance(inst);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Reset the ring buffer information */</div><div class='add'>+	new_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst);</div><div class='add'>+	inst-&gt;last_rd_ptr = new_rd_ptr;</div><div class='add'>+	inst-&gt;codec_info-&gt;dec_info.stream_rd_ptr = new_rd_ptr;</div><div class='add'>+	inst-&gt;codec_info-&gt;dec_info.stream_wr_ptr = new_rd_ptr;</div><div class='add'>+</div><div class='add'>+	if (v4l2_m2m_has_stopped(m2m_ctx))</div><div class='add'>+		send_eos_event(inst);</div><div class='add'>+</div><div class='add'>+	/* streamoff on output cancels any draining operation */</div><div class='add'>+	inst-&gt;eos = false;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int streamoff_capture(struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *buf;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; v4l2_m2m_num_dst_bufs_ready(m2m_ctx); i++) {</div><div class='add'>+		ret = wave5_vpu_dec_set_disp_flag(inst, i);</div><div class='add'>+		if (ret)</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Setting display flag of buf index: %u, fail: %d\n",</div><div class='add'>+				__func__, i, ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	while ((buf = v4l2_m2m_dst_buf_remove(m2m_ctx))) {</div><div class='add'>+		u32 plane;</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: buf type %4u | index %4u\n",</div><div class='add'>+			__func__, buf-&gt;vb2_buf.type, buf-&gt;vb2_buf.index);</div><div class='add'>+</div><div class='add'>+		for (plane = 0; plane &lt; inst-&gt;dst_fmt.num_planes; plane++)</div><div class='add'>+			vb2_set_plane_payload(&amp;buf-&gt;vb2_buf, plane, 0);</div><div class='add'>+</div><div class='add'>+		v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;needs_reallocation) {</div><div class='add'>+		wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL);</div><div class='add'>+		inst-&gt;needs_reallocation = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (v4l2_m2m_has_stopped(m2m_ctx)) {</div><div class='add'>+		ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	bool check_cmd = TRUE;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u\n", __func__, q-&gt;type);</div><div class='add'>+</div><div class='add'>+	while (check_cmd) {</div><div class='add'>+		struct queue_status_info q_status;</div><div class='add'>+		struct dec_output_info dec_output_info;</div><div class='add'>+</div><div class='add'>+		wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &amp;q_status);</div><div class='add'>+</div><div class='add'>+		if (q_status.report_queue_count == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) &lt; 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (wave5_vpu_dec_get_output_info(inst, &amp;dec_output_info))</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "Getting decoding results from fw, fail\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_update_stop_streaming_state(m2m_ctx, q);</div><div class='add'>+</div><div class='add'>+	if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		streamoff_output(q);</div><div class='add'>+	else</div><div class='add'>+		streamoff_capture(q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vb2_ops wave5_vpu_dec_vb2_ops = {</div><div class='add'>+	.queue_setup = wave5_vpu_dec_queue_setup,</div><div class='add'>+	.wait_prepare = vb2_ops_wait_prepare,</div><div class='add'>+	.wait_finish = vb2_ops_wait_finish,</div><div class='add'>+	.buf_queue = wave5_vpu_dec_buf_queue,</div><div class='add'>+	.start_streaming = wave5_vpu_dec_start_streaming,</div><div class='add'>+	.stop_streaming = wave5_vpu_dec_stop_streaming,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt,</div><div class='add'>+				     struct v4l2_pix_format_mplane *dst_fmt)</div><div class='add'>+{</div><div class='add'>+	unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt;</div><div class='add'>+	const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt);</div><div class='add'>+</div><div class='add'>+	src_fmt-&gt;pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt;</div><div class='add'>+	src_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	src_fmt-&gt;flags = 0;</div><div class='add'>+	src_fmt-&gt;num_planes = 1;</div><div class='add'>+	wave5_update_pix_fmt(src_fmt, 720, 480);</div><div class='add'>+</div><div class='add'>+	dst_fmt-&gt;pixelformat = dst_pix_fmt;</div><div class='add'>+	dst_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	dst_fmt-&gt;flags = 0;</div><div class='add'>+	dst_fmt-&gt;num_planes = dst_fmt_info-&gt;mem_planes;</div><div class='add'>+	wave5_update_pix_fmt(dst_fmt, 736, 480);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)</div><div class='add'>+{</div><div class='add'>+	return wave5_vpu_queue_init(priv, src_vq, dst_vq, &amp;wave5_vpu_dec_vb2_ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = {</div><div class='add'>+	.finish_process = wave5_vpu_dec_finish_decode,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int initialize_sequence(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct dec_initial_info initial_info;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	memset(&amp;initial_info, 0, sizeof(struct dec_initial_info));</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_issue_seq_init(inst);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) &lt; 0)</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: failed to call vpu_wait_interrupt()\n", __func__);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_complete_seq_init(inst, &amp;initial_info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n",</div><div class='add'>+			__func__, ret, initial_info.seq_init_err_reason);</div><div class='add'>+		wave5_handle_src_buffer(inst, initial_info.rd_ptr);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	handle_dynamic_resolution_change(inst);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool wave5_is_draining_or_eos(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(&amp;inst-&gt;state_spinlock);</div><div class='add'>+	return m2m_ctx-&gt;is_draining || inst-&gt;eos;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_device_run(void *priv)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct queue_status_info q_status;</div><div class='add'>+	u32 fail_res = 0;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: Fill the ring buffer with new bitstream data", __func__);</div><div class='add'>+</div><div class='add'>+	ret = fill_ringbuffer(inst);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "Filling ring buffer failed\n");</div><div class='add'>+		goto finish_job_and_return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (inst-&gt;state) {</div><div class='add'>+	case VPU_INST_STATE_OPEN:</div><div class='add'>+		ret = initialize_sequence(inst);</div><div class='add'>+		if (ret) {</div><div class='add'>+			unsigned long flags;</div><div class='add'>+</div><div class='add'>+			spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+			if (wave5_is_draining_or_eos(inst) &amp;&amp;</div><div class='add'>+			    wave5_last_src_buffer_consumed(m2m_ctx)) {</div><div class='add'>+				struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx);</div><div class='add'>+</div><div class='add'>+				switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+</div><div class='add'>+				if (vb2_is_streaming(dst_vq))</div><div class='add'>+					send_eos_event(inst);</div><div class='add'>+				else</div><div class='add'>+					handle_dynamic_resolution_change(inst);</div><div class='add'>+</div><div class='add'>+				flag_last_buffer_done(inst);</div><div class='add'>+			}</div><div class='add'>+			spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+		} else {</div><div class='add'>+			switch_state(inst, VPU_INST_STATE_INIT_SEQ);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case VPU_INST_STATE_INIT_SEQ:</div><div class='add'>+		/*</div><div class='add'>+		 * Do this early, preparing the fb can trigger an IRQ before</div><div class='add'>+		 * we had a chance to switch, which leads to an invalid state</div><div class='add'>+		 * change.</div><div class='add'>+		 */</div><div class='add'>+		switch_state(inst, VPU_INST_STATE_PIC_RUN);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * During DRC, the picture decoding remains pending, so just leave the job</div><div class='add'>+		 * active until this decode operation completes.</div><div class='add'>+		 */</div><div class='add'>+		wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &amp;q_status);</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * The sequence must be analyzed first to calculate the proper</div><div class='add'>+		 * size of the auxiliary buffers.</div><div class='add'>+		 */</div><div class='add'>+		ret = wave5_prepare_fb(inst);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "Framebuffer preparation, fail: %d\n", ret);</div><div class='add'>+			switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (q_status.instance_queue_count) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: leave with active job", __func__);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		fallthrough;</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		ret = start_decode(inst, &amp;fail_res);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"Frame decoding on m2m context (%p), fail: %d (result: %d)\n",</div><div class='add'>+				m2m_ctx, ret, fail_res);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		/* Return so that we leave this job active */</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: leave with active job", __func__);</div><div class='add'>+		return;</div><div class='add'>+	default:</div><div class='add'>+		WARN(1, "Execution of a job in state %s illegal.\n", state_to_str(inst-&gt;state));</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+finish_job_and_return:</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: leave and finish job", __func__);</div><div class='add'>+	v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_dec_job_abort(void *priv)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+	if (ret)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_set_eos_on_firmware(inst);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev,</div><div class='add'>+			 "Setting EOS for the bitstream, fail: %d\n", ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_job_ready(void *priv)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+</div><div class='add'>+	switch (inst-&gt;state) {</div><div class='add'>+	case VPU_INST_STATE_NONE:</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "Decoder must be open to start queueing M2M jobs!\n");</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_OPEN:</div><div class='add'>+		if (wave5_is_draining_or_eos(inst) || !v4l2_m2m_has_stopped(m2m_ctx) ||</div><div class='add'>+		    v4l2_m2m_num_src_bufs_ready(m2m_ctx) &gt; 0) {</div><div class='add'>+			ret = 1;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Decoder must be draining or &gt;= 1 OUTPUT queue buffer must be queued!\n");</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_INIT_SEQ:</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		if (!m2m_ctx-&gt;cap_q_ctx.q.streaming) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "CAPTURE queue must be streaming to queue jobs!\n");</div><div class='add'>+			break;</div><div class='add'>+		} else if (v4l2_m2m_num_dst_bufs_ready(m2m_ctx) &lt; (inst-&gt;fbc_buf_count - 1)) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"No capture buffer ready to decode!\n");</div><div class='add'>+			break;</div><div class='add'>+		} else if (!wave5_is_draining_or_eos(inst) &amp;&amp;</div><div class='add'>+			   !v4l2_m2m_num_src_bufs_ready(m2m_ctx)) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"No bitstream data to decode!\n");</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		ret = 1;</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_STOP:</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "Decoder is stopped, not running.\n");</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;inst-&gt;state_spinlock, flags);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = {</div><div class='add'>+	.device_run = wave5_vpu_dec_device_run,</div><div class='add'>+	.job_abort = wave5_vpu_dec_job_abort,</div><div class='add'>+	.job_ready = wave5_vpu_dec_job_ready,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_open_dec(struct file *filp)</div><div class='add'>+{</div><div class='add'>+	struct video_device *vdev = video_devdata(filp);</div><div class='add'>+	struct vpu_device *dev = video_drvdata(filp);</div><div class='add'>+	struct vpu_instance *inst = NULL;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	inst = kzalloc(sizeof(*inst), GFP_KERNEL);</div><div class='add'>+	if (!inst)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	inst-&gt;dev = dev;</div><div class='add'>+	inst-&gt;type = VPU_INST_TYPE_DEC;</div><div class='add'>+	inst-&gt;ops = &amp;wave5_vpu_dec_inst_ops;</div><div class='add'>+</div><div class='add'>+	spin_lock_init(&amp;inst-&gt;state_spinlock);</div><div class='add'>+</div><div class='add'>+	inst-&gt;codec_info = kzalloc(sizeof(*inst-&gt;codec_info), GFP_KERNEL);</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	v4l2_fh_init(&amp;inst-&gt;v4l2_fh, vdev);</div><div class='add'>+	filp-&gt;private_data = &amp;inst-&gt;v4l2_fh;</div><div class='add'>+	v4l2_fh_add(&amp;inst-&gt;v4l2_fh);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;inst-&gt;list);</div><div class='add'>+	list_add_tail(&amp;inst-&gt;list, &amp;dev-&gt;instances);</div><div class='add'>+</div><div class='add'>+	inst-&gt;v4l2_m2m_dev = inst-&gt;dev-&gt;v4l2_m2m_dec_dev;</div><div class='add'>+	inst-&gt;v4l2_fh.m2m_ctx =</div><div class='add'>+		v4l2_m2m_ctx_init(inst-&gt;v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init);</div><div class='add'>+	if (IS_ERR(inst-&gt;v4l2_fh.m2m_ctx)) {</div><div class='add'>+		ret = PTR_ERR(inst-&gt;v4l2_fh.m2m_ctx);</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+	m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_set_src_buffered(m2m_ctx, true);</div><div class='add'>+	v4l2_m2m_set_dst_buffered(m2m_ctx, true);</div><div class='add'>+	/*</div><div class='add'>+	 * We use the M2M job queue to ensure synchronization of steps where</div><div class='add'>+	 * needed, as IOCTLs can occur at anytime and we need to run commands on</div><div class='add'>+	 * the firmware in a specified order.</div><div class='add'>+	 * In order to initialize the sequence on the firmware within an M2M</div><div class='add'>+	 * job, the M2M framework needs to be able to queue jobs before</div><div class='add'>+	 * the CAPTURE queue has been started, because we need the results of the</div><div class='add'>+	 * initialization to properly prepare the CAPTURE queue with the correct</div><div class='add'>+	 * amount of buffers.</div><div class='add'>+	 * By setting ignore_cap_streaming to true the m2m framework will call</div><div class='add'>+	 * job_ready as soon as the OUTPUT queue is streaming, instead of</div><div class='add'>+	 * waiting until both the CAPTURE and OUTPUT queues are streaming.</div><div class='add'>+	 */</div><div class='add'>+	m2m_ctx-&gt;ignore_cap_streaming = true;</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_handler_init(&amp;inst-&gt;v4l2_ctrl_hdl, 10);</div><div class='add'>+	v4l2_ctrl_new_std(&amp;inst-&gt;v4l2_ctrl_hdl, NULL,</div><div class='add'>+			  V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;v4l2_ctrl_hdl.error) {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;v4l2_fh.ctrl_handler = &amp;inst-&gt;v4l2_ctrl_hdl;</div><div class='add'>+	v4l2_ctrl_handler_setup(&amp;inst-&gt;v4l2_ctrl_hdl);</div><div class='add'>+</div><div class='add'>+	wave5_set_default_format(&amp;inst-&gt;src_fmt, &amp;inst-&gt;dst_fmt);</div><div class='add'>+	inst-&gt;colorspace = V4L2_COLORSPACE_REC709;</div><div class='add'>+	inst-&gt;ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;</div><div class='add'>+	inst-&gt;quantization = V4L2_QUANTIZATION_DEFAULT;</div><div class='add'>+	inst-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='add'>+</div><div class='add'>+	init_completion(&amp;inst-&gt;irq_done);</div><div class='add'>+</div><div class='add'>+	inst-&gt;id = ida_alloc(&amp;inst-&gt;dev-&gt;inst_ida, GFP_KERNEL);</div><div class='add'>+	if (inst-&gt;id &lt; 0) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "Allocating instance ID, fail: %d\n", inst-&gt;id);</div><div class='add'>+		ret = inst-&gt;id;</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_vdi_allocate_sram(inst-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+cleanup_inst:</div><div class='add'>+	wave5_cleanup_instance(inst);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_dec_release(struct file *filp)</div><div class='add'>+{</div><div class='add'>+	return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_file_operations wave5_vpu_dec_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = wave5_vpu_open_dec,</div><div class='add'>+	.release = wave5_vpu_dec_release,</div><div class='add'>+	.unlocked_ioctl = video_ioctl2,</div><div class='add'>+	.poll = v4l2_m2m_fop_poll,</div><div class='add'>+	.mmap = v4l2_m2m_fop_mmap,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_register_device(struct vpu_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct video_device *vdev_dec;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vdev_dec = devm_kzalloc(dev-&gt;v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL);</div><div class='add'>+	if (!vdev_dec)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	dev-&gt;v4l2_m2m_dec_dev = v4l2_m2m_init(&amp;wave5_vpu_dec_m2m_ops);</div><div class='add'>+	if (IS_ERR(dev-&gt;v4l2_m2m_dec_dev)) {</div><div class='add'>+		ret = PTR_ERR(dev-&gt;v4l2_m2m_dec_dev);</div><div class='add'>+		dev_err(dev-&gt;dev, "v4l2_m2m_init, fail: %d\n", ret);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev-&gt;video_dev_dec = vdev_dec;</div><div class='add'>+</div><div class='add'>+	strscpy(vdev_dec-&gt;name, VPU_DEC_DEV_NAME, sizeof(vdev_dec-&gt;name));</div><div class='add'>+	vdev_dec-&gt;fops = &amp;wave5_vpu_dec_fops;</div><div class='add'>+	vdev_dec-&gt;ioctl_ops = &amp;wave5_vpu_dec_ioctl_ops;</div><div class='add'>+	vdev_dec-&gt;release = video_device_release_empty;</div><div class='add'>+	vdev_dec-&gt;v4l2_dev = &amp;dev-&gt;v4l2_dev;</div><div class='add'>+	vdev_dec-&gt;vfl_dir = VFL_DIR_M2M;</div><div class='add'>+	vdev_dec-&gt;device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;</div><div class='add'>+	vdev_dec-&gt;lock = &amp;dev-&gt;dev_lock;</div><div class='add'>+</div><div class='add'>+	ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	video_set_drvdata(vdev_dec, dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_vpu_dec_unregister_device(struct vpu_device *dev)</div><div class='add'>+{</div><div class='add'>+	video_unregister_device(dev-&gt;video_dev_dec);</div><div class='add'>+	if (dev-&gt;v4l2_m2m_dec_dev)</div><div class='add'>+		v4l2_m2m_release(dev-&gt;v4l2_m2m_dec_dev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c<br/>new file mode 100644<br/>index 000000000000..f29cfa3af94a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c</a></div><div class='hunk'>@@ -0,0 +1,1794 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - encoder interface</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "wave5-helper.h"</div><div class='add'>+</div><div class='add'>+#define VPU_ENC_DEV_NAME "C&amp;M Wave5 VPU encoder"</div><div class='add'>+#define VPU_ENC_DRV_NAME "wave5-enc"</div><div class='add'>+</div><div class='add'>+static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = {</div><div class='add'>+	[VPU_FMT_TYPE_CODEC] = {</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_HEVC,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_H264,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[VPU_FMT_TYPE_RAW] = {</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV420,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV12,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV21,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV12M,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+		{</div><div class='add'>+			.v4l2_pix_fmt = V4L2_PIX_FMT_NV21M,</div><div class='add'>+			.max_width = W5_MAX_ENC_PIC_WIDTH,</div><div class='add'>+			.min_width = W5_MIN_ENC_PIC_WIDTH,</div><div class='add'>+			.max_height = W5_MAX_ENC_PIC_HEIGHT,</div><div class='add'>+			.min_height = W5_MIN_ENC_PIC_HEIGHT,</div><div class='add'>+		},</div><div class='add'>+	}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state)</div><div class='add'>+{</div><div class='add'>+	switch (state) {</div><div class='add'>+	case VPU_INST_STATE_NONE:</div><div class='add'>+		goto invalid_state_switch;</div><div class='add'>+	case VPU_INST_STATE_OPEN:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_NONE)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_INIT_SEQ:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_OPEN &amp;&amp; inst-&gt;state != VPU_INST_STATE_STOP)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		if (inst-&gt;state != VPU_INST_STATE_INIT_SEQ)</div><div class='add'>+			goto invalid_state_switch;</div><div class='add'>+		break;</div><div class='add'>+	case VPU_INST_STATE_STOP:</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "Switch state from %s to %s.\n",</div><div class='add'>+		state_to_str(inst-&gt;state), state_to_str(state));</div><div class='add'>+	inst-&gt;state = state;</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+invalid_state_switch:</div><div class='add'>+	WARN(1, "Invalid state switch from %s to %s.\n",</div><div class='add'>+	     state_to_str(inst-&gt;state), state_to_str(state));</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width,</div><div class='add'>+				 unsigned int height)</div><div class='add'>+{</div><div class='add'>+	switch (pix_mp-&gt;pixelformat) {</div><div class='add'>+	case V4L2_PIX_FMT_YUV420:</div><div class='add'>+	case V4L2_PIX_FMT_NV12:</div><div class='add'>+	case V4L2_PIX_FMT_NV21:</div><div class='add'>+		pix_mp-&gt;width = width;</div><div class='add'>+		pix_mp-&gt;height = height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_YUV420M:</div><div class='add'>+		pix_mp-&gt;width = width;</div><div class='add'>+		pix_mp-&gt;height = height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = round_up(width, 32) * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = round_up(width, 32) * height / 4;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].bytesperline = round_up(width, 32) / 2;</div><div class='add'>+		pix_mp-&gt;plane_fmt[2].sizeimage = round_up(width, 32) * height / 4;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_NV12M:</div><div class='add'>+	case V4L2_PIX_FMT_NV21M:</div><div class='add'>+		pix_mp-&gt;width = width;</div><div class='add'>+		pix_mp-&gt;height = height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = round_up(width, 32) * height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = round_up(width, 32);</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].sizeimage = round_up(width, 32) * height / 2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		pix_mp-&gt;width = width;</div><div class='add'>+		pix_mp-&gt;height = height;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = 0;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].sizeimage = width * height / 8 * 3;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int start_encode(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vb2_v4l2_buffer *src_buf;</div><div class='add'>+	struct vb2_v4l2_buffer *dst_buf;</div><div class='add'>+	struct frame_buffer frame_buf;</div><div class='add'>+	struct enc_param pic_param;</div><div class='add'>+	u32 stride = ALIGN(inst-&gt;dst_fmt.width, 32);</div><div class='add'>+	u32 luma_size = (stride * inst-&gt;dst_fmt.height);</div><div class='add'>+	u32 chroma_size = ((stride / 2) * (inst-&gt;dst_fmt.height / 2));</div><div class='add'>+</div><div class='add'>+	memset(&amp;pic_param, 0, sizeof(struct enc_param));</div><div class='add'>+	memset(&amp;frame_buf, 0, sizeof(struct frame_buffer));</div><div class='add'>+</div><div class='add'>+	dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx);</div><div class='add'>+	if (!dst_buf) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: No destination buffer found\n", __func__);</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pic_param.pic_stream_buffer_addr =</div><div class='add'>+		vb2_dma_contig_plane_dma_addr(&amp;dst_buf-&gt;vb2_buf, 0);</div><div class='add'>+	pic_param.pic_stream_buffer_size =</div><div class='add'>+		vb2_plane_size(&amp;dst_buf-&gt;vb2_buf, 0);</div><div class='add'>+</div><div class='add'>+	src_buf = v4l2_m2m_next_src_buf(m2m_ctx);</div><div class='add'>+	if (!src_buf) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: No source buffer found\n", __func__);</div><div class='add'>+		if (m2m_ctx-&gt;is_draining)</div><div class='add'>+			pic_param.src_end_flag = 1;</div><div class='add'>+		else</div><div class='add'>+			return -EAGAIN;</div><div class='add'>+	} else {</div><div class='add'>+		if (inst-&gt;src_fmt.num_planes == 1) {</div><div class='add'>+			frame_buf.buf_y =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 0);</div><div class='add'>+			frame_buf.buf_cb = frame_buf.buf_y + luma_size;</div><div class='add'>+			frame_buf.buf_cr = frame_buf.buf_cb + chroma_size;</div><div class='add'>+		} else if (inst-&gt;src_fmt.num_planes == 2) {</div><div class='add'>+			frame_buf.buf_y =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 0);</div><div class='add'>+			frame_buf.buf_cb =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 1);</div><div class='add'>+			frame_buf.buf_cr = frame_buf.buf_cb + chroma_size;</div><div class='add'>+		} else if (inst-&gt;src_fmt.num_planes == 3) {</div><div class='add'>+			frame_buf.buf_y =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 0);</div><div class='add'>+			frame_buf.buf_cb =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 1);</div><div class='add'>+			frame_buf.buf_cr =</div><div class='add'>+				vb2_dma_contig_plane_dma_addr(&amp;src_buf-&gt;vb2_buf, 2);</div><div class='add'>+		}</div><div class='add'>+		frame_buf.stride = stride;</div><div class='add'>+		pic_param.src_idx = src_buf-&gt;vb2_buf.index;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pic_param.source_frame = &amp;frame_buf;</div><div class='add'>+	pic_param.code_option.implicit_header_encode = 1;</div><div class='add'>+	pic_param.code_option.encode_aud = inst-&gt;encode_aud;</div><div class='add'>+	ret = wave5_vpu_enc_start_one_frame(inst, &amp;pic_param, fail_res);</div><div class='add'>+	if (ret) {</div><div class='add'>+		if (*fail_res == WAVE5_SYSERR_QUEUEING_FAIL)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		src_buf = v4l2_m2m_src_buf_remove(m2m_ctx);</div><div class='add'>+		if (!src_buf) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Removing src buf failed, the queue is empty\n",</div><div class='add'>+				__func__);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx);</div><div class='add'>+		if (!dst_buf) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+				"%s: Removing dst buf failed, the queue is empty\n",</div><div class='add'>+				__func__);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+		dst_buf-&gt;vb2_buf.timestamp = src_buf-&gt;vb2_buf.timestamp;</div><div class='add'>+		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+		v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+	} else {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_enc_start_one_frame success\n",</div><div class='add'>+			__func__);</div><div class='add'>+		/*</div><div class='add'>+		 * Remove the source buffer from the ready-queue now and finish</div><div class='add'>+		 * it in the videobuf2 framework once the index is returned by the</div><div class='add'>+		 * firmware in finish_encode</div><div class='add'>+		 */</div><div class='add'>+		if (src_buf)</div><div class='add'>+			v4l2_m2m_src_buf_remove_by_idx(m2m_ctx, src_buf-&gt;vb2_buf.index);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret;</div><div class='add'>+	struct enc_output_info enc_output_info;</div><div class='add'>+	struct vb2_v4l2_buffer *src_buf = NULL;</div><div class='add'>+	struct vb2_v4l2_buffer *dst_buf = NULL;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_get_output_info(inst, &amp;enc_output_info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"%s: vpu_enc_get_output_info fail: %d  reason: %u | info: %u\n",</div><div class='add'>+			__func__, ret, enc_output_info.error_reason, enc_output_info.warn_info);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+		"%s: pic_type %i recon_idx %i src_idx %i pic_byte %u pts %llu\n",</div><div class='add'>+		__func__,  enc_output_info.pic_type, enc_output_info.recon_frame_index,</div><div class='add'>+		enc_output_info.enc_src_idx, enc_output_info.enc_pic_byte, enc_output_info.pts);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The source buffer will not be found in the ready-queue as it has been</div><div class='add'>+	 * dropped after sending of the encode firmware command, locate it in</div><div class='add'>+	 * the videobuf2 queue directly</div><div class='add'>+	 */</div><div class='add'>+	if (enc_output_info.enc_src_idx &gt;= 0) {</div><div class='add'>+		struct vb2_buffer *vb = vb2_get_buffer(v4l2_m2m_get_src_vq(m2m_ctx),</div><div class='add'>+						       enc_output_info.enc_src_idx);</div><div class='add'>+		if (vb-&gt;state != VB2_BUF_STATE_ACTIVE)</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev,</div><div class='add'>+				 "%s: encoded buffer (%d) was not in ready queue %i.",</div><div class='add'>+				 __func__, enc_output_info.enc_src_idx, vb-&gt;state);</div><div class='add'>+		else</div><div class='add'>+			src_buf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+</div><div class='add'>+		if (src_buf) {</div><div class='add'>+			inst-&gt;timestamp = src_buf-&gt;vb2_buf.timestamp;</div><div class='add'>+			v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);</div><div class='add'>+		} else {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "%s: no source buffer with index: %d found\n",</div><div class='add'>+				 __func__, enc_output_info.enc_src_idx);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx);</div><div class='add'>+	if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) {</div><div class='add'>+		static const struct v4l2_event vpu_event_eos = {</div><div class='add'>+			.type = V4L2_EVENT_EOS</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		if (!WARN_ON(!dst_buf)) {</div><div class='add'>+			vb2_set_plane_payload(&amp;dst_buf-&gt;vb2_buf, 0, 0);</div><div class='add'>+			dst_buf-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+			v4l2_m2m_last_buffer_done(m2m_ctx, dst_buf);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		v4l2_event_queue_fh(&amp;inst-&gt;v4l2_fh, &amp;vpu_event_eos);</div><div class='add'>+</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+	} else {</div><div class='add'>+		if (!dst_buf) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "No bitstream buffer.");</div><div class='add'>+			v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		vb2_set_plane_payload(&amp;dst_buf-&gt;vb2_buf, 0, enc_output_info.bitstream_size);</div><div class='add'>+</div><div class='add'>+		dst_buf-&gt;vb2_buf.timestamp = inst-&gt;timestamp;</div><div class='add'>+		dst_buf-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+		if (enc_output_info.pic_type == PIC_TYPE_I) {</div><div class='add'>+			if (enc_output_info.enc_vcl_nut == 19 ||</div><div class='add'>+			    enc_output_info.enc_vcl_nut == 20)</div><div class='add'>+				dst_buf-&gt;flags |= V4L2_BUF_FLAG_KEYFRAME;</div><div class='add'>+			else</div><div class='add'>+				dst_buf-&gt;flags |= V4L2_BUF_FLAG_PFRAME;</div><div class='add'>+		} else if (enc_output_info.pic_type == PIC_TYPE_P) {</div><div class='add'>+			dst_buf-&gt;flags |= V4L2_BUF_FLAG_PFRAME;</div><div class='add'>+		} else if (enc_output_info.pic_type == PIC_TYPE_B) {</div><div class='add'>+			dst_buf-&gt;flags |= V4L2_BUF_FLAG_BFRAME;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);</div><div class='add'>+</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: frame_cycle %8u\n",</div><div class='add'>+			__func__, enc_output_info.frame_cycle);</div><div class='add'>+</div><div class='add'>+		v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap)</div><div class='add'>+{</div><div class='add'>+	strscpy(cap-&gt;driver, VPU_ENC_DRV_NAME, sizeof(cap-&gt;driver));</div><div class='add'>+	strscpy(cap-&gt;card, VPU_ENC_DRV_NAME, sizeof(cap-&gt;card));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize)</div><div class='add'>+{</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	if (fsize-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(fsize-&gt;pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		vpu_fmt = wave5_find_vpu_fmt(fsize-&gt;pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+		if (!vpu_fmt)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fsize-&gt;type = V4L2_FRMSIZE_TYPE_CONTINUOUS;</div><div class='add'>+	fsize-&gt;stepwise.min_width = vpu_fmt-&gt;min_width;</div><div class='add'>+	fsize-&gt;stepwise.max_width = vpu_fmt-&gt;max_width;</div><div class='add'>+	fsize-&gt;stepwise.step_width = 1;</div><div class='add'>+	fsize-&gt;stepwise.min_height = vpu_fmt-&gt;min_height;</div><div class='add'>+	fsize-&gt;stepwise.max_height = vpu_fmt-&gt;max_height;</div><div class='add'>+	fsize-&gt;stepwise.step_height = 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: index: %u\n", __func__, f-&gt;index);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt_by_idx(f-&gt;index, enc_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	f-&gt;pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+	f-&gt;flags = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(f-&gt;fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = inst-&gt;dst_fmt.pixelformat;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = inst-&gt;dst_fmt.num_planes;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, inst-&gt;dst_fmt.width, inst-&gt;dst_fmt.height);</div><div class='add'>+	} else {</div><div class='add'>+		int width = clamp(f-&gt;fmt.pix_mp.width, vpu_fmt-&gt;min_width, vpu_fmt-&gt;max_width);</div><div class='add'>+		int height = clamp(f-&gt;fmt.pix_mp.height, vpu_fmt-&gt;min_height, vpu_fmt-&gt;max_height);</div><div class='add'>+</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = 1;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, width, height);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = 0;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = V4L2_FIELD_NONE;</div><div class='add'>+	f-&gt;fmt.pix_mp.colorspace = inst-&gt;colorspace;</div><div class='add'>+	f-&gt;fmt.pix_mp.ycbcr_enc = inst-&gt;ycbcr_enc;</div><div class='add'>+	f-&gt;fmt.pix_mp.quantization = inst-&gt;quantization;</div><div class='add'>+	f-&gt;fmt.pix_mp.xfer_func = inst-&gt;xfer_func;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_try_fmt_cap(file, fh, f);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	inst-&gt;std = wave5_to_vpu_std(f-&gt;fmt.pix_mp.pixelformat, inst-&gt;type);</div><div class='add'>+	if (inst-&gt;std == STD_UNKNOWN) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "unsupported pixelformat: %.4s\n",</div><div class='add'>+			 (char *)&amp;f-&gt;fmt.pix_mp.pixelformat);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;dst_fmt.width = f-&gt;fmt.pix_mp.width;</div><div class='add'>+	inst-&gt;dst_fmt.height = f-&gt;fmt.pix_mp.height;</div><div class='add'>+	inst-&gt;dst_fmt.pixelformat = f-&gt;fmt.pix_mp.pixelformat;</div><div class='add'>+	inst-&gt;dst_fmt.field = f-&gt;fmt.pix_mp.field;</div><div class='add'>+	inst-&gt;dst_fmt.flags = f-&gt;fmt.pix_mp.flags;</div><div class='add'>+	inst-&gt;dst_fmt.num_planes = f-&gt;fmt.pix_mp.num_planes;</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;dst_fmt.num_planes; i++) {</div><div class='add'>+		inst-&gt;dst_fmt.plane_fmt[i].bytesperline = f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline;</div><div class='add'>+		inst-&gt;dst_fmt.plane_fmt[i].sizeimage = f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.width = inst-&gt;dst_fmt.width;</div><div class='add'>+	f-&gt;fmt.pix_mp.height = inst-&gt;dst_fmt.height;</div><div class='add'>+	f-&gt;fmt.pix_mp.pixelformat = inst-&gt;dst_fmt.pixelformat;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = inst-&gt;dst_fmt.field;</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = inst-&gt;dst_fmt.flags;</div><div class='add'>+	f-&gt;fmt.pix_mp.num_planes = inst-&gt;dst_fmt.num_planes;</div><div class='add'>+	for (i = 0; i &lt; f-&gt;fmt.pix_mp.num_planes; i++) {</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline = inst-&gt;dst_fmt.plane_fmt[i].bytesperline;</div><div class='add'>+		f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage = inst-&gt;dst_fmt.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.colorspace = inst-&gt;colorspace;</div><div class='add'>+	f-&gt;fmt.pix_mp.ycbcr_enc = inst-&gt;ycbcr_enc;</div><div class='add'>+	f-&gt;fmt.pix_mp.quantization = inst-&gt;quantization;</div><div class='add'>+	f-&gt;fmt.pix_mp.xfer_func = inst-&gt;xfer_func;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: index: %u\n", __func__, f-&gt;index);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt_by_idx(f-&gt;index, enc_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+	if (!vpu_fmt)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	f-&gt;pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+	f-&gt;flags = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	const struct vpu_format *vpu_fmt;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	vpu_fmt = wave5_find_vpu_fmt(f-&gt;fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]);</div><div class='add'>+	if (!vpu_fmt) {</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = inst-&gt;src_fmt.pixelformat;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = inst-&gt;src_fmt.num_planes;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, inst-&gt;src_fmt.width, inst-&gt;src_fmt.height);</div><div class='add'>+	} else {</div><div class='add'>+		int width = clamp(f-&gt;fmt.pix_mp.width, vpu_fmt-&gt;min_width, vpu_fmt-&gt;max_width);</div><div class='add'>+		int height = clamp(f-&gt;fmt.pix_mp.height, vpu_fmt-&gt;min_height, vpu_fmt-&gt;max_height);</div><div class='add'>+		const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt-&gt;v4l2_pix_fmt);</div><div class='add'>+</div><div class='add'>+		f-&gt;fmt.pix_mp.pixelformat = vpu_fmt-&gt;v4l2_pix_fmt;</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes = info-&gt;mem_planes;</div><div class='add'>+		wave5_update_pix_fmt(&amp;f-&gt;fmt.pix_mp, width, height);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix_mp.flags = 0;</div><div class='add'>+	f-&gt;fmt.pix_mp.field = V4L2_FIELD_NONE;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n",</div><div class='add'>+		__func__, f-&gt;fmt.pix_mp.pixelformat, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height,</div><div class='add'>+		f-&gt;fmt.pix_mp.num_planes, f-&gt;fmt.pix_mp.field);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_try_fmt_out(file, fh, f);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	inst-&gt;src_fmt.width = f-&gt;fmt.pix_mp.width;</div><div class='add'>+	inst-&gt;src_fmt.height = f-&gt;fmt.pix_mp.height;</div><div class='add'>+	inst-&gt;src_fmt.pixelformat = f-&gt;fmt.pix_mp.pixelformat;</div><div class='add'>+	inst-&gt;src_fmt.field = f-&gt;fmt.pix_mp.field;</div><div class='add'>+	inst-&gt;src_fmt.flags = f-&gt;fmt.pix_mp.flags;</div><div class='add'>+	inst-&gt;src_fmt.num_planes = f-&gt;fmt.pix_mp.num_planes;</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;src_fmt.num_planes; i++) {</div><div class='add'>+		inst-&gt;src_fmt.plane_fmt[i].bytesperline = f-&gt;fmt.pix_mp.plane_fmt[i].bytesperline;</div><div class='add'>+		inst-&gt;src_fmt.plane_fmt[i].sizeimage = f-&gt;fmt.pix_mp.plane_fmt[i].sizeimage;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;src_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||</div><div class='add'>+	    inst-&gt;src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+	} else if (inst-&gt;src_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||</div><div class='add'>+		   inst-&gt;src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {</div><div class='add'>+		inst-&gt;cbcr_interleave = true;</div><div class='add'>+		inst-&gt;nv21 = true;</div><div class='add'>+	} else {</div><div class='add'>+		inst-&gt;cbcr_interleave = false;</div><div class='add'>+		inst-&gt;nv21 = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;colorspace = f-&gt;fmt.pix_mp.colorspace;</div><div class='add'>+	inst-&gt;ycbcr_enc = f-&gt;fmt.pix_mp.ycbcr_enc;</div><div class='add'>+	inst-&gt;quantization = f-&gt;fmt.pix_mp.quantization;</div><div class='add'>+	inst-&gt;xfer_func = f-&gt;fmt.pix_mp.xfer_func;</div><div class='add'>+</div><div class='add'>+	wave5_update_pix_fmt(&amp;inst-&gt;dst_fmt, f-&gt;fmt.pix_mp.width, f-&gt;fmt.pix_mp.height);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u | target: %u\n", __func__, s-&gt;type, s-&gt;target);</div><div class='add'>+</div><div class='add'>+	if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	switch (s-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		s-&gt;r.left = 0;</div><div class='add'>+		s-&gt;r.top = 0;</div><div class='add'>+		s-&gt;r.width = inst-&gt;dst_fmt.width;</div><div class='add'>+		s-&gt;r.height = inst-&gt;dst_fmt.height;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (s-&gt;target != V4L2_SEL_TGT_CROP)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n",</div><div class='add'>+		__func__, s-&gt;r.width, s-&gt;r.height);</div><div class='add'>+</div><div class='add'>+	s-&gt;r.left = 0;</div><div class='add'>+	s-&gt;r.top = 0;</div><div class='add'>+	s-&gt;r.width = inst-&gt;src_fmt.width;</div><div class='add'>+	s-&gt;r.height = inst-&gt;src_fmt.height;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_both_queues_are_streaming(inst))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (ec-&gt;cmd) {</div><div class='add'>+	case V4L2_ENC_CMD_STOP:</div><div class='add'>+		if (m2m_ctx-&gt;is_draining)</div><div class='add'>+			return -EBUSY;</div><div class='add'>+</div><div class='add'>+		if (m2m_ctx-&gt;has_stopped)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		m2m_ctx-&gt;last_src_buf = v4l2_m2m_last_src_buf(m2m_ctx);</div><div class='add'>+		m2m_ctx-&gt;is_draining = true;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_ENC_CMD_START:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u\n", __func__, a-&gt;type);</div><div class='add'>+</div><div class='add'>+	if (a-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT &amp;&amp; a-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	a-&gt;parm.output.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='add'>+	a-&gt;parm.output.timeperframe.numerator = 1;</div><div class='add'>+	a-&gt;parm.output.timeperframe.denominator = inst-&gt;frame_rate;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: numerator: %u | denominator: %u\n",</div><div class='add'>+		__func__, a-&gt;parm.output.timeperframe.numerator,</div><div class='add'>+		a-&gt;parm.output.timeperframe.denominator);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_to_vpu_inst(fh);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u\n", __func__, a-&gt;type);</div><div class='add'>+</div><div class='add'>+	if (a-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT &amp;&amp; a-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	a-&gt;parm.output.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='add'>+	if (a-&gt;parm.output.timeperframe.denominator &amp;&amp; a-&gt;parm.output.timeperframe.numerator) {</div><div class='add'>+		inst-&gt;frame_rate = a-&gt;parm.output.timeperframe.denominator /</div><div class='add'>+				   a-&gt;parm.output.timeperframe.numerator;</div><div class='add'>+	} else {</div><div class='add'>+		a-&gt;parm.output.timeperframe.numerator = 1;</div><div class='add'>+		a-&gt;parm.output.timeperframe.denominator = inst-&gt;frame_rate;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: numerator: %u | denominator: %u\n",</div><div class='add'>+		__func__, a-&gt;parm.output.timeperframe.numerator,</div><div class='add'>+		a-&gt;parm.output.timeperframe.denominator);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = {</div><div class='add'>+	.vidioc_querycap = wave5_vpu_enc_querycap,</div><div class='add'>+	.vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes,</div><div class='add'>+</div><div class='add'>+	.vidioc_enum_fmt_vid_cap	= wave5_vpu_enc_enum_fmt_cap,</div><div class='add'>+	.vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap,</div><div class='add'>+	.vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap,</div><div class='add'>+	.vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap,</div><div class='add'>+</div><div class='add'>+	.vidioc_enum_fmt_vid_out	= wave5_vpu_enc_enum_fmt_out,</div><div class='add'>+	.vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out,</div><div class='add'>+	.vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out,</div><div class='add'>+	.vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out,</div><div class='add'>+</div><div class='add'>+	.vidioc_g_selection = wave5_vpu_enc_g_selection,</div><div class='add'>+	.vidioc_s_selection = wave5_vpu_enc_s_selection,</div><div class='add'>+</div><div class='add'>+	.vidioc_g_parm = wave5_vpu_enc_g_parm,</div><div class='add'>+	.vidioc_s_parm = wave5_vpu_enc_s_parm,</div><div class='add'>+</div><div class='add'>+	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,</div><div class='add'>+	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,</div><div class='add'>+	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,</div><div class='add'>+	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,</div><div class='add'>+	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,</div><div class='add'>+	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,</div><div class='add'>+	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,</div><div class='add'>+	.vidioc_streamon = v4l2_m2m_ioctl_streamon,</div><div class='add'>+	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,</div><div class='add'>+</div><div class='add'>+	.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,</div><div class='add'>+	.vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd,</div><div class='add'>+</div><div class='add'>+	.vidioc_subscribe_event = wave5_vpu_subscribe_event,</div><div class='add'>+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: name: %s | value: %d\n", __func__, ctrl-&gt;name, ctrl-&gt;val);</div><div class='add'>+</div><div class='add'>+	switch (ctrl-&gt;id) {</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_AU_DELIMITER:</div><div class='add'>+		inst-&gt;encode_aud = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_HFLIP:</div><div class='add'>+		inst-&gt;mirror_direction |= (ctrl-&gt;val &lt;&lt; 1);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_VFLIP:</div><div class='add'>+		inst-&gt;mirror_direction |= ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_ROTATE:</div><div class='add'>+		inst-&gt;rot_angle = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_VBV_SIZE:</div><div class='add'>+		inst-&gt;vbv_buf_size = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:</div><div class='add'>+			inst-&gt;rc_mode = 0;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:</div><div class='add'>+			inst-&gt;rc_mode = 1;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_BITRATE:</div><div class='add'>+		inst-&gt;bit_rate = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_GOP_SIZE:</div><div class='add'>+		inst-&gt;enc_param.avc_idr_period = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:</div><div class='add'>+		inst-&gt;enc_param.independ_slice_mode = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.avc_slice_mode = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:</div><div class='add'>+		inst-&gt;enc_param.independ_slice_mode_arg = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.avc_slice_arg = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:</div><div class='add'>+		inst-&gt;rc_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE:</div><div class='add'>+		inst-&gt;enc_param.mb_level_rc_enable = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.cu_level_rc_enable = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.hvs_qp_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN:</div><div class='add'>+			inst-&gt;enc_param.profile = HEVC_PROFILE_MAIN;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE:</div><div class='add'>+			inst-&gt;enc_param.profile = HEVC_PROFILE_STILLPICTURE;</div><div class='add'>+			inst-&gt;enc_param.en_still_picture = 1;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10:</div><div class='add'>+			inst-&gt;enc_param.profile = HEVC_PROFILE_MAIN10;</div><div class='add'>+			inst-&gt;bit_depth = 10;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:</div><div class='add'>+			inst-&gt;enc_param.level = 10 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:</div><div class='add'>+			inst-&gt;enc_param.level = 20 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:</div><div class='add'>+			inst-&gt;enc_param.level = 21 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:</div><div class='add'>+			inst-&gt;enc_param.level = 30 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:</div><div class='add'>+			inst-&gt;enc_param.level = 31 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:</div><div class='add'>+			inst-&gt;enc_param.level = 40 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:</div><div class='add'>+			inst-&gt;enc_param.level = 41 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:</div><div class='add'>+			inst-&gt;enc_param.level = 50 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:</div><div class='add'>+			inst-&gt;enc_param.level = 51 * 3;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2:</div><div class='add'>+			inst-&gt;enc_param.level = 52 * 3;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:</div><div class='add'>+		inst-&gt;enc_param.min_qp_i = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.min_qp_p = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.min_qp_b = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:</div><div class='add'>+		inst-&gt;enc_param.max_qp_i = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.max_qp_p = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.max_qp_b = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:</div><div class='add'>+		inst-&gt;enc_param.intra_qp = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 1;</div><div class='add'>+			inst-&gt;enc_param.sao_enable = 0;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 0;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 0;</div><div class='add'>+			inst-&gt;enc_param.sao_enable = 1;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 1;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 0;</div><div class='add'>+			inst-&gt;enc_param.sao_enable = 1;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 0;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:</div><div class='add'>+		inst-&gt;enc_param.beta_offset_div2 = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:</div><div class='add'>+		inst-&gt;enc_param.tc_offset_div2 = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE:</div><div class='add'>+			inst-&gt;enc_param.decoding_refresh_type = 0;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA:</div><div class='add'>+			inst-&gt;enc_param.decoding_refresh_type = 1;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR:</div><div class='add'>+			inst-&gt;enc_param.decoding_refresh_type = 2;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:</div><div class='add'>+		inst-&gt;enc_param.intra_period = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU:</div><div class='add'>+		inst-&gt;enc_param.lossless_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED:</div><div class='add'>+		inst-&gt;enc_param.const_intra_pred_flag = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT:</div><div class='add'>+		inst-&gt;enc_param.wpp_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING:</div><div class='add'>+		inst-&gt;enc_param.strong_intra_smooth_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:</div><div class='add'>+		inst-&gt;enc_param.max_num_merge = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION:</div><div class='add'>+		inst-&gt;enc_param.tmvp_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_BP;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_MP;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_EXTENDED;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_HP;</div><div class='add'>+			inst-&gt;bit_depth = 8;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_HIGH10;</div><div class='add'>+			inst-&gt;bit_depth = 10;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_HIGH422;</div><div class='add'>+			inst-&gt;bit_depth = 10;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE:</div><div class='add'>+			inst-&gt;enc_param.profile = H264_PROFILE_HIGH444;</div><div class='add'>+			inst-&gt;bit_depth = 10;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:</div><div class='add'>+			inst-&gt;enc_param.level = 10;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_1B:</div><div class='add'>+			inst-&gt;enc_param.level = 9;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:</div><div class='add'>+			inst-&gt;enc_param.level = 11;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:</div><div class='add'>+			inst-&gt;enc_param.level = 12;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:</div><div class='add'>+			inst-&gt;enc_param.level = 13;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:</div><div class='add'>+			inst-&gt;enc_param.level = 20;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:</div><div class='add'>+			inst-&gt;enc_param.level = 21;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:</div><div class='add'>+			inst-&gt;enc_param.level = 22;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:</div><div class='add'>+			inst-&gt;enc_param.level = 30;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:</div><div class='add'>+			inst-&gt;enc_param.level = 31;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:</div><div class='add'>+			inst-&gt;enc_param.level = 32;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:</div><div class='add'>+			inst-&gt;enc_param.level = 40;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:</div><div class='add'>+			inst-&gt;enc_param.level = 41;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:</div><div class='add'>+			inst-&gt;enc_param.level = 42;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:</div><div class='add'>+			inst-&gt;enc_param.level = 50;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:</div><div class='add'>+			inst-&gt;enc_param.level = 51;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:</div><div class='add'>+		inst-&gt;enc_param.min_qp_i = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.min_qp_p = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.min_qp_b = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:</div><div class='add'>+		inst-&gt;enc_param.max_qp_i = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.max_qp_p = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.max_qp_b = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:</div><div class='add'>+		inst-&gt;enc_param.intra_qp = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:</div><div class='add'>+		switch (ctrl-&gt;val) {</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 1;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 1;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 0;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 1;</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:</div><div class='add'>+			inst-&gt;enc_param.disable_deblk = 0;</div><div class='add'>+			inst-&gt;enc_param.lf_cross_slice_boundary_enable = 0;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:</div><div class='add'>+		inst-&gt;enc_param.beta_offset_div2 = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:</div><div class='add'>+		inst-&gt;enc_param.tc_offset_div2 = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM:</div><div class='add'>+		inst-&gt;enc_param.transform8x8_enable = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION:</div><div class='add'>+		inst-&gt;enc_param.const_intra_pred_flag = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET:</div><div class='add'>+		inst-&gt;enc_param.chroma_cb_qp_offset = ctrl-&gt;val;</div><div class='add'>+		inst-&gt;enc_param.chroma_cr_qp_offset = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:</div><div class='add'>+		inst-&gt;enc_param.intra_period = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:</div><div class='add'>+		inst-&gt;enc_param.entropy_coding_mode = ctrl-&gt;val;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = {</div><div class='add'>+	.s_ctrl = wave5_vpu_enc_s_ctrl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,</div><div class='add'>+				     unsigned int *num_planes, unsigned int sizes[],</div><div class='add'>+				     struct device *alloc_devs[])</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_pix_format_mplane inst_format =</div><div class='add'>+		(q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst-&gt;src_fmt : inst-&gt;dst_fmt;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__,</div><div class='add'>+		*num_buffers, *num_planes, q-&gt;type);</div><div class='add'>+</div><div class='add'>+	if (*num_planes) {</div><div class='add'>+		if (inst_format.num_planes != *num_planes)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; *num_planes; i++) {</div><div class='add'>+			if (sizes[i] &lt; inst_format.plane_fmt[i].sizeimage)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		*num_planes = inst_format.num_planes;</div><div class='add'>+		for (i = 0; i &lt; *num_planes; i++) {</div><div class='add'>+			sizes[i] = inst_format.plane_fmt[i].sizeimage;</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: size: %u\n", __func__, sizes[0]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n",</div><div class='add'>+		__func__, vb-&gt;type, vb-&gt;index, vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 0),</div><div class='add'>+		vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 1), vb2_plane_size(&amp;vbuf-&gt;vb2_buf, 2));</div><div class='add'>+</div><div class='add'>+	if (vb-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		vbuf-&gt;sequence = inst-&gt;queued_src_buf_num++;</div><div class='add'>+	else</div><div class='add'>+		vbuf-&gt;sequence = inst-&gt;queued_dst_buf_num++;</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_buf_queue(m2m_ctx, vbuf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_set_enc_openparam(struct enc_open_param *open_param,</div><div class='add'>+				    struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct enc_wave_param input = inst-&gt;enc_param;</div><div class='add'>+	u32 num_ctu_row = ALIGN(inst-&gt;dst_fmt.height, 64) / 64;</div><div class='add'>+	u32 num_mb_row = ALIGN(inst-&gt;dst_fmt.height, 16) / 16;</div><div class='add'>+</div><div class='add'>+	open_param-&gt;wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE;</div><div class='add'>+	open_param-&gt;wave_param.hvs_qp_scale = 2;</div><div class='add'>+	open_param-&gt;wave_param.hvs_max_delta_qp = 10;</div><div class='add'>+	open_param-&gt;wave_param.skip_intra_trans = 1;</div><div class='add'>+	open_param-&gt;wave_param.intra_nx_n_enable = 1;</div><div class='add'>+	open_param-&gt;wave_param.nr_intra_weight_y = 7;</div><div class='add'>+	open_param-&gt;wave_param.nr_intra_weight_cb = 7;</div><div class='add'>+	open_param-&gt;wave_param.nr_intra_weight_cr = 7;</div><div class='add'>+	open_param-&gt;wave_param.nr_inter_weight_y = 4;</div><div class='add'>+	open_param-&gt;wave_param.nr_inter_weight_cb = 4;</div><div class='add'>+	open_param-&gt;wave_param.nr_inter_weight_cr = 4;</div><div class='add'>+	open_param-&gt;wave_param.rdo_skip = 1;</div><div class='add'>+	open_param-&gt;wave_param.lambda_scaling_enable = 1;</div><div class='add'>+</div><div class='add'>+	open_param-&gt;line_buf_int_en = true;</div><div class='add'>+	open_param-&gt;pic_width = inst-&gt;dst_fmt.width;</div><div class='add'>+	open_param-&gt;pic_height = inst-&gt;dst_fmt.height;</div><div class='add'>+	open_param-&gt;frame_rate_info = inst-&gt;frame_rate;</div><div class='add'>+	open_param-&gt;rc_enable = inst-&gt;rc_enable;</div><div class='add'>+	if (inst-&gt;rc_enable) {</div><div class='add'>+		open_param-&gt;wave_param.initial_rc_qp = -1;</div><div class='add'>+		open_param-&gt;wave_param.rc_weight_param = 16;</div><div class='add'>+		open_param-&gt;wave_param.rc_weight_buf = 128;</div><div class='add'>+	}</div><div class='add'>+	open_param-&gt;wave_param.mb_level_rc_enable = input.mb_level_rc_enable;</div><div class='add'>+	open_param-&gt;wave_param.cu_level_rc_enable = input.cu_level_rc_enable;</div><div class='add'>+	open_param-&gt;wave_param.hvs_qp_enable = input.hvs_qp_enable;</div><div class='add'>+	open_param-&gt;bit_rate = inst-&gt;bit_rate;</div><div class='add'>+	open_param-&gt;vbv_buffer_size = inst-&gt;vbv_buf_size;</div><div class='add'>+	if (inst-&gt;rc_mode == 0)</div><div class='add'>+		open_param-&gt;vbv_buffer_size = 3000;</div><div class='add'>+	open_param-&gt;wave_param.profile = input.profile;</div><div class='add'>+	open_param-&gt;wave_param.en_still_picture = input.en_still_picture;</div><div class='add'>+	open_param-&gt;wave_param.level = input.level;</div><div class='add'>+	open_param-&gt;wave_param.internal_bit_depth = inst-&gt;bit_depth;</div><div class='add'>+	open_param-&gt;wave_param.intra_qp = input.intra_qp;</div><div class='add'>+	open_param-&gt;wave_param.min_qp_i = input.min_qp_i;</div><div class='add'>+	open_param-&gt;wave_param.max_qp_i = input.max_qp_i;</div><div class='add'>+	open_param-&gt;wave_param.min_qp_p = input.min_qp_p;</div><div class='add'>+	open_param-&gt;wave_param.max_qp_p = input.max_qp_p;</div><div class='add'>+	open_param-&gt;wave_param.min_qp_b = input.min_qp_b;</div><div class='add'>+	open_param-&gt;wave_param.max_qp_b = input.max_qp_b;</div><div class='add'>+	open_param-&gt;wave_param.disable_deblk = input.disable_deblk;</div><div class='add'>+	open_param-&gt;wave_param.lf_cross_slice_boundary_enable =</div><div class='add'>+		input.lf_cross_slice_boundary_enable;</div><div class='add'>+	open_param-&gt;wave_param.tc_offset_div2 = input.tc_offset_div2;</div><div class='add'>+	open_param-&gt;wave_param.beta_offset_div2 = input.beta_offset_div2;</div><div class='add'>+	open_param-&gt;wave_param.decoding_refresh_type = input.decoding_refresh_type;</div><div class='add'>+	open_param-&gt;wave_param.intra_period = input.intra_period;</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC) {</div><div class='add'>+		if (input.intra_period == 0) {</div><div class='add'>+			open_param-&gt;wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR;</div><div class='add'>+			open_param-&gt;wave_param.intra_period = input.avc_idr_period;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		open_param-&gt;wave_param.avc_idr_period = input.avc_idr_period;</div><div class='add'>+	}</div><div class='add'>+	open_param-&gt;wave_param.entropy_coding_mode = input.entropy_coding_mode;</div><div class='add'>+	open_param-&gt;wave_param.lossless_enable = input.lossless_enable;</div><div class='add'>+	open_param-&gt;wave_param.const_intra_pred_flag = input.const_intra_pred_flag;</div><div class='add'>+	open_param-&gt;wave_param.wpp_enable = input.wpp_enable;</div><div class='add'>+	open_param-&gt;wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable;</div><div class='add'>+	open_param-&gt;wave_param.max_num_merge = input.max_num_merge;</div><div class='add'>+	open_param-&gt;wave_param.tmvp_enable = input.tmvp_enable;</div><div class='add'>+	open_param-&gt;wave_param.transform8x8_enable = input.transform8x8_enable;</div><div class='add'>+	open_param-&gt;wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset;</div><div class='add'>+	open_param-&gt;wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset;</div><div class='add'>+	open_param-&gt;wave_param.independ_slice_mode = input.independ_slice_mode;</div><div class='add'>+	open_param-&gt;wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg;</div><div class='add'>+	open_param-&gt;wave_param.avc_slice_mode = input.avc_slice_mode;</div><div class='add'>+	open_param-&gt;wave_param.avc_slice_arg = input.avc_slice_arg;</div><div class='add'>+	open_param-&gt;wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode;</div><div class='add'>+	if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) {</div><div class='add'>+		if (num_mb_row &gt;= input.intra_mb_refresh_arg)</div><div class='add'>+			open_param-&gt;wave_param.intra_mb_refresh_arg =</div><div class='add'>+				num_mb_row / input.intra_mb_refresh_arg;</div><div class='add'>+		else</div><div class='add'>+			open_param-&gt;wave_param.intra_mb_refresh_arg = num_mb_row;</div><div class='add'>+	}</div><div class='add'>+	open_param-&gt;wave_param.intra_refresh_mode = input.intra_refresh_mode;</div><div class='add'>+	if (input.intra_refresh_mode != 0) {</div><div class='add'>+		if (num_ctu_row &gt;= input.intra_refresh_arg)</div><div class='add'>+			open_param-&gt;wave_param.intra_refresh_arg =</div><div class='add'>+				num_ctu_row / input.intra_refresh_arg;</div><div class='add'>+		else</div><div class='add'>+			open_param-&gt;wave_param.intra_refresh_arg = num_ctu_row;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int initialize_sequence(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct enc_initial_info initial_info;</div><div class='add'>+	struct v4l2_ctrl *ctrl;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_issue_seq_init(inst);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) &lt; 0) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_complete_seq_init(inst, &amp;initial_info);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n",</div><div class='add'>+		__func__, initial_info.min_frame_buffer_count,</div><div class='add'>+		initial_info.min_src_frame_count);</div><div class='add'>+	inst-&gt;min_src_buf_count = initial_info.min_src_frame_count +</div><div class='add'>+				  COMMAND_QUEUE_DEPTH;</div><div class='add'>+</div><div class='add'>+	ctrl = v4l2_ctrl_find(&amp;inst-&gt;v4l2_ctrl_hdl,</div><div class='add'>+			      V4L2_CID_MIN_BUFFERS_FOR_OUTPUT);</div><div class='add'>+	if (ctrl)</div><div class='add'>+		v4l2_ctrl_s_ctrl(ctrl, inst-&gt;min_src_buf_count);</div><div class='add'>+</div><div class='add'>+	inst-&gt;fbc_buf_count = initial_info.min_frame_buffer_count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int prepare_fb(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	u32 fb_stride = ALIGN(inst-&gt;dst_fmt.width, 32);</div><div class='add'>+	u32 fb_height = ALIGN(inst-&gt;dst_fmt.height, 32);</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;fbc_buf_count; i++) {</div><div class='add'>+		u32 luma_size = fb_stride * fb_height;</div><div class='add'>+		u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height;</div><div class='add'>+</div><div class='add'>+		inst-&gt;frame_vbuf[i].size = luma_size + chroma_size;</div><div class='add'>+		ret = wave5_vdi_allocate_dma_memory(inst-&gt;dev, &amp;inst-&gt;frame_vbuf[i]);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(inst-&gt;dev-&gt;dev, "%s: failed to allocate FBC buffer %zu\n",</div><div class='add'>+				__func__, inst-&gt;frame_vbuf[i].size);</div><div class='add'>+			goto free_buffers;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		inst-&gt;frame_buf[i].buf_y = inst-&gt;frame_vbuf[i].daddr;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_cb = (dma_addr_t)-1;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_cr = (dma_addr_t)-1;</div><div class='add'>+		inst-&gt;frame_buf[i].update_fb_info = true;</div><div class='add'>+		inst-&gt;frame_buf[i].size = inst-&gt;frame_vbuf[i].size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_register_frame_buffer(inst, inst-&gt;fbc_buf_count, fb_stride,</div><div class='add'>+						  fb_height, COMPRESSED_FRAME_MAP);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		goto free_buffers;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+free_buffers:</div><div class='add'>+	for (i = 0; i &lt; inst-&gt;fbc_buf_count; i++)</div><div class='add'>+		wave5_vpu_dec_reset_framebuffer(inst, i);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_update_start_streaming_state(m2m_ctx, q);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;state == VPU_INST_STATE_NONE &amp;&amp; q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {</div><div class='add'>+		struct enc_open_param open_param;</div><div class='add'>+</div><div class='add'>+		memset(&amp;open_param, 0, sizeof(struct enc_open_param));</div><div class='add'>+</div><div class='add'>+		wave5_set_enc_openparam(&amp;open_param, inst);</div><div class='add'>+</div><div class='add'>+		ret = wave5_vpu_enc_open(inst, &amp;open_param);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "%s: wave5_vpu_enc_open, fail: %d\n",</div><div class='add'>+				__func__, ret);</div><div class='add'>+			goto return_buffers;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;mirror_direction) {</div><div class='add'>+			wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL);</div><div class='add'>+			wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION,</div><div class='add'>+						   &amp;inst-&gt;mirror_direction);</div><div class='add'>+		}</div><div class='add'>+		if (inst-&gt;rot_angle) {</div><div class='add'>+			wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL);</div><div class='add'>+			wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &amp;inst-&gt;rot_angle);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = switch_state(inst, VPU_INST_STATE_OPEN);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto return_buffers;</div><div class='add'>+	}</div><div class='add'>+	if (inst-&gt;state == VPU_INST_STATE_OPEN &amp;&amp; m2m_ctx-&gt;cap_q_ctx.q.streaming) {</div><div class='add'>+		ret = initialize_sequence(inst);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "Sequence not found: %d\n", ret);</div><div class='add'>+			goto return_buffers;</div><div class='add'>+		}</div><div class='add'>+		ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto return_buffers;</div><div class='add'>+		/*</div><div class='add'>+		 * The sequence must be analyzed first to calculate the proper</div><div class='add'>+		 * size of the auxiliary buffers.</div><div class='add'>+		 */</div><div class='add'>+		ret = prepare_fb(inst);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "Framebuffer preparation, fail: %d\n", ret);</div><div class='add'>+			goto return_buffers;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = switch_state(inst, VPU_INST_STATE_PIC_RUN);</div><div class='add'>+	}</div><div class='add'>+	if (ret)</div><div class='add'>+		goto return_buffers;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+return_buffers:</div><div class='add'>+	wave5_return_bufs(q, VB2_BUF_STATE_QUEUED);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void streamoff_output(struct vpu_instance *inst, struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *buf;</div><div class='add'>+</div><div class='add'>+	while ((buf = v4l2_m2m_src_buf_remove(m2m_ctx))) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: buf type %4u | index %4u\n",</div><div class='add'>+			__func__, buf-&gt;vb2_buf.type, buf-&gt;vb2_buf.index);</div><div class='add'>+		v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void streamoff_capture(struct vpu_instance *inst, struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	struct vb2_v4l2_buffer *buf;</div><div class='add'>+</div><div class='add'>+	while ((buf = v4l2_m2m_dst_buf_remove(m2m_ctx))) {</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: buf type %4u | index %4u\n",</div><div class='add'>+			__func__, buf-&gt;vb2_buf.type, buf-&gt;vb2_buf.index);</div><div class='add'>+		vb2_set_plane_payload(&amp;buf-&gt;vb2_buf, 0, 0);</div><div class='add'>+		v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_m2m_clear_state(m2m_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = vb2_get_drv_priv(q);</div><div class='add'>+	bool check_cmd = true;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Note that we don't need m2m_ctx-&gt;next_buf_last for this driver, so we</div><div class='add'>+	 * don't call v4l2_m2m_update_stop_streaming_state().</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: type: %u\n", __func__, q-&gt;type);</div><div class='add'>+</div><div class='add'>+	if (wave5_vpu_both_queues_are_streaming(inst))</div><div class='add'>+		switch_state(inst, VPU_INST_STATE_STOP);</div><div class='add'>+</div><div class='add'>+	while (check_cmd) {</div><div class='add'>+		struct queue_status_info q_status;</div><div class='add'>+		struct enc_output_info enc_output_info;</div><div class='add'>+</div><div class='add'>+		wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &amp;q_status);</div><div class='add'>+</div><div class='add'>+		if (q_status.report_queue_count == 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) &lt; 0)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (wave5_vpu_enc_get_output_info(inst, &amp;enc_output_info))</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "Getting encoding results from fw, fail\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (q-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)</div><div class='add'>+		streamoff_output(inst, q);</div><div class='add'>+	else</div><div class='add'>+		streamoff_capture(inst, q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vb2_ops wave5_vpu_enc_vb2_ops = {</div><div class='add'>+	.queue_setup = wave5_vpu_enc_queue_setup,</div><div class='add'>+	.wait_prepare = vb2_ops_wait_prepare,</div><div class='add'>+	.wait_finish = vb2_ops_wait_finish,</div><div class='add'>+	.buf_queue = wave5_vpu_enc_buf_queue,</div><div class='add'>+	.start_streaming = wave5_vpu_enc_start_streaming,</div><div class='add'>+	.stop_streaming = wave5_vpu_enc_stop_streaming,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt,</div><div class='add'>+				     struct v4l2_pix_format_mplane *dst_fmt)</div><div class='add'>+{</div><div class='add'>+	unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt;</div><div class='add'>+	const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt);</div><div class='add'>+</div><div class='add'>+	src_fmt-&gt;pixelformat = src_pix_fmt;</div><div class='add'>+	src_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	src_fmt-&gt;flags = 0;</div><div class='add'>+	src_fmt-&gt;num_planes = src_fmt_info-&gt;mem_planes;</div><div class='add'>+	wave5_update_pix_fmt(src_fmt, 416, 240);</div><div class='add'>+</div><div class='add'>+	dst_fmt-&gt;pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt;</div><div class='add'>+	dst_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	dst_fmt-&gt;flags = 0;</div><div class='add'>+	dst_fmt-&gt;num_planes = 1;</div><div class='add'>+	wave5_update_pix_fmt(dst_fmt, 416, 240);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)</div><div class='add'>+{</div><div class='add'>+	return wave5_vpu_queue_init(priv, src_vq, dst_vq, &amp;wave5_vpu_enc_vb2_ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = {</div><div class='add'>+	.finish_process = wave5_vpu_enc_finish_encode,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void wave5_vpu_enc_device_run(void *priv)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+	u32 fail_res = 0;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	switch (inst-&gt;state) {</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		ret = start_encode(inst, &amp;fail_res);</div><div class='add'>+		if (ret) {</div><div class='add'>+			if (ret == -EINVAL)</div><div class='add'>+				dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+					"Frame encoding on m2m context (%p), fail: %d (res: %d)\n",</div><div class='add'>+					m2m_ctx, ret, fail_res);</div><div class='add'>+			else if (ret == -EAGAIN)</div><div class='add'>+				dev_dbg(inst-&gt;dev-&gt;dev, "Missing buffers for encode, try again\n");</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "%s: leave with active job", __func__);</div><div class='add'>+		return;</div><div class='add'>+	default:</div><div class='add'>+		WARN(1, "Execution of a job in state %s is invalid.\n",</div><div class='add'>+		     state_to_str(inst-&gt;state));</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: leave and finish job", __func__);</div><div class='add'>+	v4l2_m2m_job_finish(inst-&gt;v4l2_m2m_dev, m2m_ctx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_job_ready(void *priv)</div><div class='add'>+{</div><div class='add'>+	struct vpu_instance *inst = priv;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = inst-&gt;v4l2_fh.m2m_ctx;</div><div class='add'>+</div><div class='add'>+	switch (inst-&gt;state) {</div><div class='add'>+	case VPU_INST_STATE_NONE:</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev, "Encoder must be open to start queueing M2M jobs!\n");</div><div class='add'>+		return false;</div><div class='add'>+	case VPU_INST_STATE_PIC_RUN:</div><div class='add'>+		if (m2m_ctx-&gt;is_draining || v4l2_m2m_num_src_bufs_ready(m2m_ctx)) {</div><div class='add'>+			dev_dbg(inst-&gt;dev-&gt;dev, "Encoder ready for a job, state: %s\n",</div><div class='add'>+				state_to_str(inst-&gt;state));</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		fallthrough;</div><div class='add'>+	default:</div><div class='add'>+		dev_dbg(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Encoder not ready for a job, state: %s, %s draining, %d src bufs ready\n",</div><div class='add'>+			state_to_str(inst-&gt;state), m2m_ctx-&gt;is_draining ? "is" : "is not",</div><div class='add'>+			v4l2_m2m_num_src_bufs_ready(m2m_ctx));</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = {</div><div class='add'>+	.device_run = wave5_vpu_enc_device_run,</div><div class='add'>+	.job_ready = wave5_vpu_enc_job_ready,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_open_enc(struct file *filp)</div><div class='add'>+{</div><div class='add'>+	struct video_device *vdev = video_devdata(filp);</div><div class='add'>+	struct vpu_device *dev = video_drvdata(filp);</div><div class='add'>+	struct vpu_instance *inst = NULL;</div><div class='add'>+	struct v4l2_ctrl_handler *v4l2_ctrl_hdl;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	inst = kzalloc(sizeof(*inst), GFP_KERNEL);</div><div class='add'>+	if (!inst)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	v4l2_ctrl_hdl = &amp;inst-&gt;v4l2_ctrl_hdl;</div><div class='add'>+</div><div class='add'>+	inst-&gt;dev = dev;</div><div class='add'>+	inst-&gt;type = VPU_INST_TYPE_ENC;</div><div class='add'>+	inst-&gt;ops = &amp;wave5_vpu_enc_inst_ops;</div><div class='add'>+</div><div class='add'>+	inst-&gt;codec_info = kzalloc(sizeof(*inst-&gt;codec_info), GFP_KERNEL);</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	v4l2_fh_init(&amp;inst-&gt;v4l2_fh, vdev);</div><div class='add'>+	filp-&gt;private_data = &amp;inst-&gt;v4l2_fh;</div><div class='add'>+	v4l2_fh_add(&amp;inst-&gt;v4l2_fh);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;inst-&gt;list);</div><div class='add'>+	list_add_tail(&amp;inst-&gt;list, &amp;dev-&gt;instances);</div><div class='add'>+</div><div class='add'>+	inst-&gt;v4l2_m2m_dev = inst-&gt;dev-&gt;v4l2_m2m_enc_dev;</div><div class='add'>+	inst-&gt;v4l2_fh.m2m_ctx =</div><div class='add'>+		v4l2_m2m_ctx_init(inst-&gt;v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init);</div><div class='add'>+	if (IS_ERR(inst-&gt;v4l2_fh.m2m_ctx)) {</div><div class='add'>+		ret = PTR_ERR(inst-&gt;v4l2_fh.m2m_ctx);</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+	v4l2_m2m_set_src_buffered(inst-&gt;v4l2_fh.m2m_ctx, true);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_LEVEL_1);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,</div><div class='add'>+			  0, 63, 1, 8);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,</div><div class='add'>+			  0, 63, 1, 51);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,</div><div class='add'>+			  0, 63, 1, 30);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,</div><div class='add'>+			  -6, 6, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,</div><div class='add'>+			  -6, 6, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,</div><div class='add'>+			  0, 2047, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING,</div><div class='add'>+			  0, 1, 1, 1);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,</div><div class='add'>+			  1, 2, 1, 2);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION,</div><div class='add'>+			  0, 1, 1, 1);</div><div class='add'>+</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_H264_PROFILE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_H264_LEVEL,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_LEVEL_1_0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_MIN_QP,</div><div class='add'>+			  0, 63, 1, 8);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_MAX_QP,</div><div class='add'>+			  0, 63, 1, 51);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,</div><div class='add'>+			  0, 63, 1, 30);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA,</div><div class='add'>+			  -6, 6, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA,</div><div class='add'>+			  -6, 6, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM,</div><div class='add'>+			  0, 1, 1, 1);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET,</div><div class='add'>+			  -12, 12, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,</div><div class='add'>+			  0, 2047, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_AU_DELIMITER,</div><div class='add'>+			  0, 1, 1, 1);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_HFLIP,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_VFLIP,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_ROTATE,</div><div class='add'>+			  0, 270, 90, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_VBV_SIZE,</div><div class='add'>+			  10, 3000, 1, 1000);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_BITRATE_MODE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_BITRATE,</div><div class='add'>+			  0, 700000000, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_GOP_SIZE,</div><div class='add'>+			  0, 2047, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			       V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,</div><div class='add'>+			       V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0,</div><div class='add'>+			       V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB,</div><div class='add'>+			  0, 0xFFFF, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE,</div><div class='add'>+			  0, 1, 1, 0);</div><div class='add'>+	v4l2_ctrl_new_std(v4l2_ctrl_hdl, &amp;wave5_vpu_enc_ctrl_ops,</div><div class='add'>+			  V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1);</div><div class='add'>+</div><div class='add'>+	if (v4l2_ctrl_hdl-&gt;error) {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	inst-&gt;v4l2_fh.ctrl_handler = v4l2_ctrl_hdl;</div><div class='add'>+	v4l2_ctrl_handler_setup(v4l2_ctrl_hdl);</div><div class='add'>+</div><div class='add'>+	wave5_set_default_format(&amp;inst-&gt;src_fmt, &amp;inst-&gt;dst_fmt);</div><div class='add'>+	inst-&gt;colorspace = V4L2_COLORSPACE_REC709;</div><div class='add'>+	inst-&gt;ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;</div><div class='add'>+	inst-&gt;quantization = V4L2_QUANTIZATION_DEFAULT;</div><div class='add'>+	inst-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='add'>+	inst-&gt;frame_rate = 30;</div><div class='add'>+</div><div class='add'>+	init_completion(&amp;inst-&gt;irq_done);</div><div class='add'>+</div><div class='add'>+	inst-&gt;id = ida_alloc(&amp;inst-&gt;dev-&gt;inst_ida, GFP_KERNEL);</div><div class='add'>+	if (inst-&gt;id &lt; 0) {</div><div class='add'>+		dev_warn(inst-&gt;dev-&gt;dev, "Allocating instance ID, fail: %d\n", inst-&gt;id);</div><div class='add'>+		ret = inst-&gt;id;</div><div class='add'>+		goto cleanup_inst;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_vdi_allocate_sram(inst-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+cleanup_inst:</div><div class='add'>+	wave5_cleanup_instance(inst);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_enc_release(struct file *filp)</div><div class='add'>+{</div><div class='add'>+	return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_file_operations wave5_vpu_enc_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open = wave5_vpu_open_enc,</div><div class='add'>+	.release = wave5_vpu_enc_release,</div><div class='add'>+	.unlocked_ioctl = video_ioctl2,</div><div class='add'>+	.poll = v4l2_m2m_fop_poll,</div><div class='add'>+	.mmap = v4l2_m2m_fop_mmap,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_register_device(struct vpu_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct video_device *vdev_enc;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vdev_enc = devm_kzalloc(dev-&gt;v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL);</div><div class='add'>+	if (!vdev_enc)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	dev-&gt;v4l2_m2m_enc_dev = v4l2_m2m_init(&amp;wave5_vpu_enc_m2m_ops);</div><div class='add'>+	if (IS_ERR(dev-&gt;v4l2_m2m_enc_dev)) {</div><div class='add'>+		ret = PTR_ERR(dev-&gt;v4l2_m2m_enc_dev);</div><div class='add'>+		dev_err(dev-&gt;dev, "v4l2_m2m_init, fail: %d\n", ret);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev-&gt;video_dev_enc = vdev_enc;</div><div class='add'>+</div><div class='add'>+	strscpy(vdev_enc-&gt;name, VPU_ENC_DEV_NAME, sizeof(vdev_enc-&gt;name));</div><div class='add'>+	vdev_enc-&gt;fops = &amp;wave5_vpu_enc_fops;</div><div class='add'>+	vdev_enc-&gt;ioctl_ops = &amp;wave5_vpu_enc_ioctl_ops;</div><div class='add'>+	vdev_enc-&gt;release = video_device_release_empty;</div><div class='add'>+	vdev_enc-&gt;v4l2_dev = &amp;dev-&gt;v4l2_dev;</div><div class='add'>+	vdev_enc-&gt;vfl_dir = VFL_DIR_M2M;</div><div class='add'>+	vdev_enc-&gt;device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;</div><div class='add'>+	vdev_enc-&gt;lock = &amp;dev-&gt;dev_lock;</div><div class='add'>+</div><div class='add'>+	ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	video_set_drvdata(vdev_enc, dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wave5_vpu_enc_unregister_device(struct vpu_device *dev)</div><div class='add'>+{</div><div class='add'>+	video_unregister_device(dev-&gt;video_dev_enc);</div><div class='add'>+	if (dev-&gt;v4l2_m2m_enc_dev)</div><div class='add'>+		v4l2_m2m_release(dev-&gt;v4l2_m2m_enc_dev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c<br/>new file mode 100644<br/>index 000000000000..bfe4caa79cc9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu.c</a></div><div class='hunk'>@@ -0,0 +1,291 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - platform driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include "wave5-vpu.h"</div><div class='add'>+#include "wave5-regdefine.h"</div><div class='add'>+#include "wave5-vpuconfig.h"</div><div class='add'>+#include "wave5.h"</div><div class='add'>+</div><div class='add'>+#define VPU_PLATFORM_DEVICE_NAME "vdec"</div><div class='add'>+#define VPU_CLK_NAME "vcodec"</div><div class='add'>+</div><div class='add'>+#define WAVE5_IS_ENC BIT(0)</div><div class='add'>+#define WAVE5_IS_DEC BIT(1)</div><div class='add'>+</div><div class='add'>+struct wave5_match_data {</div><div class='add'>+	int flags;</div><div class='add'>+	const char *fw_name;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = wait_for_completion_timeout(&amp;inst-&gt;irq_done,</div><div class='add'>+					  msecs_to_jiffies(timeout));</div><div class='add'>+	if (!ret)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	reinit_completion(&amp;inst-&gt;irq_done);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)</div><div class='add'>+{</div><div class='add'>+	u32 seq_done;</div><div class='add'>+	u32 cmd_done;</div><div class='add'>+	u32 irq_reason;</div><div class='add'>+	struct vpu_instance *inst;</div><div class='add'>+	struct vpu_device *dev = dev_id;</div><div class='add'>+</div><div class='add'>+	if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) {</div><div class='add'>+		irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);</div><div class='add'>+		wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason);</div><div class='add'>+		wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);</div><div class='add'>+</div><div class='add'>+		list_for_each_entry(inst, &amp;dev-&gt;instances, list) {</div><div class='add'>+			seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);</div><div class='add'>+			cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);</div><div class='add'>+</div><div class='add'>+			if (irq_reason &amp; BIT(INT_WAVE5_INIT_SEQ) ||</div><div class='add'>+			    irq_reason &amp; BIT(INT_WAVE5_ENC_SET_PARAM)) {</div><div class='add'>+				if (seq_done &amp; BIT(inst-&gt;id)) {</div><div class='add'>+					seq_done &amp;= ~BIT(inst-&gt;id);</div><div class='add'>+					wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO,</div><div class='add'>+								 seq_done);</div><div class='add'>+					complete(&amp;inst-&gt;irq_done);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (irq_reason &amp; BIT(INT_WAVE5_DEC_PIC) ||</div><div class='add'>+			    irq_reason &amp; BIT(INT_WAVE5_ENC_PIC)) {</div><div class='add'>+				if (cmd_done &amp; BIT(inst-&gt;id)) {</div><div class='add'>+					cmd_done &amp;= ~BIT(inst-&gt;id);</div><div class='add'>+					wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,</div><div class='add'>+								 cmd_done);</div><div class='add'>+					inst-&gt;ops-&gt;finish_process(inst);</div><div class='add'>+				}</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			wave5_vpu_clear_interrupt(inst, irq_reason);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name,</div><div class='add'>+				   u32 *revision)</div><div class='add'>+{</div><div class='add'>+	const struct firmware *fw;</div><div class='add'>+	int ret;</div><div class='add'>+	unsigned int product_id;</div><div class='add'>+</div><div class='add'>+	ret = request_firmware(&amp;fw, fw_name, dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "request_firmware, fail: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw-&gt;data, fw-&gt;size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);</div><div class='add'>+		release_firmware(fw);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	release_firmware(fw);</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_get_version_info(dev, revision, &amp;product_id);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "vpu_get_version_info fail: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",</div><div class='add'>+		__func__, product_id, *revision);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *dev;</div><div class='add'>+	const struct wave5_match_data *match_data;</div><div class='add'>+	u32 fw_revision;</div><div class='add'>+</div><div class='add'>+	match_data = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (!match_data) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "missing device match data\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* physical addresses limited to 32 bits */</div><div class='add'>+	ret = dma_set_mask_and_coherent(&amp;pdev-&gt;dev, DMA_BIT_MASK(32));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to set DMA mask: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*dev), GFP_KERNEL);</div><div class='add'>+	if (!dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	dev-&gt;vdb_register = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(dev-&gt;vdb_register))</div><div class='add'>+		return PTR_ERR(dev-&gt;vdb_register);</div><div class='add'>+	ida_init(&amp;dev-&gt;inst_ida);</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;dev-&gt;dev_lock);</div><div class='add'>+	mutex_init(&amp;dev-&gt;hw_lock);</div><div class='add'>+	dev_set_drvdata(&amp;pdev-&gt;dev, dev);</div><div class='add'>+	dev-&gt;dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = devm_clk_bulk_get_all(&amp;pdev-&gt;dev, &amp;dev-&gt;clks);</div><div class='add'>+</div><div class='add'>+	/* continue without clock, assume externally managed */</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "Getting clocks, fail: %d\n", ret);</div><div class='add'>+		ret = 0;</div><div class='add'>+	}</div><div class='add'>+	dev-&gt;num_clks = ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_bulk_prepare_enable(dev-&gt;num_clks, dev-&gt;clks);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Enabling clocks, fail: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = of_property_read_u32(pdev-&gt;dev.of_node, "sram-size",</div><div class='add'>+				   &amp;dev-&gt;sram_size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "sram-size not found\n");</div><div class='add'>+		dev-&gt;sram_size = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev-&gt;sram_pool = of_gen_pool_get(pdev-&gt;dev.of_node, "sram", 0);</div><div class='add'>+	if (!dev-&gt;sram_pool)</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "sram node not found\n");</div><div class='add'>+</div><div class='add'>+	dev-&gt;product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);</div><div class='add'>+	ret = wave5_vdi_init(&amp;pdev-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "wave5_vdi_init, fail: %d\n", ret);</div><div class='add'>+		goto err_clk_dis;</div><div class='add'>+	}</div><div class='add'>+	dev-&gt;product = wave5_vpu_get_product_id(dev);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;dev-&gt;instances);</div><div class='add'>+	ret = v4l2_device_register(&amp;pdev-&gt;dev, &amp;dev-&gt;v4l2_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "v4l2_device_register, fail: %d\n", ret);</div><div class='add'>+		goto err_vdi_release;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (match_data-&gt;flags &amp; WAVE5_IS_DEC) {</div><div class='add'>+		ret = wave5_vpu_dec_register_device(dev);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "wave5_vpu_dec_register_device, fail: %d\n", ret);</div><div class='add'>+			goto err_v4l2_unregister;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	if (match_data-&gt;flags &amp; WAVE5_IS_ENC) {</div><div class='add'>+		ret = wave5_vpu_enc_register_device(dev);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "wave5_vpu_enc_register_device, fail: %d\n", ret);</div><div class='add'>+			goto err_dec_unreg;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev-&gt;irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (dev-&gt;irq &lt; 0) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "failed to get irq resource\n");</div><div class='add'>+		ret = -ENXIO;</div><div class='add'>+		goto err_enc_unreg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = devm_request_threaded_irq(&amp;pdev-&gt;dev, dev-&gt;irq, NULL,</div><div class='add'>+					wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Register interrupt handler, fail: %d\n", ret);</div><div class='add'>+		goto err_enc_unreg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_load_firmware(&amp;pdev-&gt;dev, match_data-&gt;fw_name, &amp;fw_revision);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "wave5_vpu_load_firmware, fail: %d\n", ret);</div><div class='add'>+		goto err_enc_unreg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "Added wave5 driver with caps: %s %s\n",</div><div class='add'>+		 (match_data-&gt;flags &amp; WAVE5_IS_ENC) ? "'ENCODE'" : "",</div><div class='add'>+		 (match_data-&gt;flags &amp; WAVE5_IS_DEC) ? "'DECODE'" : "");</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "Product Code:      0x%x\n", dev-&gt;product_code);</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "Firmware Revision: %u\n", fw_revision);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_enc_unreg:</div><div class='add'>+	if (match_data-&gt;flags &amp; WAVE5_IS_ENC)</div><div class='add'>+		wave5_vpu_enc_unregister_device(dev);</div><div class='add'>+err_dec_unreg:</div><div class='add'>+	if (match_data-&gt;flags &amp; WAVE5_IS_DEC)</div><div class='add'>+		wave5_vpu_dec_unregister_device(dev);</div><div class='add'>+err_v4l2_unregister:</div><div class='add'>+	v4l2_device_unregister(&amp;dev-&gt;v4l2_dev);</div><div class='add'>+err_vdi_release:</div><div class='add'>+	wave5_vdi_release(&amp;pdev-&gt;dev);</div><div class='add'>+err_clk_dis:</div><div class='add'>+	clk_bulk_disable_unprepare(dev-&gt;num_clks, dev-&gt;clks);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_vpu_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct vpu_device *dev = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;dev-&gt;dev_lock);</div><div class='add'>+	mutex_destroy(&amp;dev-&gt;hw_lock);</div><div class='add'>+	clk_bulk_disable_unprepare(dev-&gt;num_clks, dev-&gt;clks);</div><div class='add'>+	wave5_vpu_enc_unregister_device(dev);</div><div class='add'>+	wave5_vpu_dec_unregister_device(dev);</div><div class='add'>+	v4l2_device_unregister(&amp;dev-&gt;v4l2_dev);</div><div class='add'>+	wave5_vdi_release(&amp;pdev-&gt;dev);</div><div class='add'>+	ida_destroy(&amp;dev-&gt;inst_ida);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct wave5_match_data ti_wave521c_data = {</div><div class='add'>+	.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,</div><div class='add'>+	.fw_name = "cnm/wave521c_k3_codec_fw.bin",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct of_device_id wave5_dt_ids[] = {</div><div class='add'>+	{ .compatible = "ti,k3-j721s2-wave521c", .data = &amp;ti_wave521c_data },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, wave5_dt_ids);</div><div class='add'>+</div><div class='add'>+static struct platform_driver wave5_vpu_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = VPU_PLATFORM_DEVICE_NAME,</div><div class='add'>+		.of_match_table = of_match_ptr(wave5_dt_ids),</div><div class='add'>+		},</div><div class='add'>+	.probe = wave5_vpu_probe,</div><div class='add'>+	.remove = wave5_vpu_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_platform_driver(wave5_vpu_driver);</div><div class='add'>+MODULE_DESCRIPTION("chips&amp;media VPU V4L2 driver");</div><div class='add'>+MODULE_LICENSE("Dual BSD/GPL");</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h<br/>new file mode 100644<br/>index 000000000000..32b7fd3730b5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpu.h</a></div><div class='hunk'>@@ -0,0 +1,83 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - basic types</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+#ifndef __VPU_DRV_H__</div><div class='add'>+#define __VPU_DRV_H__</div><div class='add'>+</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ioctl.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fh.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-v4l2.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-dma-contig.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-vmalloc.h&gt;</div><div class='add'>+#include "wave5-vpuconfig.h"</div><div class='add'>+#include "wave5-vpuapi.h"</div><div class='add'>+</div><div class='add'>+#define VPU_BUF_SYNC_TO_DEVICE 0</div><div class='add'>+#define VPU_BUF_SYNC_FROM_DEVICE 1</div><div class='add'>+</div><div class='add'>+struct vpu_src_buffer {</div><div class='add'>+	struct v4l2_m2m_buffer	v4l2_m2m_buf;</div><div class='add'>+	struct list_head	list;</div><div class='add'>+	bool			consumed;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_dst_buffer {</div><div class='add'>+	struct v4l2_m2m_buffer v4l2_m2m_buf;</div><div class='add'>+	bool                   display;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum vpu_fmt_type {</div><div class='add'>+	VPU_FMT_TYPE_CODEC = 0,</div><div class='add'>+	VPU_FMT_TYPE_RAW   = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_format {</div><div class='add'>+	unsigned int v4l2_pix_fmt;</div><div class='add'>+	unsigned int max_width;</div><div class='add'>+	unsigned int min_width;</div><div class='add'>+	unsigned int max_height;</div><div class='add'>+	unsigned int min_height;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh)</div><div class='add'>+{</div><div class='add'>+	return container_of(vfh, struct vpu_instance, v4l2_fh);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl)</div><div class='add'>+{</div><div class='add'>+	return container_of(vctrl-&gt;handler, struct vpu_instance, v4l2_ctrl_hdl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct vpu_src_buffer *wave5_to_vpu_src_buf(struct vb2_v4l2_buffer *vbuf)</div><div class='add'>+{</div><div class='add'>+	return container_of(vbuf, struct vpu_src_buffer, v4l2_m2m_buf.vb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline struct vpu_dst_buffer *wave5_to_vpu_dst_buf(struct vb2_v4l2_buffer *vbuf)</div><div class='add'>+{</div><div class='add'>+	return container_of(vbuf, struct vpu_dst_buffer, v4l2_m2m_buf.vb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout);</div><div class='add'>+</div><div class='add'>+int  wave5_vpu_dec_register_device(struct vpu_device *dev);</div><div class='add'>+void wave5_vpu_dec_unregister_device(struct vpu_device *dev);</div><div class='add'>+int  wave5_vpu_enc_register_device(struct vpu_device *dev);</div><div class='add'>+void wave5_vpu_enc_unregister_device(struct vpu_device *dev);</div><div class='add'>+static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	struct vb2_queue *vq_cap =</div><div class='add'>+		v4l2_m2m_get_vq(inst-&gt;v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);</div><div class='add'>+	struct vb2_queue *vq_out =</div><div class='add'>+		v4l2_m2m_get_vq(inst-&gt;v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);</div><div class='add'>+</div><div class='add'>+	return vb2_is_streaming(vq_cap) &amp;&amp; vb2_is_streaming(vq_out);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c<br/>new file mode 100644<br/>index 000000000000..1a3efb638dde<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuapi.c</a></div><div class='hunk'>@@ -0,0 +1,960 @@</div><div class='add'>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - helper functions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bug.h&gt;</div><div class='add'>+#include "wave5-vpuapi.h"</div><div class='add'>+#include "wave5-regdefine.h"</div><div class='add'>+#include "wave5.h"</div><div class='add'>+</div><div class='add'>+#define DECODE_ALL_TEMPORAL_LAYERS 0</div><div class='add'>+#define DECODE_ALL_SPATIAL_LAYERS 0</div><div class='add'>+</div><div class='add'>+static int wave5_initialize_vpu(struct device *dev, u8 *code, size_t size)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (wave5_vpu_is_init(vpu_dev)) {</div><div class='add'>+		wave5_vpu_re_init(dev, (void *)code, size);</div><div class='add'>+		ret = -EBUSY;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_init(dev, (void *)code, size);</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size)</div><div class='add'>+{</div><div class='add'>+	if (!bitcode || size == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return wave5_initialize_vpu(dev, bitcode, size);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_flush_instance(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret = 0;</div><div class='add'>+	int retry = 0;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	do {</div><div class='add'>+		/*</div><div class='add'>+		 * Repeat the FLUSH command until the firmware reports that the</div><div class='add'>+		 * VPU isn't running anymore</div><div class='add'>+		 */</div><div class='add'>+		ret = wave5_vpu_hw_flush_instance(inst);</div><div class='add'>+		if (ret &lt; 0 &amp;&amp; ret != -EBUSY) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "Flush of %s instance with id: %d fail: %d\n",</div><div class='add'>+				 inst-&gt;type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst-&gt;id,</div><div class='add'>+				 ret);</div><div class='add'>+			mutex_unlock(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+		if (ret == -EBUSY &amp;&amp; retry++ &gt;= MAX_FIRMWARE_CALL_RETRY) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "Flush of %s instance with id: %d timed out!\n",</div><div class='add'>+				 inst-&gt;type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst-&gt;id);</div><div class='add'>+			mutex_unlock(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+			return -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+	} while (ret != 0);</div><div class='add'>+	mutex_unlock(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_is_init(vpu_dev)) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (product_id)</div><div class='add'>+		*product_id = vpu_dev-&gt;product;</div><div class='add'>+	ret = wave5_vpu_get_version(vpu_dev, revision);</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open_param *param)</div><div class='add'>+{</div><div class='add'>+	if (inst-&gt;id &gt;= MAX_NUM_INSTANCE) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev, "Too many simultaneous instances: %d (max: %u)\n",</div><div class='add'>+			inst-&gt;id, MAX_NUM_INSTANCE);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;bitstream_buffer % 8) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Bitstream buffer must be aligned to a multiple of 8\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (param-&gt;bitstream_buffer_size % 1024 ||</div><div class='add'>+	    param-&gt;bitstream_buffer_size &lt; MIN_BITSTREAM_BUFFER_SIZE) {</div><div class='add'>+		dev_err(inst-&gt;dev-&gt;dev,</div><div class='add'>+			"Bitstream buffer size must be aligned to a multiple of 1024 and have a minimum size of %d\n",</div><div class='add'>+			MIN_BITSTREAM_BUFFER_SIZE);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	dma_addr_t buffer_addr;</div><div class='add'>+	size_t buffer_size;</div><div class='add'>+</div><div class='add'>+	ret = wave5_check_dec_open_param(inst, open_param);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_is_init(vpu_dev)) {</div><div class='add'>+		mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	memcpy(&amp;p_dec_info-&gt;open_param, open_param, sizeof(struct dec_open_param));</div><div class='add'>+</div><div class='add'>+	buffer_addr = open_param-&gt;bitstream_buffer;</div><div class='add'>+	buffer_size = open_param-&gt;bitstream_buffer_size;</div><div class='add'>+	p_dec_info-&gt;stream_wr_ptr = buffer_addr;</div><div class='add'>+	p_dec_info-&gt;stream_rd_ptr = buffer_addr;</div><div class='add'>+	p_dec_info-&gt;stream_buf_start_addr = buffer_addr;</div><div class='add'>+	p_dec_info-&gt;stream_buf_size = buffer_size;</div><div class='add'>+	p_dec_info-&gt;stream_buf_end_addr = buffer_addr + buffer_size;</div><div class='add'>+	p_dec_info-&gt;reorder_enable = TRUE;</div><div class='add'>+	p_dec_info-&gt;temp_id_select_mode = TEMPORAL_ID_MODE_ABSOLUTE;</div><div class='add'>+	p_dec_info-&gt;target_temp_id = DECODE_ALL_TEMPORAL_LAYERS;</div><div class='add'>+	p_dec_info-&gt;target_spatial_id = DECODE_ALL_SPATIAL_LAYERS;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_build_up_dec_param(inst, open_param);</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int reset_auxiliary_buffers(struct vpu_instance *inst, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	if (index &gt;= MAX_REG_FRAME)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	if (p_dec_info-&gt;vb_mv[index].size == 0 &amp;&amp; p_dec_info-&gt;vb_fbc_y_tbl[index].size == 0 &amp;&amp;</div><div class='add'>+	    p_dec_info-&gt;vb_fbc_c_tbl[index].size == 0)</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_mv[index]);</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_fbc_y_tbl[index]);</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_fbc_c_tbl[index]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	int retry = 0;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	*fail_res = 0;</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = wave5_vpu_dec_finish_seq(inst, fail_res);</div><div class='add'>+		if (ret &lt; 0 &amp;&amp; *fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "dec_finish_seq timed out\n");</div><div class='add'>+			goto unlock_and_return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING &amp;&amp;</div><div class='add'>+		    retry++ &gt;= MAX_FIRMWARE_CALL_RETRY) {</div><div class='add'>+			ret = -ETIMEDOUT;</div><div class='add'>+			goto unlock_and_return;</div><div class='add'>+		}</div><div class='add'>+	} while (ret != 0);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: dec_finish_seq complete\n", __func__);</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;p_dec_info-&gt;vb_work);</div><div class='add'>+</div><div class='add'>+	for (i = 0 ; i &lt; MAX_REG_FRAME; i++) {</div><div class='add'>+		ret = reset_auxiliary_buffers(inst, i);</div><div class='add'>+		if (ret) {</div><div class='add'>+			ret = 0;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;p_dec_info-&gt;vb_task);</div><div class='add'>+</div><div class='add'>+unlock_and_return:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_init_seq(inst);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_get_seq_info(inst, info);</div><div class='add'>+	if (!ret)</div><div class='add'>+		p_dec_info-&gt;initial_info_obtained = true;</div><div class='add'>+</div><div class='add'>+	info-&gt;rd_ptr = wave5_dec_get_rd_ptr(inst);</div><div class='add'>+	info-&gt;wr_ptr = p_dec_info-&gt;stream_wr_ptr;</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;initial_info = *info;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,</div><div class='add'>+					   int num_of_display_fbs, int stride, int height)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	struct frame_buffer *fb;</div><div class='add'>+</div><div class='add'>+	if (num_of_decoding_fbs &gt;= WAVE5_MAX_FBS || num_of_display_fbs &gt;= WAVE5_MAX_FBS)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	p_dec_info-&gt;num_of_decoding_fbs = num_of_decoding_fbs;</div><div class='add'>+	p_dec_info-&gt;num_of_display_fbs = num_of_display_fbs;</div><div class='add'>+	p_dec_info-&gt;stride = stride;</div><div class='add'>+</div><div class='add'>+	if (!p_dec_info-&gt;initial_info_obtained)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (stride &lt; p_dec_info-&gt;initial_info.pic_width || (stride % 8 != 0) ||</div><div class='add'>+	    height &lt; p_dec_info-&gt;initial_info.pic_height)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	fb = inst-&gt;frame_buf;</div><div class='add'>+	ret = wave5_vpu_dec_register_framebuffer(inst, &amp;fb[p_dec_info-&gt;num_of_decoding_fbs],</div><div class='add'>+						 LINEAR_FRAME_MAP, p_dec_info-&gt;num_of_display_fbs);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_out;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_register_framebuffer(inst, &amp;fb[0], COMPRESSED_FRAME_MAP,</div><div class='add'>+						 p_dec_info-&gt;num_of_decoding_fbs);</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,</div><div class='add'>+				       dma_addr_t *pwr_ptr, size_t *size)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info;</div><div class='add'>+	dma_addr_t rd_ptr;</div><div class='add'>+	dma_addr_t wr_ptr;</div><div class='add'>+	int room;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	rd_ptr = wave5_dec_get_rd_ptr(inst);</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	wr_ptr = p_dec_info-&gt;stream_wr_ptr;</div><div class='add'>+</div><div class='add'>+	if (wr_ptr &lt; rd_ptr)</div><div class='add'>+		room = rd_ptr - wr_ptr;</div><div class='add'>+	else</div><div class='add'>+		room = (p_dec_info-&gt;stream_buf_end_addr - wr_ptr) +</div><div class='add'>+			(rd_ptr - p_dec_info-&gt;stream_buf_start_addr);</div><div class='add'>+	room--;</div><div class='add'>+</div><div class='add'>+	if (prd_ptr)</div><div class='add'>+		*prd_ptr = rd_ptr;</div><div class='add'>+	if (pwr_ptr)</div><div class='add'>+		*pwr_ptr = wr_ptr;</div><div class='add'>+	if (size)</div><div class='add'>+		*size = room;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info;</div><div class='add'>+	dma_addr_t wr_ptr;</div><div class='add'>+	dma_addr_t rd_ptr;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	wr_ptr = p_dec_info-&gt;stream_wr_ptr;</div><div class='add'>+	rd_ptr = p_dec_info-&gt;stream_rd_ptr;</div><div class='add'>+</div><div class='add'>+	if (size &gt; 0) {</div><div class='add'>+		if (wr_ptr &lt; rd_ptr &amp;&amp; rd_ptr &lt;= wr_ptr + size)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		wr_ptr += size;</div><div class='add'>+</div><div class='add'>+		if (wr_ptr &gt; p_dec_info-&gt;stream_buf_end_addr) {</div><div class='add'>+			u32 room = wr_ptr - p_dec_info-&gt;stream_buf_end_addr;</div><div class='add'>+</div><div class='add'>+			wr_ptr = p_dec_info-&gt;stream_buf_start_addr;</div><div class='add'>+			wr_ptr += room;</div><div class='add'>+		} else if (wr_ptr == p_dec_info-&gt;stream_buf_end_addr) {</div><div class='add'>+			wr_ptr = p_dec_info-&gt;stream_buf_start_addr;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		p_dec_info-&gt;stream_wr_ptr = wr_ptr;</div><div class='add'>+		p_dec_info-&gt;stream_rd_ptr = rd_ptr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = wave5_vpu_dec_set_bitstream_flag(inst, (size == 0));</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (p_dec_info-&gt;stride == 0) /* this means frame buffers have not been registered. */</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_decode(inst, res_fail);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_dec_set_rd_ptr(inst, addr);</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;stream_rd_ptr = addr;</div><div class='add'>+	if (update_wr_ptr)</div><div class='add'>+		p_dec_info-&gt;stream_wr_ptr = addr;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	dma_addr_t rd_ptr;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	rd_ptr = wave5_dec_get_rd_ptr(inst);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;inst-&gt;dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return rd_ptr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_rect rect_info;</div><div class='add'>+	u32 val;</div><div class='add'>+	u32 decoded_index;</div><div class='add'>+	u32 disp_idx;</div><div class='add'>+	u32 max_dec_index;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	struct dec_output_info *disp_info;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	memset(info, 0, sizeof(*info));</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_dec_get_result(inst, info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		info-&gt;rd_ptr = p_dec_info-&gt;stream_rd_ptr;</div><div class='add'>+		info-&gt;wr_ptr = p_dec_info-&gt;stream_wr_ptr;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	decoded_index = info-&gt;index_frame_decoded;</div><div class='add'>+</div><div class='add'>+	/* calculate display frame region */</div><div class='add'>+	val = 0;</div><div class='add'>+	rect_info.left = 0;</div><div class='add'>+	rect_info.right = 0;</div><div class='add'>+	rect_info.top = 0;</div><div class='add'>+	rect_info.bottom = 0;</div><div class='add'>+</div><div class='add'>+	if (decoded_index &lt; WAVE5_MAX_FBS) {</div><div class='add'>+		if (inst-&gt;std == W_HEVC_DEC || inst-&gt;std == W_AVC_DEC)</div><div class='add'>+			rect_info = p_dec_info-&gt;initial_info.pic_crop_rect;</div><div class='add'>+</div><div class='add'>+		if (inst-&gt;std == W_HEVC_DEC)</div><div class='add'>+			p_dec_info-&gt;dec_out_info[decoded_index].decoded_poc = info-&gt;decoded_poc;</div><div class='add'>+</div><div class='add'>+		p_dec_info-&gt;dec_out_info[decoded_index].rc_decoded = rect_info;</div><div class='add'>+	}</div><div class='add'>+	info-&gt;rc_decoded = rect_info;</div><div class='add'>+</div><div class='add'>+	disp_idx = info-&gt;index_frame_display;</div><div class='add'>+	if (info-&gt;index_frame_display &gt;= 0 &amp;&amp; info-&gt;index_frame_display &lt; WAVE5_MAX_FBS) {</div><div class='add'>+		disp_info = &amp;p_dec_info-&gt;dec_out_info[disp_idx];</div><div class='add'>+		if (info-&gt;index_frame_display != info-&gt;index_frame_decoded) {</div><div class='add'>+			/*</div><div class='add'>+			 * when index_frame_decoded &lt; 0, and index_frame_display &gt;= 0</div><div class='add'>+			 * info-&gt;dec_pic_width and info-&gt;dec_pic_height are still valid</div><div class='add'>+			 * but those of p_dec_info-&gt;dec_out_info[disp_idx] are invalid in VP9</div><div class='add'>+			 */</div><div class='add'>+			info-&gt;disp_pic_width = disp_info-&gt;dec_pic_width;</div><div class='add'>+			info-&gt;disp_pic_height = disp_info-&gt;dec_pic_height;</div><div class='add'>+		} else {</div><div class='add'>+			info-&gt;disp_pic_width = info-&gt;dec_pic_width;</div><div class='add'>+			info-&gt;disp_pic_height = info-&gt;dec_pic_height;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		info-&gt;rc_display = disp_info-&gt;rc_decoded;</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		info-&gt;rc_display.left = 0;</div><div class='add'>+		info-&gt;rc_display.right = 0;</div><div class='add'>+		info-&gt;rc_display.top = 0;</div><div class='add'>+		info-&gt;rc_display.bottom = 0;</div><div class='add'>+		info-&gt;disp_pic_width = 0;</div><div class='add'>+		info-&gt;disp_pic_height = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_dec_info-&gt;stream_rd_ptr = wave5_dec_get_rd_ptr(inst);</div><div class='add'>+	p_dec_info-&gt;frame_display_flag = vpu_read_reg(vpu_dev, W5_RET_DEC_DISP_IDC);</div><div class='add'>+</div><div class='add'>+	val = p_dec_info-&gt;num_of_decoding_fbs; //fb_offset</div><div class='add'>+</div><div class='add'>+	max_dec_index = (p_dec_info-&gt;num_of_decoding_fbs &gt; p_dec_info-&gt;num_of_display_fbs) ?</div><div class='add'>+		p_dec_info-&gt;num_of_decoding_fbs : p_dec_info-&gt;num_of_display_fbs;</div><div class='add'>+</div><div class='add'>+	if (info-&gt;index_frame_display &gt;= 0 &amp;&amp;</div><div class='add'>+	    info-&gt;index_frame_display &lt; (int)max_dec_index)</div><div class='add'>+		info-&gt;disp_frame = inst-&gt;frame_buf[val + info-&gt;index_frame_display];</div><div class='add'>+</div><div class='add'>+	info-&gt;rd_ptr = p_dec_info-&gt;stream_rd_ptr;</div><div class='add'>+	info-&gt;wr_ptr = p_dec_info-&gt;stream_wr_ptr;</div><div class='add'>+	info-&gt;frame_display_flag = p_dec_info-&gt;frame_display_flag;</div><div class='add'>+</div><div class='add'>+	info-&gt;sequence_no = p_dec_info-&gt;initial_info.sequence_no;</div><div class='add'>+	if (decoded_index &lt; WAVE5_MAX_FBS)</div><div class='add'>+		p_dec_info-&gt;dec_out_info[decoded_index] = *info;</div><div class='add'>+</div><div class='add'>+	if (disp_idx &lt; WAVE5_MAX_FBS)</div><div class='add'>+		info-&gt;disp_frame.sequence_no = info-&gt;sequence_no;</div><div class='add'>+</div><div class='add'>+	if (info-&gt;sequence_changed) {</div><div class='add'>+		memcpy((void *)&amp;p_dec_info-&gt;initial_info, (void *)&amp;p_dec_info-&gt;new_seq_info,</div><div class='add'>+		       sizeof(struct dec_initial_info));</div><div class='add'>+		p_dec_info-&gt;initial_info.sequence_no++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err_out:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (index &gt;= p_dec_info-&gt;num_of_display_fbs)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = wave5_dec_clr_disp_flag(inst, index);</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (index &gt;= p_dec_info-&gt;num_of_display_fbs)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = wave5_dec_set_disp_flag(inst, index);</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	if (index &gt;= MAX_REG_FRAME)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;frame_vbuf[index].size == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;inst-&gt;frame_vbuf[index]);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)</div><div class='add'>+{</div><div class='add'>+	struct dec_info *p_dec_info = &amp;inst-&gt;codec_info-&gt;dec_info;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case DEC_GET_QUEUE_STATUS: {</div><div class='add'>+		struct queue_status_info *queue_info = parameter;</div><div class='add'>+</div><div class='add'>+		queue_info-&gt;instance_queue_count = p_dec_info-&gt;instance_queue_count;</div><div class='add'>+		queue_info-&gt;report_queue_count = p_dec_info-&gt;report_queue_count;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DEC_RESET_FRAMEBUF_INFO: {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_REG_FRAME; i++) {</div><div class='add'>+			ret = wave5_vpu_dec_reset_framebuffer(inst, i);</div><div class='add'>+			if (ret)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; MAX_REG_FRAME; i++) {</div><div class='add'>+			ret = reset_auxiliary_buffers(inst, i);</div><div class='add'>+			if (ret)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		wave5_vdi_free_dma_memory(inst-&gt;dev, &amp;p_dec_info-&gt;vb_task);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case DEC_GET_SEQ_INFO: {</div><div class='add'>+		struct dec_initial_info *seq_info = parameter;</div><div class='add'>+</div><div class='add'>+		*seq_info = p_dec_info-&gt;initial_info;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_check_open_param(inst, open_param);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!wave5_vpu_is_init(vpu_dev)) {</div><div class='add'>+		mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	p_enc_info-&gt;open_param = *open_param;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_build_up_enc_param(vpu_dev-&gt;dev, inst, open_param);</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	int retry = 0;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	*fail_res = 0;</div><div class='add'>+	if (!inst-&gt;codec_info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = wave5_vpu_enc_finish_seq(inst, fail_res);</div><div class='add'>+		if (ret &lt; 0 &amp;&amp; *fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) {</div><div class='add'>+			dev_warn(inst-&gt;dev-&gt;dev, "enc_finish_seq timed out\n");</div><div class='add'>+			mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING &amp;&amp;</div><div class='add'>+		    retry++ &gt;= MAX_FIRMWARE_CALL_RETRY) {</div><div class='add'>+			mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+			return -ETIMEDOUT;</div><div class='add'>+		}</div><div class='add'>+	} while (ret != 0);</div><div class='add'>+</div><div class='add'>+	dev_dbg(inst-&gt;dev-&gt;dev, "%s: enc_finish_seq complete\n", __func__);</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_work);</div><div class='add'>+</div><div class='add'>+	if (inst-&gt;std == W_HEVC_ENC || inst-&gt;std == W_AVC_ENC) {</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_sub_sam_buf);</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_mv);</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_fbc_y_tbl);</div><div class='add'>+		wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_fbc_c_tbl);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wave5_vdi_free_dma_memory(vpu_dev, &amp;p_enc_info-&gt;vb_task);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,</div><div class='add'>+					unsigned int stride, int height,</div><div class='add'>+					enum tiled_map_type map_type)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+	unsigned int size_luma, size_chroma;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (p_enc_info-&gt;stride)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!p_enc_info-&gt;initial_info_obtained)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (num &lt; p_enc_info-&gt;initial_info.min_frame_buffer_count)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (stride == 0 || stride % 8 != 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (height &lt;= 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;num_frame_buffers = num;</div><div class='add'>+	p_enc_info-&gt;stride = stride;</div><div class='add'>+</div><div class='add'>+	size_luma = stride * height;</div><div class='add'>+	size_chroma = ALIGN(stride / 2, 16) * height;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num; i++) {</div><div class='add'>+		if (!inst-&gt;frame_buf[i].update_fb_info)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		inst-&gt;frame_buf[i].update_fb_info = false;</div><div class='add'>+		inst-&gt;frame_buf[i].stride = stride;</div><div class='add'>+		inst-&gt;frame_buf[i].height = height;</div><div class='add'>+		inst-&gt;frame_buf[i].map_type = COMPRESSED_FRAME_MAP;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_y_size = size_luma;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_cb = inst-&gt;frame_buf[i].buf_y + size_luma;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_cb_size = size_chroma;</div><div class='add'>+		inst-&gt;frame_buf[i].buf_cr_size = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_register_framebuffer(inst-&gt;dev-&gt;dev, inst, &amp;inst-&gt;frame_buf[0],</div><div class='add'>+						 COMPRESSED_FRAME_MAP,</div><div class='add'>+						 p_enc_info-&gt;num_frame_buffers);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int wave5_check_enc_param(struct vpu_instance *inst, struct enc_param *param)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+</div><div class='add'>+	if (!param)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!param-&gt;source_frame)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (p_enc_info-&gt;open_param.bit_rate == 0 &amp;&amp; inst-&gt;std == W_HEVC_ENC) {</div><div class='add'>+		if (param-&gt;pic_stream_buffer_addr % 16 || param-&gt;pic_stream_buffer_size == 0)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	if (param-&gt;pic_stream_buffer_addr % 8 || param-&gt;pic_stream_buffer_size == 0)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	*fail_res = 0;</div><div class='add'>+</div><div class='add'>+	if (p_enc_info-&gt;stride == 0) /* this means frame buffers have not been registered. */</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = wave5_check_enc_param(inst, param);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;pts_map[param-&gt;src_idx] = param-&gt;pts;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_encode(inst, param, fail_res);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_get_result(inst, info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		info-&gt;pts = 0;</div><div class='add'>+		goto unlock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (info-&gt;recon_frame_index &gt;= 0)</div><div class='add'>+		info-&gt;pts = p_enc_info-&gt;pts_map[info-&gt;enc_src_idx];</div><div class='add'>+</div><div class='add'>+unlock:</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+</div><div class='add'>+	switch (cmd) {</div><div class='add'>+	case ENABLE_ROTATION:</div><div class='add'>+		p_enc_info-&gt;rotation_enable = true;</div><div class='add'>+		break;</div><div class='add'>+	case ENABLE_MIRRORING:</div><div class='add'>+		p_enc_info-&gt;mirror_enable = true;</div><div class='add'>+		break;</div><div class='add'>+	case SET_MIRROR_DIRECTION: {</div><div class='add'>+		enum mirror_direction mir_dir;</div><div class='add'>+</div><div class='add'>+		mir_dir = *(enum mirror_direction *)parameter;</div><div class='add'>+		if (mir_dir != MIRDIR_NONE &amp;&amp; mir_dir != MIRDIR_HOR &amp;&amp;</div><div class='add'>+		    mir_dir != MIRDIR_VER &amp;&amp; mir_dir != MIRDIR_HOR_VER)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		p_enc_info-&gt;mirror_direction = mir_dir;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case SET_ROTATION_ANGLE: {</div><div class='add'>+		int angle;</div><div class='add'>+</div><div class='add'>+		angle = *(int *)parameter;</div><div class='add'>+		if (angle &amp;&amp; angle != 90 &amp;&amp; angle != 180 &amp;&amp; angle != 270)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		if (p_enc_info-&gt;initial_info_obtained &amp;&amp; (angle == 90 || angle == 270))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		p_enc_info-&gt;rotation_angle = angle;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case ENC_GET_QUEUE_STATUS: {</div><div class='add'>+		struct queue_status_info *queue_info = parameter;</div><div class='add'>+</div><div class='add'>+		queue_info-&gt;instance_queue_count = p_enc_info-&gt;instance_queue_count;</div><div class='add'>+		queue_info-&gt;report_queue_count = p_enc_info-&gt;report_queue_count;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_init_seq(inst);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info)</div><div class='add'>+{</div><div class='add'>+	struct enc_info *p_enc_info = &amp;inst-&gt;codec_info-&gt;enc_info;</div><div class='add'>+	int ret;</div><div class='add'>+	struct vpu_device *vpu_dev = inst-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (!info)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = mutex_lock_interruptible(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = wave5_vpu_enc_get_seq_info(inst, info);</div><div class='add'>+	if (ret) {</div><div class='add'>+		p_enc_info-&gt;initial_info_obtained = false;</div><div class='add'>+		mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	p_enc_info-&gt;initial_info_obtained = true;</div><div class='add'>+	p_enc_info-&gt;initial_info = *info;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;vpu_dev-&gt;hw_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h<br/>new file mode 100644<br/>index 000000000000..352f6e904e50<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuapi.h</a></div><div class='hunk'>@@ -0,0 +1,870 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - helper definitions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef VPUAPI_H_INCLUDED</div><div class='add'>+#define VPUAPI_H_INCLUDED</div><div class='add'>+</div><div class='add'>+#include &lt;linux/idr.h&gt;</div><div class='add'>+#include &lt;linux/genalloc.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-mem2mem.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ctrls.h&gt;</div><div class='add'>+#include "wave5-vpuerror.h"</div><div class='add'>+#include "wave5-vpuconfig.h"</div><div class='add'>+#include "wave5-vdi.h"</div><div class='add'>+</div><div class='add'>+enum product_id {</div><div class='add'>+	PRODUCT_ID_521,</div><div class='add'>+	PRODUCT_ID_511,</div><div class='add'>+	PRODUCT_ID_517,</div><div class='add'>+	PRODUCT_ID_NONE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_attr;</div><div class='add'>+</div><div class='add'>+enum vpu_instance_type {</div><div class='add'>+	VPU_INST_TYPE_DEC = 0,</div><div class='add'>+	VPU_INST_TYPE_ENC = 1</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum vpu_instance_state {</div><div class='add'>+	VPU_INST_STATE_NONE = 0,</div><div class='add'>+	VPU_INST_STATE_OPEN = 1,</div><div class='add'>+	VPU_INST_STATE_INIT_SEQ = 2,</div><div class='add'>+	VPU_INST_STATE_PIC_RUN = 3,</div><div class='add'>+	VPU_INST_STATE_STOP = 4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Maximum available on hardware. */</div><div class='add'>+#define WAVE5_MAX_FBS 32</div><div class='add'>+</div><div class='add'>+#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2)</div><div class='add'>+</div><div class='add'>+#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64)</div><div class='add'>+#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80)</div><div class='add'>+</div><div class='add'>+#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32)</div><div class='add'>+#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32)</div><div class='add'>+#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32)</div><div class='add'>+#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * common struct and definition</div><div class='add'>+ */</div><div class='add'>+enum cod_std {</div><div class='add'>+	STD_AVC = 0,</div><div class='add'>+	STD_HEVC = 12,</div><div class='add'>+	STD_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum wave_std {</div><div class='add'>+	W_HEVC_DEC = 0x00,</div><div class='add'>+	W_HEVC_ENC = 0x01,</div><div class='add'>+	W_AVC_DEC = 0x02,</div><div class='add'>+	W_AVC_ENC = 0x03,</div><div class='add'>+	STD_UNKNOWN = 0xFF</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum set_param_option {</div><div class='add'>+	OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */</div><div class='add'>+	OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */</div><div class='add'>+	OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */</div><div class='add'>+	OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */</div><div class='add'>+	OPT_CHANGE_PARAM = 0x10,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* PROFILE &amp; LEVEL */</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* HEVC */</div><div class='add'>+#define HEVC_PROFILE_MAIN 1</div><div class='add'>+#define HEVC_PROFILE_MAIN10 2</div><div class='add'>+#define HEVC_PROFILE_STILLPICTURE 3</div><div class='add'>+#define HEVC_PROFILE_MAIN10_STILLPICTURE 2</div><div class='add'>+</div><div class='add'>+/* H.264 profile for encoder*/</div><div class='add'>+#define H264_PROFILE_BP 1</div><div class='add'>+#define H264_PROFILE_MP 2</div><div class='add'>+#define H264_PROFILE_EXTENDED 3</div><div class='add'>+#define H264_PROFILE_HP 4</div><div class='add'>+#define H264_PROFILE_HIGH10 5</div><div class='add'>+#define H264_PROFILE_HIGH422 6</div><div class='add'>+#define H264_PROFILE_HIGH444 7</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* error codes */</div><div class='add'>+/************************************************************************/</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* utility macros */</div><div class='add'>+/************************************************************************/</div><div class='add'>+</div><div class='add'>+/* Initialize sequence firmware command mode */</div><div class='add'>+#define INIT_SEQ_NORMAL				1</div><div class='add'>+</div><div class='add'>+/* Decode firmware command mode */</div><div class='add'>+#define DEC_PIC_NORMAL				0</div><div class='add'>+</div><div class='add'>+/* bit_alloc_mode */</div><div class='add'>+#define BIT_ALLOC_MODE_FIXED_RATIO		2</div><div class='add'>+</div><div class='add'>+/* bit_rate */</div><div class='add'>+#define MAX_BIT_RATE				700000000</div><div class='add'>+</div><div class='add'>+/* decoding_refresh_type */</div><div class='add'>+#define DEC_REFRESH_TYPE_NON_IRAP		0</div><div class='add'>+#define DEC_REFRESH_TYPE_CRA			1</div><div class='add'>+#define DEC_REFRESH_TYPE_IDR			2</div><div class='add'>+</div><div class='add'>+/* depend_slice_mode */</div><div class='add'>+#define DEPEND_SLICE_MODE_RECOMMENDED		1</div><div class='add'>+#define DEPEND_SLICE_MODE_BOOST			2</div><div class='add'>+#define DEPEND_SLICE_MODE_FAST			3</div><div class='add'>+</div><div class='add'>+/* hvs_max_delta_qp */</div><div class='add'>+#define MAX_HVS_MAX_DELTA_QP			51</div><div class='add'>+</div><div class='add'>+/* intra_refresh_mode */</div><div class='add'>+#define REFRESH_MODE_CTU_ROWS			1</div><div class='add'>+#define REFRESH_MODE_CTU_COLUMNS		2</div><div class='add'>+#define REFRESH_MODE_CTU_STEP_SIZE		3</div><div class='add'>+#define REFRESH_MODE_CTUS			4</div><div class='add'>+</div><div class='add'>+/* intra_mb_refresh_mode */</div><div class='add'>+#define REFRESH_MB_MODE_NONE			0</div><div class='add'>+#define REFRESH_MB_MODE_CTU_ROWS		1</div><div class='add'>+#define REFRESH_MB_MODE_CTU_COLUMNS		2</div><div class='add'>+#define REFRESH_MB_MODE_CTU_STEP_SIZE		3</div><div class='add'>+</div><div class='add'>+/* intra_qp */</div><div class='add'>+#define MAX_INTRA_QP				63</div><div class='add'>+</div><div class='add'>+/* nr_inter_weight_* */</div><div class='add'>+#define MAX_INTER_WEIGHT			31</div><div class='add'>+</div><div class='add'>+/* nr_intra_weight_* */</div><div class='add'>+#define MAX_INTRA_WEIGHT			31</div><div class='add'>+</div><div class='add'>+/* nr_noise_sigma_* */</div><div class='add'>+#define MAX_NOISE_SIGMA				255</div><div class='add'>+</div><div class='add'>+/* bitstream_buffer_size */</div><div class='add'>+#define MIN_BITSTREAM_BUFFER_SIZE		1024</div><div class='add'>+#define MIN_BITSTREAM_BUFFER_SIZE_WAVE521	(1024 * 64)</div><div class='add'>+</div><div class='add'>+/* vbv_buffer_size */</div><div class='add'>+#define MIN_VBV_BUFFER_SIZE			10</div><div class='add'>+#define MAX_VBV_BUFFER_SIZE			3000</div><div class='add'>+</div><div class='add'>+#define BUFFER_MARGIN				4096</div><div class='add'>+</div><div class='add'>+#define MAX_FIRMWARE_CALL_RETRY			10</div><div class='add'>+</div><div class='add'>+#define VDI_LITTLE_ENDIAN	0x0</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Parameters of DEC_SET_SEQ_CHANGE_MASK</div><div class='add'>+ */</div><div class='add'>+#define SEQ_CHANGE_ENABLE_PROFILE BIT(5)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_SIZE BIT(16)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_ASPECT_RATIO BIT(21)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL BIT(23)</div><div class='add'>+#define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO BIT(29)</div><div class='add'>+</div><div class='add'>+#define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_SIZE | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_BITDEPTH | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_DPB_COUNT)</div><div class='add'>+</div><div class='add'>+#define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_BITDEPTH | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_DPB_COUNT | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_ASPECT_RATIO | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_VIDEO_SIGNAL | \</div><div class='add'>+		SEQ_CHANGE_ENABLE_VUI_TIMING_INFO)</div><div class='add'>+</div><div class='add'>+#define DISPLAY_IDX_FLAG_SEQ_END -1</div><div class='add'>+#define DISPLAY_IDX_FLAG_NO_FB -3</div><div class='add'>+#define DECODED_IDX_FLAG_NO_FB -1</div><div class='add'>+#define DECODED_IDX_FLAG_SKIP -2</div><div class='add'>+</div><div class='add'>+#define RECON_IDX_FLAG_ENC_END -1</div><div class='add'>+#define RECON_IDX_FLAG_ENC_DELAY -2</div><div class='add'>+#define RECON_IDX_FLAG_HEADER_ONLY -3</div><div class='add'>+#define RECON_IDX_FLAG_CHANGE_PARAM -4</div><div class='add'>+</div><div class='add'>+enum codec_command {</div><div class='add'>+	ENABLE_ROTATION,</div><div class='add'>+	ENABLE_MIRRORING,</div><div class='add'>+	SET_MIRROR_DIRECTION,</div><div class='add'>+	SET_ROTATION_ANGLE,</div><div class='add'>+	DEC_GET_QUEUE_STATUS,</div><div class='add'>+	ENC_GET_QUEUE_STATUS,</div><div class='add'>+	DEC_RESET_FRAMEBUF_INFO,</div><div class='add'>+	DEC_GET_SEQ_INFO,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum mirror_direction {</div><div class='add'>+	MIRDIR_NONE, /* no mirroring */</div><div class='add'>+	MIRDIR_VER, /* vertical mirroring */</div><div class='add'>+	MIRDIR_HOR, /* horizontal mirroring */</div><div class='add'>+	MIRDIR_HOR_VER /* horizontal and vertical mirroring */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum frame_buffer_format {</div><div class='add'>+	FORMAT_ERR = -1,</div><div class='add'>+	FORMAT_420 = 0, /* 8bit */</div><div class='add'>+	FORMAT_422, /* 8bit */</div><div class='add'>+	FORMAT_224, /* 8bit */</div><div class='add'>+	FORMAT_444, /* 8bit */</div><div class='add'>+	FORMAT_400, /* 8bit */</div><div class='add'>+</div><div class='add'>+	/* little endian perspective */</div><div class='add'>+	/* | addr 0 | addr 1 | */</div><div class='add'>+	FORMAT_420_P10_16BIT_MSB = 5, /* lsb |000000xx|xxxxxxxx | msb */</div><div class='add'>+	FORMAT_420_P10_16BIT_LSB, /* lsb |xxxxxxx |xx000000 | msb */</div><div class='add'>+	FORMAT_420_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */</div><div class='add'>+	FORMAT_420_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */</div><div class='add'>+</div><div class='add'>+	/* 4:2:2 packed format */</div><div class='add'>+	/* little endian perspective */</div><div class='add'>+	/* | addr 0 | addr 1 | */</div><div class='add'>+	FORMAT_422_P10_16BIT_MSB, /* lsb |000000xx |xxxxxxxx | msb */</div><div class='add'>+	FORMAT_422_P10_16BIT_LSB, /* lsb |xxxxxxxx |xx000000 | msb */</div><div class='add'>+	FORMAT_422_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */</div><div class='add'>+	FORMAT_422_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */</div><div class='add'>+</div><div class='add'>+	FORMAT_YUYV, /* 8bit packed format : Y0U0Y1V0 Y2U1Y3V1 ... */</div><div class='add'>+	FORMAT_YUYV_P10_16BIT_MSB,</div><div class='add'>+	FORMAT_YUYV_P10_16BIT_LSB,</div><div class='add'>+	FORMAT_YUYV_P10_32BIT_MSB,</div><div class='add'>+	FORMAT_YUYV_P10_32BIT_LSB,</div><div class='add'>+</div><div class='add'>+	FORMAT_YVYU, /* 8bit packed format : Y0V0Y1U0 Y2V1Y3U1 ... */</div><div class='add'>+	FORMAT_YVYU_P10_16BIT_MSB,</div><div class='add'>+	FORMAT_YVYU_P10_16BIT_LSB,</div><div class='add'>+	FORMAT_YVYU_P10_32BIT_MSB,</div><div class='add'>+	FORMAT_YVYU_P10_32BIT_LSB,</div><div class='add'>+</div><div class='add'>+	FORMAT_UYVY, /* 8bit packed format : U0Y0V0Y1 U1Y2V1Y3 ... */</div><div class='add'>+	FORMAT_UYVY_P10_16BIT_MSB,</div><div class='add'>+	FORMAT_UYVY_P10_16BIT_LSB,</div><div class='add'>+	FORMAT_UYVY_P10_32BIT_MSB,</div><div class='add'>+	FORMAT_UYVY_P10_32BIT_LSB,</div><div class='add'>+</div><div class='add'>+	FORMAT_VYUY, /* 8bit packed format : V0Y0U0Y1 V1Y2U1Y3 ... */</div><div class='add'>+	FORMAT_VYUY_P10_16BIT_MSB,</div><div class='add'>+	FORMAT_VYUY_P10_16BIT_LSB,</div><div class='add'>+	FORMAT_VYUY_P10_32BIT_MSB,</div><div class='add'>+	FORMAT_VYUY_P10_32BIT_LSB,</div><div class='add'>+</div><div class='add'>+	FORMAT_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum packed_format_num {</div><div class='add'>+	NOT_PACKED = 0,</div><div class='add'>+	PACKED_YUYV,</div><div class='add'>+	PACKED_YVYU,</div><div class='add'>+	PACKED_UYVY,</div><div class='add'>+	PACKED_VYUY,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum wave5_interrupt_bit {</div><div class='add'>+	INT_WAVE5_INIT_VPU = 0,</div><div class='add'>+	INT_WAVE5_WAKEUP_VPU = 1,</div><div class='add'>+	INT_WAVE5_SLEEP_VPU = 2,</div><div class='add'>+	INT_WAVE5_CREATE_INSTANCE = 3,</div><div class='add'>+	INT_WAVE5_FLUSH_INSTANCE = 4,</div><div class='add'>+	INT_WAVE5_DESTROY_INSTANCE = 5,</div><div class='add'>+	INT_WAVE5_INIT_SEQ = 6,</div><div class='add'>+	INT_WAVE5_SET_FRAMEBUF = 7,</div><div class='add'>+	INT_WAVE5_DEC_PIC = 8,</div><div class='add'>+	INT_WAVE5_ENC_PIC = 8,</div><div class='add'>+	INT_WAVE5_ENC_SET_PARAM = 9,</div><div class='add'>+	INT_WAVE5_DEC_QUERY = 14,</div><div class='add'>+	INT_WAVE5_BSBUF_EMPTY = 15,</div><div class='add'>+	INT_WAVE5_BSBUF_FULL = 15,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum pic_type {</div><div class='add'>+	PIC_TYPE_I = 0,</div><div class='add'>+	PIC_TYPE_P = 1,</div><div class='add'>+	PIC_TYPE_B = 2,</div><div class='add'>+	PIC_TYPE_IDR = 5, /* H.264/H.265 IDR (Instantaneous Decoder Refresh) picture */</div><div class='add'>+	PIC_TYPE_MAX /* no meaning */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum sw_reset_mode {</div><div class='add'>+	SW_RESET_SAFETY,</div><div class='add'>+	SW_RESET_FORCE,</div><div class='add'>+	SW_RESET_ON_BOOT</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum tiled_map_type {</div><div class='add'>+	LINEAR_FRAME_MAP = 0, /* linear frame map type */</div><div class='add'>+	COMPRESSED_FRAME_MAP = 17, /* compressed frame map type*/</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum temporal_id_mode {</div><div class='add'>+	TEMPORAL_ID_MODE_ABSOLUTE,</div><div class='add'>+	TEMPORAL_ID_MODE_RELATIVE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_attr {</div><div class='add'>+	u32 product_id;</div><div class='add'>+	char product_name[8]; /* product name in ascii code */</div><div class='add'>+	u32 product_version;</div><div class='add'>+	u32 fw_version;</div><div class='add'>+	u32 customer_id;</div><div class='add'>+	u32 support_decoders; /* bitmask */</div><div class='add'>+	u32 support_encoders; /* bitmask */</div><div class='add'>+	u32 support_backbone: 1;</div><div class='add'>+	u32 support_avc10bit_enc: 1;</div><div class='add'>+	u32 support_hevc10bit_enc: 1;</div><div class='add'>+	u32 support_vcore_backbone: 1;</div><div class='add'>+	u32 support_vcpu_backbone: 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct frame_buffer {</div><div class='add'>+	dma_addr_t buf_y;</div><div class='add'>+	dma_addr_t buf_cb;</div><div class='add'>+	dma_addr_t buf_cr;</div><div class='add'>+	unsigned int buf_y_size;</div><div class='add'>+	unsigned int buf_cb_size;</div><div class='add'>+	unsigned int buf_cr_size;</div><div class='add'>+	enum tiled_map_type map_type;</div><div class='add'>+	unsigned int stride; /* horizontal stride for the given frame buffer */</div><div class='add'>+	unsigned int width; /* width of the given frame buffer */</div><div class='add'>+	unsigned int height; /* height of the given frame buffer */</div><div class='add'>+	size_t size; /* size of the given frame buffer */</div><div class='add'>+	unsigned int sequence_no;</div><div class='add'>+	bool update_fb_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_rect {</div><div class='add'>+	unsigned int left; /* horizontal pixel offset from left edge */</div><div class='add'>+	unsigned int top; /* vertical pixel offset from top edge */</div><div class='add'>+	unsigned int right; /* horizontal pixel offset from right edge */</div><div class='add'>+	unsigned int bottom; /* vertical pixel offset from bottom edge */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * decode struct and definition</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+struct dec_open_param {</div><div class='add'>+	dma_addr_t bitstream_buffer;</div><div class='add'>+	size_t bitstream_buffer_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dec_initial_info {</div><div class='add'>+	u32 pic_width;</div><div class='add'>+	u32 pic_height;</div><div class='add'>+	struct vpu_rect pic_crop_rect;</div><div class='add'>+	u32 min_frame_buffer_count; /* between 1 to 16 */</div><div class='add'>+</div><div class='add'>+	u32 profile;</div><div class='add'>+	u32 luma_bitdepth; /* bit-depth of the luma sample */</div><div class='add'>+	u32 chroma_bitdepth; /* bit-depth of the chroma sample */</div><div class='add'>+	u32 seq_init_err_reason;</div><div class='add'>+	dma_addr_t rd_ptr; /* read pointer of bitstream buffer */</div><div class='add'>+	dma_addr_t wr_ptr; /* write pointer of bitstream buffer */</div><div class='add'>+	u32 sequence_no;</div><div class='add'>+	u32 vlc_buf_size;</div><div class='add'>+	u32 param_buf_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dec_output_info {</div><div class='add'>+	/**</div><div class='add'>+	 * This is a frame buffer index for the picture to be displayed at the moment</div><div class='add'>+	 * among frame buffers which are registered using vpu_dec_register_frame_buffer().</div><div class='add'>+	 * Frame data that will be displayed is stored in the frame buffer with this index</div><div class='add'>+	 * When there is no display delay, this index is always the equal to</div><div class='add'>+	 * index_frame_decoded, however, if displaying is delayed (for display</div><div class='add'>+	 * reordering in AVC or B-frames in VC1), this index might be different to</div><div class='add'>+	 * index_frame_decoded. By checking this index, HOST applications can easily figure</div><div class='add'>+	 * out whether sequence decoding has been finished or not.</div><div class='add'>+	 *</div><div class='add'>+	 * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture</div><div class='add'>+	 * reordering or skip option</div><div class='add'>+	 * -1(0xFFFF) : when there is no more output for display at the end of sequence</div><div class='add'>+	 * decoding</div><div class='add'>+	 */</div><div class='add'>+	s32 index_frame_display;</div><div class='add'>+	/**</div><div class='add'>+	 * This is the frame buffer index of the decoded picture among the frame buffers which were</div><div class='add'>+	 * registered using vpu_dec_register_frame_buffer(). The currently decoded frame is stored</div><div class='add'>+	 * into the frame buffer specified by this index.</div><div class='add'>+	 *</div><div class='add'>+	 * -2 : indicates that no decoded output is generated because decoder meets EOS</div><div class='add'>+	 * (end of sequence) or skip</div><div class='add'>+	 * -1 : indicates that the decoder fails to decode a picture because there is no available</div><div class='add'>+	 * frame buffer</div><div class='add'>+	 */</div><div class='add'>+	s32 index_frame_decoded;</div><div class='add'>+	s32 index_frame_decoded_for_tiled;</div><div class='add'>+	u32 nal_type;</div><div class='add'>+	unsigned int pic_type;</div><div class='add'>+	struct vpu_rect rc_display;</div><div class='add'>+	unsigned int disp_pic_width;</div><div class='add'>+	unsigned int disp_pic_height;</div><div class='add'>+	struct vpu_rect rc_decoded;</div><div class='add'>+	u32 dec_pic_width;</div><div class='add'>+	u32 dec_pic_height;</div><div class='add'>+	s32 decoded_poc;</div><div class='add'>+	int temporal_id; /* temporal ID of the picture */</div><div class='add'>+	dma_addr_t rd_ptr; /* stream buffer read pointer for the current decoder instance */</div><div class='add'>+	dma_addr_t wr_ptr; /* stream buffer write pointer for the current decoder instance */</div><div class='add'>+	struct frame_buffer disp_frame;</div><div class='add'>+	u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */</div><div class='add'>+	/**</div><div class='add'>+	 * this variable reports that sequence has been changed while H.264/AVC stream decoding.</div><div class='add'>+	 * if it is 1, HOST application can get the new sequence information by calling</div><div class='add'>+	 * vpu_dec_get_initial_info() or wave5_vpu_dec_issue_seq_init().</div><div class='add'>+	 *</div><div class='add'>+	 * for H.265/HEVC decoder, each bit has a different meaning as follows.</div><div class='add'>+	 *</div><div class='add'>+	 * sequence_changed[5] : it indicates that the profile_idc has been changed</div><div class='add'>+	 * sequence_changed[16] : it indicates that the resolution has been changed</div><div class='add'>+	 * sequence_changed[19] : it indicates that the required number of frame buffer has</div><div class='add'>+	 * been changed.</div><div class='add'>+	 */</div><div class='add'>+	unsigned int frame_cycle; /* reports the number of cycles for processing a frame */</div><div class='add'>+	u32 sequence_no;</div><div class='add'>+</div><div class='add'>+	u32 dec_host_cmd_tick; /* tick of DEC_PIC command for the picture */</div><div class='add'>+	u32 dec_decode_end_tick; /* end tick of decoding slices of the picture */</div><div class='add'>+</div><div class='add'>+	u32 sequence_changed;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct queue_status_info {</div><div class='add'>+	u32 instance_queue_count;</div><div class='add'>+	u32 report_queue_count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * encode struct and definition</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define MAX_NUM_TEMPORAL_LAYER 7</div><div class='add'>+#define MAX_NUM_SPATIAL_LAYER 3</div><div class='add'>+#define MAX_GOP_NUM 8</div><div class='add'>+</div><div class='add'>+struct custom_gop_pic_param {</div><div class='add'>+	u32 pic_type; /* picture type of nth picture in the custom GOP */</div><div class='add'>+	u32 poc_offset; /* POC of nth picture in the custom GOP */</div><div class='add'>+	u32 pic_qp; /* quantization parameter of nth picture in the custom GOP */</div><div class='add'>+	u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */</div><div class='add'>+	u32 ref_poc_l0; /* POC of reference L0 of nth picture in the custom GOP */</div><div class='add'>+	u32 ref_poc_l1; /* POC of reference L1 of nth picture in the custom GOP */</div><div class='add'>+	s32 temporal_id; /* temporal ID of nth picture in the custom GOP */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_wave_param {</div><div class='add'>+	/*</div><div class='add'>+	 * profile indicator (HEVC only)</div><div class='add'>+	 *</div><div class='add'>+	 * 0 : the firmware determines a profile according to the internal_bit_depth</div><div class='add'>+	 * 1 : main profile</div><div class='add'>+	 * 2 : main10 profile</div><div class='add'>+	 * 3 : main still picture profile</div><div class='add'>+	 * In the AVC encoder, a profile cannot be set by the host application.</div><div class='add'>+	 * The firmware decides it based on internal_bit_depth.</div><div class='add'>+	 * profile = HIGH (bitdepth 8) profile = HIGH10 (bitdepth 10)</div><div class='add'>+	 */</div><div class='add'>+	u32 profile;</div><div class='add'>+	u32 level; /* level indicator (level * 10) */</div><div class='add'>+	u32 internal_bit_depth: 4; /* 8/10 */</div><div class='add'>+	u32 gop_preset_idx: 4; /* 0 - 9 */</div><div class='add'>+	u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */</div><div class='add'>+	u32 intra_qp; /* quantization parameter of intra picture */</div><div class='add'>+	u32 intra_period; /* period of intra picture in GOP size */</div><div class='add'>+	u32 conf_win_top; /* top offset of conformance window */</div><div class='add'>+	u32 conf_win_bot; /* bottom offset of conformance window */</div><div class='add'>+	u32 conf_win_left; /* left offset of conformance window */</div><div class='add'>+	u32 conf_win_right; /* right offset of conformance window */</div><div class='add'>+	u32 intra_refresh_mode: 3;</div><div class='add'>+	/*</div><div class='add'>+	 * Argument for intra_ctu_refresh_mode.</div><div class='add'>+	 *</div><div class='add'>+	 * Depending on intra_refresh_mode, it can mean one of the following:</div><div class='add'>+	 * - intra_ctu_refresh_mode (1) -&gt; number of consecutive CTU rows</div><div class='add'>+	 * - intra_ctu_refresh_mode (2) -&gt; the number of consecutive CTU columns</div><div class='add'>+	 * - intra_ctu_refresh_mode (3) -&gt; step size in CTU</div><div class='add'>+	 * - intra_ctu_refresh_mode (4) -&gt; number of intra ct_us to be encoded in a picture</div><div class='add'>+	 */</div><div class='add'>+	u32 intra_refresh_arg;</div><div class='add'>+	/*</div><div class='add'>+	 * 0 : custom setting</div><div class='add'>+	 * 1 : recommended encoder parameters (slow encoding speed, highest picture quality)</div><div class='add'>+	 * 2 : boost mode (normal encoding speed, moderate picture quality)</div><div class='add'>+	 * 3 : fast mode (fast encoding speed, low picture quality)</div><div class='add'>+	 */</div><div class='add'>+	u32 depend_slice_mode : 2;</div><div class='add'>+	u32 depend_slice_mode_arg;</div><div class='add'>+	u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/</div><div class='add'>+	u32 independ_slice_mode_arg;</div><div class='add'>+	u32 max_num_merge: 2;</div><div class='add'>+	s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */</div><div class='add'>+	s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */</div><div class='add'>+	u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */</div><div class='add'>+	u32 hvs_max_delta_qp; /* maximum delta QP for HVS */</div><div class='add'>+	s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */</div><div class='add'>+	s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */</div><div class='add'>+	s32 initial_rc_qp;</div><div class='add'>+	u32 nr_intra_weight_y;</div><div class='add'>+	u32 nr_intra_weight_cb; /* weight to cb noise level for intra picture (0 ~ 31) */</div><div class='add'>+	u32 nr_intra_weight_cr; /* weight to cr noise level for intra picture (0 ~ 31) */</div><div class='add'>+	u32 nr_inter_weight_y;</div><div class='add'>+	u32 nr_inter_weight_cb; /* weight to cb noise level for inter picture (0 ~ 31) */</div><div class='add'>+	u32 nr_inter_weight_cr; /* weight to cr noise level for inter picture (0 ~ 31) */</div><div class='add'>+	u32 min_qp_i; /* minimum QP of I picture for rate control */</div><div class='add'>+	u32 max_qp_i; /* maximum QP of I picture for rate control */</div><div class='add'>+	u32 min_qp_p; /* minimum QP of P picture for rate control */</div><div class='add'>+	u32 max_qp_p; /* maximum QP of P picture for rate control */</div><div class='add'>+	u32 min_qp_b; /* minimum QP of B picture for rate control */</div><div class='add'>+	u32 max_qp_b; /* maximum QP of B picture for rate control */</div><div class='add'>+	u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */</div><div class='add'>+	u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */</div><div class='add'>+	u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */</div><div class='add'>+	/**</div><div class='add'>+	 * Argument for intra_mb_refresh_mode.</div><div class='add'>+	 *</div><div class='add'>+	 * intra_mb_refresh_mode (1) -&gt; number of consecutive MB rows</div><div class='add'>+	 * intra_mb_refresh_mode (2) -&gt;the number of consecutive MB columns</div><div class='add'>+	 * intra_mb_refresh_mode (3) -&gt; step size in MB</div><div class='add'>+	 */</div><div class='add'>+	u32 intra_mb_refresh_arg;</div><div class='add'>+	u32 rc_weight_param;</div><div class='add'>+	u32 rc_weight_buf;</div><div class='add'>+</div><div class='add'>+	/* flags */</div><div class='add'>+	u32 en_still_picture: 1; /* still picture profile */</div><div class='add'>+	u32 tier: 1; /* 0=main, 1=high */</div><div class='add'>+	u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */</div><div class='add'>+	u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */</div><div class='add'>+	u32 lossless_enable: 1; /* enable lossless encoding */</div><div class='add'>+	u32 const_intra_pred_flag: 1; /* enable constrained intra prediction */</div><div class='add'>+	u32 tmvp_enable: 1; /* enable temporal motion vector prediction */</div><div class='add'>+	u32 wpp_enable: 1;</div><div class='add'>+	u32 disable_deblk: 1; /* disable in-loop deblocking filtering */</div><div class='add'>+	u32 lf_cross_slice_boundary_enable: 1;</div><div class='add'>+	u32 skip_intra_trans: 1;</div><div class='add'>+	u32 sao_enable: 1; /* enable SAO (sample adaptive offset) */</div><div class='add'>+	u32 intra_nx_n_enable: 1; /* enables intra nx_n p_us */</div><div class='add'>+	u32 cu_level_rc_enable: 1; /* enable CU level rate control */</div><div class='add'>+	u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */</div><div class='add'>+	u32 strong_intra_smooth_enable: 1; /* enable strong intra smoothing */</div><div class='add'>+	u32 rdo_skip: 1; /* skip RDO (rate distortion optimization) */</div><div class='add'>+	u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */</div><div class='add'>+	u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */</div><div class='add'>+	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_open_param {</div><div class='add'>+	dma_addr_t bitstream_buffer;</div><div class='add'>+	unsigned int bitstream_buffer_size;</div><div class='add'>+	u32 pic_width; /* width of a picture to be encoded in unit of sample */</div><div class='add'>+	u32 pic_height; /* height of a picture to be encoded in unit of sample */</div><div class='add'>+	u32 frame_rate_info;/* desired fps */</div><div class='add'>+	u32 vbv_buffer_size;</div><div class='add'>+	u32 bit_rate; /* target bitrate in bps */</div><div class='add'>+	struct enc_wave_param wave_param;</div><div class='add'>+	enum packed_format_num packed_format; /* &lt;&lt;vpuapi_h_packed_format_num&gt;&gt; */</div><div class='add'>+	enum frame_buffer_format src_format;</div><div class='add'>+	bool line_buf_int_en;</div><div class='add'>+	u32 rc_enable : 1; /* rate control */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_initial_info {</div><div class='add'>+	u32 min_frame_buffer_count; /* minimum number of frame buffers */</div><div class='add'>+	u32 min_src_frame_count; /* minimum number of source buffers */</div><div class='add'>+	u32 seq_init_err_reason;</div><div class='add'>+	u32 warn_info;</div><div class='add'>+	u32 vlc_buf_size; /* size of task buffer */</div><div class='add'>+	u32 param_buf_size; /* size of task buffer */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Flags to encode NAL units explicitly</div><div class='add'>+ */</div><div class='add'>+struct enc_code_opt {</div><div class='add'>+	u32 implicit_header_encode: 1;</div><div class='add'>+	u32 encode_vcl: 1;</div><div class='add'>+	u32 encode_vps: 1;</div><div class='add'>+	u32 encode_sps: 1;</div><div class='add'>+	u32 encode_pps: 1;</div><div class='add'>+	u32 encode_aud: 1;</div><div class='add'>+	u32 encode_eos: 1;</div><div class='add'>+	u32 encode_eob: 1;</div><div class='add'>+	u32 encode_vui: 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_param {</div><div class='add'>+	struct frame_buffer *source_frame;</div><div class='add'>+	u32 pic_stream_buffer_addr;</div><div class='add'>+	u64 pic_stream_buffer_size;</div><div class='add'>+	u32 src_idx; /* source frame buffer index */</div><div class='add'>+	struct enc_code_opt code_option;</div><div class='add'>+	u64 pts; /* presentation timestamp (PTS) of the input source */</div><div class='add'>+	bool src_end_flag;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_output_info {</div><div class='add'>+	u32 bitstream_buffer;</div><div class='add'>+	u32 bitstream_size; /* byte size of encoded bitstream */</div><div class='add'>+	u32 pic_type: 2; /* &lt;&lt;vpuapi_h_pic_type&gt;&gt; */</div><div class='add'>+	s32 recon_frame_index;</div><div class='add'>+	dma_addr_t rd_ptr;</div><div class='add'>+	dma_addr_t wr_ptr;</div><div class='add'>+	u32 enc_pic_byte; /* number of encoded picture bytes */</div><div class='add'>+	s32 enc_src_idx; /* source buffer index of the currently encoded picture */</div><div class='add'>+	u32 enc_vcl_nut;</div><div class='add'>+	u32 error_reason; /* error reason of the currently encoded picture */</div><div class='add'>+	u32 warn_info; /* warning information on the currently encoded picture */</div><div class='add'>+	unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/</div><div class='add'>+	u64 pts;</div><div class='add'>+	u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */</div><div class='add'>+	u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum enc_pic_code_option {</div><div class='add'>+	CODEOPT_ENC_HEADER_IMPLICIT = BIT(0),</div><div class='add'>+	CODEOPT_ENC_VCL = BIT(1), /* flag to encode VCL nal unit explicitly */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum gop_preset_idx {</div><div class='add'>+	PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */</div><div class='add'>+	PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */</div><div class='add'>+	PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */</div><div class='add'>+	PRESET_IDX_IBBB = 3, /* consecutive B, cyclic gopsize = 1 */</div><div class='add'>+	PRESET_IDX_IBPBP = 4, /* gopsize = 2 */</div><div class='add'>+	PRESET_IDX_IBBBP = 5, /* gopsize = 4 */</div><div class='add'>+	PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */</div><div class='add'>+	PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */</div><div class='add'>+	PRESET_IDX_RA_IB = 8, /* random access, cyclic gopsize = 8 */</div><div class='add'>+	PRESET_IDX_IPP_SINGLE = 9, /* consecutive P, cyclic gopsize = 1, with single ref */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct sec_axi_info {</div><div class='add'>+	u32 use_ip_enable;</div><div class='add'>+	u32 use_bit_enable;</div><div class='add'>+	u32 use_lf_row_enable: 1;</div><div class='add'>+	u32 use_enc_rdo_enable: 1;</div><div class='add'>+	u32 use_enc_lf_enable: 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dec_info {</div><div class='add'>+	struct dec_open_param open_param;</div><div class='add'>+	struct dec_initial_info initial_info;</div><div class='add'>+	struct dec_initial_info new_seq_info; /* temporal new sequence information */</div><div class='add'>+	u32 stream_wr_ptr;</div><div class='add'>+	u32 stream_rd_ptr;</div><div class='add'>+	u32 frame_display_flag;</div><div class='add'>+	dma_addr_t stream_buf_start_addr;</div><div class='add'>+	dma_addr_t stream_buf_end_addr;</div><div class='add'>+	u32 stream_buf_size;</div><div class='add'>+	struct vpu_buf vb_mv[MAX_REG_FRAME];</div><div class='add'>+	struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME];</div><div class='add'>+	struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME];</div><div class='add'>+	unsigned int num_of_decoding_fbs: 7;</div><div class='add'>+	unsigned int num_of_display_fbs: 7;</div><div class='add'>+	unsigned int stride;</div><div class='add'>+	struct sec_axi_info sec_axi_info;</div><div class='add'>+	dma_addr_t user_data_buf_addr;</div><div class='add'>+	u32 user_data_enable;</div><div class='add'>+	u32 user_data_buf_size;</div><div class='add'>+	struct vpu_buf vb_work;</div><div class='add'>+	struct vpu_buf vb_task;</div><div class='add'>+	struct dec_output_info dec_out_info[WAVE5_MAX_FBS];</div><div class='add'>+	u32 seq_change_mask;</div><div class='add'>+	enum temporal_id_mode temp_id_select_mode;</div><div class='add'>+	u32 target_temp_id;</div><div class='add'>+	u32 target_spatial_id;</div><div class='add'>+	u32 instance_queue_count;</div><div class='add'>+	u32 report_queue_count;</div><div class='add'>+	u32 cycle_per_tick;</div><div class='add'>+	u32 product_code;</div><div class='add'>+	u32 vlc_buf_size;</div><div class='add'>+	u32 param_buf_size;</div><div class='add'>+	bool initial_info_obtained;</div><div class='add'>+	bool reorder_enable;</div><div class='add'>+	bool first_cycle_check;</div><div class='add'>+	u32 stream_endflag: 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct enc_info {</div><div class='add'>+	struct enc_open_param open_param;</div><div class='add'>+	struct enc_initial_info initial_info;</div><div class='add'>+	u32 stream_rd_ptr;</div><div class='add'>+	u32 stream_wr_ptr;</div><div class='add'>+	dma_addr_t stream_buf_start_addr;</div><div class='add'>+	dma_addr_t stream_buf_end_addr;</div><div class='add'>+	u32 stream_buf_size;</div><div class='add'>+	unsigned int num_frame_buffers;</div><div class='add'>+	unsigned int stride;</div><div class='add'>+	bool rotation_enable;</div><div class='add'>+	bool mirror_enable;</div><div class='add'>+	enum mirror_direction mirror_direction;</div><div class='add'>+	unsigned int rotation_angle;</div><div class='add'>+	bool initial_info_obtained;</div><div class='add'>+	struct sec_axi_info sec_axi_info;</div><div class='add'>+	bool line_buf_int_en;</div><div class='add'>+	struct vpu_buf vb_work;</div><div class='add'>+	struct vpu_buf vb_mv; /* col_mv buffer */</div><div class='add'>+	struct vpu_buf vb_fbc_y_tbl; /* FBC luma table buffer */</div><div class='add'>+	struct vpu_buf vb_fbc_c_tbl; /* FBC chroma table buffer */</div><div class='add'>+	struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */</div><div class='add'>+	struct vpu_buf vb_task;</div><div class='add'>+	u64 cur_pts; /* current timestamp in 90_k_hz */</div><div class='add'>+	u64 pts_map[32]; /* PTS mapped with source frame index */</div><div class='add'>+	u32 instance_queue_count;</div><div class='add'>+	u32 report_queue_count;</div><div class='add'>+	bool first_cycle_check;</div><div class='add'>+	u32 cycle_per_tick;</div><div class='add'>+	u32 product_code;</div><div class='add'>+	u32 vlc_buf_size;</div><div class='add'>+	u32 param_buf_size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_device {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct v4l2_device v4l2_dev;</div><div class='add'>+	struct v4l2_m2m_dev *v4l2_m2m_dec_dev;</div><div class='add'>+	struct v4l2_m2m_dev *v4l2_m2m_enc_dev;</div><div class='add'>+	struct list_head instances;</div><div class='add'>+	struct video_device *video_dev_dec;</div><div class='add'>+	struct video_device *video_dev_enc;</div><div class='add'>+	struct mutex dev_lock; /* lock for the src, dst v4l2 queues */</div><div class='add'>+	struct mutex hw_lock; /* lock hw configurations */</div><div class='add'>+	int irq;</div><div class='add'>+	enum product_id product;</div><div class='add'>+	struct vpu_attr attr;</div><div class='add'>+	struct vpu_buf common_mem;</div><div class='add'>+	u32 last_performance_cycles;</div><div class='add'>+	u32 sram_size;</div><div class='add'>+	struct gen_pool *sram_pool;</div><div class='add'>+	struct vpu_buf sram_buf;</div><div class='add'>+	void __iomem *vdb_register;</div><div class='add'>+	u32 product_code;</div><div class='add'>+	struct ida inst_ida;</div><div class='add'>+	struct clk_bulk_data *clks;</div><div class='add'>+	int num_clks;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_instance;</div><div class='add'>+</div><div class='add'>+struct vpu_instance_ops {</div><div class='add'>+	void (*finish_process)(struct vpu_instance *inst);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vpu_instance {</div><div class='add'>+	struct list_head list;</div><div class='add'>+	struct v4l2_fh v4l2_fh;</div><div class='add'>+	struct v4l2_m2m_dev *v4l2_m2m_dev;</div><div class='add'>+	struct v4l2_ctrl_handler v4l2_ctrl_hdl;</div><div class='add'>+	struct vpu_device *dev;</div><div class='add'>+	struct completion irq_done;</div><div class='add'>+</div><div class='add'>+	struct v4l2_pix_format_mplane src_fmt;</div><div class='add'>+	struct v4l2_pix_format_mplane dst_fmt;</div><div class='add'>+	enum v4l2_colorspace colorspace;</div><div class='add'>+	enum v4l2_xfer_func xfer_func;</div><div class='add'>+	enum v4l2_ycbcr_encoding ycbcr_enc;</div><div class='add'>+	enum v4l2_quantization quantization;</div><div class='add'>+</div><div class='add'>+	enum vpu_instance_state state;</div><div class='add'>+	enum vpu_instance_type type;</div><div class='add'>+	const struct vpu_instance_ops *ops;</div><div class='add'>+	spinlock_t state_spinlock; /* This protects the instance state */</div><div class='add'>+</div><div class='add'>+	enum wave_std std;</div><div class='add'>+	s32 id;</div><div class='add'>+	union {</div><div class='add'>+		struct enc_info enc_info;</div><div class='add'>+		struct dec_info dec_info;</div><div class='add'>+	} *codec_info;</div><div class='add'>+	struct frame_buffer frame_buf[MAX_REG_FRAME];</div><div class='add'>+	struct vpu_buf frame_vbuf[MAX_REG_FRAME];</div><div class='add'>+	u32 fbc_buf_count;</div><div class='add'>+	u32 queued_src_buf_num;</div><div class='add'>+	u32 queued_dst_buf_num;</div><div class='add'>+	struct list_head avail_src_bufs;</div><div class='add'>+	struct list_head avail_dst_bufs;</div><div class='add'>+	struct v4l2_rect conf_win;</div><div class='add'>+	u64 timestamp;</div><div class='add'>+	enum frame_buffer_format output_format;</div><div class='add'>+	bool cbcr_interleave;</div><div class='add'>+	bool nv21;</div><div class='add'>+	bool eos;</div><div class='add'>+	struct vpu_buf bitstream_vbuf;</div><div class='add'>+	dma_addr_t last_rd_ptr;</div><div class='add'>+	size_t remaining_consumed_bytes;</div><div class='add'>+	bool needs_reallocation;</div><div class='add'>+</div><div class='add'>+	unsigned int min_src_buf_count;</div><div class='add'>+	unsigned int rot_angle;</div><div class='add'>+	unsigned int mirror_direction;</div><div class='add'>+	unsigned int bit_depth;</div><div class='add'>+	unsigned int frame_rate;</div><div class='add'>+	unsigned int vbv_buf_size;</div><div class='add'>+	unsigned int rc_mode;</div><div class='add'>+	unsigned int rc_enable;</div><div class='add'>+	unsigned int bit_rate;</div><div class='add'>+	unsigned int encode_aud;</div><div class='add'>+	struct enc_wave_param enc_param;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data);</div><div class='add'>+u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr);</div><div class='add'>+int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);</div><div class='add'>+int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);</div><div class='add'>+int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,</div><div class='add'>+			     size_t size);</div><div class='add'>+int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,</div><div class='add'>+			   u8 *data, size_t len);</div><div class='add'>+int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);</div><div class='add'>+void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev);</div><div class='add'>+void wave5_vdi_free_sram(struct vpu_device *vpu_dev);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size);</div><div class='add'>+int wave5_vpu_flush_instance(struct vpu_instance *inst);</div><div class='add'>+int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id);</div><div class='add'>+int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param);</div><div class='add'>+int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res);</div><div class='add'>+int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst);</div><div class='add'>+int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info);</div><div class='add'>+int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,</div><div class='add'>+					   int num_of_display_fbs, int stride, int height);</div><div class='add'>+int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail);</div><div class='add'>+int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info);</div><div class='add'>+int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr);</div><div class='add'>+dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst);</div><div class='add'>+int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index);</div><div class='add'>+int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);</div><div class='add'>+int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,</div><div class='add'>+				       dma_addr_t *pwr_ptr, size_t *size);</div><div class='add'>+int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size);</div><div class='add'>+int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index);</div><div class='add'>+int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param);</div><div class='add'>+int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res);</div><div class='add'>+int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst);</div><div class='add'>+int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info);</div><div class='add'>+int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,</div><div class='add'>+					unsigned int stride, int height,</div><div class='add'>+					enum tiled_map_type map_type);</div><div class='add'>+int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param,</div><div class='add'>+				  u32 *fail_res);</div><div class='add'>+int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info);</div><div class='add'>+int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h<br/>new file mode 100644<br/>index 000000000000..d9751eedb0f9<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h</a></div><div class='hunk'>@@ -0,0 +1,77 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - product config definitions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _VPU_CONFIG_H_</div><div class='add'>+#define _VPU_CONFIG_H_</div><div class='add'>+</div><div class='add'>+#define WAVE517_CODE                    0x5170</div><div class='add'>+#define WAVE537_CODE                    0x5370</div><div class='add'>+#define WAVE511_CODE                    0x5110</div><div class='add'>+#define WAVE521_CODE                    0x5210</div><div class='add'>+#define WAVE521C_CODE                   0x521c</div><div class='add'>+#define WAVE521C_DUAL_CODE              0x521d  // wave521 dual core</div><div class='add'>+#define WAVE521E1_CODE                  0x5211</div><div class='add'>+</div><div class='add'>+#define PRODUCT_CODE_W_SERIES(x) ({					\</div><div class='add'>+		int c = x;						\</div><div class='add'>+		((c) == WAVE517_CODE ||	(c) == WAVE537_CODE ||		\</div><div class='add'>+		 (c) == WAVE511_CODE || (c) == WAVE521_CODE ||		\</div><div class='add'>+		 (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE ||	\</div><div class='add'>+		 (c) == WAVE521C_DUAL_CODE);				\</div><div class='add'>+})</div><div class='add'>+</div><div class='add'>+#define WAVE517_WORKBUF_SIZE            (2 * 1024 * 1024)</div><div class='add'>+#define WAVE521ENC_WORKBUF_SIZE         (128 * 1024)      //HEVC 128K, AVC 40K</div><div class='add'>+#define WAVE521DEC_WORKBUF_SIZE         (1784 * 1024)</div><div class='add'>+</div><div class='add'>+#define MAX_NUM_INSTANCE                32</div><div class='add'>+</div><div class='add'>+#define W5_MIN_ENC_PIC_WIDTH            256</div><div class='add'>+#define W5_MIN_ENC_PIC_HEIGHT           128</div><div class='add'>+#define W5_MAX_ENC_PIC_WIDTH            8192</div><div class='add'>+#define W5_MAX_ENC_PIC_HEIGHT           8192</div><div class='add'>+</div><div class='add'>+//  application specific configuration</div><div class='add'>+#define VPU_ENC_TIMEOUT                 60000</div><div class='add'>+#define VPU_DEC_TIMEOUT                 60000</div><div class='add'>+</div><div class='add'>+// for WAVE encoder</div><div class='add'>+#define USE_SRC_PRP_AXI         0</div><div class='add'>+#define USE_SRC_PRI_AXI         1</div><div class='add'>+#define DEFAULT_SRC_AXI         USE_SRC_PRP_AXI</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* VPU COMMON MEMORY                                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define VLC_BUF_NUM                     (2)</div><div class='add'>+</div><div class='add'>+#define COMMAND_QUEUE_DEPTH             (2)</div><div class='add'>+</div><div class='add'>+#define W5_REMAP_INDEX0                 0</div><div class='add'>+#define W5_REMAP_INDEX1                 1</div><div class='add'>+#define W5_REMAP_MAX_SIZE               (1024 * 1024)</div><div class='add'>+</div><div class='add'>+#define WAVE5_MAX_CODE_BUF_SIZE         (2 * 1024 * 1024)</div><div class='add'>+#define WAVE5_TEMPBUF_OFFSET            WAVE5_MAX_CODE_BUF_SIZE</div><div class='add'>+#define WAVE5_TEMPBUF_SIZE              (1024 * 1024)</div><div class='add'>+</div><div class='add'>+#define SIZE_COMMON                 (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)</div><div class='add'>+</div><div class='add'>+//=====4. VPU REPORT MEMORY  ======================//</div><div class='add'>+</div><div class='add'>+#define WAVE5_UPPER_PROC_AXI_ID     0x0</div><div class='add'>+</div><div class='add'>+#define WAVE5_PROC_AXI_ID           0x0</div><div class='add'>+#define WAVE5_PRP_AXI_ID            0x0</div><div class='add'>+#define WAVE5_FBD_Y_AXI_ID          0x0</div><div class='add'>+#define WAVE5_FBC_Y_AXI_ID          0x0</div><div class='add'>+#define WAVE5_FBD_C_AXI_ID          0x0</div><div class='add'>+#define WAVE5_FBC_C_AXI_ID          0x0</div><div class='add'>+#define WAVE5_SEC_AXI_ID            0x0</div><div class='add'>+#define WAVE5_PRI_AXI_ID            0x0</div><div class='add'>+</div><div class='add'>+#endif  /* _VPU_CONFIG_H_ */</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h b/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h<br/>new file mode 100644<br/>index 000000000000..905d5c34fd4e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5-vpuerror.h</a></div><div class='hunk'>@@ -0,0 +1,292 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - error values</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef ERROR_CODE_H_INCLUDED</div><div class='add'>+#define ERROR_CODE_H_INCLUDED</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * WAVE5</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 COMMON SYSTEM ERROR (FAIL_REASON)                              */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define WAVE5_SYSERR_QUEUEING_FAIL                                     0x00000001</div><div class='add'>+#define WAVE5_SYSERR_ACCESS_VIOLATION_HW                               0x00000040</div><div class='add'>+#define WAVE5_SYSERR_BUS_ERROR                                         0x00000200</div><div class='add'>+#define WAVE5_SYSERR_DOUBLE_FAULT                                      0x00000400</div><div class='add'>+#define WAVE5_SYSERR_RESULT_NOT_READY                                  0x00000800</div><div class='add'>+#define WAVE5_SYSERR_VPU_STILL_RUNNING                                 0x00001000</div><div class='add'>+#define WAVE5_SYSERR_UNKNOWN_CMD                                       0x00002000</div><div class='add'>+#define WAVE5_SYSERR_UNKNOWN_CODEC_STD                                 0x00004000</div><div class='add'>+#define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION                              0x00008000</div><div class='add'>+#define WAVE5_SYSERR_VLC_BUF_FULL                                      0x00010000</div><div class='add'>+#define WAVE5_SYSERR_WATCHDOG_TIMEOUT                                  0x00020000</div><div class='add'>+#define WAVE5_SYSERR_VCPU_TIMEOUT                                      0x00080000</div><div class='add'>+#define WAVE5_SYSERR_TEMP_SEC_BUF_OVERFLOW                             0x00200000</div><div class='add'>+#define WAVE5_SYSERR_NEED_MORE_TASK_BUF                                0x00400000</div><div class='add'>+#define WAVE5_SYSERR_PRESCAN_ERR                                       0x00800000</div><div class='add'>+#define WAVE5_SYSERR_ENC_GBIN_OVERCONSUME                              0x01000000</div><div class='add'>+#define WAVE5_SYSERR_ENC_MAX_ZERO_DETECT                               0x02000000</div><div class='add'>+#define WAVE5_SYSERR_ENC_LVL_FIRST_ERROR                               0x04000000</div><div class='add'>+#define WAVE5_SYSERR_ENC_EG_RANGE_OVER                                 0x08000000</div><div class='add'>+#define WAVE5_SYSERR_ENC_IRB_FRAME_DROP                                0x10000000</div><div class='add'>+#define WAVE5_SYSERR_INPLACE_V                                         0x20000000</div><div class='add'>+#define WAVE5_SYSERR_FATAL_VPU_HANGUP                                  0xf0000000</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 COMMAND QUEUE ERROR (FAIL_REASON)                              */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define WAVE5_CMDQ_ERR_NOT_QUEABLE_CMD                                 0x00000001</div><div class='add'>+#define WAVE5_CMDQ_ERR_SKIP_MODE_ENABLE                                0x00000002</div><div class='add'>+#define WAVE5_CMDQ_ERR_INST_FLUSHING                                   0x00000003</div><div class='add'>+#define WAVE5_CMDQ_ERR_INST_INACTIVE                                   0x00000004</div><div class='add'>+#define WAVE5_CMDQ_ERR_QUEUE_FAIL                                      0x00000005</div><div class='add'>+#define WAVE5_CMDQ_ERR_CMD_BUF_FULL                                    0x00000006</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 ERROR ON DECODER (ERR_INFO)                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+// HEVC</div><div class='add'>+#define HEVC_SPSERR_SEQ_PARAMETER_SET_ID                               0x00001000</div><div class='add'>+#define HEVC_SPSERR_CHROMA_FORMAT_IDC                                  0x00001001</div><div class='add'>+#define HEVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES                          0x00001002</div><div class='add'>+#define HEVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES                         0x00001003</div><div class='add'>+#define HEVC_SPSERR_CONF_WIN_LEFT_OFFSET                               0x00001004</div><div class='add'>+#define HEVC_SPSERR_CONF_WIN_RIGHT_OFFSET                              0x00001005</div><div class='add'>+#define HEVC_SPSERR_CONF_WIN_TOP_OFFSET                                0x00001006</div><div class='add'>+#define HEVC_SPSERR_CONF_WIN_BOTTOM_OFFSET                             0x00001007</div><div class='add'>+#define HEVC_SPSERR_BIT_DEPTH_LUMA_MINUS8                              0x00001008</div><div class='add'>+#define HEVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8                            0x00001009</div><div class='add'>+#define HEVC_SPSERR_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4                  0x0000100A</div><div class='add'>+#define HEVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING                          0x0000100B</div><div class='add'>+#define HEVC_SPSERR_SPS_MAX_NUM_REORDER_PICS                           0x0000100C</div><div class='add'>+#define HEVC_SPSERR_SPS_MAX_LATENCY_INCREASE                           0x0000100D</div><div class='add'>+#define HEVC_SPSERR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3             0x0000100E</div><div class='add'>+#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE           0x0000100F</div><div class='add'>+#define HEVC_SPSERR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2               0x00001010</div><div class='add'>+#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE             0x00001011</div><div class='add'>+#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER                0x00001012</div><div class='add'>+#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA                0x00001013</div><div class='add'>+#define HEVC_SPSERR_SCALING_LIST                                       0x00001014</div><div class='add'>+#define HEVC_SPSERR_LOG2_DIFF_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3    0x00001015</div><div class='add'>+#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE       0x00001016</div><div class='add'>+#define HEVC_SPSERR_NUM_SHORT_TERM_REF_PIC_SETS                        0x00001017</div><div class='add'>+#define HEVC_SPSERR_NUM_LONG_TERM_REF_PICS_SPS                         0x00001018</div><div class='add'>+#define HEVC_SPSERR_GBU_PARSING_ERROR                                  0x00001019</div><div class='add'>+#define HEVC_SPSERR_EXTENSION_FLAG                                     0x0000101A</div><div class='add'>+#define HEVC_SPSERR_VUI_ERROR                                          0x0000101B</div><div class='add'>+#define HEVC_SPSERR_ACTIVATE_SPS                                       0x0000101C</div><div class='add'>+#define HEVC_SPSERR_PROFILE_SPACE                                      0x0000101D</div><div class='add'>+#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID                           0x00002000</div><div class='add'>+#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID                           0x00002001</div><div class='add'>+#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1               0x00002002</div><div class='add'>+#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1               0x00002003</div><div class='add'>+#define HEVC_PPSERR_INIT_QP_MINUS26                                    0x00002004</div><div class='add'>+#define HEVC_PPSERR_DIFF_CU_QP_DELTA_DEPTH                             0x00002005</div><div class='add'>+#define HEVC_PPSERR_PPS_CB_QP_OFFSET                                   0x00002006</div><div class='add'>+#define HEVC_PPSERR_PPS_CR_QP_OFFSET                                   0x00002007</div><div class='add'>+#define HEVC_PPSERR_NUM_TILE_COLUMNS_MINUS1                            0x00002008</div><div class='add'>+#define HEVC_PPSERR_NUM_TILE_ROWS_MINUS1                               0x00002009</div><div class='add'>+#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1                                0x0000200A</div><div class='add'>+#define HEVC_PPSERR_ROW_HEIGHT_MINUS1                                  0x0000200B</div><div class='add'>+#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2                               0x0000200C</div><div class='add'>+#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2                                 0x0000200D</div><div class='add'>+#define HEVC_PPSERR_SCALING_LIST                                       0x0000200E</div><div class='add'>+#define HEVC_PPSERR_LOG2_PARALLEL_MERGE_LEVEL_MINUS2                   0x0000200F</div><div class='add'>+#define HEVC_PPSERR_NUM_TILE_COLUMNS_RANGE_OUT                         0x00002010</div><div class='add'>+#define HEVC_PPSERR_NUM_TILE_ROWS_RANGE_OUT                            0x00002011</div><div class='add'>+#define HEVC_PPSERR_MORE_RBSP_DATA_ERROR                               0x00002012</div><div class='add'>+#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT                 0x00002013</div><div class='add'>+#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT                 0x00002014</div><div class='add'>+#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT     0x00002015</div><div class='add'>+#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT     0x00002016</div><div class='add'>+#define HEVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT                         0x00002017</div><div class='add'>+#define HEVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT                         0x00002018</div><div class='add'>+#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1_RANGE_OUT                      0x00002019</div><div class='add'>+#define HEVC_PPSERR_ROW_HEIGHT_MINUS1_RANGE_OUT                        0x00002020</div><div class='add'>+#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2_RANGE_OUT                     0x00002021</div><div class='add'>+#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2_RANGE_OUT                       0x00002022</div><div class='add'>+#define HEVC_SHERR_SLICE_PIC_PARAMETER_SET_ID                          0x00003000</div><div class='add'>+#define HEVC_SHERR_ACTIVATE_PPS                                        0x00003001</div><div class='add'>+#define HEVC_SHERR_ACTIVATE_SPS                                        0x00003002</div><div class='add'>+#define HEVC_SHERR_SLICE_TYPE                                          0x00003003</div><div class='add'>+#define HEVC_SHERR_FIRST_SLICE_IS_DEPENDENT_SLICE                      0x00003004</div><div class='add'>+#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_SPS_FLAG                     0x00003005</div><div class='add'>+#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET                              0x00003006</div><div class='add'>+#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_IDX                          0x00003007</div><div class='add'>+#define HEVC_SHERR_NUM_LONG_TERM_SPS                                   0x00003008</div><div class='add'>+#define HEVC_SHERR_NUM_LONG_TERM_PICS                                  0x00003009</div><div class='add'>+#define HEVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE                          0x0000300A</div><div class='add'>+#define HEVC_SHERR_DELTA_POC_MSB_CYCLE_LT                              0x0000300B</div><div class='add'>+#define HEVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1                        0x0000300C</div><div class='add'>+#define HEVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1                        0x0000300D</div><div class='add'>+#define HEVC_SHERR_COLLOCATED_REF_IDX                                  0x0000300E</div><div class='add'>+#define HEVC_SHERR_PRED_WEIGHT_TABLE                                   0x0000300F</div><div class='add'>+#define HEVC_SHERR_FIVE_MINUS_MAX_NUM_MERGE_CAND                       0x00003010</div><div class='add'>+#define HEVC_SHERR_SLICE_QP_DELTA                                      0x00003011</div><div class='add'>+#define HEVC_SHERR_SLICE_QP_DELTA_IS_OUT_OF_RANGE                      0x00003012</div><div class='add'>+#define HEVC_SHERR_SLICE_CB_QP_OFFSET                                  0x00003013</div><div class='add'>+#define HEVC_SHERR_SLICE_CR_QP_OFFSET                                  0x00003014</div><div class='add'>+#define HEVC_SHERR_SLICE_BETA_OFFSET_DIV2                              0x00003015</div><div class='add'>+#define HEVC_SHERR_SLICE_TC_OFFSET_DIV2                                0x00003016</div><div class='add'>+#define HEVC_SHERR_NUM_ENTRY_POINT_OFFSETS                             0x00003017</div><div class='add'>+#define HEVC_SHERR_OFFSET_LEN_MINUS1                                   0x00003018</div><div class='add'>+#define HEVC_SHERR_SLICE_SEGMENT_HEADER_EXTENSION_LENGTH               0x00003019</div><div class='add'>+#define HEVC_SHERR_WRONG_POC_IN_STILL_PICTURE_PROFILE                  0x0000301A</div><div class='add'>+#define HEVC_SHERR_SLICE_TYPE_ERROR_IN_STILL_PICTURE_PROFILE           0x0000301B</div><div class='add'>+#define HEVC_SHERR_PPS_ID_NOT_EQUAL_PREV_VALUE                         0x0000301C</div><div class='add'>+#define HEVC_SPECERR_OVER_PICTURE_WIDTH_SIZE                           0x00004000</div><div class='add'>+#define HEVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE                          0x00004001</div><div class='add'>+#define HEVC_SPECERR_OVER_CHROMA_FORMAT                                0x00004002</div><div class='add'>+#define HEVC_SPECERR_OVER_BIT_DEPTH                                    0x00004003</div><div class='add'>+#define HEVC_SPECERR_OVER_BUFFER_OVER_FLOW                             0x00004004</div><div class='add'>+#define HEVC_SPECERR_OVER_WRONG_BUFFER_ACCESS                          0x00004005</div><div class='add'>+#define HEVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND                             0x00005000</div><div class='add'>+#define HEVC_ETCERR_DEC_PIC_VCL_NOT_FOUND                              0x00005001</div><div class='add'>+#define HEVC_ETCERR_NO_VALID_SLICE_IN_AU                               0x00005002</div><div class='add'>+#define HEVC_ETCERR_INPLACE_V                                          0x0000500F</div><div class='add'>+</div><div class='add'>+// AVC</div><div class='add'>+#define AVC_SPSERR_SEQ_PARAMETER_SET_ID                                0x00001000</div><div class='add'>+#define AVC_SPSERR_CHROMA_FORMAT_IDC                                   0x00001001</div><div class='add'>+#define AVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES                           0x00001002</div><div class='add'>+#define AVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES                          0x00001003</div><div class='add'>+#define AVC_SPSERR_CONF_WIN_LEFT_OFFSET                                0x00001004</div><div class='add'>+#define AVC_SPSERR_CONF_WIN_RIGHT_OFFSET                               0x00001005</div><div class='add'>+#define AVC_SPSERR_CONF_WIN_TOP_OFFSET                                 0x00001006</div><div class='add'>+#define AVC_SPSERR_CONF_WIN_BOTTOM_OFFSET                              0x00001007</div><div class='add'>+#define AVC_SPSERR_BIT_DEPTH_LUMA_MINUS8                               0x00001008</div><div class='add'>+#define AVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8                             0x00001009</div><div class='add'>+#define AVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING                           0x0000100B</div><div class='add'>+#define AVC_SPSERR_SPS_MAX_NUM_REORDER_PICS                            0x0000100C</div><div class='add'>+#define AVC_SPSERR_SCALING_LIST                                        0x00001014</div><div class='add'>+#define AVC_SPSERR_GBU_PARSING_ERROR                                   0x00001019</div><div class='add'>+#define AVC_SPSERR_VUI_ERROR                                           0x0000101B</div><div class='add'>+#define AVC_SPSERR_ACTIVATE_SPS                                        0x0000101C</div><div class='add'>+#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID                            0x00002000</div><div class='add'>+#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID                            0x00002001</div><div class='add'>+#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1                0x00002002</div><div class='add'>+#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1                0x00002003</div><div class='add'>+#define AVC_PPSERR_INIT_QP_MINUS26                                     0x00002004</div><div class='add'>+#define AVC_PPSERR_PPS_CB_QP_OFFSET                                    0x00002006</div><div class='add'>+#define AVC_PPSERR_PPS_CR_QP_OFFSET                                    0x00002007</div><div class='add'>+#define AVC_PPSERR_SCALING_LIST                                        0x0000200E</div><div class='add'>+#define AVC_PPSERR_MORE_RBSP_DATA_ERROR                                0x00002012</div><div class='add'>+#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT                  0x00002013</div><div class='add'>+#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT                  0x00002014</div><div class='add'>+#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT      0x00002015</div><div class='add'>+#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT      0x00002016</div><div class='add'>+#define AVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT                          0x00002017</div><div class='add'>+#define AVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT                          0x00002018</div><div class='add'>+#define AVC_SHERR_SLICE_PIC_PARAMETER_SET_ID                           0x00003000</div><div class='add'>+#define AVC_SHERR_ACTIVATE_PPS                                         0x00003001</div><div class='add'>+#define AVC_SHERR_ACTIVATE_SPS                                         0x00003002</div><div class='add'>+#define AVC_SHERR_SLICE_TYPE                                           0x00003003</div><div class='add'>+#define AVC_SHERR_FIRST_MB_IN_SLICE                                    0x00003004</div><div class='add'>+#define AVC_SHERR_RPLM                                                 0x00003006</div><div class='add'>+#define AVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE                           0x0000300A</div><div class='add'>+#define AVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1                         0x0000300C</div><div class='add'>+#define AVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1                         0x0000300D</div><div class='add'>+#define AVC_SHERR_PRED_WEIGHT_TABLE                                    0x0000300F</div><div class='add'>+#define AVC_SHERR_SLICE_QP_DELTA                                       0x00003011</div><div class='add'>+#define AVC_SHERR_SLICE_BETA_OFFSET_DIV2                               0x00003015</div><div class='add'>+#define AVC_SHERR_SLICE_TC_OFFSET_DIV2                                 0x00003016</div><div class='add'>+#define AVC_SHERR_DISABLE_DEBLOCK_FILTER_IDC                           0x00003017</div><div class='add'>+#define AVC_SPECERR_OVER_PICTURE_WIDTH_SIZE                            0x00004000</div><div class='add'>+#define AVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE                           0x00004001</div><div class='add'>+#define AVC_SPECERR_OVER_CHROMA_FORMAT                                 0x00004002</div><div class='add'>+#define AVC_SPECERR_OVER_BIT_DEPTH                                     0x00004003</div><div class='add'>+#define AVC_SPECERR_OVER_BUFFER_OVER_FLOW                              0x00004004</div><div class='add'>+#define AVC_SPECERR_OVER_WRONG_BUFFER_ACCESS                           0x00004005</div><div class='add'>+#define AVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND                              0x00005000</div><div class='add'>+#define AVC_ETCERR_DEC_PIC_VCL_NOT_FOUND                               0x00005001</div><div class='add'>+#define AVC_ETCERR_NO_VALID_SLICE_IN_AU                                0x00005002</div><div class='add'>+#define AVC_ETCERR_ASO                                                 0x00005004</div><div class='add'>+#define AVC_ETCERR_FMO                                                 0x00005005</div><div class='add'>+#define AVC_ETCERR_INPLACE_V                                           0x0000500F</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 WARNING ON DECODER (WARN_INFO)                                 */</div><div class='add'>+/************************************************************************/</div><div class='add'>+// HEVC</div><div class='add'>+#define HEVC_SPSWARN_MAX_SUB_LAYERS_MINUS1                             0x00000001</div><div class='add'>+#define HEVC_SPSWARN_GENERAL_RESERVED_ZERO_44BITS                      0x00000002</div><div class='add'>+#define HEVC_SPSWARN_RESERVED_ZERO_2BITS                               0x00000004</div><div class='add'>+#define HEVC_SPSWARN_SUB_LAYER_RESERVED_ZERO_44BITS                    0x00000008</div><div class='add'>+#define HEVC_SPSWARN_GENERAL_LEVEL_IDC                                 0x00000010</div><div class='add'>+#define HEVC_SPSWARN_SPS_MAX_DEC_PIC_BUFFERING_VALUE_OVER              0x00000020</div><div class='add'>+#define HEVC_SPSWARN_RBSP_TRAILING_BITS                                0x00000040</div><div class='add'>+#define HEVC_SPSWARN_ST_RPS_UE_ERROR                                   0x00000080</div><div class='add'>+#define HEVC_SPSWARN_EXTENSION_FLAG                                    0x01000000</div><div class='add'>+#define HEVC_SPSWARN_REPLACED_WITH_PREV_SPS                            0x02000000</div><div class='add'>+#define HEVC_PPSWARN_RBSP_TRAILING_BITS                                0x00000100</div><div class='add'>+#define HEVC_PPSWARN_REPLACED_WITH_PREV_PPS                            0x00000200</div><div class='add'>+#define HEVC_SHWARN_FIRST_SLICE_SEGMENT_IN_PIC_FLAG                    0x00001000</div><div class='add'>+#define HEVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG                       0x00002000</div><div class='add'>+#define HEVC_SHWARN_PIC_OUTPUT_FLAG                                    0x00004000</div><div class='add'>+#define HEVC_SHWARN_DUPLICATED_SLICE_SEGMENT                           0x00008000</div><div class='add'>+#define HEVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND                            0x00010000</div><div class='add'>+#define HEVC_ETCWARN_MISSING_REFERENCE_PICTURE                         0x00020000</div><div class='add'>+#define HEVC_ETCWARN_WRONG_TEMPORAL_ID                                 0x00040000</div><div class='add'>+#define HEVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED                       0x00080000</div><div class='add'>+#define HEVC_SPECWARN_OVER_PROFILE                                     0x00100000</div><div class='add'>+#define HEVC_SPECWARN_OVER_LEVEL                                       0x00200000</div><div class='add'>+#define HEVC_PRESWARN_PARSING_ERR                                      0x04000000</div><div class='add'>+#define HEVC_PRESWARN_MVD_OUT_OF_RANGE                                 0x08000000</div><div class='add'>+#define HEVC_PRESWARN_CU_QP_DELTA_VAL_OUT_OF_RANGE                     0x09000000</div><div class='add'>+#define HEVC_PRESWARN_COEFF_LEVEL_REMAINING_OUT_OF_RANGE               0x0A000000</div><div class='add'>+#define HEVC_PRESWARN_PCM_ERR                                          0x0B000000</div><div class='add'>+#define HEVC_PRESWARN_OVERCONSUME                                      0x0C000000</div><div class='add'>+#define HEVC_PRESWARN_END_OF_SUBSET_ONE_BIT_ERR                        0x10000000</div><div class='add'>+#define HEVC_PRESWARN_END_OF_SLICE_SEGMENT_FLAG                        0x20000000</div><div class='add'>+</div><div class='add'>+// AVC</div><div class='add'>+#define AVC_SPSWARN_RESERVED_ZERO_2BITS                                0x00000004</div><div class='add'>+#define AVC_SPSWARN_GENERAL_LEVEL_IDC                                  0x00000010</div><div class='add'>+#define AVC_SPSWARN_RBSP_TRAILING_BITS                                 0x00000040</div><div class='add'>+#define AVC_PPSWARN_RBSP_TRAILING_BITS                                 0x00000100</div><div class='add'>+#define AVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG                        0x00002000</div><div class='add'>+#define AVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND                             0x00010000</div><div class='add'>+#define AVC_ETCWARN_MISSING_REFERENCE_PICTURE                          0x00020000</div><div class='add'>+#define AVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED                        0x00080000</div><div class='add'>+#define AVC_SPECWARN_OVER_PROFILE                                      0x00100000</div><div class='add'>+#define AVC_SPECWARN_OVER_LEVEL                                        0x00200000</div><div class='add'>+#define AVC_PRESWARN_MVD_RANGE_OUT                                     0x00400000</div><div class='add'>+#define AVC_PRESWARN_MB_QPD_RANGE_OUT                                  0x00500000</div><div class='add'>+#define AVC_PRESWARN_COEFF_RANGE_OUT                                   0x00600000</div><div class='add'>+#define AVC_PRESWARN_MV_RANGE_OUT                                      0x00700000</div><div class='add'>+#define AVC_PRESWARN_MB_SKIP_RUN_RANGE_OUT                             0x00800000</div><div class='add'>+#define AVC_PRESWARN_MB_TYPE_RANGE_OUT                                 0x00900000</div><div class='add'>+#define AVC_PRESWARN_SUB_MB_TYPE_RANGE_OUT                             0x00A00000</div><div class='add'>+#define AVC_PRESWARN_CBP_RANGE_OUT                                     0x00B00000</div><div class='add'>+#define AVC_PRESWARN_INTRA_CHROMA_PRED_MODE_RANGE_OUT                  0x00C00000</div><div class='add'>+#define AVC_PRESWARN_REF_IDX_RANGE_OUT                                 0x00D00000</div><div class='add'>+#define AVC_PRESWARN_COEFF_TOKEN_RANGE_OUT                             0x00E00000</div><div class='add'>+#define AVC_PRESWARN_TOTAL_ZERO_RANGE_OUT                              0x00F00000</div><div class='add'>+#define AVC_PRESWARN_RUN_BEFORE_RANGE_OUT                              0x01000000</div><div class='add'>+#define AVC_PRESWARN_OVERCONSUME                                       0x01100000</div><div class='add'>+#define AVC_PRESWARN_MISSING_SLICE                                     0x01200000</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 ERROR ON ENCODER (ERR_INFO)                                    */</div><div class='add'>+/************************************************************************/</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 WARNING ON ENCODER (WARN_INFO)                                 */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define WAVE5_ETCWARN_FORCED_SPLIT_BY_CU8X8                            0x000000001</div><div class='add'>+</div><div class='add'>+/************************************************************************/</div><div class='add'>+/* WAVE5 debug info (PRI_REASON)                                        */</div><div class='add'>+/************************************************************************/</div><div class='add'>+#define WAVE5_DEC_VCORE_VCE_HANGUP                                     0x0001</div><div class='add'>+#define WAVE5_DEC_VCORE_UNDETECTED_SYNTAX_ERR                          0x0002</div><div class='add'>+#define WAVE5_DEC_VCORE_MIB_BUSY                                       0x0003</div><div class='add'>+#define WAVE5_DEC_VCORE_VLC_BUSY                                       0x0004</div><div class='add'>+</div><div class='add'>+#endif /* ERROR_CODE_H_INCLUDED */</div><div class='head'>diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h<br/>new file mode 100644<br/>index 000000000000..063028eccd3b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/chips-media/wave5/wave5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/chips-media/wave5/wave5.h</a></div><div class='hunk'>@@ -0,0 +1,114 @@</div><div class='add'>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */</div><div class='add'>+/*</div><div class='add'>+ * Wave5 series multi-standard codec IP - wave5 backend definitions</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2021-2023 CHIPS&amp;MEDIA INC</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef __WAVE5_FUNCTION_H__</div><div class='add'>+#define __WAVE5_FUNCTION_H__</div><div class='add'>+</div><div class='add'>+#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h)	(ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))</div><div class='add'>+#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h)	(ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Bitstream buffer option: Explicit End</div><div class='add'>+ * When set to 1 the VPU assumes that the bitstream has at least one frame and</div><div class='add'>+ * will read until the end of the bitstream buffer.</div><div class='add'>+ * When set to 0 the VPU will not read the last few bytes.</div><div class='add'>+ * This option can be set anytime but cannot be cleared during processing.</div><div class='add'>+ * It can be set to force finish decoding even though there is not enough</div><div class='add'>+ * bitstream data for a full frame.</div><div class='add'>+ */</div><div class='add'>+#define BSOPTION_ENABLE_EXPLICIT_END		BIT(0)</div><div class='add'>+#define BSOPTION_HIGHLIGHT_STREAM_END		BIT(1)</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Currently the driver only supports hardware with little endian but for source</div><div class='add'>+ * picture format, the bitstream and the report parameter the hardware works</div><div class='add'>+ * with the opposite endianness, thus hard-code big endian for the register</div><div class='add'>+ * writes</div><div class='add'>+ */</div><div class='add'>+#define PIC_SRC_ENDIANNESS_BIG_ENDIAN		0xf</div><div class='add'>+#define BITSTREAM_ENDIANNESS_BIG_ENDIAN		0xf</div><div class='add'>+#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN	0xf</div><div class='add'>+</div><div class='add'>+#define WTL_RIGHT_JUSTIFIED          0</div><div class='add'>+#define WTL_LEFT_JUSTIFIED           1</div><div class='add'>+#define WTL_PIXEL_8BIT               0</div><div class='add'>+#define WTL_PIXEL_16BIT              1</div><div class='add'>+#define WTL_PIXEL_32BIT              2</div><div class='add'>+</div><div class='add'>+/* Mirror &amp; rotation modes of the PRP (pre-processing) module */</div><div class='add'>+#define NONE_ROTATE		0x0</div><div class='add'>+#define ROT_CLOCKWISE_90	0x3</div><div class='add'>+#define ROT_CLOCKWISE_180	0x5</div><div class='add'>+#define ROT_CLOCKWISE_270	0x7</div><div class='add'>+#define MIR_HOR_FLIP		0x11</div><div class='add'>+#define MIR_VER_FLIP		0x9</div><div class='add'>+#define MIR_HOR_VER_FLIP	(MIR_HOR_FLIP | MIR_VER_FLIP)</div><div class='add'>+</div><div class='add'>+bool wave5_vpu_is_init(struct vpu_device *vpu_dev);</div><div class='add'>+</div><div class='add'>+unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,</div><div class='add'>+				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,</div><div class='add'>+				       unsigned int count);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_init_seq(struct vpu_instance *inst);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);</div><div class='add'>+</div><div class='add'>+int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);</div><div class='add'>+</div><div class='add'>+int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);</div><div class='add'>+</div><div class='add'>+dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);</div><div class='add'>+</div><div class='add'>+int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);</div><div class='add'>+</div><div class='add'>+/***&lt; WAVE5 encoder &gt;******/</div><div class='add'>+</div><div class='add'>+int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,</div><div class='add'>+				 struct enc_open_param *open_param);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_init_seq(struct vpu_instance *inst);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,</div><div class='add'>+				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,</div><div class='add'>+				       unsigned int count);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);</div><div class='add'>+</div><div class='add'>+int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);</div><div class='add'>+</div><div class='add'>+#endif /* __WAVE5_FUNCTION_H__ */</div><div class='head'>diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c<br/>index 7194f88edc0f..ac48658e2de4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c</a></div><div class='hunk'>@@ -598,12 +598,11 @@ static int mtk_jpeg_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)</div><div class='ctx'> 		goto end;</div><div class='ctx'> </div><div class='ctx'> 	vq = v4l2_m2m_get_vq(fh-&gt;m2m_ctx, buf-&gt;type);</div><div class='del'>-	if (buf-&gt;index &gt;= vq-&gt;num_buffers) {</div><div class='del'>-		dev_err(ctx-&gt;jpeg-&gt;dev, "buffer index out of range\n");</div><div class='add'>+	vb = vb2_get_buffer(vq, buf-&gt;index);</div><div class='add'>+	if (!vb) {</div><div class='add'>+		dev_err(ctx-&gt;jpeg-&gt;dev, "buffer not found\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	vb = vq-&gt;bufs[buf-&gt;index];</div><div class='ctx'> 	jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(vb);</div><div class='ctx'> 	jpeg_src_buf-&gt;bs_size = buf-&gt;m.planes[0].bytesused;</div><div class='ctx'> </div><div class='hunk'>@@ -1021,13 +1020,13 @@ static void mtk_jpeg_dec_device_run(void *priv)</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto dec_end;</div><div class='ctx'> </div><div class='del'>-	schedule_delayed_work(&amp;jpeg-&gt;job_timeout_work,</div><div class='del'>-			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));</div><div class='del'>-</div><div class='ctx'> 	mtk_jpeg_set_dec_src(ctx, &amp;src_buf-&gt;vb2_buf, &amp;bs);</div><div class='ctx'> 	if (mtk_jpeg_set_dec_dst(ctx, &amp;jpeg_src_buf-&gt;dec_param, &amp;dst_buf-&gt;vb2_buf, &amp;fb))</div><div class='ctx'> 		goto dec_end;</div><div class='ctx'> </div><div class='add'>+	schedule_delayed_work(&amp;jpeg-&gt;job_timeout_work,</div><div class='add'>+			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));</div><div class='add'>+</div><div class='ctx'> 	spin_lock_irqsave(&amp;jpeg-&gt;hw_lock, flags);</div><div class='ctx'> 	mtk_jpeg_dec_reset(jpeg-&gt;reg_base);</div><div class='ctx'> 	mtk_jpeg_dec_set_config(jpeg-&gt;reg_base,</div><div class='hunk'>@@ -1403,7 +1402,6 @@ static void mtk_jpeg_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_jpeg_dev *jpeg = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	cancel_delayed_work_sync(&amp;jpeg-&gt;job_timeout_work);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	video_unregister_device(jpeg-&gt;vdev);</div><div class='ctx'> 	v4l2_m2m_release(jpeg-&gt;m2m_dev);</div><div class='hunk'>@@ -1750,9 +1748,6 @@ retry_select:</div><div class='ctx'> 	v4l2_m2m_src_buf_remove(ctx-&gt;fh.m2m_ctx);</div><div class='ctx'> 	v4l2_m2m_dst_buf_remove(ctx-&gt;fh.m2m_ctx);</div><div class='ctx'> </div><div class='del'>-	schedule_delayed_work(&amp;comp_jpeg[hw_id]-&gt;job_timeout_work,</div><div class='del'>-			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));</div><div class='del'>-</div><div class='ctx'> 	mtk_jpeg_set_dec_src(ctx, &amp;src_buf-&gt;vb2_buf, &amp;bs);</div><div class='ctx'> 	if (mtk_jpeg_set_dec_dst(ctx,</div><div class='ctx'> 				 &amp;jpeg_src_buf-&gt;dec_param,</div><div class='hunk'>@@ -1762,6 +1757,9 @@ retry_select:</div><div class='ctx'> 		goto setdst_end;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	schedule_delayed_work(&amp;comp_jpeg[hw_id]-&gt;job_timeout_work,</div><div class='add'>+			      msecs_to_jiffies(MTK_JPEG_HW_TIMEOUT_MSEC));</div><div class='add'>+</div><div class='ctx'> 	spin_lock_irqsave(&amp;comp_jpeg[hw_id]-&gt;hw_lock, flags);</div><div class='ctx'> 	ctx-&gt;total_frame_num++;</div><div class='ctx'> 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]-&gt;reg_base);</div><div class='head'>diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c<br/>index cc44be10fdb7..94f4ed78523b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c</a></div><div class='hunk'>@@ -208,13 +208,17 @@ static int mdp_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_destroy_job_wq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_SCP);</div><div class='del'>-	if (WARN_ON(!mm_pdev)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not get scp device\n");</div><div class='del'>-		ret = -ENODEV;</div><div class='del'>-		goto err_destroy_clock_wq;</div><div class='add'>+	mdp-&gt;scp = scp_get(pdev);</div><div class='add'>+	if (!mdp-&gt;scp) {</div><div class='add'>+		mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_SCP);</div><div class='add'>+		if (WARN_ON(!mm_pdev)) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "Could not get scp device\n");</div><div class='add'>+			ret = -ENODEV;</div><div class='add'>+			goto err_destroy_clock_wq;</div><div class='add'>+		}</div><div class='add'>+		mdp-&gt;scp = platform_get_drvdata(mm_pdev);</div><div class='ctx'> 	}</div><div class='del'>-	mdp-&gt;scp = platform_get_drvdata(mm_pdev);</div><div class='add'>+</div><div class='ctx'> 	mdp-&gt;rproc_handle = scp_get_rproc(mdp-&gt;scp);</div><div class='ctx'> 	dev_dbg(&amp;pdev-&gt;dev, "MDP rproc_handle: %pK", mdp-&gt;rproc_handle);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/Kconfig b/drivers/media/platform/mediatek/vcodec/Kconfig<br/>index 74b00eb1bc97..bc8292232530 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/Kconfig</a></div><div class='hunk'>@@ -24,7 +24,6 @@ config VIDEO_MEDIATEK_VCODEC</div><div class='ctx'> 	select V4L2_H264</div><div class='ctx'> 	select V4L2_VP9</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	help</div><div class='ctx'> 	  Mediatek video codec driver provides HW capability to</div><div class='ctx'> 	  encode and decode in a range of video formats on MT8173</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c<br/>index 91ed576d6821..ba742f0e391d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c</a></div><div class='hunk'>@@ -208,36 +208,14 @@ static int vidioc_vdec_dqbuf(struct file *file, void *priv,</div><div class='ctx'> 	return v4l2_m2m_dqbuf(file, ctx-&gt;m2m_ctx, buf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mtk_vcodec_dec_get_chip_name(void *priv)</div><div class='del'>-{</div><div class='del'>-	struct mtk_vcodec_dec_ctx *ctx = fh_to_dec_ctx(priv);</div><div class='del'>-	struct device *dev = &amp;ctx-&gt;dev-&gt;plat_dev-&gt;dev;</div><div class='del'>-</div><div class='del'>-	if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8173-vcodec-dec"))</div><div class='del'>-		return 8173;</div><div class='del'>-	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8183-vcodec-dec"))</div><div class='del'>-		return 8183;</div><div class='del'>-	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8192-vcodec-dec"))</div><div class='del'>-		return 8192;</div><div class='del'>-	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8195-vcodec-dec"))</div><div class='del'>-		return 8195;</div><div class='del'>-	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8186-vcodec-dec"))</div><div class='del'>-		return 8186;</div><div class='del'>-	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8188-vcodec-dec"))</div><div class='del'>-		return 8188;</div><div class='del'>-	else</div><div class='del'>-		return 8173;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int vidioc_vdec_querycap(struct file *file, void *priv,</div><div class='ctx'> 				struct v4l2_capability *cap)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_vcodec_dec_ctx *ctx = fh_to_dec_ctx(priv);</div><div class='ctx'> 	struct device *dev = &amp;ctx-&gt;dev-&gt;plat_dev-&gt;dev;</div><div class='del'>-	int platform_name = mtk_vcodec_dec_get_chip_name(priv);</div><div class='ctx'> </div><div class='ctx'> 	strscpy(cap-&gt;driver, dev-&gt;driver-&gt;name, sizeof(cap-&gt;driver));</div><div class='del'>-	snprintf(cap-&gt;card, sizeof(cap-&gt;card), "MT%d video decoder", platform_name);</div><div class='add'>+	snprintf(cap-&gt;card, sizeof(cap-&gt;card), "MT%d video decoder", ctx-&gt;dev-&gt;chip_name);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c<br/>index 0a89ce452ac3..f47c98faf068 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c</a></div><div class='hunk'>@@ -326,6 +326,26 @@ static const struct v4l2_file_operations mtk_vcodec_fops = {</div><div class='ctx'> 	.mmap		= v4l2_m2m_fop_mmap,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_dev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;vdec_dev-&gt;plat_dev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8173-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8173;</div><div class='add'>+	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8183-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8183;</div><div class='add'>+	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8192-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8192;</div><div class='add'>+	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8195-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8195;</div><div class='add'>+	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8186-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8186;</div><div class='add'>+	else if (of_device_is_compatible(dev-&gt;of_node, "mediatek,mt8188-vcodec-dec"))</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_MT8188;</div><div class='add'>+	else</div><div class='add'>+		vdec_dev-&gt;chip_name = MTK_VDEC_INVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mtk_vcodec_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_vcodec_dec_dev *dev;</div><div class='hunk'>@@ -341,6 +361,12 @@ static int mtk_vcodec_probe(struct platform_device *pdev)</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;dev-&gt;ctx_list);</div><div class='ctx'> 	dev-&gt;plat_dev = pdev;</div><div class='ctx'> </div><div class='add'>+	mtk_vcodec_dec_get_chip_name(dev);</div><div class='add'>+	if (dev-&gt;chip_name == MTK_VDEC_INVAL) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to get decoder chip name");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	dev-&gt;vdec_pdata = of_device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> 	if (!of_property_read_u32(pdev-&gt;dev.of_node, "mediatek,vpu",</div><div class='ctx'> 				  &amp;rproc_phandle)) {</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h<br/>index 7e36b2c69b7d..849b89dd205c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h</a></div><div class='hunk'>@@ -18,6 +18,16 @@</div><div class='ctx'> #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) &gt;= MTK_VDEC_LAT_SINGLE_CORE)</div><div class='ctx'> #define IS_VDEC_INNER_RACING(capability) ((capability) &amp; MTK_VCODEC_INNER_RACING)</div><div class='ctx'> </div><div class='add'>+enum mtk_vcodec_dec_chip_name {</div><div class='add'>+	MTK_VDEC_INVAL = 0,</div><div class='add'>+	MTK_VDEC_MT8173 = 8173,</div><div class='add'>+	MTK_VDEC_MT8183 = 8183,</div><div class='add'>+	MTK_VDEC_MT8186 = 8186,</div><div class='add'>+	MTK_VDEC_MT8188 = 8188,</div><div class='add'>+	MTK_VDEC_MT8192 = 8192,</div><div class='add'>+	MTK_VDEC_MT8195 = 8195,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * enum mtk_vdec_format_types - Structure used to get supported</div><div class='ctx'>  *		  format types according to decoder capability</div><div class='hunk'>@@ -249,6 +259,8 @@ struct mtk_vcodec_dec_ctx {</div><div class='ctx'>  * @vdec_racing_info: record register value</div><div class='ctx'>  * @dec_racing_info_mutex: mutex lock used for inner racing mode</div><div class='ctx'>  * @dbgfs: debug log related information</div><div class='add'>+ *</div><div class='add'>+ * @chip_name: used to distinguish platforms and select the correct codec configuration values</div><div class='ctx'>  */</div><div class='ctx'> struct mtk_vcodec_dec_dev {</div><div class='ctx'> 	struct v4l2_device v4l2_dev;</div><div class='hunk'>@@ -289,6 +301,8 @@ struct mtk_vcodec_dec_dev {</div><div class='ctx'> 	/* Protects access to vdec_racing_info data */</div><div class='ctx'> 	struct mutex dec_racing_info_mutex;</div><div class='ctx'> 	struct mtk_vcodec_dbgfs dbgfs;</div><div class='add'>+</div><div class='add'>+	enum mtk_vcodec_dec_chip_name chip_name;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh)</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c<br/>index e29c9c58f3da..d54b3833790d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c</a></div><div class='hunk'>@@ -58,6 +58,15 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.cfg = {</div><div class='add'>+			.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL,</div><div class='add'>+			.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,</div><div class='add'>+			.def = V4L2_MPEG_VIDEO_H264_LEVEL_4_1,</div><div class='add'>+			.max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,</div><div class='add'>+		},</div><div class='add'>+		.codec_type = V4L2_PIX_FMT_H264_SLICE,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.cfg = {</div><div class='ctx'> 			.id = V4L2_CID_STATELESS_H264_DECODE_MODE,</div><div class='ctx'> 			.min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,</div><div class='ctx'> 			.def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,</div><div class='hunk'>@@ -100,7 +109,17 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = {</div><div class='ctx'> 			.id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,</div><div class='ctx'> 			.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,</div><div class='ctx'> 			.def = V4L2_MPEG_VIDEO_VP9_PROFILE_0,</div><div class='del'>-			.max = V4L2_MPEG_VIDEO_VP9_PROFILE_3,</div><div class='add'>+			.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,</div><div class='add'>+			.menu_skip_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_1),</div><div class='add'>+		},</div><div class='add'>+		.codec_type = V4L2_PIX_FMT_VP9_FRAME,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.cfg = {</div><div class='add'>+			.id = V4L2_CID_MPEG_VIDEO_VP9_LEVEL,</div><div class='add'>+			.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,</div><div class='add'>+			.def = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,</div><div class='add'>+			.max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,</div><div class='ctx'> 		},</div><div class='ctx'> 		.codec_type = V4L2_PIX_FMT_VP9_FRAME,</div><div class='ctx'> 	},</div><div class='hunk'>@@ -140,6 +159,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.cfg = {</div><div class='add'>+			.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,</div><div class='add'>+			.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,</div><div class='add'>+			.def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,</div><div class='add'>+			.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,</div><div class='add'>+		},</div><div class='add'>+		.codec_type = V4L2_PIX_FMT_HEVC_SLICE,</div><div class='add'>+	},</div><div class='add'>+</div><div class='add'>+	{</div><div class='add'>+		.cfg = {</div><div class='ctx'> 			.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,</div><div class='ctx'> 			.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,</div><div class='ctx'> 			.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,</div><div class='hunk'>@@ -519,6 +548,141 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {</div><div class='ctx'> 	.s_ctrl = mtk_vdec_s_ctrl,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					   struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8192:</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;</div><div class='add'>+		break;</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;</div><div class='add'>+		break;</div><div class='add'>+	case MTK_VDEC_MT8183:</div><div class='add'>+	case MTK_VDEC_MT8186:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					     struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					   struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;</div><div class='add'>+		break;</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					     struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					  struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8192:</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;</div><div class='add'>+		break;</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;</div><div class='add'>+		break;</div><div class='add'>+	case MTK_VDEC_MT8186:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					    struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (ctx-&gt;dev-&gt;chip_name) {</div><div class='add'>+	case MTK_VDEC_MT8188:</div><div class='add'>+	case MTK_VDEC_MT8195:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		cfg-&gt;max = V4L2_MPEG_VIDEO_VP9_PROFILE_1;</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,</div><div class='add'>+					  struct mtk_vcodec_dec_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	switch (cfg-&gt;id) {</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_LEVEL:</div><div class='add'>+		mtk_vcodec_dec_fill_h264_level(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg-&gt;max, cfg-&gt;def);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:</div><div class='add'>+		mtk_vcodec_dec_fill_h265_level(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg-&gt;max, cfg-&gt;def);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_VP9_LEVEL:</div><div class='add'>+		mtk_vcodec_dec_fill_vp9_level(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported level: %lld %lld", cfg-&gt;max, cfg-&gt;def);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_H264_PROFILE:</div><div class='add'>+		mtk_vcodec_dec_fill_h264_profile(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "h264 supported profile: %lld %lld", cfg-&gt;max,</div><div class='add'>+				  cfg-&gt;menu_skip_mask);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:</div><div class='add'>+		mtk_vcodec_dec_fill_h265_profile(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "h265 supported profile: %lld %lld", cfg-&gt;max,</div><div class='add'>+				  cfg-&gt;menu_skip_mask);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:</div><div class='add'>+		mtk_vcodec_dec_fill_vp9_profile(cfg, ctx);</div><div class='add'>+		mtk_v4l2_vdec_dbg(3, ctx, "vp9 supported profile: %lld %lld", cfg-&gt;max,</div><div class='add'>+				  cfg-&gt;menu_skip_mask);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	};</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -532,6 +696,8 @@ static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx)</div><div class='ctx'> 	for (i = 0; i &lt; NUM_CTRLS; i++) {</div><div class='ctx'> 		struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg;</div><div class='ctx'> 		cfg.ops = &amp;mtk_vcodec_dec_ctrl_ops;</div><div class='add'>+</div><div class='add'>+		mtk_vcodec_dec_reset_controls(&amp;cfg, ctx);</div><div class='ctx'> 		v4l2_ctrl_new_custom(&amp;ctx-&gt;ctrl_hdl, &amp;cfg, NULL);</div><div class='ctx'> 		if (ctx-&gt;ctrl_hdl.error) {</div><div class='ctx'> 			mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i,</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c<br/>index e393e3e668f8..69d37b93bd35 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c</a></div><div class='hunk'>@@ -1695,13 +1695,8 @@ static int vdec_vp9_slice_setup_core_buffer(struct vdec_vp9_slice_instance *inst</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* update internal buffer's width/height */</div><div class='del'>-	for (i = 0; i &lt; vq-&gt;num_buffers; i++) {</div><div class='del'>-		if (vb == vq-&gt;bufs[i]) {</div><div class='del'>-			instance-&gt;dpb[i].width = w;</div><div class='del'>-			instance-&gt;dpb[i].height = h;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	instance-&gt;dpb[vb-&gt;index].width = w;</div><div class='add'>+	instance-&gt;dpb[vb-&gt;index].height = h;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * get buffer's width/height from instance</div><div class='head'>diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c<br/>index eb381fa6e7d1..181884e798fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c</a></div><div class='hunk'>@@ -912,7 +912,7 @@ static int vb2ops_venc_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_start_stream:</div><div class='del'>-	for (i = 0; i &lt; q-&gt;num_buffers; ++i) {</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(q); ++i) {</div><div class='ctx'> 		struct vb2_buffer *buf = vb2_get_buffer(q, i);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='head'>diff --git a/drivers/media/platform/microchip/microchip-csi2dc.c b/drivers/media/platform/microchip/microchip-csi2dc.c<br/>index 988c1cc1d8b6..fee73260bb1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-csi2dc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/microchip/microchip-csi2dc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-csi2dc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-csi2dc.c</a></div><div class='hunk'>@@ -232,8 +232,8 @@ static int csi2dc_get_fmt(struct v4l2_subdev *csi2dc_sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *v4l2_try_fmt;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(csi2dc_sd, sd_state,</div><div class='del'>-							  format-&gt;pad);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    format-&gt;pad);</div><div class='ctx'> 		format-&gt;format = *v4l2_try_fmt;</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -281,13 +281,12 @@ static int csi2dc_set_fmt(struct v4l2_subdev *csi2dc_sd,</div><div class='ctx'> 	req_fmt-&gt;format.field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='ctx'> 	if (req_fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(csi2dc_sd, sd_state,</div><div class='del'>-							  req_fmt-&gt;pad);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    req_fmt-&gt;pad);</div><div class='ctx'> 		*v4l2_try_fmt = req_fmt-&gt;format;</div><div class='ctx'> 		/* Trying on the sink pad makes the source pad change too */</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(csi2dc_sd,</div><div class='del'>-							  sd_state,</div><div class='del'>-							  CSI2DC_PAD_SOURCE);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    CSI2DC_PAD_SOURCE);</div><div class='ctx'> 		*v4l2_try_fmt = req_fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 		/* if we are just trying, we are done */</div><div class='hunk'>@@ -436,11 +435,11 @@ static int csi2dc_s_stream(struct v4l2_subdev *csi2dc_sd, int enable)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int csi2dc_init_cfg(struct v4l2_subdev *csi2dc_sd,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int csi2dc_init_state(struct v4l2_subdev *csi2dc_sd,</div><div class='add'>+			     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *v4l2_try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(csi2dc_sd, sd_state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	v4l2_try_fmt-&gt;height = 480;</div><div class='ctx'> 	v4l2_try_fmt-&gt;width = 640;</div><div class='hunk'>@@ -462,7 +461,6 @@ static const struct v4l2_subdev_pad_ops csi2dc_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = csi2dc_enum_mbus_code,</div><div class='ctx'> 	.set_fmt = csi2dc_set_fmt,</div><div class='ctx'> 	.get_fmt = csi2dc_get_fmt,</div><div class='del'>-	.init_cfg = csi2dc_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops csi2dc_video_ops = {</div><div class='hunk'>@@ -474,6 +472,10 @@ static const struct v4l2_subdev_ops csi2dc_subdev_ops = {</div><div class='ctx'> 	.video = &amp;csi2dc_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops csi2dc_internal_ops = {</div><div class='add'>+	.init_state = csi2dc_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int csi2dc_async_bound(struct v4l2_async_notifier *notifier,</div><div class='ctx'> 			      struct v4l2_subdev *subdev,</div><div class='ctx'> 			      struct v4l2_async_connection *asd)</div><div class='hunk'>@@ -678,6 +680,7 @@ static int csi2dc_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(&amp;csi2dc-&gt;csi2dc_sd, &amp;csi2dc_subdev_ops);</div><div class='add'>+	csi2dc-&gt;csi2dc_sd.internal_ops = &amp;csi2dc_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	csi2dc-&gt;csi2dc_sd.owner = THIS_MODULE;</div><div class='ctx'> 	csi2dc-&gt;csi2dc_sd.dev = dev;</div><div class='head'>diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/drivers/media/platform/microchip/microchip-isc-base.c<br/>index 1f8528844497..f3a5cbacadbe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-isc-base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/microchip/microchip-isc-base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-isc-base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-isc-base.c</a></div><div class='hunk'>@@ -851,38 +851,6 @@ static int isc_try_configure_pipeline(struct isc_device *isc)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void isc_try_fse(struct isc_device *isc,</div><div class='del'>-			struct v4l2_subdev_state *sd_state)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_subdev_frame_size_enum fse = {</div><div class='del'>-		.which = V4L2_SUBDEV_FORMAT_TRY,</div><div class='del'>-	};</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * If we do not know yet which format the subdev is using, we cannot</div><div class='del'>-	 * do anything.</div><div class='del'>-	 */</div><div class='del'>-	if (!isc-&gt;config.sd_format)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	fse.code = isc-&gt;try_config.sd_format-&gt;mbus_code;</div><div class='del'>-</div><div class='del'>-	ret = v4l2_subdev_call(isc-&gt;current_subdev-&gt;sd, pad, enum_frame_size,</div><div class='del'>-			       sd_state, &amp;fse);</div><div class='del'>-	/*</div><div class='del'>-	 * Attempt to obtain format size from subdev. If not available,</div><div class='del'>-	 * just use the maximum ISC can receive.</div><div class='del'>-	 */</div><div class='del'>-	if (ret) {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.width = isc-&gt;max_width;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.height = isc-&gt;max_height;</div><div class='del'>-	} else {</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.width = fse.max_width;</div><div class='del'>-		sd_state-&gt;pads-&gt;try_crop.height = fse.max_height;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_pix_format *pixfmt = &amp;f-&gt;fmt.pix;</div><div class='hunk'>@@ -944,10 +912,6 @@ static int isc_validate(struct isc_device *isc)</div><div class='ctx'> 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,</div><div class='ctx'> 		.pad = isc-&gt;remote_pad,</div><div class='ctx'> 	};</div><div class='del'>-	struct v4l2_subdev_pad_config pad_cfg = {};</div><div class='del'>-	struct v4l2_subdev_state pad_state = {</div><div class='del'>-		.pads = &amp;pad_cfg,</div><div class='del'>-	};</div><div class='ctx'> </div><div class='ctx'> 	/* Get current format from subdev */</div><div class='ctx'> 	ret = v4l2_subdev_call(isc-&gt;current_subdev-&gt;sd, pad, get_fmt, NULL,</div><div class='hunk'>@@ -1008,9 +972,6 @@ static int isc_validate(struct isc_device *isc)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	/* Obtain frame sizes if possible to have crop requirements ready */</div><div class='del'>-	isc_try_fse(isc, &amp;pad_state);</div><div class='del'>-</div><div class='ctx'> 	/* Configure ISC pipeline for the config */</div><div class='ctx'> 	ret = isc_try_configure_pipeline(isc);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1819,7 +1780,7 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier)</div><div class='ctx'> 	q-&gt;mem_ops		= &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags	= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	q-&gt;lock			= &amp;isc-&gt;lock;</div><div class='del'>-	q-&gt;min_buffers_needed	= 1;</div><div class='add'>+	q-&gt;min_queued_buffers	= 1;</div><div class='ctx'> 	q-&gt;dev			= isc-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/microchip/microchip-isc-scaler.c b/drivers/media/platform/microchip/microchip-isc-scaler.c<br/>index 0f29a32d15ce..e83463543e21 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-isc-scaler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/microchip/microchip-isc-scaler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/microchip/microchip-isc-scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/microchip/microchip-isc-scaler.c</a></div><div class='hunk'>@@ -33,8 +33,8 @@ static int isc_scaler_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *v4l2_try_fmt;</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  format-&gt;pad);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    format-&gt;pad);</div><div class='ctx'> 		format-&gt;format = *v4l2_try_fmt;</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -74,12 +74,12 @@ static int isc_scaler_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	req_fmt-&gt;format.code = fmt-&gt;mbus_code;</div><div class='ctx'> </div><div class='ctx'> 	if (req_fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  req_fmt-&gt;pad);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    req_fmt-&gt;pad);</div><div class='ctx'> 		*v4l2_try_fmt = req_fmt-&gt;format;</div><div class='ctx'> 		/* Trying on the sink pad makes the source pad change too */</div><div class='del'>-		v4l2_try_fmt = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-							  ISC_SCALER_PAD_SOURCE);</div><div class='add'>+		v4l2_try_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    ISC_SCALER_PAD_SOURCE);</div><div class='ctx'> 		*v4l2_try_fmt = req_fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 		v4l_bound_align_image(&amp;v4l2_try_fmt-&gt;width,</div><div class='hunk'>@@ -145,17 +145,17 @@ static int isc_scaler_g_sel(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int isc_scaler_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			       struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int isc_scaler_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *v4l2_try_fmt =</div><div class='del'>-		v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	struct v4l2_rect *try_crop;</div><div class='ctx'> 	struct isc_device *isc = container_of(sd, struct isc_device, scaler_sd);</div><div class='ctx'> </div><div class='ctx'> 	*v4l2_try_fmt = isc-&gt;scaler_format[ISC_SCALER_PAD_SOURCE];</div><div class='ctx'> </div><div class='del'>-	try_crop = v4l2_subdev_get_try_crop(sd, sd_state, 0);</div><div class='add'>+	try_crop = v4l2_subdev_state_get_crop(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	try_crop-&gt;top = 0;</div><div class='ctx'> 	try_crop-&gt;left = 0;</div><div class='hunk'>@@ -170,7 +170,6 @@ static const struct v4l2_subdev_pad_ops isc_scaler_pad_ops = {</div><div class='ctx'> 	.set_fmt = isc_scaler_set_fmt,</div><div class='ctx'> 	.get_fmt = isc_scaler_get_fmt,</div><div class='ctx'> 	.get_selection = isc_scaler_g_sel,</div><div class='del'>-	.init_cfg = isc_scaler_init_cfg,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct media_entity_operations isc_scaler_entity_ops = {</div><div class='hunk'>@@ -181,11 +180,16 @@ static const struct v4l2_subdev_ops xisc_scaler_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;isc_scaler_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops isc_scaler_internal_ops = {</div><div class='add'>+	.init_state = isc_scaler_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int isc_scaler_init(struct isc_device *isc)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(&amp;isc-&gt;scaler_sd, &amp;xisc_scaler_subdev_ops);</div><div class='add'>+	isc-&gt;scaler_sd.internal_ops = &amp;isc_scaler_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	isc-&gt;scaler_sd.owner = THIS_MODULE;</div><div class='ctx'> 	isc-&gt;scaler_sd.dev = isc-&gt;dev;</div><div class='head'>diff --git a/drivers/media/platform/nuvoton/npcm-video.c b/drivers/media/platform/nuvoton/npcm-video.c<br/>index b9e6782f59b4..a1fcb616b256 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nuvoton/npcm-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nuvoton/npcm-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nuvoton/npcm-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nuvoton/npcm-video.c</a></div><div class='hunk'>@@ -26,7 +26,6 @@</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/reset.h&gt;</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='del'>-#include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/string.h&gt;</div><div class='ctx'> #include &lt;linux/v4l2-controls.h&gt;</div><div class='ctx'> #include &lt;linux/videodev2.h&gt;</div><div class='hunk'>@@ -120,7 +119,7 @@ struct npcm_video {</div><div class='ctx'> 	struct mutex video_lock; /* v4l2 and videobuf2 lock */</div><div class='ctx'> </div><div class='ctx'> 	struct list_head buffers;</div><div class='del'>-	spinlock_t lock; /* buffer list lock */</div><div class='add'>+	struct mutex buffer_lock; /* buffer list lock */</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	unsigned int sequence;</div><div class='ctx'> </div><div class='hunk'>@@ -393,7 +392,7 @@ static void npcm_video_free_diff_table(struct npcm_video *video)</div><div class='ctx'> 	struct rect_list *tmp;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; video-&gt;queue.num_buffers; i++) {</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(&amp;video-&gt;queue); i++) {</div><div class='ctx'> 		head = &amp;video-&gt;list[i];</div><div class='ctx'> 		list_for_each_safe(pos, nx, head) {</div><div class='ctx'> 			tmp = list_entry(pos, struct rect_list, list);</div><div class='hunk'>@@ -782,7 +781,6 @@ static int npcm_video_start_frame(struct npcm_video *video)</div><div class='ctx'> {</div><div class='ctx'> 	struct npcm_video_buffer *buf;</div><div class='ctx'> 	struct regmap *vcd = video-&gt;vcd_regmap;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	unsigned int val;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -798,17 +796,17 @@ static int npcm_video_start_frame(struct npcm_video *video)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_lock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 	buf = list_first_entry_or_null(&amp;video-&gt;buffers,</div><div class='ctx'> 				       struct npcm_video_buffer, link);</div><div class='ctx'> 	if (!buf) {</div><div class='del'>-		spin_unlock_irqrestore(&amp;video-&gt;lock, flags);</div><div class='add'>+		mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 		dev_dbg(video-&gt;dev, "No empty buffers; skip capture frame\n");</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	set_bit(VIDEO_CAPTURING, &amp;video-&gt;flags);</div><div class='del'>-	spin_unlock_irqrestore(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> </div><div class='ctx'> 	npcm_video_vcd_state_machine_reset(video);</div><div class='ctx'> </div><div class='hunk'>@@ -834,14 +832,13 @@ static void npcm_video_bufs_done(struct npcm_video *video,</div><div class='ctx'> 				 enum vb2_buffer_state state)</div><div class='ctx'> {</div><div class='ctx'> 	struct npcm_video_buffer *buf;</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_lock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 	list_for_each_entry(buf, &amp;video-&gt;buffers, link)</div><div class='ctx'> 		vb2_buffer_done(&amp;buf-&gt;vb.vb2_buf, state);</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;video-&gt;buffers);</div><div class='del'>-	spin_unlock_irqrestore(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void npcm_video_get_diff_rect(struct npcm_video *video, unsigned int index)</div><div class='hunk'>@@ -1071,12 +1068,12 @@ static irqreturn_t npcm_video_irq(int irq, void *arg)</div><div class='ctx'> </div><div class='ctx'> 	if (status &amp; VCD_STAT_DONE) {</div><div class='ctx'> 		regmap_write(vcd, VCD_INTE, 0);</div><div class='del'>-		spin_lock(&amp;video-&gt;lock);</div><div class='add'>+		mutex_lock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 		clear_bit(VIDEO_CAPTURING, &amp;video-&gt;flags);</div><div class='ctx'> 		buf = list_first_entry_or_null(&amp;video-&gt;buffers,</div><div class='ctx'> 					       struct npcm_video_buffer, link);</div><div class='ctx'> 		if (!buf) {</div><div class='del'>-			spin_unlock(&amp;video-&gt;lock);</div><div class='add'>+			mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 			return IRQ_NONE;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1093,7 +1090,7 @@ static irqreturn_t npcm_video_irq(int irq, void *arg)</div><div class='ctx'> 			size = npcm_video_hextile(video, index, dma_addr, addr);</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='del'>-			spin_unlock(&amp;video-&gt;lock);</div><div class='add'>+			mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 			return IRQ_NONE;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1104,7 +1101,7 @@ static irqreturn_t npcm_video_irq(int irq, void *arg)</div><div class='ctx'> </div><div class='ctx'> 		vb2_buffer_done(&amp;buf-&gt;vb.vb2_buf, VB2_BUF_STATE_DONE);</div><div class='ctx'> 		list_del(&amp;buf-&gt;link);</div><div class='del'>-		spin_unlock(&amp;video-&gt;lock);</div><div class='add'>+		mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> </div><div class='ctx'> 		if (npcm_video_start_frame(video))</div><div class='ctx'> 			dev_err(video-&gt;dev, "Failed to capture next frame\n");</div><div class='hunk'>@@ -1508,13 +1505,12 @@ static void npcm_video_buf_queue(struct vb2_buffer *vb)</div><div class='ctx'> 	struct npcm_video *video = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='ctx'> 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='ctx'> 	struct npcm_video_buffer *nvb = to_npcm_video_buffer(vbuf);</div><div class='del'>-	unsigned long flags;</div><div class='ctx'> 	bool empty;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_lock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 	empty = list_empty(&amp;video-&gt;buffers);</div><div class='ctx'> 	list_add_tail(&amp;nvb-&gt;link, &amp;video-&gt;buffers);</div><div class='del'>-	spin_unlock_irqrestore(&amp;video-&gt;lock, flags);</div><div class='add'>+	mutex_unlock(&amp;video-&gt;buffer_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(VIDEO_STREAMING, &amp;video-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    !test_bit(VIDEO_CAPTURING, &amp;video-&gt;flags) &amp;&amp; empty) {</div><div class='hunk'>@@ -1616,7 +1612,7 @@ static int npcm_video_setup_video(struct npcm_video *video)</div><div class='ctx'> 	vbq-&gt;drv_priv = video;</div><div class='ctx'> 	vbq-&gt;buf_struct_size = sizeof(struct npcm_video_buffer);</div><div class='ctx'> 	vbq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	vbq-&gt;min_buffers_needed = 3;</div><div class='add'>+	vbq-&gt;min_queued_buffers = 3;</div><div class='ctx'> </div><div class='ctx'> 	rc = vb2_queue_init(vbq);</div><div class='ctx'> 	if (rc) {</div><div class='hunk'>@@ -1744,8 +1740,8 @@ static int npcm_video_probe(struct platform_device *pdev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	video-&gt;dev = &amp;pdev-&gt;dev;</div><div class='del'>-	spin_lock_init(&amp;video-&gt;lock);</div><div class='ctx'> 	mutex_init(&amp;video-&gt;video_lock);</div><div class='add'>+	mutex_init(&amp;video-&gt;buffer_lock);</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;video-&gt;buffers);</div><div class='ctx'> </div><div class='ctx'> 	regs = devm_platform_ioremap_resource(pdev, 0);</div><div class='head'>diff --git a/drivers/media/platform/nvidia/tegra-vde/Kconfig b/drivers/media/platform/nvidia/tegra-vde/Kconfig<br/>index f7454823bbbb..2fe13f39c95b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nvidia/tegra-vde/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nvidia/tegra-vde/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nvidia/tegra-vde/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nvidia/tegra-vde/Kconfig</a></div><div class='hunk'>@@ -6,7 +6,6 @@ config VIDEO_TEGRA_VDE</div><div class='ctx'> 	select DMA_SHARED_BUFFER</div><div class='ctx'> 	select IOMMU_IOVA</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	select SRAM</div><div class='ctx'> 	select VIDEOBUF2_DMA_CONTIG</div><div class='ctx'> 	select VIDEOBUF2_DMA_SG</div><div class='head'>diff --git a/drivers/media/platform/nvidia/tegra-vde/v4l2.c b/drivers/media/platform/nvidia/tegra-vde/v4l2.c<br/>index bd8c207d5b54..0f48ce6f243e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nvidia/tegra-vde/v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nvidia/tegra-vde/v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nvidia/tegra-vde/v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nvidia/tegra-vde/v4l2.c</a></div><div class='hunk'>@@ -813,7 +813,7 @@ static int tegra_open(struct file *file)</div><div class='ctx'> 	struct tegra_ctx *ctx;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	ctx = kzalloc(offsetof(struct tegra_ctx, ctrls[ARRAY_SIZE(ctrl_cfgs)]),</div><div class='add'>+	ctx = kzalloc(struct_size(ctx, ctrls, ARRAY_SIZE(ctrl_cfgs)),</div><div class='ctx'> 		      GFP_KERNEL);</div><div class='ctx'> 	if (!ctx)</div><div class='ctx'> 		return -ENOMEM;</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c<br/>index 6cb20b45e0a1..db8ff5f5c4d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx-mipi-csis.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx-mipi-csis.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx-mipi-csis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx-mipi-csis.c</a></div><div class='hunk'>@@ -954,7 +954,7 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SINK);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK);</div><div class='ctx'> 	csis_fmt = find_csis_format(format-&gt;code);</div><div class='ctx'> </div><div class='ctx'> 	ret = mipi_csis_calculate_params(csis, csis_fmt);</div><div class='hunk'>@@ -1002,7 +1002,7 @@ static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (code-&gt;index &gt; 0)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(sd, sd_state, code-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, code-&gt;pad);</div><div class='ctx'> 		code-&gt;code = fmt-&gt;code;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1069,7 +1069,7 @@ static int mipi_csis_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 			      &amp;sdformat-&gt;format.height, 1,</div><div class='ctx'> 			      CSIS_MAX_PIX_HEIGHT, 0, 0);</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	fmt-&gt;code = csis_fmt-&gt;code;</div><div class='ctx'> 	fmt-&gt;width = sdformat-&gt;format.width;</div><div class='hunk'>@@ -1083,7 +1083,7 @@ static int mipi_csis_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	sdformat-&gt;format = *fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format from sink to source. */</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, CSIS_PAD_SOURCE);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, CSIS_PAD_SOURCE);</div><div class='ctx'> 	*fmt = sdformat-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	/* The format on the source pad might change due to unpacking. */</div><div class='hunk'>@@ -1104,7 +1104,7 @@ static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, state, CSIS_PAD_SOURCE);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE);</div><div class='ctx'> 	csis_fmt = find_csis_format(fmt-&gt;code);</div><div class='ctx'> 	v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='hunk'>@@ -1122,8 +1122,8 @@ static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mipi_csis_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			      struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int mipi_csis_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = {</div><div class='ctx'> 		.pad = CSIS_PAD_SINK,</div><div class='hunk'>@@ -1163,7 +1163,6 @@ static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {</div><div class='del'>-	.init_cfg		= mipi_csis_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= mipi_csis_enum_mbus_code,</div><div class='ctx'> 	.get_fmt		= v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt		= mipi_csis_set_fmt,</div><div class='hunk'>@@ -1176,6 +1175,10 @@ static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;mipi_csis_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = {</div><div class='add'>+	.init_state		= mipi_csis_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Media entity operations</div><div class='ctx'>  */</div><div class='hunk'>@@ -1350,6 +1353,7 @@ static int mipi_csis_subdev_init(struct mipi_csis_device *csis)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;mipi_csis_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;mipi_csis_internal_ops;</div><div class='ctx'> 	sd-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	snprintf(sd-&gt;name, sizeof(sd-&gt;name), "csis-%s",</div><div class='ctx'> 		 dev_name(csis-&gt;dev));</div><div class='hunk'>@@ -1435,24 +1439,18 @@ static int mipi_csis_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* Reset PHY and enable the clocks. */</div><div class='ctx'> 	mipi_csis_phy_reset(csis);</div><div class='ctx'> </div><div class='del'>-	ret = mipi_csis_clk_enable(csis);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		dev_err(csis-&gt;dev, "failed to enable clocks: %d\n", ret);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Now that the hardware is initialized, request the interrupt. */</div><div class='ctx'> 	ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,</div><div class='ctx'> 			       dev_name(dev), csis);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Interrupt request failed\n");</div><div class='del'>-		goto err_disable_clock;</div><div class='add'>+		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize and register the subdev. */</div><div class='ctx'> 	ret = mipi_csis_subdev_init(csis);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='del'>-		goto err_disable_clock;</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	platform_set_drvdata(pdev, &amp;csis-&gt;sd);</div><div class='ctx'> </div><div class='hunk'>@@ -1486,8 +1484,6 @@ err_cleanup:</div><div class='ctx'> 	v4l2_async_nf_unregister(&amp;csis-&gt;notifier);</div><div class='ctx'> 	v4l2_async_nf_cleanup(&amp;csis-&gt;notifier);</div><div class='ctx'> 	v4l2_async_unregister_subdev(&amp;csis-&gt;sd);</div><div class='del'>-err_disable_clock:</div><div class='del'>-	mipi_csis_clk_disable(csis);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1502,9 +1498,10 @@ static void mipi_csis_remove(struct platform_device *pdev)</div><div class='ctx'> 	v4l2_async_nf_cleanup(&amp;csis-&gt;notifier);</div><div class='ctx'> 	v4l2_async_unregister_subdev(&amp;csis-&gt;sd);</div><div class='ctx'> </div><div class='add'>+	if (!pm_runtime_enabled(&amp;pdev-&gt;dev))</div><div class='add'>+		mipi_csis_runtime_suspend(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	mipi_csis_runtime_suspend(&amp;pdev-&gt;dev);</div><div class='del'>-	mipi_csis_clk_disable(csis);</div><div class='ctx'> 	v4l2_subdev_cleanup(&amp;csis-&gt;sd);</div><div class='ctx'> 	media_entity_cleanup(&amp;csis-&gt;sd.entity);</div><div class='ctx'> 	pm_runtime_set_suspended(&amp;pdev-&gt;dev);</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx7-media-csi.c b/drivers/media/platform/nxp/imx7-media-csi.c<br/>index 15049c6aab37..9566ff738818 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx7-media-csi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx7-media-csi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx7-media-csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx7-media-csi.c</a></div><div class='hunk'>@@ -3,31 +3,46 @@</div><div class='ctx'>  * V4L2 Capture CSI Subdev for Freescale i.MX6UL/L / i.MX7 SOC</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (c) 2019 Linaro Ltd</div><div class='del'>- *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/completion.h&gt;</div><div class='add'>+#include &lt;linux/container_of.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/jiffies.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/math.h&gt;</div><div class='del'>-#include &lt;linux/mfd/syscon.h&gt;</div><div class='ctx'> #include &lt;linux/minmax.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/of_graph.h&gt;</div><div class='del'>-#include &lt;linux/pinctrl/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='del'>-#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/timekeeping.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;media/media-device.h&gt;</div><div class='add'>+#include &lt;media/media-entity.h&gt;</div><div class='add'>+#include &lt;media/v4l2-async.h&gt;</div><div class='add'>+#include &lt;media/v4l2-common.h&gt;</div><div class='add'>+#include &lt;media/v4l2-dev.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='del'>-#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fh.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-ioctl.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-mc.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-core.h&gt;</div><div class='ctx'> #include &lt;media/videobuf2-dma-contig.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-v4l2.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define IMX7_CSI_PAD_SINK		0</div><div class='ctx'> #define IMX7_CSI_PAD_SRC		1</div><div class='hunk'>@@ -542,8 +557,8 @@ static void imx7_csi_configure(struct imx7_csi *csi,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		const struct v4l2_mbus_framefmt *sink_fmt;</div><div class='ctx'> </div><div class='del'>-		sink_fmt = v4l2_subdev_get_pad_format(&amp;csi-&gt;sd, sd_state,</div><div class='del'>-						      IMX7_CSI_PAD_SINK);</div><div class='add'>+		sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							IMX7_CSI_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 		cr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC</div><div class='ctx'> 		    | BIT_MCLKDIV(1) | BIT_MCLKEN;</div><div class='hunk'>@@ -1245,6 +1260,7 @@ static int imx7_csi_video_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 				      struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct imx7_csi *csi = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	struct v4l2_pix_format *pix = &amp;csi-&gt;vdev_fmt;</div><div class='ctx'> 	unsigned int count = *nbuffers;</div><div class='ctx'> </div><div class='hunk'>@@ -1254,14 +1270,14 @@ static int imx7_csi_video_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (*nplanes != 1 || sizes[0] &lt; pix-&gt;sizeimage)</div><div class='ctx'> 			return -EINVAL;</div><div class='del'>-		count += vq-&gt;num_buffers;</div><div class='add'>+		count += q_num_bufs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	count = min_t(__u32, IMX7_CSI_VIDEO_MEM_LIMIT / pix-&gt;sizeimage, count);</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes)</div><div class='del'>-		*nbuffers = (count &lt; vq-&gt;num_buffers) ? 0 :</div><div class='del'>-			count - vq-&gt;num_buffers;</div><div class='add'>+		*nbuffers = (count &lt; q_num_bufs) ? 0 :</div><div class='add'>+			count - q_num_bufs;</div><div class='ctx'> 	else</div><div class='ctx'> 		*nbuffers = count;</div><div class='ctx'> </div><div class='hunk'>@@ -1675,7 +1691,7 @@ static int imx7_csi_video_init(struct imx7_csi *csi)</div><div class='ctx'> 	vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	vq-&gt;lock = &amp;csi-&gt;vdev_mutex;</div><div class='del'>-	vq-&gt;min_buffers_needed = 2;</div><div class='add'>+	vq-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	vq-&gt;dev = csi-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(vq);</div><div class='hunk'>@@ -1728,8 +1744,8 @@ out_unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx7_csi_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			     struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx7_csi_init_state(struct v4l2_subdev *sd,</div><div class='add'>+			       struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	const struct imx7_csi_pixfmt *cc;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1738,7 +1754,7 @@ static int imx7_csi_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IMX7_CSI_PADS_NUM; i++) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *mf =</div><div class='del'>-			v4l2_subdev_get_pad_format(sd, sd_state, i);</div><div class='add'>+			v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> </div><div class='ctx'> 		mf-&gt;code = IMX7_CSI_DEF_MBUS_CODE;</div><div class='ctx'> 		mf-&gt;width = IMX7_CSI_DEF_PIX_WIDTH;</div><div class='hunk'>@@ -1762,7 +1778,7 @@ static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *in_fmt;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);</div><div class='add'>+	in_fmt = v4l2_subdev_state_get_format(sd_state, IMX7_CSI_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	switch (code-&gt;pad) {</div><div class='ctx'> 	case IMX7_CSI_PAD_SINK:</div><div class='hunk'>@@ -1841,7 +1857,7 @@ static void imx7_csi_try_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *in_fmt;</div><div class='ctx'> 	u32 code;</div><div class='ctx'> </div><div class='del'>-	in_fmt = v4l2_subdev_get_pad_format(sd, sd_state, IMX7_CSI_PAD_SINK);</div><div class='add'>+	in_fmt = v4l2_subdev_state_get_format(sd_state, IMX7_CSI_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	switch (sdformat-&gt;pad) {</div><div class='ctx'> 	case IMX7_CSI_PAD_SRC:</div><div class='hunk'>@@ -1891,7 +1907,7 @@ static int imx7_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	imx7_csi_try_fmt(sd, sd_state, sdformat, &amp;cc);</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	*fmt = sdformat-&gt;format;</div><div class='ctx'> </div><div class='hunk'>@@ -1902,8 +1918,8 @@ static int imx7_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		format.format = sdformat-&gt;format;</div><div class='ctx'> 		imx7_csi_try_fmt(sd, sd_state, &amp;format, &amp;outcc);</div><div class='ctx'> </div><div class='del'>-		outfmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-						    IMX7_CSI_PAD_SRC);</div><div class='add'>+		outfmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						      IMX7_CSI_PAD_SRC);</div><div class='ctx'> 		*outfmt = format.format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2005,7 +2021,6 @@ static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {</div><div class='del'>-	.init_cfg	= imx7_csi_init_cfg,</div><div class='ctx'> 	.enum_mbus_code	= imx7_csi_enum_mbus_code,</div><div class='ctx'> 	.get_fmt	= v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt	= imx7_csi_set_fmt,</div><div class='hunk'>@@ -2018,6 +2033,7 @@ static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {</div><div class='add'>+	.init_state	= imx7_csi_init_state,</div><div class='ctx'> 	.registered	= imx7_csi_registered,</div><div class='ctx'> 	.unregistered	= imx7_csi_unregistered,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c<br/>index 792f031e032a..575f17337388 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c</a></div><div class='hunk'>@@ -58,7 +58,7 @@ static int mxc_isi_crossbar_gasket_enable(struct mxc_isi_crossbar *xbar,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_state_get_stream_format(state, port, 0);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, port, 0);</div><div class='ctx'> 	if (!fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -176,8 +176,8 @@ mxc_isi_crossbar_xlate_streams(struct mxc_isi_crossbar *xbar,</div><div class='ctx'> 	return sd;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mxc_isi_crossbar_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				     struct v4l2_subdev_state *state)</div><div class='add'>+static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				       struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct mxc_isi_crossbar *xbar = to_isi_crossbar(sd);</div><div class='ctx'> 	struct v4l2_subdev_krouting routing = { };</div><div class='hunk'>@@ -281,8 +281,7 @@ static int mxc_isi_crossbar_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	 * Set the format on the sink stream and propagate it to the source</div><div class='ctx'> 	 * streams.</div><div class='ctx'> 	 */</div><div class='del'>-	sink_fmt = v4l2_subdev_state_get_stream_format(state, fmt-&gt;pad,</div><div class='del'>-						       fmt-&gt;stream);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(state, fmt-&gt;pad, fmt-&gt;stream);</div><div class='ctx'> 	if (!sink_fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -296,8 +295,9 @@ static int mxc_isi_crossbar_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		    route-&gt;sink_stream != fmt-&gt;stream)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		source_fmt = v4l2_subdev_state_get_stream_format(state, route-&gt;source_pad,</div><div class='del'>-								 route-&gt;source_stream);</div><div class='add'>+		source_fmt = v4l2_subdev_state_get_format(state,</div><div class='add'>+							  route-&gt;source_pad,</div><div class='add'>+							  route-&gt;source_stream);</div><div class='ctx'> 		if (!source_fmt)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -404,7 +404,6 @@ static int mxc_isi_crossbar_disable_streams(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mxc_isi_crossbar_subdev_pad_ops = {</div><div class='del'>-	.init_cfg = mxc_isi_crossbar_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mxc_isi_crossbar_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = mxc_isi_crossbar_set_fmt,</div><div class='hunk'>@@ -417,6 +416,10 @@ static const struct v4l2_subdev_ops mxc_isi_crossbar_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;mxc_isi_crossbar_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mxc_isi_crossbar_internal_ops = {</div><div class='add'>+	.init_state = mxc_isi_crossbar_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations mxc_isi_cross_entity_ops = {</div><div class='ctx'> 	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,</div><div class='ctx'> 	.link_validate	= v4l2_subdev_link_validate,</div><div class='hunk'>@@ -438,6 +441,7 @@ int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)</div><div class='ctx'> 	xbar-&gt;isi = isi;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;mxc_isi_crossbar_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;mxc_isi_crossbar_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;</div><div class='ctx'> 	strscpy(sd-&gt;name, "crossbar", sizeof(sd-&gt;name));</div><div class='ctx'> 	sd-&gt;dev = isi-&gt;dev;</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c<br/>index 6709ab7ea1f3..5e8a177da054 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c</a></div><div class='hunk'>@@ -22,10 +22,11 @@ static inline u32 mxc_isi_read(struct mxc_isi_pipe *pipe, u32 reg)</div><div class='ctx'> static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)</div><div class='ctx'> {</div><div class='ctx'> #define MXC_ISI_DEBUG_REG(name)		{ name, #name }</div><div class='del'>-	static const struct {</div><div class='add'>+	struct debug_regs {</div><div class='ctx'> 		u32 offset;</div><div class='ctx'> 		const char * const name;</div><div class='del'>-	} registers[] = {</div><div class='add'>+	};</div><div class='add'>+	static const struct debug_regs registers[] = {</div><div class='ctx'> 		MXC_ISI_DEBUG_REG(CHNL_CTRL),</div><div class='ctx'> 		MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL),</div><div class='ctx'> 		MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL),</div><div class='hunk'>@@ -67,6 +68,16 @@ static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)</div><div class='ctx'> 		MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG),</div><div class='ctx'> 		MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL),</div><div class='ctx'> 	};</div><div class='add'>+	/* These registers contain the upper 4 bits of 36-bit DMA addresses. */</div><div class='add'>+	static const struct debug_regs registers_36bit_dma[] = {</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_Y_BUF1_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_U_BUF1_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_V_BUF1_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_Y_BUF2_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_U_BUF2_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_V_BUF2_XTND_ADDR),</div><div class='add'>+		MXC_ISI_DEBUG_REG(CHNL_IN_BUF_XTND_ADDR),</div><div class='add'>+	};</div><div class='ctx'> </div><div class='ctx'> 	struct mxc_isi_pipe *pipe = m-&gt;private;</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -77,10 +88,20 @@ static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)</div><div class='ctx'> 	seq_printf(m, "--- ISI pipe %u registers ---\n", pipe-&gt;id);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(registers); ++i)</div><div class='del'>-		seq_printf(m, "%20s[0x%02x]: 0x%08x\n",</div><div class='add'>+		seq_printf(m, "%21s[0x%02x]: 0x%08x\n",</div><div class='ctx'> 			   registers[i].name, registers[i].offset,</div><div class='ctx'> 			   mxc_isi_read(pipe, registers[i].offset));</div><div class='ctx'> </div><div class='add'>+	if (pipe-&gt;isi-&gt;pdata-&gt;has_36bit_dma) {</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(registers_36bit_dma); ++i) {</div><div class='add'>+			const struct debug_regs *reg = &amp;registers_36bit_dma[i];</div><div class='add'>+</div><div class='add'>+			seq_printf(m, "%21s[0x%02x]: 0x%08x\n",</div><div class='add'>+				   reg-&gt;name, reg-&gt;offset,</div><div class='add'>+				   mxc_isi_read(pipe, reg-&gt;offset));</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_put(pipe-&gt;isi-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c<br/>index 65d20e9bae69..d76eb58deb09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-pipe.c</a></div><div class='hunk'>@@ -263,10 +263,10 @@ int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe)</div><div class='ctx'> 	/* Configure the pipeline. */</div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='del'>-	compose = v4l2_subdev_get_try_compose(sd, state, MXC_ISI_PIPE_PAD_SINK);</div><div class='del'>-	crop = *v4l2_subdev_get_try_crop(sd, state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(state, MXC_ISI_PIPE_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(state, MXC_ISI_PIPE_PAD_SINK);</div><div class='add'>+	crop = *v4l2_subdev_state_get_crop(state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	sink_info = mxc_isi_bus_format_by_code(sink_fmt-&gt;code,</div><div class='ctx'> 					       MXC_ISI_PIPE_PAD_SINK);</div><div class='hunk'>@@ -322,7 +322,7 @@ mxc_isi_pipe_get_pad_format(struct mxc_isi_pipe *pipe,</div><div class='ctx'> 			    struct v4l2_subdev_state *state,</div><div class='ctx'> 			    unsigned int pad)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_format(&amp;pipe-&gt;sd, state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct v4l2_rect *</div><div class='hunk'>@@ -330,7 +330,7 @@ mxc_isi_pipe_get_pad_crop(struct mxc_isi_pipe *pipe,</div><div class='ctx'> 			  struct v4l2_subdev_state *state,</div><div class='ctx'> 			  unsigned int pad)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_crop(&amp;pipe-&gt;sd, state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_crop(state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct v4l2_rect *</div><div class='hunk'>@@ -338,11 +338,11 @@ mxc_isi_pipe_get_pad_compose(struct mxc_isi_pipe *pipe,</div><div class='ctx'> 			     struct v4l2_subdev_state *state,</div><div class='ctx'> 			     unsigned int pad)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_compose(&amp;pipe-&gt;sd, state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_compose(state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mxc_isi_pipe_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				 struct v4l2_subdev_state *state)</div><div class='add'>+static int mxc_isi_pipe_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct mxc_isi_pipe *pipe = to_isi_pipe(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt_source;</div><div class='hunk'>@@ -682,7 +682,6 @@ static int mxc_isi_pipe_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops mxc_isi_pipe_subdev_pad_ops = {</div><div class='del'>-	.init_cfg = mxc_isi_pipe_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = mxc_isi_pipe_enum_mbus_code,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = mxc_isi_pipe_set_fmt,</div><div class='hunk'>@@ -694,6 +693,10 @@ static const struct v4l2_subdev_ops mxc_isi_pipe_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;mxc_isi_pipe_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops mxc_isi_pipe_internal_ops = {</div><div class='add'>+	.init_state = mxc_isi_pipe_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * IRQ handling</div><div class='ctx'>  */</div><div class='hunk'>@@ -767,6 +770,7 @@ int mxc_isi_pipe_init(struct mxc_isi_dev *isi, unsigned int id)</div><div class='ctx'> </div><div class='ctx'> 	sd = &amp;pipe-&gt;sd;</div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;mxc_isi_pipe_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;mxc_isi_pipe_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	snprintf(sd-&gt;name, sizeof(sd-&gt;name), "mxc_isi.%d", pipe-&gt;id);</div><div class='ctx'> 	sd-&gt;dev = isi-&gt;dev;</div><div class='hunk'>@@ -832,8 +836,8 @@ int mxc_isi_pipe_acquire(struct mxc_isi_pipe *pipe,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-	sink_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(state, MXC_ISI_PIPE_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='ctx'> 	v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='ctx'> 	sink_info = mxc_isi_bus_format_by_code(sink_fmt-&gt;code,</div><div class='head'>diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c<br/>index 10840c9a0912..4091f1c0e78b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8-isi/imx8-isi-video.c</a></div><div class='hunk'>@@ -713,7 +713,7 @@ static int mxc_isi_video_validate_format(struct mxc_isi_video *video)</div><div class='ctx'> </div><div class='ctx'> 	info = mxc_isi_format_by_fourcc(video-&gt;pix.pixelformat,</div><div class='ctx'> 					MXC_ISI_VIDEO_CAP);</div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, MXC_ISI_PIPE_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;code != info-&gt;mbus_code ||</div><div class='ctx'> 	    format-&gt;width != video-&gt;pix.width ||</div><div class='hunk'>@@ -1453,7 +1453,7 @@ int mxc_isi_video_register(struct mxc_isi_pipe *pipe,</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct mxc_isi_buffer);</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;lock = &amp;video-&gt;lock;</div><div class='ctx'> 	q-&gt;dev = pipe-&gt;isi-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c<br/>index ed048f73c982..ba2e81f24965 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8mq-mipi-csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/nxp/imx8mq-mipi-csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/nxp/imx8mq-mipi-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/nxp/imx8mq-mipi-csi2.c</a></div><div class='hunk'>@@ -296,7 +296,7 @@ static int imx8mq_mipi_csi_calc_hs_settle(struct csi_state *state,</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate the line rate from the pixel rate. */</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(&amp;state-&gt;sd, sd_state, MIPI_CSI2_PAD_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SINK);</div><div class='ctx'> 	csi2_fmt = find_csi2_format(fmt-&gt;code);</div><div class='ctx'> </div><div class='ctx'> 	link_freq = v4l2_get_link_freq(state-&gt;src_sd-&gt;ctrl_handler,</div><div class='hunk'>@@ -437,14 +437,15 @@ unlock:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int imx8mq_mipi_csi_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int imx8mq_mipi_csi_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt_sink;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt_source;</div><div class='ctx'> </div><div class='del'>-	fmt_sink = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SINK);</div><div class='del'>-	fmt_source = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);</div><div class='add'>+	fmt_sink = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SINK);</div><div class='add'>+	fmt_source = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						  MIPI_CSI2_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	fmt_sink-&gt;code = MEDIA_BUS_FMT_SGBRG10_1X10;</div><div class='ctx'> 	fmt_sink-&gt;width = MIPI_CSI2_DEF_PIX_WIDTH;</div><div class='hunk'>@@ -477,7 +478,7 @@ static int imx8mq_mipi_csi_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (code-&gt;index &gt; 0)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(sd, sd_state, code-&gt;pad);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(sd_state, code-&gt;pad);</div><div class='ctx'> 		code-&gt;code = fmt-&gt;code;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -514,7 +515,7 @@ static int imx8mq_mipi_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (!csi2_fmt)</div><div class='ctx'> 		csi2_fmt = &amp;imx8mq_mipi_csi_formats[0];</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	fmt-&gt;code = csi2_fmt-&gt;code;</div><div class='ctx'> 	fmt-&gt;width = sdformat-&gt;format.width;</div><div class='hunk'>@@ -523,7 +524,7 @@ static int imx8mq_mipi_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	sdformat-&gt;format = *fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format from sink to source. */</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, sd_state, MIPI_CSI2_PAD_SOURCE);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, MIPI_CSI2_PAD_SOURCE);</div><div class='ctx'> 	*fmt = sdformat-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -534,7 +535,6 @@ static const struct v4l2_subdev_video_ops imx8mq_mipi_csi_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops imx8mq_mipi_csi_pad_ops = {</div><div class='del'>-	.init_cfg		= imx8mq_mipi_csi_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= imx8mq_mipi_csi_enum_mbus_code,</div><div class='ctx'> 	.get_fmt		= v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt		= imx8mq_mipi_csi_set_fmt,</div><div class='hunk'>@@ -545,6 +545,10 @@ static const struct v4l2_subdev_ops imx8mq_mipi_csi_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;imx8mq_mipi_csi_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops imx8mq_mipi_csi_internal_ops = {</div><div class='add'>+	.init_state		= imx8mq_mipi_csi_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Media entity operations</div><div class='ctx'>  */</div><div class='hunk'>@@ -759,6 +763,7 @@ static int imx8mq_mipi_csi_subdev_init(struct csi_state *state)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;imx8mq_mipi_csi_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;imx8mq_mipi_csi_internal_ops;</div><div class='ctx'> 	sd-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	snprintf(sd-&gt;name, sizeof(sd-&gt;name), "%s %s",</div><div class='ctx'> 		 MIPI_CSI2_SUBDEV_NAME, dev_name(state-&gt;dev));</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c<br/>index 05ff5fa8095a..b11de4797cca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid-gen2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-csid-gen2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid-gen2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid-gen2.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'>  * interface support. As a result of that it has an</div><div class='ctx'>  * alternate register layout.</div><div class='ctx'>  */</div><div class='del'>-#define IS_LITE		(csid-&gt;id &gt;= 2 ? 1 : 0)</div><div class='ctx'> </div><div class='ctx'> #define CSID_HW_VERSION		0x0</div><div class='ctx'> #define		HW_VERSION_STEPPING	0</div><div class='hunk'>@@ -35,13 +34,13 @@</div><div class='ctx'> #define	CSID_CSI2_RX_IRQ_MASK	0x24</div><div class='ctx'> #define CSID_CSI2_RX_IRQ_CLEAR	0x28</div><div class='ctx'> </div><div class='del'>-#define CSID_CSI2_RDIN_IRQ_STATUS(rdi)		((IS_LITE ? 0x30 : 0x40) \</div><div class='add'>+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi)		((csid_is_lite(csid) ? 0x30 : 0x40) \</div><div class='ctx'> 						 + 0x10 * (rdi))</div><div class='del'>-#define CSID_CSI2_RDIN_IRQ_MASK(rdi)		((IS_LITE ? 0x34 : 0x44) \</div><div class='add'>+#define CSID_CSI2_RDIN_IRQ_MASK(rdi)		((csid_is_lite(csid) ? 0x34 : 0x44) \</div><div class='ctx'> 						 + 0x10 * (rdi))</div><div class='del'>-#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi)		((IS_LITE ? 0x38 : 0x48) \</div><div class='add'>+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi)		((csid_is_lite(csid) ? 0x38 : 0x48) \</div><div class='ctx'> 						 + 0x10 * (rdi))</div><div class='del'>-#define CSID_CSI2_RDIN_IRQ_SET(rdi)		((IS_LITE ? 0x3C : 0x4C) \</div><div class='add'>+#define CSID_CSI2_RDIN_IRQ_SET(rdi)		((csid_is_lite(csid) ? 0x3C : 0x4C) \</div><div class='ctx'> 						 + 0x10 * (rdi))</div><div class='ctx'> </div><div class='ctx'> #define CSID_TOP_IRQ_STATUS	0x70</div><div class='hunk'>@@ -73,7 +72,7 @@</div><div class='ctx'> #define			CGC_MODE_DYNAMIC_GATING		0</div><div class='ctx'> #define			CGC_MODE_ALWAYS_ON		1</div><div class='ctx'> </div><div class='del'>-#define CSID_RDI_CFG0(rdi)			((IS_LITE ? 0x200 : 0x300) \</div><div class='add'>+#define CSID_RDI_CFG0(rdi)			((csid_is_lite(csid) ? 0x200 : 0x300) \</div><div class='ctx'> 						 + 0x100 * (rdi))</div><div class='ctx'> #define		RDI_CFG0_BYTE_CNTR_EN		0</div><div class='ctx'> #define		RDI_CFG0_FORMAT_MEASURE_EN	1</div><div class='hunk'>@@ -98,32 +97,32 @@</div><div class='ctx'> #define		RDI_CFG0_PACKING_FORMAT		30</div><div class='ctx'> #define		RDI_CFG0_ENABLE			31</div><div class='ctx'> </div><div class='del'>-#define CSID_RDI_CFG1(rdi)			((IS_LITE ? 0x204 : 0x304)\</div><div class='add'>+#define CSID_RDI_CFG1(rdi)			((csid_is_lite(csid) ? 0x204 : 0x304)\</div><div class='ctx'> 						+ 0x100 * (rdi))</div><div class='ctx'> #define		RDI_CFG1_TIMESTAMP_STB_SEL	0</div><div class='ctx'> </div><div class='del'>-#define CSID_RDI_CTRL(rdi)			((IS_LITE ? 0x208 : 0x308)\</div><div class='add'>+#define CSID_RDI_CTRL(rdi)			((csid_is_lite(csid) ? 0x208 : 0x308)\</div><div class='ctx'> 						+ 0x100 * (rdi))</div><div class='ctx'> #define		RDI_CTRL_HALT_CMD		0</div><div class='ctx'> #define			HALT_CMD_HALT_AT_FRAME_BOUNDARY		0</div><div class='ctx'> #define			HALT_CMD_RESUME_AT_FRAME_BOUNDARY	1</div><div class='ctx'> #define		RDI_CTRL_HALT_MODE		2</div><div class='ctx'> </div><div class='del'>-#define CSID_RDI_FRM_DROP_PATTERN(rdi)			((IS_LITE ? 0x20C : 0x30C)\</div><div class='add'>+#define CSID_RDI_FRM_DROP_PATTERN(rdi)			((csid_is_lite(csid) ? 0x20C : 0x30C)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_FRM_DROP_PERIOD(rdi)			((IS_LITE ? 0x210 : 0x310)\</div><div class='add'>+#define CSID_RDI_FRM_DROP_PERIOD(rdi)			((csid_is_lite(csid) ? 0x210 : 0x310)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi)		((IS_LITE ? 0x214 : 0x314)\</div><div class='add'>+#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi)		((csid_is_lite(csid) ? 0x214 : 0x314)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi)		((IS_LITE ? 0x218 : 0x318)\</div><div class='add'>+#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi)		((csid_is_lite(csid) ? 0x218 : 0x318)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi)		((IS_LITE ? 0x224 : 0x324)\</div><div class='add'>+#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi)		((csid_is_lite(csid) ? 0x224 : 0x324)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi)		((IS_LITE ? 0x228 : 0x328)\</div><div class='add'>+#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi)		((csid_is_lite(csid) ? 0x228 : 0x328)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi)		((IS_LITE ? 0x22C : 0x32C)\</div><div class='add'>+#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi)		((csid_is_lite(csid) ? 0x22C : 0x32C)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='del'>-#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi)		((IS_LITE ? 0x230 : 0x330)\</div><div class='add'>+#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi)		((csid_is_lite(csid) ? 0x230 : 0x330)\</div><div class='ctx'> 							+ 0x100 * (rdi))</div><div class='ctx'> </div><div class='ctx'> #define CSID_TPG_CTRL		0x600</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c<br/>index 95873f988f7e..eb27d69e89a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-csid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid.c</a></div><div class='hunk'>@@ -263,7 +263,7 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> /*</div><div class='ctx'>  * __csid_get_format - Get pointer to format structure</div><div class='ctx'>  * @csid: CSID device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad from which format is requested</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='hunk'>@@ -276,8 +276,7 @@ __csid_get_format(struct csid_device *csid,</div><div class='ctx'> 		  enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;csid-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;csid-&gt;fmt[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -285,7 +284,7 @@ __csid_get_format(struct csid_device *csid,</div><div class='ctx'> /*</div><div class='ctx'>  * csid_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @csid: CSID device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad on which format is requested</div><div class='ctx'>  * @fmt: pointer to v4l2 format structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='hunk'>@@ -353,7 +352,7 @@ static void csid_try_format(struct csid_device *csid,</div><div class='ctx'> /*</div><div class='ctx'>  * csid_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd: CSID V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -394,7 +393,7 @@ static int csid_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csid_enum_frame_size - Handle frame size enumeration</div><div class='ctx'>  * @sd: CSID V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fse: pointer to v4l2_subdev_frame_size_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -431,7 +430,7 @@ static int csid_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csid_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd: CSID V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -455,7 +454,7 @@ static int csid_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csid_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd: CSID V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -897,3 +896,8 @@ void msm_csid_unregister_entity(struct csid_device *csid)</div><div class='ctx'> 	media_entity_cleanup(&amp;csid-&gt;subdev.entity);</div><div class='ctx'> 	v4l2_ctrl_handler_free(&amp;csid-&gt;ctrls);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+inline bool csid_is_lite(struct csid_device *csid)</div><div class='add'>+{</div><div class='add'>+	return csid-&gt;camss-&gt;res-&gt;csid_res[csid-&gt;id].is_lite;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h<br/>index 30d94eb2eb04..fddccb69da13 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-csid.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csid.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csid.h</a></div><div class='hunk'>@@ -215,5 +215,12 @@ extern const struct csid_hw_ops csid_ops_4_1;</div><div class='ctx'> extern const struct csid_hw_ops csid_ops_4_7;</div><div class='ctx'> extern const struct csid_hw_ops csid_ops_gen2;</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * csid_is_lite - Check if CSID is CSID lite.</div><div class='add'>+ * @csid: CSID Device</div><div class='add'>+ *</div><div class='add'>+ * Return whether CSID is CSID lite</div><div class='add'>+ */</div><div class='add'>+bool csid_is_lite(struct csid_device *csid);</div><div class='ctx'> </div><div class='ctx'> #endif /* QC_MSM_CAMSS_CSID_H */</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c<br/>index edd573606a6a..264c99efeae8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csiphy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-csiphy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-csiphy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-csiphy.c</a></div><div class='hunk'>@@ -312,7 +312,7 @@ static int csiphy_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> /*</div><div class='ctx'>  * __csiphy_get_format - Get pointer to format structure</div><div class='ctx'>  * @csiphy: CSIPHY device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad from which format is requested</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='hunk'>@@ -325,8 +325,7 @@ __csiphy_get_format(struct csiphy_device *csiphy,</div><div class='ctx'> 		    enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;csiphy-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;csiphy-&gt;fmt[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -334,7 +333,7 @@ __csiphy_get_format(struct csiphy_device *csiphy,</div><div class='ctx'> /*</div><div class='ctx'>  * csiphy_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @csiphy: CSIPHY device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad on which format is requested</div><div class='ctx'>  * @fmt: pointer to v4l2 format structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='hunk'>@@ -381,7 +380,7 @@ static void csiphy_try_format(struct csiphy_device *csiphy,</div><div class='ctx'> /*</div><div class='ctx'>  * csiphy_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd: CSIPHY V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -414,7 +413,7 @@ static int csiphy_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csiphy_enum_frame_size - Handle frame size enumeration</div><div class='ctx'>  * @sd: CSIPHY V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fse: pointer to v4l2_subdev_frame_size_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -451,7 +450,7 @@ static int csiphy_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csiphy_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd: CSIPHY V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -475,7 +474,7 @@ static int csiphy_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csiphy_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd: CSIPHY V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-ispif.c b/drivers/media/platform/qcom/camss/camss-ispif.c<br/>index be9d2f0a10c1..a12dcc7ff438 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-ispif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-ispif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-ispif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-ispif.c</a></div><div class='hunk'>@@ -270,7 +270,7 @@ static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)</div><div class='ctx'> 	unsigned long time;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	if (vfe_id &gt; camss-&gt;res-&gt;vfe_num - 1) {</div><div class='add'>+	if (vfe_id &gt;= camss-&gt;res-&gt;vfe_num) {</div><div class='ctx'> 		dev_err(camss-&gt;dev,</div><div class='ctx'> 			"Error: asked reset for invalid VFE%d\n", vfe_id);</div><div class='ctx'> 		return -ENOENT;</div><div class='hunk'>@@ -866,7 +866,7 @@ static int ispif_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> /*</div><div class='ctx'>  * __ispif_get_format - Get pointer to format structure</div><div class='ctx'>  * @ispif: ISPIF line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad from which format is requested</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='hunk'>@@ -879,8 +879,7 @@ __ispif_get_format(struct ispif_line *line,</div><div class='ctx'> 		   enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;line-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;line-&gt;fmt[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -888,7 +887,7 @@ __ispif_get_format(struct ispif_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * ispif_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @ispif: ISPIF line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad on which format is requested</div><div class='ctx'>  * @fmt: pointer to v4l2 format structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='hunk'>@@ -936,7 +935,7 @@ static void ispif_try_format(struct ispif_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * ispif_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd: ISPIF V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -969,7 +968,7 @@ static int ispif_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ispif_enum_frame_size - Handle frame size enumeration</div><div class='ctx'>  * @sd: ISPIF V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fse: pointer to v4l2_subdev_frame_size_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -1006,7 +1005,7 @@ static int ispif_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ispif_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd: ISPIF V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1030,7 +1029,7 @@ static int ispif_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ispif_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd: ISPIF V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe-170.c b/drivers/media/platform/qcom/camss/camss-vfe-170.c<br/>index 0b211fed1276..795ac3815339 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-170.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe-170.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-170.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-170.c</a></div><div class='hunk'>@@ -628,42 +628,6 @@ out_unlock:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-</div><div class='del'>-	if (vfe-&gt;id &gt;= camss-&gt;res-&gt;vfe_num)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	device_link_del(camss-&gt;genpd_link[vfe-&gt;id]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-	enum vfe_line_id id = vfe-&gt;id;</div><div class='del'>-</div><div class='del'>-	if (id &gt;= camss-&gt;res-&gt;vfe_num)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	camss-&gt;genpd_link[id] = device_link_add(camss-&gt;dev, camss-&gt;genpd[id],</div><div class='del'>-						DL_FLAG_STATELESS |</div><div class='del'>-						DL_FLAG_PM_RUNTIME |</div><div class='del'>-						DL_FLAG_RPM_ACTIVE);</div><div class='del'>-	if (!camss-&gt;genpd_link[id])</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='ctx'>  * vfe_queue_buffer - Add empty buffer</div><div class='ctx'>  * @vid: Video device structure</div><div class='ctx'>  * @buf: Buffer to be enqueued</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c<br/>index 2911e4126e7a..ef6b34c915df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe-4-1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-1.c</a></div><div class='hunk'>@@ -936,7 +936,7 @@ static irqreturn_t vfe_isr(int irq, void *dev)</div><div class='ctx'>  * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='ctx'>  * @vfe: VFE Device</div><div class='ctx'>  */</div><div class='del'>-static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='add'>+static void vfe_4_1_pm_domain_off(struct vfe_device *vfe)</div><div class='ctx'> {</div><div class='ctx'> 	/* nop */</div><div class='ctx'> }</div><div class='hunk'>@@ -945,7 +945,7 @@ static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='ctx'>  * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='ctx'>  * @vfe: VFE Device</div><div class='ctx'>  */</div><div class='del'>-static int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='add'>+static int vfe_4_1_pm_domain_on(struct vfe_device *vfe)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -999,8 +999,8 @@ const struct vfe_hw_ops vfe_ops_4_1 = {</div><div class='ctx'> 	.hw_version = vfe_hw_version,</div><div class='ctx'> 	.isr_read = vfe_isr_read,</div><div class='ctx'> 	.isr = vfe_isr,</div><div class='del'>-	.pm_domain_off = vfe_pm_domain_off,</div><div class='del'>-	.pm_domain_on = vfe_pm_domain_on,</div><div class='add'>+	.pm_domain_off = vfe_4_1_pm_domain_off,</div><div class='add'>+	.pm_domain_on = vfe_4_1_pm_domain_on,</div><div class='ctx'> 	.reg_update_clear = vfe_reg_update_clear,</div><div class='ctx'> 	.reg_update = vfe_reg_update,</div><div class='ctx'> 	.subdev_init = vfe_subdev_init,</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c<br/>index b65ed0fef595..7655d22a9fda 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-7.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe-4-7.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-7.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-7.c</a></div><div class='hunk'>@@ -1103,42 +1103,6 @@ static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1)</div><div class='ctx'> 	writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe-&gt;base + VFE_0_IRQ_CMD);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss;</div><div class='del'>-</div><div class='del'>-	if (!vfe)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	camss = vfe-&gt;camss;</div><div class='del'>-</div><div class='del'>-	device_link_del(camss-&gt;genpd_link[vfe-&gt;id]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-	enum vfe_line_id id = vfe-&gt;id;</div><div class='del'>-</div><div class='del'>-	camss-&gt;genpd_link[id] = device_link_add(camss-&gt;dev, camss-&gt;genpd[id], DL_FLAG_STATELESS |</div><div class='del'>-						DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);</div><div class='del'>-</div><div class='del'>-	if (!camss-&gt;genpd_link[id]) {</div><div class='del'>-		dev_err(vfe-&gt;camss-&gt;dev, "Failed to add VFE#%d to power domain\n", id);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void vfe_violation_read(struct vfe_device *vfe)</div><div class='ctx'> {</div><div class='ctx'> 	u32 violation = readl_relaxed(vfe-&gt;base + VFE_0_VIOLATION_STATUS);</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-8.c b/drivers/media/platform/qcom/camss/camss-vfe-4-8.c<br/>index 7b3805177f03..f52fa30f3853 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-8.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe-4-8.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-4-8.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-4-8.c</a></div><div class='hunk'>@@ -1093,37 +1093,6 @@ static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1)</div><div class='ctx'> 	writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe-&gt;base + VFE_0_IRQ_CMD);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-</div><div class='del'>-	device_link_del(camss-&gt;genpd_link[vfe-&gt;id]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-	enum vfe_line_id id = vfe-&gt;id;</div><div class='del'>-</div><div class='del'>-	camss-&gt;genpd_link[id] = device_link_add(camss-&gt;dev, camss-&gt;genpd[id], DL_FLAG_STATELESS |</div><div class='del'>-						DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);</div><div class='del'>-</div><div class='del'>-	if (!camss-&gt;genpd_link[id]) {</div><div class='del'>-		dev_err(vfe-&gt;camss-&gt;dev, "Failed to add VFE#%d to power domain\n", id);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void vfe_violation_read(struct vfe_device *vfe)</div><div class='ctx'> {</div><div class='ctx'> 	u32 violation = readl_relaxed(vfe-&gt;base + VFE_0_VIOLATION_STATUS);</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c<br/>index f2368b77fc6d..dc2735476c82 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-480.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe-480.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe-480.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe-480.c</a></div><div class='hunk'>@@ -15,31 +15,28 @@</div><div class='ctx'> #include "camss.h"</div><div class='ctx'> #include "camss-vfe.h"</div><div class='ctx'> </div><div class='del'>-/* VFE 2/3 are lite and have a different register layout */</div><div class='del'>-#define IS_LITE		(vfe-&gt;id &gt;= 2 ? 1 : 0)</div><div class='del'>-</div><div class='ctx'> #define VFE_HW_VERSION			(0x00)</div><div class='ctx'> </div><div class='del'>-#define VFE_GLOBAL_RESET_CMD		(IS_LITE ? 0x0c : 0x1c)</div><div class='del'>-#define	    GLOBAL_RESET_HW_AND_REG	(IS_LITE ? BIT(1) : BIT(0))</div><div class='add'>+#define VFE_GLOBAL_RESET_CMD		(vfe_is_lite(vfe) ? 0x0c : 0x1c)</div><div class='add'>+#define	    GLOBAL_RESET_HW_AND_REG	(vfe_is_lite(vfe) ? BIT(1) : BIT(0))</div><div class='ctx'> </div><div class='del'>-#define VFE_REG_UPDATE_CMD		(IS_LITE ? 0x20 : 0x34)</div><div class='add'>+#define VFE_REG_UPDATE_CMD		(vfe_is_lite(vfe) ? 0x20 : 0x34)</div><div class='ctx'> static inline int reg_update_rdi(struct vfe_device *vfe, int n)</div><div class='ctx'> {</div><div class='del'>-	return IS_LITE ? BIT(n) : BIT(1 + (n));</div><div class='add'>+	return vfe_is_lite(vfe) ? BIT(n) : BIT(1 + (n));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define	    REG_UPDATE_RDI		reg_update_rdi</div><div class='del'>-#define VFE_IRQ_CMD			(IS_LITE ? 0x24 : 0x38)</div><div class='add'>+#define VFE_IRQ_CMD			(vfe_is_lite(vfe) ? 0x24 : 0x38)</div><div class='ctx'> #define     IRQ_CMD_GLOBAL_CLEAR	BIT(0)</div><div class='ctx'> </div><div class='del'>-#define VFE_IRQ_MASK(n)			((IS_LITE ? 0x28 : 0x3c) + (n) * 4)</div><div class='del'>-#define	    IRQ_MASK_0_RESET_ACK	(IS_LITE ? BIT(17) : BIT(0))</div><div class='del'>-#define	    IRQ_MASK_0_BUS_TOP_IRQ	(IS_LITE ? BIT(4) : BIT(7))</div><div class='del'>-#define VFE_IRQ_CLEAR(n)		((IS_LITE ? 0x34 : 0x48) + (n) * 4)</div><div class='del'>-#define VFE_IRQ_STATUS(n)		((IS_LITE ? 0x40 : 0x54) + (n) * 4)</div><div class='add'>+#define VFE_IRQ_MASK(n)			((vfe_is_lite(vfe) ? 0x28 : 0x3c) + (n) * 4)</div><div class='add'>+#define	    IRQ_MASK_0_RESET_ACK	(vfe_is_lite(vfe) ? BIT(17) : BIT(0))</div><div class='add'>+#define	    IRQ_MASK_0_BUS_TOP_IRQ	(vfe_is_lite(vfe) ? BIT(4) : BIT(7))</div><div class='add'>+#define VFE_IRQ_CLEAR(n)		((vfe_is_lite(vfe) ? 0x34 : 0x48) + (n) * 4)</div><div class='add'>+#define VFE_IRQ_STATUS(n)		((vfe_is_lite(vfe) ? 0x40 : 0x54) + (n) * 4)</div><div class='ctx'> </div><div class='del'>-#define BUS_REG_BASE			(IS_LITE ? 0x1a00 : 0xaa00)</div><div class='add'>+#define BUS_REG_BASE			(vfe_is_lite(vfe) ? 0x1a00 : 0xaa00)</div><div class='ctx'> </div><div class='ctx'> #define VFE_BUS_WM_CGC_OVERRIDE		(BUS_REG_BASE + 0x08)</div><div class='ctx'> #define		WM_CGC_OVERRIDE_ALL	(0x3FFFFFF)</div><div class='hunk'>@@ -49,13 +46,13 @@ static inline int reg_update_rdi(struct vfe_device *vfe, int n)</div><div class='ctx'> #define VFE_BUS_IRQ_MASK(n)		(BUS_REG_BASE + 0x18 + (n) * 4)</div><div class='ctx'> static inline int bus_irq_mask_0_rdi_rup(struct vfe_device *vfe, int n)</div><div class='ctx'> {</div><div class='del'>-	return IS_LITE ? BIT(n) : BIT(3 + (n));</div><div class='add'>+	return vfe_is_lite(vfe) ? BIT(n) : BIT(3 + (n));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define     BUS_IRQ_MASK_0_RDI_RUP	bus_irq_mask_0_rdi_rup</div><div class='ctx'> static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n)</div><div class='ctx'> {</div><div class='del'>-	return IS_LITE ? BIT(4 + (n)) : BIT(6 + (n));</div><div class='add'>+	return vfe_is_lite(vfe) ? BIT(4 + (n)) : BIT(6 + (n));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define     BUS_IRQ_MASK_0_COMP_DONE	bus_irq_mask_0_comp_done</div><div class='hunk'>@@ -90,8 +87,8 @@ static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n)</div><div class='ctx'> /* for titan 480, each bus client is hardcoded to a specific path</div><div class='ctx'>  * and each bus client is part of a hardcoded "comp group"</div><div class='ctx'>  */</div><div class='del'>-#define RDI_WM(n)			((IS_LITE ? 0 : 23) + (n))</div><div class='del'>-#define RDI_COMP_GROUP(n)		((IS_LITE ? 0 : 11) + (n))</div><div class='add'>+#define RDI_WM(n)			((vfe_is_lite(vfe) ? 0 : 23) + (n))</div><div class='add'>+#define RDI_COMP_GROUP(n)		((vfe_is_lite(vfe) ? 0 : 11) + (n))</div><div class='ctx'> </div><div class='ctx'> #define MAX_VFE_OUTPUT_LINES	4</div><div class='ctx'> </div><div class='hunk'>@@ -453,42 +450,6 @@ out_unlock:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-</div><div class='del'>-	if (vfe-&gt;id &gt;= camss-&gt;res-&gt;vfe_num)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	device_link_del(camss-&gt;genpd_link[vfe-&gt;id]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='del'>- * @vfe: VFE Device</div><div class='del'>- */</div><div class='del'>-static int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='del'>-{</div><div class='del'>-	struct camss *camss = vfe-&gt;camss;</div><div class='del'>-	enum vfe_line_id id = vfe-&gt;id;</div><div class='del'>-</div><div class='del'>-	if (id &gt;= camss-&gt;res-&gt;vfe_num)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	camss-&gt;genpd_link[id] = device_link_add(camss-&gt;dev, camss-&gt;genpd[id],</div><div class='del'>-						DL_FLAG_STATELESS |</div><div class='del'>-						DL_FLAG_PM_RUNTIME |</div><div class='del'>-						DL_FLAG_RPM_ACTIVE);</div><div class='del'>-	if (!camss-&gt;genpd_link[id])</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='ctx'>  * vfe_queue_buffer - Add empty buffer</div><div class='ctx'>  * @vid: Video device structure</div><div class='ctx'>  * @buf: Buffer to be enqueued</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c<br/>index 4839e2cedfe5..2062be668f49 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe.c</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_domain.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock_types.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='hunk'>@@ -474,6 +475,40 @@ void vfe_isr_reset_ack(struct vfe_device *vfe)</div><div class='ctx'> 	complete(&amp;vfe-&gt;reset_complete);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='add'>+ * @vfe: VFE Device</div><div class='add'>+ */</div><div class='add'>+void vfe_pm_domain_off(struct vfe_device *vfe)</div><div class='add'>+{</div><div class='add'>+	if (!vfe-&gt;genpd)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	device_link_del(vfe-&gt;genpd_link);</div><div class='add'>+	vfe-&gt;genpd_link = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='add'>+ * @vfe: VFE Device</div><div class='add'>+ */</div><div class='add'>+int vfe_pm_domain_on(struct vfe_device *vfe)</div><div class='add'>+{</div><div class='add'>+	struct camss *camss = vfe-&gt;camss;</div><div class='add'>+</div><div class='add'>+	if (!vfe-&gt;genpd)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	vfe-&gt;genpd_link = device_link_add(camss-&gt;dev, vfe-&gt;genpd,</div><div class='add'>+					  DL_FLAG_STATELESS |</div><div class='add'>+					  DL_FLAG_PM_RUNTIME |</div><div class='add'>+					  DL_FLAG_RPM_ACTIVE);</div><div class='add'>+	if (!vfe-&gt;genpd_link)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int vfe_match_clock_names(struct vfe_device *vfe,</div><div class='ctx'> 				 struct camss_clock *clock)</div><div class='ctx'> {</div><div class='hunk'>@@ -815,7 +850,7 @@ static int vfe_set_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> /*</div><div class='ctx'>  * __vfe_get_format - Get pointer to format structure</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad from which format is requested</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='hunk'>@@ -828,8 +863,7 @@ __vfe_get_format(struct vfe_line *line,</div><div class='ctx'> 		 enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;line-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;line-&gt;fmt[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -837,7 +871,7 @@ __vfe_get_format(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * __vfe_get_compose - Get pointer to compose selection structure</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='ctx'>  * Return pointer to TRY or ACTIVE compose rectangle structure</div><div class='hunk'>@@ -848,8 +882,8 @@ __vfe_get_compose(struct vfe_line *line,</div><div class='ctx'> 		  enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_compose(&amp;line-&gt;subdev, sd_state,</div><div class='del'>-						   MSM_VFE_PAD_SINK);</div><div class='add'>+		return v4l2_subdev_state_get_compose(sd_state,</div><div class='add'>+						     MSM_VFE_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;line-&gt;compose;</div><div class='ctx'> }</div><div class='hunk'>@@ -857,7 +891,7 @@ __vfe_get_compose(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * __vfe_get_crop - Get pointer to crop selection structure</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @which: TRY or ACTIVE format</div><div class='ctx'>  *</div><div class='ctx'>  * Return pointer to TRY or ACTIVE crop rectangle structure</div><div class='hunk'>@@ -868,8 +902,7 @@ __vfe_get_crop(struct vfe_line *line,</div><div class='ctx'> 	       enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;line-&gt;subdev, sd_state,</div><div class='del'>-						MSM_VFE_PAD_SRC);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, MSM_VFE_PAD_SRC);</div><div class='ctx'> </div><div class='ctx'> 	return &amp;line-&gt;crop;</div><div class='ctx'> }</div><div class='hunk'>@@ -877,7 +910,7 @@ __vfe_get_crop(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad on which format is requested</div><div class='ctx'>  * @fmt: pointer to v4l2 format structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='hunk'>@@ -938,7 +971,7 @@ static void vfe_try_format(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_try_compose - Handle try compose selection by pad subdev method</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @rect: pointer to v4l2 rect structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='ctx'>  */</div><div class='hunk'>@@ -977,7 +1010,7 @@ static void vfe_try_compose(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_try_crop - Handle try crop selection by pad subdev method</div><div class='ctx'>  * @line: VFE line</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @rect: pointer to v4l2 rect structure</div><div class='ctx'>  * @which: wanted subdev format</div><div class='ctx'>  */</div><div class='hunk'>@@ -1020,7 +1053,7 @@ static void vfe_try_crop(struct vfe_line *line,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  *</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='hunk'>@@ -1054,7 +1087,7 @@ static int vfe_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_enum_frame_size - Handle frame size enumeration</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fse: pointer to v4l2_subdev_frame_size_enum structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1092,7 +1125,7 @@ static int vfe_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1120,7 +1153,7 @@ static int vfe_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1171,7 +1204,7 @@ static int vfe_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_get_selection - Handle get selection by pads subdev method</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: pointer to v4l2 subdev selection structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1241,7 +1274,7 @@ static int vfe_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * vfe_set_selection - Handle set selection by pads subdev method</div><div class='ctx'>  * @sd: VFE V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: pointer to v4l2 subdev selection structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return -EINVAL or zero on success</div><div class='hunk'>@@ -1347,6 +1380,34 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,</div><div class='ctx'> 	if (!res-&gt;line_num)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	/* Power domain */</div><div class='add'>+</div><div class='add'>+	if (res-&gt;pd_name) {</div><div class='add'>+		vfe-&gt;genpd = dev_pm_domain_attach_by_name(camss-&gt;dev,</div><div class='add'>+							  res-&gt;pd_name);</div><div class='add'>+		if (IS_ERR(vfe-&gt;genpd)) {</div><div class='add'>+			ret = PTR_ERR(vfe-&gt;genpd);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!vfe-&gt;genpd &amp;&amp; res-&gt;has_pd) {</div><div class='add'>+		/*</div><div class='add'>+		 * Legacy magic index.</div><div class='add'>+		 * Requires</div><div class='add'>+		 * power-domain = &lt;VFE_X&gt;,</div><div class='add'>+		 *                &lt;VFE_Y&gt;,</div><div class='add'>+		 *                &lt;TITAN_TOP&gt;</div><div class='add'>+		 * id must correspondng to the index of the VFE which must</div><div class='add'>+		 * come before the TOP GDSC. VFE Lite has no individually</div><div class='add'>+		 * collapasible domain which is why id &lt; vfe_num is a valid</div><div class='add'>+		 * check.</div><div class='add'>+		 */</div><div class='add'>+		vfe-&gt;genpd = dev_pm_domain_attach_by_id(camss-&gt;dev, id);</div><div class='add'>+		if (IS_ERR(vfe-&gt;genpd))</div><div class='add'>+			return PTR_ERR(vfe-&gt;genpd);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	vfe-&gt;line_num = res-&gt;line_num;</div><div class='ctx'> 	vfe-&gt;ops-&gt;subdev_init(dev, vfe);</div><div class='ctx'> </div><div class='hunk'>@@ -1470,6 +1531,19 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='add'>+ * msm_vfe_genpd_cleanup - Cleanup VFE genpd linkages</div><div class='add'>+ * @vfe: VFE device</div><div class='add'>+ */</div><div class='add'>+void msm_vfe_genpd_cleanup(struct vfe_device *vfe)</div><div class='add'>+{</div><div class='add'>+	if (vfe-&gt;genpd_link)</div><div class='add'>+		device_link_del(vfe-&gt;genpd_link);</div><div class='add'>+</div><div class='add'>+	if (vfe-&gt;genpd)</div><div class='add'>+		dev_pm_domain_detach(vfe-&gt;genpd, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='ctx'>  * vfe_link_setup - Setup VFE connections</div><div class='ctx'>  * @entity: Pointer to media entity structure</div><div class='ctx'>  * @local: Pointer to local pad</div><div class='hunk'>@@ -1663,3 +1737,8 @@ void msm_vfe_unregister_entities(struct vfe_device *vfe)</div><div class='ctx'> 		media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+bool vfe_is_lite(struct vfe_device *vfe)</div><div class='add'>+{</div><div class='add'>+	return vfe-&gt;camss-&gt;res-&gt;vfe_res[vfe-&gt;id].is_lite;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h<br/>index 09baded0dcdd..0572c9b08e11 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss-vfe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss-vfe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss-vfe.h</a></div><div class='hunk'>@@ -150,6 +150,8 @@ struct vfe_device {</div><div class='ctx'> 	const struct vfe_hw_ops_gen1 *ops_gen1;</div><div class='ctx'> 	struct vfe_isr_ops isr_ops;</div><div class='ctx'> 	struct camss_video_ops video_ops;</div><div class='add'>+	struct device *genpd;</div><div class='add'>+	struct device_link *genpd_link;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct camss_subdev_resources;</div><div class='hunk'>@@ -157,6 +159,8 @@ struct camss_subdev_resources;</div><div class='ctx'> int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,</div><div class='ctx'> 			const struct camss_subdev_resources *res, u8 id);</div><div class='ctx'> </div><div class='add'>+void msm_vfe_genpd_cleanup(struct vfe_device *vfe);</div><div class='add'>+</div><div class='ctx'> int msm_vfe_register_entities(struct vfe_device *vfe,</div><div class='ctx'> 			      struct v4l2_device *v4l2_dev);</div><div class='ctx'> </div><div class='hunk'>@@ -201,6 +205,18 @@ int vfe_reset(struct vfe_device *vfe);</div><div class='ctx'>  */</div><div class='ctx'> int vfe_disable(struct vfe_line *line);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * vfe_pm_domain_off - Disable power domains specific to this VFE.</div><div class='add'>+ * @vfe: VFE Device</div><div class='add'>+ */</div><div class='add'>+void vfe_pm_domain_off(struct vfe_device *vfe);</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * vfe_pm_domain_on - Enable power domains specific to this VFE.</div><div class='add'>+ * @vfe: VFE Device</div><div class='add'>+ */</div><div class='add'>+int vfe_pm_domain_on(struct vfe_device *vfe);</div><div class='add'>+</div><div class='ctx'> extern const struct vfe_hw_ops vfe_ops_4_1;</div><div class='ctx'> extern const struct vfe_hw_ops vfe_ops_4_7;</div><div class='ctx'> extern const struct vfe_hw_ops vfe_ops_4_8;</div><div class='hunk'>@@ -210,4 +226,14 @@ extern const struct vfe_hw_ops vfe_ops_480;</div><div class='ctx'> int vfe_get(struct vfe_device *vfe);</div><div class='ctx'> void vfe_put(struct vfe_device *vfe);</div><div class='ctx'> </div><div class='add'>+/*</div><div class='add'>+ * vfe_is_lite - Return if VFE is VFE lite.</div><div class='add'>+ * @vfe: VFE Device</div><div class='add'>+ *</div><div class='add'>+ * Some VFE lites have a different register layout.</div><div class='add'>+ *</div><div class='add'>+ * Return whether VFE is VFE lite</div><div class='add'>+ */</div><div class='add'>+bool vfe_is_lite(struct vfe_device *vfe);</div><div class='add'>+</div><div class='ctx'> #endif /* QC_MSM_CAMSS_VFE_H */</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c<br/>index 8e78dd8d5961..58f4be660290 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss.c</a></div><div class='hunk'>@@ -278,6 +278,7 @@ static const struct camss_subdev_resources vfe_res_8x96[] = {</div><div class='ctx'> 		.reg = { "vfe0" },</div><div class='ctx'> 		.interrupt = { "vfe0" },</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_4_7</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='hunk'>@@ -298,6 +299,7 @@ static const struct camss_subdev_resources vfe_res_8x96[] = {</div><div class='ctx'> 		.reg = { "vfe1" },</div><div class='ctx'> 		.interrupt = { "vfe1" },</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_4_7</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='hunk'>@@ -468,6 +470,7 @@ static const struct camss_subdev_resources vfe_res_660[] = {</div><div class='ctx'> 		.reg = { "vfe0" },</div><div class='ctx'> 		.interrupt = { "vfe0" },</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_4_8</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='hunk'>@@ -491,6 +494,7 @@ static const struct camss_subdev_resources vfe_res_660[] = {</div><div class='ctx'> 		.reg = { "vfe1" },</div><div class='ctx'> 		.interrupt = { "vfe1" },</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_4_8</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='hunk'>@@ -634,6 +638,7 @@ static const struct camss_subdev_resources csid_res_845[] = {</div><div class='ctx'> 				{ 384000000 } },</div><div class='ctx'> 		.reg = { "csid2" },</div><div class='ctx'> 		.interrupt = { "csid2" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.ops = &amp;csid_ops_gen2</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='hunk'>@@ -658,6 +663,7 @@ static const struct camss_subdev_resources vfe_res_845[] = {</div><div class='ctx'> 		.reg = { "vfe0" },</div><div class='ctx'> 		.interrupt = { "vfe0" },</div><div class='ctx'> 		.line_num = 4,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_170</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='hunk'>@@ -680,6 +686,7 @@ static const struct camss_subdev_resources vfe_res_845[] = {</div><div class='ctx'> 		.reg = { "vfe1" },</div><div class='ctx'> 		.interrupt = { "vfe1" },</div><div class='ctx'> 		.line_num = 4,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_170</div><div class='ctx'> 	},</div><div class='ctx'> </div><div class='hunk'>@@ -700,6 +707,7 @@ static const struct camss_subdev_resources vfe_res_845[] = {</div><div class='ctx'> 				{ 384000000 } },</div><div class='ctx'> 		.reg = { "vfe_lite" },</div><div class='ctx'> 		.interrupt = { "vfe_lite" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.line_num = 4,</div><div class='ctx'> 		.ops = &amp;vfe_ops_170</div><div class='ctx'> 	}</div><div class='hunk'>@@ -805,6 +813,7 @@ static const struct camss_subdev_resources csid_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "csid2" },</div><div class='ctx'> 		.interrupt = { "csid2" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.ops = &amp;csid_ops_gen2</div><div class='ctx'> 	},</div><div class='ctx'> 	/* CSID3 */</div><div class='hunk'>@@ -817,6 +826,7 @@ static const struct camss_subdev_resources csid_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "csid3" },</div><div class='ctx'> 		.interrupt = { "csid3" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.ops = &amp;csid_ops_gen2</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='hunk'>@@ -839,7 +849,9 @@ static const struct camss_subdev_resources vfe_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "vfe0" },</div><div class='ctx'> 		.interrupt = { "vfe0" },</div><div class='add'>+		.pd_name = "ife0",</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_480</div><div class='ctx'> 	},</div><div class='ctx'> 	/* VFE1 */</div><div class='hunk'>@@ -859,7 +871,9 @@ static const struct camss_subdev_resources vfe_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "vfe1" },</div><div class='ctx'> 		.interrupt = { "vfe1" },</div><div class='add'>+		.pd_name = "ife1",</div><div class='ctx'> 		.line_num = 3,</div><div class='add'>+		.has_pd = true,</div><div class='ctx'> 		.ops = &amp;vfe_ops_480</div><div class='ctx'> 	},</div><div class='ctx'> 	/* VFE2 (lite) */</div><div class='hunk'>@@ -878,6 +892,7 @@ static const struct camss_subdev_resources vfe_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "vfe_lite0" },</div><div class='ctx'> 		.interrupt = { "vfe_lite0" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.line_num = 4,</div><div class='ctx'> 		.ops = &amp;vfe_ops_480</div><div class='ctx'> 	},</div><div class='hunk'>@@ -897,6 +912,7 @@ static const struct camss_subdev_resources vfe_res_8250[] = {</div><div class='ctx'> 				{ 0 } },</div><div class='ctx'> 		.reg = { "vfe_lite1" },</div><div class='ctx'> 		.interrupt = { "vfe_lite1" },</div><div class='add'>+		.is_lite = true,</div><div class='ctx'> 		.line_num = 4,</div><div class='ctx'> 		.ops = &amp;vfe_ops_480</div><div class='ctx'> 	},</div><div class='hunk'>@@ -1196,7 +1212,7 @@ static int camss_init_subdevices(struct camss *camss)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* note: SM8250 requires VFE to be initialized before CSID */</div><div class='del'>-	for (i = 0; i &lt; camss-&gt;vfe_total_num; i++) {</div><div class='add'>+	for (i = 0; i &lt; camss-&gt;res-&gt;vfe_num; i++) {</div><div class='ctx'> 		ret = msm_vfe_subdev_init(camss, &amp;camss-&gt;vfe[i],</div><div class='ctx'> 					  &amp;res-&gt;vfe_res[i], i);</div><div class='ctx'> 		if (ret &lt; 0) {</div><div class='hunk'>@@ -1268,7 +1284,7 @@ static int camss_register_entities(struct camss *camss)</div><div class='ctx'> 		goto err_reg_ispif;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; camss-&gt;vfe_total_num; i++) {</div><div class='add'>+	for (i = 0; i &lt; camss-&gt;res-&gt;vfe_num; i++) {</div><div class='ctx'> 		ret = msm_vfe_register_entities(&amp;camss-&gt;vfe[i],</div><div class='ctx'> 						&amp;camss-&gt;v4l2_dev);</div><div class='ctx'> 		if (ret &lt; 0) {</div><div class='hunk'>@@ -1340,7 +1356,7 @@ static int camss_register_entities(struct camss *camss)</div><div class='ctx'> 				}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		for (i = 0; i &lt; camss-&gt;res-&gt;csid_num; i++)</div><div class='del'>-			for (k = 0; k &lt; camss-&gt;vfe_total_num; k++)</div><div class='add'>+			for (k = 0; k &lt; camss-&gt;res-&gt;vfe_num; k++)</div><div class='ctx'> 				for (j = 0; j &lt; camss-&gt;vfe[k].line_num; j++) {</div><div class='ctx'> 					struct v4l2_subdev *csid = &amp;camss-&gt;csid[i].subdev;</div><div class='ctx'> 					struct v4l2_subdev *vfe = &amp;camss-&gt;vfe[k].line[j].subdev;</div><div class='hunk'>@@ -1364,7 +1380,7 @@ static int camss_register_entities(struct camss *camss)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_link:</div><div class='del'>-	i = camss-&gt;vfe_total_num;</div><div class='add'>+	i = camss-&gt;res-&gt;vfe_num;</div><div class='ctx'> err_reg_vfe:</div><div class='ctx'> 	for (i--; i &gt;= 0; i--)</div><div class='ctx'> 		msm_vfe_unregister_entities(&amp;camss-&gt;vfe[i]);</div><div class='hunk'>@@ -1403,7 +1419,7 @@ static void camss_unregister_entities(struct camss *camss)</div><div class='ctx'> </div><div class='ctx'> 	msm_ispif_unregister_entities(camss-&gt;ispif);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; camss-&gt;vfe_total_num; i++)</div><div class='add'>+	for (i = 0; i &lt; camss-&gt;res-&gt;vfe_num; i++)</div><div class='ctx'> 		msm_vfe_unregister_entities(&amp;camss-&gt;vfe[i]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1478,7 +1494,9 @@ static const struct media_device_ops camss_media_ops = {</div><div class='ctx'> </div><div class='ctx'> static int camss_configure_pd(struct camss *camss)</div><div class='ctx'> {</div><div class='add'>+	const struct camss_resources *res = camss-&gt;res;</div><div class='ctx'> 	struct device *dev = camss-&gt;dev;</div><div class='add'>+	int vfepd_num;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1498,45 +1516,60 @@ static int camss_configure_pd(struct camss *camss)</div><div class='ctx'> 	if (camss-&gt;genpd_num == 1)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	camss-&gt;genpd = devm_kmalloc_array(dev, camss-&gt;genpd_num,</div><div class='del'>-					  sizeof(*camss-&gt;genpd), GFP_KERNEL);</div><div class='del'>-	if (!camss-&gt;genpd)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	/* count the # of VFEs which have flagged power-domain */</div><div class='add'>+	for (vfepd_num = i = 0; i &lt; camss-&gt;res-&gt;vfe_num; i++) {</div><div class='add'>+		if (res-&gt;vfe_res[i].has_pd)</div><div class='add'>+			vfepd_num++;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	camss-&gt;genpd_link = devm_kmalloc_array(dev, camss-&gt;genpd_num,</div><div class='del'>-					       sizeof(*camss-&gt;genpd_link),</div><div class='del'>-					       GFP_KERNEL);</div><div class='del'>-	if (!camss-&gt;genpd_link)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	/*</div><div class='add'>+	 * If the number of power-domains is greater than the number of VFEs</div><div class='add'>+	 * then the additional power-domain is for the entire CAMSS block.</div><div class='add'>+	 */</div><div class='add'>+	if (!(camss-&gt;genpd_num &gt; vfepd_num))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * VFE power domains are in the beginning of the list, and while all</div><div class='del'>-	 * power domains should be attached, only if TITAN_TOP power domain is</div><div class='del'>-	 * found in the list, it should be linked over here.</div><div class='add'>+	 * If a power-domain name is defined try to use it.</div><div class='add'>+	 * It is possible we are running a new kernel with an old dtb so</div><div class='add'>+	 * fallback to indexes even if a pd_name is defined but not found.</div><div class='ctx'> 	 */</div><div class='del'>-	for (i = 0; i &lt; camss-&gt;genpd_num; i++) {</div><div class='del'>-		camss-&gt;genpd[i] = dev_pm_domain_attach_by_id(camss-&gt;dev, i);</div><div class='del'>-		if (IS_ERR(camss-&gt;genpd[i])) {</div><div class='del'>-			ret = PTR_ERR(camss-&gt;genpd[i]);</div><div class='add'>+	if (camss-&gt;res-&gt;pd_name) {</div><div class='add'>+		camss-&gt;genpd = dev_pm_domain_attach_by_name(camss-&gt;dev,</div><div class='add'>+							    camss-&gt;res-&gt;pd_name);</div><div class='add'>+		if (IS_ERR(camss-&gt;genpd)) {</div><div class='add'>+			ret = PTR_ERR(camss-&gt;genpd);</div><div class='ctx'> 			goto fail_pm;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (i &gt; camss-&gt;res-&gt;vfe_num) {</div><div class='del'>-		camss-&gt;genpd_link[i - 1] = device_link_add(camss-&gt;dev, camss-&gt;genpd[i - 1],</div><div class='del'>-							   DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |</div><div class='del'>-							   DL_FLAG_RPM_ACTIVE);</div><div class='del'>-		if (!camss-&gt;genpd_link[i - 1]) {</div><div class='del'>-			ret = -EINVAL;</div><div class='del'>-			goto fail_pm;</div><div class='del'>-		}</div><div class='add'>+	if (!camss-&gt;genpd) {</div><div class='add'>+		/*</div><div class='add'>+		 * Legacy magic index. TITAN_TOP GDSC must be the last</div><div class='add'>+		 * item in the power-domain list.</div><div class='add'>+		 */</div><div class='add'>+		camss-&gt;genpd = dev_pm_domain_attach_by_id(camss-&gt;dev,</div><div class='add'>+							  camss-&gt;genpd_num - 1);</div><div class='add'>+	}</div><div class='add'>+	if (IS_ERR_OR_NULL(camss-&gt;genpd)) {</div><div class='add'>+		if (!camss-&gt;genpd)</div><div class='add'>+			ret = -ENODEV;</div><div class='add'>+		else</div><div class='add'>+			ret = PTR_ERR(camss-&gt;genpd);</div><div class='add'>+		goto fail_pm;</div><div class='add'>+	}</div><div class='add'>+	camss-&gt;genpd_link = device_link_add(camss-&gt;dev, camss-&gt;genpd,</div><div class='add'>+					    DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |</div><div class='add'>+					    DL_FLAG_RPM_ACTIVE);</div><div class='add'>+	if (!camss-&gt;genpd_link) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto fail_pm;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> fail_pm:</div><div class='del'>-	for (--i ; i &gt;= 0; i--)</div><div class='del'>-		dev_pm_domain_detach(camss-&gt;genpd[i], true);</div><div class='add'>+	dev_pm_domain_detach(camss-&gt;genpd, true);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1558,18 +1591,25 @@ static int camss_icc_get(struct camss *camss)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void camss_genpd_cleanup(struct camss *camss)</div><div class='add'>+static void camss_genpd_subdevice_cleanup(struct camss *camss)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; camss-&gt;res-&gt;vfe_num; i++)</div><div class='add'>+		msm_vfe_genpd_cleanup(&amp;camss-&gt;vfe[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void camss_genpd_cleanup(struct camss *camss)</div><div class='add'>+{</div><div class='ctx'> 	if (camss-&gt;genpd_num == 1)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (camss-&gt;genpd_num &gt; camss-&gt;res-&gt;vfe_num)</div><div class='del'>-		device_link_del(camss-&gt;genpd_link[camss-&gt;genpd_num - 1]);</div><div class='add'>+	camss_genpd_subdevice_cleanup(camss);</div><div class='add'>+</div><div class='add'>+	if (camss-&gt;genpd_link)</div><div class='add'>+		device_link_del(camss-&gt;genpd_link);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; camss-&gt;genpd_num; i++)</div><div class='del'>-		dev_pm_domain_detach(camss-&gt;genpd[i], true);</div><div class='add'>+	dev_pm_domain_detach(camss-&gt;genpd, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -1612,8 +1652,7 @@ static int camss_probe(struct platform_device *pdev)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	camss-&gt;vfe_total_num = camss-&gt;res-&gt;vfe_num + camss-&gt;res-&gt;vfe_lite_num;</div><div class='del'>-	camss-&gt;vfe = devm_kcalloc(dev, camss-&gt;vfe_total_num,</div><div class='add'>+	camss-&gt;vfe = devm_kcalloc(dev, camss-&gt;res-&gt;vfe_num,</div><div class='ctx'> 				  sizeof(*camss-&gt;vfe), GFP_KERNEL);</div><div class='ctx'> 	if (!camss-&gt;vfe)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -1771,12 +1810,12 @@ static const struct camss_resources sdm845_resources = {</div><div class='ctx'> 	.vfe_res = vfe_res_845,</div><div class='ctx'> 	.csiphy_num = ARRAY_SIZE(csiphy_res_845),</div><div class='ctx'> 	.csid_num = ARRAY_SIZE(csid_res_845),</div><div class='del'>-	.vfe_num = 2,</div><div class='del'>-	.vfe_lite_num = 1,</div><div class='add'>+	.vfe_num = ARRAY_SIZE(vfe_res_845),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct camss_resources sm8250_resources = {</div><div class='ctx'> 	.version = CAMSS_8250,</div><div class='add'>+	.pd_name = "top",</div><div class='ctx'> 	.csiphy_res = csiphy_res_8250,</div><div class='ctx'> 	.csid_res = csid_res_8250,</div><div class='ctx'> 	.vfe_res = vfe_res_8250,</div><div class='hunk'>@@ -1784,8 +1823,7 @@ static const struct camss_resources sm8250_resources = {</div><div class='ctx'> 	.icc_path_num = ARRAY_SIZE(icc_res_sm8250),</div><div class='ctx'> 	.csiphy_num = ARRAY_SIZE(csiphy_res_8250),</div><div class='ctx'> 	.csid_num = ARRAY_SIZE(csid_res_8250),</div><div class='del'>-	.vfe_num = 2,</div><div class='del'>-	.vfe_lite_num = 2,</div><div class='add'>+	.vfe_num = ARRAY_SIZE(vfe_res_8250),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id camss_dt_match[] = {</div><div class='head'>diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h<br/>index 8acad7321c09..a0c2dcc779f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/camss/camss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/camss/camss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/camss/camss.h</a></div><div class='hunk'>@@ -48,7 +48,10 @@ struct camss_subdev_resources {</div><div class='ctx'> 	u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX];</div><div class='ctx'> 	char *reg[CAMSS_RES_MAX];</div><div class='ctx'> 	char *interrupt[CAMSS_RES_MAX];</div><div class='add'>+	char *pd_name;</div><div class='ctx'> 	u8 line_num;</div><div class='add'>+	bool has_pd;</div><div class='add'>+	bool is_lite;</div><div class='ctx'> 	const void *ops;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -83,6 +86,7 @@ enum icc_count {</div><div class='ctx'> </div><div class='ctx'> struct camss_resources {</div><div class='ctx'> 	enum camss_version version;</div><div class='add'>+	const char *pd_name;</div><div class='ctx'> 	const struct camss_subdev_resources *csiphy_res;</div><div class='ctx'> 	const struct camss_subdev_resources *csid_res;</div><div class='ctx'> 	const struct camss_subdev_resources *ispif_res;</div><div class='hunk'>@@ -92,7 +96,6 @@ struct camss_resources {</div><div class='ctx'> 	const unsigned int csiphy_num;</div><div class='ctx'> 	const unsigned int csid_num;</div><div class='ctx'> 	const unsigned int vfe_num;</div><div class='del'>-	const unsigned int vfe_lite_num;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct camss {</div><div class='hunk'>@@ -106,11 +109,10 @@ struct camss {</div><div class='ctx'> 	struct vfe_device *vfe;</div><div class='ctx'> 	atomic_t ref_count;</div><div class='ctx'> 	int genpd_num;</div><div class='del'>-	struct device **genpd;</div><div class='del'>-	struct device_link **genpd_link;</div><div class='add'>+	struct device *genpd;</div><div class='add'>+	struct device_link *genpd_link;</div><div class='ctx'> 	struct icc_path *icc_path[ICC_SM8250_COUNT];</div><div class='ctx'> 	const struct camss_resources *res;</div><div class='del'>-	unsigned int vfe_total_num;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct camss_camera_interface {</div><div class='head'>diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c<br/>index 9cffe975581b..a712dd4f02a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/venus/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/core.c</a></div><div class='hunk'>@@ -881,6 +881,10 @@ static const struct venus_resources sc7280_res = {</div><div class='ctx'> 	.vmem_size = 0,</div><div class='ctx'> 	.vmem_addr = 0,</div><div class='ctx'> 	.dma_mask = 0xe0000000 - 1,</div><div class='add'>+	.cp_start = 0,</div><div class='add'>+	.cp_size = 0x25800000,</div><div class='add'>+	.cp_nonpixel_start = 0x1000000,</div><div class='add'>+	.cp_nonpixel_size = 0x24800000,</div><div class='ctx'> 	.fwname = "qcom/vpu-2.0/venus.mbn",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/qcom/venus/vdec.c b/drivers/media/platform/qcom/venus/vdec.c<br/>index dbf305cec120..29130a9441e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/vdec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/venus/vdec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/vdec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/vdec.c</a></div><div class='hunk'>@@ -1641,7 +1641,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	src_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct venus_buffer);</div><div class='ctx'> 	src_vq-&gt;allow_zero_bytesused = 1;</div><div class='del'>-	src_vq-&gt;min_buffers_needed = 0;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = 0;</div><div class='ctx'> 	src_vq-&gt;dev = inst-&gt;core-&gt;dev;</div><div class='ctx'> 	src_vq-&gt;lock = &amp;inst-&gt;ctx_q_lock;</div><div class='ctx'> 	ret = vb2_queue_init(src_vq);</div><div class='hunk'>@@ -1656,7 +1656,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	dst_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct venus_buffer);</div><div class='ctx'> 	dst_vq-&gt;allow_zero_bytesused = 1;</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = 0;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = 0;</div><div class='ctx'> 	dst_vq-&gt;dev = inst-&gt;core-&gt;dev;</div><div class='ctx'> 	dst_vq-&gt;lock = &amp;inst-&gt;ctx_q_lock;</div><div class='ctx'> 	return vb2_queue_init(dst_vq);</div><div class='head'>diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c<br/>index 44b13696cf82..3ec2fb8d9fab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/venc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/qcom/venus/venc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/qcom/venus/venc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/qcom/venus/venc.c</a></div><div class='hunk'>@@ -1398,7 +1398,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	src_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct venus_buffer);</div><div class='ctx'> 	src_vq-&gt;allow_zero_bytesused = 1;</div><div class='del'>-	src_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	src_vq-&gt;dev = inst-&gt;core-&gt;dev;</div><div class='ctx'> 	src_vq-&gt;lock = &amp;inst-&gt;ctx_q_lock;</div><div class='ctx'> 	if (inst-&gt;core-&gt;res-&gt;hfi_version == HFI_VERSION_1XX)</div><div class='hunk'>@@ -1415,7 +1415,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	dst_vq-&gt;drv_priv = inst;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct venus_buffer);</div><div class='ctx'> 	dst_vq-&gt;allow_zero_bytesused = 1;</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	dst_vq-&gt;dev = inst-&gt;core-&gt;dev;</div><div class='ctx'> 	dst_vq-&gt;lock = &amp;inst-&gt;ctx_q_lock;</div><div class='ctx'> 	return vb2_queue_init(dst_vq);</div><div class='head'>diff --git a/drivers/media/platform/renesas/rcar-isp.c b/drivers/media/platform/renesas/rcar-isp.c<br/>index 19a005d83733..530d65fc546b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-isp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rcar-isp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-isp.c</a></div><div class='hunk'>@@ -282,7 +282,7 @@ static int risp_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE) {</div><div class='ctx'> 		isp-&gt;mf = format-&gt;format;</div><div class='ctx'> 	} else {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*framefmt = format-&gt;format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -302,7 +302,7 @@ static int risp_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		format-&gt;format = isp-&gt;mf;</div><div class='ctx'> 	else</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		format-&gt;format = *v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;isp-&gt;lock);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c b/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c<br/>index 66fe553a00e7..582d5e35db0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rcar-vin/rcar-csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-vin/rcar-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-vin/rcar-csi2.c</a></div><div class='hunk'>@@ -1185,7 +1185,7 @@ static int rcsi2_set_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE) {</div><div class='ctx'> 		priv-&gt;mf = format-&gt;format;</div><div class='ctx'> 	} else {</div><div class='del'>-		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		framefmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 		*framefmt = format-&gt;format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1205,7 +1205,7 @@ static int rcsi2_get_pad_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		format-&gt;format = priv-&gt;mf;</div><div class='ctx'> 	else</div><div class='del'>-		format-&gt;format = *v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+		format-&gt;format = *v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;lock);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/rcar-vin/rcar-dma.c b/drivers/media/platform/renesas/rcar-vin/rcar-dma.c<br/>index 2a77353f10b5..e2c40abc6d3d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-vin/rcar-dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rcar-vin/rcar-dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar-vin/rcar-dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar-vin/rcar-dma.c</a></div><div class='hunk'>@@ -1559,7 +1559,7 @@ int rvin_dma_register(struct rvin_dev *vin, int irq)</div><div class='ctx'> 	q-&gt;ops = &amp;rvin_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 4;</div><div class='add'>+	q-&gt;min_queued_buffers = 4;</div><div class='ctx'> 	q-&gt;dev = vin-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/renesas/rcar_drif.c b/drivers/media/platform/renesas/rcar_drif.c<br/>index 292c5bf9e50c..f21d05054341 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar_drif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rcar_drif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rcar_drif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rcar_drif.c</a></div><div class='hunk'>@@ -424,10 +424,11 @@ static int rcar_drif_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 			unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	/* Need at least 16 buffers */</div><div class='del'>-	if (vq-&gt;num_buffers + *num_buffers &lt; 16)</div><div class='del'>-		*num_buffers = 16 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *num_buffers &lt; 16)</div><div class='add'>+		*num_buffers = 16 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	*num_planes = 1;</div><div class='ctx'> 	sizes[0] = PAGE_ALIGN(sdr-&gt;fmt-&gt;buffersize);</div><div class='head'>diff --git a/drivers/media/platform/renesas/renesas-ceu.c b/drivers/media/platform/renesas/renesas-ceu.c<br/>index 2562b30acfb9..167760276796 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/renesas-ceu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/renesas-ceu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/renesas-ceu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/renesas-ceu.c</a></div><div class='hunk'>@@ -1399,7 +1399,7 @@ static int ceu_notify_complete(struct v4l2_async_notifier *notifier)</div><div class='ctx'> 	q-&gt;mem_ops		= &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;buf_struct_size	= sizeof(struct ceu_buffer);</div><div class='ctx'> 	q-&gt;timestamp_flags	= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed	= 2;</div><div class='add'>+	q-&gt;min_queued_buffers	= 2;</div><div class='ctx'> 	q-&gt;lock			= &amp;ceudev-&gt;mlock;</div><div class='ctx'> 	q-&gt;dev			= ceudev-&gt;v4l2_dev.dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c<br/>index ad2bd71037ab..d20f4eff93a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c</a></div><div class='hunk'>@@ -250,7 +250,7 @@ static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(&amp;csi2-&gt;subdev);</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(&amp;csi2-&gt;subdev, state, RZG2L_CSI2_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);</div><div class='ctx'> 	format = rzg2l_csi2_code_to_fmt(fmt-&gt;code);</div><div class='ctx'> 	v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='hunk'>@@ -500,13 +500,13 @@ static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *src_format;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_format;</div><div class='ctx'> </div><div class='del'>-	src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SOURCE);</div><div class='add'>+	src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE);</div><div class='ctx'> 	if (fmt-&gt;pad == RZG2L_CSI2_SOURCE) {</div><div class='ctx'> 		fmt-&gt;format = *src_format;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sink_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SINK);</div><div class='add'>+	sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);</div><div class='ctx'> </div><div class='ctx'> 	if (!rzg2l_csi2_code_to_fmt(fmt-&gt;format.code))</div><div class='ctx'> 		sink_format-&gt;code = rzg2l_csi2_formats[0].code;</div><div class='hunk'>@@ -530,8 +530,8 @@ static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rzg2l_csi2_init_config(struct v4l2_subdev *sd,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int rzg2l_csi2_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, };</div><div class='ctx'> </div><div class='hunk'>@@ -582,7 +582,6 @@ static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = rzg2l_csi2_enum_mbus_code,</div><div class='del'>-	.init_cfg = rzg2l_csi2_init_config,</div><div class='ctx'> 	.enum_frame_size = rzg2l_csi2_enum_frame_size,</div><div class='ctx'> 	.set_fmt = rzg2l_csi2_set_format,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -593,6 +592,10 @@ static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;rzg2l_csi2_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = {</div><div class='add'>+	.init_state = rzg2l_csi2_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Async handling and registration of subdevices and links.</div><div class='ctx'>  */</div><div class='hunk'>@@ -777,6 +780,7 @@ static int rzg2l_csi2_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	csi2-&gt;subdev.dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	v4l2_subdev_init(&amp;csi2-&gt;subdev, &amp;rzg2l_csi2_subdev_ops);</div><div class='add'>+	csi2-&gt;subdev.internal_ops = &amp;rzg2l_csi2_internal_ops;</div><div class='ctx'> 	v4l2_set_subdevdata(&amp;csi2-&gt;subdev, &amp;pdev-&gt;dev);</div><div class='ctx'> 	snprintf(csi2-&gt;subdev.name, sizeof(csi2-&gt;subdev.name),</div><div class='ctx'> 		 "csi-%s", dev_name(&amp;pdev-&gt;dev));</div><div class='head'>diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c<br/>index 4dcd2faff5bb..9f351a05893e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c</a></div><div class='hunk'>@@ -39,7 +39,7 @@ struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru)</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(&amp;cru-&gt;ip.subdev);</div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(&amp;cru-&gt;ip.subdev, state, 1);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, 1);</div><div class='ctx'> 	v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='ctx'> 	return fmt;</div><div class='hunk'>@@ -108,13 +108,13 @@ static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *src_format;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_format;</div><div class='ctx'> </div><div class='del'>-	src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CRU_IP_SOURCE);</div><div class='add'>+	src_format = v4l2_subdev_state_get_format(state, RZG2L_CRU_IP_SOURCE);</div><div class='ctx'> 	if (fmt-&gt;pad == RZG2L_CRU_IP_SOURCE) {</div><div class='ctx'> 		fmt-&gt;format = *src_format;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sink_format = v4l2_subdev_get_pad_format(sd, state, fmt-&gt;pad);</div><div class='add'>+	sink_format = v4l2_subdev_state_get_format(state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (!rzg2l_cru_ip_code_to_fmt(fmt-&gt;format.code))</div><div class='ctx'> 		sink_format-&gt;code = rzg2l_cru_ip_formats[0].code;</div><div class='hunk'>@@ -168,8 +168,8 @@ static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rzg2l_cru_ip_init_config(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int rzg2l_cru_ip_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format fmt = { .pad = RZG2L_CRU_IP_SINK, };</div><div class='ctx'> </div><div class='hunk'>@@ -192,7 +192,6 @@ static const struct v4l2_subdev_video_ops rzg2l_cru_ip_video_ops = {</div><div class='ctx'> static const struct v4l2_subdev_pad_ops rzg2l_cru_ip_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = rzg2l_cru_ip_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = rzg2l_cru_ip_enum_frame_size,</div><div class='del'>-	.init_cfg = rzg2l_cru_ip_init_config,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = rzg2l_cru_ip_set_format,</div><div class='ctx'> };</div><div class='hunk'>@@ -202,6 +201,10 @@ static const struct v4l2_subdev_ops rzg2l_cru_ip_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;rzg2l_cru_ip_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops rzg2l_cru_ip_internal_ops = {</div><div class='add'>+	.init_state = rzg2l_cru_ip_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct media_entity_operations rzg2l_cru_ip_entity_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -213,6 +216,7 @@ int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru)</div><div class='ctx'> </div><div class='ctx'> 	ip-&gt;subdev.dev = cru-&gt;dev;</div><div class='ctx'> 	v4l2_subdev_init(&amp;ip-&gt;subdev, &amp;rzg2l_cru_ip_subdev_ops);</div><div class='add'>+	ip-&gt;subdev.internal_ops = &amp;rzg2l_cru_ip_internal_ops;</div><div class='ctx'> 	v4l2_set_subdevdata(&amp;ip-&gt;subdev, cru);</div><div class='ctx'> 	snprintf(ip-&gt;subdev.name, sizeof(ip-&gt;subdev.name),</div><div class='ctx'> 		 "cru-ip-%s", dev_name(cru-&gt;dev));</div><div class='head'>diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c<br/>index e6eedd65b71d..d0ffa90bc656 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c</a></div><div class='hunk'>@@ -767,7 +767,7 @@ int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru)</div><div class='ctx'> 	q-&gt;ops = &amp;rzg2l_cru_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 4;</div><div class='add'>+	q-&gt;min_queued_buffers = 4;</div><div class='ctx'> 	q-&gt;dev = cru-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/renesas/sh_vou.c b/drivers/media/platform/renesas/sh_vou.c<br/>index f792aedc9d82..1e74dd601c2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/sh_vou.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/sh_vou.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/sh_vou.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/sh_vou.c</a></div><div class='hunk'>@@ -1297,7 +1297,7 @@ static int sh_vou_probe(struct platform_device *pdev)</div><div class='ctx'> 	q-&gt;ops = &amp;sh_vou_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;lock = &amp;vou_dev-&gt;fop_lock;</div><div class='ctx'> 	q-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_brx.c b/drivers/media/platform/renesas/vsp1/vsp1_brx.c<br/>index 89385b4cabe5..a8535c6e2c46 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_brx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_brx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_brx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_brx.c</a></div><div class='hunk'>@@ -100,7 +100,7 @@ static struct v4l2_rect *brx_get_compose(struct vsp1_brx *brx,</div><div class='ctx'> 					 struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 					 unsigned int pad)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_compose(&amp;brx-&gt;entity.subdev, sd_state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_compose(sd_state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void brx_try_format(struct vsp1_brx *brx,</div><div class='hunk'>@@ -136,29 +136,28 @@ static int brx_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			  struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_brx *brx = to_brx(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;brx-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;brx-&gt;entity, sd_state,</div><div class='del'>-					    fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;brx-&gt;entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	brx_try_format(brx, config, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='add'>+	brx_try_format(brx, state, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, state, fmt-&gt;pad);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset the compose rectangle. */</div><div class='ctx'> 	if (fmt-&gt;pad != brx-&gt;entity.source_pad) {</div><div class='ctx'> 		struct v4l2_rect *compose;</div><div class='ctx'> </div><div class='del'>-		compose = brx_get_compose(brx, config, fmt-&gt;pad);</div><div class='add'>+		compose = brx_get_compose(brx, state, fmt-&gt;pad);</div><div class='ctx'> 		compose-&gt;left = 0;</div><div class='ctx'> 		compose-&gt;top = 0;</div><div class='ctx'> 		compose-&gt;width = format-&gt;width;</div><div class='hunk'>@@ -171,7 +170,7 @@ static int brx_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt;= brx-&gt;entity.source_pad; ++i) {</div><div class='ctx'> 			format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity,</div><div class='del'>-							    config, i);</div><div class='add'>+							    state, i);</div><div class='ctx'> 			format-&gt;code = fmt-&gt;format.code;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -186,7 +185,7 @@ static int brx_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			     struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_brx *brx = to_brx(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;pad == brx-&gt;entity.source_pad)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -200,13 +199,13 @@ static int brx_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		config = vsp1_entity_get_pad_config(&amp;brx-&gt;entity, sd_state,</div><div class='del'>-						    sel-&gt;which);</div><div class='del'>-		if (!config)</div><div class='add'>+		state = vsp1_entity_get_state(&amp;brx-&gt;entity, sd_state,</div><div class='add'>+					      sel-&gt;which);</div><div class='add'>+		if (!state)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;brx-&gt;entity.lock);</div><div class='del'>-		sel-&gt;r = *brx_get_compose(brx, config, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *brx_get_compose(brx, state, sel-&gt;pad);</div><div class='ctx'> 		mutex_unlock(&amp;brx-&gt;entity.lock);</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -220,7 +219,7 @@ static int brx_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			     struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_brx *brx = to_brx(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *compose;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -233,9 +232,8 @@ static int brx_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;brx-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;brx-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;brx-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -244,7 +242,7 @@ static int brx_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	 * The compose rectangle top left corner must be inside the output</div><div class='ctx'> 	 * frame.</div><div class='ctx'> 	 */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, state,</div><div class='ctx'> 					    brx-&gt;entity.source_pad);</div><div class='ctx'> 	sel-&gt;r.left = clamp_t(unsigned int, sel-&gt;r.left, 0, format-&gt;width - 1);</div><div class='ctx'> 	sel-&gt;r.top = clamp_t(unsigned int, sel-&gt;r.top, 0, format-&gt;height - 1);</div><div class='hunk'>@@ -253,11 +251,11 @@ static int brx_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	 * Scaling isn't supported, the compose rectangle size must be identical</div><div class='ctx'> 	 * to the sink format size.</div><div class='ctx'> 	 */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, config, sel-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, state, sel-&gt;pad);</div><div class='ctx'> 	sel-&gt;r.width = format-&gt;width;</div><div class='ctx'> 	sel-&gt;r.height = format-&gt;height;</div><div class='ctx'> </div><div class='del'>-	compose = brx_get_compose(brx, config, sel-&gt;pad);</div><div class='add'>+	compose = brx_get_compose(brx, state, sel-&gt;pad);</div><div class='ctx'> 	*compose = sel-&gt;r;</div><div class='ctx'> </div><div class='ctx'> done:</div><div class='hunk'>@@ -266,7 +264,6 @@ done:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops brx_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = brx_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = brx_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -293,7 +290,7 @@ static void brx_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	unsigned int flags;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, brx-&gt;entity.config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;brx-&gt;entity, brx-&gt;entity.state,</div><div class='ctx'> 					    brx-&gt;entity.source_pad);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_clu.c b/drivers/media/platform/renesas/vsp1/vsp1_clu.c<br/>index c5217fee24f1..625776a9bda4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_clu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_clu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_clu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_clu.c</a></div><div class='hunk'>@@ -155,7 +155,6 @@ static int clu_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops clu_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = clu_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = clu_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -182,8 +181,7 @@ static void clu_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	 * The yuv_mode can't be changed during streaming. Cache it internally</div><div class='ctx'> 	 * for future runtime configuration calls.</div><div class='ctx'> 	 */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;clu-&gt;entity,</div><div class='del'>-					    clu-&gt;entity.config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;clu-&gt;entity, clu-&gt;entity.state,</div><div class='ctx'> 					    CLU_PAD_SINK);</div><div class='ctx'> 	clu-&gt;yuv_mode = format-&gt;code == MEDIA_BUS_FMT_AYUV8_1X32;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_entity.c b/drivers/media/platform/renesas/vsp1/vsp1_entity.c<br/>index c31f05a80bb5..0a5a7f9cc870 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_entity.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_entity.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_entity.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_entity.c</a></div><div class='hunk'>@@ -101,27 +101,26 @@ void vsp1_entity_configure_partition(struct vsp1_entity *entity,</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * vsp1_entity_get_pad_config - Get the pad configuration for an entity</div><div class='add'>+ * vsp1_entity_get_state - Get the subdev state for an entity</div><div class='ctx'>  * @entity: the entity</div><div class='ctx'>  * @sd_state: the TRY state</div><div class='del'>- * @which: configuration selector (ACTIVE or TRY)</div><div class='add'>+ * @which: state selector (ACTIVE or TRY)</div><div class='ctx'>  *</div><div class='ctx'>  * When called with which set to V4L2_SUBDEV_FORMAT_ACTIVE the caller must hold</div><div class='ctx'>  * the entity lock to access the returned configuration.</div><div class='ctx'>  *</div><div class='del'>- * Return the pad configuration requested by the which argument. The TRY</div><div class='del'>- * configuration is passed explicitly to the function through the cfg argument</div><div class='del'>- * and simply returned when requested. The ACTIVE configuration comes from the</div><div class='del'>- * entity structure.</div><div class='add'>+ * Return the subdev state requested by the which argument. The TRY state is</div><div class='add'>+ * passed explicitly to the function through the sd_state argument and simply</div><div class='add'>+ * returned when requested. The ACTIVE state comes from the entity structure.</div><div class='ctx'>  */</div><div class='ctx'> struct v4l2_subdev_state *</div><div class='del'>-vsp1_entity_get_pad_config(struct vsp1_entity *entity,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state,</div><div class='del'>-			   enum v4l2_subdev_format_whence which)</div><div class='add'>+vsp1_entity_get_state(struct vsp1_entity *entity,</div><div class='add'>+		      struct v4l2_subdev_state *sd_state,</div><div class='add'>+		      enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='del'>-		return entity-&gt;config;</div><div class='add'>+		return entity-&gt;state;</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return sd_state;</div><div class='hunk'>@@ -142,7 +141,7 @@ vsp1_entity_get_pad_format(struct vsp1_entity *entity,</div><div class='ctx'> 			   struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 			   unsigned int pad)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_format(&amp;entity-&gt;subdev, sd_state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -163,46 +162,18 @@ vsp1_entity_get_pad_selection(struct vsp1_entity *entity,</div><div class='ctx'> {</div><div class='ctx'> 	switch (target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		return v4l2_subdev_get_try_compose(&amp;entity-&gt;subdev, sd_state,</div><div class='del'>-						   pad);</div><div class='add'>+		return v4l2_subdev_state_get_compose(sd_state, pad);</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;entity-&gt;subdev, sd_state,</div><div class='del'>-						pad);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, pad);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='del'>- * vsp1_entity_init_cfg - Initialize formats on all pads</div><div class='del'>- * @subdev: V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='del'>- *</div><div class='del'>- * Initialize all pad formats with default values in the given pad config. This</div><div class='del'>- * function can be used as a handler for the subdev pad::init_cfg operation.</div><div class='del'>- */</div><div class='del'>-int vsp1_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-			 struct v4l2_subdev_state *sd_state)</div><div class='del'>-{</div><div class='del'>-	unsigned int pad;</div><div class='del'>-</div><div class='del'>-	for (pad = 0; pad &lt; subdev-&gt;entity.num_pads - 1; ++pad) {</div><div class='del'>-		struct v4l2_subdev_format format = {</div><div class='del'>-			.pad = pad,</div><div class='del'>-			.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY</div><div class='del'>-			       : V4L2_SUBDEV_FORMAT_ACTIVE,</div><div class='del'>-		};</div><div class='del'>-</div><div class='del'>-		v4l2_subdev_call(subdev, pad, set_fmt, sd_state, &amp;format);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='ctx'>  * vsp1_subdev_get_pad_format - Subdev pad get_fmt handler</div><div class='ctx'>  * @subdev: V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: V4L2 subdev format</div><div class='ctx'>  *</div><div class='ctx'>  * This function implements the subdev get_fmt pad operation. It can be used as</div><div class='hunk'>@@ -213,14 +184,14 @@ int vsp1_subdev_get_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_entity *entity = to_vsp1_entity(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(entity, sd_state, fmt-&gt;which);</div><div class='del'>-	if (!config)</div><div class='add'>+	state = vsp1_entity_get_state(entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;entity-&gt;lock);</div><div class='del'>-	fmt-&gt;format = *vsp1_entity_get_pad_format(entity, config, fmt-&gt;pad);</div><div class='add'>+	fmt-&gt;format = *vsp1_entity_get_pad_format(entity, state, fmt-&gt;pad);</div><div class='ctx'> 	mutex_unlock(&amp;entity-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -229,7 +200,7 @@ int vsp1_subdev_get_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> /*</div><div class='ctx'>  * vsp1_subdev_enum_mbus_code - Subdev pad enum_mbus_code handler</div><div class='ctx'>  * @subdev: V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code: Media bus code enumeration</div><div class='ctx'>  * @codes: Array of supported media bus codes</div><div class='ctx'>  * @ncodes: Number of supported media bus codes</div><div class='hunk'>@@ -252,7 +223,7 @@ int vsp1_subdev_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 		code-&gt;code = codes[code-&gt;index];</div><div class='ctx'> 	} else {</div><div class='del'>-		struct v4l2_subdev_state *config;</div><div class='add'>+		struct v4l2_subdev_state *state;</div><div class='ctx'> 		struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='hunk'>@@ -262,13 +233,12 @@ int vsp1_subdev_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='ctx'> 		if (code-&gt;index)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		config = vsp1_entity_get_pad_config(entity, sd_state,</div><div class='del'>-						    code-&gt;which);</div><div class='del'>-		if (!config)</div><div class='add'>+		state = vsp1_entity_get_state(entity, sd_state, code-&gt;which);</div><div class='add'>+		if (!state)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;entity-&gt;lock);</div><div class='del'>-		format = vsp1_entity_get_pad_format(entity, config, 0);</div><div class='add'>+		format = vsp1_entity_get_pad_format(entity, state, 0);</div><div class='ctx'> 		code-&gt;code = format-&gt;code;</div><div class='ctx'> 		mutex_unlock(&amp;entity-&gt;lock);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -279,7 +249,7 @@ int vsp1_subdev_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='ctx'> /*</div><div class='ctx'>  * vsp1_subdev_enum_frame_size - Subdev pad enum_frame_size handler</div><div class='ctx'>  * @subdev: V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fse: Frame size enumeration</div><div class='ctx'>  * @min_width: Minimum image width</div><div class='ctx'>  * @min_height: Minimum image height</div><div class='hunk'>@@ -298,15 +268,15 @@ int vsp1_subdev_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> 				unsigned int max_width, unsigned int max_height)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_entity *entity = to_vsp1_entity(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(entity, sd_state, fse-&gt;which);</div><div class='del'>-	if (!config)</div><div class='add'>+	state = vsp1_entity_get_state(entity, sd_state, fse-&gt;which);</div><div class='add'>+	if (!state)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(entity, config, fse-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(entity, state, fse-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;entity-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -339,7 +309,7 @@ done:</div><div class='ctx'> /*</div><div class='ctx'>  * vsp1_subdev_set_pad_format - Subdev pad set_fmt handler</div><div class='ctx'>  * @subdev: V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: V4L2 subdev format</div><div class='ctx'>  * @codes: Array of supported media bus codes</div><div class='ctx'>  * @ncodes: Number of supported media bus codes</div><div class='hunk'>@@ -362,7 +332,7 @@ int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       unsigned int max_width, unsigned int max_height)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_entity *entity = to_vsp1_entity(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *selection;</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -370,13 +340,13 @@ int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;entity-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(entity, sd_state, fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(entity, state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == entity-&gt;source_pad) {</div><div class='ctx'> 		/* The output format can't be modified. */</div><div class='hunk'>@@ -404,18 +374,18 @@ int vsp1_subdev_set_pad_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 	fmt-&gt;format = *format;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format to the source pad. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(entity, config, entity-&gt;source_pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(entity, state, entity-&gt;source_pad);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset the crop and compose rectangles. */</div><div class='del'>-	selection = vsp1_entity_get_pad_selection(entity, config, fmt-&gt;pad,</div><div class='add'>+	selection = vsp1_entity_get_pad_selection(entity, state, fmt-&gt;pad,</div><div class='ctx'> 						  V4L2_SEL_TGT_CROP);</div><div class='ctx'> 	selection-&gt;left = 0;</div><div class='ctx'> 	selection-&gt;top = 0;</div><div class='ctx'> 	selection-&gt;width = format-&gt;width;</div><div class='ctx'> 	selection-&gt;height = format-&gt;height;</div><div class='ctx'> </div><div class='del'>-	selection = vsp1_entity_get_pad_selection(entity, config, fmt-&gt;pad,</div><div class='add'>+	selection = vsp1_entity_get_pad_selection(entity, state, fmt-&gt;pad,</div><div class='ctx'> 						  V4L2_SEL_TGT_COMPOSE);</div><div class='ctx'> 	selection-&gt;left = 0;</div><div class='ctx'> 	selection-&gt;top = 0;</div><div class='hunk'>@@ -427,6 +397,29 @@ done:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int vsp1_entity_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	unsigned int pad;</div><div class='add'>+</div><div class='add'>+	/* Initialize all pad formats with default values. */</div><div class='add'>+	for (pad = 0; pad &lt; subdev-&gt;entity.num_pads - 1; ++pad) {</div><div class='add'>+		struct v4l2_subdev_format format = {</div><div class='add'>+			.pad = pad,</div><div class='add'>+			.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY</div><div class='add'>+			       : V4L2_SUBDEV_FORMAT_ACTIVE,</div><div class='add'>+		};</div><div class='add'>+</div><div class='add'>+		v4l2_subdev_call(subdev, pad, set_fmt, sd_state, &amp;format);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops vsp1_entity_internal_ops = {</div><div class='add'>+	.init_state = vsp1_entity_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Media Operations</div><div class='ctx'>  */</div><div class='hunk'>@@ -661,6 +654,7 @@ int vsp1_entity_init(struct vsp1_device *vsp1, struct vsp1_entity *entity,</div><div class='ctx'> 	/* Initialize the V4L2 subdev. */</div><div class='ctx'> 	subdev = &amp;entity-&gt;subdev;</div><div class='ctx'> 	v4l2_subdev_init(subdev, ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;vsp1_entity_internal_ops;</div><div class='ctx'> </div><div class='ctx'> 	subdev-&gt;entity.function = function;</div><div class='ctx'> 	subdev-&gt;entity.ops = &amp;vsp1-&gt;media_ops;</div><div class='hunk'>@@ -669,21 +663,21 @@ int vsp1_entity_init(struct vsp1_device *vsp1, struct vsp1_entity *entity,</div><div class='ctx'> 	snprintf(subdev-&gt;name, sizeof(subdev-&gt;name), "%s %s",</div><div class='ctx'> 		 dev_name(vsp1-&gt;dev), name);</div><div class='ctx'> </div><div class='del'>-	vsp1_entity_init_cfg(subdev, NULL);</div><div class='add'>+	vsp1_entity_init_state(subdev, NULL);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Allocate the pad configuration to store formats and selection</div><div class='add'>+	 * Allocate the subdev state to store formats and selection</div><div class='ctx'> 	 * rectangles.</div><div class='ctx'> 	 */</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * FIXME: Drop this call, drivers are not supposed to use</div><div class='ctx'> 	 * __v4l2_subdev_state_alloc().</div><div class='ctx'> 	 */</div><div class='del'>-	entity-&gt;config = __v4l2_subdev_state_alloc(&amp;entity-&gt;subdev,</div><div class='del'>-						   "vsp1:config-&gt;lock", &amp;key);</div><div class='del'>-	if (IS_ERR(entity-&gt;config)) {</div><div class='add'>+	entity-&gt;state = __v4l2_subdev_state_alloc(&amp;entity-&gt;subdev,</div><div class='add'>+						  "vsp1:state-&gt;lock", &amp;key);</div><div class='add'>+	if (IS_ERR(entity-&gt;state)) {</div><div class='ctx'> 		media_entity_cleanup(&amp;entity-&gt;subdev.entity);</div><div class='del'>-		return PTR_ERR(entity-&gt;config);</div><div class='add'>+		return PTR_ERR(entity-&gt;state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -695,6 +689,6 @@ void vsp1_entity_destroy(struct vsp1_entity *entity)</div><div class='ctx'> 		entity-&gt;ops-&gt;destroy(entity);</div><div class='ctx'> 	if (entity-&gt;subdev.ctrl_handler)</div><div class='ctx'> 		v4l2_ctrl_handler_free(entity-&gt;subdev.ctrl_handler);</div><div class='del'>-	__v4l2_subdev_state_free(entity-&gt;config);</div><div class='add'>+	__v4l2_subdev_state_free(entity-&gt;state);</div><div class='ctx'> 	media_entity_cleanup(&amp;entity-&gt;subdev.entity);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_entity.h b/drivers/media/platform/renesas/vsp1/vsp1_entity.h<br/>index 17f98a6a972e..735f32dde4b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_entity.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_entity.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_entity.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_entity.h</a></div><div class='hunk'>@@ -115,9 +115,9 @@ struct vsp1_entity {</div><div class='ctx'> 	unsigned int sink_pad;</div><div class='ctx'> </div><div class='ctx'> 	struct v4l2_subdev subdev;</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> </div><div class='del'>-	struct mutex lock;	/* Protects the pad config */</div><div class='add'>+	struct mutex lock;	/* Protects the state */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct vsp1_entity *to_vsp1_entity(struct v4l2_subdev *subdev)</div><div class='hunk'>@@ -135,9 +135,9 @@ int vsp1_entity_link_setup(struct media_entity *entity,</div><div class='ctx'> 			   const struct media_pad *remote, u32 flags);</div><div class='ctx'> </div><div class='ctx'> struct v4l2_subdev_state *</div><div class='del'>-vsp1_entity_get_pad_config(struct vsp1_entity *entity,</div><div class='del'>-			   struct v4l2_subdev_state *sd_state,</div><div class='del'>-			   enum v4l2_subdev_format_whence which);</div><div class='add'>+vsp1_entity_get_state(struct vsp1_entity *entity,</div><div class='add'>+		      struct v4l2_subdev_state *sd_state,</div><div class='add'>+		      enum v4l2_subdev_format_whence which);</div><div class='ctx'> struct v4l2_mbus_framefmt *</div><div class='ctx'> vsp1_entity_get_pad_format(struct vsp1_entity *entity,</div><div class='ctx'> 			   struct v4l2_subdev_state *sd_state,</div><div class='hunk'>@@ -146,8 +146,6 @@ struct v4l2_rect *</div><div class='ctx'> vsp1_entity_get_pad_selection(struct vsp1_entity *entity,</div><div class='ctx'> 			      struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 			      unsigned int pad, unsigned int target);</div><div class='del'>-int vsp1_entity_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-			 struct v4l2_subdev_state *sd_state);</div><div class='ctx'> </div><div class='ctx'> void vsp1_entity_route_setup(struct vsp1_entity *entity,</div><div class='ctx'> 			     struct vsp1_pipeline *pipe,</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_hgo.c b/drivers/media/platform/renesas/vsp1/vsp1_hgo.c<br/>index e6492deb0a64..40c571a987ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hgo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_hgo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hgo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hgo.c</a></div><div class='hunk'>@@ -140,9 +140,9 @@ static void hgo_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	unsigned int hratio;</div><div class='ctx'> 	unsigned int vratio;</div><div class='ctx'> </div><div class='del'>-	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;config,</div><div class='add'>+	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;state,</div><div class='ctx'> 					     HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);</div><div class='del'>-	compose = vsp1_entity_get_pad_selection(entity, entity-&gt;config,</div><div class='add'>+	compose = vsp1_entity_get_pad_selection(entity, entity-&gt;state,</div><div class='ctx'> 						HISTO_PAD_SINK,</div><div class='ctx'> 						V4L2_SEL_TGT_COMPOSE);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_hgt.c b/drivers/media/platform/renesas/vsp1/vsp1_hgt.c<br/>index aa1c718e0453..8281b86874ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hgt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_hgt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hgt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hgt.c</a></div><div class='hunk'>@@ -139,9 +139,9 @@ static void hgt_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	u8 upper;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;config,</div><div class='add'>+	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;state,</div><div class='ctx'> 					     HISTO_PAD_SINK, V4L2_SEL_TGT_CROP);</div><div class='del'>-	compose = vsp1_entity_get_pad_selection(entity, entity-&gt;config,</div><div class='add'>+	compose = vsp1_entity_get_pad_selection(entity, entity-&gt;state,</div><div class='ctx'> 						HISTO_PAD_SINK,</div><div class='ctx'> 						V4L2_SEL_TGT_COMPOSE);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_histo.c b/drivers/media/platform/renesas/vsp1/vsp1_histo.c<br/>index f22449dd654c..71155282ca11 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_histo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_histo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_histo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_histo.c</a></div><div class='hunk'>@@ -203,7 +203,7 @@ static int histo_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_histogram *histo = subdev_to_histo(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -213,9 +213,8 @@ static int histo_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;histo-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;histo-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;histo-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -223,7 +222,7 @@ static int histo_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE_DEFAULT:</div><div class='del'>-		crop = vsp1_entity_get_pad_selection(&amp;histo-&gt;entity, config,</div><div class='add'>+		crop = vsp1_entity_get_pad_selection(&amp;histo-&gt;entity, state,</div><div class='ctx'> 						     HISTO_PAD_SINK,</div><div class='ctx'> 						     V4L2_SEL_TGT_CROP);</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='hunk'>@@ -234,7 +233,7 @@ static int histo_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='del'>-		format = vsp1_entity_get_pad_format(&amp;histo-&gt;entity, config,</div><div class='add'>+		format = vsp1_entity_get_pad_format(&amp;histo-&gt;entity, state,</div><div class='ctx'> 						    HISTO_PAD_SINK);</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='ctx'> 		sel-&gt;r.top = 0;</div><div class='hunk'>@@ -244,7 +243,7 @@ static int histo_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *vsp1_entity_get_pad_selection(&amp;histo-&gt;entity, config,</div><div class='add'>+		sel-&gt;r = *vsp1_entity_get_pad_selection(&amp;histo-&gt;entity, state,</div><div class='ctx'> 							sel-&gt;pad, sel-&gt;target);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='hunk'>@@ -346,7 +345,7 @@ static int histo_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_histogram *histo = subdev_to_histo(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;pad != HISTO_PAD_SINK)</div><div class='hunk'>@@ -354,17 +353,16 @@ static int histo_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;histo-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;histo-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;histo-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;target == V4L2_SEL_TGT_CROP)</div><div class='del'>-		ret = histo_set_crop(subdev, config, sel);</div><div class='add'>+		ret = histo_set_crop(subdev, state, sel);</div><div class='ctx'> 	else if (sel-&gt;target == V4L2_SEL_TGT_COMPOSE)</div><div class='del'>-		ret = histo_set_compose(subdev, config, sel);</div><div class='add'>+		ret = histo_set_compose(subdev, state, sel);</div><div class='ctx'> 	else</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_hsit.c b/drivers/media/platform/renesas/vsp1/vsp1_hsit.c<br/>index 361a870380c2..bc1299c29ac9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hsit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_hsit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_hsit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_hsit.c</a></div><div class='hunk'>@@ -66,20 +66,19 @@ static int hsit_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			   struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_hsit *hsit = to_hsit(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hsit-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;hsit-&gt;entity, sd_state,</div><div class='del'>-					    fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;hsit-&gt;entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;hsit-&gt;entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;hsit-&gt;entity, state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == HSIT_PAD_SOURCE) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -102,7 +101,7 @@ static int hsit_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 	fmt-&gt;format = *format;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format to the source pad. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;hsit-&gt;entity, config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;hsit-&gt;entity, state,</div><div class='ctx'> 					    HSIT_PAD_SOURCE);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> 	format-&gt;code = hsit-&gt;inverse ? MEDIA_BUS_FMT_ARGB8888_1X32</div><div class='hunk'>@@ -114,7 +113,6 @@ done:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops hsit_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = hsit_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = hsit_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_lif.c b/drivers/media/platform/renesas/vsp1/vsp1_lif.c<br/>index 0ab2e0c70474..b1d21a54837b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_lif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_lif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_lif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_lif.c</a></div><div class='hunk'>@@ -68,7 +68,6 @@ static int lif_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops lif_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = lif_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = lif_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -94,7 +93,7 @@ static void lif_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	unsigned int obth;</div><div class='ctx'> 	unsigned int lbth;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;lif-&gt;entity, lif-&gt;entity.config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;lif-&gt;entity, lif-&gt;entity.state,</div><div class='ctx'> 					    LIF_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	switch (entity-&gt;vsp1-&gt;version &amp; VI6_IP_VERSION_MODEL_MASK) {</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_lut.c b/drivers/media/platform/renesas/vsp1/vsp1_lut.c<br/>index ac6802a325f5..451d24ab0b56 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_lut.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_lut.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_lut.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_lut.c</a></div><div class='hunk'>@@ -131,7 +131,6 @@ static int lut_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops lut_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = lut_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = lut_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_pipe.c b/drivers/media/platform/renesas/vsp1/vsp1_pipe.c<br/>index f8093ba9539e..68d05243c3ee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_pipe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_pipe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_pipe.c</a></div><div class='hunk'>@@ -373,7 +373,7 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)</div><div class='ctx'> 			   (7 &lt;&lt; VI6_DPR_SMPPT_TGW_SHIFT) |</div><div class='ctx'> 			   (VI6_DPR_NODE_UNUSED &lt;&lt; VI6_DPR_SMPPT_PT_SHIFT));</div><div class='ctx'> </div><div class='del'>-	v4l2_subdev_call(&amp;pipe-&gt;output-&gt;entity.subdev, video, s_stream, 0);</div><div class='add'>+	vsp1_wpf_stop(pipe-&gt;output);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_rpf.c b/drivers/media/platform/renesas/vsp1/vsp1_rpf.c<br/>index 3b17f5fa4067..c47579efc65f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rpf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_rpf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rpf.c</a></div><div class='hunk'>@@ -44,14 +44,6 @@ static inline void vsp1_rpf_write(struct vsp1_rwpf *rpf,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='del'>- * V4L2 Subdevice Operations</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static const struct v4l2_subdev_ops rpf_ops = {</div><div class='del'>-	.pad    = &amp;vsp1_rwpf_pad_ops,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* -----------------------------------------------------------------------------</div><div class='ctx'>  * VSP1 Entity Operations</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -89,10 +81,10 @@ static void rpf_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> </div><div class='ctx'> 	/* Format */</div><div class='ctx'> 	sink_format = vsp1_entity_get_pad_format(&amp;rpf-&gt;entity,</div><div class='del'>-						 rpf-&gt;entity.config,</div><div class='add'>+						 rpf-&gt;entity.state,</div><div class='ctx'> 						 RWPF_PAD_SINK);</div><div class='ctx'> 	source_format = vsp1_entity_get_pad_format(&amp;rpf-&gt;entity,</div><div class='del'>-						   rpf-&gt;entity.config,</div><div class='add'>+						   rpf-&gt;entity.state,</div><div class='ctx'> 						   RWPF_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	infmt = VI6_RPF_INFMT_CIPM</div><div class='hunk'>@@ -166,7 +158,7 @@ static void rpf_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 		const struct v4l2_rect *compose;</div><div class='ctx'> </div><div class='ctx'> 		compose = vsp1_entity_get_pad_selection(pipe-&gt;brx,</div><div class='del'>-							pipe-&gt;brx-&gt;config,</div><div class='add'>+							pipe-&gt;brx-&gt;state,</div><div class='ctx'> 							rpf-&gt;brx_input,</div><div class='ctx'> 							V4L2_SEL_TGT_COMPOSE);</div><div class='ctx'> 		left = compose-&gt;left;</div><div class='hunk'>@@ -310,7 +302,7 @@ static void rpf_configure_partition(struct vsp1_entity *entity,</div><div class='ctx'> 	 * offsets are needed, as planes 2 and 3 always have identical</div><div class='ctx'> 	 * strides.</div><div class='ctx'> 	 */</div><div class='del'>-	crop = *vsp1_rwpf_get_crop(rpf, rpf-&gt;entity.config);</div><div class='add'>+	crop = *vsp1_rwpf_get_crop(rpf, rpf-&gt;entity.state);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Partition Algorithm Control</div><div class='hunk'>@@ -411,7 +403,7 @@ struct vsp1_rwpf *vsp1_rpf_create(struct vsp1_device *vsp1, unsigned int index)</div><div class='ctx'> 	rpf-&gt;entity.index = index;</div><div class='ctx'> </div><div class='ctx'> 	sprintf(name, "rpf.%u", index);</div><div class='del'>-	ret = vsp1_entity_init(vsp1, &amp;rpf-&gt;entity, name, 2, &amp;rpf_ops,</div><div class='add'>+	ret = vsp1_entity_init(vsp1, &amp;rpf-&gt;entity, name, 2, &amp;vsp1_rwpf_subdev_ops,</div><div class='ctx'> 			       MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_rwpf.c b/drivers/media/platform/renesas/vsp1/vsp1_rwpf.c<br/>index 22a82d218152..09fb6ffa14e2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rwpf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rwpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.c</a></div><div class='hunk'>@@ -19,12 +19,11 @@</div><div class='ctx'> struct v4l2_rect *vsp1_rwpf_get_crop(struct vsp1_rwpf *rwpf,</div><div class='ctx'> 				     struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='del'>-	return v4l2_subdev_get_try_crop(&amp;rwpf-&gt;entity.subdev, sd_state,</div><div class='del'>-					RWPF_PAD_SINK);</div><div class='add'>+	return v4l2_subdev_state_get_crop(sd_state, RWPF_PAD_SINK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='del'>- * V4L2 Subdevice Pad Operations</div><div class='add'>+ * V4L2 Subdevice Operations</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static int vsp1_rwpf_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='hunk'>@@ -62,15 +61,14 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 				struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_rwpf *rwpf = to_rwpf(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;rwpf-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;rwpf-&gt;entity, sd_state,</div><div class='del'>-					    fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;rwpf-&gt;entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -81,7 +79,7 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 	    fmt-&gt;format.code != MEDIA_BUS_FMT_AYUV8_1X32)</div><div class='ctx'> 		fmt-&gt;format.code = MEDIA_BUS_FMT_AYUV8_1X32;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, state, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == RWPF_PAD_SOURCE) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -107,7 +105,7 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 		struct v4l2_rect *crop;</div><div class='ctx'> </div><div class='ctx'> 		/* Update the sink crop rectangle. */</div><div class='del'>-		crop = vsp1_rwpf_get_crop(rwpf, config);</div><div class='add'>+		crop = vsp1_rwpf_get_crop(rwpf, state);</div><div class='ctx'> 		crop-&gt;left = 0;</div><div class='ctx'> 		crop-&gt;top = 0;</div><div class='ctx'> 		crop-&gt;width = fmt-&gt;format.width;</div><div class='hunk'>@@ -115,7 +113,7 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format to the source pad. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, state,</div><div class='ctx'> 					    RWPF_PAD_SOURCE);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='hunk'>@@ -134,7 +132,7 @@ static int vsp1_rwpf_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 				   struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_rwpf *rwpf = to_rwpf(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -147,20 +145,19 @@ static int vsp1_rwpf_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;rwpf-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;rwpf-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;rwpf-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *vsp1_rwpf_get_crop(rwpf, config);</div><div class='add'>+		sel-&gt;r = *vsp1_rwpf_get_crop(rwpf, state);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='del'>-		format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, config,</div><div class='add'>+		format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, state,</div><div class='ctx'> 						    RWPF_PAD_SINK);</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='ctx'> 		sel-&gt;r.top = 0;</div><div class='hunk'>@@ -183,7 +180,7 @@ static int vsp1_rwpf_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 				   struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_rwpf *rwpf = to_rwpf(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *crop;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -200,15 +197,14 @@ static int vsp1_rwpf_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;rwpf-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;rwpf-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;rwpf-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Make sure the crop rectangle is entirely contained in the image. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, state,</div><div class='ctx'> 					    RWPF_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -229,11 +225,11 @@ static int vsp1_rwpf_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	sel-&gt;r.height = min_t(unsigned int, sel-&gt;r.height,</div><div class='ctx'> 			      format-&gt;height - sel-&gt;r.top);</div><div class='ctx'> </div><div class='del'>-	crop = vsp1_rwpf_get_crop(rwpf, config);</div><div class='add'>+	crop = vsp1_rwpf_get_crop(rwpf, state);</div><div class='ctx'> 	*crop = sel-&gt;r;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format to the source pad. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, config,</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;rwpf-&gt;entity, state,</div><div class='ctx'> 					    RWPF_PAD_SOURCE);</div><div class='ctx'> 	format-&gt;width = crop-&gt;width;</div><div class='ctx'> 	format-&gt;height = crop-&gt;height;</div><div class='hunk'>@@ -243,8 +239,7 @@ done:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const struct v4l2_subdev_pad_ops vsp1_rwpf_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='add'>+static const struct v4l2_subdev_pad_ops vsp1_rwpf_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = vsp1_rwpf_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = vsp1_rwpf_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -253,6 +248,10 @@ const struct v4l2_subdev_pad_ops vsp1_rwpf_pad_ops = {</div><div class='ctx'> 	.set_selection = vsp1_rwpf_set_selection,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+const struct v4l2_subdev_ops vsp1_rwpf_subdev_ops = {</div><div class='add'>+	.pad    = &amp;vsp1_rwpf_pad_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='ctx'>  * Controls</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_rwpf.h b/drivers/media/platform/renesas/vsp1/vsp1_rwpf.h<br/>index eac5c04c2239..e0d212c70b2f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rwpf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_rwpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_rwpf.h</a></div><div class='hunk'>@@ -79,9 +79,11 @@ static inline struct vsp1_rwpf *entity_to_rwpf(struct vsp1_entity *entity)</div><div class='ctx'> struct vsp1_rwpf *vsp1_rpf_create(struct vsp1_device *vsp1, unsigned int index);</div><div class='ctx'> struct vsp1_rwpf *vsp1_wpf_create(struct vsp1_device *vsp1, unsigned int index);</div><div class='ctx'> </div><div class='add'>+void vsp1_wpf_stop(struct vsp1_rwpf *wpf);</div><div class='add'>+</div><div class='ctx'> int vsp1_rwpf_init_ctrls(struct vsp1_rwpf *rwpf, unsigned int ncontrols);</div><div class='ctx'> </div><div class='del'>-extern const struct v4l2_subdev_pad_ops vsp1_rwpf_pad_ops;</div><div class='add'>+extern const struct v4l2_subdev_ops vsp1_rwpf_subdev_ops;</div><div class='ctx'> </div><div class='ctx'> struct v4l2_rect *vsp1_rwpf_get_crop(struct vsp1_rwpf *rwpf,</div><div class='ctx'> 				     struct v4l2_subdev_state *sd_state);</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_sru.c b/drivers/media/platform/renesas/vsp1/vsp1_sru.c<br/>index b614a2aea461..11e008aa9f20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_sru.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_sru.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_sru.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_sru.c</a></div><div class='hunk'>@@ -123,16 +123,15 @@ static int sru_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       struct v4l2_subdev_frame_size_enum *fse)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_sru *sru = to_sru(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;sru-&gt;entity, sd_state,</div><div class='del'>-					    fse-&gt;which);</div><div class='del'>-	if (!config)</div><div class='add'>+	state = vsp1_entity_get_state(&amp;sru-&gt;entity, sd_state, fse-&gt;which);</div><div class='add'>+	if (!state)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, config, SRU_PAD_SINK);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, state, SRU_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;sru-&gt;entity.lock);</div><div class='ctx'> </div><div class='hunk'>@@ -221,31 +220,30 @@ static int sru_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			  struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_sru *sru = to_sru(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;sru-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;sru-&gt;entity, sd_state,</div><div class='del'>-					    fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;sru-&gt;entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sru_try_format(sru, config, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='add'>+	sru_try_format(sru, state, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, state, fmt-&gt;pad);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == SRU_PAD_SINK) {</div><div class='ctx'> 		/* Propagate the format to the source pad. */</div><div class='del'>-		format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, config,</div><div class='add'>+		format = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, state,</div><div class='ctx'> 						    SRU_PAD_SOURCE);</div><div class='ctx'> 		*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='del'>-		sru_try_format(sru, config, SRU_PAD_SOURCE, format);</div><div class='add'>+		sru_try_format(sru, state, SRU_PAD_SOURCE, format);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> done:</div><div class='hunk'>@@ -254,7 +252,6 @@ done:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops sru_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = sru_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = sru_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -280,9 +277,9 @@ static void sru_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *output;</div><div class='ctx'> 	u32 ctrl0;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					   SRU_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					    SRU_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	if (input-&gt;code == MEDIA_BUS_FMT_ARGB8888_1X32)</div><div class='hunk'>@@ -310,9 +307,9 @@ static unsigned int sru_max_width(struct vsp1_entity *entity,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *input;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *output;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					   SRU_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					    SRU_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -336,9 +333,9 @@ static void sru_partition(struct vsp1_entity *entity,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *input;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *output;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					   SRU_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;sru-&gt;entity, sru-&gt;entity.state,</div><div class='ctx'> 					    SRU_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	/* Adapt if SRUx2 is enabled. */</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_uds.c b/drivers/media/platform/renesas/vsp1/vsp1_uds.c<br/>index 1c290cda005a..d89f1197b86c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_uds.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_uds.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_uds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_uds.c</a></div><div class='hunk'>@@ -128,17 +128,15 @@ static int uds_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> 			       struct v4l2_subdev_frame_size_enum *fse)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_uds *uds = to_uds(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;uds-&gt;entity, sd_state,</div><div class='del'>-					    fse-&gt;which);</div><div class='del'>-	if (!config)</div><div class='add'>+	state = vsp1_entity_get_state(&amp;uds-&gt;entity, sd_state, fse-&gt;which);</div><div class='add'>+	if (!state)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, config,</div><div class='del'>-					    UDS_PAD_SINK);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, state, UDS_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;uds-&gt;entity.lock);</div><div class='ctx'> </div><div class='hunk'>@@ -205,31 +203,30 @@ static int uds_set_format(struct v4l2_subdev *subdev,</div><div class='ctx'> 			  struct v4l2_subdev_format *fmt)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_uds *uds = to_uds(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;uds-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;uds-&gt;entity, sd_state,</div><div class='del'>-					    fmt-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;uds-&gt;entity, sd_state, fmt-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	uds_try_format(uds, config, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='add'>+	uds_try_format(uds, state, fmt-&gt;pad, &amp;fmt-&gt;format);</div><div class='ctx'> </div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, config, fmt-&gt;pad);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, state, fmt-&gt;pad);</div><div class='ctx'> 	*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;pad == UDS_PAD_SINK) {</div><div class='ctx'> 		/* Propagate the format to the source pad. */</div><div class='del'>-		format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, config,</div><div class='add'>+		format = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, state,</div><div class='ctx'> 						    UDS_PAD_SOURCE);</div><div class='ctx'> 		*format = fmt-&gt;format;</div><div class='ctx'> </div><div class='del'>-		uds_try_format(uds, config, UDS_PAD_SOURCE, format);</div><div class='add'>+		uds_try_format(uds, state, UDS_PAD_SOURCE, format);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> done:</div><div class='hunk'>@@ -242,7 +239,6 @@ done:</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops uds_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = uds_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = uds_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -269,9 +265,9 @@ static void uds_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	unsigned int vscale;</div><div class='ctx'> 	bool multitap;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					   UDS_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					    UDS_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	hscale = uds_compute_ratio(input-&gt;width, output-&gt;width);</div><div class='hunk'>@@ -314,7 +310,7 @@ static void uds_configure_partition(struct vsp1_entity *entity,</div><div class='ctx'> 	struct vsp1_partition *partition = pipe-&gt;partition;</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *output;</div><div class='ctx'> </div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					    UDS_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	/* Input size clipping. */</div><div class='hunk'>@@ -339,9 +335,9 @@ static unsigned int uds_max_width(struct vsp1_entity *entity,</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *input;</div><div class='ctx'> 	unsigned int hscale;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					   UDS_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					    UDS_PAD_SOURCE);</div><div class='ctx'> 	hscale = output-&gt;width / input-&gt;width;</div><div class='ctx'> </div><div class='hunk'>@@ -381,9 +377,9 @@ static void uds_partition(struct vsp1_entity *entity,</div><div class='ctx'> 	partition-&gt;uds_sink = *window;</div><div class='ctx'> 	partition-&gt;uds_source = *window;</div><div class='ctx'> </div><div class='del'>-	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	input = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					   UDS_PAD_SINK);</div><div class='del'>-	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.config,</div><div class='add'>+	output = vsp1_entity_get_pad_format(&amp;uds-&gt;entity, uds-&gt;entity.state,</div><div class='ctx'> 					    UDS_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	partition-&gt;uds_sink.width = window-&gt;width * input-&gt;width</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_uif.c b/drivers/media/platform/renesas/vsp1/vsp1_uif.c<br/>index 83d7f17df80e..f66936a28a2a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_uif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_uif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_uif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_uif.c</a></div><div class='hunk'>@@ -86,7 +86,7 @@ static int uif_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			     struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_uif *uif = to_uif(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -95,9 +95,8 @@ static int uif_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;uif-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;uif-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;uif-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -105,7 +104,7 @@ static int uif_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='del'>-		format = vsp1_entity_get_pad_format(&amp;uif-&gt;entity, config,</div><div class='add'>+		format = vsp1_entity_get_pad_format(&amp;uif-&gt;entity, state,</div><div class='ctx'> 						    UIF_PAD_SINK);</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='ctx'> 		sel-&gt;r.top = 0;</div><div class='hunk'>@@ -114,7 +113,7 @@ static int uif_get_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *vsp1_entity_get_pad_selection(&amp;uif-&gt;entity, config,</div><div class='add'>+		sel-&gt;r = *vsp1_entity_get_pad_selection(&amp;uif-&gt;entity, state,</div><div class='ctx'> 							sel-&gt;pad, sel-&gt;target);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='hunk'>@@ -133,7 +132,7 @@ static int uif_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 			     struct v4l2_subdev_selection *sel)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_uif *uif = to_uif(subdev);</div><div class='del'>-	struct v4l2_subdev_state *config;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> 	struct v4l2_rect *selection;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -144,15 +143,14 @@ static int uif_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;uif-&gt;entity.lock);</div><div class='ctx'> </div><div class='del'>-	config = vsp1_entity_get_pad_config(&amp;uif-&gt;entity, sd_state,</div><div class='del'>-					    sel-&gt;which);</div><div class='del'>-	if (!config) {</div><div class='add'>+	state = vsp1_entity_get_state(&amp;uif-&gt;entity, sd_state, sel-&gt;which);</div><div class='add'>+	if (!state) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto done;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* The crop rectangle must be inside the input frame. */</div><div class='del'>-	format = vsp1_entity_get_pad_format(&amp;uif-&gt;entity, config, UIF_PAD_SINK);</div><div class='add'>+	format = vsp1_entity_get_pad_format(&amp;uif-&gt;entity, state, UIF_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	sel-&gt;r.left = clamp_t(unsigned int, sel-&gt;r.left, 0, format-&gt;width - 1);</div><div class='ctx'> 	sel-&gt;r.top = clamp_t(unsigned int, sel-&gt;r.top, 0, format-&gt;height - 1);</div><div class='hunk'>@@ -162,7 +160,7 @@ static int uif_set_selection(struct v4l2_subdev *subdev,</div><div class='ctx'> 				format-&gt;height - sel-&gt;r.top);</div><div class='ctx'> </div><div class='ctx'> 	/* Store the crop rectangle. */</div><div class='del'>-	selection = vsp1_entity_get_pad_selection(&amp;uif-&gt;entity, config,</div><div class='add'>+	selection = vsp1_entity_get_pad_selection(&amp;uif-&gt;entity, state,</div><div class='ctx'> 						  sel-&gt;pad, V4L2_SEL_TGT_CROP);</div><div class='ctx'> 	*selection = sel-&gt;r;</div><div class='ctx'> </div><div class='hunk'>@@ -176,7 +174,6 @@ done:</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops uif_pad_ops = {</div><div class='del'>-	.init_cfg = vsp1_entity_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = uif_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = uif_enum_frame_size,</div><div class='ctx'> 	.get_fmt = vsp1_subdev_get_pad_format,</div><div class='hunk'>@@ -206,7 +203,7 @@ static void uif_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	vsp1_uif_write(uif, dlb, VI6_UIF_DISCOM_DOCMPMR,</div><div class='ctx'> 		       VI6_UIF_DISCOM_DOCMPMR_SEL(9));</div><div class='ctx'> </div><div class='del'>-	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;config,</div><div class='add'>+	crop = vsp1_entity_get_pad_selection(entity, entity-&gt;state,</div><div class='ctx'> 					     UIF_PAD_SINK, V4L2_SEL_TGT_CROP);</div><div class='ctx'> </div><div class='ctx'> 	left = crop-&gt;left;</div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_video.c b/drivers/media/platform/renesas/vsp1/vsp1_video.c<br/>index e9d5027761bb..5a9cb0e5640e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_video.c</a></div><div class='hunk'>@@ -198,7 +198,7 @@ static void vsp1_video_calculate_partition(struct vsp1_pipeline *pipe,</div><div class='ctx'> 	 * at the WPF sink.</div><div class='ctx'> 	 */</div><div class='ctx'> 	format = vsp1_entity_get_pad_format(&amp;pipe-&gt;output-&gt;entity,</div><div class='del'>-					    pipe-&gt;output-&gt;entity.config,</div><div class='add'>+					    pipe-&gt;output-&gt;entity.state,</div><div class='ctx'> 					    RWPF_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	/* A single partition simply processes the output size in full. */</div><div class='hunk'>@@ -263,7 +263,7 @@ static int vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe)</div><div class='ctx'> 	 * at the WPF sink.</div><div class='ctx'> 	 */</div><div class='ctx'> 	format = vsp1_entity_get_pad_format(&amp;pipe-&gt;output-&gt;entity,</div><div class='del'>-					    pipe-&gt;output-&gt;entity.config,</div><div class='add'>+					    pipe-&gt;output-&gt;entity.state,</div><div class='ctx'> 					    RWPF_PAD_SINK);</div><div class='ctx'> 	div_size = format-&gt;width;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/renesas/vsp1/vsp1_wpf.c b/drivers/media/platform/renesas/vsp1/vsp1_wpf.c<br/>index d0074ca00920..9693aeab1cac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_wpf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/renesas/vsp1/vsp1_wpf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/renesas/vsp1/vsp1_wpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/renesas/vsp1/vsp1_wpf.c</a></div><div class='hunk'>@@ -66,10 +66,10 @@ static int vsp1_wpf_set_rotation(struct vsp1_rwpf *wpf, unsigned int rotation)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	sink_format = vsp1_entity_get_pad_format(&amp;wpf-&gt;entity,</div><div class='del'>-						 wpf-&gt;entity.config,</div><div class='add'>+						 wpf-&gt;entity.state,</div><div class='ctx'> 						 RWPF_PAD_SINK);</div><div class='ctx'> 	source_format = vsp1_entity_get_pad_format(&amp;wpf-&gt;entity,</div><div class='del'>-						   wpf-&gt;entity.config,</div><div class='add'>+						   wpf-&gt;entity.state,</div><div class='ctx'> 						   RWPF_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;wpf-&gt;entity.lock);</div><div class='hunk'>@@ -186,17 +186,13 @@ static int wpf_init_controls(struct vsp1_rwpf *wpf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* -----------------------------------------------------------------------------</div><div class='del'>- * V4L2 Subdevice Core Operations</div><div class='add'>+ * VSP1 Entity Operations</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-static int wpf_s_stream(struct v4l2_subdev *subdev, int enable)</div><div class='add'>+void vsp1_wpf_stop(struct vsp1_rwpf *wpf)</div><div class='ctx'> {</div><div class='del'>-	struct vsp1_rwpf *wpf = to_rwpf(subdev);</div><div class='ctx'> 	struct vsp1_device *vsp1 = wpf-&gt;entity.vsp1;</div><div class='ctx'> </div><div class='del'>-	if (enable)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Write to registers directly when stopping the stream as there will be</div><div class='ctx'> 	 * no pipeline run to apply the display list.</div><div class='hunk'>@@ -204,27 +200,8 @@ static int wpf_s_stream(struct v4l2_subdev *subdev, int enable)</div><div class='ctx'> 	vsp1_write(vsp1, VI6_WPF_IRQ_ENB(wpf-&gt;entity.index), 0);</div><div class='ctx'> 	vsp1_write(vsp1, wpf-&gt;entity.index * VI6_WPF_OFFSET +</div><div class='ctx'> 		   VI6_WPF_SRCRPF, 0);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* -----------------------------------------------------------------------------</div><div class='del'>- * V4L2 Subdevice Operations</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static const struct v4l2_subdev_video_ops wpf_video_ops = {</div><div class='del'>-	.s_stream = wpf_s_stream,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct v4l2_subdev_ops wpf_ops = {</div><div class='del'>-	.video	= &amp;wpf_video_ops,</div><div class='del'>-	.pad    = &amp;vsp1_rwpf_pad_ops,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* -----------------------------------------------------------------------------</div><div class='del'>- * VSP1 Entity Operations</div><div class='del'>- */</div><div class='del'>-</div><div class='ctx'> static void vsp1_wpf_destroy(struct vsp1_entity *entity)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsp1_rwpf *wpf = entity_to_rwpf(entity);</div><div class='hunk'>@@ -269,10 +246,10 @@ static void wpf_configure_stream(struct vsp1_entity *entity,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	sink_format = vsp1_entity_get_pad_format(&amp;wpf-&gt;entity,</div><div class='del'>-						 wpf-&gt;entity.config,</div><div class='add'>+						 wpf-&gt;entity.state,</div><div class='ctx'> 						 RWPF_PAD_SINK);</div><div class='ctx'> 	source_format = vsp1_entity_get_pad_format(&amp;wpf-&gt;entity,</div><div class='del'>-						   wpf-&gt;entity.config,</div><div class='add'>+						   wpf-&gt;entity.state,</div><div class='ctx'> 						   RWPF_PAD_SOURCE);</div><div class='ctx'> </div><div class='ctx'> 	/* Format */</div><div class='hunk'>@@ -407,7 +384,7 @@ static void wpf_configure_partition(struct vsp1_entity *entity,</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	sink_format = vsp1_entity_get_pad_format(&amp;wpf-&gt;entity,</div><div class='del'>-						 wpf-&gt;entity.config,</div><div class='add'>+						 wpf-&gt;entity.state,</div><div class='ctx'> 						 RWPF_PAD_SINK);</div><div class='ctx'> 	width = sink_format-&gt;width;</div><div class='ctx'> 	height = sink_format-&gt;height;</div><div class='hunk'>@@ -583,7 +560,7 @@ struct vsp1_rwpf *vsp1_wpf_create(struct vsp1_device *vsp1, unsigned int index)</div><div class='ctx'> 	wpf-&gt;entity.index = index;</div><div class='ctx'> </div><div class='ctx'> 	sprintf(name, "wpf.%u", index);</div><div class='del'>-	ret = vsp1_entity_init(vsp1, &amp;wpf-&gt;entity, name, 2, &amp;wpf_ops,</div><div class='add'>+	ret = vsp1_entity_init(vsp1, &amp;wpf-&gt;entity, name, 2, &amp;vsp1_rwpf_subdev_ops,</div><div class='ctx'> 			       MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rga/rga-buf.c b/drivers/media/platform/rockchip/rga/rga-buf.c<br/>index 81508ed5abf3..662c81b6d0b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga-buf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rga/rga-buf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga-buf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga-buf.c</a></div><div class='hunk'>@@ -5,7 +5,9 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/scatterlist.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;media/v4l2-common.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-device.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-ioctl.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-mem2mem.h&gt;</div><div class='hunk'>@@ -15,6 +17,26 @@</div><div class='ctx'> #include "rga-hw.h"</div><div class='ctx'> #include "rga.h"</div><div class='ctx'> </div><div class='add'>+static ssize_t fill_descriptors(struct rga_dma_desc *desc, size_t max_desc,</div><div class='add'>+				struct sg_table *sgt)</div><div class='add'>+{</div><div class='add'>+	struct sg_dma_page_iter iter;</div><div class='add'>+	struct rga_dma_desc *tmp = desc;</div><div class='add'>+	size_t n_desc = 0;</div><div class='add'>+	dma_addr_t addr;</div><div class='add'>+</div><div class='add'>+	for_each_sgtable_dma_page(sgt, &amp;iter, 0) {</div><div class='add'>+		if (n_desc &gt; max_desc)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		addr = sg_page_iter_dma_address(&amp;iter);</div><div class='add'>+		tmp-&gt;addr = lower_32_bits(addr);</div><div class='add'>+		tmp++;</div><div class='add'>+		n_desc++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return n_desc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int</div><div class='ctx'> rga_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		unsigned int *nbuffers, unsigned int *nplanes,</div><div class='hunk'>@@ -22,28 +44,105 @@ rga_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct rga_ctx *ctx = vb2_get_drv_priv(vq);</div><div class='ctx'> 	struct rga_frame *f = rga_get_frame(ctx, vq-&gt;type);</div><div class='add'>+	const struct v4l2_pix_format_mplane *pix_fmt;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ERR(f))</div><div class='ctx'> 		return PTR_ERR(f);</div><div class='ctx'> </div><div class='del'>-	if (*nplanes)</div><div class='del'>-		return sizes[0] &lt; f-&gt;size ? -EINVAL : 0;</div><div class='add'>+	pix_fmt = &amp;f-&gt;pix;</div><div class='add'>+</div><div class='add'>+	if (*nplanes) {</div><div class='add'>+		if (*nplanes != pix_fmt-&gt;num_planes)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; pix_fmt-&gt;num_planes; i++)</div><div class='add'>+			if (sizes[i] &lt; pix_fmt-&gt;plane_fmt[i].sizeimage)</div><div class='add'>+				return -EINVAL;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	*nplanes = pix_fmt-&gt;num_planes;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pix_fmt-&gt;num_planes; i++)</div><div class='add'>+		sizes[i] = pix_fmt-&gt;plane_fmt[i].sizeimage;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rga_buf_init(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct rga_vb_buffer *rbuf = vb_to_rga(vbuf);</div><div class='add'>+	struct rga_ctx *ctx = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='add'>+	struct rga_frame *f = rga_get_frame(ctx, vb-&gt;vb2_queue-&gt;type);</div><div class='add'>+	size_t n_desc = 0;</div><div class='ctx'> </div><div class='del'>-	sizes[0] = f-&gt;size;</div><div class='del'>-	*nplanes = 1;</div><div class='add'>+	n_desc = DIV_ROUND_UP(f-&gt;size, PAGE_SIZE);</div><div class='add'>+</div><div class='add'>+	rbuf-&gt;n_desc = n_desc;</div><div class='add'>+	rbuf-&gt;dma_desc = dma_alloc_coherent(rga-&gt;dev,</div><div class='add'>+					    rbuf-&gt;n_desc * sizeof(*rbuf-&gt;dma_desc),</div><div class='add'>+					    &amp;rbuf-&gt;dma_desc_pa, GFP_KERNEL);</div><div class='add'>+	if (!rbuf-&gt;dma_desc)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int get_plane_offset(struct rga_frame *f, int plane)</div><div class='add'>+{</div><div class='add'>+	if (plane == 0)</div><div class='add'>+		return 0;</div><div class='add'>+	if (plane == 1)</div><div class='add'>+		return f-&gt;width * f-&gt;height;</div><div class='add'>+	if (plane == 2)</div><div class='add'>+		return f-&gt;width * f-&gt;height + (f-&gt;width * f-&gt;height / f-&gt;fmt-&gt;uv_factor);</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int rga_buf_prepare(struct vb2_buffer *vb)</div><div class='ctx'> {</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct rga_vb_buffer *rbuf = vb_to_rga(vbuf);</div><div class='ctx'> 	struct rga_ctx *ctx = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='ctx'> 	struct rga_frame *f = rga_get_frame(ctx, vb-&gt;vb2_queue-&gt;type);</div><div class='add'>+	ssize_t n_desc = 0;</div><div class='add'>+	size_t curr_desc = 0;</div><div class='add'>+	int i;</div><div class='add'>+	const struct v4l2_format_info *info;</div><div class='add'>+	unsigned int offsets[VIDEO_MAX_PLANES];</div><div class='ctx'> </div><div class='ctx'> 	if (IS_ERR(f))</div><div class='ctx'> 		return PTR_ERR(f);</div><div class='ctx'> </div><div class='del'>-	vb2_set_plane_payload(vb, 0, f-&gt;size);</div><div class='add'>+	for (i = 0; i &lt; vb-&gt;num_planes; i++) {</div><div class='add'>+		vb2_set_plane_payload(vb, i, f-&gt;pix.plane_fmt[i].sizeimage);</div><div class='add'>+</div><div class='add'>+		/* Create local MMU table for RGA */</div><div class='add'>+		n_desc = fill_descriptors(&amp;rbuf-&gt;dma_desc[curr_desc],</div><div class='add'>+					  rbuf-&gt;n_desc - curr_desc,</div><div class='add'>+					  vb2_dma_sg_plane_desc(vb, i));</div><div class='add'>+		if (n_desc &lt; 0) {</div><div class='add'>+			v4l2_err(&amp;ctx-&gt;rga-&gt;v4l2_dev,</div><div class='add'>+				 "Failed to map video buffer to RGA\n");</div><div class='add'>+			return n_desc;</div><div class='add'>+		}</div><div class='add'>+		offsets[i] = curr_desc &lt;&lt; PAGE_SHIFT;</div><div class='add'>+		curr_desc += n_desc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Fill the remaining planes */</div><div class='add'>+	info = v4l2_format_info(f-&gt;fmt-&gt;fourcc);</div><div class='add'>+	for (i = info-&gt;mem_planes; i &lt; info-&gt;comp_planes; i++)</div><div class='add'>+		offsets[i] = get_plane_offset(f, i);</div><div class='add'>+</div><div class='add'>+	rbuf-&gt;offset.y_off = offsets[0];</div><div class='add'>+	rbuf-&gt;offset.u_off = offsets[1];</div><div class='add'>+	rbuf-&gt;offset.v_off = offsets[2];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -56,6 +155,17 @@ static void rga_buf_queue(struct vb2_buffer *vb)</div><div class='ctx'> 	v4l2_m2m_buf_queue(ctx-&gt;fh.m2m_ctx, vbuf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void rga_buf_cleanup(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct rga_vb_buffer *rbuf = vb_to_rga(vbuf);</div><div class='add'>+	struct rga_ctx *ctx = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='add'>+</div><div class='add'>+	dma_free_coherent(rga-&gt;dev, rbuf-&gt;n_desc * sizeof(*rbuf-&gt;dma_desc),</div><div class='add'>+			  rbuf-&gt;dma_desc, rbuf-&gt;dma_desc_pa);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void rga_buf_return_buffers(struct vb2_queue *q,</div><div class='ctx'> 				   enum vb2_buffer_state state)</div><div class='ctx'> {</div><div class='hunk'>@@ -99,50 +209,12 @@ static void rga_buf_stop_streaming(struct vb2_queue *q)</div><div class='ctx'> </div><div class='ctx'> const struct vb2_ops rga_qops = {</div><div class='ctx'> 	.queue_setup = rga_queue_setup,</div><div class='add'>+	.buf_init = rga_buf_init,</div><div class='ctx'> 	.buf_prepare = rga_buf_prepare,</div><div class='ctx'> 	.buf_queue = rga_buf_queue,</div><div class='add'>+	.buf_cleanup = rga_buf_cleanup,</div><div class='ctx'> 	.wait_prepare = vb2_ops_wait_prepare,</div><div class='ctx'> 	.wait_finish = vb2_ops_wait_finish,</div><div class='ctx'> 	.start_streaming = rga_buf_start_streaming,</div><div class='ctx'> 	.stop_streaming = rga_buf_stop_streaming,</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-/* RGA MMU is a 1-Level MMU, so it can't be used through the IOMMU API.</div><div class='del'>- * We use it more like a scatter-gather list.</div><div class='del'>- */</div><div class='del'>-void rga_buf_map(struct vb2_buffer *vb)</div><div class='del'>-{</div><div class='del'>-	struct rga_ctx *ctx = vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='del'>-	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='del'>-	struct sg_table *sgt;</div><div class='del'>-	struct scatterlist *sgl;</div><div class='del'>-	unsigned int *pages;</div><div class='del'>-	unsigned int address, len, i, p;</div><div class='del'>-	unsigned int mapped_size = 0;</div><div class='del'>-</div><div class='del'>-	if (vb-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='del'>-		pages = rga-&gt;src_mmu_pages;</div><div class='del'>-	else</div><div class='del'>-		pages = rga-&gt;dst_mmu_pages;</div><div class='del'>-</div><div class='del'>-	/* Create local MMU table for RGA */</div><div class='del'>-	sgt = vb2_plane_cookie(vb, 0);</div><div class='del'>-</div><div class='del'>-	for_each_sg(sgt-&gt;sgl, sgl, sgt-&gt;nents, i) {</div><div class='del'>-		len = sg_dma_len(sgl) &gt;&gt; PAGE_SHIFT;</div><div class='del'>-		address = sg_phys(sgl);</div><div class='del'>-</div><div class='del'>-		for (p = 0; p &lt; len; p++) {</div><div class='del'>-			dma_addr_t phys = address +</div><div class='del'>-					  ((dma_addr_t)p &lt;&lt; PAGE_SHIFT);</div><div class='del'>-</div><div class='del'>-			pages[mapped_size + p] = phys;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		mapped_size += len;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* sync local MMU table for RGA */</div><div class='del'>-	dma_sync_single_for_device(rga-&gt;dev, virt_to_phys(pages),</div><div class='del'>-				   8 * PAGE_SIZE, DMA_BIDIRECTIONAL);</div><div class='del'>-}</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c<br/>index aaa96f256356..11c3d7234757 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga-hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rga/rga-hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga-hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga-hw.c</a></div><div class='hunk'>@@ -16,12 +16,6 @@ enum e_rga_start_pos {</div><div class='ctx'> 	RB = 3,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct rga_addr_offset {</div><div class='del'>-	unsigned int y_off;</div><div class='del'>-	unsigned int u_off;</div><div class='del'>-	unsigned int v_off;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct rga_corners_addr_offset {</div><div class='ctx'> 	struct rga_addr_offset left_top;</div><div class='ctx'> 	struct rga_addr_offset right_top;</div><div class='hunk'>@@ -43,13 +37,13 @@ static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct rga_corners_addr_offset</div><div class='del'>-rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,</div><div class='del'>-		    unsigned int w, unsigned int h)</div><div class='add'>+rga_get_addr_offset(struct rga_frame *frm, struct rga_addr_offset *offset,</div><div class='add'>+		    unsigned int x, unsigned int y, unsigned int w, unsigned int h)</div><div class='ctx'> {</div><div class='ctx'> 	struct rga_corners_addr_offset offsets;</div><div class='ctx'> 	struct rga_addr_offset *lt, *lb, *rt, *rb;</div><div class='ctx'> 	unsigned int x_div = 0,</div><div class='del'>-		     y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;</div><div class='add'>+		     y_div = 0, uv_stride = 0, pixel_width = 0;</div><div class='ctx'> </div><div class='ctx'> 	lt = &amp;offsets.left_top;</div><div class='ctx'> 	lb = &amp;offsets.left_bottom;</div><div class='hunk'>@@ -58,14 +52,12 @@ rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,</div><div class='ctx'> </div><div class='ctx'> 	x_div = frm-&gt;fmt-&gt;x_div;</div><div class='ctx'> 	y_div = frm-&gt;fmt-&gt;y_div;</div><div class='del'>-	uv_factor = frm-&gt;fmt-&gt;uv_factor;</div><div class='ctx'> 	uv_stride = frm-&gt;stride / x_div;</div><div class='ctx'> 	pixel_width = frm-&gt;stride / frm-&gt;width;</div><div class='ctx'> </div><div class='del'>-	lt-&gt;y_off = y * frm-&gt;stride + x * pixel_width;</div><div class='del'>-	lt-&gt;u_off =</div><div class='del'>-		frm-&gt;width * frm-&gt;height + (y / y_div) * uv_stride + x / x_div;</div><div class='del'>-	lt-&gt;v_off = lt-&gt;u_off + frm-&gt;width * frm-&gt;height / uv_factor;</div><div class='add'>+	lt-&gt;y_off = offset-&gt;y_off + y * frm-&gt;stride + x * pixel_width;</div><div class='add'>+	lt-&gt;u_off = offset-&gt;u_off + (y / y_div) * uv_stride + x / x_div;</div><div class='add'>+	lt-&gt;v_off = offset-&gt;v_off + (y / y_div) * uv_stride + x / x_div;</div><div class='ctx'> </div><div class='ctx'> 	lb-&gt;y_off = lt-&gt;y_off + (h - 1) * frm-&gt;stride;</div><div class='ctx'> 	lb-&gt;u_off = lt-&gt;u_off + (h / y_div - 1) * uv_stride;</div><div class='hunk'>@@ -119,40 +111,40 @@ static struct rga_addr_offset *rga_lookup_draw_pos(struct</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)</div><div class='add'>+static void rga_cmd_set_src_addr(struct rga_ctx *ctx, dma_addr_t dma_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> 	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='ctx'> 	unsigned int reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;</div><div class='del'>-	dest[reg &gt;&gt; 2] = virt_to_phys(mmu_pages) &gt;&gt; 4;</div><div class='add'>+	dest[reg &gt;&gt; 2] = dma_addr &gt;&gt; 4;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;</div><div class='ctx'> 	dest[reg &gt;&gt; 2] |= 0x7;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)</div><div class='add'>+static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, dma_addr_t dma_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> 	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='ctx'> 	unsigned int reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;</div><div class='del'>-	dest[reg &gt;&gt; 2] = virt_to_phys(mmu_pages) &gt;&gt; 4;</div><div class='add'>+	dest[reg &gt;&gt; 2] = dma_addr &gt;&gt; 4;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;</div><div class='ctx'> 	dest[reg &gt;&gt; 2] |= 0x7 &lt;&lt; 4;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)</div><div class='add'>+static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, dma_addr_t dma_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> 	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='ctx'> 	unsigned int reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;</div><div class='del'>-	dest[reg &gt;&gt; 2] = virt_to_phys(mmu_pages) &gt;&gt; 4;</div><div class='add'>+	dest[reg &gt;&gt; 2] = dma_addr &gt;&gt; 4;</div><div class='ctx'> </div><div class='ctx'> 	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;</div><div class='ctx'> 	dest[reg &gt;&gt; 2] |= 0x7 &lt;&lt; 8;</div><div class='hunk'>@@ -163,7 +155,7 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> 	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='ctx'> 	unsigned int scale_dst_w, scale_dst_h;</div><div class='del'>-	unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;</div><div class='add'>+	unsigned int src_h, src_w, dst_h, dst_w;</div><div class='ctx'> 	union rga_src_info src_info;</div><div class='ctx'> 	union rga_dst_info dst_info;</div><div class='ctx'> 	union rga_src_x_factor x_factor;</div><div class='hunk'>@@ -173,18 +165,10 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)</div><div class='ctx'> 	union rga_dst_vir_info dst_vir_info;</div><div class='ctx'> 	union rga_dst_act_info dst_act_info;</div><div class='ctx'> </div><div class='del'>-	struct rga_addr_offset *dst_offset;</div><div class='del'>-	struct rga_corners_addr_offset offsets;</div><div class='del'>-	struct rga_corners_addr_offset src_offsets;</div><div class='del'>-</div><div class='ctx'> 	src_h = ctx-&gt;in.crop.height;</div><div class='ctx'> 	src_w = ctx-&gt;in.crop.width;</div><div class='del'>-	src_x = ctx-&gt;in.crop.left;</div><div class='del'>-	src_y = ctx-&gt;in.crop.top;</div><div class='ctx'> 	dst_h = ctx-&gt;out.crop.height;</div><div class='ctx'> 	dst_w = ctx-&gt;out.crop.width;</div><div class='del'>-	dst_x = ctx-&gt;out.crop.left;</div><div class='del'>-	dst_y = ctx-&gt;out.crop.top;</div><div class='ctx'> </div><div class='ctx'> 	src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2];</div><div class='ctx'> 	dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2];</div><div class='hunk'>@@ -312,18 +296,37 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)</div><div class='ctx'> 	dst_act_info.data.act_height = dst_h - 1;</div><div class='ctx'> 	dst_act_info.data.act_width = dst_w - 1;</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * Calculate the source framebuffer base address with offset pixel.</div><div class='del'>-	 */</div><div class='del'>-	src_offsets = rga_get_addr_offset(&amp;ctx-&gt;in, src_x, src_y,</div><div class='del'>-					  src_w, src_h);</div><div class='add'>+	dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) &gt;&gt; 2] = x_factor.val;</div><div class='add'>+	dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) &gt;&gt; 2] = y_factor.val;</div><div class='add'>+	dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_vir_info.val;</div><div class='add'>+	dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_act_info.val;</div><div class='add'>+</div><div class='add'>+	dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_info.val;</div><div class='add'>+</div><div class='add'>+	dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_vir_info.val;</div><div class='add'>+	dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_act_info.val;</div><div class='add'>+</div><div class='add'>+	dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_info.val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rga_cmd_set_src_info(struct rga_ctx *ctx,</div><div class='add'>+				 struct rga_addr_offset *offset)</div><div class='add'>+{</div><div class='add'>+	struct rga_corners_addr_offset src_offsets;</div><div class='add'>+	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='add'>+	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='add'>+	unsigned int src_h, src_w, src_x, src_y;</div><div class='add'>+</div><div class='add'>+	src_h = ctx-&gt;in.crop.height;</div><div class='add'>+	src_w = ctx-&gt;in.crop.width;</div><div class='add'>+	src_x = ctx-&gt;in.crop.left;</div><div class='add'>+	src_y = ctx-&gt;in.crop.top;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * Configure the dest framebuffer base address with pixel offset.</div><div class='add'>+	 * Calculate the source framebuffer base address with offset pixel.</div><div class='ctx'> 	 */</div><div class='del'>-	offsets = rga_get_addr_offset(&amp;ctx-&gt;out, dst_x, dst_y, dst_w, dst_h);</div><div class='del'>-	dst_offset = rga_lookup_draw_pos(&amp;offsets, src_info.data.rot_mode,</div><div class='del'>-					 src_info.data.mir_mode);</div><div class='add'>+	src_offsets = rga_get_addr_offset(&amp;ctx-&gt;in, offset,</div><div class='add'>+					  src_x, src_y, src_w, src_h);</div><div class='ctx'> </div><div class='ctx'> 	dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) &gt;&gt; 2] =</div><div class='ctx'> 		src_offsets.left_top.y_off;</div><div class='hunk'>@@ -331,13 +334,49 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)</div><div class='ctx'> 		src_offsets.left_top.u_off;</div><div class='ctx'> 	dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) &gt;&gt; 2] =</div><div class='ctx'> 		src_offsets.left_top.v_off;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) &gt;&gt; 2] = x_factor.val;</div><div class='del'>-	dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) &gt;&gt; 2] = y_factor.val;</div><div class='del'>-	dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_vir_info.val;</div><div class='del'>-	dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_act_info.val;</div><div class='add'>+static void rga_cmd_set_dst_info(struct rga_ctx *ctx,</div><div class='add'>+				 struct rga_addr_offset *offset)</div><div class='add'>+{</div><div class='add'>+	struct rga_addr_offset *dst_offset;</div><div class='add'>+	struct rga_corners_addr_offset offsets;</div><div class='add'>+	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='add'>+	u32 *dest = rga-&gt;cmdbuf_virt;</div><div class='add'>+	unsigned int dst_h, dst_w, dst_x, dst_y;</div><div class='add'>+	unsigned int mir_mode = 0;</div><div class='add'>+	unsigned int rot_mode = 0;</div><div class='ctx'> </div><div class='del'>-	dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = src_info.val;</div><div class='add'>+	dst_h = ctx-&gt;out.crop.height;</div><div class='add'>+	dst_w = ctx-&gt;out.crop.width;</div><div class='add'>+	dst_x = ctx-&gt;out.crop.left;</div><div class='add'>+	dst_y = ctx-&gt;out.crop.top;</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;vflip)</div><div class='add'>+		mir_mode |= RGA_SRC_MIRR_MODE_X;</div><div class='add'>+	if (ctx-&gt;hflip)</div><div class='add'>+		mir_mode |= RGA_SRC_MIRR_MODE_Y;</div><div class='add'>+</div><div class='add'>+	switch (ctx-&gt;rotate) {</div><div class='add'>+	case 90:</div><div class='add'>+		rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;</div><div class='add'>+		break;</div><div class='add'>+	case 180:</div><div class='add'>+		rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;</div><div class='add'>+		break;</div><div class='add'>+	case 270:</div><div class='add'>+		rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Configure the dest framebuffer base address with pixel offset.</div><div class='add'>+	 */</div><div class='add'>+	offsets = rga_get_addr_offset(&amp;ctx-&gt;out, offset, dst_x, dst_y, dst_w, dst_h);</div><div class='add'>+	dst_offset = rga_lookup_draw_pos(&amp;offsets, mir_mode, rot_mode);</div><div class='ctx'> </div><div class='ctx'> 	dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) &gt;&gt; 2] =</div><div class='ctx'> 		dst_offset-&gt;y_off;</div><div class='hunk'>@@ -345,11 +384,6 @@ static void rga_cmd_set_trans_info(struct rga_ctx *ctx)</div><div class='ctx'> 		dst_offset-&gt;u_off;</div><div class='ctx'> 	dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) &gt;&gt; 2] =</div><div class='ctx'> 		dst_offset-&gt;v_off;</div><div class='del'>-</div><div class='del'>-	dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_vir_info.val;</div><div class='del'>-	dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_act_info.val;</div><div class='del'>-</div><div class='del'>-	dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) &gt;&gt; 2] = dst_info.val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rga_cmd_set_mode(struct rga_ctx *ctx)</div><div class='hunk'>@@ -375,22 +409,25 @@ static void rga_cmd_set_mode(struct rga_ctx *ctx)</div><div class='ctx'> 	dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) &gt;&gt; 2] = mode.val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rga_cmd_set(struct rga_ctx *ctx)</div><div class='add'>+static void rga_cmd_set(struct rga_ctx *ctx,</div><div class='add'>+			struct rga_vb_buffer *src, struct rga_vb_buffer *dst)</div><div class='ctx'> {</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> </div><div class='ctx'> 	memset(rga-&gt;cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);</div><div class='ctx'> </div><div class='del'>-	rga_cmd_set_src_addr(ctx, rga-&gt;src_mmu_pages);</div><div class='add'>+	rga_cmd_set_src_addr(ctx, src-&gt;dma_desc_pa);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Due to hardware bug,</div><div class='ctx'> 	 * src1 mmu also should be configured when using alpha blending.</div><div class='ctx'> 	 */</div><div class='del'>-	rga_cmd_set_src1_addr(ctx, rga-&gt;dst_mmu_pages);</div><div class='add'>+	rga_cmd_set_src1_addr(ctx, dst-&gt;dma_desc_pa);</div><div class='ctx'> </div><div class='del'>-	rga_cmd_set_dst_addr(ctx, rga-&gt;dst_mmu_pages);</div><div class='add'>+	rga_cmd_set_dst_addr(ctx, dst-&gt;dma_desc_pa);</div><div class='ctx'> 	rga_cmd_set_mode(ctx);</div><div class='ctx'> </div><div class='add'>+	rga_cmd_set_src_info(ctx, &amp;src-&gt;offset);</div><div class='add'>+	rga_cmd_set_dst_info(ctx, &amp;dst-&gt;offset);</div><div class='ctx'> 	rga_cmd_set_trans_info(ctx);</div><div class='ctx'> </div><div class='ctx'> 	rga_write(rga, RGA_CMD_BASE, rga-&gt;cmdbuf_phy);</div><div class='hunk'>@@ -400,11 +437,12 @@ static void rga_cmd_set(struct rga_ctx *ctx)</div><div class='ctx'> 		PAGE_SIZE, DMA_BIDIRECTIONAL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void rga_hw_start(struct rockchip_rga *rga)</div><div class='add'>+void rga_hw_start(struct rockchip_rga *rga,</div><div class='add'>+		  struct rga_vb_buffer *src, struct rga_vb_buffer *dst)</div><div class='ctx'> {</div><div class='ctx'> 	struct rga_ctx *ctx = rga-&gt;curr;</div><div class='ctx'> </div><div class='del'>-	rga_cmd_set(ctx);</div><div class='add'>+	rga_cmd_set(ctx, src, dst);</div><div class='ctx'> </div><div class='ctx'> 	rga_write(rga, RGA_SYS_CTRL, 0x00);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c<br/>index f1c532a5802a..00fdfa9e10bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rga/rga.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga.c</a></div><div class='hunk'>@@ -45,10 +45,7 @@ static void device_run(void *prv)</div><div class='ctx'> 	src = v4l2_m2m_next_src_buf(ctx-&gt;fh.m2m_ctx);</div><div class='ctx'> 	dst = v4l2_m2m_next_dst_buf(ctx-&gt;fh.m2m_ctx);</div><div class='ctx'> </div><div class='del'>-	rga_buf_map(&amp;src-&gt;vb2_buf);</div><div class='del'>-	rga_buf_map(&amp;dst-&gt;vb2_buf);</div><div class='del'>-</div><div class='del'>-	rga_hw_start(rga);</div><div class='add'>+	rga_hw_start(rga, vb_to_rga(src), vb_to_rga(dst));</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock_irqrestore(&amp;rga-&gt;ctrl_lock, flags);</div><div class='ctx'> }</div><div class='hunk'>@@ -96,12 +93,13 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)</div><div class='ctx'> 	struct rga_ctx *ctx = priv;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	src_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_OUTPUT;</div><div class='add'>+	src_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;</div><div class='ctx'> 	src_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	src_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	src_vq-&gt;ops = &amp;rga_qops;</div><div class='ctx'> 	src_vq-&gt;mem_ops = &amp;vb2_dma_sg_memops;</div><div class='del'>-	src_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='add'>+	dst_vq-&gt;gfp_flags = __GFP_DMA32;</div><div class='add'>+	src_vq-&gt;buf_struct_size = sizeof(struct rga_vb_buffer);</div><div class='ctx'> 	src_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='ctx'> 	src_vq-&gt;lock = &amp;ctx-&gt;rga-&gt;mutex;</div><div class='ctx'> 	src_vq-&gt;dev = ctx-&gt;rga-&gt;v4l2_dev.dev;</div><div class='hunk'>@@ -110,12 +108,13 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	dst_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='add'>+	dst_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;</div><div class='ctx'> 	dst_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	dst_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	dst_vq-&gt;ops = &amp;rga_qops;</div><div class='ctx'> 	dst_vq-&gt;mem_ops = &amp;vb2_dma_sg_memops;</div><div class='del'>-	dst_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='add'>+	dst_vq-&gt;gfp_flags = __GFP_DMA32;</div><div class='add'>+	dst_vq-&gt;buf_struct_size = sizeof(struct rga_vb_buffer);</div><div class='ctx'> 	dst_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='ctx'> 	dst_vq-&gt;lock = &amp;ctx-&gt;rga-&gt;mutex;</div><div class='ctx'> 	dst_vq-&gt;dev = ctx-&gt;rga-&gt;v4l2_dev.dev;</div><div class='hunk'>@@ -184,7 +183,7 @@ static int rga_setup_ctrls(struct rga_ctx *ctx)</div><div class='ctx'> static struct rga_fmt formats[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.fourcc = V4L2_PIX_FMT_ARGB32,</div><div class='del'>-		.color_swap = RGA_COLOR_RB_SWAP,</div><div class='add'>+		.color_swap = RGA_COLOR_ALPHA_SWAP,</div><div class='ctx'> 		.hw_format = RGA_COLOR_FMT_ABGR8888,</div><div class='ctx'> 		.depth = 32,</div><div class='ctx'> 		.uv_factor = 1,</div><div class='hunk'>@@ -192,17 +191,8 @@ static struct rga_fmt formats[] = {</div><div class='ctx'> 		.x_div = 1,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='del'>-		.fourcc = V4L2_PIX_FMT_XRGB32,</div><div class='del'>-		.color_swap = RGA_COLOR_RB_SWAP,</div><div class='del'>-		.hw_format = RGA_COLOR_FMT_XBGR8888,</div><div class='del'>-		.depth = 32,</div><div class='del'>-		.uv_factor = 1,</div><div class='del'>-		.y_div = 1,</div><div class='del'>-		.x_div = 1,</div><div class='del'>-	},</div><div class='del'>-	{</div><div class='ctx'> 		.fourcc = V4L2_PIX_FMT_ABGR32,</div><div class='del'>-		.color_swap = RGA_COLOR_ALPHA_SWAP,</div><div class='add'>+		.color_swap = RGA_COLOR_RB_SWAP,</div><div class='ctx'> 		.hw_format = RGA_COLOR_FMT_ABGR8888,</div><div class='ctx'> 		.depth = 32,</div><div class='ctx'> 		.uv_factor = 1,</div><div class='hunk'>@@ -211,7 +201,7 @@ static struct rga_fmt formats[] = {</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.fourcc = V4L2_PIX_FMT_XBGR32,</div><div class='del'>-		.color_swap = RGA_COLOR_ALPHA_SWAP,</div><div class='add'>+		.color_swap = RGA_COLOR_RB_SWAP,</div><div class='ctx'> 		.hw_format = RGA_COLOR_FMT_XBGR8888,</div><div class='ctx'> 		.depth = 32,</div><div class='ctx'> 		.uv_factor = 1,</div><div class='hunk'>@@ -291,6 +281,15 @@ static struct rga_fmt formats[] = {</div><div class='ctx'> 		.x_div = 1,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		.fourcc = V4L2_PIX_FMT_NV12M,</div><div class='add'>+		.color_swap = RGA_COLOR_NONE_SWAP,</div><div class='add'>+		.hw_format = RGA_COLOR_FMT_YUV420SP,</div><div class='add'>+		.depth = 12,</div><div class='add'>+		.uv_factor = 4,</div><div class='add'>+		.y_div = 2,</div><div class='add'>+		.x_div = 1,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		.fourcc = V4L2_PIX_FMT_NV16,</div><div class='ctx'> 		.color_swap = RGA_COLOR_NONE_SWAP,</div><div class='ctx'> 		.hw_format = RGA_COLOR_FMT_YUV422SP,</div><div class='hunk'>@@ -330,12 +329,12 @@ static struct rga_fmt formats[] = {</div><div class='ctx'> </div><div class='ctx'> #define NUM_FORMATS ARRAY_SIZE(formats)</div><div class='ctx'> </div><div class='del'>-static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)</div><div class='add'>+static struct rga_fmt *rga_fmt_find(u32 pixelformat)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NUM_FORMATS; i++) {</div><div class='del'>-		if (formats[i].fourcc == f-&gt;fmt.pix.pixelformat)</div><div class='add'>+		if (formats[i].fourcc == pixelformat)</div><div class='ctx'> 			return &amp;formats[i];</div><div class='ctx'> 	}</div><div class='ctx'> 	return NULL;</div><div class='hunk'>@@ -354,14 +353,11 @@ static struct rga_frame def_frame = {</div><div class='ctx'> </div><div class='ctx'> struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)</div><div class='ctx'> {</div><div class='del'>-	switch (type) {</div><div class='del'>-	case V4L2_BUF_TYPE_VIDEO_OUTPUT:</div><div class='add'>+	if (V4L2_TYPE_IS_OUTPUT(type))</div><div class='ctx'> 		return &amp;ctx-&gt;in;</div><div class='del'>-	case V4L2_BUF_TYPE_VIDEO_CAPTURE:</div><div class='add'>+	if (V4L2_TYPE_IS_CAPTURE(type))</div><div class='ctx'> 		return &amp;ctx-&gt;out;</div><div class='del'>-	default:</div><div class='del'>-		return ERR_PTR(-EINVAL);</div><div class='del'>-	}</div><div class='add'>+	return ERR_PTR(-EINVAL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rga_open(struct file *file)</div><div class='hunk'>@@ -378,6 +374,11 @@ static int rga_open(struct file *file)</div><div class='ctx'> 	ctx-&gt;in = def_frame;</div><div class='ctx'> 	ctx-&gt;out = def_frame;</div><div class='ctx'> </div><div class='add'>+	v4l2_fill_pixfmt_mp(&amp;ctx-&gt;in.pix,</div><div class='add'>+			    ctx-&gt;in.fmt-&gt;fourcc, ctx-&gt;out.width, ctx-&gt;out.height);</div><div class='add'>+	v4l2_fill_pixfmt_mp(&amp;ctx-&gt;out.pix,</div><div class='add'>+			    ctx-&gt;out.fmt-&gt;fourcc, ctx-&gt;out.width, ctx-&gt;out.height);</div><div class='add'>+</div><div class='ctx'> 	if (mutex_lock_interruptible(&amp;rga-&gt;mutex)) {</div><div class='ctx'> 		kfree(ctx);</div><div class='ctx'> 		return -ERESTARTSYS;</div><div class='hunk'>@@ -458,6 +459,7 @@ static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)</div><div class='ctx'> </div><div class='ctx'> static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> {</div><div class='add'>+	struct v4l2_pix_format_mplane *pix_fmt = &amp;f-&gt;fmt.pix_mp;</div><div class='ctx'> 	struct rga_ctx *ctx = prv;</div><div class='ctx'> 	struct vb2_queue *vq;</div><div class='ctx'> 	struct rga_frame *frm;</div><div class='hunk'>@@ -469,58 +471,43 @@ static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> 	if (IS_ERR(frm))</div><div class='ctx'> 		return PTR_ERR(frm);</div><div class='ctx'> </div><div class='del'>-	f-&gt;fmt.pix.width = frm-&gt;width;</div><div class='del'>-	f-&gt;fmt.pix.height = frm-&gt;height;</div><div class='del'>-	f-&gt;fmt.pix.field = V4L2_FIELD_NONE;</div><div class='del'>-	f-&gt;fmt.pix.pixelformat = frm-&gt;fmt-&gt;fourcc;</div><div class='del'>-	f-&gt;fmt.pix.bytesperline = frm-&gt;stride;</div><div class='del'>-	f-&gt;fmt.pix.sizeimage = frm-&gt;size;</div><div class='del'>-	f-&gt;fmt.pix.colorspace = frm-&gt;colorspace;</div><div class='add'>+	v4l2_fill_pixfmt_mp(pix_fmt, frm-&gt;fmt-&gt;fourcc, frm-&gt;width, frm-&gt;height);</div><div class='add'>+</div><div class='add'>+	pix_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	pix_fmt-&gt;colorspace = frm-&gt;colorspace;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> {</div><div class='add'>+	struct v4l2_pix_format_mplane *pix_fmt = &amp;f-&gt;fmt.pix_mp;</div><div class='ctx'> 	struct rga_fmt *fmt;</div><div class='ctx'> </div><div class='del'>-	fmt = rga_fmt_find(f);</div><div class='del'>-	if (!fmt) {</div><div class='add'>+	fmt = rga_fmt_find(pix_fmt-&gt;pixelformat);</div><div class='add'>+	if (!fmt)</div><div class='ctx'> 		fmt = &amp;formats[0];</div><div class='del'>-		f-&gt;fmt.pix.pixelformat = fmt-&gt;fourcc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	f-&gt;fmt.pix.field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='del'>-	if (f-&gt;fmt.pix.width &gt; MAX_WIDTH)</div><div class='del'>-		f-&gt;fmt.pix.width = MAX_WIDTH;</div><div class='del'>-	if (f-&gt;fmt.pix.height &gt; MAX_HEIGHT)</div><div class='del'>-		f-&gt;fmt.pix.height = MAX_HEIGHT;</div><div class='add'>+	pix_fmt-&gt;width = clamp(pix_fmt-&gt;width,</div><div class='add'>+			       (u32)MIN_WIDTH, (u32)MAX_WIDTH);</div><div class='add'>+	pix_fmt-&gt;height = clamp(pix_fmt-&gt;height,</div><div class='add'>+				(u32)MIN_HEIGHT, (u32)MAX_HEIGHT);</div><div class='ctx'> </div><div class='del'>-	if (f-&gt;fmt.pix.width &lt; MIN_WIDTH)</div><div class='del'>-		f-&gt;fmt.pix.width = MIN_WIDTH;</div><div class='del'>-	if (f-&gt;fmt.pix.height &lt; MIN_HEIGHT)</div><div class='del'>-		f-&gt;fmt.pix.height = MIN_HEIGHT;</div><div class='del'>-</div><div class='del'>-	if (fmt-&gt;hw_format &gt;= RGA_COLOR_FMT_YUV422SP)</div><div class='del'>-		f-&gt;fmt.pix.bytesperline = f-&gt;fmt.pix.width;</div><div class='del'>-	else</div><div class='del'>-		f-&gt;fmt.pix.bytesperline = (f-&gt;fmt.pix.width * fmt-&gt;depth) &gt;&gt; 3;</div><div class='del'>-</div><div class='del'>-	f-&gt;fmt.pix.sizeimage =</div><div class='del'>-		f-&gt;fmt.pix.height * (f-&gt;fmt.pix.width * fmt-&gt;depth) &gt;&gt; 3;</div><div class='add'>+	v4l2_fill_pixfmt_mp(pix_fmt, fmt-&gt;fourcc, pix_fmt-&gt;width, pix_fmt-&gt;height);</div><div class='add'>+	pix_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> {</div><div class='add'>+	struct v4l2_pix_format_mplane *pix_fmt = &amp;f-&gt;fmt.pix_mp;</div><div class='ctx'> 	struct rga_ctx *ctx = prv;</div><div class='ctx'> 	struct rockchip_rga *rga = ctx-&gt;rga;</div><div class='ctx'> 	struct vb2_queue *vq;</div><div class='ctx'> 	struct rga_frame *frm;</div><div class='del'>-	struct rga_fmt *fmt;</div><div class='ctx'> 	int ret = 0;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* Adjust all values accordingly to the hardware capabilities</div><div class='ctx'> 	 * and chosen format.</div><div class='hunk'>@@ -536,15 +523,14 @@ static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> 	frm = rga_get_frame(ctx, f-&gt;type);</div><div class='ctx'> 	if (IS_ERR(frm))</div><div class='ctx'> 		return PTR_ERR(frm);</div><div class='del'>-	fmt = rga_fmt_find(f);</div><div class='del'>-	if (!fmt)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	frm-&gt;width = f-&gt;fmt.pix.width;</div><div class='del'>-	frm-&gt;height = f-&gt;fmt.pix.height;</div><div class='del'>-	frm-&gt;size = f-&gt;fmt.pix.sizeimage;</div><div class='del'>-	frm-&gt;fmt = fmt;</div><div class='del'>-	frm-&gt;stride = f-&gt;fmt.pix.bytesperline;</div><div class='del'>-	frm-&gt;colorspace = f-&gt;fmt.pix.colorspace;</div><div class='add'>+	frm-&gt;width = pix_fmt-&gt;width;</div><div class='add'>+	frm-&gt;height = pix_fmt-&gt;height;</div><div class='add'>+	frm-&gt;size = 0;</div><div class='add'>+	for (i = 0; i &lt; pix_fmt-&gt;num_planes; i++)</div><div class='add'>+		frm-&gt;size += pix_fmt-&gt;plane_fmt[i].sizeimage;</div><div class='add'>+	frm-&gt;fmt = rga_fmt_find(pix_fmt-&gt;pixelformat);</div><div class='add'>+	frm-&gt;stride = pix_fmt-&gt;plane_fmt[0].bytesperline;</div><div class='add'>+	frm-&gt;colorspace = pix_fmt-&gt;colorspace;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset crop settings */</div><div class='ctx'> 	frm-&gt;crop.left = 0;</div><div class='hunk'>@@ -552,6 +538,21 @@ static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)</div><div class='ctx'> 	frm-&gt;crop.width = frm-&gt;width;</div><div class='ctx'> 	frm-&gt;crop.height = frm-&gt;height;</div><div class='ctx'> </div><div class='add'>+	frm-&gt;pix = *pix_fmt;</div><div class='add'>+</div><div class='add'>+	v4l2_dbg(debug, 1, &amp;rga-&gt;v4l2_dev,</div><div class='add'>+		 "[%s] fmt - %p4cc %dx%d (stride %d, sizeimage %d)\n",</div><div class='add'>+		  V4L2_TYPE_IS_OUTPUT(f-&gt;type) ? "OUTPUT" : "CAPTURE",</div><div class='add'>+		  &amp;frm-&gt;fmt-&gt;fourcc, frm-&gt;width, frm-&gt;height,</div><div class='add'>+		  frm-&gt;stride, frm-&gt;size);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; pix_fmt-&gt;num_planes; i++) {</div><div class='add'>+		v4l2_dbg(debug, 1, &amp;rga-&gt;v4l2_dev,</div><div class='add'>+			 "plane[%d]: size %d, bytesperline %d\n",</div><div class='add'>+			 i, pix_fmt-&gt;plane_fmt[i].sizeimage,</div><div class='add'>+			 pix_fmt-&gt;plane_fmt[i].bytesperline);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -569,21 +570,21 @@ static int vidioc_g_selection(struct file *file, void *prv,</div><div class='ctx'> 	switch (s-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE_DEFAULT:</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE_BOUNDS:</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		if (!V4L2_TYPE_IS_CAPTURE(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='add'>+		if (!V4L2_TYPE_IS_OUTPUT(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		if (!V4L2_TYPE_IS_CAPTURE(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		use_frame = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='add'>+		if (!V4L2_TYPE_IS_OUTPUT(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		use_frame = true;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -621,7 +622,7 @@ static int vidioc_s_selection(struct file *file, void *prv,</div><div class='ctx'> 		 * COMPOSE target is only valid for capture buffer type, return</div><div class='ctx'> 		 * error for output buffer type</div><div class='ctx'> 		 */</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		if (!V4L2_TYPE_IS_CAPTURE(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='hunk'>@@ -629,7 +630,7 @@ static int vidioc_s_selection(struct file *file, void *prv,</div><div class='ctx'> 		 * CROP target is only valid for output buffer type, return</div><div class='ctx'> 		 * error for capture buffer type</div><div class='ctx'> 		 */</div><div class='del'>-		if (s-&gt;type != V4L2_BUF_TYPE_VIDEO_OUTPUT)</div><div class='add'>+		if (!V4L2_TYPE_IS_OUTPUT(s-&gt;type))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -662,14 +663,14 @@ static const struct v4l2_ioctl_ops rga_ioctl_ops = {</div><div class='ctx'> 	.vidioc_querycap = vidioc_querycap,</div><div class='ctx'> </div><div class='ctx'> 	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,</div><div class='del'>-	.vidioc_g_fmt_vid_cap = vidioc_g_fmt,</div><div class='del'>-	.vidioc_try_fmt_vid_cap = vidioc_try_fmt,</div><div class='del'>-	.vidioc_s_fmt_vid_cap = vidioc_s_fmt,</div><div class='add'>+	.vidioc_g_fmt_vid_cap_mplane = vidioc_g_fmt,</div><div class='add'>+	.vidioc_try_fmt_vid_cap_mplane = vidioc_try_fmt,</div><div class='add'>+	.vidioc_s_fmt_vid_cap_mplane = vidioc_s_fmt,</div><div class='ctx'> </div><div class='ctx'> 	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,</div><div class='del'>-	.vidioc_g_fmt_vid_out = vidioc_g_fmt,</div><div class='del'>-	.vidioc_try_fmt_vid_out = vidioc_try_fmt,</div><div class='del'>-	.vidioc_s_fmt_vid_out = vidioc_s_fmt,</div><div class='add'>+	.vidioc_g_fmt_vid_out_mplane = vidioc_g_fmt,</div><div class='add'>+	.vidioc_try_fmt_vid_out_mplane = vidioc_try_fmt,</div><div class='add'>+	.vidioc_s_fmt_vid_out_mplane = vidioc_s_fmt,</div><div class='ctx'> </div><div class='ctx'> 	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,</div><div class='ctx'> 	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,</div><div class='hunk'>@@ -696,7 +697,7 @@ static const struct video_device rga_videodev = {</div><div class='ctx'> 	.minor = -1,</div><div class='ctx'> 	.release = video_device_release,</div><div class='ctx'> 	.vfl_dir = VFL_DIR_M2M,</div><div class='del'>-	.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,</div><div class='add'>+	.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int rga_enable_clocks(struct rockchip_rga *rga)</div><div class='hunk'>@@ -836,6 +837,12 @@ static int rga_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err_put_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ret = dma_set_mask_and_coherent(rga-&gt;dev, DMA_BIT_MASK(32));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(rga-&gt;dev, "32-bit DMA not supported");</div><div class='add'>+		goto err_put_clk;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = v4l2_device_register(&amp;pdev-&gt;dev, &amp;rga-&gt;v4l2_dev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_put_clk;</div><div class='hunk'>@@ -881,26 +888,13 @@ static int rga_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto rel_m2m;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rga-&gt;src_mmu_pages =</div><div class='del'>-		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);</div><div class='del'>-	if (!rga-&gt;src_mmu_pages) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto free_dma;</div><div class='del'>-	}</div><div class='del'>-	rga-&gt;dst_mmu_pages =</div><div class='del'>-		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);</div><div class='del'>-	if (!rga-&gt;dst_mmu_pages) {</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto free_src_pages;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	def_frame.stride = (def_frame.width * def_frame.fmt-&gt;depth) &gt;&gt; 3;</div><div class='ctx'> 	def_frame.size = def_frame.stride * def_frame.height;</div><div class='ctx'> </div><div class='ctx'> 	ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		v4l2_err(&amp;rga-&gt;v4l2_dev, "Failed to register video device\n");</div><div class='del'>-		goto free_dst_pages;</div><div class='add'>+		goto free_dma;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_info(&amp;rga-&gt;v4l2_dev, "Registered %s as /dev/%s\n",</div><div class='hunk'>@@ -908,10 +902,6 @@ static int rga_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-free_dst_pages:</div><div class='del'>-	free_pages((unsigned long)rga-&gt;dst_mmu_pages, 3);</div><div class='del'>-free_src_pages:</div><div class='del'>-	free_pages((unsigned long)rga-&gt;src_mmu_pages, 3);</div><div class='ctx'> free_dma:</div><div class='ctx'> 	dma_free_attrs(rga-&gt;dev, RGA_CMDBUF_SIZE, rga-&gt;cmdbuf_virt,</div><div class='ctx'> 		       rga-&gt;cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);</div><div class='hunk'>@@ -934,9 +924,6 @@ static void rga_remove(struct platform_device *pdev)</div><div class='ctx'> 	dma_free_attrs(rga-&gt;dev, RGA_CMDBUF_SIZE, rga-&gt;cmdbuf_virt,</div><div class='ctx'> 		       rga-&gt;cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);</div><div class='ctx'> </div><div class='del'>-	free_pages((unsigned long)rga-&gt;src_mmu_pages, 3);</div><div class='del'>-	free_pages((unsigned long)rga-&gt;dst_mmu_pages, 3);</div><div class='del'>-</div><div class='ctx'> 	v4l2_info(&amp;rga-&gt;v4l2_dev, "Removing\n");</div><div class='ctx'> </div><div class='ctx'> 	v4l2_m2m_release(rga-&gt;m2m_dev);</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h<br/>index 5fa9d2f366dc..3502dff6055c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rga/rga.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rga/rga.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rga/rga.h</a></div><div class='hunk'>@@ -34,12 +34,17 @@ struct rga_frame {</div><div class='ctx'> </div><div class='ctx'> 	/* Image format */</div><div class='ctx'> 	struct rga_fmt *fmt;</div><div class='add'>+	struct v4l2_pix_format_mplane pix;</div><div class='ctx'> </div><div class='ctx'> 	/* Variables that can calculated once and reused */</div><div class='ctx'> 	u32 stride;</div><div class='ctx'> 	u32 size;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct rga_dma_desc {</div><div class='add'>+	u32 addr;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct rockchip_rga_version {</div><div class='ctx'> 	u32 major;</div><div class='ctx'> 	u32 minor;</div><div class='hunk'>@@ -81,15 +86,36 @@ struct rockchip_rga {</div><div class='ctx'> 	struct rga_ctx *curr;</div><div class='ctx'> 	dma_addr_t cmdbuf_phy;</div><div class='ctx'> 	void *cmdbuf_virt;</div><div class='del'>-	unsigned int *src_mmu_pages;</div><div class='del'>-	unsigned int *dst_mmu_pages;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct rga_addr_offset {</div><div class='add'>+	unsigned int y_off;</div><div class='add'>+	unsigned int u_off;</div><div class='add'>+	unsigned int v_off;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct rga_vb_buffer {</div><div class='add'>+	struct vb2_v4l2_buffer vb_buf;</div><div class='add'>+	struct list_head queue;</div><div class='add'>+</div><div class='add'>+	/* RGA MMU mapping for this buffer */</div><div class='add'>+	struct rga_dma_desc *dma_desc;</div><div class='add'>+	dma_addr_t dma_desc_pa;</div><div class='add'>+	size_t n_desc;</div><div class='add'>+</div><div class='add'>+	/* Plane offsets of this buffer into the mapping */</div><div class='add'>+	struct rga_addr_offset offset;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct rga_vb_buffer *vb_to_rga(struct vb2_v4l2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	return container_of(vb, struct rga_vb_buffer, vb_buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);</div><div class='ctx'> </div><div class='ctx'> /* RGA Buffers Manage */</div><div class='ctx'> extern const struct vb2_ops rga_qops;</div><div class='del'>-void rga_buf_map(struct vb2_buffer *vb);</div><div class='ctx'> </div><div class='ctx'> /* RGA Hardware */</div><div class='ctx'> static inline void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)</div><div class='hunk'>@@ -110,6 +136,7 @@ static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)</div><div class='ctx'> 	rga_write(rga, reg, temp);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-void rga_hw_start(struct rockchip_rga *rga);</div><div class='add'>+void rga_hw_start(struct rockchip_rga *rga,</div><div class='add'>+		  struct rga_vb_buffer *src, struct rga_vb_buffer *dst);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c<br/>index c6d7e01c8949..aebd3c12020b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c</a></div><div class='hunk'>@@ -1431,7 +1431,7 @@ static int rkisp1_register_capture(struct rkisp1_capture *cap)</div><div class='ctx'> 	q-&gt;ops = &amp;rkisp1_vb2_ops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct rkisp1_buffer);</div><div class='del'>-	q-&gt;min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED;</div><div class='add'>+	q-&gt;min_queued_buffers = RKISP1_MIN_BUFFERS_NEEDED;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	q-&gt;lock = &amp;node-&gt;vlock;</div><div class='ctx'> 	q-&gt;dev = cap-&gt;rkisp1-&gt;dev;</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h<br/>index 1e7cea1bea5e..4b6b28c05b89 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-common.h</a></div><div class='hunk'>@@ -61,6 +61,14 @@ struct dentry;</div><div class='ctx'> 						 RKISP1_CIF_ISP_EXP_END |	\</div><div class='ctx'> 						 RKISP1_CIF_ISP_HIST_MEASURE_RDY)</div><div class='ctx'> </div><div class='add'>+/* IRQ lines */</div><div class='add'>+enum rkisp1_irq_line {</div><div class='add'>+	RKISP1_IRQ_ISP = 0,</div><div class='add'>+	RKISP1_IRQ_MI,</div><div class='add'>+	RKISP1_IRQ_MIPI,</div><div class='add'>+	RKISP1_NUM_IRQS,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* enum for the resizer pads */</div><div class='ctx'> enum rkisp1_rsz_pad {</div><div class='ctx'> 	RKISP1_RSZ_PAD_SINK,</div><div class='hunk'>@@ -417,13 +425,13 @@ struct rkisp1_debug {</div><div class='ctx'> 	unsigned long stats_error;</div><div class='ctx'> 	unsigned long stop_timeout[2];</div><div class='ctx'> 	unsigned long frame_drop[2];</div><div class='add'>+	unsigned long complete_frames;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * struct rkisp1_device - ISP platform device</div><div class='ctx'>  *</div><div class='ctx'>  * @base_addr:	   base register address</div><div class='del'>- * @irq:	   the irq number</div><div class='ctx'>  * @dev:	   a pointer to the struct device</div><div class='ctx'>  * @clk_size:	   number of clocks</div><div class='ctx'>  * @clks:	   array of clocks</div><div class='hunk'>@@ -441,6 +449,7 @@ struct rkisp1_debug {</div><div class='ctx'>  * @stream_lock:   serializes {start/stop}_streaming callbacks between the capture devices.</div><div class='ctx'>  * @debug:	   debug params to be exposed on debugfs</div><div class='ctx'>  * @info:	   version-specific ISP information</div><div class='add'>+ * @irqs:          IRQ line numbers</div><div class='ctx'>  */</div><div class='ctx'> struct rkisp1_device {</div><div class='ctx'> 	void __iomem *base_addr;</div><div class='hunk'>@@ -461,6 +470,7 @@ struct rkisp1_device {</div><div class='ctx'> 	struct mutex stream_lock; /* serialize {start/stop}_streaming cb between capture devices */</div><div class='ctx'> 	struct rkisp1_debug debug;</div><div class='ctx'> 	const struct rkisp1_info *info;</div><div class='add'>+	int irqs[RKISP1_NUM_IRQS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c<br/>index 6e17b2817e61..b6e47e2f1b94 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c</a></div><div class='hunk'>@@ -125,8 +125,20 @@ static void rkisp1_csi_disable(struct rkisp1_csi *csi)</div><div class='ctx'> 	struct rkisp1_device *rkisp1 = csi-&gt;rkisp1;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	/* Mask and clear interrupts. */</div><div class='add'>+	/* Mask MIPI interrupts. */</div><div class='ctx'> 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0);</div><div class='add'>+</div><div class='add'>+	/* Flush posted writes */</div><div class='add'>+	rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wait until the IRQ handler has ended. The IRQ handler may get called</div><div class='add'>+	 * even after this, but it will return immediately as the MIPI</div><div class='add'>+	 * interrupts have been masked.</div><div class='add'>+	 */</div><div class='add'>+	synchronize_irq(rkisp1-&gt;irqs[RKISP1_IRQ_MIPI]);</div><div class='add'>+</div><div class='add'>+	/* Clear MIPI interrupt status */</div><div class='ctx'> 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);</div><div class='ctx'> </div><div class='ctx'> 	val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);</div><div class='hunk'>@@ -242,8 +254,8 @@ static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (code-&gt;index)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-						      RKISP1_CSI_PAD_SINK);</div><div class='add'>+		sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							RKISP1_CSI_PAD_SINK);</div><div class='ctx'> 		code-&gt;code = sink_fmt-&gt;code;</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -270,15 +282,13 @@ static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rkisp1_csi_init_config(struct v4l2_subdev *sd,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int rkisp1_csi_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					      RKISP1_CSI_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					     RKISP1_CSI_PAD_SRC);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC);</div><div class='ctx'> </div><div class='ctx'> 	sink_fmt-&gt;width = RKISP1_DEFAULT_WIDTH;</div><div class='ctx'> 	sink_fmt-&gt;height = RKISP1_DEFAULT_HEIGHT;</div><div class='hunk'>@@ -301,7 +311,7 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (fmt-&gt;pad == RKISP1_CSI_PAD_SRC)</div><div class='ctx'> 		return v4l2_subdev_get_fmt(sd, sd_state, fmt);</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	sink_fmt-&gt;code = fmt-&gt;format.code;</div><div class='ctx'> </div><div class='hunk'>@@ -321,7 +331,7 @@ static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	fmt-&gt;format = *sink_fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate the format to the source pad. */</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SRC);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SRC);</div><div class='ctx'> 	*src_fmt = *sink_fmt;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -374,7 +384,7 @@ static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	sd_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_CSI_PAD_SINK);</div><div class='ctx'> 	format = rkisp1_mbus_info_get_by_code(sink_fmt-&gt;code);</div><div class='ctx'> 	v4l2_subdev_unlock_state(sd_state);</div><div class='ctx'> </div><div class='hunk'>@@ -407,7 +417,6 @@ static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = rkisp1_csi_enum_mbus_code,</div><div class='del'>-	.init_cfg = rkisp1_csi_init_config,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = rkisp1_csi_set_fmt,</div><div class='ctx'> };</div><div class='hunk'>@@ -417,6 +426,10 @@ static const struct v4l2_subdev_ops rkisp1_csi_ops = {</div><div class='ctx'> 	.pad = &amp;rkisp1_csi_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops rkisp1_csi_internal_ops = {</div><div class='add'>+	.init_state = rkisp1_csi_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int rkisp1_csi_register(struct rkisp1_device *rkisp1)</div><div class='ctx'> {</div><div class='ctx'> 	struct rkisp1_csi *csi = &amp;rkisp1-&gt;csi;</div><div class='hunk'>@@ -428,6 +441,7 @@ int rkisp1_csi_register(struct rkisp1_device *rkisp1)</div><div class='ctx'> </div><div class='ctx'> 	sd = &amp;csi-&gt;sd;</div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;rkisp1_csi_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;rkisp1_csi_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	sd-&gt;entity.ops = &amp;rkisp1_csi_media_ops;</div><div class='ctx'> 	sd-&gt;entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c<br/>index 71df3dc95e6f..79cda589d935 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-debug.c</a></div><div class='hunk'>@@ -92,6 +92,10 @@ static int rkisp1_debug_dump_isp_regs_show(struct seq_file *m, void *p)</div><div class='ctx'> 		RKISP1_DEBUG_REG(ISP_FLAGS_SHD),</div><div class='ctx'> 		RKISP1_DEBUG_REG(ISP_RIS),</div><div class='ctx'> 		RKISP1_DEBUG_REG(ISP_ERR),</div><div class='add'>+		RKISP1_DEBUG_SHD_REG(ISP_IS_H_OFFS),</div><div class='add'>+		RKISP1_DEBUG_SHD_REG(ISP_IS_V_OFFS),</div><div class='add'>+		RKISP1_DEBUG_SHD_REG(ISP_IS_H_SIZE),</div><div class='add'>+		RKISP1_DEBUG_SHD_REG(ISP_IS_V_SIZE),</div><div class='ctx'> 		{ /* Sentinel */ },</div><div class='ctx'> 	};</div><div class='ctx'> 	struct rkisp1_device *rkisp1 = m-&gt;private;</div><div class='hunk'>@@ -217,6 +221,8 @@ void rkisp1_debug_init(struct rkisp1_device *rkisp1)</div><div class='ctx'> 			     &amp;debug-&gt;frame_drop[RKISP1_MAINPATH]);</div><div class='ctx'> 	debugfs_create_ulong("sp_frame_drop", 0444, debug-&gt;debugfs_dir,</div><div class='ctx'> 			     &amp;debug-&gt;frame_drop[RKISP1_SELFPATH]);</div><div class='add'>+	debugfs_create_ulong("complete_frames", 0444, debug-&gt;debugfs_dir,</div><div class='add'>+			     &amp;debug-&gt;complete_frames);</div><div class='ctx'> 	debugfs_create_file("input_status", 0444, debug-&gt;debugfs_dir, rkisp1,</div><div class='ctx'> 			    &amp;rkisp1_debug_input_status_fops);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c<br/>index c41abd2833f1..f96f821a7b50 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c</a></div><div class='hunk'>@@ -114,6 +114,7 @@</div><div class='ctx'> struct rkisp1_isr_data {</div><div class='ctx'> 	const char *name;</div><div class='ctx'> 	irqreturn_t (*isr)(int irq, void *ctx);</div><div class='add'>+	u32 line_mask;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ----------------------------------------------------------------------------</div><div class='hunk'>@@ -442,17 +443,25 @@ error:</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t rkisp1_isr(int irq, void *ctx)</div><div class='ctx'> {</div><div class='add'>+	irqreturn_t ret = IRQ_NONE;</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Call rkisp1_capture_isr() first to handle the frame that</div><div class='ctx'> 	 * potentially completed using the current frame_sequence number before</div><div class='ctx'> 	 * it is potentially incremented by rkisp1_isp_isr() in the vertical</div><div class='ctx'> 	 * sync.</div><div class='ctx'> 	 */</div><div class='del'>-	rkisp1_capture_isr(irq, ctx);</div><div class='del'>-	rkisp1_isp_isr(irq, ctx);</div><div class='del'>-	rkisp1_csi_isr(irq, ctx);</div><div class='ctx'> </div><div class='del'>-	return IRQ_HANDLED;</div><div class='add'>+	if (rkisp1_capture_isr(irq, ctx) == IRQ_HANDLED)</div><div class='add'>+		ret = IRQ_HANDLED;</div><div class='add'>+</div><div class='add'>+	if (rkisp1_isp_isr(irq, ctx) == IRQ_HANDLED)</div><div class='add'>+		ret = IRQ_HANDLED;</div><div class='add'>+</div><div class='add'>+	if (rkisp1_csi_isr(irq, ctx) == IRQ_HANDLED)</div><div class='add'>+		ret = IRQ_HANDLED;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const char * const px30_isp_clks[] = {</div><div class='hunk'>@@ -463,9 +472,9 @@ static const char * const px30_isp_clks[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rkisp1_isr_data px30_isp_isrs[] = {</div><div class='del'>-	{ "isp", rkisp1_isp_isr },</div><div class='del'>-	{ "mi", rkisp1_capture_isr },</div><div class='del'>-	{ "mipi", rkisp1_csi_isr },</div><div class='add'>+	{ "isp", rkisp1_isp_isr, BIT(RKISP1_IRQ_ISP) },</div><div class='add'>+	{ "mi", rkisp1_capture_isr, BIT(RKISP1_IRQ_MI) },</div><div class='add'>+	{ "mipi", rkisp1_csi_isr, BIT(RKISP1_IRQ_MIPI) },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rkisp1_info px30_isp_info = {</div><div class='hunk'>@@ -484,7 +493,7 @@ static const char * const rk3399_isp_clks[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rkisp1_isr_data rk3399_isp_isrs[] = {</div><div class='del'>-	{ NULL, rkisp1_isr },</div><div class='add'>+	{ NULL, rkisp1_isr, BIT(RKISP1_IRQ_ISP) | BIT(RKISP1_IRQ_MI) | BIT(RKISP1_IRQ_MIPI) },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct rkisp1_info rk3399_isp_info = {</div><div class='hunk'>@@ -535,6 +544,9 @@ static int rkisp1_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (IS_ERR(rkisp1-&gt;base_addr))</div><div class='ctx'> 		return PTR_ERR(rkisp1-&gt;base_addr);</div><div class='ctx'> </div><div class='add'>+	for (unsigned int il = 0; il &lt; ARRAY_SIZE(rkisp1-&gt;irqs); ++il)</div><div class='add'>+		rkisp1-&gt;irqs[il] = -1;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; info-&gt;isr_size; i++) {</div><div class='ctx'> 		irq = info-&gt;isrs[i].name</div><div class='ctx'> 		    ? platform_get_irq_byname(pdev, info-&gt;isrs[i].name)</div><div class='hunk'>@@ -542,7 +554,12 @@ static int rkisp1_probe(struct platform_device *pdev)</div><div class='ctx'> 		if (irq &lt; 0)</div><div class='ctx'> 			return irq;</div><div class='ctx'> </div><div class='del'>-		ret = devm_request_irq(dev, irq, info-&gt;isrs[i].isr, IRQF_SHARED,</div><div class='add'>+		for (unsigned int il = 0; il &lt; ARRAY_SIZE(rkisp1-&gt;irqs); ++il) {</div><div class='add'>+			if (info-&gt;isrs[i].line_mask &amp; BIT(il))</div><div class='add'>+				rkisp1-&gt;irqs[il] = irq;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = devm_request_irq(dev, irq, info-&gt;isrs[i].isr, 0,</div><div class='ctx'> 				       dev_driver_string(dev), dev);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			dev_err(dev, "request irq failed: %d\n", ret);</div><div class='hunk'>@@ -582,7 +599,7 @@ static int rkisp1_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	ret = v4l2_device_register(rkisp1-&gt;dev, &amp;rkisp1-&gt;v4l2_dev);</div><div class='ctx'> 	if (ret)</div><div class='del'>-		goto err_pm_runtime_disable;</div><div class='add'>+		goto err_media_dev_cleanup;</div><div class='ctx'> </div><div class='ctx'> 	ret = media_device_register(&amp;rkisp1-&gt;media_dev);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -617,6 +634,8 @@ err_unreg_media_dev:</div><div class='ctx'> 	media_device_unregister(&amp;rkisp1-&gt;media_dev);</div><div class='ctx'> err_unreg_v4l2_dev:</div><div class='ctx'> 	v4l2_device_unregister(&amp;rkisp1-&gt;v4l2_dev);</div><div class='add'>+err_media_dev_cleanup:</div><div class='add'>+	media_device_cleanup(&amp;rkisp1-&gt;media_dev);</div><div class='ctx'> err_pm_runtime_disable:</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -637,6 +656,8 @@ static void rkisp1_remove(struct platform_device *pdev)</div><div class='ctx'> 	media_device_unregister(&amp;rkisp1-&gt;media_dev);</div><div class='ctx'> 	v4l2_device_unregister(&amp;rkisp1-&gt;v4l2_dev);</div><div class='ctx'> </div><div class='add'>+	media_device_cleanup(&amp;rkisp1-&gt;media_dev);</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c<br/>index 88ca8b2283b7..f00873d31c42 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c</a></div><div class='hunk'>@@ -66,8 +66,8 @@ static void rkisp1_config_ism(struct rkisp1_isp *isp,</div><div class='ctx'> 			      struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	const struct v4l2_rect *src_crop =</div><div class='del'>-		v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					 RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+		v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					   RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	struct rkisp1_device *rkisp1 = isp-&gt;rkisp1;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='hunk'>@@ -102,12 +102,12 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *sink_frm;</div><div class='ctx'> 	const struct v4l2_rect *sink_crop;</div><div class='ctx'> </div><div class='del'>-	sink_frm = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='del'>-	src_frm = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	sink_frm = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	src_frm = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> </div><div class='ctx'> 	sink_fmt = rkisp1_mbus_info_get_by_code(sink_frm-&gt;code);</div><div class='ctx'> 	src_fmt = rkisp1_mbus_info_get_by_code(src_frm-&gt;code);</div><div class='hunk'>@@ -201,8 +201,8 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,</div><div class='ctx'> 	} else {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *src_frm;</div><div class='ctx'> </div><div class='del'>-		src_frm = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-						     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+		src_frm = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 		rkisp1_params_pre_configure(&amp;rkisp1-&gt;params, sink_fmt-&gt;bayer_pat,</div><div class='ctx'> 					    src_frm-&gt;quantization,</div><div class='ctx'> 					    src_frm-&gt;ycbcr_enc);</div><div class='hunk'>@@ -254,11 +254,25 @@ static void rkisp1_isp_stop(struct rkisp1_isp *isp)</div><div class='ctx'> 	 * ISP(mi) stop in mi frame end -&gt; Stop ISP(mipi) -&gt;</div><div class='ctx'> 	 * Stop ISP(isp) -&gt;wait for ISP isp off</div><div class='ctx'> 	 */</div><div class='del'>-	/* stop and clear MI and ISP interrupts */</div><div class='del'>-	rkisp1_write(rkisp1, RKISP1_CIF_ISP_IMSC, 0);</div><div class='del'>-	rkisp1_write(rkisp1, RKISP1_CIF_ISP_ICR, ~0);</div><div class='ctx'> </div><div class='add'>+	/* Mask MI and ISP interrupts */</div><div class='add'>+	rkisp1_write(rkisp1, RKISP1_CIF_ISP_IMSC, 0);</div><div class='ctx'> 	rkisp1_write(rkisp1, RKISP1_CIF_MI_IMSC, 0);</div><div class='add'>+</div><div class='add'>+	/* Flush posted writes */</div><div class='add'>+	rkisp1_read(rkisp1, RKISP1_CIF_MI_IMSC);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Wait until the IRQ handler has ended. The IRQ handler may get called</div><div class='add'>+	 * even after this, but it will return immediately as the MI and ISP</div><div class='add'>+	 * interrupts have been masked.</div><div class='add'>+	 */</div><div class='add'>+	synchronize_irq(rkisp1-&gt;irqs[RKISP1_IRQ_ISP]);</div><div class='add'>+	if (rkisp1-&gt;irqs[RKISP1_IRQ_ISP] != rkisp1-&gt;irqs[RKISP1_IRQ_MI])</div><div class='add'>+		synchronize_irq(rkisp1-&gt;irqs[RKISP1_IRQ_MI]);</div><div class='add'>+</div><div class='add'>+	/* Clear MI and ISP interrupt status */</div><div class='add'>+	rkisp1_write(rkisp1, RKISP1_CIF_ISP_ICR, ~0);</div><div class='ctx'> 	rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, ~0);</div><div class='ctx'> </div><div class='ctx'> 	/* stop ISP */</div><div class='hunk'>@@ -318,8 +332,8 @@ static void rkisp1_isp_start(struct rkisp1_isp *isp,</div><div class='ctx'> 	       RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE;</div><div class='ctx'> 	rkisp1_write(rkisp1, RKISP1_CIF_ISP_CTRL, val);</div><div class='ctx'> </div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	src_info = rkisp1_mbus_info_get_by_code(src_fmt-&gt;code);</div><div class='ctx'> </div><div class='ctx'> 	if (src_info-&gt;pixel_enc != V4L2_PIXEL_ENC_BAYER)</div><div class='hunk'>@@ -409,15 +423,15 @@ static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rkisp1_isp_init_config(struct v4l2_subdev *sd,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int rkisp1_isp_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;</div><div class='ctx'> 	struct v4l2_rect *sink_crop, *src_crop;</div><div class='ctx'> </div><div class='ctx'> 	/* Video. */</div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> 	sink_fmt-&gt;width = RKISP1_DEFAULT_WIDTH;</div><div class='ctx'> 	sink_fmt-&gt;height = RKISP1_DEFAULT_HEIGHT;</div><div class='ctx'> 	sink_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='hunk'>@@ -427,15 +441,15 @@ static int rkisp1_isp_init_config(struct v4l2_subdev *sd,</div><div class='ctx'> 	sink_fmt-&gt;ycbcr_enc = V4L2_YCBCR_ENC_601;</div><div class='ctx'> 	sink_fmt-&gt;quantization = V4L2_QUANTIZATION_FULL_RANGE;</div><div class='ctx'> </div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> 	sink_crop-&gt;width = RKISP1_DEFAULT_WIDTH;</div><div class='ctx'> 	sink_crop-&gt;height = RKISP1_DEFAULT_HEIGHT;</div><div class='ctx'> 	sink_crop-&gt;left = 0;</div><div class='ctx'> 	sink_crop-&gt;top = 0;</div><div class='ctx'> </div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	*src_fmt = *sink_fmt;</div><div class='ctx'> 	src_fmt-&gt;code = RKISP1_DEF_SRC_PAD_FMT;</div><div class='ctx'> 	src_fmt-&gt;colorspace = V4L2_COLORSPACE_SRGB;</div><div class='hunk'>@@ -443,15 +457,15 @@ static int rkisp1_isp_init_config(struct v4l2_subdev *sd,</div><div class='ctx'> 	src_fmt-&gt;ycbcr_enc = V4L2_YCBCR_ENC_601;</div><div class='ctx'> 	src_fmt-&gt;quantization = V4L2_QUANTIZATION_LIM_RANGE;</div><div class='ctx'> </div><div class='del'>-	src_crop = v4l2_subdev_get_pad_crop(sd, sd_state,</div><div class='del'>-					    RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					      RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	*src_crop = *sink_crop;</div><div class='ctx'> </div><div class='ctx'> 	/* Parameters and statistics. */</div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_PARAMS);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_STATS);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_PARAMS);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_STATS);</div><div class='ctx'> 	sink_fmt-&gt;width = 0;</div><div class='ctx'> 	sink_fmt-&gt;height = 0;</div><div class='ctx'> 	sink_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='hunk'>@@ -472,12 +486,12 @@ static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp,</div><div class='ctx'> 	const struct v4l2_rect *src_crop;</div><div class='ctx'> 	bool set_csc;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='del'>-	src_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					    RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					      RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Media bus code. The ISP can operate in pass-through mode (Bayer in,</div><div class='hunk'>@@ -570,10 +584,10 @@ static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,</div><div class='ctx'> 	const struct v4l2_rect *sink_crop;</div><div class='ctx'> 	struct v4l2_rect *src_crop;</div><div class='ctx'> </div><div class='del'>-	src_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					    RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	src_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					      RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> </div><div class='ctx'> 	src_crop-&gt;left = ALIGN(r-&gt;left, 2);</div><div class='ctx'> 	src_crop-&gt;width = ALIGN(r-&gt;width, 2);</div><div class='hunk'>@@ -584,8 +598,8 @@ static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,</div><div class='ctx'> 	*r = *src_crop;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate to out format */</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	rkisp1_isp_set_src_fmt(isp, sd_state, src_fmt);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -596,10 +610,10 @@ static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,</div><div class='ctx'> 	struct v4l2_rect *sink_crop, *src_crop;</div><div class='ctx'> 	const struct v4l2_mbus_framefmt *sink_fmt;</div><div class='ctx'> </div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> </div><div class='ctx'> 	sink_crop-&gt;left = ALIGN(r-&gt;left, 2);</div><div class='ctx'> 	sink_crop-&gt;width = ALIGN(r-&gt;width, 2);</div><div class='hunk'>@@ -610,8 +624,8 @@ static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,</div><div class='ctx'> 	*r = *sink_crop;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate to out crop */</div><div class='del'>-	src_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					    RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='add'>+	src_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					      RKISP1_ISP_PAD_SOURCE_VIDEO);</div><div class='ctx'> 	rkisp1_isp_set_src_crop(isp, sd_state, src_crop);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -624,8 +638,8 @@ static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,</div><div class='ctx'> 	struct v4l2_rect *sink_crop;</div><div class='ctx'> 	bool is_yuv;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> 	sink_fmt-&gt;code = format-&gt;code;</div><div class='ctx'> 	mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt-&gt;code);</div><div class='ctx'> 	if (!mbus_info || !(mbus_info-&gt;direction &amp; RKISP1_ISP_SD_SINK)) {</div><div class='hunk'>@@ -673,8 +687,8 @@ static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,</div><div class='ctx'> 	*format = *sink_fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* Propagate to in crop */</div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;isp-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+					       RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> 	rkisp1_isp_set_sink_crop(isp, sd_state, sink_crop);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -689,7 +703,8 @@ static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	else if (fmt-&gt;pad == RKISP1_ISP_PAD_SOURCE_VIDEO)</div><div class='ctx'> 		rkisp1_isp_set_src_fmt(isp, sd_state, &amp;fmt-&gt;format);</div><div class='ctx'> 	else</div><div class='del'>-		fmt-&gt;format = *v4l2_subdev_get_pad_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							    fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -709,19 +724,19 @@ static int rkisp1_isp_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (sel-&gt;pad == RKISP1_ISP_PAD_SINK_VIDEO) {</div><div class='ctx'> 			struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-			fmt = v4l2_subdev_get_pad_format(sd, sd_state, sel-&gt;pad);</div><div class='add'>+			fmt = v4l2_subdev_state_get_format(sd_state, sel-&gt;pad);</div><div class='ctx'> 			sel-&gt;r.height = fmt-&gt;height;</div><div class='ctx'> 			sel-&gt;r.width = fmt-&gt;width;</div><div class='ctx'> 			sel-&gt;r.left = 0;</div><div class='ctx'> 			sel-&gt;r.top = 0;</div><div class='ctx'> 		} else {</div><div class='del'>-			sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, sd_state,</div><div class='del'>-							   RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='add'>+			sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+							     RKISP1_ISP_PAD_SINK_VIDEO);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='hunk'>@@ -768,7 +783,6 @@ static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = {</div><div class='ctx'> 	.enum_frame_size = rkisp1_isp_enum_frame_size,</div><div class='ctx'> 	.get_selection = rkisp1_isp_get_selection,</div><div class='ctx'> 	.set_selection = rkisp1_isp_set_selection,</div><div class='del'>-	.init_cfg = rkisp1_isp_init_config,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = rkisp1_isp_set_fmt,</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate_default,</div><div class='hunk'>@@ -879,6 +893,10 @@ static const struct v4l2_subdev_ops rkisp1_isp_ops = {</div><div class='ctx'> 	.pad = &amp;rkisp1_isp_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops rkisp1_isp_internal_ops = {</div><div class='add'>+	.init_state = rkisp1_isp_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int rkisp1_isp_register(struct rkisp1_device *rkisp1)</div><div class='ctx'> {</div><div class='ctx'> 	struct rkisp1_isp *isp = &amp;rkisp1-&gt;isp;</div><div class='hunk'>@@ -889,6 +907,7 @@ int rkisp1_isp_register(struct rkisp1_device *rkisp1)</div><div class='ctx'> 	isp-&gt;rkisp1 = rkisp1;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;rkisp1_isp_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;rkisp1_isp_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	sd-&gt;entity.ops = &amp;rkisp1_isp_media_ops;</div><div class='ctx'> 	sd-&gt;entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;</div><div class='hunk'>@@ -933,6 +952,7 @@ void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	v4l2_device_unregister_subdev(&amp;isp-&gt;sd);</div><div class='add'>+	v4l2_subdev_cleanup(&amp;isp-&gt;sd);</div><div class='ctx'> 	media_entity_cleanup(&amp;isp-&gt;sd.entity);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -989,6 +1009,8 @@ irqreturn_t rkisp1_isp_isr(int irq, void *ctx)</div><div class='ctx'> 	if (status &amp; RKISP1_CIF_ISP_FRAME) {</div><div class='ctx'> 		u32 isp_ris;</div><div class='ctx'> </div><div class='add'>+		rkisp1-&gt;debug.complete_frames++;</div><div class='add'>+</div><div class='ctx'> 		/* New frame from the sensor received */</div><div class='ctx'> 		isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS);</div><div class='ctx'> 		if (isp_ris &amp; RKISP1_STATS_MEAS_MASK)</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h<br/>index 350f452e676f..bea69a0d766a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h</a></div><div class='hunk'>@@ -172,12 +172,9 @@</div><div class='ctx'> #define RKISP1_CIF_MI_FRAME(stream)			BIT((stream)-&gt;id)</div><div class='ctx'> #define RKISP1_CIF_MI_MBLK_LINE				BIT(2)</div><div class='ctx'> #define RKISP1_CIF_MI_FILL_MP_Y				BIT(3)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_MP_Y				BIT(4)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_MP_CB			BIT(5)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_MP_CR			BIT(6)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_SP_Y				BIT(7)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_SP_CB			BIT(8)</div><div class='del'>-#define RKISP1_CIF_MI_WRAP_SP_CR			BIT(9)</div><div class='add'>+#define RKISP1_CIF_MI_WRAP_Y(stream)			BIT(4 + (stream)-&gt;id * 3)</div><div class='add'>+#define RKISP1_CIF_MI_WRAP_CB(stream)			BIT(5 + (stream)-&gt;id * 3)</div><div class='add'>+#define RKISP1_CIF_MI_WRAP_CR(stream)			BIT(6 + (stream)-&gt;id * 3)</div><div class='ctx'> #define RKISP1_CIF_MI_DMA_READY				BIT(11)</div><div class='ctx'> </div><div class='ctx'> /* MI_STATUS */</div><div class='head'>diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c<br/>index 28ecc7347d54..a8e377701302 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c</a></div><div class='hunk'>@@ -142,10 +142,8 @@ static void rkisp1_dcrop_config(struct rkisp1_resizer *rsz,</div><div class='ctx'> 	struct v4l2_rect *sink_crop;</div><div class='ctx'> 	u32 dc_ctrl;</div><div class='ctx'> </div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SINK);</div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	if (sink_crop-&gt;width == sink_fmt-&gt;width &amp;&amp;</div><div class='ctx'> 	    sink_crop-&gt;height == sink_fmt-&gt;height &amp;&amp;</div><div class='hunk'>@@ -275,10 +273,8 @@ static void rkisp1_rsz_config(struct rkisp1_resizer *rsz,</div><div class='ctx'> 	struct v4l2_area src_y, src_c;</div><div class='ctx'> 	struct v4l2_rect sink_c;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SRC);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SRC);</div><div class='ctx'> </div><div class='ctx'> 	sink_yuv_info = rkisp1_rsz_get_yuv_mbus_info(sink_fmt-&gt;code);</div><div class='ctx'> 	src_yuv_info = rkisp1_rsz_get_yuv_mbus_info(src_fmt-&gt;code);</div><div class='hunk'>@@ -292,8 +288,7 @@ static void rkisp1_rsz_config(struct rkisp1_resizer *rsz,</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	sink_y = v4l2_subdev_get_pad_crop(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					  RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_y = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> 	sink_c.width = sink_y-&gt;width / sink_yuv_info-&gt;hdiv;</div><div class='ctx'> 	sink_c.height = sink_y-&gt;height / sink_yuv_info-&gt;vdiv;</div><div class='ctx'> </div><div class='hunk'>@@ -335,12 +330,8 @@ static int rkisp1_rsz_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> {</div><div class='ctx'> 	struct rkisp1_resizer *rsz =</div><div class='ctx'> 		container_of(sd, struct rkisp1_resizer, sd);</div><div class='del'>-	struct v4l2_subdev_pad_config dummy_cfg;</div><div class='del'>-	struct v4l2_subdev_state pad_state = {</div><div class='del'>-		.pads = &amp;dummy_cfg</div><div class='del'>-	};</div><div class='del'>-	u32 pad = code-&gt;pad;</div><div class='del'>-	int ret;</div><div class='add'>+	unsigned int index = code-&gt;index;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	if (code-&gt;pad == RKISP1_RSZ_PAD_SRC) {</div><div class='ctx'> 		/* supported mbus codes on the src are the same as in the capture */</div><div class='hunk'>@@ -360,25 +351,38 @@ static int rkisp1_rsz_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* supported mbus codes on the sink pad are the same as isp src pad */</div><div class='del'>-	code-&gt;pad = RKISP1_ISP_PAD_SOURCE_VIDEO;</div><div class='del'>-	ret = v4l2_subdev_call(&amp;rsz-&gt;rkisp1-&gt;isp.sd, pad, enum_mbus_code,</div><div class='del'>-			       &amp;pad_state, code);</div><div class='add'>+	/*</div><div class='add'>+	 * Supported mbus codes on the sink pad are the same as on the ISP</div><div class='add'>+	 * source pad.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; ; i++) {</div><div class='add'>+		const struct rkisp1_mbus_info *fmt =</div><div class='add'>+			rkisp1_mbus_info_get_by_index(i);</div><div class='add'>+</div><div class='add'>+		if (!fmt)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-	/* restore pad */</div><div class='del'>-	code-&gt;pad = pad;</div><div class='del'>-	code-&gt;flags = 0;</div><div class='del'>-	return ret;</div><div class='add'>+		if (!(fmt-&gt;direction &amp; RKISP1_ISP_SD_SRC))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (!index) {</div><div class='add'>+			code-&gt;code = fmt-&gt;mbus_code;</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		index--;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rkisp1_rsz_init_config(struct v4l2_subdev *sd,</div><div class='del'>-				  struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int rkisp1_rsz_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;</div><div class='ctx'> 	struct v4l2_rect *sink_crop;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SRC);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SRC);</div><div class='ctx'> 	sink_fmt-&gt;width = RKISP1_DEFAULT_WIDTH;</div><div class='ctx'> 	sink_fmt-&gt;height = RKISP1_DEFAULT_HEIGHT;</div><div class='ctx'> 	sink_fmt-&gt;field = V4L2_FIELD_NONE;</div><div class='hunk'>@@ -388,15 +392,13 @@ static int rkisp1_rsz_init_config(struct v4l2_subdev *sd,</div><div class='ctx'> 	sink_fmt-&gt;ycbcr_enc = V4L2_YCBCR_ENC_601;</div><div class='ctx'> 	sink_fmt-&gt;quantization = V4L2_QUANTIZATION_LIM_RANGE;</div><div class='ctx'> </div><div class='del'>-	sink_crop = v4l2_subdev_get_try_crop(sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> 	sink_crop-&gt;width = RKISP1_DEFAULT_WIDTH;</div><div class='ctx'> 	sink_crop-&gt;height = RKISP1_DEFAULT_HEIGHT;</div><div class='ctx'> 	sink_crop-&gt;left = 0;</div><div class='ctx'> 	sink_crop-&gt;top = 0;</div><div class='ctx'> </div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> 	*src_fmt = *sink_fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* NOTE: there is no crop in the source pad, only in the sink */</div><div class='hunk'>@@ -411,10 +413,8 @@ static void rkisp1_rsz_set_src_fmt(struct rkisp1_resizer *rsz,</div><div class='ctx'> 	const struct rkisp1_mbus_info *sink_mbus_info;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *src_fmt, *sink_fmt;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SRC);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SRC);</div><div class='ctx'> </div><div class='ctx'> 	sink_mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt-&gt;code);</div><div class='ctx'> </div><div class='hunk'>@@ -441,10 +441,8 @@ static void rkisp1_rsz_set_sink_crop(struct rkisp1_resizer *rsz,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='ctx'> 	struct v4l2_rect *sink_crop;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SINK);</div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	/* Not crop for MP bayer raw data */</div><div class='ctx'> 	mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt-&gt;code);</div><div class='hunk'>@@ -478,12 +476,9 @@ static void rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer *rsz,</div><div class='ctx'> 	struct v4l2_rect *sink_crop;</div><div class='ctx'> 	bool is_yuv;</div><div class='ctx'> </div><div class='del'>-	sink_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					      RKISP1_RSZ_PAD_SINK);</div><div class='del'>-	src_fmt = v4l2_subdev_get_pad_format(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SRC);</div><div class='del'>-	sink_crop = v4l2_subdev_get_pad_crop(&amp;rsz-&gt;sd, sd_state,</div><div class='del'>-					     RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SRC);</div><div class='add'>+	sink_crop = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	if (rsz-&gt;id == RKISP1_SELFPATH)</div><div class='ctx'> 		sink_fmt-&gt;code = MEDIA_BUS_FMT_YUYV8_2X8;</div><div class='hunk'>@@ -573,8 +568,8 @@ static int rkisp1_rsz_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='del'>-		mf_sink = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-						     RKISP1_RSZ_PAD_SINK);</div><div class='add'>+		mf_sink = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+						       RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> 		sel-&gt;r.height = mf_sink-&gt;height;</div><div class='ctx'> 		sel-&gt;r.width = mf_sink-&gt;width;</div><div class='ctx'> 		sel-&gt;r.left = 0;</div><div class='hunk'>@@ -582,8 +577,8 @@ static int rkisp1_rsz_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_pad_crop(sd, sd_state,</div><div class='del'>-						   RKISP1_RSZ_PAD_SINK);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+						     RKISP1_RSZ_PAD_SINK);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='hunk'>@@ -620,7 +615,6 @@ static const struct v4l2_subdev_pad_ops rkisp1_rsz_pad_ops = {</div><div class='ctx'> 	.enum_mbus_code = rkisp1_rsz_enum_mbus_code,</div><div class='ctx'> 	.get_selection = rkisp1_rsz_get_selection,</div><div class='ctx'> 	.set_selection = rkisp1_rsz_set_selection,</div><div class='del'>-	.init_cfg = rkisp1_rsz_init_config,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = rkisp1_rsz_set_fmt,</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate_default,</div><div class='hunk'>@@ -667,6 +661,10 @@ static const struct v4l2_subdev_ops rkisp1_rsz_ops = {</div><div class='ctx'> 	.pad = &amp;rkisp1_rsz_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops rkisp1_rsz_internal_ops = {</div><div class='add'>+	.init_state = rkisp1_rsz_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void rkisp1_rsz_unregister(struct rkisp1_resizer *rsz)</div><div class='ctx'> {</div><div class='ctx'> 	if (!rsz-&gt;rkisp1)</div><div class='hunk'>@@ -696,6 +694,7 @@ static int rkisp1_rsz_register(struct rkisp1_resizer *rsz)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;rkisp1_rsz_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;rkisp1_rsz_internal_ops;</div><div class='ctx'> 	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	sd-&gt;entity.ops = &amp;rkisp1_rsz_media_ops;</div><div class='ctx'> 	sd-&gt;entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos-gsc/gsc-core.h b/drivers/media/platform/samsung/exynos-gsc/gsc-core.h<br/>index 1ea5fa1bf3c8..b9777e07fb6d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos-gsc/gsc-core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos-gsc/gsc-core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos-gsc/gsc-core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos-gsc/gsc-core.h</a></div><div class='hunk'>@@ -26,7 +26,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "gsc-regs.h"</div><div class='ctx'> </div><div class='del'>-#define CONFIG_VB2_GSC_DMA_CONTIG	1</div><div class='ctx'> #define GSC_MODULE_NAME			"exynos-gsc"</div><div class='ctx'> </div><div class='ctx'> #define GSC_SHUTDOWN_TIMEOUT		((100*HZ)/1000)</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-capture.c b/drivers/media/platform/samsung/exynos4-is/fimc-capture.c<br/>index a0d43bf892e6..05cafba1c728 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/fimc-capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-capture.c</a></div><div class='hunk'>@@ -1479,7 +1479,7 @@ static int fimc_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1534,7 +1534,7 @@ static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	mf-&gt;colorspace = V4L2_COLORSPACE_JPEG;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1604,10 +1604,10 @@ static int fimc_subdev_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		try_sel = v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		try_sel = v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		try_sel = v4l2_subdev_get_try_compose(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		try_sel = v4l2_subdev_state_get_compose(sd_state, sel-&gt;pad);</div><div class='ctx'> 		f = &amp;ctx-&gt;d_frame;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1651,10 +1651,10 @@ static int fimc_subdev_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	switch (sel-&gt;target) {</div><div class='ctx'> 	case V4L2_SEL_TGT_CROP:</div><div class='del'>-		try_sel = v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		try_sel = v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case V4L2_SEL_TGT_COMPOSE:</div><div class='del'>-		try_sel = v4l2_subdev_get_try_compose(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		try_sel = v4l2_subdev_state_get_compose(sd_state, sel-&gt;pad);</div><div class='ctx'> 		f = &amp;ctx-&gt;d_frame;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-core.c b/drivers/media/platform/samsung/exynos4-is/fimc-core.c<br/>index 97908778e1c8..0be687b01ce5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/fimc-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-core.c</a></div><div class='hunk'>@@ -814,7 +814,7 @@ err:</div><div class='ctx'> 	fimc_clk_put(fimc);</div><div class='ctx'> 	dev_err(&amp;fimc-&gt;pdev-&gt;dev, "failed to get clock: %s\n",</div><div class='ctx'> 		fimc_clocks[i]);</div><div class='del'>-	return -ENXIO;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c b/drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c<br/>index bef6e9b4a25e..44363c4241d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-is-i2c.c</a></div><div class='hunk'>@@ -57,7 +57,6 @@ static int fimc_is_i2c_probe(struct platform_device *pdev)</div><div class='ctx'> 	strscpy(i2c_adap-&gt;name, "exynos4x12-isp-i2c", sizeof(i2c_adap-&gt;name));</div><div class='ctx'> 	i2c_adap-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	i2c_adap-&gt;algo = &amp;fimc_is_i2c_algorithm;</div><div class='del'>-	i2c_adap-&gt;class = I2C_CLASS_SPD;</div><div class='ctx'> </div><div class='ctx'> 	platform_set_drvdata(pdev, isp_i2c);</div><div class='ctx'> 	pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-isp.c b/drivers/media/platform/samsung/exynos4-is/fimc-isp.c<br/>index b85986e50f46..3c5d7bee2655 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-isp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/fimc-isp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-isp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-isp.c</a></div><div class='hunk'>@@ -126,7 +126,7 @@ static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf = &amp;fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*mf = *v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		*mf = *v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -172,9 +172,8 @@ static void __isp_subdev_try_format(struct fimc_isp *isp,</div><div class='ctx'> 		mf-&gt;code = MEDIA_BUS_FMT_SGRBG10_1X10;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-			format = v4l2_subdev_get_try_format(&amp;isp-&gt;subdev,</div><div class='del'>-							    sd_state,</div><div class='del'>-							    FIMC_ISP_SD_PAD_SINK);</div><div class='add'>+			format = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+							      FIMC_ISP_SD_PAD_SINK);</div><div class='ctx'> 		else</div><div class='ctx'> 			format = &amp;isp-&gt;sink_fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -207,7 +206,7 @@ static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	__isp_subdev_try_format(isp, sd_state, fmt);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 		/* Propagate format to the source pads */</div><div class='hunk'>@@ -220,8 +219,8 @@ static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 				format.pad = pad;</div><div class='ctx'> 				__isp_subdev_try_format(isp, sd_state,</div><div class='ctx'> 							&amp;format);</div><div class='del'>-				mf = v4l2_subdev_get_try_format(sd, sd_state,</div><div class='del'>-								pad);</div><div class='add'>+				mf = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								  pad);</div><div class='ctx'> 				*mf = format.format;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -374,18 +373,17 @@ static int fimc_isp_subdev_open(struct v4l2_subdev *sd,</div><div class='ctx'> 		.field = V4L2_FIELD_NONE,</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, fh-&gt;state,</div><div class='del'>-					    FIMC_ISP_SD_PAD_SINK);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state, FIMC_ISP_SD_PAD_SINK);</div><div class='ctx'> 	*format = fmt;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, fh-&gt;state,</div><div class='del'>-					    FIMC_ISP_SD_PAD_SRC_FIFO);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state,</div><div class='add'>+					      FIMC_ISP_SD_PAD_SRC_FIFO);</div><div class='ctx'> 	fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;</div><div class='ctx'> 	fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;</div><div class='ctx'> 	*format = fmt;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(sd, fh-&gt;state,</div><div class='del'>-					    FIMC_ISP_SD_PAD_SRC_DMA);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state,</div><div class='add'>+					      FIMC_ISP_SD_PAD_SRC_DMA);</div><div class='ctx'> 	*format = fmt;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-lite.c b/drivers/media/platform/samsung/exynos4-is/fimc-lite.c<br/>index 9396b10b5b1c..7898c9bebb04 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-lite.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/fimc-lite.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/fimc-lite.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/fimc-lite.c</a></div><div class='hunk'>@@ -574,16 +574,14 @@ static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc,</div><div class='ctx'> 		struct v4l2_rect *rect;</div><div class='ctx'> </div><div class='ctx'> 		if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-			sink_fmt = v4l2_subdev_get_try_format(&amp;fimc-&gt;subdev,</div><div class='del'>-							      sd_state,</div><div class='del'>-							      FLITE_SD_PAD_SINK);</div><div class='add'>+			sink_fmt = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								FLITE_SD_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 			mf-&gt;code = sink_fmt-&gt;code;</div><div class='ctx'> 			mf-&gt;colorspace = sink_fmt-&gt;colorspace;</div><div class='ctx'> </div><div class='del'>-			rect = v4l2_subdev_get_try_crop(&amp;fimc-&gt;subdev,</div><div class='del'>-							sd_state,</div><div class='del'>-							FLITE_SD_PAD_SINK);</div><div class='add'>+			rect = v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+							  FLITE_SD_PAD_SINK);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			mf-&gt;code = sink-&gt;fmt-&gt;mbus_code;</div><div class='ctx'> 			mf-&gt;colorspace = sink-&gt;fmt-&gt;colorspace;</div><div class='hunk'>@@ -1021,7 +1019,7 @@ static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt(</div><div class='ctx'> 	if (pad != FLITE_SD_PAD_SINK)</div><div class='ctx'> 		pad = FLITE_SD_PAD_SOURCE_DMA;</div><div class='ctx'> </div><div class='del'>-	return v4l2_subdev_get_try_format(sd, sd_state, pad);</div><div class='add'>+	return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='hunk'>@@ -1129,7 +1127,7 @@ static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1166,7 +1164,7 @@ static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	fimc_lite_try_crop(fimc, &amp;sel-&gt;r);</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad) = sel-&gt;r;</div><div class='add'>+		*v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad) = sel-&gt;r;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		unsigned long flags;</div><div class='ctx'> 		spin_lock_irqsave(&amp;fimc-&gt;slock, flags);</div><div class='head'>diff --git a/drivers/media/platform/samsung/exynos4-is/mipi-csis.c b/drivers/media/platform/samsung/exynos4-is/mipi-csis.c<br/>index 686ca8753ba2..aae8a8b2c0f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/mipi-csis.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/exynos4-is/mipi-csis.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/exynos4-is/mipi-csis.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/exynos4-is/mipi-csis.c</a></div><div class='hunk'>@@ -569,8 +569,7 @@ static struct v4l2_mbus_framefmt *__s5pcsis_get_format(</div><div class='ctx'> 		enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return sd_state ? v4l2_subdev_get_try_format(&amp;state-&gt;sd,</div><div class='del'>-							     sd_state, 0) : NULL;</div><div class='add'>+		return sd_state ? v4l2_subdev_state_get_format(sd_state, 0) : NULL;</div><div class='ctx'> </div><div class='ctx'> 	return &amp;state-&gt;format;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/platform/samsung/s3c-camif/camif-capture.c b/drivers/media/platform/samsung/s3c-camif/camif-capture.c<br/>index 0f5b3845d7b9..be58260ea67e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s3c-camif/camif-capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s3c-camif/camif-capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s3c-camif/camif-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s3c-camif/camif-capture.c</a></div><div class='hunk'>@@ -1216,7 +1216,7 @@ static int s3c_camif_subdev_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf = &amp;fmt-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		fmt-&gt;format = *mf;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1305,7 +1305,7 @@ static int s3c_camif_subdev_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 	__camif_subdev_try_format(camif, mf, fmt-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 		*mf = fmt-&gt;format;</div><div class='ctx'> 		mutex_unlock(&amp;camif-&gt;lock);</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1357,7 +1357,7 @@ static int s3c_camif_subdev_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		sel-&gt;r = *v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad);</div><div class='add'>+		sel-&gt;r = *v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1445,7 +1445,7 @@ static int s3c_camif_subdev_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	__camif_try_crop(camif, &amp;sel-&gt;r);</div><div class='ctx'> </div><div class='ctx'> 	if (sel-&gt;which == V4L2_SUBDEV_FORMAT_TRY) {</div><div class='del'>-		*v4l2_subdev_get_try_crop(sd, sd_state, sel-&gt;pad) = sel-&gt;r;</div><div class='add'>+		*v4l2_subdev_state_get_crop(sd_state, sel-&gt;pad) = sel-&gt;r;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		unsigned long flags;</div><div class='ctx'> 		unsigned int i;</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h<br/>new file mode 100644<br/>index 000000000000..24e669d8ea29<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h</a></div><div class='hunk'>@@ -0,0 +1,52 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Register definition file for Samsung MFC V12.x Interface (FIMV) driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2020 Samsung Electronics Co., Ltd.</div><div class='add'>+ *     http://www.samsung.com/</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _REGS_MFC_V12_H</div><div class='add'>+#define _REGS_MFC_V12_H</div><div class='add'>+</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+#include "regs-mfc-v10.h"</div><div class='add'>+</div><div class='add'>+/* MFCv12 Context buffer sizes */</div><div class='add'>+#define MFC_CTX_BUF_SIZE_V12		(30 * SZ_1K)</div><div class='add'>+#define MFC_H264_DEC_CTX_BUF_SIZE_V12	(2 * SZ_1M)</div><div class='add'>+#define MFC_OTHER_DEC_CTX_BUF_SIZE_V12	(30 * SZ_1K)</div><div class='add'>+#define MFC_H264_ENC_CTX_BUF_SIZE_V12	(100 * SZ_1K)</div><div class='add'>+#define MFC_HEVC_ENC_CTX_BUF_SIZE_V12	(40 * SZ_1K)</div><div class='add'>+#define MFC_OTHER_ENC_CTX_BUF_SIZE_V12	(25 * SZ_1K)</div><div class='add'>+</div><div class='add'>+/* MFCv12 variant defines */</div><div class='add'>+#define MAX_FW_SIZE_V12			(SZ_1M)</div><div class='add'>+#define MAX_CPB_SIZE_V12		(7 * SZ_1M)</div><div class='add'>+#define MFC_VERSION_V12			0xC0</div><div class='add'>+#define MFC_NUM_PORTS_V12		1</div><div class='add'>+#define S5P_FIMV_CODEC_VP9_ENC		27</div><div class='add'>+#define MFC_CHROMA_PAD_BYTES_V12        256</div><div class='add'>+#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V12 256</div><div class='add'>+</div><div class='add'>+/* Encoder buffer size for MFCv12 */</div><div class='add'>+#define ENC_V120_BASE_SIZE(x, y) \</div><div class='add'>+	((((x) + 3) * ((y) + 3) * 8) \</div><div class='add'>+	+ ((((y) * 64) + 2304) * ((x) + 7) / 8))</div><div class='add'>+</div><div class='add'>+#define ENC_V120_H264_ME_SIZE(x, y) \</div><div class='add'>+	ALIGN((ENC_V120_BASE_SIZE(x, y) \</div><div class='add'>+	+ (DIV_ROUND_UP((x) * (y), 64) * 32)), 256)</div><div class='add'>+</div><div class='add'>+#define ENC_V120_MPEG4_ME_SIZE(x, y) \</div><div class='add'>+	ALIGN((ENC_V120_BASE_SIZE(x, y) \</div><div class='add'>+	+ (DIV_ROUND_UP((x) * (y), 128) * 16)), 256)</div><div class='add'>+</div><div class='add'>+#define ENC_V120_VP8_ME_SIZE(x, y) \</div><div class='add'>+	ALIGN(ENC_V120_BASE_SIZE((x), (y)), 256)</div><div class='add'>+</div><div class='add'>+#define ENC_V120_HEVC_ME_SIZE(x, y)     \</div><div class='add'>+	ALIGN(((((x) + 3) * ((y) + 3) * 32)       \</div><div class='add'>+	+ ((((y) * 128) + 2304) * ((x) + 3) / 4)), 256)</div><div class='add'>+</div><div class='add'>+#endif /*_REGS_MFC_V12_H*/</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h<br/>index 4a7adfdaa359..50f9bf0603c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'> </div><div class='ctx'> #define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7		0xfa70</div><div class='ctx'> #define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7	0xfa74</div><div class='add'>+#define S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7		0xfa78</div><div class='ctx'> </div><div class='ctx'> #define S5P_FIMV_E_VP8_OPTIONS_V7			0xfdb0</div><div class='ctx'> #define S5P_FIMV_E_VP8_FILTER_OPTIONS_V7		0xfdb4</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h<br/>index 162e3c7e920f..0ef9eb2dff22 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h</a></div><div class='hunk'>@@ -17,13 +17,16 @@</div><div class='ctx'> #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8	0xf108</div><div class='ctx'> #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8	0xf144</div><div class='ctx'> #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8	0xf148</div><div class='add'>+#define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8	0xf14C</div><div class='ctx'> #define S5P_FIMV_D_MV_BUFFER_SIZE_V8		0xf150</div><div class='ctx'> </div><div class='ctx'> #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8	0xf138</div><div class='ctx'> #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8	0xf13c</div><div class='add'>+#define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8	0xf140</div><div class='ctx'> </div><div class='ctx'> #define S5P_FIMV_D_FIRST_PLANE_DPB_V8		0xf160</div><div class='ctx'> #define S5P_FIMV_D_SECOND_PLANE_DPB_V8		0xf260</div><div class='add'>+#define S5P_FIMV_D_THIRD_PLANE_DPB_V8		0xf360</div><div class='ctx'> #define S5P_FIMV_D_MV_BUFFER_V8			0xf460</div><div class='ctx'> </div><div class='ctx'> #define S5P_FIMV_D_NUM_MV_V8			0xf134</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c<br/>index e30e54935d79..fbb047eadf5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c</a></div><div class='hunk'>@@ -604,6 +604,8 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> 		s5p_mfc_clock_off();</div><div class='ctx'> </div><div class='ctx'> 		wake_up(&amp;ctx-&gt;queue);</div><div class='add'>+		if (ctx-&gt;src_queue_cnt &gt;= 1 &amp;&amp; ctx-&gt;dst_queue_cnt &gt;= 1)</div><div class='add'>+			set_work_bit_irqsave(ctx);</div><div class='ctx'> 		s5p_mfc_hw_call(dev-&gt;mfc_ops, try_run, dev);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		WARN_ON(test_and_clear_bit(0, &amp;dev-&gt;hw_lock) == 0);</div><div class='hunk'>@@ -790,6 +792,8 @@ static int s5p_mfc_open(struct file *file)</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;ctx-&gt;dst_queue);</div><div class='ctx'> 	ctx-&gt;src_queue_cnt = 0;</div><div class='ctx'> 	ctx-&gt;dst_queue_cnt = 0;</div><div class='add'>+	ctx-&gt;is_422 = 0;</div><div class='add'>+	ctx-&gt;is_10bit = 0;</div><div class='ctx'> 	/* Get context number */</div><div class='ctx'> 	ctx-&gt;num = 0;</div><div class='ctx'> 	while (dev-&gt;ctx[ctx-&gt;num]) {</div><div class='hunk'>@@ -863,7 +867,7 @@ static int s5p_mfc_open(struct file *file)</div><div class='ctx'> 		q-&gt;io_modes = VB2_MMAP;</div><div class='ctx'> 		q-&gt;ops = get_dec_queue_ops();</div><div class='ctx'> 	} else if (vdev == dev-&gt;vfd_enc) {</div><div class='del'>-		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR;</div><div class='add'>+		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;</div><div class='ctx'> 		q-&gt;ops = get_enc_queue_ops();</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = -ENOENT;</div><div class='hunk'>@@ -890,7 +894,7 @@ static int s5p_mfc_open(struct file *file)</div><div class='ctx'> 		q-&gt;io_modes = VB2_MMAP;</div><div class='ctx'> 		q-&gt;ops = get_dec_queue_ops();</div><div class='ctx'> 	} else if (vdev == dev-&gt;vfd_enc) {</div><div class='del'>-		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR;</div><div class='add'>+		q-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;</div><div class='ctx'> 		q-&gt;ops = get_enc_queue_ops();</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = -ENOENT;</div><div class='hunk'>@@ -1660,6 +1664,31 @@ static struct s5p_mfc_variant mfc_drvdata_v10 = {</div><div class='ctx'> 	.fw_name[0]     = "s5p-mfc-v10.fw",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct s5p_mfc_buf_size_v6 mfc_buf_size_v12 = {</div><div class='add'>+	.dev_ctx        = MFC_CTX_BUF_SIZE_V12,</div><div class='add'>+	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V12,</div><div class='add'>+	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V12,</div><div class='add'>+	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V12,</div><div class='add'>+	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V12,</div><div class='add'>+	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V12,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct s5p_mfc_buf_size buf_size_v12 = {</div><div class='add'>+	.fw     = MAX_FW_SIZE_V12,</div><div class='add'>+	.cpb    = MAX_CPB_SIZE_V12,</div><div class='add'>+	.priv   = &amp;mfc_buf_size_v12,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct s5p_mfc_variant mfc_drvdata_v12 = {</div><div class='add'>+	.version        = MFC_VERSION_V12,</div><div class='add'>+	.version_bit    = MFC_V12_BIT,</div><div class='add'>+	.port_num       = MFC_NUM_PORTS_V12,</div><div class='add'>+	.buf_size       = &amp;buf_size_v12,</div><div class='add'>+	.fw_name[0]     = "s5p-mfc-v12.fw",</div><div class='add'>+	.clk_names	= {"mfc"},</div><div class='add'>+	.num_clocks	= 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id exynos_mfc_match[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.compatible = "samsung,mfc-v5",</div><div class='hunk'>@@ -1682,6 +1711,9 @@ static const struct of_device_id exynos_mfc_match[] = {</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.compatible = "samsung,mfc-v10",</div><div class='ctx'> 		.data = &amp;mfc_drvdata_v10,</div><div class='add'>+	}, {</div><div class='add'>+		.compatible = "tesla,fsd-mfc",</div><div class='add'>+		.data = &amp;mfc_drvdata_v12,</div><div class='ctx'> 	},</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h<br/>index 5304f42c8c72..59450b324f7d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h</a></div><div class='hunk'>@@ -19,7 +19,7 @@</div><div class='ctx'> #include &lt;media/v4l2-ioctl.h&gt;</div><div class='ctx'> #include &lt;media/videobuf2-v4l2.h&gt;</div><div class='ctx'> #include "regs-mfc.h"</div><div class='del'>-#include "regs-mfc-v10.h"</div><div class='add'>+#include "regs-mfc-v12.h"</div><div class='ctx'> </div><div class='ctx'> #define S5P_MFC_NAME		"s5p-mfc"</div><div class='ctx'> </div><div class='hunk'>@@ -56,6 +56,7 @@</div><div class='ctx'> #define MFC_NO_INSTANCE_SET	-1</div><div class='ctx'> #define MFC_ENC_CAP_PLANE_COUNT	1</div><div class='ctx'> #define MFC_ENC_OUT_PLANE_COUNT	2</div><div class='add'>+#define VB2_MAX_PLANE_COUNT	3</div><div class='ctx'> #define STUFF_BYTE		4</div><div class='ctx'> #define MFC_MAX_CTRLS		128</div><div class='ctx'> </div><div class='hunk'>@@ -181,6 +182,7 @@ struct s5p_mfc_buf {</div><div class='ctx'> 		struct {</div><div class='ctx'> 			size_t luma;</div><div class='ctx'> 			size_t chroma;</div><div class='add'>+			size_t chroma_1;</div><div class='ctx'> 		} raw;</div><div class='ctx'> 		size_t stream;</div><div class='ctx'> 	} cookie;</div><div class='hunk'>@@ -621,6 +623,10 @@ struct s5p_mfc_codec_ops {</div><div class='ctx'>  *			v4l2 control framework</div><div class='ctx'>  * @ctrl_handler:	handler for v4l2 framework</div><div class='ctx'>  * @scratch_buf_size:	scratch buffer size</div><div class='add'>+ * @is_10bit:		state to check 10bit support</div><div class='add'>+ * @is_422:		state to check YUV422 10bit format</div><div class='add'>+ * @chroma_size_1:	size of a chroma third plane</div><div class='add'>+ * @stride:		size of stride for all planes</div><div class='ctx'>  */</div><div class='ctx'> struct s5p_mfc_ctx {</div><div class='ctx'> 	struct s5p_mfc_dev *dev;</div><div class='hunk'>@@ -657,6 +663,7 @@ struct s5p_mfc_ctx {</div><div class='ctx'> </div><div class='ctx'> 	int luma_size;</div><div class='ctx'> 	int chroma_size;</div><div class='add'>+	int chroma_size_1;</div><div class='ctx'> 	int mv_size;</div><div class='ctx'> </div><div class='ctx'> 	unsigned long consumed_stream;</div><div class='hunk'>@@ -720,6 +727,9 @@ struct s5p_mfc_ctx {</div><div class='ctx'> 	struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];</div><div class='ctx'> 	struct v4l2_ctrl_handler ctrl_handler;</div><div class='ctx'> 	size_t scratch_buf_size;</div><div class='add'>+	int is_10bit;</div><div class='add'>+	int is_422;</div><div class='add'>+	int stride[VB2_MAX_PLANE_COUNT];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -771,22 +781,27 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);</div><div class='ctx'> #define HAS_PORTNUM(dev)	(dev ? (dev-&gt;variant ? \</div><div class='ctx'> 				(dev-&gt;variant-&gt;port_num ? 1 : 0) : 0) : 0)</div><div class='ctx'> #define IS_TWOPORT(dev)		(dev-&gt;variant-&gt;port_num == 2 ? 1 : 0)</div><div class='del'>-#define IS_MFCV6_PLUS(dev)	(dev-&gt;variant-&gt;version &gt;= 0x60 ? 1 : 0)</div><div class='del'>-#define IS_MFCV7_PLUS(dev)	(dev-&gt;variant-&gt;version &gt;= 0x70 ? 1 : 0)</div><div class='del'>-#define IS_MFCV8_PLUS(dev)	(dev-&gt;variant-&gt;version &gt;= 0x80 ? 1 : 0)</div><div class='del'>-#define IS_MFCV10(dev)		(dev-&gt;variant-&gt;version &gt;= 0xA0 ? 1 : 0)</div><div class='del'>-#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))</div><div class='add'>+#define IS_MFCV6_PLUS(dev)	((dev)-&gt;variant-&gt;version &gt;= 0x60)</div><div class='add'>+#define IS_MFCV7_PLUS(dev)	((dev)-&gt;variant-&gt;version &gt;= 0x70)</div><div class='add'>+#define IS_MFCV8_PLUS(dev)	((dev)-&gt;variant-&gt;version &gt;= 0x80)</div><div class='add'>+#define IS_MFCV10_PLUS(dev)	((dev)-&gt;variant-&gt;version &gt;= 0xA0)</div><div class='add'>+#define IS_MFCV12(dev)		((dev)-&gt;variant-&gt;version &gt;= 0xC0)</div><div class='add'>+#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev))</div><div class='ctx'> </div><div class='ctx'> #define MFC_V5_BIT	BIT(0)</div><div class='ctx'> #define MFC_V6_BIT	BIT(1)</div><div class='ctx'> #define MFC_V7_BIT	BIT(2)</div><div class='ctx'> #define MFC_V8_BIT	BIT(3)</div><div class='ctx'> #define MFC_V10_BIT	BIT(5)</div><div class='add'>+#define MFC_V12_BIT	BIT(7)</div><div class='ctx'> </div><div class='ctx'> #define MFC_V5PLUS_BITS		(MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \</div><div class='del'>-					MFC_V8_BIT | MFC_V10_BIT)</div><div class='add'>+					MFC_V8_BIT | MFC_V10_BIT | MFC_V12_BIT)</div><div class='ctx'> #define MFC_V6PLUS_BITS		(MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \</div><div class='del'>-					MFC_V10_BIT)</div><div class='del'>-#define MFC_V7PLUS_BITS		(MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)</div><div class='add'>+					MFC_V10_BIT | MFC_V12_BIT)</div><div class='add'>+#define MFC_V7PLUS_BITS		(MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT | \</div><div class='add'>+					MFC_V12_BIT)</div><div class='add'>+</div><div class='add'>+#define MFC_V10PLUS_BITS	(MFC_V10_BIT | MFC_V12_BIT)</div><div class='ctx'> </div><div class='ctx'> #endif /* S5P_MFC_COMMON_H_ */</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c<br/>index 6d3c92045c05..503487f34a80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c</a></div><div class='hunk'>@@ -51,8 +51,14 @@ int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)</div><div class='ctx'> 	 * into kernel. */</div><div class='ctx'> 	mfc_debug_enter();</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;fw_get_done)</div><div class='del'>-		return 0;</div><div class='add'>+	/* In case of MFC v12, RET_SYS_INIT response from hardware fails due to</div><div class='add'>+	 * incorrect firmware transfer and therefore it is not able to initialize</div><div class='add'>+	 * the hardware. This causes failed response for SYS_INIT command when</div><div class='add'>+	 * MFC runs for second time. So, load the MFC v12 firmware for each run.</div><div class='add'>+	 */</div><div class='add'>+	if (!IS_MFCV12(dev))</div><div class='add'>+		if (dev-&gt;fw_get_done)</div><div class='add'>+			return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = MFC_FW_MAX_VERSIONS - 1; i &gt;= 0; i--) {</div><div class='ctx'> 		if (!dev-&gt;variant-&gt;fw_name[i])</div><div class='hunk'>@@ -130,7 +136,7 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev)</div><div class='ctx'> 			mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));</div><div class='ctx'> </div><div class='ctx'> 		/* check bus reset control before reset */</div><div class='del'>-		if (dev-&gt;risc_on)</div><div class='add'>+		if (dev-&gt;risc_on &amp;&amp; !IS_MFCV12(dev))</div><div class='ctx'> 			if (s5p_mfc_bus_reset(dev))</div><div class='ctx'> 				return -EIO;</div><div class='ctx'> 		/* Reset</div><div class='hunk'>@@ -236,7 +242,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)</div><div class='ctx'> 	else</div><div class='ctx'> 		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);</div><div class='ctx'> </div><div class='del'>-	if (IS_MFCV10(dev))</div><div class='add'>+	if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);</div><div class='ctx'> </div><div class='ctx'> 	mfc_debug(2, "Will now wait for completion of firmware transfer\n");</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c<br/>index 268ffe4da53c..3957f28d4547 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c</a></div><div class='hunk'>@@ -57,6 +57,20 @@ static struct s5p_mfc_fmt formats[] = {</div><div class='ctx'> 		.versions	= MFC_V6PLUS_BITS,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		.fourcc         = V4L2_PIX_FMT_YUV420M,</div><div class='add'>+		.codec_mode     = S5P_MFC_CODEC_NONE,</div><div class='add'>+		.type           = MFC_FMT_RAW,</div><div class='add'>+		.num_planes     = 3,</div><div class='add'>+		.versions       = MFC_V12_BIT,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.fourcc         = V4L2_PIX_FMT_YVU420M,</div><div class='add'>+		.codec_mode     = S5P_MFC_CODEC_NONE,</div><div class='add'>+		.type           = MFC_FMT_RAW,</div><div class='add'>+		.num_planes     = 3,</div><div class='add'>+		.versions       = MFC_V12_BIT</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		.fourcc		= V4L2_PIX_FMT_H264,</div><div class='ctx'> 		.codec_mode	= S5P_MFC_CODEC_H264_DEC,</div><div class='ctx'> 		.type		= MFC_FMT_DEC,</div><div class='hunk'>@@ -146,7 +160,7 @@ static struct s5p_mfc_fmt formats[] = {</div><div class='ctx'> 		.codec_mode	= S5P_FIMV_CODEC_HEVC_DEC,</div><div class='ctx'> 		.type		= MFC_FMT_DEC,</div><div class='ctx'> 		.num_planes	= 1,</div><div class='del'>-		.versions	= MFC_V10_BIT,</div><div class='add'>+		.versions	= MFC_V10PLUS_BITS,</div><div class='ctx'> 		.flags		= V4L2_FMT_FLAG_DYN_RESOLUTION |</div><div class='ctx'> 				  V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM,</div><div class='ctx'> 	},</div><div class='hunk'>@@ -155,7 +169,7 @@ static struct s5p_mfc_fmt formats[] = {</div><div class='ctx'> 		.codec_mode	= S5P_FIMV_CODEC_VP9_DEC,</div><div class='ctx'> 		.type		= MFC_FMT_DEC,</div><div class='ctx'> 		.num_planes	= 1,</div><div class='del'>-		.versions	= MFC_V10_BIT,</div><div class='add'>+		.versions	= MFC_V10PLUS_BITS,</div><div class='ctx'> 		.flags		= V4L2_FMT_FLAG_DYN_RESOLUTION,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='hunk'>@@ -355,14 +369,19 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)</div><div class='ctx'> 		pix_mp-&gt;width = ctx-&gt;buf_width;</div><div class='ctx'> 		pix_mp-&gt;height = ctx-&gt;buf_height;</div><div class='ctx'> 		pix_mp-&gt;field = V4L2_FIELD_NONE;</div><div class='del'>-		pix_mp-&gt;num_planes = 2;</div><div class='add'>+		pix_mp-&gt;num_planes = ctx-&gt;dst_fmt-&gt;num_planes;</div><div class='ctx'> 		/* Set pixelformat to the format in which MFC</div><div class='ctx'> 		   outputs the decoded frame */</div><div class='ctx'> 		pix_mp-&gt;pixelformat = ctx-&gt;dst_fmt-&gt;fourcc;</div><div class='del'>-		pix_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;stride[0];</div><div class='ctx'> 		pix_mp-&gt;plane_fmt[0].sizeimage = ctx-&gt;luma_size;</div><div class='del'>-		pix_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;stride[1];</div><div class='ctx'> 		pix_mp-&gt;plane_fmt[1].sizeimage = ctx-&gt;chroma_size;</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			pix_mp-&gt;plane_fmt[2].bytesperline = ctx-&gt;stride[2];</div><div class='add'>+			pix_mp-&gt;plane_fmt[2].sizeimage = ctx-&gt;chroma_size_1;</div><div class='add'>+		}</div><div class='ctx'> 	} else if (f-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {</div><div class='ctx'> 		/* This is run on OUTPUT</div><div class='ctx'> 		   The buffer contains compressed image</div><div class='hunk'>@@ -920,6 +939,7 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_ctx *ctx = fh_to_ctx(vq-&gt;drv_priv);</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='add'>+	const struct v4l2_format_info *format;</div><div class='ctx'> </div><div class='ctx'> 	/* Video output for decoding (source)</div><div class='ctx'> 	 * this can be set after getting an instance */</div><div class='hunk'>@@ -936,7 +956,13 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	} else if (ctx-&gt;state == MFCINST_HEAD_PARSED &amp;&amp;</div><div class='ctx'> 		   vq-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='ctx'> 		/* Output plane count is 2 - one for Y and one for CbCr */</div><div class='del'>-		*plane_count = 2;</div><div class='add'>+		format = v4l2_format_info(ctx-&gt;dst_fmt-&gt;fourcc);</div><div class='add'>+		if (!format) {</div><div class='add'>+			mfc_err("invalid format\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+		*plane_count = format-&gt;comp_planes;</div><div class='add'>+</div><div class='ctx'> 		/* Setup buffer count */</div><div class='ctx'> 		if (*buf_count &lt; ctx-&gt;pb_count)</div><div class='ctx'> 			*buf_count = ctx-&gt;pb_count;</div><div class='hunk'>@@ -955,14 +981,18 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	    vq-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='ctx'> 		psize[0] = ctx-&gt;luma_size;</div><div class='ctx'> 		psize[1] = ctx-&gt;chroma_size;</div><div class='del'>-</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M)</div><div class='add'>+			psize[2] = ctx-&gt;chroma_size_1;</div><div class='ctx'> 		if (IS_MFCV6_PLUS(dev))</div><div class='ctx'> 			alloc_devs[0] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='ctx'> 		else</div><div class='ctx'> 			alloc_devs[0] = ctx-&gt;dev-&gt;mem_dev[BANK_R_CTX];</div><div class='ctx'> 		alloc_devs[1] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='del'>-	} else if (vq-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &amp;&amp;</div><div class='del'>-		   ctx-&gt;state == MFCINST_INIT) {</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M)</div><div class='add'>+			alloc_devs[2] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='add'>+	} else if (vq-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &amp;&amp; ctx-&gt;state == MFCINST_INIT) {</div><div class='ctx'> 		psize[0] = ctx-&gt;dec_src_buf_size;</div><div class='ctx'> 		alloc_devs[0] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -994,12 +1024,24 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb)</div><div class='ctx'> 			mfc_err("Plane buffer (CAPTURE) is too small\n");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			if (vb2_plane_size(vb, 2) &lt; ctx-&gt;chroma_size_1) {</div><div class='add'>+				mfc_err("Plane buffer (CAPTURE) is too small\n");</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='ctx'> 		i = vb-&gt;index;</div><div class='ctx'> 		ctx-&gt;dst_bufs[i].b = vbuf;</div><div class='ctx'> 		ctx-&gt;dst_bufs[i].cookie.raw.luma =</div><div class='ctx'> 					vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='ctx'> 		ctx-&gt;dst_bufs[i].cookie.raw.chroma =</div><div class='ctx'> 					vb2_dma_contig_plane_dma_addr(vb, 1);</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			ctx-&gt;dst_bufs[i].cookie.raw.chroma_1 =</div><div class='add'>+					vb2_dma_contig_plane_dma_addr(vb, 2);</div><div class='add'>+		}</div><div class='ctx'> 		ctx-&gt;dst_bufs_cnt++;</div><div class='ctx'> 	} else if (vq-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {</div><div class='ctx'> 		if (IS_ERR_OR_NULL(ERR_PTR(</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c<br/>index 4b4c129c09e7..ef8bb40b9712 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c</a></div><div class='hunk'>@@ -60,6 +60,20 @@ static struct s5p_mfc_fmt formats[] = {</div><div class='ctx'> 		.versions	= MFC_V6PLUS_BITS,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='add'>+		.fourcc         = V4L2_PIX_FMT_YUV420M,</div><div class='add'>+		.codec_mode     = S5P_MFC_CODEC_NONE,</div><div class='add'>+		.type           = MFC_FMT_RAW,</div><div class='add'>+		.num_planes     = 3,</div><div class='add'>+		.versions       = MFC_V12_BIT,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.fourcc         = V4L2_PIX_FMT_YVU420M,</div><div class='add'>+		.codec_mode     = S5P_MFC_CODEC_NONE,</div><div class='add'>+		.type           = MFC_FMT_RAW,</div><div class='add'>+		.num_planes     = 3,</div><div class='add'>+		.versions       = MFC_V12_BIT,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='ctx'> 		.fourcc		= V4L2_PIX_FMT_H264,</div><div class='ctx'> 		.codec_mode	= S5P_MFC_CODEC_H264_ENC,</div><div class='ctx'> 		.type		= MFC_FMT_ENC,</div><div class='hunk'>@@ -92,7 +106,7 @@ static struct s5p_mfc_fmt formats[] = {</div><div class='ctx'> 		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,</div><div class='ctx'> 		.type		= MFC_FMT_ENC,</div><div class='ctx'> 		.num_planes	= 1,</div><div class='del'>-		.versions	= MFC_V10_BIT,</div><div class='add'>+		.versions	= MFC_V10PLUS_BITS,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1150,7 +1164,6 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	struct s5p_mfc_enc_params *p = &amp;ctx-&gt;enc_params;</div><div class='ctx'> 	struct s5p_mfc_buf *dst_mb;</div><div class='del'>-	unsigned int enc_pb_count;</div><div class='ctx'> </div><div class='ctx'> 	if (p-&gt;seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) {</div><div class='ctx'> 		if (!list_empty(&amp;ctx-&gt;dst_queue)) {</div><div class='hunk'>@@ -1172,14 +1185,12 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			set_work_bit_irqsave(ctx);</div><div class='ctx'> 		s5p_mfc_hw_call(dev-&gt;mfc_ops, try_run, dev);</div><div class='ctx'> 	} else {</div><div class='del'>-		enc_pb_count = s5p_mfc_hw_call(dev-&gt;mfc_ops,</div><div class='del'>-				get_enc_dpb_count, dev);</div><div class='del'>-		if (ctx-&gt;pb_count &lt; enc_pb_count)</div><div class='del'>-			ctx-&gt;pb_count = enc_pb_count;</div><div class='add'>+		ctx-&gt;pb_count = s5p_mfc_hw_call(dev-&gt;mfc_ops, get_enc_dpb_count, dev);</div><div class='ctx'> 		if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) {</div><div class='ctx'> 			ctx-&gt;scratch_buf_size = s5p_mfc_hw_call(dev-&gt;mfc_ops,</div><div class='ctx'> 					get_e_min_scratch_buf_size, dev);</div><div class='del'>-			ctx-&gt;bank1.size += ctx-&gt;scratch_buf_size;</div><div class='add'>+			if (!IS_MFCV12(dev))</div><div class='add'>+				ctx-&gt;bank1.size += ctx-&gt;scratch_buf_size;</div><div class='ctx'> 		}</div><div class='ctx'> 		ctx-&gt;state = MFCINST_HEAD_PRODUCED;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1192,14 +1203,20 @@ static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	struct s5p_mfc_buf *dst_mb;</div><div class='ctx'> 	struct s5p_mfc_buf *src_mb;</div><div class='del'>-	unsigned long src_y_addr, src_c_addr, dst_addr;</div><div class='add'>+	unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;</div><div class='ctx'> 	unsigned int dst_size;</div><div class='ctx'> </div><div class='ctx'> 	src_mb = list_entry(ctx-&gt;src_queue.next, struct s5p_mfc_buf, list);</div><div class='ctx'> 	src_y_addr = vb2_dma_contig_plane_dma_addr(&amp;src_mb-&gt;b-&gt;vb2_buf, 0);</div><div class='ctx'> 	src_c_addr = vb2_dma_contig_plane_dma_addr(&amp;src_mb-&gt;b-&gt;vb2_buf, 1);</div><div class='add'>+	if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+			V4L2_PIX_FMT_YVU420M)</div><div class='add'>+		src_c_1_addr =</div><div class='add'>+			vb2_dma_contig_plane_dma_addr(&amp;src_mb-&gt;b-&gt;vb2_buf, 2);</div><div class='add'>+	else</div><div class='add'>+		src_c_1_addr = 0;</div><div class='ctx'> 	s5p_mfc_hw_call(dev-&gt;mfc_ops, set_enc_frame_buffer, ctx,</div><div class='del'>-							src_y_addr, src_c_addr);</div><div class='add'>+					src_y_addr, src_c_addr, src_c_1_addr);</div><div class='ctx'> </div><div class='ctx'> 	dst_mb = list_entry(ctx-&gt;dst_queue.next, struct s5p_mfc_buf, list);</div><div class='ctx'> 	dst_addr = vb2_dma_contig_plane_dma_addr(&amp;dst_mb-&gt;b-&gt;vb2_buf, 0);</div><div class='hunk'>@@ -1214,8 +1231,8 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	struct s5p_mfc_buf *mb_entry;</div><div class='del'>-	unsigned long enc_y_addr = 0, enc_c_addr = 0;</div><div class='del'>-	unsigned long mb_y_addr, mb_c_addr;</div><div class='add'>+	unsigned long enc_y_addr = 0, enc_c_addr = 0, enc_c_1_addr = 0;</div><div class='add'>+	unsigned long mb_y_addr, mb_c_addr, mb_c_1_addr;</div><div class='ctx'> 	int slice_type;</div><div class='ctx'> 	unsigned int strm_size;</div><div class='ctx'> 	bool src_ready;</div><div class='hunk'>@@ -1228,18 +1245,26 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		  mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));</div><div class='ctx'> 	if (slice_type &gt;= 0) {</div><div class='ctx'> 		s5p_mfc_hw_call(dev-&gt;mfc_ops, get_enc_frame_buffer, ctx,</div><div class='del'>-				&amp;enc_y_addr, &amp;enc_c_addr);</div><div class='add'>+				&amp;enc_y_addr, &amp;enc_c_addr, &amp;enc_c_1_addr);</div><div class='ctx'> 		list_for_each_entry(mb_entry, &amp;ctx-&gt;src_queue, list) {</div><div class='ctx'> 			mb_y_addr = vb2_dma_contig_plane_dma_addr(</div><div class='ctx'> 					&amp;mb_entry-&gt;b-&gt;vb2_buf, 0);</div><div class='ctx'> 			mb_c_addr = vb2_dma_contig_plane_dma_addr(</div><div class='ctx'> 					&amp;mb_entry-&gt;b-&gt;vb2_buf, 1);</div><div class='del'>-			if ((enc_y_addr == mb_y_addr) &amp;&amp;</div><div class='del'>-						(enc_c_addr == mb_c_addr)) {</div><div class='add'>+			if (ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YUV420M ||</div><div class='add'>+					ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YVU420M)</div><div class='add'>+				mb_c_1_addr = vb2_dma_contig_plane_dma_addr</div><div class='add'>+					(&amp;mb_entry-&gt;b-&gt;vb2_buf, 2);</div><div class='add'>+			else</div><div class='add'>+				mb_c_1_addr = 0;</div><div class='add'>+			if (enc_y_addr == mb_y_addr &amp;&amp; enc_c_addr == mb_c_addr &amp;&amp; enc_c_1_addr</div><div class='add'>+					== mb_c_1_addr) {</div><div class='ctx'> 				list_del(&amp;mb_entry-&gt;list);</div><div class='ctx'> 				ctx-&gt;src_queue_cnt--;</div><div class='ctx'> 				vb2_buffer_done(&amp;mb_entry-&gt;b-&gt;vb2_buf,</div><div class='del'>-							VB2_BUF_STATE_DONE);</div><div class='add'>+						VB2_BUF_STATE_DONE);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1248,20 +1273,27 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 					&amp;mb_entry-&gt;b-&gt;vb2_buf, 0);</div><div class='ctx'> 			mb_c_addr = vb2_dma_contig_plane_dma_addr(</div><div class='ctx'> 					&amp;mb_entry-&gt;b-&gt;vb2_buf, 1);</div><div class='del'>-			if ((enc_y_addr == mb_y_addr) &amp;&amp;</div><div class='del'>-						(enc_c_addr == mb_c_addr)) {</div><div class='add'>+			if (ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YUV420M ||</div><div class='add'>+					ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YVU420M)</div><div class='add'>+				mb_c_1_addr = vb2_dma_contig_plane_dma_addr(&amp;</div><div class='add'>+						mb_entry-&gt;b-&gt;vb2_buf, 2);</div><div class='add'>+			else</div><div class='add'>+				mb_c_1_addr = 0;</div><div class='add'>+			if (enc_y_addr == mb_y_addr &amp;&amp; enc_c_addr == mb_c_addr &amp;&amp; enc_c_1_addr</div><div class='add'>+					== mb_c_1_addr) {</div><div class='ctx'> 				list_del(&amp;mb_entry-&gt;list);</div><div class='ctx'> 				ctx-&gt;ref_queue_cnt--;</div><div class='ctx'> 				vb2_buffer_done(&amp;mb_entry-&gt;b-&gt;vb2_buf,</div><div class='del'>-							VB2_BUF_STATE_DONE);</div><div class='add'>+						VB2_BUF_STATE_DONE);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ctx-&gt;src_queue_cnt &gt; 0 &amp;&amp; (ctx-&gt;state == MFCINST_RUNNING ||</div><div class='del'>-				       ctx-&gt;state == MFCINST_FINISHING)) {</div><div class='add'>+				ctx-&gt;state == MFCINST_FINISHING)) {</div><div class='ctx'> 		mb_entry = list_entry(ctx-&gt;src_queue.next, struct s5p_mfc_buf,</div><div class='del'>-									list);</div><div class='add'>+				list);</div><div class='ctx'> 		if (mb_entry-&gt;flags &amp; MFC_BUF_FLAG_USED) {</div><div class='ctx'> 			list_del(&amp;mb_entry-&gt;list);</div><div class='ctx'> 			ctx-&gt;src_queue_cnt--;</div><div class='hunk'>@@ -1380,10 +1412,15 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)</div><div class='ctx'> 		pix_fmt_mp-&gt;pixelformat = ctx-&gt;src_fmt-&gt;fourcc;</div><div class='ctx'> 		pix_fmt_mp-&gt;num_planes = ctx-&gt;src_fmt-&gt;num_planes;</div><div class='ctx'> </div><div class='del'>-		pix_fmt_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_fmt_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;stride[0];</div><div class='ctx'> 		pix_fmt_mp-&gt;plane_fmt[0].sizeimage = ctx-&gt;luma_size;</div><div class='del'>-		pix_fmt_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_fmt_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;stride[1];</div><div class='ctx'> 		pix_fmt_mp-&gt;plane_fmt[1].sizeimage = ctx-&gt;chroma_size;</div><div class='add'>+		if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			pix_fmt_mp-&gt;plane_fmt[2].bytesperline = ctx-&gt;stride[2];</div><div class='add'>+			pix_fmt_mp-&gt;plane_fmt[2].sizeimage = ctx-&gt;chroma_size_1;</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mfc_err("invalid buf type\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1420,9 +1457,12 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)</div><div class='ctx'> 			mfc_err("Unsupported format by this MFC version.\n");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		v4l_bound_align_image(&amp;pix_fmt_mp-&gt;width, 8, 1920, 1,</div><div class='del'>-			&amp;pix_fmt_mp-&gt;height, 4, 1080, 1, 0);</div><div class='add'>+		if (IS_MFCV12(dev))</div><div class='add'>+			v4l_bound_align_image(&amp;pix_fmt_mp-&gt;width, 8, 3840, 1, &amp;pix_fmt_mp</div><div class='add'>+					-&gt;height, 4, 2160, 1, 0);</div><div class='add'>+		else</div><div class='add'>+			v4l_bound_align_image(&amp;pix_fmt_mp-&gt;width, 8, 1920, 1, &amp;pix_fmt_mp</div><div class='add'>+					-&gt;height, 4, 1080, 1, 0);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mfc_err("invalid buf type\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1467,9 +1507,14 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)</div><div class='ctx'> </div><div class='ctx'> 		s5p_mfc_hw_call(dev-&gt;mfc_ops, enc_calc_src_size, ctx);</div><div class='ctx'> 		pix_fmt_mp-&gt;plane_fmt[0].sizeimage = ctx-&gt;luma_size;</div><div class='del'>-		pix_fmt_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_fmt_mp-&gt;plane_fmt[0].bytesperline = ctx-&gt;stride[0];</div><div class='ctx'> 		pix_fmt_mp-&gt;plane_fmt[1].sizeimage = ctx-&gt;chroma_size;</div><div class='del'>-		pix_fmt_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;buf_width;</div><div class='add'>+		pix_fmt_mp-&gt;plane_fmt[1].bytesperline = ctx-&gt;stride[1];</div><div class='add'>+		if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			pix_fmt_mp-&gt;plane_fmt[2].bytesperline = ctx-&gt;stride[2];</div><div class='add'>+			pix_fmt_mp-&gt;plane_fmt[2].sizeimage = ctx-&gt;chroma_size_1;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		ctx-&gt;src_bufs_cnt = 0;</div><div class='ctx'> 		ctx-&gt;output_state = QUEUE_FREE;</div><div class='hunk'>@@ -1489,9 +1534,10 @@ static int vidioc_reqbufs(struct file *file, void *priv,</div><div class='ctx'> 	struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	/* if memory is not mmp or userptr return error */</div><div class='add'>+	/* if memory is not mmp or userptr or dmabuf return error */</div><div class='ctx'> 	if ((reqbufs-&gt;memory != V4L2_MEMORY_MMAP) &amp;&amp;</div><div class='del'>-		(reqbufs-&gt;memory != V4L2_MEMORY_USERPTR))</div><div class='add'>+		(reqbufs-&gt;memory != V4L2_MEMORY_USERPTR) &amp;&amp;</div><div class='add'>+		(reqbufs-&gt;memory != V4L2_MEMORY_DMABUF))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	if (reqbufs-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='ctx'> 		if (reqbufs-&gt;count == 0) {</div><div class='hunk'>@@ -1514,14 +1560,6 @@ static int vidioc_reqbufs(struct file *file, void *priv,</div><div class='ctx'> 		}</div><div class='ctx'> 		ctx-&gt;capture_state = QUEUE_BUFS_REQUESTED;</div><div class='ctx'> </div><div class='del'>-		ret = s5p_mfc_hw_call(ctx-&gt;dev-&gt;mfc_ops,</div><div class='del'>-				alloc_codec_buffers, ctx);</div><div class='del'>-		if (ret) {</div><div class='del'>-			mfc_err("Failed to allocate encoding buffers\n");</div><div class='del'>-			reqbufs-&gt;count = 0;</div><div class='del'>-			ret = vb2_reqbufs(&amp;ctx-&gt;vq_dst, reqbufs);</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		}</div><div class='ctx'> 	} else if (reqbufs-&gt;type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {</div><div class='ctx'> 		if (reqbufs-&gt;count == 0) {</div><div class='ctx'> 			mfc_debug(2, "Freeing buffers\n");</div><div class='hunk'>@@ -1537,15 +1575,13 @@ static int vidioc_reqbufs(struct file *file, void *priv,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (IS_MFCV6_PLUS(dev)) {</div><div class='add'>+		if (IS_MFCV6_PLUS(dev) &amp;&amp; (!IS_MFCV12(dev))) {</div><div class='ctx'> 			/* Check for min encoder buffers */</div><div class='ctx'> 			if (ctx-&gt;pb_count &amp;&amp;</div><div class='ctx'> 				(reqbufs-&gt;count &lt; ctx-&gt;pb_count)) {</div><div class='ctx'> 				reqbufs-&gt;count = ctx-&gt;pb_count;</div><div class='ctx'> 				mfc_debug(2, "Minimum %d output buffers needed\n",</div><div class='ctx'> 						ctx-&gt;pb_count);</div><div class='del'>-			} else {</div><div class='del'>-				ctx-&gt;pb_count = reqbufs-&gt;count;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1568,9 +1604,10 @@ static int vidioc_querybuf(struct file *file, void *priv,</div><div class='ctx'> 	struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	/* if memory is not mmp or userptr return error */</div><div class='add'>+	/* if memory is not mmp or userptr or dmabuf return error */</div><div class='ctx'> 	if ((buf-&gt;memory != V4L2_MEMORY_MMAP) &amp;&amp;</div><div class='del'>-		(buf-&gt;memory != V4L2_MEMORY_USERPTR))</div><div class='add'>+		(buf-&gt;memory != V4L2_MEMORY_USERPTR) &amp;&amp;</div><div class='add'>+		(buf-&gt;memory != V4L2_MEMORY_DMABUF))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	if (buf-&gt;type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {</div><div class='ctx'> 		if (ctx-&gt;state != MFCINST_GOT_INST) {</div><div class='hunk'>@@ -2413,10 +2450,18 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> </div><div class='ctx'> 		psize[0] = ctx-&gt;luma_size;</div><div class='ctx'> 		psize[1] = ctx-&gt;chroma_size;</div><div class='add'>+		if (ctx-&gt;src_fmt &amp;&amp; (ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YVU420M))</div><div class='add'>+			psize[2] = ctx-&gt;chroma_size_1;</div><div class='ctx'> </div><div class='ctx'> 		if (IS_MFCV6_PLUS(dev)) {</div><div class='ctx'> 			alloc_devs[0] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='ctx'> 			alloc_devs[1] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='add'>+			if (ctx-&gt;src_fmt &amp;&amp; (ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+						V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+						V4L2_PIX_FMT_YVU420M))</div><div class='add'>+				alloc_devs[2] = ctx-&gt;dev-&gt;mem_dev[BANK_L_CTX];</div><div class='ctx'> 		} else {</div><div class='ctx'> 			alloc_devs[0] = ctx-&gt;dev-&gt;mem_dev[BANK_R_CTX];</div><div class='ctx'> 			alloc_devs[1] = ctx-&gt;dev-&gt;mem_dev[BANK_R_CTX];</div><div class='hunk'>@@ -2455,6 +2500,11 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb)</div><div class='ctx'> 					vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='ctx'> 		ctx-&gt;src_bufs[i].cookie.raw.chroma =</div><div class='ctx'> 					vb2_dma_contig_plane_dma_addr(vb, 1);</div><div class='add'>+		if (ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M)</div><div class='add'>+			ctx-&gt;src_bufs[i].cookie.raw.chroma_1 =</div><div class='add'>+					vb2_dma_contig_plane_dma_addr(vb, 2);</div><div class='ctx'> 		ctx-&gt;src_bufs_cnt++;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mfc_err("invalid queue type: %d\n", vq-&gt;type);</div><div class='hunk'>@@ -2492,6 +2542,12 @@ static int s5p_mfc_buf_prepare(struct vb2_buffer *vb)</div><div class='ctx'> 			mfc_err("plane size is too small for output\n");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='add'>+		if ((ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M ||</div><div class='add'>+		     ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YVU420M) &amp;&amp;</div><div class='add'>+		    (vb2_plane_size(vb, 2) &lt; ctx-&gt;chroma_size_1)) {</div><div class='add'>+			mfc_err("plane size is too small for output\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		mfc_err("invalid queue type: %d\n", vq-&gt;type);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2513,11 +2569,11 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 						S5P_MFC_R2H_CMD_SEQ_DONE_RET,</div><div class='ctx'> 						0);</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		if (ctx-&gt;src_bufs_cnt &lt; ctx-&gt;pb_count) {</div><div class='del'>-			mfc_err("Need minimum %d OUTPUT buffers\n",</div><div class='del'>-					ctx-&gt;pb_count);</div><div class='del'>-			return -ENOBUFS;</div><div class='add'>+		if (q-&gt;memory != V4L2_MEMORY_DMABUF) {</div><div class='add'>+			if (ctx-&gt;src_bufs_cnt &lt; ctx-&gt;pb_count) {</div><div class='add'>+				mfc_err("Need minimum %d OUTPUT buffers\n", ctx-&gt;pb_count);</div><div class='add'>+				return -ENOBUFS;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h<br/>index b9831275f3ab..7c5e851c8191 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h</a></div><div class='hunk'>@@ -166,9 +166,9 @@ struct s5p_mfc_regs {</div><div class='ctx'> 	void __iomem *d_decoded_third_addr;/* only v7 */</div><div class='ctx'> 	void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */</div><div class='ctx'> 	void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */</div><div class='del'>-	void __iomem *d_min_scratch_buffer_size; /* v10 */</div><div class='del'>-	void __iomem *d_static_buffer_addr; /* v10 */</div><div class='del'>-	void __iomem *d_static_buffer_size; /* v10 */</div><div class='add'>+	void __iomem *d_min_scratch_buffer_size; /* v10 and v12 */</div><div class='add'>+	void __iomem *d_static_buffer_addr; /* v10 and v12 */</div><div class='add'>+	void __iomem *d_static_buffer_size; /* v10 and v12 */</div><div class='ctx'> </div><div class='ctx'> 	/* encoder registers */</div><div class='ctx'> 	void __iomem *e_frame_width;</div><div class='hunk'>@@ -268,7 +268,7 @@ struct s5p_mfc_regs {</div><div class='ctx'> 	void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */</div><div class='ctx'> 	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */</div><div class='ctx'> 	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */</div><div class='del'>-	void __iomem *e_min_scratch_buffer_size; /* v10 */</div><div class='add'>+	void __iomem *e_min_scratch_buffer_size; /* v10 and v12 */</div><div class='ctx'> 	void __iomem *e_num_t_layer; /* v10 */</div><div class='ctx'> 	void __iomem *e_hier_qp_layer0; /* v10 */</div><div class='ctx'> 	void __iomem *e_hier_bit_rate_layer0; /* v10 */</div><div class='hunk'>@@ -293,9 +293,11 @@ struct s5p_mfc_hw_ops {</div><div class='ctx'> 	int (*set_enc_stream_buffer)(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> 			unsigned long addr, unsigned int size);</div><div class='ctx'> 	void (*set_enc_frame_buffer)(struct s5p_mfc_ctx *ctx,</div><div class='del'>-			unsigned long y_addr, unsigned long c_addr);</div><div class='add'>+			unsigned long y_addr, unsigned long c_addr,</div><div class='add'>+			unsigned long c_1_addr);</div><div class='ctx'> 	void (*get_enc_frame_buffer)(struct s5p_mfc_ctx *ctx,</div><div class='del'>-			unsigned long *y_addr, unsigned long *c_addr);</div><div class='add'>+			unsigned long *y_addr, unsigned long *c_addr,</div><div class='add'>+			unsigned long *c_1_addr);</div><div class='ctx'> 	void (*try_run)(struct s5p_mfc_dev *dev);</div><div class='ctx'> 	void (*clear_int_flags)(struct s5p_mfc_dev *dev);</div><div class='ctx'> 	int (*get_dspl_y_adr)(struct s5p_mfc_dev *dev);</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c<br/>index 28a06dc343fd..fcfaf125a5a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c</a></div><div class='hunk'>@@ -516,7 +516,8 @@ static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,</div><div class='del'>-		unsigned long y_addr, unsigned long c_addr)</div><div class='add'>+		unsigned long y_addr, unsigned long c_addr,</div><div class='add'>+		unsigned long c_1_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> </div><div class='hunk'>@@ -525,7 +526,8 @@ static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,</div><div class='del'>-		unsigned long *y_addr, unsigned long *c_addr)</div><div class='add'>+		unsigned long *y_addr, unsigned long *c_addr,</div><div class='add'>+		unsigned long *c_1_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> </div><div class='hunk'>@@ -1210,7 +1212,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	if (list_empty(&amp;ctx-&gt;src_queue)) {</div><div class='ctx'> 		/* send null frame */</div><div class='ctx'> 		s5p_mfc_set_enc_frame_buffer_v5(ctx, dev-&gt;dma_base[BANK_R_CTX],</div><div class='del'>-						dev-&gt;dma_base[BANK_R_CTX]);</div><div class='add'>+						dev-&gt;dma_base[BANK_R_CTX], 0);</div><div class='ctx'> 		src_mb = NULL;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		src_mb = list_entry(ctx-&gt;src_queue.next, struct s5p_mfc_buf,</div><div class='hunk'>@@ -1220,7 +1222,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			/* send null frame */</div><div class='ctx'> 			s5p_mfc_set_enc_frame_buffer_v5(ctx,</div><div class='ctx'> 						dev-&gt;dma_base[BANK_R_CTX],</div><div class='del'>-						dev-&gt;dma_base[BANK_R_CTX]);</div><div class='add'>+						dev-&gt;dma_base[BANK_R_CTX], 0);</div><div class='ctx'> 			ctx-&gt;state = MFCINST_FINISHING;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			src_y_addr = vb2_dma_contig_plane_dma_addr(</div><div class='hunk'>@@ -1228,7 +1230,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			src_c_addr = vb2_dma_contig_plane_dma_addr(</div><div class='ctx'> 					&amp;src_mb-&gt;b-&gt;vb2_buf, 1);</div><div class='ctx'> 			s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr,</div><div class='del'>-								src_c_addr);</div><div class='add'>+								src_c_addr, 0);</div><div class='ctx'> 			if (src_mb-&gt;flags &amp; MFC_BUF_FLAG_EOS)</div><div class='ctx'> 				ctx-&gt;state = MFCINST_FINISHING;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c<br/>index c0df5ac9fcff..fd945211d28e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c</a></div><div class='hunk'>@@ -60,21 +60,23 @@ static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='del'>-	unsigned int mb_width, mb_height;</div><div class='add'>+	unsigned int mb_width, mb_height, width64, height32;</div><div class='ctx'> 	unsigned int lcu_width = 0, lcu_height = 0;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	mb_width = MB_WIDTH(ctx-&gt;img_width);</div><div class='ctx'> 	mb_height = MB_HEIGHT(ctx-&gt;img_height);</div><div class='add'>+	width64 = ALIGN(ctx-&gt;img_width, 64);</div><div class='add'>+	height32 = ALIGN(ctx-&gt;img_height, 32);</div><div class='ctx'> </div><div class='ctx'> 	if (ctx-&gt;type == MFCINST_DECODER) {</div><div class='ctx'> 		mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",</div><div class='ctx'> 			  ctx-&gt;luma_size, ctx-&gt;chroma_size, ctx-&gt;mv_size);</div><div class='ctx'> 		mfc_debug(2, "Totals bufs: %d\n", ctx-&gt;total_dpb_count);</div><div class='ctx'> 	} else if (ctx-&gt;type == MFCINST_ENCODER) {</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			ctx-&gt;tmv_buffer_size = 0;</div><div class='del'>-		} else if (IS_MFCV8_PLUS(dev))</div><div class='add'>+		else if (IS_MFCV8_PLUS(dev))</div><div class='ctx'> 			ctx-&gt;tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *</div><div class='ctx'> 			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),</div><div class='ctx'> 			S5P_FIMV_TMV_BUFFER_ALIGN_V6);</div><div class='hunk'>@@ -82,7 +84,39 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			ctx-&gt;tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *</div><div class='ctx'> 			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),</div><div class='ctx'> 			S5P_FIMV_TMV_BUFFER_ALIGN_V6);</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='add'>+		if (IS_MFCV12(dev)) {</div><div class='add'>+			lcu_width = S5P_MFC_LCU_WIDTH(ctx-&gt;img_width);</div><div class='add'>+			lcu_height = S5P_MFC_LCU_HEIGHT(ctx-&gt;img_height);</div><div class='add'>+			if (ctx-&gt;codec_mode == S5P_FIMV_CODEC_HEVC_ENC &amp;&amp; ctx-&gt;is_10bit) {</div><div class='add'>+				ctx-&gt;luma_dpb_size =</div><div class='add'>+					width64 * height32 +</div><div class='add'>+					ALIGN(DIV_ROUND_UP(lcu_width * 32, 4), 16) * height32 + 128;</div><div class='add'>+				if (ctx-&gt;is_422)</div><div class='add'>+					ctx-&gt;chroma_dpb_size =</div><div class='add'>+						ctx-&gt;luma_dpb_size;</div><div class='add'>+				else</div><div class='add'>+					ctx-&gt;chroma_dpb_size =</div><div class='add'>+						width64 * height32 / 2 +</div><div class='add'>+						ALIGN(DIV_ROUND_UP(lcu_width *</div><div class='add'>+							32, 4), 16) * height32 / 2 + 128;</div><div class='add'>+			} else if (ctx-&gt;codec_mode == S5P_FIMV_CODEC_VP9_ENC &amp;&amp;	ctx-&gt;is_10bit) {</div><div class='add'>+				ctx-&gt;luma_dpb_size =</div><div class='add'>+					ALIGN(ctx-&gt;img_width * 2, 128) * height32 + 64;</div><div class='add'>+				ctx-&gt;chroma_dpb_size =</div><div class='add'>+					ALIGN(ctx-&gt;img_width * 2, 128) * height32 / 2 + 64;</div><div class='add'>+			} else {</div><div class='add'>+				ctx-&gt;luma_dpb_size =</div><div class='add'>+					width64 * height32 + 64;</div><div class='add'>+				if (ctx-&gt;is_422)</div><div class='add'>+					ctx-&gt;chroma_dpb_size =</div><div class='add'>+						ctx-&gt;luma_dpb_size;</div><div class='add'>+				else</div><div class='add'>+					ctx-&gt;chroma_dpb_size =</div><div class='add'>+						width64 * height32 / 2 + 64;</div><div class='add'>+			}</div><div class='add'>+			ctx-&gt;luma_dpb_size = ALIGN(ctx-&gt;luma_dpb_size + 256, SZ_2K);</div><div class='add'>+			ctx-&gt;chroma_dpb_size = ALIGN(ctx-&gt;chroma_dpb_size + 256, SZ_2K);</div><div class='add'>+		} else if (IS_MFCV10_PLUS(dev)) {</div><div class='ctx'> 			lcu_width = S5P_MFC_LCU_WIDTH(ctx-&gt;img_width);</div><div class='ctx'> 			lcu_height = S5P_MFC_LCU_HEIGHT(ctx-&gt;img_height);</div><div class='ctx'> 			if (ctx-&gt;codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {</div><div class='hunk'>@@ -133,7 +167,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	switch (ctx-&gt;codec_mode) {</div><div class='ctx'> 	case S5P_MFC_CODEC_H264_DEC:</div><div class='ctx'> 	case S5P_MFC_CODEC_H264_MVC_DEC:</div><div class='del'>-		if (IS_MFCV10(dev))</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 		else if (IS_MFCV8_PLUS(dev))</div><div class='ctx'> 			ctx-&gt;scratch_buf_size =</div><div class='hunk'>@@ -152,7 +186,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			(ctx-&gt;mv_count * ctx-&gt;mv_size);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_MPEG4_DEC:</div><div class='del'>-		if (IS_MFCV10(dev))</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 		else if (IS_MFCV7_PLUS(dev)) {</div><div class='ctx'> 			ctx-&gt;scratch_buf_size =</div><div class='hunk'>@@ -172,7 +206,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_VC1RCV_DEC:</div><div class='ctx'> 	case S5P_MFC_CODEC_VC1_DEC:</div><div class='del'>-		if (IS_MFCV10(dev))</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 		else</div><div class='ctx'> 			ctx-&gt;scratch_buf_size =</div><div class='hunk'>@@ -189,7 +223,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		ctx-&gt;bank2.size = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_H263_DEC:</div><div class='del'>-		if (IS_MFCV10(dev))</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 		else</div><div class='ctx'> 			ctx-&gt;scratch_buf_size =</div><div class='hunk'>@@ -201,7 +235,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		ctx-&gt;bank1.size = ctx-&gt;scratch_buf_size;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_VP8_DEC:</div><div class='del'>-		if (IS_MFCV10(dev))</div><div class='add'>+		if (IS_MFCV10_PLUS(dev))</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 		else if (IS_MFCV8_PLUS(dev))</div><div class='ctx'> 			ctx-&gt;scratch_buf_size =</div><div class='hunk'>@@ -230,7 +264,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 			DEC_VP9_STATIC_BUFFER_SIZE;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_H264_ENC:</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='add'>+		if (IS_MFCV12(dev)) {</div><div class='add'>+			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='add'>+			ctx-&gt;me_buffer_size =</div><div class='add'>+				ENC_V120_H264_ME_SIZE(mb_width, mb_height);</div><div class='add'>+		} else if (IS_MFCV10_PLUS(dev)) {</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 			ctx-&gt;me_buffer_size =</div><div class='ctx'> 			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);</div><div class='hunk'>@@ -254,7 +292,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_MPEG4_ENC:</div><div class='ctx'> 	case S5P_MFC_CODEC_H263_ENC:</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='add'>+		if (IS_MFCV12(dev)) {</div><div class='add'>+			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='add'>+			ctx-&gt;me_buffer_size =</div><div class='add'>+				ENC_V120_MPEG4_ME_SIZE(mb_width, mb_height);</div><div class='add'>+		} else if (IS_MFCV10_PLUS(dev)) {</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 			ctx-&gt;me_buffer_size =</div><div class='ctx'> 				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,</div><div class='hunk'>@@ -265,7 +307,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 						mb_width,</div><div class='ctx'> 						mb_height);</div><div class='ctx'> 		ctx-&gt;scratch_buf_size = ALIGN(ctx-&gt;scratch_buf_size,</div><div class='del'>-				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);</div><div class='add'>+					S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);</div><div class='ctx'> 		ctx-&gt;bank1.size =</div><div class='ctx'> 			ctx-&gt;scratch_buf_size + ctx-&gt;tmv_buffer_size +</div><div class='ctx'> 			(ctx-&gt;pb_count * (ctx-&gt;luma_dpb_size +</div><div class='hunk'>@@ -273,7 +315,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		ctx-&gt;bank2.size = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_VP8_ENC:</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='add'>+		if (IS_MFCV12(dev)) {</div><div class='add'>+			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='add'>+			ctx-&gt;me_buffer_size =</div><div class='add'>+				ENC_V120_VP8_ME_SIZE(mb_width, mb_height);</div><div class='add'>+		} else if (IS_MFCV10_PLUS(dev)) {</div><div class='ctx'> 			mfc_debug(2, "Use min scratch buffer size\n");</div><div class='ctx'> 			ctx-&gt;me_buffer_size =</div><div class='ctx'> 				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),</div><div class='hunk'>@@ -297,9 +343,13 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		ctx-&gt;bank2.size = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case S5P_MFC_CODEC_HEVC_ENC:</div><div class='add'>+		if (IS_MFCV12(dev))</div><div class='add'>+			ctx-&gt;me_buffer_size =</div><div class='add'>+				ENC_V120_HEVC_ME_SIZE(lcu_width, lcu_height);</div><div class='add'>+		else</div><div class='add'>+			ctx-&gt;me_buffer_size =</div><div class='add'>+				ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);</div><div class='ctx'> 		mfc_debug(2, "Use min scratch buffer size\n");</div><div class='del'>-		ctx-&gt;me_buffer_size =</div><div class='del'>-			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);</div><div class='ctx'> 		ctx-&gt;scratch_buf_size = ALIGN(ctx-&gt;scratch_buf_size, 256);</div><div class='ctx'> 		ctx-&gt;bank1.size =</div><div class='ctx'> 			ctx-&gt;scratch_buf_size + ctx-&gt;tmv_buffer_size +</div><div class='hunk'>@@ -438,30 +488,48 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	ctx-&gt;buf_width = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='ctx'> 	ctx-&gt;buf_height = ALIGN(ctx-&gt;img_height, S5P_FIMV_NV12MT_VALIGN_V6);</div><div class='add'>+	ctx-&gt;chroma_size_1 = 0;</div><div class='ctx'> 	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"</div><div class='ctx'> 			"buffer dimensions: %dx%d\n", ctx-&gt;img_width,</div><div class='ctx'> 			ctx-&gt;img_height, ctx-&gt;buf_width, ctx-&gt;buf_height);</div><div class='ctx'> </div><div class='del'>-	ctx-&gt;luma_size = calc_plane(ctx-&gt;img_width, ctx-&gt;img_height);</div><div class='del'>-	ctx-&gt;chroma_size = calc_plane(ctx-&gt;img_width, (ctx-&gt;img_height &gt;&gt; 1));</div><div class='add'>+	switch (ctx-&gt;dst_fmt-&gt;fourcc) {</div><div class='add'>+	case V4L2_PIX_FMT_NV12M:</div><div class='add'>+	case V4L2_PIX_FMT_NV21M:</div><div class='add'>+		ctx-&gt;stride[0] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='add'>+		ctx-&gt;stride[1] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='add'>+		ctx-&gt;luma_size = calc_plane(ctx-&gt;stride[0], ctx-&gt;img_height);</div><div class='add'>+		ctx-&gt;chroma_size = calc_plane(ctx-&gt;stride[1], (ctx-&gt;img_height / 2));</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_PIX_FMT_YUV420M:</div><div class='add'>+	case V4L2_PIX_FMT_YVU420M:</div><div class='add'>+		ctx-&gt;stride[0] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='add'>+		ctx-&gt;stride[1] = ALIGN(ctx-&gt;img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='add'>+		ctx-&gt;stride[2] = ALIGN(ctx-&gt;img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);</div><div class='add'>+		ctx-&gt;luma_size = calc_plane(ctx-&gt;stride[0], ctx-&gt;img_height);</div><div class='add'>+		ctx-&gt;chroma_size = calc_plane(ctx-&gt;stride[1], (ctx-&gt;img_height / 2));</div><div class='add'>+		ctx-&gt;chroma_size_1 = calc_plane(ctx-&gt;stride[2], (ctx-&gt;img_height / 2));</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (IS_MFCV8_PLUS(ctx-&gt;dev)) {</div><div class='ctx'> 		/* MFCv8 needs additional 64 bytes for luma,chroma dpb*/</div><div class='ctx'> 		ctx-&gt;luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;</div><div class='ctx'> 		ctx-&gt;chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;</div><div class='add'>+		ctx-&gt;chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ctx-&gt;codec_mode == S5P_MFC_CODEC_H264_DEC ||</div><div class='ctx'> 			ctx-&gt;codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {</div><div class='del'>-		if (IS_MFCV10(dev)) {</div><div class='del'>-			ctx-&gt;mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx-&gt;img_width,</div><div class='del'>-					ctx-&gt;img_height);</div><div class='del'>-		} else {</div><div class='del'>-			ctx-&gt;mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx-&gt;img_width,</div><div class='del'>-					ctx-&gt;img_height);</div><div class='del'>-		}</div><div class='add'>+		if (IS_MFCV12(dev))</div><div class='add'>+			ctx-&gt;mv_size = S5P_MFC_DEC_MV_SIZE(ctx-&gt;img_width, ctx-&gt;img_height, 1024);</div><div class='add'>+		else if (IS_MFCV10_PLUS(dev))</div><div class='add'>+			ctx-&gt;mv_size = S5P_MFC_DEC_MV_SIZE(ctx-&gt;img_width, ctx-&gt;img_height, 512);</div><div class='add'>+		else</div><div class='add'>+			ctx-&gt;mv_size = S5P_MFC_DEC_MV_SIZE(ctx-&gt;img_width, ctx-&gt;img_height, 128);</div><div class='add'>+</div><div class='ctx'> 	} else if (ctx-&gt;codec_mode == S5P_MFC_CODEC_HEVC_DEC) {</div><div class='del'>-		ctx-&gt;mv_size = s5p_mfc_dec_hevc_mv_size(ctx-&gt;img_width,</div><div class='del'>-				ctx-&gt;img_height);</div><div class='add'>+		ctx-&gt;mv_size = s5p_mfc_dec_hevc_mv_size(ctx-&gt;img_width, ctx-&gt;img_height);</div><div class='ctx'> 		ctx-&gt;mv_size = ALIGN(ctx-&gt;mv_size, 32);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ctx-&gt;mv_size = 0;</div><div class='hunk'>@@ -475,14 +543,40 @@ static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	mb_width = MB_WIDTH(ctx-&gt;img_width);</div><div class='ctx'> 	mb_height = MB_HEIGHT(ctx-&gt;img_height);</div><div class='ctx'> </div><div class='del'>-	ctx-&gt;buf_width = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='del'>-	ctx-&gt;luma_size = ALIGN((mb_width * mb_height) * 256, 256);</div><div class='del'>-	ctx-&gt;chroma_size = ALIGN((mb_width * mb_height) * 128, 256);</div><div class='del'>-</div><div class='del'>-	/* MFCv7 needs pad bytes for Luma and Chroma */</div><div class='del'>-	if (IS_MFCV7_PLUS(ctx-&gt;dev)) {</div><div class='add'>+	if (IS_MFCV12(ctx-&gt;dev)) {</div><div class='add'>+		switch (ctx-&gt;src_fmt-&gt;fourcc) {</div><div class='add'>+		case V4L2_PIX_FMT_NV12M:</div><div class='add'>+		case V4L2_PIX_FMT_NV21M:</div><div class='add'>+			ctx-&gt;stride[0] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+			ctx-&gt;stride[1] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+			ctx-&gt;luma_size = ctx-&gt;stride[0] * ALIGN(ctx-&gt;img_height, 16);</div><div class='add'>+			ctx-&gt;chroma_size =  ctx-&gt;stride[0] * ALIGN(ctx-&gt;img_height / 2, 16);</div><div class='add'>+			break;</div><div class='add'>+		case V4L2_PIX_FMT_YUV420M:</div><div class='add'>+		case V4L2_PIX_FMT_YVU420M:</div><div class='add'>+			ctx-&gt;stride[0] = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+			ctx-&gt;stride[1] = ALIGN(ctx-&gt;img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+			ctx-&gt;stride[2] = ALIGN(ctx-&gt;img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+			ctx-&gt;luma_size = ctx-&gt;stride[0] * ALIGN(ctx-&gt;img_height, 16);</div><div class='add'>+			ctx-&gt;chroma_size =  ctx-&gt;stride[1] * ALIGN(ctx-&gt;img_height / 2, 16);</div><div class='add'>+			ctx-&gt;chroma_size_1 =  ctx-&gt;stride[2] * ALIGN(ctx-&gt;img_height / 2, 16);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='ctx'> 		ctx-&gt;luma_size += MFC_LUMA_PAD_BYTES_V7;</div><div class='del'>-		ctx-&gt;chroma_size += MFC_CHROMA_PAD_BYTES_V7;</div><div class='add'>+		ctx-&gt;chroma_size += MFC_CHROMA_PAD_BYTES_V12;</div><div class='add'>+		ctx-&gt;chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12;</div><div class='add'>+	} else {</div><div class='add'>+		ctx-&gt;buf_width = ALIGN(ctx-&gt;img_width, S5P_FIMV_NV12M_HALIGN_V6);</div><div class='add'>+		ctx-&gt;stride[0] = ctx-&gt;buf_width;</div><div class='add'>+		ctx-&gt;stride[1] = ctx-&gt;buf_width;</div><div class='add'>+		ctx-&gt;luma_size = ALIGN((mb_width * mb_height) * 256, 256);</div><div class='add'>+		ctx-&gt;chroma_size = ALIGN((mb_width * mb_height) * 128, 256);</div><div class='add'>+		ctx-&gt;chroma_size_1 = 0;</div><div class='add'>+		/* MFCv7 needs pad bytes for Luma and Chroma */</div><div class='add'>+		if (IS_MFCV7_PLUS(ctx-&gt;dev)) {</div><div class='add'>+			ctx-&gt;luma_size += MFC_LUMA_PAD_BYTES_V7;</div><div class='add'>+			ctx-&gt;chroma_size += MFC_LUMA_PAD_BYTES_V7;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -529,15 +623,18 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	writel(ctx-&gt;total_dpb_count, mfc_regs-&gt;d_num_dpb);</div><div class='ctx'> 	writel(ctx-&gt;luma_size, mfc_regs-&gt;d_first_plane_dpb_size);</div><div class='ctx'> 	writel(ctx-&gt;chroma_size, mfc_regs-&gt;d_second_plane_dpb_size);</div><div class='del'>-</div><div class='add'>+	if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+			V4L2_PIX_FMT_YVU420M)</div><div class='add'>+		writel(ctx-&gt;chroma_size_1, mfc_regs-&gt;d_third_plane_dpb_size);</div><div class='ctx'> 	writel(buf_addr1, mfc_regs-&gt;d_scratch_buffer_addr);</div><div class='ctx'> 	writel(ctx-&gt;scratch_buf_size, mfc_regs-&gt;d_scratch_buffer_size);</div><div class='ctx'> </div><div class='ctx'> 	if (IS_MFCV8_PLUS(dev)) {</div><div class='del'>-		writel(ctx-&gt;img_width,</div><div class='del'>-			mfc_regs-&gt;d_first_plane_dpb_stride_size);</div><div class='del'>-		writel(ctx-&gt;img_width,</div><div class='del'>-			mfc_regs-&gt;d_second_plane_dpb_stride_size);</div><div class='add'>+		writel(ctx-&gt;stride[0], mfc_regs-&gt;d_first_plane_dpb_stride_size);</div><div class='add'>+		writel(ctx-&gt;stride[1], mfc_regs-&gt;d_second_plane_dpb_stride_size);</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M)</div><div class='add'>+			writel(ctx-&gt;stride[2], mfc_regs-&gt;d_third_plane_dpb_stride_size);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	buf_addr1 += ctx-&gt;scratch_buf_size;</div><div class='hunk'>@@ -566,6 +663,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 					ctx-&gt;dst_bufs[i].cookie.raw.chroma);</div><div class='ctx'> 		writel(ctx-&gt;dst_bufs[i].cookie.raw.chroma,</div><div class='ctx'> 				mfc_regs-&gt;d_second_plane_dpb + i * 4);</div><div class='add'>+		if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;dst_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+			mfc_debug(2, "\tChroma_1 %d: %zx\n", i, ctx</div><div class='add'>+					-&gt;dst_bufs[i].cookie.raw.chroma_1);</div><div class='add'>+			writel(ctx-&gt;dst_bufs[i].cookie.raw.chroma_1, mfc_regs-&gt;d_third_plane_dpb +</div><div class='add'>+					i * 4);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ctx-&gt;codec_mode == S5P_MFC_CODEC_H264_DEC ||</div><div class='ctx'> 			ctx-&gt;codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||</div><div class='hunk'>@@ -624,20 +728,24 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,</div><div class='del'>-		unsigned long y_addr, unsigned long c_addr)</div><div class='add'>+		unsigned long y_addr, unsigned long c_addr,</div><div class='add'>+		unsigned long c_1_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	const struct s5p_mfc_regs *mfc_regs = dev-&gt;mfc_regs;</div><div class='ctx'> </div><div class='ctx'> 	writel(y_addr, mfc_regs-&gt;e_source_first_plane_addr);</div><div class='ctx'> 	writel(c_addr, mfc_regs-&gt;e_source_second_plane_addr);</div><div class='add'>+	writel(c_1_addr, mfc_regs-&gt;e_source_third_plane_addr);</div><div class='ctx'> </div><div class='ctx'> 	mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);</div><div class='ctx'> 	mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);</div><div class='add'>+	mfc_debug(2, "enc src cr buf addr: 0x%08lx\n", c_1_addr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,</div><div class='del'>-		unsigned long *y_addr, unsigned long *c_addr)</div><div class='add'>+		unsigned long *y_addr, unsigned long *c_addr,</div><div class='add'>+		unsigned long *c_1_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	const struct s5p_mfc_regs *mfc_regs = dev-&gt;mfc_regs;</div><div class='hunk'>@@ -645,12 +753,17 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,</div><div class='ctx'> </div><div class='ctx'> 	*y_addr = readl(mfc_regs-&gt;e_encoded_source_first_plane_addr);</div><div class='ctx'> 	*c_addr = readl(mfc_regs-&gt;e_encoded_source_second_plane_addr);</div><div class='add'>+	if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+			V4L2_PIX_FMT_YVU420M)</div><div class='add'>+		*c_1_addr = readl(mfc_regs-&gt;e_encoded_source_third_plane_addr);</div><div class='add'>+	else</div><div class='add'>+		*c_1_addr = 0;</div><div class='ctx'> </div><div class='ctx'> 	enc_recon_y_addr = readl(mfc_regs-&gt;e_recon_luma_dpb_addr);</div><div class='ctx'> 	enc_recon_c_addr = readl(mfc_regs-&gt;e_recon_chroma_dpb_addr);</div><div class='ctx'> </div><div class='ctx'> 	mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);</div><div class='del'>-	mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);</div><div class='add'>+	mfc_debug(2, "recon c addr: 0x%08lx c_addr: 0x%08lx\n", enc_recon_c_addr, *c_addr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Set encoding ref &amp; codec buffer */</div><div class='hunk'>@@ -668,7 +781,7 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);</div><div class='ctx'> </div><div class='del'>-	if (IS_MFCV10(dev)) {</div><div class='add'>+	if (IS_MFCV10_PLUS(dev)) {</div><div class='ctx'> 		/* start address of per buffer is aligned */</div><div class='ctx'> 		for (i = 0; i &lt; ctx-&gt;pb_count; i++) {</div><div class='ctx'> 			writel(buf_addr1, mfc_regs-&gt;e_luma_dpb + (4 * i));</div><div class='hunk'>@@ -827,6 +940,20 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 		writel(reg, mfc_regs-&gt;e_enc_options);</div><div class='ctx'> 		/* 0: NV12(CbCr), 1: NV21(CrCb) */</div><div class='ctx'> 		writel(0x0, mfc_regs-&gt;pixel_format);</div><div class='add'>+	} else if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YVU420M) {</div><div class='add'>+		/* 0: Linear, 1: 2D tiled*/</div><div class='add'>+		reg = readl(mfc_regs-&gt;e_enc_options);</div><div class='add'>+		reg &amp;= ~(0x1 &lt;&lt; 7);</div><div class='add'>+		writel(reg, mfc_regs-&gt;e_enc_options);</div><div class='add'>+		/* 2: YV12(CrCb), 3: I420(CrCb) */</div><div class='add'>+		writel(0x2, mfc_regs-&gt;pixel_format);</div><div class='add'>+	} else if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M) {</div><div class='add'>+		/* 0: Linear, 1: 2D tiled*/</div><div class='add'>+		reg = readl(mfc_regs-&gt;e_enc_options);</div><div class='add'>+		reg &amp;= ~(0x1 &lt;&lt; 7);</div><div class='add'>+		writel(reg, mfc_regs-&gt;e_enc_options);</div><div class='add'>+		/* 2: YV12(CrCb), 3: I420(CrCb) */</div><div class='add'>+		writel(0x3, mfc_regs-&gt;pixel_format);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* memory structure recon. frame */</div><div class='hunk'>@@ -865,10 +992,24 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	/* reaction coefficient */</div><div class='ctx'> 	if (p-&gt;rc_frame) {</div><div class='del'>-		if (p-&gt;rc_reaction_coeff &lt; TIGHT_CBR_MAX) /* tight CBR */</div><div class='del'>-			writel(1, mfc_regs-&gt;e_rc_mode);</div><div class='del'>-		else					  /* loose CBR */</div><div class='del'>-			writel(2, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+		if (IS_MFCV12(dev)) {</div><div class='add'>+			/* loose CBR */</div><div class='add'>+			if (p-&gt;rc_reaction_coeff &lt; LOOSE_CBR_MAX)</div><div class='add'>+				writel(1, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+			/* tight CBR */</div><div class='add'>+			else if (p-&gt;rc_reaction_coeff &lt; TIGHT_CBR_MAX)</div><div class='add'>+				writel(0, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+			/* VBR */</div><div class='add'>+			else</div><div class='add'>+				writel(2, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+		} else {</div><div class='add'>+			/* tight CBR */</div><div class='add'>+			if (p-&gt;rc_reaction_coeff &lt; TIGHT_CBR_MAX)</div><div class='add'>+				writel(1, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+			/* loose CBR */</div><div class='add'>+			else</div><div class='add'>+				writel(2, mfc_regs-&gt;e_rc_mode);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* seq header ctrl */</div><div class='hunk'>@@ -930,6 +1071,18 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	reg |= ((p-&gt;num_b_frame &amp; 0x3) &lt;&lt; 16);</div><div class='ctx'> 	writel(reg, mfc_regs-&gt;e_gop_config);</div><div class='ctx'> </div><div class='add'>+	/* UHD encoding case */</div><div class='add'>+	if (ctx-&gt;img_width == 3840 &amp;&amp; ctx-&gt;img_height == 2160) {</div><div class='add'>+		if (p_h264-&gt;level &lt; 51) {</div><div class='add'>+			mfc_debug(2, "Set Level 5.1 for UHD\n");</div><div class='add'>+			p_h264-&gt;level = 51;</div><div class='add'>+		}</div><div class='add'>+		if (p_h264-&gt;profile != 0x2) {</div><div class='add'>+			mfc_debug(2, "Set High profile for UHD\n");</div><div class='add'>+			p_h264-&gt;profile = 0x2;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* profile &amp; level */</div><div class='ctx'> 	reg = 0;</div><div class='ctx'> 	/** level */</div><div class='hunk'>@@ -1637,8 +1790,12 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	else</div><div class='ctx'> 		writel(reg, mfc_regs-&gt;d_dec_options);</div><div class='ctx'> </div><div class='del'>-	/* 0: NV12(CbCr), 1: NV21(CrCb) */</div><div class='del'>-	if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_NV21M)</div><div class='add'>+	/* 0: NV12(CbCr), 1: NV21(CrCb), 2: YV12(CrCb), 3: I420(CbCr) */</div><div class='add'>+	if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M)</div><div class='add'>+		writel(0x3, mfc_regs-&gt;pixel_format);</div><div class='add'>+	else if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_YVU420M)</div><div class='add'>+		writel(0x2, mfc_regs-&gt;pixel_format);</div><div class='add'>+	else if (ctx-&gt;dst_fmt-&gt;fourcc == V4L2_PIX_FMT_NV21M)</div><div class='ctx'> 		writel(0x1, mfc_regs-&gt;pixel_format);</div><div class='ctx'> 	else</div><div class='ctx'> 		writel(0x0, mfc_regs-&gt;pixel_format);</div><div class='hunk'>@@ -1722,8 +1879,11 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	/* Set stride lengths for v7 &amp; above */</div><div class='ctx'> 	if (IS_MFCV7_PLUS(dev)) {</div><div class='del'>-		writel(ctx-&gt;img_width, mfc_regs-&gt;e_source_first_plane_stride);</div><div class='del'>-		writel(ctx-&gt;img_width, mfc_regs-&gt;e_source_second_plane_stride);</div><div class='add'>+		writel(ctx-&gt;stride[0], mfc_regs-&gt;e_source_first_plane_stride);</div><div class='add'>+		writel(ctx-&gt;stride[1], mfc_regs-&gt;e_source_second_plane_stride);</div><div class='add'>+		if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+				V4L2_PIX_FMT_YVU420M)</div><div class='add'>+			writel(ctx-&gt;stride[2], mfc_regs-&gt;e_source_third_plane_stride);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	writel(ctx-&gt;inst_no, mfc_regs-&gt;instance_id);</div><div class='hunk'>@@ -1832,7 +1992,7 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	struct s5p_mfc_buf *dst_mb;</div><div class='ctx'> 	struct s5p_mfc_buf *src_mb;</div><div class='del'>-	unsigned long src_y_addr, src_c_addr, dst_addr;</div><div class='add'>+	unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;</div><div class='ctx'> 	/*</div><div class='ctx'> 	unsigned int src_y_size, src_c_size;</div><div class='ctx'> 	*/</div><div class='hunk'>@@ -1850,22 +2010,28 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	if (list_empty(&amp;ctx-&gt;src_queue)) {</div><div class='ctx'> 		/* send null frame */</div><div class='del'>-		s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);</div><div class='add'>+		s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);</div><div class='ctx'> 		src_mb = NULL;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		src_mb = list_entry(ctx-&gt;src_queue.next, struct s5p_mfc_buf, list);</div><div class='ctx'> 		src_mb-&gt;flags |= MFC_BUF_FLAG_USED;</div><div class='ctx'> 		if (src_mb-&gt;b-&gt;vb2_buf.planes[0].bytesused == 0) {</div><div class='del'>-			s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);</div><div class='add'>+			s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);</div><div class='ctx'> 			ctx-&gt;state = MFCINST_FINISHING;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			src_y_addr = vb2_dma_contig_plane_dma_addr(&amp;src_mb-&gt;b-&gt;vb2_buf, 0);</div><div class='ctx'> 			src_c_addr = vb2_dma_contig_plane_dma_addr(&amp;src_mb-&gt;b-&gt;vb2_buf, 1);</div><div class='add'>+			if (ctx-&gt;src_fmt-&gt;fourcc == V4L2_PIX_FMT_YUV420M || ctx-&gt;src_fmt-&gt;fourcc ==</div><div class='add'>+					V4L2_PIX_FMT_YVU420M)</div><div class='add'>+				src_c_1_addr = vb2_dma_contig_plane_dma_addr</div><div class='add'>+					(&amp;src_mb-&gt;b-&gt;vb2_buf, 2);</div><div class='add'>+			else</div><div class='add'>+				src_c_1_addr = 0;</div><div class='ctx'> </div><div class='ctx'> 			mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);</div><div class='ctx'> 			mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);</div><div class='ctx'> </div><div class='del'>-			s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);</div><div class='add'>+			s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr, src_c_1_addr);</div><div class='ctx'> 			if (src_mb-&gt;flags &amp; MFC_BUF_FLAG_EOS)</div><div class='ctx'> 				ctx-&gt;state = MFCINST_FINISHING;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1944,6 +2110,13 @@ static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)</div><div class='ctx'> 	struct s5p_mfc_dev *dev = ctx-&gt;dev;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	ret = s5p_mfc_hw_call(ctx-&gt;dev-&gt;mfc_ops, alloc_codec_buffers, ctx);</div><div class='add'>+	if (ret) {</div><div class='add'>+		mfc_err("Failed to allocate encoding buffers\n");</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+	mfc_debug(2, "Allocated Internal Encoding Buffers\n");</div><div class='add'>+</div><div class='ctx'> 	dev-&gt;curr_ctx = ctx-&gt;num;</div><div class='ctx'> 	ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2387,10 +2560,9 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)</div><div class='ctx'> 	R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);</div><div class='ctx'> 	R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);</div><div class='ctx'> 	R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);</div><div class='del'>-	R(e_encoded_source_first_plane_addr,</div><div class='del'>-			S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);</div><div class='del'>-	R(e_encoded_source_second_plane_addr,</div><div class='del'>-			S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);</div><div class='add'>+	R(e_encoded_source_first_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);</div><div class='add'>+	R(e_encoded_source_second_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);</div><div class='add'>+	R(e_encoded_source_third_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7);</div><div class='ctx'> 	R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);</div><div class='ctx'> </div><div class='ctx'> 	if (!IS_MFCV8_PLUS(dev))</div><div class='hunk'>@@ -2405,16 +2577,17 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)</div><div class='ctx'> 	R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);</div><div class='ctx'> 	R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);</div><div class='ctx'> 	R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);</div><div class='add'>+	R(d_third_plane_dpb_size, S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8);</div><div class='ctx'> 	R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);</div><div class='ctx'> 	R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);</div><div class='del'>-	R(d_first_plane_dpb_stride_size,</div><div class='del'>-			S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);</div><div class='del'>-	R(d_second_plane_dpb_stride_size,</div><div class='del'>-			S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);</div><div class='add'>+	R(d_first_plane_dpb_stride_size, S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);</div><div class='add'>+	R(d_second_plane_dpb_stride_size, S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);</div><div class='add'>+	R(d_third_plane_dpb_stride_size, S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8);</div><div class='ctx'> 	R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);</div><div class='ctx'> 	R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);</div><div class='ctx'> 	R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);</div><div class='ctx'> 	R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);</div><div class='add'>+	R(d_third_plane_dpb, S5P_FIMV_D_THIRD_PLANE_DPB_V8);</div><div class='ctx'> 	R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);</div><div class='ctx'> 	R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);</div><div class='ctx'> 	R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);</div><div class='hunk'>@@ -2455,7 +2628,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)</div><div class='ctx'> 	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);</div><div class='ctx'> 	R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);</div><div class='ctx'> </div><div class='del'>-	if (!IS_MFCV10(dev))</div><div class='add'>+	if (!IS_MFCV10_PLUS(dev))</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize registers used in MFC v10 only.</div><div class='head'>diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h<br/>index e4dd03c5454c..94ecb0e6e7c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h</a></div><div class='hunk'>@@ -19,10 +19,8 @@</div><div class='ctx'> </div><div class='ctx'> #define MB_WIDTH(x_size)		DIV_ROUND_UP(x_size, 16)</div><div class='ctx'> #define MB_HEIGHT(y_size)		DIV_ROUND_UP(y_size, 16)</div><div class='del'>-#define S5P_MFC_DEC_MV_SIZE_V6(x, y)	(MB_WIDTH(x) * \</div><div class='del'>-					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)</div><div class='del'>-#define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \</div><div class='del'>-					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)</div><div class='add'>+#define S5P_MFC_DEC_MV_SIZE(x, y, offset)	(MB_WIDTH(x) * \</div><div class='add'>+					(((MB_HEIGHT(y) + 1) / 2) * 2) * 64 + (offset))</div><div class='ctx'> #define S5P_MFC_LCU_WIDTH(x_size)	DIV_ROUND_UP(x_size, 32)</div><div class='ctx'> #define S5P_MFC_LCU_HEIGHT(y_size)	DIV_ROUND_UP(y_size, 32)</div><div class='ctx'> </div><div class='hunk'>@@ -42,6 +40,7 @@</div><div class='ctx'> #define ENC_H264_LEVEL_MAX		42</div><div class='ctx'> #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 &lt;&lt; 16) - 1)</div><div class='ctx'> #define FRAME_DELTA_H264_H263		1</div><div class='add'>+#define LOOSE_CBR_MAX			5</div><div class='ctx'> #define TIGHT_CBR_MAX			10</div><div class='ctx'> #define ENC_HEVC_RC_FRAME_RATE_MAX	((1 &lt;&lt; 16) - 1)</div><div class='ctx'> #define ENC_HEVC_QP_INDEX_MIN		-12</div><div class='head'>diff --git a/drivers/media/platform/st/sti/hva/hva-v4l2.c b/drivers/media/platform/st/sti/hva/hva-v4l2.c<br/>index 3a848ca32a0e..161a5c0fbc4e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/st/sti/hva/hva-v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/st/sti/hva/hva-v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/sti/hva/hva-v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/sti/hva/hva-v4l2.c</a></div><div class='hunk'>@@ -569,14 +569,11 @@ static int hva_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)</div><div class='ctx'> 		struct vb2_buffer *vb2_buf;</div><div class='ctx'> </div><div class='ctx'> 		vq = v4l2_m2m_get_vq(ctx-&gt;fh.m2m_ctx, buf-&gt;type);</div><div class='del'>-</div><div class='del'>-		if (buf-&gt;index &gt;= vq-&gt;num_buffers) {</div><div class='del'>-			dev_dbg(dev, "%s buffer index %d out of range (%d)\n",</div><div class='del'>-				ctx-&gt;name, buf-&gt;index, vq-&gt;num_buffers);</div><div class='add'>+		vb2_buf = vb2_get_buffer(vq, buf-&gt;index);</div><div class='add'>+		if (!vb2_buf) {</div><div class='add'>+			dev_dbg(dev, "%s buffer index %d not found\n", ctx-&gt;name, buf-&gt;index);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		vb2_buf = vb2_get_buffer(vq, buf-&gt;index);</div><div class='ctx'> 		stream = to_hva_stream(to_vb2_v4l2_buffer(vb2_buf));</div><div class='ctx'> 		stream-&gt;bytesused = buf-&gt;bytesused;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1145,7 +1142,7 @@ static int hva_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> </div><div class='ctx'> 	src_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_OUTPUT;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct hva_frame);</div><div class='del'>-	src_vq-&gt;min_buffers_needed = MIN_FRAMES;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = MIN_FRAMES;</div><div class='ctx'> 	src_vq-&gt;dev = ctx-&gt;hva_dev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = queue_init(ctx, src_vq);</div><div class='hunk'>@@ -1154,7 +1151,7 @@ static int hva_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> </div><div class='ctx'> 	dst_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct hva_stream);</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = MIN_STREAMS;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = MIN_STREAMS;</div><div class='ctx'> 	dst_vq-&gt;dev = ctx-&gt;hva_dev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	return queue_init(ctx, dst_vq);</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/Kconfig b/drivers/media/platform/st/stm32/Kconfig<br/>index b22dd4753496..9df9a2a17728 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/st/stm32/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/Kconfig</a></div><div class='hunk'>@@ -16,6 +16,22 @@ config VIDEO_STM32_DCMI</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module</div><div class='ctx'> 	  will be called stm32-dcmi.</div><div class='ctx'> </div><div class='add'>+config VIDEO_STM32_DCMIPP</div><div class='add'>+	tristate "STM32 Digital Camera Memory Interface Pixel Processor (DCMIPP) support"</div><div class='add'>+	depends on V4L_PLATFORM_DRIVERS</div><div class='add'>+	depends on VIDEO_DEV</div><div class='add'>+	depends on ARCH_STM32 || COMPILE_TEST</div><div class='add'>+	select MEDIA_CONTROLLER</div><div class='add'>+	select VIDEOBUF2_DMA_CONTIG</div><div class='add'>+	select VIDEO_V4L2_SUBDEV_API</div><div class='add'>+	select V4L2_FWNODE</div><div class='add'>+	help</div><div class='add'>+	  This module makes the STM32 Digital Camera Memory Interface</div><div class='add'>+	  Pixel Processor (DCMIPP) available as a v4l2 device.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the module</div><div class='add'>+	  will be called stm32-dcmipp.</div><div class='add'>+</div><div class='ctx'> # Mem2mem drivers</div><div class='ctx'> config VIDEO_STM32_DMA2D</div><div class='ctx'> 	tristate "STM32 Chrom-Art Accelerator (DMA2D)"</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/Makefile b/drivers/media/platform/st/stm32/Makefile<br/>index 896ef98a73ab..7ed8297b9b19 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/st/stm32/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/Makefile</a></div><div class='hunk'>@@ -1,4 +1,5 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32-dcmi.o</div><div class='add'>+obj-$(CONFIG_VIDEO_STM32_DCMIPP) += stm32-dcmipp/</div><div class='ctx'> stm32-dma2d-objs := dma2d/dma2d.o dma2d/dma2d-hw.o</div><div class='ctx'> obj-$(CONFIG_VIDEO_STM32_DMA2D) += stm32-dma2d.o</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c<br/>index 8cb4fdcae137..c4610e305546 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/st/stm32/stm32-dcmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmi.c</a></div><div class='hunk'>@@ -20,7 +20,6 @@</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/of_graph.h&gt;</div><div class='ctx'> #include &lt;linux/pinctrl/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='hunk'>@@ -1890,7 +1889,6 @@ static int dcmi_graph_init(struct stm32_dcmi *dcmi)</div><div class='ctx'> static int dcmi_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_node *np = pdev-&gt;dev.of_node;</div><div class='del'>-	const struct of_device_id *match = NULL;</div><div class='ctx'> 	struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };</div><div class='ctx'> 	struct stm32_dcmi *dcmi;</div><div class='ctx'> 	struct vb2_queue *q;</div><div class='hunk'>@@ -1899,12 +1897,6 @@ static int dcmi_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct clk *mclk;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	match = of_match_device(of_match_ptr(stm32_dcmi_of_match), &amp;pdev-&gt;dev);</div><div class='del'>-	if (!match) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "Could not find a match in devicetree\n");</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	dcmi = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(struct stm32_dcmi), GFP_KERNEL);</div><div class='ctx'> 	if (!dcmi)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -2039,7 +2031,7 @@ static int dcmi_probe(struct platform_device *pdev)</div><div class='ctx'> 	q-&gt;ops = &amp;dcmi_video_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;allow_cache_hints = 1;</div><div class='ctx'> 	q-&gt;dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/Makefile b/drivers/media/platform/st/stm32/stm32-dcmipp/Makefile<br/>new file mode 100644<br/>index 000000000000..8920d9388a21<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/Makefile</a></div><div class='hunk'>@@ -0,0 +1,4 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+stm32-dcmipp-y := dcmipp-core.o dcmipp-common.o dcmipp-parallel.o dcmipp-byteproc.o dcmipp-bytecap.o</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_VIDEO_STM32_DCMIPP) += stm32-dcmipp.o</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c<br/>new file mode 100644<br/>index 000000000000..9f768f011fa2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c</a></div><div class='hunk'>@@ -0,0 +1,956 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;media/v4l2-ioctl.h&gt;</div><div class='add'>+#include &lt;media/v4l2-mc.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-core.h&gt;</div><div class='add'>+#include &lt;media/videobuf2-dma-contig.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dcmipp-common.h"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_PRSR		0x1f8</div><div class='add'>+#define DCMIPP_CMIER		0x3f0</div><div class='add'>+#define DCMIPP_CMIER_P0FRAMEIE	BIT(9)</div><div class='add'>+#define DCMIPP_CMIER_P0VSYNCIE	BIT(10)</div><div class='add'>+#define DCMIPP_CMIER_P0OVRIE	BIT(15)</div><div class='add'>+#define DCMIPP_CMIER_P0ALL	(DCMIPP_CMIER_P0VSYNCIE |\</div><div class='add'>+				 DCMIPP_CMIER_P0FRAMEIE |\</div><div class='add'>+				 DCMIPP_CMIER_P0OVRIE)</div><div class='add'>+#define DCMIPP_CMSR1		0x3f4</div><div class='add'>+#define DCMIPP_CMSR2		0x3f8</div><div class='add'>+#define DCMIPP_CMSR2_P0FRAMEF	BIT(9)</div><div class='add'>+#define DCMIPP_CMSR2_P0VSYNCF	BIT(10)</div><div class='add'>+#define DCMIPP_CMSR2_P0OVRF	BIT(15)</div><div class='add'>+#define DCMIPP_CMFCR		0x3fc</div><div class='add'>+#define DCMIPP_P0FSCR		0x404</div><div class='add'>+#define DCMIPP_P0FSCR_PIPEN	BIT(31)</div><div class='add'>+#define DCMIPP_P0FCTCR		0x500</div><div class='add'>+#define DCMIPP_P0FCTCR_CPTREQ	BIT(3)</div><div class='add'>+#define DCMIPP_P0DCCNTR		0x5b0</div><div class='add'>+#define DCMIPP_P0DCLMTR		0x5b4</div><div class='add'>+#define DCMIPP_P0DCLMTR_ENABLE	BIT(31)</div><div class='add'>+#define DCMIPP_P0DCLMTR_LIMIT_MASK	GENMASK(23, 0)</div><div class='add'>+#define DCMIPP_P0PPM0AR1	0x5c4</div><div class='add'>+#define DCMIPP_P0SR		0x5f8</div><div class='add'>+#define DCMIPP_P0SR_CPTACT	BIT(23)</div><div class='add'>+</div><div class='add'>+struct dcmipp_bytecap_pix_map {</div><div class='add'>+	unsigned int code;</div><div class='add'>+	u32 pixelformat;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define PIXMAP_MBUS_PFMT(mbus, fmt)			\</div><div class='add'>+	{						\</div><div class='add'>+		.code = MEDIA_BUS_FMT_##mbus,		\</div><div class='add'>+		.pixelformat = V4L2_PIX_FMT_##fmt	\</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_bytecap_pix_map dcmipp_bytecap_pix_map_list[] = {</div><div class='add'>+	PIXMAP_MBUS_PFMT(RGB565_2X8_LE, RGB565),</div><div class='add'>+	PIXMAP_MBUS_PFMT(YUYV8_2X8, YUYV),</div><div class='add'>+	PIXMAP_MBUS_PFMT(YVYU8_2X8, YVYU),</div><div class='add'>+	PIXMAP_MBUS_PFMT(UYVY8_2X8, UYVY),</div><div class='add'>+	PIXMAP_MBUS_PFMT(VYUY8_2X8, VYUY),</div><div class='add'>+	PIXMAP_MBUS_PFMT(Y8_1X8, GREY),</div><div class='add'>+	PIXMAP_MBUS_PFMT(SBGGR8_1X8, SBGGR8),</div><div class='add'>+	PIXMAP_MBUS_PFMT(SGBRG8_1X8, SGBRG8),</div><div class='add'>+	PIXMAP_MBUS_PFMT(SGRBG8_1X8, SGRBG8),</div><div class='add'>+	PIXMAP_MBUS_PFMT(SRGGB8_1X8, SRGGB8),</div><div class='add'>+	PIXMAP_MBUS_PFMT(JPEG_1X8, JPEG),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_bytecap_pix_map *</div><div class='add'>+dcmipp_bytecap_pix_map_by_pixelformat(u32 pixelformat)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(dcmipp_bytecap_pix_map_list); i++) {</div><div class='add'>+		if (dcmipp_bytecap_pix_map_list[i].pixelformat == pixelformat)</div><div class='add'>+			return &amp;dcmipp_bytecap_pix_map_list[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_buf {</div><div class='add'>+	struct vb2_v4l2_buffer	vb;</div><div class='add'>+	bool			prepared;</div><div class='add'>+	dma_addr_t		addr;</div><div class='add'>+	size_t			size;</div><div class='add'>+	struct list_head	list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum dcmipp_state {</div><div class='add'>+	DCMIPP_STOPPED = 0,</div><div class='add'>+	DCMIPP_WAIT_FOR_BUFFER,</div><div class='add'>+	DCMIPP_RUNNING,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcmipp_bytecap_device {</div><div class='add'>+	struct dcmipp_ent_device ved;</div><div class='add'>+	struct video_device vdev;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct v4l2_pix_format format;</div><div class='add'>+	struct vb2_queue queue;</div><div class='add'>+	struct list_head buffers;</div><div class='add'>+	/*</div><div class='add'>+	 * Protects concurrent calls of buf queue / irq handler</div><div class='add'>+	 * and buffer handling related variables / lists</div><div class='add'>+	 */</div><div class='add'>+	spinlock_t irqlock;</div><div class='add'>+	/* mutex used as vdev and queue lock */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	u32 sequence;</div><div class='add'>+	struct media_pipeline pipe;</div><div class='add'>+	struct v4l2_subdev *s_subdev;</div><div class='add'>+</div><div class='add'>+	enum dcmipp_state state;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * DCMIPP driver is handling 2 buffers</div><div class='add'>+	 * active: buffer into which DCMIPP is currently writing into</div><div class='add'>+	 * next: buffer given to the DCMIPP and which will become</div><div class='add'>+	 *       automatically active on next VSYNC</div><div class='add'>+	 */</div><div class='add'>+	struct dcmipp_buf *active, *next;</div><div class='add'>+</div><div class='add'>+	void __iomem *regs;</div><div class='add'>+</div><div class='add'>+	u32 cmier;</div><div class='add'>+	u32 cmsr2;</div><div class='add'>+</div><div class='add'>+	struct {</div><div class='add'>+		u32 errors;</div><div class='add'>+		u32 limit;</div><div class='add'>+		u32 overrun;</div><div class='add'>+		u32 buffers;</div><div class='add'>+		u32 vsync;</div><div class='add'>+		u32 frame;</div><div class='add'>+		u32 it;</div><div class='add'>+		u32 underrun;</div><div class='add'>+		u32 nactive;</div><div class='add'>+	} count;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_pix_format fmt_default = {</div><div class='add'>+	.width = DCMIPP_FMT_WIDTH_DEFAULT,</div><div class='add'>+	.height = DCMIPP_FMT_HEIGHT_DEFAULT,</div><div class='add'>+	.pixelformat = V4L2_PIX_FMT_RGB565,</div><div class='add'>+	.field = V4L2_FIELD_NONE,</div><div class='add'>+	.bytesperline = DCMIPP_FMT_WIDTH_DEFAULT * 2,</div><div class='add'>+	.sizeimage = DCMIPP_FMT_WIDTH_DEFAULT * DCMIPP_FMT_HEIGHT_DEFAULT * 2,</div><div class='add'>+	.colorspace = DCMIPP_COLORSPACE_DEFAULT,</div><div class='add'>+	.ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,</div><div class='add'>+	.quantization = DCMIPP_QUANTIZATION_DEFAULT,</div><div class='add'>+	.xfer_func = DCMIPP_XFER_FUNC_DEFAULT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_querycap(struct file *file, void *priv,</div><div class='add'>+				   struct v4l2_capability *cap)</div><div class='add'>+{</div><div class='add'>+	strscpy(cap-&gt;driver, DCMIPP_PDEV_NAME, sizeof(cap-&gt;driver));</div><div class='add'>+	strscpy(cap-&gt;card, KBUILD_MODNAME, sizeof(cap-&gt;card));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_g_fmt_vid_cap(struct file *file, void *priv,</div><div class='add'>+					struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = video_drvdata(file);</div><div class='add'>+</div><div class='add'>+	f-&gt;fmt.pix = vcap-&gt;format;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_try_fmt_vid_cap(struct file *file, void *priv,</div><div class='add'>+					  struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = video_drvdata(file);</div><div class='add'>+	struct v4l2_pix_format *format = &amp;f-&gt;fmt.pix;</div><div class='add'>+	const struct dcmipp_bytecap_pix_map *vpix;</div><div class='add'>+	u32 in_w, in_h;</div><div class='add'>+</div><div class='add'>+	/* Don't accept a pixelformat that is not on the table */</div><div class='add'>+	vpix = dcmipp_bytecap_pix_map_by_pixelformat(format-&gt;pixelformat);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		format-&gt;pixelformat = fmt_default.pixelformat;</div><div class='add'>+</div><div class='add'>+	/* Adjust width &amp; height */</div><div class='add'>+	in_w = format-&gt;width;</div><div class='add'>+	in_h = format-&gt;height;</div><div class='add'>+	v4l_bound_align_image(&amp;format-&gt;width, DCMIPP_FRAME_MIN_WIDTH,</div><div class='add'>+			      DCMIPP_FRAME_MAX_WIDTH, 0, &amp;format-&gt;height,</div><div class='add'>+			      DCMIPP_FRAME_MIN_HEIGHT, DCMIPP_FRAME_MAX_HEIGHT,</div><div class='add'>+			      0, 0);</div><div class='add'>+	if (format-&gt;width != in_w || format-&gt;height != in_h)</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "resolution updated: %dx%d -&gt; %dx%d\n",</div><div class='add'>+			in_w, in_h, format-&gt;width, format-&gt;height);</div><div class='add'>+</div><div class='add'>+	if (format-&gt;pixelformat == V4L2_PIX_FMT_JPEG) {</div><div class='add'>+		format-&gt;bytesperline = format-&gt;width;</div><div class='add'>+		format-&gt;sizeimage = format-&gt;bytesperline * format-&gt;height;</div><div class='add'>+	} else {</div><div class='add'>+		v4l2_fill_pixfmt(format, format-&gt;pixelformat,</div><div class='add'>+				 format-&gt;width, format-&gt;height);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (format-&gt;field == V4L2_FIELD_ANY)</div><div class='add'>+		format-&gt;field = fmt_default.field;</div><div class='add'>+</div><div class='add'>+	dcmipp_colorimetry_clamp(format);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_s_fmt_vid_cap(struct file *file, void *priv,</div><div class='add'>+					struct v4l2_format *f)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = video_drvdata(file);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Do not change the format while stream is on */</div><div class='add'>+	if (vb2_is_busy(&amp;vcap-&gt;queue))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	ret = dcmipp_bytecap_try_fmt_vid_cap(file, priv, f);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "%s: format update: old:%ux%u (0x%p4cc, %u, %u, %u, %u) new:%ux%d (0x%p4cc, %u, %u, %u, %u)\n",</div><div class='add'>+		vcap-&gt;vdev.name,</div><div class='add'>+		/* old */</div><div class='add'>+		vcap-&gt;format.width, vcap-&gt;format.height,</div><div class='add'>+		&amp;vcap-&gt;format.pixelformat, vcap-&gt;format.colorspace,</div><div class='add'>+		vcap-&gt;format.quantization, vcap-&gt;format.xfer_func,</div><div class='add'>+		vcap-&gt;format.ycbcr_enc,</div><div class='add'>+		/* new */</div><div class='add'>+		f-&gt;fmt.pix.width, f-&gt;fmt.pix.height,</div><div class='add'>+		&amp;f-&gt;fmt.pix.pixelformat, f-&gt;fmt.pix.colorspace,</div><div class='add'>+		f-&gt;fmt.pix.quantization, f-&gt;fmt.pix.xfer_func,</div><div class='add'>+		f-&gt;fmt.pix.ycbcr_enc);</div><div class='add'>+</div><div class='add'>+	vcap-&gt;format = f-&gt;fmt.pix;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_enum_fmt_vid_cap(struct file *file, void *priv,</div><div class='add'>+					   struct v4l2_fmtdesc *f)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_bytecap_pix_map *vpix;</div><div class='add'>+	unsigned int index = f-&gt;index;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (f-&gt;mbus_code) {</div><div class='add'>+		/*</div><div class='add'>+		 * If a media bus code is specified, only enumerate formats</div><div class='add'>+		 * compatible with it.</div><div class='add'>+		 */</div><div class='add'>+		for (i = 0; i &lt; ARRAY_SIZE(dcmipp_bytecap_pix_map_list); i++) {</div><div class='add'>+			vpix = &amp;dcmipp_bytecap_pix_map_list[i];</div><div class='add'>+			if (vpix-&gt;code != f-&gt;mbus_code)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (index == 0)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			index--;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (i == ARRAY_SIZE(dcmipp_bytecap_pix_map_list))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	} else {</div><div class='add'>+		/* Otherwise, enumerate all formats. */</div><div class='add'>+		if (f-&gt;index &gt;= ARRAY_SIZE(dcmipp_bytecap_pix_map_list))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		vpix = &amp;dcmipp_bytecap_pix_map_list[f-&gt;index];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	f-&gt;pixelformat = vpix-&gt;pixelformat;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_enum_framesizes(struct file *file, void *fh,</div><div class='add'>+					  struct v4l2_frmsizeenum *fsize)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_bytecap_pix_map *vpix;</div><div class='add'>+</div><div class='add'>+	if (fsize-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Only accept code in the pix map table */</div><div class='add'>+	vpix = dcmipp_bytecap_pix_map_by_pixelformat(fsize-&gt;pixel_format);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fsize-&gt;type = V4L2_FRMSIZE_TYPE_CONTINUOUS;</div><div class='add'>+	fsize-&gt;stepwise.min_width = DCMIPP_FRAME_MIN_WIDTH;</div><div class='add'>+	fsize-&gt;stepwise.max_width = DCMIPP_FRAME_MAX_WIDTH;</div><div class='add'>+	fsize-&gt;stepwise.min_height = DCMIPP_FRAME_MIN_HEIGHT;</div><div class='add'>+	fsize-&gt;stepwise.max_height = DCMIPP_FRAME_MAX_HEIGHT;</div><div class='add'>+	fsize-&gt;stepwise.step_width = 1;</div><div class='add'>+	fsize-&gt;stepwise.step_height = 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_file_operations dcmipp_bytecap_fops = {</div><div class='add'>+	.owner		= THIS_MODULE,</div><div class='add'>+	.open		= v4l2_fh_open,</div><div class='add'>+	.release	= vb2_fop_release,</div><div class='add'>+	.read           = vb2_fop_read,</div><div class='add'>+	.poll		= vb2_fop_poll,</div><div class='add'>+	.unlocked_ioctl = video_ioctl2,</div><div class='add'>+	.mmap           = vb2_fop_mmap,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_ioctl_ops dcmipp_bytecap_ioctl_ops = {</div><div class='add'>+	.vidioc_querycap = dcmipp_bytecap_querycap,</div><div class='add'>+</div><div class='add'>+	.vidioc_g_fmt_vid_cap = dcmipp_bytecap_g_fmt_vid_cap,</div><div class='add'>+	.vidioc_s_fmt_vid_cap = dcmipp_bytecap_s_fmt_vid_cap,</div><div class='add'>+	.vidioc_try_fmt_vid_cap = dcmipp_bytecap_try_fmt_vid_cap,</div><div class='add'>+	.vidioc_enum_fmt_vid_cap = dcmipp_bytecap_enum_fmt_vid_cap,</div><div class='add'>+	.vidioc_enum_framesizes = dcmipp_bytecap_enum_framesizes,</div><div class='add'>+</div><div class='add'>+	.vidioc_reqbufs = vb2_ioctl_reqbufs,</div><div class='add'>+	.vidioc_create_bufs = vb2_ioctl_create_bufs,</div><div class='add'>+	.vidioc_prepare_buf = vb2_ioctl_prepare_buf,</div><div class='add'>+	.vidioc_querybuf = vb2_ioctl_querybuf,</div><div class='add'>+	.vidioc_qbuf = vb2_ioctl_qbuf,</div><div class='add'>+	.vidioc_dqbuf = vb2_ioctl_dqbuf,</div><div class='add'>+	.vidioc_expbuf = vb2_ioctl_expbuf,</div><div class='add'>+	.vidioc_streamon = vb2_ioctl_streamon,</div><div class='add'>+	.vidioc_streamoff = vb2_ioctl_streamoff,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_pipeline_s_stream(struct dcmipp_bytecap_device *vcap,</div><div class='add'>+				    int state)</div><div class='add'>+{</div><div class='add'>+	struct media_pad *pad;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Get source subdev - since link is IMMUTABLE, pointer is cached</div><div class='add'>+	 * within the dcmipp_bytecap_device structure</div><div class='add'>+	 */</div><div class='add'>+	if (!vcap-&gt;s_subdev) {</div><div class='add'>+		pad = media_pad_remote_pad_first(&amp;vcap-&gt;vdev.entity.pads[0]);</div><div class='add'>+		if (!pad || !is_media_entity_v4l2_subdev(pad-&gt;entity))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		vcap-&gt;s_subdev = media_entity_to_v4l2_subdev(pad-&gt;entity);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_call(vcap-&gt;s_subdev, video, s_stream, state);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(vcap-&gt;dev, "failed to %s streaming (%d)\n",</div><div class='add'>+			state ? "start" : "stop", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_start_capture(struct dcmipp_bytecap_device *vcap,</div><div class='add'>+				 struct dcmipp_buf *buf)</div><div class='add'>+{</div><div class='add'>+	/* Set buffer address */</div><div class='add'>+	reg_write(vcap, DCMIPP_P0PPM0AR1, buf-&gt;addr);</div><div class='add'>+</div><div class='add'>+	/* Set buffer size */</div><div class='add'>+	reg_write(vcap, DCMIPP_P0DCLMTR, DCMIPP_P0DCLMTR_ENABLE |</div><div class='add'>+		  ((buf-&gt;size / 4) &amp; DCMIPP_P0DCLMTR_LIMIT_MASK));</div><div class='add'>+</div><div class='add'>+	/* Capture request */</div><div class='add'>+	reg_set(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_bytecap_all_buffers_done(struct dcmipp_bytecap_device *vcap,</div><div class='add'>+					    enum vb2_buffer_state state)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_buf *buf, *node;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(buf, node, &amp;vcap-&gt;buffers, list) {</div><div class='add'>+		list_del_init(&amp;buf-&gt;list);</div><div class='add'>+		vb2_buffer_done(&amp;buf-&gt;vb.vb2_buf, state);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_start_streaming(struct vb2_queue *vq,</div><div class='add'>+					  unsigned int count)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = vb2_get_drv_priv(vq);</div><div class='add'>+	struct media_entity *entity = &amp;vcap-&gt;vdev.entity;</div><div class='add'>+	struct dcmipp_buf *buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	vcap-&gt;sequence = 0;</div><div class='add'>+	memset(&amp;vcap-&gt;count, 0, sizeof(vcap-&gt;count));</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(vcap-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(vcap-&gt;dev, "%s: Failed to start streaming, cannot get sync (%d)\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		goto err_buffer_done;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = media_pipeline_start(entity-&gt;pads, &amp;vcap-&gt;pipe);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "%s: Failed to start streaming, media pipeline start error (%d)\n",</div><div class='add'>+			__func__, ret);</div><div class='add'>+		goto err_pm_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = dcmipp_pipeline_s_stream(vcap, 1);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_media_pipeline_stop;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	/* Enable pipe at the end of programming */</div><div class='add'>+	reg_set(vcap, DCMIPP_P0FSCR, DCMIPP_P0FSCR_PIPEN);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * vb2 framework guarantee that we have at least 'min_queued_buffers'</div><div class='add'>+	 * buffers in the list at this moment</div><div class='add'>+	 */</div><div class='add'>+	vcap-&gt;next = list_first_entry(&amp;vcap-&gt;buffers, typeof(*buf), list);</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "Start with next [%d] %p phy=%pad\n",</div><div class='add'>+		vcap-&gt;next-&gt;vb.vb2_buf.index, vcap-&gt;next, &amp;vcap-&gt;next-&gt;addr);</div><div class='add'>+</div><div class='add'>+	dcmipp_start_capture(vcap, vcap-&gt;next);</div><div class='add'>+</div><div class='add'>+	/* Enable interruptions */</div><div class='add'>+	vcap-&gt;cmier |= DCMIPP_CMIER_P0ALL;</div><div class='add'>+	reg_set(vcap, DCMIPP_CMIER, vcap-&gt;cmier);</div><div class='add'>+</div><div class='add'>+	vcap-&gt;state = DCMIPP_RUNNING;</div><div class='add'>+</div><div class='add'>+	spin_unlock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_media_pipeline_stop:</div><div class='add'>+	media_pipeline_stop(entity-&gt;pads);</div><div class='add'>+err_pm_put:</div><div class='add'>+	pm_runtime_put(vcap-&gt;dev);</div><div class='add'>+err_buffer_done:</div><div class='add'>+	spin_lock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+	/*</div><div class='add'>+	 * Return all buffers to vb2 in QUEUED state.</div><div class='add'>+	 * This will give ownership back to userspace</div><div class='add'>+	 */</div><div class='add'>+	dcmipp_bytecap_all_buffers_done(vcap, VB2_BUF_STATE_QUEUED);</div><div class='add'>+	vcap-&gt;active = NULL;</div><div class='add'>+	spin_unlock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_dump_status(struct dcmipp_bytecap_device *vcap)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = vcap-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "[DCMIPP_PRSR]  =%#10.8x\n", reg_read(vcap, DCMIPP_PRSR));</div><div class='add'>+	dev_dbg(dev, "[DCMIPP_P0SR] =%#10.8x\n", reg_read(vcap, DCMIPP_P0SR));</div><div class='add'>+	dev_dbg(dev, "[DCMIPP_P0DCCNTR]=%#10.8x\n",</div><div class='add'>+		reg_read(vcap, DCMIPP_P0DCCNTR));</div><div class='add'>+	dev_dbg(dev, "[DCMIPP_CMSR1] =%#10.8x\n", reg_read(vcap, DCMIPP_CMSR1));</div><div class='add'>+	dev_dbg(dev, "[DCMIPP_CMSR2] =%#10.8x\n", reg_read(vcap, DCMIPP_CMSR2));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Stop the stream engine. Any remaining buffers in the stream queue are</div><div class='add'>+ * dequeued and passed on to the vb2 framework marked as STATE_ERROR.</div><div class='add'>+ */</div><div class='add'>+static void dcmipp_bytecap_stop_streaming(struct vb2_queue *vq)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = vb2_get_drv_priv(vq);</div><div class='add'>+	int ret;</div><div class='add'>+	u32 status;</div><div class='add'>+</div><div class='add'>+	dcmipp_pipeline_s_stream(vcap, 0);</div><div class='add'>+</div><div class='add'>+	/* Stop the media pipeline */</div><div class='add'>+	media_pipeline_stop(vcap-&gt;vdev.entity.pads);</div><div class='add'>+</div><div class='add'>+	/* Disable interruptions */</div><div class='add'>+	reg_clear(vcap, DCMIPP_CMIER, vcap-&gt;cmier);</div><div class='add'>+</div><div class='add'>+	/* Stop capture */</div><div class='add'>+	reg_clear(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);</div><div class='add'>+</div><div class='add'>+	/* Wait until CPTACT become 0 */</div><div class='add'>+	ret = readl_relaxed_poll_timeout(vcap-&gt;regs + DCMIPP_P0SR, status,</div><div class='add'>+					 !(status &amp; DCMIPP_P0SR_CPTACT),</div><div class='add'>+					 20 * USEC_PER_MSEC,</div><div class='add'>+					 1000 * USEC_PER_MSEC);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_warn(vcap-&gt;dev, "Timeout when stopping\n");</div><div class='add'>+</div><div class='add'>+	/* Disable pipe */</div><div class='add'>+	reg_clear(vcap, DCMIPP_P0FSCR, DCMIPP_P0FSCR_PIPEN);</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	/* Return all queued buffers to vb2 in ERROR state */</div><div class='add'>+	dcmipp_bytecap_all_buffers_done(vcap, VB2_BUF_STATE_ERROR);</div><div class='add'>+	INIT_LIST_HEAD(&amp;vcap-&gt;buffers);</div><div class='add'>+</div><div class='add'>+	vcap-&gt;active = NULL;</div><div class='add'>+	vcap-&gt;state = DCMIPP_STOPPED;</div><div class='add'>+</div><div class='add'>+	spin_unlock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	dcmipp_dump_status(vcap);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put(vcap-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (vcap-&gt;count.errors)</div><div class='add'>+		dev_warn(vcap-&gt;dev, "Some errors found while streaming: errors=%d (overrun=%d, limit=%d, nactive=%d), underrun=%d, buffers=%d\n",</div><div class='add'>+			 vcap-&gt;count.errors, vcap-&gt;count.overrun,</div><div class='add'>+			 vcap-&gt;count.limit, vcap-&gt;count.nactive,</div><div class='add'>+			 vcap-&gt;count.underrun, vcap-&gt;count.buffers);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_buf_prepare(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =  vb2_get_drv_priv(vb-&gt;vb2_queue);</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct dcmipp_buf *buf = container_of(vbuf, struct dcmipp_buf, vb);</div><div class='add'>+	unsigned long size;</div><div class='add'>+</div><div class='add'>+	size = vcap-&gt;format.sizeimage;</div><div class='add'>+</div><div class='add'>+	if (vb2_plane_size(vb, 0) &lt; size) {</div><div class='add'>+		dev_err(vcap-&gt;dev, "%s data will not fit into plane (%lu &lt; %lu)\n",</div><div class='add'>+			__func__, vb2_plane_size(vb, 0), size);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vb2_set_plane_payload(vb, 0, size);</div><div class='add'>+</div><div class='add'>+	if (!buf-&gt;prepared) {</div><div class='add'>+		/* Get memory addresses */</div><div class='add'>+		buf-&gt;addr = vb2_dma_contig_plane_dma_addr(&amp;buf-&gt;vb.vb2_buf, 0);</div><div class='add'>+		buf-&gt;size = vb2_plane_size(&amp;buf-&gt;vb.vb2_buf, 0);</div><div class='add'>+		buf-&gt;prepared = true;</div><div class='add'>+</div><div class='add'>+		vb2_set_plane_payload(&amp;buf-&gt;vb.vb2_buf, 0, buf-&gt;size);</div><div class='add'>+</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "Setup [%d] phy=%pad size=%zu\n",</div><div class='add'>+			vb-&gt;index, &amp;buf-&gt;addr, buf-&gt;size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_bytecap_buf_queue(struct vb2_buffer *vb2_buf)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =</div><div class='add'>+		vb2_get_drv_priv(vb2_buf-&gt;vb2_queue);</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb2_buf);</div><div class='add'>+	struct dcmipp_buf *buf = container_of(vbuf, struct dcmipp_buf, vb);</div><div class='add'>+</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "Queue [%d] %p phy=%pad\n", buf-&gt;vb.vb2_buf.index,</div><div class='add'>+		buf, &amp;buf-&gt;addr);</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+	list_add_tail(&amp;buf-&gt;list, &amp;vcap-&gt;buffers);</div><div class='add'>+</div><div class='add'>+	if (vcap-&gt;state == DCMIPP_WAIT_FOR_BUFFER) {</div><div class='add'>+		vcap-&gt;next = buf;</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "Restart with next [%d] %p phy=%pad\n",</div><div class='add'>+			buf-&gt;vb.vb2_buf.index, buf, &amp;buf-&gt;addr);</div><div class='add'>+</div><div class='add'>+		dcmipp_start_capture(vcap, buf);</div><div class='add'>+</div><div class='add'>+		vcap-&gt;state = DCMIPP_RUNNING;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	spin_unlock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_queue_setup(struct vb2_queue *vq,</div><div class='add'>+				      unsigned int *nbuffers,</div><div class='add'>+				      unsigned int *nplanes,</div><div class='add'>+				      unsigned int sizes[],</div><div class='add'>+				      struct device *alloc_devs[])</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int size;</div><div class='add'>+</div><div class='add'>+	size = vcap-&gt;format.sizeimage;</div><div class='add'>+</div><div class='add'>+	/* Make sure the image size is large enough */</div><div class='add'>+	if (*nplanes)</div><div class='add'>+		return sizes[0] &lt; vcap-&gt;format.sizeimage ? -EINVAL : 0;</div><div class='add'>+</div><div class='add'>+	*nplanes = 1;</div><div class='add'>+	sizes[0] = vcap-&gt;format.sizeimage;</div><div class='add'>+</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "Setup queue, count=%d, size=%d\n",</div><div class='add'>+		*nbuffers, size);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_buf_init(struct vb2_buffer *vb)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);</div><div class='add'>+	struct dcmipp_buf *buf = container_of(vbuf, struct dcmipp_buf, vb);</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;buf-&gt;list);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct vb2_ops dcmipp_bytecap_qops = {</div><div class='add'>+	.start_streaming	= dcmipp_bytecap_start_streaming,</div><div class='add'>+	.stop_streaming		= dcmipp_bytecap_stop_streaming,</div><div class='add'>+	.buf_init		= dcmipp_bytecap_buf_init,</div><div class='add'>+	.buf_prepare		= dcmipp_bytecap_buf_prepare,</div><div class='add'>+	.buf_queue		= dcmipp_bytecap_buf_queue,</div><div class='add'>+	.queue_setup		= dcmipp_bytecap_queue_setup,</div><div class='add'>+	/*</div><div class='add'>+	 * Since q-&gt;lock is set we can use the standard</div><div class='add'>+	 * vb2_ops_wait_prepare/finish helper functions.</div><div class='add'>+	 */</div><div class='add'>+	.wait_prepare		= vb2_ops_wait_prepare,</div><div class='add'>+	.wait_finish		= vb2_ops_wait_finish,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcmipp_bytecap_release(struct video_device *vdev)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =</div><div class='add'>+		container_of(vdev, struct dcmipp_bytecap_device, vdev);</div><div class='add'>+</div><div class='add'>+	dcmipp_pads_cleanup(vcap-&gt;ved.pads);</div><div class='add'>+	mutex_destroy(&amp;vcap-&gt;lock);</div><div class='add'>+</div><div class='add'>+	kfree(vcap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void dcmipp_bytecap_ent_release(struct dcmipp_ent_device *ved)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =</div><div class='add'>+		container_of(ved, struct dcmipp_bytecap_device, ved);</div><div class='add'>+</div><div class='add'>+	media_entity_cleanup(ved-&gt;ent);</div><div class='add'>+	vb2_video_unregister_device(&amp;vcap-&gt;vdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_buffer_done(struct dcmipp_bytecap_device *vcap,</div><div class='add'>+			       struct dcmipp_buf *buf,</div><div class='add'>+			       size_t bytesused,</div><div class='add'>+			       int err)</div><div class='add'>+{</div><div class='add'>+	struct vb2_v4l2_buffer *vbuf;</div><div class='add'>+</div><div class='add'>+	list_del_init(&amp;buf-&gt;list);</div><div class='add'>+</div><div class='add'>+	vbuf = &amp;buf-&gt;vb;</div><div class='add'>+</div><div class='add'>+	vbuf-&gt;sequence = vcap-&gt;sequence++;</div><div class='add'>+	vbuf-&gt;field = V4L2_FIELD_NONE;</div><div class='add'>+	vbuf-&gt;vb2_buf.timestamp = ktime_get_ns();</div><div class='add'>+	vb2_set_plane_payload(&amp;vbuf-&gt;vb2_buf, 0, bytesused);</div><div class='add'>+	vb2_buffer_done(&amp;vbuf-&gt;vb2_buf,</div><div class='add'>+			err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "Done  [%d] %p phy=%pad\n", buf-&gt;vb.vb2_buf.index,</div><div class='add'>+		buf, &amp;buf-&gt;addr);</div><div class='add'>+	vcap-&gt;count.buffers++;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* irqlock must be held */</div><div class='add'>+static void</div><div class='add'>+dcmipp_bytecap_set_next_frame_or_stop(struct dcmipp_bytecap_device *vcap)</div><div class='add'>+{</div><div class='add'>+	if (!vcap-&gt;next &amp;&amp; list_is_singular(&amp;vcap-&gt;buffers)) {</div><div class='add'>+		/*</div><div class='add'>+		 * If there is no available buffer (none or a single one in the</div><div class='add'>+		 * list while two are expected), stop the capture (effective</div><div class='add'>+		 * for next frame). On-going frame capture will continue until</div><div class='add'>+		 * FRAME END but no further capture will be done.</div><div class='add'>+		 */</div><div class='add'>+		reg_clear(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);</div><div class='add'>+</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "Capture restart is deferred to next buffer queueing\n");</div><div class='add'>+		vcap-&gt;next = NULL;</div><div class='add'>+		vcap-&gt;state = DCMIPP_WAIT_FOR_BUFFER;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If we don't have buffer yet, pick the one after active */</div><div class='add'>+	if (!vcap-&gt;next)</div><div class='add'>+		vcap-&gt;next = list_next_entry(vcap-&gt;active, list);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set buffer address</div><div class='add'>+	 * This register is shadowed and will be taken into</div><div class='add'>+	 * account on next VSYNC (start of next frame)</div><div class='add'>+	 */</div><div class='add'>+	reg_write(vcap, DCMIPP_P0PPM0AR1, vcap-&gt;next-&gt;addr);</div><div class='add'>+	dev_dbg(vcap-&gt;dev, "Write [%d] %p phy=%pad\n",</div><div class='add'>+		vcap-&gt;next-&gt;vb.vb2_buf.index, vcap-&gt;next, &amp;vcap-&gt;next-&gt;addr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* irqlock must be held */</div><div class='add'>+static void dcmipp_bytecap_process_frame(struct dcmipp_bytecap_device *vcap,</div><div class='add'>+					 size_t bytesused)</div><div class='add'>+{</div><div class='add'>+	int err = 0;</div><div class='add'>+	struct dcmipp_buf *buf = vcap-&gt;active;</div><div class='add'>+</div><div class='add'>+	if (!buf) {</div><div class='add'>+		vcap-&gt;count.nactive++;</div><div class='add'>+		vcap-&gt;count.errors++;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (bytesused &gt; buf-&gt;size) {</div><div class='add'>+		dev_dbg(vcap-&gt;dev, "frame larger than expected (%zu &gt; %zu)\n",</div><div class='add'>+			bytesused, buf-&gt;size);</div><div class='add'>+		/* Clip to buffer size and return buffer to V4L2 in error */</div><div class='add'>+		bytesused = buf-&gt;size;</div><div class='add'>+		vcap-&gt;count.limit++;</div><div class='add'>+		vcap-&gt;count.errors++;</div><div class='add'>+		err = -EOVERFLOW;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dcmipp_buffer_done(vcap, buf, bytesused, err);</div><div class='add'>+	vcap-&gt;active = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t dcmipp_bytecap_irq_thread(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =</div><div class='add'>+			container_of(arg, struct dcmipp_bytecap_device, ved);</div><div class='add'>+	size_t bytesused = 0;</div><div class='add'>+	u32 cmsr2;</div><div class='add'>+</div><div class='add'>+	spin_lock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	cmsr2 = vcap-&gt;cmsr2 &amp; vcap-&gt;cmier;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we have an overrun, a frame-end will probably not be generated,</div><div class='add'>+	 * in that case the active buffer will be recycled as next buffer by</div><div class='add'>+	 * the VSYNC handler</div><div class='add'>+	 */</div><div class='add'>+	if (cmsr2 &amp; DCMIPP_CMSR2_P0OVRF) {</div><div class='add'>+		vcap-&gt;count.errors++;</div><div class='add'>+		vcap-&gt;count.overrun++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cmsr2 &amp; DCMIPP_CMSR2_P0FRAMEF) {</div><div class='add'>+		vcap-&gt;count.frame++;</div><div class='add'>+</div><div class='add'>+		/* Read captured buffer size */</div><div class='add'>+		bytesused = reg_read(vcap, DCMIPP_P0DCCNTR);</div><div class='add'>+		dcmipp_bytecap_process_frame(vcap, bytesused);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cmsr2 &amp; DCMIPP_CMSR2_P0VSYNCF) {</div><div class='add'>+		vcap-&gt;count.vsync++;</div><div class='add'>+		if (vcap-&gt;state == DCMIPP_WAIT_FOR_BUFFER) {</div><div class='add'>+			vcap-&gt;count.underrun++;</div><div class='add'>+			goto out;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * On VSYNC, the previously set next buffer is going to become</div><div class='add'>+		 * active thanks to the shadowing mechanism of the DCMIPP. In</div><div class='add'>+		 * most of the cases, since a FRAMEEND has already come,</div><div class='add'>+		 * pointer next is NULL since active is reset during the</div><div class='add'>+		 * FRAMEEND handling. However, in case of framerate adjustment,</div><div class='add'>+		 * there are more VSYNC than FRAMEEND. Thus we recycle the</div><div class='add'>+		 * active (but not used) buffer and put it back into next.</div><div class='add'>+		 */</div><div class='add'>+		swap(vcap-&gt;active, vcap-&gt;next);</div><div class='add'>+		dcmipp_bytecap_set_next_frame_or_stop(vcap);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	spin_unlock_irq(&amp;vcap-&gt;irqlock);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t dcmipp_bytecap_irq_callback(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap =</div><div class='add'>+			container_of(arg, struct dcmipp_bytecap_device, ved);</div><div class='add'>+</div><div class='add'>+	/* Store interrupt status register */</div><div class='add'>+	vcap-&gt;cmsr2 = reg_read(vcap, DCMIPP_CMSR2) &amp; vcap-&gt;cmier;</div><div class='add'>+	vcap-&gt;count.it++;</div><div class='add'>+</div><div class='add'>+	/* Clear interrupt */</div><div class='add'>+	reg_write(vcap, DCMIPP_CMFCR, vcap-&gt;cmsr2);</div><div class='add'>+</div><div class='add'>+	return IRQ_WAKE_THREAD;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_bytecap_link_validate(struct media_link *link)</div><div class='add'>+{</div><div class='add'>+	struct media_entity *entity = link-&gt;sink-&gt;entity;</div><div class='add'>+	struct video_device *vd = media_entity_to_video_device(entity);</div><div class='add'>+	struct dcmipp_bytecap_device *vcap = container_of(vd,</div><div class='add'>+					struct dcmipp_bytecap_device, vdev);</div><div class='add'>+	struct v4l2_subdev *source_sd =</div><div class='add'>+		media_entity_to_v4l2_subdev(link-&gt;source-&gt;entity);</div><div class='add'>+	struct v4l2_subdev_format source_fmt = {</div><div class='add'>+		.which = V4L2_SUBDEV_FORMAT_ACTIVE,</div><div class='add'>+		.pad = link-&gt;source-&gt;index,</div><div class='add'>+	};</div><div class='add'>+	const struct dcmipp_bytecap_pix_map *vpix;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_call(source_sd, pad, get_fmt, NULL, &amp;source_fmt);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (source_fmt.format.width != vcap-&gt;format.width ||</div><div class='add'>+	    source_fmt.format.height != vcap-&gt;format.height) {</div><div class='add'>+		dev_err(vcap-&gt;dev, "Wrong width or height %ux%u (%ux%u expected)\n",</div><div class='add'>+			vcap-&gt;format.width, vcap-&gt;format.height,</div><div class='add'>+			source_fmt.format.width, source_fmt.format.height);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vpix = dcmipp_bytecap_pix_map_by_pixelformat(vcap-&gt;format.pixelformat);</div><div class='add'>+	if (source_fmt.format.code != vpix-&gt;code) {</div><div class='add'>+		dev_err(vcap-&gt;dev, "Wrong mbus_code 0x%x, (0x%x expected)\n",</div><div class='add'>+			vpix-&gt;code, source_fmt.format.code);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct media_entity_operations dcmipp_bytecap_entity_ops = {</div><div class='add'>+	.link_validate = dcmipp_bytecap_link_validate,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct dcmipp_ent_device *dcmipp_bytecap_ent_init(struct device *dev,</div><div class='add'>+						  const char *entity_name,</div><div class='add'>+						  struct v4l2_device *v4l2_dev,</div><div class='add'>+						  void __iomem *regs)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_bytecap_device *vcap;</div><div class='add'>+	struct video_device *vdev;</div><div class='add'>+	struct vb2_queue *q;</div><div class='add'>+	const unsigned long pad_flag = MEDIA_PAD_FL_SINK;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Allocate the dcmipp_bytecap_device struct */</div><div class='add'>+	vcap = kzalloc(sizeof(*vcap), GFP_KERNEL);</div><div class='add'>+	if (!vcap)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	/* Allocate the pads */</div><div class='add'>+	vcap-&gt;ved.pads = dcmipp_pads_init(1, &amp;pad_flag);</div><div class='add'>+	if (IS_ERR(vcap-&gt;ved.pads)) {</div><div class='add'>+		ret = PTR_ERR(vcap-&gt;ved.pads);</div><div class='add'>+		goto err_free_vcap;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize the media entity */</div><div class='add'>+	vcap-&gt;vdev.entity.name = entity_name;</div><div class='add'>+	vcap-&gt;vdev.entity.function = MEDIA_ENT_F_IO_V4L;</div><div class='add'>+	vcap-&gt;vdev.entity.ops = &amp;dcmipp_bytecap_entity_ops;</div><div class='add'>+	ret = media_entity_pads_init(&amp;vcap-&gt;vdev.entity, 1, vcap-&gt;ved.pads);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_clean_pads;</div><div class='add'>+</div><div class='add'>+	/* Initialize the lock */</div><div class='add'>+	mutex_init(&amp;vcap-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Initialize the vb2 queue */</div><div class='add'>+	q = &amp;vcap-&gt;queue;</div><div class='add'>+	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE;</div><div class='add'>+	q-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='add'>+	q-&gt;lock = &amp;vcap-&gt;lock;</div><div class='add'>+	q-&gt;drv_priv = vcap;</div><div class='add'>+	q-&gt;buf_struct_size = sizeof(struct dcmipp_buf);</div><div class='add'>+	q-&gt;ops = &amp;dcmipp_bytecap_qops;</div><div class='add'>+	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='add'>+	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='add'>+	q-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	/* DCMIPP requires 16 bytes aligned buffers */</div><div class='add'>+	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32) &amp; ~0x0f);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "Failed to set DMA mask\n");</div><div class='add'>+		goto err_mutex_destroy;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = vb2_queue_init(q);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "%s: vb2 queue init failed (err=%d)\n",</div><div class='add'>+			entity_name, ret);</div><div class='add'>+		goto err_clean_m_ent;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize buffer list and its lock */</div><div class='add'>+	INIT_LIST_HEAD(&amp;vcap-&gt;buffers);</div><div class='add'>+	spin_lock_init(&amp;vcap-&gt;irqlock);</div><div class='add'>+</div><div class='add'>+	/* Set default frame format */</div><div class='add'>+	vcap-&gt;format = fmt_default;</div><div class='add'>+</div><div class='add'>+	/* Fill the dcmipp_ent_device struct */</div><div class='add'>+	vcap-&gt;ved.ent = &amp;vcap-&gt;vdev.entity;</div><div class='add'>+	vcap-&gt;ved.handler = dcmipp_bytecap_irq_callback;</div><div class='add'>+	vcap-&gt;ved.thread_fn = dcmipp_bytecap_irq_thread;</div><div class='add'>+	vcap-&gt;dev = dev;</div><div class='add'>+	vcap-&gt;regs = regs;</div><div class='add'>+</div><div class='add'>+	/* Initialize the video_device struct */</div><div class='add'>+	vdev = &amp;vcap-&gt;vdev;</div><div class='add'>+	vdev-&gt;device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |</div><div class='add'>+			    V4L2_CAP_IO_MC;</div><div class='add'>+	vdev-&gt;release = dcmipp_bytecap_release;</div><div class='add'>+	vdev-&gt;fops = &amp;dcmipp_bytecap_fops;</div><div class='add'>+	vdev-&gt;ioctl_ops = &amp;dcmipp_bytecap_ioctl_ops;</div><div class='add'>+	vdev-&gt;lock = &amp;vcap-&gt;lock;</div><div class='add'>+	vdev-&gt;queue = q;</div><div class='add'>+	vdev-&gt;v4l2_dev = v4l2_dev;</div><div class='add'>+	strscpy(vdev-&gt;name, entity_name, sizeof(vdev-&gt;name));</div><div class='add'>+	video_set_drvdata(vdev, &amp;vcap-&gt;ved);</div><div class='add'>+</div><div class='add'>+	/* Register the video_device with the v4l2 and the media framework */</div><div class='add'>+	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dev, "%s: video register failed (err=%d)\n",</div><div class='add'>+			vcap-&gt;vdev.name, ret);</div><div class='add'>+		goto err_clean_m_ent;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return &amp;vcap-&gt;ved;</div><div class='add'>+</div><div class='add'>+err_clean_m_ent:</div><div class='add'>+	media_entity_cleanup(&amp;vcap-&gt;vdev.entity);</div><div class='add'>+err_mutex_destroy:</div><div class='add'>+	mutex_destroy(&amp;vcap-&gt;lock);</div><div class='add'>+err_clean_pads:</div><div class='add'>+	dcmipp_pads_cleanup(vcap-&gt;ved.pads);</div><div class='add'>+err_free_vcap:</div><div class='add'>+	kfree(vcap);</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c<br/>new file mode 100644<br/>index 000000000000..5a361ad6b023<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c</a></div><div class='hunk'>@@ -0,0 +1,565 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='add'>+#include &lt;linux/v4l2-mediabus.h&gt;</div><div class='add'>+#include &lt;media/v4l2-rect.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dcmipp-common.h"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_P0FCTCR	0x500</div><div class='add'>+#define DCMIPP_P0FCTCR_FRATE_MASK	GENMASK(1, 0)</div><div class='add'>+#define DCMIPP_P0SCSTR	0x504</div><div class='add'>+#define DCMIPP_P0SCSTR_HSTART_SHIFT	0</div><div class='add'>+#define DCMIPP_P0SCSTR_VSTART_SHIFT	16</div><div class='add'>+#define DCMIPP_P0SCSZR	0x508</div><div class='add'>+#define DCMIPP_P0SCSZR_ENABLE		BIT(31)</div><div class='add'>+#define DCMIPP_P0SCSZR_HSIZE_SHIFT	0</div><div class='add'>+#define DCMIPP_P0SCSZR_VSIZE_SHIFT	16</div><div class='add'>+#define DCMIPP_P0PPCR	0x5c0</div><div class='add'>+#define DCMIPP_P0PPCR_BSM_1_2		0x1</div><div class='add'>+#define DCMIPP_P0PPCR_BSM_1_4		0x2</div><div class='add'>+#define DCMIPP_P0PPCR_BSM_2_4		0x3</div><div class='add'>+#define DCMIPP_P0PPCR_BSM_MASK		GENMASK(8, 7)</div><div class='add'>+#define DCMIPP_P0PPCR_BSM_SHIFT		0x7</div><div class='add'>+#define DCMIPP_P0PPCR_LSM		BIT(10)</div><div class='add'>+#define DCMIPP_P0PPCR_OELS		BIT(11)</div><div class='add'>+</div><div class='add'>+#define IS_SINK(pad) (!(pad))</div><div class='add'>+#define IS_SRC(pad)  ((pad))</div><div class='add'>+</div><div class='add'>+struct dcmipp_byteproc_pix_map {</div><div class='add'>+	unsigned int code;</div><div class='add'>+	unsigned int bpp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define PIXMAP_MBUS_BPP(mbus, byteperpixel)		\</div><div class='add'>+	{						\</div><div class='add'>+		.code = MEDIA_BUS_FMT_##mbus,		\</div><div class='add'>+		.bpp = byteperpixel,			\</div><div class='add'>+	}</div><div class='add'>+static const struct dcmipp_byteproc_pix_map dcmipp_byteproc_pix_map_list[] = {</div><div class='add'>+	PIXMAP_MBUS_BPP(RGB565_2X8_LE, 2),</div><div class='add'>+	PIXMAP_MBUS_BPP(YUYV8_2X8, 2),</div><div class='add'>+	PIXMAP_MBUS_BPP(YVYU8_2X8, 2),</div><div class='add'>+	PIXMAP_MBUS_BPP(UYVY8_2X8, 2),</div><div class='add'>+	PIXMAP_MBUS_BPP(VYUY8_2X8, 2),</div><div class='add'>+	PIXMAP_MBUS_BPP(Y8_1X8, 1),</div><div class='add'>+	PIXMAP_MBUS_BPP(SBGGR8_1X8, 1),</div><div class='add'>+	PIXMAP_MBUS_BPP(SGBRG8_1X8, 1),</div><div class='add'>+	PIXMAP_MBUS_BPP(SGRBG8_1X8, 1),</div><div class='add'>+	PIXMAP_MBUS_BPP(SRGGB8_1X8, 1),</div><div class='add'>+	PIXMAP_MBUS_BPP(JPEG_1X8, 1),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_byteproc_pix_map *</div><div class='add'>+dcmipp_byteproc_pix_map_by_code(u32 code)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(dcmipp_byteproc_pix_map_list); i++) {</div><div class='add'>+		if (dcmipp_byteproc_pix_map_list[i].code == code)</div><div class='add'>+			return &amp;dcmipp_byteproc_pix_map_list[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_byteproc_device {</div><div class='add'>+	struct dcmipp_ent_device ved;</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	void __iomem *regs;</div><div class='add'>+	bool streaming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_mbus_framefmt fmt_default = {</div><div class='add'>+	.width = DCMIPP_FMT_WIDTH_DEFAULT,</div><div class='add'>+	.height = DCMIPP_FMT_HEIGHT_DEFAULT,</div><div class='add'>+	.code = MEDIA_BUS_FMT_RGB565_2X8_LE,</div><div class='add'>+	.field = V4L2_FIELD_NONE,</div><div class='add'>+	.colorspace = DCMIPP_COLORSPACE_DEFAULT,</div><div class='add'>+	.ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,</div><div class='add'>+	.quantization = DCMIPP_QUANTIZATION_DEFAULT,</div><div class='add'>+	.xfer_func = DCMIPP_XFER_FUNC_DEFAULT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_rect crop_min = {</div><div class='add'>+	.width = DCMIPP_FRAME_MIN_WIDTH,</div><div class='add'>+	.height = DCMIPP_FRAME_MIN_HEIGHT,</div><div class='add'>+	.top = 0,</div><div class='add'>+	.left = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcmipp_byteproc_adjust_crop(struct v4l2_rect *r,</div><div class='add'>+					struct v4l2_rect *compose)</div><div class='add'>+{</div><div class='add'>+	/* Disallow rectangles smaller than the minimal one. */</div><div class='add'>+	v4l2_rect_set_min_size(r, &amp;crop_min);</div><div class='add'>+	v4l2_rect_map_inside(r, compose);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_byteproc_adjust_compose(struct v4l2_rect *r,</div><div class='add'>+					   const struct v4l2_mbus_framefmt *fmt)</div><div class='add'>+{</div><div class='add'>+	r-&gt;top = 0;</div><div class='add'>+	r-&gt;left = 0;</div><div class='add'>+</div><div class='add'>+	/* Compose is not possible for JPEG or Bayer formats */</div><div class='add'>+	if (fmt-&gt;code == MEDIA_BUS_FMT_JPEG_1X8 ||</div><div class='add'>+	    fmt-&gt;code == MEDIA_BUS_FMT_SBGGR8_1X8 ||</div><div class='add'>+	    fmt-&gt;code == MEDIA_BUS_FMT_SGBRG8_1X8 ||</div><div class='add'>+	    fmt-&gt;code == MEDIA_BUS_FMT_SGRBG8_1X8 ||</div><div class='add'>+	    fmt-&gt;code == MEDIA_BUS_FMT_SRGGB8_1X8) {</div><div class='add'>+		r-&gt;width = fmt-&gt;width;</div><div class='add'>+		r-&gt;height = fmt-&gt;height;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Adjust height - we can only perform 1/2 decimation */</div><div class='add'>+	if (r-&gt;height &lt;= (fmt-&gt;height / 2))</div><div class='add'>+		r-&gt;height = fmt-&gt;height / 2;</div><div class='add'>+	else</div><div class='add'>+		r-&gt;height = fmt-&gt;height;</div><div class='add'>+</div><div class='add'>+	/* Adjust width /2 or /4 for 8bits formats and /2 for 16bits formats */</div><div class='add'>+	if (fmt-&gt;code == MEDIA_BUS_FMT_Y8_1X8 &amp;&amp; r-&gt;width &lt;= (fmt-&gt;width / 4))</div><div class='add'>+		r-&gt;width = fmt-&gt;width / 4;</div><div class='add'>+	else if (r-&gt;width &lt;= (fmt-&gt;width / 2))</div><div class='add'>+		r-&gt;width = fmt-&gt;width / 2;</div><div class='add'>+	else</div><div class='add'>+		r-&gt;width = fmt-&gt;width;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_byteproc_adjust_fmt(struct v4l2_mbus_framefmt *fmt)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_byteproc_pix_map *vpix;</div><div class='add'>+</div><div class='add'>+	/* Only accept code in the pix map table */</div><div class='add'>+	vpix = dcmipp_byteproc_pix_map_by_code(fmt-&gt;code);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		fmt-&gt;code = fmt_default.code;</div><div class='add'>+</div><div class='add'>+	fmt-&gt;width = clamp_t(u32, fmt-&gt;width, DCMIPP_FRAME_MIN_WIDTH,</div><div class='add'>+			     DCMIPP_FRAME_MAX_WIDTH) &amp; ~1;</div><div class='add'>+	fmt-&gt;height = clamp_t(u32, fmt-&gt;height, DCMIPP_FRAME_MIN_HEIGHT,</div><div class='add'>+			      DCMIPP_FRAME_MAX_HEIGHT) &amp; ~1;</div><div class='add'>+</div><div class='add'>+	if (fmt-&gt;field == V4L2_FIELD_ANY || fmt-&gt;field == V4L2_FIELD_ALTERNATE)</div><div class='add'>+		fmt-&gt;field = fmt_default.field;</div><div class='add'>+</div><div class='add'>+	dcmipp_colorimetry_clamp(fmt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='add'>+		struct v4l2_mbus_framefmt *mf;</div><div class='add'>+		struct v4l2_rect *r;</div><div class='add'>+</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, i);</div><div class='add'>+		*mf = fmt_default;</div><div class='add'>+</div><div class='add'>+		if (IS_SINK(i))</div><div class='add'>+			r = v4l2_subdev_state_get_compose(sd_state, i);</div><div class='add'>+		else</div><div class='add'>+			r = v4l2_subdev_state_get_crop(sd_state, i);</div><div class='add'>+</div><div class='add'>+		r-&gt;top = 0;</div><div class='add'>+		r-&gt;left = 0;</div><div class='add'>+		r-&gt;width = DCMIPP_FMT_WIDTH_DEFAULT;</div><div class='add'>+		r-&gt;height = DCMIPP_FMT_HEIGHT_DEFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dcmipp_byteproc_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+			       struct v4l2_subdev_state *sd_state,</div><div class='add'>+			       struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_byteproc_pix_map *vpix;</div><div class='add'>+	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='add'>+</div><div class='add'>+	if (IS_SINK(code-&gt;pad)) {</div><div class='add'>+		if (code-&gt;index &gt;= ARRAY_SIZE(dcmipp_byteproc_pix_map_list))</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		vpix = &amp;dcmipp_byteproc_pix_map_list[code-&gt;index];</div><div class='add'>+		code-&gt;code = vpix-&gt;code;</div><div class='add'>+	} else {</div><div class='add'>+		/* byteproc doesn't support transformation on format */</div><div class='add'>+		if (code-&gt;index &gt; 0)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		sink_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+		code-&gt;code = sink_fmt-&gt;code;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+dcmipp_byteproc_enum_frame_size(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state,</div><div class='add'>+				struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_rect *compose;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fse-&gt;min_width = DCMIPP_FRAME_MIN_WIDTH;</div><div class='add'>+	fse-&gt;min_height = DCMIPP_FRAME_MIN_HEIGHT;</div><div class='add'>+</div><div class='add'>+	if (IS_SINK(fse-&gt;pad)) {</div><div class='add'>+		fse-&gt;max_width = DCMIPP_FRAME_MAX_WIDTH;</div><div class='add'>+		fse-&gt;max_height = DCMIPP_FRAME_MAX_HEIGHT;</div><div class='add'>+	} else {</div><div class='add'>+		compose = v4l2_subdev_state_get_compose(sd_state, 0);</div><div class='add'>+		fse-&gt;max_width = compose-&gt;width;</div><div class='add'>+		fse-&gt;max_height = compose-&gt;height;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_set_fmt(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state,</div><div class='add'>+				   struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mf;</div><div class='add'>+	struct v4l2_rect *crop, *compose;</div><div class='add'>+</div><div class='add'>+	if (byteproc-&gt;streaming)</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='add'>+</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, 1);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	if (IS_SRC(fmt-&gt;pad)) {</div><div class='add'>+		fmt-&gt;format = *v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+		fmt-&gt;format.width = crop-&gt;width;</div><div class='add'>+		fmt-&gt;format.height = crop-&gt;height;</div><div class='add'>+	} else {</div><div class='add'>+		dcmipp_byteproc_adjust_fmt(&amp;fmt-&gt;format);</div><div class='add'>+		crop-&gt;top = 0;</div><div class='add'>+		crop-&gt;left = 0;</div><div class='add'>+		crop-&gt;width = fmt-&gt;format.width;</div><div class='add'>+		crop-&gt;height = fmt-&gt;format.height;</div><div class='add'>+		*compose = *crop;</div><div class='add'>+		/* Set the same format on SOURCE pad as well */</div><div class='add'>+		*v4l2_subdev_state_get_format(sd_state, 1) = fmt-&gt;format;</div><div class='add'>+	}</div><div class='add'>+	*mf = fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_get_selection(struct v4l2_subdev *sd,</div><div class='add'>+					 struct v4l2_subdev_state *sd_state,</div><div class='add'>+					 struct v4l2_subdev_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='add'>+	struct v4l2_rect *crop, *compose;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * In the HW, the decimation block is located prior to the crop hence:</div><div class='add'>+	 * Compose is done on the sink pad</div><div class='add'>+	 * Crop is done on the src pad</div><div class='add'>+	 */</div><div class='add'>+	if (IS_SINK(s-&gt;pad) &amp;&amp;</div><div class='add'>+	    (s-&gt;target == V4L2_SEL_TGT_CROP ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_CROP_BOUNDS ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_CROP_DEFAULT))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (IS_SRC(s-&gt;pad) &amp;&amp;</div><div class='add'>+	    (s-&gt;target == V4L2_SEL_TGT_COMPOSE ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_COMPOSE_BOUNDS ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_COMPOSE_DEFAULT))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, 1);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	switch (s-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		s-&gt;r = *crop;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_SEL_TGT_CROP_BOUNDS:</div><div class='add'>+	case V4L2_SEL_TGT_CROP_DEFAULT:</div><div class='add'>+		s-&gt;r = *compose;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE:</div><div class='add'>+		s-&gt;r = *compose;</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE_BOUNDS:</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE_DEFAULT:</div><div class='add'>+		s-&gt;r.top = 0;</div><div class='add'>+		s-&gt;r.left = 0;</div><div class='add'>+		s-&gt;r.width = sink_fmt-&gt;width;</div><div class='add'>+		s-&gt;r.height = sink_fmt-&gt;height;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_set_selection(struct v4l2_subdev *sd,</div><div class='add'>+					 struct v4l2_subdev_state *sd_state,</div><div class='add'>+					 struct v4l2_subdev_selection *s)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mf;</div><div class='add'>+	struct v4l2_rect *crop, *compose;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * In the HW, the decimation block is located prior to the crop hence:</div><div class='add'>+	 * Compose is done on the sink pad</div><div class='add'>+	 * Crop is done on the src pad</div><div class='add'>+	 */</div><div class='add'>+	if ((s-&gt;target == V4L2_SEL_TGT_CROP ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_CROP_BOUNDS ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_CROP_DEFAULT) &amp;&amp; IS_SINK(s-&gt;pad))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if ((s-&gt;target == V4L2_SEL_TGT_COMPOSE ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_COMPOSE_BOUNDS ||</div><div class='add'>+	     s-&gt;target == V4L2_SEL_TGT_COMPOSE_DEFAULT) &amp;&amp; IS_SRC(s-&gt;pad))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(sd_state, 1);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(sd_state, 0);</div><div class='add'>+</div><div class='add'>+	switch (s-&gt;target) {</div><div class='add'>+	case V4L2_SEL_TGT_CROP:</div><div class='add'>+		dcmipp_byteproc_adjust_crop(&amp;s-&gt;r, compose);</div><div class='add'>+</div><div class='add'>+		*crop = s-&gt;r;</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 1);</div><div class='add'>+		mf-&gt;width = s-&gt;r.width;</div><div class='add'>+		mf-&gt;height = s-&gt;r.height;</div><div class='add'>+</div><div class='add'>+		dev_dbg(byteproc-&gt;dev, "s_selection: crop %ux%u@(%u,%u)\n",</div><div class='add'>+			crop-&gt;width, crop-&gt;height, crop-&gt;left, crop-&gt;top);</div><div class='add'>+		break;</div><div class='add'>+	case V4L2_SEL_TGT_COMPOSE:</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+		dcmipp_byteproc_adjust_compose(&amp;s-&gt;r, mf);</div><div class='add'>+		*compose = s-&gt;r;</div><div class='add'>+		*crop = s-&gt;r;</div><div class='add'>+</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 1);</div><div class='add'>+		mf-&gt;width = s-&gt;r.width;</div><div class='add'>+		mf-&gt;height = s-&gt;r.height;</div><div class='add'>+</div><div class='add'>+		dev_dbg(byteproc-&gt;dev, "s_selection: compose %ux%u@(%u,%u)\n",</div><div class='add'>+			compose-&gt;width, compose-&gt;height,</div><div class='add'>+			compose-&gt;left, compose-&gt;top);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops dcmipp_byteproc_pad_ops = {</div><div class='add'>+	.enum_mbus_code		= dcmipp_byteproc_enum_mbus_code,</div><div class='add'>+	.enum_frame_size	= dcmipp_byteproc_enum_frame_size,</div><div class='add'>+	.get_fmt		= v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt		= dcmipp_byteproc_set_fmt,</div><div class='add'>+	.get_selection		= dcmipp_byteproc_get_selection,</div><div class='add'>+	.set_selection		= dcmipp_byteproc_set_selection,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_configure_scale_crop</div><div class='add'>+			(struct dcmipp_byteproc_device *byteproc)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_byteproc_pix_map *vpix;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='add'>+	u32 hprediv, vprediv;</div><div class='add'>+	struct v4l2_rect *compose, *crop;</div><div class='add'>+	u32 val = 0;</div><div class='add'>+</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(&amp;byteproc-&gt;sd);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	compose = v4l2_subdev_state_get_compose(state, 0);</div><div class='add'>+	crop = v4l2_subdev_state_get_crop(state, 1);</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='add'>+	/* find output format bpp */</div><div class='add'>+	vpix = dcmipp_byteproc_pix_map_by_code(sink_fmt-&gt;code);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* clear decimation/crop */</div><div class='add'>+	reg_clear(byteproc, DCMIPP_P0PPCR, DCMIPP_P0PPCR_BSM_MASK);</div><div class='add'>+	reg_clear(byteproc, DCMIPP_P0PPCR, DCMIPP_P0PPCR_LSM);</div><div class='add'>+	reg_write(byteproc, DCMIPP_P0SCSTR, 0);</div><div class='add'>+	reg_write(byteproc, DCMIPP_P0SCSZR, 0);</div><div class='add'>+</div><div class='add'>+	/* Ignore decimation/crop with JPEG */</div><div class='add'>+	if (vpix-&gt;code == MEDIA_BUS_FMT_JPEG_1X8)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* decimation */</div><div class='add'>+	hprediv = sink_fmt-&gt;width / compose-&gt;width;</div><div class='add'>+	if (hprediv == 4)</div><div class='add'>+		val |= DCMIPP_P0PPCR_BSM_1_4 &lt;&lt; DCMIPP_P0PPCR_BSM_SHIFT;</div><div class='add'>+	else if ((vpix-&gt;code == MEDIA_BUS_FMT_Y8_1X8) &amp;&amp; (hprediv == 2))</div><div class='add'>+		val |= DCMIPP_P0PPCR_BSM_1_2 &lt;&lt; DCMIPP_P0PPCR_BSM_SHIFT;</div><div class='add'>+	else if (hprediv == 2)</div><div class='add'>+		val |= DCMIPP_P0PPCR_BSM_2_4 &lt;&lt; DCMIPP_P0PPCR_BSM_SHIFT;</div><div class='add'>+</div><div class='add'>+	vprediv = sink_fmt-&gt;height / compose-&gt;height;</div><div class='add'>+	if (vprediv == 2)</div><div class='add'>+		val |= DCMIPP_P0PPCR_LSM | DCMIPP_P0PPCR_OELS;</div><div class='add'>+</div><div class='add'>+	/* decimate using bytes and lines skipping */</div><div class='add'>+	if (val) {</div><div class='add'>+		reg_set(byteproc, DCMIPP_P0PPCR, val);</div><div class='add'>+</div><div class='add'>+		dev_dbg(byteproc-&gt;dev, "decimate to %dx%d [prediv=%dx%d]\n",</div><div class='add'>+			compose-&gt;width, compose-&gt;height,</div><div class='add'>+			hprediv, vprediv);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(byteproc-&gt;dev, "crop to %dx%d\n", crop-&gt;width, crop-&gt;height);</div><div class='add'>+</div><div class='add'>+	/* expressed in 32-bits words on X axis, lines on Y axis */</div><div class='add'>+	reg_write(byteproc, DCMIPP_P0SCSTR,</div><div class='add'>+		  (((crop-&gt;left * vpix-&gt;bpp) / 4) &lt;&lt;</div><div class='add'>+		   DCMIPP_P0SCSTR_HSTART_SHIFT) |</div><div class='add'>+		  (crop-&gt;top &lt;&lt; DCMIPP_P0SCSTR_VSTART_SHIFT));</div><div class='add'>+	reg_write(byteproc, DCMIPP_P0SCSZR,</div><div class='add'>+		  DCMIPP_P0SCSZR_ENABLE |</div><div class='add'>+		  (((crop-&gt;width * vpix-&gt;bpp) / 4) &lt;&lt;</div><div class='add'>+		   DCMIPP_P0SCSZR_HSIZE_SHIFT) |</div><div class='add'>+		  (crop-&gt;height &lt;&lt; DCMIPP_P0SCSZR_VSIZE_SHIFT));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_byteproc_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);</div><div class='add'>+	struct v4l2_subdev *s_subdev;</div><div class='add'>+	struct media_pad *pad;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Get source subdev */</div><div class='add'>+	pad = media_pad_remote_pad_first(&amp;sd-&gt;entity.pads[0]);</div><div class='add'>+	if (!pad || !is_media_entity_v4l2_subdev(pad-&gt;entity))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	s_subdev = media_entity_to_v4l2_subdev(pad-&gt;entity);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		ret = dcmipp_byteproc_configure_scale_crop(byteproc);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(byteproc-&gt;dev,</div><div class='add'>+				"failed to start source subdev streaming (%d)\n",</div><div class='add'>+				ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(byteproc-&gt;dev,</div><div class='add'>+				"failed to stop source subdev streaming (%d)\n",</div><div class='add'>+				ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	byteproc-&gt;streaming = enable;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops dcmipp_byteproc_video_ops = {</div><div class='add'>+	.s_stream = dcmipp_byteproc_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops dcmipp_byteproc_ops = {</div><div class='add'>+	.pad = &amp;dcmipp_byteproc_pad_ops,</div><div class='add'>+	.video = &amp;dcmipp_byteproc_video_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcmipp_byteproc_release(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);</div><div class='add'>+</div><div class='add'>+	kfree(byteproc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops dcmipp_byteproc_int_ops = {</div><div class='add'>+	.init_state = dcmipp_byteproc_init_state,</div><div class='add'>+	.release = dcmipp_byteproc_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcmipp_byteproc_ent_release(struct dcmipp_ent_device *ved)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc =</div><div class='add'>+			container_of(ved, struct dcmipp_byteproc_device, ved);</div><div class='add'>+</div><div class='add'>+	dcmipp_ent_sd_unregister(ved, &amp;byteproc-&gt;sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_ent_device *</div><div class='add'>+dcmipp_byteproc_ent_init(struct device *dev, const char *entity_name,</div><div class='add'>+			 struct v4l2_device *v4l2_dev, void __iomem *regs)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_byteproc_device *byteproc;</div><div class='add'>+	const unsigned long pads_flag[] = {</div><div class='add'>+		MEDIA_PAD_FL_SINK, MEDIA_PAD_FL_SOURCE,</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Allocate the byteproc struct */</div><div class='add'>+	byteproc = kzalloc(sizeof(*byteproc), GFP_KERNEL);</div><div class='add'>+	if (!byteproc)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	byteproc-&gt;regs = regs;</div><div class='add'>+</div><div class='add'>+	/* Initialize ved and sd */</div><div class='add'>+	ret = dcmipp_ent_sd_register(&amp;byteproc-&gt;ved, &amp;byteproc-&gt;sd,</div><div class='add'>+				     v4l2_dev, entity_name,</div><div class='add'>+				     MEDIA_ENT_F_PROC_VIDEO_SCALER,</div><div class='add'>+				     ARRAY_SIZE(pads_flag), pads_flag,</div><div class='add'>+				     &amp;dcmipp_byteproc_int_ops,</div><div class='add'>+				     &amp;dcmipp_byteproc_ops,</div><div class='add'>+				     NULL, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		kfree(byteproc);</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	byteproc-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	return &amp;byteproc-&gt;ved;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c<br/>new file mode 100644<br/>index 000000000000..562933e08d62<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.c</a></div><div class='hunk'>@@ -0,0 +1,111 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dcmipp-common.h"</div><div class='add'>+</div><div class='add'>+/* Helper function to allocate and initialize pads */</div><div class='add'>+struct media_pad *dcmipp_pads_init(u16 num_pads, const unsigned long *pads_flags)</div><div class='add'>+{</div><div class='add'>+	struct media_pad *pads;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* Allocate memory for the pads */</div><div class='add'>+	pads = kcalloc(num_pads, sizeof(*pads), GFP_KERNEL);</div><div class='add'>+	if (!pads)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	/* Initialize the pads */</div><div class='add'>+	for (i = 0; i &lt; num_pads; i++) {</div><div class='add'>+		pads[i].index = i;</div><div class='add'>+		pads[i].flags = pads_flags[i];</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return pads;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct media_entity_operations dcmipp_entity_ops = {</div><div class='add'>+	.link_validate = v4l2_subdev_link_validate,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int dcmipp_ent_sd_register(struct dcmipp_ent_device *ved,</div><div class='add'>+			   struct v4l2_subdev *sd,</div><div class='add'>+			   struct v4l2_device *v4l2_dev,</div><div class='add'>+			   const char *const name,</div><div class='add'>+			   u32 function,</div><div class='add'>+			   u16 num_pads,</div><div class='add'>+			   const unsigned long *pads_flag,</div><div class='add'>+			   const struct v4l2_subdev_internal_ops *sd_int_ops,</div><div class='add'>+			   const struct v4l2_subdev_ops *sd_ops,</div><div class='add'>+			   irq_handler_t handler,</div><div class='add'>+			   irq_handler_t thread_fn)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Allocate the pads. Should be released from the sd_int_op release */</div><div class='add'>+	ved-&gt;pads = dcmipp_pads_init(num_pads, pads_flag);</div><div class='add'>+	if (IS_ERR(ved-&gt;pads))</div><div class='add'>+		return PTR_ERR(ved-&gt;pads);</div><div class='add'>+</div><div class='add'>+	/* Fill the dcmipp_ent_device struct */</div><div class='add'>+	ved-&gt;ent = &amp;sd-&gt;entity;</div><div class='add'>+</div><div class='add'>+	/* Initialize the subdev */</div><div class='add'>+	v4l2_subdev_init(sd, sd_ops);</div><div class='add'>+	sd-&gt;internal_ops = sd_int_ops;</div><div class='add'>+	sd-&gt;entity.function = function;</div><div class='add'>+	sd-&gt;entity.ops = &amp;dcmipp_entity_ops;</div><div class='add'>+	sd-&gt;owner = THIS_MODULE;</div><div class='add'>+	strscpy(sd-&gt;name, name, sizeof(sd-&gt;name));</div><div class='add'>+	v4l2_set_subdevdata(sd, ved);</div><div class='add'>+</div><div class='add'>+	/* Expose this subdev to user space */</div><div class='add'>+	sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='add'>+	if (sd-&gt;ctrl_handler)</div><div class='add'>+		sd-&gt;flags |= V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='add'>+</div><div class='add'>+	/* Initialize the media entity */</div><div class='add'>+	ret = media_entity_pads_init(&amp;sd-&gt;entity, num_pads, ved-&gt;pads);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_clean_pads;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_subdev_init_finalize(sd);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err_clean_m_ent;</div><div class='add'>+</div><div class='add'>+	/* Register the subdev with the v4l2 and the media framework */</div><div class='add'>+	ret = v4l2_device_register_subdev(v4l2_dev, sd);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(v4l2_dev-&gt;dev,</div><div class='add'>+			"%s: subdev register failed (err=%d)\n",</div><div class='add'>+			name, ret);</div><div class='add'>+		goto err_clean_m_ent;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ved-&gt;handler = handler;</div><div class='add'>+	ved-&gt;thread_fn = thread_fn;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_clean_m_ent:</div><div class='add'>+	media_entity_cleanup(&amp;sd-&gt;entity);</div><div class='add'>+err_clean_pads:</div><div class='add'>+	dcmipp_pads_cleanup(ved-&gt;pads);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void</div><div class='add'>+dcmipp_ent_sd_unregister(struct dcmipp_ent_device *ved, struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	media_entity_cleanup(ved-&gt;ent);</div><div class='add'>+	v4l2_device_unregister_subdev(sd);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h<br/>new file mode 100644<br/>index 000000000000..7a7cf43baf24<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h</a></div><div class='hunk'>@@ -0,0 +1,217 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-or-later */</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _DCMIPP_COMMON_H_</div><div class='add'>+#define _DCMIPP_COMMON_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;media/media-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+</div><div class='add'>+#define DCMIPP_PDEV_NAME "dcmipp"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_FRAME_MAX_WIDTH 4096</div><div class='add'>+#define DCMIPP_FRAME_MAX_HEIGHT 2160</div><div class='add'>+#define DCMIPP_FRAME_MIN_WIDTH 16</div><div class='add'>+#define DCMIPP_FRAME_MIN_HEIGHT 16</div><div class='add'>+</div><div class='add'>+#define DCMIPP_FMT_WIDTH_DEFAULT  640</div><div class='add'>+#define DCMIPP_FMT_HEIGHT_DEFAULT 480</div><div class='add'>+</div><div class='add'>+#define DCMIPP_COLORSPACE_DEFAULT	V4L2_COLORSPACE_REC709</div><div class='add'>+#define DCMIPP_YCBCR_ENC_DEFAULT	V4L2_YCBCR_ENC_DEFAULT</div><div class='add'>+#define DCMIPP_QUANTIZATION_DEFAULT	V4L2_QUANTIZATION_DEFAULT</div><div class='add'>+#define DCMIPP_XFER_FUNC_DEFAULT	V4L2_XFER_FUNC_DEFAULT</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcmipp_colorimetry_clamp() - Adjust colorimetry parameters</div><div class='add'>+ *</div><div class='add'>+ * @fmt:		the pointer to struct v4l2_pix_format or</div><div class='add'>+ *			struct v4l2_mbus_framefmt</div><div class='add'>+ *</div><div class='add'>+ * Entities must check if colorimetry given by the userspace is valid, if not</div><div class='add'>+ * then set them as DEFAULT</div><div class='add'>+ */</div><div class='add'>+#define dcmipp_colorimetry_clamp(fmt)					\</div><div class='add'>+do {									\</div><div class='add'>+	if ((fmt)-&gt;colorspace == V4L2_COLORSPACE_DEFAULT ||		\</div><div class='add'>+	    (fmt)-&gt;colorspace &gt; V4L2_COLORSPACE_DCI_P3) {		\</div><div class='add'>+		(fmt)-&gt;colorspace = DCMIPP_COLORSPACE_DEFAULT;		\</div><div class='add'>+		(fmt)-&gt;ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT;		\</div><div class='add'>+		(fmt)-&gt;quantization = DCMIPP_QUANTIZATION_DEFAULT;	\</div><div class='add'>+		(fmt)-&gt;xfer_func = DCMIPP_XFER_FUNC_DEFAULT;		\</div><div class='add'>+	}								\</div><div class='add'>+	if ((fmt)-&gt;ycbcr_enc &gt; V4L2_YCBCR_ENC_SMPTE240M)		\</div><div class='add'>+		(fmt)-&gt;ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT;		\</div><div class='add'>+	if ((fmt)-&gt;quantization &gt; V4L2_QUANTIZATION_LIM_RANGE)		\</div><div class='add'>+		(fmt)-&gt;quantization = DCMIPP_QUANTIZATION_DEFAULT;	\</div><div class='add'>+	if ((fmt)-&gt;xfer_func &gt; V4L2_XFER_FUNC_SMPTE2084)		\</div><div class='add'>+		(fmt)-&gt;xfer_func = DCMIPP_XFER_FUNC_DEFAULT;		\</div><div class='add'>+} while (0)</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct dcmipp_ent_device - core struct that represents a node in the topology</div><div class='add'>+ *</div><div class='add'>+ * @ent:		the pointer to struct media_entity for the node</div><div class='add'>+ * @pads:		the list of pads of the node</div><div class='add'>+ * @bus:		struct v4l2_mbus_config_parallel describing input bus</div><div class='add'>+ * @bus_type:		type of input bus (parallel or BT656)</div><div class='add'>+ * @handler:		irq handler dedicated to the subdev</div><div class='add'>+ * @handler_ret:	value returned by the irq handler</div><div class='add'>+ * @thread_fn:		threaded irq handler</div><div class='add'>+ *</div><div class='add'>+ * The DCMIPP provides a single IRQ line and a IRQ status registers for all</div><div class='add'>+ * subdevs, hence once the main irq handler (registered at probe time) is</div><div class='add'>+ * called, it will chain calls to the irq handler of each the subdevs of the</div><div class='add'>+ * pipelines, using the handler/handler_ret/thread_fn variables.</div><div class='add'>+ *</div><div class='add'>+ * Each node of the topology must create a dcmipp_ent_device struct.</div><div class='add'>+ * Depending on the node it will be of an instance of v4l2_subdev or</div><div class='add'>+ * video_device struct where both contains a struct media_entity.</div><div class='add'>+ * Those structures should embedded the dcmipp_ent_device struct through</div><div class='add'>+ * v4l2_set_subdevdata() and video_set_drvdata() respectivaly, allowing the</div><div class='add'>+ * dcmipp_ent_device struct to be retrieved from the corresponding struct</div><div class='add'>+ * media_entity</div><div class='add'>+ */</div><div class='add'>+struct dcmipp_ent_device {</div><div class='add'>+	struct media_entity *ent;</div><div class='add'>+	struct media_pad *pads;</div><div class='add'>+</div><div class='add'>+	/* Parallel input device */</div><div class='add'>+	struct v4l2_mbus_config_parallel bus;</div><div class='add'>+	enum v4l2_mbus_type bus_type;</div><div class='add'>+	irq_handler_t handler;</div><div class='add'>+	irqreturn_t handler_ret;</div><div class='add'>+	irq_handler_t thread_fn;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcmipp_pads_init - initialize pads</div><div class='add'>+ *</div><div class='add'>+ * @num_pads:	number of pads to initialize</div><div class='add'>+ * @pads_flags:	flags to use in each pad</div><div class='add'>+ *</div><div class='add'>+ * Helper functions to allocate/initialize pads</div><div class='add'>+ */</div><div class='add'>+struct media_pad *dcmipp_pads_init(u16 num_pads,</div><div class='add'>+				   const unsigned long *pads_flags);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcmipp_pads_cleanup - free pads</div><div class='add'>+ *</div><div class='add'>+ * @pads: pointer to the pads</div><div class='add'>+ *</div><div class='add'>+ * Helper function to free the pads initialized with dcmipp_pads_init</div><div class='add'>+ */</div><div class='add'>+static inline void dcmipp_pads_cleanup(struct media_pad *pads)</div><div class='add'>+{</div><div class='add'>+	kfree(pads);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcmipp_ent_sd_register - initialize and register a subdev node</div><div class='add'>+ *</div><div class='add'>+ * @ved:	the dcmipp_ent_device struct to be initialize</div><div class='add'>+ * @sd:		the v4l2_subdev struct to be initialize and registered</div><div class='add'>+ * @v4l2_dev:	the v4l2 device to register the v4l2_subdev</div><div class='add'>+ * @name:	name of the sub-device. Please notice that the name must be</div><div class='add'>+ *		unique.</div><div class='add'>+ * @function:	media entity function defined by MEDIA_ENT_F_* macros</div><div class='add'>+ * @num_pads:	number of pads to initialize</div><div class='add'>+ * @pads_flag:	flags to use in each pad</div><div class='add'>+ * @sd_int_ops:	pointer to &amp;struct v4l2_subdev_internal_ops</div><div class='add'>+ * @sd_ops:	pointer to &amp;struct v4l2_subdev_ops.</div><div class='add'>+ * @handler:	func pointer of the irq handler</div><div class='add'>+ * @thread_fn:	func pointer of the threaded irq handler</div><div class='add'>+ *</div><div class='add'>+ * Helper function initialize and register the struct dcmipp_ent_device and</div><div class='add'>+ * struct v4l2_subdev which represents a subdev node in the topology</div><div class='add'>+ */</div><div class='add'>+int dcmipp_ent_sd_register(struct dcmipp_ent_device *ved,</div><div class='add'>+			   struct v4l2_subdev *sd,</div><div class='add'>+			   struct v4l2_device *v4l2_dev,</div><div class='add'>+			   const char *const name,</div><div class='add'>+			   u32 function,</div><div class='add'>+			   u16 num_pads,</div><div class='add'>+			   const unsigned long *pads_flag,</div><div class='add'>+			   const struct v4l2_subdev_internal_ops *sd_int_ops,</div><div class='add'>+			   const struct v4l2_subdev_ops *sd_ops,</div><div class='add'>+			   irq_handler_t handler,</div><div class='add'>+			   irq_handler_t thread_fn);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * dcmipp_ent_sd_unregister - cleanup and unregister a subdev node</div><div class='add'>+ *</div><div class='add'>+ * @ved:	the dcmipp_ent_device struct to be cleaned up</div><div class='add'>+ * @sd:		the v4l2_subdev struct to be unregistered</div><div class='add'>+ *</div><div class='add'>+ * Helper function cleanup and unregister the struct dcmipp_ent_device and</div><div class='add'>+ * struct v4l2_subdev which represents a subdev node in the topology</div><div class='add'>+ */</div><div class='add'>+void dcmipp_ent_sd_unregister(struct dcmipp_ent_device *ved,</div><div class='add'>+			      struct v4l2_subdev *sd);</div><div class='add'>+</div><div class='add'>+#define reg_write(device, reg, val) \</div><div class='add'>+	(__reg_write((device)-&gt;dev, (device)-&gt;regs, (reg), (val)))</div><div class='add'>+#define reg_read(device, reg) \</div><div class='add'>+	(__reg_read((device)-&gt;dev, (device)-&gt;regs, (reg)))</div><div class='add'>+#define reg_set(device, reg, mask) \</div><div class='add'>+	(__reg_set((device)-&gt;dev, (device)-&gt;regs, (reg), (mask)))</div><div class='add'>+#define reg_clear(device, reg, mask) \</div><div class='add'>+	(__reg_clear((device)-&gt;dev, (device)-&gt;regs, (reg), (mask)))</div><div class='add'>+</div><div class='add'>+static inline u32 __reg_read(struct device *dev, void __iomem *base, u32 reg)</div><div class='add'>+{</div><div class='add'>+	u32 val = readl_relaxed(base + reg);</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "RD 0x%x %#10.8x\n", reg, val);</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __reg_write(struct device *dev, void __iomem *base, u32 reg,</div><div class='add'>+			       u32 val)</div><div class='add'>+{</div><div class='add'>+	dev_dbg(dev, "WR 0x%x %#10.8x\n", reg, val);</div><div class='add'>+	writel_relaxed(val, base + reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __reg_set(struct device *dev, void __iomem *base, u32 reg,</div><div class='add'>+			     u32 mask)</div><div class='add'>+{</div><div class='add'>+	dev_dbg(dev, "SET 0x%x %#10.8x\n", reg, mask);</div><div class='add'>+	__reg_write(dev, base, reg, readl_relaxed(base + reg) | mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void __reg_clear(struct device *dev, void __iomem *base, u32 reg,</div><div class='add'>+			       u32 mask)</div><div class='add'>+{</div><div class='add'>+	dev_dbg(dev, "CLR 0x%x %#10.8x\n", reg, mask);</div><div class='add'>+	__reg_write(dev, base, reg, readl_relaxed(base + reg) &amp; ~mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* DCMIPP subdev init / release entry points */</div><div class='add'>+struct dcmipp_ent_device *dcmipp_par_ent_init(struct device *dev,</div><div class='add'>+					      const char *entity_name,</div><div class='add'>+					      struct v4l2_device *v4l2_dev,</div><div class='add'>+					      void __iomem *regs);</div><div class='add'>+void dcmipp_par_ent_release(struct dcmipp_ent_device *ved);</div><div class='add'>+struct dcmipp_ent_device *</div><div class='add'>+dcmipp_byteproc_ent_init(struct device *dev, const char *entity_name,</div><div class='add'>+			 struct v4l2_device *v4l2_dev, void __iomem *regs);</div><div class='add'>+void dcmipp_byteproc_ent_release(struct dcmipp_ent_device *ved);</div><div class='add'>+struct dcmipp_ent_device *dcmipp_bytecap_ent_init(struct device *dev,</div><div class='add'>+						  const char *entity_name,</div><div class='add'>+						  struct v4l2_device *v4l2_dev,</div><div class='add'>+						  void __iomem *regs);</div><div class='add'>+void dcmipp_bytecap_ent_release(struct dcmipp_ent_device *ved);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c<br/>new file mode 100644<br/>index 000000000000..32c6619be9a2<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c</a></div><div class='hunk'>@@ -0,0 +1,604 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pinctrl/consumer.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='add'>+#include &lt;linux/reset.h&gt;</div><div class='add'>+#include &lt;media/media-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-device.h&gt;</div><div class='add'>+#include &lt;media/v4l2-fwnode.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dcmipp-common.h"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_MDEV_MODEL_NAME "DCMIPP MDEV"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_ENT_LINK(src, srcpad, sink, sinkpad, link_flags) {	\</div><div class='add'>+	.src_ent = src,						\</div><div class='add'>+	.src_pad = srcpad,					\</div><div class='add'>+	.sink_ent = sink,					\</div><div class='add'>+	.sink_pad = sinkpad,					\</div><div class='add'>+	.flags = link_flags,					\</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_device {</div><div class='add'>+	/* The platform device */</div><div class='add'>+	struct platform_device		pdev;</div><div class='add'>+	struct device			*dev;</div><div class='add'>+</div><div class='add'>+	/* Hardware resources */</div><div class='add'>+	void __iomem			*regs;</div><div class='add'>+	struct clk			*kclk;</div><div class='add'>+</div><div class='add'>+	/* The pipeline configuration */</div><div class='add'>+	const struct dcmipp_pipeline_config	*pipe_cfg;</div><div class='add'>+</div><div class='add'>+	/* The Associated media_device parent */</div><div class='add'>+	struct media_device		mdev;</div><div class='add'>+</div><div class='add'>+	/* Internal v4l2 parent device*/</div><div class='add'>+	struct v4l2_device		v4l2_dev;</div><div class='add'>+</div><div class='add'>+	/* Entities */</div><div class='add'>+	struct dcmipp_ent_device	**entity;</div><div class='add'>+</div><div class='add'>+	struct v4l2_async_notifier	notifier;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline struct dcmipp_device *</div><div class='add'>+notifier_to_dcmipp(struct v4l2_async_notifier *n)</div><div class='add'>+{</div><div class='add'>+	return container_of(n, struct dcmipp_device, notifier);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Structure which describes individual configuration for each entity */</div><div class='add'>+struct dcmipp_ent_config {</div><div class='add'>+	const char *name;</div><div class='add'>+	struct dcmipp_ent_device *(*init)</div><div class='add'>+		(struct device *dev, const char *entity_name,</div><div class='add'>+		 struct v4l2_device *v4l2_dev, void __iomem *regs);</div><div class='add'>+	void (*release)(struct dcmipp_ent_device *ved);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Structure which describes links between entities */</div><div class='add'>+struct dcmipp_ent_link {</div><div class='add'>+	unsigned int src_ent;</div><div class='add'>+	u16 src_pad;</div><div class='add'>+	unsigned int sink_ent;</div><div class='add'>+	u16 sink_pad;</div><div class='add'>+	u32 flags;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Structure which describes the whole topology */</div><div class='add'>+struct dcmipp_pipeline_config {</div><div class='add'>+	const struct dcmipp_ent_config *ents;</div><div class='add'>+	size_t num_ents;</div><div class='add'>+	const struct dcmipp_ent_link *links;</div><div class='add'>+	size_t num_links;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* --------------------------------------------------------------------------</div><div class='add'>+ * Topology Configuration</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_ent_config stm32mp13_ent_config[] = {</div><div class='add'>+	{</div><div class='add'>+		.name = "dcmipp_parallel",</div><div class='add'>+		.init = dcmipp_par_ent_init,</div><div class='add'>+		.release = dcmipp_par_ent_release,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "dcmipp_dump_postproc",</div><div class='add'>+		.init = dcmipp_byteproc_ent_init,</div><div class='add'>+		.release = dcmipp_byteproc_ent_release,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.name = "dcmipp_dump_capture",</div><div class='add'>+		.init = dcmipp_bytecap_ent_init,</div><div class='add'>+		.release = dcmipp_bytecap_ent_release,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ID_PARALLEL 0</div><div class='add'>+#define ID_DUMP_BYTEPROC 1</div><div class='add'>+#define ID_DUMP_CAPTURE 2</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_ent_link stm32mp13_ent_links[] = {</div><div class='add'>+	DCMIPP_ENT_LINK(ID_PARALLEL,      1, ID_DUMP_BYTEPROC, 0,</div><div class='add'>+			MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),</div><div class='add'>+	DCMIPP_ENT_LINK(ID_DUMP_BYTEPROC, 1, ID_DUMP_CAPTURE,  0,</div><div class='add'>+			MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct dcmipp_pipeline_config stm32mp13_pipe_cfg = {</div><div class='add'>+	.ents		= stm32mp13_ent_config,</div><div class='add'>+	.num_ents	= ARRAY_SIZE(stm32mp13_ent_config),</div><div class='add'>+	.links		= stm32mp13_ent_links,</div><div class='add'>+	.num_links	= ARRAY_SIZE(stm32mp13_ent_links)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define LINK_FLAG_TO_STR(f) ((f) == 0 ? "" :\</div><div class='add'>+			     (f) == MEDIA_LNK_FL_ENABLED ? "ENABLED" :\</div><div class='add'>+			     (f) == MEDIA_LNK_FL_IMMUTABLE ? "IMMUTABLE" :\</div><div class='add'>+			     (f) == (MEDIA_LNK_FL_ENABLED |\</div><div class='add'>+				     MEDIA_LNK_FL_IMMUTABLE) ?\</div><div class='add'>+					"ENABLED, IMMUTABLE" :\</div><div class='add'>+			     "UNKNOWN")</div><div class='add'>+</div><div class='add'>+static int dcmipp_create_links(struct dcmipp_device *dcmipp)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Initialize the links between entities */</div><div class='add'>+	for (i = 0; i &lt; dcmipp-&gt;pipe_cfg-&gt;num_links; i++) {</div><div class='add'>+		const struct dcmipp_ent_link *link =</div><div class='add'>+			&amp;dcmipp-&gt;pipe_cfg-&gt;links[i];</div><div class='add'>+		struct dcmipp_ent_device *ved_src =</div><div class='add'>+			dcmipp-&gt;entity[link-&gt;src_ent];</div><div class='add'>+		struct dcmipp_ent_device *ved_sink =</div><div class='add'>+			dcmipp-&gt;entity[link-&gt;sink_ent];</div><div class='add'>+</div><div class='add'>+		dev_dbg(dcmipp-&gt;dev, "Create link \"%s\":%d -&gt; %d:\"%s\" [%s]\n",</div><div class='add'>+			dcmipp-&gt;pipe_cfg-&gt;ents[link-&gt;src_ent].name,</div><div class='add'>+			link-&gt;src_pad, link-&gt;sink_pad,</div><div class='add'>+			dcmipp-&gt;pipe_cfg-&gt;ents[link-&gt;sink_ent].name,</div><div class='add'>+			LINK_FLAG_TO_STR(link-&gt;flags));</div><div class='add'>+</div><div class='add'>+		ret = media_create_pad_link(ved_src-&gt;ent, link-&gt;src_pad,</div><div class='add'>+					    ved_sink-&gt;ent, link-&gt;sink_pad,</div><div class='add'>+					    link-&gt;flags);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_graph_init(struct dcmipp_device *dcmipp);</div><div class='add'>+</div><div class='add'>+static int dcmipp_create_subdevs(struct dcmipp_device *dcmipp)</div><div class='add'>+{</div><div class='add'>+	int ret, i;</div><div class='add'>+</div><div class='add'>+	/* Call all subdev inits */</div><div class='add'>+	for (i = 0; i &lt; dcmipp-&gt;pipe_cfg-&gt;num_ents; i++) {</div><div class='add'>+		const char *name = dcmipp-&gt;pipe_cfg-&gt;ents[i].name;</div><div class='add'>+</div><div class='add'>+		dev_dbg(dcmipp-&gt;dev, "add subdev %s\n", name);</div><div class='add'>+		dcmipp-&gt;entity[i] =</div><div class='add'>+			dcmipp-&gt;pipe_cfg-&gt;ents[i].init(dcmipp-&gt;dev, name,</div><div class='add'>+						       &amp;dcmipp-&gt;v4l2_dev,</div><div class='add'>+						       dcmipp-&gt;regs);</div><div class='add'>+		if (IS_ERR(dcmipp-&gt;entity[i])) {</div><div class='add'>+			dev_err(dcmipp-&gt;dev, "failed to init subdev %s\n",</div><div class='add'>+				name);</div><div class='add'>+			ret = PTR_ERR(dcmipp-&gt;entity[i]);</div><div class='add'>+			goto err_init_entity;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Initialize links */</div><div class='add'>+	ret = dcmipp_create_links(dcmipp);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_init_entity;</div><div class='add'>+</div><div class='add'>+	ret = dcmipp_graph_init(dcmipp);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto err_init_entity;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_init_entity:</div><div class='add'>+	while (i &gt; 0)</div><div class='add'>+		dcmipp-&gt;pipe_cfg-&gt;ents[i - 1].release(dcmipp-&gt;entity[i - 1]);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id dcmipp_of_match[] = {</div><div class='add'>+	{ .compatible = "st,stm32mp13-dcmipp", .data = &amp;stm32mp13_pipe_cfg },</div><div class='add'>+	{ /* end node */ },</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, dcmipp_of_match);</div><div class='add'>+</div><div class='add'>+static irqreturn_t dcmipp_irq_thread(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = arg;</div><div class='add'>+	struct dcmipp_ent_device *ved;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* Call irq thread of each entities of pipeline */</div><div class='add'>+	for (i = 0; i &lt; dcmipp-&gt;pipe_cfg-&gt;num_ents; i++) {</div><div class='add'>+		ved = dcmipp-&gt;entity[i];</div><div class='add'>+		if (ved-&gt;thread_fn &amp;&amp; ved-&gt;handler_ret == IRQ_WAKE_THREAD)</div><div class='add'>+			ved-&gt;thread_fn(irq, ved);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t dcmipp_irq_callback(int irq, void *arg)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = arg;</div><div class='add'>+	struct dcmipp_ent_device *ved;</div><div class='add'>+	irqreturn_t ret = IRQ_HANDLED;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* Call irq handler of each entities of pipeline */</div><div class='add'>+	for (i = 0; i &lt; dcmipp-&gt;pipe_cfg-&gt;num_ents; i++) {</div><div class='add'>+		ved = dcmipp-&gt;entity[i];</div><div class='add'>+		if (ved-&gt;handler)</div><div class='add'>+			ved-&gt;handler_ret = ved-&gt;handler(irq, ved);</div><div class='add'>+		else if (ved-&gt;thread_fn)</div><div class='add'>+			ved-&gt;handler_ret = IRQ_WAKE_THREAD;</div><div class='add'>+		else</div><div class='add'>+			ved-&gt;handler_ret = IRQ_HANDLED;</div><div class='add'>+		if (ved-&gt;handler_ret != IRQ_HANDLED)</div><div class='add'>+			ret = ved-&gt;handler_ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_graph_notify_bound(struct v4l2_async_notifier *notifier,</div><div class='add'>+				     struct v4l2_subdev *subdev,</div><div class='add'>+				     struct v4l2_async_connection *asd)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = notifier_to_dcmipp(notifier);</div><div class='add'>+	unsigned int ret;</div><div class='add'>+	int src_pad;</div><div class='add'>+	struct dcmipp_ent_device *sink;</div><div class='add'>+	struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_PARALLEL };</div><div class='add'>+	struct fwnode_handle *ep;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dcmipp-&gt;dev, "Subdev \"%s\" bound\n", subdev-&gt;name);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Link this sub-device to DCMIPP, it could be</div><div class='add'>+	 * a parallel camera sensor or a CSI-2 to parallel bridge</div><div class='add'>+	 */</div><div class='add'>+	src_pad = media_entity_get_fwnode_pad(&amp;subdev-&gt;entity,</div><div class='add'>+					      subdev-&gt;fwnode,</div><div class='add'>+					      MEDIA_PAD_FL_SOURCE);</div><div class='add'>+</div><div class='add'>+	/* Get bus characteristics from devicetree */</div><div class='add'>+	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dcmipp-&gt;dev), 0, 0,</div><div class='add'>+					     FWNODE_GRAPH_ENDPOINT_NEXT);</div><div class='add'>+	if (!ep) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Could not find the endpoint\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Check for parallel bus-type first, then bt656 */</div><div class='add'>+	ret = v4l2_fwnode_endpoint_parse(ep, &amp;vep);</div><div class='add'>+	if (ret) {</div><div class='add'>+		vep.bus_type = V4L2_MBUS_BT656;</div><div class='add'>+		ret = v4l2_fwnode_endpoint_parse(ep, &amp;vep);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(dcmipp-&gt;dev, "Could not parse the endpoint\n");</div><div class='add'>+			fwnode_handle_put(ep);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fwnode_handle_put(ep);</div><div class='add'>+</div><div class='add'>+	if (vep.bus.parallel.bus_width == 0) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Invalid parallel interface bus-width\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Only 8 bits bus width supported with BT656 bus */</div><div class='add'>+	if (vep.bus_type == V4L2_MBUS_BT656 &amp;&amp;</div><div class='add'>+	    vep.bus.parallel.bus_width != 8) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "BT656 bus conflicts with %u bits bus width (8 bits required)\n",</div><div class='add'>+			vep.bus.parallel.bus_width);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Parallel input device detected, connect it to parallel subdev */</div><div class='add'>+	sink = dcmipp-&gt;entity[ID_PARALLEL];</div><div class='add'>+	sink-&gt;bus.flags = vep.bus.parallel.flags;</div><div class='add'>+	sink-&gt;bus.bus_width = vep.bus.parallel.bus_width;</div><div class='add'>+	sink-&gt;bus.data_shift = vep.bus.parallel.data_shift;</div><div class='add'>+	sink-&gt;bus_type = vep.bus_type;</div><div class='add'>+	ret = media_create_pad_link(&amp;subdev-&gt;entity, src_pad, sink-&gt;ent, 0,</div><div class='add'>+				    MEDIA_LNK_FL_IMMUTABLE |</div><div class='add'>+				    MEDIA_LNK_FL_ENABLED);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Failed to create media pad link with subdev \"%s\"\n",</div><div class='add'>+			subdev-&gt;name);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dcmipp-&gt;dev, "DCMIPP is now linked to \"%s\"\n", subdev-&gt;name);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_graph_notify_unbind(struct v4l2_async_notifier *notifier,</div><div class='add'>+				       struct v4l2_subdev *sd,</div><div class='add'>+				       struct v4l2_async_connection *asd)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = notifier_to_dcmipp(notifier);</div><div class='add'>+</div><div class='add'>+	dev_dbg(dcmipp-&gt;dev, "Removing %s\n", sd-&gt;name);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_graph_notify_complete(struct v4l2_async_notifier *notifier)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = notifier_to_dcmipp(notifier);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Register the media device */</div><div class='add'>+	ret = media_device_register(&amp;dcmipp-&gt;mdev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dcmipp-&gt;mdev.dev,</div><div class='add'>+			"media device register failed (err=%d)\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Expose all subdev's nodes*/</div><div class='add'>+	ret = v4l2_device_register_subdev_nodes(&amp;dcmipp-&gt;v4l2_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(dcmipp-&gt;mdev.dev,</div><div class='add'>+			"dcmipp subdev nodes registration failed (err=%d)\n",</div><div class='add'>+			ret);</div><div class='add'>+		media_device_unregister(&amp;dcmipp-&gt;mdev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev_dbg(dcmipp-&gt;dev, "Notify complete !\n");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_async_notifier_operations dcmipp_graph_notify_ops = {</div><div class='add'>+	.bound = dcmipp_graph_notify_bound,</div><div class='add'>+	.unbind = dcmipp_graph_notify_unbind,</div><div class='add'>+	.complete = dcmipp_graph_notify_complete,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_graph_init(struct dcmipp_device *dcmipp)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_async_connection *asd;</div><div class='add'>+	struct fwnode_handle *ep;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dcmipp-&gt;dev), 0, 0,</div><div class='add'>+					     FWNODE_GRAPH_ENDPOINT_NEXT);</div><div class='add'>+	if (!ep) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Failed to get next endpoint\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	v4l2_async_nf_init(&amp;dcmipp-&gt;notifier, &amp;dcmipp-&gt;v4l2_dev);</div><div class='add'>+</div><div class='add'>+	asd = v4l2_async_nf_add_fwnode_remote(&amp;dcmipp-&gt;notifier, ep,</div><div class='add'>+					      struct v4l2_async_connection);</div><div class='add'>+</div><div class='add'>+	fwnode_handle_put(ep);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(asd)) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Failed to add fwnode remote subdev\n");</div><div class='add'>+		return PTR_ERR(asd);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dcmipp-&gt;notifier.ops = &amp;dcmipp_graph_notify_ops;</div><div class='add'>+</div><div class='add'>+	ret = v4l2_async_nf_register(&amp;dcmipp-&gt;notifier);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(dcmipp-&gt;dev, "Failed to register notifier\n");</div><div class='add'>+		v4l2_async_nf_cleanup(&amp;dcmipp-&gt;notifier);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp;</div><div class='add'>+	struct clk *kclk;</div><div class='add'>+	const struct dcmipp_pipeline_config *pipe_cfg;</div><div class='add'>+	struct reset_control *rstc;</div><div class='add'>+	int irq;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dcmipp = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*dcmipp), GFP_KERNEL);</div><div class='add'>+	if (!dcmipp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	dcmipp-&gt;dev = &amp;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	pipe_cfg = device_get_match_data(dcmipp-&gt;dev);</div><div class='add'>+	if (!pipe_cfg) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Can't get device data\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	dcmipp-&gt;pipe_cfg = pipe_cfg;</div><div class='add'>+</div><div class='add'>+	platform_set_drvdata(pdev, dcmipp);</div><div class='add'>+</div><div class='add'>+	/* Get hardware resources from devicetree */</div><div class='add'>+	rstc = devm_reset_control_get_exclusive(&amp;pdev-&gt;dev, NULL);</div><div class='add'>+	if (IS_ERR(rstc))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(rstc),</div><div class='add'>+				     "Could not get reset control\n");</div><div class='add'>+</div><div class='add'>+	irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (irq &lt;= 0) {</div><div class='add'>+		if (irq != -EPROBE_DEFER)</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "Could not get irq\n");</div><div class='add'>+		return irq ? irq : -ENXIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dcmipp-&gt;regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);</div><div class='add'>+	if (IS_ERR(dcmipp-&gt;regs)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Could not map registers\n");</div><div class='add'>+		return PTR_ERR(dcmipp-&gt;regs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = devm_request_threaded_irq(&amp;pdev-&gt;dev, irq, dcmipp_irq_callback,</div><div class='add'>+					dcmipp_irq_thread, IRQF_ONESHOT,</div><div class='add'>+					dev_name(&amp;pdev-&gt;dev), dcmipp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Unable to request irq %d\n", irq);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Reset device */</div><div class='add'>+	ret = reset_control_assert(rstc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to assert the reset line\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	usleep_range(3000, 5000);</div><div class='add'>+</div><div class='add'>+	ret = reset_control_deassert(rstc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to deassert the reset line\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	kclk = devm_clk_get(&amp;pdev-&gt;dev, NULL);</div><div class='add'>+	if (IS_ERR(kclk))</div><div class='add'>+		return dev_err_probe(&amp;pdev-&gt;dev, PTR_ERR(kclk),</div><div class='add'>+				     "Unable to get kclk\n");</div><div class='add'>+	dcmipp-&gt;kclk = kclk;</div><div class='add'>+</div><div class='add'>+	dcmipp-&gt;entity = devm_kcalloc(&amp;pdev-&gt;dev, dcmipp-&gt;pipe_cfg-&gt;num_ents,</div><div class='add'>+				      sizeof(*dcmipp-&gt;entity), GFP_KERNEL);</div><div class='add'>+	if (!dcmipp-&gt;entity)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Register the v4l2 struct */</div><div class='add'>+	ret = v4l2_device_register(&amp;pdev-&gt;dev, &amp;dcmipp-&gt;v4l2_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev,</div><div class='add'>+			"v4l2 device register failed (err=%d)\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Link the media device within the v4l2_device */</div><div class='add'>+	dcmipp-&gt;v4l2_dev.mdev = &amp;dcmipp-&gt;mdev;</div><div class='add'>+</div><div class='add'>+	/* Initialize media device */</div><div class='add'>+	strscpy(dcmipp-&gt;mdev.model, DCMIPP_MDEV_MODEL_NAME,</div><div class='add'>+		sizeof(dcmipp-&gt;mdev.model));</div><div class='add'>+	dcmipp-&gt;mdev.dev = &amp;pdev-&gt;dev;</div><div class='add'>+	media_device_init(&amp;dcmipp-&gt;mdev);</div><div class='add'>+</div><div class='add'>+	/* Initialize subdevs */</div><div class='add'>+	ret = dcmipp_create_subdevs(dcmipp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		media_device_cleanup(&amp;dcmipp-&gt;mdev);</div><div class='add'>+		v4l2_device_unregister(&amp;dcmipp-&gt;v4l2_dev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pm_runtime_enable(dcmipp-&gt;dev);</div><div class='add'>+</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "Probe done");</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = platform_get_drvdata(pdev);</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	v4l2_async_nf_unregister(&amp;dcmipp-&gt;notifier);</div><div class='add'>+	v4l2_async_nf_cleanup(&amp;dcmipp-&gt;notifier);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; dcmipp-&gt;pipe_cfg-&gt;num_ents; i++)</div><div class='add'>+		dcmipp-&gt;pipe_cfg-&gt;ents[i].release(dcmipp-&gt;entity[i]);</div><div class='add'>+</div><div class='add'>+	media_device_unregister(&amp;dcmipp-&gt;mdev);</div><div class='add'>+	media_device_cleanup(&amp;dcmipp-&gt;mdev);</div><div class='add'>+</div><div class='add'>+	v4l2_device_unregister(&amp;dcmipp-&gt;v4l2_dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_runtime_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	clk_disable_unprepare(dcmipp-&gt;kclk);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_runtime_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_device *dcmipp = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = clk_prepare_enable(dcmipp-&gt;kclk);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(dev, "%s: Failed to prepare_enable kclk\n", __func__);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	/* disable clock */</div><div class='add'>+	pm_runtime_force_suspend(dev);</div><div class='add'>+</div><div class='add'>+	/* change pinctrl state */</div><div class='add'>+	pinctrl_pm_select_sleep_state(dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	/* restore pinctl default state */</div><div class='add'>+	pinctrl_pm_select_default_state(dev);</div><div class='add'>+</div><div class='add'>+	/* clock enable */</div><div class='add'>+	pm_runtime_force_resume(dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct dev_pm_ops dcmipp_pm_ops = {</div><div class='add'>+	SYSTEM_SLEEP_PM_OPS(dcmipp_suspend, dcmipp_resume)</div><div class='add'>+	RUNTIME_PM_OPS(dcmipp_runtime_suspend, dcmipp_runtime_resume, NULL)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct platform_driver dcmipp_pdrv = {</div><div class='add'>+	.probe		= dcmipp_probe,</div><div class='add'>+	.remove		= dcmipp_remove,</div><div class='add'>+	.driver		= {</div><div class='add'>+		.name	= DCMIPP_PDEV_NAME,</div><div class='add'>+		.of_match_table = dcmipp_of_match,</div><div class='add'>+		.pm = pm_ptr(&amp;dcmipp_pm_ops),</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_platform_driver(dcmipp_pdrv);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Alain Volmat &lt;alain.volmat@foss.st.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface with Pixel Processor driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c b/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c<br/>new file mode 100644<br/>index 000000000000..62c5c3331cfe<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c</a></div><div class='hunk'>@@ -0,0 +1,440 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Driver for STM32 Digital Camera Memory Interface Pixel Processor</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) STMicroelectronics SA 2023</div><div class='add'>+ * Authors: Hugues Fruchet &lt;hugues.fruchet@foss.st.com&gt;</div><div class='add'>+ *          Alain Volmat &lt;alain.volmat@foss.st.com&gt;</div><div class='add'>+ *          for STMicroelectronics.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/v4l2-mediabus.h&gt;</div><div class='add'>+#include &lt;media/v4l2-event.h&gt;</div><div class='add'>+#include &lt;media/v4l2-subdev.h&gt;</div><div class='add'>+</div><div class='add'>+#include "dcmipp-common.h"</div><div class='add'>+</div><div class='add'>+#define DCMIPP_PRCR	0x104</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_SHIFT	16</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_YUV422	0x1e</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_RGB565	0x22</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_RAW8		0x2a</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_G8		0x4a</div><div class='add'>+#define DCMIPP_PRCR_FORMAT_BYTE_STREAM	0x5a</div><div class='add'>+#define DCMIPP_PRCR_ESS			BIT(4)</div><div class='add'>+#define DCMIPP_PRCR_PCKPOL		BIT(5)</div><div class='add'>+#define DCMIPP_PRCR_HSPOL		BIT(6)</div><div class='add'>+#define DCMIPP_PRCR_VSPOL		BIT(7)</div><div class='add'>+#define DCMIPP_PRCR_ENABLE		BIT(14)</div><div class='add'>+#define DCMIPP_PRCR_SWAPCYCLES		BIT(25)</div><div class='add'>+</div><div class='add'>+#define DCMIPP_PRESCR	0x108</div><div class='add'>+#define DCMIPP_PRESUR	0x10c</div><div class='add'>+</div><div class='add'>+#define IS_SINK(pad) (!(pad))</div><div class='add'>+#define IS_SRC(pad)  ((pad))</div><div class='add'>+</div><div class='add'>+struct dcmipp_par_pix_map {</div><div class='add'>+	unsigned int code_sink;</div><div class='add'>+	unsigned int code_src;</div><div class='add'>+	u8 prcr_format;</div><div class='add'>+	u8 prcr_swapcycles;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define PIXMAP_SINK_SRC_PRCR_SWAP(sink, src, prcr, swap)	\</div><div class='add'>+	{							\</div><div class='add'>+		.code_sink = MEDIA_BUS_FMT_##sink,		\</div><div class='add'>+		.code_src = MEDIA_BUS_FMT_##src,		\</div><div class='add'>+		.prcr_format = DCMIPP_PRCR_FORMAT_##prcr,	\</div><div class='add'>+		.prcr_swapcycles = swap,			\</div><div class='add'>+	}</div><div class='add'>+static const struct dcmipp_par_pix_map dcmipp_par_pix_map_list[] = {</div><div class='add'>+	/* RGB565 */</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_LE, RGB565_2X8_LE, RGB565, 1),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_BE, RGB565_2X8_LE, RGB565, 0),</div><div class='add'>+	/* YUV422 */</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, YUYV8_2X8, YUV422, 1),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, UYVY8_2X8, YUV422, 0),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, UYVY8_2X8, YUV422, 1),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, YUYV8_2X8, YUV422, 0),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_2X8, YVYU8_2X8, YUV422, 1),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_2X8, VYUY8_2X8, YUV422, 1),</div><div class='add'>+	/* GREY */</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(Y8_1X8, Y8_1X8, G8, 0),</div><div class='add'>+	/* Raw Bayer */</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR8_1X8, SBGGR8_1X8, RAW8, 0),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG8_1X8, SGBRG8_1X8, RAW8, 0),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG8_1X8, SGRBG8_1X8, RAW8, 0),</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB8_1X8, SRGGB8_1X8, RAW8, 0),</div><div class='add'>+	/* JPEG */</div><div class='add'>+	PIXMAP_SINK_SRC_PRCR_SWAP(JPEG_1X8, JPEG_1X8, BYTE_STREAM, 0),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * Search through the pix_map table, skipping two consecutive entry with the</div><div class='add'>+ * same code</div><div class='add'>+ */</div><div class='add'>+static inline const struct dcmipp_par_pix_map *dcmipp_par_pix_map_by_index</div><div class='add'>+						(unsigned int index,</div><div class='add'>+						 unsigned int pad)</div><div class='add'>+{</div><div class='add'>+	unsigned int i = 0;</div><div class='add'>+	u32 prev_code = 0, cur_code;</div><div class='add'>+</div><div class='add'>+	while (i &lt; ARRAY_SIZE(dcmipp_par_pix_map_list)) {</div><div class='add'>+		if (IS_SRC(pad))</div><div class='add'>+			cur_code = dcmipp_par_pix_map_list[i].code_src;</div><div class='add'>+		else</div><div class='add'>+			cur_code = dcmipp_par_pix_map_list[i].code_sink;</div><div class='add'>+</div><div class='add'>+		if (cur_code == prev_code) {</div><div class='add'>+			i++;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+		prev_code = cur_code;</div><div class='add'>+</div><div class='add'>+		if (index == 0)</div><div class='add'>+			break;</div><div class='add'>+		i++;</div><div class='add'>+		index--;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (i &gt;= ARRAY_SIZE(dcmipp_par_pix_map_list))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	return &amp;dcmipp_par_pix_map_list[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline const struct dcmipp_par_pix_map *dcmipp_par_pix_map_by_code</div><div class='add'>+					(u32 code_sink, u32 code_src)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(dcmipp_par_pix_map_list); i++) {</div><div class='add'>+		if ((dcmipp_par_pix_map_list[i].code_sink == code_sink &amp;&amp;</div><div class='add'>+		     dcmipp_par_pix_map_list[i].code_src == code_src) ||</div><div class='add'>+		    (dcmipp_par_pix_map_list[i].code_sink == code_src &amp;&amp;</div><div class='add'>+		     dcmipp_par_pix_map_list[i].code_src == code_sink) ||</div><div class='add'>+		    (dcmipp_par_pix_map_list[i].code_sink == code_sink &amp;&amp;</div><div class='add'>+		     code_src == 0) ||</div><div class='add'>+		    (code_sink == 0 &amp;&amp;</div><div class='add'>+		     dcmipp_par_pix_map_list[i].code_src == code_src))</div><div class='add'>+			return &amp;dcmipp_par_pix_map_list[i];</div><div class='add'>+	}</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_par_device {</div><div class='add'>+	struct dcmipp_ent_device ved;</div><div class='add'>+	struct v4l2_subdev sd;</div><div class='add'>+	struct device *dev;</div><div class='add'>+	void __iomem *regs;</div><div class='add'>+	bool streaming;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_mbus_framefmt fmt_default = {</div><div class='add'>+	.width = DCMIPP_FMT_WIDTH_DEFAULT,</div><div class='add'>+	.height = DCMIPP_FMT_HEIGHT_DEFAULT,</div><div class='add'>+	.code = MEDIA_BUS_FMT_RGB565_2X8_LE,</div><div class='add'>+	.field = V4L2_FIELD_NONE,</div><div class='add'>+	.colorspace = DCMIPP_COLORSPACE_DEFAULT,</div><div class='add'>+	.ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,</div><div class='add'>+	.quantization = DCMIPP_QUANTIZATION_DEFAULT,</div><div class='add'>+	.xfer_func = DCMIPP_XFER_FUNC_DEFAULT,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				 struct v4l2_subdev_state *sd_state)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='add'>+		struct v4l2_mbus_framefmt *mf;</div><div class='add'>+</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, i);</div><div class='add'>+		*mf = fmt_default;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='add'>+				     struct v4l2_subdev_state *sd_state,</div><div class='add'>+				     struct v4l2_subdev_mbus_code_enum *code)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_par_pix_map *vpix =</div><div class='add'>+		dcmipp_par_pix_map_by_index(code-&gt;index, code-&gt;pad);</div><div class='add'>+</div><div class='add'>+	if (!vpix)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	code-&gt;code = IS_SRC(code-&gt;pad) ? vpix-&gt;code_src : vpix-&gt;code_sink;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_enum_frame_size(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *sd_state,</div><div class='add'>+				      struct v4l2_subdev_frame_size_enum *fse)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_par_pix_map *vpix;</div><div class='add'>+</div><div class='add'>+	if (fse-&gt;index)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Only accept code in the pix map table */</div><div class='add'>+	vpix = dcmipp_par_pix_map_by_code(IS_SINK(fse-&gt;pad) ? fse-&gt;code : 0,</div><div class='add'>+					  IS_SRC(fse-&gt;pad) ? fse-&gt;code : 0);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fse-&gt;min_width = DCMIPP_FRAME_MIN_WIDTH;</div><div class='add'>+	fse-&gt;max_width = DCMIPP_FRAME_MAX_WIDTH;</div><div class='add'>+	fse-&gt;min_height = DCMIPP_FRAME_MIN_HEIGHT;</div><div class='add'>+	fse-&gt;max_height = DCMIPP_FRAME_MAX_HEIGHT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dcmipp_par_adjust_fmt(struct dcmipp_par_device *par,</div><div class='add'>+				  struct v4l2_mbus_framefmt *fmt, __u32 pad)</div><div class='add'>+{</div><div class='add'>+	const struct dcmipp_par_pix_map *vpix;</div><div class='add'>+</div><div class='add'>+	/* Only accept code in the pix map table */</div><div class='add'>+	vpix = dcmipp_par_pix_map_by_code(IS_SINK(pad) ? fmt-&gt;code : 0,</div><div class='add'>+					  IS_SRC(pad) ? fmt-&gt;code : 0);</div><div class='add'>+	if (!vpix)</div><div class='add'>+		fmt-&gt;code = fmt_default.code;</div><div class='add'>+</div><div class='add'>+	/* Exclude JPEG if BT656 bus is selected */</div><div class='add'>+	if (vpix &amp;&amp; vpix-&gt;code_sink == MEDIA_BUS_FMT_JPEG_1X8 &amp;&amp;</div><div class='add'>+	    par-&gt;ved.bus_type == V4L2_MBUS_BT656)</div><div class='add'>+		fmt-&gt;code = fmt_default.code;</div><div class='add'>+</div><div class='add'>+	fmt-&gt;width = clamp_t(u32, fmt-&gt;width, DCMIPP_FRAME_MIN_WIDTH,</div><div class='add'>+			     DCMIPP_FRAME_MAX_WIDTH) &amp; ~1;</div><div class='add'>+	fmt-&gt;height = clamp_t(u32, fmt-&gt;height, DCMIPP_FRAME_MIN_HEIGHT,</div><div class='add'>+			      DCMIPP_FRAME_MAX_HEIGHT) &amp; ~1;</div><div class='add'>+</div><div class='add'>+	if (fmt-&gt;field == V4L2_FIELD_ANY || fmt-&gt;field == V4L2_FIELD_ALTERNATE)</div><div class='add'>+		fmt-&gt;field = fmt_default.field;</div><div class='add'>+</div><div class='add'>+	dcmipp_colorimetry_clamp(fmt);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_set_fmt(struct v4l2_subdev *sd,</div><div class='add'>+			      struct v4l2_subdev_state *sd_state,</div><div class='add'>+			      struct v4l2_subdev_format *fmt)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_par_device *par = v4l2_get_subdevdata(sd);</div><div class='add'>+	struct v4l2_mbus_framefmt *mf;</div><div class='add'>+</div><div class='add'>+	if (par-&gt;streaming)</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='add'>+</div><div class='add'>+	/* Set the new format */</div><div class='add'>+	dcmipp_par_adjust_fmt(par, &amp;fmt-&gt;format, fmt-&gt;pad);</div><div class='add'>+</div><div class='add'>+	dev_dbg(par-&gt;dev, "%s: format update: old:%dx%d (0x%x, %d, %d, %d, %d) new:%dx%d (0x%x, %d, %d, %d, %d)\n",</div><div class='add'>+		par-&gt;sd.name,</div><div class='add'>+		/* old */</div><div class='add'>+		mf-&gt;width, mf-&gt;height, mf-&gt;code,</div><div class='add'>+		mf-&gt;colorspace,	mf-&gt;quantization,</div><div class='add'>+		mf-&gt;xfer_func, mf-&gt;ycbcr_enc,</div><div class='add'>+		/* new */</div><div class='add'>+		fmt-&gt;format.width, fmt-&gt;format.height, fmt-&gt;format.code,</div><div class='add'>+		fmt-&gt;format.colorspace, fmt-&gt;format.quantization,</div><div class='add'>+		fmt-&gt;format.xfer_func, fmt-&gt;format.ycbcr_enc);</div><div class='add'>+</div><div class='add'>+	*mf = fmt-&gt;format;</div><div class='add'>+</div><div class='add'>+	/* When setting the sink format, report that format on the src pad */</div><div class='add'>+	if (IS_SINK(fmt-&gt;pad)) {</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, 1);</div><div class='add'>+		*mf = fmt-&gt;format;</div><div class='add'>+		dcmipp_par_adjust_fmt(par, mf, 1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_pad_ops dcmipp_par_pad_ops = {</div><div class='add'>+	.enum_mbus_code		= dcmipp_par_enum_mbus_code,</div><div class='add'>+	.enum_frame_size	= dcmipp_par_enum_frame_size,</div><div class='add'>+	.get_fmt		= v4l2_subdev_get_fmt,</div><div class='add'>+	.set_fmt		= dcmipp_par_set_fmt,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_configure(struct dcmipp_par_device *par)</div><div class='add'>+{</div><div class='add'>+	u32 val = 0;</div><div class='add'>+	const struct dcmipp_par_pix_map *vpix;</div><div class='add'>+	struct v4l2_subdev_state *state;</div><div class='add'>+	struct v4l2_mbus_framefmt *sink_fmt;</div><div class='add'>+	struct v4l2_mbus_framefmt *src_fmt;</div><div class='add'>+</div><div class='add'>+	/* Set vertical synchronization polarity */</div><div class='add'>+	if (par-&gt;ved.bus.flags &amp; V4L2_MBUS_VSYNC_ACTIVE_HIGH)</div><div class='add'>+		val |= DCMIPP_PRCR_VSPOL;</div><div class='add'>+</div><div class='add'>+	/* Set horizontal synchronization polarity */</div><div class='add'>+	if (par-&gt;ved.bus.flags &amp; V4L2_MBUS_HSYNC_ACTIVE_HIGH)</div><div class='add'>+		val |= DCMIPP_PRCR_HSPOL;</div><div class='add'>+</div><div class='add'>+	/* Set pixel clock polarity */</div><div class='add'>+	if (par-&gt;ved.bus.flags &amp; V4L2_MBUS_PCLK_SAMPLE_RISING)</div><div class='add'>+		val |= DCMIPP_PRCR_PCKPOL;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * BT656 embedded synchronisation bus mode.</div><div class='add'>+	 *</div><div class='add'>+	 * Default SAV/EAV mode is supported here with default codes</div><div class='add'>+	 * SAV=0xff000080 &amp; EAV=0xff00009d.</div><div class='add'>+	 * With DCMIPP this means LSC=SAV=0x80 &amp; LEC=EAV=0x9d.</div><div class='add'>+	 */</div><div class='add'>+	if (par-&gt;ved.bus_type == V4L2_MBUS_BT656) {</div><div class='add'>+		val |= DCMIPP_PRCR_ESS;</div><div class='add'>+</div><div class='add'>+		/* Unmask all codes */</div><div class='add'>+		reg_write(par, DCMIPP_PRESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */</div><div class='add'>+</div><div class='add'>+		/* Trig on LSC=0x80 &amp; LEC=0x9d codes, ignore FSC and FEC */</div><div class='add'>+		reg_write(par, DCMIPP_PRESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Set format */</div><div class='add'>+	state = v4l2_subdev_lock_and_get_active_state(&amp;par-&gt;sd);</div><div class='add'>+	sink_fmt = v4l2_subdev_state_get_format(state, 0);</div><div class='add'>+	src_fmt = v4l2_subdev_state_get_format(state, 1);</div><div class='add'>+	v4l2_subdev_unlock_state(state);</div><div class='add'>+</div><div class='add'>+	vpix = dcmipp_par_pix_map_by_code(sink_fmt-&gt;code, src_fmt-&gt;code);</div><div class='add'>+	if (!vpix) {</div><div class='add'>+		dev_err(par-&gt;dev, "Invalid sink/src format configuration\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val |= vpix-&gt;prcr_format &lt;&lt; DCMIPP_PRCR_FORMAT_SHIFT;</div><div class='add'>+</div><div class='add'>+	/* swap cycles */</div><div class='add'>+	if (vpix-&gt;prcr_swapcycles)</div><div class='add'>+		val |= DCMIPP_PRCR_SWAPCYCLES;</div><div class='add'>+</div><div class='add'>+	reg_write(par, DCMIPP_PRCR, val);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dcmipp_par_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_par_device *par =</div><div class='add'>+				container_of(sd, struct dcmipp_par_device, sd);</div><div class='add'>+	struct v4l2_subdev *s_subdev;</div><div class='add'>+	struct media_pad *pad;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	/* Get source subdev */</div><div class='add'>+	pad = media_pad_remote_pad_first(&amp;sd-&gt;entity.pads[0]);</div><div class='add'>+	if (!pad || !is_media_entity_v4l2_subdev(pad-&gt;entity))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	s_subdev = media_entity_to_v4l2_subdev(pad-&gt;entity);</div><div class='add'>+</div><div class='add'>+	if (enable) {</div><div class='add'>+		ret = dcmipp_par_configure(par);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/* Enable parallel interface */</div><div class='add'>+		reg_set(par, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);</div><div class='add'>+</div><div class='add'>+		ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(par-&gt;dev,</div><div class='add'>+				"failed to start source subdev streaming (%d)\n",</div><div class='add'>+				ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(par-&gt;dev,</div><div class='add'>+				"failed to stop source subdev streaming (%d)\n",</div><div class='add'>+				ret);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Disable parallel interface */</div><div class='add'>+		reg_clear(par, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	par-&gt;streaming = enable;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_video_ops dcmipp_par_video_ops = {</div><div class='add'>+	.s_stream = dcmipp_par_s_stream,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_ops dcmipp_par_ops = {</div><div class='add'>+	.pad = &amp;dcmipp_par_pad_ops,</div><div class='add'>+	.video = &amp;dcmipp_par_video_ops,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void dcmipp_par_release(struct v4l2_subdev *sd)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_par_device *par =</div><div class='add'>+				container_of(sd, struct dcmipp_par_device, sd);</div><div class='add'>+</div><div class='add'>+	kfree(par);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct v4l2_subdev_internal_ops dcmipp_par_int_ops = {</div><div class='add'>+	.init_state = dcmipp_par_init_state,</div><div class='add'>+	.release = dcmipp_par_release,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void dcmipp_par_ent_release(struct dcmipp_ent_device *ved)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_par_device *par =</div><div class='add'>+			container_of(ved, struct dcmipp_par_device, ved);</div><div class='add'>+</div><div class='add'>+	dcmipp_ent_sd_unregister(ved, &amp;par-&gt;sd);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct dcmipp_ent_device *dcmipp_par_ent_init(struct device *dev,</div><div class='add'>+					      const char *entity_name,</div><div class='add'>+					      struct v4l2_device *v4l2_dev,</div><div class='add'>+					      void __iomem *regs)</div><div class='add'>+{</div><div class='add'>+	struct dcmipp_par_device *par;</div><div class='add'>+	const unsigned long pads_flag[] = {</div><div class='add'>+		MEDIA_PAD_FL_SINK, MEDIA_PAD_FL_SOURCE,</div><div class='add'>+	};</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Allocate the par struct */</div><div class='add'>+	par = kzalloc(sizeof(*par), GFP_KERNEL);</div><div class='add'>+	if (!par)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	par-&gt;regs = regs;</div><div class='add'>+</div><div class='add'>+	/* Initialize ved and sd */</div><div class='add'>+	ret = dcmipp_ent_sd_register(&amp;par-&gt;ved, &amp;par-&gt;sd, v4l2_dev,</div><div class='add'>+				     entity_name, MEDIA_ENT_F_VID_IF_BRIDGE,</div><div class='add'>+				     ARRAY_SIZE(pads_flag), pads_flag,</div><div class='add'>+				     &amp;dcmipp_par_int_ops, &amp;dcmipp_par_ops,</div><div class='add'>+				     NULL, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		kfree(par);</div><div class='add'>+		return ERR_PTR(ret);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	par-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	return &amp;par-&gt;ved;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c<br/>index ad13d447d483..097a3a08ef7d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c</a></div><div class='hunk'>@@ -211,6 +211,7 @@ static int sun4i_csi_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize subdev */</div><div class='ctx'> 	v4l2_subdev_init(subdev, &amp;sun4i_csi_subdev_ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;sun4i_csi_subdev_internal_ops;</div><div class='ctx'> 	subdev-&gt;flags = V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;</div><div class='ctx'> 	subdev-&gt;entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='ctx'> 	subdev-&gt;owner = THIS_MODULE;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h<br/>index 8eeed87bfb13..4e0c2df45d4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h</a></div><div class='hunk'>@@ -89,6 +89,7 @@ enum csi_subdev_pads {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern const struct v4l2_subdev_ops sun4i_csi_subdev_ops;</div><div class='add'>+extern const struct v4l2_subdev_internal_ops sun4i_csi_subdev_internal_ops;</div><div class='ctx'> </div><div class='ctx'> struct sun4i_csi_format {</div><div class='ctx'> 	u32			mbus;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c<br/>index 95b5633b7914..d1371e130113 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c</a></div><div class='hunk'>@@ -411,7 +411,7 @@ int sun4i_csi_dma_register(struct sun4i_csi *csi, int irq)</div><div class='ctx'> 	for (i = 0; i &lt; CSI_MAX_BUFFER; i++)</div><div class='ctx'> 		csi-&gt;current_buf[i] = NULL;</div><div class='ctx'> </div><div class='del'>-	q-&gt;min_buffers_needed = 3;</div><div class='add'>+	q-&gt;min_queued_buffers = 3;</div><div class='ctx'> 	q-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	q-&gt;lock = &amp;csi-&gt;lock;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c<br/>index 48702134ccc5..744197b0fccb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c</a></div><div class='hunk'>@@ -266,12 +266,12 @@ static const struct v4l2_mbus_framefmt sun4i_csi_pad_fmt_default = {</div><div class='ctx'> 	.xfer_func = V4L2_XFER_FUNC_DEFAULT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int sun4i_csi_subdev_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				     struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int sun4i_csi_subdev_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				       struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_try_format(subdev, sd_state, CSI_SUBDEV_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(sd_state, CSI_SUBDEV_SINK);</div><div class='ctx'> 	*fmt = sun4i_csi_pad_fmt_default;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -285,8 +285,7 @@ static int sun4i_csi_subdev_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *subdev_fmt;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		subdev_fmt = v4l2_subdev_get_try_format(subdev, sd_state,</div><div class='del'>-							fmt-&gt;pad);</div><div class='add'>+		subdev_fmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		subdev_fmt = &amp;csi-&gt;subdev_fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -303,8 +302,7 @@ static int sun4i_csi_subdev_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	struct v4l2_mbus_framefmt *subdev_fmt;</div><div class='ctx'> </div><div class='ctx'> 	if (fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		subdev_fmt = v4l2_subdev_get_try_format(subdev, sd_state,</div><div class='del'>-							fmt-&gt;pad);</div><div class='add'>+		subdev_fmt = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		subdev_fmt = &amp;csi-&gt;subdev_fmt;</div><div class='ctx'> </div><div class='hunk'>@@ -336,7 +334,6 @@ sun4i_csi_subdev_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops sun4i_csi_subdev_pad_ops = {</div><div class='ctx'> 	.link_validate	= v4l2_subdev_link_validate_default,</div><div class='del'>-	.init_cfg	= sun4i_csi_subdev_init_cfg,</div><div class='ctx'> 	.get_fmt	= sun4i_csi_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt	= sun4i_csi_subdev_set_fmt,</div><div class='ctx'> 	.enum_mbus_code	= sun4i_csi_subdev_enum_mbus_code,</div><div class='hunk'>@@ -346,6 +343,10 @@ const struct v4l2_subdev_ops sun4i_csi_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;sun4i_csi_subdev_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+const struct v4l2_subdev_internal_ops sun4i_csi_subdev_internal_ops = {</div><div class='add'>+	.init_state	= sun4i_csi_subdev_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int sun4i_csi_v4l2_register(struct sun4i_csi *csi)</div><div class='ctx'> {</div><div class='ctx'> 	struct video_device *vdev = &amp;csi-&gt;vdev;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c<br/>index e573413123b9..d006d9dd0170 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c</a></div><div class='hunk'>@@ -501,13 +501,13 @@ sun6i_csi_bridge_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)</div><div class='ctx'> 	mbus_format-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sun6i_csi_bridge_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				     struct v4l2_subdev_state *state)</div><div class='add'>+static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				       struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);</div><div class='ctx'> 	unsigned int pad = SUN6I_CSI_BRIDGE_PAD_SINK;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbus_format =</div><div class='del'>-		v4l2_subdev_get_try_format(subdev, state, pad);</div><div class='add'>+		v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> 	struct mutex *lock = &amp;csi_dev-&gt;bridge.lock;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(lock);</div><div class='hunk'>@@ -547,8 +547,8 @@ static int sun6i_csi_bridge_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	mutex_lock(lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*mbus_format = *v4l2_subdev_get_try_format(subdev, state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		*mbus_format = *v4l2_subdev_state_get_format(state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		*mbus_format = csi_dev-&gt;bridge.mbus_format;</div><div class='ctx'> </div><div class='hunk'>@@ -570,7 +570,7 @@ static int sun6i_csi_bridge_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	sun6i_csi_bridge_mbus_format_prepare(mbus_format);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(subdev, state, format-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(state, format-&gt;pad) =</div><div class='ctx'> 			*mbus_format;</div><div class='ctx'> 	else</div><div class='ctx'> 		csi_dev-&gt;bridge.mbus_format = *mbus_format;</div><div class='hunk'>@@ -581,7 +581,6 @@ static int sun6i_csi_bridge_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops sun6i_csi_bridge_pad_ops = {</div><div class='del'>-	.init_cfg	= sun6i_csi_bridge_init_cfg,</div><div class='ctx'> 	.enum_mbus_code	= sun6i_csi_bridge_enum_mbus_code,</div><div class='ctx'> 	.get_fmt	= sun6i_csi_bridge_get_fmt,</div><div class='ctx'> 	.set_fmt	= sun6i_csi_bridge_set_fmt,</div><div class='hunk'>@@ -592,6 +591,10 @@ static const struct v4l2_subdev_ops sun6i_csi_bridge_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;sun6i_csi_bridge_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops sun6i_csi_bridge_internal_ops = {</div><div class='add'>+	.init_state	= sun6i_csi_bridge_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Media Entity */</div><div class='ctx'> </div><div class='ctx'> static const struct media_entity_operations sun6i_csi_bridge_entity_ops = {</div><div class='hunk'>@@ -782,6 +785,7 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)</div><div class='ctx'> 	/* V4L2 Subdev */</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(subdev, &amp;sun6i_csi_bridge_subdev_ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;sun6i_csi_bridge_internal_ops;</div><div class='ctx'> 	strscpy(subdev-&gt;name, SUN6I_CSI_BRIDGE_NAME, sizeof(subdev-&gt;name));</div><div class='ctx'> 	subdev-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	subdev-&gt;owner = THIS_MODULE;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c<br/>index cf6aadbc130b..14c0dc827c52 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c</a></div><div class='hunk'>@@ -1010,7 +1010,7 @@ int sun6i_csi_capture_setup(struct sun6i_csi_device *csi_dev)</div><div class='ctx'> 	queue-&gt;buf_struct_size = sizeof(struct sun6i_csi_buffer);</div><div class='ctx'> 	queue-&gt;ops = &amp;sun6i_csi_capture_queue_ops;</div><div class='ctx'> 	queue-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='del'>-	queue-&gt;min_buffers_needed = 2;</div><div class='add'>+	queue-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	queue-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	queue-&gt;lock = &amp;capture-&gt;lock;</div><div class='ctx'> 	queue-&gt;dev = csi_dev-&gt;dev;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c<br/>index 08d86c17b284..f9d4dc45b490 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c</a></div><div class='hunk'>@@ -305,13 +305,13 @@ sun6i_mipi_csi2_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)</div><div class='ctx'> 	mbus_format-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sun6i_mipi_csi2_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-				    struct v4l2_subdev_state *state)</div><div class='add'>+static int sun6i_mipi_csi2_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+				      struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct sun6i_mipi_csi2_device *csi2_dev = v4l2_get_subdevdata(subdev);</div><div class='ctx'> 	unsigned int pad = SUN6I_MIPI_CSI2_PAD_SINK;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbus_format =</div><div class='del'>-		v4l2_subdev_get_try_format(subdev, state, pad);</div><div class='add'>+		v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> 	struct mutex *lock = &amp;csi2_dev-&gt;bridge.lock;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(lock);</div><div class='hunk'>@@ -351,8 +351,8 @@ static int sun6i_mipi_csi2_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	mutex_lock(lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*mbus_format = *v4l2_subdev_get_try_format(subdev, state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		*mbus_format = *v4l2_subdev_state_get_format(state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		*mbus_format = csi2_dev-&gt;bridge.mbus_format;</div><div class='ctx'> </div><div class='hunk'>@@ -374,7 +374,7 @@ static int sun6i_mipi_csi2_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	sun6i_mipi_csi2_mbus_format_prepare(mbus_format);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(subdev, state, format-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(state, format-&gt;pad) =</div><div class='ctx'> 			*mbus_format;</div><div class='ctx'> 	else</div><div class='ctx'> 		csi2_dev-&gt;bridge.mbus_format = *mbus_format;</div><div class='hunk'>@@ -385,7 +385,6 @@ static int sun6i_mipi_csi2_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops sun6i_mipi_csi2_pad_ops = {</div><div class='del'>-	.init_cfg	= sun6i_mipi_csi2_init_cfg,</div><div class='ctx'> 	.enum_mbus_code	= sun6i_mipi_csi2_enum_mbus_code,</div><div class='ctx'> 	.get_fmt	= sun6i_mipi_csi2_get_fmt,</div><div class='ctx'> 	.set_fmt	= sun6i_mipi_csi2_set_fmt,</div><div class='hunk'>@@ -396,6 +395,10 @@ static const struct v4l2_subdev_ops sun6i_mipi_csi2_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;sun6i_mipi_csi2_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops sun6i_mipi_csi2_internal_ops = {</div><div class='add'>+	.init_state	= sun6i_mipi_csi2_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Media Entity */</div><div class='ctx'> </div><div class='ctx'> static const struct media_entity_operations sun6i_mipi_csi2_entity_ops = {</div><div class='hunk'>@@ -504,6 +507,7 @@ static int sun6i_mipi_csi2_bridge_setup(struct sun6i_mipi_csi2_device *csi2_dev)</div><div class='ctx'> 	/* V4L2 Subdev */</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(subdev, &amp;sun6i_mipi_csi2_subdev_ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;sun6i_mipi_csi2_internal_ops;</div><div class='ctx'> 	strscpy(subdev-&gt;name, SUN6I_MIPI_CSI2_NAME, sizeof(subdev-&gt;name));</div><div class='ctx'> 	subdev-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	subdev-&gt;owner = THIS_MODULE;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c<br/>index 14a1844812c0..4a5698eb12b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c</a></div><div class='hunk'>@@ -338,14 +338,14 @@ sun8i_a83t_mipi_csi2_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)</div><div class='ctx'> 	mbus_format-&gt;xfer_func = V4L2_XFER_FUNC_DEFAULT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sun8i_a83t_mipi_csi2_init_cfg(struct v4l2_subdev *subdev,</div><div class='del'>-					 struct v4l2_subdev_state *state)</div><div class='add'>+static int sun8i_a83t_mipi_csi2_init_state(struct v4l2_subdev *subdev,</div><div class='add'>+					   struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct sun8i_a83t_mipi_csi2_device *csi2_dev =</div><div class='ctx'> 		v4l2_get_subdevdata(subdev);</div><div class='ctx'> 	unsigned int pad = SUN8I_A83T_MIPI_CSI2_PAD_SINK;</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbus_format =</div><div class='del'>-		v4l2_subdev_get_try_format(subdev, state, pad);</div><div class='add'>+		v4l2_subdev_state_get_format(state, pad);</div><div class='ctx'> 	struct mutex *lock = &amp;csi2_dev-&gt;bridge.lock;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(lock);</div><div class='hunk'>@@ -387,8 +387,8 @@ static int sun8i_a83t_mipi_csi2_get_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	mutex_lock(lock);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*mbus_format = *v4l2_subdev_get_try_format(subdev, state,</div><div class='del'>-							   format-&gt;pad);</div><div class='add'>+		*mbus_format = *v4l2_subdev_state_get_format(state,</div><div class='add'>+							     format-&gt;pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		*mbus_format = csi2_dev-&gt;bridge.mbus_format;</div><div class='ctx'> </div><div class='hunk'>@@ -411,7 +411,7 @@ static int sun8i_a83t_mipi_csi2_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> 	sun8i_a83t_mipi_csi2_mbus_format_prepare(mbus_format);</div><div class='ctx'> </div><div class='ctx'> 	if (format-&gt;which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		*v4l2_subdev_get_try_format(subdev, state, format-&gt;pad) =</div><div class='add'>+		*v4l2_subdev_state_get_format(state, format-&gt;pad) =</div><div class='ctx'> 			*mbus_format;</div><div class='ctx'> 	else</div><div class='ctx'> 		csi2_dev-&gt;bridge.mbus_format = *mbus_format;</div><div class='hunk'>@@ -422,7 +422,6 @@ static int sun8i_a83t_mipi_csi2_set_fmt(struct v4l2_subdev *subdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops sun8i_a83t_mipi_csi2_pad_ops = {</div><div class='del'>-	.init_cfg	= sun8i_a83t_mipi_csi2_init_cfg,</div><div class='ctx'> 	.enum_mbus_code	= sun8i_a83t_mipi_csi2_enum_mbus_code,</div><div class='ctx'> 	.get_fmt	= sun8i_a83t_mipi_csi2_get_fmt,</div><div class='ctx'> 	.set_fmt	= sun8i_a83t_mipi_csi2_set_fmt,</div><div class='hunk'>@@ -433,6 +432,10 @@ static const struct v4l2_subdev_ops sun8i_a83t_mipi_csi2_subdev_ops = {</div><div class='ctx'> 	.pad	= &amp;sun8i_a83t_mipi_csi2_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops sun8i_a83t_mipi_csi2_internal_ops = {</div><div class='add'>+	.init_state	= sun8i_a83t_mipi_csi2_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Media Entity */</div><div class='ctx'> </div><div class='ctx'> static const struct media_entity_operations sun8i_a83t_mipi_csi2_entity_ops = {</div><div class='hunk'>@@ -542,6 +545,7 @@ sun8i_a83t_mipi_csi2_bridge_setup(struct sun8i_a83t_mipi_csi2_device *csi2_dev)</div><div class='ctx'> 	/* V4L2 Subdev */</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(subdev, &amp;sun8i_a83t_mipi_csi2_subdev_ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;sun8i_a83t_mipi_csi2_internal_ops;</div><div class='ctx'> 	strscpy(subdev-&gt;name, SUN8I_A83T_MIPI_CSI2_NAME, sizeof(subdev-&gt;name));</div><div class='ctx'> 	subdev-&gt;flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	subdev-&gt;owner = THIS_MODULE;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c<br/>index 90ab1d77b6a5..954fabec27f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun8i-di/sun8i-di.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-di/sun8i-di.c</a></div><div class='hunk'>@@ -673,7 +673,7 @@ static int deinterlace_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	src_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	src_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='del'>-	src_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	src_vq-&gt;ops = &amp;deinterlace_qops;</div><div class='ctx'> 	src_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	src_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='hunk'>@@ -688,7 +688,7 @@ static int deinterlace_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	dst_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	dst_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = 2;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	dst_vq-&gt;ops = &amp;deinterlace_qops;</div><div class='ctx'> 	dst_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	dst_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='head'>diff --git a/drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c b/drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c<br/>index 0b025ec91826..a12323ca89fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c</a></div><div class='hunk'>@@ -536,7 +536,7 @@ static int rotate_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	src_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	src_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	src_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='del'>-	src_vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	src_vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	src_vq-&gt;ops = &amp;rotate_qops;</div><div class='ctx'> 	src_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	src_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='hunk'>@@ -551,7 +551,7 @@ static int rotate_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 	dst_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	dst_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='del'>-	dst_vq-&gt;min_buffers_needed = 2;</div><div class='add'>+	dst_vq-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	dst_vq-&gt;ops = &amp;rotate_qops;</div><div class='ctx'> 	dst_vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	dst_vq-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;</div><div class='head'>diff --git a/drivers/media/platform/ti/am437x/am437x-vpfe.c b/drivers/media/platform/ti/am437x/am437x-vpfe.c<br/>index 5fa2ea9025d9..77e12457d149 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/am437x/am437x-vpfe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/am437x/am437x-vpfe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/am437x/am437x-vpfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/am437x/am437x-vpfe.c</a></div><div class='hunk'>@@ -1771,9 +1771,10 @@ static int vpfe_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct vpfe_device *vpfe = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned size = vpfe-&gt;fmt.fmt.pix.sizeimage;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (sizes[0] &lt; size)</div><div class='hunk'>@@ -2233,7 +2234,7 @@ static int vpfe_probe_complete(struct vpfe_device *vpfe)</div><div class='ctx'> 	q-&gt;buf_struct_size = sizeof(struct vpfe_cap_buffer);</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	q-&gt;lock = &amp;vpfe-&gt;lock;</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	q-&gt;dev = vpfe-&gt;pdev;</div><div class='ctx'> </div><div class='ctx'> 	err = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/ti/cal/cal-camerarx.c b/drivers/media/platform/ti/cal/cal-camerarx.c<br/>index 1a4273bbe752..4afc2ad00330 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/cal/cal-camerarx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/cal/cal-camerarx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/cal/cal-camerarx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/cal/cal-camerarx.c</a></div><div class='hunk'>@@ -57,7 +57,7 @@ static s64 cal_camerarx_get_ext_link_freq(struct cal_camerarx *phy)</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_get_locked_active_state(&amp;phy-&gt;subdev);</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(&amp;phy-&gt;subdev, state, CAL_CAMERARX_PAD_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, CAL_CAMERARX_PAD_SINK);</div><div class='ctx'> </div><div class='ctx'> 	fmtinfo = cal_format_by_code(fmt-&gt;code);</div><div class='ctx'> 	if (!fmtinfo)</div><div class='hunk'>@@ -621,8 +621,6 @@ static int cal_camerarx_sd_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 					  struct v4l2_subdev_state *state,</div><div class='ctx'> 					  struct v4l2_subdev_mbus_code_enum *code)</div><div class='ctx'> {</div><div class='del'>-	struct cal_camerarx *phy = to_cal_camerarx(sd);</div><div class='del'>-</div><div class='ctx'> 	/* No transcoding, source and sink codes must match. */</div><div class='ctx'> 	if (cal_rx_pad_is_source(code-&gt;pad)) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='hunk'>@@ -630,8 +628,8 @@ static int cal_camerarx_sd_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 		if (code-&gt;index &gt; 0)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(&amp;phy-&gt;subdev, state,</div><div class='del'>-						 CAL_CAMERARX_PAD_SINK);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(state,</div><div class='add'>+						   CAL_CAMERARX_PAD_SINK);</div><div class='ctx'> 		code-&gt;code = fmt-&gt;code;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (code-&gt;index &gt;= cal_num_formats)</div><div class='hunk'>@@ -656,8 +654,8 @@ static int cal_camerarx_sd_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 	if (cal_rx_pad_is_source(fse-&gt;pad)) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(sd, state,</div><div class='del'>-						 CAL_CAMERARX_PAD_SINK);</div><div class='add'>+		fmt = v4l2_subdev_state_get_format(state,</div><div class='add'>+						   CAL_CAMERARX_PAD_SINK);</div><div class='ctx'> 		if (fse-&gt;code != fmt-&gt;code)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -713,18 +711,18 @@ static int cal_camerarx_sd_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	/* Store the format and propagate it to the source pad. */</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, state, CAL_CAMERARX_PAD_SINK);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, CAL_CAMERARX_PAD_SINK);</div><div class='ctx'> 	*fmt = format-&gt;format;</div><div class='ctx'> </div><div class='del'>-	fmt = v4l2_subdev_get_pad_format(sd, state,</div><div class='del'>-					 CAL_CAMERARX_PAD_FIRST_SOURCE);</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state,</div><div class='add'>+					   CAL_CAMERARX_PAD_FIRST_SOURCE);</div><div class='ctx'> 	*fmt = format-&gt;format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cal_camerarx_sd_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				    struct v4l2_subdev_state *state)</div><div class='add'>+static int cal_camerarx_sd_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				      struct v4l2_subdev_state *state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_subdev_format format = {</div><div class='ctx'> 		.which = state ? V4L2_SUBDEV_FORMAT_TRY</div><div class='hunk'>@@ -784,7 +782,6 @@ static const struct v4l2_subdev_video_ops cal_camerarx_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops cal_camerarx_pad_ops = {</div><div class='del'>-	.init_cfg = cal_camerarx_sd_init_cfg,</div><div class='ctx'> 	.enum_mbus_code = cal_camerarx_sd_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size = cal_camerarx_sd_enum_frame_size,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='hunk'>@@ -797,6 +794,10 @@ static const struct v4l2_subdev_ops cal_camerarx_subdev_ops = {</div><div class='ctx'> 	.pad = &amp;cal_camerarx_pad_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops cal_camerarx_internal_ops = {</div><div class='add'>+	.init_state = cal_camerarx_sd_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct media_entity_operations cal_camerarx_media_ops = {</div><div class='ctx'> 	.link_validate = v4l2_subdev_link_validate,</div><div class='ctx'> };</div><div class='hunk'>@@ -848,6 +849,7 @@ struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,</div><div class='ctx'> 	/* Initialize the V4L2 subdev and media entity. */</div><div class='ctx'> 	sd = &amp;phy-&gt;subdev;</div><div class='ctx'> 	v4l2_subdev_init(sd, &amp;cal_camerarx_subdev_ops);</div><div class='add'>+	sd-&gt;internal_ops = &amp;cal_camerarx_internal_ops;</div><div class='ctx'> 	sd-&gt;entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;</div><div class='ctx'> 	sd-&gt;flags = V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	snprintf(sd-&gt;name, sizeof(sd-&gt;name), "CAMERARX%u", instance);</div><div class='head'>diff --git a/drivers/media/platform/ti/cal/cal-video.c b/drivers/media/platform/ti/cal/cal-video.c<br/>index a8abcd0fee17..e1ba5dfc217e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/cal/cal-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/cal/cal-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/cal/cal-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/cal/cal-video.c</a></div><div class='hunk'>@@ -603,9 +603,10 @@ static int cal_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct cal_ctx *ctx = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned int size = ctx-&gt;v_fmt.fmt.pix.sizeimage;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (sizes[0] &lt; size)</div><div class='hunk'>@@ -697,7 +698,7 @@ static int cal_video_check_format(struct cal_ctx *ctx)</div><div class='ctx'> </div><div class='ctx'> 	state = v4l2_subdev_lock_and_get_active_state(&amp;ctx-&gt;phy-&gt;subdev);</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_pad_format(&amp;ctx-&gt;phy-&gt;subdev, state, remote_pad-&gt;index);</div><div class='add'>+	format = v4l2_subdev_state_get_format(state, remote_pad-&gt;index);</div><div class='ctx'> 	if (!format) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1009,7 +1010,7 @@ int cal_ctx_v4l2_init(struct cal_ctx *ctx)</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	q-&gt;lock = &amp;ctx-&gt;mutex;</div><div class='del'>-	q-&gt;min_buffers_needed = 3;</div><div class='add'>+	q-&gt;min_queued_buffers = 3;</div><div class='ctx'> 	q-&gt;dev = ctx-&gt;cal-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/ti/davinci/vpif_capture.c b/drivers/media/platform/ti/davinci/vpif_capture.c<br/>index 99fae8830c41..c31a5566fc5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/davinci/vpif_capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/davinci/vpif_capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/davinci/vpif_capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/davinci/vpif_capture.c</a></div><div class='hunk'>@@ -113,6 +113,7 @@ static int vpif_buffer_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	struct channel_obj *ch = vb2_get_drv_priv(vq);</div><div class='ctx'> 	struct common_obj *common = &amp;ch-&gt;common[VPIF_VIDEO_INDEX];</div><div class='ctx'> 	unsigned size = common-&gt;fmt.fmt.pix.sizeimage;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	vpif_dbg(2, debug, "vpif_buffer_setup\n");</div><div class='ctx'> </div><div class='hunk'>@@ -122,8 +123,8 @@ static int vpif_buffer_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		size = sizes[0];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	sizes[0] = size;</div><div class='hunk'>@@ -1428,7 +1429,7 @@ static int vpif_probe_complete(void)</div><div class='ctx'> 		q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 		q-&gt;buf_struct_size = sizeof(struct vpif_cap_buffer);</div><div class='ctx'> 		q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-		q-&gt;min_buffers_needed = 1;</div><div class='add'>+		q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 		q-&gt;lock = &amp;common-&gt;lock;</div><div class='ctx'> 		q-&gt;dev = vpif_dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/ti/davinci/vpif_display.c b/drivers/media/platform/ti/davinci/vpif_display.c<br/>index f8ec2991c667..02ede1fe12cb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/davinci/vpif_display.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/davinci/vpif_display.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/davinci/vpif_display.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/davinci/vpif_display.c</a></div><div class='hunk'>@@ -115,6 +115,7 @@ static int vpif_buffer_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 	struct channel_obj *ch = vb2_get_drv_priv(vq);</div><div class='ctx'> 	struct common_obj *common = &amp;ch-&gt;common[VPIF_VIDEO_INDEX];</div><div class='ctx'> 	unsigned size = common-&gt;fmt.fmt.pix.sizeimage;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes) {</div><div class='ctx'> 		if (sizes[0] &lt; size)</div><div class='hunk'>@@ -122,8 +123,8 @@ static int vpif_buffer_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		size = sizes[0];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 3)</div><div class='del'>-		*nbuffers = 3 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 3)</div><div class='add'>+		*nbuffers = 3 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	sizes[0] = size;</div><div class='hunk'>@@ -1168,7 +1169,7 @@ static int vpif_probe_complete(void)</div><div class='ctx'> 		q-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 		q-&gt;buf_struct_size = sizeof(struct vpif_disp_buffer);</div><div class='ctx'> 		q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-		q-&gt;min_buffers_needed = 1;</div><div class='add'>+		q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 		q-&gt;lock = &amp;common-&gt;lock;</div><div class='ctx'> 		q-&gt;dev = vpif_dev;</div><div class='ctx'> 		err = vb2_queue_init(q);</div><div class='head'>diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c<br/>index ada61391c8d2..59b30fc43144 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c</a></div><div class='hunk'>@@ -873,7 +873,7 @@ static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi)</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='ctx'> 	q-&gt;dev = dmaengine_get_dma_device(csi-&gt;dma.chan);</div><div class='ctx'> 	q-&gt;lock = &amp;csi-&gt;mutex;</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/platform/ti/omap/omap_vout.c b/drivers/media/platform/ti/omap/omap_vout.c<br/>index 4143274089c3..1c56b6a87ced 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap/omap_vout.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap/omap_vout.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap/omap_vout.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap/omap_vout.c</a></div><div class='hunk'>@@ -944,10 +944,11 @@ static int omap_vout_vb2_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 				     struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct omap_vout_device *vout = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	int size = vout-&gt;pix.sizeimage;</div><div class='ctx'> </div><div class='del'>-	if (is_rotation_enabled(vout) &amp;&amp; vq-&gt;num_buffers + *nbufs &gt; VRFB_NUM_BUFS) {</div><div class='del'>-		*nbufs = VRFB_NUM_BUFS - vq-&gt;num_buffers;</div><div class='add'>+	if (is_rotation_enabled(vout) &amp;&amp; q_num_bufs + *nbufs &gt; VRFB_NUM_BUFS) {</div><div class='add'>+		*nbufs = VRFB_NUM_BUFS - q_num_bufs;</div><div class='ctx'> 		if (*nbufs == 0)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1403,7 +1404,7 @@ static int __init omap_vout_setup_video_data(struct omap_vout_device *vout)</div><div class='ctx'> 	vq-&gt;ops = &amp;omap_vout_vb2_ops;</div><div class='ctx'> 	vq-&gt;mem_ops = &amp;vb2_dma_contig_memops;</div><div class='ctx'> 	vq-&gt;lock = &amp;vout-&gt;lock;</div><div class='del'>-	vq-&gt;min_buffers_needed = 1;</div><div class='add'>+	vq-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	vfd-&gt;queue = vq;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(vq);</div><div class='head'>diff --git a/drivers/media/platform/ti/omap3isp/ispccdc.c b/drivers/media/platform/ti/omap3isp/ispccdc.c<br/>index 2fe42aa91800..dd375c4e180d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispccdc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap3isp/ispccdc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispccdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispccdc.c</a></div><div class='hunk'>@@ -1948,8 +1948,7 @@ __ccdc_get_format(struct isp_ccdc_device *ccdc,</div><div class='ctx'> 		  unsigned int pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;ccdc-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;ccdc-&gt;formats[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -1960,8 +1959,8 @@ __ccdc_get_crop(struct isp_ccdc_device *ccdc,</div><div class='ctx'> 		enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;ccdc-&gt;subdev, sd_state,</div><div class='del'>-						CCDC_PAD_SOURCE_OF);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state,</div><div class='add'>+						  CCDC_PAD_SOURCE_OF);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;ccdc-&gt;crop;</div><div class='ctx'> }</div><div class='hunk'>@@ -1969,7 +1968,7 @@ __ccdc_get_crop(struct isp_ccdc_device *ccdc,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_try_format - Try video format on a pad</div><div class='ctx'>  * @ccdc: ISP CCDC device</div><div class='del'>- * @cfg : V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: Pad number</div><div class='ctx'>  * @fmt: Format</div><div class='ctx'>  */</div><div class='hunk'>@@ -2127,7 +2126,7 @@ static void ccdc_try_crop(struct isp_ccdc_device *ccdc,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd     : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg : V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code   : pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -2230,7 +2229,7 @@ static int ccdc_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_get_selection - Retrieve a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP CCDC V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangles are the crop rectangles on the output formatter</div><div class='hunk'>@@ -2274,7 +2273,7 @@ static int ccdc_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_set_selection - Set a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP CCDC V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangle is the actual crop rectangle on the output</div><div class='hunk'>@@ -2322,7 +2321,7 @@ static int ccdc_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_get_format - Retrieve the video format on a pad</div><div class='ctx'>  * @sd : ISP CCDC V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: Format</div><div class='ctx'>  *</div><div class='ctx'>  * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond</div><div class='hunk'>@@ -2346,7 +2345,7 @@ static int ccdc_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccdc_set_format - Set the video format on a pad</div><div class='ctx'>  * @sd : ISP CCDC V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: Format</div><div class='ctx'>  *</div><div class='ctx'>  * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond</div><div class='head'>diff --git a/drivers/media/platform/ti/omap3isp/ispccp2.c b/drivers/media/platform/ti/omap3isp/ispccp2.c<br/>index da5f0176ec78..1204ee221c9e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispccp2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap3isp/ispccp2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispccp2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispccp2.c</a></div><div class='hunk'>@@ -614,7 +614,7 @@ static const unsigned int ccp2_fmts[] = {</div><div class='ctx'> /*</div><div class='ctx'>  * __ccp2_get_format - helper function for getting ccp2 format</div><div class='ctx'>  * @ccp2  : Pointer to ISP CCP2 device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad   : pad number</div><div class='ctx'>  * @which : wanted subdev format</div><div class='ctx'>  * return format structure or NULL on error</div><div class='hunk'>@@ -625,8 +625,7 @@ __ccp2_get_format(struct isp_ccp2_device *ccp2,</div><div class='ctx'> 		  unsigned int pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;ccp2-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;ccp2-&gt;formats[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -634,7 +633,7 @@ __ccp2_get_format(struct isp_ccp2_device *ccp2,</div><div class='ctx'> /*</div><div class='ctx'>  * ccp2_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @ccp2  : Pointer to ISP CCP2 device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad   : pad num</div><div class='ctx'>  * @fmt   : pointer to v4l2 mbus format structure</div><div class='ctx'>  * @which : wanted subdev format</div><div class='hunk'>@@ -689,7 +688,7 @@ static void ccp2_try_format(struct isp_ccp2_device *ccp2,</div><div class='ctx'> /*</div><div class='ctx'>  * ccp2_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd     : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code   : pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -750,7 +749,7 @@ static int ccp2_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccp2_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd    : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt   : pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -772,7 +771,7 @@ static int ccp2_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * ccp2_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd    : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt   : pointer to v4l2 subdev format structure</div><div class='ctx'>  * returns zero</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/media/platform/ti/omap3isp/ispcsi2.c b/drivers/media/platform/ti/omap3isp/ispcsi2.c<br/>index 0f9a54b11f98..ae574e1b6528 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispcsi2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap3isp/ispcsi2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispcsi2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispcsi2.c</a></div><div class='hunk'>@@ -834,8 +834,7 @@ __csi2_get_format(struct isp_csi2_device *csi2,</div><div class='ctx'> 		  unsigned int pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;csi2-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;csi2-&gt;formats[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -894,7 +893,7 @@ csi2_try_format(struct isp_csi2_device *csi2,</div><div class='ctx'> /*</div><div class='ctx'>  * csi2_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd     : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code   : pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -968,7 +967,7 @@ static int csi2_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csi2_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -990,7 +989,7 @@ static int csi2_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * csi2_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/media/platform/ti/omap3isp/isppreview.c b/drivers/media/platform/ti/omap3isp/isppreview.c<br/>index 53aedec7990d..e383a57654de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/isppreview.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap3isp/isppreview.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/isppreview.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/isppreview.c</a></div><div class='hunk'>@@ -1684,8 +1684,7 @@ __preview_get_format(struct isp_prev_device *prev,</div><div class='ctx'> 		     unsigned int pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;prev-&gt;subdev, sd_state,</div><div class='del'>-						  pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;prev-&gt;formats[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -1696,8 +1695,7 @@ __preview_get_crop(struct isp_prev_device *prev,</div><div class='ctx'> 		   enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;prev-&gt;subdev, sd_state,</div><div class='del'>-						PREV_PAD_SINK);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, PREV_PAD_SINK);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;prev-&gt;crop;</div><div class='ctx'> }</div><div class='hunk'>@@ -1724,7 +1722,7 @@ static const unsigned int preview_output_fmts[] = {</div><div class='ctx'> /*</div><div class='ctx'>  * preview_try_format - Validate a format</div><div class='ctx'>  * @prev: ISP preview engine</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad: pad number</div><div class='ctx'>  * @fmt: format to be validated</div><div class='ctx'>  * @which: try/active format selector</div><div class='hunk'>@@ -1863,7 +1861,7 @@ static void preview_try_crop(struct isp_prev_device *prev,</div><div class='ctx'> /*</div><div class='ctx'>  * preview_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd     : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code   : pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -1924,7 +1922,7 @@ static int preview_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * preview_get_selection - Retrieve a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP preview V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangles are the crop rectangles on the sink pad.</div><div class='hunk'>@@ -1967,7 +1965,7 @@ static int preview_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * preview_set_selection - Set a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP preview V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangle is the actual crop rectangle on the sink pad.</div><div class='hunk'>@@ -2015,7 +2013,7 @@ static int preview_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * preview_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -2037,7 +2035,7 @@ static int preview_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * preview_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt: pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/media/platform/ti/omap3isp/ispresizer.c b/drivers/media/platform/ti/omap3isp/ispresizer.c<br/>index ed2fb0c7a57e..87d821b02e5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispresizer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/ti/omap3isp/ispresizer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/ti/omap3isp/ispresizer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/ti/omap3isp/ispresizer.c</a></div><div class='hunk'>@@ -109,7 +109,7 @@ static const struct isprsz_coef filter_coefs = {</div><div class='ctx'>  * __resizer_get_format - helper function for getting resizer format</div><div class='ctx'>  * @res   : pointer to resizer private structure</div><div class='ctx'>  * @pad   : pad number</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @which : wanted subdev format</div><div class='ctx'>  * return zero</div><div class='ctx'>  */</div><div class='hunk'>@@ -119,7 +119,7 @@ __resizer_get_format(struct isp_res_device *res,</div><div class='ctx'> 		     unsigned int pad, enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;res-&gt;subdev, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;res-&gt;formats[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -127,7 +127,7 @@ __resizer_get_format(struct isp_res_device *res,</div><div class='ctx'> /*</div><div class='ctx'>  * __resizer_get_crop - helper function for getting resizer crop rectangle</div><div class='ctx'>  * @res   : pointer to resizer private structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @which : wanted subdev crop rectangle</div><div class='ctx'>  */</div><div class='ctx'> static struct v4l2_rect *</div><div class='hunk'>@@ -136,8 +136,7 @@ __resizer_get_crop(struct isp_res_device *res,</div><div class='ctx'> 		   enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;res-&gt;subdev, sd_state,</div><div class='del'>-						RESZ_PAD_SINK);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, RESZ_PAD_SINK);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;res-&gt;crop.request;</div><div class='ctx'> }</div><div class='hunk'>@@ -1215,7 +1214,7 @@ static void resizer_try_crop(const struct v4l2_mbus_framefmt *sink,</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_get_selection - Retrieve a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP resizer V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangles are the crop rectangles on the sink pad.</div><div class='hunk'>@@ -1265,7 +1264,7 @@ static int resizer_get_selection(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_set_selection - Set a selection rectangle on a pad</div><div class='ctx'>  * @sd: ISP resizer V4L2 subdevice</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @sel: Selection rectangle</div><div class='ctx'>  *</div><div class='ctx'>  * The only supported rectangle is the actual crop rectangle on the sink pad.</div><div class='hunk'>@@ -1369,7 +1368,7 @@ static unsigned int resizer_max_in_width(struct isp_res_device *res)</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_try_format - Handle try format by pad subdev method</div><div class='ctx'>  * @res   : ISP resizer device</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @pad   : pad num</div><div class='ctx'>  * @fmt   : pointer to v4l2 format structure</div><div class='ctx'>  * @which : wanted subdev format</div><div class='hunk'>@@ -1413,7 +1412,7 @@ static void resizer_try_format(struct isp_res_device *res,</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_enum_mbus_code - Handle pixel format enumeration</div><div class='ctx'>  * @sd     : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @code   : pointer to v4l2_subdev_mbus_code_enum structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -1474,7 +1473,7 @@ static int resizer_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_get_format - Handle get format by pads subdev method</div><div class='ctx'>  * @sd    : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt   : pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='hunk'>@@ -1496,7 +1495,7 @@ static int resizer_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> /*</div><div class='ctx'>  * resizer_set_format - Handle set format by pads subdev method</div><div class='ctx'>  * @sd    : pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='add'>+ * @sd_state: V4L2 subdev state</div><div class='ctx'>  * @fmt   : pointer to v4l2 subdev format structure</div><div class='ctx'>  * return -EINVAL or zero on success</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/Kconfig b/drivers/media/platform/verisilicon/Kconfig<br/>index e65b836b9d78..24b927d8f182 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/Kconfig</a></div><div class='hunk'>@@ -8,7 +8,6 @@ config VIDEO_HANTRO</div><div class='ctx'> 	depends on V4L_MEM2MEM_DRIVERS</div><div class='ctx'> 	depends on VIDEO_DEV</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	select VIDEOBUF2_DMA_CONTIG</div><div class='ctx'> 	select VIDEOBUF2_VMALLOC</div><div class='ctx'> 	select V4L2_MEM2MEM_DEV</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h<br/>index 77aee9489516..6f5eb975d0e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro.h</a></div><div class='hunk'>@@ -328,6 +328,8 @@ struct hantro_vp9_decoded_buffer_info {</div><div class='ctx'> 	/* Info needed when the decoded frame serves as a reference frame. */</div><div class='ctx'> 	unsigned short width;</div><div class='ctx'> 	unsigned short height;</div><div class='add'>+	size_t chroma_offset;</div><div class='add'>+	size_t mv_offset;</div><div class='ctx'> 	u32 bit_depth : 4;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -469,11 +471,14 @@ hantro_get_dst_buf(struct hantro_ctx *ctx)</div><div class='ctx'> bool hantro_needs_postproc(const struct hantro_ctx *ctx,</div><div class='ctx'> 			   const struct hantro_fmt *fmt);</div><div class='ctx'> </div><div class='add'>+dma_addr_t</div><div class='add'>+hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index);</div><div class='add'>+</div><div class='ctx'> static inline dma_addr_t</div><div class='ctx'> hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)</div><div class='ctx'> {</div><div class='ctx'> 	if (hantro_needs_postproc(ctx, ctx-&gt;vpu_dst_fmt))</div><div class='del'>-		return ctx-&gt;postproc.dec_q[vb-&gt;index].dma;</div><div class='add'>+		return hantro_postproc_get_dec_buf_addr(ctx, vb-&gt;index);</div><div class='ctx'> 	return vb2_dma_contig_plane_dma_addr(vb, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -485,8 +490,8 @@ vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)</div><div class='ctx'> </div><div class='ctx'> void hantro_postproc_disable(struct hantro_ctx *ctx);</div><div class='ctx'> void hantro_postproc_enable(struct hantro_ctx *ctx);</div><div class='add'>+int hantro_postproc_init(struct hantro_ctx *ctx);</div><div class='ctx'> void hantro_postproc_free(struct hantro_ctx *ctx);</div><div class='del'>-int hantro_postproc_alloc(struct hantro_ctx *ctx);</div><div class='ctx'> int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,</div><div class='ctx'> 				   struct v4l2_frmsizeenum *fsize);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c<br/>index a9fa05ac56a9..db3df6cc4513 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_drv.c</a></div><div class='hunk'>@@ -235,8 +235,10 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)</div><div class='ctx'> 	 * The Kernel needs access to the JPEG destination buffer for the</div><div class='ctx'> 	 * JPEG encoder to fill in the JPEG headers.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!ctx-&gt;is_encoder)</div><div class='add'>+	if (!ctx-&gt;is_encoder) {</div><div class='ctx'> 		dst_vq-&gt;dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;</div><div class='add'>+		dst_vq-&gt;max_num_buffers = MAX_POSTPROC_BUFFERS;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	dst_vq-&gt;type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;</div><div class='ctx'> 	dst_vq-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='hunk'>@@ -905,6 +907,8 @@ static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)</div><div class='ctx'> </div><div class='ctx'> 	if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {</div><div class='ctx'> 		vpu-&gt;encoder = func;</div><div class='add'>+		v4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD);</div><div class='add'>+		v4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		vpu-&gt;decoder = func;</div><div class='ctx'> 		v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_g2.c b/drivers/media/platform/verisilicon/hantro_g2.c<br/>index ee5f14c5f8f2..b880a6849d58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_g2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2.c</a></div><div class='hunk'>@@ -8,6 +8,8 @@</div><div class='ctx'> #include "hantro_hw.h"</div><div class='ctx'> #include "hantro_g2_regs.h"</div><div class='ctx'> </div><div class='add'>+#define G2_ALIGN	16</div><div class='add'>+</div><div class='ctx'> void hantro_g2_check_idle(struct hantro_dev *vpu)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -42,3 +44,15 @@ irqreturn_t hantro_g2_irq(int irq, void *dev_id)</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	return ctx-&gt;dst_fmt.width * ctx-&gt;dst_fmt.height * ctx-&gt;bit_depth / 8;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	size_t cr_offset = hantro_g2_chroma_offset(ctx);</div><div class='add'>+</div><div class='add'>+	return ALIGN((cr_offset * 3) / 2, G2_ALIGN);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c<br/>index a9d4ac84a8d8..d3f8c33eb16c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c</a></div><div class='hunk'>@@ -8,20 +8,6 @@</div><div class='ctx'> #include "hantro_hw.h"</div><div class='ctx'> #include "hantro_g2_regs.h"</div><div class='ctx'> </div><div class='del'>-#define G2_ALIGN	16</div><div class='del'>-</div><div class='del'>-static size_t hantro_hevc_chroma_offset(struct hantro_ctx *ctx)</div><div class='del'>-{</div><div class='del'>-	return ctx-&gt;dst_fmt.width * ctx-&gt;dst_fmt.height * ctx-&gt;bit_depth / 8;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static size_t hantro_hevc_motion_vectors_offset(struct hantro_ctx *ctx)</div><div class='del'>-{</div><div class='del'>-	size_t cr_offset = hantro_hevc_chroma_offset(ctx);</div><div class='del'>-</div><div class='del'>-	return ALIGN((cr_offset * 3) / 2, G2_ALIGN);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void prepare_tile_info_buffer(struct hantro_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='hunk'>@@ -384,8 +370,8 @@ static int set_ref(struct hantro_ctx *ctx)</div><div class='ctx'> 	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='ctx'> 	struct vb2_v4l2_buffer *vb2_dst;</div><div class='ctx'> 	struct hantro_decoded_buffer *dst;</div><div class='del'>-	size_t cr_offset = hantro_hevc_chroma_offset(ctx);</div><div class='del'>-	size_t mv_offset = hantro_hevc_motion_vectors_offset(ctx);</div><div class='add'>+	size_t cr_offset = hantro_g2_chroma_offset(ctx);</div><div class='add'>+	size_t mv_offset = hantro_g2_motion_vectors_offset(ctx);</div><div class='ctx'> 	u32 max_ref_frames;</div><div class='ctx'> 	u16 dpb_longterm_e;</div><div class='ctx'> 	static const struct hantro_reg cur_poc[] = {</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c<br/>index 6fc4b555517f..342e543dee4c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c</a></div><div class='hunk'>@@ -16,8 +16,6 @@</div><div class='ctx'> #include "hantro_vp9.h"</div><div class='ctx'> #include "hantro_g2_regs.h"</div><div class='ctx'> </div><div class='del'>-#define G2_ALIGN 16</div><div class='del'>-</div><div class='ctx'> enum hantro_ref_frames {</div><div class='ctx'> 	INTRA_FRAME = 0,</div><div class='ctx'> 	LAST_FRAME = 1,</div><div class='hunk'>@@ -90,22 +88,6 @@ static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static size_t chroma_offset(const struct hantro_ctx *ctx,</div><div class='del'>-			    const struct v4l2_ctrl_vp9_frame *dec_params)</div><div class='del'>-{</div><div class='del'>-	int bytes_per_pixel = dec_params-&gt;bit_depth == 8 ? 1 : 2;</div><div class='del'>-</div><div class='del'>-	return ctx-&gt;src_fmt.width * ctx-&gt;src_fmt.height * bytes_per_pixel;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static size_t mv_offset(const struct hantro_ctx *ctx,</div><div class='del'>-			const struct v4l2_ctrl_vp9_frame *dec_params)</div><div class='del'>-{</div><div class='del'>-	size_t cr_offset = chroma_offset(ctx, dec_params);</div><div class='del'>-</div><div class='del'>-	return ALIGN((cr_offset * 3) / 2, G2_ALIGN);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct hantro_decoded_buffer *</div><div class='ctx'> get_ref_buf(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp)</div><div class='ctx'> {</div><div class='hunk'>@@ -156,11 +138,13 @@ static void config_output(struct hantro_ctx *ctx,</div><div class='ctx'> 	luma_addr = hantro_get_dec_buf_addr(ctx, &amp;dst-&gt;base.vb.vb2_buf);</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, G2_OUT_LUMA_ADDR, luma_addr);</div><div class='ctx'> </div><div class='del'>-	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);</div><div class='add'>+	chroma_addr = luma_addr + hantro_g2_chroma_offset(ctx);</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, G2_OUT_CHROMA_ADDR, chroma_addr);</div><div class='add'>+	dst-&gt;vp9.chroma_offset = hantro_g2_chroma_offset(ctx);</div><div class='ctx'> </div><div class='del'>-	mv_addr = luma_addr + mv_offset(ctx, dec_params);</div><div class='add'>+	mv_addr = luma_addr + hantro_g2_motion_vectors_offset(ctx);</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, G2_OUT_MV_ADDR, mv_addr);</div><div class='add'>+	dst-&gt;vp9.mv_offset = hantro_g2_motion_vectors_offset(ctx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct hantro_vp9_ref_reg {</div><div class='hunk'>@@ -195,7 +179,7 @@ static void config_ref(struct hantro_ctx *ctx,</div><div class='ctx'> 	luma_addr = hantro_get_dec_buf_addr(ctx, &amp;buf-&gt;base.vb.vb2_buf);</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, ref_reg-&gt;y_base, luma_addr);</div><div class='ctx'> </div><div class='del'>-	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);</div><div class='add'>+	chroma_addr = luma_addr + buf-&gt;vp9.chroma_offset;</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, ref_reg-&gt;c_base, chroma_addr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -238,7 +222,7 @@ static void config_ref_registers(struct hantro_ctx *ctx,</div><div class='ctx'> 	config_ref(ctx, dst, &amp;ref_regs[2], dec_params, dec_params-&gt;alt_frame_ts);</div><div class='ctx'> </div><div class='ctx'> 	mv_addr = hantro_get_dec_buf_addr(ctx, &amp;mv_ref-&gt;base.vb.vb2_buf) +</div><div class='del'>-		  mv_offset(ctx, dec_params);</div><div class='add'>+		  mv_ref-&gt;vp9.mv_offset;</div><div class='ctx'> 	hantro_write_addr(ctx-&gt;dev, G2_REF_MV_ADDR(0), mv_addr);</div><div class='ctx'> </div><div class='ctx'> 	hantro_reg_write(ctx-&gt;dev, &amp;vp9_last_sign_bias,</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h<br/>index 7f33f7b07ce4..9aec8a79acdc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_hw.h</a></div><div class='hunk'>@@ -40,6 +40,8 @@</div><div class='ctx'> </div><div class='ctx'> #define AV1_MAX_FRAME_BUF_COUNT	(V4L2_AV1_TOTAL_REFS_PER_FRAME + 1)</div><div class='ctx'> </div><div class='add'>+#define MAX_POSTPROC_BUFFERS	64</div><div class='add'>+</div><div class='ctx'> struct hantro_dev;</div><div class='ctx'> struct hantro_ctx;</div><div class='ctx'> struct hantro_buf;</div><div class='hunk'>@@ -336,7 +338,7 @@ struct hantro_av1_dec_hw_ctx {</div><div class='ctx'>  * @dec_q:		References buffers, in decoder format.</div><div class='ctx'>  */</div><div class='ctx'> struct hantro_postproc_ctx {</div><div class='del'>-	struct hantro_aux_buf dec_q[VB2_MAX_FRAME];</div><div class='add'>+	struct hantro_aux_buf dec_q[MAX_POSTPROC_BUFFERS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -519,6 +521,9 @@ hantro_av1_mv_size(unsigned int width, unsigned int height)</div><div class='ctx'> 	return ALIGN(num_sbs * 384, 16) * 2 + 512;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx);</div><div class='add'>+size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx);</div><div class='add'>+</div><div class='ctx'> int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);</div><div class='ctx'> int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);</div><div class='ctx'> void hantro_mpeg2_dec_copy_qtable(u8 *qtable,</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c b/drivers/media/platform/verisilicon/hantro_postproc.c<br/>index 64d6fb852ae9..41e93176300b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_postproc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_postproc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_postproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_postproc.c</a></div><div class='hunk'>@@ -177,9 +177,11 @@ static int hantro_postproc_g2_enum_framesizes(struct hantro_ctx *ctx,</div><div class='ctx'> void hantro_postproc_free(struct hantro_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = ctx-&gt;fh.m2m_ctx;</div><div class='add'>+	struct vb2_queue *queue = &amp;m2m_ctx-&gt;cap_q_ctx.q;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; VB2_MAX_FRAME; ++i) {</div><div class='add'>+	for (i = 0; i &lt; queue-&gt;max_num_buffers; ++i) {</div><div class='ctx'> 		struct hantro_aux_buf *priv = &amp;ctx-&gt;postproc.dec_q[i];</div><div class='ctx'> </div><div class='ctx'> 		if (priv-&gt;cpu) {</div><div class='hunk'>@@ -190,20 +192,17 @@ void hantro_postproc_free(struct hantro_ctx *ctx)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int hantro_postproc_alloc(struct hantro_ctx *ctx)</div><div class='add'>+static unsigned int hantro_postproc_buffer_size(struct hantro_ctx *ctx)</div><div class='ctx'> {</div><div class='del'>-	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='del'>-	struct v4l2_m2m_ctx *m2m_ctx = ctx-&gt;fh.m2m_ctx;</div><div class='del'>-	struct vb2_queue *cap_queue = &amp;m2m_ctx-&gt;cap_q_ctx.q;</div><div class='del'>-	unsigned int num_buffers = cap_queue-&gt;num_buffers;</div><div class='ctx'> 	struct v4l2_pix_format_mplane pix_mp;</div><div class='ctx'> 	const struct hantro_fmt *fmt;</div><div class='del'>-	unsigned int i, buf_size;</div><div class='add'>+	unsigned int buf_size;</div><div class='ctx'> </div><div class='ctx'> 	/* this should always pick native format */</div><div class='ctx'> 	fmt = hantro_get_default_fmt(ctx, false, ctx-&gt;bit_depth, HANTRO_AUTO_POSTPROC);</div><div class='ctx'> 	if (!fmt)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	v4l2_fill_pixfmt_mp(&amp;pix_mp, fmt-&gt;fourcc, ctx-&gt;src_fmt.width,</div><div class='ctx'> 			    ctx-&gt;src_fmt.height);</div><div class='ctx'> </div><div class='hunk'>@@ -221,23 +220,77 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)</div><div class='ctx'> 		buf_size += hantro_av1_mv_size(pix_mp.width,</div><div class='ctx'> 					       pix_mp.height);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; num_buffers; ++i) {</div><div class='del'>-		struct hantro_aux_buf *priv = &amp;ctx-&gt;postproc.dec_q[i];</div><div class='add'>+	return buf_size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int hantro_postproc_alloc(struct hantro_ctx *ctx, int index)</div><div class='add'>+{</div><div class='add'>+	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='add'>+	struct hantro_aux_buf *priv = &amp;ctx-&gt;postproc.dec_q[index];</div><div class='add'>+	unsigned int buf_size = hantro_postproc_buffer_size(ctx);</div><div class='add'>+</div><div class='add'>+	if (!buf_size)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The buffers on this queue are meant as intermediate</div><div class='add'>+	 * buffers for the decoder, so no mapping is needed.</div><div class='add'>+	 */</div><div class='add'>+	priv-&gt;attrs = DMA_ATTR_NO_KERNEL_MAPPING;</div><div class='add'>+	priv-&gt;cpu = dma_alloc_attrs(vpu-&gt;dev, buf_size, &amp;priv-&gt;dma,</div><div class='add'>+				    GFP_KERNEL, priv-&gt;attrs);</div><div class='add'>+	if (!priv-&gt;cpu)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	priv-&gt;size = buf_size;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		/*</div><div class='del'>-		 * The buffers on this queue are meant as intermediate</div><div class='del'>-		 * buffers for the decoder, so no mapping is needed.</div><div class='del'>-		 */</div><div class='del'>-		priv-&gt;attrs = DMA_ATTR_NO_KERNEL_MAPPING;</div><div class='del'>-		priv-&gt;cpu = dma_alloc_attrs(vpu-&gt;dev, buf_size, &amp;priv-&gt;dma,</div><div class='del'>-					    GFP_KERNEL, priv-&gt;attrs);</div><div class='del'>-		if (!priv-&gt;cpu)</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		priv-&gt;size = buf_size;</div><div class='add'>+int hantro_postproc_init(struct hantro_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_m2m_ctx *m2m_ctx = ctx-&gt;fh.m2m_ctx;</div><div class='add'>+	struct vb2_queue *cap_queue = &amp;m2m_ctx-&gt;cap_q_ctx.q;</div><div class='add'>+	unsigned int num_buffers = vb2_get_num_buffers(cap_queue);</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_buffers; i++) {</div><div class='add'>+		ret = hantro_postproc_alloc(ctx, i);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+dma_addr_t</div><div class='add'>+hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index)</div><div class='add'>+{</div><div class='add'>+	struct hantro_aux_buf *priv = &amp;ctx-&gt;postproc.dec_q[index];</div><div class='add'>+	unsigned int buf_size = hantro_postproc_buffer_size(ctx);</div><div class='add'>+	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;size &lt; buf_size &amp;&amp; priv-&gt;cpu) {</div><div class='add'>+		/* buffer is too small, release it */</div><div class='add'>+		dma_free_attrs(vpu-&gt;dev, priv-&gt;size, priv-&gt;cpu,</div><div class='add'>+			       priv-&gt;dma, priv-&gt;attrs);</div><div class='add'>+		priv-&gt;cpu = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;cpu) {</div><div class='add'>+		/* buffer not already allocated, try getting a new one */</div><div class='add'>+		ret = hantro_postproc_alloc(ctx, index);</div><div class='add'>+		if (ret)</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;cpu)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return priv-&gt;dma;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct hantro_dev *vpu = ctx-&gt;dev;</div><div class='head'>diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c<br/>index b3ae037a50f6..941fa23c211a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_v4l2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/verisilicon/hantro_v4l2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/verisilicon/hantro_v4l2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/verisilicon/hantro_v4l2.c</a></div><div class='hunk'>@@ -514,25 +514,14 @@ static int hantro_set_fmt_out(struct hantro_ctx *ctx,</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!ctx-&gt;is_encoder) {</div><div class='del'>-		struct vb2_queue *peer_vq;</div><div class='del'>-</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * In order to support dynamic resolution change,</div><div class='ctx'> 		 * the decoder admits a resolution change, as long</div><div class='del'>-		 * as the pixelformat remains. Can't be done if streaming.</div><div class='del'>-		 */</div><div class='del'>-		if (vb2_is_streaming(vq) || (vb2_is_busy(vq) &amp;&amp;</div><div class='del'>-		    pix_mp-&gt;pixelformat != ctx-&gt;src_fmt.pixelformat))</div><div class='del'>-			return -EBUSY;</div><div class='del'>-		/*</div><div class='del'>-		 * Since format change on the OUTPUT queue will reset</div><div class='del'>-		 * the CAPTURE queue, we can't allow doing so</div><div class='del'>-		 * when the CAPTURE queue has buffers allocated.</div><div class='add'>+		 * as the pixelformat remains.</div><div class='ctx'> 		 */</div><div class='del'>-		peer_vq = v4l2_m2m_get_vq(ctx-&gt;fh.m2m_ctx,</div><div class='del'>-					  V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);</div><div class='del'>-		if (vb2_is_busy(peer_vq))</div><div class='add'>+		if (vb2_is_streaming(vq) &amp;&amp; pix_mp-&gt;pixelformat != ctx-&gt;src_fmt.pixelformat) {</div><div class='ctx'> 			return -EBUSY;</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * The encoder doesn't admit a format change if</div><div class='hunk'>@@ -577,15 +566,8 @@ static int hantro_set_fmt_out(struct hantro_ctx *ctx,</div><div class='ctx'> static int hantro_set_fmt_cap(struct hantro_ctx *ctx,</div><div class='ctx'> 			      struct v4l2_pix_format_mplane *pix_mp)</div><div class='ctx'> {</div><div class='del'>-	struct vb2_queue *vq;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	/* Change not allowed if queue is busy. */</div><div class='del'>-	vq = v4l2_m2m_get_vq(ctx-&gt;fh.m2m_ctx,</div><div class='del'>-			     V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);</div><div class='del'>-	if (vb2_is_busy(vq))</div><div class='del'>-		return -EBUSY;</div><div class='del'>-</div><div class='ctx'> 	if (ctx-&gt;is_encoder) {</div><div class='ctx'> 		struct vb2_queue *peer_vq;</div><div class='ctx'> </div><div class='hunk'>@@ -785,6 +767,9 @@ const struct v4l2_ioctl_ops hantro_ioctl_ops = {</div><div class='ctx'> 	.vidioc_g_selection = vidioc_g_selection,</div><div class='ctx'> 	.vidioc_s_selection = vidioc_s_selection,</div><div class='ctx'> </div><div class='add'>+	.vidioc_decoder_cmd = v4l2_m2m_ioctl_stateless_decoder_cmd,</div><div class='add'>+	.vidioc_try_decoder_cmd = v4l2_m2m_ioctl_stateless_try_decoder_cmd,</div><div class='add'>+</div><div class='ctx'> 	.vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,</div><div class='ctx'> 	.vidioc_encoder_cmd = vidioc_encoder_cmd,</div><div class='ctx'> };</div><div class='hunk'>@@ -933,7 +918,7 @@ static int hantro_start_streaming(struct vb2_queue *q, unsigned int count)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (hantro_needs_postproc(ctx, ctx-&gt;vpu_dst_fmt)) {</div><div class='del'>-			ret = hantro_postproc_alloc(ctx);</div><div class='add'>+			ret = hantro_postproc_init(ctx);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				goto err_codec_exit;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/media/platform/video-mux.c b/drivers/media/platform/video-mux.c<br/>index 5de6b6694f53..31e9e92e723e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/video-mux.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/video-mux.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/video-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/video-mux.c</a></div><div class='hunk'>@@ -89,10 +89,10 @@ static int video_mux_link_setup(struct media_entity *entity,</div><div class='ctx'> </div><div class='ctx'> 		/* Propagate the active format to the source */</div><div class='ctx'> 		sd_state = v4l2_subdev_lock_and_get_active_state(sd);</div><div class='del'>-		source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-							       source_pad);</div><div class='del'>-		*source_mbusformat = *v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-								 vmux-&gt;active);</div><div class='add'>+		source_mbusformat = v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								 source_pad);</div><div class='add'>+		*source_mbusformat = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								   vmux-&gt;active);</div><div class='ctx'> 		v4l2_subdev_unlock_state(sd_state);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (vmux-&gt;active != local-&gt;index)</div><div class='hunk'>@@ -154,11 +154,11 @@ static int video_mux_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	struct media_pad *pad = &amp;vmux-&gt;pads[sdformat-&gt;pad];</div><div class='ctx'> 	u16 source_pad = sd-&gt;entity.num_pads - 1;</div><div class='ctx'> </div><div class='del'>-	mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, sdformat-&gt;pad);</div><div class='add'>+	mbusformat = v4l2_subdev_state_get_format(sd_state, sdformat-&gt;pad);</div><div class='ctx'> 	if (!mbusformat)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	source_mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, source_pad);</div><div class='add'>+	source_mbusformat = v4l2_subdev_state_get_format(sd_state, source_pad);</div><div class='ctx'> 	if (!source_mbusformat)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -268,8 +268,8 @@ static int video_mux_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	/* Source pad mirrors active sink pad, no limitations on sink pads */</div><div class='ctx'> 	if ((pad-&gt;flags &amp; MEDIA_PAD_FL_SOURCE) &amp;&amp; vmux-&gt;active &gt;= 0)</div><div class='del'>-		sdformat-&gt;format = *v4l2_subdev_get_pad_format(sd, sd_state,</div><div class='del'>-							       vmux-&gt;active);</div><div class='add'>+		sdformat-&gt;format = *v4l2_subdev_state_get_format(sd_state,</div><div class='add'>+								 vmux-&gt;active);</div><div class='ctx'> </div><div class='ctx'> 	*mbusformat = sdformat-&gt;format;</div><div class='ctx'> </div><div class='hunk'>@@ -282,8 +282,8 @@ static int video_mux_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int video_mux_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			      struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int video_mux_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct video_mux *vmux = v4l2_subdev_to_video_mux(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mbusformat;</div><div class='hunk'>@@ -292,7 +292,7 @@ static int video_mux_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> 	mutex_lock(&amp;vmux-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='del'>-		mbusformat = v4l2_subdev_get_pad_format(sd, sd_state, i);</div><div class='add'>+		mbusformat = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*mbusformat = video_mux_format_mbus_default;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -302,7 +302,6 @@ static int video_mux_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops video_mux_pad_ops = {</div><div class='del'>-	.init_cfg = video_mux_init_cfg,</div><div class='ctx'> 	.get_fmt = v4l2_subdev_get_fmt,</div><div class='ctx'> 	.set_fmt = video_mux_set_format,</div><div class='ctx'> };</div><div class='hunk'>@@ -312,6 +311,10 @@ static const struct v4l2_subdev_ops video_mux_subdev_ops = {</div><div class='ctx'> 	.video = &amp;video_mux_subdev_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops video_mux_internal_ops = {</div><div class='add'>+	.init_state = video_mux_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int video_mux_notify_bound(struct v4l2_async_notifier *notifier,</div><div class='ctx'> 				  struct v4l2_subdev *sd,</div><div class='ctx'> 				  struct v4l2_async_connection *asd)</div><div class='hunk'>@@ -400,6 +403,7 @@ static int video_mux_probe(struct platform_device *pdev)</div><div class='ctx'> 	platform_set_drvdata(pdev, vmux);</div><div class='ctx'> </div><div class='ctx'> 	v4l2_subdev_init(&amp;vmux-&gt;subdev, &amp;video_mux_subdev_ops);</div><div class='add'>+	vmux-&gt;subdev.internal_ops = &amp;video_mux_internal_ops;</div><div class='ctx'> 	snprintf(vmux-&gt;subdev.name, sizeof(vmux-&gt;subdev.name), "%pOFn", np);</div><div class='ctx'> 	vmux-&gt;subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='ctx'> 	vmux-&gt;subdev.dev = dev;</div><div class='head'>diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c b/drivers/media/platform/xilinx/xilinx-csi2rxss.c<br/>index 5b53745fe44e..f953d5474ae0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-csi2rxss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/xilinx/xilinx-csi2rxss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-csi2rxss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-csi2rxss.c</a></div><div class='hunk'>@@ -386,14 +386,6 @@ static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * xcsi2rxss_log_status - Logs the status of the CSI-2 Receiver</div><div class='del'>- * @sd: Pointer to V4L2 subdevice structure</div><div class='del'>- *</div><div class='del'>- * This function prints the current status of Xilinx MIPI CSI-2</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='ctx'> static int xcsi2rxss_log_status(struct v4l2_subdev *sd)</div><div class='ctx'> {</div><div class='ctx'> 	struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);</div><div class='hunk'>@@ -631,16 +623,6 @@ static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * xcsi2rxss_s_stream - It is used to start/stop the streaming.</div><div class='del'>- * @sd: V4L2 Sub device</div><div class='del'>- * @enable: Flag (True / False)</div><div class='del'>- *</div><div class='del'>- * This function controls the start or stop of streaming for the</div><div class='del'>- * Xilinx MIPI CSI-2 Rx Subsystem.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success, errors otherwise</div><div class='del'>- */</div><div class='ctx'> static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);</div><div class='hunk'>@@ -671,8 +653,7 @@ __xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;xcsi2rxss-&gt;subdev,</div><div class='del'>-						  sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;xcsi2rxss-&gt;format;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -680,18 +661,8 @@ __xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * xcsi2rxss_init_cfg - Initialise the pad format config to default</div><div class='del'>- * @sd: Pointer to V4L2 Sub device structure</div><div class='del'>- * @sd_state: Pointer to sub device state structure</div><div class='del'>- *</div><div class='del'>- * This function is used to initialize the pad format with the default</div><div class='del'>- * values.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='del'>-static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			      struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int xcsi2rxss_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='hunk'>@@ -699,7 +670,7 @@ static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;xcsi2rxss-&gt;lock);</div><div class='ctx'> 	for (i = 0; i &lt; XCSI_MEDIA_PADS; i++) {</div><div class='del'>-		format = v4l2_subdev_get_try_format(sd, sd_state, i);</div><div class='add'>+		format = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*format = xcsi2rxss-&gt;default_format;</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;xcsi2rxss-&gt;lock);</div><div class='hunk'>@@ -707,16 +678,6 @@ static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * xcsi2rxss_get_format - Get the pad format</div><div class='del'>- * @sd: Pointer to V4L2 Sub device structure</div><div class='del'>- * @sd_state: Pointer to sub device state structure</div><div class='del'>- * @fmt: Pointer to pad level media bus format</div><div class='del'>- *</div><div class='del'>- * This function is used to get the pad format information.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='ctx'> static int xcsi2rxss_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				struct v4l2_subdev_format *fmt)</div><div class='hunk'>@@ -732,19 +693,6 @@ static int xcsi2rxss_get_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * xcsi2rxss_set_format - This is used to set the pad format</div><div class='del'>- * @sd: Pointer to V4L2 Sub device structure</div><div class='del'>- * @sd_state: Pointer to sub device state structure</div><div class='del'>- * @fmt: Pointer to pad level media bus format</div><div class='del'>- *</div><div class='del'>- * This function is used to set the pad format. Since the pad format is fixed</div><div class='del'>- * in hardware, it can't be modified on run time. So when a format set is</div><div class='del'>- * requested by application, all parameters except the format type is saved</div><div class='del'>- * for the pad and the original pad format is sent back to the application.</div><div class='del'>- *</div><div class='del'>- * Return: 0 on success</div><div class='del'>- */</div><div class='ctx'> static int xcsi2rxss_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 				struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				struct v4l2_subdev_format *fmt)</div><div class='hunk'>@@ -789,14 +737,6 @@ static int xcsi2rxss_set_format(struct v4l2_subdev *sd,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * xcsi2rxss_enum_mbus_code - Handle pixel format enumeration</div><div class='del'>- * @sd: pointer to v4l2 subdev structure</div><div class='del'>- * @cfg: V4L2 subdev pad configuration</div><div class='del'>- * @code: pointer to v4l2_subdev_mbus_code_enum structure</div><div class='del'>- *</div><div class='del'>- * Return: -EINVAL or zero on success</div><div class='del'>- */</div><div class='ctx'> static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,</div><div class='ctx'> 				    struct v4l2_subdev_state *sd_state,</div><div class='ctx'> 				    struct v4l2_subdev_mbus_code_enum *code)</div><div class='hunk'>@@ -840,7 +780,6 @@ static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {</div><div class='del'>-	.init_cfg = xcsi2rxss_init_cfg,</div><div class='ctx'> 	.get_fmt = xcsi2rxss_get_format,</div><div class='ctx'> 	.set_fmt = xcsi2rxss_set_format,</div><div class='ctx'> 	.enum_mbus_code = xcsi2rxss_enum_mbus_code,</div><div class='hunk'>@@ -853,6 +792,10 @@ static const struct v4l2_subdev_ops xcsi2rxss_ops = {</div><div class='ctx'> 	.pad = &amp;xcsi2rxss_pad_ops</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops xcsi2rxss_internal_ops = {</div><div class='add'>+	.init_state = xcsi2rxss_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = xcsi2rxss-&gt;dev;</div><div class='hunk'>@@ -1030,6 +973,7 @@ static int xcsi2rxss_probe(struct platform_device *pdev)</div><div class='ctx'> 	/* Initialize V4L2 subdevice and media entity */</div><div class='ctx'> 	subdev = &amp;xcsi2rxss-&gt;subdev;</div><div class='ctx'> 	v4l2_subdev_init(subdev, &amp;xcsi2rxss_ops);</div><div class='add'>+	subdev-&gt;internal_ops = &amp;xcsi2rxss_internal_ops;</div><div class='ctx'> 	subdev-&gt;dev = dev;</div><div class='ctx'> 	strscpy(subdev-&gt;name, dev_name(dev), sizeof(subdev-&gt;name));</div><div class='ctx'> 	subdev-&gt;flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;</div><div class='head'>diff --git a/drivers/media/platform/xilinx/xilinx-tpg.c b/drivers/media/platform/xilinx/xilinx-tpg.c<br/>index 80353ca44402..e05e528ffc6f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-tpg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/xilinx/xilinx-tpg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-tpg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-tpg.c</a></div><div class='hunk'>@@ -256,8 +256,7 @@ __xtpg_get_pad_format(struct xtpg_device *xtpg,</div><div class='ctx'> {</div><div class='ctx'> 	switch (which) {</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_TRY:</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;xtpg-&gt;xvip.subdev,</div><div class='del'>-						  sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	case V4L2_SUBDEV_FORMAT_ACTIVE:</div><div class='ctx'> 		return &amp;xtpg-&gt;formats[pad];</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -326,7 +325,7 @@ static int xtpg_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(subdev, sd_state, fse-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(sd_state, fse-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fse-&gt;index || fse-&gt;code != format-&gt;code)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -354,11 +353,11 @@ static int xtpg_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)</div><div class='ctx'> 	struct xtpg_device *xtpg = to_tpg(subdev);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *format;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(subdev, fh-&gt;state, 0);</div><div class='add'>+	format = v4l2_subdev_state_get_format(fh-&gt;state, 0);</div><div class='ctx'> 	*format = xtpg-&gt;default_format;</div><div class='ctx'> </div><div class='ctx'> 	if (xtpg-&gt;npads == 2) {</div><div class='del'>-		format = v4l2_subdev_get_try_format(subdev, fh-&gt;state, 1);</div><div class='add'>+		format = v4l2_subdev_state_get_format(fh-&gt;state, 1);</div><div class='ctx'> 		*format = xtpg-&gt;default_format;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/platform/xilinx/xilinx-vip.c b/drivers/media/platform/xilinx/xilinx-vip.c<br/>index 5b214bf7f93a..f1574edd2b43 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-vip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/platform/xilinx/xilinx-vip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/platform/xilinx/xilinx-vip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/platform/xilinx/xilinx-vip.c</a></div><div class='hunk'>@@ -260,7 +260,7 @@ int xvip_enum_mbus_code(struct v4l2_subdev *subdev,</div><div class='ctx'> 	if (code-&gt;index)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(subdev, sd_state, code-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(sd_state, code-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	code-&gt;code = format-&gt;code;</div><div class='ctx'> </div><div class='hunk'>@@ -295,7 +295,7 @@ int xvip_enum_frame_size(struct v4l2_subdev *subdev,</div><div class='ctx'> 	if (fse-&gt;which == V4L2_SUBDEV_FORMAT_ACTIVE)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	format = v4l2_subdev_get_try_format(subdev, sd_state, fse-&gt;pad);</div><div class='add'>+	format = v4l2_subdev_state_get_format(sd_state, fse-&gt;pad);</div><div class='ctx'> </div><div class='ctx'> 	if (fse-&gt;index || fse-&gt;code != format-&gt;code)</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/media/rc/ir-hix5hd2.c b/drivers/media/rc/ir-hix5hd2.c<br/>index 0034f615b466..de5bb9a08ea4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/rc/ir-hix5hd2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/rc/ir-hix5hd2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/rc/ir-hix5hd2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/ir-hix5hd2.c</a></div><div class='hunk'>@@ -9,7 +9,9 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/syscon.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;media/rc-core.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -251,7 +253,6 @@ static int hix5hd2_ir_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct hix5hd2_ir_priv *priv;</div><div class='ctx'> 	struct device_node *node = pdev-&gt;dev.of_node;</div><div class='del'>-	const struct of_device_id *of_id;</div><div class='ctx'> 	const char *map_name;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -259,12 +260,11 @@ static int hix5hd2_ir_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (!priv)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	of_id = of_match_device(hix5hd2_ir_table, dev);</div><div class='del'>-	if (!of_id) {</div><div class='add'>+	priv-&gt;socdata = device_get_match_data(dev);</div><div class='add'>+	if (!priv-&gt;socdata) {</div><div class='ctx'> 		dev_err(dev, "Unable to initialize IR data\n");</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='del'>-	priv-&gt;socdata = of_id-&gt;data;</div><div class='ctx'> </div><div class='ctx'> 	priv-&gt;regmap = syscon_regmap_lookup_by_phandle(node,</div><div class='ctx'> 						       "hisilicon,power-syscon");</div><div class='head'>diff --git a/drivers/media/rc/meson-ir-tx.c b/drivers/media/rc/meson-ir-tx.c<br/>index 6355b79893fb..fded2c256f2a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/rc/meson-ir-tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/rc/meson-ir-tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/rc/meson-ir-tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/meson-ir-tx.c</a></div><div class='hunk'>@@ -305,7 +305,7 @@ static int meson_irtx_mod_clock_probe(struct meson_irtx *ir,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __init meson_irtx_probe(struct platform_device *pdev)</div><div class='add'>+static int meson_irtx_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct meson_irtx *ir;</div><div class='hunk'>@@ -333,20 +333,17 @@ static int __init meson_irtx_probe(struct platform_device *pdev)</div><div class='ctx'> 	spin_lock_init(&amp;ir-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 	ret = meson_irtx_mod_clock_probe(ir, &amp;clk_nr);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(dev, "modulator clock setup failed\n");</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "modulator clock setup failed\n");</div><div class='add'>+</div><div class='ctx'> 	meson_irtx_setup(ir, clk_nr);</div><div class='ctx'> </div><div class='ctx'> 	ret = devm_request_irq(dev, irq,</div><div class='ctx'> 			       meson_irtx_irqhandler,</div><div class='ctx'> 			       IRQF_TRIGGER_RISING,</div><div class='ctx'> 			       DRIVER_NAME, ir);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(dev, "irq request failed\n");</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	if (ret)</div><div class='add'>+		return dev_err_probe(dev, ret, "irq request failed\n");</div><div class='ctx'> </div><div class='ctx'> 	rc = rc_allocate_device(RC_DRIVER_IR_RAW_TX);</div><div class='ctx'> 	if (!rc)</div><div class='hunk'>@@ -360,25 +357,15 @@ static int __init meson_irtx_probe(struct platform_device *pdev)</div><div class='ctx'> 	rc-&gt;s_tx_carrier = meson_irtx_set_carrier;</div><div class='ctx'> 	rc-&gt;s_tx_duty_cycle = meson_irtx_set_duty_cycle;</div><div class='ctx'> </div><div class='del'>-	ret = rc_register_device(rc);</div><div class='add'>+	ret = devm_rc_register_device(dev, rc);</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='del'>-		dev_err(dev, "rc_dev registration failed\n");</div><div class='ctx'> 		rc_free_device(rc);</div><div class='del'>-		return ret;</div><div class='add'>+		return dev_err_probe(dev, ret, "rc_dev registration failed\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	platform_set_drvdata(pdev, rc);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void meson_irtx_remove(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	struct rc_dev *rc = platform_get_drvdata(pdev);</div><div class='del'>-</div><div class='del'>-	rc_unregister_device(rc);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct of_device_id meson_irtx_dt_match[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.compatible = "amlogic,meson-g12a-ir-tx",</div><div class='hunk'>@@ -388,14 +375,13 @@ static const struct of_device_id meson_irtx_dt_match[] = {</div><div class='ctx'> MODULE_DEVICE_TABLE(of, meson_irtx_dt_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver meson_irtx_pd = {</div><div class='del'>-	.remove_new = meson_irtx_remove,</div><div class='add'>+	.probe = meson_irtx_probe,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = DRIVER_NAME,</div><div class='ctx'> 		.of_match_table = meson_irtx_dt_match,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-module_platform_driver_probe(meson_irtx_pd, meson_irtx_probe);</div><div class='add'>+module_platform_driver(meson_irtx_pd);</div><div class='ctx'> </div><div class='ctx'> MODULE_DESCRIPTION("Meson IR TX driver");</div><div class='ctx'> MODULE_AUTHOR("Viktor Prutyanov &lt;viktor.prutyanov@phystech.edu&gt;");</div><div class='head'>diff --git a/drivers/media/rc/pwm-ir-tx.c b/drivers/media/rc/pwm-ir-tx.c<br/>index c5f37c03af9c..fe368aebbc13 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/rc/pwm-ir-tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/rc/pwm-ir-tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/rc/pwm-ir-tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/rc/pwm-ir-tx.c</a></div><div class='hunk'>@@ -10,6 +10,8 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/hrtimer.h&gt;</div><div class='add'>+#include &lt;linux/completion.h&gt;</div><div class='ctx'> #include &lt;media/rc-core.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define DRIVER_NAME	"pwm-ir-tx"</div><div class='hunk'>@@ -17,8 +19,14 @@</div><div class='ctx'> </div><div class='ctx'> struct pwm_ir {</div><div class='ctx'> 	struct pwm_device *pwm;</div><div class='del'>-	unsigned int carrier;</div><div class='del'>-	unsigned int duty_cycle;</div><div class='add'>+	struct hrtimer timer;</div><div class='add'>+	struct completion tx_done;</div><div class='add'>+	struct pwm_state *state;</div><div class='add'>+	u32 carrier;</div><div class='add'>+	u32 duty_cycle;</div><div class='add'>+	const unsigned int *txbuf;</div><div class='add'>+	unsigned int txbuf_len;</div><div class='add'>+	unsigned int txbuf_index;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id pwm_ir_of_match[] = {</div><div class='hunk'>@@ -49,8 +57,8 @@ static int pwm_ir_set_carrier(struct rc_dev *dev, u32 carrier)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pwm_ir_tx(struct rc_dev *dev, unsigned int *txbuf,</div><div class='del'>-		     unsigned int count)</div><div class='add'>+static int pwm_ir_tx_sleep(struct rc_dev *dev, unsigned int *txbuf,</div><div class='add'>+			   unsigned int count)</div><div class='ctx'> {</div><div class='ctx'> 	struct pwm_ir *pwm_ir = dev-&gt;priv;</div><div class='ctx'> 	struct pwm_device *pwm = pwm_ir-&gt;pwm;</div><div class='hunk'>@@ -68,7 +76,7 @@ static int pwm_ir_tx(struct rc_dev *dev, unsigned int *txbuf,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; count; i++) {</div><div class='ctx'> 		state.enabled = !(i % 2);</div><div class='del'>-		pwm_apply_state(pwm, &amp;state);</div><div class='add'>+		pwm_apply_might_sleep(pwm, &amp;state);</div><div class='ctx'> </div><div class='ctx'> 		edge = ktime_add_us(edge, txbuf[i]);</div><div class='ctx'> 		delta = ktime_us_delta(edge, ktime_get());</div><div class='hunk'>@@ -77,11 +85,67 @@ static int pwm_ir_tx(struct rc_dev *dev, unsigned int *txbuf,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	state.enabled = false;</div><div class='del'>-	pwm_apply_state(pwm, &amp;state);</div><div class='add'>+	pwm_apply_might_sleep(pwm, &amp;state);</div><div class='ctx'> </div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int pwm_ir_tx_atomic(struct rc_dev *dev, unsigned int *txbuf,</div><div class='add'>+			    unsigned int count)</div><div class='add'>+{</div><div class='add'>+	struct pwm_ir *pwm_ir = dev-&gt;priv;</div><div class='add'>+	struct pwm_device *pwm = pwm_ir-&gt;pwm;</div><div class='add'>+	struct pwm_state state;</div><div class='add'>+</div><div class='add'>+	pwm_init_state(pwm, &amp;state);</div><div class='add'>+</div><div class='add'>+	state.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, pwm_ir-&gt;carrier);</div><div class='add'>+	pwm_set_relative_duty_cycle(&amp;state, pwm_ir-&gt;duty_cycle, 100);</div><div class='add'>+</div><div class='add'>+	pwm_ir-&gt;txbuf = txbuf;</div><div class='add'>+	pwm_ir-&gt;txbuf_len = count;</div><div class='add'>+	pwm_ir-&gt;txbuf_index = 0;</div><div class='add'>+	pwm_ir-&gt;state = &amp;state;</div><div class='add'>+</div><div class='add'>+	hrtimer_start(&amp;pwm_ir-&gt;timer, 0, HRTIMER_MODE_REL);</div><div class='add'>+</div><div class='add'>+	wait_for_completion(&amp;pwm_ir-&gt;tx_done);</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum hrtimer_restart pwm_ir_timer(struct hrtimer *timer)</div><div class='add'>+{</div><div class='add'>+	struct pwm_ir *pwm_ir = container_of(timer, struct pwm_ir, timer);</div><div class='add'>+	ktime_t now;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If we happen to hit an odd latency spike, loop through the</div><div class='add'>+	 * pulses until we catch up.</div><div class='add'>+	 */</div><div class='add'>+	do {</div><div class='add'>+		u64 ns;</div><div class='add'>+</div><div class='add'>+		pwm_ir-&gt;state-&gt;enabled = !(pwm_ir-&gt;txbuf_index % 2);</div><div class='add'>+		pwm_apply_atomic(pwm_ir-&gt;pwm, pwm_ir-&gt;state);</div><div class='add'>+</div><div class='add'>+		if (pwm_ir-&gt;txbuf_index &gt;= pwm_ir-&gt;txbuf_len) {</div><div class='add'>+			complete(&amp;pwm_ir-&gt;tx_done);</div><div class='add'>+</div><div class='add'>+			return HRTIMER_NORESTART;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ns = US_TO_NS(pwm_ir-&gt;txbuf[pwm_ir-&gt;txbuf_index]);</div><div class='add'>+		hrtimer_add_expires_ns(timer, ns);</div><div class='add'>+</div><div class='add'>+		pwm_ir-&gt;txbuf_index++;</div><div class='add'>+</div><div class='add'>+		now = timer-&gt;base-&gt;get_time();</div><div class='add'>+	} while (hrtimer_get_expires_tv64(timer) &lt; now);</div><div class='add'>+</div><div class='add'>+	return HRTIMER_RESTART;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int pwm_ir_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pwm_ir *pwm_ir;</div><div class='hunk'>@@ -103,10 +167,19 @@ static int pwm_ir_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (!rcdev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	if (pwm_might_sleep(pwm_ir-&gt;pwm)) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev, "TX will not be accurate as PWM device might sleep\n");</div><div class='add'>+		rcdev-&gt;tx_ir = pwm_ir_tx_sleep;</div><div class='add'>+	} else {</div><div class='add'>+		init_completion(&amp;pwm_ir-&gt;tx_done);</div><div class='add'>+		hrtimer_init(&amp;pwm_ir-&gt;timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);</div><div class='add'>+		pwm_ir-&gt;timer.function = pwm_ir_timer;</div><div class='add'>+		rcdev-&gt;tx_ir = pwm_ir_tx_atomic;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rcdev-&gt;priv = pwm_ir;</div><div class='ctx'> 	rcdev-&gt;driver_name = DRIVER_NAME;</div><div class='ctx'> 	rcdev-&gt;device_name = DEVICE_NAME;</div><div class='del'>-	rcdev-&gt;tx_ir = pwm_ir_tx;</div><div class='ctx'> 	rcdev-&gt;s_tx_duty_cycle = pwm_ir_set_duty_cycle;</div><div class='ctx'> 	rcdev-&gt;s_tx_carrier = pwm_ir_set_carrier;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/Kconfig b/drivers/media/test-drivers/Kconfig<br/>index 459b433e9fae..5a5379524bde 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/Kconfig</a></div><div class='hunk'>@@ -12,7 +12,6 @@ config VIDEO_VIM2M</div><div class='ctx'> 	select VIDEOBUF2_VMALLOC</div><div class='ctx'> 	select V4L2_MEM2MEM_DEV</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	help</div><div class='ctx'> 	  This is a virtual test device for the memory-to-memory driver</div><div class='ctx'> 	  framework.</div><div class='head'>diff --git a/drivers/media/test-drivers/vicodec/Kconfig b/drivers/media/test-drivers/vicodec/Kconfig<br/>index a7a828eec2a4..4ea0689c3abe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vicodec/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vicodec/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vicodec/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vicodec/Kconfig</a></div><div class='hunk'>@@ -5,7 +5,6 @@ config VIDEO_VICODEC</div><div class='ctx'> 	select VIDEOBUF2_VMALLOC</div><div class='ctx'> 	select V4L2_MEM2MEM_DEV</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	help</div><div class='ctx'> 	  Driver for a Virtual Codec</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/vicodec/vicodec-core.c b/drivers/media/test-drivers/vicodec/vicodec-core.c<br/>index 6f0e20df74e9..e13f5452b927 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vicodec/vicodec-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vicodec/vicodec-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vicodec/vicodec-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vicodec/vicodec-core.c</a></div><div class='hunk'>@@ -1240,6 +1240,12 @@ static int vicodec_decoder_cmd(struct file *file, void *fh,</div><div class='ctx'> 	struct vicodec_ctx *ctx = file2ctx(file);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * This ioctl should not be used with a stateless codec that doesn't</div><div class='add'>+	 * support holding buffers and the associated flush command.</div><div class='add'>+	 */</div><div class='add'>+	WARN_ON(ctx-&gt;is_stateless);</div><div class='add'>+</div><div class='ctx'> 	ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='hunk'>@@ -1718,6 +1724,7 @@ static int queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 			V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE :</div><div class='ctx'> 			V4L2_BUF_TYPE_VIDEO_CAPTURE);</div><div class='ctx'> 	dst_vq-&gt;io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;</div><div class='add'>+	dst_vq-&gt;max_num_buffers = 64;</div><div class='ctx'> 	dst_vq-&gt;drv_priv = ctx;</div><div class='ctx'> 	dst_vq-&gt;buf_struct_size = sizeof(struct v4l2_m2m_buffer);</div><div class='ctx'> 	dst_vq-&gt;ops = &amp;vicodec_qops;</div><div class='hunk'>@@ -2025,7 +2032,7 @@ static const struct v4l2_m2m_ops m2m_ops = {</div><div class='ctx'> </div><div class='ctx'> static int register_instance(struct vicodec_dev *dev,</div><div class='ctx'> 			     struct vicodec_dev_instance *dev_instance,</div><div class='del'>-			     const char *name, bool is_enc)</div><div class='add'>+			     const char *name, bool is_enc, bool is_stateless)</div><div class='ctx'> {</div><div class='ctx'> 	struct video_device *vfd;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -2045,10 +2052,11 @@ static int register_instance(struct vicodec_dev *dev,</div><div class='ctx'> 	strscpy(vfd-&gt;name, name, sizeof(vfd-&gt;name));</div><div class='ctx'> 	vfd-&gt;device_caps = V4L2_CAP_STREAMING |</div><div class='ctx'> 		(multiplanar ? V4L2_CAP_VIDEO_M2M_MPLANE : V4L2_CAP_VIDEO_M2M);</div><div class='del'>-	if (is_enc) {</div><div class='add'>+	if (is_enc || is_stateless) {</div><div class='ctx'> 		v4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD);</div><div class='ctx'> 		v4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD);</div><div class='del'>-	} else {</div><div class='add'>+	}</div><div class='add'>+	if (!is_enc) {</div><div class='ctx'> 		v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);</div><div class='ctx'> 		v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2107,17 +2115,17 @@ static int vicodec_probe(struct platform_device *pdev)</div><div class='ctx'> 	platform_set_drvdata(pdev, dev);</div><div class='ctx'> </div><div class='ctx'> 	ret = register_instance(dev, &amp;dev-&gt;stateful_enc, "stateful-encoder",</div><div class='del'>-				true);</div><div class='add'>+				true, false);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unreg_dev;</div><div class='ctx'> </div><div class='ctx'> 	ret = register_instance(dev, &amp;dev-&gt;stateful_dec, "stateful-decoder",</div><div class='del'>-				false);</div><div class='add'>+				false, false);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unreg_sf_enc;</div><div class='ctx'> </div><div class='ctx'> 	ret = register_instance(dev, &amp;dev-&gt;stateless_dec, "stateless-decoder",</div><div class='del'>-				false);</div><div class='add'>+				false, true);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto unreg_sf_dec;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/vidtv/vidtv_pes.c b/drivers/media/test-drivers/vidtv/vidtv_pes.c<br/>index 782e5e7fbb02..6a360a0a3ccf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vidtv/vidtv_pes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vidtv/vidtv_pes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vidtv/vidtv_pes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vidtv/vidtv_pes.c</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #define pr_fmt(fmt) KBUILD_MODNAME ":%s, %d: " fmt, __func__, __LINE__</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/math64.h&gt;</div><div class='ctx'> #include &lt;linux/printk.h&gt;</div><div class='ctx'> #include &lt;linux/ratelimit.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/vimc/vimc-capture.c b/drivers/media/test-drivers/vimc/vimc-capture.c<br/>index aa944270e716..2a2d19d23bab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-capture.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vimc/vimc-capture.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-capture.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-capture.c</a></div><div class='hunk'>@@ -432,7 +432,7 @@ static struct vimc_ent_device *vimc_capture_add(struct vimc_device *vimc,</div><div class='ctx'> 	q-&gt;mem_ops = vimc_allocator == VIMC_ALLOCATOR_DMA_CONTIG</div><div class='ctx'> 		   ? &amp;vb2_dma_contig_memops : &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;lock = &amp;vcapture-&gt;lock;</div><div class='ctx'> 	q-&gt;dev = v4l2_dev-&gt;dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/vimc/vimc-debayer.c b/drivers/media/test-drivers/vimc/vimc-debayer.c<br/>index f671251fdf0e..d72ed086e00b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-debayer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vimc/vimc-debayer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-debayer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-debayer.c</a></div><div class='hunk'>@@ -150,18 +150,18 @@ static bool vimc_debayer_src_code_is_valid(u32 code)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vimc_debayer_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				 struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int vimc_debayer_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct vimc_debayer_device *vdebayer = v4l2_get_subdevdata(sd);</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	mf = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='add'>+	mf = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='ctx'> 	*mf = sink_fmt_default;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, i);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*mf = sink_fmt_default;</div><div class='ctx'> 		mf-&gt;code = vdebayer-&gt;src_code;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -221,7 +221,7 @@ static int vimc_debayer_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 	/* Get the current sink format */</div><div class='ctx'> 	fmt-&gt;format = fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY ?</div><div class='del'>-		      *v4l2_subdev_get_try_format(sd, sd_state, 0) :</div><div class='add'>+		      *v4l2_subdev_state_get_format(sd_state, 0) :</div><div class='ctx'> 		      vdebayer-&gt;sink_fmt;</div><div class='ctx'> </div><div class='ctx'> 	/* Set the right code for the source pad */</div><div class='hunk'>@@ -267,8 +267,8 @@ static int vimc_debayer_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 		sink_fmt = &amp;vdebayer-&gt;sink_fmt;</div><div class='ctx'> 		src_code = &amp;vdebayer-&gt;src_code;</div><div class='ctx'> 	} else {</div><div class='del'>-		sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);</div><div class='del'>-		src_code = &amp;v4l2_subdev_get_try_format(sd, sd_state, 1)-&gt;code;</div><div class='add'>+		sink_fmt = v4l2_subdev_state_get_format(sd_state, 0);</div><div class='add'>+		src_code = &amp;v4l2_subdev_state_get_format(sd_state, 1)-&gt;code;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -307,7 +307,6 @@ static int vimc_debayer_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops vimc_debayer_pad_ops = {</div><div class='del'>-	.init_cfg		= vimc_debayer_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= vimc_debayer_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size	= vimc_debayer_enum_frame_size,</div><div class='ctx'> 	.get_fmt		= vimc_debayer_get_fmt,</div><div class='hunk'>@@ -395,6 +394,10 @@ static const struct v4l2_subdev_ops vimc_debayer_ops = {</div><div class='ctx'> 	.video = &amp;vimc_debayer_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops vimc_debayer_internal_ops = {</div><div class='add'>+	.init_state = vimc_debayer_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static unsigned int vimc_debayer_get_val(const u8 *bytes,</div><div class='ctx'> 					 const unsigned int n_bytes)</div><div class='ctx'> {</div><div class='hunk'>@@ -595,6 +598,8 @@ static struct vimc_ent_device *vimc_debayer_add(struct vimc_device *vimc,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_free_hdl;</div><div class='ctx'> </div><div class='add'>+	vdebayer-&gt;sd.internal_ops = &amp;vimc_debayer_internal_ops;</div><div class='add'>+</div><div class='ctx'> 	vdebayer-&gt;ved.process_frame = vimc_debayer_process_frame;</div><div class='ctx'> 	vdebayer-&gt;ved.dev = vimc-&gt;mdev.dev;</div><div class='ctx'> 	vdebayer-&gt;mean_win_size = vimc_debayer_ctrl_mean_win_size.def;</div><div class='head'>diff --git a/drivers/media/test-drivers/vimc/vimc-scaler.c b/drivers/media/test-drivers/vimc/vimc-scaler.c<br/>index b671774e2784..afe13d6af321 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-scaler.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vimc/vimc-scaler.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-scaler.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-scaler.c</a></div><div class='hunk'>@@ -70,19 +70,19 @@ vimc_scaler_get_crop_bound_sink(const struct v4l2_mbus_framefmt *sink_fmt)</div><div class='ctx'> 	return r;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vimc_scaler_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-			     struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int vimc_scaler_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> 	struct v4l2_rect *r;</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, i);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*mf = fmt_default;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	r = v4l2_subdev_get_try_crop(sd, sd_state, VIMC_SCALER_SINK);</div><div class='add'>+	r = v4l2_subdev_state_get_crop(sd_state, VIMC_SCALER_SINK);</div><div class='ctx'> 	*r = crop_rect_default;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -138,7 +138,7 @@ vimc_scaler_pad_format(struct vimc_scaler_device *vscaler,</div><div class='ctx'> 		    enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_format(&amp;vscaler-&gt;sd, sd_state, pad);</div><div class='add'>+		return v4l2_subdev_state_get_format(sd_state, pad);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;vscaler-&gt;fmt[pad];</div><div class='ctx'> }</div><div class='hunk'>@@ -149,8 +149,7 @@ vimc_scaler_pad_crop(struct vimc_scaler_device *vscaler,</div><div class='ctx'> 		  enum v4l2_subdev_format_whence which)</div><div class='ctx'> {</div><div class='ctx'> 	if (which == V4L2_SUBDEV_FORMAT_TRY)</div><div class='del'>-		return v4l2_subdev_get_try_crop(&amp;vscaler-&gt;sd, sd_state,</div><div class='del'>-						VIMC_SCALER_SINK);</div><div class='add'>+		return v4l2_subdev_state_get_crop(sd_state, VIMC_SCALER_SINK);</div><div class='ctx'> 	else</div><div class='ctx'> 		return &amp;vscaler-&gt;crop_rect;</div><div class='ctx'> }</div><div class='hunk'>@@ -293,7 +292,6 @@ static int vimc_scaler_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops vimc_scaler_pad_ops = {</div><div class='del'>-	.init_cfg		= vimc_scaler_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= vimc_scaler_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size	= vimc_scaler_enum_frame_size,</div><div class='ctx'> 	.get_fmt		= vimc_scaler_get_fmt,</div><div class='hunk'>@@ -348,6 +346,10 @@ static const struct v4l2_subdev_ops vimc_scaler_ops = {</div><div class='ctx'> 	.video = &amp;vimc_scaler_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops vimc_scaler_internal_ops = {</div><div class='add'>+	.init_state = vimc_scaler_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static void vimc_scaler_fill_src_frame(const struct vimc_scaler_device *const vscaler,</div><div class='ctx'> 				    const u8 *const sink_frame)</div><div class='ctx'> {</div><div class='hunk'>@@ -425,6 +427,8 @@ static struct vimc_ent_device *vimc_scaler_add(struct vimc_device *vimc,</div><div class='ctx'> 		return ERR_PTR(ret);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	vscaler-&gt;sd.internal_ops = &amp;vimc_scaler_internal_ops;</div><div class='add'>+</div><div class='ctx'> 	vscaler-&gt;ved.process_frame = vimc_scaler_process_frame;</div><div class='ctx'> 	vscaler-&gt;ved.dev = vimc-&gt;mdev.dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/vimc/vimc-sensor.c b/drivers/media/test-drivers/vimc/vimc-sensor.c<br/>index 41a3dce2d714..5e34b1aed95e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-sensor.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vimc/vimc-sensor.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vimc/vimc-sensor.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vimc/vimc-sensor.c</a></div><div class='hunk'>@@ -41,15 +41,15 @@ static const struct v4l2_mbus_framefmt fmt_default = {</div><div class='ctx'> 	.colorspace = V4L2_COLORSPACE_SRGB,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int vimc_sensor_init_cfg(struct v4l2_subdev *sd,</div><div class='del'>-				struct v4l2_subdev_state *sd_state)</div><div class='add'>+static int vimc_sensor_init_state(struct v4l2_subdev *sd,</div><div class='add'>+				  struct v4l2_subdev_state *sd_state)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; sd-&gt;entity.num_pads; i++) {</div><div class='ctx'> 		struct v4l2_mbus_framefmt *mf;</div><div class='ctx'> </div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, i);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, i);</div><div class='ctx'> 		*mf = fmt_default;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -100,7 +100,7 @@ static int vimc_sensor_get_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> 				container_of(sd, struct vimc_sensor_device, sd);</div><div class='ctx'> </div><div class='ctx'> 	fmt-&gt;format = fmt-&gt;which == V4L2_SUBDEV_FORMAT_TRY ?</div><div class='del'>-		      *v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad) :</div><div class='add'>+		      *v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad) :</div><div class='ctx'> 		      vsensor-&gt;mbus_format;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -159,7 +159,7 @@ static int vimc_sensor_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> </div><div class='ctx'> 		mf = &amp;vsensor-&gt;mbus_format;</div><div class='ctx'> 	} else {</div><div class='del'>-		mf = v4l2_subdev_get_try_format(sd, sd_state, fmt-&gt;pad);</div><div class='add'>+		mf = v4l2_subdev_state_get_format(sd_state, fmt-&gt;pad);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set the new format */</div><div class='hunk'>@@ -183,7 +183,6 @@ static int vimc_sensor_set_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_pad_ops vimc_sensor_pad_ops = {</div><div class='del'>-	.init_cfg		= vimc_sensor_init_cfg,</div><div class='ctx'> 	.enum_mbus_code		= vimc_sensor_enum_mbus_code,</div><div class='ctx'> 	.enum_frame_size	= vimc_sensor_enum_frame_size,</div><div class='ctx'> 	.get_fmt		= vimc_sensor_get_fmt,</div><div class='hunk'>@@ -294,6 +293,10 @@ static const struct v4l2_subdev_ops vimc_sensor_ops = {</div><div class='ctx'> 	.video = &amp;vimc_sensor_video_ops,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct v4l2_subdev_internal_ops vimc_sensor_internal_ops = {</div><div class='add'>+	.init_state = vimc_sensor_init_state,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int vimc_sensor_s_ctrl(struct v4l2_ctrl *ctrl)</div><div class='ctx'> {</div><div class='ctx'> 	struct vimc_sensor_device *vsensor =</div><div class='hunk'>@@ -429,6 +432,8 @@ static struct vimc_ent_device *vimc_sensor_add(struct vimc_device *vimc,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_free_tpg;</div><div class='ctx'> </div><div class='add'>+	vsensor-&gt;sd.internal_ops = &amp;vimc_sensor_internal_ops;</div><div class='add'>+</div><div class='ctx'> 	vsensor-&gt;ved.process_frame = vimc_sensor_process_frame;</div><div class='ctx'> 	vsensor-&gt;ved.dev = vimc-&gt;mdev.dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/visl/Kconfig b/drivers/media/test-drivers/visl/Kconfig<br/>index 7508b904f196..37be9f267224 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/Kconfig</a></div><div class='hunk'>@@ -7,7 +7,6 @@ config VIDEO_VISL</div><div class='ctx'> 	select VIDEOBUF2_VMALLOC</div><div class='ctx'> 	select V4L2_MEM2MEM_DEV</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	select VIDEO_V4L2_TPG</div><div class='ctx'> 	help</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-core.c b/drivers/media/test-drivers/visl/visl-core.c<br/>index 9970dc739ca5..68dac896277b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-core.c</a></div><div class='hunk'>@@ -211,6 +211,27 @@ const struct visl_ctrls visl_hevc_ctrls = {</div><div class='ctx'> 	.num_ctrls = ARRAY_SIZE(visl_hevc_ctrl_descs),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct visl_ctrl_desc visl_av1_ctrl_descs[] = {</div><div class='add'>+	{</div><div class='add'>+		.cfg.id = V4L2_CID_STATELESS_AV1_FRAME,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.cfg.id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,</div><div class='add'>+		.cfg.dims = { V4L2_AV1_MAX_TILE_COUNT },</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.cfg.id = V4L2_CID_STATELESS_AV1_SEQUENCE,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.cfg.id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct visl_ctrls visl_av1_ctrls = {</div><div class='add'>+	.ctrls = visl_av1_ctrl_descs,</div><div class='add'>+	.num_ctrls = ARRAY_SIZE(visl_av1_ctrl_descs),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct v4l2_ctrl *visl_find_control(struct visl_ctx *ctx, u32 id)</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_ctrl_handler *hdl = &amp;ctx-&gt;hdl;</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-dec.c b/drivers/media/test-drivers/visl/visl-dec.c<br/>index 318d675e5668..f21260054e0f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-dec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-dec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-dec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-dec.c</a></div><div class='hunk'>@@ -13,12 +13,21 @@</div><div class='ctx'> #include "visl-trace-vp9.h"</div><div class='ctx'> #include "visl-trace-h264.h"</div><div class='ctx'> #include "visl-trace-hevc.h"</div><div class='add'>+#include "visl-trace-av1.h"</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='ctx'> #include &lt;media/v4l2-mem2mem.h&gt;</div><div class='ctx'> #include &lt;media/tpg/v4l2-tpg.h&gt;</div><div class='ctx'> </div><div class='add'>+#define LAST_BUF_IDX (V4L2_AV1_REF_LAST_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define LAST2_BUF_IDX (V4L2_AV1_REF_LAST2_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define LAST3_BUF_IDX (V4L2_AV1_REF_LAST3_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define GOLDEN_BUF_IDX (V4L2_AV1_REF_GOLDEN_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define BWD_BUF_IDX (V4L2_AV1_REF_BWDREF_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+#define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME)</div><div class='add'>+</div><div class='ctx'> static void *plane_vaddr(struct tpg_data *tpg, struct vb2_buffer *buf,</div><div class='ctx'> 			 u32 p, u32 bpl[TPG_MAX_PLANES], u32 h)</div><div class='ctx'> {</div><div class='hunk'>@@ -152,6 +161,55 @@ static void visl_get_ref_frames(struct visl_ctx *ctx, u8 *buf,</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	case VISL_CODEC_AV1: {</div><div class='add'>+		int idx_last = run-&gt;av1.frame-&gt;ref_frame_idx[LAST_BUF_IDX];</div><div class='add'>+		int idx_last2 = run-&gt;av1.frame-&gt;ref_frame_idx[LAST2_BUF_IDX];</div><div class='add'>+		int idx_last3 = run-&gt;av1.frame-&gt;ref_frame_idx[LAST3_BUF_IDX];</div><div class='add'>+		int idx_golden = run-&gt;av1.frame-&gt;ref_frame_idx[GOLDEN_BUF_IDX];</div><div class='add'>+		int idx_bwd = run-&gt;av1.frame-&gt;ref_frame_idx[BWD_BUF_IDX];</div><div class='add'>+		int idx_alt2 = run-&gt;av1.frame-&gt;ref_frame_idx[ALT2_BUF_IDX];</div><div class='add'>+		int idx_alt = run-&gt;av1.frame-&gt;ref_frame_idx[ALT_BUF_IDX];</div><div class='add'>+</div><div class='add'>+		struct vb2_buffer *ref_last =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_last]);</div><div class='add'>+		struct vb2_buffer *ref_last2 =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_last2]);</div><div class='add'>+		struct vb2_buffer *ref_last3 =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_last3]);</div><div class='add'>+		struct vb2_buffer *ref_golden =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_golden]);</div><div class='add'>+		struct vb2_buffer *ref_bwd =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_bwd]);</div><div class='add'>+		struct vb2_buffer *ref_alt2 =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_alt2]);</div><div class='add'>+		struct vb2_buffer *ref_alt =</div><div class='add'>+			vb2_find_buffer(cap_q, run-&gt;av1.frame-&gt;reference_frame_ts[idx_alt]);</div><div class='add'>+</div><div class='add'>+		scnprintf(buf, buflen,</div><div class='add'>+			  "ref_last_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_last2_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_last3_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_golden_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_bwd_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_alt2_ts: %llu, vb2_idx: %d\n"</div><div class='add'>+			  "ref_alt_ts: %llu, vb2_idx: %d\n",</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_last],</div><div class='add'>+			  ref_last ? ref_last-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_last2],</div><div class='add'>+			  ref_last2 ? ref_last2-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_last3],</div><div class='add'>+			  ref_last3 ? ref_last3-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_golden],</div><div class='add'>+			  ref_golden ? ref_golden-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_bwd],</div><div class='add'>+			  ref_bwd ? ref_bwd-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_alt2],</div><div class='add'>+			  ref_alt2 ? ref_alt2-&gt;index : -1,</div><div class='add'>+			  run-&gt;av1.frame-&gt;reference_frame_ts[idx_alt],</div><div class='add'>+			  ref_alt ? ref_alt-&gt;index : -1);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -287,16 +345,23 @@ static void visl_tpg_fill(struct visl_ctx *ctx, struct visl_run *run)</div><div class='ctx'> 	frame_dprintk(ctx-&gt;dev, run-&gt;dst-&gt;sequence, "%s\n", buf);</div><div class='ctx'> </div><div class='ctx'> 	len = 0;</div><div class='del'>-	for (i = 0; i &lt; out_q-&gt;num_buffers; i++) {</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(out_q); i++) {</div><div class='ctx'> 		char entry[] = "index: %u, state: %s, request_fd: %d, ";</div><div class='ctx'> 		u32 old_len = len;</div><div class='del'>-		char *q_status = visl_get_vb2_state(out_q-&gt;bufs[i]-&gt;state);</div><div class='add'>+		struct vb2_buffer *vb2;</div><div class='add'>+		char *q_status;</div><div class='add'>+</div><div class='add'>+		vb2 = vb2_get_buffer(out_q, i);</div><div class='add'>+		if (!vb2)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		q_status = visl_get_vb2_state(vb2-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 		len += scnprintf(&amp;buf[len], TPG_STR_BUF_SZ - len,</div><div class='ctx'> 				 entry, i, q_status,</div><div class='del'>-				 to_vb2_v4l2_buffer(out_q-&gt;bufs[i])-&gt;request_fd);</div><div class='add'>+				 to_vb2_v4l2_buffer(vb2)-&gt;request_fd);</div><div class='ctx'> </div><div class='del'>-		len += visl_fill_bytesused(to_vb2_v4l2_buffer(out_q-&gt;bufs[i]),</div><div class='add'>+		len += visl_fill_bytesused(to_vb2_v4l2_buffer(vb2),</div><div class='ctx'> 					   &amp;buf[len],</div><div class='ctx'> 					   TPG_STR_BUF_SZ - len);</div><div class='ctx'> </div><div class='hunk'>@@ -340,15 +405,22 @@ static void visl_tpg_fill(struct visl_ctx *ctx, struct visl_run *run)</div><div class='ctx'> 	frame_dprintk(ctx-&gt;dev, run-&gt;dst-&gt;sequence, "%s\n", buf);</div><div class='ctx'> </div><div class='ctx'> 	len = 0;</div><div class='del'>-	for (i = 0; i &lt; cap_q-&gt;num_buffers; i++) {</div><div class='add'>+	for (i = 0; i &lt; vb2_get_num_buffers(cap_q); i++) {</div><div class='ctx'> 		u32 old_len = len;</div><div class='del'>-		char *q_status = visl_get_vb2_state(cap_q-&gt;bufs[i]-&gt;state);</div><div class='add'>+		struct vb2_buffer *vb2;</div><div class='add'>+		char *q_status;</div><div class='add'>+</div><div class='add'>+		vb2 = vb2_get_buffer(cap_q, i);</div><div class='add'>+		if (!vb2)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		q_status = visl_get_vb2_state(vb2-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 		len += scnprintf(&amp;buf[len], TPG_STR_BUF_SZ - len,</div><div class='ctx'> 				 "index: %u, status: %s, timestamp: %llu, is_held: %d",</div><div class='del'>-				 cap_q-&gt;bufs[i]-&gt;index, q_status,</div><div class='del'>-				 cap_q-&gt;bufs[i]-&gt;timestamp,</div><div class='del'>-				 to_vb2_v4l2_buffer(cap_q-&gt;bufs[i])-&gt;is_held);</div><div class='add'>+				 vb2-&gt;index, q_status,</div><div class='add'>+				 vb2-&gt;timestamp,</div><div class='add'>+				 to_vb2_v4l2_buffer(vb2)-&gt;is_held);</div><div class='ctx'> </div><div class='ctx'> 		tpg_gen_text(&amp;ctx-&gt;tpg, basep, line++ * line_height, 16, &amp;buf[old_len]);</div><div class='ctx'> 		frame_dprintk(ctx-&gt;dev, run-&gt;dst-&gt;sequence, "%s", &amp;buf[old_len]);</div><div class='hunk'>@@ -410,7 +482,13 @@ static void visl_trace_ctrls(struct visl_ctx *ctx, struct visl_run *run)</div><div class='ctx'> 			trace_v4l2_hevc_dpb_entry(&amp;run-&gt;hevc.dpram-&gt;dpb[i]);</div><div class='ctx'> </div><div class='ctx'> 		trace_v4l2_hevc_pred_weight_table(&amp;run-&gt;hevc.spram-&gt;pred_weight_table);</div><div class='del'>-	break;</div><div class='add'>+		break;</div><div class='add'>+	case VISL_CODEC_AV1:</div><div class='add'>+		trace_v4l2_ctrl_av1_sequence(run-&gt;av1.seq);</div><div class='add'>+		trace_v4l2_ctrl_av1_frame(run-&gt;av1.frame);</div><div class='add'>+		trace_v4l2_ctrl_av1_film_grain(run-&gt;av1.grain);</div><div class='add'>+		trace_v4l2_ctrl_av1_tile_group_entry(run-&gt;av1.tge);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -469,6 +547,12 @@ void visl_device_run(void *priv)</div><div class='ctx'> 		run.hevc.sm = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);</div><div class='ctx'> 		run.hevc.dpram = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);</div><div class='ctx'> 		break;</div><div class='add'>+	case VISL_CODEC_AV1:</div><div class='add'>+		run.av1.seq = visl_find_control_data(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE);</div><div class='add'>+		run.av1.frame = visl_find_control_data(ctx, V4L2_CID_STATELESS_AV1_FRAME);</div><div class='add'>+		run.av1.tge = visl_find_control_data(ctx, V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY);</div><div class='add'>+		run.av1.grain = visl_find_control_data(ctx, V4L2_CID_STATELESS_AV1_FILM_GRAIN);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	frame_dprintk(ctx-&gt;dev, run.dst-&gt;sequence,</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-dec.h b/drivers/media/test-drivers/visl/visl-dec.h<br/>index 4a706a9de02e..c2c2ef3a8798 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-dec.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-dec.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-dec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-dec.h</a></div><div class='hunk'>@@ -45,6 +45,13 @@ struct visl_hevc_run {</div><div class='ctx'> 	const struct v4l2_ctrl_hevc_decode_params *dpram;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct visl_av1_run {</div><div class='add'>+	const struct v4l2_ctrl_av1_sequence *seq;</div><div class='add'>+	const struct v4l2_ctrl_av1_frame *frame;</div><div class='add'>+	const struct v4l2_ctrl_av1_tile_group_entry *tge;</div><div class='add'>+	const struct v4l2_ctrl_av1_film_grain *grain;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct visl_run {</div><div class='ctx'> 	struct vb2_v4l2_buffer	*src;</div><div class='ctx'> 	struct vb2_v4l2_buffer	*dst;</div><div class='hunk'>@@ -56,6 +63,7 @@ struct visl_run {</div><div class='ctx'> 		struct visl_vp9_run	vp9;</div><div class='ctx'> 		struct visl_h264_run	h264;</div><div class='ctx'> 		struct visl_hevc_run	hevc;</div><div class='add'>+		struct visl_av1_run	av1;</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-trace-av1.h b/drivers/media/test-drivers/visl/visl-trace-av1.h<br/>new file mode 100644<br/>index 000000000000..09f205de53df<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-trace-av1.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-trace-av1.h</a></div><div class='hunk'>@@ -0,0 +1,314 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+#if !defined(_VISL_TRACE_AV1_H_) || defined(TRACE_HEADER_MULTI_READ)</div><div class='add'>+#define _VISL_TRACE_AV1_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/tracepoint.h&gt;</div><div class='add'>+#include "visl.h"</div><div class='add'>+</div><div class='add'>+#undef TRACE_SYSTEM</div><div class='add'>+#define TRACE_SYSTEM visl_av1_controls</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(v4l2_ctrl_av1_seq_tmpl,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_sequence *s),</div><div class='add'>+	TP_ARGS(s),</div><div class='add'>+	TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_av1_sequence, s)),</div><div class='add'>+	TP_fast_assign(__entry-&gt;s = *s;),</div><div class='add'>+	TP_printk("\nflags %s\nseq_profile: %u\norder_hint_bits: %u\nbit_depth: %u\n"</div><div class='add'>+		  "max_frame_width_minus_1: %u\nmax_frame_height_minus_1: %u\n",</div><div class='add'>+		  __print_flags(__entry-&gt;s.flags, "|",</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_STILL_PICTURE, "STILL_PICTURE"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK, "USE_128X128_SUPERBLOCK"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_FILTER_INTRA, "ENABLE_FILTER_INTRA"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTRA_EDGE_FILTER, "ENABLE_INTRA_EDGE_FILTER"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_INTERINTRA_COMPOUND, "ENABLE_INTERINTRA_COMPOUND"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND, "ENABLE_MASKED_COMPOUND"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_WARPED_MOTION, "ENABLE_WARPED_MOTION"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_DUAL_FILTER, "ENABLE_DUAL_FILTER"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_ORDER_HINT, "ENABLE_ORDER_HINT"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_JNT_COMP, "ENABLE_JNT_COMP"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_REF_FRAME_MVS, "ENABLE_REF_FRAME_MVS"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_SUPERRES, "ENABLE_SUPERRES"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF, "ENABLE_CDEF"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_ENABLE_RESTORATION, "ENABLE_RESTORATION"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_MONO_CHROME, "MONO_CHROME"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_COLOR_RANGE, "COLOR_RANGE"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_SUBSAMPLING_X, "SUBSAMPLING_X"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_SUBSAMPLING_Y, "SUBSAMPLING_Y"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_FILM_GRAIN_PARAMS_PRESENT, "FILM_GRAIN_PARAMS_PRESENT"},</div><div class='add'>+		  {V4L2_AV1_SEQUENCE_FLAG_SEPARATE_UV_DELTA_Q, "SEPARATE_UV_DELTA_Q"}),</div><div class='add'>+		  __entry-&gt;s.seq_profile,</div><div class='add'>+		  __entry-&gt;s.order_hint_bits,</div><div class='add'>+		  __entry-&gt;s.bit_depth,</div><div class='add'>+		  __entry-&gt;s.max_frame_width_minus_1,</div><div class='add'>+		  __entry-&gt;s.max_frame_height_minus_1</div><div class='add'>+	)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(v4l2_ctrl_av1_tge_tmpl,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_tile_group_entry *t),</div><div class='add'>+	TP_ARGS(t),</div><div class='add'>+	TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_av1_tile_group_entry, t)),</div><div class='add'>+	TP_fast_assign(__entry-&gt;t = *t;),</div><div class='add'>+	TP_printk("\ntile_offset: %u\n tile_size: %u\n tile_row: %u\ntile_col: %u\n",</div><div class='add'>+		  __entry-&gt;t.tile_offset,</div><div class='add'>+		  __entry-&gt;t.tile_size,</div><div class='add'>+		  __entry-&gt;t.tile_row,</div><div class='add'>+		  __entry-&gt;t.tile_col</div><div class='add'>+	)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_frame *f),</div><div class='add'>+	TP_ARGS(f),</div><div class='add'>+	TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_av1_frame, f)),</div><div class='add'>+	TP_fast_assign(__entry-&gt;f = *f;),</div><div class='add'>+	TP_printk("\ntile_info.flags: %s\ntile_info.context_update_tile_id: %u\n"</div><div class='add'>+		  "tile_info.tile_cols: %u\ntile_info.tile_rows: %u\n"</div><div class='add'>+		  "tile_info.mi_col_starts: %s\ntile_info.mi_row_starts: %s\n"</div><div class='add'>+		  "tile_info.width_in_sbs_minus_1: %s\ntile_info.height_in_sbs_minus_1: %s\n"</div><div class='add'>+		  "tile_info.tile_size_bytes: %u\nquantization.flags: %s\n"</div><div class='add'>+		  "quantization.base_q_idx: %u\nquantization.delta_q_y_dc: %d\n"</div><div class='add'>+		  "quantization.delta_q_u_dc: %d\nquantization.delta_q_u_ac: %d\n"</div><div class='add'>+		  "quantization.delta_q_v_dc: %d\nquantization.delta_q_v_ac: %d\n"</div><div class='add'>+		  "quantization.qm_y: %u\nquantization.qm_u: %u\nquantization.qm_v: %u\n"</div><div class='add'>+		  "quantization.delta_q_res: %u\nsuperres_denom: %u\nsegmentation.flags: %s\n"</div><div class='add'>+		  "segmentation.last_active_seg_id: %u\nsegmentation.feature_enabled:%s\n"</div><div class='add'>+		  "loop_filter.flags: %s\nloop_filter.level: %s\nloop_filter.sharpness: %u\n"</div><div class='add'>+		  "loop_filter.ref_deltas: %s\nloop_filter.mode_deltas: %s\n"</div><div class='add'>+		  "loop_filter.delta_lf_res: %u\ncdef.damping_minus_3: %u\ncdef.bits: %u\n"</div><div class='add'>+		  "cdef.y_pri_strength: %s\ncdef.y_sec_strength: %s\n"</div><div class='add'>+		  "cdef.uv_pri_strength: %s\ncdef.uv_sec_strength:%s\nskip_mode_frame: %s\n"</div><div class='add'>+		  "primary_ref_frame: %u\nloop_restoration.flags: %s\n"</div><div class='add'>+		  "loop_restoration.lr_unit_shift: %u\nloop_restoration.lr_uv_shift: %u\n"</div><div class='add'>+		  "loop_restoration.frame_restoration_type: %s\n"</div><div class='add'>+		  "loop_restoration.loop_restoration_size: %s\nflags: %s\norder_hint: %u\n"</div><div class='add'>+		  "upscaled_width: %u\nframe_width_minus_1: %u\nframe_height_minus_1: %u\n"</div><div class='add'>+		  "render_width_minus_1: %u\nrender_height_minus_1: %u\ncurrent_frame_id: %u\n"</div><div class='add'>+		  "buffer_removal_time: %s\norder_hints: %s\nreference_frame_ts: %s\n"</div><div class='add'>+		  "ref_frame_idx: %s\nrefresh_frame_flags: %u\n",</div><div class='add'>+		  __print_flags(__entry-&gt;f.tile_info.flags, "|",</div><div class='add'>+		  {V4L2_AV1_TILE_INFO_FLAG_UNIFORM_TILE_SPACING, "UNIFORM_TILE_SPACING"}),</div><div class='add'>+		  __entry-&gt;f.tile_info.context_update_tile_id,</div><div class='add'>+		  __entry-&gt;f.tile_info.tile_cols,</div><div class='add'>+		  __entry-&gt;f.tile_info.tile_rows,</div><div class='add'>+		  __print_array(__entry-&gt;f.tile_info.mi_col_starts,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.tile_info.mi_col_starts),</div><div class='add'>+				sizeof(__entry-&gt;f.tile_info.mi_col_starts[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.tile_info.mi_row_starts,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.tile_info.mi_row_starts),</div><div class='add'>+				sizeof(__entry-&gt;f.tile_info.mi_row_starts[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.tile_info.width_in_sbs_minus_1,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.tile_info.width_in_sbs_minus_1),</div><div class='add'>+				sizeof(__entry-&gt;f.tile_info.width_in_sbs_minus_1[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.tile_info.height_in_sbs_minus_1,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.tile_info.height_in_sbs_minus_1),</div><div class='add'>+				sizeof(__entry-&gt;f.tile_info.height_in_sbs_minus_1[0])),</div><div class='add'>+		  __entry-&gt;f.tile_info.tile_size_bytes,</div><div class='add'>+		  __print_flags(__entry-&gt;f.quantization.flags, "|",</div><div class='add'>+		  {V4L2_AV1_QUANTIZATION_FLAG_DIFF_UV_DELTA, "DIFF_UV_DELTA"},</div><div class='add'>+		  {V4L2_AV1_QUANTIZATION_FLAG_USING_QMATRIX, "USING_QMATRIX"},</div><div class='add'>+		  {V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT, "DELTA_Q_PRESENT"}),</div><div class='add'>+		  __entry-&gt;f.quantization.base_q_idx,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_y_dc,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_u_dc,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_u_ac,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_v_dc,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_v_ac,</div><div class='add'>+		  __entry-&gt;f.quantization.qm_y,</div><div class='add'>+		  __entry-&gt;f.quantization.qm_u,</div><div class='add'>+		  __entry-&gt;f.quantization.qm_v,</div><div class='add'>+		  __entry-&gt;f.quantization.delta_q_res,</div><div class='add'>+		  __entry-&gt;f.superres_denom,</div><div class='add'>+		  __print_flags(__entry-&gt;f.segmentation.flags, "|",</div><div class='add'>+		  {V4L2_AV1_SEGMENTATION_FLAG_ENABLED, "ENABLED"},</div><div class='add'>+		  {V4L2_AV1_SEGMENTATION_FLAG_UPDATE_MAP, "UPDATE_MAP"},</div><div class='add'>+		  {V4L2_AV1_SEGMENTATION_FLAG_TEMPORAL_UPDATE, "TEMPORAL_UPDATE"},</div><div class='add'>+		  {V4L2_AV1_SEGMENTATION_FLAG_UPDATE_DATA, "UPDATE_DATA"},</div><div class='add'>+		  {V4L2_AV1_SEGMENTATION_FLAG_SEG_ID_PRE_SKIP, "SEG_ID_PRE_SKIP"}),</div><div class='add'>+		  __entry-&gt;f.segmentation.last_active_seg_id,</div><div class='add'>+		  __print_array(__entry-&gt;f.segmentation.feature_enabled,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.segmentation.feature_enabled),</div><div class='add'>+				sizeof(__entry-&gt;f.segmentation.feature_enabled[0])),</div><div class='add'>+		  __print_flags(__entry-&gt;f.loop_filter.flags, "|",</div><div class='add'>+		  {V4L2_AV1_LOOP_FILTER_FLAG_DELTA_ENABLED, "DELTA_ENABLED"},</div><div class='add'>+		  {V4L2_AV1_LOOP_FILTER_FLAG_DELTA_UPDATE, "DELTA_UPDATE"},</div><div class='add'>+		  {V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_PRESENT, "DELTA_LF_PRESENT"},</div><div class='add'>+		  {V4L2_AV1_LOOP_FILTER_FLAG_DELTA_LF_MULTI, "DELTA_LF_MULTI"}),</div><div class='add'>+		  __print_array(__entry-&gt;f.loop_filter.level,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.loop_filter.level),</div><div class='add'>+				sizeof(__entry-&gt;f.loop_filter.level[0])),</div><div class='add'>+		  __entry-&gt;f.loop_filter.sharpness,</div><div class='add'>+		  __print_array(__entry-&gt;f.loop_filter.ref_deltas,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.loop_filter.ref_deltas),</div><div class='add'>+				sizeof(__entry-&gt;f.loop_filter.ref_deltas[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.loop_filter.mode_deltas,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.loop_filter.mode_deltas),</div><div class='add'>+				sizeof(__entry-&gt;f.loop_filter.mode_deltas[0])),</div><div class='add'>+		  __entry-&gt;f.loop_filter.delta_lf_res,</div><div class='add'>+		  __entry-&gt;f.cdef.damping_minus_3,</div><div class='add'>+		  __entry-&gt;f.cdef.bits,</div><div class='add'>+		  __print_array(__entry-&gt;f.cdef.y_pri_strength,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.cdef.y_pri_strength),</div><div class='add'>+				sizeof(__entry-&gt;f.cdef.y_pri_strength[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.cdef.y_sec_strength,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.cdef.y_sec_strength),</div><div class='add'>+				sizeof(__entry-&gt;f.cdef.y_sec_strength[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.cdef.uv_pri_strength,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.cdef.uv_pri_strength),</div><div class='add'>+				sizeof(__entry-&gt;f.cdef.uv_pri_strength[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.cdef.uv_sec_strength,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.cdef.uv_sec_strength),</div><div class='add'>+				sizeof(__entry-&gt;f.cdef.uv_sec_strength[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.skip_mode_frame,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.skip_mode_frame),</div><div class='add'>+				sizeof(__entry-&gt;f.skip_mode_frame[0])),</div><div class='add'>+		  __entry-&gt;f.primary_ref_frame,</div><div class='add'>+		  __print_flags(__entry-&gt;f.loop_restoration.flags, "|",</div><div class='add'>+		  {V4L2_AV1_LOOP_RESTORATION_FLAG_USES_LR, "USES_LR"},</div><div class='add'>+		  {V4L2_AV1_LOOP_RESTORATION_FLAG_USES_CHROMA_LR, "USES_CHROMA_LR"}),</div><div class='add'>+		  __entry-&gt;f.loop_restoration.lr_unit_shift,</div><div class='add'>+		  __entry-&gt;f.loop_restoration.lr_uv_shift,</div><div class='add'>+		  __print_array(__entry-&gt;f.loop_restoration.frame_restoration_type,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.loop_restoration.frame_restoration_type),</div><div class='add'>+				sizeof(__entry-&gt;f.loop_restoration.frame_restoration_type[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.loop_restoration.loop_restoration_size,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.loop_restoration.loop_restoration_size),</div><div class='add'>+				sizeof(__entry-&gt;f.loop_restoration.loop_restoration_size[0])),</div><div class='add'>+		  __print_flags(__entry-&gt;f.flags, "|",</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_SHOW_FRAME, "SHOW_FRAME"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_SHOWABLE_FRAME, "SHOWABLE_FRAME"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_ERROR_RESILIENT_MODE, "ERROR_RESILIENT_MODE"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_DISABLE_CDF_UPDATE, "DISABLE_CDF_UPDATE"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_ALLOW_SCREEN_CONTENT_TOOLS, "ALLOW_SCREEN_CONTENT_TOOLS"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_FORCE_INTEGER_MV, "FORCE_INTEGER_MV"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_ALLOW_INTRABC, "ALLOW_INTRABC"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_USE_SUPERRES, "USE_SUPERRES"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV, "ALLOW_HIGH_PRECISION_MV"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE, "IS_MOTION_MODE_SWITCHABLE"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_USE_REF_FRAME_MVS, "USE_REF_FRAME_MVS"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_DISABLE_FRAME_END_UPDATE_CDF,</div><div class='add'>+		   "DISABLE_FRAME_END_UPDATE_CDF"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_ALLOW_WARPED_MOTION, "ALLOW_WARPED_MOTION"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT, "REFERENCE_SELECT"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_REDUCED_TX_SET, "REDUCED_TX_SET"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_SKIP_MODE_ALLOWED, "SKIP_MODE_ALLOWED"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT, "SKIP_MODE_PRESENT"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_FRAME_SIZE_OVERRIDE, "FRAME_SIZE_OVERRIDE"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_BUFFER_REMOVAL_TIME_PRESENT, "BUFFER_REMOVAL_TIME_PRESENT"},</div><div class='add'>+		  {V4L2_AV1_FRAME_FLAG_FRAME_REFS_SHORT_SIGNALING, "FRAME_REFS_SHORT_SIGNALING"}),</div><div class='add'>+		  __entry-&gt;f.order_hint,</div><div class='add'>+		  __entry-&gt;f.upscaled_width,</div><div class='add'>+		  __entry-&gt;f.frame_width_minus_1,</div><div class='add'>+		  __entry-&gt;f.frame_height_minus_1,</div><div class='add'>+		  __entry-&gt;f.render_width_minus_1,</div><div class='add'>+		  __entry-&gt;f.render_height_minus_1,</div><div class='add'>+		  __entry-&gt;f.current_frame_id,</div><div class='add'>+		  __print_array(__entry-&gt;f.buffer_removal_time,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.buffer_removal_time),</div><div class='add'>+				sizeof(__entry-&gt;f.buffer_removal_time[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.order_hints,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.order_hints),</div><div class='add'>+				sizeof(__entry-&gt;f.order_hints[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.reference_frame_ts,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.reference_frame_ts),</div><div class='add'>+				sizeof(__entry-&gt;f.reference_frame_ts[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.ref_frame_idx,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.ref_frame_idx),</div><div class='add'>+				sizeof(__entry-&gt;f.ref_frame_idx[0])),</div><div class='add'>+		  __entry-&gt;f.refresh_frame_flags</div><div class='add'>+	)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+</div><div class='add'>+DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_film_grain *f),</div><div class='add'>+	TP_ARGS(f),</div><div class='add'>+	TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_av1_film_grain, f)),</div><div class='add'>+	TP_fast_assign(__entry-&gt;f = *f;),</div><div class='add'>+	TP_printk("\nflags %s\ncr_mult: %u\ngrain_seed: %u\n"</div><div class='add'>+		  "film_grain_params_ref_idx: %u\nnum_y_points: %u\npoint_y_value: %s\n"</div><div class='add'>+		  "point_y_scaling: %s\nnum_cb_points: %u\npoint_cb_value: %s\n"</div><div class='add'>+		  "point_cb_scaling: %s\nnum_cr_points: %u\npoint_cr_value: %s\n"</div><div class='add'>+		  "point_cr_scaling: %s\ngrain_scaling_minus_8: %u\nar_coeff_lag: %u\n"</div><div class='add'>+		  "ar_coeffs_y_plus_128: %s\nar_coeffs_cb_plus_128: %s\n"</div><div class='add'>+		  "ar_coeffs_cr_plus_128: %s\nar_coeff_shift_minus_6: %u\n"</div><div class='add'>+		  "grain_scale_shift: %u\ncb_mult: %u\ncb_luma_mult: %u\ncr_luma_mult: %u\n"</div><div class='add'>+		  "cb_offset: %u\ncr_offset: %u\n",</div><div class='add'>+		  __print_flags(__entry-&gt;f.flags, "|",</div><div class='add'>+		  {V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN, "APPLY_GRAIN"},</div><div class='add'>+		  {V4L2_AV1_FILM_GRAIN_FLAG_UPDATE_GRAIN, "UPDATE_GRAIN"},</div><div class='add'>+		  {V4L2_AV1_FILM_GRAIN_FLAG_CHROMA_SCALING_FROM_LUMA, "CHROMA_SCALING_FROM_LUMA"},</div><div class='add'>+		  {V4L2_AV1_FILM_GRAIN_FLAG_OVERLAP, "OVERLAP"},</div><div class='add'>+		  {V4L2_AV1_FILM_GRAIN_FLAG_CLIP_TO_RESTRICTED_RANGE, "CLIP_TO_RESTRICTED_RANGE"}),</div><div class='add'>+		  __entry-&gt;f.cr_mult,</div><div class='add'>+		  __entry-&gt;f.grain_seed,</div><div class='add'>+		  __entry-&gt;f.film_grain_params_ref_idx,</div><div class='add'>+		  __entry-&gt;f.num_y_points,</div><div class='add'>+		  __print_array(__entry-&gt;f.point_y_value,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_y_value),</div><div class='add'>+				sizeof(__entry-&gt;f.point_y_value[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.point_y_scaling,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_y_scaling),</div><div class='add'>+				sizeof(__entry-&gt;f.point_y_scaling[0])),</div><div class='add'>+		  __entry-&gt;f.num_cb_points,</div><div class='add'>+		  __print_array(__entry-&gt;f.point_cb_value,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_cb_value),</div><div class='add'>+				sizeof(__entry-&gt;f.point_cb_value[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.point_cb_scaling,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_cb_scaling),</div><div class='add'>+				sizeof(__entry-&gt;f.point_cb_scaling[0])),</div><div class='add'>+		  __entry-&gt;f.num_cr_points,</div><div class='add'>+		  __print_array(__entry-&gt;f.point_cr_value,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_cr_value),</div><div class='add'>+				sizeof(__entry-&gt;f.point_cr_value[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.point_cr_scaling,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.point_cr_scaling),</div><div class='add'>+				sizeof(__entry-&gt;f.point_cr_scaling[0])),</div><div class='add'>+		  __entry-&gt;f.grain_scaling_minus_8,</div><div class='add'>+		  __entry-&gt;f.ar_coeff_lag,</div><div class='add'>+		  __print_array(__entry-&gt;f.ar_coeffs_y_plus_128,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.ar_coeffs_y_plus_128),</div><div class='add'>+				sizeof(__entry-&gt;f.ar_coeffs_y_plus_128[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.ar_coeffs_cb_plus_128,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.ar_coeffs_cb_plus_128),</div><div class='add'>+				sizeof(__entry-&gt;f.ar_coeffs_cb_plus_128[0])),</div><div class='add'>+		  __print_array(__entry-&gt;f.ar_coeffs_cr_plus_128,</div><div class='add'>+				ARRAY_SIZE(__entry-&gt;f.ar_coeffs_cr_plus_128),</div><div class='add'>+				sizeof(__entry-&gt;f.ar_coeffs_cr_plus_128[0])),</div><div class='add'>+		  __entry-&gt;f.ar_coeff_shift_minus_6,</div><div class='add'>+		  __entry-&gt;f.grain_scale_shift,</div><div class='add'>+		  __entry-&gt;f.cb_mult,</div><div class='add'>+		  __entry-&gt;f.cb_luma_mult,</div><div class='add'>+		  __entry-&gt;f.cr_luma_mult,</div><div class='add'>+		  __entry-&gt;f.cb_offset,</div><div class='add'>+		  __entry-&gt;f.cr_offset</div><div class='add'>+	)</div><div class='add'>+)</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(v4l2_ctrl_av1_seq_tmpl, v4l2_ctrl_av1_sequence,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_sequence *s),</div><div class='add'>+	TP_ARGS(s)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(v4l2_ctrl_av1_frame_tmpl, v4l2_ctrl_av1_frame,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_frame *f),</div><div class='add'>+	TP_ARGS(f)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(v4l2_ctrl_av1_tge_tmpl, v4l2_ctrl_av1_tile_group_entry,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_tile_group_entry *t),</div><div class='add'>+	TP_ARGS(t)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+DEFINE_EVENT(v4l2_ctrl_av1_film_grain_tmpl, v4l2_ctrl_av1_film_grain,</div><div class='add'>+	TP_PROTO(const struct v4l2_ctrl_av1_film_grain *f),</div><div class='add'>+	TP_ARGS(f)</div><div class='add'>+);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#undef TRACE_INCLUDE_PATH</div><div class='add'>+#undef TRACE_INCLUDE_FILE</div><div class='add'>+#define TRACE_INCLUDE_PATH ../../drivers/media/test-drivers/visl</div><div class='add'>+#define TRACE_INCLUDE_FILE visl-trace-av1</div><div class='add'>+#include &lt;trace/define_trace.h&gt;</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-trace-points.c b/drivers/media/test-drivers/visl/visl-trace-points.c<br/>index f7b866534f1e..321ff732c682 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-trace-points.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-trace-points.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-trace-points.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-trace-points.c</a></div><div class='hunk'>@@ -8,3 +8,4 @@</div><div class='ctx'> #include "visl-trace-vp9.h"</div><div class='ctx'> #include "visl-trace-h264.h"</div><div class='ctx'> #include "visl-trace-hevc.h"</div><div class='add'>+#include "visl-trace-av1.h"</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-video.c b/drivers/media/test-drivers/visl/visl-video.c<br/>index 7cac6a6456eb..b9a4b44bd0ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-video.c</a></div><div class='hunk'>@@ -40,6 +40,9 @@ static void visl_set_current_codec(struct visl_ctx *ctx)</div><div class='ctx'> 	case V4L2_PIX_FMT_HEVC_SLICE:</div><div class='ctx'> 		ctx-&gt;current_codec = VISL_CODEC_HEVC;</div><div class='ctx'> 		break;</div><div class='add'>+	case V4L2_PIX_FMT_AV1_FRAME:</div><div class='add'>+		ctx-&gt;current_codec = VISL_CODEC_AV1;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dprintk(ctx-&gt;dev, "Warning: unsupported fourcc: %d\n", fourcc);</div><div class='ctx'> 		ctx-&gt;current_codec = VISL_CODEC_NONE;</div><div class='hunk'>@@ -218,6 +221,21 @@ const struct visl_coded_format_desc visl_coded_fmts[] = {</div><div class='ctx'> 		.num_decoded_fmts = ARRAY_SIZE(visl_decoded_fmts),</div><div class='ctx'> 		.decoded_fmts = visl_decoded_fmts,</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+		.pixelformat = V4L2_PIX_FMT_AV1_FRAME,</div><div class='add'>+		.frmsize = {</div><div class='add'>+			.min_width = 64,</div><div class='add'>+			.max_width = 4096,</div><div class='add'>+			.step_width = 1,</div><div class='add'>+			.min_height = 64,</div><div class='add'>+			.max_height = 2304,</div><div class='add'>+			.step_height = 1,</div><div class='add'>+		},</div><div class='add'>+		.ctrls = &amp;visl_av1_ctrls,</div><div class='add'>+		.num_decoded_fmts = ARRAY_SIZE(visl_decoded_fmts),</div><div class='add'>+		.decoded_fmts = visl_decoded_fmts,</div><div class='add'>+	},</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const size_t num_coded_fmts = ARRAY_SIZE(visl_coded_fmts);</div><div class='hunk'>@@ -525,6 +543,9 @@ const struct v4l2_ioctl_ops visl_ioctl_ops = {</div><div class='ctx'> 	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,</div><div class='ctx'> 	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,</div><div class='ctx'> </div><div class='add'>+	.vidioc_decoder_cmd		= v4l2_m2m_ioctl_stateless_decoder_cmd,</div><div class='add'>+	.vidioc_try_decoder_cmd		= v4l2_m2m_ioctl_stateless_try_decoder_cmd,</div><div class='add'>+</div><div class='ctx'> 	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,</div><div class='ctx'> 	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl-video.h b/drivers/media/test-drivers/visl/visl-video.h<br/>index 27ad70a558db..92e274894c20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-video.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl-video.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl-video.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl-video.h</a></div><div class='hunk'>@@ -17,6 +17,7 @@ extern const struct visl_ctrls visl_vp8_ctrls;</div><div class='ctx'> extern const struct visl_ctrls visl_vp9_ctrls;</div><div class='ctx'> extern const struct visl_ctrls visl_h264_ctrls;</div><div class='ctx'> extern const struct visl_ctrls visl_hevc_ctrls;</div><div class='add'>+extern const struct visl_ctrls visl_av1_ctrls;</div><div class='ctx'> </div><div class='ctx'> int visl_queue_init(void *priv, struct vb2_queue *src_vq,</div><div class='ctx'> 		    struct vb2_queue *dst_vq);</div><div class='head'>diff --git a/drivers/media/test-drivers/visl/visl.h b/drivers/media/test-drivers/visl/visl.h<br/>index 31639f2e593d..c593b1337f11 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/visl/visl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/visl/visl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/visl/visl.h</a></div><div class='hunk'>@@ -127,6 +127,7 @@ enum visl_codec {</div><div class='ctx'> 	VISL_CODEC_VP9,</div><div class='ctx'> 	VISL_CODEC_H264,</div><div class='ctx'> 	VISL_CODEC_HEVC,</div><div class='add'>+	VISL_CODEC_AV1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct visl_blob {</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/Kconfig b/drivers/media/test-drivers/vivid/Kconfig<br/>index 5b08a5ad291e..ec2e71d76965 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/Kconfig</a></div><div class='hunk'>@@ -10,7 +10,6 @@ config VIDEO_VIVID</div><div class='ctx'> 	select VIDEOBUF2_DMA_CONTIG</div><div class='ctx'> 	select VIDEO_V4L2_TPG</div><div class='ctx'> 	select MEDIA_CONTROLLER</div><div class='del'>-	select MEDIA_CONTROLLER_REQUEST_API</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enables a virtual video driver. This driver emulates a webcam,</div><div class='ctx'> 	  TV, S-Video and HDMI capture hardware, including VBI support for</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-core.c b/drivers/media/test-drivers/vivid/vivid-core.c<br/>index 394c9f81ea72..159c72cbb5bf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-core.c</a></div><div class='hunk'>@@ -861,7 +861,7 @@ static const struct media_device_ops vivid_media_ops = {</div><div class='ctx'> static int vivid_create_queue(struct vivid_dev *dev,</div><div class='ctx'> 			      struct vb2_queue *q,</div><div class='ctx'> 			      u32 buf_type,</div><div class='del'>-			      unsigned int min_buffers_needed,</div><div class='add'>+			      unsigned int min_queued_buffers,</div><div class='ctx'> 			      const struct vb2_ops *ops)</div><div class='ctx'> {</div><div class='ctx'> 	if (buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE &amp;&amp; dev-&gt;multiplanar)</div><div class='hunk'>@@ -876,6 +876,20 @@ static int vivid_create_queue(struct vivid_dev *dev,</div><div class='ctx'> 	q-&gt;type = buf_type;</div><div class='ctx'> 	q-&gt;io_modes = VB2_MMAP | VB2_DMABUF;</div><div class='ctx'> 	q-&gt;io_modes |= V4L2_TYPE_IS_OUTPUT(buf_type) ?  VB2_WRITE : VB2_READ;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The maximum number of buffers is 32768 if PAGE_SHIFT == 12,</div><div class='add'>+	 * see also MAX_BUFFER_INDEX in videobuf2-core.c. It will be less if</div><div class='add'>+	 * PAGE_SHIFT &gt; 12, but then max_num_buffers will be clamped by</div><div class='add'>+	 * videobuf2-core.c to MAX_BUFFER_INDEX.</div><div class='add'>+	 */</div><div class='add'>+	if (buf_type == V4L2_BUF_TYPE_VIDEO_CAPTURE)</div><div class='add'>+		q-&gt;max_num_buffers = 64;</div><div class='add'>+	if (buf_type == V4L2_BUF_TYPE_SDR_CAPTURE)</div><div class='add'>+		q-&gt;max_num_buffers = 1024;</div><div class='add'>+	if (buf_type == V4L2_BUF_TYPE_VBI_CAPTURE)</div><div class='add'>+		q-&gt;max_num_buffers = 32768;</div><div class='add'>+</div><div class='ctx'> 	if (allocators[dev-&gt;inst] != 1)</div><div class='ctx'> 		q-&gt;io_modes |= VB2_USERPTR;</div><div class='ctx'> 	q-&gt;drv_priv = dev;</div><div class='hunk'>@@ -884,7 +898,7 @@ static int vivid_create_queue(struct vivid_dev *dev,</div><div class='ctx'> 	q-&gt;mem_ops = allocators[dev-&gt;inst] == 1 ? &amp;vb2_dma_contig_memops :</div><div class='ctx'> 						  &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = supports_requests[dev-&gt;inst] ? 0 : min_buffers_needed;</div><div class='add'>+	q-&gt;min_queued_buffers = supports_requests[dev-&gt;inst] ? 0 : min_queued_buffers;</div><div class='ctx'> 	q-&gt;lock = &amp;dev-&gt;mutex;</div><div class='ctx'> 	q-&gt;dev = dev-&gt;v4l2_dev.dev;</div><div class='ctx'> 	q-&gt;supports_requests = supports_requests[dev-&gt;inst];</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-meta-cap.c b/drivers/media/test-drivers/vivid/vivid-meta-cap.c<br/>index 780f96860a6d..0a718d037e59 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-meta-cap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-meta-cap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-meta-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-meta-cap.c</a></div><div class='hunk'>@@ -30,9 +30,6 @@ static int meta_cap_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,</div><div class='ctx'> 		sizes[0] = size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='del'>-</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-meta-out.c b/drivers/media/test-drivers/vivid/vivid-meta-out.c<br/>index 95835b52b58f..4a569a6e58be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-meta-out.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-meta-out.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-meta-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-meta-out.c</a></div><div class='hunk'>@@ -18,6 +18,7 @@ static int meta_out_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,</div><div class='ctx'> 				struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct vivid_dev *dev = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	unsigned int size =  sizeof(struct vivid_meta_out_buf);</div><div class='ctx'> </div><div class='ctx'> 	if (!vivid_is_webcam(dev))</div><div class='hunk'>@@ -30,8 +31,8 @@ static int meta_out_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,</div><div class='ctx'> 		sizes[0] = size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 2)</div><div class='add'>+		*nbuffers = 2 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-touch-cap.c b/drivers/media/test-drivers/vivid/vivid-touch-cap.c<br/>index c7f6e23df51e..4b3c6ea0afde 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-touch-cap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-touch-cap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-touch-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-touch-cap.c</a></div><div class='hunk'>@@ -13,6 +13,7 @@ static int touch_cap_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,</div><div class='ctx'> 				 struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct vivid_dev *dev = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> 	struct v4l2_pix_format *f = &amp;dev-&gt;tch_format;</div><div class='ctx'> 	unsigned int size = f-&gt;sizeimage;</div><div class='ctx'> </div><div class='hunk'>@@ -23,8 +24,8 @@ static int touch_cap_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,</div><div class='ctx'> 		sizes[0] = size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 2)</div><div class='add'>+		*nbuffers = 2 - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-vbi-cap.c b/drivers/media/test-drivers/vivid/vivid-vbi-cap.c<br/>index b65b02eeeb97..3840b3a664ac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vbi-cap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-vbi-cap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vbi-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vbi-cap.c</a></div><div class='hunk'>@@ -134,9 +134,6 @@ static int vbi_cap_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> </div><div class='ctx'> 	sizes[0] = size;</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='del'>-</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-vbi-out.c b/drivers/media/test-drivers/vivid/vivid-vbi-out.c<br/>index cd56476902a2..434a10676417 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vbi-out.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-vbi-out.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vbi-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vbi-out.c</a></div><div class='hunk'>@@ -30,9 +30,6 @@ static int vbi_out_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> </div><div class='ctx'> 	sizes[0] = size;</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='del'>-</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-vid-cap.c b/drivers/media/test-drivers/vivid/vivid-vid-cap.c<br/>index 3a06df35a2d7..2804975fe278 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vid-cap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-vid-cap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vid-cap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vid-cap.c</a></div><div class='hunk'>@@ -117,9 +117,6 @@ static int vid_cap_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 					dev-&gt;fmt_cap-&gt;data_offset[p];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='del'>-</div><div class='ctx'> 	*nplanes = buffers;</div><div class='ctx'> </div><div class='ctx'> 	dprintk(dev, 1, "%s: count=%d\n", __func__, *nbuffers);</div><div class='head'>diff --git a/drivers/media/test-drivers/vivid/vivid-vid-out.c b/drivers/media/test-drivers/vivid/vivid-vid-out.c<br/>index 184a6df2c29f..1653b2988f7e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vid-out.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/test-drivers/vivid/vivid-vid-out.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/test-drivers/vivid/vivid-vid-out.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/test-drivers/vivid/vivid-vid-out.c</a></div><div class='hunk'>@@ -73,12 +73,9 @@ static int vid_out_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 				       vfmt-&gt;data_offset[p] : size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='del'>-</div><div class='ctx'> 	*nplanes = planes;</div><div class='ctx'> </div><div class='del'>-	dprintk(dev, 1, "%s: count=%d\n", __func__, *nbuffers);</div><div class='add'>+	dprintk(dev, 1, "%s: count=%u\n", __func__, *nbuffers);</div><div class='ctx'> 	for (p = 0; p &lt; planes; p++)</div><div class='ctx'> 		dprintk(dev, 1, "%s: size[%u]=%u\n", __func__, p, sizes[p]);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/media/usb/airspy/airspy.c b/drivers/media/usb/airspy/airspy.c<br/>index 462eb8423506..e24e655fb1db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/airspy/airspy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/airspy/airspy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/airspy/airspy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/airspy/airspy.c</a></div><div class='hunk'>@@ -482,12 +482,13 @@ static int airspy_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		unsigned int *nplanes, unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct airspy *s = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(s-&gt;dev, "nbuffers=%d\n", *nbuffers);</div><div class='ctx'> </div><div class='ctx'> 	/* Need at least 8 buffers */</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 8)</div><div class='del'>-		*nbuffers = 8 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 8)</div><div class='add'>+		*nbuffers = 8 - q_num_bufs;</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	sizes[0] = PAGE_ALIGN(s-&gt;buffersize);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/usb/cx231xx/cx231xx-417.c b/drivers/media/usb/cx231xx/cx231xx-417.c<br/>index fe4410a5e128..3b75d062e602 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-417.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/cx231xx/cx231xx-417.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-417.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-417.c</a></div><div class='hunk'>@@ -1218,12 +1218,13 @@ static int queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct cx231xx *dev = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned int size = mpeglinesize * mpeglines;</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;ts1.ts_packet_size  = mpeglinesize;</div><div class='ctx'> 	dev-&gt;ts1.ts_packet_count = mpeglines;</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; CX231XX_MIN_BUF)</div><div class='del'>-		*nbuffers = CX231XX_MIN_BUF - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; CX231XX_MIN_BUF)</div><div class='add'>+		*nbuffers = CX231XX_MIN_BUF - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes)</div><div class='ctx'> 		return sizes[0] &lt; size ? -EINVAL : 0;</div><div class='hunk'>@@ -1781,7 +1782,7 @@ int cx231xx_417_register(struct cx231xx *dev)</div><div class='ctx'> 	q-&gt;ops = &amp;cx231xx_video_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	q-&gt;lock = &amp;dev-&gt;lock;</div><div class='ctx'> 	err = vb2_queue_init(q);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/media/usb/cx231xx/cx231xx-core.c b/drivers/media/usb/cx231xx/cx231xx-core.c<br/>index 7b7e2a26ef93..d8312201694f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/cx231xx/cx231xx-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-core.c</a></div><div class='hunk'>@@ -1023,6 +1023,7 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,</div><div class='ctx'> 	if (!dev-&gt;video_mode.isoc_ctl.urb) {</div><div class='ctx'> 		dev_err(dev-&gt;dev,</div><div class='ctx'> 			"cannot alloc memory for usb buffers\n");</div><div class='add'>+		kfree(dma_q-&gt;p_left_data);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1032,6 +1033,7 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,</div><div class='ctx'> 		dev_err(dev-&gt;dev,</div><div class='ctx'> 			"cannot allocate memory for usbtransfer\n");</div><div class='ctx'> 		kfree(dev-&gt;video_mode.isoc_ctl.urb);</div><div class='add'>+		kfree(dma_q-&gt;p_left_data);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/usb/cx231xx/cx231xx-video.c b/drivers/media/usb/cx231xx/cx231xx-video.c<br/>index e23b8ccd79d4..8f347bbeeb32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/cx231xx/cx231xx-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/cx231xx/cx231xx-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/cx231xx/cx231xx-video.c</a></div><div class='hunk'>@@ -714,11 +714,12 @@ static int queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		       unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct cx231xx *dev = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;size = (dev-&gt;width * dev-&gt;height * dev-&gt;format-&gt;depth + 7) &gt;&gt; 3;</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; CX231XX_MIN_BUF)</div><div class='del'>-		*nbuffers = CX231XX_MIN_BUF - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; CX231XX_MIN_BUF)</div><div class='add'>+		*nbuffers = CX231XX_MIN_BUF - q_num_bufs;</div><div class='ctx'> </div><div class='ctx'> 	if (*nplanes)</div><div class='ctx'> 		return sizes[0] &lt; dev-&gt;size ? -EINVAL : 0;</div><div class='hunk'>@@ -1810,7 +1811,7 @@ int cx231xx_register_analog_devices(struct cx231xx *dev)</div><div class='ctx'> 	q-&gt;ops = &amp;cx231xx_video_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	q-&gt;lock = &amp;dev-&gt;lock;</div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1870,7 +1871,7 @@ int cx231xx_register_analog_devices(struct cx231xx *dev)</div><div class='ctx'> 	q-&gt;ops = &amp;cx231xx_vbi_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 1;</div><div class='add'>+	q-&gt;min_queued_buffers = 1;</div><div class='ctx'> 	q-&gt;lock = &amp;dev-&gt;lock;</div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/usb/dvb-usb/cxusb-analog.c b/drivers/media/usb/dvb-usb/cxusb-analog.c<br/>index deba5224cb8d..b5d8c6b75ae1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/dvb-usb/cxusb-analog.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/dvb-usb/cxusb-analog.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/dvb-usb/cxusb-analog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/dvb-usb/cxusb-analog.c</a></div><div class='hunk'>@@ -1632,7 +1632,7 @@ static int cxusb_medion_register_analog_video(struct dvb_usb_device *dvbdev)</div><div class='ctx'> 	cxdev-&gt;videoqueue.buf_struct_size =</div><div class='ctx'> 		sizeof(struct cxusb_medion_vbuffer);</div><div class='ctx'> 	cxdev-&gt;videoqueue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	cxdev-&gt;videoqueue.min_buffers_needed = 6;</div><div class='add'>+	cxdev-&gt;videoqueue.min_queued_buffers = 6;</div><div class='ctx'> 	cxdev-&gt;videoqueue.lock = &amp;cxdev-&gt;dev_lock;</div><div class='ctx'> </div><div class='ctx'> 	ret = vb2_queue_init(&amp;cxdev-&gt;videoqueue);</div><div class='head'>diff --git a/drivers/media/usb/em28xx/em28xx-video.c b/drivers/media/usb/em28xx/em28xx-video.c<br/>index 25e0620deff1..4aef584e21da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/em28xx/em28xx-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/em28xx/em28xx-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/em28xx/em28xx-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/em28xx/em28xx-video.c</a></div><div class='hunk'>@@ -1607,7 +1607,8 @@ static int vidioc_g_parm(struct file *file, void *priv,</div><div class='ctx'> 	p-&gt;parm.capture.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='ctx'> 	if (dev-&gt;is_webcam) {</div><div class='ctx'> 		rc = v4l2_device_call_until_err(&amp;v4l2-&gt;v4l2_dev, 0,</div><div class='del'>-						video, g_frame_interval, &amp;ival);</div><div class='add'>+						pad, get_frame_interval, NULL,</div><div class='add'>+						&amp;ival);</div><div class='ctx'> 		if (!rc)</div><div class='ctx'> 			p-&gt;parm.capture.timeperframe = ival.interval;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1639,7 +1640,8 @@ static int vidioc_s_parm(struct file *file, void *priv,</div><div class='ctx'> 	p-&gt;parm.capture.readbuffers = EM28XX_MIN_BUF;</div><div class='ctx'> 	p-&gt;parm.capture.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='ctx'> 	rc = v4l2_device_call_until_err(&amp;dev-&gt;v4l2-&gt;v4l2_dev, 0,</div><div class='del'>-					video, s_frame_interval, &amp;ival);</div><div class='add'>+					pad, set_frame_interval, NULL,</div><div class='add'>+					&amp;ival);</div><div class='ctx'> 	if (!rc)</div><div class='ctx'> 		p-&gt;parm.capture.timeperframe = ival.interval;</div><div class='ctx'> 	return rc;</div><div class='head'>diff --git a/drivers/media/usb/gspca/gspca.c b/drivers/media/usb/gspca/gspca.c<br/>index 770714c34295..e8c8bdb9c40b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/gspca/gspca.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/gspca/gspca.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/gspca/gspca.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/gspca/gspca.c</a></div><div class='hunk'>@@ -1257,7 +1257,7 @@ static int vidioc_g_parm(struct file *filp, void *priv,</div><div class='ctx'> {</div><div class='ctx'> 	struct gspca_dev *gspca_dev = video_drvdata(filp);</div><div class='ctx'> </div><div class='del'>-	parm-&gt;parm.capture.readbuffers = gspca_dev-&gt;queue.min_buffers_needed;</div><div class='add'>+	parm-&gt;parm.capture.readbuffers = gspca_dev-&gt;queue.min_queued_buffers;</div><div class='ctx'> </div><div class='ctx'> 	if (!gspca_dev-&gt;sd_desc-&gt;get_streamparm)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1273,7 +1273,7 @@ static int vidioc_s_parm(struct file *filp, void *priv,</div><div class='ctx'> {</div><div class='ctx'> 	struct gspca_dev *gspca_dev = video_drvdata(filp);</div><div class='ctx'> </div><div class='del'>-	parm-&gt;parm.capture.readbuffers = gspca_dev-&gt;queue.min_buffers_needed;</div><div class='add'>+	parm-&gt;parm.capture.readbuffers = gspca_dev-&gt;queue.min_queued_buffers;</div><div class='ctx'> </div><div class='ctx'> 	if (!gspca_dev-&gt;sd_desc-&gt;set_streamparm) {</div><div class='ctx'> 		parm-&gt;parm.capture.capability = 0;</div><div class='hunk'>@@ -1517,7 +1517,7 @@ int gspca_dev_probe2(struct usb_interface *intf,</div><div class='ctx'> 	q-&gt;ops = &amp;gspca_qops;</div><div class='ctx'> 	q-&gt;mem_ops = &amp;vb2_vmalloc_memops;</div><div class='ctx'> 	q-&gt;timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;</div><div class='del'>-	q-&gt;min_buffers_needed = 2;</div><div class='add'>+	q-&gt;min_queued_buffers = 2;</div><div class='ctx'> 	q-&gt;lock = &amp;gspca_dev-&gt;usb_lock;</div><div class='ctx'> 	ret = vb2_queue_init(q);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/media/usb/hackrf/hackrf.c b/drivers/media/usb/hackrf/hackrf.c<br/>index 3e535be2c520..9c0ecd5f056c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/hackrf/hackrf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/hackrf/hackrf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/hackrf/hackrf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/hackrf/hackrf.c</a></div><div class='hunk'>@@ -753,12 +753,13 @@ static int hackrf_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> 		unsigned int *nplanes, unsigned int sizes[], struct device *alloc_devs[])</div><div class='ctx'> {</div><div class='ctx'> 	struct hackrf_dev *dev = vb2_get_drv_priv(vq);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(dev-&gt;dev, "nbuffers=%d\n", *nbuffers);</div><div class='ctx'> </div><div class='ctx'> 	/* Need at least 8 buffers */</div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 8)</div><div class='del'>-		*nbuffers = 8 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 8)</div><div class='add'>+		*nbuffers = 8 - q_num_bufs;</div><div class='ctx'> 	*nplanes = 1;</div><div class='ctx'> 	sizes[0] = PAGE_ALIGN(dev-&gt;buffersize);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/usb/pvrusb2/pvrusb2-context.c b/drivers/media/usb/pvrusb2/pvrusb2-context.c<br/>index 14170a5d72b3..1764674de98b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/pvrusb2/pvrusb2-context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/pvrusb2/pvrusb2-context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/pvrusb2/pvrusb2-context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/pvrusb2/pvrusb2-context.c</a></div><div class='hunk'>@@ -268,7 +268,8 @@ void pvr2_context_disconnect(struct pvr2_context *mp)</div><div class='ctx'> {</div><div class='ctx'> 	pvr2_hdw_disconnect(mp-&gt;hdw);</div><div class='ctx'> 	mp-&gt;disconnect_flag = !0;</div><div class='del'>-	pvr2_context_notify(mp);</div><div class='add'>+	if (!pvr2_context_shutok())</div><div class='add'>+		pvr2_context_notify(mp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/usb/stk1160/stk1160-video.c b/drivers/media/usb/stk1160/stk1160-video.c<br/>index 4e966f6bf608..366f0e4a5dc0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/stk1160/stk1160-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/stk1160/stk1160-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/stk1160/stk1160-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/stk1160/stk1160-video.c</a></div><div class='hunk'>@@ -107,8 +107,7 @@ void stk1160_copy_video(struct stk1160 *dev, u8 *src, int len)</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * TODO: These stk1160_dbg are very spammy!</div><div class='del'>-	 * We should 1) check why we are getting them</div><div class='del'>-	 * and 2) add ratelimit.</div><div class='add'>+	 * We should check why we are getting them.</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * UPDATE: One of the reasons (the only one?) for getting these</div><div class='ctx'> 	 * is incorrect standard (mismatch between expected and configured).</div><div class='hunk'>@@ -151,7 +150,7 @@ void stk1160_copy_video(struct stk1160 *dev, u8 *src, int len)</div><div class='ctx'> </div><div class='ctx'> 	/* Let the bug hunt begin! sanity checks! */</div><div class='ctx'> 	if (lencopy &lt; 0) {</div><div class='del'>-		stk1160_dbg("copy skipped: negative lencopy\n");</div><div class='add'>+		printk_ratelimited(KERN_DEBUG "copy skipped: negative lencopy\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/usb/usbtv/usbtv-video.c b/drivers/media/usb/usbtv/usbtv-video.c<br/>index 1e30e05953dc..62a583040cd4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/usbtv/usbtv-video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/usbtv/usbtv-video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/usbtv/usbtv-video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/usbtv/usbtv-video.c</a></div><div class='hunk'>@@ -726,9 +726,10 @@ static int usbtv_queue_setup(struct vb2_queue *vq,</div><div class='ctx'> {</div><div class='ctx'> 	struct usbtv *usbtv = vb2_get_drv_priv(vq);</div><div class='ctx'> 	unsigned size = USBTV_CHUNK * usbtv-&gt;n_chunks * 2 * sizeof(u32);</div><div class='add'>+	unsigned int q_num_bufs = vb2_get_num_buffers(vq);</div><div class='ctx'> </div><div class='del'>-	if (vq-&gt;num_buffers + *nbuffers &lt; 2)</div><div class='del'>-		*nbuffers = 2 - vq-&gt;num_buffers;</div><div class='add'>+	if (q_num_bufs + *nbuffers &lt; 2)</div><div class='add'>+		*nbuffers = 2 - q_num_bufs;</div><div class='ctx'> 	if (*nplanes)</div><div class='ctx'> 		return sizes[0] &lt; size ? -EINVAL : 0;</div><div class='ctx'> 	*nplanes = 1;</div><div class='head'>diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c<br/>index 08fcd2ffa727..bbd90123a4e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/uvc/uvc_driver.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/uvc/uvc_driver.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/uvc/uvc_driver.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/uvc/uvc_driver.c</a></div><div class='hunk'>@@ -2592,6 +2592,15 @@ static const struct usb_device_id uvc_ids[] = {</div><div class='ctx'> 	  .bInterfaceSubClass	= 1,</div><div class='ctx'> 	  .bInterfaceProtocol	= 0,</div><div class='ctx'> 	  .driver_info		= (kernel_ulong_t)&amp;uvc_ctrl_power_line_limited },</div><div class='add'>+	/* Chicony Electronics Co., Ltd Integrated Camera */</div><div class='add'>+	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE</div><div class='add'>+				| USB_DEVICE_ID_MATCH_INT_INFO,</div><div class='add'>+	  .idVendor		= 0x04f2,</div><div class='add'>+	  .idProduct		= 0xb67c,</div><div class='add'>+	  .bInterfaceClass	= USB_CLASS_VIDEO,</div><div class='add'>+	  .bInterfaceSubClass	= 1,</div><div class='add'>+	  .bInterfaceProtocol	= UVC_PC_PROTOCOL_15,</div><div class='add'>+	  .driver_info		= (kernel_ulong_t)&amp;uvc_ctrl_power_line_uvc11 },</div><div class='ctx'> 	/* Chicony EasyCamera */</div><div class='ctx'> 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE</div><div class='ctx'> 				| USB_DEVICE_ID_MATCH_INT_INFO,</div><div class='hunk'>@@ -2994,6 +3003,15 @@ static const struct usb_device_id uvc_ids[] = {</div><div class='ctx'> 	  .bInterfaceSubClass	= 1,</div><div class='ctx'> 	  .bInterfaceProtocol	= 0,</div><div class='ctx'> 	  .driver_info		= UVC_INFO_QUIRK(UVC_QUIRK_FORCE_BPP) },</div><div class='add'>+	/* SunplusIT Inc HD Camera */</div><div class='add'>+	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE</div><div class='add'>+				| USB_DEVICE_ID_MATCH_INT_INFO,</div><div class='add'>+	  .idVendor		= 0x2b7e,</div><div class='add'>+	  .idProduct		= 0xb752,</div><div class='add'>+	  .bInterfaceClass	= USB_CLASS_VIDEO,</div><div class='add'>+	  .bInterfaceSubClass	= 1,</div><div class='add'>+	  .bInterfaceProtocol	= UVC_PC_PROTOCOL_15,</div><div class='add'>+	  .driver_info		= (kernel_ulong_t)&amp;uvc_ctrl_power_line_uvc11 },</div><div class='ctx'> 	/* Lenovo Integrated Camera */</div><div class='ctx'> 	{ .match_flags		= USB_DEVICE_ID_MATCH_DEVICE</div><div class='ctx'> 				| USB_DEVICE_ID_MATCH_INT_INFO,</div><div class='head'>diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c<br/>index 28dde08ec6c5..7cbf4692bd87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/usb/uvc/uvc_video.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/usb/uvc/uvc_video.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/usb/uvc/uvc_video.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/usb/uvc/uvc_video.c</a></div><div class='hunk'>@@ -1954,7 +1954,7 @@ static int uvc_video_start_transfer(struct uvc_streaming *stream,</div><div class='ctx'> </div><div class='ctx'> 			/* Check if the bandwidth is high enough. */</div><div class='ctx'> 			psize = uvc_endpoint_max_bpi(stream-&gt;dev-&gt;udev, ep);</div><div class='del'>-			if (psize &gt;= bandwidth &amp;&amp; psize &lt;= best_psize) {</div><div class='add'>+			if (psize &gt;= bandwidth &amp;&amp; psize &lt; best_psize) {</div><div class='ctx'> 				altsetting = alts-&gt;desc.bAlternateSetting;</div><div class='ctx'> 				best_psize = psize;</div><div class='ctx'> 				best_ep = ep;</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c<br/>index 091e8cf4114b..3ec323bd528b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-async.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-async.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-async.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-async.c</a></div><div class='hunk'>@@ -876,11 +876,7 @@ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd)</div><div class='ctx'> 	if (sd-&gt;asc_list.next) {</div><div class='ctx'> 		list_for_each_entry_safe(asc, asc_tmp, &amp;sd-&gt;asc_list,</div><div class='ctx'> 					 asc_subdev_entry) {</div><div class='del'>-			list_move(&amp;asc-&gt;asc_entry,</div><div class='del'>-				  &amp;asc-&gt;notifier-&gt;waiting_list);</div><div class='del'>-</div><div class='ctx'> 			v4l2_async_unbind_subdev_one(asc-&gt;notifier, asc);</div><div class='del'>-			list_del(&amp;asc-&gt;asc_subdev_entry);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-cci.c b/drivers/media/v4l2-core/v4l2-cci.c<br/>index bc2dbec019b0..10005c80f43b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-cci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-cci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-cci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-cci.c</a></div><div class='hunk'>@@ -18,6 +18,7 @@</div><div class='ctx'> </div><div class='ctx'> int cci_read(struct regmap *map, u32 reg, u64 *val, int *err)</div><div class='ctx'> {</div><div class='add'>+	bool little_endian;</div><div class='ctx'> 	unsigned int len;</div><div class='ctx'> 	u8 buf[8];</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -25,8 +26,9 @@ int cci_read(struct regmap *map, u32 reg, u64 *val, int *err)</div><div class='ctx'> 	if (err &amp;&amp; *err)</div><div class='ctx'> 		return *err;</div><div class='ctx'> </div><div class='del'>-	len = FIELD_GET(CCI_REG_WIDTH_MASK, reg);</div><div class='del'>-	reg = FIELD_GET(CCI_REG_ADDR_MASK, reg);</div><div class='add'>+	little_endian = reg &amp; CCI_REG_LE;</div><div class='add'>+	len = CCI_REG_WIDTH_BYTES(reg);</div><div class='add'>+	reg = CCI_REG_ADDR(reg);</div><div class='ctx'> </div><div class='ctx'> 	ret = regmap_bulk_read(map, reg, buf, len);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -40,16 +42,28 @@ int cci_read(struct regmap *map, u32 reg, u64 *val, int *err)</div><div class='ctx'> 		*val = buf[0];</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='del'>-		*val = get_unaligned_be16(buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			*val = get_unaligned_le16(buf);</div><div class='add'>+		else</div><div class='add'>+			*val = get_unaligned_be16(buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 3:</div><div class='del'>-		*val = get_unaligned_be24(buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			*val = get_unaligned_le24(buf);</div><div class='add'>+		else</div><div class='add'>+			*val = get_unaligned_be24(buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 4:</div><div class='del'>-		*val = get_unaligned_be32(buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			*val = get_unaligned_le32(buf);</div><div class='add'>+		else</div><div class='add'>+			*val = get_unaligned_be32(buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 8:</div><div class='del'>-		*val = get_unaligned_be64(buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			*val = get_unaligned_le64(buf);</div><div class='add'>+		else</div><div class='add'>+			*val = get_unaligned_be64(buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(regmap_get_device(map), "Error invalid reg-width %u for reg 0x%04x\n",</div><div class='hunk'>@@ -68,6 +82,7 @@ EXPORT_SYMBOL_GPL(cci_read);</div><div class='ctx'> </div><div class='ctx'> int cci_write(struct regmap *map, u32 reg, u64 val, int *err)</div><div class='ctx'> {</div><div class='add'>+	bool little_endian;</div><div class='ctx'> 	unsigned int len;</div><div class='ctx'> 	u8 buf[8];</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -75,24 +90,37 @@ int cci_write(struct regmap *map, u32 reg, u64 val, int *err)</div><div class='ctx'> 	if (err &amp;&amp; *err)</div><div class='ctx'> 		return *err;</div><div class='ctx'> </div><div class='del'>-	len = FIELD_GET(CCI_REG_WIDTH_MASK, reg);</div><div class='del'>-	reg = FIELD_GET(CCI_REG_ADDR_MASK, reg);</div><div class='add'>+	little_endian = reg &amp; CCI_REG_LE;</div><div class='add'>+	len = CCI_REG_WIDTH_BYTES(reg);</div><div class='add'>+	reg = CCI_REG_ADDR(reg);</div><div class='ctx'> </div><div class='ctx'> 	switch (len) {</div><div class='ctx'> 	case 1:</div><div class='ctx'> 		buf[0] = val;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 2:</div><div class='del'>-		put_unaligned_be16(val, buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			put_unaligned_le16(val, buf);</div><div class='add'>+		else</div><div class='add'>+			put_unaligned_be16(val, buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 3:</div><div class='del'>-		put_unaligned_be24(val, buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			put_unaligned_le24(val, buf);</div><div class='add'>+		else</div><div class='add'>+			put_unaligned_be24(val, buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 4:</div><div class='del'>-		put_unaligned_be32(val, buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			put_unaligned_le32(val, buf);</div><div class='add'>+		else</div><div class='add'>+			put_unaligned_be32(val, buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 8:</div><div class='del'>-		put_unaligned_be64(val, buf);</div><div class='add'>+		if (little_endian)</div><div class='add'>+			put_unaligned_le64(val, buf);</div><div class='add'>+		else</div><div class='add'>+			put_unaligned_be64(val, buf);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(regmap_get_device(map), "Error invalid reg-width %u for reg 0x%04x\n",</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c<br/>index 3a4b15a98e02..273d83de2a87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-common.c</a></div><div class='hunk'>@@ -195,9 +195,9 @@ int v4l2_g_parm_cap(struct video_device *vdev,</div><div class='ctx'> </div><div class='ctx'> 	if (vdev-&gt;device_caps &amp; V4L2_CAP_READWRITE)</div><div class='ctx'> 		a-&gt;parm.capture.readbuffers = 2;</div><div class='del'>-	if (v4l2_subdev_has_op(sd, video, g_frame_interval))</div><div class='add'>+	if (v4l2_subdev_has_op(sd, pad, get_frame_interval))</div><div class='ctx'> 		a-&gt;parm.capture.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='del'>-	ret = v4l2_subdev_call(sd, video, g_frame_interval, &amp;ival);</div><div class='add'>+	ret = v4l2_subdev_call_state_active(sd, pad, get_frame_interval, &amp;ival);</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		a-&gt;parm.capture.timeperframe = ival.interval;</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -222,9 +222,9 @@ int v4l2_s_parm_cap(struct video_device *vdev,</div><div class='ctx'> 	else</div><div class='ctx'> 		a-&gt;parm.capture.readbuffers = 0;</div><div class='ctx'> </div><div class='del'>-	if (v4l2_subdev_has_op(sd, video, g_frame_interval))</div><div class='add'>+	if (v4l2_subdev_has_op(sd, pad, get_frame_interval))</div><div class='ctx'> 		a-&gt;parm.capture.capability = V4L2_CAP_TIMEPERFRAME;</div><div class='del'>-	ret = v4l2_subdev_call(sd, video, s_frame_interval, &amp;ival);</div><div class='add'>+	ret = v4l2_subdev_call_state_active(sd, pad, set_frame_interval, &amp;ival);</div><div class='ctx'> 	if (!ret)</div><div class='ctx'> 		a-&gt;parm.capture.timeperframe = ival.interval;</div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -254,6 +254,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)</div><div class='ctx'> 		{ .format = V4L2_PIX_FMT_BGR666,  .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='ctx'> 		{ .format = V4L2_PIX_FMT_BGR48_12, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 6, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='ctx'> 		{ .format = V4L2_PIX_FMT_ABGR64_12, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 8, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='add'>+		{ .format = V4L2_PIX_FMT_RGBA1010102, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='add'>+		{ .format = V4L2_PIX_FMT_RGBX1010102, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='add'>+		{ .format = V4L2_PIX_FMT_ARGB2101010, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },</div><div class='ctx'> </div><div class='ctx'> 		/* YUV packed formats */</div><div class='ctx'> 		{ .format = V4L2_PIX_FMT_YUYV,    .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c<br/>index f3bed37859a2..8c07400bd280 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-compat-ioctl32.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-compat-ioctl32.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-compat-ioctl32.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-compat-ioctl32.c</a></div><div class='hunk'>@@ -116,6 +116,9 @@ struct v4l2_format32 {</div><div class='ctx'>  * @flags:	additional buffer management attributes (ignored unless the</div><div class='ctx'>  *		queue has V4L2_BUF_CAP_SUPPORTS_MMAP_CACHE_HINTS capability and</div><div class='ctx'>  *		configured for MMAP streaming I/O).</div><div class='add'>+ * @max_num_buffers: if V4L2_BUF_CAP_SUPPORTS_MAX_NUM_BUFFERS capability flag is set</div><div class='add'>+ *		this field indicate the maximum possible number of buffers</div><div class='add'>+ *		for this queue.</div><div class='ctx'>  * @reserved:	future extensions</div><div class='ctx'>  */</div><div class='ctx'> struct v4l2_create_buffers32 {</div><div class='hunk'>@@ -125,7 +128,8 @@ struct v4l2_create_buffers32 {</div><div class='ctx'> 	struct v4l2_format32	format;</div><div class='ctx'> 	__u32			capabilities;</div><div class='ctx'> 	__u32			flags;</div><div class='del'>-	__u32			reserved[6];</div><div class='add'>+	__u32			max_num_buffers;</div><div class='add'>+	__u32			reserved[5];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int get_v4l2_format32(struct v4l2_format *p64,</div><div class='hunk'>@@ -175,6 +179,9 @@ static int get_v4l2_create32(struct v4l2_create_buffers *p64,</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	if (copy_from_user(&amp;p64-&gt;flags, &amp;p32-&gt;flags, sizeof(p32-&gt;flags)))</div><div class='ctx'> 		return -EFAULT;</div><div class='add'>+	if (copy_from_user(&amp;p64-&gt;max_num_buffers, &amp;p32-&gt;max_num_buffers,</div><div class='add'>+			   sizeof(p32-&gt;max_num_buffers)))</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> 	return get_v4l2_format32(&amp;p64-&gt;format, &amp;p32-&gt;format);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -221,6 +228,7 @@ static int put_v4l2_create32(struct v4l2_create_buffers *p64,</div><div class='ctx'> 			 offsetof(struct v4l2_create_buffers32, format)) ||</div><div class='ctx'> 	    put_user(p64-&gt;capabilities, &amp;p32-&gt;capabilities) ||</div><div class='ctx'> 	    put_user(p64-&gt;flags, &amp;p32-&gt;flags) ||</div><div class='add'>+	    put_user(p64-&gt;max_num_buffers, &amp;p32-&gt;max_num_buffers) ||</div><div class='ctx'> 	    copy_to_user(p32-&gt;reserved, p64-&gt;reserved, sizeof(p64-&gt;reserved)))</div><div class='ctx'> 		return -EFAULT;</div><div class='ctx'> 	return put_v4l2_format32(&amp;p64-&gt;format, &amp;p32-&gt;format);</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c<br/>index f81279492682..d13954bd31fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-dev.c</a></div><div class='hunk'>@@ -642,11 +642,13 @@ static void determine_valid_ioctls(struct video_device *vdev)</div><div class='ctx'> 		SET_VALID_IOCTL(ops, VIDIOC_TRY_DECODER_CMD, vidioc_try_decoder_cmd);</div><div class='ctx'> 		SET_VALID_IOCTL(ops, VIDIOC_ENUM_FRAMESIZES, vidioc_enum_framesizes);</div><div class='ctx'> 		SET_VALID_IOCTL(ops, VIDIOC_ENUM_FRAMEINTERVALS, vidioc_enum_frameintervals);</div><div class='del'>-		if (ops-&gt;vidioc_g_selection) {</div><div class='add'>+		if (ops-&gt;vidioc_g_selection &amp;&amp;</div><div class='add'>+		    !test_bit(_IOC_NR(VIDIOC_G_SELECTION), vdev-&gt;valid_ioctls)) {</div><div class='ctx'> 			__set_bit(_IOC_NR(VIDIOC_G_CROP), valid_ioctls);</div><div class='ctx'> 			__set_bit(_IOC_NR(VIDIOC_CROPCAP), valid_ioctls);</div><div class='ctx'> 		}</div><div class='del'>-		if (ops-&gt;vidioc_s_selection)</div><div class='add'>+		if (ops-&gt;vidioc_s_selection &amp;&amp;</div><div class='add'>+		    !test_bit(_IOC_NR(VIDIOC_S_SELECTION), vdev-&gt;valid_ioctls))</div><div class='ctx'> 			__set_bit(_IOC_NR(VIDIOC_S_CROP), valid_ioctls);</div><div class='ctx'> 		SET_VALID_IOCTL(ops, VIDIOC_G_SELECTION, vidioc_g_selection);</div><div class='ctx'> 		SET_VALID_IOCTL(ops, VIDIOC_S_SELECTION, vidioc_s_selection);</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c<br/>index 7f181fbbb140..89c7192148df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-fwnode.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-fwnode.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-fwnode.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-fwnode.c</a></div><div class='hunk'>@@ -1179,7 +1179,9 @@ v4l2_async_nf_parse_fwnode_sensor(struct device *dev,</div><div class='ctx'> 	static const char * const led_props[] = { "led" };</div><div class='ctx'> 	static const struct v4l2_fwnode_int_props props[] = {</div><div class='ctx'> 		{ "flash-leds", led_props, ARRAY_SIZE(led_props) },</div><div class='del'>-		{ "lens-focus", NULL, 0 },</div><div class='add'>+		{ "mipi-img-flash-leds", },</div><div class='add'>+		{ "lens-focus", },</div><div class='add'>+		{ "mipi-img-lens-focus", },</div><div class='ctx'> 	};</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c<br/>index 9b1de54ce379..33076af4dfdb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-ioctl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-ioctl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-ioctl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-ioctl.c</a></div><div class='hunk'>@@ -483,9 +483,9 @@ static void v4l_print_create_buffers(const void *arg, bool write_only)</div><div class='ctx'> {</div><div class='ctx'> 	const struct v4l2_create_buffers *p = arg;</div><div class='ctx'> </div><div class='del'>-	pr_cont("index=%d, count=%d, memory=%s, capabilities=0x%08x, ",</div><div class='add'>+	pr_cont("index=%d, count=%d, memory=%s, capabilities=0x%08x, max num buffers=%u",</div><div class='ctx'> 		p-&gt;index, p-&gt;count, prt_names(p-&gt;memory, v4l2_memory_names),</div><div class='del'>-		p-&gt;capabilities);</div><div class='add'>+		p-&gt;capabilities, p-&gt;max_num_buffers);</div><div class='ctx'> 	v4l_print_format(&amp;p-&gt;format, write_only);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2951,7 +2951,7 @@ void v4l_printk_ioctl(const char *prefix, unsigned int cmd)</div><div class='ctx'> 		type = "v4l2_int";</div><div class='ctx'> 		break;</div><div class='ctx'> 	case 'V':</div><div class='del'>-		if (_IOC_NR(cmd) &gt;= V4L2_IOCTLS) {</div><div class='add'>+		if (!v4l2_is_known_ioctl(cmd)) {</div><div class='ctx'> 			type = "v4l2";</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c<br/>index 0cc30397fbad..9e983176542b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-mem2mem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-mem2mem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-mem2mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-mem2mem.c</a></div><div class='hunk'>@@ -301,9 +301,12 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev,</div><div class='ctx'> </div><div class='ctx'> 	dprintk("Trying to schedule a job for m2m_ctx: %p\n", m2m_ctx);</div><div class='ctx'> </div><div class='del'>-	if (!m2m_ctx-&gt;out_q_ctx.q.streaming</div><div class='del'>-	    || !m2m_ctx-&gt;cap_q_ctx.q.streaming) {</div><div class='del'>-		dprintk("Streaming needs to be on for both queues\n");</div><div class='add'>+	if (!m2m_ctx-&gt;out_q_ctx.q.streaming ||</div><div class='add'>+	    (!m2m_ctx-&gt;cap_q_ctx.q.streaming &amp;&amp; !m2m_ctx-&gt;ignore_cap_streaming)) {</div><div class='add'>+		if (!m2m_ctx-&gt;ignore_cap_streaming)</div><div class='add'>+			dprintk("Streaming needs to be on for both queues\n");</div><div class='add'>+		else</div><div class='add'>+			dprintk("Streaming needs to be on for the OUTPUT queue\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/media/v4l2-core/v4l2-subdev.c b/drivers/media/v4l2-core/v4l2-subdev.c<br/>index be86b906c985..4c6198c48dd6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-subdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/media/v4l2-core/v4l2-subdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/media/v4l2-core/v4l2-subdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/media/v4l2-core/v4l2-subdev.c</a></div><div class='hunk'>@@ -177,7 +177,7 @@ static int check_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state,</div><div class='ctx'> {</div><div class='ctx'> 	if (sd-&gt;flags &amp; V4L2_SUBDEV_FL_STREAMS) {</div><div class='ctx'> #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)</div><div class='del'>-		if (!v4l2_subdev_state_get_stream_format(state, pad, stream))</div><div class='add'>+		if (!v4l2_subdev_state_get_format(state, pad, stream))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		return 0;</div><div class='ctx'> #else</div><div class='hunk'>@@ -245,29 +245,6 @@ static int call_enum_frame_size(struct v4l2_subdev *sd,</div><div class='ctx'> 	       sd-&gt;ops-&gt;pad-&gt;enum_frame_size(sd, state, fse);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int check_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				       struct v4l2_subdev_frame_interval *fi)</div><div class='del'>-{</div><div class='del'>-	if (!fi)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return check_pad(sd, fi-&gt;pad);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int call_g_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				 struct v4l2_subdev_frame_interval *fi)</div><div class='del'>-{</div><div class='del'>-	return check_frame_interval(sd, fi) ? :</div><div class='del'>-	       sd-&gt;ops-&gt;video-&gt;g_frame_interval(sd, fi);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int call_s_frame_interval(struct v4l2_subdev *sd,</div><div class='del'>-				 struct v4l2_subdev_frame_interval *fi)</div><div class='del'>-{</div><div class='del'>-	return check_frame_interval(sd, fi) ? :</div><div class='del'>-	       sd-&gt;ops-&gt;video-&gt;s_frame_interval(sd, fi);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int call_enum_frame_interval(struct v4l2_subdev *sd,</div><div class='ctx'> 				    struct v4l2_subdev_state *state,</div><div class='ctx'> 				    struct v4l2_subdev_frame_interval_enum *fie)</div><div class='hunk'>@@ -307,6 +284,33 @@ static int call_set_selection(struct v4l2_subdev *sd,</div><div class='ctx'> 	       sd-&gt;ops-&gt;pad-&gt;set_selection(sd, state, sel);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline int check_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				       struct v4l2_subdev_state *state,</div><div class='add'>+				       struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	if (!fi)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return check_which(fi-&gt;which) ? : check_pad(sd, fi-&gt;pad) ? :</div><div class='add'>+	       check_state(sd, state, fi-&gt;which, fi-&gt;pad, fi-&gt;stream);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int call_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *state,</div><div class='add'>+				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	return check_frame_interval(sd, state, fi) ? :</div><div class='add'>+	       sd-&gt;ops-&gt;pad-&gt;get_frame_interval(sd, state, fi);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int call_set_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *state,</div><div class='add'>+				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	return check_frame_interval(sd, state, fi) ? :</div><div class='add'>+	       sd-&gt;ops-&gt;pad-&gt;set_frame_interval(sd, state, fi);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int call_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,</div><div class='ctx'> 			       struct v4l2_mbus_frame_desc *fd)</div><div class='ctx'> {</div><div class='hunk'>@@ -479,6 +483,8 @@ static const struct v4l2_subdev_pad_ops v4l2_subdev_call_pad_wrappers = {</div><div class='ctx'> 	.enum_frame_interval	= call_enum_frame_interval_state,</div><div class='ctx'> 	.get_selection		= call_get_selection_state,</div><div class='ctx'> 	.set_selection		= call_set_selection_state,</div><div class='add'>+	.get_frame_interval	= call_get_frame_interval,</div><div class='add'>+	.set_frame_interval	= call_set_frame_interval,</div><div class='ctx'> 	.get_edid		= call_get_edid,</div><div class='ctx'> 	.set_edid		= call_set_edid,</div><div class='ctx'> 	.dv_timings_cap		= call_dv_timings_cap,</div><div class='hunk'>@@ -488,8 +494,6 @@ static const struct v4l2_subdev_pad_ops v4l2_subdev_call_pad_wrappers = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct v4l2_subdev_video_ops v4l2_subdev_call_video_wrappers = {</div><div class='del'>-	.g_frame_interval	= call_g_frame_interval,</div><div class='del'>-	.s_frame_interval	= call_s_frame_interval,</div><div class='ctx'> 	.s_stream		= call_s_stream,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -531,6 +535,17 @@ subdev_ioctl_get_state(struct v4l2_subdev *sd, struct v4l2_subdev_fh *subdev_fh,</div><div class='ctx'> 	case VIDIOC_SUBDEV_S_SELECTION:</div><div class='ctx'> 		which = ((struct v4l2_subdev_selection *)arg)-&gt;which;</div><div class='ctx'> 		break;</div><div class='add'>+	case VIDIOC_SUBDEV_G_FRAME_INTERVAL:</div><div class='add'>+	case VIDIOC_SUBDEV_S_FRAME_INTERVAL: {</div><div class='add'>+		struct v4l2_subdev_frame_interval *fi = arg;</div><div class='add'>+</div><div class='add'>+		if (!(subdev_fh-&gt;client_caps &amp;</div><div class='add'>+		      V4L2_SUBDEV_CLIENT_CAP_INTERVAL_USES_WHICH))</div><div class='add'>+			fi-&gt;which = V4L2_SUBDEV_FORMAT_ACTIVE;</div><div class='add'>+</div><div class='add'>+		which = fi-&gt;which;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='ctx'> 	case VIDIOC_SUBDEV_G_ROUTING:</div><div class='ctx'> 	case VIDIOC_SUBDEV_S_ROUTING:</div><div class='ctx'> 		which = ((struct v4l2_subdev_routing *)arg)-&gt;which;</div><div class='hunk'>@@ -781,20 +796,20 @@ static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg,</div><div class='ctx'> 			fi-&gt;stream = 0;</div><div class='ctx'> </div><div class='ctx'> 		memset(fi-&gt;reserved, 0, sizeof(fi-&gt;reserved));</div><div class='del'>-		return v4l2_subdev_call(sd, video, g_frame_interval, arg);</div><div class='add'>+		return v4l2_subdev_call(sd, pad, get_frame_interval, state, fi);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	case VIDIOC_SUBDEV_S_FRAME_INTERVAL: {</div><div class='ctx'> 		struct v4l2_subdev_frame_interval *fi = arg;</div><div class='ctx'> </div><div class='del'>-		if (ro_subdev)</div><div class='del'>-			return -EPERM;</div><div class='del'>-</div><div class='ctx'> 		if (!client_supports_streams)</div><div class='ctx'> 			fi-&gt;stream = 0;</div><div class='ctx'> </div><div class='add'>+		if (fi-&gt;which != V4L2_SUBDEV_FORMAT_TRY &amp;&amp; ro_subdev)</div><div class='add'>+			return -EPERM;</div><div class='add'>+</div><div class='ctx'> 		memset(fi-&gt;reserved, 0, sizeof(fi-&gt;reserved));</div><div class='del'>-		return v4l2_subdev_call(sd, video, s_frame_interval, arg);</div><div class='add'>+		return v4l2_subdev_call(sd, pad, set_frame_interval, state, fi);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	case VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL: {</div><div class='hunk'>@@ -989,7 +1004,8 @@ static long subdev_do_ioctl(struct file *file, unsigned int cmd, void *arg,</div><div class='ctx'> 			client_cap-&gt;capabilities &amp;= ~V4L2_SUBDEV_CLIENT_CAP_STREAMS;</div><div class='ctx'> </div><div class='ctx'> 		/* Filter out unsupported capabilities */</div><div class='del'>-		client_cap-&gt;capabilities &amp;= V4L2_SUBDEV_CLIENT_CAP_STREAMS;</div><div class='add'>+		client_cap-&gt;capabilities &amp;= (V4L2_SUBDEV_CLIENT_CAP_STREAMS |</div><div class='add'>+					     V4L2_SUBDEV_CLIENT_CAP_INTERVAL_USES_WHICH);</div><div class='ctx'> </div><div class='ctx'> 		subdev_fh-&gt;client_caps = client_cap-&gt;capabilities;</div><div class='ctx'> </div><div class='hunk'>@@ -1448,6 +1464,8 @@ __v4l2_subdev_state_alloc(struct v4l2_subdev *sd, const char *lock_name,</div><div class='ctx'> 	else</div><div class='ctx'> 		state-&gt;lock = &amp;state-&gt;_lock;</div><div class='ctx'> </div><div class='add'>+	state-&gt;sd = sd;</div><div class='add'>+</div><div class='ctx'> 	/* Drivers that support streams do not need the legacy pad config */</div><div class='ctx'> 	if (!(sd-&gt;flags &amp; V4L2_SUBDEV_FL_STREAMS) &amp;&amp; sd-&gt;entity.num_pads) {</div><div class='ctx'> 		state-&gt;pads = kvcalloc(sd-&gt;entity.num_pads,</div><div class='hunk'>@@ -1458,16 +1476,18 @@ __v4l2_subdev_state_alloc(struct v4l2_subdev *sd, const char *lock_name,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * There can be no race at this point, but we lock the state anyway to</div><div class='del'>-	 * satisfy lockdep checks.</div><div class='del'>-	 */</div><div class='del'>-	v4l2_subdev_lock_state(state);</div><div class='del'>-	ret = v4l2_subdev_call(sd, pad, init_cfg, state);</div><div class='del'>-	v4l2_subdev_unlock_state(state);</div><div class='add'>+	if (sd-&gt;internal_ops &amp;&amp; sd-&gt;internal_ops-&gt;init_state) {</div><div class='add'>+		/*</div><div class='add'>+		 * There can be no race at this point, but we lock the state</div><div class='add'>+		 * anyway to satisfy lockdep checks.</div><div class='add'>+		 */</div><div class='add'>+		v4l2_subdev_lock_state(state);</div><div class='add'>+		ret = sd-&gt;internal_ops-&gt;init_state(sd, state);</div><div class='add'>+		v4l2_subdev_unlock_state(state);</div><div class='ctx'> </div><div class='del'>-	if (ret &lt; 0 &amp;&amp; ret != -ENOIOCTLCMD)</div><div class='del'>-		goto err;</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return state;</div><div class='ctx'> </div><div class='hunk'>@@ -1517,7 +1537,8 @@ void v4l2_subdev_cleanup(struct v4l2_subdev *sd)</div><div class='ctx'> 	__v4l2_subdev_state_free(sd-&gt;active_state);</div><div class='ctx'> 	sd-&gt;active_state = NULL;</div><div class='ctx'> </div><div class='del'>-	if (list_empty(&amp;sd-&gt;async_subdev_endpoint_list))</div><div class='add'>+	/* Uninitialised sub-device, bail out here. */</div><div class='add'>+	if (!sd-&gt;async_subdev_endpoint_list.next)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(ase, ase_tmp, &amp;sd-&gt;async_subdev_endpoint_list,</div><div class='hunk'>@@ -1529,6 +1550,144 @@ void v4l2_subdev_cleanup(struct v4l2_subdev *sd)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(v4l2_subdev_cleanup);</div><div class='ctx'> </div><div class='add'>+struct v4l2_mbus_framefmt *</div><div class='add'>+__v4l2_subdev_state_get_format(struct v4l2_subdev_state *state,</div><div class='add'>+			       unsigned int pad, u32 stream)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON_ONCE(!state))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (state-&gt;pads) {</div><div class='add'>+		if (stream)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		if (pad &gt;= state-&gt;sd-&gt;entity.num_pads)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		return &amp;state-&gt;pads[pad].format;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(state-&gt;lock);</div><div class='add'>+</div><div class='add'>+	stream_configs = &amp;state-&gt;stream_configs;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='add'>+		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='add'>+		    stream_configs-&gt;configs[i].stream == stream)</div><div class='add'>+			return &amp;stream_configs-&gt;configs[i].fmt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__v4l2_subdev_state_get_format);</div><div class='add'>+</div><div class='add'>+struct v4l2_rect *</div><div class='add'>+__v4l2_subdev_state_get_crop(struct v4l2_subdev_state *state, unsigned int pad,</div><div class='add'>+			     u32 stream)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON_ONCE(!state))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (state-&gt;pads) {</div><div class='add'>+		if (stream)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		if (pad &gt;= state-&gt;sd-&gt;entity.num_pads)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		return &amp;state-&gt;pads[pad].crop;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(state-&gt;lock);</div><div class='add'>+</div><div class='add'>+	stream_configs = &amp;state-&gt;stream_configs;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='add'>+		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='add'>+		    stream_configs-&gt;configs[i].stream == stream)</div><div class='add'>+			return &amp;stream_configs-&gt;configs[i].crop;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__v4l2_subdev_state_get_crop);</div><div class='add'>+</div><div class='add'>+struct v4l2_rect *</div><div class='add'>+__v4l2_subdev_state_get_compose(struct v4l2_subdev_state *state,</div><div class='add'>+				unsigned int pad, u32 stream)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON_ONCE(!state))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	if (state-&gt;pads) {</div><div class='add'>+		if (stream)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		if (pad &gt;= state-&gt;sd-&gt;entity.num_pads)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		return &amp;state-&gt;pads[pad].compose;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(state-&gt;lock);</div><div class='add'>+</div><div class='add'>+	stream_configs = &amp;state-&gt;stream_configs;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='add'>+		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='add'>+		    stream_configs-&gt;configs[i].stream == stream)</div><div class='add'>+			return &amp;stream_configs-&gt;configs[i].compose;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__v4l2_subdev_state_get_compose);</div><div class='add'>+</div><div class='add'>+struct v4l2_fract *</div><div class='add'>+__v4l2_subdev_state_get_interval(struct v4l2_subdev_state *state,</div><div class='add'>+				 unsigned int pad, u32 stream)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!state))</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(state-&gt;lock);</div><div class='add'>+</div><div class='add'>+	if (state-&gt;pads) {</div><div class='add'>+		if (stream)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		if (pad &gt;= state-&gt;sd-&gt;entity.num_pads)</div><div class='add'>+			return NULL;</div><div class='add'>+</div><div class='add'>+		return &amp;state-&gt;pads[pad].interval;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	lockdep_assert_held(state-&gt;lock);</div><div class='add'>+</div><div class='add'>+	stream_configs = &amp;state-&gt;stream_configs;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='add'>+		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='add'>+		    stream_configs-&gt;configs[i].stream == stream)</div><div class='add'>+			return &amp;stream_configs-&gt;configs[i].interval;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__v4l2_subdev_state_get_interval);</div><div class='add'>+</div><div class='ctx'> #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='hunk'>@@ -1585,14 +1744,7 @@ int v4l2_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *state,</div><div class='ctx'> {</div><div class='ctx'> 	struct v4l2_mbus_framefmt *fmt;</div><div class='ctx'> </div><div class='del'>-	if (sd-&gt;flags &amp; V4L2_SUBDEV_FL_STREAMS)</div><div class='del'>-		fmt = v4l2_subdev_state_get_stream_format(state, format-&gt;pad,</div><div class='del'>-							  format-&gt;stream);</div><div class='del'>-	else if (format-&gt;pad &lt; sd-&gt;entity.num_pads &amp;&amp; format-&gt;stream == 0)</div><div class='del'>-		fmt = v4l2_subdev_get_pad_format(sd, state, format-&gt;pad);</div><div class='del'>-	else</div><div class='del'>-		fmt = NULL;</div><div class='del'>-</div><div class='add'>+	fmt = v4l2_subdev_state_get_format(state, format-&gt;pad, format-&gt;stream);</div><div class='ctx'> 	if (!fmt)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1602,6 +1754,22 @@ int v4l2_subdev_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *state,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(v4l2_subdev_get_fmt);</div><div class='ctx'> </div><div class='add'>+int v4l2_subdev_get_frame_interval(struct v4l2_subdev *sd,</div><div class='add'>+				   struct v4l2_subdev_state *state,</div><div class='add'>+				   struct v4l2_subdev_frame_interval *fi)</div><div class='add'>+{</div><div class='add'>+	struct v4l2_fract *interval;</div><div class='add'>+</div><div class='add'>+	interval = v4l2_subdev_state_get_interval(state, fi-&gt;pad, fi-&gt;stream);</div><div class='add'>+	if (!interval)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fi-&gt;interval = *interval;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(v4l2_subdev_get_frame_interval);</div><div class='add'>+</div><div class='ctx'> int v4l2_subdev_set_routing(struct v4l2_subdev *sd,</div><div class='ctx'> 			    struct v4l2_subdev_state *state,</div><div class='ctx'> 			    const struct v4l2_subdev_krouting *routing)</div><div class='hunk'>@@ -1682,69 +1850,6 @@ int v4l2_subdev_set_routing_with_fmt(struct v4l2_subdev *sd,</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(v4l2_subdev_set_routing_with_fmt);</div><div class='ctx'> </div><div class='del'>-struct v4l2_mbus_framefmt *</div><div class='del'>-v4l2_subdev_state_get_stream_format(struct v4l2_subdev_state *state,</div><div class='del'>-				    unsigned int pad, u32 stream)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='del'>-	unsigned int i;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(state-&gt;lock);</div><div class='del'>-</div><div class='del'>-	stream_configs = &amp;state-&gt;stream_configs;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='del'>-		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='del'>-		    stream_configs-&gt;configs[i].stream == stream)</div><div class='del'>-			return &amp;stream_configs-&gt;configs[i].fmt;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(v4l2_subdev_state_get_stream_format);</div><div class='del'>-</div><div class='del'>-struct v4l2_rect *</div><div class='del'>-v4l2_subdev_state_get_stream_crop(struct v4l2_subdev_state *state,</div><div class='del'>-				  unsigned int pad, u32 stream)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='del'>-	unsigned int i;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(state-&gt;lock);</div><div class='del'>-</div><div class='del'>-	stream_configs = &amp;state-&gt;stream_configs;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='del'>-		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='del'>-		    stream_configs-&gt;configs[i].stream == stream)</div><div class='del'>-			return &amp;stream_configs-&gt;configs[i].crop;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(v4l2_subdev_state_get_stream_crop);</div><div class='del'>-</div><div class='del'>-struct v4l2_rect *</div><div class='del'>-v4l2_subdev_state_get_stream_compose(struct v4l2_subdev_state *state,</div><div class='del'>-				     unsigned int pad, u32 stream)</div><div class='del'>-{</div><div class='del'>-	struct v4l2_subdev_stream_configs *stream_configs;</div><div class='del'>-	unsigned int i;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(state-&gt;lock);</div><div class='del'>-</div><div class='del'>-	stream_configs = &amp;state-&gt;stream_configs;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; stream_configs-&gt;num_configs; ++i) {</div><div class='del'>-		if (stream_configs-&gt;configs[i].pad == pad &amp;&amp;</div><div class='del'>-		    stream_configs-&gt;configs[i].stream == stream)</div><div class='del'>-			return &amp;stream_configs-&gt;configs[i].compose;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-EXPORT_SYMBOL_GPL(v4l2_subdev_state_get_stream_compose);</div><div class='del'>-</div><div class='ctx'> int v4l2_subdev_routing_find_opposite_end(const struct v4l2_subdev_krouting *routing,</div><div class='ctx'> 					  u32 pad, u32 stream, u32 *other_pad,</div><div class='ctx'> 					  u32 *other_stream)</div><div class='hunk'>@@ -1789,8 +1894,7 @@ v4l2_subdev_state_get_opposite_stream_format(struct v4l2_subdev_state *state,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	return v4l2_subdev_state_get_stream_format(state, other_pad,</div><div class='del'>-						   other_stream);</div><div class='add'>+	return v4l2_subdev_state_get_format(state, other_pad, other_stream);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(v4l2_subdev_state_get_opposite_stream_format);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c<br/>index a7ab3d377206..5028467b2dc9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/brcmstb_dpfe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/brcmstb_dpfe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/brcmstb_dpfe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/brcmstb_dpfe.c</a></div><div class='hunk'>@@ -909,13 +909,11 @@ static int brcmstb_dpfe_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int brcmstb_dpfe_remove(struct platform_device *pdev)</div><div class='add'>+static void brcmstb_dpfe_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	sysfs_remove_groups(&amp;pdev-&gt;dev.kobj, priv-&gt;dpfe_api-&gt;sysfs_attrs);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id brcmstb_dpfe_of_match[] = {</div><div class='hunk'>@@ -936,7 +934,7 @@ static struct platform_driver brcmstb_dpfe_driver = {</div><div class='ctx'> 		.of_match_table = brcmstb_dpfe_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = brcmstb_dpfe_probe,</div><div class='del'>-	.remove	= brcmstb_dpfe_remove,</div><div class='add'>+	.remove_new = brcmstb_dpfe_remove,</div><div class='ctx'> 	.resume = brcmstb_dpfe_resume,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c<br/>index a6ea51996522..ea9213f7152e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/brcmstb_memc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/brcmstb_memc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/brcmstb_memc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/brcmstb_memc.c</a></div><div class='hunk'>@@ -152,13 +152,11 @@ static int brcmstb_memc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int brcmstb_memc_remove(struct platform_device *pdev)</div><div class='add'>+static void brcmstb_memc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='ctx'> 	sysfs_remove_group(&amp;dev-&gt;kobj, &amp;dev_attr_group);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> enum brcmstb_memc_hwtype {</div><div class='hunk'>@@ -284,7 +282,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(brcmstb_memc_pm_ops, brcmstb_memc_suspend,</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver brcmstb_memc_driver = {</div><div class='ctx'> 	.probe = brcmstb_memc_probe,</div><div class='del'>-	.remove = brcmstb_memc_remove,</div><div class='add'>+	.remove_new = brcmstb_memc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "brcmstb_memc",</div><div class='ctx'> 		.of_match_table	= brcmstb_memc_of_match,</div><div class='head'>diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c<br/>index f305643209f0..434982545be6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/emif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/emif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/emif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/emif.c</a></div><div class='hunk'>@@ -1159,13 +1159,11 @@ error:</div><div class='ctx'> 	return -ENODEV;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit emif_remove(struct platform_device *pdev)</div><div class='add'>+static void __exit emif_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct emif_data *emif = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	emif_debugfs_exit(emif);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void emif_shutdown(struct platform_device *pdev)</div><div class='hunk'>@@ -1185,7 +1183,7 @@ MODULE_DEVICE_TABLE(of, emif_of_match);</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver emif_driver = {</div><div class='del'>-	.remove		= __exit_p(emif_remove),</div><div class='add'>+	.remove_new	= __exit_p(emif_remove),</div><div class='ctx'> 	.shutdown	= emif_shutdown,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "emif",</div><div class='head'>diff --git a/drivers/memory/fsl-corenet-cf.c b/drivers/memory/fsl-corenet-cf.c<br/>index 8096c4f33303..f47d05f7c5c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/fsl-corenet-cf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/fsl-corenet-cf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/fsl-corenet-cf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/fsl-corenet-cf.c</a></div><div class='hunk'>@@ -223,7 +223,7 @@ static int ccf_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ccf_remove(struct platform_device *pdev)</div><div class='add'>+static void ccf_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ccf_private *ccf = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -241,8 +241,6 @@ static int ccf_remove(struct platform_device *pdev)</div><div class='ctx'> 		iowrite32be(0, &amp;ccf-&gt;err_regs-&gt;errinten);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ccf_driver = {</div><div class='hunk'>@@ -251,7 +249,7 @@ static struct platform_driver ccf_driver = {</div><div class='ctx'> 		.of_match_table = ccf_matches,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = ccf_probe,</div><div class='del'>-	.remove = ccf_remove,</div><div class='add'>+	.remove_new = ccf_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(ccf_driver);</div><div class='head'>diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c<br/>index 2509e5152036..15e919c24f81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/fsl_ifc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/fsl_ifc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/fsl_ifc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/fsl_ifc.c</a></div><div class='hunk'>@@ -84,7 +84,7 @@ static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fsl_ifc_ctrl_remove(struct platform_device *dev)</div><div class='add'>+static void fsl_ifc_ctrl_remove(struct platform_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&amp;dev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -98,8 +98,6 @@ static int fsl_ifc_ctrl_remove(struct platform_device *dev)</div><div class='ctx'> 	iounmap(ctrl-&gt;gregs);</div><div class='ctx'> </div><div class='ctx'> 	dev_set_drvdata(&amp;dev-&gt;dev, NULL);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -318,7 +316,7 @@ static struct platform_driver fsl_ifc_ctrl_driver = {</div><div class='ctx'> 		.of_match_table = fsl_ifc_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe       = fsl_ifc_ctrl_probe,</div><div class='del'>-	.remove      = fsl_ifc_ctrl_remove,</div><div class='add'>+	.remove_new  = fsl_ifc_ctrl_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init fsl_ifc_init(void)</div><div class='head'>diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c<br/>index e5a93e7da15f..fb6db2ffe71b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/jz4780-nemc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/jz4780-nemc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/jz4780-nemc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/jz4780-nemc.c</a></div><div class='hunk'>@@ -384,12 +384,11 @@ static int jz4780_nemc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int jz4780_nemc_remove(struct platform_device *pdev)</div><div class='add'>+static void jz4780_nemc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct jz4780_nemc *nemc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(nemc-&gt;clk);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct jz_soc_info jz4740_soc_info = {</div><div class='hunk'>@@ -408,7 +407,7 @@ static const struct of_device_id jz4780_nemc_dt_match[] = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver jz4780_nemc_driver = {</div><div class='ctx'> 	.probe		= jz4780_nemc_probe,</div><div class='del'>-	.remove		= jz4780_nemc_remove,</div><div class='add'>+	.remove_new	= jz4780_nemc_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name	= "jz4780-nemc",</div><div class='ctx'> 		.of_match_table = of_match_ptr(jz4780_nemc_dt_match),</div><div class='head'>diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c<br/>index 6523cb510518..572c7fbdcfd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/mtk-smi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/mtk-smi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/mtk-smi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/mtk-smi.c</a></div><div class='hunk'>@@ -566,14 +566,13 @@ err_pm_disable:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mtk_smi_larb_remove(struct platform_device *pdev)</div><div class='add'>+static void mtk_smi_larb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_smi_larb *larb = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	device_link_remove(&amp;pdev-&gt;dev, larb-&gt;smi_common_dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	component_del(&amp;pdev-&gt;dev, &amp;mtk_smi_larb_component_ops);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused mtk_smi_larb_resume(struct device *dev)</div><div class='hunk'>@@ -616,7 +615,7 @@ static const struct dev_pm_ops smi_larb_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mtk_smi_larb_driver = {</div><div class='ctx'> 	.probe	= mtk_smi_larb_probe,</div><div class='del'>-	.remove	= mtk_smi_larb_remove,</div><div class='add'>+	.remove_new = mtk_smi_larb_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = "mtk-smi-larb",</div><div class='ctx'> 		.of_match_table = mtk_smi_larb_of_ids,</div><div class='hunk'>@@ -795,14 +794,13 @@ static int mtk_smi_common_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mtk_smi_common_remove(struct platform_device *pdev)</div><div class='add'>+static void mtk_smi_common_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtk_smi *common = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (common-&gt;plat-&gt;type == MTK_SMI_GEN2_SUB_COMM)</div><div class='ctx'> 		device_link_remove(&amp;pdev-&gt;dev, common-&gt;smi_common_dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused mtk_smi_common_resume(struct device *dev)</div><div class='hunk'>@@ -842,7 +840,7 @@ static const struct dev_pm_ops smi_common_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mtk_smi_common_driver = {</div><div class='ctx'> 	.probe	= mtk_smi_common_probe,</div><div class='del'>-	.remove = mtk_smi_common_remove,</div><div class='add'>+	.remove_new = mtk_smi_common_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = "mtk-smi-common",</div><div class='ctx'> 		.of_match_table = mtk_smi_common_of_ids,</div><div class='head'>diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c<br/>index d78f73db37c8..80d038884207 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/omap-gpmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/omap-gpmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/omap-gpmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/omap-gpmc.c</a></div><div class='hunk'>@@ -2690,7 +2690,7 @@ gpio_init_failed:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gpmc_remove(struct platform_device *pdev)</div><div class='add'>+static void gpmc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct gpmc_device *gpmc = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -2702,8 +2702,6 @@ static int gpmc_remove(struct platform_device *pdev)</div><div class='ctx'> 	gpmc_mem_exit();</div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM_SLEEP</div><div class='hunk'>@@ -2747,7 +2745,7 @@ MODULE_DEVICE_TABLE(of, gpmc_dt_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver gpmc_driver = {</div><div class='ctx'> 	.probe		= gpmc_probe,</div><div class='del'>-	.remove		= gpmc_remove,</div><div class='add'>+	.remove_new	= gpmc_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= DEVICE_NAME,</div><div class='ctx'> 		.of_match_table = of_match_ptr(gpmc_dt_ids),</div><div class='head'>diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c<br/>index 9695b2d3ae59..3167826b236a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/renesas-rpc-if.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/renesas-rpc-if.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/renesas-rpc-if.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/renesas-rpc-if.c</a></div><div class='hunk'>@@ -777,13 +777,11 @@ static int rpcif_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rpcif_remove(struct platform_device *pdev)</div><div class='add'>+static void rpcif_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct rpcif_priv *rpc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	platform_device_unregister(rpc-&gt;vdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id rpcif_of_match[] = {</div><div class='hunk'>@@ -797,7 +795,7 @@ MODULE_DEVICE_TABLE(of, rpcif_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver rpcif_driver = {</div><div class='ctx'> 	.probe	= rpcif_probe,</div><div class='del'>-	.remove	= rpcif_remove,</div><div class='add'>+	.remove_new = rpcif_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name =	"rpc-if",</div><div class='ctx'> 		.of_match_table = rpcif_of_match,</div><div class='head'>diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c<br/>index 6d019dbd721c..da7ecd921c72 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/samsung/exynos5422-dmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/samsung/exynos5422-dmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/samsung/exynos5422-dmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/samsung/exynos5422-dmc.c</a></div><div class='hunk'>@@ -1558,7 +1558,7 @@ remove_clocks:</div><div class='ctx'>  * clean the device's resources. It just calls explicitly disable function for</div><div class='ctx'>  * the performance counters.</div><div class='ctx'>  */</div><div class='del'>-static int exynos5_dmc_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos5_dmc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos5_dmc *dmc = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -1569,8 +1569,6 @@ static int exynos5_dmc_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(dmc-&gt;mout_bpll);</div><div class='ctx'> 	clk_disable_unprepare(dmc-&gt;fout_bpll);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id exynos5_dmc_of_match[] = {</div><div class='hunk'>@@ -1581,7 +1579,7 @@ MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver exynos5_dmc_platdrv = {</div><div class='ctx'> 	.probe	= exynos5_dmc_probe,</div><div class='del'>-	.remove = exynos5_dmc_remove,</div><div class='add'>+	.remove_new = exynos5_dmc_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name	= "exynos5-dmc",</div><div class='ctx'> 		.of_match_table = exynos5_dmc_of_match,</div><div class='head'>diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c<br/>index 9015e8277dc8..47d0ea5f1616 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/stm32-fmc2-ebi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/stm32-fmc2-ebi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/stm32-fmc2-ebi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/stm32-fmc2-ebi.c</a></div><div class='hunk'>@@ -1146,7 +1146,7 @@ err_release:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stm32_fmc2_ebi_remove(struct platform_device *pdev)</div><div class='add'>+static void stm32_fmc2_ebi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1154,8 +1154,6 @@ static int stm32_fmc2_ebi_remove(struct platform_device *pdev)</div><div class='ctx'> 	stm32_fmc2_ebi_disable_banks(ebi);</div><div class='ctx'> 	stm32_fmc2_ebi_disable(ebi);</div><div class='ctx'> 	clk_disable_unprepare(ebi-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)</div><div class='hunk'>@@ -1197,7 +1195,7 @@ MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver stm32_fmc2_ebi_driver = {</div><div class='ctx'> 	.probe	= stm32_fmc2_ebi_probe,</div><div class='del'>-	.remove	= stm32_fmc2_ebi_remove,</div><div class='add'>+	.remove_new = stm32_fmc2_ebi_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = "stm32_fmc2_ebi",</div><div class='ctx'> 		.of_match_table = stm32_fmc2_ebi_match,</div><div class='head'>diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c<br/>index 4007f4e16d74..fcd4aea48bda 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra186-emc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/tegra/tegra186-emc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra186-emc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra186-emc.c</a></div><div class='hunk'>@@ -378,7 +378,7 @@ put_bpmp:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tegra186_emc_remove(struct platform_device *pdev)</div><div class='add'>+static void tegra186_emc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tegra_mc *mc = dev_get_drvdata(pdev-&gt;dev.parent);</div><div class='ctx'> 	struct tegra186_emc *emc = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -387,8 +387,6 @@ static int tegra186_emc_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	mc-&gt;bpmp = NULL;</div><div class='ctx'> 	tegra_bpmp_put(emc-&gt;bpmp);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id tegra186_emc_of_match[] = {</div><div class='hunk'>@@ -413,7 +411,7 @@ static struct platform_driver tegra186_emc_driver = {</div><div class='ctx'> 		.sync_state = icc_sync_state,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = tegra186_emc_probe,</div><div class='del'>-	.remove = tegra186_emc_remove,</div><div class='add'>+	.remove_new = tegra186_emc_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(tegra186_emc_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c<br/>index 533f85a4b2bd..1b3183951bfe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra186.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/tegra/tegra186.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra186.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra186.c</a></div><div class='hunk'>@@ -75,6 +75,9 @@ static void tegra186_mc_client_sid_override(struct tegra_mc *mc,</div><div class='ctx'> {</div><div class='ctx'> 	u32 value, old;</div><div class='ctx'> </div><div class='add'>+	if (client-&gt;regs.sid.security == 0 &amp;&amp; client-&gt;regs.sid.override == 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	value = readl(mc-&gt;regs + client-&gt;regs.sid.security);</div><div class='ctx'> 	if ((value &amp; MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -111,9 +114,12 @@ static void tegra186_mc_client_sid_override(struct tegra_mc *mc,</div><div class='ctx'> static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> #if IS_ENABLED(CONFIG_IOMMU_API)</div><div class='del'>-	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);</div><div class='ctx'> 	struct of_phandle_args args;</div><div class='ctx'> 	unsigned int i, index = 0;</div><div class='add'>+	u32 sid;</div><div class='add'>+</div><div class='add'>+	if (!tegra_dev_iommu_get_stream_id(dev, &amp;sid))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	while (!of_parse_phandle_with_args(dev-&gt;of_node, "interconnects", "#interconnect-cells",</div><div class='ctx'> 					   index, &amp;args)) {</div><div class='hunk'>@@ -121,11 +127,10 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)</div><div class='ctx'> 			for (i = 0; i &lt; mc-&gt;soc-&gt;num_clients; i++) {</div><div class='ctx'> 				const struct tegra_mc_client *client = &amp;mc-&gt;soc-&gt;clients[i];</div><div class='ctx'> </div><div class='del'>-				if (client-&gt;id == args.args[0]) {</div><div class='del'>-					u32 sid = fwspec-&gt;ids[0] &amp; MC_SID_STREAMID_OVERRIDE_MASK;</div><div class='del'>-</div><div class='del'>-					tegra186_mc_client_sid_override(mc, client, sid);</div><div class='del'>-				}</div><div class='add'>+				if (client-&gt;id == args.args[0])</div><div class='add'>+					tegra186_mc_client_sid_override(</div><div class='add'>+						mc, client,</div><div class='add'>+						sid &amp; MC_SID_STREAMID_OVERRIDE_MASK);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -136,9 +141,25 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int tegra186_mc_resume(struct tegra_mc *mc)</div><div class='add'>+{</div><div class='add'>+#if IS_ENABLED(CONFIG_IOMMU_API)</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; mc-&gt;soc-&gt;num_clients; i++) {</div><div class='add'>+		const struct tegra_mc_client *client = &amp;mc-&gt;soc-&gt;clients[i];</div><div class='add'>+</div><div class='add'>+		tegra186_mc_client_sid_override(mc, client, client-&gt;sid);</div><div class='add'>+	}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct tegra_mc_ops tegra186_mc_ops = {</div><div class='ctx'> 	.probe = tegra186_mc_probe,</div><div class='ctx'> 	.remove = tegra186_mc_remove,</div><div class='add'>+	.resume = tegra186_mc_resume,</div><div class='ctx'> 	.probe_device = tegra186_mc_probe_device,</div><div class='ctx'> 	.handle_irq = tegra30_mc_handle_irq,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c<br/>index 3300bde47c13..78ca1d6c0977 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra210-emc-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/tegra/tegra210-emc-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/tegra/tegra210-emc-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/tegra/tegra210-emc-core.c</a></div><div class='hunk'>@@ -1985,15 +1985,13 @@ release:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tegra210_emc_remove(struct platform_device *pdev)</div><div class='add'>+static void tegra210_emc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tegra210_emc *emc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	debugfs_remove_recursive(emc-&gt;debugfs.root);</div><div class='ctx'> 	tegra210_clk_emc_detach(emc-&gt;clk);</div><div class='ctx'> 	of_reserved_mem_device_release(emc-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused tegra210_emc_suspend(struct device *dev)</div><div class='hunk'>@@ -2053,7 +2051,7 @@ static struct platform_driver tegra210_emc_driver = {</div><div class='ctx'> 		.pm = &amp;tegra210_emc_pm_ops,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = tegra210_emc_probe,</div><div class='del'>-	.remove = tegra210_emc_remove,</div><div class='add'>+	.remove_new = tegra210_emc_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(tegra210_emc_driver);</div><div class='head'>diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c<br/>index f81e7df8798a..e192db9e0e4b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/ti-aemif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/ti-aemif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/ti-aemif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/ti-aemif.c</a></div><div class='hunk'>@@ -427,17 +427,16 @@ error:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aemif_remove(struct platform_device *pdev)</div><div class='add'>+static void aemif_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct aemif_device *aemif = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(aemif-&gt;clk);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver aemif_driver = {</div><div class='ctx'> 	.probe = aemif_probe,</div><div class='del'>-	.remove = aemif_remove,</div><div class='add'>+	.remove_new = aemif_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "ti-aemif",</div><div class='ctx'> 		.of_match_table = of_match_ptr(aemif_of_match),</div><div class='head'>diff --git a/drivers/memory/ti-emif-pm.c b/drivers/memory/ti-emif-pm.c<br/>index cef0d3beb63b..592f70e9c8e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/memory/ti-emif-pm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/memory/ti-emif-pm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/memory/ti-emif-pm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/memory/ti-emif-pm.c</a></div><div class='hunk'>@@ -315,15 +315,13 @@ fail_free_sram:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ti_emif_remove(struct platform_device *pdev)</div><div class='add'>+static void ti_emif_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ti_emif_data *emif_data = emif_instance;</div><div class='ctx'> </div><div class='ctx'> 	emif_instance = NULL;</div><div class='ctx'> </div><div class='ctx'> 	ti_emif_free_sram(emif_data);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pm_ops ti_emif_pm_ops = {</div><div class='hunk'>@@ -332,7 +330,7 @@ static const struct dev_pm_ops ti_emif_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ti_emif_driver = {</div><div class='ctx'> 	.probe = ti_emif_probe,</div><div class='del'>-	.remove = ti_emif_remove,</div><div class='add'>+	.remove_new = ti_emif_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = KBUILD_MODNAME,</div><div class='ctx'> 		.of_match_table = ti_emif_of_match,</div><div class='head'>diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig<br/>index 90ce58fd629e..e7a6e45b9fac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/Kconfig</a></div><div class='hunk'>@@ -1483,6 +1483,7 @@ config MFD_SYSCON</div><div class='ctx'> </div><div class='ctx'> config MFD_TI_AM335X_TSCADC</div><div class='ctx'> 	tristate "TI ADC / Touch Screen chip support"</div><div class='add'>+	depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST</div><div class='ctx'> 	select MFD_CORE</div><div class='ctx'> 	select REGMAP</div><div class='ctx'> 	select REGMAP_MMIO</div><div class='hunk'>@@ -2255,7 +2256,7 @@ config MFD_VEXPRESS_SYSREG</div><div class='ctx'> config RAVE_SP_CORE</div><div class='ctx'> 	tristate "RAVE SP MCU core driver"</div><div class='ctx'> 	depends on SERIAL_DEV_BUS</div><div class='del'>-	select CRC_CCITT</div><div class='add'>+	select CRC_ITU_T</div><div class='ctx'> 	help</div><div class='ctx'> 	  Select this to get support for the Supervisory Processor</div><div class='ctx'> 	  device found on several devices in RAVE line of hardware.</div><div class='head'>diff --git a/drivers/mfd/ab8500-sysctrl.c b/drivers/mfd/ab8500-sysctrl.c<br/>index eeeb62415f53..8f3ebe651eea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/ab8500-sysctrl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/ab8500-sysctrl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/ab8500-sysctrl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/ab8500-sysctrl.c</a></div><div class='hunk'>@@ -30,7 +30,7 @@ static void ab8500_power_off(void)</div><div class='ctx'> {</div><div class='ctx'> 	sigset_t old;</div><div class='ctx'> 	sigset_t all;</div><div class='del'>-	static const char * const pss[] = {"ab8500_ac", "pm2301", "ab8500_usb"};</div><div class='add'>+	static const char * const pss[] = {"ab8500_ac", "ab8500_usb"};</div><div class='ctx'> 	int i;</div><div class='ctx'> 	bool charger_present = false;</div><div class='ctx'> 	union power_supply_propval val;</div><div class='hunk'>@@ -140,14 +140,12 @@ static int ab8500_sysctrl_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ab8500_sysctrl_remove(struct platform_device *pdev)</div><div class='add'>+static void ab8500_sysctrl_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	sysctrl_dev = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (pm_power_off == ab8500_power_off)</div><div class='ctx'> 		pm_power_off = NULL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id ab8500_sysctrl_match[] = {</div><div class='hunk'>@@ -161,7 +159,7 @@ static struct platform_driver ab8500_sysctrl_driver = {</div><div class='ctx'> 		.of_match_table = ab8500_sysctrl_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = ab8500_sysctrl_probe,</div><div class='del'>-	.remove = ab8500_sysctrl_remove,</div><div class='add'>+	.remove_new = ab8500_sysctrl_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init ab8500_sysctrl_init(void)</div><div class='head'>diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c<br/>index 79d393b602bf..603b1cd52785 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/cros_ec_dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/cros_ec_dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/cros_ec_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/cros_ec_dev.c</a></div><div class='hunk'>@@ -288,13 +288,12 @@ failed:</div><div class='ctx'> 	return retval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ec_device_remove(struct platform_device *pdev)</div><div class='add'>+static void ec_device_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct cros_ec_dev *ec = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	mfd_remove_devices(ec-&gt;dev);</div><div class='ctx'> 	device_unregister(&amp;ec-&gt;class_dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct platform_device_id cros_ec_id[] = {</div><div class='hunk'>@@ -309,7 +308,7 @@ static struct platform_driver cros_ec_dev_driver = {</div><div class='ctx'> 	},</div><div class='ctx'> 	.id_table = cros_ec_id,</div><div class='ctx'> 	.probe = ec_device_probe,</div><div class='del'>-	.remove = ec_device_remove,</div><div class='add'>+	.remove_new = ec_device_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init cros_ec_dev_init(void)</div><div class='head'>diff --git a/drivers/mfd/cs42l43-sdw.c b/drivers/mfd/cs42l43-sdw.c<br/>index 7392b3d2e6b9..1d85bbf8cdd5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/cs42l43-sdw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/cs42l43-sdw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/cs42l43-sdw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/cs42l43-sdw.c</a></div><div class='hunk'>@@ -6,24 +6,23 @@</div><div class='ctx'>  *                         Cirrus Logic International Semiconductor Ltd.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/cs42l43-regs.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='ctx'> #include &lt;linux/soundwire/sdw.h&gt;</div><div class='ctx'> #include &lt;linux/soundwire/sdw_registers.h&gt;</div><div class='ctx'> #include &lt;linux/soundwire/sdw_type.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "cs42l43.h"</div><div class='ctx'> </div><div class='del'>-enum cs42l43_sdw_ports {</div><div class='del'>-	CS42L43_DMIC_DEC_ASP_PORT = 1,</div><div class='del'>-	CS42L43_SPK_TX_PORT,</div><div class='del'>-	CS42L43_SPDIF_HP_PORT,</div><div class='del'>-	CS42L43_SPK_RX_PORT,</div><div class='del'>-	CS42L43_ASP_PORT,</div><div class='del'>-};</div><div class='add'>+#define CS42L43_SDW_PORT(port, chans) { \</div><div class='add'>+	.num = port, \</div><div class='add'>+	.max_ch = chans, \</div><div class='add'>+	.type = SDW_DPN_FULL, \</div><div class='add'>+	.max_word = 24, \</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static const struct regmap_config cs42l43_sdw_regmap = {</div><div class='ctx'> 	.reg_bits		= 32,</div><div class='hunk'>@@ -42,65 +41,48 @@ static const struct regmap_config cs42l43_sdw_regmap = {</div><div class='ctx'> 	.num_reg_defaults	= ARRAY_SIZE(cs42l43_reg_default),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct sdw_dpn_prop cs42l43_src_port_props[] = {</div><div class='add'>+	CS42L43_SDW_PORT(1, 4),</div><div class='add'>+	CS42L43_SDW_PORT(2, 2),</div><div class='add'>+	CS42L43_SDW_PORT(3, 2),</div><div class='add'>+	CS42L43_SDW_PORT(4, 2),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct sdw_dpn_prop cs42l43_sink_port_props[] = {</div><div class='add'>+	CS42L43_SDW_PORT(5, 2),</div><div class='add'>+	CS42L43_SDW_PORT(6, 2),</div><div class='add'>+	CS42L43_SDW_PORT(7, 2),</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int cs42l43_read_prop(struct sdw_slave *sdw)</div><div class='ctx'> {</div><div class='ctx'> 	struct sdw_slave_prop *prop = &amp;sdw-&gt;prop;</div><div class='ctx'> 	struct device *dev = &amp;sdw-&gt;dev;</div><div class='del'>-	struct sdw_dpn_prop *dpn;</div><div class='del'>-	unsigned long addr;</div><div class='del'>-	int nval;</div><div class='ctx'> 	int i;</div><div class='del'>-	u32 bit;</div><div class='ctx'> </div><div class='ctx'> 	prop-&gt;use_domain_irq = true;</div><div class='ctx'> 	prop-&gt;paging_support = true;</div><div class='ctx'> 	prop-&gt;wake_capable = true;</div><div class='del'>-	prop-&gt;source_ports = BIT(CS42L43_DMIC_DEC_ASP_PORT) | BIT(CS42L43_SPK_TX_PORT);</div><div class='del'>-	prop-&gt;sink_ports = BIT(CS42L43_SPDIF_HP_PORT) |</div><div class='del'>-			   BIT(CS42L43_SPK_RX_PORT) | BIT(CS42L43_ASP_PORT);</div><div class='ctx'> 	prop-&gt;quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;</div><div class='ctx'> 	prop-&gt;scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY |</div><div class='ctx'> 			      SDW_SCP_INT1_IMPL_DEF;</div><div class='ctx'> </div><div class='del'>-	nval = hweight32(prop-&gt;source_ports);</div><div class='del'>-	prop-&gt;src_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop-&gt;src_dpn_prop),</div><div class='del'>-					  GFP_KERNEL);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(cs42l43_src_port_props); i++)</div><div class='add'>+		prop-&gt;source_ports |= BIT(cs42l43_src_port_props[i].num);</div><div class='add'>+</div><div class='add'>+	prop-&gt;src_dpn_prop = devm_kmemdup(dev, cs42l43_src_port_props,</div><div class='add'>+					  sizeof(cs42l43_src_port_props), GFP_KERNEL);</div><div class='ctx'> 	if (!prop-&gt;src_dpn_prop)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	i = 0;</div><div class='del'>-	dpn = prop-&gt;src_dpn_prop;</div><div class='del'>-	addr = prop-&gt;source_ports;</div><div class='del'>-	for_each_set_bit(bit, &amp;addr, 32) {</div><div class='del'>-		dpn[i].num = bit;</div><div class='del'>-		dpn[i].max_ch = 2;</div><div class='del'>-		dpn[i].type = SDW_DPN_FULL;</div><div class='del'>-		dpn[i].max_word = 24;</div><div class='del'>-		i++;</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * All ports are 2 channels max, except the first one,</div><div class='del'>-	 * CS42L43_DMIC_DEC_ASP_PORT.</div><div class='del'>-	 */</div><div class='del'>-	dpn[CS42L43_DMIC_DEC_ASP_PORT].max_ch = 4;</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(cs42l43_sink_port_props); i++)</div><div class='add'>+		prop-&gt;sink_ports |= BIT(cs42l43_sink_port_props[i].num);</div><div class='ctx'> </div><div class='del'>-	nval = hweight32(prop-&gt;sink_ports);</div><div class='del'>-	prop-&gt;sink_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop-&gt;sink_dpn_prop),</div><div class='del'>-					   GFP_KERNEL);</div><div class='add'>+	prop-&gt;sink_dpn_prop = devm_kmemdup(dev, cs42l43_sink_port_props,</div><div class='add'>+					   sizeof(cs42l43_sink_port_props), GFP_KERNEL);</div><div class='ctx'> 	if (!prop-&gt;sink_dpn_prop)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	i = 0;</div><div class='del'>-	dpn = prop-&gt;sink_dpn_prop;</div><div class='del'>-	addr = prop-&gt;sink_ports;</div><div class='del'>-	for_each_set_bit(bit, &amp;addr, 32) {</div><div class='del'>-		dpn[i].num = bit;</div><div class='del'>-		dpn[i].max_ch = 2;</div><div class='del'>-		dpn[i].type = SDW_DPN_FULL;</div><div class='del'>-		dpn[i].max_word = 24;</div><div class='del'>-		i++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c<br/>index 45da007d3e70..73a22107900c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/da9062-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/da9062-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/da9062-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/da9062-core.c</a></div><div class='hunk'>@@ -588,16 +588,8 @@ static struct regmap_config da9062_regmap_config = {</div><div class='ctx'> 	.volatile_table = &amp;da9062_aa_volatile_table,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct of_device_id da9062_dt_ids[] = {</div><div class='del'>-	{ .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, },</div><div class='del'>-	{ .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, },</div><div class='del'>-	{ }</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(of, da9062_dt_ids);</div><div class='del'>-</div><div class='ctx'> static int da9062_i2c_probe(struct i2c_client *i2c)</div><div class='ctx'> {</div><div class='del'>-	const struct i2c_device_id *id = i2c_client_get_device_id(i2c);</div><div class='ctx'> 	struct da9062 *chip;</div><div class='ctx'> 	unsigned int irq_base = 0;</div><div class='ctx'> 	const struct mfd_cell *cell;</div><div class='hunk'>@@ -611,10 +603,7 @@ static int da9062_i2c_probe(struct i2c_client *i2c)</div><div class='ctx'> 	if (!chip)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	if (i2c-&gt;dev.of_node)</div><div class='del'>-		chip-&gt;chip_type = (uintptr_t)of_device_get_match_data(&amp;i2c-&gt;dev);</div><div class='del'>-	else</div><div class='del'>-		chip-&gt;chip_type = id-&gt;driver_data;</div><div class='add'>+	chip-&gt;chip_type = (uintptr_t)i2c_get_match_data(i2c);</div><div class='ctx'> </div><div class='ctx'> 	i2c_set_clientdata(i2c, chip);</div><div class='ctx'> 	chip-&gt;dev = &amp;i2c-&gt;dev;</div><div class='hunk'>@@ -714,10 +703,17 @@ static void da9062_i2c_remove(struct i2c_client *i2c)</div><div class='ctx'> 	regmap_del_irq_chip(i2c-&gt;irq, chip-&gt;regmap_irq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct of_device_id da9062_dt_ids[] = {</div><div class='add'>+	{ .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061 },</div><div class='add'>+	{ .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062 },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, da9062_dt_ids);</div><div class='add'>+</div><div class='ctx'> static const struct i2c_device_id da9062_i2c_id[] = {</div><div class='ctx'> 	{ "da9061", COMPAT_TYPE_DA9061 },</div><div class='ctx'> 	{ "da9062", COMPAT_TYPE_DA9062 },</div><div class='del'>-	{ },</div><div class='add'>+	{ }</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, da9062_i2c_id);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c<br/>index 1506d8d352b1..e58990c85ed8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/exynos-lpass.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/exynos-lpass.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/exynos-lpass.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/exynos-lpass.c</a></div><div class='hunk'>@@ -137,7 +137,7 @@ static int exynos_lpass_probe(struct platform_device *pdev)</div><div class='ctx'> 	return devm_of_platform_populate(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int exynos_lpass_remove(struct platform_device *pdev)</div><div class='add'>+static void exynos_lpass_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct exynos_lpass *lpass = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -146,8 +146,6 @@ static int exynos_lpass_remove(struct platform_device *pdev)</div><div class='ctx'> 	if (!pm_runtime_status_suspended(&amp;pdev-&gt;dev))</div><div class='ctx'> 		exynos_lpass_disable(lpass);</div><div class='ctx'> 	regmap_exit(lpass-&gt;top);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused exynos_lpass_suspend(struct device *dev)</div><div class='hunk'>@@ -187,7 +185,7 @@ static struct platform_driver exynos_lpass_driver = {</div><div class='ctx'> 		.of_match_table	= exynos_lpass_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe	= exynos_lpass_probe,</div><div class='del'>-	.remove	= exynos_lpass_remove,</div><div class='add'>+	.remove_new = exynos_lpass_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(exynos_lpass_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/fsl-imx25-tsadc.c b/drivers/mfd/fsl-imx25-tsadc.c<br/>index 089c2ce615b6..74f38bf3778f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/fsl-imx25-tsadc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/fsl-imx25-tsadc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/fsl-imx25-tsadc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/fsl-imx25-tsadc.c</a></div><div class='hunk'>@@ -194,11 +194,9 @@ err_irq:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mx25_tsadc_remove(struct platform_device *pdev)</div><div class='add'>+static void mx25_tsadc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	mx25_tsadc_unset_irq(pdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id mx25_tsadc_ids[] = {</div><div class='hunk'>@@ -213,7 +211,7 @@ static struct platform_driver mx25_tsadc_driver = {</div><div class='ctx'> 		.of_match_table = mx25_tsadc_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = mx25_tsadc_probe,</div><div class='del'>-	.remove = mx25_tsadc_remove,</div><div class='add'>+	.remove_new = mx25_tsadc_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(mx25_tsadc_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c<br/>index 8feae8d8fd9d..042109304db4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/hi655x-pmic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/hi655x-pmic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/hi655x-pmic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/hi655x-pmic.c</a></div><div class='hunk'>@@ -144,13 +144,12 @@ static int hi655x_pmic_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hi655x_pmic_remove(struct platform_device *pdev)</div><div class='add'>+static void hi655x_pmic_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct hi655x_pmic *pmic = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	regmap_del_irq_chip(gpiod_to_irq(pmic-&gt;gpio), pmic-&gt;irq_data);</div><div class='ctx'> 	mfd_remove_devices(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id hi655x_pmic_match[] = {</div><div class='hunk'>@@ -165,7 +164,7 @@ static struct platform_driver hi655x_pmic_driver = {</div><div class='ctx'> 		.of_match_table = hi655x_pmic_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe  = hi655x_pmic_probe,</div><div class='del'>-	.remove = hi655x_pmic_remove,</div><div class='add'>+	.remove_new = hi655x_pmic_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(hi655x_pmic_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c<br/>index 212818aef93e..2a83f8678f1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss-acpi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/intel-lpss-acpi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss-acpi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss-acpi.c</a></div><div class='hunk'>@@ -8,15 +8,20 @@</div><div class='ctx'>  *          Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/gfp_types.h&gt;</div><div class='ctx'> #include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/pxa2xx_ssp.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;asm/errno.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "intel-lpss.h"</div><div class='ctx'> </div><div class='ctx'> static const struct property_entry spt_spi_properties[] = {</div><div class='hunk'>@@ -169,23 +174,20 @@ MODULE_DEVICE_TABLE(acpi, intel_lpss_acpi_ids);</div><div class='ctx'> </div><div class='ctx'> static int intel_lpss_acpi_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='add'>+	const struct intel_lpss_platform_info *data;</div><div class='ctx'> 	struct intel_lpss_platform_info *info;</div><div class='del'>-	const struct acpi_device_id *id;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	id = acpi_match_device(intel_lpss_acpi_ids, &amp;pdev-&gt;dev);</div><div class='del'>-	if (!id)</div><div class='add'>+	data = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='add'>+	if (!data)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	info = devm_kmemdup(&amp;pdev-&gt;dev, (void *)id-&gt;driver_data, sizeof(*info),</div><div class='del'>-			    GFP_KERNEL);</div><div class='add'>+	info = devm_kmemdup(&amp;pdev-&gt;dev, data, sizeof(*info), GFP_KERNEL);</div><div class='ctx'> 	if (!info)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	/* No need to check mem and irq here as intel_lpss_probe() does it for us */</div><div class='ctx'> 	info-&gt;mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);</div><div class='del'>-	if (!info-&gt;mem)</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='ctx'> 	info-&gt;irq = platform_get_irq(pdev, 0);</div><div class='ctx'> </div><div class='ctx'> 	ret = intel_lpss_probe(&amp;pdev-&gt;dev, info);</div><div class='hunk'>@@ -198,23 +200,19 @@ static int intel_lpss_acpi_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int intel_lpss_acpi_remove(struct platform_device *pdev)</div><div class='add'>+static void intel_lpss_acpi_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	intel_lpss_remove(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static INTEL_LPSS_PM_OPS(intel_lpss_acpi_pm_ops);</div><div class='del'>-</div><div class='ctx'> static struct platform_driver intel_lpss_acpi_driver = {</div><div class='ctx'> 	.probe = intel_lpss_acpi_probe,</div><div class='del'>-	.remove = intel_lpss_acpi_remove,</div><div class='add'>+	.remove_new = intel_lpss_acpi_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "intel-lpss",</div><div class='ctx'> 		.acpi_match_table = intel_lpss_acpi_ids,</div><div class='del'>-		.pm = &amp;intel_lpss_acpi_pm_ops,</div><div class='add'>+		.pm = pm_ptr(&amp;intel_lpss_pm_ops),</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -224,3 +222,4 @@ MODULE_AUTHOR("Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;");</div><div class='ctx'> MODULE_AUTHOR("Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("Intel LPSS ACPI driver");</div><div class='ctx'> MODULE_LICENSE("GPL v2");</div><div class='add'>+MODULE_IMPORT_NS(INTEL_LPSS);</div><div class='head'>diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c<br/>index ae5759200622..4621d3950b8f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/intel-lpss-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss-pci.c</a></div><div class='hunk'>@@ -8,14 +8,19 @@</div><div class='ctx'>  *          Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/gfp_types.h&gt;</div><div class='add'>+#include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/pxa2xx_ssp.h&gt;</div><div class='ctx'> </div><div class='add'>+#include &lt;asm/errno.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "intel-lpss.h"</div><div class='ctx'> </div><div class='ctx'> /* Some DSDTs have an unused GEXP ACPI device conflicting with I2C4 resources */</div><div class='hunk'>@@ -30,6 +35,7 @@ static const struct pci_device_id ignore_resource_conflicts_ids[] = {</div><div class='ctx'> static int intel_lpss_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 				const struct pci_device_id *id)</div><div class='ctx'> {</div><div class='add'>+	const struct intel_lpss_platform_info *data = (void *)id-&gt;driver_data;</div><div class='ctx'> 	struct intel_lpss_platform_info *info;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -37,13 +43,17 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	info = devm_kmemdup(&amp;pdev-&gt;dev, (void *)id-&gt;driver_data, sizeof(*info),</div><div class='del'>-			    GFP_KERNEL);</div><div class='add'>+	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	info = devm_kmemdup(&amp;pdev-&gt;dev, data, sizeof(*info), GFP_KERNEL);</div><div class='ctx'> 	if (!info)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	info-&gt;mem = &amp;pdev-&gt;resource[0];</div><div class='del'>-	info-&gt;irq = pdev-&gt;irq;</div><div class='add'>+	/* No need to check mem and irq here as intel_lpss_probe() does it for us */</div><div class='add'>+	info-&gt;mem = pci_resource_n(pdev, 0);</div><div class='add'>+	info-&gt;irq = pci_irq_vector(pdev, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (pci_match_id(ignore_resource_conflicts_ids, pdev))</div><div class='ctx'> 		info-&gt;ignore_resource_conflicts = true;</div><div class='hunk'>@@ -72,8 +82,6 @@ static void intel_lpss_pci_remove(struct pci_dev *pdev)</div><div class='ctx'> 	intel_lpss_remove(&amp;pdev-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);</div><div class='del'>-</div><div class='ctx'> static const struct property_entry spt_spi_properties[] = {</div><div class='ctx'> 	PROPERTY_ENTRY_U32("intel,spi-pxa2xx-type", LPSS_SPT_SSP),</div><div class='ctx'> 	{ }</div><div class='hunk'>@@ -584,7 +592,7 @@ static struct pci_driver intel_lpss_pci_driver = {</div><div class='ctx'> 	.probe = intel_lpss_pci_probe,</div><div class='ctx'> 	.remove = intel_lpss_pci_remove,</div><div class='ctx'> 	.driver = {</div><div class='del'>-		.pm = &amp;intel_lpss_pci_pm_ops,</div><div class='add'>+		.pm = pm_ptr(&amp;intel_lpss_pm_ops),</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -594,3 +602,4 @@ MODULE_AUTHOR("Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;");</div><div class='ctx'> MODULE_AUTHOR("Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;");</div><div class='ctx'> MODULE_DESCRIPTION("Intel LPSS PCI driver");</div><div class='ctx'> MODULE_LICENSE("GPL v2");</div><div class='add'>+MODULE_IMPORT_NS(INTEL_LPSS);</div><div class='head'>diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c<br/>index 9591b354072a..eff423f7dd28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/intel-lpss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss.c</a></div><div class='hunk'>@@ -10,26 +10,34 @@</div><div class='ctx'>  *          Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/array_size.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='ctx'> #include &lt;linux/clkdev.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/clk-provider.h&gt;</div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='add'>+#include &lt;linux/gfp_types.h&gt;</div><div class='ctx'> #include &lt;linux/idr.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/core.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/pm_qos.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='del'>-#include &lt;linux/property.h&gt;</div><div class='del'>-#include &lt;linux/seq_file.h&gt;</div><div class='add'>+#include &lt;linux/sprintf.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='ctx'> #include &lt;linux/io-64-nonatomic-lo-hi.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma/idma64.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "intel-lpss.h"</div><div class='ctx'> </div><div class='add'>+struct dentry;</div><div class='add'>+</div><div class='ctx'> #define LPSS_DEV_OFFSET		0x000</div><div class='ctx'> #define LPSS_DEV_SIZE		0x200</div><div class='ctx'> #define LPSS_PRIV_OFFSET	0x200</div><div class='hunk'>@@ -301,8 +309,8 @@ static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,</div><div class='ctx'> </div><div class='ctx'> 	snprintf(name, sizeof(name), "%s-div", devname);</div><div class='ctx'> 	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),</div><div class='add'>+					      0, lpss-&gt;priv, 1, 15, 16, 15,</div><div class='ctx'> 					      CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,</div><div class='del'>-					      lpss-&gt;priv, 1, 15, 16, 15, 0,</div><div class='ctx'> 					      NULL);</div><div class='ctx'> 	if (IS_ERR(tmp))</div><div class='ctx'> 		return PTR_ERR(tmp);</div><div class='hunk'>@@ -378,9 +386,12 @@ int intel_lpss_probe(struct device *dev,</div><div class='ctx'> 	struct intel_lpss *lpss;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!info || !info-&gt;mem || info-&gt;irq &lt;= 0)</div><div class='add'>+	if (!info || !info-&gt;mem)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (info-&gt;irq &lt; 0)</div><div class='add'>+		return info-&gt;irq;</div><div class='add'>+</div><div class='ctx'> 	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);</div><div class='ctx'> 	if (!lpss)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -405,7 +416,7 @@ int intel_lpss_probe(struct device *dev,</div><div class='ctx'> </div><div class='ctx'> 	intel_lpss_init_dev(lpss);</div><div class='ctx'> </div><div class='del'>-	lpss-&gt;devid = ida_simple_get(&amp;intel_lpss_devid_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	lpss-&gt;devid = ida_alloc(&amp;intel_lpss_devid_ida, GFP_KERNEL);</div><div class='ctx'> 	if (lpss-&gt;devid &lt; 0)</div><div class='ctx'> 		return lpss-&gt;devid;</div><div class='ctx'> </div><div class='hunk'>@@ -442,11 +453,11 @@ err_remove_ltr:</div><div class='ctx'> 	intel_lpss_unregister_clock(lpss);</div><div class='ctx'> </div><div class='ctx'> err_clk_register:</div><div class='del'>-	ida_simple_remove(&amp;intel_lpss_devid_ida, lpss-&gt;devid);</div><div class='add'>+	ida_free(&amp;intel_lpss_devid_ida, lpss-&gt;devid);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(intel_lpss_probe);</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(intel_lpss_probe, INTEL_LPSS);</div><div class='ctx'> </div><div class='ctx'> void intel_lpss_remove(struct device *dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -456,11 +467,10 @@ void intel_lpss_remove(struct device *dev)</div><div class='ctx'> 	intel_lpss_debugfs_remove(lpss);</div><div class='ctx'> 	intel_lpss_ltr_hide(lpss);</div><div class='ctx'> 	intel_lpss_unregister_clock(lpss);</div><div class='del'>-	ida_simple_remove(&amp;intel_lpss_devid_ida, lpss-&gt;devid);</div><div class='add'>+	ida_free(&amp;intel_lpss_devid_ida, lpss-&gt;devid);</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(intel_lpss_remove);</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(intel_lpss_remove, INTEL_LPSS);</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_PM</div><div class='ctx'> static int resume_lpss_device(struct device *dev, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))</div><div class='hunk'>@@ -469,7 +479,7 @@ static int resume_lpss_device(struct device *dev, void *data)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int intel_lpss_prepare(struct device *dev)</div><div class='add'>+static int intel_lpss_prepare(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Resume both child devices before entering system sleep. This</div><div class='hunk'>@@ -478,9 +488,8 @@ int intel_lpss_prepare(struct device *dev)</div><div class='ctx'> 	device_for_each_child_reverse(dev, NULL, resume_lpss_device);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(intel_lpss_prepare);</div><div class='ctx'> </div><div class='del'>-int intel_lpss_suspend(struct device *dev)</div><div class='add'>+static int intel_lpss_suspend(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_lpss *lpss = dev_get_drvdata(dev);</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -499,9 +508,8 @@ int intel_lpss_suspend(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(intel_lpss_suspend);</div><div class='ctx'> </div><div class='del'>-int intel_lpss_resume(struct device *dev)</div><div class='add'>+static int intel_lpss_resume(struct device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct intel_lpss *lpss = dev_get_drvdata(dev);</div><div class='ctx'> 	unsigned int i;</div><div class='hunk'>@@ -514,8 +522,12 @@ int intel_lpss_resume(struct device *dev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='del'>-EXPORT_SYMBOL_GPL(intel_lpss_resume);</div><div class='del'>-#endif</div><div class='add'>+</div><div class='add'>+EXPORT_NS_GPL_DEV_PM_OPS(intel_lpss_pm_ops, INTEL_LPSS) = {</div><div class='add'>+	.prepare = pm_sleep_ptr(&amp;intel_lpss_prepare),</div><div class='add'>+	LATE_SYSTEM_SLEEP_PM_OPS(intel_lpss_suspend, intel_lpss_resume)</div><div class='add'>+	RUNTIME_PM_OPS(intel_lpss_suspend, intel_lpss_resume, NULL)</div><div class='add'>+};</div><div class='ctx'> </div><div class='ctx'> static int __init intel_lpss_init(void)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/mfd/intel-lpss.h b/drivers/mfd/intel-lpss.h<br/>index 062ce95b68b9..c1d72b117ed5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/intel-lpss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/intel-lpss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/intel-lpss.h</a></div><div class='hunk'>@@ -30,32 +30,6 @@ int intel_lpss_probe(struct device *dev,</div><div class='ctx'> 		     const struct intel_lpss_platform_info *info);</div><div class='ctx'> void intel_lpss_remove(struct device *dev);</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_PM</div><div class='del'>-int intel_lpss_prepare(struct device *dev);</div><div class='del'>-int intel_lpss_suspend(struct device *dev);</div><div class='del'>-int intel_lpss_resume(struct device *dev);</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_PM_SLEEP</div><div class='del'>-#define INTEL_LPSS_SLEEP_PM_OPS			\</div><div class='del'>-	.prepare = intel_lpss_prepare,		\</div><div class='del'>-	SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_lpss_suspend, intel_lpss_resume)</div><div class='del'>-#else</div><div class='del'>-#define INTEL_LPSS_SLEEP_PM_OPS</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-#define INTEL_LPSS_RUNTIME_PM_OPS		\</div><div class='del'>-	.runtime_suspend = intel_lpss_suspend,	\</div><div class='del'>-	.runtime_resume = intel_lpss_resume,</div><div class='del'>-</div><div class='del'>-#else /* !CONFIG_PM */</div><div class='del'>-#define INTEL_LPSS_SLEEP_PM_OPS</div><div class='del'>-#define INTEL_LPSS_RUNTIME_PM_OPS</div><div class='del'>-#endif /* CONFIG_PM */</div><div class='del'>-</div><div class='del'>-#define INTEL_LPSS_PM_OPS(name)			\</div><div class='del'>-const struct dev_pm_ops name = {		\</div><div class='del'>-	INTEL_LPSS_SLEEP_PM_OPS			\</div><div class='del'>-	INTEL_LPSS_RUNTIME_PM_OPS		\</div><div class='del'>-}</div><div class='add'>+extern const struct dev_pm_ops intel_lpss_pm_ops;</div><div class='ctx'> </div><div class='ctx'> #endif /* __MFD_INTEL_LPSS_H */</div><div class='head'>diff --git a/drivers/mfd/kempld-core.c b/drivers/mfd/kempld-core.c<br/>index 33c6cfe9fe42..67af36a38913 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/kempld-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/kempld-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/kempld-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/kempld-core.c</a></div><div class='hunk'>@@ -535,7 +535,7 @@ static int kempld_probe(struct platform_device *pdev)</div><div class='ctx'> 	return kempld_detect_device(pld);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int kempld_remove(struct platform_device *pdev)</div><div class='add'>+static void kempld_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct kempld_device_data *pld = platform_get_drvdata(pdev);</div><div class='ctx'> 	const struct kempld_platform_data *pdata = dev_get_platdata(pld-&gt;dev);</div><div class='hunk'>@@ -544,8 +544,6 @@ static int kempld_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	mfd_remove_devices(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pdata-&gt;release_hardware_mutex(pld);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_ACPI</div><div class='hunk'>@@ -563,7 +561,7 @@ static struct platform_driver kempld_driver = {</div><div class='ctx'> 		.acpi_match_table = ACPI_PTR(kempld_acpi_table),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= kempld_probe,</div><div class='del'>-	.remove		= kempld_remove,</div><div class='add'>+	.remove_new	= kempld_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dmi_system_id kempld_dmi_table[] __initconst = {</div><div class='head'>diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c<br/>index 1c9831b78cf9..3883e472b739 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/mcp-sa11x0.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/mcp-sa11x0.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/mcp-sa11x0.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/mcp-sa11x0.c</a></div><div class='hunk'>@@ -232,7 +232,7 @@ static int mcp_sa11x0_probe(struct platform_device *dev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mcp_sa11x0_remove(struct platform_device *dev)</div><div class='add'>+static void mcp_sa11x0_remove(struct platform_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mcp *mcp = platform_get_drvdata(dev);</div><div class='ctx'> 	struct mcp_sa11x0 *m = priv(mcp);</div><div class='hunk'>@@ -251,8 +251,6 @@ static int mcp_sa11x0_remove(struct platform_device *dev)</div><div class='ctx'> 	mcp_host_free(mcp);</div><div class='ctx'> 	release_mem_region(mem1-&gt;start, resource_size(mem1));</div><div class='ctx'> 	release_mem_region(mem0-&gt;start, resource_size(mem0));</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mcp_sa11x0_suspend(struct device *dev)</div><div class='hunk'>@@ -288,7 +286,7 @@ static const struct dev_pm_ops mcp_sa11x0_pm_ops = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mcp_sa11x0_driver = {</div><div class='ctx'> 	.probe		= mcp_sa11x0_probe,</div><div class='del'>-	.remove		= mcp_sa11x0_remove,</div><div class='add'>+	.remove_new	= mcp_sa11x0_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= DRIVER_NAME,</div><div class='ctx'> 		.pm	= pm_sleep_ptr(&amp;mcp_sa11x0_pm_ops),</div><div class='head'>diff --git a/drivers/mfd/mxs-lradc.c b/drivers/mfd/mxs-lradc.c<br/>index ec1b356562b9..73893890b50a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/mxs-lradc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/mxs-lradc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/mxs-lradc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/mxs-lradc.c</a></div><div class='hunk'>@@ -230,13 +230,11 @@ err_clk:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mxs_lradc_remove(struct platform_device *pdev)</div><div class='add'>+static void mxs_lradc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mxs_lradc *lradc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	clk_disable_unprepare(lradc-&gt;clk);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mxs_lradc_driver = {</div><div class='hunk'>@@ -245,7 +243,7 @@ static struct platform_driver mxs_lradc_driver = {</div><div class='ctx'> 		.of_match_table = mxs_lradc_dt_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = mxs_lradc_probe,</div><div class='del'>-	.remove = mxs_lradc_remove,</div><div class='add'>+	.remove_new = mxs_lradc_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(mxs_lradc_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c<br/>index 78f1bb55dbc0..ebc62033db16 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/omap-usb-host.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/omap-usb-host.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/omap-usb-host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/omap-usb-host.c</a></div><div class='hunk'>@@ -816,13 +816,12 @@ static int usbhs_omap_remove_child(struct device *dev, void *data)</div><div class='ctx'>  *</div><div class='ctx'>  * Reverses the effect of usbhs_omap_probe().</div><div class='ctx'>  */</div><div class='del'>-static int usbhs_omap_remove(struct platform_device *pdev)</div><div class='add'>+static void usbhs_omap_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	/* remove children */</div><div class='ctx'> 	device_for_each_child(&amp;pdev-&gt;dev, NULL, usbhs_omap_remove_child);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dev_pm_ops usbhsomap_dev_pm_ops = {</div><div class='hunk'>@@ -845,7 +844,7 @@ static struct platform_driver usbhs_omap_driver = {</div><div class='ctx'> 		.of_match_table = usbhs_omap_dt_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= usbhs_omap_probe,</div><div class='del'>-	.remove		= usbhs_omap_remove,</div><div class='add'>+	.remove_new	= usbhs_omap_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Keshava Munegowda &lt;keshava_mgowda@ti.com&gt;");</div><div class='head'>diff --git a/drivers/mfd/omap-usb-tll.c b/drivers/mfd/omap-usb-tll.c<br/>index 906353735c78..b6303ddb013b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/omap-usb-tll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/omap-usb-tll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/omap-usb-tll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/omap-usb-tll.c</a></div><div class='hunk'>@@ -270,7 +270,7 @@ static int usbtll_omap_probe(struct platform_device *pdev)</div><div class='ctx'>  *</div><div class='ctx'>  * Reverses the effect of usbtll_omap_probe().</div><div class='ctx'>  */</div><div class='del'>-static int usbtll_omap_remove(struct platform_device *pdev)</div><div class='add'>+static void usbtll_omap_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct usbtll_omap *tll = platform_get_drvdata(pdev);</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -287,7 +287,6 @@ static int usbtll_omap_remove(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id usbtll_omap_dt_ids[] = {</div><div class='hunk'>@@ -303,7 +302,7 @@ static struct platform_driver usbtll_omap_driver = {</div><div class='ctx'> 		.of_match_table = usbtll_omap_dt_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= usbtll_omap_probe,</div><div class='del'>-	.remove		= usbtll_omap_remove,</div><div class='add'>+	.remove_new	= usbtll_omap_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int omap_tll_init(struct usbhs_omap_platform_data *pdata)</div><div class='head'>diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c<br/>index 191b1bc6141c..ab55906f91f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/pcf50633-adc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/pcf50633-adc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/pcf50633-adc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/pcf50633-adc.c</a></div><div class='hunk'>@@ -218,7 +218,7 @@ static int pcf50633_adc_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pcf50633_adc_remove(struct platform_device *pdev)</div><div class='add'>+static void pcf50633_adc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pcf50633_adc *adc = platform_get_drvdata(pdev);</div><div class='ctx'> 	int i, head;</div><div class='hunk'>@@ -236,8 +236,6 @@ static int pcf50633_adc_remove(struct platform_device *pdev)</div><div class='ctx'> 		kfree(adc-&gt;queue[i]);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;adc-&gt;queue_mutex);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver pcf50633_adc_driver = {</div><div class='hunk'>@@ -245,7 +243,7 @@ static struct platform_driver pcf50633_adc_driver = {</div><div class='ctx'> 		.name = "pcf50633-adc",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = pcf50633_adc_probe,</div><div class='del'>-	.remove = pcf50633_adc_remove,</div><div class='add'>+	.remove_new = pcf50633_adc_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(pcf50633_adc_driver);</div><div class='head'>diff --git a/drivers/mfd/qcom-pm8xxx.c b/drivers/mfd/qcom-pm8xxx.c<br/>index 07c531bd1236..8b6285f687da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/qcom-pm8xxx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/qcom-pm8xxx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/qcom-pm8xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/qcom-pm8xxx.c</a></div><div class='hunk'>@@ -585,19 +585,17 @@ static int pm8xxx_remove_child(struct device *dev, void *unused)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int pm8xxx_remove(struct platform_device *pdev)</div><div class='add'>+static void pm8xxx_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct pm_irq_chip *chip = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	device_for_each_child(&amp;pdev-&gt;dev, NULL, pm8xxx_remove_child);</div><div class='ctx'> 	irq_domain_remove(chip-&gt;irqdomain);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver pm8xxx_driver = {</div><div class='ctx'> 	.probe		= pm8xxx_probe,</div><div class='del'>-	.remove		= pm8xxx_remove,</div><div class='add'>+	.remove_new	= pm8xxx_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "pm8xxx-core",</div><div class='ctx'> 		.of_match_table = pm8xxx_id_table,</div><div class='head'>diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c<br/>index 4549fa9f7d4b..eab5bf6cff10 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/qcom-spmi-pmic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/qcom-spmi-pmic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/qcom-spmi-pmic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/qcom-spmi-pmic.c</a></div><div class='hunk'>@@ -53,6 +53,7 @@ static const struct of_device_id pmic_spmi_id_table[] = {</div><div class='ctx'> 	{ .compatible = "qcom,pm8901", .data = N_USIDS(2) },</div><div class='ctx'> 	{ .compatible = "qcom,pm8909", .data = N_USIDS(2) },</div><div class='ctx'> 	{ .compatible = "qcom,pm8916", .data = N_USIDS(2) },</div><div class='add'>+	{ .compatible = "qcom,pm8937", .data = N_USIDS(2) },</div><div class='ctx'> 	{ .compatible = "qcom,pm8941", .data = N_USIDS(2) },</div><div class='ctx'> 	{ .compatible = "qcom,pm8950", .data = N_USIDS(2) },</div><div class='ctx'> 	{ .compatible = "qcom,pm8994", .data = N_USIDS(2) },</div><div class='head'>diff --git a/drivers/mfd/rave-sp.c b/drivers/mfd/rave-sp.c<br/>index da50eba10014..6ff84b2600c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/rave-sp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/rave-sp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/rave-sp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/rave-sp.c</a></div><div class='hunk'>@@ -9,7 +9,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/atomic.h&gt;</div><div class='del'>-#include &lt;linux/crc-ccitt.h&gt;</div><div class='add'>+#include &lt;linux/crc-itu-t.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/export.h&gt;</div><div class='ctx'> #include &lt;linux/init.h&gt;</div><div class='hunk'>@@ -251,7 +251,7 @@ static void csum_8b2c(const u8 *buf, size_t size, u8 *crc)</div><div class='ctx'> </div><div class='ctx'> static void csum_ccitt(const u8 *buf, size_t size, u8 *crc)</div><div class='ctx'> {</div><div class='del'>-	const u16 calculated = crc_ccitt_false(0xffff, buf, size);</div><div class='add'>+	const u16 calculated = crc_itu_t(0xffff, buf, size);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * While the rest of the wire protocol is little-endian,</div><div class='hunk'>@@ -471,17 +471,17 @@ static void rave_sp_receive_frame(struct rave_sp *sp,</div><div class='ctx'> 		rave_sp_receive_reply(sp, data, length);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rave_sp_receive_buf(struct serdev_device *serdev,</div><div class='del'>-			       const unsigned char *buf, size_t size)</div><div class='add'>+static ssize_t rave_sp_receive_buf(struct serdev_device *serdev,</div><div class='add'>+				   const u8 *buf, size_t size)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;serdev-&gt;dev;</div><div class='ctx'> 	struct rave_sp *sp = dev_get_drvdata(dev);</div><div class='ctx'> 	struct rave_sp_deframer *deframer = &amp;sp-&gt;deframer;</div><div class='del'>-	const unsigned char *src = buf;</div><div class='del'>-	const unsigned char *end = buf + size;</div><div class='add'>+	const u8 *src = buf;</div><div class='add'>+	const u8 *end = buf + size;</div><div class='ctx'> </div><div class='ctx'> 	while (src &lt; end) {</div><div class='del'>-		const unsigned char byte = *src++;</div><div class='add'>+		const u8 byte = *src++;</div><div class='ctx'> </div><div class='ctx'> 		switch (deframer-&gt;state) {</div><div class='ctx'> 		case RAVE_SP_EXPECT_SOF:</div><div class='head'>diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c<br/>index c47164a3ec1d..b1ffc3b9e2be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/rk8xx-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/rk8xx-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/rk8xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/rk8xx-core.c</a></div><div class='hunk'>@@ -53,76 +53,68 @@ static const struct resource rk817_charger_resources[] = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mfd_cell rk805s[] = {</div><div class='del'>-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },</div><div class='del'>-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },</div><div class='del'>-	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },</div><div class='add'>+	{ .name = "rk808-clkout", },</div><div class='add'>+	{ .name = "rk808-regulator", },</div><div class='add'>+	{ .name = "rk805-pinctrl", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk808-rtc",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rtc_resources),</div><div class='ctx'> 		.resources = &amp;rtc_resources[0],</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> 	{	.name = "rk805-pwrkey",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rk805_key_resources),</div><div class='ctx'> 		.resources = &amp;rk805_key_resources[0],</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mfd_cell rk806s[] = {</div><div class='del'>-	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, },</div><div class='del'>-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, },</div><div class='add'>+	{ .name = "rk805-pinctrl", },</div><div class='add'>+	{ .name = "rk808-regulator", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk805-pwrkey",</div><div class='ctx'> 		.resources = rk806_pwrkey_resources,</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rk806_pwrkey_resources),</div><div class='del'>-		.id = PLATFORM_DEVID_AUTO,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mfd_cell rk808s[] = {</div><div class='del'>-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },</div><div class='del'>-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },</div><div class='add'>+	{ .name = "rk808-clkout", },</div><div class='add'>+	{ .name = "rk808-regulator", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk808-rtc",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rtc_resources),</div><div class='ctx'> 		.resources = rtc_resources,</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mfd_cell rk817s[] = {</div><div class='del'>-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },</div><div class='del'>-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },</div><div class='add'>+	{ .name = "rk808-clkout", },</div><div class='add'>+	{ .name = "rk808-regulator", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk805-pwrkey",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),</div><div class='ctx'> 		.resources = &amp;rk817_pwrkey_resources[0],</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk808-rtc",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rk817_rtc_resources),</div><div class='ctx'> 		.resources = &amp;rk817_rtc_resources[0],</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='del'>-	{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },</div><div class='add'>+	{ .name = "rk817-codec", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk817-charger",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rk817_charger_resources),</div><div class='ctx'> 		.resources = &amp;rk817_charger_resources[0],</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mfd_cell rk818s[] = {</div><div class='del'>-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },</div><div class='del'>-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },</div><div class='add'>+	{ .name = "rk808-clkout", },</div><div class='add'>+	{ .name = "rk808-regulator", },</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "rk808-rtc",</div><div class='ctx'> 		.num_resources = ARRAY_SIZE(rtc_resources),</div><div class='ctx'> 		.resources = rtc_resources,</div><div class='del'>-		.id = PLATFORM_DEVID_NONE,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -684,7 +676,7 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap</div><div class='ctx'> 					     pre_init_reg[i].addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0,</div><div class='add'>+	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, nr_cells, NULL, 0,</div><div class='ctx'> 			      regmap_irq_get_domain(rk808-&gt;irq_data));</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return dev_err_probe(dev, ret, "failed to add MFD devices\n");</div><div class='head'>diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c<br/>index 28027982cf69..b3592982a83b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/sm501.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/sm501.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/sm501.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/sm501.c</a></div><div class='hunk'>@@ -1667,7 +1667,7 @@ static void sm501_pci_remove(struct pci_dev *dev)</div><div class='ctx'> 	pci_disable_device(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sm501_plat_remove(struct platform_device *dev)</div><div class='add'>+static void sm501_plat_remove(struct platform_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sm501_devdata *sm = platform_get_drvdata(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -1675,8 +1675,6 @@ static int sm501_plat_remove(struct platform_device *dev)</div><div class='ctx'> 	iounmap(sm-&gt;regs);</div><div class='ctx'> </div><div class='ctx'> 	release_mem_region(sm-&gt;io_res-&gt;start, 0x100);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id sm501_pci_tbl[] = {</div><div class='hunk'>@@ -1707,7 +1705,7 @@ static struct platform_driver sm501_plat_driver = {</div><div class='ctx'> 		.of_match_table = of_sm501_match_tbl,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= sm501_plat_probe,</div><div class='del'>-	.remove		= sm501_plat_remove,</div><div class='add'>+	.remove_new	= sm501_plat_remove,</div><div class='ctx'> 	.suspend	= pm_sleep_ptr(sm501_plat_suspend),</div><div class='ctx'> 	.resume		= pm_sleep_ptr(sm501_plat_resume),</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c<br/>index a656a1c186a8..9fd13d88950c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/stm32-timers.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/stm32-timers.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/stm32-timers.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/stm32-timers.c</a></div><div class='hunk'>@@ -306,7 +306,7 @@ static int stm32_timers_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stm32_timers_remove(struct platform_device *pdev)</div><div class='add'>+static void stm32_timers_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct stm32_timers *ddata = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -316,8 +316,6 @@ static int stm32_timers_remove(struct platform_device *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	of_platform_depopulate(&amp;pdev-&gt;dev);</div><div class='ctx'> 	stm32_timers_dma_remove(&amp;pdev-&gt;dev, ddata);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id stm32_timers_of_match[] = {</div><div class='hunk'>@@ -328,7 +326,7 @@ MODULE_DEVICE_TABLE(of, stm32_timers_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver stm32_timers_driver = {</div><div class='ctx'> 	.probe = stm32_timers_probe,</div><div class='del'>-	.remove = stm32_timers_remove,</div><div class='add'>+	.remove_new = stm32_timers_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name = "stm32-timers",</div><div class='ctx'> 		.of_match_table = stm32_timers_of_match,</div><div class='head'>diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c<br/>index 57b29c325131..c9550368d9ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/syscon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/syscon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/syscon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/syscon.c</a></div><div class='hunk'>@@ -105,6 +105,10 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_res)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%pa", np, &amp;res.start);</div><div class='add'>+	if (!syscon_config.name) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_regmap;</div><div class='add'>+	}</div><div class='ctx'> 	syscon_config.reg_stride = reg_io_width;</div><div class='ctx'> 	syscon_config.val_bits = reg_io_width * 8;</div><div class='ctx'> 	syscon_config.max_register = resource_size(&amp;res) - reg_io_width;</div><div class='head'>diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c<br/>index b88eb70c17b3..4bbd542d753e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/ti_am335x_tscadc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/ti_am335x_tscadc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/ti_am335x_tscadc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/ti_am335x_tscadc.c</a></div><div class='hunk'>@@ -298,7 +298,7 @@ err_disable_clk:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ti_tscadc_remove(struct platform_device *pdev)</div><div class='add'>+static void ti_tscadc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -308,8 +308,6 @@ static int ti_tscadc_remove(struct platform_device *pdev)</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	mfd_remove_devices(tscadc-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data)</div><div class='hunk'>@@ -381,7 +379,7 @@ static struct platform_driver ti_tscadc_driver = {</div><div class='ctx'> 		.of_match_table = ti_tscadc_dt_ids,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe	= ti_tscadc_probe,</div><div class='del'>-	.remove	= ti_tscadc_remove,</div><div class='add'>+	.remove_new = ti_tscadc_remove,</div><div class='ctx'> </div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c<br/>index 152179ee11ca..fdce81b33f60 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/tps65086.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/tps65086.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/tps65086.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps65086.c</a></div><div class='hunk'>@@ -36,6 +36,7 @@ static const struct regmap_config tps65086_regmap_config = {</div><div class='ctx'> 	.val_bits = 8,</div><div class='ctx'> 	.cache_type = REGCACHE_MAPLE,</div><div class='ctx'> 	.volatile_table = &amp;tps65086_volatile_table,</div><div class='add'>+	.max_register = TPS65086_OC_STATUS,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct regmap_irq tps65086_irqs[] = {</div><div class='head'>diff --git a/drivers/mfd/tps65911-comparator.c b/drivers/mfd/tps65911-comparator.c<br/>index 8f4210075913..f206a9c50e9d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/tps65911-comparator.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/tps65911-comparator.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/tps65911-comparator.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps65911-comparator.c</a></div><div class='hunk'>@@ -140,15 +140,13 @@ static int tps65911_comparator_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tps65911_comparator_remove(struct platform_device *pdev)</div><div class='add'>+static void tps65911_comparator_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct tps65910 *tps65910;</div><div class='ctx'> </div><div class='ctx'> 	tps65910 = dev_get_drvdata(pdev-&gt;dev.parent);</div><div class='ctx'> 	device_remove_file(&amp;pdev-&gt;dev, &amp;dev_attr_comp2_threshold);</div><div class='ctx'> 	device_remove_file(&amp;pdev-&gt;dev, &amp;dev_attr_comp1_threshold);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver tps65911_comparator_driver = {</div><div class='hunk'>@@ -156,7 +154,7 @@ static struct platform_driver tps65911_comparator_driver = {</div><div class='ctx'> 		.name = "tps65911-comparator",</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = tps65911_comparator_probe,</div><div class='del'>-	.remove = tps65911_comparator_remove,</div><div class='add'>+	.remove_new = tps65911_comparator_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int __init tps65911_comparator_init(void)</div><div class='head'>diff --git a/drivers/mfd/tps6594-core.c b/drivers/mfd/tps6594-core.c<br/>index 0fb9c5cf213a..783ee59901e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/tps6594-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/tps6594-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/tps6594-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps6594-core.c</a></div><div class='hunk'>@@ -433,6 +433,9 @@ int tps6594_device_init(struct tps6594 *tps, bool enable_crc)</div><div class='ctx'> 	tps6594_irq_chip.name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x",</div><div class='ctx'> 					       dev-&gt;driver-&gt;name, tps-&gt;chip_id, tps-&gt;reg);</div><div class='ctx'> </div><div class='add'>+	if (!tps6594_irq_chip.name)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	ret = devm_regmap_add_irq_chip(dev, tps-&gt;regmap, tps-&gt;irq, IRQF_SHARED | IRQF_ONESHOT,</div><div class='ctx'> 				       0, &amp;tps6594_irq_chip, &amp;tps-&gt;irq_data);</div><div class='ctx'> 	if (ret)</div><div class='head'>diff --git a/drivers/mfd/tps6594-spi.c b/drivers/mfd/tps6594-spi.c<br/>index f4b4f37f957f..24b72847e3f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/tps6594-spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/tps6594-spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/tps6594-spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/tps6594-spi.c</a></div><div class='hunk'>@@ -98,7 +98,7 @@ static int tps6594_spi_probe(struct spi_device *spi)</div><div class='ctx'> 	spi_set_drvdata(spi, tps);</div><div class='ctx'> </div><div class='ctx'> 	tps-&gt;dev = dev;</div><div class='del'>-	tps-&gt;reg = spi-&gt;chip_select;</div><div class='add'>+	tps-&gt;reg = spi_get_chipselect(spi, 0);</div><div class='ctx'> 	tps-&gt;irq = spi-&gt;irq;</div><div class='ctx'> </div><div class='ctx'> 	tps-&gt;regmap = devm_regmap_init(dev, NULL, spi, &amp;tps6594_spi_regmap_config);</div><div class='head'>diff --git a/drivers/mfd/twl4030-audio.c b/drivers/mfd/twl4030-audio.c<br/>index 88002f8941e5..d436ddf661da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/twl4030-audio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/twl4030-audio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/twl4030-audio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/twl4030-audio.c</a></div><div class='hunk'>@@ -258,12 +258,10 @@ static int twl4030_audio_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int twl4030_audio_remove(struct platform_device *pdev)</div><div class='add'>+static void twl4030_audio_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	mfd_remove_devices(&amp;pdev-&gt;dev);</div><div class='ctx'> 	twl4030_audio_dev = NULL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id twl4030_audio_of_match[] = {</div><div class='hunk'>@@ -278,7 +276,7 @@ static struct platform_driver twl4030_audio_driver = {</div><div class='ctx'> 		.of_match_table = twl4030_audio_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe		= twl4030_audio_probe,</div><div class='del'>-	.remove		= twl4030_audio_remove,</div><div class='add'>+	.remove_new	= twl4030_audio_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(twl4030_audio_driver);</div><div class='head'>diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c<br/>index f9fce8408c2c..3c03681c124c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mfd/twl6030-irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mfd/twl6030-irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mfd/twl6030-irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mfd/twl6030-irq.c</a></div><div class='hunk'>@@ -24,10 +24,10 @@</div><div class='ctx'> #include &lt;linux/kthread.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/twl.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='del'>-#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/suspend.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/irqdomain.h&gt;</div><div class='add'>+#include &lt;linux/of_device.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "twl-core.h"</div><div class='ctx'> </div><div class='hunk'>@@ -368,10 +368,10 @@ int twl6030_init_irq(struct device *dev, int irq_num)</div><div class='ctx'> 	int			nr_irqs;</div><div class='ctx'> 	int			status;</div><div class='ctx'> 	u8			mask[3];</div><div class='del'>-	const int		*irq_tbl;</div><div class='add'>+	const struct of_device_id *of_id;</div><div class='ctx'> </div><div class='del'>-	irq_tbl = device_get_match_data(dev);</div><div class='del'>-	if (!irq_tbl) {</div><div class='add'>+	of_id = of_match_device(twl6030_of_match, dev);</div><div class='add'>+	if (!of_id || !of_id-&gt;data) {</div><div class='ctx'> 		dev_err(dev, "Unknown TWL device model\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -409,7 +409,7 @@ int twl6030_init_irq(struct device *dev, int irq_num)</div><div class='ctx'> </div><div class='ctx'> 	twl6030_irq-&gt;pm_nb.notifier_call = twl6030_irq_pm_notifier;</div><div class='ctx'> 	atomic_set(&amp;twl6030_irq-&gt;wakeirqs, 0);</div><div class='del'>-	twl6030_irq-&gt;irq_mapping_tbl = irq_tbl;</div><div class='add'>+	twl6030_irq-&gt;irq_mapping_tbl = of_id-&gt;data;</div><div class='ctx'> </div><div class='ctx'> 	twl6030_irq-&gt;irq_domain =</div><div class='ctx'> 		irq_domain_add_linear(node, nr_irqs,</div><div class='head'>diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig<br/>index f37c4b8380ae..4fb291f0bf7c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/Kconfig</a></div><div class='hunk'>@@ -562,6 +562,18 @@ config TPS6594_PFSM</div><div class='ctx'> 	  This driver can also be built as a module.  If so, the module</div><div class='ctx'> 	  will be called tps6594-pfsm.</div><div class='ctx'> </div><div class='add'>+config NSM</div><div class='add'>+	tristate "Nitro (Enclaves) Security Module support"</div><div class='add'>+	depends on VIRTIO</div><div class='add'>+	select HW_RANDOM</div><div class='add'>+	help</div><div class='add'>+	  This driver provides support for the Nitro Security Module</div><div class='add'>+	  in AWS EC2 Nitro based Enclaves. The driver exposes a /dev/nsm</div><div class='add'>+	  device user space can use to communicate with the hypervisor.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here.</div><div class='add'>+	  The module will be called nsm.</div><div class='add'>+</div><div class='ctx'> source "drivers/misc/c2port/Kconfig"</div><div class='ctx'> source "drivers/misc/eeprom/Kconfig"</div><div class='ctx'> source "drivers/misc/cb710/Kconfig"</div><div class='head'>diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile<br/>index f2a4d1ff65d4..ea6ea5bbbc9c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/Makefile</a></div><div class='hunk'>@@ -67,3 +67,4 @@ obj-$(CONFIG_TMR_MANAGER)      += xilinx_tmr_manager.o</div><div class='ctx'> obj-$(CONFIG_TMR_INJECT)	+= xilinx_tmr_inject.o</div><div class='ctx'> obj-$(CONFIG_TPS6594_ESM)	+= tps6594-esm.o</div><div class='ctx'> obj-$(CONFIG_TPS6594_PFSM)	+= tps6594-pfsm.o</div><div class='add'>+obj-$(CONFIG_NSM)		+= nsm.o</div><div class='head'>diff --git a/drivers/misc/bcm-vk/bcm_vk_tty.c b/drivers/misc/bcm-vk/bcm_vk_tty.c<br/>index 2bce835ca43e..59bab76ff0a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/bcm-vk/bcm_vk_tty.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/bcm-vk/bcm_vk_tty.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/bcm-vk/bcm_vk_tty.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/bcm-vk/bcm_vk_tty.c</a></div><div class='hunk'>@@ -64,9 +64,9 @@ static void bcm_vk_tty_wq_handler(struct work_struct *work)</div><div class='ctx'> 	struct bcm_vk_tty *vktty;</div><div class='ctx'> 	int card_status;</div><div class='ctx'> 	int count;</div><div class='del'>-	unsigned char c;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int wr;</div><div class='add'>+	u8 c;</div><div class='ctx'> </div><div class='ctx'> 	card_status = vkread32(vk, BAR_0, BAR_CARD_STATUS);</div><div class='ctx'> 	if (BCM_VK_INTF_IS_DOWN(card_status))</div><div class='hunk'>@@ -192,7 +192,7 @@ static ssize_t bcm_vk_tty_write(struct tty_struct *tty, const u8 *buffer,</div><div class='ctx'> 	int index;</div><div class='ctx'> 	struct bcm_vk *vk;</div><div class='ctx'> 	struct bcm_vk_tty *vktty;</div><div class='del'>-	int i;</div><div class='add'>+	size_t i;</div><div class='ctx'> </div><div class='ctx'> 	index = tty-&gt;index;</div><div class='ctx'> 	vk = dev_get_drvdata(tty-&gt;dev);</div><div class='head'>diff --git a/drivers/misc/cardreader/Makefile b/drivers/misc/cardreader/Makefile<br/>index 895128475d83..1e1bca6b0b22 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/cardreader/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/Makefile</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='ctx'> obj-$(CONFIG_MISC_ALCOR_PCI)	+= alcor_pci.o</div><div class='ctx'> obj-$(CONFIG_MISC_RTSX_PCI)	+= rtsx_pci.o</div><div class='del'>-rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o rts5260.o rts5261.o rts5228.o</div><div class='add'>+rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o rts5260.o rts5261.o rts5228.o rts5264.o</div><div class='ctx'> obj-$(CONFIG_MISC_RTSX_USB)	+= rtsx_usb.o</div><div class='head'>diff --git a/drivers/misc/cardreader/rts5264.c b/drivers/misc/cardreader/rts5264.c<br/>new file mode 100644<br/>index 000000000000..8be4ed7d9d47<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rts5264.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rts5264.c</a></div><div class='hunk'>@@ -0,0 +1,886 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/* Driver for Realtek PCI-Express card reader</div><div class='add'>+ *</div><div class='add'>+ * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Author:</div><div class='add'>+ *   Ricky Wu &lt;ricky_wu@realtek.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/rtsx_pci.h&gt;</div><div class='add'>+</div><div class='add'>+#include "rts5264.h"</div><div class='add'>+#include "rtsx_pcr.h"</div><div class='add'>+</div><div class='add'>+static u8 rts5264_get_ic_version(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	u8 val;</div><div class='add'>+</div><div class='add'>+	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &amp;val);</div><div class='add'>+	return val &amp; 0x0F;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_fill_driving(struct rtsx_pcr *pcr, u8 voltage)</div><div class='add'>+{</div><div class='add'>+	u8 driving_3v3[4][3] = {</div><div class='add'>+		{0x88, 0x88, 0x88},</div><div class='add'>+		{0x77, 0x77, 0x77},</div><div class='add'>+		{0x99, 0x99, 0x99},</div><div class='add'>+		{0x66, 0x66, 0x66},</div><div class='add'>+	};</div><div class='add'>+	u8 driving_1v8[4][3] = {</div><div class='add'>+		{0x99, 0x99, 0x99},</div><div class='add'>+		{0x77, 0x77, 0x77},</div><div class='add'>+		{0xBB, 0xBB, 0xBB},</div><div class='add'>+		{0x65, 0x65, 0x65},</div><div class='add'>+	};</div><div class='add'>+	u8 (*driving)[3], drive_sel;</div><div class='add'>+</div><div class='add'>+	if (voltage == OUTPUT_3V3) {</div><div class='add'>+		driving = driving_3v3;</div><div class='add'>+		drive_sel = pcr-&gt;sd30_drive_sel_3v3;</div><div class='add'>+	} else {</div><div class='add'>+		driving = driving_1v8;</div><div class='add'>+		drive_sel = pcr-&gt;sd30_drive_sel_1v8;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,</div><div class='add'>+			0xFF, driving[drive_sel][0]);</div><div class='add'>+	rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,</div><div class='add'>+			0xFF, driving[drive_sel][1]);</div><div class='add'>+	rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,</div><div class='add'>+			0xFF, driving[drive_sel][2]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)</div><div class='add'>+{</div><div class='add'>+	/* Set relink_time to 0 */</div><div class='add'>+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,</div><div class='add'>+				RELINK_TIME_MASK, 0);</div><div class='add'>+</div><div class='add'>+	if (pm_state == HOST_ENTER_S3)</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3,</div><div class='add'>+					D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);</div><div class='add'>+</div><div class='add'>+	if (!runtime) {</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,</div><div class='add'>+				CD_RESUME_EN_MASK, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3, 0x01, 0x00);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+				FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);</div><div class='add'>+	} else {</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+				FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3, 0x01, 0x01);</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3,</div><div class='add'>+					D3_DELINK_MODE_EN, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_FW_CTL,</div><div class='add'>+				RTS5264_INFORM_RTD3_COLD, RTS5264_INFORM_RTD3_COLD);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,</div><div class='add'>+				RTS5264_FORCE_PRSNT_LOW, RTS5264_FORCE_PRSNT_LOW);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_REG_FPDCTL,</div><div class='add'>+		SSC_POWER_DOWN, SSC_POWER_DOWN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_enable_auto_blink(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_write_register(pcr, OLT_LED_CTL,</div><div class='add'>+		LED_SHINE_MASK, LED_SHINE_EN);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_disable_auto_blink(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_write_register(pcr, OLT_LED_CTL,</div><div class='add'>+		LED_SHINE_MASK, LED_SHINE_DISABLE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_turn_on_led(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_write_register(pcr, GPIO_CTL,</div><div class='add'>+		0x02, 0x02);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_turn_off_led(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_write_register(pcr, GPIO_CTL,</div><div class='add'>+		0x02, 0x00);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* SD Pull Control Enable:</div><div class='add'>+ *     SD_DAT[3:0] ==&gt; pull up</div><div class='add'>+ *     SD_CD       ==&gt; pull up</div><div class='add'>+ *     SD_WP       ==&gt; pull up</div><div class='add'>+ *     SD_CMD      ==&gt; pull up</div><div class='add'>+ *     SD_CLK      ==&gt; pull down</div><div class='add'>+ */</div><div class='add'>+static const u32 rts5264_sd_pull_ctl_enable_tbl[] = {</div><div class='add'>+	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),</div><div class='add'>+	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),</div><div class='add'>+	0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* SD Pull Control Disable:</div><div class='add'>+ *     SD_DAT[3:0] ==&gt; pull down</div><div class='add'>+ *     SD_CD       ==&gt; pull up</div><div class='add'>+ *     SD_WP       ==&gt; pull down</div><div class='add'>+ *     SD_CMD      ==&gt; pull down</div><div class='add'>+ *     SD_CLK      ==&gt; pull down</div><div class='add'>+ */</div><div class='add'>+static const u32 rts5264_sd_pull_ctl_disable_tbl[] = {</div><div class='add'>+	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),</div><div class='add'>+	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),</div><div class='add'>+	0,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int rts5264_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK</div><div class='add'>+		| SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);</div><div class='add'>+	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);</div><div class='add'>+	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,</div><div class='add'>+			CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);</div><div class='add'>+	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_card_power_on(struct rtsx_pcr *pcr, int card)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;pcr-&gt;option;</div><div class='add'>+</div><div class='add'>+	if (option-&gt;ocp_en)</div><div class='add'>+		rtsx_pci_enable_ocp(pcr);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,</div><div class='add'>+		CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG1,</div><div class='add'>+			RTS5264_LDO1_TUNE_MASK, RTS5264_LDO1_33);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,</div><div class='add'>+			RTS5264_LDO1_POWERON, RTS5264_LDO1_POWERON);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,</div><div class='add'>+			RTS5264_LDO3318_POWERON, RTS5264_LDO3318_POWERON);</div><div class='add'>+</div><div class='add'>+	msleep(20);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);</div><div class='add'>+</div><div class='add'>+	/* Initialize SD_CFG1 register */</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,</div><div class='add'>+			SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,</div><div class='add'>+			0xFF, SD20_RX_POS_EDGE);</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,</div><div class='add'>+			SD_STOP | SD_CLR_ERR);</div><div class='add'>+</div><div class='add'>+	/* Reset SD_CFG3 register */</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,</div><div class='add'>+			SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |</div><div class='add'>+			SD30_CLK_STOP_CFG0, 0);</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;extra_caps &amp; EXTRA_CAPS_SD_SDR50 ||</div><div class='add'>+	    pcr-&gt;extra_caps &amp; EXTRA_CAPS_SD_SDR104)</div><div class='add'>+		rts5264_sd_set_sample_push_timing_sd30(pcr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)</div><div class='add'>+{</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_CARD_PWR_CTL,</div><div class='add'>+			RTS5264_PUPDC, RTS5264_PUPDC);</div><div class='add'>+</div><div class='add'>+	switch (voltage) {</div><div class='add'>+	case OUTPUT_3V3:</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,</div><div class='add'>+				RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,</div><div class='add'>+				RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_33);</div><div class='add'>+		rtsx_pci_write_register(pcr, SD_PAD_CTL,</div><div class='add'>+				SD_IO_USING_1V8, 0);</div><div class='add'>+		break;</div><div class='add'>+	case OUTPUT_1V8:</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,</div><div class='add'>+				RTS5264_TUNE_REF_LDO3318, RTS5264_TUNE_REF_LDO3318_DFT);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_DV3318_CFG,</div><div class='add'>+				RTS5264_DV3318_TUNE_MASK, RTS5264_DV3318_18);</div><div class='add'>+		rtsx_pci_write_register(pcr, SD_PAD_CTL,</div><div class='add'>+				SD_IO_USING_1V8, SD_IO_USING_1V8);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* set pad drive */</div><div class='add'>+	rts5264_fill_driving(pcr, voltage);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_stop_cmd(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);</div><div class='add'>+	rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);</div><div class='add'>+	rtsx_pci_write_register(pcr, DMACTL, DMA_RST, DMA_RST);</div><div class='add'>+	rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_card_before_power_off(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	rts5264_stop_cmd(pcr);</div><div class='add'>+	rts5264_switch_output_voltage(pcr, OUTPUT_3V3);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_card_power_off(struct rtsx_pcr *pcr, int card)</div><div class='add'>+{</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	rts5264_card_before_power_off(pcr);</div><div class='add'>+	err = rtsx_pci_write_register(pcr, RTS5264_LDO1233318_POW_CTL,</div><div class='add'>+				RTS5264_LDO_POWERON_MASK, 0);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,</div><div class='add'>+		CFG_SD_POW_AUTO_PD, 0);</div><div class='add'>+	if (pcr-&gt;option.ocp_en)</div><div class='add'>+		rtsx_pci_disable_ocp(pcr);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_enable_ocp(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	u8 mask = 0;</div><div class='add'>+	u8 val = 0;</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,</div><div class='add'>+			RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN,</div><div class='add'>+			RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,</div><div class='add'>+			RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN,</div><div class='add'>+			RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,</div><div class='add'>+			RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN,</div><div class='add'>+			RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_DET,</div><div class='add'>+			RTS5264_POW_VDET, RTS5264_POW_VDET);</div><div class='add'>+</div><div class='add'>+	mask = SD_OCP_INT_EN | SD_DETECT_EN;</div><div class='add'>+	mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;</div><div class='add'>+	val = mask;</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);</div><div class='add'>+</div><div class='add'>+	mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;</div><div class='add'>+	val = mask;</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, val);</div><div class='add'>+</div><div class='add'>+	mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;</div><div class='add'>+	val = mask;</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_disable_ocp(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	u8 mask = 0;</div><div class='add'>+</div><div class='add'>+	mask = SD_OCP_INT_EN | SD_DETECT_EN;</div><div class='add'>+	mask |= SDVIO_OCP_INT_EN | SDVIO_DETECT_EN;</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);</div><div class='add'>+</div><div class='add'>+	mask = SD_VDD3_OCP_INT_EN | SD_VDD3_DETECT_EN;</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL, mask, 0);</div><div class='add'>+</div><div class='add'>+	mask = RTS5264_OVP_INT_EN | RTS5264_OVP_DETECT_EN;</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_CTL, mask, 0);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,</div><div class='add'>+			RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,</div><div class='add'>+			RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,</div><div class='add'>+			RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_DET, RTS5264_POW_VDET, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_init_ocp(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;pcr-&gt;option;</div><div class='add'>+</div><div class='add'>+	if (option-&gt;ocp_en) {</div><div class='add'>+		u8 mask, val;</div><div class='add'>+</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,</div><div class='add'>+			RTS5264_LDO1_OCP_THD_MASK, option-&gt;sd_800mA_ocp_thd);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,</div><div class='add'>+			RTS5264_LDO1_OCP_LMT_THD_MASK,</div><div class='add'>+			RTS5264_LDO1_LMT_THD_2000);</div><div class='add'>+</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,</div><div class='add'>+			RTS5264_LDO2_OCP_THD_MASK, RTS5264_LDO2_OCP_THD_950);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,</div><div class='add'>+			RTS5264_LDO2_OCP_LMT_THD_MASK,</div><div class='add'>+			RTS5264_LDO2_LMT_THD_2000);</div><div class='add'>+</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,</div><div class='add'>+			RTS5264_LDO3_OCP_THD_MASK, RTS5264_LDO3_OCP_THD_710);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,</div><div class='add'>+			RTS5264_LDO3_OCP_LMT_THD_MASK,</div><div class='add'>+			RTS5264_LDO3_LMT_THD_1500);</div><div class='add'>+</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_OVP_DET,</div><div class='add'>+			RTS5264_TUNE_VROV_MASK, RTS5264_TUNE_VROV_1V6);</div><div class='add'>+</div><div class='add'>+		mask = SD_OCP_GLITCH_MASK | SDVIO_OCP_GLITCH_MASK;</div><div class='add'>+		val = pcr-&gt;hw_param.ocp_glitch;</div><div class='add'>+		rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);</div><div class='add'>+</div><div class='add'>+	} else {</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO1_CFG0,</div><div class='add'>+			RTS5264_LDO1_OCP_EN | RTS5264_LDO1_OCP_LMT_EN, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO2_CFG0,</div><div class='add'>+			RTS5264_LDO2_OCP_EN | RTS5264_LDO2_OCP_LMT_EN, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_LDO3_CFG0,</div><div class='add'>+			RTS5264_LDO3_OCP_EN | RTS5264_LDO3_OCP_LMT_EN, 0);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_OVP_DET,</div><div class='add'>+			RTS5264_POW_VDET, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_read_register(pcr, RTS5264_OCP_VDD3_STS, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_get_ovpstat(struct rtsx_pcr *pcr, u8 *val)</div><div class='add'>+{</div><div class='add'>+	return rtsx_pci_read_register(pcr, RTS5264_OVP_STS, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_clear_ocpstat(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	u8 mask = 0;</div><div class='add'>+	u8 val = 0;</div><div class='add'>+</div><div class='add'>+	mask = SD_OCP_INT_CLR | SD_OC_CLR;</div><div class='add'>+	mask |= SDVIO_OCP_INT_CLR | SDVIO_OC_CLR;</div><div class='add'>+	val = mask;</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,</div><div class='add'>+		SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR,</div><div class='add'>+		SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,</div><div class='add'>+		RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR,</div><div class='add'>+		RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR);</div><div class='add'>+</div><div class='add'>+	udelay(1000);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OCP_VDD3_CTL,</div><div class='add'>+		SD_VDD3_OCP_INT_CLR | SD_VDD3_OC_CLR, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_OVP_CTL,</div><div class='add'>+		RTS5264_OVP_INT_CLR | RTS5264_OVP_CLR, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_process_ocp(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	if (!pcr-&gt;option.ocp_en)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	rtsx_pci_get_ocpstat(pcr, &amp;pcr-&gt;ocp_stat);</div><div class='add'>+	rts5264_get_ocpstat2(pcr, &amp;pcr-&gt;ocp_stat2);</div><div class='add'>+	rts5264_get_ovpstat(pcr, &amp;pcr-&gt;ovp_stat);</div><div class='add'>+</div><div class='add'>+	if ((pcr-&gt;ocp_stat &amp; (SD_OC_NOW | SD_OC_EVER | SDVIO_OC_NOW | SDVIO_OC_EVER)) ||</div><div class='add'>+			(pcr-&gt;ocp_stat2 &amp; (SD_VDD3_OC_NOW | SD_VDD3_OC_EVER)) ||</div><div class='add'>+			(pcr-&gt;ovp_stat &amp; (RTS5264_OVP_NOW | RTS5264_OVP_EVER))) {</div><div class='add'>+		rts5264_clear_ocpstat(pcr);</div><div class='add'>+		rts5264_card_power_off(pcr, RTSX_SD_CARD);</div><div class='add'>+		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);</div><div class='add'>+		pcr-&gt;ocp_stat = 0;</div><div class='add'>+		pcr-&gt;ocp_stat2 = 0;</div><div class='add'>+		pcr-&gt;ovp_stat = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_init_from_hw(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = pcr-&gt;pci;</div><div class='add'>+	u32 lval1, lval2, i;</div><div class='add'>+	u16 setting_reg1, setting_reg2;</div><div class='add'>+	u8 valid, efuse_valid, tmp;</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+		REG_EFUSE_POR | REG_EFUSE_POWER_MASK,</div><div class='add'>+		REG_EFUSE_POR | REG_EFUSE_POWERON);</div><div class='add'>+	udelay(1);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_EFUSE_ADDR,</div><div class='add'>+		RTS5264_EFUSE_ADDR_MASK, 0x00);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_EFUSE_CTL,</div><div class='add'>+		RTS5264_EFUSE_ENABLE | RTS5264_EFUSE_MODE_MASK,</div><div class='add'>+		RTS5264_EFUSE_ENABLE);</div><div class='add'>+</div><div class='add'>+	/* Wait transfer end */</div><div class='add'>+	for (i = 0; i &lt; MAX_RW_REG_CNT; i++) {</div><div class='add'>+		rtsx_pci_read_register(pcr, RTS5264_EFUSE_CTL, &amp;tmp);</div><div class='add'>+		if ((tmp &amp; 0x80) == 0)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+	rtsx_pci_read_register(pcr, RTS5264_EFUSE_READ_DATA, &amp;tmp);</div><div class='add'>+	efuse_valid = ((tmp &amp; 0x0C) &gt;&gt; 2);</div><div class='add'>+	pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, PCR_SETTING_REG2, &amp;lval2);</div><div class='add'>+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);</div><div class='add'>+	/* 0x816 */</div><div class='add'>+	valid = (u8)((lval2 &gt;&gt; 16) &amp; 0x03);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+		REG_EFUSE_POR, 0);</div><div class='add'>+	pcr_dbg(pcr, "Disable efuse por!\n");</div><div class='add'>+</div><div class='add'>+	if (efuse_valid == 2 || efuse_valid == 3) {</div><div class='add'>+		if (valid == 3) {</div><div class='add'>+			/* Bypass efuse */</div><div class='add'>+			setting_reg1 = PCR_SETTING_REG1;</div><div class='add'>+			setting_reg2 = PCR_SETTING_REG2;</div><div class='add'>+		} else {</div><div class='add'>+			/* Use efuse data */</div><div class='add'>+			setting_reg1 = PCR_SETTING_REG4;</div><div class='add'>+			setting_reg2 = PCR_SETTING_REG5;</div><div class='add'>+		}</div><div class='add'>+	} else if (efuse_valid == 0) {</div><div class='add'>+		// default</div><div class='add'>+		setting_reg1 = PCR_SETTING_REG1;</div><div class='add'>+		setting_reg2 = PCR_SETTING_REG2;</div><div class='add'>+	} else {</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, setting_reg2, &amp;lval2);</div><div class='add'>+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);</div><div class='add'>+</div><div class='add'>+	if (!rts5264_vendor_setting_valid(lval2)) {</div><div class='add'>+		pcr_dbg(pcr, "skip fetch vendor setting\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pcr-&gt;rtd3_en = rts5264_reg_to_rtd3(lval2);</div><div class='add'>+</div><div class='add'>+	if (rts5264_reg_check_reverse_socket(lval2))</div><div class='add'>+		pcr-&gt;flags |= PCR_REVERSE_SOCKET;</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, setting_reg1, &amp;lval1);</div><div class='add'>+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);</div><div class='add'>+</div><div class='add'>+	pcr-&gt;aspm_en = rts5264_reg_to_aspm(lval1);</div><div class='add'>+	pcr-&gt;sd30_drive_sel_1v8 = rts5264_reg_to_sd30_drive_sel_1v8(lval1);</div><div class='add'>+	pcr-&gt;sd30_drive_sel_3v3 = rts5264_reg_to_sd30_drive_sel_3v3(lval1);</div><div class='add'>+</div><div class='add'>+	if (setting_reg1 == PCR_SETTING_REG1) {</div><div class='add'>+		/* store setting */</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 &gt;&gt; 8) &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 &gt;&gt; 16) &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 &gt;&gt; 24) &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 &gt;&gt; 8) &amp; 0xFF));</div><div class='add'>+		rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 &gt;&gt; 16) &amp; 0xFF));</div><div class='add'>+</div><div class='add'>+		pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);</div><div class='add'>+		lval2 = lval2 &amp; 0x00FFFFFF;</div><div class='add'>+		pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_init_from_cfg(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;pcr-&gt;option;</div><div class='add'>+</div><div class='add'>+	if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN</div><div class='add'>+				| PM_L1_1_EN | PM_L1_2_EN))</div><div class='add'>+		rtsx_pci_disable_oobs_polling(pcr);</div><div class='add'>+	else</div><div class='add'>+		rtsx_pci_enable_oobs_polling(pcr);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);</div><div class='add'>+</div><div class='add'>+	if (option-&gt;ltr_en) {</div><div class='add'>+		if (option-&gt;ltr_enabled)</div><div class='add'>+			rtsx_set_ltr_latency(pcr, option-&gt;ltr_active_latency);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rts5264_extra_init_hw(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;pcr-&gt;option;</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG1,</div><div class='add'>+			CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);</div><div class='add'>+	rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);</div><div class='add'>+</div><div class='add'>+	rts5264_init_from_cfg(pcr);</div><div class='add'>+	rts5264_init_from_hw(pcr);</div><div class='add'>+</div><div class='add'>+	/* power off efuse */</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+			REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,</div><div class='add'>+			RTS5264_CHIP_RST_N_SEL, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_REG_LDO12_CFG,</div><div class='add'>+			RTS5264_LDO12_SR_MASK, RTS5264_LDO12_SR_0_0_MS);</div><div class='add'>+	rtsx_pci_write_register(pcr, CDGW, 0xFF, 0x01);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_CKMUX_MBIAS_PWR,</div><div class='add'>+			RTS5264_POW_CKMUX, RTS5264_POW_CKMUX);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_CMD_OE_START_EARLY,</div><div class='add'>+			RTS5264_CMD_OE_EARLY_EN | RTS5264_CMD_OE_EARLY_CYCLE_MASK,</div><div class='add'>+			RTS5264_CMD_OE_EARLY_EN);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_DAT_OE_START_EARLY,</div><div class='add'>+			RTS5264_DAT_OE_EARLY_EN | RTS5264_DAT_OE_EARLY_CYCLE_MASK,</div><div class='add'>+			RTS5264_DAT_OE_EARLY_EN);</div><div class='add'>+	rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_PWR_CUT,</div><div class='add'>+			RTS5264_CFG_MEM_PD, RTS5264_CFG_MEM_PD);</div><div class='add'>+	rtsx_pci_write_register(pcr, L1SUB_CONFIG1,</div><div class='add'>+			AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);</div><div class='add'>+	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,</div><div class='add'>+			RTS5264_AUX_CLK_16M_EN, 0);</div><div class='add'>+</div><div class='add'>+	/* Release PRSNT# */</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,</div><div class='add'>+			RTS5264_FORCE_PRSNT_LOW, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, PCLK_CTL,</div><div class='add'>+			PCLK_MODE_SEL, PCLK_MODE_SEL);</div><div class='add'>+</div><div class='add'>+	/* LED shine disabled, set initial shine cycle period */</div><div class='add'>+	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);</div><div class='add'>+</div><div class='add'>+	/* Configure driving */</div><div class='add'>+	rts5264_fill_driving(pcr, OUTPUT_3V3);</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;flags &amp; PCR_REVERSE_SOCKET)</div><div class='add'>+		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);</div><div class='add'>+	else</div><div class='add'>+		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced</div><div class='add'>+	 * to drive low, and we forcibly request clock.</div><div class='add'>+	 */</div><div class='add'>+	if (option-&gt;force_clkreq_0)</div><div class='add'>+		rtsx_pci_write_register(pcr, PETXCFG,</div><div class='add'>+				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);</div><div class='add'>+	else</div><div class='add'>+		rtsx_pci_write_register(pcr, PETXCFG,</div><div class='add'>+				 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFF);</div><div class='add'>+	rtsx_pci_write_register(pcr, RBCTL, U_AUTO_DMA_EN_MASK, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG4,</div><div class='add'>+			RTS5264_F_HIGH_RC_MASK, RTS5264_F_HIGH_RC_400K);</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;rtd3_en) {</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3, 0x01, 0x00);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+				FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);</div><div class='add'>+	} else {</div><div class='add'>+		rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3, 0x01, 0x00);</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_REG_PME_FORCE_CTL,</div><div class='add'>+				FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);</div><div class='add'>+	}</div><div class='add'>+	rtsx_pci_write_register(pcr, pcr-&gt;reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);</div><div class='add'>+</div><div class='add'>+	/* Clear Enter RTD3_cold Information*/</div><div class='add'>+	rtsx_pci_write_register(pcr, RTS5264_FW_CTL,</div><div class='add'>+		RTS5264_INFORM_RTD3_COLD, 0);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_enable_aspm(struct rtsx_pcr *pcr, bool enable)</div><div class='add'>+{</div><div class='add'>+	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;</div><div class='add'>+	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;aspm_enabled == enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	val |= (pcr-&gt;aspm_en &amp; 0x02);</div><div class='add'>+	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);</div><div class='add'>+	pcie_capability_clear_and_set_word(pcr-&gt;pci, PCI_EXP_LNKCTL,</div><div class='add'>+					   PCI_EXP_LNKCTL_ASPMC, pcr-&gt;aspm_en);</div><div class='add'>+	pcr-&gt;aspm_enabled = enable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_disable_aspm(struct rtsx_pcr *pcr, bool enable)</div><div class='add'>+{</div><div class='add'>+	u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;</div><div class='add'>+	u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;aspm_enabled == enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pcie_capability_clear_and_set_word(pcr-&gt;pci, PCI_EXP_LNKCTL,</div><div class='add'>+					   PCI_EXP_LNKCTL_ASPMC, 0);</div><div class='add'>+	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);</div><div class='add'>+	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);</div><div class='add'>+	udelay(10);</div><div class='add'>+	pcr-&gt;aspm_enabled = enable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_set_aspm(struct rtsx_pcr *pcr, bool enable)</div><div class='add'>+{</div><div class='add'>+	if (enable)</div><div class='add'>+		rts5264_enable_aspm(pcr, true);</div><div class='add'>+	else</div><div class='add'>+		rts5264_disable_aspm(pcr, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rts5264_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;(pcr-&gt;option);</div><div class='add'>+</div><div class='add'>+	u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);</div><div class='add'>+	int card_exist = (interrupt &amp; SD_EXIST);</div><div class='add'>+	int aspm_L1_1, aspm_L1_2;</div><div class='add'>+	u8 val = 0;</div><div class='add'>+</div><div class='add'>+	aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);</div><div class='add'>+	aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);</div><div class='add'>+</div><div class='add'>+	if (active) {</div><div class='add'>+		/* Run, latency: 60us */</div><div class='add'>+		if (aspm_L1_1)</div><div class='add'>+			val = option-&gt;ltr_l1off_snooze_sspwrgate;</div><div class='add'>+	} else {</div><div class='add'>+		/* L1off, latency: 300us */</div><div class='add'>+		if (aspm_L1_2)</div><div class='add'>+			val = option-&gt;ltr_l1off_sspwrgate;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (aspm_L1_1 || aspm_L1_2) {</div><div class='add'>+		if (rtsx_check_dev_flag(pcr,</div><div class='add'>+					LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {</div><div class='add'>+			if (card_exist)</div><div class='add'>+				val &amp;= ~L1OFF_MBIAS2_EN_5250;</div><div class='add'>+			else</div><div class='add'>+				val |= L1OFF_MBIAS2_EN_5250;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	rtsx_set_l1off_sub(pcr, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct pcr_ops rts5264_pcr_ops = {</div><div class='add'>+	.turn_on_led = rts5264_turn_on_led,</div><div class='add'>+	.turn_off_led = rts5264_turn_off_led,</div><div class='add'>+	.extra_init_hw = rts5264_extra_init_hw,</div><div class='add'>+	.enable_auto_blink = rts5264_enable_auto_blink,</div><div class='add'>+	.disable_auto_blink = rts5264_disable_auto_blink,</div><div class='add'>+	.card_power_on = rts5264_card_power_on,</div><div class='add'>+	.card_power_off = rts5264_card_power_off,</div><div class='add'>+	.switch_output_voltage = rts5264_switch_output_voltage,</div><div class='add'>+	.force_power_down = rts5264_force_power_down,</div><div class='add'>+	.stop_cmd = rts5264_stop_cmd,</div><div class='add'>+	.set_aspm = rts5264_set_aspm,</div><div class='add'>+	.set_l1off_cfg_sub_d0 = rts5264_set_l1off_cfg_sub_d0,</div><div class='add'>+	.enable_ocp = rts5264_enable_ocp,</div><div class='add'>+	.disable_ocp = rts5264_disable_ocp,</div><div class='add'>+	.init_ocp = rts5264_init_ocp,</div><div class='add'>+	.process_ocp = rts5264_process_ocp,</div><div class='add'>+	.clear_ocpstat = rts5264_clear_ocpstat,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline u8 double_ssc_depth(u8 depth)</div><div class='add'>+{</div><div class='add'>+	return ((depth &gt; 1) ? (depth - 1) : depth);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,</div><div class='add'>+		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)</div><div class='add'>+{</div><div class='add'>+	int err, clk;</div><div class='add'>+	u16 n;</div><div class='add'>+	u8 clk_divider, mcu_cnt, div;</div><div class='add'>+	static const u8 depth[] = {</div><div class='add'>+		[RTSX_SSC_DEPTH_4M] = RTS5264_SSC_DEPTH_4M,</div><div class='add'>+		[RTSX_SSC_DEPTH_2M] = RTS5264_SSC_DEPTH_2M,</div><div class='add'>+		[RTSX_SSC_DEPTH_1M] = RTS5264_SSC_DEPTH_1M,</div><div class='add'>+		[RTSX_SSC_DEPTH_500K] = RTS5264_SSC_DEPTH_512K,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	if (initial_mode) {</div><div class='add'>+		/* We use 250k(around) here, in initial stage */</div><div class='add'>+		clk_divider = SD_CLK_DIVIDE_128;</div><div class='add'>+		card_clock = 30000000;</div><div class='add'>+	} else {</div><div class='add'>+		clk_divider = SD_CLK_DIVIDE_0;</div><div class='add'>+	}</div><div class='add'>+	err = rtsx_pci_write_register(pcr, SD_CFG1,</div><div class='add'>+			SD_CLK_DIVIDE_MASK, clk_divider);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	card_clock /= 1000000;</div><div class='add'>+	pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);</div><div class='add'>+</div><div class='add'>+	clk = card_clock;</div><div class='add'>+	if (!initial_mode &amp;&amp; double_clk)</div><div class='add'>+		clk = card_clock * 2;</div><div class='add'>+	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",</div><div class='add'>+		clk, pcr-&gt;cur_clock);</div><div class='add'>+</div><div class='add'>+	if (clk == pcr-&gt;cur_clock)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (pcr-&gt;ops-&gt;conv_clk_and_div_n)</div><div class='add'>+		n = pcr-&gt;ops-&gt;conv_clk_and_div_n(clk, CLK_TO_DIV_N);</div><div class='add'>+	else</div><div class='add'>+		n = clk - 4;</div><div class='add'>+	if ((clk &lt;= 4) || (n &gt; 396))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mcu_cnt = 125/clk + 3;</div><div class='add'>+	if (mcu_cnt &gt; 15)</div><div class='add'>+		mcu_cnt = 15;</div><div class='add'>+</div><div class='add'>+	div = CLK_DIV_1;</div><div class='add'>+	while ((n &lt; MIN_DIV_N_PCR - 4) &amp;&amp; (div &lt; CLK_DIV_8)) {</div><div class='add'>+		if (pcr-&gt;ops-&gt;conv_clk_and_div_n) {</div><div class='add'>+			int dbl_clk = pcr-&gt;ops-&gt;conv_clk_and_div_n(n,</div><div class='add'>+					DIV_N_TO_CLK) * 2;</div><div class='add'>+			n = pcr-&gt;ops-&gt;conv_clk_and_div_n(dbl_clk,</div><div class='add'>+					CLK_TO_DIV_N);</div><div class='add'>+		} else {</div><div class='add'>+			n = (n + 4) * 2 - 4;</div><div class='add'>+		}</div><div class='add'>+		div++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	n = (n / 2) - 1;</div><div class='add'>+	pcr_dbg(pcr, "n = %d, div = %d\n", n, div);</div><div class='add'>+</div><div class='add'>+	ssc_depth = depth[ssc_depth];</div><div class='add'>+	if (double_clk)</div><div class='add'>+		ssc_depth = double_ssc_depth(ssc_depth);</div><div class='add'>+</div><div class='add'>+	if (ssc_depth) {</div><div class='add'>+		if (div == CLK_DIV_2) {</div><div class='add'>+			if (ssc_depth &gt; 1)</div><div class='add'>+				ssc_depth -= 1;</div><div class='add'>+			else</div><div class='add'>+				ssc_depth = RTS5264_SSC_DEPTH_8M;</div><div class='add'>+		} else if (div == CLK_DIV_4) {</div><div class='add'>+			if (ssc_depth &gt; 2)</div><div class='add'>+				ssc_depth -= 2;</div><div class='add'>+			else</div><div class='add'>+				ssc_depth = RTS5264_SSC_DEPTH_8M;</div><div class='add'>+		} else if (div == CLK_DIV_8) {</div><div class='add'>+			if (ssc_depth &gt; 3)</div><div class='add'>+				ssc_depth -= 3;</div><div class='add'>+			else</div><div class='add'>+				ssc_depth = RTS5264_SSC_DEPTH_8M;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		ssc_depth = 0;</div><div class='add'>+	}</div><div class='add'>+	pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);</div><div class='add'>+</div><div class='add'>+	rtsx_pci_init_cmd(pcr);</div><div class='add'>+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,</div><div class='add'>+				CHANGE_CLK, CHANGE_CLK);</div><div class='add'>+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,</div><div class='add'>+			0xFF, (div &lt;&lt; 4) | mcu_cnt);</div><div class='add'>+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);</div><div class='add'>+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,</div><div class='add'>+			SSC_DEPTH_MASK, ssc_depth);</div><div class='add'>+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);</div><div class='add'>+</div><div class='add'>+	if (is_version(pcr, 0x5264, IC_VER_A)) {</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_CARD_CLK_SRC2,</div><div class='add'>+			RTS5264_REG_BIG_KVCO_A, 0);</div><div class='add'>+	} else {</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS5264_SYS_DUMMY_1,</div><div class='add'>+			RTS5264_REG_BIG_KVCO, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vpclk) {</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,</div><div class='add'>+				PHASE_NOT_RESET, 0);</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,</div><div class='add'>+				PHASE_NOT_RESET, 0);</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,</div><div class='add'>+				PHASE_NOT_RESET, PHASE_NOT_RESET);</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,</div><div class='add'>+				PHASE_NOT_RESET, PHASE_NOT_RESET);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = rtsx_pci_send_cmd(pcr, 2000);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* Wait SSC clock stable */</div><div class='add'>+	udelay(SSC_CLOCK_STABLE_WAIT);</div><div class='add'>+	err = rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	pcr-&gt;cur_clock = clk;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void rts5264_init_params(struct rtsx_pcr *pcr)</div><div class='add'>+{</div><div class='add'>+	struct rtsx_cr_option *option = &amp;pcr-&gt;option;</div><div class='add'>+	struct rtsx_hw_param *hw_param = &amp;pcr-&gt;hw_param;</div><div class='add'>+	u8 val;</div><div class='add'>+</div><div class='add'>+	pcr-&gt;extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;</div><div class='add'>+	pcr-&gt;extra_caps |= EXTRA_CAPS_NO_MMC;</div><div class='add'>+	rtsx_pci_read_register(pcr, RTS5264_FW_STATUS, &amp;val);</div><div class='add'>+	if (!(val &amp; RTS5264_EXPRESS_LINK_FAIL_MASK))</div><div class='add'>+		pcr-&gt;extra_caps |= EXTRA_CAPS_SD_EXPRESS;</div><div class='add'>+	pcr-&gt;num_slots = 1;</div><div class='add'>+	pcr-&gt;ops = &amp;rts5264_pcr_ops;</div><div class='add'>+</div><div class='add'>+	pcr-&gt;flags = 0;</div><div class='add'>+	pcr-&gt;card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;</div><div class='add'>+	pcr-&gt;sd30_drive_sel_1v8 = 0x00;</div><div class='add'>+	pcr-&gt;sd30_drive_sel_3v3 = 0x00;</div><div class='add'>+	pcr-&gt;aspm_en = ASPM_L1_EN;</div><div class='add'>+	pcr-&gt;aspm_mode = ASPM_MODE_REG;</div><div class='add'>+	pcr-&gt;tx_initial_phase = SET_CLOCK_PHASE(24, 24, 11);</div><div class='add'>+	pcr-&gt;rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);</div><div class='add'>+</div><div class='add'>+	pcr-&gt;ic_version = rts5264_get_ic_version(pcr);</div><div class='add'>+	pcr-&gt;sd_pull_ctl_enable_tbl = rts5264_sd_pull_ctl_enable_tbl;</div><div class='add'>+	pcr-&gt;sd_pull_ctl_disable_tbl = rts5264_sd_pull_ctl_disable_tbl;</div><div class='add'>+</div><div class='add'>+	pcr-&gt;reg_pm_ctrl3 = RTS5264_AUTOLOAD_CFG3;</div><div class='add'>+</div><div class='add'>+	option-&gt;dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN</div><div class='add'>+				| LTR_L1SS_PWR_GATE_EN);</div><div class='add'>+	option-&gt;ltr_en = true;</div><div class='add'>+</div><div class='add'>+	/* init latency of active, idle, L1OFF to 60us, 300us, 3ms */</div><div class='add'>+	option-&gt;ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;</div><div class='add'>+	option-&gt;ltr_idle_latency = LTR_IDLE_LATENCY_DEF;</div><div class='add'>+	option-&gt;ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;</div><div class='add'>+	option-&gt;l1_snooze_delay = L1_SNOOZE_DELAY_DEF;</div><div class='add'>+	option-&gt;ltr_l1off_sspwrgate = 0x7F;</div><div class='add'>+	option-&gt;ltr_l1off_snooze_sspwrgate = 0x78;</div><div class='add'>+</div><div class='add'>+	option-&gt;ocp_en = 1;</div><div class='add'>+	hw_param-&gt;interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);</div><div class='add'>+	hw_param-&gt;ocp_glitch =  SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;</div><div class='add'>+	option-&gt;sd_800mA_ocp_thd =  RTS5264_LDO1_OCP_THD_1150;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/misc/cardreader/rts5264.h b/drivers/misc/cardreader/rts5264.h<br/>new file mode 100644<br/>index 000000000000..e3cbbf2fe1a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rts5264.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rts5264.h</a></div><div class='hunk'>@@ -0,0 +1,278 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/* Driver for Realtek PCI-Express card reader</div><div class='add'>+ *</div><div class='add'>+ * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.</div><div class='add'>+ *</div><div class='add'>+ * Author:</div><div class='add'>+ *   Ricky Wu &lt;ricky_wu@realtek.com&gt;</div><div class='add'>+ */</div><div class='add'>+#ifndef RTS5264_H</div><div class='add'>+#define RTS5264_H</div><div class='add'>+</div><div class='add'>+/*New add*/</div><div class='add'>+#define rts5264_vendor_setting_valid(reg)	((reg) &amp; 0x010000)</div><div class='add'>+#define rts5264_reg_to_aspm(reg) \</div><div class='add'>+	(((~(reg) &gt;&gt; 28) &amp; 0x02) | (((reg) &gt;&gt; 28) &amp; 0x01))</div><div class='add'>+#define rts5264_reg_check_reverse_socket(reg)	((reg) &amp; 0x04)</div><div class='add'>+#define rts5264_reg_to_sd30_drive_sel_1v8(reg)	(((reg) &gt;&gt; 22) &amp; 0x03)</div><div class='add'>+#define rts5264_reg_to_sd30_drive_sel_3v3(reg)	(((reg) &gt;&gt; 16) &amp; 0x03)</div><div class='add'>+#define rts5264_reg_to_rtd3(reg)		((reg) &amp; 0x08)</div><div class='add'>+</div><div class='add'>+#define RTS5264_AUTOLOAD_CFG0		0xFF7B</div><div class='add'>+#define RTS5264_AUTOLOAD_CFG1		0xFF7C</div><div class='add'>+#define RTS5264_AUTOLOAD_CFG3		0xFF7E</div><div class='add'>+#define RTS5264_AUTOLOAD_CFG4		0xFF7F</div><div class='add'>+#define RTS5264_FORCE_PRSNT_LOW		(1 &lt;&lt; 6)</div><div class='add'>+#define RTS5264_AUX_CLK_16M_EN		(1 &lt;&lt; 5)</div><div class='add'>+#define RTS5264_F_HIGH_RC_MASK		(1 &lt;&lt; 4)</div><div class='add'>+#define RTS5264_F_HIGH_RC_1_6M		(1 &lt;&lt; 4)</div><div class='add'>+#define RTS5264_F_HIGH_RC_400K		(0 &lt;&lt; 4)</div><div class='add'>+</div><div class='add'>+/* SSC_CTL2 0xFC12 */</div><div class='add'>+#define RTS5264_SSC_DEPTH_MASK		0x07</div><div class='add'>+#define RTS5264_SSC_DEPTH_DISALBE	0x00</div><div class='add'>+#define RTS5264_SSC_DEPTH_8M		0x01</div><div class='add'>+#define RTS5264_SSC_DEPTH_4M		0x02</div><div class='add'>+#define RTS5264_SSC_DEPTH_2M		0x03</div><div class='add'>+#define RTS5264_SSC_DEPTH_1M		0x04</div><div class='add'>+#define RTS5264_SSC_DEPTH_512K		0x05</div><div class='add'>+#define RTS5264_SSC_DEPTH_256K		0x06</div><div class='add'>+#define RTS5264_SSC_DEPTH_128K		0x07</div><div class='add'>+</div><div class='add'>+#define RTS5264_CARD_CLK_SRC2		0xFC2F</div><div class='add'>+#define RTS5264_REG_BIG_KVCO_A		0x20</div><div class='add'>+</div><div class='add'>+/* efuse control register*/</div><div class='add'>+#define RTS5264_EFUSE_CTL		0xFC30</div><div class='add'>+#define RTS5264_EFUSE_ENABLE		0x80</div><div class='add'>+/* EFUSE_MODE: 0=READ 1=PROGRAM */</div><div class='add'>+#define RTS5264_EFUSE_MODE_MASK		0x40</div><div class='add'>+#define RTS5264_EFUSE_PROGRAM		0x40</div><div class='add'>+</div><div class='add'>+#define RTS5264_EFUSE_ADDR		0xFC31</div><div class='add'>+#define	RTS5264_EFUSE_ADDR_MASK		0x3F</div><div class='add'>+</div><div class='add'>+#define RTS5264_EFUSE_WRITE_DATA	0xFC32</div><div class='add'>+#define RTS5264_EFUSE_READ_DATA		0xFC34</div><div class='add'>+</div><div class='add'>+#define RTS5264_SYS_DUMMY_1		0xFC35</div><div class='add'>+#define RTS5264_REG_BIG_KVCO		0x04</div><div class='add'>+</div><div class='add'>+/* DMACTL 0xFE2C */</div><div class='add'>+#define RTS5264_DMA_PACK_SIZE_MASK	0x70</div><div class='add'>+</div><div class='add'>+#define RTS5264_FW_CFG1			0xFF55</div><div class='add'>+#define RTS5264_SYS_CLK_SEL_MCU_CLK	(0x01&lt;&lt;7)</div><div class='add'>+#define RTS5264_CRC_CLK_SEL_MCU_CLK	(0x01&lt;&lt;6)</div><div class='add'>+#define RTS5264_FAKE_MCU_CLOCK_GATING	(0x01&lt;&lt;5)</div><div class='add'>+#define RTS5264_MCU_BUS_SEL_MASK	(0x01&lt;&lt;4)</div><div class='add'>+</div><div class='add'>+/* FW status register */</div><div class='add'>+#define RTS5264_FW_STATUS		0xFF56</div><div class='add'>+#define RTS5264_EXPRESS_LINK_FAIL_MASK	(0x01&lt;&lt;7)</div><div class='add'>+</div><div class='add'>+/* FW control register */</div><div class='add'>+#define RTS5264_FW_CTL			0xFF5F</div><div class='add'>+#define RTS5264_INFORM_RTD3_COLD	(0x01&lt;&lt;5)</div><div class='add'>+</div><div class='add'>+#define RTS5264_REG_FPDCTL		0xFF60</div><div class='add'>+</div><div class='add'>+#define RTS5264_REG_LDO12_CFG		0xFF6E</div><div class='add'>+#define RTS5264_LDO12_SR_MASK		(0x03&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO12_SR_1_0_MS		(0x03&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO12_SR_0_5_MS		(0x02&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO12_SR_0_2_5_MS	(0x01&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO12_SR_0_0_MS		(0x00&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO12_VO_TUNE_MASK	(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO12_115		(0x03&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO12_120		(0x04&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO12_125		(0x05&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO12_130		(0x06&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO12_135		(0x07&lt;&lt;1)</div><div class='add'>+</div><div class='add'>+/* LDO control register */</div><div class='add'>+#define RTS5264_CARD_PWR_CTL		0xFD50</div><div class='add'>+#define RTS5264_SD_CLK_ISO		(0x01&lt;&lt;7)</div><div class='add'>+#define RTS5264_PAD_SD_DAT_FW_CTRL	(0x01&lt;&lt;6)</div><div class='add'>+#define RTS5264_PUPDC			(0x01&lt;&lt;5)</div><div class='add'>+#define RTS5264_SD_CMD_ISO		(0x01&lt;&lt;4)</div><div class='add'>+</div><div class='add'>+#define RTS5264_OCP_VDD3_CTL		0xFD89</div><div class='add'>+#define SD_VDD3_DETECT_EN		0x08</div><div class='add'>+#define SD_VDD3_OCP_INT_EN		0x04</div><div class='add'>+#define SD_VDD3_OCP_INT_CLR		0x02</div><div class='add'>+#define SD_VDD3_OC_CLR			0x01</div><div class='add'>+</div><div class='add'>+#define RTS5264_OCP_VDD3_STS		0xFD8A</div><div class='add'>+#define SD_VDD3_OCP_DETECT		0x08</div><div class='add'>+#define SD_VDD3_OC_NOW			0x04</div><div class='add'>+#define SD_VDD3_OC_EVER			0x02</div><div class='add'>+</div><div class='add'>+#define RTS5264_OVP_CTL			0xFD8D</div><div class='add'>+#define RTS5264_OVP_TIME_MASK		0xF0</div><div class='add'>+#define RTS5264_OVP_TIME_DFT		0x50</div><div class='add'>+#define RTS5264_OVP_DETECT_EN		0x08</div><div class='add'>+#define RTS5264_OVP_INT_EN		0x04</div><div class='add'>+#define RTS5264_OVP_INT_CLR		0x02</div><div class='add'>+#define RTS5264_OVP_CLR			0x01</div><div class='add'>+</div><div class='add'>+#define RTS5264_OVP_STS			0xFD8E</div><div class='add'>+#define RTS5264_OVP_GLTCH_TIME_MASK	0xF0</div><div class='add'>+#define RTS5264_OVP_GLTCH_TIME_DFT	0x50</div><div class='add'>+#define RTS5264_VOVER_DET		0x08</div><div class='add'>+#define RTS5264_OVP_NOW			0x04</div><div class='add'>+#define RTS5264_OVP_EVER		0x02</div><div class='add'>+</div><div class='add'>+#define RTS5264_CMD_OE_START_EARLY		0xFDCB</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_LEAVE		0x08</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_CYCLE_MASK		0x06</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_4CYCLE		0x06</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_3CYCLE		0x04</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_2CYCLE		0x02</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_1CYCLE		0x00</div><div class='add'>+#define RTS5264_CMD_OE_EARLY_EN			0x01</div><div class='add'>+</div><div class='add'>+#define RTS5264_DAT_OE_START_EARLY		0xFDCC</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_LEAVE		0x08</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_CYCLE_MASK		0x06</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_4CYCLE		0x06</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_3CYCLE		0x04</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_2CYCLE		0x02</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_1CYCLE		0x00</div><div class='add'>+#define RTS5264_DAT_OE_EARLY_EN			0x01</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO1233318_POW_CTL	0xFF70</div><div class='add'>+#define RTS5264_TUNE_REF_LDO3318	(0x03&lt;&lt;6)</div><div class='add'>+#define RTS5264_TUNE_REF_LDO3318_DFT	(0x02&lt;&lt;6)</div><div class='add'>+#define RTS5264_LDO3318_POWERON		(0x01&lt;&lt;3)</div><div class='add'>+#define RTS5264_LDO3_POWERON		(0x01&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO2_POWERON		(0x01&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO1_POWERON		(0x01&lt;&lt;0)</div><div class='add'>+#define RTS5264_LDO_POWERON_MASK	(0x0F&lt;&lt;0)</div><div class='add'>+</div><div class='add'>+#define RTS5264_DV3318_CFG		0xFF71</div><div class='add'>+#define RTS5264_DV3318_TUNE_MASK	(0x07&lt;&lt;4)</div><div class='add'>+#define RTS5264_DV3318_18		(0x02&lt;&lt;4)</div><div class='add'>+#define RTS5264_DV3318_19		(0x04&lt;&lt;4)</div><div class='add'>+#define RTS5264_DV3318_33		(0x07&lt;&lt;4)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO1_CFG0		0xFF72</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_MASK	(0x07 &lt;&lt; 5)</div><div class='add'>+#define RTS5264_LDO1_OCP_EN		(0x01 &lt;&lt; 4)</div><div class='add'>+#define RTS5264_LDO1_OCP_LMT_THD_MASK	(0x03 &lt;&lt; 2)</div><div class='add'>+#define RTS5264_LDO1_OCP_LMT_EN		(0x01 &lt;&lt; 1)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_850	(0x00&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_950	(0x01&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1050	(0x02&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1100	(0x03&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1150	(0x04&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1200	(0x05&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1300	(0x06&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO1_OCP_THD_1350	(0x07&lt;&lt;5)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO1_LMT_THD_1700	(0x00&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO1_LMT_THD_1800	(0x01&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO1_LMT_THD_1900	(0x02&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO1_LMT_THD_2000	(0x03&lt;&lt;2)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO1_CFG1		0xFF73</div><div class='add'>+#define RTS5264_LDO1_TUNE_MASK		(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO1_18			(0x05&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO1_33			(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO1_PWD_MASK		(0x01&lt;&lt;0)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO2_CFG0		0xFF74</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_MASK	(0x07&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_EN		(0x01&lt;&lt;4)</div><div class='add'>+#define RTS5264_LDO2_OCP_LMT_THD_MASK	(0x03&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO2_OCP_LMT_EN		(0x01&lt;&lt;1)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_750	(0x00&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_850	(0x01&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_900	(0x02&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_950	(0x03&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_1050	(0x04&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_1100	(0x05&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_1150	(0x06&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO2_OCP_THD_1200	(0x07&lt;&lt;5)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO2_LMT_THD_1700	(0x00&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO2_LMT_THD_1800	(0x01&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO2_LMT_THD_1900	(0x02&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO2_LMT_THD_2000	(0x03&lt;&lt;2)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO2_CFG1		0xFF75</div><div class='add'>+#define RTS5264_LDO2_TUNE_MASK		(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_18			(0x02&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_185		(0x03&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_19			(0x04&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_195		(0x05&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_33			(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO2_PWD_MASK		(0x01&lt;&lt;0)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO3_CFG0		0xFF76</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_MASK	(0x07&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_EN		(0x01&lt;&lt;4)</div><div class='add'>+#define RTS5264_LDO3_OCP_LMT_THD_MASK	(0x03&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO3_OCP_LMT_EN		(0x01&lt;&lt;1)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_610	(0x00&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_630	(0x01&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_670	(0x02&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_710	(0x03&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_750	(0x04&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_770	(0x05&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_810	(0x06&lt;&lt;5)</div><div class='add'>+#define RTS5264_LDO3_OCP_THD_850	(0x07&lt;&lt;5)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO3_LMT_THD_1200	(0x00&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO3_LMT_THD_1300	(0x01&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO3_LMT_THD_1400	(0x02&lt;&lt;2)</div><div class='add'>+#define RTS5264_LDO3_LMT_THD_1500	(0x03&lt;&lt;2)</div><div class='add'>+</div><div class='add'>+#define RTS5264_LDO3_CFG1		0xFF77</div><div class='add'>+#define RTS5264_LDO3_TUNE_MASK		(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_12			(0x02&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_125		(0x03&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_13			(0x04&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_135		(0x05&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_33			(0x07&lt;&lt;1)</div><div class='add'>+#define RTS5264_LDO3_PWD_MASK		(0x01&lt;&lt;0)</div><div class='add'>+</div><div class='add'>+#define RTS5264_REG_PME_FORCE_CTL	0xFF78</div><div class='add'>+#define FORCE_PM_CONTROL		0x20</div><div class='add'>+#define FORCE_PM_VALUE			0x10</div><div class='add'>+#define REG_EFUSE_BYPASS		0x08</div><div class='add'>+#define REG_EFUSE_POR			0x04</div><div class='add'>+#define REG_EFUSE_POWER_MASK		0x03</div><div class='add'>+#define REG_EFUSE_POWERON		0x03</div><div class='add'>+#define REG_EFUSE_POWEROFF		0x00</div><div class='add'>+</div><div class='add'>+#define RTS5264_PWR_CUT			0xFF81</div><div class='add'>+#define RTS5264_CFG_MEM_PD		0xF0</div><div class='add'>+</div><div class='add'>+#define RTS5264_OVP_DET			0xFF8A</div><div class='add'>+#define RTS5264_POW_VDET		0x04</div><div class='add'>+#define RTS5264_TUNE_VROV_MASK		0x03</div><div class='add'>+#define RTS5264_TUNE_VROV_2V		0x03</div><div class='add'>+#define RTS5264_TUNE_VROV_1V8		0x02</div><div class='add'>+#define RTS5264_TUNE_VROV_1V6		0x01</div><div class='add'>+#define RTS5264_TUNE_VROV_1V4		0x00</div><div class='add'>+</div><div class='add'>+#define RTS5264_CKMUX_MBIAS_PWR		0xFF8B</div><div class='add'>+#define RTS5264_NON_XTAL_SEL		0x80</div><div class='add'>+#define RTS5264_POW_CKMUX		0x40</div><div class='add'>+#define RTS5264_LVD_MASK		0x04</div><div class='add'>+#define RTS5264_POW_PSW_MASK		0x03</div><div class='add'>+#define RTS5264_POW_PSW_DFT		0x03</div><div class='add'>+</div><div class='add'>+/* Single LUN, support SD/SD EXPRESS */</div><div class='add'>+#define DEFAULT_SINGLE		0</div><div class='add'>+#define SD_LUN			1</div><div class='add'>+#define SD_EXPRESS_LUN		2</div><div class='add'>+</div><div class='add'>+int rts5264_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,</div><div class='add'>+		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);</div><div class='add'>+</div><div class='add'>+#endif /* RTS5264_H */</div><div class='head'>diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c<br/>index a30751ad3733..1a64364700eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rtsx_pcr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/cardreader/rtsx_pcr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rtsx_pcr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rtsx_pcr.c</a></div><div class='hunk'>@@ -26,6 +26,7 @@</div><div class='ctx'> #include "rtsx_pcr.h"</div><div class='ctx'> #include "rts5261.h"</div><div class='ctx'> #include "rts5228.h"</div><div class='add'>+#include "rts5264.h"</div><div class='ctx'> </div><div class='ctx'> static bool msi_en = true;</div><div class='ctx'> module_param(msi_en, bool, S_IRUGO | S_IWUSR);</div><div class='hunk'>@@ -54,6 +55,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {</div><div class='ctx'> 	{ PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS &lt;&lt; 16, 0xFF0000 },</div><div class='ctx'> 	{ PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS &lt;&lt; 16, 0xFF0000 },</div><div class='ctx'> 	{ PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS &lt;&lt; 16, 0xFF0000 },</div><div class='add'>+	{ PCI_DEVICE(0x10EC, 0x5264), PCI_CLASS_OTHERS &lt;&lt; 16, 0xFF0000 },</div><div class='ctx'> 	{ 0, }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -714,6 +716,9 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,</div><div class='ctx'> 	if (PCI_PID(pcr) == PID_5228)</div><div class='ctx'> 		return rts5228_pci_switch_clock(pcr, card_clock,</div><div class='ctx'> 				ssc_depth, initial_mode, double_clk, vpclk);</div><div class='add'>+	if (PCI_PID(pcr) == PID_5264)</div><div class='add'>+		return rts5264_pci_switch_clock(pcr, card_clock,</div><div class='add'>+				ssc_depth, initial_mode, double_clk, vpclk);</div><div class='ctx'> </div><div class='ctx'> 	if (initial_mode) {</div><div class='ctx'> 		/* We use 250k(around) here, in initial stage */</div><div class='hunk'>@@ -987,7 +992,8 @@ static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)</div><div class='ctx'> </div><div class='ctx'> 	int_reg &amp;= (pcr-&gt;bier | 0x7FFFFF);</div><div class='ctx'> </div><div class='del'>-	if (int_reg &amp; SD_OC_INT)</div><div class='add'>+	if ((int_reg &amp; SD_OC_INT) ||</div><div class='add'>+			((int_reg &amp; SD_OVP_INT) &amp;&amp; (PCI_PID(pcr) == PID_5264)))</div><div class='ctx'> 		rtsx_pci_process_ocp_interrupt(pcr);</div><div class='ctx'> </div><div class='ctx'> 	if (int_reg &amp; SD_INT) {</div><div class='hunk'>@@ -1159,7 +1165,9 @@ void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)</div><div class='ctx'> {</div><div class='ctx'> 	u16 val;</div><div class='ctx'> </div><div class='del'>-	if ((PCI_PID(pcr) != PID_525A) &amp;&amp; (PCI_PID(pcr) != PID_5260)) {</div><div class='add'>+	if ((PCI_PID(pcr) != PID_525A) &amp;&amp;</div><div class='add'>+		(PCI_PID(pcr) != PID_5260) &amp;&amp;</div><div class='add'>+		(PCI_PID(pcr) != PID_5264)) {</div><div class='ctx'> 		rtsx_pci_read_phy_register(pcr, 0x01, &amp;val);</div><div class='ctx'> 		val |= 1&lt;&lt;9;</div><div class='ctx'> 		rtsx_pci_write_phy_register(pcr, 0x01, val);</div><div class='hunk'>@@ -1175,7 +1183,9 @@ void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)</div><div class='ctx'> {</div><div class='ctx'> 	u16 val;</div><div class='ctx'> </div><div class='del'>-	if ((PCI_PID(pcr) != PID_525A) &amp;&amp; (PCI_PID(pcr) != PID_5260)) {</div><div class='add'>+	if ((PCI_PID(pcr) != PID_525A) &amp;&amp;</div><div class='add'>+		(PCI_PID(pcr) != PID_5260) &amp;&amp;</div><div class='add'>+		(PCI_PID(pcr) != PID_5264)) {</div><div class='ctx'> 		rtsx_pci_read_phy_register(pcr, 0x01, &amp;val);</div><div class='ctx'> 		val &amp;= ~(1&lt;&lt;9);</div><div class='ctx'> 		rtsx_pci_write_phy_register(pcr, 0x01, val);</div><div class='hunk'>@@ -1226,7 +1236,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)</div><div class='ctx'> 	rtsx_pci_enable_bus_int(pcr);</div><div class='ctx'> </div><div class='ctx'> 	/* Power on SSC */</div><div class='del'>-	if (PCI_PID(pcr) == PID_5261) {</div><div class='add'>+	if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {</div><div class='ctx'> 		/* Gating real mcu clock */</div><div class='ctx'> 		err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,</div><div class='ctx'> 			RTS5261_MCU_CLOCK_GATING, 0);</div><div class='hunk'>@@ -1270,6 +1280,11 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)</div><div class='ctx'> 	else if (PCI_PID(pcr) == PID_5228)</div><div class='ctx'> 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,</div><div class='ctx'> 			RTS5228_SSC_DEPTH_2M);</div><div class='add'>+	else if (is_version(pcr, 0x5264, IC_VER_A))</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);</div><div class='add'>+	else if (PCI_PID(pcr) == PID_5264)</div><div class='add'>+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,</div><div class='add'>+			RTS5264_SSC_DEPTH_2M);</div><div class='ctx'> 	else</div><div class='ctx'> 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);</div><div class='ctx'> </div><div class='hunk'>@@ -1305,6 +1320,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)</div><div class='ctx'> 	case PID_5260:</div><div class='ctx'> 	case PID_5261:</div><div class='ctx'> 	case PID_5228:</div><div class='add'>+	case PID_5264:</div><div class='ctx'> 		rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1404,6 +1420,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)</div><div class='ctx'> 	case 0x5228:</div><div class='ctx'> 		rts5228_init_params(pcr);</div><div class='ctx'> 		break;</div><div class='add'>+</div><div class='add'>+	case 0x5264:</div><div class='add'>+		rts5264_init_params(pcr);</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",</div><div class='hunk'>@@ -1544,7 +1564,7 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,</div><div class='ctx'> 	pcr-&gt;pci = pcidev;</div><div class='ctx'> 	dev_set_drvdata(&amp;pcidev-&gt;dev, handle);</div><div class='ctx'> </div><div class='del'>-	if (CHK_PCI_PID(pcr, 0x525A))</div><div class='add'>+	if ((CHK_PCI_PID(pcr, 0x525A)) || (CHK_PCI_PID(pcr, 0x5264)))</div><div class='ctx'> 		bar = 1;</div><div class='ctx'> 	len = pci_resource_len(pcidev, bar);</div><div class='ctx'> 	base = pci_resource_start(pcidev, bar);</div><div class='head'>diff --git a/drivers/misc/cardreader/rtsx_pcr.h b/drivers/misc/cardreader/rtsx_pcr.h<br/>index 37d1f316ae17..9215d66de00c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rtsx_pcr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/cardreader/rtsx_pcr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cardreader/rtsx_pcr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cardreader/rtsx_pcr.h</a></div><div class='hunk'>@@ -74,6 +74,7 @@ void rtl8411b_init_params(struct rtsx_pcr *pcr);</div><div class='ctx'> void rts5260_init_params(struct rtsx_pcr *pcr);</div><div class='ctx'> void rts5261_init_params(struct rtsx_pcr *pcr);</div><div class='ctx'> void rts5228_init_params(struct rtsx_pcr *pcr);</div><div class='add'>+void rts5264_init_params(struct rtsx_pcr *pcr);</div><div class='ctx'> </div><div class='ctx'> static inline u8 map_sd_drive(int idx)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h<br/>index 0562071cdd4a..6ad0ab892675 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/cxl/cxl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/cxl/cxl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/cxl/cxl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/cxl/cxl.h</a></div><div class='hunk'>@@ -836,7 +836,8 @@ static inline bool cxl_is_power8(void)</div><div class='ctx'> {</div><div class='ctx'> 	if ((pvr_version_is(PVR_POWER8E)) ||</div><div class='ctx'> 	    (pvr_version_is(PVR_POWER8NVL)) ||</div><div class='del'>-	    (pvr_version_is(PVR_POWER8)))</div><div class='add'>+	    (pvr_version_is(PVR_POWER8)) ||</div><div class='add'>+	    (pvr_version_is(PVR_HX_C2000)))</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/misc/dw-xdata-pcie.c b/drivers/misc/dw-xdata-pcie.c<br/>index 257c25da5199..efd0ca8cc925 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/dw-xdata-pcie.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/dw-xdata-pcie.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/dw-xdata-pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/dw-xdata-pcie.c</a></div><div class='hunk'>@@ -333,7 +333,7 @@ static int dw_xdata_pcie_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	dw-&gt;pdev = pdev;</div><div class='ctx'> </div><div class='del'>-	id = ida_simple_get(&amp;xdata_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	id = ida_alloc(&amp;xdata_ida, GFP_KERNEL);</div><div class='ctx'> 	if (id &lt; 0) {</div><div class='ctx'> 		dev_err(dev, "xData: unable to get id\n");</div><div class='ctx'> 		return id;</div><div class='hunk'>@@ -377,7 +377,7 @@ err_kfree_name:</div><div class='ctx'> 	kfree(dw-&gt;misc_dev.name);</div><div class='ctx'> </div><div class='ctx'> err_ida_remove:</div><div class='del'>-	ida_simple_remove(&amp;xdata_ida, id);</div><div class='add'>+	ida_free(&amp;xdata_ida, id);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -396,7 +396,7 @@ static void dw_xdata_pcie_remove(struct pci_dev *pdev)</div><div class='ctx'> 	dw_xdata_stop(dw);</div><div class='ctx'> 	misc_deregister(&amp;dw-&gt;misc_dev);</div><div class='ctx'> 	kfree(dw-&gt;misc_dev.name);</div><div class='del'>-	ida_simple_remove(&amp;xdata_ida, id);</div><div class='add'>+	ida_free(&amp;xdata_ida, id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id dw_xdata_pcie_id_table[] = {</div><div class='head'>diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c<br/>index f61a80597a22..572333ead5fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/eeprom/at24.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/eeprom/at24.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/eeprom/at24.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/eeprom/at24.c</a></div><div class='hunk'>@@ -18,6 +18,7 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/mutex.h&gt;</div><div class='ctx'> #include &lt;linux/nvmem-provider.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='hunk'>@@ -242,7 +243,7 @@ static const struct i2c_device_id at24_ids[] = {</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(i2c, at24_ids);</div><div class='ctx'> </div><div class='del'>-static const struct of_device_id at24_of_match[] = {</div><div class='add'>+static const struct of_device_id __maybe_unused at24_of_match[] = {</div><div class='ctx'> 	{ .compatible = "atmel,24c00",		.data = &amp;at24_data_24c00 },</div><div class='ctx'> 	{ .compatible = "atmel,24c01",		.data = &amp;at24_data_24c01 },</div><div class='ctx'> 	{ .compatible = "atmel,24cs01",		.data = &amp;at24_data_24cs01 },</div><div class='hunk'>@@ -439,12 +440,9 @@ static int at24_read(void *priv, unsigned int off, void *val, size_t count)</div><div class='ctx'> 	if (off + count &gt; at24-&gt;byte_len)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = pm_runtime_get_sync(dev);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		pm_runtime_put_noidle(dev);</div><div class='add'>+	ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+	if (ret)</div><div class='ctx'> 		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Read data from chip, protecting against concurrent updates</div><div class='ctx'> 	 * from this host, but not from other I2C masters.</div><div class='hunk'>@@ -486,12 +484,9 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)</div><div class='ctx'> 	if (off + count &gt; at24-&gt;byte_len)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ret = pm_runtime_get_sync(dev);</div><div class='del'>-	if (ret &lt; 0) {</div><div class='del'>-		pm_runtime_put_noidle(dev);</div><div class='add'>+	ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+	if (ret)</div><div class='ctx'> 		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Write data to chip, protecting against concurrent updates</div><div class='ctx'> 	 * from this host, but not from other I2C masters.</div><div class='hunk'>@@ -563,6 +558,31 @@ static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void at24_probe_temp_sensor(struct i2c_client *client)</div><div class='add'>+{</div><div class='add'>+	struct at24_data *at24 = i2c_get_clientdata(client);</div><div class='add'>+	struct i2c_board_info info = { .type = "jc42" };</div><div class='add'>+	int ret;</div><div class='add'>+	u8 val;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Byte 2 has value 11 for DDR3, earlier versions don't</div><div class='add'>+	 * support the thermal sensor present flag</div><div class='add'>+	 */</div><div class='add'>+	ret = at24_read(at24, 2, &amp;val, 1);</div><div class='add'>+	if (ret || val != 11)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Byte 32, bit 7 is set if temp sensor is present */</div><div class='add'>+	ret = at24_read(at24, 32, &amp;val, 1);</div><div class='add'>+	if (ret || !(val &amp; BIT(7)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	info.addr = 0x18 | (client-&gt;addr &amp; 7);</div><div class='add'>+</div><div class='add'>+	i2c_new_client_device(client-&gt;adapter, &amp;info);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int at24_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='ctx'> 	struct regmap_config regmap_config = { };</div><div class='hunk'>@@ -762,6 +782,10 @@ static int at24_probe(struct i2c_client *client)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* If this a SPD EEPROM, probe for DDR3 thermal sensor */</div><div class='add'>+	if (cdata == &amp;at24_data_spd)</div><div class='add'>+		at24_probe_temp_sensor(client);</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_idle(dev);</div><div class='ctx'> </div><div class='ctx'> 	if (writable)</div><div class='hunk'>@@ -812,7 +836,7 @@ static struct i2c_driver at24_driver = {</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "at24",</div><div class='ctx'> 		.pm = &amp;at24_pm_ops,</div><div class='del'>-		.of_match_table = at24_of_match,</div><div class='add'>+		.of_match_table = of_match_ptr(at24_of_match),</div><div class='ctx'> 		.acpi_match_table = ACPI_PTR(at24_acpi_ids),</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = at24_probe,</div><div class='head'>diff --git a/drivers/misc/eeprom/ee1004.c b/drivers/misc/eeprom/ee1004.c<br/>index a1acd77130f2..21feebc3044c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/eeprom/ee1004.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/eeprom/ee1004.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/eeprom/ee1004.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/eeprom/ee1004.c</a></div><div class='hunk'>@@ -31,6 +31,7 @@</div><div class='ctx'>  * over performance.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#define EE1004_MAX_BUSSES		8</div><div class='ctx'> #define EE1004_ADDR_SET_PAGE		0x36</div><div class='ctx'> #define EE1004_NUM_PAGES		2</div><div class='ctx'> #define EE1004_PAGE_SIZE		256</div><div class='hunk'>@@ -42,9 +43,13 @@</div><div class='ctx'>  * from page selection to end of read.</div><div class='ctx'>  */</div><div class='ctx'> static DEFINE_MUTEX(ee1004_bus_lock);</div><div class='del'>-static struct i2c_client *ee1004_set_page[EE1004_NUM_PAGES];</div><div class='del'>-static unsigned int ee1004_dev_count;</div><div class='del'>-static int ee1004_current_page;</div><div class='add'>+</div><div class='add'>+static struct ee1004_bus_data {</div><div class='add'>+	struct i2c_adapter *adap;</div><div class='add'>+	struct i2c_client *set_page[EE1004_NUM_PAGES];</div><div class='add'>+	unsigned int dev_count;</div><div class='add'>+	int current_page;</div><div class='add'>+} ee1004_bus_data[EE1004_MAX_BUSSES];</div><div class='ctx'> </div><div class='ctx'> static const struct i2c_device_id ee1004_ids[] = {</div><div class='ctx'> 	{ "ee1004", 0 },</div><div class='hunk'>@@ -54,11 +59,29 @@ MODULE_DEVICE_TABLE(i2c, ee1004_ids);</div><div class='ctx'> </div><div class='ctx'> /*-------------------------------------------------------------------------*/</div><div class='ctx'> </div><div class='del'>-static int ee1004_get_current_page(void)</div><div class='add'>+static struct ee1004_bus_data *ee1004_get_bus_data(struct i2c_adapter *adap)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; EE1004_MAX_BUSSES; i++)</div><div class='add'>+		if (ee1004_bus_data[i].adap == adap)</div><div class='add'>+			return ee1004_bus_data + i;</div><div class='add'>+</div><div class='add'>+	/* If not existent yet, create new entry */</div><div class='add'>+	for (i = 0; i &lt; EE1004_MAX_BUSSES; i++)</div><div class='add'>+		if (!ee1004_bus_data[i].adap) {</div><div class='add'>+			ee1004_bus_data[i].adap = adap;</div><div class='add'>+			return ee1004_bus_data + i;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ee1004_get_current_page(struct ee1004_bus_data *bd)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = i2c_smbus_read_byte(ee1004_set_page[0]);</div><div class='add'>+	err = i2c_smbus_read_byte(bd-&gt;set_page[0]);</div><div class='ctx'> 	if (err == -ENXIO) {</div><div class='ctx'> 		/* Nack means page 1 is selected */</div><div class='ctx'> 		return 1;</div><div class='hunk'>@@ -72,28 +95,29 @@ static int ee1004_get_current_page(void)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ee1004_set_current_page(struct device *dev, int page)</div><div class='add'>+static int ee1004_set_current_page(struct i2c_client *client, int page)</div><div class='ctx'> {</div><div class='add'>+	struct ee1004_bus_data *bd = i2c_get_clientdata(client);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (page == ee1004_current_page)</div><div class='add'>+	if (page == bd-&gt;current_page)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Data is ignored */</div><div class='del'>-	ret = i2c_smbus_write_byte(ee1004_set_page[page], 0x00);</div><div class='add'>+	ret = i2c_smbus_write_byte(bd-&gt;set_page[page], 0x00);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Don't give up just yet. Some memory modules will select the page</div><div class='ctx'> 	 * but not ack the command. Check which page is selected now.</div><div class='ctx'> 	 */</div><div class='del'>-	if (ret == -ENXIO &amp;&amp; ee1004_get_current_page() == page)</div><div class='add'>+	if (ret == -ENXIO &amp;&amp; ee1004_get_current_page(bd) == page)</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 	if (ret &lt; 0) {</div><div class='del'>-		dev_err(dev, "Failed to select page %d (%d)\n", page, ret);</div><div class='add'>+		dev_err(&amp;client-&gt;dev, "Failed to select page %d (%d)\n", page, ret);</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	dev_dbg(dev, "Selected page %d\n", page);</div><div class='del'>-	ee1004_current_page = page;</div><div class='add'>+	dev_dbg(&amp;client-&gt;dev, "Selected page %d\n", page);</div><div class='add'>+	bd-&gt;current_page = page;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -106,7 +130,7 @@ static ssize_t ee1004_eeprom_read(struct i2c_client *client, char *buf,</div><div class='ctx'> 	page = offset &gt;&gt; EE1004_PAGE_SHIFT;</div><div class='ctx'> 	offset &amp;= (1 &lt;&lt; EE1004_PAGE_SHIFT) - 1;</div><div class='ctx'> </div><div class='del'>-	status = ee1004_set_current_page(&amp;client-&gt;dev, page);</div><div class='add'>+	status = ee1004_set_current_page(client, page);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='hunk'>@@ -158,17 +182,34 @@ static struct bin_attribute *ee1004_attrs[] = {</div><div class='ctx'> </div><div class='ctx'> BIN_ATTRIBUTE_GROUPS(ee1004);</div><div class='ctx'> </div><div class='del'>-static void ee1004_cleanup(int idx)</div><div class='add'>+static void ee1004_probe_temp_sensor(struct i2c_client *client)</div><div class='ctx'> {</div><div class='del'>-	if (--ee1004_dev_count == 0)</div><div class='del'>-		while (--idx &gt;= 0) {</div><div class='del'>-			i2c_unregister_device(ee1004_set_page[idx]);</div><div class='del'>-			ee1004_set_page[idx] = NULL;</div><div class='del'>-		}</div><div class='add'>+	struct i2c_board_info info = { .type = "jc42" };</div><div class='add'>+	u8 byte14;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* byte 14, bit 7 is set if temp sensor is present */</div><div class='add'>+	ret = ee1004_eeprom_read(client, &amp;byte14, 14, 1);</div><div class='add'>+	if (ret != 1 || !(byte14 &amp; BIT(7)))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	info.addr = 0x18 | (client-&gt;addr &amp; 7);</div><div class='add'>+</div><div class='add'>+	i2c_new_client_device(client-&gt;adapter, &amp;info);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ee1004_cleanup(int idx, struct ee1004_bus_data *bd)</div><div class='add'>+{</div><div class='add'>+	if (--bd-&gt;dev_count == 0) {</div><div class='add'>+		while (--idx &gt;= 0)</div><div class='add'>+			i2c_unregister_device(bd-&gt;set_page[idx]);</div><div class='add'>+		memset(bd, 0, sizeof(struct ee1004_bus_data));</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ee1004_probe(struct i2c_client *client)</div><div class='ctx'> {</div><div class='add'>+	struct ee1004_bus_data *bd;</div><div class='ctx'> 	int err, cnr = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Make sure we can operate on this adapter */</div><div class='hunk'>@@ -178,9 +219,19 @@ static int ee1004_probe(struct i2c_client *client)</div><div class='ctx'> 				     I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_READ_BYTE_DATA))</div><div class='ctx'> 		return -EPFNOSUPPORT;</div><div class='ctx'> </div><div class='del'>-	/* Use 2 dummy devices for page select command */</div><div class='ctx'> 	mutex_lock(&amp;ee1004_bus_lock);</div><div class='del'>-	if (++ee1004_dev_count == 1) {</div><div class='add'>+</div><div class='add'>+	bd = ee1004_get_bus_data(client-&gt;adapter);</div><div class='add'>+	if (!bd) {</div><div class='add'>+		mutex_unlock(&amp;ee1004_bus_lock);</div><div class='add'>+		return dev_err_probe(&amp;client-&gt;dev, -ENOSPC,</div><div class='add'>+				     "Only %d busses supported", EE1004_MAX_BUSSES);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	i2c_set_clientdata(client, bd);</div><div class='add'>+</div><div class='add'>+	if (++bd-&gt;dev_count == 1) {</div><div class='add'>+		/* Use 2 dummy devices for page select command */</div><div class='ctx'> 		for (cnr = 0; cnr &lt; EE1004_NUM_PAGES; cnr++) {</div><div class='ctx'> 			struct i2c_client *cl;</div><div class='ctx'> </div><div class='hunk'>@@ -189,21 +240,19 @@ static int ee1004_probe(struct i2c_client *client)</div><div class='ctx'> 				err = PTR_ERR(cl);</div><div class='ctx'> 				goto err_clients;</div><div class='ctx'> 			}</div><div class='del'>-			ee1004_set_page[cnr] = cl;</div><div class='add'>+			bd-&gt;set_page[cnr] = cl;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Remember current page to avoid unneeded page select */</div><div class='del'>-		err = ee1004_get_current_page();</div><div class='add'>+		err = ee1004_get_current_page(bd);</div><div class='ctx'> 		if (err &lt; 0)</div><div class='ctx'> 			goto err_clients;</div><div class='ctx'> 		dev_dbg(&amp;client-&gt;dev, "Currently selected page: %d\n", err);</div><div class='del'>-		ee1004_current_page = err;</div><div class='del'>-	} else if (client-&gt;adapter != ee1004_set_page[0]-&gt;adapter) {</div><div class='del'>-		dev_err(&amp;client-&gt;dev,</div><div class='del'>-			"Driver only supports devices on a single I2C bus\n");</div><div class='del'>-		err = -EOPNOTSUPP;</div><div class='del'>-		goto err_clients;</div><div class='add'>+		bd-&gt;current_page = err;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	ee1004_probe_temp_sensor(client);</div><div class='add'>+</div><div class='ctx'> 	mutex_unlock(&amp;ee1004_bus_lock);</div><div class='ctx'> </div><div class='ctx'> 	dev_info(&amp;client-&gt;dev,</div><div class='hunk'>@@ -213,7 +262,7 @@ static int ee1004_probe(struct i2c_client *client)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'>  err_clients:</div><div class='del'>-	ee1004_cleanup(cnr);</div><div class='add'>+	ee1004_cleanup(cnr, bd);</div><div class='ctx'> 	mutex_unlock(&amp;ee1004_bus_lock);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -221,9 +270,11 @@ static int ee1004_probe(struct i2c_client *client)</div><div class='ctx'> </div><div class='ctx'> static void ee1004_remove(struct i2c_client *client)</div><div class='ctx'> {</div><div class='add'>+	struct ee1004_bus_data *bd = i2c_get_clientdata(client);</div><div class='add'>+</div><div class='ctx'> 	/* Remove page select clients if this is the last device */</div><div class='ctx'> 	mutex_lock(&amp;ee1004_bus_lock);</div><div class='del'>-	ee1004_cleanup(EE1004_NUM_PAGES);</div><div class='add'>+	ee1004_cleanup(EE1004_NUM_PAGES, bd);</div><div class='ctx'> 	mutex_unlock(&amp;ee1004_bus_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/genwqe/card_dev.c b/drivers/misc/genwqe/card_dev.c<br/>index 55fc5b80e649..4441aca2280a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/genwqe/card_dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/genwqe/card_dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/genwqe/card_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/genwqe/card_dev.c</a></div><div class='hunk'>@@ -443,7 +443,7 @@ static int genwqe_mmap(struct file *filp, struct vm_area_struct *vma)</div><div class='ctx'> 	if (vsize == 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (get_order(vsize) &gt; MAX_ORDER)</div><div class='add'>+	if (get_order(vsize) &gt; MAX_PAGE_ORDER)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	dma_map = kzalloc(sizeof(struct dma_mapping), GFP_KERNEL);</div><div class='head'>diff --git a/drivers/misc/genwqe/card_utils.c b/drivers/misc/genwqe/card_utils.c<br/>index 1c798d6b2dfb..a2c4a9b4f871 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/genwqe/card_utils.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/genwqe/card_utils.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/genwqe/card_utils.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/genwqe/card_utils.c</a></div><div class='hunk'>@@ -210,7 +210,7 @@ u32 genwqe_crc32(u8 *buff, size_t len, u32 init)</div><div class='ctx'> void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,</div><div class='ctx'> 			       dma_addr_t *dma_handle)</div><div class='ctx'> {</div><div class='del'>-	if (get_order(size) &gt; MAX_ORDER)</div><div class='add'>+	if (get_order(size) &gt; MAX_PAGE_ORDER)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	return dma_alloc_coherent(&amp;cd-&gt;pci_dev-&gt;dev, size, dma_handle,</div><div class='hunk'>@@ -308,7 +308,7 @@ int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl,</div><div class='ctx'> 	sgl-&gt;write = write;</div><div class='ctx'> 	sgl-&gt;sgl_size = genwqe_sgl_size(sgl-&gt;nr_pages);</div><div class='ctx'> </div><div class='del'>-	if (get_order(sgl-&gt;sgl_size) &gt; MAX_ORDER) {</div><div class='add'>+	if (get_order(sgl-&gt;sgl_size) &gt; MAX_PAGE_ORDER) {</div><div class='ctx'> 		dev_err(&amp;pci_dev-&gt;dev,</div><div class='ctx'> 			"[%s] err: too much memory requested!\n", __func__);</div><div class='ctx'> 		return ret;</div><div class='head'>diff --git a/drivers/misc/lis3lv02d/lis3lv02d_i2c.c b/drivers/misc/lis3lv02d/lis3lv02d_i2c.c<br/>index 3882e97e96a7..c6eb27d46cb0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/lis3lv02d/lis3lv02d_i2c.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/lis3lv02d/lis3lv02d_i2c.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/lis3lv02d/lis3lv02d_i2c.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/lis3lv02d/lis3lv02d_i2c.c</a></div><div class='hunk'>@@ -150,6 +150,7 @@ static int lis3lv02d_i2c_probe(struct i2c_client *client)</div><div class='ctx'> 	lis3_dev.init	  = lis3_i2c_init;</div><div class='ctx'> 	lis3_dev.read	  = lis3_i2c_read;</div><div class='ctx'> 	lis3_dev.write	  = lis3_i2c_write;</div><div class='add'>+	lis3_dev.reg_ctrl = lis3_reg_ctrl;</div><div class='ctx'> 	lis3_dev.irq	  = client-&gt;irq;</div><div class='ctx'> 	lis3_dev.ac	  = lis3lv02d_axis_map;</div><div class='ctx'> 	lis3_dev.pm_dev	  = &amp;client-&gt;dev;</div><div class='head'>diff --git a/drivers/misc/lkdtm/heap.c b/drivers/misc/lkdtm/heap.c<br/>index 0ce4cbf6abda..4f467d3972a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/lkdtm/heap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/lkdtm/heap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/lkdtm/heap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/lkdtm/heap.c</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'>  * page allocation and slab allocations.</div><div class='ctx'>  */</div><div class='ctx'> #include "lkdtm.h"</div><div class='add'>+#include &lt;linux/kfence.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='ctx'> #include &lt;linux/sched.h&gt;</div><div class='hunk'>@@ -132,6 +133,64 @@ static void lkdtm_READ_AFTER_FREE(void)</div><div class='ctx'> 	kfree(val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void lkdtm_KFENCE_READ_AFTER_FREE(void)</div><div class='add'>+{</div><div class='add'>+	int *base, val, saw;</div><div class='add'>+	unsigned long timeout, resched_after;</div><div class='add'>+	size_t len = 1024;</div><div class='add'>+	/*</div><div class='add'>+	 * The slub allocator will use the either the first word or</div><div class='add'>+	 * the middle of the allocation to store the free pointer,</div><div class='add'>+	 * depending on configurations. Store in the second word to</div><div class='add'>+	 * avoid running into the freelist.</div><div class='add'>+	 */</div><div class='add'>+	size_t offset = sizeof(*base);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * 100x the sample interval should be more than enough to ensure we get</div><div class='add'>+	 * a KFENCE allocation eventually.</div><div class='add'>+	 */</div><div class='add'>+	timeout = jiffies + msecs_to_jiffies(100 * kfence_sample_interval);</div><div class='add'>+	/*</div><div class='add'>+	 * Especially for non-preemption kernels, ensure the allocation-gate</div><div class='add'>+	 * timer can catch up: after @resched_after, every failed allocation</div><div class='add'>+	 * attempt yields, to ensure the allocation-gate timer is scheduled.</div><div class='add'>+	 */</div><div class='add'>+	resched_after = jiffies + msecs_to_jiffies(kfence_sample_interval);</div><div class='add'>+	do {</div><div class='add'>+		base = kmalloc(len, GFP_KERNEL);</div><div class='add'>+		if (!base) {</div><div class='add'>+			pr_err("FAIL: Unable to allocate kfence memory!\n");</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (is_kfence_address(base)) {</div><div class='add'>+			val = 0x12345678;</div><div class='add'>+			base[offset] = val;</div><div class='add'>+			pr_info("Value in memory before free: %x\n", base[offset]);</div><div class='add'>+</div><div class='add'>+			kfree(base);</div><div class='add'>+</div><div class='add'>+			pr_info("Attempting bad read from freed memory\n");</div><div class='add'>+			saw = base[offset];</div><div class='add'>+			if (saw != val) {</div><div class='add'>+				/* Good! Poisoning happened, so declare a win. */</div><div class='add'>+				pr_info("Memory correctly poisoned (%x)\n", saw);</div><div class='add'>+			} else {</div><div class='add'>+				pr_err("FAIL: Memory was not poisoned!\n");</div><div class='add'>+				pr_expected_config_param(CONFIG_INIT_ON_FREE_DEFAULT_ON, "init_on_free");</div><div class='add'>+			}</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		kfree(base);</div><div class='add'>+		if (time_after(jiffies, resched_after))</div><div class='add'>+			cond_resched();</div><div class='add'>+	} while (time_before(jiffies, timeout));</div><div class='add'>+</div><div class='add'>+	pr_err("FAIL: kfence memory never allocated!\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void lkdtm_WRITE_BUDDY_AFTER_FREE(void)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long p = __get_free_page(GFP_KERNEL);</div><div class='hunk'>@@ -327,6 +386,7 @@ static struct crashtype crashtypes[] = {</div><div class='ctx'> 	CRASHTYPE(VMALLOC_LINEAR_OVERFLOW),</div><div class='ctx'> 	CRASHTYPE(WRITE_AFTER_FREE),</div><div class='ctx'> 	CRASHTYPE(READ_AFTER_FREE),</div><div class='add'>+	CRASHTYPE(KFENCE_READ_AFTER_FREE),</div><div class='ctx'> 	CRASHTYPE(WRITE_BUDDY_AFTER_FREE),</div><div class='ctx'> 	CRASHTYPE(READ_BUDDY_AFTER_FREE),</div><div class='ctx'> 	CRASHTYPE(SLAB_INIT_ON_ALLOC),</div><div class='head'>diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig<br/>index 37db142de413..67d9391f1855 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/Kconfig</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> config INTEL_MEI</div><div class='ctx'> 	tristate "Intel Management Engine Interface"</div><div class='ctx'> 	depends on X86 &amp;&amp; PCI</div><div class='add'>+	default GENERIC_CPU || MCORE2 || MATOM || X86_GENERIC</div><div class='ctx'> 	help</div><div class='ctx'> 	  The Intel Management Engine (Intel ME) provides Manageability,</div><div class='ctx'> 	  Security and Media services for system containing Intel chipsets.</div><div class='hunk'>@@ -11,10 +12,11 @@ config INTEL_MEI</div><div class='ctx'> 	  For more information see</div><div class='ctx'> 	  &lt;https://software.intel.com/en-us/manageability/&gt;</div><div class='ctx'> </div><div class='add'>+if INTEL_MEI</div><div class='add'>+</div><div class='ctx'> config INTEL_MEI_ME</div><div class='ctx'> 	tristate "ME Enabled Intel Chipsets"</div><div class='del'>-	select INTEL_MEI</div><div class='del'>-	depends on X86 &amp;&amp; PCI</div><div class='add'>+	default y</div><div class='ctx'> 	help</div><div class='ctx'> 	  MEI support for ME Enabled Intel chipsets.</div><div class='ctx'> </div><div class='hunk'>@@ -38,8 +40,6 @@ config INTEL_MEI_ME</div><div class='ctx'> </div><div class='ctx'> config INTEL_MEI_TXE</div><div class='ctx'> 	tristate "Intel Trusted Execution Environment with ME Interface"</div><div class='del'>-	select INTEL_MEI</div><div class='del'>-	depends on X86 &amp;&amp; PCI</div><div class='ctx'> 	help</div><div class='ctx'> 	  MEI Support for Trusted Execution Environment device on Intel SoCs</div><div class='ctx'> </div><div class='hunk'>@@ -48,9 +48,7 @@ config INTEL_MEI_TXE</div><div class='ctx'> </div><div class='ctx'> config INTEL_MEI_GSC</div><div class='ctx'> 	tristate "Intel MEI GSC embedded device"</div><div class='del'>-	depends on INTEL_MEI</div><div class='ctx'> 	depends on INTEL_MEI_ME</div><div class='del'>-	depends on X86 &amp;&amp; PCI</div><div class='ctx'> 	depends on DRM_I915</div><div class='ctx'> 	help</div><div class='ctx'> 	  Intel auxiliary driver for GSC devices embedded in Intel graphics devices.</div><div class='hunk'>@@ -60,6 +58,31 @@ config INTEL_MEI_GSC</div><div class='ctx'> 	  tasks such as graphics card firmware update and security</div><div class='ctx'> 	  tasks.</div><div class='ctx'> </div><div class='add'>+config INTEL_MEI_VSC_HW</div><div class='add'>+	tristate "Intel visual sensing controller device transport driver"</div><div class='add'>+	depends on ACPI &amp;&amp; SPI</div><div class='add'>+	depends on GPIOLIB || COMPILE_TEST</div><div class='add'>+	help</div><div class='add'>+	  Intel SPI transport driver between host and Intel visual sensing</div><div class='add'>+	  controller (IVSC) device.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module</div><div class='add'>+	  will be called mei-vsc-hw.</div><div class='add'>+</div><div class='add'>+config INTEL_MEI_VSC</div><div class='add'>+	tristate "Intel visual sensing controller device with ME interface"</div><div class='add'>+	depends on INTEL_MEI_VSC_HW</div><div class='add'>+	help</div><div class='add'>+	  Intel MEI over SPI driver for Intel visual sensing controller</div><div class='add'>+	  (IVSC) device embedded in IA platform. It supports camera sharing</div><div class='add'>+	  between IVSC for context sensing and IPU for typical media usage.</div><div class='add'>+	  Select this config should enable transport layer for IVSC device.</div><div class='add'>+</div><div class='add'>+	  This driver can also be built as a module. If so, the module</div><div class='add'>+	  will be called mei-vsc.</div><div class='add'>+</div><div class='ctx'> source "drivers/misc/mei/hdcp/Kconfig"</div><div class='ctx'> source "drivers/misc/mei/pxp/Kconfig"</div><div class='ctx'> source "drivers/misc/mei/gsc_proxy/Kconfig"</div><div class='add'>+</div><div class='add'>+endif</div><div class='head'>diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile<br/>index 14aee253ae48..6f9fdbf1a495 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/Makefile</a></div><div class='hunk'>@@ -31,3 +31,10 @@ CFLAGS_mei-trace.o = -I$(src)</div><div class='ctx'> obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/</div><div class='ctx'> obj-$(CONFIG_INTEL_MEI_PXP) += pxp/</div><div class='ctx'> obj-$(CONFIG_INTEL_MEI_GSC_PROXY) += gsc_proxy/</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_INTEL_MEI_VSC_HW) += mei-vsc-hw.o</div><div class='add'>+mei-vsc-hw-y := vsc-tp.o</div><div class='add'>+mei-vsc-hw-y += vsc-fw-loader.o</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_INTEL_MEI_VSC) += mei-vsc.o</div><div class='add'>+mei-vsc-y := platform-vsc.o</div><div class='head'>diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c<br/>index 9c8fc87938a7..9d090fa07516 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/client.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/client.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/client.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/client.c</a></div><div class='hunk'>@@ -2011,7 +2011,7 @@ ssize_t mei_cl_write(struct mei_cl *cl, struct mei_cl_cb *cb, unsigned long time</div><div class='ctx'> </div><div class='ctx'> 	mei_hdr = mei_msg_hdr_init(cb);</div><div class='ctx'> 	if (IS_ERR(mei_hdr)) {</div><div class='del'>-		rets = -PTR_ERR(mei_hdr);</div><div class='add'>+		rets = PTR_ERR(mei_hdr);</div><div class='ctx'> 		mei_hdr = NULL;</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2032,7 +2032,7 @@ ssize_t mei_cl_write(struct mei_cl *cl, struct mei_cl_cb *cb, unsigned long time</div><div class='ctx'> </div><div class='ctx'> 	hbuf_slots = mei_hbuf_empty_slots(dev);</div><div class='ctx'> 	if (hbuf_slots &lt; 0) {</div><div class='del'>-		rets = -EOVERFLOW;</div><div class='add'>+		buf_len = -EOVERFLOW;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/mei/gsc_proxy/Kconfig b/drivers/misc/mei/gsc_proxy/Kconfig<br/>index 5f68d9f3d691..ac78b9d1eccd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/gsc_proxy/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/gsc_proxy/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/gsc_proxy/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/gsc_proxy/Kconfig</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'> #</div><div class='ctx'> config INTEL_MEI_GSC_PROXY</div><div class='ctx'> 	tristate "Intel GSC Proxy services of ME Interface"</div><div class='del'>-	select INTEL_MEI_ME</div><div class='add'>+	depends on INTEL_MEI_ME</div><div class='ctx'> 	depends on DRM_I915</div><div class='ctx'> 	help</div><div class='ctx'>          MEI Support for GSC Proxy Services on Intel platforms.</div><div class='head'>diff --git a/drivers/misc/mei/hdcp/Kconfig b/drivers/misc/mei/hdcp/Kconfig<br/>index 54e1c9526909..9be312ec798d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/hdcp/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/hdcp/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/hdcp/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/hdcp/Kconfig</a></div><div class='hunk'>@@ -3,7 +3,7 @@</div><div class='ctx'> #</div><div class='ctx'> config INTEL_MEI_HDCP</div><div class='ctx'> 	tristate "Intel HDCP2.2 services of ME Interface"</div><div class='del'>-	select INTEL_MEI_ME</div><div class='add'>+	depends on INTEL_MEI_ME</div><div class='ctx'> 	depends on DRM_I915</div><div class='ctx'> 	help</div><div class='ctx'> 	  MEI Support for HDCP2.2 Services on Intel platforms.</div><div class='head'>diff --git a/drivers/misc/mei/platform-vsc.c b/drivers/misc/mei/platform-vsc.c<br/>new file mode 100644<br/>index 000000000000..8d303c6c0000<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/platform-vsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/platform-vsc.c</a></div><div class='hunk'>@@ -0,0 +1,450 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Intel Corporation.</div><div class='add'>+ * Intel Visual Sensing Controller Interface Linux driver</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+#include &lt;linux/cache.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='add'>+#include &lt;linux/mei.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/overflow.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/timekeeping.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm-generic/bug.h&gt;</div><div class='add'>+#include &lt;asm-generic/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include "mei_dev.h"</div><div class='add'>+#include "vsc-tp.h"</div><div class='add'>+</div><div class='add'>+#define MEI_VSC_DRV_NAME		"intel_vsc"</div><div class='add'>+</div><div class='add'>+#define MEI_VSC_MAX_MSG_SIZE		512</div><div class='add'>+</div><div class='add'>+#define MEI_VSC_POLL_DELAY_US		(50 * USEC_PER_MSEC)</div><div class='add'>+#define MEI_VSC_POLL_TIMEOUT_US		(200 * USEC_PER_MSEC)</div><div class='add'>+</div><div class='add'>+#define mei_dev_to_vsc_hw(dev)		((struct mei_vsc_hw *)((dev)-&gt;hw))</div><div class='add'>+</div><div class='add'>+struct mei_vsc_host_timestamp {</div><div class='add'>+	u64 realtime;</div><div class='add'>+	u64 boottime;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mei_vsc_hw {</div><div class='add'>+	struct vsc_tp *tp;</div><div class='add'>+</div><div class='add'>+	bool fw_ready;</div><div class='add'>+	bool host_ready;</div><div class='add'>+</div><div class='add'>+	atomic_t write_lock_cnt;</div><div class='add'>+</div><div class='add'>+	u32 rx_len;</div><div class='add'>+	u32 rx_hdr;</div><div class='add'>+</div><div class='add'>+	/* buffer for tx */</div><div class='add'>+	char tx_buf[MEI_VSC_MAX_MSG_SIZE + sizeof(struct mei_msg_hdr)] ____cacheline_aligned;</div><div class='add'>+	/* buffer for rx */</div><div class='add'>+	char rx_buf[MEI_VSC_MAX_MSG_SIZE + sizeof(struct mei_msg_hdr)] ____cacheline_aligned;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mei_vsc_read_helper(struct mei_vsc_hw *hw, u8 *buf,</div><div class='add'>+			       u32 max_len)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_host_timestamp ts = {</div><div class='add'>+		.realtime = ktime_to_ns(ktime_get_real()),</div><div class='add'>+		.boottime = ktime_to_ns(ktime_get_boottime()),</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	return vsc_tp_xfer(hw-&gt;tp, VSC_TP_CMD_READ, &amp;ts, sizeof(ts),</div><div class='add'>+			   buf, max_len);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_write_helper(struct mei_vsc_hw *hw, u8 *buf, u32 len)</div><div class='add'>+{</div><div class='add'>+	u8 status;</div><div class='add'>+</div><div class='add'>+	return vsc_tp_xfer(hw-&gt;tp, VSC_TP_CMD_WRITE, buf, len, &amp;status,</div><div class='add'>+			   sizeof(status));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_fw_status(struct mei_device *mei_dev,</div><div class='add'>+			     struct mei_fw_status *fw_status)</div><div class='add'>+{</div><div class='add'>+	if (!fw_status)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	fw_status-&gt;count = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline enum mei_pg_state mei_vsc_pg_state(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return MEI_PG_OFF;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mei_vsc_intr_enable(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	vsc_tp_intr_enable(hw-&gt;tp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mei_vsc_intr_disable(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	vsc_tp_intr_disable(hw-&gt;tp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* mei framework requires this ops */</div><div class='add'>+static void mei_vsc_intr_clear(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* wait for pending irq handler */</div><div class='add'>+static void mei_vsc_synchronize_irq(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	vsc_tp_intr_synchronize(hw-&gt;tp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_hw_config(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mei_vsc_host_is_ready(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	return hw-&gt;host_ready;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mei_vsc_hw_is_ready(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	return hw-&gt;fw_ready;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_hw_start(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	int ret, rlen;</div><div class='add'>+	u8 buf;</div><div class='add'>+</div><div class='add'>+	hw-&gt;host_ready = true;</div><div class='add'>+</div><div class='add'>+	vsc_tp_intr_enable(hw-&gt;tp);</div><div class='add'>+</div><div class='add'>+	ret = read_poll_timeout(mei_vsc_read_helper, rlen,</div><div class='add'>+				rlen &gt;= 0, MEI_VSC_POLL_DELAY_US,</div><div class='add'>+				MEI_VSC_POLL_TIMEOUT_US, true,</div><div class='add'>+				hw, &amp;buf, sizeof(buf));</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(mei_dev-&gt;dev, "wait fw ready failed: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hw-&gt;fw_ready = true;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mei_vsc_hbuf_is_ready(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	return atomic_read(&amp;hw-&gt;write_lock_cnt) == 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_hbuf_empty_slots(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return MEI_VSC_MAX_MSG_SIZE / MEI_SLOT_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 mei_vsc_hbuf_depth(const struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return MEI_VSC_MAX_MSG_SIZE / MEI_SLOT_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_write(struct mei_device *mei_dev,</div><div class='add'>+			 const void *hdr, size_t hdr_len,</div><div class='add'>+			 const void *data, size_t data_len)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	char *buf = hw-&gt;tx_buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(!hdr || !IS_ALIGNED(hdr_len, 4)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!data || data_len &gt; MEI_VSC_MAX_MSG_SIZE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	atomic_inc(&amp;hw-&gt;write_lock_cnt);</div><div class='add'>+</div><div class='add'>+	memcpy(buf, hdr, hdr_len);</div><div class='add'>+	memcpy(buf + hdr_len, data, data_len);</div><div class='add'>+</div><div class='add'>+	ret = mei_vsc_write_helper(hw, buf, hdr_len + data_len);</div><div class='add'>+</div><div class='add'>+	atomic_dec_if_positive(&amp;hw-&gt;write_lock_cnt);</div><div class='add'>+</div><div class='add'>+	return ret &lt; 0 ? ret : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline u32 mei_vsc_read(const struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mei_vsc_read_helper(hw, hw-&gt;rx_buf, sizeof(hw-&gt;rx_buf));</div><div class='add'>+	if (ret &lt; 0 || ret &lt; sizeof(u32))</div><div class='add'>+		return 0;</div><div class='add'>+	hw-&gt;rx_len = ret;</div><div class='add'>+</div><div class='add'>+	hw-&gt;rx_hdr = get_unaligned_le32(hw-&gt;rx_buf);</div><div class='add'>+</div><div class='add'>+	return hw-&gt;rx_hdr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_count_full_read_slots(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return MEI_VSC_MAX_MSG_SIZE / MEI_SLOT_SIZE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_read_slots(struct mei_device *mei_dev, unsigned char *buf,</div><div class='add'>+			      unsigned long len)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	struct mei_msg_hdr *hdr;</div><div class='add'>+</div><div class='add'>+	hdr = (struct mei_msg_hdr *)&amp;hw-&gt;rx_hdr;</div><div class='add'>+	if (len != hdr-&gt;length || hdr-&gt;length + sizeof(*hdr) != hw-&gt;rx_len)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	memcpy(buf, hw-&gt;rx_buf + sizeof(*hdr), len);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mei_vsc_pg_in_transition(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return mei_dev-&gt;pg_event &gt;= MEI_PG_EVENT_WAIT &amp;&amp;</div><div class='add'>+	       mei_dev-&gt;pg_event &lt;= MEI_PG_EVENT_INTR_WAIT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mei_vsc_pg_is_enabled(struct mei_device *mei_dev)</div><div class='add'>+{</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_hw_reset(struct mei_device *mei_dev, bool intr_enable)</div><div class='add'>+{</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+</div><div class='add'>+	vsc_tp_reset(hw-&gt;tp);</div><div class='add'>+</div><div class='add'>+	vsc_tp_intr_disable(hw-&gt;tp);</div><div class='add'>+</div><div class='add'>+	return vsc_tp_init(hw-&gt;tp, mei_dev-&gt;dev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mei_hw_ops mei_vsc_hw_ops = {</div><div class='add'>+	.fw_status = mei_vsc_fw_status,</div><div class='add'>+	.pg_state = mei_vsc_pg_state,</div><div class='add'>+</div><div class='add'>+	.host_is_ready = mei_vsc_host_is_ready,</div><div class='add'>+	.hw_is_ready = mei_vsc_hw_is_ready,</div><div class='add'>+	.hw_reset = mei_vsc_hw_reset,</div><div class='add'>+	.hw_config = mei_vsc_hw_config,</div><div class='add'>+	.hw_start = mei_vsc_hw_start,</div><div class='add'>+</div><div class='add'>+	.pg_in_transition = mei_vsc_pg_in_transition,</div><div class='add'>+	.pg_is_enabled = mei_vsc_pg_is_enabled,</div><div class='add'>+</div><div class='add'>+	.intr_clear = mei_vsc_intr_clear,</div><div class='add'>+	.intr_enable = mei_vsc_intr_enable,</div><div class='add'>+	.intr_disable = mei_vsc_intr_disable,</div><div class='add'>+	.synchronize_irq = mei_vsc_synchronize_irq,</div><div class='add'>+</div><div class='add'>+	.hbuf_free_slots = mei_vsc_hbuf_empty_slots,</div><div class='add'>+	.hbuf_is_ready = mei_vsc_hbuf_is_ready,</div><div class='add'>+	.hbuf_depth = mei_vsc_hbuf_depth,</div><div class='add'>+	.write = mei_vsc_write,</div><div class='add'>+</div><div class='add'>+	.rdbuf_full_slots = mei_vsc_count_full_read_slots,</div><div class='add'>+	.read_hdr = mei_vsc_read,</div><div class='add'>+	.read = mei_vsc_read_slots,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void mei_vsc_event_cb(void *context)</div><div class='add'>+{</div><div class='add'>+	struct mei_device *mei_dev = context;</div><div class='add'>+	struct mei_vsc_hw *hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	struct list_head cmpl_list;</div><div class='add'>+	s32 slots;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (mei_dev-&gt;dev_state == MEI_DEV_RESETTING ||</div><div class='add'>+	    mei_dev-&gt;dev_state == MEI_DEV_INITIALIZING)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;cmpl_list);</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;mei_dev-&gt;device_lock);</div><div class='add'>+</div><div class='add'>+	while (vsc_tp_need_read(hw-&gt;tp)) {</div><div class='add'>+		/* check slots available for reading */</div><div class='add'>+		slots = mei_count_full_read_slots(mei_dev);</div><div class='add'>+</div><div class='add'>+		ret = mei_irq_read_handler(mei_dev, &amp;cmpl_list, &amp;slots);</div><div class='add'>+		if (ret) {</div><div class='add'>+			if (ret != -ENODATA) {</div><div class='add'>+				if (mei_dev-&gt;dev_state != MEI_DEV_RESETTING &amp;&amp;</div><div class='add'>+				    mei_dev-&gt;dev_state != MEI_DEV_POWER_DOWN)</div><div class='add'>+					schedule_work(&amp;mei_dev-&gt;reset_work);</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mei_dev-&gt;hbuf_is_ready = mei_hbuf_is_ready(mei_dev);</div><div class='add'>+	ret = mei_irq_write_handler(mei_dev, &amp;cmpl_list);</div><div class='add'>+	if (ret)</div><div class='add'>+		dev_err(mei_dev-&gt;dev, "dispatch write request failed: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	mei_dev-&gt;hbuf_is_ready = mei_hbuf_is_ready(mei_dev);</div><div class='add'>+	mei_irq_compl_handler(mei_dev, &amp;cmpl_list);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct mei_device *mei_dev;</div><div class='add'>+	struct mei_vsc_hw *hw;</div><div class='add'>+	struct vsc_tp *tp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	tp = *(struct vsc_tp **)dev_get_platdata(dev);</div><div class='add'>+	if (!tp)</div><div class='add'>+		return dev_err_probe(dev, -ENODEV, "no platform data\n");</div><div class='add'>+</div><div class='add'>+	mei_dev = devm_kzalloc(dev, size_add(sizeof(*mei_dev), sizeof(*hw)),</div><div class='add'>+			       GFP_KERNEL);</div><div class='add'>+	if (!mei_dev)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	mei_device_init(mei_dev, dev, false, &amp;mei_vsc_hw_ops);</div><div class='add'>+	mei_dev-&gt;fw_f_fw_ver_supported = 0;</div><div class='add'>+	mei_dev-&gt;kind = "ivsc";</div><div class='add'>+</div><div class='add'>+	hw = mei_dev_to_vsc_hw(mei_dev);</div><div class='add'>+	atomic_set(&amp;hw-&gt;write_lock_cnt, 0);</div><div class='add'>+	hw-&gt;tp = tp;</div><div class='add'>+</div><div class='add'>+	platform_set_drvdata(pdev, mei_dev);</div><div class='add'>+</div><div class='add'>+	vsc_tp_register_event_cb(tp, mei_vsc_event_cb, mei_dev);</div><div class='add'>+</div><div class='add'>+	ret = mei_start(mei_dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err_probe(dev, ret, "init hw failed\n");</div><div class='add'>+		goto err_cancel;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mei_register(mei_dev, dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_stop;</div><div class='add'>+</div><div class='add'>+	pm_runtime_enable(mei_dev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_stop:</div><div class='add'>+	mei_stop(mei_dev);</div><div class='add'>+</div><div class='add'>+err_cancel:</div><div class='add'>+	mei_cancel_work(mei_dev);</div><div class='add'>+</div><div class='add'>+	mei_disable_interrupts(mei_dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct mei_device *mei_dev = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	pm_runtime_disable(mei_dev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	mei_stop(mei_dev);</div><div class='add'>+</div><div class='add'>+	mei_disable_interrupts(mei_dev);</div><div class='add'>+</div><div class='add'>+	mei_deregister(mei_dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_suspend(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_device *mei_dev = dev_get_drvdata(dev);</div><div class='add'>+</div><div class='add'>+	mei_stop(mei_dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mei_vsc_resume(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct mei_device *mei_dev = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = mei_restart(mei_dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* start timer if stopped in suspend */</div><div class='add'>+	schedule_delayed_work(&amp;mei_dev-&gt;timer_work, HZ);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static DEFINE_SIMPLE_DEV_PM_OPS(mei_vsc_pm_ops, mei_vsc_suspend, mei_vsc_resume);</div><div class='add'>+</div><div class='add'>+static const struct platform_device_id mei_vsc_id_table[] = {</div><div class='add'>+	{ MEI_VSC_DRV_NAME },</div><div class='add'>+	{ /* sentinel */ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(platform, mei_vsc_id_table);</div><div class='add'>+</div><div class='add'>+static struct platform_driver mei_vsc_drv = {</div><div class='add'>+	.probe = mei_vsc_probe,</div><div class='add'>+	.remove = mei_vsc_remove,</div><div class='add'>+	.id_table = mei_vsc_id_table,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = MEI_VSC_DRV_NAME,</div><div class='add'>+		.pm = &amp;mei_vsc_pm_ops,</div><div class='add'>+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_platform_driver(mei_vsc_drv);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Wentong Wu &lt;wentong.wu@intel.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Zhifeng Wang &lt;zhifeng.wang@intel.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Intel Visual Sensing Controller Interface");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='add'>+MODULE_IMPORT_NS(VSC_TP);</div><div class='head'>diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig<br/>index 4029b96afc04..e9219b61cd92 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/pxp/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/pxp/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/pxp/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/pxp/Kconfig</a></div><div class='hunk'>@@ -1,10 +1,9 @@</div><div class='del'>-</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> # Copyright (c) 2020, Intel Corporation. All rights reserved.</div><div class='ctx'> #</div><div class='ctx'> config INTEL_MEI_PXP</div><div class='ctx'> 	tristate "Intel PXP services of ME Interface"</div><div class='del'>-	select INTEL_MEI_ME</div><div class='add'>+	depends on INTEL_MEI_ME</div><div class='ctx'> 	depends on DRM_I915</div><div class='ctx'> 	help</div><div class='ctx'> 	  MEI Support for PXP Services on Intel platforms.</div><div class='head'>diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c<br/>index f77d78fa5054..787c6a27a4be 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/mei/pxp/mei_pxp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/mei/pxp/mei_pxp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/pxp/mei_pxp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/pxp/mei_pxp.c</a></div><div class='hunk'>@@ -84,9 +84,10 @@ mei_pxp_send_message(struct device *dev, const void *message, size_t size, unsig</div><div class='ctx'> 				byte = ret;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='add'>+		return byte;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return byte;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/misc/mei/vsc-fw-loader.c b/drivers/misc/mei/vsc-fw-loader.c<br/>new file mode 100644<br/>index 000000000000..ffa4ccd96a10<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/vsc-fw-loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-fw-loader.c</a></div><div class='hunk'>@@ -0,0 +1,770 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Intel Corporation.</div><div class='add'>+ * Intel Visual Sensing Controller Transport Layer Linux driver</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/string_helpers.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm-generic/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include "vsc-tp.h"</div><div class='add'>+</div><div class='add'>+#define VSC_MAGIC_NUM			0x49505343 /* IPSC */</div><div class='add'>+#define VSC_MAGIC_FW			0x49574653 /* IWFS */</div><div class='add'>+#define VSC_MAGIC_FILE			0x46564353 /* FVCS */</div><div class='add'>+</div><div class='add'>+#define VSC_ADDR_BASE			0xE0030000</div><div class='add'>+#define VSC_EFUSE_ADDR			(VSC_ADDR_BASE + 0x038)</div><div class='add'>+#define VSC_STRAP_ADDR			(VSC_ADDR_BASE + 0x100)</div><div class='add'>+</div><div class='add'>+#define VSC_MAINSTEPPING_VERSION_MASK	GENMASK(7, 4)</div><div class='add'>+#define VSC_MAINSTEPPING_VERSION_A	0</div><div class='add'>+</div><div class='add'>+#define VSC_SUBSTEPPING_VERSION_MASK	GENMASK(3, 0)</div><div class='add'>+#define VSC_SUBSTEPPING_VERSION_0	0</div><div class='add'>+#define VSC_SUBSTEPPING_VERSION_1	2</div><div class='add'>+</div><div class='add'>+#define VSC_BOOT_IMG_OPTION_MASK	GENMASK(15, 0)</div><div class='add'>+</div><div class='add'>+#define VSC_SKU_CFG_LOCATION		0x5001A000</div><div class='add'>+#define VSC_SKU_MAX_SIZE		4100u</div><div class='add'>+</div><div class='add'>+#define VSC_ACE_IMG_CNT			2</div><div class='add'>+#define VSC_CSI_IMG_CNT			4</div><div class='add'>+#define VSC_IMG_CNT_MAX			6</div><div class='add'>+</div><div class='add'>+#define VSC_ROM_PKG_SIZE		256u</div><div class='add'>+#define VSC_FW_PKG_SIZE			512u</div><div class='add'>+</div><div class='add'>+#define VSC_IMAGE_DIR			"intel/vsc/"</div><div class='add'>+</div><div class='add'>+#define VSC_CSI_IMAGE_NAME		VSC_IMAGE_DIR "ivsc_fw.bin"</div><div class='add'>+#define VSC_ACE_IMAGE_NAME_FMT		VSC_IMAGE_DIR "ivsc_pkg_%s_0.bin"</div><div class='add'>+#define VSC_CFG_IMAGE_NAME_FMT		VSC_IMAGE_DIR "ivsc_skucfg_%s_0_1.bin"</div><div class='add'>+</div><div class='add'>+#define VSC_IMAGE_PATH_MAX_LEN		64</div><div class='add'>+</div><div class='add'>+#define VSC_SENSOR_NAME_MAX_LEN		16</div><div class='add'>+</div><div class='add'>+/* command id */</div><div class='add'>+enum {</div><div class='add'>+	VSC_CMD_QUERY = 0,</div><div class='add'>+	VSC_CMD_DL_SET = 1,</div><div class='add'>+	VSC_CMD_DL_START = 2,</div><div class='add'>+	VSC_CMD_DL_CONT = 3,</div><div class='add'>+	VSC_CMD_DUMP_MEM = 4,</div><div class='add'>+	VSC_CMD_GET_CONT = 8,</div><div class='add'>+	VSC_CMD_CAM_BOOT = 10,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* command ack token */</div><div class='add'>+enum {</div><div class='add'>+	VSC_TOKEN_BOOTLOADER_REQ = 1,</div><div class='add'>+	VSC_TOKEN_DUMP_RESP = 4,</div><div class='add'>+	VSC_TOKEN_ERROR = 7,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* image type */</div><div class='add'>+enum {</div><div class='add'>+	VSC_IMG_BOOTLOADER_TYPE = 1,</div><div class='add'>+	VSC_IMG_CSI_EM7D_TYPE,</div><div class='add'>+	VSC_IMG_CSI_SEM_TYPE,</div><div class='add'>+	VSC_IMG_CSI_RUNTIME_TYPE,</div><div class='add'>+	VSC_IMG_ACE_VISION_TYPE,</div><div class='add'>+	VSC_IMG_ACE_CFG_TYPE,</div><div class='add'>+	VSC_IMG_SKU_CFG_TYPE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* image fragments */</div><div class='add'>+enum {</div><div class='add'>+	VSC_IMG_BOOTLOADER_FRAG,</div><div class='add'>+	VSC_IMG_CSI_SEM_FRAG,</div><div class='add'>+	VSC_IMG_CSI_RUNTIME_FRAG,</div><div class='add'>+	VSC_IMG_ACE_VISION_FRAG,</div><div class='add'>+	VSC_IMG_ACE_CFG_FRAG,</div><div class='add'>+	VSC_IMG_CSI_EM7D_FRAG,</div><div class='add'>+	VSC_IMG_SKU_CFG_FRAG,</div><div class='add'>+	VSC_IMG_FRAG_MAX</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_rom_cmd {</div><div class='add'>+	__le32 magic;</div><div class='add'>+	__u8 cmd_id;</div><div class='add'>+	union {</div><div class='add'>+		/* download start */</div><div class='add'>+		struct {</div><div class='add'>+			__u8 img_type;</div><div class='add'>+			__le16 option;</div><div class='add'>+			__le32 img_len;</div><div class='add'>+			__le32 img_loc;</div><div class='add'>+			__le32 crc;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__u8, res);</div><div class='add'>+		} __packed dl_start;</div><div class='add'>+		/* download set */</div><div class='add'>+		struct {</div><div class='add'>+			__u8 option;</div><div class='add'>+			__le16 img_cnt;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__le32, payload);</div><div class='add'>+		} __packed dl_set;</div><div class='add'>+		/* download continue */</div><div class='add'>+		struct {</div><div class='add'>+			__u8 end_flag;</div><div class='add'>+			__le16 len;</div><div class='add'>+			/* 8 is the offset of payload */</div><div class='add'>+			__u8 payload[VSC_ROM_PKG_SIZE - 8];</div><div class='add'>+		} __packed dl_cont;</div><div class='add'>+		/* dump memory */</div><div class='add'>+		struct {</div><div class='add'>+			__u8 res;</div><div class='add'>+			__le16 len;</div><div class='add'>+			__le32 addr;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__u8, payload);</div><div class='add'>+		} __packed dump_mem;</div><div class='add'>+		/* 5 is the offset of padding */</div><div class='add'>+		__u8 padding[VSC_ROM_PKG_SIZE - 5];</div><div class='add'>+	} data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_rom_cmd_ack {</div><div class='add'>+	__le32 magic;</div><div class='add'>+	__u8 token;</div><div class='add'>+	__u8 type;</div><div class='add'>+	__u8 res[2];</div><div class='add'>+	__u8 payload[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_fw_cmd {</div><div class='add'>+	__le32 magic;</div><div class='add'>+	__u8 cmd_id;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			__le16 option;</div><div class='add'>+			__u8 img_type;</div><div class='add'>+			__le32 img_len;</div><div class='add'>+			__le32 img_loc;</div><div class='add'>+			__le32 crc;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__u8, res);</div><div class='add'>+		} __packed dl_start;</div><div class='add'>+		struct {</div><div class='add'>+			__le16 option;</div><div class='add'>+			__u8 img_cnt;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__le32, payload);</div><div class='add'>+		} __packed dl_set;</div><div class='add'>+		struct {</div><div class='add'>+			__le32 addr;</div><div class='add'>+			__u8 len;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__u8, payload);</div><div class='add'>+		} __packed dump_mem;</div><div class='add'>+		struct {</div><div class='add'>+			__u8 resv[3];</div><div class='add'>+			__le32 crc;</div><div class='add'>+			DECLARE_FLEX_ARRAY(__u8, payload);</div><div class='add'>+		} __packed boot;</div><div class='add'>+		/* 5 is the offset of padding */</div><div class='add'>+		__u8 padding[VSC_FW_PKG_SIZE - 5];</div><div class='add'>+	} data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_img {</div><div class='add'>+	__le32 magic;</div><div class='add'>+	__le32 option;</div><div class='add'>+	__le32 image_count;</div><div class='add'>+	__le32 image_location[VSC_IMG_CNT_MAX];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_fw_sign {</div><div class='add'>+	__le32 magic;</div><div class='add'>+	__le32 image_size;</div><div class='add'>+	__u8 image[];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_image_code_data {</div><div class='add'>+	/* fragment index */</div><div class='add'>+	u8 frag_index;</div><div class='add'>+	/* image type */</div><div class='add'>+	u8 image_type;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_img_frag {</div><div class='add'>+	u8 type;</div><div class='add'>+	u32 location;</div><div class='add'>+	const u8 *data;</div><div class='add'>+	u32 size;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * struct vsc_fw_loader - represent vsc firmware loader</div><div class='add'>+ * @dev: device used to request fimware</div><div class='add'>+ * @tp: transport layer used with the firmware loader</div><div class='add'>+ * @csi: CSI image</div><div class='add'>+ * @ace: ACE image</div><div class='add'>+ * @cfg: config image</div><div class='add'>+ * @tx_buf: tx buffer</div><div class='add'>+ * @rx_buf: rx buffer</div><div class='add'>+ * @option: command option</div><div class='add'>+ * @count: total image count</div><div class='add'>+ * @sensor_name: camera sensor name</div><div class='add'>+ * @frags: image fragments</div><div class='add'>+ */</div><div class='add'>+struct vsc_fw_loader {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct vsc_tp *tp;</div><div class='add'>+</div><div class='add'>+	const struct firmware *csi;</div><div class='add'>+	const struct firmware *ace;</div><div class='add'>+	const struct firmware *cfg;</div><div class='add'>+</div><div class='add'>+	void *tx_buf;</div><div class='add'>+	void *rx_buf;</div><div class='add'>+</div><div class='add'>+	u16 option;</div><div class='add'>+	u16 count;</div><div class='add'>+</div><div class='add'>+	char sensor_name[VSC_SENSOR_NAME_MAX_LEN];</div><div class='add'>+</div><div class='add'>+	struct vsc_img_frag frags[VSC_IMG_FRAG_MAX];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline u32 vsc_sum_crc(void *data, size_t size)</div><div class='add'>+{</div><div class='add'>+	u32 crc = 0;</div><div class='add'>+	size_t i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; size; i++)</div><div class='add'>+		crc += *((u8 *)data + i);</div><div class='add'>+</div><div class='add'>+	return crc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* get sensor name to construct image name */</div><div class='add'>+static int vsc_get_sensor_name(struct vsc_fw_loader *fw_loader,</div><div class='add'>+			       struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER };</div><div class='add'>+	union acpi_object obj = {</div><div class='add'>+		.type = ACPI_TYPE_INTEGER,</div><div class='add'>+		.integer.value = 1,</div><div class='add'>+	};</div><div class='add'>+	struct acpi_object_list arg_list = {</div><div class='add'>+		.count = 1,</div><div class='add'>+		.pointer = &amp;obj,</div><div class='add'>+	};</div><div class='add'>+	union acpi_object *ret_obj;</div><div class='add'>+	acpi_handle handle;</div><div class='add'>+	acpi_status status;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	handle = ACPI_HANDLE(dev);</div><div class='add'>+	if (!handle)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	status = acpi_evaluate_object(handle, "SID", &amp;arg_list, &amp;buffer);</div><div class='add'>+	if (ACPI_FAILURE(status)) {</div><div class='add'>+		dev_err(dev, "can't evaluate SID method: %d\n", status);</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret_obj = buffer.pointer;</div><div class='add'>+	if (!ret_obj) {</div><div class='add'>+		dev_err(dev, "can't locate ACPI buffer\n");</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ret_obj-&gt;type != ACPI_TYPE_STRING) {</div><div class='add'>+		dev_err(dev, "found non-string entry\n");</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto out_free_buff;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* string length excludes trailing NUL */</div><div class='add'>+	if (ret_obj-&gt;string.length &gt;= sizeof(fw_loader-&gt;sensor_name)) {</div><div class='add'>+		dev_err(dev, "sensor name buffer too small\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto out_free_buff;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	memcpy(fw_loader-&gt;sensor_name, ret_obj-&gt;string.pointer,</div><div class='add'>+	       ret_obj-&gt;string.length);</div><div class='add'>+</div><div class='add'>+	string_lower(fw_loader-&gt;sensor_name, fw_loader-&gt;sensor_name);</div><div class='add'>+</div><div class='add'>+out_free_buff:</div><div class='add'>+	ACPI_FREE(buffer.pointer);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_identify_silicon(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	struct vsc_rom_cmd_ack *ack = fw_loader-&gt;rx_buf;</div><div class='add'>+	struct vsc_rom_cmd *cmd = fw_loader-&gt;tx_buf;</div><div class='add'>+	u8 version, sub_version;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* identify stepping information */</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_DUMP_MEM;</div><div class='add'>+	cmd-&gt;data.dump_mem.addr = cpu_to_le32(VSC_EFUSE_ADDR);</div><div class='add'>+	cmd-&gt;data.dump_mem.len = cpu_to_le16(sizeof(__le32));</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, ack, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (ack-&gt;token == VSC_TOKEN_ERROR)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_GET_CONT;</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, ack, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (ack-&gt;token != VSC_TOKEN_DUMP_RESP)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	version = FIELD_GET(VSC_MAINSTEPPING_VERSION_MASK, ack-&gt;payload[0]);</div><div class='add'>+	sub_version = FIELD_GET(VSC_SUBSTEPPING_VERSION_MASK, ack-&gt;payload[0]);</div><div class='add'>+</div><div class='add'>+	if (version != VSC_MAINSTEPPING_VERSION_A)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (sub_version != VSC_SUBSTEPPING_VERSION_0 &amp;&amp;</div><div class='add'>+	    sub_version != VSC_SUBSTEPPING_VERSION_1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	dev_info(fw_loader-&gt;dev, "silicon stepping version is %u:%u\n",</div><div class='add'>+		 version, sub_version);</div><div class='add'>+</div><div class='add'>+	/* identify strap information */</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_DUMP_MEM;</div><div class='add'>+	cmd-&gt;data.dump_mem.addr = cpu_to_le32(VSC_STRAP_ADDR);</div><div class='add'>+	cmd-&gt;data.dump_mem.len = cpu_to_le16(sizeof(__le32));</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, ack, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (ack-&gt;token == VSC_TOKEN_ERROR)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_GET_CONT;</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, ack, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (ack-&gt;token != VSC_TOKEN_DUMP_RESP)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_identify_csi_image(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	const struct firmware *image;</div><div class='add'>+	struct vsc_fw_sign *sign;</div><div class='add'>+	struct vsc_img *img;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = request_firmware(&amp;image, VSC_CSI_IMAGE_NAME, fw_loader-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	img = (struct vsc_img *)image-&gt;data;</div><div class='add'>+	if (!img) {</div><div class='add'>+		ret = -ENOENT;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(img-&gt;magic) != VSC_MAGIC_FILE) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(img-&gt;image_count) != VSC_CSI_IMG_CNT) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+	fw_loader-&gt;count += le32_to_cpu(img-&gt;image_count) - 1;</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;option =</div><div class='add'>+		FIELD_GET(VSC_BOOT_IMG_OPTION_MASK, le32_to_cpu(img-&gt;option));</div><div class='add'>+</div><div class='add'>+	sign = (struct vsc_fw_sign *)</div><div class='add'>+		(img-&gt;image_location + le32_to_cpu(img-&gt;image_count));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; VSC_CSI_IMG_CNT; i++) {</div><div class='add'>+		/* mapping from CSI image index to image code data */</div><div class='add'>+		static const struct vsc_image_code_data csi_image_map[] = {</div><div class='add'>+			{ VSC_IMG_BOOTLOADER_FRAG, VSC_IMG_BOOTLOADER_TYPE },</div><div class='add'>+			{ VSC_IMG_CSI_SEM_FRAG, VSC_IMG_CSI_SEM_TYPE },</div><div class='add'>+			{ VSC_IMG_CSI_RUNTIME_FRAG, VSC_IMG_CSI_RUNTIME_TYPE },</div><div class='add'>+			{ VSC_IMG_CSI_EM7D_FRAG, VSC_IMG_CSI_EM7D_TYPE },</div><div class='add'>+		};</div><div class='add'>+		struct vsc_img_frag *frag;</div><div class='add'>+</div><div class='add'>+		if ((u8 *)sign + sizeof(*sign) &gt; image-&gt;data + image-&gt;size) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err_release_image;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (le32_to_cpu(sign-&gt;magic) != VSC_MAGIC_FW) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err_release_image;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!le32_to_cpu(img-&gt;image_location[i])) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err_release_image;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		frag = &amp;fw_loader-&gt;frags[csi_image_map[i].frag_index];</div><div class='add'>+</div><div class='add'>+		frag-&gt;data = sign-&gt;image;</div><div class='add'>+		frag-&gt;size = le32_to_cpu(sign-&gt;image_size);</div><div class='add'>+		frag-&gt;location = le32_to_cpu(img-&gt;image_location[i]);</div><div class='add'>+		frag-&gt;type = csi_image_map[i].image_type;</div><div class='add'>+</div><div class='add'>+		sign = (struct vsc_fw_sign *)</div><div class='add'>+			(sign-&gt;image + le32_to_cpu(sign-&gt;image_size));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;csi = image;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_release_image:</div><div class='add'>+	release_firmware(image);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_identify_ace_image(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	char path[VSC_IMAGE_PATH_MAX_LEN];</div><div class='add'>+	const struct firmware *image;</div><div class='add'>+	struct vsc_fw_sign *sign;</div><div class='add'>+	struct vsc_img *img;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	snprintf(path, sizeof(path), VSC_ACE_IMAGE_NAME_FMT,</div><div class='add'>+		 fw_loader-&gt;sensor_name);</div><div class='add'>+</div><div class='add'>+	ret = request_firmware(&amp;image, path, fw_loader-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	img = (struct vsc_img *)image-&gt;data;</div><div class='add'>+	if (!img) {</div><div class='add'>+		ret = -ENOENT;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(img-&gt;magic) != VSC_MAGIC_FILE) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (le32_to_cpu(img-&gt;image_count) != VSC_ACE_IMG_CNT) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+	fw_loader-&gt;count += le32_to_cpu(img-&gt;image_count);</div><div class='add'>+</div><div class='add'>+	sign = (struct vsc_fw_sign *)</div><div class='add'>+		(img-&gt;image_location + le32_to_cpu(img-&gt;image_count));</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; VSC_ACE_IMG_CNT; i++) {</div><div class='add'>+		/* mapping from ACE image index to image code data */</div><div class='add'>+		static const struct vsc_image_code_data ace_image_map[] = {</div><div class='add'>+			{ VSC_IMG_ACE_VISION_FRAG, VSC_IMG_ACE_VISION_TYPE },</div><div class='add'>+			{ VSC_IMG_ACE_CFG_FRAG, VSC_IMG_ACE_CFG_TYPE },</div><div class='add'>+		};</div><div class='add'>+		struct vsc_img_frag *frag, *last_frag;</div><div class='add'>+		u8 frag_index;</div><div class='add'>+</div><div class='add'>+		if ((u8 *)sign + sizeof(*sign) &gt; image-&gt;data + image-&gt;size) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err_release_image;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (le32_to_cpu(sign-&gt;magic) != VSC_MAGIC_FW) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto err_release_image;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		frag_index = ace_image_map[i].frag_index;</div><div class='add'>+		frag = &amp;fw_loader-&gt;frags[frag_index];</div><div class='add'>+</div><div class='add'>+		frag-&gt;data = sign-&gt;image;</div><div class='add'>+		frag-&gt;size = le32_to_cpu(sign-&gt;image_size);</div><div class='add'>+		frag-&gt;location = le32_to_cpu(img-&gt;image_location[i]);</div><div class='add'>+		frag-&gt;type = ace_image_map[i].image_type;</div><div class='add'>+</div><div class='add'>+		if (!frag-&gt;location) {</div><div class='add'>+			last_frag = &amp;fw_loader-&gt;frags[frag_index - 1];</div><div class='add'>+			frag-&gt;location =</div><div class='add'>+				ALIGN(last_frag-&gt;location + last_frag-&gt;size, SZ_4K);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		sign = (struct vsc_fw_sign *)</div><div class='add'>+			(sign-&gt;image + le32_to_cpu(sign-&gt;image_size));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;ace = image;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_release_image:</div><div class='add'>+	release_firmware(image);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_identify_cfg_image(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	struct vsc_img_frag *frag = &amp;fw_loader-&gt;frags[VSC_IMG_SKU_CFG_FRAG];</div><div class='add'>+	char path[VSC_IMAGE_PATH_MAX_LEN];</div><div class='add'>+	const struct firmware *image;</div><div class='add'>+	u32 size;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	snprintf(path, sizeof(path), VSC_CFG_IMAGE_NAME_FMT,</div><div class='add'>+		 fw_loader-&gt;sensor_name);</div><div class='add'>+</div><div class='add'>+	ret = request_firmware(&amp;image, path, fw_loader-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* identify image size */</div><div class='add'>+	if (image-&gt;size &lt;= sizeof(u32) || image-&gt;size &gt; VSC_SKU_MAX_SIZE) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	size = le32_to_cpu(*((__le32 *)image-&gt;data)) + sizeof(u32);</div><div class='add'>+	if (image-&gt;size != size) {</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto err_release_image;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	frag-&gt;data = image-&gt;data;</div><div class='add'>+	frag-&gt;size = image-&gt;size;</div><div class='add'>+	frag-&gt;type = VSC_IMG_SKU_CFG_TYPE;</div><div class='add'>+	frag-&gt;location = VSC_SKU_CFG_LOCATION;</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;cfg = image;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_release_image:</div><div class='add'>+	release_firmware(image);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_download_bootloader(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	struct vsc_img_frag *frag = &amp;fw_loader-&gt;frags[VSC_IMG_BOOTLOADER_FRAG];</div><div class='add'>+	struct vsc_rom_cmd_ack *ack = fw_loader-&gt;rx_buf;</div><div class='add'>+	struct vsc_rom_cmd *cmd = fw_loader-&gt;tx_buf;</div><div class='add'>+	u32 len, c_len;</div><div class='add'>+	size_t remain;</div><div class='add'>+	const u8 *p;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_QUERY;</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, ack, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+	if (ack-&gt;token != VSC_TOKEN_DUMP_RESP &amp;&amp;</div><div class='add'>+	    ack-&gt;token != VSC_TOKEN_BOOTLOADER_REQ)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_DL_START;</div><div class='add'>+	cmd-&gt;data.dl_start.option = cpu_to_le16(fw_loader-&gt;option);</div><div class='add'>+	cmd-&gt;data.dl_start.img_type = frag-&gt;type;</div><div class='add'>+	cmd-&gt;data.dl_start.img_len = cpu_to_le32(frag-&gt;size);</div><div class='add'>+	cmd-&gt;data.dl_start.img_loc = cpu_to_le32(frag-&gt;location);</div><div class='add'>+</div><div class='add'>+	c_len = offsetof(struct vsc_rom_cmd, data.dl_start.crc);</div><div class='add'>+	cmd-&gt;data.dl_start.crc = cpu_to_le32(vsc_sum_crc(cmd, c_len));</div><div class='add'>+</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, NULL, VSC_ROM_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	p = frag-&gt;data;</div><div class='add'>+	remain = frag-&gt;size;</div><div class='add'>+</div><div class='add'>+	/* download image data */</div><div class='add'>+	while (remain &gt; 0) {</div><div class='add'>+		len = min(remain, sizeof(cmd-&gt;data.dl_cont.payload));</div><div class='add'>+</div><div class='add'>+		cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+		cmd-&gt;cmd_id = VSC_CMD_DL_CONT;</div><div class='add'>+		cmd-&gt;data.dl_cont.len = cpu_to_le16(len);</div><div class='add'>+		cmd-&gt;data.dl_cont.end_flag = remain == len;</div><div class='add'>+		memcpy(cmd-&gt;data.dl_cont.payload, p, len);</div><div class='add'>+</div><div class='add'>+		ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, NULL, VSC_ROM_PKG_SIZE);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		p += len;</div><div class='add'>+		remain -= len;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_download_firmware(struct vsc_fw_loader *fw_loader)</div><div class='add'>+{</div><div class='add'>+	struct vsc_fw_cmd *cmd = fw_loader-&gt;tx_buf;</div><div class='add'>+	unsigned int i, index = 0;</div><div class='add'>+	u32 c_len;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_DL_SET;</div><div class='add'>+	cmd-&gt;data.dl_set.img_cnt = cpu_to_le16(fw_loader-&gt;count);</div><div class='add'>+	put_unaligned_le16(fw_loader-&gt;option, &amp;cmd-&gt;data.dl_set.option);</div><div class='add'>+</div><div class='add'>+	for (i = VSC_IMG_CSI_SEM_FRAG; i &lt;= VSC_IMG_CSI_EM7D_FRAG; i++) {</div><div class='add'>+		struct vsc_img_frag *frag = &amp;fw_loader-&gt;frags[i];</div><div class='add'>+</div><div class='add'>+		cmd-&gt;data.dl_set.payload[index++] = cpu_to_le32(frag-&gt;location);</div><div class='add'>+		cmd-&gt;data.dl_set.payload[index++] = cpu_to_le32(frag-&gt;size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	c_len = offsetof(struct vsc_fw_cmd, data.dl_set.payload[index]);</div><div class='add'>+	cmd-&gt;data.dl_set.payload[index] = cpu_to_le32(vsc_sum_crc(cmd, c_len));</div><div class='add'>+</div><div class='add'>+	ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, NULL, VSC_FW_PKG_SIZE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	for (i = VSC_IMG_CSI_SEM_FRAG; i &lt; VSC_IMG_FRAG_MAX; i++) {</div><div class='add'>+		struct vsc_img_frag *frag = &amp;fw_loader-&gt;frags[i];</div><div class='add'>+		const u8 *p;</div><div class='add'>+		u32 remain;</div><div class='add'>+</div><div class='add'>+		cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+		cmd-&gt;cmd_id = VSC_CMD_DL_START;</div><div class='add'>+		cmd-&gt;data.dl_start.img_type = frag-&gt;type;</div><div class='add'>+		cmd-&gt;data.dl_start.img_len = cpu_to_le32(frag-&gt;size);</div><div class='add'>+		cmd-&gt;data.dl_start.img_loc = cpu_to_le32(frag-&gt;location);</div><div class='add'>+		put_unaligned_le16(fw_loader-&gt;option, &amp;cmd-&gt;data.dl_start.option);</div><div class='add'>+</div><div class='add'>+		c_len = offsetof(struct vsc_fw_cmd, data.dl_start.crc);</div><div class='add'>+		cmd-&gt;data.dl_start.crc = cpu_to_le32(vsc_sum_crc(cmd, c_len));</div><div class='add'>+</div><div class='add'>+		ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, NULL, VSC_FW_PKG_SIZE);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		p = frag-&gt;data;</div><div class='add'>+		remain = frag-&gt;size;</div><div class='add'>+</div><div class='add'>+		/* download image data */</div><div class='add'>+		while (remain &gt; 0) {</div><div class='add'>+			u32 len = min(remain, VSC_FW_PKG_SIZE);</div><div class='add'>+</div><div class='add'>+			memcpy(fw_loader-&gt;tx_buf, p, len);</div><div class='add'>+			memset(fw_loader-&gt;tx_buf + len, 0, VSC_FW_PKG_SIZE - len);</div><div class='add'>+</div><div class='add'>+			ret = vsc_tp_rom_xfer(fw_loader-&gt;tp, fw_loader-&gt;tx_buf,</div><div class='add'>+					      NULL, VSC_FW_PKG_SIZE);</div><div class='add'>+			if (ret)</div><div class='add'>+				break;</div><div class='add'>+</div><div class='add'>+			p += len;</div><div class='add'>+			remain -= len;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cmd-&gt;magic = cpu_to_le32(VSC_MAGIC_NUM);</div><div class='add'>+	cmd-&gt;cmd_id = VSC_CMD_CAM_BOOT;</div><div class='add'>+</div><div class='add'>+	c_len = offsetof(struct vsc_fw_cmd, data.dl_start.crc);</div><div class='add'>+	cmd-&gt;data.boot.crc = cpu_to_le32(vsc_sum_crc(cmd, c_len));</div><div class='add'>+</div><div class='add'>+	return vsc_tp_rom_xfer(fw_loader-&gt;tp, cmd, NULL, VSC_FW_PKG_SIZE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_init - init vsc_tp</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ * @dev: device node for mei vsc device</div><div class='add'>+ * Return: 0 in case of success, negative value in case of error</div><div class='add'>+ */</div><div class='add'>+int vsc_tp_init(struct vsc_tp *tp, struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct vsc_fw_loader *fw_loader __free(kfree) = NULL;</div><div class='add'>+	void *tx_buf __free(kfree) = NULL;</div><div class='add'>+	void *rx_buf __free(kfree) = NULL;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	fw_loader = kzalloc(sizeof(*fw_loader), GFP_KERNEL);</div><div class='add'>+	if (!fw_loader)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	tx_buf = kzalloc(VSC_FW_PKG_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!tx_buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	rx_buf = kzalloc(VSC_FW_PKG_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!rx_buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;tx_buf = tx_buf;</div><div class='add'>+	fw_loader-&gt;rx_buf = rx_buf;</div><div class='add'>+</div><div class='add'>+	fw_loader-&gt;tp = tp;</div><div class='add'>+	fw_loader-&gt;dev = dev;</div><div class='add'>+</div><div class='add'>+	ret = vsc_get_sensor_name(fw_loader, dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = vsc_identify_silicon(fw_loader);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = vsc_identify_csi_image(fw_loader);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = vsc_identify_ace_image(fw_loader);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_release_csi;</div><div class='add'>+</div><div class='add'>+	ret = vsc_identify_cfg_image(fw_loader);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_release_ace;</div><div class='add'>+</div><div class='add'>+	ret = vsc_download_bootloader(fw_loader);</div><div class='add'>+	if (!ret)</div><div class='add'>+		ret = vsc_download_firmware(fw_loader);</div><div class='add'>+</div><div class='add'>+	release_firmware(fw_loader-&gt;cfg);</div><div class='add'>+</div><div class='add'>+err_release_ace:</div><div class='add'>+	release_firmware(fw_loader-&gt;ace);</div><div class='add'>+</div><div class='add'>+err_release_csi:</div><div class='add'>+	release_firmware(fw_loader-&gt;csi);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_init, VSC_TP);</div><div class='head'>diff --git a/drivers/misc/mei/vsc-tp.c b/drivers/misc/mei/vsc-tp.c<br/>new file mode 100644<br/>index 000000000000..6f4a4be6ccb5<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/vsc-tp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-tp.c</a></div><div class='hunk'>@@ -0,0 +1,555 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Intel Corporation.</div><div class='add'>+ * Intel Visual Sensing Controller Transport Layer Linux driver</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/cleanup.h&gt;</div><div class='add'>+#include &lt;linux/crc32.h&gt;</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/irq.h&gt;</div><div class='add'>+#include &lt;linux/irqreturn.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/spi/spi.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#include "vsc-tp.h"</div><div class='add'>+</div><div class='add'>+#define VSC_TP_RESET_PIN_TOGGLE_INTERVAL_MS	20</div><div class='add'>+#define VSC_TP_ROM_BOOTUP_DELAY_MS		10</div><div class='add'>+#define VSC_TP_ROM_XFER_POLL_TIMEOUT_US		(500 * USEC_PER_MSEC)</div><div class='add'>+#define VSC_TP_ROM_XFER_POLL_DELAY_US		(20 * USEC_PER_MSEC)</div><div class='add'>+#define VSC_TP_WAIT_FW_ASSERTED_TIMEOUT		(2 * HZ)</div><div class='add'>+#define VSC_TP_MAX_XFER_COUNT			5</div><div class='add'>+</div><div class='add'>+#define VSC_TP_PACKET_SYNC			0x31</div><div class='add'>+#define VSC_TP_CRC_SIZE				sizeof(u32)</div><div class='add'>+#define VSC_TP_MAX_MSG_SIZE			2048</div><div class='add'>+/* SPI xfer timeout size */</div><div class='add'>+#define VSC_TP_XFER_TIMEOUT_BYTES		700</div><div class='add'>+#define VSC_TP_PACKET_PADDING_SIZE		1</div><div class='add'>+#define VSC_TP_PACKET_SIZE(pkt) \</div><div class='add'>+	(sizeof(struct vsc_tp_packet) + le16_to_cpu((pkt)-&gt;len) + VSC_TP_CRC_SIZE)</div><div class='add'>+#define VSC_TP_MAX_PACKET_SIZE \</div><div class='add'>+	(sizeof(struct vsc_tp_packet) + VSC_TP_MAX_MSG_SIZE + VSC_TP_CRC_SIZE)</div><div class='add'>+#define VSC_TP_MAX_XFER_SIZE \</div><div class='add'>+	(VSC_TP_MAX_PACKET_SIZE + VSC_TP_XFER_TIMEOUT_BYTES)</div><div class='add'>+#define VSC_TP_NEXT_XFER_LEN(len, offset) \</div><div class='add'>+	(len + sizeof(struct vsc_tp_packet) + VSC_TP_CRC_SIZE - offset + VSC_TP_PACKET_PADDING_SIZE)</div><div class='add'>+</div><div class='add'>+struct vsc_tp_packet {</div><div class='add'>+	__u8 sync;</div><div class='add'>+	__u8 cmd;</div><div class='add'>+	__le16 len;</div><div class='add'>+	__le32 seq;</div><div class='add'>+	__u8 buf[] __counted_by(len);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct vsc_tp {</div><div class='add'>+	/* do the actual data transfer */</div><div class='add'>+	struct spi_device *spi;</div><div class='add'>+</div><div class='add'>+	/* bind with mei framework */</div><div class='add'>+	struct platform_device *pdev;</div><div class='add'>+</div><div class='add'>+	struct gpio_desc *wakeuphost;</div><div class='add'>+	struct gpio_desc *resetfw;</div><div class='add'>+	struct gpio_desc *wakeupfw;</div><div class='add'>+</div><div class='add'>+	/* command sequence number */</div><div class='add'>+	u32 seq;</div><div class='add'>+</div><div class='add'>+	/* command buffer */</div><div class='add'>+	void *tx_buf;</div><div class='add'>+	void *rx_buf;</div><div class='add'>+</div><div class='add'>+	atomic_t assert_cnt;</div><div class='add'>+	wait_queue_head_t xfer_wait;</div><div class='add'>+</div><div class='add'>+	vsc_tp_event_cb_t event_notify;</div><div class='add'>+	void *event_notify_context;</div><div class='add'>+</div><div class='add'>+	/* used to protect command download */</div><div class='add'>+	struct mutex mutex;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* GPIO resources */</div><div class='add'>+static const struct acpi_gpio_params wakeuphost_gpio = { 0, 0, false };</div><div class='add'>+static const struct acpi_gpio_params wakeuphostint_gpio = { 1, 0, false };</div><div class='add'>+static const struct acpi_gpio_params resetfw_gpio = { 2, 0, false };</div><div class='add'>+static const struct acpi_gpio_params wakeupfw = { 3, 0, false };</div><div class='add'>+</div><div class='add'>+static const struct acpi_gpio_mapping vsc_tp_acpi_gpios[] = {</div><div class='add'>+	{ "wakeuphost-gpios", &amp;wakeuphost_gpio, 1 },</div><div class='add'>+	{ "wakeuphostint-gpios", &amp;wakeuphostint_gpio, 1 },</div><div class='add'>+	{ "resetfw-gpios", &amp;resetfw_gpio, 1 },</div><div class='add'>+	{ "wakeupfw-gpios", &amp;wakeupfw, 1 },</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* wakeup firmware and wait for response */</div><div class='add'>+static int vsc_tp_wakeup_request(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(tp-&gt;wakeupfw, 0);</div><div class='add'>+</div><div class='add'>+	ret = wait_event_timeout(tp-&gt;xfer_wait,</div><div class='add'>+				 atomic_read(&amp;tp-&gt;assert_cnt) &amp;&amp;</div><div class='add'>+				 gpiod_get_value_cansleep(tp-&gt;wakeuphost),</div><div class='add'>+				 VSC_TP_WAIT_FW_ASSERTED_TIMEOUT);</div><div class='add'>+	if (!ret)</div><div class='add'>+		return -ETIMEDOUT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vsc_tp_wakeup_release(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	atomic_dec_if_positive(&amp;tp-&gt;assert_cnt);</div><div class='add'>+</div><div class='add'>+	gpiod_set_value_cansleep(tp-&gt;wakeupfw, 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_tp_dev_xfer(struct vsc_tp *tp, void *obuf, void *ibuf, size_t len)</div><div class='add'>+{</div><div class='add'>+	struct spi_message msg = { 0 };</div><div class='add'>+	struct spi_transfer xfer = {</div><div class='add'>+		.tx_buf = obuf,</div><div class='add'>+		.rx_buf = ibuf,</div><div class='add'>+		.len = len,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	spi_message_init_with_transfers(&amp;msg, &amp;xfer, 1);</div><div class='add'>+</div><div class='add'>+	return spi_sync_locked(tp-&gt;spi, &amp;msg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_tp_xfer_helper(struct vsc_tp *tp, struct vsc_tp_packet *pkt,</div><div class='add'>+			      void *ibuf, u16 ilen)</div><div class='add'>+{</div><div class='add'>+	int ret, offset = 0, cpy_len, src_len, dst_len = sizeof(struct vsc_tp_packet);</div><div class='add'>+	int next_xfer_len = VSC_TP_PACKET_SIZE(pkt) + VSC_TP_XFER_TIMEOUT_BYTES;</div><div class='add'>+	u8 *src, *crc_src, *rx_buf = tp-&gt;rx_buf;</div><div class='add'>+	int count_down = VSC_TP_MAX_XFER_COUNT;</div><div class='add'>+	u32 recv_crc = 0, crc = ~0;</div><div class='add'>+	struct vsc_tp_packet ack;</div><div class='add'>+	u8 *dst = (u8 *)&amp;ack;</div><div class='add'>+	bool synced = false;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = vsc_tp_dev_xfer(tp, pkt, rx_buf, next_xfer_len);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+		memset(pkt, 0, VSC_TP_MAX_XFER_SIZE);</div><div class='add'>+</div><div class='add'>+		if (synced) {</div><div class='add'>+			src = rx_buf;</div><div class='add'>+			src_len = next_xfer_len;</div><div class='add'>+		} else {</div><div class='add'>+			src = memchr(rx_buf, VSC_TP_PACKET_SYNC, next_xfer_len);</div><div class='add'>+			if (!src)</div><div class='add'>+				continue;</div><div class='add'>+			synced = true;</div><div class='add'>+			src_len = next_xfer_len - (src - rx_buf);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* traverse received data */</div><div class='add'>+		while (src_len &gt; 0) {</div><div class='add'>+			cpy_len = min(src_len, dst_len);</div><div class='add'>+			memcpy(dst, src, cpy_len);</div><div class='add'>+			crc_src = src;</div><div class='add'>+			src += cpy_len;</div><div class='add'>+			src_len -= cpy_len;</div><div class='add'>+			dst += cpy_len;</div><div class='add'>+			dst_len -= cpy_len;</div><div class='add'>+</div><div class='add'>+			if (offset &lt; sizeof(ack)) {</div><div class='add'>+				offset += cpy_len;</div><div class='add'>+				crc = crc32(crc, crc_src, cpy_len);</div><div class='add'>+</div><div class='add'>+				if (!src_len)</div><div class='add'>+					continue;</div><div class='add'>+</div><div class='add'>+				if (le16_to_cpu(ack.len)) {</div><div class='add'>+					dst = ibuf;</div><div class='add'>+					dst_len = min(ilen, le16_to_cpu(ack.len));</div><div class='add'>+				} else {</div><div class='add'>+					dst = (u8 *)&amp;recv_crc;</div><div class='add'>+					dst_len = sizeof(recv_crc);</div><div class='add'>+				}</div><div class='add'>+			} else if (offset &lt; sizeof(ack) + le16_to_cpu(ack.len)) {</div><div class='add'>+				offset += cpy_len;</div><div class='add'>+				crc = crc32(crc, crc_src, cpy_len);</div><div class='add'>+</div><div class='add'>+				if (src_len) {</div><div class='add'>+					int remain = sizeof(ack) + le16_to_cpu(ack.len) - offset;</div><div class='add'>+</div><div class='add'>+					cpy_len = min(src_len, remain);</div><div class='add'>+					offset += cpy_len;</div><div class='add'>+					crc = crc32(crc, src, cpy_len);</div><div class='add'>+					src += cpy_len;</div><div class='add'>+					src_len -= cpy_len;</div><div class='add'>+					if (src_len) {</div><div class='add'>+						dst = (u8 *)&amp;recv_crc;</div><div class='add'>+						dst_len = sizeof(recv_crc);</div><div class='add'>+						continue;</div><div class='add'>+					}</div><div class='add'>+				}</div><div class='add'>+				next_xfer_len = VSC_TP_NEXT_XFER_LEN(le16_to_cpu(ack.len), offset);</div><div class='add'>+			} else if (offset &lt; sizeof(ack) + le16_to_cpu(ack.len) + VSC_TP_CRC_SIZE) {</div><div class='add'>+				offset += cpy_len;</div><div class='add'>+</div><div class='add'>+				if (src_len) {</div><div class='add'>+					/* terminate the traverse */</div><div class='add'>+					next_xfer_len = 0;</div><div class='add'>+					break;</div><div class='add'>+				}</div><div class='add'>+				next_xfer_len = VSC_TP_NEXT_XFER_LEN(le16_to_cpu(ack.len), offset);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	} while (next_xfer_len &gt; 0 &amp;&amp; --count_down);</div><div class='add'>+</div><div class='add'>+	if (next_xfer_len &gt; 0)</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	if (~recv_crc != crc || le32_to_cpu(ack.seq) != tp-&gt;seq) {</div><div class='add'>+		dev_err(&amp;tp-&gt;spi-&gt;dev, "recv crc or seq error\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ack.cmd == VSC_TP_CMD_ACK || ack.cmd == VSC_TP_CMD_NACK ||</div><div class='add'>+	    ack.cmd == VSC_TP_CMD_BUSY) {</div><div class='add'>+		dev_err(&amp;tp-&gt;spi-&gt;dev, "recv cmd ack error\n");</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return min(le16_to_cpu(ack.len), ilen);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_xfer - transfer data to firmware</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ * @cmd: the command to be sent to the device</div><div class='add'>+ * @obuf: the tx buffer to be sent to the device</div><div class='add'>+ * @olen: the length of tx buffer</div><div class='add'>+ * @ibuf: the rx buffer to receive from the device</div><div class='add'>+ * @ilen: the length of rx buffer</div><div class='add'>+ * Return: the length of received data in case of success,</div><div class='add'>+ *	otherwise negative value</div><div class='add'>+ */</div><div class='add'>+int vsc_tp_xfer(struct vsc_tp *tp, u8 cmd, const void *obuf, size_t olen,</div><div class='add'>+		void *ibuf, size_t ilen)</div><div class='add'>+{</div><div class='add'>+	struct vsc_tp_packet *pkt = tp-&gt;tx_buf;</div><div class='add'>+	u32 crc;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!obuf || !ibuf || olen &gt; VSC_TP_MAX_MSG_SIZE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;tp-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	pkt-&gt;sync = VSC_TP_PACKET_SYNC;</div><div class='add'>+	pkt-&gt;cmd = cmd;</div><div class='add'>+	pkt-&gt;len = cpu_to_le16(olen);</div><div class='add'>+	pkt-&gt;seq = cpu_to_le32(++tp-&gt;seq);</div><div class='add'>+	memcpy(pkt-&gt;buf, obuf, olen);</div><div class='add'>+</div><div class='add'>+	crc = ~crc32(~0, (u8 *)pkt, sizeof(pkt) + olen);</div><div class='add'>+	memcpy(pkt-&gt;buf + olen, &amp;crc, sizeof(crc));</div><div class='add'>+</div><div class='add'>+	ret = vsc_tp_wakeup_request(tp);</div><div class='add'>+	if (unlikely(ret))</div><div class='add'>+		dev_err(&amp;tp-&gt;spi-&gt;dev, "wakeup firmware failed ret: %d\n", ret);</div><div class='add'>+	else</div><div class='add'>+		ret = vsc_tp_xfer_helper(tp, pkt, ibuf, ilen);</div><div class='add'>+</div><div class='add'>+	vsc_tp_wakeup_release(tp);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_xfer, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_rom_xfer - transfer data to rom code</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ * @obuf: the data buffer to be sent to the device</div><div class='add'>+ * @ibuf: the buffer to receive data from the device</div><div class='add'>+ * @len: the length of tx buffer and rx buffer</div><div class='add'>+ * Return: 0 in case of success, negative value in case of error</div><div class='add'>+ */</div><div class='add'>+int vsc_tp_rom_xfer(struct vsc_tp *tp, const void *obuf, void *ibuf, size_t len)</div><div class='add'>+{</div><div class='add'>+	size_t words = len / sizeof(__be32);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (len % sizeof(__be32) || len &gt; VSC_TP_MAX_MSG_SIZE)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	guard(mutex)(&amp;tp-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	/* rom xfer is big endian */</div><div class='add'>+	cpu_to_be32_array(tp-&gt;tx_buf, obuf, words);</div><div class='add'>+</div><div class='add'>+	ret = read_poll_timeout(gpiod_get_value_cansleep, ret,</div><div class='add'>+				!ret, VSC_TP_ROM_XFER_POLL_DELAY_US,</div><div class='add'>+				VSC_TP_ROM_XFER_POLL_TIMEOUT_US, false,</div><div class='add'>+				tp-&gt;wakeuphost);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;tp-&gt;spi-&gt;dev, "wait rom failed ret: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = vsc_tp_dev_xfer(tp, tp-&gt;tx_buf, tp-&gt;rx_buf, len);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (ibuf)</div><div class='add'>+		cpu_to_be32_array(ibuf, tp-&gt;rx_buf, words);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_reset - reset vsc transport layer</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ */</div><div class='add'>+void vsc_tp_reset(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	disable_irq(tp-&gt;spi-&gt;irq);</div><div class='add'>+</div><div class='add'>+	/* toggle reset pin */</div><div class='add'>+	gpiod_set_value_cansleep(tp-&gt;resetfw, 0);</div><div class='add'>+	msleep(VSC_TP_RESET_PIN_TOGGLE_INTERVAL_MS);</div><div class='add'>+	gpiod_set_value_cansleep(tp-&gt;resetfw, 1);</div><div class='add'>+</div><div class='add'>+	/* wait for ROM */</div><div class='add'>+	msleep(VSC_TP_ROM_BOOTUP_DELAY_MS);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Set default host wakeup pin to non-active</div><div class='add'>+	 * to avoid unexpected host irq interrupt.</div><div class='add'>+	 */</div><div class='add'>+	gpiod_set_value_cansleep(tp-&gt;wakeupfw, 1);</div><div class='add'>+</div><div class='add'>+	atomic_set(&amp;tp-&gt;assert_cnt, 0);</div><div class='add'>+</div><div class='add'>+	enable_irq(tp-&gt;spi-&gt;irq);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_reset, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_need_read - check if device has data to sent</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ * Return: true if device has data to sent, otherwise false</div><div class='add'>+ */</div><div class='add'>+bool vsc_tp_need_read(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	if (!atomic_read(&amp;tp-&gt;assert_cnt))</div><div class='add'>+		return false;</div><div class='add'>+	if (!gpiod_get_value_cansleep(tp-&gt;wakeuphost))</div><div class='add'>+		return false;</div><div class='add'>+	if (!gpiod_get_value_cansleep(tp-&gt;wakeupfw))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_need_read, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_register_event_cb - register a callback function to receive event</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ * @event_cb: callback function</div><div class='add'>+ * @context: execution context of event callback</div><div class='add'>+ * Return: 0 in case of success, negative value in case of error</div><div class='add'>+ */</div><div class='add'>+int vsc_tp_register_event_cb(struct vsc_tp *tp, vsc_tp_event_cb_t event_cb,</div><div class='add'>+			    void *context)</div><div class='add'>+{</div><div class='add'>+	tp-&gt;event_notify = event_cb;</div><div class='add'>+	tp-&gt;event_notify_context = context;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_register_event_cb, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_intr_synchronize - synchronize vsc_tp interrupt</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ */</div><div class='add'>+void vsc_tp_intr_synchronize(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	synchronize_irq(tp-&gt;spi-&gt;irq);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_intr_synchronize, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_intr_enable - enable vsc_tp interrupt</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ */</div><div class='add'>+void vsc_tp_intr_enable(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	enable_irq(tp-&gt;spi-&gt;irq);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_intr_enable, VSC_TP);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * vsc_tp_intr_disable - disable vsc_tp interrupt</div><div class='add'>+ * @tp: vsc_tp device handle</div><div class='add'>+ */</div><div class='add'>+void vsc_tp_intr_disable(struct vsc_tp *tp)</div><div class='add'>+{</div><div class='add'>+	disable_irq(tp-&gt;spi-&gt;irq);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_NS_GPL(vsc_tp_intr_disable, VSC_TP);</div><div class='add'>+</div><div class='add'>+static irqreturn_t vsc_tp_isr(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct vsc_tp *tp = data;</div><div class='add'>+</div><div class='add'>+	atomic_inc(&amp;tp-&gt;assert_cnt);</div><div class='add'>+</div><div class='add'>+	wake_up(&amp;tp-&gt;xfer_wait);</div><div class='add'>+</div><div class='add'>+	return IRQ_WAKE_THREAD;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t vsc_tp_thread_isr(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct vsc_tp *tp = data;</div><div class='add'>+</div><div class='add'>+	if (tp-&gt;event_notify)</div><div class='add'>+		tp-&gt;event_notify(tp-&gt;event_notify_context);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_tp_match_any(struct acpi_device *adev, void *data)</div><div class='add'>+{</div><div class='add'>+	struct acpi_device **__adev = data;</div><div class='add'>+</div><div class='add'>+	*__adev = adev;</div><div class='add'>+</div><div class='add'>+	return 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int vsc_tp_probe(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	struct platform_device_info pinfo = { 0 };</div><div class='add'>+	struct device *dev = &amp;spi-&gt;dev;</div><div class='add'>+	struct platform_device *pdev;</div><div class='add'>+	struct acpi_device *adev;</div><div class='add'>+	struct vsc_tp *tp;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	tp = devm_kzalloc(dev, sizeof(*tp), GFP_KERNEL);</div><div class='add'>+	if (!tp)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	tp-&gt;tx_buf = devm_kzalloc(dev, VSC_TP_MAX_XFER_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!tp-&gt;tx_buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	tp-&gt;rx_buf = devm_kzalloc(dev, VSC_TP_MAX_XFER_SIZE, GFP_KERNEL);</div><div class='add'>+	if (!tp-&gt;rx_buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = devm_acpi_dev_add_driver_gpios(dev, vsc_tp_acpi_gpios);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	tp-&gt;wakeuphost = devm_gpiod_get(dev, "wakeuphost", GPIOD_IN);</div><div class='add'>+	if (IS_ERR(tp-&gt;wakeuphost))</div><div class='add'>+		return PTR_ERR(tp-&gt;wakeuphost);</div><div class='add'>+</div><div class='add'>+	tp-&gt;resetfw = devm_gpiod_get(dev, "resetfw", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(tp-&gt;resetfw))</div><div class='add'>+		return PTR_ERR(tp-&gt;resetfw);</div><div class='add'>+</div><div class='add'>+	tp-&gt;wakeupfw = devm_gpiod_get(dev, "wakeupfw", GPIOD_OUT_HIGH);</div><div class='add'>+	if (IS_ERR(tp-&gt;wakeupfw))</div><div class='add'>+		return PTR_ERR(tp-&gt;wakeupfw);</div><div class='add'>+</div><div class='add'>+	atomic_set(&amp;tp-&gt;assert_cnt, 0);</div><div class='add'>+	init_waitqueue_head(&amp;tp-&gt;xfer_wait);</div><div class='add'>+	tp-&gt;spi = spi;</div><div class='add'>+</div><div class='add'>+	irq_set_status_flags(spi-&gt;irq, IRQ_DISABLE_UNLAZY);</div><div class='add'>+	ret = devm_request_threaded_irq(dev, spi-&gt;irq, vsc_tp_isr,</div><div class='add'>+					vsc_tp_thread_isr,</div><div class='add'>+					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,</div><div class='add'>+					dev_name(dev), tp);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;tp-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	/* only one child acpi device */</div><div class='add'>+	ret = acpi_dev_for_each_child(ACPI_COMPANION(dev),</div><div class='add'>+				      vsc_tp_match_any, &amp;adev);</div><div class='add'>+	if (!ret) {</div><div class='add'>+		ret = -ENODEV;</div><div class='add'>+		goto err_destroy_lock;</div><div class='add'>+	}</div><div class='add'>+	pinfo.fwnode = acpi_fwnode_handle(adev);</div><div class='add'>+</div><div class='add'>+	pinfo.name = "intel_vsc";</div><div class='add'>+	pinfo.data = &amp;tp;</div><div class='add'>+	pinfo.size_data = sizeof(tp);</div><div class='add'>+	pinfo.id = PLATFORM_DEVID_NONE;</div><div class='add'>+</div><div class='add'>+	pdev = platform_device_register_full(&amp;pinfo);</div><div class='add'>+	if (IS_ERR(pdev)) {</div><div class='add'>+		ret = PTR_ERR(pdev);</div><div class='add'>+		goto err_destroy_lock;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tp-&gt;pdev = pdev;</div><div class='add'>+	spi_set_drvdata(spi, tp);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_destroy_lock:</div><div class='add'>+	mutex_destroy(&amp;tp-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vsc_tp_remove(struct spi_device *spi)</div><div class='add'>+{</div><div class='add'>+	struct vsc_tp *tp = spi_get_drvdata(spi);</div><div class='add'>+</div><div class='add'>+	platform_device_unregister(tp-&gt;pdev);</div><div class='add'>+</div><div class='add'>+	mutex_destroy(&amp;tp-&gt;mutex);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct acpi_device_id vsc_tp_acpi_ids[] = {</div><div class='add'>+	{ "INTC1009" }, /* Raptor Lake */</div><div class='add'>+	{ "INTC1058" }, /* Tiger Lake */</div><div class='add'>+	{ "INTC1094" }, /* Alder Lake */</div><div class='add'>+	{}</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(acpi, vsc_tp_acpi_ids);</div><div class='add'>+</div><div class='add'>+static struct spi_driver vsc_tp_driver = {</div><div class='add'>+	.probe = vsc_tp_probe,</div><div class='add'>+	.remove = vsc_tp_remove,</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "vsc-tp",</div><div class='add'>+		.acpi_match_table = vsc_tp_acpi_ids,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+module_spi_driver(vsc_tp_driver);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Wentong Wu &lt;wentong.wu@intel.com&gt;");</div><div class='add'>+MODULE_AUTHOR("Zhifeng Wang &lt;zhifeng.wang@intel.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("Intel Visual Sensing Controller Transport Layer");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/misc/mei/vsc-tp.h b/drivers/misc/mei/vsc-tp.h<br/>new file mode 100644<br/>index 000000000000..f9513ddc3e40<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/mei/vsc-tp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/mei/vsc-tp.h</a></div><div class='hunk'>@@ -0,0 +1,50 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (c) 2023, Intel Corporation.</div><div class='add'>+ * Intel Visual Sensing Controller Transport Layer Linux driver</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _VSC_TP_H_</div><div class='add'>+#define _VSC_TP_H_</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+</div><div class='add'>+#define VSC_TP_CMD_WRITE	0x01</div><div class='add'>+#define VSC_TP_CMD_READ		0x02</div><div class='add'>+</div><div class='add'>+#define VSC_TP_CMD_ACK		0x10</div><div class='add'>+#define VSC_TP_CMD_NACK		0x11</div><div class='add'>+#define VSC_TP_CMD_BUSY		0x12</div><div class='add'>+</div><div class='add'>+struct vsc_tp;</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * typedef vsc_event_cb_t - event callback function signature</div><div class='add'>+ * @context: the execution context of who registered this callback</div><div class='add'>+ *</div><div class='add'>+ * The callback function is called in interrupt context and the data</div><div class='add'>+ * payload is only valid during the call. If the user needs access</div><div class='add'>+ * the data payload later, it must copy the payload.</div><div class='add'>+ */</div><div class='add'>+typedef void (*vsc_tp_event_cb_t)(void *context);</div><div class='add'>+</div><div class='add'>+int vsc_tp_rom_xfer(struct vsc_tp *tp, const void *obuf, void *ibuf,</div><div class='add'>+		    size_t len);</div><div class='add'>+</div><div class='add'>+int vsc_tp_xfer(struct vsc_tp *tp, u8 cmd, const void *obuf, size_t olen,</div><div class='add'>+		void *ibuf, size_t ilen);</div><div class='add'>+</div><div class='add'>+int vsc_tp_register_event_cb(struct vsc_tp *tp, vsc_tp_event_cb_t event_cb,</div><div class='add'>+			     void *context);</div><div class='add'>+</div><div class='add'>+void vsc_tp_intr_enable(struct vsc_tp *tp);</div><div class='add'>+void vsc_tp_intr_disable(struct vsc_tp *tp);</div><div class='add'>+void vsc_tp_intr_synchronize(struct vsc_tp *tp);</div><div class='add'>+</div><div class='add'>+void vsc_tp_reset(struct vsc_tp *tp);</div><div class='add'>+</div><div class='add'>+bool vsc_tp_need_read(struct vsc_tp *tp);</div><div class='add'>+</div><div class='add'>+int vsc_tp_init(struct vsc_tp *tp, struct device *dev);</div><div class='add'>+</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/misc/nsm.c b/drivers/misc/nsm.c<br/>new file mode 100644<br/>index 000000000000..0eaa3b4484bd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/nsm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/nsm.c</a></div><div class='hunk'>@@ -0,0 +1,506 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * Amazon Nitro Secure Module driver.</div><div class='add'>+ *</div><div class='add'>+ * Copyright Amazon.com, Inc. or its affiliates. All Rights Reserved.</div><div class='add'>+ *</div><div class='add'>+ * The Nitro Secure Module implements commands via CBOR over virtio.</div><div class='add'>+ * This driver exposes a raw message ioctls on /dev/nsm that user</div><div class='add'>+ * space can use to issue these commands.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/file.h&gt;</div><div class='add'>+#include &lt;linux/fs.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/hw_random.h&gt;</div><div class='add'>+#include &lt;linux/miscdevice.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/uaccess.h&gt;</div><div class='add'>+#include &lt;linux/uio.h&gt;</div><div class='add'>+#include &lt;linux/virtio_config.h&gt;</div><div class='add'>+#include &lt;linux/virtio_ids.h&gt;</div><div class='add'>+#include &lt;linux/virtio.h&gt;</div><div class='add'>+#include &lt;linux/wait.h&gt;</div><div class='add'>+#include &lt;uapi/linux/nsm.h&gt;</div><div class='add'>+</div><div class='add'>+/* Timeout for NSM virtqueue respose in milliseconds. */</div><div class='add'>+#define NSM_DEFAULT_TIMEOUT_MSECS (120000) /* 2 minutes */</div><div class='add'>+</div><div class='add'>+/* Maximum length input data */</div><div class='add'>+struct nsm_data_req {</div><div class='add'>+	u32 len;</div><div class='add'>+	u8  data[NSM_REQUEST_MAX_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Maximum length output data */</div><div class='add'>+struct nsm_data_resp {</div><div class='add'>+	u32 len;</div><div class='add'>+	u8  data[NSM_RESPONSE_MAX_SIZE];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Full NSM request/response message */</div><div class='add'>+struct nsm_msg {</div><div class='add'>+	struct nsm_data_req req;</div><div class='add'>+	struct nsm_data_resp resp;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nsm {</div><div class='add'>+	struct virtio_device *vdev;</div><div class='add'>+	struct virtqueue     *vq;</div><div class='add'>+	struct mutex          lock;</div><div class='add'>+	struct completion     cmd_done;</div><div class='add'>+	struct miscdevice     misc;</div><div class='add'>+	struct hwrng          hwrng;</div><div class='add'>+	struct work_struct    misc_init;</div><div class='add'>+	struct nsm_msg        msg;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* NSM device ID */</div><div class='add'>+static const struct virtio_device_id id_table[] = {</div><div class='add'>+	{ VIRTIO_ID_NITRO_SEC_MOD, VIRTIO_DEV_ANY_ID },</div><div class='add'>+	{ 0 },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct nsm *file_to_nsm(struct file *file)</div><div class='add'>+{</div><div class='add'>+	return container_of(file-&gt;private_data, struct nsm, misc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct nsm *hwrng_to_nsm(struct hwrng *rng)</div><div class='add'>+{</div><div class='add'>+	return container_of(rng, struct nsm, hwrng);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define CBOR_TYPE_MASK  0xE0</div><div class='add'>+#define CBOR_TYPE_MAP 0xA0</div><div class='add'>+#define CBOR_TYPE_TEXT 0x60</div><div class='add'>+#define CBOR_TYPE_ARRAY 0x40</div><div class='add'>+#define CBOR_HEADER_SIZE_SHORT 1</div><div class='add'>+</div><div class='add'>+#define CBOR_SHORT_SIZE_MAX_VALUE 23</div><div class='add'>+#define CBOR_LONG_SIZE_U8  24</div><div class='add'>+#define CBOR_LONG_SIZE_U16 25</div><div class='add'>+#define CBOR_LONG_SIZE_U32 26</div><div class='add'>+#define CBOR_LONG_SIZE_U64 27</div><div class='add'>+</div><div class='add'>+static bool cbor_object_is_array(const u8 *cbor_object, size_t cbor_object_size)</div><div class='add'>+{</div><div class='add'>+	if (cbor_object_size == 0 || cbor_object == NULL)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	return (cbor_object[0] &amp; CBOR_TYPE_MASK) == CBOR_TYPE_ARRAY;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int cbor_object_get_array(u8 *cbor_object, size_t cbor_object_size, u8 **cbor_array)</div><div class='add'>+{</div><div class='add'>+	u8 cbor_short_size;</div><div class='add'>+	void *array_len_p;</div><div class='add'>+	u64 array_len;</div><div class='add'>+	u64 array_offset;</div><div class='add'>+</div><div class='add'>+	if (!cbor_object_is_array(cbor_object, cbor_object_size))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	cbor_short_size = (cbor_object[0] &amp; 0x1F);</div><div class='add'>+</div><div class='add'>+	/* Decoding byte array length */</div><div class='add'>+	array_offset = CBOR_HEADER_SIZE_SHORT;</div><div class='add'>+	if (cbor_short_size &gt;= CBOR_LONG_SIZE_U8)</div><div class='add'>+		array_offset += BIT(cbor_short_size - CBOR_LONG_SIZE_U8);</div><div class='add'>+</div><div class='add'>+	if (cbor_object_size &lt; array_offset)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	array_len_p = &amp;cbor_object[1];</div><div class='add'>+</div><div class='add'>+	switch (cbor_short_size) {</div><div class='add'>+	case CBOR_SHORT_SIZE_MAX_VALUE: /* short encoding */</div><div class='add'>+		array_len = cbor_short_size;</div><div class='add'>+		break;</div><div class='add'>+	case CBOR_LONG_SIZE_U8:</div><div class='add'>+		array_len = *(u8 *)array_len_p;</div><div class='add'>+		break;</div><div class='add'>+	case CBOR_LONG_SIZE_U16:</div><div class='add'>+		array_len = be16_to_cpup((__be16 *)array_len_p);</div><div class='add'>+		break;</div><div class='add'>+	case CBOR_LONG_SIZE_U32:</div><div class='add'>+		array_len = be32_to_cpup((__be32 *)array_len_p);</div><div class='add'>+		break;</div><div class='add'>+	case CBOR_LONG_SIZE_U64:</div><div class='add'>+		array_len = be64_to_cpup((__be64 *)array_len_p);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (cbor_object_size &lt; array_offset)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (cbor_object_size - array_offset &lt; array_len)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	if (array_len &gt; INT_MAX)</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	*cbor_array = cbor_object + array_offset;</div><div class='add'>+	return array_len;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Copy the request of a raw message to kernel space */</div><div class='add'>+static int fill_req_raw(struct nsm *nsm, struct nsm_data_req *req,</div><div class='add'>+			struct nsm_raw *raw)</div><div class='add'>+{</div><div class='add'>+	/* Verify the user input size. */</div><div class='add'>+	if (raw-&gt;request.len &gt; sizeof(req-&gt;data))</div><div class='add'>+		return -EMSGSIZE;</div><div class='add'>+</div><div class='add'>+	/* Copy the request payload */</div><div class='add'>+	if (copy_from_user(req-&gt;data, u64_to_user_ptr(raw-&gt;request.addr),</div><div class='add'>+			   raw-&gt;request.len))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	req-&gt;len = raw-&gt;request.len;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Copy the response of a raw message back to user-space */</div><div class='add'>+static int parse_resp_raw(struct nsm *nsm, struct nsm_data_resp *resp,</div><div class='add'>+			  struct nsm_raw *raw)</div><div class='add'>+{</div><div class='add'>+	/* Truncate any message that does not fit. */</div><div class='add'>+	raw-&gt;response.len = min_t(u64, raw-&gt;response.len, resp-&gt;len);</div><div class='add'>+</div><div class='add'>+	/* Copy the response content to user space */</div><div class='add'>+	if (copy_to_user(u64_to_user_ptr(raw-&gt;response.addr),</div><div class='add'>+			 resp-&gt;data, raw-&gt;response.len))</div><div class='add'>+		return -EFAULT;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Virtqueue interrupt handler */</div><div class='add'>+static void nsm_vq_callback(struct virtqueue *vq)</div><div class='add'>+{</div><div class='add'>+	struct nsm *nsm = vq-&gt;vdev-&gt;priv;</div><div class='add'>+</div><div class='add'>+	complete(&amp;nsm-&gt;cmd_done);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Forward a message to the NSM device and wait for the response from it */</div><div class='add'>+static int nsm_sendrecv_msg_locked(struct nsm *nsm)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;nsm-&gt;vdev-&gt;dev;</div><div class='add'>+	struct scatterlist sg_in, sg_out;</div><div class='add'>+	struct nsm_msg *msg = &amp;nsm-&gt;msg;</div><div class='add'>+	struct virtqueue *vq = nsm-&gt;vq;</div><div class='add'>+	unsigned int len;</div><div class='add'>+	void *queue_buf;</div><div class='add'>+	bool kicked;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	/* Initialize scatter-gather lists with request and response buffers. */</div><div class='add'>+	sg_init_one(&amp;sg_out, msg-&gt;req.data, msg-&gt;req.len);</div><div class='add'>+	sg_init_one(&amp;sg_in, msg-&gt;resp.data, sizeof(msg-&gt;resp.data));</div><div class='add'>+</div><div class='add'>+	init_completion(&amp;nsm-&gt;cmd_done);</div><div class='add'>+	/* Add the request buffer (read by the device). */</div><div class='add'>+	rc = virtqueue_add_outbuf(vq, &amp;sg_out, 1, msg-&gt;req.data, GFP_KERNEL);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	/* Add the response buffer (written by the device). */</div><div class='add'>+	rc = virtqueue_add_inbuf(vq, &amp;sg_in, 1, msg-&gt;resp.data, GFP_KERNEL);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	kicked = virtqueue_kick(vq);</div><div class='add'>+	if (!kicked) {</div><div class='add'>+		/* Cannot kick the virtqueue. */</div><div class='add'>+		rc = -EIO;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If the kick succeeded, wait for the device's response. */</div><div class='add'>+	if (!wait_for_completion_io_timeout(&amp;nsm-&gt;cmd_done,</div><div class='add'>+		msecs_to_jiffies(NSM_DEFAULT_TIMEOUT_MSECS))) {</div><div class='add'>+		rc = -ETIMEDOUT;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue_buf = virtqueue_get_buf(vq, &amp;len);</div><div class='add'>+	if (!queue_buf || (queue_buf != msg-&gt;req.data)) {</div><div class='add'>+		dev_err(dev, "wrong request buffer.");</div><div class='add'>+		rc = -ENODATA;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	queue_buf = virtqueue_get_buf(vq, &amp;len);</div><div class='add'>+	if (!queue_buf || (queue_buf != msg-&gt;resp.data)) {</div><div class='add'>+		dev_err(dev, "wrong response buffer.");</div><div class='add'>+		rc = -ENODATA;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	msg-&gt;resp.len = len;</div><div class='add'>+</div><div class='add'>+	rc = 0;</div><div class='add'>+</div><div class='add'>+cleanup:</div><div class='add'>+	if (rc) {</div><div class='add'>+		/* Clean the virtqueue. */</div><div class='add'>+		while (virtqueue_get_buf(vq, &amp;len) != NULL)</div><div class='add'>+			;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int fill_req_get_random(struct nsm *nsm, struct nsm_data_req *req)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * 69                          # text(9)</div><div class='add'>+	 *     47657452616E646F6D      # "GetRandom"</div><div class='add'>+	 */</div><div class='add'>+	const u8 request[] = { CBOR_TYPE_TEXT + strlen("GetRandom"),</div><div class='add'>+			       'G', 'e', 't', 'R', 'a', 'n', 'd', 'o', 'm' };</div><div class='add'>+</div><div class='add'>+	memcpy(req-&gt;data, request, sizeof(request));</div><div class='add'>+	req-&gt;len = sizeof(request);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int parse_resp_get_random(struct nsm *nsm, struct nsm_data_resp *resp,</div><div class='add'>+				 void *out, size_t max)</div><div class='add'>+{</div><div class='add'>+	/*</div><div class='add'>+	 * A1                          # map(1)</div><div class='add'>+	 *     69                      # text(9) - Name of field</div><div class='add'>+	 *         47657452616E646F6D  # "GetRandom"</div><div class='add'>+	 * A1                          # map(1) - The field itself</div><div class='add'>+	 *     66                      # text(6)</div><div class='add'>+	 *         72616E646F6D        # "random"</div><div class='add'>+	 *	# The rest of the response is random data</div><div class='add'>+	 */</div><div class='add'>+	const u8 response[] = { CBOR_TYPE_MAP + 1,</div><div class='add'>+				CBOR_TYPE_TEXT + strlen("GetRandom"),</div><div class='add'>+				'G', 'e', 't', 'R', 'a', 'n', 'd', 'o', 'm',</div><div class='add'>+				CBOR_TYPE_MAP + 1,</div><div class='add'>+				CBOR_TYPE_TEXT + strlen("random"),</div><div class='add'>+				'r', 'a', 'n', 'd', 'o', 'm' };</div><div class='add'>+	struct device *dev = &amp;nsm-&gt;vdev-&gt;dev;</div><div class='add'>+	u8 *rand_data = NULL;</div><div class='add'>+	u8 *resp_ptr = resp-&gt;data;</div><div class='add'>+	u64 resp_len = resp-&gt;len;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if ((resp-&gt;len &lt; sizeof(response) + 1) ||</div><div class='add'>+	    (memcmp(resp_ptr, response, sizeof(response)) != 0)) {</div><div class='add'>+		dev_err(dev, "Invalid response for GetRandom");</div><div class='add'>+		return -EFAULT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	resp_ptr += sizeof(response);</div><div class='add'>+	resp_len -= sizeof(response);</div><div class='add'>+</div><div class='add'>+	rc = cbor_object_get_array(resp_ptr, resp_len, &amp;rand_data);</div><div class='add'>+	if (rc &lt; 0) {</div><div class='add'>+		dev_err(dev, "GetRandom: Invalid CBOR encoding\n");</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = min_t(size_t, rc, max);</div><div class='add'>+	memcpy(out, rand_data, rc);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/*</div><div class='add'>+ * HwRNG implementation</div><div class='add'>+ */</div><div class='add'>+static int nsm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)</div><div class='add'>+{</div><div class='add'>+	struct nsm *nsm = hwrng_to_nsm(rng);</div><div class='add'>+	struct device *dev = &amp;nsm-&gt;vdev-&gt;dev;</div><div class='add'>+	int rc = 0;</div><div class='add'>+</div><div class='add'>+	/* NSM always needs to wait for a response */</div><div class='add'>+	if (!wait)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;nsm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	rc = fill_req_get_random(nsm, &amp;nsm-&gt;msg.req);</div><div class='add'>+	if (rc != 0)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	rc = nsm_sendrecv_msg_locked(nsm);</div><div class='add'>+	if (rc != 0)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	rc = parse_resp_get_random(nsm, &amp;nsm-&gt;msg.resp, data, max);</div><div class='add'>+	if (rc &lt; 0)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	dev_dbg(dev, "RNG: returning rand bytes = %d", rc);</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;nsm-&gt;lock);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static long nsm_dev_ioctl(struct file *file, unsigned int cmd,</div><div class='add'>+	unsigned long arg)</div><div class='add'>+{</div><div class='add'>+	void __user *argp = u64_to_user_ptr((u64)arg);</div><div class='add'>+	struct nsm *nsm = file_to_nsm(file);</div><div class='add'>+	struct nsm_raw raw;</div><div class='add'>+	int r = 0;</div><div class='add'>+</div><div class='add'>+	if (cmd != NSM_IOCTL_RAW)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (_IOC_SIZE(cmd) != sizeof(raw))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* Copy user argument struct to kernel argument struct */</div><div class='add'>+	r = -EFAULT;</div><div class='add'>+	if (copy_from_user(&amp;raw, argp, _IOC_SIZE(cmd)))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;nsm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Convert kernel argument struct to device request */</div><div class='add'>+	r = fill_req_raw(nsm, &amp;nsm-&gt;msg.req, &amp;raw);</div><div class='add'>+	if (r)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* Send message to NSM and read reply */</div><div class='add'>+	r = nsm_sendrecv_msg_locked(nsm);</div><div class='add'>+	if (r)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* Parse device response into kernel argument struct */</div><div class='add'>+	r = parse_resp_raw(nsm, &amp;nsm-&gt;msg.resp, &amp;raw);</div><div class='add'>+	if (r)</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	/* Copy kernel argument struct back to user argument struct */</div><div class='add'>+	r = -EFAULT;</div><div class='add'>+	if (copy_to_user(argp, &amp;raw, sizeof(raw)))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	r = 0;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;nsm-&gt;lock);</div><div class='add'>+	return r;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nsm_device_init_vq(struct virtio_device *vdev)</div><div class='add'>+{</div><div class='add'>+	struct virtqueue *vq = virtio_find_single_vq(vdev,</div><div class='add'>+		nsm_vq_callback, "nsm.vq.0");</div><div class='add'>+	struct nsm *nsm = vdev-&gt;priv;</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(vq))</div><div class='add'>+		return PTR_ERR(vq);</div><div class='add'>+</div><div class='add'>+	nsm-&gt;vq = vq;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations nsm_dev_fops = {</div><div class='add'>+	.unlocked_ioctl = nsm_dev_ioctl,</div><div class='add'>+	.compat_ioctl = compat_ptr_ioctl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Handler for probing the NSM device */</div><div class='add'>+static int nsm_device_probe(struct virtio_device *vdev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;vdev-&gt;dev;</div><div class='add'>+	struct nsm *nsm;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	nsm = devm_kzalloc(&amp;vdev-&gt;dev, sizeof(*nsm), GFP_KERNEL);</div><div class='add'>+	if (!nsm)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	vdev-&gt;priv = nsm;</div><div class='add'>+	nsm-&gt;vdev = vdev;</div><div class='add'>+</div><div class='add'>+	rc = nsm_device_init_vq(vdev);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_err(dev, "queue failed to initialize: %d.\n", rc);</div><div class='add'>+		goto err_init_vq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_init(&amp;nsm-&gt;lock);</div><div class='add'>+</div><div class='add'>+	/* Register as hwrng provider */</div><div class='add'>+	nsm-&gt;hwrng = (struct hwrng) {</div><div class='add'>+		.read = nsm_rng_read,</div><div class='add'>+		.name = "nsm-hwrng",</div><div class='add'>+		.quality = 1000,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rc = hwrng_register(&amp;nsm-&gt;hwrng);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_err(dev, "RNG initialization error: %d.\n", rc);</div><div class='add'>+		goto err_hwrng;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Register /dev/nsm device node */</div><div class='add'>+	nsm-&gt;misc = (struct miscdevice) {</div><div class='add'>+		.minor	= MISC_DYNAMIC_MINOR,</div><div class='add'>+		.name	= "nsm",</div><div class='add'>+		.fops	= &amp;nsm_dev_fops,</div><div class='add'>+		.mode	= 0666,</div><div class='add'>+	};</div><div class='add'>+</div><div class='add'>+	rc = misc_register(&amp;nsm-&gt;misc);</div><div class='add'>+	if (rc) {</div><div class='add'>+		dev_err(dev, "misc device registration error: %d.\n", rc);</div><div class='add'>+		goto err_misc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_misc:</div><div class='add'>+	hwrng_unregister(&amp;nsm-&gt;hwrng);</div><div class='add'>+err_hwrng:</div><div class='add'>+	vdev-&gt;config-&gt;del_vqs(vdev);</div><div class='add'>+err_init_vq:</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Handler for removing the NSM device */</div><div class='add'>+static void nsm_device_remove(struct virtio_device *vdev)</div><div class='add'>+{</div><div class='add'>+	struct nsm *nsm = vdev-&gt;priv;</div><div class='add'>+</div><div class='add'>+	hwrng_unregister(&amp;nsm-&gt;hwrng);</div><div class='add'>+</div><div class='add'>+	vdev-&gt;config-&gt;del_vqs(vdev);</div><div class='add'>+	misc_deregister(&amp;nsm-&gt;misc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* NSM device configuration structure */</div><div class='add'>+static struct virtio_driver virtio_nsm_driver = {</div><div class='add'>+	.feature_table             = 0,</div><div class='add'>+	.feature_table_size        = 0,</div><div class='add'>+	.feature_table_legacy      = 0,</div><div class='add'>+	.feature_table_size_legacy = 0,</div><div class='add'>+	.driver.name               = KBUILD_MODNAME,</div><div class='add'>+	.driver.owner              = THIS_MODULE,</div><div class='add'>+	.id_table                  = id_table,</div><div class='add'>+	.probe                     = nsm_device_probe,</div><div class='add'>+	.remove                    = nsm_device_remove,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+module_virtio_driver(virtio_nsm_driver);</div><div class='add'>+MODULE_DEVICE_TABLE(virtio, id_table);</div><div class='add'>+MODULE_DESCRIPTION("Virtio NSM driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/misc/ocxl/afu_irq.c b/drivers/misc/ocxl/afu_irq.c<br/>index a06920b7e049..36f7379b8e2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/afu_irq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/ocxl/afu_irq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/afu_irq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/afu_irq.c</a></div><div class='hunk'>@@ -57,7 +57,7 @@ EXPORT_SYMBOL_GPL(ocxl_irq_set_handler);</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t afu_irq_handler(int virq, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct afu_irq *irq = (struct afu_irq *) data;</div><div class='add'>+	struct afu_irq *irq = data;</div><div class='ctx'> </div><div class='ctx'> 	trace_ocxl_afu_irq_receive(virq);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/ocxl/context.c b/drivers/misc/ocxl/context.c<br/>index 7f83116ae11a..cded7d1caf32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/context.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/ocxl/context.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/context.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/context.c</a></div><div class='hunk'>@@ -55,7 +55,7 @@ EXPORT_SYMBOL_GPL(ocxl_context_alloc);</div><div class='ctx'>  */</div><div class='ctx'> static void xsl_fault_error(void *data, u64 addr, u64 dsisr)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_context *ctx = (struct ocxl_context *) data;</div><div class='add'>+	struct ocxl_context *ctx = data;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ctx-&gt;xsl_error_lock);</div><div class='ctx'> 	ctx-&gt;xsl_error.addr = addr;</div><div class='head'>diff --git a/drivers/misc/ocxl/file.c b/drivers/misc/ocxl/file.c<br/>index ac69b7f361f5..7eb74711ac96 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/file.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/ocxl/file.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/file.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/file.c</a></div><div class='hunk'>@@ -184,7 +184,7 @@ static irqreturn_t irq_handler(void *private)</div><div class='ctx'> {</div><div class='ctx'> 	struct eventfd_ctx *ev_ctx = private;</div><div class='ctx'> </div><div class='del'>-	eventfd_signal(ev_ctx, 1);</div><div class='add'>+	eventfd_signal(ev_ctx);</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c<br/>index c06c699c0e7b..03402203cacd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/link.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/ocxl/link.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/link.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/link.c</a></div><div class='hunk'>@@ -188,7 +188,7 @@ ack:</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t xsl_fault_handler(int irq, void *data)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) data;</div><div class='add'>+	struct ocxl_link *link = data;</div><div class='ctx'> 	struct spa *spa = link-&gt;spa;</div><div class='ctx'> 	u64 dsisr, dar, pe_handle;</div><div class='ctx'> 	struct pe_data *pe_data;</div><div class='hunk'>@@ -483,7 +483,7 @@ static void release_xsl(struct kref *ref)</div><div class='ctx'> </div><div class='ctx'> void ocxl_link_release(struct pci_dev *dev, void *link_handle)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;links_list_lock);</div><div class='ctx'> 	kref_put(&amp;link-&gt;ref, release_xsl);</div><div class='hunk'>@@ -540,7 +540,7 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,</div><div class='ctx'> 		void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),</div><div class='ctx'> 		void *xsl_err_data)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> 	struct spa *spa = link-&gt;spa;</div><div class='ctx'> 	struct ocxl_process_element *pe;</div><div class='ctx'> 	int pe_handle, rc = 0;</div><div class='hunk'>@@ -630,7 +630,7 @@ EXPORT_SYMBOL_GPL(ocxl_link_add_pe);</div><div class='ctx'> </div><div class='ctx'> int ocxl_link_update_pe(void *link_handle, int pasid, __u16 tid)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> 	struct spa *spa = link-&gt;spa;</div><div class='ctx'> 	struct ocxl_process_element *pe;</div><div class='ctx'> 	int pe_handle, rc;</div><div class='hunk'>@@ -666,7 +666,7 @@ int ocxl_link_update_pe(void *link_handle, int pasid, __u16 tid)</div><div class='ctx'> </div><div class='ctx'> int ocxl_link_remove_pe(void *link_handle, int pasid)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> 	struct spa *spa = link-&gt;spa;</div><div class='ctx'> 	struct ocxl_process_element *pe;</div><div class='ctx'> 	struct pe_data *pe_data;</div><div class='hunk'>@@ -752,7 +752,7 @@ EXPORT_SYMBOL_GPL(ocxl_link_remove_pe);</div><div class='ctx'> </div><div class='ctx'> int ocxl_link_irq_alloc(void *link_handle, int *hw_irq)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> 	int irq;</div><div class='ctx'> </div><div class='ctx'> 	if (atomic_dec_if_positive(&amp;link-&gt;irq_available) &lt; 0)</div><div class='hunk'>@@ -771,7 +771,7 @@ EXPORT_SYMBOL_GPL(ocxl_link_irq_alloc);</div><div class='ctx'> </div><div class='ctx'> void ocxl_link_free_irq(void *link_handle, int hw_irq)</div><div class='ctx'> {</div><div class='del'>-	struct ocxl_link *link = (struct ocxl_link *) link_handle;</div><div class='add'>+	struct ocxl_link *link = link_handle;</div><div class='ctx'> </div><div class='ctx'> 	xive_native_free_irq(hw_irq);</div><div class='ctx'> 	atomic_inc(&amp;link-&gt;irq_available);</div><div class='head'>diff --git a/drivers/misc/ocxl/main.c b/drivers/misc/ocxl/main.c<br/>index ef73cf35dda2..658974143c3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/ocxl/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/ocxl/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/ocxl/main.c</a></div><div class='hunk'>@@ -7,7 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> static int __init init_ocxl(void)</div><div class='ctx'> {</div><div class='del'>-	int rc = 0;</div><div class='add'>+	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (!tlbie_capable)</div><div class='ctx'> 		return -EINVAL;</div><div class='head'>diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c<br/>index af519088732d..c38a6083f0a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/pci_endpoint_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/pci_endpoint_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/pci_endpoint_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pci_endpoint_test.c</a></div><div class='hunk'>@@ -28,14 +28,14 @@</div><div class='ctx'> #define DRV_MODULE_NAME				"pci-endpoint-test"</div><div class='ctx'> </div><div class='ctx'> #define IRQ_TYPE_UNDEFINED			-1</div><div class='del'>-#define IRQ_TYPE_LEGACY				0</div><div class='add'>+#define IRQ_TYPE_INTX				0</div><div class='ctx'> #define IRQ_TYPE_MSI				1</div><div class='ctx'> #define IRQ_TYPE_MSIX				2</div><div class='ctx'> </div><div class='ctx'> #define PCI_ENDPOINT_TEST_MAGIC			0x0</div><div class='ctx'> </div><div class='ctx'> #define PCI_ENDPOINT_TEST_COMMAND		0x4</div><div class='del'>-#define COMMAND_RAISE_LEGACY_IRQ		BIT(0)</div><div class='add'>+#define COMMAND_RAISE_INTX_IRQ			BIT(0)</div><div class='ctx'> #define COMMAND_RAISE_MSI_IRQ			BIT(1)</div><div class='ctx'> #define COMMAND_RAISE_MSIX_IRQ			BIT(2)</div><div class='ctx'> #define COMMAND_READ				BIT(3)</div><div class='hunk'>@@ -183,8 +183,8 @@ static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,</div><div class='ctx'> 	bool res = true;</div><div class='ctx'> </div><div class='ctx'> 	switch (type) {</div><div class='del'>-	case IRQ_TYPE_LEGACY:</div><div class='del'>-		irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);</div><div class='add'>+	case IRQ_TYPE_INTX:</div><div class='add'>+		irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);</div><div class='ctx'> 		if (irq &lt; 0)</div><div class='ctx'> 			dev_err(dev, "Failed to get Legacy interrupt\n");</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -244,7 +244,7 @@ static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)</div><div class='ctx'> </div><div class='ctx'> fail:</div><div class='ctx'> 	switch (irq_type) {</div><div class='del'>-	case IRQ_TYPE_LEGACY:</div><div class='add'>+	case IRQ_TYPE_INTX:</div><div class='ctx'> 		dev_err(dev, "Failed to request IRQ %d for Legacy\n",</div><div class='ctx'> 			pci_irq_vector(pdev, i));</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -263,6 +263,15 @@ fail:</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const u32 bar_test_pattern[] = {</div><div class='add'>+	0xA0A0A0A0,</div><div class='add'>+	0xA1A1A1A1,</div><div class='add'>+	0xA2A2A2A2,</div><div class='add'>+	0xA3A3A3A3,</div><div class='add'>+	0xA4A4A4A4,</div><div class='add'>+	0xA5A5A5A5,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,</div><div class='ctx'> 				  enum pci_barno barno)</div><div class='ctx'> {</div><div class='hunk'>@@ -280,26 +289,27 @@ static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,</div><div class='ctx'> 		size = 0x4;</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; size; j += 4)</div><div class='del'>-		pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);</div><div class='add'>+		pci_endpoint_test_bar_writel(test, barno, j,</div><div class='add'>+					     bar_test_pattern[barno]);</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; size; j += 4) {</div><div class='ctx'> 		val = pci_endpoint_test_bar_readl(test, barno, j);</div><div class='del'>-		if (val != 0xA0A0A0A0)</div><div class='add'>+		if (val != bar_test_pattern[barno])</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)</div><div class='add'>+static bool pci_endpoint_test_intx_irq(struct pci_endpoint_test *test)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,</div><div class='del'>-				 IRQ_TYPE_LEGACY);</div><div class='add'>+				 IRQ_TYPE_INTX);</div><div class='ctx'> 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);</div><div class='ctx'> 	pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,</div><div class='del'>-				 COMMAND_RAISE_LEGACY_IRQ);</div><div class='add'>+				 COMMAND_RAISE_INTX_IRQ);</div><div class='ctx'> 	val = wait_for_completion_timeout(&amp;test-&gt;irq_raised,</div><div class='ctx'> 					  msecs_to_jiffies(1000));</div><div class='ctx'> 	if (!val)</div><div class='hunk'>@@ -385,7 +395,7 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,</div><div class='ctx'> 	if (use_dma)</div><div class='ctx'> 		flags |= FLAG_USE_DMA;</div><div class='ctx'> </div><div class='del'>-	if (irq_type &lt; IRQ_TYPE_LEGACY || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='add'>+	if (irq_type &lt; IRQ_TYPE_INTX || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='ctx'> 		dev_err(dev, "Invalid IRQ type option\n");</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -521,7 +531,7 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test,</div><div class='ctx'> 	if (use_dma)</div><div class='ctx'> 		flags |= FLAG_USE_DMA;</div><div class='ctx'> </div><div class='del'>-	if (irq_type &lt; IRQ_TYPE_LEGACY || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='add'>+	if (irq_type &lt; IRQ_TYPE_INTX || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='ctx'> 		dev_err(dev, "Invalid IRQ type option\n");</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -621,7 +631,7 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test,</div><div class='ctx'> 	if (use_dma)</div><div class='ctx'> 		flags |= FLAG_USE_DMA;</div><div class='ctx'> </div><div class='del'>-	if (irq_type &lt; IRQ_TYPE_LEGACY || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='add'>+	if (irq_type &lt; IRQ_TYPE_INTX || irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='ctx'> 		dev_err(dev, "Invalid IRQ type option\n");</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -691,7 +701,7 @@ static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,</div><div class='ctx'> 	struct pci_dev *pdev = test-&gt;pdev;</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> </div><div class='del'>-	if (req_irq_type &lt; IRQ_TYPE_LEGACY || req_irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='add'>+	if (req_irq_type &lt; IRQ_TYPE_INTX || req_irq_type &gt; IRQ_TYPE_MSIX) {</div><div class='ctx'> 		dev_err(dev, "Invalid IRQ type option\n");</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -737,8 +747,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,</div><div class='ctx'> 			goto ret;</div><div class='ctx'> 		ret = pci_endpoint_test_bar(test, bar);</div><div class='ctx'> 		break;</div><div class='del'>-	case PCITEST_LEGACY_IRQ:</div><div class='del'>-		ret = pci_endpoint_test_legacy_irq(test);</div><div class='add'>+	case PCITEST_INTX_IRQ:</div><div class='add'>+		ret = pci_endpoint_test_intx_irq(test);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case PCITEST_MSI:</div><div class='ctx'> 	case PCITEST_MSIX:</div><div class='hunk'>@@ -801,7 +811,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,</div><div class='ctx'> 	test-&gt;irq_type = IRQ_TYPE_UNDEFINED;</div><div class='ctx'> </div><div class='ctx'> 	if (no_msi)</div><div class='del'>-		irq_type = IRQ_TYPE_LEGACY;</div><div class='add'>+		irq_type = IRQ_TYPE_INTX;</div><div class='ctx'> </div><div class='ctx'> 	data = (struct pci_endpoint_test_data *)ent-&gt;driver_data;</div><div class='ctx'> 	if (data) {</div><div class='hunk'>@@ -860,7 +870,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	pci_set_drvdata(pdev, test);</div><div class='ctx'> </div><div class='del'>-	id = ida_simple_get(&amp;pci_endpoint_test_ida, 0, 0, GFP_KERNEL);</div><div class='add'>+	id = ida_alloc(&amp;pci_endpoint_test_ida, GFP_KERNEL);</div><div class='ctx'> 	if (id &lt; 0) {</div><div class='ctx'> 		err = id;</div><div class='ctx'> 		dev_err(dev, "Unable to get id\n");</div><div class='hunk'>@@ -907,7 +917,7 @@ err_kfree_test_name:</div><div class='ctx'> 	kfree(test-&gt;name);</div><div class='ctx'> </div><div class='ctx'> err_ida_remove:</div><div class='del'>-	ida_simple_remove(&amp;pci_endpoint_test_ida, id);</div><div class='add'>+	ida_free(&amp;pci_endpoint_test_ida, id);</div><div class='ctx'> </div><div class='ctx'> err_iounmap:</div><div class='ctx'> 	for (bar = 0; bar &lt; PCI_STD_NUM_BARS; bar++) {</div><div class='hunk'>@@ -943,7 +953,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)</div><div class='ctx'> 	misc_deregister(&amp;test-&gt;miscdev);</div><div class='ctx'> 	kfree(misc_device-&gt;name);</div><div class='ctx'> 	kfree(test-&gt;name);</div><div class='del'>-	ida_simple_remove(&amp;pci_endpoint_test_ida, id);</div><div class='add'>+	ida_free(&amp;pci_endpoint_test_ida, id);</div><div class='ctx'> 	for (bar = 0; bar &lt; PCI_STD_NUM_BARS; bar++) {</div><div class='ctx'> 		if (test-&gt;bar[bar])</div><div class='ctx'> 			pci_iounmap(pdev, test-&gt;bar[bar]);</div><div class='head'>diff --git a/drivers/misc/pvpanic/pvpanic-mmio.c b/drivers/misc/pvpanic/pvpanic-mmio.c<br/>index 9715798acce3..f3f2113a54a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic-mmio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/pvpanic/pvpanic-mmio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic-mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic-mmio.c</a></div><div class='hunk'>@@ -7,16 +7,15 @@</div><div class='ctx'>  *  Copyright (C) 2021 Oracle.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/err.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/ioport.h&gt;</div><div class='ctx'> #include &lt;linux/kexec.h&gt;</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;uapi/misc/pvpanic.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "pvpanic.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/pvpanic/pvpanic-pci.c b/drivers/misc/pvpanic/pvpanic-pci.c<br/>index 689af4c28c2a..9ad20e82785b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/pvpanic/pvpanic-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic-pci.c</a></div><div class='hunk'>@@ -5,17 +5,13 @@</div><div class='ctx'>  *  Copyright (C) 2021 Oracle.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;uapi/misc/pvpanic.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "pvpanic.h"</div><div class='ctx'> </div><div class='del'>-#define PCI_VENDOR_ID_REDHAT             0x1b36</div><div class='ctx'> #define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0011</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Mihai Carabas &lt;mihai.carabas@oracle.com&gt;");</div><div class='head'>diff --git a/drivers/misc/pvpanic/pvpanic.c b/drivers/misc/pvpanic/pvpanic.c<br/>index 305b367e0ce3..df3457ce1cb1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/pvpanic/pvpanic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic.c</a></div><div class='hunk'>@@ -8,16 +8,20 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+#include &lt;linux/gfp_types.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/kexec.h&gt;</div><div class='add'>+#include &lt;linux/kstrtox.h&gt;</div><div class='add'>+#include &lt;linux/limits.h&gt;</div><div class='add'>+#include &lt;linux/list.h&gt;</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/panic_notifier.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/spinlock.h&gt;</div><div class='add'>+#include &lt;linux/sysfs.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/cdev.h&gt;</div><div class='del'>-#include &lt;linux/list.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;uapi/misc/pvpanic.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/pvpanic/pvpanic.h b/drivers/misc/pvpanic/pvpanic.h<br/>index 46ffb10438ad..a42fa760eed5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/pvpanic/pvpanic.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/pvpanic/pvpanic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/pvpanic/pvpanic.h</a></div><div class='hunk'>@@ -8,6 +8,11 @@</div><div class='ctx'> #ifndef PVPANIC_H_</div><div class='ctx'> #define PVPANIC_H_</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/compiler_types.h&gt;</div><div class='add'>+</div><div class='add'>+struct attribute_group;</div><div class='add'>+struct device;</div><div class='add'>+</div><div class='ctx'> int devm_pvpanic_probe(struct device *dev, void __iomem *base);</div><div class='ctx'> extern const struct attribute_group *pvpanic_dev_groups[];</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/misc/vmw_vmci/vmci_handle_array.c b/drivers/misc/vmw_vmci/vmci_handle_array.c<br/>index de7fee7ead1b..681b3500125a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/vmw_vmci/vmci_handle_array.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/vmw_vmci/vmci_handle_array.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/vmw_vmci/vmci_handle_array.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/vmw_vmci/vmci_handle_array.c</a></div><div class='hunk'>@@ -8,12 +8,6 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include "vmci_handle_array.h"</div><div class='ctx'> </div><div class='del'>-static size_t handle_arr_calc_size(u32 capacity)</div><div class='del'>-{</div><div class='del'>-	return VMCI_HANDLE_ARRAY_HEADER_SIZE +</div><div class='del'>-	    capacity * sizeof(struct vmci_handle);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct vmci_handle_arr *vmci_handle_arr_create(u32 capacity, u32 max_capacity)</div><div class='ctx'> {</div><div class='ctx'> 	struct vmci_handle_arr *array;</div><div class='hunk'>@@ -25,7 +19,7 @@ struct vmci_handle_arr *vmci_handle_arr_create(u32 capacity, u32 max_capacity)</div><div class='ctx'> 		capacity = min((u32)VMCI_HANDLE_ARRAY_DEFAULT_CAPACITY,</div><div class='ctx'> 			       max_capacity);</div><div class='ctx'> </div><div class='del'>-	array = kmalloc(handle_arr_calc_size(capacity), GFP_ATOMIC);</div><div class='add'>+	array = kmalloc(struct_size(array, entries, capacity), GFP_ATOMIC);</div><div class='ctx'> 	if (!array)</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -51,8 +45,8 @@ int vmci_handle_arr_append_entry(struct vmci_handle_arr **array_ptr,</div><div class='ctx'> 		struct vmci_handle_arr *new_array;</div><div class='ctx'> 		u32 capacity_bump = min(array-&gt;max_capacity - array-&gt;capacity,</div><div class='ctx'> 					array-&gt;capacity);</div><div class='del'>-		size_t new_size = handle_arr_calc_size(array-&gt;capacity +</div><div class='del'>-						       capacity_bump);</div><div class='add'>+		size_t new_size = struct_size(array, entries,</div><div class='add'>+					      size_add(array-&gt;capacity, capacity_bump));</div><div class='ctx'> </div><div class='ctx'> 		if (array-&gt;size &gt;= array-&gt;max_capacity)</div><div class='ctx'> 			return VMCI_ERROR_NO_MEM;</div><div class='head'>diff --git a/drivers/misc/vmw_vmci/vmci_handle_array.h b/drivers/misc/vmw_vmci/vmci_handle_array.h<br/>index 96193f85be5b..27a38b97e8a8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/misc/vmw_vmci/vmci_handle_array.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/misc/vmw_vmci/vmci_handle_array.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/misc/vmw_vmci/vmci_handle_array.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/misc/vmw_vmci/vmci_handle_array.h</a></div><div class='hunk'>@@ -17,17 +17,11 @@ struct vmci_handle_arr {</div><div class='ctx'> 	u32 max_capacity;</div><div class='ctx'> 	u32 size;</div><div class='ctx'> 	u32 pad;</div><div class='del'>-	struct vmci_handle entries[];</div><div class='add'>+	struct vmci_handle entries[] __counted_by(capacity);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define VMCI_HANDLE_ARRAY_HEADER_SIZE				\</div><div class='del'>-	offsetof(struct vmci_handle_arr, entries)</div><div class='ctx'> /* Select a default capacity that results in a 64 byte sized array */</div><div class='ctx'> #define VMCI_HANDLE_ARRAY_DEFAULT_CAPACITY			6</div><div class='del'>-/* Make sure that the max array size can be expressed by a u32 */</div><div class='del'>-#define VMCI_HANDLE_ARRAY_MAX_CAPACITY				\</div><div class='del'>-	((U32_MAX - VMCI_HANDLE_ARRAY_HEADER_SIZE - 1) /	\</div><div class='del'>-	sizeof(struct vmci_handle))</div><div class='ctx'> </div><div class='ctx'> struct vmci_handle_arr *vmci_handle_arr_create(u32 capacity, u32 max_capacity);</div><div class='ctx'> void vmci_handle_arr_destroy(struct vmci_handle_arr *array);</div><div class='head'>diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c<br/>index 152dfe593c43..32d49100dff5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/block.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/block.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/block.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/block.c</a></div><div class='hunk'>@@ -400,6 +400,10 @@ struct mmc_blk_ioc_data {</div><div class='ctx'> 	struct mmc_ioc_cmd ic;</div><div class='ctx'> 	unsigned char *buf;</div><div class='ctx'> 	u64 buf_bytes;</div><div class='add'>+	unsigned int flags;</div><div class='add'>+#define MMC_BLK_IOC_DROP	BIT(0)	/* drop this mrq */</div><div class='add'>+#define MMC_BLK_IOC_SBC	BIT(1)	/* use mrq.sbc */</div><div class='add'>+</div><div class='ctx'> 	struct mmc_rpmb_data *rpmb;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -465,7 +469,7 @@ static int mmc_blk_ioctl_copy_to_user(struct mmc_ioc_cmd __user *ic_ptr,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,</div><div class='del'>-			       struct mmc_blk_ioc_data *idata)</div><div class='add'>+			       struct mmc_blk_ioc_data **idatas, int i)</div><div class='ctx'> {</div><div class='ctx'> 	struct mmc_command cmd = {}, sbc = {};</div><div class='ctx'> 	struct mmc_data data = {};</div><div class='hunk'>@@ -475,10 +479,18 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,</div><div class='ctx'> 	unsigned int busy_timeout_ms;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	unsigned int target_part;</div><div class='add'>+	struct mmc_blk_ioc_data *idata = idatas[i];</div><div class='add'>+	struct mmc_blk_ioc_data *prev_idata = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (!card || !md || !idata)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (idata-&gt;flags &amp; MMC_BLK_IOC_DROP)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (idata-&gt;flags &amp; MMC_BLK_IOC_SBC)</div><div class='add'>+		prev_idata = idatas[i - 1];</div><div class='add'>+</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The RPMB accesses comes in from the character device, so we</div><div class='ctx'> 	 * need to target these explicitly. Else we just target the</div><div class='hunk'>@@ -532,7 +544,7 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (idata-&gt;rpmb) {</div><div class='add'>+	if (idata-&gt;rpmb || prev_idata) {</div><div class='ctx'> 		sbc.opcode = MMC_SET_BLOCK_COUNT;</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * We don't do any blockcount validation because the max size</div><div class='hunk'>@@ -540,6 +552,8 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,</div><div class='ctx'> 		 * 'Reliable Write' bit here.</div><div class='ctx'> 		 */</div><div class='ctx'> 		sbc.arg = data.blocks | (idata-&gt;ic.write_flag &amp; BIT(31));</div><div class='add'>+		if (prev_idata)</div><div class='add'>+			sbc.arg = prev_idata-&gt;ic.arg;</div><div class='ctx'> 		sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;</div><div class='ctx'> 		mrq.sbc = &amp;sbc;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -557,6 +571,15 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,</div><div class='ctx'> 	mmc_wait_for_req(card-&gt;host, &amp;mrq);</div><div class='ctx'> 	memcpy(&amp;idata-&gt;ic.response, cmd.resp, sizeof(cmd.resp));</div><div class='ctx'> </div><div class='add'>+	if (prev_idata) {</div><div class='add'>+		memcpy(&amp;prev_idata-&gt;ic.response, sbc.resp, sizeof(sbc.resp));</div><div class='add'>+		if (sbc.error) {</div><div class='add'>+			dev_err(mmc_dev(card-&gt;host), "%s: sbc error %d\n",</div><div class='add'>+							__func__, sbc.error);</div><div class='add'>+			return sbc.error;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (cmd.error) {</div><div class='ctx'> 		dev_err(mmc_dev(card-&gt;host), "%s: cmd error %d\n",</div><div class='ctx'> 						__func__, cmd.error);</div><div class='hunk'>@@ -851,9 +874,10 @@ static const struct block_device_operations mmc_bdops = {</div><div class='ctx'> static int mmc_blk_part_switch_pre(struct mmc_card *card,</div><div class='ctx'> 				   unsigned int part_type)</div><div class='ctx'> {</div><div class='add'>+	const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {</div><div class='add'>+	if ((part_type &amp; mask) == mask) {</div><div class='ctx'> 		if (card-&gt;ext_csd.cmdq_en) {</div><div class='ctx'> 			ret = mmc_cmdq_disable(card);</div><div class='ctx'> 			if (ret)</div><div class='hunk'>@@ -868,9 +892,10 @@ static int mmc_blk_part_switch_pre(struct mmc_card *card,</div><div class='ctx'> static int mmc_blk_part_switch_post(struct mmc_card *card,</div><div class='ctx'> 				    unsigned int part_type)</div><div class='ctx'> {</div><div class='add'>+	const unsigned int mask = EXT_CSD_PART_CONFIG_ACC_RPMB;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (part_type == EXT_CSD_PART_CONFIG_ACC_RPMB) {</div><div class='add'>+	if ((part_type &amp; mask) == mask) {</div><div class='ctx'> 		mmc_retune_unpause(card-&gt;host);</div><div class='ctx'> 		if (card-&gt;reenable_cmdq &amp;&amp; !card-&gt;ext_csd.cmdq_en)</div><div class='ctx'> 			ret = mmc_cmdq_enable(card);</div><div class='hunk'>@@ -1032,6 +1057,20 @@ static inline void mmc_blk_reset_success(struct mmc_blk_data *md, int type)</div><div class='ctx'> 	md-&gt;reset_done &amp;= ~type;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmc_blk_check_sbc(struct mmc_queue_req *mq_rq)</div><div class='add'>+{</div><div class='add'>+	struct mmc_blk_ioc_data **idata = mq_rq-&gt;drv_op_data;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 1; i &lt; mq_rq-&gt;ioc_count; i++) {</div><div class='add'>+		if (idata[i - 1]-&gt;ic.opcode == MMC_SET_BLOCK_COUNT &amp;&amp;</div><div class='add'>+		    mmc_op_multi(idata[i]-&gt;ic.opcode)) {</div><div class='add'>+			idata[i - 1]-&gt;flags |= MMC_BLK_IOC_DROP;</div><div class='add'>+			idata[i]-&gt;flags |= MMC_BLK_IOC_SBC;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * The non-block commands come back from the block layer after it queued it and</div><div class='ctx'>  * processed it with all other requests and then they get issued in this</div><div class='hunk'>@@ -1059,11 +1098,14 @@ static void mmc_blk_issue_drv_op(struct mmc_queue *mq, struct request *req)</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		mmc_blk_check_sbc(mq_rq);</div><div class='add'>+</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case MMC_DRV_OP_IOCTL_RPMB:</div><div class='ctx'> 		idata = mq_rq-&gt;drv_op_data;</div><div class='ctx'> 		for (i = 0, ret = 0; i &lt; mq_rq-&gt;ioc_count; i++) {</div><div class='del'>-			ret = __mmc_blk_ioctl_cmd(card, md, idata[i]);</div><div class='add'>+			ret = __mmc_blk_ioctl_cmd(card, md, idata, i);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1482,6 +1524,8 @@ static void mmc_blk_cqe_complete_rq(struct mmc_queue *mq, struct request *req)</div><div class='ctx'> 			blk_mq_requeue_request(req, true);</div><div class='ctx'> 		else</div><div class='ctx'> 			__blk_mq_end_request(req, BLK_STS_OK);</div><div class='add'>+	} else if (mq-&gt;in_recovery) {</div><div class='add'>+		blk_mq_requeue_request(req, true);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		blk_mq_end_request(req, BLK_STS_OK);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3143,4 +3187,3 @@ module_exit(mmc_blk_exit);</div><div class='ctx'> </div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_DESCRIPTION("Multimedia Card (MMC) block device driver");</div><div class='del'>-</div><div class='head'>diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c<br/>index 3d3e0ca52614..a8c17b4cd737 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/core.c</a></div><div class='hunk'>@@ -551,7 +551,9 @@ int mmc_cqe_recovery(struct mmc_host *host)</div><div class='ctx'> 	cmd.flags        = MMC_RSP_R1B | MMC_CMD_AC;</div><div class='ctx'> 	cmd.flags       &amp;= ~MMC_RSP_CRC; /* Ignore CRC */</div><div class='ctx'> 	cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;</div><div class='del'>-	mmc_wait_for_cmd(host, &amp;cmd, 0);</div><div class='add'>+	mmc_wait_for_cmd(host, &amp;cmd, MMC_CMD_RETRIES);</div><div class='add'>+</div><div class='add'>+	mmc_poll_for_busy(host-&gt;card, MMC_CQE_RECOVERY_TIMEOUT, true, MMC_BUSY_IO);</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='ctx'> 	cmd.opcode       = MMC_CMDQ_TASK_MGMT;</div><div class='hunk'>@@ -559,10 +561,13 @@ int mmc_cqe_recovery(struct mmc_host *host)</div><div class='ctx'> 	cmd.flags        = MMC_RSP_R1B | MMC_CMD_AC;</div><div class='ctx'> 	cmd.flags       &amp;= ~MMC_RSP_CRC; /* Ignore CRC */</div><div class='ctx'> 	cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;</div><div class='del'>-	err = mmc_wait_for_cmd(host, &amp;cmd, 0);</div><div class='add'>+	err = mmc_wait_for_cmd(host, &amp;cmd, MMC_CMD_RETRIES);</div><div class='ctx'> </div><div class='ctx'> 	host-&gt;cqe_ops-&gt;cqe_recovery_finish(host);</div><div class='ctx'> </div><div class='add'>+	if (err)</div><div class='add'>+		err = mmc_wait_for_cmd(host, &amp;cmd, MMC_CMD_RETRIES);</div><div class='add'>+</div><div class='ctx'> 	mmc_retune_release(host);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='head'>diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c<br/>index 096093f7be00..cf396e8f34e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/host.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/host.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/host.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/host.c</a></div><div class='hunk'>@@ -119,13 +119,12 @@ void mmc_retune_enable(struct mmc_host *host)</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * Pause re-tuning for a small set of operations.  The pause begins after the</div><div class='del'>- * next command and after first doing re-tuning.</div><div class='add'>+ * next command.</div><div class='ctx'>  */</div><div class='ctx'> void mmc_retune_pause(struct mmc_host *host)</div><div class='ctx'> {</div><div class='ctx'> 	if (!host-&gt;retune_paused) {</div><div class='ctx'> 		host-&gt;retune_paused = 1;</div><div class='del'>-		mmc_retune_needed(host);</div><div class='ctx'> 		mmc_retune_hold(host);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -692,6 +691,7 @@ EXPORT_SYMBOL(mmc_remove_host);</div><div class='ctx'>  */</div><div class='ctx'> void mmc_free_host(struct mmc_host *host)</div><div class='ctx'> {</div><div class='add'>+	cancel_delayed_work_sync(&amp;host-&gt;detect);</div><div class='ctx'> 	mmc_pwrseq_free(host);</div><div class='ctx'> 	put_device(&amp;host-&gt;class_dev);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c<br/>index 705942edacc6..f410bee50132 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/mmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/mmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/mmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/mmc.c</a></div><div class='hunk'>@@ -136,6 +136,17 @@ static void mmc_set_erase_size(struct mmc_card *card)</div><div class='ctx'> 	mmc_init_erase(card);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+</div><div class='add'>+static void mmc_set_wp_grp_size(struct mmc_card *card)</div><div class='add'>+{</div><div class='add'>+	if (card-&gt;ext_csd.erase_group_def &amp; 1)</div><div class='add'>+		card-&gt;wp_grp_size = card-&gt;ext_csd.hc_erase_size *</div><div class='add'>+			card-&gt;ext_csd.raw_hc_erase_gap_size;</div><div class='add'>+	else</div><div class='add'>+		card-&gt;wp_grp_size = card-&gt;csd.erase_size *</div><div class='add'>+			(card-&gt;csd.wp_grp_size + 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Given a 128-bit response, decode to our card CSD structure.</div><div class='ctx'>  */</div><div class='hunk'>@@ -186,6 +197,7 @@ static int mmc_decode_csd(struct mmc_card *card)</div><div class='ctx'> 		b = UNSTUFF_BITS(resp, 37, 5);</div><div class='ctx'> 		csd-&gt;erase_size = (a + 1) * (b + 1);</div><div class='ctx'> 		csd-&gt;erase_size &lt;&lt;= csd-&gt;write_blkbits - 9;</div><div class='add'>+		csd-&gt;wp_grp_size = UNSTUFF_BITS(resp, 32, 5);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -613,11 +625,6 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)</div><div class='ctx'> 		} else {</div><div class='ctx'> 			card-&gt;ext_csd.data_tag_unit_size = 0;</div><div class='ctx'> 		}</div><div class='del'>-</div><div class='del'>-		card-&gt;ext_csd.max_packed_writes =</div><div class='del'>-			ext_csd[EXT_CSD_MAX_PACKED_WRITES];</div><div class='del'>-		card-&gt;ext_csd.max_packed_reads =</div><div class='del'>-			ext_csd[EXT_CSD_MAX_PACKED_READS];</div><div class='ctx'> 	} else {</div><div class='ctx'> 		card-&gt;ext_csd.data_sector_size = 512;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -790,6 +797,7 @@ MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card-&gt;raw_csd[0], card-&gt;raw_csd[1],</div><div class='ctx'> MMC_DEV_ATTR(date, "%02d/%04d\n", card-&gt;cid.month, card-&gt;cid.year);</div><div class='ctx'> MMC_DEV_ATTR(erase_size, "%u\n", card-&gt;erase_size &lt;&lt; 9);</div><div class='ctx'> MMC_DEV_ATTR(preferred_erase_size, "%u\n", card-&gt;pref_erase &lt;&lt; 9);</div><div class='add'>+MMC_DEV_ATTR(wp_grp_size, "%u\n", card-&gt;wp_grp_size &lt;&lt; 9);</div><div class='ctx'> MMC_DEV_ATTR(ffu_capable, "%d\n", card-&gt;ext_csd.ffu_capable);</div><div class='ctx'> MMC_DEV_ATTR(hwrev, "0x%x\n", card-&gt;cid.hwrev);</div><div class='ctx'> MMC_DEV_ATTR(manfid, "0x%06x\n", card-&gt;cid.manfid);</div><div class='hunk'>@@ -850,6 +858,7 @@ static struct attribute *mmc_std_attrs[] = {</div><div class='ctx'> 	&amp;dev_attr_date.attr,</div><div class='ctx'> 	&amp;dev_attr_erase_size.attr,</div><div class='ctx'> 	&amp;dev_attr_preferred_erase_size.attr,</div><div class='add'>+	&amp;dev_attr_wp_grp_size.attr,</div><div class='ctx'> 	&amp;dev_attr_fwrev.attr,</div><div class='ctx'> 	&amp;dev_attr_ffu_capable.attr,</div><div class='ctx'> 	&amp;dev_attr_hwrev.attr,</div><div class='hunk'>@@ -1764,7 +1773,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,</div><div class='ctx'> 			mmc_set_erase_size(card);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='add'>+	mmc_set_wp_grp_size(card);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Ensure eMMC user default partition is enabled</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -1822,8 +1831,13 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,</div><div class='ctx'> </div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto free_card;</div><div class='del'>-</div><div class='del'>-	} else if (!mmc_card_hs400es(card)) {</div><div class='add'>+	} else if (mmc_card_hs400es(card)) {</div><div class='add'>+		if (host-&gt;ops-&gt;execute_hs400_tuning) {</div><div class='add'>+			err = host-&gt;ops-&gt;execute_hs400_tuning(host, card);</div><div class='add'>+			if (err)</div><div class='add'>+				goto free_card;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='ctx'> 		/* Select the desired bus width optionally */</div><div class='ctx'> 		err = mmc_select_bus_width(card);</div><div class='ctx'> 		if (err &gt; 0 &amp;&amp; mmc_card_hs(card)) {</div><div class='head'>diff --git a/drivers/mmc/core/mmc_test.c b/drivers/mmc/core/mmc_test.c<br/>index 0f6a563103fd..8f7f587a0025 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/mmc_test.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/mmc_test.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/mmc_test.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/mmc_test.c</a></div><div class='hunk'>@@ -1904,7 +1904,7 @@ static unsigned int mmc_test_rnd_num(unsigned int rnd_cnt)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mmc_test_rnd_perf(struct mmc_test_card *test, int write, int print,</div><div class='del'>-			     unsigned long sz)</div><div class='add'>+			     unsigned long sz, int secs, int force_retuning)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int dev_addr, cnt, rnd_addr, range1, range2, last_ea = 0, ea;</div><div class='ctx'> 	unsigned int ssz;</div><div class='hunk'>@@ -1921,7 +1921,7 @@ static int mmc_test_rnd_perf(struct mmc_test_card *test, int write, int print,</div><div class='ctx'> 	for (cnt = 0; cnt &lt; UINT_MAX; cnt++) {</div><div class='ctx'> 		ktime_get_ts64(&amp;ts2);</div><div class='ctx'> 		ts = timespec64_sub(ts2, ts1);</div><div class='del'>-		if (ts.tv_sec &gt;= 10)</div><div class='add'>+		if (ts.tv_sec &gt;= secs)</div><div class='ctx'> 			break;</div><div class='ctx'> 		ea = mmc_test_rnd_num(range1);</div><div class='ctx'> 		if (ea == last_ea)</div><div class='hunk'>@@ -1929,6 +1929,8 @@ static int mmc_test_rnd_perf(struct mmc_test_card *test, int write, int print,</div><div class='ctx'> 		last_ea = ea;</div><div class='ctx'> 		dev_addr = rnd_addr + test-&gt;card-&gt;pref_erase * ea +</div><div class='ctx'> 			   ssz * mmc_test_rnd_num(range2);</div><div class='add'>+		if (force_retuning)</div><div class='add'>+			mmc_retune_needed(test-&gt;card-&gt;host);</div><div class='ctx'> 		ret = mmc_test_area_io(test, sz, dev_addr, write, 0, 0);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -1953,24 +1955,35 @@ static int mmc_test_random_perf(struct mmc_test_card *test, int write)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (write) {</div><div class='ctx'> 			next = rnd_next;</div><div class='del'>-			ret = mmc_test_rnd_perf(test, write, 0, sz);</div><div class='add'>+			ret = mmc_test_rnd_perf(test, write, 0, sz, 10, 0);</div><div class='ctx'> 			if (ret)</div><div class='ctx'> 				return ret;</div><div class='ctx'> 			rnd_next = next;</div><div class='ctx'> 		}</div><div class='del'>-		ret = mmc_test_rnd_perf(test, write, 1, sz);</div><div class='add'>+		ret = mmc_test_rnd_perf(test, write, 1, sz, 10, 0);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	sz = t-&gt;max_tfr;</div><div class='ctx'> 	if (write) {</div><div class='ctx'> 		next = rnd_next;</div><div class='del'>-		ret = mmc_test_rnd_perf(test, write, 0, sz);</div><div class='add'>+		ret = mmc_test_rnd_perf(test, write, 0, sz, 10, 0);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		rnd_next = next;</div><div class='ctx'> 	}</div><div class='del'>-	return mmc_test_rnd_perf(test, write, 1, sz);</div><div class='add'>+	return mmc_test_rnd_perf(test, write, 1, sz, 10, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mmc_test_retuning(struct mmc_test_card *test)</div><div class='add'>+{</div><div class='add'>+	if (!mmc_can_retune(test-&gt;card-&gt;host)) {</div><div class='add'>+		pr_info("%s: No retuning - test skipped\n",</div><div class='add'>+			mmc_hostname(test-&gt;card-&gt;host));</div><div class='add'>+		return RESULT_UNSUP_HOST;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return mmc_test_rnd_perf(test, 0, 0, 8192, 30, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -2921,6 +2934,14 @@ static const struct mmc_test_case mmc_test_cases[] = {</div><div class='ctx'> 		.run = mmc_test_cmds_during_write_cmd23_nonblock,</div><div class='ctx'> 		.cleanup = mmc_test_area_cleanup,</div><div class='ctx'> 	},</div><div class='add'>+</div><div class='add'>+	{</div><div class='add'>+		.name = "Re-tuning reliability",</div><div class='add'>+		.prepare = mmc_test_area_prepare,</div><div class='add'>+		.run = mmc_test_retuning,</div><div class='add'>+		.cleanup = mmc_test_area_cleanup,</div><div class='add'>+	},</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static DEFINE_MUTEX(mmc_test_lock);</div><div class='head'>diff --git a/drivers/mmc/core/sdio_uart.c b/drivers/mmc/core/sdio_uart.c<br/>index ef38dcd3a887..575ebbce378e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/core/sdio_uart.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/core/sdio_uart.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/core/sdio_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/core/sdio_uart.c</a></div><div class='hunk'>@@ -178,11 +178,9 @@ static inline void sdio_uart_release_func(struct sdio_uart_port *port)</div><div class='ctx'> 		sdio_release_host(port-&gt;func);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline unsigned int sdio_in(struct sdio_uart_port *port, int offset)</div><div class='add'>+static inline u8 sdio_in(struct sdio_uart_port *port, int offset)</div><div class='ctx'> {</div><div class='del'>-	unsigned char c;</div><div class='del'>-	c = sdio_readb(port-&gt;func, port-&gt;regs_offset + offset, NULL);</div><div class='del'>-	return c;</div><div class='add'>+	return sdio_readb(port-&gt;func, port-&gt;regs_offset + offset, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void sdio_out(struct sdio_uart_port *port, int offset, int value)</div><div class='hunk'>@@ -192,8 +190,8 @@ static inline void sdio_out(struct sdio_uart_port *port, int offset, int value)</div><div class='ctx'> </div><div class='ctx'> static unsigned int sdio_uart_get_mctrl(struct sdio_uart_port *port)</div><div class='ctx'> {</div><div class='del'>-	unsigned char status;</div><div class='ctx'> 	unsigned int ret;</div><div class='add'>+	u8 status;</div><div class='ctx'> </div><div class='ctx'> 	/* FIXME: What stops this losing the delta bits and breaking</div><div class='ctx'> 	   sdio_uart_check_modem_status ? */</div><div class='hunk'>@@ -354,15 +352,13 @@ static void sdio_uart_stop_rx(struct sdio_uart_port *port)</div><div class='ctx'> 	sdio_out(port, UART_IER, port-&gt;ier);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdio_uart_receive_chars(struct sdio_uart_port *port,</div><div class='del'>-				    unsigned int *status)</div><div class='add'>+static void sdio_uart_receive_chars(struct sdio_uart_port *port, u8 *status)</div><div class='ctx'> {</div><div class='del'>-	unsigned int ch, flag;</div><div class='ctx'> 	int max_count = 256;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='del'>-		ch = sdio_in(port, UART_RX);</div><div class='del'>-		flag = TTY_NORMAL;</div><div class='add'>+		u8 ch = sdio_in(port, UART_RX);</div><div class='add'>+		u8 flag = TTY_NORMAL;</div><div class='ctx'> 		port-&gt;icount.rx++;</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(*status &amp; (UART_LSR_BI | UART_LSR_PE |</div><div class='hunk'>@@ -449,8 +445,8 @@ static void sdio_uart_transmit_chars(struct sdio_uart_port *port)</div><div class='ctx'> </div><div class='ctx'> static void sdio_uart_check_modem_status(struct sdio_uart_port *port)</div><div class='ctx'> {</div><div class='del'>-	int status;</div><div class='ctx'> 	struct tty_struct *tty;</div><div class='add'>+	u8 status;</div><div class='ctx'> </div><div class='ctx'> 	status = sdio_in(port, UART_MSR);</div><div class='ctx'> </div><div class='hunk'>@@ -499,7 +495,7 @@ static void sdio_uart_check_modem_status(struct sdio_uart_port *port)</div><div class='ctx'> static void sdio_uart_irq(struct sdio_func *func)</div><div class='ctx'> {</div><div class='ctx'> 	struct sdio_uart_port *port = sdio_get_drvdata(func);</div><div class='del'>-	unsigned int iir, lsr;</div><div class='add'>+	u8 iir, lsr;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * In a few places sdio_uart_irq() is called directly instead of</div><div class='hunk'>@@ -795,7 +791,7 @@ static unsigned int sdio_uart_chars_in_buffer(struct tty_struct *tty)</div><div class='ctx'> 	return kfifo_len(&amp;port-&gt;xmit_fifo);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sdio_uart_send_xchar(struct tty_struct *tty, char ch)</div><div class='add'>+static void sdio_uart_send_xchar(struct tty_struct *tty, u8 ch)</div><div class='ctx'> {</div><div class='ctx'> 	struct sdio_uart_port *port = tty-&gt;driver_data;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig<br/>index 58bd5fe4cd25..81f2c4e05287 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/Kconfig</a></div><div class='hunk'>@@ -1026,14 +1026,15 @@ config MMC_SDHCI_XENON</div><div class='ctx'> </div><div class='ctx'> config MMC_SDHCI_OMAP</div><div class='ctx'> 	tristate "TI SDHCI Controller Support"</div><div class='add'>+	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || COMPILE_TEST</div><div class='ctx'> 	depends on MMC_SDHCI_PLTFM &amp;&amp; OF</div><div class='ctx'> 	select THERMAL</div><div class='ctx'> 	imply TI_SOC_THERMAL</div><div class='ctx'> 	select MMC_SDHCI_EXTERNAL_DMA if DMA_ENGINE</div><div class='ctx'> 	help</div><div class='ctx'> 	  This selects the Secure Digital Host Controller Interface (SDHCI)</div><div class='del'>-	  support present in TI's DRA7 SOCs. The controller supports</div><div class='del'>-	  SD/MMC/SDIO devices.</div><div class='add'>+	  support present in TI's Keystone/OMAP2+/DRA7 SOCs. The controller</div><div class='add'>+	  supports SD/MMC/SDIO devices.</div><div class='ctx'> </div><div class='ctx'> 	  If you have a controller with this interface, say Y or M here.</div><div class='ctx'> </div><div class='hunk'>@@ -1041,14 +1042,15 @@ config MMC_SDHCI_OMAP</div><div class='ctx'> </div><div class='ctx'> config MMC_SDHCI_AM654</div><div class='ctx'> 	tristate "Support for the SDHCI Controller in TI's AM654 SOCs"</div><div class='add'>+	depends on ARCH_K3 || COMPILE_TEST</div><div class='ctx'> 	depends on MMC_SDHCI_PLTFM &amp;&amp; OF</div><div class='ctx'> 	select MMC_SDHCI_IO_ACCESSORS</div><div class='ctx'> 	select MMC_CQHCI</div><div class='ctx'> 	select REGMAP_MMIO</div><div class='ctx'> 	help</div><div class='ctx'> 	  This selects the Secure Digital Host Controller Interface (SDHCI)</div><div class='del'>-	  support present in TI's AM654 SOCs. The controller supports</div><div class='del'>-	  SD/MMC/SDIO devices.</div><div class='add'>+	  support present in TI's AM65x/AM64x/AM62x/J721E SOCs. The controller</div><div class='add'>+	  supports SD/MMC/SDIO devices.</div><div class='ctx'> </div><div class='ctx'> 	  If you have a controller with this interface, say Y or M here.</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c<br/>index b3d7d6d8d654..41e94cd14109 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/cqhci-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/cqhci-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/cqhci-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/cqhci-core.c</a></div><div class='hunk'>@@ -942,8 +942,8 @@ static bool cqhci_clear_all_tasks(struct mmc_host *mmc, unsigned int timeout)</div><div class='ctx'> 	ret = cqhci_tasks_cleared(cq_host);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		pr_debug("%s: cqhci: Failed to clear tasks\n",</div><div class='del'>-			 mmc_hostname(mmc));</div><div class='add'>+		pr_warn("%s: cqhci: Failed to clear tasks\n",</div><div class='add'>+			mmc_hostname(mmc));</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -976,7 +976,7 @@ static bool cqhci_halt(struct mmc_host *mmc, unsigned int timeout)</div><div class='ctx'> 	ret = cqhci_halted(cq_host);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='del'>-		pr_debug("%s: cqhci: Failed to halt\n", mmc_hostname(mmc));</div><div class='add'>+		pr_warn("%s: cqhci: Failed to halt\n", mmc_hostname(mmc));</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -984,10 +984,10 @@ static bool cqhci_halt(struct mmc_host *mmc, unsigned int timeout)</div><div class='ctx'> /*</div><div class='ctx'>  * After halting we expect to be able to use the command line. We interpret the</div><div class='ctx'>  * failure to halt to mean the data lines might still be in use (and the upper</div><div class='del'>- * layers will need to send a STOP command), so we set the timeout based on a</div><div class='del'>- * generous command timeout.</div><div class='add'>+ * layers will need to send a STOP command), however failing to halt complicates</div><div class='add'>+ * the recovery, so set a timeout that would reasonably allow I/O to complete.</div><div class='ctx'>  */</div><div class='del'>-#define CQHCI_START_HALT_TIMEOUT	5</div><div class='add'>+#define CQHCI_START_HALT_TIMEOUT	500</div><div class='ctx'> </div><div class='ctx'> static void cqhci_recovery_start(struct mmc_host *mmc)</div><div class='ctx'> {</div><div class='hunk'>@@ -1075,28 +1075,28 @@ static void cqhci_recovery_finish(struct mmc_host *mmc)</div><div class='ctx'> </div><div class='ctx'> 	ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);</div><div class='ctx'> </div><div class='del'>-	if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))</div><div class='del'>-		ok = false;</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The specification contradicts itself, by saying that tasks cannot be</div><div class='ctx'> 	 * cleared if CQHCI does not halt, but if CQHCI does not halt, it should</div><div class='ctx'> 	 * be disabled/re-enabled, but not to disable before clearing tasks.</div><div class='ctx'> 	 * Have a go anyway.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!ok) {</div><div class='del'>-		pr_debug("%s: cqhci: disable / re-enable\n", mmc_hostname(mmc));</div><div class='del'>-		cqcfg = cqhci_readl(cq_host, CQHCI_CFG);</div><div class='del'>-		cqcfg &amp;= ~CQHCI_ENABLE;</div><div class='del'>-		cqhci_writel(cq_host, cqcfg, CQHCI_CFG);</div><div class='del'>-		cqcfg |= CQHCI_ENABLE;</div><div class='del'>-		cqhci_writel(cq_host, cqcfg, CQHCI_CFG);</div><div class='del'>-		/* Be sure that there are no tasks */</div><div class='del'>-		ok = cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);</div><div class='del'>-		if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))</div><div class='del'>-			ok = false;</div><div class='del'>-		WARN_ON(!ok);</div><div class='del'>-	}</div><div class='add'>+	if (!cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT))</div><div class='add'>+		ok = false;</div><div class='add'>+</div><div class='add'>+	/* Disable to make sure tasks really are cleared */</div><div class='add'>+	cqcfg = cqhci_readl(cq_host, CQHCI_CFG);</div><div class='add'>+	cqcfg &amp;= ~CQHCI_ENABLE;</div><div class='add'>+	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);</div><div class='add'>+</div><div class='add'>+	cqcfg = cqhci_readl(cq_host, CQHCI_CFG);</div><div class='add'>+	cqcfg |= CQHCI_ENABLE;</div><div class='add'>+	cqhci_writel(cq_host, cqcfg, CQHCI_CFG);</div><div class='add'>+</div><div class='add'>+	cqhci_halt(mmc, CQHCI_FINISH_HALT_TIMEOUT);</div><div class='add'>+</div><div class='add'>+	if (!ok)</div><div class='add'>+		cqhci_clear_all_tasks(mmc, CQHCI_CLEAR_TIMEOUT);</div><div class='ctx'> </div><div class='ctx'> 	cqhci_recover_mrqs(cq_host);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mmc/host/meson-mx-sdhc-mmc.c b/drivers/mmc/host/meson-mx-sdhc-mmc.c<br/>index 528ec8166e7c..1ed9731e77ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/meson-mx-sdhc-mmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/meson-mx-sdhc-mmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/meson-mx-sdhc-mmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/meson-mx-sdhc-mmc.c</a></div><div class='hunk'>@@ -269,7 +269,7 @@ static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)</div><div class='ctx'> static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> {</div><div class='ctx'> 	struct meson_mx_sdhc_host *host = mmc_priv(mmc);</div><div class='del'>-	u32 rx_clk_phase;</div><div class='add'>+	u32 val, rx_clk_phase;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	meson_mx_sdhc_disable_clks(mmc);</div><div class='hunk'>@@ -290,27 +290,11 @@ static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> 		mmc-&gt;actual_clock = clk_get_rate(host-&gt;sd_clk);</div><div class='ctx'> </div><div class='ctx'> 		/*</div><div class='del'>-		 * according to Amlogic the following latching points are</div><div class='del'>-		 * selected with empirical values, there is no (known) formula</div><div class='del'>-		 * to calculate these.</div><div class='add'>+		 * Phase 90 should work in most cases. For data transmission,</div><div class='add'>+		 * meson_mx_sdhc_execute_tuning() will find a accurate value</div><div class='ctx'> 		 */</div><div class='del'>-		if (mmc-&gt;actual_clock &gt; 100000000) {</div><div class='del'>-			rx_clk_phase = 1;</div><div class='del'>-		} else if (mmc-&gt;actual_clock &gt; 45000000) {</div><div class='del'>-			if (ios-&gt;signal_voltage == MMC_SIGNAL_VOLTAGE_330)</div><div class='del'>-				rx_clk_phase = 15;</div><div class='del'>-			else</div><div class='del'>-				rx_clk_phase = 11;</div><div class='del'>-		} else if (mmc-&gt;actual_clock &gt;= 25000000) {</div><div class='del'>-			rx_clk_phase = 15;</div><div class='del'>-		} else if (mmc-&gt;actual_clock &gt; 5000000) {</div><div class='del'>-			rx_clk_phase = 23;</div><div class='del'>-		} else if (mmc-&gt;actual_clock &gt; 1000000) {</div><div class='del'>-			rx_clk_phase = 55;</div><div class='del'>-		} else {</div><div class='del'>-			rx_clk_phase = 1061;</div><div class='del'>-		}</div><div class='del'>-</div><div class='add'>+		regmap_read(host-&gt;regmap, MESON_SDHC_CLKC, &amp;val);</div><div class='add'>+		rx_clk_phase = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val) / 4;</div><div class='ctx'> 		regmap_update_bits(host-&gt;regmap, MESON_SDHC_CLK2,</div><div class='ctx'> 				   MESON_SDHC_CLK2_RX_CLK_PHASE,</div><div class='ctx'> 				   FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,</div><div class='head'>diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c<br/>index cc333ad67cac..b8dda8160c4e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmc_spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/mmc_spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmc_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmc_spi.c</a></div><div class='hunk'>@@ -15,7 +15,7 @@</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/bio.h&gt;</div><div class='del'>-#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/dma-direction.h&gt;</div><div class='ctx'> #include &lt;linux/crc7.h&gt;</div><div class='ctx'> #include &lt;linux/crc-itu-t.h&gt;</div><div class='ctx'> #include &lt;linux/scatterlist.h&gt;</div><div class='hunk'>@@ -119,19 +119,14 @@ struct mmc_spi_host {</div><div class='ctx'> 	struct spi_transfer	status;</div><div class='ctx'> 	struct spi_message	readback;</div><div class='ctx'> </div><div class='del'>-	/* underlying DMA-aware controller, or null */</div><div class='del'>-	struct device		*dma_dev;</div><div class='del'>-</div><div class='ctx'> 	/* buffer used for commands and for message "overhead" */</div><div class='ctx'> 	struct scratch		*data;</div><div class='del'>-	dma_addr_t		data_dma;</div><div class='ctx'> </div><div class='ctx'> 	/* Specs say to write ones most of the time, even when the card</div><div class='ctx'> 	 * has no need to read its input data; and many cards won't care.</div><div class='ctx'> 	 * This is our source of those ones.</div><div class='ctx'> 	 */</div><div class='ctx'> 	void			*ones;</div><div class='del'>-	dma_addr_t		ones_dma;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -147,11 +142,8 @@ static inline int mmc_cs_off(struct mmc_spi_host *host)</div><div class='ctx'> 	return spi_setup(host-&gt;spi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int</div><div class='del'>-mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)</div><div class='add'>+static int mmc_spi_readbytes(struct mmc_spi_host *host, unsigned int len)</div><div class='ctx'> {</div><div class='del'>-	int status;</div><div class='del'>-</div><div class='ctx'> 	if (len &gt; sizeof(*host-&gt;data)) {</div><div class='ctx'> 		WARN_ON(1);</div><div class='ctx'> 		return -EIO;</div><div class='hunk'>@@ -159,19 +151,7 @@ mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)</div><div class='ctx'> </div><div class='ctx'> 	host-&gt;status.len = len;</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*host-&gt;data),</div><div class='del'>-				DMA_FROM_DEVICE);</div><div class='del'>-</div><div class='del'>-	status = spi_sync_locked(host-&gt;spi, &amp;host-&gt;readback);</div><div class='del'>-</div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*host-&gt;data),</div><div class='del'>-				DMA_FROM_DEVICE);</div><div class='del'>-</div><div class='del'>-	return status;</div><div class='add'>+	return spi_sync_locked(host-&gt;spi, &amp;host-&gt;readback);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,</div><div class='hunk'>@@ -506,23 +486,11 @@ mmc_spi_command_send(struct mmc_spi_host *host,</div><div class='ctx'> 	t = &amp;host-&gt;t;</div><div class='ctx'> 	memset(t, 0, sizeof(*t));</div><div class='ctx'> 	t-&gt;tx_buf = t-&gt;rx_buf = data-&gt;status;</div><div class='del'>-	t-&gt;tx_dma = t-&gt;rx_dma = host-&gt;data_dma;</div><div class='ctx'> 	t-&gt;len = cp - data-&gt;status;</div><div class='ctx'> 	t-&gt;cs_change = 1;</div><div class='ctx'> 	spi_message_add_tail(t, &amp;host-&gt;m);</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;dma_dev) {</div><div class='del'>-		host-&gt;m.is_dma_mapped = 1;</div><div class='del'>-		dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*host-&gt;data),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='del'>-	}</div><div class='ctx'> 	status = spi_sync_locked(host-&gt;spi, &amp;host-&gt;m);</div><div class='del'>-</div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*host-&gt;data),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='ctx'> 	if (status &lt; 0) {</div><div class='ctx'> 		dev_dbg(&amp;host-&gt;spi-&gt;dev, "  ... write returned %d\n", status);</div><div class='ctx'> 		cmd-&gt;error = status;</div><div class='hunk'>@@ -540,9 +508,6 @@ mmc_spi_command_send(struct mmc_spi_host *host,</div><div class='ctx'>  * We always provide TX data for data and CRC.  The MMC/SD protocol</div><div class='ctx'>  * requires us to write ones; but Linux defaults to writing zeroes;</div><div class='ctx'>  * so we explicitly initialize it to all ones on RX paths.</div><div class='del'>- *</div><div class='del'>- * We also handle DMA mapping, so the underlying SPI controller does</div><div class='del'>- * not need to (re)do it for each message.</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='ctx'> mmc_spi_setup_data_message(</div><div class='hunk'>@@ -552,11 +517,8 @@ mmc_spi_setup_data_message(</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_transfer	*t;</div><div class='ctx'> 	struct scratch		*scratch = host-&gt;data;</div><div class='del'>-	dma_addr_t		dma = host-&gt;data_dma;</div><div class='ctx'> </div><div class='ctx'> 	spi_message_init(&amp;host-&gt;m);</div><div class='del'>-	if (dma)</div><div class='del'>-		host-&gt;m.is_dma_mapped = 1;</div><div class='ctx'> </div><div class='ctx'> 	/* for reads, readblock() skips 0xff bytes before finding</div><div class='ctx'> 	 * the token; for writes, this transfer issues that token.</div><div class='hunk'>@@ -570,8 +532,6 @@ mmc_spi_setup_data_message(</div><div class='ctx'> 		else</div><div class='ctx'> 			scratch-&gt;data_token = SPI_TOKEN_SINGLE;</div><div class='ctx'> 		t-&gt;tx_buf = &amp;scratch-&gt;data_token;</div><div class='del'>-		if (dma)</div><div class='del'>-			t-&gt;tx_dma = dma + offsetof(struct scratch, data_token);</div><div class='ctx'> 		spi_message_add_tail(t, &amp;host-&gt;m);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -581,7 +541,6 @@ mmc_spi_setup_data_message(</div><div class='ctx'> 	t = &amp;host-&gt;t;</div><div class='ctx'> 	memset(t, 0, sizeof(*t));</div><div class='ctx'> 	t-&gt;tx_buf = host-&gt;ones;</div><div class='del'>-	t-&gt;tx_dma = host-&gt;ones_dma;</div><div class='ctx'> 	/* length and actual buffer info are written later */</div><div class='ctx'> 	spi_message_add_tail(t, &amp;host-&gt;m);</div><div class='ctx'> </div><div class='hunk'>@@ -591,14 +550,9 @@ mmc_spi_setup_data_message(</div><div class='ctx'> 	if (direction == DMA_TO_DEVICE) {</div><div class='ctx'> 		/* the actual CRC may get written later */</div><div class='ctx'> 		t-&gt;tx_buf = &amp;scratch-&gt;crc_val;</div><div class='del'>-		if (dma)</div><div class='del'>-			t-&gt;tx_dma = dma + offsetof(struct scratch, crc_val);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		t-&gt;tx_buf = host-&gt;ones;</div><div class='del'>-		t-&gt;tx_dma = host-&gt;ones_dma;</div><div class='ctx'> 		t-&gt;rx_buf = &amp;scratch-&gt;crc_val;</div><div class='del'>-		if (dma)</div><div class='del'>-			t-&gt;rx_dma = dma + offsetof(struct scratch, crc_val);</div><div class='ctx'> 	}</div><div class='ctx'> 	spi_message_add_tail(t, &amp;host-&gt;m);</div><div class='ctx'> </div><div class='hunk'>@@ -621,10 +575,7 @@ mmc_spi_setup_data_message(</div><div class='ctx'> 		memset(t, 0, sizeof(*t));</div><div class='ctx'> 		t-&gt;len = (direction == DMA_TO_DEVICE) ? sizeof(scratch-&gt;status) : 1;</div><div class='ctx'> 		t-&gt;tx_buf = host-&gt;ones;</div><div class='del'>-		t-&gt;tx_dma = host-&gt;ones_dma;</div><div class='ctx'> 		t-&gt;rx_buf = scratch-&gt;status;</div><div class='del'>-		if (dma)</div><div class='del'>-			t-&gt;rx_dma = dma + offsetof(struct scratch, status);</div><div class='ctx'> 		t-&gt;cs_change = 1;</div><div class='ctx'> 		spi_message_add_tail(t, &amp;host-&gt;m);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -653,23 +604,13 @@ mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,</div><div class='ctx'> </div><div class='ctx'> 	if (host-&gt;mmc-&gt;use_spi_crc)</div><div class='ctx'> 		scratch-&gt;crc_val = cpu_to_be16(crc_itu_t(0, t-&gt;tx_buf, t-&gt;len));</div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='ctx'> </div><div class='ctx'> 	status = spi_sync_locked(spi, &amp;host-&gt;m);</div><div class='del'>-</div><div class='ctx'> 	if (status != 0) {</div><div class='ctx'> 		dev_dbg(&amp;spi-&gt;dev, "write error (%d)\n", status);</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='del'>-</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Get the transmission data-response reply.  It must follow</div><div class='ctx'> 	 * immediately after the data block we transferred.  This reply</div><div class='hunk'>@@ -718,8 +659,6 @@ mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	t-&gt;tx_buf += t-&gt;len;</div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		t-&gt;tx_dma += t-&gt;len;</div><div class='ctx'> </div><div class='ctx'> 	/* Return when not busy.  If we didn't collect that status yet,</div><div class='ctx'> 	 * we'll need some more I/O.</div><div class='hunk'>@@ -783,30 +722,12 @@ mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,</div><div class='ctx'> 	}</div><div class='ctx'> 	leftover = status &lt;&lt; 1;</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;dma_dev) {</div><div class='del'>-		dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='del'>-		dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-				t-&gt;rx_dma, t-&gt;len,</div><div class='del'>-				DMA_FROM_DEVICE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	status = spi_sync_locked(spi, &amp;host-&gt;m);</div><div class='ctx'> 	if (status &lt; 0) {</div><div class='ctx'> 		dev_dbg(&amp;spi-&gt;dev, "read error %d\n", status);</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;dma_dev) {</div><div class='del'>-		dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-				host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='del'>-		dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-				t-&gt;rx_dma, t-&gt;len,</div><div class='del'>-				DMA_FROM_DEVICE);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (bitshift) {</div><div class='ctx'> 		/* Walk through the data and the crc and do</div><div class='ctx'> 		 * all the magic to get byte-aligned data.</div><div class='hunk'>@@ -841,8 +762,6 @@ mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	t-&gt;rx_buf += t-&gt;len;</div><div class='del'>-	if (host-&gt;dma_dev)</div><div class='del'>-		t-&gt;rx_dma += t-&gt;len;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -857,7 +776,6 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,</div><div class='ctx'> 		struct mmc_data *data, u32 blk_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_device	*spi = host-&gt;spi;</div><div class='del'>-	struct device		*dma_dev = host-&gt;dma_dev;</div><div class='ctx'> 	struct spi_transfer	*t;</div><div class='ctx'> 	enum dma_data_direction	direction = mmc_get_dma_dir(data);</div><div class='ctx'> 	struct scatterlist	*sg;</div><div class='hunk'>@@ -884,31 +802,8 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,</div><div class='ctx'> 	 */</div><div class='ctx'> 	for_each_sg(data-&gt;sg, sg, data-&gt;sg_len, n_sg) {</div><div class='ctx'> 		int			status = 0;</div><div class='del'>-		dma_addr_t		dma_addr = 0;</div><div class='ctx'> 		void			*kmap_addr;</div><div class='ctx'> 		unsigned		length = sg-&gt;length;</div><div class='del'>-		enum dma_data_direction	dir = direction;</div><div class='del'>-</div><div class='del'>-		/* set up dma mapping for controller drivers that might</div><div class='del'>-		 * use DMA ... though they may fall back to PIO</div><div class='del'>-		 */</div><div class='del'>-		if (dma_dev) {</div><div class='del'>-			/* never invalidate whole *shared* pages ... */</div><div class='del'>-			if ((sg-&gt;offset != 0 || length != PAGE_SIZE)</div><div class='del'>-					&amp;&amp; dir == DMA_FROM_DEVICE)</div><div class='del'>-				dir = DMA_BIDIRECTIONAL;</div><div class='del'>-</div><div class='del'>-			dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,</div><div class='del'>-						PAGE_SIZE, dir);</div><div class='del'>-			if (dma_mapping_error(dma_dev, dma_addr)) {</div><div class='del'>-				data-&gt;error = -EFAULT;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-			if (direction == DMA_TO_DEVICE)</div><div class='del'>-				t-&gt;tx_dma = dma_addr + sg-&gt;offset;</div><div class='del'>-			else</div><div class='del'>-				t-&gt;rx_dma = dma_addr + sg-&gt;offset;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		/* allow pio too; we don't allow highmem */</div><div class='ctx'> 		kmap_addr = kmap(sg_page(sg));</div><div class='hunk'>@@ -941,8 +836,6 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,</div><div class='ctx'> 		if (direction == DMA_FROM_DEVICE)</div><div class='ctx'> 			flush_dcache_page(sg_page(sg));</div><div class='ctx'> 		kunmap(sg_page(sg));</div><div class='del'>-		if (dma_dev)</div><div class='del'>-			dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);</div><div class='ctx'> </div><div class='ctx'> 		if (status &lt; 0) {</div><div class='ctx'> 			data-&gt;error = status;</div><div class='hunk'>@@ -977,21 +870,9 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,</div><div class='ctx'> 		scratch-&gt;status[0] = SPI_TOKEN_STOP_TRAN;</div><div class='ctx'> </div><div class='ctx'> 		host-&gt;early_status.tx_buf = host-&gt;early_status.rx_buf;</div><div class='del'>-		host-&gt;early_status.tx_dma = host-&gt;early_status.rx_dma;</div><div class='ctx'> 		host-&gt;early_status.len = statlen;</div><div class='ctx'> </div><div class='del'>-		if (host-&gt;dma_dev)</div><div class='del'>-			dma_sync_single_for_device(host-&gt;dma_dev,</div><div class='del'>-					host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-					DMA_BIDIRECTIONAL);</div><div class='del'>-</div><div class='ctx'> 		tmp = spi_sync_locked(spi, &amp;host-&gt;m);</div><div class='del'>-</div><div class='del'>-		if (host-&gt;dma_dev)</div><div class='del'>-			dma_sync_single_for_cpu(host-&gt;dma_dev,</div><div class='del'>-					host-&gt;data_dma, sizeof(*scratch),</div><div class='del'>-					DMA_BIDIRECTIONAL);</div><div class='del'>-</div><div class='ctx'> 		if (tmp &lt; 0) {</div><div class='ctx'> 			if (!data-&gt;error)</div><div class='ctx'> 				data-&gt;error = tmp;</div><div class='hunk'>@@ -1265,52 +1146,6 @@ mmc_spi_detect_irq(int irq, void *mmc)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_HAS_DMA</div><div class='del'>-static int mmc_spi_dma_alloc(struct mmc_spi_host *host)</div><div class='del'>-{</div><div class='del'>-	struct spi_device *spi = host-&gt;spi;</div><div class='del'>-	struct device *dev;</div><div class='del'>-</div><div class='del'>-	if (!spi-&gt;master-&gt;dev.parent-&gt;dma_mask)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	dev = spi-&gt;master-&gt;dev.parent;</div><div class='del'>-</div><div class='del'>-	host-&gt;ones_dma = dma_map_single(dev, host-&gt;ones, MMC_SPI_BLOCKSIZE,</div><div class='del'>-					DMA_TO_DEVICE);</div><div class='del'>-	if (dma_mapping_error(dev, host-&gt;ones_dma))</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	host-&gt;data_dma = dma_map_single(dev, host-&gt;data, sizeof(*host-&gt;data),</div><div class='del'>-					DMA_BIDIRECTIONAL);</div><div class='del'>-	if (dma_mapping_error(dev, host-&gt;data_dma)) {</div><div class='del'>-		dma_unmap_single(dev, host-&gt;ones_dma, MMC_SPI_BLOCKSIZE,</div><div class='del'>-				 DMA_TO_DEVICE);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dma_sync_single_for_cpu(dev, host-&gt;data_dma, sizeof(*host-&gt;data),</div><div class='del'>-				DMA_BIDIRECTIONAL);</div><div class='del'>-</div><div class='del'>-	host-&gt;dma_dev = dev;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mmc_spi_dma_free(struct mmc_spi_host *host)</div><div class='del'>-{</div><div class='del'>-	if (!host-&gt;dma_dev)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	dma_unmap_single(host-&gt;dma_dev, host-&gt;ones_dma, MMC_SPI_BLOCKSIZE,</div><div class='del'>-			 DMA_TO_DEVICE);</div><div class='del'>-	dma_unmap_single(host-&gt;dma_dev, host-&gt;data_dma,	sizeof(*host-&gt;data),</div><div class='del'>-			 DMA_BIDIRECTIONAL);</div><div class='del'>-}</div><div class='del'>-#else</div><div class='del'>-static inline int mmc_spi_dma_alloc(struct mmc_spi_host *host) { return 0; }</div><div class='del'>-static inline void mmc_spi_dma_free(struct mmc_spi_host *host) {}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> static int mmc_spi_probe(struct spi_device *spi)</div><div class='ctx'> {</div><div class='ctx'> 	void			*ones;</div><div class='hunk'>@@ -1322,7 +1157,7 @@ static int mmc_spi_probe(struct spi_device *spi)</div><div class='ctx'> 	/* We rely on full duplex transfers, mostly to reduce</div><div class='ctx'> 	 * per-transfer overheads (by making fewer transfers).</div><div class='ctx'> 	 */</div><div class='del'>-	if (spi-&gt;master-&gt;flags &amp; SPI_MASTER_HALF_DUPLEX)</div><div class='add'>+	if (spi-&gt;master-&gt;flags &amp; SPI_CONTROLLER_HALF_DUPLEX)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* MMC and SD specs only seem to care that sampling is on the</div><div class='hunk'>@@ -1402,24 +1237,17 @@ static int mmc_spi_probe(struct spi_device *spi)</div><div class='ctx'> 			host-&gt;powerup_msecs = 250;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* preallocate dma buffers */</div><div class='add'>+	/* Preallocate buffers */</div><div class='ctx'> 	host-&gt;data = kmalloc(sizeof(*host-&gt;data), GFP_KERNEL);</div><div class='ctx'> 	if (!host-&gt;data)</div><div class='ctx'> 		goto fail_nobuf1;</div><div class='ctx'> </div><div class='del'>-	status = mmc_spi_dma_alloc(host);</div><div class='del'>-	if (status)</div><div class='del'>-		goto fail_dma;</div><div class='del'>-</div><div class='ctx'> 	/* setup message for status/busy readback */</div><div class='ctx'> 	spi_message_init(&amp;host-&gt;readback);</div><div class='del'>-	host-&gt;readback.is_dma_mapped = (host-&gt;dma_dev != NULL);</div><div class='ctx'> </div><div class='ctx'> 	spi_message_add_tail(&amp;host-&gt;status, &amp;host-&gt;readback);</div><div class='ctx'> 	host-&gt;status.tx_buf = host-&gt;ones;</div><div class='del'>-	host-&gt;status.tx_dma = host-&gt;ones_dma;</div><div class='ctx'> 	host-&gt;status.rx_buf = &amp;host-&gt;data-&gt;status;</div><div class='del'>-	host-&gt;status.rx_dma = host-&gt;data_dma + offsetof(struct scratch, status);</div><div class='ctx'> 	host-&gt;status.cs_change = 1;</div><div class='ctx'> </div><div class='ctx'> 	/* register card detect irq */</div><div class='hunk'>@@ -1464,9 +1292,8 @@ static int mmc_spi_probe(struct spi_device *spi)</div><div class='ctx'> 	if (!status)</div><div class='ctx'> 		has_ro = true;</div><div class='ctx'> </div><div class='del'>-	dev_info(&amp;spi-&gt;dev, "SD/MMC host %s%s%s%s%s\n",</div><div class='add'>+	dev_info(&amp;spi-&gt;dev, "SD/MMC host %s%s%s%s\n",</div><div class='ctx'> 			dev_name(&amp;mmc-&gt;class_dev),</div><div class='del'>-			host-&gt;dma_dev ? "" : ", no DMA",</div><div class='ctx'> 			has_ro ? "" : ", no WP",</div><div class='ctx'> 			(host-&gt;pdata &amp;&amp; host-&gt;pdata-&gt;setpower)</div><div class='ctx'> 				? "" : ", no poweroff",</div><div class='hunk'>@@ -1477,8 +1304,6 @@ static int mmc_spi_probe(struct spi_device *spi)</div><div class='ctx'> fail_gpiod_request:</div><div class='ctx'> 	mmc_remove_host(mmc);</div><div class='ctx'> fail_glue_init:</div><div class='del'>-	mmc_spi_dma_free(host);</div><div class='del'>-fail_dma:</div><div class='ctx'> 	kfree(host-&gt;data);</div><div class='ctx'> fail_nobuf1:</div><div class='ctx'> 	mmc_spi_put_pdata(spi);</div><div class='hunk'>@@ -1500,7 +1325,6 @@ static void mmc_spi_remove(struct spi_device *spi)</div><div class='ctx'> </div><div class='ctx'> 	mmc_remove_host(mmc);</div><div class='ctx'> </div><div class='del'>-	mmc_spi_dma_free(host);</div><div class='ctx'> 	kfree(host-&gt;data);</div><div class='ctx'> 	kfree(host-&gt;ones);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c<br/>index e967cca7a16f..b790c3c3c8f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/mmci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmci.c</a></div><div class='hunk'>@@ -273,6 +273,7 @@ static struct variant_data variant_stm32_sdmmc = {</div><div class='ctx'> 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,</div><div class='ctx'> 	.stm32_idmabsize_mask	= GENMASK(12, 5),</div><div class='ctx'> 	.stm32_idmabsize_align	= BIT(5),</div><div class='add'>+	.supports_sdio_irq	= true,</div><div class='ctx'> 	.busy_timeout		= true,</div><div class='ctx'> 	.busy_detect		= true,</div><div class='ctx'> 	.busy_detect_flag	= MCI_STM32_BUSYD0,</div><div class='hunk'>@@ -300,6 +301,7 @@ static struct variant_data variant_stm32_sdmmcv2 = {</div><div class='ctx'> 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,</div><div class='ctx'> 	.stm32_idmabsize_mask	= GENMASK(16, 5),</div><div class='ctx'> 	.stm32_idmabsize_align	= BIT(5),</div><div class='add'>+	.supports_sdio_irq	= true,</div><div class='ctx'> 	.dma_lli		= true,</div><div class='ctx'> 	.busy_timeout		= true,</div><div class='ctx'> 	.busy_detect		= true,</div><div class='hunk'>@@ -328,6 +330,7 @@ static struct variant_data variant_stm32_sdmmcv3 = {</div><div class='ctx'> 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,</div><div class='ctx'> 	.stm32_idmabsize_mask	= GENMASK(16, 6),</div><div class='ctx'> 	.stm32_idmabsize_align	= BIT(6),</div><div class='add'>+	.supports_sdio_irq	= true,</div><div class='ctx'> 	.dma_lli		= true,</div><div class='ctx'> 	.busy_timeout		= true,</div><div class='ctx'> 	.busy_detect		= true,</div><div class='hunk'>@@ -421,8 +424,9 @@ void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)</div><div class='ctx'>  */</div><div class='ctx'> static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)</div><div class='ctx'> {</div><div class='del'>-	/* Keep busy mode in DPSM if enabled */</div><div class='del'>-	datactrl |= host-&gt;datactrl_reg &amp; host-&gt;variant-&gt;busy_dpsm_flag;</div><div class='add'>+	/* Keep busy mode in DPSM and SDIO mask if enabled */</div><div class='add'>+	datactrl |= host-&gt;datactrl_reg &amp; (host-&gt;variant-&gt;busy_dpsm_flag |</div><div class='add'>+					  host-&gt;variant-&gt;datactrl_mask_sdio);</div><div class='ctx'> </div><div class='ctx'> 	if (host-&gt;datactrl_reg != datactrl) {</div><div class='ctx'> 		host-&gt;datactrl_reg = datactrl;</div><div class='hunk'>@@ -1762,6 +1766,25 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmci_write_sdio_irq_bit(struct mmci_host *host, int enable)</div><div class='add'>+{</div><div class='add'>+	void __iomem *base = host-&gt;base;</div><div class='add'>+	u32 mask = readl_relaxed(base + MMCIMASK0);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);</div><div class='add'>+	else</div><div class='add'>+		writel_relaxed(mask &amp; ~MCI_ST_SDIOITMASK, base + MMCIMASK0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmci_signal_sdio_irq(struct mmci_host *host, u32 status)</div><div class='add'>+{</div><div class='add'>+	if (status &amp; MCI_ST_SDIOIT) {</div><div class='add'>+		mmci_write_sdio_irq_bit(host, 0);</div><div class='add'>+		sdio_signal_irq(host-&gt;mmc);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Handle completion of command and data transfers.</div><div class='ctx'>  */</div><div class='hunk'>@@ -1806,6 +1829,9 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)</div><div class='ctx'> 			mmci_data_irq(host, host-&gt;data, status);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		if (host-&gt;variant-&gt;supports_sdio_irq)</div><div class='add'>+			mmci_signal_sdio_irq(host, status);</div><div class='add'>+</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Busy detection has been handled by mmci_cmd_irq() above.</div><div class='ctx'> 		 * Clear the status bit to prevent polling in IRQ context.</div><div class='hunk'>@@ -2042,6 +2068,35 @@ static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mmci_enable_sdio_irq(struct mmc_host *mmc, int enable)</div><div class='add'>+{</div><div class='add'>+	struct mmci_host *host = mmc_priv(mmc);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		/* Keep the SDIO mode bit if SDIO irqs are enabled */</div><div class='add'>+		pm_runtime_get_sync(mmc_dev(mmc));</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;host-&gt;lock, flags);</div><div class='add'>+	mmci_write_sdio_irq_bit(host, enable);</div><div class='add'>+	spin_unlock_irqrestore(&amp;host-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	if (!enable) {</div><div class='add'>+		pm_runtime_mark_last_busy(mmc_dev(mmc));</div><div class='add'>+		pm_runtime_put_autosuspend(mmc_dev(mmc));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mmci_ack_sdio_irq(struct mmc_host *mmc)</div><div class='add'>+{</div><div class='add'>+	struct mmci_host *host = mmc_priv(mmc);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;host-&gt;lock, flags);</div><div class='add'>+	mmci_write_sdio_irq_bit(host, 1);</div><div class='add'>+	spin_unlock_irqrestore(&amp;host-&gt;lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct mmc_host_ops mmci_ops = {</div><div class='ctx'> 	.request	= mmci_request,</div><div class='ctx'> 	.pre_req	= mmci_pre_request,</div><div class='hunk'>@@ -2317,6 +2372,16 @@ static int mmci_probe(struct amba_device *dev,</div><div class='ctx'> 		mmc-&gt;caps |= MMC_CAP_WAIT_WHILE_BUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (variant-&gt;supports_sdio_irq &amp;&amp; host-&gt;mmc-&gt;caps &amp; MMC_CAP_SDIO_IRQ) {</div><div class='add'>+		mmc-&gt;caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;</div><div class='add'>+</div><div class='add'>+		mmci_ops.enable_sdio_irq = mmci_enable_sdio_irq;</div><div class='add'>+		mmci_ops.ack_sdio_irq	= mmci_ack_sdio_irq;</div><div class='add'>+</div><div class='add'>+		mmci_write_datactrlreg(host,</div><div class='add'>+				       host-&gt;variant-&gt;datactrl_mask_sdio);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Variants with mandatory busy timeout in HW needs R1B responses. */</div><div class='ctx'> 	if (variant-&gt;busy_timeout)</div><div class='ctx'> 		mmc-&gt;caps |= MMC_CAP_NEED_RSP_BUSY;</div><div class='head'>diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h<br/>index 34d9897c289b..a5eb4ced4d5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/mmci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/mmci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mmci.h</a></div><div class='hunk'>@@ -331,6 +331,7 @@ enum mmci_busy_state {</div><div class='ctx'>  *	       register.</div><div class='ctx'>  * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register</div><div class='ctx'>  * @dma_lli: true if variant has dma link list feature.</div><div class='add'>+ * @supports_sdio_irq: allow SD I/O card to interrupt the host</div><div class='ctx'>  * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.</div><div class='ctx'>  * @dma_flow_controller: use peripheral as flow controller for DMA.</div><div class='ctx'>  */</div><div class='hunk'>@@ -377,6 +378,7 @@ struct variant_data {</div><div class='ctx'> 	u32			start_err;</div><div class='ctx'> 	u32			opendrain;</div><div class='ctx'> 	u8			dma_lli:1;</div><div class='add'>+	bool			supports_sdio_irq;</div><div class='ctx'> 	u32			stm32_idmabsize_mask;</div><div class='ctx'> 	u32			stm32_idmabsize_align;</div><div class='ctx'> 	bool			dma_flow_controller;</div><div class='head'>diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c<br/>index 97f7c3d4be6e..1634b1f5d201 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/mtk-sd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/mtk-sd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/mtk-sd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/mtk-sd.c</a></div><div class='hunk'>@@ -252,12 +252,16 @@</div><div class='ctx'> </div><div class='ctx'> #define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */</div><div class='add'>+#define MSDC_PAD_TUNE_DATRRDLY2	  GENMASK(12, 8)	/* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */</div><div class='add'>+#define MSDC_PAD_TUNE_CMDRDLY2	  GENMASK(20, 16)	/* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */</div><div class='ctx'> #define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */</div><div class='add'>+#define MSDC_PAD_TUNE_RD2_SEL	  BIT(13)   /* RW */</div><div class='add'>+#define MSDC_PAD_TUNE_CMD2_SEL	  BIT(21)   /* RW */</div><div class='ctx'> </div><div class='ctx'> #define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */</div><div class='ctx'> #define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */</div><div class='hunk'>@@ -325,7 +329,9 @@</div><div class='ctx'> </div><div class='ctx'> #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */</div><div class='ctx'> </div><div class='del'>-#define PAD_DELAY_MAX	32 /* PAD delay cells */</div><div class='add'>+#define TUNING_REG2_FIXED_OFFEST	4</div><div class='add'>+#define PAD_DELAY_HALF	32 /* PAD delay cells */</div><div class='add'>+#define PAD_DELAY_FULL	64</div><div class='ctx'> /*--------------------------------------------------------------------------*/</div><div class='ctx'> /* Descriptor Structure                                                     */</div><div class='ctx'> /*--------------------------------------------------------------------------*/</div><div class='hunk'>@@ -461,6 +467,7 @@ struct msdc_host {</div><div class='ctx'> 	u32 hs400_ds_dly3;</div><div class='ctx'> 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */</div><div class='ctx'> 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */</div><div class='add'>+	u32 tuning_step;</div><div class='ctx'> 	bool hs400_cmd_resp_sel_rising;</div><div class='ctx'> 				 /* cmd response sample selection for HS400 */</div><div class='ctx'> 	bool hs400_mode;	/* current eMMC will run at hs400 mode */</div><div class='hunk'>@@ -1149,9 +1156,11 @@ static void msdc_recheck_sdio_irq(struct msdc_host *host)</div><div class='ctx'> </div><div class='ctx'> static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)</div><div class='ctx'> {</div><div class='del'>-	if (host-&gt;error)</div><div class='del'>-		dev_dbg(host-&gt;dev, "%s: cmd=%d arg=%08X; host-&gt;error=0x%08X\n",</div><div class='del'>-			__func__, cmd-&gt;opcode, cmd-&gt;arg, host-&gt;error);</div><div class='add'>+	if (host-&gt;error &amp;&amp;</div><div class='add'>+	    ((!mmc_op_tuning(cmd-&gt;opcode) &amp;&amp; !host-&gt;hs400_tuning) ||</div><div class='add'>+	     cmd-&gt;error == -ETIMEDOUT))</div><div class='add'>+		dev_warn(host-&gt;dev, "%s: cmd=%d arg=%08X; host-&gt;error=0x%08X\n",</div><div class='add'>+			 __func__, cmd-&gt;opcode, cmd-&gt;arg, host-&gt;error);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)</div><div class='hunk'>@@ -1615,7 +1624,7 @@ static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (cmd_err || dat_err) {</div><div class='del'>-		dev_err(host-&gt;dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",</div><div class='add'>+		dev_err(host-&gt;dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",</div><div class='ctx'> 			cmd_err, dat_err, intsts);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1780,10 +1789,20 @@ static void msdc_init_hw(struct msdc_host *host)</div><div class='ctx'> 				     DATA_K_VALUE_SEL);</div><div class='ctx'> 			sdr_set_bits(host-&gt;top_base + EMMC_TOP_CMD,</div><div class='ctx'> 				     PAD_CMD_RD_RXDLY_SEL);</div><div class='add'>+			if (host-&gt;tuning_step &gt; PAD_DELAY_HALF) {</div><div class='add'>+				sdr_set_bits(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='add'>+					     PAD_DAT_RD_RXDLY2_SEL);</div><div class='add'>+				sdr_set_bits(host-&gt;top_base + EMMC_TOP_CMD,</div><div class='add'>+					     PAD_CMD_RD_RXDLY2_SEL);</div><div class='add'>+			}</div><div class='ctx'> 		} else {</div><div class='ctx'> 			sdr_set_bits(host-&gt;base + tune_reg,</div><div class='ctx'> 				     MSDC_PAD_TUNE_RD_SEL |</div><div class='ctx'> 				     MSDC_PAD_TUNE_CMD_SEL);</div><div class='add'>+			if (host-&gt;tuning_step &gt; PAD_DELAY_HALF)</div><div class='add'>+				sdr_set_bits(host-&gt;base + tune_reg + TUNING_REG2_FIXED_OFFEST,</div><div class='add'>+					     MSDC_PAD_TUNE_RD2_SEL |</div><div class='add'>+					     MSDC_PAD_TUNE_CMD2_SEL);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* choose clock tune */</div><div class='hunk'>@@ -1925,24 +1944,24 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> 		msdc_set_mclk(host, ios-&gt;timing, ios-&gt;clock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u32 test_delay_bit(u32 delay, u32 bit)</div><div class='add'>+static u64 test_delay_bit(u64 delay, u32 bit)</div><div class='ctx'> {</div><div class='del'>-	bit %= PAD_DELAY_MAX;</div><div class='del'>-	return delay &amp; BIT(bit);</div><div class='add'>+	bit %= PAD_DELAY_FULL;</div><div class='add'>+	return delay &amp; BIT_ULL(bit);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int get_delay_len(u32 delay, u32 start_bit)</div><div class='add'>+static int get_delay_len(u64 delay, u32 start_bit)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; (PAD_DELAY_MAX - start_bit); i++) {</div><div class='add'>+	for (i = 0; i &lt; (PAD_DELAY_FULL - start_bit); i++) {</div><div class='ctx'> 		if (test_delay_bit(delay, start_bit + i) == 0)</div><div class='ctx'> 			return i;</div><div class='ctx'> 	}</div><div class='del'>-	return PAD_DELAY_MAX - start_bit;</div><div class='add'>+	return PAD_DELAY_FULL - start_bit;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)</div><div class='add'>+static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)</div><div class='ctx'> {</div><div class='ctx'> 	int start = 0, len = 0;</div><div class='ctx'> 	int start_final = 0, len_final = 0;</div><div class='hunk'>@@ -1950,28 +1969,28 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)</div><div class='ctx'> 	struct msdc_delay_phase delay_phase = { 0, };</div><div class='ctx'> </div><div class='ctx'> 	if (delay == 0) {</div><div class='del'>-		dev_err(host-&gt;dev, "phase error: [map:%x]\n", delay);</div><div class='add'>+		dev_err(host-&gt;dev, "phase error: [map:%016llx]\n", delay);</div><div class='ctx'> 		delay_phase.final_phase = final_phase;</div><div class='ctx'> 		return delay_phase;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	while (start &lt; PAD_DELAY_MAX) {</div><div class='add'>+	while (start &lt; PAD_DELAY_FULL) {</div><div class='ctx'> 		len = get_delay_len(delay, start);</div><div class='ctx'> 		if (len_final &lt; len) {</div><div class='ctx'> 			start_final = start;</div><div class='ctx'> 			len_final = len;</div><div class='ctx'> 		}</div><div class='ctx'> 		start += len ? len : 1;</div><div class='del'>-		if (len &gt;= 12 &amp;&amp; start_final &lt; 4)</div><div class='add'>+		if (!upper_32_bits(delay) &amp;&amp; len &gt;= 12 &amp;&amp; start_final &lt; 4)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* The rule is that to find the smallest delay cell */</div><div class='ctx'> 	if (start_final == 0)</div><div class='del'>-		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;</div><div class='add'>+		final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;</div><div class='ctx'> 	else</div><div class='del'>-		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;</div><div class='del'>-	dev_dbg(host-&gt;dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",</div><div class='add'>+		final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;</div><div class='add'>+	dev_dbg(host-&gt;dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",</div><div class='ctx'> 		delay, len_final, final_phase);</div><div class='ctx'> </div><div class='ctx'> 	delay_phase.maxlen = len_final;</div><div class='hunk'>@@ -1984,30 +2003,64 @@ static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tune_reg = host-&gt;dev_comp-&gt;pad_tune_reg;</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;top_base)</div><div class='del'>-		sdr_set_field(host-&gt;top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,</div><div class='del'>-			      value);</div><div class='del'>-	else</div><div class='del'>-		sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,</div><div class='del'>-			      value);</div><div class='add'>+	if (host-&gt;top_base) {</div><div class='add'>+		if (value &lt; PAD_DELAY_HALF) {</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);</div><div class='add'>+		} else {</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,</div><div class='add'>+				      PAD_DELAY_HALF - 1);</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,</div><div class='add'>+				      value - PAD_DELAY_HALF);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (value &lt; PAD_DELAY_HALF) {</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg + TUNING_REG2_FIXED_OFFEST,</div><div class='add'>+				      MSDC_PAD_TUNE_CMDRDLY2, 0);</div><div class='add'>+		} else {</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,</div><div class='add'>+				      PAD_DELAY_HALF - 1);</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg + TUNING_REG2_FIXED_OFFEST,</div><div class='add'>+				      MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)</div><div class='ctx'> {</div><div class='ctx'> 	u32 tune_reg = host-&gt;dev_comp-&gt;pad_tune_reg;</div><div class='ctx'> </div><div class='del'>-	if (host-&gt;top_base)</div><div class='del'>-		sdr_set_field(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='del'>-			      PAD_DAT_RD_RXDLY, value);</div><div class='del'>-	else</div><div class='del'>-		sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,</div><div class='del'>-			      value);</div><div class='add'>+	if (host-&gt;top_base) {</div><div class='add'>+		if (value &lt; PAD_DELAY_HALF) {</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='add'>+				      PAD_DAT_RD_RXDLY, value);</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='add'>+				      PAD_DAT_RD_RXDLY2, 0);</div><div class='add'>+		} else {</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='add'>+				      PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);</div><div class='add'>+			sdr_set_field(host-&gt;top_base + EMMC_TOP_CONTROL,</div><div class='add'>+				      PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (value &lt; PAD_DELAY_HALF) {</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg + TUNING_REG2_FIXED_OFFEST,</div><div class='add'>+				      MSDC_PAD_TUNE_DATRRDLY2, 0);</div><div class='add'>+		} else {</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,</div><div class='add'>+				      PAD_DELAY_HALF - 1);</div><div class='add'>+			sdr_set_field(host-&gt;base + tune_reg + TUNING_REG2_FIXED_OFFEST,</div><div class='add'>+				      MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> {</div><div class='ctx'> 	struct msdc_host *host = mmc_priv(mmc);</div><div class='del'>-	u32 rise_delay = 0, fall_delay = 0;</div><div class='add'>+	u64 rise_delay = 0, fall_delay = 0;</div><div class='ctx'> 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};</div><div class='ctx'> 	struct msdc_delay_phase internal_delay_phase;</div><div class='ctx'> 	u8 final_delay, final_maxlen;</div><div class='hunk'>@@ -2023,7 +2076,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 			      host-&gt;hs200_cmd_int_delay);</div><div class='ctx'> </div><div class='ctx'> 	sdr_clr_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='del'>-	for (i = 0 ; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_cmd_delay(host, i);</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Using the same parameters, it may sometimes pass the test,</div><div class='hunk'>@@ -2033,9 +2086,9 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 		for (j = 0; j &lt; 3; j++) {</div><div class='ctx'> 			mmc_send_tuning(mmc, opcode, &amp;cmd_err);</div><div class='ctx'> 			if (!cmd_err) {</div><div class='del'>-				rise_delay |= BIT(i);</div><div class='add'>+				rise_delay |= BIT_ULL(i);</div><div class='ctx'> 			} else {</div><div class='del'>-				rise_delay &amp;= ~BIT(i);</div><div class='add'>+				rise_delay &amp;= ~BIT_ULL(i);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2047,7 +2100,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 		goto skip_fall;</div><div class='ctx'> </div><div class='ctx'> 	sdr_set_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='del'>-	for (i = 0; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_cmd_delay(host, i);</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * Using the same parameters, it may sometimes pass the test,</div><div class='hunk'>@@ -2057,9 +2110,9 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 		for (j = 0; j &lt; 3; j++) {</div><div class='ctx'> 			mmc_send_tuning(mmc, opcode, &amp;cmd_err);</div><div class='ctx'> 			if (!cmd_err) {</div><div class='del'>-				fall_delay |= BIT(i);</div><div class='add'>+				fall_delay |= BIT_ULL(i);</div><div class='ctx'> 			} else {</div><div class='del'>-				fall_delay &amp;= ~BIT(i);</div><div class='add'>+				fall_delay &amp;= ~BIT_ULL(i);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2082,12 +2135,12 @@ skip_fall:</div><div class='ctx'> 	if (host-&gt;dev_comp-&gt;async_fifo || host-&gt;hs200_cmd_int_delay)</div><div class='ctx'> 		goto skip_internal;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		sdr_set_field(host-&gt;base + tune_reg,</div><div class='ctx'> 			      MSDC_PAD_TUNE_CMDRRDLY, i);</div><div class='ctx'> 		mmc_send_tuning(mmc, opcode, &amp;cmd_err);</div><div class='ctx'> 		if (!cmd_err)</div><div class='del'>-			internal_delay |= BIT(i);</div><div class='add'>+			internal_delay |= BIT_ULL(i);</div><div class='ctx'> 	}</div><div class='ctx'> 	dev_dbg(host-&gt;dev, "Final internal delay: 0x%x\n", internal_delay);</div><div class='ctx'> 	internal_delay_phase = get_best_delay(host, internal_delay);</div><div class='hunk'>@@ -2121,7 +2174,8 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 		sdr_clr_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='ctx'> 	else</div><div class='ctx'> 		sdr_set_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='del'>-	for (i = 0 ; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; PAD_DELAY_HALF; i++) {</div><div class='ctx'> 		sdr_set_field(host-&gt;base + PAD_CMD_TUNE,</div><div class='ctx'> 			      PAD_CMD_TUNE_RX_DLY3, i);</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -2151,7 +2205,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> {</div><div class='ctx'> 	struct msdc_host *host = mmc_priv(mmc);</div><div class='del'>-	u32 rise_delay = 0, fall_delay = 0;</div><div class='add'>+	u64 rise_delay = 0, fall_delay = 0;</div><div class='ctx'> 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};</div><div class='ctx'> 	u8 final_delay, final_maxlen;</div><div class='ctx'> 	int i, ret;</div><div class='hunk'>@@ -2160,11 +2214,11 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 		      host-&gt;latch_ck);</div><div class='ctx'> 	sdr_clr_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_DSPL);</div><div class='ctx'> 	sdr_clr_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_W_DSPL);</div><div class='del'>-	for (i = 0 ; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_data_delay(host, i);</div><div class='ctx'> 		ret = mmc_send_tuning(mmc, opcode, NULL);</div><div class='ctx'> 		if (!ret)</div><div class='del'>-			rise_delay |= BIT(i);</div><div class='add'>+			rise_delay |= BIT_ULL(i);</div><div class='ctx'> 	}</div><div class='ctx'> 	final_rise_delay = get_best_delay(host, rise_delay);</div><div class='ctx'> 	/* if rising edge has enough margin, then do not scan falling edge */</div><div class='hunk'>@@ -2174,11 +2228,11 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> </div><div class='ctx'> 	sdr_set_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_DSPL);</div><div class='ctx'> 	sdr_set_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_W_DSPL);</div><div class='del'>-	for (i = 0; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_data_delay(host, i);</div><div class='ctx'> 		ret = mmc_send_tuning(mmc, opcode, NULL);</div><div class='ctx'> 		if (!ret)</div><div class='del'>-			fall_delay |= BIT(i);</div><div class='add'>+			fall_delay |= BIT_ULL(i);</div><div class='ctx'> 	}</div><div class='ctx'> 	final_fall_delay = get_best_delay(host, fall_delay);</div><div class='ctx'> </div><div class='hunk'>@@ -2206,7 +2260,7 @@ skip_fall:</div><div class='ctx'> static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> {</div><div class='ctx'> 	struct msdc_host *host = mmc_priv(mmc);</div><div class='del'>-	u32 rise_delay = 0, fall_delay = 0;</div><div class='add'>+	u64 rise_delay = 0, fall_delay = 0;</div><div class='ctx'> 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};</div><div class='ctx'> 	u8 final_delay, final_maxlen;</div><div class='ctx'> 	int i, ret;</div><div class='hunk'>@@ -2217,12 +2271,12 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 	sdr_clr_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='ctx'> 	sdr_clr_bits(host-&gt;base + MSDC_IOCON,</div><div class='ctx'> 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);</div><div class='del'>-	for (i = 0 ; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_cmd_delay(host, i);</div><div class='ctx'> 		msdc_set_data_delay(host, i);</div><div class='ctx'> 		ret = mmc_send_tuning(mmc, opcode, NULL);</div><div class='ctx'> 		if (!ret)</div><div class='del'>-			rise_delay |= BIT(i);</div><div class='add'>+			rise_delay |= BIT_ULL(i);</div><div class='ctx'> 	}</div><div class='ctx'> 	final_rise_delay = get_best_delay(host, rise_delay);</div><div class='ctx'> 	/* if rising edge has enough margin, then do not scan falling edge */</div><div class='hunk'>@@ -2233,12 +2287,12 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> 	sdr_set_bits(host-&gt;base + MSDC_IOCON, MSDC_IOCON_RSPL);</div><div class='ctx'> 	sdr_set_bits(host-&gt;base + MSDC_IOCON,</div><div class='ctx'> 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);</div><div class='del'>-	for (i = 0; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; host-&gt;tuning_step; i++) {</div><div class='ctx'> 		msdc_set_cmd_delay(host, i);</div><div class='ctx'> 		msdc_set_data_delay(host, i);</div><div class='ctx'> 		ret = mmc_send_tuning(mmc, opcode, NULL);</div><div class='ctx'> 		if (!ret)</div><div class='del'>-			fall_delay |= BIT(i);</div><div class='add'>+			fall_delay |= BIT_ULL(i);</div><div class='ctx'> 	}</div><div class='ctx'> 	final_fall_delay = get_best_delay(host, fall_delay);</div><div class='ctx'> </div><div class='hunk'>@@ -2346,7 +2400,7 @@ static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	host-&gt;hs400_tuning = true;</div><div class='del'>-	for (i = 0; i &lt; PAD_DELAY_MAX; i++) {</div><div class='add'>+	for (i = 0; i &lt; PAD_DELAY_HALF; i++) {</div><div class='ctx'> 		if (host-&gt;top_base)</div><div class='ctx'> 			sdr_set_field(host-&gt;top_base + EMMC50_PAD_DS_TUNE,</div><div class='ctx'> 				      PAD_DS_DLY1, i);</div><div class='hunk'>@@ -2580,6 +2634,8 @@ static const struct cqhci_host_ops msdc_cmdq_ops = {</div><div class='ctx'> static void msdc_of_property_parse(struct platform_device *pdev,</div><div class='ctx'> 				   struct msdc_host *host)</div><div class='ctx'> {</div><div class='add'>+	struct mmc_host *mmc = mmc_from_priv(host);</div><div class='add'>+</div><div class='ctx'> 	of_property_read_u32(pdev-&gt;dev.of_node, "mediatek,latch-ck",</div><div class='ctx'> 			     &amp;host-&gt;latch_ck);</div><div class='ctx'> </div><div class='hunk'>@@ -2601,6 +2657,14 @@ static void msdc_of_property_parse(struct platform_device *pdev,</div><div class='ctx'> 	else</div><div class='ctx'> 		host-&gt;hs400_cmd_resp_sel_rising = false;</div><div class='ctx'> </div><div class='add'>+	if (of_property_read_u32(pdev-&gt;dev.of_node, "mediatek,tuning-step",</div><div class='add'>+				 &amp;host-&gt;tuning_step)) {</div><div class='add'>+		if (mmc-&gt;caps2 &amp; MMC_CAP2_NO_MMC)</div><div class='add'>+			host-&gt;tuning_step = PAD_DELAY_FULL;</div><div class='add'>+		else</div><div class='add'>+			host-&gt;tuning_step = PAD_DELAY_HALF;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (of_property_read_bool(pdev-&gt;dev.of_node,</div><div class='ctx'> 				  "supports-cqe"))</div><div class='ctx'> 		host-&gt;cqhci = true;</div><div class='head'>diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c<br/>index 87d78432a1e0..7dfe7c4e0077 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/rtsx_pci_sdmmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/rtsx_pci_sdmmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/rtsx_pci_sdmmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/rtsx_pci_sdmmc.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'>  *   Wei WANG &lt;wei_wang@realsil.com.cn&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/slab.h&gt;</div><div class='ctx'> #include &lt;linux/highmem.h&gt;</div><div class='hunk'>@@ -947,7 +948,7 @@ static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)</div><div class='ctx'> 	/* send at least 74 clocks */</div><div class='ctx'> 	rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);</div><div class='ctx'> </div><div class='del'>-	if (PCI_PID(pcr) == PID_5261) {</div><div class='add'>+	if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {</div><div class='ctx'> 		/*</div><div class='ctx'> 		 * If test mode is set switch to SD Express mandatorily,</div><div class='ctx'> 		 * this is only for factory testing.</div><div class='hunk'>@@ -1364,6 +1365,14 @@ static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> 	struct realtek_pci_sdmmc *host = mmc_priv(mmc);</div><div class='ctx'> 	struct rtsx_pcr *pcr = host-&gt;pcr;</div><div class='ctx'> </div><div class='add'>+	if (PCI_PID(pcr) == PID_5264) {</div><div class='add'>+		pcie_capability_clear_and_set_word(pcr-&gt;pci, PCI_EXP_LNKCTL2,</div><div class='add'>+				PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_2_5GT);</div><div class='add'>+		pci_write_config_byte(pcr-&gt;pci, 0x80e, 0x02);</div><div class='add'>+		pcie_capability_clear_and_set_word(pcr-&gt;pci, PCI_EXP_LNKCTL2,</div><div class='add'>+				PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_5_0GT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Set relink_time for changing to PCIe card */</div><div class='ctx'> 	relink_time = 0x8FFF;</div><div class='ctx'> </div><div class='hunk'>@@ -1379,6 +1388,12 @@ static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='ctx'> 	if (pcr-&gt;ops-&gt;disable_auto_blink)</div><div class='ctx'> 		pcr-&gt;ops-&gt;disable_auto_blink(pcr);</div><div class='ctx'> </div><div class='add'>+	if (PCI_PID(pcr) == PID_5264) {</div><div class='add'>+		rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,</div><div class='add'>+			RTS5264_CHIP_RST_N_SEL, RTS5264_CHIP_RST_N_SEL);</div><div class='add'>+		rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* For PCIe/NVMe mode can't enter delink issue */</div><div class='ctx'> 	pcr-&gt;hw_param.interrupt_en &amp;= ~(SD_INT_EN);</div><div class='ctx'> 	rtsx_pci_writel(pcr, RTSX_BIER, pcr-&gt;hw_param.interrupt_en);</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c<br/>index c23251bb95f3..9053526fa212 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-brcmstb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-brcmstb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-brcmstb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-brcmstb.c</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='ctx'> #include &lt;linux/mmc/host.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='hunk'>@@ -44,8 +45,13 @@ struct brcmstb_match_priv {</div><div class='ctx'> </div><div class='ctx'> static inline void enable_clock_gating(struct sdhci_host *host)</div><div class='ctx'> {</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='add'>+	if (!(priv-&gt;flags &amp; BRCMSTB_PRIV_FLAGS_GATE_CLOCK))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	reg = sdhci_readl(host, SDHCI_VENDOR);</div><div class='ctx'> 	reg |= SDHCI_VENDOR_GATE_SDCLK_EN;</div><div class='ctx'> 	sdhci_writel(host, reg, SDHCI_VENDOR);</div><div class='hunk'>@@ -53,14 +59,53 @@ static inline void enable_clock_gating(struct sdhci_host *host)</div><div class='ctx'> </div><div class='ctx'> static void brcmstb_reset(struct sdhci_host *host, u8 mask)</div><div class='ctx'> {</div><div class='del'>-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='del'>-	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='del'>-</div><div class='ctx'> 	sdhci_and_cqhci_reset(host, mask);</div><div class='ctx'> </div><div class='ctx'> 	/* Reset will clear this, so re-enable it */</div><div class='del'>-	if (priv-&gt;flags &amp; BRCMSTB_PRIV_FLAGS_GATE_CLOCK)</div><div class='del'>-		enable_clock_gating(host);</div><div class='add'>+	enable_clock_gating(host);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)</div><div class='add'>+{</div><div class='add'>+	u32 new_mask = (mask &amp;  (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) &lt;&lt; 24;</div><div class='add'>+	int ret;</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall</div><div class='add'>+	 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA</div><div class='add'>+	 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register</div><div class='add'>+	 */</div><div class='add'>+	new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;</div><div class='add'>+	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);</div><div class='add'>+	sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);</div><div class='add'>+</div><div class='add'>+	reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);</div><div class='add'>+</div><div class='add'>+	ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg &amp; mask),</div><div class='add'>+				       10, 10000, false,</div><div class='add'>+				       host, SDHCI_SOFTWARE_RESET);</div><div class='add'>+</div><div class='add'>+	if (ret) {</div><div class='add'>+		pr_err("%s: Reset 0x%x never completed.\n",</div><div class='add'>+		       mmc_hostname(host-&gt;mmc), (int)mask);</div><div class='add'>+		sdhci_err_stats_inc(host, CTRL_TIMEOUT);</div><div class='add'>+		sdhci_dumpregs(host);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)</div><div class='add'>+{</div><div class='add'>+	/* take care of RESET_ALL as usual */</div><div class='add'>+	if (mask &amp; SDHCI_RESET_ALL)</div><div class='add'>+		sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);</div><div class='add'>+</div><div class='add'>+	/* cmd and/or data treated differently on this core */</div><div class='add'>+	if (mask &amp; (SDHCI_RESET_CMD | SDHCI_RESET_DATA))</div><div class='add'>+		brcmstb_sdhci_reset_cmd_data(host, mask);</div><div class='add'>+</div><div class='add'>+	/* Reset will clear this, so re-enable it */</div><div class='add'>+	enable_clock_gating(host);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)</div><div class='hunk'>@@ -162,6 +207,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = {</div><div class='ctx'> 	.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = {</div><div class='add'>+	.set_clock = sdhci_brcmstb_set_clock,</div><div class='add'>+	.set_bus_width = sdhci_set_bus_width,</div><div class='add'>+	.reset = brcmstb_reset_74165b0,</div><div class='add'>+	.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static struct brcmstb_match_priv match_priv_7425 = {</div><div class='ctx'> 	.flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |</div><div class='ctx'> 	BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,</div><div class='hunk'>@@ -179,10 +231,17 @@ static const struct brcmstb_match_priv match_priv_7216 = {</div><div class='ctx'> 	.ops = &amp;sdhci_brcmstb_ops_7216,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct brcmstb_match_priv match_priv_74165b0 = {</div><div class='add'>+	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,</div><div class='add'>+	.hs400es = sdhci_brcmstb_hs400es,</div><div class='add'>+	.ops = &amp;sdhci_brcmstb_ops_74165b0,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {</div><div class='ctx'> 	{ .compatible = "brcm,bcm7425-sdhci", .data = &amp;match_priv_7425 },</div><div class='ctx'> 	{ .compatible = "brcm,bcm7445-sdhci", .data = &amp;match_priv_7445 },</div><div class='ctx'> 	{ .compatible = "brcm,bcm7216-sdhci", .data = &amp;match_priv_7216 },</div><div class='add'>+	{ .compatible = "brcm,bcm74165b0-sdhci", .data = &amp;match_priv_74165b0 },</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c<br/>index 3a3bae6948a8..a1f57af6acfb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-of-dwcmshc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-of-dwcmshc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-of-dwcmshc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-of-dwcmshc.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/acpi.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include &lt;linux/iopoll.h&gt;</div><div class='hunk'>@@ -35,6 +36,21 @@</div><div class='ctx'> #define DWCMSHC_CARD_IS_EMMC		BIT(0)</div><div class='ctx'> #define DWCMSHC_ENHANCED_STROBE		BIT(8)</div><div class='ctx'> #define DWCMSHC_EMMC_ATCTRL		0x40</div><div class='add'>+/* Tuning and auto-tuning fields in AT_CTRL_R control register */</div><div class='add'>+#define AT_CTRL_AT_EN			BIT(0) /* autotuning is enabled */</div><div class='add'>+#define AT_CTRL_CI_SEL			BIT(1) /* interval to drive center phase select */</div><div class='add'>+#define AT_CTRL_SWIN_TH_EN		BIT(2) /* sampling window threshold enable */</div><div class='add'>+#define AT_CTRL_RPT_TUNE_ERR		BIT(3) /* enable reporting framing errors */</div><div class='add'>+#define AT_CTRL_SW_TUNE_EN		BIT(4) /* enable software managed tuning */</div><div class='add'>+#define AT_CTRL_WIN_EDGE_SEL_MASK	GENMASK(11, 8) /* bits [11:8] */</div><div class='add'>+#define AT_CTRL_WIN_EDGE_SEL		0xf /* sampling window edge select */</div><div class='add'>+#define AT_CTRL_TUNE_CLK_STOP_EN	BIT(16) /* clocks stopped during phase code change */</div><div class='add'>+#define AT_CTRL_PRE_CHANGE_DLY_MASK	GENMASK(18, 17) /* bits [18:17] */</div><div class='add'>+#define AT_CTRL_PRE_CHANGE_DLY		0x1  /* 2-cycle latency */</div><div class='add'>+#define AT_CTRL_POST_CHANGE_DLY_MASK	GENMASK(20, 19) /* bits [20:19] */</div><div class='add'>+#define AT_CTRL_POST_CHANGE_DLY		0x3  /* 4-cycle latency */</div><div class='add'>+#define AT_CTRL_SWIN_TH_VAL_MASK	GENMASK(31, 24) /* bits [31:24] */</div><div class='add'>+#define AT_CTRL_SWIN_TH_VAL		0x9  /* sampling window threshold */</div><div class='ctx'> </div><div class='ctx'> /* Rockchip specific Registers */</div><div class='ctx'> #define DWCMSHC_EMMC_DLL_CTRL		0x800</div><div class='hunk'>@@ -72,6 +88,82 @@</div><div class='ctx'> 	(((x) &amp; DWCMSHC_EMMC_DLL_TIMEOUT) == 0))</div><div class='ctx'> #define RK35xx_MAX_CLKS 3</div><div class='ctx'> </div><div class='add'>+/* PHY register area pointer */</div><div class='add'>+#define DWC_MSHC_PTR_PHY_R	0x300</div><div class='add'>+</div><div class='add'>+/* PHY general configuration */</div><div class='add'>+#define PHY_CNFG_R		(DWC_MSHC_PTR_PHY_R + 0x00)</div><div class='add'>+#define PHY_CNFG_RSTN_DEASSERT	0x1  /* Deassert PHY reset */</div><div class='add'>+#define PHY_CNFG_PAD_SP_MASK	GENMASK(19, 16) /* bits [19:16] */</div><div class='add'>+#define PHY_CNFG_PAD_SP		0x0c /* PMOS TX drive strength */</div><div class='add'>+#define PHY_CNFG_PAD_SN_MASK	GENMASK(23, 20) /* bits [23:20] */</div><div class='add'>+#define PHY_CNFG_PAD_SN		0x0c /* NMOS TX drive strength */</div><div class='add'>+</div><div class='add'>+/* PHY command/response pad settings */</div><div class='add'>+#define PHY_CMDPAD_CNFG_R	(DWC_MSHC_PTR_PHY_R + 0x04)</div><div class='add'>+</div><div class='add'>+/* PHY data pad settings */</div><div class='add'>+#define PHY_DATAPAD_CNFG_R	(DWC_MSHC_PTR_PHY_R + 0x06)</div><div class='add'>+</div><div class='add'>+/* PHY clock pad settings */</div><div class='add'>+#define PHY_CLKPAD_CNFG_R	(DWC_MSHC_PTR_PHY_R + 0x08)</div><div class='add'>+</div><div class='add'>+/* PHY strobe pad settings */</div><div class='add'>+#define PHY_STBPAD_CNFG_R	(DWC_MSHC_PTR_PHY_R + 0x0a)</div><div class='add'>+</div><div class='add'>+/* PHY reset pad settings */</div><div class='add'>+#define PHY_RSTNPAD_CNFG_R	(DWC_MSHC_PTR_PHY_R + 0x0c)</div><div class='add'>+</div><div class='add'>+/* Bitfields are common for all pad settings */</div><div class='add'>+#define PHY_PAD_RXSEL_1V8		0x1 /* Receiver type select for 1.8V */</div><div class='add'>+#define PHY_PAD_RXSEL_3V3		0x2 /* Receiver type select for 3.3V */</div><div class='add'>+</div><div class='add'>+#define PHY_PAD_WEAKPULL_MASK		GENMASK(4, 3) /* bits [4:3] */</div><div class='add'>+#define PHY_PAD_WEAKPULL_PULLUP		0x1 /* Weak pull up enabled */</div><div class='add'>+#define PHY_PAD_WEAKPULL_PULLDOWN	0x2 /* Weak pull down enabled */</div><div class='add'>+</div><div class='add'>+#define PHY_PAD_TXSLEW_CTRL_P_MASK	GENMASK(8, 5) /* bits [8:5] */</div><div class='add'>+#define PHY_PAD_TXSLEW_CTRL_P		0x3 /* Slew control for P-Type pad TX */</div><div class='add'>+#define PHY_PAD_TXSLEW_CTRL_N_MASK	GENMASK(12, 9) /* bits [12:9] */</div><div class='add'>+#define PHY_PAD_TXSLEW_CTRL_N		0x3 /* Slew control for N-Type pad TX */</div><div class='add'>+</div><div class='add'>+/* PHY CLK delay line settings */</div><div class='add'>+#define PHY_SDCLKDL_CNFG_R		(DWC_MSHC_PTR_PHY_R + 0x1d)</div><div class='add'>+#define PHY_SDCLKDL_CNFG_UPDATE	BIT(4) /* set before writing to SDCLKDL_DC */</div><div class='add'>+</div><div class='add'>+/* PHY CLK delay line delay code */</div><div class='add'>+#define PHY_SDCLKDL_DC_R		(DWC_MSHC_PTR_PHY_R + 0x1e)</div><div class='add'>+#define PHY_SDCLKDL_DC_INITIAL		0x40 /* initial delay code */</div><div class='add'>+#define PHY_SDCLKDL_DC_DEFAULT		0x32 /* default delay code */</div><div class='add'>+#define PHY_SDCLKDL_DC_HS400		0x18 /* delay code for HS400 mode */</div><div class='add'>+</div><div class='add'>+/* PHY drift_cclk_rx delay line configuration setting */</div><div class='add'>+#define PHY_ATDL_CNFG_R			(DWC_MSHC_PTR_PHY_R + 0x21)</div><div class='add'>+#define PHY_ATDL_CNFG_INPSEL_MASK	GENMASK(3, 2) /* bits [3:2] */</div><div class='add'>+#define PHY_ATDL_CNFG_INPSEL		0x3 /* delay line input source */</div><div class='add'>+</div><div class='add'>+/* PHY DLL control settings */</div><div class='add'>+#define PHY_DLL_CTRL_R			(DWC_MSHC_PTR_PHY_R + 0x24)</div><div class='add'>+#define PHY_DLL_CTRL_DISABLE		0x0 /* PHY DLL is enabled */</div><div class='add'>+#define PHY_DLL_CTRL_ENABLE		0x1 /* PHY DLL is disabled */</div><div class='add'>+</div><div class='add'>+/* PHY DLL  configuration register 1 */</div><div class='add'>+#define PHY_DLL_CNFG1_R			(DWC_MSHC_PTR_PHY_R + 0x25)</div><div class='add'>+#define PHY_DLL_CNFG1_SLVDLY_MASK	GENMASK(5, 4) /* bits [5:4] */</div><div class='add'>+#define PHY_DLL_CNFG1_SLVDLY		0x2 /* DLL slave update delay input */</div><div class='add'>+#define PHY_DLL_CNFG1_WAITCYCLE		0x5 /* DLL wait cycle input */</div><div class='add'>+</div><div class='add'>+/* PHY DLL configuration register 2 */</div><div class='add'>+#define PHY_DLL_CNFG2_R			(DWC_MSHC_PTR_PHY_R + 0x26)</div><div class='add'>+#define PHY_DLL_CNFG2_JUMPSTEP		0xa /* DLL jump step input */</div><div class='add'>+</div><div class='add'>+/* PHY DLL master and slave delay line configuration settings */</div><div class='add'>+#define PHY_DLLDL_CNFG_R		(DWC_MSHC_PTR_PHY_R + 0x28)</div><div class='add'>+#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK	GENMASK(6, 5) /* bits [6:5] */</div><div class='add'>+#define PHY_DLLDL_CNFG_SLV_INPSEL	0x3 /* clock source select for slave DL */</div><div class='add'>+</div><div class='add'>+#define FLAG_IO_FIXED_1V8	BIT(0)</div><div class='add'>+</div><div class='ctx'> #define BOUNDARY_OK(addr, len) \</div><div class='ctx'> 	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))</div><div class='ctx'> </div><div class='hunk'>@@ -92,6 +184,8 @@ struct dwcmshc_priv {</div><div class='ctx'> 	struct clk	*bus_clk;</div><div class='ctx'> 	int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */</div><div class='ctx'> 	void *priv; /* pointer to SoC private stuff */</div><div class='add'>+	u16 delay_line;</div><div class='add'>+	u16 flags;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='hunk'>@@ -157,6 +251,127 @@ static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)</div><div class='ctx'> 	sdhci_request(mmc, mrq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	/* deassert phy reset &amp; set tx drive strength */</div><div class='add'>+	val = PHY_CNFG_RSTN_DEASSERT;</div><div class='add'>+	val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);</div><div class='add'>+	val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);</div><div class='add'>+	sdhci_writel(host, val, PHY_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* disable delay line */</div><div class='add'>+	sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* set delay line */</div><div class='add'>+	sdhci_writeb(host, priv-&gt;delay_line, PHY_SDCLKDL_DC_R);</div><div class='add'>+	sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);</div><div class='add'>+</div><div class='add'>+	/* enable delay lane */</div><div class='add'>+	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+	val &amp;= ~(PHY_SDCLKDL_CNFG_UPDATE);</div><div class='add'>+	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* configure phy pads */</div><div class='add'>+	val = PHY_PAD_RXSEL_1V8;</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);</div><div class='add'>+	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);</div><div class='add'>+	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	val = PHY_PAD_RXSEL_1V8;</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* enable data strobe mode */</div><div class='add'>+	sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),</div><div class='add'>+		     PHY_DLLDL_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* enable phy dll */</div><div class='add'>+	sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	/* deassert phy reset &amp; set tx drive strength */</div><div class='add'>+	val = PHY_CNFG_RSTN_DEASSERT;</div><div class='add'>+	val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);</div><div class='add'>+	val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);</div><div class='add'>+	sdhci_writel(host, val, PHY_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* disable delay line */</div><div class='add'>+	sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* set delay line */</div><div class='add'>+	sdhci_writeb(host, priv-&gt;delay_line, PHY_SDCLKDL_DC_R);</div><div class='add'>+	sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);</div><div class='add'>+</div><div class='add'>+	/* enable delay lane */</div><div class='add'>+	val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+	val &amp;= ~(PHY_SDCLKDL_CNFG_UPDATE);</div><div class='add'>+	sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* configure phy pads */</div><div class='add'>+	val = PHY_PAD_RXSEL_3V3;</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);</div><div class='add'>+	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);</div><div class='add'>+	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	val = PHY_PAD_RXSEL_3V3;</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);</div><div class='add'>+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);</div><div class='add'>+	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);</div><div class='add'>+</div><div class='add'>+	/* enable phy dll */</div><div class='add'>+	sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void th1520_sdhci_set_phy(struct sdhci_host *host)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+	u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;</div><div class='add'>+	u16 emmc_ctrl;</div><div class='add'>+</div><div class='add'>+	/* Before power on, set PHY configs */</div><div class='add'>+	if (priv-&gt;flags &amp; FLAG_IO_FIXED_1V8)</div><div class='add'>+		dwcmshc_phy_1_8v_init(host);</div><div class='add'>+	else</div><div class='add'>+		dwcmshc_phy_3_3v_init(host);</div><div class='add'>+</div><div class='add'>+	if ((host-&gt;mmc-&gt;caps2 &amp; emmc_caps) == emmc_caps) {</div><div class='add'>+		emmc_ctrl = sdhci_readw(host, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);</div><div class='add'>+		emmc_ctrl |= DWCMSHC_CARD_IS_EMMC;</div><div class='add'>+		sdhci_writew(host, emmc_ctrl, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |</div><div class='add'>+		     PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,</div><div class='ctx'> 				      unsigned int timing)</div><div class='ctx'> {</div><div class='hunk'>@@ -189,9 +404,25 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,</div><div class='ctx'> 		ctrl_2 |= DWCMSHC_CTRL_HS400;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (priv-&gt;flags &amp; FLAG_IO_FIXED_1V8)</div><div class='add'>+		ctrl_2 |= SDHCI_CTRL_VDD_180;</div><div class='ctx'> 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void th1520_set_uhs_signaling(struct sdhci_host *host,</div><div class='add'>+				     unsigned int timing)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+</div><div class='add'>+	dwcmshc_set_uhs_signaling(host, timing);</div><div class='add'>+	if (timing == MMC_TIMING_MMC_HS400)</div><div class='add'>+		priv-&gt;delay_line = PHY_SDCLKDL_DC_HS400;</div><div class='add'>+	else</div><div class='add'>+		sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);</div><div class='add'>+	th1520_sdhci_set_phy(host);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,</div><div class='ctx'> 					  struct mmc_ios *ios)</div><div class='ctx'> {</div><div class='hunk'>@@ -338,6 +569,79 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)</div><div class='ctx'> 	sdhci_reset(host, mask);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+	u32 val = 0;</div><div class='add'>+</div><div class='add'>+	if (host-&gt;flags &amp; SDHCI_HS400_TUNING)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),</div><div class='add'>+		     PHY_ATDL_CNFG_R);</div><div class='add'>+	val = sdhci_readl(host, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * configure tuning settings:</div><div class='add'>+	 *  - center phase select code driven in block gap interval</div><div class='add'>+	 *  - disable reporting of framing errors</div><div class='add'>+	 *  - disable software managed tuning</div><div class='add'>+	 *  - disable user selection of sampling window edges,</div><div class='add'>+	 *    instead tuning calculated edges are used</div><div class='add'>+	 */</div><div class='add'>+	val &amp;= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |</div><div class='add'>+		 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * configure tuning settings:</div><div class='add'>+	 *  - enable auto-tuning</div><div class='add'>+	 *  - enable sampling window threshold</div><div class='add'>+	 *  - stop clocks during phase code change</div><div class='add'>+	 *  - set max latency in cycles between tx and rx clocks</div><div class='add'>+	 *  - set max latency in cycles to switch output phase</div><div class='add'>+	 *  - set max sampling window threshold value</div><div class='add'>+	 */</div><div class='add'>+	val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;</div><div class='add'>+	val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);</div><div class='add'>+	val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);</div><div class='add'>+	val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);</div><div class='add'>+</div><div class='add'>+	sdhci_writel(host, val, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);</div><div class='add'>+	val = sdhci_readl(host, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);</div><div class='add'>+</div><div class='add'>+	/* perform tuning */</div><div class='add'>+	sdhci_start_tuning(host);</div><div class='add'>+	host-&gt;tuning_err = __sdhci_execute_tuning(host, opcode);</div><div class='add'>+	if (host-&gt;tuning_err) {</div><div class='add'>+		/* disable auto-tuning upon tuning error */</div><div class='add'>+		val &amp;= ~AT_CTRL_AT_EN;</div><div class='add'>+		sdhci_writel(host, val, priv-&gt;vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);</div><div class='add'>+		dev_err(mmc_dev(host-&gt;mmc), "tuning failed: %d\n", host-&gt;tuning_err);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+	sdhci_end_tuning(host);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)</div><div class='add'>+{</div><div class='add'>+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);</div><div class='add'>+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='add'>+	u16 ctrl_2;</div><div class='add'>+</div><div class='add'>+	sdhci_reset(host, mask);</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;flags &amp; FLAG_IO_FIXED_1V8) {</div><div class='add'>+		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);</div><div class='add'>+		if (!(ctrl_2 &amp; SDHCI_CTRL_VDD_180)) {</div><div class='add'>+			ctrl_2 |= SDHCI_CTRL_VDD_180;</div><div class='add'>+			sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct sdhci_ops sdhci_dwcmshc_ops = {</div><div class='ctx'> 	.set_clock		= sdhci_set_clock,</div><div class='ctx'> 	.set_bus_width		= sdhci_set_bus_width,</div><div class='hunk'>@@ -356,6 +660,17 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {</div><div class='ctx'> 	.adma_write_desc	= dwcmshc_adma_write_desc,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {</div><div class='add'>+	.set_clock		= sdhci_set_clock,</div><div class='add'>+	.set_bus_width		= sdhci_set_bus_width,</div><div class='add'>+	.set_uhs_signaling	= th1520_set_uhs_signaling,</div><div class='add'>+	.get_max_clock		= dwcmshc_get_max_clock,</div><div class='add'>+	.reset			= th1520_sdhci_reset,</div><div class='add'>+	.adma_write_desc	= dwcmshc_adma_write_desc,</div><div class='add'>+	.voltage_switch		= dwcmshc_phy_1_8v_init,</div><div class='add'>+	.platform_execute_tuning = &amp;th1520_execute_tuning,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {</div><div class='ctx'> 	.ops = &amp;sdhci_dwcmshc_ops,</div><div class='ctx'> 	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,</div><div class='hunk'>@@ -379,6 +694,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {</div><div class='ctx'> 		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {</div><div class='add'>+	.ops = &amp;sdhci_dwcmshc_th1520_ops,</div><div class='add'>+	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,</div><div class='add'>+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -447,6 +768,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {</div><div class='ctx'> 		.compatible = "snps,dwcmshc-sdhci",</div><div class='ctx'> 		.data = &amp;sdhci_dwcmshc_pdata,</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+		.compatible = "thead,th1520-dwcmshc",</div><div class='add'>+		.data = &amp;sdhci_dwcmshc_th1520_pdata,</div><div class='add'>+	},</div><div class='ctx'> 	{},</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);</div><div class='hunk'>@@ -542,6 +867,30 @@ static int dwcmshc_probe(struct platform_device *pdev)</div><div class='ctx'> 			goto err_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (pltfm_data == &amp;sdhci_dwcmshc_th1520_pdata) {</div><div class='add'>+		priv-&gt;delay_line = PHY_SDCLKDL_DC_DEFAULT;</div><div class='add'>+</div><div class='add'>+		if (device_property_read_bool(dev, "mmc-ddr-1_8v") ||</div><div class='add'>+		    device_property_read_bool(dev, "mmc-hs200-1_8v") ||</div><div class='add'>+		    device_property_read_bool(dev, "mmc-hs400-1_8v"))</div><div class='add'>+			priv-&gt;flags |= FLAG_IO_FIXED_1V8;</div><div class='add'>+		else</div><div class='add'>+			priv-&gt;flags &amp;= ~FLAG_IO_FIXED_1V8;</div><div class='add'>+</div><div class='add'>+		/*</div><div class='add'>+		 * start_signal_voltage_switch() will try 3.3V first</div><div class='add'>+		 * then 1.8V. Use SDHCI_SIGNALING_180 rather than</div><div class='add'>+		 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V</div><div class='add'>+		 * in sdhci_start_signal_voltage_switch().</div><div class='add'>+		 */</div><div class='add'>+		if (priv-&gt;flags &amp; FLAG_IO_FIXED_1V8) {</div><div class='add'>+			host-&gt;flags &amp;= ~SDHCI_SIGNALING_330;</div><div class='add'>+			host-&gt;flags |=  SDHCI_SIGNALING_180;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		sdhci_enable_v4_mode(host);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_ACPI</div><div class='ctx'> 	if (pltfm_data == &amp;sdhci_dwcmshc_bf3_pdata)</div><div class='ctx'> 		sdhci_enable_v4_mode(host);</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c<br/>index 1e0bc7bace1b..e78faef67d7a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-omap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-omap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-omap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-omap.c</a></div><div class='hunk'>@@ -1,5 +1,5 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-/**</div><div class='add'>+/*</div><div class='ctx'>  * SDHCI Controller driver for TI's OMAP SoCs</div><div class='ctx'>  *</div><div class='ctx'>  * Copyright (C) 2017 Texas Instruments</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c<br/>index d8a991b349a8..77911a57b12c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-pci-gli.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-pci-gli.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-pci-gli.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-pci-gli.c</a></div><div class='hunk'>@@ -1189,6 +1189,32 @@ static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,</div><div class='ctx'> 	sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot,</div><div class='add'>+					      bool enable)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = slot-&gt;chip-&gt;pdev;</div><div class='add'>+	u32 value;</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &amp;value);</div><div class='add'>+	value &amp;= ~GLI_9763E_VHS_REV;</div><div class='add'>+	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);</div><div class='add'>+	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &amp;value);</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		value &amp;= ~GLI_9763E_CFG_LPSN_DIS;</div><div class='add'>+	else</div><div class='add'>+		value |= GLI_9763E_CFG_LPSN_DIS;</div><div class='add'>+</div><div class='add'>+	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);</div><div class='add'>+</div><div class='add'>+	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &amp;value);</div><div class='add'>+	value &amp;= ~GLI_9763E_VHS_REV;</div><div class='add'>+	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);</div><div class='add'>+	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,</div><div class='ctx'> 					unsigned int timing)</div><div class='ctx'> {</div><div class='hunk'>@@ -1297,6 +1323,9 @@ static int gl9763e_add_host(struct sdhci_pci_slot *slot)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto cleanup;</div><div class='ctx'> </div><div class='add'>+	/* Disable LPM negotiation to avoid entering L1 state. */</div><div class='add'>+	gl9763e_set_low_power_negotiation(slot, false);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> cleanup:</div><div class='hunk'>@@ -1340,31 +1369,6 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM</div><div class='del'>-static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable)</div><div class='del'>-{</div><div class='del'>-	struct pci_dev *pdev = slot-&gt;chip-&gt;pdev;</div><div class='del'>-	u32 value;</div><div class='del'>-</div><div class='del'>-	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &amp;value);</div><div class='del'>-	value &amp;= ~GLI_9763E_VHS_REV;</div><div class='del'>-	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);</div><div class='del'>-	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);</div><div class='del'>-</div><div class='del'>-	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &amp;value);</div><div class='del'>-</div><div class='del'>-	if (enable)</div><div class='del'>-		value &amp;= ~GLI_9763E_CFG_LPSN_DIS;</div><div class='del'>-	else</div><div class='del'>-		value |= GLI_9763E_CFG_LPSN_DIS;</div><div class='del'>-</div><div class='del'>-	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);</div><div class='del'>-</div><div class='del'>-	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &amp;value);</div><div class='del'>-	value &amp;= ~GLI_9763E_VHS_REV;</div><div class='del'>-	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);</div><div class='del'>-	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)</div><div class='ctx'> {</div><div class='ctx'> 	struct sdhci_pci_slot *slot = chip-&gt;slots[0];</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c<br/>index 6b84ba27e6ab..bed57a1c64b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-sprd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-sprd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-sprd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-sprd.c</a></div><div class='hunk'>@@ -239,15 +239,19 @@ static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,</div><div class='ctx'> 	div = ((div &amp; 0x300) &gt;&gt; 2) | ((div &amp; 0xFF) &lt;&lt; 8);</div><div class='ctx'> 	sdhci_enable_clk(host, div);</div><div class='ctx'> </div><div class='add'>+	val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);</div><div class='add'>+	mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;</div><div class='ctx'> 	/* Enable CLK_AUTO when the clock is greater than 400K. */</div><div class='ctx'> 	if (clk &gt; 400000) {</div><div class='del'>-		val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);</div><div class='del'>-		mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |</div><div class='del'>-			SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;</div><div class='ctx'> 		if (mask != (val &amp; mask)) {</div><div class='ctx'> 			val |= mask;</div><div class='ctx'> 			sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);</div><div class='ctx'> 		}</div><div class='add'>+	} else {</div><div class='add'>+		if (val &amp; mask) {</div><div class='add'>+			val &amp;= ~mask;</div><div class='add'>+			sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -416,12 +420,33 @@ static void sdhci_sprd_request_done(struct sdhci_host *host,</div><div class='ctx'> 	mmc_request_done(host-&gt;mmc, mrq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode,</div><div class='add'>+				 unsigned short vdd)</div><div class='add'>+{</div><div class='add'>+	struct mmc_host *mmc = host-&gt;mmc;</div><div class='add'>+</div><div class='add'>+	switch (mode) {</div><div class='add'>+	case MMC_POWER_OFF:</div><div class='add'>+		mmc_regulator_set_ocr(host-&gt;mmc, mmc-&gt;supply.vmmc, 0);</div><div class='add'>+</div><div class='add'>+		mmc_regulator_disable_vqmmc(mmc);</div><div class='add'>+		break;</div><div class='add'>+	case MMC_POWER_ON:</div><div class='add'>+		mmc_regulator_enable_vqmmc(mmc);</div><div class='add'>+		break;</div><div class='add'>+	case MMC_POWER_UP:</div><div class='add'>+		mmc_regulator_set_ocr(host-&gt;mmc, mmc-&gt;supply.vmmc, vdd);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct sdhci_ops sdhci_sprd_ops = {</div><div class='ctx'> 	.read_l = sdhci_sprd_readl,</div><div class='ctx'> 	.write_l = sdhci_sprd_writel,</div><div class='ctx'> 	.write_w = sdhci_sprd_writew,</div><div class='ctx'> 	.write_b = sdhci_sprd_writeb,</div><div class='ctx'> 	.set_clock = sdhci_sprd_set_clock,</div><div class='add'>+	.set_power = sdhci_sprd_set_power,</div><div class='ctx'> 	.get_max_clock = sdhci_sprd_get_max_clock,</div><div class='ctx'> 	.get_min_clock = sdhci_sprd_get_min_clock,</div><div class='ctx'> 	.set_bus_width = sdhci_set_bus_width,</div><div class='hunk'>@@ -823,6 +848,10 @@ static int sdhci_sprd_probe(struct platform_device *pdev)</div><div class='ctx'> 	host-&gt;caps1 &amp;= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |</div><div class='ctx'> 			 SDHCI_SUPPORT_DDR50);</div><div class='ctx'> </div><div class='add'>+	ret = mmc_regulator_get_supply(host-&gt;mmc);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto pm_runtime_disable;</div><div class='add'>+</div><div class='ctx'> 	ret = sdhci_setup_host(host);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto pm_runtime_disable;</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c<br/>index 25ba7aecc3be..0e52867f6e91 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-xenon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-xenon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-xenon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-xenon.c</a></div><div class='hunk'>@@ -18,6 +18,8 @@</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/pm.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/mm.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "sdhci-pltfm.h"</div><div class='ctx'> #include "sdhci-xenon.h"</div><div class='hunk'>@@ -422,6 +424,7 @@ static int xenon_probe_params(struct platform_device *pdev)</div><div class='ctx'> 	struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);</div><div class='ctx'> 	u32 sdhc_id, nr_sdhc;</div><div class='ctx'> 	u32 tuning_count;</div><div class='add'>+	struct sysinfo si;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable HS200 on Armada AP806 */</div><div class='ctx'> 	if (priv-&gt;hw_version == XENON_AP806)</div><div class='hunk'>@@ -450,6 +453,23 @@ static int xenon_probe_params(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> 	priv-&gt;tuning_count = tuning_count;</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * AC5/X/IM HW has only 31-bits passed in the crossbar switch.</div><div class='add'>+	 * If we have more than 2GB of memory, this means we might pass</div><div class='add'>+	 * memory pointers which are above 2GB and which cannot be properly</div><div class='add'>+	 * represented. In this case, disable ADMA, 64-bit DMA and allow only SDMA.</div><div class='add'>+	 * This effectively will enable bounce buffer quirk in the</div><div class='add'>+	 * generic SDHCI driver, which will make sure DMA is only done</div><div class='add'>+	 * from supported memory regions:</div><div class='add'>+	 */</div><div class='add'>+	if (priv-&gt;hw_version == XENON_AC5) {</div><div class='add'>+		si_meminfo(&amp;si);</div><div class='add'>+		if (si.totalram * si.mem_unit &gt; SZ_2G) {</div><div class='add'>+			host-&gt;quirks |= SDHCI_QUIRK_BROKEN_ADMA;</div><div class='add'>+			host-&gt;quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return xenon_phy_parse_params(dev, host);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -562,6 +582,16 @@ static int xenon_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto remove_sdhc;</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_put_autosuspend(&amp;pdev-&gt;dev);</div><div class='add'>+	/*</div><div class='add'>+	 * If we previously detected AC5 with over 2GB of memory,</div><div class='add'>+	 * then we disable ADMA and 64-bit DMA.</div><div class='add'>+	 * This means generic SDHCI driver has set the DMA mask to</div><div class='add'>+	 * 32-bit. Since DDR starts at 0x2_0000_0000, we must use</div><div class='add'>+	 * 34-bit DMA mask to access this DDR memory:</div><div class='add'>+	 */</div><div class='add'>+	if (priv-&gt;hw_version == XENON_AC5 &amp;&amp;</div><div class='add'>+	    host-&gt;quirks2 &amp; SDHCI_QUIRK2_BROKEN_64_BIT_DMA)</div><div class='add'>+		dma_set_mask_and_coherent(&amp;pdev-&gt;dev, DMA_BIT_MASK(34));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -680,6 +710,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = {</div><div class='ctx'> 	{ .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807},</div><div class='ctx'> 	{ .compatible = "marvell,armada-cp110-sdhci", .data =  (void *)XENON_CP110},</div><div class='ctx'> 	{ .compatible = "marvell,armada-3700-sdhci", .data =  (void *)XENON_A3700},</div><div class='add'>+	{ .compatible = "marvell,ac5-sdhci",	     .data =  (void *)XENON_AC5},</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);</div><div class='head'>diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h<br/>index 3e9c6c908a79..0460d97aad26 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-xenon.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci-xenon.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci-xenon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci-xenon.h</a></div><div class='hunk'>@@ -57,7 +57,8 @@ enum xenon_variant {</div><div class='ctx'> 	XENON_A3700,</div><div class='ctx'> 	XENON_AP806,</div><div class='ctx'> 	XENON_AP807,</div><div class='del'>-	XENON_CP110</div><div class='add'>+	XENON_CP110,</div><div class='add'>+	XENON_AC5</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct xenon_priv {</div><div class='head'>diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c<br/>index ff41aa56564e..c79f73459915 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci.c</a></div><div class='hunk'>@@ -2841,7 +2841,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(sdhci_send_tuning);</div><div class='ctx'> </div><div class='del'>-static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)</div><div class='add'>+int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -2879,6 +2879,7 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)</div><div class='ctx'> 	sdhci_reset_tuning(host);</div><div class='ctx'> 	return -EAGAIN;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(__sdhci_execute_tuning);</div><div class='ctx'> </div><div class='ctx'> int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h<br/>index f219bdea8f28..a20864fc0641 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci.h</a></div><div class='hunk'>@@ -793,6 +793,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width);</div><div class='ctx'> void sdhci_reset(struct sdhci_host *host, u8 mask);</div><div class='ctx'> void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);</div><div class='ctx'> int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);</div><div class='add'>+int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);</div><div class='ctx'> void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);</div><div class='ctx'> int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,</div><div class='ctx'> 				      struct mmc_ios *ios);</div><div class='head'>diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c<br/>index 967bd2dfcda1..d659c59422e1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci_am654.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mmc/host/sdhci_am654.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mmc/host/sdhci_am654.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mmc/host/sdhci_am654.c</a></div><div class='hunk'>@@ -141,7 +141,6 @@ static const struct timing_data td[] = {</div><div class='ctx'> </div><div class='ctx'> struct sdhci_am654_data {</div><div class='ctx'> 	struct regmap *base;</div><div class='del'>-	bool legacy_otapdly;</div><div class='ctx'> 	int otap_del_sel[ARRAY_SIZE(td)];</div><div class='ctx'> 	int itap_del_sel[ARRAY_SIZE(td)];</div><div class='ctx'> 	int clkbuf_sel;</div><div class='hunk'>@@ -272,11 +271,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)</div><div class='ctx'> 	sdhci_set_clock(host, clock);</div><div class='ctx'> </div><div class='ctx'> 	/* Setup DLL Output TAP delay */</div><div class='del'>-	if (sdhci_am654-&gt;legacy_otapdly)</div><div class='del'>-		otap_del_sel = sdhci_am654-&gt;otap_del_sel[0];</div><div class='del'>-	else</div><div class='del'>-		otap_del_sel = sdhci_am654-&gt;otap_del_sel[timing];</div><div class='del'>-</div><div class='add'>+	otap_del_sel = sdhci_am654-&gt;otap_del_sel[timing];</div><div class='ctx'> 	otap_del_ena = (timing &gt; MMC_TIMING_UHS_SDR25) ? 1 : 0;</div><div class='ctx'> </div><div class='ctx'> 	mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;</div><div class='hunk'>@@ -314,10 +309,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,</div><div class='ctx'> 	u32 mask, val;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup DLL Output TAP delay */</div><div class='del'>-	if (sdhci_am654-&gt;legacy_otapdly)</div><div class='del'>-		otap_del_sel = sdhci_am654-&gt;otap_del_sel[0];</div><div class='del'>-	else</div><div class='del'>-		otap_del_sel = sdhci_am654-&gt;otap_del_sel[timing];</div><div class='add'>+	otap_del_sel = sdhci_am654-&gt;otap_del_sel[timing];</div><div class='ctx'> </div><div class='ctx'> 	mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;</div><div class='ctx'> 	val = (0x1 &lt;&lt; OTAPDLYENA_SHIFT) |</div><div class='hunk'>@@ -577,32 +569,15 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host,</div><div class='ctx'> 	int i;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,</div><div class='del'>-				 &amp;sdhci_am654-&gt;otap_del_sel[MMC_TIMING_LEGACY]);</div><div class='del'>-	if (ret) {</div><div class='del'>-		/*</div><div class='del'>-		 * ti,otap-del-sel-legacy is mandatory, look for old binding</div><div class='del'>-		 * if not found.</div><div class='del'>-		 */</div><div class='del'>-		ret = device_property_read_u32(dev, "ti,otap-del-sel",</div><div class='del'>-					       &amp;sdhci_am654-&gt;otap_del_sel[0]);</div><div class='del'>-		if (ret) {</div><div class='del'>-			dev_err(dev, "Couldn't find otap-del-sel\n");</div><div class='del'>-</div><div class='del'>-			return ret;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		dev_info(dev, "Using legacy binding ti,otap-del-sel\n");</div><div class='del'>-		sdhci_am654-&gt;legacy_otapdly = true;</div><div class='del'>-</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	for (i = MMC_TIMING_LEGACY; i &lt;= MMC_TIMING_MMC_HS400; i++) {</div><div class='ctx'> </div><div class='ctx'> 		ret = device_property_read_u32(dev, td[i].otap_binding,</div><div class='ctx'> 					       &amp;sdhci_am654-&gt;otap_del_sel[i]);</div><div class='ctx'> 		if (ret) {</div><div class='add'>+			if (i == MMC_TIMING_LEGACY) {</div><div class='add'>+				dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");</div><div class='add'>+				return ret;</div><div class='add'>+			}</div><div class='ctx'> 			dev_dbg(dev, "Couldn't find %s\n",</div><div class='ctx'> 				td[i].otap_binding);</div><div class='ctx'> 			/*</div><div class='head'>diff --git a/drivers/mtd/maps/vmu-flash.c b/drivers/mtd/maps/vmu-flash.c<br/>index a7ec947a3ebb..53019d313db7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/maps/vmu-flash.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/maps/vmu-flash.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/maps/vmu-flash.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/maps/vmu-flash.c</a></div><div class='hunk'>@@ -719,7 +719,7 @@ static int vmu_can_unload(struct maple_device *mdev)</div><div class='ctx'> 	card = maple_get_drvdata(mdev);</div><div class='ctx'> 	for (x = 0; x &lt; card-&gt;partitions; x++) {</div><div class='ctx'> 		mtd = &amp;((card-&gt;mtd)[x]);</div><div class='del'>-		if (mtd-&gt;usecount &gt; 0)</div><div class='add'>+		if (kref_read(&amp;mtd-&gt;refcnt))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 1;</div><div class='head'>diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c<br/>index ff18636e0889..f0526dcc2162 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/mtd_blkdevs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/mtd_blkdevs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/mtd_blkdevs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/mtd_blkdevs.c</a></div><div class='hunk'>@@ -376,10 +376,8 @@ int add_mtd_blktrans_dev(struct mtd_blktrans_dev *new)</div><div class='ctx'> 	blk_queue_flag_set(QUEUE_FLAG_NONROT, new-&gt;rq);</div><div class='ctx'> 	blk_queue_flag_clear(QUEUE_FLAG_ADD_RANDOM, new-&gt;rq);</div><div class='ctx'> </div><div class='del'>-	if (tr-&gt;discard) {</div><div class='add'>+	if (tr-&gt;discard)</div><div class='ctx'> 		blk_queue_max_discard_sectors(new-&gt;rq, UINT_MAX);</div><div class='del'>-		new-&gt;rq-&gt;limits.discard_granularity = tr-&gt;blksize;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	gd-&gt;queue = new-&gt;rq;</div><div class='ctx'> </div><div class='hunk'>@@ -463,7 +461,7 @@ static void blktrans_notify_add(struct mtd_info *mtd)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtd_blktrans_ops *tr;</div><div class='ctx'> </div><div class='del'>-	if (mtd-&gt;type == MTD_ABSENT)</div><div class='add'>+	if (mtd-&gt;type == MTD_ABSENT || mtd-&gt;type == MTD_UBIVOLUME)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry(tr, &amp;blktrans_majors, list)</div><div class='hunk'>@@ -503,7 +501,7 @@ int register_mtd_blktrans(struct mtd_blktrans_ops *tr)</div><div class='ctx'> 	mutex_lock(&amp;mtd_table_mutex);</div><div class='ctx'> 	list_add(&amp;tr-&gt;list, &amp;blktrans_majors);</div><div class='ctx'> 	mtd_for_each_device(mtd)</div><div class='del'>-		if (mtd-&gt;type != MTD_ABSENT)</div><div class='add'>+		if (mtd-&gt;type != MTD_ABSENT &amp;&amp; mtd-&gt;type != MTD_UBIVOLUME)</div><div class='ctx'> 			tr-&gt;add_mtd(tr, mtd);</div><div class='ctx'> 	mutex_unlock(&amp;mtd_table_mutex);</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c<br/>index bb0759ca12f1..e451b28840d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/mtdcore.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/mtdcore.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/mtdcore.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/mtdcore.c</a></div><div class='hunk'>@@ -30,6 +30,7 @@</div><div class='ctx'> #include &lt;linux/debugfs.h&gt;</div><div class='ctx'> #include &lt;linux/nvmem-provider.h&gt;</div><div class='ctx'> #include &lt;linux/root_dev.h&gt;</div><div class='add'>+#include &lt;linux/error-injection.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/mtd/mtd.h&gt;</div><div class='ctx'> #include &lt;linux/mtd/partitions.h&gt;</div><div class='hunk'>@@ -1412,6 +1413,7 @@ int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mtd_erase);</div><div class='add'>+ALLOW_ERROR_INJECTION(mtd_erase, ERRNO);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * This stuff for eXecute-In-Place. phys is optional and may be set to NULL.</div><div class='hunk'>@@ -1511,6 +1513,7 @@ int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mtd_read);</div><div class='add'>+ALLOW_ERROR_INJECTION(mtd_read, ERRNO);</div><div class='ctx'> </div><div class='ctx'> int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,</div><div class='ctx'> 	      const u_char *buf)</div><div class='hunk'>@@ -1527,6 +1530,7 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mtd_write);</div><div class='add'>+ALLOW_ERROR_INJECTION(mtd_write, ERRNO);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * In blackbox flight recorder like scenarios we want to make successful writes</div><div class='hunk'>@@ -2347,6 +2351,7 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(mtd_block_markbad);</div><div class='add'>+ALLOW_ERROR_INJECTION(mtd_block_markbad, ERRNO);</div><div class='ctx'> </div><div class='ctx'> /*</div><div class='ctx'>  * default_mtd_writev - the default writev method</div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c<br/>index 9596629000f4..968c5b674b08 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c</a></div><div class='hunk'>@@ -85,7 +85,7 @@ MODULE_DEVICE_TABLE(of, bcm63138_nand_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver bcm63138_nand_driver = {</div><div class='ctx'> 	.probe			= bcm63138_nand_probe,</div><div class='del'>-	.remove			= brcmnand_remove,</div><div class='add'>+	.remove_new		= brcmnand_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "bcm63138_nand",</div><div class='ctx'> 		.pm		= &amp;brcmnand_pm_ops,</div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c<br/>index a06cd87f839a..05b7b653bdf3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c</a></div><div class='hunk'>@@ -117,7 +117,7 @@ MODULE_DEVICE_TABLE(of, bcm6368_nand_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver bcm6368_nand_driver = {</div><div class='ctx'> 	.probe			= bcm6368_nand_probe,</div><div class='del'>-	.remove			= brcmnand_remove,</div><div class='add'>+	.remove_new		= brcmnand_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "bcm6368_nand",</div><div class='ctx'> 		.pm		= &amp;brcmnand_pm_ops,</div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/bcma_nand.c b/drivers/mtd/nand/raw/brcmnand/bcma_nand.c<br/>index dd27977919fb..4e7e435ba339 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcma_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/bcma_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/bcma_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/bcma_nand.c</a></div><div class='hunk'>@@ -119,7 +119,7 @@ static int brcmnand_bcma_nand_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver brcmnand_bcma_nand_driver = {</div><div class='ctx'> 	.probe			= brcmnand_bcma_nand_probe,</div><div class='del'>-	.remove			= brcmnand_remove,</div><div class='add'>+	.remove_new		= brcmnand_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "bcma_brcmnand",</div><div class='ctx'> 		.pm		= &amp;brcmnand_pm_ops,</div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c<br/>index 440bef477930..8faca43ae1ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmnand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/brcmnand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmnand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmnand.c</a></div><div class='hunk'>@@ -625,6 +625,8 @@ enum {</div><div class='ctx'> /* Only for v7.2 */</div><div class='ctx'> #define	ACC_CONTROL_ECC_EXT_SHIFT		13</div><div class='ctx'> </div><div class='add'>+static u8 brcmnand_status(struct brcmnand_host *host);</div><div class='add'>+</div><div class='ctx'> static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)</div><div class='ctx'> {</div><div class='ctx'> #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)</div><div class='hunk'>@@ -1022,19 +1024,6 @@ static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)</div><div class='ctx'> 		return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)</div><div class='del'>-{</div><div class='del'>-	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='del'>-	int shift = brcmnand_sector_1k_shift(ctrl);</div><div class='del'>-	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host-&gt;cs,</div><div class='del'>-						  BRCMNAND_CS_ACC_CONTROL);</div><div class='del'>-</div><div class='del'>-	if (shift &lt; 0)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return (nand_readreg(ctrl, acc_control_offs) &gt;&gt; shift) &amp; 0x1;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)</div><div class='ctx'> {</div><div class='ctx'> 	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='hunk'>@@ -1061,10 +1050,11 @@ enum {</div><div class='ctx'> 	CS_SELECT_AUTO_DEVICE_ID_CFG		= BIT(30),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,</div><div class='add'>+static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,</div><div class='ctx'> 				    u32 mask, u32 expected_val,</div><div class='ctx'> 				    unsigned long timeout_ms)</div><div class='ctx'> {</div><div class='add'>+	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='ctx'> 	unsigned long limit;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='hunk'>@@ -1073,6 +1063,9 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,</div><div class='ctx'> </div><div class='ctx'> 	limit = jiffies + msecs_to_jiffies(timeout_ms);</div><div class='ctx'> 	do {</div><div class='add'>+		if (mask &amp; INTFC_FLASH_STATUS)</div><div class='add'>+			brcmnand_status(host);</div><div class='add'>+</div><div class='ctx'> 		val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);</div><div class='ctx'> 		if ((val &amp; mask) == expected_val)</div><div class='ctx'> 			return 0;</div><div class='hunk'>@@ -1084,6 +1077,9 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl,</div><div class='ctx'> 	 * do a final check after time out in case the CPU was busy and the driver</div><div class='ctx'> 	 * did not get enough time to perform the polling to avoid false alarms</div><div class='ctx'> 	 */</div><div class='add'>+	if (mask &amp; INTFC_FLASH_STATUS)</div><div class='add'>+		brcmnand_status(host);</div><div class='add'>+</div><div class='ctx'> 	val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);</div><div class='ctx'> 	if ((val &amp; mask) == expected_val)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1379,7 +1375,7 @@ static void brcmnand_wp(struct mtd_info *mtd, int wp)</div><div class='ctx'> 		 * make sure ctrl/flash ready before and after</div><div class='ctx'> 		 * changing state of #WP pin</div><div class='ctx'> 		 */</div><div class='del'>-		ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY |</div><div class='add'>+		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY |</div><div class='ctx'> 					       NAND_STATUS_READY,</div><div class='ctx'> 					       NAND_CTRL_RDY |</div><div class='ctx'> 					       NAND_STATUS_READY, 0);</div><div class='hunk'>@@ -1387,9 +1383,10 @@ static void brcmnand_wp(struct mtd_info *mtd, int wp)</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='ctx'> 		brcmnand_set_wp(ctrl, wp);</div><div class='del'>-		nand_status_op(chip, NULL);</div><div class='add'>+		/* force controller operation to update internal copy of NAND chip status */</div><div class='add'>+		brcmnand_status(host);</div><div class='ctx'> 		/* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */</div><div class='del'>-		ret = bcmnand_ctrl_poll_status(ctrl,</div><div class='add'>+		ret = bcmnand_ctrl_poll_status(host,</div><div class='ctx'> 					       NAND_CTRL_RDY |</div><div class='ctx'> 					       NAND_STATUS_READY |</div><div class='ctx'> 					       NAND_STATUS_WP,</div><div class='hunk'>@@ -1629,13 +1626,13 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (oops_in_progress) {</div><div class='ctx'> 		if (ctrl-&gt;cmd_pending &amp;&amp;</div><div class='del'>-			bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))</div><div class='add'>+			bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))</div><div class='ctx'> 			return;</div><div class='ctx'> 	} else</div><div class='ctx'> 		BUG_ON(ctrl-&gt;cmd_pending != 0);</div><div class='ctx'> 	ctrl-&gt;cmd_pending = cmd;</div><div class='ctx'> </div><div class='del'>-	ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);</div><div class='add'>+	ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);</div><div class='ctx'> 	WARN_ON(ret);</div><div class='ctx'> </div><div class='ctx'> 	mb(); /* flush previous writes */</div><div class='hunk'>@@ -1643,16 +1640,6 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)</div><div class='ctx'> 			   cmd &lt;&lt; brcmnand_cmd_shift(ctrl));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/***********************************************************************</div><div class='del'>- * NAND MTD API: read/program/erase</div><div class='del'>- ***********************************************************************/</div><div class='del'>-</div><div class='del'>-static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat,</div><div class='del'>-			      unsigned int ctrl)</div><div class='del'>-{</div><div class='del'>-	/* intentionally left blank */</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)</div><div class='ctx'> {</div><div class='ctx'> 	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='hunk'>@@ -1664,7 +1651,7 @@ static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)</div><div class='ctx'> 	if (mtd-&gt;oops_panic_write || ctrl-&gt;irq &lt; 0) {</div><div class='ctx'> 		/* switch to interrupt polling and PIO mode */</div><div class='ctx'> 		disable_ctrl_irqs(ctrl);</div><div class='del'>-		sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,</div><div class='add'>+		sts = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY,</div><div class='ctx'> 					       NAND_CTRL_RDY, 0);</div><div class='ctx'> 		err = sts &lt; 0;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1703,6 +1690,26 @@ static int brcmnand_waitfunc(struct nand_chip *chip)</div><div class='ctx'> 				 INTFC_FLASH_STATUS;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u8 brcmnand_status(struct brcmnand_host *host)</div><div class='add'>+{</div><div class='add'>+	struct nand_chip *chip = &amp;host-&gt;chip;</div><div class='add'>+	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='add'>+</div><div class='add'>+	brcmnand_set_cmd_addr(mtd, 0);</div><div class='add'>+	brcmnand_send_cmd(host, CMD_STATUS_READ);</div><div class='add'>+</div><div class='add'>+	return brcmnand_waitfunc(chip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u8 brcmnand_reset(struct brcmnand_host *host)</div><div class='add'>+{</div><div class='add'>+	struct nand_chip *chip = &amp;host-&gt;chip;</div><div class='add'>+</div><div class='add'>+	brcmnand_send_cmd(host, CMD_FLASH_RESET);</div><div class='add'>+</div><div class='add'>+	return brcmnand_waitfunc(chip);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> enum {</div><div class='ctx'> 	LLOP_RE				= BIT(16),</div><div class='ctx'> 	LLOP_WE				= BIT(17),</div><div class='hunk'>@@ -1752,190 +1759,6 @@ static int brcmnand_low_level_op(struct brcmnand_host *host,</div><div class='ctx'> 	return brcmnand_waitfunc(chip);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command,</div><div class='del'>-			     int column, int page_addr)</div><div class='del'>-{</div><div class='del'>-	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='del'>-	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='del'>-	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='del'>-	u64 addr = (u64)page_addr &lt;&lt; chip-&gt;page_shift;</div><div class='del'>-	int native_cmd = 0;</div><div class='del'>-</div><div class='del'>-	if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||</div><div class='del'>-			command == NAND_CMD_RNDOUT)</div><div class='del'>-		addr = (u64)column;</div><div class='del'>-	/* Avoid propagating a negative, don't-care address */</div><div class='del'>-	else if (page_addr &lt; 0)</div><div class='del'>-		addr = 0;</div><div class='del'>-</div><div class='del'>-	dev_dbg(ctrl-&gt;dev, "cmd 0x%x addr 0x%llx\n", command,</div><div class='del'>-		(unsigned long long)addr);</div><div class='del'>-</div><div class='del'>-	host-&gt;last_cmd = command;</div><div class='del'>-	host-&gt;last_byte = 0;</div><div class='del'>-	host-&gt;last_addr = addr;</div><div class='del'>-</div><div class='del'>-	switch (command) {</div><div class='del'>-	case NAND_CMD_RESET:</div><div class='del'>-		native_cmd = CMD_FLASH_RESET;</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_STATUS:</div><div class='del'>-		native_cmd = CMD_STATUS_READ;</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_READID:</div><div class='del'>-		native_cmd = CMD_DEVICE_ID_READ;</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_READOOB:</div><div class='del'>-		native_cmd = CMD_SPARE_AREA_READ;</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_ERASE1:</div><div class='del'>-		native_cmd = CMD_BLOCK_ERASE;</div><div class='del'>-		brcmnand_wp(mtd, 0);</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_PARAM:</div><div class='del'>-		native_cmd = CMD_PARAMETER_READ;</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_SET_FEATURES:</div><div class='del'>-	case NAND_CMD_GET_FEATURES:</div><div class='del'>-		brcmnand_low_level_op(host, LL_OP_CMD, command, false);</div><div class='del'>-		brcmnand_low_level_op(host, LL_OP_ADDR, column, false);</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_RNDOUT:</div><div class='del'>-		native_cmd = CMD_PARAMETER_CHANGE_COL;</div><div class='del'>-		addr &amp;= ~((u64)(FC_BYTES - 1));</div><div class='del'>-		/*</div><div class='del'>-		 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0</div><div class='del'>-		 * NB: hwcfg.sector_size_1k may not be initialized yet</div><div class='del'>-		 */</div><div class='del'>-		if (brcmnand_get_sector_size_1k(host)) {</div><div class='del'>-			host-&gt;hwcfg.sector_size_1k =</div><div class='del'>-				brcmnand_get_sector_size_1k(host);</div><div class='del'>-			brcmnand_set_sector_size_1k(host, 0);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!native_cmd)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	brcmnand_set_cmd_addr(mtd, addr);</div><div class='del'>-	brcmnand_send_cmd(host, native_cmd);</div><div class='del'>-	brcmnand_waitfunc(chip);</div><div class='del'>-</div><div class='del'>-	if (native_cmd == CMD_PARAMETER_READ ||</div><div class='del'>-			native_cmd == CMD_PARAMETER_CHANGE_COL) {</div><div class='del'>-		/* Copy flash cache word-wise */</div><div class='del'>-		u32 *flash_cache = (u32 *)ctrl-&gt;flash_cache;</div><div class='del'>-		int i;</div><div class='del'>-</div><div class='del'>-		brcmnand_soc_data_bus_prepare(ctrl-&gt;soc, true);</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Must cache the FLASH_CACHE now, since changes in</div><div class='del'>-		 * SECTOR_SIZE_1K may invalidate it</div><div class='del'>-		 */</div><div class='del'>-		for (i = 0; i &lt; FC_WORDS; i++)</div><div class='del'>-			/*</div><div class='del'>-			 * Flash cache is big endian for parameter pages, at</div><div class='del'>-			 * least on STB SoCs</div><div class='del'>-			 */</div><div class='del'>-			flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));</div><div class='del'>-</div><div class='del'>-		brcmnand_soc_data_bus_unprepare(ctrl-&gt;soc, true);</div><div class='del'>-</div><div class='del'>-		/* Cleanup from HW quirk: restore SECTOR_SIZE_1K */</div><div class='del'>-		if (host-&gt;hwcfg.sector_size_1k)</div><div class='del'>-			brcmnand_set_sector_size_1k(host,</div><div class='del'>-						    host-&gt;hwcfg.sector_size_1k);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Re-enable protection is necessary only after erase */</div><div class='del'>-	if (command == NAND_CMD_ERASE1)</div><div class='del'>-		brcmnand_wp(mtd, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static uint8_t brcmnand_read_byte(struct nand_chip *chip)</div><div class='del'>-{</div><div class='del'>-	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='del'>-	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='del'>-	uint8_t ret = 0;</div><div class='del'>-	int addr, offs;</div><div class='del'>-</div><div class='del'>-	switch (host-&gt;last_cmd) {</div><div class='del'>-	case NAND_CMD_READID:</div><div class='del'>-		if (host-&gt;last_byte &lt; 4)</div><div class='del'>-			ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) &gt;&gt;</div><div class='del'>-				(24 - (host-&gt;last_byte &lt;&lt; 3));</div><div class='del'>-		else if (host-&gt;last_byte &lt; 8)</div><div class='del'>-			ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) &gt;&gt;</div><div class='del'>-				(56 - (host-&gt;last_byte &lt;&lt; 3));</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case NAND_CMD_READOOB:</div><div class='del'>-		ret = oob_reg_read(ctrl, host-&gt;last_byte);</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case NAND_CMD_STATUS:</div><div class='del'>-		ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &amp;</div><div class='del'>-					INTFC_FLASH_STATUS;</div><div class='del'>-		if (wp_on) /* hide WP status */</div><div class='del'>-			ret |= NAND_STATUS_WP;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case NAND_CMD_PARAM:</div><div class='del'>-	case NAND_CMD_RNDOUT:</div><div class='del'>-		addr = host-&gt;last_addr + host-&gt;last_byte;</div><div class='del'>-		offs = addr &amp; (FC_BYTES - 1);</div><div class='del'>-</div><div class='del'>-		/* At FC_BYTES boundary, switch to next column */</div><div class='del'>-		if (host-&gt;last_byte &gt; 0 &amp;&amp; offs == 0)</div><div class='del'>-			nand_change_read_column_op(chip, addr, NULL, 0, false);</div><div class='del'>-</div><div class='del'>-		ret = ctrl-&gt;flash_cache[offs];</div><div class='del'>-		break;</div><div class='del'>-	case NAND_CMD_GET_FEATURES:</div><div class='del'>-		if (host-&gt;last_byte &gt;= ONFI_SUBFEATURE_PARAM_LEN) {</div><div class='del'>-			ret = 0;</div><div class='del'>-		} else {</div><div class='del'>-			bool last = host-&gt;last_byte ==</div><div class='del'>-				ONFI_SUBFEATURE_PARAM_LEN - 1;</div><div class='del'>-			brcmnand_low_level_op(host, LL_OP_RD, 0, last);</div><div class='del'>-			ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) &amp; 0xff;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dev_dbg(ctrl-&gt;dev, "read byte = 0x%02x\n", ret);</div><div class='del'>-	host-&gt;last_byte++;</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void brcmnand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; len; i++, buf++)</div><div class='del'>-		*buf = brcmnand_read_byte(chip);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf,</div><div class='del'>-			       int len)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='del'>-</div><div class='del'>-	switch (host-&gt;last_cmd) {</div><div class='del'>-	case NAND_CMD_SET_FEATURES:</div><div class='del'>-		for (i = 0; i &lt; len; i++)</div><div class='del'>-			brcmnand_low_level_op(host, LL_OP_WR, buf[i],</div><div class='del'>-						  (i + 1) == len);</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		BUG();</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> /*</div><div class='ctx'>  *  Kick EDU engine</div><div class='ctx'>  */</div><div class='hunk'>@@ -2345,8 +2168,9 @@ static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,</div><div class='ctx'> 	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='ctx'> 	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='ctx'> 	u8 *oob = oob_required ? (u8 *)chip-&gt;oob_poi : NULL;</div><div class='add'>+	u64 addr = (u64)page &lt;&lt; chip-&gt;page_shift;</div><div class='ctx'> </div><div class='del'>-	nand_read_page_op(chip, page, 0, NULL, 0);</div><div class='add'>+	host-&gt;last_addr = addr;</div><div class='ctx'> </div><div class='ctx'> 	return brcmnand_read(mtd, chip, host-&gt;last_addr,</div><div class='ctx'> 			mtd-&gt;writesize &gt;&gt; FC_SHIFT, (u32 *)buf, oob);</div><div class='hunk'>@@ -2359,8 +2183,9 @@ static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,</div><div class='ctx'> 	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='ctx'> 	u8 *oob = oob_required ? (u8 *)chip-&gt;oob_poi : NULL;</div><div class='ctx'> 	int ret;</div><div class='add'>+	u64 addr = (u64)page &lt;&lt; chip-&gt;page_shift;</div><div class='ctx'> </div><div class='del'>-	nand_read_page_op(chip, page, 0, NULL, 0);</div><div class='add'>+	host-&gt;last_addr = addr;</div><div class='ctx'> </div><div class='ctx'> 	brcmnand_set_ecc_enabled(host, 0);</div><div class='ctx'> 	ret = brcmnand_read(mtd, chip, host-&gt;last_addr,</div><div class='hunk'>@@ -2468,11 +2293,11 @@ static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,</div><div class='ctx'> 	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='ctx'> 	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='ctx'> 	void *oob = oob_required ? chip-&gt;oob_poi : NULL;</div><div class='add'>+	u64 addr = (u64)page &lt;&lt; chip-&gt;page_shift;</div><div class='ctx'> </div><div class='del'>-	nand_prog_page_begin_op(chip, page, 0, NULL, 0);</div><div class='del'>-	brcmnand_write(mtd, chip, host-&gt;last_addr, (const u32 *)buf, oob);</div><div class='add'>+	host-&gt;last_addr = addr;</div><div class='ctx'> </div><div class='del'>-	return nand_prog_page_end_op(chip);</div><div class='add'>+	return brcmnand_write(mtd, chip, host-&gt;last_addr, (const u32 *)buf, oob);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,</div><div class='hunk'>@@ -2481,13 +2306,15 @@ static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,</div><div class='ctx'> 	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='ctx'> 	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='ctx'> 	void *oob = oob_required ? chip-&gt;oob_poi : NULL;</div><div class='add'>+	u64 addr = (u64)page &lt;&lt; chip-&gt;page_shift;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	nand_prog_page_begin_op(chip, page, 0, NULL, 0);</div><div class='add'>+	host-&gt;last_addr = addr;</div><div class='ctx'> 	brcmnand_set_ecc_enabled(host, 0);</div><div class='del'>-	brcmnand_write(mtd, chip, host-&gt;last_addr, (const u32 *)buf, oob);</div><div class='add'>+	ret = brcmnand_write(mtd, chip, host-&gt;last_addr, (const u32 *)buf, oob);</div><div class='ctx'> 	brcmnand_set_ecc_enabled(host, 1);</div><div class='ctx'> </div><div class='del'>-	return nand_prog_page_end_op(chip);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int brcmnand_write_oob(struct nand_chip *chip, int page)</div><div class='hunk'>@@ -2511,6 +2338,130 @@ static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int brcmnand_exec_instr(struct brcmnand_host *host, int i,</div><div class='add'>+				const struct nand_operation *op)</div><div class='add'>+{</div><div class='add'>+	const struct nand_op_instr *instr = &amp;op-&gt;instrs[i];</div><div class='add'>+	struct brcmnand_controller *ctrl = host-&gt;ctrl;</div><div class='add'>+	const u8 *out;</div><div class='add'>+	bool last_op;</div><div class='add'>+	int ret = 0;</div><div class='add'>+	u8 *in;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * The controller needs to be aware of the last command in the operation</div><div class='add'>+	 * (WAITRDY excepted).</div><div class='add'>+	 */</div><div class='add'>+	last_op = ((i == (op-&gt;ninstrs - 1)) &amp;&amp; (instr-&gt;type != NAND_OP_WAITRDY_INSTR)) ||</div><div class='add'>+		  ((i == (op-&gt;ninstrs - 2)) &amp;&amp; (op-&gt;instrs[i+1].type == NAND_OP_WAITRDY_INSTR));</div><div class='add'>+</div><div class='add'>+	switch (instr-&gt;type) {</div><div class='add'>+	case NAND_OP_CMD_INSTR:</div><div class='add'>+		brcmnand_low_level_op(host, LL_OP_CMD, instr-&gt;ctx.cmd.opcode, last_op);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case NAND_OP_ADDR_INSTR:</div><div class='add'>+		for (i = 0; i &lt; instr-&gt;ctx.addr.naddrs; i++)</div><div class='add'>+			brcmnand_low_level_op(host, LL_OP_ADDR, instr-&gt;ctx.addr.addrs[i],</div><div class='add'>+					      last_op &amp;&amp; (i == (instr-&gt;ctx.addr.naddrs - 1)));</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case NAND_OP_DATA_IN_INSTR:</div><div class='add'>+		in = instr-&gt;ctx.data.buf.in;</div><div class='add'>+		for (i = 0; i &lt; instr-&gt;ctx.data.len; i++) {</div><div class='add'>+			brcmnand_low_level_op(host, LL_OP_RD, 0,</div><div class='add'>+					      last_op &amp;&amp; (i == (instr-&gt;ctx.data.len - 1)));</div><div class='add'>+			in[i] = brcmnand_read_reg(host-&gt;ctrl, BRCMNAND_LL_RDATA);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case NAND_OP_DATA_OUT_INSTR:</div><div class='add'>+		out = instr-&gt;ctx.data.buf.out;</div><div class='add'>+		for (i = 0; i &lt; instr-&gt;ctx.data.len; i++)</div><div class='add'>+			brcmnand_low_level_op(host, LL_OP_WR, out[i],</div><div class='add'>+					      last_op &amp;&amp; (i == (instr-&gt;ctx.data.len - 1)));</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case NAND_OP_WAITRDY_INSTR:</div><div class='add'>+		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		dev_err(ctrl-&gt;dev, "unsupported instruction type: %d\n",</div><div class='add'>+			instr-&gt;type);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int brcmnand_op_is_status(const struct nand_operation *op)</div><div class='add'>+{</div><div class='add'>+	if ((op-&gt;ninstrs == 2) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[0].type == NAND_OP_CMD_INSTR) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[1].type == NAND_OP_DATA_IN_INSTR))</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int brcmnand_op_is_reset(const struct nand_operation *op)</div><div class='add'>+{</div><div class='add'>+	if ((op-&gt;ninstrs == 2) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[0].type == NAND_OP_CMD_INSTR) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[0].ctx.cmd.opcode == NAND_CMD_RESET) &amp;&amp;</div><div class='add'>+	    (op-&gt;instrs[1].type == NAND_OP_WAITRDY_INSTR))</div><div class='add'>+		return 1;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int brcmnand_exec_op(struct nand_chip *chip,</div><div class='add'>+			    const struct nand_operation *op,</div><div class='add'>+			    bool check_only)</div><div class='add'>+{</div><div class='add'>+	struct brcmnand_host *host = nand_get_controller_data(chip);</div><div class='add'>+	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='add'>+	u8 *status;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (check_only)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (brcmnand_op_is_status(op)) {</div><div class='add'>+		status = op-&gt;instrs[1].ctx.data.buf.in;</div><div class='add'>+		*status = brcmnand_status(host);</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	else if (brcmnand_op_is_reset(op)) {</div><div class='add'>+		ret = brcmnand_reset(host);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		brcmnand_wp(mtd, 1);</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (op-&gt;deassert_wp)</div><div class='add'>+		brcmnand_wp(mtd, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; op-&gt;ninstrs; i++) {</div><div class='add'>+		ret = brcmnand_exec_instr(host, i, op);</div><div class='add'>+		if (ret)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (op-&gt;deassert_wp)</div><div class='add'>+		brcmnand_wp(mtd, 1);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /***********************************************************************</div><div class='ctx'>  * Per-CS setup (1 NAND device)</div><div class='ctx'>  ***********************************************************************/</div><div class='hunk'>@@ -2821,6 +2772,7 @@ static int brcmnand_attach_chip(struct nand_chip *chip)</div><div class='ctx'> </div><div class='ctx'> static const struct nand_controller_ops brcmnand_controller_ops = {</div><div class='ctx'> 	.attach_chip = brcmnand_attach_chip,</div><div class='add'>+	.exec_op = brcmnand_exec_op,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int brcmnand_init_cs(struct brcmnand_host *host,</div><div class='hunk'>@@ -2845,13 +2797,6 @@ static int brcmnand_init_cs(struct brcmnand_host *host,</div><div class='ctx'> 	mtd-&gt;owner = THIS_MODULE;</div><div class='ctx'> 	mtd-&gt;dev.parent = dev;</div><div class='ctx'> </div><div class='del'>-	chip-&gt;legacy.cmd_ctrl = brcmnand_cmd_ctrl;</div><div class='del'>-	chip-&gt;legacy.cmdfunc = brcmnand_cmdfunc;</div><div class='del'>-	chip-&gt;legacy.waitfunc = brcmnand_waitfunc;</div><div class='del'>-	chip-&gt;legacy.read_byte = brcmnand_read_byte;</div><div class='del'>-	chip-&gt;legacy.read_buf = brcmnand_read_buf;</div><div class='del'>-	chip-&gt;legacy.write_buf = brcmnand_write_buf;</div><div class='del'>-</div><div class='ctx'> 	chip-&gt;ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;</div><div class='ctx'> 	chip-&gt;ecc.read_page = brcmnand_read_page;</div><div class='ctx'> 	chip-&gt;ecc.write_page = brcmnand_write_page;</div><div class='hunk'>@@ -2863,6 +2808,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host,</div><div class='ctx'> 	chip-&gt;ecc.write_oob = brcmnand_write_oob;</div><div class='ctx'> </div><div class='ctx'> 	chip-&gt;controller = &amp;ctrl-&gt;controller;</div><div class='add'>+	ctrl-&gt;controller.controller_wp = 1;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The bootloader might have configured 16bit mode but</div><div class='hunk'>@@ -3299,7 +3245,7 @@ err:</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(brcmnand_probe);</div><div class='ctx'> </div><div class='del'>-int brcmnand_remove(struct platform_device *pdev)</div><div class='add'>+void brcmnand_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct brcmnand_controller *ctrl = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct brcmnand_host *host;</div><div class='hunk'>@@ -3316,8 +3262,6 @@ int brcmnand_remove(struct platform_device *pdev)</div><div class='ctx'> 	clk_disable_unprepare(ctrl-&gt;clk);</div><div class='ctx'> </div><div class='ctx'> 	dev_set_drvdata(&amp;pdev-&gt;dev, NULL);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(brcmnand_remove);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.h b/drivers/mtd/nand/raw/brcmnand/brcmnand.h<br/>index f1f93d85f50d..928114c0be5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmnand.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/brcmnand.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmnand.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmnand.h</a></div><div class='hunk'>@@ -88,7 +88,7 @@ static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);</div><div class='del'>-int brcmnand_remove(struct platform_device *pdev);</div><div class='add'>+void brcmnand_remove(struct platform_device *pdev);</div><div class='ctx'> </div><div class='ctx'> extern const struct dev_pm_ops brcmnand_pm_ops;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c b/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c<br/>index 950923d977b7..558f083b92e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c</a></div><div class='hunk'>@@ -23,7 +23,7 @@ static int brcmstb_nand_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver brcmstb_nand_driver = {</div><div class='ctx'> 	.probe			= brcmstb_nand_probe,</div><div class='del'>-	.remove			= brcmnand_remove,</div><div class='add'>+	.remove_new		= brcmnand_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "brcmstb_nand",</div><div class='ctx'> 		.pm		= &amp;brcmnand_pm_ops,</div><div class='head'>diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c<br/>index 089c70fc6edf..bf46c8b85898 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/iproc_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/brcmnand/iproc_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/brcmnand/iproc_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/brcmnand/iproc_nand.c</a></div><div class='hunk'>@@ -134,7 +134,7 @@ MODULE_DEVICE_TABLE(of, iproc_nand_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver iproc_nand_driver = {</div><div class='ctx'> 	.probe			= iproc_nand_probe,</div><div class='del'>-	.remove			= brcmnand_remove,</div><div class='add'>+	.remove_new		= brcmnand_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name		= "iproc_nand",</div><div class='ctx'> 		.pm		= &amp;brcmnand_pm_ops,</div><div class='head'>diff --git a/drivers/mtd/nand/raw/diskonchip.c b/drivers/mtd/nand/raw/diskonchip.c<br/>index 5d2ddb037a9a..5243fab9face 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/diskonchip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/diskonchip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/diskonchip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/diskonchip.c</a></div><div class='hunk'>@@ -1491,10 +1491,12 @@ static int __init doc_probe(unsigned long physadr)</div><div class='ctx'> 	else</div><div class='ctx'> 		numchips = doc2001_init(mtd);</div><div class='ctx'> </div><div class='del'>-	if ((ret = nand_scan(nand, numchips)) || (ret = doc-&gt;late_init(mtd))) {</div><div class='del'>-		/* DBB note: i believe nand_cleanup is necessary here, as</div><div class='del'>-		   buffers may have been allocated in nand_base.  Check with</div><div class='del'>-		   Thomas. FIX ME! */</div><div class='add'>+	ret = nand_scan(nand, numchips);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto fail;</div><div class='add'>+</div><div class='add'>+	ret = doc-&gt;late_init(mtd);</div><div class='add'>+	if (ret) {</div><div class='ctx'> 		nand_cleanup(nand);</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c<br/>index 20bb1e0cb5eb..f0e2318ce088 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/fsl_ifc_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/fsl_ifc_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/fsl_ifc_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/fsl_ifc_nand.c</a></div><div class='hunk'>@@ -21,7 +21,7 @@</div><div class='ctx'> </div><div class='ctx'> #define ERR_BYTE		0xFF /* Value returned for read</div><div class='ctx'> 					bytes when read failed	*/</div><div class='del'>-#define IFC_TIMEOUT_MSECS	500  /* Maximum number of mSecs to wait</div><div class='add'>+#define IFC_TIMEOUT_MSECS	1000 /* Maximum timeout to wait</div><div class='ctx'> 					for IFC NAND Machine	*/</div><div class='ctx'> </div><div class='ctx'> struct fsl_ifc_ctrl;</div><div class='head'>diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c<br/>index 71ec4052e52a..cdb58aca59c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/meson_nand.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/meson_nand.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/meson_nand.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/meson_nand.c</a></div><div class='hunk'>@@ -90,6 +90,8 @@</div><div class='ctx'> </div><div class='ctx'> /* eMMC clock register, misc control */</div><div class='ctx'> #define CLK_SELECT_NAND		BIT(31)</div><div class='add'>+#define CLK_ALWAYS_ON_NAND	BIT(24)</div><div class='add'>+#define CLK_SELECT_FIX_PLL2	BIT(6)</div><div class='ctx'> </div><div class='ctx'> #define NFC_CLK_CYCLE		6</div><div class='ctx'> </div><div class='hunk'>@@ -509,7 +511,7 @@ static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)</div><div class='ctx'> 	__le64 *info;</div><div class='ctx'> 	int i, count;</div><div class='ctx'> </div><div class='del'>-	for (i = 0, count = 0; i &lt; nand-&gt;ecc.steps; i++, count += 2) {</div><div class='add'>+	for (i = 0, count = 0; i &lt; nand-&gt;ecc.steps; i++, count += (2 + nand-&gt;ecc.bytes)) {</div><div class='ctx'> 		info = &amp;meson_chip-&gt;info_buf[i];</div><div class='ctx'> 		*info |= oob_buf[count];</div><div class='ctx'> 		*info |= oob_buf[count + 1] &lt;&lt; 8;</div><div class='hunk'>@@ -522,7 +524,7 @@ static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)</div><div class='ctx'> 	__le64 *info;</div><div class='ctx'> 	int i, count;</div><div class='ctx'> </div><div class='del'>-	for (i = 0, count = 0; i &lt; nand-&gt;ecc.steps; i++, count += 2) {</div><div class='add'>+	for (i = 0, count = 0; i &lt; nand-&gt;ecc.steps; i++, count += (2 + nand-&gt;ecc.bytes)) {</div><div class='ctx'> 		info = &amp;meson_chip-&gt;info_buf[i];</div><div class='ctx'> 		oob_buf[count] = *info;</div><div class='ctx'> 		oob_buf[count + 1] = *info &gt;&gt; 8;</div><div class='hunk'>@@ -1154,7 +1156,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc)</div><div class='ctx'> 		return PTR_ERR(nfc-&gt;nand_clk);</div><div class='ctx'> </div><div class='ctx'> 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */</div><div class='del'>-	writel(CLK_SELECT_NAND | readl(nfc-&gt;reg_clk),</div><div class='add'>+	writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_SELECT_FIX_PLL2,</div><div class='ctx'> 	       nfc-&gt;reg_clk);</div><div class='ctx'> </div><div class='ctx'> 	ret = clk_prepare_enable(nfc-&gt;core_clk);</div><div class='head'>diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c<br/>index 9e24bedffd89..3b3ce2926f5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/nand_base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/nand_base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/nand_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/nand_base.c</a></div><div class='hunk'>@@ -366,6 +366,10 @@ static int nand_check_wp(struct nand_chip *chip)</div><div class='ctx'> 	if (chip-&gt;options &amp; NAND_BROKEN_XD)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	/* controller responsible for NAND write protect */</div><div class='add'>+	if (chip-&gt;controller-&gt;controller_wp)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	/* Check the WP bit */</div><div class='ctx'> 	ret = nand_status_op(chip, &amp;status);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -1207,6 +1211,23 @@ static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,</div><div class='ctx'> 	return nand_exec_op(chip, &amp;op);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void rawnand_cap_cont_reads(struct nand_chip *chip)</div><div class='add'>+{</div><div class='add'>+	struct nand_memory_organization *memorg;</div><div class='add'>+	unsigned int pages_per_lun, first_lun, last_lun;</div><div class='add'>+</div><div class='add'>+	memorg = nanddev_get_memorg(&amp;chip-&gt;base);</div><div class='add'>+	pages_per_lun = memorg-&gt;pages_per_eraseblock * memorg-&gt;eraseblocks_per_lun;</div><div class='add'>+	first_lun = chip-&gt;cont_read.first_page / pages_per_lun;</div><div class='add'>+	last_lun = chip-&gt;cont_read.last_page / pages_per_lun;</div><div class='add'>+</div><div class='add'>+	/* Prevent sequential cache reads across LUN boundaries */</div><div class='add'>+	if (first_lun != last_lun)</div><div class='add'>+		chip-&gt;cont_read.pause_page = first_lun * pages_per_lun + pages_per_lun - 1;</div><div class='add'>+	else</div><div class='add'>+		chip-&gt;cont_read.pause_page = chip-&gt;cont_read.last_page;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page,</div><div class='ctx'> 					  unsigned int offset_in_page, void *buf,</div><div class='ctx'> 					  unsigned int len, bool check_only)</div><div class='hunk'>@@ -1225,7 +1246,7 @@ static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int p</div><div class='ctx'> 		NAND_OP_DATA_IN(len, buf, 0),</div><div class='ctx'> 	};</div><div class='ctx'> 	struct nand_op_instr cont_instrs[] = {</div><div class='del'>-		NAND_OP_CMD(page == chip-&gt;cont_read.last_page ?</div><div class='add'>+		NAND_OP_CMD(page == chip-&gt;cont_read.pause_page ?</div><div class='ctx'> 			    NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ,</div><div class='ctx'> 			    NAND_COMMON_TIMING_NS(conf, tWB_max)),</div><div class='ctx'> 		NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),</div><div class='hunk'>@@ -1262,16 +1283,29 @@ static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int p</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (page == chip-&gt;cont_read.first_page)</div><div class='del'>-		return nand_exec_op(chip, &amp;start_op);</div><div class='add'>+		ret = nand_exec_op(chip, &amp;start_op);</div><div class='ctx'> 	else</div><div class='del'>-		return nand_exec_op(chip, &amp;cont_op);</div><div class='add'>+		ret = nand_exec_op(chip, &amp;cont_op);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (!chip-&gt;cont_read.ongoing)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (page == chip-&gt;cont_read.pause_page &amp;&amp;</div><div class='add'>+	    page != chip-&gt;cont_read.last_page) {</div><div class='add'>+		chip-&gt;cont_read.first_page = chip-&gt;cont_read.pause_page + 1;</div><div class='add'>+		rawnand_cap_cont_reads(chip);</div><div class='add'>+	} else if (page == chip-&gt;cont_read.last_page) {</div><div class='add'>+		chip-&gt;cont_read.ongoing = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page)</div><div class='ctx'> {</div><div class='del'>-	return chip-&gt;cont_read.ongoing &amp;&amp;</div><div class='del'>-		page &gt;= chip-&gt;cont_read.first_page &amp;&amp;</div><div class='del'>-		page &lt;= chip-&gt;cont_read.last_page;</div><div class='add'>+	return chip-&gt;cont_read.ongoing &amp;&amp; page &gt;= chip-&gt;cont_read.first_page;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1493,7 +1527,8 @@ static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,</div><div class='ctx'> 			    NAND_COMMON_TIMING_NS(conf, tWB_max)),</div><div class='ctx'> 		NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0),</div><div class='ctx'> 	};</div><div class='del'>-	struct nand_operation op = NAND_OPERATION(chip-&gt;cur_cs, instrs);</div><div class='add'>+	struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip-&gt;cur_cs,</div><div class='add'>+							      instrs);</div><div class='ctx'> 	int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);</div><div class='ctx'> </div><div class='ctx'> 	if (naddrs &lt; 0)</div><div class='hunk'>@@ -1916,7 +1951,8 @@ int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)</div><div class='ctx'> 			NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max),</div><div class='ctx'> 					 0),</div><div class='ctx'> 		};</div><div class='del'>-		struct nand_operation op = NAND_OPERATION(chip-&gt;cur_cs, instrs);</div><div class='add'>+		struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip-&gt;cur_cs,</div><div class='add'>+								      instrs);</div><div class='ctx'> </div><div class='ctx'> 		if (chip-&gt;options &amp; NAND_ROW_ADDR_3)</div><div class='ctx'> 			instrs[1].ctx.addr.naddrs++;</div><div class='hunk'>@@ -3430,21 +3466,42 @@ static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page,</div><div class='ctx'> 				      u32 readlen, int col)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtd_info *mtd = nand_to_mtd(chip);</div><div class='add'>+	unsigned int end_page, end_col;</div><div class='add'>+</div><div class='add'>+	chip-&gt;cont_read.ongoing = false;</div><div class='ctx'> </div><div class='ctx'> 	if (!chip-&gt;controller-&gt;supported_op.cont_read)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if ((col &amp;&amp; col + readlen &lt; (3 * mtd-&gt;writesize)) ||</div><div class='del'>-	    (!col &amp;&amp; readlen &lt; (2 * mtd-&gt;writesize))) {</div><div class='del'>-		chip-&gt;cont_read.ongoing = false;</div><div class='add'>+	end_page = DIV_ROUND_UP(col + readlen, mtd-&gt;writesize);</div><div class='add'>+	end_col = (col + readlen) % mtd-&gt;writesize;</div><div class='add'>+</div><div class='add'>+	if (col)</div><div class='add'>+		page++;</div><div class='add'>+</div><div class='add'>+	if (end_col &amp;&amp; end_page)</div><div class='add'>+		end_page--;</div><div class='add'>+</div><div class='add'>+	if (page + 1 &gt; end_page)</div><div class='ctx'> 		return;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	chip-&gt;cont_read.ongoing = true;</div><div class='ctx'> 	chip-&gt;cont_read.first_page = page;</div><div class='del'>-	if (col)</div><div class='add'>+	chip-&gt;cont_read.last_page = end_page;</div><div class='add'>+	chip-&gt;cont_read.ongoing = true;</div><div class='add'>+</div><div class='add'>+	rawnand_cap_cont_reads(chip);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page)</div><div class='add'>+{</div><div class='add'>+	if (!chip-&gt;cont_read.ongoing || page != chip-&gt;cont_read.first_page)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	chip-&gt;cont_read.first_page++;</div><div class='add'>+	if (chip-&gt;cont_read.first_page == chip-&gt;cont_read.pause_page)</div><div class='ctx'> 		chip-&gt;cont_read.first_page++;</div><div class='del'>-	chip-&gt;cont_read.last_page = page + ((readlen &gt;&gt; chip-&gt;page_shift) &amp; chip-&gt;pagemask);</div><div class='add'>+	if (chip-&gt;cont_read.first_page &gt;= chip-&gt;cont_read.last_page)</div><div class='add'>+		chip-&gt;cont_read.ongoing = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3621,6 +3678,8 @@ read_retry:</div><div class='ctx'> 			buf += bytes;</div><div class='ctx'> 			max_bitflips = max_t(unsigned int, max_bitflips,</div><div class='ctx'> 					     chip-&gt;pagecache.bitflips);</div><div class='add'>+</div><div class='add'>+			rawnand_cont_read_skip_first_page(chip, page);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		readlen -= bytes;</div><div class='hunk'>@@ -5125,6 +5184,14 @@ static void rawnand_late_check_supported_ops(struct nand_chip *chip)</div><div class='ctx'> 	/* The supported_op fields should not be set by individual drivers */</div><div class='ctx'> 	WARN_ON_ONCE(chip-&gt;controller-&gt;supported_op.cont_read);</div><div class='ctx'> </div><div class='add'>+	/*</div><div class='add'>+	 * Too many devices do not support sequential cached reads with on-die</div><div class='add'>+	 * ECC correction enabled, so in this case refuse to perform the</div><div class='add'>+	 * automation.</div><div class='add'>+	 */</div><div class='add'>+	if (chip-&gt;ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (!nand_has_exec_op(chip))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c<br/>index c506e92a3e45..1c76ee98efb7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/pl35x-nand-controller.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/pl35x-nand-controller.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/pl35x-nand-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/pl35x-nand-controller.c</a></div><div class='hunk'>@@ -128,7 +128,7 @@ struct pl35x_nand {</div><div class='ctx'>  * @conf_regs: SMC configuration registers for command phase</div><div class='ctx'>  * @io_regs: NAND data registers for data phase</div><div class='ctx'>  * @controller: Core NAND controller structure</div><div class='del'>- * @chip: NAND chip information structure</div><div class='add'>+ * @chips: List of connected NAND chips</div><div class='ctx'>  * @selected_chip: NAND chip currently selected by the controller</div><div class='ctx'>  * @assigned_cs: List of assigned CS</div><div class='ctx'>  * @ecc_buf: Temporary buffer to extract ECC bytes</div><div class='head'>diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mtd/nand/raw/rockchip-nand-controller.c<br/>index 596cf9a78274..7baaef69d70a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/rockchip-nand-controller.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/rockchip-nand-controller.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/rockchip-nand-controller.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/rockchip-nand-controller.c</a></div><div class='hunk'>@@ -98,7 +98,7 @@ enum nfc_type {</div><div class='ctx'>  * @high: ECC count high bit index at register.</div><div class='ctx'>  * @high_mask: mask bit</div><div class='ctx'>  */</div><div class='del'>-struct ecc_cnt_status {</div><div class='add'>+struct rk_ecc_cnt_status {</div><div class='ctx'> 	u8 err_flag_bit;</div><div class='ctx'> 	u8 low;</div><div class='ctx'> 	u8 low_mask;</div><div class='hunk'>@@ -108,6 +108,7 @@ struct ecc_cnt_status {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct nfc_cfg: Rockchip NAND controller configuration</div><div class='ctx'>  * @type: NFC version</div><div class='ctx'>  * @ecc_strengths: ECC strengths</div><div class='ctx'>  * @ecc_cfgs: ECC config values</div><div class='hunk'>@@ -144,8 +145,8 @@ struct nfc_cfg {</div><div class='ctx'> 	u32 int_st_off;</div><div class='ctx'> 	u32 oob0_off;</div><div class='ctx'> 	u32 oob1_off;</div><div class='del'>-	struct ecc_cnt_status ecc0;</div><div class='del'>-	struct ecc_cnt_status ecc1;</div><div class='add'>+	struct rk_ecc_cnt_status ecc0;</div><div class='add'>+	struct rk_ecc_cnt_status ecc1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct rk_nfc_nand_chip {</div><div class='head'>diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c<br/>index 3d3d5c9814ff..48c1d0eb66ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/s3c2410.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/s3c2410.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/s3c2410.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/s3c2410.c</a></div><div class='hunk'>@@ -105,7 +105,6 @@ struct s3c2410_nand_info;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct s3c2410_nand_mtd - driver MTD structure</div><div class='del'>- * @mtd: The MTD instance to pass to the MTD layer.</div><div class='ctx'>  * @chip: The NAND chip information.</div><div class='ctx'>  * @set: The platform information supplied for this set of NAND chips.</div><div class='ctx'>  * @info: Link back to the hardware information.</div><div class='hunk'>@@ -145,7 +144,6 @@ enum s3c_nand_clk_state {</div><div class='ctx'>  * @clk_rate: The clock rate from @clk.</div><div class='ctx'>  * @clk_state: The current clock state.</div><div class='ctx'>  * @cpu_type: The exact type of this controller.</div><div class='del'>- * @freq_transition: CPUFreq notifier block</div><div class='ctx'>  */</div><div class='ctx'> struct s3c2410_nand_info {</div><div class='ctx'> 	/* mtd info */</div><div class='head'>diff --git a/drivers/mtd/nand/raw/txx9ndfmc.c b/drivers/mtd/nand/raw/txx9ndfmc.c<br/>index eddcc0728a67..37f79c019a72 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/txx9ndfmc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/raw/txx9ndfmc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/raw/txx9ndfmc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/raw/txx9ndfmc.c</a></div><div class='hunk'>@@ -276,7 +276,7 @@ static const struct nand_controller_ops txx9ndfmc_controller_ops = {</div><div class='ctx'> 	.attach_chip = txx9ndfmc_attach_chip,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int __init txx9ndfmc_probe(struct platform_device *dev)</div><div class='add'>+static int txx9ndfmc_probe(struct platform_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct txx9ndfmc_platform_data *plat = dev_get_platdata(&amp;dev-&gt;dev);</div><div class='ctx'> 	int hold, spw;</div><div class='hunk'>@@ -369,13 +369,11 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int __exit txx9ndfmc_remove(struct platform_device *dev)</div><div class='add'>+static void txx9ndfmc_remove(struct platform_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);</div><div class='ctx'> 	int ret, i;</div><div class='ctx'> </div><div class='del'>-	if (!drvdata)</div><div class='del'>-		return 0;</div><div class='ctx'> 	for (i = 0; i &lt; MAX_TXX9NDFMC_DEV; i++) {</div><div class='ctx'> 		struct mtd_info *mtd = drvdata-&gt;mtds[i];</div><div class='ctx'> 		struct nand_chip *chip;</div><div class='hunk'>@@ -392,7 +390,6 @@ static int __exit txx9ndfmc_remove(struct platform_device *dev)</div><div class='ctx'> 		kfree(txx9_priv-&gt;mtdname);</div><div class='ctx'> 		kfree(txx9_priv);</div><div class='ctx'> 	}</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM</div><div class='hunk'>@@ -407,14 +404,14 @@ static int txx9ndfmc_resume(struct platform_device *dev)</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver txx9ndfmc_driver = {</div><div class='del'>-	.remove		= __exit_p(txx9ndfmc_remove),</div><div class='add'>+	.probe		= txx9ndfmc_probe,</div><div class='add'>+	.remove_new	= txx9ndfmc_remove,</div><div class='ctx'> 	.resume		= txx9ndfmc_resume,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "txx9ndfmc",</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='del'>-</div><div class='del'>-module_platform_driver_probe(txx9ndfmc_driver, txx9ndfmc_probe);</div><div class='add'>+module_platform_driver(txx9ndfmc_driver);</div><div class='ctx'> </div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");</div><div class='head'>diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c<br/>index 849ccfedbc72..e0b6715e5dfe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/nand/spi/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/nand/spi/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/nand/spi/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/nand/spi/core.c</a></div><div class='hunk'>@@ -974,7 +974,7 @@ static int spinand_manufacturer_match(struct spinand_device *spinand,</div><div class='ctx'> 		spinand-&gt;manufacturer = manufacturer;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='del'>-	return -ENOTSUPP;</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int spinand_id_detect(struct spinand_device *spinand)</div><div class='head'>diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c<br/>index e13b8d2dd50a..45d1153a04a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/atmel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/atmel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/atmel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/atmel.c</a></div><div class='hunk'>@@ -16,12 +16,12 @@</div><div class='ctx'>  * is to unlock the whole flash array on startup. Therefore, we have to support</div><div class='ctx'>  * exactly this operation.</div><div class='ctx'>  */</div><div class='del'>-static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -37,7 +37,7 @@ static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='hunk'>@@ -69,7 +69,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {</div><div class='ctx'>  * Return: 0 on success, -error otherwise.</div><div class='ctx'>  */</div><div class='ctx'> static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-					   uint64_t len, bool is_protect)</div><div class='add'>+					   u64 len, bool is_protect)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u8 sr;</div><div class='hunk'>@@ -118,20 +118,18 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,</div><div class='ctx'> 	return spi_nor_write_sr(nor, nor-&gt;bouncebuf, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-				    uint64_t len)</div><div class='add'>+static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return atmel_nor_set_global_protection(nor, ofs, len, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-				      uint64_t len)</div><div class='add'>+static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return atmel_nor_set_global_protection(nor, ofs, len, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-					 uint64_t len)</div><div class='add'>+					 u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c<br/>index 1c443fe568cf..4129764fad8c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/core.c</a></div><div class='hunk'>@@ -1060,24 +1060,32 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * spi_nor_erase_chip() - Erase the entire flash memory.</div><div class='add'>+ * spi_nor_erase_die() - Erase the entire die.</div><div class='ctx'>  * @nor:	pointer to 'struct spi_nor'.</div><div class='add'>+ * @addr:	address of the die.</div><div class='add'>+ * @die_size:	size of the die.</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0 on success, -errno otherwise.</div><div class='ctx'>  */</div><div class='del'>-static int spi_nor_erase_chip(struct spi_nor *nor)</div><div class='add'>+static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)</div><div class='ctx'> {</div><div class='add'>+	bool multi_die = nor-&gt;mtd.size != die_size;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(nor-&gt;dev, " %lldKiB\n", (long long)(nor-&gt;mtd.size &gt;&gt; 10));</div><div class='add'>+	dev_dbg(nor-&gt;dev, " %lldKiB\n", (long long)(die_size &gt;&gt; 10));</div><div class='ctx'> </div><div class='ctx'> 	if (nor-&gt;spimem) {</div><div class='del'>-		struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP;</div><div class='add'>+		struct spi_mem_op op =</div><div class='add'>+			SPI_NOR_DIE_ERASE_OP(nor-&gt;params-&gt;die_erase_opcode,</div><div class='add'>+					     nor-&gt;addr_nbytes, addr, multi_die);</div><div class='ctx'> </div><div class='ctx'> 		spi_nor_spimem_setup_op(nor, &amp;op, nor-&gt;reg_proto);</div><div class='ctx'> </div><div class='ctx'> 		ret = spi_mem_exec_op(nor-&gt;spimem, &amp;op);</div><div class='ctx'> 	} else {</div><div class='add'>+		if (multi_die)</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='ctx'> 		ret = spi_nor_controller_ops_write_reg(nor,</div><div class='ctx'> 						       SPINOR_OP_CHIP_ERASE,</div><div class='ctx'> 						       NULL, 0);</div><div class='hunk'>@@ -1792,6 +1800,51 @@ destroy_erase_cmd_list:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr,</div><div class='add'>+			      size_t len, size_t die_size)</div><div class='add'>+{</div><div class='add'>+	unsigned long timeout;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Scale the timeout linearly with the size of the flash, with</div><div class='add'>+	 * a minimum calibrated to an old 2MB flash. We could try to</div><div class='add'>+	 * pull these from CFI/SFDP, but these values should be good</div><div class='add'>+	 * enough for now.</div><div class='add'>+	 */</div><div class='add'>+	timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,</div><div class='add'>+		      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *</div><div class='add'>+		      (unsigned long)(nor-&gt;mtd.size / SZ_2M));</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		ret = spi_nor_lock_device(nor);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = spi_nor_write_enable(nor);</div><div class='add'>+		if (ret) {</div><div class='add'>+			spi_nor_unlock_device(nor);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = spi_nor_erase_die(nor, addr, die_size);</div><div class='add'>+</div><div class='add'>+		spi_nor_unlock_device(nor);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		addr += die_size;</div><div class='add'>+		len -= die_size;</div><div class='add'>+</div><div class='add'>+	} while (len);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * Erase an address range on the nor chip.  The address range may extend</div><div class='ctx'>  * one or more erase sectors. Return an error if there is a problem erasing.</div><div class='hunk'>@@ -1799,8 +1852,10 @@ destroy_erase_cmd_list:</div><div class='ctx'> static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_nor *nor = mtd_to_spi_nor(mtd);</div><div class='del'>-	u32 addr, len;</div><div class='del'>-	uint32_t rem;</div><div class='add'>+	u8 n_dice = nor-&gt;params-&gt;n_dice;</div><div class='add'>+	bool multi_die_erase = false;</div><div class='add'>+	u32 addr, len, rem;</div><div class='add'>+	size_t die_size;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(nor-&gt;dev, "at 0x%llx, len %lld\n", (long long)instr-&gt;addr,</div><div class='hunk'>@@ -1815,39 +1870,22 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)</div><div class='ctx'> 	addr = instr-&gt;addr;</div><div class='ctx'> 	len = instr-&gt;len;</div><div class='ctx'> </div><div class='add'>+	if (n_dice) {</div><div class='add'>+		die_size = div_u64(mtd-&gt;size, n_dice);</div><div class='add'>+		if (!(len &amp; (die_size - 1)) &amp;&amp; !(addr &amp; (die_size - 1)))</div><div class='add'>+			multi_die_erase = true;</div><div class='add'>+	} else {</div><div class='add'>+		die_size = mtd-&gt;size;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = spi_nor_prep_and_lock_pe(nor, instr-&gt;addr, instr-&gt;len);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	/* whole-chip erase? */</div><div class='del'>-	if (len == mtd-&gt;size &amp;&amp; !(nor-&gt;flags &amp; SNOR_F_NO_OP_CHIP_ERASE)) {</div><div class='del'>-		unsigned long timeout;</div><div class='del'>-</div><div class='del'>-		ret = spi_nor_lock_device(nor);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto erase_err;</div><div class='del'>-</div><div class='del'>-		ret = spi_nor_write_enable(nor);</div><div class='del'>-		if (ret) {</div><div class='del'>-			spi_nor_unlock_device(nor);</div><div class='del'>-			goto erase_err;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		ret = spi_nor_erase_chip(nor);</div><div class='del'>-		spi_nor_unlock_device(nor);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto erase_err;</div><div class='del'>-</div><div class='del'>-		/*</div><div class='del'>-		 * Scale the timeout linearly with the size of the flash, with</div><div class='del'>-		 * a minimum calibrated to an old 2MB flash. We could try to</div><div class='del'>-		 * pull these from CFI/SFDP, but these values should be good</div><div class='del'>-		 * enough for now.</div><div class='del'>-		 */</div><div class='del'>-		timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,</div><div class='del'>-			      CHIP_ERASE_2MB_READY_WAIT_JIFFIES *</div><div class='del'>-			      (unsigned long)(mtd-&gt;size / SZ_2M));</div><div class='del'>-		ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);</div><div class='add'>+	/* chip (die) erase? */</div><div class='add'>+	if ((len == mtd-&gt;size &amp;&amp; !(nor-&gt;flags &amp; SNOR_F_NO_OP_CHIP_ERASE)) ||</div><div class='add'>+	    multi_die_erase) {</div><div class='add'>+		ret = spi_nor_erase_dice(nor, addr, len, die_size);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto erase_err;</div><div class='ctx'> </div><div class='hunk'>@@ -2146,7 +2184,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,</div><div class='ctx'> 		if (is_power_of_2(page_size)) {</div><div class='ctx'> 			page_offset = addr &amp; (page_size - 1);</div><div class='ctx'> 		} else {</div><div class='del'>-			uint64_t aux = addr;</div><div class='add'>+			u64 aux = addr;</div><div class='ctx'> </div><div class='ctx'> 			page_offset = do_div(aux, page_size);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2850,9 +2888,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)</div><div class='ctx'> 			nor-&gt;flags |= SNOR_F_HAS_SR_BP3_BIT6;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (flags &amp; NO_CHIP_ERASE)</div><div class='del'>-		nor-&gt;flags |= SNOR_F_NO_OP_CHIP_ERASE;</div><div class='del'>-</div><div class='ctx'> 	if (flags &amp; SPI_NOR_RWW &amp;&amp; nor-&gt;params-&gt;n_banks &gt; 1 &amp;&amp;</div><div class='ctx'> 	    !nor-&gt;controller_ops)</div><div class='ctx'> 		nor-&gt;flags |= SNOR_F_RWW;</div><div class='hunk'>@@ -2897,17 +2932,22 @@ static int spi_nor_late_init_params(struct spi_nor *nor)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Needed by some flashes late_init hooks. */</div><div class='add'>+	spi_nor_init_flags(nor);</div><div class='add'>+</div><div class='ctx'> 	if (nor-&gt;info-&gt;fixups &amp;&amp; nor-&gt;info-&gt;fixups-&gt;late_init) {</div><div class='ctx'> 		ret = nor-&gt;info-&gt;fixups-&gt;late_init(nor);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!nor-&gt;params-&gt;die_erase_opcode)</div><div class='add'>+		nor-&gt;params-&gt;die_erase_opcode = SPINOR_OP_CHIP_ERASE;</div><div class='add'>+</div><div class='ctx'> 	/* Default method kept for backward compatibility. */</div><div class='ctx'> 	if (!params-&gt;set_4byte_addr_mode)</div><div class='ctx'> 		params-&gt;set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;</div><div class='ctx'> </div><div class='del'>-	spi_nor_init_flags(nor);</div><div class='ctx'> 	spi_nor_init_fixup_flags(nor);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -3145,8 +3185,20 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)</div><div class='ctx'> 	struct spi_nor_flash_parameter *params = nor-&gt;params;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	if (enable) {</div><div class='add'>+		/*</div><div class='add'>+		 * If the RESET# pin isn't hooked up properly, or the system</div><div class='add'>+		 * otherwise doesn't perform a reset command in the boot</div><div class='add'>+		 * sequence, it's impossible to 100% protect against unexpected</div><div class='add'>+		 * reboots (e.g., crashes). Warn the user (or hopefully, system</div><div class='add'>+		 * designer) that this is bad.</div><div class='add'>+		 */</div><div class='add'>+		WARN_ONCE(nor-&gt;flags &amp; SNOR_F_BROKEN_RESET,</div><div class='add'>+			  "enabling reset hack; may not recover from unexpected reboots\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = params-&gt;set_4byte_addr_mode(nor, enable);</div><div class='del'>-	if (ret &amp;&amp; ret != -ENOTSUPP)</div><div class='add'>+	if (ret &amp;&amp; ret != -EOPNOTSUPP)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='hunk'>@@ -3193,20 +3245,8 @@ static int spi_nor_init(struct spi_nor *nor)</div><div class='ctx'> </div><div class='ctx'> 	if (nor-&gt;addr_nbytes == 4 &amp;&amp;</div><div class='ctx'> 	    nor-&gt;read_proto != SNOR_PROTO_8_8_8_DTR &amp;&amp;</div><div class='del'>-	    !(nor-&gt;flags &amp; SNOR_F_4B_OPCODES)) {</div><div class='del'>-		/*</div><div class='del'>-		 * If the RESET# pin isn't hooked up properly, or the system</div><div class='del'>-		 * otherwise doesn't perform a reset command in the boot</div><div class='del'>-		 * sequence, it's impossible to 100% protect against unexpected</div><div class='del'>-		 * reboots (e.g., crashes). Warn the user (or hopefully, system</div><div class='del'>-		 * designer) that this is bad.</div><div class='del'>-		 */</div><div class='del'>-		WARN_ONCE(nor-&gt;flags &amp; SNOR_F_BROKEN_RESET,</div><div class='del'>-			  "enabling reset hack; may not recover from unexpected reboots\n");</div><div class='del'>-		err = spi_nor_set_4byte_addr_mode(nor, true);</div><div class='del'>-		if (err)</div><div class='del'>-			return err;</div><div class='del'>-	}</div><div class='add'>+	    !(nor-&gt;flags &amp; SNOR_F_4B_OPCODES))</div><div class='add'>+		return spi_nor_set_4byte_addr_mode(nor, true);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3237,7 +3277,8 @@ static void spi_nor_soft_reset(struct spi_nor *nor)</div><div class='ctx'> </div><div class='ctx'> 	ret = spi_mem_exec_op(nor-&gt;spimem, &amp;op);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		dev_warn(nor-&gt;dev, "Software reset failed: %d\n", ret);</div><div class='add'>+		if (ret != -EOPNOTSUPP)</div><div class='add'>+			dev_warn(nor-&gt;dev, "Software reset failed: %d\n", ret);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3452,9 +3493,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,</div><div class='ctx'> {</div><div class='ctx'> 	const struct flash_info *info;</div><div class='ctx'> 	struct device *dev = nor-&gt;dev;</div><div class='del'>-	struct mtd_info *mtd = &amp;nor-&gt;mtd;</div><div class='ctx'> 	int ret;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='ctx'> 	ret = spi_nor_check(nor);</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -3518,25 +3557,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,</div><div class='ctx'> 	/* No mtd_info fields should be used up to this point. */</div><div class='ctx'> 	spi_nor_set_mtd_info(nor);</div><div class='ctx'> </div><div class='del'>-	dev_info(dev, "%s (%lld Kbytes)\n", info-&gt;name,</div><div class='del'>-			(long long)mtd-&gt;size &gt;&gt; 10);</div><div class='del'>-</div><div class='del'>-	dev_dbg(dev,</div><div class='del'>-		"mtd .name = %s, .size = 0x%llx (%lldMiB), "</div><div class='del'>-		".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",</div><div class='del'>-		mtd-&gt;name, (long long)mtd-&gt;size, (long long)(mtd-&gt;size &gt;&gt; 20),</div><div class='del'>-		mtd-&gt;erasesize, mtd-&gt;erasesize / 1024, mtd-&gt;numeraseregions);</div><div class='del'>-</div><div class='del'>-	if (mtd-&gt;numeraseregions)</div><div class='del'>-		for (i = 0; i &lt; mtd-&gt;numeraseregions; i++)</div><div class='del'>-			dev_dbg(dev,</div><div class='del'>-				"mtd.eraseregions[%d] = { .offset = 0x%llx, "</div><div class='del'>-				".erasesize = 0x%.8x (%uKiB), "</div><div class='del'>-				".numblocks = %d }\n",</div><div class='del'>-				i, (long long)mtd-&gt;eraseregions[i].offset,</div><div class='del'>-				mtd-&gt;eraseregions[i].erasesize,</div><div class='del'>-				mtd-&gt;eraseregions[i].erasesize / 1024,</div><div class='del'>-				mtd-&gt;eraseregions[i].numblocks);</div><div class='add'>+	dev_dbg(dev, "Manufacturer and device ID: %*phN\n",</div><div class='add'>+		SPI_NOR_MAX_ID_LEN, nor-&gt;id);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(spi_nor_scan);</div><div class='head'>diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h<br/>index 93cd2fc3606d..d36c0e072954 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/core.h</a></div><div class='hunk'>@@ -85,9 +85,9 @@</div><div class='ctx'> 		   SPI_MEM_OP_NO_DUMMY,					\</div><div class='ctx'> 		   SPI_MEM_OP_NO_DATA)</div><div class='ctx'> </div><div class='del'>-#define SPI_NOR_CHIP_ERASE_OP						\</div><div class='del'>-	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0),		\</div><div class='del'>-		   SPI_MEM_OP_NO_ADDR,					\</div><div class='add'>+#define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice)		\</div><div class='add'>+	SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),				\</div><div class='add'>+		   SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0),	\</div><div class='ctx'> 		   SPI_MEM_OP_NO_DUMMY,					\</div><div class='ctx'> 		   SPI_MEM_OP_NO_DATA)</div><div class='ctx'> </div><div class='hunk'>@@ -293,9 +293,9 @@ struct spi_nor_erase_map {</div><div class='ctx'>  * @is_locked:	check if a region of the SPI NOR is completely locked</div><div class='ctx'>  */</div><div class='ctx'> struct spi_nor_locking_ops {</div><div class='del'>-	int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);</div><div class='del'>-	int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);</div><div class='del'>-	int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);</div><div class='add'>+	int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len);</div><div class='add'>+	int (*unlock)(struct spi_nor *nor, loff_t ofs, u64 len);</div><div class='add'>+	int (*is_locked)(struct spi_nor *nor, loff_t ofs, u64 len);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -362,6 +362,7 @@ struct spi_nor_otp {</div><div class='ctx'>  *			command in octal DTR mode.</div><div class='ctx'>  * @n_banks:		number of banks.</div><div class='ctx'>  * @n_dice:		number of dice in the flash memory.</div><div class='add'>+ * @die_erase_opcode:	die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.</div><div class='ctx'>  * @vreg_offset:	volatile register offset for each die.</div><div class='ctx'>  * @hwcaps:		describes the read and page program hardware</div><div class='ctx'>  *			capabilities.</div><div class='hunk'>@@ -399,6 +400,7 @@ struct spi_nor_flash_parameter {</div><div class='ctx'> 	u8				rdsr_addr_nbytes;</div><div class='ctx'> 	u8				n_banks;</div><div class='ctx'> 	u8				n_dice;</div><div class='add'>+	u8				die_erase_opcode;</div><div class='ctx'> 	u32				*vreg_offset;</div><div class='ctx'> </div><div class='ctx'> 	struct spi_nor_hwcaps		hwcaps;</div><div class='hunk'>@@ -463,7 +465,7 @@ struct spi_nor_id {</div><div class='ctx'>  * struct flash_info - SPI NOR flash_info entry.</div><div class='ctx'>  * @id:   pointer to struct spi_nor_id or NULL, which means "no ID" (mostly</div><div class='ctx'>  *        older chips).</div><div class='del'>- * @name: the name of the flash.</div><div class='add'>+ * @name: (obsolete) the name of the flash. Do not set it for new additions.</div><div class='ctx'>  * @size:           the size of the flash in bytes.</div><div class='ctx'>  * @sector_size:    (optional) the size listed here is what works with</div><div class='ctx'>  *                  SPINOR_OP_SE, which isn't necessarily called a "sector" by</div><div class='hunk'>@@ -487,7 +489,6 @@ struct spi_nor_id {</div><div class='ctx'>  *                            Usually these will power-up in a write-protected</div><div class='ctx'>  *                            state.</div><div class='ctx'>  *   SPI_NOR_NO_ERASE:        no erase command needed.</div><div class='del'>- *   NO_CHIP_ERASE:           chip does not support chip erase.</div><div class='ctx'>  *   SPI_NOR_NO_FR:           can't do fastread.</div><div class='ctx'>  *   SPI_NOR_QUAD_PP:         flash supports Quad Input Page Program.</div><div class='ctx'>  *   SPI_NOR_RWW:             flash supports reads while write.</div><div class='hunk'>@@ -537,10 +538,9 @@ struct flash_info {</div><div class='ctx'> #define SPI_NOR_BP3_SR_BIT6		BIT(4)</div><div class='ctx'> #define SPI_NOR_SWP_IS_VOLATILE		BIT(5)</div><div class='ctx'> #define SPI_NOR_NO_ERASE		BIT(6)</div><div class='del'>-#define NO_CHIP_ERASE			BIT(7)</div><div class='del'>-#define SPI_NOR_NO_FR			BIT(8)</div><div class='del'>-#define SPI_NOR_QUAD_PP			BIT(9)</div><div class='del'>-#define SPI_NOR_RWW			BIT(10)</div><div class='add'>+#define SPI_NOR_NO_FR			BIT(7)</div><div class='add'>+#define SPI_NOR_QUAD_PP			BIT(8)</div><div class='add'>+#define SPI_NOR_RWW			BIT(9)</div><div class='ctx'> </div><div class='ctx'> 	u8 no_sfdp_flags;</div><div class='ctx'> #define SPI_NOR_SKIP_SFDP		BIT(0)</div><div class='head'>diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c<br/>index 6e163cb5b478..2dbda6b6938a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/debugfs.c</a></div><div class='hunk'>@@ -138,7 +138,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data)</div><div class='ctx'> </div><div class='ctx'> 	if (!(nor-&gt;flags &amp; SNOR_F_NO_OP_CHIP_ERASE)) {</div><div class='ctx'> 		string_get_size(params-&gt;size, 1, STRING_UNITS_2, buf, sizeof(buf));</div><div class='del'>-		seq_printf(s, " %02x (%s)\n", SPINOR_OP_CHIP_ERASE, buf);</div><div class='add'>+		seq_printf(s, " %02x (%s)\n", nor-&gt;params-&gt;die_erase_opcode, buf);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	seq_puts(s, "\nsector map\n");</div><div class='head'>diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c<br/>index 8920547c12bf..3c6499fdb712 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/micron-st.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/micron-st.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/micron-st.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/micron-st.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> /* flash_info mfr_flag. Used to read proprietary FSR register. */</div><div class='ctx'> #define USE_FSR		BIT(0)</div><div class='ctx'> </div><div class='add'>+#define SPINOR_OP_MT_DIE_ERASE	0xc4	/* Chip (die) erase opcode */</div><div class='ctx'> #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */</div><div class='ctx'> #define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */</div><div class='ctx'> #define SPINOR_OP_MT_DTR_RD	0xfd	/* Fast Read opcode in DTR mode */</div><div class='hunk'>@@ -192,6 +193,50 @@ static struct spi_nor_fixups mt25qu512a_fixups = {</div><div class='ctx'> 	.post_bfpt = mt25qu512a_post_bfpt_fixup,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static int st_nor_four_die_late_init(struct spi_nor *nor)</div><div class='add'>+{</div><div class='add'>+	struct spi_nor_flash_parameter *params = nor-&gt;params;</div><div class='add'>+</div><div class='add'>+	params-&gt;die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;</div><div class='add'>+	params-&gt;n_dice = 4;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Unfortunately the die erase opcode does not have a 4-byte opcode</div><div class='add'>+	 * correspondent for these flashes. The SFDP 4BAIT table fails to</div><div class='add'>+	 * consider the die erase too. We're forced to enter in the 4 byte</div><div class='add'>+	 * address mode in order to benefit of the die erase.</div><div class='add'>+	 */</div><div class='add'>+	return spi_nor_set_4byte_addr_mode(nor, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int st_nor_two_die_late_init(struct spi_nor *nor)</div><div class='add'>+{</div><div class='add'>+	struct spi_nor_flash_parameter *params = nor-&gt;params;</div><div class='add'>+</div><div class='add'>+	params-&gt;die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;</div><div class='add'>+	params-&gt;n_dice = 2;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * Unfortunately the die erase opcode does not have a 4-byte opcode</div><div class='add'>+	 * correspondent for these flashes. The SFDP 4BAIT table fails to</div><div class='add'>+	 * consider the die erase too. We're forced to enter in the 4 byte</div><div class='add'>+	 * address mode in order to benefit of the die erase.</div><div class='add'>+	 */</div><div class='add'>+	return spi_nor_set_4byte_addr_mode(nor, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct spi_nor_fixups n25q00_fixups = {</div><div class='add'>+	.late_init = st_nor_four_die_late_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct spi_nor_fixups mt25q01_fixups = {</div><div class='add'>+	.late_init = st_nor_two_die_late_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static struct spi_nor_fixups mt25q02_fixups = {</div><div class='add'>+	.late_init = st_nor_four_die_late_init,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct flash_info st_nor_parts[] = {</div><div class='ctx'> 	{</div><div class='ctx'> 		.name = "m25p05-nonjedec",</div><div class='hunk'>@@ -366,16 +411,17 @@ static const struct flash_info st_nor_parts[] = {</div><div class='ctx'> 		.name = "n25q00",</div><div class='ctx'> 		.size = SZ_128M,</div><div class='ctx'> 		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |</div><div class='del'>-			 SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE,</div><div class='add'>+			 SPI_NOR_BP3_SR_BIT6,</div><div class='ctx'> 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,</div><div class='ctx'> 		.mfr_flags = USE_FSR,</div><div class='add'>+		.fixups = &amp;n25q00_fixups,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x20, 0xba, 0x22),</div><div class='ctx'> 		.name = "mt25ql02g",</div><div class='ctx'> 		.size = SZ_256M,</div><div class='del'>-		.flags = NO_CHIP_ERASE,</div><div class='ctx'> 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,</div><div class='ctx'> 		.mfr_flags = USE_FSR,</div><div class='add'>+		.fixups = &amp;mt25q02_fixups,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x20, 0xbb, 0x15),</div><div class='ctx'> 		.name = "n25q016a",</div><div class='hunk'>@@ -430,19 +476,24 @@ static const struct flash_info st_nor_parts[] = {</div><div class='ctx'> 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,</div><div class='ctx'> 		.mfr_flags = USE_FSR,</div><div class='ctx'> 	}, {</div><div class='add'>+		.id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),</div><div class='add'>+		.name = "mt25qu01g",</div><div class='add'>+		.mfr_flags = USE_FSR,</div><div class='add'>+		.fixups = &amp;mt25q01_fixups,</div><div class='add'>+	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x20, 0xbb, 0x21),</div><div class='ctx'> 		.name = "n25q00a",</div><div class='ctx'> 		.size = SZ_128M,</div><div class='del'>-		.flags = NO_CHIP_ERASE,</div><div class='ctx'> 		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,</div><div class='ctx'> 		.mfr_flags = USE_FSR,</div><div class='add'>+		.fixups = &amp;n25q00_fixups,</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x20, 0xbb, 0x22),</div><div class='ctx'> 		.name = "mt25qu02g",</div><div class='ctx'> 		.size = SZ_256M,</div><div class='del'>-		.flags = NO_CHIP_ERASE,</div><div class='ctx'> 		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,</div><div class='ctx'> 		.mfr_flags = USE_FSR,</div><div class='add'>+		.fixups = &amp;mt25q02_fixups,</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c<br/>index b3b11dfed789..57713de32832 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sfdp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/sfdp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sfdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sfdp.c</a></div><div class='hunk'>@@ -446,6 +446,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,</div><div class='ctx'> 	u32 dword;</div><div class='ctx'> 	u16 half;</div><div class='ctx'> 	u8 erase_mask;</div><div class='add'>+	u8 wait_states, mode_clocks, opcode;</div><div class='ctx'> </div><div class='ctx'> 	/* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */</div><div class='ctx'> 	if (bfpt_header-&gt;length &lt; BFPT_DWORD_MAX_JESD216)</div><div class='hunk'>@@ -631,6 +632,32 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,</div><div class='ctx'> 	if (bfpt_header-&gt;length == BFPT_DWORD_MAX_JESD216B)</div><div class='ctx'> 		return spi_nor_post_bfpt_fixups(nor, bfpt_header, &amp;bfpt);</div><div class='ctx'> </div><div class='add'>+	/* Parse 1-1-8 read instruction */</div><div class='add'>+	opcode = FIELD_GET(BFPT_DWORD17_RD_1_1_8_CMD, bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+	if (opcode) {</div><div class='add'>+		mode_clocks = FIELD_GET(BFPT_DWORD17_RD_1_1_8_MODE_CLOCKS,</div><div class='add'>+					bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+		wait_states = FIELD_GET(BFPT_DWORD17_RD_1_1_8_WAIT_STATES,</div><div class='add'>+					bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+		params-&gt;hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;</div><div class='add'>+		spi_nor_set_read_settings(&amp;params-&gt;reads[SNOR_CMD_READ_1_1_8],</div><div class='add'>+					  mode_clocks, wait_states, opcode,</div><div class='add'>+					  SNOR_PROTO_1_1_8);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Parse 1-8-8 read instruction */</div><div class='add'>+	opcode = FIELD_GET(BFPT_DWORD17_RD_1_8_8_CMD, bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+	if (opcode) {</div><div class='add'>+		mode_clocks = FIELD_GET(BFPT_DWORD17_RD_1_8_8_MODE_CLOCKS,</div><div class='add'>+					bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+		wait_states = FIELD_GET(BFPT_DWORD17_RD_1_8_8_WAIT_STATES,</div><div class='add'>+					bfpt.dwords[SFDP_DWORD(17)]);</div><div class='add'>+		params-&gt;hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;</div><div class='add'>+		spi_nor_set_read_settings(&amp;params-&gt;reads[SNOR_CMD_READ_1_8_8],</div><div class='add'>+					  mode_clocks, wait_states, opcode,</div><div class='add'>+					  SNOR_PROTO_1_8_8);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* 8D-8D-8D command extension. */</div><div class='ctx'> 	switch (bfpt.dwords[SFDP_DWORD(18)] &amp; BFPT_DWORD18_CMD_EXT_MASK) {</div><div class='ctx'> 	case BFPT_DWORD18_CMD_EXT_REP:</div><div class='hunk'>@@ -968,6 +995,8 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,</div><div class='ctx'> 		{ SNOR_HWCAPS_READ_1_1_1_DTR,	BIT(13) },</div><div class='ctx'> 		{ SNOR_HWCAPS_READ_1_2_2_DTR,	BIT(14) },</div><div class='ctx'> 		{ SNOR_HWCAPS_READ_1_4_4_DTR,	BIT(15) },</div><div class='add'>+		{ SNOR_HWCAPS_READ_1_1_8,	BIT(20) },</div><div class='add'>+		{ SNOR_HWCAPS_READ_1_8_8,	BIT(21) },</div><div class='ctx'> 	};</div><div class='ctx'> 	static const struct sfdp_4bait programs[] = {</div><div class='ctx'> 		{ SNOR_HWCAPS_PP,		BIT(6) },</div><div class='head'>diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h<br/>index 6eb99e1cdd61..da0fe5aa9bb0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sfdp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/sfdp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sfdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sfdp.h</a></div><div class='hunk'>@@ -118,6 +118,13 @@ struct sfdp_bfpt {</div><div class='ctx'> 	(BFPT_DWORD16_EN4B_EN4B | BFPT_DWORD16_EX4B_EX4B)</div><div class='ctx'> #define BFPT_DWORD16_SWRST_EN_RST		BIT(12)</div><div class='ctx'> </div><div class='add'>+#define BFPT_DWORD17_RD_1_1_8_CMD		GENMASK(31, 24)</div><div class='add'>+#define BFPT_DWORD17_RD_1_1_8_MODE_CLOCKS	GENMASK(23, 21)</div><div class='add'>+#define BFPT_DWORD17_RD_1_1_8_WAIT_STATES	GENMASK(20, 16)</div><div class='add'>+#define BFPT_DWORD17_RD_1_8_8_CMD		GENMASK(15, 8)</div><div class='add'>+#define BFPT_DWORD17_RD_1_8_8_MODE_CLOCKS	GENMASK(7, 5)</div><div class='add'>+#define BFPT_DWORD17_RD_1_8_8_WAIT_STATES	GENMASK(4, 0)</div><div class='add'>+</div><div class='ctx'> #define BFPT_DWORD18_CMD_EXT_MASK		GENMASK(30, 29)</div><div class='ctx'> #define BFPT_DWORD18_CMD_EXT_REP		(0x0UL &lt;&lt; 29) /* Repeat */</div><div class='ctx'> #define BFPT_DWORD18_CMD_EXT_INV		(0x1UL &lt;&lt; 29) /* Invert */</div><div class='head'>diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c<br/>index 12921344373d..6cc237c24e07 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/spansion.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/spansion.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/spansion.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/spansion.c</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> </div><div class='ctx'> #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */</div><div class='ctx'> #define SPINOR_OP_CLPEF		0x82	/* Clear program/erase failure flags */</div><div class='add'>+#define SPINOR_OP_CYPRESS_DIE_ERASE		0x61	/* Chip (die) erase */</div><div class='ctx'> #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */</div><div class='ctx'> #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */</div><div class='ctx'> #define SPINOR_REG_CYPRESS_VREG			0x00800000</div><div class='hunk'>@@ -644,6 +645,7 @@ static int s25hx_t_late_init(struct spi_nor *nor)</div><div class='ctx'> 	params-&gt;ready = cypress_nor_sr_ready_and_clear;</div><div class='ctx'> 	cypress_nor_ecc_init(nor);</div><div class='ctx'> </div><div class='add'>+	params-&gt;die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -933,7 +935,6 @@ static const struct flash_info spansion_nor_parts[] = {</div><div class='ctx'> 		.id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),</div><div class='ctx'> 		.name = "s25hl02gt",</div><div class='ctx'> 		.mfr_flags = USE_CLPEF,</div><div class='del'>-		.flags = NO_CHIP_ERASE,</div><div class='ctx'> 		.fixups = &amp;s25hx_t_fixups</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),</div><div class='hunk'>@@ -954,7 +955,6 @@ static const struct flash_info spansion_nor_parts[] = {</div><div class='ctx'> 		.id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),</div><div class='ctx'> 		.name = "s25hs02gt",</div><div class='ctx'> 		.mfr_flags = USE_CLPEF,</div><div class='del'>-		.flags = NO_CHIP_ERASE,</div><div class='ctx'> 		.fixups = &amp;s25hx_t_fixups</div><div class='ctx'> 	}, {</div><div class='ctx'> 		.id = SNOR_ID(0x34, 0x5a, 0x1a),</div><div class='head'>diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c<br/>index 44d2a546bf17..180b7390690c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sst.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/sst.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sst.c</a></div><div class='hunk'>@@ -13,12 +13,12 @@</div><div class='ctx'> </div><div class='ctx'> #define SST26VF_CR_BPNV		BIT(3)</div><div class='ctx'> </div><div class='del'>-static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -38,7 +38,7 @@ static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='ctx'> 	return spi_nor_global_block_unlock(nor);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c<br/>index 585813310ee1..e48c3cff247a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/swp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/swp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/swp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/swp.c</a></div><div class='hunk'>@@ -53,7 +53,7 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs,</div><div class='del'>-					uint64_t *len)</div><div class='add'>+					u64 *len)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtd_info *mtd = &amp;nor-&gt;mtd;</div><div class='ctx'> 	u64 min_prot_len;</div><div class='hunk'>@@ -90,10 +90,10 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs,</div><div class='ctx'>  * (if @locked is false); false otherwise.</div><div class='ctx'>  */</div><div class='ctx'> static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-					 uint64_t len, u8 sr, bool locked)</div><div class='add'>+					 u64 len, u8 sr, bool locked)</div><div class='ctx'> {</div><div class='ctx'> 	loff_t lock_offs, lock_offs_max, offs_max;</div><div class='del'>-	uint64_t lock_len;</div><div class='add'>+	u64 lock_len;</div><div class='ctx'> </div><div class='ctx'> 	if (!len)</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -111,14 +111,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs,</div><div class='ctx'> 		return (ofs &gt;= lock_offs_max) || (offs_max &lt;= lock_offs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,</div><div class='del'>-				 u8 sr)</div><div class='add'>+static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, u8 sr)</div><div class='ctx'> {</div><div class='ctx'> 	return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs,</div><div class='del'>-				   uint64_t len, u8 sr)</div><div class='add'>+static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 len,</div><div class='add'>+				   u8 sr)</div><div class='ctx'> {</div><div class='ctx'> 	return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false);</div><div class='ctx'> }</div><div class='hunk'>@@ -156,7 +155,7 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs,</div><div class='ctx'>  *</div><div class='ctx'>  * Returns negative on errors, 0 on success.</div><div class='ctx'>  */</div><div class='del'>-static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtd_info *mtd = &amp;nor-&gt;mtd;</div><div class='ctx'> 	u64 min_prot_len;</div><div class='hunk'>@@ -246,7 +245,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='ctx'>  *</div><div class='ctx'>  * Returns negative on errors, 0 on success.</div><div class='ctx'>  */</div><div class='del'>-static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct mtd_info *mtd = &amp;nor-&gt;mtd;</div><div class='ctx'> 	u64 min_prot_len;</div><div class='hunk'>@@ -331,7 +330,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='ctx'>  * Returns 1 if entire region is locked, 0 if any portion is unlocked, and</div><div class='ctx'>  * negative on errors.</div><div class='ctx'>  */</div><div class='del'>-static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -353,7 +352,7 @@ void spi_nor_init_default_locking_ops(struct spi_nor *nor)</div><div class='ctx'> 	nor-&gt;params-&gt;locking_ops = &amp;spi_nor_sr_locking_ops;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_nor *nor = mtd_to_spi_nor(mtd);</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -368,7 +367,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_nor *nor = mtd_to_spi_nor(mtd);</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -383,7 +382,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)</div><div class='add'>+static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, u64 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct spi_nor *nor = mtd_to_spi_nor(mtd);</div><div class='ctx'> 	int ret;</div><div class='head'>diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c<br/>index 2dfdc555a69f..96064e4babf0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sysfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/spi-nor/sysfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/spi-nor/sysfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/spi-nor/sysfs.c</a></div><div class='hunk'>@@ -78,6 +78,8 @@ static umode_t spi_nor_sysfs_is_visible(struct kobject *kobj,</div><div class='ctx'> </div><div class='ctx'> 	if (attr == &amp;dev_attr_manufacturer.attr &amp;&amp; !nor-&gt;manufacturer)</div><div class='ctx'> 		return 0;</div><div class='add'>+	if (attr == &amp;dev_attr_partname.attr &amp;&amp; !nor-&gt;info-&gt;name)</div><div class='add'>+		return 0;</div><div class='ctx'> 	if (attr == &amp;dev_attr_jedec_id.attr &amp;&amp; !nor-&gt;info-&gt;id &amp;&amp; !nor-&gt;id)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/mtd/ssfdc.c b/drivers/mtd/ssfdc.c<br/>index 04da685c36be..211f279a33a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ssfdc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ssfdc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ssfdc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ssfdc.c</a></div><div class='hunk'>@@ -18,7 +18,6 @@</div><div class='ctx'> </div><div class='ctx'> struct ssfdcr_record {</div><div class='ctx'> 	struct mtd_blktrans_dev mbd;</div><div class='del'>-	int usecount;</div><div class='ctx'> 	unsigned char heads;</div><div class='ctx'> 	unsigned char sectors;</div><div class='ctx'> 	unsigned short cylinders;</div><div class='head'>diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig<br/>index 2ed77b7b3fcb..7499a540121e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/Kconfig</a></div><div class='hunk'>@@ -104,4 +104,13 @@ config MTD_UBI_BLOCK</div><div class='ctx'> </div><div class='ctx'> 	   If in doubt, say "N".</div><div class='ctx'> </div><div class='add'>+config MTD_UBI_FAULT_INJECTION</div><div class='add'>+	bool "Fault injection capability of UBI device"</div><div class='add'>+	default n</div><div class='add'>+	depends on FAULT_INJECTION_DEBUG_FS</div><div class='add'>+	help</div><div class='add'>+	   This option enables fault-injection support for UBI devices for</div><div class='add'>+	   testing purposes.</div><div class='add'>+</div><div class='add'>+	   If in doubt, say "N".</div><div class='ctx'> endif # MTD_UBI</div><div class='head'>diff --git a/drivers/mtd/ubi/block.c b/drivers/mtd/ubi/block.c<br/>index 309a42aeaa4c..654bd7372cd8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/block.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/block.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/block.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/block.c</a></div><div class='hunk'>@@ -434,7 +434,7 @@ out_remove_minor:</div><div class='ctx'> 	list_del(&amp;dev-&gt;list);</div><div class='ctx'> 	idr_remove(&amp;ubiblock_minor_idr, gd-&gt;first_minor);</div><div class='ctx'> out_cleanup_disk:</div><div class='del'>-	put_disk(dev-&gt;gd);</div><div class='add'>+	put_disk(gd);</div><div class='ctx'> out_free_tags:</div><div class='ctx'> 	blk_mq_free_tag_set(&amp;dev-&gt;tag_set);</div><div class='ctx'> out_free_dev:</div><div class='head'>diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c<br/>index 27168f511d6d..d57f52bd2ff3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/debug.c</a></div><div class='hunk'>@@ -10,7 +10,37 @@</div><div class='ctx'> #include &lt;linux/uaccess.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/seq_file.h&gt;</div><div class='add'>+#include &lt;linux/fault-inject.h&gt;</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_MTD_UBI_FAULT_INJECTION</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_eccerr_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_bitflips_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_read_failure_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_write_failure_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_erase_failure_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_power_cut_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_io_ff_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_io_ff_bitflips_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_bad_hdr_attr);</div><div class='add'>+static DECLARE_FAULT_ATTR(fault_bad_hdr_ebadmsg_attr);</div><div class='add'>+</div><div class='add'>+#define FAIL_ACTION(name, fault_attr)			\</div><div class='add'>+bool should_fail_##name(void)				\</div><div class='add'>+{							\</div><div class='add'>+	return should_fail(&amp;fault_attr, 1);		\</div><div class='add'>+}</div><div class='ctx'> </div><div class='add'>+FAIL_ACTION(eccerr,		fault_eccerr_attr)</div><div class='add'>+FAIL_ACTION(bitflips,		fault_bitflips_attr)</div><div class='add'>+FAIL_ACTION(read_failure,	fault_read_failure_attr)</div><div class='add'>+FAIL_ACTION(write_failure,	fault_write_failure_attr)</div><div class='add'>+FAIL_ACTION(erase_failure,	fault_erase_failure_attr)</div><div class='add'>+FAIL_ACTION(power_cut,		fault_power_cut_attr)</div><div class='add'>+FAIL_ACTION(io_ff,		fault_io_ff_attr)</div><div class='add'>+FAIL_ACTION(io_ff_bitflips,	fault_io_ff_bitflips_attr)</div><div class='add'>+FAIL_ACTION(bad_hdr,		fault_bad_hdr_attr)</div><div class='add'>+FAIL_ACTION(bad_hdr_ebadmsg,	fault_bad_hdr_ebadmsg_attr)</div><div class='add'>+#endif</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ubi_dump_flash - dump a region of flash.</div><div class='hunk'>@@ -212,6 +242,52 @@ void ubi_dump_mkvol_req(const struct ubi_mkvol_req *req)</div><div class='ctx'>  */</div><div class='ctx'> static struct dentry *dfs_rootdir;</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_MTD_UBI_FAULT_INJECTION</div><div class='add'>+static void dfs_create_fault_entry(struct dentry *parent)</div><div class='add'>+{</div><div class='add'>+	struct dentry *dir;</div><div class='add'>+</div><div class='add'>+	dir = debugfs_create_dir("fault_inject", parent);</div><div class='add'>+	if (IS_ERR_OR_NULL(dir)) {</div><div class='add'>+		int err = dir ? PTR_ERR(dir) : -ENODEV;</div><div class='add'>+</div><div class='add'>+		pr_warn("UBI error: cannot create \"fault_inject\" debugfs directory, error %d\n",</div><div class='add'>+			 err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_eccerr", dir,</div><div class='add'>+				  &amp;fault_eccerr_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_read_failure", dir,</div><div class='add'>+				  &amp;fault_read_failure_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_bitflips", dir,</div><div class='add'>+				  &amp;fault_bitflips_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_write_failure", dir,</div><div class='add'>+				  &amp;fault_write_failure_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_erase_failure", dir,</div><div class='add'>+				  &amp;fault_erase_failure_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_power_cut", dir,</div><div class='add'>+				  &amp;fault_power_cut_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_io_ff", dir,</div><div class='add'>+				  &amp;fault_io_ff_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_io_ff_bitflips", dir,</div><div class='add'>+				  &amp;fault_io_ff_bitflips_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_bad_hdr", dir,</div><div class='add'>+				  &amp;fault_bad_hdr_attr);</div><div class='add'>+</div><div class='add'>+	fault_create_debugfs_attr("emulate_bad_hdr_ebadmsg", dir,</div><div class='add'>+				  &amp;fault_bad_hdr_ebadmsg_attr);</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ubi_debugfs_init - create UBI debugfs directory.</div><div class='ctx'>  *</div><div class='hunk'>@@ -232,6 +308,10 @@ int ubi_debugfs_init(void)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_MTD_UBI_FAULT_INJECTION</div><div class='add'>+	dfs_create_fault_entry(dfs_rootdir);</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -252,7 +332,7 @@ static ssize_t dfs_file_read(struct file *file, char __user *user_buf,</div><div class='ctx'> 	struct dentry *dent = file-&gt;f_path.dentry;</div><div class='ctx'> 	struct ubi_device *ubi;</div><div class='ctx'> 	struct ubi_debug_info *d;</div><div class='del'>-	char buf[8];</div><div class='add'>+	char buf[16];</div><div class='ctx'> 	int val;</div><div class='ctx'> </div><div class='ctx'> 	ubi = ubi_get_device(ubi_num);</div><div class='hunk'>@@ -272,7 +352,12 @@ static ssize_t dfs_file_read(struct file *file, char __user *user_buf,</div><div class='ctx'> 		val = d-&gt;emulate_bitflips;</div><div class='ctx'> 	else if (dent == d-&gt;dfs_emulate_io_failures)</div><div class='ctx'> 		val = d-&gt;emulate_io_failures;</div><div class='del'>-	else if (dent == d-&gt;dfs_emulate_power_cut) {</div><div class='add'>+	else if (dent == d-&gt;dfs_emulate_failures) {</div><div class='add'>+		snprintf(buf, sizeof(buf), "0x%04x\n", d-&gt;emulate_failures);</div><div class='add'>+		count = simple_read_from_buffer(user_buf, count, ppos,</div><div class='add'>+						buf, strlen(buf));</div><div class='add'>+		goto out;</div><div class='add'>+	} else if (dent == d-&gt;dfs_emulate_power_cut) {</div><div class='ctx'> 		snprintf(buf, sizeof(buf), "%u\n", d-&gt;emulate_power_cut);</div><div class='ctx'> 		count = simple_read_from_buffer(user_buf, count, ppos,</div><div class='ctx'> 						buf, strlen(buf));</div><div class='hunk'>@@ -287,8 +372,7 @@ static ssize_t dfs_file_read(struct file *file, char __user *user_buf,</div><div class='ctx'> 		count = simple_read_from_buffer(user_buf, count, ppos,</div><div class='ctx'> 						buf, strlen(buf));</div><div class='ctx'> 		goto out;</div><div class='del'>-	}</div><div class='del'>-	else {</div><div class='add'>+	} else {</div><div class='ctx'> 		count = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -316,7 +400,7 @@ static ssize_t dfs_file_write(struct file *file, const char __user *user_buf,</div><div class='ctx'> 	struct ubi_device *ubi;</div><div class='ctx'> 	struct ubi_debug_info *d;</div><div class='ctx'> 	size_t buf_size;</div><div class='del'>-	char buf[8] = {0};</div><div class='add'>+	char buf[16] = {0};</div><div class='ctx'> 	int val;</div><div class='ctx'> </div><div class='ctx'> 	ubi = ubi_get_device(ubi_num);</div><div class='hunk'>@@ -330,7 +414,11 @@ static ssize_t dfs_file_write(struct file *file, const char __user *user_buf,</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dent == d-&gt;dfs_power_cut_min) {</div><div class='add'>+	if (dent == d-&gt;dfs_emulate_failures) {</div><div class='add'>+		if (kstrtouint(buf, 0, &amp;d-&gt;emulate_failures) != 0)</div><div class='add'>+			count = -EINVAL;</div><div class='add'>+		goto out;</div><div class='add'>+	} else if (dent == d-&gt;dfs_power_cut_min) {</div><div class='ctx'> 		if (kstrtouint(buf, 0, &amp;d-&gt;power_cut_min) != 0)</div><div class='ctx'> 			count = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -559,6 +647,12 @@ int ubi_debugfs_init_dev(struct ubi_device *ubi)</div><div class='ctx'> 	debugfs_create_file("detailed_erase_block_info", S_IRUSR, d-&gt;dfs_dir,</div><div class='ctx'> 			    (void *)ubi_num, &amp;eraseblk_count_fops);</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_MTD_UBI_FAULT_INJECTION</div><div class='add'>+	d-&gt;dfs_emulate_failures = debugfs_create_file("emulate_failures",</div><div class='add'>+						       mode, d-&gt;dfs_dir,</div><div class='add'>+						       (void *)ubi_num,</div><div class='add'>+						       &amp;dfs_fops);</div><div class='add'>+#endif</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -600,7 +694,5 @@ int ubi_dbg_power_cut(struct ubi_device *ubi, int caller)</div><div class='ctx'> 	if (ubi-&gt;dbg.power_cut_counter)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	ubi_msg(ubi, "XXXXXXXXXXXXXXX emulating a power cut XXXXXXXXXXXXXXXX");</div><div class='del'>-	ubi_ro_mode(ubi);</div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h<br/>index 23676f32b681..b2fd97548808 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/debug.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/debug.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/debug.h</a></div><div class='hunk'>@@ -53,56 +53,315 @@ int ubi_debugfs_init_dev(struct ubi_device *ubi);</div><div class='ctx'> void ubi_debugfs_exit_dev(struct ubi_device *ubi);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ubi_dbg_is_bgt_disabled - if the background thread is disabled.</div><div class='add'>+ * The following function is a legacy implementation of UBI fault-injection</div><div class='add'>+ * hook. When using more powerful fault injection capabilities, the legacy</div><div class='add'>+ * fault injection interface should be retained.</div><div class='add'>+ */</div><div class='add'>+int ubi_dbg_power_cut(struct ubi_device *ubi, int caller);</div><div class='add'>+</div><div class='add'>+static inline int ubi_dbg_bitflip(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_bitflips)</div><div class='add'>+		return !get_random_u32_below(200);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int ubi_dbg_write_failure(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_io_failures)</div><div class='add'>+		return !get_random_u32_below(500);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int ubi_dbg_erase_failure(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_io_failures)</div><div class='add'>+		return !get_random_u32_below(400);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * MASK_XXX: Mask for emulate_failures in ubi_debug_info.The mask is used to</div><div class='add'>+ * precisely control the type and process of fault injection.</div><div class='add'>+ */</div><div class='add'>+/* Emulate a power cut when writing EC/VID header */</div><div class='add'>+#define MASK_POWER_CUT_EC			(1 &lt;&lt; 0)</div><div class='add'>+#define MASK_POWER_CUT_VID			(1 &lt;&lt; 1)</div><div class='add'>+/* Emulate a power cut when writing data*/</div><div class='add'>+#define MASK_POWER_CUT_DATA			(1 &lt;&lt; 2)</div><div class='add'>+/* Emulate bit-flips */</div><div class='add'>+#define MASK_BITFLIPS				(1 &lt;&lt; 3)</div><div class='add'>+/* Emulate ecc error */</div><div class='add'>+#define MASK_ECCERR				(1 &lt;&lt; 4)</div><div class='add'>+/* Emulates -EIO during data read */</div><div class='add'>+#define MASK_READ_FAILURE			(1 &lt;&lt; 5)</div><div class='add'>+#define MASK_READ_FAILURE_EC			(1 &lt;&lt; 6)</div><div class='add'>+#define MASK_READ_FAILURE_VID			(1 &lt;&lt; 7)</div><div class='add'>+/* Emulates -EIO during data write */</div><div class='add'>+#define MASK_WRITE_FAILURE			(1 &lt;&lt; 8)</div><div class='add'>+/* Emulates -EIO during erase a PEB*/</div><div class='add'>+#define MASK_ERASE_FAILURE			(1 &lt;&lt; 9)</div><div class='add'>+/* Return UBI_IO_FF when reading EC/VID header */</div><div class='add'>+#define MASK_IO_FF_EC				(1 &lt;&lt; 10)</div><div class='add'>+#define MASK_IO_FF_VID				(1 &lt;&lt; 11)</div><div class='add'>+/* Return UBI_IO_FF_BITFLIPS when reading EC/VID header */</div><div class='add'>+#define MASK_IO_FF_BITFLIPS_EC			(1 &lt;&lt; 12)</div><div class='add'>+#define MASK_IO_FF_BITFLIPS_VID			(1 &lt;&lt; 13)</div><div class='add'>+/* Return UBI_IO_BAD_HDR when reading EC/VID header */</div><div class='add'>+#define MASK_BAD_HDR_EC				(1 &lt;&lt; 14)</div><div class='add'>+#define MASK_BAD_HDR_VID			(1 &lt;&lt; 15)</div><div class='add'>+/* Return UBI_IO_BAD_HDR_EBADMSG when reading EC/VID header */</div><div class='add'>+#define MASK_BAD_HDR_EBADMSG_EC			(1 &lt;&lt; 16)</div><div class='add'>+#define MASK_BAD_HDR_EBADMSG_VID		(1 &lt;&lt; 17)</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_MTD_UBI_FAULT_INJECTION</div><div class='add'>+</div><div class='add'>+extern bool should_fail_eccerr(void);</div><div class='add'>+extern bool should_fail_bitflips(void);</div><div class='add'>+extern bool should_fail_read_failure(void);</div><div class='add'>+extern bool should_fail_write_failure(void);</div><div class='add'>+extern bool should_fail_erase_failure(void);</div><div class='add'>+extern bool should_fail_power_cut(void);</div><div class='add'>+extern bool should_fail_io_ff(void);</div><div class='add'>+extern bool should_fail_io_ff_bitflips(void);</div><div class='add'>+extern bool should_fail_bad_hdr(void);</div><div class='add'>+extern bool should_fail_bad_hdr_ebadmsg(void);</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_bitflip(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; MASK_BITFLIPS)</div><div class='add'>+		return should_fail_bitflips();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_write(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; MASK_WRITE_FAILURE)</div><div class='add'>+		return should_fail_write_failure();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_erase(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; MASK_ERASE_FAILURE)</div><div class='add'>+		return should_fail_erase_failure();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_power_cut(const struct ubi_device *ubi,</div><div class='add'>+					  unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_power_cut();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_read(const struct ubi_device *ubi,</div><div class='add'>+				     unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_read_failure();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_eccerr(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; MASK_ECCERR)</div><div class='add'>+		return should_fail_eccerr();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_ff(const struct ubi_device *ubi,</div><div class='add'>+				   unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_io_ff();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_ff_bitflips(const struct ubi_device *ubi,</div><div class='add'>+					    unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_io_ff_bitflips();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_bad_hdr(const struct ubi_device *ubi,</div><div class='add'>+					 unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_bad_hdr();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ubi_dbg_fail_bad_hdr_ebadmsg(const struct ubi_device *ubi,</div><div class='add'>+						 unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	if (ubi-&gt;dbg.emulate_failures &amp; caller)</div><div class='add'>+		return should_fail_bad_hdr_ebadmsg();</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+#else /* CONFIG_MTD_UBI_FAULT_INJECTION */</div><div class='add'>+</div><div class='add'>+#define ubi_dbg_fail_bitflip(u)             false</div><div class='add'>+#define ubi_dbg_fail_write(u)               false</div><div class='add'>+#define ubi_dbg_fail_erase(u)               false</div><div class='add'>+#define ubi_dbg_fail_power_cut(u, c)        false</div><div class='add'>+#define ubi_dbg_fail_read(u, c)             false</div><div class='add'>+#define ubi_dbg_fail_eccerr(u)              false</div><div class='add'>+#define ubi_dbg_fail_ff(u, c)               false</div><div class='add'>+#define ubi_dbg_fail_ff_bitflips(u, v)      false</div><div class='add'>+#define ubi_dbg_fail_bad_hdr(u, c)          false</div><div class='add'>+#define ubi_dbg_fail_bad_hdr_ebadmsg(u, c)  false</div><div class='add'>+</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_power_cut - if it is time to emulate power cut.</div><div class='ctx'>  * @ubi: UBI device description object</div><div class='ctx'>  *</div><div class='del'>- * Returns non-zero if the UBI background thread is disabled for testing</div><div class='del'>- * purposes.</div><div class='add'>+ * Returns true if power cut should be emulated, otherwise returns false.</div><div class='ctx'>  */</div><div class='del'>-static inline int ubi_dbg_is_bgt_disabled(const struct ubi_device *ubi)</div><div class='add'>+static inline bool ubi_dbg_is_power_cut(struct ubi_device *ubi,</div><div class='add'>+					unsigned int caller)</div><div class='ctx'> {</div><div class='del'>-	return ubi-&gt;dbg.disable_bgt;</div><div class='add'>+	if (ubi_dbg_power_cut(ubi, caller))</div><div class='add'>+		return true;</div><div class='add'>+	return ubi_dbg_fail_power_cut(ubi, caller);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ubi_dbg_is_bitflip - if it is time to emulate a bit-flip.</div><div class='ctx'>  * @ubi: UBI device description object</div><div class='ctx'>  *</div><div class='del'>- * Returns non-zero if a bit-flip should be emulated, otherwise returns zero.</div><div class='add'>+ * Returns true if a bit-flip should be emulated, otherwise returns false.</div><div class='ctx'>  */</div><div class='del'>-static inline int ubi_dbg_is_bitflip(const struct ubi_device *ubi)</div><div class='add'>+static inline bool ubi_dbg_is_bitflip(const struct ubi_device *ubi)</div><div class='ctx'> {</div><div class='del'>-	if (ubi-&gt;dbg.emulate_bitflips)</div><div class='del'>-		return !get_random_u32_below(200);</div><div class='del'>-	return 0;</div><div class='add'>+	if (ubi_dbg_bitflip(ubi))</div><div class='add'>+		return true;</div><div class='add'>+	return ubi_dbg_fail_bitflip(ubi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ubi_dbg_is_write_failure - if it is time to emulate a write failure.</div><div class='ctx'>  * @ubi: UBI device description object</div><div class='ctx'>  *</div><div class='del'>- * Returns non-zero if a write failure should be emulated, otherwise returns</div><div class='del'>- * zero.</div><div class='add'>+ * Returns true if a write failure should be emulated, otherwise returns</div><div class='add'>+ * false.</div><div class='ctx'>  */</div><div class='del'>-static inline int ubi_dbg_is_write_failure(const struct ubi_device *ubi)</div><div class='add'>+static inline bool ubi_dbg_is_write_failure(const struct ubi_device *ubi)</div><div class='ctx'> {</div><div class='del'>-	if (ubi-&gt;dbg.emulate_io_failures)</div><div class='del'>-		return !get_random_u32_below(500);</div><div class='del'>-	return 0;</div><div class='add'>+	if (ubi_dbg_write_failure(ubi))</div><div class='add'>+		return true;</div><div class='add'>+	return ubi_dbg_fail_write(ubi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ubi_dbg_is_erase_failure - if its time to emulate an erase failure.</div><div class='ctx'>  * @ubi: UBI device description object</div><div class='ctx'>  *</div><div class='del'>- * Returns non-zero if an erase failure should be emulated, otherwise returns</div><div class='del'>- * zero.</div><div class='add'>+ * Returns true if an erase failure should be emulated, otherwise returns</div><div class='add'>+ * false.</div><div class='ctx'>  */</div><div class='del'>-static inline int ubi_dbg_is_erase_failure(const struct ubi_device *ubi)</div><div class='add'>+static inline bool ubi_dbg_is_erase_failure(const struct ubi_device *ubi)</div><div class='ctx'> {</div><div class='del'>-	if (ubi-&gt;dbg.emulate_io_failures)</div><div class='del'>-		return !get_random_u32_below(400);</div><div class='del'>-	return 0;</div><div class='add'>+	if (ubi_dbg_erase_failure(ubi))</div><div class='add'>+		return true;</div><div class='add'>+	return ubi_dbg_fail_erase(ubi);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_eccerr - if it is time to emulate ECC error.</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if a ECC error should be emulated, otherwise returns false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_eccerr(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_eccerr(ubi);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_read_failure - if it is time to emulate a read failure.</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if a read failure should be emulated, otherwise returns</div><div class='add'>+ * false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_read_failure(const struct ubi_device *ubi,</div><div class='add'>+					   unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_read(ubi, caller);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_ff - if it is time to emulate that read region is only 0xFF.</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if read region should be emulated 0xFF, otherwise</div><div class='add'>+ * returns false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_ff(const struct ubi_device *ubi,</div><div class='add'>+				 unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_ff(ubi, caller);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_ff_bitflips - if it is time to emulate that read region is only 0xFF</div><div class='add'>+ * with error reported by the MTD driver</div><div class='add'>+ *</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if read region should be emulated 0xFF and error</div><div class='add'>+ * reported by the MTD driver, otherwise returns false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_ff_bitflips(const struct ubi_device *ubi,</div><div class='add'>+					  unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_ff_bitflips(ubi, caller);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_bad_hdr - if it is time to emulate a bad header</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if a bad header error should be emulated, otherwise</div><div class='add'>+ * returns false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_bad_hdr(const struct ubi_device *ubi,</div><div class='add'>+				      unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_bad_hdr(ubi, caller);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_bad_hdr_ebadmsg - if it is time to emulate a bad header with</div><div class='add'>+ * ECC error.</div><div class='add'>+ *</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns true if a bad header with ECC error should be emulated, otherwise</div><div class='add'>+ * returns false.</div><div class='add'>+ */</div><div class='add'>+static inline bool ubi_dbg_is_bad_hdr_ebadmsg(const struct ubi_device *ubi,</div><div class='add'>+					      unsigned int caller)</div><div class='add'>+{</div><div class='add'>+	return ubi_dbg_fail_bad_hdr_ebadmsg(ubi, caller);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ubi_dbg_is_bgt_disabled - if the background thread is disabled.</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ *</div><div class='add'>+ * Returns non-zero if the UBI background thread is disabled for testing</div><div class='add'>+ * purposes.</div><div class='add'>+ */</div><div class='add'>+static inline int ubi_dbg_is_bgt_disabled(const struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	return ubi-&gt;dbg.disable_bgt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int ubi_dbg_chk_io(const struct ubi_device *ubi)</div><div class='hunk'>@@ -125,5 +384,4 @@ static inline void ubi_enable_dbg_chk_fastmap(struct ubi_device *ubi)</div><div class='ctx'> 	ubi-&gt;dbg.chk_fastmap = 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ubi_dbg_power_cut(struct ubi_device *ubi, int caller);</div><div class='ctx'> #endif /* !__UBI_DEBUG_H__ */</div><div class='head'>diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c<br/>index 01b644861253..a4999bce435f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/io.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/io.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/io.c</a></div><div class='hunk'>@@ -195,7 +195,19 @@ retry:</div><div class='ctx'> </div><div class='ctx'> 		if (ubi_dbg_is_bitflip(ubi)) {</div><div class='ctx'> 			dbg_gen("bit-flip (emulated)");</div><div class='del'>-			err = UBI_IO_BITFLIPS;</div><div class='add'>+			return UBI_IO_BITFLIPS;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ubi_dbg_is_read_failure(ubi, MASK_READ_FAILURE)) {</div><div class='add'>+			ubi_warn(ubi, "cannot read %d bytes from PEB %d:%d (emulated)",</div><div class='add'>+				 len, pnum, offset);</div><div class='add'>+			return -EIO;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ubi_dbg_is_eccerr(ubi)) {</div><div class='add'>+			ubi_warn(ubi, "ECC error (emulated) while reading %d bytes from PEB %d:%d, read %zd bytes",</div><div class='add'>+				 len, pnum, offset, read);</div><div class='add'>+			return -EBADMSG;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -782,7 +794,36 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum,</div><div class='ctx'> 	 * If there was %-EBADMSG, but the header CRC is still OK, report about</div><div class='ctx'> 	 * a bit-flip to force scrubbing on this PEB.</div><div class='ctx'> 	 */</div><div class='del'>-	return read_err ? UBI_IO_BITFLIPS : 0;</div><div class='add'>+	if (read_err)</div><div class='add'>+		return UBI_IO_BITFLIPS;</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_read_failure(ubi, MASK_READ_FAILURE_EC)) {</div><div class='add'>+		ubi_warn(ubi, "cannot read EC header from PEB %d (emulated)",</div><div class='add'>+			 pnum);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_ff(ubi, MASK_IO_FF_EC)) {</div><div class='add'>+		ubi_warn(ubi, "bit-all-ff (emulated)");</div><div class='add'>+		return UBI_IO_FF;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_ff_bitflips(ubi, MASK_IO_FF_BITFLIPS_EC)) {</div><div class='add'>+		ubi_warn(ubi, "bit-all-ff with error reported by MTD driver (emulated)");</div><div class='add'>+		return UBI_IO_FF_BITFLIPS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_bad_hdr(ubi, MASK_BAD_HDR_EC)) {</div><div class='add'>+		ubi_warn(ubi, "bad_hdr (emulated)");</div><div class='add'>+		return UBI_IO_BAD_HDR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_bad_hdr_ebadmsg(ubi, MASK_BAD_HDR_EBADMSG_EC)) {</div><div class='add'>+		ubi_warn(ubi, "bad_hdr with ECC error (emulated)");</div><div class='add'>+		return UBI_IO_BAD_HDR_EBADMSG;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -821,8 +862,11 @@ int ubi_io_write_ec_hdr(struct ubi_device *ubi, int pnum,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	if (ubi_dbg_power_cut(ubi, POWER_CUT_EC_WRITE))</div><div class='add'>+	if (ubi_dbg_is_power_cut(ubi, MASK_POWER_CUT_EC)) {</div><div class='add'>+		ubi_warn(ubi, "emulating a power cut when writing EC header");</div><div class='add'>+		ubi_ro_mode(ubi);</div><div class='ctx'> 		return -EROFS;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	err = ubi_io_write(ubi, ec_hdr, pnum, 0, ubi-&gt;ec_hdr_alsize);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -1029,7 +1073,36 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return read_err ? UBI_IO_BITFLIPS : 0;</div><div class='add'>+	if (read_err)</div><div class='add'>+		return UBI_IO_BITFLIPS;</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_read_failure(ubi, MASK_READ_FAILURE_VID)) {</div><div class='add'>+		ubi_warn(ubi, "cannot read VID header from PEB %d (emulated)",</div><div class='add'>+			 pnum);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_ff(ubi, MASK_IO_FF_VID)) {</div><div class='add'>+		ubi_warn(ubi, "bit-all-ff (emulated)");</div><div class='add'>+		return UBI_IO_FF;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_ff_bitflips(ubi, MASK_IO_FF_BITFLIPS_VID)) {</div><div class='add'>+		ubi_warn(ubi, "bit-all-ff with error reported by MTD driver (emulated)");</div><div class='add'>+		return UBI_IO_FF_BITFLIPS;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_bad_hdr(ubi, MASK_BAD_HDR_VID)) {</div><div class='add'>+		ubi_warn(ubi, "bad_hdr (emulated)");</div><div class='add'>+		return UBI_IO_BAD_HDR;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ubi_dbg_is_bad_hdr_ebadmsg(ubi, MASK_BAD_HDR_EBADMSG_VID)) {</div><div class='add'>+		ubi_warn(ubi, "bad_hdr with ECC error (emulated)");</div><div class='add'>+		return UBI_IO_BAD_HDR_EBADMSG;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1071,8 +1144,11 @@ int ubi_io_write_vid_hdr(struct ubi_device *ubi, int pnum,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	if (ubi_dbg_power_cut(ubi, POWER_CUT_VID_WRITE))</div><div class='add'>+	if (ubi_dbg_is_power_cut(ubi, MASK_POWER_CUT_VID)) {</div><div class='add'>+		ubi_warn(ubi, "emulating a power cut when writing VID header");</div><div class='add'>+		ubi_ro_mode(ubi);</div><div class='ctx'> 		return -EROFS;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	err = ubi_io_write(ubi, p, pnum, ubi-&gt;vid_hdr_aloffset,</div><div class='ctx'> 			   ubi-&gt;vid_hdr_alsize);</div><div class='head'>diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h<br/>index a5ec566df0d7..0b42bb45dd84 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/ubi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mtd/ubi/ubi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mtd/ubi/ubi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mtd/ubi/ubi.h</a></div><div class='hunk'>@@ -145,17 +145,6 @@ enum {</div><div class='ctx'> 	UBI_BAD_FASTMAP,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * Flags for emulate_power_cut in ubi_debug_info</div><div class='del'>- *</div><div class='del'>- * POWER_CUT_EC_WRITE: Emulate a power cut when writing an EC header</div><div class='del'>- * POWER_CUT_VID_WRITE: Emulate a power cut when writing a VID header</div><div class='del'>- */</div><div class='del'>-enum {</div><div class='del'>-	POWER_CUT_EC_WRITE = 0x01,</div><div class='del'>-	POWER_CUT_VID_WRITE = 0x02,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * struct ubi_vid_io_buf - VID buffer used to read/write VID info to/from the</div><div class='ctx'>  *			   flash.</div><div class='hunk'>@@ -404,6 +393,7 @@ struct ubi_volume_desc {</div><div class='ctx'>  * @power_cut_counter: count down for writes left until emulated power cut</div><div class='ctx'>  * @power_cut_min: minimum number of writes before emulating a power cut</div><div class='ctx'>  * @power_cut_max: maximum number of writes until emulating a power cut</div><div class='add'>+ * @emulate_failures: emulate failures for testing purposes</div><div class='ctx'>  * @dfs_dir_name: name of debugfs directory containing files of this UBI device</div><div class='ctx'>  * @dfs_dir: direntry object of the UBI device debugfs directory</div><div class='ctx'>  * @dfs_chk_gen: debugfs knob to enable UBI general extra checks</div><div class='hunk'>@@ -415,6 +405,7 @@ struct ubi_volume_desc {</div><div class='ctx'>  * @dfs_emulate_power_cut: debugfs knob to emulate power cuts</div><div class='ctx'>  * @dfs_power_cut_min: debugfs knob for minimum writes before power cut</div><div class='ctx'>  * @dfs_power_cut_max: debugfs knob for maximum writes until power cut</div><div class='add'>+ * @dfs_emulate_failures: debugfs entry to control the fault injection type</div><div class='ctx'>  */</div><div class='ctx'> struct ubi_debug_info {</div><div class='ctx'> 	unsigned int chk_gen:1;</div><div class='hunk'>@@ -427,6 +418,7 @@ struct ubi_debug_info {</div><div class='ctx'> 	unsigned int power_cut_counter;</div><div class='ctx'> 	unsigned int power_cut_min;</div><div class='ctx'> 	unsigned int power_cut_max;</div><div class='add'>+	unsigned int emulate_failures;</div><div class='ctx'> 	char dfs_dir_name[UBI_DFS_DIR_LEN + 1];</div><div class='ctx'> 	struct dentry *dfs_dir;</div><div class='ctx'> 	struct dentry *dfs_chk_gen;</div><div class='hunk'>@@ -438,6 +430,7 @@ struct ubi_debug_info {</div><div class='ctx'> 	struct dentry *dfs_emulate_power_cut;</div><div class='ctx'> 	struct dentry *dfs_power_cut_min;</div><div class='ctx'> 	struct dentry *dfs_power_cut_max;</div><div class='add'>+	struct dentry *dfs_emulate_failures;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1130,6 +1123,19 @@ static inline struct ubi_vid_hdr *ubi_get_vid_hdr(struct ubi_vid_io_buf *vidb)</div><div class='ctx'> 	return vidb-&gt;hdr;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ubi_ro_mode - switch to read-only mode.</div><div class='add'>+ * @ubi: UBI device description object</div><div class='add'>+ */</div><div class='add'>+static inline void ubi_ro_mode(struct ubi_device *ubi)</div><div class='add'>+{</div><div class='add'>+	if (!ubi-&gt;ro_mode) {</div><div class='add'>+		ubi-&gt;ro_mode = 1;</div><div class='add'>+		ubi_warn(ubi, "switch to read-only mode");</div><div class='add'>+		dump_stack();</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * This function is equivalent to 'ubi_io_read()', but @offset is relative to</div><div class='ctx'>  * the beginning of the logical eraseblock, not to the beginning of the</div><div class='hunk'>@@ -1151,20 +1157,13 @@ static inline int ubi_io_write_data(struct ubi_device *ubi, const void *buf,</div><div class='ctx'> 				    int pnum, int offset, int len)</div><div class='ctx'> {</div><div class='ctx'> 	ubi_assert(offset &gt;= 0);</div><div class='del'>-	return ubi_io_write(ubi, buf, pnum, offset + ubi-&gt;leb_start, len);</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * ubi_ro_mode - switch to read-only mode.</div><div class='del'>- * @ubi: UBI device description object</div><div class='del'>- */</div><div class='del'>-static inline void ubi_ro_mode(struct ubi_device *ubi)</div><div class='del'>-{</div><div class='del'>-	if (!ubi-&gt;ro_mode) {</div><div class='del'>-		ubi-&gt;ro_mode = 1;</div><div class='del'>-		ubi_warn(ubi, "switch to read-only mode");</div><div class='del'>-		dump_stack();</div><div class='add'>+	if (ubi_dbg_power_cut(ubi, MASK_POWER_CUT_DATA)) {</div><div class='add'>+		ubi_warn(ubi, "XXXXX emulating a power cut when writing data XXXXX");</div><div class='add'>+		ubi_ro_mode(ubi);</div><div class='add'>+		return -EROFS;</div><div class='ctx'> 	}</div><div class='add'>+	return ubi_io_write(ubi, buf, pnum, offset + ubi-&gt;leb_start, len);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c<br/>index fd1d121a584b..30a952c34365 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/mux/mmio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/mux/mmio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/mux/mmio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/mux/mmio.c</a></div><div class='hunk'>@@ -44,15 +44,20 @@ static int mux_mmio_probe(struct platform_device *pdev)</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (of_device_is_compatible(np, "mmio-mux"))</div><div class='add'>+	if (of_device_is_compatible(np, "mmio-mux")) {</div><div class='ctx'> 		regmap = syscon_node_to_regmap(np-&gt;parent);</div><div class='del'>-	else</div><div class='del'>-		regmap = dev_get_regmap(dev-&gt;parent, NULL) ?: ERR_PTR(-ENODEV);</div><div class='del'>-	if (IS_ERR(regmap)) {</div><div class='del'>-		ret = PTR_ERR(regmap);</div><div class='del'>-		dev_err(dev, "failed to get regmap: %d\n", ret);</div><div class='del'>-		return ret;</div><div class='add'>+	} else {</div><div class='add'>+		regmap = device_node_to_regmap(np);</div><div class='add'>+		/* Fallback to checking the parent node on "real" errors. */</div><div class='add'>+		if (IS_ERR(regmap) &amp;&amp; regmap != ERR_PTR(-EPROBE_DEFER)) {</div><div class='add'>+			regmap = dev_get_regmap(dev-&gt;parent, NULL);</div><div class='add'>+			if (!regmap)</div><div class='add'>+				regmap = ERR_PTR(-ENODEV);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+	if (IS_ERR(regmap))</div><div class='add'>+		return dev_err_probe(dev, PTR_ERR(regmap),</div><div class='add'>+				     "failed to get regmap\n");</div><div class='ctx'> </div><div class='ctx'> 	ret = of_property_count_u32_elems(np, "mux-reg-masks");</div><div class='ctx'> 	if (ret == 0 || ret % 2)</div><div class='head'>diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig<br/>index af0da4bb429b..8ca0bc223b30 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/Kconfig</a></div><div class='hunk'>@@ -434,6 +434,7 @@ config VIRTIO_NET</div><div class='ctx'> 	tristate "Virtio network driver"</div><div class='ctx'> 	depends on VIRTIO</div><div class='ctx'> 	select NET_FAILOVER</div><div class='add'>+	select DIMLIB</div><div class='ctx'> 	help</div><div class='ctx'> 	  This is the virtual network driver for virtio.  It can be used with</div><div class='ctx'> 	  QEMU based VMMs (like KVM or Xen).  Say Y or M.</div><div class='head'>diff --git a/drivers/net/amt.c b/drivers/net/amt.c<br/>index 53415e83821c..68e79b1272f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/amt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/amt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/amt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/amt.c</a></div><div class='hunk'>@@ -11,7 +11,7 @@</div><div class='ctx'> #include &lt;linux/net.h&gt;</div><div class='ctx'> #include &lt;linux/igmp.h&gt;</div><div class='ctx'> #include &lt;linux/workqueue.h&gt;</div><div class='del'>-#include &lt;net/sch_generic.h&gt;</div><div class='add'>+#include &lt;net/pkt_sched.h&gt;</div><div class='ctx'> #include &lt;net/net_namespace.h&gt;</div><div class='ctx'> #include &lt;net/ip.h&gt;</div><div class='ctx'> #include &lt;net/udp.h&gt;</div><div class='hunk'>@@ -80,11 +80,11 @@ static struct mld2_grec mldv2_zero_grec;</div><div class='ctx'> </div><div class='ctx'> static struct amt_skb_cb *amt_skb_cb(struct sk_buff *skb)</div><div class='ctx'> {</div><div class='del'>-	BUILD_BUG_ON(sizeof(struct amt_skb_cb) + sizeof(struct qdisc_skb_cb) &gt;</div><div class='add'>+	BUILD_BUG_ON(sizeof(struct amt_skb_cb) + sizeof(struct tc_skb_cb) &gt;</div><div class='ctx'> 		     sizeof_field(struct sk_buff, cb));</div><div class='ctx'> </div><div class='ctx'> 	return (struct amt_skb_cb *)((void *)skb-&gt;cb +</div><div class='del'>-		sizeof(struct qdisc_skb_cb));</div><div class='add'>+		sizeof(struct tc_skb_cb));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void __amt_source_gc_work(void)</div><div class='head'>diff --git a/drivers/net/arcnet/arcdevice.h b/drivers/net/arcnet/arcdevice.h<br/>index 19e996a829c9..b54275389f8a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/arcnet/arcdevice.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/arcnet/arcdevice.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/arcnet/arcdevice.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/arcnet/arcdevice.h</a></div><div class='hunk'>@@ -186,6 +186,8 @@ do {									\</div><div class='ctx'> #define ARC_IS_5MBIT    1   /* card default speed is 5MBit */</div><div class='ctx'> #define ARC_CAN_10MBIT  2   /* card uses COM20022, supporting 10MBit,</div><div class='ctx'> 				 but default is 2.5MBit. */</div><div class='add'>+#define ARC_HAS_LED     4   /* card has software controlled LEDs */</div><div class='add'>+#define ARC_HAS_ROTARY  8   /* card has rotary encoder */</div><div class='ctx'> </div><div class='ctx'> /* information needed to define an encapsulation driver */</div><div class='ctx'> struct ArcProto {</div><div class='head'>diff --git a/drivers/net/arcnet/com20020-pci.c b/drivers/net/arcnet/com20020-pci.c<br/>index c580acb8b1d3..7b5c8bb02f11 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/arcnet/com20020-pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/arcnet/com20020-pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/arcnet/com20020-pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/arcnet/com20020-pci.c</a></div><div class='hunk'>@@ -213,12 +213,13 @@ static int com20020pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 		if (!strncmp(ci-&gt;name, "EAE PLX-PCI FB2", 15))</div><div class='ctx'> 			lp-&gt;backplane = 1;</div><div class='ctx'> </div><div class='del'>-		/* Get the dev_id from the PLX rotary coder */</div><div class='del'>-		if (!strncmp(ci-&gt;name, "EAE PLX-PCI MA1", 15))</div><div class='del'>-			dev_id_mask = 0x3;</div><div class='del'>-		dev-&gt;dev_id = (inb(priv-&gt;misc + ci-&gt;rotary) &gt;&gt; 4) &amp; dev_id_mask;</div><div class='del'>-</div><div class='del'>-		snprintf(dev-&gt;name, sizeof(dev-&gt;name), "arc%d-%d", dev-&gt;dev_id, i);</div><div class='add'>+		if (ci-&gt;flags &amp; ARC_HAS_ROTARY) {</div><div class='add'>+			/* Get the dev_id from the PLX rotary coder */</div><div class='add'>+			if (!strncmp(ci-&gt;name, "EAE PLX-PCI MA1", 15))</div><div class='add'>+				dev_id_mask = 0x3;</div><div class='add'>+			dev-&gt;dev_id = (inb(priv-&gt;misc + ci-&gt;rotary) &gt;&gt; 4) &amp; dev_id_mask;</div><div class='add'>+			snprintf(dev-&gt;name, sizeof(dev-&gt;name), "arc%d-%d", dev-&gt;dev_id, i);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (arcnet_inb(ioaddr, COM20020_REG_R_STATUS) == 0xFF) {</div><div class='ctx'> 			pr_err("IO address %Xh is empty!\n", ioaddr);</div><div class='hunk'>@@ -230,6 +231,10 @@ static int com20020pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 			goto err_free_arcdev;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		ret = com20020_found(dev, IRQF_SHARED);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_free_arcdev;</div><div class='add'>+</div><div class='ctx'> 		card = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(struct com20020_dev),</div><div class='ctx'> 				    GFP_KERNEL);</div><div class='ctx'> 		if (!card) {</div><div class='hunk'>@@ -239,41 +244,39 @@ static int com20020pci_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 		card-&gt;index = i;</div><div class='ctx'> 		card-&gt;pci_priv = priv;</div><div class='del'>-		card-&gt;tx_led.brightness_set = led_tx_set;</div><div class='del'>-		card-&gt;tx_led.default_trigger = devm_kasprintf(&amp;pdev-&gt;dev,</div><div class='del'>-						GFP_KERNEL, "arc%d-%d-tx",</div><div class='del'>-						dev-&gt;dev_id, i);</div><div class='del'>-		card-&gt;tx_led.name = devm_kasprintf(&amp;pdev-&gt;dev, GFP_KERNEL,</div><div class='del'>-						"pci:green:tx:%d-%d",</div><div class='del'>-						dev-&gt;dev_id, i);</div><div class='del'>-</div><div class='del'>-		card-&gt;tx_led.dev = &amp;dev-&gt;dev;</div><div class='del'>-		card-&gt;recon_led.brightness_set = led_recon_set;</div><div class='del'>-		card-&gt;recon_led.default_trigger = devm_kasprintf(&amp;pdev-&gt;dev,</div><div class='del'>-						GFP_KERNEL, "arc%d-%d-recon",</div><div class='del'>-						dev-&gt;dev_id, i);</div><div class='del'>-		card-&gt;recon_led.name = devm_kasprintf(&amp;pdev-&gt;dev, GFP_KERNEL,</div><div class='del'>-						"pci:red:recon:%d-%d",</div><div class='del'>-						dev-&gt;dev_id, i);</div><div class='del'>-		card-&gt;recon_led.dev = &amp;dev-&gt;dev;</div><div class='del'>-		card-&gt;dev = dev;</div><div class='del'>-</div><div class='del'>-		ret = devm_led_classdev_register(&amp;pdev-&gt;dev, &amp;card-&gt;tx_led);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err_free_arcdev;</div><div class='ctx'> </div><div class='del'>-		ret = devm_led_classdev_register(&amp;pdev-&gt;dev, &amp;card-&gt;recon_led);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err_free_arcdev;</div><div class='del'>-</div><div class='del'>-		dev_set_drvdata(&amp;dev-&gt;dev, card);</div><div class='del'>-</div><div class='del'>-		ret = com20020_found(dev, IRQF_SHARED);</div><div class='del'>-		if (ret)</div><div class='del'>-			goto err_free_arcdev;</div><div class='del'>-</div><div class='del'>-		devm_arcnet_led_init(dev, dev-&gt;dev_id, i);</div><div class='add'>+		if (ci-&gt;flags &amp; ARC_HAS_LED) {</div><div class='add'>+			card-&gt;tx_led.brightness_set = led_tx_set;</div><div class='add'>+			card-&gt;tx_led.default_trigger = devm_kasprintf(&amp;pdev-&gt;dev,</div><div class='add'>+							GFP_KERNEL, "arc%d-%d-tx",</div><div class='add'>+							dev-&gt;dev_id, i);</div><div class='add'>+			card-&gt;tx_led.name = devm_kasprintf(&amp;pdev-&gt;dev, GFP_KERNEL,</div><div class='add'>+							"pci:green:tx:%d-%d",</div><div class='add'>+							dev-&gt;dev_id, i);</div><div class='add'>+</div><div class='add'>+			card-&gt;tx_led.dev = &amp;dev-&gt;dev;</div><div class='add'>+			card-&gt;recon_led.brightness_set = led_recon_set;</div><div class='add'>+			card-&gt;recon_led.default_trigger = devm_kasprintf(&amp;pdev-&gt;dev,</div><div class='add'>+							GFP_KERNEL, "arc%d-%d-recon",</div><div class='add'>+							dev-&gt;dev_id, i);</div><div class='add'>+			card-&gt;recon_led.name = devm_kasprintf(&amp;pdev-&gt;dev, GFP_KERNEL,</div><div class='add'>+							"pci:red:recon:%d-%d",</div><div class='add'>+							dev-&gt;dev_id, i);</div><div class='add'>+			card-&gt;recon_led.dev = &amp;dev-&gt;dev;</div><div class='add'>+</div><div class='add'>+			ret = devm_led_classdev_register(&amp;pdev-&gt;dev, &amp;card-&gt;tx_led);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto err_free_arcdev;</div><div class='add'>+</div><div class='add'>+			ret = devm_led_classdev_register(&amp;pdev-&gt;dev, &amp;card-&gt;recon_led);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto err_free_arcdev;</div><div class='add'>+</div><div class='add'>+			dev_set_drvdata(&amp;dev-&gt;dev, card);</div><div class='add'>+			devm_arcnet_led_init(dev, dev-&gt;dev_id, i);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='add'>+		card-&gt;dev = dev;</div><div class='ctx'> 		list_add(&amp;card-&gt;list, &amp;priv-&gt;list_dev);</div><div class='ctx'> 		continue;</div><div class='ctx'> </div><div class='hunk'>@@ -329,7 +332,7 @@ static struct com20020_pci_card_info card_info_5mbit = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct com20020_pci_card_info card_info_sohard = {</div><div class='del'>-	.name = "PLX-PCI",</div><div class='add'>+	.name = "SOHARD SH ARC-PCI",</div><div class='ctx'> 	.devcount = 1,</div><div class='ctx'> 	/* SOHARD needs PCI base addr 4 */</div><div class='ctx'> 	.chan_map_tbl = {</div><div class='hunk'>@@ -364,7 +367,7 @@ static struct com20020_pci_card_info card_info_eae_arc1 = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	.rotary = 0x0,</div><div class='del'>-	.flags = ARC_CAN_10MBIT,</div><div class='add'>+	.flags = ARC_HAS_ROTARY | ARC_HAS_LED | ARC_CAN_10MBIT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct com20020_pci_card_info card_info_eae_ma1 = {</div><div class='hunk'>@@ -396,7 +399,7 @@ static struct com20020_pci_card_info card_info_eae_ma1 = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	.rotary = 0x0,</div><div class='del'>-	.flags = ARC_CAN_10MBIT,</div><div class='add'>+	.flags = ARC_HAS_ROTARY | ARC_HAS_LED | ARC_CAN_10MBIT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct com20020_pci_card_info card_info_eae_fb2 = {</div><div class='hunk'>@@ -421,7 +424,7 @@ static struct com20020_pci_card_info card_info_eae_fb2 = {</div><div class='ctx'> 		},</div><div class='ctx'> 	},</div><div class='ctx'> 	.rotary = 0x0,</div><div class='del'>-	.flags = ARC_CAN_10MBIT,</div><div class='add'>+	.flags = ARC_HAS_ROTARY | ARC_HAS_LED | ARC_CAN_10MBIT,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct pci_device_id com20020pci_id_table[] = {</div><div class='head'>diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c<br/>index dc2c7b979656..7edf0fd58c34 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/bonding/bond_alb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/bonding/bond_alb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/bonding/bond_alb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/bonding/bond_alb.c</a></div><div class='hunk'>@@ -985,7 +985,8 @@ static int alb_upper_dev_walk(struct net_device *upper,</div><div class='ctx'> 	if (netif_is_macvlan(upper) &amp;&amp; !strict_match) {</div><div class='ctx'> 		tags = bond_verify_device_path(bond-&gt;dev, upper, 0);</div><div class='ctx'> 		if (IS_ERR_OR_NULL(tags))</div><div class='del'>-			BUG();</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 		alb_send_lp_vid(slave, upper-&gt;dev_addr,</div><div class='ctx'> 				tags[0].vlan_proto, tags[0].vlan_id);</div><div class='ctx'> 		kfree(tags);</div><div class='head'>diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c<br/>index 8e6cc0e133b7..4e0600c7b050 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/bonding/bond_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/bonding/bond_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/bonding/bond_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/bonding/bond_main.c</a></div><div class='hunk'>@@ -5755,10 +5755,8 @@ static int bond_ethtool_get_ts_info(struct net_device *bond_dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct bonding *bond = netdev_priv(bond_dev);</div><div class='ctx'> 	struct ethtool_ts_info ts_info;</div><div class='del'>-	const struct ethtool_ops *ops;</div><div class='ctx'> 	struct net_device *real_dev;</div><div class='ctx'> 	bool sw_tx_support = false;</div><div class='del'>-	struct phy_device *phydev;</div><div class='ctx'> 	struct list_head *iter;</div><div class='ctx'> 	struct slave *slave;</div><div class='ctx'> 	int ret = 0;</div><div class='hunk'>@@ -5769,29 +5767,12 @@ static int bond_ethtool_get_ts_info(struct net_device *bond_dev,</div><div class='ctx'> 	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	if (real_dev) {</div><div class='del'>-		ops = real_dev-&gt;ethtool_ops;</div><div class='del'>-		phydev = real_dev-&gt;phydev;</div><div class='del'>-</div><div class='del'>-		if (phy_has_tsinfo(phydev)) {</div><div class='del'>-			ret = phy_ts_info(phydev, info);</div><div class='del'>-			goto out;</div><div class='del'>-		} else if (ops-&gt;get_ts_info) {</div><div class='del'>-			ret = ops-&gt;get_ts_info(real_dev, info);</div><div class='del'>-			goto out;</div><div class='del'>-		}</div><div class='add'>+		ret = ethtool_get_ts_info_by_layer(real_dev, info);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Check if all slaves support software tx timestamping */</div><div class='ctx'> 		rcu_read_lock();</div><div class='ctx'> 		bond_for_each_slave_rcu(bond, slave, iter) {</div><div class='del'>-			ret = -1;</div><div class='del'>-			ops = slave-&gt;dev-&gt;ethtool_ops;</div><div class='del'>-			phydev = slave-&gt;dev-&gt;phydev;</div><div class='del'>-</div><div class='del'>-			if (phy_has_tsinfo(phydev))</div><div class='del'>-				ret = phy_ts_info(phydev, &amp;ts_info);</div><div class='del'>-			else if (ops-&gt;get_ts_info)</div><div class='del'>-				ret = ops-&gt;get_ts_info(slave-&gt;dev, &amp;ts_info);</div><div class='del'>-</div><div class='add'>+			ret = ethtool_get_ts_info_by_layer(slave-&gt;dev, &amp;ts_info);</div><div class='ctx'> 			if (!ret &amp;&amp; (ts_info.so_timestamping &amp; SOF_TIMESTAMPING_TX_SOFTWARE)) {</div><div class='ctx'> 				sw_tx_support = true;</div><div class='ctx'> 				continue;</div><div class='hunk'>@@ -5803,15 +5784,9 @@ static int bond_ethtool_get_ts_info(struct net_device *bond_dev,</div><div class='ctx'> 		rcu_read_unlock();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = 0;</div><div class='del'>-	info-&gt;so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |</div><div class='del'>-				SOF_TIMESTAMPING_SOFTWARE;</div><div class='ctx'> 	if (sw_tx_support)</div><div class='ctx'> 		info-&gt;so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE;</div><div class='ctx'> </div><div class='del'>-	info-&gt;phc_index = -1;</div><div class='del'>-</div><div class='del'>-out:</div><div class='ctx'> 	dev_put(real_dev);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c<br/>index f44ba2600415..e2ec69aa46e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/can/c_can/c_can_platform.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/can/c_can/c_can_platform.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/can/c_can/c_can_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/c_can/c_can_platform.c</a></div><div class='hunk'>@@ -30,9 +30,9 @@</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/mfd/syscon.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -259,22 +259,13 @@ static int c_can_plat_probe(struct platform_device *pdev)</div><div class='ctx'> 	void __iomem *addr;</div><div class='ctx'> 	struct net_device *dev;</div><div class='ctx'> 	struct c_can_priv *priv;</div><div class='del'>-	const struct of_device_id *match;</div><div class='ctx'> 	struct resource *mem;</div><div class='ctx'> 	int irq;</div><div class='ctx'> 	struct clk *clk;</div><div class='ctx'> 	const struct c_can_driver_data *drvdata;</div><div class='ctx'> 	struct device_node *np = pdev-&gt;dev.of_node;</div><div class='ctx'> </div><div class='del'>-	match = of_match_device(c_can_of_table, &amp;pdev-&gt;dev);</div><div class='del'>-	if (match) {</div><div class='del'>-		drvdata = match-&gt;data;</div><div class='del'>-	} else if (pdev-&gt;id_entry-&gt;driver_data) {</div><div class='del'>-		drvdata = (struct c_can_driver_data *)</div><div class='del'>-			platform_get_device_id(pdev)-&gt;driver_data;</div><div class='del'>-	} else {</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='add'>+	drvdata = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	/* get the appropriate clk */</div><div class='ctx'> 	clk = devm_clk_get(&amp;pdev-&gt;dev, NULL);</div><div class='head'>diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c<br/>index d15f85a40c1e..8ea7f2795551 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/can/flexcan/flexcan-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/can/flexcan/flexcan-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/can/flexcan/flexcan-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/flexcan/flexcan-core.c</a></div><div class='hunk'>@@ -23,11 +23,11 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/pinctrl/consumer.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='ctx'> #include &lt;linux/can/platform/flexcan.h&gt;</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;linux/regulator/consumer.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -2034,7 +2034,6 @@ MODULE_DEVICE_TABLE(platform, flexcan_id_table);</div><div class='ctx'> </div><div class='ctx'> static int flexcan_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *of_id;</div><div class='ctx'> 	const struct flexcan_devtype_data *devtype_data;</div><div class='ctx'> 	struct net_device *dev;</div><div class='ctx'> 	struct flexcan_priv *priv;</div><div class='hunk'>@@ -2090,14 +2089,7 @@ static int flexcan_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (IS_ERR(regs))</div><div class='ctx'> 		return PTR_ERR(regs);</div><div class='ctx'> </div><div class='del'>-	of_id = of_match_device(flexcan_of_match, &amp;pdev-&gt;dev);</div><div class='del'>-	if (of_id)</div><div class='del'>-		devtype_data = of_id-&gt;data;</div><div class='del'>-	else if (platform_get_device_id(pdev)-&gt;driver_data)</div><div class='del'>-		devtype_data = (struct flexcan_devtype_data *)</div><div class='del'>-			platform_get_device_id(pdev)-&gt;driver_data;</div><div class='del'>-	else</div><div class='del'>-		return -ENODEV;</div><div class='add'>+	devtype_data = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if ((devtype_data-&gt;quirks &amp; FLEXCAN_QUIRK_SUPPORT_FD) &amp;&amp;</div><div class='ctx'> 	    !((devtype_data-&gt;quirks &amp;</div><div class='head'>diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c<br/>index 4837df6efa92..5b3d69c3b6b6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/can/mscan/mpc5xxx_can.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/can/mscan/mpc5xxx_can.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/can/mscan/mpc5xxx_can.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/mscan/mpc5xxx_can.c</a></div><div class='hunk'>@@ -12,8 +12,10 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/can/dev.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='ctx'> #include &lt;linux/of_address.h&gt;</div><div class='ctx'> #include &lt;linux/of_irq.h&gt;</div><div class='ctx'> #include &lt;linux/of_platform.h&gt;</div><div class='hunk'>@@ -290,7 +292,7 @@ static int mpc5xxx_can_probe(struct platform_device *ofdev)</div><div class='ctx'> 	int irq, mscan_clksrc = 0;</div><div class='ctx'> 	int err = -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	data = of_device_get_match_data(&amp;ofdev-&gt;dev);</div><div class='add'>+	data = device_get_match_data(&amp;ofdev-&gt;dev);</div><div class='ctx'> 	if (!data)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -351,13 +353,11 @@ exit_unmap_mem:</div><div class='ctx'> </div><div class='ctx'> static void mpc5xxx_can_remove(struct platform_device *ofdev)</div><div class='ctx'> {</div><div class='del'>-	const struct of_device_id *match;</div><div class='ctx'> 	const struct mpc5xxx_can_data *data;</div><div class='ctx'> 	struct net_device *dev = platform_get_drvdata(ofdev);</div><div class='ctx'> 	struct mscan_priv *priv = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	match = of_match_device(mpc5xxx_can_table, &amp;ofdev-&gt;dev);</div><div class='del'>-	data = match ? match-&gt;data : NULL;</div><div class='add'>+	data = device_get_match_data(&amp;ofdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	unregister_mscandev(dev);</div><div class='ctx'> 	if (data &amp;&amp; data-&gt;put_clock)</div><div class='head'>diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_core.c b/drivers/net/can/usb/peak_usb/pcan_usb_core.c<br/>index 24ad9f593a77..1efa39e134f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/can/usb/peak_usb/pcan_usb_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/can/usb/peak_usb/pcan_usb_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/can/usb/peak_usb/pcan_usb_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/usb/peak_usb/pcan_usb_core.c</a></div><div class='hunk'>@@ -1143,7 +1143,7 @@ static void __exit peak_usb_exit(void)</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	/* last chance do send any synchronous commands here */</div><div class='del'>-	err = driver_for_each_device(&amp;peak_usb_driver.drvwrap.driver, NULL,</div><div class='add'>+	err = driver_for_each_device(&amp;peak_usb_driver.driver, NULL,</div><div class='ctx'> 				     NULL, peak_usb_do_device_exit);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		pr_err("%s: failed to stop all can devices (err %d)\n",</div><div class='head'>diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c<br/>index abe58f103043..3722eaa84234 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/can/xilinx_can.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/can/xilinx_can.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/can/xilinx_can.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/can/xilinx_can.c</a></div><div class='hunk'>@@ -20,8 +20,8 @@</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='ctx'> #include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/of.h&gt;</div><div class='del'>-#include &lt;linux/of_device.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/skbuff.h&gt;</div><div class='ctx'> #include &lt;linux/spinlock.h&gt;</div><div class='ctx'> #include &lt;linux/string.h&gt;</div><div class='hunk'>@@ -1726,8 +1726,7 @@ static int xcan_probe(struct platform_device *pdev)</div><div class='ctx'> 	struct net_device *ndev;</div><div class='ctx'> 	struct xcan_priv *priv;</div><div class='ctx'> 	struct phy *transceiver;</div><div class='del'>-	const struct of_device_id *of_id;</div><div class='del'>-	const struct xcan_devtype_data *devtype = &amp;xcan_axi_data;</div><div class='add'>+	const struct xcan_devtype_data *devtype;</div><div class='ctx'> 	void __iomem *addr;</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int rx_max, tx_max;</div><div class='hunk'>@@ -1741,9 +1740,7 @@ static int xcan_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	of_id = of_match_device(xcan_of_match, &amp;pdev-&gt;dev);</div><div class='del'>-	if (of_id &amp;&amp; of_id-&gt;data)</div><div class='del'>-		devtype = of_id-&gt;data;</div><div class='add'>+	devtype = device_get_match_data(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	hw_tx_max_property = devtype-&gt;flags &amp; XCAN_FLAG_TX_MAILBOXES ?</div><div class='ctx'> 			     "tx-mailbox-count" : "tx-fifo-depth";</div><div class='head'>diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c<br/>index cadee5505c29..4a52ccbe393f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/bcm_sf2.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/bcm_sf2.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/bcm_sf2.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/bcm_sf2.c</a></div><div class='hunk'>@@ -621,8 +621,6 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)</div><div class='ctx'> 		goto err_of_node_put;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	priv-&gt;master_mii_dn = dn;</div><div class='del'>-</div><div class='ctx'> 	priv-&gt;user_mii_bus = mdiobus_alloc();</div><div class='ctx'> 	if (!priv-&gt;user_mii_bus) {</div><div class='ctx'> 		err = -ENOMEM;</div><div class='hunk'>@@ -635,7 +633,6 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)</div><div class='ctx'> 	priv-&gt;user_mii_bus-&gt;write = bcm_sf2_sw_mdio_write;</div><div class='ctx'> 	snprintf(priv-&gt;user_mii_bus-&gt;id, MII_BUS_ID_SIZE, "sf2-%d",</div><div class='ctx'> 		 index++);</div><div class='del'>-	priv-&gt;user_mii_bus-&gt;dev.of_node = dn;</div><div class='ctx'> </div><div class='ctx'> 	/* Include the pseudo-PHY address to divert reads towards our</div><div class='ctx'> 	 * workaround. This is only required for 7445D0, since 7445E0</div><div class='hunk'>@@ -683,9 +680,11 @@ static int bcm_sf2_mdio_register(struct dsa_switch *ds)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = mdiobus_register(priv-&gt;user_mii_bus);</div><div class='del'>-	if (err &amp;&amp; dn)</div><div class='add'>+	if (err)</div><div class='ctx'> 		goto err_free_user_mii_bus;</div><div class='ctx'> </div><div class='add'>+	of_node_put(dn);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_free_user_mii_bus:</div><div class='head'>diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h<br/>index 424f896b5a6f..f95f4880b69e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/bcm_sf2.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/bcm_sf2.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/bcm_sf2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/bcm_sf2.h</a></div><div class='hunk'>@@ -107,7 +107,6 @@ struct bcm_sf2_priv {</div><div class='ctx'> </div><div class='ctx'> 	/* Master and slave MDIO bus controller */</div><div class='ctx'> 	unsigned int			indir_phy_mask;</div><div class='del'>-	struct device_node		*master_mii_dn;</div><div class='ctx'> 	struct mii_bus			*user_mii_bus;</div><div class='ctx'> 	struct mii_bus			*master_mii_bus;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c<br/>index 9c185c9f0963..de48b194048f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/lantiq_gswip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/lantiq_gswip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/lantiq_gswip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/lantiq_gswip.c</a></div><div class='hunk'>@@ -505,27 +505,34 @@ static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg)</div><div class='ctx'> 	return gswip_mdio_r(priv, GSWIP_MDIO_READ);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np)</div><div class='add'>+static int gswip_mdio(struct gswip_priv *priv)</div><div class='ctx'> {</div><div class='del'>-	struct dsa_switch *ds = priv-&gt;ds;</div><div class='del'>-	int err;</div><div class='add'>+	struct device_node *mdio_np, *switch_np = priv-&gt;dev-&gt;of_node;</div><div class='add'>+	struct device *dev = priv-&gt;dev;</div><div class='add'>+	struct mii_bus *bus;</div><div class='add'>+	int err = 0;</div><div class='ctx'> </div><div class='del'>-	ds-&gt;user_mii_bus = mdiobus_alloc();</div><div class='del'>-	if (!ds-&gt;user_mii_bus)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio");</div><div class='add'>+	if (!of_device_is_available(mdio_np))</div><div class='add'>+		goto out_put_node;</div><div class='ctx'> </div><div class='del'>-	ds-&gt;user_mii_bus-&gt;priv = priv;</div><div class='del'>-	ds-&gt;user_mii_bus-&gt;read = gswip_mdio_rd;</div><div class='del'>-	ds-&gt;user_mii_bus-&gt;write = gswip_mdio_wr;</div><div class='del'>-	ds-&gt;user_mii_bus-&gt;name = "lantiq,xrx200-mdio";</div><div class='del'>-	snprintf(ds-&gt;user_mii_bus-&gt;id, MII_BUS_ID_SIZE, "%s-mii",</div><div class='del'>-		 dev_name(priv-&gt;dev));</div><div class='del'>-	ds-&gt;user_mii_bus-&gt;parent = priv-&gt;dev;</div><div class='del'>-	ds-&gt;user_mii_bus-&gt;phy_mask = ~ds-&gt;phys_mii_mask;</div><div class='add'>+	bus = devm_mdiobus_alloc(dev);</div><div class='add'>+	if (!bus) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto out_put_node;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	err = of_mdiobus_register(ds-&gt;user_mii_bus, mdio_np);</div><div class='del'>-	if (err)</div><div class='del'>-		mdiobus_free(ds-&gt;user_mii_bus);</div><div class='add'>+	bus-&gt;priv = priv;</div><div class='add'>+	bus-&gt;read = gswip_mdio_rd;</div><div class='add'>+	bus-&gt;write = gswip_mdio_wr;</div><div class='add'>+	bus-&gt;name = "lantiq,xrx200-mdio";</div><div class='add'>+	snprintf(bus-&gt;id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv-&gt;dev));</div><div class='add'>+	bus-&gt;parent = priv-&gt;dev;</div><div class='add'>+</div><div class='add'>+	err = devm_of_mdiobus_register(dev, bus, mdio_np);</div><div class='add'>+</div><div class='add'>+out_put_node:</div><div class='add'>+	of_node_put(mdio_np);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -1759,7 +1766,7 @@ static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(gswip_rmon_cnt); i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", gswip_rmon_cnt[i].name);</div><div class='add'>+		ethtool_puts(&amp;data, gswip_rmon_cnt[i].name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table,</div><div class='hunk'>@@ -2094,9 +2101,9 @@ remove_gphy:</div><div class='ctx'> </div><div class='ctx'> static int gswip_probe(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='del'>-	struct gswip_priv *priv;</div><div class='del'>-	struct device_node *np, *mdio_np, *gphy_fw_np;</div><div class='add'>+	struct device_node *np, *gphy_fw_np;</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='add'>+	struct gswip_priv *priv;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	int i;</div><div class='ctx'> 	u32 version;</div><div class='hunk'>@@ -2163,19 +2170,16 @@ static int gswip_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* bring up the mdio bus */</div><div class='del'>-	mdio_np = of_get_compatible_child(dev-&gt;of_node, "lantiq,xrx200-mdio");</div><div class='del'>-	if (mdio_np) {</div><div class='del'>-		err = gswip_mdio(priv, mdio_np);</div><div class='del'>-		if (err) {</div><div class='del'>-			dev_err(dev, "mdio probe failed\n");</div><div class='del'>-			goto put_mdio_node;</div><div class='del'>-		}</div><div class='add'>+	err = gswip_mdio(priv);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(dev, "mdio probe failed\n");</div><div class='add'>+		goto gphy_fw_remove;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = dsa_register_switch(priv-&gt;ds);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(dev, "dsa switch register failed: %i\n", err);</div><div class='del'>-		goto mdio_bus;</div><div class='add'>+		goto gphy_fw_remove;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!dsa_is_cpu_port(priv-&gt;ds, priv-&gt;hw_info-&gt;cpu_port)) {</div><div class='ctx'> 		dev_err(dev, "wrong CPU port defined, HW only supports port: %i",</div><div class='hunk'>@@ -2194,13 +2198,7 @@ static int gswip_probe(struct platform_device *pdev)</div><div class='ctx'> disable_switch:</div><div class='ctx'> 	gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB);</div><div class='ctx'> 	dsa_unregister_switch(priv-&gt;ds);</div><div class='del'>-mdio_bus:</div><div class='del'>-	if (mdio_np) {</div><div class='del'>-		mdiobus_unregister(priv-&gt;ds-&gt;user_mii_bus);</div><div class='del'>-		mdiobus_free(priv-&gt;ds-&gt;user_mii_bus);</div><div class='del'>-	}</div><div class='del'>-put_mdio_node:</div><div class='del'>-	of_node_put(mdio_np);</div><div class='add'>+gphy_fw_remove:</div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;num_gphy_fw; i++)</div><div class='ctx'> 		gswip_gphy_fw_remove(priv, &amp;priv-&gt;gphy_fw[i]);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -2219,12 +2217,6 @@ static void gswip_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dsa_unregister_switch(priv-&gt;ds);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;ds-&gt;user_mii_bus) {</div><div class='del'>-		mdiobus_unregister(priv-&gt;ds-&gt;user_mii_bus);</div><div class='del'>-		of_node_put(priv-&gt;ds-&gt;user_mii_bus-&gt;dev.of_node);</div><div class='del'>-		mdiobus_free(priv-&gt;ds-&gt;user_mii_bus);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;num_gphy_fw; i++)</div><div class='ctx'> 		gswip_gphy_fw_remove(priv, &amp;priv-&gt;gphy_fw[i]);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/dsa/microchip/ksz8.h b/drivers/net/dsa/microchip/ksz8.h<br/>index 4cea811e73ac..1a5225264e6a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/microchip/ksz8.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8.h</a></div><div class='hunk'>@@ -56,5 +56,9 @@ int ksz8_reset_switch(struct ksz_device *dev);</div><div class='ctx'> int ksz8_switch_init(struct ksz_device *dev);</div><div class='ctx'> void ksz8_switch_exit(struct ksz_device *dev);</div><div class='ctx'> int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu);</div><div class='add'>+void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,</div><div class='add'>+			      unsigned int mode, phy_interface_t interface,</div><div class='add'>+			      struct phy_device *phydev, int speed, int duplex,</div><div class='add'>+			      bool tx_pause, bool rx_pause);</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c<br/>index 4bf4d67557dc..61b71bcfe396 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8795.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/microchip/ksz8795.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8795.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8795.c</a></div><div class='hunk'>@@ -1358,6 +1358,9 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_port *p = &amp;dev-&gt;ports[port];</div><div class='ctx'> </div><div class='add'>+	if (!ksz_is_ksz87xx(dev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (!p-&gt;interface &amp;&amp; dev-&gt;compat_interface) {</div><div class='ctx'> 		dev_warn(dev-&gt;dev,</div><div class='ctx'> 			 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "</div><div class='hunk'>@@ -1391,18 +1394,29 @@ void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)</div><div class='ctx'> 	/* enable 802.1p priority */</div><div class='ctx'> 	ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);</div><div class='ctx'> </div><div class='del'>-	if (cpu_port) {</div><div class='del'>-		if (!ksz_is_ksz88x3(dev))</div><div class='del'>-			ksz8795_cpu_interface_select(dev, port);</div><div class='del'>-</div><div class='add'>+	if (cpu_port)</div><div class='ctx'> 		member = dsa_user_ports(ds);</div><div class='del'>-	} else {</div><div class='add'>+	else</div><div class='ctx'> 		member = BIT(dsa_upstream_port(ds, port));</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	ksz8_cfg_port_member(dev, port, member);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ksz88x3_config_rmii_clk(struct ksz_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct dsa_port *cpu_dp = dsa_to_port(dev-&gt;ds, dev-&gt;cpu_port);</div><div class='add'>+	bool rmii_clk_internal;</div><div class='add'>+</div><div class='add'>+	if (!ksz_is_ksz88x3(dev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	rmii_clk_internal = of_property_read_bool(cpu_dp-&gt;dn,</div><div class='add'>+						  "microchip,rmii-clk-internal");</div><div class='add'>+</div><div class='add'>+	ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,</div><div class='add'>+		KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void ksz8_config_cpu_port(struct dsa_switch *ds)</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_device *dev = ds-&gt;priv;</div><div class='hunk'>@@ -1419,6 +1433,9 @@ void ksz8_config_cpu_port(struct dsa_switch *ds)</div><div class='ctx'> </div><div class='ctx'> 	ksz8_port_setup(dev, dev-&gt;cpu_port, true);</div><div class='ctx'> </div><div class='add'>+	ksz8795_cpu_interface_select(dev, dev-&gt;cpu_port);</div><div class='add'>+	ksz88x3_config_rmii_clk(dev);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; dev-&gt;phy_port_cnt; i++) {</div><div class='ctx'> 		ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1439,6 +1456,127 @@ void ksz8_config_cpu_port(struct dsa_switch *ds)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ksz8_phy_port_link_up - Configures ports with integrated PHYs</div><div class='add'>+ * @dev: The KSZ device instance.</div><div class='add'>+ * @port: The port number to configure.</div><div class='add'>+ * @duplex: The desired duplex mode.</div><div class='add'>+ * @tx_pause: If true, enables transmit pause.</div><div class='add'>+ * @rx_pause: If true, enables receive pause.</div><div class='add'>+ *</div><div class='add'>+ * Description:</div><div class='add'>+ * The function configures flow control settings for a given port based on the</div><div class='add'>+ * desired settings and current duplex mode.</div><div class='add'>+ *</div><div class='add'>+ * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the</div><div class='add'>+ * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)</div><div class='add'>+ * determines how flow control is handled on the port:</div><div class='add'>+ *    "1 = will always enable full-duplex flow control on the port, regardless</div><div class='add'>+ *         of AN result.</div><div class='add'>+ *     0 = full-duplex flow control is enabled based on AN result."</div><div class='add'>+ *</div><div class='add'>+ * This means that the flow control behavior depends on the state of this bit:</div><div class='add'>+ * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and</div><div class='add'>+ *   force flow control on the port.</div><div class='add'>+ * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable</div><div class='add'>+ *   flow control based on the AN results.</div><div class='add'>+ *</div><div class='add'>+ * However, there is a potential limitation in this configuration. It is</div><div class='add'>+ * currently not possible to force disable flow control on a port if we still</div><div class='add'>+ * advertise pause support. While such a configuration is not currently</div><div class='add'>+ * supported by Linux, and may not make practical sense, it's important to be</div><div class='add'>+ * aware of this limitation when working with the KSZ8873 and similar devices.</div><div class='add'>+ */</div><div class='add'>+static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,</div><div class='add'>+				  bool tx_pause, bool rx_pause)</div><div class='add'>+{</div><div class='add'>+	const u16 *regs = dev-&gt;info-&gt;regs;</div><div class='add'>+	u8 sctrl = 0;</div><div class='add'>+</div><div class='add'>+	/* The KSZ8795 switch differs from the KSZ8873 by supporting</div><div class='add'>+	 * asymmetric pause control. However, since a single bit is used to</div><div class='add'>+	 * control both RX and TX pause, we can't enforce asymmetric pause</div><div class='add'>+	 * control - both TX and RX pause will be either enabled or disabled</div><div class='add'>+	 * together.</div><div class='add'>+	 *</div><div class='add'>+	 * If auto-negotiation is enabled, we usually allow the flow control to</div><div class='add'>+	 * be determined by the auto-negotiation process based on the</div><div class='add'>+	 * capabilities of both link partners. However, for KSZ8873, the</div><div class='add'>+	 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,</div><div class='add'>+	 * ignoring the auto-negotiation result. Thus, even in auto-negotiation</div><div class='add'>+	 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is</div><div class='add'>+	 * properly cleared.</div><div class='add'>+	 *</div><div class='add'>+	 * In the absence of pause auto-negotiation, we will enforce symmetric</div><div class='add'>+	 * pause control for both variants of switches - KSZ8873 and KSZ8795.</div><div class='add'>+	 *</div><div class='add'>+	 * Autoneg Pause Autoneg      rx,tx	PORT_FORCE_FLOW_CTRL</div><div class='add'>+	 * 1		1		x	0</div><div class='add'>+	 * 0		1		x	0 (flow control probably disabled)</div><div class='add'>+	 * x		0		1	1 (flow control force enabled)</div><div class='add'>+	 * 1		0		0	0 (flow control still depends on</div><div class='add'>+	 *					   aneg result due to hardware)</div><div class='add'>+	 * 0		0		0	0 (flow control probably disabled)</div><div class='add'>+	 */</div><div class='add'>+	if (dev-&gt;ports[port].manual_flow &amp;&amp; tx_pause)</div><div class='add'>+		sctrl |= PORT_FORCE_FLOW_CTRL;</div><div class='add'>+</div><div class='add'>+	ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ksz8_cpu_port_link_up - Configures the CPU port of the switch.</div><div class='add'>+ * @dev: The KSZ device instance.</div><div class='add'>+ * @speed: The desired link speed.</div><div class='add'>+ * @duplex: The desired duplex mode.</div><div class='add'>+ * @tx_pause: If true, enables transmit pause.</div><div class='add'>+ * @rx_pause: If true, enables receive pause.</div><div class='add'>+ *</div><div class='add'>+ * Description:</div><div class='add'>+ * The function configures flow control and speed settings for the CPU</div><div class='add'>+ * port of the switch based on the desired settings, current duplex mode, and</div><div class='add'>+ * speed.</div><div class='add'>+ */</div><div class='add'>+static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,</div><div class='add'>+				  bool tx_pause, bool rx_pause)</div><div class='add'>+{</div><div class='add'>+	const u16 *regs = dev-&gt;info-&gt;regs;</div><div class='add'>+	u8 ctrl = 0;</div><div class='add'>+</div><div class='add'>+	/* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable</div><div class='add'>+	 * at least on KSZ8873. They can have different values depending on your</div><div class='add'>+	 * board setup.</div><div class='add'>+	 */</div><div class='add'>+	if (tx_pause || rx_pause)</div><div class='add'>+		ctrl |= SW_FLOW_CTRL;</div><div class='add'>+</div><div class='add'>+	if (duplex == DUPLEX_HALF)</div><div class='add'>+		ctrl |= SW_HALF_DUPLEX;</div><div class='add'>+</div><div class='add'>+	/* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10</div><div class='add'>+	 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.</div><div class='add'>+	 */</div><div class='add'>+	if (speed == SPEED_10)</div><div class='add'>+		ctrl |= SW_10_MBIT;</div><div class='add'>+</div><div class='add'>+	ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |</div><div class='add'>+		 SW_10_MBIT, ctrl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,</div><div class='add'>+			      unsigned int mode, phy_interface_t interface,</div><div class='add'>+			      struct phy_device *phydev, int speed, int duplex,</div><div class='add'>+			      bool tx_pause, bool rx_pause)</div><div class='add'>+{</div><div class='add'>+	/* If the port is the CPU port, apply special handling. Only the CPU</div><div class='add'>+	 * port is configured via global registers.</div><div class='add'>+	 */</div><div class='add'>+	if (dev-&gt;cpu_port == port)</div><div class='add'>+		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);</div><div class='add'>+	else if (dev-&gt;info-&gt;internal_phy[port])</div><div class='add'>+		ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ksz8_handle_global_errata(struct dsa_switch *ds)</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_device *dev = ds-&gt;priv;</div><div class='hunk'>@@ -1487,8 +1625,6 @@ int ksz8_setup(struct dsa_switch *ds)</div><div class='ctx'> 	 */</div><div class='ctx'> 	ds-&gt;vlan_filtering_is_global = true;</div><div class='ctx'> </div><div class='del'>-	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);</div><div class='del'>-</div><div class='ctx'> 	/* Enable automatic fast aging when link changed detected. */</div><div class='ctx'> 	ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/microchip/ksz8795_reg.h b/drivers/net/dsa/microchip/ksz8795_reg.h<br/>index 3c9dae53e4d8..beca974e0171 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8795_reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/microchip/ksz8795_reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz8795_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz8795_reg.h</a></div><div class='hunk'>@@ -22,6 +22,9 @@</div><div class='ctx'> #define KSZ8863_GLOBAL_SOFTWARE_RESET	BIT(4)</div><div class='ctx'> #define KSZ8863_PCS_RESET		BIT(0)</div><div class='ctx'> </div><div class='add'>+#define KSZ88X3_REG_FVID_AND_HOST_MODE  0xC6</div><div class='add'>+#define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)</div><div class='add'>+</div><div class='ctx'> #define REG_SW_CTRL_0			0x02</div><div class='ctx'> </div><div class='ctx'> #define SW_NEW_BACKOFF			BIT(7)</div><div class='head'>diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c<br/>index 3fed406fb46a..245dfb7a7a31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/microchip/ksz_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz_common.c</a></div><div class='hunk'>@@ -277,6 +277,7 @@ static const struct ksz_dev_ops ksz8_dev_ops = {</div><div class='ctx'> 	.mirror_add = ksz8_port_mirror_add,</div><div class='ctx'> 	.mirror_del = ksz8_port_mirror_del,</div><div class='ctx'> 	.get_caps = ksz8_get_caps,</div><div class='add'>+	.phylink_mac_link_up = ksz8_phylink_mac_link_up,</div><div class='ctx'> 	.config_cpu_port = ksz8_config_cpu_port,</div><div class='ctx'> 	.enable_stp_addr = ksz8_enable_stp_addr,</div><div class='ctx'> 	.reset = ksz8_reset_switch,</div><div class='hunk'>@@ -1672,15 +1673,23 @@ static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)</div><div class='ctx'> </div><div class='ctx'> static int ksz_check_device_id(struct ksz_device *dev)</div><div class='ctx'> {</div><div class='del'>-	const struct ksz_chip_data *dt_chip_data;</div><div class='add'>+	const struct ksz_chip_data *expected_chip_data;</div><div class='add'>+	u32 expected_chip_id;</div><div class='ctx'> </div><div class='del'>-	dt_chip_data = of_device_get_match_data(dev-&gt;dev);</div><div class='add'>+	if (dev-&gt;pdata) {</div><div class='add'>+		expected_chip_id = dev-&gt;pdata-&gt;chip_id;</div><div class='add'>+		expected_chip_data = ksz_lookup_info(expected_chip_id);</div><div class='add'>+		if (WARN_ON(!expected_chip_data))</div><div class='add'>+			return -ENODEV;</div><div class='add'>+	} else {</div><div class='add'>+		expected_chip_data = of_device_get_match_data(dev-&gt;dev);</div><div class='add'>+		expected_chip_id = expected_chip_data-&gt;chip_id;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* Check for Device Tree and Chip ID */</div><div class='del'>-	if (dt_chip_data-&gt;chip_id != dev-&gt;chip_id) {</div><div class='add'>+	if (expected_chip_id != dev-&gt;chip_id) {</div><div class='ctx'> 		dev_err(dev-&gt;dev,</div><div class='ctx'> 			"Device tree specifies chip %s but found %s, please fix it!\n",</div><div class='del'>-			dt_chip_data-&gt;dev_name, dev-&gt;info-&gt;dev_name);</div><div class='add'>+			expected_chip_data-&gt;dev_name, dev-&gt;info-&gt;dev_name);</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2703,7 +2712,7 @@ static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,</div><div class='ctx'> 		proto = DSA_TAG_PROTO_KSZ9477;</div><div class='ctx'> </div><div class='ctx'> 	if (is_lan937x(dev))</div><div class='del'>-		proto = DSA_TAG_PROTO_LAN937X_VALUE;</div><div class='add'>+		proto = DSA_TAG_PROTO_LAN937X;</div><div class='ctx'> </div><div class='ctx'> 	return proto;</div><div class='ctx'> }</div><div class='hunk'>@@ -2713,10 +2722,18 @@ static int ksz_connect_tag_protocol(struct dsa_switch *ds,</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_tagger_data *tagger_data;</div><div class='ctx'> </div><div class='del'>-	tagger_data = ksz_tagger_data(ds);</div><div class='del'>-	tagger_data-&gt;xmit_work_fn = ksz_port_deferred_xmit;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	switch (proto) {</div><div class='add'>+	case DSA_TAG_PROTO_KSZ8795:</div><div class='add'>+		return 0;</div><div class='add'>+	case DSA_TAG_PROTO_KSZ9893:</div><div class='add'>+	case DSA_TAG_PROTO_KSZ9477:</div><div class='add'>+	case DSA_TAG_PROTO_LAN937X:</div><div class='add'>+		tagger_data = ksz_tagger_data(ds);</div><div class='add'>+		tagger_data-&gt;xmit_work_fn = ksz_port_deferred_xmit;</div><div class='add'>+		return 0;</div><div class='add'>+	default:</div><div class='add'>+		return -EPROTONOSUPPORT;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,</div><div class='hunk'>@@ -2966,8 +2983,10 @@ static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_device *dev = ds-&gt;priv;</div><div class='ctx'> </div><div class='del'>-	if (ksz_is_ksz88x3(dev))</div><div class='add'>+	if (ksz_is_ksz88x3(dev)) {</div><div class='add'>+		dev-&gt;ports[port].manual_flow = !(state-&gt;pause &amp; MLO_PAUSE_AN);</div><div class='ctx'> 		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Internal PHYs */</div><div class='ctx'> 	if (dev-&gt;info-&gt;internal_phy[port])</div><div class='hunk'>@@ -3110,10 +3129,8 @@ static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,</div><div class='ctx'> {</div><div class='ctx'> 	struct ksz_device *dev = ds-&gt;priv;</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;dev_ops-&gt;phylink_mac_link_up)</div><div class='del'>-		dev-&gt;dev_ops-&gt;phylink_mac_link_up(dev, port, mode, interface,</div><div class='del'>-						  phydev, speed, duplex,</div><div class='del'>-						  tx_pause, rx_pause);</div><div class='add'>+	dev-&gt;dev_ops-&gt;phylink_mac_link_up(dev, port, mode, interface, phydev,</div><div class='add'>+					  speed, duplex, tx_pause, rx_pause);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ksz_switch_detect(struct ksz_device *dev)</div><div class='hunk'>@@ -4155,9 +4172,6 @@ int ksz_switch_register(struct ksz_device *dev)</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;pdata)</div><div class='del'>-		dev-&gt;chip_id = dev-&gt;pdata-&gt;chip_id;</div><div class='del'>-</div><div class='ctx'> 	dev-&gt;reset_gpio = devm_gpiod_get_optional(dev-&gt;dev, "reset",</div><div class='ctx'> 						  GPIOD_OUT_LOW);</div><div class='ctx'> 	if (IS_ERR(dev-&gt;reset_gpio))</div><div class='head'>diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h<br/>index b7e8a403a132..15612101a155 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/microchip/ksz_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/microchip/ksz_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/microchip/ksz_common.h</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include &lt;linux/regmap.h&gt;</div><div class='ctx'> #include &lt;net/dsa.h&gt;</div><div class='ctx'> #include &lt;linux/irq.h&gt;</div><div class='add'>+#include &lt;linux/platform_data/microchip-ksz.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "ksz_ptp.h"</div><div class='ctx'> </div><div class='hunk'>@@ -134,6 +135,7 @@ struct ksz_port {</div><div class='ctx'> 	ktime_t tstamp_msg;</div><div class='ctx'> 	struct completion tstamp_msg_comp;</div><div class='ctx'> #endif</div><div class='add'>+	bool manual_flow;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ksz_device {</div><div class='hunk'>@@ -202,25 +204,6 @@ enum ksz_model {</div><div class='ctx'> 	LAN9374,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum ksz_chip_id {</div><div class='del'>-	KSZ8563_CHIP_ID = 0x8563,</div><div class='del'>-	KSZ8795_CHIP_ID = 0x8795,</div><div class='del'>-	KSZ8794_CHIP_ID = 0x8794,</div><div class='del'>-	KSZ8765_CHIP_ID = 0x8765,</div><div class='del'>-	KSZ8830_CHIP_ID = 0x8830,</div><div class='del'>-	KSZ9477_CHIP_ID = 0x00947700,</div><div class='del'>-	KSZ9896_CHIP_ID = 0x00989600,</div><div class='del'>-	KSZ9897_CHIP_ID = 0x00989700,</div><div class='del'>-	KSZ9893_CHIP_ID = 0x00989300,</div><div class='del'>-	KSZ9563_CHIP_ID = 0x00956300,</div><div class='del'>-	KSZ9567_CHIP_ID = 0x00956700,</div><div class='del'>-	LAN9370_CHIP_ID = 0x00937000,</div><div class='del'>-	LAN9371_CHIP_ID = 0x00937100,</div><div class='del'>-	LAN9372_CHIP_ID = 0x00937200,</div><div class='del'>-	LAN9373_CHIP_ID = 0x00937300,</div><div class='del'>-	LAN9374_CHIP_ID = 0x00937400,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> enum ksz_regs {</div><div class='ctx'> 	REG_SW_MAC_ADDR,</div><div class='ctx'> 	REG_IND_CTRL_0,</div><div class='head'>diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c<br/>index d27c6b70a2f6..391c4dbdff42 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mt7530.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mt7530.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mt7530.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mt7530.c</a></div><div class='hunk'>@@ -836,7 +836,7 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(mt7530_mib); i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", mt7530_mib[i].name);</div><div class='add'>+		ethtool_puts(&amp;data, mt7530_mib[i].name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c<br/>index 42b1acaca33a..383b3c4d6f59 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/chip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/chip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/chip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/chip.c</a></div><div class='hunk'>@@ -577,6 +577,18 @@ static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,</div><div class='ctx'> 	config-&gt;mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       struct phylink_config *config)</div><div class='add'>+{</div><div class='add'>+	unsigned long *supported = config-&gt;supported_interfaces;</div><div class='add'>+</div><div class='add'>+	/* Translate the default cmode */</div><div class='add'>+	mv88e6xxx_translate_cmode(chip-&gt;ports[port].cmode, supported);</div><div class='add'>+</div><div class='add'>+	config-&gt;mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |</div><div class='add'>+				   MAC_1000FD;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)</div><div class='ctx'> {</div><div class='ctx'> 	u16 reg, val;</div><div class='hunk'>@@ -931,76 +943,94 @@ error:</div><div class='ctx'> </div><div class='ctx'> static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)</div><div class='ctx'> {</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='ctx'> 	if (!chip-&gt;info-&gt;ops-&gt;stats_snapshot)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	return chip-&gt;info-&gt;ops-&gt;stats_snapshot(chip, port);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {</div><div class='del'>-	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "single",			4, 0x14, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },</div><div class='del'>-	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },</div><div class='del'>-	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },</div><div class='del'>-	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },</div><div class='del'>-	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },</div><div class='del'>-	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },</div><div class='add'>+	mv88e6xxx_reg_lock(chip);</div><div class='add'>+	err = chip-&gt;info-&gt;ops-&gt;stats_snapshot(chip, port);</div><div class='add'>+	mv88e6xxx_reg_unlock(chip);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define MV88E6XXX_HW_STAT_MAPPER(_fn)				    \</div><div class='add'>+	_fn(in_good_octets,		8, 0x00, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_bad_octets,		4, 0x02, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_unicast,			4, 0x04, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_broadcasts,		4, 0x06, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_multicasts,		4, 0x07, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_pause,			4, 0x16, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_undersize,		4, 0x18, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_fragments,		4, 0x19, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_oversize,		4, 0x1a, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_jabber,			4, 0x1b, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_rx_error,		4, 0x1c, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(in_fcs_error,		4, 0x1d, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_octets,			8, 0x0e, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_unicast,		4, 0x10, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_broadcasts,		4, 0x13, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_multicasts,		4, 0x12, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_pause,			4, 0x15, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(excessive,			4, 0x11, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(collisions,			4, 0x1e, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(deferred,			4, 0x05, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(single,			4, 0x14, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(multiple,			4, 0x17, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(out_fcs_error,		4, 0x03, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(late,			4, 0x1f, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_64bytes,		4, 0x08, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_65_127bytes,		4, 0x09, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_128_255bytes,		4, 0x0a, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_256_511bytes,		4, 0x0b, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_512_1023bytes,		4, 0x0c, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(hist_1024_max_bytes,	4, 0x0d, STATS_TYPE_BANK0), \</div><div class='add'>+	_fn(sw_in_discards,		4, 0x10, STATS_TYPE_PORT), \</div><div class='add'>+	_fn(sw_in_filtered,		2, 0x12, STATS_TYPE_PORT), \</div><div class='add'>+	_fn(sw_out_filtered,		2, 0x13, STATS_TYPE_PORT), \</div><div class='add'>+	_fn(in_discards,		4, 0x00, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_filtered,		4, 0x01, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_accepted,		4, 0x02, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_bad_accepted,		4, 0x03, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_good_avb_class_a,	4, 0x04, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_good_avb_class_b,	4, 0x05, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_bad_avb_class_a,		4, 0x06, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_bad_avb_class_b,		4, 0x07, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(tcam_counter_0,		4, 0x08, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(tcam_counter_1,		4, 0x09, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(tcam_counter_2,		4, 0x0a, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(tcam_counter_3,		4, 0x0b, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_da_unknown,		4, 0x0e, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(in_management,		4, 0x0f, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_0,		4, 0x10, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_1,		4, 0x11, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_2,		4, 0x12, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_3,		4, 0x13, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_4,		4, 0x14, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_5,		4, 0x15, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_6,		4, 0x16, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_queue_7,		4, 0x17, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_cut_through,		4, 0x18, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_octets_a,		4, 0x1a, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_octets_b,		4, 0x1b, STATS_TYPE_BANK1), \</div><div class='add'>+	_fn(out_management,		4, 0x1f, STATS_TYPE_BANK1), \</div><div class='add'>+	/*  */</div><div class='add'>+</div><div class='add'>+#define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \</div><div class='add'>+	{ #_string, _size, _reg, _type }</div><div class='add'>+static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {</div><div class='add'>+	MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \</div><div class='add'>+	MV88E6XXX_HW_STAT_ID_ ## _string</div><div class='add'>+enum mv88e6xxx_hw_stat_id {</div><div class='add'>+	MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,</div><div class='del'>-					    struct mv88e6xxx_hw_stat *s,</div><div class='add'>+					    const struct mv88e6xxx_hw_stat *s,</div><div class='ctx'> 					    int port, u16 bank1_select,</div><div class='ctx'> 					    u16 histogram)</div><div class='ctx'> {</div><div class='hunk'>@@ -1043,7 +1073,7 @@ static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,</div><div class='ctx'> static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 				       uint8_t *data, int types)</div><div class='ctx'> {</div><div class='del'>-	struct mv88e6xxx_hw_stat *stat;</div><div class='add'>+	const struct mv88e6xxx_hw_stat *stat;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, j = 0; i &lt; ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {</div><div class='hunk'>@@ -1124,7 +1154,7 @@ static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,</div><div class='ctx'> static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 					  int types)</div><div class='ctx'> {</div><div class='del'>-	struct mv88e6xxx_hw_stat *stat;</div><div class='add'>+	const struct mv88e6xxx_hw_stat *stat;</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0, j = 0; i &lt; ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {</div><div class='hunk'>@@ -1183,59 +1213,82 @@ out:</div><div class='ctx'> 	return count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-				     uint64_t *data, int types,</div><div class='del'>-				     u16 bank1_select, u16 histogram)</div><div class='add'>+static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				       uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	struct mv88e6xxx_hw_stat *stat;</div><div class='del'>-	int i, j;</div><div class='add'>+	if (!(stat-&gt;type &amp; (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0, j = 0; i &lt; ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {</div><div class='del'>-		stat = &amp;mv88e6xxx_hw_stats[i];</div><div class='del'>-		if (stat-&gt;type &amp; types) {</div><div class='del'>-			mv88e6xxx_reg_lock(chip);</div><div class='del'>-			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,</div><div class='del'>-							      bank1_select,</div><div class='del'>-							      histogram);</div><div class='del'>-			mv88e6xxx_reg_unlock(chip);</div><div class='add'>+	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,</div><div class='add'>+					    MV88E6XXX_G1_STATS_OP_HIST_RX);</div><div class='add'>+	return 1;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-			j++;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return j;</div><div class='add'>+static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				       uint64_t *data)</div><div class='add'>+{</div><div class='add'>+	if (!(stat-&gt;type &amp; STATS_TYPE_BANK0))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,</div><div class='add'>+					    MV88E6XXX_G1_STATS_OP_HIST_RX);</div><div class='add'>+	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-				     uint64_t *data)</div><div class='add'>+static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				       uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	return mv88e6xxx_stats_get_stats(chip, port, data,</div><div class='del'>-					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,</div><div class='del'>-					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);</div><div class='add'>+	if (!(stat-&gt;type &amp; (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,</div><div class='add'>+					    MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,</div><div class='add'>+					    MV88E6XXX_G1_STATS_OP_HIST_RX);</div><div class='add'>+	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-				     uint64_t *data)</div><div class='add'>+static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				       uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,</div><div class='del'>-					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);</div><div class='add'>+	if (!(stat-&gt;type &amp; (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,</div><div class='add'>+					    MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,</div><div class='add'>+					    0);</div><div class='add'>+	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-				     uint64_t *data)</div><div class='add'>+static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				       const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				       uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	return mv88e6xxx_stats_get_stats(chip, port, data,</div><div class='del'>-					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,</div><div class='del'>-					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,</div><div class='del'>-					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);</div><div class='add'>+	int ret = 0;</div><div class='add'>+</div><div class='add'>+	if (chip-&gt;info-&gt;ops-&gt;stats_get_stat) {</div><div class='add'>+		mv88e6xxx_reg_lock(chip);</div><div class='add'>+		ret = chip-&gt;info-&gt;ops-&gt;stats_get_stat(chip, port, stat, data);</div><div class='add'>+		mv88e6xxx_reg_unlock(chip);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-				     uint64_t *data)</div><div class='add'>+static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+					uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	return mv88e6xxx_stats_get_stats(chip, port, data,</div><div class='del'>-					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,</div><div class='del'>-					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,</div><div class='del'>-					 0);</div><div class='add'>+	const struct mv88e6xxx_hw_stat *stat;</div><div class='add'>+	size_t i, j;</div><div class='add'>+</div><div class='add'>+	for (i = 0, j = 0; i &lt; ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {</div><div class='add'>+		stat = &amp;mv88e6xxx_hw_stats[i];</div><div class='add'>+		j += mv88e6xxx_stats_get_stat(chip, port, stat, &amp;data[j]);</div><div class='add'>+	}</div><div class='add'>+	return j;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='hunk'>@@ -1251,10 +1304,9 @@ static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='ctx'> static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='ctx'> 				uint64_t *data)</div><div class='ctx'> {</div><div class='del'>-	int count = 0;</div><div class='add'>+	size_t count;</div><div class='ctx'> </div><div class='del'>-	if (chip-&gt;info-&gt;ops-&gt;stats_get_stats)</div><div class='del'>-		count = chip-&gt;info-&gt;ops-&gt;stats_get_stats(chip, port, data);</div><div class='add'>+	count = mv88e6xxx_stats_get_stats(chip, port, data);</div><div class='ctx'> </div><div class='ctx'> 	mv88e6xxx_reg_lock(chip);</div><div class='ctx'> 	if (chip-&gt;info-&gt;ops-&gt;serdes_get_stats) {</div><div class='hunk'>@@ -1272,16 +1324,90 @@ static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,</div><div class='ctx'> 	struct mv88e6xxx_chip *chip = ds-&gt;priv;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	mv88e6xxx_reg_lock(chip);</div><div class='add'>+	ret = mv88e6xxx_stats_snapshot(chip, port);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mv88e6xxx_get_stats(chip, port, data);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,</div><div class='add'>+					struct ethtool_eth_mac_stats *mac_stats)</div><div class='add'>+{</div><div class='add'>+	struct mv88e6xxx_chip *chip = ds-&gt;priv;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = mv88e6xxx_stats_snapshot(chip, port);</div><div class='del'>-	mv88e6xxx_reg_unlock(chip);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member)			\</div><div class='add'>+	mv88e6xxx_stats_get_stat(chip, port,				\</div><div class='add'>+				 &amp;mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \</div><div class='add'>+				 &amp;mac_stats-&gt;stats._member)</div><div class='add'>+</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);</div><div class='add'>+	MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);</div><div class='add'>+</div><div class='add'>+#undef MV88E6XXX_ETH_MAC_STAT_MAP</div><div class='add'>+</div><div class='add'>+	mac_stats-&gt;stats.FramesTransmittedOK += mac_stats-&gt;stats.MulticastFramesXmittedOK;</div><div class='add'>+	mac_stats-&gt;stats.FramesTransmittedOK += mac_stats-&gt;stats.BroadcastFramesXmittedOK;</div><div class='add'>+	mac_stats-&gt;stats.FramesReceivedOK += mac_stats-&gt;stats.MulticastFramesReceivedOK;</div><div class='add'>+	mac_stats-&gt;stats.FramesReceivedOK += mac_stats-&gt;stats.BroadcastFramesReceivedOK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,</div><div class='add'>+				     struct ethtool_rmon_stats *rmon_stats,</div><div class='add'>+				     const struct ethtool_rmon_hist_range **ranges)</div><div class='add'>+{</div><div class='add'>+	static const struct ethtool_rmon_hist_range rmon_ranges[] = {</div><div class='add'>+		{   64,    64 },</div><div class='add'>+		{   65,   127 },</div><div class='add'>+		{  128,   255 },</div><div class='add'>+		{  256,   511 },</div><div class='add'>+		{  512,  1023 },</div><div class='add'>+		{ 1024, 65535 },</div><div class='add'>+		{}</div><div class='add'>+	};</div><div class='add'>+	struct mv88e6xxx_chip *chip = ds-&gt;priv;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='add'>+	ret = mv88e6xxx_stats_snapshot(chip, port);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	mv88e6xxx_get_stats(chip, port, data);</div><div class='add'>+#define MV88E6XXX_RMON_STAT_MAP(_id, _member)				\</div><div class='add'>+	mv88e6xxx_stats_get_stat(chip, port,				\</div><div class='add'>+				 &amp;mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \</div><div class='add'>+				 &amp;rmon_stats-&gt;stats._member)</div><div class='add'>+</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);</div><div class='add'>+	MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);</div><div class='ctx'> </div><div class='add'>+#undef MV88E6XXX_RMON_STAT_MAP</div><div class='add'>+</div><div class='add'>+	*ranges = rmon_ranges;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)</div><div class='hunk'>@@ -3880,7 +4006,8 @@ static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)</div><div class='ctx'> 	struct mv88e6xxx_chip *chip = ds-&gt;priv;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_init) {</div><div class='add'>+	if (chip-&gt;info-&gt;ops-&gt;pcs_ops &amp;&amp;</div><div class='add'>+	    chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_init) {</div><div class='ctx'> 		err = chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_init(chip, port);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -3895,7 +4022,8 @@ static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)</div><div class='ctx'> </div><div class='ctx'> 	mv88e6xxx_teardown_devlink_regions_port(ds, port);</div><div class='ctx'> </div><div class='del'>-	if (chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_teardown)</div><div class='add'>+	if (chip-&gt;info-&gt;ops-&gt;pcs_ops &amp;&amp;</div><div class='add'>+	    chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_teardown)</div><div class='ctx'> 		chip-&gt;info-&gt;ops-&gt;pcs_ops-&gt;pcs_teardown(chip, port);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3973,7 +4101,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4011,7 +4139,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,</div><div class='ctx'> 	.ppu_enable = mv88e6185_g1_ppu_enable,</div><div class='ctx'> 	.ppu_disable = mv88e6185_g1_ppu_disable,</div><div class='hunk'>@@ -4052,7 +4180,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4094,7 +4222,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4137,7 +4265,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4186,7 +4314,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4241,7 +4369,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4279,7 +4407,7 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4327,7 +4455,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4340,7 +4468,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {</div><div class='ctx'> 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,</div><div class='ctx'> 	.stu_getnext = mv88e6352_g1_stu_getnext,</div><div class='ctx'> 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,</div><div class='del'>-	.phylink_get_caps = mv88e6185_phylink_get_caps,</div><div class='add'>+	.phylink_get_caps = mv88e6351_phylink_get_caps,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mv88e6xxx_ops mv88e6172_ops = {</div><div class='hunk'>@@ -4376,7 +4504,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4427,7 +4555,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4440,7 +4568,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {</div><div class='ctx'> 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,</div><div class='ctx'> 	.stu_getnext = mv88e6352_g1_stu_getnext,</div><div class='ctx'> 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,</div><div class='del'>-	.phylink_get_caps = mv88e6185_phylink_get_caps,</div><div class='add'>+	.phylink_get_caps = mv88e6351_phylink_get_caps,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mv88e6xxx_ops mv88e6176_ops = {</div><div class='hunk'>@@ -4476,7 +4604,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4521,7 +4649,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4570,7 +4698,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4628,7 +4756,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4684,7 +4812,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4743,7 +4871,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -4796,7 +4924,7 @@ static const struct mv88e6xxx_ops mv88e6250_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6250_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6250_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6250_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6250_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6250_watchdog_ops,</div><div class='hunk'>@@ -4843,7 +4971,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4902,7 +5030,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6320_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6320_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4949,7 +5077,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6320_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6320_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -4998,7 +5126,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -5056,7 +5184,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -5069,7 +5197,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {</div><div class='ctx'> 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,</div><div class='ctx'> 	.stu_getnext = mv88e6352_g1_stu_getnext,</div><div class='ctx'> 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,</div><div class='del'>-	.phylink_get_caps = mv88e6185_phylink_get_caps,</div><div class='add'>+	.phylink_get_caps = mv88e6351_phylink_get_caps,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mv88e6xxx_ops mv88e6351_ops = {</div><div class='hunk'>@@ -5102,7 +5230,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -5117,7 +5245,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {</div><div class='ctx'> 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,</div><div class='ctx'> 	.avb_ops = &amp;mv88e6352_avb_ops,</div><div class='ctx'> 	.ptp_ops = &amp;mv88e6352_ptp_ops,</div><div class='del'>-	.phylink_get_caps = mv88e6185_phylink_get_caps,</div><div class='add'>+	.phylink_get_caps = mv88e6351_phylink_get_caps,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct mv88e6xxx_ops mv88e6352_ops = {</div><div class='hunk'>@@ -5153,7 +5281,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6095_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6095_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6095_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6095_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6095_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6097_watchdog_ops,</div><div class='hunk'>@@ -5215,7 +5343,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -5277,7 +5405,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	.set_cpu_port = mv88e6390_g1_set_cpu_port,</div><div class='ctx'> 	.set_egress_port = mv88e6390_g1_set_egress_port,</div><div class='ctx'> 	.watchdog_ops = &amp;mv88e6390_watchdog_ops,</div><div class='hunk'>@@ -5339,7 +5467,7 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = {</div><div class='ctx'> 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,</div><div class='ctx'> 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,</div><div class='ctx'> 	.stats_get_strings = mv88e6320_stats_get_strings,</div><div class='del'>-	.stats_get_stats = mv88e6390_stats_get_stats,</div><div class='add'>+	.stats_get_stat = mv88e6390_stats_get_stat,</div><div class='ctx'> 	/* .set_cpu_port is missing because this family does not support a global</div><div class='ctx'> 	 * CPU port, only per port CPU port which is set via</div><div class='ctx'> 	 * .port_set_upstream_port method.</div><div class='hunk'>@@ -6803,6 +6931,8 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = {</div><div class='ctx'> 	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,</div><div class='ctx'> 	.get_strings		= mv88e6xxx_get_strings,</div><div class='ctx'> 	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,</div><div class='add'>+	.get_eth_mac_stats	= mv88e6xxx_get_eth_mac_stats,</div><div class='add'>+	.get_rmon_stats		= mv88e6xxx_get_rmon_stats,</div><div class='ctx'> 	.get_sset_count		= mv88e6xxx_get_sset_count,</div><div class='ctx'> 	.port_max_mtu		= mv88e6xxx_get_max_mtu,</div><div class='ctx'> 	.port_change_mtu	= mv88e6xxx_change_mtu,</div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h<br/>index 44383a03ef2f..85eb293381a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/chip.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/chip.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/chip.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/chip.h</a></div><div class='hunk'>@@ -318,6 +318,17 @@ struct mv88e6xxx_mst {</div><div class='ctx'> 	struct mv88e6xxx_stu_entry stu;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define STATS_TYPE_PORT		BIT(0)</div><div class='add'>+#define STATS_TYPE_BANK0	BIT(1)</div><div class='add'>+#define STATS_TYPE_BANK1	BIT(2)</div><div class='add'>+</div><div class='add'>+struct mv88e6xxx_hw_stat {</div><div class='add'>+	char string[ETH_GSTRING_LEN];</div><div class='add'>+	size_t size;</div><div class='add'>+	int reg;</div><div class='add'>+	int type;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mv88e6xxx_chip {</div><div class='ctx'> 	const struct mv88e6xxx_info *info;</div><div class='ctx'> </div><div class='hunk'>@@ -574,8 +585,9 @@ struct mv88e6xxx_ops {</div><div class='ctx'> 	/* Return the number of strings describing statistics */</div><div class='ctx'> 	int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);</div><div class='ctx'> 	int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);</div><div class='del'>-	int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,</div><div class='del'>-			       uint64_t *data);</div><div class='add'>+	size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				 const struct mv88e6xxx_hw_stat *stat,</div><div class='add'>+				 uint64_t *data);</div><div class='ctx'> 	int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);</div><div class='ctx'> 	int (*set_egress_port)(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 			       enum mv88e6xxx_egress_direction direction,</div><div class='hunk'>@@ -601,8 +613,8 @@ struct mv88e6xxx_ops {</div><div class='ctx'> 	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);</div><div class='ctx'> 	int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,</div><div class='ctx'> 				  uint8_t *data);</div><div class='del'>-	int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,</div><div class='del'>-				uint64_t *data);</div><div class='add'>+	size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				   uint64_t *data);</div><div class='ctx'> </div><div class='ctx'> 	/* SERDES registers for ethtool */</div><div class='ctx'> 	int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);</div><div class='hunk'>@@ -727,17 +739,6 @@ struct mv88e6xxx_pcs_ops {</div><div class='ctx'> </div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define STATS_TYPE_PORT		BIT(0)</div><div class='del'>-#define STATS_TYPE_BANK0	BIT(1)</div><div class='del'>-#define STATS_TYPE_BANK1	BIT(2)</div><div class='del'>-</div><div class='del'>-struct mv88e6xxx_hw_stat {</div><div class='del'>-	char string[ETH_GSTRING_LEN];</div><div class='del'>-	size_t size;</div><div class='del'>-	int reg;</div><div class='del'>-	int type;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)</div><div class='ctx'> {</div><div class='ctx'> 	return chip-&gt;info-&gt;max_sid &gt; 0 &amp;&amp;</div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c<br/>index 174c773b38c2..49444a72ff09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/global1.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/global1.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/global1.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/global1.c</a></div><div class='hunk'>@@ -462,8 +462,7 @@ int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)</div><div class='ctx'> int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)</div><div class='ctx'> {</div><div class='ctx'> 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,</div><div class='del'>-				      MV88E6390_G1_CTL2_HIST_MODE_RX |</div><div class='del'>-				      MV88E6390_G1_CTL2_HIST_MODE_TX);</div><div class='add'>+				      MV88E6390_G1_CTL2_HIST_MODE_RX);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)</div><div class='hunk'>@@ -491,7 +490,7 @@ int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;</div><div class='add'>+	val |= MV88E6XXX_G1_STATS_OP_HIST_RX;</div><div class='ctx'> </div><div class='ctx'> 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);</div><div class='ctx'> </div><div class='hunk'>@@ -506,7 +505,7 @@ int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)</div><div class='ctx'> 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,</div><div class='ctx'> 				 MV88E6XXX_G1_STATS_OP_BUSY |</div><div class='ctx'> 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |</div><div class='del'>-				 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);</div><div class='add'>+				 MV88E6XXX_G1_STATS_OP_HIST_RX | port);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/pcs-639x.c b/drivers/net/dsa/mv88e6xxx/pcs-639x.c<br/>index 9a8429f5d09c..d758a6c1b226 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/pcs-639x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/pcs-639x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/pcs-639x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/pcs-639x.c</a></div><div class='hunk'>@@ -465,6 +465,7 @@ mv88e639x_pcs_select(struct mv88e6xxx_chip *chip, int port,</div><div class='ctx'> 	case PHY_INTERFACE_MODE_10GBASER:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_XAUI:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_RXAUI:</div><div class='add'>+	case PHY_INTERFACE_MODE_USXGMII:</div><div class='ctx'> 		return &amp;mpcs-&gt;xg_pcs;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='hunk'>@@ -873,7 +874,8 @@ static int mv88e6393x_xg_pcs_post_config(struct phylink_pcs *pcs,</div><div class='ctx'> 	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (interface == PHY_INTERFACE_MODE_10GBASER) {</div><div class='add'>+	if (interface == PHY_INTERFACE_MODE_10GBASER ||</div><div class='add'>+	    interface == PHY_INTERFACE_MODE_USXGMII) {</div><div class='ctx'> 		err = mv88e6393x_erratum_5_2(mpcs);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='hunk'>@@ -886,12 +888,37 @@ static int mv88e6393x_xg_pcs_post_config(struct phylink_pcs *pcs,</div><div class='ctx'> 	return mv88e639x_xg_pcs_enable(mpcs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mv88e6393x_xg_pcs_get_state(struct phylink_pcs *pcs,</div><div class='add'>+					struct phylink_link_state *state)</div><div class='add'>+{</div><div class='add'>+	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);</div><div class='add'>+	u16 status, lp_status;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (state-&gt;interface != PHY_INTERFACE_MODE_USXGMII)</div><div class='add'>+		return mv88e639x_xg_pcs_get_state(pcs, state);</div><div class='add'>+</div><div class='add'>+	state-&gt;link = false;</div><div class='add'>+</div><div class='add'>+	err = mv88e639x_read(mpcs, MV88E6390_USXGMII_PHY_STATUS, &amp;status);</div><div class='add'>+	err = err ? : mv88e639x_read(mpcs, MV88E6390_USXGMII_LP_STATUS, &amp;lp_status);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(mpcs-&gt;mdio.dev.parent,</div><div class='add'>+			"can't read USXGMII status: %pe\n", ERR_PTR(err));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	state-&gt;link = !!(status &amp; MDIO_USXGMII_LINK);</div><div class='add'>+	state-&gt;an_complete = state-&gt;link;</div><div class='add'>+	phylink_decode_usxgmii_word(state, lp_status);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct phylink_pcs_ops mv88e6393x_xg_pcs_ops = {</div><div class='ctx'> 	.pcs_enable = mv88e6393x_xg_pcs_enable,</div><div class='ctx'> 	.pcs_disable = mv88e6393x_xg_pcs_disable,</div><div class='ctx'> 	.pcs_pre_config = mv88e6393x_xg_pcs_pre_config,</div><div class='ctx'> 	.pcs_post_config = mv88e6393x_xg_pcs_post_config,</div><div class='del'>-	.pcs_get_state = mv88e639x_xg_pcs_get_state,</div><div class='add'>+	.pcs_get_state = mv88e6393x_xg_pcs_get_state,</div><div class='ctx'> 	.pcs_config = mv88e639x_xg_pcs_config,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c<br/>index 3b4b42651fa3..01ea53940786 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/serdes.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/serdes.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/serdes.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/serdes.c</a></div><div class='hunk'>@@ -177,8 +177,8 @@ static uint64_t mv88e6352_serdes_get_stat(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 	return val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-			       uint64_t *data)</div><div class='add'>+size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				  uint64_t *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct mv88e6xxx_port *mv88e6xxx_port = &amp;chip-&gt;ports[port];</div><div class='ctx'> 	struct mv88e6352_serdes_hw_stat *stat;</div><div class='hunk'>@@ -187,7 +187,7 @@ int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='ctx'> </div><div class='ctx'> 	err = mv88e6352_g2_scratch_port_has_serdes(chip, port);</div><div class='ctx'> 	if (err &lt;= 0)</div><div class='del'>-		return err;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	BUILD_BUG_ON(ARRAY_SIZE(mv88e6352_serdes_hw_stats) &gt;</div><div class='ctx'> 		     ARRAY_SIZE(mv88e6xxx_port-&gt;serdes_stats));</div><div class='hunk'>@@ -429,8 +429,8 @@ static uint64_t mv88e6390_serdes_get_stat(struct mv88e6xxx_chip *chip, int lane,</div><div class='ctx'> 	return reg[0] | ((u64)reg[1] &lt;&lt; 16) | ((u64)reg[2] &lt;&lt; 32);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-			       uint64_t *data)</div><div class='add'>+size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				  uint64_t *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct mv88e6390_serdes_hw_stat *stat;</div><div class='ctx'> 	int lane;</div><div class='head'>diff --git a/drivers/net/dsa/mv88e6xxx/serdes.h b/drivers/net/dsa/mv88e6xxx/serdes.h<br/>index aac95cab46e3..ff5c3ab31e15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/serdes.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/mv88e6xxx/serdes.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/mv88e6xxx/serdes.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/mv88e6xxx/serdes.h</a></div><div class='hunk'>@@ -127,13 +127,13 @@ unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,</div><div class='ctx'> int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);</div><div class='ctx'> int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 				 int port, uint8_t *data);</div><div class='del'>-int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-			       uint64_t *data);</div><div class='add'>+size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				  uint64_t *data);</div><div class='ctx'> int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);</div><div class='ctx'> int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,</div><div class='ctx'> 				 int port, uint8_t *data);</div><div class='del'>-int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='del'>-			       uint64_t *data);</div><div class='add'>+size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,</div><div class='add'>+				  uint64_t *data);</div><div class='ctx'> </div><div class='ctx'> int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);</div><div class='ctx'> void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);</div><div class='head'>diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c<br/>index ec57d9d52072..c51f40960961 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-8xxx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/qca/qca8k-8xxx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-8xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-8xxx.c</a></div><div class='hunk'>@@ -947,36 +947,49 @@ static int</div><div class='ctx'> qca8k_mdio_register(struct qca8k_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct dsa_switch *ds = priv-&gt;ds;</div><div class='add'>+	struct device *dev = ds-&gt;dev;</div><div class='ctx'> 	struct device_node *mdio;</div><div class='ctx'> 	struct mii_bus *bus;</div><div class='add'>+	int err = 0;</div><div class='ctx'> </div><div class='del'>-	bus = devm_mdiobus_alloc(ds-&gt;dev);</div><div class='del'>-	if (!bus)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	mdio = of_get_child_by_name(dev-&gt;of_node, "mdio");</div><div class='add'>+	if (mdio &amp;&amp; !of_device_is_available(mdio))</div><div class='add'>+		goto out;</div><div class='add'>+</div><div class='add'>+	bus = devm_mdiobus_alloc(dev);</div><div class='add'>+	if (!bus) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto out_put_node;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	priv-&gt;internal_mdio_bus = bus;</div><div class='ctx'> 	bus-&gt;priv = (void *)priv;</div><div class='ctx'> 	snprintf(bus-&gt;id, MII_BUS_ID_SIZE, "qca8k-%d.%d",</div><div class='ctx'> 		 ds-&gt;dst-&gt;index, ds-&gt;index);</div><div class='del'>-	bus-&gt;parent = ds-&gt;dev;</div><div class='del'>-	bus-&gt;phy_mask = ~ds-&gt;phys_mii_mask;</div><div class='del'>-	ds-&gt;user_mii_bus = bus;</div><div class='add'>+	bus-&gt;parent = dev;</div><div class='ctx'> </div><div class='del'>-	/* Check if the devicetree declare the port:phy mapping */</div><div class='del'>-	mdio = of_get_child_by_name(priv-&gt;dev-&gt;of_node, "mdio");</div><div class='del'>-	if (of_device_is_available(mdio)) {</div><div class='add'>+	if (mdio) {</div><div class='add'>+		/* Check if the device tree declares the port:phy mapping */</div><div class='ctx'> 		bus-&gt;name = "qca8k user mii";</div><div class='ctx'> 		bus-&gt;read = qca8k_internal_mdio_read;</div><div class='ctx'> 		bus-&gt;write = qca8k_internal_mdio_write;</div><div class='del'>-		return devm_of_mdiobus_register(priv-&gt;dev, bus, mdio);</div><div class='add'>+	} else {</div><div class='add'>+		/* If a mapping can't be found, the legacy mapping is used,</div><div class='add'>+		 * using qca8k_port_to_phy()</div><div class='add'>+		 */</div><div class='add'>+		ds-&gt;user_mii_bus = bus;</div><div class='add'>+		bus-&gt;phy_mask = ~ds-&gt;phys_mii_mask;</div><div class='add'>+		bus-&gt;name = "qca8k-legacy user mii";</div><div class='add'>+		bus-&gt;read = qca8k_legacy_mdio_read;</div><div class='add'>+		bus-&gt;write = qca8k_legacy_mdio_write;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* If a mapping can't be found the legacy mapping is used,</div><div class='del'>-	 * using the qca8k_port_to_phy function</div><div class='del'>-	 */</div><div class='del'>-	bus-&gt;name = "qca8k-legacy user mii";</div><div class='del'>-	bus-&gt;read = qca8k_legacy_mdio_read;</div><div class='del'>-	bus-&gt;write = qca8k_legacy_mdio_write;</div><div class='del'>-	return devm_mdiobus_register(priv-&gt;dev, bus);</div><div class='add'>+	err = devm_of_mdiobus_register(dev, bus, mdio);</div><div class='add'>+</div><div class='add'>+out_put_node:</div><div class='add'>+	of_node_put(mdio);</div><div class='add'>+out:</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='head'>diff --git a/drivers/net/dsa/qca/qca8k-common.c b/drivers/net/dsa/qca/qca8k-common.c<br/>index 9243eff8918d..2358cd399c7e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/qca/qca8k-common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-common.c</a></div><div class='hunk'>@@ -487,7 +487,7 @@ void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;info-&gt;mib_count; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", ar8327_mib[i].name);</div><div class='add'>+		ethtool_puts(&amp;data, ar8327_mib[i].name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,</div><div class='head'>diff --git a/drivers/net/dsa/qca/qca8k-leds.c b/drivers/net/dsa/qca/qca8k-leds.c<br/>index 90e30c2909e4..811ebeeff4ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-leds.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/qca/qca8k-leds.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k-leds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k-leds.c</a></div><div class='hunk'>@@ -366,7 +366,6 @@ qca8k_parse_port_leds(struct qca8k_priv *priv, struct fwnode_handle *port, int p</div><div class='ctx'> {</div><div class='ctx'> 	struct fwnode_handle *led = NULL, *leds = NULL;</div><div class='ctx'> 	struct led_init_data init_data = { };</div><div class='del'>-	struct dsa_switch *ds = priv-&gt;ds;</div><div class='ctx'> 	enum led_default_state state;</div><div class='ctx'> 	struct qca8k_led *port_led;</div><div class='ctx'> 	int led_num, led_index;</div><div class='hunk'>@@ -429,7 +428,8 @@ qca8k_parse_port_leds(struct qca8k_priv *priv, struct fwnode_handle *port, int p</div><div class='ctx'> 		init_data.default_label = ":port";</div><div class='ctx'> 		init_data.fwnode = led;</div><div class='ctx'> 		init_data.devname_mandatory = true;</div><div class='del'>-		init_data.devicename = kasprintf(GFP_KERNEL, "%s:0%d", ds-&gt;user_mii_bus-&gt;id,</div><div class='add'>+		init_data.devicename = kasprintf(GFP_KERNEL, "%s:0%d",</div><div class='add'>+						 priv-&gt;internal_mdio_bus-&gt;id,</div><div class='ctx'> 						 port_num);</div><div class='ctx'> 		if (!init_data.devicename)</div><div class='ctx'> 			return -ENOMEM;</div><div class='head'>diff --git a/drivers/net/dsa/qca/qca8k.h b/drivers/net/dsa/qca/qca8k.h<br/>index 2ac7e88f8da5..c8785c36c54e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/qca/qca8k.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/qca/qca8k.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/qca/qca8k.h</a></div><div class='hunk'>@@ -454,6 +454,7 @@ struct qca8k_priv {</div><div class='ctx'> 	struct qca8k_ports_config ports_config;</div><div class='ctx'> 	struct regmap *regmap;</div><div class='ctx'> 	struct mii_bus *bus;</div><div class='add'>+	struct mii_bus *internal_mdio_bus;</div><div class='ctx'> 	struct dsa_switch *ds;</div><div class='ctx'> 	struct mutex reg_mutex;</div><div class='ctx'> 	struct device *dev;</div><div class='head'>diff --git a/drivers/net/dsa/realtek/rtl8365mb.c b/drivers/net/dsa/realtek/rtl8365mb.c<br/>index 0875e4fc9f57..b072045eb154 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8365mb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/realtek/rtl8365mb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8365mb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8365mb.c</a></div><div class='hunk'>@@ -1303,7 +1303,7 @@ static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; RTL8365MB_MIB_END; i++) {</div><div class='ctx'> 		struct rtl8365mb_mib_counter *mib = &amp;rtl8365mb_mib_counters[i];</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", mib-&gt;name);</div><div class='add'>+		ethtool_puts(&amp;data, mib-&gt;name);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/realtek/rtl8366-core.c b/drivers/net/dsa/realtek/rtl8366-core.c<br/>index 82e267b8fddb..59f98d2c8769 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8366-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/realtek/rtl8366-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8366-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8366-core.c</a></div><div class='hunk'>@@ -401,7 +401,7 @@ void rtl8366_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;num_mib_counters; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", priv-&gt;mib_counters[i].name);</div><div class='add'>+		ethtool_puts(&amp;data, priv-&gt;mib_counters[i].name);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(rtl8366_get_strings);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/realtek/rtl8366rb.c b/drivers/net/dsa/realtek/rtl8366rb.c<br/>index b39b719a5b8f..e3b6a470ca67 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8366rb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/realtek/rtl8366rb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/realtek/rtl8366rb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/realtek/rtl8366rb.c</a></div><div class='hunk'>@@ -15,6 +15,7 @@</div><div class='ctx'> #include &lt;linux/bitops.h&gt;</div><div class='ctx'> #include &lt;linux/etherdevice.h&gt;</div><div class='ctx'> #include &lt;linux/if_bridge.h&gt;</div><div class='add'>+#include &lt;linux/if_vlan.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/irqdomain.h&gt;</div><div class='ctx'> #include &lt;linux/irqchip/chained_irq.h&gt;</div><div class='hunk'>@@ -117,10 +118,11 @@</div><div class='ctx'> 	RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)</div><div class='ctx'> </div><div class='ctx'> /* CPU port control reg */</div><div class='del'>-#define RTL8368RB_CPU_CTRL_REG		0x0061</div><div class='del'>-#define RTL8368RB_CPU_PORTS_MSK		0x00FF</div><div class='add'>+#define RTL8366RB_CPU_CTRL_REG		0x0061</div><div class='add'>+#define RTL8366RB_CPU_PORTS_MSK		0x00FF</div><div class='ctx'> /* Disables inserting custom tag length/type 0x8899 */</div><div class='del'>-#define RTL8368RB_CPU_NO_TAG		BIT(15)</div><div class='add'>+#define RTL8366RB_CPU_NO_TAG		BIT(15)</div><div class='add'>+#define RTL8366RB_CPU_TAG_SIZE		4</div><div class='ctx'> </div><div class='ctx'> #define RTL8366RB_SMAR0			0x0070 /* bits 0..15 */</div><div class='ctx'> #define RTL8366RB_SMAR1			0x0071 /* bits 16..31 */</div><div class='hunk'>@@ -912,10 +914,10 @@ static int rtl8366rb_setup(struct dsa_switch *ds)</div><div class='ctx'> </div><div class='ctx'> 	/* Enable CPU port with custom DSA tag 8899.</div><div class='ctx'> 	 *</div><div class='del'>-	 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers</div><div class='add'>+	 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register</div><div class='ctx'> 	 * the custom tag is turned off.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = regmap_update_bits(priv-&gt;map, RTL8368RB_CPU_CTRL_REG,</div><div class='add'>+	ret = regmap_update_bits(priv-&gt;map, RTL8366RB_CPU_CTRL_REG,</div><div class='ctx'> 				 0xFFFF,</div><div class='ctx'> 				 BIT(priv-&gt;cpu_port));</div><div class='ctx'> 	if (ret)</div><div class='hunk'>@@ -928,15 +930,19 @@ static int rtl8366rb_setup(struct dsa_switch *ds)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	/* Set maximum packet length to 1536 bytes */</div><div class='add'>+	/* Set default maximum packet length to 1536 bytes */</div><div class='ctx'> 	ret = regmap_update_bits(priv-&gt;map, RTL8366RB_SGCR,</div><div class='ctx'> 				 RTL8366RB_SGCR_MAX_LENGTH_MASK,</div><div class='ctx'> 				 RTL8366RB_SGCR_MAX_LENGTH_1536);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='del'>-	for (i = 0; i &lt; RTL8366RB_NUM_PORTS; i++)</div><div class='del'>-		/* layer 2 size, see rtl8366rb_change_mtu() */</div><div class='del'>-		rb-&gt;max_mtu[i] = 1532;</div><div class='add'>+	for (i = 0; i &lt; RTL8366RB_NUM_PORTS; i++) {</div><div class='add'>+		if (i == priv-&gt;cpu_port)</div><div class='add'>+			/* CPU port need to also accept the tag */</div><div class='add'>+			rb-&gt;max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;</div><div class='add'>+		else</div><div class='add'>+			rb-&gt;max_mtu[i] = ETH_DATA_LEN;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Disable learning for all ports */</div><div class='ctx'> 	ret = regmap_write(priv-&gt;map, RTL8366RB_PORT_LEARNDIS_CTRL,</div><div class='hunk'>@@ -1441,24 +1447,29 @@ static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)</div><div class='ctx'> 	/* Roof out the MTU for the entire switch to the greatest</div><div class='ctx'> 	 * common denominator: the biggest set for any one port will</div><div class='ctx'> 	 * be the biggest MTU for the switch.</div><div class='del'>-	 *</div><div class='del'>-	 * The first setting, 1522 bytes, is max IP packet 1500 bytes,</div><div class='del'>-	 * plus ethernet header, 1518 bytes, plus CPU tag, 4 bytes.</div><div class='del'>-	 * This function should consider the parameter an SDU, so the</div><div class='del'>-	 * MTU passed for this setting is 1518 bytes. The same logic</div><div class='del'>-	 * of subtracting the DSA tag of 4 bytes apply to the other</div><div class='del'>-	 * settings.</div><div class='ctx'> 	 */</div><div class='del'>-	max_mtu = 1518;</div><div class='add'>+	max_mtu = ETH_DATA_LEN;</div><div class='ctx'> 	for (i = 0; i &lt; RTL8366RB_NUM_PORTS; i++) {</div><div class='ctx'> 		if (rb-&gt;max_mtu[i] &gt; max_mtu)</div><div class='ctx'> 			max_mtu = rb-&gt;max_mtu[i];</div><div class='ctx'> 	}</div><div class='del'>-	if (max_mtu &lt;= 1518)</div><div class='add'>+</div><div class='add'>+	/* Translate to layer 2 size.</div><div class='add'>+	 * Add ethernet and (possible) VLAN headers, and checksum to the size.</div><div class='add'>+	 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.</div><div class='add'>+	 */</div><div class='add'>+	max_mtu += VLAN_ETH_HLEN;</div><div class='add'>+	max_mtu += ETH_FCS_LEN;</div><div class='add'>+</div><div class='add'>+	if (max_mtu &lt;= 1522)</div><div class='ctx'> 		len = RTL8366RB_SGCR_MAX_LENGTH_1522;</div><div class='del'>-	else if (max_mtu &gt; 1518 &amp;&amp; max_mtu &lt;= 1532)</div><div class='add'>+	else if (max_mtu &gt; 1522 &amp;&amp; max_mtu &lt;= 1536)</div><div class='add'>+		/* This will be the most common default if using VLAN and</div><div class='add'>+		 * CPU tagging on a port as both VLAN and CPU tag will</div><div class='add'>+		 * result in 1518 + 4 + 4 = 1526 bytes.</div><div class='add'>+		 */</div><div class='ctx'> 		len = RTL8366RB_SGCR_MAX_LENGTH_1536;</div><div class='del'>-	else if (max_mtu &gt; 1532 &amp;&amp; max_mtu &lt;= 1548)</div><div class='add'>+	else if (max_mtu &gt; 1536 &amp;&amp; max_mtu &lt;= 1552)</div><div class='ctx'> 		len = RTL8366RB_SGCR_MAX_LENGTH_1552;</div><div class='ctx'> 	else</div><div class='ctx'> 		len = RTL8366RB_SGCR_MAX_LENGTH_16000;</div><div class='hunk'>@@ -1470,10 +1481,12 @@ static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)</div><div class='ctx'> </div><div class='ctx'> static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)</div><div class='ctx'> {</div><div class='del'>-	/* The max MTU is 16000 bytes, so we subtract the CPU tag</div><div class='del'>-	 * and the max presented to the system is 15996 bytes.</div><div class='add'>+	/* The max MTU is 16000 bytes, so we subtract the ethernet</div><div class='add'>+	 * headers with VLAN and checksum and arrive at</div><div class='add'>+	 * 16000 - 18 - 4 = 15978. This does not include the CPU tag</div><div class='add'>+	 * since that is added to the requested MTU by the DSA framework.</div><div class='ctx'> 	 */</div><div class='del'>-	return 15996;</div><div class='add'>+	return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,</div><div class='head'>diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c<br/>index 74cee39d73df..6646f7fb0f90 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/sja1105/sja1105_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/sja1105/sja1105_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/sja1105/sja1105_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/sja1105/sja1105_main.c</a></div><div class='hunk'>@@ -21,6 +21,8 @@</div><div class='ctx'> #include &lt;linux/if_bridge.h&gt;</div><div class='ctx'> #include &lt;linux/if_ether.h&gt;</div><div class='ctx'> #include &lt;linux/dsa/8021q.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "sja1105.h"</div><div class='ctx'> #include "sja1105_tas.h"</div><div class='ctx'> </div><div class='hunk'>@@ -2138,7 +2140,6 @@ static void sja1105_bridge_leave(struct dsa_switch *ds, int port,</div><div class='ctx'> 	sja1105_bridge_member(ds, port, bridge, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define BYTES_PER_KBIT (1000LL / 8)</div><div class='ctx'> /* Port 0 (the uC port) does not have CBS shapers */</div><div class='ctx'> #define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/dsa/vitesse-vsc73xx-core.c b/drivers/net/dsa/vitesse-vsc73xx-core.c<br/>index e6f29e4e508c..ae70eac3be28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/dsa/vitesse-vsc73xx-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/dsa/vitesse-vsc73xx-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/dsa/vitesse-vsc73xx-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/dsa/vitesse-vsc73xx-core.c</a></div><div class='hunk'>@@ -949,7 +949,7 @@ static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 	indices[5] = ((val &gt;&gt; 26) &amp; 0x1f); /* TX counter 2 */</div><div class='ctx'> </div><div class='ctx'> 	/* The first counters is the RX octets */</div><div class='del'>-	ethtool_sprintf(&amp;buf, "RxEtherStatsOctets");</div><div class='add'>+	ethtool_puts(&amp;buf, "RxEtherStatsOctets");</div><div class='ctx'> </div><div class='ctx'> 	/* Each port supports recording 3 RX counters and 3 TX counters,</div><div class='ctx'> 	 * figure out what counters we use in this set-up and return the</div><div class='hunk'>@@ -959,15 +959,15 @@ static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 3; i++) {</div><div class='ctx'> 		cnt = vsc73xx_find_counter(vsc, indices[i], false);</div><div class='del'>-		ethtool_sprintf(&amp;buf, "%s", cnt ? cnt-&gt;name : "");</div><div class='add'>+		ethtool_puts(&amp;buf, cnt ? cnt-&gt;name : "");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* TX stats begins with the number of TX octets */</div><div class='del'>-	ethtool_sprintf(&amp;buf, "TxEtherStatsOctets");</div><div class='add'>+	ethtool_puts(&amp;buf, "TxEtherStatsOctets");</div><div class='ctx'> </div><div class='ctx'> 	for (i = 3; i &lt; 6; i++) {</div><div class='ctx'> 		cnt = vsc73xx_find_counter(vsc, indices[i], true);</div><div class='del'>-		ethtool_sprintf(&amp;buf, "%s", cnt ? cnt-&gt;name : "");</div><div class='add'>+		ethtool_puts(&amp;buf, cnt ? cnt-&gt;name : "");</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1135,6 +1135,8 @@ static int vsc73xx_gpio_probe(struct vsc73xx *vsc)</div><div class='ctx'> </div><div class='ctx'> 	vsc-&gt;gc.label = devm_kasprintf(vsc-&gt;dev, GFP_KERNEL, "VSC%04x",</div><div class='ctx'> 				       vsc-&gt;chipid);</div><div class='add'>+	if (!vsc-&gt;gc.label)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	vsc-&gt;gc.ngpio = 4;</div><div class='ctx'> 	vsc-&gt;gc.owner = THIS_MODULE;</div><div class='ctx'> 	vsc-&gt;gc.parent = vsc-&gt;dev;</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/Makefile b/drivers/net/ethernet/amazon/ena/Makefile<br/>index f1f752a8f7bb..6ab615365172 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amazon/ena/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/Makefile</a></div><div class='hunk'>@@ -5,4 +5,4 @@</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_ENA_ETHERNET) += ena.o</div><div class='ctx'> </div><div class='del'>-ena-y := ena_netdev.o ena_com.o ena_eth_com.o ena_ethtool.o</div><div class='add'>+ena-y := ena_netdev.o ena_com.o ena_eth_com.o ena_ethtool.o ena_xdp.o</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_eth_com.c b/drivers/net/ethernet/amazon/ena/ena_eth_com.c<br/>index 3d6f0a466a9e..f9f886289b97 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_eth_com.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amazon/ena/ena_eth_com.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_eth_com.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_eth_com.c</a></div><div class='hunk'>@@ -328,9 +328,6 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,</div><div class='ctx'> 	 * compare it to the stored version, just create the meta</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (io_sq-&gt;disable_meta_caching) {</div><div class='del'>-		if (unlikely(!ena_tx_ctx-&gt;meta_valid))</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 		*have_meta = true;</div><div class='ctx'> 		return ena_com_create_meta(io_sq, ena_meta);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_ethtool.c b/drivers/net/ethernet/amazon/ena/ena_ethtool.c<br/>index d671df4b76bc..0cb6cc1cef56 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amazon/ena/ena_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_ethtool.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "ena_netdev.h"</div><div class='add'>+#include "ena_xdp.h"</div><div class='ctx'> </div><div class='ctx'> struct ena_stats {</div><div class='ctx'> 	char name[ETH_GSTRING_LEN];</div><div class='hunk'>@@ -262,17 +263,14 @@ static void ena_queue_strings(struct ena_adapter *adapter, u8 **data)</div><div class='ctx'> 					ena_stats-&gt;name);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (!is_xdp) {</div><div class='del'>-			/* RX stats, in XDP there isn't a RX queue</div><div class='del'>-			 * counterpart</div><div class='del'>-			 */</div><div class='del'>-			for (j = 0; j &lt; ENA_STATS_ARRAY_RX; j++) {</div><div class='del'>-				ena_stats = &amp;ena_stats_rx_strings[j];</div><div class='add'>+		/* In XDP there isn't an RX queue counterpart */</div><div class='add'>+		if (is_xdp)</div><div class='add'>+			continue;</div><div class='ctx'> </div><div class='del'>-				ethtool_sprintf(data,</div><div class='del'>-						"queue_%u_rx_%s", i,</div><div class='del'>-						ena_stats-&gt;name);</div><div class='del'>-			}</div><div class='add'>+		for (j = 0; j &lt; ENA_STATS_ARRAY_RX; j++) {</div><div class='add'>+			ena_stats = &amp;ena_stats_rx_strings[j];</div><div class='add'>+</div><div class='add'>+			ethtool_sprintf(data, "queue_%u_rx_%s", i, ena_stats-&gt;name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -299,13 +297,13 @@ static void ena_get_strings(struct ena_adapter *adapter,</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ENA_STATS_ARRAY_GLOBAL; i++) {</div><div class='ctx'> 		ena_stats = &amp;ena_stats_global_strings[i];</div><div class='del'>-		ethtool_sprintf(&amp;data, ena_stats-&gt;name);</div><div class='add'>+		ethtool_puts(&amp;data, ena_stats-&gt;name);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (eni_stats_needed) {</div><div class='ctx'> 		for (i = 0; i &lt; ENA_STATS_ARRAY_ENI(adapter); i++) {</div><div class='ctx'> 			ena_stats = &amp;ena_stats_eni_strings[i];</div><div class='del'>-			ethtool_sprintf(&amp;data, ena_stats-&gt;name);</div><div class='add'>+			ethtool_puts(&amp;data, ena_stats-&gt;name);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -802,15 +800,15 @@ static int ena_indirection_table_get(struct ena_adapter *adapter, u32 *indir)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			u8 *hfunc)</div><div class='add'>+static int ena_get_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	enum ena_admin_hash_functions ena_func;</div><div class='ctx'> 	u8 func;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	rc = ena_indirection_table_get(adapter, indir);</div><div class='add'>+	rc = ena_indirection_table_get(adapter, rxfh-&gt;indir);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -825,7 +823,7 @@ static int ena_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 		return rc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = ena_com_get_hash_key(adapter-&gt;ena_dev, key);</div><div class='add'>+	rc = ena_com_get_hash_key(adapter-&gt;ena_dev, rxfh-&gt;key);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='hunk'>@@ -842,27 +840,27 @@ static int ena_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = func;</div><div class='add'>+	rxfh-&gt;hfunc = func;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			const u8 *key, const u8 hfunc)</div><div class='add'>+static int ena_set_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	struct ena_com_dev *ena_dev = adapter-&gt;ena_dev;</div><div class='ctx'> 	enum ena_admin_hash_functions func = 0;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='del'>-		rc = ena_indirection_table_set(adapter, indir);</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='add'>+		rc = ena_indirection_table_set(adapter, rxfh-&gt;indir);</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			return rc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	switch (hfunc) {</div><div class='add'>+	switch (rxfh-&gt;hfunc) {</div><div class='ctx'> 	case ETH_RSS_HASH_NO_CHANGE:</div><div class='ctx'> 		func = ena_com_get_current_hash_function(ena_dev);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -874,12 +872,12 @@ static int ena_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		netif_err(adapter, drv, netdev, "Unsupported hfunc %d\n",</div><div class='del'>-			  hfunc);</div><div class='add'>+			  rxfh-&gt;hfunc);</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key || func) {</div><div class='del'>-		rc = ena_com_fill_hash_function(ena_dev, func, key,</div><div class='add'>+	if (rxfh-&gt;key || func) {</div><div class='add'>+		rc = ena_com_fill_hash_function(ena_dev, func, rxfh-&gt;key,</div><div class='ctx'> 						ENA_HASH_KEY_SIZE,</div><div class='ctx'> 						0xFFFFFFFF);</div><div class='ctx'> 		if (unlikely(rc)) {</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c<br/>index b5bca4814830..1c0a7828d397 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_netdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amazon/ena/ena_netdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_netdev.c</a></div><div class='hunk'>@@ -19,8 +19,8 @@</div><div class='ctx'> #include &lt;net/ip.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "ena_netdev.h"</div><div class='del'>-#include &lt;linux/bpf_trace.h&gt;</div><div class='ctx'> #include "ena_pci_id_tbl.h"</div><div class='add'>+#include "ena_xdp.h"</div><div class='ctx'> </div><div class='ctx'> MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");</div><div class='ctx'> MODULE_DESCRIPTION(DEVICE_NAME);</div><div class='hunk'>@@ -45,51 +45,6 @@ static void check_for_admin_com_state(struct ena_adapter *adapter);</div><div class='ctx'> static void ena_destroy_device(struct ena_adapter *adapter, bool graceful);</div><div class='ctx'> static int ena_restore_device(struct ena_adapter *adapter);</div><div class='ctx'> </div><div class='del'>-static void ena_init_io_rings(struct ena_adapter *adapter,</div><div class='del'>-			      int first_index, int count);</div><div class='del'>-static void ena_init_napi_in_range(struct ena_adapter *adapter, int first_index,</div><div class='del'>-				   int count);</div><div class='del'>-static void ena_del_napi_in_range(struct ena_adapter *adapter, int first_index,</div><div class='del'>-				  int count);</div><div class='del'>-static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid);</div><div class='del'>-static int ena_setup_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='del'>-					   int first_index,</div><div class='del'>-					   int count);</div><div class='del'>-static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid);</div><div class='del'>-static void ena_free_tx_resources(struct ena_adapter *adapter, int qid);</div><div class='del'>-static int ena_clean_xdp_irq(struct ena_ring *xdp_ring, u32 budget);</div><div class='del'>-static void ena_destroy_all_tx_queues(struct ena_adapter *adapter);</div><div class='del'>-static void ena_free_all_io_tx_resources(struct ena_adapter *adapter);</div><div class='del'>-static void ena_napi_disable_in_range(struct ena_adapter *adapter,</div><div class='del'>-				      int first_index, int count);</div><div class='del'>-static void ena_napi_enable_in_range(struct ena_adapter *adapter,</div><div class='del'>-				     int first_index, int count);</div><div class='del'>-static int ena_up(struct ena_adapter *adapter);</div><div class='del'>-static void ena_down(struct ena_adapter *adapter);</div><div class='del'>-static void ena_unmask_interrupt(struct ena_ring *tx_ring,</div><div class='del'>-				 struct ena_ring *rx_ring);</div><div class='del'>-static void ena_update_ring_numa_node(struct ena_ring *tx_ring,</div><div class='del'>-				      struct ena_ring *rx_ring);</div><div class='del'>-static void ena_unmap_tx_buff(struct ena_ring *tx_ring,</div><div class='del'>-			      struct ena_tx_buffer *tx_info);</div><div class='del'>-static int ena_create_io_tx_queues_in_range(struct ena_adapter *adapter,</div><div class='del'>-					    int first_index, int count);</div><div class='del'>-</div><div class='del'>-/* Increase a stat by cnt while holding syncp seqlock on 32bit machines */</div><div class='del'>-static void ena_increase_stat(u64 *statp, u64 cnt,</div><div class='del'>-			      struct u64_stats_sync *syncp)</div><div class='del'>-{</div><div class='del'>-	u64_stats_update_begin(syncp);</div><div class='del'>-	(*statp) += cnt;</div><div class='del'>-	u64_stats_update_end(syncp);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ena_ring_tx_doorbell(struct ena_ring *tx_ring)</div><div class='del'>-{</div><div class='del'>-	ena_com_write_sq_doorbell(tx_ring-&gt;ena_com_io_sq);</div><div class='del'>-	ena_increase_stat(&amp;tx_ring-&gt;tx_stats.doorbells, 1, &amp;tx_ring-&gt;syncp);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void ena_tx_timeout(struct net_device *dev, unsigned int txqueue)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_adapter *adapter = netdev_priv(dev);</div><div class='hunk'>@@ -133,19 +88,18 @@ static int ena_change_mtu(struct net_device *dev, int new_mtu)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_xmit_common(struct net_device *dev,</div><div class='del'>-			   struct ena_ring *ring,</div><div class='del'>-			   struct ena_tx_buffer *tx_info,</div><div class='del'>-			   struct ena_com_tx_ctx *ena_tx_ctx,</div><div class='del'>-			   u16 next_to_use,</div><div class='del'>-			   u32 bytes)</div><div class='add'>+int ena_xmit_common(struct ena_adapter *adapter,</div><div class='add'>+		    struct ena_ring *ring,</div><div class='add'>+		    struct ena_tx_buffer *tx_info,</div><div class='add'>+		    struct ena_com_tx_ctx *ena_tx_ctx,</div><div class='add'>+		    u16 next_to_use,</div><div class='add'>+		    u32 bytes)</div><div class='ctx'> {</div><div class='del'>-	struct ena_adapter *adapter = netdev_priv(dev);</div><div class='ctx'> 	int rc, nb_hw_desc;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(ena_com_is_doorbell_needed(ring-&gt;ena_com_io_sq,</div><div class='ctx'> 						ena_tx_ctx))) {</div><div class='del'>-		netif_dbg(adapter, tx_queued, dev,</div><div class='add'>+		netif_dbg(adapter, tx_queued, adapter-&gt;netdev,</div><div class='ctx'> 			  "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",</div><div class='ctx'> 			  ring-&gt;qid);</div><div class='ctx'> 		ena_ring_tx_doorbell(ring);</div><div class='hunk'>@@ -160,7 +114,7 @@ static int ena_xmit_common(struct net_device *dev,</div><div class='ctx'> 	 * ena_com_prepare_tx() are fatal and therefore require a device reset.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (unlikely(rc)) {</div><div class='del'>-		netif_err(adapter, tx_queued, dev,</div><div class='add'>+		netif_err(adapter, tx_queued, adapter-&gt;netdev,</div><div class='ctx'> 			  "Failed to prepare tx bufs\n");</div><div class='ctx'> 		ena_increase_stat(&amp;ring-&gt;tx_stats.prepare_ctx_err, 1,</div><div class='ctx'> 				  &amp;ring-&gt;syncp);</div><div class='hunk'>@@ -176,6 +130,7 @@ static int ena_xmit_common(struct net_device *dev,</div><div class='ctx'> 	u64_stats_update_end(&amp;ring-&gt;syncp);</div><div class='ctx'> </div><div class='ctx'> 	tx_info-&gt;tx_descs = nb_hw_desc;</div><div class='add'>+	tx_info-&gt;total_tx_size = bytes;</div><div class='ctx'> 	tx_info-&gt;last_jiffies = jiffies;</div><div class='ctx'> 	tx_info-&gt;print_once = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -184,468 +139,6 @@ static int ena_xmit_common(struct net_device *dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* This is the XDP napi callback. XDP queues use a separate napi callback</div><div class='del'>- * than Rx/Tx queues.</div><div class='del'>- */</div><div class='del'>-static int ena_xdp_io_poll(struct napi_struct *napi, int budget)</div><div class='del'>-{</div><div class='del'>-	struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);</div><div class='del'>-	u32 xdp_work_done, xdp_budget;</div><div class='del'>-	struct ena_ring *xdp_ring;</div><div class='del'>-	int napi_comp_call = 0;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	xdp_ring = ena_napi-&gt;xdp_ring;</div><div class='del'>-</div><div class='del'>-	xdp_budget = budget;</div><div class='del'>-</div><div class='del'>-	if (!test_bit(ENA_FLAG_DEV_UP, &amp;xdp_ring-&gt;adapter-&gt;flags) ||</div><div class='del'>-	    test_bit(ENA_FLAG_TRIGGER_RESET, &amp;xdp_ring-&gt;adapter-&gt;flags)) {</div><div class='del'>-		napi_complete_done(napi, 0);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	xdp_work_done = ena_clean_xdp_irq(xdp_ring, xdp_budget);</div><div class='del'>-</div><div class='del'>-	/* If the device is about to reset or down, avoid unmask</div><div class='del'>-	 * the interrupt and return 0 so NAPI won't reschedule</div><div class='del'>-	 */</div><div class='del'>-	if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &amp;xdp_ring-&gt;adapter-&gt;flags))) {</div><div class='del'>-		napi_complete_done(napi, 0);</div><div class='del'>-		ret = 0;</div><div class='del'>-	} else if (xdp_budget &gt; xdp_work_done) {</div><div class='del'>-		napi_comp_call = 1;</div><div class='del'>-		if (napi_complete_done(napi, xdp_work_done))</div><div class='del'>-			ena_unmask_interrupt(xdp_ring, NULL);</div><div class='del'>-		ena_update_ring_numa_node(xdp_ring, NULL);</div><div class='del'>-		ret = xdp_work_done;</div><div class='del'>-	} else {</div><div class='del'>-		ret = xdp_budget;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	u64_stats_update_begin(&amp;xdp_ring-&gt;syncp);</div><div class='del'>-	xdp_ring-&gt;tx_stats.napi_comp += napi_comp_call;</div><div class='del'>-	xdp_ring-&gt;tx_stats.tx_poll++;</div><div class='del'>-	u64_stats_update_end(&amp;xdp_ring-&gt;syncp);</div><div class='del'>-	xdp_ring-&gt;tx_stats.last_napi_jiffies = jiffies;</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_xdp_tx_map_frame(struct ena_ring *xdp_ring,</div><div class='del'>-				struct ena_tx_buffer *tx_info,</div><div class='del'>-				struct xdp_frame *xdpf,</div><div class='del'>-				struct ena_com_tx_ctx *ena_tx_ctx)</div><div class='del'>-{</div><div class='del'>-	struct ena_adapter *adapter = xdp_ring-&gt;adapter;</div><div class='del'>-	struct ena_com_buf *ena_buf;</div><div class='del'>-	int push_len = 0;</div><div class='del'>-	dma_addr_t dma;</div><div class='del'>-	void *data;</div><div class='del'>-	u32 size;</div><div class='del'>-</div><div class='del'>-	tx_info-&gt;xdpf = xdpf;</div><div class='del'>-	data = tx_info-&gt;xdpf-&gt;data;</div><div class='del'>-	size = tx_info-&gt;xdpf-&gt;len;</div><div class='del'>-</div><div class='del'>-	if (xdp_ring-&gt;tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {</div><div class='del'>-		/* Designate part of the packet for LLQ */</div><div class='del'>-		push_len = min_t(u32, size, xdp_ring-&gt;tx_max_header_size);</div><div class='del'>-</div><div class='del'>-		ena_tx_ctx-&gt;push_header = data;</div><div class='del'>-</div><div class='del'>-		size -= push_len;</div><div class='del'>-		data += push_len;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ena_tx_ctx-&gt;header_len = push_len;</div><div class='del'>-</div><div class='del'>-	if (size &gt; 0) {</div><div class='del'>-		dma = dma_map_single(xdp_ring-&gt;dev,</div><div class='del'>-				     data,</div><div class='del'>-				     size,</div><div class='del'>-				     DMA_TO_DEVICE);</div><div class='del'>-		if (unlikely(dma_mapping_error(xdp_ring-&gt;dev, dma)))</div><div class='del'>-			goto error_report_dma_error;</div><div class='del'>-</div><div class='del'>-		tx_info-&gt;map_linear_data = 0;</div><div class='del'>-</div><div class='del'>-		ena_buf = tx_info-&gt;bufs;</div><div class='del'>-		ena_buf-&gt;paddr = dma;</div><div class='del'>-		ena_buf-&gt;len = size;</div><div class='del'>-</div><div class='del'>-		ena_tx_ctx-&gt;ena_bufs = ena_buf;</div><div class='del'>-		ena_tx_ctx-&gt;num_bufs = tx_info-&gt;num_of_bufs = 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-error_report_dma_error:</div><div class='del'>-	ena_increase_stat(&amp;xdp_ring-&gt;tx_stats.dma_mapping_err, 1,</div><div class='del'>-			  &amp;xdp_ring-&gt;syncp);</div><div class='del'>-	netif_warn(adapter, tx_queued, adapter-&gt;netdev, "Failed to map xdp buff\n");</div><div class='del'>-</div><div class='del'>-	return -EINVAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_xdp_xmit_frame(struct ena_ring *xdp_ring,</div><div class='del'>-			      struct net_device *dev,</div><div class='del'>-			      struct xdp_frame *xdpf,</div><div class='del'>-			      int flags)</div><div class='del'>-{</div><div class='del'>-	struct ena_com_tx_ctx ena_tx_ctx = {};</div><div class='del'>-	struct ena_tx_buffer *tx_info;</div><div class='del'>-	u16 next_to_use, req_id;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	next_to_use = xdp_ring-&gt;next_to_use;</div><div class='del'>-	req_id = xdp_ring-&gt;free_ids[next_to_use];</div><div class='del'>-	tx_info = &amp;xdp_ring-&gt;tx_buffer_info[req_id];</div><div class='del'>-	tx_info-&gt;num_of_bufs = 0;</div><div class='del'>-</div><div class='del'>-	rc = ena_xdp_tx_map_frame(xdp_ring, tx_info, xdpf, &amp;ena_tx_ctx);</div><div class='del'>-	if (unlikely(rc))</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	ena_tx_ctx.req_id = req_id;</div><div class='del'>-</div><div class='del'>-	rc = ena_xmit_common(dev,</div><div class='del'>-			     xdp_ring,</div><div class='del'>-			     tx_info,</div><div class='del'>-			     &amp;ena_tx_ctx,</div><div class='del'>-			     next_to_use,</div><div class='del'>-			     xdpf-&gt;len);</div><div class='del'>-	if (rc)</div><div class='del'>-		goto error_unmap_dma;</div><div class='del'>-</div><div class='del'>-	/* trigger the dma engine. ena_ring_tx_doorbell()</div><div class='del'>-	 * calls a memory barrier inside it.</div><div class='del'>-	 */</div><div class='del'>-	if (flags &amp; XDP_XMIT_FLUSH)</div><div class='del'>-		ena_ring_tx_doorbell(xdp_ring);</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='del'>-</div><div class='del'>-error_unmap_dma:</div><div class='del'>-	ena_unmap_tx_buff(xdp_ring, tx_info);</div><div class='del'>-	tx_info-&gt;xdpf = NULL;</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_xdp_xmit(struct net_device *dev, int n,</div><div class='del'>-			struct xdp_frame **frames, u32 flags)</div><div class='del'>-{</div><div class='del'>-	struct ena_adapter *adapter = netdev_priv(dev);</div><div class='del'>-	struct ena_ring *xdp_ring;</div><div class='del'>-	int qid, i, nxmit = 0;</div><div class='del'>-</div><div class='del'>-	if (unlikely(flags &amp; ~XDP_XMIT_FLAGS_MASK))</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if (!test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags))</div><div class='del'>-		return -ENETDOWN;</div><div class='del'>-</div><div class='del'>-	/* We assume that all rings have the same XDP program */</div><div class='del'>-	if (!READ_ONCE(adapter-&gt;rx_ring-&gt;xdp_bpf_prog))</div><div class='del'>-		return -ENXIO;</div><div class='del'>-</div><div class='del'>-	qid = smp_processor_id() % adapter-&gt;xdp_num_queues;</div><div class='del'>-	qid += adapter-&gt;xdp_first_ring;</div><div class='del'>-	xdp_ring = &amp;adapter-&gt;tx_ring[qid];</div><div class='del'>-</div><div class='del'>-	/* Other CPU ids might try to send thorugh this queue */</div><div class='del'>-	spin_lock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; n; i++) {</div><div class='del'>-		if (ena_xdp_xmit_frame(xdp_ring, dev, frames[i], 0))</div><div class='del'>-			break;</div><div class='del'>-		nxmit++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Ring doorbell to make device aware of the packets */</div><div class='del'>-	if (flags &amp; XDP_XMIT_FLUSH)</div><div class='del'>-		ena_ring_tx_doorbell(xdp_ring);</div><div class='del'>-</div><div class='del'>-	spin_unlock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='del'>-</div><div class='del'>-	/* Return number of packets sent */</div><div class='del'>-	return nxmit;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_xdp_execute(struct ena_ring *rx_ring, struct xdp_buff *xdp)</div><div class='del'>-{</div><div class='del'>-	u32 verdict = ENA_XDP_PASS;</div><div class='del'>-	struct bpf_prog *xdp_prog;</div><div class='del'>-	struct ena_ring *xdp_ring;</div><div class='del'>-	struct xdp_frame *xdpf;</div><div class='del'>-	u64 *xdp_stat;</div><div class='del'>-</div><div class='del'>-	xdp_prog = READ_ONCE(rx_ring-&gt;xdp_bpf_prog);</div><div class='del'>-</div><div class='del'>-	if (!xdp_prog)</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	verdict = bpf_prog_run_xdp(xdp_prog, xdp);</div><div class='del'>-</div><div class='del'>-	switch (verdict) {</div><div class='del'>-	case XDP_TX:</div><div class='del'>-		xdpf = xdp_convert_buff_to_frame(xdp);</div><div class='del'>-		if (unlikely(!xdpf)) {</div><div class='del'>-			trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='del'>-			xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='del'>-			verdict = ENA_XDP_DROP;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Find xmit queue */</div><div class='del'>-		xdp_ring = rx_ring-&gt;xdp_ring;</div><div class='del'>-</div><div class='del'>-		/* The XDP queues are shared between XDP_TX and XDP_REDIRECT */</div><div class='del'>-		spin_lock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='del'>-</div><div class='del'>-		if (ena_xdp_xmit_frame(xdp_ring, rx_ring-&gt;netdev, xdpf,</div><div class='del'>-				       XDP_XMIT_FLUSH))</div><div class='del'>-			xdp_return_frame(xdpf);</div><div class='del'>-</div><div class='del'>-		spin_unlock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_tx;</div><div class='del'>-		verdict = ENA_XDP_TX;</div><div class='del'>-		break;</div><div class='del'>-	case XDP_REDIRECT:</div><div class='del'>-		if (likely(!xdp_do_redirect(rx_ring-&gt;netdev, xdp, xdp_prog))) {</div><div class='del'>-			xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_redirect;</div><div class='del'>-			verdict = ENA_XDP_REDIRECT;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-		trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='del'>-		verdict = ENA_XDP_DROP;</div><div class='del'>-		break;</div><div class='del'>-	case XDP_ABORTED:</div><div class='del'>-		trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='del'>-		verdict = ENA_XDP_DROP;</div><div class='del'>-		break;</div><div class='del'>-	case XDP_DROP:</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_drop;</div><div class='del'>-		verdict = ENA_XDP_DROP;</div><div class='del'>-		break;</div><div class='del'>-	case XDP_PASS:</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_pass;</div><div class='del'>-		verdict = ENA_XDP_PASS;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		bpf_warn_invalid_xdp_action(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='del'>-		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_invalid;</div><div class='del'>-		verdict = ENA_XDP_DROP;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ena_increase_stat(xdp_stat, 1, &amp;rx_ring-&gt;syncp);</div><div class='del'>-out:</div><div class='del'>-	return verdict;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ena_init_all_xdp_queues(struct ena_adapter *adapter)</div><div class='del'>-{</div><div class='del'>-	adapter-&gt;xdp_first_ring = adapter-&gt;num_io_queues;</div><div class='del'>-	adapter-&gt;xdp_num_queues = adapter-&gt;num_io_queues;</div><div class='del'>-</div><div class='del'>-	ena_init_io_rings(adapter,</div><div class='del'>-			  adapter-&gt;xdp_first_ring,</div><div class='del'>-			  adapter-&gt;xdp_num_queues);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_setup_and_create_all_xdp_queues(struct ena_adapter *adapter)</div><div class='del'>-{</div><div class='del'>-	int rc = 0;</div><div class='del'>-</div><div class='del'>-	rc = ena_setup_tx_resources_in_range(adapter, adapter-&gt;xdp_first_ring,</div><div class='del'>-					     adapter-&gt;xdp_num_queues);</div><div class='del'>-	if (rc)</div><div class='del'>-		goto setup_err;</div><div class='del'>-</div><div class='del'>-	rc = ena_create_io_tx_queues_in_range(adapter,</div><div class='del'>-					      adapter-&gt;xdp_first_ring,</div><div class='del'>-					      adapter-&gt;xdp_num_queues);</div><div class='del'>-	if (rc)</div><div class='del'>-		goto create_err;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-create_err:</div><div class='del'>-	ena_free_all_io_tx_resources(adapter);</div><div class='del'>-setup_err:</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Provides a way for both kernel and bpf-prog to know</div><div class='del'>- * more about the RX-queue a given XDP frame arrived on.</div><div class='del'>- */</div><div class='del'>-static int ena_xdp_register_rxq_info(struct ena_ring *rx_ring)</div><div class='del'>-{</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	rc = xdp_rxq_info_reg(&amp;rx_ring-&gt;xdp_rxq, rx_ring-&gt;netdev, rx_ring-&gt;qid, 0);</div><div class='del'>-</div><div class='del'>-	if (rc) {</div><div class='del'>-		netif_err(rx_ring-&gt;adapter, ifup, rx_ring-&gt;netdev,</div><div class='del'>-			  "Failed to register xdp rx queue info. RX queue num %d rc: %d\n",</div><div class='del'>-			  rx_ring-&gt;qid, rc);</div><div class='del'>-		goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rc = xdp_rxq_info_reg_mem_model(&amp;rx_ring-&gt;xdp_rxq, MEM_TYPE_PAGE_SHARED,</div><div class='del'>-					NULL);</div><div class='del'>-</div><div class='del'>-	if (rc) {</div><div class='del'>-		netif_err(rx_ring-&gt;adapter, ifup, rx_ring-&gt;netdev,</div><div class='del'>-			  "Failed to register xdp rx queue info memory model. RX queue num %d rc: %d\n",</div><div class='del'>-			  rx_ring-&gt;qid, rc);</div><div class='del'>-		xdp_rxq_info_unreg(&amp;rx_ring-&gt;xdp_rxq);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-err:</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ena_xdp_unregister_rxq_info(struct ena_ring *rx_ring)</div><div class='del'>-{</div><div class='del'>-	xdp_rxq_info_unreg_mem_model(&amp;rx_ring-&gt;xdp_rxq);</div><div class='del'>-	xdp_rxq_info_unreg(&amp;rx_ring-&gt;xdp_rxq);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ena_xdp_exchange_program_rx_in_range(struct ena_adapter *adapter,</div><div class='del'>-						 struct bpf_prog *prog,</div><div class='del'>-						 int first, int count)</div><div class='del'>-{</div><div class='del'>-	struct bpf_prog *old_bpf_prog;</div><div class='del'>-	struct ena_ring *rx_ring;</div><div class='del'>-	int i = 0;</div><div class='del'>-</div><div class='del'>-	for (i = first; i &lt; count; i++) {</div><div class='del'>-		rx_ring = &amp;adapter-&gt;rx_ring[i];</div><div class='del'>-		old_bpf_prog = xchg(&amp;rx_ring-&gt;xdp_bpf_prog, prog);</div><div class='del'>-</div><div class='del'>-		if (!old_bpf_prog &amp;&amp; prog) {</div><div class='del'>-			ena_xdp_register_rxq_info(rx_ring);</div><div class='del'>-			rx_ring-&gt;rx_headroom = XDP_PACKET_HEADROOM;</div><div class='del'>-		} else if (old_bpf_prog &amp;&amp; !prog) {</div><div class='del'>-			ena_xdp_unregister_rxq_info(rx_ring);</div><div class='del'>-			rx_ring-&gt;rx_headroom = NET_SKB_PAD;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ena_xdp_exchange_program(struct ena_adapter *adapter,</div><div class='del'>-				     struct bpf_prog *prog)</div><div class='del'>-{</div><div class='del'>-	struct bpf_prog *old_bpf_prog = xchg(&amp;adapter-&gt;xdp_bpf_prog, prog);</div><div class='del'>-</div><div class='del'>-	ena_xdp_exchange_program_rx_in_range(adapter,</div><div class='del'>-					     prog,</div><div class='del'>-					     0,</div><div class='del'>-					     adapter-&gt;num_io_queues);</div><div class='del'>-</div><div class='del'>-	if (old_bpf_prog)</div><div class='del'>-		bpf_prog_put(old_bpf_prog);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_destroy_and_free_all_xdp_queues(struct ena_adapter *adapter)</div><div class='del'>-{</div><div class='del'>-	bool was_up;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	was_up = test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags);</div><div class='del'>-</div><div class='del'>-	if (was_up)</div><div class='del'>-		ena_down(adapter);</div><div class='del'>-</div><div class='del'>-	adapter-&gt;xdp_first_ring = 0;</div><div class='del'>-	adapter-&gt;xdp_num_queues = 0;</div><div class='del'>-	ena_xdp_exchange_program(adapter, NULL);</div><div class='del'>-	if (was_up) {</div><div class='del'>-		rc = ena_up(adapter);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int ena_xdp_set(struct net_device *netdev, struct netdev_bpf *bpf)</div><div class='del'>-{</div><div class='del'>-	struct ena_adapter *adapter = netdev_priv(netdev);</div><div class='del'>-	struct bpf_prog *prog = bpf-&gt;prog;</div><div class='del'>-	struct bpf_prog *old_bpf_prog;</div><div class='del'>-	int rc, prev_mtu;</div><div class='del'>-	bool is_up;</div><div class='del'>-</div><div class='del'>-	is_up = test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags);</div><div class='del'>-	rc = ena_xdp_allowed(adapter);</div><div class='del'>-	if (rc == ENA_XDP_ALLOWED) {</div><div class='del'>-		old_bpf_prog = adapter-&gt;xdp_bpf_prog;</div><div class='del'>-		if (prog) {</div><div class='del'>-			if (!is_up) {</div><div class='del'>-				ena_init_all_xdp_queues(adapter);</div><div class='del'>-			} else if (!old_bpf_prog) {</div><div class='del'>-				ena_down(adapter);</div><div class='del'>-				ena_init_all_xdp_queues(adapter);</div><div class='del'>-			}</div><div class='del'>-			ena_xdp_exchange_program(adapter, prog);</div><div class='del'>-</div><div class='del'>-			if (is_up &amp;&amp; !old_bpf_prog) {</div><div class='del'>-				rc = ena_up(adapter);</div><div class='del'>-				if (rc)</div><div class='del'>-					return rc;</div><div class='del'>-			}</div><div class='del'>-			xdp_features_set_redirect_target(netdev, false);</div><div class='del'>-		} else if (old_bpf_prog) {</div><div class='del'>-			xdp_features_clear_redirect_target(netdev);</div><div class='del'>-			rc = ena_destroy_and_free_all_xdp_queues(adapter);</div><div class='del'>-			if (rc)</div><div class='del'>-				return rc;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		prev_mtu = netdev-&gt;max_mtu;</div><div class='del'>-		netdev-&gt;max_mtu = prog ? ENA_XDP_MAX_MTU : adapter-&gt;max_mtu;</div><div class='del'>-</div><div class='del'>-		if (!old_bpf_prog)</div><div class='del'>-			netif_info(adapter, drv, adapter-&gt;netdev,</div><div class='del'>-				   "XDP program is set, changing the max_mtu from %d to %d",</div><div class='del'>-				   prev_mtu, netdev-&gt;max_mtu);</div><div class='del'>-</div><div class='del'>-	} else if (rc == ENA_XDP_CURRENT_MTU_TOO_LARGE) {</div><div class='del'>-		netif_err(adapter, drv, adapter-&gt;netdev,</div><div class='del'>-			  "Failed to set xdp program, the current MTU (%d) is larger than the maximum allowed MTU (%lu) while xdp is on",</div><div class='del'>-			  netdev-&gt;mtu, ENA_XDP_MAX_MTU);</div><div class='del'>-		NL_SET_ERR_MSG_MOD(bpf-&gt;extack,</div><div class='del'>-				   "Failed to set xdp program, the current MTU is larger than the maximum allowed MTU. Check the dmesg for more info");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	} else if (rc == ENA_XDP_NO_ENOUGH_QUEUES) {</div><div class='del'>-		netif_err(adapter, drv, adapter-&gt;netdev,</div><div class='del'>-			  "Failed to set xdp program, the Rx/Tx channel count should be at most half of the maximum allowed channel count. The current queue count (%d), the maximal queue count (%d)\n",</div><div class='del'>-			  adapter-&gt;num_io_queues, adapter-&gt;max_num_io_queues);</div><div class='del'>-		NL_SET_ERR_MSG_MOD(bpf-&gt;extack,</div><div class='del'>-				   "Failed to set xdp program, there is no enough space for allocating XDP queues, Check the dmesg for more info");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* This is the main xdp callback, it's used by the kernel to set/unset the xdp</div><div class='del'>- * program as well as to query the current xdp program id.</div><div class='del'>- */</div><div class='del'>-static int ena_xdp(struct net_device *netdev, struct netdev_bpf *bpf)</div><div class='del'>-{</div><div class='del'>-	switch (bpf-&gt;command) {</div><div class='del'>-	case XDP_SETUP_PROG:</div><div class='del'>-		return ena_xdp_set(netdev, bpf);</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> #ifdef CONFIG_RFS_ACCEL</div><div class='hunk'>@@ -687,8 +180,8 @@ static void ena_init_io_rings_common(struct ena_adapter *adapter,</div><div class='ctx'> 	u64_stats_init(&amp;ring-&gt;syncp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_init_io_rings(struct ena_adapter *adapter,</div><div class='del'>-			      int first_index, int count)</div><div class='add'>+void ena_init_io_rings(struct ena_adapter *adapter,</div><div class='add'>+		       int first_index, int count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_com_dev *ena_dev;</div><div class='ctx'> 	struct ena_ring *txr, *rxr;</div><div class='hunk'>@@ -819,9 +312,8 @@ static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)</div><div class='ctx'> 	tx_ring-&gt;push_buf_intermediate_buf = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_setup_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='del'>-					   int first_index,</div><div class='del'>-					   int count)</div><div class='add'>+int ena_setup_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='add'>+				    int first_index, int count)</div><div class='ctx'> {</div><div class='ctx'> 	int i, rc = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -844,8 +336,8 @@ err_setup_tx:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='del'>-						  int first_index, int count)</div><div class='add'>+void ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='add'>+					   int first_index, int count)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -858,7 +350,7 @@ static void ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='ctx'>  *</div><div class='ctx'>  * Free all transmit software resources</div><div class='ctx'>  */</div><div class='del'>-static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)</div><div class='add'>+void ena_free_all_io_tx_resources(struct ena_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> 	ena_free_all_io_tx_resources_in_range(adapter,</div><div class='ctx'> 					      0,</div><div class='hunk'>@@ -1168,8 +660,8 @@ static void ena_free_all_rx_bufs(struct ena_adapter *adapter)</div><div class='ctx'> 		ena_free_rx_bufs(adapter, i);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_unmap_tx_buff(struct ena_ring *tx_ring,</div><div class='del'>-			      struct ena_tx_buffer *tx_info)</div><div class='add'>+void ena_unmap_tx_buff(struct ena_ring *tx_ring,</div><div class='add'>+		       struct ena_tx_buffer *tx_info)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_com_buf *ena_buf;</div><div class='ctx'> 	u32 cnt;</div><div class='hunk'>@@ -1261,6 +753,7 @@ static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)</div><div class='ctx'> 	for (i = 0; i &lt; adapter-&gt;num_io_queues; i++) {</div><div class='ctx'> 		ena_qid = ENA_IO_RXQ_IDX(i);</div><div class='ctx'> 		cancel_work_sync(&amp;adapter-&gt;ena_napi[i].dim.work);</div><div class='add'>+		ena_xdp_unregister_rxq_info(&amp;adapter-&gt;rx_ring[i]);</div><div class='ctx'> 		ena_com_destroy_io_queue(adapter-&gt;ena_dev, ena_qid);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1271,8 +764,8 @@ static void ena_destroy_all_io_queues(struct ena_adapter *adapter)</div><div class='ctx'> 	ena_destroy_all_rx_queues(adapter);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int handle_invalid_req_id(struct ena_ring *ring, u16 req_id,</div><div class='del'>-				 struct ena_tx_buffer *tx_info, bool is_xdp)</div><div class='add'>+int handle_invalid_req_id(struct ena_ring *ring, u16 req_id,</div><div class='add'>+			  struct ena_tx_buffer *tx_info, bool is_xdp)</div><div class='ctx'> {</div><div class='ctx'> 	if (tx_info)</div><div class='ctx'> 		netif_err(ring-&gt;adapter,</div><div class='hunk'>@@ -1304,17 +797,6 @@ static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)</div><div class='ctx'> 	return handle_invalid_req_id(tx_ring, req_id, tx_info, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int validate_xdp_req_id(struct ena_ring *xdp_ring, u16 req_id)</div><div class='del'>-{</div><div class='del'>-	struct ena_tx_buffer *tx_info;</div><div class='del'>-</div><div class='del'>-	tx_info = &amp;xdp_ring-&gt;tx_buffer_info[req_id];</div><div class='del'>-	if (likely(tx_info-&gt;xdpf))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	return handle_invalid_req_id(xdp_ring, req_id, tx_info, true);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct netdev_queue *txq;</div><div class='hunk'>@@ -1362,7 +844,7 @@ static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)</div><div class='ctx'> 			  "tx_poll: q %d skb %p completed\n", tx_ring-&gt;qid,</div><div class='ctx'> 			  skb);</div><div class='ctx'> </div><div class='del'>-		tx_bytes += skb-&gt;len;</div><div class='add'>+		tx_bytes += tx_info-&gt;total_tx_size;</div><div class='ctx'> 		dev_kfree_skb(skb);</div><div class='ctx'> 		tx_pkts++;</div><div class='ctx'> 		total_done += tx_info-&gt;tx_descs;</div><div class='hunk'>@@ -1492,11 +974,6 @@ static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,</div><div class='ctx'> 		if (unlikely(!skb))</div><div class='ctx'> 			return NULL;</div><div class='ctx'> </div><div class='del'>-		/* sync this buffer for CPU use */</div><div class='del'>-		dma_sync_single_for_cpu(rx_ring-&gt;dev,</div><div class='del'>-					dma_unmap_addr(&amp;rx_info-&gt;ena_buf, paddr) + pkt_offset,</div><div class='del'>-					len,</div><div class='del'>-					DMA_FROM_DEVICE);</div><div class='ctx'> 		skb_copy_to_linear_data(skb, buf_addr + buf_offset, len);</div><div class='ctx'> 		dma_sync_single_for_device(rx_ring-&gt;dev,</div><div class='ctx'> 					   dma_unmap_addr(&amp;rx_info-&gt;ena_buf, paddr) + pkt_offset,</div><div class='hunk'>@@ -1515,17 +992,10 @@ static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,</div><div class='ctx'> </div><div class='ctx'> 	buf_len = SKB_DATA_ALIGN(len + buf_offset + tailroom);</div><div class='ctx'> </div><div class='del'>-	pre_reuse_paddr = dma_unmap_addr(&amp;rx_info-&gt;ena_buf, paddr);</div><div class='del'>-</div><div class='ctx'> 	/* If XDP isn't loaded try to reuse part of the RX buffer */</div><div class='ctx'> 	reuse_rx_buf_page = !is_xdp_loaded &amp;&amp;</div><div class='ctx'> 			    ena_try_rx_buf_page_reuse(rx_info, buf_len, len, pkt_offset);</div><div class='ctx'> </div><div class='del'>-	dma_sync_single_for_cpu(rx_ring-&gt;dev,</div><div class='del'>-				pre_reuse_paddr + pkt_offset,</div><div class='del'>-				len,</div><div class='del'>-				DMA_FROM_DEVICE);</div><div class='del'>-</div><div class='ctx'> 	if (!reuse_rx_buf_page)</div><div class='ctx'> 		ena_unmap_rx_buff_attrs(rx_ring, rx_info, DMA_ATTR_SKIP_CPU_SYNC);</div><div class='ctx'> </div><div class='hunk'>@@ -1671,20 +1141,23 @@ static void ena_set_rx_hash(struct ena_ring *rx_ring,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_xdp_handle_buff(struct ena_ring *rx_ring, struct xdp_buff *xdp)</div><div class='add'>+static int ena_xdp_handle_buff(struct ena_ring *rx_ring, struct xdp_buff *xdp, u16 num_descs)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_rx_buffer *rx_info;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='add'>+	/* XDP multi-buffer packets not supported */</div><div class='add'>+	if (unlikely(num_descs &gt; 1)) {</div><div class='add'>+		netdev_err_once(rx_ring-&gt;adapter-&gt;netdev,</div><div class='add'>+				"xdp: dropped unsupported multi-buffer packets\n");</div><div class='add'>+		ena_increase_stat(&amp;rx_ring-&gt;rx_stats.xdp_drop, 1, &amp;rx_ring-&gt;syncp);</div><div class='add'>+		return ENA_XDP_DROP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	rx_info = &amp;rx_ring-&gt;rx_buffer_info[rx_ring-&gt;ena_bufs[0].req_id];</div><div class='ctx'> 	xdp_prepare_buff(xdp, page_address(rx_info-&gt;page),</div><div class='ctx'> 			 rx_info-&gt;buf_offset,</div><div class='ctx'> 			 rx_ring-&gt;ena_bufs[0].len, false);</div><div class='del'>-	/* If for some reason we received a bigger packet than</div><div class='del'>-	 * we expect, then we simply drop it</div><div class='del'>-	 */</div><div class='del'>-	if (unlikely(rx_ring-&gt;ena_bufs[0].len &gt; ENA_XDP_MAX_MTU))</div><div class='del'>-		return ENA_XDP_DROP;</div><div class='ctx'> </div><div class='ctx'> 	ret = ena_xdp_execute(rx_ring, xdp);</div><div class='ctx'> </div><div class='hunk'>@@ -1696,6 +1169,7 @@ static int ena_xdp_handle_buff(struct ena_ring *rx_ring, struct xdp_buff *xdp)</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /* ena_clean_rx_irq - Cleanup RX irq</div><div class='ctx'>  * @rx_ring: RX ring to clean</div><div class='ctx'>  * @napi: napi handler</div><div class='hunk'>@@ -1719,6 +1193,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,</div><div class='ctx'> 	int xdp_flags = 0;</div><div class='ctx'> 	int total_len = 0;</div><div class='ctx'> 	int xdp_verdict;</div><div class='add'>+	u8 pkt_offset;</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -1745,15 +1220,21 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,</div><div class='ctx'> </div><div class='ctx'> 		/* First descriptor might have an offset set by the device */</div><div class='ctx'> 		rx_info = &amp;rx_ring-&gt;rx_buffer_info[rx_ring-&gt;ena_bufs[0].req_id];</div><div class='del'>-		rx_info-&gt;buf_offset += ena_rx_ctx.pkt_offset;</div><div class='add'>+		pkt_offset = ena_rx_ctx.pkt_offset;</div><div class='add'>+		rx_info-&gt;buf_offset += pkt_offset;</div><div class='ctx'> </div><div class='ctx'> 		netif_dbg(rx_ring-&gt;adapter, rx_status, rx_ring-&gt;netdev,</div><div class='ctx'> 			  "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",</div><div class='ctx'> 			  rx_ring-&gt;qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,</div><div class='ctx'> 			  ena_rx_ctx.l4_proto, ena_rx_ctx.hash);</div><div class='ctx'> </div><div class='add'>+		dma_sync_single_for_cpu(rx_ring-&gt;dev,</div><div class='add'>+					dma_unmap_addr(&amp;rx_info-&gt;ena_buf, paddr) + pkt_offset,</div><div class='add'>+					rx_ring-&gt;ena_bufs[0].len,</div><div class='add'>+					DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='ctx'> 		if (ena_xdp_present_ring(rx_ring))</div><div class='del'>-			xdp_verdict = ena_xdp_handle_buff(rx_ring, &amp;xdp);</div><div class='add'>+			xdp_verdict = ena_xdp_handle_buff(rx_ring, &amp;xdp, ena_rx_ctx.descs);</div><div class='ctx'> </div><div class='ctx'> 		/* allocate skb and fill it */</div><div class='ctx'> 		if (xdp_verdict == ENA_XDP_PASS)</div><div class='hunk'>@@ -1777,7 +1258,7 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,</div><div class='ctx'> 				if (xdp_verdict &amp; ENA_XDP_FORWARDED) {</div><div class='ctx'> 					ena_unmap_rx_buff_attrs(rx_ring,</div><div class='ctx'> 								&amp;rx_ring-&gt;rx_buffer_info[req_id],</div><div class='del'>-								0);</div><div class='add'>+								DMA_ATTR_SKIP_CPU_SYNC);</div><div class='ctx'> 					rx_ring-&gt;rx_buffer_info[req_id].page = NULL;</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1881,8 +1362,8 @@ static void ena_adjust_adaptive_rx_intr_moderation(struct ena_napi *ena_napi)</div><div class='ctx'> 	rx_ring-&gt;per_napi_packets = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_unmask_interrupt(struct ena_ring *tx_ring,</div><div class='del'>-					struct ena_ring *rx_ring)</div><div class='add'>+void ena_unmask_interrupt(struct ena_ring *tx_ring,</div><div class='add'>+			  struct ena_ring *rx_ring)</div><div class='ctx'> {</div><div class='ctx'> 	u32 rx_interval = tx_ring-&gt;smoothed_interval;</div><div class='ctx'> 	struct ena_eth_io_intr_reg intr_reg;</div><div class='hunk'>@@ -1914,8 +1395,8 @@ static void ena_unmask_interrupt(struct ena_ring *tx_ring,</div><div class='ctx'> 	ena_com_unmask_intr(tx_ring-&gt;ena_com_io_cq, &amp;intr_reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_update_ring_numa_node(struct ena_ring *tx_ring,</div><div class='del'>-					     struct ena_ring *rx_ring)</div><div class='add'>+void ena_update_ring_numa_node(struct ena_ring *tx_ring,</div><div class='add'>+			       struct ena_ring *rx_ring)</div><div class='ctx'> {</div><div class='ctx'> 	int cpu = get_cpu();</div><div class='ctx'> 	int numa_node;</div><div class='hunk'>@@ -1950,67 +1431,6 @@ out:</div><div class='ctx'> 	put_cpu();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_clean_xdp_irq(struct ena_ring *xdp_ring, u32 budget)</div><div class='del'>-{</div><div class='del'>-	u32 total_done = 0;</div><div class='del'>-	u16 next_to_clean;</div><div class='del'>-	int tx_pkts = 0;</div><div class='del'>-	u16 req_id;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	if (unlikely(!xdp_ring))</div><div class='del'>-		return 0;</div><div class='del'>-	next_to_clean = xdp_ring-&gt;next_to_clean;</div><div class='del'>-</div><div class='del'>-	while (tx_pkts &lt; budget) {</div><div class='del'>-		struct ena_tx_buffer *tx_info;</div><div class='del'>-		struct xdp_frame *xdpf;</div><div class='del'>-</div><div class='del'>-		rc = ena_com_tx_comp_req_id_get(xdp_ring-&gt;ena_com_io_cq,</div><div class='del'>-						&amp;req_id);</div><div class='del'>-		if (rc) {</div><div class='del'>-			if (unlikely(rc == -EINVAL))</div><div class='del'>-				handle_invalid_req_id(xdp_ring, req_id, NULL,</div><div class='del'>-						      true);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* validate that the request id points to a valid xdp_frame */</div><div class='del'>-		rc = validate_xdp_req_id(xdp_ring, req_id);</div><div class='del'>-		if (rc)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		tx_info = &amp;xdp_ring-&gt;tx_buffer_info[req_id];</div><div class='del'>-		xdpf = tx_info-&gt;xdpf;</div><div class='del'>-</div><div class='del'>-		tx_info-&gt;xdpf = NULL;</div><div class='del'>-		tx_info-&gt;last_jiffies = 0;</div><div class='del'>-		ena_unmap_tx_buff(xdp_ring, tx_info);</div><div class='del'>-</div><div class='del'>-		netif_dbg(xdp_ring-&gt;adapter, tx_done, xdp_ring-&gt;netdev,</div><div class='del'>-			  "tx_poll: q %d skb %p completed\n", xdp_ring-&gt;qid,</div><div class='del'>-			  xdpf);</div><div class='del'>-</div><div class='del'>-		tx_pkts++;</div><div class='del'>-		total_done += tx_info-&gt;tx_descs;</div><div class='del'>-</div><div class='del'>-		xdp_return_frame(xdpf);</div><div class='del'>-		xdp_ring-&gt;free_ids[next_to_clean] = req_id;</div><div class='del'>-		next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,</div><div class='del'>-						     xdp_ring-&gt;ring_size);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	xdp_ring-&gt;next_to_clean = next_to_clean;</div><div class='del'>-	ena_com_comp_ack(xdp_ring-&gt;ena_com_io_sq, total_done);</div><div class='del'>-	ena_com_update_dev_comp_head(xdp_ring-&gt;ena_com_io_cq);</div><div class='del'>-</div><div class='del'>-	netif_dbg(xdp_ring-&gt;adapter, tx_done, xdp_ring-&gt;netdev,</div><div class='del'>-		  "tx_poll: q %d done. total pkts: %d\n",</div><div class='del'>-		  xdp_ring-&gt;qid, tx_pkts);</div><div class='del'>-</div><div class='del'>-	return tx_pkts;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int ena_io_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);</div><div class='hunk'>@@ -2327,28 +1747,36 @@ static void ena_del_napi_in_range(struct ena_adapter *adapter,</div><div class='ctx'> 	for (i = first_index; i &lt; first_index + count; i++) {</div><div class='ctx'> 		netif_napi_del(&amp;adapter-&gt;ena_napi[i].napi);</div><div class='ctx'> </div><div class='del'>-		WARN_ON(!ENA_IS_XDP_INDEX(adapter, i) &amp;&amp;</div><div class='del'>-			adapter-&gt;ena_napi[i].xdp_ring);</div><div class='add'>+		WARN_ON(ENA_IS_XDP_INDEX(adapter, i) &amp;&amp;</div><div class='add'>+			adapter-&gt;ena_napi[i].rx_ring);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ena_init_napi_in_range(struct ena_adapter *adapter,</div><div class='ctx'> 				   int first_index, int count)</div><div class='ctx'> {</div><div class='add'>+	int (*napi_handler)(struct napi_struct *napi, int budget);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = first_index; i &lt; first_index + count; i++) {</div><div class='ctx'> 		struct ena_napi *napi = &amp;adapter-&gt;ena_napi[i];</div><div class='add'>+		struct ena_ring *rx_ring, *tx_ring;</div><div class='ctx'> </div><div class='del'>-		netif_napi_add(adapter-&gt;netdev, &amp;napi-&gt;napi,</div><div class='del'>-			       ENA_IS_XDP_INDEX(adapter, i) ? ena_xdp_io_poll : ena_io_poll);</div><div class='add'>+		memset(napi, 0, sizeof(*napi));</div><div class='ctx'> </div><div class='del'>-		if (!ENA_IS_XDP_INDEX(adapter, i)) {</div><div class='del'>-			napi-&gt;rx_ring = &amp;adapter-&gt;rx_ring[i];</div><div class='del'>-			napi-&gt;tx_ring = &amp;adapter-&gt;tx_ring[i];</div><div class='del'>-		} else {</div><div class='del'>-			napi-&gt;xdp_ring = &amp;adapter-&gt;tx_ring[i];</div><div class='del'>-		}</div><div class='add'>+		rx_ring = &amp;adapter-&gt;rx_ring[i];</div><div class='add'>+		tx_ring = &amp;adapter-&gt;tx_ring[i];</div><div class='add'>+</div><div class='add'>+		napi_handler = ena_io_poll;</div><div class='add'>+		if (ENA_IS_XDP_INDEX(adapter, i))</div><div class='add'>+			napi_handler = ena_xdp_io_poll;</div><div class='add'>+</div><div class='add'>+		netif_napi_add(adapter-&gt;netdev, &amp;napi-&gt;napi, napi_handler);</div><div class='add'>+</div><div class='add'>+		if (!ENA_IS_XDP_INDEX(adapter, i))</div><div class='add'>+			napi-&gt;rx_ring = rx_ring;</div><div class='add'>+</div><div class='add'>+		napi-&gt;tx_ring = tx_ring;</div><div class='ctx'> 		napi-&gt;qid = i;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -2476,8 +1904,8 @@ static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_create_io_tx_queues_in_range(struct ena_adapter *adapter,</div><div class='del'>-					    int first_index, int count)</div><div class='add'>+int ena_create_io_tx_queues_in_range(struct ena_adapter *adapter,</div><div class='add'>+				     int first_index, int count)</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_com_dev *ena_dev = adapter-&gt;ena_dev;</div><div class='ctx'> 	int rc, i;</div><div class='hunk'>@@ -2557,12 +1985,15 @@ static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			goto create_err;</div><div class='ctx'> 		INIT_WORK(&amp;adapter-&gt;ena_napi[i].dim.work, ena_dim_work);</div><div class='add'>+</div><div class='add'>+		ena_xdp_register_rxq_info(&amp;adapter-&gt;rx_ring[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> create_err:</div><div class='ctx'> 	while (i--) {</div><div class='add'>+		ena_xdp_unregister_rxq_info(&amp;adapter-&gt;rx_ring[i]);</div><div class='ctx'> 		cancel_work_sync(&amp;adapter-&gt;ena_napi[i].dim.work);</div><div class='ctx'> 		ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2687,7 +2118,7 @@ err_setup_tx:</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ena_up(struct ena_adapter *adapter)</div><div class='add'>+int ena_up(struct ena_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> 	int io_queue_count, rc, i;</div><div class='ctx'> </div><div class='hunk'>@@ -2749,7 +2180,7 @@ err_req_irq:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ena_down(struct ena_adapter *adapter)</div><div class='add'>+void ena_down(struct ena_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> 	int io_queue_count = adapter-&gt;num_io_queues + adapter-&gt;xdp_num_queues;</div><div class='ctx'> </div><div class='hunk'>@@ -3180,7 +2611,7 @@ static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 	/* set flags and meta data */</div><div class='ctx'> 	ena_tx_csum(&amp;ena_tx_ctx, skb, tx_ring-&gt;disable_meta_caching);</div><div class='ctx'> </div><div class='del'>-	rc = ena_xmit_common(dev,</div><div class='add'>+	rc = ena_xmit_common(adapter,</div><div class='ctx'> 			     tx_ring,</div><div class='ctx'> 			     tx_info,</div><div class='ctx'> 			     &amp;ena_tx_ctx,</div><div class='hunk'>@@ -3276,8 +2707,8 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev, struct pci_dev *pd</div><div class='ctx'> 	strscpy(host_info-&gt;kernel_ver_str, utsname()-&gt;version,</div><div class='ctx'> 		sizeof(host_info-&gt;kernel_ver_str) - 1);</div><div class='ctx'> 	host_info-&gt;os_dist = 0;</div><div class='del'>-	strncpy(host_info-&gt;os_dist_str, utsname()-&gt;release,</div><div class='del'>-		sizeof(host_info-&gt;os_dist_str) - 1);</div><div class='add'>+	strscpy(host_info-&gt;os_dist_str, utsname()-&gt;release,</div><div class='add'>+		sizeof(host_info-&gt;os_dist_str));</div><div class='ctx'> 	host_info-&gt;driver_version =</div><div class='ctx'> 		(DRV_MODULE_GEN_MAJOR) |</div><div class='ctx'> 		(DRV_MODULE_GEN_MINOR &lt;&lt; ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |</div><div class='hunk'>@@ -3364,6 +2795,7 @@ static void ena_get_stats64(struct net_device *netdev,</div><div class='ctx'> {</div><div class='ctx'> 	struct ena_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	struct ena_ring *rx_ring, *tx_ring;</div><div class='add'>+	u64 total_xdp_rx_drops = 0;</div><div class='ctx'> 	unsigned int start;</div><div class='ctx'> 	u64 rx_drops;</div><div class='ctx'> 	u64 tx_drops;</div><div class='hunk'>@@ -3372,8 +2804,8 @@ static void ena_get_stats64(struct net_device *netdev,</div><div class='ctx'> 	if (!test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; adapter-&gt;num_io_queues; i++) {</div><div class='del'>-		u64 bytes, packets;</div><div class='add'>+	for (i = 0; i &lt; adapter-&gt;num_io_queues + adapter-&gt;xdp_num_queues; i++) {</div><div class='add'>+		u64 bytes, packets, xdp_rx_drops;</div><div class='ctx'> </div><div class='ctx'> 		tx_ring = &amp;adapter-&gt;tx_ring[i];</div><div class='ctx'> </div><div class='hunk'>@@ -3386,16 +2818,22 @@ static void ena_get_stats64(struct net_device *netdev,</div><div class='ctx'> 		stats-&gt;tx_packets += packets;</div><div class='ctx'> 		stats-&gt;tx_bytes += bytes;</div><div class='ctx'> </div><div class='add'>+		/* In XDP there isn't an RX queue counterpart */</div><div class='add'>+		if (ENA_IS_XDP_INDEX(adapter, i))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		rx_ring = &amp;adapter-&gt;rx_ring[i];</div><div class='ctx'> </div><div class='ctx'> 		do {</div><div class='ctx'> 			start = u64_stats_fetch_begin(&amp;rx_ring-&gt;syncp);</div><div class='ctx'> 			packets = rx_ring-&gt;rx_stats.cnt;</div><div class='ctx'> 			bytes = rx_ring-&gt;rx_stats.bytes;</div><div class='add'>+			xdp_rx_drops = rx_ring-&gt;rx_stats.xdp_drop;</div><div class='ctx'> 		} while (u64_stats_fetch_retry(&amp;rx_ring-&gt;syncp, start));</div><div class='ctx'> </div><div class='ctx'> 		stats-&gt;rx_packets += packets;</div><div class='ctx'> 		stats-&gt;rx_bytes += bytes;</div><div class='add'>+		total_xdp_rx_drops += xdp_rx_drops;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='hunk'>@@ -3404,7 +2842,7 @@ static void ena_get_stats64(struct net_device *netdev,</div><div class='ctx'> 		tx_drops = adapter-&gt;dev_stats.tx_drops;</div><div class='ctx'> 	} while (u64_stats_fetch_retry(&amp;adapter-&gt;syncp, start));</div><div class='ctx'> </div><div class='del'>-	stats-&gt;rx_dropped = rx_drops;</div><div class='add'>+	stats-&gt;rx_dropped = rx_drops + total_xdp_rx_drops;</div><div class='ctx'> 	stats-&gt;tx_dropped = tx_drops;</div><div class='ctx'> </div><div class='ctx'> 	stats-&gt;multicast = 0;</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.h b/drivers/net/ethernet/amazon/ena/ena_netdev.h<br/>index 33c923e1261a..6d2cc20210cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_netdev.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amazon/ena/ena_netdev.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_netdev.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_netdev.h</a></div><div class='hunk'>@@ -110,19 +110,6 @@</div><div class='ctx'> </div><div class='ctx'> #define ENA_MMIO_DISABLE_REG_READ	BIT(0)</div><div class='ctx'> </div><div class='del'>-/* The max MTU size is configured to be the ethernet frame size without</div><div class='del'>- * the overhead of the ethernet header, which can have a VLAN header, and</div><div class='del'>- * a frame check sequence (FCS).</div><div class='del'>- * The buffer size we share with the device is defined to be ENA_PAGE_SIZE</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN -	\</div><div class='del'>-			 VLAN_HLEN - XDP_PACKET_HEADROOM -		\</div><div class='del'>-			 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))</div><div class='del'>-</div><div class='del'>-#define ENA_IS_XDP_INDEX(adapter, index) (((index) &gt;= (adapter)-&gt;xdp_first_ring) &amp;&amp; \</div><div class='del'>-	((index) &lt; (adapter)-&gt;xdp_first_ring + (adapter)-&gt;xdp_num_queues))</div><div class='del'>-</div><div class='ctx'> struct ena_irq {</div><div class='ctx'> 	irq_handler_t handler;</div><div class='ctx'> 	void *data;</div><div class='hunk'>@@ -138,13 +125,18 @@ struct ena_napi {</div><div class='ctx'> 	struct napi_struct napi;</div><div class='ctx'> 	struct ena_ring *tx_ring;</div><div class='ctx'> 	struct ena_ring *rx_ring;</div><div class='del'>-	struct ena_ring *xdp_ring;</div><div class='ctx'> 	u32 qid;</div><div class='ctx'> 	struct dim dim;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ena_tx_buffer {</div><div class='del'>-	struct sk_buff *skb;</div><div class='add'>+	union {</div><div class='add'>+		struct sk_buff *skb;</div><div class='add'>+		/* XDP buffer structure which is used for sending packets in</div><div class='add'>+		 * the xdp queues</div><div class='add'>+		 */</div><div class='add'>+		struct xdp_frame *xdpf;</div><div class='add'>+	};</div><div class='ctx'> 	/* num of ena desc for this specific skb</div><div class='ctx'> 	 * (includes data desc and metadata desc)</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -152,16 +144,14 @@ struct ena_tx_buffer {</div><div class='ctx'> 	/* num of buffers used by this skb */</div><div class='ctx'> 	u32 num_of_bufs;</div><div class='ctx'> </div><div class='del'>-	/* XDP buffer structure which is used for sending packets in</div><div class='del'>-	 * the xdp queues</div><div class='del'>-	 */</div><div class='del'>-	struct xdp_frame *xdpf;</div><div class='add'>+	/* Total size of all buffers in bytes */</div><div class='add'>+	u32 total_tx_size;</div><div class='ctx'> </div><div class='ctx'> 	/* Indicate if bufs[0] map the linear data of the skb. */</div><div class='ctx'> 	u8 map_linear_data;</div><div class='ctx'> </div><div class='ctx'> 	/* Used for detect missing tx packets to limit the number of prints */</div><div class='del'>-	u32 print_once;</div><div class='add'>+	u8 print_once;</div><div class='ctx'> 	/* Save the last jiffies to detect missing tx packets</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * sets to non zero value on ena_start_xmit and set to zero on</div><div class='hunk'>@@ -421,47 +411,44 @@ static inline void ena_reset_device(struct ena_adapter *adapter,</div><div class='ctx'> 	set_bit(ENA_FLAG_TRIGGER_RESET, &amp;adapter-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-enum ena_xdp_errors_t {</div><div class='del'>-	ENA_XDP_ALLOWED = 0,</div><div class='del'>-	ENA_XDP_CURRENT_MTU_TOO_LARGE,</div><div class='del'>-	ENA_XDP_NO_ENOUGH_QUEUES,</div><div class='del'>-};</div><div class='add'>+int handle_invalid_req_id(struct ena_ring *ring, u16 req_id,</div><div class='add'>+			  struct ena_tx_buffer *tx_info, bool is_xdp);</div><div class='ctx'> </div><div class='del'>-enum ENA_XDP_ACTIONS {</div><div class='del'>-	ENA_XDP_PASS		= 0,</div><div class='del'>-	ENA_XDP_TX		= BIT(0),</div><div class='del'>-	ENA_XDP_REDIRECT	= BIT(1),</div><div class='del'>-	ENA_XDP_DROP		= BIT(2)</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define ENA_XDP_FORWARDED (ENA_XDP_TX | ENA_XDP_REDIRECT)</div><div class='del'>-</div><div class='del'>-static inline bool ena_xdp_present(struct ena_adapter *adapter)</div><div class='del'>-{</div><div class='del'>-	return !!adapter-&gt;xdp_bpf_prog;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline bool ena_xdp_present_ring(struct ena_ring *ring)</div><div class='add'>+/* Increase a stat by cnt while holding syncp seqlock on 32bit machines */</div><div class='add'>+static inline void ena_increase_stat(u64 *statp, u64 cnt,</div><div class='add'>+				     struct u64_stats_sync *syncp)</div><div class='ctx'> {</div><div class='del'>-	return !!ring-&gt;xdp_bpf_prog;</div><div class='add'>+	u64_stats_update_begin(syncp);</div><div class='add'>+	(*statp) += cnt;</div><div class='add'>+	u64_stats_update_end(syncp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline bool ena_xdp_legal_queue_count(struct ena_adapter *adapter,</div><div class='del'>-					     u32 queues)</div><div class='add'>+static inline void ena_ring_tx_doorbell(struct ena_ring *tx_ring)</div><div class='ctx'> {</div><div class='del'>-	return 2 * queues &lt;= adapter-&gt;max_num_io_queues;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter)</div><div class='del'>-{</div><div class='del'>-	enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED;</div><div class='del'>-</div><div class='del'>-	if (adapter-&gt;netdev-&gt;mtu &gt; ENA_XDP_MAX_MTU)</div><div class='del'>-		rc = ENA_XDP_CURRENT_MTU_TOO_LARGE;</div><div class='del'>-	else if (!ena_xdp_legal_queue_count(adapter, adapter-&gt;num_io_queues))</div><div class='del'>-		rc = ENA_XDP_NO_ENOUGH_QUEUES;</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='add'>+	ena_com_write_sq_doorbell(tx_ring-&gt;ena_com_io_sq);</div><div class='add'>+	ena_increase_stat(&amp;tx_ring-&gt;tx_stats.doorbells, 1, &amp;tx_ring-&gt;syncp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int ena_xmit_common(struct ena_adapter *adapter,</div><div class='add'>+		    struct ena_ring *ring,</div><div class='add'>+		    struct ena_tx_buffer *tx_info,</div><div class='add'>+		    struct ena_com_tx_ctx *ena_tx_ctx,</div><div class='add'>+		    u16 next_to_use,</div><div class='add'>+		    u32 bytes);</div><div class='add'>+void ena_unmap_tx_buff(struct ena_ring *tx_ring,</div><div class='add'>+		       struct ena_tx_buffer *tx_info);</div><div class='add'>+void ena_init_io_rings(struct ena_adapter *adapter,</div><div class='add'>+		       int first_index, int count);</div><div class='add'>+int ena_create_io_tx_queues_in_range(struct ena_adapter *adapter,</div><div class='add'>+				     int first_index, int count);</div><div class='add'>+int ena_setup_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='add'>+				    int first_index, int count);</div><div class='add'>+void ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter,</div><div class='add'>+					   int first_index, int count);</div><div class='add'>+void ena_free_all_io_tx_resources(struct ena_adapter *adapter);</div><div class='add'>+void ena_down(struct ena_adapter *adapter);</div><div class='add'>+int ena_up(struct ena_adapter *adapter);</div><div class='add'>+void ena_unmask_interrupt(struct ena_ring *tx_ring, struct ena_ring *rx_ring);</div><div class='add'>+void ena_update_ring_numa_node(struct ena_ring *tx_ring,</div><div class='add'>+			       struct ena_ring *rx_ring);</div><div class='ctx'> #endif /* !(ENA_H) */</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_xdp.c b/drivers/net/ethernet/amazon/ena/ena_xdp.c<br/>new file mode 100644<br/>index 000000000000..fc1c4ef73ba3<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_xdp.c</a></div><div class='hunk'>@@ -0,0 +1,468 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2015-2021 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include "ena_xdp.h"</div><div class='add'>+</div><div class='add'>+static int validate_xdp_req_id(struct ena_ring *tx_ring, u16 req_id)</div><div class='add'>+{</div><div class='add'>+	struct ena_tx_buffer *tx_info;</div><div class='add'>+</div><div class='add'>+	tx_info = &amp;tx_ring-&gt;tx_buffer_info[req_id];</div><div class='add'>+	if (likely(tx_info-&gt;xdpf))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return handle_invalid_req_id(tx_ring, req_id, tx_info, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ena_xdp_tx_map_frame(struct ena_ring *tx_ring,</div><div class='add'>+				struct ena_tx_buffer *tx_info,</div><div class='add'>+				struct xdp_frame *xdpf,</div><div class='add'>+				struct ena_com_tx_ctx *ena_tx_ctx)</div><div class='add'>+{</div><div class='add'>+	struct ena_adapter *adapter = tx_ring-&gt;adapter;</div><div class='add'>+	struct ena_com_buf *ena_buf;</div><div class='add'>+	int push_len = 0;</div><div class='add'>+	dma_addr_t dma;</div><div class='add'>+	void *data;</div><div class='add'>+	u32 size;</div><div class='add'>+</div><div class='add'>+	tx_info-&gt;xdpf = xdpf;</div><div class='add'>+	data = tx_info-&gt;xdpf-&gt;data;</div><div class='add'>+	size = tx_info-&gt;xdpf-&gt;len;</div><div class='add'>+</div><div class='add'>+	if (tx_ring-&gt;tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {</div><div class='add'>+		/* Designate part of the packet for LLQ */</div><div class='add'>+		push_len = min_t(u32, size, tx_ring-&gt;tx_max_header_size);</div><div class='add'>+</div><div class='add'>+		ena_tx_ctx-&gt;push_header = data;</div><div class='add'>+</div><div class='add'>+		size -= push_len;</div><div class='add'>+		data += push_len;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ena_tx_ctx-&gt;header_len = push_len;</div><div class='add'>+</div><div class='add'>+	if (size &gt; 0) {</div><div class='add'>+		dma = dma_map_single(tx_ring-&gt;dev,</div><div class='add'>+				     data,</div><div class='add'>+				     size,</div><div class='add'>+				     DMA_TO_DEVICE);</div><div class='add'>+		if (unlikely(dma_mapping_error(tx_ring-&gt;dev, dma)))</div><div class='add'>+			goto error_report_dma_error;</div><div class='add'>+</div><div class='add'>+		tx_info-&gt;map_linear_data = 0;</div><div class='add'>+</div><div class='add'>+		ena_buf = tx_info-&gt;bufs;</div><div class='add'>+		ena_buf-&gt;paddr = dma;</div><div class='add'>+		ena_buf-&gt;len = size;</div><div class='add'>+</div><div class='add'>+		ena_tx_ctx-&gt;ena_bufs = ena_buf;</div><div class='add'>+		ena_tx_ctx-&gt;num_bufs = tx_info-&gt;num_of_bufs = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+error_report_dma_error:</div><div class='add'>+	ena_increase_stat(&amp;tx_ring-&gt;tx_stats.dma_mapping_err, 1,</div><div class='add'>+			  &amp;tx_ring-&gt;syncp);</div><div class='add'>+	netif_warn(adapter, tx_queued, adapter-&gt;netdev, "Failed to map xdp buff\n");</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int ena_xdp_xmit_frame(struct ena_ring *tx_ring,</div><div class='add'>+		       struct ena_adapter *adapter,</div><div class='add'>+		       struct xdp_frame *xdpf,</div><div class='add'>+		       int flags)</div><div class='add'>+{</div><div class='add'>+	struct ena_com_tx_ctx ena_tx_ctx = {};</div><div class='add'>+	struct ena_tx_buffer *tx_info;</div><div class='add'>+	u16 next_to_use, req_id;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	next_to_use = tx_ring-&gt;next_to_use;</div><div class='add'>+	req_id = tx_ring-&gt;free_ids[next_to_use];</div><div class='add'>+	tx_info = &amp;tx_ring-&gt;tx_buffer_info[req_id];</div><div class='add'>+	tx_info-&gt;num_of_bufs = 0;</div><div class='add'>+</div><div class='add'>+	rc = ena_xdp_tx_map_frame(tx_ring, tx_info, xdpf, &amp;ena_tx_ctx);</div><div class='add'>+	if (unlikely(rc))</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	ena_tx_ctx.req_id = req_id;</div><div class='add'>+</div><div class='add'>+	rc = ena_xmit_common(adapter,</div><div class='add'>+			     tx_ring,</div><div class='add'>+			     tx_info,</div><div class='add'>+			     &amp;ena_tx_ctx,</div><div class='add'>+			     next_to_use,</div><div class='add'>+			     xdpf-&gt;len);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto error_unmap_dma;</div><div class='add'>+</div><div class='add'>+	/* trigger the dma engine. ena_ring_tx_doorbell()</div><div class='add'>+	 * calls a memory barrier inside it.</div><div class='add'>+	 */</div><div class='add'>+	if (flags &amp; XDP_XMIT_FLUSH)</div><div class='add'>+		ena_ring_tx_doorbell(tx_ring);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+</div><div class='add'>+error_unmap_dma:</div><div class='add'>+	ena_unmap_tx_buff(tx_ring, tx_info);</div><div class='add'>+	tx_info-&gt;xdpf = NULL;</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int ena_xdp_xmit(struct net_device *dev, int n,</div><div class='add'>+		 struct xdp_frame **frames, u32 flags)</div><div class='add'>+{</div><div class='add'>+	struct ena_adapter *adapter = netdev_priv(dev);</div><div class='add'>+	struct ena_ring *tx_ring;</div><div class='add'>+	int qid, i, nxmit = 0;</div><div class='add'>+</div><div class='add'>+	if (unlikely(flags &amp; ~XDP_XMIT_FLAGS_MASK))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags))</div><div class='add'>+		return -ENETDOWN;</div><div class='add'>+</div><div class='add'>+	/* We assume that all rings have the same XDP program */</div><div class='add'>+	if (!READ_ONCE(adapter-&gt;rx_ring-&gt;xdp_bpf_prog))</div><div class='add'>+		return -ENXIO;</div><div class='add'>+</div><div class='add'>+	qid = smp_processor_id() % adapter-&gt;xdp_num_queues;</div><div class='add'>+	qid += adapter-&gt;xdp_first_ring;</div><div class='add'>+	tx_ring = &amp;adapter-&gt;tx_ring[qid];</div><div class='add'>+</div><div class='add'>+	/* Other CPU ids might try to send thorugh this queue */</div><div class='add'>+	spin_lock(&amp;tx_ring-&gt;xdp_tx_lock);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; n; i++) {</div><div class='add'>+		if (ena_xdp_xmit_frame(tx_ring, adapter, frames[i], 0))</div><div class='add'>+			break;</div><div class='add'>+		nxmit++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Ring doorbell to make device aware of the packets */</div><div class='add'>+	if (flags &amp; XDP_XMIT_FLUSH)</div><div class='add'>+		ena_ring_tx_doorbell(tx_ring);</div><div class='add'>+</div><div class='add'>+	spin_unlock(&amp;tx_ring-&gt;xdp_tx_lock);</div><div class='add'>+</div><div class='add'>+	/* Return number of packets sent */</div><div class='add'>+	return nxmit;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ena_init_all_xdp_queues(struct ena_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	adapter-&gt;xdp_first_ring = adapter-&gt;num_io_queues;</div><div class='add'>+	adapter-&gt;xdp_num_queues = adapter-&gt;num_io_queues;</div><div class='add'>+</div><div class='add'>+	ena_init_io_rings(adapter,</div><div class='add'>+			  adapter-&gt;xdp_first_ring,</div><div class='add'>+			  adapter-&gt;xdp_num_queues);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int ena_setup_and_create_all_xdp_queues(struct ena_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	u32 xdp_first_ring = adapter-&gt;xdp_first_ring;</div><div class='add'>+	u32 xdp_num_queues = adapter-&gt;xdp_num_queues;</div><div class='add'>+	int rc = 0;</div><div class='add'>+</div><div class='add'>+	rc = ena_setup_tx_resources_in_range(adapter, xdp_first_ring, xdp_num_queues);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto setup_err;</div><div class='add'>+</div><div class='add'>+	rc = ena_create_io_tx_queues_in_range(adapter, xdp_first_ring, xdp_num_queues);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto create_err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+create_err:</div><div class='add'>+	ena_free_all_io_tx_resources_in_range(adapter, xdp_first_ring, xdp_num_queues);</div><div class='add'>+setup_err:</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Provides a way for both kernel and bpf-prog to know</div><div class='add'>+ * more about the RX-queue a given XDP frame arrived on.</div><div class='add'>+ */</div><div class='add'>+int ena_xdp_register_rxq_info(struct ena_ring *rx_ring)</div><div class='add'>+{</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	rc = xdp_rxq_info_reg(&amp;rx_ring-&gt;xdp_rxq, rx_ring-&gt;netdev, rx_ring-&gt;qid, 0);</div><div class='add'>+</div><div class='add'>+	netif_dbg(rx_ring-&gt;adapter, ifup, rx_ring-&gt;netdev, "Registering RX info for queue %d",</div><div class='add'>+		  rx_ring-&gt;qid);</div><div class='add'>+	if (rc) {</div><div class='add'>+		netif_err(rx_ring-&gt;adapter, ifup, rx_ring-&gt;netdev,</div><div class='add'>+			  "Failed to register xdp rx queue info. RX queue num %d rc: %d\n",</div><div class='add'>+			  rx_ring-&gt;qid, rc);</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = xdp_rxq_info_reg_mem_model(&amp;rx_ring-&gt;xdp_rxq, MEM_TYPE_PAGE_SHARED, NULL);</div><div class='add'>+</div><div class='add'>+	if (rc) {</div><div class='add'>+		netif_err(rx_ring-&gt;adapter, ifup, rx_ring-&gt;netdev,</div><div class='add'>+			  "Failed to register xdp rx queue info memory model. RX queue num %d rc: %d\n",</div><div class='add'>+			  rx_ring-&gt;qid, rc);</div><div class='add'>+		xdp_rxq_info_unreg(&amp;rx_ring-&gt;xdp_rxq);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ena_xdp_unregister_rxq_info(struct ena_ring *rx_ring)</div><div class='add'>+{</div><div class='add'>+	netif_dbg(rx_ring-&gt;adapter, ifdown, rx_ring-&gt;netdev,</div><div class='add'>+		  "Unregistering RX info for queue %d",</div><div class='add'>+		  rx_ring-&gt;qid);</div><div class='add'>+	xdp_rxq_info_unreg_mem_model(&amp;rx_ring-&gt;xdp_rxq);</div><div class='add'>+	xdp_rxq_info_unreg(&amp;rx_ring-&gt;xdp_rxq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ena_xdp_exchange_program_rx_in_range(struct ena_adapter *adapter,</div><div class='add'>+					  struct bpf_prog *prog,</div><div class='add'>+					  int first, int count)</div><div class='add'>+{</div><div class='add'>+	struct bpf_prog *old_bpf_prog;</div><div class='add'>+	struct ena_ring *rx_ring;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	for (i = first; i &lt; count; i++) {</div><div class='add'>+		rx_ring = &amp;adapter-&gt;rx_ring[i];</div><div class='add'>+		old_bpf_prog = xchg(&amp;rx_ring-&gt;xdp_bpf_prog, prog);</div><div class='add'>+</div><div class='add'>+		if (!old_bpf_prog &amp;&amp; prog) {</div><div class='add'>+			rx_ring-&gt;rx_headroom = XDP_PACKET_HEADROOM;</div><div class='add'>+		} else if (old_bpf_prog &amp;&amp; !prog) {</div><div class='add'>+			rx_ring-&gt;rx_headroom = NET_SKB_PAD;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ena_xdp_exchange_program(struct ena_adapter *adapter,</div><div class='add'>+				     struct bpf_prog *prog)</div><div class='add'>+{</div><div class='add'>+	struct bpf_prog *old_bpf_prog = xchg(&amp;adapter-&gt;xdp_bpf_prog, prog);</div><div class='add'>+</div><div class='add'>+	ena_xdp_exchange_program_rx_in_range(adapter,</div><div class='add'>+					     prog,</div><div class='add'>+					     0,</div><div class='add'>+					     adapter-&gt;num_io_queues);</div><div class='add'>+</div><div class='add'>+	if (old_bpf_prog)</div><div class='add'>+		bpf_prog_put(old_bpf_prog);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ena_destroy_and_free_all_xdp_queues(struct ena_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	bool was_up;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	was_up = test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags);</div><div class='add'>+</div><div class='add'>+	if (was_up)</div><div class='add'>+		ena_down(adapter);</div><div class='add'>+</div><div class='add'>+	adapter-&gt;xdp_first_ring = 0;</div><div class='add'>+	adapter-&gt;xdp_num_queues = 0;</div><div class='add'>+	ena_xdp_exchange_program(adapter, NULL);</div><div class='add'>+	if (was_up) {</div><div class='add'>+		rc = ena_up(adapter);</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ena_xdp_set(struct net_device *netdev, struct netdev_bpf *bpf)</div><div class='add'>+{</div><div class='add'>+	struct ena_adapter *adapter = netdev_priv(netdev);</div><div class='add'>+	struct bpf_prog *prog = bpf-&gt;prog;</div><div class='add'>+	struct bpf_prog *old_bpf_prog;</div><div class='add'>+	int rc, prev_mtu;</div><div class='add'>+	bool is_up;</div><div class='add'>+</div><div class='add'>+	is_up = test_bit(ENA_FLAG_DEV_UP, &amp;adapter-&gt;flags);</div><div class='add'>+	rc = ena_xdp_allowed(adapter);</div><div class='add'>+	if (rc == ENA_XDP_ALLOWED) {</div><div class='add'>+		old_bpf_prog = adapter-&gt;xdp_bpf_prog;</div><div class='add'>+		if (prog) {</div><div class='add'>+			if (!is_up) {</div><div class='add'>+				ena_init_all_xdp_queues(adapter);</div><div class='add'>+			} else if (!old_bpf_prog) {</div><div class='add'>+				ena_down(adapter);</div><div class='add'>+				ena_init_all_xdp_queues(adapter);</div><div class='add'>+			}</div><div class='add'>+			ena_xdp_exchange_program(adapter, prog);</div><div class='add'>+</div><div class='add'>+			netif_dbg(adapter, drv, adapter-&gt;netdev, "Set a new XDP program\n");</div><div class='add'>+</div><div class='add'>+			if (is_up &amp;&amp; !old_bpf_prog) {</div><div class='add'>+				rc = ena_up(adapter);</div><div class='add'>+				if (rc)</div><div class='add'>+					return rc;</div><div class='add'>+			}</div><div class='add'>+			xdp_features_set_redirect_target(netdev, false);</div><div class='add'>+		} else if (old_bpf_prog) {</div><div class='add'>+			xdp_features_clear_redirect_target(netdev);</div><div class='add'>+			netif_dbg(adapter, drv, adapter-&gt;netdev, "Removing XDP program\n");</div><div class='add'>+</div><div class='add'>+			rc = ena_destroy_and_free_all_xdp_queues(adapter);</div><div class='add'>+			if (rc)</div><div class='add'>+				return rc;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		prev_mtu = netdev-&gt;max_mtu;</div><div class='add'>+		netdev-&gt;max_mtu = prog ? ENA_XDP_MAX_MTU : adapter-&gt;max_mtu;</div><div class='add'>+</div><div class='add'>+		if (!old_bpf_prog)</div><div class='add'>+			netif_info(adapter, drv, adapter-&gt;netdev,</div><div class='add'>+				   "XDP program is set, changing the max_mtu from %d to %d",</div><div class='add'>+				   prev_mtu, netdev-&gt;max_mtu);</div><div class='add'>+</div><div class='add'>+	} else if (rc == ENA_XDP_CURRENT_MTU_TOO_LARGE) {</div><div class='add'>+		netif_err(adapter, drv, adapter-&gt;netdev,</div><div class='add'>+			  "Failed to set xdp program, the current MTU (%d) is larger than the maximum allowed MTU (%lu) while xdp is on",</div><div class='add'>+			  netdev-&gt;mtu, ENA_XDP_MAX_MTU);</div><div class='add'>+		NL_SET_ERR_MSG_MOD(bpf-&gt;extack,</div><div class='add'>+				   "Failed to set xdp program, the current MTU is larger than the maximum allowed MTU. Check the dmesg for more info");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	} else if (rc == ENA_XDP_NO_ENOUGH_QUEUES) {</div><div class='add'>+		netif_err(adapter, drv, adapter-&gt;netdev,</div><div class='add'>+			  "Failed to set xdp program, the Rx/Tx channel count should be at most half of the maximum allowed channel count. The current queue count (%d), the maximal queue count (%d)\n",</div><div class='add'>+			  adapter-&gt;num_io_queues, adapter-&gt;max_num_io_queues);</div><div class='add'>+		NL_SET_ERR_MSG_MOD(bpf-&gt;extack,</div><div class='add'>+				   "Failed to set xdp program, there is no enough space for allocating XDP queues, Check the dmesg for more info");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This is the main xdp callback, it's used by the kernel to set/unset the xdp</div><div class='add'>+ * program as well as to query the current xdp program id.</div><div class='add'>+ */</div><div class='add'>+int ena_xdp(struct net_device *netdev, struct netdev_bpf *bpf)</div><div class='add'>+{</div><div class='add'>+	switch (bpf-&gt;command) {</div><div class='add'>+	case XDP_SETUP_PROG:</div><div class='add'>+		return ena_xdp_set(netdev, bpf);</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ena_clean_xdp_irq(struct ena_ring *tx_ring, u32 budget)</div><div class='add'>+{</div><div class='add'>+	u32 total_done = 0;</div><div class='add'>+	u16 next_to_clean;</div><div class='add'>+	int tx_pkts = 0;</div><div class='add'>+	u16 req_id;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (unlikely(!tx_ring))</div><div class='add'>+		return 0;</div><div class='add'>+	next_to_clean = tx_ring-&gt;next_to_clean;</div><div class='add'>+</div><div class='add'>+	while (tx_pkts &lt; budget) {</div><div class='add'>+		struct ena_tx_buffer *tx_info;</div><div class='add'>+		struct xdp_frame *xdpf;</div><div class='add'>+</div><div class='add'>+		rc = ena_com_tx_comp_req_id_get(tx_ring-&gt;ena_com_io_cq,</div><div class='add'>+						&amp;req_id);</div><div class='add'>+		if (rc) {</div><div class='add'>+			if (unlikely(rc == -EINVAL))</div><div class='add'>+				handle_invalid_req_id(tx_ring, req_id, NULL, true);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* validate that the request id points to a valid xdp_frame */</div><div class='add'>+		rc = validate_xdp_req_id(tx_ring, req_id);</div><div class='add'>+		if (rc)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		tx_info = &amp;tx_ring-&gt;tx_buffer_info[req_id];</div><div class='add'>+</div><div class='add'>+		tx_info-&gt;last_jiffies = 0;</div><div class='add'>+</div><div class='add'>+		xdpf = tx_info-&gt;xdpf;</div><div class='add'>+		tx_info-&gt;xdpf = NULL;</div><div class='add'>+		ena_unmap_tx_buff(tx_ring, tx_info);</div><div class='add'>+		xdp_return_frame(xdpf);</div><div class='add'>+</div><div class='add'>+		tx_pkts++;</div><div class='add'>+		total_done += tx_info-&gt;tx_descs;</div><div class='add'>+		tx_ring-&gt;free_ids[next_to_clean] = req_id;</div><div class='add'>+		next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,</div><div class='add'>+						     tx_ring-&gt;ring_size);</div><div class='add'>+</div><div class='add'>+		netif_dbg(tx_ring-&gt;adapter, tx_done, tx_ring-&gt;netdev,</div><div class='add'>+			  "tx_poll: q %d pkt #%d req_id %d\n", tx_ring-&gt;qid, tx_pkts, req_id);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tx_ring-&gt;next_to_clean = next_to_clean;</div><div class='add'>+	ena_com_comp_ack(tx_ring-&gt;ena_com_io_sq, total_done);</div><div class='add'>+	ena_com_update_dev_comp_head(tx_ring-&gt;ena_com_io_cq);</div><div class='add'>+</div><div class='add'>+	netif_dbg(tx_ring-&gt;adapter, tx_done, tx_ring-&gt;netdev,</div><div class='add'>+		  "tx_poll: q %d done. total pkts: %d\n",</div><div class='add'>+		  tx_ring-&gt;qid, tx_pkts);</div><div class='add'>+</div><div class='add'>+	return tx_pkts;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* This is the XDP napi callback. XDP queues use a separate napi callback</div><div class='add'>+ * than Rx/Tx queues.</div><div class='add'>+ */</div><div class='add'>+int ena_xdp_io_poll(struct napi_struct *napi, int budget)</div><div class='add'>+{</div><div class='add'>+	struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);</div><div class='add'>+	struct ena_ring *tx_ring;</div><div class='add'>+	u32 work_done;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	tx_ring = ena_napi-&gt;tx_ring;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ENA_FLAG_DEV_UP, &amp;tx_ring-&gt;adapter-&gt;flags) ||</div><div class='add'>+	    test_bit(ENA_FLAG_TRIGGER_RESET, &amp;tx_ring-&gt;adapter-&gt;flags)) {</div><div class='add'>+		napi_complete_done(napi, 0);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	work_done = ena_clean_xdp_irq(tx_ring, budget);</div><div class='add'>+</div><div class='add'>+	/* If the device is about to reset or down, avoid unmask</div><div class='add'>+	 * the interrupt and return 0 so NAPI won't reschedule</div><div class='add'>+	 */</div><div class='add'>+	if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &amp;tx_ring-&gt;adapter-&gt;flags))) {</div><div class='add'>+		napi_complete_done(napi, 0);</div><div class='add'>+		ret = 0;</div><div class='add'>+	} else if (budget &gt; work_done) {</div><div class='add'>+		ena_increase_stat(&amp;tx_ring-&gt;tx_stats.napi_comp, 1,</div><div class='add'>+				  &amp;tx_ring-&gt;syncp);</div><div class='add'>+		if (napi_complete_done(napi, work_done))</div><div class='add'>+			ena_unmask_interrupt(tx_ring, NULL);</div><div class='add'>+</div><div class='add'>+		ena_update_ring_numa_node(tx_ring, NULL);</div><div class='add'>+		ret = work_done;</div><div class='add'>+	} else {</div><div class='add'>+		ret = budget;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	u64_stats_update_begin(&amp;tx_ring-&gt;syncp);</div><div class='add'>+	tx_ring-&gt;tx_stats.tx_poll++;</div><div class='add'>+	u64_stats_update_end(&amp;tx_ring-&gt;syncp);</div><div class='add'>+	tx_ring-&gt;tx_stats.last_napi_jiffies = jiffies;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/amazon/ena/ena_xdp.h b/drivers/net/ethernet/amazon/ena/ena_xdp.h<br/>new file mode 100644<br/>index 000000000000..cfd82728486a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amazon/ena/ena_xdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amazon/ena/ena_xdp.h</a></div><div class='hunk'>@@ -0,0 +1,151 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */</div><div class='add'>+/*</div><div class='add'>+ * Copyright 2015-2021 Amazon.com, Inc. or its affiliates. All rights reserved.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef ENA_XDP_H</div><div class='add'>+#define ENA_XDP_H</div><div class='add'>+</div><div class='add'>+#include "ena_netdev.h"</div><div class='add'>+#include &lt;linux/bpf_trace.h&gt;</div><div class='add'>+</div><div class='add'>+/* The max MTU size is configured to be the ethernet frame size without</div><div class='add'>+ * the overhead of the ethernet header, which can have a VLAN header, and</div><div class='add'>+ * a frame check sequence (FCS).</div><div class='add'>+ * The buffer size we share with the device is defined to be ENA_PAGE_SIZE</div><div class='add'>+ */</div><div class='add'>+#define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN -	\</div><div class='add'>+			 VLAN_HLEN - XDP_PACKET_HEADROOM -		\</div><div class='add'>+			 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))</div><div class='add'>+</div><div class='add'>+#define ENA_IS_XDP_INDEX(adapter, index) (((index) &gt;= (adapter)-&gt;xdp_first_ring) &amp;&amp; \</div><div class='add'>+	((index) &lt; (adapter)-&gt;xdp_first_ring + (adapter)-&gt;xdp_num_queues))</div><div class='add'>+</div><div class='add'>+enum ENA_XDP_ACTIONS {</div><div class='add'>+	ENA_XDP_PASS		= 0,</div><div class='add'>+	ENA_XDP_TX		= BIT(0),</div><div class='add'>+	ENA_XDP_REDIRECT	= BIT(1),</div><div class='add'>+	ENA_XDP_DROP		= BIT(2)</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ENA_XDP_FORWARDED (ENA_XDP_TX | ENA_XDP_REDIRECT)</div><div class='add'>+</div><div class='add'>+int ena_setup_and_create_all_xdp_queues(struct ena_adapter *adapter);</div><div class='add'>+void ena_xdp_exchange_program_rx_in_range(struct ena_adapter *adapter,</div><div class='add'>+					  struct bpf_prog *prog,</div><div class='add'>+					  int first, int count);</div><div class='add'>+int ena_xdp_io_poll(struct napi_struct *napi, int budget);</div><div class='add'>+int ena_xdp_xmit_frame(struct ena_ring *tx_ring,</div><div class='add'>+		       struct ena_adapter *adapter,</div><div class='add'>+		       struct xdp_frame *xdpf,</div><div class='add'>+		       int flags);</div><div class='add'>+int ena_xdp_xmit(struct net_device *dev, int n,</div><div class='add'>+		 struct xdp_frame **frames, u32 flags);</div><div class='add'>+int ena_xdp(struct net_device *netdev, struct netdev_bpf *bpf);</div><div class='add'>+int ena_xdp_register_rxq_info(struct ena_ring *rx_ring);</div><div class='add'>+void ena_xdp_unregister_rxq_info(struct ena_ring *rx_ring);</div><div class='add'>+</div><div class='add'>+enum ena_xdp_errors_t {</div><div class='add'>+	ENA_XDP_ALLOWED = 0,</div><div class='add'>+	ENA_XDP_CURRENT_MTU_TOO_LARGE,</div><div class='add'>+	ENA_XDP_NO_ENOUGH_QUEUES,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static inline bool ena_xdp_present(struct ena_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	return !!adapter-&gt;xdp_bpf_prog;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ena_xdp_present_ring(struct ena_ring *ring)</div><div class='add'>+{</div><div class='add'>+	return !!ring-&gt;xdp_bpf_prog;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline bool ena_xdp_legal_queue_count(struct ena_adapter *adapter,</div><div class='add'>+					     u32 queues)</div><div class='add'>+{</div><div class='add'>+	return 2 * queues &lt;= adapter-&gt;max_num_io_queues;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED;</div><div class='add'>+</div><div class='add'>+	if (adapter-&gt;netdev-&gt;mtu &gt; ENA_XDP_MAX_MTU)</div><div class='add'>+		rc = ENA_XDP_CURRENT_MTU_TOO_LARGE;</div><div class='add'>+	else if (!ena_xdp_legal_queue_count(adapter, adapter-&gt;num_io_queues))</div><div class='add'>+		rc = ENA_XDP_NO_ENOUGH_QUEUES;</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline int ena_xdp_execute(struct ena_ring *rx_ring, struct xdp_buff *xdp)</div><div class='add'>+{</div><div class='add'>+	u32 verdict = ENA_XDP_PASS;</div><div class='add'>+	struct bpf_prog *xdp_prog;</div><div class='add'>+	struct ena_ring *xdp_ring;</div><div class='add'>+	struct xdp_frame *xdpf;</div><div class='add'>+	u64 *xdp_stat;</div><div class='add'>+</div><div class='add'>+	xdp_prog = READ_ONCE(rx_ring-&gt;xdp_bpf_prog);</div><div class='add'>+</div><div class='add'>+	verdict = bpf_prog_run_xdp(xdp_prog, xdp);</div><div class='add'>+</div><div class='add'>+	switch (verdict) {</div><div class='add'>+	case XDP_TX:</div><div class='add'>+		xdpf = xdp_convert_buff_to_frame(xdp);</div><div class='add'>+		if (unlikely(!xdpf)) {</div><div class='add'>+			trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='add'>+			xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='add'>+			verdict = ENA_XDP_DROP;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Find xmit queue */</div><div class='add'>+		xdp_ring = rx_ring-&gt;xdp_ring;</div><div class='add'>+</div><div class='add'>+		/* The XDP queues are shared between XDP_TX and XDP_REDIRECT */</div><div class='add'>+		spin_lock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='add'>+</div><div class='add'>+		if (ena_xdp_xmit_frame(xdp_ring, rx_ring-&gt;adapter, xdpf,</div><div class='add'>+				       XDP_XMIT_FLUSH))</div><div class='add'>+			xdp_return_frame(xdpf);</div><div class='add'>+</div><div class='add'>+		spin_unlock(&amp;xdp_ring-&gt;xdp_tx_lock);</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_tx;</div><div class='add'>+		verdict = ENA_XDP_TX;</div><div class='add'>+		break;</div><div class='add'>+	case XDP_REDIRECT:</div><div class='add'>+		if (likely(!xdp_do_redirect(rx_ring-&gt;netdev, xdp, xdp_prog))) {</div><div class='add'>+			xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_redirect;</div><div class='add'>+			verdict = ENA_XDP_REDIRECT;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='add'>+		verdict = ENA_XDP_DROP;</div><div class='add'>+		break;</div><div class='add'>+	case XDP_ABORTED:</div><div class='add'>+		trace_xdp_exception(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_aborted;</div><div class='add'>+		verdict = ENA_XDP_DROP;</div><div class='add'>+		break;</div><div class='add'>+	case XDP_DROP:</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_drop;</div><div class='add'>+		verdict = ENA_XDP_DROP;</div><div class='add'>+		break;</div><div class='add'>+	case XDP_PASS:</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_pass;</div><div class='add'>+		verdict = ENA_XDP_PASS;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		bpf_warn_invalid_xdp_action(rx_ring-&gt;netdev, xdp_prog, verdict);</div><div class='add'>+		xdp_stat = &amp;rx_ring-&gt;rx_stats.xdp_invalid;</div><div class='add'>+		verdict = ENA_XDP_DROP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ena_increase_stat(xdp_stat, 1, &amp;rx_ring-&gt;syncp);</div><div class='add'>+</div><div class='add'>+	return verdict;</div><div class='add'>+}</div><div class='add'>+#endif /* ENA_XDP_H */</div><div class='head'>diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c<br/>index 32fab5e77246..58e7e88aae5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c</a></div><div class='hunk'>@@ -527,47 +527,48 @@ static u32 xgbe_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return ARRAY_SIZE(pdata-&gt;rss_table);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int xgbe_get_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct xgbe_prv_data *pdata = netdev_priv(netdev);</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(pdata-&gt;rss_table); i++)</div><div class='del'>-			indir[i] = XGMAC_GET_BITS(pdata-&gt;rss_table[i],</div><div class='del'>-						  MAC_RSSDR, DMCH);</div><div class='add'>+			rxfh-&gt;indir[i] = XGMAC_GET_BITS(pdata-&gt;rss_table[i],</div><div class='add'>+							MAC_RSSDR, DMCH);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, pdata-&gt;rss_key, sizeof(pdata-&gt;rss_key));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, pdata-&gt;rss_key, sizeof(pdata-&gt;rss_key));</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int xgbe_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int xgbe_set_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct xgbe_prv_data *pdata = netdev_priv(netdev);</div><div class='ctx'> 	struct xgbe_hw_if *hw_if = &amp;pdata-&gt;hw_if;</div><div class='ctx'> 	unsigned int ret;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP) {</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP) {</div><div class='ctx'> 		netdev_err(netdev, "unsupported hash function\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='del'>-		ret = hw_if-&gt;set_rss_lookup_table(pdata, indir);</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='add'>+		ret = hw_if-&gt;set_rss_lookup_table(pdata, rxfh-&gt;indir);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='del'>-		ret = hw_if-&gt;set_rss_hash_key(pdata, key);</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		ret = hw_if-&gt;set_rss_hash_key(pdata, rxfh-&gt;key);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h<br/>index ad136ed493ed..f01a1e566da6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amd/xgbe/xgbe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/amd/xgbe/xgbe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/amd/xgbe/xgbe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/amd/xgbe/xgbe.h</a></div><div class='hunk'>@@ -495,7 +495,7 @@ struct xgbe_ring {</div><div class='ctx'>  * a DMA channel.</div><div class='ctx'>  */</div><div class='ctx'> struct xgbe_channel {</div><div class='del'>-	char name[16];</div><div class='add'>+	char name[20];</div><div class='ctx'> </div><div class='ctx'> 	/* Address of private data area for device */</div><div class='ctx'> 	struct xgbe_prv_data *pdata;</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c<br/>index ac4ea93bd8dd..18a6c8d99fa0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c</a></div><div class='hunk'>@@ -447,8 +447,8 @@ static u32 aq_ethtool_get_rss_key_size(struct net_device *ndev)</div><div class='ctx'> 	return sizeof(cfg-&gt;aq_rss.hash_secret_key);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aq_ethtool_get_rss(struct net_device *ndev, u32 *indir, u8 *key,</div><div class='del'>-			      u8 *hfunc)</div><div class='add'>+static int aq_ethtool_get_rss(struct net_device *ndev,</div><div class='add'>+			      struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct aq_nic_s *aq_nic = netdev_priv(ndev);</div><div class='ctx'> 	struct aq_nic_cfg_s *cfg;</div><div class='hunk'>@@ -456,21 +456,21 @@ static int aq_ethtool_get_rss(struct net_device *ndev, u32 *indir, u8 *key,</div><div class='ctx'> </div><div class='ctx'> 	cfg = aq_nic_get_cfg(aq_nic);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */</div><div class='del'>-	if (indir) {</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; AQ_CFG_RSS_INDIRECTION_TABLE_MAX; i++)</div><div class='del'>-			indir[i] = cfg-&gt;aq_rss.indirection_table[i];</div><div class='add'>+			rxfh-&gt;indir[i] = cfg-&gt;aq_rss.indirection_table[i];</div><div class='ctx'> 	}</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, cfg-&gt;aq_rss.hash_secret_key,</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, cfg-&gt;aq_rss.hash_secret_key,</div><div class='ctx'> 		       sizeof(cfg-&gt;aq_rss.hash_secret_key));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int aq_ethtool_set_rss(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			      const u8 *key, const u8 hfunc)</div><div class='add'>+static int aq_ethtool_set_rss(struct net_device *netdev,</div><div class='add'>+			      struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			      struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct aq_nic_s *aq_nic = netdev_priv(netdev);</div><div class='ctx'> 	struct aq_nic_cfg_s *cfg;</div><div class='hunk'>@@ -482,16 +482,17 @@ static int aq_ethtool_set_rss(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	rss_entries = cfg-&gt;aq_rss.indirection_table_size;</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	/* Fill out the redirection table */</div><div class='del'>-	if (indir)</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='ctx'> 		for (i = 0; i &lt; rss_entries; i++)</div><div class='del'>-			cfg-&gt;aq_rss.indirection_table[i] = indir[i];</div><div class='add'>+			cfg-&gt;aq_rss.indirection_table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 	/* Fill out the rss hash key */</div><div class='del'>-	if (key) {</div><div class='del'>-		memcpy(cfg-&gt;aq_rss.hash_secret_key, key,</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(cfg-&gt;aq_rss.hash_secret_key, rxfh-&gt;key,</div><div class='ctx'> 		       sizeof(cfg-&gt;aq_rss.hash_secret_key));</div><div class='ctx'> 		err = aq_nic-&gt;aq_hw_ops-&gt;hw_rss_hash_set(aq_nic-&gt;aq_hw,</div><div class='ctx'> 			&amp;cfg-&gt;aq_rss);</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c<br/>index 80b44043e6c5..abd4832e4ed2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.c</a></div><div class='hunk'>@@ -553,17 +553,17 @@ void aq_ptp_tx_hwtstamp(struct aq_nic_s *aq_nic, u64 timestamp)</div><div class='ctx'> </div><div class='ctx'> /* aq_ptp_rx_hwtstamp - utility function which checks for RX time stamp</div><div class='ctx'>  * @adapter: pointer to adapter struct</div><div class='del'>- * @skb: particular skb to send timestamp with</div><div class='add'>+ * @shhwtstamps: particular skb_shared_hwtstamps to save timestamp</div><div class='ctx'>  *</div><div class='ctx'>  * if the timestamp is valid, we convert it into the timecounter ns</div><div class='ctx'>  * value, then store that result into the hwtstamps structure which</div><div class='ctx'>  * is passed up the network stack</div><div class='ctx'>  */</div><div class='del'>-static void aq_ptp_rx_hwtstamp(struct aq_ptp_s *aq_ptp, struct sk_buff *skb,</div><div class='add'>+static void aq_ptp_rx_hwtstamp(struct aq_ptp_s *aq_ptp, struct skb_shared_hwtstamps *shhwtstamps,</div><div class='ctx'> 			       u64 timestamp)</div><div class='ctx'> {</div><div class='ctx'> 	timestamp -= atomic_read(&amp;aq_ptp-&gt;offset_ingress);</div><div class='del'>-	aq_ptp_convert_to_hwtstamp(aq_ptp, skb_hwtstamps(skb), timestamp);</div><div class='add'>+	aq_ptp_convert_to_hwtstamp(aq_ptp, shhwtstamps, timestamp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void aq_ptp_hwtstamp_config_get(struct aq_ptp_s *aq_ptp,</div><div class='hunk'>@@ -639,7 +639,7 @@ bool aq_ptp_ring(struct aq_nic_s *aq_nic, struct aq_ring_s *ring)</div><div class='ctx'> 	       &amp;aq_ptp-&gt;ptp_rx == ring || &amp;aq_ptp-&gt;hwts_rx == ring;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct sk_buff *skb, u8 *p,</div><div class='add'>+u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct skb_shared_hwtstamps *shhwtstamps, u8 *p,</div><div class='ctx'> 		      unsigned int len)</div><div class='ctx'> {</div><div class='ctx'> 	struct aq_ptp_s *aq_ptp = aq_nic-&gt;aq_ptp;</div><div class='hunk'>@@ -648,7 +648,7 @@ u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct sk_buff *skb, u8 *p,</div><div class='ctx'> 						   p, len, &amp;timestamp);</div><div class='ctx'> </div><div class='ctx'> 	if (ret &gt; 0)</div><div class='del'>-		aq_ptp_rx_hwtstamp(aq_ptp, skb, timestamp);</div><div class='add'>+		aq_ptp_rx_hwtstamp(aq_ptp, shhwtstamps, timestamp);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -953,8 +953,6 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic)</div><div class='ctx'> {</div><div class='ctx'> 	struct aq_ptp_s *aq_ptp = aq_nic-&gt;aq_ptp;</div><div class='ctx'> 	unsigned int tx_ring_idx, rx_ring_idx;</div><div class='del'>-	struct aq_ring_s *hwts;</div><div class='del'>-	struct aq_ring_s *ring;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!aq_ptp)</div><div class='hunk'>@@ -962,29 +960,23 @@ int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic)</div><div class='ctx'> </div><div class='ctx'> 	tx_ring_idx = aq_ptp_ring_idx(aq_nic-&gt;aq_nic_cfg.tc_mode);</div><div class='ctx'> </div><div class='del'>-	ring = aq_ring_tx_alloc(&amp;aq_ptp-&gt;ptp_tx, aq_nic,</div><div class='del'>-				tx_ring_idx, &amp;aq_nic-&gt;aq_nic_cfg);</div><div class='del'>-	if (!ring) {</div><div class='del'>-		err = -ENOMEM;</div><div class='add'>+	err = aq_ring_tx_alloc(&amp;aq_ptp-&gt;ptp_tx, aq_nic,</div><div class='add'>+			       tx_ring_idx, &amp;aq_nic-&gt;aq_nic_cfg);</div><div class='add'>+	if (err)</div><div class='ctx'> 		goto err_exit;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	rx_ring_idx = aq_ptp_ring_idx(aq_nic-&gt;aq_nic_cfg.tc_mode);</div><div class='ctx'> </div><div class='del'>-	ring = aq_ring_rx_alloc(&amp;aq_ptp-&gt;ptp_rx, aq_nic,</div><div class='del'>-				rx_ring_idx, &amp;aq_nic-&gt;aq_nic_cfg);</div><div class='del'>-	if (!ring) {</div><div class='del'>-		err = -ENOMEM;</div><div class='add'>+	err = aq_ring_rx_alloc(&amp;aq_ptp-&gt;ptp_rx, aq_nic,</div><div class='add'>+			       rx_ring_idx, &amp;aq_nic-&gt;aq_nic_cfg);</div><div class='add'>+	if (err)</div><div class='ctx'> 		goto err_exit_ptp_tx;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	hwts = aq_ring_hwts_rx_alloc(&amp;aq_ptp-&gt;hwts_rx, aq_nic, PTP_HWST_RING_IDX,</div><div class='del'>-				     aq_nic-&gt;aq_nic_cfg.rxds,</div><div class='del'>-				     aq_nic-&gt;aq_nic_cfg.aq_hw_caps-&gt;rxd_size);</div><div class='del'>-	if (!hwts) {</div><div class='del'>-		err = -ENOMEM;</div><div class='add'>+	err = aq_ring_hwts_rx_alloc(&amp;aq_ptp-&gt;hwts_rx, aq_nic, PTP_HWST_RING_IDX,</div><div class='add'>+				    aq_nic-&gt;aq_nic_cfg.rxds,</div><div class='add'>+				    aq_nic-&gt;aq_nic_cfg.aq_hw_caps-&gt;rxd_size);</div><div class='add'>+	if (err)</div><div class='ctx'> 		goto err_exit_ptp_rx;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	err = aq_ptp_skb_ring_init(&amp;aq_ptp-&gt;skb_ring, aq_nic-&gt;aq_nic_cfg.rxds);</div><div class='ctx'> 	if (err != 0) {</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h b/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h<br/>index 28ccb7ca2df9..210b723f2207 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ptp.h</a></div><div class='hunk'>@@ -67,7 +67,7 @@ int aq_ptp_hwtstamp_config_set(struct aq_ptp_s *aq_ptp,</div><div class='ctx'> /* Return either ring is belong to PTP or not*/</div><div class='ctx'> bool aq_ptp_ring(struct aq_nic_s *aq_nic, struct aq_ring_s *ring);</div><div class='ctx'> </div><div class='del'>-u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct sk_buff *skb, u8 *p,</div><div class='add'>+u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct skb_shared_hwtstamps *shhwtstamps, u8 *p,</div><div class='ctx'> 		      unsigned int len);</div><div class='ctx'> </div><div class='ctx'> struct ptp_clock *aq_ptp_get_ptp_clock(struct aq_ptp_s *aq_ptp);</div><div class='hunk'>@@ -143,7 +143,7 @@ static inline bool aq_ptp_ring(struct aq_nic_s *aq_nic, struct aq_ring_s *ring)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic,</div><div class='del'>-				    struct sk_buff *skb, u8 *p,</div><div class='add'>+				    struct skb_shared_hwtstamps *shhwtstamps, u8 *p,</div><div class='ctx'> 				    unsigned int len)</div><div class='ctx'> {</div><div class='ctx'> 	return 0;</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c<br/>index 4de22eed099a..cda8597b4e14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_ring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ring.c</a></div><div class='hunk'>@@ -132,8 +132,8 @@ static int aq_get_rxpages(struct aq_ring_s *self, struct aq_ring_buff_s *rxbuf)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct aq_ring_s *aq_ring_alloc(struct aq_ring_s *self,</div><div class='del'>-				       struct aq_nic_s *aq_nic)</div><div class='add'>+static int aq_ring_alloc(struct aq_ring_s *self,</div><div class='add'>+			 struct aq_nic_s *aq_nic)</div><div class='ctx'> {</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -156,46 +156,29 @@ static struct aq_ring_s *aq_ring_alloc(struct aq_ring_s *self,</div><div class='ctx'> err_exit:</div><div class='ctx'> 	if (err &lt; 0) {</div><div class='ctx'> 		aq_ring_free(self);</div><div class='del'>-		self = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return self;</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,</div><div class='del'>-				   struct aq_nic_s *aq_nic,</div><div class='del'>-				   unsigned int idx,</div><div class='del'>-				   struct aq_nic_cfg_s *aq_nic_cfg)</div><div class='add'>+int aq_ring_tx_alloc(struct aq_ring_s *self,</div><div class='add'>+		     struct aq_nic_s *aq_nic,</div><div class='add'>+		     unsigned int idx,</div><div class='add'>+		     struct aq_nic_cfg_s *aq_nic_cfg)</div><div class='ctx'> {</div><div class='del'>-	int err = 0;</div><div class='del'>-</div><div class='ctx'> 	self-&gt;aq_nic = aq_nic;</div><div class='ctx'> 	self-&gt;idx = idx;</div><div class='ctx'> 	self-&gt;size = aq_nic_cfg-&gt;txds;</div><div class='ctx'> 	self-&gt;dx_size = aq_nic_cfg-&gt;aq_hw_caps-&gt;txd_size;</div><div class='ctx'> </div><div class='del'>-	self = aq_ring_alloc(self, aq_nic);</div><div class='del'>-	if (!self) {</div><div class='del'>-		err = -ENOMEM;</div><div class='del'>-		goto err_exit;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-err_exit:</div><div class='del'>-	if (err &lt; 0) {</div><div class='del'>-		aq_ring_free(self);</div><div class='del'>-		self = NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return self;</div><div class='add'>+	return aq_ring_alloc(self, aq_nic);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,</div><div class='del'>-				   struct aq_nic_s *aq_nic,</div><div class='del'>-				   unsigned int idx,</div><div class='del'>-				   struct aq_nic_cfg_s *aq_nic_cfg)</div><div class='add'>+int aq_ring_rx_alloc(struct aq_ring_s *self,</div><div class='add'>+		     struct aq_nic_s *aq_nic,</div><div class='add'>+		     unsigned int idx,</div><div class='add'>+		     struct aq_nic_cfg_s *aq_nic_cfg)</div><div class='ctx'> {</div><div class='del'>-	int err = 0;</div><div class='del'>-</div><div class='ctx'> 	self-&gt;aq_nic = aq_nic;</div><div class='ctx'> 	self-&gt;idx = idx;</div><div class='ctx'> 	self-&gt;size = aq_nic_cfg-&gt;rxds;</div><div class='hunk'>@@ -217,22 +200,10 @@ struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,</div><div class='ctx'> 		self-&gt;tail_size = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	self = aq_ring_alloc(self, aq_nic);</div><div class='del'>-	if (!self) {</div><div class='del'>-		err = -ENOMEM;</div><div class='del'>-		goto err_exit;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-err_exit:</div><div class='del'>-	if (err &lt; 0) {</div><div class='del'>-		aq_ring_free(self);</div><div class='del'>-		self = NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return self;</div><div class='add'>+	return aq_ring_alloc(self, aq_nic);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct aq_ring_s *</div><div class='add'>+int</div><div class='ctx'> aq_ring_hwts_rx_alloc(struct aq_ring_s *self, struct aq_nic_s *aq_nic,</div><div class='ctx'> 		      unsigned int idx, unsigned int size, unsigned int dx_size)</div><div class='ctx'> {</div><div class='hunk'>@@ -250,10 +221,10 @@ aq_ring_hwts_rx_alloc(struct aq_ring_s *self, struct aq_nic_s *aq_nic,</div><div class='ctx'> 					   GFP_KERNEL);</div><div class='ctx'> 	if (!self-&gt;dx_ring) {</div><div class='ctx'> 		aq_ring_free(self);</div><div class='del'>-		return NULL;</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return self;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int aq_ring_init(struct aq_ring_s *self, const enum atl_ring_type ring_type)</div><div class='hunk'>@@ -647,7 +618,7 @@ static int __aq_ring_rx_clean(struct aq_ring_s *self, struct napi_struct *napi,</div><div class='ctx'> 		}</div><div class='ctx'> 		if (is_ptp_ring)</div><div class='ctx'> 			buff-&gt;len -=</div><div class='del'>-				aq_ptp_extract_ts(self-&gt;aq_nic, skb,</div><div class='add'>+				aq_ptp_extract_ts(self-&gt;aq_nic, skb_hwtstamps(skb),</div><div class='ctx'> 						  aq_buf_vaddr(&amp;buff-&gt;rxdata),</div><div class='ctx'> 						  buff-&gt;len);</div><div class='ctx'> </div><div class='hunk'>@@ -742,6 +713,8 @@ static int __aq_ring_xdp_clean(struct aq_ring_s *rx_ring,</div><div class='ctx'> 		struct aq_ring_buff_s *buff = &amp;rx_ring-&gt;buff_ring[rx_ring-&gt;sw_head];</div><div class='ctx'> 		bool is_ptp_ring = aq_ptp_ring(rx_ring-&gt;aq_nic, rx_ring);</div><div class='ctx'> 		struct aq_ring_buff_s *buff_ = NULL;</div><div class='add'>+		u16 ptp_hwtstamp_len = 0;</div><div class='add'>+		struct skb_shared_hwtstamps shhwtstamps;</div><div class='ctx'> 		struct sk_buff *skb = NULL;</div><div class='ctx'> 		unsigned int next_ = 0U;</div><div class='ctx'> 		struct xdp_buff xdp;</div><div class='hunk'>@@ -810,11 +783,12 @@ static int __aq_ring_xdp_clean(struct aq_ring_s *rx_ring,</div><div class='ctx'> 		hard_start = page_address(buff-&gt;rxdata.page) +</div><div class='ctx'> 			     buff-&gt;rxdata.pg_off - rx_ring-&gt;page_offset;</div><div class='ctx'> </div><div class='del'>-		if (is_ptp_ring)</div><div class='del'>-			buff-&gt;len -=</div><div class='del'>-				aq_ptp_extract_ts(rx_ring-&gt;aq_nic, skb,</div><div class='del'>-						  aq_buf_vaddr(&amp;buff-&gt;rxdata),</div><div class='del'>-						  buff-&gt;len);</div><div class='add'>+		if (is_ptp_ring) {</div><div class='add'>+			ptp_hwtstamp_len = aq_ptp_extract_ts(rx_ring-&gt;aq_nic, &amp;shhwtstamps,</div><div class='add'>+							     aq_buf_vaddr(&amp;buff-&gt;rxdata),</div><div class='add'>+							     buff-&gt;len);</div><div class='add'>+			buff-&gt;len -= ptp_hwtstamp_len;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		xdp_init_buff(&amp;xdp, frame_sz, &amp;rx_ring-&gt;xdp_rxq);</div><div class='ctx'> 		xdp_prepare_buff(&amp;xdp, hard_start, rx_ring-&gt;page_offset,</div><div class='hunk'>@@ -834,6 +808,9 @@ static int __aq_ring_xdp_clean(struct aq_ring_s *rx_ring,</div><div class='ctx'> 		if (IS_ERR(skb) || !skb)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='add'>+		if (ptp_hwtstamp_len &gt; 0)</div><div class='add'>+			*skb_hwtstamps(skb) = shhwtstamps;</div><div class='add'>+</div><div class='ctx'> 		if (buff-&gt;is_vlan)</div><div class='ctx'> 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),</div><div class='ctx'> 					       buff-&gt;vlan_rx_tag);</div><div class='hunk'>@@ -932,11 +909,14 @@ void aq_ring_free(struct aq_ring_s *self)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	kfree(self-&gt;buff_ring);</div><div class='add'>+	self-&gt;buff_ring = NULL;</div><div class='ctx'> </div><div class='del'>-	if (self-&gt;dx_ring)</div><div class='add'>+	if (self-&gt;dx_ring) {</div><div class='ctx'> 		dma_free_coherent(aq_nic_get_dev(self-&gt;aq_nic),</div><div class='ctx'> 				  self-&gt;size * self-&gt;dx_size, self-&gt;dx_ring,</div><div class='ctx'> 				  self-&gt;dx_ring_pa);</div><div class='add'>+		self-&gt;dx_ring = NULL;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> unsigned int aq_ring_fill_stats_data(struct aq_ring_s *self, u64 *data)</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h<br/>index 0a6c34438c1d..52847310740a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ring.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_ring.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_ring.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_ring.h</a></div><div class='hunk'>@@ -183,14 +183,14 @@ static inline unsigned int aq_ring_avail_dx(struct aq_ring_s *self)</div><div class='ctx'> 		self-&gt;sw_head - self-&gt;sw_tail - 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,</div><div class='del'>-				   struct aq_nic_s *aq_nic,</div><div class='del'>-				   unsigned int idx,</div><div class='del'>-				   struct aq_nic_cfg_s *aq_nic_cfg);</div><div class='del'>-struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,</div><div class='del'>-				   struct aq_nic_s *aq_nic,</div><div class='del'>-				   unsigned int idx,</div><div class='del'>-				   struct aq_nic_cfg_s *aq_nic_cfg);</div><div class='add'>+int aq_ring_tx_alloc(struct aq_ring_s *self,</div><div class='add'>+		     struct aq_nic_s *aq_nic,</div><div class='add'>+		     unsigned int idx,</div><div class='add'>+		     struct aq_nic_cfg_s *aq_nic_cfg);</div><div class='add'>+int aq_ring_rx_alloc(struct aq_ring_s *self,</div><div class='add'>+		     struct aq_nic_s *aq_nic,</div><div class='add'>+		     unsigned int idx,</div><div class='add'>+		     struct aq_nic_cfg_s *aq_nic_cfg);</div><div class='ctx'> </div><div class='ctx'> int aq_ring_init(struct aq_ring_s *self, const enum atl_ring_type ring_type);</div><div class='ctx'> void aq_ring_rx_deinit(struct aq_ring_s *self);</div><div class='hunk'>@@ -207,9 +207,9 @@ int aq_ring_rx_clean(struct aq_ring_s *self,</div><div class='ctx'> 		     int budget);</div><div class='ctx'> int aq_ring_rx_fill(struct aq_ring_s *self);</div><div class='ctx'> </div><div class='del'>-struct aq_ring_s *aq_ring_hwts_rx_alloc(struct aq_ring_s *self,</div><div class='del'>-		struct aq_nic_s *aq_nic, unsigned int idx,</div><div class='del'>-		unsigned int size, unsigned int dx_size);</div><div class='add'>+int aq_ring_hwts_rx_alloc(struct aq_ring_s *self,</div><div class='add'>+			  struct aq_nic_s *aq_nic, unsigned int idx,</div><div class='add'>+			  unsigned int size, unsigned int dx_size);</div><div class='ctx'> void aq_ring_hwts_rx_clean(struct aq_ring_s *self, struct aq_nic_s *aq_nic);</div><div class='ctx'> </div><div class='ctx'> unsigned int aq_ring_fill_stats_data(struct aq_ring_s *self, u64 *data);</div><div class='head'>diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c<br/>index f5db1c44e9b9..9769ab4f9bef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_vec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/aquantia/atlantic/aq_vec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/aquantia/atlantic/aq_vec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/aquantia/atlantic/aq_vec.c</a></div><div class='hunk'>@@ -136,35 +136,32 @@ int aq_vec_ring_alloc(struct aq_vec_s *self, struct aq_nic_s *aq_nic,</div><div class='ctx'> 		const unsigned int idx_ring = AQ_NIC_CFG_TCVEC2RING(aq_nic_cfg,</div><div class='ctx'> 								    i, idx);</div><div class='ctx'> </div><div class='del'>-		ring = aq_ring_tx_alloc(&amp;self-&gt;ring[i][AQ_VEC_TX_ID], aq_nic,</div><div class='del'>-					idx_ring, aq_nic_cfg);</div><div class='del'>-		if (!ring) {</div><div class='del'>-			err = -ENOMEM;</div><div class='add'>+		ring = &amp;self-&gt;ring[i][AQ_VEC_TX_ID];</div><div class='add'>+		err = aq_ring_tx_alloc(ring, aq_nic, idx_ring, aq_nic_cfg);</div><div class='add'>+		if (err)</div><div class='ctx'> 			goto err_exit;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		++self-&gt;tx_rings;</div><div class='ctx'> </div><div class='ctx'> 		aq_nic_set_tx_ring(aq_nic, idx_ring, ring);</div><div class='ctx'> </div><div class='del'>-		if (xdp_rxq_info_reg(&amp;self-&gt;ring[i][AQ_VEC_RX_ID].xdp_rxq,</div><div class='add'>+		ring = &amp;self-&gt;ring[i][AQ_VEC_RX_ID];</div><div class='add'>+		if (xdp_rxq_info_reg(&amp;ring-&gt;xdp_rxq,</div><div class='ctx'> 				     aq_nic-&gt;ndev, idx,</div><div class='ctx'> 				     self-&gt;napi.napi_id) &lt; 0) {</div><div class='ctx'> 			err = -ENOMEM;</div><div class='ctx'> 			goto err_exit;</div><div class='ctx'> 		}</div><div class='del'>-		if (xdp_rxq_info_reg_mem_model(&amp;self-&gt;ring[i][AQ_VEC_RX_ID].xdp_rxq,</div><div class='add'>+		if (xdp_rxq_info_reg_mem_model(&amp;ring-&gt;xdp_rxq,</div><div class='ctx'> 					       MEM_TYPE_PAGE_SHARED, NULL) &lt; 0) {</div><div class='del'>-			xdp_rxq_info_unreg(&amp;self-&gt;ring[i][AQ_VEC_RX_ID].xdp_rxq);</div><div class='add'>+			xdp_rxq_info_unreg(&amp;ring-&gt;xdp_rxq);</div><div class='ctx'> 			err = -ENOMEM;</div><div class='ctx'> 			goto err_exit;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ring = aq_ring_rx_alloc(&amp;self-&gt;ring[i][AQ_VEC_RX_ID], aq_nic,</div><div class='del'>-					idx_ring, aq_nic_cfg);</div><div class='del'>-		if (!ring) {</div><div class='del'>-			xdp_rxq_info_unreg(&amp;self-&gt;ring[i][AQ_VEC_RX_ID].xdp_rxq);</div><div class='del'>-			err = -ENOMEM;</div><div class='add'>+		err = aq_ring_rx_alloc(ring, aq_nic, idx_ring, aq_nic_cfg);</div><div class='add'>+		if (err) {</div><div class='add'>+			xdp_rxq_info_unreg(&amp;ring-&gt;xdp_rxq);</div><div class='ctx'> 			goto err_exit;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/asix/ax88796c_main.c b/drivers/net/ethernet/asix/ax88796c_main.c<br/>index e551ffaed20d..11e8996b33d7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/asix/ax88796c_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/asix/ax88796c_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/asix/ax88796c_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/asix/ax88796c_main.c</a></div><div class='hunk'>@@ -284,7 +284,7 @@ ax88796c_tx_fixup(struct net_device *ndev, struct sk_buff_head *q)</div><div class='ctx'> 	ax88796c_proc_tx_hdr(&amp;info, skb-&gt;ip_summed);</div><div class='ctx'> </div><div class='ctx'> 	/* SOP and SEG header */</div><div class='del'>-	memcpy(skb_push(skb, TX_OVERHEAD), &amp;info.sop, TX_OVERHEAD);</div><div class='add'>+	memcpy(skb_push(skb, TX_OVERHEAD), &amp;info.tx_overhead, TX_OVERHEAD);</div><div class='ctx'> </div><div class='ctx'> 	/* Write SPI TXQ header */</div><div class='ctx'> 	memcpy(skb_push(skb, spi_len), ax88796c_tx_cmd_buf, spi_len);</div><div class='head'>diff --git a/drivers/net/ethernet/asix/ax88796c_main.h b/drivers/net/ethernet/asix/ax88796c_main.h<br/>index 4a83c991dcbe..68a09edecab8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/asix/ax88796c_main.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/asix/ax88796c_main.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/asix/ax88796c_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/asix/ax88796c_main.h</a></div><div class='hunk'>@@ -25,7 +25,7 @@</div><div class='ctx'> #define AX88796C_PHY_REGDUMP_LEN	14</div><div class='ctx'> #define AX88796C_PHY_ID			0x10</div><div class='ctx'> </div><div class='del'>-#define TX_OVERHEAD			8</div><div class='add'>+#define TX_OVERHEAD     sizeof_field(struct tx_pkt_info, tx_overhead)</div><div class='ctx'> #define TX_EOP_SIZE			4</div><div class='ctx'> </div><div class='ctx'> #define AX_MCAST_FILTER_SIZE		8</div><div class='hunk'>@@ -549,8 +549,10 @@ struct tx_eop_header {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct tx_pkt_info {</div><div class='del'>-	struct tx_sop_header sop;</div><div class='del'>-	struct tx_segment_header seg;</div><div class='add'>+	struct_group(tx_overhead,</div><div class='add'>+		struct tx_sop_header sop;</div><div class='add'>+		struct tx_segment_header seg;</div><div class='add'>+	);</div><div class='ctx'> 	struct tx_eop_header eop;</div><div class='ctx'> 	u16 pkt_len;</div><div class='ctx'> 	u16 seq_num;</div><div class='head'>diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c<br/>index 5935be190b9e..5f2a6fcba967 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/atheros/atl1e/atl1e_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/atheros/atl1e/atl1e_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/atheros/atl1e/atl1e_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/atheros/atl1e/atl1e_main.c</a></div><div class='hunk'>@@ -866,10 +866,13 @@ static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)</div><div class='ctx'> 		netdev_err(adapter-&gt;netdev, "offset(%d) &gt; ring size(%d) !!\n",</div><div class='ctx'> 			   offset, adapter-&gt;ring_size);</div><div class='ctx'> 		err = -1;</div><div class='del'>-		goto failed;</div><div class='add'>+		goto free_buffer;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='add'>+free_buffer:</div><div class='add'>+	kfree(tx_ring-&gt;tx_buffer);</div><div class='add'>+	tx_ring-&gt;tx_buffer = NULL;</div><div class='ctx'> failed:</div><div class='ctx'> 	if (adapter-&gt;ring_vir_addr != NULL) {</div><div class='ctx'> 		dma_free_coherent(&amp;pdev-&gt;dev, adapter-&gt;ring_size,</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c<br/>index bda3ccc28eca..81d232e6d05f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c</a></div><div class='hunk'>@@ -3486,16 +3486,15 @@ static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return T_ETH_INDIRECTION_TABLE_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int bnx2x_get_rxfh(struct net_device *dev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnx2x *bp = netdev_priv(dev);</div><div class='ctx'> 	u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};</div><div class='ctx'> 	size_t i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Get the current configuration of the RSS indirection table */</div><div class='hunk'>@@ -3511,13 +3510,14 @@ static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='ctx'> 	 * queue.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; T_ETH_INDIRECTION_TABLE_SIZE; i++)</div><div class='del'>-		indir[i] = ind_table[i] - bp-&gt;fp-&gt;cl_id;</div><div class='add'>+		rxfh-&gt;indir[i] = ind_table[i] - bp-&gt;fp-&gt;cl_id;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int bnx2x_set_rxfh(struct net_device *dev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnx2x *bp = netdev_priv(dev);</div><div class='ctx'> 	size_t i;</div><div class='hunk'>@@ -3525,11 +3525,12 @@ static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 	/* We require at least one supported parameter to be changed and no</div><div class='ctx'> 	 * change in any of the unsupported parameters</div><div class='ctx'> 	 */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; T_ETH_INDIRECTION_TABLE_SIZE; i++) {</div><div class='hunk'>@@ -3542,7 +3543,7 @@ static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 		 * align the received table to the Client ID of the leading RSS</div><div class='ctx'> 		 * queue</div><div class='ctx'> 		 */</div><div class='del'>-		bp-&gt;rss_conf_obj.ind_table[i] = indir[i] + bp-&gt;fp-&gt;cl_id;</div><div class='add'>+		bp-&gt;rss_conf_obj.ind_table[i] = rxfh-&gt;indir[i] + bp-&gt;fp-&gt;cl_id;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;state == BNX2X_STATE_OPEN)</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c<br/>index d0359b569afe..0aacd3c6ed5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt.c</a></div><div class='hunk'>@@ -120,6 +120,10 @@ static const struct {</div><div class='ctx'> 	[BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },</div><div class='ctx'> 	[BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },</div><div class='ctx'> 	[BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },</div><div class='add'>+	[BCM57608] = { "Broadcom BCM57608 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb/400Gb Ethernet" },</div><div class='add'>+	[BCM57604] = { "Broadcom BCM57604 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },</div><div class='add'>+	[BCM57602] = { "Broadcom BCM57602 NetXtreme-E 10Gb/25Gb/50Gb/100Gb Ethernet" },</div><div class='add'>+	[BCM57601] = { "Broadcom BCM57601 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb/400Gb Ethernet" },</div><div class='ctx'> 	[BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },</div><div class='ctx'> 	[BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },</div><div class='ctx'> 	[BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },</div><div class='hunk'>@@ -174,6 +178,10 @@ static const struct pci_device_id bnxt_pci_tbl[] = {</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },</div><div class='add'>+	{ PCI_VDEVICE(BROADCOM, 0x1760), .driver_data = BCM57608 },</div><div class='add'>+	{ PCI_VDEVICE(BROADCOM, 0x1761), .driver_data = BCM57604 },</div><div class='add'>+	{ PCI_VDEVICE(BROADCOM, 0x1762), .driver_data = BCM57602 },</div><div class='add'>+	{ PCI_VDEVICE(BROADCOM, 0x1763), .driver_data = BCM57601 },</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR },</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },</div><div class='ctx'> 	{ PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR },</div><div class='hunk'>@@ -254,22 +262,28 @@ static bool bnxt_vf_pciid(enum board_idx idx)</div><div class='ctx'> 		writel(DB_CP_IRQ_DIS_FLAGS, db)</div><div class='ctx'> </div><div class='ctx'> #define BNXT_DB_CQ(db, idx)						\</div><div class='del'>-	writel(DB_CP_FLAGS | RING_CMP(idx), (db)-&gt;doorbell)</div><div class='add'>+	writel(DB_CP_FLAGS | DB_RING_IDX(db, idx), (db)-&gt;doorbell)</div><div class='ctx'> </div><div class='ctx'> #define BNXT_DB_NQ_P5(db, idx)						\</div><div class='del'>-	bnxt_writeq(bp, (db)-&gt;db_key64 | DBR_TYPE_NQ | RING_CMP(idx),	\</div><div class='add'>+	bnxt_writeq(bp, (db)-&gt;db_key64 | DBR_TYPE_NQ | DB_RING_IDX(db, idx),\</div><div class='ctx'> 		    (db)-&gt;doorbell)</div><div class='ctx'> </div><div class='add'>+#define BNXT_DB_NQ_P7(db, idx)						\</div><div class='add'>+	bnxt_writeq(bp, (db)-&gt;db_key64 | DBR_TYPE_NQ_MASK |		\</div><div class='add'>+		    DB_RING_IDX(db, idx), (db)-&gt;doorbell)</div><div class='add'>+</div><div class='ctx'> #define BNXT_DB_CQ_ARM(db, idx)						\</div><div class='del'>-	writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)-&gt;doorbell)</div><div class='add'>+	writel(DB_CP_REARM_FLAGS | DB_RING_IDX(db, idx), (db)-&gt;doorbell)</div><div class='ctx'> </div><div class='ctx'> #define BNXT_DB_NQ_ARM_P5(db, idx)					\</div><div class='del'>-	bnxt_writeq(bp, (db)-&gt;db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\</div><div class='del'>-		    (db)-&gt;doorbell)</div><div class='add'>+	bnxt_writeq(bp, (db)-&gt;db_key64 | DBR_TYPE_NQ_ARM |		\</div><div class='add'>+		    DB_RING_IDX(db, idx), (db)-&gt;doorbell)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P7)</div><div class='add'>+		BNXT_DB_NQ_P7(db, idx);</div><div class='add'>+	else if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		BNXT_DB_NQ_P5(db, idx);</div><div class='ctx'> 	else</div><div class='ctx'> 		BNXT_DB_CQ(db, idx);</div><div class='hunk'>@@ -277,7 +291,7 @@ static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		BNXT_DB_NQ_ARM_P5(db, idx);</div><div class='ctx'> 	else</div><div class='ctx'> 		BNXT_DB_CQ_ARM(db, idx);</div><div class='hunk'>@@ -285,9 +299,9 @@ static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		bnxt_writeq(bp, db-&gt;db_key64 | DBR_TYPE_CQ_ARMALL |</div><div class='del'>-			    RING_CMP(idx), db-&gt;doorbell);</div><div class='add'>+			    DB_RING_IDX(db, idx), db-&gt;doorbell);</div><div class='ctx'> 	else</div><div class='ctx'> 		BNXT_DB_CQ(db, idx);</div><div class='ctx'> }</div><div class='hunk'>@@ -321,7 +335,7 @@ static void bnxt_sched_reset_rxr(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)</div><div class='ctx'> {</div><div class='ctx'> 	if (!rxr-&gt;bnapi-&gt;in_reset) {</div><div class='ctx'> 		rxr-&gt;bnapi-&gt;in_reset = true;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			set_bit(BNXT_RESET_TASK_SP_EVENT, &amp;bp-&gt;sp_event);</div><div class='ctx'> 		else</div><div class='ctx'> 			set_bit(BNXT_RST_RING_SP_EVENT, &amp;bp-&gt;sp_event);</div><div class='hunk'>@@ -331,16 +345,16 @@ static void bnxt_sched_reset_rxr(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,</div><div class='del'>-			  int idx)</div><div class='add'>+			  u16 curr)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_napi *bnapi = txr-&gt;bnapi;</div><div class='ctx'> </div><div class='ctx'> 	if (bnapi-&gt;tx_fault)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	netdev_err(bp-&gt;dev, "Invalid Tx completion (ring:%d tx_pkts:%d cons:%u prod:%u i:%d)",</div><div class='del'>-		   txr-&gt;txq_index, bnapi-&gt;tx_pkts,</div><div class='del'>-		   txr-&gt;tx_cons, txr-&gt;tx_prod, idx);</div><div class='add'>+	netdev_err(bp-&gt;dev, "Invalid Tx completion (ring:%d tx_hw_cons:%u cons:%u prod:%u curr:%u)",</div><div class='add'>+		   txr-&gt;txq_index, txr-&gt;tx_hw_cons,</div><div class='add'>+		   txr-&gt;tx_cons, txr-&gt;tx_prod, curr);</div><div class='ctx'> 	WARN_ON_ONCE(1);</div><div class='ctx'> 	bnapi-&gt;tx_fault = 1;</div><div class='ctx'> 	bnxt_queue_sp_work(bp, BNXT_RESET_TASK_SP_EVENT);</div><div class='hunk'>@@ -381,6 +395,8 @@ static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)</div><div class='ctx'> static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,</div><div class='ctx'> 			     u16 prod)</div><div class='ctx'> {</div><div class='add'>+	/* Sync BD data before updating doorbell */</div><div class='add'>+	wmb();</div><div class='ctx'> 	bnxt_db_write(bp, &amp;txr-&gt;tx_db, prod);</div><div class='ctx'> 	txr-&gt;kick_pending = 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -388,7 +404,7 @@ static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,</div><div class='ctx'> static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='del'>-	struct tx_bd *txbd;</div><div class='add'>+	struct tx_bd *txbd, *txbd0;</div><div class='ctx'> 	struct tx_bd_ext *txbd1;</div><div class='ctx'> 	struct netdev_queue *txq;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -430,11 +446,9 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 	len = skb_headlen(skb);</div><div class='ctx'> 	last_frag = skb_shinfo(skb)-&gt;nr_frags;</div><div class='ctx'> </div><div class='del'>-	txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+	txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> </div><div class='del'>-	txbd-&gt;tx_bd_opaque = prod;</div><div class='del'>-</div><div class='del'>-	tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+	tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 	tx_buf-&gt;skb = skb;</div><div class='ctx'> 	tx_buf-&gt;nr_frags = last_frag;</div><div class='ctx'> </div><div class='hunk'>@@ -519,12 +533,15 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> </div><div class='ctx'> 		txbd-&gt;tx_bd_len_flags_type = tx_push-&gt;tx_bd_len_flags_type;</div><div class='ctx'> 		txbd-&gt;tx_bd_haddr = txr-&gt;data_mapping;</div><div class='add'>+		txbd-&gt;tx_bd_opaque = SET_TX_OPAQUE(bp, txr, prod, 2);</div><div class='ctx'> 		prod = NEXT_TX(prod);</div><div class='del'>-		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+		tx_push-&gt;tx_bd_opaque = txbd-&gt;tx_bd_opaque;</div><div class='add'>+		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> 		memcpy(txbd, tx_push1, sizeof(*txbd));</div><div class='ctx'> 		prod = NEXT_TX(prod);</div><div class='ctx'> 		tx_push-&gt;doorbell =</div><div class='del'>-			cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);</div><div class='add'>+			cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH |</div><div class='add'>+				    DB_RING_IDX(&amp;txr-&gt;tx_db, prod));</div><div class='ctx'> 		WRITE_ONCE(txr-&gt;tx_prod, prod);</div><div class='ctx'> </div><div class='ctx'> 		tx_buf-&gt;is_push = 1;</div><div class='hunk'>@@ -562,19 +579,29 @@ normal_tx:</div><div class='ctx'> 		((last_frag + 2) &lt;&lt; TX_BD_FLAGS_BD_CNT_SHIFT);</div><div class='ctx'> </div><div class='ctx'> 	txbd-&gt;tx_bd_haddr = cpu_to_le64(mapping);</div><div class='add'>+	txbd-&gt;tx_bd_opaque = SET_TX_OPAQUE(bp, txr, prod, 2 + last_frag);</div><div class='ctx'> </div><div class='ctx'> 	prod = NEXT_TX(prod);</div><div class='ctx'> 	txbd1 = (struct tx_bd_ext *)</div><div class='del'>-		&amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+		&amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> </div><div class='ctx'> 	txbd1-&gt;tx_bd_hsize_lflags = lflags;</div><div class='ctx'> 	if (skb_is_gso(skb)) {</div><div class='add'>+		bool udp_gso = !!(skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4);</div><div class='ctx'> 		u32 hdr_len;</div><div class='ctx'> </div><div class='del'>-		if (skb-&gt;encapsulation)</div><div class='del'>-			hdr_len = skb_inner_tcp_all_headers(skb);</div><div class='del'>-		else</div><div class='add'>+		if (skb-&gt;encapsulation) {</div><div class='add'>+			if (udp_gso)</div><div class='add'>+				hdr_len = skb_inner_transport_offset(skb) +</div><div class='add'>+					  sizeof(struct udphdr);</div><div class='add'>+			else</div><div class='add'>+				hdr_len = skb_inner_tcp_all_headers(skb);</div><div class='add'>+		} else if (udp_gso) {</div><div class='add'>+			hdr_len = skb_transport_offset(skb) +</div><div class='add'>+				  sizeof(struct udphdr);</div><div class='add'>+		} else {</div><div class='ctx'> 			hdr_len = skb_tcp_all_headers(skb);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		txbd1-&gt;tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |</div><div class='ctx'> 					TX_BD_FLAGS_T_IPID |</div><div class='hunk'>@@ -601,11 +628,12 @@ normal_tx:</div><div class='ctx'> 	txbd1-&gt;tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);</div><div class='ctx'> 	txbd1-&gt;tx_bd_cfa_action =</div><div class='ctx'> 			cpu_to_le32(cfa_action &lt;&lt; TX_BD_CFA_ACTION_SHIFT);</div><div class='add'>+	txbd0 = txbd;</div><div class='ctx'> 	for (i = 0; i &lt; last_frag; i++) {</div><div class='ctx'> 		skb_frag_t *frag = &amp;skb_shinfo(skb)-&gt;frags[i];</div><div class='ctx'> </div><div class='ctx'> 		prod = NEXT_TX(prod);</div><div class='del'>-		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> </div><div class='ctx'> 		len = skb_frag_size(frag);</div><div class='ctx'> 		mapping = skb_frag_dma_map(&amp;pdev-&gt;dev, frag, 0, len,</div><div class='hunk'>@@ -614,7 +642,7 @@ normal_tx:</div><div class='ctx'> 		if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, mapping)))</div><div class='ctx'> 			goto tx_dma_error;</div><div class='ctx'> </div><div class='del'>-		tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+		tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 		dma_unmap_addr_set(tx_buf, mapping, mapping);</div><div class='ctx'> </div><div class='ctx'> 		txbd-&gt;tx_bd_haddr = cpu_to_le64(mapping);</div><div class='hunk'>@@ -632,22 +660,26 @@ normal_tx:</div><div class='ctx'> </div><div class='ctx'> 	skb_tx_timestamp(skb);</div><div class='ctx'> </div><div class='del'>-	/* Sync BD data before updating doorbell */</div><div class='del'>-	wmb();</div><div class='del'>-</div><div class='ctx'> 	prod = NEXT_TX(prod);</div><div class='ctx'> 	WRITE_ONCE(txr-&gt;tx_prod, prod);</div><div class='ctx'> </div><div class='del'>-	if (!netdev_xmit_more() || netif_xmit_stopped(txq))</div><div class='add'>+	if (!netdev_xmit_more() || netif_xmit_stopped(txq)) {</div><div class='ctx'> 		bnxt_txr_db_kick(bp, txr, prod);</div><div class='del'>-	else</div><div class='add'>+	} else {</div><div class='add'>+		if (free_size &gt;= bp-&gt;tx_wake_thresh)</div><div class='add'>+			txbd0-&gt;tx_bd_len_flags_type |=</div><div class='add'>+				cpu_to_le32(TX_BD_FLAGS_NO_CMPL);</div><div class='ctx'> 		txr-&gt;kick_pending = 1;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> tx_done:</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(bnxt_tx_avail(bp, txr) &lt;= MAX_SKB_FRAGS + 1)) {</div><div class='del'>-		if (netdev_xmit_more() &amp;&amp; !tx_buf-&gt;is_push)</div><div class='add'>+		if (netdev_xmit_more() &amp;&amp; !tx_buf-&gt;is_push) {</div><div class='add'>+			txbd0-&gt;tx_bd_len_flags_type &amp;=</div><div class='add'>+				cpu_to_le32(~TX_BD_FLAGS_NO_CMPL);</div><div class='ctx'> 			bnxt_txr_db_kick(bp, txr, prod);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr),</div><div class='ctx'> 				   bp-&gt;tx_wake_thresh);</div><div class='hunk'>@@ -662,7 +694,7 @@ tx_dma_error:</div><div class='ctx'> </div><div class='ctx'> 	/* start back at beginning and unmap skb */</div><div class='ctx'> 	prod = txr-&gt;tx_prod;</div><div class='del'>-	tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+	tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 	dma_unmap_single(&amp;pdev-&gt;dev, dma_unmap_addr(tx_buf, mapping),</div><div class='ctx'> 			 skb_headlen(skb), DMA_TO_DEVICE);</div><div class='ctx'> 	prod = NEXT_TX(prod);</div><div class='hunk'>@@ -670,7 +702,7 @@ tx_dma_error:</div><div class='ctx'> 	/* unmap remaining mapped pages */</div><div class='ctx'> 	for (i = 0; i &lt; last_frag; i++) {</div><div class='ctx'> 		prod = NEXT_TX(prod);</div><div class='del'>-		tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+		tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 		dma_unmap_page(&amp;pdev-&gt;dev, dma_unmap_addr(tx_buf, mapping),</div><div class='ctx'> 			       skb_frag_size(&amp;skb_shinfo(skb)-&gt;frags[i]),</div><div class='ctx'> 			       DMA_TO_DEVICE);</div><div class='hunk'>@@ -686,31 +718,32 @@ tx_kick_pending:</div><div class='ctx'> 	return NETDEV_TX_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='add'>+static void __bnxt_tx_int(struct bnxt *bp, struct bnxt_tx_ring_info *txr,</div><div class='add'>+			  int budget)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring;</div><div class='ctx'> 	struct netdev_queue *txq = netdev_get_tx_queue(bp-&gt;dev, txr-&gt;txq_index);</div><div class='del'>-	u16 cons = txr-&gt;tx_cons;</div><div class='ctx'> 	struct pci_dev *pdev = bp-&gt;pdev;</div><div class='del'>-	int nr_pkts = bnapi-&gt;tx_pkts;</div><div class='del'>-	int i;</div><div class='add'>+	u16 hw_cons = txr-&gt;tx_hw_cons;</div><div class='ctx'> 	unsigned int tx_bytes = 0;</div><div class='add'>+	u16 cons = txr-&gt;tx_cons;</div><div class='add'>+	int tx_pkts = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; nr_pkts; i++) {</div><div class='add'>+	while (RING_TX(bp, cons) != hw_cons) {</div><div class='ctx'> 		struct bnxt_sw_tx_bd *tx_buf;</div><div class='ctx'> 		struct sk_buff *skb;</div><div class='ctx'> 		int j, last;</div><div class='ctx'> </div><div class='del'>-		tx_buf = &amp;txr-&gt;tx_buf_ring[cons];</div><div class='add'>+		tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, cons)];</div><div class='ctx'> 		cons = NEXT_TX(cons);</div><div class='ctx'> 		skb = tx_buf-&gt;skb;</div><div class='ctx'> 		tx_buf-&gt;skb = NULL;</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(!skb)) {</div><div class='del'>-			bnxt_sched_reset_txr(bp, txr, i);</div><div class='add'>+			bnxt_sched_reset_txr(bp, txr, cons);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		tx_pkts++;</div><div class='ctx'> 		tx_bytes += skb-&gt;len;</div><div class='ctx'> </div><div class='ctx'> 		if (tx_buf-&gt;is_push) {</div><div class='hunk'>@@ -724,7 +757,7 @@ static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; last; j++) {</div><div class='ctx'> 			cons = NEXT_TX(cons);</div><div class='del'>-			tx_buf = &amp;txr-&gt;tx_buf_ring[cons];</div><div class='add'>+			tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, cons)];</div><div class='ctx'> 			dma_unmap_page(</div><div class='ctx'> 				&amp;pdev-&gt;dev,</div><div class='ctx'> 				dma_unmap_addr(tx_buf, mapping),</div><div class='hunk'>@@ -732,7 +765,7 @@ static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='ctx'> 				DMA_TO_DEVICE);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (unlikely(skb_shinfo(skb)-&gt;tx_flags &amp; SKBTX_IN_PROGRESS)) {</div><div class='del'>-			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+			if (BNXT_CHIP_P5(bp)) {</div><div class='ctx'> 				/* PTP worker takes ownership of the skb */</div><div class='ctx'> 				if (!bnxt_get_tx_ts_p5(bp, skb))</div><div class='ctx'> 					skb = NULL;</div><div class='hunk'>@@ -747,14 +780,25 @@ next_tx_int:</div><div class='ctx'> 		dev_consume_skb_any(skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bnapi-&gt;tx_pkts = 0;</div><div class='ctx'> 	WRITE_ONCE(txr-&gt;tx_cons, cons);</div><div class='ctx'> </div><div class='del'>-	__netif_txq_completed_wake(txq, nr_pkts, tx_bytes,</div><div class='add'>+	__netif_txq_completed_wake(txq, tx_pkts, tx_bytes,</div><div class='ctx'> 				   bnxt_tx_avail(bp, txr), bp-&gt;tx_wake_thresh,</div><div class='ctx'> 				   READ_ONCE(txr-&gt;dev_state) == BNXT_DEV_STATE_CLOSING);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_tx_ring_info *txr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	bnxt_for_each_napi_tx(i, bnapi, txr) {</div><div class='add'>+		if (txr-&gt;tx_hw_cons != RING_TX(bp, txr-&gt;tx_cons))</div><div class='add'>+			__bnxt_tx_int(bp, txr, budget);</div><div class='add'>+	}</div><div class='add'>+	bnapi-&gt;events &amp;= ~BNXT_TX_CMP_EVENT;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,</div><div class='ctx'> 					 struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 					 unsigned int *offset,</div><div class='hunk'>@@ -803,8 +847,8 @@ static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping,</div><div class='ctx'> int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 		       u16 prod, gfp_t gfp)</div><div class='ctx'> {</div><div class='del'>-	struct rx_bd *rxbd = &amp;rxr-&gt;rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];</div><div class='del'>-	struct bnxt_sw_rx_bd *rx_buf = &amp;rxr-&gt;rx_buf_ring[prod];</div><div class='add'>+	struct rx_bd *rxbd = &amp;rxr-&gt;rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];</div><div class='add'>+	struct bnxt_sw_rx_bd *rx_buf = &amp;rxr-&gt;rx_buf_ring[RING_RX(bp, prod)];</div><div class='ctx'> 	dma_addr_t mapping;</div><div class='ctx'> </div><div class='ctx'> 	if (BNXT_RX_PAGE_MODE(bp)) {</div><div class='hunk'>@@ -837,9 +881,10 @@ void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	u16 prod = rxr-&gt;rx_prod;</div><div class='ctx'> 	struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;</div><div class='add'>+	struct bnxt *bp = rxr-&gt;bnapi-&gt;bp;</div><div class='ctx'> 	struct rx_bd *cons_bd, *prod_bd;</div><div class='ctx'> </div><div class='del'>-	prod_rx_buf = &amp;rxr-&gt;rx_buf_ring[prod];</div><div class='add'>+	prod_rx_buf = &amp;rxr-&gt;rx_buf_ring[RING_RX(bp, prod)];</div><div class='ctx'> 	cons_rx_buf = &amp;rxr-&gt;rx_buf_ring[cons];</div><div class='ctx'> </div><div class='ctx'> 	prod_rx_buf-&gt;data = data;</div><div class='hunk'>@@ -847,8 +892,8 @@ void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)</div><div class='ctx'> </div><div class='ctx'> 	prod_rx_buf-&gt;mapping = cons_rx_buf-&gt;mapping;</div><div class='ctx'> </div><div class='del'>-	prod_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];</div><div class='del'>-	cons_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];</div><div class='add'>+	prod_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];</div><div class='add'>+	cons_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(bp, cons)][RX_IDX(cons)];</div><div class='ctx'> </div><div class='ctx'> 	prod_bd-&gt;rx_bd_haddr = cons_bd-&gt;rx_bd_haddr;</div><div class='ctx'> }</div><div class='hunk'>@@ -868,7 +913,7 @@ static inline int bnxt_alloc_rx_page(struct bnxt *bp,</div><div class='ctx'> 				     u16 prod, gfp_t gfp)</div><div class='ctx'> {</div><div class='ctx'> 	struct rx_bd *rxbd =</div><div class='del'>-		&amp;rxr-&gt;rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];</div><div class='add'>+		&amp;rxr-&gt;rx_agg_desc_ring[RX_AGG_RING(bp, prod)][RX_IDX(prod)];</div><div class='ctx'> 	struct bnxt_sw_rx_agg_bd *rx_agg_buf;</div><div class='ctx'> 	struct page *page;</div><div class='ctx'> 	dma_addr_t mapping;</div><div class='hunk'>@@ -885,7 +930,7 @@ static inline int bnxt_alloc_rx_page(struct bnxt *bp,</div><div class='ctx'> </div><div class='ctx'> 	__set_bit(sw_prod, rxr-&gt;rx_agg_bmap);</div><div class='ctx'> 	rx_agg_buf = &amp;rxr-&gt;rx_agg_ring[sw_prod];</div><div class='del'>-	rxr-&gt;rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);</div><div class='add'>+	rxr-&gt;rx_sw_agg_prod = RING_RX_AGG(bp, NEXT_RX_AGG(sw_prod));</div><div class='ctx'> </div><div class='ctx'> 	rx_agg_buf-&gt;page = page;</div><div class='ctx'> 	rx_agg_buf-&gt;offset = offset;</div><div class='hunk'>@@ -927,7 +972,7 @@ static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,</div><div class='ctx'> 	bool p5_tpa = false;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp; tpa)</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp; tpa)</div><div class='ctx'> 		p5_tpa = true;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; agg_bufs; i++) {</div><div class='hunk'>@@ -961,13 +1006,13 @@ static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,</div><div class='ctx'> </div><div class='ctx'> 		prod_rx_buf-&gt;mapping = cons_rx_buf-&gt;mapping;</div><div class='ctx'> </div><div class='del'>-		prod_bd = &amp;rxr-&gt;rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];</div><div class='add'>+		prod_bd = &amp;rxr-&gt;rx_agg_desc_ring[RX_AGG_RING(bp, prod)][RX_IDX(prod)];</div><div class='ctx'> </div><div class='ctx'> 		prod_bd-&gt;rx_bd_haddr = cpu_to_le64(cons_rx_buf-&gt;mapping);</div><div class='ctx'> 		prod_bd-&gt;rx_bd_opaque = sw_prod;</div><div class='ctx'> </div><div class='ctx'> 		prod = NEXT_RX_AGG(prod);</div><div class='del'>-		sw_prod = NEXT_RX_AGG(sw_prod);</div><div class='add'>+		sw_prod = RING_RX_AGG(bp, NEXT_RX_AGG(sw_prod));</div><div class='ctx'> 	}</div><div class='ctx'> 	rxr-&gt;rx_agg_prod = prod;</div><div class='ctx'> 	rxr-&gt;rx_sw_agg_prod = sw_prod;</div><div class='hunk'>@@ -1094,7 +1139,7 @@ static u32 __bnxt_rx_agg_pages(struct bnxt *bp,</div><div class='ctx'> 	u32 i, total_frag_len = 0;</div><div class='ctx'> 	bool p5_tpa = false;</div><div class='ctx'> </div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp; tpa)</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp; tpa)</div><div class='ctx'> 		p5_tpa = true;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; agg_bufs; i++) {</div><div class='hunk'>@@ -1249,7 +1294,7 @@ static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	} else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {</div><div class='ctx'> 		struct rx_tpa_end_cmp *tpa_end = cmp;</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			return 0;</div><div class='ctx'> </div><div class='ctx'> 		agg_bufs = TPA_END_AGG_BUFS(tpa_end);</div><div class='hunk'>@@ -1290,8 +1335,39 @@ static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)</div><div class='ctx'> 	return map-&gt;agg_id_tbl[agg_id];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void bnxt_tpa_metadata(struct bnxt_tpa_info *tpa_info,</div><div class='add'>+			      struct rx_tpa_start_cmp *tpa_start,</div><div class='add'>+			      struct rx_tpa_start_cmp_ext *tpa_start1)</div><div class='add'>+{</div><div class='add'>+	tpa_info-&gt;cfa_code_valid = 1;</div><div class='add'>+	tpa_info-&gt;cfa_code = TPA_START_CFA_CODE(tpa_start1);</div><div class='add'>+	tpa_info-&gt;vlan_valid = 0;</div><div class='add'>+	if (tpa_info-&gt;flags2 &amp; RX_CMP_FLAGS2_META_FORMAT_VLAN) {</div><div class='add'>+		tpa_info-&gt;vlan_valid = 1;</div><div class='add'>+		tpa_info-&gt;metadata =</div><div class='add'>+			le32_to_cpu(tpa_start1-&gt;rx_tpa_start_cmp_metadata);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void bnxt_tpa_metadata_v2(struct bnxt_tpa_info *tpa_info,</div><div class='add'>+				 struct rx_tpa_start_cmp *tpa_start,</div><div class='add'>+				 struct rx_tpa_start_cmp_ext *tpa_start1)</div><div class='add'>+{</div><div class='add'>+	tpa_info-&gt;vlan_valid = 0;</div><div class='add'>+	if (TPA_START_VLAN_VALID(tpa_start)) {</div><div class='add'>+		u32 tpid_sel = TPA_START_VLAN_TPID_SEL(tpa_start);</div><div class='add'>+		u32 vlan_proto = ETH_P_8021Q;</div><div class='add'>+</div><div class='add'>+		tpa_info-&gt;vlan_valid = 1;</div><div class='add'>+		if (tpid_sel == RX_TPA_START_METADATA1_TPID_8021AD)</div><div class='add'>+			vlan_proto = ETH_P_8021AD;</div><div class='add'>+		tpa_info-&gt;metadata = vlan_proto &lt;&lt; 16 |</div><div class='add'>+				     TPA_START_METADATA0_TCI(tpa_start1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='del'>-			   struct rx_tpa_start_cmp *tpa_start,</div><div class='add'>+			   u8 cmp_type, struct rx_tpa_start_cmp *tpa_start,</div><div class='ctx'> 			   struct rx_tpa_start_cmp_ext *tpa_start1)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;</div><div class='hunk'>@@ -1300,7 +1376,7 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 	struct rx_bd *prod_bd;</div><div class='ctx'> 	dma_addr_t mapping;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		agg_id = TPA_START_AGG_ID_P5(tpa_start);</div><div class='ctx'> 		agg_id = bnxt_alloc_agg_idx(rxr, agg_id);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1309,7 +1385,7 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 	cons = tpa_start-&gt;rx_tpa_start_cmp_opaque;</div><div class='ctx'> 	prod = rxr-&gt;rx_prod;</div><div class='ctx'> 	cons_rx_buf = &amp;rxr-&gt;rx_buf_ring[cons];</div><div class='del'>-	prod_rx_buf = &amp;rxr-&gt;rx_buf_ring[prod];</div><div class='add'>+	prod_rx_buf = &amp;rxr-&gt;rx_buf_ring[RING_RX(bp, prod)];</div><div class='ctx'> 	tpa_info = &amp;rxr-&gt;rx_tpa[agg_id];</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(cons != rxr-&gt;rx_next_cons ||</div><div class='hunk'>@@ -1320,17 +1396,13 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 		bnxt_sched_reset_rxr(bp, rxr);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='del'>-	/* Store cfa_code in tpa_info to use in tpa_end</div><div class='del'>-	 * completion processing.</div><div class='del'>-	 */</div><div class='del'>-	tpa_info-&gt;cfa_code = TPA_START_CFA_CODE(tpa_start1);</div><div class='ctx'> 	prod_rx_buf-&gt;data = tpa_info-&gt;data;</div><div class='ctx'> 	prod_rx_buf-&gt;data_ptr = tpa_info-&gt;data_ptr;</div><div class='ctx'> </div><div class='ctx'> 	mapping = tpa_info-&gt;mapping;</div><div class='ctx'> 	prod_rx_buf-&gt;mapping = mapping;</div><div class='ctx'> </div><div class='del'>-	prod_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];</div><div class='add'>+	prod_bd = &amp;rxr-&gt;rx_desc_ring[RX_RING(bp, prod)][RX_IDX(prod)];</div><div class='ctx'> </div><div class='ctx'> 	prod_bd-&gt;rx_bd_haddr = cpu_to_le64(mapping);</div><div class='ctx'> </div><div class='hunk'>@@ -1343,12 +1415,13 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 		le32_to_cpu(tpa_start-&gt;rx_tpa_start_cmp_len_flags_type) &gt;&gt;</div><div class='ctx'> 				RX_TPA_START_CMP_LEN_SHIFT;</div><div class='ctx'> 	if (likely(TPA_START_HASH_VALID(tpa_start))) {</div><div class='del'>-		u32 hash_type = TPA_START_HASH_TYPE(tpa_start);</div><div class='del'>-</div><div class='ctx'> 		tpa_info-&gt;hash_type = PKT_HASH_TYPE_L4;</div><div class='ctx'> 		tpa_info-&gt;gso_type = SKB_GSO_TCPV4;</div><div class='add'>+		if (TPA_START_IS_IPV6(tpa_start1))</div><div class='add'>+			tpa_info-&gt;gso_type = SKB_GSO_TCPV6;</div><div class='ctx'> 		/* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */</div><div class='del'>-		if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))</div><div class='add'>+		else if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP &amp;&amp;</div><div class='add'>+			 TPA_START_HASH_TYPE(tpa_start) == 3)</div><div class='ctx'> 			tpa_info-&gt;gso_type = SKB_GSO_TCPV6;</div><div class='ctx'> 		tpa_info-&gt;rss_hash =</div><div class='ctx'> 			le32_to_cpu(tpa_start-&gt;rx_tpa_start_cmp_rss_hash);</div><div class='hunk'>@@ -1358,13 +1431,16 @@ static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> 		netif_warn(bp, rx_err, bp-&gt;dev, "TPA packet without valid hash\n");</div><div class='ctx'> 	}</div><div class='ctx'> 	tpa_info-&gt;flags2 = le32_to_cpu(tpa_start1-&gt;rx_tpa_start_cmp_flags2);</div><div class='del'>-	tpa_info-&gt;metadata = le32_to_cpu(tpa_start1-&gt;rx_tpa_start_cmp_metadata);</div><div class='ctx'> 	tpa_info-&gt;hdr_info = le32_to_cpu(tpa_start1-&gt;rx_tpa_start_cmp_hdr_info);</div><div class='add'>+	if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP)</div><div class='add'>+		bnxt_tpa_metadata(tpa_info, tpa_start, tpa_start1);</div><div class='add'>+	else</div><div class='add'>+		bnxt_tpa_metadata_v2(tpa_info, tpa_start, tpa_start1);</div><div class='ctx'> 	tpa_info-&gt;agg_count = 0;</div><div class='ctx'> </div><div class='ctx'> 	rxr-&gt;rx_prod = NEXT_RX(prod);</div><div class='del'>-	cons = NEXT_RX(cons);</div><div class='del'>-	rxr-&gt;rx_next_cons = NEXT_RX(cons);</div><div class='add'>+	cons = RING_RX(bp, NEXT_RX(cons));</div><div class='add'>+	rxr-&gt;rx_next_cons = RING_RX(bp, NEXT_RX(cons));</div><div class='ctx'> 	cons_rx_buf = &amp;rxr-&gt;rx_buf_ring[cons];</div><div class='ctx'> </div><div class='ctx'> 	bnxt_reuse_rx_data(rxr, cons, cons_rx_buf-&gt;data);</div><div class='hunk'>@@ -1563,7 +1639,7 @@ static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,</div><div class='ctx'> 	skb_shinfo(skb)-&gt;gso_size =</div><div class='ctx'> 		le32_to_cpu(tpa_end1-&gt;rx_tpa_end_cmp_seg_len);</div><div class='ctx'> 	skb_shinfo(skb)-&gt;gso_type = tpa_info-&gt;gso_type;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);</div><div class='ctx'> 	else</div><div class='ctx'> 		payload_off = TPA_END_PAYLOAD_OFF(tpa_end);</div><div class='hunk'>@@ -1594,6 +1670,7 @@ static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_napi *bnapi = cpr-&gt;bnapi;</div><div class='ctx'> 	struct bnxt_rx_ring_info *rxr = bnapi-&gt;rx_ring;</div><div class='add'>+	struct net_device *dev = bp-&gt;dev;</div><div class='ctx'> 	u8 *data_ptr, agg_bufs;</div><div class='ctx'> 	unsigned int len;</div><div class='ctx'> 	struct bnxt_tpa_info *tpa_info;</div><div class='hunk'>@@ -1611,7 +1688,7 @@ static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		agg_id = TPA_END_AGG_ID_P5(tpa_end);</div><div class='ctx'> 		agg_id = bnxt_lookup_agg_idx(rxr, agg_id);</div><div class='ctx'> 		agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);</div><div class='hunk'>@@ -1700,14 +1777,15 @@ static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	skb-&gt;protocol =</div><div class='del'>-		eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info-&gt;cfa_code));</div><div class='add'>+	if (tpa_info-&gt;cfa_code_valid)</div><div class='add'>+		dev = bnxt_get_pkt_dev(bp, tpa_info-&gt;cfa_code);</div><div class='add'>+	skb-&gt;protocol = eth_type_trans(skb, dev);</div><div class='ctx'> </div><div class='ctx'> 	if (tpa_info-&gt;hash_type != PKT_HASH_TYPE_NONE)</div><div class='ctx'> 		skb_set_hash(skb, tpa_info-&gt;rss_hash, tpa_info-&gt;hash_type);</div><div class='ctx'> </div><div class='del'>-	if ((tpa_info-&gt;flags2 &amp; RX_CMP_FLAGS2_META_FORMAT_VLAN) &amp;&amp;</div><div class='del'>-	    (skb-&gt;dev-&gt;features &amp; BNXT_HW_FEATURE_VLAN_ALL_RX)) {</div><div class='add'>+	if (tpa_info-&gt;vlan_valid &amp;&amp;</div><div class='add'>+	    (dev-&gt;features &amp; BNXT_HW_FEATURE_VLAN_ALL_RX)) {</div><div class='ctx'> 		__be16 vlan_proto = htons(tpa_info-&gt;metadata &gt;&gt;</div><div class='ctx'> 					  RX_CMP_FLAGS2_METADATA_TPID_SFT);</div><div class='ctx'> 		u16 vtag = tpa_info-&gt;metadata &amp; RX_CMP_FLAGS2_METADATA_TCI_MASK;</div><div class='hunk'>@@ -1748,16 +1826,90 @@ static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,</div><div class='ctx'> static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='ctx'> 			     struct sk_buff *skb)</div><div class='ctx'> {</div><div class='add'>+	skb_mark_for_recycle(skb);</div><div class='add'>+</div><div class='ctx'> 	if (skb-&gt;dev != bp-&gt;dev) {</div><div class='ctx'> 		/* this packet belongs to a vf-rep */</div><div class='ctx'> 		bnxt_vf_rep_rx(bp, skb);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	skb_record_rx_queue(skb, bnapi-&gt;index);</div><div class='del'>-	skb_mark_for_recycle(skb);</div><div class='ctx'> 	napi_gro_receive(&amp;bnapi-&gt;napi, skb);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool bnxt_rx_ts_valid(struct bnxt *bp, u32 flags,</div><div class='add'>+			     struct rx_cmp_ext *rxcmp1, u32 *cmpl_ts)</div><div class='add'>+{</div><div class='add'>+	u32 ts = le32_to_cpu(rxcmp1-&gt;rx_cmp_timestamp);</div><div class='add'>+</div><div class='add'>+	if (BNXT_PTP_RX_TS_VALID(flags))</div><div class='add'>+		goto ts_valid;</div><div class='add'>+	if (!bp-&gt;ptp_all_rx_tstamp || !ts || !BNXT_ALL_RX_TS_VALID(flags))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+ts_valid:</div><div class='add'>+	*cmpl_ts = ts;</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct sk_buff *bnxt_rx_vlan(struct sk_buff *skb, u8 cmp_type,</div><div class='add'>+				    struct rx_cmp *rxcmp,</div><div class='add'>+				    struct rx_cmp_ext *rxcmp1)</div><div class='add'>+{</div><div class='add'>+	__be16 vlan_proto;</div><div class='add'>+	u16 vtag;</div><div class='add'>+</div><div class='add'>+	if (cmp_type == CMP_TYPE_RX_L2_CMP) {</div><div class='add'>+		__le32 flags2 = rxcmp1-&gt;rx_cmp_flags2;</div><div class='add'>+		u32 meta_data;</div><div class='add'>+</div><div class='add'>+		if (!(flags2 &amp; cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)))</div><div class='add'>+			return skb;</div><div class='add'>+</div><div class='add'>+		meta_data = le32_to_cpu(rxcmp1-&gt;rx_cmp_meta_data);</div><div class='add'>+		vtag = meta_data &amp; RX_CMP_FLAGS2_METADATA_TCI_MASK;</div><div class='add'>+		vlan_proto = htons(meta_data &gt;&gt; RX_CMP_FLAGS2_METADATA_TPID_SFT);</div><div class='add'>+		if (eth_type_vlan(vlan_proto))</div><div class='add'>+			__vlan_hwaccel_put_tag(skb, vlan_proto, vtag);</div><div class='add'>+		else</div><div class='add'>+			goto vlan_err;</div><div class='add'>+	} else if (cmp_type == CMP_TYPE_RX_L2_V3_CMP) {</div><div class='add'>+		if (RX_CMP_VLAN_VALID(rxcmp)) {</div><div class='add'>+			u32 tpid_sel = RX_CMP_VLAN_TPID_SEL(rxcmp);</div><div class='add'>+</div><div class='add'>+			if (tpid_sel == RX_CMP_METADATA1_TPID_8021Q)</div><div class='add'>+				vlan_proto = htons(ETH_P_8021Q);</div><div class='add'>+			else if (tpid_sel == RX_CMP_METADATA1_TPID_8021AD)</div><div class='add'>+				vlan_proto = htons(ETH_P_8021AD);</div><div class='add'>+			else</div><div class='add'>+				goto vlan_err;</div><div class='add'>+			vtag = RX_CMP_METADATA0_TCI(rxcmp1);</div><div class='add'>+			__vlan_hwaccel_put_tag(skb, vlan_proto, vtag);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return skb;</div><div class='add'>+vlan_err:</div><div class='add'>+	dev_kfree_skb(skb);</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static enum pkt_hash_types bnxt_rss_ext_op(struct bnxt *bp,</div><div class='add'>+					   struct rx_cmp *rxcmp)</div><div class='add'>+{</div><div class='add'>+	u8 ext_op;</div><div class='add'>+</div><div class='add'>+	ext_op = RX_CMP_V3_HASH_TYPE(bp, rxcmp);</div><div class='add'>+	switch (ext_op) {</div><div class='add'>+	case EXT_OP_INNER_4:</div><div class='add'>+	case EXT_OP_OUTER_4:</div><div class='add'>+	case EXT_OP_INNFL_3:</div><div class='add'>+	case EXT_OP_OUTFL_3:</div><div class='add'>+		return PKT_HASH_TYPE_L4;</div><div class='add'>+	default:</div><div class='add'>+		return PKT_HASH_TYPE_L3;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* returns the following:</div><div class='ctx'>  * 1       - 1 packet successfully received</div><div class='ctx'>  * 0       - successful TPA_START, packet not completed yet</div><div class='hunk'>@@ -1774,7 +1926,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	struct rx_cmp *rxcmp;</div><div class='ctx'> 	struct rx_cmp_ext *rxcmp1;</div><div class='ctx'> 	u32 tmp_raw_cons = *raw_cons;</div><div class='del'>-	u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);</div><div class='add'>+	u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);</div><div class='ctx'> 	struct bnxt_sw_rx_bd *rx_buf;</div><div class='ctx'> 	unsigned int len;</div><div class='ctx'> 	u8 *data_ptr, agg_bufs, cmp_type;</div><div class='hunk'>@@ -1783,6 +1935,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	struct xdp_buff xdp;</div><div class='ctx'> 	u32 flags, misc;</div><div class='add'>+	u32 cmpl_ts;</div><div class='ctx'> 	void *data;</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1810,8 +1963,10 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	dma_rmb();</div><div class='ctx'> 	prod = rxr-&gt;rx_prod;</div><div class='ctx'> </div><div class='del'>-	if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {</div><div class='del'>-		bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,</div><div class='add'>+	if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP ||</div><div class='add'>+	    cmp_type == CMP_TYPE_RX_L2_TPA_START_V3_CMP) {</div><div class='add'>+		bnxt_tpa_start(bp, rxr, cmp_type,</div><div class='add'>+			       (struct rx_tpa_start_cmp *)rxcmp,</div><div class='ctx'> 			       (struct rx_tpa_start_cmp_ext *)rxcmp1);</div><div class='ctx'> </div><div class='ctx'> 		*event |= BNXT_RX_EVENT;</div><div class='hunk'>@@ -1876,7 +2031,7 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 		rc = -EIO;</div><div class='ctx'> 		if (rx_err &amp; RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {</div><div class='ctx'> 			bnapi-&gt;cp_ring.sw_stats.rx.rx_buf_errors++;</div><div class='del'>-			if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp;</div><div class='add'>+			if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp;</div><div class='ctx'> 			    !(bp-&gt;fw_cap &amp; BNXT_FW_CAP_RING_MONITOR)) {</div><div class='ctx'> 				netdev_warn_once(bp-&gt;dev, "RX buffer error %x\n",</div><div class='ctx'> 						 rx_err);</div><div class='hunk'>@@ -1964,32 +2119,32 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (RX_CMP_HASH_VALID(rxcmp)) {</div><div class='del'>-		u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);</div><div class='del'>-		enum pkt_hash_types type = PKT_HASH_TYPE_L4;</div><div class='add'>+		enum pkt_hash_types type;</div><div class='ctx'> </div><div class='del'>-		/* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */</div><div class='del'>-		if (hash_type != 1 &amp;&amp; hash_type != 3)</div><div class='del'>-			type = PKT_HASH_TYPE_L3;</div><div class='add'>+		if (cmp_type == CMP_TYPE_RX_L2_V3_CMP) {</div><div class='add'>+			type = bnxt_rss_ext_op(bp, rxcmp);</div><div class='add'>+		} else {</div><div class='add'>+			u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);</div><div class='add'>+</div><div class='add'>+			/* RSS profiles 1 and 3 with extract code 0 for inner</div><div class='add'>+			 * 4-tuple</div><div class='add'>+			 */</div><div class='add'>+			if (hash_type != 1 &amp;&amp; hash_type != 3)</div><div class='add'>+				type = PKT_HASH_TYPE_L3;</div><div class='add'>+			else</div><div class='add'>+				type = PKT_HASH_TYPE_L4;</div><div class='add'>+		}</div><div class='ctx'> 		skb_set_hash(skb, le32_to_cpu(rxcmp-&gt;rx_cmp_rss_hash), type);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	cfa_code = RX_CMP_CFA_CODE(rxcmp1);</div><div class='del'>-	skb-&gt;protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));</div><div class='del'>-</div><div class='del'>-	if ((rxcmp1-&gt;rx_cmp_flags2 &amp;</div><div class='del'>-	     cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &amp;&amp;</div><div class='del'>-	    (skb-&gt;dev-&gt;features &amp; BNXT_HW_FEATURE_VLAN_ALL_RX)) {</div><div class='del'>-		u32 meta_data = le32_to_cpu(rxcmp1-&gt;rx_cmp_meta_data);</div><div class='del'>-		u16 vtag = meta_data &amp; RX_CMP_FLAGS2_METADATA_TCI_MASK;</div><div class='del'>-		__be16 vlan_proto = htons(meta_data &gt;&gt;</div><div class='del'>-					  RX_CMP_FLAGS2_METADATA_TPID_SFT);</div><div class='add'>+	if (cmp_type == CMP_TYPE_RX_L2_CMP)</div><div class='add'>+		dev = bnxt_get_pkt_dev(bp, RX_CMP_CFA_CODE(rxcmp1));</div><div class='add'>+	skb-&gt;protocol = eth_type_trans(skb, dev);</div><div class='ctx'> </div><div class='del'>-		if (eth_type_vlan(vlan_proto)) {</div><div class='del'>-			__vlan_hwaccel_put_tag(skb, vlan_proto, vtag);</div><div class='del'>-		} else {</div><div class='del'>-			dev_kfree_skb(skb);</div><div class='add'>+	if (skb-&gt;dev-&gt;features &amp; BNXT_HW_FEATURE_VLAN_ALL_RX) {</div><div class='add'>+		skb = bnxt_rx_vlan(skb, cmp_type, rxcmp, rxcmp1);</div><div class='add'>+		if (!skb)</div><div class='ctx'> 			goto next_rx;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	skb_checksum_none_assert(skb);</div><div class='hunk'>@@ -2005,10 +2160,8 @@ static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (unlikely((flags &amp; RX_CMP_FLAGS_ITYPES_MASK) ==</div><div class='del'>-		     RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp-&gt;ptp_all_rx_tstamp) {</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-			u32 cmpl_ts = le32_to_cpu(rxcmp1-&gt;rx_cmp_timestamp);</div><div class='add'>+	if (bnxt_rx_ts_valid(bp, flags, rxcmp1, &amp;cmpl_ts)) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			u64 ns, ts;</div><div class='ctx'> </div><div class='ctx'> 			if (!bnxt_get_rx_ts_p5(bp, &amp;ts, cmpl_ts)) {</div><div class='hunk'>@@ -2032,7 +2185,7 @@ next_rx:</div><div class='ctx'> </div><div class='ctx'> next_rx_no_len:</div><div class='ctx'> 	rxr-&gt;rx_prod = NEXT_RX(prod);</div><div class='del'>-	rxr-&gt;rx_next_cons = NEXT_RX(cons);</div><div class='add'>+	rxr-&gt;rx_next_cons = RING_RX(bp, NEXT_RX(cons));</div><div class='ctx'> </div><div class='ctx'> next_rx_no_prod_no_len:</div><div class='ctx'> 	*raw_cons = tmp_raw_cons;</div><div class='hunk'>@@ -2071,7 +2224,8 @@ static int bnxt_force_rx_discard(struct bnxt *bp,</div><div class='ctx'> 	 */</div><div class='ctx'> 	dma_rmb();</div><div class='ctx'> 	cmp_type = RX_CMP_TYPE(rxcmp);</div><div class='del'>-	if (cmp_type == CMP_TYPE_RX_L2_CMP) {</div><div class='add'>+	if (cmp_type == CMP_TYPE_RX_L2_CMP ||</div><div class='add'>+	    cmp_type == CMP_TYPE_RX_L2_V3_CMP) {</div><div class='ctx'> 		rxcmp1-&gt;rx_cmp_cfa_code_errors_v2 |=</div><div class='ctx'> 			cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);</div><div class='ctx'> 	} else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {</div><div class='hunk'>@@ -2131,6 +2285,10 @@ static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)</div><div class='ctx'> </div><div class='ctx'> static u16 bnxt_get_force_speed(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2)</div><div class='add'>+		return link_info-&gt;force_link_speed2;</div><div class='ctx'> 	if (link_info-&gt;req_signal_mode == BNXT_SIG_MODE_PAM4)</div><div class='ctx'> 		return link_info-&gt;force_pam4_link_speed;</div><div class='ctx'> 	return link_info-&gt;force_link_speed;</div><div class='hunk'>@@ -2138,6 +2296,28 @@ static u16 bnxt_get_force_speed(struct bnxt_link_info *link_info)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_set_force_speed(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		link_info-&gt;req_link_speed = link_info-&gt;force_link_speed2;</div><div class='add'>+		link_info-&gt;req_signal_mode = BNXT_SIG_MODE_NRZ;</div><div class='add'>+		switch (link_info-&gt;req_link_speed) {</div><div class='add'>+		case BNXT_LINK_SPEED_50GB_PAM4:</div><div class='add'>+		case BNXT_LINK_SPEED_100GB_PAM4:</div><div class='add'>+		case BNXT_LINK_SPEED_200GB_PAM4:</div><div class='add'>+		case BNXT_LINK_SPEED_400GB_PAM4:</div><div class='add'>+			link_info-&gt;req_signal_mode = BNXT_SIG_MODE_PAM4;</div><div class='add'>+			break;</div><div class='add'>+		case BNXT_LINK_SPEED_100GB_PAM4_112:</div><div class='add'>+		case BNXT_LINK_SPEED_200GB_PAM4_112:</div><div class='add'>+		case BNXT_LINK_SPEED_400GB_PAM4_112:</div><div class='add'>+			link_info-&gt;req_signal_mode = BNXT_SIG_MODE_PAM4_112;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			link_info-&gt;req_signal_mode = BNXT_SIG_MODE_NRZ;</div><div class='add'>+		}</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> 	link_info-&gt;req_link_speed = link_info-&gt;force_link_speed;</div><div class='ctx'> 	link_info-&gt;req_signal_mode = BNXT_SIG_MODE_NRZ;</div><div class='ctx'> 	if (link_info-&gt;force_pam4_link_speed) {</div><div class='hunk'>@@ -2148,12 +2328,25 @@ static void bnxt_set_force_speed(struct bnxt_link_info *link_info)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_set_auto_speed(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		link_info-&gt;advertising = link_info-&gt;auto_link_speeds2;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> 	link_info-&gt;advertising = link_info-&gt;auto_link_speeds;</div><div class='ctx'> 	link_info-&gt;advertising_pam4 = link_info-&gt;auto_pam4_link_speeds;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool bnxt_force_speed_updated(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		if (link_info-&gt;req_link_speed != link_info-&gt;force_link_speed2)</div><div class='add'>+			return true;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> 	if (link_info-&gt;req_signal_mode == BNXT_SIG_MODE_NRZ &amp;&amp;</div><div class='ctx'> 	    link_info-&gt;req_link_speed != link_info-&gt;force_link_speed)</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -2165,6 +2358,13 @@ static bool bnxt_force_speed_updated(struct bnxt_link_info *link_info)</div><div class='ctx'> </div><div class='ctx'> static bool bnxt_auto_speed_updated(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		if (link_info-&gt;advertising != link_info-&gt;auto_link_speeds2)</div><div class='add'>+			return true;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> 	if (link_info-&gt;advertising != link_info-&gt;auto_link_speeds ||</div><div class='ctx'> 	    link_info-&gt;advertising_pam4 != link_info-&gt;auto_pam4_link_speeds)</div><div class='ctx'> 		return true;</div><div class='hunk'>@@ -2415,7 +2615,7 @@ static int bnxt_async_event_process(struct bnxt *bp,</div><div class='ctx'> 		struct bnxt_rx_ring_info *rxr;</div><div class='ctx'> 		u16 grp_idx;</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			goto async_event_process_exit;</div><div class='ctx'> </div><div class='ctx'> 		netdev_warn(bp-&gt;dev, "Ring monitor event, ring type %lu id 0x%x\n",</div><div class='hunk'>@@ -2588,7 +2788,6 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	struct bnxt_napi *bnapi = cpr-&gt;bnapi;</div><div class='ctx'> 	u32 raw_cons = cpr-&gt;cp_raw_cons;</div><div class='ctx'> 	u32 cons;</div><div class='del'>-	int tx_pkts = 0;</div><div class='ctx'> 	int rx_pkts = 0;</div><div class='ctx'> 	u8 event = 0;</div><div class='ctx'> 	struct tx_cmp *txcmp;</div><div class='hunk'>@@ -2596,6 +2795,7 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	cpr-&gt;has_more_work = 0;</div><div class='ctx'> 	cpr-&gt;had_work_done = 1;</div><div class='ctx'> 	while (1) {</div><div class='add'>+		u8 cmp_type;</div><div class='ctx'> 		int rc;</div><div class='ctx'> </div><div class='ctx'> 		cons = RING_CMP(raw_cons);</div><div class='hunk'>@@ -2608,17 +2808,31 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 		 * reading any further.</div><div class='ctx'> 		 */</div><div class='ctx'> 		dma_rmb();</div><div class='del'>-		if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {</div><div class='del'>-			tx_pkts++;</div><div class='add'>+		cmp_type = TX_CMP_TYPE(txcmp);</div><div class='add'>+		if (cmp_type == CMP_TYPE_TX_L2_CMP ||</div><div class='add'>+		    cmp_type == CMP_TYPE_TX_L2_COAL_CMP) {</div><div class='add'>+			u32 opaque = txcmp-&gt;tx_cmp_opaque;</div><div class='add'>+			struct bnxt_tx_ring_info *txr;</div><div class='add'>+			u16 tx_freed;</div><div class='add'>+</div><div class='add'>+			txr = bnapi-&gt;tx_ring[TX_OPAQUE_RING(opaque)];</div><div class='add'>+			event |= BNXT_TX_CMP_EVENT;</div><div class='add'>+			if (cmp_type == CMP_TYPE_TX_L2_COAL_CMP)</div><div class='add'>+				txr-&gt;tx_hw_cons = TX_CMP_SQ_CONS_IDX(txcmp);</div><div class='add'>+			else</div><div class='add'>+				txr-&gt;tx_hw_cons = TX_OPAQUE_PROD(bp, opaque);</div><div class='add'>+			tx_freed = (txr-&gt;tx_hw_cons - txr-&gt;tx_cons) &amp;</div><div class='add'>+				   bp-&gt;tx_ring_mask;</div><div class='ctx'> 			/* return full budget so NAPI will complete. */</div><div class='del'>-			if (unlikely(tx_pkts &gt;= bp-&gt;tx_wake_thresh)) {</div><div class='add'>+			if (unlikely(tx_freed &gt;= bp-&gt;tx_wake_thresh)) {</div><div class='ctx'> 				rx_pkts = budget;</div><div class='ctx'> 				raw_cons = NEXT_RAW_CMP(raw_cons);</div><div class='ctx'> 				if (budget)</div><div class='ctx'> 					cpr-&gt;has_more_work = 1;</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='del'>-		} else if ((TX_CMP_TYPE(txcmp) &amp; 0x30) == 0x10) {</div><div class='add'>+		} else if (cmp_type &gt;= CMP_TYPE_RX_L2_CMP &amp;&amp;</div><div class='add'>+			   cmp_type &lt;= CMP_TYPE_RX_L2_TPA_START_V3_CMP) {</div><div class='ctx'> 			if (likely(budget))</div><div class='ctx'> 				rc = bnxt_rx_pkt(bp, cpr, &amp;raw_cons, &amp;event);</div><div class='ctx'> 			else</div><div class='hunk'>@@ -2635,12 +2849,9 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 				rx_pkts++;</div><div class='ctx'> 			else if (rc == -EBUSY)	/* partial completion */</div><div class='ctx'> 				break;</div><div class='del'>-		} else if (unlikely((TX_CMP_TYPE(txcmp) ==</div><div class='del'>-				     CMPL_BASE_TYPE_HWRM_DONE) ||</div><div class='del'>-				    (TX_CMP_TYPE(txcmp) ==</div><div class='del'>-				     CMPL_BASE_TYPE_HWRM_FWD_REQ) ||</div><div class='del'>-				    (TX_CMP_TYPE(txcmp) ==</div><div class='del'>-				     CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {</div><div class='add'>+		} else if (unlikely(cmp_type == CMPL_BASE_TYPE_HWRM_DONE ||</div><div class='add'>+				    cmp_type == CMPL_BASE_TYPE_HWRM_FWD_REQ ||</div><div class='add'>+				    cmp_type == CMPL_BASE_TYPE_HWRM_ASYNC_EVENT)) {</div><div class='ctx'> 			bnxt_hwrm_handler(bp, txcmp);</div><div class='ctx'> 		}</div><div class='ctx'> 		raw_cons = NEXT_RAW_CMP(raw_cons);</div><div class='hunk'>@@ -2655,7 +2866,7 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 		xdp_do_flush();</div><div class='ctx'> </div><div class='ctx'> 	if (event &amp; BNXT_TX_EVENT) {</div><div class='del'>-		struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring;</div><div class='add'>+		struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring[0];</div><div class='ctx'> 		u16 prod = txr-&gt;tx_prod;</div><div class='ctx'> </div><div class='ctx'> 		/* Sync BD data before updating doorbell */</div><div class='hunk'>@@ -2665,7 +2876,6 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cpr-&gt;cp_raw_cons = raw_cons;</div><div class='del'>-	bnapi-&gt;tx_pkts += tx_pkts;</div><div class='ctx'> 	bnapi-&gt;events |= event;</div><div class='ctx'> 	return rx_pkts;</div><div class='ctx'> }</div><div class='hunk'>@@ -2673,7 +2883,7 @@ static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='ctx'> 				  int budget)</div><div class='ctx'> {</div><div class='del'>-	if (bnapi-&gt;tx_pkts &amp;&amp; !bnapi-&gt;tx_fault)</div><div class='add'>+	if ((bnapi-&gt;events &amp; BNXT_TX_CMP_EVENT) &amp;&amp; !bnapi-&gt;tx_fault)</div><div class='ctx'> 		bnapi-&gt;tx_int(bp, bnapi, budget);</div><div class='ctx'> </div><div class='ctx'> 	if ((bnapi-&gt;events &amp; BNXT_RX_EVENT) &amp;&amp; !(bnapi-&gt;in_reset)) {</div><div class='hunk'>@@ -2686,7 +2896,7 @@ static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='ctx'> </div><div class='ctx'> 		bnxt_db_write(bp, &amp;rxr-&gt;rx_agg_db, rxr-&gt;rx_agg_prod);</div><div class='ctx'> 	}</div><div class='del'>-	bnapi-&gt;events = 0;</div><div class='add'>+	bnapi-&gt;events &amp;= BNXT_TX_CMP_EVENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='hunk'>@@ -2826,10 +3036,10 @@ static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='ctx'> 	struct bnxt_cp_ring_info *cpr = &amp;bnapi-&gt;cp_ring;</div><div class='ctx'> 	int i, work_done = 0;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; 2; i++) {</div><div class='del'>-		struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[i];</div><div class='add'>+	for (i = 0; i &lt; cpr-&gt;cp_ring_count; i++) {</div><div class='add'>+		struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[i];</div><div class='ctx'> </div><div class='del'>-		if (cpr2) {</div><div class='add'>+		if (cpr2-&gt;had_nqe_notify) {</div><div class='ctx'> 			work_done += __bnxt_poll_work(bp, cpr2,</div><div class='ctx'> 						      budget - work_done);</div><div class='ctx'> 			cpr-&gt;has_more_work |= cpr2-&gt;has_more_work;</div><div class='hunk'>@@ -2844,14 +3054,22 @@ static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='ctx'> 	struct bnxt_cp_ring_info *cpr = &amp;bnapi-&gt;cp_ring;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; 2; i++) {</div><div class='del'>-		struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[i];</div><div class='add'>+	for (i = 0; i &lt; cpr-&gt;cp_ring_count; i++) {</div><div class='add'>+		struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[i];</div><div class='ctx'> 		struct bnxt_db_info *db;</div><div class='ctx'> </div><div class='del'>-		if (cpr2 &amp;&amp; cpr2-&gt;had_work_done) {</div><div class='add'>+		if (cpr2-&gt;had_work_done) {</div><div class='add'>+			u32 tgl = 0;</div><div class='add'>+</div><div class='add'>+			if (dbr_type == DBR_TYPE_CQ_ARMALL) {</div><div class='add'>+				cpr2-&gt;had_nqe_notify = 0;</div><div class='add'>+				tgl = cpr2-&gt;toggle;</div><div class='add'>+			}</div><div class='ctx'> 			db = &amp;cpr2-&gt;cp_db;</div><div class='del'>-			bnxt_writeq(bp, db-&gt;db_key64 | dbr_type |</div><div class='del'>-				    RING_CMP(cpr2-&gt;cp_raw_cons), db-&gt;doorbell);</div><div class='add'>+			bnxt_writeq(bp,</div><div class='add'>+				    db-&gt;db_key64 | dbr_type | DB_TOGGLE(tgl) |</div><div class='add'>+				    DB_RING_IDX(db, cpr2-&gt;cp_raw_cons),</div><div class='add'>+				    db-&gt;doorbell);</div><div class='ctx'> 			cpr2-&gt;had_work_done = 0;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2878,6 +3096,8 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget)</div><div class='ctx'> 		work_done = __bnxt_poll_cqs(bp, bnapi, budget);</div><div class='ctx'> 	}</div><div class='ctx'> 	while (1) {</div><div class='add'>+		u16 type;</div><div class='add'>+</div><div class='ctx'> 		cons = RING_CMP(raw_cons);</div><div class='ctx'> 		nqcmp = &amp;cpr-&gt;nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];</div><div class='ctx'> </div><div class='hunk'>@@ -2899,15 +3119,21 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget)</div><div class='ctx'> 		 */</div><div class='ctx'> 		dma_rmb();</div><div class='ctx'> </div><div class='del'>-		if (nqcmp-&gt;type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {</div><div class='add'>+		type = le16_to_cpu(nqcmp-&gt;type);</div><div class='add'>+		if (NQE_CN_TYPE(type) == NQ_CN_TYPE_CQ_NOTIFICATION) {</div><div class='ctx'> 			u32 idx = le32_to_cpu(nqcmp-&gt;cq_handle_low);</div><div class='add'>+			u32 cq_type = BNXT_NQ_HDL_TYPE(idx);</div><div class='ctx'> 			struct bnxt_cp_ring_info *cpr2;</div><div class='ctx'> </div><div class='ctx'> 			/* No more budget for RX work */</div><div class='del'>-			if (budget &amp;&amp; work_done &gt;= budget &amp;&amp; idx == BNXT_RX_HDL)</div><div class='add'>+			if (budget &amp;&amp; work_done &gt;= budget &amp;&amp;</div><div class='add'>+			    cq_type == BNXT_NQ_HDL_TYPE_RX)</div><div class='ctx'> 				break;</div><div class='ctx'> </div><div class='del'>-			cpr2 = cpr-&gt;cp_ring_arr[idx];</div><div class='add'>+			idx = BNXT_NQ_HDL_IDX(idx);</div><div class='add'>+			cpr2 = &amp;cpr-&gt;cp_ring_arr[idx];</div><div class='add'>+			cpr2-&gt;had_nqe_notify = 1;</div><div class='add'>+			cpr2-&gt;toggle = NQE_CN_TOGGLE(type);</div><div class='ctx'> 			work_done += __bnxt_poll_work(bp, cpr2,</div><div class='ctx'> 						      budget - work_done);</div><div class='ctx'> 			cpr-&gt;has_more_work |= cpr2-&gt;has_more_work;</div><div class='hunk'>@@ -2922,8 +3148,9 @@ static int bnxt_poll_p5(struct napi_struct *napi, int budget)</div><div class='ctx'> 		BNXT_DB_NQ_P5(&amp;cpr-&gt;cp_db, raw_cons);</div><div class='ctx'> 	}</div><div class='ctx'> poll_done:</div><div class='del'>-	cpr_rx = cpr-&gt;cp_ring_arr[BNXT_RX_HDL];</div><div class='del'>-	if (cpr_rx &amp;&amp; (bp-&gt;flags &amp; BNXT_FLAG_DIM)) {</div><div class='add'>+	cpr_rx = &amp;cpr-&gt;cp_ring_arr[0];</div><div class='add'>+	if (cpr_rx-&gt;cp_ring_type == BNXT_NQ_HDL_TYPE_RX &amp;&amp;</div><div class='add'>+	    (bp-&gt;flags &amp; BNXT_FLAG_DIM)) {</div><div class='ctx'> 		struct dim_sample dim_sample = {};</div><div class='ctx'> </div><div class='ctx'> 		dim_update_sample(cpr-&gt;event_ctr,</div><div class='hunk'>@@ -3097,20 +3324,20 @@ static void bnxt_free_skbs(struct bnxt *bp)</div><div class='ctx'> 	bnxt_free_rx_skbs(bp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)</div><div class='add'>+static void bnxt_init_ctx_mem(struct bnxt_ctx_mem_type *ctxm, void *p, int len)</div><div class='ctx'> {</div><div class='del'>-	u8 init_val = mem_init-&gt;init_val;</div><div class='del'>-	u16 offset = mem_init-&gt;offset;</div><div class='add'>+	u8 init_val = ctxm-&gt;init_value;</div><div class='add'>+	u16 offset = ctxm-&gt;init_offset;</div><div class='ctx'> 	u8 *p2 = p;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!init_val)</div><div class='ctx'> 		return;</div><div class='del'>-	if (offset == BNXT_MEM_INVALID_OFFSET) {</div><div class='add'>+	if (offset == BNXT_CTX_INIT_INVALID_OFFSET) {</div><div class='ctx'> 		memset(p, init_val, len);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='del'>-	for (i = 0; i &lt; len; i += mem_init-&gt;size)</div><div class='add'>+	for (i = 0; i &lt; len; i += ctxm-&gt;entry_size)</div><div class='ctx'> 		*(p2 + i + offset) = init_val;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3177,8 +3404,8 @@ static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)</div><div class='ctx'> 		if (!rmem-&gt;pg_arr[i])</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-		if (rmem-&gt;mem_init)</div><div class='del'>-			bnxt_init_ctx_mem(rmem-&gt;mem_init, rmem-&gt;pg_arr[i],</div><div class='add'>+		if (rmem-&gt;ctx_mem)</div><div class='add'>+			bnxt_init_ctx_mem(rmem-&gt;ctx_mem, rmem-&gt;pg_arr[i],</div><div class='ctx'> 					  rmem-&gt;page_size);</div><div class='ctx'> 		if (rmem-&gt;nr_pages &gt; 1 || rmem-&gt;depth &gt; 0) {</div><div class='ctx'> 			if (i == rmem-&gt;nr_pages - 2 &amp;&amp;</div><div class='hunk'>@@ -3225,7 +3452,7 @@ static int bnxt_alloc_tpa_info(struct bnxt *bp)</div><div class='ctx'> 	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	bp-&gt;max_tpa = MAX_TPA;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		if (!bp-&gt;max_tpa_v2)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		bp-&gt;max_tpa = max_t(u16, bp-&gt;max_tpa_v2, MAX_TPA_P5);</div><div class='hunk'>@@ -3240,7 +3467,7 @@ static int bnxt_alloc_tpa_info(struct bnxt *bp)</div><div class='ctx'> 		if (!rxr-&gt;rx_tpa)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 			continue;</div><div class='ctx'> 		for (j = 0; j &lt; bp-&gt;max_tpa; j++) {</div><div class='ctx'> 			agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL);</div><div class='hunk'>@@ -3298,6 +3525,7 @@ static int bnxt_alloc_rx_page_pool(struct bnxt *bp,</div><div class='ctx'> 		pp.pool_size += bp-&gt;rx_ring_size;</div><div class='ctx'> 	pp.nid = dev_to_node(&amp;bp-&gt;pdev-&gt;dev);</div><div class='ctx'> 	pp.napi = &amp;rxr-&gt;bnapi-&gt;napi;</div><div class='add'>+	pp.netdev = bp-&gt;dev;</div><div class='ctx'> 	pp.dev = &amp;bp-&gt;pdev-&gt;dev;</div><div class='ctx'> 	pp.dma_dir = bp-&gt;rx_dir;</div><div class='ctx'> 	pp.max_len = PAGE_SIZE;</div><div class='hunk'>@@ -3395,6 +3623,15 @@ static void bnxt_free_tx_rings(struct bnxt *bp)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define BNXT_TC_TO_RING_BASE(bp, tc)	\</div><div class='add'>+	((tc) * (bp)-&gt;tx_nr_rings_per_tc)</div><div class='add'>+</div><div class='add'>+#define BNXT_RING_TO_TC_OFF(bp, tx)	\</div><div class='add'>+	((tx) % (bp)-&gt;tx_nr_rings_per_tc)</div><div class='add'>+</div><div class='add'>+#define BNXT_RING_TO_TC(bp, tx)		\</div><div class='add'>+	((tx) / (bp)-&gt;tx_nr_rings_per_tc)</div><div class='add'>+</div><div class='ctx'> static int bnxt_alloc_tx_rings(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	int i, j, rc;</div><div class='hunk'>@@ -3450,7 +3687,7 @@ static int bnxt_alloc_tx_rings(struct bnxt *bp)</div><div class='ctx'> 		spin_lock_init(&amp;txr-&gt;xdp_tx_lock);</div><div class='ctx'> 		if (i &lt; bp-&gt;tx_nr_rings_xdp)</div><div class='ctx'> 			continue;</div><div class='del'>-		if (i % bp-&gt;tx_nr_rings_per_tc == (bp-&gt;tx_nr_rings_per_tc - 1))</div><div class='add'>+		if (BNXT_RING_TO_TC_OFF(bp, i) == (bp-&gt;tx_nr_rings_per_tc - 1))</div><div class='ctx'> 			j++;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3533,36 +3770,33 @@ static void bnxt_free_cp_rings(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> 		bnxt_free_ring(bp, &amp;ring-&gt;ring_mem);</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; 2; j++) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[j];</div><div class='add'>+		if (!cpr-&gt;cp_ring_arr)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		for (j = 0; j &lt; cpr-&gt;cp_ring_count; j++) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[j];</div><div class='ctx'> </div><div class='del'>-			if (cpr2) {</div><div class='del'>-				ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='del'>-				bnxt_free_ring(bp, &amp;ring-&gt;ring_mem);</div><div class='del'>-				bnxt_free_cp_arrays(cpr2);</div><div class='del'>-				kfree(cpr2);</div><div class='del'>-				cpr-&gt;cp_ring_arr[j] = NULL;</div><div class='del'>-			}</div><div class='add'>+			ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='add'>+			bnxt_free_ring(bp, &amp;ring-&gt;ring_mem);</div><div class='add'>+			bnxt_free_cp_arrays(cpr2);</div><div class='ctx'> 		}</div><div class='add'>+		kfree(cpr-&gt;cp_ring_arr);</div><div class='add'>+		cpr-&gt;cp_ring_arr = NULL;</div><div class='add'>+		cpr-&gt;cp_ring_count = 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)</div><div class='add'>+static int bnxt_alloc_cp_sub_ring(struct bnxt *bp,</div><div class='add'>+				  struct bnxt_cp_ring_info *cpr)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_ring_mem_info *rmem;</div><div class='ctx'> 	struct bnxt_ring_struct *ring;</div><div class='del'>-	struct bnxt_cp_ring_info *cpr;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);</div><div class='del'>-	if (!cpr)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='ctx'> 	rc = bnxt_alloc_cp_arrays(cpr, bp-&gt;cp_nr_pages);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		bnxt_free_cp_arrays(cpr);</div><div class='del'>-		kfree(cpr);</div><div class='del'>-		return NULL;</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> 	ring = &amp;cpr-&gt;cp_ring_struct;</div><div class='ctx'> 	rmem = &amp;ring-&gt;ring_mem;</div><div class='hunk'>@@ -3575,23 +3809,26 @@ static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		bnxt_free_ring(bp, rmem);</div><div class='ctx'> 		bnxt_free_cp_arrays(cpr);</div><div class='del'>-		kfree(cpr);</div><div class='del'>-		cpr = NULL;</div><div class='ctx'> 	}</div><div class='del'>-	return cpr;</div><div class='add'>+	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_cp_rings(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	bool sh = !!(bp-&gt;flags &amp; BNXT_FLAG_SHARED_RINGS);</div><div class='del'>-	int i, rc, ulp_base_vec, ulp_msix;</div><div class='add'>+	int i, j, rc, ulp_base_vec, ulp_msix;</div><div class='add'>+	int tcs = netdev_get_num_tc(bp-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	if (!tcs)</div><div class='add'>+		tcs = 1;</div><div class='ctx'> 	ulp_msix = bnxt_get_ulp_msix_num(bp);</div><div class='ctx'> 	ulp_base_vec = bnxt_get_ulp_msix_base(bp);</div><div class='del'>-	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='add'>+	for (i = 0, j = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='ctx'> 		struct bnxt_napi *bnapi = bp-&gt;bnapi[i];</div><div class='del'>-		struct bnxt_cp_ring_info *cpr;</div><div class='add'>+		struct bnxt_cp_ring_info *cpr, *cpr2;</div><div class='ctx'> 		struct bnxt_ring_struct *ring;</div><div class='add'>+		int cp_count = 0, k;</div><div class='add'>+		int rx = 0, tx = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (!bnapi)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -3609,35 +3846,55 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp)</div><div class='ctx'> 		else</div><div class='ctx'> 			ring-&gt;map_idx = i;</div><div class='ctx'> </div><div class='del'>-		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		if (i &lt; bp-&gt;rx_nr_rings) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 =</div><div class='del'>-				bnxt_alloc_cp_sub_ring(bp);</div><div class='del'>-</div><div class='del'>-			cpr-&gt;cp_ring_arr[BNXT_RX_HDL] = cpr2;</div><div class='del'>-			if (!cpr2)</div><div class='del'>-				return -ENOMEM;</div><div class='del'>-			cpr2-&gt;bnapi = bnapi;</div><div class='add'>+			cp_count++;</div><div class='add'>+			rx = 1;</div><div class='add'>+		}</div><div class='add'>+		if (i &lt; bp-&gt;tx_nr_rings_xdp) {</div><div class='add'>+			cp_count++;</div><div class='add'>+			tx = 1;</div><div class='add'>+		} else if ((sh &amp;&amp; i &lt; bp-&gt;tx_nr_rings) ||</div><div class='add'>+			 (!sh &amp;&amp; i &gt;= bp-&gt;rx_nr_rings)) {</div><div class='add'>+			cp_count += tcs;</div><div class='add'>+			tx = 1;</div><div class='ctx'> 		}</div><div class='del'>-		if ((sh &amp;&amp; i &lt; bp-&gt;tx_nr_rings) ||</div><div class='del'>-		    (!sh &amp;&amp; i &gt;= bp-&gt;rx_nr_rings)) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 =</div><div class='del'>-				bnxt_alloc_cp_sub_ring(bp);</div><div class='ctx'> </div><div class='del'>-			cpr-&gt;cp_ring_arr[BNXT_TX_HDL] = cpr2;</div><div class='del'>-			if (!cpr2)</div><div class='del'>-				return -ENOMEM;</div><div class='add'>+		cpr-&gt;cp_ring_arr = kcalloc(cp_count, sizeof(*cpr),</div><div class='add'>+					   GFP_KERNEL);</div><div class='add'>+		if (!cpr-&gt;cp_ring_arr)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		cpr-&gt;cp_ring_count = cp_count;</div><div class='add'>+</div><div class='add'>+		for (k = 0; k &lt; cp_count; k++) {</div><div class='add'>+			cpr2 = &amp;cpr-&gt;cp_ring_arr[k];</div><div class='add'>+			rc = bnxt_alloc_cp_sub_ring(bp, cpr2);</div><div class='add'>+			if (rc)</div><div class='add'>+				return rc;</div><div class='ctx'> 			cpr2-&gt;bnapi = bnapi;</div><div class='add'>+			cpr2-&gt;cp_idx = k;</div><div class='add'>+			if (!k &amp;&amp; rx) {</div><div class='add'>+				bp-&gt;rx_ring[i].rx_cpr = cpr2;</div><div class='add'>+				cpr2-&gt;cp_ring_type = BNXT_NQ_HDL_TYPE_RX;</div><div class='add'>+			} else {</div><div class='add'>+				int n, tc = k - rx;</div><div class='add'>+</div><div class='add'>+				n = BNXT_TC_TO_RING_BASE(bp, tc) + j;</div><div class='add'>+				bp-&gt;tx_ring[n].tx_cpr = cpr2;</div><div class='add'>+				cpr2-&gt;cp_ring_type = BNXT_NQ_HDL_TYPE_TX;</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='add'>+		if (tx)</div><div class='add'>+			j++;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_init_ring_struct(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='ctx'> 		struct bnxt_napi *bnapi = bp-&gt;bnapi[i];</div><div class='hunk'>@@ -3682,18 +3939,16 @@ static void bnxt_init_ring_struct(struct bnxt *bp)</div><div class='ctx'> 		rmem-&gt;vmem = (void **)&amp;rxr-&gt;rx_agg_ring;</div><div class='ctx'> </div><div class='ctx'> skip_rx:</div><div class='del'>-		txr = bnapi-&gt;tx_ring;</div><div class='del'>-		if (!txr)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		ring = &amp;txr-&gt;tx_ring_struct;</div><div class='del'>-		rmem = &amp;ring-&gt;ring_mem;</div><div class='del'>-		rmem-&gt;nr_pages = bp-&gt;tx_nr_pages;</div><div class='del'>-		rmem-&gt;page_size = HW_RXBD_RING_SIZE;</div><div class='del'>-		rmem-&gt;pg_arr = (void **)txr-&gt;tx_desc_ring;</div><div class='del'>-		rmem-&gt;dma_arr = txr-&gt;tx_desc_mapping;</div><div class='del'>-		rmem-&gt;vmem_size = SW_TXBD_RING_SIZE * bp-&gt;tx_nr_pages;</div><div class='del'>-		rmem-&gt;vmem = (void **)&amp;txr-&gt;tx_buf_ring;</div><div class='add'>+		bnxt_for_each_napi_tx(j, bnapi, txr) {</div><div class='add'>+			ring = &amp;txr-&gt;tx_ring_struct;</div><div class='add'>+			rmem = &amp;ring-&gt;ring_mem;</div><div class='add'>+			rmem-&gt;nr_pages = bp-&gt;tx_nr_pages;</div><div class='add'>+			rmem-&gt;page_size = HW_TXBD_RING_SIZE;</div><div class='add'>+			rmem-&gt;pg_arr = (void **)txr-&gt;tx_desc_ring;</div><div class='add'>+			rmem-&gt;dma_arr = txr-&gt;tx_desc_mapping;</div><div class='add'>+			rmem-&gt;vmem_size = SW_TXBD_RING_SIZE * bp-&gt;tx_nr_pages;</div><div class='add'>+			rmem-&gt;vmem = (void **)&amp;txr-&gt;tx_buf_ring;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3784,6 +4039,9 @@ static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)</div><div class='ctx'> 	ring = &amp;rxr-&gt;rx_ring_struct;</div><div class='ctx'> 	bnxt_init_rxbd_pages(ring, type);</div><div class='ctx'> </div><div class='add'>+	netif_queue_set_napi(bp-&gt;dev, ring_nr, NETDEV_QUEUE_TYPE_RX,</div><div class='add'>+			     &amp;rxr-&gt;bnapi-&gt;napi);</div><div class='add'>+</div><div class='ctx'> 	if (BNXT_RX_PAGE_MODE(bp) &amp;&amp; bp-&gt;xdp_prog) {</div><div class='ctx'> 		bpf_prog_add(bp-&gt;xdp_prog, 1);</div><div class='ctx'> 		rxr-&gt;xdp_prog = bp-&gt;xdp_prog;</div><div class='hunk'>@@ -3814,11 +4072,10 @@ static void bnxt_init_cp_rings(struct bnxt *bp)</div><div class='ctx'> 		ring-&gt;fw_ring_id = INVALID_HW_RING_ID;</div><div class='ctx'> 		cpr-&gt;rx_ring_coal.coal_ticks = bp-&gt;rx_coal.coal_ticks;</div><div class='ctx'> 		cpr-&gt;rx_ring_coal.coal_bufs = bp-&gt;rx_coal.coal_bufs;</div><div class='del'>-		for (j = 0; j &lt; 2; j++) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[j];</div><div class='del'>-</div><div class='del'>-			if (!cpr2)</div><div class='del'>-				continue;</div><div class='add'>+		if (!cpr-&gt;cp_ring_arr)</div><div class='add'>+			continue;</div><div class='add'>+		for (j = 0; j &lt; cpr-&gt;cp_ring_count; j++) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[j];</div><div class='ctx'> </div><div class='ctx'> 			ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='ctx'> 			ring-&gt;fw_ring_id = INVALID_HW_RING_ID;</div><div class='hunk'>@@ -3861,6 +4118,11 @@ static int bnxt_init_tx_rings(struct bnxt *bp)</div><div class='ctx'> 		struct bnxt_ring_struct *ring = &amp;txr-&gt;tx_ring_struct;</div><div class='ctx'> </div><div class='ctx'> 		ring-&gt;fw_ring_id = INVALID_HW_RING_ID;</div><div class='add'>+</div><div class='add'>+		if (i &gt;= bp-&gt;tx_nr_rings_xdp)</div><div class='add'>+			netif_queue_set_napi(bp-&gt;dev, i - bp-&gt;tx_nr_rings_xdp,</div><div class='add'>+					     NETDEV_QUEUE_TYPE_TX,</div><div class='add'>+					     &amp;txr-&gt;bnapi-&gt;napi);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3906,7 +4168,7 @@ static int bnxt_alloc_vnics(struct bnxt *bp)</div><div class='ctx'> 	int num_vnics = 1;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_RFS_ACCEL</div><div class='del'>-	if ((bp-&gt;flags &amp; (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)</div><div class='add'>+	if ((bp-&gt;flags &amp; (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5_PLUS)) == BNXT_FLAG_RFS)</div><div class='ctx'> 		num_vnics += bp-&gt;rx_nr_rings;</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='hunk'>@@ -3937,13 +4199,22 @@ static void bnxt_init_vnics(struct bnxt *bp)</div><div class='ctx'> 		vnic-&gt;fw_l2_ctx_id = INVALID_HW_RING_ID;</div><div class='ctx'> </div><div class='ctx'> 		if (bp-&gt;vnic_info[i].rss_hash_key) {</div><div class='del'>-			if (i == 0)</div><div class='add'>+			if (!i) {</div><div class='add'>+				u8 *key = (void *)vnic-&gt;rss_hash_key;</div><div class='add'>+				int k;</div><div class='add'>+</div><div class='add'>+				bp-&gt;toeplitz_prefix = 0;</div><div class='ctx'> 				get_random_bytes(vnic-&gt;rss_hash_key,</div><div class='ctx'> 					      HW_HASH_KEY_SIZE);</div><div class='del'>-			else</div><div class='add'>+				for (k = 0; k &lt; 8; k++) {</div><div class='add'>+					bp-&gt;toeplitz_prefix &lt;&lt;= 8;</div><div class='add'>+					bp-&gt;toeplitz_prefix |= key[k];</div><div class='add'>+				}</div><div class='add'>+			} else {</div><div class='ctx'> 				memcpy(vnic-&gt;rss_hash_key,</div><div class='ctx'> 				       bp-&gt;vnic_info[0].rss_hash_key,</div><div class='ctx'> 				       HW_HASH_KEY_SIZE);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -4179,7 +4450,7 @@ static int bnxt_alloc_vnic_attributes(struct bnxt *bp)</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			goto vnic_skip_grps;</div><div class='ctx'> </div><div class='ctx'> 		if (vnic-&gt;flags &amp; BNXT_VNIC_RSS_FLAG)</div><div class='hunk'>@@ -4193,13 +4464,13 @@ static int bnxt_alloc_vnic_attributes(struct bnxt *bp)</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> vnic_skip_grps:</div><div class='del'>-		if ((bp-&gt;flags &amp; BNXT_FLAG_NEW_RSS_CAP) &amp;&amp;</div><div class='add'>+		if ((bp-&gt;rss_cap &amp; BNXT_RSS_CAP_NEW_RSS_CAP) &amp;&amp;</div><div class='ctx'> 		    !(vnic-&gt;flags &amp; BNXT_VNIC_RSS_FLAG))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* Allocate rss table and hash key */</div><div class='ctx'> 		size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);</div><div class='ctx'> </div><div class='ctx'> 		vnic-&gt;rss_table_size = size + HW_HASH_KEY_SIZE;</div><div class='hunk'>@@ -4309,7 +4580,7 @@ static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (!(bp-&gt;fw_cap &amp; BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||</div><div class='del'>-	    !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	    !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT);</div><div class='hunk'>@@ -4347,7 +4618,7 @@ static void bnxt_init_stats(struct bnxt *bp)</div><div class='ctx'> 	stats = &amp;cpr-&gt;stats;</div><div class='ctx'> 	rc = bnxt_hwrm_func_qstat_ext(bp, stats);</div><div class='ctx'> 	if (rc) {</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			mask = (1ULL &lt;&lt; 48) - 1;</div><div class='ctx'> 		else</div><div class='ctx'> 			mask = -1ULL;</div><div class='hunk'>@@ -4493,7 +4764,7 @@ alloc_tx_ext_stats:</div><div class='ctx'> </div><div class='ctx'> static void bnxt_clear_ring_indices(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	int i, j;</div><div class='ctx'> </div><div class='ctx'> 	if (!bp-&gt;bnapi)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -4510,10 +4781,10 @@ static void bnxt_clear_ring_indices(struct bnxt *bp)</div><div class='ctx'> 		cpr = &amp;bnapi-&gt;cp_ring;</div><div class='ctx'> 		cpr-&gt;cp_raw_cons = 0;</div><div class='ctx'> </div><div class='del'>-		txr = bnapi-&gt;tx_ring;</div><div class='del'>-		if (txr) {</div><div class='add'>+		bnxt_for_each_napi_tx(j, bnapi, txr) {</div><div class='ctx'> 			txr-&gt;tx_prod = 0;</div><div class='ctx'> 			txr-&gt;tx_cons = 0;</div><div class='add'>+			txr-&gt;tx_hw_cons = 0;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		rxr = bnapi-&gt;rx_ring;</div><div class='hunk'>@@ -4523,12 +4794,12 @@ static void bnxt_clear_ring_indices(struct bnxt *bp)</div><div class='ctx'> 			rxr-&gt;rx_sw_agg_prod = 0;</div><div class='ctx'> 			rxr-&gt;rx_next_cons = 0;</div><div class='ctx'> 		}</div><div class='add'>+		bnapi-&gt;events = 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)</div><div class='add'>+static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool all)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* Under rtnl_lock and all our NAPIs have been disabled.  It's</div><div class='hunk'>@@ -4540,40 +4811,73 @@ static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)</div><div class='ctx'> 		struct bnxt_ntuple_filter *fltr;</div><div class='ctx'> </div><div class='ctx'> 		head = &amp;bp-&gt;ntp_fltr_hash_tbl[i];</div><div class='del'>-		hlist_for_each_entry_safe(fltr, tmp, head, hash) {</div><div class='del'>-			hlist_del(&amp;fltr-&gt;hash);</div><div class='add'>+		hlist_for_each_entry_safe(fltr, tmp, head, base.hash) {</div><div class='add'>+			bnxt_del_l2_filter(bp, fltr-&gt;l2_fltr);</div><div class='add'>+			if (!all &amp;&amp; (fltr-&gt;base.flags &amp; BNXT_ACT_FUNC_DST))</div><div class='add'>+				continue;</div><div class='add'>+			hlist_del(&amp;fltr-&gt;base.hash);</div><div class='add'>+			clear_bit(fltr-&gt;base.sw_id, bp-&gt;ntp_fltr_bmap);</div><div class='add'>+			bp-&gt;ntp_fltr_count--;</div><div class='ctx'> 			kfree(fltr);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (irq_reinit) {</div><div class='del'>-		bitmap_free(bp-&gt;ntp_fltr_bmap);</div><div class='del'>-		bp-&gt;ntp_fltr_bmap = NULL;</div><div class='del'>-	}</div><div class='add'>+	if (!all)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	bitmap_free(bp-&gt;ntp_fltr_bmap);</div><div class='add'>+	bp-&gt;ntp_fltr_bmap = NULL;</div><div class='ctx'> 	bp-&gt;ntp_fltr_count = 0;</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	int i, rc = 0;</div><div class='ctx'> </div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_RFS))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_RFS) || bp-&gt;ntp_fltr_bmap)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; BNXT_NTP_FLTR_HASH_SIZE; i++)</div><div class='ctx'> 		INIT_HLIST_HEAD(&amp;bp-&gt;ntp_fltr_hash_tbl[i]);</div><div class='ctx'> </div><div class='ctx'> 	bp-&gt;ntp_fltr_count = 0;</div><div class='del'>-	bp-&gt;ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL);</div><div class='add'>+	bp-&gt;ntp_fltr_bmap = bitmap_zalloc(BNXT_MAX_FLTR, GFP_KERNEL);</div><div class='ctx'> </div><div class='ctx'> 	if (!bp-&gt;ntp_fltr_bmap)</div><div class='ctx'> 		rc = -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='del'>-#else</div><div class='del'>-	return 0;</div><div class='del'>-#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void bnxt_free_l2_filters(struct bnxt *bp, bool all)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; BNXT_L2_FLTR_HASH_SIZE; i++) {</div><div class='add'>+		struct hlist_head *head;</div><div class='add'>+		struct hlist_node *tmp;</div><div class='add'>+		struct bnxt_l2_filter *fltr;</div><div class='add'>+</div><div class='add'>+		head = &amp;bp-&gt;l2_fltr_hash_tbl[i];</div><div class='add'>+		hlist_for_each_entry_safe(fltr, tmp, head, base.hash) {</div><div class='add'>+			if (!all &amp;&amp; (fltr-&gt;base.flags &amp; BNXT_ACT_FUNC_DST))</div><div class='add'>+				continue;</div><div class='add'>+			hlist_del(&amp;fltr-&gt;base.hash);</div><div class='add'>+			if (fltr-&gt;base.flags) {</div><div class='add'>+				clear_bit(fltr-&gt;base.sw_id, bp-&gt;ntp_fltr_bmap);</div><div class='add'>+				bp-&gt;ntp_fltr_count--;</div><div class='add'>+			}</div><div class='add'>+			kfree(fltr);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void bnxt_init_l2_fltr_tbl(struct bnxt *bp)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; BNXT_L2_FLTR_HASH_SIZE; i++)</div><div class='add'>+		INIT_HLIST_HEAD(&amp;bp-&gt;l2_fltr_hash_tbl[i]);</div><div class='add'>+	get_random_bytes(&amp;bp-&gt;hash_seed, sizeof(bp-&gt;hash_seed));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)</div><div class='hunk'>@@ -4583,7 +4887,8 @@ static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)</div><div class='ctx'> 	bnxt_free_rx_rings(bp);</div><div class='ctx'> 	bnxt_free_cp_rings(bp);</div><div class='ctx'> 	bnxt_free_all_cp_arrays(bp);</div><div class='del'>-	bnxt_free_ntp_fltrs(bp, irq_re_init);</div><div class='add'>+	bnxt_free_ntp_fltrs(bp, false);</div><div class='add'>+	bnxt_free_l2_filters(bp, false);</div><div class='ctx'> 	if (irq_re_init) {</div><div class='ctx'> 		bnxt_free_ring_stats(bp);</div><div class='ctx'> 		if (!(bp-&gt;phy_flags &amp; BNXT_PHY_FL_PORT_STATS_NO_RESET) ||</div><div class='hunk'>@@ -4626,7 +4931,7 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)</div><div class='ctx'> 			bp-&gt;bnapi[i] = bnapi;</div><div class='ctx'> 			bp-&gt;bnapi[i]-&gt;index = i;</div><div class='ctx'> 			bp-&gt;bnapi[i]-&gt;bp = bp;</div><div class='del'>-			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 				struct bnxt_cp_ring_info *cpr =</div><div class='ctx'> 					&amp;bp-&gt;bnapi[i]-&gt;cp_ring;</div><div class='ctx'> </div><div class='hunk'>@@ -4644,11 +4949,13 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)</div><div class='ctx'> 		for (i = 0; i &lt; bp-&gt;rx_nr_rings; i++) {</div><div class='ctx'> 			struct bnxt_rx_ring_info *rxr = &amp;bp-&gt;rx_ring[i];</div><div class='ctx'> </div><div class='del'>-			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 				rxr-&gt;rx_ring_struct.ring_mem.flags =</div><div class='ctx'> 					BNXT_RMEM_RING_PTE_FLAG;</div><div class='ctx'> 				rxr-&gt;rx_agg_ring_struct.ring_mem.flags =</div><div class='ctx'> 					BNXT_RMEM_RING_PTE_FLAG;</div><div class='add'>+			} else {</div><div class='add'>+				rxr-&gt;rx_cpr =  &amp;bp-&gt;bnapi[i]-&gt;cp_ring;</div><div class='ctx'> 			}</div><div class='ctx'> 			rxr-&gt;bnapi = bp-&gt;bnapi[i];</div><div class='ctx'> 			bp-&gt;bnapi[i]-&gt;rx_ring = &amp;bp-&gt;rx_ring[i];</div><div class='hunk'>@@ -4671,22 +4978,33 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)</div><div class='ctx'> 		else</div><div class='ctx'> 			j = bp-&gt;rx_nr_rings;</div><div class='ctx'> </div><div class='del'>-		for (i = 0; i &lt; bp-&gt;tx_nr_rings; i++, j++) {</div><div class='add'>+		for (i = 0; i &lt; bp-&gt;tx_nr_rings; i++) {</div><div class='ctx'> 			struct bnxt_tx_ring_info *txr = &amp;bp-&gt;tx_ring[i];</div><div class='add'>+			struct bnxt_napi *bnapi2;</div><div class='ctx'> </div><div class='del'>-			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+			if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 				txr-&gt;tx_ring_struct.ring_mem.flags =</div><div class='ctx'> 					BNXT_RMEM_RING_PTE_FLAG;</div><div class='del'>-			txr-&gt;bnapi = bp-&gt;bnapi[j];</div><div class='del'>-			bp-&gt;bnapi[j]-&gt;tx_ring = txr;</div><div class='ctx'> 			bp-&gt;tx_ring_map[i] = bp-&gt;tx_nr_rings_xdp + i;</div><div class='ctx'> 			if (i &gt;= bp-&gt;tx_nr_rings_xdp) {</div><div class='add'>+				int k = j + BNXT_RING_TO_TC_OFF(bp, i);</div><div class='add'>+</div><div class='add'>+				bnapi2 = bp-&gt;bnapi[k];</div><div class='ctx'> 				txr-&gt;txq_index = i - bp-&gt;tx_nr_rings_xdp;</div><div class='del'>-				bp-&gt;bnapi[j]-&gt;tx_int = bnxt_tx_int;</div><div class='add'>+				txr-&gt;tx_napi_idx =</div><div class='add'>+					BNXT_RING_TO_TC(bp, txr-&gt;txq_index);</div><div class='add'>+				bnapi2-&gt;tx_ring[txr-&gt;tx_napi_idx] = txr;</div><div class='add'>+				bnapi2-&gt;tx_int = bnxt_tx_int;</div><div class='ctx'> 			} else {</div><div class='del'>-				bp-&gt;bnapi[j]-&gt;flags |= BNXT_NAPI_FLAG_XDP;</div><div class='del'>-				bp-&gt;bnapi[j]-&gt;tx_int = bnxt_tx_int_xdp;</div><div class='add'>+				bnapi2 = bp-&gt;bnapi[j];</div><div class='add'>+				bnapi2-&gt;flags |= BNXT_NAPI_FLAG_XDP;</div><div class='add'>+				bnapi2-&gt;tx_ring[0] = txr;</div><div class='add'>+				bnapi2-&gt;tx_int = bnxt_tx_int_xdp;</div><div class='add'>+				j++;</div><div class='ctx'> 			}</div><div class='add'>+			txr-&gt;bnapi = bnapi2;</div><div class='add'>+			if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='add'>+				txr-&gt;tx_cpr = &amp;bnapi2-&gt;cp_ring;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		rc = bnxt_alloc_stats(bp);</div><div class='hunk'>@@ -4898,6 +5216,8 @@ int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)</div><div class='ctx'> 	return hwrm_req_send(bp, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa);</div><div class='add'>+</div><div class='ctx'> static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwrm_tunnel_dst_port_free_input *req;</div><div class='hunk'>@@ -4927,6 +5247,11 @@ static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)</div><div class='ctx'> 		bp-&gt;nge_port = 0;</div><div class='ctx'> 		bp-&gt;nge_fw_dst_port_id = INVALID_HW_RING_ID;</div><div class='ctx'> 		break;</div><div class='add'>+	case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE:</div><div class='add'>+		req-&gt;tunnel_dst_port_id = cpu_to_le16(bp-&gt;vxlan_gpe_fw_dst_port_id);</div><div class='add'>+		bp-&gt;vxlan_gpe_port = 0;</div><div class='add'>+		bp-&gt;vxlan_gpe_fw_dst_port_id = INVALID_HW_RING_ID;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4935,6 +5260,8 @@ static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		netdev_err(bp-&gt;dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",</div><div class='ctx'> 			   rc);</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_TPA)</div><div class='add'>+		bnxt_set_tpa(bp, true);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4970,9 +5297,16 @@ static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,</div><div class='ctx'> 		bp-&gt;nge_port = port;</div><div class='ctx'> 		bp-&gt;nge_fw_dst_port_id = le16_to_cpu(resp-&gt;tunnel_dst_port_id);</div><div class='ctx'> 		break;</div><div class='add'>+	case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE:</div><div class='add'>+		bp-&gt;vxlan_gpe_port = port;</div><div class='add'>+		bp-&gt;vxlan_gpe_fw_dst_port_id =</div><div class='add'>+			le16_to_cpu(resp-&gt;tunnel_dst_port_id);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_TPA)</div><div class='add'>+		bnxt_set_tpa(bp, true);</div><div class='ctx'> </div><div class='ctx'> err_out:</div><div class='ctx'> 	hwrm_req_drop(bp, req);</div><div class='hunk'>@@ -4998,25 +5332,301 @@ static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)</div><div class='ctx'> 	return hwrm_req_send_silent(bp, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr)</div><div class='add'>+{</div><div class='add'>+	if (!atomic_dec_and_test(&amp;fltr-&gt;refcnt))</div><div class='add'>+		return;</div><div class='add'>+	spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	if (!test_and_clear_bit(BNXT_FLTR_INSERTED, &amp;fltr-&gt;base.state)) {</div><div class='add'>+		spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	hlist_del_rcu(&amp;fltr-&gt;base.hash);</div><div class='add'>+	if (fltr-&gt;base.flags) {</div><div class='add'>+		clear_bit(fltr-&gt;base.sw_id, bp-&gt;ntp_fltr_bmap);</div><div class='add'>+		bp-&gt;ntp_fltr_count--;</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	kfree_rcu(fltr, base.rcu);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct bnxt_l2_filter *__bnxt_lookup_l2_filter(struct bnxt *bp,</div><div class='add'>+						      struct bnxt_l2_key *key,</div><div class='add'>+						      u32 idx)</div><div class='add'>+{</div><div class='add'>+	struct hlist_head *head = &amp;bp-&gt;l2_fltr_hash_tbl[idx];</div><div class='add'>+	struct bnxt_l2_filter *fltr;</div><div class='add'>+</div><div class='add'>+	hlist_for_each_entry_rcu(fltr, head, base.hash) {</div><div class='add'>+		struct bnxt_l2_key *l2_key = &amp;fltr-&gt;l2_key;</div><div class='add'>+</div><div class='add'>+		if (ether_addr_equal(l2_key-&gt;dst_mac_addr, key-&gt;dst_mac_addr) &amp;&amp;</div><div class='add'>+		    l2_key-&gt;vlan == key-&gt;vlan)</div><div class='add'>+			return fltr;</div><div class='add'>+	}</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct bnxt_l2_filter *bnxt_lookup_l2_filter(struct bnxt *bp,</div><div class='add'>+						    struct bnxt_l2_key *key,</div><div class='add'>+						    u32 idx)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_l2_filter *fltr = NULL;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	fltr = __bnxt_lookup_l2_filter(bp, key, idx);</div><div class='add'>+	if (fltr)</div><div class='add'>+		atomic_inc(&amp;fltr-&gt;refcnt);</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+	return fltr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define BNXT_IPV4_4TUPLE(bp, fkeys)					\</div><div class='add'>+	(((fkeys)-&gt;basic.ip_proto == IPPROTO_TCP &amp;&amp;			\</div><div class='add'>+	  (bp)-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4) ||	\</div><div class='add'>+	 ((fkeys)-&gt;basic.ip_proto == IPPROTO_UDP &amp;&amp;			\</div><div class='add'>+	  (bp)-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4))</div><div class='add'>+</div><div class='add'>+#define BNXT_IPV6_4TUPLE(bp, fkeys)					\</div><div class='add'>+	(((fkeys)-&gt;basic.ip_proto == IPPROTO_TCP &amp;&amp;			\</div><div class='add'>+	  (bp)-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6) ||	\</div><div class='add'>+	 ((fkeys)-&gt;basic.ip_proto == IPPROTO_UDP &amp;&amp;			\</div><div class='add'>+	  (bp)-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6))</div><div class='add'>+</div><div class='add'>+static u32 bnxt_get_rss_flow_tuple_len(struct bnxt *bp, struct flow_keys *fkeys)</div><div class='add'>+{</div><div class='add'>+	if (fkeys-&gt;basic.n_proto == htons(ETH_P_IP)) {</div><div class='add'>+		if (BNXT_IPV4_4TUPLE(bp, fkeys))</div><div class='add'>+			return sizeof(fkeys-&gt;addrs.v4addrs) +</div><div class='add'>+			       sizeof(fkeys-&gt;ports);</div><div class='add'>+</div><div class='add'>+		if (bp-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)</div><div class='add'>+			return sizeof(fkeys-&gt;addrs.v4addrs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (fkeys-&gt;basic.n_proto == htons(ETH_P_IPV6)) {</div><div class='add'>+		if (BNXT_IPV6_4TUPLE(bp, fkeys))</div><div class='add'>+			return sizeof(fkeys-&gt;addrs.v6addrs) +</div><div class='add'>+			       sizeof(fkeys-&gt;ports);</div><div class='add'>+</div><div class='add'>+		if (bp-&gt;rss_hash_cfg &amp; VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)</div><div class='add'>+			return sizeof(fkeys-&gt;addrs.v6addrs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u32 bnxt_toeplitz(struct bnxt *bp, struct flow_keys *fkeys,</div><div class='add'>+			 const unsigned char *key)</div><div class='add'>+{</div><div class='add'>+	u64 prefix = bp-&gt;toeplitz_prefix, hash = 0;</div><div class='add'>+	struct bnxt_ipv4_tuple tuple4;</div><div class='add'>+	struct bnxt_ipv6_tuple tuple6;</div><div class='add'>+	int i, j, len = 0;</div><div class='add'>+	u8 *four_tuple;</div><div class='add'>+</div><div class='add'>+	len = bnxt_get_rss_flow_tuple_len(bp, fkeys);</div><div class='add'>+	if (!len)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (fkeys-&gt;basic.n_proto == htons(ETH_P_IP)) {</div><div class='add'>+		tuple4.v4addrs = fkeys-&gt;addrs.v4addrs;</div><div class='add'>+		tuple4.ports = fkeys-&gt;ports;</div><div class='add'>+		four_tuple = (unsigned char *)&amp;tuple4;</div><div class='add'>+	} else {</div><div class='add'>+		tuple6.v6addrs = fkeys-&gt;addrs.v6addrs;</div><div class='add'>+		tuple6.ports = fkeys-&gt;ports;</div><div class='add'>+		four_tuple = (unsigned char *)&amp;tuple6;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0, j = 8; i &lt; len; i++, j++) {</div><div class='add'>+		u8 byte = four_tuple[i];</div><div class='add'>+		int bit;</div><div class='add'>+</div><div class='add'>+		for (bit = 0; bit &lt; 8; bit++, prefix &lt;&lt;= 1, byte &lt;&lt;= 1) {</div><div class='add'>+			if (byte &amp; 0x80)</div><div class='add'>+				hash ^= prefix;</div><div class='add'>+		}</div><div class='add'>+		prefix |= (j &lt; HW_HASH_KEY_SIZE) ? key[j] : 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* The valid part of the hash is in the upper 32 bits. */</div><div class='add'>+	return (hash &gt;&gt; 32) &amp; BNXT_NTP_FLTR_HASH_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_RFS_ACCEL</div><div class='del'>-static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,</div><div class='del'>-					    struct bnxt_ntuple_filter *fltr)</div><div class='add'>+static struct bnxt_l2_filter *</div><div class='add'>+bnxt_lookup_l2_filter_from_key(struct bnxt *bp, struct bnxt_l2_key *key)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_l2_filter *fltr;</div><div class='add'>+	u32 idx;</div><div class='add'>+</div><div class='add'>+	idx = jhash2(&amp;key-&gt;filter_key, BNXT_L2_KEY_SIZE, bp-&gt;hash_seed) &amp;</div><div class='add'>+	      BNXT_L2_FLTR_HASH_MASK;</div><div class='add'>+	fltr = bnxt_lookup_l2_filter(bp, key, idx);</div><div class='add'>+	return fltr;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static int bnxt_init_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr,</div><div class='add'>+			       struct bnxt_l2_key *key, u32 idx)</div><div class='add'>+{</div><div class='add'>+	struct hlist_head *head;</div><div class='add'>+</div><div class='add'>+	ether_addr_copy(fltr-&gt;l2_key.dst_mac_addr, key-&gt;dst_mac_addr);</div><div class='add'>+	fltr-&gt;l2_key.vlan = key-&gt;vlan;</div><div class='add'>+	fltr-&gt;base.type = BNXT_FLTR_TYPE_L2;</div><div class='add'>+	if (fltr-&gt;base.flags) {</div><div class='add'>+		int bit_id;</div><div class='add'>+</div><div class='add'>+		bit_id = bitmap_find_free_region(bp-&gt;ntp_fltr_bmap,</div><div class='add'>+						 BNXT_MAX_FLTR, 0);</div><div class='add'>+		if (bit_id &lt; 0)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		fltr-&gt;base.sw_id = (u16)bit_id;</div><div class='add'>+	}</div><div class='add'>+	head = &amp;bp-&gt;l2_fltr_hash_tbl[idx];</div><div class='add'>+	hlist_add_head_rcu(&amp;fltr-&gt;base.hash, head);</div><div class='add'>+	set_bit(BNXT_FLTR_INSERTED, &amp;fltr-&gt;base.state);</div><div class='add'>+	atomic_set(&amp;fltr-&gt;refcnt, 1);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct bnxt_l2_filter *bnxt_alloc_l2_filter(struct bnxt *bp,</div><div class='add'>+						   struct bnxt_l2_key *key,</div><div class='add'>+						   gfp_t gfp)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_l2_filter *fltr;</div><div class='add'>+	u32 idx;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	idx = jhash2(&amp;key-&gt;filter_key, BNXT_L2_KEY_SIZE, bp-&gt;hash_seed) &amp;</div><div class='add'>+	      BNXT_L2_FLTR_HASH_MASK;</div><div class='add'>+	fltr = bnxt_lookup_l2_filter(bp, key, idx);</div><div class='add'>+	if (fltr)</div><div class='add'>+		return fltr;</div><div class='add'>+</div><div class='add'>+	fltr = kzalloc(sizeof(*fltr), gfp);</div><div class='add'>+	if (!fltr)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+	spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	rc = bnxt_init_l2_filter(bp, fltr, key, idx);</div><div class='add'>+	spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	if (rc) {</div><div class='add'>+		bnxt_del_l2_filter(bp, fltr);</div><div class='add'>+		fltr = ERR_PTR(rc);</div><div class='add'>+	}</div><div class='add'>+	return fltr;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16 bnxt_vf_target_id(struct bnxt_pf_info *pf, u16 vf_idx)</div><div class='add'>+{</div><div class='add'>+#ifdef CONFIG_BNXT_SRIOV</div><div class='add'>+	struct bnxt_vf_info *vf = &amp;pf-&gt;vf[vf_idx];</div><div class='add'>+</div><div class='add'>+	return vf-&gt;fw_fid;</div><div class='add'>+#else</div><div class='add'>+	return INVALID_HW_RING_ID;</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr)</div><div class='add'>+{</div><div class='add'>+	struct hwrm_cfa_l2_filter_free_input *req;</div><div class='add'>+	u16 target_id = 0xffff;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (fltr-&gt;base.flags &amp; BNXT_ACT_FUNC_DST) {</div><div class='add'>+		struct bnxt_pf_info *pf = &amp;bp-&gt;pf;</div><div class='add'>+</div><div class='add'>+		if (fltr-&gt;base.vf_idx &gt;= pf-&gt;active_vfs)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		target_id = bnxt_vf_target_id(pf, fltr-&gt;base.vf_idx);</div><div class='add'>+		if (target_id == INVALID_HW_RING_ID)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	req-&gt;target_id = cpu_to_le16(target_id);</div><div class='add'>+	req-&gt;l2_filter_id = fltr-&gt;base.filter_id;</div><div class='add'>+	return hwrm_req_send(bp, req);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr)</div><div class='add'>+{</div><div class='add'>+	struct hwrm_cfa_l2_filter_alloc_output *resp;</div><div class='add'>+	struct hwrm_cfa_l2_filter_alloc_input *req;</div><div class='add'>+	u16 target_id = 0xffff;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (fltr-&gt;base.flags &amp; BNXT_ACT_FUNC_DST) {</div><div class='add'>+		struct bnxt_pf_info *pf = &amp;bp-&gt;pf;</div><div class='add'>+</div><div class='add'>+		if (fltr-&gt;base.vf_idx &gt;= pf-&gt;active_vfs)</div><div class='add'>+			return -EINVAL;</div><div class='add'>+</div><div class='add'>+		target_id = bnxt_vf_target_id(pf, fltr-&gt;base.vf_idx);</div><div class='add'>+	}</div><div class='add'>+	rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	req-&gt;target_id = cpu_to_le16(target_id);</div><div class='add'>+	req-&gt;flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);</div><div class='add'>+</div><div class='add'>+	if (!BNXT_CHIP_TYPE_NITRO_A0(bp))</div><div class='add'>+		req-&gt;flags |=</div><div class='add'>+			cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);</div><div class='add'>+	req-&gt;dst_id = cpu_to_le16(fltr-&gt;base.fw_vnic_id);</div><div class='add'>+	req-&gt;enables =</div><div class='add'>+		cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |</div><div class='add'>+			    CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |</div><div class='add'>+			    CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);</div><div class='add'>+	ether_addr_copy(req-&gt;l2_addr, fltr-&gt;l2_key.dst_mac_addr);</div><div class='add'>+	eth_broadcast_addr(req-&gt;l2_addr_mask);</div><div class='add'>+</div><div class='add'>+	if (fltr-&gt;l2_key.vlan) {</div><div class='add'>+		req-&gt;enables |=</div><div class='add'>+			cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN |</div><div class='add'>+				CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK |</div><div class='add'>+				CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS);</div><div class='add'>+		req-&gt;num_vlans = 1;</div><div class='add'>+		req-&gt;l2_ivlan = cpu_to_le16(fltr-&gt;l2_key.vlan);</div><div class='add'>+		req-&gt;l2_ivlan_mask = cpu_to_le16(0xfff);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	resp = hwrm_req_hold(bp, req);</div><div class='add'>+	rc = hwrm_req_send(bp, req);</div><div class='add'>+	if (!rc) {</div><div class='add'>+		fltr-&gt;base.filter_id = resp-&gt;l2_filter_id;</div><div class='add'>+		set_bit(BNXT_FLTR_VALID, &amp;fltr-&gt;base.state);</div><div class='add'>+	}</div><div class='add'>+	hwrm_req_drop(bp, req);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,</div><div class='add'>+				     struct bnxt_ntuple_filter *fltr)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwrm_cfa_ntuple_filter_free_input *req;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='add'>+	set_bit(BNXT_FLTR_FW_DELETED, &amp;fltr-&gt;base.state);</div><div class='ctx'> 	rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	req-&gt;ntuple_filter_id = fltr-&gt;filter_id;</div><div class='add'>+	req-&gt;ntuple_filter_id = fltr-&gt;base.filter_id;</div><div class='ctx'> 	return hwrm_req_send(bp, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define BNXT_NTP_FLTR_FLAGS					\</div><div class='ctx'> 	(CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |	\</div><div class='ctx'> 	 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |	\</div><div class='del'>-	 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |	\</div><div class='ctx'> 	 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |	\</div><div class='ctx'> 	 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |	\</div><div class='ctx'> 	 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |	\</div><div class='hunk'>@@ -5032,12 +5642,21 @@ static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,</div><div class='ctx'> #define BNXT_NTP_TUNNEL_FLTR_FLAG				\</div><div class='ctx'> 		CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE</div><div class='ctx'> </div><div class='del'>-static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,</div><div class='del'>-					     struct bnxt_ntuple_filter *fltr)</div><div class='add'>+void bnxt_fill_ipv6_mask(__be32 mask[4])</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; 4; i++)</div><div class='add'>+		mask[i] = cpu_to_be32(~0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,</div><div class='add'>+				      struct bnxt_ntuple_filter *fltr)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwrm_cfa_ntuple_filter_alloc_output *resp;</div><div class='ctx'> 	struct hwrm_cfa_ntuple_filter_alloc_input *req;</div><div class='ctx'> 	struct flow_keys *keys = &amp;fltr-&gt;fkeys;</div><div class='add'>+	struct bnxt_l2_filter *l2_fltr;</div><div class='ctx'> 	struct bnxt_vnic_info *vnic;</div><div class='ctx'> 	u32 flags = 0;</div><div class='ctx'> 	int rc;</div><div class='hunk'>@@ -5046,42 +5665,47 @@ static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	req-&gt;l2_filter_id = bp-&gt;vnic_info[0].fw_l2_filter_id[fltr-&gt;l2_fltr_idx];</div><div class='add'>+	l2_fltr = fltr-&gt;l2_fltr;</div><div class='add'>+	req-&gt;l2_filter_id = l2_fltr-&gt;base.filter_id;</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {</div><div class='ctx'> 		flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;</div><div class='del'>-		req-&gt;dst_id = cpu_to_le16(fltr-&gt;rxq);</div><div class='add'>+		req-&gt;dst_id = cpu_to_le16(fltr-&gt;base.rxq);</div><div class='ctx'> 	} else {</div><div class='del'>-		vnic = &amp;bp-&gt;vnic_info[fltr-&gt;rxq + 1];</div><div class='add'>+		vnic = &amp;bp-&gt;vnic_info[fltr-&gt;base.rxq + 1];</div><div class='ctx'> 		req-&gt;dst_id = cpu_to_le16(vnic-&gt;fw_vnic_id);</div><div class='ctx'> 	}</div><div class='ctx'> 	req-&gt;flags = cpu_to_le32(flags);</div><div class='ctx'> 	req-&gt;enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);</div><div class='ctx'> </div><div class='ctx'> 	req-&gt;ethertype = htons(ETH_P_IP);</div><div class='del'>-	memcpy(req-&gt;src_macaddr, fltr-&gt;src_mac_addr, ETH_ALEN);</div><div class='ctx'> 	req-&gt;ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;</div><div class='ctx'> 	req-&gt;ip_protocol = keys-&gt;basic.ip_proto;</div><div class='ctx'> </div><div class='ctx'> 	if (keys-&gt;basic.n_proto == htons(ETH_P_IPV6)) {</div><div class='del'>-		int i;</div><div class='del'>-</div><div class='ctx'> 		req-&gt;ethertype = htons(ETH_P_IPV6);</div><div class='ctx'> 		req-&gt;ip_addr_type =</div><div class='ctx'> 			CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;</div><div class='del'>-		*(struct in6_addr *)&amp;req-&gt;src_ipaddr[0] =</div><div class='del'>-			keys-&gt;addrs.v6addrs.src;</div><div class='del'>-		*(struct in6_addr *)&amp;req-&gt;dst_ipaddr[0] =</div><div class='del'>-			keys-&gt;addrs.v6addrs.dst;</div><div class='del'>-		for (i = 0; i &lt; 4; i++) {</div><div class='del'>-			req-&gt;src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);</div><div class='del'>-			req-&gt;dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) {</div><div class='add'>+			*(struct in6_addr *)&amp;req-&gt;src_ipaddr[0] =</div><div class='add'>+				keys-&gt;addrs.v6addrs.src;</div><div class='add'>+			bnxt_fill_ipv6_mask(req-&gt;src_ipaddr_mask);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) {</div><div class='add'>+			*(struct in6_addr *)&amp;req-&gt;dst_ipaddr[0] =</div><div class='add'>+				keys-&gt;addrs.v6addrs.dst;</div><div class='add'>+			bnxt_fill_ipv6_mask(req-&gt;dst_ipaddr_mask);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		req-&gt;src_ipaddr[0] = keys-&gt;addrs.v4addrs.src;</div><div class='del'>-		req-&gt;src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);</div><div class='del'>-		req-&gt;dst_ipaddr[0] = keys-&gt;addrs.v4addrs.dst;</div><div class='del'>-		req-&gt;dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) {</div><div class='add'>+			req-&gt;src_ipaddr[0] = keys-&gt;addrs.v4addrs.src;</div><div class='add'>+			req-&gt;src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) {</div><div class='add'>+			req-&gt;dst_ipaddr[0] = keys-&gt;addrs.v4addrs.dst;</div><div class='add'>+			req-&gt;dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (keys-&gt;control.flags &amp; FLOW_DIS_ENCAPSULATION) {</div><div class='ctx'> 		req-&gt;enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);</div><div class='hunk'>@@ -5089,80 +5713,85 @@ static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,</div><div class='ctx'> 			CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	req-&gt;src_port = keys-&gt;ports.src;</div><div class='del'>-	req-&gt;src_port_mask = cpu_to_be16(0xffff);</div><div class='del'>-	req-&gt;dst_port = keys-&gt;ports.dst;</div><div class='del'>-	req-&gt;dst_port_mask = cpu_to_be16(0xffff);</div><div class='add'>+	if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_PORT) {</div><div class='add'>+		req-&gt;src_port = keys-&gt;ports.src;</div><div class='add'>+		req-&gt;src_port_mask = cpu_to_be16(0xffff);</div><div class='add'>+	}</div><div class='add'>+	if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_PORT) {</div><div class='add'>+		req-&gt;dst_port = keys-&gt;ports.dst;</div><div class='add'>+		req-&gt;dst_port_mask = cpu_to_be16(0xffff);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	resp = hwrm_req_hold(bp, req);</div><div class='ctx'> 	rc = hwrm_req_send(bp, req);</div><div class='ctx'> 	if (!rc)</div><div class='del'>-		fltr-&gt;filter_id = resp-&gt;ntuple_filter_id;</div><div class='add'>+		fltr-&gt;base.filter_id = resp-&gt;ntuple_filter_id;</div><div class='ctx'> 	hwrm_req_drop(bp, req);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,</div><div class='ctx'> 				     const u8 *mac_addr)</div><div class='ctx'> {</div><div class='del'>-	struct hwrm_cfa_l2_filter_alloc_output *resp;</div><div class='del'>-	struct hwrm_cfa_l2_filter_alloc_input *req;</div><div class='add'>+	struct bnxt_l2_filter *fltr;</div><div class='add'>+	struct bnxt_l2_key key;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='add'>+	ether_addr_copy(key.dst_mac_addr, mac_addr);</div><div class='add'>+	key.vlan = 0;</div><div class='add'>+	fltr = bnxt_alloc_l2_filter(bp, &amp;key, GFP_KERNEL);</div><div class='add'>+	if (IS_ERR(fltr))</div><div class='add'>+		return PTR_ERR(fltr);</div><div class='ctx'> </div><div class='del'>-	req-&gt;flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);</div><div class='del'>-	if (!BNXT_CHIP_TYPE_NITRO_A0(bp))</div><div class='del'>-		req-&gt;flags |=</div><div class='del'>-			cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);</div><div class='del'>-	req-&gt;dst_id = cpu_to_le16(bp-&gt;vnic_info[vnic_id].fw_vnic_id);</div><div class='del'>-	req-&gt;enables =</div><div class='del'>-		cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |</div><div class='del'>-			    CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |</div><div class='del'>-			    CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);</div><div class='del'>-	memcpy(req-&gt;l2_addr, mac_addr, ETH_ALEN);</div><div class='del'>-	req-&gt;l2_addr_mask[0] = 0xff;</div><div class='del'>-	req-&gt;l2_addr_mask[1] = 0xff;</div><div class='del'>-	req-&gt;l2_addr_mask[2] = 0xff;</div><div class='del'>-	req-&gt;l2_addr_mask[3] = 0xff;</div><div class='del'>-	req-&gt;l2_addr_mask[4] = 0xff;</div><div class='del'>-	req-&gt;l2_addr_mask[5] = 0xff;</div><div class='del'>-</div><div class='del'>-	resp = hwrm_req_hold(bp, req);</div><div class='del'>-	rc = hwrm_req_send(bp, req);</div><div class='del'>-	if (!rc)</div><div class='del'>-		bp-&gt;vnic_info[vnic_id].fw_l2_filter_id[idx] =</div><div class='del'>-							resp-&gt;l2_filter_id;</div><div class='del'>-	hwrm_req_drop(bp, req);</div><div class='add'>+	fltr-&gt;base.fw_vnic_id = bp-&gt;vnic_info[vnic_id].fw_vnic_id;</div><div class='add'>+	rc = bnxt_hwrm_l2_filter_alloc(bp, fltr);</div><div class='add'>+	if (rc)</div><div class='add'>+		bnxt_del_l2_filter(bp, fltr);</div><div class='add'>+	else</div><div class='add'>+		bp-&gt;vnic_info[vnic_id].l2_filters[idx] = fltr;</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)</div><div class='add'>+static void bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	struct hwrm_cfa_l2_filter_free_input *req;</div><div class='ctx'> 	u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */</div><div class='del'>-	int rc;</div><div class='ctx'> </div><div class='ctx'> 	/* Any associated ntuple filters will also be cleared by firmware. */</div><div class='del'>-	rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='del'>-	hwrm_req_hold(bp, req);</div><div class='ctx'> 	for (i = 0; i &lt; num_of_vnics; i++) {</div><div class='ctx'> 		struct bnxt_vnic_info *vnic = &amp;bp-&gt;vnic_info[i];</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; vnic-&gt;uc_filter_count; j++) {</div><div class='del'>-			req-&gt;l2_filter_id = vnic-&gt;fw_l2_filter_id[j];</div><div class='add'>+			struct bnxt_l2_filter *fltr = vnic-&gt;l2_filters[j];</div><div class='ctx'> </div><div class='del'>-			rc = hwrm_req_send(bp, req);</div><div class='add'>+			bnxt_hwrm_l2_filter_free(bp, fltr);</div><div class='add'>+			bnxt_del_l2_filter(bp, fltr);</div><div class='ctx'> 		}</div><div class='ctx'> 		vnic-&gt;uc_filter_count = 0;</div><div class='ctx'> 	}</div><div class='del'>-	hwrm_req_drop(bp, req);</div><div class='del'>-	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define BNXT_DFLT_TUNL_TPA_BMAP				\</div><div class='add'>+	(VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE |	\</div><div class='add'>+	 VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 |	\</div><div class='add'>+	 VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6)</div><div class='add'>+</div><div class='add'>+static void bnxt_hwrm_vnic_update_tunl_tpa(struct bnxt *bp,</div><div class='add'>+					   struct hwrm_vnic_tpa_cfg_input *req)</div><div class='add'>+{</div><div class='add'>+	u32 tunl_tpa_bmap = BNXT_DFLT_TUNL_TPA_BMAP;</div><div class='add'>+</div><div class='add'>+	if (!(bp-&gt;fw_cap &amp; BNXT_FW_CAP_VNIC_TUNNEL_TPA))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;vxlan_port)</div><div class='add'>+		tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN;</div><div class='add'>+	if (bp-&gt;vxlan_gpe_port)</div><div class='add'>+		tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE;</div><div class='add'>+	if (bp-&gt;nge_port)</div><div class='add'>+		tunl_tpa_bmap |= VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE;</div><div class='add'>+</div><div class='add'>+	req-&gt;enables |= cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN);</div><div class='add'>+	req-&gt;tnl_tpa_en_bitmap = cpu_to_le32(tunl_tpa_bmap);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)</div><div class='hunk'>@@ -5211,7 +5840,7 @@ static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)</div><div class='ctx'> 			nsegs = (MAX_SKB_FRAGS - n) / n;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			segs = MAX_TPA_SEGS_P5;</div><div class='ctx'> 			max_aggs = bp-&gt;max_tpa;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -5221,6 +5850,7 @@ static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)</div><div class='ctx'> 		req-&gt;max_aggs = cpu_to_le16(max_aggs);</div><div class='ctx'> </div><div class='ctx'> 		req-&gt;min_agg_len = cpu_to_le32(512);</div><div class='add'>+		bnxt_hwrm_vnic_update_tunl_tpa(bp, req);</div><div class='ctx'> 	}</div><div class='ctx'> 	req-&gt;vnic_id = cpu_to_le16(vnic-&gt;fw_vnic_id);</div><div class='ctx'> </div><div class='hunk'>@@ -5237,35 +5867,25 @@ static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)</div><div class='ctx'> </div><div class='ctx'> static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		struct bnxt_napi *bnapi = rxr-&gt;bnapi;</div><div class='del'>-		struct bnxt_cp_ring_info *cpr;</div><div class='del'>-</div><div class='del'>-		cpr = bnapi-&gt;cp_ring.cp_ring_arr[BNXT_RX_HDL];</div><div class='del'>-		return cpr-&gt;cp_ring_struct.fw_ring_id;</div><div class='del'>-	} else {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='add'>+		return rxr-&gt;rx_cpr-&gt;cp_ring_struct.fw_ring_id;</div><div class='add'>+	else</div><div class='ctx'> 		return bnxt_cp_ring_from_grp(bp, &amp;rxr-&gt;rx_ring_struct);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		struct bnxt_napi *bnapi = txr-&gt;bnapi;</div><div class='del'>-		struct bnxt_cp_ring_info *cpr;</div><div class='del'>-</div><div class='del'>-		cpr = bnapi-&gt;cp_ring.cp_ring_arr[BNXT_TX_HDL];</div><div class='del'>-		return cpr-&gt;cp_ring_struct.fw_ring_id;</div><div class='del'>-	} else {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='add'>+		return txr-&gt;tx_cpr-&gt;cp_ring_struct.fw_ring_id;</div><div class='add'>+	else</div><div class='ctx'> 		return bnxt_cp_ring_from_grp(bp, &amp;txr-&gt;tx_ring_struct);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	int entries;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;</div><div class='ctx'> 	else</div><div class='ctx'> 		entries = HW_HASH_INDEX_SIZE;</div><div class='hunk'>@@ -5315,7 +5935,7 @@ static u16 bnxt_get_max_rss_ring(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);</div><div class='ctx'> 	if (BNXT_CHIP_TYPE_NITRO_A0(bp))</div><div class='ctx'> 		return 2;</div><div class='hunk'>@@ -5361,7 +5981,7 @@ static void</div><div class='ctx'> __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,</div><div class='ctx'> 			 struct bnxt_vnic_info *vnic)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		bnxt_fill_hw_rss_tbl_p5(bp, vnic);</div><div class='ctx'> 	else</div><div class='ctx'> 		bnxt_fill_hw_rss_tbl(bp, vnic);</div><div class='hunk'>@@ -5386,7 +6006,7 @@ static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)</div><div class='ctx'> 	struct hwrm_vnic_rss_cfg_input *req;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) ||</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) ||</div><div class='ctx'> 	    vnic-&gt;fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -5551,7 +6171,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		struct bnxt_rx_ring_info *rxr = &amp;bp-&gt;rx_ring[0];</div><div class='ctx'> </div><div class='ctx'> 		req-&gt;default_rx_ring_id =</div><div class='hunk'>@@ -5651,7 +6271,7 @@ static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		goto vnic_no_ring_grps;</div><div class='ctx'> </div><div class='ctx'> 	/* map ring groups to this vnic */</div><div class='hunk'>@@ -5686,7 +6306,8 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	bp-&gt;hw_ring_stats_size = sizeof(struct ctx_hw_stats);</div><div class='del'>-	bp-&gt;flags &amp;= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);</div><div class='add'>+	bp-&gt;flags &amp;= ~BNXT_FLAG_ROCE_MIRROR_CAP;</div><div class='add'>+	bp-&gt;rss_cap &amp;= ~BNXT_RSS_CAP_NEW_RSS_CAP;</div><div class='ctx'> 	if (bp-&gt;hwrm_spec_code &lt; 0x10600)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -5699,9 +6320,9 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)</div><div class='ctx'> 	if (!rc) {</div><div class='ctx'> 		u32 flags = le32_to_cpu(resp-&gt;flags);</div><div class='ctx'> </div><div class='del'>-		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp;</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp;</div><div class='ctx'> 		    (flags &amp; VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))</div><div class='del'>-			bp-&gt;flags |= BNXT_FLAG_NEW_RSS_CAP;</div><div class='add'>+			bp-&gt;rss_cap |= BNXT_RSS_CAP_NEW_RSS_CAP;</div><div class='ctx'> 		if (flags &amp;</div><div class='ctx'> 		    VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)</div><div class='ctx'> 			bp-&gt;flags |= BNXT_FLAG_ROCE_MIRROR_CAP;</div><div class='hunk'>@@ -5710,18 +6331,22 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)</div><div class='ctx'> 		 * VLAN_STRIP_CAP properly.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if ((flags &amp; VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||</div><div class='del'>-		    (BNXT_CHIP_P5_THOR(bp) &amp;&amp;</div><div class='add'>+		    (BNXT_CHIP_P5(bp) &amp;&amp;</div><div class='ctx'> 		     !(bp-&gt;fw_cap &amp; BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))</div><div class='ctx'> 			bp-&gt;fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;</div><div class='ctx'> 		if (flags &amp; VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP)</div><div class='del'>-			bp-&gt;fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA;</div><div class='add'>+			bp-&gt;rss_cap |= BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA;</div><div class='add'>+		if (flags &amp; VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED)</div><div class='add'>+			bp-&gt;rss_cap |= BNXT_RSS_CAP_RSS_TCAM;</div><div class='ctx'> 		bp-&gt;max_tpa_v2 = le16_to_cpu(resp-&gt;max_aggs_supported);</div><div class='ctx'> 		if (bp-&gt;max_tpa_v2) {</div><div class='del'>-			if (BNXT_CHIP_P5_THOR(bp))</div><div class='add'>+			if (BNXT_CHIP_P5(bp))</div><div class='ctx'> 				bp-&gt;hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;</div><div class='ctx'> 			else</div><div class='del'>-				bp-&gt;hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;</div><div class='add'>+				bp-&gt;hw_ring_stats_size = BNXT_RING_STATS_SIZE_P7;</div><div class='ctx'> 		}</div><div class='add'>+		if (flags &amp; VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP)</div><div class='add'>+			bp-&gt;fw_cap |= BNXT_FW_CAP_VNIC_TUNNEL_TPA;</div><div class='ctx'> 	}</div><div class='ctx'> 	hwrm_req_drop(bp, req);</div><div class='ctx'> 	return rc;</div><div class='hunk'>@@ -5734,7 +6359,7 @@ static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)</div><div class='ctx'> 	int rc;</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC);</div><div class='hunk'>@@ -5767,7 +6392,7 @@ static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)</div><div class='ctx'> 	struct hwrm_ring_grp_free_input *req;</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='del'>-	if (!bp-&gt;grp_info || (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!bp-&gt;grp_info || (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE))</div><div class='hunk'>@@ -5827,12 +6452,15 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp,</div><div class='ctx'> 		req-&gt;length = cpu_to_le32(bp-&gt;tx_ring_mask + 1);</div><div class='ctx'> 		req-&gt;stat_ctx_id = cpu_to_le32(grp_info-&gt;fw_stats_ctx);</div><div class='ctx'> 		req-&gt;queue_id = cpu_to_le16(ring-&gt;queue_id);</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_TX_COAL_CMPL)</div><div class='add'>+			req-&gt;cmpl_coal_cnt =</div><div class='add'>+				RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	case HWRM_RING_ALLOC_RX:</div><div class='ctx'> 		req-&gt;ring_type = RING_ALLOC_REQ_RING_TYPE_RX;</div><div class='ctx'> 		req-&gt;length = cpu_to_le32(bp-&gt;rx_ring_mask + 1);</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			u16 flags = 0;</div><div class='ctx'> </div><div class='ctx'> 			/* Association of rx ring with stats context */</div><div class='hunk'>@@ -5847,7 +6475,7 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp,</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HWRM_RING_ALLOC_AGG:</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			req-&gt;ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;</div><div class='ctx'> 			/* Association of agg ring with rx ring */</div><div class='ctx'> 			grp_info = &amp;bp-&gt;grp_info[ring-&gt;grp_idx];</div><div class='hunk'>@@ -5865,7 +6493,7 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp,</div><div class='ctx'> 	case HWRM_RING_ALLOC_CMPL:</div><div class='ctx'> 		req-&gt;ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;</div><div class='ctx'> 		req-&gt;length = cpu_to_le32(bp-&gt;cp_ring_mask + 1);</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			/* Association of cp ring with nq */</div><div class='ctx'> 			grp_info = &amp;bp-&gt;grp_info[map_index];</div><div class='ctx'> 			req-&gt;nq_ring_id = cpu_to_le16(grp_info-&gt;cp_fw_ring_id);</div><div class='hunk'>@@ -5933,14 +6561,34 @@ static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void bnxt_set_db_mask(struct bnxt *bp, struct bnxt_db_info *db,</div><div class='add'>+			     u32 ring_type)</div><div class='add'>+{</div><div class='add'>+	switch (ring_type) {</div><div class='add'>+	case HWRM_RING_ALLOC_TX:</div><div class='add'>+		db-&gt;db_ring_mask = bp-&gt;tx_ring_mask;</div><div class='add'>+		break;</div><div class='add'>+	case HWRM_RING_ALLOC_RX:</div><div class='add'>+		db-&gt;db_ring_mask = bp-&gt;rx_ring_mask;</div><div class='add'>+		break;</div><div class='add'>+	case HWRM_RING_ALLOC_AGG:</div><div class='add'>+		db-&gt;db_ring_mask = bp-&gt;rx_agg_ring_mask;</div><div class='add'>+		break;</div><div class='add'>+	case HWRM_RING_ALLOC_CMPL:</div><div class='add'>+	case HWRM_RING_ALLOC_NQ:</div><div class='add'>+		db-&gt;db_ring_mask = bp-&gt;cp_ring_mask;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P7) {</div><div class='add'>+		db-&gt;db_epoch_mask = db-&gt;db_ring_mask + 1;</div><div class='add'>+		db-&gt;db_epoch_shift = DBR_EPOCH_SFT - ilog2(db-&gt;db_epoch_mask);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,</div><div class='ctx'> 			u32 map_idx, u32 xid)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		if (BNXT_PF(bp))</div><div class='del'>-			db-&gt;doorbell = bp-&gt;bar1 + DB_PF_OFFSET_P5;</div><div class='del'>-		else</div><div class='del'>-			db-&gt;doorbell = bp-&gt;bar1 + DB_VF_OFFSET_P5;</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		switch (ring_type) {</div><div class='ctx'> 		case HWRM_RING_ALLOC_TX:</div><div class='ctx'> 			db-&gt;db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;</div><div class='hunk'>@@ -5957,6 +6605,11 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 		db-&gt;db_key64 |= (u64)xid &lt;&lt; DBR_XID_SFT;</div><div class='add'>+</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P7)</div><div class='add'>+			db-&gt;db_key64 |= DBR_VALID;</div><div class='add'>+</div><div class='add'>+		db-&gt;doorbell = bp-&gt;bar1 + bp-&gt;db_offset;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		db-&gt;doorbell = bp-&gt;bar1 + map_idx * 0x80;</div><div class='ctx'> 		switch (ring_type) {</div><div class='hunk'>@@ -5972,6 +6625,7 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	bnxt_set_db_mask(bp, db, ring_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_hwrm_ring_alloc(struct bnxt *bp)</div><div class='hunk'>@@ -5980,7 +6634,7 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)</div><div class='ctx'> 	int i, rc = 0;</div><div class='ctx'> 	u32 type;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		type = HWRM_RING_ALLOC_NQ;</div><div class='ctx'> 	else</div><div class='ctx'> 		type = HWRM_RING_ALLOC_CMPL;</div><div class='hunk'>@@ -6016,15 +6670,13 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)</div><div class='ctx'> 		struct bnxt_ring_struct *ring;</div><div class='ctx'> 		u32 map_idx;</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = txr-&gt;tx_cpr;</div><div class='ctx'> 			struct bnxt_napi *bnapi = txr-&gt;bnapi;</div><div class='del'>-			struct bnxt_cp_ring_info *cpr, *cpr2;</div><div class='ctx'> 			u32 type2 = HWRM_RING_ALLOC_CMPL;</div><div class='ctx'> </div><div class='del'>-			cpr = &amp;bnapi-&gt;cp_ring;</div><div class='del'>-			cpr2 = cpr-&gt;cp_ring_arr[BNXT_TX_HDL];</div><div class='ctx'> 			ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='del'>-			ring-&gt;handle = BNXT_TX_HDL;</div><div class='add'>+			ring-&gt;handle = BNXT_SET_NQ_HDL(cpr2);</div><div class='ctx'> 			map_idx = bnapi-&gt;index;</div><div class='ctx'> 			rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);</div><div class='ctx'> 			if (rc)</div><div class='hunk'>@@ -6056,14 +6708,12 @@ static int bnxt_hwrm_ring_alloc(struct bnxt *bp)</div><div class='ctx'> 		if (!agg_rings)</div><div class='ctx'> 			bnxt_db_write(bp, &amp;rxr-&gt;rx_db, rxr-&gt;rx_prod);</div><div class='ctx'> 		bp-&gt;grp_info[map_idx].rx_fw_ring_id = ring-&gt;fw_ring_id;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr = &amp;bnapi-&gt;cp_ring;</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = rxr-&gt;rx_cpr;</div><div class='ctx'> 			u32 type2 = HWRM_RING_ALLOC_CMPL;</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2;</div><div class='ctx'> </div><div class='del'>-			cpr2 = cpr-&gt;cp_ring_arr[BNXT_RX_HDL];</div><div class='ctx'> 			ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='del'>-			ring-&gt;handle = BNXT_RX_HDL;</div><div class='add'>+			ring-&gt;handle = BNXT_SET_NQ_HDL(cpr2);</div><div class='ctx'> 			rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);</div><div class='ctx'> 			if (rc)</div><div class='ctx'> 				goto err_out;</div><div class='hunk'>@@ -6171,7 +6821,7 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		type = RING_FREE_REQ_RING_TYPE_RX_AGG;</div><div class='ctx'> 	else</div><div class='ctx'> 		type = RING_FREE_REQ_RING_TYPE_RX;</div><div class='hunk'>@@ -6198,7 +6848,7 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)</div><div class='ctx'> 	 */</div><div class='ctx'> 	bnxt_disable_int_sync(bp);</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		type = RING_FREE_REQ_RING_TYPE_NQ;</div><div class='ctx'> 	else</div><div class='ctx'> 		type = RING_FREE_REQ_RING_TYPE_L2_CMPL;</div><div class='hunk'>@@ -6208,18 +6858,16 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)</div><div class='ctx'> 		struct bnxt_ring_struct *ring;</div><div class='ctx'> 		int j;</div><div class='ctx'> </div><div class='del'>-		for (j = 0; j &lt; 2; j++) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[j];</div><div class='add'>+		for (j = 0; j &lt; cpr-&gt;cp_ring_count &amp;&amp; cpr-&gt;cp_ring_arr; j++) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[j];</div><div class='ctx'> </div><div class='del'>-			if (cpr2) {</div><div class='del'>-				ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='del'>-				if (ring-&gt;fw_ring_id == INVALID_HW_RING_ID)</div><div class='del'>-					continue;</div><div class='del'>-				hwrm_ring_free_send_msg(bp, ring,</div><div class='del'>-					RING_FREE_REQ_RING_TYPE_L2_CMPL,</div><div class='del'>-					INVALID_HW_RING_ID);</div><div class='del'>-				ring-&gt;fw_ring_id = INVALID_HW_RING_ID;</div><div class='del'>-			}</div><div class='add'>+			ring = &amp;cpr2-&gt;cp_ring_struct;</div><div class='add'>+			if (ring-&gt;fw_ring_id == INVALID_HW_RING_ID)</div><div class='add'>+				continue;</div><div class='add'>+			hwrm_ring_free_send_msg(bp, ring,</div><div class='add'>+						RING_FREE_REQ_RING_TYPE_L2_CMPL,</div><div class='add'>+						INVALID_HW_RING_ID);</div><div class='add'>+			ring-&gt;fw_ring_id = INVALID_HW_RING_ID;</div><div class='ctx'> 		}</div><div class='ctx'> 		ring = &amp;cpr-&gt;cp_ring_struct;</div><div class='ctx'> 		if (ring-&gt;fw_ring_id != INVALID_HW_RING_ID) {</div><div class='hunk'>@@ -6231,6 +6879,8 @@ static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int __bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='add'>+			     bool shared);</div><div class='ctx'> static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='ctx'> 			   bool shared);</div><div class='ctx'> </div><div class='hunk'>@@ -6267,14 +6917,16 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp)</div><div class='ctx'> 		cp = le16_to_cpu(resp-&gt;alloc_cmpl_rings);</div><div class='ctx'> 		stats = le16_to_cpu(resp-&gt;alloc_stat_ctx);</div><div class='ctx'> 		hw_resc-&gt;resv_irqs = cp;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			int rx = hw_resc-&gt;resv_rx_rings;</div><div class='ctx'> 			int tx = hw_resc-&gt;resv_tx_rings;</div><div class='ctx'> </div><div class='ctx'> 			if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 				rx &gt;&gt;= 1;</div><div class='ctx'> 			if (cp &lt; (rx + tx)) {</div><div class='del'>-				bnxt_trim_rings(bp, &amp;rx, &amp;tx, cp, false);</div><div class='add'>+				rc = __bnxt_trim_rings(bp, &amp;rx, &amp;tx, cp, false);</div><div class='add'>+				if (rc)</div><div class='add'>+					return rc;</div><div class='ctx'> 				if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 					rx &lt;&lt;= 1;</div><div class='ctx'> 				hw_resc-&gt;resv_rx_rings = rx;</div><div class='hunk'>@@ -6331,7 +6983,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 	if (BNXT_NEW_RM(bp)) {</div><div class='ctx'> 		enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;</div><div class='ctx'> 		enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;</div><div class='ctx'> 			enables |= tx_rings + ring_grps ?</div><div class='ctx'> 				   FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;</div><div class='hunk'>@@ -6347,7 +6999,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 		enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;</div><div class='ctx'> </div><div class='ctx'> 		req-&gt;num_rx_rings = cpu_to_le16(rx_rings);</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 			req-&gt;num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);</div><div class='ctx'> 			req-&gt;num_msix = cpu_to_le16(cp_rings);</div><div class='ctx'> 			req-&gt;num_rsscos_ctxs =</div><div class='hunk'>@@ -6356,7 +7008,7 @@ __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 			req-&gt;num_cmpl_rings = cpu_to_le16(cp_rings);</div><div class='ctx'> 			req-&gt;num_hw_ring_grps = cpu_to_le16(ring_grps);</div><div class='ctx'> 			req-&gt;num_rsscos_ctxs = cpu_to_le16(1);</div><div class='del'>-			if (!(bp-&gt;flags &amp; BNXT_FLAG_NEW_RSS_CAP) &amp;&amp;</div><div class='add'>+			if (!(bp-&gt;rss_cap &amp; BNXT_RSS_CAP_NEW_RSS_CAP) &amp;&amp;</div><div class='ctx'> 			    bnxt_rfs_supported(bp))</div><div class='ctx'> 				req-&gt;num_rsscos_ctxs =</div><div class='ctx'> 					cpu_to_le16(ring_grps + 1);</div><div class='hunk'>@@ -6382,7 +7034,7 @@ __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 	enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |</div><div class='ctx'> 			      FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;</div><div class='ctx'> 	enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		enables |= tx_rings + ring_grps ?</div><div class='ctx'> 			   FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -6397,7 +7049,7 @@ __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 	req-&gt;num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);</div><div class='ctx'> 	req-&gt;num_tx_rings = cpu_to_le16(tx_rings);</div><div class='ctx'> 	req-&gt;num_rx_rings = cpu_to_le16(rx_rings);</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		req-&gt;num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);</div><div class='ctx'> 		req-&gt;num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -6493,7 +7145,7 @@ static int bnxt_cp_rings_in_use(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	int cp;</div><div class='ctx'> </div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		return bnxt_nq_rings_in_use(bp);</div><div class='ctx'> </div><div class='ctx'> 	cp = bp-&gt;tx_nr_rings + bp-&gt;rx_nr_rings;</div><div class='hunk'>@@ -6550,7 +7202,8 @@ static bool bnxt_need_reserve_rings(struct bnxt *bp)</div><div class='ctx'> 		bnxt_check_rss_tbl_no_rmgr(bp);</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_RFS) &amp;&amp; !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_RFS) &amp;&amp;</div><div class='add'>+	    !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		vnic = rx + 1;</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 		rx &lt;&lt;= 1;</div><div class='hunk'>@@ -6558,9 +7211,9 @@ static bool bnxt_need_reserve_rings(struct bnxt *bp)</div><div class='ctx'> 	if (hw_resc-&gt;resv_rx_rings != rx || hw_resc-&gt;resv_cp_rings != cp ||</div><div class='ctx'> 	    hw_resc-&gt;resv_vnics != vnic || hw_resc-&gt;resv_stat_ctxs != stat ||</div><div class='ctx'> 	    (hw_resc-&gt;resv_hw_ring_grps != grp &amp;&amp;</div><div class='del'>-	     !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)))</div><div class='add'>+	     !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)))</div><div class='ctx'> 		return true;</div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp; BNXT_PF(bp) &amp;&amp;</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp; BNXT_PF(bp) &amp;&amp;</div><div class='ctx'> 	    hw_resc-&gt;resv_irqs != nq)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -6575,13 +7228,15 @@ static int __bnxt_reserve_rings(struct bnxt *bp)</div><div class='ctx'> 	int grp, rx_rings, rc;</div><div class='ctx'> 	int vnic = 1, stat;</div><div class='ctx'> 	bool sh = false;</div><div class='add'>+	int tx_cp;</div><div class='ctx'> </div><div class='ctx'> 	if (!bnxt_need_reserve_rings(bp))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_SHARED_RINGS)</div><div class='ctx'> 		sh = true;</div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_RFS) &amp;&amp; !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_RFS) &amp;&amp;</div><div class='add'>+	    !(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		vnic = rx + 1;</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 		rx &lt;&lt;= 1;</div><div class='hunk'>@@ -6624,7 +7279,8 @@ static int __bnxt_reserve_rings(struct bnxt *bp)</div><div class='ctx'> 	rc = bnxt_trim_rings(bp, &amp;rx_rings, &amp;tx, cp, sh);</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 		rx = rx_rings &lt;&lt; 1;</div><div class='del'>-	cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;</div><div class='add'>+	tx_cp = bnxt_num_tx_to_cp(bp, tx);</div><div class='add'>+	cp = sh ? max_t(int, tx_cp, rx_rings) : tx_cp + rx_rings;</div><div class='ctx'> 	bp-&gt;tx_nr_rings = tx;</div><div class='ctx'> </div><div class='ctx'> 	/* If we cannot reserve all the RX rings, reset the RSS map only</div><div class='hunk'>@@ -6671,7 +7327,7 @@ static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 		FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |</div><div class='ctx'> 		FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |</div><div class='ctx'> 		FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;</div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;</div><div class='ctx'> </div><div class='ctx'> 	req-&gt;flags = cpu_to_le32(flags);</div><div class='hunk'>@@ -6693,7 +7349,7 @@ static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,</div><div class='ctx'> 			 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |</div><div class='ctx'> 			 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |</div><div class='ctx'> 			 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |</div><div class='ctx'> 				 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;</div><div class='ctx'> 		else</div><div class='hunk'>@@ -6887,10 +7543,40 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)</div><div class='ctx'> 	return hwrm_req_send(bp, req_rx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+bnxt_hwrm_set_rx_coal(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='add'>+		      struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)</div><div class='add'>+{</div><div class='add'>+	u16 ring_id = bnxt_cp_ring_for_rx(bp, bnapi-&gt;rx_ring);</div><div class='add'>+</div><div class='add'>+	req-&gt;ring_id = cpu_to_le16(ring_id);</div><div class='add'>+	return hwrm_req_send(bp, req);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+bnxt_hwrm_set_tx_coal(struct bnxt *bp, struct bnxt_napi *bnapi,</div><div class='add'>+		      struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_tx_ring_info *txr;</div><div class='add'>+	int i, rc;</div><div class='add'>+</div><div class='add'>+	bnxt_for_each_napi_tx(i, bnapi, txr) {</div><div class='add'>+		u16 ring_id;</div><div class='add'>+</div><div class='add'>+		ring_id = bnxt_cp_ring_for_tx(bp, txr);</div><div class='add'>+		req-&gt;ring_id = cpu_to_le16(ring_id);</div><div class='add'>+		rc = hwrm_req_send(bp, req);</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int bnxt_hwrm_set_coal(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx,</div><div class='del'>-							   *req;</div><div class='add'>+	struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx;</div><div class='ctx'> 	int i, rc;</div><div class='ctx'> </div><div class='ctx'> 	rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);</div><div class='hunk'>@@ -6911,29 +7597,19 @@ int bnxt_hwrm_set_coal(struct bnxt *bp)</div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='ctx'> 		struct bnxt_napi *bnapi = bp-&gt;bnapi[i];</div><div class='ctx'> 		struct bnxt_coal *hw_coal;</div><div class='del'>-		u16 ring_id;</div><div class='ctx'> </div><div class='del'>-		req = req_rx;</div><div class='del'>-		if (!bnapi-&gt;rx_ring) {</div><div class='del'>-			ring_id = bnxt_cp_ring_for_tx(bp, bnapi-&gt;tx_ring);</div><div class='del'>-			req = req_tx;</div><div class='del'>-		} else {</div><div class='del'>-			ring_id = bnxt_cp_ring_for_rx(bp, bnapi-&gt;rx_ring);</div><div class='del'>-		}</div><div class='del'>-		req-&gt;ring_id = cpu_to_le16(ring_id);</div><div class='del'>-</div><div class='del'>-		rc = hwrm_req_send(bp, req);</div><div class='add'>+		if (!bnapi-&gt;rx_ring)</div><div class='add'>+			rc = bnxt_hwrm_set_tx_coal(bp, bnapi, req_tx);</div><div class='add'>+		else</div><div class='add'>+			rc = bnxt_hwrm_set_rx_coal(bp, bnapi, req_rx);</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		if (bnapi-&gt;rx_ring &amp;&amp; bnapi-&gt;tx_ring) {</div><div class='del'>-			req = req_tx;</div><div class='del'>-			ring_id = bnxt_cp_ring_for_tx(bp, bnapi-&gt;tx_ring);</div><div class='del'>-			req-&gt;ring_id = cpu_to_le16(ring_id);</div><div class='del'>-			rc = hwrm_req_send(bp, req);</div><div class='add'>+		if (bnapi-&gt;rx_ring &amp;&amp; bnapi-&gt;tx_ring[0]) {</div><div class='add'>+			rc = bnxt_hwrm_set_tx_coal(bp, bnapi, req_tx);</div><div class='ctx'> 			if (rc)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -7029,7 +7705,6 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwrm_func_qcfg_output *resp;</div><div class='ctx'> 	struct hwrm_func_qcfg_input *req;</div><div class='del'>-	u32 min_db_offset = 0;</div><div class='ctx'> 	u16 flags;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='hunk'>@@ -7087,16 +7762,17 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)</div><div class='ctx'> 	if (bp-&gt;db_size)</div><div class='ctx'> 		goto func_qcfg_exit;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	bp-&gt;db_offset = le16_to_cpu(resp-&gt;legacy_l2_db_size_kb) * 1024;</div><div class='add'>+	if (BNXT_CHIP_P5(bp)) {</div><div class='ctx'> 		if (BNXT_PF(bp))</div><div class='del'>-			min_db_offset = DB_PF_OFFSET_P5;</div><div class='add'>+			bp-&gt;db_offset = DB_PF_OFFSET_P5;</div><div class='ctx'> 		else</div><div class='del'>-			min_db_offset = DB_VF_OFFSET_P5;</div><div class='add'>+			bp-&gt;db_offset = DB_VF_OFFSET_P5;</div><div class='ctx'> 	}</div><div class='ctx'> 	bp-&gt;db_size = PAGE_ALIGN(le16_to_cpu(resp-&gt;l2_doorbell_bar_size_kb) *</div><div class='ctx'> 				 1024);</div><div class='ctx'> 	if (!bp-&gt;db_size || bp-&gt;db_size &gt; pci_resource_len(bp-&gt;pdev, 2) ||</div><div class='del'>-	    bp-&gt;db_size &lt;= min_db_offset)</div><div class='add'>+	    bp-&gt;db_size &lt;= bp-&gt;db_offset)</div><div class='ctx'> 		bp-&gt;db_size = pci_resource_len(bp-&gt;pdev, 2);</div><div class='ctx'> </div><div class='ctx'> func_qcfg_exit:</div><div class='hunk'>@@ -7104,37 +7780,99 @@ func_qcfg_exit:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,</div><div class='del'>-			struct hwrm_func_backing_store_qcaps_output *resp)</div><div class='add'>+static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_type *ctxm,</div><div class='add'>+				      u8 init_val, u8 init_offset,</div><div class='add'>+				      bool init_mask_set)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_mem_init *mem_init;</div><div class='del'>-	u16 init_mask;</div><div class='del'>-	u8 init_val;</div><div class='del'>-	u8 *offset;</div><div class='del'>-	int i;</div><div class='add'>+	ctxm-&gt;init_value = init_val;</div><div class='add'>+	ctxm-&gt;init_offset = BNXT_CTX_INIT_INVALID_OFFSET;</div><div class='add'>+	if (init_mask_set)</div><div class='add'>+		ctxm-&gt;init_offset = init_offset * 4;</div><div class='add'>+	else</div><div class='add'>+		ctxm-&gt;init_value = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_alloc_all_ctx_pg_info(struct bnxt *bp, int ctx_max)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_ctx_mem_info *ctx = bp-&gt;ctx;</div><div class='add'>+	u16 type;</div><div class='add'>+</div><div class='add'>+	for (type = 0; type &lt; ctx_max; type++) {</div><div class='add'>+		struct bnxt_ctx_mem_type *ctxm = &amp;ctx-&gt;ctx_arr[type];</div><div class='add'>+		int n = 1;</div><div class='ctx'> </div><div class='del'>-	init_val = resp-&gt;ctx_kind_initializer;</div><div class='del'>-	init_mask = le16_to_cpu(resp-&gt;ctx_init_mask);</div><div class='del'>-	offset = &amp;resp-&gt;qp_init_offset;</div><div class='del'>-	mem_init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_QP];</div><div class='del'>-	for (i = 0; i &lt; BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {</div><div class='del'>-		mem_init-&gt;init_val = init_val;</div><div class='del'>-		mem_init-&gt;offset = BNXT_MEM_INVALID_OFFSET;</div><div class='del'>-		if (!init_mask)</div><div class='add'>+		if (!ctxm-&gt;max_entries)</div><div class='ctx'> 			continue;</div><div class='del'>-		if (i == BNXT_CTX_MEM_INIT_STAT)</div><div class='del'>-			offset = &amp;resp-&gt;stat_init_offset;</div><div class='del'>-		if (init_mask &amp; (1 &lt;&lt; i))</div><div class='del'>-			mem_init-&gt;offset = *offset * 4;</div><div class='del'>-		else</div><div class='del'>-			mem_init-&gt;init_val = 0;</div><div class='add'>+</div><div class='add'>+		if (ctxm-&gt;instance_bmap)</div><div class='add'>+			n = hweight32(ctxm-&gt;instance_bmap);</div><div class='add'>+		ctxm-&gt;pg_info = kcalloc(n, sizeof(*ctxm-&gt;pg_info), GFP_KERNEL);</div><div class='add'>+		if (!ctxm-&gt;pg_info)</div><div class='add'>+			return -ENOMEM;</div><div class='ctx'> 	}</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx-&gt;qp_entry_size;</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx-&gt;srq_entry_size;</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx-&gt;cq_entry_size;</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx-&gt;vnic_entry_size;</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx-&gt;stat_entry_size;</div><div class='del'>-	ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx-&gt;mrav_entry_size;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define BNXT_CTX_INIT_VALID(flags)	\</div><div class='add'>+	(!!((flags) &amp;			\</div><div class='add'>+	    FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT))</div><div class='add'>+</div><div class='add'>+static int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp)</div><div class='add'>+{</div><div class='add'>+	struct hwrm_func_backing_store_qcaps_v2_output *resp;</div><div class='add'>+	struct hwrm_func_backing_store_qcaps_v2_input *req;</div><div class='add'>+	struct bnxt_ctx_mem_info *ctx;</div><div class='add'>+	u16 type;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS_V2);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);</div><div class='add'>+	if (!ctx)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	bp-&gt;ctx = ctx;</div><div class='add'>+</div><div class='add'>+	resp = hwrm_req_hold(bp, req);</div><div class='add'>+</div><div class='add'>+	for (type = 0; type &lt; BNXT_CTX_V2_MAX; ) {</div><div class='add'>+		struct bnxt_ctx_mem_type *ctxm = &amp;ctx-&gt;ctx_arr[type];</div><div class='add'>+		u8 init_val, init_off, i;</div><div class='add'>+		__le32 *p;</div><div class='add'>+		u32 flags;</div><div class='add'>+</div><div class='add'>+		req-&gt;type = cpu_to_le16(type);</div><div class='add'>+		rc = hwrm_req_send(bp, req);</div><div class='add'>+		if (rc)</div><div class='add'>+			goto ctx_done;</div><div class='add'>+		flags = le32_to_cpu(resp-&gt;flags);</div><div class='add'>+		type = le16_to_cpu(resp-&gt;next_valid_type);</div><div class='add'>+		if (!(flags &amp; FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		ctxm-&gt;type = le16_to_cpu(resp-&gt;type);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;entry_size);</div><div class='add'>+		ctxm-&gt;flags = flags;</div><div class='add'>+		ctxm-&gt;instance_bmap = le32_to_cpu(resp-&gt;instance_bit_map);</div><div class='add'>+		ctxm-&gt;entry_multiple = resp-&gt;entry_multiple;</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;max_num_entries);</div><div class='add'>+		ctxm-&gt;min_entries = le32_to_cpu(resp-&gt;min_num_entries);</div><div class='add'>+		init_val = resp-&gt;ctx_init_value;</div><div class='add'>+		init_off = resp-&gt;ctx_init_offset;</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val, init_off,</div><div class='add'>+					  BNXT_CTX_INIT_VALID(flags));</div><div class='add'>+		ctxm-&gt;split_entry_cnt = min_t(u8, resp-&gt;subtype_valid_cnt,</div><div class='add'>+					      BNXT_MAX_SPLIT_ENTRY);</div><div class='add'>+		for (i = 0, p = &amp;resp-&gt;split_entry_0; i &lt; ctxm-&gt;split_entry_cnt;</div><div class='add'>+		     i++, p++)</div><div class='add'>+			ctxm-&gt;split[i] = le32_to_cpu(*p);</div><div class='add'>+	}</div><div class='add'>+	rc = bnxt_alloc_all_ctx_pg_info(bp, BNXT_CTX_V2_MAX);</div><div class='add'>+</div><div class='add'>+ctx_done:</div><div class='add'>+	hwrm_req_drop(bp, req);</div><div class='add'>+	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)</div><div class='hunk'>@@ -7146,6 +7884,9 @@ static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)</div><div class='ctx'> 	if (bp-&gt;hwrm_spec_code &lt; 0x10902 || BNXT_VF(bp) || bp-&gt;ctx)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_BACKING_STORE_V2)</div><div class='add'>+		return bnxt_hwrm_func_backing_store_qcaps_v2(bp);</div><div class='add'>+</div><div class='ctx'> 	rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='hunk'>@@ -7153,48 +7894,84 @@ static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)</div><div class='ctx'> 	resp = hwrm_req_hold(bp, req);</div><div class='ctx'> 	rc = hwrm_req_send_silent(bp, req);</div><div class='ctx'> 	if (!rc) {</div><div class='del'>-		struct bnxt_ctx_pg_info *ctx_pg;</div><div class='add'>+		struct bnxt_ctx_mem_type *ctxm;</div><div class='ctx'> 		struct bnxt_ctx_mem_info *ctx;</div><div class='del'>-		int i, tqm_rings;</div><div class='add'>+		u8 init_val, init_idx = 0;</div><div class='add'>+		u16 init_mask;</div><div class='ctx'> </div><div class='del'>-		ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);</div><div class='add'>+		ctx = bp-&gt;ctx;</div><div class='ctx'> 		if (!ctx) {</div><div class='del'>-			rc = -ENOMEM;</div><div class='del'>-			goto ctx_err;</div><div class='del'>-		}</div><div class='del'>-		ctx-&gt;qp_max_entries = le32_to_cpu(resp-&gt;qp_max_entries);</div><div class='del'>-		ctx-&gt;qp_min_qp1_entries = le16_to_cpu(resp-&gt;qp_min_qp1_entries);</div><div class='del'>-		ctx-&gt;qp_max_l2_entries = le16_to_cpu(resp-&gt;qp_max_l2_entries);</div><div class='del'>-		ctx-&gt;qp_entry_size = le16_to_cpu(resp-&gt;qp_entry_size);</div><div class='del'>-		ctx-&gt;srq_max_l2_entries = le16_to_cpu(resp-&gt;srq_max_l2_entries);</div><div class='del'>-		ctx-&gt;srq_max_entries = le32_to_cpu(resp-&gt;srq_max_entries);</div><div class='del'>-		ctx-&gt;srq_entry_size = le16_to_cpu(resp-&gt;srq_entry_size);</div><div class='del'>-		ctx-&gt;cq_max_l2_entries = le16_to_cpu(resp-&gt;cq_max_l2_entries);</div><div class='del'>-		ctx-&gt;cq_max_entries = le32_to_cpu(resp-&gt;cq_max_entries);</div><div class='del'>-		ctx-&gt;cq_entry_size = le16_to_cpu(resp-&gt;cq_entry_size);</div><div class='del'>-		ctx-&gt;vnic_max_vnic_entries =</div><div class='del'>-			le16_to_cpu(resp-&gt;vnic_max_vnic_entries);</div><div class='del'>-		ctx-&gt;vnic_max_ring_table_entries =</div><div class='add'>+			ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);</div><div class='add'>+			if (!ctx) {</div><div class='add'>+				rc = -ENOMEM;</div><div class='add'>+				goto ctx_err;</div><div class='add'>+			}</div><div class='add'>+			bp-&gt;ctx = ctx;</div><div class='add'>+		}</div><div class='add'>+		init_val = resp-&gt;ctx_kind_initializer;</div><div class='add'>+		init_mask = le16_to_cpu(resp-&gt;ctx_init_mask);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_QP];</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;qp_max_entries);</div><div class='add'>+		ctxm-&gt;qp_qp1_entries = le16_to_cpu(resp-&gt;qp_min_qp1_entries);</div><div class='add'>+		ctxm-&gt;qp_l2_entries = le16_to_cpu(resp-&gt;qp_max_l2_entries);</div><div class='add'>+		ctxm-&gt;qp_fast_qpmd_entries = le16_to_cpu(resp-&gt;fast_qpmd_qp_num_entries);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;qp_entry_size);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val, resp-&gt;qp_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_SRQ];</div><div class='add'>+		ctxm-&gt;srq_l2_entries = le16_to_cpu(resp-&gt;srq_max_l2_entries);</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;srq_max_entries);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;srq_entry_size);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val, resp-&gt;srq_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_CQ];</div><div class='add'>+		ctxm-&gt;cq_l2_entries = le16_to_cpu(resp-&gt;cq_max_l2_entries);</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;cq_max_entries);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;cq_entry_size);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val, resp-&gt;cq_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_VNIC];</div><div class='add'>+		ctxm-&gt;vnic_entries = le16_to_cpu(resp-&gt;vnic_max_vnic_entries);</div><div class='add'>+		ctxm-&gt;max_entries = ctxm-&gt;vnic_entries +</div><div class='ctx'> 			le16_to_cpu(resp-&gt;vnic_max_ring_table_entries);</div><div class='del'>-		ctx-&gt;vnic_entry_size = le16_to_cpu(resp-&gt;vnic_entry_size);</div><div class='del'>-		ctx-&gt;stat_max_entries = le32_to_cpu(resp-&gt;stat_max_entries);</div><div class='del'>-		ctx-&gt;stat_entry_size = le16_to_cpu(resp-&gt;stat_entry_size);</div><div class='del'>-		ctx-&gt;tqm_entry_size = le16_to_cpu(resp-&gt;tqm_entry_size);</div><div class='del'>-		ctx-&gt;tqm_min_entries_per_ring =</div><div class='del'>-			le32_to_cpu(resp-&gt;tqm_min_entries_per_ring);</div><div class='del'>-		ctx-&gt;tqm_max_entries_per_ring =</div><div class='del'>-			le32_to_cpu(resp-&gt;tqm_max_entries_per_ring);</div><div class='del'>-		ctx-&gt;tqm_entries_multiple = resp-&gt;tqm_entries_multiple;</div><div class='del'>-		if (!ctx-&gt;tqm_entries_multiple)</div><div class='del'>-			ctx-&gt;tqm_entries_multiple = 1;</div><div class='del'>-		ctx-&gt;mrav_max_entries = le32_to_cpu(resp-&gt;mrav_max_entries);</div><div class='del'>-		ctx-&gt;mrav_entry_size = le16_to_cpu(resp-&gt;mrav_entry_size);</div><div class='del'>-		ctx-&gt;mrav_num_entries_units =</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;vnic_entry_size);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val,</div><div class='add'>+					  resp-&gt;vnic_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STAT];</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;stat_max_entries);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;stat_entry_size);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val,</div><div class='add'>+					  resp-&gt;stat_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STQM];</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;tqm_entry_size);</div><div class='add'>+		ctxm-&gt;min_entries = le32_to_cpu(resp-&gt;tqm_min_entries_per_ring);</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;tqm_max_entries_per_ring);</div><div class='add'>+		ctxm-&gt;entry_multiple = resp-&gt;tqm_entries_multiple;</div><div class='add'>+		if (!ctxm-&gt;entry_multiple)</div><div class='add'>+			ctxm-&gt;entry_multiple = 1;</div><div class='add'>+</div><div class='add'>+		memcpy(&amp;ctx-&gt;ctx_arr[BNXT_CTX_FTQM], ctxm, sizeof(*ctxm));</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_MRAV];</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;mrav_max_entries);</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;mrav_entry_size);</div><div class='add'>+		ctxm-&gt;mrav_num_entries_units =</div><div class='ctx'> 			le16_to_cpu(resp-&gt;mrav_num_entries_units);</div><div class='del'>-		ctx-&gt;tim_entry_size = le16_to_cpu(resp-&gt;tim_entry_size);</div><div class='del'>-		ctx-&gt;tim_max_entries = le32_to_cpu(resp-&gt;tim_max_entries);</div><div class='add'>+		bnxt_init_ctx_initializer(ctxm, init_val,</div><div class='add'>+					  resp-&gt;mrav_init_offset,</div><div class='add'>+					  (init_mask &amp; (1 &lt;&lt; init_idx++)) != 0);</div><div class='ctx'> </div><div class='del'>-		bnxt_init_ctx_initializer(ctx, resp);</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_TIM];</div><div class='add'>+		ctxm-&gt;entry_size = le16_to_cpu(resp-&gt;tim_entry_size);</div><div class='add'>+		ctxm-&gt;max_entries = le32_to_cpu(resp-&gt;tim_max_entries);</div><div class='ctx'> </div><div class='ctx'> 		ctx-&gt;tqm_fp_rings_count = resp-&gt;tqm_fp_rings_count;</div><div class='ctx'> 		if (!ctx-&gt;tqm_fp_rings_count)</div><div class='hunk'>@@ -7202,16 +7979,11 @@ static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)</div><div class='ctx'> 		else if (ctx-&gt;tqm_fp_rings_count &gt; BNXT_MAX_TQM_FP_RINGS)</div><div class='ctx'> 			ctx-&gt;tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;</div><div class='ctx'> </div><div class='del'>-		tqm_rings = ctx-&gt;tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;</div><div class='del'>-		ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);</div><div class='del'>-		if (!ctx_pg) {</div><div class='del'>-			kfree(ctx);</div><div class='del'>-			rc = -ENOMEM;</div><div class='del'>-			goto ctx_err;</div><div class='del'>-		}</div><div class='del'>-		for (i = 0; i &lt; tqm_rings; i++, ctx_pg++)</div><div class='del'>-			ctx-&gt;tqm_mem[i] = ctx_pg;</div><div class='del'>-		bp-&gt;ctx = ctx;</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_FTQM];</div><div class='add'>+		memcpy(ctxm, &amp;ctx-&gt;ctx_arr[BNXT_CTX_STQM], sizeof(*ctxm));</div><div class='add'>+		ctxm-&gt;instance_bmap = (1 &lt;&lt; ctx-&gt;tqm_fp_rings_count) - 1;</div><div class='add'>+</div><div class='add'>+		rc = bnxt_alloc_all_ctx_pg_info(bp, BNXT_CTX_MAX);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		rc = 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7250,6 +8022,7 @@ static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)</div><div class='ctx'> 	struct hwrm_func_backing_store_cfg_input *req;</div><div class='ctx'> 	struct bnxt_ctx_mem_info *ctx = bp-&gt;ctx;</div><div class='ctx'> 	struct bnxt_ctx_pg_info *ctx_pg;</div><div class='add'>+	struct bnxt_ctx_mem_type *ctxm;</div><div class='ctx'> 	void **__req = (void **)&amp;req;</div><div class='ctx'> 	u32 req_len = sizeof(*req);</div><div class='ctx'> 	__le32 *num_entries;</div><div class='hunk'>@@ -7271,82 +8044,102 @@ static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)</div><div class='ctx'> </div><div class='ctx'> 	req-&gt;enables = cpu_to_le32(enables);</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;qp_mem;</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_QP];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 		req-&gt;qp_num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='del'>-		req-&gt;qp_num_qp1_entries = cpu_to_le16(ctx-&gt;qp_min_qp1_entries);</div><div class='del'>-		req-&gt;qp_num_l2_entries = cpu_to_le16(ctx-&gt;qp_max_l2_entries);</div><div class='del'>-		req-&gt;qp_entry_size = cpu_to_le16(ctx-&gt;qp_entry_size);</div><div class='add'>+		req-&gt;qp_num_qp1_entries = cpu_to_le16(ctxm-&gt;qp_qp1_entries);</div><div class='add'>+		req-&gt;qp_num_l2_entries = cpu_to_le16(ctxm-&gt;qp_l2_entries);</div><div class='add'>+		req-&gt;qp_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;qpc_pg_size_qpc_lvl,</div><div class='ctx'> 				      &amp;req-&gt;qpc_page_dir);</div><div class='add'>+</div><div class='add'>+		if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD)</div><div class='add'>+			req-&gt;qp_num_fast_qpmd_entries = cpu_to_le16(ctxm-&gt;qp_fast_qpmd_entries);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;srq_mem;</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_SRQ];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 		req-&gt;srq_num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='del'>-		req-&gt;srq_num_l2_entries = cpu_to_le16(ctx-&gt;srq_max_l2_entries);</div><div class='del'>-		req-&gt;srq_entry_size = cpu_to_le16(ctx-&gt;srq_entry_size);</div><div class='add'>+		req-&gt;srq_num_l2_entries = cpu_to_le16(ctxm-&gt;srq_l2_entries);</div><div class='add'>+		req-&gt;srq_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;srq_pg_size_srq_lvl,</div><div class='ctx'> 				      &amp;req-&gt;srq_page_dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;cq_mem;</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_CQ];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 		req-&gt;cq_num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='del'>-		req-&gt;cq_num_l2_entries = cpu_to_le16(ctx-&gt;cq_max_l2_entries);</div><div class='del'>-		req-&gt;cq_entry_size = cpu_to_le16(ctx-&gt;cq_entry_size);</div><div class='add'>+		req-&gt;cq_num_l2_entries = cpu_to_le16(ctxm-&gt;cq_l2_entries);</div><div class='add'>+		req-&gt;cq_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;cq_pg_size_cq_lvl,</div><div class='ctx'> 				      &amp;req-&gt;cq_page_dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;vnic_mem;</div><div class='del'>-		req-&gt;vnic_num_vnic_entries =</div><div class='del'>-			cpu_to_le16(ctx-&gt;vnic_max_vnic_entries);</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_VNIC];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='add'>+		req-&gt;vnic_num_vnic_entries = cpu_to_le16(ctxm-&gt;vnic_entries);</div><div class='ctx'> 		req-&gt;vnic_num_ring_table_entries =</div><div class='del'>-			cpu_to_le16(ctx-&gt;vnic_max_ring_table_entries);</div><div class='del'>-		req-&gt;vnic_entry_size = cpu_to_le16(ctx-&gt;vnic_entry_size);</div><div class='add'>+			cpu_to_le16(ctxm-&gt;max_entries - ctxm-&gt;vnic_entries);</div><div class='add'>+		req-&gt;vnic_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;vnic_pg_size_vnic_lvl,</div><div class='ctx'> 				      &amp;req-&gt;vnic_page_dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;stat_mem;</div><div class='del'>-		req-&gt;stat_num_entries = cpu_to_le32(ctx-&gt;stat_max_entries);</div><div class='del'>-		req-&gt;stat_entry_size = cpu_to_le16(ctx-&gt;stat_entry_size);</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STAT];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='add'>+		req-&gt;stat_num_entries = cpu_to_le32(ctxm-&gt;max_entries);</div><div class='add'>+		req-&gt;stat_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;stat_pg_size_stat_lvl,</div><div class='ctx'> 				      &amp;req-&gt;stat_page_dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;mrav_mem;</div><div class='add'>+		u32 units;</div><div class='add'>+</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_MRAV];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 		req-&gt;mrav_num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='del'>-		if (ctx-&gt;mrav_num_entries_units)</div><div class='del'>-			flags |=</div><div class='del'>-			FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;</div><div class='del'>-		req-&gt;mrav_entry_size = cpu_to_le16(ctx-&gt;mrav_entry_size);</div><div class='add'>+		units = ctxm-&gt;mrav_num_entries_units;</div><div class='add'>+		if (units) {</div><div class='add'>+			u32 num_mr, num_ah = ctxm-&gt;mrav_av_entries;</div><div class='add'>+			u32 entries;</div><div class='add'>+</div><div class='add'>+			num_mr = ctx_pg-&gt;entries - num_ah;</div><div class='add'>+			entries = ((num_mr / units) &lt;&lt; 16) | (num_ah / units);</div><div class='add'>+			req-&gt;mrav_num_entries = cpu_to_le32(entries);</div><div class='add'>+			flags |= FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;</div><div class='add'>+		}</div><div class='add'>+		req-&gt;mrav_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;mrav_pg_size_mrav_lvl,</div><div class='ctx'> 				      &amp;req-&gt;mrav_page_dir);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (enables &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {</div><div class='del'>-		ctx_pg = &amp;ctx-&gt;tim_mem;</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_TIM];</div><div class='add'>+		ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 		req-&gt;tim_num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='del'>-		req-&gt;tim_entry_size = cpu_to_le16(ctx-&gt;tim_entry_size);</div><div class='add'>+		req-&gt;tim_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='ctx'> 				      &amp;req-&gt;tim_pg_size_tim_lvl,</div><div class='ctx'> 				      &amp;req-&gt;tim_page_dir);</div><div class='ctx'> 	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STQM];</div><div class='ctx'> 	for (i = 0, num_entries = &amp;req-&gt;tqm_sp_num_entries,</div><div class='ctx'> 	     pg_attr = &amp;req-&gt;tqm_sp_pg_size_tqm_sp_lvl,</div><div class='ctx'> 	     pg_dir = &amp;req-&gt;tqm_sp_page_dir,</div><div class='del'>-	     ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;</div><div class='add'>+	     ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP,</div><div class='add'>+	     ctx_pg = ctxm-&gt;pg_info;</div><div class='ctx'> 	     i &lt; BNXT_MAX_TQM_RINGS;</div><div class='add'>+	     ctx_pg = &amp;ctx-&gt;ctx_arr[BNXT_CTX_FTQM].pg_info[i],</div><div class='ctx'> 	     i++, num_entries++, pg_attr++, pg_dir++, ena &lt;&lt;= 1) {</div><div class='ctx'> 		if (!(enables &amp; ena))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		req-&gt;tqm_entry_size = cpu_to_le16(ctx-&gt;tqm_entry_size);</div><div class='del'>-		ctx_pg = ctx-&gt;tqm_mem[i];</div><div class='add'>+		req-&gt;tqm_entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='ctx'> 		*num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='ctx'> 		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem, pg_attr, pg_dir);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7370,7 +8163,7 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,</div><div class='ctx'> 				  struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,</div><div class='del'>-				  u8 depth, struct bnxt_mem_init *mem_init)</div><div class='add'>+				  u8 depth, struct bnxt_ctx_mem_type *ctxm)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_ring_mem_info *rmem = &amp;ctx_pg-&gt;ring_mem;</div><div class='ctx'> 	int rc;</div><div class='hunk'>@@ -7408,7 +8201,7 @@ static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,</div><div class='ctx'> 			rmem-&gt;pg_tbl_map = ctx_pg-&gt;ctx_dma_arr[i];</div><div class='ctx'> 			rmem-&gt;depth = 1;</div><div class='ctx'> 			rmem-&gt;nr_pages = MAX_CTX_PAGES;</div><div class='del'>-			rmem-&gt;mem_init = mem_init;</div><div class='add'>+			rmem-&gt;ctx_mem = ctxm;</div><div class='ctx'> 			if (i == (nr_tbls - 1)) {</div><div class='ctx'> 				int rem = ctx_pg-&gt;nr_pages % MAX_CTX_PAGES;</div><div class='ctx'> </div><div class='hunk'>@@ -7423,7 +8216,7 @@ static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,</div><div class='ctx'> 		rmem-&gt;nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);</div><div class='ctx'> 		if (rmem-&gt;nr_pages &gt; 1 || depth)</div><div class='ctx'> 			rmem-&gt;depth = 1;</div><div class='del'>-		rmem-&gt;mem_init = mem_init;</div><div class='add'>+		rmem-&gt;ctx_mem = ctxm;</div><div class='ctx'> 		rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);</div><div class='ctx'> 	}</div><div class='ctx'> 	return rc;</div><div class='hunk'>@@ -7458,41 +8251,144 @@ static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,</div><div class='ctx'> 	ctx_pg-&gt;nr_pages = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int bnxt_setup_ctxm_pg_tbls(struct bnxt *bp,</div><div class='add'>+				   struct bnxt_ctx_mem_type *ctxm, u32 entries,</div><div class='add'>+				   u8 pg_lvl)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_ctx_pg_info *ctx_pg = ctxm-&gt;pg_info;</div><div class='add'>+	int i, rc = 0, n = 1;</div><div class='add'>+	u32 mem_size;</div><div class='add'>+</div><div class='add'>+	if (!ctxm-&gt;entry_size || !ctx_pg)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	if (ctxm-&gt;instance_bmap)</div><div class='add'>+		n = hweight32(ctxm-&gt;instance_bmap);</div><div class='add'>+	if (ctxm-&gt;entry_multiple)</div><div class='add'>+		entries = roundup(entries, ctxm-&gt;entry_multiple);</div><div class='add'>+	entries = clamp_t(u32, entries, ctxm-&gt;min_entries, ctxm-&gt;max_entries);</div><div class='add'>+	mem_size = entries * ctxm-&gt;entry_size;</div><div class='add'>+	for (i = 0; i &lt; n &amp;&amp; !rc; i++) {</div><div class='add'>+		ctx_pg[i].entries = entries;</div><div class='add'>+		rc = bnxt_alloc_ctx_pg_tbls(bp, &amp;ctx_pg[i], mem_size, pg_lvl,</div><div class='add'>+					    ctxm-&gt;init_value ? ctxm : NULL);</div><div class='add'>+	}</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp,</div><div class='add'>+					       struct bnxt_ctx_mem_type *ctxm,</div><div class='add'>+					       bool last)</div><div class='add'>+{</div><div class='add'>+	struct hwrm_func_backing_store_cfg_v2_input *req;</div><div class='add'>+	u32 instance_bmap = ctxm-&gt;instance_bmap;</div><div class='add'>+	int i, j, rc = 0, n = 1;</div><div class='add'>+	__le32 *p;</div><div class='add'>+</div><div class='add'>+	if (!(ctxm-&gt;flags &amp; BNXT_CTX_MEM_TYPE_VALID) || !ctxm-&gt;pg_info)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (instance_bmap)</div><div class='add'>+		n = hweight32(ctxm-&gt;instance_bmap);</div><div class='add'>+	else</div><div class='add'>+		instance_bmap = 1;</div><div class='add'>+</div><div class='add'>+	rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_CFG_V2);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+	hwrm_req_hold(bp, req);</div><div class='add'>+	req-&gt;type = cpu_to_le16(ctxm-&gt;type);</div><div class='add'>+	req-&gt;entry_size = cpu_to_le16(ctxm-&gt;entry_size);</div><div class='add'>+	req-&gt;subtype_valid_cnt = ctxm-&gt;split_entry_cnt;</div><div class='add'>+	for (i = 0, p = &amp;req-&gt;split_entry_0; i &lt; ctxm-&gt;split_entry_cnt; i++)</div><div class='add'>+		p[i] = cpu_to_le32(ctxm-&gt;split[i]);</div><div class='add'>+	for (i = 0, j = 0; j &lt; n &amp;&amp; !rc; i++) {</div><div class='add'>+		struct bnxt_ctx_pg_info *ctx_pg;</div><div class='add'>+</div><div class='add'>+		if (!(instance_bmap &amp; (1 &lt;&lt; i)))</div><div class='add'>+			continue;</div><div class='add'>+		req-&gt;instance = cpu_to_le16(i);</div><div class='add'>+		ctx_pg = &amp;ctxm-&gt;pg_info[j++];</div><div class='add'>+		if (!ctx_pg-&gt;entries)</div><div class='add'>+			continue;</div><div class='add'>+		req-&gt;num_entries = cpu_to_le32(ctx_pg-&gt;entries);</div><div class='add'>+		bnxt_hwrm_set_pg_attr(&amp;ctx_pg-&gt;ring_mem,</div><div class='add'>+				      &amp;req-&gt;page_size_pbl_level,</div><div class='add'>+				      &amp;req-&gt;page_dir);</div><div class='add'>+		if (last &amp;&amp; j == n)</div><div class='add'>+			req-&gt;flags =</div><div class='add'>+				cpu_to_le32(FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE);</div><div class='add'>+		rc = hwrm_req_send(bp, req);</div><div class='add'>+	}</div><div class='add'>+	hwrm_req_drop(bp, req);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_backing_store_cfg_v2(struct bnxt *bp, u32 ena)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_ctx_mem_info *ctx = bp-&gt;ctx;</div><div class='add'>+	struct bnxt_ctx_mem_type *ctxm;</div><div class='add'>+	u16 last_type;</div><div class='add'>+	int rc = 0;</div><div class='add'>+	u16 type;</div><div class='add'>+</div><div class='add'>+	if (!ena)</div><div class='add'>+		return 0;</div><div class='add'>+	else if (ena &amp; FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM)</div><div class='add'>+		last_type = BNXT_CTX_MAX - 1;</div><div class='add'>+	else</div><div class='add'>+		last_type = BNXT_CTX_L2_MAX - 1;</div><div class='add'>+	ctx-&gt;ctx_arr[last_type].last = 1;</div><div class='add'>+</div><div class='add'>+	for (type = 0 ; type &lt; BNXT_CTX_V2_MAX; type++) {</div><div class='add'>+		ctxm = &amp;ctx-&gt;ctx_arr[type];</div><div class='add'>+</div><div class='add'>+		rc = bnxt_hwrm_func_backing_store_cfg_v2(bp, ctxm, ctxm-&gt;last);</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void bnxt_free_ctx_mem(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_ctx_mem_info *ctx = bp-&gt;ctx;</div><div class='del'>-	int i;</div><div class='add'>+	u16 type;</div><div class='ctx'> </div><div class='ctx'> 	if (!ctx)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (ctx-&gt;tqm_mem[0]) {</div><div class='del'>-		for (i = 0; i &lt; ctx-&gt;tqm_fp_rings_count + 1; i++)</div><div class='del'>-			bnxt_free_ctx_pg_tbls(bp, ctx-&gt;tqm_mem[i]);</div><div class='del'>-		kfree(ctx-&gt;tqm_mem[0]);</div><div class='del'>-		ctx-&gt;tqm_mem[0] = NULL;</div><div class='add'>+	for (type = 0; type &lt; BNXT_CTX_V2_MAX; type++) {</div><div class='add'>+		struct bnxt_ctx_mem_type *ctxm = &amp;ctx-&gt;ctx_arr[type];</div><div class='add'>+		struct bnxt_ctx_pg_info *ctx_pg = ctxm-&gt;pg_info;</div><div class='add'>+		int i, n = 1;</div><div class='add'>+</div><div class='add'>+		if (!ctx_pg)</div><div class='add'>+			continue;</div><div class='add'>+		if (ctxm-&gt;instance_bmap)</div><div class='add'>+			n = hweight32(ctxm-&gt;instance_bmap);</div><div class='add'>+		for (i = 0; i &lt; n; i++)</div><div class='add'>+			bnxt_free_ctx_pg_tbls(bp, &amp;ctx_pg[i]);</div><div class='add'>+</div><div class='add'>+		kfree(ctx_pg);</div><div class='add'>+		ctxm-&gt;pg_info = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;tim_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;mrav_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;stat_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;vnic_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;cq_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;srq_mem);</div><div class='del'>-	bnxt_free_ctx_pg_tbls(bp, &amp;ctx-&gt;qp_mem);</div><div class='ctx'> 	ctx-&gt;flags &amp;= ~BNXT_CTX_FLAG_INITED;</div><div class='add'>+	kfree(ctx);</div><div class='add'>+	bp-&gt;ctx = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_ctx_mem(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_ctx_pg_info *ctx_pg;</div><div class='add'>+	struct bnxt_ctx_mem_type *ctxm;</div><div class='ctx'> 	struct bnxt_ctx_mem_info *ctx;</div><div class='del'>-	struct bnxt_mem_init *init;</div><div class='del'>-	u32 mem_size, ena, entries;</div><div class='del'>-	u32 entries_sp, min;</div><div class='add'>+	u32 l2_qps, qp1_qps, max_qps;</div><div class='add'>+	u32 ena, entries_sp, entries;</div><div class='add'>+	u32 srqs, max_srqs, min;</div><div class='ctx'> 	u32 num_mr, num_ah;</div><div class='ctx'> 	u32 extra_srqs = 0;</div><div class='ctx'> 	u32 extra_qps = 0;</div><div class='add'>+	u32 fast_qpmd_qps;</div><div class='ctx'> 	u8 pg_lvl = 1;</div><div class='ctx'> 	int i, rc;</div><div class='ctx'> </div><div class='hunk'>@@ -7506,120 +8402,98 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)</div><div class='ctx'> 	if (!ctx || (ctx-&gt;flags &amp; BNXT_CTX_FLAG_INITED))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_QP];</div><div class='add'>+	l2_qps = ctxm-&gt;qp_l2_entries;</div><div class='add'>+	qp1_qps = ctxm-&gt;qp_qp1_entries;</div><div class='add'>+	fast_qpmd_qps = ctxm-&gt;qp_fast_qpmd_entries;</div><div class='add'>+	max_qps = ctxm-&gt;max_entries;</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_SRQ];</div><div class='add'>+	srqs = ctxm-&gt;srq_l2_entries;</div><div class='add'>+	max_srqs = ctxm-&gt;max_entries;</div><div class='add'>+	ena = 0;</div><div class='ctx'> 	if ((bp-&gt;flags &amp; BNXT_FLAG_ROCE_CAP) &amp;&amp; !is_kdump_kernel()) {</div><div class='ctx'> 		pg_lvl = 2;</div><div class='del'>-		extra_qps = 65536;</div><div class='del'>-		extra_srqs = 8192;</div><div class='add'>+		extra_qps = min_t(u32, 65536, max_qps - l2_qps - qp1_qps);</div><div class='add'>+		/* allocate extra qps if fw supports RoCE fast qp destroy feature */</div><div class='add'>+		extra_qps += fast_qpmd_qps;</div><div class='add'>+		extra_srqs = min_t(u32, 8192, max_srqs - srqs);</div><div class='add'>+		if (fast_qpmd_qps)</div><div class='add'>+			ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;qp_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;qp_min_qp1_entries + ctx-&gt;qp_max_l2_entries +</div><div class='del'>-			  extra_qps;</div><div class='del'>-	if (ctx-&gt;qp_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;qp_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_QP];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_QP];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, l2_qps + qp1_qps + extra_qps,</div><div class='add'>+				     pg_lvl);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;srq_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;srq_max_l2_entries + extra_srqs;</div><div class='del'>-	if (ctx-&gt;srq_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;srq_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_SRQ];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_SRQ];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, srqs + extra_srqs, pg_lvl);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;cq_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;cq_max_l2_entries + extra_qps * 2;</div><div class='del'>-	if (ctx-&gt;cq_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;cq_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_CQ];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_CQ];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm-&gt;cq_l2_entries +</div><div class='add'>+				     extra_qps * 2, pg_lvl);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;vnic_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;vnic_max_vnic_entries +</div><div class='del'>-			  ctx-&gt;vnic_max_ring_table_entries;</div><div class='del'>-	if (ctx-&gt;vnic_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;vnic_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_VNIC];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_VNIC];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm-&gt;max_entries, 1);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;stat_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;stat_max_entries;</div><div class='del'>-	if (ctx-&gt;stat_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;stat_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_STAT];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STAT];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, ctxm-&gt;max_entries, 1);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> </div><div class='del'>-	ena = 0;</div><div class='ctx'> 	if (!(bp-&gt;flags &amp; BNXT_FLAG_ROCE_CAP))</div><div class='ctx'> 		goto skip_rdma;</div><div class='ctx'> </div><div class='del'>-	ctx_pg = &amp;ctx-&gt;mrav_mem;</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_MRAV];</div><div class='ctx'> 	/* 128K extra is needed to accommodate static AH context</div><div class='ctx'> 	 * allocation by f/w.</div><div class='ctx'> 	 */</div><div class='del'>-	num_mr = 1024 * 256;</div><div class='del'>-	num_ah = 1024 * 128;</div><div class='del'>-	ctx_pg-&gt;entries = num_mr + num_ah;</div><div class='del'>-	if (ctx-&gt;mrav_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;mrav_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		init = &amp;ctx-&gt;mem_init[BNXT_CTX_MEM_INIT_MRAV];</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='del'>-	ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;</div><div class='del'>-	if (ctx-&gt;mrav_num_entries_units)</div><div class='del'>-		ctx_pg-&gt;entries =</div><div class='del'>-			((num_mr / ctx-&gt;mrav_num_entries_units) &lt;&lt; 16) |</div><div class='del'>-			 (num_ah / ctx-&gt;mrav_num_entries_units);</div><div class='del'>-</div><div class='del'>-	ctx_pg = &amp;ctx-&gt;tim_mem;</div><div class='del'>-	ctx_pg-&gt;entries = ctx-&gt;qp_mem.entries;</div><div class='del'>-	if (ctx-&gt;tim_entry_size) {</div><div class='del'>-		mem_size = ctx-&gt;tim_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-		rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);</div><div class='del'>-		if (rc)</div><div class='del'>-			return rc;</div><div class='del'>-	}</div><div class='add'>+	num_mr = min_t(u32, ctxm-&gt;max_entries / 2, 1024 * 256);</div><div class='add'>+	num_ah = min_t(u32, num_mr, 1024 * 128);</div><div class='add'>+	ctxm-&gt;split_entry_cnt = BNXT_CTX_MRAV_AV_SPLIT_ENTRY + 1;</div><div class='add'>+	if (!ctxm-&gt;mrav_av_entries || ctxm-&gt;mrav_av_entries &gt; num_ah)</div><div class='add'>+		ctxm-&gt;mrav_av_entries = num_ah;</div><div class='add'>+</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, num_mr + num_ah, 2);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+	ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;</div><div class='add'>+</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_TIM];</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, l2_qps + qp1_qps + extra_qps, 1);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='ctx'> 	ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;</div><div class='ctx'> </div><div class='ctx'> skip_rdma:</div><div class='del'>-	min = ctx-&gt;tqm_min_entries_per_ring;</div><div class='del'>-	entries_sp = ctx-&gt;vnic_max_vnic_entries + ctx-&gt;qp_max_l2_entries +</div><div class='del'>-		     2 * (extra_qps + ctx-&gt;qp_min_qp1_entries) + min;</div><div class='del'>-	entries_sp = roundup(entries_sp, ctx-&gt;tqm_entries_multiple);</div><div class='del'>-	entries = ctx-&gt;qp_max_l2_entries + 2 * (extra_qps + ctx-&gt;qp_min_qp1_entries);</div><div class='del'>-	entries = roundup(entries, ctx-&gt;tqm_entries_multiple);</div><div class='del'>-	entries = clamp_t(u32, entries, min, ctx-&gt;tqm_max_entries_per_ring);</div><div class='del'>-	for (i = 0; i &lt; ctx-&gt;tqm_fp_rings_count + 1; i++) {</div><div class='del'>-		ctx_pg = ctx-&gt;tqm_mem[i];</div><div class='del'>-		ctx_pg-&gt;entries = i ? entries : entries_sp;</div><div class='del'>-		if (ctx-&gt;tqm_entry_size) {</div><div class='del'>-			mem_size = ctx-&gt;tqm_entry_size * ctx_pg-&gt;entries;</div><div class='del'>-			rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,</div><div class='del'>-						    NULL);</div><div class='del'>-			if (rc)</div><div class='del'>-				return rc;</div><div class='del'>-		}</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_STQM];</div><div class='add'>+	min = ctxm-&gt;min_entries;</div><div class='add'>+	entries_sp = ctx-&gt;ctx_arr[BNXT_CTX_VNIC].vnic_entries + l2_qps +</div><div class='add'>+		     2 * (extra_qps + qp1_qps) + min;</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, entries_sp, 2);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	ctxm = &amp;ctx-&gt;ctx_arr[BNXT_CTX_FTQM];</div><div class='add'>+	entries = l2_qps + 2 * (extra_qps + qp1_qps);</div><div class='add'>+	rc = bnxt_setup_ctxm_pg_tbls(bp, ctxm, entries, 2);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+	for (i = 0; i &lt; ctx-&gt;tqm_fp_rings_count + 1; i++)</div><div class='ctx'> 		ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP &lt;&lt; i;</div><div class='del'>-	}</div><div class='ctx'> 	ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;</div><div class='del'>-	rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);</div><div class='add'>+</div><div class='add'>+	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_BACKING_STORE_V2)</div><div class='add'>+		rc = bnxt_backing_store_cfg_v2(bp, ena);</div><div class='add'>+	else</div><div class='add'>+		rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);</div><div class='ctx'> 	if (rc) {</div><div class='ctx'> 		netdev_err(bp-&gt;dev, "Failed configuring context mem, rc = %d.\n",</div><div class='ctx'> 			   rc);</div><div class='hunk'>@@ -7667,7 +8541,7 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)</div><div class='ctx'> 	hw_resc-&gt;min_stat_ctxs = le16_to_cpu(resp-&gt;min_stat_ctx);</div><div class='ctx'> 	hw_resc-&gt;max_stat_ctxs = le16_to_cpu(resp-&gt;max_stat_ctx);</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		u16 max_msix = le16_to_cpu(resp-&gt;max_msix);</div><div class='ctx'> </div><div class='ctx'> 		hw_resc-&gt;max_nqs = max_msix;</div><div class='hunk'>@@ -7696,7 +8570,7 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)</div><div class='ctx'> 	u8 flags;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;hwrm_spec_code &lt; 0x10801 || !BNXT_CHIP_P5_THOR(bp)) {</div><div class='add'>+	if (bp-&gt;hwrm_spec_code &lt; 0x10801 || !BNXT_CHIP_P5(bp)) {</div><div class='ctx'> 		rc = -ENODEV;</div><div class='ctx'> 		goto no_ptp;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -7728,7 +8602,7 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)</div><div class='ctx'> 	if (flags &amp; PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {</div><div class='ctx'> 		ptp-&gt;refclk_regs[0] = le32_to_cpu(resp-&gt;ts_ref_clock_reg_lower);</div><div class='ctx'> 		ptp-&gt;refclk_regs[1] = le32_to_cpu(resp-&gt;ts_ref_clock_reg_upper);</div><div class='del'>-	} else if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	} else if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		ptp-&gt;refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;</div><div class='ctx'> 		ptp-&gt;refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -7800,10 +8674,16 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)</div><div class='ctx'> 		bp-&gt;fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;</div><div class='ctx'> 	if (BNXT_PF(bp) &amp;&amp; (flags_ext &amp; FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED))</div><div class='ctx'> 		bp-&gt;fw_cap |= BNXT_FW_CAP_LIVEPATCH;</div><div class='add'>+	if (flags_ext &amp; FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED)</div><div class='add'>+		bp-&gt;fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2;</div><div class='add'>+	if (flags_ext &amp; FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP)</div><div class='add'>+		bp-&gt;flags |= BNXT_FLAG_TX_COAL_CMPL;</div><div class='ctx'> </div><div class='ctx'> 	flags_ext2 = le32_to_cpu(resp-&gt;flags_ext2);</div><div class='ctx'> 	if (flags_ext2 &amp; FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)</div><div class='ctx'> 		bp-&gt;fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;</div><div class='add'>+	if (flags_ext2 &amp; FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED)</div><div class='add'>+		bp-&gt;flags |= BNXT_FLAG_UDP_GSO_CAP;</div><div class='ctx'> </div><div class='ctx'> 	bp-&gt;tx_push_thresh = 0;</div><div class='ctx'> 	if ((flags &amp; FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &amp;&amp;</div><div class='hunk'>@@ -8435,7 +9315,7 @@ static void bnxt_accumulate_all_stats(struct bnxt *bp)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* Chip bug.  Counter intermittently becomes 0. */</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		ignore_zero = true;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='hunk'>@@ -8629,7 +9509,7 @@ static void bnxt_clear_vnic(struct bnxt *bp)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	bnxt_hwrm_clear_vnic_filter(bp);</div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)) {</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)) {</div><div class='ctx'> 		/* clear all RSS setting before free vnic ctx */</div><div class='ctx'> 		bnxt_hwrm_clear_vnic_rss(bp);</div><div class='ctx'> 		bnxt_hwrm_vnic_ctx_free(bp);</div><div class='hunk'>@@ -8638,7 +9518,7 @@ static void bnxt_clear_vnic(struct bnxt *bp)</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_TPA)</div><div class='ctx'> 		bnxt_set_tpa(bp, false);</div><div class='ctx'> 	bnxt_hwrm_vnic_free(bp);</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		bnxt_hwrm_vnic_ctx_free(bp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -8795,7 +9675,7 @@ static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)</div><div class='ctx'> </div><div class='ctx'> static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return __bnxt_setup_vnic_p5(bp, vnic_id);</div><div class='ctx'> 	else</div><div class='ctx'> 		return __bnxt_setup_vnic(bp, vnic_id);</div><div class='hunk'>@@ -8803,10 +9683,9 @@ static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)</div><div class='ctx'> </div><div class='ctx'> static int bnxt_alloc_rfs_vnics(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	int i, rc = 0;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;rx_nr_rings; i++) {</div><div class='hunk'>@@ -8819,7 +9698,7 @@ static int bnxt_alloc_rfs_vnics(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> 		vnic = &amp;bp-&gt;vnic_info[vnic_id];</div><div class='ctx'> 		vnic-&gt;flags |= BNXT_VNIC_RFS_FLAG;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_NEW_RSS_CAP)</div><div class='add'>+		if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_NEW_RSS_CAP)</div><div class='ctx'> 			vnic-&gt;flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;</div><div class='ctx'> 		rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);</div><div class='ctx'> 		if (rc) {</div><div class='hunk'>@@ -8832,9 +9711,6 @@ static int bnxt_alloc_rfs_vnics(struct bnxt *bp)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='ctx'> 	return rc;</div><div class='del'>-#else</div><div class='del'>-	return 0;</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */</div><div class='hunk'>@@ -8913,7 +9789,7 @@ static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)</div><div class='ctx'> 	rc = bnxt_setup_vnic(bp, 0);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto err_out;</div><div class='del'>-	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)</div><div class='add'>+	if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)</div><div class='ctx'> 		bnxt_hwrm_update_rss_hash_cfg(bp);</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_RFS) {</div><div class='hunk'>@@ -9031,8 +9907,8 @@ static int bnxt_set_real_num_queues(struct bnxt *bp)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='del'>-			   bool shared)</div><div class='add'>+static int __bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='add'>+			     bool shared)</div><div class='ctx'> {</div><div class='ctx'> 	int _rx = *rx, _tx = *tx;</div><div class='ctx'> </div><div class='hunk'>@@ -9055,6 +9931,46 @@ static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int __bnxt_num_tx_to_cp(struct bnxt *bp, int tx, int tx_sets, int tx_xdp)</div><div class='add'>+{</div><div class='add'>+	return (tx - tx_xdp) / tx_sets + tx_xdp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_num_tx_to_cp(struct bnxt *bp, int tx)</div><div class='add'>+{</div><div class='add'>+	int tcs = netdev_get_num_tc(bp-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (!tcs)</div><div class='add'>+		tcs = 1;</div><div class='add'>+	return __bnxt_num_tx_to_cp(bp, tx, tcs, bp-&gt;tx_nr_rings_xdp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_num_cp_to_tx(struct bnxt *bp, int tx_cp)</div><div class='add'>+{</div><div class='add'>+	int tcs = netdev_get_num_tc(bp-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return (tx_cp - bp-&gt;tx_nr_rings_xdp) * tcs +</div><div class='add'>+	       bp-&gt;tx_nr_rings_xdp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,</div><div class='add'>+			   bool sh)</div><div class='add'>+{</div><div class='add'>+	int tx_cp = bnxt_num_tx_to_cp(bp, *tx);</div><div class='add'>+</div><div class='add'>+	if (tx_cp != *tx) {</div><div class='add'>+		int tx_saved = tx_cp, rc;</div><div class='add'>+</div><div class='add'>+		rc = __bnxt_trim_rings(bp, rx, &amp;tx_cp, max, sh);</div><div class='add'>+		if (rc)</div><div class='add'>+			return rc;</div><div class='add'>+		if (tx_cp != tx_saved)</div><div class='add'>+			*tx = bnxt_num_cp_to_tx(bp, tx_cp);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+	return __bnxt_trim_rings(bp, rx, tx, max, sh);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void bnxt_setup_msix(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	const int len = sizeof(bp-&gt;irq_tbl[0].name);</div><div class='hunk'>@@ -9067,7 +9983,7 @@ static void bnxt_setup_msix(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; tcs; i++) {</div><div class='ctx'> 			count = bp-&gt;tx_nr_rings_per_tc;</div><div class='del'>-			off = i * count;</div><div class='add'>+			off = BNXT_TC_TO_RING_BASE(bp, i);</div><div class='ctx'> 			netdev_set_tc_queue(dev, i, count, off);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -9122,7 +10038,6 @@ static int bnxt_setup_int_mode(struct bnxt *bp)</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	return bp-&gt;hw_resc.max_rsscos_ctxs;</div><div class='hunk'>@@ -9132,7 +10047,6 @@ static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	return bp-&gt;hw_resc.max_vnics;</div><div class='ctx'> }</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)</div><div class='ctx'> {</div><div class='hunk'>@@ -9148,7 +10062,7 @@ static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int cp = bp-&gt;hw_resc.max_cp_rings;</div><div class='ctx'> </div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		cp -= bnxt_get_ulp_msix_num(bp);</div><div class='ctx'> </div><div class='ctx'> 	return cp;</div><div class='hunk'>@@ -9158,7 +10072,7 @@ static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_hw_resc *hw_resc = &amp;bp-&gt;hw_resc;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return min_t(unsigned int, hw_resc-&gt;max_irqs, hw_resc-&gt;max_nqs);</div><div class='ctx'> </div><div class='ctx'> 	return min_t(unsigned int, hw_resc-&gt;max_irqs, hw_resc-&gt;max_cp_rings);</div><div class='hunk'>@@ -9174,7 +10088,7 @@ unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)</div><div class='ctx'> 	unsigned int cp;</div><div class='ctx'> </div><div class='ctx'> 	cp = bnxt_get_max_func_cp_rings_for_en(bp);</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return cp - bp-&gt;rx_nr_rings - bp-&gt;tx_nr_rings;</div><div class='ctx'> 	else</div><div class='ctx'> 		return cp - bp-&gt;cp_nr_rings;</div><div class='hunk'>@@ -9193,7 +10107,7 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num)</div><div class='ctx'> 	int max_idx, avail_msix;</div><div class='ctx'> </div><div class='ctx'> 	max_idx = bp-&gt;total_irqs;</div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		max_idx = min_t(int, bp-&gt;total_irqs, max_cp);</div><div class='ctx'> 	avail_msix = max_idx - bp-&gt;cp_nr_rings;</div><div class='ctx'> 	if (!BNXT_NEW_RM(bp) || avail_msix &gt;= num)</div><div class='hunk'>@@ -9217,7 +10131,7 @@ static int bnxt_get_num_msix(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> static int bnxt_init_msix(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	int i, total_vecs, max, rc = 0, min = 1, ulp_msix;</div><div class='add'>+	int i, total_vecs, max, rc = 0, min = 1, ulp_msix, tx_cp;</div><div class='ctx'> 	struct msix_entry *msix_ent;</div><div class='ctx'> </div><div class='ctx'> 	total_vecs = bnxt_get_num_msix(bp);</div><div class='hunk'>@@ -9259,9 +10173,10 @@ static int bnxt_init_msix(struct bnxt *bp)</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			goto msix_setup_exit;</div><div class='ctx'> </div><div class='add'>+		tx_cp = bnxt_num_tx_to_cp(bp, bp-&gt;tx_nr_rings);</div><div class='ctx'> 		bp-&gt;cp_nr_rings = (min == 1) ?</div><div class='del'>-				  max_t(int, bp-&gt;tx_nr_rings, bp-&gt;rx_nr_rings) :</div><div class='del'>-				  bp-&gt;tx_nr_rings + bp-&gt;rx_nr_rings;</div><div class='add'>+				  max_t(int, tx_cp, bp-&gt;rx_nr_rings) :</div><div class='add'>+				  tx_cp + bp-&gt;rx_nr_rings;</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='ctx'> 		rc = -ENOMEM;</div><div class='hunk'>@@ -9424,6 +10339,7 @@ static int bnxt_request_irq(struct bnxt *bp)</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='add'>+		netif_napi_set_irq(&amp;bp-&gt;bnapi[i]-&gt;napi, irq-&gt;vector);</div><div class='ctx'> 		irq-&gt;requested = 1;</div><div class='ctx'> </div><div class='ctx'> 		if (zalloc_cpumask_var(&amp;irq-&gt;cpu_mask, GFP_KERNEL)) {</div><div class='hunk'>@@ -9451,6 +10367,11 @@ static void bnxt_del_napi(struct bnxt *bp)</div><div class='ctx'> 	if (!bp-&gt;bnapi)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; bp-&gt;rx_nr_rings; i++)</div><div class='add'>+		netif_queue_set_napi(bp-&gt;dev, i, NETDEV_QUEUE_TYPE_RX, NULL);</div><div class='add'>+	for (i = 0; i &lt; bp-&gt;tx_nr_rings - bp-&gt;tx_nr_rings_xdp; i++)</div><div class='add'>+		netif_queue_set_napi(bp-&gt;dev, i, NETDEV_QUEUE_TYPE_TX, NULL);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='ctx'> 		struct bnxt_napi *bnapi = bp-&gt;bnapi[i];</div><div class='ctx'> </div><div class='hunk'>@@ -9471,7 +10392,7 @@ static void bnxt_init_napi(struct bnxt *bp)</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_USING_MSIX) {</div><div class='ctx'> 		int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;</div><div class='ctx'> </div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			poll_fn = bnxt_poll_p5;</div><div class='ctx'> 		else if (BNXT_CHIP_TYPE_NITRO_A0(bp))</div><div class='ctx'> 			cp_nr_rings--;</div><div class='hunk'>@@ -9527,8 +10448,6 @@ static void bnxt_enable_napi(struct bnxt *bp)</div><div class='ctx'> 		cpr = &amp;bnapi-&gt;cp_ring;</div><div class='ctx'> 		bnapi-&gt;in_reset = false;</div><div class='ctx'> </div><div class='del'>-		bnapi-&gt;tx_pkts = 0;</div><div class='del'>-</div><div class='ctx'> 		if (bnapi-&gt;rx_ring) {</div><div class='ctx'> 			INIT_WORK(&amp;cpr-&gt;dim.work, bnxt_dim_work);</div><div class='ctx'> 			cpr-&gt;dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;</div><div class='hunk'>@@ -9632,7 +10551,10 @@ void bnxt_report_link(struct bnxt *bp)</div><div class='ctx'> 				signal = "(NRZ) ";</div><div class='ctx'> 				break;</div><div class='ctx'> 			case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:</div><div class='del'>-				signal = "(PAM4) ";</div><div class='add'>+				signal = "(PAM4 56Gbps) ";</div><div class='add'>+				break;</div><div class='add'>+			case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112:</div><div class='add'>+				signal = "(PAM4 112Gbps) ";</div><div class='ctx'> 				break;</div><div class='ctx'> 			default:</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -9660,7 +10582,9 @@ static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)</div><div class='ctx'> 	if (!resp-&gt;supported_speeds_auto_mode &amp;&amp;</div><div class='ctx'> 	    !resp-&gt;supported_speeds_force_mode &amp;&amp;</div><div class='ctx'> 	    !resp-&gt;supported_pam4_speeds_auto_mode &amp;&amp;</div><div class='del'>-	    !resp-&gt;supported_pam4_speeds_force_mode)</div><div class='add'>+	    !resp-&gt;supported_pam4_speeds_force_mode &amp;&amp;</div><div class='add'>+	    !resp-&gt;supported_speeds2_auto_mode &amp;&amp;</div><div class='add'>+	    !resp-&gt;supported_speeds2_force_mode)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -9706,6 +10630,7 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)</div><div class='ctx'> 			/* Phy re-enabled, reprobe the speeds */</div><div class='ctx'> 			link_info-&gt;support_auto_speeds = 0;</div><div class='ctx'> 			link_info-&gt;support_pam4_auto_speeds = 0;</div><div class='add'>+			link_info-&gt;support_auto_speeds2 = 0;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (resp-&gt;supported_speeds_auto_mode)</div><div class='hunk'>@@ -9714,6 +10639,9 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)</div><div class='ctx'> 	if (resp-&gt;supported_pam4_speeds_auto_mode)</div><div class='ctx'> 		link_info-&gt;support_pam4_auto_speeds =</div><div class='ctx'> 			le16_to_cpu(resp-&gt;supported_pam4_speeds_auto_mode);</div><div class='add'>+	if (resp-&gt;supported_speeds2_auto_mode)</div><div class='add'>+		link_info-&gt;support_auto_speeds2 =</div><div class='add'>+			le16_to_cpu(resp-&gt;supported_speeds2_auto_mode);</div><div class='ctx'> </div><div class='ctx'> 	bp-&gt;port_count = resp-&gt;port_cnt;</div><div class='ctx'> </div><div class='hunk'>@@ -9731,9 +10659,19 @@ static bool bnxt_support_dropped(u16 advertising, u16 supported)</div><div class='ctx'> </div><div class='ctx'> static bool bnxt_support_speed_dropped(struct bnxt_link_info *link_info)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+</div><div class='ctx'> 	/* Check if any advertised speeds are no longer supported. The caller</div><div class='ctx'> 	 * holds the link_lock mutex, so we can modify link_info settings.</div><div class='ctx'> 	 */</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		if (bnxt_support_dropped(link_info-&gt;advertising,</div><div class='add'>+					 link_info-&gt;support_auto_speeds2)) {</div><div class='add'>+			link_info-&gt;advertising = link_info-&gt;support_auto_speeds2;</div><div class='add'>+			return true;</div><div class='add'>+		}</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='ctx'> 	if (bnxt_support_dropped(link_info-&gt;advertising,</div><div class='ctx'> 				 link_info-&gt;support_auto_speeds)) {</div><div class='ctx'> 		link_info-&gt;advertising = link_info-&gt;support_auto_speeds;</div><div class='hunk'>@@ -9782,18 +10720,25 @@ int bnxt_update_link(struct bnxt *bp, bool chng_link_state)</div><div class='ctx'> 	link_info-&gt;lp_pause = resp-&gt;link_partner_adv_pause;</div><div class='ctx'> 	link_info-&gt;force_pause_setting = resp-&gt;force_pause;</div><div class='ctx'> 	link_info-&gt;duplex_setting = resp-&gt;duplex_cfg;</div><div class='del'>-	if (link_info-&gt;phy_link_status == BNXT_LINK_LINK)</div><div class='add'>+	if (link_info-&gt;phy_link_status == BNXT_LINK_LINK) {</div><div class='ctx'> 		link_info-&gt;link_speed = le16_to_cpu(resp-&gt;link_speed);</div><div class='del'>-	else</div><div class='add'>+		if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2)</div><div class='add'>+			link_info-&gt;active_lanes = resp-&gt;active_lanes;</div><div class='add'>+	} else {</div><div class='ctx'> 		link_info-&gt;link_speed = 0;</div><div class='add'>+		link_info-&gt;active_lanes = 0;</div><div class='add'>+	}</div><div class='ctx'> 	link_info-&gt;force_link_speed = le16_to_cpu(resp-&gt;force_link_speed);</div><div class='ctx'> 	link_info-&gt;force_pam4_link_speed =</div><div class='ctx'> 		le16_to_cpu(resp-&gt;force_pam4_link_speed);</div><div class='add'>+	link_info-&gt;force_link_speed2 = le16_to_cpu(resp-&gt;force_link_speeds2);</div><div class='ctx'> 	link_info-&gt;support_speeds = le16_to_cpu(resp-&gt;support_speeds);</div><div class='ctx'> 	link_info-&gt;support_pam4_speeds = le16_to_cpu(resp-&gt;support_pam4_speeds);</div><div class='add'>+	link_info-&gt;support_speeds2 = le16_to_cpu(resp-&gt;support_speeds2);</div><div class='ctx'> 	link_info-&gt;auto_link_speeds = le16_to_cpu(resp-&gt;auto_link_speed_mask);</div><div class='ctx'> 	link_info-&gt;auto_pam4_link_speeds =</div><div class='ctx'> 		le16_to_cpu(resp-&gt;auto_pam4_link_speed_mask);</div><div class='add'>+	link_info-&gt;auto_link_speeds2 = le16_to_cpu(resp-&gt;auto_link_speeds2);</div><div class='ctx'> 	link_info-&gt;lp_auto_link_speeds =</div><div class='ctx'> 		le16_to_cpu(resp-&gt;link_partner_adv_speeds);</div><div class='ctx'> 	link_info-&gt;lp_auto_pam4_link_speeds =</div><div class='hunk'>@@ -9932,7 +10877,11 @@ static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_</div><div class='ctx'> {</div><div class='ctx'> 	if (bp-&gt;link_info.autoneg &amp; BNXT_AUTONEG_SPEED) {</div><div class='ctx'> 		req-&gt;auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;</div><div class='del'>-		if (bp-&gt;link_info.advertising) {</div><div class='add'>+		if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+			req-&gt;enables |=</div><div class='add'>+				cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK);</div><div class='add'>+			req-&gt;auto_link_speeds2_mask = cpu_to_le16(bp-&gt;link_info.advertising);</div><div class='add'>+		} else if (bp-&gt;link_info.advertising) {</div><div class='ctx'> 			req-&gt;enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);</div><div class='ctx'> 			req-&gt;auto_link_speed_mask = cpu_to_le16(bp-&gt;link_info.advertising);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -9946,7 +10895,12 @@ static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_</div><div class='ctx'> 		req-&gt;flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		req-&gt;flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);</div><div class='del'>-		if (bp-&gt;link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {</div><div class='add'>+		if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+			req-&gt;force_link_speeds2 = cpu_to_le16(bp-&gt;link_info.req_link_speed);</div><div class='add'>+			req-&gt;enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2);</div><div class='add'>+			netif_info(bp, link, bp-&gt;dev, "Forcing FW speed2: %d\n",</div><div class='add'>+				   (u32)bp-&gt;link_info.req_link_speed);</div><div class='add'>+		} else if (bp-&gt;link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {</div><div class='ctx'> 			req-&gt;force_pam4_link_speed = cpu_to_le16(bp-&gt;link_info.req_link_speed);</div><div class='ctx'> 			req-&gt;enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -10211,8 +11165,6 @@ static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)</div><div class='ctx'> 			if (!test_bit(BNXT_STATE_IN_FW_RESET, &amp;bp-&gt;state))</div><div class='ctx'> 				bnxt_ulp_stop(bp);</div><div class='ctx'> 			bnxt_free_ctx_mem(bp);</div><div class='del'>-			kfree(bp-&gt;ctx);</div><div class='del'>-			bp-&gt;ctx = NULL;</div><div class='ctx'> 			bnxt_dcb_free(bp);</div><div class='ctx'> 			rc = bnxt_fw_init_one(bp);</div><div class='ctx'> 			if (rc) {</div><div class='hunk'>@@ -10731,10 +11683,8 @@ static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,</div><div class='ctx'> 	bnxt_free_mem(bp, irq_re_init);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)</div><div class='add'>+void bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)</div><div class='ctx'> {</div><div class='del'>-	int rc = 0;</div><div class='del'>-</div><div class='ctx'> 	if (test_bit(BNXT_STATE_IN_FW_RESET, &amp;bp-&gt;state)) {</div><div class='ctx'> 		/* If we get here, it means firmware reset is in progress</div><div class='ctx'> 		 * while we are trying to close.  We can safely proceed with</div><div class='hunk'>@@ -10749,15 +11699,18 @@ int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_BNXT_SRIOV</div><div class='ctx'> 	if (bp-&gt;sriov_cfg) {</div><div class='add'>+		int rc;</div><div class='add'>+</div><div class='ctx'> 		rc = wait_event_interruptible_timeout(bp-&gt;sriov_cfg_wait,</div><div class='ctx'> 						      !bp-&gt;sriov_cfg,</div><div class='ctx'> 						      BNXT_SRIOV_CFG_WAIT_TMO);</div><div class='del'>-		if (rc)</div><div class='del'>-			netdev_warn(bp-&gt;dev, "timeout waiting for SRIOV config operation to complete!\n");</div><div class='add'>+		if (!rc)</div><div class='add'>+			netdev_warn(bp-&gt;dev, "timeout waiting for SRIOV config operation to complete, proceeding to close!\n");</div><div class='add'>+		else if (rc &lt; 0)</div><div class='add'>+			netdev_warn(bp-&gt;dev, "SRIOV config operation interrupted, proceeding to close!\n");</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> 	__bnxt_close_nic(bp, irq_re_init, link_re_init);</div><div class='del'>-	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bnxt_close(struct net_device *dev)</div><div class='hunk'>@@ -11096,7 +12049,6 @@ static int bnxt_cfg_rx_mode(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *dev = bp-&gt;dev;</div><div class='ctx'> 	struct bnxt_vnic_info *vnic = &amp;bp-&gt;vnic_info[0];</div><div class='del'>-	struct hwrm_cfa_l2_filter_free_input *req;</div><div class='ctx'> 	struct netdev_hw_addr *ha;</div><div class='ctx'> 	int i, off = 0, rc;</div><div class='ctx'> 	bool uc_update;</div><div class='hunk'>@@ -11108,16 +12060,12 @@ static int bnxt_cfg_rx_mode(struct bnxt *bp)</div><div class='ctx'> 	if (!uc_update)</div><div class='ctx'> 		goto skip_uc;</div><div class='ctx'> </div><div class='del'>-	rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='del'>-	hwrm_req_hold(bp, req);</div><div class='ctx'> 	for (i = 1; i &lt; vnic-&gt;uc_filter_count; i++) {</div><div class='del'>-		req-&gt;l2_filter_id = vnic-&gt;fw_l2_filter_id[i];</div><div class='add'>+		struct bnxt_l2_filter *fltr = vnic-&gt;l2_filters[i];</div><div class='ctx'> </div><div class='del'>-		rc = hwrm_req_send(bp, req);</div><div class='add'>+		bnxt_hwrm_l2_filter_free(bp, fltr);</div><div class='add'>+		bnxt_del_l2_filter(bp, fltr);</div><div class='ctx'> 	}</div><div class='del'>-	hwrm_req_drop(bp, req);</div><div class='ctx'> </div><div class='ctx'> 	vnic-&gt;uc_filter_count = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -11194,7 +12142,7 @@ static bool bnxt_can_reserve_rings(struct bnxt *bp)</div><div class='ctx'> /* If the chip and firmware supports RFS */</div><div class='ctx'> static bool bnxt_rfs_supported(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)</div><div class='ctx'> 			return true;</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -11204,7 +12152,7 @@ static bool bnxt_rfs_supported(struct bnxt *bp)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	if (BNXT_PF(bp) &amp;&amp; !BNXT_CHIP_TYPE_NITRO_A0(bp))</div><div class='ctx'> 		return true;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_NEW_RSS_CAP)</div><div class='add'>+	if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_NEW_RSS_CAP)</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -11212,10 +12160,9 @@ static bool bnxt_rfs_supported(struct bnxt *bp)</div><div class='ctx'> /* If runtime conditions support RFS */</div><div class='ctx'> static bool bnxt_rfs_capable(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	int vnics, max_vnics, max_rss_ctxs;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return bnxt_rfs_supported(bp);</div><div class='ctx'> 	if (!(bp-&gt;flags &amp; BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp-&gt;rx_nr_rings)</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -11225,7 +12172,7 @@ static bool bnxt_rfs_capable(struct bnxt *bp)</div><div class='ctx'> 	max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);</div><div class='ctx'> </div><div class='ctx'> 	/* RSS contexts not a limiting factor */</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_NEW_RSS_CAP)</div><div class='add'>+	if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_NEW_RSS_CAP)</div><div class='ctx'> 		max_rss_ctxs = max_vnics;</div><div class='ctx'> 	if (vnics &gt; max_vnics || vnics &gt; max_rss_ctxs) {</div><div class='ctx'> 		if (bp-&gt;rx_nr_rings &gt; 1)</div><div class='hunk'>@@ -11248,9 +12195,6 @@ static bool bnxt_rfs_capable(struct bnxt *bp)</div><div class='ctx'> 	netdev_warn(bp-&gt;dev, "Unable to reserve resources to support NTUPLE filters.\n");</div><div class='ctx'> 	bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);</div><div class='ctx'> 	return false;</div><div class='del'>-#else</div><div class='del'>-	return false;</div><div class='del'>-#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static netdev_features_t bnxt_fix_features(struct net_device *dev,</div><div class='hunk'>@@ -11317,7 +12261,7 @@ static int bnxt_set_features(struct net_device *dev, netdev_features_t features)</div><div class='ctx'> 		update_tpa = true;</div><div class='ctx'> 		if ((bp-&gt;flags &amp; BNXT_FLAG_TPA) == 0 ||</div><div class='ctx'> 		    (flags &amp; BNXT_FLAG_TPA) == 0 ||</div><div class='del'>-		    (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+		    (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 			re_init = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -11426,9 +12370,10 @@ static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)</div><div class='ctx'> 	struct udphdr *uh = udp_hdr(skb);</div><div class='ctx'> 	__be16 udp_port = uh-&gt;dest;</div><div class='ctx'> </div><div class='del'>-	if (udp_port != bp-&gt;vxlan_port &amp;&amp; udp_port != bp-&gt;nge_port)</div><div class='add'>+	if (udp_port != bp-&gt;vxlan_port &amp;&amp; udp_port != bp-&gt;nge_port &amp;&amp;</div><div class='add'>+	    udp_port != bp-&gt;vxlan_gpe_port)</div><div class='ctx'> 		return false;</div><div class='del'>-	if (skb-&gt;inner_protocol_type == ENCAP_TYPE_ETHER) {</div><div class='add'>+	if (skb-&gt;inner_protocol == htons(ETH_P_TEB)) {</div><div class='ctx'> 		struct ethhdr *eh = inner_eth_hdr(skb);</div><div class='ctx'> </div><div class='ctx'> 		switch (eh-&gt;h_proto) {</div><div class='hunk'>@@ -11439,6 +12384,11 @@ static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)</div><div class='ctx'> 						 skb_inner_network_offset(skb),</div><div class='ctx'> 						 NULL);</div><div class='ctx'> 		}</div><div class='add'>+	} else if (skb-&gt;inner_protocol == htons(ETH_P_IP)) {</div><div class='add'>+		return true;</div><div class='add'>+	} else if (skb-&gt;inner_protocol == htons(ETH_P_IPV6)) {</div><div class='add'>+		return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),</div><div class='add'>+					 NULL);</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -11559,15 +12509,13 @@ static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,</div><div class='ctx'> </div><div class='ctx'> static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring;</div><div class='del'>-	int i = bnapi-&gt;index;</div><div class='del'>-</div><div class='del'>-	if (!txr)</div><div class='del'>-		return;</div><div class='add'>+	struct bnxt_tx_ring_info *txr;</div><div class='add'>+	int i = bnapi-&gt;index, j;</div><div class='ctx'> </div><div class='del'>-	netdev_info(bnapi-&gt;bp-&gt;dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",</div><div class='del'>-		    i, txr-&gt;tx_ring_struct.fw_ring_id, txr-&gt;tx_prod,</div><div class='del'>-		    txr-&gt;tx_cons);</div><div class='add'>+	bnxt_for_each_napi_tx(j, bnapi, txr)</div><div class='add'>+		netdev_info(bnapi-&gt;bp-&gt;dev, "[%d.%d]: tx{fw_ring: %d prod: %x cons: %x}\n",</div><div class='add'>+			    i, j, txr-&gt;tx_ring_struct.fw_ring_id, txr-&gt;tx_prod,</div><div class='add'>+			    txr-&gt;tx_cons);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)</div><div class='hunk'>@@ -11730,8 +12678,7 @@ static void bnxt_timer(struct timer_list *t)</div><div class='ctx'> 	if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &amp;bp-&gt;state))</div><div class='ctx'> 		bnxt_queue_sp_work(bp, BNXT_RX_MASK_SP_EVENT);</div><div class='ctx'> </div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp; !bp-&gt;chip_rev &amp;&amp;</div><div class='del'>-	    netif_carrier_ok(dev))</div><div class='add'>+	if ((BNXT_CHIP_P5(bp)) &amp;&amp; !bp-&gt;chip_rev &amp;&amp; netif_carrier_ok(dev))</div><div class='ctx'> 		bnxt_queue_sp_work(bp, BNXT_RING_COAL_NOW_SP_EVENT);</div><div class='ctx'> </div><div class='ctx'> bnxt_restart_timer:</div><div class='hunk'>@@ -11840,8 +12787,6 @@ static void bnxt_fw_reset_close(struct bnxt *bp)</div><div class='ctx'> 	if (pci_is_enabled(bp-&gt;pdev))</div><div class='ctx'> 		pci_disable_device(bp-&gt;pdev);</div><div class='ctx'> 	bnxt_free_ctx_mem(bp);</div><div class='del'>-	kfree(bp-&gt;ctx);</div><div class='del'>-	bp-&gt;ctx = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool is_bnxt_fw_ok(struct bnxt *bp)</div><div class='hunk'>@@ -11984,7 +12929,7 @@ static void bnxt_chk_missed_irq(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; bp-&gt;cp_nr_rings; i++) {</div><div class='hunk'>@@ -11997,12 +12942,11 @@ static void bnxt_chk_missed_irq(struct bnxt *bp)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		cpr = &amp;bnapi-&gt;cp_ring;</div><div class='del'>-		for (j = 0; j &lt; 2; j++) {</div><div class='del'>-			struct bnxt_cp_ring_info *cpr2 = cpr-&gt;cp_ring_arr[j];</div><div class='add'>+		for (j = 0; j &lt; cpr-&gt;cp_ring_count; j++) {</div><div class='add'>+			struct bnxt_cp_ring_info *cpr2 = &amp;cpr-&gt;cp_ring_arr[j];</div><div class='ctx'> 			u32 val[2];</div><div class='ctx'> </div><div class='del'>-			if (!cpr2 || cpr2-&gt;has_more_work ||</div><div class='del'>-			    !bnxt_has_work(bp, cpr2))</div><div class='add'>+			if (cpr2-&gt;has_more_work || !bnxt_has_work(bp, cpr2))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='ctx'> 			if (cpr2-&gt;cp_raw_cons != cpr2-&gt;last_cp_raw_cons) {</div><div class='hunk'>@@ -12077,6 +13021,8 @@ static void bnxt_sp_task(struct work_struct *work)</div><div class='ctx'> 		bnxt_cfg_ntp_filters(bp);</div><div class='ctx'> 	if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &amp;bp-&gt;sp_event))</div><div class='ctx'> 		bnxt_hwrm_exec_fwd_req(bp);</div><div class='add'>+	if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &amp;bp-&gt;sp_event))</div><div class='add'>+		netdev_info(bp-&gt;dev, "Receive PF driver unload event!\n");</div><div class='ctx'> 	if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &amp;bp-&gt;sp_event)) {</div><div class='ctx'> 		bnxt_hwrm_port_qstats(bp, 0);</div><div class='ctx'> 		bnxt_hwrm_port_qstats_ext(bp, 0);</div><div class='hunk'>@@ -12161,36 +13107,42 @@ static void bnxt_sp_task(struct work_struct *work)</div><div class='ctx'> 	clear_bit(BNXT_STATE_IN_SP_TASK, &amp;bp-&gt;state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,</div><div class='add'>+				int *max_cp);</div><div class='add'>+</div><div class='ctx'> /* Under rtnl_lock */</div><div class='ctx'> int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,</div><div class='ctx'> 		     int tx_xdp)</div><div class='ctx'> {</div><div class='del'>-	int max_rx, max_tx, tx_sets = 1;</div><div class='add'>+	int max_rx, max_tx, max_cp, tx_sets = 1, tx_cp;</div><div class='ctx'> 	int tx_rings_needed, stats;</div><div class='ctx'> 	int rx_rings = rx;</div><div class='del'>-	int cp, vnics, rc;</div><div class='add'>+	int cp, vnics;</div><div class='ctx'> </div><div class='ctx'> 	if (tcs)</div><div class='ctx'> 		tx_sets = tcs;</div><div class='ctx'> </div><div class='del'>-	rc = bnxt_get_max_rings(bp, &amp;max_rx, &amp;max_tx, sh);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='add'>+	_bnxt_get_max_rings(bp, &amp;max_rx, &amp;max_tx, &amp;max_cp);</div><div class='ctx'> </div><div class='del'>-	if (max_rx &lt; rx)</div><div class='add'>+	if (max_rx &lt; rx_rings)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='add'>+		rx_rings &lt;&lt;= 1;</div><div class='add'>+</div><div class='ctx'> 	tx_rings_needed = tx * tx_sets + tx_xdp;</div><div class='ctx'> 	if (max_tx &lt; tx_rings_needed)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	vnics = 1;</div><div class='del'>-	if ((bp-&gt;flags &amp; (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)</div><div class='del'>-		vnics += rx_rings;</div><div class='add'>+	if ((bp-&gt;flags &amp; (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5_PLUS)) ==</div><div class='add'>+	    BNXT_FLAG_RFS)</div><div class='add'>+		vnics += rx;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='del'>-		rx_rings &lt;&lt;= 1;</div><div class='del'>-	cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;</div><div class='add'>+	tx_cp = __bnxt_num_tx_to_cp(bp, tx_rings_needed, tx_sets, tx_xdp);</div><div class='add'>+	cp = sh ? max_t(int, tx_cp, rx) : tx_cp + rx;</div><div class='add'>+	if (max_cp &lt; cp)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> 	stats = cp;</div><div class='ctx'> 	if (BNXT_NEW_RM(bp)) {</div><div class='ctx'> 		cp += bnxt_get_ulp_msix_num(bp);</div><div class='hunk'>@@ -12265,10 +13217,10 @@ static bool bnxt_fw_pre_resv_vnics(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	u16 fw_maj = BNXT_FW_MAJ(bp), fw_bld = BNXT_FW_BLD(bp);</div><div class='ctx'> </div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp;</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp;</div><div class='ctx'> 	    (fw_maj &gt; 218 || (fw_maj == 218 &amp;&amp; fw_bld &gt;= 18)))</div><div class='ctx'> 		return true;</div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp;</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp;</div><div class='ctx'> 	    (fw_maj &gt; 216 || (fw_maj == 216 &amp;&amp; fw_bld &gt;= 172)))</div><div class='ctx'> 		return true;</div><div class='ctx'> 	return false;</div><div class='hunk'>@@ -12346,15 +13298,15 @@ static int bnxt_fw_init_one_p2(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)</div><div class='ctx'> {</div><div class='del'>-	bp-&gt;flags &amp;= ~BNXT_FLAG_UDP_RSS_CAP;</div><div class='add'>+	bp-&gt;rss_cap &amp;= ~BNXT_RSS_CAP_UDP_RSS_CAP;</div><div class='ctx'> 	bp-&gt;rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |</div><div class='ctx'> 			   VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |</div><div class='ctx'> 			   VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |</div><div class='ctx'> 			   VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;</div><div class='del'>-	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)</div><div class='add'>+	if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)</div><div class='ctx'> 		bp-&gt;rss_hash_delta = bp-&gt;rss_hash_cfg;</div><div class='ctx'> 	if (BNXT_CHIP_P4_PLUS(bp) &amp;&amp; bp-&gt;hwrm_spec_code &gt;= 0x10501) {</div><div class='del'>-		bp-&gt;flags |= BNXT_FLAG_UDP_RSS_CAP;</div><div class='add'>+		bp-&gt;rss_cap |= BNXT_RSS_CAP_UDP_RSS_CAP;</div><div class='ctx'> 		bp-&gt;rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |</div><div class='ctx'> 				    VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -12824,7 +13776,7 @@ int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='ctx'> 	bool sh = false;</div><div class='del'>-	int rc;</div><div class='add'>+	int rc, tx_cp;</div><div class='ctx'> </div><div class='ctx'> 	if (tc &gt; bp-&gt;max_tc) {</div><div class='ctx'> 		netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",</div><div class='hunk'>@@ -12855,8 +13807,9 @@ int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)</div><div class='ctx'> 		netdev_reset_tc(dev);</div><div class='ctx'> 	}</div><div class='ctx'> 	bp-&gt;tx_nr_rings += bp-&gt;tx_nr_rings_xdp;</div><div class='del'>-	bp-&gt;cp_nr_rings = sh ? max_t(int, bp-&gt;tx_nr_rings, bp-&gt;rx_nr_rings) :</div><div class='del'>-			       bp-&gt;tx_nr_rings + bp-&gt;rx_nr_rings;</div><div class='add'>+	tx_cp = bnxt_num_tx_to_cp(bp, bp-&gt;tx_nr_rings);</div><div class='add'>+	bp-&gt;cp_nr_rings = sh ? max_t(int, tx_cp, bp-&gt;rx_nr_rings) :</div><div class='add'>+			       tx_cp + bp-&gt;rx_nr_rings;</div><div class='ctx'> </div><div class='ctx'> 	if (netif_running(bp-&gt;dev))</div><div class='ctx'> 		return bnxt_open_nic(bp, true, false);</div><div class='hunk'>@@ -12906,38 +13859,102 @@ static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='add'>+u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,</div><div class='add'>+			    const struct sk_buff *skb)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_vnic_info *vnic;</div><div class='add'>+</div><div class='add'>+	if (skb)</div><div class='add'>+		return skb_get_hash_raw(skb) &amp; BNXT_NTP_FLTR_HASH_MASK;</div><div class='add'>+</div><div class='add'>+	vnic = &amp;bp-&gt;vnic_info[0];</div><div class='add'>+	return bnxt_toeplitz(bp, fkeys, (void *)vnic-&gt;rss_hash_key);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,</div><div class='add'>+			   u32 idx)</div><div class='add'>+{</div><div class='add'>+	struct hlist_head *head;</div><div class='add'>+	int bit_id;</div><div class='add'>+</div><div class='add'>+	spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	bit_id = bitmap_find_free_region(bp-&gt;ntp_fltr_bmap, BNXT_MAX_FLTR, 0);</div><div class='add'>+	if (bit_id &lt; 0) {</div><div class='add'>+		spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fltr-&gt;base.sw_id = (u16)bit_id;</div><div class='add'>+	fltr-&gt;base.type = BNXT_FLTR_TYPE_NTUPLE;</div><div class='add'>+	fltr-&gt;base.flags |= BNXT_ACT_RING_DST;</div><div class='add'>+	head = &amp;bp-&gt;ntp_fltr_hash_tbl[idx];</div><div class='add'>+	hlist_add_head_rcu(&amp;fltr-&gt;base.hash, head);</div><div class='add'>+	set_bit(BNXT_FLTR_INSERTED, &amp;fltr-&gt;base.state);</div><div class='add'>+	bp-&gt;ntp_fltr_count++;</div><div class='add'>+	spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,</div><div class='ctx'> 			    struct bnxt_ntuple_filter *f2)</div><div class='ctx'> {</div><div class='ctx'> 	struct flow_keys *keys1 = &amp;f1-&gt;fkeys;</div><div class='ctx'> 	struct flow_keys *keys2 = &amp;f2-&gt;fkeys;</div><div class='ctx'> </div><div class='add'>+	if (f1-&gt;ntuple_flags != f2-&gt;ntuple_flags)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	if (keys1-&gt;basic.n_proto != keys2-&gt;basic.n_proto ||</div><div class='ctx'> 	    keys1-&gt;basic.ip_proto != keys2-&gt;basic.ip_proto)</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (keys1-&gt;basic.n_proto == htons(ETH_P_IP)) {</div><div class='del'>-		if (keys1-&gt;addrs.v4addrs.src != keys2-&gt;addrs.v4addrs.src ||</div><div class='del'>-		    keys1-&gt;addrs.v4addrs.dst != keys2-&gt;addrs.v4addrs.dst)</div><div class='add'>+		if (((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) &amp;&amp;</div><div class='add'>+		     keys1-&gt;addrs.v4addrs.src != keys2-&gt;addrs.v4addrs.src) ||</div><div class='add'>+		    ((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) &amp;&amp;</div><div class='add'>+		     keys1-&gt;addrs.v4addrs.dst != keys2-&gt;addrs.v4addrs.dst))</div><div class='ctx'> 			return false;</div><div class='ctx'> 	} else {</div><div class='del'>-		if (memcmp(&amp;keys1-&gt;addrs.v6addrs.src, &amp;keys2-&gt;addrs.v6addrs.src,</div><div class='del'>-			   sizeof(keys1-&gt;addrs.v6addrs.src)) ||</div><div class='del'>-		    memcmp(&amp;keys1-&gt;addrs.v6addrs.dst, &amp;keys2-&gt;addrs.v6addrs.dst,</div><div class='del'>-			   sizeof(keys1-&gt;addrs.v6addrs.dst)))</div><div class='add'>+		if (((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) &amp;&amp;</div><div class='add'>+		     memcmp(&amp;keys1-&gt;addrs.v6addrs.src,</div><div class='add'>+			    &amp;keys2-&gt;addrs.v6addrs.src,</div><div class='add'>+			    sizeof(keys1-&gt;addrs.v6addrs.src))) ||</div><div class='add'>+		    ((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) &amp;&amp;</div><div class='add'>+		     memcmp(&amp;keys1-&gt;addrs.v6addrs.dst,</div><div class='add'>+			    &amp;keys2-&gt;addrs.v6addrs.dst,</div><div class='add'>+			    sizeof(keys1-&gt;addrs.v6addrs.dst))))</div><div class='ctx'> 			return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (keys1-&gt;ports.ports == keys2-&gt;ports.ports &amp;&amp;</div><div class='del'>-	    keys1-&gt;control.flags == keys2-&gt;control.flags &amp;&amp;</div><div class='del'>-	    ether_addr_equal(f1-&gt;src_mac_addr, f2-&gt;src_mac_addr) &amp;&amp;</div><div class='del'>-	    ether_addr_equal(f1-&gt;dst_mac_addr, f2-&gt;dst_mac_addr))</div><div class='add'>+	if (((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_PORT) &amp;&amp;</div><div class='add'>+	     keys1-&gt;ports.src != keys2-&gt;ports.src) ||</div><div class='add'>+	    ((f1-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_PORT) &amp;&amp;</div><div class='add'>+	     keys1-&gt;ports.dst != keys2-&gt;ports.dst))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (keys1-&gt;control.flags == keys2-&gt;control.flags &amp;&amp;</div><div class='add'>+	    f1-&gt;l2_fltr == f2-&gt;l2_fltr)</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct bnxt_ntuple_filter *</div><div class='add'>+bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,</div><div class='add'>+				struct bnxt_ntuple_filter *fltr, u32 idx)</div><div class='add'>+{</div><div class='add'>+	struct bnxt_ntuple_filter *f;</div><div class='add'>+	struct hlist_head *head;</div><div class='add'>+</div><div class='add'>+	head = &amp;bp-&gt;ntp_fltr_hash_tbl[idx];</div><div class='add'>+	hlist_for_each_entry_rcu(f, head, base.hash) {</div><div class='add'>+		if (bnxt_fltr_match(f, fltr))</div><div class='add'>+			return f;</div><div class='add'>+	}</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,</div><div class='ctx'> 			      u16 rxq_index, u32 flow_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -12945,29 +13962,31 @@ static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,</div><div class='ctx'> 	struct bnxt_ntuple_filter *fltr, *new_fltr;</div><div class='ctx'> 	struct flow_keys *fkeys;</div><div class='ctx'> 	struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);</div><div class='del'>-	int rc = 0, idx, bit_id, l2_idx = 0;</div><div class='del'>-	struct hlist_head *head;</div><div class='add'>+	struct bnxt_l2_filter *l2_fltr;</div><div class='add'>+	int rc = 0, idx;</div><div class='ctx'> 	u32 flags;</div><div class='ctx'> </div><div class='del'>-	if (!ether_addr_equal(dev-&gt;dev_addr, eth-&gt;h_dest)) {</div><div class='del'>-		struct bnxt_vnic_info *vnic = &amp;bp-&gt;vnic_info[0];</div><div class='del'>-		int off = 0, j;</div><div class='add'>+	if (ether_addr_equal(dev-&gt;dev_addr, eth-&gt;h_dest)) {</div><div class='add'>+		l2_fltr = bp-&gt;vnic_info[0].l2_filters[0];</div><div class='add'>+		atomic_inc(&amp;l2_fltr-&gt;refcnt);</div><div class='add'>+	} else {</div><div class='add'>+		struct bnxt_l2_key key;</div><div class='ctx'> </div><div class='del'>-		netif_addr_lock_bh(dev);</div><div class='del'>-		for (j = 0; j &lt; vnic-&gt;uc_filter_count; j++, off += ETH_ALEN) {</div><div class='del'>-			if (ether_addr_equal(eth-&gt;h_dest,</div><div class='del'>-					     vnic-&gt;uc_list + off)) {</div><div class='del'>-				l2_idx = j + 1;</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		netif_addr_unlock_bh(dev);</div><div class='del'>-		if (!l2_idx)</div><div class='add'>+		ether_addr_copy(key.dst_mac_addr, eth-&gt;h_dest);</div><div class='add'>+		key.vlan = 0;</div><div class='add'>+		l2_fltr = bnxt_lookup_l2_filter_from_key(bp, &amp;key);</div><div class='add'>+		if (!l2_fltr)</div><div class='ctx'> 			return -EINVAL;</div><div class='add'>+		if (l2_fltr-&gt;base.flags &amp; BNXT_ACT_FUNC_DST) {</div><div class='add'>+			bnxt_del_l2_filter(bp, l2_fltr);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);</div><div class='del'>-	if (!new_fltr)</div><div class='add'>+	if (!new_fltr) {</div><div class='add'>+		bnxt_del_l2_filter(bp, l2_fltr);</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	fkeys = &amp;new_fltr-&gt;fkeys;</div><div class='ctx'> 	if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {</div><div class='hunk'>@@ -12994,49 +14013,52 @@ static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	memcpy(new_fltr-&gt;dst_mac_addr, eth-&gt;h_dest, ETH_ALEN);</div><div class='del'>-	memcpy(new_fltr-&gt;src_mac_addr, eth-&gt;h_source, ETH_ALEN);</div><div class='add'>+	new_fltr-&gt;l2_fltr = l2_fltr;</div><div class='add'>+	new_fltr-&gt;ntuple_flags = BNXT_NTUPLE_MATCH_ALL;</div><div class='ctx'> </div><div class='del'>-	idx = skb_get_hash_raw(skb) &amp; BNXT_NTP_FLTR_HASH_MASK;</div><div class='del'>-	head = &amp;bp-&gt;ntp_fltr_hash_tbl[idx];</div><div class='add'>+	idx = bnxt_get_ntp_filter_idx(bp, fkeys, skb);</div><div class='ctx'> 	rcu_read_lock();</div><div class='del'>-	hlist_for_each_entry_rcu(fltr, head, hash) {</div><div class='del'>-		if (bnxt_fltr_match(fltr, new_fltr)) {</div><div class='del'>-			rc = fltr-&gt;sw_id;</div><div class='del'>-			rcu_read_unlock();</div><div class='del'>-			goto err_free;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	rcu_read_unlock();</div><div class='del'>-</div><div class='del'>-	spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='del'>-	bit_id = bitmap_find_free_region(bp-&gt;ntp_fltr_bmap,</div><div class='del'>-					 BNXT_NTP_FLTR_MAX_FLTR, 0);</div><div class='del'>-	if (bit_id &lt; 0) {</div><div class='del'>-		spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='del'>-		rc = -ENOMEM;</div><div class='add'>+	fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);</div><div class='add'>+	if (fltr) {</div><div class='add'>+		rc = fltr-&gt;base.sw_id;</div><div class='add'>+		rcu_read_unlock();</div><div class='ctx'> 		goto err_free;</div><div class='ctx'> 	}</div><div class='add'>+	rcu_read_unlock();</div><div class='ctx'> </div><div class='del'>-	new_fltr-&gt;sw_id = (u16)bit_id;</div><div class='ctx'> 	new_fltr-&gt;flow_id = flow_id;</div><div class='del'>-	new_fltr-&gt;l2_fltr_idx = l2_idx;</div><div class='del'>-	new_fltr-&gt;rxq = rxq_index;</div><div class='del'>-	hlist_add_head_rcu(&amp;new_fltr-&gt;hash, head);</div><div class='del'>-	bp-&gt;ntp_fltr_count++;</div><div class='del'>-	spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='del'>-</div><div class='del'>-	bnxt_queue_sp_work(bp, BNXT_RX_NTP_FLTR_SP_EVENT);</div><div class='del'>-</div><div class='del'>-	return new_fltr-&gt;sw_id;</div><div class='add'>+	new_fltr-&gt;base.rxq = rxq_index;</div><div class='add'>+	rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);</div><div class='add'>+	if (!rc) {</div><div class='add'>+		bnxt_queue_sp_work(bp, BNXT_RX_NTP_FLTR_SP_EVENT);</div><div class='add'>+		return new_fltr-&gt;base.sw_id;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> err_free:</div><div class='add'>+	bnxt_del_l2_filter(bp, l2_fltr);</div><div class='ctx'> 	kfree(new_fltr);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr)</div><div class='add'>+{</div><div class='add'>+	spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	if (!test_and_clear_bit(BNXT_FLTR_INSERTED, &amp;fltr-&gt;base.state)) {</div><div class='add'>+		spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	hlist_del_rcu(&amp;fltr-&gt;base.hash);</div><div class='add'>+	bp-&gt;ntp_fltr_count--;</div><div class='add'>+	spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='add'>+	bnxt_del_l2_filter(bp, fltr-&gt;l2_fltr);</div><div class='add'>+	clear_bit(fltr-&gt;base.sw_id, bp-&gt;ntp_fltr_bmap);</div><div class='add'>+	kfree_rcu(fltr, base.rcu);</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static void bnxt_cfg_ntp_filters(struct bnxt *bp)</div><div class='ctx'> {</div><div class='add'>+#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; BNXT_NTP_FLTR_HASH_SIZE; i++) {</div><div class='hunk'>@@ -13046,13 +14068,15 @@ static void bnxt_cfg_ntp_filters(struct bnxt *bp)</div><div class='ctx'> 		int rc;</div><div class='ctx'> </div><div class='ctx'> 		head = &amp;bp-&gt;ntp_fltr_hash_tbl[i];</div><div class='del'>-		hlist_for_each_entry_safe(fltr, tmp, head, hash) {</div><div class='add'>+		hlist_for_each_entry_safe(fltr, tmp, head, base.hash) {</div><div class='ctx'> 			bool del = false;</div><div class='ctx'> </div><div class='del'>-			if (test_bit(BNXT_FLTR_VALID, &amp;fltr-&gt;state)) {</div><div class='del'>-				if (rps_may_expire_flow(bp-&gt;dev, fltr-&gt;rxq,</div><div class='add'>+			if (test_bit(BNXT_FLTR_VALID, &amp;fltr-&gt;base.state)) {</div><div class='add'>+				if (fltr-&gt;base.flags &amp; BNXT_ACT_NO_AGING)</div><div class='add'>+					continue;</div><div class='add'>+				if (rps_may_expire_flow(bp-&gt;dev, fltr-&gt;base.rxq,</div><div class='ctx'> 							fltr-&gt;flow_id,</div><div class='del'>-							fltr-&gt;sw_id)) {</div><div class='add'>+							fltr-&gt;base.sw_id)) {</div><div class='ctx'> 					bnxt_hwrm_cfa_ntuple_filter_free(bp,</div><div class='ctx'> 									 fltr);</div><div class='ctx'> 					del = true;</div><div class='hunk'>@@ -13063,32 +14087,16 @@ static void bnxt_cfg_ntp_filters(struct bnxt *bp)</div><div class='ctx'> 				if (rc)</div><div class='ctx'> 					del = true;</div><div class='ctx'> 				else</div><div class='del'>-					set_bit(BNXT_FLTR_VALID, &amp;fltr-&gt;state);</div><div class='add'>+					set_bit(BNXT_FLTR_VALID, &amp;fltr-&gt;base.state);</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='del'>-			if (del) {</div><div class='del'>-				spin_lock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='del'>-				hlist_del_rcu(&amp;fltr-&gt;hash);</div><div class='del'>-				bp-&gt;ntp_fltr_count--;</div><div class='del'>-				spin_unlock_bh(&amp;bp-&gt;ntp_fltr_lock);</div><div class='del'>-				synchronize_rcu();</div><div class='del'>-				clear_bit(fltr-&gt;sw_id, bp-&gt;ntp_fltr_bmap);</div><div class='del'>-				kfree(fltr);</div><div class='del'>-			}</div><div class='add'>+			if (del)</div><div class='add'>+				bnxt_del_ntp_filter(bp, fltr);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &amp;bp-&gt;sp_event))</div><div class='del'>-		netdev_info(bp-&gt;dev, "Receive PF driver unload event!\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#else</div><div class='del'>-</div><div class='del'>-static void bnxt_cfg_ntp_filters(struct bnxt *bp)</div><div class='del'>-{</div><div class='add'>+#endif</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#endif /* CONFIG_RFS_ACCEL */</div><div class='del'>-</div><div class='ctx'> static int bnxt_udp_tunnel_set_port(struct net_device *netdev, unsigned int table,</div><div class='ctx'> 				    unsigned int entry, struct udp_tunnel_info *ti)</div><div class='ctx'> {</div><div class='hunk'>@@ -13096,9 +14104,11 @@ static int bnxt_udp_tunnel_set_port(struct net_device *netdev, unsigned int tabl</div><div class='ctx'> 	unsigned int cmd;</div><div class='ctx'> </div><div class='ctx'> 	if (ti-&gt;type == UDP_TUNNEL_TYPE_VXLAN)</div><div class='del'>-		cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;</div><div class='add'>+		cmd = TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN;</div><div class='add'>+	else if (ti-&gt;type == UDP_TUNNEL_TYPE_GENEVE)</div><div class='add'>+		cmd = TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE;</div><div class='ctx'> 	else</div><div class='del'>-		cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;</div><div class='add'>+		cmd = TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE;</div><div class='ctx'> </div><div class='ctx'> 	return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti-&gt;port, cmd);</div><div class='ctx'> }</div><div class='hunk'>@@ -13111,8 +14121,10 @@ static int bnxt_udp_tunnel_unset_port(struct net_device *netdev, unsigned int ta</div><div class='ctx'> </div><div class='ctx'> 	if (ti-&gt;type == UDP_TUNNEL_TYPE_VXLAN)</div><div class='ctx'> 		cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;</div><div class='del'>-	else</div><div class='add'>+	else if (ti-&gt;type == UDP_TUNNEL_TYPE_GENEVE)</div><div class='ctx'> 		cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;</div><div class='add'>+	else</div><div class='add'>+		cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE;</div><div class='ctx'> </div><div class='ctx'> 	return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);</div><div class='ctx'> }</div><div class='hunk'>@@ -13126,6 +14138,16 @@ static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {</div><div class='ctx'> 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },</div><div class='ctx'> 		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },</div><div class='ctx'> 	},</div><div class='add'>+}, bnxt_udp_tunnels_p7 = {</div><div class='add'>+	.set_port	= bnxt_udp_tunnel_set_port,</div><div class='add'>+	.unset_port	= bnxt_udp_tunnel_unset_port,</div><div class='add'>+	.flags		= UDP_TUNNEL_NIC_INFO_MAY_SLEEP |</div><div class='add'>+			  UDP_TUNNEL_NIC_INFO_OPEN_ONLY,</div><div class='add'>+	.tables		= {</div><div class='add'>+		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },</div><div class='add'>+		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },</div><div class='add'>+		{ .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN_GPE, },</div><div class='add'>+	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,</div><div class='hunk'>@@ -13233,6 +14255,8 @@ static void bnxt_remove_one(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	bnxt_ptp_clear(bp);</div><div class='ctx'> 	unregister_netdev(dev);</div><div class='add'>+	bnxt_free_l2_filters(bp, true);</div><div class='add'>+	bnxt_free_ntp_fltrs(bp, true);</div><div class='ctx'> 	clear_bit(BNXT_STATE_IN_FW_RESET, &amp;bp-&gt;state);</div><div class='ctx'> 	/* Flush any pending tasks */</div><div class='ctx'> 	cancel_work_sync(&amp;bp-&gt;sp_task);</div><div class='hunk'>@@ -13255,8 +14279,6 @@ static void bnxt_remove_one(struct pci_dev *pdev)</div><div class='ctx'> 	bp-&gt;fw_health = NULL;</div><div class='ctx'> 	bnxt_cleanup_pci(bp);</div><div class='ctx'> 	bnxt_free_ctx_mem(bp);</div><div class='del'>-	kfree(bp-&gt;ctx);</div><div class='del'>-	bp-&gt;ctx = NULL;</div><div class='ctx'> 	kfree(bp-&gt;rss_indir_tbl);</div><div class='ctx'> 	bp-&gt;rss_indir_tbl = NULL;</div><div class='ctx'> 	bnxt_free_port_stats(bp);</div><div class='hunk'>@@ -13325,7 +14347,7 @@ static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,</div><div class='ctx'> 	max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -</div><div class='ctx'> 			bnxt_get_ulp_msix_num(bp),</div><div class='ctx'> 			hw_resc-&gt;max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));</div><div class='del'>-	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 		*max_cp = min_t(int, *max_cp, max_irq);</div><div class='ctx'> 	max_ring_grps = hw_resc-&gt;max_hw_ring_grps;</div><div class='ctx'> 	if (BNXT_CHIP_TYPE_NITRO_A0(bp) &amp;&amp; BNXT_PF(bp)) {</div><div class='hunk'>@@ -13334,8 +14356,14 @@ static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,</div><div class='ctx'> 	}</div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_AGG_RINGS)</div><div class='ctx'> 		*max_rx &gt;&gt;= 1;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='add'>+		int rc;</div><div class='add'>+</div><div class='add'>+		rc = __bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);</div><div class='add'>+		if (rc) {</div><div class='add'>+			*max_rx = 0;</div><div class='add'>+			*max_tx = 0;</div><div class='add'>+		}</div><div class='ctx'> 		/* On P5 chips, max_cp output param should be available NQs */</div><div class='ctx'> 		*max_cp = max_irq;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -13636,7 +14664,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	max_irqs = bnxt_get_max_irq(pdev);</div><div class='del'>-	dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);</div><div class='add'>+	dev = alloc_etherdev_mqs(sizeof(*bp), max_irqs * BNXT_MAX_QUEUE,</div><div class='add'>+				 max_irqs);</div><div class='ctx'> 	if (!dev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -13678,10 +14707,10 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	if (BNXT_PF(bp))</div><div class='ctx'> 		bnxt_vpd_read_info(bp);</div><div class='ctx'> </div><div class='del'>-	if (BNXT_CHIP_P5(bp)) {</div><div class='del'>-		bp-&gt;flags |= BNXT_FLAG_CHIP_P5;</div><div class='del'>-		if (BNXT_CHIP_SR2(bp))</div><div class='del'>-			bp-&gt;flags |= BNXT_FLAG_CHIP_SR2;</div><div class='add'>+	if (BNXT_CHIP_P5_PLUS(bp)) {</div><div class='add'>+		bp-&gt;flags |= BNXT_FLAG_CHIP_P5_PLUS;</div><div class='add'>+		if (BNXT_CHIP_P7(bp))</div><div class='add'>+			bp-&gt;flags |= BNXT_FLAG_CHIP_P7;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rc = bnxt_alloc_rss_indir_tbl(bp);</div><div class='hunk'>@@ -13706,6 +14735,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 			   NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |</div><div class='ctx'> 			   NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |</div><div class='ctx'> 			   NETIF_F_RXCSUM | NETIF_F_GRO;</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_UDP_GSO_CAP)</div><div class='add'>+		dev-&gt;hw_features |= NETIF_F_GSO_UDP_L4;</div><div class='ctx'> </div><div class='ctx'> 	if (BNXT_SUPPORTS_TPA(bp))</div><div class='ctx'> 		dev-&gt;hw_features |= NETIF_F_LRO;</div><div class='hunk'>@@ -13716,7 +14747,12 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 			NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |</div><div class='ctx'> 			NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |</div><div class='ctx'> 			NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;</div><div class='del'>-	dev-&gt;udp_tunnel_nic_info = &amp;bnxt_udp_tunnels;</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_UDP_GSO_CAP)</div><div class='add'>+		dev-&gt;hw_enc_features |= NETIF_F_GSO_UDP_L4;</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P7)</div><div class='add'>+		dev-&gt;udp_tunnel_nic_info = &amp;bnxt_udp_tunnels_p7;</div><div class='add'>+	else</div><div class='add'>+		dev-&gt;udp_tunnel_nic_info = &amp;bnxt_udp_tunnels;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |</div><div class='ctx'> 				    NETIF_F_GSO_GRE_CSUM;</div><div class='hunk'>@@ -13744,7 +14780,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		bp-&gt;gro_func = bnxt_gro_func_5730x;</div><div class='ctx'> 		if (BNXT_CHIP_P4(bp))</div><div class='ctx'> 			bp-&gt;gro_func = bnxt_gro_func_5731x;</div><div class='del'>-		else if (BNXT_CHIP_P5(bp))</div><div class='add'>+		else if (BNXT_CHIP_P5_PLUS(bp))</div><div class='ctx'> 			bp-&gt;gro_func = bnxt_gro_func_5750x;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!BNXT_CHIP_P4_PLUS(bp))</div><div class='hunk'>@@ -13770,6 +14806,7 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto init_err_pci_clean;</div><div class='ctx'> </div><div class='add'>+	bnxt_init_l2_fltr_tbl(bp);</div><div class='ctx'> 	bnxt_set_rx_skb_mode(bp, false);</div><div class='ctx'> 	bnxt_set_tpa_flags(bp);</div><div class='ctx'> 	bnxt_set_ring_params(bp);</div><div class='hunk'>@@ -13852,8 +14889,6 @@ init_err_pci_clean:</div><div class='ctx'> 	bp-&gt;fw_health = NULL;</div><div class='ctx'> 	bnxt_cleanup_pci(bp);</div><div class='ctx'> 	bnxt_free_ctx_mem(bp);</div><div class='del'>-	kfree(bp-&gt;ctx);</div><div class='del'>-	bp-&gt;ctx = NULL;</div><div class='ctx'> 	kfree(bp-&gt;rss_indir_tbl);</div><div class='ctx'> 	bp-&gt;rss_indir_tbl = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -13906,8 +14941,6 @@ static int bnxt_suspend(struct device *device)</div><div class='ctx'> 	bnxt_hwrm_func_drv_unrgtr(bp);</div><div class='ctx'> 	pci_disable_device(bp-&gt;pdev);</div><div class='ctx'> 	bnxt_free_ctx_mem(bp);</div><div class='del'>-	kfree(bp-&gt;ctx);</div><div class='del'>-	bp-&gt;ctx = NULL;</div><div class='ctx'> 	rtnl_unlock();</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='hunk'>@@ -13940,6 +14973,8 @@ static int bnxt_resume(struct device *device)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto resume_exit;</div><div class='ctx'> </div><div class='add'>+	bnxt_clear_reservations(bp, true);</div><div class='add'>+</div><div class='ctx'> 	if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {</div><div class='ctx'> 		rc = -ENODEV;</div><div class='ctx'> 		goto resume_exit;</div><div class='hunk'>@@ -14004,8 +15039,6 @@ static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,</div><div class='ctx'> 	if (pci_is_enabled(pdev))</div><div class='ctx'> 		pci_disable_device(pdev);</div><div class='ctx'> 	bnxt_free_ctx_mem(bp);</div><div class='del'>-	kfree(bp-&gt;ctx);</div><div class='del'>-	bp-&gt;ctx = NULL;</div><div class='ctx'> 	rtnl_unlock();</div><div class='ctx'> </div><div class='ctx'> 	/* Request a slot slot reset. */</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h<br/>index e702dbc3e6b1..b8ef1717cb65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt.h</a></div><div class='hunk'>@@ -18,7 +18,7 @@</div><div class='ctx'>  */</div><div class='ctx'> #define DRV_VER_MAJ	1</div><div class='ctx'> #define DRV_VER_MIN	10</div><div class='del'>-#define DRV_VER_UPD	2</div><div class='add'>+#define DRV_VER_UPD	3</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/ethtool.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='hunk'>@@ -61,6 +61,24 @@ struct tx_bd {</div><div class='ctx'> 	__le64 tx_bd_haddr;</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='add'>+#define TX_OPAQUE_IDX_MASK	0x0000ffff</div><div class='add'>+#define TX_OPAQUE_BDS_MASK	0x00ff0000</div><div class='add'>+#define TX_OPAQUE_BDS_SHIFT	16</div><div class='add'>+#define TX_OPAQUE_RING_MASK	0xff000000</div><div class='add'>+#define TX_OPAQUE_RING_SHIFT	24</div><div class='add'>+</div><div class='add'>+#define SET_TX_OPAQUE(bp, txr, idx, bds)				\</div><div class='add'>+	(((txr)-&gt;tx_napi_idx &lt;&lt; TX_OPAQUE_RING_SHIFT) |			\</div><div class='add'>+	 ((bds) &lt;&lt; TX_OPAQUE_BDS_SHIFT) | ((idx) &amp; (bp)-&gt;tx_ring_mask))</div><div class='add'>+</div><div class='add'>+#define TX_OPAQUE_IDX(opq)	((opq) &amp; TX_OPAQUE_IDX_MASK)</div><div class='add'>+#define TX_OPAQUE_RING(opq)	(((opq) &amp; TX_OPAQUE_RING_MASK) &gt;&gt;	\</div><div class='add'>+				 TX_OPAQUE_RING_SHIFT)</div><div class='add'>+#define TX_OPAQUE_BDS(opq)	(((opq) &amp; TX_OPAQUE_BDS_MASK) &gt;&gt;	\</div><div class='add'>+				 TX_OPAQUE_BDS_SHIFT)</div><div class='add'>+#define TX_OPAQUE_PROD(bp, opq)	((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &amp;\</div><div class='add'>+				 (bp)-&gt;tx_ring_mask)</div><div class='add'>+</div><div class='ctx'> struct tx_bd_ext {</div><div class='ctx'> 	__le32 tx_bd_hsize_lflags;</div><div class='ctx'> 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 &lt;&lt; 0)</div><div class='hunk'>@@ -121,11 +139,15 @@ struct tx_cmp {</div><div class='ctx'> 	__le32 tx_cmp_flags_type;</div><div class='ctx'> 	#define CMP_TYPE					(0x3f &lt;&lt; 0)</div><div class='ctx'> 	 #define CMP_TYPE_TX_L2_CMP				 0</div><div class='add'>+	 #define CMP_TYPE_TX_L2_COAL_CMP			 2</div><div class='add'>+	 #define CMP_TYPE_TX_L2_PKT_TS_CMP			 4</div><div class='ctx'> 	 #define CMP_TYPE_RX_L2_CMP				 17</div><div class='ctx'> 	 #define CMP_TYPE_RX_AGG_CMP				 18</div><div class='ctx'> 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19</div><div class='ctx'> 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21</div><div class='ctx'> 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22</div><div class='add'>+	 #define CMP_TYPE_RX_L2_V3_CMP				 23</div><div class='add'>+	 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP		 25</div><div class='ctx'> 	 #define CMP_TYPE_STATUS_CMP				 32</div><div class='ctx'> 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34</div><div class='ctx'> 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36</div><div class='hunk'>@@ -152,16 +174,20 @@ struct tx_cmp {</div><div class='ctx'> 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 &lt;&lt; 6)</div><div class='ctx'> 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 &lt;&lt; 7)</div><div class='ctx'> </div><div class='del'>-	__le32 tx_cmp_unsed_3;</div><div class='add'>+	__le32 sq_cons_idx;</div><div class='add'>+	#define TX_CMP_SQ_CONS_IDX_MASK				0x00ffffff</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define TX_CMP_SQ_CONS_IDX(txcmp)					\</div><div class='add'>+	(le32_to_cpu((txcmp)-&gt;sq_cons_idx) &amp; TX_CMP_SQ_CONS_IDX_MASK)</div><div class='add'>+</div><div class='ctx'> struct rx_cmp {</div><div class='ctx'> 	__le32 rx_cmp_len_flags_type;</div><div class='ctx'> 	#define RX_CMP_CMP_TYPE					(0x3f &lt;&lt; 0)</div><div class='ctx'> 	#define RX_CMP_FLAGS_ERROR				(1 &lt;&lt; 6)</div><div class='ctx'> 	#define RX_CMP_FLAGS_PLACEMENT				(7 &lt;&lt; 7)</div><div class='ctx'> 	#define RX_CMP_FLAGS_RSS_VALID				(1 &lt;&lt; 10)</div><div class='del'>-	#define RX_CMP_FLAGS_UNUSED				(1 &lt;&lt; 11)</div><div class='add'>+	#define RX_CMP_FLAGS_PKT_METADATA_PRESENT		(1 &lt;&lt; 11)</div><div class='ctx'> 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12</div><div class='ctx'> 	 #define RX_CMP_FLAGS_ITYPES_MASK			 0xf000</div><div class='ctx'> 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 &lt;&lt; 12)</div><div class='hunk'>@@ -182,12 +208,30 @@ struct rx_cmp {</div><div class='ctx'> 	 #define RX_CMP_AGG_BUFS_SHIFT				 1</div><div class='ctx'> 	#define RX_CMP_RSS_HASH_TYPE				(0x7f &lt;&lt; 9)</div><div class='ctx'> 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9</div><div class='add'>+	#define RX_CMP_V3_RSS_EXT_OP_LEGACY			(0xf &lt;&lt; 12)</div><div class='add'>+	 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT		 12</div><div class='add'>+	#define RX_CMP_V3_RSS_EXT_OP_NEW			(0xf &lt;&lt; 8)</div><div class='add'>+	 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT			 8</div><div class='ctx'> 	#define RX_CMP_PAYLOAD_OFFSET				(0xff &lt;&lt; 16)</div><div class='ctx'> 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16</div><div class='add'>+	#define RX_CMP_SUB_NS_TS				(0xf &lt;&lt; 16)</div><div class='add'>+	 #define RX_CMP_SUB_NS_TS_SHIFT				 16</div><div class='add'>+	#define RX_CMP_METADATA1				(0xf &lt;&lt; 28)</div><div class='add'>+	 #define RX_CMP_METADATA1_SHIFT				 28</div><div class='add'>+	#define RX_CMP_METADATA1_TPID_SEL			(0x7 &lt;&lt; 28)</div><div class='add'>+	#define RX_CMP_METADATA1_TPID_8021Q			(0x1 &lt;&lt; 28)</div><div class='add'>+	#define RX_CMP_METADATA1_TPID_8021AD			(0x0 &lt;&lt; 28)</div><div class='add'>+	#define RX_CMP_METADATA1_VALID				(0x8 &lt;&lt; 28)</div><div class='ctx'> </div><div class='ctx'> 	__le32 rx_cmp_rss_hash;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define BNXT_PTP_RX_TS_VALID(flags)				\</div><div class='add'>+	(((flags) &amp; RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)</div><div class='add'>+</div><div class='add'>+#define BNXT_ALL_RX_TS_VALID(flags)				\</div><div class='add'>+	!((flags) &amp; RX_CMP_FLAGS_PKT_METADATA_PRESENT)</div><div class='add'>+</div><div class='ctx'> #define RX_CMP_HASH_VALID(rxcmp)				\</div><div class='ctx'> 	((rxcmp)-&gt;rx_cmp_len_flags_type &amp; cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))</div><div class='ctx'> </div><div class='hunk'>@@ -197,6 +241,30 @@ struct rx_cmp {</div><div class='ctx'> 	(((le32_to_cpu((rxcmp)-&gt;rx_cmp_misc_v1) &amp; RX_CMP_RSS_HASH_TYPE) &gt;&gt;\</div><div class='ctx'> 	  RX_CMP_RSS_HASH_TYPE_SHIFT) &amp; RSS_PROFILE_ID_MASK)</div><div class='ctx'> </div><div class='add'>+#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp)				\</div><div class='add'>+	((le32_to_cpu((rxcmp)-&gt;rx_cmp_misc_v1) &amp; RX_CMP_V3_RSS_EXT_OP_LEGACY) &gt;&gt;\</div><div class='add'>+	 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)</div><div class='add'>+</div><div class='add'>+#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp)				\</div><div class='add'>+	((le32_to_cpu((rxcmp)-&gt;rx_cmp_misc_v1) &amp; RX_CMP_V3_RSS_EXT_OP_NEW) &gt;&gt;\</div><div class='add'>+	 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)</div><div class='add'>+</div><div class='add'>+#define RX_CMP_V3_HASH_TYPE(bp, rxcmp)				\</div><div class='add'>+	(((bp)-&gt;rss_cap &amp; BNXT_RSS_CAP_RSS_TCAM) ?		\</div><div class='add'>+	  RX_CMP_V3_HASH_TYPE_NEW(rxcmp) :			\</div><div class='add'>+	  RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))</div><div class='add'>+</div><div class='add'>+#define EXT_OP_INNER_4		0x0</div><div class='add'>+#define EXT_OP_OUTER_4		0x2</div><div class='add'>+#define EXT_OP_INNFL_3		0x8</div><div class='add'>+#define EXT_OP_OUTFL_3		0xa</div><div class='add'>+</div><div class='add'>+#define RX_CMP_VLAN_VALID(rxcmp)				\</div><div class='add'>+	((rxcmp)-&gt;rx_cmp_misc_v1 &amp; cpu_to_le32(RX_CMP_METADATA1_VALID))</div><div class='add'>+</div><div class='add'>+#define RX_CMP_VLAN_TPID_SEL(rxcmp)				\</div><div class='add'>+	(le32_to_cpu((rxcmp)-&gt;rx_cmp_misc_v1) &amp; RX_CMP_METADATA1_TPID_SEL)</div><div class='add'>+</div><div class='ctx'> struct rx_cmp_ext {</div><div class='ctx'> 	__le32 rx_cmp_flags2;</div><div class='ctx'> 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1</div><div class='hunk'>@@ -244,6 +312,9 @@ struct rx_cmp_ext {</div><div class='ctx'> </div><div class='ctx'> 	#define RX_CMPL_CFA_CODE_MASK				(0xffff &lt;&lt; 16)</div><div class='ctx'> 	 #define RX_CMPL_CFA_CODE_SFT				 16</div><div class='add'>+	#define RX_CMPL_METADATA0_TCI_MASK			(0xffff &lt;&lt; 16)</div><div class='add'>+	#define RX_CMPL_METADATA0_VID_MASK			(0x0fff &lt;&lt; 16)</div><div class='add'>+	 #define RX_CMPL_METADATA0_SFT				 16</div><div class='ctx'> </div><div class='ctx'> 	__le32 rx_cmp_timestamp;</div><div class='ctx'> };</div><div class='hunk'>@@ -269,6 +340,10 @@ struct rx_cmp_ext {</div><div class='ctx'> 	((le32_to_cpu((rxcmpl1)-&gt;rx_cmp_cfa_code_errors_v2) &amp;		\</div><div class='ctx'> 	  RX_CMPL_CFA_CODE_MASK) &gt;&gt; RX_CMPL_CFA_CODE_SFT)</div><div class='ctx'> </div><div class='add'>+#define RX_CMP_METADATA0_TCI(rxcmp1)					\</div><div class='add'>+	((le32_to_cpu((rxcmp1)-&gt;rx_cmp_cfa_code_errors_v2) &amp;		\</div><div class='add'>+	  RX_CMPL_METADATA0_TCI_MASK) &gt;&gt; RX_CMPL_METADATA0_SFT)</div><div class='add'>+</div><div class='ctx'> struct rx_agg_cmp {</div><div class='ctx'> 	__le32 rx_agg_cmp_len_flags_type;</div><div class='ctx'> 	#define RX_AGG_CMP_TYPE					(0x3f &lt;&lt; 0)</div><div class='hunk'>@@ -311,10 +386,18 @@ struct rx_tpa_start_cmp {</div><div class='ctx'> 	#define RX_TPA_START_CMP_V1				(0x1 &lt;&lt; 0)</div><div class='ctx'> 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f &lt;&lt; 9)</div><div class='ctx'> 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9</div><div class='add'>+	#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE		(0x1ff &lt;&lt; 7)</div><div class='add'>+	 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT	 7</div><div class='ctx'> 	#define RX_TPA_START_CMP_AGG_ID				(0x7f &lt;&lt; 25)</div><div class='ctx'> 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25</div><div class='ctx'> 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff &lt;&lt; 16)</div><div class='ctx'> 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16</div><div class='add'>+	#define RX_TPA_START_CMP_METADATA1			(0xf &lt;&lt; 28)</div><div class='add'>+	 #define RX_TPA_START_CMP_METADATA1_SHIFT		 28</div><div class='add'>+	#define RX_TPA_START_METADATA1_TPID_SEL			(0x7 &lt;&lt; 28)</div><div class='add'>+	#define RX_TPA_START_METADATA1_TPID_8021Q		(0x1 &lt;&lt; 28)</div><div class='add'>+	#define RX_TPA_START_METADATA1_TPID_8021AD		(0x0 &lt;&lt; 28)</div><div class='add'>+	#define RX_TPA_START_METADATA1_VALID			(0x8 &lt;&lt; 28)</div><div class='ctx'> </div><div class='ctx'> 	__le32 rx_tpa_start_cmp_rss_hash;</div><div class='ctx'> };</div><div class='hunk'>@@ -328,6 +411,11 @@ struct rx_tpa_start_cmp {</div><div class='ctx'> 	   RX_TPA_START_CMP_RSS_HASH_TYPE) &gt;&gt;				\</div><div class='ctx'> 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) &amp; RSS_PROFILE_ID_MASK)</div><div class='ctx'> </div><div class='add'>+#define TPA_START_V3_HASH_TYPE(rx_tpa_start)				\</div><div class='add'>+	(((le32_to_cpu((rx_tpa_start)-&gt;rx_tpa_start_cmp_misc_v1) &amp;	\</div><div class='add'>+	   RX_TPA_START_CMP_V3_RSS_HASH_TYPE) &gt;&gt;			\</div><div class='add'>+	  RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) &amp; RSS_PROFILE_ID_MASK)</div><div class='add'>+</div><div class='ctx'> #define TPA_START_AGG_ID(rx_tpa_start)					\</div><div class='ctx'> 	((le32_to_cpu((rx_tpa_start)-&gt;rx_tpa_start_cmp_misc_v1) &amp;	\</div><div class='ctx'> 	 RX_TPA_START_CMP_AGG_ID) &gt;&gt; RX_TPA_START_CMP_AGG_ID_SHIFT)</div><div class='hunk'>@@ -340,6 +428,14 @@ struct rx_tpa_start_cmp {</div><div class='ctx'> 	((rx_tpa_start)-&gt;rx_tpa_start_cmp_len_flags_type &amp;		\</div><div class='ctx'> 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))</div><div class='ctx'> </div><div class='add'>+#define TPA_START_VLAN_VALID(rx_tpa_start)				\</div><div class='add'>+	((rx_tpa_start)-&gt;rx_tpa_start_cmp_misc_v1 &amp;			\</div><div class='add'>+	 cpu_to_le32(RX_TPA_START_METADATA1_VALID))</div><div class='add'>+</div><div class='add'>+#define TPA_START_VLAN_TPID_SEL(rx_tpa_start)				\</div><div class='add'>+	(le32_to_cpu((rx_tpa_start)-&gt;rx_tpa_start_cmp_misc_v1) &amp;	\</div><div class='add'>+	 RX_TPA_START_METADATA1_TPID_SEL)</div><div class='add'>+</div><div class='ctx'> struct rx_tpa_start_cmp_ext {</div><div class='ctx'> 	__le32 rx_tpa_start_cmp_flags2;</div><div class='ctx'> 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 &lt;&lt; 0)</div><div class='hunk'>@@ -350,6 +446,8 @@ struct rx_tpa_start_cmp_ext {</div><div class='ctx'> 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 &lt;&lt; 9)</div><div class='ctx'> 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 &lt;&lt; 10)</div><div class='ctx'> 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10</div><div class='add'>+	#define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE		(0x1 &lt;&lt; 10)</div><div class='add'>+	#define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO		(0x1 &lt;&lt; 11)</div><div class='ctx'> 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff &lt;&lt; 16)</div><div class='ctx'> 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16</div><div class='ctx'> </div><div class='hunk'>@@ -363,6 +461,9 @@ struct rx_tpa_start_cmp_ext {</div><div class='ctx'> 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 &lt;&lt; 1)</div><div class='ctx'> 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff &lt;&lt; 16)</div><div class='ctx'> 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16</div><div class='add'>+	#define RX_TPA_START_CMP_METADATA0_TCI_MASK		(0xffff &lt;&lt; 16)</div><div class='add'>+	#define RX_TPA_START_CMP_METADATA0_VID_MASK		(0x0fff &lt;&lt; 16)</div><div class='add'>+	 #define RX_TPA_START_CMP_METADATA0_SFT			 16</div><div class='ctx'> 	__le32 rx_tpa_start_cmp_hdr_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -379,6 +480,11 @@ struct rx_tpa_start_cmp_ext {</div><div class='ctx'> 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) &gt;&gt;			\</div><div class='ctx'> 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)</div><div class='ctx'> </div><div class='add'>+#define TPA_START_METADATA0_TCI(rx_tpa_start)				\</div><div class='add'>+	((le32_to_cpu((rx_tpa_start)-&gt;rx_tpa_start_cmp_cfa_code_v2) &amp;	\</div><div class='add'>+	  RX_TPA_START_CMP_METADATA0_TCI_MASK) &gt;&gt;			\</div><div class='add'>+	 RX_TPA_START_CMP_METADATA0_SFT)</div><div class='add'>+</div><div class='ctx'> struct rx_tpa_end_cmp {</div><div class='ctx'> 	__le32 rx_tpa_end_cmp_len_flags_type;</div><div class='ctx'> 	#define RX_TPA_END_CMP_TYPE				(0x3f &lt;&lt; 0)</div><div class='hunk'>@@ -523,6 +629,8 @@ struct nqe_cn {</div><div class='ctx'> 	#define NQ_CN_TYPE_SFT            0</div><div class='ctx'> 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL</div><div class='ctx'> 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION</div><div class='add'>+	#define NQ_CN_TOGGLE_MASK         0xc0UL</div><div class='add'>+	#define NQ_CN_TOGGLE_SFT          6</div><div class='ctx'> 	__le16	reserved16;</div><div class='ctx'> 	__le32	cq_handle_low;</div><div class='ctx'> 	__le32	v;</div><div class='hunk'>@@ -530,6 +638,23 @@ struct nqe_cn {</div><div class='ctx'> 	__le32	cq_handle_high;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define BNXT_NQ_HDL_IDX_MASK	0x00ffffff</div><div class='add'>+#define BNXT_NQ_HDL_TYPE_MASK	0xff000000</div><div class='add'>+#define BNXT_NQ_HDL_TYPE_SHIFT	24</div><div class='add'>+#define BNXT_NQ_HDL_TYPE_RX	0x00</div><div class='add'>+#define BNXT_NQ_HDL_TYPE_TX	0x01</div><div class='add'>+</div><div class='add'>+#define BNXT_NQ_HDL_IDX(hdl)	((hdl) &amp; BNXT_NQ_HDL_IDX_MASK)</div><div class='add'>+#define BNXT_NQ_HDL_TYPE(hdl)	(((hdl) &amp; BNXT_NQ_HDL_TYPE_MASK) &gt;&gt;	\</div><div class='add'>+				 BNXT_NQ_HDL_TYPE_SHIFT)</div><div class='add'>+</div><div class='add'>+#define BNXT_SET_NQ_HDL(cpr)						\</div><div class='add'>+	(((cpr)-&gt;cp_ring_type &lt;&lt; BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)-&gt;cp_idx)</div><div class='add'>+</div><div class='add'>+#define NQE_CN_TYPE(type)	((type) &amp; NQ_CN_TYPE_MASK)</div><div class='add'>+#define NQE_CN_TOGGLE(type)	(((type) &amp; NQ_CN_TOGGLE_MASK) &gt;&gt;	\</div><div class='add'>+				 NQ_CN_TOGGLE_SFT)</div><div class='add'>+</div><div class='ctx'> #define DB_IDX_MASK						0xffffff</div><div class='ctx'> #define DB_IDX_VALID						(0x1 &lt;&lt; 26)</div><div class='ctx'> #define DB_IRQ_DIS						(0x1 &lt;&lt; 27)</div><div class='hunk'>@@ -545,9 +670,14 @@ struct nqe_cn {</div><div class='ctx'> </div><div class='ctx'> /* 64-bit doorbell */</div><div class='ctx'> #define DBR_INDEX_MASK					0x0000000000ffffffULL</div><div class='add'>+#define DBR_EPOCH_MASK					0x01000000UL</div><div class='add'>+#define DBR_EPOCH_SFT					24</div><div class='add'>+#define DBR_TOGGLE_MASK					0x06000000UL</div><div class='add'>+#define DBR_TOGGLE_SFT					25</div><div class='ctx'> #define DBR_XID_MASK					0x000fffff00000000ULL</div><div class='ctx'> #define DBR_XID_SFT					32</div><div class='ctx'> #define DBR_PATH_L2					(0x1ULL &lt;&lt; 56)</div><div class='add'>+#define DBR_VALID					(0x1ULL &lt;&lt; 58)</div><div class='ctx'> #define DBR_TYPE_SQ					(0x0ULL &lt;&lt; 60)</div><div class='ctx'> #define DBR_TYPE_RQ					(0x1ULL &lt;&lt; 60)</div><div class='ctx'> #define DBR_TYPE_SRQ					(0x2ULL &lt;&lt; 60)</div><div class='hunk'>@@ -560,6 +690,7 @@ struct nqe_cn {</div><div class='ctx'> #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL &lt;&lt; 60)</div><div class='ctx'> #define DBR_TYPE_NQ					(0xaULL &lt;&lt; 60)</div><div class='ctx'> #define DBR_TYPE_NQ_ARM					(0xbULL &lt;&lt; 60)</div><div class='add'>+#define DBR_TYPE_NQ_MASK				(0xeULL &lt;&lt; 60)</div><div class='ctx'> #define DBR_TYPE_NULL					(0xfULL &lt;&lt; 60)</div><div class='ctx'> </div><div class='ctx'> #define DB_PF_OFFSET_P5					0x10000</div><div class='hunk'>@@ -655,10 +786,12 @@ struct nqe_cn {</div><div class='ctx'>  */</div><div class='ctx'> #define BNXT_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)</div><div class='ctx'> </div><div class='del'>-#define RX_RING(x)	(((x) &amp; ~(RX_DESC_CNT - 1)) &gt;&gt; (BNXT_PAGE_SHIFT - 4))</div><div class='add'>+#define RX_RING(bp, x)	(((x) &amp; (bp)-&gt;rx_ring_mask) &gt;&gt; (BNXT_PAGE_SHIFT - 4))</div><div class='add'>+#define RX_AGG_RING(bp, x)	(((x) &amp; (bp)-&gt;rx_agg_ring_mask) &gt;&gt;	\</div><div class='add'>+				 (BNXT_PAGE_SHIFT - 4))</div><div class='ctx'> #define RX_IDX(x)	((x) &amp; (RX_DESC_CNT - 1))</div><div class='ctx'> </div><div class='del'>-#define TX_RING(x)	(((x) &amp; ~(TX_DESC_CNT - 1)) &gt;&gt; (BNXT_PAGE_SHIFT - 4))</div><div class='add'>+#define TX_RING(bp, x)	(((x) &amp; (bp)-&gt;tx_ring_mask) &gt;&gt; (BNXT_PAGE_SHIFT - 4))</div><div class='ctx'> #define TX_IDX(x)	((x) &amp; (TX_DESC_CNT - 1))</div><div class='ctx'> </div><div class='ctx'> #define CP_RING(x)	(((x) &amp; ~(CP_DESC_CNT - 1)) &gt;&gt; (BNXT_PAGE_SHIFT - 4))</div><div class='hunk'>@@ -685,11 +818,14 @@ struct nqe_cn {</div><div class='ctx'> #define RX_CMP_TYPE(rxcmp)					\</div><div class='ctx'> 	(le32_to_cpu((rxcmp)-&gt;rx_cmp_len_flags_type) &amp; RX_CMP_CMP_TYPE)</div><div class='ctx'> </div><div class='del'>-#define NEXT_RX(idx)		(((idx) + 1) &amp; bp-&gt;rx_ring_mask)</div><div class='add'>+#define RING_RX(bp, idx)	((idx) &amp; (bp)-&gt;rx_ring_mask)</div><div class='add'>+#define NEXT_RX(idx)		((idx) + 1)</div><div class='ctx'> </div><div class='del'>-#define NEXT_RX_AGG(idx)	(((idx) + 1) &amp; bp-&gt;rx_agg_ring_mask)</div><div class='add'>+#define RING_RX_AGG(bp, idx)	((idx) &amp; (bp)-&gt;rx_agg_ring_mask)</div><div class='add'>+#define NEXT_RX_AGG(idx)	((idx) + 1)</div><div class='ctx'> </div><div class='del'>-#define NEXT_TX(idx)		(((idx) + 1) &amp; bp-&gt;tx_ring_mask)</div><div class='add'>+#define RING_TX(bp, idx)	((idx) &amp; (bp)-&gt;tx_ring_mask)</div><div class='add'>+#define NEXT_TX(idx)		((idx) + 1)</div><div class='ctx'> </div><div class='ctx'> #define ADV_RAW_CMP(idx, n)	((idx) + (n))</div><div class='ctx'> #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)</div><div class='hunk'>@@ -702,6 +838,7 @@ struct nqe_cn {</div><div class='ctx'> #define BNXT_AGG_EVENT		2</div><div class='ctx'> #define BNXT_TX_EVENT		4</div><div class='ctx'> #define BNXT_REDIRECT_EVENT	8</div><div class='add'>+#define BNXT_TX_CMP_EVENT	0x10</div><div class='ctx'> </div><div class='ctx'> struct bnxt_sw_tx_bd {</div><div class='ctx'> 	union {</div><div class='hunk'>@@ -730,13 +867,6 @@ struct bnxt_sw_rx_agg_bd {</div><div class='ctx'> 	dma_addr_t		mapping;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct bnxt_mem_init {</div><div class='del'>-	u8	init_val;</div><div class='del'>-	u16	offset;</div><div class='del'>-#define	BNXT_MEM_INVALID_OFFSET	0xffff</div><div class='del'>-	u16	size;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct bnxt_ring_mem_info {</div><div class='ctx'> 	int			nr_pages;</div><div class='ctx'> 	int			page_size;</div><div class='hunk'>@@ -746,7 +876,7 @@ struct bnxt_ring_mem_info {</div><div class='ctx'> #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4</div><div class='ctx'> </div><div class='ctx'> 	u16			depth;</div><div class='del'>-	struct bnxt_mem_init	*mem_init;</div><div class='add'>+	struct bnxt_ctx_mem_type	*ctx_mem;</div><div class='ctx'> </div><div class='ctx'> 	void			**pg_arr;</div><div class='ctx'> 	dma_addr_t		*dma_arr;</div><div class='hunk'>@@ -788,13 +918,27 @@ struct bnxt_db_info {</div><div class='ctx'> 		u64		db_key64;</div><div class='ctx'> 		u32		db_key32;</div><div class='ctx'> 	};</div><div class='add'>+	u32			db_ring_mask;</div><div class='add'>+	u32			db_epoch_mask;</div><div class='add'>+	u8			db_epoch_shift;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define DB_EPOCH(db, idx)	(((idx) &amp; (db)-&gt;db_epoch_mask) &lt;&lt;	\</div><div class='add'>+				 ((db)-&gt;db_epoch_shift))</div><div class='add'>+</div><div class='add'>+#define DB_TOGGLE(tgl)		((tgl) &lt;&lt; DBR_TOGGLE_SFT)</div><div class='add'>+</div><div class='add'>+#define DB_RING_IDX(db, idx)	(((idx) &amp; (db)-&gt;db_ring_mask) |		\</div><div class='add'>+				 DB_EPOCH(db, idx))</div><div class='add'>+</div><div class='ctx'> struct bnxt_tx_ring_info {</div><div class='ctx'> 	struct bnxt_napi	*bnapi;</div><div class='add'>+	struct bnxt_cp_ring_info	*tx_cpr;</div><div class='ctx'> 	u16			tx_prod;</div><div class='ctx'> 	u16			tx_cons;</div><div class='add'>+	u16			tx_hw_cons;</div><div class='ctx'> 	u16			txq_index;</div><div class='add'>+	u8			tx_napi_idx;</div><div class='ctx'> 	u8			kick_pending;</div><div class='ctx'> 	struct bnxt_db_info	tx_db;</div><div class='ctx'> </div><div class='hunk'>@@ -889,6 +1033,8 @@ struct bnxt_tpa_info {</div><div class='ctx'> </div><div class='ctx'> 	u16			cfa_code; /* cfa_code in TPA start compl */</div><div class='ctx'> 	u8			agg_count;</div><div class='add'>+	u8			vlan_valid:1;</div><div class='add'>+	u8			cfa_code_valid:1;</div><div class='ctx'> 	struct rx_agg_cmp	*agg_arr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -901,6 +1047,7 @@ struct bnxt_tpa_idx_map {</div><div class='ctx'> </div><div class='ctx'> struct bnxt_rx_ring_info {</div><div class='ctx'> 	struct bnxt_napi	*bnapi;</div><div class='add'>+	struct bnxt_cp_ring_info	*rx_cpr;</div><div class='ctx'> 	u16			rx_prod;</div><div class='ctx'> 	u16			rx_agg_prod;</div><div class='ctx'> 	u16			rx_sw_agg_prod;</div><div class='hunk'>@@ -980,6 +1127,11 @@ struct bnxt_cp_ring_info {</div><div class='ctx'> </div><div class='ctx'> 	u8			had_work_done:1;</div><div class='ctx'> 	u8			has_more_work:1;</div><div class='add'>+	u8			had_nqe_notify:1;</div><div class='add'>+	u8			toggle;</div><div class='add'>+</div><div class='add'>+	u8			cp_ring_type;</div><div class='add'>+	u8			cp_idx;</div><div class='ctx'> </div><div class='ctx'> 	u32			last_cp_raw_cons;</div><div class='ctx'> </div><div class='hunk'>@@ -1004,11 +1156,18 @@ struct bnxt_cp_ring_info {</div><div class='ctx'> </div><div class='ctx'> 	struct bnxt_ring_struct	cp_ring_struct;</div><div class='ctx'> </div><div class='del'>-	struct bnxt_cp_ring_info *cp_ring_arr[2];</div><div class='del'>-#define BNXT_RX_HDL	0</div><div class='del'>-#define BNXT_TX_HDL	1</div><div class='add'>+	int			cp_ring_count;</div><div class='add'>+	struct bnxt_cp_ring_info *cp_ring_arr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define BNXT_MAX_QUEUE		8</div><div class='add'>+#define BNXT_MAX_TXR_PER_NAPI	BNXT_MAX_QUEUE</div><div class='add'>+</div><div class='add'>+#define bnxt_for_each_napi_tx(iter, bnapi, txr)		\</div><div class='add'>+	for (iter = 0, txr = (bnapi)-&gt;tx_ring[0]; txr;	\</div><div class='add'>+	     txr = (iter &lt; BNXT_MAX_TXR_PER_NAPI - 1) ?	\</div><div class='add'>+	     (bnapi)-&gt;tx_ring[++iter] : NULL)</div><div class='add'>+</div><div class='ctx'> struct bnxt_napi {</div><div class='ctx'> 	struct napi_struct	napi;</div><div class='ctx'> 	struct bnxt		*bp;</div><div class='hunk'>@@ -1016,11 +1175,10 @@ struct bnxt_napi {</div><div class='ctx'> 	int			index;</div><div class='ctx'> 	struct bnxt_cp_ring_info	cp_ring;</div><div class='ctx'> 	struct bnxt_rx_ring_info	*rx_ring;</div><div class='del'>-	struct bnxt_tx_ring_info	*tx_ring;</div><div class='add'>+	struct bnxt_tx_ring_info	*tx_ring[BNXT_MAX_TXR_PER_NAPI];</div><div class='ctx'> </div><div class='ctx'> 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,</div><div class='ctx'> 					  int budget);</div><div class='del'>-	int			tx_pkts;</div><div class='ctx'> 	u8			events;</div><div class='ctx'> 	u8			tx_fault:1;</div><div class='ctx'> </div><div class='hunk'>@@ -1061,7 +1219,7 @@ struct bnxt_vnic_info {</div><div class='ctx'> 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];</div><div class='ctx'> 	u16		fw_l2_ctx_id;</div><div class='ctx'> #define BNXT_MAX_UC_ADDRS	4</div><div class='del'>-	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];</div><div class='add'>+	struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];</div><div class='ctx'> 				/* index 0 always dev_addr */</div><div class='ctx'> 	u16		uc_filter_count;</div><div class='ctx'> 	u8		*uc_list;</div><div class='hunk'>@@ -1174,19 +1332,71 @@ struct bnxt_pf_info {</div><div class='ctx'> 	struct bnxt_vf_info	*vf;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct bnxt_ntuple_filter {</div><div class='add'>+struct bnxt_filter_base {</div><div class='ctx'> 	struct hlist_node	hash;</div><div class='del'>-	u8			dst_mac_addr[ETH_ALEN];</div><div class='del'>-	u8			src_mac_addr[ETH_ALEN];</div><div class='del'>-	struct flow_keys	fkeys;</div><div class='ctx'> 	__le64			filter_id;</div><div class='add'>+	u8			type;</div><div class='add'>+#define BNXT_FLTR_TYPE_NTUPLE	1</div><div class='add'>+#define BNXT_FLTR_TYPE_L2	2</div><div class='add'>+	u8			flags;</div><div class='add'>+#define BNXT_ACT_DROP		1</div><div class='add'>+#define BNXT_ACT_RING_DST	2</div><div class='add'>+#define BNXT_ACT_FUNC_DST	4</div><div class='add'>+#define BNXT_ACT_NO_AGING	8</div><div class='ctx'> 	u16			sw_id;</div><div class='del'>-	u8			l2_fltr_idx;</div><div class='ctx'> 	u16			rxq;</div><div class='del'>-	u32			flow_id;</div><div class='add'>+	u16			fw_vnic_id;</div><div class='add'>+	u16			vf_idx;</div><div class='ctx'> 	unsigned long		state;</div><div class='ctx'> #define BNXT_FLTR_VALID		0</div><div class='del'>-#define BNXT_FLTR_UPDATE	1</div><div class='add'>+#define BNXT_FLTR_INSERTED	1</div><div class='add'>+#define BNXT_FLTR_FW_DELETED	2</div><div class='add'>+</div><div class='add'>+	struct rcu_head         rcu;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bnxt_ntuple_filter {</div><div class='add'>+	struct bnxt_filter_base	base;</div><div class='add'>+	struct flow_keys	fkeys;</div><div class='add'>+	struct bnxt_l2_filter	*l2_fltr;</div><div class='add'>+	u32			ntuple_flags;</div><div class='add'>+#define BNXT_NTUPLE_MATCH_SRC_IP	1</div><div class='add'>+#define BNXT_NTUPLE_MATCH_DST_IP	2</div><div class='add'>+#define BNXT_NTUPLE_MATCH_SRC_PORT	4</div><div class='add'>+#define BNXT_NTUPLE_MATCH_DST_PORT	8</div><div class='add'>+#define BNXT_NTUPLE_MATCH_ALL		(BNXT_NTUPLE_MATCH_SRC_IP |	\</div><div class='add'>+					 BNXT_NTUPLE_MATCH_DST_IP |	\</div><div class='add'>+					 BNXT_NTUPLE_MATCH_SRC_PORT |	\</div><div class='add'>+					 BNXT_NTUPLE_MATCH_DST_PORT)</div><div class='add'>+	u32			flow_id;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bnxt_l2_key {</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			u8	dst_mac_addr[ETH_ALEN];</div><div class='add'>+			u16	vlan;</div><div class='add'>+		};</div><div class='add'>+		u32	filter_key;</div><div class='add'>+	};</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bnxt_ipv4_tuple {</div><div class='add'>+	struct flow_dissector_key_ipv4_addrs v4addrs;</div><div class='add'>+	struct flow_dissector_key_ports ports;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct bnxt_ipv6_tuple {</div><div class='add'>+	struct flow_dissector_key_ipv6_addrs v6addrs;</div><div class='add'>+	struct flow_dissector_key_ports ports;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define BNXT_L2_KEY_SIZE	(sizeof(struct bnxt_l2_key) / 4)</div><div class='add'>+</div><div class='add'>+struct bnxt_l2_filter {</div><div class='add'>+	struct bnxt_filter_base	base;</div><div class='add'>+	struct bnxt_l2_key	l2_key;</div><div class='add'>+	atomic_t		refcnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct bnxt_link_info {</div><div class='hunk'>@@ -1208,6 +1418,7 @@ struct bnxt_link_info {</div><div class='ctx'> #define BNXT_LINK_STATE_DOWN	1</div><div class='ctx'> #define BNXT_LINK_STATE_UP	2</div><div class='ctx'> #define BNXT_LINK_IS_UP(bp)	((bp)-&gt;link_info.link_state == BNXT_LINK_STATE_UP)</div><div class='add'>+	u8			active_lanes;</div><div class='ctx'> 	u8			duplex;</div><div class='ctx'> #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF</div><div class='ctx'> #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL</div><div class='hunk'>@@ -1242,8 +1453,11 @@ struct bnxt_link_info {</div><div class='ctx'> #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB</div><div class='ctx'> #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB</div><div class='ctx'> #define BNXT_LINK_SPEED_200GB	PORT_PHY_QCFG_RESP_LINK_SPEED_200GB</div><div class='add'>+#define BNXT_LINK_SPEED_400GB	PORT_PHY_QCFG_RESP_LINK_SPEED_400GB</div><div class='ctx'> 	u16			support_speeds;</div><div class='ctx'> 	u16			support_pam4_speeds;</div><div class='add'>+	u16			support_speeds2;</div><div class='add'>+</div><div class='ctx'> 	u16			auto_link_speeds;	/* fw adv setting */</div><div class='ctx'> #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB</div><div class='ctx'> #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB</div><div class='hunk'>@@ -1259,12 +1473,52 @@ struct bnxt_link_info {</div><div class='ctx'> #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G</div><div class='ctx'> #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G</div><div class='ctx'> #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G</div><div class='add'>+	u16			auto_link_speeds2;</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112</div><div class='add'>+#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112</div><div class='add'>+</div><div class='ctx'> 	u16			support_auto_speeds;</div><div class='ctx'> 	u16			support_pam4_auto_speeds;</div><div class='add'>+	u16			support_auto_speeds2;</div><div class='add'>+</div><div class='ctx'> 	u16			lp_auto_link_speeds;</div><div class='ctx'> 	u16			lp_auto_pam4_link_speeds;</div><div class='ctx'> 	u16			force_link_speed;</div><div class='ctx'> 	u16			force_pam4_link_speed;</div><div class='add'>+	u16			force_link_speed2;</div><div class='add'>+#define BNXT_LINK_SPEED_50GB_PAM4	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEED_100GB_PAM4	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEED_200GB_PAM4	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEED_400GB_PAM4	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56</div><div class='add'>+#define BNXT_LINK_SPEED_100GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112</div><div class='add'>+#define BNXT_LINK_SPEED_200GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112</div><div class='add'>+#define BNXT_LINK_SPEED_400GB_PAM4_112	\</div><div class='add'>+	PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112</div><div class='add'>+</div><div class='ctx'> 	u32			preemphasis;</div><div class='ctx'> 	u8			module_status;</div><div class='ctx'> 	u8			active_fec_sig_mode;</div><div class='hunk'>@@ -1295,6 +1549,7 @@ struct bnxt_link_info {</div><div class='ctx'> 	u8			req_signal_mode;</div><div class='ctx'> #define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ</div><div class='ctx'> #define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4</div><div class='add'>+#define BNXT_SIG_MODE_PAM4_112	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112</div><div class='ctx'> #define BNXT_SIG_MODE_MAX	(PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)</div><div class='ctx'> 	u8			req_duplex;</div><div class='ctx'> 	u8			req_flow_ctrl;</div><div class='hunk'>@@ -1355,8 +1610,6 @@ struct bnxt_link_info {</div><div class='ctx'> 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\</div><div class='ctx'> 	 BNXT_FEC_RS_OFF(link_info))</div><div class='ctx'> </div><div class='del'>-#define BNXT_MAX_QUEUE	8</div><div class='del'>-</div><div class='ctx'> struct bnxt_queue_info {</div><div class='ctx'> 	u8	queue_id;</div><div class='ctx'> 	u8	queue_profile;</div><div class='hunk'>@@ -1385,7 +1638,7 @@ struct bnxt_test_info {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define CHIMP_REG_VIEW_ADDR				\</div><div class='del'>-	((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)</div><div class='add'>+	((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)</div><div class='ctx'> </div><div class='ctx'> #define BNXT_GRCPF_REG_CHIMP_COMM		0x0</div><div class='ctx'> #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100</div><div class='hunk'>@@ -1509,53 +1762,73 @@ do {									\</div><div class='ctx'> 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;	\</div><div class='ctx'> } while (0)</div><div class='ctx'> </div><div class='add'>+struct bnxt_ctx_mem_type {</div><div class='add'>+	u16	type;</div><div class='add'>+	u16	entry_size;</div><div class='add'>+	u32	flags;</div><div class='add'>+#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID</div><div class='add'>+	u32	instance_bmap;</div><div class='add'>+	u8	init_value;</div><div class='add'>+	u8	entry_multiple;</div><div class='add'>+	u16	init_offset;</div><div class='add'>+#define	BNXT_CTX_INIT_INVALID_OFFSET	0xffff</div><div class='add'>+	u32	max_entries;</div><div class='add'>+	u32	min_entries;</div><div class='add'>+	u8	last:1;</div><div class='add'>+	u8	split_entry_cnt;</div><div class='add'>+#define BNXT_MAX_SPLIT_ENTRY	4</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			u32	qp_l2_entries;</div><div class='add'>+			u32	qp_qp1_entries;</div><div class='add'>+			u32	qp_fast_qpmd_entries;</div><div class='add'>+		};</div><div class='add'>+		u32	srq_l2_entries;</div><div class='add'>+		u32	cq_l2_entries;</div><div class='add'>+		u32	vnic_entries;</div><div class='add'>+		struct {</div><div class='add'>+			u32	mrav_av_entries;</div><div class='add'>+			u32	mrav_num_entries_units;</div><div class='add'>+		};</div><div class='add'>+		u32	split[BNXT_MAX_SPLIT_ENTRY];</div><div class='add'>+	};</div><div class='add'>+	struct bnxt_ctx_pg_info	*pg_info;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY	0</div><div class='add'>+</div><div class='add'>+#define BNXT_CTX_QP	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP</div><div class='add'>+#define BNXT_CTX_SRQ	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ</div><div class='add'>+#define BNXT_CTX_CQ	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ</div><div class='add'>+#define BNXT_CTX_VNIC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC</div><div class='add'>+#define BNXT_CTX_STAT	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT</div><div class='add'>+#define BNXT_CTX_STQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING</div><div class='add'>+#define BNXT_CTX_FTQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING</div><div class='add'>+#define BNXT_CTX_MRAV	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV</div><div class='add'>+#define BNXT_CTX_TIM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM</div><div class='add'>+#define BNXT_CTX_TKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC</div><div class='add'>+#define BNXT_CTX_RKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC</div><div class='add'>+#define BNXT_CTX_MTQM	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING</div><div class='add'>+#define BNXT_CTX_SQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW</div><div class='add'>+#define BNXT_CTX_RQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW</div><div class='add'>+#define BNXT_CTX_SRQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW</div><div class='add'>+#define BNXT_CTX_CQDBS	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW</div><div class='add'>+#define BNXT_CTX_QTKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC</div><div class='add'>+#define BNXT_CTX_QRKC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC</div><div class='add'>+#define BNXT_CTX_TBLSC	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE</div><div class='add'>+#define BNXT_CTX_XPAR	FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION</div><div class='add'>+</div><div class='add'>+#define BNXT_CTX_MAX	(BNXT_CTX_TIM + 1)</div><div class='add'>+#define BNXT_CTX_L2_MAX	(BNXT_CTX_FTQM + 1)</div><div class='add'>+#define BNXT_CTX_V2_MAX	(BNXT_CTX_XPAR + 1)</div><div class='add'>+#define BNXT_CTX_INV	((u16)-1)</div><div class='add'>+</div><div class='ctx'> struct bnxt_ctx_mem_info {</div><div class='del'>-	u32	qp_max_entries;</div><div class='del'>-	u16	qp_min_qp1_entries;</div><div class='del'>-	u16	qp_max_l2_entries;</div><div class='del'>-	u16	qp_entry_size;</div><div class='del'>-	u16	srq_max_l2_entries;</div><div class='del'>-	u32	srq_max_entries;</div><div class='del'>-	u16	srq_entry_size;</div><div class='del'>-	u16	cq_max_l2_entries;</div><div class='del'>-	u32	cq_max_entries;</div><div class='del'>-	u16	cq_entry_size;</div><div class='del'>-	u16	vnic_max_vnic_entries;</div><div class='del'>-	u16	vnic_max_ring_table_entries;</div><div class='del'>-	u16	vnic_entry_size;</div><div class='del'>-	u32	stat_max_entries;</div><div class='del'>-	u16	stat_entry_size;</div><div class='del'>-	u16	tqm_entry_size;</div><div class='del'>-	u32	tqm_min_entries_per_ring;</div><div class='del'>-	u32	tqm_max_entries_per_ring;</div><div class='del'>-	u32	mrav_max_entries;</div><div class='del'>-	u16	mrav_entry_size;</div><div class='del'>-	u16	tim_entry_size;</div><div class='del'>-	u32	tim_max_entries;</div><div class='del'>-	u16	mrav_num_entries_units;</div><div class='del'>-	u8	tqm_entries_multiple;</div><div class='ctx'> 	u8	tqm_fp_rings_count;</div><div class='ctx'> </div><div class='ctx'> 	u32	flags;</div><div class='ctx'> 	#define BNXT_CTX_FLAG_INITED	0x01</div><div class='del'>-</div><div class='del'>-	struct bnxt_ctx_pg_info qp_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info srq_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info cq_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info vnic_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info stat_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info mrav_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info tim_mem;</div><div class='del'>-	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];</div><div class='del'>-</div><div class='del'>-#define BNXT_CTX_MEM_INIT_QP	0</div><div class='del'>-#define BNXT_CTX_MEM_INIT_SRQ	1</div><div class='del'>-#define BNXT_CTX_MEM_INIT_CQ	2</div><div class='del'>-#define BNXT_CTX_MEM_INIT_VNIC	3</div><div class='del'>-#define BNXT_CTX_MEM_INIT_STAT	4</div><div class='del'>-#define BNXT_CTX_MEM_INIT_MRAV	5</div><div class='del'>-#define BNXT_CTX_MEM_INIT_MAX	6</div><div class='del'>-	struct bnxt_mem_init	mem_init[BNXT_CTX_MEM_INIT_MAX];</div><div class='add'>+	struct bnxt_ctx_mem_type	ctx_arr[BNXT_CTX_V2_MAX];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum bnxt_health_severity {</div><div class='hunk'>@@ -1691,6 +1964,10 @@ enum board_idx {</div><div class='ctx'> 	BCM57508_NPAR,</div><div class='ctx'> 	BCM57504_NPAR,</div><div class='ctx'> 	BCM57502_NPAR,</div><div class='add'>+	BCM57608,</div><div class='add'>+	BCM57604,</div><div class='add'>+	BCM57602,</div><div class='add'>+	BCM57601,</div><div class='ctx'> 	BCM58802,</div><div class='ctx'> 	BCM58804,</div><div class='ctx'> 	BCM58808,</div><div class='hunk'>@@ -1738,14 +2015,14 @@ struct bnxt {</div><div class='ctx'> #define CHIP_NUM_57504		0x1751</div><div class='ctx'> #define CHIP_NUM_57502		0x1752</div><div class='ctx'> </div><div class='add'>+#define CHIP_NUM_57608		0x1760</div><div class='add'>+</div><div class='ctx'> #define CHIP_NUM_58802		0xd802</div><div class='ctx'> #define CHIP_NUM_58804		0xd804</div><div class='ctx'> #define CHIP_NUM_58808		0xd808</div><div class='ctx'> </div><div class='ctx'> 	u8			chip_rev;</div><div class='ctx'> </div><div class='del'>-#define CHIP_NUM_58818		0xd818</div><div class='del'>-</div><div class='ctx'> #define BNXT_CHIP_NUM_5730X(chip_num)		\</div><div class='ctx'> 	((chip_num) &gt;= CHIP_NUM_57301 &amp;&amp;	\</div><div class='ctx'> 	 (chip_num) &lt;= CHIP_NUM_57304)</div><div class='hunk'>@@ -1795,7 +2072,7 @@ struct bnxt {</div><div class='ctx'> 	atomic_t		intr_sem;</div><div class='ctx'> </div><div class='ctx'> 	u32			flags;</div><div class='del'>-	#define BNXT_FLAG_CHIP_P5	0x1</div><div class='add'>+	#define BNXT_FLAG_CHIP_P5_PLUS	0x1</div><div class='ctx'> 	#define BNXT_FLAG_VF		0x2</div><div class='ctx'> 	#define BNXT_FLAG_LRO		0x4</div><div class='ctx'> #ifdef CONFIG_INET</div><div class='hunk'>@@ -1814,8 +2091,6 @@ struct bnxt {</div><div class='ctx'> 	#define BNXT_FLAG_RFS		0x100</div><div class='ctx'> 	#define BNXT_FLAG_SHARED_RINGS	0x200</div><div class='ctx'> 	#define BNXT_FLAG_PORT_STATS	0x400</div><div class='del'>-	#define BNXT_FLAG_UDP_RSS_CAP	0x800</div><div class='del'>-	#define BNXT_FLAG_NEW_RSS_CAP	0x2000</div><div class='ctx'> 	#define BNXT_FLAG_WOL_CAP	0x4000</div><div class='ctx'> 	#define BNXT_FLAG_ROCEV1_CAP	0x8000</div><div class='ctx'> 	#define BNXT_FLAG_ROCEV2_CAP	0x10000</div><div class='hunk'>@@ -1823,13 +2098,15 @@ struct bnxt {</div><div class='ctx'> 					 BNXT_FLAG_ROCEV2_CAP)</div><div class='ctx'> 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000</div><div class='ctx'> 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000</div><div class='del'>-	#define BNXT_FLAG_CHIP_SR2	0x80000</div><div class='add'>+	#define BNXT_FLAG_CHIP_P7	0x80000</div><div class='ctx'> 	#define BNXT_FLAG_MULTI_HOST	0x100000</div><div class='ctx'> 	#define BNXT_FLAG_DSN_VALID	0x200000</div><div class='ctx'> 	#define BNXT_FLAG_DOUBLE_DB	0x400000</div><div class='add'>+	#define BNXT_FLAG_UDP_GSO_CAP	0x800000</div><div class='ctx'> 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000</div><div class='ctx'> 	#define BNXT_FLAG_DIM		0x2000000</div><div class='ctx'> 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000</div><div class='add'>+	#define BNXT_FLAG_TX_COAL_CMPL	0x8000000</div><div class='ctx'> 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000</div><div class='ctx'> </div><div class='ctx'> 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\</div><div class='hunk'>@@ -1849,21 +2126,21 @@ struct bnxt {</div><div class='ctx'> #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)-&gt;flags &amp; BNXT_FLAG_CHIP_NITRO_A0)</div><div class='ctx'> #define BNXT_RX_PAGE_MODE(bp)	((bp)-&gt;flags &amp; BNXT_FLAG_RX_PAGE_MODE)</div><div class='ctx'> #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &amp;&amp;	\</div><div class='del'>-				 (!((bp)-&gt;flags &amp; BNXT_FLAG_CHIP_P5) ||	\</div><div class='add'>+				 (!((bp)-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) ||\</div><div class='ctx'> 				  (bp)-&gt;max_tpa_v2) &amp;&amp; !is_kdump_kernel())</div><div class='ctx'> #define BNXT_RX_JUMBO_MODE(bp)	((bp)-&gt;flags &amp; BNXT_FLAG_JUMBO)</div><div class='ctx'> </div><div class='del'>-#define BNXT_CHIP_SR2(bp)			\</div><div class='del'>-	((bp)-&gt;chip_num == CHIP_NUM_58818)</div><div class='add'>+#define BNXT_CHIP_P7(bp)			\</div><div class='add'>+	((bp)-&gt;chip_num == CHIP_NUM_57608)</div><div class='ctx'> </div><div class='del'>-#define BNXT_CHIP_P5_THOR(bp)			\</div><div class='add'>+#define BNXT_CHIP_P5(bp)			\</div><div class='ctx'> 	((bp)-&gt;chip_num == CHIP_NUM_57508 ||	\</div><div class='ctx'> 	 (bp)-&gt;chip_num == CHIP_NUM_57504 ||	\</div><div class='ctx'> 	 (bp)-&gt;chip_num == CHIP_NUM_57502)</div><div class='ctx'> </div><div class='ctx'> /* Chip class phase 5 */</div><div class='del'>-#define BNXT_CHIP_P5(bp)			\</div><div class='del'>-	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))</div><div class='add'>+#define BNXT_CHIP_P5_PLUS(bp)			\</div><div class='add'>+	(BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))</div><div class='ctx'> </div><div class='ctx'> /* Chip class phase 4.x */</div><div class='ctx'> #define BNXT_CHIP_P4(bp)			\</div><div class='hunk'>@@ -1874,7 +2151,7 @@ struct bnxt {</div><div class='ctx'> 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))</div><div class='ctx'> </div><div class='ctx'> #define BNXT_CHIP_P4_PLUS(bp)			\</div><div class='del'>-	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))</div><div class='add'>+	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))</div><div class='ctx'> </div><div class='ctx'> 	struct bnxt_aux_priv	*aux_priv;</div><div class='ctx'> 	struct bnxt_en_dev	*edev;</div><div class='hunk'>@@ -1935,6 +2212,11 @@ struct bnxt {</div><div class='ctx'> 	u16			rss_indir_tbl_entries;</div><div class='ctx'> 	u32			rss_hash_cfg;</div><div class='ctx'> 	u32			rss_hash_delta;</div><div class='add'>+	u32			rss_cap;</div><div class='add'>+#define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA	BIT(0)</div><div class='add'>+#define BNXT_RSS_CAP_UDP_RSS_CAP		BIT(1)</div><div class='add'>+#define BNXT_RSS_CAP_NEW_RSS_CAP		BIT(2)</div><div class='add'>+#define BNXT_RSS_CAP_RSS_TCAM			BIT(3)</div><div class='ctx'> </div><div class='ctx'> 	u16			max_mtu;</div><div class='ctx'> 	u8			max_tc;</div><div class='hunk'>@@ -2000,7 +2282,6 @@ struct bnxt {</div><div class='ctx'> 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	BIT_ULL(16)</div><div class='ctx'> 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	BIT_ULL(17)</div><div class='ctx'> 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		BIT_ULL(18)</div><div class='del'>-	#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA		BIT_ULL(19)</div><div class='ctx'> 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		BIT_ULL(20)</div><div class='ctx'> 	#define BNXT_FW_CAP_HOT_RESET			BIT_ULL(21)</div><div class='ctx'> 	#define BNXT_FW_CAP_PTP_RTC			BIT_ULL(22)</div><div class='hunk'>@@ -2017,6 +2298,8 @@ struct bnxt {</div><div class='ctx'> 	#define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED	BIT_ULL(33)</div><div class='ctx'> 	#define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP		BIT_ULL(34)</div><div class='ctx'> 	#define BNXT_FW_CAP_PRE_RESV_VNICS		BIT_ULL(35)</div><div class='add'>+	#define BNXT_FW_CAP_BACKING_STORE_V2		BIT_ULL(36)</div><div class='add'>+	#define BNXT_FW_CAP_VNIC_TUNNEL_TPA		BIT_ULL(37)</div><div class='ctx'> </div><div class='ctx'> 	u32			fw_dbg_cap;</div><div class='ctx'> </div><div class='hunk'>@@ -2061,8 +2344,10 @@ struct bnxt {</div><div class='ctx'> </div><div class='ctx'> 	u16			vxlan_fw_dst_port_id;</div><div class='ctx'> 	u16			nge_fw_dst_port_id;</div><div class='add'>+	u16			vxlan_gpe_fw_dst_port_id;</div><div class='ctx'> 	__be16			vxlan_port;</div><div class='ctx'> 	__be16			nge_port;</div><div class='add'>+	__be16			vxlan_gpe_port;</div><div class='ctx'> 	u8			port_partition_type;</div><div class='ctx'> 	u8			port_count;</div><div class='ctx'> 	u16			br_mode;</div><div class='hunk'>@@ -2130,9 +2415,11 @@ struct bnxt {</div><div class='ctx'> 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */</div><div class='ctx'> 	spinlock_t		db_lock;</div><div class='ctx'> #endif</div><div class='add'>+	int			db_offset;	/* db_offset within db_size */</div><div class='ctx'> 	int			db_size;</div><div class='ctx'> </div><div class='ctx'> #define BNXT_NTP_FLTR_MAX_FLTR	4096</div><div class='add'>+#define BNXT_MAX_FLTR		(BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)</div><div class='ctx'> #define BNXT_NTP_FLTR_HASH_SIZE	512</div><div class='ctx'> #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)</div><div class='ctx'> 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];</div><div class='hunk'>@@ -2141,6 +2428,14 @@ struct bnxt {</div><div class='ctx'> 	unsigned long		*ntp_fltr_bmap;</div><div class='ctx'> 	int			ntp_fltr_count;</div><div class='ctx'> </div><div class='add'>+#define BNXT_L2_FLTR_MAX_FLTR	1024</div><div class='add'>+#define BNXT_L2_FLTR_HASH_SIZE	32</div><div class='add'>+#define BNXT_L2_FLTR_HASH_MASK	(BNXT_L2_FLTR_HASH_SIZE - 1)</div><div class='add'>+	struct hlist_head	l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];</div><div class='add'>+</div><div class='add'>+	u32			hash_seed;</div><div class='add'>+	u64			toeplitz_prefix;</div><div class='add'>+</div><div class='ctx'> 	/* To protect link related settings during link changes and</div><div class='ctx'> 	 * ethtool settings changes.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -2163,6 +2458,7 @@ struct bnxt {</div><div class='ctx'> #define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED &lt;&lt; 8)</div><div class='ctx'> #define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED &lt;&lt; 8)</div><div class='ctx'> #define BNXT_PHY_FL_BANK_SEL		(PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED &lt;&lt; 8)</div><div class='add'>+#define BNXT_PHY_FL_SPEEDS2		(PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED &lt;&lt; 8)</div><div class='ctx'> </div><div class='ctx'> 	u8			num_tests;</div><div class='ctx'> 	struct bnxt_test_info	*test_info;</div><div class='hunk'>@@ -2206,15 +2502,15 @@ struct bnxt {</div><div class='ctx'> #define BNXT_NUM_TX_RING_STATS			8</div><div class='ctx'> #define BNXT_NUM_TPA_RING_STATS			4</div><div class='ctx'> #define BNXT_NUM_TPA_RING_STATS_P5		5</div><div class='del'>-#define BNXT_NUM_TPA_RING_STATS_P5_SR2		6</div><div class='add'>+#define BNXT_NUM_TPA_RING_STATS_P7		6</div><div class='ctx'> </div><div class='ctx'> #define BNXT_RING_STATS_SIZE_P5					\</div><div class='ctx'> 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\</div><div class='ctx'> 	  BNXT_NUM_TPA_RING_STATS_P5) * 8)</div><div class='ctx'> </div><div class='del'>-#define BNXT_RING_STATS_SIZE_P5_SR2				\</div><div class='add'>+#define BNXT_RING_STATS_SIZE_P7					\</div><div class='ctx'> 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\</div><div class='del'>-	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)</div><div class='add'>+	  BNXT_NUM_TPA_RING_STATS_P7) * 8)</div><div class='ctx'> </div><div class='ctx'> #define BNXT_GET_RING_STATS64(sw, counter)		\</div><div class='ctx'> 	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))</div><div class='hunk'>@@ -2297,10 +2593,11 @@ static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,</div><div class='ctx'> static inline void bnxt_db_write_relaxed(struct bnxt *bp,</div><div class='ctx'> 					 struct bnxt_db_info *db, u32 idx)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		bnxt_writeq_relaxed(bp, db-&gt;db_key64 | idx, db-&gt;doorbell);</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='add'>+		bnxt_writeq_relaxed(bp, db-&gt;db_key64 | DB_RING_IDX(db, idx),</div><div class='add'>+				    db-&gt;doorbell);</div><div class='ctx'> 	} else {</div><div class='del'>-		u32 db_val = db-&gt;db_key32 | idx;</div><div class='add'>+		u32 db_val = db-&gt;db_key32 | DB_RING_IDX(db, idx);</div><div class='ctx'> </div><div class='ctx'> 		writel_relaxed(db_val, db-&gt;doorbell);</div><div class='ctx'> 		if (bp-&gt;flags &amp; BNXT_FLAG_DOUBLE_DB)</div><div class='hunk'>@@ -2312,10 +2609,11 @@ static inline void bnxt_db_write_relaxed(struct bnxt *bp,</div><div class='ctx'> static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,</div><div class='ctx'> 				 u32 idx)</div><div class='ctx'> {</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-		bnxt_writeq(bp, db-&gt;db_key64 | idx, db-&gt;doorbell);</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='add'>+		bnxt_writeq(bp, db-&gt;db_key64 | DB_RING_IDX(db, idx),</div><div class='add'>+			    db-&gt;doorbell);</div><div class='ctx'> 	} else {</div><div class='del'>-		u32 db_val = db-&gt;db_key32 | idx;</div><div class='add'>+		u32 db_val = db-&gt;db_key32 | DB_RING_IDX(db, idx);</div><div class='ctx'> </div><div class='ctx'> 		writel(db_val, db-&gt;doorbell);</div><div class='ctx'> 		if (bp-&gt;flags &amp; BNXT_FLAG_DOUBLE_DB)</div><div class='hunk'>@@ -2345,12 +2643,21 @@ int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);</div><div class='ctx'> int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,</div><div class='ctx'> 			    int bmap_size, bool async_only);</div><div class='ctx'> int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);</div><div class='add'>+void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);</div><div class='add'>+int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);</div><div class='add'>+int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);</div><div class='add'>+int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,</div><div class='add'>+				     struct bnxt_ntuple_filter *fltr);</div><div class='add'>+int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,</div><div class='add'>+				      struct bnxt_ntuple_filter *fltr);</div><div class='add'>+void bnxt_fill_ipv6_mask(__be32 mask[4]);</div><div class='ctx'> int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);</div><div class='ctx'> int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);</div><div class='ctx'> int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);</div><div class='ctx'> int bnxt_nq_rings_in_use(struct bnxt *bp);</div><div class='ctx'> int bnxt_hwrm_set_coal(struct bnxt *);</div><div class='ctx'> void bnxt_free_ctx_mem(struct bnxt *bp);</div><div class='add'>+int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);</div><div class='ctx'> unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);</div><div class='ctx'> unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);</div><div class='ctx'> unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);</div><div class='hunk'>@@ -2360,7 +2667,7 @@ int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);</div><div class='ctx'> void bnxt_tx_disable(struct bnxt *bp);</div><div class='ctx'> void bnxt_tx_enable(struct bnxt *bp);</div><div class='ctx'> void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,</div><div class='del'>-			  int idx);</div><div class='add'>+			  u16 curr);</div><div class='ctx'> void bnxt_report_link(struct bnxt *bp);</div><div class='ctx'> int bnxt_update_link(struct bnxt *bp, bool chng_link_state);</div><div class='ctx'> int bnxt_hwrm_set_pause(struct bnxt *);</div><div class='hunk'>@@ -2375,7 +2682,7 @@ int bnxt_open_nic(struct bnxt *, bool, bool);</div><div class='ctx'> int bnxt_half_open_nic(struct bnxt *bp);</div><div class='ctx'> void bnxt_half_close_nic(struct bnxt *bp);</div><div class='ctx'> void bnxt_reenable_sriov(struct bnxt *bp);</div><div class='del'>-int bnxt_close_nic(struct bnxt *, bool, bool);</div><div class='add'>+void bnxt_close_nic(struct bnxt *, bool, bool);</div><div class='ctx'> void bnxt_get_ring_err_stats(struct bnxt *bp,</div><div class='ctx'> 			     struct bnxt_total_ring_err_stats *stats);</div><div class='ctx'> int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,</div><div class='hunk'>@@ -2387,6 +2694,13 @@ int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,</div><div class='ctx'> int bnxt_fw_init_one(struct bnxt *bp);</div><div class='ctx'> bool bnxt_hwrm_reset_permitted(struct bnxt *bp);</div><div class='ctx'> int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);</div><div class='add'>+struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,</div><div class='add'>+				struct bnxt_ntuple_filter *fltr, u32 idx);</div><div class='add'>+u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,</div><div class='add'>+			    const struct sk_buff *skb);</div><div class='add'>+int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,</div><div class='add'>+			   u32 idx);</div><div class='add'>+void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);</div><div class='ctx'> int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);</div><div class='ctx'> int bnxt_restore_pf_fw_resources(struct bnxt *bp);</div><div class='ctx'> int bnxt_get_port_parent_id(struct net_device *dev,</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c<br/>index f302dac56599..ae4529c043f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c</a></div><div class='hunk'>@@ -449,15 +449,8 @@ static int bnxt_dl_reload_down(struct devlink *dl, bool netns_change,</div><div class='ctx'> 			return -ENODEV;</div><div class='ctx'> 		}</div><div class='ctx'> 		bnxt_ulp_stop(bp);</div><div class='del'>-		if (netif_running(bp-&gt;dev)) {</div><div class='del'>-			rc = bnxt_close_nic(bp, true, true);</div><div class='del'>-			if (rc) {</div><div class='del'>-				NL_SET_ERR_MSG_MOD(extack, "Failed to close");</div><div class='del'>-				dev_close(bp-&gt;dev);</div><div class='del'>-				rtnl_unlock();</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='add'>+		if (netif_running(bp-&gt;dev))</div><div class='add'>+			bnxt_close_nic(bp, true, true);</div><div class='ctx'> 		bnxt_vf_reps_free(bp);</div><div class='ctx'> 		rc = bnxt_hwrm_func_drv_unrgtr(bp);</div><div class='ctx'> 		if (rc) {</div><div class='hunk'>@@ -469,8 +462,6 @@ static int bnxt_dl_reload_down(struct devlink *dl, bool netns_change,</div><div class='ctx'> 		}</div><div class='ctx'> 		bnxt_cancel_reservations(bp, false);</div><div class='ctx'> 		bnxt_free_ctx_mem(bp);</div><div class='del'>-		kfree(bp-&gt;ctx);</div><div class='del'>-		bp-&gt;ctx = NULL;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	case DEVLINK_RELOAD_ACTION_FW_ACTIVATE: {</div><div class='hunk'>@@ -741,7 +732,7 @@ static int bnxt_hwrm_get_nvm_cfg_ver(struct bnxt *bp, u32 *nvm_cfg_ver)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* earlier devices present as an array of raw bytes */</div><div class='del'>-	if (!BNXT_CHIP_P5(bp)) {</div><div class='add'>+	if (!BNXT_CHIP_P5_PLUS(bp)) {</div><div class='ctx'> 		dim = 0;</div><div class='ctx'> 		i = 0;</div><div class='ctx'> 		bits *= 3;  /* array of 3 version components */</div><div class='hunk'>@@ -761,7 +752,7 @@ static int bnxt_hwrm_get_nvm_cfg_ver(struct bnxt *bp, u32 *nvm_cfg_ver)</div><div class='ctx'> 			goto exit;</div><div class='ctx'> 		bnxt_copy_from_nvm_data(&amp;ver, data, bits, bytes);</div><div class='ctx'> </div><div class='del'>-		if (BNXT_CHIP_P5(bp)) {</div><div class='add'>+		if (BNXT_CHIP_P5_PLUS(bp)) {</div><div class='ctx'> 			*nvm_cfg_ver &lt;&lt;= 8;</div><div class='ctx'> 			*nvm_cfg_ver |= ver.vu8;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -781,7 +772,7 @@ static int bnxt_dl_info_put(struct bnxt *bp, struct devlink_info_req *req,</div><div class='ctx'> 	if (!strlen(buf))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) &amp;&amp;</div><div class='add'>+	if ((bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) &amp;&amp;</div><div class='ctx'> 	    (!strcmp(key, DEVLINK_INFO_VERSION_GENERIC_FW_NCSI) ||</div><div class='ctx'> 	     !strcmp(key, DEVLINK_INFO_VERSION_GENERIC_FW_ROCE)))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1007,7 +998,7 @@ static int bnxt_dl_info_get(struct devlink *dl, struct devlink_info_req *req,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	if (BNXT_CHIP_P5(bp)) {</div><div class='add'>+	if (BNXT_CHIP_P5_PLUS(bp)) {</div><div class='ctx'> 		rc = bnxt_dl_livepatch_info_put(bp, req, BNXT_FW_SRT_PATCH);</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			return rc;</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c<br/>index f3f384773ac0..27b983c0a8a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c</a></div><div class='hunk'>@@ -165,9 +165,8 @@ static int bnxt_set_coalesce(struct net_device *dev,</div><div class='ctx'> reset_coalesce:</div><div class='ctx'> 	if (test_bit(BNXT_STATE_OPEN, &amp;bp-&gt;state)) {</div><div class='ctx'> 		if (update_stats) {</div><div class='del'>-			rc = bnxt_close_nic(bp, true, false);</div><div class='del'>-			if (!rc)</div><div class='del'>-				rc = bnxt_open_nic(bp, true, false);</div><div class='add'>+			bnxt_close_nic(bp, true, false);</div><div class='add'>+			rc = bnxt_open_nic(bp, true, false);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			rc = bnxt_hwrm_set_coal(bp);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -461,6 +460,7 @@ static const struct {</div><div class='ctx'> 	BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,</div><div class='ctx'> 	BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),</div><div class='ctx'> 	BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),</div><div class='add'>+	BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct {</div><div class='hunk'>@@ -511,9 +511,9 @@ static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	if (BNXT_SUPPORTS_TPA(bp)) {</div><div class='ctx'> 		if (bp-&gt;max_tpa_v2) {</div><div class='del'>-			if (BNXT_CHIP_P5_THOR(bp))</div><div class='add'>+			if (BNXT_CHIP_P5(bp))</div><div class='ctx'> 				return BNXT_NUM_TPA_RING_STATS_P5;</div><div class='del'>-			return BNXT_NUM_TPA_RING_STATS_P5_SR2;</div><div class='add'>+			return BNXT_NUM_TPA_RING_STATS_P7;</div><div class='ctx'> 		}</div><div class='ctx'> 		return BNXT_NUM_TPA_RING_STATS;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -528,7 +528,8 @@ static int bnxt_get_num_ring_stats(struct bnxt *bp)</div><div class='ctx'> 	     bnxt_get_num_tpa_ring_stats(bp);</div><div class='ctx'> 	tx = NUM_RING_TX_HW_STATS;</div><div class='ctx'> 	cmn = NUM_RING_CMN_SW_STATS;</div><div class='del'>-	return rx * bp-&gt;rx_nr_rings + tx * bp-&gt;tx_nr_rings +</div><div class='add'>+	return rx * bp-&gt;rx_nr_rings +</div><div class='add'>+	       tx * (bp-&gt;tx_nr_rings_xdp + bp-&gt;tx_nr_rings_per_tc) +</div><div class='ctx'> 	       cmn * bp-&gt;cp_nr_rings;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -923,6 +924,7 @@ static int bnxt_set_channels(struct net_device *dev,</div><div class='ctx'> 	bool sh = false;</div><div class='ctx'> 	int tx_xdp = 0;</div><div class='ctx'> 	int rc = 0;</div><div class='add'>+	int tx_cp;</div><div class='ctx'> </div><div class='ctx'> 	if (channel-&gt;other_count)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -972,12 +974,7 @@ static int bnxt_set_channels(struct net_device *dev,</div><div class='ctx'> 			 * before PF unload</div><div class='ctx'> 			 */</div><div class='ctx'> 		}</div><div class='del'>-		rc = bnxt_close_nic(bp, true, false);</div><div class='del'>-		if (rc) {</div><div class='del'>-			netdev_err(bp-&gt;dev, "Set channel failure rc :%x\n",</div><div class='del'>-				   rc);</div><div class='del'>-			return rc;</div><div class='del'>-		}</div><div class='add'>+		bnxt_close_nic(bp, true, false);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (sh) {</div><div class='hunk'>@@ -994,8 +991,9 @@ static int bnxt_set_channels(struct net_device *dev,</div><div class='ctx'> 	if (tcs &gt; 1)</div><div class='ctx'> 		bp-&gt;tx_nr_rings = bp-&gt;tx_nr_rings_per_tc * tcs + tx_xdp;</div><div class='ctx'> </div><div class='del'>-	bp-&gt;cp_nr_rings = sh ? max_t(int, bp-&gt;tx_nr_rings, bp-&gt;rx_nr_rings) :</div><div class='del'>-			       bp-&gt;tx_nr_rings + bp-&gt;rx_nr_rings;</div><div class='add'>+	tx_cp = bnxt_num_tx_to_cp(bp, bp-&gt;tx_nr_rings);</div><div class='add'>+	bp-&gt;cp_nr_rings = sh ? max_t(int, tx_cp, bp-&gt;rx_nr_rings) :</div><div class='add'>+			       tx_cp + bp-&gt;rx_nr_rings;</div><div class='ctx'> </div><div class='ctx'> 	/* After changing number of rx channels, update NTUPLE feature. */</div><div class='ctx'> 	netdev_update_features(dev);</div><div class='hunk'>@@ -1013,29 +1011,60 @@ static int bnxt_set_channels(struct net_device *dev,</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='del'>-static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,</div><div class='del'>-			    u32 *rule_locs)</div><div class='add'>+static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],</div><div class='add'>+				     int tbl_size, u32 *ids, u32 start,</div><div class='add'>+				     u32 id_cnt)</div><div class='ctx'> {</div><div class='del'>-	int i, j = 0;</div><div class='add'>+	int i, j = start;</div><div class='ctx'> </div><div class='del'>-	cmd-&gt;data = bp-&gt;ntp_fltr_count;</div><div class='del'>-	for (i = 0; i &lt; BNXT_NTP_FLTR_HASH_SIZE; i++) {</div><div class='add'>+	if (j &gt;= id_cnt)</div><div class='add'>+		return j;</div><div class='add'>+	for (i = 0; i &lt; tbl_size; i++) {</div><div class='ctx'> 		struct hlist_head *head;</div><div class='del'>-		struct bnxt_ntuple_filter *fltr;</div><div class='add'>+		struct bnxt_filter_base *fltr;</div><div class='ctx'> </div><div class='del'>-		head = &amp;bp-&gt;ntp_fltr_hash_tbl[i];</div><div class='del'>-		rcu_read_lock();</div><div class='add'>+		head = &amp;tbl[i];</div><div class='ctx'> 		hlist_for_each_entry_rcu(fltr, head, hash) {</div><div class='del'>-			if (j == cmd-&gt;rule_cnt)</div><div class='del'>-				break;</div><div class='del'>-			rule_locs[j++] = fltr-&gt;sw_id;</div><div class='add'>+			if (!fltr-&gt;flags ||</div><div class='add'>+			    test_bit(BNXT_FLTR_FW_DELETED, &amp;fltr-&gt;state))</div><div class='add'>+				continue;</div><div class='add'>+			ids[j++] = fltr-&gt;sw_id;</div><div class='add'>+			if (j == id_cnt)</div><div class='add'>+				return j;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return j;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,</div><div class='add'>+						      struct hlist_head tbl[],</div><div class='add'>+						      int tbl_size, u32 id)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; tbl_size; i++) {</div><div class='add'>+		struct hlist_head *head;</div><div class='add'>+		struct bnxt_filter_base *fltr;</div><div class='add'>+</div><div class='add'>+		head = &amp;tbl[i];</div><div class='add'>+		hlist_for_each_entry_rcu(fltr, head, hash) {</div><div class='add'>+			if (fltr-&gt;flags &amp;&amp; fltr-&gt;sw_id == id)</div><div class='add'>+				return fltr;</div><div class='ctx'> 		}</div><div class='del'>-		rcu_read_unlock();</div><div class='del'>-		if (j == cmd-&gt;rule_cnt)</div><div class='del'>-			break;</div><div class='ctx'> 	}</div><div class='del'>-	cmd-&gt;rule_cnt = j;</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,</div><div class='add'>+			    u32 *rule_locs)</div><div class='add'>+{</div><div class='add'>+	cmd-&gt;data = bp-&gt;ntp_fltr_count;</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	cmd-&gt;rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp-&gt;ntp_fltr_hash_tbl,</div><div class='add'>+						  BNXT_NTP_FLTR_HASH_SIZE,</div><div class='add'>+						  rule_locs, 0, cmd-&gt;rule_cnt);</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1043,27 +1072,24 @@ static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='ctx'> {</div><div class='ctx'> 	struct ethtool_rx_flow_spec *fs =</div><div class='ctx'> 		(struct ethtool_rx_flow_spec *)&amp;cmd-&gt;fs;</div><div class='add'>+	struct bnxt_filter_base *fltr_base;</div><div class='ctx'> 	struct bnxt_ntuple_filter *fltr;</div><div class='ctx'> 	struct flow_keys *fkeys;</div><div class='del'>-	int i, rc = -EINVAL;</div><div class='add'>+	int rc = -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (fs-&gt;location &gt;= BNXT_NTP_FLTR_MAX_FLTR)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; BNXT_NTP_FLTR_HASH_SIZE; i++) {</div><div class='del'>-		struct hlist_head *head;</div><div class='del'>-</div><div class='del'>-		head = &amp;bp-&gt;ntp_fltr_hash_tbl[i];</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		hlist_for_each_entry_rcu(fltr, head, hash) {</div><div class='del'>-			if (fltr-&gt;sw_id == fs-&gt;location)</div><div class='del'>-				goto fltr_found;</div><div class='del'>-		}</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	fltr_base = bnxt_get_one_fltr_rcu(bp, bp-&gt;ntp_fltr_hash_tbl,</div><div class='add'>+					  BNXT_NTP_FLTR_HASH_SIZE,</div><div class='add'>+					  fs-&gt;location);</div><div class='add'>+	if (!fltr_base) {</div><div class='ctx'> 		rcu_read_unlock();</div><div class='add'>+		return rc;</div><div class='ctx'> 	}</div><div class='del'>-	return rc;</div><div class='add'>+	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);</div><div class='ctx'> </div><div class='del'>-fltr_found:</div><div class='ctx'> 	fkeys = &amp;fltr-&gt;fkeys;</div><div class='ctx'> 	if (fkeys-&gt;basic.n_proto == htons(ETH_P_IP)) {</div><div class='ctx'> 		if (fkeys-&gt;basic.ip_proto == IPPROTO_TCP)</div><div class='hunk'>@@ -1073,20 +1099,23 @@ fltr_found:</div><div class='ctx'> 		else</div><div class='ctx'> 			goto fltr_err;</div><div class='ctx'> </div><div class='del'>-		fs-&gt;h_u.tcp_ip4_spec.ip4src = fkeys-&gt;addrs.v4addrs.src;</div><div class='del'>-		fs-&gt;m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);</div><div class='del'>-</div><div class='del'>-		fs-&gt;h_u.tcp_ip4_spec.ip4dst = fkeys-&gt;addrs.v4addrs.dst;</div><div class='del'>-		fs-&gt;m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);</div><div class='del'>-</div><div class='del'>-		fs-&gt;h_u.tcp_ip4_spec.psrc = fkeys-&gt;ports.src;</div><div class='del'>-		fs-&gt;m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);</div><div class='del'>-</div><div class='del'>-		fs-&gt;h_u.tcp_ip4_spec.pdst = fkeys-&gt;ports.dst;</div><div class='del'>-		fs-&gt;m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip4_spec.ip4src = fkeys-&gt;addrs.v4addrs.src;</div><div class='add'>+			fs-&gt;m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip4_spec.ip4dst = fkeys-&gt;addrs.v4addrs.dst;</div><div class='add'>+			fs-&gt;m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_PORT) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip4_spec.psrc = fkeys-&gt;ports.src;</div><div class='add'>+			fs-&gt;m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_PORT) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip4_spec.pdst = fkeys-&gt;ports.dst;</div><div class='add'>+			fs-&gt;m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);</div><div class='add'>+		}</div><div class='ctx'> 	} else {</div><div class='del'>-		int i;</div><div class='del'>-</div><div class='ctx'> 		if (fkeys-&gt;basic.ip_proto == IPPROTO_TCP)</div><div class='ctx'> 			fs-&gt;flow_type = TCP_V6_FLOW;</div><div class='ctx'> 		else if (fkeys-&gt;basic.ip_proto == IPPROTO_UDP)</div><div class='hunk'>@@ -1094,22 +1123,27 @@ fltr_found:</div><div class='ctx'> 		else</div><div class='ctx'> 			goto fltr_err;</div><div class='ctx'> </div><div class='del'>-		*(struct in6_addr *)&amp;fs-&gt;h_u.tcp_ip6_spec.ip6src[0] =</div><div class='del'>-			fkeys-&gt;addrs.v6addrs.src;</div><div class='del'>-		*(struct in6_addr *)&amp;fs-&gt;h_u.tcp_ip6_spec.ip6dst[0] =</div><div class='del'>-			fkeys-&gt;addrs.v6addrs.dst;</div><div class='del'>-		for (i = 0; i &lt; 4; i++) {</div><div class='del'>-			fs-&gt;m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);</div><div class='del'>-			fs-&gt;m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_IP) {</div><div class='add'>+			*(struct in6_addr *)&amp;fs-&gt;h_u.tcp_ip6_spec.ip6src[0] =</div><div class='add'>+				fkeys-&gt;addrs.v6addrs.src;</div><div class='add'>+			bnxt_fill_ipv6_mask(fs-&gt;m_u.tcp_ip6_spec.ip6src);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_IP) {</div><div class='add'>+			*(struct in6_addr *)&amp;fs-&gt;h_u.tcp_ip6_spec.ip6dst[0] =</div><div class='add'>+				fkeys-&gt;addrs.v6addrs.dst;</div><div class='add'>+			bnxt_fill_ipv6_mask(fs-&gt;m_u.tcp_ip6_spec.ip6dst);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_SRC_PORT) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip6_spec.psrc = fkeys-&gt;ports.src;</div><div class='add'>+			fs-&gt;m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);</div><div class='add'>+		}</div><div class='add'>+		if (fltr-&gt;ntuple_flags &amp; BNXT_NTUPLE_MATCH_DST_PORT) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip6_spec.pdst = fkeys-&gt;ports.dst;</div><div class='add'>+			fs-&gt;m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);</div><div class='ctx'> 		}</div><div class='del'>-		fs-&gt;h_u.tcp_ip6_spec.psrc = fkeys-&gt;ports.src;</div><div class='del'>-		fs-&gt;m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);</div><div class='del'>-</div><div class='del'>-		fs-&gt;h_u.tcp_ip6_spec.pdst = fkeys-&gt;ports.dst;</div><div class='del'>-		fs-&gt;m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fs-&gt;ring_cookie = fltr-&gt;rxq;</div><div class='add'>+	fs-&gt;ring_cookie = fltr-&gt;base.rxq;</div><div class='ctx'> 	rc = 0;</div><div class='ctx'> </div><div class='ctx'> fltr_err:</div><div class='hunk'>@@ -1117,7 +1151,221 @@ fltr_err:</div><div class='ctx'> </div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='del'>-#endif</div><div class='add'>+</div><div class='add'>+#define IPV4_ALL_MASK		((__force __be32)~0)</div><div class='add'>+#define L4_PORT_ALL_MASK	((__force __be16)~0)</div><div class='add'>+</div><div class='add'>+static bool ipv6_mask_is_full(__be32 mask[4])</div><div class='add'>+{</div><div class='add'>+	return (mask[0] &amp; mask[1] &amp; mask[2] &amp; mask[3]) == IPV4_ALL_MASK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool ipv6_mask_is_zero(__be32 mask[4])</div><div class='add'>+{</div><div class='add'>+	return !(mask[0] | mask[1] | mask[2] | mask[3]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,</div><div class='add'>+				    struct ethtool_rx_flow_spec *fs)</div><div class='add'>+{</div><div class='add'>+	u8 vf = ethtool_get_flow_spec_ring_vf(fs-&gt;ring_cookie);</div><div class='add'>+	u32 ring = ethtool_get_flow_spec_ring(fs-&gt;ring_cookie);</div><div class='add'>+	struct bnxt_ntuple_filter *new_fltr, *fltr;</div><div class='add'>+	struct bnxt_l2_filter *l2_fltr;</div><div class='add'>+	u32 flow_type = fs-&gt;flow_type;</div><div class='add'>+	struct flow_keys *fkeys;</div><div class='add'>+	u32 idx;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;vnic_info)</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+</div><div class='add'>+	if ((flow_type &amp; (FLOW_MAC_EXT | FLOW_EXT)) || vf)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	new_fltr = kzalloc(sizeof(*new_fltr), GFP_KERNEL);</div><div class='add'>+	if (!new_fltr)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	l2_fltr = bp-&gt;vnic_info[0].l2_filters[0];</div><div class='add'>+	atomic_inc(&amp;l2_fltr-&gt;refcnt);</div><div class='add'>+	new_fltr-&gt;l2_fltr = l2_fltr;</div><div class='add'>+	fkeys = &amp;new_fltr-&gt;fkeys;</div><div class='add'>+</div><div class='add'>+	rc = -EOPNOTSUPP;</div><div class='add'>+	switch (flow_type) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW: {</div><div class='add'>+		struct ethtool_tcpip4_spec *ip_spec = &amp;fs-&gt;h_u.tcp_ip4_spec;</div><div class='add'>+		struct ethtool_tcpip4_spec *ip_mask = &amp;fs-&gt;m_u.tcp_ip4_spec;</div><div class='add'>+</div><div class='add'>+		fkeys-&gt;basic.ip_proto = IPPROTO_TCP;</div><div class='add'>+		if (flow_type == UDP_V4_FLOW)</div><div class='add'>+			fkeys-&gt;basic.ip_proto = IPPROTO_UDP;</div><div class='add'>+		fkeys-&gt;basic.n_proto = htons(ETH_P_IP);</div><div class='add'>+</div><div class='add'>+		if (ip_mask-&gt;ip4src == IPV4_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;addrs.v4addrs.src = ip_spec-&gt;ip4src;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP;</div><div class='add'>+		} else if (ip_mask-&gt;ip4src) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		if (ip_mask-&gt;ip4dst == IPV4_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;addrs.v4addrs.dst = ip_spec-&gt;ip4dst;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP;</div><div class='add'>+		} else if (ip_mask-&gt;ip4dst) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ip_mask-&gt;psrc == L4_PORT_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;ports.src = ip_spec-&gt;psrc;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT;</div><div class='add'>+		} else if (ip_mask-&gt;psrc) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		if (ip_mask-&gt;pdst == L4_PORT_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;ports.dst = ip_spec-&gt;pdst;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT;</div><div class='add'>+		} else if (ip_mask-&gt;pdst) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW: {</div><div class='add'>+		struct ethtool_tcpip6_spec *ip_spec = &amp;fs-&gt;h_u.tcp_ip6_spec;</div><div class='add'>+		struct ethtool_tcpip6_spec *ip_mask = &amp;fs-&gt;m_u.tcp_ip6_spec;</div><div class='add'>+</div><div class='add'>+		fkeys-&gt;basic.ip_proto = IPPROTO_TCP;</div><div class='add'>+		if (flow_type == UDP_V6_FLOW)</div><div class='add'>+			fkeys-&gt;basic.ip_proto = IPPROTO_UDP;</div><div class='add'>+		fkeys-&gt;basic.n_proto = htons(ETH_P_IPV6);</div><div class='add'>+</div><div class='add'>+		if (ipv6_mask_is_full(ip_mask-&gt;ip6src)) {</div><div class='add'>+			fkeys-&gt;addrs.v6addrs.src =</div><div class='add'>+				*(struct in6_addr *)&amp;ip_spec-&gt;ip6src;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_IP;</div><div class='add'>+		} else if (!ipv6_mask_is_zero(ip_mask-&gt;ip6src)) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		if (ipv6_mask_is_full(ip_mask-&gt;ip6dst)) {</div><div class='add'>+			fkeys-&gt;addrs.v6addrs.dst =</div><div class='add'>+				*(struct in6_addr *)&amp;ip_spec-&gt;ip6dst;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_DST_IP;</div><div class='add'>+		} else if (!ipv6_mask_is_zero(ip_mask-&gt;ip6dst)) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (ip_mask-&gt;psrc == L4_PORT_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;ports.src = ip_spec-&gt;psrc;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_SRC_PORT;</div><div class='add'>+		} else if (ip_mask-&gt;psrc) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		if (ip_mask-&gt;pdst == L4_PORT_ALL_MASK) {</div><div class='add'>+			fkeys-&gt;ports.dst = ip_spec-&gt;pdst;</div><div class='add'>+			new_fltr-&gt;ntuple_flags |= BNXT_NTUPLE_MATCH_DST_PORT;</div><div class='add'>+		} else if (ip_mask-&gt;pdst) {</div><div class='add'>+			goto ntuple_err;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	default:</div><div class='add'>+		rc = -EOPNOTSUPP;</div><div class='add'>+		goto ntuple_err;</div><div class='add'>+	}</div><div class='add'>+	if (!new_fltr-&gt;ntuple_flags)</div><div class='add'>+		goto ntuple_err;</div><div class='add'>+</div><div class='add'>+	idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);</div><div class='add'>+	if (fltr) {</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+		rc = -EEXIST;</div><div class='add'>+		goto ntuple_err;</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+</div><div class='add'>+	new_fltr-&gt;base.rxq = ring;</div><div class='add'>+	new_fltr-&gt;base.flags = BNXT_ACT_NO_AGING;</div><div class='add'>+	__set_bit(BNXT_FLTR_VALID, &amp;new_fltr-&gt;base.state);</div><div class='add'>+	rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);</div><div class='add'>+	if (!rc) {</div><div class='add'>+		rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);</div><div class='add'>+		if (rc) {</div><div class='add'>+			bnxt_del_ntp_filter(bp, new_fltr);</div><div class='add'>+			return rc;</div><div class='add'>+		}</div><div class='add'>+		fs-&gt;location = new_fltr-&gt;base.sw_id;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+ntuple_err:</div><div class='add'>+	atomic_dec(&amp;l2_fltr-&gt;refcnt);</div><div class='add'>+	kfree(new_fltr);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct ethtool_rx_flow_spec *fs = &amp;cmd-&gt;fs;</div><div class='add'>+	u32 ring, flow_type;</div><div class='add'>+	int rc;</div><div class='add'>+	u8 vf;</div><div class='add'>+</div><div class='add'>+	if (!netif_running(bp-&gt;dev))</div><div class='add'>+		return -EAGAIN;</div><div class='add'>+	if (!(bp-&gt;flags &amp; BNXT_FLAG_RFS))</div><div class='add'>+		return -EPERM;</div><div class='add'>+	if (fs-&gt;location != RX_CLS_LOC_ANY)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ring = ethtool_get_flow_spec_ring(fs-&gt;ring_cookie);</div><div class='add'>+	vf = ethtool_get_flow_spec_ring_vf(fs-&gt;ring_cookie);</div><div class='add'>+	if (BNXT_VF(bp) &amp;&amp; vf)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	if (BNXT_PF(bp) &amp;&amp; vf &gt; bp-&gt;pf.active_vfs)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	if (!vf &amp;&amp; ring &gt;= bp-&gt;rx_nr_rings)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	flow_type = fs-&gt;flow_type;</div><div class='add'>+	if (flow_type &amp; (FLOW_MAC_EXT | FLOW_RSS))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	flow_type &amp;= ~FLOW_EXT;</div><div class='add'>+	if (flow_type == ETHER_FLOW)</div><div class='add'>+		rc = -EOPNOTSUPP;</div><div class='add'>+	else</div><div class='add'>+		rc = bnxt_add_ntuple_cls_rule(bp, fs);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct ethtool_rx_flow_spec *fs = &amp;cmd-&gt;fs;</div><div class='add'>+	struct bnxt_filter_base *fltr_base;</div><div class='add'>+	struct bnxt_ntuple_filter *fltr;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	fltr_base = bnxt_get_one_fltr_rcu(bp, bp-&gt;ntp_fltr_hash_tbl,</div><div class='add'>+					  BNXT_NTP_FLTR_HASH_SIZE,</div><div class='add'>+					  fs-&gt;location);</div><div class='add'>+	if (!fltr_base) {</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+		return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);</div><div class='add'>+	if (!(fltr-&gt;base.flags &amp; BNXT_ACT_NO_AGING)) {</div><div class='add'>+		rcu_read_unlock();</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+	bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);</div><div class='add'>+	bnxt_del_ntp_filter(bp, fltr);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static u64 get_ethtool_ipv4_rss(struct bnxt *bp)</div><div class='ctx'> {</div><div class='hunk'>@@ -1200,7 +1448,7 @@ static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 		if (tuple == 4)</div><div class='ctx'> 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;</div><div class='ctx'> 	} else if (cmd-&gt;flow_type == UDP_V4_FLOW) {</div><div class='del'>-		if (tuple == 4 &amp;&amp; !(bp-&gt;flags &amp; BNXT_FLAG_UDP_RSS_CAP))</div><div class='add'>+		if (tuple == 4 &amp;&amp; !(bp-&gt;rss_cap &amp; BNXT_RSS_CAP_UDP_RSS_CAP))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		rss_hash_cfg &amp;= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;</div><div class='ctx'> 		if (tuple == 4)</div><div class='hunk'>@@ -1210,7 +1458,7 @@ static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 		if (tuple == 4)</div><div class='ctx'> 			rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;</div><div class='ctx'> 	} else if (cmd-&gt;flow_type == UDP_V6_FLOW) {</div><div class='del'>-		if (tuple == 4 &amp;&amp; !(bp-&gt;flags &amp; BNXT_FLAG_UDP_RSS_CAP))</div><div class='add'>+		if (tuple == 4 &amp;&amp; !(bp-&gt;rss_cap &amp; BNXT_RSS_CAP_UDP_RSS_CAP))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		rss_hash_cfg &amp;= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;</div><div class='ctx'> 		if (tuple == 4)</div><div class='hunk'>@@ -1250,7 +1498,7 @@ static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 	if (bp-&gt;rss_hash_cfg == rss_hash_cfg)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;fw_cap &amp; BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)</div><div class='add'>+	if (bp-&gt;rss_cap &amp; BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)</div><div class='ctx'> 		bp-&gt;rss_hash_delta = bp-&gt;rss_hash_cfg ^ rss_hash_cfg;</div><div class='ctx'> 	bp-&gt;rss_hash_cfg = rss_hash_cfg;</div><div class='ctx'> 	if (netif_running(bp-&gt;dev)) {</div><div class='hunk'>@@ -1267,14 +1515,13 @@ static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (cmd-&gt;cmd) {</div><div class='del'>-#ifdef CONFIG_RFS_ACCEL</div><div class='ctx'> 	case ETHTOOL_GRXRINGS:</div><div class='ctx'> 		cmd-&gt;data = bp-&gt;rx_nr_rings;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case ETHTOOL_GRXCLSRLCNT:</div><div class='ctx'> 		cmd-&gt;rule_cnt = bp-&gt;ntp_fltr_count;</div><div class='del'>-		cmd-&gt;data = BNXT_NTP_FLTR_MAX_FLTR;</div><div class='add'>+		cmd-&gt;data = BNXT_NTP_FLTR_MAX_FLTR | RX_CLS_LOC_SPECIAL;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	case ETHTOOL_GRXCLSRLALL:</div><div class='hunk'>@@ -1284,7 +1531,6 @@ static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,</div><div class='ctx'> 	case ETHTOOL_GRXCLSRULE:</div><div class='ctx'> 		rc = bnxt_grxclsrule(bp, cmd);</div><div class='ctx'> 		break;</div><div class='del'>-#endif</div><div class='ctx'> </div><div class='ctx'> 	case ETHTOOL_GRXFH:</div><div class='ctx'> 		rc = bnxt_grxfh(bp, cmd);</div><div class='hunk'>@@ -1308,6 +1554,14 @@ static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 		rc = bnxt_srxfh(bp, cmd);</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='add'>+	case ETHTOOL_SRXCLSRLINS:</div><div class='add'>+		rc = bnxt_srxclsrlins(bp, cmd);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case ETHTOOL_SRXCLSRLDEL:</div><div class='add'>+		rc = bnxt_srxclsrldel(bp, cmd);</div><div class='add'>+		break;</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		rc = -EOPNOTSUPP;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1319,7 +1573,7 @@ u32 bnxt_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		return ALIGN(bp-&gt;rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);</div><div class='ctx'> 	return HW_HASH_INDEX_SIZE;</div><div class='ctx'> }</div><div class='hunk'>@@ -1329,49 +1583,49 @@ static u32 bnxt_get_rxfh_key_size(struct net_device *dev)</div><div class='ctx'> 	return HW_HASH_KEY_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int bnxt_get_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='ctx'> 	struct bnxt_vnic_info *vnic;</div><div class='ctx'> 	u32 i, tbl_size;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	if (!bp-&gt;vnic_info)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	vnic = &amp;bp-&gt;vnic_info[0];</div><div class='del'>-	if (indir &amp;&amp; bp-&gt;rss_indir_tbl) {</div><div class='add'>+	if (rxfh-&gt;indir &amp;&amp; bp-&gt;rss_indir_tbl) {</div><div class='ctx'> 		tbl_size = bnxt_get_rxfh_indir_size(dev);</div><div class='ctx'> 		for (i = 0; i &lt; tbl_size; i++)</div><div class='del'>-			indir[i] = bp-&gt;rss_indir_tbl[i];</div><div class='add'>+			rxfh-&gt;indir[i] = bp-&gt;rss_indir_tbl[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key &amp;&amp; vnic-&gt;rss_hash_key)</div><div class='del'>-		memcpy(key, vnic-&gt;rss_hash_key, HW_HASH_KEY_SIZE);</div><div class='add'>+	if (rxfh-&gt;key &amp;&amp; vnic-&gt;rss_hash_key)</div><div class='add'>+		memcpy(rxfh-&gt;key, vnic-&gt;rss_hash_key, HW_HASH_KEY_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int bnxt_set_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='ctx'> 	int rc = 0;</div><div class='ctx'> </div><div class='del'>-	if (hfunc &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc &amp;&amp; rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; tbl_size; i++)</div><div class='del'>-			bp-&gt;rss_indir_tbl[i] = indir[i];</div><div class='add'>+			bp-&gt;rss_indir_tbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 		pad = bp-&gt;rss_indir_tbl_entries - tbl_size;</div><div class='ctx'> 		if (pad)</div><div class='ctx'> 			memset(&amp;bp-&gt;rss_indir_tbl[i], 0, pad * sizeof(u16));</div><div class='hunk'>@@ -1574,6 +1828,22 @@ static const enum bnxt_media_type bnxt_phy_types[] = {</div><div class='ctx'> 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,</div><div class='ctx'> 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,</div><div class='ctx'> 	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,</div><div class='add'>+	[PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static enum bnxt_media_type</div><div class='hunk'>@@ -1601,6 +1871,7 @@ enum bnxt_link_speed_indices {</div><div class='ctx'> 	BNXT_LINK_SPEED_50GB_IDX,</div><div class='ctx'> 	BNXT_LINK_SPEED_100GB_IDX,</div><div class='ctx'> 	BNXT_LINK_SPEED_200GB_IDX,</div><div class='add'>+	BNXT_LINK_SPEED_400GB_IDX,</div><div class='ctx'> 	__BNXT_LINK_SPEED_END</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1612,9 +1883,21 @@ static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)</div><div class='ctx'> 	case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;</div><div class='ctx'> 	case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;</div><div class='ctx'> 	case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;</div><div class='del'>-	case BNXT_LINK_SPEED_50GB: return BNXT_LINK_SPEED_50GB_IDX;</div><div class='del'>-	case BNXT_LINK_SPEED_100GB: return BNXT_LINK_SPEED_100GB_IDX;</div><div class='del'>-	case BNXT_LINK_SPEED_200GB: return BNXT_LINK_SPEED_200GB_IDX;</div><div class='add'>+	case BNXT_LINK_SPEED_50GB:</div><div class='add'>+	case BNXT_LINK_SPEED_50GB_PAM4:</div><div class='add'>+		return BNXT_LINK_SPEED_50GB_IDX;</div><div class='add'>+	case BNXT_LINK_SPEED_100GB:</div><div class='add'>+	case BNXT_LINK_SPEED_100GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_100GB_PAM4_112:</div><div class='add'>+		return BNXT_LINK_SPEED_100GB_IDX;</div><div class='add'>+	case BNXT_LINK_SPEED_200GB:</div><div class='add'>+	case BNXT_LINK_SPEED_200GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_200GB_PAM4_112:</div><div class='add'>+		return BNXT_LINK_SPEED_200GB_IDX;</div><div class='add'>+	case BNXT_LINK_SPEED_400GB:</div><div class='add'>+	case BNXT_LINK_SPEED_400GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_400GB_PAM4_112:</div><div class='add'>+		return BNXT_LINK_SPEED_400GB_IDX;</div><div class='ctx'> 	default: return BNXT_LINK_SPEED_UNKNOWN;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1687,6 +1970,12 @@ bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {</div><div class='ctx'> 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,</div><div class='ctx'> 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,</div><div class='ctx'> 		},</div><div class='add'>+		[BNXT_SIG_MODE_PAM4_112] = {</div><div class='add'>+			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,</div><div class='add'>+		},</div><div class='ctx'> 	},</div><div class='ctx'> 	[BNXT_LINK_SPEED_200GB_IDX] = {</div><div class='ctx'> 		[BNXT_SIG_MODE_PAM4] = {</div><div class='hunk'>@@ -1695,6 +1984,26 @@ bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {</div><div class='ctx'> 			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,</div><div class='ctx'> 			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,</div><div class='ctx'> 		},</div><div class='add'>+		[BNXT_SIG_MODE_PAM4_112] = {</div><div class='add'>+			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[BNXT_LINK_SPEED_400GB_IDX] = {</div><div class='add'>+		[BNXT_SIG_MODE_PAM4] = {</div><div class='add'>+			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,</div><div class='add'>+		},</div><div class='add'>+		[BNXT_SIG_MODE_PAM4_112] = {</div><div class='add'>+			[BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,</div><div class='add'>+			[BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,</div><div class='add'>+		},</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1759,7 +2068,8 @@ static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,</div><div class='ctx'> 				 lk_ksettings-&gt;link_modes.supported);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (link_info-&gt;support_auto_speeds || link_info-&gt;support_pam4_auto_speeds)</div><div class='add'>+	if (link_info-&gt;support_auto_speeds || link_info-&gt;support_auto_speeds2 ||</div><div class='add'>+	    link_info-&gt;support_pam4_auto_speeds)</div><div class='ctx'> 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,</div><div class='ctx'> 				 lk_ksettings-&gt;link_modes.supported);</div><div class='ctx'> </div><div class='hunk'>@@ -1795,22 +2105,60 @@ static const u16 bnxt_pam4_speed_masks[] = {</div><div class='ctx'> 	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,</div><div class='ctx'> 	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,</div><div class='ctx'> 	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,</div><div class='add'>+	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 bnxt_nrz_speeds2_masks[] = {</div><div class='add'>+	[BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,</div><div class='add'>+	[BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,</div><div class='add'>+	[BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,</div><div class='add'>+	[BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,</div><div class='add'>+	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,</div><div class='add'>+	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,</div><div class='add'>+	[__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 bnxt_pam4_speeds2_masks[] = {</div><div class='add'>+	[BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,</div><div class='add'>+	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,</div><div class='add'>+	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,</div><div class='add'>+	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const u16 bnxt_pam4_112_speeds2_masks[] = {</div><div class='add'>+	[BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,</div><div class='add'>+	[BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,</div><div class='add'>+	[BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static enum bnxt_link_speed_indices</div><div class='del'>-bnxt_encoding_speed_idx(u8 sig_mode, u16 speed_msk)</div><div class='add'>+bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)</div><div class='ctx'> {</div><div class='ctx'> 	const u16 *speeds;</div><div class='ctx'> 	int idx, len;</div><div class='ctx'> </div><div class='ctx'> 	switch (sig_mode) {</div><div class='ctx'> 	case BNXT_SIG_MODE_NRZ:</div><div class='del'>-		speeds = bnxt_nrz_speed_masks;</div><div class='del'>-		len = ARRAY_SIZE(bnxt_nrz_speed_masks);</div><div class='add'>+		if (phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+			speeds = bnxt_nrz_speeds2_masks;</div><div class='add'>+			len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);</div><div class='add'>+		} else {</div><div class='add'>+			speeds = bnxt_nrz_speed_masks;</div><div class='add'>+			len = ARRAY_SIZE(bnxt_nrz_speed_masks);</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case BNXT_SIG_MODE_PAM4:</div><div class='del'>-		speeds = bnxt_pam4_speed_masks;</div><div class='del'>-		len = ARRAY_SIZE(bnxt_pam4_speed_masks);</div><div class='add'>+		if (phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+			speeds = bnxt_pam4_speeds2_masks;</div><div class='add'>+			len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);</div><div class='add'>+		} else {</div><div class='add'>+			speeds = bnxt_pam4_speed_masks;</div><div class='add'>+			len = ARRAY_SIZE(bnxt_pam4_speed_masks);</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case BNXT_SIG_MODE_PAM4_112:</div><div class='add'>+		speeds = bnxt_pam4_112_speeds2_masks;</div><div class='add'>+		len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return BNXT_LINK_SPEED_UNKNOWN;</div><div class='hunk'>@@ -1828,14 +2176,14 @@ bnxt_encoding_speed_idx(u8 sig_mode, u16 speed_msk)</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='ctx'> __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,</div><div class='del'>-			  u8 sig_mode, unsigned long *et_mask)</div><div class='add'>+			  u8 sig_mode, u16 phy_flags, unsigned long *et_mask)</div><div class='ctx'> {</div><div class='ctx'> 	enum ethtool_link_mode_bit_indices link_mode;</div><div class='ctx'> 	enum bnxt_link_speed_indices speed;</div><div class='ctx'> 	u8 bit;</div><div class='ctx'> </div><div class='ctx'> 	for_each_set_bit(bit, &amp;fw_mask, BNXT_FW_SPEED_MSK_BITS) {</div><div class='del'>-		speed = bnxt_encoding_speed_idx(sig_mode, 1 &lt;&lt; bit);</div><div class='add'>+		speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 &lt;&lt; bit);</div><div class='ctx'> 		if (!speed)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -1849,16 +2197,83 @@ __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='ctx'> bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,</div><div class='del'>-			u8 sig_mode, unsigned long *et_mask)</div><div class='add'>+			u8 sig_mode, u16 phy_flags, unsigned long *et_mask)</div><div class='ctx'> {</div><div class='ctx'> 	if (media) {</div><div class='del'>-		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask);</div><div class='add'>+		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,</div><div class='add'>+					  et_mask);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* list speeds for all media if unknown */</div><div class='ctx'> 	for (media = 1; media &lt; __BNXT_MEDIA_END; media++)</div><div class='del'>-		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, et_mask);</div><div class='add'>+		__bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,</div><div class='add'>+					  et_mask);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,</div><div class='add'>+				    enum bnxt_media_type media,</div><div class='add'>+				    struct ethtool_link_ksettings *lk_ksettings)</div><div class='add'>+{</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;</div><div class='add'>+	u16 phy_flags = bp-&gt;phy_flags;</div><div class='add'>+</div><div class='add'>+	if (phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		sp_nrz = link_info-&gt;support_speeds2;</div><div class='add'>+		sp_pam4 = link_info-&gt;support_speeds2;</div><div class='add'>+		sp_pam4_112 = link_info-&gt;support_speeds2;</div><div class='add'>+	} else {</div><div class='add'>+		sp_nrz = link_info-&gt;support_speeds;</div><div class='add'>+		sp_pam4 = link_info-&gt;support_pam4_speeds;</div><div class='add'>+	}</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.supported);</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.supported);</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,</div><div class='add'>+				phy_flags, lk_ksettings-&gt;link_modes.supported);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,</div><div class='add'>+				enum bnxt_media_type media,</div><div class='add'>+				struct ethtool_link_ksettings *lk_ksettings)</div><div class='add'>+{</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+	u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;</div><div class='add'>+	u16 phy_flags = bp-&gt;phy_flags;</div><div class='add'>+</div><div class='add'>+	sp_nrz = link_info-&gt;advertising;</div><div class='add'>+	if (phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		sp_pam4 = link_info-&gt;advertising;</div><div class='add'>+		sp_pam4_112 = link_info-&gt;advertising;</div><div class='add'>+	} else {</div><div class='add'>+		sp_pam4 = link_info-&gt;advertising_pam4;</div><div class='add'>+	}</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.advertising);</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.advertising);</div><div class='add'>+	bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,</div><div class='add'>+				phy_flags, lk_ksettings-&gt;link_modes.advertising);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,</div><div class='add'>+			       enum bnxt_media_type media,</div><div class='add'>+			       struct ethtool_link_ksettings *lk_ksettings)</div><div class='add'>+{</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+	u16 phy_flags = bp-&gt;phy_flags;</div><div class='add'>+</div><div class='add'>+	bnxt_get_ethtool_speeds(link_info-&gt;lp_auto_link_speeds, media,</div><div class='add'>+				BNXT_SIG_MODE_NRZ, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.lp_advertising);</div><div class='add'>+	bnxt_get_ethtool_speeds(link_info-&gt;lp_auto_pam4_link_speeds, media,</div><div class='add'>+				BNXT_SIG_MODE_PAM4, phy_flags,</div><div class='add'>+				lk_ksettings-&gt;link_modes.lp_advertising);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,</div><div class='hunk'>@@ -1887,22 +2302,42 @@ static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,</div><div class='ctx'> static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,</div><div class='ctx'> 				    const unsigned long *et_mask)</div><div class='ctx'> {</div><div class='add'>+	struct bnxt *bp = container_of(link_info, struct bnxt, link_info);</div><div class='add'>+	u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;</div><div class='ctx'> 	enum bnxt_media_type media = bnxt_get_media(link_info);</div><div class='add'>+	u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;</div><div class='add'>+	u32 delta_pam4_112 = 0;</div><div class='ctx'> 	u32 delta_pam4 = 0;</div><div class='ctx'> 	u32 delta_nrz = 0;</div><div class='ctx'> 	int i, m;</div><div class='ctx'> </div><div class='add'>+	adv = &amp;link_info-&gt;advertising;</div><div class='add'>+	if (bp-&gt;phy_flags &amp; BNXT_PHY_FL_SPEEDS2) {</div><div class='add'>+		adv_pam4 = &amp;link_info-&gt;advertising;</div><div class='add'>+		adv_pam4_112 = &amp;link_info-&gt;advertising;</div><div class='add'>+		sp_msks = bnxt_nrz_speeds2_masks;</div><div class='add'>+		sp_pam4_msks = bnxt_pam4_speeds2_masks;</div><div class='add'>+		sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;</div><div class='add'>+	} else {</div><div class='add'>+		adv_pam4 = &amp;link_info-&gt;advertising_pam4;</div><div class='add'>+		sp_msks = bnxt_nrz_speed_masks;</div><div class='add'>+		sp_pam4_msks = bnxt_pam4_speed_masks;</div><div class='add'>+	}</div><div class='ctx'> 	for (i = 1; i &lt; __BNXT_LINK_SPEED_END; i++) {</div><div class='ctx'> 		/* accept any legal media from user */</div><div class='ctx'> 		for (m = 1; m &lt; __BNXT_MEDIA_END; m++) {</div><div class='ctx'> 			bnxt_update_speed(&amp;delta_nrz, m == media,</div><div class='del'>-					  &amp;link_info-&gt;advertising,</div><div class='del'>-					  bnxt_nrz_speed_masks[i], et_mask,</div><div class='add'>+					  adv, sp_msks[i], et_mask,</div><div class='ctx'> 					  bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);</div><div class='ctx'> 			bnxt_update_speed(&amp;delta_pam4, m == media,</div><div class='del'>-					  &amp;link_info-&gt;advertising_pam4,</div><div class='del'>-					  bnxt_pam4_speed_masks[i], et_mask,</div><div class='add'>+					  adv_pam4, sp_pam4_msks[i], et_mask,</div><div class='ctx'> 					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);</div><div class='add'>+			if (!adv_pam4_112)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			bnxt_update_speed(&amp;delta_pam4_112, m == media,</div><div class='add'>+					  adv_pam4_112, sp_pam4_112_msks[i], et_mask,</div><div class='add'>+					  bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1967,11 +2402,20 @@ u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)</div><div class='ctx'> 	case BNXT_LINK_SPEED_40GB:</div><div class='ctx'> 		return SPEED_40000;</div><div class='ctx'> 	case BNXT_LINK_SPEED_50GB:</div><div class='add'>+	case BNXT_LINK_SPEED_50GB_PAM4:</div><div class='ctx'> 		return SPEED_50000;</div><div class='ctx'> 	case BNXT_LINK_SPEED_100GB:</div><div class='add'>+	case BNXT_LINK_SPEED_100GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_100GB_PAM4_112:</div><div class='ctx'> 		return SPEED_100000;</div><div class='ctx'> 	case BNXT_LINK_SPEED_200GB:</div><div class='add'>+	case BNXT_LINK_SPEED_200GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_200GB_PAM4_112:</div><div class='ctx'> 		return SPEED_200000;</div><div class='add'>+	case BNXT_LINK_SPEED_400GB:</div><div class='add'>+	case BNXT_LINK_SPEED_400GB_PAM4:</div><div class='add'>+	case BNXT_LINK_SPEED_400GB_PAM4_112:</div><div class='add'>+		return SPEED_400000;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return SPEED_UNKNOWN;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1987,6 +2431,7 @@ static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,</div><div class='ctx'> 		base-&gt;duplex = DUPLEX_HALF;</div><div class='ctx'> 		if (link_info-&gt;duplex &amp; BNXT_LINK_DUPLEX_FULL)</div><div class='ctx'> 			base-&gt;duplex = DUPLEX_FULL;</div><div class='add'>+		lk_ksettings-&gt;lanes = link_info-&gt;active_lanes;</div><div class='ctx'> 	} else if (!link_info-&gt;autoneg) {</div><div class='ctx'> 		base-&gt;speed = bnxt_fw_to_ethtool_speed(link_info-&gt;req_link_speed);</div><div class='ctx'> 		base-&gt;duplex = DUPLEX_HALF;</div><div class='hunk'>@@ -2014,12 +2459,7 @@ static int bnxt_get_link_ksettings(struct net_device *dev,</div><div class='ctx'> 	mutex_lock(&amp;bp-&gt;link_lock);</div><div class='ctx'> 	bnxt_get_ethtool_modes(link_info, lk_ksettings);</div><div class='ctx'> 	media = bnxt_get_media(link_info);</div><div class='del'>-	bnxt_get_ethtool_speeds(link_info-&gt;support_speeds,</div><div class='del'>-				media, BNXT_SIG_MODE_NRZ,</div><div class='del'>-				lk_ksettings-&gt;link_modes.supported);</div><div class='del'>-	bnxt_get_ethtool_speeds(link_info-&gt;support_pam4_speeds,</div><div class='del'>-				media, BNXT_SIG_MODE_PAM4,</div><div class='del'>-				lk_ksettings-&gt;link_modes.supported);</div><div class='add'>+	bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);</div><div class='ctx'> 	bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);</div><div class='ctx'> 	link_mode = bnxt_get_link_mode(link_info);</div><div class='ctx'> 	if (link_mode != BNXT_LINK_MODE_UNKNOWN)</div><div class='hunk'>@@ -2032,20 +2472,10 @@ static int bnxt_get_link_ksettings(struct net_device *dev,</div><div class='ctx'> 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,</div><div class='ctx'> 				 lk_ksettings-&gt;link_modes.advertising);</div><div class='ctx'> 		base-&gt;autoneg = AUTONEG_ENABLE;</div><div class='del'>-		bnxt_get_ethtool_speeds(link_info-&gt;advertising,</div><div class='del'>-					media, BNXT_SIG_MODE_NRZ,</div><div class='del'>-					lk_ksettings-&gt;link_modes.advertising);</div><div class='del'>-		bnxt_get_ethtool_speeds(link_info-&gt;advertising_pam4,</div><div class='del'>-					media, BNXT_SIG_MODE_PAM4,</div><div class='del'>-					lk_ksettings-&gt;link_modes.advertising);</div><div class='del'>-		if (link_info-&gt;phy_link_status == BNXT_LINK_LINK) {</div><div class='del'>-			bnxt_get_ethtool_speeds(link_info-&gt;lp_auto_link_speeds,</div><div class='del'>-						media, BNXT_SIG_MODE_NRZ,</div><div class='del'>-						lk_ksettings-&gt;link_modes.lp_advertising);</div><div class='del'>-			bnxt_get_ethtool_speeds(link_info-&gt;lp_auto_pam4_link_speeds,</div><div class='del'>-						media, BNXT_SIG_MODE_PAM4,</div><div class='del'>-						lk_ksettings-&gt;link_modes.lp_advertising);</div><div class='del'>-		}</div><div class='add'>+		bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);</div><div class='add'>+		if (link_info-&gt;phy_link_status == BNXT_LINK_LINK)</div><div class='add'>+			bnxt_get_all_ethtool_lp_speeds(link_info, media,</div><div class='add'>+						       lk_ksettings);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		base-&gt;autoneg = AUTONEG_DISABLE;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2080,6 +2510,7 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 	struct bnxt *bp = netdev_priv(dev);</div><div class='ctx'> 	struct bnxt_link_info *link_info = &amp;bp-&gt;link_info;</div><div class='ctx'> 	u16 support_pam4_spds = link_info-&gt;support_pam4_speeds;</div><div class='add'>+	u16 support_spds2 = link_info-&gt;support_speeds2;</div><div class='ctx'> 	u16 support_spds = link_info-&gt;support_speeds;</div><div class='ctx'> 	u8 sig_mode = BNXT_SIG_MODE_NRZ;</div><div class='ctx'> 	u32 lanes_needed = 1;</div><div class='hunk'>@@ -2091,7 +2522,8 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_1000:</div><div class='del'>-		if (support_spds &amp; BNXT_LINK_SPEED_MSK_1GB)</div><div class='add'>+		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_1GB) ||</div><div class='add'>+		    (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_1GB))</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_2500:</div><div class='hunk'>@@ -2099,7 +2531,8 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_10000:</div><div class='del'>-		if (support_spds &amp; BNXT_LINK_SPEED_MSK_10GB)</div><div class='add'>+		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_10GB) ||</div><div class='add'>+		    (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_10GB))</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_20000:</div><div class='hunk'>@@ -2109,26 +2542,34 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_25000:</div><div class='del'>-		if (support_spds &amp; BNXT_LINK_SPEED_MSK_25GB)</div><div class='add'>+		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_25GB) ||</div><div class='add'>+		    (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_25GB))</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_40000:</div><div class='del'>-		if (support_spds &amp; BNXT_LINK_SPEED_MSK_40GB) {</div><div class='add'>+		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_40GB) ||</div><div class='add'>+		    (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_40GB)) {</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;</div><div class='ctx'> 			lanes_needed = 4;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_50000:</div><div class='del'>-		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_50GB) &amp;&amp; lanes != 1) {</div><div class='add'>+		if (((support_spds &amp; BNXT_LINK_SPEED_MSK_50GB) ||</div><div class='add'>+		     (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_50GB)) &amp;&amp;</div><div class='add'>+		    lanes != 1) {</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;</div><div class='ctx'> 			lanes_needed = 2;</div><div class='ctx'> 		} else if (support_pam4_spds &amp; BNXT_LINK_PAM4_SPEED_MSK_50GB) {</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;</div><div class='ctx'> 			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='add'>+		} else if (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_50GB_PAM4;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_100000:</div><div class='del'>-		if ((support_spds &amp; BNXT_LINK_SPEED_MSK_100GB) &amp;&amp;</div><div class='add'>+		if (((support_spds &amp; BNXT_LINK_SPEED_MSK_100GB) ||</div><div class='add'>+		     (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_100GB)) &amp;&amp;</div><div class='ctx'> 		    lanes != 2 &amp;&amp; lanes != 1) {</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;</div><div class='ctx'> 			lanes_needed = 4;</div><div class='hunk'>@@ -2136,6 +2577,14 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;</div><div class='ctx'> 			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='ctx'> 			lanes_needed = 2;</div><div class='add'>+		} else if ((support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &amp;&amp;</div><div class='add'>+			   lanes != 1) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_100GB_PAM4;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='add'>+			lanes_needed = 2;</div><div class='add'>+		} else if (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4_112;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_200000:</div><div class='hunk'>@@ -2143,6 +2592,27 @@ bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)</div><div class='ctx'> 			fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;</div><div class='ctx'> 			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='ctx'> 			lanes_needed = 4;</div><div class='add'>+		} else if ((support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &amp;&amp;</div><div class='add'>+			   lanes != 2) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_200GB_PAM4;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='add'>+			lanes_needed = 4;</div><div class='add'>+		} else if (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4_112;</div><div class='add'>+			lanes_needed = 2;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case SPEED_400000:</div><div class='add'>+		if ((support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &amp;&amp;</div><div class='add'>+		    lanes != 4) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_400GB_PAM4;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4;</div><div class='add'>+			lanes_needed = 8;</div><div class='add'>+		} else if (support_spds2 &amp; BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {</div><div class='add'>+			fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;</div><div class='add'>+			sig_mode = BNXT_SIG_MODE_PAM4_112;</div><div class='add'>+			lanes_needed = 4;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3916,7 +4386,8 @@ static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,</div><div class='ctx'> 		 * reading any further.</div><div class='ctx'> 		 */</div><div class='ctx'> 		dma_rmb();</div><div class='del'>-		if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {</div><div class='add'>+		if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||</div><div class='add'>+		    TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {</div><div class='ctx'> 			rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);</div><div class='ctx'> 			raw_cons = NEXT_RAW_CMP(raw_cons);</div><div class='ctx'> 			raw_cons = NEXT_RAW_CMP(raw_cons);</div><div class='hunk'>@@ -3940,8 +4411,8 @@ static int bnxt_run_loopback(struct bnxt *bp)</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	cpr = &amp;rxr-&gt;bnapi-&gt;cp_ring;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='del'>-		cpr = cpr-&gt;cp_ring_arr[BNXT_RX_HDL];</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='add'>+		cpr = rxr-&gt;rx_cpr;</div><div class='ctx'> 	pkt_size = min(bp-&gt;dev-&gt;mtu + ETH_HLEN, bp-&gt;rx_copy_thresh);</div><div class='ctx'> 	skb = netdev_alloc_skb(bp-&gt;dev, pkt_size);</div><div class='ctx'> 	if (!skb)</div><div class='hunk'>@@ -4042,12 +4513,7 @@ static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,</div><div class='ctx'> 		bnxt_run_fw_tests(bp, test_mask, &amp;test_results);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		bnxt_ulp_stop(bp);</div><div class='del'>-		rc = bnxt_close_nic(bp, true, false);</div><div class='del'>-		if (rc) {</div><div class='del'>-			etest-&gt;flags |= ETH_TEST_FL_FAILED;</div><div class='del'>-			bnxt_ulp_start(bp, rc);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='add'>+		bnxt_close_nic(bp, true, false);</div><div class='ctx'> 		bnxt_run_fw_tests(bp, test_mask, &amp;test_results);</div><div class='ctx'> </div><div class='ctx'> 		buf[BNXT_MACLPBK_TEST_IDX] = 1;</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h<br/>index d5fad5a3cdd1..e957abd704db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h</a></div><div class='hunk'>@@ -40,6 +40,8 @@ struct hwrm_resp_hdr {</div><div class='ctx'> #define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL</div><div class='ctx'> #define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL</div><div class='ctx'> #define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL</div><div class='add'>+#define TLV_TYPE_QUERY_ROCE_CC_GEN2              0x6UL</div><div class='add'>+#define TLV_TYPE_MODIFY_ROCE_CC_GEN2             0x7UL</div><div class='ctx'> #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL</div><div class='ctx'> #define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL</div><div class='ctx'> #define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL</div><div class='hunk'>@@ -196,6 +198,9 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG      0x8aUL</div><div class='ctx'> 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG       0x8bUL</div><div class='ctx'> 	#define HWRM_QUEUE_QCAPS                          0x8cUL</div><div class='add'>+	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG       0x8dUL</div><div class='add'>+	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG        0x8eUL</div><div class='add'>+	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG       0x8fUL</div><div class='ctx'> 	#define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL</div><div class='ctx'> 	#define HWRM_CFA_L2_FILTER_FREE                   0x91UL</div><div class='ctx'> 	#define HWRM_CFA_L2_FILTER_CFG                    0x92UL</div><div class='hunk'>@@ -214,6 +219,7 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL</div><div class='ctx'> 	#define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL</div><div class='ctx'> 	#define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL</div><div class='add'>+	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG        0xa3UL</div><div class='ctx'> 	#define HWRM_STAT_CTX_ENG_QUERY                   0xafUL</div><div class='ctx'> 	#define HWRM_STAT_CTX_ALLOC                       0xb0UL</div><div class='ctx'> 	#define HWRM_STAT_CTX_FREE                        0xb1UL</div><div class='hunk'>@@ -261,6 +267,7 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_PORT_EP_TX_CFG                       0xdbUL</div><div class='ctx'> 	#define HWRM_PORT_CFG                             0xdcUL</div><div class='ctx'> 	#define HWRM_PORT_QCFG                            0xddUL</div><div class='add'>+	#define HWRM_PORT_MAC_QCAPS                       0xdfUL</div><div class='ctx'> 	#define HWRM_TEMP_MONITOR_QUERY                   0xe0UL</div><div class='ctx'> 	#define HWRM_REG_POWER_QUERY                      0xe1UL</div><div class='ctx'> 	#define HWRM_CORE_FREQUENCY_QUERY                 0xe2UL</div><div class='hunk'>@@ -392,6 +399,10 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_FUNC_KEY_CTX_FREE                    0x1adUL</div><div class='ctx'> 	#define HWRM_FUNC_LAG_MODE_CFG                    0x1aeUL</div><div class='ctx'> 	#define HWRM_FUNC_LAG_MODE_QCFG                   0x1afUL</div><div class='add'>+	#define HWRM_FUNC_LAG_CREATE                      0x1b0UL</div><div class='add'>+	#define HWRM_FUNC_LAG_UPDATE                      0x1b1UL</div><div class='add'>+	#define HWRM_FUNC_LAG_FREE                        0x1b2UL</div><div class='add'>+	#define HWRM_FUNC_LAG_QCFG                        0x1b3UL</div><div class='ctx'> 	#define HWRM_SELFTEST_QLIST                       0x200UL</div><div class='ctx'> 	#define HWRM_SELFTEST_EXEC                        0x201UL</div><div class='ctx'> 	#define HWRM_SELFTEST_IRQ                         0x202UL</div><div class='hunk'>@@ -406,9 +417,9 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_MFG_FRU_EEPROM_READ                  0x20bUL</div><div class='ctx'> 	#define HWRM_MFG_SOC_IMAGE                        0x20cUL</div><div class='ctx'> 	#define HWRM_MFG_SOC_QSTATUS                      0x20dUL</div><div class='del'>-	#define HWRM_MFG_PARAM_SEEPROM_SYNC               0x20eUL</div><div class='del'>-	#define HWRM_MFG_PARAM_SEEPROM_READ               0x20fUL</div><div class='del'>-	#define HWRM_MFG_PARAM_SEEPROM_HEALTH             0x210UL</div><div class='add'>+	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE     0x20eUL</div><div class='add'>+	#define HWRM_MFG_PARAM_CRITICAL_DATA_READ         0x20fUL</div><div class='add'>+	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH       0x210UL</div><div class='ctx'> 	#define HWRM_MFG_PRVSN_EXPORT_CSR                 0x211UL</div><div class='ctx'> 	#define HWRM_MFG_PRVSN_IMPORT_CERT                0x212UL</div><div class='ctx'> 	#define HWRM_MFG_PRVSN_GET_STATE                  0x213UL</div><div class='hunk'>@@ -418,6 +429,16 @@ struct cmd_nums {</div><div class='ctx'> 	#define HWRM_MFG_SELFTEST_EXEC                    0x217UL</div><div class='ctx'> 	#define HWRM_STAT_GENERIC_QSTATS                  0x218UL</div><div class='ctx'> 	#define HWRM_MFG_PRVSN_EXPORT_CERT                0x219UL</div><div class='add'>+	#define HWRM_STAT_DB_ERROR_QSTATS                 0x21aUL</div><div class='add'>+	#define HWRM_UDCC_QCAPS                           0x258UL</div><div class='add'>+	#define HWRM_UDCC_CFG                             0x259UL</div><div class='add'>+	#define HWRM_UDCC_QCFG                            0x25aUL</div><div class='add'>+	#define HWRM_UDCC_SESSION_CFG                     0x25bUL</div><div class='add'>+	#define HWRM_UDCC_SESSION_QCFG                    0x25cUL</div><div class='add'>+	#define HWRM_UDCC_SESSION_QUERY                   0x25dUL</div><div class='add'>+	#define HWRM_UDCC_COMP_CFG                        0x25eUL</div><div class='add'>+	#define HWRM_UDCC_COMP_QCFG                       0x25fUL</div><div class='add'>+	#define HWRM_UDCC_COMP_QUERY                      0x260UL</div><div class='ctx'> 	#define HWRM_TF                                   0x2bcUL</div><div class='ctx'> 	#define HWRM_TF_VERSION_GET                       0x2bdUL</div><div class='ctx'> 	#define HWRM_TF_SESSION_OPEN                      0x2c6UL</div><div class='hunk'>@@ -582,9 +603,9 @@ struct hwrm_err_output {</div><div class='ctx'> #define HWRM_TARGET_ID_TOOLS 0xFFFD</div><div class='ctx'> #define HWRM_VERSION_MAJOR 1</div><div class='ctx'> #define HWRM_VERSION_MINOR 10</div><div class='del'>-#define HWRM_VERSION_UPDATE 2</div><div class='del'>-#define HWRM_VERSION_RSVD 171</div><div class='del'>-#define HWRM_VERSION_STR "1.10.2.171"</div><div class='add'>+#define HWRM_VERSION_UPDATE 3</div><div class='add'>+#define HWRM_VERSION_RSVD 15</div><div class='add'>+#define HWRM_VERSION_STR "1.10.3.15"</div><div class='ctx'> </div><div class='ctx'> /* hwrm_ver_get_input (size:192b/24B) */</div><div class='ctx'> struct hwrm_ver_get_input {</div><div class='hunk'>@@ -816,7 +837,8 @@ struct hwrm_async_event_cmpl {</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE       0x48UL</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR                       0x4aUL</div><div class='del'>-	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x4bUL</div><div class='add'>+	#define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE             0x4bUL</div><div class='add'>+	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x4cUL</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG                    0xfeUL</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                      0xffUL</div><div class='ctx'> 	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST                           ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR</div><div class='hunk'>@@ -1632,7 +1654,7 @@ struct hwrm_func_qcaps_input {</div><div class='ctx'> 	u8	unused_0[6];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_func_qcaps_output (size:896b/112B) */</div><div class='add'>+/* hwrm_func_qcaps_output (size:1088b/136B) */</div><div class='ctx'> struct hwrm_func_qcaps_output {</div><div class='ctx'> 	__le16	error_code;</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -1736,21 +1758,29 @@ struct hwrm_func_qcaps_output {</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE     0x10UL</div><div class='ctx'> 	__le16	max_key_ctxs_alloc;</div><div class='ctx'> 	__le32	flags_ext2;</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED     0x1UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED                       0x2UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED                      0x4UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED             0x8UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED       0x10UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED              0x20UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED                    0x40UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED                      0x80UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED              0x100UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED             0x200UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED                     0x400UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED                0x800UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED               0x1000UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED          0x2000UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED          0x4000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED      0x1UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED                        0x2UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED                       0x4UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED              0x8UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED        0x10UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED               0x20UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED                     0x40UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED                       0x80UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED               0x100UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED              0x200UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED                      0x400UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED                 0x800UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED                0x1000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED           0x2000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED           0x4000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED        0x8000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED           0x10000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED             0x20000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED     0x40000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED              0x80000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED       0x100000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED                        0x200000UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED          0x400000UL</div><div class='ctx'> 	__le16	tunnel_disable_flag;</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN      0x1UL</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE        0x2UL</div><div class='hunk'>@@ -1760,15 +1790,21 @@ struct hwrm_func_qcaps_output {</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP     0x20UL</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS       0x40UL</div><div class='ctx'> 	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE      0x80UL</div><div class='del'>-	u8	key_xid_partition_cap;</div><div class='del'>-	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_TKC          0x1UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_RKC          0x2UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_QUIC_TKC     0x4UL</div><div class='del'>-	#define FUNC_QCAPS_RESP_KEY_XID_PARTITION_CAP_QUIC_RKC     0x8UL</div><div class='del'>-	u8	unused_1;</div><div class='add'>+	__le16	xid_partition_cap;</div><div class='add'>+	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_TKC     0x1UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_RKC     0x2UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_TKC     0x4UL</div><div class='add'>+	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_RKC     0x8UL</div><div class='ctx'> 	u8	device_serial_number[8];</div><div class='ctx'> 	__le16	ctxs_per_partition;</div><div class='del'>-	u8	unused_2[5];</div><div class='add'>+	u8	unused_2[2];</div><div class='add'>+	__le32	roce_vf_max_av;</div><div class='add'>+	__le32	roce_vf_max_cq;</div><div class='add'>+	__le32	roce_vf_max_mrw;</div><div class='add'>+	__le32	roce_vf_max_qp;</div><div class='add'>+	__le32	roce_vf_max_srq;</div><div class='add'>+	__le32	roce_vf_max_gid;</div><div class='add'>+	u8	unused_3[3];</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1783,7 +1819,7 @@ struct hwrm_func_qcfg_input {</div><div class='ctx'> 	u8	unused_0[6];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_func_qcfg_output (size:1024b/128B) */</div><div class='add'>+/* hwrm_func_qcfg_output (size:1280b/160B) */</div><div class='ctx'> struct hwrm_func_qcfg_output {</div><div class='ctx'> 	__le16	error_code;</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -1892,7 +1928,7 @@ struct hwrm_func_qcfg_output {</div><div class='ctx'> 	__le16	alloc_msix;</div><div class='ctx'> 	__le16	registered_vfs;</div><div class='ctx'> 	__le16	l2_doorbell_bar_size_kb;</div><div class='del'>-	u8	unused_1;</div><div class='add'>+	u8	active_endpoints;</div><div class='ctx'> 	u8	always_1;</div><div class='ctx'> 	__le32	reset_addr_poll;</div><div class='ctx'> 	__le16	legacy_l2_db_size_kb;</div><div class='hunk'>@@ -1952,15 +1988,26 @@ struct hwrm_func_qcfg_output {</div><div class='ctx'> 	u8	kdnet_pcie_function;</div><div class='ctx'> 	__le16	port_kdnet_fid;</div><div class='ctx'> 	u8	unused_5[2];</div><div class='del'>-	__le32	alloc_tx_key_ctxs;</div><div class='del'>-	__le32	alloc_rx_key_ctxs;</div><div class='add'>+	__le32	num_ktls_tx_key_ctxs;</div><div class='add'>+	__le32	num_ktls_rx_key_ctxs;</div><div class='ctx'> 	u8	lag_id;</div><div class='ctx'> 	u8	parif;</div><div class='del'>-	u8	unused_6[5];</div><div class='add'>+	u8	fw_lag_id;</div><div class='add'>+	u8	unused_6;</div><div class='add'>+	__le32	num_quic_tx_key_ctxs;</div><div class='add'>+	__le32	num_quic_rx_key_ctxs;</div><div class='add'>+	__le32	roce_max_av_per_vf;</div><div class='add'>+	__le32	roce_max_cq_per_vf;</div><div class='add'>+	__le32	roce_max_mrw_per_vf;</div><div class='add'>+	__le32	roce_max_qp_per_vf;</div><div class='add'>+	__le32	roce_max_srq_per_vf;</div><div class='add'>+	__le32	roce_max_gid_per_vf;</div><div class='add'>+	__le16	xid_partition_cfg;</div><div class='add'>+	u8	unused_7;</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_func_cfg_input (size:1088b/136B) */</div><div class='add'>+/* hwrm_func_cfg_input (size:1280b/160B) */</div><div class='ctx'> struct hwrm_func_cfg_input {</div><div class='ctx'> 	__le16	req_type;</div><div class='ctx'> 	__le16	cmpl_ring;</div><div class='hunk'>@@ -1996,7 +2043,6 @@ struct hwrm_func_cfg_input {</div><div class='ctx'> 	#define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE          0x10000000UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE             0x20000000UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE            0x40000000UL</div><div class='del'>-	#define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST            0x80000000UL</div><div class='ctx'> 	__le32	enables;</div><div class='ctx'> 	#define FUNC_CFG_REQ_ENABLES_ADMIN_MTU                0x1UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_ENABLES_MRU                      0x2UL</div><div class='hunk'>@@ -2028,8 +2074,8 @@ struct hwrm_func_cfg_input {</div><div class='ctx'> 	#define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW         0x8000000UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_ENABLES_TPID                     0x10000000UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_ENABLES_HOST_MTU                 0x20000000UL</div><div class='del'>-	#define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS              0x40000000UL</div><div class='del'>-	#define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS              0x80000000UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS         0x40000000UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS         0x80000000UL</div><div class='ctx'> 	__le16	admin_mtu;</div><div class='ctx'> 	__le16	mru;</div><div class='ctx'> 	__le16	num_rsscos_ctxs;</div><div class='hunk'>@@ -2139,10 +2185,21 @@ struct hwrm_func_cfg_input {</div><div class='ctx'> 	#define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100</div><div class='ctx'> 	__be16	tpid;</div><div class='ctx'> 	__le16	host_mtu;</div><div class='del'>-	u8	unused_0[4];</div><div class='add'>+	__le32	flags2;</div><div class='add'>+	#define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST     0x1UL</div><div class='add'>+	#define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST     0x2UL</div><div class='ctx'> 	__le32	enables2;</div><div class='del'>-	#define FUNC_CFG_REQ_ENABLES2_KDNET            0x1UL</div><div class='del'>-	#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE     0x2UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_KDNET                   0x1UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE            0x2UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS        0x4UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS        0x8UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF      0x10UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF      0x20UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF     0x40UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF      0x80UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF     0x100UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF     0x200UL</div><div class='add'>+	#define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG       0x400UL</div><div class='ctx'> 	u8	port_kdnet_mode;</div><div class='ctx'> 	#define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL</div><div class='ctx'> 	#define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED  0x1UL</div><div class='hunk'>@@ -2165,7 +2222,18 @@ struct hwrm_func_cfg_input {</div><div class='ctx'> 	__le32	num_ktls_rx_key_ctxs;</div><div class='ctx'> 	__le32	num_quic_tx_key_ctxs;</div><div class='ctx'> 	__le32	num_quic_rx_key_ctxs;</div><div class='del'>-	__le32	unused_2;</div><div class='add'>+	__le32	roce_max_av_per_vf;</div><div class='add'>+	__le32	roce_max_cq_per_vf;</div><div class='add'>+	__le32	roce_max_mrw_per_vf;</div><div class='add'>+	__le32	roce_max_qp_per_vf;</div><div class='add'>+	__le32	roce_max_srq_per_vf;</div><div class='add'>+	__le32	roce_max_gid_per_vf;</div><div class='add'>+	__le16	xid_partition_cfg;</div><div class='add'>+	#define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_TKC     0x1UL</div><div class='add'>+	#define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_RKC     0x2UL</div><div class='add'>+	#define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_TKC     0x4UL</div><div class='add'>+	#define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_RKC     0x8UL</div><div class='add'>+	__le16	unused_2;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* hwrm_func_cfg_output (size:128b/16B) */</div><div class='hunk'>@@ -2604,7 +2672,7 @@ struct hwrm_func_vf_resource_cfg_input {</div><div class='ctx'> 	__le32	max_quic_rx_key_ctxs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */</div><div class='add'>+/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */</div><div class='ctx'> struct hwrm_func_vf_resource_cfg_output {</div><div class='ctx'> 	__le16	error_code;</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -2618,8 +2686,10 @@ struct hwrm_func_vf_resource_cfg_output {</div><div class='ctx'> 	__le16	reserved_vnics;</div><div class='ctx'> 	__le16	reserved_stat_ctx;</div><div class='ctx'> 	__le16	reserved_hw_ring_grps;</div><div class='del'>-	__le32	reserved_tx_key_ctxs;</div><div class='del'>-	__le32	reserved_rx_key_ctxs;</div><div class='add'>+	__le32	reserved_ktls_tx_key_ctxs;</div><div class='add'>+	__le32	reserved_ktls_rx_key_ctxs;</div><div class='add'>+	__le32	reserved_quic_tx_key_ctxs;</div><div class='add'>+	__le32	reserved_quic_rx_key_ctxs;</div><div class='ctx'> 	u8	unused_0[7];</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='hunk'>@@ -3441,7 +3511,8 @@ struct hwrm_func_ptp_cfg_input {</div><div class='ctx'> 	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K   0x1UL</div><div class='ctx'> 	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K   0x2UL</div><div class='ctx'> 	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M  0x3UL</div><div class='del'>-	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M</div><div class='add'>+	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M  0x4UL</div><div class='add'>+	#define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M</div><div class='ctx'> 	u8	unused_0[3];</div><div class='ctx'> 	__le32	ptp_freq_adj_ext_period;</div><div class='ctx'> 	__le32	ptp_freq_adj_ext_up;</div><div class='hunk'>@@ -3627,28 +3698,28 @@ struct hwrm_func_backing_store_qcfg_v2_input {</div><div class='ctx'> 	__le16	target_id;</div><div class='ctx'> 	__le64	resp_addr;</div><div class='ctx'> 	__le16	type;</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP            0x0UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ           0x1UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ            0x2UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC          0x3UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT          0x4UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING   0x5UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING   0x6UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV          0xeUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM           0xfUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC           0x13UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC           0x14UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING   0x15UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC      0x1aUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC      0x1bUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE     0x1cUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID       0xffffUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP                  0x0UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ                 0x1UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ                  0x2UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC                0x3UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT                0x4UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING         0x5UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING         0x6UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV                0xeUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM                 0xfUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC                 0x13UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC                 0x14UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING         0x15UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW        0x16UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW        0x17UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW       0x18UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW        0x19UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC            0x1aUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC            0x1bUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE           0x1cUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID             0xffffUL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST               FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID</div><div class='ctx'> 	__le16	instance;</div><div class='ctx'> 	u8	rsvd[4];</div><div class='ctx'> };</div><div class='hunk'>@@ -3744,6 +3815,15 @@ struct mrav_split_entries {</div><div class='ctx'> 	__le32	rsvd2[2];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* ts_split_entries (size:128b/16B) */</div><div class='add'>+struct ts_split_entries {</div><div class='add'>+	__le32	region_num_entries;</div><div class='add'>+	u8	tsid;</div><div class='add'>+	u8	lkup_static_bkt_cnt_exp[2];</div><div class='add'>+	u8	rsvd;</div><div class='add'>+	__le32	rsvd2[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */</div><div class='ctx'> struct hwrm_func_backing_store_qcaps_v2_input {</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -3761,8 +3841,8 @@ struct hwrm_func_backing_store_qcaps_v2_input {</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING   0x6UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV          0xeUL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM           0xfUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC           0x13UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC           0x14UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_TKC      0x13UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_RKC      0x14UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING   0x15UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL</div><div class='hunk'>@@ -3793,8 +3873,8 @@ struct hwrm_func_backing_store_qcaps_v2_output {</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING   0x6UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV          0xeUL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM           0xfUL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC           0x13UL</div><div class='del'>-	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC           0x14UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_TKC      0x13UL</div><div class='add'>+	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_RKC      0x14UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING   0x15UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW  0x16UL</div><div class='ctx'> 	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW  0x17UL</div><div class='hunk'>@@ -3838,56 +3918,55 @@ struct hwrm_func_backing_store_qcaps_v2_output {</div><div class='ctx'> </div><div class='ctx'> /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */</div><div class='ctx'> struct hwrm_func_dbr_pacing_qcfg_input {</div><div class='del'>-	__le16  req_type;</div><div class='del'>-	__le16  cmpl_ring;</div><div class='del'>-	__le16  seq_id;</div><div class='del'>-	__le16  target_id;</div><div class='del'>-	__le64  resp_addr;</div><div class='add'>+	__le16	req_type;</div><div class='add'>+	__le16	cmpl_ring;</div><div class='add'>+	__le16	seq_id;</div><div class='add'>+	__le16	target_id;</div><div class='add'>+	__le64	resp_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */</div><div class='ctx'> struct hwrm_func_dbr_pacing_qcfg_output {</div><div class='del'>-	__le16  error_code;</div><div class='del'>-	__le16  req_type;</div><div class='del'>-	__le16  seq_id;</div><div class='del'>-	__le16  resp_len;</div><div class='del'>-	u8      flags;</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED     0x1UL</div><div class='del'>-	u8      unused_0[7];</div><div class='del'>-	__le32  dbr_stat_db_fifo_reg;</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK    0x3UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT     0</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG  0x0UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC       0x1UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0      0x2UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1      0x3UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST     \</div><div class='del'>-		FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK          0xfffffffcUL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT           2</div><div class='del'>-	__le32  dbr_stat_db_fifo_reg_watermark_mask;</div><div class='del'>-	u8      dbr_stat_db_fifo_reg_watermark_shift;</div><div class='del'>-	u8      unused_1[3];</div><div class='del'>-	__le32  dbr_stat_db_fifo_reg_fifo_room_mask;</div><div class='del'>-	u8      dbr_stat_db_fifo_reg_fifo_room_shift;</div><div class='del'>-	u8      unused_2[3];</div><div class='del'>-	__le32  dbr_throttling_aeq_arm_reg;</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK    0x3UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT     0</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG  0x0UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC       0x1UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0      0x2UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1      0x3UL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST	\</div><div class='del'>-		FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK          0xfffffffcUL</div><div class='del'>-#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT           2</div><div class='del'>-	u8      dbr_throttling_aeq_arm_reg_val;</div><div class='del'>-	u8      unused_3[7];</div><div class='del'>-	__le32  primary_nq_id;</div><div class='del'>-	__le32  pacing_threshold;</div><div class='del'>-	u8      unused_4[7];</div><div class='del'>-	u8      valid;</div><div class='add'>+	__le16	error_code;</div><div class='add'>+	__le16	req_type;</div><div class='add'>+	__le16	seq_id;</div><div class='add'>+	__le16	resp_len;</div><div class='add'>+	u8	flags;</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED     0x1UL</div><div class='add'>+	u8	unused_0[7];</div><div class='add'>+	__le32	dbr_stat_db_fifo_reg;</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK    0x3UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT     0</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG  0x0UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC       0x1UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0      0x2UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1      0x3UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST     FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK          0xfffffffcUL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT           2</div><div class='add'>+	__le32	dbr_stat_db_fifo_reg_watermark_mask;</div><div class='add'>+	u8	dbr_stat_db_fifo_reg_watermark_shift;</div><div class='add'>+	u8	unused_1[3];</div><div class='add'>+	__le32	dbr_stat_db_fifo_reg_fifo_room_mask;</div><div class='add'>+	u8	dbr_stat_db_fifo_reg_fifo_room_shift;</div><div class='add'>+	u8	unused_2[3];</div><div class='add'>+	__le32	dbr_throttling_aeq_arm_reg;</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK    0x3UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT     0</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG  0x0UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC       0x1UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0      0x2UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1      0x3UL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST     FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK          0xfffffffcUL</div><div class='add'>+	#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT           2</div><div class='add'>+	u8	dbr_throttling_aeq_arm_reg_val;</div><div class='add'>+	u8	unused_3[3];</div><div class='add'>+	__le32	dbr_stat_db_max_fifo_depth;</div><div class='add'>+	__le32	primary_nq_id;</div><div class='add'>+	__le32	pacing_threshold;</div><div class='add'>+	u8	unused_4[7];</div><div class='add'>+	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* hwrm_func_drv_if_change_input (size:192b/24B) */</div><div class='hunk'>@@ -3915,7 +3994,7 @@ struct hwrm_func_drv_if_change_output {</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_port_phy_cfg_input (size:448b/56B) */</div><div class='add'>+/* hwrm_port_phy_cfg_input (size:512b/64B) */</div><div class='ctx'> struct hwrm_port_phy_cfg_input {</div><div class='ctx'> 	__le16	req_type;</div><div class='ctx'> 	__le16	cmpl_ring;</div><div class='hunk'>@@ -3960,6 +4039,8 @@ struct hwrm_port_phy_cfg_input {</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER                  0x400UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2            0x2000UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK        0x4000UL</div><div class='ctx'> 	__le16	port_id;</div><div class='ctx'> 	__le16	force_link_speed;</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL</div><div class='hunk'>@@ -3990,7 +4071,9 @@ struct hwrm_port_phy_cfg_input {</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL</div><div class='del'>-	u8	unused_0;</div><div class='add'>+	u8	mgmt_flag;</div><div class='add'>+	#define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE     0x1UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID       0x80UL</div><div class='ctx'> 	__le16	auto_link_speed;</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL</div><div class='hunk'>@@ -4054,7 +4137,36 @@ struct hwrm_port_phy_cfg_input {</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL</div><div class='ctx'> 	#define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL</div><div class='del'>-	u8	unused_2[2];</div><div class='add'>+	__le16	force_link_speeds2;</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB            0xaUL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB           0x64UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB           0xfaUL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB           0x190UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB           0x1f4UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB          0x3e8UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112</div><div class='add'>+	__le16	auto_link_speeds2_mask;</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB                0x1UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB               0x2UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB               0x4UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB               0x8UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB               0x10UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB              0x20UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56       0x40UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56      0x80UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56      0x100UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56      0x200UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112     0x400UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112     0x800UL</div><div class='add'>+	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112     0x1000UL</div><div class='add'>+	u8	unused_2[6];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* hwrm_port_phy_cfg_output (size:128b/16B) */</div><div class='hunk'>@@ -4104,7 +4216,8 @@ struct hwrm_port_phy_qcfg_output {</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT                 0</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ                   0x0UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4                  0x1UL</div><div class='del'>-	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST                 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112              0x2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST                 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                 0xf0UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                  4</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL &lt;&lt; 4)</div><div class='hunk'>@@ -4127,6 +4240,7 @@ struct hwrm_port_phy_qcfg_output {</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB</div><div class='ctx'> 	u8	duplex_cfg;</div><div class='hunk'>@@ -4270,7 +4384,23 @@ struct hwrm_port_phy_qcfg_output {</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2     0x25UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2     0x26UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2     0x27UL</div><div class='del'>-	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR      0x28UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR      0x29UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR      0x2aUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER      0x2bUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2     0x2cUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2     0x2dUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2     0x2eUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2     0x2fUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8     0x30UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8     0x31UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8     0x32UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8     0x33UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4     0x34UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4     0x35UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4     0x36UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4     0x37UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4</div><div class='ctx'> 	u8	media_type;</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL</div><div class='hunk'>@@ -4366,6 +4496,7 @@ struct hwrm_port_phy_qcfg_output {</div><div class='ctx'> 	u8	option_flags;</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN     0x2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED     0x4UL</div><div class='ctx'> 	char	phy_vendor_name[16];</div><div class='ctx'> 	char	phy_vendor_partnumber[16];</div><div class='ctx'> 	__le16	support_pam4_speeds;</div><div class='hunk'>@@ -4387,7 +4518,53 @@ struct hwrm_port_phy_qcfg_output {</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB     0x4UL</div><div class='ctx'> 	u8	link_down_reason;</div><div class='ctx'> 	#define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF     0x1UL</div><div class='del'>-	u8	unused_0[7];</div><div class='add'>+	__le16	support_speeds2;</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB                0x1UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB               0x2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB               0x4UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB               0x8UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB               0x10UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB              0x20UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56       0x40UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56      0x80UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56      0x100UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56      0x200UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112     0x400UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112     0x800UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112     0x1000UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112     0x2000UL</div><div class='add'>+	__le16	force_link_speeds2;</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB            0xaUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB           0x64UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB           0xfaUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB           0x190UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB           0x1f4UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB          0x3e8UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56   0x1f5UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56  0x3e9UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56  0x7d1UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56  0xfa1UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112</div><div class='add'>+	__le16	auto_link_speeds2;</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB                0x1UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB               0x2UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB               0x4UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB               0x8UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB               0x10UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB              0x20UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56       0x40UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56      0x80UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56      0x100UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56      0x200UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112     0x400UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112     0x800UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112     0x1000UL</div><div class='add'>+	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112     0x2000UL</div><div class='add'>+	u8	active_lanes;</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -4426,6 +4603,7 @@ struct hwrm_port_mac_cfg_input {</div><div class='ctx'> 	#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL</div><div class='ctx'> 	#define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB               0x200UL</div><div class='ctx'> 	#define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE                  0x400UL</div><div class='add'>+	#define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL               0x800UL</div><div class='ctx'> 	__le16	port_id;</div><div class='ctx'> 	u8	ipg;</div><div class='ctx'> 	u8	lpbk;</div><div class='hunk'>@@ -4459,7 +4637,12 @@ struct hwrm_port_mac_cfg_input {</div><div class='ctx'> 	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           5</div><div class='ctx'> 	u8	unused_0[3];</div><div class='ctx'> 	__le32	ptp_freq_adj_ppb;</div><div class='del'>-	u8	unused_1[4];</div><div class='add'>+	u8	unused_1[3];</div><div class='add'>+	u8	ptp_load_control;</div><div class='add'>+	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE      0x0UL</div><div class='add'>+	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL</div><div class='add'>+	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL</div><div class='add'>+	#define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST     PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT</div><div class='ctx'> 	__le64	ptp_adj_phase;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -4504,6 +4687,7 @@ struct hwrm_port_mac_ptp_qcfg_output {</div><div class='ctx'> 	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS                         0x8UL</div><div class='ctx'> 	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK     0x10UL</div><div class='ctx'> 	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED                      0x20UL</div><div class='add'>+	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME                        0x40UL</div><div class='ctx'> 	u8	unused_0[3];</div><div class='ctx'> 	__le32	rx_ts_reg_off_lower;</div><div class='ctx'> 	__le32	rx_ts_reg_off_upper;</div><div class='hunk'>@@ -4968,7 +5152,7 @@ struct hwrm_port_phy_qcaps_input {</div><div class='ctx'> 	u8	unused_0[6];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_port_phy_qcaps_output (size:256b/32B) */</div><div class='add'>+/* hwrm_port_phy_qcaps_output (size:320b/40B) */</div><div class='ctx'> struct hwrm_port_phy_qcaps_output {</div><div class='ctx'> 	__le16	error_code;</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -5051,7 +5235,40 @@ struct hwrm_port_phy_qcaps_output {</div><div class='ctx'> 	#define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED       0x1UL</div><div class='ctx'> 	#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED         0x2UL</div><div class='ctx'> 	#define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED     0x4UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED       0x8UL</div><div class='ctx'> 	u8	internal_port_cnt;</div><div class='add'>+	u8	unused_0;</div><div class='add'>+	__le16	supported_speeds2_force_mode;</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB                0x1UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB               0x2UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB               0x4UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB               0x8UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB               0x10UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB              0x20UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56       0x40UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56      0x80UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56      0x100UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56      0x200UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112     0x400UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112     0x800UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112     0x1000UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112     0x2000UL</div><div class='add'>+	__le16	supported_speeds2_auto_mode;</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB                0x1UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB               0x2UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB               0x4UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB               0x8UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB               0x10UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB              0x20UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56       0x40UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56      0x80UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56      0x100UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56      0x200UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112     0x400UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112     0x800UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112     0x1000UL</div><div class='add'>+	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112     0x2000UL</div><div class='add'>+	u8	unused_1[3];</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -5472,6 +5689,30 @@ struct hwrm_port_led_qcaps_output {</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* hwrm_port_mac_qcaps_input (size:192b/24B) */</div><div class='add'>+struct hwrm_port_mac_qcaps_input {</div><div class='add'>+	__le16	req_type;</div><div class='add'>+	__le16	cmpl_ring;</div><div class='add'>+	__le16	seq_id;</div><div class='add'>+	__le16	target_id;</div><div class='add'>+	__le64	resp_addr;</div><div class='add'>+	__le16	port_id;</div><div class='add'>+	u8	unused_0[6];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* hwrm_port_mac_qcaps_output (size:128b/16B) */</div><div class='add'>+struct hwrm_port_mac_qcaps_output {</div><div class='add'>+	__le16	error_code;</div><div class='add'>+	__le16	req_type;</div><div class='add'>+	__le16	seq_id;</div><div class='add'>+	__le16	resp_len;</div><div class='add'>+	u8	flags;</div><div class='add'>+	#define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED     0x1UL</div><div class='add'>+	#define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED        0x2UL</div><div class='add'>+	u8	unused_0[6];</div><div class='add'>+	u8	valid;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* hwrm_queue_qportcfg_input (size:192b/24B) */</div><div class='ctx'> struct hwrm_queue_qportcfg_input {</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -7488,7 +7729,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input {</div><div class='ctx'> 	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD    0xffUL</div><div class='ctx'> 	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD</div><div class='ctx'> 	__le16	dst_id;</div><div class='del'>-	__le16	mirror_vnic_id;</div><div class='add'>+	__le16	rfs_ring_tbl_idx;</div><div class='ctx'> 	u8	tunnel_type;</div><div class='ctx'> 	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL</div><div class='ctx'> 	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL</div><div class='hunk'>@@ -8201,6 +8442,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {</div><div class='ctx'> 	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED               0x40000UL</div><div class='ctx'> 	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED                     0x80000UL</div><div class='ctx'> 	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED        0x100000UL</div><div class='add'>+	#define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED                0x200000UL</div><div class='ctx'> 	u8	unused_0[3];</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='hunk'>@@ -8223,7 +8465,8 @@ struct hwrm_tunnel_dst_port_query_input {</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI        0xeUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6         0xfUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL</div><div class='del'>-	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE</div><div class='add'>+	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE          0x11UL</div><div class='add'>+	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE</div><div class='ctx'> 	u8	tunnel_next_proto;</div><div class='ctx'> 	u8	unused_0[6];</div><div class='ctx'> };</div><div class='hunk'>@@ -8245,7 +8488,10 @@ struct hwrm_tunnel_dst_port_query_output {</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5     0x20UL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6     0x40UL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7     0x80UL</div><div class='del'>-	u8	unused_0[2];</div><div class='add'>+	u8	status;</div><div class='add'>+	#define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL     0x1UL</div><div class='add'>+	#define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL     0x2UL</div><div class='add'>+	u8	unused_0;</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -8267,7 +8513,8 @@ struct hwrm_tunnel_dst_port_alloc_input {</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI        0xeUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6         0xfUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL</div><div class='del'>-	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE</div><div class='add'>+	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE          0x11UL</div><div class='add'>+	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE</div><div class='ctx'> 	u8	tunnel_next_proto;</div><div class='ctx'> 	__be16	tunnel_dst_port_val;</div><div class='ctx'> 	u8	unused_0[4];</div><div class='hunk'>@@ -8284,7 +8531,8 @@ struct hwrm_tunnel_dst_port_alloc_output {</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS         0x0UL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED   0x1UL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL</div><div class='del'>-	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST           TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE</div><div class='add'>+	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED     0x3UL</div><div class='add'>+	#define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST           TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED</div><div class='ctx'> 	u8	upar_in_use;</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0     0x1UL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1     0x2UL</div><div class='hunk'>@@ -8316,7 +8564,8 @@ struct hwrm_tunnel_dst_port_free_input {</div><div class='ctx'> 	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI        0xeUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6         0xfUL</div><div class='ctx'> 	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE    0x10UL</div><div class='del'>-	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE</div><div class='add'>+	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE          0x11UL</div><div class='add'>+	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE</div><div class='ctx'> 	u8	tunnel_next_proto;</div><div class='ctx'> 	__le16	tunnel_dst_port_id;</div><div class='ctx'> 	u8	unused_0[4];</div><div class='hunk'>@@ -9717,7 +9966,7 @@ struct hwrm_nvm_get_dev_info_input {</div><div class='ctx'> 	__le64	resp_addr;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* hwrm_nvm_get_dev_info_output (size:640b/80B) */</div><div class='add'>+/* hwrm_nvm_get_dev_info_output (size:704b/88B) */</div><div class='ctx'> struct hwrm_nvm_get_dev_info_output {</div><div class='ctx'> 	__le16	error_code;</div><div class='ctx'> 	__le16	req_type;</div><div class='hunk'>@@ -9747,6 +9996,10 @@ struct hwrm_nvm_get_dev_info_output {</div><div class='ctx'> 	__le16	roce_fw_minor;</div><div class='ctx'> 	__le16	roce_fw_build;</div><div class='ctx'> 	__le16	roce_fw_patch;</div><div class='add'>+	__le16	netctrl_fw_major;</div><div class='add'>+	__le16	netctrl_fw_minor;</div><div class='add'>+	__le16	netctrl_fw_build;</div><div class='add'>+	__le16	netctrl_fw_patch;</div><div class='ctx'> 	u8	unused_0[7];</div><div class='ctx'> 	u8	valid;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c<br/>index f3886710e778..adad188e38b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c</a></div><div class='hunk'>@@ -129,7 +129,7 @@ static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)</div><div class='ctx'> 	}</div><div class='ctx'> 	resp = hwrm_req_hold(bp, req);</div><div class='ctx'> </div><div class='del'>-	rc = hwrm_req_send(bp, req);</div><div class='add'>+	rc = hwrm_req_send_silent(bp, req);</div><div class='ctx'> 	if (!rc)</div><div class='ctx'> 		*ts = le64_to_cpu(resp-&gt;ptp_msg_ts);</div><div class='ctx'> 	hwrm_req_drop(bp, req);</div><div class='hunk'>@@ -319,15 +319,17 @@ static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)</div><div class='ctx'> 	return hwrm_req_send(bp, req);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)</div><div class='add'>+int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_ptp_cfg *ptp = bp-&gt;ptp_cfg;</div><div class='ctx'> 	struct hwrm_port_mac_cfg_input *req;</div><div class='add'>+	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (!ptp || !ptp-&gt;tstamp_filters)</div><div class='del'>-		return;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='del'>-	if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG))</div><div class='add'>+	rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);</div><div class='add'>+	if (rc)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	if (!(bp-&gt;fw_cap &amp; BNXT_FW_CAP_RX_ALL_PKT_TS) &amp;&amp; (ptp-&gt;tstamp_filters &amp;</div><div class='hunk'>@@ -342,15 +344,17 @@ void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)</div><div class='ctx'> 	req-&gt;enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);</div><div class='ctx'> 	req-&gt;rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp-&gt;rxctl);</div><div class='ctx'> </div><div class='del'>-	if (!hwrm_req_send(bp, req)) {</div><div class='add'>+	rc = hwrm_req_send(bp, req);</div><div class='add'>+	if (!rc) {</div><div class='ctx'> 		bp-&gt;ptp_all_rx_tstamp = !!(ptp-&gt;tstamp_filters &amp;</div><div class='ctx'> 					   PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);</div><div class='del'>-		return;</div><div class='add'>+		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> 	ptp-&gt;tstamp_filters = 0;</div><div class='ctx'> out:</div><div class='ctx'> 	bp-&gt;ptp_all_rx_tstamp = 0;</div><div class='ctx'> 	netdev_warn(bp-&gt;dev, "Failed to configure HW packet timestamp filters\n");</div><div class='add'>+	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void bnxt_ptp_reapply_pps(struct bnxt *bp)</div><div class='hunk'>@@ -494,7 +498,6 @@ static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)</div><div class='ctx'> {</div><div class='ctx'> 	struct bnxt_ptp_cfg *ptp = bp-&gt;ptp_cfg;</div><div class='ctx'> 	u32 flags = 0;</div><div class='del'>-	int rc = 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (ptp-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_ALL:</div><div class='hunk'>@@ -519,19 +522,7 @@ static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)</div><div class='ctx'> </div><div class='ctx'> 	ptp-&gt;tstamp_filters = flags;</div><div class='ctx'> </div><div class='del'>-	if (netif_running(bp-&gt;dev)) {</div><div class='del'>-		if (ptp-&gt;rx_filter == HWTSTAMP_FILTER_ALL) {</div><div class='del'>-			rc = bnxt_close_nic(bp, false, false);</div><div class='del'>-			if (!rc)</div><div class='del'>-				rc = bnxt_open_nic(bp, false, false);</div><div class='del'>-		} else {</div><div class='del'>-			bnxt_ptp_cfg_tstamp_filters(bp);</div><div class='del'>-		}</div><div class='del'>-		if (!rc &amp;&amp; !ptp-&gt;tstamp_filters)</div><div class='del'>-			rc = -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='add'>+	return bnxt_ptp_cfg_tstamp_filters(bp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)</div><div class='hunk'>@@ -650,7 +641,7 @@ static int bnxt_map_ptp_regs(struct bnxt *bp)</div><div class='ctx'> 	int rc, i;</div><div class='ctx'> </div><div class='ctx'> 	reg_arr = ptp-&gt;refclk_regs;</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (BNXT_CHIP_P5(bp)) {</div><div class='ctx'> 		rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);</div><div class='ctx'> 		if (rc)</div><div class='ctx'> 			return rc;</div><div class='hunk'>@@ -693,8 +684,8 @@ static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)</div><div class='ctx'> 		timestamp.hwtstamp = ns_to_ktime(ns);</div><div class='ctx'> 		skb_tstamp_tx(ptp-&gt;tx_skb, &amp;timestamp);</div><div class='ctx'> 	} else {</div><div class='del'>-		netdev_err(bp-&gt;dev, "TS query for TX timer failed rc = %x\n",</div><div class='del'>-			   rc);</div><div class='add'>+		netdev_WARN_ONCE(bp-&gt;dev,</div><div class='add'>+				 "TS query for TX timer failed rc = %x\n", rc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev_kfree_skb_any(ptp-&gt;tx_skb);</div><div class='hunk'>@@ -967,7 +958,7 @@ int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)</div><div class='ctx'> 		rc = err;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (BNXT_CHIP_P5(bp)) {</div><div class='ctx'> 		spin_lock_bh(&amp;ptp-&gt;ptp_lock);</div><div class='ctx'> 		bnxt_refclk_read(bp, NULL, &amp;ptp-&gt;current_time);</div><div class='ctx'> 		WRITE_ONCE(ptp-&gt;old_time, ptp-&gt;current_time);</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h<br/>index 34162e07a119..fce8dc39a7d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h</a></div><div class='hunk'>@@ -137,7 +137,7 @@ do {						\</div><div class='ctx'> int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off);</div><div class='ctx'> void bnxt_ptp_update_current_time(struct bnxt *bp);</div><div class='ctx'> void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);</div><div class='del'>-void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp);</div><div class='add'>+int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp);</div><div class='ctx'> void bnxt_ptp_reapply_pps(struct bnxt *bp);</div><div class='ctx'> int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);</div><div class='ctx'> int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c<br/>index c722b3b41730..175192ebaa77 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c</a></div><div class='hunk'>@@ -536,7 +536,7 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs, bool reset)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS) {</div><div class='ctx'> 		vf_msix = hw_resc-&gt;max_nqs - bnxt_nq_rings_in_use(bp);</div><div class='ctx'> 		vf_ring_grps = 0;</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -565,7 +565,7 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs, bool reset)</div><div class='ctx'> 		req-&gt;min_l2_ctxs = cpu_to_le16(min);</div><div class='ctx'> 		req-&gt;min_vnics = cpu_to_le16(min);</div><div class='ctx'> 		req-&gt;min_stat_ctx = cpu_to_le16(min);</div><div class='del'>-		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5))</div><div class='add'>+		if (!(bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS))</div><div class='ctx'> 			req-&gt;min_hw_ring_grps = cpu_to_le16(min);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		vf_cp_rings /= num_vfs;</div><div class='hunk'>@@ -602,7 +602,7 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs, bool reset)</div><div class='ctx'> 	req-&gt;max_stat_ctx = cpu_to_le16(vf_stat_ctx);</div><div class='ctx'> 	req-&gt;max_hw_ring_grps = cpu_to_le16(vf_ring_grps);</div><div class='ctx'> 	req-&gt;max_rsscos_ctx = cpu_to_le16(vf_rss);</div><div class='del'>-	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+	if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 		req-&gt;max_msix = cpu_to_le16(vf_msix / num_vfs);</div><div class='ctx'> </div><div class='ctx'> 	hwrm_req_hold(bp, req);</div><div class='hunk'>@@ -630,7 +630,7 @@ static int bnxt_hwrm_func_vf_resc_cfg(struct bnxt *bp, int num_vfs, bool reset)</div><div class='ctx'> 			le16_to_cpu(req-&gt;min_rsscos_ctx) * n;</div><div class='ctx'> 		hw_resc-&gt;max_stat_ctxs -= le16_to_cpu(req-&gt;min_stat_ctx) * n;</div><div class='ctx'> 		hw_resc-&gt;max_vnics -= le16_to_cpu(req-&gt;min_vnics) * n;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5)</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='ctx'> 			hw_resc-&gt;max_nqs -= vf_msix;</div><div class='ctx'> </div><div class='ctx'> 		rc = pf-&gt;active_vfs;</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c<br/>index 38d89d80b4a9..273c9ba48f09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c</a></div><div class='hunk'>@@ -2075,6 +2075,7 @@ destroy_flow_table:</div><div class='ctx'> 	rhashtable_destroy(&amp;tc_info-&gt;flow_table);</div><div class='ctx'> free_tc_info:</div><div class='ctx'> 	kfree(tc_info);</div><div class='add'>+	bp-&gt;tc_info = NULL;</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c<br/>index 6ba2b9398633..93f9bd55020f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c</a></div><div class='hunk'>@@ -42,13 +42,10 @@ static void bnxt_fill_msix_vecs(struct bnxt *bp, struct bnxt_msix_entry *ent)</div><div class='ctx'> 	for (i = 0; i &lt; num_msix; i++) {</div><div class='ctx'> 		ent[i].vector = bp-&gt;irq_tbl[idx + i].vector;</div><div class='ctx'> 		ent[i].ring_idx = idx + i;</div><div class='del'>-		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5) {</div><div class='del'>-			ent[i].db_offset = DB_PF_OFFSET_P5;</div><div class='del'>-			if (BNXT_VF(bp))</div><div class='del'>-				ent[i].db_offset = DB_VF_OFFSET_P5;</div><div class='del'>-		} else {</div><div class='add'>+		if (bp-&gt;flags &amp; BNXT_FLAG_CHIP_P5_PLUS)</div><div class='add'>+			ent[i].db_offset = bp-&gt;db_offset;</div><div class='add'>+		else</div><div class='ctx'> 			ent[i].db_offset = (idx + i) * 0x80;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -333,6 +330,7 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp)</div><div class='ctx'> 	edev-&gt;pdev = bp-&gt;pdev;</div><div class='ctx'> 	edev-&gt;l2_db_size = bp-&gt;db_size;</div><div class='ctx'> 	edev-&gt;l2_db_size_nc = bp-&gt;db_size;</div><div class='add'>+	edev-&gt;l2_db_offset = bp-&gt;db_offset;</div><div class='ctx'> </div><div class='ctx'> 	if (bp-&gt;flags &amp; BNXT_FLAG_ROCEV1_CAP)</div><div class='ctx'> 		edev-&gt;flags |= BNXT_EN_FLAG_ROCEV1_CAP;</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h<br/>index 6ff77f082e6c..b9e73de14b57 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h</a></div><div class='hunk'>@@ -73,6 +73,10 @@ struct bnxt_en_dev {</div><div class='ctx'> 							 * bytes mapped as non-</div><div class='ctx'> 							 * cacheable.</div><div class='ctx'> 							 */</div><div class='add'>+	int				l2_db_offset;	/* Doorbell offset in</div><div class='add'>+							 * bytes within</div><div class='add'>+							 * l2_db_size_nc.</div><div class='add'>+							 */</div><div class='ctx'> 	u16				chip_num;</div><div class='ctx'> 	u16				hw_ring_stats_size;</div><div class='ctx'> 	u16				pf_port_id;</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c b/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c<br/>index 96f5ca778c67..c2b25fc623ec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c</a></div><div class='hunk'>@@ -42,24 +42,23 @@ struct bnxt_sw_tx_bd *bnxt_xmit_bd(struct bnxt *bp,</div><div class='ctx'> </div><div class='ctx'> 	/* fill up the first buffer */</div><div class='ctx'> 	prod = txr-&gt;tx_prod;</div><div class='del'>-	tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+	tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 	tx_buf-&gt;nr_frags = num_frags;</div><div class='ctx'> 	if (xdp)</div><div class='ctx'> 		tx_buf-&gt;page = virt_to_head_page(xdp-&gt;data);</div><div class='ctx'> </div><div class='del'>-	txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+	txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> 	flags = (len &lt;&lt; TX_BD_LEN_SHIFT) |</div><div class='ctx'> 		((num_frags + 1) &lt;&lt; TX_BD_FLAGS_BD_CNT_SHIFT) |</div><div class='ctx'> 		bnxt_lhint_arr[len &gt;&gt; 9];</div><div class='ctx'> 	txbd-&gt;tx_bd_len_flags_type = cpu_to_le32(flags);</div><div class='del'>-	txbd-&gt;tx_bd_opaque = prod;</div><div class='add'>+	txbd-&gt;tx_bd_opaque = SET_TX_OPAQUE(bp, txr, prod, 1 + num_frags);</div><div class='ctx'> 	txbd-&gt;tx_bd_haddr = cpu_to_le64(mapping);</div><div class='ctx'> </div><div class='ctx'> 	/* now let us fill up the frags into the next buffers */</div><div class='ctx'> 	for (i = 0; i &lt; num_frags ; i++) {</div><div class='ctx'> 		skb_frag_t *frag = &amp;sinfo-&gt;frags[i];</div><div class='ctx'> 		struct bnxt_sw_tx_bd *frag_tx_buf;</div><div class='del'>-		struct pci_dev *pdev = bp-&gt;pdev;</div><div class='ctx'> 		dma_addr_t frag_mapping;</div><div class='ctx'> 		int frag_len;</div><div class='ctx'> </div><div class='hunk'>@@ -67,22 +66,16 @@ struct bnxt_sw_tx_bd *bnxt_xmit_bd(struct bnxt *bp,</div><div class='ctx'> 		WRITE_ONCE(txr-&gt;tx_prod, prod);</div><div class='ctx'> </div><div class='ctx'> 		/* first fill up the first buffer */</div><div class='del'>-		frag_tx_buf = &amp;txr-&gt;tx_buf_ring[prod];</div><div class='add'>+		frag_tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, prod)];</div><div class='ctx'> 		frag_tx_buf-&gt;page = skb_frag_page(frag);</div><div class='ctx'> </div><div class='del'>-		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];</div><div class='add'>+		txbd = &amp;txr-&gt;tx_desc_ring[TX_RING(bp, prod)][TX_IDX(prod)];</div><div class='ctx'> </div><div class='ctx'> 		frag_len = skb_frag_size(frag);</div><div class='del'>-		frag_mapping = skb_frag_dma_map(&amp;pdev-&gt;dev, frag, 0,</div><div class='del'>-						frag_len, DMA_TO_DEVICE);</div><div class='del'>-</div><div class='del'>-		if (unlikely(dma_mapping_error(&amp;pdev-&gt;dev, frag_mapping)))</div><div class='del'>-			return NULL;</div><div class='del'>-</div><div class='del'>-		dma_unmap_addr_set(frag_tx_buf, mapping, frag_mapping);</div><div class='del'>-</div><div class='ctx'> 		flags = frag_len &lt;&lt; TX_BD_LEN_SHIFT;</div><div class='ctx'> 		txbd-&gt;tx_bd_len_flags_type = cpu_to_le32(flags);</div><div class='add'>+		frag_mapping = page_pool_get_dma_addr(skb_frag_page(frag)) +</div><div class='add'>+			       skb_frag_off(frag);</div><div class='ctx'> 		txbd-&gt;tx_bd_haddr = cpu_to_le64(frag_mapping);</div><div class='ctx'> </div><div class='ctx'> 		len = frag_len;</div><div class='hunk'>@@ -127,20 +120,20 @@ static void __bnxt_xmit_xdp_redirect(struct bnxt *bp,</div><div class='ctx'> </div><div class='ctx'> void bnxt_tx_int_xdp(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='ctx'> {</div><div class='del'>-	struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring;</div><div class='add'>+	struct bnxt_tx_ring_info *txr = bnapi-&gt;tx_ring[0];</div><div class='ctx'> 	struct bnxt_rx_ring_info *rxr = bnapi-&gt;rx_ring;</div><div class='add'>+	u16 tx_hw_cons = txr-&gt;tx_hw_cons;</div><div class='ctx'> 	bool rx_doorbell_needed = false;</div><div class='del'>-	int nr_pkts = bnapi-&gt;tx_pkts;</div><div class='ctx'> 	struct bnxt_sw_tx_bd *tx_buf;</div><div class='ctx'> 	u16 tx_cons = txr-&gt;tx_cons;</div><div class='ctx'> 	u16 last_tx_cons = tx_cons;</div><div class='del'>-	int i, j, frags;</div><div class='add'>+	int j, frags;</div><div class='ctx'> </div><div class='ctx'> 	if (!budget)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; nr_pkts; i++) {</div><div class='del'>-		tx_buf = &amp;txr-&gt;tx_buf_ring[tx_cons];</div><div class='add'>+	while (RING_TX(bp, tx_cons) != tx_hw_cons) {</div><div class='add'>+		tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, tx_cons)];</div><div class='ctx'> </div><div class='ctx'> 		if (tx_buf-&gt;action == XDP_REDIRECT) {</div><div class='ctx'> 			struct pci_dev *pdev = bp-&gt;pdev;</div><div class='hunk'>@@ -160,20 +153,20 @@ void bnxt_tx_int_xdp(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)</div><div class='ctx'> 			frags = tx_buf-&gt;nr_frags;</div><div class='ctx'> 			for (j = 0; j &lt; frags; j++) {</div><div class='ctx'> 				tx_cons = NEXT_TX(tx_cons);</div><div class='del'>-				tx_buf = &amp;txr-&gt;tx_buf_ring[tx_cons];</div><div class='add'>+				tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, tx_cons)];</div><div class='ctx'> 				page_pool_recycle_direct(rxr-&gt;page_pool, tx_buf-&gt;page);</div><div class='ctx'> 			}</div><div class='ctx'> 		} else {</div><div class='del'>-			bnxt_sched_reset_txr(bp, txr, i);</div><div class='add'>+			bnxt_sched_reset_txr(bp, txr, tx_cons);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> 		tx_cons = NEXT_TX(tx_cons);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	bnapi-&gt;tx_pkts = 0;</div><div class='add'>+	bnapi-&gt;events &amp;= ~BNXT_TX_CMP_EVENT;</div><div class='ctx'> 	WRITE_ONCE(txr-&gt;tx_cons, tx_cons);</div><div class='ctx'> 	if (rx_doorbell_needed) {</div><div class='del'>-		tx_buf = &amp;txr-&gt;tx_buf_ring[last_tx_cons];</div><div class='add'>+		tx_buf = &amp;txr-&gt;tx_buf_ring[RING_TX(bp, last_tx_cons)];</div><div class='ctx'> 		bnxt_db_write(bp, &amp;rxr-&gt;rx_db, tx_buf-&gt;rx_prod);</div><div class='ctx'> </div><div class='ctx'> 	}</div><div class='hunk'>@@ -249,7 +242,7 @@ bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons,</div><div class='ctx'> 	pdev = bp-&gt;pdev;</div><div class='ctx'> 	offset = bp-&gt;rx_offset;</div><div class='ctx'> </div><div class='del'>-	txr = rxr-&gt;bnapi-&gt;tx_ring;</div><div class='add'>+	txr = rxr-&gt;bnapi-&gt;tx_ring[0];</div><div class='ctx'> 	/* BNXT_RX_PAGE_MODE(bp) when XDP enabled */</div><div class='ctx'> 	orig_data = xdp.data;</div><div class='ctx'> </div><div class='hunk'>@@ -275,7 +268,7 @@ bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons,</div><div class='ctx'> 	case XDP_TX:</div><div class='ctx'> 		rx_buf = &amp;rxr-&gt;rx_buf_ring[cons];</div><div class='ctx'> 		mapping = rx_buf-&gt;mapping - bp-&gt;rx_dma_offset;</div><div class='del'>-		*event = 0;</div><div class='add'>+		*event &amp;= BNXT_TX_CMP_EVENT;</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(xdp_buff_has_frags(&amp;xdp))) {</div><div class='ctx'> 			struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(&amp;xdp);</div><div class='hunk'>@@ -398,7 +391,7 @@ int bnxt_xdp_xmit(struct net_device *dev, int num_frames,</div><div class='ctx'> static int bnxt_xdp_set(struct bnxt *bp, struct bpf_prog *prog)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *dev = bp-&gt;dev;</div><div class='del'>-	int tx_xdp = 0, rc, tc;</div><div class='add'>+	int tx_xdp = 0, tx_cp, rc, tc;</div><div class='ctx'> 	struct bpf_prog *old;</div><div class='ctx'> </div><div class='ctx'> 	if (prog &amp;&amp; !prog-&gt;aux-&gt;xdp_has_frags &amp;&amp;</div><div class='hunk'>@@ -446,7 +439,8 @@ static int bnxt_xdp_set(struct bnxt *bp, struct bpf_prog *prog)</div><div class='ctx'> 	}</div><div class='ctx'> 	bp-&gt;tx_nr_rings_xdp = tx_xdp;</div><div class='ctx'> 	bp-&gt;tx_nr_rings = bp-&gt;tx_nr_rings_per_tc * tc + tx_xdp;</div><div class='del'>-	bp-&gt;cp_nr_rings = max_t(int, bp-&gt;tx_nr_rings, bp-&gt;rx_nr_rings);</div><div class='add'>+	tx_cp = bnxt_num_tx_to_cp(bp, bp-&gt;tx_nr_rings);</div><div class='add'>+	bp-&gt;cp_nr_rings = max_t(int, tx_cp, bp-&gt;rx_nr_rings);</div><div class='ctx'> 	bnxt_set_tpa_flags(bp);</div><div class='ctx'> 	bnxt_set_ring_params(bp);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c<br/>index 9282403d1bf6..2d7ae71287b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/genet/bcmgenet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/genet/bcmgenet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/genet/bcmgenet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/genet/bcmgenet.c</a></div><div class='hunk'>@@ -2132,8 +2132,10 @@ static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 		/* Note: if we ever change from DMA_TX_APPEND_CRC below we</div><div class='ctx'> 		 * will need to restore software padding of "runt" packets</div><div class='ctx'> 		 */</div><div class='add'>+		len_stat |= DMA_TX_APPEND_CRC;</div><div class='add'>+</div><div class='ctx'> 		if (!i) {</div><div class='del'>-			len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;</div><div class='add'>+			len_stat |= DMA_SOP;</div><div class='ctx'> 			if (skb-&gt;ip_summed == CHECKSUM_PARTIAL)</div><div class='ctx'> 				len_stat |= DMA_TX_DO_CSUM;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c<br/>index 48b6191efa56..04964bbe08cf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/tg3.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/broadcom/tg3.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/broadcom/tg3.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/broadcom/tg3.c</a></div><div class='hunk'>@@ -6474,6 +6474,14 @@ static void tg3_dump_state(struct tg3 *tp)</div><div class='ctx'> 	int i;</div><div class='ctx'> 	u32 *regs;</div><div class='ctx'> </div><div class='add'>+	/* If it is a PCI error, all registers will be 0xffff,</div><div class='add'>+	 * we don't dump them out, just report the error and return</div><div class='add'>+	 */</div><div class='add'>+	if (tp-&gt;pdev-&gt;error_state != pci_channel_io_normal) {</div><div class='add'>+		netdev_err(tp-&gt;dev, "PCI channel ERROR!\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);</div><div class='ctx'> 	if (!regs)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -11259,7 +11267,8 @@ static void tg3_reset_task(struct work_struct *work)</div><div class='ctx'> 	rtnl_lock();</div><div class='ctx'> 	tg3_full_lock(tp, 0);</div><div class='ctx'> </div><div class='del'>-	if (tp-&gt;pcierr_recovery || !netif_running(tp-&gt;dev)) {</div><div class='add'>+	if (tp-&gt;pcierr_recovery || !netif_running(tp-&gt;dev) ||</div><div class='add'>+	    tp-&gt;pdev-&gt;error_state != pci_channel_io_normal) {</div><div class='ctx'> 		tg3_flag_clear(tp, RESET_TASK_PENDING);</div><div class='ctx'> 		tg3_full_unlock(tp);</div><div class='ctx'> 		rtnl_unlock();</div><div class='hunk'>@@ -12736,24 +12745,23 @@ static u32 tg3_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+static int tg3_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct tg3 *tp = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; TG3_RSS_INDIR_TBL_SIZE; i++)</div><div class='del'>-		indir[i] = tp-&gt;rss_ind_tbl[i];</div><div class='add'>+		rxfh-&gt;indir[i] = tp-&gt;rss_ind_tbl[i];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,</div><div class='del'>-			const u8 hfunc)</div><div class='add'>+static int tg3_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct tg3 *tp = netdev_priv(dev);</div><div class='ctx'> 	size_t i;</div><div class='hunk'>@@ -12761,15 +12769,16 @@ static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,</div><div class='ctx'> 	/* We require at least one supported parameter to be changed and no</div><div class='ctx'> 	 * change in any of the unsupported parameters</div><div class='ctx'> 	 */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; TG3_RSS_INDIR_TBL_SIZE; i++)</div><div class='del'>-		tp-&gt;rss_ind_tbl[i] = indir[i];</div><div class='add'>+		tp-&gt;rss_ind_tbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 	if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))</div><div class='ctx'> 		return 0;</div><div class='head'>diff --git a/drivers/net/ethernet/brocade/bna/bnad_ethtool.c b/drivers/net/ethernet/brocade/bna/bnad_ethtool.c<br/>index df10edff5603..d1ad6c9f8140 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/brocade/bna/bnad_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/brocade/bna/bnad_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/brocade/bna/bnad_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/brocade/bna/bnad_ethtool.c</a></div><div class='hunk'>@@ -608,7 +608,7 @@ bnad_get_strings(struct net_device *netdev, u32 stringset, u8 *string)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; BNAD_ETHTOOL_STATS_NUM; i++) {</div><div class='ctx'> 		BUG_ON(!(strlen(bnad_net_stats_strings[i]) &lt; ETH_GSTRING_LEN));</div><div class='del'>-		ethtool_sprintf(&amp;string, bnad_net_stats_strings[i]);</div><div class='add'>+		ethtool_puts(&amp;string, bnad_net_stats_strings[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	bmap = bna_tx_rid_mask(&amp;bnad-&gt;bna);</div><div class='head'>diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h<br/>index 78c972bb1d96..aa5700ac9c00 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cadence/macb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb.h</a></div><div class='hunk'>@@ -1165,9 +1165,10 @@ struct macb_ptp_info {</div><div class='ctx'> 	int (*get_ts_info)(struct net_device *dev,</div><div class='ctx'> 			   struct ethtool_ts_info *info);</div><div class='ctx'> 	int (*get_hwtst)(struct net_device *netdev,</div><div class='del'>-			 struct ifreq *ifr);</div><div class='add'>+			 struct kernel_hwtstamp_config *tstamp_config);</div><div class='ctx'> 	int (*set_hwtst)(struct net_device *netdev,</div><div class='del'>-			 struct ifreq *ifr, int cmd);</div><div class='add'>+			 struct kernel_hwtstamp_config *tstamp_config,</div><div class='add'>+			 struct netlink_ext_ack *extack);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct macb_pm_data {</div><div class='hunk'>@@ -1314,7 +1315,7 @@ struct macb {</div><div class='ctx'> 	struct ptp_clock *ptp_clock;</div><div class='ctx'> 	struct ptp_clock_info ptp_clock_info;</div><div class='ctx'> 	struct tsu_incr tsu_incr;</div><div class='del'>-	struct hwtstamp_config tstamp_config;</div><div class='add'>+	struct kernel_hwtstamp_config tstamp_config;</div><div class='ctx'> </div><div class='ctx'> 	/* RX queue filer rule set*/</div><div class='ctx'> 	struct ethtool_rx_fs_list rx_fs_list;</div><div class='hunk'>@@ -1363,8 +1364,12 @@ static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, stru</div><div class='ctx'> </div><div class='ctx'> 	gem_ptp_rxstamp(bp, skb, desc);</div><div class='ctx'> }</div><div class='del'>-int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);</div><div class='del'>-int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);</div><div class='add'>+</div><div class='add'>+int gem_get_hwtst(struct net_device *dev,</div><div class='add'>+		  struct kernel_hwtstamp_config *tstamp_config);</div><div class='add'>+int gem_set_hwtst(struct net_device *dev,</div><div class='add'>+		  struct kernel_hwtstamp_config *tstamp_config,</div><div class='add'>+		  struct netlink_ext_ack *extack);</div><div class='ctx'> #else</div><div class='ctx'> static inline void gem_ptp_init(struct net_device *ndev) { }</div><div class='ctx'> static inline void gem_ptp_remove(struct net_device *ndev) { }</div><div class='head'>diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c<br/>index cebae0f418f2..898debfd4db3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cadence/macb_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb_main.c</a></div><div class='hunk'>@@ -3773,18 +3773,38 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)</div><div class='ctx'> 	if (!netif_running(dev))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (bp-&gt;ptp_info) {</div><div class='del'>-		switch (cmd) {</div><div class='del'>-		case SIOCSHWTSTAMP:</div><div class='del'>-			return bp-&gt;ptp_info-&gt;set_hwtst(dev, rq, cmd);</div><div class='del'>-		case SIOCGHWTSTAMP:</div><div class='del'>-			return bp-&gt;ptp_info-&gt;get_hwtst(dev, rq);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return phylink_mii_ioctl(bp-&gt;phylink, rq, cmd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int macb_hwtstamp_get(struct net_device *dev,</div><div class='add'>+			     struct kernel_hwtstamp_config *cfg)</div><div class='add'>+{</div><div class='add'>+	struct macb *bp = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	if (!netif_running(dev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;ptp_info)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return bp-&gt;ptp_info-&gt;get_hwtst(dev, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int macb_hwtstamp_set(struct net_device *dev,</div><div class='add'>+			     struct kernel_hwtstamp_config *cfg,</div><div class='add'>+			     struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct macb *bp = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	if (!netif_running(dev))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (!bp-&gt;ptp_info)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return bp-&gt;ptp_info-&gt;set_hwtst(dev, cfg, extack);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void macb_set_txcsum_feature(struct macb *bp,</div><div class='ctx'> 					   netdev_features_t features)</div><div class='ctx'> {</div><div class='hunk'>@@ -3884,6 +3904,8 @@ static const struct net_device_ops macb_netdev_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> 	.ndo_set_features	= macb_set_features,</div><div class='ctx'> 	.ndo_features_check	= macb_features_check,</div><div class='add'>+	.ndo_hwtstamp_set	= macb_hwtstamp_set,</div><div class='add'>+	.ndo_hwtstamp_get	= macb_hwtstamp_get,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Configure peripheral capabilities according to device tree</div><div class='hunk'>@@ -4539,6 +4561,8 @@ static const struct net_device_ops at91ether_netdev_ops = {</div><div class='ctx'> #ifdef CONFIG_NET_POLL_CONTROLLER</div><div class='ctx'> 	.ndo_poll_controller	= at91ether_poll_controller,</div><div class='ctx'> #endif</div><div class='add'>+	.ndo_hwtstamp_set	= macb_hwtstamp_set,</div><div class='add'>+	.ndo_hwtstamp_get	= macb_hwtstamp_get,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,</div><div class='head'>diff --git a/drivers/net/ethernet/cadence/macb_ptp.c b/drivers/net/ethernet/cadence/macb_ptp.c<br/>index 51d26fa190d7..a63bf29c4fa8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cadence/macb_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cadence/macb_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cadence/macb_ptp.c</a></div><div class='hunk'>@@ -374,19 +374,16 @@ static int gem_ptp_set_ts_mode(struct macb *bp,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int gem_get_hwtst(struct net_device *dev, struct ifreq *rq)</div><div class='add'>+int gem_get_hwtst(struct net_device *dev,</div><div class='add'>+		  struct kernel_hwtstamp_config *tstamp_config)</div><div class='ctx'> {</div><div class='del'>-	struct hwtstamp_config *tstamp_config;</div><div class='ctx'> 	struct macb *bp = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	tstamp_config = &amp;bp-&gt;tstamp_config;</div><div class='add'>+	*tstamp_config = bp-&gt;tstamp_config;</div><div class='ctx'> 	if ((bp-&gt;hw_dma_cap &amp; HW_DMA_CAP_PTP) == 0)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (copy_to_user(rq-&gt;ifr_data, tstamp_config, sizeof(*tstamp_config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)</div><div class='hunk'>@@ -401,22 +398,18 @@ static void gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)</div><div class='ctx'> 		macb_writel(bp, NCR, reg_val &amp; ~MACB_BIT(OSSMODE));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd)</div><div class='add'>+int gem_set_hwtst(struct net_device *dev,</div><div class='add'>+		  struct kernel_hwtstamp_config *tstamp_config,</div><div class='add'>+		  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	enum macb_bd_control tx_bd_control = TSTAMP_DISABLED;</div><div class='ctx'> 	enum macb_bd_control rx_bd_control = TSTAMP_DISABLED;</div><div class='del'>-	struct hwtstamp_config *tstamp_config;</div><div class='ctx'> 	struct macb *bp = netdev_priv(dev);</div><div class='ctx'> 	u32 regval;</div><div class='ctx'> </div><div class='del'>-	tstamp_config = &amp;bp-&gt;tstamp_config;</div><div class='ctx'> 	if ((bp-&gt;hw_dma_cap &amp; HW_DMA_CAP_PTP) == 0)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(tstamp_config, ifr-&gt;ifr_data,</div><div class='del'>-			   sizeof(*tstamp_config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='ctx'> 	switch (tstamp_config-&gt;tx_type) {</div><div class='ctx'> 	case HWTSTAMP_TX_OFF:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -463,12 +456,11 @@ int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	bp-&gt;tstamp_config = *tstamp_config;</div><div class='add'>+</div><div class='ctx'> 	if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> </div><div class='del'>-	if (copy_to_user(ifr-&gt;ifr_data, tstamp_config, sizeof(*tstamp_config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-	else</div><div class='del'>-		return 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c<br/>index 068ed52b66c9..b3c81a2e9d46 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c</a></div><div class='hunk'>@@ -1490,7 +1490,7 @@ int cn23xx_get_vf_stats(struct octeon_device *oct, int vfidx,</div><div class='ctx'> 	mbox_cmd.q_no = vfidx * oct-&gt;sriov_info.rings_per_vf;</div><div class='ctx'> 	mbox_cmd.recv_len = 0;</div><div class='ctx'> 	mbox_cmd.recv_status = 0;</div><div class='del'>-	mbox_cmd.fn = (octeon_mbox_callback_t)cn23xx_get_vf_stats_callback;</div><div class='add'>+	mbox_cmd.fn = cn23xx_get_vf_stats_callback;</div><div class='ctx'> 	ctx.stats = stats;</div><div class='ctx'> 	atomic_set(&amp;ctx.status, 0);</div><div class='ctx'> 	mbox_cmd.fn_arg = (void *)&amp;ctx;</div><div class='head'>diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c<br/>index dd5d80fee24f..d2fcb3da484e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c</a></div><div class='hunk'>@@ -429,7 +429,7 @@ int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct)</div><div class='ctx'> 	mbox_cmd.q_no = 0;</div><div class='ctx'> 	mbox_cmd.recv_len = 0;</div><div class='ctx'> 	mbox_cmd.recv_status = 0;</div><div class='del'>-	mbox_cmd.fn = (octeon_mbox_callback_t)octeon_pfvf_hs_callback;</div><div class='add'>+	mbox_cmd.fn = octeon_pfvf_hs_callback;</div><div class='ctx'> 	mbox_cmd.fn_arg = &amp;status;</div><div class='ctx'> </div><div class='ctx'> 	octeon_mbox_write(oct, &amp;mbox_cmd);</div><div class='head'>diff --git a/drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h b/drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h<br/>index d92bd7e16477..9ac85d22c615 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/liquidio/octeon_mailbox.h</a></div><div class='hunk'>@@ -57,7 +57,10 @@ union octeon_mbox_message {</div><div class='ctx'> 	} s;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-typedef void (*octeon_mbox_callback_t)(void *, void *, void *);</div><div class='add'>+struct octeon_mbox_cmd;</div><div class='add'>+</div><div class='add'>+typedef void (*octeon_mbox_callback_t)(struct octeon_device *,</div><div class='add'>+				       struct octeon_mbox_cmd *, void *);</div><div class='ctx'> </div><div class='ctx'> struct octeon_mbox_cmd {</div><div class='ctx'> 	union octeon_mbox_message msg;</div><div class='head'>diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c b/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c<br/>index d8d71bf97983..34125b8cd935 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c</a></div><div class='hunk'>@@ -653,35 +653,36 @@ static u32 nicvf_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return nic-&gt;rss_info.rss_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nicvf_get_rxfh(struct net_device *dev, u32 *indir, u8 *hkey,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int nicvf_get_rxfh(struct net_device *dev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct nicvf *nic = netdev_priv(dev);</div><div class='ctx'> 	struct nicvf_rss_info *rss = &amp;nic-&gt;rss_info;</div><div class='ctx'> 	int idx;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (idx = 0; idx &lt; rss-&gt;rss_size; idx++)</div><div class='del'>-			indir[idx] = rss-&gt;ind_tbl[idx];</div><div class='add'>+			rxfh-&gt;indir[idx] = rss-&gt;ind_tbl[idx];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hkey)</div><div class='del'>-		memcpy(hkey, rss-&gt;key, RSS_HASH_KEY_SIZE * sizeof(u64));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, rss-&gt;key, RSS_HASH_KEY_SIZE * sizeof(u64));</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nicvf_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			  const u8 *hkey, const u8 hfunc)</div><div class='add'>+static int nicvf_set_rxfh(struct net_device *dev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct nicvf *nic = netdev_priv(dev);</div><div class='ctx'> 	struct nicvf_rss_info *rss = &amp;nic-&gt;rss_info;</div><div class='ctx'> 	int idx;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (!rss-&gt;enable) {</div><div class='hunk'>@@ -690,13 +691,13 @@ static int nicvf_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (idx = 0; idx &lt; rss-&gt;rss_size; idx++)</div><div class='del'>-			rss-&gt;ind_tbl[idx] = indir[idx];</div><div class='add'>+			rss-&gt;ind_tbl[idx] = rxfh-&gt;indir[idx];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hkey) {</div><div class='del'>-		memcpy(rss-&gt;key, hkey, RSS_HASH_KEY_SIZE * sizeof(u64));</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(rss-&gt;key, rxfh-&gt;key, RSS_HASH_KEY_SIZE * sizeof(u64));</div><div class='ctx'> 		nicvf_set_rss_key(nic);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/chelsio/cxgb3/adapter.h b/drivers/net/ethernet/chelsio/cxgb3/adapter.h<br/>index 6d682b7c7aac..9d11e55981a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb3/adapter.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/chelsio/cxgb3/adapter.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb3/adapter.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb3/adapter.h</a></div><div class='hunk'>@@ -237,7 +237,7 @@ struct adapter {</div><div class='ctx'> 	int msix_nvectors;</div><div class='ctx'> 	struct {</div><div class='ctx'> 		unsigned short vec;</div><div class='del'>-		char desc[22];</div><div class='add'>+		char desc[IFNAMSIZ + 1 + 12];	/* Needs space for "%s-%d" */</div><div class='ctx'> 	} msix_info[SGE_QSETS + 1];</div><div class='ctx'> </div><div class='ctx'> 	/* T3 modules */</div><div class='head'>diff --git a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c<br/>index d117022d15d7..2236f1d35f2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c</a></div><div class='hunk'>@@ -380,19 +380,18 @@ static irqreturn_t t3_async_intr_handler(int irq, void *cookie)</div><div class='ctx'>  */</div><div class='ctx'> static void name_msix_vecs(struct adapter *adap)</div><div class='ctx'> {</div><div class='del'>-	int i, j, msi_idx = 1, n = sizeof(adap-&gt;msix_info[0].desc) - 1;</div><div class='add'>+	int i, j, msi_idx = 1;</div><div class='ctx'> </div><div class='del'>-	snprintf(adap-&gt;msix_info[0].desc, n, "%s", adap-&gt;name);</div><div class='del'>-	adap-&gt;msix_info[0].desc[n] = 0;</div><div class='add'>+	strscpy(adap-&gt;msix_info[0].desc, adap-&gt;name, sizeof(adap-&gt;msix_info[0].desc));</div><div class='ctx'> </div><div class='ctx'> 	for_each_port(adap, j) {</div><div class='ctx'> 		struct net_device *d = adap-&gt;port[j];</div><div class='ctx'> 		const struct port_info *pi = netdev_priv(d);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; pi-&gt;nqsets; i++, msi_idx++) {</div><div class='del'>-			snprintf(adap-&gt;msix_info[msi_idx].desc, n,</div><div class='add'>+			snprintf(adap-&gt;msix_info[msi_idx].desc,</div><div class='add'>+				 sizeof(adap-&gt;msix_info[0].desc),</div><div class='ctx'> 				 "%s-%d", d-&gt;name, pi-&gt;first_qset + i);</div><div class='del'>-			adap-&gt;msix_info[msi_idx].desc[n] = 0;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c<br/>index 8477a93cee6b..47eecde36285 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c</a></div><div class='hunk'>@@ -1588,22 +1588,23 @@ static u32 get_rss_table_size(struct net_device *dev)</div><div class='ctx'> 	return pi-&gt;rss_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int get_rss_table(struct net_device *dev, u32 *p, u8 *key, u8 *hfunc)</div><div class='add'>+static int get_rss_table(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	const struct port_info *pi = netdev_priv(dev);</div><div class='ctx'> 	unsigned int n = pi-&gt;rss_size;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!p)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	while (n--)</div><div class='del'>-		p[n] = pi-&gt;rss[n];</div><div class='add'>+		rxfh-&gt;indir[n] = pi-&gt;rss[n];</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,</div><div class='del'>-			 const u8 hfunc)</div><div class='add'>+static int set_rss_table(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	struct port_info *pi = netdev_priv(dev);</div><div class='hunk'>@@ -1611,16 +1612,17 @@ static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,</div><div class='ctx'> 	/* We require at least one supported parameter to be changed and no</div><div class='ctx'> 	 * change in any of the unsupported parameters</div><div class='ctx'> 	 */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	if (!p)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Interface must be brought up atleast once */</div><div class='ctx'> 	if (pi-&gt;adapter-&gt;flags &amp; CXGB4_FULL_INIT_DONE) {</div><div class='ctx'> 		for (i = 0; i &lt; pi-&gt;rss_size; i++)</div><div class='del'>-			pi-&gt;rss[i] = p[i];</div><div class='add'>+			pi-&gt;rss[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 		return cxgb4_write_rss(pi, pi-&gt;rss);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/cisco/enic/enic_ethtool.c b/drivers/net/ethernet/cisco/enic/enic_ethtool.c<br/>index 08b7cc0a1809..241906697019 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cisco/enic/enic_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cisco/enic/enic_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cisco/enic/enic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cisco/enic/enic_ethtool.c</a></div><div class='hunk'>@@ -568,31 +568,32 @@ static u32 enic_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return ENIC_RSS_LEN;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int enic_get_rxfh(struct net_device *netdev, u32 *indir, u8 *hkey,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int enic_get_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct enic *enic = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if (hkey)</div><div class='del'>-		memcpy(hkey, enic-&gt;rss_key, ENIC_RSS_LEN);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, enic-&gt;rss_key, ENIC_RSS_LEN);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int enic_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			 const u8 *hkey, const u8 hfunc)</div><div class='add'>+static int enic_set_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct enic *enic = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if ((hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP) ||</div><div class='del'>-	    indir)</div><div class='add'>+	if (rxfh-&gt;indir ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (hkey)</div><div class='del'>-		memcpy(enic-&gt;rss_key, hkey, ENIC_RSS_LEN);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(enic-&gt;rss_key, rxfh-&gt;key, ENIC_RSS_LEN);</div><div class='ctx'> </div><div class='ctx'> 	return __enic_set_rsskey(enic);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/cortina/gemini.c b/drivers/net/ethernet/cortina/gemini.c<br/>index 78287cfcbf63..705c3eb19cd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cortina/gemini.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/cortina/gemini.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/cortina/gemini.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/cortina/gemini.c</a></div><div class='hunk'>@@ -79,8 +79,7 @@ MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");</div><div class='ctx'> #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)</div><div class='ctx'> </div><div class='ctx'> #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \</div><div class='del'>-		NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \</div><div class='del'>-		NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)</div><div class='add'>+			       NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct gmac_queue_page - page buffer per-page info</div><div class='hunk'>@@ -1143,23 +1142,13 @@ static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,</div><div class='ctx'> 	struct gmac_txdesc *txd;</div><div class='ctx'> 	skb_frag_t *skb_frag;</div><div class='ctx'> 	dma_addr_t mapping;</div><div class='del'>-	unsigned short mtu;</div><div class='ctx'> 	void *buffer;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	mtu  = ETH_HLEN;</div><div class='del'>-	mtu += netdev-&gt;mtu;</div><div class='del'>-	if (skb-&gt;protocol == htons(ETH_P_8021Q))</div><div class='del'>-		mtu += VLAN_HLEN;</div><div class='del'>-</div><div class='add'>+	/* TODO: implement proper TSO using MTU in word3 */</div><div class='ctx'> 	word1 = skb-&gt;len;</div><div class='ctx'> 	word3 = SOF_BIT;</div><div class='ctx'> </div><div class='del'>-	if (word1 &gt; mtu) {</div><div class='del'>-		word1 |= TSS_MTU_ENABLE_BIT;</div><div class='del'>-		word3 |= mtu;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	if (skb-&gt;len &gt;= ETH_FRAME_LEN) {</div><div class='ctx'> 		/* Hardware offloaded checksumming isn't working on frames</div><div class='ctx'> 		 * bigger than 1514 bytes. A hypothesis about this is that the</div><div class='head'>diff --git a/drivers/net/ethernet/dlink/dl2k.c b/drivers/net/ethernet/dlink/dl2k.c<br/>index db6615aa921b..7bfeae04b52b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/dlink/dl2k.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/dlink/dl2k.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/dlink/dl2k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/dlink/dl2k.c</a></div><div class='hunk'>@@ -565,8 +565,7 @@ static void rio_hw_init(struct net_device *dev)</div><div class='ctx'> 	 * too. However, it doesn't work on IP1000A so we use 16-bit access.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 3; i++)</div><div class='del'>-		dw16(StationAddr0 + 2 * i,</div><div class='del'>-		     cpu_to_le16(((const u16 *)dev-&gt;dev_addr)[i]));</div><div class='add'>+		dw16(StationAddr0 + 2 * i, get_unaligned_le16(&amp;dev-&gt;dev_addr[2 * i]));</div><div class='ctx'> </div><div class='ctx'> 	set_multicast (dev);</div><div class='ctx'> 	if (np-&gt;coalesce) {</div><div class='head'>diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c<br/>index a29de29bdf23..f001a649f58f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/emulex/benet/be_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/emulex/benet/be_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/emulex/benet/be_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/emulex/benet/be_ethtool.c</a></div><div class='hunk'>@@ -1271,43 +1271,45 @@ static u32 be_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return RSS_HASH_KEY_LEN;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int be_get_rxfh(struct net_device *netdev, u32 *indir, u8 *hkey,</div><div class='del'>-		       u8 *hfunc)</div><div class='add'>+static int be_get_rxfh(struct net_device *netdev,</div><div class='add'>+		       struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct be_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> 	struct rss_info *rss = &amp;adapter-&gt;rss_info;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; RSS_INDIR_TABLE_LEN; i++)</div><div class='del'>-			indir[i] = rss-&gt;rss_queue[i];</div><div class='add'>+			rxfh-&gt;indir[i] = rss-&gt;rss_queue[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hkey)</div><div class='del'>-		memcpy(hkey, rss-&gt;rss_hkey, RSS_HASH_KEY_LEN);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, rss-&gt;rss_hkey, RSS_HASH_KEY_LEN);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int be_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-		       const u8 *hkey, const u8 hfunc)</div><div class='add'>+static int be_set_rxfh(struct net_device *netdev,</div><div class='add'>+		       struct ethtool_rxfh_param *rxfh,</div><div class='add'>+		       struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	int rc = 0, i, j;</div><div class='ctx'> 	struct be_adapter *adapter = netdev_priv(netdev);</div><div class='add'>+	u8 *hkey = rxfh-&gt;key;</div><div class='ctx'> 	u8 rsstable[RSS_INDIR_TABLE_LEN];</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		struct be_rx_obj *rxo;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; RSS_INDIR_TABLE_LEN; i++) {</div><div class='del'>-			j = indir[i];</div><div class='add'>+			j = rxfh-&gt;indir[i];</div><div class='ctx'> 			rxo = &amp;adapter-&gt;rx_obj[j];</div><div class='ctx'> 			rsstable[i] = rxo-&gt;rss_id;</div><div class='ctx'> 			adapter-&gt;rss_info.rss_queue[i] = j;</div><div class='head'>diff --git a/drivers/net/ethernet/ezchip/nps_enet.c b/drivers/net/ethernet/ezchip/nps_enet.c<br/>index 4d7184d46824..07c2b701b5fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ezchip/nps_enet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ezchip/nps_enet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ezchip/nps_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ezchip/nps_enet.c</a></div><div class='hunk'>@@ -633,7 +633,7 @@ out_netdev:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static s32 nps_enet_remove(struct platform_device *pdev)</div><div class='add'>+static void nps_enet_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *ndev = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct nps_enet_priv *priv = netdev_priv(ndev);</div><div class='hunk'>@@ -641,8 +641,6 @@ static s32 nps_enet_remove(struct platform_device *pdev)</div><div class='ctx'> 	unregister_netdev(ndev);</div><div class='ctx'> 	netif_napi_del(&amp;priv-&gt;napi);</div><div class='ctx'> 	free_netdev(ndev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id nps_enet_dt_ids[] = {</div><div class='hunk'>@@ -653,7 +651,7 @@ MODULE_DEVICE_TABLE(of, nps_enet_dt_ids);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver nps_enet_driver = {</div><div class='ctx'> 	.probe = nps_enet_probe,</div><div class='del'>-	.remove = nps_enet_remove,</div><div class='add'>+	.remove_new = nps_enet_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = DRV_NAME,</div><div class='ctx'> 		.of_match_table  = nps_enet_dt_ids,</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c<br/>index 15bab41cee48..888509cf1f21 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c</a></div><div class='hunk'>@@ -516,8 +516,6 @@ struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv,</div><div class='ctx'> </div><div class='ctx'> 	memcpy(skb-&gt;data, fd_vaddr + fd_offset, fd_length);</div><div class='ctx'> </div><div class='del'>-	dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(fd));</div><div class='del'>-</div><div class='ctx'> 	return skb;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -589,6 +587,7 @@ void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,</div><div class='ctx'> 	struct rtnl_link_stats64 *percpu_stats;</div><div class='ctx'> 	struct dpaa2_eth_drv_stats *percpu_extras;</div><div class='ctx'> 	struct device *dev = priv-&gt;net_dev-&gt;dev.parent;</div><div class='add'>+	bool recycle_rx_buf = false;</div><div class='ctx'> 	void *buf_data;</div><div class='ctx'> 	u32 xdp_act;</div><div class='ctx'> </div><div class='hunk'>@@ -618,6 +617,8 @@ void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,</div><div class='ctx'> 			dma_unmap_page(dev, addr, priv-&gt;rx_buf_size,</div><div class='ctx'> 				       DMA_BIDIRECTIONAL);</div><div class='ctx'> 			skb = dpaa2_eth_build_linear_skb(ch, fd, vaddr);</div><div class='add'>+		} else {</div><div class='add'>+			recycle_rx_buf = true;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (fd_format == dpaa2_fd_sg) {</div><div class='ctx'> 		WARN_ON(priv-&gt;xdp_prog);</div><div class='hunk'>@@ -637,6 +638,9 @@ void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,</div><div class='ctx'> 		goto err_build_skb;</div><div class='ctx'> </div><div class='ctx'> 	dpaa2_eth_receive_skb(priv, ch, fd, vaddr, fq, percpu_stats, skb);</div><div class='add'>+</div><div class='add'>+	if (recycle_rx_buf)</div><div class='add'>+		dpaa2_eth_recycle_buf(priv, ch, dpaa2_fd_get_addr(fd));</div><div class='ctx'> 	return;</div><div class='ctx'> </div><div class='ctx'> err_build_skb:</div><div class='hunk'>@@ -1073,14 +1077,12 @@ static int dpaa2_eth_build_single_fd(struct dpaa2_eth_priv *priv,</div><div class='ctx'> 	dma_addr_t addr;</div><div class='ctx'> </div><div class='ctx'> 	buffer_start = skb-&gt;data - dpaa2_eth_needed_headroom(skb);</div><div class='del'>-</div><div class='del'>-	/* If there's enough room to align the FD address, do it.</div><div class='del'>-	 * It will help hardware optimize accesses.</div><div class='del'>-	 */</div><div class='ctx'> 	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,</div><div class='ctx'> 				  DPAA2_ETH_TX_BUF_ALIGN);</div><div class='ctx'> 	if (aligned_start &gt;= skb-&gt;head)</div><div class='ctx'> 		buffer_start = aligned_start;</div><div class='add'>+	else</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/* Store a backpointer to the skb at the beginning of the buffer</div><div class='ctx'> 	 * (in the private data area) such that we can release it</div><div class='hunk'>@@ -4967,6 +4969,8 @@ static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_dl_port_add;</div><div class='ctx'> </div><div class='add'>+	net_dev-&gt;needed_headroom = DPAA2_ETH_SWA_SIZE + DPAA2_ETH_TX_BUF_ALIGN;</div><div class='add'>+</div><div class='ctx'> 	err = register_netdev(net_dev);</div><div class='ctx'> 	if (err &lt; 0) {</div><div class='ctx'> 		dev_err(dev, "register_netdev() failed\n");</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h<br/>index bfb6c96c3b2f..834cba8c3a41 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h</a></div><div class='hunk'>@@ -740,7 +740,7 @@ static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)</div><div class='ctx'> </div><div class='ctx'> static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)</div><div class='ctx'> {</div><div class='del'>-	unsigned int headroom = DPAA2_ETH_SWA_SIZE;</div><div class='add'>+	unsigned int headroom = DPAA2_ETH_SWA_SIZE + DPAA2_ETH_TX_BUF_ALIGN;</div><div class='ctx'> </div><div class='ctx'> 	/* If we don't have an skb (e.g. XDP buffer), we only need space for</div><div class='ctx'> 	 * the software annotation area</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c<br/>index 4798fb7fe35d..b6a534a3e0b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch-flower.c</a></div><div class='hunk'>@@ -139,7 +139,8 @@ int dpaa2_switch_acl_entry_add(struct dpaa2_switch_filter_block *filter_block,</div><div class='ctx'> 	err = dpsw_acl_add_entry(ethsw-&gt;mc_io, 0, ethsw-&gt;dpsw_handle,</div><div class='ctx'> 				 filter_block-&gt;acl_id, acl_entry_cfg);</div><div class='ctx'> </div><div class='del'>-	dma_unmap_single(dev, acl_entry_cfg-&gt;key_iova, sizeof(cmd_buff),</div><div class='add'>+	dma_unmap_single(dev, acl_entry_cfg-&gt;key_iova,</div><div class='add'>+			 DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE,</div><div class='ctx'> 			 DMA_TO_DEVICE);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(dev, "dpsw_acl_add_entry() failed %d\n", err);</div><div class='hunk'>@@ -181,8 +182,8 @@ dpaa2_switch_acl_entry_remove(struct dpaa2_switch_filter_block *block,</div><div class='ctx'> 	err = dpsw_acl_remove_entry(ethsw-&gt;mc_io, 0, ethsw-&gt;dpsw_handle,</div><div class='ctx'> 				    block-&gt;acl_id, acl_entry_cfg);</div><div class='ctx'> </div><div class='del'>-	dma_unmap_single(dev, acl_entry_cfg-&gt;key_iova, sizeof(cmd_buff),</div><div class='del'>-			 DMA_TO_DEVICE);</div><div class='add'>+	dma_unmap_single(dev, acl_entry_cfg-&gt;key_iova,</div><div class='add'>+			 DPAA2_ETHSW_PORT_ACL_CMD_BUF_SIZE, DMA_TO_DEVICE);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(dev, "dpsw_acl_remove_entry() failed %d\n", err);</div><div class='ctx'> 		kfree(cmd_buff);</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c<br/>index 97d3151076d5..f3543a2df68d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c</a></div><div class='hunk'>@@ -289,7 +289,7 @@ static int dpaa2_switch_port_add_vlan(struct ethsw_port_priv *port_priv,</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (port_priv-&gt;vlans[vid]) {</div><div class='del'>-		netdev_warn(netdev, "VLAN %d already configured\n", vid);</div><div class='add'>+		netdev_err(netdev, "VLAN %d already configured\n", vid);</div><div class='ctx'> 		return -EEXIST;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1509,9 +1509,9 @@ static irqreturn_t dpaa2_switch_irq0_handler_thread(int irq_num, void *arg)</div><div class='ctx'> 	struct device *dev = (struct device *)arg;</div><div class='ctx'> 	struct ethsw_core *ethsw = dev_get_drvdata(dev);</div><div class='ctx'> 	struct ethsw_port_priv *port_priv;</div><div class='del'>-	u32 status = ~0;</div><div class='ctx'> 	int err, if_id;</div><div class='ctx'> 	bool had_mac;</div><div class='add'>+	u32 status;</div><div class='ctx'> </div><div class='ctx'> 	err = dpsw_get_irq_status(ethsw-&gt;mc_io, 0, ethsw-&gt;dpsw_handle,</div><div class='ctx'> 				  DPSW_IRQ_INDEX_IF, &amp;status);</div><div class='hunk'>@@ -1523,12 +1523,11 @@ static irqreturn_t dpaa2_switch_irq0_handler_thread(int irq_num, void *arg)</div><div class='ctx'> 	if_id = (status &amp; 0xFFFF0000) &gt;&gt; 16;</div><div class='ctx'> 	port_priv = ethsw-&gt;ports[if_id];</div><div class='ctx'> </div><div class='del'>-	if (status &amp; DPSW_IRQ_EVENT_LINK_CHANGED) {</div><div class='add'>+	if (status &amp; DPSW_IRQ_EVENT_LINK_CHANGED)</div><div class='ctx'> 		dpaa2_switch_port_link_state_update(port_priv-&gt;netdev);</div><div class='del'>-		dpaa2_switch_port_set_mac_addr(port_priv);</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	if (status &amp; DPSW_IRQ_EVENT_ENDPOINT_CHANGED) {</div><div class='add'>+		dpaa2_switch_port_set_mac_addr(port_priv);</div><div class='ctx'> 		/* We can avoid locking because the "endpoint changed" IRQ</div><div class='ctx'> 		 * handler is the only one who changes priv-&gt;mac at runtime,</div><div class='ctx'> 		 * so we are not racing with anyone.</div><div class='hunk'>@@ -1540,20 +1539,20 @@ static irqreturn_t dpaa2_switch_irq0_handler_thread(int irq_num, void *arg)</div><div class='ctx'> 			dpaa2_switch_port_connect_mac(port_priv);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='ctx'> 	err = dpsw_clear_irq_status(ethsw-&gt;mc_io, 0, ethsw-&gt;dpsw_handle,</div><div class='ctx'> 				    DPSW_IRQ_INDEX_IF, status);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		dev_err(dev, "Can't clear irq status (err %d)\n", err);</div><div class='ctx'> </div><div class='add'>+out:</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dpaa2_switch_setup_irqs(struct fsl_mc_device *sw_dev)</div><div class='ctx'> {</div><div class='add'>+	u32 mask = DPSW_IRQ_EVENT_LINK_CHANGED | DPSW_IRQ_EVENT_ENDPOINT_CHANGED;</div><div class='ctx'> 	struct device *dev = &amp;sw_dev-&gt;dev;</div><div class='ctx'> 	struct ethsw_core *ethsw = dev_get_drvdata(dev);</div><div class='del'>-	u32 mask = DPSW_IRQ_EVENT_LINK_CHANGED;</div><div class='ctx'> 	struct fsl_mc_device_irq *irq;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -1775,8 +1774,10 @@ int dpaa2_switch_port_vlans_add(struct net_device *netdev,</div><div class='ctx'> 	/* Make sure that the VLAN is not already configured</div><div class='ctx'> 	 * on the switch port</div><div class='ctx'> 	 */</div><div class='del'>-	if (port_priv-&gt;vlans[vlan-&gt;vid] &amp; ETHSW_VLAN_MEMBER)</div><div class='add'>+	if (port_priv-&gt;vlans[vlan-&gt;vid] &amp; ETHSW_VLAN_MEMBER) {</div><div class='add'>+		netdev_err(netdev, "VLAN %d already configured\n", vlan-&gt;vid);</div><div class='ctx'> 		return -EEXIST;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check if there is space for a new VLAN */</div><div class='ctx'> 	err = dpsw_get_attributes(ethsw-&gt;mc_io, 0, ethsw-&gt;dpsw_handle,</div><div class='hunk'>@@ -1998,33 +1999,16 @@ static int dpaa2_switch_port_attr_set_event(struct net_device *netdev,</div><div class='ctx'> 	return notifier_from_errno(err);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static struct notifier_block dpaa2_switch_port_switchdev_nb;</div><div class='del'>-static struct notifier_block dpaa2_switch_port_switchdev_blocking_nb;</div><div class='del'>-</div><div class='ctx'> static int dpaa2_switch_port_bridge_join(struct net_device *netdev,</div><div class='ctx'> 					 struct net_device *upper_dev,</div><div class='ctx'> 					 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ethsw_port_priv *port_priv = netdev_priv(netdev);</div><div class='add'>+	struct dpaa2_switch_fdb *old_fdb = port_priv-&gt;fdb;</div><div class='ctx'> 	struct ethsw_core *ethsw = port_priv-&gt;ethsw_data;</div><div class='del'>-	struct ethsw_port_priv *other_port_priv;</div><div class='del'>-	struct net_device *other_dev;</div><div class='del'>-	struct list_head *iter;</div><div class='ctx'> 	bool learn_ena;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	netdev_for_each_lower_dev(upper_dev, other_dev, iter) {</div><div class='del'>-		if (!dpaa2_switch_port_dev_check(other_dev))</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		other_port_priv = netdev_priv(other_dev);</div><div class='del'>-		if (other_port_priv-&gt;ethsw_data != port_priv-&gt;ethsw_data) {</div><div class='del'>-			NL_SET_ERR_MSG_MOD(extack,</div><div class='del'>-					   "Interface from a different DPSW is in the bridge already");</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Delete the previously manually installed VLAN 1 */</div><div class='ctx'> 	err = dpaa2_switch_port_del_vlan(port_priv, 1);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -2042,10 +2026,13 @@ static int dpaa2_switch_port_bridge_join(struct net_device *netdev,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_egress_flood;</div><div class='ctx'> </div><div class='add'>+	/* Recreate the egress flood domain of the FDB that we just left. */</div><div class='add'>+	err = dpaa2_switch_fdb_set_egress_flood(ethsw, old_fdb-&gt;fdb_id);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_egress_flood;</div><div class='add'>+</div><div class='ctx'> 	err = switchdev_bridge_port_offload(netdev, netdev, NULL,</div><div class='del'>-					    &amp;dpaa2_switch_port_switchdev_nb,</div><div class='del'>-					    &amp;dpaa2_switch_port_switchdev_blocking_nb,</div><div class='del'>-					    false, extack);</div><div class='add'>+					    NULL, NULL, false, extack);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_switchdev_offload;</div><div class='ctx'> </div><div class='hunk'>@@ -2079,9 +2066,7 @@ static int dpaa2_switch_port_restore_rxvlan(struct net_device *vdev, int vid, vo</div><div class='ctx'> </div><div class='ctx'> static void dpaa2_switch_port_pre_bridge_leave(struct net_device *netdev)</div><div class='ctx'> {</div><div class='del'>-	switchdev_bridge_port_unoffload(netdev, NULL,</div><div class='del'>-					&amp;dpaa2_switch_port_switchdev_nb,</div><div class='del'>-					&amp;dpaa2_switch_port_switchdev_blocking_nb);</div><div class='add'>+	switchdev_bridge_port_unoffload(netdev, NULL, NULL, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int dpaa2_switch_port_bridge_leave(struct net_device *netdev)</div><div class='hunk'>@@ -2162,6 +2147,10 @@ dpaa2_switch_prechangeupper_sanity_checks(struct net_device *netdev,</div><div class='ctx'> 					  struct net_device *upper_dev,</div><div class='ctx'> 					  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='add'>+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);</div><div class='add'>+	struct ethsw_port_priv *other_port_priv;</div><div class='add'>+	struct net_device *other_dev;</div><div class='add'>+	struct list_head *iter;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!br_vlan_enabled(upper_dev)) {</div><div class='hunk'>@@ -2176,54 +2165,93 @@ dpaa2_switch_prechangeupper_sanity_checks(struct net_device *netdev,</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	netdev_for_each_lower_dev(upper_dev, other_dev, iter) {</div><div class='add'>+		if (!dpaa2_switch_port_dev_check(other_dev))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		other_port_priv = netdev_priv(other_dev);</div><div class='add'>+		if (other_port_priv-&gt;ethsw_data != port_priv-&gt;ethsw_data) {</div><div class='add'>+			NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+					   "Interface from a different DPSW is in the bridge already");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dpaa2_switch_port_netdevice_event(struct notifier_block *nb,</div><div class='del'>-					     unsigned long event, void *ptr)</div><div class='add'>+static int dpaa2_switch_port_prechangeupper(struct net_device *netdev,</div><div class='add'>+					    struct netdev_notifier_changeupper_info *info)</div><div class='ctx'> {</div><div class='del'>-	struct net_device *netdev = netdev_notifier_info_to_dev(ptr);</div><div class='del'>-	struct netdev_notifier_changeupper_info *info = ptr;</div><div class='ctx'> 	struct netlink_ext_ack *extack;</div><div class='ctx'> 	struct net_device *upper_dev;</div><div class='del'>-	int err = 0;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!dpaa2_switch_port_dev_check(netdev))</div><div class='del'>-		return NOTIFY_DONE;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	extack = netdev_notifier_info_to_extack(&amp;info-&gt;info);</div><div class='del'>-</div><div class='del'>-	switch (event) {</div><div class='del'>-	case NETDEV_PRECHANGEUPPER:</div><div class='del'>-		upper_dev = info-&gt;upper_dev;</div><div class='del'>-		if (!netif_is_bridge_master(upper_dev))</div><div class='del'>-			break;</div><div class='del'>-</div><div class='add'>+	upper_dev = info-&gt;upper_dev;</div><div class='add'>+	if (netif_is_bridge_master(upper_dev)) {</div><div class='ctx'> 		err = dpaa2_switch_prechangeupper_sanity_checks(netdev,</div><div class='ctx'> 								upper_dev,</div><div class='ctx'> 								extack);</div><div class='ctx'> 		if (err)</div><div class='del'>-			goto out;</div><div class='add'>+			return err;</div><div class='ctx'> </div><div class='ctx'> 		if (!info-&gt;linking)</div><div class='ctx'> 			dpaa2_switch_port_pre_bridge_leave(netdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dpaa2_switch_port_changeupper(struct net_device *netdev,</div><div class='add'>+					 struct netdev_notifier_changeupper_info *info)</div><div class='add'>+{</div><div class='add'>+	struct netlink_ext_ack *extack;</div><div class='add'>+	struct net_device *upper_dev;</div><div class='add'>+</div><div class='add'>+	if (!dpaa2_switch_port_dev_check(netdev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	extack = netdev_notifier_info_to_extack(&amp;info-&gt;info);</div><div class='add'>+</div><div class='add'>+	upper_dev = info-&gt;upper_dev;</div><div class='add'>+	if (netif_is_bridge_master(upper_dev)) {</div><div class='add'>+		if (info-&gt;linking)</div><div class='add'>+			return dpaa2_switch_port_bridge_join(netdev,</div><div class='add'>+							     upper_dev,</div><div class='add'>+							     extack);</div><div class='add'>+		else</div><div class='add'>+			return dpaa2_switch_port_bridge_leave(netdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dpaa2_switch_port_netdevice_event(struct notifier_block *nb,</div><div class='add'>+					     unsigned long event, void *ptr)</div><div class='add'>+{</div><div class='add'>+	struct net_device *netdev = netdev_notifier_info_to_dev(ptr);</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	switch (event) {</div><div class='add'>+	case NETDEV_PRECHANGEUPPER:</div><div class='add'>+		err = dpaa2_switch_port_prechangeupper(netdev, ptr);</div><div class='add'>+		if (err)</div><div class='add'>+			return notifier_from_errno(err);</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	case NETDEV_CHANGEUPPER:</div><div class='del'>-		upper_dev = info-&gt;upper_dev;</div><div class='del'>-		if (netif_is_bridge_master(upper_dev)) {</div><div class='del'>-			if (info-&gt;linking)</div><div class='del'>-				err = dpaa2_switch_port_bridge_join(netdev,</div><div class='del'>-								    upper_dev,</div><div class='del'>-								    extack);</div><div class='del'>-			else</div><div class='del'>-				err = dpaa2_switch_port_bridge_leave(netdev);</div><div class='del'>-		}</div><div class='add'>+		err = dpaa2_switch_port_changeupper(netdev, ptr);</div><div class='add'>+		if (err)</div><div class='add'>+			return notifier_from_errno(err);</div><div class='add'>+</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='del'>-	return notifier_from_errno(err);</div><div class='add'>+	return NOTIFY_DONE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> struct ethsw_switchdev_event_work {</div><div class='hunk'>@@ -3301,6 +3329,7 @@ static int dpaa2_switch_probe_port(struct ethsw_core *ethsw,</div><div class='ctx'> 	port_netdev-&gt;features = NETIF_F_HW_VLAN_CTAG_FILTER |</div><div class='ctx'> 				NETIF_F_HW_VLAN_STAG_FILTER |</div><div class='ctx'> 				NETIF_F_HW_TC;</div><div class='add'>+	port_netdev-&gt;priv_flags |= IFF_LIVE_ADDR_CHANGE;</div><div class='ctx'> </div><div class='ctx'> 	err = dpaa2_switch_port_init(port_priv, port_idx);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c<br/>index e993ed04ab57..f7753ea5b57e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/enetc/enetc_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/enetc/enetc_ethtool.c</a></div><div class='hunk'>@@ -690,25 +690,26 @@ static u32 enetc_get_rxfh_indir_size(struct net_device *ndev)</div><div class='ctx'> 	return priv-&gt;si-&gt;num_rss;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int enetc_get_rxfh(struct net_device *ndev, u32 *indir, u8 *key,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int enetc_get_rxfh(struct net_device *ndev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct enetc_ndev_priv *priv = netdev_priv(ndev);</div><div class='ctx'> 	struct enetc_hw *hw = &amp;priv-&gt;si-&gt;hw;</div><div class='ctx'> 	int err = 0, i;</div><div class='ctx'> </div><div class='ctx'> 	/* return hash function */</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	/* return hash key */</div><div class='del'>-	if (key &amp;&amp; hw-&gt;port)</div><div class='add'>+	if (rxfh-&gt;key &amp;&amp; hw-&gt;port)</div><div class='ctx'> 		for (i = 0; i &lt; ENETC_RSSHASH_KEY_SIZE / 4; i++)</div><div class='del'>-			((u32 *)key)[i] = enetc_port_rd(hw, ENETC_PRSSK(i));</div><div class='add'>+			((u32 *)rxfh-&gt;key)[i] = enetc_port_rd(hw,</div><div class='add'>+							      ENETC_PRSSK(i));</div><div class='ctx'> </div><div class='ctx'> 	/* return RSS table */</div><div class='del'>-	if (indir)</div><div class='del'>-		err = enetc_get_rss_table(priv-&gt;si, indir, priv-&gt;si-&gt;num_rss);</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		err = enetc_get_rss_table(priv-&gt;si, rxfh-&gt;indir,</div><div class='add'>+					  priv-&gt;si-&gt;num_rss);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -722,20 +723,22 @@ void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL_GPL(enetc_set_rss_key);</div><div class='ctx'> </div><div class='del'>-static int enetc_set_rxfh(struct net_device *ndev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int enetc_set_rxfh(struct net_device *ndev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct enetc_ndev_priv *priv = netdev_priv(ndev);</div><div class='ctx'> 	struct enetc_hw *hw = &amp;priv-&gt;si-&gt;hw;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* set hash key, if PF */</div><div class='del'>-	if (key &amp;&amp; hw-&gt;port)</div><div class='del'>-		enetc_set_rss_key(hw, key);</div><div class='add'>+	if (rxfh-&gt;key &amp;&amp; hw-&gt;port)</div><div class='add'>+		enetc_set_rss_key(hw, rxfh-&gt;key);</div><div class='ctx'> </div><div class='ctx'> 	/* set RSS table */</div><div class='del'>-	if (indir)</div><div class='del'>-		err = enetc_set_rss_table(priv-&gt;si, indir, priv-&gt;si-&gt;num_rss);</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		err = enetc_set_rss_table(priv-&gt;si, rxfh-&gt;indir,</div><div class='add'>+					  priv-&gt;si-&gt;num_rss);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c<br/>index c153dc083aff..11b14555802c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/enetc/enetc_pf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/enetc/enetc_pf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/enetc/enetc_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/enetc/enetc_pf.c</a></div><div class='hunk'>@@ -920,6 +920,7 @@ static void enetc_imdio_remove(struct enetc_pf *pf)</div><div class='ctx'> static bool enetc_port_has_pcs(struct enetc_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	return (pf-&gt;if_mode == PHY_INTERFACE_MODE_SGMII ||</div><div class='add'>+		pf-&gt;if_mode == PHY_INTERFACE_MODE_1000BASEX ||</div><div class='ctx'> 		pf-&gt;if_mode == PHY_INTERFACE_MODE_2500BASEX ||</div><div class='ctx'> 		pf-&gt;if_mode == PHY_INTERFACE_MODE_USXGMII);</div><div class='ctx'> }</div><div class='hunk'>@@ -1116,6 +1117,8 @@ static int enetc_phylink_create(struct enetc_ndev_priv *priv,</div><div class='ctx'> 		  pf-&gt;phylink_config.supported_interfaces);</div><div class='ctx'> 	__set_bit(PHY_INTERFACE_MODE_SGMII,</div><div class='ctx'> 		  pf-&gt;phylink_config.supported_interfaces);</div><div class='add'>+	__set_bit(PHY_INTERFACE_MODE_1000BASEX,</div><div class='add'>+		  pf-&gt;phylink_config.supported_interfaces);</div><div class='ctx'> 	__set_bit(PHY_INTERFACE_MODE_2500BASEX,</div><div class='ctx'> 		  pf-&gt;phylink_config.supported_interfaces);</div><div class='ctx'> 	__set_bit(PHY_INTERFACE_MODE_USXGMII,</div><div class='head'>diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c<br/>index c3b7694a7485..d42594f32275 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/fec_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/freescale/fec_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/freescale/fec_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/freescale/fec_main.c</a></div><div class='hunk'>@@ -2932,10 +2932,10 @@ static void fec_enet_get_strings(struct net_device *netdev,</div><div class='ctx'> 	switch (stringset) {</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(fec_stats); i++) {</div><div class='del'>-			ethtool_sprintf(&amp;data, "%s", fec_stats[i].name);</div><div class='add'>+			ethtool_puts(&amp;data, fec_stats[i].name);</div><div class='ctx'> 		}</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(fec_xdp_stat_strs); i++) {</div><div class='del'>-			ethtool_sprintf(&amp;data, "%s", fec_xdp_stat_strs[i]);</div><div class='add'>+			ethtool_puts(&amp;data, fec_xdp_stat_strs[i]);</div><div class='ctx'> 		}</div><div class='ctx'> 		page_pool_ethtool_stats_get_strings(data);</div><div class='ctx'> </div><div class='hunk'>@@ -3731,31 +3731,26 @@ static int fec_set_features(struct net_device *netdev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)</div><div class='del'>-{</div><div class='del'>-	struct vlan_ethhdr *vhdr;</div><div class='del'>-	unsigned short vlan_TCI = 0;</div><div class='del'>-</div><div class='del'>-	if (skb-&gt;protocol == htons(ETH_P_ALL)) {</div><div class='del'>-		vhdr = (struct vlan_ethhdr *)(skb-&gt;data);</div><div class='del'>-		vlan_TCI = ntohs(vhdr-&gt;h_vlan_TCI);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return vlan_TCI;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,</div><div class='ctx'> 				 struct net_device *sb_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fec_enet_private *fep = netdev_priv(ndev);</div><div class='del'>-	u16 vlan_tag;</div><div class='add'>+	u16 vlan_tag = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!(fep-&gt;quirks &amp; FEC_QUIRK_HAS_AVB))</div><div class='ctx'> 		return netdev_pick_tx(ndev, skb, NULL);</div><div class='ctx'> </div><div class='del'>-	vlan_tag = fec_enet_get_raw_vlan_tci(skb);</div><div class='del'>-	if (!vlan_tag)</div><div class='add'>+	/* VLAN is present in the payload.*/</div><div class='add'>+	if (eth_type_vlan(skb-&gt;protocol)) {</div><div class='add'>+		struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);</div><div class='add'>+</div><div class='add'>+		vlan_tag = ntohs(vhdr-&gt;h_vlan_TCI);</div><div class='add'>+	/*  VLAN is present in the skb but not yet pushed in the payload.*/</div><div class='add'>+	} else if (skb_vlan_tag_present(skb)) {</div><div class='add'>+		vlan_tag = skb-&gt;vlan_tci;</div><div class='add'>+	} else {</div><div class='ctx'> 		return vlan_tag;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return fec_enet_vlan_pri_to_queue[vlan_tag &gt;&gt; 13];</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/fungible/funeth/funeth_ethtool.c b/drivers/net/ethernet/fungible/funeth/funeth_ethtool.c<br/>index 31aa185f4d17..4edd0adfc6c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/fungible/funeth/funeth_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/fungible/funeth/funeth_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/fungible/funeth/funeth_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/fungible/funeth/funeth_ethtool.c</a></div><div class='hunk'>@@ -655,7 +655,7 @@ static void fun_get_strings(struct net_device *netdev, u32 sset, u8 *data)</div><div class='ctx'> 						i);</div><div class='ctx'> 		}</div><div class='ctx'> 		for (j = 0; j &lt; ARRAY_SIZE(txq_stat_names); j++)</div><div class='del'>-			ethtool_sprintf(&amp;p, txq_stat_names[j]);</div><div class='add'>+			ethtool_puts(&amp;p, txq_stat_names[j]);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; fp-&gt;num_xdpqs; i++) {</div><div class='ctx'> 			for (j = 0; j &lt; ARRAY_SIZE(xdpq_stat_names); j++)</div><div class='hunk'>@@ -663,7 +663,7 @@ static void fun_get_strings(struct net_device *netdev, u32 sset, u8 *data)</div><div class='ctx'> 						xdpq_stat_names[j], i);</div><div class='ctx'> 		}</div><div class='ctx'> 		for (j = 0; j &lt; ARRAY_SIZE(xdpq_stat_names); j++)</div><div class='del'>-			ethtool_sprintf(&amp;p, xdpq_stat_names[j]);</div><div class='add'>+			ethtool_puts(&amp;p, xdpq_stat_names[j]);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; netdev-&gt;real_num_rx_queues; i++) {</div><div class='ctx'> 			for (j = 0; j &lt; ARRAY_SIZE(rxq_stat_names); j++)</div><div class='hunk'>@@ -671,10 +671,10 @@ static void fun_get_strings(struct net_device *netdev, u32 sset, u8 *data)</div><div class='ctx'> 						i);</div><div class='ctx'> 		}</div><div class='ctx'> 		for (j = 0; j &lt; ARRAY_SIZE(rxq_stat_names); j++)</div><div class='del'>-			ethtool_sprintf(&amp;p, rxq_stat_names[j]);</div><div class='add'>+			ethtool_puts(&amp;p, rxq_stat_names[j]);</div><div class='ctx'> </div><div class='ctx'> 		for (j = 0; j &lt; ARRAY_SIZE(tls_stat_names); j++)</div><div class='del'>-			ethtool_sprintf(&amp;p, tls_stat_names[j]);</div><div class='add'>+			ethtool_puts(&amp;p, tls_stat_names[j]);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -977,44 +977,44 @@ static u32 fun_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return sizeof(fp-&gt;rss_key);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fun_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			u8 *hfunc)</div><div class='add'>+static int fun_get_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	const struct funeth_priv *fp = netdev_priv(netdev);</div><div class='ctx'> </div><div class='ctx'> 	if (!fp-&gt;rss_cfg)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, fp-&gt;indir_table,</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, fp-&gt;indir_table,</div><div class='ctx'> 		       sizeof(u32) * fp-&gt;indir_table_nentries);</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, fp-&gt;rss_key, sizeof(fp-&gt;rss_key));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, fp-&gt;rss_key, sizeof(fp-&gt;rss_key));</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = fp-&gt;hash_algo == FUN_ETH_RSS_ALG_TOEPLITZ ?</div><div class='del'>-				ETH_RSS_HASH_TOP : ETH_RSS_HASH_CRC32;</div><div class='add'>+	rxfh-&gt;hfunc = fp-&gt;hash_algo == FUN_ETH_RSS_ALG_TOEPLITZ ?</div><div class='add'>+			ETH_RSS_HASH_TOP : ETH_RSS_HASH_CRC32;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fun_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			const u8 *key, const u8 hfunc)</div><div class='add'>+static int fun_set_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct funeth_priv *fp = netdev_priv(netdev);</div><div class='del'>-	const u32 *rss_indir = indir ? indir : fp-&gt;indir_table;</div><div class='del'>-	const u8 *rss_key = key ? key : fp-&gt;rss_key;</div><div class='add'>+	const u32 *rss_indir = rxfh-&gt;indir ? rxfh-&gt;indir : fp-&gt;indir_table;</div><div class='add'>+	const u8 *rss_key = rxfh-&gt;key ? rxfh-&gt;key : fp-&gt;rss_key;</div><div class='ctx'> 	enum fun_eth_hash_alg algo;</div><div class='ctx'> </div><div class='ctx'> 	if (!fp-&gt;rss_cfg)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc == ETH_RSS_HASH_NO_CHANGE)</div><div class='add'>+	if (rxfh-&gt;hfunc == ETH_RSS_HASH_NO_CHANGE)</div><div class='ctx'> 		algo = fp-&gt;hash_algo;</div><div class='del'>-	else if (hfunc == ETH_RSS_HASH_CRC32)</div><div class='add'>+	else if (rxfh-&gt;hfunc == ETH_RSS_HASH_CRC32)</div><div class='ctx'> 		algo = FUN_ETH_RSS_ALG_CRC32;</div><div class='del'>-	else if (hfunc == ETH_RSS_HASH_TOP)</div><div class='add'>+	else if (rxfh-&gt;hfunc == ETH_RSS_HASH_TOP)</div><div class='ctx'> 		algo = FUN_ETH_RSS_ALG_TOEPLITZ;</div><div class='ctx'> 	else</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1031,10 +1031,10 @@ static int fun_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	fp-&gt;hash_algo = algo;</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(fp-&gt;rss_key, key, sizeof(fp-&gt;rss_key));</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(fp-&gt;indir_table, indir,</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(fp-&gt;rss_key, rxfh-&gt;key, sizeof(fp-&gt;rss_key));</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(fp-&gt;indir_table, rxfh-&gt;indir,</div><div class='ctx'> 		       sizeof(u32) * fp-&gt;indir_table_nentries);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve.h b/drivers/net/ethernet/google/gve/gve.h<br/>index 0d1e681be250..b80349154604 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve.h</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #define _GVE_H_</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/dmapool.h&gt;</div><div class='ctx'> #include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/u64_stats_sync.h&gt;</div><div class='hunk'>@@ -41,12 +42,16 @@</div><div class='ctx'> #define NIC_TX_STATS_REPORT_NUM	0</div><div class='ctx'> #define NIC_RX_STATS_REPORT_NUM	4</div><div class='ctx'> </div><div class='add'>+#define GVE_ADMINQ_BUFFER_SIZE 4096</div><div class='add'>+</div><div class='ctx'> #define GVE_DATA_SLOT_ADDR_PAGE_MASK (~(PAGE_SIZE - 1))</div><div class='ctx'> </div><div class='ctx'> /* PTYPEs are always 10 bits. */</div><div class='ctx'> #define GVE_NUM_PTYPES	1024</div><div class='ctx'> </div><div class='del'>-#define GVE_RX_BUFFER_SIZE_DQO 2048</div><div class='add'>+#define GVE_DEFAULT_RX_BUFFER_SIZE 2048</div><div class='add'>+</div><div class='add'>+#define GVE_DEFAULT_RX_BUFFER_OFFSET 2048</div><div class='ctx'> </div><div class='ctx'> #define GVE_XDP_ACTIONS 5</div><div class='ctx'> </div><div class='hunk'>@@ -672,6 +677,7 @@ struct gve_priv {</div><div class='ctx'> 	/* Admin queue - see gve_adminq.h*/</div><div class='ctx'> 	union gve_adminq_command *adminq;</div><div class='ctx'> 	dma_addr_t adminq_bus_addr;</div><div class='add'>+	struct dma_pool *adminq_pool;</div><div class='ctx'> 	u32 adminq_mask; /* masks prod_cnt to adminq size */</div><div class='ctx'> 	u32 adminq_prod_cnt; /* free-running count of AQ cmds executed */</div><div class='ctx'> 	u32 adminq_cmd_fail; /* free-running count of AQ cmds failed */</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_adminq.c b/drivers/net/ethernet/google/gve/gve_adminq.c<br/>index 79db7a6d42bc..12fbd723ecc6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_adminq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_adminq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_adminq.c</a></div><div class='hunk'>@@ -194,12 +194,19 @@ gve_process_device_options(struct gve_priv *priv,</div><div class='ctx'> </div><div class='ctx'> int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)</div><div class='ctx'> {</div><div class='del'>-	priv-&gt;adminq = dma_alloc_coherent(dev, PAGE_SIZE,</div><div class='del'>-					  &amp;priv-&gt;adminq_bus_addr, GFP_KERNEL);</div><div class='del'>-	if (unlikely(!priv-&gt;adminq))</div><div class='add'>+	priv-&gt;adminq_pool = dma_pool_create("adminq_pool", dev,</div><div class='add'>+					    GVE_ADMINQ_BUFFER_SIZE, 0, 0);</div><div class='add'>+	if (unlikely(!priv-&gt;adminq_pool))</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	priv-&gt;adminq = dma_pool_alloc(priv-&gt;adminq_pool, GFP_KERNEL,</div><div class='add'>+				      &amp;priv-&gt;adminq_bus_addr);</div><div class='add'>+	if (unlikely(!priv-&gt;adminq)) {</div><div class='add'>+		dma_pool_destroy(priv-&gt;adminq_pool);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	priv-&gt;adminq_mask = (PAGE_SIZE / sizeof(union gve_adminq_command)) - 1;</div><div class='add'>+	priv-&gt;adminq_mask =</div><div class='add'>+		(GVE_ADMINQ_BUFFER_SIZE / sizeof(union gve_adminq_command)) - 1;</div><div class='ctx'> 	priv-&gt;adminq_prod_cnt = 0;</div><div class='ctx'> 	priv-&gt;adminq_cmd_fail = 0;</div><div class='ctx'> 	priv-&gt;adminq_timeouts = 0;</div><div class='hunk'>@@ -218,9 +225,20 @@ int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)</div><div class='ctx'> 	priv-&gt;adminq_get_ptype_map_cnt = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup Admin queue with the device */</div><div class='del'>-	iowrite32be(priv-&gt;adminq_bus_addr / PAGE_SIZE,</div><div class='del'>-		    &amp;priv-&gt;reg_bar0-&gt;adminq_pfn);</div><div class='del'>-</div><div class='add'>+	if (priv-&gt;pdev-&gt;revision &lt; 0x1) {</div><div class='add'>+		iowrite32be(priv-&gt;adminq_bus_addr / PAGE_SIZE,</div><div class='add'>+			    &amp;priv-&gt;reg_bar0-&gt;adminq_pfn);</div><div class='add'>+	} else {</div><div class='add'>+		iowrite16be(GVE_ADMINQ_BUFFER_SIZE,</div><div class='add'>+			    &amp;priv-&gt;reg_bar0-&gt;adminq_length);</div><div class='add'>+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT</div><div class='add'>+		iowrite32be(priv-&gt;adminq_bus_addr &gt;&gt; 32,</div><div class='add'>+			    &amp;priv-&gt;reg_bar0-&gt;adminq_base_address_hi);</div><div class='add'>+#endif</div><div class='add'>+		iowrite32be(priv-&gt;adminq_bus_addr,</div><div class='add'>+			    &amp;priv-&gt;reg_bar0-&gt;adminq_base_address_lo);</div><div class='add'>+		iowrite32be(GVE_DRIVER_STATUS_RUN_MASK, &amp;priv-&gt;reg_bar0-&gt;driver_status);</div><div class='add'>+	}</div><div class='ctx'> 	gve_set_admin_queue_ok(priv);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -230,16 +248,27 @@ void gve_adminq_release(struct gve_priv *priv)</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Tell the device the adminq is leaving */</div><div class='del'>-	iowrite32be(0x0, &amp;priv-&gt;reg_bar0-&gt;adminq_pfn);</div><div class='del'>-	while (ioread32be(&amp;priv-&gt;reg_bar0-&gt;adminq_pfn)) {</div><div class='del'>-		/* If this is reached the device is unrecoverable and still</div><div class='del'>-		 * holding memory. Continue looping to avoid memory corruption,</div><div class='del'>-		 * but WARN so it is visible what is going on.</div><div class='del'>-		 */</div><div class='del'>-		if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)</div><div class='del'>-			WARN(1, "Unrecoverable platform error!");</div><div class='del'>-		i++;</div><div class='del'>-		msleep(GVE_ADMINQ_SLEEP_LEN);</div><div class='add'>+	if (priv-&gt;pdev-&gt;revision &lt; 0x1) {</div><div class='add'>+		iowrite32be(0x0, &amp;priv-&gt;reg_bar0-&gt;adminq_pfn);</div><div class='add'>+		while (ioread32be(&amp;priv-&gt;reg_bar0-&gt;adminq_pfn)) {</div><div class='add'>+			/* If this is reached the device is unrecoverable and still</div><div class='add'>+			 * holding memory. Continue looping to avoid memory corruption,</div><div class='add'>+			 * but WARN so it is visible what is going on.</div><div class='add'>+			 */</div><div class='add'>+			if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)</div><div class='add'>+				WARN(1, "Unrecoverable platform error!");</div><div class='add'>+			i++;</div><div class='add'>+			msleep(GVE_ADMINQ_SLEEP_LEN);</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		iowrite32be(GVE_DRIVER_STATUS_RESET_MASK, &amp;priv-&gt;reg_bar0-&gt;driver_status);</div><div class='add'>+		while (!(ioread32be(&amp;priv-&gt;reg_bar0-&gt;device_status)</div><div class='add'>+				&amp; GVE_DEVICE_STATUS_DEVICE_IS_RESET)) {</div><div class='add'>+			if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)</div><div class='add'>+				WARN(1, "Unrecoverable platform error!");</div><div class='add'>+			i++;</div><div class='add'>+			msleep(GVE_ADMINQ_SLEEP_LEN);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> 	gve_clear_device_rings_ok(priv);</div><div class='ctx'> 	gve_clear_device_resources_ok(priv);</div><div class='hunk'>@@ -251,7 +280,8 @@ void gve_adminq_free(struct device *dev, struct gve_priv *priv)</div><div class='ctx'> 	if (!gve_get_admin_queue_ok(priv))</div><div class='ctx'> 		return;</div><div class='ctx'> 	gve_adminq_release(priv);</div><div class='del'>-	dma_free_coherent(dev, PAGE_SIZE, priv-&gt;adminq, priv-&gt;adminq_bus_addr);</div><div class='add'>+	dma_pool_free(priv-&gt;adminq_pool, priv-&gt;adminq, priv-&gt;adminq_bus_addr);</div><div class='add'>+	dma_pool_destroy(priv-&gt;adminq_pool);</div><div class='ctx'> 	gve_clear_admin_queue_ok(priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -697,18 +727,7 @@ static int gve_set_desc_cnt(struct gve_priv *priv,</div><div class='ctx'> 			    struct gve_device_descriptor *descriptor)</div><div class='ctx'> {</div><div class='ctx'> 	priv-&gt;tx_desc_cnt = be16_to_cpu(descriptor-&gt;tx_queue_entries);</div><div class='del'>-	if (priv-&gt;tx_desc_cnt * sizeof(priv-&gt;tx-&gt;desc[0]) &lt; PAGE_SIZE) {</div><div class='del'>-		dev_err(&amp;priv-&gt;pdev-&gt;dev, "Tx desc count %d too low\n",</div><div class='del'>-			priv-&gt;tx_desc_cnt);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> 	priv-&gt;rx_desc_cnt = be16_to_cpu(descriptor-&gt;rx_queue_entries);</div><div class='del'>-	if (priv-&gt;rx_desc_cnt * sizeof(priv-&gt;rx-&gt;desc.desc_ring[0])</div><div class='del'>-	    &lt; PAGE_SIZE) {</div><div class='del'>-		dev_err(&amp;priv-&gt;pdev-&gt;dev, "Rx desc count %d too low\n",</div><div class='del'>-			priv-&gt;rx_desc_cnt);</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -778,8 +797,8 @@ int gve_adminq_describe_device(struct gve_priv *priv)</div><div class='ctx'> 	u16 mtu;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	descriptor = dma_alloc_coherent(&amp;priv-&gt;pdev-&gt;dev, PAGE_SIZE,</div><div class='del'>-					&amp;descriptor_bus, GFP_KERNEL);</div><div class='add'>+	descriptor = dma_pool_alloc(priv-&gt;adminq_pool, GFP_KERNEL,</div><div class='add'>+				    &amp;descriptor_bus);</div><div class='ctx'> 	if (!descriptor)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESCRIBE_DEVICE);</div><div class='hunk'>@@ -787,7 +806,8 @@ int gve_adminq_describe_device(struct gve_priv *priv)</div><div class='ctx'> 						cpu_to_be64(descriptor_bus);</div><div class='ctx'> 	cmd.describe_device.device_descriptor_version =</div><div class='ctx'> 			cpu_to_be32(GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION);</div><div class='del'>-	cmd.describe_device.available_length = cpu_to_be32(PAGE_SIZE);</div><div class='add'>+	cmd.describe_device.available_length =</div><div class='add'>+		cpu_to_be32(GVE_ADMINQ_BUFFER_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	err = gve_adminq_execute_cmd(priv, &amp;cmd);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -868,8 +888,7 @@ int gve_adminq_describe_device(struct gve_priv *priv)</div><div class='ctx'> 				      dev_op_jumbo_frames, dev_op_dqo_qpl);</div><div class='ctx'> </div><div class='ctx'> free_device_descriptor:</div><div class='del'>-	dma_free_coherent(&amp;priv-&gt;pdev-&gt;dev, PAGE_SIZE, descriptor,</div><div class='del'>-			  descriptor_bus);</div><div class='add'>+	dma_pool_free(priv-&gt;adminq_pool, descriptor, descriptor_bus);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -898,6 +917,7 @@ int gve_adminq_register_page_list(struct gve_priv *priv,</div><div class='ctx'> 		.page_list_id = cpu_to_be32(qpl-&gt;id),</div><div class='ctx'> 		.num_pages = cpu_to_be32(num_entries),</div><div class='ctx'> 		.page_address_list_addr = cpu_to_be64(page_list_bus),</div><div class='add'>+		.page_size = cpu_to_be64(PAGE_SIZE),</div><div class='ctx'> 	};</div><div class='ctx'> </div><div class='ctx'> 	err = gve_adminq_execute_cmd(priv, &amp;cmd);</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_adminq.h b/drivers/net/ethernet/google/gve/gve_adminq.h<br/>index 38a22279e863..5865ccdccbd0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_adminq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_adminq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_adminq.h</a></div><div class='hunk'>@@ -219,9 +219,10 @@ struct gve_adminq_register_page_list {</div><div class='ctx'> 	__be32 page_list_id;</div><div class='ctx'> 	__be32 num_pages;</div><div class='ctx'> 	__be64 page_address_list_addr;</div><div class='add'>+	__be64 page_size;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static_assert(sizeof(struct gve_adminq_register_page_list) == 16);</div><div class='add'>+static_assert(sizeof(struct gve_adminq_register_page_list) == 24);</div><div class='ctx'> </div><div class='ctx'> struct gve_adminq_unregister_page_list {</div><div class='ctx'> 	__be32 page_list_id;</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_dqo.h b/drivers/net/ethernet/google/gve/gve_dqo.h<br/>index 1eb4d5fd8561..c36b93f0de15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_dqo.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_dqo.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_dqo.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_dqo.h</a></div><div class='hunk'>@@ -33,6 +33,9 @@</div><div class='ctx'> #define GVE_DEALLOCATE_COMPL_TIMEOUT 60</div><div class='ctx'> </div><div class='ctx'> netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);</div><div class='add'>+netdev_features_t gve_features_check_dqo(struct sk_buff *skb,</div><div class='add'>+					 struct net_device *dev,</div><div class='add'>+					 netdev_features_t features);</div><div class='ctx'> bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);</div><div class='ctx'> int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);</div><div class='ctx'> int gve_tx_alloc_rings_dqo(struct gve_priv *priv);</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_ethtool.c b/drivers/net/ethernet/google/gve/gve_ethtool.c<br/>index 233e5946905e..e5397aa1e48f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_ethtool.c</a></div><div class='hunk'>@@ -519,7 +519,7 @@ static int gve_set_tunable(struct net_device *netdev,</div><div class='ctx'> 	case ETHTOOL_RX_COPYBREAK:</div><div class='ctx'> 	{</div><div class='ctx'> 		u32 max_copybreak = gve_is_gqi(priv) ?</div><div class='del'>-			(PAGE_SIZE / 2) : priv-&gt;data_buffer_size_dqo;</div><div class='add'>+			GVE_DEFAULT_RX_BUFFER_SIZE : priv-&gt;data_buffer_size_dqo;</div><div class='ctx'> </div><div class='ctx'> 		len = *(u32 *)value;</div><div class='ctx'> 		if (len &gt; max_copybreak)</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_main.c b/drivers/net/ethernet/google/gve/gve_main.c<br/>index 2d42e733837b..619bf63ec935 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_main.c</a></div><div class='hunk'>@@ -79,6 +79,18 @@ static int gve_verify_driver_compatibility(struct gve_priv *priv)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static netdev_features_t gve_features_check(struct sk_buff *skb,</div><div class='add'>+					    struct net_device *dev,</div><div class='add'>+					    netdev_features_t features)</div><div class='add'>+{</div><div class='add'>+	struct gve_priv *priv = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	if (!gve_is_gqi(priv))</div><div class='add'>+		return gve_features_check_dqo(skb, dev, features);</div><div class='add'>+</div><div class='add'>+	return features;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static netdev_tx_t gve_start_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct gve_priv *priv = netdev_priv(dev);</div><div class='hunk'>@@ -1316,7 +1328,7 @@ static int gve_open(struct net_device *dev)</div><div class='ctx'> 		/* Hard code this for now. This may be tuned in the future for</div><div class='ctx'> 		 * performance.</div><div class='ctx'> 		 */</div><div class='del'>-		priv-&gt;data_buffer_size_dqo = GVE_RX_BUFFER_SIZE_DQO;</div><div class='add'>+		priv-&gt;data_buffer_size_dqo = GVE_DEFAULT_RX_BUFFER_SIZE;</div><div class='ctx'> 	}</div><div class='ctx'> 	err = gve_create_rings(priv);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -1652,7 +1664,7 @@ static int verify_xdp_configuration(struct net_device *dev)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (dev-&gt;mtu &gt; (PAGE_SIZE / 2) - sizeof(struct ethhdr) - GVE_RX_PAD) {</div><div class='add'>+	if (dev-&gt;mtu &gt; GVE_DEFAULT_RX_BUFFER_SIZE - sizeof(struct ethhdr) - GVE_RX_PAD) {</div><div class='ctx'> 		netdev_warn(dev, "XDP is not supported for mtu %d.\n",</div><div class='ctx'> 			    dev-&gt;mtu);</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='hunk'>@@ -1879,6 +1891,7 @@ err:</div><div class='ctx'> </div><div class='ctx'> static const struct net_device_ops gve_netdev_ops = {</div><div class='ctx'> 	.ndo_start_xmit		=	gve_start_xmit,</div><div class='add'>+	.ndo_features_check	=	gve_features_check,</div><div class='ctx'> 	.ndo_open		=	gve_open,</div><div class='ctx'> 	.ndo_stop		=	gve_close,</div><div class='ctx'> 	.ndo_get_stats64	=	gve_get_stats,</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_register.h b/drivers/net/ethernet/google/gve/gve_register.h<br/>index fb655463c357..8e72b97008d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_register.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_register.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_register.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_register.h</a></div><div class='hunk'>@@ -18,11 +18,20 @@ struct gve_registers {</div><div class='ctx'> 	__be32	adminq_event_counter;</div><div class='ctx'> 	u8	reserved[3];</div><div class='ctx'> 	u8	driver_version;</div><div class='add'>+	__be32	adminq_base_address_hi;</div><div class='add'>+	__be32	adminq_base_address_lo;</div><div class='add'>+	__be16	adminq_length;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum gve_device_status_flags {</div><div class='ctx'> 	GVE_DEVICE_STATUS_RESET_MASK		= BIT(1),</div><div class='ctx'> 	GVE_DEVICE_STATUS_LINK_STATUS_MASK	= BIT(2),</div><div class='ctx'> 	GVE_DEVICE_STATUS_REPORT_STATS_MASK	= BIT(3),</div><div class='add'>+	GVE_DEVICE_STATUS_DEVICE_IS_RESET	= BIT(4),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum gve_driver_status_flags {</div><div class='add'>+	GVE_DRIVER_STATUS_RUN_MASK		= BIT(0),</div><div class='add'>+	GVE_DRIVER_STATUS_RESET_MASK		= BIT(1),</div><div class='ctx'> };</div><div class='ctx'> #endif /* _GVE_REGISTER_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_rx.c b/drivers/net/ethernet/google/gve/gve_rx.c<br/>index 73655347902d..7a8dc5386fff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_rx.c</a></div><div class='hunk'>@@ -211,9 +211,9 @@ static int gve_rx_alloc_ring(struct gve_priv *priv, int idx)</div><div class='ctx'> {</div><div class='ctx'> 	struct gve_rx_ring *rx = &amp;priv-&gt;rx[idx];</div><div class='ctx'> 	struct device *hdev = &amp;priv-&gt;pdev-&gt;dev;</div><div class='del'>-	u32 slots, npages;</div><div class='ctx'> 	int filled_pages;</div><div class='ctx'> 	size_t bytes;</div><div class='add'>+	u32 slots;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	netif_dbg(priv, drv, priv-&gt;dev, "allocating rx ring\n");</div><div class='hunk'>@@ -270,12 +270,6 @@ static int gve_rx_alloc_ring(struct gve_priv *priv, int idx)</div><div class='ctx'> </div><div class='ctx'> 	/* alloc rx desc ring */</div><div class='ctx'> 	bytes = sizeof(struct gve_rx_desc) * priv-&gt;rx_desc_cnt;</div><div class='del'>-	npages = bytes / PAGE_SIZE;</div><div class='del'>-	if (npages * PAGE_SIZE != bytes) {</div><div class='del'>-		err = -EIO;</div><div class='del'>-		goto abort_with_q_resources;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	rx-&gt;desc.desc_ring = dma_alloc_coherent(hdev, bytes, &amp;rx-&gt;desc.bus,</div><div class='ctx'> 						GFP_KERNEL);</div><div class='ctx'> 	if (!rx-&gt;desc.desc_ring) {</div><div class='hunk'>@@ -289,7 +283,7 @@ static int gve_rx_alloc_ring(struct gve_priv *priv, int idx)</div><div class='ctx'> 	/* Allocating half-page buffers allows page-flipping which is faster</div><div class='ctx'> 	 * than copying or allocating new pages.</div><div class='ctx'> 	 */</div><div class='del'>-	rx-&gt;packet_buffer_size = PAGE_SIZE / 2;</div><div class='add'>+	rx-&gt;packet_buffer_size = GVE_DEFAULT_RX_BUFFER_SIZE;</div><div class='ctx'> 	gve_rx_ctx_clear(&amp;rx-&gt;ctx);</div><div class='ctx'> 	gve_rx_add_to_block(priv, idx);</div><div class='ctx'> </div><div class='hunk'>@@ -405,10 +399,10 @@ static struct sk_buff *gve_rx_add_frags(struct napi_struct *napi,</div><div class='ctx'> </div><div class='ctx'> static void gve_rx_flip_buff(struct gve_rx_slot_page_info *page_info, __be64 *slot_addr)</div><div class='ctx'> {</div><div class='del'>-	const __be64 offset = cpu_to_be64(PAGE_SIZE / 2);</div><div class='add'>+	const __be64 offset = cpu_to_be64(GVE_DEFAULT_RX_BUFFER_OFFSET);</div><div class='ctx'> </div><div class='ctx'> 	/* "flip" to other packet buffer on this page */</div><div class='del'>-	page_info-&gt;page_offset ^= PAGE_SIZE / 2;</div><div class='add'>+	page_info-&gt;page_offset ^= GVE_DEFAULT_RX_BUFFER_OFFSET;</div><div class='ctx'> 	*(slot_addr) ^= offset;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -513,8 +507,7 @@ static struct sk_buff *gve_rx_copy_to_pool(struct gve_rx_ring *rx,</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='ctx'> 	gve_dec_pagecnt_bias(copy_page_info);</div><div class='del'>-	copy_page_info-&gt;page_offset += rx-&gt;packet_buffer_size;</div><div class='del'>-	copy_page_info-&gt;page_offset &amp;= (PAGE_SIZE - 1);</div><div class='add'>+	copy_page_info-&gt;page_offset ^= GVE_DEFAULT_RX_BUFFER_OFFSET;</div><div class='ctx'> </div><div class='ctx'> 	if (copy_page_info-&gt;can_flip) {</div><div class='ctx'> 		/* We have used both halves of this copy page, it</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_tx.c b/drivers/net/ethernet/google/gve/gve_tx.c<br/>index 9f6ffc4a54f0..07ba124780df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_tx.c</a></div><div class='hunk'>@@ -819,7 +819,7 @@ int gve_xdp_xmit_one(struct gve_priv *priv, struct gve_tx_ring *tx,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define GVE_TX_START_THRESH	PAGE_SIZE</div><div class='add'>+#define GVE_TX_START_THRESH	4096</div><div class='ctx'> </div><div class='ctx'> static int gve_clean_tx_done(struct gve_priv *priv, struct gve_tx_ring *tx,</div><div class='ctx'> 			     u32 to_do, bool try_to_wake)</div><div class='head'>diff --git a/drivers/net/ethernet/google/gve/gve_tx_dqo.c b/drivers/net/ethernet/google/gve/gve_tx_dqo.c<br/>index 1e19b834a613..f59c4710f118 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_tx_dqo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/google/gve/gve_tx_dqo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/google/gve/gve_tx_dqo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/google/gve/gve_tx_dqo.c</a></div><div class='hunk'>@@ -843,6 +843,16 @@ static bool gve_can_send_tso(const struct sk_buff *skb)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+netdev_features_t gve_features_check_dqo(struct sk_buff *skb,</div><div class='add'>+					 struct net_device *dev,</div><div class='add'>+					 netdev_features_t features)</div><div class='add'>+{</div><div class='add'>+	if (skb_is_gso(skb) &amp;&amp; !gve_can_send_tso(skb))</div><div class='add'>+		return features &amp; ~NETIF_F_GSO_MASK;</div><div class='add'>+</div><div class='add'>+	return features;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* Attempt to transmit specified SKB.</div><div class='ctx'>  *</div><div class='ctx'>  * Returns 0 if the SKB was transmitted or dropped.</div><div class='hunk'>@@ -854,11 +864,10 @@ static int gve_try_tx_skb(struct gve_priv *priv, struct gve_tx_ring *tx,</div><div class='ctx'> 	int num_buffer_descs;</div><div class='ctx'> 	int total_num_descs;</div><div class='ctx'> </div><div class='del'>-	if (tx-&gt;dqo.qpl) {</div><div class='del'>-		if (skb_is_gso(skb))</div><div class='del'>-			if (unlikely(ipv6_hopopt_jumbo_remove(skb)))</div><div class='del'>-				goto drop;</div><div class='add'>+	if (skb_is_gso(skb) &amp;&amp; unlikely(ipv6_hopopt_jumbo_remove(skb)))</div><div class='add'>+		goto drop;</div><div class='ctx'> </div><div class='add'>+	if (tx-&gt;dqo.qpl) {</div><div class='ctx'> 		/* We do not need to verify the number of buffers used per</div><div class='ctx'> 		 * packet or per segment in case of TSO as with 2K size buffers</div><div class='ctx'> 		 * none of the TX packet rules would be violated.</div><div class='hunk'>@@ -868,24 +877,8 @@ static int gve_try_tx_skb(struct gve_priv *priv, struct gve_tx_ring *tx,</div><div class='ctx'> 		 */</div><div class='ctx'> 		num_buffer_descs = DIV_ROUND_UP(skb-&gt;len, GVE_TX_BUF_SIZE_DQO);</div><div class='ctx'> 	} else {</div><div class='del'>-		if (skb_is_gso(skb)) {</div><div class='del'>-			/* If TSO doesn't meet HW requirements, attempt to linearize the</div><div class='del'>-			 * packet.</div><div class='del'>-			 */</div><div class='del'>-			if (unlikely(!gve_can_send_tso(skb) &amp;&amp;</div><div class='del'>-				     skb_linearize(skb) &lt; 0)) {</div><div class='del'>-				net_err_ratelimited("%s: Failed to transmit TSO packet\n",</div><div class='del'>-						    priv-&gt;dev-&gt;name);</div><div class='del'>-				goto drop;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (unlikely(ipv6_hopopt_jumbo_remove(skb)))</div><div class='del'>-				goto drop;</div><div class='del'>-</div><div class='del'>-			num_buffer_descs = gve_num_buffer_descs_needed(skb);</div><div class='del'>-		} else {</div><div class='del'>-			num_buffer_descs = gve_num_buffer_descs_needed(skb);</div><div class='del'>-</div><div class='add'>+		num_buffer_descs = gve_num_buffer_descs_needed(skb);</div><div class='add'>+		if (!skb_is_gso(skb)) {</div><div class='ctx'> 			if (unlikely(num_buffer_descs &gt; GVE_TX_MAX_DATA_DESCS)) {</div><div class='ctx'> 				if (unlikely(skb_linearize(skb) &lt; 0))</div><div class='ctx'> 					goto drop;</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c<br/>index 8f391e2adcc0..bdb7afaabdd0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c</a></div><div class='hunk'>@@ -678,7 +678,7 @@ static void hns_gmac_get_strings(u32 stringset, u8 *data)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(g_gmac_stats_string); i++)</div><div class='del'>-		ethtool_sprintf(&amp;buff, g_gmac_stats_string[i].desc);</div><div class='add'>+		ethtool_puts(&amp;buff, g_gmac_stats_string[i].desc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hns_gmac_get_sset_count(int stringset)</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c<br/>index 928d934cb21a..f75668c47935 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c</a></div><div class='hunk'>@@ -66,6 +66,27 @@ static enum mac_mode hns_get_enet_interface(const struct hns_mac_cb *mac_cb)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 hns_mac_link_anti_shake(struct mac_driver *mac_ctrl_drv)</div><div class='add'>+{</div><div class='add'>+#define HNS_MAC_LINK_WAIT_TIME 5</div><div class='add'>+#define HNS_MAC_LINK_WAIT_CNT 40</div><div class='add'>+</div><div class='add'>+	u32 link_status = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!mac_ctrl_drv-&gt;get_link_status)</div><div class='add'>+		return link_status;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; HNS_MAC_LINK_WAIT_CNT; i++) {</div><div class='add'>+		msleep(HNS_MAC_LINK_WAIT_TIME);</div><div class='add'>+		mac_ctrl_drv-&gt;get_link_status(mac_ctrl_drv, &amp;link_status);</div><div class='add'>+		if (!link_status)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return link_status;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void hns_mac_get_link_status(struct hns_mac_cb *mac_cb, u32 *link_status)</div><div class='ctx'> {</div><div class='ctx'> 	struct mac_driver *mac_ctrl_drv;</div><div class='hunk'>@@ -83,6 +104,14 @@ void hns_mac_get_link_status(struct hns_mac_cb *mac_cb, u32 *link_status)</div><div class='ctx'> 							       &amp;sfp_prsnt);</div><div class='ctx'> 		if (!ret)</div><div class='ctx'> 			*link_status = *link_status &amp;&amp; sfp_prsnt;</div><div class='add'>+</div><div class='add'>+		/* for FIBER port, it may have a fake link up.</div><div class='add'>+		 * when the link status changes from down to up, we need to do</div><div class='add'>+		 * anti-shake. the anti-shake time is base on tests.</div><div class='add'>+		 * only FIBER port need to do this.</div><div class='add'>+		 */</div><div class='add'>+		if (*link_status &amp;&amp; !mac_cb-&gt;link)</div><div class='add'>+			*link_status = hns_mac_link_anti_shake(mac_ctrl_drv);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mac_cb-&gt;link = *link_status;</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c<br/>index fc26ffaae620..c58833eb4830 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c</a></div><div class='hunk'>@@ -752,7 +752,7 @@ static void hns_xgmac_get_strings(u32 stringset, u8 *data)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(g_xgmac_stats_string); i++)</div><div class='del'>-		ethtool_sprintf(&amp;buff, g_xgmac_stats_string[i].desc);</div><div class='add'>+		ethtool_puts(&amp;buff, g_xgmac_stats_string[i].desc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.c b/drivers/net/ethernet/hisilicon/hns/hns_enet.c<br/>index 0900abf5c508..8a713eed4465 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_enet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_enet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_enet.c</a></div><div class='hunk'>@@ -142,7 +142,8 @@ MODULE_DEVICE_TABLE(acpi, hns_enet_acpi_match);</div><div class='ctx'> </div><div class='ctx'> static void fill_desc(struct hnae_ring *ring, void *priv,</div><div class='ctx'> 		      int size, dma_addr_t dma, int frag_end,</div><div class='del'>-		      int buf_num, enum hns_desc_type type, int mtu)</div><div class='add'>+		      int buf_num, enum hns_desc_type type, int mtu,</div><div class='add'>+		      bool is_gso)</div><div class='ctx'> {</div><div class='ctx'> 	struct hnae_desc *desc = &amp;ring-&gt;desc[ring-&gt;next_to_use];</div><div class='ctx'> 	struct hnae_desc_cb *desc_cb = &amp;ring-&gt;desc_cb[ring-&gt;next_to_use];</div><div class='hunk'>@@ -275,6 +276,15 @@ static int hns_nic_maybe_stop_tso(</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int hns_nic_maybe_stop_tx_v2(struct sk_buff **out_skb, int *bnum,</div><div class='add'>+				    struct hnae_ring *ring)</div><div class='add'>+{</div><div class='add'>+	if (skb_is_gso(*out_skb))</div><div class='add'>+		return hns_nic_maybe_stop_tso(out_skb, bnum, ring);</div><div class='add'>+	else</div><div class='add'>+		return hns_nic_maybe_stop_tx(out_skb, bnum, ring);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void fill_tso_desc(struct hnae_ring *ring, void *priv,</div><div class='ctx'> 			  int size, dma_addr_t dma, int frag_end,</div><div class='ctx'> 			  int buf_num, enum hns_desc_type type, int mtu)</div><div class='hunk'>@@ -300,6 +310,19 @@ static void fill_tso_desc(struct hnae_ring *ring, void *priv,</div><div class='ctx'> 				mtu);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void fill_desc_v2(struct hnae_ring *ring, void *priv,</div><div class='add'>+			 int size, dma_addr_t dma, int frag_end,</div><div class='add'>+			 int buf_num, enum hns_desc_type type, int mtu,</div><div class='add'>+			 bool is_gso)</div><div class='add'>+{</div><div class='add'>+	if (is_gso)</div><div class='add'>+		fill_tso_desc(ring, priv, size, dma, frag_end, buf_num, type,</div><div class='add'>+			      mtu);</div><div class='add'>+	else</div><div class='add'>+		fill_v2_desc(ring, priv, size, dma, frag_end, buf_num, type,</div><div class='add'>+			     mtu);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev,</div><div class='ctx'> 				struct sk_buff *skb,</div><div class='ctx'> 				struct hns_nic_ring_data *ring_data)</div><div class='hunk'>@@ -313,6 +336,7 @@ netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev,</div><div class='ctx'> 	int seg_num;</div><div class='ctx'> 	dma_addr_t dma;</div><div class='ctx'> 	int size, next_to_use;</div><div class='add'>+	bool is_gso;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	switch (priv-&gt;ops.maybe_stop_tx(&amp;skb, &amp;buf_num, ring)) {</div><div class='hunk'>@@ -339,8 +363,9 @@ netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev,</div><div class='ctx'> 		ring-&gt;stats.sw_err_cnt++;</div><div class='ctx'> 		goto out_err_tx_ok;</div><div class='ctx'> 	}</div><div class='add'>+	is_gso = skb_is_gso(skb);</div><div class='ctx'> 	priv-&gt;ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,</div><div class='del'>-			    buf_num, DESC_TYPE_SKB, ndev-&gt;mtu);</div><div class='add'>+			    buf_num, DESC_TYPE_SKB, ndev-&gt;mtu, is_gso);</div><div class='ctx'> </div><div class='ctx'> 	/* fill the fragments */</div><div class='ctx'> 	for (i = 1; i &lt; seg_num; i++) {</div><div class='hunk'>@@ -354,7 +379,7 @@ netdev_tx_t hns_nic_net_xmit_hw(struct net_device *ndev,</div><div class='ctx'> 		}</div><div class='ctx'> 		priv-&gt;ops.fill_desc(ring, skb_frag_page(frag), size, dma,</div><div class='ctx'> 				    seg_num - 1 == i ? 1 : 0, buf_num,</div><div class='del'>-				    DESC_TYPE_PAGE, ndev-&gt;mtu);</div><div class='add'>+				    DESC_TYPE_PAGE, ndev-&gt;mtu, is_gso);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*complete translate all packets*/</div><div class='hunk'>@@ -1776,15 +1801,6 @@ static int hns_nic_set_features(struct net_device *netdev,</div><div class='ctx'> 			netdev_info(netdev, "enet v1 do not support tso!\n");</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		if (features &amp; (NETIF_F_TSO | NETIF_F_TSO6)) {</div><div class='del'>-			priv-&gt;ops.fill_desc = fill_tso_desc;</div><div class='del'>-			priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tso;</div><div class='del'>-			/* The chip only support 7*4096 */</div><div class='del'>-			netif_set_tso_max_size(netdev, 7 * 4096);</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;ops.fill_desc = fill_v2_desc;</div><div class='del'>-			priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tx;</div><div class='del'>-		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> 	netdev-&gt;features = features;</div><div class='hunk'>@@ -2159,16 +2175,9 @@ static void hns_nic_set_priv_ops(struct net_device *netdev)</div><div class='ctx'> 		priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tx;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		priv-&gt;ops.get_rxd_bnum = get_v2rx_desc_bnum;</div><div class='del'>-		if ((netdev-&gt;features &amp; NETIF_F_TSO) ||</div><div class='del'>-		    (netdev-&gt;features &amp; NETIF_F_TSO6)) {</div><div class='del'>-			priv-&gt;ops.fill_desc = fill_tso_desc;</div><div class='del'>-			priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tso;</div><div class='del'>-			/* This chip only support 7*4096 */</div><div class='del'>-			netif_set_tso_max_size(netdev, 7 * 4096);</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;ops.fill_desc = fill_v2_desc;</div><div class='del'>-			priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tx;</div><div class='del'>-		}</div><div class='add'>+		priv-&gt;ops.fill_desc = fill_desc_v2;</div><div class='add'>+		priv-&gt;ops.maybe_stop_tx = hns_nic_maybe_stop_tx_v2;</div><div class='add'>+		netif_set_tso_max_size(netdev, 7 * 4096);</div><div class='ctx'> 		/* enable tso when init</div><div class='ctx'> 		 * control tso on/off through TSE bit in bd</div><div class='ctx'> 		 */</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_enet.h b/drivers/net/ethernet/hisilicon/hns/hns_enet.h<br/>index ffa9d6573f54..3f3ee032f631 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_enet.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_enet.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_enet.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_enet.h</a></div><div class='hunk'>@@ -44,7 +44,8 @@ struct hns_nic_ring_data {</div><div class='ctx'> struct hns_nic_ops {</div><div class='ctx'> 	void (*fill_desc)(struct hnae_ring *ring, void *priv,</div><div class='ctx'> 			  int size, dma_addr_t dma, int frag_end,</div><div class='del'>-			  int buf_num, enum hns_desc_type type, int mtu);</div><div class='add'>+			  int buf_num, enum hns_desc_type type, int mtu,</div><div class='add'>+			  bool is_gso);</div><div class='ctx'> 	int (*maybe_stop_tx)(struct sk_buff **out_skb,</div><div class='ctx'> 			     int *bnum, struct hnae_ring *ring);</div><div class='ctx'> 	void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c b/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c<br/>index b54f3706fb97..a5bb306b2cf1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns/hns_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns/hns_ethtool.c</a></div><div class='hunk'>@@ -912,42 +912,41 @@ static void hns_get_strings(struct net_device *netdev, u32 stringset, u8 *data)</div><div class='ctx'> </div><div class='ctx'> 	if (stringset == ETH_SS_TEST) {</div><div class='ctx'> 		if (priv-&gt;ae_handle-&gt;phy_if != PHY_INTERFACE_MODE_XGMII)</div><div class='del'>-			ethtool_sprintf(&amp;buff,</div><div class='del'>-					hns_nic_test_strs[MAC_INTERNALLOOP_MAC]);</div><div class='del'>-		ethtool_sprintf(&amp;buff,</div><div class='del'>-				hns_nic_test_strs[MAC_INTERNALLOOP_SERDES]);</div><div class='add'>+			ethtool_puts(&amp;buff,</div><div class='add'>+				     hns_nic_test_strs[MAC_INTERNALLOOP_MAC]);</div><div class='add'>+		ethtool_puts(&amp;buff, hns_nic_test_strs[MAC_INTERNALLOOP_SERDES]);</div><div class='ctx'> 		if ((netdev-&gt;phydev) &amp;&amp; (!netdev-&gt;phydev-&gt;is_c45))</div><div class='del'>-			ethtool_sprintf(&amp;buff,</div><div class='del'>-					hns_nic_test_strs[MAC_INTERNALLOOP_PHY]);</div><div class='add'>+			ethtool_puts(&amp;buff,</div><div class='add'>+				     hns_nic_test_strs[MAC_INTERNALLOOP_PHY]);</div><div class='ctx'> </div><div class='ctx'> 	} else {</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_packets");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_packets");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_bytes");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_bytes");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_dropped");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_dropped");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "multicast");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "collisions");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_over_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_crc_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_frame_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_fifo_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_missed_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_aborted_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_carrier_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_fifo_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_heartbeat_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_length_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_window_errors");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "rx_compressed");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "tx_compressed");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "netdev_rx_dropped");</div><div class='del'>-		ethtool_sprintf(&amp;buff, "netdev_tx_dropped");</div><div class='del'>-</div><div class='del'>-		ethtool_sprintf(&amp;buff, "netdev_tx_timeout");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_packets");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_packets");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_bytes");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_bytes");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_dropped");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_dropped");</div><div class='add'>+		ethtool_puts(&amp;buff, "multicast");</div><div class='add'>+		ethtool_puts(&amp;buff, "collisions");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_over_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_crc_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_frame_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_fifo_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_missed_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_aborted_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_carrier_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_fifo_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_heartbeat_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_length_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_window_errors");</div><div class='add'>+		ethtool_puts(&amp;buff, "rx_compressed");</div><div class='add'>+		ethtool_puts(&amp;buff, "tx_compressed");</div><div class='add'>+		ethtool_puts(&amp;buff, "netdev_rx_dropped");</div><div class='add'>+		ethtool_puts(&amp;buff, "netdev_tx_dropped");</div><div class='add'>+</div><div class='add'>+		ethtool_puts(&amp;buff, "netdev_tx_timeout");</div><div class='ctx'> </div><div class='ctx'> 		h-&gt;dev-&gt;ops-&gt;get_strings(h, stringset, buff);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1187,7 +1186,7 @@ hns_get_rss_indir_size(struct net_device *netdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-hns_get_rss(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+hns_get_rss(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct hns_nic_priv *priv = netdev_priv(netdev);</div><div class='ctx'> 	struct hnae_ae_ops *ops;</div><div class='hunk'>@@ -1200,15 +1199,16 @@ hns_get_rss(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='ctx'> </div><div class='ctx'> 	ops = priv-&gt;ae_handle-&gt;dev-&gt;ops;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return ops-&gt;get_rss(priv-&gt;ae_handle, indir, key, hfunc);</div><div class='add'>+	return ops-&gt;get_rss(priv-&gt;ae_handle,</div><div class='add'>+			    rxfh-&gt;indir, rxfh-&gt;key, &amp;rxfh-&gt;hfunc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-hns_set_rss(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='del'>-	    const u8 hfunc)</div><div class='add'>+hns_set_rss(struct net_device *netdev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+	    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct hns_nic_priv *priv = netdev_priv(netdev);</div><div class='ctx'> 	struct hnae_ae_ops *ops;</div><div class='hunk'>@@ -1221,12 +1221,14 @@ hns_set_rss(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='ctx'> </div><div class='ctx'> 	ops = priv-&gt;ae_handle-&gt;dev-&gt;ops;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP) {</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP) {</div><div class='ctx'> 		netdev_err(netdev, "Invalid hfunc!\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ops-&gt;set_rss(priv-&gt;ae_handle, indir, key, hfunc);</div><div class='add'>+	return ops-&gt;set_rss(priv-&gt;ae_handle,</div><div class='add'>+			    rxfh-&gt;indir, rxfh-&gt;key, rxfh-&gt;hfunc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hns_get_rxnfc(struct net_device *netdev,</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c<br/>index b618797a7e8d..f1695c889d3a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns3/hns3_enet.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3_enet.c</a></div><div class='hunk'>@@ -1041,7 +1041,7 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	order = get_order(alloc_size);</div><div class='del'>-	if (order &gt; MAX_ORDER) {</div><div class='add'>+	if (order &gt; MAX_PAGE_ORDER) {</div><div class='ctx'> 		if (net_ratelimit())</div><div class='ctx'> 			dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");</div><div class='ctx'> 		return;</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c<br/>index 682239f33082..999a0ee162a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c</a></div><div class='hunk'>@@ -941,19 +941,21 @@ static u32 hns3_get_rss_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return ae_dev-&gt;dev_specs.rss_ind_tbl_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hns3_get_rss(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			u8 *hfunc)</div><div class='add'>+static int hns3_get_rss(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct hnae3_handle *h = hns3_get_handle(netdev);</div><div class='ctx'> </div><div class='ctx'> 	if (!h-&gt;ae_algo-&gt;ops-&gt;get_rss)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	return h-&gt;ae_algo-&gt;ops-&gt;get_rss(h, indir, key, hfunc);</div><div class='add'>+	return h-&gt;ae_algo-&gt;ops-&gt;get_rss(h, rxfh-&gt;indir, rxfh-&gt;key,</div><div class='add'>+					&amp;rxfh-&gt;hfunc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hns3_set_rss(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			const u8 *key, const u8 hfunc)</div><div class='add'>+static int hns3_set_rss(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct hnae3_handle *h = hns3_get_handle(netdev);</div><div class='ctx'> 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h-&gt;pdev);</div><div class='hunk'>@@ -962,19 +964,22 @@ static int hns3_set_rss(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if ((ae_dev-&gt;dev_version &lt; HNAE3_DEVICE_VERSION_V2 &amp;&amp;</div><div class='del'>-	     hfunc != ETH_RSS_HASH_TOP) || (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='del'>-	     hfunc != ETH_RSS_HASH_TOP &amp;&amp; hfunc != ETH_RSS_HASH_XOR)) {</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP) ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_XOR)) {</div><div class='ctx'> 		netdev_err(netdev, "hash func not supported\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!indir) {</div><div class='add'>+	if (!rxfh-&gt;indir) {</div><div class='ctx'> 		netdev_err(netdev,</div><div class='ctx'> 			   "set rss failed for indir is empty\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return h-&gt;ae_algo-&gt;ops-&gt;set_rss(h, indir, key, hfunc);</div><div class='add'>+	return h-&gt;ae_algo-&gt;ops-&gt;set_rss(h, rxfh-&gt;indir, rxfh-&gt;key,</div><div class='add'>+					rxfh-&gt;hfunc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hns3_get_rxnfc(struct net_device *netdev,</div><div class='head'>diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c<br/>index ff3f8f424ad9..9ec471ced3d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c</a></div><div class='hunk'>@@ -981,19 +981,24 @@ static const struct hclge_dbg_item tm_pri_items[] = {</div><div class='ctx'> </div><div class='ctx'> static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)</div><div class='ctx'> {</div><div class='del'>-	char data_str[ARRAY_SIZE(tm_pri_items)][HCLGE_DBG_DATA_STR_LEN];</div><div class='ctx'> 	struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;</div><div class='ctx'> 	char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str;</div><div class='ctx'> 	char content[HCLGE_DBG_TM_INFO_LEN];</div><div class='ctx'> 	u8 pri_num, sch_mode, weight, i, j;</div><div class='add'>+	char *data_str;</div><div class='ctx'> 	int pos, ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = hclge_tm_get_pri_num(hdev, &amp;pri_num);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	data_str = kcalloc(ARRAY_SIZE(tm_pri_items), HCLGE_DBG_DATA_STR_LEN,</div><div class='add'>+			   GFP_KERNEL);</div><div class='add'>+	if (!data_str)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(tm_pri_items); i++)</div><div class='del'>-		result[i] = &amp;data_str[i][0];</div><div class='add'>+		result[i] = &amp;data_str[i * HCLGE_DBG_DATA_STR_LEN];</div><div class='ctx'> </div><div class='ctx'> 	hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,</div><div class='ctx'> 			       NULL, ARRAY_SIZE(tm_pri_items));</div><div class='hunk'>@@ -1002,23 +1007,23 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)</div><div class='ctx'> 	for (i = 0; i &lt; pri_num; i++) {</div><div class='ctx'> 		ret = hclge_tm_get_pri_sch_mode(hdev, i, &amp;sch_mode);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		ret = hclge_tm_get_pri_weight(hdev, i, &amp;weight);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		ret = hclge_tm_get_pri_shaper(hdev, i,</div><div class='ctx'> 					      HCLGE_OPC_TM_PRI_C_SHAPPING,</div><div class='ctx'> 					      &amp;c_shaper_para);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		ret = hclge_tm_get_pri_shaper(hdev, i,</div><div class='ctx'> 					      HCLGE_OPC_TM_PRI_P_SHAPPING,</div><div class='ctx'> 					      &amp;p_shaper_para);</div><div class='ctx'> 		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		sch_mode_str = sch_mode &amp; HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :</div><div class='ctx'> 			       "sp";</div><div class='hunk'>@@ -1035,7 +1040,9 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)</div><div class='ctx'> 		pos += scnprintf(buf + pos, len - pos, "%s", content);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+out:</div><div class='add'>+	kfree(data_str);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct hclge_dbg_item tm_qset_items[] = {</div><div class='head'>diff --git a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c<br/>index f4b680286911..0304f03d4093 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/huawei/hinic/hinic_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/huawei/hinic/hinic_ethtool.c</a></div><div class='hunk'>@@ -1137,7 +1137,7 @@ static int hinic_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int hinic_get_rxfh(struct net_device *netdev,</div><div class='del'>-			  u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct hinic_dev *nic_dev = netdev_priv(netdev);</div><div class='ctx'> 	u8 hash_engine_type = 0;</div><div class='hunk'>@@ -1146,32 +1146,33 @@ static int hinic_get_rxfh(struct net_device *netdev,</div><div class='ctx'> 	if (!(nic_dev-&gt;flags &amp; HINIC_RSS_ENABLE))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc) {</div><div class='del'>-		err = hinic_rss_get_hash_engine(nic_dev,</div><div class='del'>-						nic_dev-&gt;rss_tmpl_idx,</div><div class='del'>-						&amp;hash_engine_type);</div><div class='del'>-		if (err)</div><div class='del'>-			return -EFAULT;</div><div class='add'>+	err = hinic_rss_get_hash_engine(nic_dev,</div><div class='add'>+					nic_dev-&gt;rss_tmpl_idx,</div><div class='add'>+					&amp;hash_engine_type);</div><div class='add'>+	if (err)</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> </div><div class='del'>-		*hfunc = hash_engine_type ? ETH_RSS_HASH_TOP : ETH_RSS_HASH_XOR;</div><div class='del'>-	}</div><div class='add'>+	rxfh-&gt;hfunc = hash_engine_type ? ETH_RSS_HASH_TOP : ETH_RSS_HASH_XOR;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		err = hinic_rss_get_indir_tbl(nic_dev,</div><div class='del'>-					      nic_dev-&gt;rss_tmpl_idx, indir);</div><div class='add'>+					      nic_dev-&gt;rss_tmpl_idx,</div><div class='add'>+					      rxfh-&gt;indir);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='ctx'> 		err = hinic_rss_get_template_tbl(nic_dev,</div><div class='del'>-						 nic_dev-&gt;rss_tmpl_idx, key);</div><div class='add'>+						 nic_dev-&gt;rss_tmpl_idx,</div><div class='add'>+						 rxfh-&gt;key);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hinic_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int hinic_set_rxfh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct hinic_dev *nic_dev = netdev_priv(netdev);</div><div class='ctx'> 	int err = 0;</div><div class='hunk'>@@ -1179,11 +1180,12 @@ static int hinic_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	if (!(nic_dev-&gt;flags &amp; HINIC_RSS_ENABLE))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE) {</div><div class='del'>-		if (hfunc != ETH_RSS_HASH_TOP &amp;&amp; hfunc != ETH_RSS_HASH_XOR)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE) {</div><div class='add'>+		if (rxfh-&gt;hfunc != ETH_RSS_HASH_TOP &amp;&amp;</div><div class='add'>+		    rxfh-&gt;hfunc != ETH_RSS_HASH_XOR)</div><div class='ctx'> 			return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-		nic_dev-&gt;rss_hash_engine = (hfunc == ETH_RSS_HASH_XOR) ?</div><div class='add'>+		nic_dev-&gt;rss_hash_engine = (rxfh-&gt;hfunc == ETH_RSS_HASH_XOR) ?</div><div class='ctx'> 			HINIC_RSS_HASH_ENGINE_TYPE_XOR :</div><div class='ctx'> 			HINIC_RSS_HASH_ENGINE_TYPE_TOEP;</div><div class='ctx'> 		err = hinic_rss_set_hash_engine</div><div class='hunk'>@@ -1193,7 +1195,7 @@ static int hinic_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 			return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = __set_rss_rxfh(netdev, indir, key);</div><div class='add'>+	err = __set_rss_rxfh(netdev, rxfh-&gt;indir, rxfh-&gt;key);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/ibm/ibmvnic.h b/drivers/net/ethernet/ibm/ibmvnic.h<br/>index 4e18b4cefa97..94ac36b1408b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ibm/ibmvnic.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ibm/ibmvnic.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ibm/ibmvnic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ibm/ibmvnic.h</a></div><div class='hunk'>@@ -48,7 +48,7 @@</div><div class='ctx'>  * of 4096 jumbo frames (MTU=9000) we will need about 9K*4K = 36MB plus</div><div class='ctx'>  * some padding.</div><div class='ctx'>  *</div><div class='del'>- * But the size of a single DMA region is limited by MAX_ORDER in the</div><div class='add'>+ * But the size of a single DMA region is limited by MAX_PAGE_ORDER in the</div><div class='ctx'>  * kernel (about 16MB currently).  To support say 4K Jumbo frames, we</div><div class='ctx'>  * use a set of LTBs (struct ltb_set) per pool.</div><div class='ctx'>  *</div><div class='hunk'>@@ -75,7 +75,7 @@</div><div class='ctx'>  * pool for the 4MB. Thus the 16 Rx and Tx queues require 32 * 5 = 160</div><div class='ctx'>  * plus 16 for the TSO pools for a total of 176 LTB mappings per VNIC.</div><div class='ctx'>  */</div><div class='del'>-#define IBMVNIC_ONE_LTB_MAX	((u32)((1 &lt;&lt; MAX_ORDER) * PAGE_SIZE))</div><div class='add'>+#define IBMVNIC_ONE_LTB_MAX	((u32)((1 &lt;&lt; MAX_PAGE_ORDER) * PAGE_SIZE))</div><div class='ctx'> #define IBMVNIC_ONE_LTB_SIZE	min((u32)(8 &lt;&lt; 20), IBMVNIC_ONE_LTB_MAX)</div><div class='ctx'> #define IBMVNIC_LTB_SET_SIZE	(38 &lt;&lt; 20)</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig<br/>index 06ddd7147c7f..d55638ad8704 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/Kconfig</a></div><div class='hunk'>@@ -299,6 +299,17 @@ config ICE</div><div class='ctx'> 	  To compile this driver as a module, choose M here. The module</div><div class='ctx'> 	  will be called ice.</div><div class='ctx'> </div><div class='add'>+config ICE_HWMON</div><div class='add'>+	bool "Intel(R) Ethernet Connection E800 Series Support HWMON support"</div><div class='add'>+	default y</div><div class='add'>+	depends on ICE &amp;&amp; HWMON &amp;&amp; !(ICE=y &amp;&amp; HWMON=m)</div><div class='add'>+	help</div><div class='add'>+	  Say Y if you want to expose thermal sensor data on Intel devices.</div><div class='add'>+</div><div class='add'>+	  Some of our devices contain internal thermal sensors.</div><div class='add'>+	  This data is available via the hwmon sysfs interface and exposes</div><div class='add'>+	  the onboard sensors.</div><div class='add'>+</div><div class='ctx'> config ICE_SWITCHDEV</div><div class='ctx'> 	bool "Switchdev Support"</div><div class='ctx'> 	default y</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.c b/drivers/net/ethernet/intel/e1000/e1000_hw.c<br/>index 4542e2bc28e8..f9328f2e669f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000/e1000_hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000/e1000_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000/e1000_hw.c</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'>  * Shared functions for accessing and configuring the MAC</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "e1000.h"</div><div class='ctx'> </div><div class='ctx'> static s32 e1000_check_downshift(struct e1000_hw *hw);</div><div class='hunk'>@@ -3260,8 +3261,7 @@ static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='ctx'> 	phy_info-&gt;mdix_mode =</div><div class='del'>-	    (e1000_auto_x_mode) ((phy_data &amp; IGP01E1000_PSSR_MDIX) &gt;&gt;</div><div class='del'>-				 IGP01E1000_PSSR_MDIX_SHIFT);</div><div class='add'>+	    (e1000_auto_x_mode)FIELD_GET(IGP01E1000_PSSR_MDIX, phy_data);</div><div class='ctx'> </div><div class='ctx'> 	if ((phy_data &amp; IGP01E1000_PSSR_SPEED_MASK) ==</div><div class='ctx'> 	    IGP01E1000_PSSR_SPEED_1000MBPS) {</div><div class='hunk'>@@ -3272,11 +3272,11 @@ static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> </div><div class='del'>-		phy_info-&gt;local_rx = ((phy_data &amp; SR_1000T_LOCAL_RX_STATUS) &gt;&gt;</div><div class='del'>-				      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?</div><div class='add'>+		phy_info-&gt;local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS,</div><div class='add'>+					       phy_data) ?</div><div class='ctx'> 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;</div><div class='del'>-		phy_info-&gt;remote_rx = ((phy_data &amp; SR_1000T_REMOTE_RX_STATUS) &gt;&gt;</div><div class='del'>-				       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?</div><div class='add'>+		phy_info-&gt;remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS,</div><div class='add'>+						phy_data) ?</div><div class='ctx'> 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;</div><div class='ctx'> </div><div class='ctx'> 		/* Get cable length */</div><div class='hunk'>@@ -3326,14 +3326,12 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='ctx'> 	phy_info-&gt;extended_10bt_distance =</div><div class='del'>-	    ((phy_data &amp; M88E1000_PSCR_10BT_EXT_DIST_ENABLE) &gt;&gt;</div><div class='del'>-	     M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?</div><div class='add'>+	    FIELD_GET(M88E1000_PSCR_10BT_EXT_DIST_ENABLE, phy_data) ?</div><div class='ctx'> 	    e1000_10bt_ext_dist_enable_lower :</div><div class='ctx'> 	    e1000_10bt_ext_dist_enable_normal;</div><div class='ctx'> </div><div class='ctx'> 	phy_info-&gt;polarity_correction =</div><div class='del'>-	    ((phy_data &amp; M88E1000_PSCR_POLARITY_REVERSAL) &gt;&gt;</div><div class='del'>-	     M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?</div><div class='add'>+	    FIELD_GET(M88E1000_PSCR_POLARITY_REVERSAL, phy_data) ?</div><div class='ctx'> 	    e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;</div><div class='ctx'> </div><div class='ctx'> 	/* Check polarity status */</div><div class='hunk'>@@ -3347,27 +3345,25 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='ctx'> 	phy_info-&gt;mdix_mode =</div><div class='del'>-	    (e1000_auto_x_mode) ((phy_data &amp; M88E1000_PSSR_MDIX) &gt;&gt;</div><div class='del'>-				 M88E1000_PSSR_MDIX_SHIFT);</div><div class='add'>+	    (e1000_auto_x_mode)FIELD_GET(M88E1000_PSSR_MDIX, phy_data);</div><div class='ctx'> </div><div class='ctx'> 	if ((phy_data &amp; M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {</div><div class='ctx'> 		/* Cable Length Estimation and Local/Remote Receiver Information</div><div class='ctx'> 		 * are only valid at 1000 Mbps.</div><div class='ctx'> 		 */</div><div class='ctx'> 		phy_info-&gt;cable_length =</div><div class='del'>-		    (e1000_cable_length) ((phy_data &amp;</div><div class='del'>-					   M88E1000_PSSR_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-					  M88E1000_PSSR_CABLE_LENGTH_SHIFT);</div><div class='add'>+		    (e1000_cable_length)FIELD_GET(M88E1000_PSSR_CABLE_LENGTH,</div><div class='add'>+						  phy_data);</div><div class='ctx'> </div><div class='ctx'> 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &amp;phy_data);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> </div><div class='del'>-		phy_info-&gt;local_rx = ((phy_data &amp; SR_1000T_LOCAL_RX_STATUS) &gt;&gt;</div><div class='del'>-				      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?</div><div class='add'>+		phy_info-&gt;local_rx = FIELD_GET(SR_1000T_LOCAL_RX_STATUS,</div><div class='add'>+					       phy_data) ?</div><div class='ctx'> 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;</div><div class='del'>-		phy_info-&gt;remote_rx = ((phy_data &amp; SR_1000T_REMOTE_RX_STATUS) &gt;&gt;</div><div class='del'>-				       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?</div><div class='add'>+		phy_info-&gt;remote_rx = FIELD_GET(SR_1000T_REMOTE_RX_STATUS,</div><div class='add'>+						phy_data) ?</div><div class='ctx'> 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3515,7 +3511,7 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw)</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> 		eeprom_size =</div><div class='del'>-		    (eeprom_size &amp; EEPROM_SIZE_MASK) &gt;&gt; EEPROM_SIZE_SHIFT;</div><div class='add'>+		    FIELD_GET(EEPROM_SIZE_MASK, eeprom_size);</div><div class='ctx'> 		/* 256B eeprom size was not supported in earlier hardware, so we</div><div class='ctx'> 		 * bump eeprom_size up one to ensure that "1" (which maps to</div><div class='ctx'> 		 * 256B) is never the result used in the shifting logic below.</div><div class='hunk'>@@ -4891,8 +4887,7 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,</div><div class='ctx'> 					     &amp;phy_data);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='del'>-		cable_length = (phy_data &amp; M88E1000_PSSR_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-		    M88E1000_PSSR_CABLE_LENGTH_SHIFT;</div><div class='add'>+		cable_length = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);</div><div class='ctx'> </div><div class='ctx'> 		/* Convert the enum value to ranged values */</div><div class='ctx'> 		switch (cable_length) {</div><div class='hunk'>@@ -5001,8 +4996,7 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,</div><div class='ctx'> 					     &amp;phy_data);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='del'>-		*polarity = ((phy_data &amp; M88E1000_PSSR_REV_POLARITY) &gt;&gt;</div><div class='del'>-			     M88E1000_PSSR_REV_POLARITY_SHIFT) ?</div><div class='add'>+		*polarity = FIELD_GET(M88E1000_PSSR_REV_POLARITY, phy_data) ?</div><div class='ctx'> 		    e1000_rev_polarity_reversed : e1000_rev_polarity_normal;</div><div class='ctx'> </div><div class='ctx'> 	} else if (hw-&gt;phy_type == e1000_phy_igp) {</div><div class='hunk'>@@ -5072,8 +5066,8 @@ static s32 e1000_check_downshift(struct e1000_hw *hw)</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> </div><div class='del'>-		hw-&gt;speed_downgraded = (phy_data &amp; M88E1000_PSSR_DOWNSHIFT) &gt;&gt;</div><div class='del'>-		    M88E1000_PSSR_DOWNSHIFT_SHIFT;</div><div class='add'>+		hw-&gt;speed_downgraded = FIELD_GET(M88E1000_PSSR_DOWNSHIFT,</div><div class='add'>+						 phy_data);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return E1000_SUCCESS;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c<br/>index be9c695dde12..4eb1ceaf865a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/80003es2lan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/80003es2lan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/80003es2lan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/80003es2lan.c</a></div><div class='hunk'>@@ -92,8 +92,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	nvm-&gt;type = e1000_nvm_eeprom_spi;</div><div class='ctx'> </div><div class='del'>-	size = (u16)((eecd &amp; E1000_EECD_SIZE_EX_MASK) &gt;&gt;</div><div class='del'>-		     E1000_EECD_SIZE_EX_SHIFT);</div><div class='add'>+	size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);</div><div class='ctx'> </div><div class='ctx'> 	/* Added to a constant, "size" becomes the left-shift value</div><div class='ctx'> 	 * for setting word_size.</div><div class='hunk'>@@ -1035,17 +1034,18 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)</div><div class='ctx'> 	 * iteration and increase the max iterations when</div><div class='ctx'> 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.</div><div class='ctx'> 	 */</div><div class='del'>-	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),</div><div class='del'>-						   0xFFFF);</div><div class='add'>+	/* these next three accesses were always meant to use page 0x34 using</div><div class='add'>+	 * GG82563_REG(0x34, N) but never did, so we've just corrected the call</div><div class='add'>+	 * to not drop bits</div><div class='add'>+	 */</div><div class='add'>+	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 4, 0xFFFF);</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='del'>-	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),</div><div class='del'>-						  &amp;reg_data);</div><div class='add'>+	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 9, &amp;reg_data);</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> 	reg_data |= 0x3F;</div><div class='del'>-	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),</div><div class='del'>-						   reg_data);</div><div class='add'>+	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 9, reg_data);</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> 	ret_val =</div><div class='hunk'>@@ -1209,8 +1209,8 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='del'>-	kmrnctrlsta = ((offset &lt;&lt; E1000_KMRNCTRLSTA_OFFSET_SHIFT) &amp;</div><div class='del'>-		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;</div><div class='add'>+	kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |</div><div class='add'>+		      E1000_KMRNCTRLSTA_REN;</div><div class='ctx'> 	ew32(KMRNCTRLSTA, kmrnctrlsta);</div><div class='ctx'> 	e1e_flush();</div><div class='ctx'> </div><div class='hunk'>@@ -1244,8 +1244,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='del'>-	kmrnctrlsta = ((offset &lt;&lt; E1000_KMRNCTRLSTA_OFFSET_SHIFT) &amp;</div><div class='del'>-		       E1000_KMRNCTRLSTA_OFFSET) | data;</div><div class='add'>+	kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;</div><div class='ctx'> 	ew32(KMRNCTRLSTA, kmrnctrlsta);</div><div class='ctx'> 	e1e_flush();</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c<br/>index 0b1e890dd583..969f855a79ee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/82571.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/82571.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/82571.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/82571.c</a></div><div class='hunk'>@@ -157,8 +157,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	default:</div><div class='ctx'> 		nvm-&gt;type = e1000_nvm_eeprom_spi;</div><div class='del'>-		size = (u16)((eecd &amp; E1000_EECD_SIZE_EX_MASK) &gt;&gt;</div><div class='del'>-			     E1000_EECD_SIZE_EX_SHIFT);</div><div class='add'>+		size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);</div><div class='ctx'> 		/* Added to a constant, "size" becomes the left-shift value</div><div class='ctx'> 		 * for setting word_size.</div><div class='ctx'> 		 */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h<br/>index 63c3c79380a1..23a58cada43a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/defines.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/defines.h</a></div><div class='hunk'>@@ -678,11 +678,8 @@</div><div class='ctx'> </div><div class='ctx'> /* PCI/PCI-X/PCI-EX Config space */</div><div class='ctx'> #define PCI_HEADER_TYPE_REGISTER     0x0E</div><div class='del'>-#define PCIE_LINK_STATUS             0x12</div><div class='ctx'> </div><div class='ctx'> #define PCI_HEADER_TYPE_MULTIFUNC    0x80</div><div class='del'>-#define PCIE_LINK_WIDTH_MASK         0x3F0</div><div class='del'>-#define PCIE_LINK_WIDTH_SHIFT        4</div><div class='ctx'> </div><div class='ctx'> #define PHY_REVISION_MASK      0xFFFFFFF0</div><div class='ctx'> #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c<br/>index 9835e6a90d56..fc0f98ea6133 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/ethtool.c</a></div><div class='hunk'>@@ -654,8 +654,8 @@ static void e1000_get_drvinfo(struct net_device *netdev,</div><div class='ctx'> 	 */</div><div class='ctx'> 	snprintf(drvinfo-&gt;fw_version, sizeof(drvinfo-&gt;fw_version),</div><div class='ctx'> 		 "%d.%d-%d",</div><div class='del'>-		 (adapter-&gt;eeprom_vers &amp; 0xF000) &gt;&gt; 12,</div><div class='del'>-		 (adapter-&gt;eeprom_vers &amp; 0x0FF0) &gt;&gt; 4,</div><div class='add'>+		 FIELD_GET(0xF000, adapter-&gt;eeprom_vers),</div><div class='add'>+		 FIELD_GET(0x0FF0, adapter-&gt;eeprom_vers),</div><div class='ctx'> 		 (adapter-&gt;eeprom_vers &amp; 0x000F));</div><div class='ctx'> </div><div class='ctx'> 	strscpy(drvinfo-&gt;bus_info, pci_name(adapter-&gt;pdev),</div><div class='hunk'>@@ -925,8 +925,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (mac-&gt;type &gt;= e1000_pch_lpt)</div><div class='del'>-		wlock_mac = (er32(FWSM) &amp; E1000_FWSM_WLOCK_MAC_MASK) &gt;&gt;</div><div class='del'>-		    E1000_FWSM_WLOCK_MAC_SHIFT;</div><div class='add'>+		wlock_mac = FIELD_GET(E1000_FWSM_WLOCK_MAC_MASK, er32(FWSM));</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; mac-&gt;rar_entry_count; i++) {</div><div class='ctx'> 		if (mac-&gt;type &gt;= e1000_pch_lpt) {</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c<br/>index 39e9fc601bf5..a2788fd5f8bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/ich8lan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/ich8lan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/ich8lan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/ich8lan.c</a></div><div class='hunk'>@@ -1072,13 +1072,11 @@ static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)</div><div class='ctx'> </div><div class='ctx'> 		lat_enc_d = (lat_enc &amp; E1000_LTRV_VALUE_MASK) *</div><div class='ctx'> 			     (1U &lt;&lt; (E1000_LTRV_SCALE_FACTOR *</div><div class='del'>-			     ((lat_enc &amp; E1000_LTRV_SCALE_MASK)</div><div class='del'>-			     &gt;&gt; E1000_LTRV_SCALE_SHIFT)));</div><div class='add'>+			     FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc)));</div><div class='ctx'> </div><div class='ctx'> 		max_ltr_enc_d = (max_ltr_enc &amp; E1000_LTRV_VALUE_MASK) *</div><div class='del'>-				 (1U &lt;&lt; (E1000_LTRV_SCALE_FACTOR *</div><div class='del'>-				 ((max_ltr_enc &amp; E1000_LTRV_SCALE_MASK)</div><div class='del'>-				 &gt;&gt; E1000_LTRV_SCALE_SHIFT)));</div><div class='add'>+			(1U &lt;&lt; (E1000_LTRV_SCALE_FACTOR *</div><div class='add'>+				FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc)));</div><div class='ctx'> </div><div class='ctx'> 		if (lat_enc_d &gt; max_ltr_enc_d)</div><div class='ctx'> 			lat_enc = max_ltr_enc;</div><div class='hunk'>@@ -2075,8 +2073,7 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u16 phy_data;</div><div class='ctx'> 	u32 strap = er32(STRAP);</div><div class='del'>-	u32 freq = (strap &amp; E1000_STRAP_SMT_FREQ_MASK) &gt;&gt;</div><div class='del'>-	    E1000_STRAP_SMT_FREQ_SHIFT;</div><div class='add'>+	u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap);</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	strap &amp;= E1000_STRAP_SMBUS_ADDRESS_MASK;</div><div class='hunk'>@@ -2562,8 +2559,7 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)</div><div class='ctx'> 		hw-&gt;phy.ops.write_reg_page(hw, BM_RAR_H(i),</div><div class='ctx'> 					   (u16)(mac_reg &amp; 0xFFFF));</div><div class='ctx'> 		hw-&gt;phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),</div><div class='del'>-					   (u16)((mac_reg &amp; E1000_RAH_AV)</div><div class='del'>-						 &gt;&gt; 16));</div><div class='add'>+					   FIELD_GET(E1000_RAH_AV, mac_reg));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	e1000_disable_phy_wakeup_reg_access_bm(hw, &amp;phy_reg);</div><div class='hunk'>@@ -3205,7 +3201,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)</div><div class='ctx'> 							 &amp;nvm_dword);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='del'>-		sig_byte = (u8)((nvm_dword &amp; 0xFF00) &gt;&gt; 8);</div><div class='add'>+		sig_byte = FIELD_GET(0xFF00, nvm_dword);</div><div class='ctx'> 		if ((sig_byte &amp; E1000_ICH_NVM_VALID_SIG_MASK) ==</div><div class='ctx'> 		    E1000_ICH_NVM_SIG_VALUE) {</div><div class='ctx'> 			*bank = 0;</div><div class='hunk'>@@ -3218,7 +3214,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)</div><div class='ctx'> 							 &amp;nvm_dword);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='del'>-		sig_byte = (u8)((nvm_dword &amp; 0xFF00) &gt;&gt; 8);</div><div class='add'>+		sig_byte = FIELD_GET(0xFF00, nvm_dword);</div><div class='ctx'> 		if ((sig_byte &amp; E1000_ICH_NVM_VALID_SIG_MASK) ==</div><div class='ctx'> 		    E1000_ICH_NVM_SIG_VALUE) {</div><div class='ctx'> 			*bank = 1;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/mac.c b/drivers/net/ethernet/intel/e1000e/mac.c<br/>index 5df7ad93f3d7..d7df2a0ed629 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/mac.c</a></div><div class='hunk'>@@ -1,6 +1,8 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 1999 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+</div><div class='ctx'> #include "e1000.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -13,21 +15,17 @@</div><div class='ctx'>  **/</div><div class='ctx'> s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)</div><div class='ctx'> {</div><div class='add'>+	struct pci_dev *pdev = hw-&gt;adapter-&gt;pdev;</div><div class='ctx'> 	struct e1000_mac_info *mac = &amp;hw-&gt;mac;</div><div class='ctx'> 	struct e1000_bus_info *bus = &amp;hw-&gt;bus;</div><div class='del'>-	struct e1000_adapter *adapter = hw-&gt;adapter;</div><div class='del'>-	u16 pcie_link_status, cap_offset;</div><div class='add'>+	u16 pcie_link_status;</div><div class='ctx'> </div><div class='del'>-	cap_offset = adapter-&gt;pdev-&gt;pcie_cap;</div><div class='del'>-	if (!cap_offset) {</div><div class='add'>+	if (!pci_pcie_cap(pdev)) {</div><div class='ctx'> 		bus-&gt;width = e1000_bus_width_unknown;</div><div class='ctx'> 	} else {</div><div class='del'>-		pci_read_config_word(adapter-&gt;pdev,</div><div class='del'>-				     cap_offset + PCIE_LINK_STATUS,</div><div class='del'>-				     &amp;pcie_link_status);</div><div class='del'>-		bus-&gt;width = (enum e1000_bus_width)((pcie_link_status &amp;</div><div class='del'>-						     PCIE_LINK_WIDTH_MASK) &gt;&gt;</div><div class='del'>-						    PCIE_LINK_WIDTH_SHIFT);</div><div class='add'>+		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &amp;pcie_link_status);</div><div class='add'>+		bus-&gt;width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,</div><div class='add'>+							     pcie_link_status);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mac-&gt;ops.set_lan_id(hw);</div><div class='hunk'>@@ -52,7 +50,7 @@ void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)</div><div class='ctx'> 	 * for the device regardless of function swap state.</div><div class='ctx'> 	 */</div><div class='ctx'> 	reg = er32(STATUS);</div><div class='del'>-	bus-&gt;func = (reg &amp; E1000_STATUS_FUNC_MASK) &gt;&gt; E1000_STATUS_FUNC_SHIFT;</div><div class='add'>+	bus-&gt;func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c<br/>index f536c856727c..af5d9d97a0d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/netdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/netdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/netdev.c</a></div><div class='hunk'>@@ -1788,8 +1788,7 @@ static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)</div><div class='ctx'> 		adapter-&gt;corr_errors +=</div><div class='ctx'> 		    pbeccsts &amp; E1000_PBECCSTS_CORR_ERR_CNT_MASK;</div><div class='ctx'> 		adapter-&gt;uncorr_errors +=</div><div class='del'>-		    (pbeccsts &amp; E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) &gt;&gt;</div><div class='del'>-		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;</div><div class='add'>+		    FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);</div><div class='ctx'> </div><div class='ctx'> 		/* Do the reset outside of interrupt context */</div><div class='ctx'> 		schedule_work(&amp;adapter-&gt;reset_task);</div><div class='hunk'>@@ -1868,8 +1867,7 @@ static irqreturn_t e1000_intr(int __always_unused irq, void *data)</div><div class='ctx'> 		adapter-&gt;corr_errors +=</div><div class='ctx'> 		    pbeccsts &amp; E1000_PBECCSTS_CORR_ERR_CNT_MASK;</div><div class='ctx'> 		adapter-&gt;uncorr_errors +=</div><div class='del'>-		    (pbeccsts &amp; E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) &gt;&gt;</div><div class='del'>-		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;</div><div class='add'>+		    FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);</div><div class='ctx'> </div><div class='ctx'> 		/* Do the reset outside of interrupt context */</div><div class='ctx'> 		schedule_work(&amp;adapter-&gt;reset_task);</div><div class='hunk'>@@ -5031,8 +5029,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)</div><div class='ctx'> 		adapter-&gt;corr_errors +=</div><div class='ctx'> 		    pbeccsts &amp; E1000_PBECCSTS_CORR_ERR_CNT_MASK;</div><div class='ctx'> 		adapter-&gt;uncorr_errors +=</div><div class='del'>-		    (pbeccsts &amp; E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) &gt;&gt;</div><div class='del'>-		    E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;</div><div class='add'>+		    FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6249,7 +6246,7 @@ static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)</div><div class='ctx'> 		phy_reg |= BM_RCTL_MPE;</div><div class='ctx'> 	phy_reg &amp;= ~(BM_RCTL_MO_MASK);</div><div class='ctx'> 	if (mac_reg &amp; E1000_RCTL_MO_3)</div><div class='del'>-		phy_reg |= (((mac_reg &amp; E1000_RCTL_MO_3) &gt;&gt; E1000_RCTL_MO_SHIFT)</div><div class='add'>+		phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)</div><div class='ctx'> 			    &lt;&lt; BM_RCTL_MO_SHIFT);</div><div class='ctx'> 	if (mac_reg &amp; E1000_RCTL_BAM)</div><div class='ctx'> 		phy_reg |= BM_RCTL_BAM;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c<br/>index 08c3d477dd6f..5e329156d1ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/e1000e/phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/e1000e/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/e1000e/phy.c</a></div><div class='hunk'>@@ -154,10 +154,9 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)</div><div class='ctx'> 		e_dbg("MDI Read PHY Reg Address %d Error\n", offset);</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='ctx'> 	}</div><div class='del'>-	if (((mdic &amp; E1000_MDIC_REG_MASK) &gt;&gt; E1000_MDIC_REG_SHIFT) != offset) {</div><div class='add'>+	if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {</div><div class='ctx'> 		e_dbg("MDI Read offset error - requested %d, returned %d\n",</div><div class='del'>-		      offset,</div><div class='del'>-		      (mdic &amp; E1000_MDIC_REG_MASK) &gt;&gt; E1000_MDIC_REG_SHIFT);</div><div class='add'>+		      offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='ctx'> 	}</div><div class='ctx'> 	*data = (u16)mdic;</div><div class='hunk'>@@ -167,7 +166,6 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (hw-&gt;mac.type == e1000_pch2lan)</div><div class='ctx'> 		udelay(100);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -218,10 +216,9 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)</div><div class='ctx'> 		e_dbg("MDI Write PHY Red Address %d Error\n", offset);</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='ctx'> 	}</div><div class='del'>-	if (((mdic &amp; E1000_MDIC_REG_MASK) &gt;&gt; E1000_MDIC_REG_SHIFT) != offset) {</div><div class='add'>+	if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {</div><div class='ctx'> 		e_dbg("MDI Write offset error - requested %d, returned %d\n",</div><div class='del'>-		      offset,</div><div class='del'>-		      (mdic &amp; E1000_MDIC_REG_MASK) &gt;&gt; E1000_MDIC_REG_SHIFT);</div><div class='add'>+		      offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -463,8 +460,8 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kmrnctrlsta = ((offset &lt;&lt; E1000_KMRNCTRLSTA_OFFSET_SHIFT) &amp;</div><div class='del'>-		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;</div><div class='add'>+	kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |</div><div class='add'>+		      E1000_KMRNCTRLSTA_REN;</div><div class='ctx'> 	ew32(KMRNCTRLSTA, kmrnctrlsta);</div><div class='ctx'> 	e1e_flush();</div><div class='ctx'> </div><div class='hunk'>@@ -536,8 +533,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	kmrnctrlsta = ((offset &lt;&lt; E1000_KMRNCTRLSTA_OFFSET_SHIFT) &amp;</div><div class='del'>-		       E1000_KMRNCTRLSTA_OFFSET) | data;</div><div class='add'>+	kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;</div><div class='ctx'> 	ew32(KMRNCTRLSTA, kmrnctrlsta);</div><div class='ctx'> 	e1e_flush();</div><div class='ctx'> </div><div class='hunk'>@@ -1793,8 +1789,7 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='del'>-	index = ((phy_data &amp; M88E1000_PSSR_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-		 M88E1000_PSSR_CABLE_LENGTH_SHIFT);</div><div class='add'>+	index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt;= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='hunk'>@@ -3234,8 +3229,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='del'>-	length = ((phy_data &amp; I82577_DSTATUS_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-		  I82577_DSTATUS_CABLE_LENGTH_SHIFT);</div><div class='add'>+	length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);</div><div class='ctx'> </div><div class='ctx'> 	if (length == E1000_CABLE_LENGTH_UNDEFINED)</div><div class='ctx'> 		return -E1000_ERR_PHY;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c b/drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c<br/>index 13a05604dcc0..1bc5b6c0b897 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_ethtool.c</a></div><div class='hunk'>@@ -1057,16 +1057,16 @@ static u32 fm10k_get_rssrk_size(struct net_device __always_unused *netdev)</div><div class='ctx'> 	return FM10K_RSSRK_SIZE * FM10K_RSSRK_ENTRIES_PER_REG;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fm10k_get_rssh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int fm10k_get_rssh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct fm10k_intfc *interface = netdev_priv(netdev);</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='ctx'> 	int i, err;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	err = fm10k_get_reta(netdev, indir);</div><div class='add'>+	err = fm10k_get_reta(netdev, rxfh-&gt;indir);</div><div class='ctx'> 	if (err || !key)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1076,23 +1076,25 @@ static int fm10k_get_rssh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fm10k_set_rssh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int fm10k_set_rssh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct fm10k_intfc *interface = netdev_priv(netdev);</div><div class='ctx'> 	struct fm10k_hw *hw = &amp;interface-&gt;hw;</div><div class='ctx'> 	int i, err;</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	err = fm10k_set_reta(netdev, indir);</div><div class='del'>-	if (err || !key)</div><div class='add'>+	err = fm10k_set_reta(netdev, rxfh-&gt;indir);</div><div class='add'>+	if (err || !rxfh-&gt;key)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; FM10K_RSSRK_SIZE; i++, key += 4) {</div><div class='del'>-		u32 rssrk = le32_to_cpu(*(__le32 *)key);</div><div class='add'>+	for (i = 0; i &lt; FM10K_RSSRK_SIZE; i++, rxfh-&gt;key += 4) {</div><div class='add'>+		u32 rssrk = le32_to_cpu(*(__le32 *)rxfh-&gt;key);</div><div class='ctx'> </div><div class='ctx'> 		if (interface-&gt;rssrk[i] == rssrk)</div><div class='ctx'> 			continue;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_pf.c b/drivers/net/ethernet/intel/fm10k/fm10k_pf.c<br/>index af1b0cde3670..98861cc6df7c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_pf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/fm10k/fm10k_pf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_pf.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2019 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "fm10k_pf.h"</div><div class='ctx'> #include "fm10k_vf.h"</div><div class='ctx'> </div><div class='hunk'>@@ -865,8 +866,7 @@ static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,</div><div class='ctx'> 	 * register is RO from the VF, so the PF must do this even in the</div><div class='ctx'> 	 * case of notifying the VF of a new VID via the mailbox.</div><div class='ctx'> 	 */</div><div class='del'>-	txqctl = ((u32)vf_vid &lt;&lt; FM10K_TXQCTL_VID_SHIFT) &amp;</div><div class='del'>-		 FM10K_TXQCTL_VID_MASK;</div><div class='add'>+	txqctl = FIELD_PREP(FM10K_TXQCTL_VID_MASK, vf_vid);</div><div class='ctx'> 	txqctl |= (vf_idx &lt;&lt; FM10K_TXQCTL_TC_SHIFT) |</div><div class='ctx'> 		  FM10K_TXQCTL_VF | vf_idx;</div><div class='ctx'> </div><div class='hunk'>@@ -1575,8 +1575,7 @@ static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,</div><div class='ctx'> 	if (func &amp; FM10K_FAULT_FUNC_PF)</div><div class='ctx'> 		fault-&gt;func = 0;</div><div class='ctx'> 	else</div><div class='del'>-		fault-&gt;func = 1 + ((func &amp; FM10K_FAULT_FUNC_VF_MASK) &gt;&gt;</div><div class='del'>-				   FM10K_FAULT_FUNC_VF_SHIFT);</div><div class='add'>+		fault-&gt;func = 1 + FIELD_GET(FM10K_FAULT_FUNC_VF_MASK, func);</div><div class='ctx'> </div><div class='ctx'> 	/* record fault type */</div><div class='ctx'> 	fault-&gt;type = func &amp; FM10K_FAULT_FUNC_TYPE_MASK;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_vf.c b/drivers/net/ethernet/intel/fm10k/fm10k_vf.c<br/>index dc8ccd378ec9..7fb1961f2921 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_vf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/fm10k/fm10k_vf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/fm10k/fm10k_vf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/fm10k/fm10k_vf.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2019 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "fm10k_vf.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -126,15 +127,14 @@ static s32 fm10k_init_hw_vf(struct fm10k_hw *hw)</div><div class='ctx'> 	hw-&gt;mac.max_queues = i;</div><div class='ctx'> </div><div class='ctx'> 	/* fetch default VLAN and ITR scale */</div><div class='del'>-	hw-&gt;mac.default_vid = (fm10k_read_reg(hw, FM10K_TXQCTL(0)) &amp;</div><div class='del'>-			       FM10K_TXQCTL_VID_MASK) &gt;&gt; FM10K_TXQCTL_VID_SHIFT;</div><div class='add'>+	hw-&gt;mac.default_vid = FIELD_GET(FM10K_TXQCTL_VID_MASK,</div><div class='add'>+					fm10k_read_reg(hw, FM10K_TXQCTL(0)));</div><div class='ctx'> 	/* Read the ITR scale from TDLEN. See the definition of</div><div class='ctx'> 	 * FM10K_TDLEN_ITR_SCALE_SHIFT for more information about how TDLEN is</div><div class='ctx'> 	 * used here.</div><div class='ctx'> 	 */</div><div class='del'>-	hw-&gt;mac.itr_scale = (fm10k_read_reg(hw, FM10K_TDLEN(0)) &amp;</div><div class='del'>-			     FM10K_TDLEN_ITR_SCALE_MASK) &gt;&gt;</div><div class='del'>-			    FM10K_TDLEN_ITR_SCALE_SHIFT;</div><div class='add'>+	hw-&gt;mac.itr_scale = FIELD_GET(FM10K_TDLEN_ITR_SCALE_MASK,</div><div class='add'>+				      fm10k_read_reg(hw, FM10K_TDLEN(0)));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h<br/>index 1bf424ac3145..9b701615c7c6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e.h</a></div><div class='hunk'>@@ -24,6 +24,7 @@</div><div class='ctx'> #define I40E_MAX_VEB			16</div><div class='ctx'> </div><div class='ctx'> #define I40E_MAX_NUM_DESCRIPTORS	4096</div><div class='add'>+#define I40E_MAX_NUM_DESCRIPTORS_XL710	8160</div><div class='ctx'> #define I40E_MAX_CSR_SPACE		(4 * 1024 * 1024 - 64 * 1024)</div><div class='ctx'> #define I40E_DEFAULT_NUM_DESCRIPTORS	512</div><div class='ctx'> #define I40E_REQ_DESCRIPTOR_MULTIPLE	32</div><div class='hunk'>@@ -33,11 +34,11 @@</div><div class='ctx'> #define I40E_MIN_VSI_ALLOC		83 /* LAN, ATR, FCOE, 64 VF */</div><div class='ctx'> /* max 16 qps */</div><div class='ctx'> #define i40e_default_queues_per_vmdq(pf) \</div><div class='del'>-		(((pf)-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)</div><div class='add'>+	(test_bit(I40E_HW_CAP_RSS_AQ, (pf)-&gt;hw.caps) ? 4 : 1)</div><div class='ctx'> #define I40E_DEFAULT_QUEUES_PER_VF	4</div><div class='ctx'> #define I40E_MAX_VF_QUEUES		16</div><div class='ctx'> #define i40e_pf_get_max_q_per_tc(pf) \</div><div class='del'>-		(((pf)-&gt;hw_features &amp; I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)</div><div class='add'>+	(test_bit(I40E_HW_CAP_128_QP_RSS, (pf)-&gt;hw.caps) ? 128 : 64)</div><div class='ctx'> #define I40E_FDIR_RING_COUNT		32</div><div class='ctx'> #define I40E_MAX_AQ_BUF_SIZE		4096</div><div class='ctx'> #define I40E_AQ_LEN			256</div><div class='hunk'>@@ -78,7 +79,7 @@</div><div class='ctx'> #define I40E_MAX_BW_INACTIVE_ACCUM	4 /* accumulate 4 credits max */</div><div class='ctx'> </div><div class='ctx'> /* driver state flags */</div><div class='del'>-enum i40e_state_t {</div><div class='add'>+enum i40e_state {</div><div class='ctx'> 	__I40E_TESTING,</div><div class='ctx'> 	__I40E_CONFIG_BUSY,</div><div class='ctx'> 	__I40E_CONFIG_DONE,</div><div class='hunk'>@@ -126,7 +127,7 @@ enum i40e_state_t {</div><div class='ctx'> 	BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)</div><div class='ctx'> </div><div class='ctx'> /* VSI state flags */</div><div class='del'>-enum i40e_vsi_state_t {</div><div class='add'>+enum i40e_vsi_state {</div><div class='ctx'> 	__I40E_VSI_DOWN,</div><div class='ctx'> 	__I40E_VSI_NEEDS_RESTART,</div><div class='ctx'> 	__I40E_VSI_SYNCING_FILTERS,</div><div class='hunk'>@@ -138,6 +139,60 @@ enum i40e_vsi_state_t {</div><div class='ctx'> 	__I40E_VSI_STATE_SIZE__,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum i40e_pf_flags {</div><div class='add'>+	I40E_FLAG_MSI_ENA,</div><div class='add'>+	I40E_FLAG_MSIX_ENA,</div><div class='add'>+	I40E_FLAG_RSS_ENA,</div><div class='add'>+	I40E_FLAG_VMDQ_ENA,</div><div class='add'>+	I40E_FLAG_SRIOV_ENA,</div><div class='add'>+	I40E_FLAG_DCB_CAPABLE,</div><div class='add'>+	I40E_FLAG_DCB_ENA,</div><div class='add'>+	I40E_FLAG_FD_SB_ENA,</div><div class='add'>+	I40E_FLAG_FD_ATR_ENA,</div><div class='add'>+	I40E_FLAG_MFP_ENA,</div><div class='add'>+	I40E_FLAG_HW_ATR_EVICT_ENA,</div><div class='add'>+	I40E_FLAG_VEB_MODE_ENA,</div><div class='add'>+	I40E_FLAG_VEB_STATS_ENA,</div><div class='add'>+	I40E_FLAG_LINK_POLLING_ENA,</div><div class='add'>+	I40E_FLAG_TRUE_PROMISC_ENA,</div><div class='add'>+	I40E_FLAG_LEGACY_RX_ENA,</div><div class='add'>+	I40E_FLAG_PTP_ENA,</div><div class='add'>+	I40E_FLAG_IWARP_ENA,</div><div class='add'>+	I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA,</div><div class='add'>+	I40E_FLAG_SOURCE_PRUNING_DIS,</div><div class='add'>+	I40E_FLAG_TC_MQPRIO_ENA,</div><div class='add'>+	I40E_FLAG_FD_SB_INACTIVE,</div><div class='add'>+	I40E_FLAG_FD_SB_TO_CLOUD_FILTER,</div><div class='add'>+	I40E_FLAG_FW_LLDP_DIS,</div><div class='add'>+	I40E_FLAG_RS_FEC,</div><div class='add'>+	I40E_FLAG_BASE_R_FEC,</div><div class='add'>+	/* TOTAL_PORT_SHUTDOWN_ENA</div><div class='add'>+	 * Allows to physically disable the link on the NIC's port.</div><div class='add'>+	 * If enabled, (after link down request from the OS)</div><div class='add'>+	 * no link, traffic or led activity is possible on that port.</div><div class='add'>+	 *</div><div class='add'>+	 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the</div><div class='add'>+	 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced</div><div class='add'>+	 * to true and cannot be disabled by system admin at that time.</div><div class='add'>+	 * The functionalities are exclusive in terms of configuration, but</div><div class='add'>+	 * they also have similar behavior (allowing to disable physical</div><div class='add'>+	 * link of the port), with following differences:</div><div class='add'>+	 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and</div><div class='add'>+	 *   is supported by whole family of 7xx Intel Ethernet Controllers</div><div class='add'>+	 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads</div><div class='add'>+	 *   (in BIOS) only if motherboard's BIOS and NIC's FW has support of it</div><div class='add'>+	 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought</div><div class='add'>+	 *   down by sending phy_type=0 to NIC's FW</div><div class='add'>+	 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered,</div><div class='add'>+	 *   instead the link is being brought down by clearing</div><div class='add'>+	 *   bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of</div><div class='add'>+	 *   i40e_aq_set_phy_config structure</div><div class='add'>+	 */</div><div class='add'>+	I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA,</div><div class='add'>+	I40E_FLAG_VF_VLAN_PRUNING_ENA,</div><div class='add'>+	I40E_PF_FLAGS_NBITS,		/* must be last */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum i40e_interrupt_policy {</div><div class='ctx'> 	I40E_INTERRUPT_BEST_CASE,</div><div class='ctx'> 	I40E_INTERRUPT_MEDIUM,</div><div class='hunk'>@@ -413,9 +468,7 @@ struct i40e_pf {</div><div class='ctx'> 	struct i40e_hw hw;</div><div class='ctx'> 	DECLARE_BITMAP(state, __I40E_STATE_SIZE__);</div><div class='ctx'> 	struct msix_entry *msix_entries;</div><div class='del'>-	bool fc_autoneg_status;</div><div class='ctx'> </div><div class='del'>-	u16 eeprom_version;</div><div class='ctx'> 	u16 num_vmdq_vsis;         /* num vmdq vsis this PF has set up */</div><div class='ctx'> 	u16 num_vmdq_qps;          /* num queue pairs per vmdq pool */</div><div class='ctx'> 	u16 num_vmdq_msix;         /* num queue vectors per vmdq pool */</div><div class='hunk'>@@ -431,7 +484,6 @@ struct i40e_pf {</div><div class='ctx'> 	u16 rss_size_max;          /* HW defined max RSS queues */</div><div class='ctx'> 	u16 fdir_pf_filter_count;  /* num of guaranteed filters for this PF */</div><div class='ctx'> 	u16 num_alloc_vsi;         /* num VSIs this driver supports */</div><div class='del'>-	u8 atr_sample_rate;</div><div class='ctx'> 	bool wol_en;</div><div class='ctx'> </div><div class='ctx'> 	struct hlist_head fdir_filter_list;</div><div class='hunk'>@@ -469,89 +521,16 @@ struct i40e_pf {</div><div class='ctx'> 	struct hlist_head cloud_filter_list;</div><div class='ctx'> 	u16 num_cloud_filters;</div><div class='ctx'> </div><div class='del'>-	enum i40e_interrupt_policy int_policy;</div><div class='ctx'> 	u16 rx_itr_default;</div><div class='ctx'> 	u16 tx_itr_default;</div><div class='ctx'> 	u32 msg_enable;</div><div class='ctx'> 	char int_name[I40E_INT_NAME_STR_LEN];</div><div class='del'>-	u16 adminq_work_limit; /* num of admin receive queue desc to process */</div><div class='ctx'> 	unsigned long service_timer_period;</div><div class='ctx'> 	unsigned long service_timer_previous;</div><div class='ctx'> 	struct timer_list service_timer;</div><div class='ctx'> 	struct work_struct service_task;</div><div class='ctx'> </div><div class='del'>-	u32 hw_features;</div><div class='del'>-#define I40E_HW_RSS_AQ_CAPABLE			BIT(0)</div><div class='del'>-#define I40E_HW_128_QP_RSS_CAPABLE		BIT(1)</div><div class='del'>-#define I40E_HW_ATR_EVICT_CAPABLE		BIT(2)</div><div class='del'>-#define I40E_HW_WB_ON_ITR_CAPABLE		BIT(3)</div><div class='del'>-#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE	BIT(4)</div><div class='del'>-#define I40E_HW_NO_PCI_LINK_CHECK		BIT(5)</div><div class='del'>-#define I40E_HW_100M_SGMII_CAPABLE		BIT(6)</div><div class='del'>-#define I40E_HW_NO_DCB_SUPPORT			BIT(7)</div><div class='del'>-#define I40E_HW_USE_SET_LLDP_MIB		BIT(8)</div><div class='del'>-#define I40E_HW_GENEVE_OFFLOAD_CAPABLE		BIT(9)</div><div class='del'>-#define I40E_HW_PTP_L4_CAPABLE			BIT(10)</div><div class='del'>-#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE		BIT(11)</div><div class='del'>-#define I40E_HW_HAVE_CRT_RETIMER		BIT(13)</div><div class='del'>-#define I40E_HW_OUTER_UDP_CSUM_CAPABLE		BIT(14)</div><div class='del'>-#define I40E_HW_PHY_CONTROLS_LEDS		BIT(15)</div><div class='del'>-#define I40E_HW_STOP_FW_LLDP			BIT(16)</div><div class='del'>-#define I40E_HW_PORT_ID_VALID			BIT(17)</div><div class='del'>-#define I40E_HW_RESTART_AUTONEG			BIT(18)</div><div class='del'>-</div><div class='del'>-	u32 flags;</div><div class='del'>-#define I40E_FLAG_RX_CSUM_ENABLED		BIT(0)</div><div class='del'>-#define I40E_FLAG_MSI_ENABLED			BIT(1)</div><div class='del'>-#define I40E_FLAG_MSIX_ENABLED			BIT(2)</div><div class='del'>-#define I40E_FLAG_RSS_ENABLED			BIT(3)</div><div class='del'>-#define I40E_FLAG_VMDQ_ENABLED			BIT(4)</div><div class='del'>-#define I40E_FLAG_SRIOV_ENABLED			BIT(5)</div><div class='del'>-#define I40E_FLAG_DCB_CAPABLE			BIT(6)</div><div class='del'>-#define I40E_FLAG_DCB_ENABLED			BIT(7)</div><div class='del'>-#define I40E_FLAG_FD_SB_ENABLED			BIT(8)</div><div class='del'>-#define I40E_FLAG_FD_ATR_ENABLED		BIT(9)</div><div class='del'>-#define I40E_FLAG_MFP_ENABLED			BIT(10)</div><div class='del'>-#define I40E_FLAG_HW_ATR_EVICT_ENABLED		BIT(11)</div><div class='del'>-#define I40E_FLAG_VEB_MODE_ENABLED		BIT(12)</div><div class='del'>-#define I40E_FLAG_VEB_STATS_ENABLED		BIT(13)</div><div class='del'>-#define I40E_FLAG_LINK_POLLING_ENABLED		BIT(14)</div><div class='del'>-#define I40E_FLAG_TRUE_PROMISC_SUPPORT		BIT(15)</div><div class='del'>-#define I40E_FLAG_LEGACY_RX			BIT(16)</div><div class='del'>-#define I40E_FLAG_PTP				BIT(17)</div><div class='del'>-#define I40E_FLAG_IWARP_ENABLED			BIT(18)</div><div class='del'>-#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(19)</div><div class='del'>-#define I40E_FLAG_SOURCE_PRUNING_DISABLED       BIT(20)</div><div class='del'>-#define I40E_FLAG_TC_MQPRIO			BIT(21)</div><div class='del'>-#define I40E_FLAG_FD_SB_INACTIVE		BIT(22)</div><div class='del'>-#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER		BIT(23)</div><div class='del'>-#define I40E_FLAG_DISABLE_FW_LLDP		BIT(24)</div><div class='del'>-#define I40E_FLAG_RS_FEC			BIT(25)</div><div class='del'>-#define I40E_FLAG_BASE_R_FEC			BIT(26)</div><div class='del'>-/* TOTAL_PORT_SHUTDOWN</div><div class='del'>- * Allows to physically disable the link on the NIC's port.</div><div class='del'>- * If enabled, (after link down request from the OS)</div><div class='del'>- * no link, traffic or led activity is possible on that port.</div><div class='del'>- *</div><div class='del'>- * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the</div><div class='del'>- * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true</div><div class='del'>- * and cannot be disabled by system admin at that time.</div><div class='del'>- * The functionalities are exclusive in terms of configuration, but they also</div><div class='del'>- * have similar behavior (allowing to disable physical link of the port),</div><div class='del'>- * with following differences:</div><div class='del'>- * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is</div><div class='del'>- *   supported by whole family of 7xx Intel Ethernet Controllers</div><div class='del'>- * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)</div><div class='del'>- *   only if motherboard's BIOS and NIC's FW has support of it</div><div class='del'>- * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down</div><div class='del'>- *   by sending phy_type=0 to NIC's FW</div><div class='del'>- * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead</div><div class='del'>- *   the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)</div><div class='del'>- *   in abilities field of i40e_aq_set_phy_config structure</div><div class='del'>- */</div><div class='del'>-#define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED	BIT(27)</div><div class='del'>-#define I40E_FLAG_VF_VLAN_PRUNING		BIT(28)</div><div class='del'>-</div><div class='add'>+	DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS);</div><div class='ctx'> 	struct i40e_client_instance *cinst;</div><div class='ctx'> 	bool stat_offsets_loaded;</div><div class='ctx'> 	struct i40e_hw_port_stats stats;</div><div class='hunk'>@@ -559,7 +538,6 @@ struct i40e_pf {</div><div class='ctx'> 	u32 tx_timeout_count;</div><div class='ctx'> 	u32 tx_timeout_recovery_level;</div><div class='ctx'> 	unsigned long tx_timeout_last_recovery;</div><div class='del'>-	u32 tx_sluggish_count;</div><div class='ctx'> 	u32 hw_csum_rx_error;</div><div class='ctx'> 	u32 led_status;</div><div class='ctx'> 	u16 corer_count; /* Core reset count */</div><div class='hunk'>@@ -581,17 +559,13 @@ struct i40e_pf {</div><div class='ctx'> 	struct i40e_lump_tracking *irq_pile;</div><div class='ctx'> </div><div class='ctx'> 	/* switch config info */</div><div class='del'>-	u16 pf_seid;</div><div class='ctx'> 	u16 main_vsi_seid;</div><div class='ctx'> 	u16 mac_seid;</div><div class='del'>-	struct kobject *switch_kobj;</div><div class='ctx'> #ifdef CONFIG_DEBUG_FS</div><div class='ctx'> 	struct dentry *i40e_dbg_pf;</div><div class='ctx'> #endif /* CONFIG_DEBUG_FS */</div><div class='ctx'> 	bool cur_promisc;</div><div class='ctx'> </div><div class='del'>-	u16 instance; /* A unique number per i40e_pf instance in the system */</div><div class='del'>-</div><div class='ctx'> 	/* sr-iov config info */</div><div class='ctx'> 	struct i40e_vf *vf;</div><div class='ctx'> 	int num_alloc_vfs;	/* actual number of VFs allocated */</div><div class='hunk'>@@ -685,9 +659,7 @@ struct i40e_pf {</div><div class='ctx'> 	unsigned long ptp_tx_start;</div><div class='ctx'> 	struct hwtstamp_config tstamp_config;</div><div class='ctx'> 	struct timespec64 ptp_prev_hw_time;</div><div class='del'>-	struct work_struct ptp_pps_work;</div><div class='ctx'> 	struct work_struct ptp_extts0_work;</div><div class='del'>-	struct work_struct ptp_extts1_work;</div><div class='ctx'> 	ktime_t ptp_reset_start;</div><div class='ctx'> 	struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */</div><div class='ctx'> 	u32 ptp_adj_mult;</div><div class='hunk'>@@ -695,10 +667,7 @@ struct i40e_pf {</div><div class='ctx'> 	u32 tx_hwtstamp_skipped;</div><div class='ctx'> 	u32 rx_hwtstamp_cleared;</div><div class='ctx'> 	u32 latch_event_flags;</div><div class='del'>-	u64 ptp_pps_start;</div><div class='del'>-	u32 pps_delay;</div><div class='ctx'> 	spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */</div><div class='del'>-	struct ptp_pin_desc ptp_pin[3];</div><div class='ctx'> 	unsigned long latch_events[4];</div><div class='ctx'> 	bool ptp_tx;</div><div class='ctx'> 	bool ptp_rx;</div><div class='hunk'>@@ -711,7 +680,6 @@ struct i40e_pf {</div><div class='ctx'> 	u32 fd_inv;</div><div class='ctx'> 	u16 phy_led_val;</div><div class='ctx'> </div><div class='del'>-	u16 override_q_count;</div><div class='ctx'> 	u16 last_sw_conf_flags;</div><div class='ctx'> 	u16 last_sw_conf_valid_flags;</div><div class='ctx'> 	/* List to keep previous DDP profiles to be rolled back in the future */</div><div class='hunk'>@@ -1267,7 +1235,7 @@ struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);</div><div class='ctx'> void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);</div><div class='ctx'> static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	return !!(pf-&gt;flags &amp; I40E_FLAG_DISABLE_FW_LLDP);</div><div class='add'>+	return test_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_I40E_DCB</div><div class='hunk'>@@ -1301,7 +1269,7 @@ int i40e_set_partition_bw_setting(struct i40e_pf *pf);</div><div class='ctx'> int i40e_commit_partition_bw_setting(struct i40e_pf *pf);</div><div class='ctx'> void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);</div><div class='ctx'> </div><div class='del'>-void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);</div><div class='add'>+void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags);</div><div class='ctx'> </div><div class='ctx'> static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> {</div><div class='hunk'>@@ -1321,13 +1289,13 @@ int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,</div><div class='ctx'>  * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF</div><div class='ctx'>  * @pf: pointer to a pf.</div><div class='ctx'>  *</div><div class='del'>- * Check and return value of flag I40E_FLAG_TC_MQPRIO.</div><div class='add'>+ * Check and return state of flag I40E_FLAG_TC_MQPRIO.</div><div class='ctx'>  *</div><div class='del'>- * Return: I40E_FLAG_TC_MQPRIO set state.</div><div class='add'>+ * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not</div><div class='ctx'>  **/</div><div class='del'>-static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)</div><div class='add'>+static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	return pf-&gt;flags &amp; I40E_FLAG_TC_MQPRIO;</div><div class='add'>+	return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c<br/>index 9ce6e633cc2f..f73f5930fc58 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_adminq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq.c</a></div><div class='hunk'>@@ -9,40 +9,6 @@</div><div class='ctx'> static void i40e_resume_aq(struct i40e_hw *hw);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- *  i40e_adminq_init_regs - Initialize AdminQ registers</div><div class='del'>- *  @hw: pointer to the hardware structure</div><div class='del'>- *</div><div class='del'>- *  This assumes the alloc_asq and alloc_arq functions have already been called</div><div class='del'>- **/</div><div class='del'>-static void i40e_adminq_init_regs(struct i40e_hw *hw)</div><div class='del'>-{</div><div class='del'>-	/* set head and tail registers in our local struct */</div><div class='del'>-	if (i40e_is_vf(hw)) {</div><div class='del'>-		hw-&gt;aq.asq.tail = I40E_VF_ATQT1;</div><div class='del'>-		hw-&gt;aq.asq.head = I40E_VF_ATQH1;</div><div class='del'>-		hw-&gt;aq.asq.len  = I40E_VF_ATQLEN1;</div><div class='del'>-		hw-&gt;aq.asq.bal  = I40E_VF_ATQBAL1;</div><div class='del'>-		hw-&gt;aq.asq.bah  = I40E_VF_ATQBAH1;</div><div class='del'>-		hw-&gt;aq.arq.tail = I40E_VF_ARQT1;</div><div class='del'>-		hw-&gt;aq.arq.head = I40E_VF_ARQH1;</div><div class='del'>-		hw-&gt;aq.arq.len  = I40E_VF_ARQLEN1;</div><div class='del'>-		hw-&gt;aq.arq.bal  = I40E_VF_ARQBAL1;</div><div class='del'>-		hw-&gt;aq.arq.bah  = I40E_VF_ARQBAH1;</div><div class='del'>-	} else {</div><div class='del'>-		hw-&gt;aq.asq.tail = I40E_PF_ATQT;</div><div class='del'>-		hw-&gt;aq.asq.head = I40E_PF_ATQH;</div><div class='del'>-		hw-&gt;aq.asq.len  = I40E_PF_ATQLEN;</div><div class='del'>-		hw-&gt;aq.asq.bal  = I40E_PF_ATQBAL;</div><div class='del'>-		hw-&gt;aq.asq.bah  = I40E_PF_ATQBAH;</div><div class='del'>-		hw-&gt;aq.arq.tail = I40E_PF_ARQT;</div><div class='del'>-		hw-&gt;aq.arq.head = I40E_PF_ARQH;</div><div class='del'>-		hw-&gt;aq.arq.len  = I40E_PF_ARQLEN;</div><div class='del'>-		hw-&gt;aq.arq.bal  = I40E_PF_ARQBAL;</div><div class='del'>-		hw-&gt;aq.arq.bah  = I40E_PF_ARQBAH;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings</div><div class='ctx'>  *  @hw: pointer to the hardware structure</div><div class='ctx'>  **/</div><div class='hunk'>@@ -267,17 +233,17 @@ static int i40e_config_asq_regs(struct i40e_hw *hw)</div><div class='ctx'> 	u32 reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear Head and Tail */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.tail, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQH, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQT, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* set starting point */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.len, (hw-&gt;aq.num_asq_entries |</div><div class='add'>+	wr32(hw, I40E_PF_ATQLEN, (hw-&gt;aq.num_asq_entries |</div><div class='ctx'> 				  I40E_PF_ATQLEN_ATQENABLE_MASK));</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bal, lower_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bah, upper_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='add'>+	wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='add'>+	wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='ctx'> </div><div class='ctx'> 	/* Check one register to verify that config was applied */</div><div class='del'>-	reg = rd32(hw, hw-&gt;aq.asq.bal);</div><div class='add'>+	reg = rd32(hw, I40E_PF_ATQBAL);</div><div class='ctx'> 	if (reg != lower_32_bits(hw-&gt;aq.asq.desc_buf.pa))</div><div class='ctx'> 		ret_code = -EIO;</div><div class='ctx'> </div><div class='hunk'>@@ -296,20 +262,20 @@ static int i40e_config_arq_regs(struct i40e_hw *hw)</div><div class='ctx'> 	u32 reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear Head and Tail */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQH, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQT, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* set starting point */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.len, (hw-&gt;aq.num_arq_entries |</div><div class='add'>+	wr32(hw, I40E_PF_ARQLEN, (hw-&gt;aq.num_arq_entries |</div><div class='ctx'> 				  I40E_PF_ARQLEN_ARQENABLE_MASK));</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bal, lower_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bah, upper_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='add'>+	wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='add'>+	wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='ctx'> </div><div class='ctx'> 	/* Update tail in the HW to post pre-allocated buffers */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, hw-&gt;aq.num_arq_entries - 1);</div><div class='add'>+	wr32(hw, I40E_PF_ARQT, hw-&gt;aq.num_arq_entries - 1);</div><div class='ctx'> </div><div class='ctx'> 	/* Check one register to verify that config was applied */</div><div class='del'>-	reg = rd32(hw, hw-&gt;aq.arq.bal);</div><div class='add'>+	reg = rd32(hw, I40E_PF_ARQBAL);</div><div class='ctx'> 	if (reg != lower_32_bits(hw-&gt;aq.arq.desc_buf.pa))</div><div class='ctx'> 		ret_code = -EIO;</div><div class='ctx'> </div><div class='hunk'>@@ -452,11 +418,11 @@ static int i40e_shutdown_asq(struct i40e_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Stop firmware AdminQ processing */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.tail, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.len, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bal, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bah, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQH, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQT, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQLEN, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQBAL, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ATQBAH, 0);</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.asq.count = 0; /* to indicate uninitialized queue */</div><div class='ctx'> </div><div class='hunk'>@@ -486,11 +452,11 @@ static int i40e_shutdown_arq(struct i40e_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Stop firmware AdminQ processing */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.len, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bal, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bah, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQH, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQT, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQLEN, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQBAL, 0);</div><div class='add'>+	wr32(hw, I40E_PF_ARQBAH, 0);</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.arq.count = 0; /* to indicate uninitialized queue */</div><div class='ctx'> </div><div class='hunk'>@@ -503,44 +469,76 @@ shutdown_arq_out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- *  i40e_set_hw_flags - set HW flags</div><div class='add'>+ *  i40e_set_hw_caps - set HW flags</div><div class='ctx'>  *  @hw: pointer to the hardware structure</div><div class='ctx'>  **/</div><div class='del'>-static void i40e_set_hw_flags(struct i40e_hw *hw)</div><div class='add'>+static void i40e_set_hw_caps(struct i40e_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	struct i40e_adminq_info *aq = &amp;hw-&gt;aq;</div><div class='del'>-</div><div class='del'>-	hw-&gt;flags = 0;</div><div class='add'>+	bitmap_zero(hw-&gt;caps, I40E_HW_CAPS_NBITS);</div><div class='ctx'> </div><div class='ctx'> 	switch (hw-&gt;mac.type) {</div><div class='ctx'> 	case I40E_MAC_XL710:</div><div class='del'>-		if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-		    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-		     aq-&gt;api_min_ver &gt;= I40E_MINOR_VER_GET_LINK_INFO_XL710)) {</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1,</div><div class='add'>+					  I40E_MINOR_VER_GET_LINK_INFO_XL710)) {</div><div class='add'>+			set_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps);</div><div class='add'>+			set_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw-&gt;caps);</div><div class='ctx'> 			/* The ability to RX (not drop) 802.1ad frames */</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_802_1AD_CAPABLE;</div><div class='add'>+			set_bit(I40E_HW_CAP_802_1AD, hw-&gt;caps);</div><div class='add'>+		}</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1, 5)) {</div><div class='add'>+			/* Supported in FW API version higher than 1.4 */</div><div class='add'>+			set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, hw-&gt;caps);</div><div class='add'>+		}</div><div class='add'>+		if (i40e_is_fw_ver_lt(hw, 4, 33)) {</div><div class='add'>+			set_bit(I40E_HW_CAP_RESTART_AUTONEG, hw-&gt;caps);</div><div class='add'>+			/* No DCB support  for FW &lt; v4.33 */</div><div class='add'>+			set_bit(I40E_HW_CAP_NO_DCB_SUPPORT, hw-&gt;caps);</div><div class='add'>+		}</div><div class='add'>+		if (i40e_is_fw_ver_lt(hw, 4, 3)) {</div><div class='add'>+			/* Disable FW LLDP if FW &lt; v4.3 */</div><div class='add'>+			set_bit(I40E_HW_CAP_STOP_FW_LLDP, hw-&gt;caps);</div><div class='add'>+		}</div><div class='add'>+		if (i40e_is_fw_ver_ge(hw, 4, 40)) {</div><div class='add'>+			/* Use the FW Set LLDP MIB API if FW &gt;= v4.40 */</div><div class='add'>+			set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, hw-&gt;caps);</div><div class='add'>+		}</div><div class='add'>+		if (i40e_is_fw_ver_ge(hw, 6, 0)) {</div><div class='add'>+			/* Enable PTP L4 if FW &gt; v6.0 */</div><div class='add'>+			set_bit(I40E_HW_CAP_PTP_L4, hw-&gt;caps);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case I40E_MAC_X722:</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |</div><div class='del'>-			     I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;</div><div class='add'>+		set_bit(I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_RSS_AQ, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_128_QP_RSS, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_ATR_EVICT, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_WB_ON_ITR, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_PTP_L4, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, hw-&gt;caps);</div><div class='add'>+		set_bit(I40E_HW_CAP_OUTER_UDP_CSUM, hw-&gt;caps);</div><div class='add'>+</div><div class='add'>+		if (rd32(hw, I40E_GLQF_FDEVICTENA(1)) !=</div><div class='add'>+		    I40E_FDEVICT_PCTYPE_DEFAULT) {</div><div class='add'>+			hw_warn(hw, "FD EVICT PCTYPES are not right, disable FD HW EVICT\n");</div><div class='add'>+			clear_bit(I40E_HW_CAP_ATR_EVICT, hw-&gt;caps);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-		    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-		     aq-&gt;api_min_ver &gt;= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722))</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1,</div><div class='add'>+					  I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722))</div><div class='add'>+			set_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw-&gt;caps);</div><div class='ctx'> </div><div class='del'>-		if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-		    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-		     aq-&gt;api_min_ver &gt;= I40E_MINOR_VER_GET_LINK_INFO_X722))</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1,</div><div class='add'>+					  I40E_MINOR_VER_GET_LINK_INFO_X722))</div><div class='add'>+			set_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps);</div><div class='ctx'> </div><div class='del'>-		if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-		    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-		     aq-&gt;api_min_ver &gt;= I40E_MINOR_VER_FW_REQUEST_FEC_X722))</div><div class='del'>-			hw-&gt;flags |= I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE;</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1,</div><div class='add'>+					  I40E_MINOR_VER_FW_REQUEST_FEC_X722))</div><div class='add'>+			set_bit(I40E_HW_CAP_X722_FEC_REQUEST, hw-&gt;caps);</div><div class='ctx'> </div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -548,22 +546,18 @@ static void i40e_set_hw_flags(struct i40e_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Newer versions of firmware require lock when reading the NVM */</div><div class='del'>-	if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-	    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-	     aq-&gt;api_min_ver &gt;= 5))</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;</div><div class='del'>-</div><div class='del'>-	if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-	    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-	     aq-&gt;api_min_ver &gt;= 8)) {</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT;</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_DROP_MODE;</div><div class='del'>-	}</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 5))</div><div class='add'>+		set_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw-&gt;caps);</div><div class='add'>+</div><div class='add'>+	/* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 7))</div><div class='add'>+		set_bit(I40E_HW_CAP_802_1AD, hw-&gt;caps);</div><div class='add'>+</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 8))</div><div class='add'>+		set_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw-&gt;caps);</div><div class='ctx'> </div><div class='del'>-	if (aq-&gt;api_maj_ver &gt; 1 ||</div><div class='del'>-	    (aq-&gt;api_maj_ver == 1 &amp;&amp;</div><div class='del'>-	     aq-&gt;api_min_ver &gt;= 9))</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED;</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 9))</div><div class='add'>+		set_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw-&gt;caps);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -593,9 +587,6 @@ int i40e_init_adminq(struct i40e_hw *hw)</div><div class='ctx'> 		goto init_adminq_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Set up register offsets */</div><div class='del'>-	i40e_adminq_init_regs(hw);</div><div class='del'>-</div><div class='ctx'> 	/* setup ASQ command write back timeout */</div><div class='ctx'> 	hw-&gt;aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;</div><div class='ctx'> </div><div class='hunk'>@@ -633,7 +624,7 @@ int i40e_init_adminq(struct i40e_hw *hw)</div><div class='ctx'> 	/* Some features were introduced in different FW API version</div><div class='ctx'> 	 * for different MAC type.</div><div class='ctx'> 	 */</div><div class='del'>-	i40e_set_hw_flags(hw);</div><div class='add'>+	i40e_set_hw_caps(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* get the NVM version info */</div><div class='ctx'> 	i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,</div><div class='hunk'>@@ -648,25 +639,7 @@ int i40e_init_adminq(struct i40e_hw *hw)</div><div class='ctx'> 			   &amp;oem_lo);</div><div class='ctx'> 	hw-&gt;nvm.oem_ver = ((u32)oem_hi &lt;&lt; 16) | oem_lo;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;mac.type == I40E_MAC_XL710 &amp;&amp;</div><div class='del'>-	    hw-&gt;aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &amp;&amp;</div><div class='del'>-	    hw-&gt;aq.api_min_ver &gt;= I40E_MINOR_VER_GET_LINK_INFO_XL710) {</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;</div><div class='del'>-	}</div><div class='del'>-	if (hw-&gt;mac.type == I40E_MAC_X722 &amp;&amp;</div><div class='del'>-	    hw-&gt;aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &amp;&amp;</div><div class='del'>-	    hw-&gt;aq.api_min_ver &gt;= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) {</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */</div><div class='del'>-	if (hw-&gt;aq.api_maj_ver &gt; 1 ||</div><div class='del'>-	    (hw-&gt;aq.api_maj_ver == 1 &amp;&amp;</div><div class='del'>-	     hw-&gt;aq.api_min_ver &gt;= 7))</div><div class='del'>-		hw-&gt;flags |= I40E_HW_FLAG_802_1AD_CAPABLE;</div><div class='del'>-</div><div class='del'>-	if (hw-&gt;aq.api_maj_ver &gt; I40E_FW_API_VERSION_MAJOR) {</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR + 1, 0)) {</div><div class='ctx'> 		ret_code = -EIO;</div><div class='ctx'> 		goto init_adminq_free_arq;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -723,9 +696,9 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	desc = I40E_ADMINQ_DESC(*asq, ntc);</div><div class='ctx'> 	details = I40E_ADMINQ_DETAILS(*asq, ntc);</div><div class='del'>-	while (rd32(hw, hw-&gt;aq.asq.head) != ntc) {</div><div class='add'>+	while (rd32(hw, I40E_PF_ATQH) != ntc) {</div><div class='ctx'> 		i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,</div><div class='del'>-			   "ntc %d head %d.\n", ntc, rd32(hw, hw-&gt;aq.asq.head));</div><div class='add'>+			   "ntc %d head %d.\n", ntc, rd32(hw, I40E_PF_ATQH));</div><div class='ctx'> </div><div class='ctx'> 		if (details-&gt;callback) {</div><div class='ctx'> 			I40E_ADMINQ_CALLBACK cb_func =</div><div class='hunk'>@@ -759,7 +732,7 @@ static bool i40e_asq_done(struct i40e_hw *hw)</div><div class='ctx'> 	/* AQ designers suggest use of head for better</div><div class='ctx'> 	 * timing reliability than DD bit</div><div class='ctx'> 	 */</div><div class='del'>-	return rd32(hw, hw-&gt;aq.asq.head) == hw-&gt;aq.asq.next_to_use;</div><div class='add'>+	return rd32(hw, I40E_PF_ATQH) == hw-&gt;aq.asq.next_to_use;</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -800,7 +773,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.asq_last_status = I40E_AQ_RC_OK;</div><div class='ctx'> </div><div class='del'>-	val = rd32(hw, hw-&gt;aq.asq.head);</div><div class='add'>+	val = rd32(hw, I40E_PF_ATQH);</div><div class='ctx'> 	if (val &gt;= hw-&gt;aq.num_asq_entries) {</div><div class='ctx'> 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,</div><div class='ctx'> 			   "AQTX: head overrun at %d\n", val);</div><div class='hunk'>@@ -892,7 +865,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,</div><div class='ctx'> 	if (hw-&gt;aq.asq.next_to_use == hw-&gt;aq.asq.count)</div><div class='ctx'> 		hw-&gt;aq.asq.next_to_use = 0;</div><div class='ctx'> 	if (!details-&gt;postpone)</div><div class='del'>-		wr32(hw, hw-&gt;aq.asq.tail, hw-&gt;aq.asq.next_to_use);</div><div class='add'>+		wr32(hw, I40E_PF_ATQT, hw-&gt;aq.asq.next_to_use);</div><div class='ctx'> </div><div class='ctx'> 	/* if cmd_details are not defined or async flag is not set,</div><div class='ctx'> 	 * we need to wait for desc write back</div><div class='hunk'>@@ -952,7 +925,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,</div><div class='ctx'> 	/* update the error if time out occurred */</div><div class='ctx'> 	if ((!cmd_completed) &amp;&amp;</div><div class='ctx'> 	    (!details-&gt;async &amp;&amp; !details-&gt;postpone)) {</div><div class='del'>-		if (rd32(hw, hw-&gt;aq.asq.len) &amp; I40E_GL_ATQLEN_ATQCRIT_MASK) {</div><div class='add'>+		if (rd32(hw, I40E_PF_ATQLEN) &amp; I40E_GL_ATQLEN_ATQCRIT_MASK) {</div><div class='ctx'> 			i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,</div><div class='ctx'> 				   "AQTX: AQ Critical error.\n");</div><div class='ctx'> 			status = -EIO;</div><div class='hunk'>@@ -1106,7 +1079,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* set next_to_use to head */</div><div class='del'>-	ntu = rd32(hw, hw-&gt;aq.arq.head) &amp; I40E_PF_ARQH_ARQH_MASK;</div><div class='add'>+	ntu = rd32(hw, I40E_PF_ARQH) &amp; I40E_PF_ARQH_ARQH_MASK;</div><div class='ctx'> 	if (ntu == ntc) {</div><div class='ctx'> 		/* nothing to do - shouldn't need to update ring's values */</div><div class='ctx'> 		ret_code = -EALREADY;</div><div class='hunk'>@@ -1154,7 +1127,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw,</div><div class='ctx'> 	desc-&gt;params.external.addr_low = cpu_to_le32(lower_32_bits(bi-&gt;pa));</div><div class='ctx'> </div><div class='ctx'> 	/* set tail = the last cleaned desc index. */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, ntc);</div><div class='add'>+	wr32(hw, I40E_PF_ARQT, ntc);</div><div class='ctx'> 	/* ntc is updated to tail + 1 */</div><div class='ctx'> 	ntc++;</div><div class='ctx'> 	if (ntc == hw-&gt;aq.num_arq_entries)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.h b/drivers/net/ethernet/intel/i40e/i40e_adminq.h<br/>index 80125bea80a2..ee86d2c53079 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_adminq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq.h</a></div><div class='hunk'>@@ -29,13 +29,6 @@ struct i40e_adminq_ring {</div><div class='ctx'> 	/* used for interrupt processing */</div><div class='ctx'> 	u16 next_to_use;</div><div class='ctx'> 	u16 next_to_clean;</div><div class='del'>-</div><div class='del'>-	/* used for queue tracking */</div><div class='del'>-	u32 head;</div><div class='del'>-	u32 tail;</div><div class='del'>-	u32 len;</div><div class='del'>-	u32 bah;</div><div class='del'>-	u32 bal;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ASQ transaction details */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h<br/>index 18a1c3b6d72c..c8f35d4de271 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h</a></div><div class='hunk'>@@ -5,6 +5,7 @@</div><div class='ctx'> #define _I40E_ADMINQ_CMD_H_</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/bits.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='ctx'> </div><div class='ctx'> /* This header file defines the i40e Admin Queue commands and is shared between</div><div class='ctx'>  * i40e Firmware and Software.</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c<br/>index d7e24d661724..de6ca6295742 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_common.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /* Copyright(c) 2013 - 2021 Intel Corporation. */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/avf/virtchnl.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/etherdevice.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='hunk'>@@ -195,11 +196,11 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,</div><div class='ctx'>  **/</div><div class='ctx'> bool i40e_check_asq_alive(struct i40e_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	if (hw-&gt;aq.asq.len)</div><div class='del'>-		return !!(rd32(hw, hw-&gt;aq.asq.len) &amp;</div><div class='del'>-			  I40E_PF_ATQLEN_ATQENABLE_MASK);</div><div class='del'>-	else</div><div class='add'>+	/* Check if the queue is initialized */</div><div class='add'>+	if (!hw-&gt;aq.asq.count)</div><div class='ctx'> 		return false;</div><div class='add'>+</div><div class='add'>+	return !!(rd32(hw, I40E_PF_ATQLEN) &amp; I40E_PF_ATQLEN_ATQENABLE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -248,6 +249,7 @@ static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,</div><div class='ctx'> 	struct i40e_aqc_get_set_rss_lut *cmd_resp =</div><div class='ctx'> 		   (struct i40e_aqc_get_set_rss_lut *)&amp;desc.params.raw;</div><div class='ctx'> 	int status;</div><div class='add'>+	u16 flags;</div><div class='ctx'> </div><div class='ctx'> 	if (set)</div><div class='ctx'> 		i40e_fill_default_direct_cmd_desc(&amp;desc,</div><div class='hunk'>@@ -260,23 +262,18 @@ static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);</div><div class='ctx'> </div><div class='del'>-	cmd_resp-&gt;vsi_id =</div><div class='del'>-			cpu_to_le16((u16)((vsi_id &lt;&lt;</div><div class='del'>-					  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &amp;</div><div class='del'>-					  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));</div><div class='del'>-	cmd_resp-&gt;vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);</div><div class='add'>+	vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |</div><div class='add'>+		 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1);</div><div class='add'>+	cmd_resp-&gt;vsi_id = cpu_to_le16(vsi_id);</div><div class='ctx'> </div><div class='ctx'> 	if (pf_lut)</div><div class='del'>-		cmd_resp-&gt;flags |= cpu_to_le16((u16)</div><div class='del'>-					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF &lt;&lt;</div><div class='del'>-					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &amp;</div><div class='del'>-					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));</div><div class='add'>+		flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,</div><div class='add'>+				   I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF);</div><div class='ctx'> 	else</div><div class='del'>-		cmd_resp-&gt;flags |= cpu_to_le16((u16)</div><div class='del'>-					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI &lt;&lt;</div><div class='del'>-					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &amp;</div><div class='del'>-					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));</div><div class='add'>+		flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,</div><div class='add'>+				   I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI);</div><div class='ctx'> </div><div class='add'>+	cmd_resp-&gt;flags = cpu_to_le16(flags);</div><div class='ctx'> 	status = i40e_asq_send_command(hw, &amp;desc, lut, lut_size, NULL);</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -346,11 +343,9 @@ static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);</div><div class='ctx'> </div><div class='del'>-	cmd_resp-&gt;vsi_id =</div><div class='del'>-			cpu_to_le16((u16)((vsi_id &lt;&lt;</div><div class='del'>-					  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &amp;</div><div class='del'>-					  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));</div><div class='del'>-	cmd_resp-&gt;vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);</div><div class='add'>+	vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |</div><div class='add'>+		 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1);</div><div class='add'>+	cmd_resp-&gt;vsi_id = cpu_to_le16(vsi_id);</div><div class='ctx'> </div><div class='ctx'> 	status = i40e_asq_send_command(hw, &amp;desc, key, key_size, NULL);</div><div class='ctx'> </div><div class='hunk'>@@ -669,11 +664,11 @@ int i40e_init_shared_code(struct i40e_hw *hw)</div><div class='ctx'> 	hw-&gt;phy.get_link_info = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Determine port number and PF number*/</div><div class='del'>-	port = (rd32(hw, I40E_PFGEN_PORTNUM) &amp; I40E_PFGEN_PORTNUM_PORT_NUM_MASK)</div><div class='del'>-					   &gt;&gt; I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;</div><div class='add'>+	port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,</div><div class='add'>+			 rd32(hw, I40E_PFGEN_PORTNUM));</div><div class='ctx'> 	hw-&gt;port = (u8)port;</div><div class='del'>-	ari = (rd32(hw, I40E_GLPCI_CAPSUP) &amp; I40E_GLPCI_CAPSUP_ARI_EN_MASK) &gt;&gt;</div><div class='del'>-						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;</div><div class='add'>+	ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,</div><div class='add'>+			rd32(hw, I40E_GLPCI_CAPSUP));</div><div class='ctx'> 	func_rid = rd32(hw, I40E_PF_FUNC_RID);</div><div class='ctx'> 	if (ari)</div><div class='ctx'> 		hw-&gt;pf_id = (u8)(func_rid &amp; 0xff);</div><div class='hunk'>@@ -991,9 +986,8 @@ int i40e_pf_reset(struct i40e_hw *hw)</div><div class='ctx'> 	 * The grst delay value is in 100ms units, and we'll wait a</div><div class='ctx'> 	 * couple counts longer to be sure we don't just miss the end.</div><div class='ctx'> 	 */</div><div class='del'>-	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &amp;</div><div class='del'>-		    I40E_GLGEN_RSTCTL_GRSTDEL_MASK) &gt;&gt;</div><div class='del'>-		    I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;</div><div class='add'>+	grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,</div><div class='add'>+			     rd32(hw, I40E_GLGEN_RSTCTL));</div><div class='ctx'> </div><div class='ctx'> 	/* It can take upto 15 secs for GRST steady state.</div><div class='ctx'> 	 * Bump it to 16 secs max to be safe.</div><div class='hunk'>@@ -1085,26 +1079,20 @@ void i40e_clear_hw(struct i40e_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* get number of interrupts, queues, and VFs */</div><div class='ctx'> 	val = rd32(hw, I40E_GLPCI_CNF2);</div><div class='del'>-	num_pf_int = (val &amp; I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) &gt;&gt;</div><div class='del'>-		     I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;</div><div class='del'>-	num_vf_int = (val &amp; I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) &gt;&gt;</div><div class='del'>-		     I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;</div><div class='add'>+	num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);</div><div class='add'>+	num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, I40E_PFLAN_QALLOC);</div><div class='del'>-	base_queue = (val &amp; I40E_PFLAN_QALLOC_FIRSTQ_MASK) &gt;&gt;</div><div class='del'>-		     I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;</div><div class='del'>-	j = (val &amp; I40E_PFLAN_QALLOC_LASTQ_MASK) &gt;&gt;</div><div class='del'>-	    I40E_PFLAN_QALLOC_LASTQ_SHIFT;</div><div class='add'>+	base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);</div><div class='add'>+	j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);</div><div class='ctx'> 	if (val &amp; I40E_PFLAN_QALLOC_VALID_MASK &amp;&amp; j &gt;= base_queue)</div><div class='ctx'> 		num_queues = (j - base_queue) + 1;</div><div class='ctx'> 	else</div><div class='ctx'> 		num_queues = 0;</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, I40E_PF_VT_PFALLOC);</div><div class='del'>-	i = (val &amp; I40E_PF_VT_PFALLOC_FIRSTVF_MASK) &gt;&gt;</div><div class='del'>-	    I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;</div><div class='del'>-	j = (val &amp; I40E_PF_VT_PFALLOC_LASTVF_MASK) &gt;&gt;</div><div class='del'>-	    I40E_PF_VT_PFALLOC_LASTVF_SHIFT;</div><div class='add'>+	i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);</div><div class='add'>+	j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);</div><div class='ctx'> 	if (val &amp; I40E_PF_VT_PFALLOC_VALID_MASK &amp;&amp; j &gt;= i)</div><div class='ctx'> 		num_vfs = (j - i) + 1;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -1199,8 +1187,7 @@ static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)</div><div class='ctx'> 	    !hw-&gt;func_caps.led[idx])</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));</div><div class='del'>-	port = (gpio_val &amp; I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) &gt;&gt;</div><div class='del'>-		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;</div><div class='add'>+	port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);</div><div class='ctx'> </div><div class='ctx'> 	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR</div><div class='ctx'> 	 * if it is not our port then ignore</div><div class='hunk'>@@ -1244,8 +1231,7 @@ u32 i40e_led_get(struct i40e_hw *hw)</div><div class='ctx'> 		if (!gpio_val)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		mode = (gpio_val &amp; I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) &gt;&gt;</div><div class='del'>-			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;</div><div class='add'>+		mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1288,14 +1274,14 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)</div><div class='ctx'> 				pin_func = I40E_PIN_FUNC_LED;</div><div class='ctx'> </div><div class='ctx'> 			gpio_val &amp;= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;</div><div class='del'>-			gpio_val |= ((pin_func &lt;&lt;</div><div class='del'>-				     I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &amp;</div><div class='del'>-				     I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);</div><div class='add'>+			gpio_val |=</div><div class='add'>+				FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK,</div><div class='add'>+					   pin_func);</div><div class='ctx'> 		}</div><div class='ctx'> 		gpio_val &amp;= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;</div><div class='ctx'> 		/* this &amp; is a bit of paranoia, but serves as a range check */</div><div class='del'>-		gpio_val |= ((mode &lt;&lt; I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &amp;</div><div class='del'>-			     I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);</div><div class='add'>+		gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK,</div><div class='add'>+				       mode);</div><div class='ctx'> </div><div class='ctx'> 		if (blink)</div><div class='ctx'> 			gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);</div><div class='hunk'>@@ -1374,8 +1360,8 @@ i40e_aq_get_phy_capabilities(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	if (report_init) {</div><div class='ctx'> 		if (hw-&gt;mac.type ==  I40E_MAC_XL710 &amp;&amp;</div><div class='del'>-		    hw-&gt;aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &amp;&amp;</div><div class='del'>-		    hw-&gt;aq.api_min_ver &gt;= I40E_MINOR_VER_GET_LINK_INFO_XL710) {</div><div class='add'>+		    i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,</div><div class='add'>+					  I40E_MINOR_VER_GET_LINK_INFO_XL710)) {</div><div class='ctx'> 			status = i40e_aq_get_link_info(hw, true, NULL, NULL);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			hw-&gt;phy.phy_types = le32_to_cpu(abilities-&gt;phy_type);</div><div class='hunk'>@@ -1645,12 +1631,11 @@ int i40e_aq_get_link_info(struct i40e_hw *hw,</div><div class='ctx'> 	else</div><div class='ctx'> 		hw_link_info-&gt;lse_enable = false;</div><div class='ctx'> </div><div class='del'>-	if ((hw-&gt;mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    (hw-&gt;aq.fw_maj_ver &lt; 4 || (hw-&gt;aq.fw_maj_ver == 4 &amp;&amp;</div><div class='del'>-	     hw-&gt;aq.fw_min_ver &lt; 40)) &amp;&amp; hw_link_info-&gt;phy_type == 0xE)</div><div class='add'>+	if (hw-&gt;mac.type == I40E_MAC_XL710 &amp;&amp; i40e_is_fw_ver_lt(hw, 4, 40) &amp;&amp;</div><div class='add'>+	    hw_link_info-&gt;phy_type == 0xE)</div><div class='ctx'> 		hw_link_info-&gt;phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps) &amp;&amp;</div><div class='ctx'> 	    hw-&gt;mac.type != I40E_MAC_X722) {</div><div class='ctx'> 		__le32 tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -1750,21 +1735,6 @@ int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * i40e_is_aq_api_ver_ge</div><div class='del'>- * @aq: pointer to AdminQ info containing HW API version to compare</div><div class='del'>- * @maj: API major value</div><div class='del'>- * @min: API minor value</div><div class='del'>- *</div><div class='del'>- * Assert whether current HW API version is greater/equal than provided.</div><div class='del'>- **/</div><div class='del'>-static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,</div><div class='del'>-				  u16 min)</div><div class='del'>-{</div><div class='del'>-	return (aq-&gt;api_maj_ver &gt; maj ||</div><div class='del'>-		(aq-&gt;api_maj_ver == maj &amp;&amp; aq-&gt;api_min_ver &gt;= min));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * i40e_aq_add_vsi</div><div class='ctx'>  * @hw: pointer to the hw struct</div><div class='ctx'>  * @vsi_ctx: pointer to a vsi context struct</div><div class='hunk'>@@ -1890,14 +1860,14 @@ int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	if (set) {</div><div class='ctx'> 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;</div><div class='del'>-		if (rx_only_promisc &amp;&amp; i40e_is_aq_api_ver_ge(&amp;hw-&gt;aq, 1, 5))</div><div class='add'>+		if (rx_only_promisc &amp;&amp; i40e_is_aq_api_ver_ge(hw, 1, 5))</div><div class='ctx'> 			flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;promiscuous_flags = cpu_to_le16(flags);</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);</div><div class='del'>-	if (i40e_is_aq_api_ver_ge(&amp;hw-&gt;aq, 1, 5))</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 5))</div><div class='ctx'> 		cmd-&gt;valid_flags |=</div><div class='ctx'> 			cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);</div><div class='ctx'> </div><div class='hunk'>@@ -2000,13 +1970,13 @@ int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	if (enable) {</div><div class='ctx'> 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;</div><div class='del'>-		if (i40e_is_aq_api_ver_ge(&amp;hw-&gt;aq, 1, 5))</div><div class='add'>+		if (i40e_is_aq_api_ver_ge(hw, 1, 5))</div><div class='ctx'> 			flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;promiscuous_flags = cpu_to_le16(flags);</div><div class='ctx'> 	cmd-&gt;valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);</div><div class='del'>-	if (i40e_is_aq_api_ver_ge(&amp;hw-&gt;aq, 1, 5))</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, 1, 5))</div><div class='ctx'> 		cmd-&gt;valid_flags |=</div><div class='ctx'> 			cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);</div><div class='ctx'> 	cmd-&gt;seid = cpu_to_le16(seid);</div><div class='hunk'>@@ -2253,7 +2223,7 @@ int i40e_aq_set_switch_config(struct i40e_hw *hw,</div><div class='ctx'> 	scfg-&gt;flags = cpu_to_le16(flags);</div><div class='ctx'> 	scfg-&gt;valid_flags = cpu_to_le16(valid_flags);</div><div class='ctx'> 	scfg-&gt;mode = mode;</div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_802_1AD_CAPABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_802_1AD, hw-&gt;caps)) {</div><div class='ctx'> 		scfg-&gt;switch_tag = cpu_to_le16(hw-&gt;switch_tag);</div><div class='ctx'> 		scfg-&gt;first_tag = cpu_to_le16(hw-&gt;first_tag);</div><div class='ctx'> 		scfg-&gt;second_tag = cpu_to_le16(hw-&gt;second_tag);</div><div class='hunk'>@@ -3530,8 +3500,7 @@ int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;type = mib_type &amp; I40E_AQ_LLDP_MIB_TYPE_MASK;</div><div class='del'>-	cmd-&gt;type |= ((bridge_type &lt;&lt; I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &amp;</div><div class='del'>-		       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);</div><div class='add'>+	cmd-&gt;type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type);</div><div class='ctx'> </div><div class='ctx'> 	desc.datalen = cpu_to_le16(buff_size);</div><div class='ctx'> </div><div class='hunk'>@@ -3637,7 +3606,7 @@ i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,</div><div class='ctx'> 		(struct i40e_aqc_lldp_restore *)&amp;desc.params.raw;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='del'>-	if (!(hw-&gt;flags &amp; I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw-&gt;caps)) {</div><div class='ctx'> 		i40e_debug(hw, I40E_DEBUG_ALL,</div><div class='ctx'> 			   "Restore LLDP not supported by current FW version.\n");</div><div class='ctx'> 		return -ENODEV;</div><div class='hunk'>@@ -3680,7 +3649,7 @@ int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,</div><div class='ctx'> 		cmd-&gt;command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;</div><div class='ctx'> </div><div class='ctx'> 	if (persist) {</div><div class='del'>-		if (hw-&gt;flags &amp; I40E_HW_FLAG_FW_LLDP_PERSISTENT)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw-&gt;caps))</div><div class='ctx'> 			cmd-&gt;command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;</div><div class='ctx'> 		else</div><div class='ctx'> 			i40e_debug(hw, I40E_DEBUG_ALL,</div><div class='hunk'>@@ -3713,7 +3682,7 @@ int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,</div><div class='ctx'> 	cmd-&gt;command = I40E_AQ_LLDP_AGENT_START;</div><div class='ctx'> </div><div class='ctx'> 	if (persist) {</div><div class='del'>-		if (hw-&gt;flags &amp; I40E_HW_FLAG_FW_LLDP_PERSISTENT)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw-&gt;caps))</div><div class='ctx'> 			cmd-&gt;command |= I40E_AQ_LLDP_AGENT_START_PERSIST;</div><div class='ctx'> 		else</div><div class='ctx'> 			i40e_debug(hw, I40E_DEBUG_ALL,</div><div class='hunk'>@@ -3741,7 +3710,7 @@ i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,</div><div class='ctx'> 		(struct i40e_aqc_set_dcb_parameters *)&amp;desc.params.raw;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='del'>-	if (!(hw-&gt;flags &amp; I40E_HW_FLAG_FW_LLDP_STOPPABLE))</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw-&gt;caps))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	i40e_fill_default_direct_cmd_desc(&amp;desc,</div><div class='hunk'>@@ -4212,8 +4181,7 @@ i40e_validate_filter_settings(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */</div><div class='ctx'> 	val = rd32(hw, I40E_GLHMC_FCOEFMAX);</div><div class='del'>-	fcoe_fmax = (val &amp; I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)</div><div class='del'>-		     &gt;&gt; I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;</div><div class='add'>+	fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);</div><div class='ctx'> 	if (fcoe_filt_size + fcoe_cntx_size &gt;  fcoe_fmax)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -4249,30 +4217,25 @@ int i40e_set_filter_control(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	/* Program required PE hash buckets for the PF */</div><div class='ctx'> 	val &amp;= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;</div><div class='del'>-	val |= ((u32)settings-&gt;pe_filt_num &lt;&lt; I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PFQF_CTL_0_PEHSIZE_MASK;</div><div class='add'>+	val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings-&gt;pe_filt_num);</div><div class='ctx'> 	/* Program required PE contexts for the PF */</div><div class='ctx'> 	val &amp;= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;</div><div class='del'>-	val |= ((u32)settings-&gt;pe_cntx_num &lt;&lt; I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PFQF_CTL_0_PEDSIZE_MASK;</div><div class='add'>+	val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings-&gt;pe_cntx_num);</div><div class='ctx'> </div><div class='ctx'> 	/* Program required FCoE hash buckets for the PF */</div><div class='ctx'> 	val &amp;= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;</div><div class='del'>-	val |= ((u32)settings-&gt;fcoe_filt_num &lt;&lt;</div><div class='del'>-			I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PFQF_CTL_0_PFFCHSIZE_MASK;</div><div class='add'>+	val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK,</div><div class='add'>+			  settings-&gt;fcoe_filt_num);</div><div class='ctx'> 	/* Program required FCoE DDP contexts for the PF */</div><div class='ctx'> 	val &amp;= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;</div><div class='del'>-	val |= ((u32)settings-&gt;fcoe_cntx_num &lt;&lt;</div><div class='del'>-			I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PFQF_CTL_0_PFFCDSIZE_MASK;</div><div class='add'>+	val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK,</div><div class='add'>+			  settings-&gt;fcoe_cntx_num);</div><div class='ctx'> </div><div class='ctx'> 	/* Program Hash LUT size for the PF */</div><div class='ctx'> 	val &amp;= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;</div><div class='ctx'> 	if (settings-&gt;hash_lut_size == I40E_HASH_LUT_SIZE_512)</div><div class='ctx'> 		hash_lut_size = 1;</div><div class='del'>-	val |= (hash_lut_size &lt;&lt; I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;</div><div class='add'>+	val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size);</div><div class='ctx'> </div><div class='ctx'> 	/* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */</div><div class='ctx'> 	if (settings-&gt;enable_fdir)</div><div class='hunk'>@@ -4673,8 +4636,7 @@ int i40e_read_phy_register_clause22(struct i40e_hw *hw,</div><div class='ctx'> 			   "PHY: Can't write command to external PHY.\n");</div><div class='ctx'> 	} else {</div><div class='ctx'> 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));</div><div class='del'>-		*value = (command &amp; I40E_GLGEN_MSRWD_MDIRDDATA_MASK) &gt;&gt;</div><div class='del'>-			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;</div><div class='add'>+		*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -4783,8 +4745,7 @@ int i40e_read_phy_register_clause45(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	if (!status) {</div><div class='ctx'> 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));</div><div class='del'>-		*value = (command &amp; I40E_GLGEN_MSRWD_MDIRDDATA_MASK) &gt;&gt;</div><div class='del'>-			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;</div><div class='add'>+		*value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		i40e_debug(hw, I40E_DEBUG_PHY,</div><div class='ctx'> 			   "PHY: Can't read register value from external PHY.\n");</div><div class='hunk'>@@ -5043,7 +5004,7 @@ static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	*reg_val = 0;</div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps)) {</div><div class='ctx'> 		status =</div><div class='ctx'> 		       i40e_aq_get_phy_register(hw,</div><div class='ctx'> 						I40E_AQ_PHY_REG_ACCESS_EXTERNAL,</div><div class='hunk'>@@ -5076,7 +5037,7 @@ static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,</div><div class='ctx'> 	int status;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps)) {</div><div class='ctx'> 		status =</div><div class='ctx'> 		       i40e_aq_set_phy_register(hw,</div><div class='ctx'> 						I40E_AQ_PHY_REG_ACCESS_EXTERNAL,</div><div class='hunk'>@@ -5115,7 +5076,7 @@ int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,</div><div class='ctx'> 	u8 port_num;</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps)) {</div><div class='ctx'> 		status =</div><div class='ctx'> 		      i40e_aq_get_phy_register(hw,</div><div class='ctx'> 					       I40E_AQ_PHY_REG_ACCESS_EXTERNAL,</div><div class='hunk'>@@ -5238,14 +5199,14 @@ int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,</div><div class='ctx'>  **/</div><div class='ctx'> u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)</div><div class='ctx'> {</div><div class='del'>-	bool use_register;</div><div class='add'>+	bool use_register = false;</div><div class='ctx'> 	int status = 0;</div><div class='ctx'> 	int retry = 5;</div><div class='ctx'> 	u32 val = 0;</div><div class='ctx'> </div><div class='del'>-	use_register = (((hw-&gt;aq.api_maj_ver == 1) &amp;&amp;</div><div class='del'>-			(hw-&gt;aq.api_min_ver &lt; 5)) ||</div><div class='del'>-			(hw-&gt;mac.type == I40E_MAC_X722));</div><div class='add'>+	if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw-&gt;mac.type == I40E_MAC_X722)</div><div class='add'>+		use_register = true;</div><div class='add'>+</div><div class='ctx'> 	if (!use_register) {</div><div class='ctx'> do_retry:</div><div class='ctx'> 		status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &amp;val, NULL);</div><div class='hunk'>@@ -5300,13 +5261,13 @@ int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,</div><div class='ctx'>  **/</div><div class='ctx'> void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)</div><div class='ctx'> {</div><div class='del'>-	bool use_register;</div><div class='add'>+	bool use_register = false;</div><div class='ctx'> 	int status = 0;</div><div class='ctx'> 	int retry = 5;</div><div class='ctx'> </div><div class='del'>-	use_register = (((hw-&gt;aq.api_maj_ver == 1) &amp;&amp;</div><div class='del'>-			(hw-&gt;aq.api_min_ver &lt; 5)) ||</div><div class='del'>-			(hw-&gt;mac.type == I40E_MAC_X722));</div><div class='add'>+	if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw-&gt;mac.type == I40E_MAC_X722)</div><div class='add'>+		use_register = true;</div><div class='add'>+</div><div class='ctx'> 	if (!use_register) {</div><div class='ctx'> do_retry:</div><div class='ctx'> 		status = i40e_aq_rx_ctl_write_register(hw, reg_addr,</div><div class='hunk'>@@ -5334,16 +5295,17 @@ static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,</div><div class='ctx'> 					  u8 mdio_num,</div><div class='ctx'> 					  struct i40e_aqc_phy_register_access *cmd)</div><div class='ctx'> {</div><div class='del'>-	if (set_mdio &amp;&amp; cmd-&gt;phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {</div><div class='del'>-		if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)</div><div class='del'>-			cmd-&gt;cmd_flags |=</div><div class='del'>-				I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |</div><div class='del'>-				((mdio_num &lt;&lt;</div><div class='del'>-				I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &amp;</div><div class='del'>-				I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);</div><div class='del'>-		else</div><div class='del'>-			i40e_debug(hw, I40E_DEBUG_PHY,</div><div class='del'>-				   "MDIO I/F number selection not supported by current FW version.\n");</div><div class='add'>+	if (!set_mdio ||</div><div class='add'>+	    cmd-&gt;phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw-&gt;caps)) {</div><div class='add'>+		cmd-&gt;cmd_flags |=</div><div class='add'>+			I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |</div><div class='add'>+			FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK,</div><div class='add'>+				   mdio_num);</div><div class='add'>+	} else {</div><div class='add'>+		i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n");</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5928,9 +5890,8 @@ i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,</div><div class='ctx'> 		u16 tnl_type;</div><div class='ctx'> 		u32 ti;</div><div class='ctx'> </div><div class='del'>-		tnl_type = (le16_to_cpu(filters[i].element.flags) &amp;</div><div class='del'>-			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) &gt;&gt;</div><div class='del'>-			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;</div><div class='add'>+		tnl_type = le16_get_bits(filters[i].element.flags,</div><div class='add'>+					 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);</div><div class='ctx'> </div><div class='ctx'> 		/* Due to hardware eccentricities, the VNI for Geneve is shifted</div><div class='ctx'> 		 * one more byte further than normally used for Tenant ID in</div><div class='hunk'>@@ -6022,9 +5983,8 @@ i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,</div><div class='ctx'> 		u16 tnl_type;</div><div class='ctx'> 		u32 ti;</div><div class='ctx'> </div><div class='del'>-		tnl_type = (le16_to_cpu(filters[i].element.flags) &amp;</div><div class='del'>-			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) &gt;&gt;</div><div class='del'>-			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;</div><div class='add'>+		tnl_type = le16_get_bits(filters[i].element.flags,</div><div class='add'>+					 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);</div><div class='ctx'> </div><div class='ctx'> 		/* Due to hardware eccentricities, the VNI for Geneve is shifted</div><div class='ctx'> 		 * one more byte further than normally used for Tenant ID in</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.c b/drivers/net/ethernet/intel/i40e/i40e_dcb.c<br/>index 68602fc375f6..9d88ed6105fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_dcb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_dcb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_dcb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_dcb.c</a></div><div class='hunk'>@@ -1,6 +1,8 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2021 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include "i40e_adminq.h"</div><div class='ctx'> #include "i40e_alloc.h"</div><div class='ctx'> #include "i40e_dcb.h"</div><div class='ctx'> #include "i40e_prototype.h"</div><div class='hunk'>@@ -20,8 +22,7 @@ int i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, I40E_PRTDCB_GENS);</div><div class='del'>-	*status = (u16)((reg &amp; I40E_PRTDCB_GENS_DCBX_STATUS_MASK) &gt;&gt;</div><div class='del'>-			I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT);</div><div class='add'>+	*status = FIELD_GET(I40E_PRTDCB_GENS_DCBX_STATUS_MASK, reg);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -50,12 +51,9 @@ static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	 * |1bit | 1bit|3 bits|3bits|</div><div class='ctx'> 	 */</div><div class='ctx'> 	etscfg = &amp;dcbcfg-&gt;etscfg;</div><div class='del'>-	etscfg-&gt;willing = (u8)((buf[offset] &amp; I40E_IEEE_ETS_WILLING_MASK) &gt;&gt;</div><div class='del'>-			       I40E_IEEE_ETS_WILLING_SHIFT);</div><div class='del'>-	etscfg-&gt;cbs = (u8)((buf[offset] &amp; I40E_IEEE_ETS_CBS_MASK) &gt;&gt;</div><div class='del'>-			   I40E_IEEE_ETS_CBS_SHIFT);</div><div class='del'>-	etscfg-&gt;maxtcs = (u8)((buf[offset] &amp; I40E_IEEE_ETS_MAXTC_MASK) &gt;&gt;</div><div class='del'>-			      I40E_IEEE_ETS_MAXTC_SHIFT);</div><div class='add'>+	etscfg-&gt;willing = FIELD_GET(I40E_IEEE_ETS_WILLING_MASK, buf[offset]);</div><div class='add'>+	etscfg-&gt;cbs = FIELD_GET(I40E_IEEE_ETS_CBS_MASK, buf[offset]);</div><div class='add'>+	etscfg-&gt;maxtcs = FIELD_GET(I40E_IEEE_ETS_MAXTC_MASK, buf[offset]);</div><div class='ctx'> </div><div class='ctx'> 	/* Move offset to Priority Assignment Table */</div><div class='ctx'> 	offset++;</div><div class='hunk'>@@ -69,11 +67,9 @@ static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	 *        -----------------------------------------</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_IEEE_ETS_PRIO_1_MASK) &gt;&gt;</div><div class='del'>-				I40E_IEEE_ETS_PRIO_1_SHIFT);</div><div class='del'>-		etscfg-&gt;prioritytable[i * 2] =  priority;</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_IEEE_ETS_PRIO_0_MASK) &gt;&gt;</div><div class='del'>-				I40E_IEEE_ETS_PRIO_0_SHIFT);</div><div class='add'>+		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]);</div><div class='add'>+		etscfg-&gt;prioritytable[i * 2] = priority;</div><div class='add'>+		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]);</div><div class='ctx'> 		etscfg-&gt;prioritytable[i * 2 + 1] = priority;</div><div class='ctx'> 		offset++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -124,12 +120,10 @@ static void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	 *        -----------------------------------------</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_IEEE_ETS_PRIO_1_MASK) &gt;&gt;</div><div class='del'>-				I40E_IEEE_ETS_PRIO_1_SHIFT);</div><div class='del'>-		dcbcfg-&gt;etsrec.prioritytable[i*2] =  priority;</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_IEEE_ETS_PRIO_0_MASK) &gt;&gt;</div><div class='del'>-				I40E_IEEE_ETS_PRIO_0_SHIFT);</div><div class='del'>-		dcbcfg-&gt;etsrec.prioritytable[i*2 + 1] = priority;</div><div class='add'>+		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_1_MASK, buf[offset]);</div><div class='add'>+		dcbcfg-&gt;etsrec.prioritytable[i * 2] = priority;</div><div class='add'>+		priority = FIELD_GET(I40E_IEEE_ETS_PRIO_0_MASK, buf[offset]);</div><div class='add'>+		dcbcfg-&gt;etsrec.prioritytable[(i * 2) + 1] = priority;</div><div class='ctx'> 		offset++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -170,12 +164,9 @@ static void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	 * -----------------------------------------</div><div class='ctx'> 	 * |1bit | 1bit|2 bits|4bits| 1 octet      |</div><div class='ctx'> 	 */</div><div class='del'>-	dcbcfg-&gt;pfc.willing = (u8)((buf[0] &amp; I40E_IEEE_PFC_WILLING_MASK) &gt;&gt;</div><div class='del'>-				   I40E_IEEE_PFC_WILLING_SHIFT);</div><div class='del'>-	dcbcfg-&gt;pfc.mbc = (u8)((buf[0] &amp; I40E_IEEE_PFC_MBC_MASK) &gt;&gt;</div><div class='del'>-			       I40E_IEEE_PFC_MBC_SHIFT);</div><div class='del'>-	dcbcfg-&gt;pfc.pfccap = (u8)((buf[0] &amp; I40E_IEEE_PFC_CAP_MASK) &gt;&gt;</div><div class='del'>-				  I40E_IEEE_PFC_CAP_SHIFT);</div><div class='add'>+	dcbcfg-&gt;pfc.willing = FIELD_GET(I40E_IEEE_PFC_WILLING_MASK, buf[0]);</div><div class='add'>+	dcbcfg-&gt;pfc.mbc = FIELD_GET(I40E_IEEE_PFC_MBC_MASK, buf[0]);</div><div class='add'>+	dcbcfg-&gt;pfc.pfccap = FIELD_GET(I40E_IEEE_PFC_CAP_MASK, buf[0]);</div><div class='ctx'> 	dcbcfg-&gt;pfc.pfcenable = buf[1];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -196,8 +187,7 @@ static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	u8 *buf;</div><div class='ctx'> </div><div class='ctx'> 	typelength = ntohs(tlv-&gt;typelength);</div><div class='del'>-	length = (u16)((typelength &amp; I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-		       I40E_LLDP_TLV_LEN_SHIFT);</div><div class='add'>+	length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='ctx'> 	buf = tlv-&gt;tlvinfo;</div><div class='ctx'> </div><div class='ctx'> 	/* The App priority table starts 5 octets after TLV header */</div><div class='hunk'>@@ -215,12 +205,10 @@ static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	 *        -----------------------------------------</div><div class='ctx'> 	 */</div><div class='ctx'> 	while (offset &lt; length) {</div><div class='del'>-		dcbcfg-&gt;app[i].priority = (u8)((buf[offset] &amp;</div><div class='del'>-						I40E_IEEE_APP_PRIO_MASK) &gt;&gt;</div><div class='del'>-					       I40E_IEEE_APP_PRIO_SHIFT);</div><div class='del'>-		dcbcfg-&gt;app[i].selector = (u8)((buf[offset] &amp;</div><div class='del'>-						I40E_IEEE_APP_SEL_MASK) &gt;&gt;</div><div class='del'>-					       I40E_IEEE_APP_SEL_SHIFT);</div><div class='add'>+		dcbcfg-&gt;app[i].priority = FIELD_GET(I40E_IEEE_APP_PRIO_MASK,</div><div class='add'>+						    buf[offset]);</div><div class='add'>+		dcbcfg-&gt;app[i].selector = FIELD_GET(I40E_IEEE_APP_SEL_MASK,</div><div class='add'>+						    buf[offset]);</div><div class='ctx'> 		dcbcfg-&gt;app[i].protocolid = (buf[offset + 1] &lt;&lt; 0x8) |</div><div class='ctx'> 					     buf[offset + 2];</div><div class='ctx'> 		/* Move to next app */</div><div class='hunk'>@@ -248,8 +236,7 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	u8 subtype;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	subtype = (u8)((ouisubtype &amp; I40E_LLDP_TLV_SUBTYPE_MASK) &gt;&gt;</div><div class='del'>-		       I40E_LLDP_TLV_SUBTYPE_SHIFT);</div><div class='add'>+	subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype);</div><div class='ctx'> 	switch (subtype) {</div><div class='ctx'> 	case I40E_IEEE_SUBTYPE_ETS_CFG:</div><div class='ctx'> 		i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg);</div><div class='hunk'>@@ -299,11 +286,9 @@ static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,</div><div class='ctx'> 	 *        -----------------------------------------</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_CEE_PGID_PRIO_1_MASK) &gt;&gt;</div><div class='del'>-				 I40E_CEE_PGID_PRIO_1_SHIFT);</div><div class='del'>-		etscfg-&gt;prioritytable[i * 2] =  priority;</div><div class='del'>-		priority = (u8)((buf[offset] &amp; I40E_CEE_PGID_PRIO_0_MASK) &gt;&gt;</div><div class='del'>-				 I40E_CEE_PGID_PRIO_0_SHIFT);</div><div class='add'>+		priority = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK, buf[offset]);</div><div class='add'>+		etscfg-&gt;prioritytable[i * 2] = priority;</div><div class='add'>+		priority = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK, buf[offset]);</div><div class='ctx'> 		etscfg-&gt;prioritytable[i * 2 + 1] = priority;</div><div class='ctx'> 		offset++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -360,8 +345,7 @@ static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,</div><div class='ctx'> 	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	typelength = ntohs(tlv-&gt;hdr.typelen);</div><div class='del'>-	length = (u16)((typelength &amp; I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-		       I40E_LLDP_TLV_LEN_SHIFT);</div><div class='add'>+	length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='ctx'> </div><div class='ctx'> 	dcbcfg-&gt;numapps = length / sizeof(*app);</div><div class='ctx'> </div><div class='hunk'>@@ -417,15 +401,13 @@ static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	u32 ouisubtype;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	subtype = (u8)((ouisubtype &amp; I40E_LLDP_TLV_SUBTYPE_MASK) &gt;&gt;</div><div class='del'>-		       I40E_LLDP_TLV_SUBTYPE_SHIFT);</div><div class='add'>+	subtype = FIELD_GET(I40E_LLDP_TLV_SUBTYPE_MASK, ouisubtype);</div><div class='ctx'> 	/* Return if not CEE DCBX */</div><div class='ctx'> 	if (subtype != I40E_CEE_DCBX_TYPE)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	typelength = ntohs(tlv-&gt;typelength);</div><div class='del'>-	tlvlen = (u16)((typelength &amp; I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-			I40E_LLDP_TLV_LEN_SHIFT);</div><div class='add'>+	tlvlen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='ctx'> 	len = sizeof(tlv-&gt;typelength) + sizeof(ouisubtype) +</div><div class='ctx'> 	      sizeof(struct i40e_cee_ctrl_tlv);</div><div class='ctx'> 	/* Return if no CEE DCBX Feature TLVs */</div><div class='hunk'>@@ -435,11 +417,8 @@ static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);</div><div class='ctx'> 	while (feat_tlv_count &lt; I40E_CEE_MAX_FEAT_TYPE) {</div><div class='ctx'> 		typelength = ntohs(sub_tlv-&gt;hdr.typelen);</div><div class='del'>-		sublen = (u16)((typelength &amp;</div><div class='del'>-				I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-				I40E_LLDP_TLV_LEN_SHIFT);</div><div class='del'>-		subtype = (u8)((typelength &amp; I40E_LLDP_TLV_TYPE_MASK) &gt;&gt;</div><div class='del'>-				I40E_LLDP_TLV_TYPE_SHIFT);</div><div class='add'>+		sublen = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='add'>+		subtype = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength);</div><div class='ctx'> 		switch (subtype) {</div><div class='ctx'> 		case I40E_CEE_SUBTYPE_PG_CFG:</div><div class='ctx'> 			i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);</div><div class='hunk'>@@ -476,8 +455,7 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 	u32 oui;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	oui = (u32)((ouisubtype &amp; I40E_LLDP_TLV_OUI_MASK) &gt;&gt;</div><div class='del'>-		    I40E_LLDP_TLV_OUI_SHIFT);</div><div class='add'>+	oui = FIELD_GET(I40E_LLDP_TLV_OUI_MASK, ouisubtype);</div><div class='ctx'> 	switch (oui) {</div><div class='ctx'> 	case I40E_IEEE_8021QAZ_OUI:</div><div class='ctx'> 		i40e_parse_ieee_tlv(tlv, dcbcfg);</div><div class='hunk'>@@ -515,10 +493,8 @@ int i40e_lldp_to_dcb_config(u8 *lldpmib,</div><div class='ctx'> 	tlv = (struct i40e_lldp_org_tlv *)lldpmib;</div><div class='ctx'> 	while (1) {</div><div class='ctx'> 		typelength = ntohs(tlv-&gt;typelength);</div><div class='del'>-		type = (u16)((typelength &amp; I40E_LLDP_TLV_TYPE_MASK) &gt;&gt;</div><div class='del'>-			     I40E_LLDP_TLV_TYPE_SHIFT);</div><div class='del'>-		length = (u16)((typelength &amp; I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-			       I40E_LLDP_TLV_LEN_SHIFT);</div><div class='add'>+		type = FIELD_GET(I40E_LLDP_TLV_TYPE_MASK, typelength);</div><div class='add'>+		length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='ctx'> 		offset += sizeof(typelength) + length;</div><div class='ctx'> </div><div class='ctx'> 		/* END TLV or beyond LLDPDU size */</div><div class='hunk'>@@ -592,7 +568,7 @@ static void i40e_cee_to_dcb_v1_config(</div><div class='ctx'> {</div><div class='ctx'> 	u16 status, tlv_status = le16_to_cpu(cee_cfg-&gt;tlv_status);</div><div class='ctx'> 	u16 app_prio = le16_to_cpu(cee_cfg-&gt;oper_app_prio);</div><div class='del'>-	u8 i, tc, err;</div><div class='add'>+	u8 i, err;</div><div class='ctx'> </div><div class='ctx'> 	/* CEE PG data to ETS config */</div><div class='ctx'> 	dcbcfg-&gt;etscfg.maxtcs = cee_cfg-&gt;oper_num_tc;</div><div class='hunk'>@@ -601,13 +577,13 @@ static void i40e_cee_to_dcb_v1_config(</div><div class='ctx'> 	 * from those in the CEE Priority Group sub-TLV.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='del'>-		tc = (u8)((cee_cfg-&gt;oper_prio_tc[i] &amp;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_0_MASK) &gt;&gt;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_0_SHIFT);</div><div class='del'>-		dcbcfg-&gt;etscfg.prioritytable[i * 2] =  tc;</div><div class='del'>-		tc = (u8)((cee_cfg-&gt;oper_prio_tc[i] &amp;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_1_MASK) &gt;&gt;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_1_SHIFT);</div><div class='add'>+		u8 tc;</div><div class='add'>+</div><div class='add'>+		tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK,</div><div class='add'>+			       cee_cfg-&gt;oper_prio_tc[i]);</div><div class='add'>+		dcbcfg-&gt;etscfg.prioritytable[i * 2] = tc;</div><div class='add'>+		tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK,</div><div class='add'>+			       cee_cfg-&gt;oper_prio_tc[i]);</div><div class='ctx'> 		dcbcfg-&gt;etscfg.prioritytable[i*2 + 1] = tc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -629,8 +605,7 @@ static void i40e_cee_to_dcb_v1_config(</div><div class='ctx'> 	dcbcfg-&gt;pfc.pfcenable = cee_cfg-&gt;oper_pfc_en;</div><div class='ctx'> 	dcbcfg-&gt;pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;</div><div class='ctx'> </div><div class='del'>-	status = (tlv_status &amp; I40E_AQC_CEE_APP_STATUS_MASK) &gt;&gt;</div><div class='del'>-		  I40E_AQC_CEE_APP_STATUS_SHIFT;</div><div class='add'>+	status = FIELD_GET(I40E_AQC_CEE_APP_STATUS_MASK, tlv_status);</div><div class='ctx'> 	err = (status &amp; I40E_TLV_STATUS_ERR) ? 1 : 0;</div><div class='ctx'> 	/* Add APPs if Error is False */</div><div class='ctx'> 	if (!err) {</div><div class='hunk'>@@ -639,22 +614,19 @@ static void i40e_cee_to_dcb_v1_config(</div><div class='ctx'> </div><div class='ctx'> 		/* FCoE APP */</div><div class='ctx'> 		dcbcfg-&gt;app[0].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_FCOE_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_FCOE_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[0].selector = I40E_APP_SEL_ETHTYPE;</div><div class='ctx'> 		dcbcfg-&gt;app[0].protocolid = I40E_APP_PROTOID_FCOE;</div><div class='ctx'> </div><div class='ctx'> 		/* iSCSI APP */</div><div class='ctx'> 		dcbcfg-&gt;app[1].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_ISCSI_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_ISCSI_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[1].selector = I40E_APP_SEL_TCPIP;</div><div class='ctx'> 		dcbcfg-&gt;app[1].protocolid = I40E_APP_PROTOID_ISCSI;</div><div class='ctx'> </div><div class='ctx'> 		/* FIP APP */</div><div class='ctx'> 		dcbcfg-&gt;app[2].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_FIP_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_FIP_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[2].selector = I40E_APP_SEL_ETHTYPE;</div><div class='ctx'> 		dcbcfg-&gt;app[2].protocolid = I40E_APP_PROTOID_FIP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -673,7 +645,7 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> {</div><div class='ctx'> 	u32 status, tlv_status = le32_to_cpu(cee_cfg-&gt;tlv_status);</div><div class='ctx'> 	u16 app_prio = le16_to_cpu(cee_cfg-&gt;oper_app_prio);</div><div class='del'>-	u8 i, tc, err, sync, oper;</div><div class='add'>+	u8 i, err, sync, oper;</div><div class='ctx'> </div><div class='ctx'> 	/* CEE PG data to ETS config */</div><div class='ctx'> 	dcbcfg-&gt;etscfg.maxtcs = cee_cfg-&gt;oper_num_tc;</div><div class='hunk'>@@ -682,13 +654,13 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> 	 * from those in the CEE Priority Group sub-TLV.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='del'>-		tc = (u8)((cee_cfg-&gt;oper_prio_tc[i] &amp;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_0_MASK) &gt;&gt;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_0_SHIFT);</div><div class='del'>-		dcbcfg-&gt;etscfg.prioritytable[i * 2] =  tc;</div><div class='del'>-		tc = (u8)((cee_cfg-&gt;oper_prio_tc[i] &amp;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_1_MASK) &gt;&gt;</div><div class='del'>-			 I40E_CEE_PGID_PRIO_1_SHIFT);</div><div class='add'>+		u8 tc;</div><div class='add'>+</div><div class='add'>+		tc = FIELD_GET(I40E_CEE_PGID_PRIO_0_MASK,</div><div class='add'>+			       cee_cfg-&gt;oper_prio_tc[i]);</div><div class='add'>+		dcbcfg-&gt;etscfg.prioritytable[i * 2] = tc;</div><div class='add'>+		tc = FIELD_GET(I40E_CEE_PGID_PRIO_1_MASK,</div><div class='add'>+			       cee_cfg-&gt;oper_prio_tc[i]);</div><div class='ctx'> 		dcbcfg-&gt;etscfg.prioritytable[i * 2 + 1] = tc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -711,8 +683,7 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> 	dcbcfg-&gt;pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;</div><div class='ctx'> </div><div class='ctx'> 	i = 0;</div><div class='del'>-	status = (tlv_status &amp; I40E_AQC_CEE_FCOE_STATUS_MASK) &gt;&gt;</div><div class='del'>-		  I40E_AQC_CEE_FCOE_STATUS_SHIFT;</div><div class='add'>+	status = FIELD_GET(I40E_AQC_CEE_FCOE_STATUS_MASK, tlv_status);</div><div class='ctx'> 	err = (status &amp; I40E_TLV_STATUS_ERR) ? 1 : 0;</div><div class='ctx'> 	sync = (status &amp; I40E_TLV_STATUS_SYNC) ? 1 : 0;</div><div class='ctx'> 	oper = (status &amp; I40E_TLV_STATUS_OPER) ? 1 : 0;</div><div class='hunk'>@@ -720,15 +691,13 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> 	if (!err &amp;&amp; sync &amp;&amp; oper) {</div><div class='ctx'> 		/* FCoE APP */</div><div class='ctx'> 		dcbcfg-&gt;app[i].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_FCOE_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_FCOE_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_FCOE_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[i].selector = I40E_APP_SEL_ETHTYPE;</div><div class='ctx'> 		dcbcfg-&gt;app[i].protocolid = I40E_APP_PROTOID_FCOE;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = (tlv_status &amp; I40E_AQC_CEE_ISCSI_STATUS_MASK) &gt;&gt;</div><div class='del'>-		  I40E_AQC_CEE_ISCSI_STATUS_SHIFT;</div><div class='add'>+	status = FIELD_GET(I40E_AQC_CEE_ISCSI_STATUS_MASK, tlv_status);</div><div class='ctx'> 	err = (status &amp; I40E_TLV_STATUS_ERR) ? 1 : 0;</div><div class='ctx'> 	sync = (status &amp; I40E_TLV_STATUS_SYNC) ? 1 : 0;</div><div class='ctx'> 	oper = (status &amp; I40E_TLV_STATUS_OPER) ? 1 : 0;</div><div class='hunk'>@@ -736,15 +705,13 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> 	if (!err &amp;&amp; sync &amp;&amp; oper) {</div><div class='ctx'> 		/* iSCSI APP */</div><div class='ctx'> 		dcbcfg-&gt;app[i].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_ISCSI_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_ISCSI_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_ISCSI_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[i].selector = I40E_APP_SEL_TCPIP;</div><div class='ctx'> 		dcbcfg-&gt;app[i].protocolid = I40E_APP_PROTOID_ISCSI;</div><div class='ctx'> 		i++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = (tlv_status &amp; I40E_AQC_CEE_FIP_STATUS_MASK) &gt;&gt;</div><div class='del'>-		  I40E_AQC_CEE_FIP_STATUS_SHIFT;</div><div class='add'>+	status = FIELD_GET(I40E_AQC_CEE_FIP_STATUS_MASK, tlv_status);</div><div class='ctx'> 	err = (status &amp; I40E_TLV_STATUS_ERR) ? 1 : 0;</div><div class='ctx'> 	sync = (status &amp; I40E_TLV_STATUS_SYNC) ? 1 : 0;</div><div class='ctx'> 	oper = (status &amp; I40E_TLV_STATUS_OPER) ? 1 : 0;</div><div class='hunk'>@@ -752,8 +719,7 @@ static void i40e_cee_to_dcb_config(</div><div class='ctx'> 	if (!err &amp;&amp; sync &amp;&amp; oper) {</div><div class='ctx'> 		/* FIP APP */</div><div class='ctx'> 		dcbcfg-&gt;app[i].priority =</div><div class='del'>-			(app_prio &amp; I40E_AQC_CEE_APP_FIP_MASK) &gt;&gt;</div><div class='del'>-			 I40E_AQC_CEE_APP_FIP_SHIFT;</div><div class='add'>+			FIELD_GET(I40E_AQC_CEE_APP_FIP_MASK, app_prio);</div><div class='ctx'> 		dcbcfg-&gt;app[i].selector = I40E_APP_SEL_ETHTYPE;</div><div class='ctx'> 		dcbcfg-&gt;app[i].protocolid = I40E_APP_PROTOID_FIP;</div><div class='ctx'> 		i++;</div><div class='hunk'>@@ -804,14 +770,11 @@ int i40e_get_dcb_config(struct i40e_hw *hw)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* If Firmware version &lt; v4.33 on X710/XL710, IEEE only */</div><div class='del'>-	if ((hw-&gt;mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    (((hw-&gt;aq.fw_maj_ver == 4) &amp;&amp; (hw-&gt;aq.fw_min_ver &lt; 33)) ||</div><div class='del'>-	      (hw-&gt;aq.fw_maj_ver &lt; 4)))</div><div class='add'>+	if (hw-&gt;mac.type == I40E_MAC_XL710 &amp;&amp; i40e_is_fw_ver_lt(hw, 4, 33))</div><div class='ctx'> 		return i40e_get_ieee_dcb_config(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* If Firmware version == v4.33 on X710/XL710, use old CEE struct */</div><div class='del'>-	if ((hw-&gt;mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    ((hw-&gt;aq.fw_maj_ver == 4) &amp;&amp; (hw-&gt;aq.fw_min_ver == 33))) {</div><div class='add'>+	if (hw-&gt;mac.type == I40E_MAC_XL710 &amp;&amp; i40e_is_fw_ver_eq(hw, 4, 33)) {</div><div class='ctx'> 		ret = i40e_aq_get_cee_dcb_config(hw, &amp;cee_v1_cfg,</div><div class='ctx'> 						 sizeof(cee_v1_cfg), NULL);</div><div class='ctx'> 		if (!ret) {</div><div class='hunk'>@@ -877,7 +840,7 @@ int i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/* Read LLDP NVM area */</div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_FW_LLDP_PERSISTENT) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw-&gt;caps)) {</div><div class='ctx'> 		u8 offset = 0;</div><div class='ctx'> </div><div class='ctx'> 		if (hw-&gt;mac.type == I40E_MAC_XL710)</div><div class='hunk'>@@ -1189,7 +1152,7 @@ static void i40e_add_ieee_app_pri_tlv(struct i40e_lldp_org_tlv *tlv,</div><div class='ctx'> 		selector = dcbcfg-&gt;app[i].selector &amp; 0x7;</div><div class='ctx'> 		buf[offset] = (priority &lt;&lt; I40E_IEEE_APP_PRIO_SHIFT) | selector;</div><div class='ctx'> 		buf[offset + 1] = (dcbcfg-&gt;app[i].protocolid &gt;&gt; 0x8) &amp; 0xFF;</div><div class='del'>-		buf[offset + 2] =  dcbcfg-&gt;app[i].protocolid &amp; 0xFF;</div><div class='add'>+		buf[offset + 2] = dcbcfg-&gt;app[i].protocolid &amp; 0xFF;</div><div class='ctx'> 		/* Move to next app */</div><div class='ctx'> 		offset += 3;</div><div class='ctx'> 		i++;</div><div class='hunk'>@@ -1285,8 +1248,7 @@ int i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,</div><div class='ctx'> 	do {</div><div class='ctx'> 		i40e_add_dcb_tlv(tlv, dcbcfg, tlvid++);</div><div class='ctx'> 		typelength = ntohs(tlv-&gt;typelength);</div><div class='del'>-		length = (u16)((typelength &amp; I40E_LLDP_TLV_LEN_MASK) &gt;&gt;</div><div class='del'>-				I40E_LLDP_TLV_LEN_SHIFT);</div><div class='add'>+		length = FIELD_GET(I40E_LLDP_TLV_LEN_MASK, typelength);</div><div class='ctx'> 		if (length)</div><div class='ctx'> 			offset += length + I40E_IEEE_TLV_HEADER_LENGTH;</div><div class='ctx'> 		/* END TLV or beyond LLDPDU size */</div><div class='hunk'>@@ -1321,20 +1283,16 @@ void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,</div><div class='ctx'> 	u32 reg = rd32(hw, I40E_PRTDCB_RETSC);</div><div class='ctx'> </div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RETSC_ETS_MODE_MASK;</div><div class='del'>-	reg |= ((u32)ets_mode &lt;&lt; I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_RETSC_ETS_MODE_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RETSC_ETS_MODE_MASK, ets_mode);</div><div class='ctx'> </div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK;</div><div class='del'>-	reg |= ((u32)non_ets_mode &lt;&lt; I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK, non_ets_mode);</div><div class='ctx'> </div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK;</div><div class='del'>-	reg |= (max_exponent &lt;&lt; I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK, max_exponent);</div><div class='ctx'> </div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RETSC_LLTC_MASK;</div><div class='del'>-	reg |= (lltc_map &lt;&lt; I40E_PRTDCB_RETSC_LLTC_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_RETSC_LLTC_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RETSC_LLTC_MASK, lltc_map);</div><div class='ctx'> 	wr32(hw, I40E_PRTDCB_RETSC, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1389,14 +1347,12 @@ void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,</div><div class='ctx'> 	 */</div><div class='ctx'> 	reg = rd32(hw, I40E_PRT_SWR_PM_THR);</div><div class='ctx'> 	reg &amp;= ~I40E_PRT_SWR_PM_THR_THRESHOLD_MASK;</div><div class='del'>-	reg |= (threshold &lt;&lt; I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) &amp;</div><div class='del'>-		I40E_PRT_SWR_PM_THR_THRESHOLD_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRT_SWR_PM_THR_THRESHOLD_MASK, threshold);</div><div class='ctx'> 	wr32(hw, I40E_PRT_SWR_PM_THR, reg);</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, I40E_PRTDCB_RPPMC);</div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK;</div><div class='del'>-	reg |= (fifo_size &lt;&lt; I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK, fifo_size);</div><div class='ctx'> 	wr32(hw, I40E_PRTDCB_RPPMC, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1438,19 +1394,17 @@ void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,</div><div class='ctx'> 		reg &amp;= ~I40E_PRTDCB_MFLCN_RFCE_MASK;</div><div class='ctx'> 		reg &amp;= ~I40E_PRTDCB_MFLCN_RPFCE_MASK;</div><div class='ctx'> 		if (pfc_en) {</div><div class='del'>-			reg |= BIT(I40E_PRTDCB_MFLCN_RPFCM_SHIFT) &amp;</div><div class='del'>-				I40E_PRTDCB_MFLCN_RPFCM_MASK;</div><div class='del'>-			reg |= ((u32)pfc_en &lt;&lt; I40E_PRTDCB_MFLCN_RPFCE_SHIFT) &amp;</div><div class='del'>-				I40E_PRTDCB_MFLCN_RPFCE_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTDCB_MFLCN_RPFCM_MASK, 1);</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTDCB_MFLCN_RPFCE_MASK,</div><div class='add'>+					  pfc_en);</div><div class='ctx'> 		}</div><div class='ctx'> 		wr32(hw, I40E_PRTDCB_MFLCN, reg);</div><div class='ctx'> </div><div class='ctx'> 		reg = rd32(hw, I40E_PRTDCB_FCCFG);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTDCB_FCCFG_TFCE_MASK;</div><div class='ctx'> 		if (pfc_en)</div><div class='del'>-			reg |= (I40E_DCB_PFC_ENABLED &lt;&lt;</div><div class='del'>-				I40E_PRTDCB_FCCFG_TFCE_SHIFT) &amp;</div><div class='del'>-				I40E_PRTDCB_FCCFG_TFCE_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTDCB_FCCFG_TFCE_MASK,</div><div class='add'>+					  I40E_DCB_PFC_ENABLED);</div><div class='ctx'> 		wr32(hw, I40E_PRTDCB_FCCFG, reg);</div><div class='ctx'> </div><div class='ctx'> 		/* FCTTV and FCRTV to be set by default */</div><div class='hunk'>@@ -1468,25 +1422,22 @@ void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK;</div><div class='del'>-		reg |= ((u32)pfc_en &lt;&lt;</div><div class='del'>-			   I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) &amp;</div><div class='del'>-			I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK,</div><div class='add'>+				  pfc_en);</div><div class='ctx'> 		wr32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE, reg);</div><div class='ctx'> </div><div class='ctx'> 		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK;</div><div class='del'>-		reg |= ((u32)pfc_en &lt;&lt;</div><div class='del'>-			   I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) &amp;</div><div class='del'>-			I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK,</div><div class='add'>+				  pfc_en);</div><div class='ctx'> 		wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE, reg);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX; i++) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK;</div><div class='ctx'> 			if (pfc_en) {</div><div class='del'>-				reg |= ((u32)refresh_time &lt;&lt;</div><div class='del'>-					I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) &amp;</div><div class='del'>-					I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK;</div><div class='add'>+				reg |= FIELD_PREP(I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK,</div><div class='add'>+						  refresh_time);</div><div class='ctx'> 			}</div><div class='ctx'> 			wr32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(i), reg);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1498,14 +1449,12 @@ void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, I40E_PRTDCB_TC2PFC);</div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_TC2PFC_TC2PFC_MASK;</div><div class='del'>-	reg |= ((u32)tc2pfc &lt;&lt; I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_TC2PFC_TC2PFC_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_TC2PFC_TC2PFC_MASK, tc2pfc);</div><div class='ctx'> 	wr32(hw, I40E_PRTDCB_TC2PFC, reg);</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, I40E_PRTDCB_RUP);</div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_RUP_NOVLANUP_MASK;</div><div class='del'>-	reg |= ((u32)first_pfc_prio &lt;&lt; I40E_PRTDCB_RUP_NOVLANUP_SHIFT) &amp;</div><div class='del'>-		 I40E_PRTDCB_RUP_NOVLANUP_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_RUP_NOVLANUP_MASK, first_pfc_prio);</div><div class='ctx'> 	wr32(hw, I40E_PRTDCB_RUP, reg);</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, I40E_PRTDCB_TDPMC);</div><div class='hunk'>@@ -1537,8 +1486,7 @@ void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc)</div><div class='ctx'> 	u32 reg = rd32(hw, I40E_PRTDCB_GENC);</div><div class='ctx'> </div><div class='ctx'> 	reg &amp;= ~I40E_PRTDCB_GENC_NUMTC_MASK;</div><div class='del'>-	reg |= ((u32)num_tc &lt;&lt; I40E_PRTDCB_GENC_NUMTC_SHIFT) &amp;</div><div class='del'>-		I40E_PRTDCB_GENC_NUMTC_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTDCB_GENC_NUMTC_MASK, num_tc);</div><div class='ctx'> 	wr32(hw, I40E_PRTDCB_GENC, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1552,8 +1500,7 @@ u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u32 reg = rd32(hw, I40E_PRTDCB_GENC);</div><div class='ctx'> </div><div class='del'>-	return (u8)((reg &amp; I40E_PRTDCB_GENC_NUMTC_MASK) &gt;&gt;</div><div class='del'>-		I40E_PRTDCB_GENC_NUMTC_SHIFT);</div><div class='add'>+	return FIELD_GET(I40E_PRTDCB_GENC_NUMTC_MASK, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1577,12 +1524,12 @@ void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,</div><div class='ctx'> 		reg &amp;= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |</div><div class='ctx'> 			 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |</div><div class='ctx'> 			 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);</div><div class='del'>-		reg |= ((u32)bw_share[i] &lt;&lt; I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &amp;</div><div class='del'>-			 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;</div><div class='del'>-		reg |= ((u32)mode[i] &lt;&lt; I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &amp;</div><div class='del'>-			 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;</div><div class='del'>-		reg |= ((u32)prio_type[i] &lt;&lt; I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &amp;</div><div class='del'>-			 I40E_PRTDCB_RETSTCC_ETSTC_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_BWSHARE_MASK,</div><div class='add'>+				  bw_share[i]);</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK,</div><div class='add'>+				  mode[i]);</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTDCB_RETSTCC_ETSTC_MASK,</div><div class='add'>+				  prio_type[i]);</div><div class='ctx'> 		wr32(hw, I40E_PRTDCB_RETSTCC(i), reg);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -1722,8 +1669,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 	if (new_val &lt; old_val) {</div><div class='ctx'> 		reg = rd32(hw, I40E_PRTRPB_SLW);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTRPB_SLW_SLW_MASK;</div><div class='del'>-		reg |= (new_val &lt;&lt; I40E_PRTRPB_SLW_SLW_SHIFT) &amp;</div><div class='del'>-			I40E_PRTRPB_SLW_SLW_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val);</div><div class='ctx'> 		wr32(hw, I40E_PRTRPB_SLW, reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1736,8 +1682,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &lt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_SLT(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_SLT_SLT_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_SLT_SLT_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_SLT_SLT_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_SLT_SLT_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_SLT(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1746,8 +1692,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &lt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_DLW(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_DLW_DLW_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_DLW_DLW_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_DLW_DLW_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_DLW_DLW_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_DLW(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1758,8 +1704,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 	if (new_val &lt; old_val) {</div><div class='ctx'> 		reg = rd32(hw, I40E_PRTRPB_SHW);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTRPB_SHW_SHW_MASK;</div><div class='del'>-		reg |= (new_val &lt;&lt; I40E_PRTRPB_SHW_SHW_SHIFT) &amp;</div><div class='del'>-			I40E_PRTRPB_SHW_SHW_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val);</div><div class='ctx'> 		wr32(hw, I40E_PRTRPB_SHW, reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1772,8 +1717,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &lt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_SHT(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_SHT_SHT_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_SHT_SHT_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_SHT_SHT_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_SHT_SHT_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_SHT(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1782,8 +1727,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &lt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_DHW(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_DHW_DHW_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_DHW_DHW_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_DHW_DHW_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_DHW_DHW_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_DHW(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1793,8 +1738,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		new_val = new_pb_cfg-&gt;tc_pool_size[i];</div><div class='ctx'> 		reg = rd32(hw, I40E_PRTRPB_DPS(i));</div><div class='ctx'> 		reg &amp;= ~I40E_PRTRPB_DPS_DPS_TCN_MASK;</div><div class='del'>-		reg |= (new_val &lt;&lt; I40E_PRTRPB_DPS_DPS_TCN_SHIFT) &amp;</div><div class='del'>-			I40E_PRTRPB_DPS_DPS_TCN_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTRPB_DPS_DPS_TCN_MASK, new_val);</div><div class='ctx'> 		wr32(hw, I40E_PRTRPB_DPS(i), reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1802,8 +1746,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 	new_val = new_pb_cfg-&gt;shared_pool_size;</div><div class='ctx'> 	reg = rd32(hw, I40E_PRTRPB_SPS);</div><div class='ctx'> 	reg &amp;= ~I40E_PRTRPB_SPS_SPS_MASK;</div><div class='del'>-	reg |= (new_val &lt;&lt; I40E_PRTRPB_SPS_SPS_SHIFT) &amp;</div><div class='del'>-		I40E_PRTRPB_SPS_SPS_MASK;</div><div class='add'>+	reg |= FIELD_PREP(I40E_PRTRPB_SPS_SPS_MASK, new_val);</div><div class='ctx'> 	wr32(hw, I40E_PRTRPB_SPS, reg);</div><div class='ctx'> </div><div class='ctx'> 	/* Program the shared pool low water mark per port if increasing */</div><div class='hunk'>@@ -1812,8 +1755,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 	if (new_val &gt; old_val) {</div><div class='ctx'> 		reg = rd32(hw, I40E_PRTRPB_SLW);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTRPB_SLW_SLW_MASK;</div><div class='del'>-		reg |= (new_val &lt;&lt; I40E_PRTRPB_SLW_SLW_SHIFT) &amp;</div><div class='del'>-			I40E_PRTRPB_SLW_SLW_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTRPB_SLW_SLW_MASK, new_val);</div><div class='ctx'> 		wr32(hw, I40E_PRTRPB_SLW, reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1826,8 +1768,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &gt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_SLT(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_SLT_SLT_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_SLT_SLT_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_SLT_SLT_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_SLT_SLT_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_SLT(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1836,8 +1778,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &gt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_DLW(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_DLW_DLW_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_DLW_DLW_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_DLW_DLW_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_DLW_DLW_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_DLW(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1848,8 +1790,7 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 	if (new_val &gt; old_val) {</div><div class='ctx'> 		reg = rd32(hw, I40E_PRTRPB_SHW);</div><div class='ctx'> 		reg &amp;= ~I40E_PRTRPB_SHW_SHW_MASK;</div><div class='del'>-		reg |= (new_val &lt;&lt; I40E_PRTRPB_SHW_SHW_SHIFT) &amp;</div><div class='del'>-			I40E_PRTRPB_SHW_SHW_MASK;</div><div class='add'>+		reg |= FIELD_PREP(I40E_PRTRPB_SHW_SHW_MASK, new_val);</div><div class='ctx'> 		wr32(hw, I40E_PRTRPB_SHW, reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1862,8 +1803,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &gt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_SHT(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_SHT_SHT_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_SHT_SHT_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_SHT_SHT_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_SHT_SHT_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_SHT(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1872,8 +1813,8 @@ void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,</div><div class='ctx'> 		if (new_val &gt; old_val) {</div><div class='ctx'> 			reg = rd32(hw, I40E_PRTRPB_DHW(i));</div><div class='ctx'> 			reg &amp;= ~I40E_PRTRPB_DHW_DHW_TCN_MASK;</div><div class='del'>-			reg |= (new_val &lt;&lt; I40E_PRTRPB_DHW_DHW_TCN_SHIFT) &amp;</div><div class='del'>-				I40E_PRTRPB_DHW_DHW_TCN_MASK;</div><div class='add'>+			reg |= FIELD_PREP(I40E_PRTRPB_DHW_DHW_TCN_MASK,</div><div class='add'>+					  new_val);</div><div class='ctx'> 			wr32(hw, I40E_PRTRPB_DHW(i), reg);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c b/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c<br/>index 077a95dad32c..b96a92187ab3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c</a></div><div class='hunk'>@@ -21,8 +21,7 @@ static void i40e_get_pfc_delay(struct i40e_hw *hw, u16 *delay)</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, I40E_PRTDCB_GENC);</div><div class='del'>-	*delay = (u16)((val &amp; I40E_PRTDCB_GENC_PFCLDA_MASK) &gt;&gt;</div><div class='del'>-		       I40E_PRTDCB_GENC_PFCLDA_SHIFT);</div><div class='add'>+	*delay = FIELD_GET(I40E_PRTDCB_GENC_PFCLDA_MASK, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -310,8 +309,8 @@ static u8 i40e_dcbnl_getstate(struct net_device *netdev)</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(netdev);</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;pf-&gt;pdev-&gt;dev, "DCB state=%d\n",</div><div class='del'>-		!!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED));</div><div class='del'>-	return !!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED);</div><div class='add'>+		test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags) ? 1 : 0);</div><div class='add'>+	return test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags) ? 1 : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -331,19 +330,19 @@ static u8 i40e_dcbnl_setstate(struct net_device *netdev, u8 state)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;pf-&gt;pdev-&gt;dev, "new state=%d current state=%d\n",</div><div class='del'>-		state, (pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED) ? 1 : 0);</div><div class='add'>+		state, test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags) ? 1 : 0);</div><div class='ctx'> 	/* Nothing to do */</div><div class='del'>-	if (!state == !(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED))</div><div class='add'>+	if (!state == !test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (i40e_is_sw_dcb(pf)) {</div><div class='ctx'> 		if (state) {</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_DCB_ENABLED;</div><div class='add'>+			set_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 			memcpy(&amp;pf-&gt;hw.desired_dcbx_config,</div><div class='ctx'> 			       &amp;pf-&gt;hw.local_dcbx_config,</div><div class='ctx'> 			       sizeof(struct i40e_dcbx_config));</div><div class='ctx'> 		} else {</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Cannot directly manipulate FW LLDP Agent */</div><div class='hunk'>@@ -653,7 +652,7 @@ static u8 i40e_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(netdev);</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		return I40E_DCBNL_STATUS_ERROR;</div><div class='ctx'> </div><div class='ctx'> 	switch (capid) {</div><div class='hunk'>@@ -693,7 +692,7 @@ static int i40e_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(netdev);</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	*num = I40E_MAX_TRAFFIC_CLASS;</div><div class='hunk'>@@ -827,15 +826,12 @@ static void i40e_dcbnl_get_perm_hw_addr(struct net_device *dev,</div><div class='ctx'> 					u8 *perm_addr)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(dev);</div><div class='del'>-	int i, j;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	memset(perm_addr, 0xff, MAX_ADDR_LEN);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; dev-&gt;addr_len; i++)</div><div class='ctx'> 		perm_addr[i] = pf-&gt;hw.mac.perm_addr[i];</div><div class='del'>-</div><div class='del'>-	for (j = 0; j &lt; dev-&gt;addr_len; j++, i++)</div><div class='del'>-		perm_addr[i] = pf-&gt;hw.mac.san_addr[j];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct dcbnl_rtnl_ops dcbnl_ops = {</div><div class='hunk'>@@ -891,11 +887,11 @@ void i40e_dcbnl_set_all(struct i40e_vsi *vsi)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* DCB not enabled */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* MFP mode but not an iSCSI PF so return */</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) &amp;&amp; !(hw-&gt;func_caps.iscsi))</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags) &amp;&amp; !(hw-&gt;func_caps.iscsi))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dcbxcfg = &amp;hw-&gt;local_dcbx_config;</div><div class='hunk'>@@ -1002,7 +998,7 @@ void i40e_dcbnl_flush_apps(struct i40e_pf *pf,</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* MFP mode but not an iSCSI PF so return */</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) &amp;&amp; !(pf-&gt;hw.func_caps.iscsi))</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags) &amp;&amp; !(pf-&gt;hw.func_caps.iscsi))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; old_cfg-&gt;numapps; i++) {</div><div class='hunk'>@@ -1025,7 +1021,7 @@ void i40e_dcbnl_setup(struct i40e_vsi *vsi)</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(dev);</div><div class='ctx'> </div><div class='ctx'> 	/* Not DCB capable */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;dcbnl_ops = &amp;dcbnl_ops;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_ddp.c b/drivers/net/ethernet/intel/i40e/i40e_ddp.c<br/>index cf25bfc5dc3f..2f53f0f53bc3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ddp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_ddp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ddp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ddp.c</a></div><div class='hunk'>@@ -81,8 +81,8 @@ static int i40e_ddp_does_profile_exist(struct i40e_hw *hw,</div><div class='ctx'> static bool i40e_ddp_profiles_overlap(struct i40e_profile_info *new,</div><div class='ctx'> 				      struct i40e_profile_info *old)</div><div class='ctx'> {</div><div class='del'>-	unsigned int group_id_old = (u8)((old-&gt;track_id &amp; 0x00FF0000) &gt;&gt; 16);</div><div class='del'>-	unsigned int group_id_new = (u8)((new-&gt;track_id &amp; 0x00FF0000) &gt;&gt; 16);</div><div class='add'>+	unsigned int group_id_old = FIELD_GET(0x00FF0000, old-&gt;track_id);</div><div class='add'>+	unsigned int group_id_new = FIELD_GET(0x00FF0000, new-&gt;track_id);</div><div class='ctx'> </div><div class='ctx'> 	/* 0x00 group must be only the first */</div><div class='ctx'> 	if (group_id_new == 0)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_debug.h b/drivers/net/ethernet/intel/i40e/i40e_debug.h<br/>index 27ebc72d8bfe..e9871dfb32bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_debug.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_debug.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_debug.h</a></div><div class='hunk'>@@ -37,6 +37,7 @@ struct i40e_hw;</div><div class='ctx'> struct device *i40e_hw_to_dev(struct i40e_hw *hw);</div><div class='ctx'> </div><div class='ctx'> #define hw_dbg(hw, S, A...) dev_dbg(i40e_hw_to_dev(hw), S, ##A)</div><div class='add'>+#define hw_warn(hw, S, A...) dev_warn(i40e_hw_to_dev(hw), S, ##A)</div><div class='ctx'> </div><div class='ctx'> #define i40e_debug(h, m, s, ...)				\</div><div class='ctx'> do {								\</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c<br/>index 999c9708def5..ef70ddbe9c2f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_debugfs.c</a></div><div class='hunk'>@@ -147,9 +147,8 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)</div><div class='ctx'> 			 "    state[%d] = %08lx\n",</div><div class='ctx'> 			 i, vsi-&gt;state[i]);</div><div class='ctx'> 	if (vsi == pf-&gt;vsi[pf-&gt;lan_vsi])</div><div class='del'>-		dev_info(&amp;pf-&gt;pdev-&gt;dev, "    MAC address: %pM SAN MAC: %pM Port MAC: %pM\n",</div><div class='add'>+		dev_info(&amp;pf-&gt;pdev-&gt;dev, "    MAC address: %pM Port MAC: %pM\n",</div><div class='ctx'> 			 pf-&gt;hw.mac.addr,</div><div class='del'>-			 pf-&gt;hw.mac.san_addr,</div><div class='ctx'> 			 pf-&gt;hw.mac.port_addr);</div><div class='ctx'> 	hash_for_each(vsi-&gt;mac_filter_hash, bkt, f, hlist) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -820,8 +819,8 @@ static ssize_t i40e_dbg_command_write(struct file *filp,</div><div class='ctx'> 		/* By default we are in VEPA mode, if this is the first VF/VMDq</div><div class='ctx'> 		 * VSI to be added switch to VEB mode.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!(pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)) {</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+		if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags)) {</div><div class='add'>+			set_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1029,9 +1028,6 @@ static ssize_t i40e_dbg_command_write(struct file *filp,</div><div class='ctx'> 				 "emp reset count: %d\n", pf-&gt;empr_count);</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "pf reset count: %d\n", pf-&gt;pfr_count);</div><div class='del'>-			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='del'>-				 "pf tx sluggish count: %d\n",</div><div class='del'>-				 pf-&gt;tx_sluggish_count);</div><div class='ctx'> 		} else if (strncmp(&amp;cmd_buf[5], "port", 4) == 0) {</div><div class='ctx'> 			struct i40e_aqc_query_port_ets_config_resp *bw_data;</div><div class='ctx'> 			struct i40e_dcbx_config *cfg =</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.h b/drivers/net/ethernet/intel/i40e/i40e_diag.h<br/>index ece3a6b9a5c6..ab20202a3da3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_diag.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_diag.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_diag.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_diag.h</a></div><div class='hunk'>@@ -4,6 +4,7 @@</div><div class='ctx'> #ifndef _I40E_DIAG_H_</div><div class='ctx'> #define _I40E_DIAG_H_</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='ctx'> #include "i40e_adminq_cmd.h"</div><div class='ctx'> </div><div class='ctx'> /* forward-declare the HW struct for the compiler */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c<br/>index fd7163128c4d..c841779713f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ethtool.c</a></div><div class='hunk'>@@ -430,35 +430,35 @@ static const char i40e_gstrings_test[][ETH_GSTRING_LEN] = {</div><div class='ctx'> </div><div class='ctx'> struct i40e_priv_flags {</div><div class='ctx'> 	char flag_string[ETH_GSTRING_LEN];</div><div class='del'>-	u64 flag;</div><div class='add'>+	u8 bitno;</div><div class='ctx'> 	bool read_only;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define I40E_PRIV_FLAG(_name, _flag, _read_only) { \</div><div class='add'>+#define I40E_PRIV_FLAG(_name, _bitno, _read_only) { \</div><div class='ctx'> 	.flag_string = _name, \</div><div class='del'>-	.flag = _flag, \</div><div class='add'>+	.bitno = _bitno, \</div><div class='ctx'> 	.read_only = _read_only, \</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {</div><div class='ctx'> 	/* NOTE: MFP setting cannot be changed */</div><div class='del'>-	I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENABLED, 1),</div><div class='add'>+	I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENA, 1),</div><div class='ctx'> 	I40E_PRIV_FLAG("total-port-shutdown",</div><div class='del'>-		       I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED, 1),</div><div class='del'>-	I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),</div><div class='del'>-	I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),</div><div class='del'>-	I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),</div><div class='del'>-	I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),</div><div class='add'>+		       I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, 1),</div><div class='add'>+	I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENA, 0),</div><div class='add'>+	I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENA, 0),</div><div class='add'>+	I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENA, 0),</div><div class='add'>+	I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENA, 0),</div><div class='ctx'> 	I40E_PRIV_FLAG("link-down-on-close",</div><div class='del'>-		       I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED, 0),</div><div class='del'>-	I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),</div><div class='add'>+		       I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, 0),</div><div class='add'>+	I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX_ENA, 0),</div><div class='ctx'> 	I40E_PRIV_FLAG("disable-source-pruning",</div><div class='del'>-		       I40E_FLAG_SOURCE_PRUNING_DISABLED, 0),</div><div class='del'>-	I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_DISABLE_FW_LLDP, 0),</div><div class='add'>+		       I40E_FLAG_SOURCE_PRUNING_DIS, 0),</div><div class='add'>+	I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_FW_LLDP_DIS, 0),</div><div class='ctx'> 	I40E_PRIV_FLAG("rs-fec", I40E_FLAG_RS_FEC, 0),</div><div class='ctx'> 	I40E_PRIV_FLAG("base-r-fec", I40E_FLAG_BASE_R_FEC, 0),</div><div class='ctx'> 	I40E_PRIV_FLAG("vf-vlan-pruning",</div><div class='del'>-		       I40E_FLAG_VF_VLAN_PRUNING, 0),</div><div class='add'>+		       I40E_FLAG_VF_VLAN_PRUNING_ENA, 0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)</div><div class='hunk'>@@ -466,7 +466,7 @@ static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {</div><div class='ctx'> /* Private flags with a global effect, restricted to PF 0 */</div><div class='ctx'> static const struct i40e_priv_flags i40e_gl_gstrings_priv_flags[] = {</div><div class='ctx'> 	I40E_PRIV_FLAG("vf-true-promisc-support",</div><div class='del'>-		       I40E_FLAG_TRUE_PROMISC_SUPPORT, 0),</div><div class='add'>+		       I40E_FLAG_TRUE_PROMISC_ENA, 0),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define I40E_GL_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gl_gstrings_priv_flags)</div><div class='hunk'>@@ -502,7 +502,7 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,</div><div class='ctx'> 		if (hw_link_info-&gt;requested_speeds &amp; I40E_LINK_SPEED_1GB)</div><div class='ctx'> 			ethtool_link_ksettings_add_link_mode(ks, advertising,</div><div class='ctx'> 							     1000baseT_Full);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_100M_SGMII_CAPABLE) {</div><div class='add'>+		if (test_bit(I40E_HW_CAP_100M_SGMII, pf-&gt;hw.caps)) {</div><div class='ctx'> 			ethtool_link_ksettings_add_link_mode(ks, supported,</div><div class='ctx'> 							     100baseT_Full);</div><div class='ctx'> 			ethtool_link_ksettings_add_link_mode(ks, advertising,</div><div class='hunk'>@@ -601,7 +601,7 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,</div><div class='ctx'> 							     10000baseKX4_Full);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (phy_types &amp; I40E_CAP_PHY_TYPE_10GBASE_KR &amp;&amp;</div><div class='del'>-	    !(pf-&gt;hw_features &amp; I40E_HW_HAVE_CRT_RETIMER)) {</div><div class='add'>+	    !test_bit(I40E_HW_CAP_CRT_RETIMER, pf-&gt;hw.caps)) {</div><div class='ctx'> 		ethtool_link_ksettings_add_link_mode(ks, supported,</div><div class='ctx'> 						     10000baseKR_Full);</div><div class='ctx'> 		if (hw_link_info-&gt;requested_speeds &amp; I40E_LINK_SPEED_10GB)</div><div class='hunk'>@@ -609,7 +609,7 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,</div><div class='ctx'> 							     10000baseKR_Full);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (phy_types &amp; I40E_CAP_PHY_TYPE_1000BASE_KX &amp;&amp;</div><div class='del'>-	    !(pf-&gt;hw_features &amp; I40E_HW_HAVE_CRT_RETIMER)) {</div><div class='add'>+	    !test_bit(I40E_HW_CAP_CRT_RETIMER, pf-&gt;hw.caps)) {</div><div class='ctx'> 		ethtool_link_ksettings_add_link_mode(ks, supported,</div><div class='ctx'> 						     1000baseKX_Full);</div><div class='ctx'> 		if (hw_link_info-&gt;requested_speeds &amp; I40E_LINK_SPEED_1GB)</div><div class='hunk'>@@ -917,7 +917,7 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,</div><div class='ctx'> 		if (hw_link_info-&gt;requested_speeds &amp; I40E_LINK_SPEED_1GB)</div><div class='ctx'> 			ethtool_link_ksettings_add_link_mode(ks, advertising,</div><div class='ctx'> 							     1000baseT_Full);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_100M_SGMII_CAPABLE) {</div><div class='add'>+		if (test_bit(I40E_HW_CAP_100M_SGMII, pf-&gt;hw.caps)) {</div><div class='ctx'> 			ethtool_link_ksettings_add_link_mode(ks, supported,</div><div class='ctx'> 							     100baseT_Full);</div><div class='ctx'> 			if (hw_link_info-&gt;requested_speeds &amp;</div><div class='hunk'>@@ -1488,12 +1488,8 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)</div><div class='ctx'> 	struct i40e_pf *pf = np-&gt;vsi-&gt;back;</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	int status = 0;</div><div class='del'>-	u32 flags = 0;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	flags = READ_ONCE(pf-&gt;flags);</div><div class='del'>-	i40e_set_fec_in_flags(fec_cfg, &amp;flags);</div><div class='del'>-</div><div class='ctx'> 	/* Get the current phy config */</div><div class='ctx'> 	memset(&amp;abilities, 0, sizeof(abilities));</div><div class='ctx'> 	status = i40e_aq_get_phy_capabilities(hw, false, false, &amp;abilities,</div><div class='hunk'>@@ -1525,7 +1521,7 @@ static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)</div><div class='ctx'> 			err = -EAGAIN;</div><div class='ctx'> 			goto done;</div><div class='ctx'> 		}</div><div class='del'>-		pf-&gt;flags = flags;</div><div class='add'>+		i40e_set_fec_in_flags(fec_cfg, pf-&gt;flags);</div><div class='ctx'> 		status = i40e_update_link_info(hw);</div><div class='ctx'> 		if (status)</div><div class='ctx'> 			/* debug level message only due to relation to the link</div><div class='hunk'>@@ -1599,7 +1595,7 @@ static int i40e_set_fec_param(struct net_device *netdev,</div><div class='ctx'> 		return -EPERM;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.type == I40E_MAC_X722 &amp;&amp;</div><div class='del'>-	    !(hw-&gt;flags &amp; I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE)) {</div><div class='add'>+	    !test_bit(I40E_HW_CAP_X722_FEC_REQUEST, hw-&gt;caps)) {</div><div class='ctx'> 		netdev_err(netdev, "Setting FEC encoding not supported by firmware. Please update the NVM image.\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1915,7 +1911,7 @@ static int i40e_get_eeprom(struct net_device *netdev,</div><div class='ctx'> 			len = eeprom-&gt;len - (I40E_NVM_SECTOR_SIZE * i);</div><div class='ctx'> 			last = true;</div><div class='ctx'> 		}</div><div class='del'>-		offset = eeprom-&gt;offset + (I40E_NVM_SECTOR_SIZE * i),</div><div class='add'>+		offset = eeprom-&gt;offset + (I40E_NVM_SECTOR_SIZE * i);</div><div class='ctx'> 		ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,</div><div class='ctx'> 				(u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),</div><div class='ctx'> 				last, NULL);</div><div class='hunk'>@@ -1956,9 +1952,8 @@ static int i40e_get_eeprom_len(struct net_device *netdev)</div><div class='ctx'> 		val = X722_EEPROM_SCOPE_LIMIT + 1;</div><div class='ctx'> 		return val;</div><div class='ctx'> 	}</div><div class='del'>-	val = (rd32(hw, I40E_GLPCI_LBARCTRL)</div><div class='del'>-		&amp; I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)</div><div class='del'>-		&gt;&gt; I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;</div><div class='add'>+	val = FIELD_GET(I40E_GLPCI_LBARCTRL_FL_SIZE_MASK,</div><div class='add'>+			rd32(hw, I40E_GLPCI_LBARCTRL));</div><div class='ctx'> 	/* register returns value in power of 2, 64Kbyte chunks. */</div><div class='ctx'> 	val = (64 * 1024) * BIT(val);</div><div class='ctx'> 	return val;</div><div class='hunk'>@@ -2015,6 +2010,18 @@ static void i40e_get_drvinfo(struct net_device *netdev,</div><div class='ctx'> 		drvinfo-&gt;n_priv_flags += I40E_GL_PRIV_FLAGS_STR_LEN;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 i40e_get_max_num_descriptors(struct i40e_pf *pf)</div><div class='add'>+{</div><div class='add'>+	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+</div><div class='add'>+	switch (hw-&gt;mac.type) {</div><div class='add'>+	case I40E_MAC_XL710:</div><div class='add'>+		return I40E_MAX_NUM_DESCRIPTORS_XL710;</div><div class='add'>+	default:</div><div class='add'>+		return I40E_MAX_NUM_DESCRIPTORS;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void i40e_get_ringparam(struct net_device *netdev,</div><div class='ctx'> 			       struct ethtool_ringparam *ring,</div><div class='ctx'> 			       struct kernel_ethtool_ringparam *kernel_ring,</div><div class='hunk'>@@ -2024,8 +2031,8 @@ static void i40e_get_ringparam(struct net_device *netdev,</div><div class='ctx'> 	struct i40e_pf *pf = np-&gt;vsi-&gt;back;</div><div class='ctx'> 	struct i40e_vsi *vsi = pf-&gt;vsi[pf-&gt;lan_vsi];</div><div class='ctx'> </div><div class='del'>-	ring-&gt;rx_max_pending = I40E_MAX_NUM_DESCRIPTORS;</div><div class='del'>-	ring-&gt;tx_max_pending = I40E_MAX_NUM_DESCRIPTORS;</div><div class='add'>+	ring-&gt;rx_max_pending = i40e_get_max_num_descriptors(pf);</div><div class='add'>+	ring-&gt;tx_max_pending = i40e_get_max_num_descriptors(pf);</div><div class='ctx'> 	ring-&gt;rx_mini_max_pending = 0;</div><div class='ctx'> 	ring-&gt;rx_jumbo_max_pending = 0;</div><div class='ctx'> 	ring-&gt;rx_pending = vsi-&gt;rx_rings[0]-&gt;count;</div><div class='hunk'>@@ -2050,12 +2057,12 @@ static int i40e_set_ringparam(struct net_device *netdev,</div><div class='ctx'> 			      struct kernel_ethtool_ringparam *kernel_ring,</div><div class='ctx'> 			      struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='add'>+	u32 new_rx_count, new_tx_count, max_num_descriptors;</div><div class='ctx'> 	struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;</div><div class='ctx'> 	struct i40e_netdev_priv *np = netdev_priv(netdev);</div><div class='ctx'> 	struct i40e_hw *hw = &amp;np-&gt;vsi-&gt;back-&gt;hw;</div><div class='ctx'> 	struct i40e_vsi *vsi = np-&gt;vsi;</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='del'>-	u32 new_rx_count, new_tx_count;</div><div class='ctx'> 	u16 tx_alloc_queue_pairs;</div><div class='ctx'> 	int timeout = 50;</div><div class='ctx'> 	int i, err = 0;</div><div class='hunk'>@@ -2063,14 +2070,15 @@ static int i40e_set_ringparam(struct net_device *netdev,</div><div class='ctx'> 	if ((ring-&gt;rx_mini_pending) || (ring-&gt;rx_jumbo_pending))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (ring-&gt;tx_pending &gt; I40E_MAX_NUM_DESCRIPTORS ||</div><div class='add'>+	max_num_descriptors = i40e_get_max_num_descriptors(pf);</div><div class='add'>+	if (ring-&gt;tx_pending &gt; max_num_descriptors ||</div><div class='ctx'> 	    ring-&gt;tx_pending &lt; I40E_MIN_NUM_DESCRIPTORS ||</div><div class='del'>-	    ring-&gt;rx_pending &gt; I40E_MAX_NUM_DESCRIPTORS ||</div><div class='add'>+	    ring-&gt;rx_pending &gt; max_num_descriptors ||</div><div class='ctx'> 	    ring-&gt;rx_pending &lt; I40E_MIN_NUM_DESCRIPTORS) {</div><div class='ctx'> 		netdev_info(netdev,</div><div class='ctx'> 			    "Descriptors requested (Tx: %d / Rx: %d) out of range [%d-%d]\n",</div><div class='ctx'> 			    ring-&gt;tx_pending, ring-&gt;rx_pending,</div><div class='del'>-			    I40E_MIN_NUM_DESCRIPTORS, I40E_MAX_NUM_DESCRIPTORS);</div><div class='add'>+			    I40E_MIN_NUM_DESCRIPTORS, max_num_descriptors);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2419,7 +2427,7 @@ static void i40e_get_ethtool_stats(struct net_device *netdev,</div><div class='ctx'> </div><div class='ctx'> 	veb_stats = ((pf-&gt;lan_veb != I40E_NO_VEB) &amp;&amp;</div><div class='ctx'> 		     (pf-&gt;lan_veb &lt; I40E_MAX_VEB) &amp;&amp;</div><div class='del'>-		     (pf-&gt;flags &amp; I40E_FLAG_VEB_STATS_ENABLED));</div><div class='add'>+		     test_bit(I40E_FLAG_VEB_STATS_ENA, pf-&gt;flags));</div><div class='ctx'> </div><div class='ctx'> 	if (veb_stats) {</div><div class='ctx'> 		veb = pf-&gt;veb[pf-&gt;lan_veb];</div><div class='hunk'>@@ -2514,13 +2522,11 @@ static void i40e_get_priv_flag_strings(struct net_device *netdev, u8 *data)</div><div class='ctx'> 	u8 *p = data;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; I40E_PRIV_FLAGS_STR_LEN; i++)</div><div class='del'>-		ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-				i40e_gstrings_priv_flags[i].flag_string);</div><div class='add'>+		ethtool_puts(&amp;p, i40e_gstrings_priv_flags[i].flag_string);</div><div class='ctx'> 	if (pf-&gt;hw.pf_id != 0)</div><div class='ctx'> 		return;</div><div class='ctx'> 	for (i = 0; i &lt; I40E_GL_PRIV_FLAGS_STR_LEN; i++)</div><div class='del'>-		ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-				i40e_gl_gstrings_priv_flags[i].flag_string);</div><div class='add'>+		ethtool_puts(&amp;p, i40e_gl_gstrings_priv_flags[i].flag_string);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void i40e_get_strings(struct net_device *netdev, u32 stringset,</div><div class='hunk'>@@ -2548,7 +2554,7 @@ static int i40e_get_ts_info(struct net_device *dev,</div><div class='ctx'> 	struct i40e_pf *pf = i40e_netdev_to_pf(dev);</div><div class='ctx'> </div><div class='ctx'> 	/* only report HW timestamping if PTP is enabled */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP))</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return ethtool_op_get_ts_info(dev, info);</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |</div><div class='hunk'>@@ -2570,7 +2576,7 @@ static int i40e_get_ts_info(struct net_device *dev,</div><div class='ctx'> 			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |</div><div class='ctx'> 			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_PTP_L4_CAPABLE)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_PTP_L4, pf-&gt;hw.caps))</div><div class='ctx'> 		info-&gt;rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |</div><div class='ctx'> 				    BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |</div><div class='ctx'> 				    BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |</div><div class='hunk'>@@ -2819,10 +2825,10 @@ static int i40e_set_phys_id(struct net_device *netdev,</div><div class='ctx'> </div><div class='ctx'> 	switch (state) {</div><div class='ctx'> 	case ETHTOOL_ID_ACTIVE:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PHY_CONTROLS_LEDS)) {</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf-&gt;hw.caps)) {</div><div class='ctx'> 			pf-&gt;led_status = i40e_led_get(hw);</div><div class='ctx'> 		} else {</div><div class='del'>-			if (!(hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))</div><div class='add'>+			if (!test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps))</div><div class='ctx'> 				i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL,</div><div class='ctx'> 						      NULL);</div><div class='ctx'> 			ret = i40e_led_get_phy(hw, &amp;temp_status,</div><div class='hunk'>@@ -2831,25 +2837,25 @@ static int i40e_set_phys_id(struct net_device *netdev,</div><div class='ctx'> 		}</div><div class='ctx'> 		return blink_freq;</div><div class='ctx'> 	case ETHTOOL_ID_ON:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PHY_CONTROLS_LEDS))</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf-&gt;hw.caps))</div><div class='ctx'> 			i40e_led_set(hw, 0xf, false);</div><div class='ctx'> 		else</div><div class='ctx'> 			ret = i40e_led_set_phy(hw, true, pf-&gt;led_status, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETHTOOL_ID_OFF:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PHY_CONTROLS_LEDS))</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf-&gt;hw.caps))</div><div class='ctx'> 			i40e_led_set(hw, 0x0, false);</div><div class='ctx'> 		else</div><div class='ctx'> 			ret = i40e_led_set_phy(hw, false, pf-&gt;led_status, 0);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETHTOOL_ID_INACTIVE:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PHY_CONTROLS_LEDS)) {</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf-&gt;hw.caps)) {</div><div class='ctx'> 			i40e_led_set(hw, pf-&gt;led_status, false);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			ret = i40e_led_set_phy(hw, false, pf-&gt;led_status,</div><div class='ctx'> 					       (pf-&gt;phy_led_val |</div><div class='ctx'> 					       I40E_PHY_LED_MODE_ORIG));</div><div class='del'>-			if (!(hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))</div><div class='add'>+			if (!test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps))</div><div class='ctx'> 				i40e_aq_set_phy_debug(hw, 0, NULL);</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2886,7 +2892,6 @@ static int __i40e_get_coalesce(struct net_device *netdev,</div><div class='ctx'> 	struct i40e_vsi *vsi = np-&gt;vsi;</div><div class='ctx'> </div><div class='ctx'> 	ec-&gt;tx_max_coalesced_frames_irq = vsi-&gt;work_limit;</div><div class='del'>-	ec-&gt;rx_max_coalesced_frames_irq = vsi-&gt;work_limit;</div><div class='ctx'> </div><div class='ctx'> 	/* rx and tx usecs has per queue value. If user doesn't specify the</div><div class='ctx'> 	 * queue, return queue 0's value to represent.</div><div class='hunk'>@@ -3020,7 +3025,7 @@ static int __i40e_set_coalesce(struct net_device *netdev,</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (ec-&gt;tx_max_coalesced_frames_irq || ec-&gt;rx_max_coalesced_frames_irq)</div><div class='add'>+	if (ec-&gt;tx_max_coalesced_frames_irq)</div><div class='ctx'> 		vsi-&gt;work_limit = ec-&gt;tx_max_coalesced_frames_irq;</div><div class='ctx'> </div><div class='ctx'> 	if (queue &lt; 0) {</div><div class='hunk'>@@ -3278,7 +3283,7 @@ static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,</div><div class='ctx'> 	} else if (valid) {</div><div class='ctx'> 		data-&gt;flex_word = value &amp; I40E_USERDEF_FLEX_WORD;</div><div class='ctx'> 		data-&gt;flex_offset =</div><div class='del'>-			(value &amp; I40E_USERDEF_FLEX_OFFSET) &gt;&gt; 16;</div><div class='add'>+			FIELD_GET(I40E_USERDEF_FLEX_OFFSET, value);</div><div class='ctx'> 		data-&gt;flex_filter = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3628,7 +3633,7 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)</div><div class='ctx'> </div><div class='ctx'> 	bitmap_zero(flow_pctypes, FLOW_PCTYPES_SIZE);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		dev_err(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			"Change of RSS hash input set is not supported when MFP mode is enabled\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='hunk'>@@ -3644,19 +3649,22 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 	switch (nfc-&gt;flow_type) {</div><div class='ctx'> 	case TCP_V4_FLOW:</div><div class='ctx'> 		set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, flow_pctypes);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,</div><div class='add'>+			     pf-&gt;hw.caps))</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK,</div><div class='ctx'> 				flow_pctypes);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TCP_V6_FLOW:</div><div class='ctx'> 		set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, flow_pctypes);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,</div><div class='add'>+			     pf-&gt;hw.caps))</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK,</div><div class='ctx'> 				flow_pctypes);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case UDP_V4_FLOW:</div><div class='ctx'> 		set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, flow_pctypes);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) {</div><div class='add'>+		if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,</div><div class='add'>+			     pf-&gt;hw.caps)) {</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP,</div><div class='ctx'> 				flow_pctypes);</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP,</div><div class='hunk'>@@ -3666,7 +3674,8 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case UDP_V6_FLOW:</div><div class='ctx'> 		set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, flow_pctypes);</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) {</div><div class='add'>+		if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,</div><div class='add'>+			     pf-&gt;hw.caps)) {</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP,</div><div class='ctx'> 				flow_pctypes);</div><div class='ctx'> 			set_bit(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP,</div><div class='hunk'>@@ -4644,7 +4653,7 @@ static int i40e_check_fdir_input_set(struct i40e_vsi *vsi,</div><div class='ctx'> 	 * main port cannot change them when in MFP mode as this would impact</div><div class='ctx'> 	 * any filters on the other ports.</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		netif_err(pf, drv, vsi-&gt;netdev, "Cannot change Flow Director input sets while MFP is enabled\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4804,7 +4813,7 @@ static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	pf = vsi-&gt;back;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(__I40E_FD_SB_AUTO_DISABLED, pf-&gt;state))</div><div class='hunk'>@@ -5001,7 +5010,7 @@ static void i40e_get_channels(struct net_device *dev,</div><div class='ctx'> 	ch-&gt;max_combined = i40e_max_channels(vsi);</div><div class='ctx'> </div><div class='ctx'> 	/* report info for other vector */</div><div class='del'>-	ch-&gt;other_count = (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) ? 1 : 0;</div><div class='add'>+	ch-&gt;other_count = test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) ? 1 : 0;</div><div class='ctx'> 	ch-&gt;max_other = ch-&gt;other_count;</div><div class='ctx'> </div><div class='ctx'> 	/* Note: This code assumes DCB is disabled for now. */</div><div class='hunk'>@@ -5044,7 +5053,7 @@ static int i40e_set_channels(struct net_device *dev,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* verify other_count has not changed */</div><div class='del'>-	if (ch-&gt;other_count != ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) ? 1 : 0))</div><div class='add'>+	if (ch-&gt;other_count != (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) ? 1 : 0))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* verify the number of channels does not exceed hardware limits */</div><div class='hunk'>@@ -5109,15 +5118,13 @@ static u32 i40e_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> /**</div><div class='ctx'>  * i40e_get_rxfh - get the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='ctx'>  *</div><div class='ctx'>  * Reads the indirection table directly from the hardware. Returns 0 on</div><div class='ctx'>  * success.</div><div class='ctx'>  **/</div><div class='del'>-static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int i40e_get_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_netdev_priv *np = netdev_priv(netdev);</div><div class='ctx'> 	struct i40e_vsi *vsi = np-&gt;vsi;</div><div class='hunk'>@@ -5125,13 +5132,12 @@ static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	seed = key;</div><div class='add'>+	seed = rxfh-&gt;key;</div><div class='ctx'> 	lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);</div><div class='ctx'> 	if (!lut)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -5139,7 +5145,7 @@ static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	for (i = 0; i &lt; I40E_HLUT_ARRAY_SIZE; i++)</div><div class='del'>-		indir[i] = (u32)(lut[i]);</div><div class='add'>+		rxfh-&gt;indir[i] = (u32)(lut[i]);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	kfree(lut);</div><div class='hunk'>@@ -5150,15 +5156,15 @@ out:</div><div class='ctx'> /**</div><div class='ctx'>  * i40e_set_rxfh - set the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function to use</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='add'>+ * @extack: extended ACK from the Netlink message</div><div class='ctx'>  *</div><div class='ctx'>  * Returns -EINVAL if the table specifies an invalid queue id, otherwise</div><div class='ctx'>  * returns 0 after programming the table.</div><div class='ctx'>  **/</div><div class='del'>-static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int i40e_set_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_netdev_priv *np = netdev_priv(netdev);</div><div class='ctx'> 	struct i40e_vsi *vsi = np-&gt;vsi;</div><div class='hunk'>@@ -5166,17 +5172,18 @@ static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	u8 *seed = NULL;</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='ctx'> 		if (!vsi-&gt;rss_hkey_user) {</div><div class='ctx'> 			vsi-&gt;rss_hkey_user = kzalloc(I40E_HKEY_ARRAY_SIZE,</div><div class='ctx'> 						     GFP_KERNEL);</div><div class='ctx'> 			if (!vsi-&gt;rss_hkey_user)</div><div class='ctx'> 				return -ENOMEM;</div><div class='ctx'> 		}</div><div class='del'>-		memcpy(vsi-&gt;rss_hkey_user, key, I40E_HKEY_ARRAY_SIZE);</div><div class='add'>+		memcpy(vsi-&gt;rss_hkey_user, rxfh-&gt;key, I40E_HKEY_ARRAY_SIZE);</div><div class='ctx'> 		seed = vsi-&gt;rss_hkey_user;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (!vsi-&gt;rss_lut_user) {</div><div class='hunk'>@@ -5186,9 +5193,9 @@ static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Each 32 bits pointed by 'indir' is stored with a lut entry */</div><div class='del'>-	if (indir)</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='ctx'> 		for (i = 0; i &lt; I40E_HLUT_ARRAY_SIZE; i++)</div><div class='del'>-			vsi-&gt;rss_lut_user[i] = (u8)(indir[i]);</div><div class='add'>+			vsi-&gt;rss_lut_user[i] = (u8)(rxfh-&gt;indir[i]);</div><div class='ctx'> 	else</div><div class='ctx'> 		i40e_fill_rss_lut(pf, vsi-&gt;rss_lut_user, I40E_HLUT_ARRAY_SIZE,</div><div class='ctx'> 				  vsi-&gt;rss_size);</div><div class='hunk'>@@ -5215,11 +5222,11 @@ static u32 i40e_get_priv_flags(struct net_device *dev)</div><div class='ctx'> 	u32 i, j, ret_flags = 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; I40E_PRIV_FLAGS_STR_LEN; i++) {</div><div class='del'>-		const struct i40e_priv_flags *priv_flags;</div><div class='add'>+		const struct i40e_priv_flags *priv_flag;</div><div class='ctx'> </div><div class='del'>-		priv_flags = &amp;i40e_gstrings_priv_flags[i];</div><div class='add'>+		priv_flag = &amp;i40e_gstrings_priv_flags[i];</div><div class='ctx'> </div><div class='del'>-		if (priv_flags-&gt;flag &amp; pf-&gt;flags)</div><div class='add'>+		if (test_bit(priv_flag-&gt;bitno, pf-&gt;flags))</div><div class='ctx'> 			ret_flags |= BIT(i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5227,11 +5234,11 @@ static u32 i40e_get_priv_flags(struct net_device *dev)</div><div class='ctx'> 		return ret_flags;</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; I40E_GL_PRIV_FLAGS_STR_LEN; j++) {</div><div class='del'>-		const struct i40e_priv_flags *priv_flags;</div><div class='add'>+		const struct i40e_priv_flags *priv_flag;</div><div class='ctx'> </div><div class='del'>-		priv_flags = &amp;i40e_gl_gstrings_priv_flags[j];</div><div class='add'>+		priv_flag = &amp;i40e_gl_gstrings_priv_flags[j];</div><div class='ctx'> </div><div class='del'>-		if (priv_flags-&gt;flag &amp; pf-&gt;flags)</div><div class='add'>+		if (test_bit(priv_flag-&gt;bitno, pf-&gt;flags))</div><div class='ctx'> 			ret_flags |= BIT(i + j);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5245,8 +5252,10 @@ static u32 i40e_get_priv_flags(struct net_device *dev)</div><div class='ctx'>  **/</div><div class='ctx'> static int i40e_set_priv_flags(struct net_device *dev, u32 flags)</div><div class='ctx'> {</div><div class='add'>+	DECLARE_BITMAP(changed_flags, I40E_PF_FLAGS_NBITS);</div><div class='add'>+	DECLARE_BITMAP(orig_flags, I40E_PF_FLAGS_NBITS);</div><div class='add'>+	DECLARE_BITMAP(new_flags, I40E_PF_FLAGS_NBITS);</div><div class='ctx'> 	struct i40e_netdev_priv *np = netdev_priv(dev);</div><div class='del'>-	u64 orig_flags, new_flags, changed_flags;</div><div class='ctx'> 	enum i40e_admin_queue_err adq_err;</div><div class='ctx'> 	struct i40e_vsi *vsi = np-&gt;vsi;</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='hunk'>@@ -5254,51 +5263,57 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)</div><div class='ctx'> 	int status;</div><div class='ctx'> 	u32 i, j;</div><div class='ctx'> </div><div class='del'>-	orig_flags = READ_ONCE(pf-&gt;flags);</div><div class='del'>-	new_flags = orig_flags;</div><div class='add'>+	bitmap_copy(orig_flags, pf-&gt;flags, I40E_PF_FLAGS_NBITS);</div><div class='add'>+	bitmap_copy(new_flags, pf-&gt;flags, I40E_PF_FLAGS_NBITS);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; I40E_PRIV_FLAGS_STR_LEN; i++) {</div><div class='del'>-		const struct i40e_priv_flags *priv_flags;</div><div class='del'>-</div><div class='del'>-		priv_flags = &amp;i40e_gstrings_priv_flags[i];</div><div class='add'>+		const struct i40e_priv_flags *priv_flag;</div><div class='add'>+		bool new_val;</div><div class='ctx'> </div><div class='del'>-		if (flags &amp; BIT(i))</div><div class='del'>-			new_flags |= priv_flags-&gt;flag;</div><div class='del'>-		else</div><div class='del'>-			new_flags &amp;= ~(priv_flags-&gt;flag);</div><div class='add'>+		priv_flag = &amp;i40e_gstrings_priv_flags[i];</div><div class='add'>+		new_val = (flags &amp; BIT(i)) ? true : false;</div><div class='ctx'> </div><div class='ctx'> 		/* If this is a read-only flag, it can't be changed */</div><div class='del'>-		if (priv_flags-&gt;read_only &amp;&amp;</div><div class='del'>-		    ((orig_flags ^ new_flags) &amp; ~BIT(i)))</div><div class='add'>+		if (priv_flag-&gt;read_only &amp;&amp;</div><div class='add'>+		    test_bit(priv_flag-&gt;bitno, orig_flags) != new_val)</div><div class='ctx'> 			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (new_val)</div><div class='add'>+			set_bit(priv_flag-&gt;bitno, new_flags);</div><div class='add'>+		else</div><div class='add'>+			clear_bit(priv_flag-&gt;bitno, new_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pf-&gt;hw.pf_id != 0)</div><div class='ctx'> 		goto flags_complete;</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; I40E_GL_PRIV_FLAGS_STR_LEN; j++) {</div><div class='del'>-		const struct i40e_priv_flags *priv_flags;</div><div class='add'>+		const struct i40e_priv_flags *priv_flag;</div><div class='add'>+		bool new_val;</div><div class='ctx'> </div><div class='del'>-		priv_flags = &amp;i40e_gl_gstrings_priv_flags[j];</div><div class='del'>-</div><div class='del'>-		if (flags &amp; BIT(i + j))</div><div class='del'>-			new_flags |= priv_flags-&gt;flag;</div><div class='del'>-		else</div><div class='del'>-			new_flags &amp;= ~(priv_flags-&gt;flag);</div><div class='add'>+		priv_flag = &amp;i40e_gl_gstrings_priv_flags[j];</div><div class='add'>+		new_val = (flags &amp; BIT(i + j)) ? true : false;</div><div class='ctx'> </div><div class='ctx'> 		/* If this is a read-only flag, it can't be changed */</div><div class='del'>-		if (priv_flags-&gt;read_only &amp;&amp;</div><div class='del'>-		    ((orig_flags ^ new_flags) &amp; ~BIT(i)))</div><div class='add'>+		if (priv_flag-&gt;read_only &amp;&amp;</div><div class='add'>+		    test_bit(priv_flag-&gt;bitno, orig_flags) != new_val)</div><div class='ctx'> 			return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		if (new_val)</div><div class='add'>+			set_bit(priv_flag-&gt;bitno, new_flags);</div><div class='add'>+		else</div><div class='add'>+			clear_bit(priv_flag-&gt;bitno, new_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> flags_complete:</div><div class='del'>-	changed_flags = orig_flags ^ new_flags;</div><div class='add'>+	bitmap_xor(changed_flags, pf-&gt;flags, orig_flags, I40E_PF_FLAGS_NBITS);</div><div class='ctx'> </div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_DISABLE_FW_LLDP)</div><div class='add'>+	if (test_bit(I40E_FLAG_FW_LLDP_DIS, changed_flags))</div><div class='ctx'> 		reset_needed = I40E_PF_RESET_AND_REBUILD_FLAG;</div><div class='del'>-	if (changed_flags &amp; (I40E_FLAG_VEB_STATS_ENABLED |</div><div class='del'>-	    I40E_FLAG_LEGACY_RX | I40E_FLAG_SOURCE_PRUNING_DISABLED))</div><div class='add'>+</div><div class='add'>+	if (test_bit(I40E_FLAG_VEB_STATS_ENA, changed_flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_LEGACY_RX_ENA, changed_flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_SOURCE_PRUNING_DIS, changed_flags))</div><div class='ctx'> 		reset_needed = BIT(__I40E_PF_RESET_REQUESTED);</div><div class='ctx'> </div><div class='ctx'> 	/* Before we finalize any flag changes, we need to perform some</div><div class='hunk'>@@ -5306,8 +5321,8 @@ flags_complete:</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/* ATR eviction is not supported on all devices */</div><div class='del'>-	if ((new_flags &amp; I40E_FLAG_HW_ATR_EVICT_ENABLED) &amp;&amp;</div><div class='del'>-	    !(pf-&gt;hw_features &amp; I40E_HW_ATR_EVICT_CAPABLE))</div><div class='add'>+	if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, new_flags) &amp;&amp;</div><div class='add'>+	    !test_bit(I40E_HW_CAP_ATR_EVICT, pf-&gt;hw.caps))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/* If the driver detected FW LLDP was disabled on init, this flag could</div><div class='hunk'>@@ -5318,15 +5333,14 @@ flags_complete:</div><div class='ctx'> 	 * disable LLDP, however we _must_ not allow the user to enable/disable</div><div class='ctx'> 	 * LLDP with this flag on unsupported FW versions.</div><div class='ctx'> 	 */</div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_DISABLE_FW_LLDP) {</div><div class='del'>-		if (!(pf-&gt;hw.flags &amp; I40E_HW_FLAG_FW_LLDP_STOPPABLE)) {</div><div class='del'>-			dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='del'>-				 "Device does not support changing FW LLDP\n");</div><div class='del'>-			return -EOPNOTSUPP;</div><div class='del'>-		}</div><div class='add'>+	if (test_bit(I40E_FLAG_FW_LLDP_DIS, changed_flags) &amp;&amp;</div><div class='add'>+	    !test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, pf-&gt;hw.caps)) {</div><div class='add'>+		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='add'>+			 "Device does not support changing FW LLDP\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_RS_FEC &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_RS_FEC, changed_flags) &amp;&amp;</div><div class='ctx'> 	    pf-&gt;hw.device_id != I40E_DEV_ID_25G_SFP28 &amp;&amp;</div><div class='ctx'> 	    pf-&gt;hw.device_id != I40E_DEV_ID_25G_B) {</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -5334,7 +5348,7 @@ flags_complete:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_BASE_R_FEC &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_BASE_R_FEC, changed_flags) &amp;&amp;</div><div class='ctx'> 	    pf-&gt;hw.device_id != I40E_DEV_ID_25G_SFP28 &amp;&amp;</div><div class='ctx'> 	    pf-&gt;hw.device_id != I40E_DEV_ID_25G_B &amp;&amp;</div><div class='ctx'> 	    pf-&gt;hw.device_id != I40E_DEV_ID_KX_X722) {</div><div class='hunk'>@@ -5349,17 +5363,17 @@ flags_complete:</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/* Flush current ATR settings if ATR was disabled */</div><div class='del'>-	if ((changed_flags &amp; I40E_FLAG_FD_ATR_ENABLED) &amp;&amp;</div><div class='del'>-	    !(new_flags &amp; I40E_FLAG_FD_ATR_ENABLED)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_ATR_ENA, changed_flags) &amp;&amp;</div><div class='add'>+	    !test_bit(I40E_FLAG_FD_ATR_ENA, new_flags)) {</div><div class='ctx'> 		set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state);</div><div class='ctx'> 		set_bit(__I40E_FD_FLUSH_REQUESTED, pf-&gt;state);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_TRUE_PROMISC_SUPPORT) {</div><div class='add'>+	if (test_bit(I40E_FLAG_TRUE_PROMISC_ENA, changed_flags)) {</div><div class='ctx'> 		u16 sw_flags = 0, valid_flags = 0;</div><div class='ctx'> 		int ret;</div><div class='ctx'> </div><div class='del'>-		if (!(new_flags &amp; I40E_FLAG_TRUE_PROMISC_SUPPORT))</div><div class='add'>+		if (!test_bit(I40E_FLAG_TRUE_PROMISC_ENA, new_flags))</div><div class='ctx'> 			sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;</div><div class='ctx'> 		valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;</div><div class='ctx'> 		ret = i40e_aq_set_switch_config(&amp;pf-&gt;hw, sw_flags, valid_flags,</div><div class='hunk'>@@ -5374,17 +5388,17 @@ flags_complete:</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((changed_flags &amp; I40E_FLAG_RS_FEC) ||</div><div class='del'>-	    (changed_flags &amp; I40E_FLAG_BASE_R_FEC)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_RS_FEC, changed_flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_BASE_R_FEC, changed_flags)) {</div><div class='ctx'> 		u8 fec_cfg = 0;</div><div class='ctx'> </div><div class='del'>-		if (new_flags &amp; I40E_FLAG_RS_FEC &amp;&amp;</div><div class='del'>-		    new_flags &amp; I40E_FLAG_BASE_R_FEC) {</div><div class='add'>+		if (test_bit(I40E_FLAG_RS_FEC, new_flags) &amp;&amp;</div><div class='add'>+		    test_bit(I40E_FLAG_BASE_R_FEC, new_flags)) {</div><div class='ctx'> 			fec_cfg = I40E_AQ_SET_FEC_AUTO;</div><div class='del'>-		} else if (new_flags &amp; I40E_FLAG_RS_FEC) {</div><div class='add'>+		} else if (test_bit(I40E_FLAG_RS_FEC, new_flags)) {</div><div class='ctx'> 			fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |</div><div class='ctx'> 				   I40E_AQ_SET_FEC_ABILITY_RS);</div><div class='del'>-		} else if (new_flags &amp; I40E_FLAG_BASE_R_FEC) {</div><div class='add'>+		} else if (test_bit(I40E_FLAG_BASE_R_FEC, new_flags)) {</div><div class='ctx'> 			fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |</div><div class='ctx'> 				   I40E_AQ_SET_FEC_ABILITY_KR);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -5392,35 +5406,35 @@ flags_complete:</div><div class='ctx'> 			dev_warn(&amp;pf-&gt;pdev-&gt;dev, "Cannot change FEC config\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((changed_flags &amp; I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &amp;&amp;</div><div class='del'>-	    (orig_flags &amp; I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, changed_flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, orig_flags)) {</div><div class='ctx'> 		dev_err(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			"Setting link-down-on-close not supported on this port (because total-port-shutdown is enabled)\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((changed_flags &amp; I40E_FLAG_VF_VLAN_PRUNING) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_VF_VLAN_PRUNING_ENA, changed_flags) &amp;&amp;</div><div class='ctx'> 	    pf-&gt;num_alloc_vfs) {</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			 "Changing vf-vlan-pruning flag while VF(s) are active is not supported\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((changed_flags &amp; I40E_FLAG_LEGACY_RX) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_LEGACY_RX_ENA, changed_flags) &amp;&amp;</div><div class='ctx'> 	    I40E_2K_TOO_SMALL_WITH_PADDING) {</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			 "2k Rx buffer is too small to fit standard MTU and skb_shared_info\n");</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((changed_flags &amp; new_flags &amp;</div><div class='del'>-	     I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &amp;&amp;</div><div class='del'>-	    (new_flags &amp; I40E_FLAG_MFP_ENABLED))</div><div class='add'>+	if (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, changed_flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, new_flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_MFP_ENA, new_flags))</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			 "Turning on link-down-on-close flag may affect other partitions\n");</div><div class='ctx'> </div><div class='del'>-	if (changed_flags &amp; I40E_FLAG_DISABLE_FW_LLDP) {</div><div class='del'>-		if (new_flags &amp; I40E_FLAG_DISABLE_FW_LLDP) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FW_LLDP_DIS, changed_flags)) {</div><div class='add'>+		if (test_bit(I40E_FLAG_FW_LLDP_DIS, new_flags)) {</div><div class='ctx'> #ifdef CONFIG_I40E_DCB</div><div class='ctx'> 			i40e_dcb_sw_default_config(pf);</div><div class='ctx'> #endif /* CONFIG_I40E_DCB */</div><div class='hunk'>@@ -5461,7 +5475,7 @@ flags_complete:</div><div class='ctx'> 	 * initialization or (b) while holding the RTNL lock, we don't need</div><div class='ctx'> 	 * anything fancy here.</div><div class='ctx'> 	 */</div><div class='del'>-	pf-&gt;flags = new_flags;</div><div class='add'>+	bitmap_copy(pf-&gt;flags, new_flags, I40E_PF_FLAGS_NBITS);</div><div class='ctx'> </div><div class='ctx'> 	/* Issue reset to cause things to take effect, as additional bits</div><div class='ctx'> 	 * are added we will need to create a mask of bits requiring reset</div><div class='hunk'>@@ -5491,7 +5505,7 @@ static int i40e_get_module_info(struct net_device *netdev,</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='ctx'> 	/* Check if firmware supports reading module EEPROM. */</div><div class='del'>-	if (!(hw-&gt;flags &amp; I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw-&gt;caps)) {</div><div class='ctx'> 		netdev_err(vsi-&gt;netdev, "Module EEPROM memory read not supported. Please update the NVM image.\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -5571,8 +5585,8 @@ static int i40e_get_module_info(struct net_device *netdev,</div><div class='ctx'> 		modinfo-&gt;eeprom_len = I40E_MODULE_QSFP_MAX_LEN;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='del'>-		netdev_err(vsi-&gt;netdev, "Module type unrecognized\n");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		netdev_dbg(vsi-&gt;netdev, "SFP module type unrecognized or no SFP connector used.\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -5768,7 +5782,7 @@ static const struct ethtool_ops i40e_ethtool_recovery_mode_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops i40e_ethtool_ops = {</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='del'>-				     ETHTOOL_COALESCE_MAX_FRAMES_IRQ |</div><div class='add'>+				     ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE |</div><div class='ctx'> 				     ETHTOOL_COALESCE_RX_USECS_HIGH |</div><div class='ctx'> 				     ETHTOOL_COALESCE_TX_USECS_HIGH,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c<br/>index f7a332e51524..ae8f9f135725 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_main.c</a></div><div class='hunk'>@@ -107,12 +107,18 @@ static struct workqueue_struct *i40e_wq;</div><div class='ctx'> static void netdev_hw_addr_refcnt(struct i40e_mac_filter *f,</div><div class='ctx'> 				  struct net_device *netdev, int delta)</div><div class='ctx'> {</div><div class='add'>+	struct netdev_hw_addr_list *ha_list;</div><div class='ctx'> 	struct netdev_hw_addr *ha;</div><div class='ctx'> </div><div class='ctx'> 	if (!f || !netdev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	netdev_for_each_mc_addr(ha, netdev) {</div><div class='add'>+	if (is_unicast_ether_addr(f-&gt;macaddr) || is_link_local_ether_addr(f-&gt;macaddr))</div><div class='add'>+		ha_list = &amp;netdev-&gt;uc;</div><div class='add'>+	else</div><div class='add'>+		ha_list = &amp;netdev-&gt;mc;</div><div class='add'>+</div><div class='add'>+	netdev_hw_addr_list_for_each(ha, ha_list) {</div><div class='ctx'> 		if (ether_addr_equal(ha-&gt;addr, f-&gt;macaddr)) {</div><div class='ctx'> 			ha-&gt;refcount += delta;</div><div class='ctx'> 			if (ha-&gt;refcount &lt;= 0)</div><div class='hunk'>@@ -371,7 +377,7 @@ static void i40e_tx_timeout(struct net_device *netdev, unsigned int txqueue)</div><div class='ctx'> 	if (tx_ring) {</div><div class='ctx'> 		head = i40e_get_head(tx_ring);</div><div class='ctx'> 		/* Read interrupt register */</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+		if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 			val = rd32(&amp;pf-&gt;hw,</div><div class='ctx'> 			     I40E_PFINT_DYN_CTLN(tx_ring-&gt;q_vector-&gt;v_idx +</div><div class='ctx'> 						tx_ring-&gt;vsi-&gt;base_vector - 1));</div><div class='hunk'>@@ -1197,11 +1203,9 @@ static void i40e_update_pf_stats(struct i40e_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, I40E_PRTPM_EEE_STAT);</div><div class='ctx'> 	nsd-&gt;tx_lpi_status =</div><div class='del'>-		       (val &amp; I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) &gt;&gt;</div><div class='del'>-			I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;</div><div class='add'>+		       FIELD_GET(I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK, val);</div><div class='ctx'> 	nsd-&gt;rx_lpi_status =</div><div class='del'>-		       (val &amp; I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) &gt;&gt;</div><div class='del'>-			I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;</div><div class='add'>+		       FIELD_GET(I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK, val);</div><div class='ctx'> 	i40e_stat_update32(hw, I40E_PRTPM_TLPIC,</div><div class='ctx'> 			   pf-&gt;stat_offsets_loaded,</div><div class='ctx'> 			   &amp;osd-&gt;tx_lpi_count, &amp;nsd-&gt;tx_lpi_count);</div><div class='hunk'>@@ -1209,13 +1213,13 @@ static void i40e_update_pf_stats(struct i40e_pf *pf)</div><div class='ctx'> 			   pf-&gt;stat_offsets_loaded,</div><div class='ctx'> 			   &amp;osd-&gt;rx_lpi_count, &amp;nsd-&gt;rx_lpi_count);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    !test_bit(__I40E_FD_SB_AUTO_DISABLED, pf-&gt;state))</div><div class='ctx'> 		nsd-&gt;fd_sb_status = true;</div><div class='ctx'> 	else</div><div class='ctx'> 		nsd-&gt;fd_sb_status = false;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    !test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state))</div><div class='ctx'> 		nsd-&gt;fd_atr_status = true;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -1485,7 +1489,7 @@ static s16 i40e_get_vf_new_vlan(struct i40e_vsi *vsi,</div><div class='ctx'> 		return pvid;</div><div class='ctx'> </div><div class='ctx'> 	is_any = (trusted ||</div><div class='del'>-		  !(pf-&gt;flags &amp; I40E_FLAG_VF_VLAN_PRUNING));</div><div class='add'>+		  !test_bit(I40E_FLAG_VF_VLAN_PRUNING_ENA, pf-&gt;flags));</div><div class='ctx'> </div><div class='ctx'> 	if ((vlan_filters &amp;&amp; f-&gt;vlan == I40E_VLAN_ANY) ||</div><div class='ctx'> 	    (!is_any &amp;&amp; !vlan_filters &amp;&amp; f-&gt;vlan == I40E_VLAN_ANY) ||</div><div class='hunk'>@@ -1890,7 +1894,7 @@ static int i40e_vsi_config_rss(struct i40e_vsi *vsi)</div><div class='ctx'> 	u8 *lut;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_RSS_AQ, pf-&gt;hw.caps))</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	if (!vsi-&gt;rss_size)</div><div class='ctx'> 		vsi-&gt;rss_size = min_t(int, pf-&gt;alloc_rss_size,</div><div class='hunk'>@@ -2045,7 +2049,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (vsi-&gt;req_queue_pairs &gt; 0)</div><div class='ctx'> 			vsi-&gt;num_queue_pairs = vsi-&gt;req_queue_pairs;</div><div class='del'>-		else if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+		else if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 			vsi-&gt;num_queue_pairs = pf-&gt;num_lan_msix;</div><div class='ctx'> 		else</div><div class='ctx'> 			vsi-&gt;num_queue_pairs = 1;</div><div class='hunk'>@@ -2058,7 +2062,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,</div><div class='ctx'> 	else</div><div class='ctx'> 		num_tc_qps = vsi-&gt;alloc_queue_pairs;</div><div class='ctx'> </div><div class='del'>-	if (enabled_tc &amp;&amp; (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_DCB_ENABLED)) {</div><div class='add'>+	if (enabled_tc &amp;&amp; test_bit(I40E_FLAG_DCB_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		/* Find numtc from enabled TC bitmap */</div><div class='ctx'> 		for (i = 0, numtc = 0; i &lt; I40E_MAX_TRAFFIC_CLASS; i++) {</div><div class='ctx'> 			if (enabled_tc &amp; BIT(i)) /* TC is enabled */</div><div class='hunk'>@@ -2077,7 +2081,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,</div><div class='ctx'> 	vsi-&gt;tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;</div><div class='ctx'> </div><div class='ctx'> 	/* Do not allow use more TC queue pairs than MSI-X vectors exist */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		num_tc_qps = min_t(int, num_tc_qps, pf-&gt;num_lan_msix);</div><div class='ctx'> </div><div class='ctx'> 	/* Setup queue offset/count for all TCs for given VSI */</div><div class='hunk'>@@ -2089,8 +2093,10 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,</div><div class='ctx'> </div><div class='ctx'> 			switch (vsi-&gt;type) {</div><div class='ctx'> 			case I40E_VSI_MAIN:</div><div class='del'>-				if (!(pf-&gt;flags &amp; (I40E_FLAG_FD_SB_ENABLED |</div><div class='del'>-				    I40E_FLAG_FD_ATR_ENABLED)) ||</div><div class='add'>+				if ((!test_bit(I40E_FLAG_FD_SB_ENA,</div><div class='add'>+					       pf-&gt;flags) &amp;&amp;</div><div class='add'>+				     !test_bit(I40E_FLAG_FD_ATR_ENA,</div><div class='add'>+					       pf-&gt;flags)) ||</div><div class='ctx'> 				    vsi-&gt;tc_config.enabled_tc != 1) {</div><div class='ctx'> 					qcount = min_t(int, pf-&gt;alloc_rss_size,</div><div class='ctx'> 						       num_tc_qps);</div><div class='hunk'>@@ -2476,7 +2482,7 @@ static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)</div><div class='ctx'> </div><div class='ctx'> 	if (vsi-&gt;type == I40E_VSI_MAIN &amp;&amp;</div><div class='ctx'> 	    pf-&gt;lan_veb != I40E_NO_VEB &amp;&amp;</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED)) {</div><div class='add'>+	    !test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		/* set defport ON for Main VSI instead of true promisc</div><div class='ctx'> 		 * this way we will get all unicast/multicast and VLAN</div><div class='ctx'> 		 * promisc behavior but will not get VF or VMDq traffic</div><div class='hunk'>@@ -2907,7 +2913,7 @@ static void i40e_sync_filters_subtask(struct i40e_pf *pf)</div><div class='ctx'>  */</div><div class='ctx'> static u16 i40e_calculate_vsi_rx_buf_len(struct i40e_vsi *vsi)</div><div class='ctx'> {</div><div class='del'>-	if (!vsi-&gt;netdev || (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_LEGACY_RX))</div><div class='add'>+	if (!vsi-&gt;netdev || test_bit(I40E_FLAG_LEGACY_RX_ENA, vsi-&gt;back-&gt;flags))</div><div class='ctx'> 		return SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048);</div><div class='ctx'> </div><div class='ctx'> 	return PAGE_SIZE &lt; 8192 ? I40E_RXBUFFER_3072 : I40E_RXBUFFER_2048;</div><div class='hunk'>@@ -3462,8 +3468,8 @@ static int i40e_configure_tx_ring(struct i40e_ring *ring)</div><div class='ctx'> 		ring-&gt;xsk_pool = i40e_xsk_pool(ring);</div><div class='ctx'> </div><div class='ctx'> 	/* some ATR related tx ring init */</div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED) {</div><div class='del'>-		ring-&gt;atr_sample_rate = vsi-&gt;back-&gt;atr_sample_rate;</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_ATR_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='add'>+		ring-&gt;atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;</div><div class='ctx'> 		ring-&gt;atr_count = 0;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ring-&gt;atr_sample_rate = 0;</div><div class='hunk'>@@ -3478,9 +3484,11 @@ static int i40e_configure_tx_ring(struct i40e_ring *ring)</div><div class='ctx'> 	tx_ctx.new_context = 1;</div><div class='ctx'> 	tx_ctx.base = (ring-&gt;dma / 128);</div><div class='ctx'> 	tx_ctx.qlen = ring-&gt;count;</div><div class='del'>-	tx_ctx.fd_ena = !!(vsi-&gt;back-&gt;flags &amp; (I40E_FLAG_FD_SB_ENABLED |</div><div class='del'>-					       I40E_FLAG_FD_ATR_ENABLED));</div><div class='del'>-	tx_ctx.timesync_ena = !!(vsi-&gt;back-&gt;flags &amp; I40E_FLAG_PTP);</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, vsi-&gt;back-&gt;flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_FD_ATR_ENA, vsi-&gt;back-&gt;flags))</div><div class='add'>+		tx_ctx.fd_ena = 1;</div><div class='add'>+	if (test_bit(I40E_FLAG_PTP_ENA, vsi-&gt;back-&gt;flags))</div><div class='add'>+		tx_ctx.timesync_ena = 1;</div><div class='ctx'> 	/* FDIR VSI tx ring can still use RS bit and writebacks */</div><div class='ctx'> 	if (vsi-&gt;type != I40E_VSI_FDIR)</div><div class='ctx'> 		tx_ctx.head_wb_ena = 1;</div><div class='hunk'>@@ -3532,21 +3540,19 @@ static int i40e_configure_tx_ring(struct i40e_ring *ring)</div><div class='ctx'> 		else</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='del'>-		qtx_ctl |= (ring-&gt;ch-&gt;vsi_number &lt;&lt;</div><div class='del'>-			    I40E_QTX_CTL_VFVM_INDX_SHIFT) &amp;</div><div class='del'>-			    I40E_QTX_CTL_VFVM_INDX_MASK;</div><div class='add'>+		qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,</div><div class='add'>+				      ring-&gt;ch-&gt;vsi_number);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (vsi-&gt;type == I40E_VSI_VMDQ2) {</div><div class='ctx'> 			qtx_ctl = I40E_QTX_CTL_VM_QUEUE;</div><div class='del'>-			qtx_ctl |= ((vsi-&gt;id) &lt;&lt; I40E_QTX_CTL_VFVM_INDX_SHIFT) &amp;</div><div class='del'>-				    I40E_QTX_CTL_VFVM_INDX_MASK;</div><div class='add'>+			qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,</div><div class='add'>+					      vsi-&gt;id);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			qtx_ctl = I40E_QTX_CTL_PF_QUEUE;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	qtx_ctl |= ((hw-&gt;pf_id &lt;&lt; I40E_QTX_CTL_PF_INDX_SHIFT) &amp;</div><div class='del'>-		    I40E_QTX_CTL_PF_INDX_MASK);</div><div class='add'>+	qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw-&gt;pf_id);</div><div class='ctx'> 	wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);</div><div class='ctx'> 	i40e_flush(hw);</div><div class='ctx'> </div><div class='hunk'>@@ -3663,7 +3669,7 @@ static int i40e_configure_rx_ring(struct i40e_ring *ring)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* configure Rx buffer alignment */</div><div class='del'>-	if (!vsi-&gt;netdev || (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_LEGACY_RX)) {</div><div class='add'>+	if (!vsi-&gt;netdev || test_bit(I40E_FLAG_LEGACY_RX_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		if (I40E_2K_TOO_SMALL_WITH_PADDING) {</div><div class='ctx'> 			dev_info(&amp;vsi-&gt;back-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "2k Rx buffer is too small to fit standard MTU and skb_shared_info\n");</div><div class='hunk'>@@ -3761,7 +3767,7 @@ static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)</div><div class='ctx'> 	u16 qoffset, qcount;</div><div class='ctx'> 	int i, n;</div><div class='ctx'> </div><div class='del'>-	if (!(vsi-&gt;back-&gt;flags &amp; I40E_FLAG_DCB_ENABLED)) {</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		/* Reset the TC information */</div><div class='ctx'> 		for (i = 0; i &lt; vsi-&gt;num_queue_pairs; i++) {</div><div class='ctx'> 			rx_ring = vsi-&gt;rx_rings[i];</div><div class='hunk'>@@ -3828,7 +3834,7 @@ static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	struct hlist_node *node;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset FDir counters as we're replaying all existing filters */</div><div class='hunk'>@@ -3966,10 +3972,10 @@ static void i40e_enable_misc_int_causes(struct i40e_pf *pf)</div><div class='ctx'> 	      I40E_PFINT_ICR0_ENA_VFLR_MASK          |</div><div class='ctx'> 	      I40E_PFINT_ICR0_ENA_ADMINQ_MASK;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags))</div><div class='ctx'> 		val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_PTP)</div><div class='add'>+	if (test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;</div><div class='ctx'> </div><div class='ctx'> 	wr32(hw, I40E_PFINT_ICR0_ENA, val);</div><div class='hunk'>@@ -4205,7 +4211,7 @@ static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* disable each interrupt */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		for (i = vsi-&gt;base_vector;</div><div class='ctx'> 		     i &lt; (vsi-&gt;num_q_vectors + vsi-&gt;base_vector); i++)</div><div class='ctx'> 			wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);</div><div class='hunk'>@@ -4231,7 +4237,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		for (i = 0; i &lt; vsi-&gt;num_q_vectors; i++)</div><div class='ctx'> 			i40e_irq_dynamic_enable(vsi, i);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -4252,7 +4258,7 @@ static void i40e_free_misc_vector(struct i40e_pf *pf)</div><div class='ctx'> 	wr32(&amp;pf-&gt;hw, I40E_PFINT_ICR0_ENA, 0);</div><div class='ctx'> 	i40e_flush(&amp;pf-&gt;hw);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED &amp;&amp; pf-&gt;msix_entries) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags) &amp;&amp; pf-&gt;msix_entries) {</div><div class='ctx'> 		free_irq(pf-&gt;msix_entries[0].vector, pf);</div><div class='ctx'> 		clear_bit(__I40E_MISC_IRQ_REQUESTED, pf-&gt;state);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4287,7 +4293,7 @@ static irqreturn_t i40e_intr(int irq, void *data)</div><div class='ctx'> 	    (icr0 &amp; I40E_PFINT_ICR0_SWINT_MASK))</div><div class='ctx'> 		pf-&gt;sw_int_count++;</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    (icr0 &amp; I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {</div><div class='ctx'> 		ena_mask &amp;= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;</div><div class='ctx'> 		dev_dbg(&amp;pf-&gt;pdev-&gt;dev, "cleared PE_CRITERR\n");</div><div class='hunk'>@@ -4338,8 +4344,7 @@ static irqreturn_t i40e_intr(int irq, void *data)</div><div class='ctx'> 			set_bit(__I40E_RESET_INTR_RECEIVED, pf-&gt;state);</div><div class='ctx'> 		ena_mask &amp;= ~I40E_PFINT_ICR0_ENA_GRST_MASK;</div><div class='ctx'> 		val = rd32(hw, I40E_GLGEN_RSTAT);</div><div class='del'>-		val = (val &amp; I40E_GLGEN_RSTAT_RESET_TYPE_MASK)</div><div class='del'>-		       &gt;&gt; I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;</div><div class='add'>+		val = FIELD_GET(I40E_GLGEN_RSTAT_RESET_TYPE_MASK, val);</div><div class='ctx'> 		if (val == I40E_RESET_CORER) {</div><div class='ctx'> 			pf-&gt;corer_count++;</div><div class='ctx'> 		} else if (val == I40E_RESET_GLOBR) {</div><div class='hunk'>@@ -4480,7 +4485,7 @@ static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)</div><div class='ctx'> 	i += tx_ring-&gt;count;</div><div class='ctx'> 	tx_ring-&gt;next_to_clean = i;</div><div class='ctx'> </div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, vsi-&gt;back-&gt;flags))</div><div class='ctx'> 		i40e_irq_dynamic_enable(vsi, tx_ring-&gt;q_vector-&gt;v_idx);</div><div class='ctx'> </div><div class='ctx'> 	return budget &gt; 0;</div><div class='hunk'>@@ -4593,9 +4598,9 @@ static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		err = i40e_vsi_request_irq_msix(vsi, basename);</div><div class='del'>-	else if (pf-&gt;flags &amp; I40E_FLAG_MSI_ENABLED)</div><div class='add'>+	else if (test_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags))</div><div class='ctx'> 		err = request_irq(pf-&gt;pdev-&gt;irq, i40e_intr, 0,</div><div class='ctx'> 				  pf-&gt;int_name, pf);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -4627,7 +4632,7 @@ static void i40e_netpoll(struct net_device *netdev)</div><div class='ctx'> 	if (test_bit(__I40E_VSI_DOWN, vsi-&gt;state))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		for (i = 0; i &lt; vsi-&gt;num_q_vectors; i++)</div><div class='ctx'> 			i40e_msix_clean_rings(0, vsi-&gt;q_vectors[i]);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -4967,7 +4972,7 @@ static void i40e_vsi_free_irq(struct i40e_vsi *vsi)</div><div class='ctx'> 	u32 val, qp;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		if (!vsi-&gt;q_vectors)</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='hunk'>@@ -5001,8 +5006,8 @@ static void i40e_vsi_free_irq(struct i40e_vsi *vsi)</div><div class='ctx'> 			 * next_q field of the registers.</div><div class='ctx'> 			 */</div><div class='ctx'> 			val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));</div><div class='del'>-			qp = (val &amp; I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)</div><div class='del'>-				&gt;&gt; I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;</div><div class='add'>+			qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK,</div><div class='add'>+				       val);</div><div class='ctx'> 			val |= I40E_QUEUE_END_OF_LIST</div><div class='ctx'> 				&lt;&lt; I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;</div><div class='ctx'> 			wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);</div><div class='hunk'>@@ -5024,8 +5029,8 @@ static void i40e_vsi_free_irq(struct i40e_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 				val = rd32(hw, I40E_QINT_TQCTL(qp));</div><div class='ctx'> </div><div class='del'>-				next = (val &amp; I40E_QINT_TQCTL_NEXTQ_INDX_MASK)</div><div class='del'>-					&gt;&gt; I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;</div><div class='add'>+				next = FIELD_GET(I40E_QINT_TQCTL_NEXTQ_INDX_MASK,</div><div class='add'>+						 val);</div><div class='ctx'> </div><div class='ctx'> 				val &amp;= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK  |</div><div class='ctx'> 					 I40E_QINT_TQCTL_MSIX0_INDX_MASK |</div><div class='hunk'>@@ -5043,8 +5048,7 @@ static void i40e_vsi_free_irq(struct i40e_vsi *vsi)</div><div class='ctx'> 		free_irq(pf-&gt;pdev-&gt;irq, pf);</div><div class='ctx'> </div><div class='ctx'> 		val = rd32(hw, I40E_PFINT_LNKLST0);</div><div class='del'>-		qp = (val &amp; I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)</div><div class='del'>-			&gt;&gt; I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;</div><div class='add'>+		qp = FIELD_GET(I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK, val);</div><div class='ctx'> 		val |= I40E_QUEUE_END_OF_LIST</div><div class='ctx'> 			&lt;&lt; I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;</div><div class='ctx'> 		wr32(hw, I40E_PFINT_LNKLST0, val);</div><div class='hunk'>@@ -5129,16 +5133,17 @@ static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)</div><div class='ctx'> static void i40e_reset_interrupt_capability(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	/* If we're in Legacy mode, the interrupt was cleaned in vsi_close */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		pci_disable_msix(pf-&gt;pdev);</div><div class='ctx'> 		kfree(pf-&gt;msix_entries);</div><div class='ctx'> 		pf-&gt;msix_entries = NULL;</div><div class='ctx'> 		kfree(pf-&gt;irq_pile);</div><div class='ctx'> 		pf-&gt;irq_pile = NULL;</div><div class='del'>-	} else if (pf-&gt;flags &amp; I40E_FLAG_MSI_ENABLED) {</div><div class='add'>+	} else if (test_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		pci_disable_msi(pf-&gt;pdev);</div><div class='ctx'> 	}</div><div class='del'>-	pf-&gt;flags &amp;= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);</div><div class='add'>+	clear_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags);</div><div class='add'>+	clear_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -5478,11 +5483,11 @@ static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)</div><div class='ctx'> 		return pf-&gt;vsi[pf-&gt;lan_vsi]-&gt;mqprio_qopt.qopt.num_tc;</div><div class='ctx'> </div><div class='ctx'> 	/* If neither MQPRIO nor DCB is enabled, then always use single TC */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return 1;</div><div class='ctx'> </div><div class='ctx'> 	/* SFP mode will be enabled for all TCs on port */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return i40e_dcb_get_num_tc(dcbcfg);</div><div class='ctx'> </div><div class='ctx'> 	/* MFP mode return count of enabled TCs for this PF */</div><div class='hunk'>@@ -5512,11 +5517,11 @@ static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)</div><div class='ctx'> 	/* If neither MQPRIO nor DCB is enabled for this PF then just return</div><div class='ctx'> 	 * default TC</div><div class='ctx'> 	 */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return I40E_DEFAULT_TRAFFIC_CLASS;</div><div class='ctx'> </div><div class='ctx'> 	/* SFP mode we want PF to be enabled for all TCs */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return i40e_dcb_get_enabled_tc(&amp;pf-&gt;hw.local_dcbx_config);</div><div class='ctx'> </div><div class='ctx'> 	/* MFP enabled and iSCSI PF type */</div><div class='hunk'>@@ -5605,7 +5610,7 @@ static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,</div><div class='ctx'> 	/* There is no need to reset BW when mqprio mode is on.  */</div><div class='ctx'> 	if (i40e_is_tc_mqprio_enabled(pf))</div><div class='ctx'> 		return 0;</div><div class='del'>-	if (!vsi-&gt;mqprio_qopt.qopt.hw &amp;&amp; !(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED)) {</div><div class='add'>+	if (!vsi-&gt;mqprio_qopt.qopt.hw &amp;&amp; !test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		ret = i40e_set_bw_limit(vsi, vsi-&gt;seid, 0);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -5858,7 +5863,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)</div><div class='ctx'> 		}</div><div class='ctx'> 		vsi-&gt;reconfig_rss = false;</div><div class='ctx'> 	}</div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		ctxt.info.valid_sections |=</div><div class='ctx'> 				cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);</div><div class='ctx'> 		ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;</div><div class='hunk'>@@ -6271,7 +6276,7 @@ static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid,</div><div class='ctx'> 	if (ch-&gt;type == I40E_VSI_VMDQ2)</div><div class='ctx'> 		ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		ctxt.info.valid_sections |=</div><div class='ctx'> 		     cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);</div><div class='ctx'> 		ctxt.info.switch_id =</div><div class='hunk'>@@ -6576,8 +6581,8 @@ int i40e_create_queue_channel(struct i40e_vsi *vsi,</div><div class='ctx'> 	 * VSI to be added switch to VEB mode.</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+	if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags)) {</div><div class='add'>+		set_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 		if (vsi-&gt;type == I40E_VSI_MAIN) {</div><div class='ctx'> 			if (i40e_is_tc_mqprio_enabled(pf))</div><div class='hunk'>@@ -6988,9 +6993,9 @@ int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg)</div><div class='ctx'> 	if (need_reconfig) {</div><div class='ctx'> 		/* Enable DCB tagging only when more than one TC */</div><div class='ctx'> 		if (new_numtc &gt; 1)</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_DCB_ENABLED;</div><div class='add'>+			set_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		else</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 		set_bit(__I40E_PORT_SUSPENDED, pf-&gt;state);</div><div class='ctx'> 		/* Reconfiguration needed quiesce all VSIs */</div><div class='hunk'>@@ -7080,7 +7085,7 @@ out:</div><div class='ctx'> 			set_bit(__I40E_CLIENT_L2_CHANGE, pf-&gt;state);</div><div class='ctx'> 		}</div><div class='ctx'> 		/* registers are set, lets apply */</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_USE_SET_LLDP_MIB)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf-&gt;hw.caps))</div><div class='ctx'> 			ret = i40e_hw_set_dcb_config(pf, new_cfg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -7101,7 +7106,7 @@ int i40e_dcb_sw_default_config(struct i40e_pf *pf)</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_USE_SET_LLDP_MIB) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf-&gt;hw.caps)) {</div><div class='ctx'> 		/* Update the local cached instance with TC0 ETS */</div><div class='ctx'> 		memset(&amp;pf-&gt;tmp_cfg, 0, sizeof(struct i40e_dcbx_config));</div><div class='ctx'> 		pf-&gt;tmp_cfg.etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING;</div><div class='hunk'>@@ -7162,12 +7167,12 @@ static int i40e_init_pf_dcb(struct i40e_pf *pf)</div><div class='ctx'> 	/* Do not enable DCB for SW1 and SW2 images even if the FW is capable</div><div class='ctx'> 	 * Also do not enable DCBx if FW LLDP agent is disabled</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_NO_DCB_SUPPORT) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_NO_DCB_SUPPORT, pf-&gt;hw.caps)) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "DCB is not supported.\n");</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_DISABLE_FW_LLDP) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags)) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "FW LLDP is disabled, attempting SW DCB\n");</div><div class='ctx'> 		err = i40e_dcb_sw_default_config(pf);</div><div class='ctx'> 		if (err) {</div><div class='hunk'>@@ -7178,8 +7183,8 @@ static int i40e_init_pf_dcb(struct i40e_pf *pf)</div><div class='ctx'> 		pf-&gt;dcbx_cap = DCB_CAP_DCBX_HOST |</div><div class='ctx'> 			       DCB_CAP_DCBX_VER_IEEE;</div><div class='ctx'> 		/* at init capable but disabled */</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_DCB_CAPABLE;</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> 	err = i40e_init_dcb(hw, true);</div><div class='hunk'>@@ -7194,20 +7199,20 @@ static int i40e_init_pf_dcb(struct i40e_pf *pf)</div><div class='ctx'> 			pf-&gt;dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |</div><div class='ctx'> 				       DCB_CAP_DCBX_VER_IEEE;</div><div class='ctx'> </div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_DCB_CAPABLE;</div><div class='add'>+			set_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='ctx'> 			/* Enable DCB tagging only when more than one TC</div><div class='ctx'> 			 * or explicitly disable if only one TC</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (i40e_dcb_get_num_tc(&amp;hw-&gt;local_dcbx_config) &gt; 1)</div><div class='del'>-				pf-&gt;flags |= I40E_FLAG_DCB_ENABLED;</div><div class='add'>+				set_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 			else</div><div class='del'>-				pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+				clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 			dev_dbg(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				"DCBX offload is supported for this PF.\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	} else if (pf-&gt;hw.aq.asq_last_status == I40E_AQ_RC_EPERM) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "FW LLDP disabled for this PF.\n");</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_DISABLE_FW_LLDP;</div><div class='add'>+		set_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			 "Query for DCB configuration failed, err %pe aq_err %s\n",</div><div class='hunk'>@@ -7367,7 +7372,7 @@ static int i40e_up_complete(struct i40e_vsi *vsi)</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		i40e_vsi_configure_msix(vsi);</div><div class='ctx'> 	else</div><div class='ctx'> 		i40e_configure_msi_and_legacy(vsi);</div><div class='hunk'>@@ -7471,7 +7476,7 @@ static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)</div><div class='ctx'> 	 * and its speed values are OK, no need for a flap</div><div class='ctx'> 	 * if non_zero_phy_type was set, still need to force up</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf-&gt;flags))</div><div class='ctx'> 		non_zero_phy_type = true;</div><div class='ctx'> 	else if (is_up &amp;&amp; abilities.phy_type != 0 &amp;&amp; abilities.link_speed != 0)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -7487,7 +7492,7 @@ static int i40e_force_link_state(struct i40e_pf *pf, bool is_up)</div><div class='ctx'> 		non_zero_phy_type ? (u8)((mask &gt;&gt; 32) &amp; 0xff) : 0;</div><div class='ctx'> 	/* Copy the old settings, except of phy_type */</div><div class='ctx'> 	config.abilities = abilities.abilities;</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		if (is_up)</div><div class='ctx'> 			config.abilities |= I40E_AQ_PHY_ENABLE_LINK;</div><div class='ctx'> 		else</div><div class='hunk'>@@ -7537,8 +7542,8 @@ int i40e_up(struct i40e_vsi *vsi)</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (vsi-&gt;type == I40E_VSI_MAIN &amp;&amp;</div><div class='del'>-	    (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED ||</div><div class='del'>-	     vsi-&gt;back-&gt;flags &amp; I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED))</div><div class='add'>+	    (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, vsi-&gt;back-&gt;flags) ||</div><div class='add'>+	     test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, vsi-&gt;back-&gt;flags)))</div><div class='ctx'> 		i40e_force_link_state(vsi-&gt;back, true);</div><div class='ctx'> </div><div class='ctx'> 	err = i40e_vsi_configure(vsi);</div><div class='hunk'>@@ -7566,8 +7571,8 @@ void i40e_down(struct i40e_vsi *vsi)</div><div class='ctx'> 	i40e_vsi_disable_irq(vsi);</div><div class='ctx'> 	i40e_vsi_stop_rings(vsi);</div><div class='ctx'> 	if (vsi-&gt;type == I40E_VSI_MAIN &amp;&amp;</div><div class='del'>-	   (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED ||</div><div class='del'>-	    vsi-&gt;back-&gt;flags &amp; I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED))</div><div class='add'>+	   (test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, vsi-&gt;back-&gt;flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, vsi-&gt;back-&gt;flags)))</div><div class='ctx'> 		i40e_force_link_state(vsi-&gt;back, false);</div><div class='ctx'> 	i40e_napi_disable_all(vsi);</div><div class='ctx'> </div><div class='hunk'>@@ -7973,7 +7978,7 @@ static void *i40e_fwd_add(struct net_device *netdev, struct net_device *vdev)</div><div class='ctx'> 	struct i40e_fwd_adapter *fwd;</div><div class='ctx'> 	int avail_macvlan, ret;</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		netdev_info(netdev, "Macvlans are not supported when DCB is enabled\n");</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -8168,23 +8173,23 @@ static int i40e_setup_tc(struct net_device *netdev, void *type_data)</div><div class='ctx'> 	hw = mqprio_qopt-&gt;qopt.hw;</div><div class='ctx'> 	mode = mqprio_qopt-&gt;mode;</div><div class='ctx'> 	if (!hw) {</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_TC_MQPRIO;</div><div class='add'>+		clear_bit(I40E_FLAG_TC_MQPRIO_ENA, pf-&gt;flags);</div><div class='ctx'> 		memcpy(&amp;vsi-&gt;mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt));</div><div class='ctx'> 		goto config_tc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check if MFP enabled */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		netdev_info(netdev,</div><div class='ctx'> 			    "Configuring TC not supported in MFP mode\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> 	switch (mode) {</div><div class='ctx'> 	case TC_MQPRIO_MODE_DCB:</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_TC_MQPRIO;</div><div class='add'>+		clear_bit(I40E_FLAG_TC_MQPRIO_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 		/* Check if DCB enabled to continue */</div><div class='del'>-		if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED)) {</div><div class='add'>+		if (!test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 			netdev_info(netdev,</div><div class='ctx'> 				    "DCB is not enabled for adapter\n");</div><div class='ctx'> 			return ret;</div><div class='hunk'>@@ -8198,20 +8203,20 @@ static int i40e_setup_tc(struct net_device *netdev, void *type_data)</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case TC_MQPRIO_MODE_CHANNEL:</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_DCB_ENABLED) {</div><div class='add'>+		if (test_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 			netdev_info(netdev,</div><div class='ctx'> 				    "Full offload of TC Mqprio options is not supported when DCB is enabled\n");</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='del'>-		if (!(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED))</div><div class='add'>+		if (!test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		memcpy(&amp;vsi-&gt;mqprio_qopt, mqprio_qopt,</div><div class='ctx'> 		       sizeof(*mqprio_qopt));</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_TC_MQPRIO;</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_TC_MQPRIO_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -8795,11 +8800,11 @@ static int i40e_configure_clsflower(struct i40e_vsi *vsi,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		dev_err(&amp;vsi-&gt;back-&gt;pdev-&gt;dev,</div><div class='ctx'> 			"Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n");</div><div class='del'>-		vsi-&gt;back-&gt;flags &amp;= ~I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-		vsi-&gt;back-&gt;flags |= I40E_FLAG_FD_SB_TO_CLOUD_FILTER;</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_ENA, vsi-&gt;back-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, vsi-&gt;back-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	filter = kzalloc(sizeof(*filter), GFP_KERNEL);</div><div class='hunk'>@@ -8895,11 +8900,11 @@ static int i40e_delete_clsflower(struct i40e_vsi *vsi,</div><div class='ctx'> </div><div class='ctx'> 	pf-&gt;num_cloud_filters--;</div><div class='ctx'> 	if (!pf-&gt;num_cloud_filters)</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_TO_CLOUD_FILTER) &amp;&amp;</div><div class='del'>-		    !(pf-&gt;flags &amp; I40E_FLAG_FD_SB_INACTIVE)) {</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER;</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+		if (test_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf-&gt;flags) &amp;&amp;</div><div class='add'>+		    !test_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags)) {</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -9200,11 +9205,11 @@ static void i40e_cloud_filter_exit(struct i40e_pf *pf)</div><div class='ctx'> 	}</div><div class='ctx'> 	pf-&gt;num_cloud_filters = 0;</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_TO_CLOUD_FILTER) &amp;&amp;</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_FD_SB_INACTIVE)) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER;</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    !test_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags)) {</div><div class='add'>+		set_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_TO_CLOUD_FILTER, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -9292,7 +9297,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired)</div><div class='ctx'> 		i40e_prep_for_reset(pf);</div><div class='ctx'> 		i40e_reset_and_rebuild(pf, true, lock_acquired);</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='del'>-			 pf-&gt;flags &amp; I40E_FLAG_DISABLE_FW_LLDP ?</div><div class='add'>+			 test_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags) ?</div><div class='ctx'> 			 "FW LLDP is disabled\n" :</div><div class='ctx'> 			 "FW LLDP is enabled\n");</div><div class='ctx'> </div><div class='hunk'>@@ -9407,12 +9412,12 @@ static int i40e_handle_lldp_event(struct i40e_pf *pf,</div><div class='ctx'> 	if (I40E_IS_X710TL_DEVICE(hw-&gt;device_id) &amp;&amp;</div><div class='ctx'> 	    (hw-&gt;phy.link_info.link_speed &amp;</div><div class='ctx'> 	     ~(I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB)) &amp;&amp;</div><div class='del'>-	     !(pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE))</div><div class='add'>+	     !test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		/* let firmware decide if the DCB should be disabled */</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_DCB_CAPABLE;</div><div class='add'>+		set_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	/* Not DCB capable or capability disabled */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Ignore if event is not for Nearest Bridge */</div><div class='hunk'>@@ -9448,7 +9453,7 @@ static int i40e_handle_lldp_event(struct i40e_pf *pf,</div><div class='ctx'> 		     (I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB))) {</div><div class='ctx'> 			dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "DCB is not supported for X710-T*L 2.5/5G speeds\n");</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_DCB_CAPABLE;</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "Failed querying DCB configuration data from firmware, err %pe aq_err %s\n",</div><div class='hunk'>@@ -9476,9 +9481,9 @@ static int i40e_handle_lldp_event(struct i40e_pf *pf,</div><div class='ctx'> </div><div class='ctx'> 	/* Enable DCB tagging only when more than one TC */</div><div class='ctx'> 	if (i40e_dcb_get_num_tc(&amp;hw-&gt;local_dcbx_config) &gt; 1)</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_DCB_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 	else</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	set_bit(__I40E_PORT_SUSPENDED, pf-&gt;state);</div><div class='ctx'> 	/* Reconfiguration needed quiesce all VSIs */</div><div class='hunk'>@@ -9546,18 +9551,18 @@ static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,</div><div class='ctx'> 	dev_dbg(&amp;pf-&gt;pdev-&gt;dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",</div><div class='ctx'> 		queue, qtx_ctl);</div><div class='ctx'> </div><div class='add'>+	if (FIELD_GET(I40E_QTX_CTL_PFVF_Q_MASK, qtx_ctl) !=</div><div class='add'>+	    I40E_QTX_CTL_VF_QUEUE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	/* Queue belongs to VF, find the VF and issue VF reset */</div><div class='del'>-	if (((qtx_ctl &amp; I40E_QTX_CTL_PFVF_Q_MASK)</div><div class='del'>-	    &gt;&gt; I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {</div><div class='del'>-		vf_id = (u16)((qtx_ctl &amp; I40E_QTX_CTL_VFVM_INDX_MASK)</div><div class='del'>-			 &gt;&gt; I40E_QTX_CTL_VFVM_INDX_SHIFT);</div><div class='del'>-		vf_id -= hw-&gt;func_caps.vf_base_id;</div><div class='del'>-		vf = &amp;pf-&gt;vf[vf_id];</div><div class='del'>-		i40e_vc_notify_vf_reset(vf);</div><div class='del'>-		/* Allow VF to process pending reset notification */</div><div class='del'>-		msleep(20);</div><div class='del'>-		i40e_reset_vf(vf, false);</div><div class='del'>-	}</div><div class='add'>+	vf_id = FIELD_GET(I40E_QTX_CTL_VFVM_INDX_MASK, qtx_ctl);</div><div class='add'>+	vf_id -= hw-&gt;func_caps.vf_base_id;</div><div class='add'>+	vf = &amp;pf-&gt;vf[vf_id];</div><div class='add'>+	i40e_vc_notify_vf_reset(vf);</div><div class='add'>+	/* Allow VF to process pending reset notification */</div><div class='add'>+	msleep(20);</div><div class='add'>+	i40e_reset_vf(vf, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -9583,8 +9588,7 @@ u32 i40e_get_current_fd_count(struct i40e_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(&amp;pf-&gt;hw, I40E_PFQF_FDSTAT);</div><div class='ctx'> 	fcnt_prog = (val &amp; I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +</div><div class='del'>-		    ((val &amp; I40E_PFQF_FDSTAT_BEST_CNT_MASK) &gt;&gt;</div><div class='del'>-		      I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);</div><div class='add'>+		    FIELD_GET(I40E_PFQF_FDSTAT_BEST_CNT_MASK, val);</div><div class='ctx'> 	return fcnt_prog;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -9598,8 +9602,7 @@ u32 i40e_get_global_fd_count(struct i40e_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(&amp;pf-&gt;hw, I40E_GLQF_FDCNT_0);</div><div class='ctx'> 	fcnt_prog = (val &amp; I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +</div><div class='del'>-		    ((val &amp; I40E_GLQF_FDCNT_0_BESTCNT_MASK) &gt;&gt;</div><div class='del'>-		     I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);</div><div class='add'>+		    FIELD_GET(I40E_GLQF_FDCNT_0_BESTCNT_MASK, val);</div><div class='ctx'> 	return fcnt_prog;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -9610,7 +9613,7 @@ u32 i40e_get_global_fd_count(struct i40e_pf *pf)</div><div class='ctx'> static void i40e_reenable_fdir_sb(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	if (test_and_clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf-&gt;state))</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    (I40E_DEBUG_FD &amp; pf-&gt;hw.debug_mask))</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");</div><div class='ctx'> }</div><div class='hunk'>@@ -9631,7 +9634,7 @@ static void i40e_reenable_fdir_atr(struct i40e_pf *pf)</div><div class='ctx'> 					I40E_L3_SRC_MASK | I40E_L3_DST_MASK |</div><div class='ctx'> 					I40E_L4_SRC_MASK | I40E_L4_DST_MASK);</div><div class='ctx'> </div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    (I40E_DEBUG_FD &amp; pf-&gt;hw.debug_mask))</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n");</div><div class='ctx'> 	}</div><div class='hunk'>@@ -9946,7 +9949,7 @@ static void i40e_link_event(struct i40e_pf *pf)</div><div class='ctx'> 	if (pf-&gt;vf)</div><div class='ctx'> 		i40e_vc_notify_link_state(pf);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_PTP)</div><div class='add'>+	if (test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		i40e_ptp_set_increment(pf);</div><div class='ctx'> #ifdef CONFIG_I40E_DCB</div><div class='ctx'> 	if (new_link == old_link)</div><div class='hunk'>@@ -9963,13 +9966,13 @@ static void i40e_link_event(struct i40e_pf *pf)</div><div class='ctx'> 		memset(&amp;pf-&gt;tmp_cfg, 0, sizeof(pf-&gt;tmp_cfg));</div><div class='ctx'> 		err = i40e_dcb_sw_default_config(pf);</div><div class='ctx'> 		if (err) {</div><div class='del'>-			pf-&gt;flags &amp;= ~(I40E_FLAG_DCB_CAPABLE |</div><div class='del'>-				       I40E_FLAG_DCB_ENABLED);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			pf-&gt;dcbx_cap = DCB_CAP_DCBX_HOST |</div><div class='ctx'> 				       DCB_CAP_DCBX_VER_IEEE;</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_DCB_CAPABLE;</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_DCB_ENABLED;</div><div class='add'>+			set_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> #endif /* CONFIG_I40E_DCB */</div><div class='hunk'>@@ -9994,7 +9997,7 @@ static void i40e_watchdog_subtask(struct i40e_pf *pf)</div><div class='ctx'> 		return;</div><div class='ctx'> 	pf-&gt;service_timer_previous = jiffies;</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_LINK_POLLING_ENABLED) ||</div><div class='add'>+	if (test_bit(I40E_FLAG_LINK_POLLING_ENA, pf-&gt;flags) ||</div><div class='ctx'> 	    test_bit(__I40E_TEMP_LINK_POLLING, pf-&gt;state))</div><div class='ctx'> 		i40e_link_event(pf);</div><div class='ctx'> </div><div class='hunk'>@@ -10005,7 +10008,7 @@ static void i40e_watchdog_subtask(struct i40e_pf *pf)</div><div class='ctx'> 		if (pf-&gt;vsi[i] &amp;&amp; pf-&gt;vsi[i]-&gt;netdev)</div><div class='ctx'> 			i40e_update_stats(pf-&gt;vsi[i]);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_VEB_STATS_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_VEB_STATS_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		/* Update the stats for the active switching components */</div><div class='ctx'> 		for (i = 0; i &lt; I40E_MAX_VEB; i++)</div><div class='ctx'> 			if (pf-&gt;veb[i])</div><div class='hunk'>@@ -10094,7 +10097,7 @@ static void i40e_handle_link_event(struct i40e_pf *pf,</div><div class='ctx'> 		if ((status-&gt;link_info &amp; I40E_AQ_MEDIA_AVAILABLE) &amp;&amp;</div><div class='ctx'> 		    (!(status-&gt;an_info &amp; I40E_AQ_QUALIFIED_MODULE)) &amp;&amp;</div><div class='ctx'> 		    (!(status-&gt;link_info &amp; I40E_AQ_LINK_UP)) &amp;&amp;</div><div class='del'>-		    (!(pf-&gt;flags &amp; I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED))) {</div><div class='add'>+		    (!test_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf-&gt;flags))) {</div><div class='ctx'> 			dev_err(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				"Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n");</div><div class='ctx'> 			dev_err(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -10122,7 +10125,7 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* check for error indications */</div><div class='del'>-	val = rd32(&amp;pf-&gt;hw, pf-&gt;hw.aq.arq.len);</div><div class='add'>+	val = rd32(&amp;pf-&gt;hw, I40E_PF_ARQLEN);</div><div class='ctx'> 	oldval = val;</div><div class='ctx'> 	if (val &amp; I40E_PF_ARQLEN_ARQVFE_MASK) {</div><div class='ctx'> 		if (hw-&gt;debug_mask &amp; I40E_DEBUG_AQ)</div><div class='hunk'>@@ -10141,9 +10144,9 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)</div><div class='ctx'> 		val &amp;= ~I40E_PF_ARQLEN_ARQCRIT_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (oldval != val)</div><div class='del'>-		wr32(&amp;pf-&gt;hw, pf-&gt;hw.aq.arq.len, val);</div><div class='add'>+		wr32(&amp;pf-&gt;hw, I40E_PF_ARQLEN, val);</div><div class='ctx'> </div><div class='del'>-	val = rd32(&amp;pf-&gt;hw, pf-&gt;hw.aq.asq.len);</div><div class='add'>+	val = rd32(&amp;pf-&gt;hw, I40E_PF_ATQLEN);</div><div class='ctx'> 	oldval = val;</div><div class='ctx'> 	if (val &amp; I40E_PF_ATQLEN_ATQVFE_MASK) {</div><div class='ctx'> 		if (pf-&gt;hw.debug_mask &amp; I40E_DEBUG_AQ)</div><div class='hunk'>@@ -10161,7 +10164,7 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)</div><div class='ctx'> 		val &amp;= ~I40E_PF_ATQLEN_ATQCRIT_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (oldval != val)</div><div class='del'>-		wr32(&amp;pf-&gt;hw, pf-&gt;hw.aq.asq.len, val);</div><div class='add'>+		wr32(&amp;pf-&gt;hw, I40E_PF_ATQLEN, val);</div><div class='ctx'> </div><div class='ctx'> 	event.buf_len = I40E_MAX_AQ_BUF_SIZE;</div><div class='ctx'> 	event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);</div><div class='hunk'>@@ -10221,9 +10224,9 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)</div><div class='ctx'> 				 opcode);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-	} while (i++ &lt; pf-&gt;adminq_work_limit);</div><div class='add'>+	} while (i++ &lt; I40E_AQ_WORK_LIMIT);</div><div class='ctx'> </div><div class='del'>-	if (i &lt; pf-&gt;adminq_work_limit)</div><div class='add'>+	if (i &lt; I40E_AQ_WORK_LIMIT)</div><div class='ctx'> 		clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf-&gt;state);</div><div class='ctx'> </div><div class='ctx'> 	/* re-enable Admin queue interrupt cause */</div><div class='hunk'>@@ -10400,7 +10403,7 @@ static int i40e_reconstitute_veb(struct i40e_veb *veb)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto end_reconstitute;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags))</div><div class='ctx'> 		veb-&gt;bridge_mode = BRIDGE_MODE_VEB;</div><div class='ctx'> 	else</div><div class='ctx'> 		veb-&gt;bridge_mode = BRIDGE_MODE_VEPA;</div><div class='hunk'>@@ -10545,7 +10548,7 @@ static void i40e_fdir_sb_setup(struct i40e_pf *pf)</div><div class='ctx'> 			wr32(&amp;pf-&gt;hw, I40E_GLQF_HKEY(i), hkey[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* find existing VSI and see if it needs configuring */</div><div class='hunk'>@@ -10557,8 +10560,8 @@ static void i40e_fdir_sb_setup(struct i40e_pf *pf)</div><div class='ctx'> 				     pf-&gt;vsi[pf-&gt;lan_vsi]-&gt;seid, 0);</div><div class='ctx'> 		if (!vsi) {</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "Couldn't create FDir VSI\n");</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -10936,14 +10939,14 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)</div><div class='ctx'> 			i40e_aq_set_dcb_parameters(hw, false, NULL);</div><div class='ctx'> 			dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "DCB is not supported for X710-T*L 2.5/5G speeds\n");</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_DCB_CAPABLE;</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			i40e_aq_set_dcb_parameters(hw, true, NULL);</div><div class='ctx'> 			ret = i40e_init_pf_dcb(pf);</div><div class='ctx'> 			if (ret) {</div><div class='ctx'> 				dev_info(&amp;pf-&gt;pdev-&gt;dev, "DCB init failed %d, disabled\n",</div><div class='ctx'> 					 ret);</div><div class='del'>-				pf-&gt;flags &amp;= ~I40E_FLAG_DCB_CAPABLE;</div><div class='add'>+				clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='ctx'> 				/* Continue without DCB enabled */</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -11064,7 +11067,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)</div><div class='ctx'> 		wr32(hw, I40E_REG_MSS, val);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_RESTART_AUTONEG) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf-&gt;hw.caps)) {</div><div class='ctx'> 		msleep(75);</div><div class='ctx'> 		ret = i40e_aq_set_link_restart_an(&amp;pf-&gt;hw, true, NULL);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -11074,7 +11077,7 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)</div><div class='ctx'> 					     pf-&gt;hw.aq.asq_last_status));</div><div class='ctx'> 	}</div><div class='ctx'> 	/* reinit the misc interrupt */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		ret = i40e_setup_misc_vector(pf);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			goto end_unlock;</div><div class='hunk'>@@ -11181,14 +11184,10 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)</div><div class='ctx'> 	/* find what triggered the MDD event */</div><div class='ctx'> 	reg = rd32(hw, I40E_GL_MDET_TX);</div><div class='ctx'> 	if (reg &amp; I40E_GL_MDET_TX_VALID_MASK) {</div><div class='del'>-		u8 pf_num = (reg &amp; I40E_GL_MDET_TX_PF_NUM_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_TX_PF_NUM_SHIFT;</div><div class='del'>-		u16 vf_num = (reg &amp; I40E_GL_MDET_TX_VF_NUM_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_TX_VF_NUM_SHIFT;</div><div class='del'>-		u8 event = (reg &amp; I40E_GL_MDET_TX_EVENT_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_TX_EVENT_SHIFT;</div><div class='del'>-		u16 queue = ((reg &amp; I40E_GL_MDET_TX_QUEUE_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_TX_QUEUE_SHIFT) -</div><div class='add'>+		u8 pf_num = FIELD_GET(I40E_GL_MDET_TX_PF_NUM_MASK, reg);</div><div class='add'>+		u16 vf_num = FIELD_GET(I40E_GL_MDET_TX_VF_NUM_MASK, reg);</div><div class='add'>+		u8 event = FIELD_GET(I40E_GL_MDET_TX_EVENT_MASK, reg);</div><div class='add'>+		u16 queue = FIELD_GET(I40E_GL_MDET_TX_QUEUE_MASK, reg) -</div><div class='ctx'> 				pf-&gt;hw.func_caps.base_queue;</div><div class='ctx'> 		if (netif_msg_tx_err(pf))</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",</div><div class='hunk'>@@ -11198,12 +11197,9 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)</div><div class='ctx'> 	}</div><div class='ctx'> 	reg = rd32(hw, I40E_GL_MDET_RX);</div><div class='ctx'> 	if (reg &amp; I40E_GL_MDET_RX_VALID_MASK) {</div><div class='del'>-		u8 func = (reg &amp; I40E_GL_MDET_RX_FUNCTION_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_RX_FUNCTION_SHIFT;</div><div class='del'>-		u8 event = (reg &amp; I40E_GL_MDET_RX_EVENT_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_RX_EVENT_SHIFT;</div><div class='del'>-		u16 queue = ((reg &amp; I40E_GL_MDET_RX_QUEUE_MASK) &gt;&gt;</div><div class='del'>-				I40E_GL_MDET_RX_QUEUE_SHIFT) -</div><div class='add'>+		u8 func = FIELD_GET(I40E_GL_MDET_RX_FUNCTION_MASK, reg);</div><div class='add'>+		u8 event = FIELD_GET(I40E_GL_MDET_RX_EVENT_MASK, reg);</div><div class='add'>+		u16 queue = FIELD_GET(I40E_GL_MDET_RX_QUEUE_MASK, reg) -</div><div class='ctx'> 				pf-&gt;hw.func_caps.base_queue;</div><div class='ctx'> 		if (netif_msg_rx_err(pf))</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",</div><div class='hunk'>@@ -11349,7 +11345,7 @@ static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> 		if (!vsi-&gt;num_rx_desc)</div><div class='ctx'> 			vsi-&gt;num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,</div><div class='ctx'> 						 I40E_REQ_DESCRIPTOR_MULTIPLE);</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+		if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 			vsi-&gt;num_q_vectors = pf-&gt;num_lan_msix;</div><div class='ctx'> 		else</div><div class='ctx'> 			vsi-&gt;num_q_vectors = 1;</div><div class='hunk'>@@ -11667,7 +11663,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)</div><div class='ctx'> 		ring-&gt;count = vsi-&gt;num_tx_desc;</div><div class='ctx'> 		ring-&gt;size = 0;</div><div class='ctx'> 		ring-&gt;dcb_tc = 0;</div><div class='del'>-		if (vsi-&gt;back-&gt;hw_features &amp; I40E_HW_WB_ON_ITR_CAPABLE)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi-&gt;back-&gt;hw.caps))</div><div class='ctx'> 			ring-&gt;flags = I40E_TXR_FLAGS_WB_ON_ITR;</div><div class='ctx'> 		ring-&gt;itr_setting = pf-&gt;tx_itr_default;</div><div class='ctx'> 		WRITE_ONCE(vsi-&gt;tx_rings[i], ring++);</div><div class='hunk'>@@ -11684,7 +11680,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)</div><div class='ctx'> 		ring-&gt;count = vsi-&gt;num_tx_desc;</div><div class='ctx'> 		ring-&gt;size = 0;</div><div class='ctx'> 		ring-&gt;dcb_tc = 0;</div><div class='del'>-		if (vsi-&gt;back-&gt;hw_features &amp; I40E_HW_WB_ON_ITR_CAPABLE)</div><div class='add'>+		if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi-&gt;back-&gt;hw.caps))</div><div class='ctx'> 			ring-&gt;flags = I40E_TXR_FLAGS_WB_ON_ITR;</div><div class='ctx'> 		set_ring_xdp(ring);</div><div class='ctx'> 		ring-&gt;itr_setting = pf-&gt;tx_itr_default;</div><div class='hunk'>@@ -11748,7 +11744,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 	int v_actual;</div><div class='ctx'> 	int iwarp_requested = 0;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	/* The number of vectors we'll request will be comprised of:</div><div class='hunk'>@@ -11787,7 +11783,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 	vectors_left -= pf-&gt;num_lan_msix;</div><div class='ctx'> </div><div class='ctx'> 	/* reserve one vector for sideband flow director */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		if (vectors_left) {</div><div class='ctx'> 			pf-&gt;num_fdsb_msix = 1;</div><div class='ctx'> 			v_budget++;</div><div class='hunk'>@@ -11798,7 +11794,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* can we reserve enough for iWARP? */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		iwarp_requested = pf-&gt;num_iwarp_msix;</div><div class='ctx'> </div><div class='ctx'> 		if (!vectors_left)</div><div class='hunk'>@@ -11810,7 +11806,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* any vectors left over go for VMDq support */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_VMDQ_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		if (!vectors_left) {</div><div class='ctx'> 			pf-&gt;num_vmdq_msix = 0;</div><div class='ctx'> 			pf-&gt;num_vmdq_qps = 0;</div><div class='hunk'>@@ -11867,7 +11863,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 	v_actual = i40e_reserve_msix_vectors(pf, v_budget);</div><div class='ctx'> </div><div class='ctx'> 	if (v_actual &lt; I40E_MIN_MSIX) {</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_MSIX_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags);</div><div class='ctx'> 		kfree(pf-&gt;msix_entries);</div><div class='ctx'> 		pf-&gt;msix_entries = NULL;</div><div class='ctx'> 		pci_disable_msix(pf-&gt;pdev);</div><div class='hunk'>@@ -11905,7 +11901,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 			pf-&gt;num_lan_msix = 1;</div><div class='ctx'> 			break;</div><div class='ctx'> 		case 3:</div><div class='del'>-			if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+			if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 				pf-&gt;num_lan_msix = 1;</div><div class='ctx'> 				pf-&gt;num_iwarp_msix = 1;</div><div class='ctx'> 			} else {</div><div class='hunk'>@@ -11913,7 +11909,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 			}</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='del'>-			if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+			if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 				pf-&gt;num_iwarp_msix = min_t(int, (vec / 3),</div><div class='ctx'> 						 iwarp_requested);</div><div class='ctx'> 				pf-&gt;num_vmdq_vsis = min_t(int, (vec / 3),</div><div class='hunk'>@@ -11922,7 +11918,7 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 				pf-&gt;num_vmdq_vsis = min_t(int, (vec / 2),</div><div class='ctx'> 						  I40E_DEFAULT_NUM_VMDQ_VSI);</div><div class='ctx'> 			}</div><div class='del'>-			if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+			if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 				pf-&gt;num_fdsb_msix = 1;</div><div class='ctx'> 				vec--;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -11934,22 +11930,20 @@ static int i40e_init_msix(struct i40e_pf *pf)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;num_fdsb_msix == 0)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) &amp;&amp; pf-&gt;num_fdsb_msix == 0) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n");</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+		set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_VMDQ_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;num_vmdq_msix == 0)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags) &amp;&amp; pf-&gt;num_vmdq_msix == 0) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "VMDq disabled, not enough MSI-X vectors\n");</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_VMDQ_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;num_iwarp_msix == 0)) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    pf-&gt;num_iwarp_msix == 0) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "IWARP disabled, not enough MSI-X vectors\n");</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_IWARP_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> 	i40e_debug(&amp;pf-&gt;hw, I40E_DEBUG_INIT,</div><div class='ctx'> 		   "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n",</div><div class='hunk'>@@ -12003,7 +11997,7 @@ static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)</div><div class='ctx'> 	int err, v_idx, num_q_vectors;</div><div class='ctx'> </div><div class='ctx'> 	/* if not MSIX, give the one vector only to the LAN VSI */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		num_q_vectors = vsi-&gt;num_q_vectors;</div><div class='ctx'> 	else if (vsi == pf-&gt;vsi[pf-&gt;lan_vsi])</div><div class='ctx'> 		num_q_vectors = 1;</div><div class='hunk'>@@ -12034,38 +12028,39 @@ static int i40e_init_interrupt_scheme(struct i40e_pf *pf)</div><div class='ctx'> 	int vectors = 0;</div><div class='ctx'> 	ssize_t size;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		vectors = i40e_init_msix(pf);</div><div class='ctx'> 		if (vectors &lt; 0) {</div><div class='del'>-			pf-&gt;flags &amp;= ~(I40E_FLAG_MSIX_ENABLED	|</div><div class='del'>-				       I40E_FLAG_IWARP_ENABLED	|</div><div class='del'>-				       I40E_FLAG_RSS_ENABLED	|</div><div class='del'>-				       I40E_FLAG_DCB_CAPABLE	|</div><div class='del'>-				       I40E_FLAG_DCB_ENABLED	|</div><div class='del'>-				       I40E_FLAG_SRIOV_ENABLED	|</div><div class='del'>-				       I40E_FLAG_FD_SB_ENABLED	|</div><div class='del'>-				       I40E_FLAG_FD_ATR_ENABLED	|</div><div class='del'>-				       I40E_FLAG_VMDQ_ENABLED);</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+			clear_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags);</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 			/* rework the queue expectations without MSIX */</div><div class='ctx'> 			i40e_determine_queue_usage(pf);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;flags &amp; I40E_FLAG_MSI_ENABLED)) {</div><div class='add'>+	if (!test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "MSI-X not available, trying MSI\n");</div><div class='ctx'> 		vectors = pci_enable_msi(pf-&gt;pdev);</div><div class='ctx'> 		if (vectors &lt; 0) {</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "MSI init failed - %d\n",</div><div class='ctx'> 				 vectors);</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_MSI_ENABLED;</div><div class='add'>+			clear_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 		vectors = 1;  /* one MSI or Legacy vector */</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    !test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");</div><div class='ctx'> </div><div class='ctx'> 	/* set up vector assignment tracking */</div><div class='hunk'>@@ -12098,7 +12093,8 @@ static int i40e_restore_interrupt_scheme(struct i40e_pf *pf)</div><div class='ctx'> 	 * scheme. We need to re-enabled them here in order to attempt to</div><div class='ctx'> 	 * re-acquire the MSI or MSI-X vectors</div><div class='ctx'> 	 */</div><div class='del'>-	pf-&gt;flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);</div><div class='add'>+	set_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags);</div><div class='add'>+	set_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	err = i40e_init_interrupt_scheme(pf);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -12120,7 +12116,7 @@ static int i40e_restore_interrupt_scheme(struct i40e_pf *pf)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_unwind;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags))</div><div class='ctx'> 		i40e_client_update_msix_info(pf);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -12148,7 +12144,7 @@ static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		err = i40e_setup_misc_vector(pf);</div><div class='ctx'> </div><div class='ctx'> 		if (err) {</div><div class='hunk'>@@ -12158,7 +12154,7 @@ static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf)</div><div class='ctx'> 			return err;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='del'>-		u32 flags = pf-&gt;flags &amp; I40E_FLAG_MSI_ENABLED ? 0 : IRQF_SHARED;</div><div class='add'>+		u32 flags = test_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags) ? 0 : IRQF_SHARED;</div><div class='ctx'> </div><div class='ctx'> 		err = request_irq(pf-&gt;pdev-&gt;irq, i40e_intr, flags,</div><div class='ctx'> 				  pf-&gt;int_name, pf);</div><div class='hunk'>@@ -12362,7 +12358,7 @@ int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_RSS_AQ, pf-&gt;hw.caps))</div><div class='ctx'> 		return i40e_config_rss_aq(vsi, seed, lut, lut_size);</div><div class='ctx'> 	else</div><div class='ctx'> 		return i40e_config_rss_reg(vsi, seed, lut, lut_size);</div><div class='hunk'>@@ -12381,7 +12377,7 @@ int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = vsi-&gt;back;</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_RSS_AQ, pf-&gt;hw.caps))</div><div class='ctx'> 		return i40e_get_rss_aq(vsi, seed, lut, lut_size);</div><div class='ctx'> 	else</div><div class='ctx'> 		return i40e_get_rss_reg(vsi, seed, lut, lut_size);</div><div class='hunk'>@@ -12484,7 +12480,7 @@ int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)</div><div class='ctx'> 	struct i40e_vsi *vsi = pf-&gt;vsi[pf-&gt;lan_vsi];</div><div class='ctx'> 	int new_rss_size;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_RSS_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	queue_count = min_t(int, queue_count, num_online_cpus());</div><div class='hunk'>@@ -12717,9 +12713,9 @@ static int i40e_sw_init(struct i40e_pf *pf)</div><div class='ctx'> 	u16 pow;</div><div class='ctx'> </div><div class='ctx'> 	/* Set default capability flags */</div><div class='del'>-	pf-&gt;flags = I40E_FLAG_RX_CSUM_ENABLED |</div><div class='del'>-		    I40E_FLAG_MSI_ENABLED     |</div><div class='del'>-		    I40E_FLAG_MSIX_ENABLED;</div><div class='add'>+	bitmap_zero(pf-&gt;flags, I40E_PF_FLAGS_NBITS);</div><div class='add'>+	set_bit(I40E_FLAG_MSI_ENA, pf-&gt;flags);</div><div class='add'>+	set_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	/* Set default ITR */</div><div class='ctx'> 	pf-&gt;rx_itr_default = I40E_ITR_RX_DEF;</div><div class='hunk'>@@ -12739,14 +12735,14 @@ static int i40e_sw_init(struct i40e_pf *pf)</div><div class='ctx'> 	pf-&gt;rss_size_max = min_t(int, pf-&gt;rss_size_max, pow);</div><div class='ctx'> </div><div class='ctx'> 	if (pf-&gt;hw.func_caps.rss) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_RSS_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags);</div><div class='ctx'> 		pf-&gt;alloc_rss_size = min_t(int, pf-&gt;rss_size_max,</div><div class='ctx'> 					   num_online_cpus());</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* MFP mode enabled */</div><div class='ctx'> 	if (pf-&gt;hw.func_caps.npar_enable || pf-&gt;hw.func_caps.flex10_enable) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_MFP_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags);</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "MFP mode Enabled\n");</div><div class='ctx'> 		if (i40e_get_partition_bw_setting(pf)) {</div><div class='ctx'> 			dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -12763,84 +12759,31 @@ static int i40e_sw_init(struct i40e_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	if ((pf-&gt;hw.func_caps.fd_filters_guaranteed &gt; 0) ||</div><div class='ctx'> 	    (pf-&gt;hw.func_caps.fd_filters_best_effort &gt; 0)) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_ATR_ENABLED;</div><div class='del'>-		pf-&gt;atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED &amp;&amp;</div><div class='add'>+		set_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags);</div><div class='add'>+		if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    pf-&gt;hw.num_partitions &gt; 1)</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "Flow Director Sideband mode Disabled in MFP mode\n");</div><div class='ctx'> 		else</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_ENABLED;</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='ctx'> 		pf-&gt;fdir_pf_filter_count =</div><div class='ctx'> 				 pf-&gt;hw.func_caps.fd_filters_guaranteed;</div><div class='ctx'> 		pf-&gt;hw.fdir_shared_filter_count =</div><div class='ctx'> 				 pf-&gt;hw.func_caps.fd_filters_best_effort;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw.mac.type == I40E_MAC_X722) {</div><div class='del'>-		pf-&gt;hw_features |= (I40E_HW_RSS_AQ_CAPABLE |</div><div class='del'>-				    I40E_HW_128_QP_RSS_CAPABLE |</div><div class='del'>-				    I40E_HW_ATR_EVICT_CAPABLE |</div><div class='del'>-				    I40E_HW_WB_ON_ITR_CAPABLE |</div><div class='del'>-				    I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE |</div><div class='del'>-				    I40E_HW_NO_PCI_LINK_CHECK |</div><div class='del'>-				    I40E_HW_USE_SET_LLDP_MIB |</div><div class='del'>-				    I40E_HW_GENEVE_OFFLOAD_CAPABLE |</div><div class='del'>-				    I40E_HW_PTP_L4_CAPABLE |</div><div class='del'>-				    I40E_HW_WOL_MC_MAGIC_PKT_WAKE |</div><div class='del'>-				    I40E_HW_OUTER_UDP_CSUM_CAPABLE);</div><div class='del'>-</div><div class='del'>-#define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03</div><div class='del'>-		if (rd32(&amp;pf-&gt;hw, I40E_GLQF_FDEVICTENA(1)) !=</div><div class='del'>-		    I40E_FDEVICT_PCTYPE_DEFAULT) {</div><div class='del'>-			dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='del'>-				 "FD EVICT PCTYPES are not right, disable FD HW EVICT\n");</div><div class='del'>-			pf-&gt;hw_features &amp;= ~I40E_HW_ATR_EVICT_CAPABLE;</div><div class='del'>-		}</div><div class='del'>-	} else if ((pf-&gt;hw.aq.api_maj_ver &gt; 1) ||</div><div class='del'>-		   ((pf-&gt;hw.aq.api_maj_ver == 1) &amp;&amp;</div><div class='del'>-		    (pf-&gt;hw.aq.api_min_ver &gt; 4))) {</div><div class='del'>-		/* Supported in FW API version higher than 1.4 */</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* Enable HW ATR eviction if possible */</div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_ATR_EVICT_CAPABLE)</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED;</div><div class='del'>-</div><div class='del'>-	if ((pf-&gt;hw.mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    (((pf-&gt;hw.aq.fw_maj_ver == 4) &amp;&amp; (pf-&gt;hw.aq.fw_min_ver &lt; 33)) ||</div><div class='del'>-	    (pf-&gt;hw.aq.fw_maj_ver &lt; 4))) {</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_RESTART_AUTONEG;</div><div class='del'>-		/* No DCB support  for FW &lt; v4.33 */</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_NO_DCB_SUPPORT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Disable FW LLDP if FW &lt; v4.3 */</div><div class='del'>-	if ((pf-&gt;hw.mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    (((pf-&gt;hw.aq.fw_maj_ver == 4) &amp;&amp; (pf-&gt;hw.aq.fw_min_ver &lt; 3)) ||</div><div class='del'>-	    (pf-&gt;hw.aq.fw_maj_ver &lt; 4)))</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_STOP_FW_LLDP;</div><div class='del'>-</div><div class='del'>-	/* Use the FW Set LLDP MIB API if FW &gt; v4.40 */</div><div class='del'>-	if ((pf-&gt;hw.mac.type == I40E_MAC_XL710) &amp;&amp;</div><div class='del'>-	    (((pf-&gt;hw.aq.fw_maj_ver == 4) &amp;&amp; (pf-&gt;hw.aq.fw_min_ver &gt;= 40)) ||</div><div class='del'>-	    (pf-&gt;hw.aq.fw_maj_ver &gt;= 5)))</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_USE_SET_LLDP_MIB;</div><div class='del'>-</div><div class='del'>-	/* Enable PTP L4 if FW &gt; v6.0 */</div><div class='del'>-	if (pf-&gt;hw.mac.type == I40E_MAC_XL710 &amp;&amp;</div><div class='del'>-	    pf-&gt;hw.aq.fw_maj_ver &gt;= 6)</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_PTP_L4_CAPABLE;</div><div class='add'>+	if (test_bit(I40E_HW_CAP_ATR_EVICT, pf-&gt;hw.caps))</div><div class='add'>+		set_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	if (pf-&gt;hw.func_caps.vmdq &amp;&amp; num_online_cpus() != 1) {</div><div class='ctx'> 		pf-&gt;num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_VMDQ_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags);</div><div class='ctx'> 		pf-&gt;num_vmdq_qps = i40e_default_queues_per_vmdq(pf);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (pf-&gt;hw.func_caps.iwarp &amp;&amp; num_online_cpus() != 1) {</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_IWARP_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='ctx'> 		/* IWARP needs one extra vector for CQP just like MISC.*/</div><div class='ctx'> 		pf-&gt;num_iwarp_msix = (int)num_online_cpus() + 1;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -12850,25 +12793,23 @@ static int i40e_sw_init(struct i40e_pf *pf)</div><div class='ctx'> 	 * if NPAR is functioning so unset this hw flag in this case.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (pf-&gt;hw.mac.type == I40E_MAC_XL710 &amp;&amp;</div><div class='del'>-	    pf-&gt;hw.func_caps.npar_enable &amp;&amp;</div><div class='del'>-	    (pf-&gt;hw.flags &amp; I40E_HW_FLAG_FW_LLDP_STOPPABLE))</div><div class='del'>-		pf-&gt;hw.flags &amp;= ~I40E_HW_FLAG_FW_LLDP_STOPPABLE;</div><div class='add'>+	    pf-&gt;hw.func_caps.npar_enable)</div><div class='add'>+		clear_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, pf-&gt;hw.caps);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PCI_IOV</div><div class='ctx'> 	if (pf-&gt;hw.func_caps.num_vfs &amp;&amp; pf-&gt;hw.partition_id == 1) {</div><div class='ctx'> 		pf-&gt;num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_SRIOV_ENABLED;</div><div class='add'>+		set_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags);</div><div class='ctx'> 		pf-&gt;num_req_vfs = min_t(int,</div><div class='ctx'> 					pf-&gt;hw.func_caps.num_vfs,</div><div class='ctx'> 					I40E_MAX_VF_COUNT);</div><div class='ctx'> 	}</div><div class='ctx'> #endif /* CONFIG_PCI_IOV */</div><div class='del'>-	pf-&gt;eeprom_version = 0xDEAD;</div><div class='ctx'> 	pf-&gt;lan_veb = I40E_NO_VEB;</div><div class='ctx'> 	pf-&gt;lan_vsi = I40E_NO_VSI;</div><div class='ctx'> </div><div class='ctx'> 	/* By default FW has this off for performance reasons */</div><div class='del'>-	pf-&gt;flags &amp;= ~I40E_FLAG_VEB_STATS_ENABLED;</div><div class='add'>+	clear_bit(I40E_FLAG_VEB_STATS_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	/* set up queue assignment tracking */</div><div class='ctx'> 	size = sizeof(struct i40e_lump_tracking)</div><div class='hunk'>@@ -12887,8 +12828,8 @@ static int i40e_sw_init(struct i40e_pf *pf)</div><div class='ctx'> 		/* Link down on close must be on when total port shutdown</div><div class='ctx'> 		 * is enabled for a given port</div><div class='ctx'> 		 */</div><div class='del'>-		pf-&gt;flags |= (I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED |</div><div class='del'>-			      I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED);</div><div class='add'>+		set_bit(I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf-&gt;flags);</div><div class='add'>+		set_bit(I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf-&gt;flags);</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 			 "total-port-shutdown was enabled, link-down-on-close is forced on\n");</div><div class='ctx'> 	}</div><div class='hunk'>@@ -12914,31 +12855,31 @@ bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (features &amp; NETIF_F_NTUPLE) {</div><div class='ctx'> 		/* Enable filters and mark for reset */</div><div class='del'>-		if (!(pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED))</div><div class='add'>+		if (!test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags))</div><div class='ctx'> 			need_reset = true;</div><div class='ctx'> 		/* enable FD_SB only if there is MSI-X vector and no cloud</div><div class='ctx'> 		 * filters exist</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (pf-&gt;num_fdsb_msix &gt; 0 &amp;&amp; !pf-&gt;num_cloud_filters) {</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* turn off filters, mark for reset and clear SW filter list */</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+		if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 			need_reset = true;</div><div class='ctx'> 			i40e_fdir_filter_exit(pf);</div><div class='ctx'> 		}</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='ctx'> 		clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf-&gt;state);</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+		set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 		/* reset fd counters */</div><div class='ctx'> 		pf-&gt;fd_add_err = 0;</div><div class='ctx'> 		pf-&gt;fd_atr_cnt = 0;</div><div class='ctx'> 		/* if ATR was auto disabled it can be re-enabled. */</div><div class='ctx'> 		if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state))</div><div class='del'>-			if ((pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED) &amp;&amp;</div><div class='add'>+			if (test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 			    (I40E_DEBUG_FD &amp; pf-&gt;hw.debug_mask))</div><div class='ctx'> 				dev_info(&amp;pf-&gt;pdev-&gt;dev, "ATR re-enabled.\n");</div><div class='ctx'> 	}</div><div class='hunk'>@@ -13087,7 +13028,7 @@ static int i40e_get_phys_port_id(struct net_device *netdev,</div><div class='ctx'> 	struct i40e_pf *pf = np-&gt;vsi-&gt;back;</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;hw_features &amp; I40E_HW_PORT_ID_VALID))</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_PORT_ID_VALID, pf-&gt;hw.caps))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	ppid-&gt;id_len = min_t(int, sizeof(hw-&gt;mac.port_addr), sizeof(ppid-&gt;id));</div><div class='hunk'>@@ -13116,7 +13057,7 @@ static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],</div><div class='ctx'> 	struct i40e_pf *pf = np-&gt;vsi-&gt;back;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_SRIOV_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (vid) {</div><div class='hunk'>@@ -13216,9 +13157,9 @@ static int i40e_ndo_bridge_setlink(struct net_device *dev,</div><div class='ctx'> 			veb-&gt;bridge_mode = mode;</div><div class='ctx'> 			/* TODO: If no VFs or VMDq VSIs, disallow VEB mode */</div><div class='ctx'> 			if (mode == BRIDGE_MODE_VEB)</div><div class='del'>-				pf-&gt;flags |= I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+				set_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			else</div><div class='del'>-				pf-&gt;flags &amp;= ~I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+				clear_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -13552,7 +13493,7 @@ static void i40e_queue_pair_enable_irq(struct i40e_vsi *vsi, int queue_pair)</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> </div><div class='ctx'> 	/* All rings in a qp belong to the same qvector. */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		i40e_irq_dynamic_enable(vsi, rxr-&gt;q_vector-&gt;v_idx);</div><div class='ctx'> 	else</div><div class='ctx'> 		i40e_irq_dynamic_enable_icr0(pf);</div><div class='hunk'>@@ -13577,7 +13518,7 @@ static void i40e_queue_pair_disable_irq(struct i40e_vsi *vsi, int queue_pair)</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * All rings in a qp belong to the same qvector.</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		u32 intpf = vsi-&gt;base_vector + rxr-&gt;q_vector-&gt;v_idx;</div><div class='ctx'> </div><div class='ctx'> 		wr32(hw, I40E_PFINT_DYN_CTLN(intpf - 1), 0);</div><div class='hunk'>@@ -13762,7 +13703,7 @@ static int i40e_config_netdev(struct i40e_vsi *vsi)</div><div class='ctx'> 			  NETIF_F_RXCSUM		|</div><div class='ctx'> 			  0;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;hw_features &amp; I40E_HW_OUTER_UDP_CSUM_CAPABLE))</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf-&gt;hw.caps))</div><div class='ctx'> 		netdev-&gt;gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;udp_tunnel_nic_info = &amp;pf-&gt;udp_tunnel_nic;</div><div class='hunk'>@@ -13798,7 +13739,7 @@ static int i40e_config_netdev(struct i40e_vsi *vsi)</div><div class='ctx'> 		      NETIF_F_HW_VLAN_CTAG_TX	|</div><div class='ctx'> 		      NETIF_F_HW_VLAN_CTAG_RX;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags))</div><div class='ctx'> 		hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC;</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;hw_features |= hw_features | NETIF_F_LOOPBACK;</div><div class='hunk'>@@ -13989,7 +13930,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> 		 * negative logic - if it's set, we need to fiddle with</div><div class='ctx'> 		 * the VSI to disable source pruning.</div><div class='ctx'> 		 */</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_SOURCE_PRUNING_DISABLED) {</div><div class='add'>+		if (test_bit(I40E_FLAG_SOURCE_PRUNING_DIS, pf-&gt;flags)) {</div><div class='ctx'> 			memset(&amp;ctxt, 0, sizeof(ctxt));</div><div class='ctx'> 			ctxt.seid = pf-&gt;main_vsi_seid;</div><div class='ctx'> 			ctxt.pf_num = pf-&gt;hw.pf_id;</div><div class='hunk'>@@ -14011,7 +13952,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* MFP mode setup queue map and update VSI */</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    !(pf-&gt;hw.func_caps.iscsi)) { /* NIC type PF */</div><div class='ctx'> 			memset(&amp;ctxt, 0, sizeof(ctxt));</div><div class='ctx'> 			ctxt.seid = pf-&gt;main_vsi_seid;</div><div class='hunk'>@@ -14059,7 +14000,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> 		ctxt.uplink_seid = vsi-&gt;uplink_seid;</div><div class='ctx'> 		ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;</div><div class='ctx'> 		ctxt.flags = I40E_AQ_VSI_TYPE_PF;</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    (i40e_is_vsi_uplink_mode_veb(vsi))) {</div><div class='ctx'> 			ctxt.info.valid_sections |=</div><div class='ctx'> 			     cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);</div><div class='hunk'>@@ -14107,7 +14048,7 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)</div><div class='ctx'> 				cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+		if (test_bit(I40E_FLAG_IWARP_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 			ctxt.info.valid_sections |=</div><div class='ctx'> 				cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);</div><div class='ctx'> 			ctxt.info.queueing_opt_flags |=</div><div class='hunk'>@@ -14323,7 +14264,7 @@ static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)</div><div class='ctx'> 	/* In Legacy mode, we do not have to get any other vector since we</div><div class='ctx'> 	 * piggyback on the misc/ICR0 for queue interrupts.</div><div class='ctx'> 	*/</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	if (vsi-&gt;num_q_vectors)</div><div class='ctx'> 		vsi-&gt;base_vector = i40e_get_lump(pf, pf-&gt;irq_pile,</div><div class='hunk'>@@ -14490,9 +14431,9 @@ struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,</div><div class='ctx'> 			 * already enabled, in which case we can't force VEPA</div><div class='ctx'> 			 * mode.</div><div class='ctx'> 			 */</div><div class='del'>-			if (!(pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)) {</div><div class='add'>+			if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags)) {</div><div class='ctx'> 				veb-&gt;bridge_mode = BRIDGE_MODE_VEPA;</div><div class='del'>-				pf-&gt;flags &amp;= ~I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+				clear_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			}</div><div class='ctx'> 			i40e_config_bridge_mode(veb);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -14588,12 +14529,16 @@ struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE) &amp;&amp;</div><div class='del'>-	    (vsi-&gt;type == I40E_VSI_VMDQ2)) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_RSS_AQ, pf-&gt;hw.caps) &amp;&amp;</div><div class='add'>+	    vsi-&gt;type == I40E_VSI_VMDQ2) {</div><div class='ctx'> 		ret = i40e_vsi_config_rss(vsi);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_config;</div><div class='ctx'> 	}</div><div class='ctx'> 	return vsi;</div><div class='ctx'> </div><div class='add'>+err_config:</div><div class='add'>+	i40e_vsi_clear_rings(vsi);</div><div class='ctx'> err_rings:</div><div class='ctx'> 	i40e_vsi_free_q_vectors(vsi);</div><div class='ctx'> err_msix:</div><div class='hunk'>@@ -14831,7 +14776,7 @@ void i40e_veb_release(struct i40e_veb *veb)</div><div class='ctx'> static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)</div><div class='ctx'> {</div><div class='ctx'> 	struct i40e_pf *pf = veb-&gt;pf;</div><div class='del'>-	bool enable_stats = !!(pf-&gt;flags &amp; I40E_FLAG_VEB_STATS_ENABLED);</div><div class='add'>+	bool enable_stats = !!test_bit(I40E_FLAG_VEB_STATS_ENA, pf-&gt;flags);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = i40e_aq_add_veb(&amp;pf-&gt;hw, veb-&gt;uplink_seid, vsi-&gt;seid,</div><div class='hunk'>@@ -15020,12 +14965,11 @@ static void i40e_setup_pf_switch_element(struct i40e_pf *pf,</div><div class='ctx'> 		 * the PF's VSI</div><div class='ctx'> 		 */</div><div class='ctx'> 		pf-&gt;mac_seid = uplink_seid;</div><div class='del'>-		pf-&gt;pf_seid = downlink_seid;</div><div class='ctx'> 		pf-&gt;main_vsi_seid = seid;</div><div class='ctx'> 		if (printconfig)</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				 "pf_seid=%d main_vsi_seid=%d\n",</div><div class='del'>-				 pf-&gt;pf_seid, pf-&gt;main_vsi_seid);</div><div class='add'>+				 downlink_seid, pf-&gt;main_vsi_seid);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case I40E_SWITCH_ELEMENT_TYPE_PF:</div><div class='ctx'> 	case I40E_SWITCH_ELEMENT_TYPE_VF:</div><div class='hunk'>@@ -15131,7 +15075,7 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acqui</div><div class='ctx'> 	*/</div><div class='ctx'> </div><div class='ctx'> 	if ((pf-&gt;hw.pf_id == 0) &amp;&amp;</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_TRUE_PROMISC_SUPPORT)) {</div><div class='add'>+	    !test_bit(I40E_FLAG_TRUE_PROMISC_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;</div><div class='ctx'> 		pf-&gt;last_sw_conf_flags = flags;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -15198,16 +15142,12 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acqui</div><div class='ctx'> 	/* enable RSS in the HW, even for only one queue, as the stack can use</div><div class='ctx'> 	 * the hash</div><div class='ctx'> 	 */</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_RSS_ENABLED))</div><div class='add'>+	if (test_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags))</div><div class='ctx'> 		i40e_pf_config_rss(pf);</div><div class='ctx'> </div><div class='ctx'> 	/* fill in link information and enable LSE reporting */</div><div class='ctx'> 	i40e_link_event(pf);</div><div class='ctx'> </div><div class='del'>-	/* Initialize user-specific link properties */</div><div class='del'>-	pf-&gt;fc_autoneg_status = ((pf-&gt;hw.phy.link_info.an_info &amp;</div><div class='del'>-				  I40E_AQ_AN_COMPLETED) ? true : false);</div><div class='del'>-</div><div class='ctx'> 	i40e_ptp_init(pf);</div><div class='ctx'> </div><div class='ctx'> 	if (!lock_acquired)</div><div class='hunk'>@@ -15240,42 +15180,42 @@ static void i40e_determine_queue_usage(struct i40e_pf *pf)</div><div class='ctx'> 	queues_left = pf-&gt;hw.func_caps.num_tx_qp;</div><div class='ctx'> </div><div class='ctx'> 	if ((queues_left == 1) ||</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)) {</div><div class='add'>+	    !test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		/* one qp for PF, no queues for anything else */</div><div class='ctx'> 		queues_left = 0;</div><div class='ctx'> 		pf-&gt;alloc_rss_size = pf-&gt;num_lan_qps = 1;</div><div class='ctx'> </div><div class='ctx'> 		/* make sure all the fancies are disabled */</div><div class='del'>-		pf-&gt;flags &amp;= ~(I40E_FLAG_RSS_ENABLED	|</div><div class='del'>-			       I40E_FLAG_IWARP_ENABLED	|</div><div class='del'>-			       I40E_FLAG_FD_SB_ENABLED	|</div><div class='del'>-			       I40E_FLAG_FD_ATR_ENABLED	|</div><div class='del'>-			       I40E_FLAG_DCB_CAPABLE	|</div><div class='del'>-			       I40E_FLAG_DCB_ENABLED	|</div><div class='del'>-			       I40E_FLAG_SRIOV_ENABLED	|</div><div class='del'>-			       I40E_FLAG_VMDQ_ENABLED);</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='del'>-	} else if (!(pf-&gt;flags &amp; (I40E_FLAG_RSS_ENABLED |</div><div class='del'>-				  I40E_FLAG_FD_SB_ENABLED |</div><div class='del'>-				  I40E_FLAG_FD_ATR_ENABLED |</div><div class='del'>-				  I40E_FLAG_DCB_CAPABLE))) {</div><div class='add'>+		clear_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags);</div><div class='add'>+		set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='add'>+	} else if (!test_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+		   !test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+		   !test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+		   !test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags)) {</div><div class='ctx'> 		/* one qp for PF */</div><div class='ctx'> 		pf-&gt;alloc_rss_size = pf-&gt;num_lan_qps = 1;</div><div class='ctx'> 		queues_left -= pf-&gt;num_lan_qps;</div><div class='ctx'> </div><div class='del'>-		pf-&gt;flags &amp;= ~(I40E_FLAG_RSS_ENABLED	|</div><div class='del'>-			       I40E_FLAG_IWARP_ENABLED	|</div><div class='del'>-			       I40E_FLAG_FD_SB_ENABLED	|</div><div class='del'>-			       I40E_FLAG_FD_ATR_ENABLED	|</div><div class='del'>-			       I40E_FLAG_DCB_ENABLED	|</div><div class='del'>-			       I40E_FLAG_VMDQ_ENABLED);</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+		clear_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags);</div><div class='add'>+		set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* Not enough queues for all TCs */</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE) &amp;&amp;</div><div class='del'>-		    (queues_left &lt; I40E_MAX_TRAFFIC_CLASS)) {</div><div class='del'>-			pf-&gt;flags &amp;= ~(I40E_FLAG_DCB_CAPABLE |</div><div class='del'>-					I40E_FLAG_DCB_ENABLED);</div><div class='add'>+		if (test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags) &amp;&amp;</div><div class='add'>+		    queues_left &lt; I40E_MAX_TRAFFIC_CLASS) {</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+			clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "not enough queues for DCB. DCB is disabled.\n");</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -15288,24 +15228,24 @@ static void i40e_determine_queue_usage(struct i40e_pf *pf)</div><div class='ctx'> 		queues_left -= pf-&gt;num_lan_qps;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		if (queues_left &gt; 1) {</div><div class='ctx'> 			queues_left -= 1; /* save 1 queue for FD */</div><div class='ctx'> 		} else {</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_FD_SB_ENABLED;</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_FD_SB_INACTIVE;</div><div class='add'>+			clear_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags);</div><div class='add'>+			set_bit(I40E_FLAG_FD_SB_INACTIVE, pf-&gt;flags);</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_SRIOV_ENABLED) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    pf-&gt;num_vf_qps &amp;&amp; pf-&gt;num_req_vfs &amp;&amp; queues_left) {</div><div class='ctx'> 		pf-&gt;num_req_vfs = min_t(int, pf-&gt;num_req_vfs,</div><div class='ctx'> 					(queues_left / pf-&gt;num_vf_qps));</div><div class='ctx'> 		queues_left -= (pf-&gt;num_req_vfs * pf-&gt;num_vf_qps);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_VMDQ_ENABLED) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_VMDQ_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    pf-&gt;num_vmdq_vsis &amp;&amp; pf-&gt;num_vmdq_qps &amp;&amp; queues_left) {</div><div class='ctx'> 		pf-&gt;num_vmdq_vsis = min_t(int, pf-&gt;num_vmdq_vsis,</div><div class='ctx'> 					  (queues_left / pf-&gt;num_vmdq_qps));</div><div class='hunk'>@@ -15316,7 +15256,7 @@ static void i40e_determine_queue_usage(struct i40e_pf *pf)</div><div class='ctx'> 	dev_dbg(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 		"qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",</div><div class='ctx'> 		pf-&gt;hw.func_caps.num_tx_qp,</div><div class='del'>-		!!(pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED),</div><div class='add'>+		!!test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags),</div><div class='ctx'> 		pf-&gt;num_lan_qps, pf-&gt;alloc_rss_size, pf-&gt;num_req_vfs,</div><div class='ctx'> 		pf-&gt;num_vf_qps, pf-&gt;num_vmdq_vsis, pf-&gt;num_vmdq_qps,</div><div class='ctx'> 		queues_left);</div><div class='hunk'>@@ -15340,7 +15280,8 @@ static int i40e_setup_pf_filter_control(struct i40e_pf *pf)</div><div class='ctx'> 	settings-&gt;hash_lut_size = I40E_HASH_LUT_SIZE_128;</div><div class='ctx'> </div><div class='ctx'> 	/* Flow Director is enabled */</div><div class='del'>-	if (pf-&gt;flags &amp; (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) ||</div><div class='add'>+	    test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags))</div><div class='ctx'> 		settings-&gt;enable_fdir = true;</div><div class='ctx'> </div><div class='ctx'> 	/* Ethtype and MACVLAN filters enabled for PF */</div><div class='hunk'>@@ -15372,21 +15313,21 @@ static void i40e_print_features(struct i40e_pf *pf)</div><div class='ctx'> 	i += scnprintf(&amp;buf[i], REMAIN(i), " VSIs: %d QP: %d",</div><div class='ctx'> 		      pf-&gt;hw.func_caps.num_vsis,</div><div class='ctx'> 		      pf-&gt;vsi[pf-&gt;lan_vsi]-&gt;num_queue_pairs);</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_RSS_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_RSS_ENA, pf-&gt;flags))</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " RSS");</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags))</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " FD_ATR");</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " FD_SB");</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " NTUPLE");</div><div class='ctx'> 	}</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_DCB_CAPABLE)</div><div class='add'>+	if (test_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags))</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " DCB");</div><div class='ctx'> 	i += scnprintf(&amp;buf[i], REMAIN(i), " VxLAN");</div><div class='ctx'> 	i += scnprintf(&amp;buf[i], REMAIN(i), " Geneve");</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_PTP)</div><div class='add'>+	if (test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " PTP");</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags))</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " VEB");</div><div class='ctx'> 	else</div><div class='ctx'> 		i += scnprintf(&amp;buf[i], REMAIN(i), " VEPA");</div><div class='hunk'>@@ -15417,22 +15358,26 @@ static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)</div><div class='ctx'>  * @fec_cfg: FEC option to set in flags</div><div class='ctx'>  * @flags: ptr to flags in which we set FEC option</div><div class='ctx'>  **/</div><div class='del'>-void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags)</div><div class='add'>+void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags)</div><div class='ctx'> {</div><div class='del'>-	if (fec_cfg &amp; I40E_AQ_SET_FEC_AUTO)</div><div class='del'>-		*flags |= I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC;</div><div class='add'>+	if (fec_cfg &amp; I40E_AQ_SET_FEC_AUTO) {</div><div class='add'>+		set_bit(I40E_FLAG_RS_FEC, flags);</div><div class='add'>+		set_bit(I40E_FLAG_BASE_R_FEC, flags);</div><div class='add'>+	}</div><div class='ctx'> 	if ((fec_cfg &amp; I40E_AQ_SET_FEC_REQUEST_RS) ||</div><div class='ctx'> 	    (fec_cfg &amp; I40E_AQ_SET_FEC_ABILITY_RS)) {</div><div class='del'>-		*flags |= I40E_FLAG_RS_FEC;</div><div class='del'>-		*flags &amp;= ~I40E_FLAG_BASE_R_FEC;</div><div class='add'>+		set_bit(I40E_FLAG_RS_FEC, flags);</div><div class='add'>+		clear_bit(I40E_FLAG_BASE_R_FEC, flags);</div><div class='ctx'> 	}</div><div class='ctx'> 	if ((fec_cfg &amp; I40E_AQ_SET_FEC_REQUEST_KR) ||</div><div class='ctx'> 	    (fec_cfg &amp; I40E_AQ_SET_FEC_ABILITY_KR)) {</div><div class='del'>-		*flags |= I40E_FLAG_BASE_R_FEC;</div><div class='del'>-		*flags &amp;= ~I40E_FLAG_RS_FEC;</div><div class='add'>+		set_bit(I40E_FLAG_BASE_R_FEC, flags);</div><div class='add'>+		clear_bit(I40E_FLAG_RS_FEC, flags);</div><div class='add'>+	}</div><div class='add'>+	if (fec_cfg == 0) {</div><div class='add'>+		clear_bit(I40E_FLAG_RS_FEC, flags);</div><div class='add'>+		clear_bit(I40E_FLAG_BASE_R_FEC, flags);</div><div class='ctx'> 	}</div><div class='del'>-	if (fec_cfg == 0)</div><div class='del'>-		*flags &amp;= ~(I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -15676,7 +15621,6 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> #endif /* CONFIG_I40E_DCB */</div><div class='ctx'> 	struct i40e_pf *pf;</div><div class='ctx'> 	struct i40e_hw *hw;</div><div class='del'>-	static u16 pfs_found;</div><div class='ctx'> 	u16 wol_nvm_bits;</div><div class='ctx'> 	char nvm_ver[32];</div><div class='ctx'> 	u16 link_status;</div><div class='hunk'>@@ -15754,7 +15698,6 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	hw-&gt;bus.device = PCI_SLOT(pdev-&gt;devfn);</div><div class='ctx'> 	hw-&gt;bus.func = PCI_FUNC(pdev-&gt;devfn);</div><div class='ctx'> 	hw-&gt;bus.bus_id = pdev-&gt;bus-&gt;number;</div><div class='del'>-	pf-&gt;instance = pfs_found;</div><div class='ctx'> </div><div class='ctx'> 	/* Select something other than the 802.1ad ethertype for the</div><div class='ctx'> 	 * switch to use internally and drop on ingress.</div><div class='hunk'>@@ -15816,7 +15759,6 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	}</div><div class='ctx'> 	hw-&gt;aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;</div><div class='ctx'> 	hw-&gt;aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;</div><div class='del'>-	pf-&gt;adminq_work_limit = I40E_AQ_WORK_LIMIT;</div><div class='ctx'> </div><div class='ctx'> 	snprintf(pf-&gt;int_name, sizeof(pf-&gt;int_name) - 1,</div><div class='ctx'> 		 "%s-%s:misc",</div><div class='hunk'>@@ -15858,15 +15800,15 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		 hw-&gt;vendor_id, hw-&gt;device_id, hw-&gt;subsystem_vendor_id,</div><div class='ctx'> 		 hw-&gt;subsystem_device_id);</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &amp;&amp;</div><div class='del'>-	    hw-&gt;aq.api_min_ver &gt; I40E_FW_MINOR_VERSION(hw))</div><div class='add'>+	if (i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,</div><div class='add'>+				  I40E_FW_MINOR_VERSION(hw) + 1))</div><div class='ctx'> 		dev_dbg(&amp;pdev-&gt;dev,</div><div class='ctx'> 			"The driver for the device detected a newer version of the NVM image v%u.%u than v%u.%u.\n",</div><div class='ctx'> 			 hw-&gt;aq.api_maj_ver,</div><div class='ctx'> 			 hw-&gt;aq.api_min_ver,</div><div class='ctx'> 			 I40E_FW_API_VERSION_MAJOR,</div><div class='ctx'> 			 I40E_FW_MINOR_VERSION(hw));</div><div class='del'>-	else if (hw-&gt;aq.api_maj_ver == 1 &amp;&amp; hw-&gt;aq.api_min_ver &lt; 4)</div><div class='add'>+	else if (i40e_is_aq_api_ver_lt(hw, 1, 4))</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev,</div><div class='ctx'> 			 "The driver for the device detected an older version of the NVM image v%u.%u than expected v%u.%u. Please update the NVM image.\n",</div><div class='ctx'> 			 hw-&gt;aq.api_maj_ver,</div><div class='hunk'>@@ -15913,7 +15855,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	 * Ignore error return codes because if it was already disabled via</div><div class='ctx'> 	 * hardware settings this will fail</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_STOP_FW_LLDP) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_STOP_FW_LLDP, pf-&gt;hw.caps)) {</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "Stopping firmware LLDP agent.\n");</div><div class='ctx'> 		i40e_aq_stop_lldp(hw, true, false, NULL);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -15930,7 +15872,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	ether_addr_copy(hw-&gt;mac.perm_addr, hw-&gt;mac.addr);</div><div class='ctx'> 	i40e_get_port_mac_addr(hw, hw-&gt;mac.port_addr);</div><div class='ctx'> 	if (is_valid_ether_addr(hw-&gt;mac.port_addr))</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_PORT_ID_VALID;</div><div class='add'>+		set_bit(I40E_HW_CAP_PORT_ID_VALID, pf-&gt;hw.caps);</div><div class='ctx'> </div><div class='ctx'> 	i40e_ptp_alloc_pins(pf);</div><div class='ctx'> 	pci_set_drvdata(pdev, pf);</div><div class='hunk'>@@ -15940,10 +15882,10 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	status = i40e_get_fw_lldp_status(&amp;pf-&gt;hw, &amp;lldp_status);</div><div class='ctx'> 	(!status &amp;&amp;</div><div class='ctx'> 	 lldp_status == I40E_GET_FW_LLDP_STATUS_ENABLED) ?</div><div class='del'>-		(pf-&gt;flags &amp;= ~I40E_FLAG_DISABLE_FW_LLDP) :</div><div class='del'>-		(pf-&gt;flags |= I40E_FLAG_DISABLE_FW_LLDP);</div><div class='add'>+		(clear_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags)) :</div><div class='add'>+		(set_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags));</div><div class='ctx'> 	dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-		 (pf-&gt;flags &amp; I40E_FLAG_DISABLE_FW_LLDP) ?</div><div class='add'>+		 test_bit(I40E_FLAG_FW_LLDP_DIS, pf-&gt;flags) ?</div><div class='ctx'> 			"FW LLDP is disabled\n" :</div><div class='ctx'> 			"FW LLDP is enabled\n");</div><div class='ctx'> </div><div class='hunk'>@@ -15953,7 +15895,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	err = i40e_init_pf_dcb(pf);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "DCB init failed %d, disabled\n", err);</div><div class='del'>-		pf-&gt;flags &amp;= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_CAPABLE, pf-&gt;flags);</div><div class='add'>+		clear_bit(I40E_FLAG_DCB_ENA, pf-&gt;flags);</div><div class='ctx'> 		/* Continue without DCB enabled */</div><div class='ctx'> 	}</div><div class='ctx'> #endif /* CONFIG_I40E_DCB */</div><div class='hunk'>@@ -16021,11 +15964,11 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PCI_IOV</div><div class='ctx'> 	/* prep for VF support */</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_SRIOV_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    !test_bit(__I40E_BAD_EEPROM, pf-&gt;state)) {</div><div class='ctx'> 		if (pci_num_vf(pdev))</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+			set_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> 	err = i40e_setup_pf_switch(pf, false, false);</div><div class='hunk'>@@ -16066,7 +16009,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		wr32(hw, I40E_REG_MSS, val);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_RESTART_AUTONEG) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf-&gt;hw.caps)) {</div><div class='ctx'> 		msleep(75);</div><div class='ctx'> 		err = i40e_aq_set_link_restart_an(&amp;pf-&gt;hw, true, NULL);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -16086,7 +16029,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	 * the misc functionality and queue processing is combined in</div><div class='ctx'> 	 * the same vector and that gets setup at open.</div><div class='ctx'> 	 */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		err = i40e_setup_misc_vector(pf);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			dev_info(&amp;pdev-&gt;dev,</div><div class='hunk'>@@ -16099,8 +16042,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PCI_IOV</div><div class='ctx'> 	/* prep for VF support */</div><div class='del'>-	if ((pf-&gt;flags &amp; I40E_FLAG_SRIOV_ENABLED) &amp;&amp;</div><div class='del'>-	    (pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags) &amp;&amp;</div><div class='add'>+	    test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 	    !test_bit(__I40E_BAD_EEPROM, pf-&gt;state)) {</div><div class='ctx'> 		/* disable link interrupts for VFs */</div><div class='ctx'> 		val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);</div><div class='hunk'>@@ -16120,7 +16063,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	}</div><div class='ctx'> #endif /* CONFIG_PCI_IOV */</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		pf-&gt;iwarp_base_vector = i40e_get_lump(pf, pf-&gt;irq_pile,</div><div class='ctx'> 						      pf-&gt;num_iwarp_msix,</div><div class='ctx'> 						      I40E_IWARP_IRQ_PILE_ID);</div><div class='hunk'>@@ -16128,7 +16071,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 			dev_info(&amp;pdev-&gt;dev,</div><div class='ctx'> 				 "failed to get tracking for %d vectors for IWARP err=%d\n",</div><div class='ctx'> 				 pf-&gt;num_iwarp_msix, pf-&gt;iwarp_base_vector);</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_IWARP_ENABLED;</div><div class='add'>+			clear_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -16142,7 +16085,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		  round_jiffies(jiffies + pf-&gt;service_timer_period));</div><div class='ctx'> </div><div class='ctx'> 	/* add this PF to client device list and launch a client service task */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		err = i40e_lan_add_device(pf);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			dev_info(&amp;pdev-&gt;dev, "Failed to add PF to client API service list: %d\n",</div><div class='hunk'>@@ -16155,7 +16098,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	 * and will report PCI Gen 1 x 1 by default so don't bother</div><div class='ctx'> 	 * checking them.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!(pf-&gt;hw_features &amp; I40E_HW_NO_PCI_LINK_CHECK)) {</div><div class='add'>+	if (!test_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, pf-&gt;hw.caps)) {</div><div class='ctx'> 		char speed[PCI_SPEED_SIZE] = "Unknown";</div><div class='ctx'> 		char width[PCI_WIDTH_SIZE] = "Unknown";</div><div class='ctx'> </div><div class='hunk'>@@ -16209,7 +16152,7 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	pf-&gt;hw.phy.link_info.requested_speeds = abilities.link_speed;</div><div class='ctx'> </div><div class='ctx'> 	/* set the FEC config due to the board capabilities */</div><div class='del'>-	i40e_set_fec_in_flags(abilities.fec_cfg_curr_mod_ext_info, &amp;pf-&gt;flags);</div><div class='add'>+	i40e_set_fec_in_flags(abilities.fec_cfg_curr_mod_ext_info, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 	/* get the supported phy types from the fw */</div><div class='ctx'> 	err = i40e_aq_get_phy_capabilities(hw, false, true, &amp;abilities, NULL);</div><div class='hunk'>@@ -16220,11 +16163,11 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> </div><div class='ctx'> 	/* make sure the MFS hasn't been set lower than the default */</div><div class='ctx'> #define MAX_FRAME_SIZE_DEFAULT 0x2600</div><div class='del'>-	val = (rd32(&amp;pf-&gt;hw, I40E_PRTGL_SAH) &amp;</div><div class='del'>-	       I40E_PRTGL_SAH_MFS_MASK) &gt;&gt; I40E_PRTGL_SAH_MFS_SHIFT;</div><div class='add'>+	val = FIELD_GET(I40E_PRTGL_SAH_MFS_MASK,</div><div class='add'>+			rd32(&amp;pf-&gt;hw, I40E_PRTGL_SAH));</div><div class='ctx'> 	if (val &lt; MAX_FRAME_SIZE_DEFAULT)</div><div class='ctx'> 		dev_warn(&amp;pdev-&gt;dev, "MFS for port %x has been set below the default: %x\n",</div><div class='del'>-			 i, val);</div><div class='add'>+			 pf-&gt;hw.port, val);</div><div class='ctx'> </div><div class='ctx'> 	/* Add a filter to drop all Flow control frames from any VSI from being</div><div class='ctx'> 	 * transmitted. By doing so we stop a malicious VF from sending out</div><div class='hunk'>@@ -16236,10 +16179,10 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 						       pf-&gt;main_vsi_seid);</div><div class='ctx'> </div><div class='ctx'> 	if ((pf-&gt;hw.device_id == I40E_DEV_ID_10G_BASE_T) ||</div><div class='del'>-		(pf-&gt;hw.device_id == I40E_DEV_ID_10G_BASE_T4))</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_PHY_CONTROLS_LEDS;</div><div class='add'>+	    (pf-&gt;hw.device_id == I40E_DEV_ID_10G_BASE_T4))</div><div class='add'>+		set_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf-&gt;hw.caps);</div><div class='ctx'> 	if (pf-&gt;hw.device_id == I40E_DEV_ID_SFP_I_X722)</div><div class='del'>-		pf-&gt;hw_features |= I40E_HW_HAVE_CRT_RETIMER;</div><div class='add'>+		set_bit(I40E_HW_CAP_CRT_RETIMER, pf-&gt;hw.caps);</div><div class='ctx'> 	/* print a string summarizing features */</div><div class='ctx'> 	i40e_print_features(pf);</div><div class='ctx'> </div><div class='hunk'>@@ -16308,10 +16251,10 @@ static void i40e_remove(struct pci_dev *pdev)</div><div class='ctx'> 		usleep_range(1000, 2000);</div><div class='ctx'> 	set_bit(__I40E_IN_REMOVE, pf-&gt;state);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_SRIOV_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		set_bit(__I40E_VF_RESETS_DISABLED, pf-&gt;state);</div><div class='ctx'> 		i40e_free_vfs(pf);</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_SRIOV_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_SRIOV_ENA, pf-&gt;flags);</div><div class='ctx'> 	}</div><div class='ctx'> 	/* no more scheduling of any task */</div><div class='ctx'> 	set_bit(__I40E_SUSPENDED, pf-&gt;state);</div><div class='hunk'>@@ -16366,7 +16309,7 @@ static void i40e_remove(struct pci_dev *pdev)</div><div class='ctx'> 	i40e_cloud_filter_exit(pf);</div><div class='ctx'> </div><div class='ctx'> 	/* remove attached clients */</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_IWARP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_IWARP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		ret_code = i40e_lan_del_device(pf);</div><div class='ctx'> 		if (ret_code)</div><div class='ctx'> 			dev_warn(&amp;pdev-&gt;dev, "Failed to delete client device: %d\n",</div><div class='hunk'>@@ -16385,7 +16328,7 @@ static void i40e_remove(struct pci_dev *pdev)</div><div class='ctx'> unmap:</div><div class='ctx'> 	/* Free MSI/legacy interrupt 0 when in recovery mode. */</div><div class='ctx'> 	if (test_bit(__I40E_RECOVERY_MODE, pf-&gt;state) &amp;&amp;</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED))</div><div class='add'>+	    !test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		free_irq(pf-&gt;pdev-&gt;irq, pf);</div><div class='ctx'> </div><div class='ctx'> 	/* shutdown the adminq */</div><div class='hunk'>@@ -16512,6 +16455,9 @@ static void i40e_pci_error_reset_done(struct pci_dev *pdev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	i40e_reset_and_rebuild(pf, false, false);</div><div class='add'>+#ifdef CONFIG_PCI_IOV</div><div class='add'>+	i40e_restore_all_vfs_msi_state(pdev);</div><div class='add'>+#endif /* CONFIG_PCI_IOV */</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -16601,7 +16547,8 @@ static void i40e_shutdown(struct pci_dev *pdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	i40e_notify_client_of_netdev_close(pf-&gt;vsi[pf-&gt;lan_vsi], false);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;wol_en &amp;&amp; (pf-&gt;hw_features &amp; I40E_HW_WOL_MC_MAGIC_PKT_WAKE))</div><div class='add'>+	if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf-&gt;hw.caps) &amp;&amp;</div><div class='add'>+	    pf-&gt;wol_en)</div><div class='ctx'> 		i40e_enable_mc_magic_wake(pf);</div><div class='ctx'> </div><div class='ctx'> 	i40e_prep_for_reset(pf);</div><div class='hunk'>@@ -16613,7 +16560,7 @@ static void i40e_shutdown(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	/* Free MSI/legacy interrupt 0 when in recovery mode. */</div><div class='ctx'> 	if (test_bit(__I40E_RECOVERY_MODE, pf-&gt;state) &amp;&amp;</div><div class='del'>-	    !(pf-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED))</div><div class='add'>+	    !test_bit(I40E_FLAG_MSIX_ENA, pf-&gt;flags))</div><div class='ctx'> 		free_irq(pf-&gt;pdev-&gt;irq, pf);</div><div class='ctx'> </div><div class='ctx'> 	/* Since we're going to destroy queues during the</div><div class='hunk'>@@ -16654,7 +16601,8 @@ static int __maybe_unused i40e_suspend(struct device *dev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	i40e_notify_client_of_netdev_close(pf-&gt;vsi[pf-&gt;lan_vsi], false);</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;wol_en &amp;&amp; (pf-&gt;hw_features &amp; I40E_HW_WOL_MC_MAGIC_PKT_WAKE))</div><div class='add'>+	if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf-&gt;hw.caps) &amp;&amp;</div><div class='add'>+	    pf-&gt;wol_en)</div><div class='ctx'> 		i40e_enable_mc_magic_wake(pf);</div><div class='ctx'> </div><div class='ctx'> 	/* Since we're going to destroy queues during the</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c<br/>index 77cdbfc19d47..605fd82f5d20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_nvm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_nvm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_nvm.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include "i40e_alloc.h"</div><div class='ctx'> #include "i40e_prototype.h"</div><div class='hunk'>@@ -26,8 +27,7 @@ int i40e_init_nvm(struct i40e_hw *hw)</div><div class='ctx'> 	 * as the blank mode may be used in the factory line.</div><div class='ctx'> 	 */</div><div class='ctx'> 	gens = rd32(hw, I40E_GLNVM_GENS);</div><div class='del'>-	sr_size = ((gens &amp; I40E_GLNVM_GENS_SR_SIZE_MASK) &gt;&gt;</div><div class='del'>-			   I40E_GLNVM_GENS_SR_SIZE_SHIFT);</div><div class='add'>+	sr_size = FIELD_GET(I40E_GLNVM_GENS_SR_SIZE_MASK, gens);</div><div class='ctx'> 	/* Switching to words (sr_size contains power of 2KB) */</div><div class='ctx'> 	nvm-&gt;sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;</div><div class='ctx'> </div><div class='hunk'>@@ -193,9 +193,8 @@ static int i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,</div><div class='ctx'> 		ret_code = i40e_poll_sr_srctl_done_bit(hw);</div><div class='ctx'> 		if (!ret_code) {</div><div class='ctx'> 			sr_reg = rd32(hw, I40E_GLNVM_SRDATA);</div><div class='del'>-			*data = (u16)((sr_reg &amp;</div><div class='del'>-				       I40E_GLNVM_SRDATA_RDDATA_MASK)</div><div class='del'>-				    &gt;&gt; I40E_GLNVM_SRDATA_RDDATA_SHIFT);</div><div class='add'>+			*data = FIELD_GET(I40E_GLNVM_SRDATA_RDDATA_MASK,</div><div class='add'>+					  sr_reg);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ret_code)</div><div class='hunk'>@@ -291,7 +290,7 @@ static int i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,</div><div class='ctx'> static int __i40e_read_nvm_word(struct i40e_hw *hw,</div><div class='ctx'> 				u16 offset, u16 *data)</div><div class='ctx'> {</div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, hw-&gt;caps))</div><div class='ctx'> 		return i40e_read_nvm_word_aq(hw, offset, data);</div><div class='ctx'> </div><div class='ctx'> 	return i40e_read_nvm_word_srctl(hw, offset, data);</div><div class='hunk'>@@ -310,14 +309,14 @@ int i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,</div><div class='ctx'> {</div><div class='ctx'> 	int ret_code = 0;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw-&gt;caps))</div><div class='ctx'> 		ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);</div><div class='ctx'> 	if (ret_code)</div><div class='ctx'> 		return ret_code;</div><div class='ctx'> </div><div class='ctx'> 	ret_code = __i40e_read_nvm_word(hw, offset, data);</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, hw-&gt;caps))</div><div class='ctx'> 		i40e_release_nvm(hw);</div><div class='ctx'> </div><div class='ctx'> 	return ret_code;</div><div class='hunk'>@@ -499,7 +498,7 @@ static int __i40e_read_nvm_buffer(struct i40e_hw *hw,</div><div class='ctx'> 				  u16 offset, u16 *words,</div><div class='ctx'> 				  u16 *data)</div><div class='ctx'> {</div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, hw-&gt;caps))</div><div class='ctx'> 		return i40e_read_nvm_buffer_aq(hw, offset, words, data);</div><div class='ctx'> </div><div class='ctx'> 	return i40e_read_nvm_buffer_srctl(hw, offset, words, data);</div><div class='hunk'>@@ -521,7 +520,7 @@ int i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,</div><div class='ctx'> {</div><div class='ctx'> 	int ret_code = 0;</div><div class='ctx'> </div><div class='del'>-	if (hw-&gt;flags &amp; I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, hw-&gt;caps)) {</div><div class='ctx'> 		ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);</div><div class='ctx'> 		if (!ret_code) {</div><div class='ctx'> 			ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,</div><div class='hunk'>@@ -771,13 +770,12 @@ static inline u8 i40e_nvmupd_get_module(u32 val)</div><div class='ctx'> }</div><div class='ctx'> static inline u8 i40e_nvmupd_get_transaction(u32 val)</div><div class='ctx'> {</div><div class='del'>-	return (u8)((val &amp; I40E_NVM_TRANS_MASK) &gt;&gt; I40E_NVM_TRANS_SHIFT);</div><div class='add'>+	return FIELD_GET(I40E_NVM_TRANS_MASK, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline u8 i40e_nvmupd_get_preservation_flags(u32 val)</div><div class='ctx'> {</div><div class='del'>-	return (u8)((val &amp; I40E_NVM_PRESERVATION_FLAGS_MASK) &gt;&gt;</div><div class='del'>-		    I40E_NVM_PRESERVATION_FLAGS_SHIFT);</div><div class='add'>+	return FIELD_GET(I40E_NVM_PRESERVATION_FLAGS_MASK, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const char * const i40e_nvm_update_state_str[] = {</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h<br/>index 001162042050..af4269330581 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_prototype.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_prototype.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_prototype.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_prototype.h</a></div><div class='hunk'>@@ -501,4 +501,74 @@ i40e_add_pinfo_to_list(struct i40e_hw *hw,</div><div class='ctx'> /* i40e_ddp */</div><div class='ctx'> int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);</div><div class='ctx'> </div><div class='add'>+/* Firmware and AdminQ version check helpers */</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * i40e_is_aq_api_ver_ge</div><div class='add'>+ * @hw: pointer to i40e_hw structure</div><div class='add'>+ * @maj: API major value to compare</div><div class='add'>+ * @min: API minor value to compare</div><div class='add'>+ *</div><div class='add'>+ * Assert whether current HW API version is greater/equal than provided.</div><div class='add'>+ **/</div><div class='add'>+static inline bool i40e_is_aq_api_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)</div><div class='add'>+{</div><div class='add'>+	return (hw-&gt;aq.api_maj_ver &gt; maj ||</div><div class='add'>+		(hw-&gt;aq.api_maj_ver == maj &amp;&amp; hw-&gt;aq.api_min_ver &gt;= min));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * i40e_is_aq_api_ver_lt</div><div class='add'>+ * @hw: pointer to i40e_hw structure</div><div class='add'>+ * @maj: API major value to compare</div><div class='add'>+ * @min: API minor value to compare</div><div class='add'>+ *</div><div class='add'>+ * Assert whether current HW API version is less than provided.</div><div class='add'>+ **/</div><div class='add'>+static inline bool i40e_is_aq_api_ver_lt(struct i40e_hw *hw, u16 maj, u16 min)</div><div class='add'>+{</div><div class='add'>+	return !i40e_is_aq_api_ver_ge(hw, maj, min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * i40e_is_fw_ver_ge</div><div class='add'>+ * @hw: pointer to i40e_hw structure</div><div class='add'>+ * @maj: API major value to compare</div><div class='add'>+ * @min: API minor value to compare</div><div class='add'>+ *</div><div class='add'>+ * Assert whether current firmware version is greater/equal than provided.</div><div class='add'>+ **/</div><div class='add'>+static inline bool i40e_is_fw_ver_ge(struct i40e_hw *hw, u16 maj, u16 min)</div><div class='add'>+{</div><div class='add'>+	return (hw-&gt;aq.fw_maj_ver &gt; maj ||</div><div class='add'>+		(hw-&gt;aq.fw_maj_ver == maj &amp;&amp; hw-&gt;aq.fw_min_ver &gt;= min));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * i40e_is_fw_ver_lt</div><div class='add'>+ * @hw: pointer to i40e_hw structure</div><div class='add'>+ * @maj: API major value to compare</div><div class='add'>+ * @min: API minor value to compare</div><div class='add'>+ *</div><div class='add'>+ * Assert whether current firmware version is less than provided.</div><div class='add'>+ **/</div><div class='add'>+static inline bool i40e_is_fw_ver_lt(struct i40e_hw *hw, u16 maj, u16 min)</div><div class='add'>+{</div><div class='add'>+	return !i40e_is_fw_ver_ge(hw, maj, min);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * i40e_is_fw_ver_eq</div><div class='add'>+ * @hw: pointer to i40e_hw structure</div><div class='add'>+ * @maj: API major value to compare</div><div class='add'>+ * @min: API minor value to compare</div><div class='add'>+ *</div><div class='add'>+ * Assert whether current firmware version is equal to provided.</div><div class='add'>+ **/</div><div class='add'>+static inline bool i40e_is_fw_ver_eq(struct i40e_hw *hw, u16 maj, u16 min)</div><div class='add'>+{</div><div class='add'>+	return (hw-&gt;aq.fw_maj_ver &gt; maj ||</div><div class='add'>+		(hw-&gt;aq.fw_maj_ver == maj &amp;&amp; hw-&gt;aq.fw_min_ver == min));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif /* _I40E_PROTOTYPE_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c<br/>index 20b77398f060..e7ebcb09f23c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_ptp.c</a></div><div class='hunk'>@@ -35,7 +35,7 @@ enum i40e_ptp_pin {</div><div class='ctx'> 	GPIO_4</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum i40e_can_set_pins_t {</div><div class='add'>+enum i40e_can_set_pins {</div><div class='ctx'> 	CANT_DO_PINS = -1,</div><div class='ctx'> 	CAN_SET_PINS,</div><div class='ctx'> 	CAN_DO_PINS</div><div class='hunk'>@@ -193,7 +193,7 @@ static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw)</div><div class='ctx'>  * return CAN_DO_PINS if pins can be manipulated within a NIC or</div><div class='ctx'>  * return CANT_DO_PINS otherwise.</div><div class='ctx'>  **/</div><div class='del'>-static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf)</div><div class='add'>+static enum i40e_can_set_pins i40e_can_set_pins(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	if (!i40e_is_ptp_pin_dev(&amp;pf-&gt;hw)) {</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -680,7 +680,7 @@ void i40e_ptp_rx_hang(struct i40e_pf *pf)</div><div class='ctx'> 	 * configured. We don't want to spuriously warn about Rx timestamp</div><div class='ctx'> 	 * hangs if we don't care about the timestamps.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP) || !pf-&gt;ptp_rx)</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags) || !pf-&gt;ptp_rx)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;pf-&gt;ptp_rx_lock);</div><div class='hunk'>@@ -733,7 +733,7 @@ void i40e_ptp_tx_hang(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP) || !pf-&gt;ptp_tx)</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags) || !pf-&gt;ptp_tx)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* Nothing to do if we're not already waiting for a timestamp */</div><div class='hunk'>@@ -771,7 +771,7 @@ void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)</div><div class='ctx'> 	u32 hi, lo;</div><div class='ctx'> 	u64 ns;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP) || !pf-&gt;ptp_tx)</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags) || !pf-&gt;ptp_tx)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* don't attempt to timestamp if we don't have an skb */</div><div class='hunk'>@@ -818,7 +818,7 @@ void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)</div><div class='ctx'> 	/* Since we cannot turn off the Rx timestamp logic if the device is</div><div class='ctx'> 	 * doing Tx timestamping, check if Rx timestamping is configured.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP) || !pf-&gt;ptp_rx)</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags) || !pf-&gt;ptp_rx)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	hw = &amp;pf-&gt;hw;</div><div class='hunk'>@@ -924,7 +924,7 @@ int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwtstamp_config *config = &amp;pf-&gt;tstamp_config;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP))</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	return copy_to_user(ifr-&gt;ifr_data, config, sizeof(*config)) ?</div><div class='hunk'>@@ -1071,7 +1071,7 @@ static void i40e_ptp_set_pins_hw(struct i40e_pf *pf)</div><div class='ctx'> static int i40e_ptp_set_pins(struct i40e_pf *pf,</div><div class='ctx'> 			     struct i40e_ptp_pins_settings *pins)</div><div class='ctx'> {</div><div class='del'>-	enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf);</div><div class='add'>+	enum i40e_can_set_pins pin_caps = i40e_can_set_pins(pf);</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (pin_caps == CANT_DO_PINS)</div><div class='hunk'>@@ -1211,7 +1211,7 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PTP_L4_CAPABLE))</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PTP_L4, pf-&gt;hw.caps))</div><div class='ctx'> 			return -ERANGE;</div><div class='ctx'> 		pf-&gt;ptp_rx = true;</div><div class='ctx'> 		tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |</div><div class='hunk'>@@ -1225,7 +1225,7 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:</div><div class='del'>-		if (!(pf-&gt;hw_features &amp; I40E_HW_PTP_L4_CAPABLE))</div><div class='add'>+		if (!test_bit(I40E_HW_CAP_PTP_L4, pf-&gt;hw.caps))</div><div class='ctx'> 			return -ERANGE;</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:</div><div class='hunk'>@@ -1234,7 +1234,7 @@ static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,</div><div class='ctx'> 		pf-&gt;ptp_rx = true;</div><div class='ctx'> 		tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |</div><div class='ctx'> 			   I40E_PRTTSYN_CTL1_TSYNTYPE_V2;</div><div class='del'>-		if (pf-&gt;hw_features &amp; I40E_HW_PTP_L4_CAPABLE) {</div><div class='add'>+		if (test_bit(I40E_HW_CAP_PTP_L4, pf-&gt;hw.caps)) {</div><div class='ctx'> 			tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;</div><div class='ctx'> 			config-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -1308,7 +1308,7 @@ int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)</div><div class='ctx'> 	struct hwtstamp_config config;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP))</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (copy_from_user(&amp;config, ifr-&gt;ifr_data, sizeof(config)))</div><div class='hunk'>@@ -1426,7 +1426,7 @@ static long i40e_ptp_create_clock(struct i40e_pf *pf)</div><div class='ctx'> void i40e_ptp_save_hw_time(struct i40e_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	/* don't try to access the PTP clock if it's not enabled */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP))</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	i40e_ptp_gettimex(&amp;pf-&gt;ptp_caps, &amp;pf-&gt;ptp_prev_hw_time, NULL);</div><div class='hunk'>@@ -1480,10 +1480,10 @@ void i40e_ptp_init(struct i40e_pf *pf)</div><div class='ctx'> 	/* Only one PF is assigned to control 1588 logic per port. Do not</div><div class='ctx'> 	 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID</div><div class='ctx'> 	 */</div><div class='del'>-	pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) &amp; I40E_PRTTSYN_CTL0_PF_ID_MASK) &gt;&gt;</div><div class='del'>-		I40E_PRTTSYN_CTL0_PF_ID_SHIFT;</div><div class='add'>+	pf_id = FIELD_GET(I40E_PRTTSYN_CTL0_PF_ID_MASK,</div><div class='add'>+			  rd32(hw, I40E_PRTTSYN_CTL0));</div><div class='ctx'> 	if (hw-&gt;pf_id != pf_id) {</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_PTP;</div><div class='add'>+		clear_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags);</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "%s: PTP not supported on %s\n",</div><div class='ctx'> 			 __func__,</div><div class='ctx'> 			 netdev-&gt;name);</div><div class='hunk'>@@ -1504,7 +1504,7 @@ void i40e_ptp_init(struct i40e_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 		if (pf-&gt;hw.debug_mask &amp; I40E_DEBUG_LAN)</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "PHC enabled\n");</div><div class='del'>-		pf-&gt;flags |= I40E_FLAG_PTP;</div><div class='add'>+		set_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags);</div><div class='ctx'> </div><div class='ctx'> 		/* Ensure the clocks are running. */</div><div class='ctx'> 		regval = rd32(hw, I40E_PRTTSYN_CTL0);</div><div class='hunk'>@@ -1539,7 +1539,7 @@ void i40e_ptp_stop(struct i40e_pf *pf)</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	u32 regval;</div><div class='ctx'> </div><div class='del'>-	pf-&gt;flags &amp;= ~I40E_FLAG_PTP;</div><div class='add'>+	clear_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags);</div><div class='ctx'> 	pf-&gt;ptp_tx = false;</div><div class='ctx'> 	pf-&gt;ptp_rx = false;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h<br/>index f408fcf23ce8..14ab642cafdb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_register.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_register.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_register.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_register.h</a></div><div class='hunk'>@@ -207,7 +207,7 @@</div><div class='ctx'> #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26</div><div class='ctx'> #define I40E_GLGEN_MSCA_OPCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_OPCODE_SHIFT)</div><div class='ctx'> #define I40E_GLGEN_MSCA_STCODE_SHIFT 28</div><div class='del'>-#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_STCODE_SHIFT)</div><div class='add'>+#define I40E_GLGEN_MSCA_STCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_STCODE_SHIFT)</div><div class='ctx'> #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30</div><div class='ctx'> #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)</div><div class='ctx'> #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31</div><div class='hunk'>@@ -863,16 +863,6 @@</div><div class='ctx'> #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */</div><div class='ctx'> #define I40E_PFPM_WUFC_MAG_SHIFT 1</div><div class='ctx'> #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)</div><div class='del'>-#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */</div><div class='del'>-#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */</div><div class='ctx'> #define I40E_VFQF_HLUT_MAX_INDEX 15</div><div class='ctx'> </div><div class='ctx'> </div><div class='hunk'>@@ -899,6 +889,7 @@</div><div class='ctx'> #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7</div><div class='ctx'> #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)</div><div class='ctx'> #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */</div><div class='add'>+#define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03</div><div class='ctx'> /* Redefined for X722 family */</div><div class='ctx'> #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */</div><div class='ctx'> #endif /* _I40E_REGISTER_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c<br/>index dd410b15000f..971ba3322038 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_txrx.c</a></div><div class='hunk'>@@ -33,19 +33,16 @@ static void i40e_fdir(struct i40e_ring *tx_ring,</div><div class='ctx'> 	i++;</div><div class='ctx'> 	tx_ring-&gt;next_to_use = (i &lt; tx_ring-&gt;count) ? i : 0;</div><div class='ctx'> </div><div class='del'>-	flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &amp;</div><div class='del'>-		     (fdata-&gt;q_index &lt;&lt; I40E_TXD_FLTR_QW0_QINDEX_SHIFT);</div><div class='add'>+	flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata-&gt;q_index);</div><div class='ctx'> </div><div class='del'>-	flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &amp;</div><div class='del'>-		      (fdata-&gt;flex_off &lt;&lt; I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);</div><div class='add'>+	flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK,</div><div class='add'>+				 fdata-&gt;flex_off);</div><div class='ctx'> </div><div class='del'>-	flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &amp;</div><div class='del'>-		      (fdata-&gt;pctype &lt;&lt; I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);</div><div class='add'>+	flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata-&gt;pctype);</div><div class='ctx'> </div><div class='ctx'> 	/* Use LAN VSI Id if not programmed by user */</div><div class='del'>-	flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &amp;</div><div class='del'>-		      ((u32)(fdata-&gt;dest_vsi ? : pf-&gt;vsi[pf-&gt;lan_vsi]-&gt;id) &lt;&lt;</div><div class='del'>-		       I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);</div><div class='add'>+	flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK,</div><div class='add'>+				 fdata-&gt;dest_vsi ? : pf-&gt;vsi[pf-&gt;lan_vsi]-&gt;id);</div><div class='ctx'> </div><div class='ctx'> 	dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;</div><div class='ctx'> </div><div class='hunk'>@@ -55,17 +52,15 @@ static void i40e_fdir(struct i40e_ring *tx_ring,</div><div class='ctx'> 		     I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE &lt;&lt;</div><div class='ctx'> 		     I40E_TXD_FLTR_QW1_PCMD_SHIFT;</div><div class='ctx'> </div><div class='del'>-	dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &amp;</div><div class='del'>-		     (fdata-&gt;dest_ctl &lt;&lt; I40E_TXD_FLTR_QW1_DEST_SHIFT);</div><div class='add'>+	dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata-&gt;dest_ctl);</div><div class='ctx'> </div><div class='del'>-	dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &amp;</div><div class='del'>-		     (fdata-&gt;fd_status &lt;&lt; I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);</div><div class='add'>+	dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK,</div><div class='add'>+				fdata-&gt;fd_status);</div><div class='ctx'> </div><div class='ctx'> 	if (fdata-&gt;cnt_index) {</div><div class='ctx'> 		dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;</div><div class='del'>-		dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &amp;</div><div class='del'>-			     ((u32)fdata-&gt;cnt_index &lt;&lt;</div><div class='del'>-			      I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);</div><div class='add'>+		dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,</div><div class='add'>+					fdata-&gt;cnt_index);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	fdir_desc-&gt;qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);</div><div class='hunk'>@@ -464,7 +459,7 @@ static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi,</div><div class='ctx'> 			       &amp;pf-&gt;fd_tcp6_filter_cnt);</div><div class='ctx'> </div><div class='ctx'> 	if (add) {</div><div class='del'>-		if ((pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 		    I40E_DEBUG_FD &amp; pf-&gt;hw.debug_mask)</div><div class='ctx'> 			dev_info(&amp;pf-&gt;pdev-&gt;dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");</div><div class='ctx'> 		set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state);</div><div class='hunk'>@@ -691,8 +686,7 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,</div><div class='ctx'> 	u32 error;</div><div class='ctx'> </div><div class='ctx'> 	qw0 = (struct i40e_16b_rx_wb_qw0 *)&amp;qword0_raw;</div><div class='del'>-	error = (qword1 &amp; I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) &gt;&gt;</div><div class='del'>-		I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;</div><div class='add'>+	error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1);</div><div class='ctx'> </div><div class='ctx'> 	if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {</div><div class='ctx'> 		pf-&gt;fd_inv = le32_to_cpu(qw0-&gt;hi_dword.fd_id);</div><div class='hunk'>@@ -734,7 +728,7 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,</div><div class='ctx'> 		 * FD ATR/SB and then re-enable it when there is room.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (fcnt_prog &gt;= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {</div><div class='del'>-			if ((pf-&gt;flags &amp; I40E_FLAG_FD_SB_ENABLED) &amp;&amp;</div><div class='add'>+			if (test_bit(I40E_FLAG_FD_SB_ENA, pf-&gt;flags) &amp;&amp;</div><div class='ctx'> 			    !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,</div><div class='ctx'> 					      pf-&gt;state))</div><div class='ctx'> 				if (I40E_DEBUG_FD &amp; pf-&gt;hw.debug_mask)</div><div class='hunk'>@@ -1071,7 +1065,7 @@ static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,</div><div class='ctx'> 	if (q_vector-&gt;arm_wb_state)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |</div><div class='ctx'> 		      I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */</div><div class='ctx'> </div><div class='hunk'>@@ -1095,7 +1089,7 @@ static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,</div><div class='ctx'>  **/</div><div class='ctx'> void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)</div><div class='ctx'> {</div><div class='del'>-	if (vsi-&gt;back-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MSIX_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |</div><div class='ctx'> 			  I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */</div><div class='ctx'> 			  I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |</div><div class='hunk'>@@ -1403,8 +1397,7 @@ void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,</div><div class='ctx'> {</div><div class='ctx'> 	u8 id;</div><div class='ctx'> </div><div class='del'>-	id = (qword1 &amp; I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) &gt;&gt;</div><div class='del'>-		  I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;</div><div class='add'>+	id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1);</div><div class='ctx'> </div><div class='ctx'> 	if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)</div><div class='ctx'> 		i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);</div><div class='hunk'>@@ -1764,11 +1757,9 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,</div><div class='ctx'> 	u64 qword;</div><div class='ctx'> </div><div class='ctx'> 	qword = le64_to_cpu(rx_desc-&gt;wb.qword1.status_error_len);</div><div class='del'>-	ptype = (qword &amp; I40E_RXD_QW1_PTYPE_MASK) &gt;&gt; I40E_RXD_QW1_PTYPE_SHIFT;</div><div class='del'>-	rx_error = (qword &amp; I40E_RXD_QW1_ERROR_MASK) &gt;&gt;</div><div class='del'>-		   I40E_RXD_QW1_ERROR_SHIFT;</div><div class='del'>-	rx_status = (qword &amp; I40E_RXD_QW1_STATUS_MASK) &gt;&gt;</div><div class='del'>-		    I40E_RXD_QW1_STATUS_SHIFT;</div><div class='add'>+	ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);</div><div class='add'>+	rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword);</div><div class='add'>+	rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);</div><div class='ctx'> 	decoded = decode_rx_desc_ptype(ptype);</div><div class='ctx'> </div><div class='ctx'> 	skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='hunk'>@@ -1901,13 +1892,10 @@ void i40e_process_skb_fields(struct i40e_ring *rx_ring,</div><div class='ctx'> 			     union i40e_rx_desc *rx_desc, struct sk_buff *skb)</div><div class='ctx'> {</div><div class='ctx'> 	u64 qword = le64_to_cpu(rx_desc-&gt;wb.qword1.status_error_len);</div><div class='del'>-	u32 rx_status = (qword &amp; I40E_RXD_QW1_STATUS_MASK) &gt;&gt;</div><div class='del'>-			I40E_RXD_QW1_STATUS_SHIFT;</div><div class='add'>+	u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);</div><div class='ctx'> 	u32 tsynvalid = rx_status &amp; I40E_RXD_QW1_STATUS_TSYNVALID_MASK;</div><div class='del'>-	u32 tsyn = (rx_status &amp; I40E_RXD_QW1_STATUS_TSYNINDX_MASK) &gt;&gt;</div><div class='del'>-		   I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;</div><div class='del'>-	u8 rx_ptype = (qword &amp; I40E_RXD_QW1_PTYPE_MASK) &gt;&gt;</div><div class='del'>-		      I40E_RXD_QW1_PTYPE_SHIFT;</div><div class='add'>+	u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status);</div><div class='add'>+	u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(tsynvalid))</div><div class='ctx'> 		i40e_ptp_rx_hwtstamp(rx_ring-&gt;vsi-&gt;back, skb, tsyn);</div><div class='hunk'>@@ -2554,8 +2542,7 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget,</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		size = (qword &amp; I40E_RXD_QW1_LENGTH_PBUF_MASK) &gt;&gt;</div><div class='del'>-		       I40E_RXD_QW1_LENGTH_PBUF_SHIFT;</div><div class='add'>+		size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword);</div><div class='ctx'> 		if (!size)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='hunk'>@@ -2699,7 +2686,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,</div><div class='ctx'> 	u32 intval;</div><div class='ctx'> </div><div class='ctx'> 	/* If we don't have MSIX, then we only need to re-enable icr0 */</div><div class='del'>-	if (!(vsi-&gt;back-&gt;flags &amp; I40E_FLAG_MSIX_ENABLED)) {</div><div class='add'>+	if (!test_bit(I40E_FLAG_MSIX_ENA, vsi-&gt;back-&gt;flags)) {</div><div class='ctx'> 		i40e_irq_dynamic_enable_icr0(vsi-&gt;back);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2888,7 +2875,7 @@ static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='ctx'> 	/* make sure ATR is enabled */</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_FD_ATR_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_FD_ATR_ENA, pf-&gt;flags))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state))</div><div class='hunk'>@@ -2933,7 +2920,7 @@ static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> 	/* Due to lack of space, no more new filters can be programmed */</div><div class='ctx'> 	if (th-&gt;syn &amp;&amp; test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf-&gt;state))</div><div class='ctx'> 		return;</div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_HW_ATR_EVICT_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		/* HW ATR eviction will take care of removing filters on FIN</div><div class='ctx'> 		 * and RST packets.</div><div class='ctx'> 		 */</div><div class='hunk'>@@ -2959,8 +2946,8 @@ static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> 	i++;</div><div class='ctx'> 	tx_ring-&gt;next_to_use = (i &lt; tx_ring-&gt;count) ? i : 0;</div><div class='ctx'> </div><div class='del'>-	flex_ptype = (tx_ring-&gt;queue_index &lt;&lt; I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &amp;</div><div class='del'>-		      I40E_TXD_FLTR_QW0_QINDEX_MASK;</div><div class='add'>+	flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK,</div><div class='add'>+				tx_ring-&gt;queue_index);</div><div class='ctx'> 	flex_ptype |= (tx_flags &amp; I40E_TX_FLAGS_IPV4) ?</div><div class='ctx'> 		      (I40E_FILTER_PCTYPE_NONF_IPV4_TCP &lt;&lt;</div><div class='ctx'> 		       I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :</div><div class='hunk'>@@ -2986,16 +2973,14 @@ static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> 	dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;</div><div class='ctx'> 	if (!(tx_flags &amp; I40E_TX_FLAGS_UDP_TUNNEL))</div><div class='ctx'> 		dtype_cmd |=</div><div class='del'>-			((u32)I40E_FD_ATR_STAT_IDX(pf-&gt;hw.pf_id) &lt;&lt;</div><div class='del'>-			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &amp;</div><div class='del'>-			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;</div><div class='add'>+			FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,</div><div class='add'>+				   I40E_FD_ATR_STAT_IDX(pf-&gt;hw.pf_id));</div><div class='ctx'> 	else</div><div class='ctx'> 		dtype_cmd |=</div><div class='del'>-			((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf-&gt;hw.pf_id) &lt;&lt;</div><div class='del'>-			I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &amp;</div><div class='del'>-			I40E_TXD_FLTR_QW1_CNTINDEX_MASK;</div><div class='add'>+			FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,</div><div class='add'>+				   I40E_FD_ATR_TUNNEL_STAT_IDX(pf-&gt;hw.pf_id));</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_HW_ATR_EVICT_ENABLED)</div><div class='add'>+	if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf-&gt;flags))</div><div class='ctx'> 		dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;</div><div class='ctx'> </div><div class='ctx'> 	fdir_desc-&gt;qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);</div><div class='hunk'>@@ -3053,7 +3038,7 @@ static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,</div><div class='ctx'> 		tx_flags |= I40E_TX_FLAGS_SW_VLAN;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!(tx_ring-&gt;vsi-&gt;back-&gt;flags &amp; I40E_FLAG_DCB_ENABLED))</div><div class='add'>+	if (!test_bit(I40E_FLAG_DCB_ENA, tx_ring-&gt;vsi-&gt;back-&gt;flags))</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	/* Insert 802.1p priority into VLAN header */</div><div class='hunk'>@@ -3229,7 +3214,7 @@ static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> 	 * we are not already transmitting a packet to be timestamped</div><div class='ctx'> 	 */</div><div class='ctx'> 	pf = i40e_netdev_to_pf(tx_ring-&gt;netdev);</div><div class='del'>-	if (!(pf-&gt;flags &amp; I40E_FLAG_PTP))</div><div class='add'>+	if (!test_bit(I40E_FLAG_PTP_ENA, pf-&gt;flags))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (pf-&gt;ptp_tx &amp;&amp;</div><div class='hunk'>@@ -3601,8 +3586,7 @@ static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> </div><div class='ctx'> 	if (tx_flags &amp; I40E_TX_FLAGS_HW_VLAN) {</div><div class='ctx'> 		td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;</div><div class='del'>-		td_tag = (tx_flags &amp; I40E_TX_FLAGS_VLAN_MASK) &gt;&gt;</div><div class='del'>-			 I40E_TX_FLAGS_VLAN_SHIFT;</div><div class='add'>+		td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	first-&gt;tx_flags = tx_flags;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h<br/>index 421fe5675584..abf15067eb5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_txrx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_txrx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_txrx.h</a></div><div class='hunk'>@@ -58,7 +58,7 @@ static inline u16 i40e_intrl_usec_to_reg(int intrl)</div><div class='ctx'>  * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any</div><div class='ctx'>  * register but instead is a special value meaning "don't update" ITR0/1/2.</div><div class='ctx'>  */</div><div class='del'>-enum i40e_dyn_idx_t {</div><div class='add'>+enum i40e_dyn_idx {</div><div class='ctx'> 	I40E_IDX_ITR0 = 0,</div><div class='ctx'> 	I40E_IDX_ITR1 = 1,</div><div class='ctx'> 	I40E_IDX_ITR2 = 2,</div><div class='hunk'>@@ -92,8 +92,8 @@ enum i40e_dyn_idx_t {</div><div class='ctx'> 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))</div><div class='ctx'> </div><div class='ctx'> #define i40e_pf_get_default_rss_hena(pf) \</div><div class='del'>-	(((pf)-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \</div><div class='del'>-	  I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)</div><div class='add'>+	(test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, (pf)-&gt;hw.caps) ? \</div><div class='add'>+	 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)</div><div class='ctx'> </div><div class='ctx'> /* Supported Rx Buffer Sizes (a multiple of 128) */</div><div class='ctx'> #define I40E_RXBUFFER_256   256</div><div class='hunk'>@@ -306,7 +306,7 @@ struct i40e_rx_queue_stats {</div><div class='ctx'> 	u64 page_busy_count;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-enum i40e_ring_state_t {</div><div class='add'>+enum i40e_ring_state {</div><div class='ctx'> 	__I40E_TX_FDIR_INIT_DONE,</div><div class='ctx'> 	__I40E_TX_XPS_INIT_DONE,</div><div class='ctx'> 	__I40E_RING_STATE_NBITS /* must be last */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h<br/>index aff6dc6afbe2..d9031499697e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_type.h</a></div><div class='hunk'>@@ -37,11 +37,11 @@ typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);</div><div class='ctx'> #define I40E_QTX_CTL_VM_QUEUE	0x1</div><div class='ctx'> #define I40E_QTX_CTL_PF_QUEUE	0x2</div><div class='ctx'> </div><div class='del'>-#define I40E_MDIO_CLAUSE22_STCODE_MASK		I40E_GLGEN_MSCA_STCODE_MASK</div><div class='add'>+#define I40E_MDIO_CLAUSE22_STCODE_MASK		I40E_GLGEN_MSCA_STCODE_MASK(1)</div><div class='ctx'> #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK	I40E_GLGEN_MSCA_OPCODE_MASK(1)</div><div class='ctx'> #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK	I40E_GLGEN_MSCA_OPCODE_MASK(2)</div><div class='ctx'> </div><div class='del'>-#define I40E_MDIO_CLAUSE45_STCODE_MASK		I40E_GLGEN_MSCA_STCODE_MASK</div><div class='add'>+#define I40E_MDIO_CLAUSE45_STCODE_MASK		I40E_GLGEN_MSCA_STCODE_MASK(0)</div><div class='ctx'> #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK	I40E_GLGEN_MSCA_OPCODE_MASK(0)</div><div class='ctx'> #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK	I40E_GLGEN_MSCA_OPCODE_MASK(1)</div><div class='ctx'> #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK	I40E_GLGEN_MSCA_OPCODE_MASK(3)</div><div class='hunk'>@@ -64,9 +64,7 @@ typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);</div><div class='ctx'> enum i40e_mac_type {</div><div class='ctx'> 	I40E_MAC_UNKNOWN = 0,</div><div class='ctx'> 	I40E_MAC_XL710,</div><div class='del'>-	I40E_MAC_VF,</div><div class='ctx'> 	I40E_MAC_X722,</div><div class='del'>-	I40E_MAC_X722_VF,</div><div class='ctx'> 	I40E_MAC_GENERIC,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -272,9 +270,7 @@ struct i40e_mac_info {</div><div class='ctx'> 	enum i40e_mac_type type;</div><div class='ctx'> 	u8 addr[ETH_ALEN];</div><div class='ctx'> 	u8 perm_addr[ETH_ALEN];</div><div class='del'>-	u8 san_addr[ETH_ALEN];</div><div class='ctx'> 	u8 port_addr[ETH_ALEN];</div><div class='del'>-	u16 max_fcoeq;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum i40e_aq_resources_ids {</div><div class='hunk'>@@ -482,6 +478,36 @@ struct i40e_dcbx_config {</div><div class='ctx'> 	struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum i40e_hw_flags {</div><div class='add'>+	I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE,</div><div class='add'>+	I40E_HW_CAP_802_1AD,</div><div class='add'>+	I40E_HW_CAP_AQ_PHY_ACCESS,</div><div class='add'>+	I40E_HW_CAP_NVM_READ_REQUIRES_LOCK,</div><div class='add'>+	I40E_HW_CAP_FW_LLDP_STOPPABLE,</div><div class='add'>+	I40E_HW_CAP_FW_LLDP_PERSISTENT,</div><div class='add'>+	I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED,</div><div class='add'>+	I40E_HW_CAP_X722_FEC_REQUEST,</div><div class='add'>+	I40E_HW_CAP_RSS_AQ,</div><div class='add'>+	I40E_HW_CAP_128_QP_RSS,</div><div class='add'>+	I40E_HW_CAP_ATR_EVICT,</div><div class='add'>+	I40E_HW_CAP_WB_ON_ITR,</div><div class='add'>+	I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,</div><div class='add'>+	I40E_HW_CAP_NO_PCI_LINK_CHECK,</div><div class='add'>+	I40E_HW_CAP_100M_SGMII,</div><div class='add'>+	I40E_HW_CAP_NO_DCB_SUPPORT,</div><div class='add'>+	I40E_HW_CAP_USE_SET_LLDP_MIB,</div><div class='add'>+	I40E_HW_CAP_GENEVE_OFFLOAD,</div><div class='add'>+	I40E_HW_CAP_PTP_L4,</div><div class='add'>+	I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE,</div><div class='add'>+	I40E_HW_CAP_CRT_RETIMER,</div><div class='add'>+	I40E_HW_CAP_OUTER_UDP_CSUM,</div><div class='add'>+	I40E_HW_CAP_PHY_CONTROLS_LEDS,</div><div class='add'>+	I40E_HW_CAP_STOP_FW_LLDP,</div><div class='add'>+	I40E_HW_CAP_PORT_ID_VALID,</div><div class='add'>+	I40E_HW_CAP_RESTART_AUTONEG,</div><div class='add'>+	I40E_HW_CAPS_NBITS,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Port hardware description */</div><div class='ctx'> struct i40e_hw {</div><div class='ctx'> 	u8 __iomem *hw_addr;</div><div class='hunk'>@@ -546,16 +572,7 @@ struct i40e_hw {</div><div class='ctx'> 	struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */</div><div class='ctx'> 	struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */</div><div class='ctx'> </div><div class='del'>-#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)</div><div class='del'>-#define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)</div><div class='del'>-#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)</div><div class='del'>-#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)</div><div class='del'>-#define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)</div><div class='del'>-#define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)</div><div class='del'>-#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)</div><div class='del'>-#define I40E_HW_FLAG_DROP_MODE              BIT_ULL(7)</div><div class='del'>-#define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)</div><div class='del'>-	u64 flags;</div><div class='add'>+	DECLARE_BITMAP(caps, I40E_HW_CAPS_NBITS);</div><div class='ctx'> </div><div class='ctx'> 	/* Used in set switch config AQ command */</div><div class='ctx'> 	u16 switch_tag;</div><div class='hunk'>@@ -567,12 +584,6 @@ struct i40e_hw {</div><div class='ctx'> 	char err_str[16];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static inline bool i40e_is_vf(struct i40e_hw *hw)</div><div class='del'>-{</div><div class='del'>-	return (hw-&gt;mac.type == I40E_MAC_VF ||</div><div class='del'>-		hw-&gt;mac.type == I40E_MAC_X722_VF);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> struct i40e_driver_version {</div><div class='ctx'> 	u8 major_version;</div><div class='ctx'> 	u8 minor_version;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c<br/>index 3f99eb198245..908cdbd3ec5d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c</a></div><div class='hunk'>@@ -154,6 +154,32 @@ void i40e_vc_notify_reset(struct i40e_pf *pf)</div><div class='ctx'> 			     (u8 *)&amp;pfe, sizeof(struct virtchnl_pf_event));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#ifdef CONFIG_PCI_IOV</div><div class='add'>+void i40e_restore_all_vfs_msi_state(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	u16 vf_id;</div><div class='add'>+	u16 pos;</div><div class='add'>+</div><div class='add'>+	/* Continue only if this is a PF */</div><div class='add'>+	if (!pdev-&gt;is_physfn)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!pci_num_vf(pdev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);</div><div class='add'>+	if (pos) {</div><div class='add'>+		struct pci_dev *vf_dev = NULL;</div><div class='add'>+</div><div class='add'>+		pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &amp;vf_id);</div><div class='add'>+		while ((vf_dev = pci_get_device(pdev-&gt;vendor, vf_id, vf_dev))) {</div><div class='add'>+			if (vf_dev-&gt;is_virtfn &amp;&amp; vf_dev-&gt;physfn == pdev)</div><div class='add'>+				pci_restore_msi_state(vf_dev);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+#endif /* CONFIG_PCI_IOV */</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * i40e_vc_notify_vf_reset</div><div class='ctx'>  * @vf: pointer to the VF structure</div><div class='hunk'>@@ -474,10 +500,10 @@ static void i40e_release_rdma_qvlist(struct i40e_vf *vf)</div><div class='ctx'> 			 */</div><div class='ctx'> 			reg_idx = (msix_vf - 1) * vf-&gt;vf_id + qv_info-&gt;ceq_idx;</div><div class='ctx'> 			reg = rd32(hw, I40E_VPINT_CEQCTL(reg_idx));</div><div class='del'>-			next_q_index = (reg &amp; I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK)</div><div class='del'>-					&gt;&gt; I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT;</div><div class='del'>-			next_q_type = (reg &amp; I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK)</div><div class='del'>-					&gt;&gt; I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT;</div><div class='add'>+			next_q_index = FIELD_GET(I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK,</div><div class='add'>+						 reg);</div><div class='add'>+			next_q_type = FIELD_GET(I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK,</div><div class='add'>+						reg);</div><div class='ctx'> </div><div class='ctx'> 			reg_idx = ((msix_vf - 1) * vf-&gt;vf_id) + (v_idx - 1);</div><div class='ctx'> 			reg = (next_q_index &amp;</div><div class='hunk'>@@ -555,10 +581,10 @@ i40e_config_rdma_qvlist(struct i40e_vf *vf,</div><div class='ctx'> 		 * queue on top. Also link it with the new queue in CEQCTL.</div><div class='ctx'> 		 */</div><div class='ctx'> 		reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx));</div><div class='del'>-		next_q_idx = ((reg &amp; I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) &gt;&gt;</div><div class='del'>-				I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT);</div><div class='del'>-		next_q_type = ((reg &amp; I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK) &gt;&gt;</div><div class='del'>-				I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT);</div><div class='add'>+		next_q_idx = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK,</div><div class='add'>+				       reg);</div><div class='add'>+		next_q_type = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK,</div><div class='add'>+					reg);</div><div class='ctx'> </div><div class='ctx'> 		if (qv_info-&gt;ceq_idx != I40E_QUEUE_INVALID_IDX) {</div><div class='ctx'> 			reg_idx = (msix_vf - 1) * vf-&gt;vf_id + qv_info-&gt;ceq_idx;</div><div class='hunk'>@@ -659,11 +685,9 @@ static int i40e_config_vsi_tx_queue(struct i40e_vf *vf, u16 vsi_id,</div><div class='ctx'> </div><div class='ctx'> 	/* associate this queue with the PCI VF function */</div><div class='ctx'> 	qtx_ctl = I40E_QTX_CTL_VF_QUEUE;</div><div class='del'>-	qtx_ctl |= ((hw-&gt;pf_id &lt;&lt; I40E_QTX_CTL_PF_INDX_SHIFT)</div><div class='del'>-		    &amp; I40E_QTX_CTL_PF_INDX_MASK);</div><div class='del'>-	qtx_ctl |= (((vf-&gt;vf_id + hw-&gt;func_caps.vf_base_id)</div><div class='del'>-		     &lt;&lt; I40E_QTX_CTL_VFVM_INDX_SHIFT)</div><div class='del'>-		    &amp; I40E_QTX_CTL_VFVM_INDX_MASK);</div><div class='add'>+	qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw-&gt;pf_id);</div><div class='add'>+	qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,</div><div class='add'>+			      vf-&gt;vf_id + hw-&gt;func_caps.vf_base_id);</div><div class='ctx'> 	wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl);</div><div class='ctx'> 	i40e_flush(hw);</div><div class='ctx'> </div><div class='hunk'>@@ -1808,7 +1832,7 @@ int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)</div><div class='ctx'> 	if (pci_num_vf(pf-&gt;pdev) != num_alloc_vfs) {</div><div class='ctx'> 		ret = pci_enable_sriov(pf-&gt;pdev, num_alloc_vfs);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			pf-&gt;flags &amp;= ~I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+			clear_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			pf-&gt;num_alloc_vfs = 0;</div><div class='ctx'> 			goto err_iov;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1919,8 +1943,8 @@ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (num_vfs) {</div><div class='del'>-		if (!(pf-&gt;flags &amp; I40E_FLAG_VEB_MODE_ENABLED)) {</div><div class='del'>-			pf-&gt;flags |= I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+		if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags)) {</div><div class='add'>+			set_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 			i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);</div><div class='ctx'> 		}</div><div class='ctx'> 		ret = i40e_pci_sriov_enable(pdev, num_vfs);</div><div class='hunk'>@@ -1929,7 +1953,7 @@ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)</div><div class='ctx'> </div><div class='ctx'> 	if (!pci_vfs_assigned(pf-&gt;pdev)) {</div><div class='ctx'> 		i40e_free_vfs(pf);</div><div class='del'>-		pf-&gt;flags &amp;= ~I40E_FLAG_VEB_MODE_ENABLED;</div><div class='add'>+		clear_bit(I40E_FLAG_VEB_MODE_ENA, pf-&gt;flags);</div><div class='ctx'> 		i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev_warn(&amp;pdev-&gt;dev, "Unable to free VFs because some are assigned to VMs.\n");</div><div class='hunk'>@@ -2137,14 +2161,14 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)</div><div class='ctx'> 	if (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_RSS_PF) {</div><div class='ctx'> 		vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_PF;</div><div class='ctx'> 	} else {</div><div class='del'>-		if ((pf-&gt;hw_features &amp; I40E_HW_RSS_AQ_CAPABLE) &amp;&amp;</div><div class='add'>+		if (test_bit(I40E_HW_CAP_RSS_AQ, pf-&gt;hw.caps) &amp;&amp;</div><div class='ctx'> 		    (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_RSS_AQ))</div><div class='ctx'> 			vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_AQ;</div><div class='ctx'> 		else</div><div class='ctx'> 			vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RSS_REG;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, pf-&gt;hw.caps)) {</div><div class='ctx'> 		if (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2)</div><div class='ctx'> 			vfres-&gt;vf_cap_flags |=</div><div class='ctx'> 				VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2;</div><div class='hunk'>@@ -2153,12 +2177,12 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)</div><div class='ctx'> 	if (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_ENCAP)</div><div class='ctx'> 		vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP;</div><div class='ctx'> </div><div class='del'>-	if ((pf-&gt;hw_features &amp; I40E_HW_OUTER_UDP_CSUM_CAPABLE) &amp;&amp;</div><div class='add'>+	if (test_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf-&gt;hw.caps) &amp;&amp;</div><div class='ctx'> 	    (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM))</div><div class='ctx'> 		vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM;</div><div class='ctx'> </div><div class='ctx'> 	if (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_RX_POLLING) {</div><div class='del'>-		if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) {</div><div class='add'>+		if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 			dev_err(&amp;pf-&gt;pdev-&gt;dev,</div><div class='ctx'> 				"VF %d requested polling mode: this feature is supported only when the device is running in single function per port (SFP) mode\n",</div><div class='ctx'> 				 vf-&gt;vf_id);</div><div class='hunk'>@@ -2168,7 +2192,7 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)</div><div class='ctx'> 		vfres-&gt;vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RX_POLLING;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;hw_features &amp; I40E_HW_WB_ON_ITR_CAPABLE) {</div><div class='add'>+	if (test_bit(I40E_HW_CAP_WB_ON_ITR, pf-&gt;hw.caps)) {</div><div class='ctx'> 		if (vf-&gt;driver_caps &amp; VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)</div><div class='ctx'> 			vfres-&gt;vf_cap_flags |=</div><div class='ctx'> 					VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;</div><div class='hunk'>@@ -2581,6 +2605,14 @@ static int i40e_vc_enable_queues_msg(struct i40e_vf *vf, u8 *msg)</div><div class='ctx'> 	int aq_ret = 0;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (vf-&gt;is_disabled_from_host) {</div><div class='add'>+		aq_ret = -EPERM;</div><div class='add'>+		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='add'>+			 "Admin has disabled VF %d, will not enable queues\n",</div><div class='add'>+			 vf-&gt;vf_id);</div><div class='add'>+		goto error_param;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!test_bit(I40E_VF_STATE_ACTIVE, &amp;vf-&gt;vf_states)) {</div><div class='ctx'> 		aq_ret = -EINVAL;</div><div class='ctx'> 		goto error_param;</div><div class='hunk'>@@ -3521,16 +3553,16 @@ static int i40e_validate_cloud_filter(struct i40e_vf *vf,</div><div class='ctx'> 	bool found = false;</div><div class='ctx'> 	int bkt;</div><div class='ctx'> </div><div class='del'>-	if (!tc_filter-&gt;action) {</div><div class='add'>+	if (tc_filter-&gt;action != VIRTCHNL_ACTION_TC_REDIRECT) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev,</div><div class='del'>-			 "VF %d: Currently ADq doesn't support Drop Action\n",</div><div class='del'>-			 vf-&gt;vf_id);</div><div class='add'>+			 "VF %d: ADQ doesn't support this action (%d)\n",</div><div class='add'>+			 vf-&gt;vf_id, tc_filter-&gt;action);</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* action_meta is TC number here to which the filter is applied */</div><div class='ctx'> 	if (!tc_filter-&gt;action_meta ||</div><div class='del'>-	    tc_filter-&gt;action_meta &gt; I40E_MAX_VF_VSI) {</div><div class='add'>+	    tc_filter-&gt;action_meta &gt; vf-&gt;num_tc) {</div><div class='ctx'> 		dev_info(&amp;pf-&gt;pdev-&gt;dev, "VF %d: Invalid TC number %u\n",</div><div class='ctx'> 			 vf-&gt;vf_id, tc_filter-&gt;action_meta);</div><div class='ctx'> 		goto err;</div><div class='hunk'>@@ -4675,9 +4707,8 @@ int i40e_ndo_get_vf_config(struct net_device *netdev,</div><div class='ctx'> </div><div class='ctx'> 	ivi-&gt;max_tx_rate = vf-&gt;tx_rate;</div><div class='ctx'> 	ivi-&gt;min_tx_rate = 0;</div><div class='del'>-	ivi-&gt;vlan = le16_to_cpu(vsi-&gt;info.pvid) &amp; I40E_VLAN_MASK;</div><div class='del'>-	ivi-&gt;qos = (le16_to_cpu(vsi-&gt;info.pvid) &amp; I40E_PRIORITY_MASK) &gt;&gt;</div><div class='del'>-		   I40E_VLAN_PRIORITY_SHIFT;</div><div class='add'>+	ivi-&gt;vlan = le16_get_bits(vsi-&gt;info.pvid, I40E_VLAN_MASK);</div><div class='add'>+	ivi-&gt;qos = le16_get_bits(vsi-&gt;info.pvid, I40E_PRIORITY_MASK);</div><div class='ctx'> 	if (vf-&gt;link_forced == false)</div><div class='ctx'> 		ivi-&gt;linkstate = IFLA_VF_LINK_STATE_AUTO;</div><div class='ctx'> 	else if (vf-&gt;link_up == true)</div><div class='hunk'>@@ -4708,9 +4739,12 @@ int i40e_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link)</div><div class='ctx'> 	struct i40e_link_status *ls = &amp;pf-&gt;hw.phy.link_info;</div><div class='ctx'> 	struct virtchnl_pf_event pfe;</div><div class='ctx'> 	struct i40e_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	struct i40e_vsi *vsi;</div><div class='add'>+	unsigned long q_map;</div><div class='ctx'> 	struct i40e_vf *vf;</div><div class='ctx'> 	int abs_vf_id;</div><div class='ctx'> 	int ret = 0;</div><div class='add'>+	int tmp;</div><div class='ctx'> </div><div class='ctx'> 	if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf-&gt;state)) {</div><div class='ctx'> 		dev_warn(&amp;pf-&gt;pdev-&gt;dev, "Unable to configure VFs, other operation is pending.\n");</div><div class='hunk'>@@ -4733,17 +4767,38 @@ int i40e_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link)</div><div class='ctx'> 	switch (link) {</div><div class='ctx'> 	case IFLA_VF_LINK_STATE_AUTO:</div><div class='ctx'> 		vf-&gt;link_forced = false;</div><div class='add'>+		vf-&gt;is_disabled_from_host = false;</div><div class='add'>+		/* reset needed to reinit VF resources */</div><div class='add'>+		i40e_vc_reset_vf(vf, true);</div><div class='ctx'> 		i40e_set_vf_link_state(vf, &amp;pfe, ls);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IFLA_VF_LINK_STATE_ENABLE:</div><div class='ctx'> 		vf-&gt;link_forced = true;</div><div class='ctx'> 		vf-&gt;link_up = true;</div><div class='add'>+		vf-&gt;is_disabled_from_host = false;</div><div class='add'>+		/* reset needed to reinit VF resources */</div><div class='add'>+		i40e_vc_reset_vf(vf, true);</div><div class='ctx'> 		i40e_set_vf_link_state(vf, &amp;pfe, ls);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IFLA_VF_LINK_STATE_DISABLE:</div><div class='ctx'> 		vf-&gt;link_forced = true;</div><div class='ctx'> 		vf-&gt;link_up = false;</div><div class='ctx'> 		i40e_set_vf_link_state(vf, &amp;pfe, ls);</div><div class='add'>+</div><div class='add'>+		vsi = pf-&gt;vsi[vf-&gt;lan_vsi_idx];</div><div class='add'>+		q_map = BIT(vsi-&gt;num_queue_pairs) - 1;</div><div class='add'>+</div><div class='add'>+		vf-&gt;is_disabled_from_host = true;</div><div class='add'>+</div><div class='add'>+		/* Try to stop both Tx&amp;Rx rings even if one of the calls fails</div><div class='add'>+		 * to ensure we stop the rings even in case of errors.</div><div class='add'>+		 * If any of them returns with an error then the first</div><div class='add'>+		 * error that occurred will be returned.</div><div class='add'>+		 */</div><div class='add'>+		tmp = i40e_ctrl_vf_tx_rings(vsi, q_map, false);</div><div class='add'>+		ret = i40e_ctrl_vf_rx_rings(vsi, q_map, false);</div><div class='add'>+</div><div class='add'>+		ret = tmp ? tmp : ret;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ret = -EINVAL;</div><div class='hunk'>@@ -4843,7 +4898,7 @@ int i40e_ndo_set_vf_trust(struct net_device *netdev, int vf_id, bool setting)</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;flags &amp; I40E_FLAG_MFP_ENABLED) {</div><div class='add'>+	if (test_bit(I40E_FLAG_MFP_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		dev_err(&amp;pf-&gt;pdev-&gt;dev, "Trusted VF not supported in MFP mode.\n");</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto out;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h<br/>index 2ee0f8a23248..66f95e2f3146 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h</a></div><div class='hunk'>@@ -100,6 +100,7 @@ struct i40e_vf {</div><div class='ctx'> 	bool link_forced;</div><div class='ctx'> 	bool link_up;		/* only valid if VF link is forced */</div><div class='ctx'> 	bool spoofchk;</div><div class='add'>+	bool is_disabled_from_host; /* PF ctrl of VF enable/disable */</div><div class='ctx'> 	u16 num_vlan;</div><div class='ctx'> </div><div class='ctx'> 	/* ADq related variables */</div><div class='hunk'>@@ -137,6 +138,9 @@ int i40e_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_id, bool enable);</div><div class='ctx'> </div><div class='ctx'> void i40e_vc_notify_link_state(struct i40e_pf *pf);</div><div class='ctx'> void i40e_vc_notify_reset(struct i40e_pf *pf);</div><div class='add'>+#ifdef CONFIG_PCI_IOV</div><div class='add'>+void i40e_restore_all_vfs_msi_state(struct pci_dev *pdev);</div><div class='add'>+#endif /* CONFIG_PCI_IOV */</div><div class='ctx'> int i40e_get_vf_stats(struct net_device *netdev, int vf_id,</div><div class='ctx'> 		      struct ifla_vf_stats *vf_stats);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/i40e/i40e_xsk.c b/drivers/net/ethernet/intel/i40e/i40e_xsk.c<br/>index e99fa854d17f..af7d5fa6cdc1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_xsk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/i40e/i40e_xsk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/i40e/i40e_xsk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/i40e/i40e_xsk.c</a></div><div class='hunk'>@@ -476,8 +476,7 @@ int i40e_clean_rx_irq_zc(struct i40e_ring *rx_ring, int budget)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		size = (qword &amp; I40E_RXD_QW1_LENGTH_PBUF_MASK) &gt;&gt;</div><div class='del'>-		       I40E_RXD_QW1_LENGTH_PBUF_SHIFT;</div><div class='add'>+		size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword);</div><div class='ctx'> 		if (!size)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf.h b/drivers/net/ethernet/intel/iavf/iavf.h<br/>index e7ab89dc883a..db8188c7ac4b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf.h</a></div><div class='hunk'>@@ -292,6 +292,7 @@ struct iavf_adapter {</div><div class='ctx'> #define IAVF_FLAG_QUEUES_DISABLED		BIT(17)</div><div class='ctx'> #define IAVF_FLAG_SETUP_NETDEV_FEATURES		BIT(18)</div><div class='ctx'> #define IAVF_FLAG_REINIT_MSIX_NEEDED		BIT(20)</div><div class='add'>+#define IAVF_FLAG_FDIR_ENABLED			BIT(21)</div><div class='ctx'> /* duplicates for common code */</div><div class='ctx'> #define IAVF_FLAG_DCB_ENABLED			0</div><div class='ctx'> 	/* flags for admin queue service task */</div><div class='hunk'>@@ -312,7 +313,8 @@ struct iavf_adapter {</div><div class='ctx'> #define IAVF_FLAG_AQ_SET_HENA			BIT_ULL(12)</div><div class='ctx'> #define IAVF_FLAG_AQ_SET_RSS_KEY		BIT_ULL(13)</div><div class='ctx'> #define IAVF_FLAG_AQ_SET_RSS_LUT		BIT_ULL(14)</div><div class='del'>-#define IAVF_FLAG_AQ_CONFIGURE_PROMISC_MODE	BIT_ULL(15)</div><div class='add'>+#define IAVF_FLAG_AQ_SET_RSS_HFUNC		BIT_ULL(15)</div><div class='add'>+#define IAVF_FLAG_AQ_CONFIGURE_PROMISC_MODE	BIT_ULL(16)</div><div class='ctx'> #define IAVF_FLAG_AQ_ENABLE_VLAN_STRIPPING	BIT_ULL(19)</div><div class='ctx'> #define IAVF_FLAG_AQ_DISABLE_VLAN_STRIPPING	BIT_ULL(20)</div><div class='ctx'> #define IAVF_FLAG_AQ_ENABLE_CHANNELS		BIT_ULL(21)</div><div class='hunk'>@@ -414,6 +416,7 @@ struct iavf_adapter {</div><div class='ctx'> 	struct iavf_vsi vsi;</div><div class='ctx'> 	u32 aq_wait_count;</div><div class='ctx'> 	/* RSS stuff */</div><div class='add'>+	enum virtchnl_rss_algorithm hfunc;</div><div class='ctx'> 	u64 hena;</div><div class='ctx'> 	u16 rss_key_size;</div><div class='ctx'> 	u16 rss_lut_size;</div><div class='hunk'>@@ -539,6 +542,7 @@ void iavf_get_hena(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_set_hena(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_set_rss_key(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_set_rss_lut(struct iavf_adapter *adapter);</div><div class='add'>+void iavf_set_rss_hfunc(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_enable_vlan_stripping(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_disable_vlan_stripping(struct iavf_adapter *adapter);</div><div class='ctx'> void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq.c b/drivers/net/ethernet/intel/iavf/iavf_adminq.c<br/>index 9ffbd24d83cb..82fcd18ad660 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adminq.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_adminq.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adminq.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adminq.c</a></div><div class='hunk'>@@ -8,27 +8,6 @@</div><div class='ctx'> #include "iavf_prototype.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- *  iavf_adminq_init_regs - Initialize AdminQ registers</div><div class='del'>- *  @hw: pointer to the hardware structure</div><div class='del'>- *</div><div class='del'>- *  This assumes the alloc_asq and alloc_arq functions have already been called</div><div class='del'>- **/</div><div class='del'>-static void iavf_adminq_init_regs(struct iavf_hw *hw)</div><div class='del'>-{</div><div class='del'>-	/* set head and tail registers in our local struct */</div><div class='del'>-	hw-&gt;aq.asq.tail = IAVF_VF_ATQT1;</div><div class='del'>-	hw-&gt;aq.asq.head = IAVF_VF_ATQH1;</div><div class='del'>-	hw-&gt;aq.asq.len  = IAVF_VF_ATQLEN1;</div><div class='del'>-	hw-&gt;aq.asq.bal  = IAVF_VF_ATQBAL1;</div><div class='del'>-	hw-&gt;aq.asq.bah  = IAVF_VF_ATQBAH1;</div><div class='del'>-	hw-&gt;aq.arq.tail = IAVF_VF_ARQT1;</div><div class='del'>-	hw-&gt;aq.arq.head = IAVF_VF_ARQH1;</div><div class='del'>-	hw-&gt;aq.arq.len  = IAVF_VF_ARQLEN1;</div><div class='del'>-	hw-&gt;aq.arq.bal  = IAVF_VF_ARQBAL1;</div><div class='del'>-	hw-&gt;aq.arq.bah  = IAVF_VF_ARQBAH1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  *  iavf_alloc_adminq_asq_ring - Allocate Admin Queue send rings</div><div class='ctx'>  *  @hw: pointer to the hardware structure</div><div class='ctx'>  **/</div><div class='hunk'>@@ -259,17 +238,17 @@ static enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)</div><div class='ctx'> 	u32 reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear Head and Tail */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.tail, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQH1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQT1, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* set starting point */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.len, (hw-&gt;aq.num_asq_entries |</div><div class='add'>+	wr32(hw, IAVF_VF_ATQLEN1, (hw-&gt;aq.num_asq_entries |</div><div class='ctx'> 				  IAVF_VF_ATQLEN1_ATQENABLE_MASK));</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bal, lower_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bah, upper_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='add'>+	wr32(hw, IAVF_VF_ATQBAL1, lower_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='add'>+	wr32(hw, IAVF_VF_ATQBAH1, upper_32_bits(hw-&gt;aq.asq.desc_buf.pa));</div><div class='ctx'> </div><div class='ctx'> 	/* Check one register to verify that config was applied */</div><div class='del'>-	reg = rd32(hw, hw-&gt;aq.asq.bal);</div><div class='add'>+	reg = rd32(hw, IAVF_VF_ATQBAL1);</div><div class='ctx'> 	if (reg != lower_32_bits(hw-&gt;aq.asq.desc_buf.pa))</div><div class='ctx'> 		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;</div><div class='ctx'> </div><div class='hunk'>@@ -288,20 +267,20 @@ static enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)</div><div class='ctx'> 	u32 reg = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear Head and Tail */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQH1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQT1, 0);</div><div class='ctx'> </div><div class='ctx'> 	/* set starting point */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.len, (hw-&gt;aq.num_arq_entries |</div><div class='add'>+	wr32(hw, IAVF_VF_ARQLEN1, (hw-&gt;aq.num_arq_entries |</div><div class='ctx'> 				  IAVF_VF_ARQLEN1_ARQENABLE_MASK));</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bal, lower_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bah, upper_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='add'>+	wr32(hw, IAVF_VF_ARQBAL1, lower_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='add'>+	wr32(hw, IAVF_VF_ARQBAH1, upper_32_bits(hw-&gt;aq.arq.desc_buf.pa));</div><div class='ctx'> </div><div class='ctx'> 	/* Update tail in the HW to post pre-allocated buffers */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, hw-&gt;aq.num_arq_entries - 1);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQT1, hw-&gt;aq.num_arq_entries - 1);</div><div class='ctx'> </div><div class='ctx'> 	/* Check one register to verify that config was applied */</div><div class='del'>-	reg = rd32(hw, hw-&gt;aq.arq.bal);</div><div class='add'>+	reg = rd32(hw, IAVF_VF_ARQBAL1);</div><div class='ctx'> 	if (reg != lower_32_bits(hw-&gt;aq.arq.desc_buf.pa))</div><div class='ctx'> 		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;</div><div class='ctx'> </div><div class='hunk'>@@ -455,11 +434,11 @@ static enum iavf_status iavf_shutdown_asq(struct iavf_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Stop firmware AdminQ processing */</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.tail, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.len, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bal, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.asq.bah, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQH1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQT1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQLEN1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQBAL1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ATQBAH1, 0);</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.asq.count = 0; /* to indicate uninitialized queue */</div><div class='ctx'> </div><div class='hunk'>@@ -489,11 +468,11 @@ static enum iavf_status iavf_shutdown_arq(struct iavf_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Stop firmware AdminQ processing */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.head, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.len, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bal, 0);</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.bah, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQH1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQT1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQLEN1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQBAL1, 0);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQBAH1, 0);</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.arq.count = 0; /* to indicate uninitialized queue */</div><div class='ctx'> </div><div class='hunk'>@@ -529,9 +508,6 @@ enum iavf_status iavf_init_adminq(struct iavf_hw *hw)</div><div class='ctx'> 		goto init_adminq_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Set up register offsets */</div><div class='del'>-	iavf_adminq_init_regs(hw);</div><div class='del'>-</div><div class='ctx'> 	/* setup ASQ command write back timeout */</div><div class='ctx'> 	hw-&gt;aq.asq_cmd_timeout = IAVF_ASQ_CMD_TIMEOUT;</div><div class='ctx'> </div><div class='hunk'>@@ -587,9 +563,9 @@ static u16 iavf_clean_asq(struct iavf_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	desc = IAVF_ADMINQ_DESC(*asq, ntc);</div><div class='ctx'> 	details = IAVF_ADMINQ_DETAILS(*asq, ntc);</div><div class='del'>-	while (rd32(hw, hw-&gt;aq.asq.head) != ntc) {</div><div class='add'>+	while (rd32(hw, IAVF_VF_ATQH1) != ntc) {</div><div class='ctx'> 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,</div><div class='del'>-			   "ntc %d head %d.\n", ntc, rd32(hw, hw-&gt;aq.asq.head));</div><div class='add'>+			   "ntc %d head %d.\n", ntc, rd32(hw, IAVF_VF_ATQH1));</div><div class='ctx'> </div><div class='ctx'> 		if (details-&gt;callback) {</div><div class='ctx'> 			IAVF_ADMINQ_CALLBACK cb_func =</div><div class='hunk'>@@ -624,7 +600,7 @@ bool iavf_asq_done(struct iavf_hw *hw)</div><div class='ctx'> 	/* AQ designers suggest use of head for better</div><div class='ctx'> 	 * timing reliability than DD bit</div><div class='ctx'> 	 */</div><div class='del'>-	return rd32(hw, hw-&gt;aq.asq.head) == hw-&gt;aq.asq.next_to_use;</div><div class='add'>+	return rd32(hw, IAVF_VF_ATQH1) == hw-&gt;aq.asq.next_to_use;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -663,7 +639,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;aq.asq_last_status = IAVF_AQ_RC_OK;</div><div class='ctx'> </div><div class='del'>-	val = rd32(hw, hw-&gt;aq.asq.head);</div><div class='add'>+	val = rd32(hw, IAVF_VF_ATQH1);</div><div class='ctx'> 	if (val &gt;= hw-&gt;aq.num_asq_entries) {</div><div class='ctx'> 		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,</div><div class='ctx'> 			   "AQTX: head overrun at %d\n", val);</div><div class='hunk'>@@ -755,7 +731,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,</div><div class='ctx'> 	if (hw-&gt;aq.asq.next_to_use == hw-&gt;aq.asq.count)</div><div class='ctx'> 		hw-&gt;aq.asq.next_to_use = 0;</div><div class='ctx'> 	if (!details-&gt;postpone)</div><div class='del'>-		wr32(hw, hw-&gt;aq.asq.tail, hw-&gt;aq.asq.next_to_use);</div><div class='add'>+		wr32(hw, IAVF_VF_ATQT1, hw-&gt;aq.asq.next_to_use);</div><div class='ctx'> </div><div class='ctx'> 	/* if cmd_details are not defined or async flag is not set,</div><div class='ctx'> 	 * we need to wait for desc write back</div><div class='hunk'>@@ -810,7 +786,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,</div><div class='ctx'> 	/* update the error if time out occurred */</div><div class='ctx'> 	if ((!cmd_completed) &amp;&amp;</div><div class='ctx'> 	    (!details-&gt;async &amp;&amp; !details-&gt;postpone)) {</div><div class='del'>-		if (rd32(hw, hw-&gt;aq.asq.len) &amp; IAVF_VF_ATQLEN1_ATQCRIT_MASK) {</div><div class='add'>+		if (rd32(hw, IAVF_VF_ATQLEN1) &amp; IAVF_VF_ATQLEN1_ATQCRIT_MASK) {</div><div class='ctx'> 			iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,</div><div class='ctx'> 				   "AQTX: AQ Critical error.\n");</div><div class='ctx'> 			status = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;</div><div class='hunk'>@@ -878,7 +854,7 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* set next_to_use to head */</div><div class='del'>-	ntu = rd32(hw, hw-&gt;aq.arq.head) &amp; IAVF_VF_ARQH1_ARQH_MASK;</div><div class='add'>+	ntu = rd32(hw, IAVF_VF_ARQH1) &amp; IAVF_VF_ARQH1_ARQH_MASK;</div><div class='ctx'> 	if (ntu == ntc) {</div><div class='ctx'> 		/* nothing to do - shouldn't need to update ring's values */</div><div class='ctx'> 		ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;</div><div class='hunk'>@@ -926,7 +902,7 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,</div><div class='ctx'> 	desc-&gt;params.external.addr_low = cpu_to_le32(lower_32_bits(bi-&gt;pa));</div><div class='ctx'> </div><div class='ctx'> 	/* set tail = the last cleaned desc index. */</div><div class='del'>-	wr32(hw, hw-&gt;aq.arq.tail, ntc);</div><div class='add'>+	wr32(hw, IAVF_VF_ARQT1, ntc);</div><div class='ctx'> 	/* ntc is updated to tail + 1 */</div><div class='ctx'> 	ntc++;</div><div class='ctx'> 	if (ntc == hw-&gt;aq.num_arq_entries)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_adminq.h b/drivers/net/ethernet/intel/iavf/iavf_adminq.h<br/>index 1f60518eb0e5..406506f64bdd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adminq.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_adminq.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adminq.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adminq.h</a></div><div class='hunk'>@@ -29,13 +29,6 @@ struct iavf_adminq_ring {</div><div class='ctx'> 	/* used for interrupt processing */</div><div class='ctx'> 	u16 next_to_use;</div><div class='ctx'> 	u16 next_to_clean;</div><div class='del'>-</div><div class='del'>-	/* used for queue tracking */</div><div class='del'>-	u32 head;</div><div class='del'>-	u32 tail;</div><div class='del'>-	u32 len;</div><div class='del'>-	u32 bah;</div><div class='del'>-	u32 bal;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ASQ transaction details */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_adv_rss.c b/drivers/net/ethernet/intel/iavf/iavf_adv_rss.c<br/>index 6edbf134b73f..a9e1da35e248 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adv_rss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adv_rss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.c</a></div><div class='hunk'>@@ -95,17 +95,21 @@ iavf_fill_adv_rss_sctp_hdr(struct virtchnl_proto_hdr *hdr, u64 hash_flds)</div><div class='ctx'>  * @rss_cfg: the virtchnl message to be filled with RSS configuration setting</div><div class='ctx'>  * @packet_hdrs: the RSS configuration protocol header types</div><div class='ctx'>  * @hash_flds: the RSS configuration protocol hash fields</div><div class='add'>+ * @symm: if true, symmetric hash is required</div><div class='ctx'>  *</div><div class='ctx'>  * Returns 0 if the RSS configuration virtchnl message is filled successfully</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='ctx'> iavf_fill_adv_rss_cfg_msg(struct virtchnl_rss_cfg *rss_cfg,</div><div class='del'>-			  u32 packet_hdrs, u64 hash_flds)</div><div class='add'>+			  u32 packet_hdrs, u64 hash_flds, bool symm)</div><div class='ctx'> {</div><div class='ctx'> 	struct virtchnl_proto_hdrs *proto_hdrs = &amp;rss_cfg-&gt;proto_hdrs;</div><div class='ctx'> 	struct virtchnl_proto_hdr *hdr;</div><div class='ctx'> </div><div class='del'>-	rss_cfg-&gt;rss_algorithm = VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC;</div><div class='add'>+	if (symm)</div><div class='add'>+		rss_cfg-&gt;rss_algorithm = VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC;</div><div class='add'>+	else</div><div class='add'>+		rss_cfg-&gt;rss_algorithm = VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC;</div><div class='ctx'> </div><div class='ctx'> 	proto_hdrs-&gt;tunnel_level = 0;	/* always outer layer */</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_adv_rss.h b/drivers/net/ethernet/intel/iavf/iavf_adv_rss.h<br/>index 4d3be11af7aa..e31eb2afebea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adv_rss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_adv_rss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_adv_rss.h</a></div><div class='hunk'>@@ -80,13 +80,14 @@ struct iavf_adv_rss {</div><div class='ctx'> </div><div class='ctx'> 	u32 packet_hdrs;</div><div class='ctx'> 	u64 hash_flds;</div><div class='add'>+	bool symm;</div><div class='ctx'> </div><div class='ctx'> 	struct virtchnl_rss_cfg cfg_msg;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int</div><div class='ctx'> iavf_fill_adv_rss_cfg_msg(struct virtchnl_rss_cfg *rss_cfg,</div><div class='del'>-			  u32 packet_hdrs, u64 hash_flds);</div><div class='add'>+			  u32 packet_hdrs, u64 hash_flds, bool symm);</div><div class='ctx'> struct iavf_adv_rss *</div><div class='ctx'> iavf_find_adv_rss_cfg_by_hdrs(struct iavf_adapter *adapter, u32 packet_hdrs);</div><div class='ctx'> void</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_common.c b/drivers/net/ethernet/intel/iavf/iavf_common.c<br/>index 8091e6feca01..5a25233a89d5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_common.c</a></div><div class='hunk'>@@ -1,10 +1,11 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/avf/virtchnl.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "iavf_type.h"</div><div class='ctx'> #include "iavf_adminq.h"</div><div class='ctx'> #include "iavf_prototype.h"</div><div class='del'>-#include &lt;linux/avf/virtchnl.h&gt;</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * iavf_aq_str - convert AQ err code to a string</div><div class='hunk'>@@ -279,11 +280,11 @@ void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc,</div><div class='ctx'>  **/</div><div class='ctx'> bool iavf_check_asq_alive(struct iavf_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	if (hw-&gt;aq.asq.len)</div><div class='del'>-		return !!(rd32(hw, hw-&gt;aq.asq.len) &amp;</div><div class='del'>-			  IAVF_VF_ATQLEN1_ATQENABLE_MASK);</div><div class='del'>-	else</div><div class='add'>+	/* Check if the queue is initialized */</div><div class='add'>+	if (!hw-&gt;aq.asq.count)</div><div class='ctx'> 		return false;</div><div class='add'>+</div><div class='add'>+	return !!(rd32(hw, IAVF_VF_ATQLEN1) &amp; IAVF_VF_ATQLEN1_ATQENABLE_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -330,6 +331,7 @@ static enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,</div><div class='ctx'> 	struct iavf_aq_desc desc;</div><div class='ctx'> 	struct iavf_aqc_get_set_rss_lut *cmd_resp =</div><div class='ctx'> 		   (struct iavf_aqc_get_set_rss_lut *)&amp;desc.params.raw;</div><div class='add'>+	u16 flags;</div><div class='ctx'> </div><div class='ctx'> 	if (set)</div><div class='ctx'> 		iavf_fill_default_direct_cmd_desc(&amp;desc,</div><div class='hunk'>@@ -342,22 +344,18 @@ static enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);</div><div class='ctx'> </div><div class='del'>-	cmd_resp-&gt;vsi_id =</div><div class='del'>-			cpu_to_le16((u16)((vsi_id &lt;&lt;</div><div class='del'>-					  IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &amp;</div><div class='del'>-					  IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK));</div><div class='del'>-	cmd_resp-&gt;vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_LUT_VSI_VALID);</div><div class='add'>+	vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |</div><div class='add'>+		 FIELD_PREP(IAVF_AQC_SET_RSS_LUT_VSI_VALID, 1);</div><div class='add'>+	cmd_resp-&gt;vsi_id = cpu_to_le16(vsi_id);</div><div class='ctx'> </div><div class='ctx'> 	if (pf_lut)</div><div class='del'>-		cmd_resp-&gt;flags |= cpu_to_le16((u16)</div><div class='del'>-					((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF &lt;&lt;</div><div class='del'>-					IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &amp;</div><div class='del'>-					IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));</div><div class='add'>+		flags = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,</div><div class='add'>+				   IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF);</div><div class='ctx'> 	else</div><div class='del'>-		cmd_resp-&gt;flags |= cpu_to_le16((u16)</div><div class='del'>-					((IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI &lt;&lt;</div><div class='del'>-					IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &amp;</div><div class='del'>-					IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));</div><div class='add'>+		flags = FIELD_PREP(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,</div><div class='add'>+				   IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI);</div><div class='add'>+</div><div class='add'>+	cmd_resp-&gt;flags = cpu_to_le16(flags);</div><div class='ctx'> </div><div class='ctx'> 	status = iavf_asq_send_command(hw, &amp;desc, lut, lut_size, NULL);</div><div class='ctx'> </div><div class='hunk'>@@ -411,11 +409,9 @@ iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw, u16 vsi_id,</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_BUF);</div><div class='ctx'> 	desc.flags |= cpu_to_le16((u16)IAVF_AQ_FLAG_RD);</div><div class='ctx'> </div><div class='del'>-	cmd_resp-&gt;vsi_id =</div><div class='del'>-			cpu_to_le16((u16)((vsi_id &lt;&lt;</div><div class='del'>-					  IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &amp;</div><div class='del'>-					  IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK));</div><div class='del'>-	cmd_resp-&gt;vsi_id |= cpu_to_le16((u16)IAVF_AQC_SET_RSS_KEY_VSI_VALID);</div><div class='add'>+	vsi_id = FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |</div><div class='add'>+		 FIELD_PREP(IAVF_AQC_SET_RSS_KEY_VSI_VALID, 1);</div><div class='add'>+	cmd_resp-&gt;vsi_id = cpu_to_le16(vsi_id);</div><div class='ctx'> </div><div class='ctx'> 	status = iavf_asq_send_command(hw, &amp;desc, key, key_size, NULL);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_ethtool.c b/drivers/net/ethernet/intel/iavf/iavf_ethtool.c<br/>index 6f236d1a6444..378c3e9ddf9d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_ethtool.c</a></div><div class='hunk'>@@ -1,11 +1,12 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/uaccess.h&gt;</div><div class='add'>+</div><div class='ctx'> /* ethtool support for iavf */</div><div class='ctx'> #include "iavf.h"</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/uaccess.h&gt;</div><div class='del'>-</div><div class='ctx'> /* ethtool statistics helpers */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -396,8 +397,7 @@ static void iavf_get_priv_flag_strings(struct net_device *netdev, u8 *data)</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IAVF_PRIV_FLAGS_STR_LEN; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s",</div><div class='del'>-				iavf_gstrings_priv_flags[i].flag_string);</div><div class='add'>+		ethtool_puts(&amp;data, iavf_gstrings_priv_flags[i].flag_string);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -827,18 +827,10 @@ static int __iavf_set_coalesce(struct net_device *netdev,</div><div class='ctx'> 	struct iavf_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (ec-&gt;rx_coalesce_usecs == 0) {</div><div class='del'>-		if (ec-&gt;use_adaptive_rx_coalesce)</div><div class='del'>-			netif_info(adapter, drv, netdev, "rx-usecs=0, need to disable adaptive-rx for a complete disable\n");</div><div class='del'>-	} else if ((ec-&gt;rx_coalesce_usecs &lt; IAVF_MIN_ITR) ||</div><div class='del'>-		   (ec-&gt;rx_coalesce_usecs &gt; IAVF_MAX_ITR)) {</div><div class='add'>+	if (ec-&gt;rx_coalesce_usecs &gt; IAVF_MAX_ITR) {</div><div class='ctx'> 		netif_info(adapter, drv, netdev, "Invalid value, rx-usecs range is 0-8160\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='del'>-	} else if (ec-&gt;tx_coalesce_usecs == 0) {</div><div class='del'>-		if (ec-&gt;use_adaptive_tx_coalesce)</div><div class='del'>-			netif_info(adapter, drv, netdev, "tx-usecs=0, need to disable adaptive-tx for a complete disable\n");</div><div class='del'>-	} else if ((ec-&gt;tx_coalesce_usecs &lt; IAVF_MIN_ITR) ||</div><div class='del'>-		   (ec-&gt;tx_coalesce_usecs &gt; IAVF_MAX_ITR)) {</div><div class='add'>+	} else if (ec-&gt;tx_coalesce_usecs &gt; IAVF_MAX_ITR) {</div><div class='ctx'> 		netif_info(adapter, drv, netdev, "Invalid value, tx-usecs range is 0-8160\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1025,8 +1017,7 @@ iavf_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,</div><div class='ctx'> #define IAVF_USERDEF_FLEX_MAX_OFFS_VAL 504</div><div class='ctx'> 		flex = &amp;fltr-&gt;flex_words[cnt++];</div><div class='ctx'> 		flex-&gt;word = value &amp; IAVF_USERDEF_FLEX_WORD_M;</div><div class='del'>-		flex-&gt;offset = (value &amp; IAVF_USERDEF_FLEX_OFFS_M) &gt;&gt;</div><div class='del'>-			     IAVF_USERDEF_FLEX_OFFS_S;</div><div class='add'>+		flex-&gt;offset = FIELD_GET(IAVF_USERDEF_FLEX_OFFS_M, value);</div><div class='ctx'> 		if (flex-&gt;offset &gt; IAVF_USERDEF_FLEX_MAX_OFFS_VAL)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1069,7 +1060,7 @@ iavf_get_ethtool_fdir_entry(struct iavf_adapter *adapter,</div><div class='ctx'> 	struct iavf_fdir_fltr *rule = NULL;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='del'>-	if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+	if (!(adapter-&gt;flags &amp; IAVF_FLAG_FDIR_ENABLED))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='hunk'>@@ -1211,7 +1202,7 @@ iavf_get_fdir_fltr_ids(struct iavf_adapter *adapter, struct ethtool_rxnfc *cmd,</div><div class='ctx'> 	unsigned int cnt = 0;</div><div class='ctx'> 	int val = 0;</div><div class='ctx'> </div><div class='del'>-	if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+	if (!(adapter-&gt;flags &amp; IAVF_FLAG_FDIR_ENABLED))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;data = IAVF_MAX_FDIR_FILTERS;</div><div class='hunk'>@@ -1403,7 +1394,7 @@ static int iavf_add_fdir_ethtool(struct iavf_adapter *adapter, struct ethtool_rx</div><div class='ctx'> 	int count = 50;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+	if (!(adapter-&gt;flags &amp; IAVF_FLAG_FDIR_ENABLED))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (fsp-&gt;flow_type &amp; FLOW_MAC_EXT)</div><div class='hunk'>@@ -1444,12 +1435,15 @@ static int iavf_add_fdir_ethtool(struct iavf_adapter *adapter, struct ethtool_rx</div><div class='ctx'> 	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> 	iavf_fdir_list_add_fltr(adapter, fltr);</div><div class='ctx'> 	adapter-&gt;fdir_active_fltr++;</div><div class='del'>-	fltr-&gt;state = IAVF_FDIR_FLTR_ADD_REQUEST;</div><div class='del'>-	adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_FDIR_FILTER;</div><div class='del'>-	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> </div><div class='del'>-	mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+	if (adapter-&gt;link_up)</div><div class='add'>+		fltr-&gt;state = IAVF_FDIR_FLTR_ADD_REQUEST;</div><div class='add'>+	else</div><div class='add'>+		fltr-&gt;state = IAVF_FDIR_FLTR_INACTIVE;</div><div class='add'>+	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> </div><div class='add'>+	if (adapter-&gt;link_up)</div><div class='add'>+		iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_FDIR_FILTER);</div><div class='ctx'> ret:</div><div class='ctx'> 	if (err &amp;&amp; fltr)</div><div class='ctx'> 		kfree(fltr);</div><div class='hunk'>@@ -1471,7 +1465,7 @@ static int iavf_del_fdir_ethtool(struct iavf_adapter *adapter, struct ethtool_rx</div><div class='ctx'> 	struct iavf_fdir_fltr *fltr = NULL;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+	if (!(adapter-&gt;flags &amp; IAVF_FLAG_FDIR_ENABLED))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='hunk'>@@ -1479,7 +1473,11 @@ static int iavf_del_fdir_ethtool(struct iavf_adapter *adapter, struct ethtool_rx</div><div class='ctx'> 	if (fltr) {</div><div class='ctx'> 		if (fltr-&gt;state == IAVF_FDIR_FLTR_ACTIVE) {</div><div class='ctx'> 			fltr-&gt;state = IAVF_FDIR_FLTR_DEL_REQUEST;</div><div class='del'>-			adapter-&gt;aq_required |= IAVF_FLAG_AQ_DEL_FDIR_FILTER;</div><div class='add'>+		} else if (fltr-&gt;state == IAVF_FDIR_FLTR_INACTIVE) {</div><div class='add'>+			list_del(&amp;fltr-&gt;list);</div><div class='add'>+			kfree(fltr);</div><div class='add'>+			adapter-&gt;fdir_active_fltr--;</div><div class='add'>+			fltr = NULL;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			err = -EBUSY;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1489,7 +1487,7 @@ static int iavf_del_fdir_ethtool(struct iavf_adapter *adapter, struct ethtool_rx</div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (fltr &amp;&amp; fltr-&gt;state == IAVF_FDIR_FLTR_DEL_REQUEST)</div><div class='del'>-		mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+		iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_DEL_FDIR_FILTER);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -1540,11 +1538,12 @@ static u32 iavf_adv_rss_parse_hdrs(struct ethtool_rxnfc *cmd)</div><div class='ctx'> /**</div><div class='ctx'>  * iavf_adv_rss_parse_hash_flds - parses hash fields from RSS hash input</div><div class='ctx'>  * @cmd: ethtool rxnfc command</div><div class='add'>+ * @symm: true if Symmetric Topelitz is set</div><div class='ctx'>  *</div><div class='ctx'>  * This function parses the rxnfc command and returns intended hash fields for</div><div class='ctx'>  * RSS configuration</div><div class='ctx'>  */</div><div class='del'>-static u64 iavf_adv_rss_parse_hash_flds(struct ethtool_rxnfc *cmd)</div><div class='add'>+static u64 iavf_adv_rss_parse_hash_flds(struct ethtool_rxnfc *cmd, bool symm)</div><div class='ctx'> {</div><div class='ctx'> 	u64 hfld = IAVF_ADV_RSS_HASH_INVALID;</div><div class='ctx'> </div><div class='hunk'>@@ -1616,17 +1615,20 @@ iavf_set_adv_rss_hash_opt(struct iavf_adapter *adapter,</div><div class='ctx'> 	struct iavf_adv_rss *rss_old, *rss_new;</div><div class='ctx'> 	bool rss_new_add = false;</div><div class='ctx'> 	int count = 50, err = 0;</div><div class='add'>+	bool symm = false;</div><div class='ctx'> 	u64 hash_flds;</div><div class='ctx'> 	u32 hdrs;</div><div class='ctx'> </div><div class='ctx'> 	if (!ADV_RSS_SUPPORT(adapter))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='add'>+	symm = !!(adapter-&gt;hfunc == VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC);</div><div class='add'>+</div><div class='ctx'> 	hdrs = iavf_adv_rss_parse_hdrs(cmd);</div><div class='ctx'> 	if (hdrs == IAVF_ADV_RSS_FLOW_SEG_HDR_NONE)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	hash_flds = iavf_adv_rss_parse_hash_flds(cmd);</div><div class='add'>+	hash_flds = iavf_adv_rss_parse_hash_flds(cmd, symm);</div><div class='ctx'> 	if (hash_flds == IAVF_ADV_RSS_HASH_INVALID)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -1634,7 +1636,8 @@ iavf_set_adv_rss_hash_opt(struct iavf_adapter *adapter,</div><div class='ctx'> 	if (!rss_new)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	if (iavf_fill_adv_rss_cfg_msg(&amp;rss_new-&gt;cfg_msg, hdrs, hash_flds)) {</div><div class='add'>+	if (iavf_fill_adv_rss_cfg_msg(&amp;rss_new-&gt;cfg_msg, hdrs, hash_flds,</div><div class='add'>+				      symm)) {</div><div class='ctx'> 		kfree(rss_new);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1653,12 +1656,13 @@ iavf_set_adv_rss_hash_opt(struct iavf_adapter *adapter,</div><div class='ctx'> 	if (rss_old) {</div><div class='ctx'> 		if (rss_old-&gt;state != IAVF_ADV_RSS_ACTIVE) {</div><div class='ctx'> 			err = -EBUSY;</div><div class='del'>-		} else if (rss_old-&gt;hash_flds != hash_flds) {</div><div class='add'>+		} else if (rss_old-&gt;hash_flds != hash_flds ||</div><div class='add'>+			   rss_old-&gt;symm != symm) {</div><div class='ctx'> 			rss_old-&gt;state = IAVF_ADV_RSS_ADD_REQUEST;</div><div class='ctx'> 			rss_old-&gt;hash_flds = hash_flds;</div><div class='add'>+			rss_old-&gt;symm = symm;</div><div class='ctx'> 			memcpy(&amp;rss_old-&gt;cfg_msg, &amp;rss_new-&gt;cfg_msg,</div><div class='ctx'> 			       sizeof(rss_new-&gt;cfg_msg));</div><div class='del'>-			adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_ADV_RSS_CFG;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			err = -EEXIST;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1667,13 +1671,13 @@ iavf_set_adv_rss_hash_opt(struct iavf_adapter *adapter,</div><div class='ctx'> 		rss_new-&gt;state = IAVF_ADV_RSS_ADD_REQUEST;</div><div class='ctx'> 		rss_new-&gt;packet_hdrs = hdrs;</div><div class='ctx'> 		rss_new-&gt;hash_flds = hash_flds;</div><div class='add'>+		rss_new-&gt;symm = symm;</div><div class='ctx'> 		list_add_tail(&amp;rss_new-&gt;list, &amp;adapter-&gt;adv_rss_list_head);</div><div class='del'>-		adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_ADV_RSS_CFG;</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;adv_rss_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (!err)</div><div class='del'>-		mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+		iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_ADV_RSS_CFG);</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;adapter-&gt;crit_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -1788,7 +1792,7 @@ static int iavf_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETHTOOL_GRXCLSRLCNT:</div><div class='del'>-		if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+		if (!(adapter-&gt;flags &amp; IAVF_FLAG_FDIR_ENABLED))</div><div class='ctx'> 			break;</div><div class='ctx'> 		spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> 		cmd-&gt;rule_cnt = adapter-&gt;fdir_active_fltr;</div><div class='hunk'>@@ -1907,27 +1911,27 @@ static u32 iavf_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> /**</div><div class='ctx'>  * iavf_get_rxfh - get the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function in use</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='ctx'>  *</div><div class='ctx'>  * Reads the indirection table directly from the hardware. Always returns 0.</div><div class='ctx'>  **/</div><div class='del'>-static int iavf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int iavf_get_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct iavf_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, adapter-&gt;rss_key, adapter-&gt;rss_key_size);</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (adapter-&gt;hfunc == VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC)</div><div class='add'>+		rxfh-&gt;input_xfrm |= RXH_XFRM_SYM_XOR;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, adapter-&gt;rss_key, adapter-&gt;rss_key_size);</div><div class='ctx'> </div><div class='del'>-	if (indir)</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='ctx'> 		/* Each 32 bits pointed by 'indir' is stored with a lut entry */</div><div class='ctx'> 		for (i = 0; i &lt; adapter-&gt;rss_lut_size; i++)</div><div class='del'>-			indir[i] = (u32)adapter-&gt;rss_lut[i];</div><div class='add'>+			rxfh-&gt;indir[i] = (u32)adapter-&gt;rss_lut[i];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1935,33 +1939,46 @@ static int iavf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> /**</div><div class='ctx'>  * iavf_set_rxfh - set the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function to use</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='add'>+ * @extack: extended ACK from the Netlink message</div><div class='ctx'>  *</div><div class='ctx'>  * Returns -EINVAL if the table specifies an invalid queue id, otherwise</div><div class='ctx'>  * returns 0 after programming the table.</div><div class='ctx'>  **/</div><div class='del'>-static int iavf_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int iavf_set_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct iavf_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	u16 i;</div><div class='ctx'> </div><div class='ctx'> 	/* Only support toeplitz hash function */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!key &amp;&amp; !indir)</div><div class='add'>+	if ((rxfh-&gt;input_xfrm &amp; RXH_XFRM_SYM_XOR) &amp;&amp;</div><div class='add'>+	    adapter-&gt;hfunc != VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC) {</div><div class='add'>+		if (!ADV_RSS_SUPPORT(adapter))</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		adapter-&gt;hfunc = VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC;</div><div class='add'>+		adapter-&gt;aq_required |= IAVF_FLAG_AQ_SET_RSS_HFUNC;</div><div class='add'>+	} else if (!(rxfh-&gt;input_xfrm &amp; RXH_XFRM_SYM_XOR) &amp;&amp;</div><div class='add'>+		    adapter-&gt;hfunc != VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC) {</div><div class='add'>+		adapter-&gt;hfunc = VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC;</div><div class='add'>+		adapter-&gt;aq_required |= IAVF_FLAG_AQ_SET_RSS_HFUNC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!rxfh-&gt;key &amp;&amp; !rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(adapter-&gt;rss_key, key, adapter-&gt;rss_key_size);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(adapter-&gt;rss_key, rxfh-&gt;key, adapter-&gt;rss_key_size);</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		/* Each 32 bits pointed by 'indir' is stored with a lut entry */</div><div class='ctx'> 		for (i = 0; i &lt; adapter-&gt;rss_lut_size; i++)</div><div class='del'>-			adapter-&gt;rss_lut[i] = (u8)(indir[i]);</div><div class='add'>+			adapter-&gt;rss_lut[i] = (u8)(rxfh-&gt;indir[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return iavf_config_rss(adapter);</div><div class='hunk'>@@ -1970,6 +1987,7 @@ static int iavf_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> static const struct ethtool_ops iavf_ethtool_ops = {</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE,</div><div class='add'>+	.cap_rss_sym_xor_supported = true,</div><div class='ctx'> 	.get_drvinfo		= iavf_get_drvinfo,</div><div class='ctx'> 	.get_link		= ethtool_op_get_link,</div><div class='ctx'> 	.get_ringparam		= iavf_get_ringparam,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_fdir.c b/drivers/net/ethernet/intel/iavf/iavf_fdir.c<br/>index 03e774bd2a5b..2d47b0b4640e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_fdir.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_fdir.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_fdir.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'> </div><div class='ctx'> /* flow director ethtool support for iavf */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "iavf.h"</div><div class='ctx'> </div><div class='ctx'> #define GTPU_PORT	2152</div><div class='hunk'>@@ -357,7 +358,7 @@ iavf_fill_fdir_ip6_hdr(struct iavf_fdir_fltr *fltr,</div><div class='ctx'> </div><div class='ctx'> 	if (fltr-&gt;ip_mask.tclass == U8_MAX) {</div><div class='ctx'> 		iph-&gt;priority = (fltr-&gt;ip_data.tclass &gt;&gt; 4) &amp; 0xF;</div><div class='del'>-		iph-&gt;flow_lbl[0] = (fltr-&gt;ip_data.tclass &lt;&lt; 4) &amp; 0xF0;</div><div class='add'>+		iph-&gt;flow_lbl[0] = FIELD_PREP(0xF0, fltr-&gt;ip_data.tclass);</div><div class='ctx'> 		VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, IPV6, TC);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_fdir.h b/drivers/net/ethernet/intel/iavf/iavf_fdir.h<br/>index 9eb9f73f6adf..d31bd923ba8c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_fdir.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_fdir.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_fdir.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_fdir.h</a></div><div class='hunk'>@@ -6,12 +6,25 @@</div><div class='ctx'> </div><div class='ctx'> struct iavf_adapter;</div><div class='ctx'> </div><div class='del'>-/* State of Flow Director filter */</div><div class='add'>+/* State of Flow Director filter</div><div class='add'>+ *</div><div class='add'>+ * *_REQUEST states are used to mark filter to be sent to PF driver to perform</div><div class='add'>+ * an action (either add or delete filter). *_PENDING states are an indication</div><div class='add'>+ * that request was sent to PF and the driver is waiting for response.</div><div class='add'>+ *</div><div class='add'>+ * Both DELETE and DISABLE states are being used to delete a filter in PF.</div><div class='add'>+ * The difference is that after a successful response filter in DEL_PENDING</div><div class='add'>+ * state is being deleted from VF driver as well and filter in DIS_PENDING state</div><div class='add'>+ * is being changed to INACTIVE state.</div><div class='add'>+ */</div><div class='ctx'> enum iavf_fdir_fltr_state_t {</div><div class='ctx'> 	IAVF_FDIR_FLTR_ADD_REQUEST,	/* User requests to add filter */</div><div class='ctx'> 	IAVF_FDIR_FLTR_ADD_PENDING,	/* Filter pending add by the PF */</div><div class='ctx'> 	IAVF_FDIR_FLTR_DEL_REQUEST,	/* User requests to delete filter */</div><div class='ctx'> 	IAVF_FDIR_FLTR_DEL_PENDING,	/* Filter pending delete by the PF */</div><div class='add'>+	IAVF_FDIR_FLTR_DIS_REQUEST,	/* Filter scheduled to be disabled */</div><div class='add'>+	IAVF_FDIR_FLTR_DIS_PENDING,	/* Filter pending disable by the PF */</div><div class='add'>+	IAVF_FDIR_FLTR_INACTIVE,	/* Filter inactive on link down */</div><div class='ctx'> 	IAVF_FDIR_FLTR_ACTIVE,		/* Filter is active */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_main.c b/drivers/net/ethernet/intel/iavf/iavf_main.c<br/>index c862ebcd2e39..335fd13e86f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_main.c</a></div><div class='hunk'>@@ -277,27 +277,6 @@ void iavf_free_virt_mem(struct iavf_hw *hw, struct iavf_virt_mem *mem)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * iavf_lock_timeout - try to lock mutex but give up after timeout</div><div class='del'>- * @lock: mutex that should be locked</div><div class='del'>- * @msecs: timeout in msecs</div><div class='del'>- *</div><div class='del'>- * Returns 0 on success, negative on failure</div><div class='del'>- **/</div><div class='del'>-static int iavf_lock_timeout(struct mutex *lock, unsigned int msecs)</div><div class='del'>-{</div><div class='del'>-	unsigned int wait, delay = 10;</div><div class='del'>-</div><div class='del'>-	for (wait = 0; wait &lt; msecs; wait += delay) {</div><div class='del'>-		if (mutex_trylock(lock))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-		msleep(delay);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * iavf_schedule_reset - Set the flags and schedule a reset event</div><div class='ctx'>  * @adapter: board private structure</div><div class='ctx'>  * @flags: IAVF_FLAG_RESET_PENDING or IAVF_FLAG_RESET_NEEDED</div><div class='hunk'>@@ -1059,13 +1038,12 @@ static int iavf_replace_primary_mac(struct iavf_adapter *adapter,</div><div class='ctx'> 	 */</div><div class='ctx'> 	new_f-&gt;is_primary = true;</div><div class='ctx'> 	new_f-&gt;add = true;</div><div class='del'>-	adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_MAC_FILTER;</div><div class='ctx'> 	ether_addr_copy(hw-&gt;mac.addr, new_mac);</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;mac_vlan_list_lock);</div><div class='ctx'> </div><div class='ctx'> 	/* schedule the watchdog task to immediately process the request */</div><div class='del'>-	mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+	iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ADD_MAC_FILTER);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1284,8 +1262,7 @@ static void iavf_up_complete(struct iavf_adapter *adapter)</div><div class='ctx'> </div><div class='ctx'> 	iavf_napi_enable_all(adapter);</div><div class='ctx'> </div><div class='del'>-	adapter-&gt;aq_required |= IAVF_FLAG_AQ_ENABLE_QUEUES;</div><div class='del'>-	mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+	iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_ENABLE_QUEUES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1353,18 +1330,20 @@ static void iavf_clear_cloud_filters(struct iavf_adapter *adapter)</div><div class='ctx'>  **/</div><div class='ctx'> static void iavf_clear_fdir_filters(struct iavf_adapter *adapter)</div><div class='ctx'> {</div><div class='del'>-	struct iavf_fdir_fltr *fdir, *fdirtmp;</div><div class='add'>+	struct iavf_fdir_fltr *fdir;</div><div class='ctx'> </div><div class='ctx'> 	/* remove all Flow Director filters */</div><div class='ctx'> 	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='del'>-	list_for_each_entry_safe(fdir, fdirtmp, &amp;adapter-&gt;fdir_list_head,</div><div class='del'>-				 list) {</div><div class='add'>+	list_for_each_entry(fdir, &amp;adapter-&gt;fdir_list_head, list) {</div><div class='ctx'> 		if (fdir-&gt;state == IAVF_FDIR_FLTR_ADD_REQUEST) {</div><div class='del'>-			list_del(&amp;fdir-&gt;list);</div><div class='del'>-			kfree(fdir);</div><div class='del'>-			adapter-&gt;fdir_active_fltr--;</div><div class='del'>-		} else {</div><div class='del'>-			fdir-&gt;state = IAVF_FDIR_FLTR_DEL_REQUEST;</div><div class='add'>+			/* Cancel a request, keep filter as inactive */</div><div class='add'>+			fdir-&gt;state = IAVF_FDIR_FLTR_INACTIVE;</div><div class='add'>+		} else if (fdir-&gt;state == IAVF_FDIR_FLTR_ADD_PENDING ||</div><div class='add'>+			 fdir-&gt;state == IAVF_FDIR_FLTR_ACTIVE) {</div><div class='add'>+			/* Disable filters which are active or have a pending</div><div class='add'>+			 * request to PF to be added</div><div class='add'>+			 */</div><div class='add'>+			fdir-&gt;state = IAVF_FDIR_FLTR_DIS_REQUEST;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='hunk'>@@ -1439,8 +1418,7 @@ void iavf_down(struct iavf_adapter *adapter)</div><div class='ctx'> 			adapter-&gt;aq_required |= IAVF_FLAG_AQ_DEL_ADV_RSS_CFG;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	adapter-&gt;aq_required |= IAVF_FLAG_AQ_DISABLE_QUEUES;</div><div class='del'>-	mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+	iavf_schedule_aq_request(adapter, IAVF_FLAG_AQ_DISABLE_QUEUES);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2169,6 +2147,10 @@ static int iavf_process_aq_command(struct iavf_adapter *adapter)</div><div class='ctx'> 		iavf_set_rss_lut(adapter);</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='add'>+	if (adapter-&gt;aq_required &amp; IAVF_FLAG_AQ_SET_RSS_HFUNC) {</div><div class='add'>+		iavf_set_rss_hfunc(adapter);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (adapter-&gt;aq_required &amp; IAVF_FLAG_AQ_CONFIGURE_PROMISC_MODE) {</div><div class='ctx'> 		iavf_set_promiscuous(adapter);</div><div class='hunk'>@@ -2337,10 +2319,8 @@ iavf_set_vlan_offload_features(struct iavf_adapter *adapter,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (aq_required) {</div><div class='del'>-		adapter-&gt;aq_required |= aq_required;</div><div class='del'>-		mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='del'>-	}</div><div class='add'>+	if (aq_required)</div><div class='add'>+		iavf_schedule_aq_request(adapter, aq_required);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3253,7 +3233,7 @@ static void iavf_adminq_task(struct work_struct *work)</div><div class='ctx'> 		goto freedom;</div><div class='ctx'> </div><div class='ctx'> 	/* check for error indications */</div><div class='del'>-	val = rd32(hw, hw-&gt;aq.arq.len);</div><div class='add'>+	val = rd32(hw, IAVF_VF_ARQLEN1);</div><div class='ctx'> 	if (val == 0xdeadbeef || val == 0xffffffff) /* device in reset */</div><div class='ctx'> 		goto freedom;</div><div class='ctx'> 	oldval = val;</div><div class='hunk'>@@ -3270,9 +3250,9 @@ static void iavf_adminq_task(struct work_struct *work)</div><div class='ctx'> 		val &amp;= ~IAVF_VF_ARQLEN1_ARQCRIT_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (oldval != val)</div><div class='del'>-		wr32(hw, hw-&gt;aq.arq.len, val);</div><div class='add'>+		wr32(hw, IAVF_VF_ARQLEN1, val);</div><div class='ctx'> </div><div class='del'>-	val = rd32(hw, hw-&gt;aq.asq.len);</div><div class='add'>+	val = rd32(hw, IAVF_VF_ATQLEN1);</div><div class='ctx'> 	oldval = val;</div><div class='ctx'> 	if (val &amp; IAVF_VF_ATQLEN1_ATQVFE_MASK) {</div><div class='ctx'> 		dev_info(&amp;adapter-&gt;pdev-&gt;dev, "ASQ VF Error detected\n");</div><div class='hunk'>@@ -3287,7 +3267,7 @@ static void iavf_adminq_task(struct work_struct *work)</div><div class='ctx'> 		val &amp;= ~IAVF_VF_ATQLEN1_ATQCRIT_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (oldval != val)</div><div class='del'>-		wr32(hw, hw-&gt;aq.asq.len, val);</div><div class='add'>+		wr32(hw, IAVF_VF_ATQLEN1, val);</div><div class='ctx'> </div><div class='ctx'> freedom:</div><div class='ctx'> 	kfree(event.msg_buf);</div><div class='hunk'>@@ -4113,6 +4093,33 @@ static int iavf_setup_tc(struct net_device *netdev, enum tc_setup_type type,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * iavf_restore_fdir_filters</div><div class='add'>+ * @adapter: board private structure</div><div class='add'>+ *</div><div class='add'>+ * Restore existing FDIR filters when VF netdev comes back up.</div><div class='add'>+ **/</div><div class='add'>+static void iavf_restore_fdir_filters(struct iavf_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	struct iavf_fdir_fltr *f;</div><div class='add'>+</div><div class='add'>+	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+	list_for_each_entry(f, &amp;adapter-&gt;fdir_list_head, list) {</div><div class='add'>+		if (f-&gt;state == IAVF_FDIR_FLTR_DIS_REQUEST) {</div><div class='add'>+			/* Cancel a request, keep filter as active */</div><div class='add'>+			f-&gt;state = IAVF_FDIR_FLTR_ACTIVE;</div><div class='add'>+		} else if (f-&gt;state == IAVF_FDIR_FLTR_DIS_PENDING ||</div><div class='add'>+			   f-&gt;state == IAVF_FDIR_FLTR_INACTIVE) {</div><div class='add'>+			/* Add filters which are inactive or have a pending</div><div class='add'>+			 * request to PF to be deleted</div><div class='add'>+			 */</div><div class='add'>+			f-&gt;state = IAVF_FDIR_FLTR_ADD_REQUEST;</div><div class='add'>+			adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_FDIR_FILTER;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * iavf_open - Called when a network interface is made active</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='ctx'>  *</div><div class='hunk'>@@ -4179,8 +4186,9 @@ static int iavf_open(struct net_device *netdev)</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;mac_vlan_list_lock);</div><div class='ctx'> </div><div class='del'>-	/* Restore VLAN filters that were removed with IFF_DOWN */</div><div class='add'>+	/* Restore filters that were removed with IFF_DOWN */</div><div class='ctx'> 	iavf_restore_filters(adapter);</div><div class='add'>+	iavf_restore_fdir_filters(adapter);</div><div class='ctx'> </div><div class='ctx'> 	iavf_configure(adapter);</div><div class='ctx'> </div><div class='hunk'>@@ -4311,6 +4319,49 @@ static int iavf_change_mtu(struct net_device *netdev, int new_mtu)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * iavf_disable_fdir - disable Flow Director and clear existing filters</div><div class='add'>+ * @adapter: board private structure</div><div class='add'>+ **/</div><div class='add'>+static void iavf_disable_fdir(struct iavf_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	struct iavf_fdir_fltr *fdir, *fdirtmp;</div><div class='add'>+	bool del_filters = false;</div><div class='add'>+</div><div class='add'>+	adapter-&gt;flags &amp;= ~IAVF_FLAG_FDIR_ENABLED;</div><div class='add'>+</div><div class='add'>+	/* remove all Flow Director filters */</div><div class='add'>+	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+	list_for_each_entry_safe(fdir, fdirtmp, &amp;adapter-&gt;fdir_list_head,</div><div class='add'>+				 list) {</div><div class='add'>+		if (fdir-&gt;state == IAVF_FDIR_FLTR_ADD_REQUEST ||</div><div class='add'>+		    fdir-&gt;state == IAVF_FDIR_FLTR_INACTIVE) {</div><div class='add'>+			/* Delete filters not registered in PF */</div><div class='add'>+			list_del(&amp;fdir-&gt;list);</div><div class='add'>+			kfree(fdir);</div><div class='add'>+			adapter-&gt;fdir_active_fltr--;</div><div class='add'>+		} else if (fdir-&gt;state == IAVF_FDIR_FLTR_ADD_PENDING ||</div><div class='add'>+			   fdir-&gt;state == IAVF_FDIR_FLTR_DIS_REQUEST ||</div><div class='add'>+			   fdir-&gt;state == IAVF_FDIR_FLTR_ACTIVE) {</div><div class='add'>+			/* Filters registered in PF, schedule their deletion */</div><div class='add'>+			fdir-&gt;state = IAVF_FDIR_FLTR_DEL_REQUEST;</div><div class='add'>+			del_filters = true;</div><div class='add'>+		} else if (fdir-&gt;state == IAVF_FDIR_FLTR_DIS_PENDING) {</div><div class='add'>+			/* Request to delete filter already sent to PF, change</div><div class='add'>+			 * state to DEL_PENDING to delete filter after PF's</div><div class='add'>+			 * response, not set as INACTIVE</div><div class='add'>+			 */</div><div class='add'>+			fdir-&gt;state = IAVF_FDIR_FLTR_DEL_PENDING;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+</div><div class='add'>+	if (del_filters) {</div><div class='add'>+		adapter-&gt;aq_required |= IAVF_FLAG_AQ_DEL_FDIR_FILTER;</div><div class='add'>+		mod_delayed_work(adapter-&gt;wq, &amp;adapter-&gt;watchdog_task, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define NETIF_VLAN_OFFLOAD_FEATURES	(NETIF_F_HW_VLAN_CTAG_RX | \</div><div class='ctx'> 					 NETIF_F_HW_VLAN_CTAG_TX | \</div><div class='ctx'> 					 NETIF_F_HW_VLAN_STAG_RX | \</div><div class='hunk'>@@ -4336,6 +4387,13 @@ static int iavf_set_features(struct net_device *netdev,</div><div class='ctx'> 	    ((netdev-&gt;features &amp; NETIF_F_RXFCS) ^ (features &amp; NETIF_F_RXFCS)))</div><div class='ctx'> 		iavf_schedule_reset(adapter, IAVF_FLAG_RESET_NEEDED);</div><div class='ctx'> </div><div class='add'>+	if ((netdev-&gt;features &amp; NETIF_F_NTUPLE) ^ (features &amp; NETIF_F_NTUPLE)) {</div><div class='add'>+		if (features &amp; NETIF_F_NTUPLE)</div><div class='add'>+			adapter-&gt;flags |= IAVF_FLAG_FDIR_ENABLED;</div><div class='add'>+		else</div><div class='add'>+			iavf_disable_fdir(adapter);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4685,6 +4743,9 @@ static netdev_features_t iavf_fix_features(struct net_device *netdev,</div><div class='ctx'> </div><div class='ctx'> 	features = iavf_fix_netdev_vlan_features(adapter, features);</div><div class='ctx'> </div><div class='add'>+	if (!FDIR_FLTR_SUPPORT(adapter))</div><div class='add'>+		features &amp;= ~NETIF_F_NTUPLE;</div><div class='add'>+</div><div class='ctx'> 	return iavf_fix_strip_features(adapter, features);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4802,6 +4863,12 @@ int iavf_process_config(struct iavf_adapter *adapter)</div><div class='ctx'> 	if (vfres-&gt;vf_cap_flags &amp; VIRTCHNL_VF_OFFLOAD_VLAN)</div><div class='ctx'> 		netdev-&gt;features |= NETIF_F_HW_VLAN_CTAG_FILTER;</div><div class='ctx'> </div><div class='add'>+	if (FDIR_FLTR_SUPPORT(adapter)) {</div><div class='add'>+		netdev-&gt;hw_features |= NETIF_F_NTUPLE;</div><div class='add'>+		netdev-&gt;features |= NETIF_F_NTUPLE;</div><div class='add'>+		adapter-&gt;flags |= IAVF_FLAG_FDIR_ENABLED;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	netdev-&gt;priv_flags |= IFF_UNICAST_FLT;</div><div class='ctx'> </div><div class='ctx'> 	/* Do not turn on offloads when they are requested to be turned off.</div><div class='hunk'>@@ -4826,34 +4893,6 @@ int iavf_process_config(struct iavf_adapter *adapter)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * iavf_shutdown - Shutdown the device in preparation for a reboot</div><div class='del'>- * @pdev: pci device structure</div><div class='del'>- **/</div><div class='del'>-static void iavf_shutdown(struct pci_dev *pdev)</div><div class='del'>-{</div><div class='del'>-	struct iavf_adapter *adapter = iavf_pdev_to_adapter(pdev);</div><div class='del'>-	struct net_device *netdev = adapter-&gt;netdev;</div><div class='del'>-</div><div class='del'>-	netif_device_detach(netdev);</div><div class='del'>-</div><div class='del'>-	if (netif_running(netdev))</div><div class='del'>-		iavf_close(netdev);</div><div class='del'>-</div><div class='del'>-	if (iavf_lock_timeout(&amp;adapter-&gt;crit_lock, 5000))</div><div class='del'>-		dev_warn(&amp;adapter-&gt;pdev-&gt;dev, "%s: failed to acquire crit_lock\n", __func__);</div><div class='del'>-	/* Prevent the watchdog from running. */</div><div class='del'>-	iavf_change_state(adapter, __IAVF_REMOVE);</div><div class='del'>-	adapter-&gt;aq_required = 0;</div><div class='del'>-	mutex_unlock(&amp;adapter-&gt;crit_lock);</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_PM</div><div class='del'>-	pci_save_state(pdev);</div><div class='del'>-</div><div class='del'>-#endif</div><div class='del'>-	pci_disable_device(pdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * iavf_probe - Device Initialization Routine</div><div class='ctx'>  * @pdev: PCI device information struct</div><div class='ctx'>  * @ent: entry in iavf_pci_tbl</div><div class='hunk'>@@ -5063,16 +5102,21 @@ static int __maybe_unused iavf_resume(struct device *dev_d)</div><div class='ctx'>  **/</div><div class='ctx'> static void iavf_remove(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='del'>-	struct iavf_adapter *adapter = iavf_pdev_to_adapter(pdev);</div><div class='ctx'> 	struct iavf_fdir_fltr *fdir, *fdirtmp;</div><div class='ctx'> 	struct iavf_vlan_filter *vlf, *vlftmp;</div><div class='ctx'> 	struct iavf_cloud_filter *cf, *cftmp;</div><div class='ctx'> 	struct iavf_adv_rss *rss, *rsstmp;</div><div class='ctx'> 	struct iavf_mac_filter *f, *ftmp;</div><div class='add'>+	struct iavf_adapter *adapter;</div><div class='ctx'> 	struct net_device *netdev;</div><div class='ctx'> 	struct iavf_hw *hw;</div><div class='ctx'> </div><div class='del'>-	netdev = adapter-&gt;netdev;</div><div class='add'>+	/* Don't proceed with remove if netdev is already freed */</div><div class='add'>+	netdev = pci_get_drvdata(pdev);</div><div class='add'>+	if (!netdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	adapter = iavf_pdev_to_adapter(pdev);</div><div class='ctx'> 	hw = &amp;adapter-&gt;hw;</div><div class='ctx'> </div><div class='ctx'> 	if (test_and_set_bit(__IAVF_IN_REMOVE_TASK, &amp;adapter-&gt;crit_section))</div><div class='hunk'>@@ -5184,11 +5228,25 @@ static void iavf_remove(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	destroy_workqueue(adapter-&gt;wq);</div><div class='ctx'> </div><div class='add'>+	pci_set_drvdata(pdev, NULL);</div><div class='add'>+</div><div class='ctx'> 	free_netdev(netdev);</div><div class='ctx'> </div><div class='ctx'> 	pci_disable_device(pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * iavf_shutdown - Shutdown the device in preparation for a reboot</div><div class='add'>+ * @pdev: pci device structure</div><div class='add'>+ **/</div><div class='add'>+static void iavf_shutdown(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	iavf_remove(pdev);</div><div class='add'>+</div><div class='add'>+	if (system_state == SYSTEM_POWER_OFF)</div><div class='add'>+		pci_set_power_state(pdev, PCI_D3hot);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static SIMPLE_DEV_PM_OPS(iavf_pm_ops, iavf_suspend, iavf_resume);</div><div class='ctx'> </div><div class='ctx'> static struct pci_driver iavf_driver = {</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_txrx.c b/drivers/net/ethernet/intel/iavf/iavf_txrx.c<br/>index d64c4997136b..b71484c87a84 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_txrx.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2013 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/prefetch.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "iavf.h"</div><div class='hunk'>@@ -988,11 +989,9 @@ static void iavf_rx_checksum(struct iavf_vsi *vsi,</div><div class='ctx'> 	u64 qword;</div><div class='ctx'> </div><div class='ctx'> 	qword = le64_to_cpu(rx_desc-&gt;wb.qword1.status_error_len);</div><div class='del'>-	ptype = (qword &amp; IAVF_RXD_QW1_PTYPE_MASK) &gt;&gt; IAVF_RXD_QW1_PTYPE_SHIFT;</div><div class='del'>-	rx_error = (qword &amp; IAVF_RXD_QW1_ERROR_MASK) &gt;&gt;</div><div class='del'>-		   IAVF_RXD_QW1_ERROR_SHIFT;</div><div class='del'>-	rx_status = (qword &amp; IAVF_RXD_QW1_STATUS_MASK) &gt;&gt;</div><div class='del'>-		    IAVF_RXD_QW1_STATUS_SHIFT;</div><div class='add'>+	ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);</div><div class='add'>+	rx_error = FIELD_GET(IAVF_RXD_QW1_ERROR_MASK, qword);</div><div class='add'>+	rx_status = FIELD_GET(IAVF_RXD_QW1_STATUS_MASK, qword);</div><div class='ctx'> 	decoded = decode_rx_desc_ptype(ptype);</div><div class='ctx'> </div><div class='ctx'> 	skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='hunk'>@@ -1533,8 +1532,7 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)</div><div class='ctx'> 		if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD))</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='del'>-		size = (qword &amp; IAVF_RXD_QW1_LENGTH_PBUF_MASK) &gt;&gt;</div><div class='del'>-		       IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;</div><div class='add'>+		size = FIELD_GET(IAVF_RXD_QW1_LENGTH_PBUF_MASK, qword);</div><div class='ctx'> </div><div class='ctx'> 		iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb);</div><div class='ctx'> 		rx_buffer = iavf_get_rx_buffer(rx_ring, size);</div><div class='hunk'>@@ -1581,8 +1579,7 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)</div><div class='ctx'> 		total_rx_bytes += skb-&gt;len;</div><div class='ctx'> </div><div class='ctx'> 		qword = le64_to_cpu(rx_desc-&gt;wb.qword1.status_error_len);</div><div class='del'>-		rx_ptype = (qword &amp; IAVF_RXD_QW1_PTYPE_MASK) &gt;&gt;</div><div class='del'>-			   IAVF_RXD_QW1_PTYPE_SHIFT;</div><div class='add'>+		rx_ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);</div><div class='ctx'> </div><div class='ctx'> 		/* populate checksum, VLAN, and protocol */</div><div class='ctx'> 		iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);</div><div class='hunk'>@@ -2290,8 +2287,7 @@ static void iavf_tx_map(struct iavf_ring *tx_ring, struct sk_buff *skb,</div><div class='ctx'> </div><div class='ctx'> 	if (tx_flags &amp; IAVF_TX_FLAGS_HW_VLAN) {</div><div class='ctx'> 		td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;</div><div class='del'>-		td_tag = (tx_flags &amp; IAVF_TX_FLAGS_VLAN_MASK) &gt;&gt;</div><div class='del'>-			 IAVF_TX_FLAGS_VLAN_SHIFT;</div><div class='add'>+		td_tag = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	first-&gt;tx_flags = tx_flags;</div><div class='hunk'>@@ -2467,8 +2463,7 @@ static netdev_tx_t iavf_xmit_frame_ring(struct sk_buff *skb,</div><div class='ctx'> 	if (tx_flags &amp; IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN) {</div><div class='ctx'> 		cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2 &lt;&lt;</div><div class='ctx'> 			IAVF_TXD_CTX_QW1_CMD_SHIFT;</div><div class='del'>-		cd_l2tag2 = (tx_flags &amp; IAVF_TX_FLAGS_VLAN_MASK) &gt;&gt;</div><div class='del'>-			IAVF_TX_FLAGS_VLAN_SHIFT;</div><div class='add'>+		cd_l2tag2 = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* obtain protocol of skb */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_txrx.h b/drivers/net/ethernet/intel/iavf/iavf_txrx.h<br/>index 7e6ee32d19b6..10ba36602c0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_txrx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_txrx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_txrx.h</a></div><div class='hunk'>@@ -15,7 +15,6 @@</div><div class='ctx'>  */</div><div class='ctx'> #define IAVF_ITR_DYNAMIC	0x8000	/* use top bit as a flag */</div><div class='ctx'> #define IAVF_ITR_MASK		0x1FFE	/* mask for ITR register value */</div><div class='del'>-#define IAVF_MIN_ITR		     2	/* reg uses 2 usec resolution */</div><div class='ctx'> #define IAVF_ITR_100K		    10	/* all values below must be even */</div><div class='ctx'> #define IAVF_ITR_50K		    20</div><div class='ctx'> #define IAVF_ITR_20K		    50</div><div class='head'>diff --git a/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c b/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c<br/>index 64c4443dbef9..22f2df7c460b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/iavf/iavf_virtchnl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/iavf/iavf_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/iavf/iavf_virtchnl.c</a></div><div class='hunk'>@@ -1142,6 +1142,34 @@ void iavf_set_rss_lut(struct iavf_adapter *adapter)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * iavf_set_rss_hfunc</div><div class='add'>+ * @adapter: adapter structure</div><div class='add'>+ *</div><div class='add'>+ * Request the PF to set our RSS Hash function</div><div class='add'>+ **/</div><div class='add'>+void iavf_set_rss_hfunc(struct iavf_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	struct virtchnl_rss_hfunc *vrh;</div><div class='add'>+	int len = sizeof(*vrh);</div><div class='add'>+</div><div class='add'>+	if (adapter-&gt;current_op != VIRTCHNL_OP_UNKNOWN) {</div><div class='add'>+		/* bail because we already have a command pending */</div><div class='add'>+		dev_err(&amp;adapter-&gt;pdev-&gt;dev, "Cannot set RSS Hash function, command %d pending\n",</div><div class='add'>+			adapter-&gt;current_op);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	vrh = kzalloc(len, GFP_KERNEL);</div><div class='add'>+	if (!vrh)</div><div class='add'>+		return;</div><div class='add'>+	vrh-&gt;vsi_id = adapter-&gt;vsi.id;</div><div class='add'>+	vrh-&gt;rss_algorithm = adapter-&gt;hfunc;</div><div class='add'>+	adapter-&gt;current_op = VIRTCHNL_OP_CONFIG_RSS_HFUNC;</div><div class='add'>+	adapter-&gt;aq_required &amp;= ~IAVF_FLAG_AQ_SET_RSS_HFUNC;</div><div class='add'>+	iavf_send_pf_msg(adapter, VIRTCHNL_OP_CONFIG_RSS_HFUNC, (u8 *)vrh, len);</div><div class='add'>+	kfree(vrh);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * iavf_enable_vlan_stripping</div><div class='ctx'>  * @adapter: adapter structure</div><div class='ctx'>  *</div><div class='hunk'>@@ -1735,8 +1763,8 @@ void iavf_add_fdir_filter(struct iavf_adapter *adapter)</div><div class='ctx'>  **/</div><div class='ctx'> void iavf_del_fdir_filter(struct iavf_adapter *adapter)</div><div class='ctx'> {</div><div class='add'>+	struct virtchnl_fdir_del f = {};</div><div class='ctx'> 	struct iavf_fdir_fltr *fdir;</div><div class='del'>-	struct virtchnl_fdir_del f;</div><div class='ctx'> 	bool process_fltr = false;</div><div class='ctx'> 	int len;</div><div class='ctx'> </div><div class='hunk'>@@ -1753,11 +1781,16 @@ void iavf_del_fdir_filter(struct iavf_adapter *adapter)</div><div class='ctx'> 	list_for_each_entry(fdir, &amp;adapter-&gt;fdir_list_head, list) {</div><div class='ctx'> 		if (fdir-&gt;state == IAVF_FDIR_FLTR_DEL_REQUEST) {</div><div class='ctx'> 			process_fltr = true;</div><div class='del'>-			memset(&amp;f, 0, len);</div><div class='ctx'> 			f.vsi_id = fdir-&gt;vc_add_msg.vsi_id;</div><div class='ctx'> 			f.flow_id = fdir-&gt;flow_id;</div><div class='ctx'> 			fdir-&gt;state = IAVF_FDIR_FLTR_DEL_PENDING;</div><div class='ctx'> 			break;</div><div class='add'>+		} else if (fdir-&gt;state == IAVF_FDIR_FLTR_DIS_REQUEST) {</div><div class='add'>+			process_fltr = true;</div><div class='add'>+			f.vsi_id = fdir-&gt;vc_add_msg.vsi_id;</div><div class='add'>+			f.flow_id = fdir-&gt;flow_id;</div><div class='add'>+			fdir-&gt;state = IAVF_FDIR_FLTR_DIS_PENDING;</div><div class='add'>+			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='hunk'>@@ -1902,6 +1935,48 @@ static void iavf_netdev_features_vlan_strip_set(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * iavf_activate_fdir_filters - Reactivate all FDIR filters after a reset</div><div class='add'>+ * @adapter: private adapter structure</div><div class='add'>+ *</div><div class='add'>+ * Called after a reset to re-add all FDIR filters and delete some of them</div><div class='add'>+ * if they were pending to be deleted.</div><div class='add'>+ */</div><div class='add'>+static void iavf_activate_fdir_filters(struct iavf_adapter *adapter)</div><div class='add'>+{</div><div class='add'>+	struct iavf_fdir_fltr *f, *ftmp;</div><div class='add'>+	bool add_filters = false;</div><div class='add'>+</div><div class='add'>+	spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+	list_for_each_entry_safe(f, ftmp, &amp;adapter-&gt;fdir_list_head, list) {</div><div class='add'>+		if (f-&gt;state == IAVF_FDIR_FLTR_ADD_REQUEST ||</div><div class='add'>+		    f-&gt;state == IAVF_FDIR_FLTR_ADD_PENDING ||</div><div class='add'>+		    f-&gt;state == IAVF_FDIR_FLTR_ACTIVE) {</div><div class='add'>+			/* All filters and requests have been removed in PF,</div><div class='add'>+			 * restore them</div><div class='add'>+			 */</div><div class='add'>+			f-&gt;state = IAVF_FDIR_FLTR_ADD_REQUEST;</div><div class='add'>+			add_filters = true;</div><div class='add'>+		} else if (f-&gt;state == IAVF_FDIR_FLTR_DIS_REQUEST ||</div><div class='add'>+			   f-&gt;state == IAVF_FDIR_FLTR_DIS_PENDING) {</div><div class='add'>+			/* Link down state, leave filters as inactive */</div><div class='add'>+			f-&gt;state = IAVF_FDIR_FLTR_INACTIVE;</div><div class='add'>+		} else if (f-&gt;state == IAVF_FDIR_FLTR_DEL_REQUEST ||</div><div class='add'>+			   f-&gt;state == IAVF_FDIR_FLTR_DEL_PENDING) {</div><div class='add'>+			/* Delete filters that were pending to be deleted, the</div><div class='add'>+			 * list on PF is already cleared after a reset</div><div class='add'>+			 */</div><div class='add'>+			list_del(&amp;f-&gt;list);</div><div class='add'>+			kfree(f);</div><div class='add'>+			adapter-&gt;fdir_active_fltr--;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='add'>+</div><div class='add'>+	if (add_filters)</div><div class='add'>+		adapter-&gt;aq_required |= IAVF_FLAG_AQ_ADD_FDIR_FILTER;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * iavf_virtchnl_completion</div><div class='ctx'>  * @adapter: adapter structure</div><div class='ctx'>  * @v_opcode: opcode sent by PF</div><div class='hunk'>@@ -2078,7 +2153,8 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='ctx'> 			spin_lock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='ctx'> 			list_for_each_entry(fdir, &amp;adapter-&gt;fdir_list_head,</div><div class='ctx'> 					    list) {</div><div class='del'>-				if (fdir-&gt;state == IAVF_FDIR_FLTR_DEL_PENDING) {</div><div class='add'>+				if (fdir-&gt;state == IAVF_FDIR_FLTR_DEL_PENDING ||</div><div class='add'>+				    fdir-&gt;state == IAVF_FDIR_FLTR_DIS_PENDING) {</div><div class='ctx'> 					fdir-&gt;state = IAVF_FDIR_FLTR_ACTIVE;</div><div class='ctx'> 					dev_info(&amp;adapter-&gt;pdev-&gt;dev, "Failed to del Flow Director filter, error %s\n",</div><div class='ctx'> 						 iavf_stat_str(&amp;adapter-&gt;hw,</div><div class='hunk'>@@ -2142,6 +2218,19 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='ctx'> 			dev_warn(&amp;adapter-&gt;pdev-&gt;dev, "Failed to add VLAN filter, error %s\n",</div><div class='ctx'> 				 iavf_stat_str(&amp;adapter-&gt;hw, v_retval));</div><div class='ctx'> 			break;</div><div class='add'>+		case VIRTCHNL_OP_CONFIG_RSS_HFUNC:</div><div class='add'>+			dev_warn(&amp;adapter-&gt;pdev-&gt;dev, "Failed to configure hash function, error %s\n",</div><div class='add'>+				 iavf_stat_str(&amp;adapter-&gt;hw, v_retval));</div><div class='add'>+</div><div class='add'>+			if (adapter-&gt;hfunc ==</div><div class='add'>+					VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC)</div><div class='add'>+				adapter-&gt;hfunc =</div><div class='add'>+					VIRTCHNL_RSS_ALG_TOEPLITZ_ASYMMETRIC;</div><div class='add'>+			else</div><div class='add'>+				adapter-&gt;hfunc =</div><div class='add'>+					VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC;</div><div class='add'>+</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			dev_err(&amp;adapter-&gt;pdev-&gt;dev, "PF returned error %d (%s) to our request %d\n",</div><div class='ctx'> 				v_retval, iavf_stat_str(&amp;adapter-&gt;hw, v_retval),</div><div class='hunk'>@@ -2214,6 +2303,8 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='ctx'> </div><div class='ctx'> 		spin_unlock_bh(&amp;adapter-&gt;mac_vlan_list_lock);</div><div class='ctx'> </div><div class='add'>+		iavf_activate_fdir_filters(adapter);</div><div class='add'>+</div><div class='ctx'> 		iavf_parse_vf_resource_msg(adapter);</div><div class='ctx'> </div><div class='ctx'> 		/* negotiated VIRTCHNL_VF_OFFLOAD_VLAN_V2, so wait for the</div><div class='hunk'>@@ -2390,7 +2481,9 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='ctx'> 		list_for_each_entry_safe(fdir, fdir_tmp, &amp;adapter-&gt;fdir_list_head,</div><div class='ctx'> 					 list) {</div><div class='ctx'> 			if (fdir-&gt;state == IAVF_FDIR_FLTR_DEL_PENDING) {</div><div class='del'>-				if (del_fltr-&gt;status == VIRTCHNL_FDIR_SUCCESS) {</div><div class='add'>+				if (del_fltr-&gt;status == VIRTCHNL_FDIR_SUCCESS ||</div><div class='add'>+				    del_fltr-&gt;status ==</div><div class='add'>+				    VIRTCHNL_FDIR_FAILURE_RULE_NONEXIST) {</div><div class='ctx'> 					dev_info(&amp;adapter-&gt;pdev-&gt;dev, "Flow Director filter with location %u is deleted\n",</div><div class='ctx'> 						 fdir-&gt;loc);</div><div class='ctx'> 					list_del(&amp;fdir-&gt;list);</div><div class='hunk'>@@ -2402,6 +2495,17 @@ void iavf_virtchnl_completion(struct iavf_adapter *adapter,</div><div class='ctx'> 						 del_fltr-&gt;status);</div><div class='ctx'> 					iavf_print_fdir_fltr(adapter, fdir);</div><div class='ctx'> 				}</div><div class='add'>+			} else if (fdir-&gt;state == IAVF_FDIR_FLTR_DIS_PENDING) {</div><div class='add'>+				if (del_fltr-&gt;status == VIRTCHNL_FDIR_SUCCESS ||</div><div class='add'>+				    del_fltr-&gt;status ==</div><div class='add'>+				    VIRTCHNL_FDIR_FAILURE_RULE_NONEXIST) {</div><div class='add'>+					fdir-&gt;state = IAVF_FDIR_FLTR_INACTIVE;</div><div class='add'>+				} else {</div><div class='add'>+					fdir-&gt;state = IAVF_FDIR_FLTR_ACTIVE;</div><div class='add'>+					dev_info(&amp;adapter-&gt;pdev-&gt;dev, "Failed to disable Flow Director filter with status: %d\n",</div><div class='add'>+						 del_fltr-&gt;status);</div><div class='add'>+					iavf_print_fdir_fltr(adapter, fdir);</div><div class='add'>+				}</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 		spin_unlock_bh(&amp;adapter-&gt;fdir_fltr_lock);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile<br/>index 0679907980f7..cddd82d4ca0f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/Makefile</a></div><div class='hunk'>@@ -34,7 +34,9 @@ ice-y := ice_main.o	\</div><div class='ctx'> 	 ice_lag.o	\</div><div class='ctx'> 	 ice_ethtool.o  \</div><div class='ctx'> 	 ice_repr.o	\</div><div class='del'>-	 ice_tc_lib.o</div><div class='add'>+	 ice_tc_lib.o	\</div><div class='add'>+	 ice_fwlog.o	\</div><div class='add'>+	 ice_debugfs.o</div><div class='ctx'> ice-$(CONFIG_PCI_IOV) +=	\</div><div class='ctx'> 	ice_sriov.o		\</div><div class='ctx'> 	ice_virtchnl.o		\</div><div class='hunk'>@@ -49,3 +51,4 @@ ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o</div><div class='ctx'> ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o</div><div class='ctx'> ice-$(CONFIG_ICE_SWITCHDEV) += ice_eswitch.o ice_eswitch_br.o</div><div class='ctx'> ice-$(CONFIG_GNSS) += ice_gnss.o</div><div class='add'>+ice-$(CONFIG_ICE_HWMON) += ice_hwmon.o</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h<br/>index 351e0d36df44..367b613d92c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice.h</a></div><div class='hunk'>@@ -360,6 +360,7 @@ struct ice_vsi {</div><div class='ctx'> 	/* RSS config */</div><div class='ctx'> 	u16 rss_table_size;	/* HW RSS table size */</div><div class='ctx'> 	u16 rss_size;		/* Allocated RSS queues */</div><div class='add'>+	u8 rss_hfunc;		/* User configured hash type */</div><div class='ctx'> 	u8 *rss_hkey_user;	/* User configured hash keys */</div><div class='ctx'> 	u8 *rss_lut_user;	/* User configured lookup table entries */</div><div class='ctx'> 	u8 rss_lut_type;	/* used to configure Get/Set RSS LUT AQ call */</div><div class='hunk'>@@ -517,16 +518,22 @@ enum ice_pf_flags {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum ice_misc_thread_tasks {</div><div class='del'>-	ICE_MISC_THREAD_EXTTS_EVENT,</div><div class='ctx'> 	ICE_MISC_THREAD_TX_TSTAMP,</div><div class='ctx'> 	ICE_MISC_THREAD_NBITS		/* must be last */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct ice_switchdev_info {</div><div class='add'>+struct ice_eswitch {</div><div class='ctx'> 	struct ice_vsi *control_vsi;</div><div class='ctx'> 	struct ice_vsi *uplink_vsi;</div><div class='ctx'> 	struct ice_esw_br_offloads *br_offloads;</div><div class='add'>+	struct xarray reprs;</div><div class='ctx'> 	bool is_running;</div><div class='add'>+	/* struct to allow cp queues management optimization */</div><div class='add'>+	struct {</div><div class='add'>+		int to_reach;</div><div class='add'>+		int value;</div><div class='add'>+		bool is_reaching;</div><div class='add'>+	} qs;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ice_agg_node {</div><div class='hunk'>@@ -563,6 +570,10 @@ struct ice_pf {</div><div class='ctx'> 	struct ice_vsi_stats **vsi_stats;</div><div class='ctx'> 	struct ice_sw *first_sw;	/* first switch created by firmware */</div><div class='ctx'> 	u16 eswitch_mode;		/* current mode of eswitch */</div><div class='add'>+	struct dentry *ice_debugfs_pf;</div><div class='add'>+	struct dentry *ice_debugfs_pf_fwlog;</div><div class='add'>+	/* keep track of all the dentrys for FW log modules */</div><div class='add'>+	struct dentry **ice_debugfs_pf_fwlog_modules;</div><div class='ctx'> 	struct ice_vfs vfs;</div><div class='ctx'> 	DECLARE_BITMAP(features, ICE_F_MAX);</div><div class='ctx'> 	DECLARE_BITMAP(state, ICE_STATE_NBITS);</div><div class='hunk'>@@ -597,6 +608,7 @@ struct ice_pf {</div><div class='ctx'> 	u32 hw_csum_rx_error;</div><div class='ctx'> 	u32 oicr_err_reg;</div><div class='ctx'> 	struct msi_map oicr_irq;	/* Other interrupt cause MSIX vector */</div><div class='add'>+	struct msi_map ll_ts_irq;	/* LL_TS interrupt MSIX vector */</div><div class='ctx'> 	u16 max_pf_txqs;	/* Total Tx queues PF wide */</div><div class='ctx'> 	u16 max_pf_rxqs;	/* Total Rx queues PF wide */</div><div class='ctx'> 	u16 num_lan_msix;	/* Total MSIX vectors for base driver */</div><div class='hunk'>@@ -621,6 +633,7 @@ struct ice_pf {</div><div class='ctx'> 	unsigned long tx_timeout_last_recovery;</div><div class='ctx'> 	u32 tx_timeout_recovery_level;</div><div class='ctx'> 	char int_name[ICE_INT_NAME_STR_LEN];</div><div class='add'>+	char int_name_ll_ts[ICE_INT_NAME_STR_LEN];</div><div class='ctx'> 	struct auxiliary_device *adev;</div><div class='ctx'> 	int aux_idx;</div><div class='ctx'> 	u32 sw_int_count;</div><div class='hunk'>@@ -637,7 +650,7 @@ struct ice_pf {</div><div class='ctx'> 	struct ice_link_default_override_tlv link_dflt_override;</div><div class='ctx'> 	struct ice_lag *lag; /* Link Aggregation information */</div><div class='ctx'> </div><div class='del'>-	struct ice_switchdev_info switchdev;</div><div class='add'>+	struct ice_eswitch eswitch;</div><div class='ctx'> 	struct ice_esw_br_port *br_port;</div><div class='ctx'> </div><div class='ctx'> #define ICE_INVALID_AGG_NODE_ID		0</div><div class='hunk'>@@ -648,6 +661,7 @@ struct ice_pf {</div><div class='ctx'> #define ICE_MAX_VF_AGG_NODES		32</div><div class='ctx'> 	struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES];</div><div class='ctx'> 	struct ice_dplls dplls;</div><div class='add'>+	struct device *hwmon_dev;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern struct workqueue_struct *ice_lag_wq;</div><div class='hunk'>@@ -846,7 +860,7 @@ static inline struct ice_vsi *ice_find_vsi(struct ice_pf *pf, u16 vsi_num)</div><div class='ctx'>  */</div><div class='ctx'> static inline bool ice_is_switchdev_running(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	return pf-&gt;switchdev.is_running;</div><div class='add'>+	return pf-&gt;eswitch.is_running;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define ICE_FD_STAT_CTR_BLOCK_COUNT	256</div><div class='hunk'>@@ -881,6 +895,11 @@ static inline bool ice_is_adq_active(struct ice_pf *pf)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void ice_debugfs_fwlog_init(struct ice_pf *pf);</div><div class='add'>+void ice_debugfs_init(void);</div><div class='add'>+void ice_debugfs_exit(void);</div><div class='add'>+void ice_pf_fwlog_update_module(struct ice_pf *pf, int log_level, int module);</div><div class='add'>+</div><div class='ctx'> bool netif_is_ice(const struct net_device *dev);</div><div class='ctx'> int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);</div><div class='ctx'> int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);</div><div class='hunk'>@@ -912,6 +931,7 @@ int ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);</div><div class='ctx'> int ice_get_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size);</div><div class='ctx'> int ice_set_rss_key(struct ice_vsi *vsi, u8 *seed);</div><div class='ctx'> int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed);</div><div class='add'>+int ice_set_rss_hfunc(struct ice_vsi *vsi, u8 hfunc);</div><div class='ctx'> void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);</div><div class='ctx'> int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);</div><div class='ctx'> void ice_print_link_msg(struct ice_vsi *vsi, bool isup);</div><div class='hunk'>@@ -989,4 +1009,6 @@ static inline void ice_clear_rdma_cap(struct ice_pf *pf)</div><div class='ctx'> 	set_bit(ICE_FLAG_UNPLUG_AUX_DEV, pf-&gt;flags);</div><div class='ctx'> 	clear_bit(ICE_FLAG_RDMA_ENA, pf-&gt;flags);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+extern const struct xdp_metadata_ops ice_xdp_md_ops;</div><div class='ctx'> #endif /* _ICE_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h<br/>index d7fdb7ba7268..8040317c9561 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_adminq_cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_adminq_cmd.h</a></div><div class='hunk'>@@ -117,6 +117,7 @@ struct ice_aqc_list_caps_elem {</div><div class='ctx'> #define ICE_AQC_CAPS_NET_VER				0x004C</div><div class='ctx'> #define ICE_AQC_CAPS_PENDING_NET_VER			0x004D</div><div class='ctx'> #define ICE_AQC_CAPS_RDMA				0x0051</div><div class='add'>+#define ICE_AQC_CAPS_SENSOR_READING			0x0067</div><div class='ctx'> #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076</div><div class='ctx'> #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077</div><div class='ctx'> #define ICE_AQC_CAPS_NVM_MGMT				0x0080</div><div class='hunk'>@@ -421,10 +422,10 @@ struct ice_aqc_vsi_props {</div><div class='ctx'> #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID	BIT(2)</div><div class='ctx'> #define ICE_AQ_VSI_INNER_VLAN_EMODE_S		3</div><div class='ctx'> #define ICE_AQ_VSI_INNER_VLAN_EMODE_M		(0x3 &lt;&lt; ICE_AQ_VSI_INNER_VLAN_EMODE_S)</div><div class='del'>-#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	(0x0 &lt;&lt; ICE_AQ_VSI_INNER_VLAN_EMODE_S)</div><div class='del'>-#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	(0x1 &lt;&lt; ICE_AQ_VSI_INNER_VLAN_EMODE_S)</div><div class='del'>-#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		(0x2 &lt;&lt; ICE_AQ_VSI_INNER_VLAN_EMODE_S)</div><div class='del'>-#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	(0x3 &lt;&lt; ICE_AQ_VSI_INNER_VLAN_EMODE_S)</div><div class='add'>+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	0x0U</div><div class='add'>+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	0x1U</div><div class='add'>+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		0x2U</div><div class='add'>+#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	0x3U</div><div class='ctx'> 	u8 inner_vlan_reserved2[3];</div><div class='ctx'> 	/* ingress egress up sections */</div><div class='ctx'> 	__le32 ingress_table; /* bitmap, 3 bits per up */</div><div class='hunk'>@@ -490,11 +491,11 @@ struct ice_aqc_vsi_props {</div><div class='ctx'> #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S		2</div><div class='ctx'> #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M		(0xF &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)</div><div class='ctx'> #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S		6</div><div class='del'>-#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M		(0x3 &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_HASH_S)</div><div class='del'>-#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ		(0x0 &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_HASH_S)</div><div class='del'>-#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ		(0x1 &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_HASH_S)</div><div class='del'>-#define ICE_AQ_VSI_Q_OPT_RSS_XOR		(0x2 &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_HASH_S)</div><div class='del'>-#define ICE_AQ_VSI_Q_OPT_RSS_JHASH		(0x3 &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_HASH_S)</div><div class='add'>+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M		GENMASK(7, 6)</div><div class='add'>+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ		0x0U</div><div class='add'>+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ	0x1U</div><div class='add'>+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR		0x2U</div><div class='add'>+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH		0x3U</div><div class='ctx'> 	u8 q_opt_tc;</div><div class='ctx'> #define ICE_AQ_VSI_Q_OPT_TC_OVR_S		0</div><div class='ctx'> #define ICE_AQ_VSI_Q_OPT_TC_OVR_M		(0x1F &lt;&lt; ICE_AQ_VSI_Q_OPT_TC_OVR_S)</div><div class='hunk'>@@ -1359,8 +1360,9 @@ struct ice_aqc_get_link_status_data {</div><div class='ctx'> 	u8 lp_flowcontrol;</div><div class='ctx'> #define ICE_AQ_LINK_LP_PAUSE_ADV       BIT(0)</div><div class='ctx'> #define ICE_AQ_LINK_LP_ASM_DIR_ADV     BIT(1)</div><div class='add'>+	u8 reserved5[5];</div><div class='ctx'> #define ICE_AQC_LS_DATA_SIZE_V2 \</div><div class='del'>-	offsetofend(struct ice_aqc_get_link_status_data, lp_flowcontrol)</div><div class='add'>+	offsetofend(struct ice_aqc_get_link_status_data, reserved5)</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='ctx'> /* Set event mask command (direct 0x0613) */</div><div class='hunk'>@@ -1413,6 +1415,30 @@ struct ice_aqc_get_phy_rec_clk_out {</div><div class='ctx'> 	__le16 node_handle;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* Get sensor reading (direct 0x0632) */</div><div class='add'>+struct ice_aqc_get_sensor_reading {</div><div class='add'>+	u8 sensor;</div><div class='add'>+	u8 format;</div><div class='add'>+	u8 reserved[6];</div><div class='add'>+	__le32 addr_high;</div><div class='add'>+	__le32 addr_low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Get sensor reading response (direct 0x0632) */</div><div class='add'>+struct ice_aqc_get_sensor_reading_resp {</div><div class='add'>+	union {</div><div class='add'>+		u8 raw[8];</div><div class='add'>+		/* Output data for sensor 0x00, format 0x00 */</div><div class='add'>+		struct _packed {</div><div class='add'>+			s8 temp;</div><div class='add'>+			u8 temp_warning_threshold;</div><div class='add'>+			u8 temp_critical_threshold;</div><div class='add'>+			u8 temp_fatal_threshold;</div><div class='add'>+			u8 reserved[4];</div><div class='add'>+		} s0f0;</div><div class='add'>+	} data;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct ice_aqc_link_topo_params {</div><div class='ctx'> 	u8 lport_num;</div><div class='ctx'> 	u8 lport_num_valid;</div><div class='hunk'>@@ -2069,78 +2095,6 @@ struct ice_aqc_add_rdma_qset_data {</div><div class='ctx'> 	struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* Configure Firmware Logging Command (indirect 0xFF09)</div><div class='del'>- * Logging Information Read Response (indirect 0xFF10)</div><div class='del'>- * Note: The 0xFF10 command has no input parameters.</div><div class='del'>- */</div><div class='del'>-struct ice_aqc_fw_logging {</div><div class='del'>-	u8 log_ctrl;</div><div class='del'>-#define ICE_AQC_FW_LOG_AQ_EN		BIT(0)</div><div class='del'>-#define ICE_AQC_FW_LOG_UART_EN		BIT(1)</div><div class='del'>-	u8 rsvd0;</div><div class='del'>-	u8 log_ctrl_valid; /* Not used by 0xFF10 Response */</div><div class='del'>-#define ICE_AQC_FW_LOG_AQ_VALID		BIT(0)</div><div class='del'>-#define ICE_AQC_FW_LOG_UART_VALID	BIT(1)</div><div class='del'>-	u8 rsvd1[5];</div><div class='del'>-	__le32 addr_high;</div><div class='del'>-	__le32 addr_low;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-enum ice_aqc_fw_logging_mod {</div><div class='del'>-	ICE_AQC_FW_LOG_ID_GENERAL = 0,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_CTRL,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_LINK,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_LINK_TOPO,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_DNL,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_I2C,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_SDP,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_MDIO,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_ADMINQ,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_HDMA,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_LLDP,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_DCBX,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_DCB,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_NETPROXY,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_NVM,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_AUTH,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_VPD,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_IOSF,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_PARSER,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_SW,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_SCHEDULER,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_TXQ,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_RSVD,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_POST,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_WATCHDOG,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_MNG,</div><div class='del'>-	ICE_AQC_FW_LOG_ID_MAX,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-/* Defines for both above FW logging command/response buffers */</div><div class='del'>-#define ICE_AQC_FW_LOG_ID_S		0</div><div class='del'>-#define ICE_AQC_FW_LOG_ID_M		(0xFFF &lt;&lt; ICE_AQC_FW_LOG_ID_S)</div><div class='del'>-</div><div class='del'>-#define ICE_AQC_FW_LOG_CONF_SUCCESS	0	/* Used by response */</div><div class='del'>-#define ICE_AQC_FW_LOG_CONF_BAD_INDX	BIT(12)	/* Used by response */</div><div class='del'>-</div><div class='del'>-#define ICE_AQC_FW_LOG_EN_S		12</div><div class='del'>-#define ICE_AQC_FW_LOG_EN_M		(0xF &lt;&lt; ICE_AQC_FW_LOG_EN_S)</div><div class='del'>-#define ICE_AQC_FW_LOG_INFO_EN		BIT(12)	/* Used by command */</div><div class='del'>-#define ICE_AQC_FW_LOG_INIT_EN		BIT(13)	/* Used by command */</div><div class='del'>-#define ICE_AQC_FW_LOG_FLOW_EN		BIT(14)	/* Used by command */</div><div class='del'>-#define ICE_AQC_FW_LOG_ERR_EN		BIT(15)	/* Used by command */</div><div class='del'>-</div><div class='del'>-/* Get/Clear FW Log (indirect 0xFF11) */</div><div class='del'>-struct ice_aqc_get_clear_fw_log {</div><div class='del'>-	u8 flags;</div><div class='del'>-#define ICE_AQC_FW_LOG_CLEAR		BIT(0)</div><div class='del'>-#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL	BIT(1)</div><div class='del'>-	u8 rsvd1[7];</div><div class='del'>-	__le32 addr_high;</div><div class='del'>-	__le32 addr_low;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* Download Package (indirect 0x0C40) */</div><div class='ctx'> /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */</div><div class='ctx'> struct ice_aqc_download_pkg {</div><div class='hunk'>@@ -2403,6 +2357,84 @@ struct ice_aqc_event_lan_overflow {</div><div class='ctx'> 	u8 reserved[8];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+enum ice_aqc_fw_logging_mod {</div><div class='add'>+	ICE_AQC_FW_LOG_ID_GENERAL = 0,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_CTRL,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_LINK,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_LINK_TOPO,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_DNL,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_I2C,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_SDP,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_MDIO,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_ADMINQ,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_HDMA,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_LLDP,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_DCBX,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_DCB,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_XLR,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_NVM,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_AUTH,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_VPD,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_IOSF,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_PARSER,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_SW,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_SCHEDULER,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_TXQ,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_RSVD,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_POST,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_WATCHDOG,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_MNG,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_SYNCE,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_HEALTH,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_TSDRV,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_PFREG,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_MDLVER,</div><div class='add'>+	ICE_AQC_FW_LOG_ID_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Set FW Logging configuration (indirect 0xFF30)</div><div class='add'>+ * Register for FW Logging (indirect 0xFF31)</div><div class='add'>+ * Query FW Logging (indirect 0xFF32)</div><div class='add'>+ * FW Log Event (indirect 0xFF33)</div><div class='add'>+ */</div><div class='add'>+struct ice_aqc_fw_log {</div><div class='add'>+	u8 cmd_flags;</div><div class='add'>+#define ICE_AQC_FW_LOG_CONF_UART_EN	BIT(0)</div><div class='add'>+#define ICE_AQC_FW_LOG_CONF_AQ_EN	BIT(1)</div><div class='add'>+#define ICE_AQC_FW_LOG_QUERY_REGISTERED	BIT(2)</div><div class='add'>+#define ICE_AQC_FW_LOG_CONF_SET_VALID	BIT(3)</div><div class='add'>+#define ICE_AQC_FW_LOG_AQ_REGISTER	BIT(0)</div><div class='add'>+#define ICE_AQC_FW_LOG_AQ_QUERY		BIT(2)</div><div class='add'>+</div><div class='add'>+	u8 rsp_flag;</div><div class='add'>+	__le16 fw_rt_msb;</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			__le32 fw_rt_lsb;</div><div class='add'>+		} sync;</div><div class='add'>+		struct {</div><div class='add'>+			__le16 log_resolution;</div><div class='add'>+#define ICE_AQC_FW_LOG_MIN_RESOLUTION		(1)</div><div class='add'>+#define ICE_AQC_FW_LOG_MAX_RESOLUTION		(128)</div><div class='add'>+</div><div class='add'>+			__le16 mdl_cnt;</div><div class='add'>+		} cfg;</div><div class='add'>+	} ops;</div><div class='add'>+	__le32 addr_high;</div><div class='add'>+	__le32 addr_low;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Response Buffer for:</div><div class='add'>+ *    Set Firmware Logging Configuration (0xFF30)</div><div class='add'>+ *    Query FW Logging (0xFF32)</div><div class='add'>+ */</div><div class='add'>+struct ice_aqc_fw_log_cfg_resp {</div><div class='add'>+	__le16 module_identifier;</div><div class='add'>+	u8 log_level;</div><div class='add'>+	u8 rsvd0;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * struct ice_aq_desc - Admin Queue (AQ) descriptor</div><div class='ctx'>  * @flags: ICE_AQ_FLAG_* flags</div><div class='hunk'>@@ -2443,6 +2475,8 @@ struct ice_aq_desc {</div><div class='ctx'> 		struct ice_aqc_restart_an restart_an;</div><div class='ctx'> 		struct ice_aqc_set_phy_rec_clk_out set_phy_rec_clk_out;</div><div class='ctx'> 		struct ice_aqc_get_phy_rec_clk_out get_phy_rec_clk_out;</div><div class='add'>+		struct ice_aqc_get_sensor_reading get_sensor_reading;</div><div class='add'>+		struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;</div><div class='ctx'> 		struct ice_aqc_gpio read_write_gpio;</div><div class='ctx'> 		struct ice_aqc_sff_eeprom read_write_sff_param;</div><div class='ctx'> 		struct ice_aqc_set_port_id_led set_port_id_led;</div><div class='hunk'>@@ -2480,8 +2514,6 @@ struct ice_aq_desc {</div><div class='ctx'> 		struct ice_aqc_add_rdma_qset add_rdma_qset;</div><div class='ctx'> 		struct ice_aqc_add_get_update_free_vsi vsi_cmd;</div><div class='ctx'> 		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;</div><div class='del'>-		struct ice_aqc_fw_logging fw_logging;</div><div class='del'>-		struct ice_aqc_get_clear_fw_log get_clear_fw_log;</div><div class='ctx'> 		struct ice_aqc_download_pkg download_pkg;</div><div class='ctx'> 		struct ice_aqc_set_cgu_input_config set_cgu_input_config;</div><div class='ctx'> 		struct ice_aqc_get_cgu_input_config get_cgu_input_config;</div><div class='hunk'>@@ -2493,6 +2525,7 @@ struct ice_aq_desc {</div><div class='ctx'> 		struct ice_aqc_get_cgu_ref_prio get_cgu_ref_prio;</div><div class='ctx'> 		struct ice_aqc_get_cgu_info get_cgu_info;</div><div class='ctx'> 		struct ice_aqc_driver_shared_params drv_shared_params;</div><div class='add'>+		struct ice_aqc_fw_log fw_log;</div><div class='ctx'> 		struct ice_aqc_set_mac_lb set_mac_lb;</div><div class='ctx'> 		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;</div><div class='ctx'> 		struct ice_aqc_set_mac_cfg set_mac_cfg;</div><div class='hunk'>@@ -2618,6 +2651,7 @@ enum ice_adminq_opc {</div><div class='ctx'> 	ice_aqc_opc_set_mac_lb				= 0x0620,</div><div class='ctx'> 	ice_aqc_opc_set_phy_rec_clk_out			= 0x0630,</div><div class='ctx'> 	ice_aqc_opc_get_phy_rec_clk_out			= 0x0631,</div><div class='add'>+	ice_aqc_opc_get_sensor_reading			= 0x0632,</div><div class='ctx'> 	ice_aqc_opc_get_link_topo			= 0x06E0,</div><div class='ctx'> 	ice_aqc_opc_read_i2c				= 0x06E2,</div><div class='ctx'> 	ice_aqc_opc_write_i2c				= 0x06E3,</div><div class='hunk'>@@ -2690,9 +2724,11 @@ enum ice_adminq_opc {</div><div class='ctx'> 	/* Standalone Commands/Events */</div><div class='ctx'> 	ice_aqc_opc_event_lan_overflow			= 0x1001,</div><div class='ctx'> </div><div class='del'>-	/* debug commands */</div><div class='del'>-	ice_aqc_opc_fw_logging				= 0xFF09,</div><div class='del'>-	ice_aqc_opc_fw_logging_info			= 0xFF10,</div><div class='add'>+	/* FW Logging Commands */</div><div class='add'>+	ice_aqc_opc_fw_logs_config			= 0xFF30,</div><div class='add'>+	ice_aqc_opc_fw_logs_register			= 0xFF31,</div><div class='add'>+	ice_aqc_opc_fw_logs_query			= 0xFF32,</div><div class='add'>+	ice_aqc_opc_fw_logs_event			= 0xFF33,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #endif /* _ICE_ADMINQ_CMD_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_base.c b/drivers/net/ethernet/intel/ice/ice_base.c<br/>index 7fa43827a3f0..533b923cae2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_base.c</a></div><div class='hunk'>@@ -189,10 +189,18 @@ static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)</div><div class='ctx'> 	}</div><div class='ctx'> 	q_vector = vsi-&gt;q_vectors[v_idx];</div><div class='ctx'> </div><div class='del'>-	ice_for_each_tx_ring(tx_ring, q_vector-&gt;tx)</div><div class='add'>+	ice_for_each_tx_ring(tx_ring, q_vector-&gt;tx) {</div><div class='add'>+		if (vsi-&gt;netdev)</div><div class='add'>+			netif_queue_set_napi(vsi-&gt;netdev, tx_ring-&gt;q_index,</div><div class='add'>+					     NETDEV_QUEUE_TYPE_TX, NULL);</div><div class='ctx'> 		tx_ring-&gt;q_vector = NULL;</div><div class='del'>-	ice_for_each_rx_ring(rx_ring, q_vector-&gt;rx)</div><div class='add'>+	}</div><div class='add'>+	ice_for_each_rx_ring(rx_ring, q_vector-&gt;rx) {</div><div class='add'>+		if (vsi-&gt;netdev)</div><div class='add'>+			netif_queue_set_napi(vsi-&gt;netdev, rx_ring-&gt;q_index,</div><div class='add'>+					     NETDEV_QUEUE_TYPE_RX, NULL);</div><div class='ctx'> 		rx_ring-&gt;q_vector = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* only VSI with an associated netdev is set up with NAPI */</div><div class='ctx'> 	if (vsi-&gt;netdev)</div><div class='hunk'>@@ -224,24 +232,16 @@ static void ice_cfg_itr_gran(struct ice_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* no need to update global register if ITR gran is already set */</div><div class='ctx'> 	if (!(regval &amp; GLINT_CTL_DIS_AUTOMASK_M) &amp;&amp;</div><div class='del'>-	    (((regval &amp; GLINT_CTL_ITR_GRAN_200_M) &gt;&gt;</div><div class='del'>-	     GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='del'>-	    (((regval &amp; GLINT_CTL_ITR_GRAN_100_M) &gt;&gt;</div><div class='del'>-	     GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='del'>-	    (((regval &amp; GLINT_CTL_ITR_GRAN_50_M) &gt;&gt;</div><div class='del'>-	     GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='del'>-	    (((regval &amp; GLINT_CTL_ITR_GRAN_25_M) &gt;&gt;</div><div class='del'>-	      GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))</div><div class='add'>+	    (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='add'>+	    (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='add'>+	    (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) &amp;&amp;</div><div class='add'>+	    (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	regval = ((ICE_ITR_GRAN_US &lt;&lt; GLINT_CTL_ITR_GRAN_200_S) &amp;</div><div class='del'>-		  GLINT_CTL_ITR_GRAN_200_M) |</div><div class='del'>-		 ((ICE_ITR_GRAN_US &lt;&lt; GLINT_CTL_ITR_GRAN_100_S) &amp;</div><div class='del'>-		  GLINT_CTL_ITR_GRAN_100_M) |</div><div class='del'>-		 ((ICE_ITR_GRAN_US &lt;&lt; GLINT_CTL_ITR_GRAN_50_S) &amp;</div><div class='del'>-		  GLINT_CTL_ITR_GRAN_50_M) |</div><div class='del'>-		 ((ICE_ITR_GRAN_US &lt;&lt; GLINT_CTL_ITR_GRAN_25_S) &amp;</div><div class='del'>-		  GLINT_CTL_ITR_GRAN_25_M);</div><div class='add'>+	regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |</div><div class='add'>+		 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) |</div><div class='add'>+		 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) |</div><div class='add'>+		 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US);</div><div class='ctx'> 	wr32(hw, GLINT_CTL, regval);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -278,7 +278,7 @@ static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8</div><div class='ctx'>  */</div><div class='ctx'> static u16 ice_eswitch_calc_txq_handle(struct ice_tx_ring *ring)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *vsi = ring-&gt;vsi;</div><div class='add'>+	const struct ice_vsi *vsi = ring-&gt;vsi;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	ice_for_each_txq(vsi, i) {</div><div class='hunk'>@@ -519,6 +519,19 @@ static int ice_setup_rx_ctx(struct ice_rx_ring *ring)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ice_xsk_pool_fill_cb(struct ice_rx_ring *ring)</div><div class='add'>+{</div><div class='add'>+	void *ctx_ptr = &amp;ring-&gt;pkt_ctx;</div><div class='add'>+	struct xsk_cb_desc desc = {};</div><div class='add'>+</div><div class='add'>+	XSK_CHECK_PRIV_TYPE(struct ice_xdp_buff);</div><div class='add'>+	desc.src = &amp;ctx_ptr;</div><div class='add'>+	desc.off = offsetof(struct ice_xdp_buff, pkt_ctx) -</div><div class='add'>+		   sizeof(struct xdp_buff);</div><div class='add'>+	desc.bytes = sizeof(ctx_ptr);</div><div class='add'>+	xsk_pool_fill_cb(ring-&gt;xsk_pool, &amp;desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ice_vsi_cfg_rxq - Configure an Rx queue</div><div class='ctx'>  * @ring: the ring being configured</div><div class='hunk'>@@ -553,6 +566,7 @@ int ice_vsi_cfg_rxq(struct ice_rx_ring *ring)</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='ctx'> 			xsk_pool_set_rxq_info(ring-&gt;xsk_pool, &amp;ring-&gt;xdp_rxq);</div><div class='add'>+			ice_xsk_pool_fill_cb(ring);</div><div class='ctx'> </div><div class='ctx'> 			dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",</div><div class='ctx'> 				 ring-&gt;q_index);</div><div class='hunk'>@@ -575,6 +589,7 @@ int ice_vsi_cfg_rxq(struct ice_rx_ring *ring)</div><div class='ctx'> </div><div class='ctx'> 	xdp_init_buff(&amp;ring-&gt;xdp, ice_rx_pg_size(ring) / 2, &amp;ring-&gt;xdp_rxq);</div><div class='ctx'> 	ring-&gt;xdp.data = NULL;</div><div class='add'>+	ring-&gt;xdp_ext.pkt_ctx = &amp;ring-&gt;pkt_ctx;</div><div class='ctx'> 	err = ice_setup_rx_ctx(ring);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n",</div><div class='hunk'>@@ -913,10 +928,10 @@ ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	itr_idx = (itr_idx &lt;&lt; QINT_TQCTL_ITR_INDX_S) &amp; QINT_TQCTL_ITR_INDX_M;</div><div class='add'>+	itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx);</div><div class='ctx'> </div><div class='ctx'> 	val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |</div><div class='del'>-	      ((msix_idx &lt;&lt; QINT_TQCTL_MSIX_INDX_S) &amp; QINT_TQCTL_MSIX_INDX_M);</div><div class='add'>+	      FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx);</div><div class='ctx'> </div><div class='ctx'> 	wr32(hw, QINT_TQCTL(vsi-&gt;txq_map[txq]), val);</div><div class='ctx'> 	if (ice_is_xdp_ena_vsi(vsi)) {</div><div class='hunk'>@@ -945,10 +960,10 @@ ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	itr_idx = (itr_idx &lt;&lt; QINT_RQCTL_ITR_INDX_S) &amp; QINT_RQCTL_ITR_INDX_M;</div><div class='add'>+	itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx);</div><div class='ctx'> </div><div class='ctx'> 	val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |</div><div class='del'>-	      ((msix_idx &lt;&lt; QINT_RQCTL_MSIX_INDX_S) &amp; QINT_RQCTL_MSIX_INDX_M);</div><div class='add'>+	      FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx);</div><div class='ctx'> </div><div class='ctx'> 	wr32(hw, QINT_RQCTL(vsi-&gt;rxq_map[rxq]), val);</div><div class='ctx'> </div><div class='hunk'>@@ -960,7 +975,7 @@ ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)</div><div class='ctx'>  * @hw: pointer to the HW structure</div><div class='ctx'>  * @q_vector: interrupt vector to trigger the software interrupt for</div><div class='ctx'>  */</div><div class='del'>-void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)</div><div class='add'>+void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector)</div><div class='ctx'> {</div><div class='ctx'> 	wr32(hw, GLINT_DYN_CTL(q_vector-&gt;reg_idx),</div><div class='ctx'> 	     (ICE_ITR_NONE &lt;&lt; GLINT_DYN_CTL_ITR_INDX_S) |</div><div class='hunk'>@@ -1035,7 +1050,7 @@ ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,</div><div class='ctx'>  * are needed for stopping Tx queue</div><div class='ctx'>  */</div><div class='ctx'> void</div><div class='del'>-ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_tx_ring *ring,</div><div class='add'>+ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,</div><div class='ctx'> 		  struct ice_txq_meta *txq_meta)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_channel *ch = ring-&gt;ch;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_base.h b/drivers/net/ethernet/intel/ice/ice_base.h<br/>index b67dca417acb..17321ba75602 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_base.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_base.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_base.h</a></div><div class='hunk'>@@ -22,12 +22,12 @@ void</div><div class='ctx'> ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx);</div><div class='ctx'> void</div><div class='ctx'> ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx);</div><div class='del'>-void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector);</div><div class='add'>+void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector);</div><div class='ctx'> int</div><div class='ctx'> ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,</div><div class='ctx'> 		     u16 rel_vmvf_num, struct ice_tx_ring *ring,</div><div class='ctx'> 		     struct ice_txq_meta *txq_meta);</div><div class='ctx'> void</div><div class='del'>-ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_tx_ring *ring,</div><div class='add'>+ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,</div><div class='ctx'> 		  struct ice_txq_meta *txq_meta);</div><div class='ctx'> #endif /* _ICE_BASE_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c<br/>index 9a6c25f98632..10c32cd80fff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_common.c</a></div><div class='hunk'>@@ -934,216 +934,6 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_get_fw_log_cfg - get FW logging configuration</div><div class='del'>- * @hw: pointer to the HW struct</div><div class='del'>- */</div><div class='del'>-static int ice_get_fw_log_cfg(struct ice_hw *hw)</div><div class='del'>-{</div><div class='del'>-	struct ice_aq_desc desc;</div><div class='del'>-	__le16 *config;</div><div class='del'>-	int status;</div><div class='del'>-	u16 size;</div><div class='del'>-</div><div class='del'>-	size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX;</div><div class='del'>-	config = kzalloc(size, GFP_KERNEL);</div><div class='del'>-	if (!config)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_fw_logging_info);</div><div class='del'>-</div><div class='del'>-	status = ice_aq_send_cmd(hw, &amp;desc, config, size, NULL);</div><div class='del'>-	if (!status) {</div><div class='del'>-		u16 i;</div><div class='del'>-</div><div class='del'>-		/* Save FW logging information into the HW structure */</div><div class='del'>-		for (i = 0; i &lt; ICE_AQC_FW_LOG_ID_MAX; i++) {</div><div class='del'>-			u16 v, m, flgs;</div><div class='del'>-</div><div class='del'>-			v = le16_to_cpu(config[i]);</div><div class='del'>-			m = (v &amp; ICE_AQC_FW_LOG_ID_M) &gt;&gt; ICE_AQC_FW_LOG_ID_S;</div><div class='del'>-			flgs = (v &amp; ICE_AQC_FW_LOG_EN_M) &gt;&gt; ICE_AQC_FW_LOG_EN_S;</div><div class='del'>-</div><div class='del'>-			if (m &lt; ICE_AQC_FW_LOG_ID_MAX)</div><div class='del'>-				hw-&gt;fw_log.evnts[m].cur = flgs;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	kfree(config);</div><div class='del'>-</div><div class='del'>-	return status;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * ice_cfg_fw_log - configure FW logging</div><div class='del'>- * @hw: pointer to the HW struct</div><div class='del'>- * @enable: enable certain FW logging events if true, disable all if false</div><div class='del'>- *</div><div class='del'>- * This function enables/disables the FW logging via Rx CQ events and a UART</div><div class='del'>- * port based on predetermined configurations. FW logging via the Rx CQ can be</div><div class='del'>- * enabled/disabled for individual PF's. However, FW logging via the UART can</div><div class='del'>- * only be enabled/disabled for all PFs on the same device.</div><div class='del'>- *</div><div class='del'>- * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in</div><div class='del'>- * hw-&gt;fw_log need to be set accordingly, e.g. based on user-provided input,</div><div class='del'>- * before initializing the device.</div><div class='del'>- *</div><div class='del'>- * When re/configuring FW logging, callers need to update the "cfg" elements of</div><div class='del'>- * the hw-&gt;fw_log.evnts array with the desired logging event configurations for</div><div class='del'>- * modules of interest. When disabling FW logging completely, the callers can</div><div class='del'>- * just pass false in the "enable" parameter. On completion, the function will</div><div class='del'>- * update the "cur" element of the hw-&gt;fw_log.evnts array with the resulting</div><div class='del'>- * logging event configurations of the modules that are being re/configured. FW</div><div class='del'>- * logging modules that are not part of a reconfiguration operation retain their</div><div class='del'>- * previous states.</div><div class='del'>- *</div><div class='del'>- * Before resetting the device, it is recommended that the driver disables FW</div><div class='del'>- * logging before shutting down the control queue. When disabling FW logging</div><div class='del'>- * ("enable" = false), the latest configurations of FW logging events stored in</div><div class='del'>- * hw-&gt;fw_log.evnts[] are not overridden to allow them to be reconfigured after</div><div class='del'>- * a device reset.</div><div class='del'>- *</div><div class='del'>- * When enabling FW logging to emit log messages via the Rx CQ during the</div><div class='del'>- * device's initialization phase, a mechanism alternative to interrupt handlers</div><div class='del'>- * needs to be used to extract FW log messages from the Rx CQ periodically and</div><div class='del'>- * to prevent the Rx CQ from being full and stalling other types of control</div><div class='del'>- * messages from FW to SW. Interrupts are typically disabled during the device's</div><div class='del'>- * initialization phase.</div><div class='del'>- */</div><div class='del'>-static int ice_cfg_fw_log(struct ice_hw *hw, bool enable)</div><div class='del'>-{</div><div class='del'>-	struct ice_aqc_fw_logging *cmd;</div><div class='del'>-	u16 i, chgs = 0, len = 0;</div><div class='del'>-	struct ice_aq_desc desc;</div><div class='del'>-	__le16 *data = NULL;</div><div class='del'>-	u8 actv_evnts = 0;</div><div class='del'>-	void *buf = NULL;</div><div class='del'>-	int status = 0;</div><div class='del'>-</div><div class='del'>-	if (!hw-&gt;fw_log.cq_en &amp;&amp; !hw-&gt;fw_log.uart_en)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Disable FW logging only when the control queue is still responsive */</div><div class='del'>-	if (!enable &amp;&amp;</div><div class='del'>-	    (!hw-&gt;fw_log.actv_evnts || !ice_check_sq_alive(hw, &amp;hw-&gt;adminq)))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Get current FW log settings */</div><div class='del'>-	status = ice_get_fw_log_cfg(hw);</div><div class='del'>-	if (status)</div><div class='del'>-		return status;</div><div class='del'>-</div><div class='del'>-	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_fw_logging);</div><div class='del'>-	cmd = &amp;desc.params.fw_logging;</div><div class='del'>-</div><div class='del'>-	/* Indicate which controls are valid */</div><div class='del'>-	if (hw-&gt;fw_log.cq_en)</div><div class='del'>-		cmd-&gt;log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;</div><div class='del'>-</div><div class='del'>-	if (hw-&gt;fw_log.uart_en)</div><div class='del'>-		cmd-&gt;log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;</div><div class='del'>-</div><div class='del'>-	if (enable) {</div><div class='del'>-		/* Fill in an array of entries with FW logging modules and</div><div class='del'>-		 * logging events being reconfigured.</div><div class='del'>-		 */</div><div class='del'>-		for (i = 0; i &lt; ICE_AQC_FW_LOG_ID_MAX; i++) {</div><div class='del'>-			u16 val;</div><div class='del'>-</div><div class='del'>-			/* Keep track of enabled event types */</div><div class='del'>-			actv_evnts |= hw-&gt;fw_log.evnts[i].cfg;</div><div class='del'>-</div><div class='del'>-			if (hw-&gt;fw_log.evnts[i].cfg == hw-&gt;fw_log.evnts[i].cur)</div><div class='del'>-				continue;</div><div class='del'>-</div><div class='del'>-			if (!data) {</div><div class='del'>-				data = devm_kcalloc(ice_hw_to_dev(hw),</div><div class='del'>-						    ICE_AQC_FW_LOG_ID_MAX,</div><div class='del'>-						    sizeof(*data),</div><div class='del'>-						    GFP_KERNEL);</div><div class='del'>-				if (!data)</div><div class='del'>-					return -ENOMEM;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			val = i &lt;&lt; ICE_AQC_FW_LOG_ID_S;</div><div class='del'>-			val |= hw-&gt;fw_log.evnts[i].cfg &lt;&lt; ICE_AQC_FW_LOG_EN_S;</div><div class='del'>-			data[chgs++] = cpu_to_le16(val);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Only enable FW logging if at least one module is specified.</div><div class='del'>-		 * If FW logging is currently enabled but all modules are not</div><div class='del'>-		 * enabled to emit log messages, disable FW logging altogether.</div><div class='del'>-		 */</div><div class='del'>-		if (actv_evnts) {</div><div class='del'>-			/* Leave if there is effectively no change */</div><div class='del'>-			if (!chgs)</div><div class='del'>-				goto out;</div><div class='del'>-</div><div class='del'>-			if (hw-&gt;fw_log.cq_en)</div><div class='del'>-				cmd-&gt;log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;</div><div class='del'>-</div><div class='del'>-			if (hw-&gt;fw_log.uart_en)</div><div class='del'>-				cmd-&gt;log_ctrl |= ICE_AQC_FW_LOG_UART_EN;</div><div class='del'>-</div><div class='del'>-			buf = data;</div><div class='del'>-			len = sizeof(*data) * chgs;</div><div class='del'>-			desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	status = ice_aq_send_cmd(hw, &amp;desc, buf, len, NULL);</div><div class='del'>-	if (!status) {</div><div class='del'>-		/* Update the current configuration to reflect events enabled.</div><div class='del'>-		 * hw-&gt;fw_log.cq_en and hw-&gt;fw_log.uart_en indicate if the FW</div><div class='del'>-		 * logging mode is enabled for the device. They do not reflect</div><div class='del'>-		 * actual modules being enabled to emit log messages. So, their</div><div class='del'>-		 * values remain unchanged even when all modules are disabled.</div><div class='del'>-		 */</div><div class='del'>-		u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;</div><div class='del'>-</div><div class='del'>-		hw-&gt;fw_log.actv_evnts = actv_evnts;</div><div class='del'>-		for (i = 0; i &lt; cnt; i++) {</div><div class='del'>-			u16 v, m;</div><div class='del'>-</div><div class='del'>-			if (!enable) {</div><div class='del'>-				/* When disabling all FW logging events as part</div><div class='del'>-				 * of device's de-initialization, the original</div><div class='del'>-				 * configurations are retained, and can be used</div><div class='del'>-				 * to reconfigure FW logging later if the device</div><div class='del'>-				 * is re-initialized.</div><div class='del'>-				 */</div><div class='del'>-				hw-&gt;fw_log.evnts[i].cur = 0;</div><div class='del'>-				continue;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			v = le16_to_cpu(data[i]);</div><div class='del'>-			m = (v &amp; ICE_AQC_FW_LOG_ID_M) &gt;&gt; ICE_AQC_FW_LOG_ID_S;</div><div class='del'>-			hw-&gt;fw_log.evnts[m].cur = hw-&gt;fw_log.evnts[m].cfg;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	devm_kfree(ice_hw_to_dev(hw), data);</div><div class='del'>-</div><div class='del'>-	return status;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * ice_output_fw_log</div><div class='del'>- * @hw: pointer to the HW struct</div><div class='del'>- * @desc: pointer to the AQ message descriptor</div><div class='del'>- * @buf: pointer to the buffer accompanying the AQ message</div><div class='del'>- *</div><div class='del'>- * Formats a FW Log message and outputs it via the standard driver logs.</div><div class='del'>- */</div><div class='del'>-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)</div><div class='del'>-{</div><div class='del'>-	ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");</div><div class='del'>-	ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,</div><div class='del'>-			le16_to_cpu(desc-&gt;datalen));</div><div class='del'>-	ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ice_get_itr_intrl_gran</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  *</div><div class='hunk'>@@ -1152,9 +942,8 @@ void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)</div><div class='ctx'>  */</div><div class='ctx'> static void ice_get_itr_intrl_gran(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &amp;</div><div class='del'>-			 GL_PWR_MODE_CTL_CAR_MAX_BW_M) &gt;&gt;</div><div class='del'>-			GL_PWR_MODE_CTL_CAR_MAX_BW_S;</div><div class='add'>+	u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M,</div><div class='add'>+				  rd32(hw, GL_PWR_MODE_CTL));</div><div class='ctx'> </div><div class='ctx'> 	switch (max_agg_bw) {</div><div class='ctx'> 	case ICE_MAX_AGG_BW_200G:</div><div class='hunk'>@@ -1186,9 +975,7 @@ int ice_init_hw(struct ice_hw *hw)</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='del'>-	hw-&gt;pf_id = (u8)(rd32(hw, PF_FUNC_RID) &amp;</div><div class='del'>-			 PF_FUNC_RID_FUNC_NUM_M) &gt;&gt;</div><div class='del'>-		PF_FUNC_RID_FUNC_NUM_S;</div><div class='add'>+	hw-&gt;pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID));</div><div class='ctx'> </div><div class='ctx'> 	status = ice_reset(hw, ICE_RESET_PFR);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -1200,10 +987,10 @@ int ice_init_hw(struct ice_hw *hw)</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		goto err_unroll_cqinit;</div><div class='ctx'> </div><div class='del'>-	/* Enable FW logging. Not fatal if this fails. */</div><div class='del'>-	status = ice_cfg_fw_log(hw, true);</div><div class='add'>+	status = ice_fwlog_init(hw);</div><div class='ctx'> 	if (status)</div><div class='del'>-		ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n",</div><div class='add'>+			  status);</div><div class='ctx'> </div><div class='ctx'> 	status = ice_clear_pf_cfg(hw);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -1354,8 +1141,7 @@ void ice_deinit_hw(struct ice_hw *hw)</div><div class='ctx'> 	ice_free_hw_tbls(hw);</div><div class='ctx'> 	mutex_destroy(&amp;hw-&gt;tnl_lock);</div><div class='ctx'> </div><div class='del'>-	/* Attempt to disable FW logging before shutting down control queues */</div><div class='del'>-	ice_cfg_fw_log(hw, false);</div><div class='add'>+	ice_fwlog_deinit(hw);</div><div class='ctx'> 	ice_destroy_all_ctrlq(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Clear VSI contexts if not already cleared */</div><div class='hunk'>@@ -1374,8 +1160,8 @@ int ice_check_reset(struct ice_hw *hw)</div><div class='ctx'> 	 * or EMPR has occurred. The grst delay value is in 100ms units.</div><div class='ctx'> 	 * Add 1sec for outstanding AQ commands that can take a long time.</div><div class='ctx'> 	 */</div><div class='del'>-	grst_timeout = ((rd32(hw, GLGEN_RSTCTL) &amp; GLGEN_RSTCTL_GRSTDEL_M) &gt;&gt;</div><div class='del'>-			GLGEN_RSTCTL_GRSTDEL_S) + 10;</div><div class='add'>+	grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M,</div><div class='add'>+				 rd32(hw, GLGEN_RSTCTL)) + 10;</div><div class='ctx'> </div><div class='ctx'> 	for (cnt = 0; cnt &lt; grst_timeout; cnt++) {</div><div class='ctx'> 		mdelay(100);</div><div class='hunk'>@@ -2459,7 +2245,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,</div><div class='ctx'> 	info-&gt;tmr_index_owned = ((number &amp; ICE_TS_TMR_IDX_OWND_M) != 0);</div><div class='ctx'> 	info-&gt;tmr_index_assoc = ((number &amp; ICE_TS_TMR_IDX_ASSOC_M) != 0);</div><div class='ctx'> </div><div class='del'>-	info-&gt;clk_freq = (number &amp; ICE_TS_CLK_FREQ_M) &gt;&gt; ICE_TS_CLK_FREQ_S;</div><div class='add'>+	info-&gt;clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);</div><div class='ctx'> 	info-&gt;clk_src = ((number &amp; ICE_TS_CLK_SRC_M) != 0);</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;clk_freq &lt; NUM_ICE_TIME_REF_FREQ) {</div><div class='hunk'>@@ -2660,11 +2446,12 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,</div><div class='ctx'> 	info-&gt;tmr0_owned = ((number &amp; ICE_TS_TMR0_OWND_M) != 0);</div><div class='ctx'> 	info-&gt;tmr0_ena = ((number &amp; ICE_TS_TMR0_ENA_M) != 0);</div><div class='ctx'> </div><div class='del'>-	info-&gt;tmr1_owner = (number &amp; ICE_TS_TMR1_OWNR_M) &gt;&gt; ICE_TS_TMR1_OWNR_S;</div><div class='add'>+	info-&gt;tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number);</div><div class='ctx'> 	info-&gt;tmr1_owned = ((number &amp; ICE_TS_TMR1_OWND_M) != 0);</div><div class='ctx'> 	info-&gt;tmr1_ena = ((number &amp; ICE_TS_TMR1_ENA_M) != 0);</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;ts_ll_read = ((number &amp; ICE_TS_LL_TX_TS_READ_M) != 0);</div><div class='add'>+	info-&gt;ts_ll_int_read = ((number &amp; ICE_TS_LL_TX_TS_INT_READ_M) != 0);</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;ena_ports = logical_id;</div><div class='ctx'> 	info-&gt;tmr_own_map = phys_id;</div><div class='hunk'>@@ -2685,6 +2472,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,</div><div class='ctx'> 		  info-&gt;tmr1_ena);</div><div class='ctx'> 	ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",</div><div class='ctx'> 		  info-&gt;ts_ll_read);</div><div class='add'>+	ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n",</div><div class='add'>+		  info-&gt;ts_ll_int_read);</div><div class='ctx'> 	ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",</div><div class='ctx'> 		  info-&gt;ena_ports);</div><div class='ctx'> 	ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",</div><div class='hunk'>@@ -2711,6 +2500,26 @@ ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap</div><div class='add'>+ * @hw: pointer to the HW struct</div><div class='add'>+ * @dev_p: pointer to device capabilities structure</div><div class='add'>+ * @cap: capability element to parse</div><div class='add'>+ *</div><div class='add'>+ * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading</div><div class='add'>+ * enabled sensors.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,</div><div class='add'>+			     struct ice_aqc_list_caps_elem *cap)</div><div class='add'>+{</div><div class='add'>+	dev_p-&gt;supported_sensors = le32_to_cpu(cap-&gt;number);</div><div class='add'>+</div><div class='add'>+	ice_debug(hw, ICE_DBG_INIT,</div><div class='add'>+		  "dev caps: supported sensors (bitmap) = 0x%x\n",</div><div class='add'>+		  dev_p-&gt;supported_sensors);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_parse_dev_caps - Parse device capabilities</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @dev_p: pointer to device capabilities structure</div><div class='hunk'>@@ -2755,9 +2564,12 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,</div><div class='ctx'> 		case ICE_AQC_CAPS_1588:</div><div class='ctx'> 			ice_parse_1588_dev_caps(hw, dev_p, &amp;cap_resp[i]);</div><div class='ctx'> 			break;</div><div class='del'>-		case  ICE_AQC_CAPS_FD:</div><div class='add'>+		case ICE_AQC_CAPS_FD:</div><div class='ctx'> 			ice_parse_fdir_dev_caps(hw, dev_p, &amp;cap_resp[i]);</div><div class='ctx'> 			break;</div><div class='add'>+		case ICE_AQC_CAPS_SENSOR_READING:</div><div class='add'>+			ice_parse_sensor_reading_cap(hw, dev_p, &amp;cap_resp[i]);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			/* Don't list common capabilities as unknown */</div><div class='ctx'> 			if (!found)</div><div class='hunk'>@@ -4072,6 +3884,7 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_aqc_sff_eeprom *cmd;</div><div class='ctx'> 	struct ice_aq_desc desc;</div><div class='add'>+	u16 i2c_bus_addr;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='ctx'> 	if (!data || (mem_addr &amp; 0xff00))</div><div class='hunk'>@@ -4082,15 +3895,13 @@ ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,</div><div class='ctx'> 	desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);</div><div class='ctx'> 	cmd-&gt;lport_num = (u8)(lport &amp; 0xff);</div><div class='ctx'> 	cmd-&gt;lport_num_valid = (u8)((lport &gt;&gt; 8) &amp; 0x01);</div><div class='del'>-	cmd-&gt;i2c_bus_addr = cpu_to_le16(((bus_addr &gt;&gt; 1) &amp;</div><div class='del'>-					 ICE_AQC_SFF_I2CBUS_7BIT_M) |</div><div class='del'>-					((set_page &lt;&lt;</div><div class='del'>-					  ICE_AQC_SFF_SET_EEPROM_PAGE_S) &amp;</div><div class='del'>-					 ICE_AQC_SFF_SET_EEPROM_PAGE_M));</div><div class='del'>-	cmd-&gt;i2c_mem_addr = cpu_to_le16(mem_addr &amp; 0xff);</div><div class='del'>-	cmd-&gt;eeprom_page = cpu_to_le16((u16)page &lt;&lt; ICE_AQC_SFF_EEPROM_PAGE_S);</div><div class='add'>+	i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr &gt;&gt; 1) |</div><div class='add'>+		       FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page);</div><div class='ctx'> 	if (write)</div><div class='del'>-		cmd-&gt;i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);</div><div class='add'>+		i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE;</div><div class='add'>+	cmd-&gt;i2c_bus_addr = cpu_to_le16(i2c_bus_addr);</div><div class='add'>+	cmd-&gt;i2c_mem_addr = cpu_to_le16(mem_addr &amp; 0xff);</div><div class='add'>+	cmd-&gt;eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M);</div><div class='ctx'> </div><div class='ctx'> 	status = ice_aq_send_cmd(hw, &amp;desc, data, length, cd);</div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -4345,6 +4156,7 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,</div><div class='ctx'> 	struct ice_aqc_dis_txq_item *item;</div><div class='ctx'> 	struct ice_aqc_dis_txqs *cmd;</div><div class='ctx'> 	struct ice_aq_desc desc;</div><div class='add'>+	u16 vmvf_and_timeout;</div><div class='ctx'> 	u16 i, sz = 0;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='hunk'>@@ -4360,27 +4172,26 @@ ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;num_entries = num_qgrps;</div><div class='ctx'> </div><div class='del'>-	cmd-&gt;vmvf_and_timeout = cpu_to_le16((5 &lt;&lt; ICE_AQC_Q_DIS_TIMEOUT_S) &amp;</div><div class='del'>-					    ICE_AQC_Q_DIS_TIMEOUT_M);</div><div class='add'>+	vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5);</div><div class='ctx'> </div><div class='ctx'> 	switch (rst_src) {</div><div class='ctx'> 	case ICE_VM_RESET:</div><div class='ctx'> 		cmd-&gt;cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;</div><div class='del'>-		cmd-&gt;vmvf_and_timeout |=</div><div class='del'>-			cpu_to_le16(vmvf_num &amp; ICE_AQC_Q_DIS_VMVF_NUM_M);</div><div class='add'>+		vmvf_and_timeout |= vmvf_num &amp; ICE_AQC_Q_DIS_VMVF_NUM_M;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_VF_RESET:</div><div class='ctx'> 		cmd-&gt;cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;</div><div class='ctx'> 		/* In this case, FW expects vmvf_num to be absolute VF ID */</div><div class='del'>-		cmd-&gt;vmvf_and_timeout |=</div><div class='del'>-			cpu_to_le16((vmvf_num + hw-&gt;func_caps.vf_base_id) &amp;</div><div class='del'>-				    ICE_AQC_Q_DIS_VMVF_NUM_M);</div><div class='add'>+		vmvf_and_timeout |= (vmvf_num + hw-&gt;func_caps.vf_base_id) &amp;</div><div class='add'>+				    ICE_AQC_Q_DIS_VMVF_NUM_M;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_NO_RESET:</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	cmd-&gt;vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout);</div><div class='add'>+</div><div class='ctx'> 	/* flush pipe on time out */</div><div class='ctx'> 	cmd-&gt;cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;</div><div class='ctx'> 	/* If no queue group info, we are in a reset flow. Issue the AQ */</div><div class='hunk'>@@ -4455,10 +4266,8 @@ ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,</div><div class='ctx'> 	cmd-&gt;cmd_type = ICE_AQC_Q_CFG_TC_CHNG;</div><div class='ctx'> 	cmd-&gt;num_qs = num_qs;</div><div class='ctx'> 	cmd-&gt;port_num_chng = (oldport &amp; ICE_AQC_Q_CFG_SRC_PRT_M);</div><div class='del'>-	cmd-&gt;port_num_chng |= (newport &lt;&lt; ICE_AQC_Q_CFG_DST_PRT_S) &amp;</div><div class='del'>-			      ICE_AQC_Q_CFG_DST_PRT_M;</div><div class='del'>-	cmd-&gt;time_out = (5 &lt;&lt; ICE_AQC_Q_CFG_TIMEOUT_S) &amp;</div><div class='del'>-			ICE_AQC_Q_CFG_TIMEOUT_M;</div><div class='add'>+	cmd-&gt;port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport);</div><div class='add'>+	cmd-&gt;time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5);</div><div class='ctx'> 	cmd-&gt;blocked_cgds = 0;</div><div class='ctx'> </div><div class='ctx'> 	status = ice_aq_send_cmd(hw, &amp;desc, buf, buf_size, cd);</div><div class='hunk'>@@ -5332,7 +5141,6 @@ ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,</div><div class='ctx'> 			   u8 *eec_mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_aqc_get_cgu_dpll_status *cmd;</div><div class='del'>-	const s64 nsec_per_psec = 1000LL;</div><div class='ctx'> 	struct ice_aq_desc desc;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='hunk'>@@ -5348,8 +5156,7 @@ ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,</div><div class='ctx'> 		*phase_offset = le32_to_cpu(cmd-&gt;phase_offset_h);</div><div class='ctx'> 		*phase_offset &lt;&lt;= 32;</div><div class='ctx'> 		*phase_offset += le32_to_cpu(cmd-&gt;phase_offset_l);</div><div class='del'>-		*phase_offset = div64_s64(sign_extend64(*phase_offset, 47),</div><div class='del'>-					  nsec_per_psec);</div><div class='add'>+		*phase_offset = sign_extend64(*phase_offset, 47);</div><div class='ctx'> 		*eec_mode = cmd-&gt;eec_mode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5541,6 +5348,35 @@ ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_aq_get_sensor_reading</div><div class='add'>+ * @hw: pointer to the HW struct</div><div class='add'>+ * @data: pointer to data to be read from the sensor</div><div class='add'>+ *</div><div class='add'>+ * Get sensor reading (0x0632)</div><div class='add'>+ */</div><div class='add'>+int ice_aq_get_sensor_reading(struct ice_hw *hw,</div><div class='add'>+			      struct ice_aqc_get_sensor_reading_resp *data)</div><div class='add'>+{</div><div class='add'>+	struct ice_aqc_get_sensor_reading *cmd;</div><div class='add'>+	struct ice_aq_desc desc;</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_get_sensor_reading);</div><div class='add'>+	cmd = &amp;desc.params.get_sensor_reading;</div><div class='add'>+#define ICE_INTERNAL_TEMP_SENSOR_FORMAT	0</div><div class='add'>+#define ICE_INTERNAL_TEMP_SENSOR	0</div><div class='add'>+	cmd-&gt;sensor = ICE_INTERNAL_TEMP_SENSOR;</div><div class='add'>+	cmd-&gt;format = ICE_INTERNAL_TEMP_SENSOR_FORMAT;</div><div class='add'>+</div><div class='add'>+	status = ice_aq_send_cmd(hw, &amp;desc, NULL, 0, NULL);</div><div class='add'>+	if (!status)</div><div class='add'>+		memcpy(data, &amp;desc.params.get_sensor_reading_resp,</div><div class='add'>+		       sizeof(*data));</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_replay_pre_init - replay pre initialization</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  *</div><div class='hunk'>@@ -5935,7 +5771,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='del'>-	ldo-&gt;options = buf &amp; ICE_LINK_OVERRIDE_OPT_M;</div><div class='add'>+	ldo-&gt;options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf);</div><div class='ctx'> 	ldo-&gt;phy_config = (buf &amp; ICE_LINK_OVERRIDE_PHY_CFG_M) &gt;&gt;</div><div class='ctx'> 		ICE_LINK_OVERRIDE_PHY_CFG_S;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h<br/>index 31fdcac33986..3e933f75e948 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_common.h</a></div><div class='hunk'>@@ -6,6 +6,7 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "ice.h"</div><div class='ctx'> #include "ice_type.h"</div><div class='ctx'> #include "ice_nvm.h"</div><div class='ctx'> #include "ice_flex_pipe.h"</div><div class='hunk'>@@ -199,7 +200,6 @@ ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,</div><div class='ctx'> 		   struct ice_sq_cd *cd);</div><div class='ctx'> int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);</div><div class='ctx'> void ice_replay_post(struct ice_hw *hw);</div><div class='del'>-void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);</div><div class='ctx'> struct ice_q_ctx *</div><div class='ctx'> ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);</div><div class='ctx'> int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in);</div><div class='hunk'>@@ -241,6 +241,8 @@ ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,</div><div class='ctx'> int</div><div class='ctx'> ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,</div><div class='ctx'> 			   u8 *flags, u16 *node_handle);</div><div class='add'>+int ice_aq_get_sensor_reading(struct ice_hw *hw,</div><div class='add'>+			      struct ice_aqc_get_sensor_reading_resp *data);</div><div class='ctx'> void</div><div class='ctx'> ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,</div><div class='ctx'> 		  u64 *prev_stat, u64 *cur_stat);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_dcb.c b/drivers/net/ethernet/intel/ice/ice_dcb.c<br/>index 396e555023aa..74418c445cc4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_dcb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb.c</a></div><div class='hunk'>@@ -35,8 +35,7 @@ ice_aq_get_lldp_mib(struct ice_hw *hw, u8 bridge_type, u8 mib_type, void *buf,</div><div class='ctx'> 	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_lldp_get_mib);</div><div class='ctx'> </div><div class='ctx'> 	cmd-&gt;type = mib_type &amp; ICE_AQ_LLDP_MIB_TYPE_M;</div><div class='del'>-	cmd-&gt;type |= (bridge_type &lt;&lt; ICE_AQ_LLDP_BRID_TYPE_S) &amp;</div><div class='del'>-		ICE_AQ_LLDP_BRID_TYPE_M;</div><div class='add'>+	cmd-&gt;type |= FIELD_PREP(ICE_AQ_LLDP_BRID_TYPE_M, bridge_type);</div><div class='ctx'> </div><div class='ctx'> 	desc.datalen = cpu_to_le16(buf_size);</div><div class='ctx'> </div><div class='hunk'>@@ -147,8 +146,7 @@ static u8 ice_get_dcbx_status(struct ice_hw *hw)</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, PRTDCB_GENS);</div><div class='del'>-	return (u8)((reg &amp; PRTDCB_GENS_DCBX_STATUS_M) &gt;&gt;</div><div class='del'>-		    PRTDCB_GENS_DCBX_STATUS_S);</div><div class='add'>+	return FIELD_GET(PRTDCB_GENS_DCBX_STATUS_M, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -174,11 +172,9 @@ ice_parse_ieee_ets_common_tlv(u8 *buf, struct ice_dcb_ets_cfg *ets_cfg)</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='ctx'> 		ets_cfg-&gt;prio_table[i * 2] =</div><div class='del'>-			((buf[offset] &amp; ICE_IEEE_ETS_PRIO_1_M) &gt;&gt;</div><div class='del'>-			 ICE_IEEE_ETS_PRIO_1_S);</div><div class='add'>+			FIELD_GET(ICE_IEEE_ETS_PRIO_1_M, buf[offset]);</div><div class='ctx'> 		ets_cfg-&gt;prio_table[i * 2 + 1] =</div><div class='del'>-			((buf[offset] &amp; ICE_IEEE_ETS_PRIO_0_M) &gt;&gt;</div><div class='del'>-			 ICE_IEEE_ETS_PRIO_0_S);</div><div class='add'>+			FIELD_GET(ICE_IEEE_ETS_PRIO_0_M, buf[offset]);</div><div class='ctx'> 		offset++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -222,11 +218,9 @@ ice_parse_ieee_etscfg_tlv(struct ice_lldp_org_tlv *tlv,</div><div class='ctx'> 	 * |1bit | 1bit|3 bits|3bits|</div><div class='ctx'> 	 */</div><div class='ctx'> 	etscfg = &amp;dcbcfg-&gt;etscfg;</div><div class='del'>-	etscfg-&gt;willing = ((buf[0] &amp; ICE_IEEE_ETS_WILLING_M) &gt;&gt;</div><div class='del'>-			   ICE_IEEE_ETS_WILLING_S);</div><div class='del'>-	etscfg-&gt;cbs = ((buf[0] &amp; ICE_IEEE_ETS_CBS_M) &gt;&gt; ICE_IEEE_ETS_CBS_S);</div><div class='del'>-	etscfg-&gt;maxtcs = ((buf[0] &amp; ICE_IEEE_ETS_MAXTC_M) &gt;&gt;</div><div class='del'>-			  ICE_IEEE_ETS_MAXTC_S);</div><div class='add'>+	etscfg-&gt;willing = FIELD_GET(ICE_IEEE_ETS_WILLING_M, buf[0]);</div><div class='add'>+	etscfg-&gt;cbs = FIELD_GET(ICE_IEEE_ETS_CBS_M, buf[0]);</div><div class='add'>+	etscfg-&gt;maxtcs = FIELD_GET(ICE_IEEE_ETS_MAXTC_M, buf[0]);</div><div class='ctx'> </div><div class='ctx'> 	/* Begin parsing at Priority Assignment Table (offset 1 in buf) */</div><div class='ctx'> 	ice_parse_ieee_ets_common_tlv(&amp;buf[1], etscfg);</div><div class='hunk'>@@ -268,11 +262,9 @@ ice_parse_ieee_pfccfg_tlv(struct ice_lldp_org_tlv *tlv,</div><div class='ctx'> 	 * -----------------------------------------</div><div class='ctx'> 	 * |1bit | 1bit|2 bits|4bits| 1 octet      |</div><div class='ctx'> 	 */</div><div class='del'>-	dcbcfg-&gt;pfc.willing = ((buf[0] &amp; ICE_IEEE_PFC_WILLING_M) &gt;&gt;</div><div class='del'>-			       ICE_IEEE_PFC_WILLING_S);</div><div class='del'>-	dcbcfg-&gt;pfc.mbc = ((buf[0] &amp; ICE_IEEE_PFC_MBC_M) &gt;&gt; ICE_IEEE_PFC_MBC_S);</div><div class='del'>-	dcbcfg-&gt;pfc.pfccap = ((buf[0] &amp; ICE_IEEE_PFC_CAP_M) &gt;&gt;</div><div class='del'>-			      ICE_IEEE_PFC_CAP_S);</div><div class='add'>+	dcbcfg-&gt;pfc.willing = FIELD_GET(ICE_IEEE_PFC_WILLING_M, buf[0]);</div><div class='add'>+	dcbcfg-&gt;pfc.mbc = FIELD_GET(ICE_IEEE_PFC_MBC_M, buf[0]);</div><div class='add'>+	dcbcfg-&gt;pfc.pfccap = FIELD_GET(ICE_IEEE_PFC_CAP_M, buf[0]);</div><div class='ctx'> 	dcbcfg-&gt;pfc.pfcena = buf[1];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -294,7 +286,7 @@ ice_parse_ieee_app_tlv(struct ice_lldp_org_tlv *tlv,</div><div class='ctx'> 	u8 *buf;</div><div class='ctx'> </div><div class='ctx'> 	typelen = ntohs(tlv-&gt;typelen);</div><div class='del'>-	len = ((typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S);</div><div class='add'>+	len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 	buf = tlv-&gt;tlvinfo;</div><div class='ctx'> </div><div class='ctx'> 	/* Removing sizeof(ouisubtype) and reserved byte from len.</div><div class='hunk'>@@ -314,12 +306,10 @@ ice_parse_ieee_app_tlv(struct ice_lldp_org_tlv *tlv,</div><div class='ctx'> 	 *        -----------------------------------------</div><div class='ctx'> 	 */</div><div class='ctx'> 	while (offset &lt; len) {</div><div class='del'>-		dcbcfg-&gt;app[i].priority = ((buf[offset] &amp;</div><div class='del'>-					    ICE_IEEE_APP_PRIO_M) &gt;&gt;</div><div class='del'>-					   ICE_IEEE_APP_PRIO_S);</div><div class='del'>-		dcbcfg-&gt;app[i].selector = ((buf[offset] &amp;</div><div class='del'>-					    ICE_IEEE_APP_SEL_M) &gt;&gt;</div><div class='del'>-					   ICE_IEEE_APP_SEL_S);</div><div class='add'>+		dcbcfg-&gt;app[i].priority = FIELD_GET(ICE_IEEE_APP_PRIO_M,</div><div class='add'>+						    buf[offset]);</div><div class='add'>+		dcbcfg-&gt;app[i].selector = FIELD_GET(ICE_IEEE_APP_SEL_M,</div><div class='add'>+						    buf[offset]);</div><div class='ctx'> 		dcbcfg-&gt;app[i].prot_id = (buf[offset + 1] &lt;&lt; 0x8) |</div><div class='ctx'> 			buf[offset + 2];</div><div class='ctx'> 		/* Move to next app */</div><div class='hunk'>@@ -347,8 +337,7 @@ ice_parse_ieee_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	u8 subtype;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	subtype = (u8)((ouisubtype &amp; ICE_LLDP_TLV_SUBTYPE_M) &gt;&gt;</div><div class='del'>-		       ICE_LLDP_TLV_SUBTYPE_S);</div><div class='add'>+	subtype = FIELD_GET(ICE_LLDP_TLV_SUBTYPE_M, ouisubtype);</div><div class='ctx'> 	switch (subtype) {</div><div class='ctx'> 	case ICE_IEEE_SUBTYPE_ETS_CFG:</div><div class='ctx'> 		ice_parse_ieee_etscfg_tlv(tlv, dcbcfg);</div><div class='hunk'>@@ -399,11 +388,9 @@ ice_parse_cee_pgcfg_tlv(struct ice_cee_feat_tlv *tlv,</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; 4; i++) {</div><div class='ctx'> 		etscfg-&gt;prio_table[i * 2] =</div><div class='del'>-			((buf[offset] &amp; ICE_CEE_PGID_PRIO_1_M) &gt;&gt;</div><div class='del'>-			 ICE_CEE_PGID_PRIO_1_S);</div><div class='add'>+			FIELD_GET(ICE_CEE_PGID_PRIO_1_M, buf[offset]);</div><div class='ctx'> 		etscfg-&gt;prio_table[i * 2 + 1] =</div><div class='del'>-			((buf[offset] &amp; ICE_CEE_PGID_PRIO_0_M) &gt;&gt;</div><div class='del'>-			 ICE_CEE_PGID_PRIO_0_S);</div><div class='add'>+			FIELD_GET(ICE_CEE_PGID_PRIO_0_M, buf[offset]);</div><div class='ctx'> 		offset++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -466,7 +453,7 @@ ice_parse_cee_app_tlv(struct ice_cee_feat_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	typelen = ntohs(tlv-&gt;hdr.typelen);</div><div class='del'>-	len = ((typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S);</div><div class='add'>+	len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> </div><div class='ctx'> 	dcbcfg-&gt;numapps = len / sizeof(*app);</div><div class='ctx'> 	if (!dcbcfg-&gt;numapps)</div><div class='hunk'>@@ -521,14 +508,13 @@ ice_parse_cee_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	u32 ouisubtype;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	subtype = (u8)((ouisubtype &amp; ICE_LLDP_TLV_SUBTYPE_M) &gt;&gt;</div><div class='del'>-		       ICE_LLDP_TLV_SUBTYPE_S);</div><div class='add'>+	subtype = FIELD_GET(ICE_LLDP_TLV_SUBTYPE_M, ouisubtype);</div><div class='ctx'> 	/* Return if not CEE DCBX */</div><div class='ctx'> 	if (subtype != ICE_CEE_DCBX_TYPE)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	typelen = ntohs(tlv-&gt;typelen);</div><div class='del'>-	tlvlen = ((typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S);</div><div class='add'>+	tlvlen = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 	len = sizeof(tlv-&gt;typelen) + sizeof(ouisubtype) +</div><div class='ctx'> 		sizeof(struct ice_cee_ctrl_tlv);</div><div class='ctx'> 	/* Return if no CEE DCBX Feature TLVs */</div><div class='hunk'>@@ -540,9 +526,8 @@ ice_parse_cee_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 		u16 sublen;</div><div class='ctx'> </div><div class='ctx'> 		typelen = ntohs(sub_tlv-&gt;hdr.typelen);</div><div class='del'>-		sublen = ((typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S);</div><div class='del'>-		subtype = (u8)((typelen &amp; ICE_LLDP_TLV_TYPE_M) &gt;&gt;</div><div class='del'>-			       ICE_LLDP_TLV_TYPE_S);</div><div class='add'>+		sublen = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='add'>+		subtype = FIELD_GET(ICE_LLDP_TLV_TYPE_M, typelen);</div><div class='ctx'> 		switch (subtype) {</div><div class='ctx'> 		case ICE_CEE_SUBTYPE_PG_CFG:</div><div class='ctx'> 			ice_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);</div><div class='hunk'>@@ -579,7 +564,7 @@ ice_parse_org_tlv(struct ice_lldp_org_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	u32 oui;</div><div class='ctx'> </div><div class='ctx'> 	ouisubtype = ntohl(tlv-&gt;ouisubtype);</div><div class='del'>-	oui = ((ouisubtype &amp; ICE_LLDP_TLV_OUI_M) &gt;&gt; ICE_LLDP_TLV_OUI_S);</div><div class='add'>+	oui = FIELD_GET(ICE_LLDP_TLV_OUI_M, ouisubtype);</div><div class='ctx'> 	switch (oui) {</div><div class='ctx'> 	case ICE_IEEE_8021QAZ_OUI:</div><div class='ctx'> 		ice_parse_ieee_tlv(tlv, dcbcfg);</div><div class='hunk'>@@ -616,8 +601,8 @@ static int ice_lldp_to_dcb_cfg(u8 *lldpmib, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	tlv = (struct ice_lldp_org_tlv *)lldpmib;</div><div class='ctx'> 	while (1) {</div><div class='ctx'> 		typelen = ntohs(tlv-&gt;typelen);</div><div class='del'>-		type = ((typelen &amp; ICE_LLDP_TLV_TYPE_M) &gt;&gt; ICE_LLDP_TLV_TYPE_S);</div><div class='del'>-		len = ((typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S);</div><div class='add'>+		type = FIELD_GET(ICE_LLDP_TLV_TYPE_M, typelen);</div><div class='add'>+		len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 		offset += sizeof(typelen) + len;</div><div class='ctx'> </div><div class='ctx'> 		/* END TLV or beyond LLDPDU size */</div><div class='hunk'>@@ -806,11 +791,11 @@ ice_cee_to_dcb_cfg(struct ice_aqc_get_cee_dcb_cfg_resp *cee_cfg,</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; ICE_MAX_TRAFFIC_CLASS / 2; i++) {</div><div class='ctx'> 		dcbcfg-&gt;etscfg.prio_table[i * 2] =</div><div class='del'>-			((cee_cfg-&gt;oper_prio_tc[i] &amp; ICE_CEE_PGID_PRIO_0_M) &gt;&gt;</div><div class='del'>-			 ICE_CEE_PGID_PRIO_0_S);</div><div class='add'>+			FIELD_GET(ICE_CEE_PGID_PRIO_0_M,</div><div class='add'>+				  cee_cfg-&gt;oper_prio_tc[i]);</div><div class='ctx'> 		dcbcfg-&gt;etscfg.prio_table[i * 2 + 1] =</div><div class='del'>-			((cee_cfg-&gt;oper_prio_tc[i] &amp; ICE_CEE_PGID_PRIO_1_M) &gt;&gt;</div><div class='del'>-			 ICE_CEE_PGID_PRIO_1_S);</div><div class='add'>+			FIELD_GET(ICE_CEE_PGID_PRIO_1_M,</div><div class='add'>+				  cee_cfg-&gt;oper_prio_tc[i]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ice_for_each_traffic_class(i) {</div><div class='hunk'>@@ -982,7 +967,7 @@ void ice_get_dcb_cfg_from_mib_change(struct ice_port_info *pi,</div><div class='ctx'> </div><div class='ctx'> 	mib = (struct ice_aqc_lldp_get_mib *)&amp;event-&gt;desc.params.raw;</div><div class='ctx'> </div><div class='del'>-	change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M,  mib-&gt;type);</div><div class='add'>+	change_type = FIELD_GET(ICE_AQ_LLDP_MIB_TYPE_M, mib-&gt;type);</div><div class='ctx'> 	if (change_type == ICE_AQ_LLDP_MIB_REMOTE)</div><div class='ctx'> 		dcbx_cfg = &amp;pi-&gt;qos_cfg.remote_dcbx_cfg;</div><div class='ctx'> </div><div class='hunk'>@@ -1483,7 +1468,7 @@ ice_dcb_cfg_to_lldp(u8 *lldpmib, u16 *miblen, struct ice_dcbx_cfg *dcbcfg)</div><div class='ctx'> 	while (1) {</div><div class='ctx'> 		ice_add_dcb_tlv(tlv, dcbcfg, tlvid++);</div><div class='ctx'> 		typelen = ntohs(tlv-&gt;typelen);</div><div class='del'>-		len = (typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S;</div><div class='add'>+		len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 		if (len)</div><div class='ctx'> 			offset += len + 2;</div><div class='ctx'> 		/* END TLV or beyond LLDPDU size */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c<br/>index 850db8e0e6b0..6e20ee610022 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_dcb_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb_lib.c</a></div><div class='hunk'>@@ -934,7 +934,7 @@ ice_tx_prepare_vlan_flags_dcb(struct ice_tx_ring *tx_ring,</div><div class='ctx'> 	    skb-&gt;priority != TC_PRIO_CONTROL) {</div><div class='ctx'> 		first-&gt;vid &amp;= ~VLAN_PRIO_MASK;</div><div class='ctx'> 		/* Mask the lower 3 bits to set the 802.1p priority */</div><div class='del'>-		first-&gt;vid |= (skb-&gt;priority &lt;&lt; VLAN_PRIO_SHIFT) &amp; VLAN_PRIO_MASK;</div><div class='add'>+		first-&gt;vid |= FIELD_PREP(VLAN_PRIO_MASK, skb-&gt;priority);</div><div class='ctx'> 		/* if this is not already set it means a VLAN 0 + priority needs</div><div class='ctx'> 		 * to be offloaded</div><div class='ctx'> 		 */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_nl.c b/drivers/net/ethernet/intel/ice/ice_dcb_nl.c<br/>index e1fbc6de452d..6d50b90a7359 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb_nl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_dcb_nl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dcb_nl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dcb_nl.c</a></div><div class='hunk'>@@ -227,7 +227,7 @@ static void ice_get_pfc_delay(struct ice_hw *hw, u16 *delay)</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, PRTDCB_GENC);</div><div class='del'>-	*delay = (u16)((val &amp; PRTDCB_GENC_PFCLDA_M) &gt;&gt; PRTDCB_GENC_PFCLDA_S);</div><div class='add'>+	*delay = FIELD_GET(PRTDCB_GENC_PFCLDA_M, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_debugfs.c b/drivers/net/ethernet/intel/ice/ice_debugfs.c<br/>new file mode 100644<br/>index 000000000000..c2bfba6b9ead<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_debugfs.c</a></div><div class='hunk'>@@ -0,0 +1,667 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright (c) 2022, Intel Corporation. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/fs.h&gt;</div><div class='add'>+#include &lt;linux/debugfs.h&gt;</div><div class='add'>+#include &lt;linux/random.h&gt;</div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='add'>+#include "ice.h"</div><div class='add'>+</div><div class='add'>+static struct dentry *ice_debugfs_root;</div><div class='add'>+</div><div class='add'>+/* create a define that has an extra module that doesn't really exist. this</div><div class='add'>+ * is so we can add a module 'all' to easily enable/disable all the modules</div><div class='add'>+ */</div><div class='add'>+#define ICE_NR_FW_LOG_MODULES (ICE_AQC_FW_LOG_ID_MAX + 1)</div><div class='add'>+</div><div class='add'>+/* the ordering in this array is important. it matches the ordering of the</div><div class='add'>+ * values in the FW so the index is the same value as in ice_aqc_fw_logging_mod</div><div class='add'>+ */</div><div class='add'>+static const char * const ice_fwlog_module_string[] = {</div><div class='add'>+	"general",</div><div class='add'>+	"ctrl",</div><div class='add'>+	"link",</div><div class='add'>+	"link_topo",</div><div class='add'>+	"dnl",</div><div class='add'>+	"i2c",</div><div class='add'>+	"sdp",</div><div class='add'>+	"mdio",</div><div class='add'>+	"adminq",</div><div class='add'>+	"hdma",</div><div class='add'>+	"lldp",</div><div class='add'>+	"dcbx",</div><div class='add'>+	"dcb",</div><div class='add'>+	"xlr",</div><div class='add'>+	"nvm",</div><div class='add'>+	"auth",</div><div class='add'>+	"vpd",</div><div class='add'>+	"iosf",</div><div class='add'>+	"parser",</div><div class='add'>+	"sw",</div><div class='add'>+	"scheduler",</div><div class='add'>+	"txq",</div><div class='add'>+	"rsvd",</div><div class='add'>+	"post",</div><div class='add'>+	"watchdog",</div><div class='add'>+	"task_dispatch",</div><div class='add'>+	"mng",</div><div class='add'>+	"synce",</div><div class='add'>+	"health",</div><div class='add'>+	"tsdrv",</div><div class='add'>+	"pfreg",</div><div class='add'>+	"mdlver",</div><div class='add'>+	"all",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* the ordering in this array is important. it matches the ordering of the</div><div class='add'>+ * values in the FW so the index is the same value as in ice_fwlog_level</div><div class='add'>+ */</div><div class='add'>+static const char * const ice_fwlog_level_string[] = {</div><div class='add'>+	"none",</div><div class='add'>+	"error",</div><div class='add'>+	"warning",</div><div class='add'>+	"normal",</div><div class='add'>+	"verbose",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* the order in this array is important. it matches the ordering of the</div><div class='add'>+ * values in the FW so the index is the same value as in ice_fwlog_level</div><div class='add'>+ */</div><div class='add'>+static const char * const ice_fwlog_log_size[] = {</div><div class='add'>+	"128K",</div><div class='add'>+	"256K",</div><div class='add'>+	"512K",</div><div class='add'>+	"1M",</div><div class='add'>+	"2M",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_print_module_cfg - print current FW logging module configuration</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @module: module to print</div><div class='add'>+ * @s: the seq file to put data into</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_fwlog_print_module_cfg(struct ice_hw *hw, int module, struct seq_file *s)</div><div class='add'>+{</div><div class='add'>+	struct ice_fwlog_cfg *cfg = &amp;hw-&gt;fwlog_cfg;</div><div class='add'>+	struct ice_fwlog_module_entry *entry;</div><div class='add'>+</div><div class='add'>+	if (module != ICE_AQC_FW_LOG_ID_MAX) {</div><div class='add'>+		entry =	&amp;cfg-&gt;module_entries[module];</div><div class='add'>+</div><div class='add'>+		seq_printf(s, "\tModule: %s, Log Level: %s\n",</div><div class='add'>+			   ice_fwlog_module_string[entry-&gt;module_id],</div><div class='add'>+			   ice_fwlog_level_string[entry-&gt;log_level]);</div><div class='add'>+	} else {</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; ICE_AQC_FW_LOG_ID_MAX; i++) {</div><div class='add'>+			entry =	&amp;cfg-&gt;module_entries[i];</div><div class='add'>+</div><div class='add'>+			seq_printf(s, "\tModule: %s, Log Level: %s\n",</div><div class='add'>+				   ice_fwlog_module_string[entry-&gt;module_id],</div><div class='add'>+				   ice_fwlog_level_string[entry-&gt;log_level]);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ice_find_module_by_dentry(struct ice_pf *pf, struct dentry *d)</div><div class='add'>+{</div><div class='add'>+	int i, module;</div><div class='add'>+</div><div class='add'>+	module = -1;</div><div class='add'>+	/* find the module based on the dentry */</div><div class='add'>+	for (i = 0; i &lt; ICE_NR_FW_LOG_MODULES; i++) {</div><div class='add'>+		if (d == pf-&gt;ice_debugfs_pf_fwlog_modules[i]) {</div><div class='add'>+			module = i;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return module;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_module_show - read from 'module' file</div><div class='add'>+ * @s: the opened file</div><div class='add'>+ * @v: pointer to the offset</div><div class='add'>+ */</div><div class='add'>+static int ice_debugfs_module_show(struct seq_file *s, void *v)</div><div class='add'>+{</div><div class='add'>+	const struct file *filp = s-&gt;file;</div><div class='add'>+	struct dentry *dentry;</div><div class='add'>+	struct ice_pf *pf;</div><div class='add'>+	int module;</div><div class='add'>+</div><div class='add'>+	dentry = file_dentry(filp);</div><div class='add'>+	pf = s-&gt;private;</div><div class='add'>+</div><div class='add'>+	module = ice_find_module_by_dentry(pf, dentry);</div><div class='add'>+	if (module &lt; 0) {</div><div class='add'>+		dev_info(ice_pf_to_dev(pf), "unknown module\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ice_fwlog_print_module_cfg(&amp;pf-&gt;hw, module, s);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ice_debugfs_module_open(struct inode *inode, struct file *filp)</div><div class='add'>+{</div><div class='add'>+	return single_open(filp, ice_debugfs_module_show, inode-&gt;i_private);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_module_write - write into 'module' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buf: where to find the user's data</div><div class='add'>+ * @count: the length of the user's data</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t</div><div class='add'>+ice_debugfs_module_write(struct file *filp, const char __user *buf,</div><div class='add'>+			 size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = file_inode(filp)-&gt;i_private;</div><div class='add'>+	struct dentry *dentry = file_dentry(filp);</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	char user_val[16], *cmd_buf;</div><div class='add'>+	int module, log_level, cnt;</div><div class='add'>+</div><div class='add'>+	/* don't allow partial writes or invalid input */</div><div class='add'>+	if (*ppos != 0 || count &gt; 8)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd_buf = memdup_user(buf, count);</div><div class='add'>+	if (IS_ERR(cmd_buf))</div><div class='add'>+		return PTR_ERR(cmd_buf);</div><div class='add'>+</div><div class='add'>+	module = ice_find_module_by_dentry(pf, dentry);</div><div class='add'>+	if (module &lt; 0) {</div><div class='add'>+		dev_info(dev, "unknown module\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cnt = sscanf(cmd_buf, "%s", user_val);</div><div class='add'>+	if (cnt != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	log_level = sysfs_match_string(ice_fwlog_level_string, user_val);</div><div class='add'>+	if (log_level &lt; 0) {</div><div class='add'>+		dev_info(dev, "unknown log level '%s'\n", user_val);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (module != ICE_AQC_FW_LOG_ID_MAX) {</div><div class='add'>+		ice_pf_fwlog_update_module(pf, log_level, module);</div><div class='add'>+	} else {</div><div class='add'>+		/* the module 'all' is a shortcut so that we can set</div><div class='add'>+		 * all of the modules to the same level quickly</div><div class='add'>+		 */</div><div class='add'>+		int i;</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; ICE_AQC_FW_LOG_ID_MAX; i++)</div><div class='add'>+			ice_pf_fwlog_update_module(pf, log_level, i);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations ice_debugfs_module_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open  = ice_debugfs_module_open,</div><div class='add'>+	.read = seq_read,</div><div class='add'>+	.release = single_release,</div><div class='add'>+	.write = ice_debugfs_module_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_nr_messages_read - read from 'nr_messages' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buffer: where to write the data for the user to read</div><div class='add'>+ * @count: the size of the user's buffer</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t ice_debugfs_nr_messages_read(struct file *filp,</div><div class='add'>+					    char __user *buffer, size_t count,</div><div class='add'>+					    loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char buff[32] = {};</div><div class='add'>+</div><div class='add'>+	snprintf(buff, sizeof(buff), "%d\n",</div><div class='add'>+		 hw-&gt;fwlog_cfg.log_resolution);</div><div class='add'>+</div><div class='add'>+	return simple_read_from_buffer(buffer, count, ppos, buff, strlen(buff));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_nr_messages_write - write into 'nr_messages' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buf: where to find the user's data</div><div class='add'>+ * @count: the length of the user's data</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t</div><div class='add'>+ice_debugfs_nr_messages_write(struct file *filp, const char __user *buf,</div><div class='add'>+			      size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char user_val[8], *cmd_buf;</div><div class='add'>+	s16 nr_messages;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	/* don't allow partial writes or invalid input */</div><div class='add'>+	if (*ppos != 0 || count &gt; 4)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd_buf = memdup_user(buf, count);</div><div class='add'>+	if (IS_ERR(cmd_buf))</div><div class='add'>+		return PTR_ERR(cmd_buf);</div><div class='add'>+</div><div class='add'>+	ret = sscanf(cmd_buf, "%s", user_val);</div><div class='add'>+	if (ret != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = kstrtos16(user_val, 0, &amp;nr_messages);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (nr_messages &lt; ICE_AQC_FW_LOG_MIN_RESOLUTION ||</div><div class='add'>+	    nr_messages &gt; ICE_AQC_FW_LOG_MAX_RESOLUTION) {</div><div class='add'>+		dev_err(dev, "Invalid FW log number of messages %d, value must be between %d - %d\n",</div><div class='add'>+			nr_messages, ICE_AQC_FW_LOG_MIN_RESOLUTION,</div><div class='add'>+			ICE_AQC_FW_LOG_MAX_RESOLUTION);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	hw-&gt;fwlog_cfg.log_resolution = nr_messages;</div><div class='add'>+</div><div class='add'>+	return count;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations ice_debugfs_nr_messages_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open  = simple_open,</div><div class='add'>+	.read = ice_debugfs_nr_messages_read,</div><div class='add'>+	.write = ice_debugfs_nr_messages_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_enable_read - read from 'enable' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buffer: where to write the data for the user to read</div><div class='add'>+ * @count: the size of the user's buffer</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t ice_debugfs_enable_read(struct file *filp,</div><div class='add'>+				       char __user *buffer, size_t count,</div><div class='add'>+				       loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char buff[32] = {};</div><div class='add'>+</div><div class='add'>+	snprintf(buff, sizeof(buff), "%u\n",</div><div class='add'>+		 (u16)(hw-&gt;fwlog_cfg.options &amp;</div><div class='add'>+		 ICE_FWLOG_OPTION_IS_REGISTERED) &gt;&gt; 3);</div><div class='add'>+</div><div class='add'>+	return simple_read_from_buffer(buffer, count, ppos, buff, strlen(buff));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_enable_write - write into 'enable' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buf: where to find the user's data</div><div class='add'>+ * @count: the length of the user's data</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t</div><div class='add'>+ice_debugfs_enable_write(struct file *filp, const char __user *buf,</div><div class='add'>+			 size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char user_val[8], *cmd_buf;</div><div class='add'>+	bool enable;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	/* don't allow partial writes or invalid input */</div><div class='add'>+	if (*ppos != 0 || count &gt; 2)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd_buf = memdup_user(buf, count);</div><div class='add'>+	if (IS_ERR(cmd_buf))</div><div class='add'>+		return PTR_ERR(cmd_buf);</div><div class='add'>+</div><div class='add'>+	ret = sscanf(cmd_buf, "%s", user_val);</div><div class='add'>+	if (ret != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ret = kstrtobool(user_val, &amp;enable);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto enable_write_error;</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		hw-&gt;fwlog_cfg.options |= ICE_FWLOG_OPTION_ARQ_ENA;</div><div class='add'>+	else</div><div class='add'>+		hw-&gt;fwlog_cfg.options &amp;= ~ICE_FWLOG_OPTION_ARQ_ENA;</div><div class='add'>+</div><div class='add'>+	ret = ice_fwlog_set(hw, &amp;hw-&gt;fwlog_cfg);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto enable_write_error;</div><div class='add'>+</div><div class='add'>+	if (enable)</div><div class='add'>+		ret = ice_fwlog_register(hw);</div><div class='add'>+	else</div><div class='add'>+		ret = ice_fwlog_unregister(hw);</div><div class='add'>+</div><div class='add'>+	if (ret)</div><div class='add'>+		goto enable_write_error;</div><div class='add'>+</div><div class='add'>+	/* if we get here, nothing went wrong; return count since we didn't</div><div class='add'>+	 * really write anything</div><div class='add'>+	 */</div><div class='add'>+	ret = (ssize_t)count;</div><div class='add'>+</div><div class='add'>+enable_write_error:</div><div class='add'>+	/* This function always consumes all of the written input, or produces</div><div class='add'>+	 * an error. Check and enforce this. Otherwise, the write operation</div><div class='add'>+	 * won't complete properly.</div><div class='add'>+	 */</div><div class='add'>+	if (WARN_ON(ret != (ssize_t)count &amp;&amp; ret &gt;= 0))</div><div class='add'>+		ret = -EIO;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations ice_debugfs_enable_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open  = simple_open,</div><div class='add'>+	.read = ice_debugfs_enable_read,</div><div class='add'>+	.write = ice_debugfs_enable_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_log_size_read - read from 'log_size' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buffer: where to write the data for the user to read</div><div class='add'>+ * @count: the size of the user's buffer</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t ice_debugfs_log_size_read(struct file *filp,</div><div class='add'>+					 char __user *buffer, size_t count,</div><div class='add'>+					 loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char buff[32] = {};</div><div class='add'>+	int index;</div><div class='add'>+</div><div class='add'>+	index = hw-&gt;fwlog_ring.index;</div><div class='add'>+	snprintf(buff, sizeof(buff), "%s\n", ice_fwlog_log_size[index]);</div><div class='add'>+</div><div class='add'>+	return simple_read_from_buffer(buffer, count, ppos, buff, strlen(buff));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_log_size_write - write into 'log_size' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buf: where to find the user's data</div><div class='add'>+ * @count: the length of the user's data</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t</div><div class='add'>+ice_debugfs_log_size_write(struct file *filp, const char __user *buf,</div><div class='add'>+			   size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	char user_val[8], *cmd_buf;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+	int index;</div><div class='add'>+</div><div class='add'>+	/* don't allow partial writes or invalid input */</div><div class='add'>+	if (*ppos != 0 || count &gt; 5)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	cmd_buf = memdup_user(buf, count);</div><div class='add'>+	if (IS_ERR(cmd_buf))</div><div class='add'>+		return PTR_ERR(cmd_buf);</div><div class='add'>+</div><div class='add'>+	ret = sscanf(cmd_buf, "%s", user_val);</div><div class='add'>+	if (ret != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	index = sysfs_match_string(ice_fwlog_log_size, user_val);</div><div class='add'>+	if (index &lt; 0) {</div><div class='add'>+		dev_info(dev, "Invalid log size '%s'. The value must be one of 128K, 256K, 512K, 1M, 2M\n",</div><div class='add'>+			 user_val);</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto log_size_write_error;</div><div class='add'>+	} else if (hw-&gt;fwlog_cfg.options &amp; ICE_FWLOG_OPTION_IS_REGISTERED) {</div><div class='add'>+		dev_info(dev, "FW logging is currently running. Please disable FW logging to change log_size\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto log_size_write_error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* free all the buffers and the tracking info and resize */</div><div class='add'>+	ice_fwlog_realloc_rings(hw, index);</div><div class='add'>+</div><div class='add'>+	/* if we get here, nothing went wrong; return count since we didn't</div><div class='add'>+	 * really write anything</div><div class='add'>+	 */</div><div class='add'>+	ret = (ssize_t)count;</div><div class='add'>+</div><div class='add'>+log_size_write_error:</div><div class='add'>+	/* This function always consumes all of the written input, or produces</div><div class='add'>+	 * an error. Check and enforce this. Otherwise, the write operation</div><div class='add'>+	 * won't complete properly.</div><div class='add'>+	 */</div><div class='add'>+	if (WARN_ON(ret != (ssize_t)count &amp;&amp; ret &gt;= 0))</div><div class='add'>+		ret = -EIO;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations ice_debugfs_log_size_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open  = simple_open,</div><div class='add'>+	.read = ice_debugfs_log_size_read,</div><div class='add'>+	.write = ice_debugfs_log_size_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_data_read - read from 'data' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buffer: where to write the data for the user to read</div><div class='add'>+ * @count: the size of the user's buffer</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t ice_debugfs_data_read(struct file *filp, char __user *buffer,</div><div class='add'>+				     size_t count, loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	int data_copied = 0;</div><div class='add'>+	bool done = false;</div><div class='add'>+</div><div class='add'>+	if (ice_fwlog_ring_empty(&amp;hw-&gt;fwlog_ring))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	while (!ice_fwlog_ring_empty(&amp;hw-&gt;fwlog_ring) &amp;&amp; !done) {</div><div class='add'>+		struct ice_fwlog_data *log;</div><div class='add'>+		u16 cur_buf_len;</div><div class='add'>+</div><div class='add'>+		log = &amp;hw-&gt;fwlog_ring.rings[hw-&gt;fwlog_ring.head];</div><div class='add'>+		cur_buf_len = log-&gt;data_size;</div><div class='add'>+		if (cur_buf_len &gt;= count) {</div><div class='add'>+			done = true;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (copy_to_user(buffer, log-&gt;data, cur_buf_len)) {</div><div class='add'>+			/* if there is an error then bail and return whatever</div><div class='add'>+			 * the driver has copied so far</div><div class='add'>+			 */</div><div class='add'>+			done = true;</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		data_copied += cur_buf_len;</div><div class='add'>+		buffer += cur_buf_len;</div><div class='add'>+		count -= cur_buf_len;</div><div class='add'>+		*ppos += cur_buf_len;</div><div class='add'>+		ice_fwlog_ring_increment(&amp;hw-&gt;fwlog_ring.head,</div><div class='add'>+					 hw-&gt;fwlog_ring.size);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return data_copied;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_data_write - write into 'data' file</div><div class='add'>+ * @filp: the opened file</div><div class='add'>+ * @buf: where to find the user's data</div><div class='add'>+ * @count: the length of the user's data</div><div class='add'>+ * @ppos: file position offset</div><div class='add'>+ */</div><div class='add'>+static ssize_t</div><div class='add'>+ice_debugfs_data_write(struct file *filp, const char __user *buf, size_t count,</div><div class='add'>+		       loff_t *ppos)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = filp-&gt;private_data;</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	ssize_t ret;</div><div class='add'>+</div><div class='add'>+	/* don't allow partial writes */</div><div class='add'>+	if (*ppos != 0)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* any value is allowed to clear the buffer so no need to even look at</div><div class='add'>+	 * what the value is</div><div class='add'>+	 */</div><div class='add'>+	if (!(hw-&gt;fwlog_cfg.options &amp; ICE_FWLOG_OPTION_IS_REGISTERED)) {</div><div class='add'>+		hw-&gt;fwlog_ring.head = 0;</div><div class='add'>+		hw-&gt;fwlog_ring.tail = 0;</div><div class='add'>+	} else {</div><div class='add'>+		dev_info(dev, "Can't clear FW log data while FW log running\n");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto nr_buffs_write_error;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* if we get here, nothing went wrong; return count since we didn't</div><div class='add'>+	 * really write anything</div><div class='add'>+	 */</div><div class='add'>+	ret = (ssize_t)count;</div><div class='add'>+</div><div class='add'>+nr_buffs_write_error:</div><div class='add'>+	/* This function always consumes all of the written input, or produces</div><div class='add'>+	 * an error. Check and enforce this. Otherwise, the write operation</div><div class='add'>+	 * won't complete properly.</div><div class='add'>+	 */</div><div class='add'>+	if (WARN_ON(ret != (ssize_t)count &amp;&amp; ret &gt;= 0))</div><div class='add'>+		ret = -EIO;</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct file_operations ice_debugfs_data_fops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.open  = simple_open,</div><div class='add'>+	.read = ice_debugfs_data_read,</div><div class='add'>+	.write = ice_debugfs_data_write,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_fwlog_init - setup the debugfs directory</div><div class='add'>+ * @pf: the ice that is starting up</div><div class='add'>+ */</div><div class='add'>+void ice_debugfs_fwlog_init(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	const char *name = pci_name(pf-&gt;pdev);</div><div class='add'>+	struct dentry *fw_modules_dir;</div><div class='add'>+	struct dentry **fw_modules;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* only support fw log commands on PF 0 */</div><div class='add'>+	if (pf-&gt;hw.bus.func)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* allocate space for this first because if it fails then we don't</div><div class='add'>+	 * need to unwind</div><div class='add'>+	 */</div><div class='add'>+	fw_modules = kcalloc(ICE_NR_FW_LOG_MODULES, sizeof(*fw_modules),</div><div class='add'>+			     GFP_KERNEL);</div><div class='add'>+	if (!fw_modules)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	pf-&gt;ice_debugfs_pf = debugfs_create_dir(name, ice_debugfs_root);</div><div class='add'>+	if (IS_ERR(pf-&gt;ice_debugfs_pf))</div><div class='add'>+		goto err_create_module_files;</div><div class='add'>+</div><div class='add'>+	pf-&gt;ice_debugfs_pf_fwlog = debugfs_create_dir("fwlog",</div><div class='add'>+						      pf-&gt;ice_debugfs_pf);</div><div class='add'>+	if (IS_ERR(pf-&gt;ice_debugfs_pf))</div><div class='add'>+		goto err_create_module_files;</div><div class='add'>+</div><div class='add'>+	fw_modules_dir = debugfs_create_dir("modules",</div><div class='add'>+					    pf-&gt;ice_debugfs_pf_fwlog);</div><div class='add'>+	if (IS_ERR(fw_modules_dir))</div><div class='add'>+		goto err_create_module_files;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ICE_NR_FW_LOG_MODULES; i++) {</div><div class='add'>+		fw_modules[i] = debugfs_create_file(ice_fwlog_module_string[i],</div><div class='add'>+						    0600, fw_modules_dir, pf,</div><div class='add'>+						    &amp;ice_debugfs_module_fops);</div><div class='add'>+		if (IS_ERR(fw_modules[i]))</div><div class='add'>+			goto err_create_module_files;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("nr_messages", 0600,</div><div class='add'>+			    pf-&gt;ice_debugfs_pf_fwlog, pf,</div><div class='add'>+			    &amp;ice_debugfs_nr_messages_fops);</div><div class='add'>+</div><div class='add'>+	pf-&gt;ice_debugfs_pf_fwlog_modules = fw_modules;</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("enable", 0600, pf-&gt;ice_debugfs_pf_fwlog,</div><div class='add'>+			    pf, &amp;ice_debugfs_enable_fops);</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("log_size", 0600, pf-&gt;ice_debugfs_pf_fwlog,</div><div class='add'>+			    pf, &amp;ice_debugfs_log_size_fops);</div><div class='add'>+</div><div class='add'>+	debugfs_create_file("data", 0600, pf-&gt;ice_debugfs_pf_fwlog,</div><div class='add'>+			    pf, &amp;ice_debugfs_data_fops);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+err_create_module_files:</div><div class='add'>+	debugfs_remove_recursive(pf-&gt;ice_debugfs_pf_fwlog);</div><div class='add'>+	kfree(fw_modules);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_init - create root directory for debugfs entries</div><div class='add'>+ */</div><div class='add'>+void ice_debugfs_init(void)</div><div class='add'>+{</div><div class='add'>+	ice_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);</div><div class='add'>+	if (IS_ERR(ice_debugfs_root))</div><div class='add'>+		pr_info("init of debugfs failed\n");</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_debugfs_exit - remove debugfs entries</div><div class='add'>+ */</div><div class='add'>+void ice_debugfs_exit(void)</div><div class='add'>+{</div><div class='add'>+	debugfs_remove_recursive(ice_debugfs_root);</div><div class='add'>+	ice_debugfs_root = NULL;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_devlink.c b/drivers/net/ethernet/intel/ice/ice_devlink.c<br/>index 80dc5445b50d..65be56f2af9e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_devlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_devlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_devlink.c</a></div><div class='hunk'>@@ -193,6 +193,24 @@ ice_info_pending_netlist_build(struct ice_pf __always_unused *pf,</div><div class='ctx'> 		snprintf(ctx-&gt;buf, sizeof(ctx-&gt;buf), "0x%08x", netlist-&gt;hash);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ice_info_cgu_fw_build(struct ice_pf *pf, struct ice_info_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	u32 id, cfg_ver, fw_ver;</div><div class='add'>+</div><div class='add'>+	if (!ice_is_feature_supported(pf, ICE_F_CGU))</div><div class='add'>+		return;</div><div class='add'>+	if (ice_aq_get_cgu_info(&amp;pf-&gt;hw, &amp;id, &amp;cfg_ver, &amp;fw_ver))</div><div class='add'>+		return;</div><div class='add'>+	snprintf(ctx-&gt;buf, sizeof(ctx-&gt;buf), "%u.%u.%u", id, cfg_ver, fw_ver);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ice_info_cgu_id(struct ice_pf *pf, struct ice_info_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	if (!ice_is_feature_supported(pf, ICE_F_CGU))</div><div class='add'>+		return;</div><div class='add'>+	snprintf(ctx-&gt;buf, sizeof(ctx-&gt;buf), "%u", pf-&gt;hw.cgu_part_number);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define fixed(key, getter) { ICE_VERSION_FIXED, key, getter, NULL }</div><div class='ctx'> #define running(key, getter) { ICE_VERSION_RUNNING, key, getter, NULL }</div><div class='ctx'> #define stored(key, getter, fallback) { ICE_VERSION_STORED, key, getter, fallback }</div><div class='hunk'>@@ -235,6 +253,8 @@ static const struct ice_devlink_version {</div><div class='ctx'> 	running("fw.app.bundle_id", ice_info_ddp_pkg_bundle_id),</div><div class='ctx'> 	combined("fw.netlist", ice_info_netlist_ver, ice_info_pending_netlist_ver),</div><div class='ctx'> 	combined("fw.netlist.build", ice_info_netlist_build, ice_info_pending_netlist_build),</div><div class='add'>+	fixed("cgu.id", ice_info_cgu_id),</div><div class='add'>+	running("fw.cgu", ice_info_cgu_fw_build),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -810,6 +830,10 @@ static void ice_traverse_tx_tree(struct devlink *devlink, struct ice_sched_node</div><div class='ctx'> 	struct ice_vf *vf;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	if (node-&gt;rate_node)</div><div class='add'>+		/* already added, skip to the next */</div><div class='add'>+		goto traverse_children;</div><div class='add'>+</div><div class='ctx'> 	if (node-&gt;parent == tc_node) {</div><div class='ctx'> 		/* create root node */</div><div class='ctx'> 		rate_node = devl_rate_node_create(devlink, node, node-&gt;name, NULL);</div><div class='hunk'>@@ -831,6 +855,7 @@ static void ice_traverse_tx_tree(struct devlink *devlink, struct ice_sched_node</div><div class='ctx'> 	if (rate_node &amp;&amp; !IS_ERR(rate_node))</div><div class='ctx'> 		node-&gt;rate_node = rate_node;</div><div class='ctx'> </div><div class='add'>+traverse_children:</div><div class='ctx'> 	for (i = 0; i &lt; node-&gt;num_children; i++)</div><div class='ctx'> 		ice_traverse_tx_tree(devlink, node-&gt;children[i], tc_node, pf);</div><div class='ctx'> }</div><div class='hunk'>@@ -861,6 +886,30 @@ int ice_devlink_rate_init_tx_topology(struct devlink *devlink, struct ice_vsi *v</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ice_clear_rate_nodes(struct ice_sched_node *node)</div><div class='add'>+{</div><div class='add'>+	node-&gt;rate_node = NULL;</div><div class='add'>+</div><div class='add'>+	for (int i = 0; i &lt; node-&gt;num_children; i++)</div><div class='add'>+		ice_clear_rate_nodes(node-&gt;children[i]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_devlink_rate_clear_tx_topology - clear node-&gt;rate_node</div><div class='add'>+ * @vsi: main vsi struct</div><div class='add'>+ *</div><div class='add'>+ * Clear rate_node to cleanup creation of Tx topology.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void ice_devlink_rate_clear_tx_topology(struct ice_vsi *vsi)</div><div class='add'>+{</div><div class='add'>+	struct ice_port_info *pi = vsi-&gt;port_info;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;pi-&gt;sched_lock);</div><div class='add'>+	ice_clear_rate_nodes(pi-&gt;root-&gt;children[0]);</div><div class='add'>+	mutex_unlock(&amp;pi-&gt;sched_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ice_set_object_tx_share - sets node scheduling parameter</div><div class='ctx'>  * @pi: devlink struct instance</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_devlink.h b/drivers/net/ethernet/intel/ice/ice_devlink.h<br/>index 6ec96779f52e..d291c0e2e17b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_devlink.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_devlink.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_devlink.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_devlink.h</a></div><div class='hunk'>@@ -20,5 +20,6 @@ void ice_devlink_destroy_regions(struct ice_pf *pf);</div><div class='ctx'> </div><div class='ctx'> int ice_devlink_rate_init_tx_topology(struct devlink *devlink, struct ice_vsi *vsi);</div><div class='ctx'> void ice_tear_down_devlink_rate_tree(struct ice_pf *pf);</div><div class='add'>+void ice_devlink_rate_clear_tx_topology(struct ice_vsi *vsi);</div><div class='ctx'> </div><div class='ctx'> #endif /* _ICE_DEVLINK_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c<br/>index 86b180cb32a0..b9c5eced6326 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dpll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_dpll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_dpll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_dpll.c</a></div><div class='hunk'>@@ -513,31 +513,6 @@ ice_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_dpll_mode_supported - check if dpll's working mode is supported</div><div class='del'>- * @dpll: registered dpll pointer</div><div class='del'>- * @dpll_priv: private data pointer passed on dpll registration</div><div class='del'>- * @mode: mode to be checked for support</div><div class='del'>- * @extack: error reporting</div><div class='del'>- *</div><div class='del'>- * Dpll subsystem callback. Provides information if working mode is supported</div><div class='del'>- * by dpll.</div><div class='del'>- *</div><div class='del'>- * Return:</div><div class='del'>- * * true - mode is supported</div><div class='del'>- * * false - mode is not supported</div><div class='del'>- */</div><div class='del'>-static bool ice_dpll_mode_supported(const struct dpll_device *dpll,</div><div class='del'>-				    void *dpll_priv,</div><div class='del'>-				    enum dpll_mode mode,</div><div class='del'>-				    struct netlink_ext_ack *extack)</div><div class='del'>-{</div><div class='del'>-	if (mode == DPLL_MODE_AUTOMATIC)</div><div class='del'>-		return true;</div><div class='del'>-</div><div class='del'>-	return false;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ice_dpll_mode_get - get dpll's working mode</div><div class='ctx'>  * @dpll: registered dpll pointer</div><div class='ctx'>  * @dpll_priv: private data pointer passed on dpll registration</div><div class='hunk'>@@ -1197,7 +1172,6 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {</div><div class='ctx'> </div><div class='ctx'> static const struct dpll_device_ops ice_dpll_ops = {</div><div class='ctx'> 	.lock_status_get = ice_dpll_lock_status_get,</div><div class='del'>-	.mode_supported = ice_dpll_mode_supported,</div><div class='ctx'> 	.mode_get = ice_dpll_mode_get,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_eswitch.c b/drivers/net/ethernet/intel/ice/ice_eswitch.c<br/>index a655d499abfa..9069725c71b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_eswitch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch.c</a></div><div class='hunk'>@@ -11,17 +11,34 @@</div><div class='ctx'> #include "ice_tc_lib.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_add_vf_sp_rule - add adv rule with VF's VSI index</div><div class='add'>+ * ice_eswitch_del_sp_rules - delete adv rules added on PRs</div><div class='add'>+ * @pf: pointer to the PF struct</div><div class='add'>+ *</div><div class='add'>+ * Delete all advanced rules that were used to forward packets with the</div><div class='add'>+ * device's VSI index to the corresponding eswitch ctrl VSI queue.</div><div class='add'>+ */</div><div class='add'>+static void ice_eswitch_del_sp_rules(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr) {</div><div class='add'>+		if (repr-&gt;sp_rule.rid)</div><div class='add'>+			ice_rem_adv_rule_by_id(&amp;pf-&gt;hw, &amp;repr-&gt;sp_rule);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_eswitch_add_sp_rule - add adv rule with device's VSI index</div><div class='ctx'>  * @pf: pointer to PF struct</div><div class='del'>- * @vf: pointer to VF struct</div><div class='add'>+ * @repr: pointer to the repr struct</div><div class='ctx'>  *</div><div class='ctx'>  * This function adds advanced rule that forwards packets with</div><div class='del'>- * VF's VSI index to the corresponding switchdev ctrl VSI queue.</div><div class='add'>+ * device's VSI index to the corresponding eswitch ctrl VSI queue.</div><div class='ctx'>  */</div><div class='del'>-static int</div><div class='del'>-ice_eswitch_add_vf_sp_rule(struct ice_pf *pf, struct ice_vf *vf)</div><div class='add'>+static int ice_eswitch_add_sp_rule(struct ice_pf *pf, struct ice_repr *repr)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='add'>+	struct ice_vsi *ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='ctx'> 	struct ice_adv_rule_info rule_info = { 0 };</div><div class='ctx'> 	struct ice_adv_lkup_elem *list;</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='hunk'>@@ -38,39 +55,42 @@ ice_eswitch_add_vf_sp_rule(struct ice_pf *pf, struct ice_vf *vf)</div><div class='ctx'> 	rule_info.sw_act.vsi_handle = ctrl_vsi-&gt;idx;</div><div class='ctx'> 	rule_info.sw_act.fltr_act = ICE_FWD_TO_Q;</div><div class='ctx'> 	rule_info.sw_act.fwd_id.q_id = hw-&gt;func_caps.common_cap.rxq_first_id +</div><div class='del'>-				       ctrl_vsi-&gt;rxq_map[vf-&gt;vf_id];</div><div class='add'>+				       ctrl_vsi-&gt;rxq_map[repr-&gt;q_id];</div><div class='ctx'> 	rule_info.flags_info.act |= ICE_SINGLE_ACT_LB_ENABLE;</div><div class='ctx'> 	rule_info.flags_info.act_valid = true;</div><div class='ctx'> 	rule_info.tun_type = ICE_SW_TUN_AND_NON_TUN;</div><div class='del'>-	rule_info.src_vsi = vf-&gt;lan_vsi_idx;</div><div class='add'>+	rule_info.src_vsi = repr-&gt;src_vsi-&gt;idx;</div><div class='ctx'> </div><div class='ctx'> 	err = ice_add_adv_rule(hw, list, lkups_cnt, &amp;rule_info,</div><div class='del'>-			       &amp;vf-&gt;repr-&gt;sp_rule);</div><div class='add'>+			       &amp;repr-&gt;sp_rule);</div><div class='ctx'> 	if (err)</div><div class='del'>-		dev_err(ice_pf_to_dev(pf), "Unable to add VF slow-path rule in switchdev mode for VF %d",</div><div class='del'>-			vf-&gt;vf_id);</div><div class='add'>+		dev_err(ice_pf_to_dev(pf), "Unable to add slow-path rule for eswitch for PR %d",</div><div class='add'>+			repr-&gt;id);</div><div class='ctx'> </div><div class='ctx'> 	kfree(list);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * ice_eswitch_del_vf_sp_rule - delete adv rule with VF's VSI index</div><div class='del'>- * @vf: pointer to the VF struct</div><div class='del'>- *</div><div class='del'>- * Delete the advanced rule that was used to forward packets with the VF's VSI</div><div class='del'>- * index to the corresponding switchdev ctrl VSI queue.</div><div class='del'>- */</div><div class='del'>-static void ice_eswitch_del_vf_sp_rule(struct ice_vf *vf)</div><div class='add'>+static int</div><div class='add'>+ice_eswitch_add_sp_rules(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	if (!vf-&gt;repr)</div><div class='del'>-		return;</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr) {</div><div class='add'>+		err = ice_eswitch_add_sp_rule(pf, repr);</div><div class='add'>+		if (err) {</div><div class='add'>+			ice_eswitch_del_sp_rules(pf);</div><div class='add'>+			return err;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ice_rem_adv_rule_by_id(&amp;vf-&gt;pf-&gt;hw, &amp;vf-&gt;repr-&gt;sp_rule);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_setup_env - configure switchdev HW filters</div><div class='add'>+ * ice_eswitch_setup_env - configure eswitch HW filters</div><div class='ctx'>  * @pf: pointer to PF struct</div><div class='ctx'>  *</div><div class='ctx'>  * This function adds HW filters configuration specific for switchdev</div><div class='hunk'>@@ -78,18 +98,18 @@ static void ice_eswitch_del_vf_sp_rule(struct ice_vf *vf)</div><div class='ctx'>  */</div><div class='ctx'> static int ice_eswitch_setup_env(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *uplink_vsi = pf-&gt;switchdev.uplink_vsi;</div><div class='del'>-	struct net_device *uplink_netdev = uplink_vsi-&gt;netdev;</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='add'>+	struct ice_vsi *uplink_vsi = pf-&gt;eswitch.uplink_vsi;</div><div class='add'>+	struct ice_vsi *ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='add'>+	struct net_device *netdev = uplink_vsi-&gt;netdev;</div><div class='ctx'> 	struct ice_vsi_vlan_ops *vlan_ops;</div><div class='ctx'> 	bool rule_added = false;</div><div class='ctx'> </div><div class='ctx'> 	ice_remove_vsi_fltr(&amp;pf-&gt;hw, uplink_vsi-&gt;idx);</div><div class='ctx'> </div><div class='del'>-	netif_addr_lock_bh(uplink_netdev);</div><div class='del'>-	__dev_uc_unsync(uplink_netdev, NULL);</div><div class='del'>-	__dev_mc_unsync(uplink_netdev, NULL);</div><div class='del'>-	netif_addr_unlock_bh(uplink_netdev);</div><div class='add'>+	netif_addr_lock_bh(netdev);</div><div class='add'>+	__dev_uc_unsync(netdev, NULL);</div><div class='add'>+	__dev_mc_unsync(netdev, NULL);</div><div class='add'>+	netif_addr_unlock_bh(netdev);</div><div class='ctx'> </div><div class='ctx'> 	if (ice_vsi_add_vlan_zero(uplink_vsi))</div><div class='ctx'> 		goto err_def_rx;</div><div class='hunk'>@@ -132,19 +152,20 @@ err_def_rx:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_remap_rings_to_vectors - reconfigure rings of switchdev ctrl VSI</div><div class='del'>- * @pf: pointer to PF struct</div><div class='add'>+ * ice_eswitch_remap_rings_to_vectors - reconfigure rings of eswitch ctrl VSI</div><div class='add'>+ * @eswitch: pointer to eswitch struct</div><div class='ctx'>  *</div><div class='del'>- * In switchdev number of allocated Tx/Rx rings is equal.</div><div class='add'>+ * In eswitch number of allocated Tx/Rx rings is equal.</div><div class='ctx'>  *</div><div class='ctx'>  * This function fills q_vectors structures associated with representor and</div><div class='ctx'>  * move each ring pairs to port representor netdevs. Each port representor</div><div class='ctx'>  * will have dedicated 1 Tx/Rx ring pair, so number of rings pair is equal to</div><div class='ctx'>  * number of VFs.</div><div class='ctx'>  */</div><div class='del'>-static void ice_eswitch_remap_rings_to_vectors(struct ice_pf *pf)</div><div class='add'>+static void ice_eswitch_remap_rings_to_vectors(struct ice_eswitch *eswitch)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *vsi = pf-&gt;switchdev.control_vsi;</div><div class='add'>+	struct ice_vsi *vsi = eswitch-&gt;control_vsi;</div><div class='add'>+	unsigned long repr_id = 0;</div><div class='ctx'> 	int q_id;</div><div class='ctx'> </div><div class='ctx'> 	ice_for_each_txq(vsi, q_id) {</div><div class='hunk'>@@ -152,13 +173,14 @@ static void ice_eswitch_remap_rings_to_vectors(struct ice_pf *pf)</div><div class='ctx'> 		struct ice_tx_ring *tx_ring;</div><div class='ctx'> 		struct ice_rx_ring *rx_ring;</div><div class='ctx'> 		struct ice_repr *repr;</div><div class='del'>-		struct ice_vf *vf;</div><div class='ctx'> </div><div class='del'>-		vf = ice_get_vf_by_id(pf, q_id);</div><div class='del'>-		if (WARN_ON(!vf))</div><div class='del'>-			continue;</div><div class='add'>+		repr = xa_find(&amp;eswitch-&gt;reprs, &amp;repr_id, U32_MAX,</div><div class='add'>+			       XA_PRESENT);</div><div class='add'>+		if (!repr)</div><div class='add'>+			break;</div><div class='ctx'> </div><div class='del'>-		repr = vf-&gt;repr;</div><div class='add'>+		repr_id += 1;</div><div class='add'>+		repr-&gt;q_id = q_id;</div><div class='ctx'> 		q_vector = repr-&gt;q_vector;</div><div class='ctx'> 		tx_ring = vsi-&gt;tx_rings[q_id];</div><div class='ctx'> 		rx_ring = vsi-&gt;rx_rings[q_id];</div><div class='hunk'>@@ -181,136 +203,96 @@ static void ice_eswitch_remap_rings_to_vectors(struct ice_pf *pf)</div><div class='ctx'> 		rx_ring-&gt;q_vector = q_vector;</div><div class='ctx'> 		rx_ring-&gt;next = NULL;</div><div class='ctx'> 		rx_ring-&gt;netdev = repr-&gt;netdev;</div><div class='del'>-</div><div class='del'>-		ice_put_vf(vf);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_release_reprs - clear PR VSIs configuration</div><div class='add'>+ * ice_eswitch_release_repr - clear PR VSI configuration</div><div class='ctx'>  * @pf: poiner to PF struct</div><div class='del'>- * @ctrl_vsi: pointer to switchdev control VSI</div><div class='add'>+ * @repr: pointer to PR</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='del'>-ice_eswitch_release_reprs(struct ice_pf *pf, struct ice_vsi *ctrl_vsi)</div><div class='add'>+ice_eswitch_release_repr(struct ice_pf *pf, struct ice_repr *repr)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='add'>+	struct ice_vsi *vsi = repr-&gt;src_vsi;</div><div class='ctx'> </div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='del'>-</div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		struct ice_vsi *vsi = vf-&gt;repr-&gt;src_vsi;</div><div class='del'>-</div><div class='del'>-		/* Skip VFs that aren't configured */</div><div class='del'>-		if (!vf-&gt;repr-&gt;dst)</div><div class='del'>-			continue;</div><div class='add'>+	/* Skip representors that aren't configured */</div><div class='add'>+	if (!repr-&gt;dst)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-		ice_vsi_update_security(vsi, ice_vsi_ctx_set_antispoof);</div><div class='del'>-		metadata_dst_free(vf-&gt;repr-&gt;dst);</div><div class='del'>-		vf-&gt;repr-&gt;dst = NULL;</div><div class='del'>-		ice_eswitch_del_vf_sp_rule(vf);</div><div class='del'>-		ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr,</div><div class='del'>-					       ICE_FWD_TO_VSI);</div><div class='add'>+	ice_vsi_update_security(vsi, ice_vsi_ctx_set_antispoof);</div><div class='add'>+	metadata_dst_free(repr-&gt;dst);</div><div class='add'>+	repr-&gt;dst = NULL;</div><div class='add'>+	ice_fltr_add_mac_and_broadcast(vsi, repr-&gt;parent_mac,</div><div class='add'>+				       ICE_FWD_TO_VSI);</div><div class='ctx'> </div><div class='del'>-		netif_napi_del(&amp;vf-&gt;repr-&gt;q_vector-&gt;napi);</div><div class='del'>-	}</div><div class='add'>+	netif_napi_del(&amp;repr-&gt;q_vector-&gt;napi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_setup_reprs - configure port reprs to run in switchdev mode</div><div class='add'>+ * ice_eswitch_setup_repr - configure PR to run in switchdev mode</div><div class='ctx'>  * @pf: pointer to PF struct</div><div class='add'>+ * @repr: pointer to PR struct</div><div class='ctx'>  */</div><div class='del'>-static int ice_eswitch_setup_reprs(struct ice_pf *pf)</div><div class='add'>+static int ice_eswitch_setup_repr(struct ice_pf *pf, struct ice_repr *repr)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='del'>-	int max_vsi_num = 0;</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='del'>-</div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		struct ice_vsi *vsi = vf-&gt;repr-&gt;src_vsi;</div><div class='del'>-</div><div class='del'>-		ice_remove_vsi_fltr(&amp;pf-&gt;hw, vsi-&gt;idx);</div><div class='del'>-		vf-&gt;repr-&gt;dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,</div><div class='del'>-						   GFP_KERNEL);</div><div class='del'>-		if (!vf-&gt;repr-&gt;dst) {</div><div class='del'>-			ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr,</div><div class='del'>-						       ICE_FWD_TO_VSI);</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='add'>+	struct ice_vsi *ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='add'>+	struct ice_vsi *vsi = repr-&gt;src_vsi;</div><div class='add'>+	struct metadata_dst *dst;</div><div class='ctx'> </div><div class='del'>-		if (ice_eswitch_add_vf_sp_rule(pf, vf)) {</div><div class='del'>-			ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr,</div><div class='del'>-						       ICE_FWD_TO_VSI);</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='add'>+	ice_remove_vsi_fltr(&amp;pf-&gt;hw, vsi-&gt;idx);</div><div class='add'>+	repr-&gt;dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,</div><div class='add'>+				       GFP_KERNEL);</div><div class='add'>+	if (!repr-&gt;dst)</div><div class='add'>+		goto err_add_mac_fltr;</div><div class='ctx'> </div><div class='del'>-		if (ice_vsi_update_security(vsi, ice_vsi_ctx_clear_antispoof)) {</div><div class='del'>-			ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr,</div><div class='del'>-						       ICE_FWD_TO_VSI);</div><div class='del'>-			ice_eswitch_del_vf_sp_rule(vf);</div><div class='del'>-			metadata_dst_free(vf-&gt;repr-&gt;dst);</div><div class='del'>-			vf-&gt;repr-&gt;dst = NULL;</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='add'>+	if (ice_vsi_update_security(vsi, ice_vsi_ctx_clear_antispoof))</div><div class='add'>+		goto err_dst_free;</div><div class='ctx'> </div><div class='del'>-		if (ice_vsi_add_vlan_zero(vsi)) {</div><div class='del'>-			ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr,</div><div class='del'>-						       ICE_FWD_TO_VSI);</div><div class='del'>-			ice_eswitch_del_vf_sp_rule(vf);</div><div class='del'>-			metadata_dst_free(vf-&gt;repr-&gt;dst);</div><div class='del'>-			vf-&gt;repr-&gt;dst = NULL;</div><div class='del'>-			ice_vsi_update_security(vsi, ice_vsi_ctx_set_antispoof);</div><div class='del'>-			goto err;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (max_vsi_num &lt; vsi-&gt;vsi_num)</div><div class='del'>-			max_vsi_num = vsi-&gt;vsi_num;</div><div class='add'>+	if (ice_vsi_add_vlan_zero(vsi))</div><div class='add'>+		goto err_update_security;</div><div class='ctx'> </div><div class='del'>-		netif_napi_add(vf-&gt;repr-&gt;netdev, &amp;vf-&gt;repr-&gt;q_vector-&gt;napi,</div><div class='del'>-			       ice_napi_poll);</div><div class='add'>+	netif_napi_add(repr-&gt;netdev, &amp;repr-&gt;q_vector-&gt;napi,</div><div class='add'>+		       ice_napi_poll);</div><div class='ctx'> </div><div class='del'>-		netif_keep_dst(vf-&gt;repr-&gt;netdev);</div><div class='del'>-	}</div><div class='add'>+	netif_keep_dst(repr-&gt;netdev);</div><div class='ctx'> </div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		struct ice_repr *repr = vf-&gt;repr;</div><div class='del'>-		struct ice_vsi *vsi = repr-&gt;src_vsi;</div><div class='del'>-		struct metadata_dst *dst;</div><div class='del'>-</div><div class='del'>-		dst = repr-&gt;dst;</div><div class='del'>-		dst-&gt;u.port_info.port_id = vsi-&gt;vsi_num;</div><div class='del'>-		dst-&gt;u.port_info.lower_dev = repr-&gt;netdev;</div><div class='del'>-		ice_repr_set_traffic_vsi(repr, ctrl_vsi);</div><div class='del'>-	}</div><div class='add'>+	dst = repr-&gt;dst;</div><div class='add'>+	dst-&gt;u.port_info.port_id = vsi-&gt;vsi_num;</div><div class='add'>+	dst-&gt;u.port_info.lower_dev = repr-&gt;netdev;</div><div class='add'>+	ice_repr_set_traffic_vsi(repr, ctrl_vsi);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err:</div><div class='del'>-	ice_eswitch_release_reprs(pf, ctrl_vsi);</div><div class='add'>+err_update_security:</div><div class='add'>+	ice_vsi_update_security(vsi, ice_vsi_ctx_set_antispoof);</div><div class='add'>+err_dst_free:</div><div class='add'>+	metadata_dst_free(repr-&gt;dst);</div><div class='add'>+	repr-&gt;dst = NULL;</div><div class='add'>+err_add_mac_fltr:</div><div class='add'>+	ice_fltr_add_mac_and_broadcast(vsi, repr-&gt;parent_mac, ICE_FWD_TO_VSI);</div><div class='ctx'> </div><div class='ctx'> 	return -ENODEV;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_update_repr - reconfigure VF port representor</div><div class='del'>- * @vsi: VF VSI for which port representor is configured</div><div class='add'>+ * ice_eswitch_update_repr - reconfigure port representor</div><div class='add'>+ * @repr_id: representor ID</div><div class='add'>+ * @vsi: VSI for which port representor is configured</div><div class='ctx'>  */</div><div class='del'>-void ice_eswitch_update_repr(struct ice_vsi *vsi)</div><div class='add'>+void ice_eswitch_update_repr(unsigned long repr_id, struct ice_vsi *vsi)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	struct ice_repr *repr;</div><div class='del'>-	struct ice_vf *vf;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!ice_is_switchdev_running(pf))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	vf = vsi-&gt;vf;</div><div class='del'>-	repr = vf-&gt;repr;</div><div class='add'>+	repr = xa_load(&amp;pf-&gt;eswitch.reprs, repr_id);</div><div class='add'>+	if (!repr)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	repr-&gt;src_vsi = vsi;</div><div class='ctx'> 	repr-&gt;dst-&gt;u.port_info.port_id = vsi-&gt;vsi_num;</div><div class='ctx'> </div><div class='hunk'>@@ -319,9 +301,10 @@ void ice_eswitch_update_repr(struct ice_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 	ret = ice_vsi_update_security(vsi, ice_vsi_ctx_clear_antispoof);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		ice_fltr_add_mac_and_broadcast(vsi, vf-&gt;hw_lan_addr, ICE_FWD_TO_VSI);</div><div class='del'>-		dev_err(ice_pf_to_dev(pf), "Failed to update VF %d port representor",</div><div class='del'>-			vsi-&gt;vf-&gt;vf_id);</div><div class='add'>+		ice_fltr_add_mac_and_broadcast(vsi, repr-&gt;parent_mac,</div><div class='add'>+					       ICE_FWD_TO_VSI);</div><div class='add'>+		dev_err(ice_pf_to_dev(pf), "Failed to update VSI of port representor %d",</div><div class='add'>+			repr-&gt;id);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -353,13 +336,13 @@ ice_eswitch_port_start_xmit(struct sk_buff *skb, struct net_device *netdev)</div><div class='ctx'> 	skb_dst_drop(skb);</div><div class='ctx'> 	dst_hold((struct dst_entry *)repr-&gt;dst);</div><div class='ctx'> 	skb_dst_set(skb, (struct dst_entry *)repr-&gt;dst);</div><div class='del'>-	skb-&gt;queue_mapping = repr-&gt;vf-&gt;vf_id;</div><div class='add'>+	skb-&gt;queue_mapping = repr-&gt;q_id;</div><div class='ctx'> </div><div class='ctx'> 	return ice_start_xmit(skb, netdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_set_target_vsi - set switchdev context in Tx context descriptor</div><div class='add'>+ * ice_eswitch_set_target_vsi - set eswitch context in Tx context descriptor</div><div class='ctx'>  * @skb: pointer to send buffer</div><div class='ctx'>  * @off: pointer to offload struct</div><div class='ctx'>  */</div><div class='hunk'>@@ -375,14 +358,14 @@ ice_eswitch_set_target_vsi(struct sk_buff *skb,</div><div class='ctx'> 		off-&gt;cd_qw1 |= (cd_cmd | ICE_TX_DESC_DTYPE_CTX);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		cd_cmd = ICE_TX_CTX_DESC_SWTCH_VSI &lt;&lt; ICE_TXD_CTX_QW1_CMD_S;</div><div class='del'>-		dst_vsi = ((u64)dst-&gt;u.port_info.port_id &lt;&lt;</div><div class='del'>-			   ICE_TXD_CTX_QW1_VSI_S) &amp; ICE_TXD_CTX_QW1_VSI_M;</div><div class='add'>+		dst_vsi = FIELD_PREP(ICE_TXD_CTX_QW1_VSI_M,</div><div class='add'>+				     dst-&gt;u.port_info.port_id);</div><div class='ctx'> 		off-&gt;cd_qw1 = cd_cmd | dst_vsi | ICE_TX_DESC_DTYPE_CTX;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_release_env - clear switchdev HW filters</div><div class='add'>+ * ice_eswitch_release_env - clear eswitch HW filters</div><div class='ctx'>  * @pf: pointer to PF struct</div><div class='ctx'>  *</div><div class='ctx'>  * This function removes HW filters configuration specific for switchdev</div><div class='hunk'>@@ -390,8 +373,8 @@ ice_eswitch_set_target_vsi(struct sk_buff *skb,</div><div class='ctx'>  */</div><div class='ctx'> static void ice_eswitch_release_env(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *uplink_vsi = pf-&gt;switchdev.uplink_vsi;</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='add'>+	struct ice_vsi *uplink_vsi = pf-&gt;eswitch.uplink_vsi;</div><div class='add'>+	struct ice_vsi *ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='ctx'> 	struct ice_vsi_vlan_ops *vlan_ops;</div><div class='ctx'> </div><div class='ctx'> 	vlan_ops = ice_get_compat_vsi_vlan_ops(uplink_vsi);</div><div class='hunk'>@@ -407,7 +390,7 @@ static void ice_eswitch_release_env(struct ice_pf *pf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_vsi_setup - configure switchdev control VSI</div><div class='add'>+ * ice_eswitch_vsi_setup - configure eswitch control VSI</div><div class='ctx'>  * @pf: pointer to PF structure</div><div class='ctx'>  * @pi: pointer to port_info structure</div><div class='ctx'>  */</div><div class='hunk'>@@ -424,48 +407,29 @@ ice_eswitch_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_napi_del - remove NAPI handle for all port representors</div><div class='del'>- * @pf: pointer to PF structure</div><div class='del'>- */</div><div class='del'>-static void ice_eswitch_napi_del(struct ice_pf *pf)</div><div class='del'>-{</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='del'>-</div><div class='del'>-	ice_for_each_vf(pf, bkt, vf)</div><div class='del'>-		netif_napi_del(&amp;vf-&gt;repr-&gt;q_vector-&gt;napi);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ice_eswitch_napi_enable - enable NAPI for all port representors</div><div class='del'>- * @pf: pointer to PF structure</div><div class='add'>+ * @reprs: xarray of reprs</div><div class='ctx'>  */</div><div class='del'>-static void ice_eswitch_napi_enable(struct ice_pf *pf)</div><div class='add'>+static void ice_eswitch_napi_enable(struct xarray *reprs)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='ctx'> </div><div class='del'>-	ice_for_each_vf(pf, bkt, vf)</div><div class='del'>-		napi_enable(&amp;vf-&gt;repr-&gt;q_vector-&gt;napi);</div><div class='add'>+	xa_for_each(reprs, id, repr)</div><div class='add'>+		napi_enable(&amp;repr-&gt;q_vector-&gt;napi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ice_eswitch_napi_disable - disable NAPI for all port representors</div><div class='del'>- * @pf: pointer to PF structure</div><div class='add'>+ * @reprs: xarray of reprs</div><div class='ctx'>  */</div><div class='del'>-static void ice_eswitch_napi_disable(struct ice_pf *pf)</div><div class='add'>+static void ice_eswitch_napi_disable(struct xarray *reprs)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='ctx'> </div><div class='del'>-	ice_for_each_vf(pf, bkt, vf)</div><div class='del'>-		napi_disable(&amp;vf-&gt;repr-&gt;q_vector-&gt;napi);</div><div class='add'>+	xa_for_each(reprs, id, repr)</div><div class='add'>+		napi_disable(&amp;repr-&gt;q_vector-&gt;napi);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -486,39 +450,26 @@ static int ice_eswitch_enable_switchdev(struct ice_pf *pf)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pf-&gt;switchdev.control_vsi = ice_eswitch_vsi_setup(pf, pf-&gt;hw.port_info);</div><div class='del'>-	if (!pf-&gt;switchdev.control_vsi)</div><div class='add'>+	pf-&gt;eswitch.control_vsi = ice_eswitch_vsi_setup(pf, pf-&gt;hw.port_info);</div><div class='add'>+	if (!pf-&gt;eswitch.control_vsi)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='del'>-	pf-&gt;switchdev.uplink_vsi = uplink_vsi;</div><div class='add'>+	ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='add'>+	/* cp VSI is createad with 1 queue as default */</div><div class='add'>+	pf-&gt;eswitch.qs.value = 1;</div><div class='add'>+	pf-&gt;eswitch.uplink_vsi = uplink_vsi;</div><div class='ctx'> </div><div class='ctx'> 	if (ice_eswitch_setup_env(pf))</div><div class='ctx'> 		goto err_vsi;</div><div class='ctx'> </div><div class='del'>-	if (ice_repr_add_for_all_vfs(pf))</div><div class='del'>-		goto err_repr_add;</div><div class='del'>-</div><div class='del'>-	if (ice_eswitch_setup_reprs(pf))</div><div class='del'>-		goto err_setup_reprs;</div><div class='del'>-</div><div class='del'>-	ice_eswitch_remap_rings_to_vectors(pf);</div><div class='del'>-</div><div class='del'>-	if (ice_vsi_open(ctrl_vsi))</div><div class='del'>-		goto err_setup_reprs;</div><div class='del'>-</div><div class='ctx'> 	if (ice_eswitch_br_offloads_init(pf))</div><div class='ctx'> 		goto err_br_offloads;</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_napi_enable(pf);</div><div class='add'>+	pf-&gt;eswitch.is_running = true;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_br_offloads:</div><div class='del'>-	ice_vsi_close(ctrl_vsi);</div><div class='del'>-err_setup_reprs:</div><div class='del'>-	ice_repr_rem_from_all_vfs(pf);</div><div class='del'>-err_repr_add:</div><div class='ctx'> 	ice_eswitch_release_env(pf);</div><div class='ctx'> err_vsi:</div><div class='ctx'> 	ice_vsi_release(ctrl_vsi);</div><div class='hunk'>@@ -526,19 +477,19 @@ err_vsi:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_disable_switchdev - disable switchdev resources</div><div class='add'>+ * ice_eswitch_disable_switchdev - disable eswitch resources</div><div class='ctx'>  * @pf: pointer to PF structure</div><div class='ctx'>  */</div><div class='ctx'> static void ice_eswitch_disable_switchdev(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='add'>+	struct ice_vsi *ctrl_vsi = pf-&gt;eswitch.control_vsi;</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_napi_disable(pf);</div><div class='ctx'> 	ice_eswitch_br_offloads_deinit(pf);</div><div class='ctx'> 	ice_eswitch_release_env(pf);</div><div class='del'>-	ice_eswitch_release_reprs(pf, ctrl_vsi);</div><div class='ctx'> 	ice_vsi_release(ctrl_vsi);</div><div class='del'>-	ice_repr_rem_from_all_vfs(pf);</div><div class='add'>+</div><div class='add'>+	pf-&gt;eswitch.is_running = false;</div><div class='add'>+	pf-&gt;eswitch.qs.is_reaching = false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -566,6 +517,7 @@ ice_eswitch_mode_set(struct devlink *devlink, u16 mode,</div><div class='ctx'> 	case DEVLINK_ESWITCH_MODE_LEGACY:</div><div class='ctx'> 		dev_info(ice_pf_to_dev(pf), "PF %d changed eswitch mode to legacy",</div><div class='ctx'> 			 pf-&gt;hw.pf_id);</div><div class='add'>+		xa_destroy(&amp;pf-&gt;eswitch.reprs);</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(extack, "Changed eswitch mode to legacy");</div><div class='ctx'> 		break;</div><div class='ctx'> 	case DEVLINK_ESWITCH_MODE_SWITCHDEV:</div><div class='hunk'>@@ -578,6 +530,7 @@ ice_eswitch_mode_set(struct devlink *devlink, u16 mode,</div><div class='ctx'> </div><div class='ctx'> 		dev_info(ice_pf_to_dev(pf), "PF %d changed eswitch mode to switchdev",</div><div class='ctx'> 			 pf-&gt;hw.pf_id);</div><div class='add'>+		xa_init_flags(&amp;pf-&gt;eswitch.reprs, XA_FLAGS_ALLOC);</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(extack, "Changed eswitch mode to switchdev");</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -616,74 +569,168 @@ bool ice_is_eswitch_mode_switchdev(struct ice_pf *pf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_release - cleanup eswitch</div><div class='add'>+ * ice_eswitch_start_all_tx_queues - start Tx queues of all port representors</div><div class='ctx'>  * @pf: pointer to PF structure</div><div class='ctx'>  */</div><div class='del'>-void ice_eswitch_release(struct ice_pf *pf)</div><div class='add'>+static void ice_eswitch_start_all_tx_queues(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	if (pf-&gt;eswitch_mode == DEVLINK_ESWITCH_MODE_LEGACY)</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='add'>+</div><div class='add'>+	if (test_bit(ICE_DOWN, pf-&gt;state))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_disable_switchdev(pf);</div><div class='del'>-	pf-&gt;switchdev.is_running = false;</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr)</div><div class='add'>+		ice_repr_start_tx_queues(repr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_eswitch_configure - configure eswitch</div><div class='add'>+ * ice_eswitch_stop_all_tx_queues - stop Tx queues of all port representors</div><div class='ctx'>  * @pf: pointer to PF structure</div><div class='ctx'>  */</div><div class='del'>-int ice_eswitch_configure(struct ice_pf *pf)</div><div class='add'>+void ice_eswitch_stop_all_tx_queues(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	int status;</div><div class='del'>-</div><div class='del'>-	if (pf-&gt;eswitch_mode == DEVLINK_ESWITCH_MODE_LEGACY || pf-&gt;switchdev.is_running)</div><div class='del'>-		return 0;</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='ctx'> </div><div class='del'>-	status = ice_eswitch_enable_switchdev(pf);</div><div class='del'>-	if (status)</div><div class='del'>-		return status;</div><div class='add'>+	if (test_bit(ICE_DOWN, pf-&gt;state))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	pf-&gt;switchdev.is_running = true;</div><div class='del'>-	return 0;</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr)</div><div class='add'>+		ice_repr_stop_tx_queues(repr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * ice_eswitch_start_all_tx_queues - start Tx queues of all port representors</div><div class='del'>- * @pf: pointer to PF structure</div><div class='del'>- */</div><div class='del'>-static void ice_eswitch_start_all_tx_queues(struct ice_pf *pf)</div><div class='add'>+static void ice_eswitch_stop_reprs(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='add'>+	ice_eswitch_del_sp_rules(pf);</div><div class='add'>+	ice_eswitch_stop_all_tx_queues(pf);</div><div class='add'>+	ice_eswitch_napi_disable(&amp;pf-&gt;eswitch.reprs);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='add'>+static void ice_eswitch_start_reprs(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	ice_eswitch_napi_enable(&amp;pf-&gt;eswitch.reprs);</div><div class='add'>+	ice_eswitch_start_all_tx_queues(pf);</div><div class='add'>+	ice_eswitch_add_sp_rules(pf);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	if (test_bit(ICE_DOWN, pf-&gt;state))</div><div class='del'>-		return;</div><div class='add'>+static void</div><div class='add'>+ice_eswitch_cp_change_queues(struct ice_eswitch *eswitch, int change)</div><div class='add'>+{</div><div class='add'>+	struct ice_vsi *cp = eswitch-&gt;control_vsi;</div><div class='add'>+	int queues = 0;</div><div class='add'>+</div><div class='add'>+	if (eswitch-&gt;qs.is_reaching) {</div><div class='add'>+		if (eswitch-&gt;qs.to_reach &gt;= eswitch-&gt;qs.value + change) {</div><div class='add'>+			queues = eswitch-&gt;qs.to_reach;</div><div class='add'>+			eswitch-&gt;qs.is_reaching = false;</div><div class='add'>+		} else {</div><div class='add'>+			queues = 0;</div><div class='add'>+		}</div><div class='add'>+	} else if ((change &gt; 0 &amp;&amp; cp-&gt;alloc_txq &lt;= eswitch-&gt;qs.value) ||</div><div class='add'>+		   change &lt; 0) {</div><div class='add'>+		queues = cp-&gt;alloc_txq + change;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		if (vf-&gt;repr)</div><div class='del'>-			ice_repr_start_tx_queues(vf-&gt;repr);</div><div class='add'>+	if (queues) {</div><div class='add'>+		cp-&gt;req_txq = queues;</div><div class='add'>+		cp-&gt;req_rxq = queues;</div><div class='add'>+		ice_vsi_close(cp);</div><div class='add'>+		ice_vsi_rebuild(cp, ICE_VSI_FLAG_NO_INIT);</div><div class='add'>+		ice_vsi_open(cp);</div><div class='add'>+	} else if (!change) {</div><div class='add'>+		/* change == 0 means that VSI wasn't open, open it here */</div><div class='add'>+		ice_vsi_open(cp);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	eswitch-&gt;qs.value += change;</div><div class='add'>+	ice_eswitch_remap_rings_to_vectors(eswitch);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * ice_eswitch_stop_all_tx_queues - stop Tx queues of all port representors</div><div class='del'>- * @pf: pointer to PF structure</div><div class='del'>- */</div><div class='del'>-void ice_eswitch_stop_all_tx_queues(struct ice_pf *pf)</div><div class='add'>+int</div><div class='add'>+ice_eswitch_attach(struct ice_pf *pf, struct ice_vf *vf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	int change = 1;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='add'>+	if (pf-&gt;eswitch_mode == DEVLINK_ESWITCH_MODE_LEGACY)</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(ICE_DOWN, pf-&gt;state))</div><div class='add'>+	if (xa_empty(&amp;pf-&gt;eswitch.reprs)) {</div><div class='add'>+		err = ice_eswitch_enable_switchdev(pf);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+		/* Control plane VSI is created with 1 queue as default */</div><div class='add'>+		pf-&gt;eswitch.qs.to_reach -= 1;</div><div class='add'>+		change = 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ice_eswitch_stop_reprs(pf);</div><div class='add'>+</div><div class='add'>+	repr = ice_repr_add_vf(vf);</div><div class='add'>+	if (IS_ERR(repr)) {</div><div class='add'>+		err = PTR_ERR(repr);</div><div class='add'>+		goto err_create_repr;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = ice_eswitch_setup_repr(pf, repr);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_setup_repr;</div><div class='add'>+</div><div class='add'>+	err = xa_alloc(&amp;pf-&gt;eswitch.reprs, &amp;repr-&gt;id, repr,</div><div class='add'>+		       XA_LIMIT(1, INT_MAX), GFP_KERNEL);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_xa_alloc;</div><div class='add'>+</div><div class='add'>+	vf-&gt;repr_id = repr-&gt;id;</div><div class='add'>+</div><div class='add'>+	ice_eswitch_cp_change_queues(&amp;pf-&gt;eswitch, change);</div><div class='add'>+	ice_eswitch_start_reprs(pf);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_xa_alloc:</div><div class='add'>+	ice_eswitch_release_repr(pf, repr);</div><div class='add'>+err_setup_repr:</div><div class='add'>+	ice_repr_rem_vf(repr);</div><div class='add'>+err_create_repr:</div><div class='add'>+	if (xa_empty(&amp;pf-&gt;eswitch.reprs))</div><div class='add'>+		ice_eswitch_disable_switchdev(pf);</div><div class='add'>+	ice_eswitch_start_reprs(pf);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ice_eswitch_detach(struct ice_pf *pf, struct ice_vf *vf)</div><div class='add'>+{</div><div class='add'>+	struct ice_repr *repr = xa_load(&amp;pf-&gt;eswitch.reprs, vf-&gt;repr_id);</div><div class='add'>+	struct devlink *devlink = priv_to_devlink(pf);</div><div class='add'>+</div><div class='add'>+	if (!repr)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		if (vf-&gt;repr)</div><div class='del'>-			ice_repr_stop_tx_queues(vf-&gt;repr);</div><div class='add'>+	ice_eswitch_stop_reprs(pf);</div><div class='add'>+	xa_erase(&amp;pf-&gt;eswitch.reprs, repr-&gt;id);</div><div class='add'>+</div><div class='add'>+	if (xa_empty(&amp;pf-&gt;eswitch.reprs))</div><div class='add'>+		ice_eswitch_disable_switchdev(pf);</div><div class='add'>+	else</div><div class='add'>+		ice_eswitch_cp_change_queues(&amp;pf-&gt;eswitch, -1);</div><div class='add'>+</div><div class='add'>+	ice_eswitch_release_repr(pf, repr);</div><div class='add'>+	ice_repr_rem_vf(repr);</div><div class='add'>+</div><div class='add'>+	if (xa_empty(&amp;pf-&gt;eswitch.reprs)) {</div><div class='add'>+		/* since all port representors are destroyed, there is</div><div class='add'>+		 * no point in keeping the nodes</div><div class='add'>+		 */</div><div class='add'>+		ice_devlink_rate_clear_tx_topology(ice_get_main_vsi(pf));</div><div class='add'>+		devl_lock(devlink);</div><div class='add'>+		devl_rate_nodes_destroy(devlink);</div><div class='add'>+		devl_unlock(devlink);</div><div class='add'>+	} else {</div><div class='add'>+		ice_eswitch_start_reprs(pf);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -693,30 +740,35 @@ void ice_eswitch_stop_all_tx_queues(struct ice_pf *pf)</div><div class='ctx'>  */</div><div class='ctx'> int ice_eswitch_rebuild(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *ctrl_vsi = pf-&gt;switchdev.control_vsi;</div><div class='del'>-	int status;</div><div class='del'>-</div><div class='del'>-	ice_eswitch_napi_disable(pf);</div><div class='del'>-	ice_eswitch_napi_del(pf);</div><div class='del'>-</div><div class='del'>-	status = ice_eswitch_setup_env(pf);</div><div class='del'>-	if (status)</div><div class='del'>-		return status;</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-	status = ice_eswitch_setup_reprs(pf);</div><div class='del'>-	if (status)</div><div class='del'>-		return status;</div><div class='add'>+	if (!ice_is_switchdev_running(pf))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_remap_rings_to_vectors(pf);</div><div class='add'>+	err = ice_vsi_rebuild(pf-&gt;eswitch.control_vsi, ICE_VSI_FLAG_INIT);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='del'>-	ice_replay_tc_fltrs(pf);</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr)</div><div class='add'>+		ice_eswitch_detach(pf, repr-&gt;vf);</div><div class='ctx'> </div><div class='del'>-	status = ice_vsi_open(ctrl_vsi);</div><div class='del'>-	if (status)</div><div class='del'>-		return status;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_napi_enable(pf);</div><div class='del'>-	ice_eswitch_start_all_tx_queues(pf);</div><div class='add'>+/**</div><div class='add'>+ * ice_eswitch_reserve_cp_queues - reserve control plane VSI queues</div><div class='add'>+ * @pf: pointer to PF structure</div><div class='add'>+ * @change: how many more (or less) queues is needed</div><div class='add'>+ *</div><div class='add'>+ * Remember to call ice_eswitch_attach/detach() the "change" times.</div><div class='add'>+ */</div><div class='add'>+void ice_eswitch_reserve_cp_queues(struct ice_pf *pf, int change)</div><div class='add'>+{</div><div class='add'>+	if (pf-&gt;eswitch.qs.value + change &lt; 0)</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	pf-&gt;eswitch.qs.to_reach = pf-&gt;eswitch.qs.value + change;</div><div class='add'>+	pf-&gt;eswitch.qs.is_reaching = true;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_eswitch.h b/drivers/net/ethernet/intel/ice/ice_eswitch.h<br/>index b18bf83a2f5b..1a288a03a79a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_eswitch.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch.h</a></div><div class='hunk'>@@ -7,8 +7,9 @@</div><div class='ctx'> #include &lt;net/devlink.h&gt;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_ICE_SWITCHDEV</div><div class='del'>-void ice_eswitch_release(struct ice_pf *pf);</div><div class='del'>-int ice_eswitch_configure(struct ice_pf *pf);</div><div class='add'>+void ice_eswitch_detach(struct ice_pf *pf, struct ice_vf *vf);</div><div class='add'>+int</div><div class='add'>+ice_eswitch_attach(struct ice_pf *pf, struct ice_vf *vf);</div><div class='ctx'> int ice_eswitch_rebuild(struct ice_pf *pf);</div><div class='ctx'> </div><div class='ctx'> int ice_eswitch_mode_get(struct devlink *devlink, u16 *mode);</div><div class='hunk'>@@ -17,7 +18,7 @@ ice_eswitch_mode_set(struct devlink *devlink, u16 mode,</div><div class='ctx'> 		     struct netlink_ext_ack *extack);</div><div class='ctx'> bool ice_is_eswitch_mode_switchdev(struct ice_pf *pf);</div><div class='ctx'> </div><div class='del'>-void ice_eswitch_update_repr(struct ice_vsi *vsi);</div><div class='add'>+void ice_eswitch_update_repr(unsigned long repr_id, struct ice_vsi *vsi);</div><div class='ctx'> </div><div class='ctx'> void ice_eswitch_stop_all_tx_queues(struct ice_pf *pf);</div><div class='ctx'> </div><div class='hunk'>@@ -25,8 +26,15 @@ void ice_eswitch_set_target_vsi(struct sk_buff *skb,</div><div class='ctx'> 				struct ice_tx_offload_params *off);</div><div class='ctx'> netdev_tx_t</div><div class='ctx'> ice_eswitch_port_start_xmit(struct sk_buff *skb, struct net_device *netdev);</div><div class='add'>+void ice_eswitch_reserve_cp_queues(struct ice_pf *pf, int change);</div><div class='ctx'> #else /* CONFIG_ICE_SWITCHDEV */</div><div class='del'>-static inline void ice_eswitch_release(struct ice_pf *pf) { }</div><div class='add'>+static inline void ice_eswitch_detach(struct ice_pf *pf, struct ice_vf *vf) { }</div><div class='add'>+</div><div class='add'>+static inline int</div><div class='add'>+ice_eswitch_attach(struct ice_pf *pf, struct ice_vf *vf)</div><div class='add'>+{</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static inline void ice_eswitch_stop_all_tx_queues(struct ice_pf *pf) { }</div><div class='ctx'> </div><div class='hunk'>@@ -34,7 +42,8 @@ static inline void</div><div class='ctx'> ice_eswitch_set_target_vsi(struct sk_buff *skb,</div><div class='ctx'> 			   struct ice_tx_offload_params *off) { }</div><div class='ctx'> </div><div class='del'>-static inline void ice_eswitch_update_repr(struct ice_vsi *vsi) { }</div><div class='add'>+static inline void</div><div class='add'>+ice_eswitch_update_repr(unsigned long repr_id, struct ice_vsi *vsi) { }</div><div class='ctx'> </div><div class='ctx'> static inline int ice_eswitch_configure(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='hunk'>@@ -68,5 +77,8 @@ ice_eswitch_port_start_xmit(struct sk_buff *skb, struct net_device *netdev)</div><div class='ctx'> {</div><div class='ctx'> 	return NETDEV_TX_BUSY;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+ice_eswitch_reserve_cp_queues(struct ice_pf *pf, int change) { }</div><div class='ctx'> #endif /* CONFIG_ICE_SWITCHDEV */</div><div class='ctx'> #endif /* _ICE_ESWITCH_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_eswitch_br.c b/drivers/net/ethernet/intel/ice/ice_eswitch_br.c<br/>index 6ae0269bdf73..ac5beecd028b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch_br.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_eswitch_br.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_eswitch_br.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_eswitch_br.c</a></div><div class='hunk'>@@ -893,10 +893,14 @@ ice_eswitch_br_port_deinit(struct ice_esw_br *bridge,</div><div class='ctx'> 			ice_eswitch_br_fdb_entry_delete(bridge, fdb_entry);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (br_port-&gt;type == ICE_ESWITCH_BR_UPLINK_PORT &amp;&amp; vsi-&gt;back)</div><div class='add'>+	if (br_port-&gt;type == ICE_ESWITCH_BR_UPLINK_PORT &amp;&amp; vsi-&gt;back) {</div><div class='ctx'> 		vsi-&gt;back-&gt;br_port = NULL;</div><div class='del'>-	else if (vsi-&gt;vf &amp;&amp; vsi-&gt;vf-&gt;repr)</div><div class='del'>-		vsi-&gt;vf-&gt;repr-&gt;br_port = NULL;</div><div class='add'>+	} else {</div><div class='add'>+		struct ice_repr *repr = ice_repr_get_by_vsi(vsi);</div><div class='add'>+</div><div class='add'>+		if (repr)</div><div class='add'>+			repr-&gt;br_port = NULL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	xa_erase(&amp;bridge-&gt;ports, br_port-&gt;vsi_idx);</div><div class='ctx'> 	ice_eswitch_br_port_vlans_flush(br_port);</div><div class='hunk'>@@ -947,7 +951,7 @@ ice_eswitch_br_vf_repr_port_init(struct ice_esw_br *bridge,</div><div class='ctx'> static int</div><div class='ctx'> ice_eswitch_br_uplink_port_init(struct ice_esw_br *bridge, struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_vsi *vsi = pf-&gt;switchdev.uplink_vsi;</div><div class='add'>+	struct ice_vsi *vsi = pf-&gt;eswitch.uplink_vsi;</div><div class='ctx'> 	struct ice_esw_br_port *br_port;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -1185,7 +1189,7 @@ ice_eswitch_br_port_event(struct notifier_block *nb,</div><div class='ctx'> static void</div><div class='ctx'> ice_eswitch_br_offloads_dealloc(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='del'>-	struct ice_esw_br_offloads *br_offloads = pf-&gt;switchdev.br_offloads;</div><div class='add'>+	struct ice_esw_br_offloads *br_offloads = pf-&gt;eswitch.br_offloads;</div><div class='ctx'> </div><div class='ctx'> 	ASSERT_RTNL();</div><div class='ctx'> </div><div class='hunk'>@@ -1194,7 +1198,7 @@ ice_eswitch_br_offloads_dealloc(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	ice_eswitch_br_deinit(br_offloads, br_offloads-&gt;bridge);</div><div class='ctx'> </div><div class='del'>-	pf-&gt;switchdev.br_offloads = NULL;</div><div class='add'>+	pf-&gt;eswitch.br_offloads = NULL;</div><div class='ctx'> 	kfree(br_offloads);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1205,14 +1209,14 @@ ice_eswitch_br_offloads_alloc(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	ASSERT_RTNL();</div><div class='ctx'> </div><div class='del'>-	if (pf-&gt;switchdev.br_offloads)</div><div class='add'>+	if (pf-&gt;eswitch.br_offloads)</div><div class='ctx'> 		return ERR_PTR(-EEXIST);</div><div class='ctx'> </div><div class='ctx'> 	br_offloads = kzalloc(sizeof(*br_offloads), GFP_KERNEL);</div><div class='ctx'> 	if (!br_offloads)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='del'>-	pf-&gt;switchdev.br_offloads = br_offloads;</div><div class='add'>+	pf-&gt;eswitch.br_offloads = br_offloads;</div><div class='ctx'> 	br_offloads-&gt;pf = pf;</div><div class='ctx'> </div><div class='ctx'> 	return br_offloads;</div><div class='hunk'>@@ -1223,7 +1227,7 @@ ice_eswitch_br_offloads_deinit(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_esw_br_offloads *br_offloads;</div><div class='ctx'> </div><div class='del'>-	br_offloads = pf-&gt;switchdev.br_offloads;</div><div class='add'>+	br_offloads = pf-&gt;eswitch.br_offloads;</div><div class='ctx'> 	if (!br_offloads)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c<br/>index a34083567e6f..a19b06f18e40 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ethtool.c</a></div><div class='hunk'>@@ -129,7 +129,6 @@ static const struct ice_stats ice_gstrings_pf_stats[] = {</div><div class='ctx'> 	ICE_PF_STAT("rx_oversize.nic", stats.rx_oversize),</div><div class='ctx'> 	ICE_PF_STAT("rx_jabber.nic", stats.rx_jabber),</div><div class='ctx'> 	ICE_PF_STAT("rx_csum_bad.nic", hw_csum_rx_error),</div><div class='del'>-	ICE_PF_STAT("rx_length_errors.nic", stats.rx_len_errors),</div><div class='ctx'> 	ICE_PF_STAT("rx_dropped.nic", stats.eth.rx_discards),</div><div class='ctx'> 	ICE_PF_STAT("rx_crc_errors.nic", stats.crc_errors),</div><div class='ctx'> 	ICE_PF_STAT("illegal_bytes.nic", stats.illegal_bytes),</div><div class='hunk'>@@ -1142,8 +1141,7 @@ __ice_get_strings(struct net_device *netdev, u32 stringset, u8 *data,</div><div class='ctx'> 	switch (stringset) {</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; ICE_VSI_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					ice_gstrings_vsi_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, ice_gstrings_vsi_stats[i].stat_string);</div><div class='ctx'> </div><div class='ctx'> 		if (ice_is_port_repr_netdev(netdev))</div><div class='ctx'> 			return;</div><div class='hunk'>@@ -1162,8 +1160,7 @@ __ice_get_strings(struct net_device *netdev, u32 stringset, u8 *data,</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; ICE_PF_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					ice_gstrings_pf_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, ice_gstrings_pf_stats[i].stat_string);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; ICE_MAX_USER_PRIORITY; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_priority_%u_xon.nic", i);</div><div class='hunk'>@@ -1179,8 +1176,7 @@ __ice_get_strings(struct net_device *netdev, u32 stringset, u8 *data,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETH_SS_PRIV_FLAGS:</div><div class='ctx'> 		for (i = 0; i &lt; ICE_PRIV_FLAG_ARRAY_SIZE; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					ice_gstrings_priv_flags[i].name);</div><div class='add'>+			ethtool_puts(&amp;p, ice_gstrings_priv_flags[i].name);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1850,14 +1846,14 @@ ice_phy_type_to_ethtool(struct net_device *netdev,</div><div class='ctx'> 	linkmode_zero(ks-&gt;link_modes.supported);</div><div class='ctx'> 	linkmode_zero(ks-&gt;link_modes.advertising);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; BITS_PER_TYPE(u64); i++) {</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(phy_type_low_lkup); i++) {</div><div class='ctx'> 		if (phy_types_low &amp; BIT_ULL(i))</div><div class='ctx'> 			ice_linkmode_set_bit(&amp;phy_type_low_lkup[i], ks,</div><div class='ctx'> 					     req_speeds, advert_phy_type_lo,</div><div class='ctx'> 					     i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; BITS_PER_TYPE(u64); i++) {</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(phy_type_high_lkup); i++) {</div><div class='ctx'> 		if (phy_types_high &amp; BIT_ULL(i))</div><div class='ctx'> 			ice_linkmode_set_bit(&amp;phy_type_high_lkup[i], ks,</div><div class='ctx'> 					     req_speeds, advert_phy_type_hi,</div><div class='hunk'>@@ -2505,27 +2501,15 @@ static u32 ice_parse_hdrs(struct ethtool_rxnfc *nfc)</div><div class='ctx'> 	return hdrs;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define ICE_FLOW_HASH_FLD_IPV4_SA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_IPV6_SA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_IPV4_DA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_IPV6_DA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_TCP_SRC_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_TCP_DST_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_UDP_SRC_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_UDP_DST_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_SCTP_SRC_PORT	\</div><div class='del'>-	BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT)</div><div class='del'>-#define ICE_FLOW_HASH_FLD_SCTP_DST_PORT	\</div><div class='del'>-	BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT)</div><div class='del'>-</div><div class='ctx'> /**</div><div class='ctx'>  * ice_parse_hash_flds - parses hash fields from RSS hash input</div><div class='ctx'>  * @nfc: ethtool rxnfc command</div><div class='add'>+ * @symm: true if Symmetric Topelitz is set</div><div class='ctx'>  *</div><div class='ctx'>  * This function parses the rxnfc command and returns intended</div><div class='ctx'>  * hash fields for RSS configuration</div><div class='ctx'>  */</div><div class='del'>-static u64 ice_parse_hash_flds(struct ethtool_rxnfc *nfc)</div><div class='add'>+static u64 ice_parse_hash_flds(struct ethtool_rxnfc *nfc, bool symm)</div><div class='ctx'> {</div><div class='ctx'> 	u64 hfld = ICE_HASH_INVALID;</div><div class='ctx'> </div><div class='hunk'>@@ -2594,9 +2578,11 @@ static int</div><div class='ctx'> ice_set_rss_hash_opt(struct ice_vsi *vsi, struct ethtool_rxnfc *nfc)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='add'>+	struct ice_rss_hash_cfg cfg;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	u64 hashed_flds;</div><div class='ctx'> 	int status;</div><div class='add'>+	bool symm;</div><div class='ctx'> 	u32 hdrs;</div><div class='ctx'> </div><div class='ctx'> 	dev = ice_pf_to_dev(pf);</div><div class='hunk'>@@ -2606,7 +2592,8 @@ ice_set_rss_hash_opt(struct ice_vsi *vsi, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	hashed_flds = ice_parse_hash_flds(nfc);</div><div class='add'>+	symm = !!(vsi-&gt;rss_hfunc == ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ);</div><div class='add'>+	hashed_flds = ice_parse_hash_flds(nfc, symm);</div><div class='ctx'> 	if (hashed_flds == ICE_HASH_INVALID) {</div><div class='ctx'> 		dev_dbg(dev, "Invalid hash fields, vsi num = %d\n",</div><div class='ctx'> 			vsi-&gt;vsi_num);</div><div class='hunk'>@@ -2620,7 +2607,12 @@ ice_set_rss_hash_opt(struct ice_vsi *vsi, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = ice_add_rss_cfg(&amp;pf-&gt;hw, vsi-&gt;idx, hashed_flds, hdrs);</div><div class='add'>+	cfg.hash_flds = hashed_flds;</div><div class='add'>+	cfg.addl_hdrs = hdrs;</div><div class='add'>+	cfg.hdr_type = ICE_RSS_ANY_HEADERS;</div><div class='add'>+	cfg.symm = symm;</div><div class='add'>+</div><div class='add'>+	status = ice_add_rss_cfg(&amp;pf-&gt;hw, vsi, &amp;cfg);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		dev_dbg(dev, "ice_add_rss_cfg failed, vsi num = %d, error = %d\n",</div><div class='ctx'> 			vsi-&gt;vsi_num, status);</div><div class='hunk'>@@ -2641,6 +2633,7 @@ ice_get_rss_hash_opt(struct ice_vsi *vsi, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	u64 hash_flds;</div><div class='add'>+	bool symm;</div><div class='ctx'> 	u32 hdrs;</div><div class='ctx'> </div><div class='ctx'> 	dev = ice_pf_to_dev(pf);</div><div class='hunk'>@@ -2659,7 +2652,7 @@ ice_get_rss_hash_opt(struct ice_vsi *vsi, struct ethtool_rxnfc *nfc)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	hash_flds = ice_get_rss_cfg(&amp;pf-&gt;hw, vsi-&gt;idx, hdrs);</div><div class='add'>+	hash_flds = ice_get_rss_cfg(&amp;pf-&gt;hw, vsi-&gt;idx, hdrs, &amp;symm);</div><div class='ctx'> 	if (hash_flds == ICE_HASH_INVALID) {</div><div class='ctx'> 		dev_dbg(dev, "No hash fields found for the given header type, vsi num = %d\n",</div><div class='ctx'> 			vsi-&gt;vsi_num);</div><div class='hunk'>@@ -3198,11 +3191,18 @@ static u32 ice_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return np-&gt;vsi-&gt;rss_table_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ice_get_rxfh - get the Rx flow hash indirection table</div><div class='add'>+ * @netdev: network interface device structure</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='add'>+ *</div><div class='add'>+ * Reads the indirection table directly from the hardware.</div><div class='add'>+ */</div><div class='ctx'> static int</div><div class='del'>-ice_get_rxfh_context(struct net_device *netdev, u32 *indir,</div><div class='del'>-		     u8 *key, u8 *hfunc, u32 rss_context)</div><div class='add'>+ice_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_netdev_priv *np = netdev_priv(netdev);</div><div class='add'>+	u32 rss_context = rxfh-&gt;rss_context;</div><div class='ctx'> 	struct ice_vsi *vsi = np-&gt;vsi;</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	u16 qcount, offset;</div><div class='hunk'>@@ -3233,17 +3233,18 @@ ice_get_rxfh_context(struct net_device *netdev, u32 *indir,</div><div class='ctx'> 		vsi = vsi-&gt;tc_map_vsi[rss_context];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (vsi-&gt;rss_hfunc == ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ)</div><div class='add'>+		rxfh-&gt;input_xfrm |= RXH_XFRM_SYM_XOR;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	lut = kzalloc(vsi-&gt;rss_table_size, GFP_KERNEL);</div><div class='ctx'> 	if (!lut)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	err = ice_get_rss_key(vsi, key);</div><div class='add'>+	err = ice_get_rss_key(vsi, rxfh-&gt;key);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='hunk'>@@ -3253,12 +3254,12 @@ ice_get_rxfh_context(struct net_device *netdev, u32 *indir,</div><div class='ctx'> </div><div class='ctx'> 	if (ice_is_adq_active(pf)) {</div><div class='ctx'> 		for (i = 0; i &lt; vsi-&gt;rss_table_size; i++)</div><div class='del'>-			indir[i] = offset + lut[i] % qcount;</div><div class='add'>+			rxfh-&gt;indir[i] = offset + lut[i] % qcount;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; vsi-&gt;rss_table_size; i++)</div><div class='del'>-		indir[i] = lut[i];</div><div class='add'>+		rxfh-&gt;indir[i] = lut[i];</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	kfree(lut);</div><div class='hunk'>@@ -3266,42 +3267,31 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_get_rxfh - get the Rx flow hash indirection table</div><div class='del'>- * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function</div><div class='del'>- *</div><div class='del'>- * Reads the indirection table directly from the hardware.</div><div class='del'>- */</div><div class='del'>-static int</div><div class='del'>-ice_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	return ice_get_rxfh_context(netdev, indir, key, hfunc, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ice_set_rxfh - set the Rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='add'>+ * @extack: extended ACK from the Netlink message</div><div class='ctx'>  *</div><div class='ctx'>  * Returns -EINVAL if the table specifies an invalid queue ID, otherwise</div><div class='ctx'>  * returns 0 after programming the table.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='del'>-	     const u8 hfunc)</div><div class='add'>+ice_set_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+	     struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_netdev_priv *np = netdev_priv(netdev);</div><div class='add'>+	u8 hfunc = ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ;</div><div class='ctx'> 	struct ice_vsi *vsi = np-&gt;vsi;</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	dev = ice_pf_to_dev(pf);</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (!test_bit(ICE_FLAG_RSS_ENA, pf-&gt;flags)) {</div><div class='hunk'>@@ -3315,7 +3305,15 @@ ice_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='add'>+	/* Update the VSI's hash function */</div><div class='add'>+	if (rxfh-&gt;input_xfrm &amp; RXH_XFRM_SYM_XOR)</div><div class='add'>+		hfunc = ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ;</div><div class='add'>+</div><div class='add'>+	err = ice_set_rss_hfunc(vsi, hfunc);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='ctx'> 		if (!vsi-&gt;rss_hkey_user) {</div><div class='ctx'> 			vsi-&gt;rss_hkey_user =</div><div class='ctx'> 				devm_kzalloc(dev, ICE_VSIQF_HKEY_ARRAY_SIZE,</div><div class='hunk'>@@ -3323,7 +3321,8 @@ ice_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='ctx'> 			if (!vsi-&gt;rss_hkey_user)</div><div class='ctx'> 				return -ENOMEM;</div><div class='ctx'> 		}</div><div class='del'>-		memcpy(vsi-&gt;rss_hkey_user, key, ICE_VSIQF_HKEY_ARRAY_SIZE);</div><div class='add'>+		memcpy(vsi-&gt;rss_hkey_user, rxfh-&gt;key,</div><div class='add'>+		       ICE_VSIQF_HKEY_ARRAY_SIZE);</div><div class='ctx'> </div><div class='ctx'> 		err = ice_set_rss_key(vsi, vsi-&gt;rss_hkey_user);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -3338,11 +3337,11 @@ ice_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Each 32 bits pointed by 'indir' is stored with a lut entry */</div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; vsi-&gt;rss_table_size; i++)</div><div class='del'>-			vsi-&gt;rss_lut_user[i] = (u8)(indir[i]);</div><div class='add'>+			vsi-&gt;rss_lut_user[i] = (u8)(rxfh-&gt;indir[i]);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ice_fill_rss_lut(vsi-&gt;rss_lut_user, vsi-&gt;rss_table_size,</div><div class='ctx'> 				 vsi-&gt;rss_size);</div><div class='hunk'>@@ -4220,9 +4219,11 @@ ice_get_module_eeprom(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops ice_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported  = true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE |</div><div class='ctx'> 				     ETHTOOL_COALESCE_RX_USECS_HIGH,</div><div class='add'>+	.cap_rss_sym_xor_supported = true,</div><div class='ctx'> 	.get_link_ksettings	= ice_get_link_ksettings,</div><div class='ctx'> 	.set_link_ksettings	= ice_set_link_ksettings,</div><div class='ctx'> 	.get_drvinfo		= ice_get_drvinfo,</div><div class='hunk'>@@ -4253,7 +4254,6 @@ static const struct ethtool_ops ice_ethtool_ops = {</div><div class='ctx'> 	.set_pauseparam		= ice_set_pauseparam,</div><div class='ctx'> 	.get_rxfh_key_size	= ice_get_rxfh_key_size,</div><div class='ctx'> 	.get_rxfh_indir_size	= ice_get_rxfh_indir_size,</div><div class='del'>-	.get_rxfh_context	= ice_get_rxfh_context,</div><div class='ctx'> 	.get_rxfh		= ice_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= ice_set_rxfh,</div><div class='ctx'> 	.get_channels		= ice_get_channels,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c b/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c<br/>index d151e5bacfec..9a1a04f5f146 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ethtool_fdir.c</a></div><div class='hunk'>@@ -302,9 +302,7 @@ void ice_fdir_rem_adq_chnl(struct ice_hw *hw, u16 vsi_idx)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		for (tun = 0; tun &lt; ICE_FD_HW_SEG_MAX; tun++) {</div><div class='del'>-			u64 prof_id;</div><div class='del'>-</div><div class='del'>-			prof_id = flow + tun * ICE_FLTR_PTYPE_MAX;</div><div class='add'>+			u64 prof_id = prof-&gt;prof_id[tun];</div><div class='ctx'> </div><div class='ctx'> 			for (i = 0; i &lt; prof-&gt;cnt; i++) {</div><div class='ctx'> 				if (prof-&gt;vsi_h[i] != vsi_idx)</div><div class='hunk'>@@ -362,10 +360,9 @@ ice_fdir_erase_flow_from_hw(struct ice_hw *hw, enum ice_block blk, int flow)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (tun = 0; tun &lt; ICE_FD_HW_SEG_MAX; tun++) {</div><div class='del'>-		u64 prof_id;</div><div class='add'>+		u64 prof_id = prof-&gt;prof_id[tun];</div><div class='ctx'> 		int j;</div><div class='ctx'> </div><div class='del'>-		prof_id = flow + tun * ICE_FLTR_PTYPE_MAX;</div><div class='ctx'> 		for (j = 0; j &lt; prof-&gt;cnt; j++) {</div><div class='ctx'> 			u16 vsi_num;</div><div class='ctx'> </div><div class='hunk'>@@ -439,14 +436,12 @@ void ice_fdir_replay_flows(struct ice_hw *hw)</div><div class='ctx'> 		for (tun = 0; tun &lt; ICE_FD_HW_SEG_MAX; tun++) {</div><div class='ctx'> 			struct ice_flow_prof *hw_prof;</div><div class='ctx'> 			struct ice_fd_hw_prof *prof;</div><div class='del'>-			u64 prof_id;</div><div class='ctx'> 			int j;</div><div class='ctx'> </div><div class='ctx'> 			prof = hw-&gt;fdir_prof[flow];</div><div class='del'>-			prof_id = flow + tun * ICE_FLTR_PTYPE_MAX;</div><div class='del'>-			ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX, prof_id,</div><div class='add'>+			ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX,</div><div class='ctx'> 					  prof-&gt;fdir_seg[tun], TNL_SEG_CNT(tun),</div><div class='del'>-					  &amp;hw_prof);</div><div class='add'>+					  false, &amp;hw_prof);</div><div class='ctx'> 			for (j = 0; j &lt; prof-&gt;cnt; j++) {</div><div class='ctx'> 				enum ice_flow_priority prio;</div><div class='ctx'> 				u64 entry_h = 0;</div><div class='hunk'>@@ -454,7 +449,7 @@ void ice_fdir_replay_flows(struct ice_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 				prio = ICE_FLOW_PRIO_NORMAL;</div><div class='ctx'> 				err = ice_flow_add_entry(hw, ICE_BLK_FD,</div><div class='del'>-							 prof_id,</div><div class='add'>+							 hw_prof-&gt;id,</div><div class='ctx'> 							 prof-&gt;vsi_h[0],</div><div class='ctx'> 							 prof-&gt;vsi_h[j],</div><div class='ctx'> 							 prio, prof-&gt;fdir_seg,</div><div class='hunk'>@@ -464,6 +459,7 @@ void ice_fdir_replay_flows(struct ice_hw *hw)</div><div class='ctx'> 						flow);</div><div class='ctx'> 					continue;</div><div class='ctx'> 				}</div><div class='add'>+				prof-&gt;prof_id[tun] = hw_prof-&gt;id;</div><div class='ctx'> 				prof-&gt;entry_h[j][tun] = entry_h;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -507,8 +503,7 @@ ice_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;flex_word = value &amp; ICE_USERDEF_FLEX_WORD_M;</div><div class='del'>-	data-&gt;flex_offset = (value &amp; ICE_USERDEF_FLEX_OFFS_M) &gt;&gt;</div><div class='del'>-			     ICE_USERDEF_FLEX_OFFS_S;</div><div class='add'>+	data-&gt;flex_offset = FIELD_GET(ICE_USERDEF_FLEX_OFFS_M, value);</div><div class='ctx'> 	if (data-&gt;flex_offset &gt; ICE_USERDEF_FLEX_MAX_OFFS_VAL)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='hunk'>@@ -638,7 +633,6 @@ ice_fdir_set_hw_fltr_rule(struct ice_pf *pf, struct ice_flow_seg_info *seg,</div><div class='ctx'> 	u64 entry1_h = 0;</div><div class='ctx'> 	u64 entry2_h = 0;</div><div class='ctx'> 	bool del_last;</div><div class='del'>-	u64 prof_id;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	int idx;</div><div class='ctx'> </div><div class='hunk'>@@ -668,7 +662,7 @@ ice_fdir_set_hw_fltr_rule(struct ice_pf *pf, struct ice_flow_seg_info *seg,</div><div class='ctx'> 		 * then return error.</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (hw-&gt;fdir_fltr_cnt[flow]) {</div><div class='del'>-			dev_err(dev, "Failed to add filter.  Flow director filters on each port must have the same input set.\n");</div><div class='add'>+			dev_err(dev, "Failed to add filter. Flow director filters on each port must have the same input set.\n");</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -686,23 +680,23 @@ ice_fdir_set_hw_fltr_rule(struct ice_pf *pf, struct ice_flow_seg_info *seg,</div><div class='ctx'> 	 * That is the final parameters are 1 header (segment), no</div><div class='ctx'> 	 * actions (NULL) and zero actions 0.</div><div class='ctx'> 	 */</div><div class='del'>-	prof_id = flow + tun * ICE_FLTR_PTYPE_MAX;</div><div class='del'>-	err = ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX, prof_id, seg,</div><div class='del'>-				TNL_SEG_CNT(tun), &amp;prof);</div><div class='add'>+	err = ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX, seg,</div><div class='add'>+				TNL_SEG_CNT(tun), false, &amp;prof);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='del'>-	err = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id, main_vsi-&gt;idx,</div><div class='add'>+	err = ice_flow_add_entry(hw, ICE_BLK_FD, prof-&gt;id, main_vsi-&gt;idx,</div><div class='ctx'> 				 main_vsi-&gt;idx, ICE_FLOW_PRIO_NORMAL,</div><div class='ctx'> 				 seg, &amp;entry1_h);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_prof;</div><div class='del'>-	err = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id, main_vsi-&gt;idx,</div><div class='add'>+	err = ice_flow_add_entry(hw, ICE_BLK_FD, prof-&gt;id, main_vsi-&gt;idx,</div><div class='ctx'> 				 ctrl_vsi-&gt;idx, ICE_FLOW_PRIO_NORMAL,</div><div class='ctx'> 				 seg, &amp;entry2_h);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_entry;</div><div class='ctx'> </div><div class='ctx'> 	hw_prof-&gt;fdir_seg[tun] = seg;</div><div class='add'>+	hw_prof-&gt;prof_id[tun] = prof-&gt;id;</div><div class='ctx'> 	hw_prof-&gt;entry_h[0][tun] = entry1_h;</div><div class='ctx'> 	hw_prof-&gt;entry_h[1][tun] = entry2_h;</div><div class='ctx'> 	hw_prof-&gt;vsi_h[0] = main_vsi-&gt;idx;</div><div class='hunk'>@@ -719,7 +713,7 @@ ice_fdir_set_hw_fltr_rule(struct ice_pf *pf, struct ice_flow_seg_info *seg,</div><div class='ctx'> </div><div class='ctx'> 		entry1_h = 0;</div><div class='ctx'> 		vsi_h = main_vsi-&gt;tc_map_vsi[idx]-&gt;idx;</div><div class='del'>-		err = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id,</div><div class='add'>+		err = ice_flow_add_entry(hw, ICE_BLK_FD, prof-&gt;id,</div><div class='ctx'> 					 main_vsi-&gt;idx, vsi_h,</div><div class='ctx'> 					 ICE_FLOW_PRIO_NORMAL, seg,</div><div class='ctx'> 					 &amp;entry1_h);</div><div class='hunk'>@@ -756,7 +750,7 @@ err_unroll:</div><div class='ctx'> </div><div class='ctx'> 		if (!hw_prof-&gt;entry_h[idx][tun])</div><div class='ctx'> 			continue;</div><div class='del'>-		ice_rem_prof_id_flow(hw, ICE_BLK_FD, vsi_num, prof_id);</div><div class='add'>+		ice_rem_prof_id_flow(hw, ICE_BLK_FD, vsi_num, prof-&gt;id);</div><div class='ctx'> 		ice_flow_rem_entry(hw, ICE_BLK_FD, hw_prof-&gt;entry_h[idx][tun]);</div><div class='ctx'> 		hw_prof-&gt;entry_h[idx][tun] = 0;</div><div class='ctx'> 		if (del_last)</div><div class='hunk'>@@ -766,11 +760,11 @@ err_unroll:</div><div class='ctx'> 		hw_prof-&gt;cnt = 0;</div><div class='ctx'> err_entry:</div><div class='ctx'> 	ice_rem_prof_id_flow(hw, ICE_BLK_FD,</div><div class='del'>-			     ice_get_hw_vsi_num(hw, main_vsi-&gt;idx), prof_id);</div><div class='add'>+			     ice_get_hw_vsi_num(hw, main_vsi-&gt;idx), prof-&gt;id);</div><div class='ctx'> 	ice_flow_rem_entry(hw, ICE_BLK_FD, entry1_h);</div><div class='ctx'> err_prof:</div><div class='del'>-	ice_flow_rem_prof(hw, ICE_BLK_FD, prof_id);</div><div class='del'>-	dev_err(dev, "Failed to add filter.  Flow director filters on each port must have the same input set.\n");</div><div class='add'>+	ice_flow_rem_prof(hw, ICE_BLK_FD, prof-&gt;id);</div><div class='add'>+	dev_err(dev, "Failed to add filter. Flow director filters on each port must have the same input set.\n");</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -1853,6 +1847,7 @@ int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 	struct ice_pf *pf;</div><div class='ctx'> 	struct ice_hw *hw;</div><div class='ctx'> 	int fltrs_needed;</div><div class='add'>+	u32 max_location;</div><div class='ctx'> 	u16 tunnel_port;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1884,8 +1879,10 @@ int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (fsp-&gt;location &gt;= ice_get_fdir_cnt_all(hw)) {</div><div class='del'>-		dev_err(dev, "Failed to add filter.  The maximum number of flow director filters has been reached.\n");</div><div class='add'>+	max_location = ice_get_fdir_cnt_all(hw);</div><div class='add'>+	if (fsp-&gt;location &gt;= max_location) {</div><div class='add'>+		dev_err(dev, "Failed to add filter. The number of ntuple filters or provided location exceed max %d.\n",</div><div class='add'>+			max_location);</div><div class='ctx'> 		return -ENOSPC;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1893,7 +1890,7 @@ int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd)</div><div class='ctx'> 	fltrs_needed = ice_get_open_tunnel_port(hw, &amp;tunnel_port, TNL_ALL) ? 2 : 1;</div><div class='ctx'> 	if (!ice_fdir_find_fltr_by_idx(hw, fsp-&gt;location) &amp;&amp;</div><div class='ctx'> 	    ice_fdir_num_avail_fltr(hw, pf-&gt;vsi[vsi-&gt;idx]) &lt; fltrs_needed) {</div><div class='del'>-		dev_err(dev, "Failed to add filter.  The maximum number of flow director filters has been reached.\n");</div><div class='add'>+		dev_err(dev, "Failed to add filter. The maximum number of flow director filters has been reached.\n");</div><div class='ctx'> 		return -ENOSPC;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_fdir.c b/drivers/net/ethernet/intel/ice/ice_fdir.c<br/>index ae089d32ee9d..5840c3e04a5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_fdir.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_fdir.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fdir.c</a></div><div class='hunk'>@@ -604,55 +604,32 @@ ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx,</div><div class='ctx'> 	u64 qword;</div><div class='ctx'> </div><div class='ctx'> 	/* prep QW0 of FD filter programming desc */</div><div class='del'>-	qword = ((u64)ctx-&gt;qindex &lt;&lt; ICE_FXD_FLTR_QW0_QINDEX_S) &amp;</div><div class='del'>-		ICE_FXD_FLTR_QW0_QINDEX_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;comp_q &lt;&lt; ICE_FXD_FLTR_QW0_COMP_Q_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_COMP_Q_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;comp_report &lt;&lt; ICE_FXD_FLTR_QW0_COMP_REPORT_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_COMP_REPORT_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;fd_space &lt;&lt; ICE_FXD_FLTR_QW0_FD_SPACE_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_FD_SPACE_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;cnt_index &lt;&lt; ICE_FXD_FLTR_QW0_STAT_CNT_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_STAT_CNT_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;cnt_ena &lt;&lt; ICE_FXD_FLTR_QW0_STAT_ENA_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_STAT_ENA_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;evict_ena &lt;&lt; ICE_FXD_FLTR_QW0_EVICT_ENA_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_EVICT_ENA_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;toq &lt;&lt; ICE_FXD_FLTR_QW0_TO_Q_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_TO_Q_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;toq_prio &lt;&lt; ICE_FXD_FLTR_QW0_TO_Q_PRI_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_TO_Q_PRI_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;dpu_recipe &lt;&lt; ICE_FXD_FLTR_QW0_DPU_RECIPE_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_DPU_RECIPE_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;drop &lt;&lt; ICE_FXD_FLTR_QW0_DROP_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_DROP_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;flex_prio &lt;&lt; ICE_FXD_FLTR_QW0_FLEX_PRI_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_FLEX_PRI_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;flex_mdid &lt;&lt; ICE_FXD_FLTR_QW0_FLEX_MDID_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_FLEX_MDID_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;flex_val &lt;&lt; ICE_FXD_FLTR_QW0_FLEX_VAL_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW0_FLEX_VAL_M;</div><div class='add'>+	qword = FIELD_PREP(ICE_FXD_FLTR_QW0_QINDEX_M, ctx-&gt;qindex);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_COMP_Q_M, ctx-&gt;comp_q);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_COMP_REPORT_M, ctx-&gt;comp_report);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FD_SPACE_M, ctx-&gt;fd_space);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_STAT_CNT_M, ctx-&gt;cnt_index);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_STAT_ENA_M, ctx-&gt;cnt_ena);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_EVICT_ENA_M, ctx-&gt;evict_ena);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_TO_Q_M, ctx-&gt;toq);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_TO_Q_PRI_M, ctx-&gt;toq_prio);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_DPU_RECIPE_M, ctx-&gt;dpu_recipe);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_DROP_M, ctx-&gt;drop);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_PRI_M, ctx-&gt;flex_prio);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_MDID_M, ctx-&gt;flex_mdid);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW0_FLEX_VAL_M, ctx-&gt;flex_val);</div><div class='ctx'> 	fdir_desc-&gt;qidx_compq_space_stat = cpu_to_le64(qword);</div><div class='ctx'> </div><div class='ctx'> 	/* prep QW1 of FD filter programming desc */</div><div class='del'>-	qword = ((u64)ctx-&gt;dtype &lt;&lt; ICE_FXD_FLTR_QW1_DTYPE_S) &amp;</div><div class='del'>-		ICE_FXD_FLTR_QW1_DTYPE_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;pcmd &lt;&lt; ICE_FXD_FLTR_QW1_PCMD_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_PCMD_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;desc_prof_prio &lt;&lt; ICE_FXD_FLTR_QW1_PROF_PRI_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_PROF_PRI_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;desc_prof &lt;&lt; ICE_FXD_FLTR_QW1_PROF_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_PROF_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;fd_vsi &lt;&lt; ICE_FXD_FLTR_QW1_FD_VSI_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_FD_VSI_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;swap &lt;&lt; ICE_FXD_FLTR_QW1_SWAP_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_SWAP_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;fdid_prio &lt;&lt; ICE_FXD_FLTR_QW1_FDID_PRI_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_FDID_PRI_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;fdid_mdid &lt;&lt; ICE_FXD_FLTR_QW1_FDID_MDID_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_FDID_MDID_M;</div><div class='del'>-	qword |= ((u64)ctx-&gt;fdid &lt;&lt; ICE_FXD_FLTR_QW1_FDID_S) &amp;</div><div class='del'>-		 ICE_FXD_FLTR_QW1_FDID_M;</div><div class='add'>+	qword = FIELD_PREP(ICE_FXD_FLTR_QW1_DTYPE_M, ctx-&gt;dtype);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PCMD_M, ctx-&gt;pcmd);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PROF_PRI_M, ctx-&gt;desc_prof_prio);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_PROF_M, ctx-&gt;desc_prof);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FD_VSI_M, ctx-&gt;fd_vsi);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_SWAP_M, ctx-&gt;swap);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_PRI_M, ctx-&gt;fdid_prio);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_MDID_M, ctx-&gt;fdid_mdid);</div><div class='add'>+	qword |= FIELD_PREP(ICE_FXD_FLTR_QW1_FDID_M, ctx-&gt;fdid);</div><div class='ctx'> 	fdir_desc-&gt;dtype_cmd_vsi_fdid = cpu_to_le64(qword);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_flex_pipe.c b/drivers/net/ethernet/intel/ice/ice_flex_pipe.c<br/>index 5ce413965930..20d5db88c99f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_pipe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_flex_pipe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_pipe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_pipe.c</a></div><div class='hunk'>@@ -1218,11 +1218,13 @@ ice_prof_has_mask(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 *masks)</div><div class='ctx'>  * @blk: HW block</div><div class='ctx'>  * @fv: field vector to search for</div><div class='ctx'>  * @masks: masks for FV</div><div class='add'>+ * @symm: symmetric setting for RSS flows</div><div class='ctx'>  * @prof_id: receives the profile ID</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='ctx'> ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,</div><div class='del'>-			   struct ice_fv_word *fv, u16 *masks, u8 *prof_id)</div><div class='add'>+			   struct ice_fv_word *fv, u16 *masks, bool symm,</div><div class='add'>+			   u8 *prof_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_es *es = &amp;hw-&gt;blk[blk].es;</div><div class='ctx'> 	u8 i;</div><div class='hunk'>@@ -1236,6 +1238,9 @@ ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 	for (i = 0; i &lt; (u8)es-&gt;count; i++) {</div><div class='ctx'> 		u16 off = i * es-&gt;fvw;</div><div class='ctx'> </div><div class='add'>+		if (blk == ICE_BLK_RSS &amp;&amp; es-&gt;symm[i] != symm)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		if (memcmp(&amp;es-&gt;t[off], fv, es-&gt;fvw * sizeof(*fv)))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='hunk'>@@ -1409,13 +1414,13 @@ ice_write_prof_mask_reg(struct ice_hw *hw, enum ice_block blk, u16 mask_idx,</div><div class='ctx'> 	switch (blk) {</div><div class='ctx'> 	case ICE_BLK_RSS:</div><div class='ctx'> 		offset = GLQF_HMASK(mask_idx);</div><div class='del'>-		val = (idx &lt;&lt; GLQF_HMASK_MSK_INDEX_S) &amp; GLQF_HMASK_MSK_INDEX_M;</div><div class='del'>-		val |= (mask &lt;&lt; GLQF_HMASK_MASK_S) &amp; GLQF_HMASK_MASK_M;</div><div class='add'>+		val = FIELD_PREP(GLQF_HMASK_MSK_INDEX_M, idx);</div><div class='add'>+		val |= FIELD_PREP(GLQF_HMASK_MASK_M, mask);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_BLK_FD:</div><div class='ctx'> 		offset = GLQF_FDMASK(mask_idx);</div><div class='del'>-		val = (idx &lt;&lt; GLQF_FDMASK_MSK_INDEX_S) &amp; GLQF_FDMASK_MSK_INDEX_M;</div><div class='del'>-		val |= (mask &lt;&lt; GLQF_FDMASK_MASK_S) &amp; GLQF_FDMASK_MASK_M;</div><div class='add'>+		val = FIELD_PREP(GLQF_FDMASK_MSK_INDEX_M, idx);</div><div class='add'>+		val |= FIELD_PREP(GLQF_FDMASK_MASK_M, mask);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PKG, "No profile masks for block %d\n",</div><div class='hunk'>@@ -1716,15 +1721,16 @@ ice_update_prof_masking(struct ice_hw *hw, enum ice_block blk, u16 prof_id,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_es - write an extraction sequence to hardware</div><div class='add'>+ * ice_write_es - write an extraction sequence and symmetric setting to hardware</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @blk: the block in which to write the extraction sequence</div><div class='ctx'>  * @prof_id: the profile ID to write</div><div class='ctx'>  * @fv: pointer to the extraction sequence to write - NULL to clear extraction</div><div class='add'>+ * @symm: symmetric setting for RSS profiles</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='ctx'> ice_write_es(struct ice_hw *hw, enum ice_block blk, u8 prof_id,</div><div class='del'>-	     struct ice_fv_word *fv)</div><div class='add'>+	     struct ice_fv_word *fv, bool symm)</div><div class='ctx'> {</div><div class='ctx'> 	u16 off;</div><div class='ctx'> </div><div class='hunk'>@@ -1737,6 +1743,9 @@ ice_write_es(struct ice_hw *hw, enum ice_block blk, u8 prof_id,</div><div class='ctx'> 		memcpy(&amp;hw-&gt;blk[blk].es.t[off], fv,</div><div class='ctx'> 		       hw-&gt;blk[blk].es.fvw * sizeof(*fv));</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	if (blk == ICE_BLK_RSS)</div><div class='add'>+		hw-&gt;blk[blk].es.symm[prof_id] = symm;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1753,7 +1762,7 @@ ice_prof_dec_ref(struct ice_hw *hw, enum ice_block blk, u8 prof_id)</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;blk[blk].es.ref_count[prof_id] &gt; 0) {</div><div class='ctx'> 		if (!--hw-&gt;blk[blk].es.ref_count[prof_id]) {</div><div class='del'>-			ice_write_es(hw, blk, prof_id, NULL);</div><div class='add'>+			ice_write_es(hw, blk, prof_id, NULL, false);</div><div class='ctx'> 			ice_free_prof_masks(hw, blk, prof_id);</div><div class='ctx'> 			return ice_free_prof_id(hw, blk, prof_id);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2116,8 +2125,10 @@ void ice_free_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].prof_redir.t);</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].es.t);</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].es.ref_count);</div><div class='add'>+		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].es.symm);</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].es.written);</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].es.mask_ena);</div><div class='add'>+		devm_kfree(ice_hw_to_dev(hw), hw-&gt;blk[i].prof_id.id);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	list_for_each_entry_safe(r, rt, &amp;hw-&gt;rss_list_head, l_entry) {</div><div class='hunk'>@@ -2150,6 +2161,7 @@ void ice_clear_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ICE_BLK_COUNT; i++) {</div><div class='ctx'> 		struct ice_prof_redir *prof_redir = &amp;hw-&gt;blk[i].prof_redir;</div><div class='add'>+		struct ice_prof_id *prof_id = &amp;hw-&gt;blk[i].prof_id;</div><div class='ctx'> 		struct ice_prof_tcam *prof = &amp;hw-&gt;blk[i].prof;</div><div class='ctx'> 		struct ice_xlt1 *xlt1 = &amp;hw-&gt;blk[i].xlt1;</div><div class='ctx'> 		struct ice_xlt2 *xlt2 = &amp;hw-&gt;blk[i].xlt2;</div><div class='hunk'>@@ -2178,8 +2190,11 @@ void ice_clear_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 		memset(es-&gt;t, 0, es-&gt;count * sizeof(*es-&gt;t) * es-&gt;fvw);</div><div class='ctx'> 		memset(es-&gt;ref_count, 0, es-&gt;count * sizeof(*es-&gt;ref_count));</div><div class='add'>+		memset(es-&gt;symm, 0, es-&gt;count * sizeof(*es-&gt;symm));</div><div class='ctx'> 		memset(es-&gt;written, 0, es-&gt;count * sizeof(*es-&gt;written));</div><div class='ctx'> 		memset(es-&gt;mask_ena, 0, es-&gt;count * sizeof(*es-&gt;mask_ena));</div><div class='add'>+</div><div class='add'>+		memset(prof_id-&gt;id, 0, prof_id-&gt;count * sizeof(*prof_id-&gt;id));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2196,6 +2211,7 @@ int ice_init_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> 	ice_init_all_prof_masks(hw);</div><div class='ctx'> 	for (i = 0; i &lt; ICE_BLK_COUNT; i++) {</div><div class='ctx'> 		struct ice_prof_redir *prof_redir = &amp;hw-&gt;blk[i].prof_redir;</div><div class='add'>+		struct ice_prof_id *prof_id = &amp;hw-&gt;blk[i].prof_id;</div><div class='ctx'> 		struct ice_prof_tcam *prof = &amp;hw-&gt;blk[i].prof;</div><div class='ctx'> 		struct ice_xlt1 *xlt1 = &amp;hw-&gt;blk[i].xlt1;</div><div class='ctx'> 		struct ice_xlt2 *xlt2 = &amp;hw-&gt;blk[i].xlt2;</div><div class='hunk'>@@ -2292,6 +2308,11 @@ int ice_init_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> 		if (!es-&gt;ref_count)</div><div class='ctx'> 			goto err;</div><div class='ctx'> </div><div class='add'>+		es-&gt;symm = devm_kcalloc(ice_hw_to_dev(hw), es-&gt;count,</div><div class='add'>+					sizeof(*es-&gt;symm), GFP_KERNEL);</div><div class='add'>+		if (!es-&gt;symm)</div><div class='add'>+			goto err;</div><div class='add'>+</div><div class='ctx'> 		es-&gt;written = devm_kcalloc(ice_hw_to_dev(hw), es-&gt;count,</div><div class='ctx'> 					   sizeof(*es-&gt;written), GFP_KERNEL);</div><div class='ctx'> 		if (!es-&gt;written)</div><div class='hunk'>@@ -2301,6 +2322,12 @@ int ice_init_hw_tbls(struct ice_hw *hw)</div><div class='ctx'> 					    sizeof(*es-&gt;mask_ena), GFP_KERNEL);</div><div class='ctx'> 		if (!es-&gt;mask_ena)</div><div class='ctx'> 			goto err;</div><div class='add'>+</div><div class='add'>+		prof_id-&gt;count = blk_sizes[i].prof_id;</div><div class='add'>+		prof_id-&gt;id = devm_kcalloc(ice_hw_to_dev(hw), prof_id-&gt;count,</div><div class='add'>+					   sizeof(*prof_id-&gt;id), GFP_KERNEL);</div><div class='add'>+		if (!prof_id-&gt;id)</div><div class='add'>+			goto err;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2963,6 +2990,7 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype,</div><div class='ctx'>  * @attr_cnt: number of elements in attr array</div><div class='ctx'>  * @es: extraction sequence (length of array is determined by the block)</div><div class='ctx'>  * @masks: mask for extraction sequence</div><div class='add'>+ * @symm: symmetric setting for RSS profiles</div><div class='ctx'>  *</div><div class='ctx'>  * This function registers a profile, which matches a set of PTYPES with a</div><div class='ctx'>  * particular extraction sequence. While the hardware profile is allocated</div><div class='hunk'>@@ -2972,7 +3000,7 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype,</div><div class='ctx'> int</div><div class='ctx'> ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],</div><div class='ctx'> 	     const struct ice_ptype_attributes *attr, u16 attr_cnt,</div><div class='del'>-	     struct ice_fv_word *es, u16 *masks)</div><div class='add'>+	     struct ice_fv_word *es, u16 *masks, bool symm)</div><div class='ctx'> {</div><div class='ctx'> 	u32 bytes = DIV_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);</div><div class='ctx'> 	DECLARE_BITMAP(ptgs_used, ICE_XLT1_CNT);</div><div class='hunk'>@@ -2986,7 +3014,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],</div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;blk[blk].es.prof_map_lock);</div><div class='ctx'> </div><div class='ctx'> 	/* search for existing profile */</div><div class='del'>-	status = ice_find_prof_id_with_mask(hw, blk, es, masks, &amp;prof_id);</div><div class='add'>+	status = ice_find_prof_id_with_mask(hw, blk, es, masks, symm, &amp;prof_id);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		/* allocate profile ID */</div><div class='ctx'> 		status = ice_alloc_prof_id(hw, blk, &amp;prof_id);</div><div class='hunk'>@@ -3009,7 +3037,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],</div><div class='ctx'> 			goto err_ice_add_prof;</div><div class='ctx'> </div><div class='ctx'> 		/* and write new es */</div><div class='del'>-		ice_write_es(hw, blk, prof_id, es);</div><div class='add'>+		ice_write_es(hw, blk, prof_id, es, symm);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ice_prof_inc_ref(hw, blk, prof_id);</div><div class='hunk'>@@ -3097,7 +3125,7 @@ err_ice_add_prof:</div><div class='ctx'>  * This will search for a profile tracking ID which was previously added.</div><div class='ctx'>  * The profile map lock should be held before calling this function.</div><div class='ctx'>  */</div><div class='del'>-static struct ice_prof_map *</div><div class='add'>+struct ice_prof_map *</div><div class='ctx'> ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_prof_map *entry = NULL;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_flex_pipe.h b/drivers/net/ethernet/intel/ice/ice_flex_pipe.h<br/>index 7af7c8e9aa4e..b39d7cdc381f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_pipe.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_flex_pipe.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_pipe.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_pipe.h</a></div><div class='hunk'>@@ -42,7 +42,9 @@ bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype);</div><div class='ctx'> int</div><div class='ctx'> ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],</div><div class='ctx'> 	     const struct ice_ptype_attributes *attr, u16 attr_cnt,</div><div class='del'>-	     struct ice_fv_word *es, u16 *masks);</div><div class='add'>+	     struct ice_fv_word *es, u16 *masks, bool symm);</div><div class='add'>+struct ice_prof_map *</div><div class='add'>+ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);</div><div class='ctx'> int</div><div class='ctx'> ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);</div><div class='ctx'> int</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_flex_type.h b/drivers/net/ethernet/intel/ice/ice_flex_type.h<br/>index 4f42e14ed3ae..d427a79d001a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_flex_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flex_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flex_type.h</a></div><div class='hunk'>@@ -146,6 +146,7 @@ struct ice_es {</div><div class='ctx'> 	u32 *mask_ena;</div><div class='ctx'> 	struct list_head prof_map;</div><div class='ctx'> 	struct ice_fv_word *t;</div><div class='add'>+	u8 *symm;	/* symmetric setting per profile (RSS blk)*/</div><div class='ctx'> 	struct mutex prof_map_lock;	/* protect access to profiles list */</div><div class='ctx'> 	u8 *written;</div><div class='ctx'> 	u8 reverse; /* set to true to reverse FV order */</div><div class='hunk'>@@ -304,10 +305,16 @@ struct ice_masks {</div><div class='ctx'> 	struct ice_mask masks[ICE_PROF_MASK_COUNT];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct ice_prof_id {</div><div class='add'>+	unsigned long *id;</div><div class='add'>+	int count;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Tables per block */</div><div class='ctx'> struct ice_blk_info {</div><div class='ctx'> 	struct ice_xlt1 xlt1;</div><div class='ctx'> 	struct ice_xlt2 xlt2;</div><div class='add'>+	struct ice_prof_id prof_id;</div><div class='ctx'> 	struct ice_prof_tcam prof;</div><div class='ctx'> 	struct ice_prof_redir prof_redir;</div><div class='ctx'> 	struct ice_es es;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_flow.c b/drivers/net/ethernet/intel/ice/ice_flow.c<br/>index fb8b925aaf8b..fc2b58f56279 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flow.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_flow.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flow.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flow.c</a></div><div class='hunk'>@@ -1235,6 +1235,7 @@ ice_flow_proc_segs(struct ice_hw *hw, struct ice_flow_prof_params *params)</div><div class='ctx'> #define ICE_FLOW_FIND_PROF_CHK_FLDS	0x00000001</div><div class='ctx'> #define ICE_FLOW_FIND_PROF_CHK_VSI	0x00000002</div><div class='ctx'> #define ICE_FLOW_FIND_PROF_NOT_CHK_DIR	0x00000004</div><div class='add'>+#define ICE_FLOW_FIND_PROF_CHK_SYMM	0x00000008</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ice_flow_find_prof_conds - Find a profile matching headers and conditions</div><div class='hunk'>@@ -1243,13 +1244,14 @@ ice_flow_proc_segs(struct ice_hw *hw, struct ice_flow_prof_params *params)</div><div class='ctx'>  * @dir: flow direction</div><div class='ctx'>  * @segs: array of one or more packet segments that describe the flow</div><div class='ctx'>  * @segs_cnt: number of packet segments provided</div><div class='add'>+ * @symm: symmetric setting for RSS profiles</div><div class='ctx'>  * @vsi_handle: software VSI handle to check VSI (ICE_FLOW_FIND_PROF_CHK_VSI)</div><div class='ctx'>  * @conds: additional conditions to be checked (ICE_FLOW_FIND_PROF_CHK_*)</div><div class='ctx'>  */</div><div class='ctx'> static struct ice_flow_prof *</div><div class='ctx'> ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 			 enum ice_flow_dir dir, struct ice_flow_seg_info *segs,</div><div class='del'>-			 u8 segs_cnt, u16 vsi_handle, u32 conds)</div><div class='add'>+			 u8 segs_cnt, bool symm, u16 vsi_handle, u32 conds)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_flow_prof *p, *prof = NULL;</div><div class='ctx'> </div><div class='hunk'>@@ -1265,6 +1267,11 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 			    !test_bit(vsi_handle, p-&gt;vsis))</div><div class='ctx'> 				continue;</div><div class='ctx'> </div><div class='add'>+			/* Check for symmetric settings */</div><div class='add'>+			if ((conds &amp; ICE_FLOW_FIND_PROF_CHK_SYMM) &amp;&amp;</div><div class='add'>+			    p-&gt;symm != symm)</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='ctx'> 			/* Protocol headers must be checked. Matched fields are</div><div class='ctx'> 			 * checked if specified.</div><div class='ctx'> 			 */</div><div class='hunk'>@@ -1328,26 +1335,33 @@ ice_flow_rem_entry_sync(struct ice_hw *hw, enum ice_block __always_unused blk,</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @blk: classification stage</div><div class='ctx'>  * @dir: flow direction</div><div class='del'>- * @prof_id: unique ID to identify this flow profile</div><div class='ctx'>  * @segs: array of one or more packet segments that describe the flow</div><div class='ctx'>  * @segs_cnt: number of packet segments provided</div><div class='add'>+ * @symm: symmetric setting for RSS profiles</div><div class='ctx'>  * @prof: stores the returned flow profile added</div><div class='ctx'>  *</div><div class='ctx'>  * Assumption: the caller has acquired the lock to the profile list</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='ctx'> ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,</div><div class='del'>-		       enum ice_flow_dir dir, u64 prof_id,</div><div class='add'>+		       enum ice_flow_dir dir,</div><div class='ctx'> 		       struct ice_flow_seg_info *segs, u8 segs_cnt,</div><div class='del'>-		       struct ice_flow_prof **prof)</div><div class='add'>+		       bool symm, struct ice_flow_prof **prof)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_flow_prof_params *params;</div><div class='add'>+	struct ice_prof_id *ids;</div><div class='ctx'> 	int status;</div><div class='add'>+	u64 prof_id;</div><div class='ctx'> 	u8 i;</div><div class='ctx'> </div><div class='ctx'> 	if (!prof)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	ids = &amp;hw-&gt;blk[blk].prof_id;</div><div class='add'>+	prof_id = find_first_zero_bit(ids-&gt;id, ids-&gt;count);</div><div class='add'>+	if (prof_id &gt;= ids-&gt;count)</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+</div><div class='ctx'> 	params = kzalloc(sizeof(*params), GFP_KERNEL);</div><div class='ctx'> 	if (!params)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -1369,6 +1383,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 	params-&gt;prof-&gt;id = prof_id;</div><div class='ctx'> 	params-&gt;prof-&gt;dir = dir;</div><div class='ctx'> 	params-&gt;prof-&gt;segs_cnt = segs_cnt;</div><div class='add'>+	params-&gt;prof-&gt;symm = symm;</div><div class='ctx'> </div><div class='ctx'> 	/* Make a copy of the segments that need to be persistent in the flow</div><div class='ctx'> 	 * profile instance</div><div class='hunk'>@@ -1385,7 +1400,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 	/* Add a HW profile for this flow profile */</div><div class='ctx'> 	status = ice_add_prof(hw, blk, prof_id, (u8 *)params-&gt;ptypes,</div><div class='ctx'> 			      params-&gt;attr, params-&gt;attr_cnt, params-&gt;es,</div><div class='del'>-			      params-&gt;mask);</div><div class='add'>+			      params-&gt;mask, symm);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n");</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1393,6 +1408,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> </div><div class='ctx'> 	INIT_LIST_HEAD(&amp;params-&gt;prof-&gt;entries);</div><div class='ctx'> 	mutex_init(&amp;params-&gt;prof-&gt;entries_lock);</div><div class='add'>+	set_bit(prof_id, ids-&gt;id);</div><div class='ctx'> 	*prof = params-&gt;prof;</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -1436,6 +1452,7 @@ ice_flow_rem_prof_sync(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'> 	/* Remove all hardware profiles associated with this flow profile */</div><div class='ctx'> 	status = ice_rem_prof(hw, blk, prof-&gt;id);</div><div class='ctx'> 	if (!status) {</div><div class='add'>+		clear_bit(prof-&gt;id, hw-&gt;blk[blk].prof_id.id);</div><div class='ctx'> 		list_del(&amp;prof-&gt;l_entry);</div><div class='ctx'> 		mutex_destroy(&amp;prof-&gt;entries_lock);</div><div class='ctx'> 		devm_kfree(ice_hw_to_dev(hw), prof);</div><div class='hunk'>@@ -1511,15 +1528,15 @@ ice_flow_disassoc_prof(struct ice_hw *hw, enum ice_block blk,</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @blk: classification stage</div><div class='ctx'>  * @dir: flow direction</div><div class='del'>- * @prof_id: unique ID to identify this flow profile</div><div class='ctx'>  * @segs: array of one or more packet segments that describe the flow</div><div class='ctx'>  * @segs_cnt: number of packet segments provided</div><div class='add'>+ * @symm: symmetric setting for RSS profiles</div><div class='ctx'>  * @prof: stores the returned flow profile added</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='ctx'> ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,</div><div class='del'>-		  u64 prof_id, struct ice_flow_seg_info *segs, u8 segs_cnt,</div><div class='del'>-		  struct ice_flow_prof **prof)</div><div class='add'>+		  struct ice_flow_seg_info *segs, u8 segs_cnt,</div><div class='add'>+		  bool symm, struct ice_flow_prof **prof)</div><div class='ctx'> {</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='hunk'>@@ -1538,8 +1555,8 @@ ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;fl_profs_locks[blk]);</div><div class='ctx'> </div><div class='del'>-	status = ice_flow_add_prof_sync(hw, blk, dir, prof_id, segs, segs_cnt,</div><div class='del'>-					prof);</div><div class='add'>+	status = ice_flow_add_prof_sync(hw, blk, dir, segs, segs_cnt,</div><div class='add'>+					symm, prof);</div><div class='ctx'> 	if (!status)</div><div class='ctx'> 		list_add(&amp;(*prof)-&gt;l_entry, &amp;hw-&gt;fl_profs[blk]);</div><div class='ctx'> </div><div class='hunk'>@@ -1855,37 +1872,49 @@ int ice_flow_rem_vsi_prof(struct ice_hw *hw, u16 vsi_handle, u64 prof_id)</div><div class='ctx'> /**</div><div class='ctx'>  * ice_flow_set_rss_seg_info - setup packet segments for RSS</div><div class='ctx'>  * @segs: pointer to the flow field segment(s)</div><div class='del'>- * @hash_fields: fields to be hashed on for the segment(s)</div><div class='del'>- * @flow_hdr: protocol header fields within a packet segment</div><div class='add'>+ * @seg_cnt: segment count</div><div class='add'>+ * @cfg: configure parameters</div><div class='ctx'>  *</div><div class='ctx'>  * Helper function to extract fields from hash bitmap and use flow</div><div class='ctx'>  * header value to set flow field segment for further use in flow</div><div class='ctx'>  * profile entry or removal.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u64 hash_fields,</div><div class='del'>-			  u32 flow_hdr)</div><div class='add'>+ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u8 seg_cnt,</div><div class='add'>+			  const struct ice_rss_hash_cfg *cfg)</div><div class='ctx'> {</div><div class='add'>+	struct ice_flow_seg_info *seg;</div><div class='ctx'> 	u64 val;</div><div class='del'>-	u8 i;</div><div class='add'>+	u16 i;</div><div class='ctx'> </div><div class='del'>-	for_each_set_bit(i, (unsigned long *)&amp;hash_fields,</div><div class='del'>-			 ICE_FLOW_FIELD_IDX_MAX)</div><div class='del'>-		ice_flow_set_fld(segs, (enum ice_flow_field)i,</div><div class='add'>+	/* set inner most segment */</div><div class='add'>+	seg = &amp;segs[seg_cnt - 1];</div><div class='add'>+</div><div class='add'>+	for_each_set_bit(i, (const unsigned long *)&amp;cfg-&gt;hash_flds,</div><div class='add'>+			 (u16)ICE_FLOW_FIELD_IDX_MAX)</div><div class='add'>+		ice_flow_set_fld(seg, (enum ice_flow_field)i,</div><div class='ctx'> 				 ICE_FLOW_FLD_OFF_INVAL, ICE_FLOW_FLD_OFF_INVAL,</div><div class='ctx'> 				 ICE_FLOW_FLD_OFF_INVAL, false);</div><div class='ctx'> </div><div class='del'>-	ICE_FLOW_SET_HDRS(segs, flow_hdr);</div><div class='add'>+	ICE_FLOW_SET_HDRS(seg, cfg-&gt;addl_hdrs);</div><div class='add'>+</div><div class='add'>+	/* set outer most header */</div><div class='add'>+	if (cfg-&gt;hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV4)</div><div class='add'>+		segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV4 |</div><div class='add'>+						    ICE_FLOW_SEG_HDR_IPV_OTHER;</div><div class='add'>+	else if (cfg-&gt;hdr_type == ICE_RSS_INNER_HEADERS_W_OUTER_IPV6)</div><div class='add'>+		segs[ICE_RSS_OUTER_HEADERS].hdrs |= ICE_FLOW_SEG_HDR_IPV6 |</div><div class='add'>+						    ICE_FLOW_SEG_HDR_IPV_OTHER;</div><div class='ctx'> </div><div class='del'>-	if (segs-&gt;hdrs &amp; ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS &amp;</div><div class='add'>+	if (seg-&gt;hdrs &amp; ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS &amp;</div><div class='ctx'> 	    ~ICE_FLOW_RSS_HDRS_INNER_MASK &amp; ~ICE_FLOW_SEG_HDR_IPV_OTHER)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	val = (u64)(segs-&gt;hdrs &amp; ICE_FLOW_RSS_SEG_HDR_L3_MASKS);</div><div class='add'>+	val = (u64)(seg-&gt;hdrs &amp; ICE_FLOW_RSS_SEG_HDR_L3_MASKS);</div><div class='ctx'> 	if (val &amp;&amp; !is_power_of_2(val))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='del'>-	val = (u64)(segs-&gt;hdrs &amp; ICE_FLOW_RSS_SEG_HDR_L4_MASKS);</div><div class='add'>+	val = (u64)(seg-&gt;hdrs &amp; ICE_FLOW_RSS_SEG_HDR_L4_MASKS);</div><div class='ctx'> 	if (val &amp;&amp; !is_power_of_2(val))</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='hunk'>@@ -1956,6 +1985,39 @@ int ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_get_rss_hdr_type - get a RSS profile's header type</div><div class='add'>+ * @prof: RSS flow profile</div><div class='add'>+ */</div><div class='add'>+static enum ice_rss_cfg_hdr_type</div><div class='add'>+ice_get_rss_hdr_type(struct ice_flow_prof *prof)</div><div class='add'>+{</div><div class='add'>+	if (prof-&gt;segs_cnt == ICE_FLOW_SEG_SINGLE) {</div><div class='add'>+		return ICE_RSS_OUTER_HEADERS;</div><div class='add'>+	} else if (prof-&gt;segs_cnt == ICE_FLOW_SEG_MAX) {</div><div class='add'>+		const struct ice_flow_seg_info *s;</div><div class='add'>+</div><div class='add'>+		s = &amp;prof-&gt;segs[ICE_RSS_OUTER_HEADERS];</div><div class='add'>+		if (s-&gt;hdrs == ICE_FLOW_SEG_HDR_NONE)</div><div class='add'>+			return ICE_RSS_INNER_HEADERS;</div><div class='add'>+		if (s-&gt;hdrs &amp; ICE_FLOW_SEG_HDR_IPV4)</div><div class='add'>+			return ICE_RSS_INNER_HEADERS_W_OUTER_IPV4;</div><div class='add'>+		if (s-&gt;hdrs &amp; ICE_FLOW_SEG_HDR_IPV6)</div><div class='add'>+			return ICE_RSS_INNER_HEADERS_W_OUTER_IPV6;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ICE_RSS_ANY_HEADERS;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool</div><div class='add'>+ice_rss_match_prof(struct ice_rss_cfg *r, struct ice_flow_prof *prof,</div><div class='add'>+		   enum ice_rss_cfg_hdr_type hdr_type)</div><div class='add'>+{</div><div class='add'>+	return (r-&gt;hash.hdr_type == hdr_type &amp;&amp;</div><div class='add'>+		r-&gt;hash.hash_flds == prof-&gt;segs[prof-&gt;segs_cnt - 1].match &amp;&amp;</div><div class='add'>+		r-&gt;hash.addl_hdrs == prof-&gt;segs[prof-&gt;segs_cnt - 1].hdrs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_rem_rss_list - remove RSS configuration from list</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='ctx'>  * @vsi_handle: software VSI handle</div><div class='hunk'>@@ -1966,15 +2028,16 @@ int ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)</div><div class='ctx'> static void</div><div class='ctx'> ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)</div><div class='ctx'> {</div><div class='add'>+	enum ice_rss_cfg_hdr_type hdr_type;</div><div class='ctx'> 	struct ice_rss_cfg *r, *tmp;</div><div class='ctx'> </div><div class='ctx'> 	/* Search for RSS hash fields associated to the VSI that match the</div><div class='ctx'> 	 * hash configurations associated to the flow profile. If found</div><div class='ctx'> 	 * remove from the RSS entry list of the VSI context and delete entry.</div><div class='ctx'> 	 */</div><div class='add'>+	hdr_type = ice_get_rss_hdr_type(prof);</div><div class='ctx'> 	list_for_each_entry_safe(r, tmp, &amp;hw-&gt;rss_list_head, l_entry)</div><div class='del'>-		if (r-&gt;hashed_flds == prof-&gt;segs[prof-&gt;segs_cnt - 1].match &amp;&amp;</div><div class='del'>-		    r-&gt;packet_hdr == prof-&gt;segs[prof-&gt;segs_cnt - 1].hdrs) {</div><div class='add'>+		if (ice_rss_match_prof(r, prof, hdr_type)) {</div><div class='ctx'> 			clear_bit(vsi_handle, r-&gt;vsis);</div><div class='ctx'> 			if (bitmap_empty(r-&gt;vsis, ICE_MAX_VSI)) {</div><div class='ctx'> 				list_del(&amp;r-&gt;l_entry);</div><div class='hunk'>@@ -1995,11 +2058,12 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)</div><div class='ctx'> static int</div><div class='ctx'> ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)</div><div class='ctx'> {</div><div class='add'>+	enum ice_rss_cfg_hdr_type hdr_type;</div><div class='ctx'> 	struct ice_rss_cfg *r, *rss_cfg;</div><div class='ctx'> </div><div class='add'>+	hdr_type = ice_get_rss_hdr_type(prof);</div><div class='ctx'> 	list_for_each_entry(r, &amp;hw-&gt;rss_list_head, l_entry)</div><div class='del'>-		if (r-&gt;hashed_flds == prof-&gt;segs[prof-&gt;segs_cnt - 1].match &amp;&amp;</div><div class='del'>-		    r-&gt;packet_hdr == prof-&gt;segs[prof-&gt;segs_cnt - 1].hdrs) {</div><div class='add'>+		if (ice_rss_match_prof(r, prof, hdr_type)) {</div><div class='ctx'> 			set_bit(vsi_handle, r-&gt;vsis);</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2009,8 +2073,10 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)</div><div class='ctx'> 	if (!rss_cfg)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	rss_cfg-&gt;hashed_flds = prof-&gt;segs[prof-&gt;segs_cnt - 1].match;</div><div class='del'>-	rss_cfg-&gt;packet_hdr = prof-&gt;segs[prof-&gt;segs_cnt - 1].hdrs;</div><div class='add'>+	rss_cfg-&gt;hash.hash_flds = prof-&gt;segs[prof-&gt;segs_cnt - 1].match;</div><div class='add'>+	rss_cfg-&gt;hash.addl_hdrs = prof-&gt;segs[prof-&gt;segs_cnt - 1].hdrs;</div><div class='add'>+	rss_cfg-&gt;hash.hdr_type = hdr_type;</div><div class='add'>+	rss_cfg-&gt;hash.symm = prof-&gt;symm;</div><div class='ctx'> 	set_bit(vsi_handle, rss_cfg-&gt;vsis);</div><div class='ctx'> </div><div class='ctx'> 	list_add_tail(&amp;rss_cfg-&gt;l_entry, &amp;hw-&gt;rss_list_head);</div><div class='hunk'>@@ -2018,65 +2084,177 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define ICE_FLOW_PROF_HASH_S	0</div><div class='del'>-#define ICE_FLOW_PROF_HASH_M	(0xFFFFFFFFULL &lt;&lt; ICE_FLOW_PROF_HASH_S)</div><div class='del'>-#define ICE_FLOW_PROF_HDR_S	32</div><div class='del'>-#define ICE_FLOW_PROF_HDR_M	(0x3FFFFFFFULL &lt;&lt; ICE_FLOW_PROF_HDR_S)</div><div class='del'>-#define ICE_FLOW_PROF_ENCAP_S	63</div><div class='del'>-#define ICE_FLOW_PROF_ENCAP_M	(BIT_ULL(ICE_FLOW_PROF_ENCAP_S))</div><div class='add'>+/**</div><div class='add'>+ * ice_rss_config_xor_word - set the HSYMM registers for one input set word</div><div class='add'>+ * @hw: pointer to the hardware structure</div><div class='add'>+ * @prof_id: RSS hardware profile id</div><div class='add'>+ * @src: the FV index used by the protocol's source field</div><div class='add'>+ * @dst: the FV index used by the protocol's destination field</div><div class='add'>+ *</div><div class='add'>+ * Write to the HSYMM register with the index of @src FV the value of the @dst</div><div class='add'>+ * FV index. This will tell the hardware to XOR HSYMM[src] with INSET[dst]</div><div class='add'>+ * while calculating the RSS input set.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_rss_config_xor_word(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst)</div><div class='add'>+{</div><div class='add'>+	u32 val, reg, bits_shift;</div><div class='add'>+	u8 reg_idx;</div><div class='add'>+</div><div class='add'>+	reg_idx = src / GLQF_HSYMM_REG_SIZE;</div><div class='add'>+	bits_shift = ((src % GLQF_HSYMM_REG_SIZE) &lt;&lt; 3);</div><div class='add'>+	val = dst | GLQF_HSYMM_ENABLE_BIT;</div><div class='add'>+</div><div class='add'>+	reg = rd32(hw, GLQF_HSYMM(prof_id, reg_idx));</div><div class='add'>+	reg = (reg &amp; ~(0xff &lt;&lt; bits_shift)) | (val &lt;&lt; bits_shift);</div><div class='add'>+	wr32(hw, GLQF_HSYMM(prof_id, reg_idx), reg);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-#define ICE_RSS_OUTER_HEADERS	1</div><div class='del'>-#define ICE_RSS_INNER_HEADERS	2</div><div class='add'>+/**</div><div class='add'>+ * ice_rss_config_xor - set the symmetric registers for a profile's protocol</div><div class='add'>+ * @hw: pointer to the hardware structure</div><div class='add'>+ * @prof_id: RSS hardware profile id</div><div class='add'>+ * @src: the FV index used by the protocol's source field</div><div class='add'>+ * @dst: the FV index used by the protocol's destination field</div><div class='add'>+ * @len: length of the source/destination fields in words</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_rss_config_xor(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst, u8 len)</div><div class='add'>+{</div><div class='add'>+	int fv_last_word =</div><div class='add'>+		ICE_FLOW_SW_FIELD_VECTOR_MAX / ICE_FLOW_FV_EXTRACT_SZ - 1;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; len; i++) {</div><div class='add'>+		ice_rss_config_xor_word(hw, prof_id,</div><div class='add'>+					/* Yes, field vector in GLQF_HSYMM and</div><div class='add'>+					 * GLQF_HINSET is inversed!</div><div class='add'>+					 */</div><div class='add'>+					fv_last_word - (src + i),</div><div class='add'>+					fv_last_word - (dst + i));</div><div class='add'>+		ice_rss_config_xor_word(hw, prof_id,</div><div class='add'>+					fv_last_word - (dst + i),</div><div class='add'>+					fv_last_word - (src + i));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-/* Flow profile ID format:</div><div class='del'>- * [0:31] - Packet match fields</div><div class='del'>- * [32:62] - Protocol header</div><div class='del'>- * [63] - Encapsulation flag, 0 if non-tunneled, 1 if tunneled</div><div class='add'>+/**</div><div class='add'>+ * ice_rss_set_symm - set the symmetric settings for an RSS profile</div><div class='add'>+ * @hw: pointer to the hardware structure</div><div class='add'>+ * @prof: pointer to flow profile</div><div class='add'>+ *</div><div class='add'>+ * The symmetric hash will result from XORing the protocol's fields with</div><div class='add'>+ * indexes in GLQF_HSYMM and GLQF_HINSET. This function configures the profile's</div><div class='add'>+ * GLQF_HSYMM registers.</div><div class='ctx'>  */</div><div class='del'>-#define ICE_FLOW_GEN_PROFID(hash, hdr, segs_cnt) \</div><div class='del'>-	((u64)(((u64)(hash) &amp; ICE_FLOW_PROF_HASH_M) | \</div><div class='del'>-	       (((u64)(hdr) &lt;&lt; ICE_FLOW_PROF_HDR_S) &amp; ICE_FLOW_PROF_HDR_M) | \</div><div class='del'>-	       ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0)))</div><div class='add'>+static void ice_rss_set_symm(struct ice_hw *hw, struct ice_flow_prof *prof)</div><div class='add'>+{</div><div class='add'>+	struct ice_prof_map *map;</div><div class='add'>+	u8 prof_id, m;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hw-&gt;blk[ICE_BLK_RSS].es.prof_map_lock);</div><div class='add'>+	map = ice_search_prof_id(hw, ICE_BLK_RSS, prof-&gt;id);</div><div class='add'>+	if (map)</div><div class='add'>+		prof_id = map-&gt;prof_id;</div><div class='add'>+	mutex_unlock(&amp;hw-&gt;blk[ICE_BLK_RSS].es.prof_map_lock);</div><div class='add'>+</div><div class='add'>+	if (!map)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* clear to default */</div><div class='add'>+	for (m = 0; m &lt; GLQF_HSYMM_REG_PER_PROF; m++)</div><div class='add'>+		wr32(hw, GLQF_HSYMM(prof_id, m), 0);</div><div class='add'>+</div><div class='add'>+	if (prof-&gt;symm) {</div><div class='add'>+		struct ice_flow_seg_xtrct *ipv4_src, *ipv4_dst;</div><div class='add'>+		struct ice_flow_seg_xtrct *ipv6_src, *ipv6_dst;</div><div class='add'>+		struct ice_flow_seg_xtrct *sctp_src, *sctp_dst;</div><div class='add'>+		struct ice_flow_seg_xtrct *tcp_src, *tcp_dst;</div><div class='add'>+		struct ice_flow_seg_xtrct *udp_src, *udp_dst;</div><div class='add'>+		struct ice_flow_seg_info *seg;</div><div class='add'>+</div><div class='add'>+		seg = &amp;prof-&gt;segs[prof-&gt;segs_cnt - 1];</div><div class='add'>+</div><div class='add'>+		ipv4_src = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_IPV4_SA].xtrct;</div><div class='add'>+		ipv4_dst = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_IPV4_DA].xtrct;</div><div class='add'>+</div><div class='add'>+		ipv6_src = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_IPV6_SA].xtrct;</div><div class='add'>+		ipv6_dst = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_IPV6_DA].xtrct;</div><div class='add'>+</div><div class='add'>+		tcp_src = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_TCP_SRC_PORT].xtrct;</div><div class='add'>+		tcp_dst = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_TCP_DST_PORT].xtrct;</div><div class='add'>+</div><div class='add'>+		udp_src = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_UDP_SRC_PORT].xtrct;</div><div class='add'>+		udp_dst = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_UDP_DST_PORT].xtrct;</div><div class='add'>+</div><div class='add'>+		sctp_src = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT].xtrct;</div><div class='add'>+		sctp_dst = &amp;seg-&gt;fields[ICE_FLOW_FIELD_IDX_SCTP_DST_PORT].xtrct;</div><div class='add'>+</div><div class='add'>+		/* xor IPv4 */</div><div class='add'>+		if (ipv4_src-&gt;prot_id != 0 &amp;&amp; ipv4_dst-&gt;prot_id != 0)</div><div class='add'>+			ice_rss_config_xor(hw, prof_id,</div><div class='add'>+					   ipv4_src-&gt;idx, ipv4_dst-&gt;idx, 2);</div><div class='add'>+</div><div class='add'>+		/* xor IPv6 */</div><div class='add'>+		if (ipv6_src-&gt;prot_id != 0 &amp;&amp; ipv6_dst-&gt;prot_id != 0)</div><div class='add'>+			ice_rss_config_xor(hw, prof_id,</div><div class='add'>+					   ipv6_src-&gt;idx, ipv6_dst-&gt;idx, 8);</div><div class='add'>+</div><div class='add'>+		/* xor TCP */</div><div class='add'>+		if (tcp_src-&gt;prot_id != 0 &amp;&amp; tcp_dst-&gt;prot_id != 0)</div><div class='add'>+			ice_rss_config_xor(hw, prof_id,</div><div class='add'>+					   tcp_src-&gt;idx, tcp_dst-&gt;idx, 1);</div><div class='add'>+</div><div class='add'>+		/* xor UDP */</div><div class='add'>+		if (udp_src-&gt;prot_id != 0 &amp;&amp; udp_dst-&gt;prot_id != 0)</div><div class='add'>+			ice_rss_config_xor(hw, prof_id,</div><div class='add'>+					   udp_src-&gt;idx, udp_dst-&gt;idx, 1);</div><div class='add'>+</div><div class='add'>+		/* xor SCTP */</div><div class='add'>+		if (sctp_src-&gt;prot_id != 0 &amp;&amp; sctp_dst-&gt;prot_id != 0)</div><div class='add'>+			ice_rss_config_xor(hw, prof_id,</div><div class='add'>+					   sctp_src-&gt;idx, sctp_dst-&gt;idx, 1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ice_add_rss_cfg_sync - add an RSS configuration</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='ctx'>  * @vsi_handle: software VSI handle</div><div class='del'>- * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure</div><div class='del'>- * @addl_hdrs: protocol header fields</div><div class='del'>- * @segs_cnt: packet segment count</div><div class='add'>+ * @cfg: configure parameters</div><div class='ctx'>  *</div><div class='ctx'>  * Assumption: lock has already been acquired for RSS list</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		     u32 addl_hdrs, u8 segs_cnt)</div><div class='add'>+ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle,</div><div class='add'>+		     const struct ice_rss_hash_cfg *cfg)</div><div class='ctx'> {</div><div class='ctx'> 	const enum ice_block blk = ICE_BLK_RSS;</div><div class='ctx'> 	struct ice_flow_prof *prof = NULL;</div><div class='ctx'> 	struct ice_flow_seg_info *segs;</div><div class='add'>+	u8 segs_cnt;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='del'>-	if (!segs_cnt || segs_cnt &gt; ICE_FLOW_SEG_MAX)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	segs_cnt = (cfg-&gt;hdr_type == ICE_RSS_OUTER_HEADERS) ?</div><div class='add'>+			ICE_FLOW_SEG_SINGLE : ICE_FLOW_SEG_MAX;</div><div class='ctx'> </div><div class='ctx'> 	segs = kcalloc(segs_cnt, sizeof(*segs), GFP_KERNEL);</div><div class='ctx'> 	if (!segs)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/* Construct the packet segment info from the hashed fields */</div><div class='del'>-	status = ice_flow_set_rss_seg_info(&amp;segs[segs_cnt - 1], hashed_flds,</div><div class='del'>-					   addl_hdrs);</div><div class='add'>+	status = ice_flow_set_rss_seg_info(segs, segs_cnt, cfg);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> </div><div class='del'>-	/* Search for a flow profile that has matching headers, hash fields</div><div class='del'>-	 * and has the input VSI associated to it. If found, no further</div><div class='add'>+	/* Search for a flow profile that has matching headers, hash fields,</div><div class='add'>+	 * symm and has the input VSI associated to it. If found, no further</div><div class='ctx'> 	 * operations required and exit.</div><div class='ctx'> 	 */</div><div class='ctx'> 	prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,</div><div class='del'>-					vsi_handle,</div><div class='add'>+					cfg-&gt;symm, vsi_handle,</div><div class='ctx'> 					ICE_FLOW_FIND_PROF_CHK_FLDS |</div><div class='add'>+					ICE_FLOW_FIND_PROF_CHK_SYMM |</div><div class='ctx'> 					ICE_FLOW_FIND_PROF_CHK_VSI);</div><div class='ctx'> 	if (prof)</div><div class='ctx'> 		goto exit;</div><div class='hunk'>@@ -2087,7 +2265,8 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='ctx'> 	 * the protocol header and new hash field configuration.</div><div class='ctx'> 	 */</div><div class='ctx'> 	prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,</div><div class='del'>-					vsi_handle, ICE_FLOW_FIND_PROF_CHK_VSI);</div><div class='add'>+					cfg-&gt;symm, vsi_handle,</div><div class='add'>+					ICE_FLOW_FIND_PROF_CHK_VSI);</div><div class='ctx'> 	if (prof) {</div><div class='ctx'> 		status = ice_flow_disassoc_prof(hw, blk, prof, vsi_handle);</div><div class='ctx'> 		if (!status)</div><div class='hunk'>@@ -2103,11 +2282,12 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Search for a profile that has same match fields only. If this</div><div class='del'>-	 * exists then associate the VSI to this profile.</div><div class='add'>+	/* Search for a profile that has the same match fields and symmetric</div><div class='add'>+	 * setting. If this exists then associate the VSI to this profile.</div><div class='ctx'> 	 */</div><div class='ctx'> 	prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,</div><div class='del'>-					vsi_handle,</div><div class='add'>+					cfg-&gt;symm, vsi_handle,</div><div class='add'>+					ICE_FLOW_FIND_PROF_CHK_SYMM |</div><div class='ctx'> 					ICE_FLOW_FIND_PROF_CHK_FLDS);</div><div class='ctx'> 	if (prof) {</div><div class='ctx'> 		status = ice_flow_assoc_prof(hw, blk, prof, vsi_handle);</div><div class='hunk'>@@ -2116,17 +2296,14 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='ctx'> 		goto exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Create a new flow profile with generated profile and packet</div><div class='del'>-	 * segment information.</div><div class='del'>-	 */</div><div class='add'>+	/* Create a new flow profile with packet segment information. */</div><div class='ctx'> 	status = ice_flow_add_prof(hw, blk, ICE_FLOW_RX,</div><div class='del'>-				   ICE_FLOW_GEN_PROFID(hashed_flds,</div><div class='del'>-						       segs[segs_cnt - 1].hdrs,</div><div class='del'>-						       segs_cnt),</div><div class='del'>-				   segs, segs_cnt, &amp;prof);</div><div class='add'>+				   segs, segs_cnt, cfg-&gt;symm, &amp;prof);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> </div><div class='add'>+	prof-&gt;symm = cfg-&gt;symm;</div><div class='add'>+	ice_rss_set_symm(hw, prof);</div><div class='ctx'> 	status = ice_flow_assoc_prof(hw, blk, prof, vsi_handle);</div><div class='ctx'> 	/* If association to a new flow profile failed then this profile can</div><div class='ctx'> 	 * be removed.</div><div class='hunk'>@@ -2146,30 +2323,43 @@ exit:</div><div class='ctx'> /**</div><div class='ctx'>  * ice_add_rss_cfg - add an RSS configuration with specified hashed fields</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='del'>- * @vsi_handle: software VSI handle</div><div class='del'>- * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure</div><div class='del'>- * @addl_hdrs: protocol header fields</div><div class='add'>+ * @vsi: VSI to add the RSS configuration to</div><div class='add'>+ * @cfg: configure parameters</div><div class='ctx'>  *</div><div class='ctx'>  * This function will generate a flow profile based on fields associated with</div><div class='ctx'>  * the input fields to hash on, the flow type and use the VSI number to add</div><div class='ctx'>  * a flow entry to the profile.</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='del'>-ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		u32 addl_hdrs)</div><div class='add'>+ice_add_rss_cfg(struct ice_hw *hw, struct ice_vsi *vsi,</div><div class='add'>+		const struct ice_rss_hash_cfg *cfg)</div><div class='ctx'> {</div><div class='add'>+	struct ice_rss_hash_cfg local_cfg;</div><div class='add'>+	u16 vsi_handle;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='del'>-	if (hashed_flds == ICE_HASH_INVALID ||</div><div class='del'>-	    !ice_is_vsi_valid(hw, vsi_handle))</div><div class='add'>+	if (!vsi)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vsi_handle = vsi-&gt;idx;</div><div class='add'>+	if (!ice_is_vsi_valid(hw, vsi_handle) ||</div><div class='add'>+	    !cfg || cfg-&gt;hdr_type &gt; ICE_RSS_ANY_HEADERS ||</div><div class='add'>+	    cfg-&gt;hash_flds == ICE_HASH_INVALID)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;rss_locks);</div><div class='del'>-	status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,</div><div class='del'>-				      ICE_RSS_OUTER_HEADERS);</div><div class='del'>-	if (!status)</div><div class='del'>-		status = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,</div><div class='del'>-					      addl_hdrs, ICE_RSS_INNER_HEADERS);</div><div class='add'>+	local_cfg = *cfg;</div><div class='add'>+	if (cfg-&gt;hdr_type &lt; ICE_RSS_ANY_HEADERS) {</div><div class='add'>+		status = ice_add_rss_cfg_sync(hw, vsi_handle, &amp;local_cfg);</div><div class='add'>+	} else {</div><div class='add'>+		local_cfg.hdr_type = ICE_RSS_OUTER_HEADERS;</div><div class='add'>+		status = ice_add_rss_cfg_sync(hw, vsi_handle, &amp;local_cfg);</div><div class='add'>+		if (!status) {</div><div class='add'>+			local_cfg.hdr_type = ICE_RSS_INNER_HEADERS;</div><div class='add'>+			status = ice_add_rss_cfg_sync(hw, vsi_handle,</div><div class='add'>+						      &amp;local_cfg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	mutex_unlock(&amp;hw-&gt;rss_locks);</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -2179,33 +2369,33 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='ctx'>  * ice_rem_rss_cfg_sync - remove an existing RSS configuration</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='ctx'>  * @vsi_handle: software VSI handle</div><div class='del'>- * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove</div><div class='del'>- * @addl_hdrs: Protocol header fields within a packet segment</div><div class='del'>- * @segs_cnt: packet segment count</div><div class='add'>+ * @cfg: configure parameters</div><div class='ctx'>  *</div><div class='ctx'>  * Assumption: lock has already been acquired for RSS list</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		     u32 addl_hdrs, u8 segs_cnt)</div><div class='add'>+ice_rem_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle,</div><div class='add'>+		     const struct ice_rss_hash_cfg *cfg)</div><div class='ctx'> {</div><div class='ctx'> 	const enum ice_block blk = ICE_BLK_RSS;</div><div class='ctx'> 	struct ice_flow_seg_info *segs;</div><div class='ctx'> 	struct ice_flow_prof *prof;</div><div class='add'>+	u8 segs_cnt;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='add'>+	segs_cnt = (cfg-&gt;hdr_type == ICE_RSS_OUTER_HEADERS) ?</div><div class='add'>+			ICE_FLOW_SEG_SINGLE : ICE_FLOW_SEG_MAX;</div><div class='ctx'> 	segs = kcalloc(segs_cnt, sizeof(*segs), GFP_KERNEL);</div><div class='ctx'> 	if (!segs)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	/* Construct the packet segment info from the hashed fields */</div><div class='del'>-	status = ice_flow_set_rss_seg_info(&amp;segs[segs_cnt - 1], hashed_flds,</div><div class='del'>-					   addl_hdrs);</div><div class='add'>+	status = ice_flow_set_rss_seg_info(segs, segs_cnt, cfg);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='ctx'> 	prof = ice_flow_find_prof_conds(hw, blk, ICE_FLOW_RX, segs, segs_cnt,</div><div class='del'>-					vsi_handle,</div><div class='add'>+					cfg-&gt;symm, vsi_handle,</div><div class='ctx'> 					ICE_FLOW_FIND_PROF_CHK_FLDS);</div><div class='ctx'> 	if (!prof) {</div><div class='ctx'> 		status = -ENOENT;</div><div class='hunk'>@@ -2233,31 +2423,39 @@ out:</div><div class='ctx'>  * ice_rem_rss_cfg - remove an existing RSS config with matching hashed fields</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='ctx'>  * @vsi_handle: software VSI handle</div><div class='del'>- * @hashed_flds: Packet hash types (ICE_FLOW_HASH_*) to remove</div><div class='del'>- * @addl_hdrs: Protocol header fields within a packet segment</div><div class='add'>+ * @cfg: configure parameters</div><div class='ctx'>  *</div><div class='ctx'>  * This function will lookup the flow profile based on the input</div><div class='ctx'>  * hash field bitmap, iterate through the profile entry list of</div><div class='ctx'>  * that profile and find entry associated with input VSI to be</div><div class='del'>- * removed. Calls are made to underlying flow s which will APIs</div><div class='add'>+ * removed. Calls are made to underlying flow apis which will in</div><div class='ctx'>  * turn build or update buffers for RSS XLT1 section.</div><div class='ctx'>  */</div><div class='del'>-int __maybe_unused</div><div class='del'>-ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		u32 addl_hdrs)</div><div class='add'>+int</div><div class='add'>+ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle,</div><div class='add'>+		const struct ice_rss_hash_cfg *cfg)</div><div class='ctx'> {</div><div class='add'>+	struct ice_rss_hash_cfg local_cfg;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='del'>-	if (hashed_flds == ICE_HASH_INVALID ||</div><div class='del'>-	    !ice_is_vsi_valid(hw, vsi_handle))</div><div class='add'>+	if (!ice_is_vsi_valid(hw, vsi_handle) ||</div><div class='add'>+	    !cfg || cfg-&gt;hdr_type &gt; ICE_RSS_ANY_HEADERS ||</div><div class='add'>+	    cfg-&gt;hash_flds == ICE_HASH_INVALID)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;rss_locks);</div><div class='del'>-	status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,</div><div class='del'>-				      ICE_RSS_OUTER_HEADERS);</div><div class='del'>-	if (!status)</div><div class='del'>-		status = ice_rem_rss_cfg_sync(hw, vsi_handle, hashed_flds,</div><div class='del'>-					      addl_hdrs, ICE_RSS_INNER_HEADERS);</div><div class='add'>+	local_cfg = *cfg;</div><div class='add'>+	if (cfg-&gt;hdr_type &lt; ICE_RSS_ANY_HEADERS) {</div><div class='add'>+		status = ice_rem_rss_cfg_sync(hw, vsi_handle, &amp;local_cfg);</div><div class='add'>+	} else {</div><div class='add'>+		local_cfg.hdr_type = ICE_RSS_OUTER_HEADERS;</div><div class='add'>+		status = ice_rem_rss_cfg_sync(hw, vsi_handle, &amp;local_cfg);</div><div class='add'>+		if (!status) {</div><div class='add'>+			local_cfg.hdr_type = ICE_RSS_INNER_HEADERS;</div><div class='add'>+			status = ice_rem_rss_cfg_sync(hw, vsi_handle,</div><div class='add'>+						      &amp;local_cfg);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> 	mutex_unlock(&amp;hw-&gt;rss_locks);</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -2298,18 +2496,24 @@ ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='ctx'> /**</div><div class='ctx'>  * ice_add_avf_rss_cfg - add an RSS configuration for AVF driver</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='del'>- * @vsi_handle: software VSI handle</div><div class='add'>+ * @vsi: VF's VSI</div><div class='ctx'>  * @avf_hash: hash bit fields (ICE_AVF_FLOW_FIELD_*) to configure</div><div class='ctx'>  *</div><div class='ctx'>  * This function will take the hash bitmap provided by the AVF driver via a</div><div class='ctx'>  * message, convert it to ICE-compatible values, and configure RSS flow</div><div class='ctx'>  * profiles.</div><div class='ctx'>  */</div><div class='del'>-int ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)</div><div class='add'>+int ice_add_avf_rss_cfg(struct ice_hw *hw, struct ice_vsi *vsi, u64 avf_hash)</div><div class='ctx'> {</div><div class='add'>+	struct ice_rss_hash_cfg hcfg;</div><div class='add'>+	u16 vsi_handle;</div><div class='ctx'> 	int status = 0;</div><div class='ctx'> 	u64 hash_flds;</div><div class='ctx'> </div><div class='add'>+	if (!vsi)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	vsi_handle = vsi-&gt;idx;</div><div class='ctx'> 	if (avf_hash == ICE_AVF_FLOW_FIELD_INVALID ||</div><div class='ctx'> 	    !ice_is_vsi_valid(hw, vsi_handle))</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -2379,8 +2583,11 @@ int ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)</div><div class='ctx'> 		if (rss_hash == ICE_HASH_INVALID)</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> </div><div class='del'>-		status = ice_add_rss_cfg(hw, vsi_handle, rss_hash,</div><div class='del'>-					 ICE_FLOW_SEG_HDR_NONE);</div><div class='add'>+		hcfg.addl_hdrs = ICE_FLOW_SEG_HDR_NONE;</div><div class='add'>+		hcfg.hash_flds = rss_hash;</div><div class='add'>+		hcfg.hdr_type = ICE_RSS_ANY_HEADERS;</div><div class='add'>+		hcfg.symm = false;</div><div class='add'>+		status = ice_add_rss_cfg(hw, vsi, &amp;hcfg);</div><div class='ctx'> 		if (status)</div><div class='ctx'> 			break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2388,6 +2595,54 @@ int ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 avf_hash)</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool rss_cfg_symm_valid(u64 hfld)</div><div class='add'>+{</div><div class='add'>+	return !((!!(hfld &amp; ICE_FLOW_HASH_FLD_IPV4_SA) ^</div><div class='add'>+		  !!(hfld &amp; ICE_FLOW_HASH_FLD_IPV4_DA)) ||</div><div class='add'>+		 (!!(hfld &amp; ICE_FLOW_HASH_FLD_IPV6_SA) ^</div><div class='add'>+		  !!(hfld &amp; ICE_FLOW_HASH_FLD_IPV6_DA)) ||</div><div class='add'>+		 (!!(hfld &amp; ICE_FLOW_HASH_FLD_TCP_SRC_PORT) ^</div><div class='add'>+		  !!(hfld &amp; ICE_FLOW_HASH_FLD_TCP_DST_PORT)) ||</div><div class='add'>+		 (!!(hfld &amp; ICE_FLOW_HASH_FLD_UDP_SRC_PORT) ^</div><div class='add'>+		  !!(hfld &amp; ICE_FLOW_HASH_FLD_UDP_DST_PORT)) ||</div><div class='add'>+		 (!!(hfld &amp; ICE_FLOW_HASH_FLD_SCTP_SRC_PORT) ^</div><div class='add'>+		  !!(hfld &amp; ICE_FLOW_HASH_FLD_SCTP_DST_PORT)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_set_rss_cfg_symm - set symmtery for all VSI's RSS configurations</div><div class='add'>+ * @hw: pointer to the hardware structure</div><div class='add'>+ * @vsi: VSI to set/unset Symmetric RSS</div><div class='add'>+ * @symm: TRUE to set Symmetric RSS hashing</div><div class='add'>+ */</div><div class='add'>+int ice_set_rss_cfg_symm(struct ice_hw *hw, struct ice_vsi *vsi, bool symm)</div><div class='add'>+{</div><div class='add'>+	struct ice_rss_hash_cfg	local;</div><div class='add'>+	struct ice_rss_cfg *r, *tmp;</div><div class='add'>+	u16 vsi_handle = vsi-&gt;idx;</div><div class='add'>+	int status = 0;</div><div class='add'>+</div><div class='add'>+	if (!ice_is_vsi_valid(hw, vsi_handle))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;hw-&gt;rss_locks);</div><div class='add'>+	list_for_each_entry_safe(r, tmp, &amp;hw-&gt;rss_list_head, l_entry) {</div><div class='add'>+		if (test_bit(vsi_handle, r-&gt;vsis) &amp;&amp; r-&gt;hash.symm != symm) {</div><div class='add'>+			local = r-&gt;hash;</div><div class='add'>+			local.symm = symm;</div><div class='add'>+			if (symm &amp;&amp; !rss_cfg_symm_valid(r-&gt;hash.hash_flds))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			status = ice_add_rss_cfg_sync(hw, vsi_handle, &amp;local);</div><div class='add'>+			if (status)</div><div class='add'>+				break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;hw-&gt;rss_locks);</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ice_replay_rss_cfg - replay RSS configurations associated with VSI</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='hunk'>@@ -2404,16 +2659,7 @@ int ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle)</div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;rss_locks);</div><div class='ctx'> 	list_for_each_entry(r, &amp;hw-&gt;rss_list_head, l_entry) {</div><div class='ctx'> 		if (test_bit(vsi_handle, r-&gt;vsis)) {</div><div class='del'>-			status = ice_add_rss_cfg_sync(hw, vsi_handle,</div><div class='del'>-						      r-&gt;hashed_flds,</div><div class='del'>-						      r-&gt;packet_hdr,</div><div class='del'>-						      ICE_RSS_OUTER_HEADERS);</div><div class='del'>-			if (status)</div><div class='del'>-				break;</div><div class='del'>-			status = ice_add_rss_cfg_sync(hw, vsi_handle,</div><div class='del'>-						      r-&gt;hashed_flds,</div><div class='del'>-						      r-&gt;packet_hdr,</div><div class='del'>-						      ICE_RSS_INNER_HEADERS);</div><div class='add'>+			status = ice_add_rss_cfg_sync(hw, vsi_handle, &amp;r-&gt;hash);</div><div class='ctx'> 			if (status)</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2428,11 +2674,12 @@ int ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle)</div><div class='ctx'>  * @hw: pointer to the hardware structure</div><div class='ctx'>  * @vsi_handle: software VSI handle</div><div class='ctx'>  * @hdrs: protocol header type</div><div class='add'>+ * @symm: whether the RSS is symmetric (bool, output)</div><div class='ctx'>  *</div><div class='ctx'>  * This function will return the match fields of the first instance of flow</div><div class='ctx'>  * profile having the given header types and containing input VSI</div><div class='ctx'>  */</div><div class='del'>-u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs)</div><div class='add'>+u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs, bool *symm)</div><div class='ctx'> {</div><div class='ctx'> 	u64 rss_hash = ICE_HASH_INVALID;</div><div class='ctx'> 	struct ice_rss_cfg *r;</div><div class='hunk'>@@ -2444,8 +2691,9 @@ u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs)</div><div class='ctx'> 	mutex_lock(&amp;hw-&gt;rss_locks);</div><div class='ctx'> 	list_for_each_entry(r, &amp;hw-&gt;rss_list_head, l_entry)</div><div class='ctx'> 		if (test_bit(vsi_handle, r-&gt;vsis) &amp;&amp;</div><div class='del'>-		    r-&gt;packet_hdr == hdrs) {</div><div class='del'>-			rss_hash = r-&gt;hashed_flds;</div><div class='add'>+		    r-&gt;hash.addl_hdrs == hdrs) {</div><div class='add'>+			rss_hash = r-&gt;hash.hash_flds;</div><div class='add'>+			*symm = r-&gt;hash.symm;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	mutex_unlock(&amp;hw-&gt;rss_locks);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_flow.h b/drivers/net/ethernet/intel/ice/ice_flow.h<br/>index 96923ef0a5a8..ff82915ab497 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flow.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_flow.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_flow.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_flow.h</a></div><div class='hunk'>@@ -34,6 +34,8 @@</div><div class='ctx'> #define ICE_HASH_TCP_IPV6	(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_TCP_PORT)</div><div class='ctx'> #define ICE_HASH_UDP_IPV4	(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_UDP_PORT)</div><div class='ctx'> #define ICE_HASH_UDP_IPV6	(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_UDP_PORT)</div><div class='add'>+#define ICE_HASH_SCTP_IPV4	(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_SCTP_PORT)</div><div class='add'>+#define ICE_HASH_SCTP_IPV6	(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_SCTP_PORT)</div><div class='ctx'> </div><div class='ctx'> #define ICE_FLOW_HASH_GTP_TEID \</div><div class='ctx'> 	(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))</div><div class='hunk'>@@ -227,6 +229,19 @@ enum ice_flow_field {</div><div class='ctx'> 	ICE_FLOW_FIELD_IDX_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define ICE_FLOW_HASH_FLD_IPV4_SA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_IPV6_SA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_IPV4_DA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_IPV6_DA	BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_TCP_SRC_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_TCP_DST_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_UDP_SRC_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_UDP_DST_PORT	BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_SCTP_SRC_PORT	\</div><div class='add'>+	BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT)</div><div class='add'>+#define ICE_FLOW_HASH_FLD_SCTP_DST_PORT	\</div><div class='add'>+	BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT)</div><div class='add'>+</div><div class='ctx'> /* Flow headers and fields for AVF support */</div><div class='ctx'> enum ice_flow_avf_hdr_field {</div><div class='ctx'> 	/* Values 0 - 28 are reserved for future use */</div><div class='hunk'>@@ -279,6 +294,24 @@ enum ice_flow_avf_hdr_field {</div><div class='ctx'> 	BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \</div><div class='ctx'> 	BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP))</div><div class='ctx'> </div><div class='add'>+enum ice_rss_cfg_hdr_type {</div><div class='add'>+	ICE_RSS_OUTER_HEADERS, /* take outer headers as inputset. */</div><div class='add'>+	ICE_RSS_INNER_HEADERS, /* take inner headers as inputset. */</div><div class='add'>+	/* take inner headers as inputset for packet with outer ipv4. */</div><div class='add'>+	ICE_RSS_INNER_HEADERS_W_OUTER_IPV4,</div><div class='add'>+	/* take inner headers as inputset for packet with outer ipv6. */</div><div class='add'>+	ICE_RSS_INNER_HEADERS_W_OUTER_IPV6,</div><div class='add'>+	/* take outer headers first then inner headers as inputset */</div><div class='add'>+	ICE_RSS_ANY_HEADERS</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_rss_hash_cfg {</div><div class='add'>+	u32 addl_hdrs; /* protocol header fields */</div><div class='add'>+	u64 hash_flds; /* hash bit field (ICE_FLOW_HASH_*) to configure */</div><div class='add'>+	enum ice_rss_cfg_hdr_type hdr_type; /* to specify inner or outer */</div><div class='add'>+	bool symm; /* symmetric or asymmetric hash */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum ice_flow_dir {</div><div class='ctx'> 	ICE_FLOW_RX		= 0x02,</div><div class='ctx'> };</div><div class='hunk'>@@ -289,8 +322,10 @@ enum ice_flow_priority {</div><div class='ctx'> 	ICE_FLOW_PRIO_HIGH</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define ICE_FLOW_SEG_SINGLE		1</div><div class='ctx'> #define ICE_FLOW_SEG_MAX		2</div><div class='ctx'> #define ICE_FLOW_SEG_RAW_FLD_MAX	2</div><div class='add'>+#define ICE_FLOW_SW_FIELD_VECTOR_MAX	48</div><div class='ctx'> #define ICE_FLOW_FV_EXTRACT_SZ		2</div><div class='ctx'> </div><div class='ctx'> #define ICE_FLOW_SET_HDRS(seg, val)	((seg)-&gt;hdrs |= (u32)(val))</div><div class='hunk'>@@ -372,20 +407,21 @@ struct ice_flow_prof {</div><div class='ctx'> </div><div class='ctx'> 	/* software VSI handles referenced by this flow profile */</div><div class='ctx'> 	DECLARE_BITMAP(vsis, ICE_MAX_VSI);</div><div class='add'>+</div><div class='add'>+	bool symm; /* Symmetric Hash for RSS */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ice_rss_cfg {</div><div class='ctx'> 	struct list_head l_entry;</div><div class='ctx'> 	/* bitmap of VSIs added to the RSS entry */</div><div class='ctx'> 	DECLARE_BITMAP(vsis, ICE_MAX_VSI);</div><div class='del'>-	u64 hashed_flds;</div><div class='del'>-	u32 packet_hdr;</div><div class='add'>+	struct ice_rss_hash_cfg hash;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int</div><div class='ctx'> ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,</div><div class='del'>-		  u64 prof_id, struct ice_flow_seg_info *segs, u8 segs_cnt,</div><div class='del'>-		  struct ice_flow_prof **prof);</div><div class='add'>+		  struct ice_flow_seg_info *segs, u8 segs_cnt,</div><div class='add'>+		  bool symm, struct ice_flow_prof **prof);</div><div class='ctx'> int ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id);</div><div class='ctx'> int</div><div class='ctx'> ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,</div><div class='hunk'>@@ -401,13 +437,13 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,</div><div class='ctx'> int ice_flow_rem_vsi_prof(struct ice_hw *hw, u16 vsi_handle, u64 prof_id);</div><div class='ctx'> void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);</div><div class='ctx'> int ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);</div><div class='del'>-int ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds);</div><div class='add'>+int ice_set_rss_cfg_symm(struct ice_hw *hw, struct ice_vsi *vsi, bool symm);</div><div class='add'>+int ice_add_avf_rss_cfg(struct ice_hw *hw, struct ice_vsi *vsi,</div><div class='add'>+			u64 hashed_flds);</div><div class='ctx'> int ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle);</div><div class='del'>-int</div><div class='del'>-ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		u32 addl_hdrs);</div><div class='del'>-int</div><div class='del'>-ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,</div><div class='del'>-		u32 addl_hdrs);</div><div class='del'>-u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs);</div><div class='add'>+int ice_add_rss_cfg(struct ice_hw *hw, struct ice_vsi *vsi,</div><div class='add'>+		    const struct ice_rss_hash_cfg *cfg);</div><div class='add'>+int ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle,</div><div class='add'>+		    const struct ice_rss_hash_cfg *cfg);</div><div class='add'>+u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs, bool *symm);</div><div class='ctx'> #endif /* _ICE_FLOW_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_fwlog.c b/drivers/net/ethernet/intel/ice/ice_fwlog.c<br/>new file mode 100644<br/>index 000000000000..92b5dac481cd<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_fwlog.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fwlog.c</a></div><div class='hunk'>@@ -0,0 +1,470 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright (c) 2022, Intel Corporation. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='add'>+#include "ice.h"</div><div class='add'>+#include "ice_common.h"</div><div class='add'>+#include "ice_fwlog.h"</div><div class='add'>+</div><div class='add'>+bool ice_fwlog_ring_full(struct ice_fwlog_ring *rings)</div><div class='add'>+{</div><div class='add'>+	u16 head, tail;</div><div class='add'>+</div><div class='add'>+	head = rings-&gt;head;</div><div class='add'>+	tail = rings-&gt;tail;</div><div class='add'>+</div><div class='add'>+	if (head &lt; tail &amp;&amp; (tail - head == (rings-&gt;size - 1)))</div><div class='add'>+		return true;</div><div class='add'>+	else if (head &gt; tail &amp;&amp; (tail == (head - 1)))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+bool ice_fwlog_ring_empty(struct ice_fwlog_ring *rings)</div><div class='add'>+{</div><div class='add'>+	return rings-&gt;head == rings-&gt;tail;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ice_fwlog_ring_increment(u16 *item, u16 size)</div><div class='add'>+{</div><div class='add'>+	*item = (*item + 1) &amp; (size - 1);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ice_fwlog_alloc_ring_buffs(struct ice_fwlog_ring *rings)</div><div class='add'>+{</div><div class='add'>+	int i, nr_bytes;</div><div class='add'>+	u8 *mem;</div><div class='add'>+</div><div class='add'>+	nr_bytes = rings-&gt;size * ICE_AQ_MAX_BUF_LEN;</div><div class='add'>+	mem = vzalloc(nr_bytes);</div><div class='add'>+	if (!mem)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; rings-&gt;size; i++) {</div><div class='add'>+		struct ice_fwlog_data *ring = &amp;rings-&gt;rings[i];</div><div class='add'>+</div><div class='add'>+		ring-&gt;data_size = ICE_AQ_MAX_BUF_LEN;</div><div class='add'>+		ring-&gt;data = mem;</div><div class='add'>+		mem += ICE_AQ_MAX_BUF_LEN;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ice_fwlog_free_ring_buffs(struct ice_fwlog_ring *rings)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; rings-&gt;size; i++) {</div><div class='add'>+		struct ice_fwlog_data *ring = &amp;rings-&gt;rings[i];</div><div class='add'>+</div><div class='add'>+		/* the first ring is the base memory for the whole range so</div><div class='add'>+		 * free it</div><div class='add'>+		 */</div><div class='add'>+		if (!i)</div><div class='add'>+			vfree(ring-&gt;data);</div><div class='add'>+</div><div class='add'>+		ring-&gt;data = NULL;</div><div class='add'>+		ring-&gt;data_size = 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define ICE_FWLOG_INDEX_TO_BYTES(n) ((128 * 1024) &lt;&lt; (n))</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_realloc_rings - reallocate the FW log rings</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @index: the new index to use to allocate memory for the log data</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+void ice_fwlog_realloc_rings(struct ice_hw *hw, int index)</div><div class='add'>+{</div><div class='add'>+	struct ice_fwlog_ring ring;</div><div class='add'>+	int status, ring_size;</div><div class='add'>+</div><div class='add'>+	/* convert the number of bytes into a number of 4K buffers. externally</div><div class='add'>+	 * the driver presents the interface to the FW log data as a number of</div><div class='add'>+	 * bytes because that's easy for users to understand. internally the</div><div class='add'>+	 * driver uses a ring of buffers because the driver doesn't know where</div><div class='add'>+	 * the beginning and end of any line of log data is so the driver has</div><div class='add'>+	 * to overwrite data as complete blocks. when the data is returned to</div><div class='add'>+	 * the user the driver knows that the data is correct and the FW log</div><div class='add'>+	 * can be correctly parsed by the tools</div><div class='add'>+	 */</div><div class='add'>+	ring_size = ICE_FWLOG_INDEX_TO_BYTES(index) / ICE_AQ_MAX_BUF_LEN;</div><div class='add'>+	if (ring_size == hw-&gt;fwlog_ring.size)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* allocate space for the new rings and buffers then release the</div><div class='add'>+	 * old rings and buffers. that way if we don't have enough</div><div class='add'>+	 * memory then we at least have what we had before</div><div class='add'>+	 */</div><div class='add'>+	ring.rings = kcalloc(ring_size, sizeof(*ring.rings), GFP_KERNEL);</div><div class='add'>+	if (!ring.rings)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ring.size = ring_size;</div><div class='add'>+</div><div class='add'>+	status = ice_fwlog_alloc_ring_buffs(&amp;ring);</div><div class='add'>+	if (status) {</div><div class='add'>+		dev_warn(ice_hw_to_dev(hw), "Unable to allocate memory for FW log ring data buffers\n");</div><div class='add'>+		ice_fwlog_free_ring_buffs(&amp;ring);</div><div class='add'>+		kfree(ring.rings);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ice_fwlog_free_ring_buffs(&amp;hw-&gt;fwlog_ring);</div><div class='add'>+	kfree(hw-&gt;fwlog_ring.rings);</div><div class='add'>+</div><div class='add'>+	hw-&gt;fwlog_ring.rings = ring.rings;</div><div class='add'>+	hw-&gt;fwlog_ring.size = ring.size;</div><div class='add'>+	hw-&gt;fwlog_ring.index = index;</div><div class='add'>+	hw-&gt;fwlog_ring.head = 0;</div><div class='add'>+	hw-&gt;fwlog_ring.tail = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_init - Initialize FW logging configuration</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ *</div><div class='add'>+ * This function should be called on driver initialization during</div><div class='add'>+ * ice_init_hw().</div><div class='add'>+ */</div><div class='add'>+int ice_fwlog_init(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	/* only support fw log commands on PF 0 */</div><div class='add'>+	if (hw-&gt;bus.func)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	ice_fwlog_set_supported(hw);</div><div class='add'>+</div><div class='add'>+	if (ice_fwlog_supported(hw)) {</div><div class='add'>+		int status;</div><div class='add'>+</div><div class='add'>+		/* read the current config from the FW and store it */</div><div class='add'>+		status = ice_fwlog_get(hw, &amp;hw-&gt;fwlog_cfg);</div><div class='add'>+		if (status)</div><div class='add'>+			return status;</div><div class='add'>+</div><div class='add'>+		hw-&gt;fwlog_ring.rings = kcalloc(ICE_FWLOG_RING_SIZE_DFLT,</div><div class='add'>+					       sizeof(*hw-&gt;fwlog_ring.rings),</div><div class='add'>+					       GFP_KERNEL);</div><div class='add'>+		if (!hw-&gt;fwlog_ring.rings) {</div><div class='add'>+			dev_warn(ice_hw_to_dev(hw), "Unable to allocate memory for FW log rings\n");</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		hw-&gt;fwlog_ring.size = ICE_FWLOG_RING_SIZE_DFLT;</div><div class='add'>+		hw-&gt;fwlog_ring.index = ICE_FWLOG_RING_SIZE_INDEX_DFLT;</div><div class='add'>+</div><div class='add'>+		status = ice_fwlog_alloc_ring_buffs(&amp;hw-&gt;fwlog_ring);</div><div class='add'>+		if (status) {</div><div class='add'>+			dev_warn(ice_hw_to_dev(hw), "Unable to allocate memory for FW log ring data buffers\n");</div><div class='add'>+			ice_fwlog_free_ring_buffs(&amp;hw-&gt;fwlog_ring);</div><div class='add'>+			kfree(hw-&gt;fwlog_ring.rings);</div><div class='add'>+			return status;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ice_debugfs_fwlog_init(hw-&gt;back);</div><div class='add'>+	} else {</div><div class='add'>+		dev_warn(ice_hw_to_dev(hw), "FW logging is not supported in this NVM image. Please update the NVM to get FW log support\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_deinit - unroll FW logging configuration</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ *</div><div class='add'>+ * This function should be called in ice_deinit_hw().</div><div class='add'>+ */</div><div class='add'>+void ice_fwlog_deinit(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = hw-&gt;back;</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	/* only support fw log commands on PF 0 */</div><div class='add'>+	if (hw-&gt;bus.func)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* make sure FW logging is disabled to not put the FW in a weird state</div><div class='add'>+	 * for the next driver load</div><div class='add'>+	 */</div><div class='add'>+	hw-&gt;fwlog_cfg.options &amp;= ~ICE_FWLOG_OPTION_ARQ_ENA;</div><div class='add'>+	status = ice_fwlog_set(hw, &amp;hw-&gt;fwlog_cfg);</div><div class='add'>+	if (status)</div><div class='add'>+		dev_warn(ice_hw_to_dev(hw), "Unable to turn off FW logging, status: %d\n",</div><div class='add'>+			 status);</div><div class='add'>+</div><div class='add'>+	kfree(pf-&gt;ice_debugfs_pf_fwlog_modules);</div><div class='add'>+</div><div class='add'>+	pf-&gt;ice_debugfs_pf_fwlog_modules = NULL;</div><div class='add'>+</div><div class='add'>+	status = ice_fwlog_unregister(hw);</div><div class='add'>+	if (status)</div><div class='add'>+		dev_warn(ice_hw_to_dev(hw), "Unable to unregister FW logging, status: %d\n",</div><div class='add'>+			 status);</div><div class='add'>+</div><div class='add'>+	if (hw-&gt;fwlog_ring.rings) {</div><div class='add'>+		ice_fwlog_free_ring_buffs(&amp;hw-&gt;fwlog_ring);</div><div class='add'>+		kfree(hw-&gt;fwlog_ring.rings);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_supported - Cached for whether FW supports FW logging or not</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ *</div><div class='add'>+ * This will always return false if called before ice_init_hw(), so it must be</div><div class='add'>+ * called after ice_init_hw().</div><div class='add'>+ */</div><div class='add'>+bool ice_fwlog_supported(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	return hw-&gt;fwlog_supported;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_aq_fwlog_set - Set FW logging configuration AQ command (0xFF30)</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @entries: entries to configure</div><div class='add'>+ * @num_entries: number of @entries</div><div class='add'>+ * @options: options from ice_fwlog_cfg-&gt;options structure</div><div class='add'>+ * @log_resolution: logging resolution</div><div class='add'>+ */</div><div class='add'>+static int</div><div class='add'>+ice_aq_fwlog_set(struct ice_hw *hw, struct ice_fwlog_module_entry *entries,</div><div class='add'>+		 u16 num_entries, u16 options, u16 log_resolution)</div><div class='add'>+{</div><div class='add'>+	struct ice_aqc_fw_log_cfg_resp *fw_modules;</div><div class='add'>+	struct ice_aqc_fw_log *cmd;</div><div class='add'>+	struct ice_aq_desc desc;</div><div class='add'>+	int status;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	fw_modules = kcalloc(num_entries, sizeof(*fw_modules), GFP_KERNEL);</div><div class='add'>+	if (!fw_modules)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_entries; i++) {</div><div class='add'>+		fw_modules[i].module_identifier =</div><div class='add'>+			cpu_to_le16(entries[i].module_id);</div><div class='add'>+		fw_modules[i].log_level = entries[i].log_level;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_fw_logs_config);</div><div class='add'>+	desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);</div><div class='add'>+</div><div class='add'>+	cmd = &amp;desc.params.fw_log;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd_flags = ICE_AQC_FW_LOG_CONF_SET_VALID;</div><div class='add'>+	cmd-&gt;ops.cfg.log_resolution = cpu_to_le16(log_resolution);</div><div class='add'>+	cmd-&gt;ops.cfg.mdl_cnt = cpu_to_le16(num_entries);</div><div class='add'>+</div><div class='add'>+	if (options &amp; ICE_FWLOG_OPTION_ARQ_ENA)</div><div class='add'>+		cmd-&gt;cmd_flags |= ICE_AQC_FW_LOG_CONF_AQ_EN;</div><div class='add'>+	if (options &amp; ICE_FWLOG_OPTION_UART_ENA)</div><div class='add'>+		cmd-&gt;cmd_flags |= ICE_AQC_FW_LOG_CONF_UART_EN;</div><div class='add'>+</div><div class='add'>+	status = ice_aq_send_cmd(hw, &amp;desc, fw_modules,</div><div class='add'>+				 sizeof(*fw_modules) * num_entries,</div><div class='add'>+				 NULL);</div><div class='add'>+</div><div class='add'>+	kfree(fw_modules);</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_set - Set the firmware logging settings</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @cfg: config used to set firmware logging</div><div class='add'>+ *</div><div class='add'>+ * This function should be called whenever the driver needs to set the firmware</div><div class='add'>+ * logging configuration. It can be called on initialization, reset, or during</div><div class='add'>+ * runtime.</div><div class='add'>+ *</div><div class='add'>+ * If the PF wishes to receive FW logging then it must register via</div><div class='add'>+ * ice_fwlog_register. Note, that ice_fwlog_register does not need to be called</div><div class='add'>+ * for init.</div><div class='add'>+ */</div><div class='add'>+int ice_fwlog_set(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)</div><div class='add'>+{</div><div class='add'>+	if (!ice_fwlog_supported(hw))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return ice_aq_fwlog_set(hw, cfg-&gt;module_entries,</div><div class='add'>+				ICE_AQC_FW_LOG_ID_MAX, cfg-&gt;options,</div><div class='add'>+				cfg-&gt;log_resolution);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_aq_fwlog_get - Get the current firmware logging configuration (0xFF32)</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @cfg: firmware logging configuration to populate</div><div class='add'>+ */</div><div class='add'>+static int ice_aq_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)</div><div class='add'>+{</div><div class='add'>+	struct ice_aqc_fw_log_cfg_resp *fw_modules;</div><div class='add'>+	struct ice_aqc_fw_log *cmd;</div><div class='add'>+	struct ice_aq_desc desc;</div><div class='add'>+	u16 module_id_cnt;</div><div class='add'>+	int status;</div><div class='add'>+	void *buf;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	memset(cfg, 0, sizeof(*cfg));</div><div class='add'>+</div><div class='add'>+	buf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);</div><div class='add'>+	if (!buf)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_fw_logs_query);</div><div class='add'>+	cmd = &amp;desc.params.fw_log;</div><div class='add'>+</div><div class='add'>+	cmd-&gt;cmd_flags = ICE_AQC_FW_LOG_AQ_QUERY;</div><div class='add'>+</div><div class='add'>+	status = ice_aq_send_cmd(hw, &amp;desc, buf, ICE_AQ_MAX_BUF_LEN, NULL);</div><div class='add'>+	if (status) {</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "Failed to get FW log configuration\n");</div><div class='add'>+		goto status_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	module_id_cnt = le16_to_cpu(cmd-&gt;ops.cfg.mdl_cnt);</div><div class='add'>+	if (module_id_cnt &lt; ICE_AQC_FW_LOG_ID_MAX) {</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "FW returned less than the expected number of FW log module IDs\n");</div><div class='add'>+	} else if (module_id_cnt &gt; ICE_AQC_FW_LOG_ID_MAX) {</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "FW returned more than expected number of FW log module IDs, setting module_id_cnt to software expected max %u\n",</div><div class='add'>+			  ICE_AQC_FW_LOG_ID_MAX);</div><div class='add'>+		module_id_cnt = ICE_AQC_FW_LOG_ID_MAX;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	cfg-&gt;log_resolution = le16_to_cpu(cmd-&gt;ops.cfg.log_resolution);</div><div class='add'>+	if (cmd-&gt;cmd_flags &amp; ICE_AQC_FW_LOG_CONF_AQ_EN)</div><div class='add'>+		cfg-&gt;options |= ICE_FWLOG_OPTION_ARQ_ENA;</div><div class='add'>+	if (cmd-&gt;cmd_flags &amp; ICE_AQC_FW_LOG_CONF_UART_EN)</div><div class='add'>+		cfg-&gt;options |= ICE_FWLOG_OPTION_UART_ENA;</div><div class='add'>+	if (cmd-&gt;cmd_flags &amp; ICE_AQC_FW_LOG_QUERY_REGISTERED)</div><div class='add'>+		cfg-&gt;options |= ICE_FWLOG_OPTION_IS_REGISTERED;</div><div class='add'>+</div><div class='add'>+	fw_modules = (struct ice_aqc_fw_log_cfg_resp *)buf;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; module_id_cnt; i++) {</div><div class='add'>+		struct ice_aqc_fw_log_cfg_resp *fw_module = &amp;fw_modules[i];</div><div class='add'>+</div><div class='add'>+		cfg-&gt;module_entries[i].module_id =</div><div class='add'>+			le16_to_cpu(fw_module-&gt;module_identifier);</div><div class='add'>+		cfg-&gt;module_entries[i].log_level = fw_module-&gt;log_level;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+status_out:</div><div class='add'>+	kfree(buf);</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_get - Get the firmware logging settings</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @cfg: config to populate based on current firmware logging settings</div><div class='add'>+ */</div><div class='add'>+int ice_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg)</div><div class='add'>+{</div><div class='add'>+	if (!ice_fwlog_supported(hw))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return ice_aq_fwlog_get(hw, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_aq_fwlog_register - Register PF for firmware logging events (0xFF31)</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ * @reg: true to register and false to unregister</div><div class='add'>+ */</div><div class='add'>+static int ice_aq_fwlog_register(struct ice_hw *hw, bool reg)</div><div class='add'>+{</div><div class='add'>+	struct ice_aq_desc desc;</div><div class='add'>+</div><div class='add'>+	ice_fill_dflt_direct_cmd_desc(&amp;desc, ice_aqc_opc_fw_logs_register);</div><div class='add'>+</div><div class='add'>+	if (reg)</div><div class='add'>+		desc.params.fw_log.cmd_flags = ICE_AQC_FW_LOG_AQ_REGISTER;</div><div class='add'>+</div><div class='add'>+	return ice_aq_send_cmd(hw, &amp;desc, NULL, 0, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_register - Register the PF for firmware logging</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ *</div><div class='add'>+ * After this call the PF will start to receive firmware logging based on the</div><div class='add'>+ * configuration set in ice_fwlog_set.</div><div class='add'>+ */</div><div class='add'>+int ice_fwlog_register(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	if (!ice_fwlog_supported(hw))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	status = ice_aq_fwlog_register(hw, true);</div><div class='add'>+	if (status)</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "Failed to register for firmware logging events over ARQ\n");</div><div class='add'>+	else</div><div class='add'>+		hw-&gt;fwlog_cfg.options |= ICE_FWLOG_OPTION_IS_REGISTERED;</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_unregister - Unregister the PF from firmware logging</div><div class='add'>+ * @hw: pointer to the HW structure</div><div class='add'>+ */</div><div class='add'>+int ice_fwlog_unregister(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	if (!ice_fwlog_supported(hw))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	status = ice_aq_fwlog_register(hw, false);</div><div class='add'>+	if (status)</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "Failed to unregister from firmware logging events over ARQ\n");</div><div class='add'>+	else</div><div class='add'>+		hw-&gt;fwlog_cfg.options &amp;= ~ICE_FWLOG_OPTION_IS_REGISTERED;</div><div class='add'>+</div><div class='add'>+	return status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_fwlog_set_supported - Set if FW logging is supported by FW</div><div class='add'>+ * @hw: pointer to the HW struct</div><div class='add'>+ *</div><div class='add'>+ * If FW returns success to the ice_aq_fwlog_get call then it supports FW</div><div class='add'>+ * logging, else it doesn't. Set the fwlog_supported flag accordingly.</div><div class='add'>+ *</div><div class='add'>+ * This function is only meant to be called during driver init to determine if</div><div class='add'>+ * the FW support FW logging.</div><div class='add'>+ */</div><div class='add'>+void ice_fwlog_set_supported(struct ice_hw *hw)</div><div class='add'>+{</div><div class='add'>+	struct ice_fwlog_cfg *cfg;</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	hw-&gt;fwlog_supported = false;</div><div class='add'>+</div><div class='add'>+	cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);</div><div class='add'>+	if (!cfg)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* don't call ice_fwlog_get() because that would check to see if FW</div><div class='add'>+	 * logging is supported which is what the driver is determining now</div><div class='add'>+	 */</div><div class='add'>+	status = ice_aq_fwlog_get(hw, cfg);</div><div class='add'>+	if (status)</div><div class='add'>+		ice_debug(hw, ICE_DBG_FW_LOG, "ice_aq_fwlog_get failed, FW logging is not supported on this version of FW, status %d\n",</div><div class='add'>+			  status);</div><div class='add'>+	else</div><div class='add'>+		hw-&gt;fwlog_supported = true;</div><div class='add'>+</div><div class='add'>+	kfree(cfg);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_fwlog.h b/drivers/net/ethernet/intel/ice/ice_fwlog.h<br/>new file mode 100644<br/>index 000000000000..287e71fa4b86<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_fwlog.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_fwlog.h</a></div><div class='hunk'>@@ -0,0 +1,79 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Copyright (C) 2022, Intel Corporation. */</div><div class='add'>+</div><div class='add'>+#ifndef _ICE_FWLOG_H_</div><div class='add'>+#define _ICE_FWLOG_H_</div><div class='add'>+#include "ice_adminq_cmd.h"</div><div class='add'>+</div><div class='add'>+struct ice_hw;</div><div class='add'>+</div><div class='add'>+/* Only a single log level should be set and all log levels under the set value</div><div class='add'>+ * are enabled, e.g. if log level is set to ICE_FW_LOG_LEVEL_VERBOSE, then all</div><div class='add'>+ * other log levels are included (except ICE_FW_LOG_LEVEL_NONE)</div><div class='add'>+ */</div><div class='add'>+enum ice_fwlog_level {</div><div class='add'>+	ICE_FWLOG_LEVEL_NONE = 0,</div><div class='add'>+	ICE_FWLOG_LEVEL_ERROR = 1,</div><div class='add'>+	ICE_FWLOG_LEVEL_WARNING = 2,</div><div class='add'>+	ICE_FWLOG_LEVEL_NORMAL = 3,</div><div class='add'>+	ICE_FWLOG_LEVEL_VERBOSE = 4,</div><div class='add'>+	ICE_FWLOG_LEVEL_INVALID, /* all values &gt;= this entry are invalid */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_fwlog_module_entry {</div><div class='add'>+	/* module ID for the corresponding firmware logging event */</div><div class='add'>+	u16 module_id;</div><div class='add'>+	/* verbosity level for the module_id */</div><div class='add'>+	u8 log_level;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_fwlog_cfg {</div><div class='add'>+	/* list of modules for configuring log level */</div><div class='add'>+	struct ice_fwlog_module_entry module_entries[ICE_AQC_FW_LOG_ID_MAX];</div><div class='add'>+	/* options used to configure firmware logging */</div><div class='add'>+	u16 options;</div><div class='add'>+#define ICE_FWLOG_OPTION_ARQ_ENA		BIT(0)</div><div class='add'>+#define ICE_FWLOG_OPTION_UART_ENA		BIT(1)</div><div class='add'>+	/* set before calling ice_fwlog_init() so the PF registers for firmware</div><div class='add'>+	 * logging on initialization</div><div class='add'>+	 */</div><div class='add'>+#define ICE_FWLOG_OPTION_REGISTER_ON_INIT	BIT(2)</div><div class='add'>+	/* set in the ice_fwlog_get() response if the PF is registered for FW</div><div class='add'>+	 * logging events over ARQ</div><div class='add'>+	 */</div><div class='add'>+#define ICE_FWLOG_OPTION_IS_REGISTERED		BIT(3)</div><div class='add'>+</div><div class='add'>+	/* minimum number of log events sent per Admin Receive Queue event */</div><div class='add'>+	u16 log_resolution;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_fwlog_data {</div><div class='add'>+	u16 data_size;</div><div class='add'>+	u8 *data;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_fwlog_ring {</div><div class='add'>+	struct ice_fwlog_data *rings;</div><div class='add'>+	u16 index;</div><div class='add'>+	u16 size;</div><div class='add'>+	u16 head;</div><div class='add'>+	u16 tail;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define ICE_FWLOG_RING_SIZE_INDEX_DFLT 3</div><div class='add'>+#define ICE_FWLOG_RING_SIZE_DFLT 256</div><div class='add'>+#define ICE_FWLOG_RING_SIZE_MAX 512</div><div class='add'>+</div><div class='add'>+bool ice_fwlog_ring_full(struct ice_fwlog_ring *rings);</div><div class='add'>+bool ice_fwlog_ring_empty(struct ice_fwlog_ring *rings);</div><div class='add'>+void ice_fwlog_ring_increment(u16 *item, u16 size);</div><div class='add'>+void ice_fwlog_set_supported(struct ice_hw *hw);</div><div class='add'>+bool ice_fwlog_supported(struct ice_hw *hw);</div><div class='add'>+int ice_fwlog_init(struct ice_hw *hw);</div><div class='add'>+void ice_fwlog_deinit(struct ice_hw *hw);</div><div class='add'>+int ice_fwlog_set(struct ice_hw *hw, struct ice_fwlog_cfg *cfg);</div><div class='add'>+int ice_fwlog_get(struct ice_hw *hw, struct ice_fwlog_cfg *cfg);</div><div class='add'>+int ice_fwlog_register(struct ice_hw *hw);</div><div class='add'>+int ice_fwlog_unregister(struct ice_hw *hw);</div><div class='add'>+void ice_fwlog_realloc_rings(struct ice_hw *hw, int index);</div><div class='add'>+#endif /* _ICE_FWLOG_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h<br/>index 86936b758ade..cfac1d432c15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_hw_autogen.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_hw_autogen.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_hw_autogen.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hw_autogen.h</a></div><div class='hunk'>@@ -200,6 +200,8 @@</div><div class='ctx'> #define GLINT_VECT2FUNC_PF_NUM_M		ICE_M(0x7, 12)</div><div class='ctx'> #define GLINT_VECT2FUNC_IS_PF_S			16</div><div class='ctx'> #define GLINT_VECT2FUNC_IS_PF_M			BIT(16)</div><div class='add'>+#define PFINT_ALLOC				0x001D2600</div><div class='add'>+#define PFINT_ALLOC_FIRST			ICE_M(0x7FF, 0)</div><div class='ctx'> #define PFINT_FW_CTL				0x0016C800</div><div class='ctx'> #define PFINT_FW_CTL_MSIX_INDX_M		ICE_M(0x7FF, 0)</div><div class='ctx'> #define PFINT_FW_CTL_ITR_INDX_S			11</div><div class='hunk'>@@ -404,6 +406,10 @@</div><div class='ctx'> #define GLQF_HMASK_SEL(_i)			(0x00410000 + ((_i) * 4))</div><div class='ctx'> #define GLQF_HMASK_SEL_MAX_INDEX		127</div><div class='ctx'> #define GLQF_HMASK_SEL_MASK_SEL_S		0</div><div class='add'>+#define GLQF_HSYMM(_i, _j)			(0x0040F000 + ((_i) * 4 + (_j) * 512))</div><div class='add'>+#define GLQF_HSYMM_REG_SIZE			4</div><div class='add'>+#define GLQF_HSYMM_REG_PER_PROF			6</div><div class='add'>+#define GLQF_HSYMM_ENABLE_BIT			BIT(7)</div><div class='ctx'> #define E800_PFQF_FD_CNT_FD_GCNT_M		GENMASK(14, 0)</div><div class='ctx'> #define E830_PFQF_FD_CNT_FD_GCNT_M		GENMASK(15, 0)</div><div class='ctx'> #define E800_PFQF_FD_CNT_FD_BCNT_M		GENMASK(30, 16)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_hwmon.c b/drivers/net/ethernet/intel/ice/ice_hwmon.c<br/>new file mode 100644<br/>index 000000000000..e4c2c1bff6c0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hwmon.c</a></div><div class='hunk'>@@ -0,0 +1,126 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Copyright (C) 2023, Intel Corporation. */</div><div class='add'>+</div><div class='add'>+#include "ice.h"</div><div class='add'>+#include "ice_hwmon.h"</div><div class='add'>+#include "ice_adminq_cmd.h"</div><div class='add'>+</div><div class='add'>+#include &lt;linux/hwmon.h&gt;</div><div class='add'>+</div><div class='add'>+#define TEMP_FROM_REG(reg) ((reg) * 1000)</div><div class='add'>+</div><div class='add'>+static const struct hwmon_channel_info *ice_hwmon_info[] = {</div><div class='add'>+	HWMON_CHANNEL_INFO(temp,</div><div class='add'>+			   HWMON_T_INPUT | HWMON_T_MAX |</div><div class='add'>+			   HWMON_T_CRIT | HWMON_T_EMERGENCY),</div><div class='add'>+	NULL</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ice_hwmon_read(struct device *dev, enum hwmon_sensor_types type,</div><div class='add'>+			  u32 attr, int channel, long *val)</div><div class='add'>+{</div><div class='add'>+	struct ice_aqc_get_sensor_reading_resp resp;</div><div class='add'>+	struct ice_pf *pf = dev_get_drvdata(dev);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (type != hwmon_temp)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	ret = ice_aq_get_sensor_reading(&amp;pf-&gt;hw, &amp;resp);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_warn_ratelimited(dev,</div><div class='add'>+				     "%s HW read failure (%d)\n",</div><div class='add'>+				     __func__,</div><div class='add'>+				     ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_temp_input:</div><div class='add'>+		*val = TEMP_FROM_REG(resp.data.s0f0.temp);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_temp_max:</div><div class='add'>+		*val = TEMP_FROM_REG(resp.data.s0f0.temp_warning_threshold);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_temp_crit:</div><div class='add'>+		*val = TEMP_FROM_REG(resp.data.s0f0.temp_critical_threshold);</div><div class='add'>+		break;</div><div class='add'>+	case hwmon_temp_emergency:</div><div class='add'>+		*val = TEMP_FROM_REG(resp.data.s0f0.temp_fatal_threshold);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_dbg(dev, "%s unsupported attribute (%d)\n",</div><div class='add'>+			__func__, attr);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static umode_t ice_hwmon_is_visible(const void *data,</div><div class='add'>+				    enum hwmon_sensor_types type, u32 attr,</div><div class='add'>+				    int channel)</div><div class='add'>+{</div><div class='add'>+	if (type != hwmon_temp)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	switch (attr) {</div><div class='add'>+	case hwmon_temp_input:</div><div class='add'>+	case hwmon_temp_crit:</div><div class='add'>+	case hwmon_temp_max:</div><div class='add'>+	case hwmon_temp_emergency:</div><div class='add'>+		return 0444;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct hwmon_ops ice_hwmon_ops = {</div><div class='add'>+	.is_visible = ice_hwmon_is_visible,</div><div class='add'>+	.read = ice_hwmon_read</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct hwmon_chip_info ice_chip_info = {</div><div class='add'>+	.ops = &amp;ice_hwmon_ops,</div><div class='add'>+	.info = ice_hwmon_info</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool ice_is_internal_reading_supported(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	/* Only the first PF will report temperature for a chip.</div><div class='add'>+	 * Note that internal temp reading is not supported</div><div class='add'>+	 * for older FW (&lt; v4.30).</div><div class='add'>+	 */</div><div class='add'>+	if (pf-&gt;hw.pf_id)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	unsigned long sensors = pf-&gt;hw.dev_caps.supported_sensors;</div><div class='add'>+</div><div class='add'>+	return _test_bit(ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT, &amp;sensors);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+void ice_hwmon_init(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	struct device *hdev;</div><div class='add'>+</div><div class='add'>+	if (!ice_is_internal_reading_supported(pf))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	hdev = hwmon_device_register_with_info(dev, "ice", pf, &amp;ice_chip_info,</div><div class='add'>+					       NULL);</div><div class='add'>+	if (IS_ERR(hdev)) {</div><div class='add'>+		dev_warn(dev,</div><div class='add'>+			 "hwmon_device_register_with_info returns error (%ld)",</div><div class='add'>+			 PTR_ERR(hdev));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	pf-&gt;hwmon_dev = hdev;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void ice_hwmon_exit(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	if (!pf-&gt;hwmon_dev)</div><div class='add'>+		return;</div><div class='add'>+	hwmon_device_unregister(pf-&gt;hwmon_dev);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_hwmon.h b/drivers/net/ethernet/intel/ice/ice_hwmon.h<br/>new file mode 100644<br/>index 000000000000..d66d40354f5a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_hwmon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_hwmon.h</a></div><div class='hunk'>@@ -0,0 +1,15 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Copyright (C) 2023, Intel Corporation. */</div><div class='add'>+</div><div class='add'>+#ifndef _ICE_HWMON_H_</div><div class='add'>+#define _ICE_HWMON_H_</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_ICE_HWMON</div><div class='add'>+void ice_hwmon_init(struct ice_pf *pf);</div><div class='add'>+void ice_hwmon_exit(struct ice_pf *pf);</div><div class='add'>+#else /* CONFIG_ICE_HWMON */</div><div class='add'>+static inline void ice_hwmon_init(struct ice_pf *pf) { }</div><div class='add'>+static inline void ice_hwmon_exit(struct ice_pf *pf) { }</div><div class='add'>+#endif /* CONFIG_ICE_HWMON */</div><div class='add'>+</div><div class='add'>+#endif /* _ICE_HWMON_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_lag.c b/drivers/net/ethernet/intel/ice/ice_lag.c<br/>index cd065ec48c87..2a25323105e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lag.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_lag.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lag.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lag.c</a></div><div class='hunk'>@@ -208,8 +208,7 @@ ice_lag_cfg_fltr(struct ice_lag *lag, u32 act, u16 recipe_id, u16 *rule_idx,</div><div class='ctx'> 		eth_hdr = s_rule-&gt;hdr_data;</div><div class='ctx'> 		ice_fill_eth_hdr(eth_hdr);</div><div class='ctx'> </div><div class='del'>-		act |= (vsi_num &lt;&lt; ICE_SINGLE_ACT_VSI_ID_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_VSI_ID_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, vsi_num);</div><div class='ctx'> </div><div class='ctx'> 		s_rule-&gt;hdr.type = cpu_to_le16(ICE_AQC_SW_RULES_T_LKUP_RX);</div><div class='ctx'> 		s_rule-&gt;recipe_id = cpu_to_le16(recipe_id);</div><div class='hunk'>@@ -570,6 +569,50 @@ resume_traffic:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_lag_build_netdev_list - populate the lag struct's netdev list</div><div class='add'>+ * @lag: local lag struct</div><div class='add'>+ * @ndlist: pointer to netdev list to populate</div><div class='add'>+ */</div><div class='add'>+static void ice_lag_build_netdev_list(struct ice_lag *lag,</div><div class='add'>+				      struct ice_lag_netdev_list *ndlist)</div><div class='add'>+{</div><div class='add'>+	struct ice_lag_netdev_list *nl;</div><div class='add'>+	struct net_device *tmp_nd;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;ndlist-&gt;node);</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	for_each_netdev_in_bond_rcu(lag-&gt;upper_netdev, tmp_nd) {</div><div class='add'>+		nl = kzalloc(sizeof(*nl), GFP_ATOMIC);</div><div class='add'>+		if (!nl)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		nl-&gt;netdev = tmp_nd;</div><div class='add'>+		list_add(&amp;nl-&gt;node, &amp;ndlist-&gt;node);</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+	lag-&gt;netdev_head = &amp;ndlist-&gt;node;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_lag_destroy_netdev_list - free lag struct's netdev list</div><div class='add'>+ * @lag: pointer to local lag struct</div><div class='add'>+ * @ndlist: pointer to lag struct netdev list</div><div class='add'>+ */</div><div class='add'>+static void ice_lag_destroy_netdev_list(struct ice_lag *lag,</div><div class='add'>+					struct ice_lag_netdev_list *ndlist)</div><div class='add'>+{</div><div class='add'>+	struct ice_lag_netdev_list *entry, *n;</div><div class='add'>+</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	list_for_each_entry_safe(entry, n, &amp;ndlist-&gt;node, node) {</div><div class='add'>+		list_del(&amp;entry-&gt;node);</div><div class='add'>+		kfree(entry);</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+	lag-&gt;netdev_head = NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_lag_move_single_vf_nodes - Move Tx scheduling nodes for single VF</div><div class='ctx'>  * @lag: primary interface LAG struct</div><div class='ctx'>  * @oldport: lport of previous interface</div><div class='hunk'>@@ -597,7 +640,6 @@ ice_lag_move_single_vf_nodes(struct ice_lag *lag, u8 oldport, u8 newport,</div><div class='ctx'> void ice_lag_move_new_vf_nodes(struct ice_vf *vf)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_lag_netdev_list ndlist;</div><div class='del'>-	struct list_head *tmp, *n;</div><div class='ctx'> 	u8 pri_port, act_port;</div><div class='ctx'> 	struct ice_lag *lag;</div><div class='ctx'> 	struct ice_vsi *vsi;</div><div class='hunk'>@@ -621,38 +663,15 @@ void ice_lag_move_new_vf_nodes(struct ice_vf *vf)</div><div class='ctx'> 	pri_port = pf-&gt;hw.port_info-&gt;lport;</div><div class='ctx'> 	act_port = lag-&gt;active_port;</div><div class='ctx'> </div><div class='del'>-	if (lag-&gt;upper_netdev) {</div><div class='del'>-		struct ice_lag_netdev_list *nl;</div><div class='del'>-		struct net_device *tmp_nd;</div><div class='del'>-</div><div class='del'>-		INIT_LIST_HEAD(&amp;ndlist.node);</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		for_each_netdev_in_bond_rcu(lag-&gt;upper_netdev, tmp_nd) {</div><div class='del'>-			nl = kzalloc(sizeof(*nl), GFP_ATOMIC);</div><div class='del'>-			if (!nl)</div><div class='del'>-				break;</div><div class='del'>-</div><div class='del'>-			nl-&gt;netdev = tmp_nd;</div><div class='del'>-			list_add(&amp;nl-&gt;node, &amp;ndlist.node);</div><div class='del'>-		}</div><div class='del'>-		rcu_read_unlock();</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	lag-&gt;netdev_head = &amp;ndlist.node;</div><div class='add'>+	if (lag-&gt;upper_netdev)</div><div class='add'>+		ice_lag_build_netdev_list(lag, &amp;ndlist);</div><div class='ctx'> </div><div class='ctx'> 	if (ice_is_feature_supported(pf, ICE_F_SRIOV_LAG) &amp;&amp;</div><div class='ctx'> 	    lag-&gt;bonded &amp;&amp; lag-&gt;primary &amp;&amp; pri_port != act_port &amp;&amp;</div><div class='ctx'> 	    !list_empty(lag-&gt;netdev_head))</div><div class='ctx'> 		ice_lag_move_single_vf_nodes(lag, pri_port, act_port, vsi-&gt;idx);</div><div class='ctx'> </div><div class='del'>-	list_for_each_safe(tmp, n, &amp;ndlist.node) {</div><div class='del'>-		struct ice_lag_netdev_list *entry;</div><div class='del'>-</div><div class='del'>-		entry = list_entry(tmp, struct ice_lag_netdev_list, node);</div><div class='del'>-		list_del(&amp;entry-&gt;node);</div><div class='del'>-		kfree(entry);</div><div class='del'>-	}</div><div class='del'>-	lag-&gt;netdev_head = NULL;</div><div class='add'>+	ice_lag_destroy_netdev_list(lag, &amp;ndlist);</div><div class='ctx'> </div><div class='ctx'> new_vf_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;pf-&gt;lag_mutex);</div><div class='hunk'>@@ -679,6 +698,29 @@ static void ice_lag_move_vf_nodes(struct ice_lag *lag, u8 oldport, u8 newport)</div><div class='ctx'> 			ice_lag_move_single_vf_nodes(lag, oldport, newport, i);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ice_lag_move_vf_nodes_cfg - move vf nodes outside LAG netdev event context</div><div class='add'>+ * @lag: local lag struct</div><div class='add'>+ * @src_prt: lport value for source port</div><div class='add'>+ * @dst_prt: lport value for destination port</div><div class='add'>+ *</div><div class='add'>+ * This function is used to move nodes during an out-of-netdev-event situation,</div><div class='add'>+ * primarily when the driver needs to reconfigure or recreate resources.</div><div class='add'>+ *</div><div class='add'>+ * Must be called while holding the lag_mutex to avoid lag events from</div><div class='add'>+ * processing while out-of-sync moves are happening.  Also, paired moves,</div><div class='add'>+ * such as used in a reset flow, should both be called under the same mutex</div><div class='add'>+ * lock to avoid changes between start of reset and end of reset.</div><div class='add'>+ */</div><div class='add'>+void ice_lag_move_vf_nodes_cfg(struct ice_lag *lag, u8 src_prt, u8 dst_prt)</div><div class='add'>+{</div><div class='add'>+	struct ice_lag_netdev_list ndlist;</div><div class='add'>+</div><div class='add'>+	ice_lag_build_netdev_list(lag, &amp;ndlist);</div><div class='add'>+	ice_lag_move_vf_nodes(lag, src_prt, dst_prt);</div><div class='add'>+	ice_lag_destroy_netdev_list(lag, &amp;ndlist);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #define ICE_LAG_SRIOV_CP_RECIPE		10</div><div class='ctx'> #define ICE_LAG_SRIOV_TRAIN_PKT_LEN	16</div><div class='ctx'> </div><div class='hunk'>@@ -711,9 +753,7 @@ ice_lag_cfg_cp_fltr(struct ice_lag *lag, bool add)</div><div class='ctx'> 		s_rule-&gt;act = cpu_to_le32(ICE_FWD_TO_VSI |</div><div class='ctx'> 					  ICE_SINGLE_ACT_LAN_ENABLE |</div><div class='ctx'> 					  ICE_SINGLE_ACT_VALID_BIT |</div><div class='del'>-					  ((vsi-&gt;vsi_num &lt;&lt;</div><div class='del'>-					    ICE_SINGLE_ACT_VSI_ID_S) &amp;</div><div class='del'>-					   ICE_SINGLE_ACT_VSI_ID_M));</div><div class='add'>+					  FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M, vsi-&gt;vsi_num));</div><div class='ctx'> 		s_rule-&gt;hdr_len = cpu_to_le16(ICE_LAG_SRIOV_TRAIN_PKT_LEN);</div><div class='ctx'> 		memcpy(s_rule-&gt;hdr_data, lacp_train_pkt, LACP_TRAIN_PKT_LEN);</div><div class='ctx'> 		opc = ice_aqc_opc_add_sw_rules;</div><div class='hunk'>@@ -1938,6 +1978,8 @@ int ice_init_lag(struct ice_pf *pf)</div><div class='ctx'> 	int n, err;</div><div class='ctx'> </div><div class='ctx'> 	ice_lag_init_feature_support_flag(pf);</div><div class='add'>+	if (!ice_is_feature_supported(pf, ICE_F_SRIOV_LAG))</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	pf-&gt;lag = kzalloc(sizeof(*lag), GFP_KERNEL);</div><div class='ctx'> 	if (!pf-&gt;lag)</div><div class='hunk'>@@ -2051,7 +2093,6 @@ void ice_lag_rebuild(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_lag_netdev_list ndlist;</div><div class='ctx'> 	struct ice_lag *lag, *prim_lag;</div><div class='del'>-	struct list_head *tmp, *n;</div><div class='ctx'> 	u8 act_port, loc_port;</div><div class='ctx'> </div><div class='ctx'> 	if (!pf-&gt;lag || !pf-&gt;lag-&gt;bonded)</div><div class='hunk'>@@ -2063,21 +2104,7 @@ void ice_lag_rebuild(struct ice_pf *pf)</div><div class='ctx'> 	if (lag-&gt;primary) {</div><div class='ctx'> 		prim_lag = lag;</div><div class='ctx'> 	} else {</div><div class='del'>-		struct ice_lag_netdev_list *nl;</div><div class='del'>-		struct net_device *tmp_nd;</div><div class='del'>-</div><div class='del'>-		INIT_LIST_HEAD(&amp;ndlist.node);</div><div class='del'>-		rcu_read_lock();</div><div class='del'>-		for_each_netdev_in_bond_rcu(lag-&gt;upper_netdev, tmp_nd) {</div><div class='del'>-			nl = kzalloc(sizeof(*nl), GFP_ATOMIC);</div><div class='del'>-			if (!nl)</div><div class='del'>-				break;</div><div class='del'>-</div><div class='del'>-			nl-&gt;netdev = tmp_nd;</div><div class='del'>-			list_add(&amp;nl-&gt;node, &amp;ndlist.node);</div><div class='del'>-		}</div><div class='del'>-		rcu_read_unlock();</div><div class='del'>-		lag-&gt;netdev_head = &amp;ndlist.node;</div><div class='add'>+		ice_lag_build_netdev_list(lag, &amp;ndlist);</div><div class='ctx'> 		prim_lag = ice_lag_find_primary(lag);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2107,13 +2134,7 @@ void ice_lag_rebuild(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	ice_clear_rdma_cap(pf);</div><div class='ctx'> lag_rebuild_out:</div><div class='del'>-	list_for_each_safe(tmp, n, &amp;ndlist.node) {</div><div class='del'>-		struct ice_lag_netdev_list *entry;</div><div class='del'>-</div><div class='del'>-		entry = list_entry(tmp, struct ice_lag_netdev_list, node);</div><div class='del'>-		list_del(&amp;entry-&gt;node);</div><div class='del'>-		kfree(entry);</div><div class='del'>-	}</div><div class='add'>+	ice_lag_destroy_netdev_list(lag, &amp;ndlist);</div><div class='ctx'> 	mutex_unlock(&amp;pf-&gt;lag_mutex);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_lag.h b/drivers/net/ethernet/intel/ice/ice_lag.h<br/>index 9557e8605a07..ede833dfa658 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lag.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_lag.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lag.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lag.h</a></div><div class='hunk'>@@ -65,4 +65,5 @@ int ice_init_lag(struct ice_pf *pf);</div><div class='ctx'> void ice_deinit_lag(struct ice_pf *pf);</div><div class='ctx'> void ice_lag_rebuild(struct ice_pf *pf);</div><div class='ctx'> bool ice_lag_is_switchdev_running(struct ice_pf *pf);</div><div class='add'>+void ice_lag_move_vf_nodes_cfg(struct ice_lag *lag, u8 src_prt, u8 dst_prt);</div><div class='ctx'> #endif /* _ICE_LAG_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h<br/>index 89f986a75cc8..d384ddfcb83e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h</a></div><div class='hunk'>@@ -673,6 +673,212 @@ struct ice_tlan_ctx {</div><div class='ctx'>  *      Use the enum ice_rx_l2_ptype to decode the packet type</div><div class='ctx'>  * ENDIF</div><div class='ctx'>  */</div><div class='add'>+#define ICE_PTYPES								\</div><div class='add'>+	/* L2 Packet types */							\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(0),						\</div><div class='add'>+	ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),			\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(2),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(3),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(4),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(5),						\</div><div class='add'>+	ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),			\</div><div class='add'>+	ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),			\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(8),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(9),						\</div><div class='add'>+	ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),		\</div><div class='add'>+	ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(12),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(13),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(14),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(15),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(16),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(17),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(18),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(19),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(20),						\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(21),						\</div><div class='add'>+										\</div><div class='add'>+	/* Non Tunneled IPv4 */							\</div><div class='add'>+	ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(25),						\</div><div class='add'>+	ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; IPv4 */							\</div><div class='add'>+	ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(32),						\</div><div class='add'>+	ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; IPv6 */							\</div><div class='add'>+	ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(39),						\</div><div class='add'>+	ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT */							\</div><div class='add'>+	ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT --&gt; IPv4 */						\</div><div class='add'>+	ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(47),						\</div><div class='add'>+	ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT --&gt; IPv6 */						\</div><div class='add'>+	ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(54),						\</div><div class='add'>+	ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT --&gt; MAC */						\</div><div class='add'>+	ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT --&gt; MAC --&gt; IPv4 */					\</div><div class='add'>+	ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(62),						\</div><div class='add'>+	ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT -&gt; MAC --&gt; IPv6 */					\</div><div class='add'>+	ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(69),						\</div><div class='add'>+	ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 --&gt; GRE/NAT --&gt; MAC/VLAN */					\</div><div class='add'>+	ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 ---&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv4 */				\</div><div class='add'>+	ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(77),						\</div><div class='add'>+	ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv4 -&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv6 */				\</div><div class='add'>+	ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(84),						\</div><div class='add'>+	ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* Non Tunneled IPv6 */							\</div><div class='add'>+	ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(91),						\</div><div class='add'>+	ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; IPv4 */							\</div><div class='add'>+	ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(98),						\</div><div class='add'>+	ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; IPv6 */							\</div><div class='add'>+	ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(105),						\</div><div class='add'>+	ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT */							\</div><div class='add'>+	ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; IPv4 */						\</div><div class='add'>+	ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(113),						\</div><div class='add'>+	ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; IPv6 */						\</div><div class='add'>+	ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),		\</div><div class='add'>+	ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),		\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(120),						\</div><div class='add'>+	ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),		\</div><div class='add'>+	ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),		\</div><div class='add'>+	ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),		\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC */						\</div><div class='add'>+	ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC -&gt; IPv4 */					\</div><div class='add'>+	ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(128),						\</div><div class='add'>+	ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC -&gt; IPv6 */					\</div><div class='add'>+	ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(135),						\</div><div class='add'>+	ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN */					\</div><div class='add'>+	ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv4 */				\</div><div class='add'>+	ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(143),						\</div><div class='add'>+	ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),	\</div><div class='add'>+										\</div><div class='add'>+	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv6 */				\</div><div class='add'>+	ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),	\</div><div class='add'>+	ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),	\</div><div class='add'>+	ICE_PTT_UNUSED_ENTRY(150),						\</div><div class='add'>+	ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),	\</div><div class='add'>+	ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),	\</div><div class='add'>+	ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),</div><div class='add'>+</div><div class='add'>+#define ICE_NUM_DEFINED_PTYPES	154</div><div class='ctx'> </div><div class='ctx'> /* macro to make the table lines short, use explicit indexing with [PTYPE] */</div><div class='ctx'> #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\</div><div class='hunk'>@@ -695,212 +901,10 @@ struct ice_tlan_ctx {</div><div class='ctx'> </div><div class='ctx'> /* Lookup table mapping in the 10-bit HW PTYPE to the bit field for decoding */</div><div class='ctx'> static const struct ice_rx_ptype_decoded ice_ptype_lkup[BIT(10)] = {</div><div class='del'>-	/* L2 Packet types */</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(0),</div><div class='del'>-	ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(2),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(3),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(5),</div><div class='del'>-	ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),</div><div class='del'>-	ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(8),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(9),</div><div class='del'>-	ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),</div><div class='del'>-	ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(12),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(13),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(14),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(15),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(16),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(17),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(18),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(19),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(20),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(21),</div><div class='del'>-</div><div class='del'>-	/* Non Tunneled IPv4 */</div><div class='del'>-	ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(25),</div><div class='del'>-	ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(32),</div><div class='del'>-	ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(39),</div><div class='del'>-	ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT */</div><div class='del'>-	ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(47),</div><div class='del'>-	ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(54),</div><div class='del'>-	ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT --&gt; MAC */</div><div class='del'>-	ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT --&gt; MAC --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(62),</div><div class='del'>-	ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT -&gt; MAC --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(69),</div><div class='del'>-	ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 --&gt; GRE/NAT --&gt; MAC/VLAN */</div><div class='del'>-	ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv4 ---&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(77),</div><div class='del'>-	ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv4 -&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(84),</div><div class='del'>-	ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* Non Tunneled IPv6 */</div><div class='del'>-	ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(91),</div><div class='del'>-	ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(98),</div><div class='del'>-	ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(105),</div><div class='del'>-	ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT */</div><div class='del'>-	ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; IPv4 */</div><div class='del'>-	ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(113),</div><div class='del'>-	ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; IPv6 */</div><div class='del'>-	ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(120),</div><div class='del'>-	ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC */</div><div class='del'>-	ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC -&gt; IPv4 */</div><div class='del'>-	ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(128),</div><div class='del'>-	ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC -&gt; IPv6 */</div><div class='del'>-	ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(135),</div><div class='del'>-	ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN */</div><div class='del'>-	ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv4 */</div><div class='del'>-	ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(143),</div><div class='del'>-	ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),</div><div class='del'>-</div><div class='del'>-	/* IPv6 --&gt; GRE/NAT -&gt; MAC/VLAN --&gt; IPv6 */</div><div class='del'>-	ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),</div><div class='del'>-	ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),</div><div class='del'>-	ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),</div><div class='del'>-	ICE_PTT_UNUSED_ENTRY(150),</div><div class='del'>-	ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),</div><div class='del'>-	ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),</div><div class='del'>-	ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),</div><div class='add'>+	ICE_PTYPES</div><div class='ctx'> </div><div class='ctx'> 	/* unused entries */</div><div class='del'>-	[154 ... 1023] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }</div><div class='add'>+	[ICE_NUM_DEFINED_PTYPES ... 1023] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c<br/>index 4b1e56396293..9be724291ef8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lib.c</a></div><div class='hunk'>@@ -212,11 +212,18 @@ static void ice_vsi_set_num_qs(struct ice_vsi *vsi)</div><div class='ctx'> 						 vsi-&gt;alloc_txq));</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_VSI_SWITCHDEV_CTRL:</div><div class='del'>-		/* The number of queues for ctrl VSI is equal to number of VFs.</div><div class='add'>+		/* The number of queues for ctrl VSI is equal to number of PRs</div><div class='ctx'> 		 * Each ring is associated to the corresponding VF_PR netdev.</div><div class='add'>+		 * Tx and Rx rings are always equal</div><div class='ctx'> 		 */</div><div class='del'>-		vsi-&gt;alloc_txq = ice_get_num_vfs(pf);</div><div class='del'>-		vsi-&gt;alloc_rxq = vsi-&gt;alloc_txq;</div><div class='add'>+		if (vsi-&gt;req_txq &amp;&amp; vsi-&gt;req_rxq) {</div><div class='add'>+			vsi-&gt;alloc_txq = vsi-&gt;req_txq;</div><div class='add'>+			vsi-&gt;alloc_rxq = vsi-&gt;req_rxq;</div><div class='add'>+		} else {</div><div class='add'>+			vsi-&gt;alloc_txq = 1;</div><div class='add'>+			vsi-&gt;alloc_rxq = 1;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		vsi-&gt;num_q_vectors = 1;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_VSI_VF:</div><div class='hunk'>@@ -519,16 +526,14 @@ static irqreturn_t ice_eswitch_msix_clean_rings(int __always_unused irq, void *d</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_q_vector *q_vector = (struct ice_q_vector *)data;</div><div class='ctx'> 	struct ice_pf *pf = q_vector-&gt;vsi-&gt;back;</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	unsigned long id;</div><div class='ctx'> </div><div class='ctx'> 	if (!q_vector-&gt;tx.tx_ring &amp;&amp; !q_vector-&gt;rx.rx_ring)</div><div class='ctx'> 		return IRQ_HANDLED;</div><div class='ctx'> </div><div class='del'>-	rcu_read_lock();</div><div class='del'>-	ice_for_each_vf_rcu(pf, bkt, vf)</div><div class='del'>-		napi_schedule(&amp;vf-&gt;repr-&gt;q_vector-&gt;napi);</div><div class='del'>-	rcu_read_unlock();</div><div class='add'>+	xa_for_each(&amp;pf-&gt;eswitch.reprs, id, repr)</div><div class='add'>+		napi_schedule(&amp;repr-&gt;q_vector-&gt;napi);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='hunk'>@@ -969,9 +974,8 @@ static void ice_set_dflt_vsi_ctx(struct ice_hw *hw, struct ice_vsi_ctx *ctxt)</div><div class='ctx'> 	/* Traffic from VSI can be sent to LAN */</div><div class='ctx'> 	ctxt-&gt;info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;</div><div class='ctx'> 	/* allow all untagged/tagged packets by default on Tx */</div><div class='del'>-	ctxt-&gt;info.inner_vlan_flags = ((ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL &amp;</div><div class='del'>-				  ICE_AQ_VSI_INNER_VLAN_TX_MODE_M) &gt;&gt;</div><div class='del'>-				 ICE_AQ_VSI_INNER_VLAN_TX_MODE_S);</div><div class='add'>+	ctxt-&gt;info.inner_vlan_flags = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_TX_MODE_M,</div><div class='add'>+						 ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL);</div><div class='ctx'> 	/* SVM - by default bits 3 and 4 in inner_vlan_flags are 0's which</div><div class='ctx'> 	 * results in legacy behavior (show VLAN, DEI, and UP) in descriptor.</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -979,15 +983,14 @@ static void ice_set_dflt_vsi_ctx(struct ice_hw *hw, struct ice_vsi_ctx *ctxt)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ice_is_dvm_ena(hw)) {</div><div class='ctx'> 		ctxt-&gt;info.inner_vlan_flags |=</div><div class='del'>-			ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;</div><div class='add'>+			FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M,</div><div class='add'>+				   ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING);</div><div class='ctx'> 		ctxt-&gt;info.outer_vlan_flags =</div><div class='del'>-			(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL &lt;&lt;</div><div class='del'>-			 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &amp;</div><div class='del'>-			ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;</div><div class='add'>+			FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M,</div><div class='add'>+				   ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL);</div><div class='ctx'> 		ctxt-&gt;info.outer_vlan_flags |=</div><div class='del'>-			(ICE_AQ_VSI_OUTER_TAG_VLAN_8100 &lt;&lt;</div><div class='del'>-			 ICE_AQ_VSI_OUTER_TAG_TYPE_S) &amp;</div><div class='del'>-			ICE_AQ_VSI_OUTER_TAG_TYPE_M;</div><div class='add'>+			FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M,</div><div class='add'>+				   ICE_AQ_VSI_OUTER_TAG_VLAN_8100);</div><div class='ctx'> 		ctxt-&gt;info.outer_vlan_flags |=</div><div class='ctx'> 			FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_EMODE_M,</div><div class='ctx'> 				   ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING);</div><div class='hunk'>@@ -1066,10 +1069,8 @@ static int ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)</div><div class='ctx'> 		vsi-&gt;tc_cfg.tc_info[i].qcount_tx = num_txq_per_tc;</div><div class='ctx'> 		vsi-&gt;tc_cfg.tc_info[i].netdev_tc = netdev_tc++;</div><div class='ctx'> </div><div class='del'>-		qmap = ((offset &lt;&lt; ICE_AQ_VSI_TC_Q_OFFSET_S) &amp;</div><div class='del'>-			ICE_AQ_VSI_TC_Q_OFFSET_M) |</div><div class='del'>-			((pow &lt;&lt; ICE_AQ_VSI_TC_Q_NUM_S) &amp;</div><div class='del'>-			 ICE_AQ_VSI_TC_Q_NUM_M);</div><div class='add'>+		qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, offset);</div><div class='add'>+		qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow);</div><div class='ctx'> 		offset += num_rxq_per_tc;</div><div class='ctx'> 		tx_count += num_txq_per_tc;</div><div class='ctx'> 		ctxt-&gt;info.tc_mapping[i] = cpu_to_le16(qmap);</div><div class='hunk'>@@ -1152,18 +1153,14 @@ static void ice_set_fd_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)</div><div class='ctx'> 	ctxt-&gt;info.max_fd_fltr_shared =</div><div class='ctx'> 			cpu_to_le16(vsi-&gt;num_bfltr);</div><div class='ctx'> 	/* default queue index within the VSI of the default FD */</div><div class='del'>-	val = ((dflt_q &lt;&lt; ICE_AQ_VSI_FD_DEF_Q_S) &amp;</div><div class='del'>-	       ICE_AQ_VSI_FD_DEF_Q_M);</div><div class='add'>+	val = FIELD_PREP(ICE_AQ_VSI_FD_DEF_Q_M, dflt_q);</div><div class='ctx'> 	/* target queue or queue group to the FD filter */</div><div class='del'>-	val |= ((dflt_q_group &lt;&lt; ICE_AQ_VSI_FD_DEF_GRP_S) &amp;</div><div class='del'>-		ICE_AQ_VSI_FD_DEF_GRP_M);</div><div class='add'>+	val |= FIELD_PREP(ICE_AQ_VSI_FD_DEF_GRP_M, dflt_q_group);</div><div class='ctx'> 	ctxt-&gt;info.fd_def_q = cpu_to_le16(val);</div><div class='ctx'> 	/* queue index on which FD filter completion is reported */</div><div class='del'>-	val = ((report_q &lt;&lt; ICE_AQ_VSI_FD_REPORT_Q_S) &amp;</div><div class='del'>-	       ICE_AQ_VSI_FD_REPORT_Q_M);</div><div class='add'>+	val = FIELD_PREP(ICE_AQ_VSI_FD_REPORT_Q_M, report_q);</div><div class='ctx'> 	/* priority of the default qindex action */</div><div class='del'>-	val |= ((dflt_q_prio &lt;&lt; ICE_AQ_VSI_FD_DEF_PRIORITY_S) &amp;</div><div class='del'>-		ICE_AQ_VSI_FD_DEF_PRIORITY_M);</div><div class='add'>+	val |= FIELD_PREP(ICE_AQ_VSI_FD_DEF_PRIORITY_M, dflt_q_prio);</div><div class='ctx'> 	ctxt-&gt;info.fd_report_opt = cpu_to_le16(val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1186,12 +1183,10 @@ static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)</div><div class='ctx'> 	case ICE_VSI_PF:</div><div class='ctx'> 		/* PF VSI will inherit RSS instance of PF */</div><div class='ctx'> 		lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF;</div><div class='del'>-		hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_VSI_VF:</div><div class='ctx'> 		/* VF VSI will gets a small RSS table which is a VSI LUT type */</div><div class='ctx'> 		lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;</div><div class='del'>-		hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_dbg(dev, "Unsupported VSI type %s\n",</div><div class='hunk'>@@ -1199,9 +1194,12 @@ static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ctxt-&gt;info.q_opt_rss = ((lut_type &lt;&lt; ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &amp;</div><div class='del'>-				ICE_AQ_VSI_Q_OPT_RSS_LUT_M) |</div><div class='del'>-				(hash_type &amp; ICE_AQ_VSI_Q_OPT_RSS_HASH_M);</div><div class='add'>+	hash_type = ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ;</div><div class='add'>+	vsi-&gt;rss_hfunc = hash_type;</div><div class='add'>+</div><div class='add'>+	ctxt-&gt;info.q_opt_rss =</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_Q_OPT_RSS_LUT_M, lut_type) |</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_Q_OPT_RSS_HASH_M, hash_type);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -1215,10 +1213,8 @@ ice_chnl_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)</div><div class='ctx'> 	qcount = min_t(int, vsi-&gt;num_rxq, pf-&gt;num_lan_msix);</div><div class='ctx'> </div><div class='ctx'> 	pow = order_base_2(qcount);</div><div class='del'>-	qmap = ((offset &lt;&lt; ICE_AQ_VSI_TC_Q_OFFSET_S) &amp;</div><div class='del'>-		 ICE_AQ_VSI_TC_Q_OFFSET_M) |</div><div class='del'>-		 ((pow &lt;&lt; ICE_AQ_VSI_TC_Q_NUM_S) &amp;</div><div class='del'>-		   ICE_AQ_VSI_TC_Q_NUM_M);</div><div class='add'>+	qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, offset);</div><div class='add'>+	qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow);</div><div class='ctx'> </div><div class='ctx'> 	ctxt-&gt;info.tc_mapping[0] = cpu_to_le16(qmap);</div><div class='ctx'> 	ctxt-&gt;info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG);</div><div class='hunk'>@@ -1600,12 +1596,44 @@ static void ice_vsi_set_vf_rss_flow_fld(struct ice_vsi *vsi)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	status = ice_add_avf_rss_cfg(&amp;pf-&gt;hw, vsi-&gt;idx, ICE_DEFAULT_RSS_HENA);</div><div class='add'>+	status = ice_add_avf_rss_cfg(&amp;pf-&gt;hw, vsi, ICE_DEFAULT_RSS_HENA);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		dev_dbg(dev, "ice_add_avf_rss_cfg failed for vsi = %d, error = %d\n",</div><div class='ctx'> 			vsi-&gt;vsi_num, status);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct ice_rss_hash_cfg default_rss_cfgs[] = {</div><div class='add'>+	/* configure RSS for IPv4 with input set IP src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_IPV4, ICE_FLOW_HASH_IPV4, ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for IPv6 with input set IPv6 src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_IPV6, ICE_FLOW_HASH_IPV6, ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4,</div><div class='add'>+				ICE_HASH_TCP_IPV4,  ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for udp4 with input set IP src/dst, UDP src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4,</div><div class='add'>+				ICE_HASH_UDP_IPV4,  ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for sctp4 with input set IP src/dst - only support</div><div class='add'>+	 * RSS on SCTPv4 on outer headers (non-tunneled)</div><div class='add'>+	 */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4,</div><div class='add'>+		ICE_HASH_SCTP_IPV4, ICE_RSS_OUTER_HEADERS, false},</div><div class='add'>+	/* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6,</div><div class='add'>+				ICE_HASH_TCP_IPV6,  ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6,</div><div class='add'>+				ICE_HASH_UDP_IPV6,  ICE_RSS_ANY_HEADERS, false},</div><div class='add'>+	/* configure RSS for sctp6 with input set IPv6 src/dst - only support</div><div class='add'>+	 * RSS on SCTPv6 on outer headers (non-tunneled)</div><div class='add'>+	 */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6,</div><div class='add'>+		ICE_HASH_SCTP_IPV6, ICE_RSS_OUTER_HEADERS, false},</div><div class='add'>+	/* configure RSS for IPSEC ESP SPI with input set MAC_IPV4_SPI */</div><div class='add'>+	{ICE_FLOW_SEG_HDR_ESP,</div><div class='add'>+		ICE_FLOW_HASH_ESP_SPI, ICE_RSS_OUTER_HEADERS, false},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * ice_vsi_set_rss_flow_fld - Sets RSS input set for different flows</div><div class='ctx'>  * @vsi: VSI to be configured</div><div class='hunk'>@@ -1619,11 +1647,12 @@ static void ice_vsi_set_vf_rss_flow_fld(struct ice_vsi *vsi)</div><div class='ctx'>  */</div><div class='ctx'> static void ice_vsi_set_rss_flow_fld(struct ice_vsi *vsi)</div><div class='ctx'> {</div><div class='del'>-	u16 vsi_handle = vsi-&gt;idx, vsi_num = vsi-&gt;vsi_num;</div><div class='add'>+	u16 vsi_num = vsi-&gt;vsi_num;</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	int status;</div><div class='add'>+	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	dev = ice_pf_to_dev(pf);</div><div class='ctx'> 	if (ice_is_safe_mode(pf)) {</div><div class='hunk'>@@ -1631,67 +1660,15 @@ static void ice_vsi_set_rss_flow_fld(struct ice_vsi *vsi)</div><div class='ctx'> 			vsi_num);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='del'>-	/* configure RSS for IPv4 with input set IP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV4,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_IPV4);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for ipv4 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for IPv6 with input set IPv6 src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV6,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_IPV6);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for ipv6 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_TCP_IPV4,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for tcp4 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(default_rss_cfgs); i++) {</div><div class='add'>+		const struct ice_rss_hash_cfg *cfg = &amp;default_rss_cfgs[i];</div><div class='ctx'> </div><div class='del'>-	/* configure RSS for udp4 with input set IP src/dst, UDP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_UDP_IPV4,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for udp4 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for sctp4 with input set IP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV4,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for sctp4 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_TCP_IPV6,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for tcp6 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_UDP_IPV6,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for udp6 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	/* configure RSS for sctp6 with input set IPv6 src/dst */</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV6,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for sctp6 flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='del'>-</div><div class='del'>-	status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_ESP_SPI,</div><div class='del'>-				 ICE_FLOW_SEG_HDR_ESP);</div><div class='del'>-	if (status)</div><div class='del'>-		dev_dbg(dev, "ice_add_rss_cfg failed for esp/spi flow, vsi = %d, error = %d\n",</div><div class='del'>-			vsi_num, status);</div><div class='add'>+		status = ice_add_rss_cfg(hw, vsi, cfg);</div><div class='add'>+		if (status)</div><div class='add'>+			dev_dbg(dev, "ice_add_rss_cfg failed, addl_hdrs = %x, hash_flds = %llx, hdr_type = %d, symm = %d\n",</div><div class='add'>+				cfg-&gt;addl_hdrs, cfg-&gt;hash_flds,</div><div class='add'>+				cfg-&gt;hdr_type, cfg-&gt;symm);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1808,11 +1785,8 @@ ice_write_qrxflxp_cntxt(struct ice_hw *hw, u16 pf_q, u32 rxdid, u32 prio,</div><div class='ctx'> 		    QRXFLXP_CNTXT_RXDID_PRIO_M |</div><div class='ctx'> 		    QRXFLXP_CNTXT_TS_M);</div><div class='ctx'> </div><div class='del'>-	regval |= (rxdid &lt;&lt; QRXFLXP_CNTXT_RXDID_IDX_S) &amp;</div><div class='del'>-		QRXFLXP_CNTXT_RXDID_IDX_M;</div><div class='del'>-</div><div class='del'>-	regval |= (prio &lt;&lt; QRXFLXP_CNTXT_RXDID_PRIO_S) &amp;</div><div class='del'>-		QRXFLXP_CNTXT_RXDID_PRIO_M;</div><div class='add'>+	regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_IDX_M, rxdid);</div><div class='add'>+	regval |= FIELD_PREP(QRXFLXP_CNTXT_RXDID_PRIO_M, prio);</div><div class='ctx'> </div><div class='ctx'> 	if (ena_ts)</div><div class='ctx'> 		/* Enable TimeSync on this queue */</div><div class='hunk'>@@ -2371,6 +2345,9 @@ static int ice_vsi_cfg_tc_lan(struct ice_pf *pf, struct ice_vsi *vsi)</div><div class='ctx'> 		} else {</div><div class='ctx'> 			max_txqs[i] = vsi-&gt;alloc_txq;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		if (vsi-&gt;type == ICE_VSI_PF)</div><div class='add'>+			max_txqs[i] += vsi-&gt;num_xdp_txq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(dev, "vsi-&gt;tc_cfg.ena_tc = %d\n", vsi-&gt;tc_cfg.ena_tc);</div><div class='hunk'>@@ -2447,6 +2424,10 @@ ice_vsi_cfg_def(struct ice_vsi *vsi, struct ice_vsi_cfg_params *params)</div><div class='ctx'> 			goto unroll_vector_base;</div><div class='ctx'> </div><div class='ctx'> 		ice_vsi_map_rings_to_vectors(vsi);</div><div class='add'>+</div><div class='add'>+		/* Associate q_vector rings to napi */</div><div class='add'>+		ice_vsi_set_napi_queues(vsi, true);</div><div class='add'>+</div><div class='ctx'> 		vsi-&gt;stat_offsets_loaded = false;</div><div class='ctx'> </div><div class='ctx'> 		if (ice_is_xdp_ena_vsi(vsi)) {</div><div class='hunk'>@@ -2620,10 +2601,6 @@ void ice_vsi_decfg(struct ice_vsi *vsi)</div><div class='ctx'> 	if (vsi-&gt;type == ICE_VSI_VF &amp;&amp;</div><div class='ctx'> 	    vsi-&gt;agg_node &amp;&amp; vsi-&gt;agg_node-&gt;valid)</div><div class='ctx'> 		vsi-&gt;agg_node-&gt;num_vsis--;</div><div class='del'>-	if (vsi-&gt;agg_node) {</div><div class='del'>-		vsi-&gt;agg_node-&gt;valid = false;</div><div class='del'>-		vsi-&gt;agg_node-&gt;agg_id = 0;</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2927,6 +2904,71 @@ void ice_vsi_dis_irq(struct ice_vsi *vsi)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_queue_set_napi - Set the napi instance for the queue</div><div class='add'>+ * @dev: device to which NAPI and queue belong</div><div class='add'>+ * @queue_index: Index of queue</div><div class='add'>+ * @type: queue type as RX or TX</div><div class='add'>+ * @napi: NAPI context</div><div class='add'>+ * @locked: is the rtnl_lock already held</div><div class='add'>+ *</div><div class='add'>+ * Set the napi instance for the queue</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_queue_set_napi(struct net_device *dev, unsigned int queue_index,</div><div class='add'>+		   enum netdev_queue_type type, struct napi_struct *napi,</div><div class='add'>+		   bool locked)</div><div class='add'>+{</div><div class='add'>+	if (!locked)</div><div class='add'>+		rtnl_lock();</div><div class='add'>+	netif_queue_set_napi(dev, queue_index, type, napi);</div><div class='add'>+	if (!locked)</div><div class='add'>+		rtnl_unlock();</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_q_vector_set_napi_queues - Map queue[s] associated with the napi</div><div class='add'>+ * @q_vector: q_vector pointer</div><div class='add'>+ * @locked: is the rtnl_lock already held</div><div class='add'>+ *</div><div class='add'>+ * Associate the q_vector napi with all the queue[s] on the vector</div><div class='add'>+ */</div><div class='add'>+void ice_q_vector_set_napi_queues(struct ice_q_vector *q_vector, bool locked)</div><div class='add'>+{</div><div class='add'>+	struct ice_rx_ring *rx_ring;</div><div class='add'>+	struct ice_tx_ring *tx_ring;</div><div class='add'>+</div><div class='add'>+	ice_for_each_rx_ring(rx_ring, q_vector-&gt;rx)</div><div class='add'>+		ice_queue_set_napi(q_vector-&gt;vsi-&gt;netdev, rx_ring-&gt;q_index,</div><div class='add'>+				   NETDEV_QUEUE_TYPE_RX, &amp;q_vector-&gt;napi,</div><div class='add'>+				   locked);</div><div class='add'>+</div><div class='add'>+	ice_for_each_tx_ring(tx_ring, q_vector-&gt;tx)</div><div class='add'>+		ice_queue_set_napi(q_vector-&gt;vsi-&gt;netdev, tx_ring-&gt;q_index,</div><div class='add'>+				   NETDEV_QUEUE_TYPE_TX, &amp;q_vector-&gt;napi,</div><div class='add'>+				   locked);</div><div class='add'>+	/* Also set the interrupt number for the NAPI */</div><div class='add'>+	netif_napi_set_irq(&amp;q_vector-&gt;napi, q_vector-&gt;irq.virq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_vsi_set_napi_queues</div><div class='add'>+ * @vsi: VSI pointer</div><div class='add'>+ * @locked: is the rtnl_lock already held</div><div class='add'>+ *</div><div class='add'>+ * Associate queue[s] with napi for all vectors</div><div class='add'>+ */</div><div class='add'>+void ice_vsi_set_napi_queues(struct ice_vsi *vsi, bool locked)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!vsi-&gt;netdev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ice_for_each_q_vector(vsi, i)</div><div class='add'>+		ice_q_vector_set_napi_queues(vsi-&gt;q_vectors[i], locked);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_vsi_release - Delete a VSI and free its resources</div><div class='ctx'>  * @vsi: the VSI being removed</div><div class='ctx'>  *</div><div class='hunk'>@@ -3071,27 +3113,26 @@ ice_vsi_rebuild_set_coalesce(struct ice_vsi *vsi,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_vsi_realloc_stat_arrays - Frees unused stat structures</div><div class='add'>+ * ice_vsi_realloc_stat_arrays - Frees unused stat structures or alloc new ones</div><div class='ctx'>  * @vsi: VSI pointer</div><div class='del'>- * @prev_txq: Number of Tx rings before ring reallocation</div><div class='del'>- * @prev_rxq: Number of Rx rings before ring reallocation</div><div class='ctx'>  */</div><div class='del'>-static void</div><div class='del'>-ice_vsi_realloc_stat_arrays(struct ice_vsi *vsi, int prev_txq, int prev_rxq)</div><div class='add'>+static int</div><div class='add'>+ice_vsi_realloc_stat_arrays(struct ice_vsi *vsi)</div><div class='ctx'> {</div><div class='add'>+	u16 req_txq = vsi-&gt;req_txq ? vsi-&gt;req_txq : vsi-&gt;alloc_txq;</div><div class='add'>+	u16 req_rxq = vsi-&gt;req_rxq ? vsi-&gt;req_rxq : vsi-&gt;alloc_rxq;</div><div class='add'>+	struct ice_ring_stats **tx_ring_stats;</div><div class='add'>+	struct ice_ring_stats **rx_ring_stats;</div><div class='ctx'> 	struct ice_vsi_stats *vsi_stat;</div><div class='ctx'> 	struct ice_pf *pf = vsi-&gt;back;</div><div class='add'>+	u16 prev_txq = vsi-&gt;alloc_txq;</div><div class='add'>+	u16 prev_rxq = vsi-&gt;alloc_rxq;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (!prev_txq || !prev_rxq)</div><div class='del'>-		return;</div><div class='del'>-	if (vsi-&gt;type == ICE_VSI_CHNL)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	vsi_stat = pf-&gt;vsi_stats[vsi-&gt;idx];</div><div class='ctx'> </div><div class='del'>-	if (vsi-&gt;num_txq &lt; prev_txq) {</div><div class='del'>-		for (i = vsi-&gt;num_txq; i &lt; prev_txq; i++) {</div><div class='add'>+	if (req_txq &lt; prev_txq) {</div><div class='add'>+		for (i = req_txq; i &lt; prev_txq; i++) {</div><div class='ctx'> 			if (vsi_stat-&gt;tx_ring_stats[i]) {</div><div class='ctx'> 				kfree_rcu(vsi_stat-&gt;tx_ring_stats[i], rcu);</div><div class='ctx'> 				WRITE_ONCE(vsi_stat-&gt;tx_ring_stats[i], NULL);</div><div class='hunk'>@@ -3099,14 +3140,36 @@ ice_vsi_realloc_stat_arrays(struct ice_vsi *vsi, int prev_txq, int prev_rxq)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (vsi-&gt;num_rxq &lt; prev_rxq) {</div><div class='del'>-		for (i = vsi-&gt;num_rxq; i &lt; prev_rxq; i++) {</div><div class='add'>+	tx_ring_stats = vsi_stat-&gt;rx_ring_stats;</div><div class='add'>+	vsi_stat-&gt;tx_ring_stats =</div><div class='add'>+		krealloc_array(vsi_stat-&gt;tx_ring_stats, req_txq,</div><div class='add'>+			       sizeof(*vsi_stat-&gt;tx_ring_stats),</div><div class='add'>+			       GFP_KERNEL | __GFP_ZERO);</div><div class='add'>+	if (!vsi_stat-&gt;tx_ring_stats) {</div><div class='add'>+		vsi_stat-&gt;tx_ring_stats = tx_ring_stats;</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (req_rxq &lt; prev_rxq) {</div><div class='add'>+		for (i = req_rxq; i &lt; prev_rxq; i++) {</div><div class='ctx'> 			if (vsi_stat-&gt;rx_ring_stats[i]) {</div><div class='ctx'> 				kfree_rcu(vsi_stat-&gt;rx_ring_stats[i], rcu);</div><div class='ctx'> 				WRITE_ONCE(vsi_stat-&gt;rx_ring_stats[i], NULL);</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	rx_ring_stats = vsi_stat-&gt;rx_ring_stats;</div><div class='add'>+	vsi_stat-&gt;rx_ring_stats =</div><div class='add'>+		krealloc_array(vsi_stat-&gt;rx_ring_stats, req_rxq,</div><div class='add'>+			       sizeof(*vsi_stat-&gt;rx_ring_stats),</div><div class='add'>+			       GFP_KERNEL | __GFP_ZERO);</div><div class='add'>+	if (!vsi_stat-&gt;rx_ring_stats) {</div><div class='add'>+		vsi_stat-&gt;rx_ring_stats = rx_ring_stats;</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3123,9 +3186,9 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, u32 vsi_flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_vsi_cfg_params params = {};</div><div class='ctx'> 	struct ice_coalesce_stored *coalesce;</div><div class='del'>-	int ret, prev_txq, prev_rxq;</div><div class='ctx'> 	int prev_num_q_vectors = 0;</div><div class='ctx'> 	struct ice_pf *pf;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (!vsi)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -3144,8 +3207,9 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, u32 vsi_flags)</div><div class='ctx'> </div><div class='ctx'> 	prev_num_q_vectors = ice_vsi_rebuild_get_coalesce(vsi, coalesce);</div><div class='ctx'> </div><div class='del'>-	prev_txq = vsi-&gt;num_txq;</div><div class='del'>-	prev_rxq = vsi-&gt;num_rxq;</div><div class='add'>+	ret = ice_vsi_realloc_stat_arrays(vsi);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto err_vsi_cfg;</div><div class='ctx'> </div><div class='ctx'> 	ice_vsi_decfg(vsi);</div><div class='ctx'> 	ret = ice_vsi_cfg_def(vsi, &amp;params);</div><div class='hunk'>@@ -3163,8 +3227,6 @@ int ice_vsi_rebuild(struct ice_vsi *vsi, u32 vsi_flags)</div><div class='ctx'> 		return ice_schedule_reset(pf, ICE_RESET_PFR);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ice_vsi_realloc_stat_arrays(vsi, prev_txq, prev_rxq);</div><div class='del'>-</div><div class='ctx'> 	ice_vsi_rebuild_set_coalesce(vsi, coalesce, prev_num_q_vectors);</div><div class='ctx'> 	kfree(coalesce);</div><div class='ctx'> </div><div class='hunk'>@@ -3316,9 +3378,8 @@ ice_vsi_setup_q_map_mqprio(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt,</div><div class='ctx'> 	vsi-&gt;tc_cfg.ena_tc = ena_tc ? ena_tc : 1;</div><div class='ctx'> </div><div class='ctx'> 	pow = order_base_2(tc0_qcount);</div><div class='del'>-	qmap = ((tc0_offset &lt;&lt; ICE_AQ_VSI_TC_Q_OFFSET_S) &amp;</div><div class='del'>-		ICE_AQ_VSI_TC_Q_OFFSET_M) |</div><div class='del'>-		((pow &lt;&lt; ICE_AQ_VSI_TC_Q_NUM_S) &amp; ICE_AQ_VSI_TC_Q_NUM_M);</div><div class='add'>+	qmap = FIELD_PREP(ICE_AQ_VSI_TC_Q_OFFSET_M, tc0_offset);</div><div class='add'>+	qmap |= FIELD_PREP(ICE_AQ_VSI_TC_Q_NUM_M, pow);</div><div class='ctx'> </div><div class='ctx'> 	ice_for_each_traffic_class(i) {</div><div class='ctx'> 		if (!(vsi-&gt;tc_cfg.ena_tc &amp; BIT(i))) {</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_lib.h b/drivers/net/ethernet/intel/ice/ice_lib.h<br/>index f24f5d1e6f9c..71bd27244941 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_lib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_lib.h</a></div><div class='hunk'>@@ -91,6 +91,10 @@ void ice_vsi_cfg_netdev_tc(struct ice_vsi *vsi, u8 ena_tc);</div><div class='ctx'> struct ice_vsi *</div><div class='ctx'> ice_vsi_setup(struct ice_pf *pf, struct ice_vsi_cfg_params *params);</div><div class='ctx'> </div><div class='add'>+void ice_q_vector_set_napi_queues(struct ice_q_vector *q_vector, bool locked);</div><div class='add'>+</div><div class='add'>+void ice_vsi_set_napi_queues(struct ice_vsi *vsi, bool locked);</div><div class='add'>+</div><div class='ctx'> int ice_vsi_release(struct ice_vsi *vsi);</div><div class='ctx'> </div><div class='ctx'> void ice_vsi_close(struct ice_vsi *vsi);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c<br/>index fb9c93f37e84..dd4a9bc0dfdc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_main.c</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include "ice_dcb_lib.h"</div><div class='ctx'> #include "ice_dcb_nl.h"</div><div class='ctx'> #include "ice_devlink.h"</div><div class='add'>+#include "ice_hwmon.h"</div><div class='ctx'> /* Including ice_trace.h with CREATE_TRACE_POINTS defined will generate the</div><div class='ctx'>  * ice tracepoint functions. This must be done exactly once across the</div><div class='ctx'>  * ice driver.</div><div class='hunk'>@@ -979,7 +980,7 @@ static void ice_set_dflt_mib(struct ice_pf *pf)</div><div class='ctx'> 	 * Octets 13 - 20 are TSA values - leave as zeros</div><div class='ctx'> 	 */</div><div class='ctx'> 	buf[5] = 0x64;</div><div class='del'>-	len = (typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S;</div><div class='add'>+	len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 	offset += len + 2;</div><div class='ctx'> 	tlv = (struct ice_lldp_org_tlv *)</div><div class='ctx'> 		((char *)tlv + sizeof(tlv-&gt;typelen) + len);</div><div class='hunk'>@@ -1013,7 +1014,7 @@ static void ice_set_dflt_mib(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	/* Octet 1 left as all zeros - PFC disabled */</div><div class='ctx'> 	buf[0] = 0x08;</div><div class='del'>-	len = (typelen &amp; ICE_LLDP_TLV_LEN_M) &gt;&gt; ICE_LLDP_TLV_LEN_S;</div><div class='add'>+	len = FIELD_GET(ICE_LLDP_TLV_LEN_M, typelen);</div><div class='ctx'> 	offset += len + 2;</div><div class='ctx'> </div><div class='ctx'> 	if (ice_aq_set_lldp_mib(hw, mib_type, (void *)lldpmib, offset, NULL))</div><div class='hunk'>@@ -1252,6 +1253,32 @@ ice_handle_link_event(struct ice_pf *pf, struct ice_rq_event_info *event)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_get_fwlog_data - copy the FW log data from ARQ event</div><div class='add'>+ * @pf: PF that the FW log event is associated with</div><div class='add'>+ * @event: event structure containing FW log data</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_get_fwlog_data(struct ice_pf *pf, struct ice_rq_event_info *event)</div><div class='add'>+{</div><div class='add'>+	struct ice_fwlog_data *fwlog;</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+</div><div class='add'>+	fwlog = &amp;hw-&gt;fwlog_ring.rings[hw-&gt;fwlog_ring.tail];</div><div class='add'>+</div><div class='add'>+	memset(fwlog-&gt;data, 0, PAGE_SIZE);</div><div class='add'>+	fwlog-&gt;data_size = le16_to_cpu(event-&gt;desc.datalen);</div><div class='add'>+</div><div class='add'>+	memcpy(fwlog-&gt;data, event-&gt;msg_buf, fwlog-&gt;data_size);</div><div class='add'>+	ice_fwlog_ring_increment(&amp;hw-&gt;fwlog_ring.tail, hw-&gt;fwlog_ring.size);</div><div class='add'>+</div><div class='add'>+	if (ice_fwlog_ring_full(&amp;hw-&gt;fwlog_ring)) {</div><div class='add'>+		/* the rings are full so bump the head to create room */</div><div class='add'>+		ice_fwlog_ring_increment(&amp;hw-&gt;fwlog_ring.head,</div><div class='add'>+					 hw-&gt;fwlog_ring.size);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_aq_prep_for_event - Prepare to wait for an AdminQ event from firmware</div><div class='ctx'>  * @pf: pointer to the PF private structure</div><div class='ctx'>  * @task: intermediate helper storage and identifier for waiting</div><div class='hunk'>@@ -1532,8 +1559,8 @@ static int __ice_clean_ctrlq(struct ice_pf *pf, enum ice_ctl_q q_type)</div><div class='ctx'> </div><div class='ctx'> 			ice_vc_process_vf_msg(pf, &amp;event, &amp;data);</div><div class='ctx'> 			break;</div><div class='del'>-		case ice_aqc_opc_fw_logging:</div><div class='del'>-			ice_output_fw_log(hw, &amp;event.desc, event.msg_buf);</div><div class='add'>+		case ice_aqc_opc_fw_logs_event:</div><div class='add'>+			ice_get_fwlog_data(pf, &amp;event);</div><div class='ctx'> 			break;</div><div class='ctx'> 		case ice_aqc_opc_lldp_set_mib_change:</div><div class='ctx'> 			ice_dcb_process_lldp_set_mib_change(pf, &amp;event);</div><div class='hunk'>@@ -1744,14 +1771,10 @@ static void ice_handle_mdd_event(struct ice_pf *pf)</div><div class='ctx'> 	/* find what triggered an MDD event */</div><div class='ctx'> 	reg = rd32(hw, GL_MDET_TX_PQM);</div><div class='ctx'> 	if (reg &amp; GL_MDET_TX_PQM_VALID_M) {</div><div class='del'>-		u8 pf_num = (reg &amp; GL_MDET_TX_PQM_PF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_PQM_PF_NUM_S;</div><div class='del'>-		u16 vf_num = (reg &amp; GL_MDET_TX_PQM_VF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_PQM_VF_NUM_S;</div><div class='del'>-		u8 event = (reg &amp; GL_MDET_TX_PQM_MAL_TYPE_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_PQM_MAL_TYPE_S;</div><div class='del'>-		u16 queue = ((reg &amp; GL_MDET_TX_PQM_QNUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_PQM_QNUM_S);</div><div class='add'>+		u8 pf_num = FIELD_GET(GL_MDET_TX_PQM_PF_NUM_M, reg);</div><div class='add'>+		u16 vf_num = FIELD_GET(GL_MDET_TX_PQM_VF_NUM_M, reg);</div><div class='add'>+		u8 event = FIELD_GET(GL_MDET_TX_PQM_MAL_TYPE_M, reg);</div><div class='add'>+		u16 queue = FIELD_GET(GL_MDET_TX_PQM_QNUM_M, reg);</div><div class='ctx'> </div><div class='ctx'> 		if (netif_msg_tx_err(pf))</div><div class='ctx'> 			dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",</div><div class='hunk'>@@ -1761,14 +1784,10 @@ static void ice_handle_mdd_event(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, GL_MDET_TX_TCLAN_BY_MAC(hw));</div><div class='ctx'> 	if (reg &amp; GL_MDET_TX_TCLAN_VALID_M) {</div><div class='del'>-		u8 pf_num = (reg &amp; GL_MDET_TX_TCLAN_PF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_TCLAN_PF_NUM_S;</div><div class='del'>-		u16 vf_num = (reg &amp; GL_MDET_TX_TCLAN_VF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_TCLAN_VF_NUM_S;</div><div class='del'>-		u8 event = (reg &amp; GL_MDET_TX_TCLAN_MAL_TYPE_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_TCLAN_MAL_TYPE_S;</div><div class='del'>-		u16 queue = ((reg &amp; GL_MDET_TX_TCLAN_QNUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_TX_TCLAN_QNUM_S);</div><div class='add'>+		u8 pf_num = FIELD_GET(GL_MDET_TX_TCLAN_PF_NUM_M, reg);</div><div class='add'>+		u16 vf_num = FIELD_GET(GL_MDET_TX_TCLAN_VF_NUM_M, reg);</div><div class='add'>+		u8 event = FIELD_GET(GL_MDET_TX_TCLAN_MAL_TYPE_M, reg);</div><div class='add'>+		u16 queue = FIELD_GET(GL_MDET_TX_TCLAN_QNUM_M, reg);</div><div class='ctx'> </div><div class='ctx'> 		if (netif_msg_tx_err(pf))</div><div class='ctx'> 			dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",</div><div class='hunk'>@@ -1778,14 +1797,10 @@ static void ice_handle_mdd_event(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(hw, GL_MDET_RX);</div><div class='ctx'> 	if (reg &amp; GL_MDET_RX_VALID_M) {</div><div class='del'>-		u8 pf_num = (reg &amp; GL_MDET_RX_PF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_RX_PF_NUM_S;</div><div class='del'>-		u16 vf_num = (reg &amp; GL_MDET_RX_VF_NUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_RX_VF_NUM_S;</div><div class='del'>-		u8 event = (reg &amp; GL_MDET_RX_MAL_TYPE_M) &gt;&gt;</div><div class='del'>-				GL_MDET_RX_MAL_TYPE_S;</div><div class='del'>-		u16 queue = ((reg &amp; GL_MDET_RX_QNUM_M) &gt;&gt;</div><div class='del'>-				GL_MDET_RX_QNUM_S);</div><div class='add'>+		u8 pf_num = FIELD_GET(GL_MDET_RX_PF_NUM_M, reg);</div><div class='add'>+		u16 vf_num = FIELD_GET(GL_MDET_RX_VF_NUM_M, reg);</div><div class='add'>+		u8 event = FIELD_GET(GL_MDET_RX_MAL_TYPE_M, reg);</div><div class='add'>+		u16 queue = FIELD_GET(GL_MDET_RX_QNUM_M, reg);</div><div class='ctx'> </div><div class='ctx'> 		if (netif_msg_rx_err(pf))</div><div class='ctx'> 			dev_info(dev, "Malicious Driver Detection event %d on RX queue %d PF# %d VF# %d\n",</div><div class='hunk'>@@ -2146,7 +2161,7 @@ static int ice_configure_phy(struct ice_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 	/* Ensure we have media as we cannot configure a medialess port */</div><div class='ctx'> 	if (!(phy-&gt;link_info.link_info &amp; ICE_AQ_MEDIA_AVAILABLE))</div><div class='del'>-		return -EPERM;</div><div class='add'>+		return -ENOMEDIUM;</div><div class='ctx'> </div><div class='ctx'> 	ice_print_topo_conflict(vsi);</div><div class='ctx'> </div><div class='hunk'>@@ -3031,6 +3046,7 @@ static int ice_xdp(struct net_device *dev, struct netdev_bpf *xdp)</div><div class='ctx'> static void ice_ena_misc_vector(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	u32 pf_intr_start_offset;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable anti-spoof detection interrupt to prevent spurious event</div><div class='hunk'>@@ -3059,6 +3075,47 @@ static void ice_ena_misc_vector(struct ice_pf *pf)</div><div class='ctx'> 	/* SW_ITR_IDX = 0, but don't change INTENA */</div><div class='ctx'> 	wr32(hw, GLINT_DYN_CTL(pf-&gt;oicr_irq.index),</div><div class='ctx'> 	     GLINT_DYN_CTL_SW_ITR_INDX_M | GLINT_DYN_CTL_INTENA_MSK_M);</div><div class='add'>+</div><div class='add'>+	if (!pf-&gt;hw.dev_caps.ts_dev_info.ts_ll_int_read)</div><div class='add'>+		return;</div><div class='add'>+	pf_intr_start_offset = rd32(hw, PFINT_ALLOC) &amp; PFINT_ALLOC_FIRST;</div><div class='add'>+	wr32(hw, GLINT_DYN_CTL(pf-&gt;ll_ts_irq.index + pf_intr_start_offset),</div><div class='add'>+	     GLINT_DYN_CTL_SW_ITR_INDX_M | GLINT_DYN_CTL_INTENA_MSK_M);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_ll_ts_intr - ll_ts interrupt handler</div><div class='add'>+ * @irq: interrupt number</div><div class='add'>+ * @data: pointer to a q_vector</div><div class='add'>+ */</div><div class='add'>+static irqreturn_t ice_ll_ts_intr(int __always_unused irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct ice_pf *pf = data;</div><div class='add'>+	u32 pf_intr_start_offset;</div><div class='add'>+	struct ice_ptp_tx *tx;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	struct ice_hw *hw;</div><div class='add'>+	u32 val;</div><div class='add'>+	u8 idx;</div><div class='add'>+</div><div class='add'>+	hw = &amp;pf-&gt;hw;</div><div class='add'>+	tx = &amp;pf-&gt;ptp.port.tx;</div><div class='add'>+	spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='add'>+	ice_ptp_complete_tx_single_tstamp(tx);</div><div class='add'>+</div><div class='add'>+	idx = find_next_bit_wrap(tx-&gt;in_use, tx-&gt;len,</div><div class='add'>+				 tx-&gt;last_ll_ts_idx_read + 1);</div><div class='add'>+	if (idx != tx-&gt;len)</div><div class='add'>+		ice_ptp_req_tx_single_tstamp(tx, idx);</div><div class='add'>+	spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='add'>+</div><div class='add'>+	val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |</div><div class='add'>+	      (ICE_ITR_NONE &lt;&lt; GLINT_DYN_CTL_ITR_INDX_S);</div><div class='add'>+	pf_intr_start_offset = rd32(hw, PFINT_ALLOC) &amp; PFINT_ALLOC_FIRST;</div><div class='add'>+	wr32(hw, GLINT_DYN_CTL(pf-&gt;ll_ts_irq.index + pf_intr_start_offset),</div><div class='add'>+	     val);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3069,6 +3126,7 @@ static void ice_ena_misc_vector(struct ice_pf *pf)</div><div class='ctx'> static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_pf *pf = (struct ice_pf *)data;</div><div class='add'>+	irqreturn_t ret = IRQ_HANDLED;</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	u32 oicr, ena_mask;</div><div class='hunk'>@@ -3108,8 +3166,8 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)</div><div class='ctx'> </div><div class='ctx'> 		/* we have a reset warning */</div><div class='ctx'> 		ena_mask &amp;= ~PFINT_OICR_GRST_M;</div><div class='del'>-		reset = (rd32(hw, GLGEN_RSTAT) &amp; GLGEN_RSTAT_RESET_TYPE_M) &gt;&gt;</div><div class='del'>-			GLGEN_RSTAT_RESET_TYPE_S;</div><div class='add'>+		reset = FIELD_GET(GLGEN_RSTAT_RESET_TYPE_M,</div><div class='add'>+				  rd32(hw, GLGEN_RSTAT));</div><div class='ctx'> </div><div class='ctx'> 		if (reset == ICE_RESET_CORER)</div><div class='ctx'> 			pf-&gt;corer_count++;</div><div class='hunk'>@@ -3150,8 +3208,22 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)</div><div class='ctx'> </div><div class='ctx'> 	if (oicr &amp; PFINT_OICR_TSYN_TX_M) {</div><div class='ctx'> 		ena_mask &amp;= ~PFINT_OICR_TSYN_TX_M;</div><div class='del'>-		if (!hw-&gt;reset_ongoing &amp;&amp; ice_ptp_pf_handles_tx_interrupt(pf))</div><div class='add'>+		if (ice_pf_state_is_nominal(pf) &amp;&amp;</div><div class='add'>+		    pf-&gt;hw.dev_caps.ts_dev_info.ts_ll_int_read) {</div><div class='add'>+			struct ice_ptp_tx *tx = &amp;pf-&gt;ptp.port.tx;</div><div class='add'>+			unsigned long flags;</div><div class='add'>+			u8 idx;</div><div class='add'>+</div><div class='add'>+			spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='add'>+			idx = find_next_bit_wrap(tx-&gt;in_use, tx-&gt;len,</div><div class='add'>+						 tx-&gt;last_ll_ts_idx_read + 1);</div><div class='add'>+			if (idx != tx-&gt;len)</div><div class='add'>+				ice_ptp_req_tx_single_tstamp(tx, idx);</div><div class='add'>+			spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='add'>+		} else if (ice_ptp_pf_handles_tx_interrupt(pf)) {</div><div class='ctx'> 			set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf-&gt;misc_thread);</div><div class='add'>+			ret = IRQ_WAKE_THREAD;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (oicr &amp; PFINT_OICR_TSYN_EVNT_M) {</div><div class='hunk'>@@ -3167,7 +3239,7 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)</div><div class='ctx'> 					       GLTSYN_STAT_EVENT1_M |</div><div class='ctx'> 					       GLTSYN_STAT_EVENT2_M);</div><div class='ctx'> </div><div class='del'>-			set_bit(ICE_MISC_THREAD_EXTTS_EVENT, pf-&gt;misc_thread);</div><div class='add'>+			ice_ptp_extts_event(pf);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3190,8 +3262,11 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)</div><div class='ctx'> 			set_bit(ICE_PFR_REQ, pf-&gt;state);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='add'>+	ice_service_task_schedule(pf);</div><div class='add'>+	if (ret == IRQ_HANDLED)</div><div class='add'>+		ice_irq_dynamic_ena(hw, NULL, NULL);</div><div class='ctx'> </div><div class='del'>-	return IRQ_WAKE_THREAD;</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3207,12 +3282,7 @@ static irqreturn_t ice_misc_intr_thread_fn(int __always_unused irq, void *data)</div><div class='ctx'> 	hw = &amp;pf-&gt;hw;</div><div class='ctx'> </div><div class='ctx'> 	if (ice_is_reset_in_progress(pf-&gt;state))</div><div class='del'>-		return IRQ_HANDLED;</div><div class='del'>-</div><div class='del'>-	ice_service_task_schedule(pf);</div><div class='del'>-</div><div class='del'>-	if (test_and_clear_bit(ICE_MISC_THREAD_EXTTS_EVENT, pf-&gt;misc_thread))</div><div class='del'>-		ice_ptp_extts_event(pf);</div><div class='add'>+		goto skip_irq;</div><div class='ctx'> </div><div class='ctx'> 	if (test_and_clear_bit(ICE_MISC_THREAD_TX_TSTAMP, pf-&gt;misc_thread)) {</div><div class='ctx'> 		/* Process outstanding Tx timestamps. If there is more work,</div><div class='hunk'>@@ -3224,6 +3294,7 @@ static irqreturn_t ice_misc_intr_thread_fn(int __always_unused irq, void *data)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+skip_irq:</div><div class='ctx'> 	ice_irq_dynamic_ena(hw, NULL, NULL);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='hunk'>@@ -3254,6 +3325,20 @@ static void ice_dis_ctrlq_interrupts(struct ice_hw *hw)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_free_irq_msix_ll_ts- Unroll ll_ts vector setup</div><div class='add'>+ * @pf: board private structure</div><div class='add'>+ */</div><div class='add'>+static void ice_free_irq_msix_ll_ts(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	int irq_num = pf-&gt;ll_ts_irq.virq;</div><div class='add'>+</div><div class='add'>+	synchronize_irq(irq_num);</div><div class='add'>+	devm_free_irq(ice_pf_to_dev(pf), irq_num, pf);</div><div class='add'>+</div><div class='add'>+	ice_free_irq(pf, pf-&gt;ll_ts_irq);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_free_irq_msix_misc - Unroll misc vector setup</div><div class='ctx'>  * @pf: board private structure</div><div class='ctx'>  */</div><div class='hunk'>@@ -3272,6 +3357,8 @@ static void ice_free_irq_msix_misc(struct ice_pf *pf)</div><div class='ctx'> 	devm_free_irq(ice_pf_to_dev(pf), misc_irq_num, pf);</div><div class='ctx'> </div><div class='ctx'> 	ice_free_irq(pf, pf-&gt;oicr_irq);</div><div class='add'>+	if (pf-&gt;hw.dev_caps.ts_dev_info.ts_ll_int_read)</div><div class='add'>+		ice_free_irq_msix_ll_ts(pf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3297,10 +3384,12 @@ static void ice_ena_ctrlq_interrupts(struct ice_hw *hw, u16 reg_idx)</div><div class='ctx'> 	       PFINT_MBX_CTL_CAUSE_ENA_M);</div><div class='ctx'> 	wr32(hw, PFINT_MBX_CTL, val);</div><div class='ctx'> </div><div class='del'>-	/* This enables Sideband queue Interrupt causes */</div><div class='del'>-	val = ((reg_idx &amp; PFINT_SB_CTL_MSIX_INDX_M) |</div><div class='del'>-	       PFINT_SB_CTL_CAUSE_ENA_M);</div><div class='del'>-	wr32(hw, PFINT_SB_CTL, val);</div><div class='add'>+	if (!hw-&gt;dev_caps.ts_dev_info.ts_ll_int_read) {</div><div class='add'>+		/* enable Sideband queue Interrupt causes */</div><div class='add'>+		val = ((reg_idx &amp; PFINT_SB_CTL_MSIX_INDX_M) |</div><div class='add'>+		       PFINT_SB_CTL_CAUSE_ENA_M);</div><div class='add'>+		wr32(hw, PFINT_SB_CTL, val);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ice_flush(hw);</div><div class='ctx'> }</div><div class='hunk'>@@ -3317,13 +3406,17 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = ice_pf_to_dev(pf);</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='del'>-	struct msi_map oicr_irq;</div><div class='add'>+	u32 pf_intr_start_offset;</div><div class='add'>+	struct msi_map irq;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!pf-&gt;int_name[0])</div><div class='ctx'> 		snprintf(pf-&gt;int_name, sizeof(pf-&gt;int_name) - 1, "%s-%s:misc",</div><div class='ctx'> 			 dev_driver_string(dev), dev_name(dev));</div><div class='ctx'> </div><div class='add'>+	if (!pf-&gt;int_name_ll_ts[0])</div><div class='add'>+		snprintf(pf-&gt;int_name_ll_ts, sizeof(pf-&gt;int_name_ll_ts) - 1,</div><div class='add'>+			 "%s-%s:ll_ts", dev_driver_string(dev), dev_name(dev));</div><div class='ctx'> 	/* Do not request IRQ but do enable OICR interrupt since settings are</div><div class='ctx'> 	 * lost during reset. Note that this function is called only during</div><div class='ctx'> 	 * rebuild path and not while reset is in progress.</div><div class='hunk'>@@ -3332,11 +3425,11 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)</div><div class='ctx'> 		goto skip_req_irq;</div><div class='ctx'> </div><div class='ctx'> 	/* reserve one vector in irq_tracker for misc interrupts */</div><div class='del'>-	oicr_irq = ice_alloc_irq(pf, false);</div><div class='del'>-	if (oicr_irq.index &lt; 0)</div><div class='del'>-		return oicr_irq.index;</div><div class='add'>+	irq = ice_alloc_irq(pf, false);</div><div class='add'>+	if (irq.index &lt; 0)</div><div class='add'>+		return irq.index;</div><div class='ctx'> </div><div class='del'>-	pf-&gt;oicr_irq = oicr_irq;</div><div class='add'>+	pf-&gt;oicr_irq = irq;</div><div class='ctx'> 	err = devm_request_threaded_irq(dev, pf-&gt;oicr_irq.virq, ice_misc_intr,</div><div class='ctx'> 					ice_misc_intr_thread_fn, 0,</div><div class='ctx'> 					pf-&gt;int_name, pf);</div><div class='hunk'>@@ -3347,10 +3440,34 @@ static int ice_req_irq_msix_misc(struct ice_pf *pf)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* reserve one vector in irq_tracker for ll_ts interrupt */</div><div class='add'>+	if (!pf-&gt;hw.dev_caps.ts_dev_info.ts_ll_int_read)</div><div class='add'>+		goto skip_req_irq;</div><div class='add'>+</div><div class='add'>+	irq = ice_alloc_irq(pf, false);</div><div class='add'>+	if (irq.index &lt; 0)</div><div class='add'>+		return irq.index;</div><div class='add'>+</div><div class='add'>+	pf-&gt;ll_ts_irq = irq;</div><div class='add'>+	err = devm_request_irq(dev, pf-&gt;ll_ts_irq.virq, ice_ll_ts_intr, 0,</div><div class='add'>+			       pf-&gt;int_name_ll_ts, pf);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(dev, "devm_request_irq for %s failed: %d\n",</div><div class='add'>+			pf-&gt;int_name_ll_ts, err);</div><div class='add'>+		ice_free_irq(pf, pf-&gt;ll_ts_irq);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> skip_req_irq:</div><div class='ctx'> 	ice_ena_misc_vector(pf);</div><div class='ctx'> </div><div class='ctx'> 	ice_ena_ctrlq_interrupts(hw, pf-&gt;oicr_irq.index);</div><div class='add'>+	/* This enables LL TS interrupt */</div><div class='add'>+	pf_intr_start_offset = rd32(hw, PFINT_ALLOC) &amp; PFINT_ALLOC_FIRST;</div><div class='add'>+	if (pf-&gt;hw.dev_caps.ts_dev_info.ts_ll_int_read)</div><div class='add'>+		wr32(hw, PFINT_SB_CTL,</div><div class='add'>+		     ((pf-&gt;ll_ts_irq.index + pf_intr_start_offset) &amp;</div><div class='add'>+		      PFINT_SB_CTL_MSIX_INDX_M) | PFINT_SB_CTL_CAUSE_ENA_M);</div><div class='ctx'> 	wr32(hw, GLINT_ITR(ICE_RX_ITR, pf-&gt;oicr_irq.index),</div><div class='ctx'> 	     ITR_REG_ALIGN(ICE_ITR_8K) &gt;&gt; ICE_ITR_GRAN_S);</div><div class='ctx'> </div><div class='hunk'>@@ -3375,9 +3492,11 @@ static void ice_napi_add(struct ice_vsi *vsi)</div><div class='ctx'> 	if (!vsi-&gt;netdev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	ice_for_each_q_vector(vsi, v_idx)</div><div class='add'>+	ice_for_each_q_vector(vsi, v_idx) {</div><div class='ctx'> 		netif_napi_add(vsi-&gt;netdev, &amp;vsi-&gt;q_vectors[v_idx]-&gt;napi,</div><div class='ctx'> 			       ice_napi_poll);</div><div class='add'>+		ice_q_vector_set_napi_queues(vsi-&gt;q_vectors[v_idx], false);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3397,6 +3516,7 @@ static void ice_set_ops(struct ice_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;netdev_ops = &amp;ice_netdev_ops;</div><div class='ctx'> 	netdev-&gt;udp_tunnel_nic_info = &amp;pf-&gt;hw.udp_tunnel_nic;</div><div class='add'>+	netdev-&gt;xdp_metadata_ops = &amp;ice_xdp_md_ops;</div><div class='ctx'> 	ice_set_ethtool_ops(netdev);</div><div class='ctx'> </div><div class='ctx'> 	if (vsi-&gt;type != ICE_VSI_PF)</div><div class='hunk'>@@ -4361,6 +4481,19 @@ static void ice_print_wake_reason(struct ice_pf *pf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_pf_fwlog_update_module - update 1 module</div><div class='add'>+ * @pf: pointer to the PF struct</div><div class='add'>+ * @log_level: log_level to use for the @module</div><div class='add'>+ * @module: module to update</div><div class='add'>+ */</div><div class='add'>+void ice_pf_fwlog_update_module(struct ice_pf *pf, int log_level, int module)</div><div class='add'>+{</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+</div><div class='add'>+	hw-&gt;fwlog_cfg.module_entries[module].log_level = log_level;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_register_netdev - register netdev</div><div class='ctx'>  * @vsi: pointer to the VSI struct</div><div class='ctx'>  */</div><div class='hunk'>@@ -4685,6 +4818,8 @@ static void ice_init_features(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	if (ice_init_lag(pf))</div><div class='ctx'> 		dev_warn(dev, "Failed to init link aggregation support\n");</div><div class='add'>+</div><div class='add'>+	ice_hwmon_init(pf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ice_deinit_features(struct ice_pf *pf)</div><div class='hunk'>@@ -4702,6 +4837,8 @@ static void ice_deinit_features(struct ice_pf *pf)</div><div class='ctx'> 		ice_ptp_release(pf);</div><div class='ctx'> 	if (test_bit(ICE_FLAG_DPLL, pf-&gt;flags))</div><div class='ctx'> 		ice_dpll_deinit(pf);</div><div class='add'>+	if (pf-&gt;eswitch_mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)</div><div class='add'>+		xa_destroy(&amp;pf-&gt;eswitch.reprs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ice_init_wakeup(struct ice_pf *pf)</div><div class='hunk'>@@ -5203,11 +5340,15 @@ static void ice_remove(struct pci_dev *pdev)</div><div class='ctx'> 		msleep(100);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ice_debugfs_exit();</div><div class='add'>+</div><div class='ctx'> 	if (test_bit(ICE_FLAG_SRIOV_ENA, pf-&gt;flags)) {</div><div class='ctx'> 		set_bit(ICE_VF_RESETS_DISABLED, pf-&gt;state);</div><div class='ctx'> 		ice_free_vfs(pf);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ice_hwmon_exit(pf);</div><div class='add'>+</div><div class='ctx'> 	ice_service_task_stop(pf);</div><div class='ctx'> 	ice_aq_cancel_waiting_tasks(pf);</div><div class='ctx'> 	set_bit(ICE_DOWN, pf-&gt;state);</div><div class='hunk'>@@ -5672,6 +5813,8 @@ static int __init ice_module_init(void)</div><div class='ctx'> 		goto err_dest_wq;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ice_debugfs_init();</div><div class='add'>+</div><div class='ctx'> 	status = pci_register_driver(&amp;ice_driver);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		pr_err("failed to register PCI driver, err %d\n", status);</div><div class='hunk'>@@ -5682,6 +5825,7 @@ static int __init ice_module_init(void)</div><div class='ctx'> </div><div class='ctx'> err_dest_lag_wq:</div><div class='ctx'> 	destroy_workqueue(ice_lag_wq);</div><div class='add'>+	ice_debugfs_exit();</div><div class='ctx'> err_dest_wq:</div><div class='ctx'> 	destroy_workqueue(ice_wq);</div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -6041,6 +6185,23 @@ ice_fix_features(struct net_device *netdev, netdev_features_t features)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_set_rx_rings_vlan_proto - update rings with new stripped VLAN proto</div><div class='add'>+ * @vsi: PF's VSI</div><div class='add'>+ * @vlan_ethertype: VLAN ethertype (802.1Q or 802.1ad) in network byte order</div><div class='add'>+ *</div><div class='add'>+ * Store current stripped VLAN proto in ring packet context,</div><div class='add'>+ * so it can be accessed more efficiently by packet processing code.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_set_rx_rings_vlan_proto(struct ice_vsi *vsi, __be16 vlan_ethertype)</div><div class='add'>+{</div><div class='add'>+	u16 i;</div><div class='add'>+</div><div class='add'>+	ice_for_each_alloc_rxq(vsi, i)</div><div class='add'>+		vsi-&gt;rx_rings[i]-&gt;pkt_ctx.vlan_proto = vlan_ethertype;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_set_vlan_offload_features - set VLAN offload features for the PF VSI</div><div class='ctx'>  * @vsi: PF's VSI</div><div class='ctx'>  * @features: features used to determine VLAN offload settings</div><div class='hunk'>@@ -6082,6 +6243,9 @@ ice_set_vlan_offload_features(struct ice_vsi *vsi, netdev_features_t features)</div><div class='ctx'> 	if (strip_err || insert_err)</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> </div><div class='add'>+	ice_set_rx_rings_vlan_proto(vsi, enable_stripping ?</div><div class='add'>+				    htons(vlan_ethertype) : 0);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6670,13 +6834,11 @@ void ice_update_vsi_stats(struct ice_vsi *vsi)</div><div class='ctx'> 		cur_ns-&gt;rx_crc_errors = pf-&gt;stats.crc_errors;</div><div class='ctx'> 		cur_ns-&gt;rx_errors = pf-&gt;stats.crc_errors +</div><div class='ctx'> 				    pf-&gt;stats.illegal_bytes +</div><div class='del'>-				    pf-&gt;stats.rx_len_errors +</div><div class='ctx'> 				    pf-&gt;stats.rx_undersize +</div><div class='ctx'> 				    pf-&gt;hw_csum_rx_error +</div><div class='ctx'> 				    pf-&gt;stats.rx_jabber +</div><div class='ctx'> 				    pf-&gt;stats.rx_fragments +</div><div class='ctx'> 				    pf-&gt;stats.rx_oversize;</div><div class='del'>-		cur_ns-&gt;rx_length_errors = pf-&gt;stats.rx_len_errors;</div><div class='ctx'> 		/* record drops from the port level */</div><div class='ctx'> 		cur_ns-&gt;rx_missed_errors = pf-&gt;stats.eth.rx_discards;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -6816,9 +6978,6 @@ void ice_update_pf_stats(struct ice_pf *pf)</div><div class='ctx'> 			  &amp;prev_ps-&gt;mac_remote_faults,</div><div class='ctx'> 			  &amp;cur_ps-&gt;mac_remote_faults);</div><div class='ctx'> </div><div class='del'>-	ice_stat_update32(hw, GLPRT_RLEC(port), pf-&gt;stat_prev_loaded,</div><div class='del'>-			  &amp;prev_ps-&gt;rx_len_errors, &amp;cur_ps-&gt;rx_len_errors);</div><div class='del'>-</div><div class='ctx'> 	ice_stat_update32(hw, GLPRT_RUC(port), pf-&gt;stat_prev_loaded,</div><div class='ctx'> 			  &amp;prev_ps-&gt;rx_undersize, &amp;cur_ps-&gt;rx_undersize);</div><div class='ctx'> </div><div class='hunk'>@@ -7401,9 +7560,9 @@ static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)</div><div class='ctx'> 		goto err_vsi_rebuild;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_vsi_rebuild_by_type(pf, ICE_VSI_SWITCHDEV_CTRL);</div><div class='add'>+	err = ice_eswitch_rebuild(pf);</div><div class='ctx'> 	if (err) {</div><div class='del'>-		dev_err(dev, "Switchdev CTRL VSI rebuild failed: %d\n", err);</div><div class='add'>+		dev_err(dev, "Switchdev rebuild failed: %d\n", err);</div><div class='ctx'> 		goto err_vsi_rebuild;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -7704,6 +7863,59 @@ int ice_get_rss_key(struct ice_vsi *vsi, u8 *seed)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_set_rss_hfunc - Set RSS HASH function</div><div class='add'>+ * @vsi: Pointer to VSI structure</div><div class='add'>+ * @hfunc: hash function (ICE_AQ_VSI_Q_OPT_RSS_*)</div><div class='add'>+ *</div><div class='add'>+ * Returns 0 on success, negative on failure</div><div class='add'>+ */</div><div class='add'>+int ice_set_rss_hfunc(struct ice_vsi *vsi, u8 hfunc)</div><div class='add'>+{</div><div class='add'>+	struct ice_hw *hw = &amp;vsi-&gt;back-&gt;hw;</div><div class='add'>+	struct ice_vsi_ctx *ctx;</div><div class='add'>+	bool symm;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (hfunc == vsi-&gt;rss_hfunc)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (hfunc != ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ &amp;&amp;</div><div class='add'>+	    hfunc != ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);</div><div class='add'>+	if (!ctx)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ctx-&gt;info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_Q_OPT_VALID);</div><div class='add'>+	ctx-&gt;info.q_opt_rss = vsi-&gt;info.q_opt_rss;</div><div class='add'>+	ctx-&gt;info.q_opt_rss &amp;= ~ICE_AQ_VSI_Q_OPT_RSS_HASH_M;</div><div class='add'>+	ctx-&gt;info.q_opt_rss |=</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_Q_OPT_RSS_HASH_M, hfunc);</div><div class='add'>+	ctx-&gt;info.q_opt_tc = vsi-&gt;info.q_opt_tc;</div><div class='add'>+	ctx-&gt;info.q_opt_flags = vsi-&gt;info.q_opt_rss;</div><div class='add'>+</div><div class='add'>+	err = ice_update_vsi(hw, vsi-&gt;idx, ctx, NULL);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(ice_pf_to_dev(vsi-&gt;back), "Failed to configure RSS hash for VSI %d, error %d\n",</div><div class='add'>+			vsi-&gt;vsi_num, err);</div><div class='add'>+	} else {</div><div class='add'>+		vsi-&gt;info.q_opt_rss = ctx-&gt;info.q_opt_rss;</div><div class='add'>+		vsi-&gt;rss_hfunc = hfunc;</div><div class='add'>+		netdev_info(vsi-&gt;netdev, "Hash function set to: %sToeplitz\n",</div><div class='add'>+			    hfunc == ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ ?</div><div class='add'>+			    "Symmetric " : "");</div><div class='add'>+	}</div><div class='add'>+	kfree(ctx);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* Fix the symmetry setting for all existing RSS configurations */</div><div class='add'>+	symm = !!(hfunc == ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ);</div><div class='add'>+	return ice_set_rss_cfg_symm(hw, vsi, symm);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_bridge_getlink - Get the hardware bridge mode</div><div class='ctx'>  * @skb: skb buff</div><div class='ctx'>  * @pid: process ID</div><div class='hunk'>@@ -7889,8 +8101,8 @@ static void ice_tx_timeout(struct net_device *netdev, unsigned int txqueue)</div><div class='ctx'> 		struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='ctx'> 		u32 head, val = 0;</div><div class='ctx'> </div><div class='del'>-		head = (rd32(hw, QTX_COMM_HEAD(vsi-&gt;txq_map[txqueue])) &amp;</div><div class='del'>-			QTX_COMM_HEAD_HEAD_M) &gt;&gt; QTX_COMM_HEAD_HEAD_S;</div><div class='add'>+		head = FIELD_GET(QTX_COMM_HEAD_HEAD_M,</div><div class='add'>+				 rd32(hw, QTX_COMM_HEAD(vsi-&gt;txq_map[txqueue])));</div><div class='ctx'> 		/* Read interrupt register */</div><div class='ctx'> 		val = rd32(hw, GLINT_DYN_CTL(tx_ring-&gt;q_vector-&gt;reg_idx));</div><div class='ctx'> </div><div class='hunk'>@@ -8138,13 +8350,12 @@ static int ice_add_vsi_to_fdir(struct ice_pf *pf, struct ice_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 		for (tun = 0; tun &lt; ICE_FD_HW_SEG_MAX; tun++) {</div><div class='ctx'> 			enum ice_flow_priority prio;</div><div class='del'>-			u64 prof_id;</div><div class='ctx'> </div><div class='ctx'> 			/* add this VSI to FDir profile for this flow */</div><div class='ctx'> 			prio = ICE_FLOW_PRIO_NORMAL;</div><div class='ctx'> 			prof = hw-&gt;fdir_prof[flow];</div><div class='del'>-			prof_id = flow + tun * ICE_FLTR_PTYPE_MAX;</div><div class='del'>-			status = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id,</div><div class='add'>+			status = ice_flow_add_entry(hw, ICE_BLK_FD,</div><div class='add'>+						    prof-&gt;prof_id[tun],</div><div class='ctx'> 						    prof-&gt;vsi_h[0], vsi-&gt;idx,</div><div class='ctx'> 						    prio, prof-&gt;fdir_seg[tun],</div><div class='ctx'> 						    &amp;entry_h);</div><div class='hunk'>@@ -9187,8 +9398,14 @@ int ice_stop(struct net_device *netdev)</div><div class='ctx'> 		int link_err = ice_force_phys_link_state(vsi, false);</div><div class='ctx'> </div><div class='ctx'> 		if (link_err) {</div><div class='del'>-			netdev_err(vsi-&gt;netdev, "Failed to set physical link down, VSI %d error %d\n",</div><div class='del'>-				   vsi-&gt;vsi_num, link_err);</div><div class='add'>+			if (link_err == -ENOMEDIUM)</div><div class='add'>+				netdev_info(vsi-&gt;netdev, "Skipping link reconfig - no media attached, VSI %d\n",</div><div class='add'>+					    vsi-&gt;vsi_num);</div><div class='add'>+			else</div><div class='add'>+				netdev_err(vsi-&gt;netdev, "Failed to set physical link down, VSI %d error %d\n",</div><div class='add'>+					   vsi-&gt;vsi_num, link_err);</div><div class='add'>+</div><div class='add'>+			ice_vsi_close(vsi);</div><div class='ctx'> 			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c<br/>index f6f52a248066..d4e05d2cb30c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_nvm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_nvm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_nvm.c</a></div><div class='hunk'>@@ -571,8 +571,8 @@ ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nv</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	nvm-&gt;major = (ver &amp; ICE_NVM_VER_HI_MASK) &gt;&gt; ICE_NVM_VER_HI_SHIFT;</div><div class='del'>-	nvm-&gt;minor = (ver &amp; ICE_NVM_VER_LO_MASK) &gt;&gt; ICE_NVM_VER_LO_SHIFT;</div><div class='add'>+	nvm-&gt;major = FIELD_GET(ICE_NVM_VER_HI_MASK, ver);</div><div class='add'>+	nvm-&gt;minor = FIELD_GET(ICE_NVM_VER_LO_MASK, ver);</div><div class='ctx'> </div><div class='ctx'> 	status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &amp;eetrack_lo);</div><div class='ctx'> 	if (status) {</div><div class='hunk'>@@ -706,9 +706,9 @@ ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_o</div><div class='ctx'> </div><div class='ctx'> 	combo_ver = le32_to_cpu(civd.combo_ver);</div><div class='ctx'> </div><div class='del'>-	orom-&gt;major = (u8)((combo_ver &amp; ICE_OROM_VER_MASK) &gt;&gt; ICE_OROM_VER_SHIFT);</div><div class='del'>-	orom-&gt;patch = (u8)(combo_ver &amp; ICE_OROM_VER_PATCH_MASK);</div><div class='del'>-	orom-&gt;build = (u16)((combo_ver &amp; ICE_OROM_VER_BUILD_MASK) &gt;&gt; ICE_OROM_VER_BUILD_SHIFT);</div><div class='add'>+	orom-&gt;major = FIELD_GET(ICE_OROM_VER_MASK, combo_ver);</div><div class='add'>+	orom-&gt;patch = FIELD_GET(ICE_OROM_VER_PATCH_MASK, combo_ver);</div><div class='add'>+	orom-&gt;build = FIELD_GET(ICE_OROM_VER_BUILD_MASK, combo_ver);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -950,7 +950,8 @@ static int ice_determine_active_flash_banks(struct ice_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check that the control word indicates validity */</div><div class='del'>-	if ((ctrl_word &amp; ICE_SR_CTRL_WORD_1_M) &gt;&gt; ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {</div><div class='add'>+	if (FIELD_GET(ICE_SR_CTRL_WORD_1_M, ctrl_word) !=</div><div class='add'>+	    ICE_SR_CTRL_WORD_VALID) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1027,7 +1028,7 @@ int ice_init_nvm(struct ice_hw *hw)</div><div class='ctx'> 	 * as the blank mode may be used in the factory line.</div><div class='ctx'> 	 */</div><div class='ctx'> 	gens_stat = rd32(hw, GLNVM_GENS);</div><div class='del'>-	sr_size = (gens_stat &amp; GLNVM_GENS_SR_SIZE_M) &gt;&gt; GLNVM_GENS_SR_SIZE_S;</div><div class='add'>+	sr_size = FIELD_GET(GLNVM_GENS_SR_SIZE_M, gens_stat);</div><div class='ctx'> </div><div class='ctx'> 	/* Switching to words (sr_size contains power of 2) */</div><div class='ctx'> 	flash-&gt;sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c<br/>index 71f405f8a6fe..3b6605c8585e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp.c</a></div><div class='hunk'>@@ -7,7 +7,7 @@</div><div class='ctx'> </div><div class='ctx'> #define E810_OUT_PROP_DELAY_NS 1</div><div class='ctx'> </div><div class='del'>-#define UNKNOWN_INCVAL_E822 0x100000000ULL</div><div class='add'>+#define UNKNOWN_INCVAL_E82X 0x100000000ULL</div><div class='ctx'> </div><div class='ctx'> static const struct ptp_pin_desc ice_pin_desc_e810t[] = {</div><div class='ctx'> 	/* name    idx   func         chan */</div><div class='hunk'>@@ -525,6 +525,119 @@ ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_ptp_req_tx_single_tstamp - Request Tx timestamp for a port from FW</div><div class='add'>+ * @tx: the PTP Tx timestamp tracker</div><div class='add'>+ * @idx: index of the timestamp to request</div><div class='add'>+ */</div><div class='add'>+void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx)</div><div class='add'>+{</div><div class='add'>+	struct ice_ptp_port *ptp_port;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	struct ice_pf *pf;</div><div class='add'>+</div><div class='add'>+	if (!tx-&gt;init)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ptp_port = container_of(tx, struct ice_ptp_port, tx);</div><div class='add'>+	pf = ptp_port_to_pf(ptp_port);</div><div class='add'>+</div><div class='add'>+	/* Drop packets which have waited for more than 2 seconds */</div><div class='add'>+	if (time_is_before_jiffies(tx-&gt;tstamps[idx].start + 2 * HZ)) {</div><div class='add'>+		/* Count the number of Tx timestamps that timed out */</div><div class='add'>+		pf-&gt;ptp.tx_hwtstamp_timeouts++;</div><div class='add'>+</div><div class='add'>+		skb = tx-&gt;tstamps[idx].skb;</div><div class='add'>+		tx-&gt;tstamps[idx].skb = NULL;</div><div class='add'>+		clear_bit(idx, tx-&gt;in_use);</div><div class='add'>+</div><div class='add'>+		dev_kfree_skb_any(skb);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ice_trace(tx_tstamp_fw_req, tx-&gt;tstamps[idx].skb, idx);</div><div class='add'>+</div><div class='add'>+	/* Write TS index to read to the PF register so the FW can read it */</div><div class='add'>+	wr32(&amp;pf-&gt;hw, PF_SB_ATQBAL,</div><div class='add'>+	     TS_LL_READ_TS_INTR | FIELD_PREP(TS_LL_READ_TS_IDX, idx) |</div><div class='add'>+	     TS_LL_READ_TS);</div><div class='add'>+	tx-&gt;last_ll_ts_idx_read = idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_ptp_complete_tx_single_tstamp - Complete Tx timestamp for a port</div><div class='add'>+ * @tx: the PTP Tx timestamp tracker</div><div class='add'>+ */</div><div class='add'>+void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx)</div><div class='add'>+{</div><div class='add'>+	struct skb_shared_hwtstamps shhwtstamps = {};</div><div class='add'>+	u8 idx = tx-&gt;last_ll_ts_idx_read;</div><div class='add'>+	struct ice_ptp_port *ptp_port;</div><div class='add'>+	u64 raw_tstamp, tstamp;</div><div class='add'>+	bool drop_ts = false;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	struct ice_pf *pf;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	if (!tx-&gt;init || tx-&gt;last_ll_ts_idx_read &lt; 0)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ptp_port = container_of(tx, struct ice_ptp_port, tx);</div><div class='add'>+	pf = ptp_port_to_pf(ptp_port);</div><div class='add'>+</div><div class='add'>+	ice_trace(tx_tstamp_fw_done, tx-&gt;tstamps[idx].skb, idx);</div><div class='add'>+</div><div class='add'>+	val = rd32(&amp;pf-&gt;hw, PF_SB_ATQBAL);</div><div class='add'>+</div><div class='add'>+	/* When the bit is cleared, the TS is ready in the register */</div><div class='add'>+	if (val &amp; TS_LL_READ_TS) {</div><div class='add'>+		dev_err(ice_pf_to_dev(pf), "Failed to get the Tx tstamp - FW not ready");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* High 8 bit value of the TS is on the bits 16:23 */</div><div class='add'>+	raw_tstamp = FIELD_GET(TS_LL_READ_TS_HIGH, val);</div><div class='add'>+	raw_tstamp &lt;&lt;= 32;</div><div class='add'>+</div><div class='add'>+	/* Read the low 32 bit value */</div><div class='add'>+	raw_tstamp |= (u64)rd32(&amp;pf-&gt;hw, PF_SB_ATQBAH);</div><div class='add'>+</div><div class='add'>+	/* For PHYs which don't implement a proper timestamp ready bitmap,</div><div class='add'>+	 * verify that the timestamp value is different from the last cached</div><div class='add'>+	 * timestamp. If it is not, skip this for now assuming it hasn't yet</div><div class='add'>+	 * been captured by hardware.</div><div class='add'>+	 */</div><div class='add'>+	if (!drop_ts &amp;&amp; tx-&gt;verify_cached &amp;&amp;</div><div class='add'>+	    raw_tstamp == tx-&gt;tstamps[idx].cached_tstamp)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (tx-&gt;verify_cached &amp;&amp; raw_tstamp)</div><div class='add'>+		tx-&gt;tstamps[idx].cached_tstamp = raw_tstamp;</div><div class='add'>+	clear_bit(idx, tx-&gt;in_use);</div><div class='add'>+	skb = tx-&gt;tstamps[idx].skb;</div><div class='add'>+	tx-&gt;tstamps[idx].skb = NULL;</div><div class='add'>+	if (test_and_clear_bit(idx, tx-&gt;stale))</div><div class='add'>+		drop_ts = true;</div><div class='add'>+</div><div class='add'>+	if (!skb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (drop_ts) {</div><div class='add'>+		dev_kfree_skb_any(skb);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Extend the timestamp using cached PHC time */</div><div class='add'>+	tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);</div><div class='add'>+	if (tstamp) {</div><div class='add'>+		shhwtstamps.hwtstamp = ns_to_ktime(tstamp);</div><div class='add'>+		ice_trace(tx_tstamp_complete, skb, idx);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	skb_tstamp_tx(skb, &amp;shhwtstamps);</div><div class='add'>+	dev_kfree_skb_any(skb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_ptp_process_tx_tstamp - Process Tx timestamps for a port</div><div class='ctx'>  * @tx: the PTP Tx timestamp tracker</div><div class='ctx'>  *</div><div class='hunk'>@@ -575,6 +688,7 @@ ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)</div><div class='ctx'> static void ice_ptp_process_tx_tstamp(struct ice_ptp_tx *tx)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_ptp_port *ptp_port;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> 	struct ice_pf *pf;</div><div class='ctx'> 	struct ice_hw *hw;</div><div class='ctx'> 	u64 tstamp_ready;</div><div class='hunk'>@@ -646,7 +760,7 @@ static void ice_ptp_process_tx_tstamp(struct ice_ptp_tx *tx)</div><div class='ctx'> 			drop_ts = true;</div><div class='ctx'> </div><div class='ctx'> skip_ts_read:</div><div class='del'>-		spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+		spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 		if (tx-&gt;verify_cached &amp;&amp; raw_tstamp)</div><div class='ctx'> 			tx-&gt;tstamps[idx].cached_tstamp = raw_tstamp;</div><div class='ctx'> 		clear_bit(idx, tx-&gt;in_use);</div><div class='hunk'>@@ -654,7 +768,7 @@ skip_ts_read:</div><div class='ctx'> 		tx-&gt;tstamps[idx].skb = NULL;</div><div class='ctx'> 		if (test_and_clear_bit(idx, tx-&gt;stale))</div><div class='ctx'> 			drop_ts = true;</div><div class='del'>-		spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+		spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 		/* It is unlikely but possible that the SKB will have been</div><div class='ctx'> 		 * flushed at this point due to link change or teardown.</div><div class='hunk'>@@ -705,7 +819,9 @@ static enum ice_tx_tstamp_work ice_ptp_tx_tstamp_owner(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 		/* Read the Tx ready status first */</div><div class='ctx'> 		err = ice_get_phy_tx_tstamp_ready(&amp;pf-&gt;hw, i, &amp;tstamp_ready);</div><div class='del'>-		if (err || tstamp_ready)</div><div class='add'>+		if (err)</div><div class='add'>+			break;</div><div class='add'>+		else if (tstamp_ready)</div><div class='ctx'> 			return ICE_TX_TSTAMP_WORK_PENDING;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -722,6 +838,7 @@ static enum ice_tx_tstamp_work ice_ptp_tx_tstamp_owner(struct ice_pf *pf)</div><div class='ctx'> static enum ice_tx_tstamp_work ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)</div><div class='ctx'> {</div><div class='ctx'> 	bool more_timestamps;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> </div><div class='ctx'> 	if (!tx-&gt;init)</div><div class='ctx'> 		return ICE_TX_TSTAMP_WORK_DONE;</div><div class='hunk'>@@ -730,9 +847,9 @@ static enum ice_tx_tstamp_work ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)</div><div class='ctx'> 	ice_ptp_process_tx_tstamp(tx);</div><div class='ctx'> </div><div class='ctx'> 	/* Check if there are outstanding Tx timestamps */</div><div class='del'>-	spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 	more_timestamps = tx-&gt;init &amp;&amp; !bitmap_empty(tx-&gt;in_use, tx-&gt;len);</div><div class='del'>-	spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	if (more_timestamps)</div><div class='ctx'> 		return ICE_TX_TSTAMP_WORK_PENDING;</div><div class='hunk'>@@ -769,6 +886,7 @@ ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)</div><div class='ctx'> 	tx-&gt;in_use = in_use;</div><div class='ctx'> 	tx-&gt;stale = stale;</div><div class='ctx'> 	tx-&gt;init = 1;</div><div class='add'>+	tx-&gt;last_ll_ts_idx_read = -1;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;tx-&gt;lock);</div><div class='ctx'> </div><div class='hunk'>@@ -786,6 +904,7 @@ static void</div><div class='ctx'> ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> 	u64 tstamp_ready;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u8 idx;</div><div class='hunk'>@@ -809,12 +928,12 @@ ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'> 		if (!hw-&gt;reset_ongoing &amp;&amp; (tstamp_ready &amp; BIT_ULL(phy_idx)))</div><div class='ctx'> 			ice_clear_phy_tstamp(hw, tx-&gt;block, phy_idx);</div><div class='ctx'> </div><div class='del'>-		spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+		spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 		skb = tx-&gt;tstamps[idx].skb;</div><div class='ctx'> 		tx-&gt;tstamps[idx].skb = NULL;</div><div class='ctx'> 		clear_bit(idx, tx-&gt;in_use);</div><div class='ctx'> 		clear_bit(idx, tx-&gt;stale);</div><div class='del'>-		spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+		spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 		/* Count the number of Tx timestamps flushed */</div><div class='ctx'> 		pf-&gt;ptp.tx_hwtstamp_flushed++;</div><div class='hunk'>@@ -838,9 +957,11 @@ ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'> static void</div><div class='ctx'> ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)</div><div class='ctx'> {</div><div class='del'>-	spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 	bitmap_or(tx-&gt;stale, tx-&gt;stale, tx-&gt;in_use, tx-&gt;len);</div><div class='del'>-	spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -853,9 +974,11 @@ ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)</div><div class='ctx'> static void</div><div class='ctx'> ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'> {</div><div class='del'>-	spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 	tx-&gt;init = 0;</div><div class='del'>-	spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	/* wait for potentially outstanding interrupt to complete */</div><div class='ctx'> 	synchronize_irq(pf-&gt;oicr_irq.virq);</div><div class='hunk'>@@ -875,7 +998,7 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps</div><div class='add'>+ * ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps</div><div class='ctx'>  * @pf: Board private structure</div><div class='ctx'>  * @tx: the Tx tracking structure to initialize</div><div class='ctx'>  * @port: the port this structure tracks</div><div class='hunk'>@@ -886,11 +1009,11 @@ ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)</div><div class='ctx'>  * registers into chunks based on the port number.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)</div><div class='add'>+ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	tx-&gt;block = port / ICE_PORTS_PER_QUAD;</div><div class='del'>-	tx-&gt;offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E822;</div><div class='del'>-	tx-&gt;len = INDEX_PER_PORT_E822;</div><div class='add'>+	tx-&gt;offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;</div><div class='add'>+	tx-&gt;len = INDEX_PER_PORT_E82X;</div><div class='ctx'> 	tx-&gt;verify_cached = 0;</div><div class='ctx'> </div><div class='ctx'> 	return ice_ptp_alloc_tx_tracker(tx);</div><div class='hunk'>@@ -1093,10 +1216,10 @@ static u64 ice_base_incval(struct ice_pf *pf)</div><div class='ctx'> </div><div class='ctx'> 	if (ice_is_e810(hw))</div><div class='ctx'> 		incval = ICE_PTP_NOMINAL_INCVAL_E810;</div><div class='del'>-	else if (ice_e822_time_ref(hw) &lt; NUM_ICE_TIME_REF_FREQ)</div><div class='del'>-		incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));</div><div class='add'>+	else if (ice_e82x_time_ref(hw) &lt; NUM_ICE_TIME_REF_FREQ)</div><div class='add'>+		incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));</div><div class='ctx'> 	else</div><div class='del'>-		incval = UNKNOWN_INCVAL_E822;</div><div class='add'>+		incval = UNKNOWN_INCVAL_E82X;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",</div><div class='ctx'> 		incval);</div><div class='hunk'>@@ -1125,10 +1248,10 @@ static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)</div><div class='ctx'> </div><div class='ctx'> 	/* need to read FIFO state */</div><div class='ctx'> 	if (offs == 0 || offs == 1)</div><div class='del'>-		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,</div><div class='add'>+		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO01_STATUS,</div><div class='ctx'> 					     &amp;val);</div><div class='ctx'> 	else</div><div class='del'>-		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,</div><div class='add'>+		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO23_STATUS,</div><div class='ctx'> 					     &amp;val);</div><div class='ctx'> </div><div class='ctx'> 	if (err) {</div><div class='hunk'>@@ -1138,9 +1261,9 @@ static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (offs &amp; 0x1)</div><div class='del'>-		phy_sts = (val &amp; Q_REG_FIFO13_M) &gt;&gt; Q_REG_FIFO13_S;</div><div class='add'>+		phy_sts = FIELD_GET(Q_REG_FIFO13_M, val);</div><div class='ctx'> 	else</div><div class='del'>-		phy_sts = (val &amp; Q_REG_FIFO02_M) &gt;&gt; Q_REG_FIFO02_S;</div><div class='add'>+		phy_sts = FIELD_GET(Q_REG_FIFO02_M, val);</div><div class='ctx'> </div><div class='ctx'> 	if (phy_sts &amp; FIFO_EMPTY) {</div><div class='ctx'> 		port-&gt;tx_fifo_busy_cnt = FIFO_OK;</div><div class='hunk'>@@ -1156,7 +1279,7 @@ static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)</div><div class='ctx'> 		dev_dbg(ice_pf_to_dev(pf),</div><div class='ctx'> 			"Port %d Tx FIFO still not empty; resetting quad %d\n",</div><div class='ctx'> 			port-&gt;port_num, quad);</div><div class='del'>-		ice_ptp_reset_ts_memory_quad_e822(hw, quad);</div><div class='add'>+		ice_ptp_reset_ts_memory_quad_e82x(hw, quad);</div><div class='ctx'> 		port-&gt;tx_fifo_busy_cnt = FIFO_OK;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1201,8 +1324,8 @@ static void ice_ptp_wait_for_offsets(struct kthread_work *work)</div><div class='ctx'> </div><div class='ctx'> 	tx_err = ice_ptp_check_tx_fifo(port);</div><div class='ctx'> 	if (!tx_err)</div><div class='del'>-		tx_err = ice_phy_cfg_tx_offset_e822(hw, port-&gt;port_num);</div><div class='del'>-	rx_err = ice_phy_cfg_rx_offset_e822(hw, port-&gt;port_num);</div><div class='add'>+		tx_err = ice_phy_cfg_tx_offset_e82x(hw, port-&gt;port_num);</div><div class='add'>+	rx_err = ice_phy_cfg_rx_offset_e82x(hw, port-&gt;port_num);</div><div class='ctx'> 	if (tx_err || rx_err) {</div><div class='ctx'> 		/* Tx and/or Rx offset not yet configured, try again later */</div><div class='ctx'> 		kthread_queue_delayed_work(pf-&gt;ptp.kworker,</div><div class='hunk'>@@ -1231,7 +1354,7 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)</div><div class='ctx'> </div><div class='ctx'> 	kthread_cancel_delayed_work_sync(&amp;ptp_port-&gt;ov_work);</div><div class='ctx'> </div><div class='del'>-	err = ice_stop_phy_timer_e822(hw, port, true);</div><div class='add'>+	err = ice_stop_phy_timer_e82x(hw, port, true);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",</div><div class='ctx'> 			port, err);</div><div class='hunk'>@@ -1255,6 +1378,7 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)</div><div class='ctx'> 	struct ice_pf *pf = ptp_port_to_pf(ptp_port);</div><div class='ctx'> 	u8 port = ptp_port-&gt;port_num;</div><div class='ctx'> 	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (ice_is_e810(hw))</div><div class='hunk'>@@ -1268,20 +1392,20 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)</div><div class='ctx'> 	kthread_cancel_delayed_work_sync(&amp;ptp_port-&gt;ov_work);</div><div class='ctx'> </div><div class='ctx'> 	/* temporarily disable Tx timestamps while calibrating PHY offset */</div><div class='del'>-	spin_lock(&amp;ptp_port-&gt;tx.lock);</div><div class='add'>+	spin_lock_irqsave(&amp;ptp_port-&gt;tx.lock, flags);</div><div class='ctx'> 	ptp_port-&gt;tx.calibrating = true;</div><div class='del'>-	spin_unlock(&amp;ptp_port-&gt;tx.lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;ptp_port-&gt;tx.lock, flags);</div><div class='ctx'> 	ptp_port-&gt;tx_fifo_busy_cnt = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Start the PHY timer in Vernier mode */</div><div class='del'>-	err = ice_start_phy_timer_e822(hw, port);</div><div class='add'>+	err = ice_start_phy_timer_e82x(hw, port);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='ctx'> 	/* Enable Tx timestamps right away */</div><div class='del'>-	spin_lock(&amp;ptp_port-&gt;tx.lock);</div><div class='add'>+	spin_lock_irqsave(&amp;ptp_port-&gt;tx.lock, flags);</div><div class='ctx'> 	ptp_port-&gt;tx.calibrating = false;</div><div class='del'>-	spin_unlock(&amp;ptp_port-&gt;tx.lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;ptp_port-&gt;tx.lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	kthread_queue_delayed_work(pf-&gt;ptp.kworker, &amp;ptp_port-&gt;ov_work, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -1323,7 +1447,7 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		/* Do not reconfigure E810 PHY */</div><div class='ctx'> 		return;</div><div class='del'>-	case ICE_PHY_E822:</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='ctx'> 		ice_ptp_port_phy_restart(ptp_port);</div><div class='ctx'> 		return;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1349,7 +1473,7 @@ static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)</div><div class='ctx'> 	ice_ptp_reset_ts_memory(hw);</div><div class='ctx'> </div><div class='ctx'> 	for (quad = 0; quad &lt; ICE_MAX_QUAD; quad++) {</div><div class='del'>-		err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,</div><div class='add'>+		err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,</div><div class='ctx'> 					     &amp;val);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1357,13 +1481,13 @@ static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)</div><div class='ctx'> 		if (ena) {</div><div class='ctx'> 			val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;</div><div class='ctx'> 			val &amp;= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;</div><div class='del'>-			val |= ((threshold &lt;&lt; Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &amp;</div><div class='del'>-				Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);</div><div class='add'>+			val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,</div><div class='add'>+					  threshold);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			val &amp;= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,</div><div class='add'>+		err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,</div><div class='ctx'> 					      val);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -1503,8 +1627,7 @@ ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,</div><div class='ctx'> 		 * + num_in_channels * tmr_idx</div><div class='ctx'> 		 */</div><div class='ctx'> 		func = 1 + chan + (tmr_idx * 3);</div><div class='del'>-		gpio_reg = ((func &lt;&lt; GLGEN_GPIO_CTL_PIN_FUNC_S) &amp;</div><div class='del'>-			    GLGEN_GPIO_CTL_PIN_FUNC_M);</div><div class='add'>+		gpio_reg = FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);</div><div class='ctx'> 		pf-&gt;ptp.ext_ts_chan |= (1 &lt;&lt; chan);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* clear the values we set to reset defaults */</div><div class='hunk'>@@ -1601,7 +1724,7 @@ static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,</div><div class='ctx'> 	if (ice_is_e810(hw))</div><div class='ctx'> 		start_time -= E810_OUT_PROP_DELAY_NS;</div><div class='ctx'> 	else</div><div class='del'>-		start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));</div><div class='add'>+		start_time -= ice_e82x_pps_delay(ice_e82x_time_ref(hw));</div><div class='ctx'> </div><div class='ctx'> 	/* 2. Write TARGET time */</div><div class='ctx'> 	wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));</div><div class='hunk'>@@ -1614,7 +1737,7 @@ static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,</div><div class='ctx'> 	/* 4. write GPIO CTL reg */</div><div class='ctx'> 	func = 8 + chan + (tmr_idx * 4);</div><div class='ctx'> 	val = GLGEN_GPIO_CTL_PIN_DIR_M |</div><div class='del'>-	      ((func &lt;&lt; GLGEN_GPIO_CTL_PIN_FUNC_S) &amp; GLGEN_GPIO_CTL_PIN_FUNC_M);</div><div class='add'>+	      FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);</div><div class='ctx'> 	wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);</div><div class='ctx'> </div><div class='ctx'> 	/* Store the value if requested */</div><div class='hunk'>@@ -1840,7 +1963,7 @@ ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)</div><div class='ctx'> 	ice_ptp_enable_all_clkout(pf);</div><div class='ctx'> </div><div class='ctx'> 	/* Recalibrate and re-enable timestamp blocks for E822/E823 */</div><div class='del'>-	if (hw-&gt;phy_model == ICE_PHY_E822)</div><div class='add'>+	if (hw-&gt;phy_model == ICE_PHY_E82X)</div><div class='ctx'> 		ice_ptp_restart_all_phy(pf);</div><div class='ctx'> exit:</div><div class='ctx'> 	if (err) {</div><div class='hunk'>@@ -2127,30 +2250,26 @@ int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_rx_hwtstamp - Check for an Rx timestamp</div><div class='del'>- * @rx_ring: Ring to get the VSI info</div><div class='add'>+ * ice_ptp_get_rx_hwts - Get packet Rx timestamp in ns</div><div class='ctx'>  * @rx_desc: Receive descriptor</div><div class='del'>- * @skb: Particular skb to send timestamp with</div><div class='add'>+ * @pkt_ctx: Packet context to get the cached time</div><div class='ctx'>  *</div><div class='ctx'>  * The driver receives a notification in the receive descriptor with timestamp.</div><div class='del'>- * The timestamp is in ns, so we must convert the result first.</div><div class='ctx'>  */</div><div class='del'>-void</div><div class='del'>-ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,</div><div class='del'>-		    union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)</div><div class='add'>+u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,</div><div class='add'>+			const struct ice_pkt_ctx *pkt_ctx)</div><div class='ctx'> {</div><div class='del'>-	struct skb_shared_hwtstamps *hwtstamps;</div><div class='ctx'> 	u64 ts_ns, cached_time;</div><div class='ctx'> 	u32 ts_high;</div><div class='ctx'> </div><div class='ctx'> 	if (!(rx_desc-&gt;wb.time_stamp_low &amp; ICE_PTP_TS_VALID))</div><div class='del'>-		return;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='del'>-	cached_time = READ_ONCE(rx_ring-&gt;cached_phctime);</div><div class='add'>+	cached_time = READ_ONCE(pkt_ctx-&gt;cached_phctime);</div><div class='ctx'> </div><div class='ctx'> 	/* Do not report a timestamp if we don't have a cached PHC time */</div><div class='ctx'> 	if (!cached_time)</div><div class='del'>-		return;</div><div class='add'>+		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached</div><div class='ctx'> 	 * PHC value, rather than accessing the PF. This also allows us to</div><div class='hunk'>@@ -2161,9 +2280,7 @@ ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,</div><div class='ctx'> 	ts_high = le32_to_cpu(rx_desc-&gt;wb.flex_ts.ts_high);</div><div class='ctx'> 	ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);</div><div class='ctx'> </div><div class='del'>-	hwtstamps = skb_hwtstamps(skb);</div><div class='del'>-	memset(hwtstamps, 0, sizeof(*hwtstamps));</div><div class='del'>-	hwtstamps-&gt;hwtstamp = ns_to_ktime(ts_ns);</div><div class='add'>+	return ts_ns;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2378,18 +2495,23 @@ static long ice_ptp_create_clock(struct ice_pf *pf)</div><div class='ctx'>  */</div><div class='ctx'> s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)</div><div class='ctx'> {</div><div class='add'>+	unsigned long flags;</div><div class='ctx'> 	u8 idx;</div><div class='ctx'> </div><div class='del'>-	spin_lock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_lock_irqsave(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	/* Check that this tracker is accepting new timestamp requests */</div><div class='ctx'> 	if (!ice_ptp_is_tx_tracker_up(tx)) {</div><div class='del'>-		spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+		spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> 		return -1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Find and set the first available index */</div><div class='del'>-	idx = find_first_zero_bit(tx-&gt;in_use, tx-&gt;len);</div><div class='add'>+	idx = find_next_zero_bit(tx-&gt;in_use, tx-&gt;len,</div><div class='add'>+				 tx-&gt;last_ll_ts_idx_read + 1);</div><div class='add'>+	if (idx == tx-&gt;len)</div><div class='add'>+		idx = find_first_zero_bit(tx-&gt;in_use, tx-&gt;len);</div><div class='add'>+</div><div class='ctx'> 	if (idx &lt; tx-&gt;len) {</div><div class='ctx'> 		/* We got a valid index that no other thread could have set. Store</div><div class='ctx'> 		 * a reference to the skb and the start time to allow discarding old</div><div class='hunk'>@@ -2403,7 +2525,7 @@ s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)</div><div class='ctx'> 		ice_trace(tx_tstamp_request, skb, idx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	spin_unlock(&amp;tx-&gt;lock);</div><div class='add'>+	spin_unlock_irqrestore(&amp;tx-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	/* return the appropriate PHY timestamp register index, -1 if no</div><div class='ctx'> 	 * indexes were available.</div><div class='hunk'>@@ -2440,6 +2562,54 @@ enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ice_ptp_maybe_trigger_tx_interrupt - Trigger Tx timstamp interrupt</div><div class='add'>+ * @pf: Board private structure</div><div class='add'>+ *</div><div class='add'>+ * The device PHY issues Tx timestamp interrupts to the driver for processing</div><div class='add'>+ * timestamp data from the PHY. It will not interrupt again until all</div><div class='add'>+ * current timestamp data is read. In rare circumstances, it is possible that</div><div class='add'>+ * the driver fails to read all outstanding data.</div><div class='add'>+ *</div><div class='add'>+ * To avoid getting permanently stuck, periodically check if the PHY has</div><div class='add'>+ * outstanding timestamp data. If so, trigger an interrupt from software to</div><div class='add'>+ * process this data.</div><div class='add'>+ */</div><div class='add'>+static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = ice_pf_to_dev(pf);</div><div class='add'>+	struct ice_hw *hw = &amp;pf-&gt;hw;</div><div class='add'>+	bool trigger_oicr = false;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	if (ice_is_e810(hw))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (!ice_pf_src_tmr_owned(pf))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ICE_MAX_QUAD; i++) {</div><div class='add'>+		u64 tstamp_ready;</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		err = ice_get_phy_tx_tstamp_ready(&amp;pf-&gt;hw, i, &amp;tstamp_ready);</div><div class='add'>+		if (!err &amp;&amp; tstamp_ready) {</div><div class='add'>+			trigger_oicr = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (trigger_oicr) {</div><div class='add'>+		/* Trigger a software interrupt, to ensure this data</div><div class='add'>+		 * gets processed.</div><div class='add'>+		 */</div><div class='add'>+		dev_dbg(dev, "PTP periodic task detected waiting timestamps. Triggering Tx timestamp interrupt now.\n");</div><div class='add'>+</div><div class='add'>+		wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);</div><div class='add'>+		ice_flush(hw);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void ice_ptp_periodic_work(struct kthread_work *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);</div><div class='hunk'>@@ -2451,6 +2621,8 @@ static void ice_ptp_periodic_work(struct kthread_work *work)</div><div class='ctx'> </div><div class='ctx'> 	err = ice_ptp_update_cached_phctime(pf);</div><div class='ctx'> </div><div class='add'>+	ice_ptp_maybe_trigger_tx_interrupt(pf);</div><div class='add'>+</div><div class='ctx'> 	/* Run twice a second or reschedule if phc update failed */</div><div class='ctx'> 	kthread_queue_delayed_work(ptp-&gt;kworker, &amp;ptp-&gt;work,</div><div class='ctx'> 				   msecs_to_jiffies(err ? 10 : 500));</div><div class='hunk'>@@ -2468,12 +2640,10 @@ void ice_ptp_reset(struct ice_pf *pf)</div><div class='ctx'> 	int err, itr = 1;</div><div class='ctx'> 	u64 time_diff;</div><div class='ctx'> </div><div class='del'>-	if (test_bit(ICE_PFR_REQ, pf-&gt;state))</div><div class='add'>+	if (test_bit(ICE_PFR_REQ, pf-&gt;state) ||</div><div class='add'>+	    !ice_pf_src_tmr_owned(pf))</div><div class='ctx'> 		goto pfr;</div><div class='ctx'> </div><div class='del'>-	if (!ice_pf_src_tmr_owned(pf))</div><div class='del'>-		goto reset_ts;</div><div class='del'>-</div><div class='ctx'> 	err = ice_ptp_init_phc(hw);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err;</div><div class='hunk'>@@ -2517,10 +2687,6 @@ void ice_ptp_reset(struct ice_pf *pf)</div><div class='ctx'> 			goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-reset_ts:</div><div class='del'>-	/* Restart the PHY timestamping block */</div><div class='del'>-	ice_ptp_reset_phy_timestamping(pf);</div><div class='del'>-</div><div class='ctx'> pfr:</div><div class='ctx'> 	/* Init Tx structures */</div><div class='ctx'> 	if (ice_is_e810(&amp;pf-&gt;hw)) {</div><div class='hunk'>@@ -2528,7 +2694,7 @@ pfr:</div><div class='ctx'> 	} else {</div><div class='ctx'> 		kthread_init_delayed_work(&amp;ptp-&gt;port.ov_work,</div><div class='ctx'> 					  ice_ptp_wait_for_offsets);</div><div class='del'>-		err = ice_ptp_init_tx_e822(pf, &amp;ptp-&gt;port.tx,</div><div class='add'>+		err = ice_ptp_init_tx_e82x(pf, &amp;ptp-&gt;port.tx,</div><div class='ctx'> 					   ptp-&gt;port.port_num);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -2536,6 +2702,11 @@ pfr:</div><div class='ctx'> </div><div class='ctx'> 	set_bit(ICE_FLAG_PTP, pf-&gt;flags);</div><div class='ctx'> </div><div class='add'>+	/* Restart the PHY timestamping block */</div><div class='add'>+	if (!test_bit(ICE_PFR_REQ, pf-&gt;state) &amp;&amp;</div><div class='add'>+	    ice_pf_src_tmr_owned(pf))</div><div class='add'>+		ice_ptp_restart_all_phy(pf);</div><div class='add'>+</div><div class='ctx'> 	/* Start periodic work going */</div><div class='ctx'> 	kthread_queue_delayed_work(ptp-&gt;kworker, &amp;ptp-&gt;work, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -2692,6 +2863,8 @@ static int ice_ptp_register_auxbus_driver(struct ice_pf *pf)</div><div class='ctx'> 	name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",</div><div class='ctx'> 			      pf-&gt;pdev-&gt;bus-&gt;number, PCI_SLOT(pf-&gt;pdev-&gt;devfn),</div><div class='ctx'> 			      ice_get_ptp_src_clock_index(&amp;pf-&gt;hw));</div><div class='add'>+	if (!name)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	aux_driver-&gt;name = name;</div><div class='ctx'> 	aux_driver-&gt;shutdown = ice_ptp_auxbus_shutdown;</div><div class='hunk'>@@ -2896,11 +3069,11 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)</div><div class='ctx'> 	switch (hw-&gt;phy_model) {</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		return ice_ptp_init_tx_e810(pf, &amp;ptp_port-&gt;tx);</div><div class='del'>-	case ICE_PHY_E822:</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='ctx'> 		kthread_init_delayed_work(&amp;ptp_port-&gt;ov_work,</div><div class='ctx'> 					  ice_ptp_wait_for_offsets);</div><div class='ctx'> </div><div class='del'>-		return ice_ptp_init_tx_e822(pf, &amp;ptp_port-&gt;tx,</div><div class='add'>+		return ice_ptp_init_tx_e82x(pf, &amp;ptp_port-&gt;tx,</div><div class='ctx'> 					    ptp_port-&gt;port_num);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ENODEV;</div><div class='hunk'>@@ -2938,6 +3111,8 @@ static int ice_ptp_create_auxbus_device(struct ice_pf *pf)</div><div class='ctx'> 	name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",</div><div class='ctx'> 			      pf-&gt;pdev-&gt;bus-&gt;number, PCI_SLOT(pf-&gt;pdev-&gt;devfn),</div><div class='ctx'> 			      ice_get_ptp_src_clock_index(&amp;pf-&gt;hw));</div><div class='add'>+	if (!name)</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	aux_dev-&gt;name = name;</div><div class='ctx'> 	aux_dev-&gt;id = id;</div><div class='hunk'>@@ -2987,7 +3162,7 @@ static void ice_ptp_remove_auxbus_device(struct ice_pf *pf)</div><div class='ctx'> static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	switch (pf-&gt;hw.phy_model) {</div><div class='del'>-	case ICE_PHY_E822:</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='ctx'> 		/* E822 based PHY has the clock owner process the interrupt</div><div class='ctx'> 		 * for all ports.</div><div class='ctx'> 		 */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h<br/>index 06a330867fc9..087dd32d8762 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp.h</a></div><div class='hunk'>@@ -131,6 +131,7 @@ enum ice_tx_tstamp_work {</div><div class='ctx'>  * @calibrating: if true, the PHY is calibrating the Tx offset. During this</div><div class='ctx'>  *               window, timestamps are temporarily disabled.</div><div class='ctx'>  * @verify_cached: if true, verify new timestamp differs from last read value</div><div class='add'>+ * @last_ll_ts_idx_read: index of the last LL TS read by the FW</div><div class='ctx'>  */</div><div class='ctx'> struct ice_ptp_tx {</div><div class='ctx'> 	spinlock_t lock; /* lock protecting in_use bitmap */</div><div class='hunk'>@@ -143,11 +144,12 @@ struct ice_ptp_tx {</div><div class='ctx'> 	u8 init : 1;</div><div class='ctx'> 	u8 calibrating : 1;</div><div class='ctx'> 	u8 verify_cached : 1;</div><div class='add'>+	s8 last_ll_ts_idx_read;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Quad and port information for initializing timestamp blocks */</div><div class='ctx'> #define INDEX_PER_QUAD			64</div><div class='del'>-#define INDEX_PER_PORT_E822		16</div><div class='add'>+#define INDEX_PER_PORT_E82X		16</div><div class='ctx'> #define INDEX_PER_PORT_E810		64</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -296,11 +298,12 @@ void ice_ptp_restore_timestamp_mode(struct ice_pf *pf);</div><div class='ctx'> </div><div class='ctx'> void ice_ptp_extts_event(struct ice_pf *pf);</div><div class='ctx'> s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb);</div><div class='add'>+void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx);</div><div class='add'>+void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx);</div><div class='ctx'> enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf);</div><div class='ctx'> </div><div class='del'>-void</div><div class='del'>-ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,</div><div class='del'>-		    union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb);</div><div class='add'>+u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,</div><div class='add'>+			const struct ice_pkt_ctx *pkt_ctx);</div><div class='ctx'> void ice_ptp_reset(struct ice_pf *pf);</div><div class='ctx'> void ice_ptp_prepare_for_reset(struct ice_pf *pf);</div><div class='ctx'> void ice_ptp_init(struct ice_pf *pf);</div><div class='hunk'>@@ -325,13 +328,23 @@ ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)</div><div class='ctx'> 	return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx)</div><div class='add'>+{ }</div><div class='add'>+</div><div class='add'>+static inline void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx) { }</div><div class='add'>+</div><div class='ctx'> static inline bool ice_ptp_process_ts(struct ice_pf *pf)</div><div class='ctx'> {</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='del'>-static inline void</div><div class='del'>-ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,</div><div class='del'>-		    union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb) { }</div><div class='add'>+</div><div class='add'>+static inline u64</div><div class='add'>+ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,</div><div class='add'>+		    const struct ice_pkt_ctx *pkt_ctx)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static inline void ice_ptp_reset(struct ice_pf *pf) { }</div><div class='ctx'> static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf) { }</div><div class='ctx'> static inline void ice_ptp_init(struct ice_pf *pf) { }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h<br/>index 4109aa3b2fcd..2c4dab0c48ab 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_consts.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ptp_consts.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_consts.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_consts.h</a></div><div class='hunk'>@@ -9,17 +9,17 @@</div><div class='ctx'>  */</div><div class='ctx'> /* Constants defined for the PTP 1588 clock hardware. */</div><div class='ctx'> </div><div class='del'>-/* struct ice_time_ref_info_e822</div><div class='add'>+/* struct ice_time_ref_info_e82x</div><div class='ctx'>  *</div><div class='ctx'>  * E822 hardware can use different sources as the reference for the PTP</div><div class='ctx'>  * hardware clock. Each clock has different characteristics such as a slightly</div><div class='ctx'>  * different frequency, etc.</div><div class='ctx'>  *</div><div class='ctx'>  * This lookup table defines several constants that depend on the current time</div><div class='del'>- * reference. See the struct ice_time_ref_info_e822 for information about the</div><div class='add'>+ * reference. See the struct ice_time_ref_info_e82x for information about the</div><div class='ctx'>  * meaning of each constant.</div><div class='ctx'>  */</div><div class='del'>-const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {</div><div class='add'>+const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {</div><div class='ctx'> 	/* ICE_TIME_REF_FREQ_25_000 -&gt; 25 MHz */</div><div class='ctx'> 	{</div><div class='ctx'> 		/* pll_freq */</div><div class='hunk'>@@ -81,7 +81,7 @@ const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {</div><div class='add'>+const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {</div><div class='ctx'> 	/* ICE_TIME_REF_FREQ_25_000 -&gt; 25 MHz */</div><div class='ctx'> 	{</div><div class='ctx'> 		/* refclk_pre_div */</div><div class='hunk'>@@ -155,7 +155,7 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* struct ice_vernier_info_e822</div><div class='add'>+/* struct ice_vernier_info_e82x</div><div class='ctx'>  *</div><div class='ctx'>  * E822 hardware calibrates the delay of the timestamp indication from the</div><div class='ctx'>  * actual packet transmission or reception during the initialization of the</div><div class='hunk'>@@ -168,7 +168,7 @@ const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {</div><div class='ctx'>  * used by this link speed, and that the register should be cleared by writing</div><div class='ctx'>  * 0. Other values specify the clock frequency in Hz.</div><div class='ctx'>  */</div><div class='del'>-const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {</div><div class='add'>+const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = {</div><div class='ctx'> 	/* ICE_PTP_LNK_SPD_1G */</div><div class='ctx'> 	{</div><div class='ctx'> 		/* tx_par_clk */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c<br/>index a00b55e14aac..187ce9b54e1a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ptp_hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_hw.c</a></div><div class='hunk'>@@ -284,19 +284,19 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_fill_phy_msg_e822 - Fill message data for a PHY register access</div><div class='add'>+ * ice_fill_phy_msg_e82x - Fill message data for a PHY register access</div><div class='ctx'>  * @msg: the PHY message buffer to fill in</div><div class='ctx'>  * @port: the port to access</div><div class='ctx'>  * @offset: the register offset</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='del'>-ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)</div><div class='add'>+ice_fill_phy_msg_e82x(struct ice_sbq_msg_input *msg, u8 port, u16 offset)</div><div class='ctx'> {</div><div class='ctx'> 	int phy_port, phy, quadtype;</div><div class='ctx'> </div><div class='del'>-	phy_port = port % ICE_PORTS_PER_PHY_E822;</div><div class='del'>-	phy = port / ICE_PORTS_PER_PHY_E822;</div><div class='del'>-	quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E822;</div><div class='add'>+	phy_port = port % ICE_PORTS_PER_PHY_E82X;</div><div class='add'>+	phy = port / ICE_PORTS_PER_PHY_E82X;</div><div class='add'>+	quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E82X;</div><div class='ctx'> </div><div class='ctx'> 	if (quadtype == 0) {</div><div class='ctx'> 		msg-&gt;msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);</div><div class='hunk'>@@ -315,7 +315,7 @@ ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register</div><div class='add'>+ * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register</div><div class='ctx'>  * @low_addr: the low address to check</div><div class='ctx'>  * @high_addr: on return, contains the high address of the 64bit register</div><div class='ctx'>  *</div><div class='hunk'>@@ -323,7 +323,7 @@ ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset)</div><div class='ctx'>  * represented as two 32bit registers. If it is, return the appropriate high</div><div class='ctx'>  * register offset to use.</div><div class='ctx'>  */</div><div class='del'>-static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='add'>+static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr)</div><div class='ctx'> {</div><div class='ctx'> 	switch (low_addr) {</div><div class='ctx'> 	case P_REG_PAR_PCS_TX_OFFSET_L:</div><div class='hunk'>@@ -368,7 +368,7 @@ static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register</div><div class='add'>+ * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register</div><div class='ctx'>  * @low_addr: the low address to check</div><div class='ctx'>  * @high_addr: on return, contains the high address of the 40bit value</div><div class='ctx'>  *</div><div class='hunk'>@@ -377,7 +377,7 @@ static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='ctx'>  * upper 32 bits in the high register. If it is, return the appropriate high</div><div class='ctx'>  * register offset to use.</div><div class='ctx'>  */</div><div class='del'>-static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='add'>+static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)</div><div class='ctx'> {</div><div class='ctx'> 	switch (low_addr) {</div><div class='ctx'> 	case P_REG_TIMETUS_L:</div><div class='hunk'>@@ -413,7 +413,7 @@ static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_phy_reg_e822 - Read a PHY register</div><div class='add'>+ * ice_read_phy_reg_e82x - Read a PHY register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: PHY port to read from</div><div class='ctx'>  * @offset: PHY register offset to read</div><div class='hunk'>@@ -422,12 +422,12 @@ static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr)</div><div class='ctx'>  * Read a PHY register for the given port over the device sideband queue.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)</div><div class='add'>+ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input msg = {0};</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	ice_fill_phy_msg_e822(&amp;msg, port, offset);</div><div class='add'>+	ice_fill_phy_msg_e82x(&amp;msg, port, offset);</div><div class='ctx'> 	msg.opcode = ice_sbq_msg_rd;</div><div class='ctx'> </div><div class='ctx'> 	err = ice_sbq_rw_reg(hw, &amp;msg);</div><div class='hunk'>@@ -443,7 +443,7 @@ ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers</div><div class='add'>+ * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: PHY port to read from</div><div class='ctx'>  * @low_addr: offset of the lower register to read from</div><div class='hunk'>@@ -455,7 +455,7 @@ ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val)</div><div class='ctx'>  * known to be two parts of a 64bit value.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)</div><div class='add'>+ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)</div><div class='ctx'> {</div><div class='ctx'> 	u32 low, high;</div><div class='ctx'> 	u16 high_addr;</div><div class='hunk'>@@ -464,20 +464,20 @@ ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)</div><div class='ctx'> 	/* Only operate on registers known to be split into two 32bit</div><div class='ctx'> 	 * registers.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!ice_is_64b_phy_reg_e822(low_addr, &amp;high_addr)) {</div><div class='add'>+	if (!ice_is_64b_phy_reg_e82x(low_addr, &amp;high_addr)) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",</div><div class='ctx'> 			  low_addr);</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, low_addr, &amp;low);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, low_addr, &amp;low);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",</div><div class='ctx'> 			  low_addr, err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, high_addr, &amp;high);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, high_addr, &amp;high);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",</div><div class='ctx'> 			  high_addr, err);</div><div class='hunk'>@@ -490,7 +490,7 @@ ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_phy_reg_e822 - Write a PHY register</div><div class='add'>+ * ice_write_phy_reg_e82x - Write a PHY register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: PHY port to write to</div><div class='ctx'>  * @offset: PHY register offset to write</div><div class='hunk'>@@ -499,12 +499,12 @@ ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)</div><div class='ctx'>  * Write a PHY register for the given port over the device sideband queue.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)</div><div class='add'>+ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input msg = {0};</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	ice_fill_phy_msg_e822(&amp;msg, port, offset);</div><div class='add'>+	ice_fill_phy_msg_e82x(&amp;msg, port, offset);</div><div class='ctx'> 	msg.opcode = ice_sbq_msg_wr;</div><div class='ctx'> 	msg.data = val;</div><div class='ctx'> </div><div class='hunk'>@@ -519,7 +519,7 @@ ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY</div><div class='add'>+ * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: port to write to</div><div class='ctx'>  * @low_addr: offset of the low register</div><div class='hunk'>@@ -529,7 +529,7 @@ ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)</div><div class='ctx'>  * it up into two chunks, the lower 8 bits and the upper 32 bits.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='add'>+ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> {</div><div class='ctx'> 	u32 low, high;</div><div class='ctx'> 	u16 high_addr;</div><div class='hunk'>@@ -538,7 +538,7 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> 	/* Only operate on registers known to be split into a lower 8 bit</div><div class='ctx'> 	 * register and an upper 32 bit register.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!ice_is_40b_phy_reg_e822(low_addr, &amp;high_addr)) {</div><div class='add'>+	if (!ice_is_40b_phy_reg_e82x(low_addr, &amp;high_addr)) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",</div><div class='ctx'> 			  low_addr);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -547,14 +547,14 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> 	low = (u32)(val &amp; P_REG_40B_LOW_M);</div><div class='ctx'> 	high = (u32)(val &gt;&gt; P_REG_40B_HIGH_S);</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, low_addr, low);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, low_addr, low);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",</div><div class='ctx'> 			  low_addr, err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, high_addr, high);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, high_addr, high);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",</div><div class='ctx'> 			  high_addr, err);</div><div class='hunk'>@@ -565,7 +565,7 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers</div><div class='add'>+ * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: PHY port to read from</div><div class='ctx'>  * @low_addr: offset of the lower register to read from</div><div class='hunk'>@@ -577,7 +577,7 @@ ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'>  * a 64bit value.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='add'>+ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> {</div><div class='ctx'> 	u32 low, high;</div><div class='ctx'> 	u16 high_addr;</div><div class='hunk'>@@ -586,7 +586,7 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> 	/* Only operate on registers known to be split into two 32bit</div><div class='ctx'> 	 * registers.</div><div class='ctx'> 	 */</div><div class='del'>-	if (!ice_is_64b_phy_reg_e822(low_addr, &amp;high_addr)) {</div><div class='add'>+	if (!ice_is_64b_phy_reg_e82x(low_addr, &amp;high_addr)) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",</div><div class='ctx'> 			  low_addr);</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -595,14 +595,14 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> 	low = lower_32_bits(val);</div><div class='ctx'> 	high = upper_32_bits(val);</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, low_addr, low);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, low_addr, low);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",</div><div class='ctx'> 			  low_addr, err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, high_addr, high);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, high_addr, high);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",</div><div class='ctx'> 			  high_addr, err);</div><div class='hunk'>@@ -613,7 +613,7 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_fill_quad_msg_e822 - Fill message data for quad register access</div><div class='add'>+ * ice_fill_quad_msg_e82x - Fill message data for quad register access</div><div class='ctx'>  * @msg: the PHY message buffer to fill in</div><div class='ctx'>  * @quad: the quad to access</div><div class='ctx'>  * @offset: the register offset</div><div class='hunk'>@@ -622,7 +622,7 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)</div><div class='ctx'>  * multiple PHYs.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)</div><div class='add'>+ice_fill_quad_msg_e82x(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)</div><div class='ctx'> {</div><div class='ctx'> 	u32 addr;</div><div class='ctx'> </div><div class='hunk'>@@ -631,7 +631,7 @@ ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)</div><div class='ctx'> </div><div class='ctx'> 	msg-&gt;dest_dev = rmn_0;</div><div class='ctx'> </div><div class='del'>-	if ((quad % ICE_QUADS_PER_PHY_E822) == 0)</div><div class='add'>+	if ((quad % ICE_QUADS_PER_PHY_E82X) == 0)</div><div class='ctx'> 		addr = Q_0_BASE + offset;</div><div class='ctx'> 	else</div><div class='ctx'> 		addr = Q_1_BASE + offset;</div><div class='hunk'>@@ -643,7 +643,7 @@ ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_quad_reg_e822 - Read a PHY quad register</div><div class='add'>+ * ice_read_quad_reg_e82x - Read a PHY quad register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: quad to read from</div><div class='ctx'>  * @offset: quad register offset to read</div><div class='hunk'>@@ -653,12 +653,12 @@ ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)</div><div class='ctx'>  * shared between multiple PHYs.</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='del'>-ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)</div><div class='add'>+ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input msg = {0};</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_fill_quad_msg_e822(&amp;msg, quad, offset);</div><div class='add'>+	err = ice_fill_quad_msg_e82x(&amp;msg, quad, offset);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -677,7 +677,7 @@ ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_quad_reg_e822 - Write a PHY quad register</div><div class='add'>+ * ice_write_quad_reg_e82x - Write a PHY quad register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: quad to write to</div><div class='ctx'>  * @offset: quad register offset to write</div><div class='hunk'>@@ -687,12 +687,12 @@ ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)</div><div class='ctx'>  * shared between multiple PHYs.</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='del'>-ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)</div><div class='add'>+ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input msg = {0};</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_fill_quad_msg_e822(&amp;msg, quad, offset);</div><div class='add'>+	err = ice_fill_quad_msg_e82x(&amp;msg, quad, offset);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -710,7 +710,7 @@ ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block</div><div class='add'>+ * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: the quad to read from</div><div class='ctx'>  * @idx: the timestamp index to read</div><div class='hunk'>@@ -721,7 +721,7 @@ ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)</div><div class='ctx'>  * family of devices.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)</div><div class='add'>+ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)</div><div class='ctx'> {</div><div class='ctx'> 	u16 lo_addr, hi_addr;</div><div class='ctx'> 	u32 lo, hi;</div><div class='hunk'>@@ -730,14 +730,14 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)</div><div class='ctx'> 	lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);</div><div class='ctx'> 	hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);</div><div class='ctx'> </div><div class='del'>-	err = ice_read_quad_reg_e822(hw, quad, lo_addr, &amp;lo);</div><div class='add'>+	err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &amp;lo);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",</div><div class='ctx'> 			  err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_quad_reg_e822(hw, quad, hi_addr, &amp;hi);</div><div class='add'>+	err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &amp;hi);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -754,7 +754,7 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block</div><div class='add'>+ * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: the quad to read from</div><div class='ctx'>  * @idx: the timestamp index to reset</div><div class='hunk'>@@ -770,18 +770,18 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)</div><div class='ctx'>  *</div><div class='ctx'>  * To directly clear the contents of the timestamp block entirely, discarding</div><div class='ctx'>  * all timestamp data at once, software should instead use</div><div class='del'>- * ice_ptp_reset_ts_memory_quad_e822().</div><div class='add'>+ * ice_ptp_reset_ts_memory_quad_e82x().</div><div class='ctx'>  *</div><div class='ctx'>  * This function should only be called on an idx whose bit is set according to</div><div class='ctx'>  * ice_get_phy_tx_tstamp_ready().</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)</div><div class='add'>+ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)</div><div class='ctx'> {</div><div class='ctx'> 	u64 unused_tstamp;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_tstamp_e822(hw, quad, idx, &amp;unused_tstamp);</div><div class='add'>+	err = ice_read_phy_tstamp_e82x(hw, quad, idx, &amp;unused_tstamp);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",</div><div class='ctx'> 			  quad, idx, err);</div><div class='hunk'>@@ -792,33 +792,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block</div><div class='add'>+ * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: the quad to read from</div><div class='ctx'>  *</div><div class='ctx'>  * Clear all timestamps from the PHY quad block that is shared between the</div><div class='ctx'>  * internal PHYs on the E822 devices.</div><div class='ctx'>  */</div><div class='del'>-void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad)</div><div class='add'>+void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)</div><div class='ctx'> {</div><div class='del'>-	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);</div><div class='del'>-	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);</div><div class='add'>+	ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);</div><div class='add'>+	ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks</div><div class='add'>+ * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  */</div><div class='del'>-static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)</div><div class='add'>+static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int quad;</div><div class='ctx'> </div><div class='ctx'> 	for (quad = 0; quad &lt; ICE_MAX_QUAD; quad++)</div><div class='del'>-		ice_ptp_reset_ts_memory_quad_e822(hw, quad);</div><div class='add'>+		ice_ptp_reset_ts_memory_quad_e82x(hw, quad);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_cgu_reg_e822 - Read a CGU register</div><div class='add'>+ * ice_read_cgu_reg_e82x - Read a CGU register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @addr: Register address to read</div><div class='ctx'>  * @val: storage for register value read</div><div class='hunk'>@@ -827,7 +827,7 @@ static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)</div><div class='ctx'>  * applicable to E822 devices.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)</div><div class='add'>+ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input cgu_msg;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -850,7 +850,7 @@ ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_write_cgu_reg_e822 - Write a CGU register</div><div class='add'>+ * ice_write_cgu_reg_e82x - Write a CGU register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @addr: Register address to write</div><div class='ctx'>  * @val: value to write into the register</div><div class='hunk'>@@ -859,7 +859,7 @@ ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val)</div><div class='ctx'>  * applicable to E822 devices.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val)</div><div class='add'>+ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_sbq_msg_input cgu_msg;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -925,7 +925,7 @@ static const char *ice_clk_src_str(u8 clk_src)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit</div><div class='add'>+ * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @clk_freq: Clock frequency to program</div><div class='ctx'>  * @clk_src: Clock source to select (TIME_REF, or TCX0)</div><div class='hunk'>@@ -934,7 +934,7 @@ static const char *ice_clk_src_str(u8 clk_src)</div><div class='ctx'>  * time reference, enabling the PLL which drives the PTP hardware clock.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='add'>+ice_cfg_cgu_pll_e82x(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='ctx'> 		     enum ice_clk_src clk_src)</div><div class='ctx'> {</div><div class='ctx'> 	union tspll_ro_bwm_lf bwm_lf;</div><div class='hunk'>@@ -963,15 +963,15 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &amp;dw9.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &amp;dw9.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &amp;dw24.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &amp;dw24.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &amp;bwm_lf.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &amp;bwm_lf.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -986,43 +986,43 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='ctx'> 	if (dw24.field.ts_pll_enable) {</div><div class='ctx'> 		dw24.field.ts_pll_enable = 0;</div><div class='ctx'> </div><div class='del'>-		err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='add'>+		err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set the frequency */</div><div class='ctx'> 	dw9.field.time_ref_freq_sel = clk_freq;</div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Configure the TS PLL feedback divisor */</div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &amp;dw19.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &amp;dw19.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;</div><div class='ctx'> 	dw19.field.tspll_ndivratio = 1;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Configure the TS PLL post divisor */</div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &amp;dw22.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &amp;dw22.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;</div><div class='ctx'> 	dw22.field.time1588clk_sel_div2 = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Configure the TS PLL pre divisor and clock source */</div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &amp;dw24.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &amp;dw24.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1030,21 +1030,21 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='ctx'> 	dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;</div><div class='ctx'> 	dw24.field.time_ref_sel = clk_src;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Finally, enable the PLL */</div><div class='ctx'> 	dw24.field.ts_pll_enable = 1;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	/* Wait to verify if the PLL locks */</div><div class='ctx'> 	usleep_range(1000, 5000);</div><div class='ctx'> </div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &amp;bwm_lf.val);</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &amp;bwm_lf.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1064,18 +1064,18 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_init_cgu_e822 - Initialize CGU with settings from firmware</div><div class='add'>+ * ice_init_cgu_e82x - Initialize CGU with settings from firmware</div><div class='ctx'>  * @hw: pointer to the HW structure</div><div class='ctx'>  *</div><div class='ctx'>  * Initialize the Clock Generation Unit of the E822 device.</div><div class='ctx'>  */</div><div class='del'>-static int ice_init_cgu_e822(struct ice_hw *hw)</div><div class='add'>+static int ice_init_cgu_e82x(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_ts_func_info *ts_info = &amp;hw-&gt;func_caps.ts_func_info;</div><div class='ctx'> 	union tspll_cntr_bist_settings cntr_bist;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,</div><div class='add'>+	err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,</div><div class='ctx'> 				    &amp;cntr_bist.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1084,7 +1084,7 @@ static int ice_init_cgu_e822(struct ice_hw *hw)</div><div class='ctx'> 	cntr_bist.field.i_plllock_sel_0 = 0;</div><div class='ctx'> 	cntr_bist.field.i_plllock_sel_1 = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,</div><div class='add'>+	err = ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,</div><div class='ctx'> 				     cntr_bist.val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1092,7 +1092,7 @@ static int ice_init_cgu_e822(struct ice_hw *hw)</div><div class='ctx'> 	/* Configure the CGU PLL using the parameters from the function</div><div class='ctx'> 	 * capabilities.</div><div class='ctx'> 	 */</div><div class='del'>-	err = ice_cfg_cgu_pll_e822(hw, ts_info-&gt;time_ref,</div><div class='add'>+	err = ice_cfg_cgu_pll_e82x(hw, ts_info-&gt;time_ref,</div><div class='ctx'> 				   (enum ice_clk_src)ts_info-&gt;clk_src);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1113,7 +1113,7 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)</div><div class='ctx'> 	for (port = 0; port &lt; ICE_NUM_EXTERNAL_PORTS; port++) {</div><div class='ctx'> 		int err;</div><div class='ctx'> </div><div class='del'>-		err = ice_write_phy_reg_e822(hw, port, P_REG_WL,</div><div class='add'>+		err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,</div><div class='ctx'> 					     PTP_VERNIER_WL);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",</div><div class='hunk'>@@ -1126,12 +1126,12 @@ static int ice_ptp_set_vernier_wl(struct ice_hw *hw)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization</div><div class='add'>+ * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  *</div><div class='ctx'>  * Perform PHC initialization steps specific to E822 devices.</div><div class='ctx'>  */</div><div class='del'>-static int ice_ptp_init_phc_e822(struct ice_hw *hw)</div><div class='add'>+static int ice_ptp_init_phc_e82x(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 regval;</div><div class='hunk'>@@ -1145,7 +1145,7 @@ static int ice_ptp_init_phc_e822(struct ice_hw *hw)</div><div class='ctx'> 	wr32(hw, PF_SB_REM_DEV_CTL, regval);</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize the Clock Generation Unit */</div><div class='del'>-	err = ice_init_cgu_e822(hw);</div><div class='add'>+	err = ice_init_cgu_e82x(hw);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1154,7 +1154,7 @@ static int ice_ptp_init_phc_e822(struct ice_hw *hw)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time</div><div class='add'>+ * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @time: Time to initialize the PHY port clocks to</div><div class='ctx'>  *</div><div class='hunk'>@@ -1164,7 +1164,7 @@ static int ice_ptp_init_phc_e822(struct ice_hw *hw)</div><div class='ctx'>  * units of nominal nanoseconds.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)</div><div class='add'>+ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)</div><div class='ctx'> {</div><div class='ctx'> 	u64 phy_time;</div><div class='ctx'> 	u8 port;</div><div class='hunk'>@@ -1177,14 +1177,14 @@ ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)</div><div class='ctx'> </div><div class='ctx'> 	for (port = 0; port &lt; ICE_NUM_EXTERNAL_PORTS; port++) {</div><div class='ctx'> 		/* Tx case */</div><div class='del'>-		err = ice_write_64b_phy_reg_e822(hw, port,</div><div class='add'>+		err = ice_write_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 						 P_REG_TX_TIMER_INC_PRE_L,</div><div class='ctx'> 						 phy_time);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto exit_err;</div><div class='ctx'> </div><div class='ctx'> 		/* Rx case */</div><div class='del'>-		err = ice_write_64b_phy_reg_e822(hw, port,</div><div class='add'>+		err = ice_write_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 						 P_REG_RX_TIMER_INC_PRE_L,</div><div class='ctx'> 						 phy_time);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -1201,7 +1201,7 @@ exit_err:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust</div><div class='add'>+ * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @port: Port number to be programmed</div><div class='ctx'>  * @time: time in cycles to adjust the port Tx and Rx clocks</div><div class='hunk'>@@ -1216,7 +1216,7 @@ exit_err:</div><div class='ctx'>  * Negative adjustments are supported using 2s complement arithmetic.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time)</div><div class='add'>+ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time)</div><div class='ctx'> {</div><div class='ctx'> 	u32 l_time, u_time;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -1225,23 +1225,23 @@ ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time)</div><div class='ctx'> 	u_time = upper_32_bits(time);</div><div class='ctx'> </div><div class='ctx'> 	/* Tx case */</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_L,</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,</div><div class='ctx'> 				     l_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto exit_err;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_U,</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,</div><div class='ctx'> 				     u_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto exit_err;</div><div class='ctx'> </div><div class='ctx'> 	/* Rx case */</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_L,</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,</div><div class='ctx'> 				     l_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto exit_err;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_U,</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,</div><div class='ctx'> 				     u_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto exit_err;</div><div class='hunk'>@@ -1255,7 +1255,7 @@ exit_err:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment</div><div class='add'>+ * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @adj: adjustment in nanoseconds</div><div class='ctx'>  *</div><div class='hunk'>@@ -1264,7 +1264,7 @@ exit_err:</div><div class='ctx'>  * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)</div><div class='add'>+ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)</div><div class='ctx'> {</div><div class='ctx'> 	s64 cycles;</div><div class='ctx'> 	u8 port;</div><div class='hunk'>@@ -1281,7 +1281,7 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)</div><div class='ctx'> 	for (port = 0; port &lt; ICE_NUM_EXTERNAL_PORTS; port++) {</div><div class='ctx'> 		int err;</div><div class='ctx'> </div><div class='del'>-		err = ice_ptp_prep_port_adj_e822(hw, port, cycles);</div><div class='add'>+		err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1290,7 +1290,7 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment</div><div class='add'>+ * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @incval: new increment value to prepare</div><div class='ctx'>  *</div><div class='hunk'>@@ -1299,13 +1299,13 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj)</div><div class='ctx'>  * issuing an ICE_PTP_INIT_INCVAL command.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)</div><div class='add'>+ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u8 port;</div><div class='ctx'> </div><div class='ctx'> 	for (port = 0; port &lt; ICE_NUM_EXTERNAL_PORTS; port++) {</div><div class='del'>-		err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L,</div><div class='add'>+		err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,</div><div class='ctx'> 						 incval);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto exit_err;</div><div class='hunk'>@@ -1337,7 +1337,7 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	/* Tx case */</div><div class='del'>-	err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts);</div><div class='add'>+	err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1348,7 +1348,7 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)</div><div class='ctx'> 		  (unsigned long long)*tx_ts);</div><div class='ctx'> </div><div class='ctx'> 	/* Rx case */</div><div class='del'>-	err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts);</div><div class='add'>+	err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1362,7 +1362,7 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_write_port_cmd_e822 - Prepare a single PHY port for a timer command</div><div class='add'>+ * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @port: Port to which cmd has to be sent</div><div class='ctx'>  * @cmd: Command to be sent to the port</div><div class='hunk'>@@ -1372,8 +1372,8 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)</div><div class='ctx'>  * Do not use this function directly. If you want to configure exactly one</div><div class='ctx'>  * port, use ice_ptp_one_port_cmd() instead.</div><div class='ctx'>  */</div><div class='del'>-static int</div><div class='del'>-ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd)</div><div class='add'>+static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,</div><div class='add'>+				       enum ice_ptp_tmr_cmd cmd)</div><div class='ctx'> {</div><div class='ctx'> 	u32 cmd_val, val;</div><div class='ctx'> 	u8 tmr_idx;</div><div class='hunk'>@@ -1403,7 +1403,7 @@ ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd</div><div class='ctx'> </div><div class='ctx'> 	/* Tx case */</div><div class='ctx'> 	/* Read, modify, write */</div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, &amp;val);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, &amp;val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1414,7 +1414,7 @@ ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd</div><div class='ctx'> 	val &amp;= ~TS_CMD_MASK;</div><div class='ctx'> 	val |= cmd_val;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1423,7 +1423,7 @@ ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd</div><div class='ctx'> </div><div class='ctx'> 	/* Rx case */</div><div class='ctx'> 	/* Read, modify, write */</div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, &amp;val);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, &amp;val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1434,7 +1434,7 @@ ice_ptp_write_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd</div><div class='ctx'> 	val &amp;= ~TS_CMD_MASK;</div><div class='ctx'> 	val |= cmd_val;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1469,7 +1469,7 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,</div><div class='ctx'> 		else</div><div class='ctx'> 			cmd = ICE_PTP_NOP;</div><div class='ctx'> </div><div class='del'>-		err = ice_ptp_write_port_cmd_e822(hw, port, cmd);</div><div class='add'>+		err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1478,7 +1478,7 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command</div><div class='add'>+ * ice_ptp_port_cmd_e82x - Prepare all ports for a timer command</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @cmd: timer command to prepare</div><div class='ctx'>  *</div><div class='hunk'>@@ -1486,14 +1486,14 @@ ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,</div><div class='ctx'>  * command.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)</div><div class='add'>+ice_ptp_port_cmd_e82x(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)</div><div class='ctx'> {</div><div class='ctx'> 	u8 port;</div><div class='ctx'> </div><div class='ctx'> 	for (port = 0; port &lt; ICE_NUM_EXTERNAL_PORTS; port++) {</div><div class='ctx'> 		int err;</div><div class='ctx'> </div><div class='del'>-		err = ice_ptp_write_port_cmd_e822(hw, port, cmd);</div><div class='add'>+		err = ice_ptp_write_port_cmd_e82x(hw, port, cmd);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1509,7 +1509,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode</div><div class='add'>+ * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @port: the port to read from</div><div class='ctx'>  * @link_out: if non-NULL, holds link speed on success</div><div class='hunk'>@@ -1519,7 +1519,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)</div><div class='ctx'>  * algorithm.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,</div><div class='add'>+ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port,</div><div class='ctx'> 			       enum ice_ptp_link_spd *link_out,</div><div class='ctx'> 			       enum ice_ptp_fec_mode *fec_out)</div><div class='ctx'> {</div><div class='hunk'>@@ -1528,7 +1528,7 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> 	u32 serdes;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &amp;serdes);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &amp;serdes);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1585,18 +1585,18 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp</div><div class='add'>+ * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @port: to configure the quad for</div><div class='ctx'>  */</div><div class='del'>-static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	enum ice_ptp_link_spd link_spd;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> 	u8 quad;</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_get_speed_and_fec_e822(hw, port, &amp;link_spd, NULL);</div><div class='add'>+	err = ice_phy_get_speed_and_fec_e82x(hw, port, &amp;link_spd, NULL);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1605,7 +1605,7 @@ static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> </div><div class='ctx'> 	quad = port / ICE_PORTS_PER_QUAD;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &amp;val);</div><div class='add'>+	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &amp;val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1617,7 +1617,7 @@ static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);</div><div class='add'>+	err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -1626,7 +1626,7 @@ static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822</div><div class='add'>+ * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822</div><div class='ctx'>  * @hw: pointer to the HW structure</div><div class='ctx'>  * @port: the port to configure</div><div class='ctx'>  *</div><div class='hunk'>@@ -1671,12 +1671,12 @@ static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'>  * a divide by 390,625,000. This does lose some precision, but avoids</div><div class='ctx'>  * miscalculation due to arithmetic overflow.</div><div class='ctx'>  */</div><div class='del'>-static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	u64 cur_freq, clk_incval, tu_per_sec, uix;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));</div><div class='add'>+	cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));</div><div class='ctx'> 	clk_incval = ice_ptp_read_src_incval(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate TUs per second divided by 256 */</div><div class='hunk'>@@ -1688,7 +1688,7 @@ static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	/* Program the 10Gb/40Gb conversion ratio */</div><div class='ctx'> 	uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);</div><div class='ctx'> </div><div class='del'>-	err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,</div><div class='add'>+	err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,</div><div class='ctx'> 					 uix);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",</div><div class='hunk'>@@ -1699,7 +1699,7 @@ static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	/* Program the 25Gb/100Gb conversion ratio */</div><div class='ctx'> 	uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);</div><div class='ctx'> </div><div class='del'>-	err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,</div><div class='add'>+	err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,</div><div class='ctx'> 					 uix);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",</div><div class='hunk'>@@ -1711,7 +1711,7 @@ static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle</div><div class='add'>+ * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: port to configure</div><div class='ctx'>  *</div><div class='hunk'>@@ -1753,18 +1753,18 @@ static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'>  * frequency is ~29 bits, so multiplying them together should fit within the</div><div class='ctx'>  * 64 bit arithmetic.</div><div class='ctx'>  */</div><div class='del'>-static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	u64 cur_freq, clk_incval, tu_per_sec, phy_tus;</div><div class='ctx'> 	enum ice_ptp_link_spd link_spd;</div><div class='ctx'> 	enum ice_ptp_fec_mode fec_mode;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_get_speed_and_fec_e822(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='add'>+	err = ice_phy_get_speed_and_fec_e82x(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));</div><div class='add'>+	cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));</div><div class='ctx'> 	clk_incval = ice_ptp_read_src_incval(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate TUs per cycle of the PHC clock */</div><div class='hunk'>@@ -1784,7 +1784,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1796,7 +1796,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1808,7 +1808,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1820,7 +1820,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1832,7 +1832,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1844,7 +1844,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1856,7 +1856,7 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L,</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,</div><div class='ctx'> 					 phy_tus);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -1868,23 +1868,23 @@ static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	else</div><div class='ctx'> 		phy_tus = 0;</div><div class='ctx'> </div><div class='del'>-	return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L,</div><div class='add'>+	return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L,</div><div class='ctx'> 					  phy_tus);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port</div><div class='add'>+ * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @link_spd: the Link speed to calculate for</div><div class='ctx'>  *</div><div class='ctx'>  * Calculate the fixed offset due to known static latency data.</div><div class='ctx'>  */</div><div class='ctx'> static u64</div><div class='del'>-ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='add'>+ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'> {</div><div class='ctx'> 	u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;</div><div class='ctx'> </div><div class='del'>-	cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));</div><div class='add'>+	cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));</div><div class='ctx'> 	clk_incval = ice_ptp_read_src_incval(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate TUs per second */</div><div class='hunk'>@@ -1904,7 +1904,7 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset</div><div class='add'>+ * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to configure</div><div class='ctx'>  *</div><div class='hunk'>@@ -1926,7 +1926,7 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'>  * Returns zero on success, -EBUSY if the hardware vernier offset</div><div class='ctx'>  * calibration has not completed, or another error code on failure.</div><div class='ctx'>  */</div><div class='del'>-int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	enum ice_ptp_link_spd link_spd;</div><div class='ctx'> 	enum ice_ptp_fec_mode fec_mode;</div><div class='hunk'>@@ -1935,7 +1935,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	/* Nothing to do if we've already programmed the offset */</div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, &amp;reg);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, &amp;reg);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",</div><div class='ctx'> 			  port, err);</div><div class='hunk'>@@ -1945,7 +1945,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	if (reg)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &amp;reg);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, &amp;reg);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",</div><div class='ctx'> 			  port, err);</div><div class='hunk'>@@ -1955,11 +1955,11 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	if (!(reg &amp; P_REG_TX_OV_STATUS_OV_M))</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_get_speed_and_fec_e822(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='add'>+	err = ice_phy_get_speed_and_fec_e82x(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);</div><div class='add'>+	total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd);</div><div class='ctx'> </div><div class='ctx'> 	/* Read the first Vernier offset from the PHY register and add it to</div><div class='ctx'> 	 * the total offset.</div><div class='hunk'>@@ -1970,7 +1970,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_25G_RS ||</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_40G ||</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_50G) {</div><div class='del'>-		err = ice_read_64b_phy_reg_e822(hw, port,</div><div class='add'>+		err = ice_read_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 						P_REG_PAR_PCS_TX_OFFSET_L,</div><div class='ctx'> 						&amp;val);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -1985,7 +1985,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_100G_RS) {</div><div class='del'>-		err = ice_read_64b_phy_reg_e822(hw, port,</div><div class='add'>+		err = ice_read_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 						P_REG_PAR_TX_TIME_L,</div><div class='ctx'> 						&amp;val);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -1998,12 +1998,12 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	 * PHY and indicate that the Tx offset is ready. After this,</div><div class='ctx'> 	 * timestamps will be enabled.</div><div class='ctx'> 	 */</div><div class='del'>-	err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,</div><div class='add'>+	err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,</div><div class='ctx'> 					 total_offset);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2014,7 +2014,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx</div><div class='add'>+ * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to adjust for</div><div class='ctx'>  * @link_spd: the current link speed of the PHY</div><div class='hunk'>@@ -2026,7 +2026,7 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'>  * various delays caused when receiving a packet.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='add'>+ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port,</div><div class='ctx'> 			  enum ice_ptp_link_spd link_spd,</div><div class='ctx'> 			  enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)</div><div class='ctx'> {</div><div class='hunk'>@@ -2035,7 +2035,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> 	u32 val;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &amp;val);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &amp;val);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",</div><div class='ctx'> 			  err);</div><div class='hunk'>@@ -2044,7 +2044,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> </div><div class='ctx'> 	pmd_align = (u8)val;</div><div class='ctx'> </div><div class='del'>-	cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));</div><div class='add'>+	cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));</div><div class='ctx'> 	clk_incval = ice_ptp_read_src_incval(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate TUs per second */</div><div class='hunk'>@@ -2123,7 +2123,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> 		u64 cycle_adj;</div><div class='ctx'> 		u8 rx_cycle;</div><div class='ctx'> </div><div class='del'>-		err = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT,</div><div class='add'>+		err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,</div><div class='ctx'> 					    &amp;val);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",</div><div class='hunk'>@@ -2145,7 +2145,7 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> 		u64 cycle_adj;</div><div class='ctx'> 		u8 rx_cycle;</div><div class='ctx'> </div><div class='del'>-		err = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT,</div><div class='add'>+		err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,</div><div class='ctx'> 					    &amp;val);</div><div class='ctx'> 		if (err) {</div><div class='ctx'> 			ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",</div><div class='hunk'>@@ -2172,18 +2172,18 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port</div><div class='add'>+ * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port</div><div class='ctx'>  * @hw: pointer to HW struct</div><div class='ctx'>  * @link_spd: The Link speed to calculate for</div><div class='ctx'>  *</div><div class='ctx'>  * Determine the fixed Rx latency for a given link speed.</div><div class='ctx'>  */</div><div class='ctx'> static u64</div><div class='del'>-ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='add'>+ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'> {</div><div class='ctx'> 	u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;</div><div class='ctx'> </div><div class='del'>-	cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw));</div><div class='add'>+	cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));</div><div class='ctx'> 	clk_incval = ice_ptp_read_src_incval(hw);</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate TUs per second */</div><div class='hunk'>@@ -2203,7 +2203,7 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset</div><div class='add'>+ * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to configure</div><div class='ctx'>  *</div><div class='hunk'>@@ -2229,7 +2229,7 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)</div><div class='ctx'>  * Returns zero on success, -EBUSY if the hardware vernier offset</div><div class='ctx'>  * calibration has not completed, or another error code on failure.</div><div class='ctx'>  */</div><div class='del'>-int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	enum ice_ptp_link_spd link_spd;</div><div class='ctx'> 	enum ice_ptp_fec_mode fec_mode;</div><div class='hunk'>@@ -2238,7 +2238,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	/* Nothing to do if we've already programmed the offset */</div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, &amp;reg);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, &amp;reg);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",</div><div class='ctx'> 			  port, err);</div><div class='hunk'>@@ -2248,7 +2248,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	if (reg)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &amp;reg);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, &amp;reg);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",</div><div class='ctx'> 			  port, err);</div><div class='hunk'>@@ -2258,16 +2258,16 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	if (!(reg &amp; P_REG_RX_OV_STATUS_OV_M))</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_get_speed_and_fec_e822(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='add'>+	err = ice_phy_get_speed_and_fec_e82x(hw, port, &amp;link_spd, &amp;fec_mode);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);</div><div class='add'>+	total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd);</div><div class='ctx'> </div><div class='ctx'> 	/* Read the first Vernier offset from the PHY register and add it to</div><div class='ctx'> 	 * the total offset.</div><div class='ctx'> 	 */</div><div class='del'>-	err = ice_read_64b_phy_reg_e822(hw, port,</div><div class='add'>+	err = ice_read_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 					P_REG_PAR_PCS_RX_OFFSET_L,</div><div class='ctx'> 					&amp;val);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -2282,7 +2282,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_50G ||</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_50G_RS ||</div><div class='ctx'> 	    link_spd == ICE_PTP_LNK_SPD_100G_RS) {</div><div class='del'>-		err = ice_read_64b_phy_reg_e822(hw, port,</div><div class='add'>+		err = ice_read_64b_phy_reg_e82x(hw, port,</div><div class='ctx'> 						P_REG_PAR_RX_TIME_L,</div><div class='ctx'> 						&amp;val);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -2292,7 +2292,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* In addition, Rx must account for the PMD alignment */</div><div class='del'>-	err = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &amp;pmd);</div><div class='add'>+	err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &amp;pmd);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2308,12 +2308,12 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	 * PHY and indicate that the Rx offset is ready. After this,</div><div class='ctx'> 	 * timestamps will be enabled.</div><div class='ctx'> 	 */</div><div class='del'>-	err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,</div><div class='add'>+	err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,</div><div class='ctx'> 					 total_offset);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2324,7 +2324,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time</div><div class='add'>+ * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to read</div><div class='ctx'>  * @phy_time: on return, the 64bit PHY timer value</div><div class='hunk'>@@ -2334,7 +2334,7 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'>  * and PHC timer values.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,</div><div class='add'>+ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time,</div><div class='ctx'> 			       u64 *phc_time)</div><div class='ctx'> {</div><div class='ctx'> 	u64 tx_time, rx_time;</div><div class='hunk'>@@ -2381,7 +2381,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer</div><div class='add'>+ * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to synchronize</div><div class='ctx'>  *</div><div class='hunk'>@@ -2392,7 +2392,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,</div><div class='ctx'>  * to the PHY timer in order to ensure it reads the same value as the</div><div class='ctx'>  * primary PHC timer.</div><div class='ctx'>  */</div><div class='del'>-static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	u64 phc_time, phy_time, difference;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -2402,7 +2402,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_and_phc_time_e822(hw, port, &amp;phy_time, &amp;phc_time);</div><div class='add'>+	err = ice_read_phy_and_phc_time_e82x(hw, port, &amp;phy_time, &amp;phc_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -2416,7 +2416,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	 */</div><div class='ctx'> 	difference = phc_time - phy_time;</div><div class='ctx'> </div><div class='del'>-	err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference);</div><div class='add'>+	err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -2433,7 +2433,7 @@ static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	/* Re-capture the timer values to flush the command registers and</div><div class='ctx'> 	 * verify that the time was properly adjusted.</div><div class='ctx'> 	 */</div><div class='del'>-	err = ice_read_phy_and_phc_time_e822(hw, port, &amp;phy_time, &amp;phc_time);</div><div class='add'>+	err = ice_read_phy_and_phc_time_e82x(hw, port, &amp;phy_time, &amp;phc_time);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_unlock;</div><div class='ctx'> </div><div class='hunk'>@@ -2452,7 +2452,7 @@ err_unlock:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_stop_phy_timer_e822 - Stop the PHY clock timer</div><div class='add'>+ * ice_stop_phy_timer_e82x - Stop the PHY clock timer</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to stop</div><div class='ctx'>  * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS</div><div class='hunk'>@@ -2462,36 +2462,36 @@ err_unlock:</div><div class='ctx'>  * initialized or when link speed changes.</div><div class='ctx'>  */</div><div class='ctx'> int</div><div class='del'>-ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)</div><div class='add'>+ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &amp;val);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &amp;val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val &amp;= ~P_REG_PS_START_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val &amp;= ~P_REG_PS_ENA_CLK_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	if (soft_reset) {</div><div class='ctx'> 		val |= P_REG_PS_SFT_RESET_M;</div><div class='del'>-		err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+		err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2502,7 +2502,7 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_start_phy_timer_e822 - Start the PHY clock timer</div><div class='add'>+ * ice_start_phy_timer_e82x - Start the PHY clock timer</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @port: the PHY port to start</div><div class='ctx'>  *</div><div class='hunk'>@@ -2512,7 +2512,7 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)</div><div class='ctx'>  *</div><div class='ctx'>  * Hardware will take Vernier measurements on Tx or Rx of packets.</div><div class='ctx'>  */</div><div class='del'>-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='add'>+int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port)</div><div class='ctx'> {</div><div class='ctx'> 	u32 lo, hi, val;</div><div class='ctx'> 	u64 incval;</div><div class='hunk'>@@ -2521,17 +2521,17 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> </div><div class='ctx'> 	tmr_idx = ice_get_ptp_src_clock_index(hw);</div><div class='ctx'> </div><div class='del'>-	err = ice_stop_phy_timer_e822(hw, port, false);</div><div class='add'>+	err = ice_stop_phy_timer_e82x(hw, port, false);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	ice_phy_cfg_lane_e822(hw, port);</div><div class='add'>+	ice_phy_cfg_lane_e82x(hw, port);</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_cfg_uix_e822(hw, port);</div><div class='add'>+	err = ice_phy_cfg_uix_e82x(hw, port);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = ice_phy_cfg_parpcs_e822(hw, port);</div><div class='add'>+	err = ice_phy_cfg_parpcs_e82x(hw, port);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2539,7 +2539,7 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));</div><div class='ctx'> 	incval = (u64)hi &lt;&lt; 32 | lo;</div><div class='ctx'> </div><div class='del'>-	err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval);</div><div class='add'>+	err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2552,22 +2552,22 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> </div><div class='ctx'> 	ice_ptp_exec_tmr_cmd(hw);</div><div class='ctx'> </div><div class='del'>-	err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &amp;val);</div><div class='add'>+	err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &amp;val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val |= P_REG_PS_SFT_RESET_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val |= P_REG_PS_START_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val &amp;= ~P_REG_PS_SFT_RESET_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2578,18 +2578,18 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> 	ice_ptp_exec_tmr_cmd(hw);</div><div class='ctx'> </div><div class='ctx'> 	val |= P_REG_PS_ENA_CLK_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	val |= P_REG_PS_LOAD_OFFSET_M;</div><div class='del'>-	err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);</div><div class='add'>+	err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	ice_ptp_exec_tmr_cmd(hw);</div><div class='ctx'> </div><div class='del'>-	err = ice_sync_phy_timer_e822(hw, port);</div><div class='add'>+	err = ice_sync_phy_timer_e82x(hw, port);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2599,7 +2599,7 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register</div><div class='add'>+ * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register</div><div class='ctx'>  * @hw: pointer to the HW struct</div><div class='ctx'>  * @quad: the timestamp quad to read from</div><div class='ctx'>  * @tstamp_ready: contents of the Tx memory status register</div><div class='hunk'>@@ -2609,19 +2609,19 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)</div><div class='ctx'>  * ready to be captured from the PHY timestamp block.</div><div class='ctx'>  */</div><div class='ctx'> static int</div><div class='del'>-ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)</div><div class='add'>+ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)</div><div class='ctx'> {</div><div class='ctx'> 	u32 hi, lo;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &amp;hi);</div><div class='add'>+	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &amp;hi);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",</div><div class='ctx'> 			  quad, err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &amp;lo);</div><div class='add'>+	err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &amp;lo);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",</div><div class='ctx'> 			  quad, err);</div><div class='hunk'>@@ -3307,7 +3307,7 @@ void ice_ptp_init_phy_model(struct ice_hw *hw)</div><div class='ctx'> 	if (ice_is_e810(hw))</div><div class='ctx'> 		hw-&gt;phy_model = ICE_PHY_E810;</div><div class='ctx'> 	else</div><div class='del'>-		hw-&gt;phy_model = ICE_PHY_E822;</div><div class='add'>+		hw-&gt;phy_model = ICE_PHY_E82X;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3332,8 +3332,8 @@ static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		err = ice_ptp_port_cmd_e810(hw, cmd);</div><div class='ctx'> 		break;</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		err = ice_ptp_port_cmd_e822(hw, cmd);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		err = ice_ptp_port_cmd_e82x(hw, cmd);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='hunk'>@@ -3384,8 +3384,8 @@ int ice_ptp_init_time(struct ice_hw *hw, u64 time)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		err = ice_ptp_prep_phy_time_e810(hw, time &amp; 0xFFFFFFFF);</div><div class='ctx'> 		break;</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		err = ice_ptp_prep_phy_time_e822(hw, time &amp; 0xFFFFFFFF);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		err = ice_ptp_prep_phy_time_e82x(hw, time &amp; 0xFFFFFFFF);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='hunk'>@@ -3426,8 +3426,8 @@ int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		err = ice_ptp_prep_phy_incval_e810(hw, incval);</div><div class='ctx'> 		break;</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		err = ice_ptp_prep_phy_incval_e822(hw, incval);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		err = ice_ptp_prep_phy_incval_e82x(hw, incval);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='hunk'>@@ -3492,8 +3492,8 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		err = ice_ptp_prep_phy_adj_e810(hw, adj);</div><div class='ctx'> 		break;</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		err = ice_ptp_prep_phy_adj_e822(hw, adj);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		err = ice_ptp_prep_phy_adj_e82x(hw, adj);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='hunk'>@@ -3521,8 +3521,8 @@ int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)</div><div class='ctx'> 	switch (hw-&gt;phy_model) {</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3549,8 +3549,8 @@ int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)</div><div class='ctx'> 	switch (hw-&gt;phy_model) {</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		return ice_clear_phy_tstamp_e810(hw, block, idx);</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		return ice_clear_phy_tstamp_e822(hw, block, idx);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		return ice_clear_phy_tstamp_e82x(hw, block, idx);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3608,8 +3608,8 @@ static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)</div><div class='ctx'> void ice_ptp_reset_ts_memory(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	switch (hw-&gt;phy_model) {</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		ice_ptp_reset_ts_memory_e822(hw);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		ice_ptp_reset_ts_memory_e82x(hw);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -3636,8 +3636,8 @@ int ice_ptp_init_phc(struct ice_hw *hw)</div><div class='ctx'> 	switch (hw-&gt;phy_model) {</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		return ice_ptp_init_phc_e810(hw);</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		return ice_ptp_init_phc_e822(hw);</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		return ice_ptp_init_phc_e82x(hw);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3660,8 +3660,8 @@ int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)</div><div class='ctx'> 	case ICE_PHY_E810:</div><div class='ctx'> 		return ice_get_phy_tx_tstamp_ready_e810(hw, block,</div><div class='ctx'> 							tstamp_ready);</div><div class='del'>-	case ICE_PHY_E822:</div><div class='del'>-		return ice_get_phy_tx_tstamp_ready_e822(hw, block,</div><div class='add'>+	case ICE_PHY_E82X:</div><div class='add'>+		return ice_get_phy_tx_tstamp_ready_e82x(hw, block,</div><div class='ctx'> 							tstamp_ready);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -3942,7 +3942,7 @@ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)</div><div class='ctx'> 	case ICE_DEV_ID_E823C_QSFP:</div><div class='ctx'> 	case ICE_DEV_ID_E823C_SFP:</div><div class='ctx'> 	case ICE_DEV_ID_E823C_SGMII:</div><div class='del'>-		*pin_num = ICE_E822_RCLK_PINS_NUM;</div><div class='add'>+		*pin_num = ICE_E82X_RCLK_PINS_NUM;</div><div class='ctx'> 		ret = 0;</div><div class='ctx'> 		if (hw-&gt;cgu_part_number ==</div><div class='ctx'> 		    ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h<br/>index cf76701566c7..1f3e03124430 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_ptp_hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_ptp_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_ptp_hw.h</a></div><div class='hunk'>@@ -42,7 +42,7 @@ enum ice_ptp_fec_mode {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct ice_time_ref_info_e822</div><div class='add'>+ * struct ice_time_ref_info_e82x</div><div class='ctx'>  * @pll_freq: Frequency of PLL that drives timer ticks in Hz</div><div class='ctx'>  * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L</div><div class='ctx'>  * @pps_delay: propagation delay of the PPS output signal</div><div class='hunk'>@@ -50,14 +50,14 @@ enum ice_ptp_fec_mode {</div><div class='ctx'>  * Characteristic information for the various TIME_REF sources possible in the</div><div class='ctx'>  * E822 devices</div><div class='ctx'>  */</div><div class='del'>-struct ice_time_ref_info_e822 {</div><div class='add'>+struct ice_time_ref_info_e82x {</div><div class='ctx'> 	u64 pll_freq;</div><div class='ctx'> 	u64 nominal_incval;</div><div class='ctx'> 	u8 pps_delay;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct ice_vernier_info_e822</div><div class='add'>+ * struct ice_vernier_info_e82x</div><div class='ctx'>  * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS</div><div class='ctx'>  * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS</div><div class='ctx'>  * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS</div><div class='hunk'>@@ -80,7 +80,7 @@ struct ice_time_ref_info_e822 {</div><div class='ctx'>  * different link speeds, either the deskew marker for multi-lane link speeds</div><div class='ctx'>  * or the Reed Solomon gearbox marker for RS-FEC.</div><div class='ctx'>  */</div><div class='del'>-struct ice_vernier_info_e822 {</div><div class='add'>+struct ice_vernier_info_e82x {</div><div class='ctx'> 	u32 tx_par_clk;</div><div class='ctx'> 	u32 rx_par_clk;</div><div class='ctx'> 	u32 tx_pcs_clk;</div><div class='hunk'>@@ -95,7 +95,7 @@ struct ice_vernier_info_e822 {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * struct ice_cgu_pll_params_e822</div><div class='add'>+ * struct ice_cgu_pll_params_e82x</div><div class='ctx'>  * @refclk_pre_div: Reference clock pre-divisor</div><div class='ctx'>  * @feedback_div: Feedback divisor</div><div class='ctx'>  * @frac_n_div: Fractional divisor</div><div class='hunk'>@@ -104,7 +104,7 @@ struct ice_vernier_info_e822 {</div><div class='ctx'>  * Clock Generation Unit parameters used to program the PLL based on the</div><div class='ctx'>  * selected TIME_REF frequency.</div><div class='ctx'>  */</div><div class='del'>-struct ice_cgu_pll_params_e822 {</div><div class='add'>+struct ice_cgu_pll_params_e82x {</div><div class='ctx'> 	u32 refclk_pre_div;</div><div class='ctx'> 	u32 feedback_div;</div><div class='ctx'> 	u32 frac_n_div;</div><div class='hunk'>@@ -124,7 +124,7 @@ enum ice_phy_rclk_pins {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define ICE_E810_RCLK_PINS_NUM		(ICE_RCLKB_PIN + 1)</div><div class='del'>-#define ICE_E822_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)</div><div class='add'>+#define ICE_E82X_RCLK_PINS_NUM		(ICE_RCLKA_PIN + 1)</div><div class='ctx'> #define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \</div><div class='ctx'> 					  (_pin) + ZL_REF1P)</div><div class='ctx'> </div><div class='hunk'>@@ -183,16 +183,16 @@ struct ice_cgu_pin_desc {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern const struct</div><div class='del'>-ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];</div><div class='add'>+ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];</div><div class='ctx'> </div><div class='ctx'> #define E810C_QSFP_C827_0_HANDLE 2</div><div class='ctx'> #define E810C_QSFP_C827_1_HANDLE 3</div><div class='ctx'> </div><div class='ctx'> /* Table of constants related to possible TIME_REF sources */</div><div class='del'>-extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];</div><div class='add'>+extern const struct ice_time_ref_info_e82x e822_time_ref[NUM_ICE_TIME_REF_FREQ];</div><div class='ctx'> </div><div class='ctx'> /* Table of constants for Vernier calibration on E822 */</div><div class='del'>-extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];</div><div class='add'>+extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];</div><div class='ctx'> </div><div class='ctx'> /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for</div><div class='ctx'>  * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.</div><div class='hunk'>@@ -215,23 +215,23 @@ int ice_ptp_init_phc(struct ice_hw *hw);</div><div class='ctx'> int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);</div><div class='ctx'> </div><div class='ctx'> /* E822 family functions */</div><div class='del'>-int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);</div><div class='del'>-int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);</div><div class='del'>-void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);</div><div class='add'>+int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);</div><div class='add'>+int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);</div><div class='add'>+void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_e822_time_ref - Get the current TIME_REF from capabilities</div><div class='add'>+ * ice_e82x_time_ref - Get the current TIME_REF from capabilities</div><div class='ctx'>  * @hw: pointer to the HW structure</div><div class='ctx'>  *</div><div class='ctx'>  * Returns the current TIME_REF from the capabilities structure.</div><div class='ctx'>  */</div><div class='del'>-static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)</div><div class='add'>+static inline enum ice_time_ref_freq ice_e82x_time_ref(struct ice_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	return hw-&gt;func_caps.ts_func_info.time_ref;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_set_e822_time_ref - Set new TIME_REF</div><div class='add'>+ * ice_set_e82x_time_ref - Set new TIME_REF</div><div class='ctx'>  * @hw: pointer to the HW structure</div><div class='ctx'>  * @time_ref: new TIME_REF to set</div><div class='ctx'>  *</div><div class='hunk'>@@ -239,31 +239,31 @@ static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)</div><div class='ctx'>  * change, such as an update to the CGU registers.</div><div class='ctx'>  */</div><div class='ctx'> static inline void</div><div class='del'>-ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)</div><div class='add'>+ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)</div><div class='ctx'> {</div><div class='ctx'> 	hw-&gt;func_caps.ts_func_info.time_ref = time_ref;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)</div><div class='add'>+static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)</div><div class='ctx'> {</div><div class='ctx'> 	return e822_time_ref[time_ref].pll_freq;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)</div><div class='add'>+static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)</div><div class='ctx'> {</div><div class='ctx'> 	return e822_time_ref[time_ref].nominal_incval;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)</div><div class='add'>+static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref)</div><div class='ctx'> {</div><div class='ctx'> 	return e822_time_ref[time_ref].pps_delay;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* E822 Vernier calibration functions */</div><div class='del'>-int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);</div><div class='del'>-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);</div><div class='del'>-int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);</div><div class='del'>-int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);</div><div class='add'>+int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);</div><div class='add'>+int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);</div><div class='add'>+int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);</div><div class='add'>+int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);</div><div class='ctx'> </div><div class='ctx'> /* E810 family functions */</div><div class='ctx'> int ice_ptp_init_phy_e810(struct ice_hw *hw);</div><div class='hunk'>@@ -509,6 +509,7 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,</div><div class='ctx'> #define TS_LL_READ_RETRIES		200</div><div class='ctx'> #define TS_LL_READ_TS_HIGH		GENMASK(23, 16)</div><div class='ctx'> #define TS_LL_READ_TS_IDX		GENMASK(29, 24)</div><div class='add'>+#define TS_LL_READ_TS_INTR		BIT(30)</div><div class='ctx'> #define TS_LL_READ_TS			BIT(31)</div><div class='ctx'> </div><div class='ctx'> /* Internal PHY timestamp address */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_repr.c b/drivers/net/ethernet/intel/ice/ice_repr.c<br/>index c686ac0935eb..5f30fb131f74 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_repr.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_repr.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_repr.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_repr.c</a></div><div class='hunk'>@@ -14,7 +14,7 @@</div><div class='ctx'>  */</div><div class='ctx'> static int ice_repr_get_sw_port_id(struct ice_repr *repr)</div><div class='ctx'> {</div><div class='del'>-	return repr-&gt;vf-&gt;pf-&gt;hw.port_info-&gt;lport;</div><div class='add'>+	return repr-&gt;src_vsi-&gt;back-&gt;hw.port_info-&gt;lport;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -35,7 +35,7 @@ ice_repr_get_phys_port_name(struct net_device *netdev, char *buf, size_t len)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	res = snprintf(buf, len, "pf%dvfr%d", ice_repr_get_sw_port_id(repr),</div><div class='del'>-		       repr-&gt;vf-&gt;vf_id);</div><div class='add'>+		       repr-&gt;id);</div><div class='ctx'> 	if (res &lt;= 0)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -278,25 +278,67 @@ ice_repr_reg_netdev(struct net_device *netdev)</div><div class='ctx'> 	return register_netdev(netdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ice_repr_remove_node(struct devlink_port *devlink_port)</div><div class='add'>+{</div><div class='add'>+	devl_lock(devlink_port-&gt;devlink);</div><div class='add'>+	devl_rate_leaf_destroy(devlink_port);</div><div class='add'>+	devl_unlock(devlink_port-&gt;devlink);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='del'>- * ice_repr_add - add representor for VF</div><div class='del'>- * @vf: pointer to VF structure</div><div class='add'>+ * ice_repr_rem - remove representor from VF</div><div class='add'>+ * @repr: pointer to representor structure</div><div class='ctx'>  */</div><div class='del'>-static int ice_repr_add(struct ice_vf *vf)</div><div class='add'>+static void ice_repr_rem(struct ice_repr *repr)</div><div class='add'>+{</div><div class='add'>+	kfree(repr-&gt;q_vector);</div><div class='add'>+	free_netdev(repr-&gt;netdev);</div><div class='add'>+	kfree(repr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_repr_rem_vf - remove representor from VF</div><div class='add'>+ * @repr: pointer to representor structure</div><div class='add'>+ */</div><div class='add'>+void ice_repr_rem_vf(struct ice_repr *repr)</div><div class='add'>+{</div><div class='add'>+	ice_repr_remove_node(&amp;repr-&gt;vf-&gt;devlink_port);</div><div class='add'>+	unregister_netdev(repr-&gt;netdev);</div><div class='add'>+	ice_devlink_destroy_vf_port(repr-&gt;vf);</div><div class='add'>+	ice_virtchnl_set_dflt_ops(repr-&gt;vf);</div><div class='add'>+	ice_repr_rem(repr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ice_repr_set_tx_topology(struct ice_pf *pf)</div><div class='add'>+{</div><div class='add'>+	struct devlink *devlink;</div><div class='add'>+</div><div class='add'>+	/* only export if ADQ and DCB disabled and eswitch enabled*/</div><div class='add'>+	if (ice_is_adq_active(pf) || ice_is_dcb_active(pf) ||</div><div class='add'>+	    !ice_is_switchdev_running(pf))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	devlink = priv_to_devlink(pf);</div><div class='add'>+	ice_devlink_rate_init_tx_topology(devlink, ice_get_main_vsi(pf));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_repr_add - add representor for generic VSI</div><div class='add'>+ * @pf: pointer to PF structure</div><div class='add'>+ * @src_vsi: pointer to VSI structure of device to represent</div><div class='add'>+ * @parent_mac: device MAC address</div><div class='add'>+ */</div><div class='add'>+static struct ice_repr *</div><div class='add'>+ice_repr_add(struct ice_pf *pf, struct ice_vsi *src_vsi, const u8 *parent_mac)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_q_vector *q_vector;</div><div class='ctx'> 	struct ice_netdev_priv *np;</div><div class='ctx'> 	struct ice_repr *repr;</div><div class='del'>-	struct ice_vsi *vsi;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	vsi = ice_get_vf_vsi(vf);</div><div class='del'>-	if (!vsi)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='ctx'> 	repr = kzalloc(sizeof(*repr), GFP_KERNEL);</div><div class='ctx'> 	if (!repr)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='ctx'> </div><div class='ctx'> 	repr-&gt;netdev = alloc_etherdev(sizeof(struct ice_netdev_priv));</div><div class='ctx'> 	if (!repr-&gt;netdev) {</div><div class='hunk'>@@ -304,9 +346,7 @@ static int ice_repr_add(struct ice_vf *vf)</div><div class='ctx'> 		goto err_alloc;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	repr-&gt;src_vsi = vsi;</div><div class='del'>-	repr-&gt;vf = vf;</div><div class='del'>-	vf-&gt;repr = repr;</div><div class='add'>+	repr-&gt;src_vsi = src_vsi;</div><div class='ctx'> 	np = netdev_priv(repr-&gt;netdev);</div><div class='ctx'> 	np-&gt;repr = repr;</div><div class='ctx'> </div><div class='hunk'>@@ -316,10 +356,40 @@ static int ice_repr_add(struct ice_vf *vf)</div><div class='ctx'> 		goto err_alloc_q_vector;</div><div class='ctx'> 	}</div><div class='ctx'> 	repr-&gt;q_vector = q_vector;</div><div class='add'>+	repr-&gt;q_id = repr-&gt;id;</div><div class='add'>+</div><div class='add'>+	ether_addr_copy(repr-&gt;parent_mac, parent_mac);</div><div class='add'>+</div><div class='add'>+	return repr;</div><div class='add'>+</div><div class='add'>+err_alloc_q_vector:</div><div class='add'>+	free_netdev(repr-&gt;netdev);</div><div class='add'>+err_alloc:</div><div class='add'>+	kfree(repr);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct ice_repr *ice_repr_add_vf(struct ice_vf *vf)</div><div class='add'>+{</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+	struct ice_vsi *vsi;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	vsi = ice_get_vf_vsi(vf);</div><div class='add'>+	if (!vsi)</div><div class='add'>+		return ERR_PTR(-ENOENT);</div><div class='ctx'> </div><div class='ctx'> 	err = ice_devlink_create_vf_port(vf);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto err_devlink;</div><div class='add'>+		return ERR_PTR(err);</div><div class='add'>+</div><div class='add'>+	repr = ice_repr_add(vf-&gt;pf, vsi, vf-&gt;hw_lan_addr);</div><div class='add'>+	if (IS_ERR(repr)) {</div><div class='add'>+		err = PTR_ERR(repr);</div><div class='add'>+		goto err_repr_add;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	repr-&gt;vf = vf;</div><div class='ctx'> </div><div class='ctx'> 	repr-&gt;netdev-&gt;min_mtu = ETH_MIN_MTU;</div><div class='ctx'> 	repr-&gt;netdev-&gt;max_mtu = ICE_MAX_MTU;</div><div class='hunk'>@@ -331,100 +401,23 @@ static int ice_repr_add(struct ice_vf *vf)</div><div class='ctx'> 		goto err_netdev;</div><div class='ctx'> </div><div class='ctx'> 	ice_virtchnl_set_repr_ops(vf);</div><div class='add'>+	ice_repr_set_tx_topology(vf-&gt;pf);</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='add'>+	return repr;</div><div class='ctx'> </div><div class='ctx'> err_netdev:</div><div class='add'>+	ice_repr_rem(repr);</div><div class='add'>+err_repr_add:</div><div class='ctx'> 	ice_devlink_destroy_vf_port(vf);</div><div class='del'>-err_devlink:</div><div class='del'>-	kfree(repr-&gt;q_vector);</div><div class='del'>-	vf-&gt;repr-&gt;q_vector = NULL;</div><div class='del'>-err_alloc_q_vector:</div><div class='del'>-	free_netdev(repr-&gt;netdev);</div><div class='del'>-	repr-&gt;netdev = NULL;</div><div class='del'>-err_alloc:</div><div class='del'>-	kfree(repr);</div><div class='del'>-	vf-&gt;repr = NULL;</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * ice_repr_rem - remove representor from VF</div><div class='del'>- * @vf: pointer to VF structure</div><div class='del'>- */</div><div class='del'>-static void ice_repr_rem(struct ice_vf *vf)</div><div class='del'>-{</div><div class='del'>-	if (!vf-&gt;repr)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	kfree(vf-&gt;repr-&gt;q_vector);</div><div class='del'>-	vf-&gt;repr-&gt;q_vector = NULL;</div><div class='del'>-	unregister_netdev(vf-&gt;repr-&gt;netdev);</div><div class='del'>-	ice_devlink_destroy_vf_port(vf);</div><div class='del'>-	free_netdev(vf-&gt;repr-&gt;netdev);</div><div class='del'>-	vf-&gt;repr-&gt;netdev = NULL;</div><div class='del'>-	kfree(vf-&gt;repr);</div><div class='del'>-	vf-&gt;repr = NULL;</div><div class='del'>-</div><div class='del'>-	ice_virtchnl_set_dflt_ops(vf);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * ice_repr_rem_from_all_vfs - remove port representor for all VFs</div><div class='del'>- * @pf: pointer to PF structure</div><div class='del'>- */</div><div class='del'>-void ice_repr_rem_from_all_vfs(struct ice_pf *pf)</div><div class='del'>-{</div><div class='del'>-	struct devlink *devlink;</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='del'>-</div><div class='del'>-	ice_for_each_vf(pf, bkt, vf)</div><div class='del'>-		ice_repr_rem(vf);</div><div class='del'>-</div><div class='del'>-	/* since all port representors are destroyed, there is</div><div class='del'>-	 * no point in keeping the nodes</div><div class='del'>-	 */</div><div class='del'>-	devlink = priv_to_devlink(pf);</div><div class='del'>-	devl_lock(devlink);</div><div class='del'>-	devl_rate_nodes_destroy(devlink);</div><div class='del'>-	devl_unlock(devlink);</div><div class='add'>+	return ERR_PTR(err);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/**</div><div class='del'>- * ice_repr_add_for_all_vfs - add port representor for all VFs</div><div class='del'>- * @pf: pointer to PF structure</div><div class='del'>- */</div><div class='del'>-int ice_repr_add_for_all_vfs(struct ice_pf *pf)</div><div class='add'>+struct ice_repr *ice_repr_get_by_vsi(struct ice_vsi *vsi)</div><div class='ctx'> {</div><div class='del'>-	struct devlink *devlink;</div><div class='del'>-	struct ice_vf *vf;</div><div class='del'>-	unsigned int bkt;</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	lockdep_assert_held(&amp;pf-&gt;vfs.table_lock);</div><div class='del'>-</div><div class='del'>-	ice_for_each_vf(pf, bkt, vf) {</div><div class='del'>-		err = ice_repr_add(vf);</div><div class='del'>-		if (err)</div><div class='del'>-			goto err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* only export if ADQ and DCB disabled */</div><div class='del'>-	if (ice_is_adq_active(pf) || ice_is_dcb_active(pf))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	devlink = priv_to_devlink(pf);</div><div class='del'>-	ice_devlink_rate_init_tx_topology(devlink, ice_get_main_vsi(pf));</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err:</div><div class='del'>-	ice_repr_rem_from_all_vfs(pf);</div><div class='add'>+	if (!vsi-&gt;vf)</div><div class='add'>+		return NULL;</div><div class='ctx'> </div><div class='del'>-	return err;</div><div class='add'>+	return xa_load(&amp;vsi-&gt;back-&gt;eswitch.reprs, vsi-&gt;vf-&gt;repr_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_repr.h b/drivers/net/ethernet/intel/ice/ice_repr.h<br/>index e1ee2d2c1d2d..f9aede315716 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_repr.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_repr.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_repr.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_repr.h</a></div><div class='hunk'>@@ -13,14 +13,17 @@ struct ice_repr {</div><div class='ctx'> 	struct net_device *netdev;</div><div class='ctx'> 	struct metadata_dst *dst;</div><div class='ctx'> 	struct ice_esw_br_port *br_port;</div><div class='add'>+	int q_id;</div><div class='add'>+	u32 id;</div><div class='add'>+	u8 parent_mac[ETH_ALEN];</div><div class='ctx'> #ifdef CONFIG_ICE_SWITCHDEV</div><div class='ctx'> 	/* info about slow path rule */</div><div class='ctx'> 	struct ice_rule_query_data sp_rule;</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-int ice_repr_add_for_all_vfs(struct ice_pf *pf);</div><div class='del'>-void ice_repr_rem_from_all_vfs(struct ice_pf *pf);</div><div class='add'>+struct ice_repr *ice_repr_add_vf(struct ice_vf *vf);</div><div class='add'>+void ice_repr_rem_vf(struct ice_repr *repr);</div><div class='ctx'> </div><div class='ctx'> void ice_repr_start_tx_queues(struct ice_repr *repr);</div><div class='ctx'> void ice_repr_stop_tx_queues(struct ice_repr *repr);</div><div class='hunk'>@@ -29,4 +32,6 @@ void ice_repr_set_traffic_vsi(struct ice_repr *repr, struct ice_vsi *vsi);</div><div class='ctx'> </div><div class='ctx'> struct ice_repr *ice_netdev_to_repr(struct net_device *netdev);</div><div class='ctx'> bool ice_is_port_repr_netdev(const struct net_device *netdev);</div><div class='add'>+</div><div class='add'>+struct ice_repr *ice_repr_get_by_vsi(struct ice_vsi *vsi);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_sched.c b/drivers/net/ethernet/intel/ice/ice_sched.c<br/>index 2f4a621254e8..d174a4eeb899 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_sched.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_sched.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_sched.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_sched.c</a></div><div class='hunk'>@@ -1387,8 +1387,7 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)</div><div class='ctx'> 	u32 val, clk_src;</div><div class='ctx'> </div><div class='ctx'> 	val = rd32(hw, GLGEN_CLKSTAT_SRC);</div><div class='del'>-	clk_src = (val &amp; GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) &gt;&gt;</div><div class='del'>-		GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S;</div><div class='add'>+	clk_src = FIELD_GET(GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M, val);</div><div class='ctx'> </div><div class='ctx'> #define PSM_CLK_SRC_367_MHZ 0x0</div><div class='ctx'> #define PSM_CLK_SRC_416_MHZ 0x1</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_sriov.c b/drivers/net/ethernet/intel/ice/ice_sriov.c<br/>index 2a5e6616cc0a..a94a1c48c3de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_sriov.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_sriov.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_sriov.c</a></div><div class='hunk'>@@ -106,10 +106,8 @@ static void ice_dis_vf_mappings(struct ice_vf *vf)</div><div class='ctx'> 	for (v = first; v &lt;= last; v++) {</div><div class='ctx'> 		u32 reg;</div><div class='ctx'> </div><div class='del'>-		reg = (((1 &lt;&lt; GLINT_VECT2FUNC_IS_PF_S) &amp;</div><div class='del'>-			GLINT_VECT2FUNC_IS_PF_M) |</div><div class='del'>-		       ((hw-&gt;pf_id &lt;&lt; GLINT_VECT2FUNC_PF_NUM_S) &amp;</div><div class='del'>-			GLINT_VECT2FUNC_PF_NUM_M));</div><div class='add'>+		reg = FIELD_PREP(GLINT_VECT2FUNC_IS_PF_M, 1) |</div><div class='add'>+		      FIELD_PREP(GLINT_VECT2FUNC_PF_NUM_M, hw-&gt;pf_id);</div><div class='ctx'> 		wr32(hw, GLINT_VECT2FUNC(v), reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -172,13 +170,14 @@ void ice_free_vfs(struct ice_pf *pf)</div><div class='ctx'> 	else</div><div class='ctx'> 		dev_warn(dev, "VFs are assigned - not disabling SR-IOV\n");</div><div class='ctx'> </div><div class='del'>-	mutex_lock(&amp;vfs-&gt;table_lock);</div><div class='add'>+	ice_eswitch_reserve_cp_queues(pf, -ice_get_num_vfs(pf));</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_release(pf);</div><div class='add'>+	mutex_lock(&amp;vfs-&gt;table_lock);</div><div class='ctx'> </div><div class='ctx'> 	ice_for_each_vf(pf, bkt, vf) {</div><div class='ctx'> 		mutex_lock(&amp;vf-&gt;cfg_lock);</div><div class='ctx'> </div><div class='add'>+		ice_eswitch_detach(pf, vf);</div><div class='ctx'> 		ice_dis_vf_qs(vf);</div><div class='ctx'> </div><div class='ctx'> 		if (test_bit(ICE_VF_STATE_INIT, vf-&gt;vf_states)) {</div><div class='hunk'>@@ -274,24 +273,20 @@ static void ice_ena_vf_msix_mappings(struct ice_vf *vf)</div><div class='ctx'> 		(device_based_first_msix + vf-&gt;num_msix) - 1;</div><div class='ctx'> 	device_based_vf_id = vf-&gt;vf_id + hw-&gt;func_caps.vf_base_id;</div><div class='ctx'> </div><div class='del'>-	reg = (((device_based_first_msix &lt;&lt; VPINT_ALLOC_FIRST_S) &amp;</div><div class='del'>-		VPINT_ALLOC_FIRST_M) |</div><div class='del'>-	       ((device_based_last_msix &lt;&lt; VPINT_ALLOC_LAST_S) &amp;</div><div class='del'>-		VPINT_ALLOC_LAST_M) | VPINT_ALLOC_VALID_M);</div><div class='add'>+	reg = FIELD_PREP(VPINT_ALLOC_FIRST_M, device_based_first_msix) |</div><div class='add'>+	      FIELD_PREP(VPINT_ALLOC_LAST_M, device_based_last_msix) |</div><div class='add'>+	      VPINT_ALLOC_VALID_M;</div><div class='ctx'> 	wr32(hw, VPINT_ALLOC(vf-&gt;vf_id), reg);</div><div class='ctx'> </div><div class='del'>-	reg = (((device_based_first_msix &lt;&lt; VPINT_ALLOC_PCI_FIRST_S)</div><div class='del'>-		 &amp; VPINT_ALLOC_PCI_FIRST_M) |</div><div class='del'>-	       ((device_based_last_msix &lt;&lt; VPINT_ALLOC_PCI_LAST_S) &amp;</div><div class='del'>-		VPINT_ALLOC_PCI_LAST_M) | VPINT_ALLOC_PCI_VALID_M);</div><div class='add'>+	reg = FIELD_PREP(VPINT_ALLOC_PCI_FIRST_M, device_based_first_msix) |</div><div class='add'>+	      FIELD_PREP(VPINT_ALLOC_PCI_LAST_M, device_based_last_msix) |</div><div class='add'>+	      VPINT_ALLOC_PCI_VALID_M;</div><div class='ctx'> 	wr32(hw, VPINT_ALLOC_PCI(vf-&gt;vf_id), reg);</div><div class='ctx'> </div><div class='ctx'> 	/* map the interrupts to its functions */</div><div class='ctx'> 	for (v = pf_based_first_msix; v &lt;= pf_based_last_msix; v++) {</div><div class='del'>-		reg = (((device_based_vf_id &lt;&lt; GLINT_VECT2FUNC_VF_NUM_S) &amp;</div><div class='del'>-			GLINT_VECT2FUNC_VF_NUM_M) |</div><div class='del'>-		       ((hw-&gt;pf_id &lt;&lt; GLINT_VECT2FUNC_PF_NUM_S) &amp;</div><div class='del'>-			GLINT_VECT2FUNC_PF_NUM_M));</div><div class='add'>+		reg = FIELD_PREP(GLINT_VECT2FUNC_VF_NUM_M, device_based_vf_id) |</div><div class='add'>+		      FIELD_PREP(GLINT_VECT2FUNC_PF_NUM_M, hw-&gt;pf_id);</div><div class='ctx'> 		wr32(hw, GLINT_VECT2FUNC(v), reg);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -324,10 +319,8 @@ static void ice_ena_vf_q_mappings(struct ice_vf *vf, u16 max_txq, u16 max_rxq)</div><div class='ctx'> 		 * VFNUMQ value should be set to (number of queues - 1). A value</div><div class='ctx'> 		 * of 0 means 1 queue and a value of 255 means 256 queues</div><div class='ctx'> 		 */</div><div class='del'>-		reg = (((vsi-&gt;txq_map[0] &lt;&lt; VPLAN_TX_QBASE_VFFIRSTQ_S) &amp;</div><div class='del'>-			VPLAN_TX_QBASE_VFFIRSTQ_M) |</div><div class='del'>-		       (((max_txq - 1) &lt;&lt; VPLAN_TX_QBASE_VFNUMQ_S) &amp;</div><div class='del'>-			VPLAN_TX_QBASE_VFNUMQ_M));</div><div class='add'>+		reg = FIELD_PREP(VPLAN_TX_QBASE_VFFIRSTQ_M, vsi-&gt;txq_map[0]) |</div><div class='add'>+		      FIELD_PREP(VPLAN_TX_QBASE_VFNUMQ_M, max_txq - 1);</div><div class='ctx'> 		wr32(hw, VPLAN_TX_QBASE(vf-&gt;vf_id), reg);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev_err(dev, "Scattered mode for VF Tx queues is not yet implemented\n");</div><div class='hunk'>@@ -342,10 +335,8 @@ static void ice_ena_vf_q_mappings(struct ice_vf *vf, u16 max_txq, u16 max_rxq)</div><div class='ctx'> 		 * VFNUMQ value should be set to (number of queues - 1). A value</div><div class='ctx'> 		 * of 0 means 1 queue and a value of 255 means 256 queues</div><div class='ctx'> 		 */</div><div class='del'>-		reg = (((vsi-&gt;rxq_map[0] &lt;&lt; VPLAN_RX_QBASE_VFFIRSTQ_S) &amp;</div><div class='del'>-			VPLAN_RX_QBASE_VFFIRSTQ_M) |</div><div class='del'>-		       (((max_rxq - 1) &lt;&lt; VPLAN_RX_QBASE_VFNUMQ_S) &amp;</div><div class='del'>-			VPLAN_RX_QBASE_VFNUMQ_M));</div><div class='add'>+		reg = FIELD_PREP(VPLAN_RX_QBASE_VFFIRSTQ_M, vsi-&gt;rxq_map[0]) |</div><div class='add'>+		      FIELD_PREP(VPLAN_RX_QBASE_VFNUMQ_M, max_rxq - 1);</div><div class='ctx'> 		wr32(hw, VPLAN_RX_QBASE(vf-&gt;vf_id), reg);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev_err(dev, "Scattered mode for VF Rx queues is not yet implemented\n");</div><div class='hunk'>@@ -374,16 +365,11 @@ static void ice_ena_vf_mappings(struct ice_vf *vf)</div><div class='ctx'>  */</div><div class='ctx'> int ice_calc_vf_reg_idx(struct ice_vf *vf, struct ice_q_vector *q_vector)</div><div class='ctx'> {</div><div class='del'>-	struct ice_pf *pf;</div><div class='del'>-</div><div class='ctx'> 	if (!vf || !q_vector)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	pf = vf-&gt;pf;</div><div class='del'>-</div><div class='ctx'> 	/* always add one to account for the OICR being the first MSIX */</div><div class='del'>-	return pf-&gt;sriov_base_vector + pf-&gt;vfs.num_msix_per * vf-&gt;vf_id +</div><div class='del'>-		q_vector-&gt;v_idx + 1;</div><div class='add'>+	return vf-&gt;first_vector_idx + q_vector-&gt;v_idx + 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -614,6 +600,14 @@ static int ice_start_vfs(struct ice_pf *pf)</div><div class='ctx'> 			goto teardown;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		retval = ice_eswitch_attach(pf, vf);</div><div class='add'>+		if (retval) {</div><div class='add'>+			dev_err(ice_pf_to_dev(pf), "Failed to attach VF %d to eswitch, error %d",</div><div class='add'>+				vf-&gt;vf_id, retval);</div><div class='add'>+			ice_vf_vsi_release(vf);</div><div class='add'>+			goto teardown;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		set_bit(ICE_VF_STATE_INIT, vf-&gt;vf_states);</div><div class='ctx'> 		ice_ena_vf_mappings(vf);</div><div class='ctx'> 		wr32(hw, VFGEN_RSTAT(vf-&gt;vf_id), VIRTCHNL_VFR_VFACTIVE);</div><div class='hunk'>@@ -768,24 +762,6 @@ static void ice_sriov_clear_reset_trigger(struct ice_vf *vf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_sriov_create_vsi - Create a new VSI for a VF</div><div class='del'>- * @vf: VF to create the VSI for</div><div class='del'>- *</div><div class='del'>- * This is called by ice_vf_recreate_vsi to create the new VSI after the old</div><div class='del'>- * VSI has been released.</div><div class='del'>- */</div><div class='del'>-static int ice_sriov_create_vsi(struct ice_vf *vf)</div><div class='del'>-{</div><div class='del'>-	struct ice_vsi *vsi;</div><div class='del'>-</div><div class='del'>-	vsi = ice_vf_vsi_setup(vf);</div><div class='del'>-	if (!vsi)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ice_sriov_post_vsi_rebuild - tasks to do after the VF's VSI have been rebuilt</div><div class='ctx'>  * @vf: VF to perform tasks on</div><div class='ctx'>  */</div><div class='hunk'>@@ -804,7 +780,6 @@ static const struct ice_vf_ops ice_sriov_vf_ops = {</div><div class='ctx'> 	.poll_reset_status = ice_sriov_poll_reset_status,</div><div class='ctx'> 	.clear_reset_trigger = ice_sriov_clear_reset_trigger,</div><div class='ctx'> 	.irq_close = NULL,</div><div class='del'>-	.create_vsi = ice_sriov_create_vsi,</div><div class='ctx'> 	.post_vsi_rebuild = ice_sriov_post_vsi_rebuild,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -923,6 +898,7 @@ static int ice_ena_vfs(struct ice_pf *pf, u16 num_vfs)</div><div class='ctx'> 		goto err_unroll_sriov;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ice_eswitch_reserve_cp_queues(pf, num_vfs);</div><div class='ctx'> 	ret = ice_start_vfs(pf);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_err(dev, "Failed to start %d VFs, err %d\n", num_vfs, ret);</div><div class='hunk'>@@ -932,12 +908,6 @@ static int ice_ena_vfs(struct ice_pf *pf, u16 num_vfs)</div><div class='ctx'> </div><div class='ctx'> 	clear_bit(ICE_VF_DIS, pf-&gt;state);</div><div class='ctx'> </div><div class='del'>-	ret = ice_eswitch_configure(pf);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(dev, "Failed to configure eswitch, err %d\n", ret);</div><div class='del'>-		goto err_unroll_sriov;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* rearm global interrupts */</div><div class='ctx'> 	if (test_and_clear_bit(ICE_OICR_INTR_DIS, pf-&gt;state))</div><div class='ctx'> 		ice_irq_dynamic_ena(hw, NULL, NULL);</div><div class='hunk'>@@ -1152,8 +1122,7 @@ int ice_sriov_set_msix_vec_count(struct pci_dev *vf_dev, int msix_vec_count)</div><div class='ctx'> 	if (vf-&gt;first_vector_idx &lt; 0)</div><div class='ctx'> 		goto unroll;</div><div class='ctx'> </div><div class='del'>-	ice_vf_vsi_release(vf);</div><div class='del'>-	if (vf-&gt;vf_ops-&gt;create_vsi(vf)) {</div><div class='add'>+	if (ice_vf_reconfig_vsi(vf)) {</div><div class='ctx'> 		/* Try to rebuild with previous values */</div><div class='ctx'> 		needs_rebuild = true;</div><div class='ctx'> 		goto unroll;</div><div class='hunk'>@@ -1180,7 +1149,7 @@ unroll:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (needs_rebuild)</div><div class='del'>-		vf-&gt;vf_ops-&gt;create_vsi(vf);</div><div class='add'>+		ice_vf_reconfig_vsi(vf);</div><div class='ctx'> </div><div class='ctx'> 	ice_ena_vf_mappings(vf);</div><div class='ctx'> 	ice_put_vf(vf);</div><div class='hunk'>@@ -1329,8 +1298,7 @@ ice_vf_lan_overflow_event(struct ice_pf *pf, struct ice_rq_event_info *event)</div><div class='ctx'> 	dev_dbg(ice_pf_to_dev(pf), "GLDCB_RTCTQ: 0x%08x\n", gldcb_rtctq);</div><div class='ctx'> </div><div class='ctx'> 	/* event returns device global Rx queue number */</div><div class='del'>-	queue = (gldcb_rtctq &amp; GLDCB_RTCTQ_RXQNUM_M) &gt;&gt;</div><div class='del'>-		GLDCB_RTCTQ_RXQNUM_S;</div><div class='add'>+	queue = FIELD_GET(GLDCB_RTCTQ_RXQNUM_M, gldcb_rtctq);</div><div class='ctx'> </div><div class='ctx'> 	vf = ice_get_vf_from_pfq(pf, ice_globalq_to_pfq(pf, queue));</div><div class='ctx'> 	if (!vf)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_switch.c b/drivers/net/ethernet/intel/ice/ice_switch.c<br/>index ee19f3aa3d19..f84bab80ca42 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_switch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_switch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_switch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_switch.c</a></div><div class='hunk'>@@ -2492,25 +2492,24 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,</div><div class='ctx'> </div><div class='ctx'> 	switch (f_info-&gt;fltr_act) {</div><div class='ctx'> 	case ICE_FWD_TO_VSI:</div><div class='del'>-		act |= (f_info-&gt;fwd_id.hw_vsi_id &lt;&lt; ICE_SINGLE_ACT_VSI_ID_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_VSI_ID_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M,</div><div class='add'>+				  f_info-&gt;fwd_id.hw_vsi_id);</div><div class='ctx'> 		if (f_info-&gt;lkup_type != ICE_SW_LKUP_VLAN)</div><div class='ctx'> 			act |= ICE_SINGLE_ACT_VSI_FORWARDING |</div><div class='ctx'> 				ICE_SINGLE_ACT_VALID_BIT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_FWD_TO_VSI_LIST:</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_VSI_LIST;</div><div class='del'>-		act |= (f_info-&gt;fwd_id.vsi_list_id &lt;&lt;</div><div class='del'>-			ICE_SINGLE_ACT_VSI_LIST_ID_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_VSI_LIST_ID_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_LIST_ID_M,</div><div class='add'>+				  f_info-&gt;fwd_id.vsi_list_id);</div><div class='ctx'> 		if (f_info-&gt;lkup_type != ICE_SW_LKUP_VLAN)</div><div class='ctx'> 			act |= ICE_SINGLE_ACT_VSI_FORWARDING |</div><div class='ctx'> 				ICE_SINGLE_ACT_VALID_BIT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_FWD_TO_Q:</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_TO_Q;</div><div class='del'>-		act |= (f_info-&gt;fwd_id.q_id &lt;&lt; ICE_SINGLE_ACT_Q_INDEX_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_Q_INDEX_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M,</div><div class='add'>+				  f_info-&gt;fwd_id.q_id);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_DROP_PACKET:</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |</div><div class='hunk'>@@ -2520,10 +2519,9 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,</div><div class='ctx'> 		q_rgn = f_info-&gt;qgrp_size &gt; 0 ?</div><div class='ctx'> 			(u8)ilog2(f_info-&gt;qgrp_size) : 0;</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_TO_Q;</div><div class='del'>-		act |= (f_info-&gt;fwd_id.q_id &lt;&lt; ICE_SINGLE_ACT_Q_INDEX_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_Q_INDEX_M;</div><div class='del'>-		act |= (q_rgn &lt;&lt; ICE_SINGLE_ACT_Q_REGION_S) &amp;</div><div class='del'>-			ICE_SINGLE_ACT_Q_REGION_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M,</div><div class='add'>+				  f_info-&gt;fwd_id.q_id);</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_REGION_M, q_rgn);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -2649,7 +2647,7 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,</div><div class='ctx'> 		m_ent-&gt;fltr_info.fwd_id.hw_vsi_id;</div><div class='ctx'> </div><div class='ctx'> 	act = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;</div><div class='del'>-	act |= (id &lt;&lt; ICE_LG_ACT_VSI_LIST_ID_S) &amp; ICE_LG_ACT_VSI_LIST_ID_M;</div><div class='add'>+	act |= FIELD_PREP(ICE_LG_ACT_VSI_LIST_ID_M, id);</div><div class='ctx'> 	if (m_ent-&gt;vsi_count &gt; 1)</div><div class='ctx'> 		act |= ICE_LG_ACT_VSI_LIST;</div><div class='ctx'> 	lg_act-&gt;act[0] = cpu_to_le32(act);</div><div class='hunk'>@@ -2657,16 +2655,15 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,</div><div class='ctx'> 	/* Second action descriptor type */</div><div class='ctx'> 	act = ICE_LG_ACT_GENERIC;</div><div class='ctx'> </div><div class='del'>-	act |= (1 &lt;&lt; ICE_LG_ACT_GENERIC_VALUE_S) &amp; ICE_LG_ACT_GENERIC_VALUE_M;</div><div class='add'>+	act |= FIELD_PREP(ICE_LG_ACT_GENERIC_VALUE_M, 1);</div><div class='ctx'> 	lg_act-&gt;act[1] = cpu_to_le32(act);</div><div class='ctx'> </div><div class='del'>-	act = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX &lt;&lt;</div><div class='del'>-	       ICE_LG_ACT_GENERIC_OFFSET_S) &amp; ICE_LG_ACT_GENERIC_OFFSET_M;</div><div class='add'>+	act = FIELD_PREP(ICE_LG_ACT_GENERIC_OFFSET_M,</div><div class='add'>+			 ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX);</div><div class='ctx'> </div><div class='ctx'> 	/* Third action Marker value */</div><div class='ctx'> 	act |= ICE_LG_ACT_GENERIC;</div><div class='del'>-	act |= (sw_marker &lt;&lt; ICE_LG_ACT_GENERIC_VALUE_S) &amp;</div><div class='del'>-		ICE_LG_ACT_GENERIC_VALUE_M;</div><div class='add'>+	act |= FIELD_PREP(ICE_LG_ACT_GENERIC_VALUE_M, sw_marker);</div><div class='ctx'> </div><div class='ctx'> 	lg_act-&gt;act[2] = cpu_to_le32(act);</div><div class='ctx'> </div><div class='hunk'>@@ -2675,9 +2672,9 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,</div><div class='ctx'> 			 ice_aqc_opc_update_sw_rules);</div><div class='ctx'> </div><div class='ctx'> 	/* Update the action to point to the large action ID */</div><div class='del'>-	rx_tx-&gt;act = cpu_to_le32(ICE_SINGLE_ACT_PTR |</div><div class='del'>-				 ((l_id &lt;&lt; ICE_SINGLE_ACT_PTR_VAL_S) &amp;</div><div class='del'>-				  ICE_SINGLE_ACT_PTR_VAL_M));</div><div class='add'>+	act = ICE_SINGLE_ACT_PTR;</div><div class='add'>+	act |= FIELD_PREP(ICE_SINGLE_ACT_PTR_VAL_M, l_id);</div><div class='add'>+	rx_tx-&gt;act = cpu_to_le32(act);</div><div class='ctx'> </div><div class='ctx'> 	/* Use the filter rule ID of the previously created rule with single</div><div class='ctx'> 	 * act. Once the update happens, hardware will treat this as large</div><div class='hunk'>@@ -4426,8 +4423,8 @@ ice_alloc_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='ctx'> 	buf-&gt;num_elems = cpu_to_le16(num_items);</div><div class='del'>-	buf-&gt;res_type = cpu_to_le16(((type &lt;&lt; ICE_AQC_RES_TYPE_S) &amp;</div><div class='del'>-				      ICE_AQC_RES_TYPE_M) | alloc_shared);</div><div class='add'>+	buf-&gt;res_type = cpu_to_le16(FIELD_PREP(ICE_AQC_RES_TYPE_M, type) |</div><div class='add'>+				    alloc_shared);</div><div class='ctx'> </div><div class='ctx'> 	status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -4454,8 +4451,8 @@ ice_free_res_cntr(struct ice_hw *hw, u8 type, u8 alloc_shared, u16 num_items,</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='ctx'> 	buf-&gt;num_elems = cpu_to_le16(num_items);</div><div class='del'>-	buf-&gt;res_type = cpu_to_le16(((type &lt;&lt; ICE_AQC_RES_TYPE_S) &amp;</div><div class='del'>-				      ICE_AQC_RES_TYPE_M) | alloc_shared);</div><div class='add'>+	buf-&gt;res_type = cpu_to_le16(FIELD_PREP(ICE_AQC_RES_TYPE_M, type) |</div><div class='add'>+				    alloc_shared);</div><div class='ctx'> 	buf-&gt;elem[0].e.sw_resp = cpu_to_le16(counter_id);</div><div class='ctx'> </div><div class='ctx'> 	status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res);</div><div class='hunk'>@@ -4481,18 +4478,15 @@ int ice_share_res(struct ice_hw *hw, u16 type, u8 shared, u16 res_id)</div><div class='ctx'> {</div><div class='ctx'> 	DEFINE_FLEX(struct ice_aqc_alloc_free_res_elem, buf, elem, 1);</div><div class='ctx'> 	u16 buf_len = __struct_size(buf);</div><div class='add'>+	u16 res_type;</div><div class='ctx'> 	int status;</div><div class='ctx'> </div><div class='ctx'> 	buf-&gt;num_elems = cpu_to_le16(1);</div><div class='add'>+	res_type = FIELD_PREP(ICE_AQC_RES_TYPE_M, type);</div><div class='ctx'> 	if (shared)</div><div class='del'>-		buf-&gt;res_type = cpu_to_le16(((type &lt;&lt; ICE_AQC_RES_TYPE_S) &amp;</div><div class='del'>-					     ICE_AQC_RES_TYPE_M) |</div><div class='del'>-					    ICE_AQC_RES_TYPE_FLAG_SHARED);</div><div class='del'>-	else</div><div class='del'>-		buf-&gt;res_type = cpu_to_le16(((type &lt;&lt; ICE_AQC_RES_TYPE_S) &amp;</div><div class='del'>-					     ICE_AQC_RES_TYPE_M) &amp;</div><div class='del'>-					    ~ICE_AQC_RES_TYPE_FLAG_SHARED);</div><div class='add'>+		res_type |= ICE_AQC_RES_TYPE_FLAG_SHARED;</div><div class='ctx'> </div><div class='add'>+	buf-&gt;res_type = cpu_to_le16(res_type);</div><div class='ctx'> 	buf-&gt;elem[0].e.sw_resp = cpu_to_le16(res_id);</div><div class='ctx'> 	status = ice_aq_alloc_free_res(hw, buf, buf_len,</div><div class='ctx'> 				       ice_aqc_opc_share_res);</div><div class='hunk'>@@ -5024,8 +5018,8 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,</div><div class='ctx'> 			entry-&gt;chain_idx = chain_idx;</div><div class='ctx'> 			content-&gt;result_indx =</div><div class='ctx'> 				ICE_AQ_RECIPE_RESULT_EN |</div><div class='del'>-				((chain_idx &lt;&lt; ICE_AQ_RECIPE_RESULT_DATA_S) &amp;</div><div class='del'>-				 ICE_AQ_RECIPE_RESULT_DATA_M);</div><div class='add'>+				FIELD_PREP(ICE_AQ_RECIPE_RESULT_DATA_M,</div><div class='add'>+					   chain_idx);</div><div class='ctx'> 			clear_bit(chain_idx, result_idx_bm);</div><div class='ctx'> 			chain_idx = find_first_bit(result_idx_bm,</div><div class='ctx'> 						   ICE_MAX_FV_WORDS);</div><div class='hunk'>@@ -6065,6 +6059,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,</div><div class='ctx'> 	      rinfo-&gt;sw_act.fltr_act == ICE_FWD_TO_Q ||</div><div class='ctx'> 	      rinfo-&gt;sw_act.fltr_act == ICE_FWD_TO_QGRP ||</div><div class='ctx'> 	      rinfo-&gt;sw_act.fltr_act == ICE_DROP_PACKET ||</div><div class='add'>+	      rinfo-&gt;sw_act.fltr_act == ICE_MIRROR_PACKET ||</div><div class='ctx'> 	      rinfo-&gt;sw_act.fltr_act == ICE_NOP)) {</div><div class='ctx'> 		status = -EIO;</div><div class='ctx'> 		goto free_pkt_profile;</div><div class='hunk'>@@ -6077,9 +6072,11 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rinfo-&gt;sw_act.fltr_act == ICE_FWD_TO_VSI ||</div><div class='del'>-	    rinfo-&gt;sw_act.fltr_act == ICE_NOP)</div><div class='add'>+	    rinfo-&gt;sw_act.fltr_act == ICE_MIRROR_PACKET ||</div><div class='add'>+	    rinfo-&gt;sw_act.fltr_act == ICE_NOP) {</div><div class='ctx'> 		rinfo-&gt;sw_act.fwd_id.hw_vsi_id =</div><div class='ctx'> 			ice_get_hw_vsi_num(hw, vsi_handle);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (rinfo-&gt;src_vsi)</div><div class='ctx'> 		rinfo-&gt;sw_act.src = ice_get_hw_vsi_num(hw, rinfo-&gt;src_vsi);</div><div class='hunk'>@@ -6115,38 +6112,45 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,</div><div class='ctx'> 		status = -ENOMEM;</div><div class='ctx'> 		goto free_pkt_profile;</div><div class='ctx'> 	}</div><div class='del'>-	if (!rinfo-&gt;flags_info.act_valid) {</div><div class='del'>-		act |= ICE_SINGLE_ACT_LAN_ENABLE;</div><div class='del'>-		act |= ICE_SINGLE_ACT_LB_ENABLE;</div><div class='del'>-	} else {</div><div class='del'>-		act |= rinfo-&gt;flags_info.act &amp; (ICE_SINGLE_ACT_LAN_ENABLE |</div><div class='del'>-						ICE_SINGLE_ACT_LB_ENABLE);</div><div class='add'>+</div><div class='add'>+	if (rinfo-&gt;sw_act.fltr_act != ICE_MIRROR_PACKET) {</div><div class='add'>+		if (!rinfo-&gt;flags_info.act_valid) {</div><div class='add'>+			act |= ICE_SINGLE_ACT_LAN_ENABLE;</div><div class='add'>+			act |= ICE_SINGLE_ACT_LB_ENABLE;</div><div class='add'>+		} else {</div><div class='add'>+			act |= rinfo-&gt;flags_info.act &amp; (ICE_SINGLE_ACT_LAN_ENABLE |</div><div class='add'>+							ICE_SINGLE_ACT_LB_ENABLE);</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (rinfo-&gt;sw_act.fltr_act) {</div><div class='ctx'> 	case ICE_FWD_TO_VSI:</div><div class='del'>-		act |= (rinfo-&gt;sw_act.fwd_id.hw_vsi_id &lt;&lt;</div><div class='del'>-			ICE_SINGLE_ACT_VSI_ID_S) &amp; ICE_SINGLE_ACT_VSI_ID_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M,</div><div class='add'>+				  rinfo-&gt;sw_act.fwd_id.hw_vsi_id);</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_VALID_BIT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_FWD_TO_Q:</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_TO_Q;</div><div class='del'>-		act |= (rinfo-&gt;sw_act.fwd_id.q_id &lt;&lt; ICE_SINGLE_ACT_Q_INDEX_S) &amp;</div><div class='del'>-		       ICE_SINGLE_ACT_Q_INDEX_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M,</div><div class='add'>+				  rinfo-&gt;sw_act.fwd_id.q_id);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_FWD_TO_QGRP:</div><div class='ctx'> 		q_rgn = rinfo-&gt;sw_act.qgrp_size &gt; 0 ?</div><div class='ctx'> 			(u8)ilog2(rinfo-&gt;sw_act.qgrp_size) : 0;</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_TO_Q;</div><div class='del'>-		act |= (rinfo-&gt;sw_act.fwd_id.q_id &lt;&lt; ICE_SINGLE_ACT_Q_INDEX_S) &amp;</div><div class='del'>-		       ICE_SINGLE_ACT_Q_INDEX_M;</div><div class='del'>-		act |= (q_rgn &lt;&lt; ICE_SINGLE_ACT_Q_REGION_S) &amp;</div><div class='del'>-		       ICE_SINGLE_ACT_Q_REGION_M;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_INDEX_M,</div><div class='add'>+				  rinfo-&gt;sw_act.fwd_id.q_id);</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_Q_REGION_M, q_rgn);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ICE_DROP_PACKET:</div><div class='ctx'> 		act |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |</div><div class='ctx'> 		       ICE_SINGLE_ACT_VALID_BIT;</div><div class='ctx'> 		break;</div><div class='add'>+	case ICE_MIRROR_PACKET:</div><div class='add'>+		act |= ICE_SINGLE_ACT_OTHER_ACTS;</div><div class='add'>+		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M,</div><div class='add'>+				  rinfo-&gt;sw_act.fwd_id.hw_vsi_id);</div><div class='add'>+		break;</div><div class='ctx'> 	case ICE_NOP:</div><div class='ctx'> 		act |= FIELD_PREP(ICE_SINGLE_ACT_VSI_ID_M,</div><div class='ctx'> 				  rinfo-&gt;sw_act.fwd_id.hw_vsi_id);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_tc_lib.c b/drivers/net/ethernet/intel/ice/ice_tc_lib.c<br/>index dd03cb69ad26..b890410a2bc0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_tc_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_tc_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_tc_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_tc_lib.c</a></div><div class='hunk'>@@ -653,7 +653,7 @@ static int ice_tc_setup_redirect_action(struct net_device *filter_dev,</div><div class='ctx'> 		   ice_tc_is_dev_uplink(target_dev)) {</div><div class='ctx'> 		repr = ice_netdev_to_repr(filter_dev);</div><div class='ctx'> </div><div class='del'>-		fltr-&gt;dest_vsi = repr-&gt;src_vsi-&gt;back-&gt;switchdev.uplink_vsi;</div><div class='add'>+		fltr-&gt;dest_vsi = repr-&gt;src_vsi-&gt;back-&gt;eswitch.uplink_vsi;</div><div class='ctx'> 		fltr-&gt;direction = ICE_ESWITCH_FLTR_EGRESS;</div><div class='ctx'> 	} else if (ice_tc_is_dev_uplink(filter_dev) &amp;&amp;</div><div class='ctx'> 		   ice_is_port_repr_netdev(target_dev)) {</div><div class='hunk'>@@ -689,6 +689,41 @@ ice_tc_setup_drop_action(struct net_device *filter_dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ice_tc_setup_mirror_action(struct net_device *filter_dev,</div><div class='add'>+				      struct ice_tc_flower_fltr *fltr,</div><div class='add'>+				      struct net_device *target_dev)</div><div class='add'>+{</div><div class='add'>+	struct ice_repr *repr;</div><div class='add'>+</div><div class='add'>+	fltr-&gt;action.fltr_act = ICE_MIRROR_PACKET;</div><div class='add'>+</div><div class='add'>+	if (ice_is_port_repr_netdev(filter_dev) &amp;&amp;</div><div class='add'>+	    ice_is_port_repr_netdev(target_dev)) {</div><div class='add'>+		repr = ice_netdev_to_repr(target_dev);</div><div class='add'>+</div><div class='add'>+		fltr-&gt;dest_vsi = repr-&gt;src_vsi;</div><div class='add'>+		fltr-&gt;direction = ICE_ESWITCH_FLTR_EGRESS;</div><div class='add'>+	} else if (ice_is_port_repr_netdev(filter_dev) &amp;&amp;</div><div class='add'>+		   ice_tc_is_dev_uplink(target_dev)) {</div><div class='add'>+		repr = ice_netdev_to_repr(filter_dev);</div><div class='add'>+</div><div class='add'>+		fltr-&gt;dest_vsi = repr-&gt;src_vsi-&gt;back-&gt;eswitch.uplink_vsi;</div><div class='add'>+		fltr-&gt;direction = ICE_ESWITCH_FLTR_EGRESS;</div><div class='add'>+	} else if (ice_tc_is_dev_uplink(filter_dev) &amp;&amp;</div><div class='add'>+		   ice_is_port_repr_netdev(target_dev)) {</div><div class='add'>+		repr = ice_netdev_to_repr(target_dev);</div><div class='add'>+</div><div class='add'>+		fltr-&gt;dest_vsi = repr-&gt;src_vsi;</div><div class='add'>+		fltr-&gt;direction = ICE_ESWITCH_FLTR_INGRESS;</div><div class='add'>+	} else {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(fltr-&gt;extack,</div><div class='add'>+				   "Unsupported netdevice in switchdev mode");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ice_eswitch_tc_parse_action(struct net_device *filter_dev,</div><div class='ctx'> 				       struct ice_tc_flower_fltr *fltr,</div><div class='ctx'> 				       struct flow_action_entry *act)</div><div class='hunk'>@@ -710,6 +745,12 @@ static int ice_eswitch_tc_parse_action(struct net_device *filter_dev,</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='add'>+	case FLOW_ACTION_MIRRED:</div><div class='add'>+		err = ice_tc_setup_mirror_action(filter_dev, fltr, act-&gt;dev);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='ctx'> 	default:</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(fltr-&gt;extack, "Unsupported action in switchdev mode");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -765,7 +806,7 @@ ice_eswitch_add_tc_fltr(struct ice_vsi *vsi, struct ice_tc_flower_fltr *fltr)</div><div class='ctx'> 		rule_info.sw_act.src = hw-&gt;pf_id;</div><div class='ctx'> 		rule_info.flags_info.act = ICE_SINGLE_ACT_LB_ENABLE;</div><div class='ctx'> 	} else if (fltr-&gt;direction == ICE_ESWITCH_FLTR_EGRESS &amp;&amp;</div><div class='del'>-		   fltr-&gt;dest_vsi == vsi-&gt;back-&gt;switchdev.uplink_vsi) {</div><div class='add'>+		   fltr-&gt;dest_vsi == vsi-&gt;back-&gt;eswitch.uplink_vsi) {</div><div class='ctx'> 		/* VF to Uplink */</div><div class='ctx'> 		rule_info.sw_act.flag |= ICE_FLTR_TX;</div><div class='ctx'> 		rule_info.sw_act.src = vsi-&gt;idx;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c b/drivers/net/ethernet/intel/ice/ice_txrx.c<br/>index 9e97ea863068..74d13cc5a3a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx.c</a></div><div class='hunk'>@@ -557,13 +557,14 @@ ice_rx_frame_truesize(struct ice_rx_ring *rx_ring, const unsigned int size)</div><div class='ctx'>  * @xdp_prog: XDP program to run</div><div class='ctx'>  * @xdp_ring: ring to be used for XDP_TX action</div><div class='ctx'>  * @rx_buf: Rx buffer to store the XDP action</div><div class='add'>+ * @eop_desc: Last descriptor in packet to read metadata from</div><div class='ctx'>  *</div><div class='ctx'>  * Returns any of ICE_XDP_{PASS, CONSUMED, TX, REDIR}</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='ctx'> ice_run_xdp(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp,</div><div class='ctx'> 	    struct bpf_prog *xdp_prog, struct ice_tx_ring *xdp_ring,</div><div class='del'>-	    struct ice_rx_buf *rx_buf)</div><div class='add'>+	    struct ice_rx_buf *rx_buf, union ice_32b_rx_flex_desc *eop_desc)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int ret = ICE_XDP_PASS;</div><div class='ctx'> 	u32 act;</div><div class='hunk'>@@ -571,6 +572,8 @@ ice_run_xdp(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp,</div><div class='ctx'> 	if (!xdp_prog)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> </div><div class='add'>+	ice_xdp_meta_set_desc(xdp, eop_desc);</div><div class='add'>+</div><div class='ctx'> 	act = bpf_prog_run_xdp(xdp_prog, xdp);</div><div class='ctx'> 	switch (act) {</div><div class='ctx'> 	case XDP_PASS:</div><div class='hunk'>@@ -1180,8 +1183,7 @@ int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget)</div><div class='ctx'> 		struct sk_buff *skb;</div><div class='ctx'> 		unsigned int size;</div><div class='ctx'> 		u16 stat_err_bits;</div><div class='del'>-		u16 vlan_tag = 0;</div><div class='del'>-		u16 rx_ptype;</div><div class='add'>+		u16 vlan_tci;</div><div class='ctx'> </div><div class='ctx'> 		/* get the Rx desc from Rx ring based on 'next_to_clean' */</div><div class='ctx'> 		rx_desc = ICE_RX_DESC(rx_ring, ntc);</div><div class='hunk'>@@ -1241,7 +1243,7 @@ int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget)</div><div class='ctx'> 		if (ice_is_non_eop(rx_ring, rx_desc))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='del'>-		ice_run_xdp(rx_ring, xdp, xdp_prog, xdp_ring, rx_buf);</div><div class='add'>+		ice_run_xdp(rx_ring, xdp, xdp_prog, xdp_ring, rx_buf, rx_desc);</div><div class='ctx'> 		if (rx_buf-&gt;act == ICE_XDP_PASS)</div><div class='ctx'> 			goto construct_skb;</div><div class='ctx'> 		total_rx_bytes += xdp_get_buff_len(xdp);</div><div class='hunk'>@@ -1276,7 +1278,7 @@ construct_skb:</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		vlan_tag = ice_get_vlan_tag_from_rx_desc(rx_desc);</div><div class='add'>+		vlan_tci = ice_get_vlan_tci(rx_desc);</div><div class='ctx'> </div><div class='ctx'> 		/* pad the skb if needed, to make a valid ethernet frame */</div><div class='ctx'> 		if (eth_skb_pad(skb))</div><div class='hunk'>@@ -1286,14 +1288,11 @@ construct_skb:</div><div class='ctx'> 		total_rx_bytes += skb-&gt;len;</div><div class='ctx'> </div><div class='ctx'> 		/* populate checksum, VLAN, and protocol */</div><div class='del'>-		rx_ptype = le16_to_cpu(rx_desc-&gt;wb.ptype_flex_flags0) &amp;</div><div class='del'>-			ICE_RX_FLEX_DESC_PTYPE_M;</div><div class='del'>-</div><div class='del'>-		ice_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);</div><div class='add'>+		ice_process_skb_fields(rx_ring, rx_desc, skb);</div><div class='ctx'> </div><div class='ctx'> 		ice_trace(clean_rx_irq_indicate, rx_ring, rx_desc, skb);</div><div class='ctx'> 		/* send completed skb up the stack */</div><div class='del'>-		ice_receive_skb(rx_ring, skb, vlan_tag);</div><div class='add'>+		ice_receive_skb(rx_ring, skb, vlan_tci);</div><div class='ctx'> </div><div class='ctx'> 		/* update budget accounting */</div><div class='ctx'> 		total_rx_pkts++;</div><div class='hunk'>@@ -1494,9 +1493,9 @@ static void ice_set_wb_on_itr(struct ice_q_vector *q_vector)</div><div class='ctx'> 	 * be static in non-adaptive mode (user configured)</div><div class='ctx'> 	 */</div><div class='ctx'> 	wr32(&amp;vsi-&gt;back-&gt;hw, GLINT_DYN_CTL(q_vector-&gt;reg_idx),</div><div class='del'>-	     ((ICE_ITR_NONE &lt;&lt; GLINT_DYN_CTL_ITR_INDX_S) &amp;</div><div class='del'>-	      GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M |</div><div class='del'>-	     GLINT_DYN_CTL_WB_ON_ITR_M);</div><div class='add'>+	     FIELD_PREP(GLINT_DYN_CTL_ITR_INDX_M, ICE_ITR_NONE) |</div><div class='add'>+	     FIELD_PREP(GLINT_DYN_CTL_INTENA_MSK_M, 1) |</div><div class='add'>+	     FIELD_PREP(GLINT_DYN_CTL_WB_ON_ITR_M, 1));</div><div class='ctx'> </div><div class='ctx'> 	q_vector-&gt;wb_on_itr = true;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h<br/>index daf7b9dbb143..b3379ff73674 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_txrx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx.h</a></div><div class='hunk'>@@ -257,6 +257,20 @@ enum ice_rx_dtype {</div><div class='ctx'> 	ICE_RX_DTYPE_SPLIT_ALWAYS	= 2,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct ice_pkt_ctx {</div><div class='add'>+	u64 cached_phctime;</div><div class='add'>+	__be16 vlan_proto;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct ice_xdp_buff {</div><div class='add'>+	struct xdp_buff xdp_buff;</div><div class='add'>+	const union ice_32b_rx_flex_desc *eop_desc;</div><div class='add'>+	const struct ice_pkt_ctx *pkt_ctx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Required for compatibility with xdp_buffs from xsk_pool */</div><div class='add'>+static_assert(offsetof(struct ice_xdp_buff, xdp_buff) == 0);</div><div class='add'>+</div><div class='ctx'> /* indices into GLINT_ITR registers */</div><div class='ctx'> #define ICE_RX_ITR	ICE_IDX_ITR0</div><div class='ctx'> #define ICE_TX_ITR	ICE_IDX_ITR1</div><div class='hunk'>@@ -298,7 +312,6 @@ enum ice_dynamic_itr {</div><div class='ctx'> /* descriptor ring, associated with a VSI */</div><div class='ctx'> struct ice_rx_ring {</div><div class='ctx'> 	/* CL1 - 1st cacheline starts here */</div><div class='del'>-	struct ice_rx_ring *next;	/* pointer to next ring in q_vector */</div><div class='ctx'> 	void *desc;			/* Descriptor ring memory */</div><div class='ctx'> 	struct device *dev;		/* Used for DMA mapping */</div><div class='ctx'> 	struct net_device *netdev;	/* netdev ring maps to */</div><div class='hunk'>@@ -310,13 +323,24 @@ struct ice_rx_ring {</div><div class='ctx'> 	u16 count;			/* Number of descriptors */</div><div class='ctx'> 	u16 reg_idx;			/* HW register index of the ring */</div><div class='ctx'> 	u16 next_to_alloc;</div><div class='del'>-	/* CL2 - 2nd cacheline starts here */</div><div class='add'>+</div><div class='ctx'> 	union {</div><div class='ctx'> 		struct ice_rx_buf *rx_buf;</div><div class='ctx'> 		struct xdp_buff **xdp_buf;</div><div class='ctx'> 	};</div><div class='del'>-	struct xdp_buff xdp;</div><div class='add'>+	/* CL2 - 2nd cacheline starts here */</div><div class='add'>+	union {</div><div class='add'>+		struct ice_xdp_buff xdp_ext;</div><div class='add'>+		struct xdp_buff xdp;</div><div class='add'>+	};</div><div class='ctx'> 	/* CL3 - 3rd cacheline starts here */</div><div class='add'>+	union {</div><div class='add'>+		struct ice_pkt_ctx pkt_ctx;</div><div class='add'>+		struct {</div><div class='add'>+			u64 cached_phctime;</div><div class='add'>+			__be16 vlan_proto;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> 	struct bpf_prog *xdp_prog;</div><div class='ctx'> 	u16 rx_offset;</div><div class='ctx'> </div><div class='hunk'>@@ -332,9 +356,9 @@ struct ice_rx_ring {</div><div class='ctx'> 	/* CL4 - 4th cacheline starts here */</div><div class='ctx'> 	struct ice_channel *ch;</div><div class='ctx'> 	struct ice_tx_ring *xdp_ring;</div><div class='add'>+	struct ice_rx_ring *next;	/* pointer to next ring in q_vector */</div><div class='ctx'> 	struct xsk_buff_pool *xsk_pool;</div><div class='ctx'> 	dma_addr_t dma;			/* physical address of ring */</div><div class='del'>-	u64 cached_phctime;</div><div class='ctx'> 	u16 rx_buf_len;</div><div class='ctx'> 	u8 dcb_tc;			/* Traffic class of ring */</div><div class='ctx'> 	u8 ptp_rx;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_txrx_lib.c b/drivers/net/ethernet/intel/ice/ice_txrx_lib.c<br/>index 7e06373e14d9..839e5da24ad5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_txrx_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx_lib.c</a></div><div class='hunk'>@@ -63,28 +63,42 @@ static enum pkt_hash_types ice_ptype_to_htype(u16 ptype)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_rx_hash - set the hash value in the skb</div><div class='add'>+ * ice_get_rx_hash - get RX hash value from descriptor</div><div class='add'>+ * @rx_desc: specific descriptor</div><div class='add'>+ *</div><div class='add'>+ * Returns hash, if present, 0 otherwise.</div><div class='add'>+ */</div><div class='add'>+static u32 ice_get_rx_hash(const union ice_32b_rx_flex_desc *rx_desc)</div><div class='add'>+{</div><div class='add'>+	const struct ice_32b_rx_flex_desc_nic *nic_mdid;</div><div class='add'>+</div><div class='add'>+	if (unlikely(rx_desc-&gt;wb.rxdid != ICE_RXDID_FLEX_NIC))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	nic_mdid = (struct ice_32b_rx_flex_desc_nic *)rx_desc;</div><div class='add'>+	return le32_to_cpu(nic_mdid-&gt;rss_hash);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_rx_hash_to_skb - set the hash value in the skb</div><div class='ctx'>  * @rx_ring: descriptor ring</div><div class='ctx'>  * @rx_desc: specific descriptor</div><div class='ctx'>  * @skb: pointer to current skb</div><div class='ctx'>  * @rx_ptype: the ptype value from the descriptor</div><div class='ctx'>  */</div><div class='ctx'> static void</div><div class='del'>-ice_rx_hash(struct ice_rx_ring *rx_ring, union ice_32b_rx_flex_desc *rx_desc,</div><div class='del'>-	    struct sk_buff *skb, u16 rx_ptype)</div><div class='add'>+ice_rx_hash_to_skb(const struct ice_rx_ring *rx_ring,</div><div class='add'>+		   const union ice_32b_rx_flex_desc *rx_desc,</div><div class='add'>+		   struct sk_buff *skb, u16 rx_ptype)</div><div class='ctx'> {</div><div class='del'>-	struct ice_32b_rx_flex_desc_nic *nic_mdid;</div><div class='ctx'> 	u32 hash;</div><div class='ctx'> </div><div class='ctx'> 	if (!(rx_ring-&gt;netdev-&gt;features &amp; NETIF_F_RXHASH))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (rx_desc-&gt;wb.rxdid != ICE_RXDID_FLEX_NIC)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	nic_mdid = (struct ice_32b_rx_flex_desc_nic *)rx_desc;</div><div class='del'>-	hash = le32_to_cpu(nic_mdid-&gt;rss_hash);</div><div class='del'>-	skb_set_hash(skb, hash, ice_ptype_to_htype(rx_ptype));</div><div class='add'>+	hash = ice_get_rx_hash(rx_desc);</div><div class='add'>+	if (likely(hash))</div><div class='add'>+		skb_set_hash(skb, hash, ice_ptype_to_htype(rx_ptype));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -171,11 +185,38 @@ checksum_fail:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_ptp_rx_hwts_to_skb - Put RX timestamp into skb</div><div class='add'>+ * @rx_ring: Ring to get the VSI info</div><div class='add'>+ * @rx_desc: Receive descriptor</div><div class='add'>+ * @skb: Particular skb to send timestamp with</div><div class='add'>+ *</div><div class='add'>+ * The timestamp is in ns, so we must convert the result first.</div><div class='add'>+ */</div><div class='add'>+static void</div><div class='add'>+ice_ptp_rx_hwts_to_skb(struct ice_rx_ring *rx_ring,</div><div class='add'>+		       const union ice_32b_rx_flex_desc *rx_desc,</div><div class='add'>+		       struct sk_buff *skb)</div><div class='add'>+{</div><div class='add'>+	u64 ts_ns = ice_ptp_get_rx_hwts(rx_desc, &amp;rx_ring-&gt;pkt_ctx);</div><div class='add'>+</div><div class='add'>+	skb_hwtstamps(skb)-&gt;hwtstamp = ns_to_ktime(ts_ns);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_get_ptype - Read HW packet type from the descriptor</div><div class='add'>+ * @rx_desc: RX descriptor</div><div class='add'>+ */</div><div class='add'>+static u16 ice_get_ptype(const union ice_32b_rx_flex_desc *rx_desc)</div><div class='add'>+{</div><div class='add'>+	return le16_to_cpu(rx_desc-&gt;wb.ptype_flex_flags0) &amp;</div><div class='add'>+	       ICE_RX_FLEX_DESC_PTYPE_M;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_process_skb_fields - Populate skb header fields from Rx descriptor</div><div class='ctx'>  * @rx_ring: Rx descriptor ring packet is being transacted on</div><div class='ctx'>  * @rx_desc: pointer to the EOP Rx descriptor</div><div class='ctx'>  * @skb: pointer to current skb being populated</div><div class='del'>- * @ptype: the packet type decoded by hardware</div><div class='ctx'>  *</div><div class='ctx'>  * This function checks the ring, descriptor, and packet information in</div><div class='ctx'>  * order to populate the hash, checksum, VLAN, protocol, and</div><div class='hunk'>@@ -184,9 +225,11 @@ checksum_fail:</div><div class='ctx'> void</div><div class='ctx'> ice_process_skb_fields(struct ice_rx_ring *rx_ring,</div><div class='ctx'> 		       union ice_32b_rx_flex_desc *rx_desc,</div><div class='del'>-		       struct sk_buff *skb, u16 ptype)</div><div class='add'>+		       struct sk_buff *skb)</div><div class='ctx'> {</div><div class='del'>-	ice_rx_hash(rx_ring, rx_desc, skb, ptype);</div><div class='add'>+	u16 ptype = ice_get_ptype(rx_desc);</div><div class='add'>+</div><div class='add'>+	ice_rx_hash_to_skb(rx_ring, rx_desc, skb, ptype);</div><div class='ctx'> </div><div class='ctx'> 	/* modifies the skb - consumes the enet header */</div><div class='ctx'> 	skb-&gt;protocol = eth_type_trans(skb, rx_ring-&gt;netdev);</div><div class='hunk'>@@ -194,28 +237,24 @@ ice_process_skb_fields(struct ice_rx_ring *rx_ring,</div><div class='ctx'> 	ice_rx_csum(rx_ring, skb, rx_desc, ptype);</div><div class='ctx'> </div><div class='ctx'> 	if (rx_ring-&gt;ptp_rx)</div><div class='del'>-		ice_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);</div><div class='add'>+		ice_ptp_rx_hwts_to_skb(rx_ring, rx_desc, skb);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * ice_receive_skb - Send a completed packet up the stack</div><div class='ctx'>  * @rx_ring: Rx ring in play</div><div class='ctx'>  * @skb: packet to send up</div><div class='del'>- * @vlan_tag: VLAN tag for packet</div><div class='add'>+ * @vlan_tci: VLAN TCI for packet</div><div class='ctx'>  *</div><div class='ctx'>  * This function sends the completed packet (via. skb) up the stack using</div><div class='ctx'>  * gro receive functions (with/without VLAN tag)</div><div class='ctx'>  */</div><div class='ctx'> void</div><div class='del'>-ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tag)</div><div class='add'>+ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tci)</div><div class='ctx'> {</div><div class='del'>-	netdev_features_t features = rx_ring-&gt;netdev-&gt;features;</div><div class='del'>-	bool non_zero_vlan = !!(vlan_tag &amp; VLAN_VID_MASK);</div><div class='del'>-</div><div class='del'>-	if ((features &amp; NETIF_F_HW_VLAN_CTAG_RX) &amp;&amp; non_zero_vlan)</div><div class='del'>-		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);</div><div class='del'>-	else if ((features &amp; NETIF_F_HW_VLAN_STAG_RX) &amp;&amp; non_zero_vlan)</div><div class='del'>-		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan_tag);</div><div class='add'>+	if ((vlan_tci &amp; VLAN_VID_MASK) &amp;&amp; rx_ring-&gt;vlan_proto)</div><div class='add'>+		__vlan_hwaccel_put_tag(skb, rx_ring-&gt;vlan_proto,</div><div class='add'>+				       vlan_tci);</div><div class='ctx'> </div><div class='ctx'> 	napi_gro_receive(&amp;rx_ring-&gt;q_vector-&gt;napi, skb);</div><div class='ctx'> }</div><div class='hunk'>@@ -464,3 +503,125 @@ void ice_finalize_xdp_rx(struct ice_tx_ring *xdp_ring, unsigned int xdp_res,</div><div class='ctx'> 			spin_unlock(&amp;xdp_ring-&gt;tx_lock);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_xdp_rx_hw_ts - HW timestamp XDP hint handler</div><div class='add'>+ * @ctx: XDP buff pointer</div><div class='add'>+ * @ts_ns: destination address</div><div class='add'>+ *</div><div class='add'>+ * Copy HW timestamp (if available) to the destination address.</div><div class='add'>+ */</div><div class='add'>+static int ice_xdp_rx_hw_ts(const struct xdp_md *ctx, u64 *ts_ns)</div><div class='add'>+{</div><div class='add'>+	const struct ice_xdp_buff *xdp_ext = (void *)ctx;</div><div class='add'>+</div><div class='add'>+	*ts_ns = ice_ptp_get_rx_hwts(xdp_ext-&gt;eop_desc,</div><div class='add'>+				     xdp_ext-&gt;pkt_ctx);</div><div class='add'>+	if (!*ts_ns)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Define a ptype index -&gt; XDP hash type lookup table.</div><div class='add'>+ * It uses the same ptype definitions as ice_decode_rx_desc_ptype[],</div><div class='add'>+ * avoiding possible copy-paste errors.</div><div class='add'>+ */</div><div class='add'>+#undef ICE_PTT</div><div class='add'>+#undef ICE_PTT_UNUSED_ENTRY</div><div class='add'>+</div><div class='add'>+#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\</div><div class='add'>+	[PTYPE] = XDP_RSS_L3_##OUTER_IP_VER | XDP_RSS_L4_##I | XDP_RSS_TYPE_##PL</div><div class='add'>+</div><div class='add'>+#define ICE_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = 0</div><div class='add'>+</div><div class='add'>+/* A few supplementary definitions for when XDP hash types do not coincide</div><div class='add'>+ * with what can be generated from ptype definitions</div><div class='add'>+ * by means of preprocessor concatenation.</div><div class='add'>+ */</div><div class='add'>+#define XDP_RSS_L3_NONE		XDP_RSS_TYPE_NONE</div><div class='add'>+#define XDP_RSS_L4_NONE		XDP_RSS_TYPE_NONE</div><div class='add'>+#define XDP_RSS_TYPE_PAY2	XDP_RSS_TYPE_L2</div><div class='add'>+#define XDP_RSS_TYPE_PAY3	XDP_RSS_TYPE_NONE</div><div class='add'>+#define XDP_RSS_TYPE_PAY4	XDP_RSS_L4</div><div class='add'>+</div><div class='add'>+static const enum xdp_rss_hash_type</div><div class='add'>+ice_ptype_to_xdp_hash[ICE_NUM_DEFINED_PTYPES] = {</div><div class='add'>+	ICE_PTYPES</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#undef XDP_RSS_L3_NONE</div><div class='add'>+#undef XDP_RSS_L4_NONE</div><div class='add'>+#undef XDP_RSS_TYPE_PAY2</div><div class='add'>+#undef XDP_RSS_TYPE_PAY3</div><div class='add'>+#undef XDP_RSS_TYPE_PAY4</div><div class='add'>+</div><div class='add'>+#undef ICE_PTT</div><div class='add'>+#undef ICE_PTT_UNUSED_ENTRY</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_xdp_rx_hash_type - Get XDP-specific hash type from the RX descriptor</div><div class='add'>+ * @eop_desc: End of Packet descriptor</div><div class='add'>+ */</div><div class='add'>+static enum xdp_rss_hash_type</div><div class='add'>+ice_xdp_rx_hash_type(const union ice_32b_rx_flex_desc *eop_desc)</div><div class='add'>+{</div><div class='add'>+	u16 ptype = ice_get_ptype(eop_desc);</div><div class='add'>+</div><div class='add'>+	if (unlikely(ptype &gt;= ICE_NUM_DEFINED_PTYPES))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return ice_ptype_to_xdp_hash[ptype];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_xdp_rx_hash - RX hash XDP hint handler</div><div class='add'>+ * @ctx: XDP buff pointer</div><div class='add'>+ * @hash: hash destination address</div><div class='add'>+ * @rss_type: XDP hash type destination address</div><div class='add'>+ *</div><div class='add'>+ * Copy RX hash (if available) and its type to the destination address.</div><div class='add'>+ */</div><div class='add'>+static int ice_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,</div><div class='add'>+			   enum xdp_rss_hash_type *rss_type)</div><div class='add'>+{</div><div class='add'>+	const struct ice_xdp_buff *xdp_ext = (void *)ctx;</div><div class='add'>+</div><div class='add'>+	*hash = ice_get_rx_hash(xdp_ext-&gt;eop_desc);</div><div class='add'>+	*rss_type = ice_xdp_rx_hash_type(xdp_ext-&gt;eop_desc);</div><div class='add'>+	if (!likely(*hash))</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * ice_xdp_rx_vlan_tag - VLAN tag XDP hint handler</div><div class='add'>+ * @ctx: XDP buff pointer</div><div class='add'>+ * @vlan_proto: destination address for VLAN protocol</div><div class='add'>+ * @vlan_tci: destination address for VLAN TCI</div><div class='add'>+ *</div><div class='add'>+ * Copy VLAN tag (if was stripped) and corresponding protocol</div><div class='add'>+ * to the destination address.</div><div class='add'>+ */</div><div class='add'>+static int ice_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,</div><div class='add'>+			       u16 *vlan_tci)</div><div class='add'>+{</div><div class='add'>+	const struct ice_xdp_buff *xdp_ext = (void *)ctx;</div><div class='add'>+</div><div class='add'>+	*vlan_proto = xdp_ext-&gt;pkt_ctx-&gt;vlan_proto;</div><div class='add'>+	if (!*vlan_proto)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	*vlan_tci = ice_get_vlan_tci(xdp_ext-&gt;eop_desc);</div><div class='add'>+	if (!*vlan_tci)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct xdp_metadata_ops ice_xdp_md_ops = {</div><div class='add'>+	.xmo_rx_timestamp		= ice_xdp_rx_hw_ts,</div><div class='add'>+	.xmo_rx_hash			= ice_xdp_rx_hash,</div><div class='add'>+	.xmo_rx_vlan_tag		= ice_xdp_rx_vlan_tag,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_txrx_lib.h b/drivers/net/ethernet/intel/ice/ice_txrx_lib.h<br/>index 115969ecdf7b..762047508619 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx_lib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_txrx_lib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_txrx_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_txrx_lib.h</a></div><div class='hunk'>@@ -84,7 +84,7 @@ ice_build_ctob(u64 td_cmd, u64 td_offset, unsigned int size, u64 td_tag)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_get_vlan_tag_from_rx_desc - get VLAN from Rx flex descriptor</div><div class='add'>+ * ice_get_vlan_tci - get VLAN TCI from Rx flex descriptor</div><div class='ctx'>  * @rx_desc: Rx 32b flex descriptor with RXDID=2</div><div class='ctx'>  *</div><div class='ctx'>  * The OS and current PF implementation only support stripping a single VLAN tag</div><div class='hunk'>@@ -92,7 +92,7 @@ ice_build_ctob(u64 td_cmd, u64 td_offset, unsigned int size, u64 td_tag)</div><div class='ctx'>  * one is found return the tag, else return 0 to mean no VLAN tag was found.</div><div class='ctx'>  */</div><div class='ctx'> static inline u16</div><div class='del'>-ice_get_vlan_tag_from_rx_desc(union ice_32b_rx_flex_desc *rx_desc)</div><div class='add'>+ice_get_vlan_tci(const union ice_32b_rx_flex_desc *rx_desc)</div><div class='ctx'> {</div><div class='ctx'> 	u16 stat_err_bits;</div><div class='ctx'> </div><div class='hunk'>@@ -148,7 +148,17 @@ void ice_release_rx_desc(struct ice_rx_ring *rx_ring, u16 val);</div><div class='ctx'> void</div><div class='ctx'> ice_process_skb_fields(struct ice_rx_ring *rx_ring,</div><div class='ctx'> 		       union ice_32b_rx_flex_desc *rx_desc,</div><div class='del'>-		       struct sk_buff *skb, u16 ptype);</div><div class='add'>+		       struct sk_buff *skb);</div><div class='ctx'> void</div><div class='del'>-ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tag);</div><div class='add'>+ice_receive_skb(struct ice_rx_ring *rx_ring, struct sk_buff *skb, u16 vlan_tci);</div><div class='add'>+</div><div class='add'>+static inline void</div><div class='add'>+ice_xdp_meta_set_desc(struct xdp_buff *xdp,</div><div class='add'>+		      union ice_32b_rx_flex_desc *eop_desc)</div><div class='add'>+{</div><div class='add'>+	struct ice_xdp_buff *xdp_ext = container_of(xdp, struct ice_xdp_buff,</div><div class='add'>+						    xdp_buff);</div><div class='add'>+</div><div class='add'>+	xdp_ext-&gt;eop_desc = eop_desc;</div><div class='add'>+}</div><div class='ctx'> #endif /* !_ICE_TXRX_LIB_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h<br/>index a18ca0ff879f..41ab6d7bbd9e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_type.h</a></div><div class='hunk'>@@ -17,6 +17,7 @@</div><div class='ctx'> #include "ice_protocol_type.h"</div><div class='ctx'> #include "ice_sbq_cmd.h"</div><div class='ctx'> #include "ice_vlan_mode.h"</div><div class='add'>+#include "ice_fwlog.h"</div><div class='ctx'> </div><div class='ctx'> static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)</div><div class='ctx'> {</div><div class='hunk'>@@ -246,6 +247,7 @@ struct ice_fd_hw_prof {</div><div class='ctx'> 	int cnt;</div><div class='ctx'> 	u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];</div><div class='ctx'> 	u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];</div><div class='add'>+	u64 prof_id[ICE_FD_HW_SEG_MAX];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Common HW capabilities for SW use */</div><div class='hunk'>@@ -351,6 +353,7 @@ struct ice_ts_func_info {</div><div class='ctx'> #define ICE_TS_TMR0_ENA_M		BIT(25)</div><div class='ctx'> #define ICE_TS_TMR1_ENA_M		BIT(26)</div><div class='ctx'> #define ICE_TS_LL_TX_TS_READ_M		BIT(28)</div><div class='add'>+#define ICE_TS_LL_TX_TS_INT_READ_M	BIT(29)</div><div class='ctx'> </div><div class='ctx'> struct ice_ts_dev_info {</div><div class='ctx'> 	/* Device specific info */</div><div class='hunk'>@@ -364,6 +367,7 @@ struct ice_ts_dev_info {</div><div class='ctx'> 	u8 tmr0_ena;</div><div class='ctx'> 	u8 tmr1_ena;</div><div class='ctx'> 	u8 ts_ll_read;</div><div class='add'>+	u8 ts_ll_int_read;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Function specific capabilities */</div><div class='hunk'>@@ -377,6 +381,8 @@ struct ice_hw_func_caps {</div><div class='ctx'> 	struct ice_ts_func_info ts_func_info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT	0</div><div class='add'>+</div><div class='ctx'> /* Device wide capabilities */</div><div class='ctx'> struct ice_hw_dev_caps {</div><div class='ctx'> 	struct ice_hw_common_caps common_cap;</div><div class='hunk'>@@ -385,6 +391,11 @@ struct ice_hw_dev_caps {</div><div class='ctx'> 	u32 num_flow_director_fltr;	/* Number of FD filters available */</div><div class='ctx'> 	struct ice_ts_dev_info ts_dev_info;</div><div class='ctx'> 	u32 num_funcs;</div><div class='add'>+	/* bitmap of supported sensors</div><div class='add'>+	 * bit 0 - internal temperature sensor</div><div class='add'>+	 * bit 31:1 - Reserved</div><div class='add'>+	 */</div><div class='add'>+	u32 supported_sensors;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* MAC info */</div><div class='hunk'>@@ -730,24 +741,6 @@ struct ice_switch_info {</div><div class='ctx'> 	DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* FW logging configuration */</div><div class='del'>-struct ice_fw_log_evnt {</div><div class='del'>-	u8 cfg : 4;	/* New event enables to configure */</div><div class='del'>-	u8 cur : 4;	/* Current/active event enables */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct ice_fw_log_cfg {</div><div class='del'>-	u8 cq_en : 1;    /* FW logging is enabled via the control queue */</div><div class='del'>-	u8 uart_en : 1;  /* FW logging is enabled via UART for all PFs */</div><div class='del'>-	u8 actv_evnts;   /* Cumulation of currently enabled log events */</div><div class='del'>-</div><div class='del'>-#define ICE_FW_LOG_EVNT_INFO	(ICE_AQC_FW_LOG_INFO_EN &gt;&gt; ICE_AQC_FW_LOG_EN_S)</div><div class='del'>-#define ICE_FW_LOG_EVNT_INIT	(ICE_AQC_FW_LOG_INIT_EN &gt;&gt; ICE_AQC_FW_LOG_EN_S)</div><div class='del'>-#define ICE_FW_LOG_EVNT_FLOW	(ICE_AQC_FW_LOG_FLOW_EN &gt;&gt; ICE_AQC_FW_LOG_EN_S)</div><div class='del'>-#define ICE_FW_LOG_EVNT_ERR	(ICE_AQC_FW_LOG_ERR_EN &gt;&gt; ICE_AQC_FW_LOG_EN_S)</div><div class='del'>-	struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> /* Enum defining the different states of the mailbox snapshot in the</div><div class='ctx'>  * PF-VF mailbox overflow detection algorithm. The snapshot can be in</div><div class='ctx'>  * states:</div><div class='hunk'>@@ -827,7 +820,7 @@ struct ice_mbx_data {</div><div class='ctx'> enum ice_phy_model {</div><div class='ctx'> 	ICE_PHY_UNSUP = -1,</div><div class='ctx'> 	ICE_PHY_E810  = 1,</div><div class='del'>-	ICE_PHY_E822,</div><div class='add'>+	ICE_PHY_E82X,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Port hardware description */</div><div class='hunk'>@@ -889,7 +882,9 @@ struct ice_hw {</div><div class='ctx'> 	u8 fw_patch;		/* firmware patch version */</div><div class='ctx'> 	u32 fw_build;		/* firmware build number */</div><div class='ctx'> </div><div class='del'>-	struct ice_fw_log_cfg fw_log;</div><div class='add'>+	struct ice_fwlog_cfg fwlog_cfg;</div><div class='add'>+	bool fwlog_supported; /* does hardware support FW logging? */</div><div class='add'>+	struct ice_fwlog_ring fwlog_ring;</div><div class='ctx'> </div><div class='ctx'> /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL</div><div class='ctx'>  * register. Used for determining the ITR/INTRL granularity during</div><div class='hunk'>@@ -910,10 +905,9 @@ struct ice_hw {</div><div class='ctx'> 	/* INTRL granularity in 1 us */</div><div class='ctx'> 	u8 intrl_gran;</div><div class='ctx'> </div><div class='del'>-#define ICE_PHY_PER_NAC_E822		1</div><div class='ctx'> #define ICE_MAX_QUAD			2</div><div class='del'>-#define ICE_QUADS_PER_PHY_E822		2</div><div class='del'>-#define ICE_PORTS_PER_PHY_E822		8</div><div class='add'>+#define ICE_QUADS_PER_PHY_E82X		2</div><div class='add'>+#define ICE_PORTS_PER_PHY_E82X		8</div><div class='ctx'> #define ICE_PORTS_PER_QUAD		4</div><div class='ctx'> #define ICE_PORTS_PER_PHY_E810		4</div><div class='ctx'> #define ICE_NUM_EXTERNAL_PORTS		(ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)</div><div class='hunk'>@@ -1009,7 +1003,6 @@ struct ice_hw_port_stats {</div><div class='ctx'> 	u64 error_bytes;		/* errbc */</div><div class='ctx'> 	u64 mac_local_faults;		/* mlfc */</div><div class='ctx'> 	u64 mac_remote_faults;		/* mrfc */</div><div class='del'>-	u64 rx_len_errors;		/* rlec */</div><div class='ctx'> 	u64 link_xon_rx;		/* lxonrxc */</div><div class='ctx'> 	u64 link_xoff_rx;		/* lxoffrxc */</div><div class='ctx'> 	u64 link_xon_tx;		/* lxontxc */</div><div class='hunk'>@@ -1048,6 +1041,7 @@ enum ice_sw_fwd_act_type {</div><div class='ctx'> 	ICE_FWD_TO_Q,</div><div class='ctx'> 	ICE_FWD_TO_QGRP,</div><div class='ctx'> 	ICE_DROP_PACKET,</div><div class='add'>+	ICE_MIRROR_PACKET,</div><div class='ctx'> 	ICE_NOP,</div><div class='ctx'> 	ICE_INVAL_ACT</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.c b/drivers/net/ethernet/intel/ice/ice_vf_lib.c<br/>index aca1f2ea5034..2ffdae9a82df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_vf_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib.c</a></div><div class='hunk'>@@ -248,29 +248,44 @@ static void ice_vf_pre_vsi_rebuild(struct ice_vf *vf)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ice_vf_recreate_vsi - Release and re-create the VF's VSI</div><div class='del'>- * @vf: VF to recreate the VSI for</div><div class='add'>+ * ice_vf_reconfig_vsi - Reconfigure a VF VSI with the device</div><div class='add'>+ * @vf: VF to reconfigure the VSI for</div><div class='ctx'>  *</div><div class='del'>- * This is only called when a single VF is being reset (i.e. VVF, VFLR, host</div><div class='del'>- * VF configuration change, etc)</div><div class='add'>+ * This is called when a single VF is being reset (i.e. VVF, VFLR, host VF</div><div class='add'>+ * configuration change, etc).</div><div class='ctx'>  *</div><div class='del'>- * It releases and then re-creates a new VSI.</div><div class='add'>+ * It brings the VSI down and then reconfigures it with the hardware.</div><div class='ctx'>  */</div><div class='del'>-static int ice_vf_recreate_vsi(struct ice_vf *vf)</div><div class='add'>+int ice_vf_reconfig_vsi(struct ice_vf *vf)</div><div class='ctx'> {</div><div class='add'>+	struct ice_vsi *vsi = ice_get_vf_vsi(vf);</div><div class='add'>+	struct ice_vsi_cfg_params params = {};</div><div class='ctx'> 	struct ice_pf *pf = vf-&gt;pf;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	ice_vf_vsi_release(vf);</div><div class='add'>+	if (WARN_ON(!vsi))</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	err = vf-&gt;vf_ops-&gt;create_vsi(vf);</div><div class='add'>+	params = ice_vsi_to_params(vsi);</div><div class='add'>+	params.flags = ICE_VSI_FLAG_NO_INIT;</div><div class='add'>+</div><div class='add'>+	ice_vsi_decfg(vsi);</div><div class='add'>+	ice_fltr_remove_all(vsi);</div><div class='add'>+</div><div class='add'>+	err = ice_vsi_cfg(vsi, &amp;params);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(ice_pf_to_dev(pf),</div><div class='del'>-			"Failed to recreate the VF%u's VSI, error %d\n",</div><div class='add'>+			"Failed to reconfigure the VF%u's VSI, error %d\n",</div><div class='ctx'> 			vf-&gt;vf_id, err);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Update the lan_vsi_num field since it might have been changed. The</div><div class='add'>+	 * PF lan_vsi_idx number remains the same so we don't need to change</div><div class='add'>+	 * that.</div><div class='add'>+	 */</div><div class='add'>+	vf-&gt;lan_vsi_num = vsi-&gt;vsi_num;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -760,6 +775,7 @@ void ice_reset_all_vfs(struct ice_pf *pf)</div><div class='ctx'> 	ice_for_each_vf(pf, bkt, vf) {</div><div class='ctx'> 		mutex_lock(&amp;vf-&gt;cfg_lock);</div><div class='ctx'> </div><div class='add'>+		ice_eswitch_detach(pf, vf);</div><div class='ctx'> 		vf-&gt;driver_caps = 0;</div><div class='ctx'> 		ice_vc_set_default_allowlist(vf);</div><div class='ctx'> </div><div class='hunk'>@@ -775,13 +791,11 @@ void ice_reset_all_vfs(struct ice_pf *pf)</div><div class='ctx'> 		ice_vf_rebuild_vsi(vf);</div><div class='ctx'> 		ice_vf_post_vsi_rebuild(vf);</div><div class='ctx'> </div><div class='add'>+		ice_eswitch_attach(pf, vf);</div><div class='add'>+</div><div class='ctx'> 		mutex_unlock(&amp;vf-&gt;cfg_lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ice_is_eswitch_mode_switchdev(pf))</div><div class='del'>-		if (ice_eswitch_rebuild(pf))</div><div class='del'>-			dev_warn(dev, "eswitch rebuild failed\n");</div><div class='del'>-</div><div class='ctx'> 	ice_flush(hw);</div><div class='ctx'> 	clear_bit(ICE_VF_DIS, pf-&gt;state);</div><div class='ctx'> </div><div class='hunk'>@@ -829,12 +843,16 @@ static void ice_notify_vf_reset(struct ice_vf *vf)</div><div class='ctx'> int ice_reset_vf(struct ice_vf *vf, u32 flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_pf *pf = vf-&gt;pf;</div><div class='add'>+	struct ice_lag *lag;</div><div class='ctx'> 	struct ice_vsi *vsi;</div><div class='add'>+	u8 act_prt, pri_prt;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> 	bool rsd;</div><div class='ctx'> </div><div class='ctx'> 	dev = ice_pf_to_dev(pf);</div><div class='add'>+	act_prt = ICE_LAG_INVALID_PORT;</div><div class='add'>+	pri_prt = pf-&gt;hw.port_info-&gt;lport;</div><div class='ctx'> </div><div class='ctx'> 	if (flags &amp; ICE_VF_RESET_NOTIFY)</div><div class='ctx'> 		ice_notify_vf_reset(vf);</div><div class='hunk'>@@ -845,6 +863,17 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	lag = pf-&gt;lag;</div><div class='add'>+	mutex_lock(&amp;pf-&gt;lag_mutex);</div><div class='add'>+	if (lag &amp;&amp; lag-&gt;bonded &amp;&amp; lag-&gt;primary) {</div><div class='add'>+		act_prt = lag-&gt;active_port;</div><div class='add'>+		if (act_prt != pri_prt &amp;&amp; act_prt != ICE_LAG_INVALID_PORT &amp;&amp;</div><div class='add'>+		    lag-&gt;upper_netdev)</div><div class='add'>+			ice_lag_move_vf_nodes_cfg(lag, act_prt, pri_prt);</div><div class='add'>+		else</div><div class='add'>+			act_prt = ICE_LAG_INVALID_PORT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (flags &amp; ICE_VF_RESET_LOCK)</div><div class='ctx'> 		mutex_lock(&amp;vf-&gt;cfg_lock);</div><div class='ctx'> 	else</div><div class='hunk'>@@ -914,7 +943,7 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags)</div><div class='ctx'> </div><div class='ctx'> 	ice_vf_pre_vsi_rebuild(vf);</div><div class='ctx'> </div><div class='del'>-	if (ice_vf_recreate_vsi(vf)) {</div><div class='add'>+	if (ice_vf_reconfig_vsi(vf)) {</div><div class='ctx'> 		dev_err(dev, "Failed to release and setup the VF%u's VSI\n",</div><div class='ctx'> 			vf-&gt;vf_id);</div><div class='ctx'> 		err = -EFAULT;</div><div class='hunk'>@@ -928,7 +957,7 @@ int ice_reset_vf(struct ice_vf *vf, u32 flags)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ice_eswitch_update_repr(vsi);</div><div class='add'>+	ice_eswitch_update_repr(vf-&gt;repr_id, vsi);</div><div class='ctx'> </div><div class='ctx'> 	/* if the VF has been reset allow it to come up again */</div><div class='ctx'> 	ice_mbx_clear_malvf(&amp;vf-&gt;mbx_info);</div><div class='hunk'>@@ -937,6 +966,11 @@ out_unlock:</div><div class='ctx'> 	if (flags &amp; ICE_VF_RESET_LOCK)</div><div class='ctx'> 		mutex_unlock(&amp;vf-&gt;cfg_lock);</div><div class='ctx'> </div><div class='add'>+	if (lag &amp;&amp; lag-&gt;bonded &amp;&amp; lag-&gt;primary &amp;&amp;</div><div class='add'>+	    act_prt != ICE_LAG_INVALID_PORT)</div><div class='add'>+		ice_lag_move_vf_nodes_cfg(lag, pri_prt, act_prt);</div><div class='add'>+	mutex_unlock(&amp;pf-&gt;lag_mutex);</div><div class='add'>+</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib.h b/drivers/net/ethernet/intel/ice/ice_vf_lib.h<br/>index 93c774f2f437..0cc9034065c5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_vf_lib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib.h</a></div><div class='hunk'>@@ -62,7 +62,6 @@ struct ice_vf_ops {</div><div class='ctx'> 	bool (*poll_reset_status)(struct ice_vf *vf);</div><div class='ctx'> 	void (*clear_reset_trigger)(struct ice_vf *vf);</div><div class='ctx'> 	void (*irq_close)(struct ice_vf *vf);</div><div class='del'>-	int (*create_vsi)(struct ice_vf *vf);</div><div class='ctx'> 	void (*post_vsi_rebuild)(struct ice_vf *vf);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -130,7 +129,7 @@ struct ice_vf {</div><div class='ctx'> 	struct ice_mdd_vf_events mdd_tx_events;</div><div class='ctx'> 	DECLARE_BITMAP(opcodes_allowlist, VIRTCHNL_OP_MAX);</div><div class='ctx'> </div><div class='del'>-	struct ice_repr *repr;</div><div class='add'>+	unsigned long repr_id;</div><div class='ctx'> 	const struct ice_virtchnl_ops *virtchnl_ops;</div><div class='ctx'> 	const struct ice_vf_ops *vf_ops;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_vf_lib_private.h b/drivers/net/ethernet/intel/ice/ice_vf_lib_private.h<br/>index 0c7e77c0a09f..91ba7fe0eaee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib_private.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_vf_lib_private.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_lib_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_lib_private.h</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'> #warning "Only include ice_vf_lib_private.h in CONFIG_PCI_IOV virtualization files"</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+int ice_vf_reconfig_vsi(struct ice_vf *vf);</div><div class='ctx'> void ice_initialize_vf_entry(struct ice_vf *vf);</div><div class='ctx'> void ice_dis_vf_qs(struct ice_vf *vf);</div><div class='ctx'> int ice_check_vf_init(struct ice_vf *vf);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c b/drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c<br/>index d7b10dc67f03..80dc4bcdd3a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vf_vsi_vlan_ops.c</a></div><div class='hunk'>@@ -32,7 +32,6 @@ static void ice_port_vlan_on(struct ice_vsi *vsi)</div><div class='ctx'> 		/* setup outer VLAN ops */</div><div class='ctx'> 		vlan_ops-&gt;set_port_vlan = ice_vsi_set_outer_port_vlan;</div><div class='ctx'> 		vlan_ops-&gt;clear_port_vlan = ice_vsi_clear_outer_port_vlan;</div><div class='del'>-		vlan_ops-&gt;clear_port_vlan = ice_vsi_clear_outer_port_vlan;</div><div class='ctx'> </div><div class='ctx'> 		/* setup inner VLAN ops */</div><div class='ctx'> 		vlan_ops = &amp;vsi-&gt;inner_vlan_ops;</div><div class='hunk'>@@ -47,8 +46,13 @@ static void ice_port_vlan_on(struct ice_vsi *vsi)</div><div class='ctx'> </div><div class='ctx'> 		vlan_ops-&gt;set_port_vlan = ice_vsi_set_inner_port_vlan;</div><div class='ctx'> 		vlan_ops-&gt;clear_port_vlan = ice_vsi_clear_inner_port_vlan;</div><div class='del'>-		vlan_ops-&gt;clear_port_vlan = ice_vsi_clear_inner_port_vlan;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	/* all Rx traffic should be in the domain of the assigned port VLAN,</div><div class='add'>+	 * so prevent disabling Rx VLAN filtering</div><div class='add'>+	 */</div><div class='add'>+	vlan_ops-&gt;dis_rx_filtering = noop_vlan;</div><div class='add'>+</div><div class='ctx'> 	vlan_ops-&gt;ena_rx_filtering = ice_vsi_ena_rx_vlan_filtering;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -77,6 +81,8 @@ static void ice_port_vlan_off(struct ice_vsi *vsi)</div><div class='ctx'> 		vlan_ops-&gt;del_vlan = ice_vsi_del_vlan;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	vlan_ops-&gt;dis_rx_filtering = ice_vsi_dis_rx_vlan_filtering;</div><div class='add'>+</div><div class='ctx'> 	if (!test_bit(ICE_FLAG_VF_VLAN_PRUNING, pf-&gt;flags))</div><div class='ctx'> 		vlan_ops-&gt;ena_rx_filtering = noop_vlan;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -141,7 +147,6 @@ void ice_vf_vsi_init_vlan_ops(struct ice_vsi *vsi)</div><div class='ctx'> 		&amp;vsi-&gt;outer_vlan_ops : &amp;vsi-&gt;inner_vlan_ops;</div><div class='ctx'> </div><div class='ctx'> 	vlan_ops-&gt;add_vlan = ice_vsi_add_vlan;</div><div class='del'>-	vlan_ops-&gt;dis_rx_filtering = ice_vsi_dis_rx_vlan_filtering;</div><div class='ctx'> 	vlan_ops-&gt;ena_tx_filtering = ice_vsi_ena_tx_vlan_filtering;</div><div class='ctx'> 	vlan_ops-&gt;dis_tx_filtering = ice_vsi_dis_tx_vlan_filtering;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl.c b/drivers/net/ethernet/intel/ice/ice_virtchnl.c<br/>index cdf17b1e2f25..c925813ec9ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_virtchnl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl.c</a></div><div class='hunk'>@@ -689,9 +689,7 @@ out:</div><div class='ctx'>  * a specific virtchnl RSS cfg</div><div class='ctx'>  * @hw: pointer to the hardware</div><div class='ctx'>  * @rss_cfg: pointer to the virtchnl RSS cfg</div><div class='del'>- * @addl_hdrs: pointer to the protocol header fields (ICE_FLOW_SEG_HDR_*)</div><div class='del'>- * to configure</div><div class='del'>- * @hash_flds: pointer to the hash bit fields (ICE_FLOW_HASH_*) to configure</div><div class='add'>+ * @hash_cfg: pointer to the HW hash configuration</div><div class='ctx'>  *</div><div class='ctx'>  * Return true if all the protocol header and hash fields in the RSS cfg could</div><div class='ctx'>  * be parsed, else return false</div><div class='hunk'>@@ -699,13 +697,23 @@ out:</div><div class='ctx'>  * This function parses the virtchnl RSS cfg to be the intended</div><div class='ctx'>  * hash fields and the intended header for RSS configuration</div><div class='ctx'>  */</div><div class='del'>-static bool</div><div class='del'>-ice_vc_parse_rss_cfg(struct ice_hw *hw, struct virtchnl_rss_cfg *rss_cfg,</div><div class='del'>-		     u32 *addl_hdrs, u64 *hash_flds)</div><div class='add'>+static bool ice_vc_parse_rss_cfg(struct ice_hw *hw,</div><div class='add'>+				 struct virtchnl_rss_cfg *rss_cfg,</div><div class='add'>+				 struct ice_rss_hash_cfg *hash_cfg)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ice_vc_hash_field_match_type *hf_list;</div><div class='ctx'> 	const struct ice_vc_hdr_match_type *hdr_list;</div><div class='ctx'> 	int i, hf_list_len, hdr_list_len;</div><div class='add'>+	u32 *addl_hdrs = &amp;hash_cfg-&gt;addl_hdrs;</div><div class='add'>+	u64 *hash_flds = &amp;hash_cfg-&gt;hash_flds;</div><div class='add'>+</div><div class='add'>+	/* set outer layer RSS as default */</div><div class='add'>+	hash_cfg-&gt;hdr_type = ICE_RSS_OUTER_HEADERS;</div><div class='add'>+</div><div class='add'>+	if (rss_cfg-&gt;rss_algorithm == VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC)</div><div class='add'>+		hash_cfg-&gt;symm = true;</div><div class='add'>+	else</div><div class='add'>+		hash_cfg-&gt;symm = false;</div><div class='ctx'> </div><div class='ctx'> 	hf_list = ice_vc_hash_field_list;</div><div class='ctx'> 	hf_list_len = ARRAY_SIZE(ice_vc_hash_field_list);</div><div class='hunk'>@@ -823,8 +831,8 @@ static int ice_vc_handle_rss_cfg(struct ice_vf *vf, u8 *msg, bool add)</div><div class='ctx'> 		int status;</div><div class='ctx'> </div><div class='ctx'> 		lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;</div><div class='del'>-		hash_type = add ? ICE_AQ_VSI_Q_OPT_RSS_XOR :</div><div class='del'>-				ICE_AQ_VSI_Q_OPT_RSS_TPLZ;</div><div class='add'>+		hash_type = add ? ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR :</div><div class='add'>+				ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ;</div><div class='ctx'> </div><div class='ctx'> 		ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);</div><div class='ctx'> 		if (!ctx) {</div><div class='hunk'>@@ -832,11 +840,9 @@ static int ice_vc_handle_rss_cfg(struct ice_vf *vf, u8 *msg, bool add)</div><div class='ctx'> 			goto error_param;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ctx-&gt;info.q_opt_rss = ((lut_type &lt;&lt;</div><div class='del'>-					ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &amp;</div><div class='del'>-				       ICE_AQ_VSI_Q_OPT_RSS_LUT_M) |</div><div class='del'>-				       (hash_type &amp;</div><div class='del'>-					ICE_AQ_VSI_Q_OPT_RSS_HASH_M);</div><div class='add'>+		ctx-&gt;info.q_opt_rss =</div><div class='add'>+			FIELD_PREP(ICE_AQ_VSI_Q_OPT_RSS_LUT_M, lut_type) |</div><div class='add'>+			FIELD_PREP(ICE_AQ_VSI_Q_OPT_RSS_HASH_M, hash_type);</div><div class='ctx'> </div><div class='ctx'> 		/* Preserve existing queueing option setting */</div><div class='ctx'> 		ctx-&gt;info.q_opt_rss |= (vsi-&gt;info.q_opt_rss &amp;</div><div class='hunk'>@@ -858,18 +864,24 @@ static int ice_vc_handle_rss_cfg(struct ice_vf *vf, u8 *msg, bool add)</div><div class='ctx'> </div><div class='ctx'> 		kfree(ctx);</div><div class='ctx'> 	} else {</div><div class='del'>-		u32 addl_hdrs = ICE_FLOW_SEG_HDR_NONE;</div><div class='del'>-		u64 hash_flds = ICE_HASH_INVALID;</div><div class='add'>+		struct ice_rss_hash_cfg cfg;</div><div class='ctx'> </div><div class='del'>-		if (!ice_vc_parse_rss_cfg(hw, rss_cfg, &amp;addl_hdrs,</div><div class='del'>-					  &amp;hash_flds)) {</div><div class='add'>+		/* Only check for none raw pattern case */</div><div class='add'>+		if (!ice_vc_validate_pattern(vf, &amp;rss_cfg-&gt;proto_hdrs)) {</div><div class='add'>+			v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='add'>+			goto error_param;</div><div class='add'>+		}</div><div class='add'>+		cfg.addl_hdrs = ICE_FLOW_SEG_HDR_NONE;</div><div class='add'>+		cfg.hash_flds = ICE_HASH_INVALID;</div><div class='add'>+		cfg.hdr_type = ICE_RSS_ANY_HEADERS;</div><div class='add'>+</div><div class='add'>+		if (!ice_vc_parse_rss_cfg(hw, rss_cfg, &amp;cfg)) {</div><div class='ctx'> 			v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='ctx'> 			goto error_param;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (add) {</div><div class='del'>-			if (ice_add_rss_cfg(hw, vsi-&gt;idx, hash_flds,</div><div class='del'>-					    addl_hdrs)) {</div><div class='add'>+			if (ice_add_rss_cfg(hw, vsi, &amp;cfg)) {</div><div class='ctx'> 				v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='ctx'> 				dev_err(dev, "ice_add_rss_cfg failed for vsi = %d, v_ret = %d\n",</div><div class='ctx'> 					vsi-&gt;vsi_num, v_ret);</div><div class='hunk'>@@ -877,8 +889,7 @@ static int ice_vc_handle_rss_cfg(struct ice_vf *vf, u8 *msg, bool add)</div><div class='ctx'> 		} else {</div><div class='ctx'> 			int status;</div><div class='ctx'> </div><div class='del'>-			status = ice_rem_rss_cfg(hw, vsi-&gt;idx, hash_flds,</div><div class='del'>-						 addl_hdrs);</div><div class='add'>+			status = ice_rem_rss_cfg(hw, vsi-&gt;idx, &amp;cfg);</div><div class='ctx'> 			/* We just ignore -ENOENT, because if two configurations</div><div class='ctx'> 			 * share the same profile remove one of them actually</div><div class='ctx'> 			 * removes both, since the profile is deleted.</div><div class='hunk'>@@ -989,6 +1000,51 @@ error_param:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * ice_vc_config_rss_hfunc</div><div class='add'>+ * @vf: pointer to the VF info</div><div class='add'>+ * @msg: pointer to the msg buffer</div><div class='add'>+ *</div><div class='add'>+ * Configure the VF's RSS Hash function</div><div class='add'>+ */</div><div class='add'>+static int ice_vc_config_rss_hfunc(struct ice_vf *vf, u8 *msg)</div><div class='add'>+{</div><div class='add'>+	struct virtchnl_rss_hfunc *vrh = (struct virtchnl_rss_hfunc *)msg;</div><div class='add'>+	enum virtchnl_status_code v_ret = VIRTCHNL_STATUS_SUCCESS;</div><div class='add'>+	u8 hfunc = ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ;</div><div class='add'>+	struct ice_vsi *vsi;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ICE_VF_STATE_ACTIVE, vf-&gt;vf_states)) {</div><div class='add'>+		v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='add'>+		goto error_param;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!ice_vc_isvalid_vsi_id(vf, vrh-&gt;vsi_id)) {</div><div class='add'>+		v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='add'>+		goto error_param;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ICE_FLAG_RSS_ENA, vf-&gt;pf-&gt;flags)) {</div><div class='add'>+		v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='add'>+		goto error_param;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	vsi = ice_get_vf_vsi(vf);</div><div class='add'>+	if (!vsi) {</div><div class='add'>+		v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='add'>+		goto error_param;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (vrh-&gt;rss_algorithm == VIRTCHNL_RSS_ALG_TOEPLITZ_SYMMETRIC)</div><div class='add'>+		hfunc = ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ;</div><div class='add'>+</div><div class='add'>+	if (ice_set_rss_hfunc(vsi, hfunc))</div><div class='add'>+		v_ret = VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR;</div><div class='add'>+error_param:</div><div class='add'>+	return ice_vc_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_HFUNC, v_ret,</div><div class='add'>+				     NULL, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ice_vc_cfg_promiscuous_mode_msg</div><div class='ctx'>  * @vf: pointer to the VF info</div><div class='ctx'>  * @msg: pointer to the msg buffer</div><div class='hunk'>@@ -1523,7 +1579,6 @@ static int ice_vc_cfg_irq_map_msg(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 	u16 num_q_vectors_mapped, vsi_id, vector_id;</div><div class='ctx'> 	struct virtchnl_irq_map_info *irqmap_info;</div><div class='ctx'> 	struct virtchnl_vector_map *map;</div><div class='del'>-	struct ice_pf *pf = vf-&gt;pf;</div><div class='ctx'> 	struct ice_vsi *vsi;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='hunk'>@@ -1535,7 +1590,7 @@ static int ice_vc_cfg_irq_map_msg(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 	 * there is actually at least a single VF queue vector mapped</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!test_bit(ICE_VF_STATE_ACTIVE, vf-&gt;vf_states) ||</div><div class='del'>-	    pf-&gt;vfs.num_msix_per &lt; num_q_vectors_mapped ||</div><div class='add'>+	    vf-&gt;num_msix &lt; num_q_vectors_mapped ||</div><div class='ctx'> 	    !num_q_vectors_mapped) {</div><div class='ctx'> 		v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='ctx'> 		goto error_param;</div><div class='hunk'>@@ -1557,7 +1612,7 @@ static int ice_vc_cfg_irq_map_msg(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 		/* vector_id is always 0-based for each VF, and can never be</div><div class='ctx'> 		 * larger than or equal to the max allowed interrupts per VF</div><div class='ctx'> 		 */</div><div class='del'>-		if (!(vector_id &lt; pf-&gt;vfs.num_msix_per) ||</div><div class='add'>+		if (!(vector_id &lt; vf-&gt;num_msix) ||</div><div class='ctx'> 		    !ice_vc_isvalid_vsi_id(vf, vsi_id) ||</div><div class='ctx'> 		    (!vector_id &amp;&amp; (map-&gt;rxq_map || map-&gt;txq_map))) {</div><div class='ctx'> 			v_ret = VIRTCHNL_STATUS_ERR_PARAM;</div><div class='hunk'>@@ -1603,9 +1658,24 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 	    (struct virtchnl_vsi_queue_config_info *)msg;</div><div class='ctx'> 	struct virtchnl_queue_pair_info *qpi;</div><div class='ctx'> 	struct ice_pf *pf = vf-&gt;pf;</div><div class='add'>+	struct ice_lag *lag;</div><div class='ctx'> 	struct ice_vsi *vsi;</div><div class='add'>+	u8 act_prt, pri_prt;</div><div class='ctx'> 	int i = -1, q_idx;</div><div class='ctx'> </div><div class='add'>+	lag = pf-&gt;lag;</div><div class='add'>+	mutex_lock(&amp;pf-&gt;lag_mutex);</div><div class='add'>+	act_prt = ICE_LAG_INVALID_PORT;</div><div class='add'>+	pri_prt = pf-&gt;hw.port_info-&gt;lport;</div><div class='add'>+	if (lag &amp;&amp; lag-&gt;bonded &amp;&amp; lag-&gt;primary) {</div><div class='add'>+		act_prt = lag-&gt;active_port;</div><div class='add'>+		if (act_prt != pri_prt &amp;&amp; act_prt != ICE_LAG_INVALID_PORT &amp;&amp;</div><div class='add'>+		    lag-&gt;upper_netdev)</div><div class='add'>+			ice_lag_move_vf_nodes_cfg(lag, act_prt, pri_prt);</div><div class='add'>+		else</div><div class='add'>+			act_prt = ICE_LAG_INVALID_PORT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (!test_bit(ICE_VF_STATE_ACTIVE, vf-&gt;vf_states))</div><div class='ctx'> 		goto error_param;</div><div class='ctx'> </div><div class='hunk'>@@ -1729,6 +1799,11 @@ static int ice_vc_cfg_qs_msg(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (lag &amp;&amp; lag-&gt;bonded &amp;&amp; lag-&gt;primary &amp;&amp;</div><div class='add'>+	    act_prt != ICE_LAG_INVALID_PORT)</div><div class='add'>+		ice_lag_move_vf_nodes_cfg(lag, pri_prt, act_prt);</div><div class='add'>+	mutex_unlock(&amp;pf-&gt;lag_mutex);</div><div class='add'>+</div><div class='ctx'> 	/* send the response to the VF */</div><div class='ctx'> 	return ice_vc_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,</div><div class='ctx'> 				     VIRTCHNL_STATUS_SUCCESS, NULL, 0);</div><div class='hunk'>@@ -1743,6 +1818,11 @@ error_param:</div><div class='ctx'> 				vf-&gt;vf_id, i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (lag &amp;&amp; lag-&gt;bonded &amp;&amp; lag-&gt;primary &amp;&amp;</div><div class='add'>+	    act_prt != ICE_LAG_INVALID_PORT)</div><div class='add'>+		ice_lag_move_vf_nodes_cfg(lag, pri_prt, act_prt);</div><div class='add'>+	mutex_unlock(&amp;pf-&gt;lag_mutex);</div><div class='add'>+</div><div class='ctx'> 	ice_lag_move_new_vf_nodes(vf);</div><div class='ctx'> </div><div class='ctx'> 	/* send the response to the VF */</div><div class='hunk'>@@ -2610,7 +2690,7 @@ static int ice_vc_set_rss_hena(struct ice_vf *vf, u8 *msg)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (vrh-&gt;hena) {</div><div class='del'>-		status = ice_add_avf_rss_cfg(&amp;pf-&gt;hw, vsi-&gt;idx, vrh-&gt;hena);</div><div class='add'>+		status = ice_add_avf_rss_cfg(&amp;pf-&gt;hw, vsi, vrh-&gt;hena);</div><div class='ctx'> 		v_ret = ice_err_to_virt_err(status);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3022,7 +3102,7 @@ static struct ice_vlan ice_vc_to_vlan(struct virtchnl_vlan *vc_vlan)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_vlan vlan = { 0 };</div><div class='ctx'> </div><div class='del'>-	vlan.prio = (vc_vlan-&gt;tci &amp; VLAN_PRIO_MASK) &gt;&gt; VLAN_PRIO_SHIFT;</div><div class='add'>+	vlan.prio = FIELD_GET(VLAN_PRIO_MASK, vc_vlan-&gt;tci);</div><div class='ctx'> 	vlan.vid = vc_vlan-&gt;tci &amp; VLAN_VID_MASK;</div><div class='ctx'> 	vlan.tpid = vc_vlan-&gt;tpid;</div><div class='ctx'> </div><div class='hunk'>@@ -3731,6 +3811,7 @@ static const struct ice_virtchnl_ops ice_virtchnl_dflt_ops = {</div><div class='ctx'> 	.cfg_irq_map_msg = ice_vc_cfg_irq_map_msg,</div><div class='ctx'> 	.config_rss_key = ice_vc_config_rss_key,</div><div class='ctx'> 	.config_rss_lut = ice_vc_config_rss_lut,</div><div class='add'>+	.config_rss_hfunc = ice_vc_config_rss_hfunc,</div><div class='ctx'> 	.get_stats_msg = ice_vc_get_stats_msg,</div><div class='ctx'> 	.cfg_promiscuous_mode_msg = ice_vc_cfg_promiscuous_mode_msg,</div><div class='ctx'> 	.add_vlan_msg = ice_vc_add_vlan_msg,</div><div class='hunk'>@@ -3860,6 +3941,7 @@ static const struct ice_virtchnl_ops ice_virtchnl_repr_ops = {</div><div class='ctx'> 	.cfg_irq_map_msg = ice_vc_cfg_irq_map_msg,</div><div class='ctx'> 	.config_rss_key = ice_vc_config_rss_key,</div><div class='ctx'> 	.config_rss_lut = ice_vc_config_rss_lut,</div><div class='add'>+	.config_rss_hfunc = ice_vc_config_rss_hfunc,</div><div class='ctx'> 	.get_stats_msg = ice_vc_get_stats_msg,</div><div class='ctx'> 	.cfg_promiscuous_mode_msg = ice_vc_repr_cfg_promiscuous_mode,</div><div class='ctx'> 	.add_vlan_msg = ice_vc_add_vlan_msg,</div><div class='hunk'>@@ -4042,6 +4124,9 @@ error_handler:</div><div class='ctx'> 	case VIRTCHNL_OP_CONFIG_RSS_LUT:</div><div class='ctx'> 		err = ops-&gt;config_rss_lut(vf, msg);</div><div class='ctx'> 		break;</div><div class='add'>+	case VIRTCHNL_OP_CONFIG_RSS_HFUNC:</div><div class='add'>+		err = ops-&gt;config_rss_hfunc(vf, msg);</div><div class='add'>+		break;</div><div class='ctx'> 	case VIRTCHNL_OP_GET_STATS:</div><div class='ctx'> 		err = ops-&gt;get_stats_msg(vf, msg);</div><div class='ctx'> 		break;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl.h b/drivers/net/ethernet/intel/ice/ice_virtchnl.h<br/>index cd747718de73..60dfbe05980a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_virtchnl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl.h</a></div><div class='hunk'>@@ -32,6 +32,7 @@ struct ice_virtchnl_ops {</div><div class='ctx'> 	int (*cfg_irq_map_msg)(struct ice_vf *vf, u8 *msg);</div><div class='ctx'> 	int (*config_rss_key)(struct ice_vf *vf, u8 *msg);</div><div class='ctx'> 	int (*config_rss_lut)(struct ice_vf *vf, u8 *msg);</div><div class='add'>+	int (*config_rss_hfunc)(struct ice_vf *vf, u8 *msg);</div><div class='ctx'> 	int (*get_stats_msg)(struct ice_vf *vf, u8 *msg);</div><div class='ctx'> 	int (*cfg_promiscuous_mode_msg)(struct ice_vf *vf, u8 *msg);</div><div class='ctx'> 	int (*add_vlan_msg)(struct ice_vf *vf, u8 *msg);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c<br/>index 7d547fa616fa..5e19d48a05b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl_allowlist.c</a></div><div class='hunk'>@@ -68,6 +68,7 @@ static const u32 vlan_v2_allowlist_opcodes[] = {</div><div class='ctx'> static const u32 rss_pf_allowlist_opcodes[] = {</div><div class='ctx'> 	VIRTCHNL_OP_CONFIG_RSS_KEY, VIRTCHNL_OP_CONFIG_RSS_LUT,</div><div class='ctx'> 	VIRTCHNL_OP_GET_RSS_HENA_CAPS, VIRTCHNL_OP_SET_RSS_HENA,</div><div class='add'>+	VIRTCHNL_OP_CONFIG_RSS_HFUNC,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c<br/>index 24b23b7ef04a..f001553e1a1a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_virtchnl_fdir.c</a></div><div class='hunk'>@@ -10,19 +10,6 @@</div><div class='ctx'> #define to_fltr_conf_from_desc(p) \</div><div class='ctx'> 	container_of(p, struct virtchnl_fdir_fltr_conf, input)</div><div class='ctx'> </div><div class='del'>-#define ICE_FLOW_PROF_TYPE_S	0</div><div class='del'>-#define ICE_FLOW_PROF_TYPE_M	(0xFFFFFFFFULL &lt;&lt; ICE_FLOW_PROF_TYPE_S)</div><div class='del'>-#define ICE_FLOW_PROF_VSI_S	32</div><div class='del'>-#define ICE_FLOW_PROF_VSI_M	(0xFFFFFFFFULL &lt;&lt; ICE_FLOW_PROF_VSI_S)</div><div class='del'>-</div><div class='del'>-/* Flow profile ID format:</div><div class='del'>- * [0:31] - flow type, flow + tun_offs</div><div class='del'>- * [32:63] - VSI index</div><div class='del'>- */</div><div class='del'>-#define ICE_FLOW_PROF_FD(vsi, flow, tun_offs) \</div><div class='del'>-	((u64)(((((flow) + (tun_offs)) &amp; ICE_FLOW_PROF_TYPE_M)) | \</div><div class='del'>-	      (((u64)(vsi) &lt;&lt; ICE_FLOW_PROF_VSI_S) &amp; ICE_FLOW_PROF_VSI_M)))</div><div class='del'>-</div><div class='ctx'> #define GTPU_TEID_OFFSET 4</div><div class='ctx'> #define GTPU_EH_QFI_OFFSET 1</div><div class='ctx'> #define GTPU_EH_QFI_MASK 0x3F</div><div class='hunk'>@@ -493,6 +480,7 @@ ice_vc_fdir_rem_prof(struct ice_vf *vf, enum ice_fltr_ptype flow, int tun)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	vf_prof = fdir-&gt;fdir_prof[flow];</div><div class='add'>+	prof_id = vf_prof-&gt;prof_id[tun];</div><div class='ctx'> </div><div class='ctx'> 	vf_vsi = ice_get_vf_vsi(vf);</div><div class='ctx'> 	if (!vf_vsi) {</div><div class='hunk'>@@ -503,9 +491,6 @@ ice_vc_fdir_rem_prof(struct ice_vf *vf, enum ice_fltr_ptype flow, int tun)</div><div class='ctx'> 	if (!fdir-&gt;prof_entry_cnt[flow][tun])</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	prof_id = ICE_FLOW_PROF_FD(vf_vsi-&gt;vsi_num,</div><div class='del'>-				   flow, tun ? ICE_FLTR_PTYPE_MAX : 0);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; fdir-&gt;prof_entry_cnt[flow][tun]; i++)</div><div class='ctx'> 		if (vf_prof-&gt;entry_h[i][tun]) {</div><div class='ctx'> 			u16 vsi_num = ice_get_hw_vsi_num(hw, vf_prof-&gt;vsi_h[i]);</div><div class='hunk'>@@ -647,7 +632,6 @@ ice_vc_fdir_write_flow_prof(struct ice_vf *vf, enum ice_fltr_ptype flow,</div><div class='ctx'> 	struct ice_hw *hw;</div><div class='ctx'> 	u64 entry1_h = 0;</div><div class='ctx'> 	u64 entry2_h = 0;</div><div class='del'>-	u64 prof_id;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	pf = vf-&gt;pf;</div><div class='hunk'>@@ -681,18 +665,15 @@ ice_vc_fdir_write_flow_prof(struct ice_vf *vf, enum ice_fltr_ptype flow,</div><div class='ctx'> 		ice_vc_fdir_rem_prof(vf, flow, tun);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	prof_id = ICE_FLOW_PROF_FD(vf_vsi-&gt;vsi_num, flow,</div><div class='del'>-				   tun ? ICE_FLTR_PTYPE_MAX : 0);</div><div class='del'>-</div><div class='del'>-	ret = ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX, prof_id, seg,</div><div class='del'>-				tun + 1, &amp;prof);</div><div class='add'>+	ret = ice_flow_add_prof(hw, ICE_BLK_FD, ICE_FLOW_RX, seg,</div><div class='add'>+				tun + 1, false, &amp;prof);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		dev_dbg(dev, "Could not add VSI flow 0x%x for VF %d\n",</div><div class='ctx'> 			flow, vf-&gt;vf_id);</div><div class='ctx'> 		goto err_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id, vf_vsi-&gt;idx,</div><div class='add'>+	ret = ice_flow_add_entry(hw, ICE_BLK_FD, prof-&gt;id, vf_vsi-&gt;idx,</div><div class='ctx'> 				 vf_vsi-&gt;idx, ICE_FLOW_PRIO_NORMAL,</div><div class='ctx'> 				 seg, &amp;entry1_h);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -701,7 +682,7 @@ ice_vc_fdir_write_flow_prof(struct ice_vf *vf, enum ice_fltr_ptype flow,</div><div class='ctx'> 		goto err_prof;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = ice_flow_add_entry(hw, ICE_BLK_FD, prof_id, vf_vsi-&gt;idx,</div><div class='add'>+	ret = ice_flow_add_entry(hw, ICE_BLK_FD, prof-&gt;id, vf_vsi-&gt;idx,</div><div class='ctx'> 				 ctrl_vsi-&gt;idx, ICE_FLOW_PRIO_NORMAL,</div><div class='ctx'> 				 seg, &amp;entry2_h);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -725,14 +706,16 @@ ice_vc_fdir_write_flow_prof(struct ice_vf *vf, enum ice_fltr_ptype flow,</div><div class='ctx'> 	vf_prof-&gt;cnt++;</div><div class='ctx'> 	fdir-&gt;prof_entry_cnt[flow][tun]++;</div><div class='ctx'> </div><div class='add'>+	vf_prof-&gt;prof_id[tun] = prof-&gt;id;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_entry_1:</div><div class='ctx'> 	ice_rem_prof_id_flow(hw, ICE_BLK_FD,</div><div class='del'>-			     ice_get_hw_vsi_num(hw, vf_vsi-&gt;idx), prof_id);</div><div class='add'>+			     ice_get_hw_vsi_num(hw, vf_vsi-&gt;idx), prof-&gt;id);</div><div class='ctx'> 	ice_flow_rem_entry(hw, ICE_BLK_FD, entry1_h);</div><div class='ctx'> err_prof:</div><div class='del'>-	ice_flow_rem_prof(hw, ICE_BLK_FD, prof_id);</div><div class='add'>+	ice_flow_rem_prof(hw, ICE_BLK_FD, prof-&gt;id);</div><div class='ctx'> err_exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1480,16 +1463,15 @@ ice_vf_verify_rx_desc(struct ice_vf *vf, struct ice_vf_fdir_ctx *ctx,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	stat_err = le16_to_cpu(ctx-&gt;rx_desc.wb.status_error0);</div><div class='del'>-	if (((stat_err &amp; ICE_FXD_FLTR_WB_QW1_DD_M) &gt;&gt;</div><div class='del'>-	    ICE_FXD_FLTR_WB_QW1_DD_S) != ICE_FXD_FLTR_WB_QW1_DD_YES) {</div><div class='add'>+	if (FIELD_GET(ICE_FXD_FLTR_WB_QW1_DD_M, stat_err) !=</div><div class='add'>+	    ICE_FXD_FLTR_WB_QW1_DD_YES) {</div><div class='ctx'> 		*status = VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE;</div><div class='ctx'> 		dev_err(dev, "VF %d: Desc Done not set\n", vf-&gt;vf_id);</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		goto err_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	prog_id = (stat_err &amp; ICE_FXD_FLTR_WB_QW1_PROG_ID_M) &gt;&gt;</div><div class='del'>-		ICE_FXD_FLTR_WB_QW1_PROG_ID_S;</div><div class='add'>+	prog_id = FIELD_GET(ICE_FXD_FLTR_WB_QW1_PROG_ID_M, stat_err);</div><div class='ctx'> 	if (prog_id == ICE_FXD_FLTR_WB_QW1_PROG_ADD &amp;&amp;</div><div class='ctx'> 	    ctx-&gt;v_opcode != VIRTCHNL_OP_ADD_FDIR_FILTER) {</div><div class='ctx'> 		dev_err(dev, "VF %d: Desc show add, but ctx not",</div><div class='hunk'>@@ -1508,8 +1490,7 @@ ice_vf_verify_rx_desc(struct ice_vf *vf, struct ice_vf_fdir_ctx *ctx,</div><div class='ctx'> 		goto err_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	error = (stat_err &amp; ICE_FXD_FLTR_WB_QW1_FAIL_M) &gt;&gt;</div><div class='del'>-		ICE_FXD_FLTR_WB_QW1_FAIL_S;</div><div class='add'>+	error = FIELD_GET(ICE_FXD_FLTR_WB_QW1_FAIL_M, stat_err);</div><div class='ctx'> 	if (error == ICE_FXD_FLTR_WB_QW1_FAIL_YES) {</div><div class='ctx'> 		if (prog_id == ICE_FXD_FLTR_WB_QW1_PROG_ADD) {</div><div class='ctx'> 			dev_err(dev, "VF %d, Failed to add FDIR rule due to no space in the table",</div><div class='hunk'>@@ -1524,8 +1505,7 @@ ice_vf_verify_rx_desc(struct ice_vf *vf, struct ice_vf_fdir_ctx *ctx,</div><div class='ctx'> 		goto err_exit;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	error = (stat_err &amp; ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M) &gt;&gt;</div><div class='del'>-		ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S;</div><div class='add'>+	error = FIELD_GET(ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M, stat_err);</div><div class='ctx'> 	if (error == ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES) {</div><div class='ctx'> 		dev_err(dev, "VF %d: Profile matching error", vf-&gt;vf_id);</div><div class='ctx'> 		*status = VIRTCHNL_FDIR_FAILURE_RULE_NORESOURCE;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c b/drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c<br/>index 76266e709a39..2e9ad27cb9d1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_vsi_vlan_lib.c</a></div><div class='hunk'>@@ -131,6 +131,7 @@ static int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)</div><div class='ctx'> {</div><div class='ctx'> 	struct ice_hw *hw = &amp;vsi-&gt;back-&gt;hw;</div><div class='ctx'> 	struct ice_vsi_ctx *ctxt;</div><div class='add'>+	u8 *ivf;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	/* do not allow modifying VLAN stripping when a port VLAN is configured</div><div class='hunk'>@@ -143,19 +144,24 @@ static int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)</div><div class='ctx'> 	if (!ctxt)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	ivf = &amp;ctxt-&gt;info.inner_vlan_flags;</div><div class='add'>+</div><div class='ctx'> 	/* Here we are configuring what the VSI should do with the VLAN tag in</div><div class='ctx'> 	 * the Rx packet. We can either leave the tag in the packet or put it in</div><div class='ctx'> 	 * the Rx descriptor.</div><div class='ctx'> 	 */</div><div class='del'>-	if (ena)</div><div class='add'>+	if (ena) {</div><div class='ctx'> 		/* Strip VLAN tag from Rx packet and put it in the desc */</div><div class='del'>-		ctxt-&gt;info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;</div><div class='del'>-	else</div><div class='add'>+		*ivf = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M,</div><div class='add'>+				  ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH);</div><div class='add'>+	} else {</div><div class='ctx'> 		/* Disable stripping. Leave tag in packet */</div><div class='del'>-		ctxt-&gt;info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;</div><div class='add'>+		*ivf = FIELD_PREP(ICE_AQ_VSI_INNER_VLAN_EMODE_M,</div><div class='add'>+				  ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Allow all packets untagged/tagged */</div><div class='del'>-	ctxt-&gt;info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;</div><div class='add'>+	*ivf |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;</div><div class='ctx'> </div><div class='ctx'> 	ctxt-&gt;info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);</div><div class='ctx'> </div><div class='hunk'>@@ -481,10 +487,11 @@ int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi, u16 tpid)</div><div class='ctx'> 	ctxt-&gt;info.outer_vlan_flags = vsi-&gt;info.outer_vlan_flags &amp;</div><div class='ctx'> 		~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);</div><div class='ctx'> 	ctxt-&gt;info.outer_vlan_flags |=</div><div class='del'>-		((ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH &lt;&lt;</div><div class='del'>-		  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |</div><div class='del'>-		 ((tag_type &lt;&lt; ICE_AQ_VSI_OUTER_TAG_TYPE_S) &amp;</div><div class='del'>-		  ICE_AQ_VSI_OUTER_TAG_TYPE_M));</div><div class='add'>+		/* we want EMODE_SHOW_BOTH, but that value is zero, so the line</div><div class='add'>+		 * above clears it well enough that we don't need to try to set</div><div class='add'>+		 * zero here, so just do the tag type</div><div class='add'>+		 */</div><div class='add'>+		 FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type);</div><div class='ctx'> </div><div class='ctx'> 	err = ice_update_vsi(hw, vsi-&gt;idx, ctxt, NULL);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -589,11 +596,9 @@ int ice_vsi_ena_outer_insertion(struct ice_vsi *vsi, u16 tpid)</div><div class='ctx'> 		  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M |</div><div class='ctx'> 		  ICE_AQ_VSI_OUTER_TAG_TYPE_M);</div><div class='ctx'> 	ctxt-&gt;info.outer_vlan_flags |=</div><div class='del'>-		((ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL &lt;&lt;</div><div class='del'>-		  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &amp;</div><div class='del'>-		 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M) |</div><div class='del'>-		((tag_type &lt;&lt; ICE_AQ_VSI_OUTER_TAG_TYPE_S) &amp;</div><div class='del'>-		 ICE_AQ_VSI_OUTER_TAG_TYPE_M);</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M,</div><div class='add'>+			   ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL) |</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type);</div><div class='ctx'> </div><div class='ctx'> 	err = ice_update_vsi(hw, vsi-&gt;idx, ctxt, NULL);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -642,9 +647,8 @@ int ice_vsi_dis_outer_insertion(struct ice_vsi *vsi)</div><div class='ctx'> 		  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M);</div><div class='ctx'> 	ctxt-&gt;info.outer_vlan_flags |=</div><div class='ctx'> 		ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC |</div><div class='del'>-		((ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL &lt;&lt;</div><div class='del'>-		  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &amp;</div><div class='del'>-		 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M);</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M,</div><div class='add'>+			   ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL);</div><div class='ctx'> </div><div class='ctx'> 	err = ice_update_vsi(hw, vsi-&gt;idx, ctxt, NULL);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -702,8 +706,7 @@ __ice_vsi_set_outer_port_vlan(struct ice_vsi *vsi, u16 vlan_info, u16 tpid)</div><div class='ctx'> 	ctxt-&gt;info.outer_vlan_flags =</div><div class='ctx'> 		(ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW &lt;&lt;</div><div class='ctx'> 		 ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |</div><div class='del'>-		((tag_type &lt;&lt; ICE_AQ_VSI_OUTER_TAG_TYPE_S) &amp;</div><div class='del'>-		 ICE_AQ_VSI_OUTER_TAG_TYPE_M) |</div><div class='add'>+		FIELD_PREP(ICE_AQ_VSI_OUTER_TAG_TYPE_M, tag_type) |</div><div class='ctx'> 		ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC |</div><div class='ctx'> 		(ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED &lt;&lt;</div><div class='ctx'> 		 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) |</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ice/ice_xsk.c b/drivers/net/ethernet/intel/ice/ice_xsk.c<br/>index 99954508184f..5d1ae8e4058a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_xsk.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ice/ice_xsk.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ice/ice_xsk.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ice/ice_xsk.c</a></div><div class='hunk'>@@ -458,6 +458,11 @@ static u16 ice_fill_rx_descs(struct xsk_buff_pool *pool, struct xdp_buff **xdp,</div><div class='ctx'> 		rx_desc-&gt;read.pkt_addr = cpu_to_le64(dma);</div><div class='ctx'> 		rx_desc-&gt;wb.status_error0 = 0;</div><div class='ctx'> </div><div class='add'>+		/* Put private info that changes on a per-packet basis</div><div class='add'>+		 * into xdp_buff_xsk-&gt;cb.</div><div class='add'>+		 */</div><div class='add'>+		ice_xdp_meta_set_desc(*xdp, rx_desc);</div><div class='add'>+</div><div class='ctx'> 		rx_desc++;</div><div class='ctx'> 		xdp++;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -863,8 +868,7 @@ int ice_clean_rx_irq_zc(struct ice_rx_ring *rx_ring, int budget)</div><div class='ctx'> 		struct xdp_buff *xdp;</div><div class='ctx'> 		struct sk_buff *skb;</div><div class='ctx'> 		u16 stat_err_bits;</div><div class='del'>-		u16 vlan_tag = 0;</div><div class='del'>-		u16 rx_ptype;</div><div class='add'>+		u16 vlan_tci;</div><div class='ctx'> </div><div class='ctx'> 		rx_desc = ICE_RX_DESC(rx_ring, ntc);</div><div class='ctx'> </div><div class='hunk'>@@ -942,13 +946,10 @@ construct_skb:</div><div class='ctx'> 		total_rx_bytes += skb-&gt;len;</div><div class='ctx'> 		total_rx_packets++;</div><div class='ctx'> </div><div class='del'>-		vlan_tag = ice_get_vlan_tag_from_rx_desc(rx_desc);</div><div class='del'>-</div><div class='del'>-		rx_ptype = le16_to_cpu(rx_desc-&gt;wb.ptype_flex_flags0) &amp;</div><div class='del'>-				       ICE_RX_FLEX_DESC_PTYPE_M;</div><div class='add'>+		vlan_tci = ice_get_vlan_tci(rx_desc);</div><div class='ctx'> </div><div class='del'>-		ice_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);</div><div class='del'>-		ice_receive_skb(rx_ring, skb, vlan_tag);</div><div class='add'>+		ice_process_skb_fields(rx_ring, rx_desc, skb);</div><div class='add'>+		ice_receive_skb(rx_ring, skb, vlan_tci);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rx_ring-&gt;next_to_clean = ntc;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf.h b/drivers/net/ethernet/intel/idpf/idpf.h<br/>index bee73353b56a..0acc125decb3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf.h</a></div><div class='hunk'>@@ -15,7 +15,7 @@ struct idpf_vport_max_q;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/sctp.h&gt;</div><div class='del'>-#include &lt;linux/ethtool.h&gt;</div><div class='add'>+#include &lt;linux/ethtool_netlink.h&gt;</div><div class='ctx'> #include &lt;net/gro.h&gt;</div><div class='ctx'> #include &lt;linux/dim.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -418,11 +418,13 @@ struct idpf_vport {</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * enum idpf_user_flags</div><div class='add'>+ * @__IDPF_USER_FLAG_HSPLIT: header split state</div><div class='ctx'>  * @__IDPF_PROMISC_UC: Unicast promiscuous mode</div><div class='ctx'>  * @__IDPF_PROMISC_MC: Multicast promiscuous mode</div><div class='ctx'>  * @__IDPF_USER_FLAGS_NBITS: Must be last</div><div class='ctx'>  */</div><div class='ctx'> enum idpf_user_flags {</div><div class='add'>+	__IDPF_USER_FLAG_HSPLIT = 0U,</div><div class='ctx'> 	__IDPF_PROMISC_UC = 32,</div><div class='ctx'> 	__IDPF_PROMISC_MC,</div><div class='ctx'> </div><div class='hunk'>@@ -965,4 +967,7 @@ int idpf_send_map_unmap_queue_vector_msg(struct idpf_vport *vport, bool map);</div><div class='ctx'> int idpf_send_set_sriov_vfs_msg(struct idpf_adapter *adapter, u16 num_vfs);</div><div class='ctx'> int idpf_sriov_configure(struct pci_dev *pdev, int num_vfs);</div><div class='ctx'> </div><div class='add'>+u8 idpf_vport_get_hsplit(const struct idpf_vport *vport);</div><div class='add'>+bool idpf_vport_set_hsplit(const struct idpf_vport *vport, u8 val);</div><div class='add'>+</div><div class='ctx'> #endif /* !_IDPF_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf_ethtool.c b/drivers/net/ethernet/intel/idpf/idpf_ethtool.c<br/>index 52ea38669f85..986d429d1175 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_ethtool.c</a></div><div class='hunk'>@@ -75,14 +75,12 @@ static u32 idpf_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> /**</div><div class='ctx'>  * idpf_get_rxfh - get the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function in use</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='ctx'>  *</div><div class='ctx'>  * Reads the indirection table directly from the hardware. Always returns 0.</div><div class='ctx'>  */</div><div class='del'>-static int idpf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int idpf_get_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct idpf_netdev_priv *np = netdev_priv(netdev);</div><div class='ctx'> 	struct idpf_rss_data *rss_data;</div><div class='hunk'>@@ -103,15 +101,14 @@ static int idpf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 	if (np-&gt;state != __IDPF_VPORT_UP)</div><div class='ctx'> 		goto unlock_mutex;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, rss_data-&gt;rss_key, rss_data-&gt;rss_key_size);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, rss_data-&gt;rss_key, rss_data-&gt;rss_key_size);</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; rss_data-&gt;rss_lut_size; i++)</div><div class='del'>-			indir[i] = rss_data-&gt;rss_lut[i];</div><div class='add'>+			rxfh-&gt;indir[i] = rss_data-&gt;rss_lut[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> unlock_mutex:</div><div class='hunk'>@@ -123,15 +120,15 @@ unlock_mutex:</div><div class='ctx'> /**</div><div class='ctx'>  * idpf_set_rxfh - set the rx flow hash indirection table</div><div class='ctx'>  * @netdev: network interface device structure</div><div class='del'>- * @indir: indirection table</div><div class='del'>- * @key: hash key</div><div class='del'>- * @hfunc: hash function to use</div><div class='add'>+ * @rxfh: pointer to param struct (indir, key, hfunc)</div><div class='add'>+ * @extack: extended ACK from the Netlink message</div><div class='ctx'>  *</div><div class='ctx'>  * Returns -EINVAL if the table specifies an invalid queue id, otherwise</div><div class='ctx'>  * returns 0 after programming the table.</div><div class='ctx'>  */</div><div class='del'>-static int idpf_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int idpf_set_rxfh(struct net_device *netdev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct idpf_netdev_priv *np = netdev_priv(netdev);</div><div class='ctx'> 	struct idpf_rss_data *rss_data;</div><div class='hunk'>@@ -154,17 +151,18 @@ static int idpf_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	if (np-&gt;state != __IDPF_VPORT_UP)</div><div class='ctx'> 		goto unlock_mutex;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP) {</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP) {</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='ctx'> 		goto unlock_mutex;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(rss_data-&gt;rss_key, key, rss_data-&gt;rss_key_size);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rss_data-&gt;rss_key, rxfh-&gt;key, rss_data-&gt;rss_key_size);</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (lut = 0; lut &lt; rss_data-&gt;rss_lut_size; lut++)</div><div class='del'>-			rss_data-&gt;rss_lut[lut] = indir[lut];</div><div class='add'>+			rss_data-&gt;rss_lut[lut] = rxfh-&gt;indir[lut];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = idpf_config_rss(vport);</div><div class='hunk'>@@ -320,6 +318,8 @@ static void idpf_get_ringparam(struct net_device *netdev,</div><div class='ctx'> 	ring-&gt;rx_pending = vport-&gt;rxq_desc_count;</div><div class='ctx'> 	ring-&gt;tx_pending = vport-&gt;txq_desc_count;</div><div class='ctx'> </div><div class='add'>+	kring-&gt;tcp_data_split = idpf_vport_get_hsplit(vport);</div><div class='add'>+</div><div class='ctx'> 	idpf_vport_ctrl_unlock(netdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -379,6 +379,14 @@ static int idpf_set_ringparam(struct net_device *netdev,</div><div class='ctx'> 	    new_rx_count == vport-&gt;rxq_desc_count)</div><div class='ctx'> 		goto unlock_mutex;</div><div class='ctx'> </div><div class='add'>+	if (!idpf_vport_set_hsplit(vport, kring-&gt;tcp_data_split)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(ext_ack,</div><div class='add'>+				   "setting TCP data split is not supported");</div><div class='add'>+		err = -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+		goto unlock_mutex;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	config_data = &amp;vport-&gt;adapter-&gt;vport_config[idx]-&gt;user_config;</div><div class='ctx'> 	config_data-&gt;num_req_txq_desc = new_tx_count;</div><div class='ctx'> 	config_data-&gt;num_req_rxq_desc = new_rx_count;</div><div class='hunk'>@@ -532,7 +540,7 @@ static void idpf_add_stat_strings(u8 **p, const struct idpf_stats *stats,</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; size; i++)</div><div class='del'>-		ethtool_sprintf(p, "%s", stats[i].stat_string);</div><div class='add'>+		ethtool_puts(p, stats[i].stat_string);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1334,6 +1342,7 @@ static int idpf_get_link_ksettings(struct net_device *netdev,</div><div class='ctx'> static const struct ethtool_ops idpf_ethtool_ops = {</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE,</div><div class='add'>+	.supported_ring_params	= ETHTOOL_RING_USE_TCP_DATA_SPLIT,</div><div class='ctx'> 	.get_msglevel		= idpf_get_msglevel,</div><div class='ctx'> 	.set_msglevel		= idpf_set_msglevel,</div><div class='ctx'> 	.get_link		= ethtool_op_get_link,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf_lib.c b/drivers/net/ethernet/intel/idpf/idpf_lib.c<br/>index 19809b0ddcd9..5fea2fd957eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_lib.c</a></div><div class='hunk'>@@ -1058,6 +1058,71 @@ static void idpf_vport_dealloc(struct idpf_vport *vport)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * idpf_is_hsplit_supported - check whether the header split is supported</div><div class='add'>+ * @vport: virtual port to check the capability for</div><div class='add'>+ *</div><div class='add'>+ * Return: true if it's supported by the HW/FW, false if not.</div><div class='add'>+ */</div><div class='add'>+static bool idpf_is_hsplit_supported(const struct idpf_vport *vport)</div><div class='add'>+{</div><div class='add'>+	return idpf_is_queue_model_split(vport-&gt;rxq_model) &amp;&amp;</div><div class='add'>+	       idpf_is_cap_ena_all(vport-&gt;adapter, IDPF_HSPLIT_CAPS,</div><div class='add'>+				   IDPF_CAP_HSPLIT);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * idpf_vport_get_hsplit - get the current header split feature state</div><div class='add'>+ * @vport: virtual port to query the state for</div><div class='add'>+ *</div><div class='add'>+ * Return: ``ETHTOOL_TCP_DATA_SPLIT_UNKNOWN`` if not supported,</div><div class='add'>+ *         ``ETHTOOL_TCP_DATA_SPLIT_DISABLED`` if disabled,</div><div class='add'>+ *         ``ETHTOOL_TCP_DATA_SPLIT_ENABLED`` if active.</div><div class='add'>+ */</div><div class='add'>+u8 idpf_vport_get_hsplit(const struct idpf_vport *vport)</div><div class='add'>+{</div><div class='add'>+	const struct idpf_vport_user_config_data *config;</div><div class='add'>+</div><div class='add'>+	if (!idpf_is_hsplit_supported(vport))</div><div class='add'>+		return ETHTOOL_TCP_DATA_SPLIT_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	config = &amp;vport-&gt;adapter-&gt;vport_config[vport-&gt;idx]-&gt;user_config;</div><div class='add'>+</div><div class='add'>+	return test_bit(__IDPF_USER_FLAG_HSPLIT, config-&gt;user_flags) ?</div><div class='add'>+	       ETHTOOL_TCP_DATA_SPLIT_ENABLED :</div><div class='add'>+	       ETHTOOL_TCP_DATA_SPLIT_DISABLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * idpf_vport_set_hsplit - enable or disable header split on a given vport</div><div class='add'>+ * @vport: virtual port to configure</div><div class='add'>+ * @val: Ethtool flag controlling the header split state</div><div class='add'>+ *</div><div class='add'>+ * Return: true on success, false if not supported by the HW.</div><div class='add'>+ */</div><div class='add'>+bool idpf_vport_set_hsplit(const struct idpf_vport *vport, u8 val)</div><div class='add'>+{</div><div class='add'>+	struct idpf_vport_user_config_data *config;</div><div class='add'>+</div><div class='add'>+	if (!idpf_is_hsplit_supported(vport))</div><div class='add'>+		return val == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	config = &amp;vport-&gt;adapter-&gt;vport_config[vport-&gt;idx]-&gt;user_config;</div><div class='add'>+</div><div class='add'>+	switch (val) {</div><div class='add'>+	case ETHTOOL_TCP_DATA_SPLIT_UNKNOWN:</div><div class='add'>+		/* Default is to enable */</div><div class='add'>+	case ETHTOOL_TCP_DATA_SPLIT_ENABLED:</div><div class='add'>+		__set_bit(__IDPF_USER_FLAG_HSPLIT, config-&gt;user_flags);</div><div class='add'>+		return true;</div><div class='add'>+	case ETHTOOL_TCP_DATA_SPLIT_DISABLED:</div><div class='add'>+		__clear_bit(__IDPF_USER_FLAG_HSPLIT, config-&gt;user_flags);</div><div class='add'>+		return true;</div><div class='add'>+	default:</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * idpf_vport_alloc - Allocates the next available struct vport in the adapter</div><div class='ctx'>  * @adapter: board private structure</div><div class='ctx'>  * @max_q: vport max queue info</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c b/drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c<br/>index 81288a17da2a..27b93592c4ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c</a></div><div class='hunk'>@@ -328,10 +328,9 @@ static void idpf_tx_singleq_build_ctx_desc(struct idpf_queue *txq,</div><div class='ctx'> </div><div class='ctx'> 	if (offload-&gt;tso_segs) {</div><div class='ctx'> 		qw1 |= IDPF_TX_CTX_DESC_TSO &lt;&lt; IDPF_TXD_CTX_QW1_CMD_S;</div><div class='del'>-		qw1 |= ((u64)offload-&gt;tso_len &lt;&lt; IDPF_TXD_CTX_QW1_TSO_LEN_S) &amp;</div><div class='del'>-			IDPF_TXD_CTX_QW1_TSO_LEN_M;</div><div class='del'>-		qw1 |= ((u64)offload-&gt;mss &lt;&lt; IDPF_TXD_CTX_QW1_MSS_S) &amp;</div><div class='del'>-			IDPF_TXD_CTX_QW1_MSS_M;</div><div class='add'>+		qw1 |= FIELD_PREP(IDPF_TXD_CTX_QW1_TSO_LEN_M,</div><div class='add'>+				  offload-&gt;tso_len);</div><div class='add'>+		qw1 |= FIELD_PREP(IDPF_TXD_CTX_QW1_MSS_M, offload-&gt;mss);</div><div class='ctx'> </div><div class='ctx'> 		u64_stats_update_begin(&amp;txq-&gt;stats_sync);</div><div class='ctx'> 		u64_stats_inc(&amp;txq-&gt;q_stats.tx.lso_pkts);</div><div class='hunk'>@@ -1044,7 +1043,6 @@ static int idpf_rx_singleq_clean(struct idpf_queue *rx_q, int budget)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		idpf_rx_sync_for_cpu(rx_buf, fields.size);</div><div class='del'>-		skb = rx_q-&gt;skb;</div><div class='ctx'> 		if (skb)</div><div class='ctx'> 			idpf_rx_add_frag(rx_buf, skb, fields.size);</div><div class='ctx'> 		else</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf_txrx.c b/drivers/net/ethernet/intel/idpf/idpf_txrx.c<br/>index 1f728a9004d9..2f8ad79ae3f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_txrx.c</a></div><div class='hunk'>@@ -396,7 +396,7 @@ static void idpf_rx_desc_rel(struct idpf_queue *rxq, bool bufq, s32 q_model)</div><div class='ctx'> 	if (!rxq)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	if (!bufq &amp;&amp; idpf_is_queue_model_split(q_model) &amp;&amp; rxq-&gt;skb) {</div><div class='add'>+	if (rxq-&gt;skb) {</div><div class='ctx'> 		dev_kfree_skb_any(rxq-&gt;skb);</div><div class='ctx'> 		rxq-&gt;skb = NULL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -505,9 +505,9 @@ static void idpf_rx_post_buf_refill(struct idpf_sw_queue *refillq, u16 buf_id)</div><div class='ctx'> </div><div class='ctx'> 	/* store the buffer ID and the SW maintained GEN bit to the refillq */</div><div class='ctx'> 	refillq-&gt;ring[nta] =</div><div class='del'>-		((buf_id &lt;&lt; IDPF_RX_BI_BUFID_S) &amp; IDPF_RX_BI_BUFID_M) |</div><div class='del'>-		(!!(test_bit(__IDPF_Q_GEN_CHK, refillq-&gt;flags)) &lt;&lt;</div><div class='del'>-		 IDPF_RX_BI_GEN_S);</div><div class='add'>+		FIELD_PREP(IDPF_RX_BI_BUFID_M, buf_id) |</div><div class='add'>+		FIELD_PREP(IDPF_RX_BI_GEN_M,</div><div class='add'>+			   test_bit(__IDPF_Q_GEN_CHK, refillq-&gt;flags));</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(++nta == refillq-&gt;desc_count)) {</div><div class='ctx'> 		nta = 0;</div><div class='hunk'>@@ -1240,12 +1240,15 @@ static int idpf_rxq_group_alloc(struct idpf_vport *vport, u16 num_rxq)</div><div class='ctx'> 	struct idpf_adapter *adapter = vport-&gt;adapter;</div><div class='ctx'> 	struct idpf_queue *q;</div><div class='ctx'> 	int i, k, err = 0;</div><div class='add'>+	bool hs;</div><div class='ctx'> </div><div class='ctx'> 	vport-&gt;rxq_grps = kcalloc(vport-&gt;num_rxq_grp,</div><div class='ctx'> 				  sizeof(struct idpf_rxq_group), GFP_KERNEL);</div><div class='ctx'> 	if (!vport-&gt;rxq_grps)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	hs = idpf_vport_get_hsplit(vport) == ETHTOOL_TCP_DATA_SPLIT_ENABLED;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; vport-&gt;num_rxq_grp; i++) {</div><div class='ctx'> 		struct idpf_rxq_group *rx_qgrp = &amp;vport-&gt;rxq_grps[i];</div><div class='ctx'> 		int j;</div><div class='hunk'>@@ -1298,9 +1301,8 @@ static int idpf_rxq_group_alloc(struct idpf_vport *vport, u16 num_rxq)</div><div class='ctx'> 			q-&gt;rx_buf_size = vport-&gt;bufq_size[j];</div><div class='ctx'> 			q-&gt;rx_buffer_low_watermark = IDPF_LOW_WATERMARK;</div><div class='ctx'> 			q-&gt;rx_buf_stride = IDPF_RX_BUF_STRIDE;</div><div class='del'>-			if (idpf_is_cap_ena_all(adapter, IDPF_HSPLIT_CAPS,</div><div class='del'>-						IDPF_CAP_HSPLIT) &amp;&amp;</div><div class='del'>-			    idpf_is_queue_model_split(vport-&gt;rxq_model)) {</div><div class='add'>+</div><div class='add'>+			if (hs) {</div><div class='ctx'> 				q-&gt;rx_hsplit_en = true;</div><div class='ctx'> 				q-&gt;rx_hbuf_size = IDPF_HDR_BUF_SIZE;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1344,9 +1346,7 @@ skip_splitq_rx_init:</div><div class='ctx'> 				rx_qgrp-&gt;splitq.rxq_sets[j]-&gt;refillq1 =</div><div class='ctx'> 				      &amp;rx_qgrp-&gt;splitq.bufq_sets[1].refillqs[j];</div><div class='ctx'> </div><div class='del'>-			if (idpf_is_cap_ena_all(adapter, IDPF_HSPLIT_CAPS,</div><div class='del'>-						IDPF_CAP_HSPLIT) &amp;&amp;</div><div class='del'>-			    idpf_is_queue_model_split(vport-&gt;rxq_model)) {</div><div class='add'>+			if (hs) {</div><div class='ctx'> 				q-&gt;rx_hsplit_en = true;</div><div class='ctx'> 				q-&gt;rx_hbuf_size = IDPF_HDR_BUF_SIZE;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -1825,14 +1825,14 @@ static bool idpf_tx_clean_complq(struct idpf_queue *complq, int budget,</div><div class='ctx'> 		u16 gen;</div><div class='ctx'> </div><div class='ctx'> 		/* if the descriptor isn't done, no work yet to do */</div><div class='del'>-		gen = (le16_to_cpu(tx_desc-&gt;qid_comptype_gen) &amp;</div><div class='del'>-		      IDPF_TXD_COMPLQ_GEN_M) &gt;&gt; IDPF_TXD_COMPLQ_GEN_S;</div><div class='add'>+		gen = le16_get_bits(tx_desc-&gt;qid_comptype_gen,</div><div class='add'>+				    IDPF_TXD_COMPLQ_GEN_M);</div><div class='ctx'> 		if (test_bit(__IDPF_Q_GEN_CHK, complq-&gt;flags) != gen)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		/* Find necessary info of TX queue to clean buffers */</div><div class='del'>-		rel_tx_qid = (le16_to_cpu(tx_desc-&gt;qid_comptype_gen) &amp;</div><div class='del'>-			 IDPF_TXD_COMPLQ_QID_M) &gt;&gt; IDPF_TXD_COMPLQ_QID_S;</div><div class='add'>+		rel_tx_qid = le16_get_bits(tx_desc-&gt;qid_comptype_gen,</div><div class='add'>+					   IDPF_TXD_COMPLQ_QID_M);</div><div class='ctx'> 		if (rel_tx_qid &gt;= complq-&gt;txq_grp-&gt;num_txq ||</div><div class='ctx'> 		    !complq-&gt;txq_grp-&gt;txqs[rel_tx_qid]) {</div><div class='ctx'> 			dev_err(&amp;complq-&gt;vport-&gt;adapter-&gt;pdev-&gt;dev,</div><div class='hunk'>@@ -1842,9 +1842,8 @@ static bool idpf_tx_clean_complq(struct idpf_queue *complq, int budget,</div><div class='ctx'> 		tx_q = complq-&gt;txq_grp-&gt;txqs[rel_tx_qid];</div><div class='ctx'> </div><div class='ctx'> 		/* Determine completion type */</div><div class='del'>-		ctype = (le16_to_cpu(tx_desc-&gt;qid_comptype_gen) &amp;</div><div class='del'>-			IDPF_TXD_COMPLQ_COMPL_TYPE_M) &gt;&gt;</div><div class='del'>-			IDPF_TXD_COMPLQ_COMPL_TYPE_S;</div><div class='add'>+		ctype = le16_get_bits(tx_desc-&gt;qid_comptype_gen,</div><div class='add'>+				      IDPF_TXD_COMPLQ_COMPL_TYPE_M);</div><div class='ctx'> 		switch (ctype) {</div><div class='ctx'> 		case IDPF_TXD_COMPLT_RE:</div><div class='ctx'> 			hw_head = le16_to_cpu(tx_desc-&gt;q_head_compl_tag.q_head);</div><div class='hunk'>@@ -1945,11 +1944,10 @@ void idpf_tx_splitq_build_ctb(union idpf_tx_flex_desc *desc,</div><div class='ctx'> 			      u16 td_cmd, u16 size)</div><div class='ctx'> {</div><div class='ctx'> 	desc-&gt;q.qw1.cmd_dtype =</div><div class='del'>-		cpu_to_le16(params-&gt;dtype &amp; IDPF_FLEX_TXD_QW1_DTYPE_M);</div><div class='add'>+		le16_encode_bits(params-&gt;dtype, IDPF_FLEX_TXD_QW1_DTYPE_M);</div><div class='ctx'> 	desc-&gt;q.qw1.cmd_dtype |=</div><div class='del'>-		cpu_to_le16((td_cmd &lt;&lt; IDPF_FLEX_TXD_QW1_CMD_S) &amp;</div><div class='del'>-			    IDPF_FLEX_TXD_QW1_CMD_M);</div><div class='del'>-	desc-&gt;q.qw1.buf_size = cpu_to_le16((u16)size);</div><div class='add'>+		le16_encode_bits(td_cmd, IDPF_FLEX_TXD_QW1_CMD_M);</div><div class='add'>+	desc-&gt;q.qw1.buf_size = cpu_to_le16(size);</div><div class='ctx'> 	desc-&gt;q.qw1.l2tags.l2tag1 = cpu_to_le16(params-&gt;td_tag);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2843,8 +2841,9 @@ static void idpf_rx_splitq_extract_csum_bits(struct virtchnl2_rx_flex_desc_adv_n</div><div class='ctx'> 				qword1);</div><div class='ctx'> 	csum-&gt;ipv6exadd = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_M,</div><div class='ctx'> 				    qword0);</div><div class='del'>-	csum-&gt;raw_csum_inv = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M,</div><div class='del'>-				       le16_to_cpu(rx_desc-&gt;ptype_err_fflags0));</div><div class='add'>+	csum-&gt;raw_csum_inv =</div><div class='add'>+		le16_get_bits(rx_desc-&gt;ptype_err_fflags0,</div><div class='add'>+			      VIRTCHNL2_RX_FLEX_DESC_ADV_RAW_CSUM_INV_M);</div><div class='ctx'> 	csum-&gt;raw_csum = le16_to_cpu(rx_desc-&gt;misc.raw_cs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2938,8 +2937,8 @@ static int idpf_rx_process_skb_fields(struct idpf_queue *rxq,</div><div class='ctx'> 	struct idpf_rx_ptype_decoded decoded;</div><div class='ctx'> 	u16 rx_ptype;</div><div class='ctx'> </div><div class='del'>-	rx_ptype = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M,</div><div class='del'>-			     le16_to_cpu(rx_desc-&gt;ptype_err_fflags0));</div><div class='add'>+	rx_ptype = le16_get_bits(rx_desc-&gt;ptype_err_fflags0,</div><div class='add'>+				 VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M);</div><div class='ctx'> </div><div class='ctx'> 	decoded = rxq-&gt;vport-&gt;rx_ptype_lkup[rx_ptype];</div><div class='ctx'> 	/* If we don't know the ptype we can't do anything else with it. Just</div><div class='hunk'>@@ -2953,8 +2952,8 @@ static int idpf_rx_process_skb_fields(struct idpf_queue *rxq,</div><div class='ctx'> </div><div class='ctx'> 	skb-&gt;protocol = eth_type_trans(skb, rxq-&gt;vport-&gt;netdev);</div><div class='ctx'> </div><div class='del'>-	if (FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M,</div><div class='del'>-		      le16_to_cpu(rx_desc-&gt;hdrlen_flags)))</div><div class='add'>+	if (le16_get_bits(rx_desc-&gt;hdrlen_flags,</div><div class='add'>+			  VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M))</div><div class='ctx'> 		return idpf_rx_rsc(rxq, skb, rx_desc, &amp;decoded);</div><div class='ctx'> </div><div class='ctx'> 	idpf_rx_splitq_extract_csum_bits(rx_desc, &amp;csum_bits);</div><div class='hunk'>@@ -3148,8 +3147,8 @@ static int idpf_rx_splitq_clean(struct idpf_queue *rxq, int budget)</div><div class='ctx'> 		dma_rmb();</div><div class='ctx'> </div><div class='ctx'> 		/* if the descriptor isn't done, no work yet to do */</div><div class='del'>-		gen_id = le16_to_cpu(rx_desc-&gt;pktlen_gen_bufq_id);</div><div class='del'>-		gen_id = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M, gen_id);</div><div class='add'>+		gen_id = le16_get_bits(rx_desc-&gt;pktlen_gen_bufq_id,</div><div class='add'>+				       VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M);</div><div class='ctx'> </div><div class='ctx'> 		if (test_bit(__IDPF_Q_GEN_CHK, rxq-&gt;flags) != gen_id)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -3164,9 +3163,8 @@ static int idpf_rx_splitq_clean(struct idpf_queue *rxq, int budget)</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		pkt_len = le16_to_cpu(rx_desc-&gt;pktlen_gen_bufq_id);</div><div class='del'>-		pkt_len = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M,</div><div class='del'>-				    pkt_len);</div><div class='add'>+		pkt_len = le16_get_bits(rx_desc-&gt;pktlen_gen_bufq_id,</div><div class='add'>+					VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M);</div><div class='ctx'> </div><div class='ctx'> 		hbo = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_HBO_M,</div><div class='ctx'> 				rx_desc-&gt;status_err0_qw1);</div><div class='hunk'>@@ -3183,14 +3181,12 @@ static int idpf_rx_splitq_clean(struct idpf_queue *rxq, int budget)</div><div class='ctx'> 			goto bypass_hsplit;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		hdr_len = le16_to_cpu(rx_desc-&gt;hdrlen_flags);</div><div class='del'>-		hdr_len = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M,</div><div class='del'>-				    hdr_len);</div><div class='add'>+		hdr_len = le16_get_bits(rx_desc-&gt;hdrlen_flags,</div><div class='add'>+					VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M);</div><div class='ctx'> </div><div class='ctx'> bypass_hsplit:</div><div class='del'>-		bufq_id = le16_to_cpu(rx_desc-&gt;pktlen_gen_bufq_id);</div><div class='del'>-		bufq_id = FIELD_GET(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M,</div><div class='del'>-				    bufq_id);</div><div class='add'>+		bufq_id = le16_get_bits(rx_desc-&gt;pktlen_gen_bufq_id,</div><div class='add'>+					VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M);</div><div class='ctx'> </div><div class='ctx'> 		rxq_set = container_of(rxq, struct idpf_rxq_set, rxq);</div><div class='ctx'> 		if (!bufq_id)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/idpf_virtchnl.c b/drivers/net/ethernet/intel/idpf/idpf_virtchnl.c<br/>index 2c1b051fdc0d..d0cdd63b3d5b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_virtchnl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/idpf_virtchnl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/idpf_virtchnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/idpf_virtchnl.c</a></div><div class='hunk'>@@ -3285,6 +3285,8 @@ void idpf_vport_init(struct idpf_vport *vport, struct idpf_vport_max_q *max_q)</div><div class='ctx'> 	memcpy(vport-&gt;rx_itr_profile, rx_itr, IDPF_DIM_PROFILE_SLOTS);</div><div class='ctx'> 	memcpy(vport-&gt;tx_itr_profile, tx_itr, IDPF_DIM_PROFILE_SLOTS);</div><div class='ctx'> </div><div class='add'>+	idpf_vport_set_hsplit(vport, ETHTOOL_TCP_DATA_SPLIT_ENABLED);</div><div class='add'>+</div><div class='ctx'> 	idpf_vport_init_num_qs(vport, vport_msg);</div><div class='ctx'> 	idpf_vport_calc_num_q_desc(vport);</div><div class='ctx'> 	idpf_vport_calc_num_q_groups(vport);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/idpf/virtchnl2.h b/drivers/net/ethernet/intel/idpf/virtchnl2.h<br/>index 07e72c72d156..8dc837889723 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/virtchnl2.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/idpf/virtchnl2.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/idpf/virtchnl2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/idpf/virtchnl2.h</a></div><div class='hunk'>@@ -1104,9 +1104,9 @@ struct virtchnl2_rss_key {</div><div class='ctx'> 	__le32 vport_id;</div><div class='ctx'> 	__le16 key_len;</div><div class='ctx'> 	u8 pad;</div><div class='del'>-	__DECLARE_FLEX_ARRAY(u8, key_flex);</div><div class='del'>-};</div><div class='del'>-VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_rss_key);</div><div class='add'>+	u8 key_flex[];</div><div class='add'>+} __packed;</div><div class='add'>+VIRTCHNL2_CHECK_STRUCT_LEN(7, virtchnl2_rss_key);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='ctx'>  * struct virtchnl2_queue_chunk - chunk of contiguous queues</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c<br/>index 8d6e44ee1895..64dfc362d1dc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_82575.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/e1000_82575.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_82575.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_82575.c</a></div><div class='hunk'>@@ -222,8 +222,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* set lan id */</div><div class='del'>-	hw-&gt;bus.func = (rd32(E1000_STATUS) &amp; E1000_STATUS_FUNC_MASK) &gt;&gt;</div><div class='del'>-			E1000_STATUS_FUNC_SHIFT;</div><div class='add'>+	hw-&gt;bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS));</div><div class='ctx'> </div><div class='ctx'> 	/* Set phy-&gt;phy_addr and phy-&gt;id. */</div><div class='ctx'> 	ret_val = igb_get_phy_id_82575(hw);</div><div class='hunk'>@@ -262,8 +261,8 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)</div><div class='ctx'> 			if (ret_val)</div><div class='ctx'> 				goto out;</div><div class='ctx'> </div><div class='del'>-			data = (data &amp; E1000_M88E1112_MAC_CTRL_1_MODE_MASK) &gt;&gt;</div><div class='del'>-			       E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;</div><div class='add'>+			data = FIELD_GET(E1000_M88E1112_MAC_CTRL_1_MODE_MASK,</div><div class='add'>+					 data);</div><div class='ctx'> 			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||</div><div class='ctx'> 			    data == E1000_M88E1112_AUTO_COPPER_BASEX)</div><div class='ctx'> 				hw-&gt;mac.ops.check_for_link =</div><div class='hunk'>@@ -330,8 +329,7 @@ static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)</div><div class='ctx'> 	u32 eecd = rd32(E1000_EECD);</div><div class='ctx'> 	u16 size;</div><div class='ctx'> </div><div class='del'>-	size = (u16)((eecd &amp; E1000_EECD_SIZE_EX_MASK) &gt;&gt;</div><div class='del'>-		     E1000_EECD_SIZE_EX_SHIFT);</div><div class='add'>+	size = FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);</div><div class='ctx'> </div><div class='ctx'> 	/* Added to a constant, "size" becomes the left-shift value</div><div class='ctx'> 	 * for setting word_size.</div><div class='hunk'>@@ -2798,7 +2796,7 @@ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;nvm.ops.read(hw, ets_offset, 1, &amp;ets_cfg);</div><div class='del'>-	if (((ets_cfg &amp; NVM_ETS_TYPE_MASK) &gt;&gt; NVM_ETS_TYPE_SHIFT)</div><div class='add'>+	if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)</div><div class='ctx'> 	    != NVM_ETS_TYPE_EMC)</div><div class='ctx'> 		return E1000_NOT_IMPLEMENTED;</div><div class='ctx'> </div><div class='hunk'>@@ -2808,10 +2806,8 @@ static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt; num_sensors; i++) {</div><div class='ctx'> 		hw-&gt;nvm.ops.read(hw, (ets_offset + i), 1, &amp;ets_sensor);</div><div class='del'>-		sensor_index = ((ets_sensor &amp; NVM_ETS_DATA_INDEX_MASK) &gt;&gt;</div><div class='del'>-				NVM_ETS_DATA_INDEX_SHIFT);</div><div class='del'>-		sensor_location = ((ets_sensor &amp; NVM_ETS_DATA_LOC_MASK) &gt;&gt;</div><div class='del'>-				   NVM_ETS_DATA_LOC_SHIFT);</div><div class='add'>+		sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);</div><div class='add'>+		sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);</div><div class='ctx'> </div><div class='ctx'> 		if (sensor_location != 0)</div><div class='ctx'> 			hw-&gt;phy.ops.read_i2c_byte(hw,</div><div class='hunk'>@@ -2859,20 +2855,17 @@ static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;nvm.ops.read(hw, ets_offset, 1, &amp;ets_cfg);</div><div class='del'>-	if (((ets_cfg &amp; NVM_ETS_TYPE_MASK) &gt;&gt; NVM_ETS_TYPE_SHIFT)</div><div class='add'>+	if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)</div><div class='ctx'> 	    != NVM_ETS_TYPE_EMC)</div><div class='ctx'> 		return E1000_NOT_IMPLEMENTED;</div><div class='ctx'> </div><div class='del'>-	low_thresh_delta = ((ets_cfg &amp; NVM_ETS_LTHRES_DELTA_MASK) &gt;&gt;</div><div class='del'>-			    NVM_ETS_LTHRES_DELTA_SHIFT);</div><div class='add'>+	low_thresh_delta = FIELD_GET(NVM_ETS_LTHRES_DELTA_MASK, ets_cfg);</div><div class='ctx'> 	num_sensors = (ets_cfg &amp; NVM_ETS_NUM_SENSORS_MASK);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 1; i &lt;= num_sensors; i++) {</div><div class='ctx'> 		hw-&gt;nvm.ops.read(hw, (ets_offset + i), 1, &amp;ets_sensor);</div><div class='del'>-		sensor_index = ((ets_sensor &amp; NVM_ETS_DATA_INDEX_MASK) &gt;&gt;</div><div class='del'>-				NVM_ETS_DATA_INDEX_SHIFT);</div><div class='del'>-		sensor_location = ((ets_sensor &amp; NVM_ETS_DATA_LOC_MASK) &gt;&gt;</div><div class='del'>-				   NVM_ETS_DATA_LOC_SHIFT);</div><div class='add'>+		sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);</div><div class='add'>+		sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);</div><div class='ctx'> 		therm_limit = ets_sensor &amp; NVM_ETS_DATA_HTHRESH_MASK;</div><div class='ctx'> </div><div class='ctx'> 		hw-&gt;phy.ops.write_i2c_byte(hw,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c<br/>index b9b9d35494d2..503b239868e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_i210.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/e1000_i210.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_i210.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_i210.c</a></div><div class='hunk'>@@ -5,9 +5,9 @@</div><div class='ctx'>  * e1000_i211</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/if_ether.h&gt;</div><div class='del'>-</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='ctx'> #include "e1000_hw.h"</div><div class='ctx'> #include "e1000_i210.h"</div><div class='ctx'> </div><div class='hunk'>@@ -473,7 +473,7 @@ s32 igb_read_invm_version(struct e1000_hw *hw,</div><div class='ctx'> 		/* Check if we have second version location used */</div><div class='ctx'> 		else if ((i == 1) &amp;&amp;</div><div class='ctx'> 			 ((*record &amp; E1000_INVM_VER_FIELD_TWO) == 0)) {</div><div class='del'>-			version = (*record &amp; E1000_INVM_VER_FIELD_ONE) &gt;&gt; 3;</div><div class='add'>+			version = FIELD_GET(E1000_INVM_VER_FIELD_ONE, *record);</div><div class='ctx'> 			status = 0;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -483,8 +483,8 @@ s32 igb_read_invm_version(struct e1000_hw *hw,</div><div class='ctx'> 		else if ((((*record &amp; E1000_INVM_VER_FIELD_ONE) == 0) &amp;&amp;</div><div class='ctx'> 			 ((*record &amp; 0x3) == 0)) || (((*record &amp; 0x3) != 0) &amp;&amp;</div><div class='ctx'> 			 (i != 1))) {</div><div class='del'>-			version = (*next_record &amp; E1000_INVM_VER_FIELD_TWO)</div><div class='del'>-				  &gt;&gt; 13;</div><div class='add'>+			version = FIELD_GET(E1000_INVM_VER_FIELD_TWO,</div><div class='add'>+					    *next_record);</div><div class='ctx'> 			status = 0;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -493,15 +493,15 @@ s32 igb_read_invm_version(struct e1000_hw *hw,</div><div class='ctx'> 		 */</div><div class='ctx'> 		else if (((*record &amp; E1000_INVM_VER_FIELD_TWO) == 0) &amp;&amp;</div><div class='ctx'> 			 ((*record &amp; 0x3) == 0)) {</div><div class='del'>-			version = (*record &amp; E1000_INVM_VER_FIELD_ONE) &gt;&gt; 3;</div><div class='add'>+			version = FIELD_GET(E1000_INVM_VER_FIELD_ONE, *record);</div><div class='ctx'> 			status = 0;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!status) {</div><div class='del'>-		invm_ver-&gt;invm_major = (version &amp; E1000_INVM_MAJOR_MASK)</div><div class='del'>-					&gt;&gt; E1000_INVM_MAJOR_SHIFT;</div><div class='add'>+		invm_ver-&gt;invm_major = FIELD_GET(E1000_INVM_MAJOR_MASK,</div><div class='add'>+						 version);</div><div class='ctx'> 		invm_ver-&gt;invm_minor = version &amp; E1000_INVM_MINOR_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Read Image Type */</div><div class='hunk'>@@ -520,7 +520,8 @@ s32 igb_read_invm_version(struct e1000_hw *hw,</div><div class='ctx'> 			 ((*record &amp; E1000_INVM_IMGTYPE_FIELD) == 0)) ||</div><div class='ctx'> 			 ((((*record &amp; 0x3) != 0) &amp;&amp; (i != 1)))) {</div><div class='ctx'> 			invm_ver-&gt;invm_img_type =</div><div class='del'>-				(*next_record &amp; E1000_INVM_IMGTYPE_FIELD) &gt;&gt; 23;</div><div class='add'>+				FIELD_GET(E1000_INVM_IMGTYPE_FIELD,</div><div class='add'>+					  *next_record);</div><div class='ctx'> 			status = 0;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c<br/>index caf91c6f52b4..fa3dfafd2bb1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/e1000_mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_mac.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2007 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/if_ether.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='hunk'>@@ -50,13 +51,12 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		bus-&gt;width = (enum e1000_bus_width)((pcie_link_status &amp;</div><div class='del'>-						     PCI_EXP_LNKSTA_NLW) &gt;&gt;</div><div class='del'>-						     PCI_EXP_LNKSTA_NLW_SHIFT);</div><div class='add'>+		bus-&gt;width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,</div><div class='add'>+							     pcie_link_status);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	reg = rd32(E1000_STATUS);</div><div class='del'>-	bus-&gt;func = (reg &amp; E1000_STATUS_FUNC_MASK) &gt;&gt; E1000_STATUS_FUNC_SHIFT;</div><div class='add'>+	bus-&gt;func = FIELD_GET(E1000_STATUS_FUNC_MASK, reg);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/e1000_nvm.c b/drivers/net/ethernet/intel/igb/e1000_nvm.c<br/>index fa136e6e9328..2dcd64d6dec3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_nvm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/e1000_nvm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_nvm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_nvm.c</a></div><div class='hunk'>@@ -1,9 +1,9 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2007 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/if_ether.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='del'>-</div><div class='add'>+#include &lt;linux/if_ether.h&gt;</div><div class='ctx'> #include "e1000_mac.h"</div><div class='ctx'> #include "e1000_nvm.h"</div><div class='ctx'> </div><div class='hunk'>@@ -708,10 +708,10 @@ void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if ((etrack_test &amp;  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {</div><div class='ctx'> 			hw-&gt;nvm.ops.read(hw, NVM_VERSION, 1, &amp;fw_version);</div><div class='del'>-			fw_vers-&gt;eep_major = (fw_version &amp; NVM_MAJOR_MASK)</div><div class='del'>-					      &gt;&gt; NVM_MAJOR_SHIFT;</div><div class='del'>-			fw_vers-&gt;eep_minor = (fw_version &amp; NVM_MINOR_MASK)</div><div class='del'>-					      &gt;&gt; NVM_MINOR_SHIFT;</div><div class='add'>+			fw_vers-&gt;eep_major = FIELD_GET(NVM_MAJOR_MASK,</div><div class='add'>+						       fw_version);</div><div class='add'>+			fw_vers-&gt;eep_minor = FIELD_GET(NVM_MINOR_MASK,</div><div class='add'>+						       fw_version);</div><div class='ctx'> 			fw_vers-&gt;eep_build = (fw_version &amp; NVM_IMAGE_ID_MASK);</div><div class='ctx'> 			goto etrack_id;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -753,15 +753,13 @@ void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> 	hw-&gt;nvm.ops.read(hw, NVM_VERSION, 1, &amp;fw_version);</div><div class='del'>-	fw_vers-&gt;eep_major = (fw_version &amp; NVM_MAJOR_MASK)</div><div class='del'>-			      &gt;&gt; NVM_MAJOR_SHIFT;</div><div class='add'>+	fw_vers-&gt;eep_major = FIELD_GET(NVM_MAJOR_MASK, fw_version);</div><div class='ctx'> </div><div class='ctx'> 	/* check for old style version format in newer images*/</div><div class='ctx'> 	if ((fw_version &amp; NVM_NEW_DEC_MASK) == 0x0) {</div><div class='ctx'> 		eeprom_verl = (fw_version &amp; NVM_COMB_VER_MASK);</div><div class='ctx'> 	} else {</div><div class='del'>-		eeprom_verl = (fw_version &amp; NVM_MINOR_MASK)</div><div class='del'>-				&gt;&gt; NVM_MINOR_SHIFT;</div><div class='add'>+		eeprom_verl = FIELD_GET(NVM_MINOR_MASK, fw_version);</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Convert minor value to hex before assigning to output struct</div><div class='ctx'> 	 * Val to be converted will not be higher than 99, per tool output</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c<br/>index a018000f7db9..cd65008c7ef5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/e1000_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/e1000_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/e1000_phy.c</a></div><div class='hunk'>@@ -1,9 +1,9 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2007 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/if_ether.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='del'>-</div><div class='add'>+#include &lt;linux/if_ether.h&gt;</div><div class='ctx'> #include "e1000_mac.h"</div><div class='ctx'> #include "e1000_phy.h"</div><div class='ctx'> </div><div class='hunk'>@@ -255,7 +255,7 @@ s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Need to byte-swap the 16-bit value. */</div><div class='del'>-	*data = ((i2ccmd &gt;&gt; 8) &amp; 0x00FF) | ((i2ccmd &lt;&lt; 8) &amp; 0xFF00);</div><div class='add'>+	*data = ((i2ccmd &gt;&gt; 8) &amp; 0x00FF) | FIELD_PREP(0xFF00, i2ccmd);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -282,7 +282,7 @@ s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Swap the data bytes for the I2C interface */</div><div class='del'>-	phy_data_swapped = ((data &gt;&gt; 8) &amp; 0x00FF) | ((data &lt;&lt; 8) &amp; 0xFF00);</div><div class='add'>+	phy_data_swapped = ((data &gt;&gt; 8) &amp; 0x00FF) | FIELD_PREP(0xFF00, data);</div><div class='ctx'> </div><div class='ctx'> 	/* Set up Op-code, Phy Address, and register address in the I2CCMD</div><div class='ctx'> 	 * register.  The MAC will take care of interfacing with the</div><div class='hunk'>@@ -1682,8 +1682,7 @@ s32 igb_get_cable_length_m88(struct e1000_hw *hw)</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	index = (phy_data &amp; M88E1000_PSSR_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-		M88E1000_PSSR_CABLE_LENGTH_SHIFT;</div><div class='add'>+	index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);</div><div class='ctx'> 	if (index &gt;= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {</div><div class='ctx'> 		ret_val = -E1000_ERR_PHY;</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -1796,8 +1795,7 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			goto out;</div><div class='ctx'> </div><div class='del'>-		index = (phy_data &amp; M88E1000_PSSR_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-			M88E1000_PSSR_CABLE_LENGTH_SHIFT;</div><div class='add'>+		index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);</div><div class='ctx'> 		if (index &gt;= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {</div><div class='ctx'> 			ret_val = -E1000_ERR_PHY;</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -2578,8 +2576,7 @@ s32 igb_get_cable_length_82580(struct e1000_hw *hw)</div><div class='ctx'> 	if (ret_val)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	length = (phy_data &amp; I82580_DSTATUS_CABLE_LENGTH) &gt;&gt;</div><div class='del'>-		 I82580_DSTATUS_CABLE_LENGTH_SHIFT;</div><div class='add'>+	length = FIELD_GET(I82580_DSTATUS_CABLE_LENGTH, phy_data);</div><div class='ctx'> </div><div class='ctx'> 	if (length == E1000_CABLE_LENGTH_UNDEFINED)</div><div class='ctx'> 		ret_val = -E1000_ERR_PHY;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c<br/>index 16d2a55d5e17..b66199c9bb3a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/igb_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/igb_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/igb_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/igb_ethtool.c</a></div><div class='hunk'>@@ -2356,11 +2356,9 @@ static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; IGB_GLOBAL_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					igb_gstrings_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, igb_gstrings_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; IGB_NETDEV_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					igb_gstrings_net_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, igb_gstrings_net_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; adapter-&gt;num_tx_queues; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_packets", i);</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_bytes", i);</div><div class='hunk'>@@ -2434,7 +2432,7 @@ static int igb_get_ts_info(struct net_device *dev,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#define ETHER_TYPE_FULL_MASK ((__force __be16)~0)</div><div class='add'>+#define ETHER_TYPE_FULL_MASK cpu_to_be16(FIELD_MAX(U16_MAX))</div><div class='ctx'> static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,</div><div class='ctx'> 				     struct ethtool_rxnfc *cmd)</div><div class='ctx'> {</div><div class='hunk'>@@ -2713,8 +2711,7 @@ static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,</div><div class='ctx'> 	etqf |= (etype &amp; E1000_ETQF_ETYPE_MASK);</div><div class='ctx'> </div><div class='ctx'> 	etqf &amp;= ~E1000_ETQF_QUEUE_MASK;</div><div class='del'>-	etqf |= ((input-&gt;action &lt;&lt; E1000_ETQF_QUEUE_SHIFT)</div><div class='del'>-		&amp; E1000_ETQF_QUEUE_MASK);</div><div class='add'>+	etqf |= FIELD_PREP(E1000_ETQF_QUEUE_MASK, input-&gt;action);</div><div class='ctx'> 	etqf |= E1000_ETQF_QUEUE_ENABLE;</div><div class='ctx'> </div><div class='ctx'> 	wr32(E1000_ETQF(i), etqf);</div><div class='hunk'>@@ -2733,8 +2730,8 @@ static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,</div><div class='ctx'> 	u32 vlapqf;</div><div class='ctx'> </div><div class='ctx'> 	vlapqf = rd32(E1000_VLAPQF);</div><div class='del'>-	vlan_priority = (ntohs(input-&gt;filter.vlan_tci) &amp; VLAN_PRIO_MASK)</div><div class='del'>-				&gt;&gt; VLAN_PRIO_SHIFT;</div><div class='add'>+	vlan_priority = FIELD_GET(VLAN_PRIO_MASK,</div><div class='add'>+				  ntohs(input-&gt;filter.vlan_tci));</div><div class='ctx'> 	queue_index = (vlapqf &gt;&gt; (vlan_priority * 4)) &amp; E1000_VLAPQF_QUEUE_MASK;</div><div class='ctx'> </div><div class='ctx'> 	/* check whether this vlan prio is already set */</div><div class='hunk'>@@ -2817,7 +2814,7 @@ static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,</div><div class='ctx'> 	u8 vlan_priority;</div><div class='ctx'> 	u32 vlapqf;</div><div class='ctx'> </div><div class='del'>-	vlan_priority = (vlan_tci &amp; VLAN_PRIO_MASK) &gt;&gt; VLAN_PRIO_SHIFT;</div><div class='add'>+	vlan_priority = FIELD_GET(VLAN_PRIO_MASK, vlan_tci);</div><div class='ctx'> </div><div class='ctx'> 	vlapqf = rd32(E1000_VLAPQF);</div><div class='ctx'> 	vlapqf &amp;= ~E1000_VLAPQF_P_VALID(vlan_priority);</div><div class='hunk'>@@ -3282,18 +3279,17 @@ static u32 igb_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return IGB_RETA_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			u8 *hfunc)</div><div class='add'>+static int igb_get_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct igb_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	for (i = 0; i &lt; IGB_RETA_SIZE; i++)</div><div class='del'>-		indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='add'>+		rxfh-&gt;indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3333,8 +3329,9 @@ void igb_write_rss_indir_tbl(struct igb_adapter *adapter)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			const u8 *key, const u8 hfunc)</div><div class='add'>+static int igb_set_rxfh(struct net_device *netdev,</div><div class='add'>+			struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct igb_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	struct e1000_hw *hw = &amp;adapter-&gt;hw;</div><div class='hunk'>@@ -3342,10 +3339,11 @@ static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> 	u32 num_queues;</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	num_queues = adapter-&gt;rss_queues;</div><div class='hunk'>@@ -3362,12 +3360,12 @@ static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> </div><div class='ctx'> 	/* Verify user input. */</div><div class='ctx'> 	for (i = 0; i &lt; IGB_RETA_SIZE; i++)</div><div class='del'>-		if (indir[i] &gt;= num_queues)</div><div class='add'>+		if (rxfh-&gt;indir[i] &gt;= num_queues)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IGB_RETA_SIZE; i++)</div><div class='del'>-		adapter-&gt;rss_indir_tbl[i] = indir[i];</div><div class='add'>+		adapter-&gt;rss_indir_tbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 	igb_write_rss_indir_tbl(adapter);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c<br/>index b2295caa2f0a..4df8d4153aa5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/igb_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igb/igb_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igb/igb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igb/igb_main.c</a></div><div class='hunk'>@@ -7295,7 +7295,7 @@ static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)</div><div class='ctx'> static int igb_set_vf_multicasts(struct igb_adapter *adapter,</div><div class='ctx'> 				  u32 *msgbuf, u32 vf)</div><div class='ctx'> {</div><div class='del'>-	int n = (msgbuf[0] &amp; E1000_VT_MSGINFO_MASK) &gt;&gt; E1000_VT_MSGINFO_SHIFT;</div><div class='add'>+	int n = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);</div><div class='ctx'> 	u16 *hash_list = (u16 *)&amp;msgbuf[1];</div><div class='ctx'> 	struct vf_data_storage *vf_data = &amp;adapter-&gt;vf_data[vf];</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -7555,7 +7555,7 @@ static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,</div><div class='ctx'> </div><div class='ctx'> static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)</div><div class='ctx'> {</div><div class='del'>-	int add = (msgbuf[0] &amp; E1000_VT_MSGINFO_MASK) &gt;&gt; E1000_VT_MSGINFO_SHIFT;</div><div class='add'>+	int add = FIELD_GET(E1000_VT_MSGINFO_MASK, msgbuf[0]);</div><div class='ctx'> 	int vid = (msgbuf[1] &amp; E1000_VLVF_VLANID_MASK);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -9810,8 +9810,7 @@ static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,</div><div class='ctx'> 			 tx_rate;</div><div class='ctx'> </div><div class='ctx'> 		bcnrc_val = E1000_RTTBCNRC_RS_ENA;</div><div class='del'>-		bcnrc_val |= ((rf_int &lt;&lt; E1000_RTTBCNRC_RF_INT_SHIFT) &amp;</div><div class='del'>-			      E1000_RTTBCNRC_RF_INT_MASK);</div><div class='add'>+		bcnrc_val |= FIELD_PREP(E1000_RTTBCNRC_RF_INT_MASK, rf_int);</div><div class='ctx'> 		bcnrc_val |= (rf_dec &amp; E1000_RTTBCNRC_RF_DEC_MASK);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		bcnrc_val = 0;</div><div class='hunk'>@@ -10000,8 +9999,7 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)</div><div class='ctx'> 			hwm = 64 * (pba - 6);</div><div class='ctx'> 			reg = rd32(E1000_FCRTC);</div><div class='ctx'> 			reg &amp;= ~E1000_FCRTC_RTH_COAL_MASK;</div><div class='del'>-			reg |= ((hwm &lt;&lt; E1000_FCRTC_RTH_COAL_SHIFT)</div><div class='del'>-				&amp; E1000_FCRTC_RTH_COAL_MASK);</div><div class='add'>+			reg |= FIELD_PREP(E1000_FCRTC_RTH_COAL_MASK, hwm);</div><div class='ctx'> 			wr32(E1000_FCRTC, reg);</div><div class='ctx'> </div><div class='ctx'> 			/* Set the DMA Coalescing Rx threshold to PBA - 2 * max</div><div class='hunk'>@@ -10010,8 +10008,7 @@ static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)</div><div class='ctx'> 			dmac_thr = pba - 10;</div><div class='ctx'> 			reg = rd32(E1000_DMACR);</div><div class='ctx'> 			reg &amp;= ~E1000_DMACR_DMACTHR_MASK;</div><div class='del'>-			reg |= ((dmac_thr &lt;&lt; E1000_DMACR_DMACTHR_SHIFT)</div><div class='del'>-				&amp; E1000_DMACR_DMACTHR_MASK);</div><div class='add'>+			reg |= FIELD_PREP(E1000_DMACR_DMACTHR_MASK, dmac_thr);</div><div class='ctx'> </div><div class='ctx'> 			/* transition to L0x or L1 if available..*/</div><div class='ctx'> 			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igbvf/mbx.c b/drivers/net/ethernet/intel/igbvf/mbx.c<br/>index a3cd7ac48d4b..d15282ee5ea8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igbvf/mbx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igbvf/mbx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igbvf/mbx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igbvf/mbx.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright(c) 2009 - 2018 Intel Corporation. */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "mbx.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c<br/>index fd712585af27..a4d4f00e6a87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igbvf/netdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igbvf/netdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igbvf/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igbvf/netdev.c</a></div><div class='hunk'>@@ -3,25 +3,25 @@</div><div class='ctx'> </div><div class='ctx'> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt</div><div class='ctx'> </div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/types.h&gt;</div><div class='del'>-#include &lt;linux/init.h&gt;</div><div class='del'>-#include &lt;linux/pci.h&gt;</div><div class='del'>-#include &lt;linux/vmalloc.h&gt;</div><div class='del'>-#include &lt;linux/pagemap.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/netdevice.h&gt;</div><div class='del'>-#include &lt;linux/tcp.h&gt;</div><div class='del'>-#include &lt;linux/ipv6.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;net/checksum.h&gt;</div><div class='del'>-#include &lt;net/ip6_checksum.h&gt;</div><div class='del'>-#include &lt;linux/mii.h&gt;</div><div class='ctx'> #include &lt;linux/ethtool.h&gt;</div><div class='ctx'> #include &lt;linux/if_vlan.h&gt;</div><div class='add'>+#include &lt;linux/init.h&gt;</div><div class='add'>+#include &lt;linux/ipv6.h&gt;</div><div class='add'>+#include &lt;linux/mii.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/netdevice.h&gt;</div><div class='add'>+#include &lt;linux/pagemap.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='ctx'> #include &lt;linux/prefetch.h&gt;</div><div class='ctx'> #include &lt;linux/sctp.h&gt;</div><div class='del'>-</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include &lt;linux/tcp.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/vmalloc.h&gt;</div><div class='add'>+#include &lt;net/checksum.h&gt;</div><div class='add'>+#include &lt;net/ip6_checksum.h&gt;</div><div class='ctx'> #include "igbvf.h"</div><div class='ctx'> </div><div class='ctx'> char igbvf_driver_name[] = "igbvf";</div><div class='hunk'>@@ -273,9 +273,8 @@ static bool igbvf_clean_rx_irq(struct igbvf_adapter *adapter,</div><div class='ctx'> 		 * that case, it fills the header buffer and spills the rest</div><div class='ctx'> 		 * into the page.</div><div class='ctx'> 		 */</div><div class='del'>-		hlen = (le16_to_cpu(rx_desc-&gt;wb.lower.lo_dword.hs_rss.hdr_info)</div><div class='del'>-		       &amp; E1000_RXDADV_HDRBUFLEN_MASK) &gt;&gt;</div><div class='del'>-		       E1000_RXDADV_HDRBUFLEN_SHIFT;</div><div class='add'>+		hlen = le16_get_bits(rx_desc-&gt;wb.lower.lo_dword.hs_rss.hdr_info,</div><div class='add'>+				     E1000_RXDADV_HDRBUFLEN_MASK);</div><div class='ctx'> 		if (hlen &gt; adapter-&gt;rx_ps_hdr_size)</div><div class='ctx'> 			hlen = adapter-&gt;rx_ps_hdr_size;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h<br/>index f48f82d5e274..45430e246e9c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc.h</a></div><div class='hunk'>@@ -81,6 +81,21 @@ struct igc_tx_timestamp_request {</div><div class='ctx'> 	u32 flags;             /* flags that should be added to the tx_buffer */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct igc_inline_rx_tstamps {</div><div class='add'>+	/* Timestamps are saved in little endian at the beginning of the packet</div><div class='add'>+	 * buffer following the layout:</div><div class='add'>+	 *</div><div class='add'>+	 * DWORD: | 0              | 1              | 2              | 3              |</div><div class='add'>+	 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |</div><div class='add'>+	 *</div><div class='add'>+	 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds</div><div class='add'>+	 * part of the timestamp.</div><div class='add'>+	 *</div><div class='add'>+	 */</div><div class='add'>+	__le32 timer1[2];</div><div class='add'>+	__le32 timer0[2];</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct igc_ring_container {</div><div class='ctx'> 	struct igc_ring *ring;          /* pointer to linked list of rings */</div><div class='ctx'> 	unsigned int total_bytes;       /* total bytes processed this int */</div><div class='hunk'>@@ -261,6 +276,8 @@ struct igc_adapter {</div><div class='ctx'> 	unsigned int ptp_flags;</div><div class='ctx'> 	/* System time value lock */</div><div class='ctx'> 	spinlock_t tmreg_lock;</div><div class='add'>+	/* Free-running timer lock */</div><div class='add'>+	spinlock_t free_timer_lock;</div><div class='ctx'> 	struct cyclecounter cc;</div><div class='ctx'> 	struct timecounter tc;</div><div class='ctx'> 	struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */</div><div class='hunk'>@@ -469,6 +486,8 @@ enum igc_tx_flags {</div><div class='ctx'> 	IGC_TX_FLAGS_TSTAMP_1	= 0x100,</div><div class='ctx'> 	IGC_TX_FLAGS_TSTAMP_2	= 0x200,</div><div class='ctx'> 	IGC_TX_FLAGS_TSTAMP_3	= 0x400,</div><div class='add'>+</div><div class='add'>+	IGC_TX_FLAGS_TSTAMP_TIMER_1 = 0x800,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum igc_boards {</div><div class='hunk'>@@ -531,7 +550,7 @@ struct igc_rx_buffer {</div><div class='ctx'> struct igc_xdp_buff {</div><div class='ctx'> 	struct xdp_buff xdp;</div><div class='ctx'> 	union igc_adv_rx_desc *rx_desc;</div><div class='del'>-	ktime_t rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */</div><div class='add'>+	struct igc_inline_rx_tstamps *rx_ts; /* data indication bit IGC_RXDADV_STAT_TSIP */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct igc_q_vector {</div><div class='hunk'>@@ -568,6 +587,7 @@ struct igc_nfc_filter {</div><div class='ctx'> 	u16 etype;</div><div class='ctx'> 	__be16 vlan_etype;</div><div class='ctx'> 	u16 vlan_tci;</div><div class='add'>+	u16 vlan_tci_mask;</div><div class='ctx'> 	u8 src_addr[ETH_ALEN];</div><div class='ctx'> 	u8 dst_addr[ETH_ALEN];</div><div class='ctx'> 	u8 user_data[8];</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_base.c b/drivers/net/ethernet/intel/igc/igc_base.c<br/>index a1d815af507d..9fae8bdec2a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_base.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_base.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_base.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_base.c</a></div><div class='hunk'>@@ -68,8 +68,7 @@ static s32 igc_init_nvm_params_base(struct igc_hw *hw)</div><div class='ctx'> 	u32 eecd = rd32(IGC_EECD);</div><div class='ctx'> 	u16 size;</div><div class='ctx'> </div><div class='del'>-	size = (u16)((eecd &amp; IGC_EECD_SIZE_EX_MASK) &gt;&gt;</div><div class='del'>-		     IGC_EECD_SIZE_EX_SHIFT);</div><div class='add'>+	size = FIELD_GET(IGC_EECD_SIZE_EX_MASK, eecd);</div><div class='ctx'> </div><div class='ctx'> 	/* Added to a constant, "size" becomes the left-shift value</div><div class='ctx'> 	 * for setting word_size.</div><div class='hunk'>@@ -162,8 +161,7 @@ static s32 igc_init_phy_params_base(struct igc_hw *hw)</div><div class='ctx'> 	phy-&gt;reset_delay_us	= 100;</div><div class='ctx'> </div><div class='ctx'> 	/* set lan id */</div><div class='del'>-	hw-&gt;bus.func = (rd32(IGC_STATUS) &amp; IGC_STATUS_FUNC_MASK) &gt;&gt;</div><div class='del'>-			IGC_STATUS_FUNC_SHIFT;</div><div class='add'>+	hw-&gt;bus.func = FIELD_GET(IGC_STATUS_FUNC_MASK, rd32(IGC_STATUS));</div><div class='ctx'> </div><div class='ctx'> 	/* Make sure the PHY is in a good state. Several people have reported</div><div class='ctx'> 	 * firmware leaving the PHY's page select register set to something</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h<br/>index f7d6491d4c60..bf8cdfbba9ff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_base.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_base.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_base.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_base.h</a></div><div class='hunk'>@@ -37,6 +37,10 @@ struct igc_adv_tx_context_desc {</div><div class='ctx'> #define IGC_ADVTXD_TSTAMP_REG_1	0x00010000 /* Select register 1 for timestamp */</div><div class='ctx'> #define IGC_ADVTXD_TSTAMP_REG_2	0x00020000 /* Select register 2 for timestamp */</div><div class='ctx'> #define IGC_ADVTXD_TSTAMP_REG_3	0x00030000 /* Select register 3 for timestamp */</div><div class='add'>+#define IGC_ADVTXD_TSTAMP_TIMER_1	0x00010000 /* Select timer 1 for timestamp */</div><div class='add'>+#define IGC_ADVTXD_TSTAMP_TIMER_2	0x00020000 /* Select timer 2 for timestamp */</div><div class='add'>+#define IGC_ADVTXD_TSTAMP_TIMER_3	0x00030000 /* Select timer 3 for timestamp */</div><div class='add'>+</div><div class='ctx'> #define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */</div><div class='ctx'> #define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */</div><div class='ctx'> #define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h<br/>index b3037016f31d..5f92b3c7c3d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_defines.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_defines.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_defines.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_defines.h</a></div><div class='hunk'>@@ -317,6 +317,8 @@</div><div class='ctx'> #define IGC_TXD_CMD_TSE		0x04000000 /* TCP Seg enable */</div><div class='ctx'> #define IGC_TXD_EXTCMD_TSTAMP	0x00000010 /* IEEE1588 Timestamp packet */</div><div class='ctx'> </div><div class='add'>+#define IGC_TXD_PTP2_TIMER_1	0x00000020</div><div class='add'>+</div><div class='ctx'> /* IPSec Encrypt Enable */</div><div class='ctx'> #define IGC_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */</div><div class='ctx'> #define IGC_ADVTXD_MSS_SHIFT	16 /* Adv ctxt MSS shift */</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/ethernet/intel/igc/igc_ethtool.c<br/>index 785eaa8e0ba8..b95d2c86e803 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_ethtool.c</a></div><div class='hunk'>@@ -773,11 +773,9 @@ static void igc_ethtool_get_strings(struct net_device *netdev, u32 stringset,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; IGC_GLOBAL_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					igc_gstrings_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, igc_gstrings_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; IGC_NETDEV_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					igc_gstrings_net_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, igc_gstrings_net_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; adapter-&gt;num_tx_queues; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_packets", i);</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_bytes", i);</div><div class='hunk'>@@ -958,6 +956,7 @@ static int igc_ethtool_set_coalesce(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)</div><div class='add'>+#define VLAN_TCI_FULL_MASK ((__force __be16)~0)</div><div class='ctx'> static int igc_ethtool_get_nfc_rule(struct igc_adapter *adapter,</div><div class='ctx'> 				    struct ethtool_rxnfc *cmd)</div><div class='ctx'> {</div><div class='hunk'>@@ -980,10 +979,16 @@ static int igc_ethtool_get_nfc_rule(struct igc_adapter *adapter,</div><div class='ctx'> 		fsp-&gt;m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_ETYPE) {</div><div class='add'>+		fsp-&gt;flow_type |= FLOW_EXT;</div><div class='add'>+		fsp-&gt;h_ext.vlan_etype = rule-&gt;filter.vlan_etype;</div><div class='add'>+		fsp-&gt;m_ext.vlan_etype = ETHER_TYPE_FULL_MASK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_TCI) {</div><div class='ctx'> 		fsp-&gt;flow_type |= FLOW_EXT;</div><div class='ctx'> 		fsp-&gt;h_ext.vlan_tci = htons(rule-&gt;filter.vlan_tci);</div><div class='del'>-		fsp-&gt;m_ext.vlan_tci = htons(VLAN_PRIO_MASK);</div><div class='add'>+		fsp-&gt;m_ext.vlan_tci = htons(rule-&gt;filter.vlan_tci_mask);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_DST_MAC_ADDR) {</div><div class='hunk'>@@ -1218,6 +1223,7 @@ static void igc_ethtool_init_nfc_rule(struct igc_nfc_rule *rule,</div><div class='ctx'> </div><div class='ctx'> 	if ((fsp-&gt;flow_type &amp; FLOW_EXT) &amp;&amp; fsp-&gt;m_ext.vlan_tci) {</div><div class='ctx'> 		rule-&gt;filter.vlan_tci = ntohs(fsp-&gt;h_ext.vlan_tci);</div><div class='add'>+		rule-&gt;filter.vlan_tci_mask = ntohs(fsp-&gt;m_ext.vlan_tci);</div><div class='ctx'> 		rule-&gt;filter.match_flags |= IGC_FILTER_FLAG_VLAN_TCI;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1255,11 +1261,19 @@ static void igc_ethtool_init_nfc_rule(struct igc_nfc_rule *rule,</div><div class='ctx'> 		memcpy(rule-&gt;filter.user_mask, fsp-&gt;m_ext.data, sizeof(fsp-&gt;m_ext.data));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* When multiple filter options or user data or vlan etype is set, use a</div><div class='del'>-	 * flex filter.</div><div class='add'>+	/* The i225/i226 has various different filters. Flex filters provide a</div><div class='add'>+	 * way to match up to the first 128 bytes of a packet. Use them for:</div><div class='add'>+	 *   a) For specific user data</div><div class='add'>+	 *   b) For VLAN EtherType</div><div class='add'>+	 *   c) For full TCI match</div><div class='add'>+	 *   d) Or in case multiple filter criteria are set</div><div class='add'>+	 *</div><div class='add'>+	 * Otherwise, use the simple MAC, VLAN PRIO or EtherType filters.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if ((rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_USER_DATA) ||</div><div class='ctx'> 	    (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_ETYPE) ||</div><div class='add'>+	    ((rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_TCI) &amp;&amp;</div><div class='add'>+	     rule-&gt;filter.vlan_tci_mask == ntohs(VLAN_TCI_FULL_MASK)) ||</div><div class='ctx'> 	    (rule-&gt;filter.match_flags &amp; (rule-&gt;filter.match_flags - 1)))</div><div class='ctx'> 		rule-&gt;flex = true;</div><div class='ctx'> 	else</div><div class='hunk'>@@ -1329,6 +1343,26 @@ static int igc_ethtool_add_nfc_rule(struct igc_adapter *adapter,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* There are two ways to match the VLAN TCI:</div><div class='add'>+	 *  1. Match on PCP field and use vlan prio filter for it</div><div class='add'>+	 *  2. Match on complete TCI field and use flex filter for it</div><div class='add'>+	 */</div><div class='add'>+	if ((fsp-&gt;flow_type &amp; FLOW_EXT) &amp;&amp;</div><div class='add'>+	    fsp-&gt;m_ext.vlan_tci &amp;&amp;</div><div class='add'>+	    fsp-&gt;m_ext.vlan_tci != htons(VLAN_PRIO_MASK) &amp;&amp;</div><div class='add'>+	    fsp-&gt;m_ext.vlan_tci != VLAN_TCI_FULL_MASK) {</div><div class='add'>+		netdev_dbg(netdev, "VLAN mask not supported\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* VLAN EtherType can only be matched by full mask. */</div><div class='add'>+	if ((fsp-&gt;flow_type &amp; FLOW_EXT) &amp;&amp;</div><div class='add'>+	    fsp-&gt;m_ext.vlan_etype &amp;&amp;</div><div class='add'>+	    fsp-&gt;m_ext.vlan_etype != ETHER_TYPE_FULL_MASK) {</div><div class='add'>+		netdev_dbg(netdev, "VLAN EtherType mask not supported\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (fsp-&gt;location &gt;= IGC_MAX_RXNFC_RULES) {</div><div class='ctx'> 		netdev_dbg(netdev, "Invalid location\n");</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -1428,45 +1462,46 @@ static u32 igc_ethtool_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return IGC_RETA_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int igc_ethtool_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-				u8 *hfunc)</div><div class='add'>+static int igc_ethtool_get_rxfh(struct net_device *netdev,</div><div class='add'>+				struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct igc_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	for (i = 0; i &lt; IGC_RETA_SIZE; i++)</div><div class='del'>-		indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='add'>+		rxfh-&gt;indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int igc_ethtool_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-				const u8 *key, const u8 hfunc)</div><div class='add'>+static int igc_ethtool_set_rxfh(struct net_device *netdev,</div><div class='add'>+				struct ethtool_rxfh_param *rxfh,</div><div class='add'>+				struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct igc_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	u32 num_queues;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	num_queues = adapter-&gt;rss_queues;</div><div class='ctx'> </div><div class='ctx'> 	/* Verify user input. */</div><div class='ctx'> 	for (i = 0; i &lt; IGC_RETA_SIZE; i++)</div><div class='del'>-		if (indir[i] &gt;= num_queues)</div><div class='add'>+		if (rxfh-&gt;indir[i] &gt;= num_queues)</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IGC_RETA_SIZE; i++)</div><div class='del'>-		adapter-&gt;rss_indir_tbl[i] = indir[i];</div><div class='add'>+		adapter-&gt;rss_indir_tbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 	igc_write_rss_indir_tbl(adapter);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_i225.c b/drivers/net/ethernet/intel/igc/igc_i225.c<br/>index 17546a035ab1..0dd61719f1ed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_i225.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_i225.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_i225.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_i225.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright (c)  2018 Intel Corporation */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "igc_hw.h"</div><div class='hunk'>@@ -578,9 +579,8 @@ s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)</div><div class='ctx'> </div><div class='ctx'> 			/* Calculate tw_system (nsec). */</div><div class='ctx'> 			if (speed == SPEED_100) {</div><div class='del'>-				tw_system = ((rd32(IGC_EEE_SU) &amp;</div><div class='del'>-					     IGC_TW_SYSTEM_100_MASK) &gt;&gt;</div><div class='del'>-					     IGC_TW_SYSTEM_100_SHIFT) * 500;</div><div class='add'>+				tw_system = FIELD_GET(IGC_TW_SYSTEM_100_MASK,</div><div class='add'>+						      rd32(IGC_EEE_SU)) * 500;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				tw_system = (rd32(IGC_EEE_SU) &amp;</div><div class='ctx'> 					     IGC_TW_SYSTEM_1000_MASK) * 500;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c<br/>index e9bb403bbacf..ba8d3fe186ae 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_main.c</a></div><div class='hunk'>@@ -1299,14 +1299,16 @@ static void igc_tx_olinfo_status(struct igc_ring *tx_ring,</div><div class='ctx'> 	u32 olinfo_status = paylen &lt;&lt; IGC_ADVTXD_PAYLEN_SHIFT;</div><div class='ctx'> </div><div class='ctx'> 	/* insert L4 checksum */</div><div class='del'>-	olinfo_status |= (tx_flags &amp; IGC_TX_FLAGS_CSUM) *</div><div class='del'>-			  ((IGC_TXD_POPTS_TXSM &lt;&lt; 8) /</div><div class='del'>-			  IGC_TX_FLAGS_CSUM);</div><div class='add'>+	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_CSUM,</div><div class='add'>+				      (IGC_TXD_POPTS_TXSM &lt;&lt; 8));</div><div class='ctx'> </div><div class='ctx'> 	/* insert IPv4 checksum */</div><div class='del'>-	olinfo_status |= (tx_flags &amp; IGC_TX_FLAGS_IPV4) *</div><div class='del'>-			  (((IGC_TXD_POPTS_IXSM &lt;&lt; 8)) /</div><div class='del'>-			  IGC_TX_FLAGS_IPV4);</div><div class='add'>+	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_IPV4,</div><div class='add'>+				      (IGC_TXD_POPTS_IXSM &lt;&lt; 8));</div><div class='add'>+</div><div class='add'>+	/* Use the second timer (free running, in general) for the timestamp */</div><div class='add'>+	olinfo_status |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP_TIMER_1,</div><div class='add'>+				      IGC_TXD_PTP2_TIMER_1);</div><div class='ctx'> </div><div class='ctx'> 	tx_desc-&gt;read.olinfo_status = cpu_to_le32(olinfo_status);</div><div class='ctx'> }</div><div class='hunk'>@@ -1651,6 +1653,8 @@ done:</div><div class='ctx'> 		if (igc_request_tx_tstamp(adapter, skb, &amp;tstamp_flags)) {</div><div class='ctx'> 			skb_shinfo(skb)-&gt;tx_flags |= SKBTX_IN_PROGRESS;</div><div class='ctx'> 			tx_flags |= IGC_TX_FLAGS_TSTAMP | tstamp_flags;</div><div class='add'>+			if (skb_shinfo(skb)-&gt;tx_flags &amp; SKBTX_HW_TSTAMP_USE_CYCLES)</div><div class='add'>+				tx_flags |= IGC_TX_FLAGS_TSTAMP_TIMER_1;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			adapter-&gt;tx_hwtstamp_skipped++;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1963,9 +1967,9 @@ static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,</div><div class='ctx'> </div><div class='ctx'> static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,</div><div class='ctx'> 					 struct igc_rx_buffer *rx_buffer,</div><div class='del'>-					 struct xdp_buff *xdp,</div><div class='del'>-					 ktime_t timestamp)</div><div class='add'>+					 struct igc_xdp_buff *ctx)</div><div class='ctx'> {</div><div class='add'>+	struct xdp_buff *xdp = &amp;ctx-&gt;xdp;</div><div class='ctx'> 	unsigned int metasize = xdp-&gt;data - xdp-&gt;data_meta;</div><div class='ctx'> 	unsigned int size = xdp-&gt;data_end - xdp-&gt;data;</div><div class='ctx'> 	unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);</div><div class='hunk'>@@ -1982,8 +1986,10 @@ static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,</div><div class='ctx'> 	if (unlikely(!skb))</div><div class='ctx'> 		return NULL;</div><div class='ctx'> </div><div class='del'>-	if (timestamp)</div><div class='del'>-		skb_hwtstamps(skb)-&gt;hwtstamp = timestamp;</div><div class='add'>+	if (ctx-&gt;rx_ts) {</div><div class='add'>+		skb_shinfo(skb)-&gt;tx_flags |= SKBTX_HW_TSTAMP_NETDEV;</div><div class='add'>+		skb_hwtstamps(skb)-&gt;netdev_data = ctx-&gt;rx_ts;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Determine available headroom for copy */</div><div class='ctx'> 	headlen = size;</div><div class='hunk'>@@ -2583,11 +2589,10 @@ static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)</div><div class='ctx'> 	int xdp_status = 0, rx_buffer_pgcnt;</div><div class='ctx'> </div><div class='ctx'> 	while (likely(total_packets &lt; budget)) {</div><div class='del'>-		union igc_adv_rx_desc *rx_desc;</div><div class='add'>+		struct igc_xdp_buff ctx = { .rx_ts = NULL };</div><div class='ctx'> 		struct igc_rx_buffer *rx_buffer;</div><div class='add'>+		union igc_adv_rx_desc *rx_desc;</div><div class='ctx'> 		unsigned int size, truesize;</div><div class='del'>-		struct igc_xdp_buff ctx;</div><div class='del'>-		ktime_t timestamp = 0;</div><div class='ctx'> 		int pkt_offset = 0;</div><div class='ctx'> 		void *pktbuf;</div><div class='ctx'> </div><div class='hunk'>@@ -2614,9 +2619,7 @@ static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)</div><div class='ctx'> 		pktbuf = page_address(rx_buffer-&gt;page) + rx_buffer-&gt;page_offset;</div><div class='ctx'> </div><div class='ctx'> 		if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) {</div><div class='del'>-			timestamp = igc_ptp_rx_pktstamp(q_vector-&gt;adapter,</div><div class='del'>-							pktbuf);</div><div class='del'>-			ctx.rx_ts = timestamp;</div><div class='add'>+			ctx.rx_ts = pktbuf;</div><div class='ctx'> 			pkt_offset = IGC_TS_HDR_LEN;</div><div class='ctx'> 			size -= IGC_TS_HDR_LEN;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -2653,8 +2656,7 @@ static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)</div><div class='ctx'> 		else if (ring_uses_build_skb(rx_ring))</div><div class='ctx'> 			skb = igc_build_skb(rx_ring, rx_buffer, &amp;ctx.xdp);</div><div class='ctx'> 		else</div><div class='del'>-			skb = igc_construct_skb(rx_ring, rx_buffer, &amp;ctx.xdp,</div><div class='del'>-						timestamp);</div><div class='add'>+			skb = igc_construct_skb(rx_ring, rx_buffer, &amp;ctx);</div><div class='ctx'> </div><div class='ctx'> 		/* exit if we failed to retrieve a buffer */</div><div class='ctx'> 		if (!skb) {</div><div class='hunk'>@@ -2803,9 +2805,7 @@ static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget)</div><div class='ctx'> 		ctx-&gt;rx_desc = desc;</div><div class='ctx'> </div><div class='ctx'> 		if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) {</div><div class='del'>-			timestamp = igc_ptp_rx_pktstamp(q_vector-&gt;adapter,</div><div class='del'>-							bi-&gt;xdp-&gt;data);</div><div class='del'>-			ctx-&gt;rx_ts = timestamp;</div><div class='add'>+			ctx-&gt;rx_ts = bi-&gt;xdp-&gt;data;</div><div class='ctx'> </div><div class='ctx'> 			bi-&gt;xdp-&gt;data += IGC_TS_HDR_LEN;</div><div class='ctx'> </div><div class='hunk'>@@ -3452,8 +3452,8 @@ static int igc_write_flex_filter_ll(struct igc_adapter *adapter,</div><div class='ctx'> </div><div class='ctx'> 	/* Configure filter */</div><div class='ctx'> 	queuing = input-&gt;length &amp; IGC_FHFT_LENGTH_MASK;</div><div class='del'>-	queuing |= (input-&gt;rx_queue &lt;&lt; IGC_FHFT_QUEUE_SHIFT) &amp; IGC_FHFT_QUEUE_MASK;</div><div class='del'>-	queuing |= (input-&gt;prio &lt;&lt; IGC_FHFT_PRIO_SHIFT) &amp; IGC_FHFT_PRIO_MASK;</div><div class='add'>+	queuing |= FIELD_PREP(IGC_FHFT_QUEUE_MASK, input-&gt;rx_queue);</div><div class='add'>+	queuing |= FIELD_PREP(IGC_FHFT_PRIO_MASK, input-&gt;prio);</div><div class='ctx'> </div><div class='ctx'> 	if (input-&gt;immediate_irq)</div><div class='ctx'> 		queuing |= IGC_FHFT_IMM_INT;</div><div class='hunk'>@@ -3712,8 +3712,7 @@ static int igc_enable_nfc_rule(struct igc_adapter *adapter,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_TCI) {</div><div class='del'>-		int prio = (rule-&gt;filter.vlan_tci &amp; VLAN_PRIO_MASK) &gt;&gt;</div><div class='del'>-			   VLAN_PRIO_SHIFT;</div><div class='add'>+		int prio = FIELD_GET(VLAN_PRIO_MASK, rule-&gt;filter.vlan_tci);</div><div class='ctx'> </div><div class='ctx'> 		err = igc_add_vlan_prio_filter(adapter, prio, rule-&gt;action);</div><div class='ctx'> 		if (err)</div><div class='hunk'>@@ -3735,8 +3734,7 @@ static void igc_disable_nfc_rule(struct igc_adapter *adapter,</div><div class='ctx'> 		igc_del_etype_filter(adapter, rule-&gt;filter.etype);</div><div class='ctx'> </div><div class='ctx'> 	if (rule-&gt;filter.match_flags &amp; IGC_FILTER_FLAG_VLAN_TCI) {</div><div class='del'>-		int prio = (rule-&gt;filter.vlan_tci &amp; VLAN_PRIO_MASK) &gt;&gt;</div><div class='del'>-			   VLAN_PRIO_SHIFT;</div><div class='add'>+		int prio = FIELD_GET(VLAN_PRIO_MASK, rule-&gt;filter.vlan_tci);</div><div class='ctx'> </div><div class='ctx'> 		igc_del_vlan_prio_filter(adapter, prio);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -6562,6 +6560,24 @@ int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static ktime_t igc_get_tstamp(struct net_device *dev,</div><div class='add'>+			      const struct skb_shared_hwtstamps *hwtstamps,</div><div class='add'>+			      bool cycles)</div><div class='add'>+{</div><div class='add'>+	struct igc_adapter *adapter = netdev_priv(dev);</div><div class='add'>+	struct igc_inline_rx_tstamps *tstamp;</div><div class='add'>+	ktime_t timestamp;</div><div class='add'>+</div><div class='add'>+	tstamp = hwtstamps-&gt;netdev_data;</div><div class='add'>+</div><div class='add'>+	if (cycles)</div><div class='add'>+		timestamp = igc_ptp_rx_pktstamp(adapter, tstamp-&gt;timer1);</div><div class='add'>+	else</div><div class='add'>+		timestamp = igc_ptp_rx_pktstamp(adapter, tstamp-&gt;timer0);</div><div class='add'>+</div><div class='add'>+	return timestamp;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops igc_netdev_ops = {</div><div class='ctx'> 	.ndo_open		= igc_open,</div><div class='ctx'> 	.ndo_stop		= igc_close,</div><div class='hunk'>@@ -6579,6 +6595,7 @@ static const struct net_device_ops igc_netdev_ops = {</div><div class='ctx'> 	.ndo_bpf		= igc_bpf,</div><div class='ctx'> 	.ndo_xdp_xmit		= igc_xdp_xmit,</div><div class='ctx'> 	.ndo_xsk_wakeup		= igc_xsk_wakeup,</div><div class='add'>+	.ndo_get_tstamp		= igc_get_tstamp,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* PCIe configuration access */</div><div class='hunk'>@@ -6682,9 +6699,11 @@ static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash,</div><div class='ctx'> static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)</div><div class='ctx'> {</div><div class='ctx'> 	const struct igc_xdp_buff *ctx = (void *)_ctx;</div><div class='add'>+	struct igc_adapter *adapter = netdev_priv(ctx-&gt;xdp.rxq-&gt;dev);</div><div class='add'>+	struct igc_inline_rx_tstamps *tstamp = ctx-&gt;rx_ts;</div><div class='ctx'> </div><div class='ctx'> 	if (igc_test_staterr(ctx-&gt;rx_desc, IGC_RXDADV_STAT_TSIP)) {</div><div class='del'>-		*timestamp = ctx-&gt;rx_ts;</div><div class='add'>+		*timestamp = igc_ptp_rx_pktstamp(adapter, tstamp-&gt;timer0);</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_phy.c b/drivers/net/ethernet/intel/igc/igc_phy.c<br/>index 53b77c969c85..7cd8716d2ffa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_phy.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* Copyright (c)  2018 Intel Corporation */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include "igc_phy.h"</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -726,7 +727,7 @@ static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr,</div><div class='ctx'>  */</div><div class='ctx'> s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)</div><div class='ctx'> {</div><div class='del'>-	u8 dev_addr = (offset &amp; GPY_MMD_MASK) &gt;&gt; GPY_MMD_SHIFT;</div><div class='add'>+	u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	offset = offset &amp; GPY_REG_MASK;</div><div class='hunk'>@@ -757,7 +758,7 @@ s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)</div><div class='ctx'>  */</div><div class='ctx'> s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)</div><div class='ctx'> {</div><div class='del'>-	u8 dev_addr = (offset &amp; GPY_MMD_MASK) &gt;&gt; GPY_MMD_SHIFT;</div><div class='add'>+	u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	offset = offset &amp; GPY_REG_MASK;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c<br/>index 928f38792203..885faaa7b9de 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_ptp.c</a></div><div class='hunk'>@@ -459,12 +459,10 @@ static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,</div><div class='ctx'> /**</div><div class='ctx'>  * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer</div><div class='ctx'>  * @adapter: Pointer to adapter the packet buffer belongs to</div><div class='del'>- * @buf: Pointer to packet buffer</div><div class='add'>+ * @buf: Pointer to start of timestamp in HW format (2 32-bit words)</div><div class='ctx'>  *</div><div class='del'>- * This function retrieves the timestamp saved in the beginning of packet</div><div class='del'>- * buffer. While two timestamps are available, one in timer0 reference and the</div><div class='del'>- * other in timer1 reference, this function considers only the timestamp in</div><div class='del'>- * timer0 reference.</div><div class='add'>+ * This function retrieves and converts the timestamp stored at @buf</div><div class='add'>+ * to ktime_t, adjusting for hardware latencies.</div><div class='ctx'>  *</div><div class='ctx'>  * Returns timestamp value.</div><div class='ctx'>  */</div><div class='hunk'>@@ -474,17 +472,8 @@ ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)</div><div class='ctx'> 	u32 secs, nsecs;</div><div class='ctx'> 	int adjust;</div><div class='ctx'> </div><div class='del'>-	/* Timestamps are saved in little endian at the beginning of the packet</div><div class='del'>-	 * buffer following the layout:</div><div class='del'>-	 *</div><div class='del'>-	 * DWORD: | 0              | 1              | 2              | 3              |</div><div class='del'>-	 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |</div><div class='del'>-	 *</div><div class='del'>-	 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds</div><div class='del'>-	 * part of the timestamp.</div><div class='del'>-	 */</div><div class='del'>-	nsecs = le32_to_cpu(buf[2]);</div><div class='del'>-	secs = le32_to_cpu(buf[3]);</div><div class='add'>+	nsecs = le32_to_cpu(buf[0]);</div><div class='add'>+	secs = le32_to_cpu(buf[1]);</div><div class='ctx'> </div><div class='ctx'> 	timestamp = ktime_set(secs, nsecs);</div><div class='ctx'> </div><div class='hunk'>@@ -542,10 +531,11 @@ static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; adapter-&gt;num_rx_queues; i++) {</div><div class='ctx'> 		val = rd32(IGC_SRRCTL(i));</div><div class='del'>-		/* FIXME: For now, only support retrieving RX timestamps from</div><div class='del'>-		 * timer 0.</div><div class='add'>+		/* Enable retrieving timestamps from timer 0, the</div><div class='add'>+		 * "adjustable clock" and timer 1 the "free running</div><div class='add'>+		 * clock".</div><div class='ctx'> 		 */</div><div class='del'>-		val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |</div><div class='add'>+		val |= IGC_SRRCTL_TIMER1SEL(1) | IGC_SRRCTL_TIMER0SEL(0) |</div><div class='ctx'> 		       IGC_SRRCTL_TIMESTAMP;</div><div class='ctx'> 		wr32(IGC_SRRCTL(i), val);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1035,6 +1025,26 @@ static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,</div><div class='ctx'> 					     adapter, &amp;adapter-&gt;snapshot, cts);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int igc_ptp_getcyclesx64(struct ptp_clock_info *ptp,</div><div class='add'>+				struct timespec64 *ts,</div><div class='add'>+				struct ptp_system_timestamp *sts)</div><div class='add'>+{</div><div class='add'>+	struct igc_adapter *igc = container_of(ptp, struct igc_adapter, ptp_caps);</div><div class='add'>+	struct igc_hw *hw = &amp;igc-&gt;hw;</div><div class='add'>+	unsigned long flags;</div><div class='add'>+</div><div class='add'>+	spin_lock_irqsave(&amp;igc-&gt;free_timer_lock, flags);</div><div class='add'>+</div><div class='add'>+	ptp_read_system_prets(sts);</div><div class='add'>+	ts-&gt;tv_nsec = rd32(IGC_SYSTIML_1);</div><div class='add'>+	ts-&gt;tv_sec = rd32(IGC_SYSTIMH_1);</div><div class='add'>+	ptp_read_system_postts(sts);</div><div class='add'>+</div><div class='add'>+	spin_unlock_irqrestore(&amp;igc-&gt;free_timer_lock, flags);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * igc_ptp_init - Initialize PTP functionality</div><div class='ctx'>  * @adapter: Board private structure</div><div class='hunk'>@@ -1088,6 +1098,7 @@ void igc_ptp_init(struct igc_adapter *adapter)</div><div class='ctx'> 		adapter-&gt;ptp_caps.adjfine = igc_ptp_adjfine_i225;</div><div class='ctx'> 		adapter-&gt;ptp_caps.adjtime = igc_ptp_adjtime_i225;</div><div class='ctx'> 		adapter-&gt;ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;</div><div class='add'>+		adapter-&gt;ptp_caps.getcyclesx64 = igc_ptp_getcyclesx64;</div><div class='ctx'> 		adapter-&gt;ptp_caps.settime64 = igc_ptp_settime_i225;</div><div class='ctx'> 		adapter-&gt;ptp_caps.enable = igc_ptp_feature_enable_i225;</div><div class='ctx'> 		adapter-&gt;ptp_caps.pps = 1;</div><div class='hunk'>@@ -1108,6 +1119,7 @@ void igc_ptp_init(struct igc_adapter *adapter)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;adapter-&gt;ptp_tx_lock);</div><div class='add'>+	spin_lock_init(&amp;adapter-&gt;free_timer_lock);</div><div class='ctx'> 	spin_lock_init(&amp;adapter-&gt;tmreg_lock);</div><div class='ctx'> </div><div class='ctx'> 	adapter-&gt;tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h<br/>index 20e17f5fbce3..d38c87d7e5e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_regs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_regs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_regs.h</a></div><div class='hunk'>@@ -243,6 +243,11 @@</div><div class='ctx'> #define IGC_SYSTIMR	0x0B6F8  /* System time register Residue */</div><div class='ctx'> #define IGC_TIMINCA	0x0B608  /* Increment attributes register - RW */</div><div class='ctx'> </div><div class='add'>+#define IGC_SYSTIML_1	0x0B688  /* System time register Low - RO (timer 1) */</div><div class='add'>+#define IGC_SYSTIMH_1	0x0B68C  /* System time register High - RO (timer 1) */</div><div class='add'>+#define IGC_SYSTIMR_1	0x0B684  /* System time register Residue (timer 1) */</div><div class='add'>+#define IGC_TIMINCA_1	0x0B690  /* Increment attributes register - RW (timer 1) */</div><div class='add'>+</div><div class='ctx'> /* TX Timestamp Low */</div><div class='ctx'> #define IGC_TXSTMPL_0		0x0B618</div><div class='ctx'> #define IGC_TXSTMPL_1		0x0B698</div><div class='head'>diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/ethernet/intel/igc/igc_tsn.c<br/>index a9c08321aca9..22cefb1eeedf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_tsn.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/igc/igc_tsn.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/igc/igc_tsn.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/igc/igc_tsn.c</a></div><div class='hunk'>@@ -227,7 +227,7 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)</div><div class='ctx'> 			wr32(IGC_TQAVCC(i), tqavcc);</div><div class='ctx'> </div><div class='ctx'> 			wr32(IGC_TQAVHC(i),</div><div class='del'>-			     0x80000000 + ring-&gt;hicredit * 0x7735);</div><div class='add'>+			     0x80000000 + ring-&gt;hicredit * 0x7736);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* Disable any CBS for the queue */</div><div class='ctx'> 			txqctl &amp;= ~(IGC_TXQCTL_QAV_SEL_MASK);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c<br/>index 100388968e4d..6835d5f18753 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c</a></div><div class='hunk'>@@ -123,14 +123,14 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			return ret_val;</div><div class='ctx'> 		if (hw-&gt;phy.sfp_type == ixgbe_sfp_type_unknown)</div><div class='del'>-			return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 		/* Check to see if SFP+ module is supported */</div><div class='ctx'> 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,</div><div class='ctx'> 							    &amp;list_offset,</div><div class='ctx'> 							    &amp;data_offset);</div><div class='ctx'> 		if (ret_val)</div><div class='del'>-			return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -213,7 +213,7 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -283,7 +283,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Validate the water mark configuration */</div><div class='ctx'> 	if (!hw-&gt;fc.pause_time)</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Low water mark of zero causes XOFF floods */</div><div class='ctx'> 	for (i = 0; i &lt; MAX_TRAFFIC_CLASS; i++) {</div><div class='hunk'>@@ -292,7 +292,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)</div><div class='ctx'> 			if (!hw-&gt;fc.low_water[i] ||</div><div class='ctx'> 			    hw-&gt;fc.low_water[i] &gt;= hw-&gt;fc.high_water[i]) {</div><div class='ctx'> 				hw_dbg(hw, "Invalid water mark configuration\n");</div><div class='del'>-				return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -369,7 +369,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, "Flow control param set incorrectly\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set 802.3x based flow control settings. */</div><div class='hunk'>@@ -438,7 +438,7 @@ static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,</div><div class='ctx'> 				msleep(100);</div><div class='ctx'> 			}</div><div class='ctx'> 			if (!(links_reg &amp; IXGBE_LINKS_KX_AN_COMP)) {</div><div class='del'>-				status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;</div><div class='add'>+				status = -EIO;</div><div class='ctx'> 				hw_dbg(hw, "Autonegotiation did not complete.\n");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -478,7 +478,7 @@ static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {</div><div class='ctx'> 		hw_dbg(hw, "Link was indicated but link is down\n");</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -594,7 +594,7 @@ static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,</div><div class='ctx'> 	speed &amp;= link_capabilities;</div><div class='ctx'> </div><div class='ctx'> 	if (speed == IXGBE_LINK_SPEED_UNKNOWN)</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Set KX4/KX support according to speed requested */</div><div class='ctx'> 	else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||</div><div class='hunk'>@@ -701,9 +701,9 @@ static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 		/* Init PHY and function pointers, perform SFP setup */</div><div class='ctx'> 		phy_status = hw-&gt;phy.ops.init(hw);</div><div class='del'>-		if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+		if (phy_status == -EOPNOTSUPP)</div><div class='ctx'> 			return phy_status;</div><div class='del'>-		if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)</div><div class='add'>+		if (phy_status == -ENOENT)</div><div class='ctx'> 			goto mac_reset_top;</div><div class='ctx'> </div><div class='ctx'> 		hw-&gt;phy.ops.reset(hw);</div><div class='hunk'>@@ -727,7 +727,7 @@ mac_reset_top:</div><div class='ctx'> 		udelay(1);</div><div class='ctx'> 	}</div><div class='ctx'> 	if (ctrl &amp; IXGBE_CTRL_RST) {</div><div class='del'>-		status = IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		hw_dbg(hw, "Reset polling failed to complete.\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -789,12 +789,12 @@ static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (rar &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));</div><div class='ctx'> 	rar_high &amp;= ~IXGBE_RAH_VIND_MASK;</div><div class='del'>-	rar_high |= ((vmdq &lt;&lt; IXGBE_RAH_VIND_SHIFT) &amp; IXGBE_RAH_VIND_MASK);</div><div class='add'>+	rar_high |= FIELD_PREP(IXGBE_RAH_VIND_MASK, vmdq);</div><div class='ctx'> 	IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -814,7 +814,7 @@ static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (rar &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));</div><div class='hunk'>@@ -845,7 +845,7 @@ static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,</div><div class='ctx'> 	u32 vftabyte;</div><div class='ctx'> </div><div class='ctx'> 	if (vlan &gt; 4095)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Determine 32-bit word position in array */</div><div class='ctx'> 	regindex = (vlan &gt;&gt; 5) &amp; 0x7F;   /* upper seven bits */</div><div class='hunk'>@@ -964,7 +964,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,</div><div class='ctx'> 		gssr = IXGBE_GSSR_PHY0_SM;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, gssr) != 0)</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.type == ixgbe_phy_nl) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -993,7 +993,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,</div><div class='ctx'> </div><div class='ctx'> 		if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {</div><div class='ctx'> 			hw_dbg(hw, "EEPROM read did not pass.\n");</div><div class='del'>-			status = IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+			status = -ENOENT;</div><div class='ctx'> 			goto out;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1003,7 +1003,7 @@ static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,</div><div class='ctx'> </div><div class='ctx'> 		*eeprom_data = (u8)(sfp_data &gt;&gt; 8);</div><div class='ctx'> 	} else {</div><div class='del'>-		status = IXGBE_ERR_PHY;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c<br/>index 58ea959a4482..339e106a5732 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c</a></div><div class='hunk'>@@ -117,7 +117,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 		ret_val = hw-&gt;mac.ops.acquire_swfw_sync(hw,</div><div class='ctx'> 							IXGBE_GSSR_MAC_CSR_SM);</div><div class='ctx'> 		if (ret_val)</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		if (hw-&gt;eeprom.ops.read(hw, ++data_offset, &amp;data_value))</div><div class='ctx'> 			goto setup_sfp_err;</div><div class='hunk'>@@ -144,7 +144,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 		if (ret_val) {</div><div class='ctx'> 			hw_dbg(hw, " sfp module setup not complete\n");</div><div class='del'>-			return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -159,7 +159,7 @@ setup_sfp_err:</div><div class='ctx'> 	usleep_range(hw-&gt;eeprom.semaphore_delay * 1000,</div><div class='ctx'> 		     hw-&gt;eeprom.semaphore_delay * 2000);</div><div class='ctx'> 	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);</div><div class='del'>-	return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -184,7 +184,7 @@ static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,</div><div class='ctx'> 		ret_val = hw-&gt;mac.ops.acquire_swfw_sync(hw,</div><div class='ctx'> 					IXGBE_GSSR_MAC_CSR_SM);</div><div class='ctx'> 		if (ret_val)</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		*locked = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -219,7 +219,7 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)</div><div class='ctx'> 		ret_val = hw-&gt;mac.ops.acquire_swfw_sync(hw,</div><div class='ctx'> 					IXGBE_GSSR_MAC_CSR_SM);</div><div class='ctx'> 		if (ret_val)</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		locked = true;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -400,7 +400,7 @@ static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.multispeed_fiber) {</div><div class='hunk'>@@ -541,7 +541,7 @@ static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 				msleep(100);</div><div class='ctx'> 			}</div><div class='ctx'> 			if (!(links_reg &amp; IXGBE_LINKS_KX_AN_COMP)) {</div><div class='del'>-				status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;</div><div class='add'>+				status = -EIO;</div><div class='ctx'> 				hw_dbg(hw, "Autoneg did not complete.\n");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='hunk'>@@ -794,7 +794,7 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 	speed &amp;= link_capabilities;</div><div class='ctx'> </div><div class='ctx'> 	if (speed == IXGBE_LINK_SPEED_UNKNOWN)</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/</div><div class='ctx'> 	if (hw-&gt;mac.orig_link_settings_stored)</div><div class='hunk'>@@ -861,8 +861,7 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 					msleep(100);</div><div class='ctx'> 				}</div><div class='ctx'> 				if (!(links_reg &amp; IXGBE_LINKS_KX_AN_COMP)) {</div><div class='del'>-					status =</div><div class='del'>-						IXGBE_ERR_AUTONEG_NOT_COMPLETE;</div><div class='add'>+					status = -EIO;</div><div class='ctx'> 					hw_dbg(hw, "Autoneg did not complete.\n");</div><div class='ctx'> 				}</div><div class='ctx'> 			}</div><div class='hunk'>@@ -927,7 +926,7 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 	/* Identify PHY and related function pointers */</div><div class='ctx'> 	status = hw-&gt;phy.ops.init(hw);</div><div class='ctx'> </div><div class='del'>-	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+	if (status == -EOPNOTSUPP)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup SFP module if there is one present. */</div><div class='hunk'>@@ -936,7 +935,7 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 		hw-&gt;phy.sfp_setup_needed = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+	if (status == -EOPNOTSUPP)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset PHY */</div><div class='hunk'>@@ -974,7 +973,7 @@ mac_reset_top:</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl &amp; IXGBE_CTRL_RST_MASK) {</div><div class='del'>-		status = IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		hw_dbg(hw, "Reset polling failed to complete.\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1093,7 +1092,7 @@ static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)</div><div class='ctx'> 		udelay(10);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_FDIR_CMD_INCOMPLETE;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1155,7 +1154,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> 	if (i &gt;= IXGBE_FDIR_INIT_DONE_POLL) {</div><div class='ctx'> 		hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");</div><div class='del'>-		return IXGBE_ERR_FDIR_REINIT_FAILED;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Clear FDIR statistics registers (read to clear) */</div><div class='hunk'>@@ -1387,7 +1386,7 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, " Error on flow type input\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* configure FDIRCMD register */</div><div class='hunk'>@@ -1546,7 +1545,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, " Error on vm pool mask\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (input_mask-&gt;formatted.flow_type &amp; IXGBE_ATR_L4TYPE_MASK) {</div><div class='hunk'>@@ -1555,14 +1554,14 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		if (input_mask-&gt;formatted.dst_port ||</div><div class='ctx'> 		    input_mask-&gt;formatted.src_port) {</div><div class='ctx'> 			hw_dbg(hw, " Error on src/dst port mask\n");</div><div class='del'>-			return IXGBE_ERR_CONFIG;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case IXGBE_ATR_L4TYPE_MASK:</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, " Error on flow type mask\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (ntohs(input_mask-&gt;formatted.vlan_id) &amp; 0xEFFF) {</div><div class='hunk'>@@ -1583,7 +1582,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, " Error on VLAN mask\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch ((__force u16)input_mask-&gt;formatted.flex_bytes &amp; 0xFFFF) {</div><div class='hunk'>@@ -1595,7 +1594,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, " Error on flexible byte mask\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */</div><div class='hunk'>@@ -1824,7 +1823,7 @@ static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Return error if SFP module has been detected but is not supported */</div><div class='ctx'> 	if (hw-&gt;phy.type == ixgbe_phy_sfp_unsupported)</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='hunk'>@@ -1863,13 +1862,13 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)</div><div class='ctx'>  *  Verifies that installed the firmware version is 0.6 or higher</div><div class='ctx'>  *  for SFI devices. All 82599 SFI devices should have version 0.6 or higher.</div><div class='ctx'>  *</div><div class='del'>- *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or</div><div class='del'>- *  if the FW version is not supported.</div><div class='add'>+ *  Return: -EACCES if the FW is not present or if the FW version is</div><div class='add'>+ *  not supported.</div><div class='ctx'>  **/</div><div class='ctx'> static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	s32 status = IXGBE_ERR_EEPROM_VERSION;</div><div class='ctx'> 	u16 fw_offset, fw_ptp_cfg_offset;</div><div class='add'>+	s32 status = -EACCES;</div><div class='ctx'> 	u16 offset;</div><div class='ctx'> 	u16 fw_version = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1883,7 +1882,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 		goto fw_version_err;</div><div class='ctx'> </div><div class='ctx'> 	if (fw_offset == 0 || fw_offset == 0xFFFF)</div><div class='del'>-		return IXGBE_ERR_EEPROM_VERSION;</div><div class='add'>+		return -EACCES;</div><div class='ctx'> </div><div class='ctx'> 	/* get the offset to the Pass Through Patch Configuration block */</div><div class='ctx'> 	offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;</div><div class='hunk'>@@ -1891,7 +1890,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)</div><div class='ctx'> 		goto fw_version_err;</div><div class='ctx'> </div><div class='ctx'> 	if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF)</div><div class='del'>-		return IXGBE_ERR_EEPROM_VERSION;</div><div class='add'>+		return -EACCES;</div><div class='ctx'> </div><div class='ctx'> 	/* get the firmware version */</div><div class='ctx'> 	offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;</div><div class='hunk'>@@ -1905,7 +1904,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> fw_version_err:</div><div class='ctx'> 	hw_err(hw, "eeprom read at offset %d failed\n", offset);</div><div class='del'>-	return IXGBE_ERR_EEPROM_VERSION;</div><div class='add'>+	return -EACCES;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2038,7 +2037,7 @@ static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (!(anlp1_reg &amp; IXGBE_ANLP1_AN_STATE_MASK)) {</div><div class='ctx'> 		hw_dbg(hw, "auto negotiation not completed\n");</div><div class='del'>-		ret_val = IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		ret_val = -EIO;</div><div class='ctx'> 		goto reset_pipeline_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2087,7 +2086,7 @@ static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='ctx'> </div><div class='ctx'> 		if (!timeout) {</div><div class='ctx'> 			hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");</div><div class='del'>-			status = IXGBE_ERR_I2C;</div><div class='add'>+			status = -EIO;</div><div class='ctx'> 			goto release_i2c_access;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2141,7 +2140,7 @@ static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='ctx'> </div><div class='ctx'> 		if (!timeout) {</div><div class='ctx'> 			hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");</div><div class='del'>-			status = IXGBE_ERR_I2C;</div><div class='add'>+			status = -EIO;</div><div class='ctx'> 			goto release_i2c_access;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c<br/>index 878dd8dff528..2e6e0365154a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_common.c</a></div><div class='hunk'>@@ -124,7 +124,7 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (hw-&gt;fc.strict_ieee &amp;&amp; hw-&gt;fc.requested_mode == ixgbe_fc_rx_pause) {</div><div class='ctx'> 		hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -215,7 +215,7 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, "Flow control param set incorrectly\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.type != ixgbe_mac_X540) {</div><div class='hunk'>@@ -500,7 +500,7 @@ s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,</div><div class='ctx'> </div><div class='ctx'> 	if (pba_num == NULL) {</div><div class='ctx'> 		hw_dbg(hw, "PBA string buffer was null\n");</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret_val = hw-&gt;eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &amp;data);</div><div class='hunk'>@@ -526,7 +526,7 @@ s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,</div><div class='ctx'> 		/* we will need 11 characters to store the PBA */</div><div class='ctx'> 		if (pba_num_size &lt; 11) {</div><div class='ctx'> 			hw_dbg(hw, "PBA string buffer too small\n");</div><div class='del'>-			return IXGBE_ERR_NO_SPACE;</div><div class='add'>+			return -ENOSPC;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* extract hex string from data and pba_ptr */</div><div class='hunk'>@@ -563,13 +563,13 @@ s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,</div><div class='ctx'> </div><div class='ctx'> 	if (length == 0xFFFF || length == 0) {</div><div class='ctx'> 		hw_dbg(hw, "NVM PBA number section invalid length\n");</div><div class='del'>-		return IXGBE_ERR_PBA_SECTION;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* check if pba_num buffer is big enough */</div><div class='ctx'> 	if (pba_num_size  &lt; (((u32)length * 2) - 1)) {</div><div class='ctx'> 		hw_dbg(hw, "PBA string buffer too small\n");</div><div class='del'>-		return IXGBE_ERR_NO_SPACE;</div><div class='add'>+		return -ENOSPC;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* trim pba length from start of string */</div><div class='hunk'>@@ -684,7 +684,7 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	reg = IXGBE_READ_REG(hw, IXGBE_STATUS);</div><div class='del'>-	bus-&gt;func = (reg &amp; IXGBE_STATUS_LAN_ID) &gt;&gt; IXGBE_STATUS_LAN_ID_SHIFT;</div><div class='add'>+	bus-&gt;func = FIELD_GET(IXGBE_STATUS_LAN_ID, reg);</div><div class='ctx'> 	bus-&gt;lan_id = bus-&gt;func;</div><div class='ctx'> </div><div class='ctx'> 	/* check for a port swap */</div><div class='hunk'>@@ -695,8 +695,8 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)</div><div class='ctx'> 	/* Get MAC instance from EEPROM for configuring CS4227 */</div><div class='ctx'> 	if (hw-&gt;device_id == IXGBE_DEV_ID_X550EM_A_SFP) {</div><div class='ctx'> 		hw-&gt;eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &amp;ee_ctrl_4);</div><div class='del'>-		bus-&gt;instance_id = (ee_ctrl_4 &amp; IXGBE_EE_CTRL_4_INST_ID) &gt;&gt;</div><div class='del'>-				   IXGBE_EE_CTRL_4_INST_ID_SHIFT;</div><div class='add'>+		bus-&gt;instance_id = FIELD_GET(IXGBE_EE_CTRL_4_INST_ID,</div><div class='add'>+					     ee_ctrl_4);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -805,7 +805,7 @@ s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* To turn on the LED, set mode to ON. */</div><div class='ctx'> 	led_reg &amp;= ~IXGBE_LED_MODE_MASK(index);</div><div class='hunk'>@@ -826,7 +826,7 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* To turn off the LED, set mode to OFF. */</div><div class='ctx'> 	led_reg &amp;= ~IXGBE_LED_MODE_MASK(index);</div><div class='hunk'>@@ -870,10 +870,9 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 			 * SPI EEPROM is assumed here.  This code would need to</div><div class='ctx'> 			 * change if a future EEPROM is not SPI.</div><div class='ctx'> 			 */</div><div class='del'>-			eeprom_size = (u16)((eec &amp; IXGBE_EEC_SIZE) &gt;&gt;</div><div class='del'>-					    IXGBE_EEC_SIZE_SHIFT);</div><div class='add'>+			eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);</div><div class='ctx'> 			eeprom-&gt;word_size = BIT(eeprom_size +</div><div class='del'>-						 IXGBE_EEPROM_WORD_SIZE_SHIFT);</div><div class='add'>+						IXGBE_EEPROM_WORD_SIZE_SHIFT);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (eec &amp; IXGBE_EEC_ADDR_SIZE)</div><div class='hunk'>@@ -904,11 +903,8 @@ s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='del'>-	if (words == 0)</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='del'>-</div><div class='del'>-	if (offset + words &gt; hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+	if (words == 0 || (offset + words &gt; hw-&gt;eeprom.word_size))</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * The EEPROM page size cannot be queried from the chip. We do lazy</div><div class='hunk'>@@ -962,7 +958,7 @@ static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	if (ixgbe_ready_eeprom(hw) != 0) {</div><div class='ctx'> 		ixgbe_release_eeprom(hw);</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; words; i++) {</div><div class='hunk'>@@ -1028,7 +1024,7 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)</div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='ctx'> 	if (offset &gt;= hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &amp;data);</div><div class='ctx'> }</div><div class='hunk'>@@ -1050,11 +1046,8 @@ s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='del'>-	if (words == 0)</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='del'>-</div><div class='del'>-	if (offset + words &gt; hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+	if (words == 0 || (offset + words &gt; hw-&gt;eeprom.word_size))</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * We cannot hold synchronization semaphores for too long</div><div class='hunk'>@@ -1099,7 +1092,7 @@ static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	if (ixgbe_ready_eeprom(hw) != 0) {</div><div class='ctx'> 		ixgbe_release_eeprom(hw);</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; words; i++) {</div><div class='hunk'>@@ -1142,7 +1135,7 @@ s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='ctx'> 	if (offset &gt;= hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);</div><div class='ctx'> }</div><div class='hunk'>@@ -1165,11 +1158,8 @@ s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='del'>-	if (words == 0)</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='del'>-</div><div class='del'>-	if (offset &gt;= hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+	if (words == 0 || offset &gt;= hw-&gt;eeprom.word_size)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; words; i++) {</div><div class='ctx'> 		eerd = ((offset + i) &lt;&lt; IXGBE_EEPROM_RW_ADDR_SHIFT) |</div><div class='hunk'>@@ -1262,11 +1252,8 @@ s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;eeprom.ops.init_params(hw);</div><div class='ctx'> </div><div class='del'>-	if (words == 0)</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='del'>-</div><div class='del'>-	if (offset &gt;= hw-&gt;eeprom.word_size)</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+	if (words == 0 || offset &gt;= hw-&gt;eeprom.word_size)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; words; i++) {</div><div class='ctx'> 		eewr = ((offset + i) &lt;&lt; IXGBE_EEPROM_RW_ADDR_SHIFT) |</div><div class='hunk'>@@ -1328,7 +1315,7 @@ static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)</div><div class='ctx'> 		}</div><div class='ctx'> 		udelay(5);</div><div class='ctx'> 	}</div><div class='del'>-	return IXGBE_ERR_EEPROM;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1344,7 +1331,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)</div><div class='ctx'> 	u32 i;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));</div><div class='ctx'> </div><div class='hunk'>@@ -1366,7 +1353,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)</div><div class='ctx'> 		hw_dbg(hw, "Could not acquire EEPROM grant\n");</div><div class='ctx'> </div><div class='ctx'> 		hw-&gt;mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Setup EEPROM for Read/Write */</div><div class='hunk'>@@ -1419,7 +1406,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)</div><div class='ctx'> 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));</div><div class='ctx'> 		if (swsm &amp; IXGBE_SWSM_SMBI) {</div><div class='ctx'> 			hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");</div><div class='del'>-			return IXGBE_ERR_EEPROM;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1447,7 +1434,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)</div><div class='ctx'> 	if (i &gt;= timeout) {</div><div class='ctx'> 		hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");</div><div class='ctx'> 		ixgbe_release_eeprom_semaphore(hw);</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1503,7 +1490,7 @@ static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (i &gt;= IXGBE_EEPROM_MAX_RETRY_SPI) {</div><div class='ctx'> 		hw_dbg(hw, "SPI EEPROM Status error\n");</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1715,7 +1702,7 @@ s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 	for (i = IXGBE_PCIE_ANALOG_PTR; i &lt; IXGBE_FW_PTR; i++) {</div><div class='ctx'> 		if (hw-&gt;eeprom.ops.read(hw, i, &amp;pointer)) {</div><div class='ctx'> 			hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-			return IXGBE_ERR_EEPROM;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* If the pointer seems invalid */</div><div class='hunk'>@@ -1724,7 +1711,7 @@ s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 		if (hw-&gt;eeprom.ops.read(hw, pointer, &amp;length)) {</div><div class='ctx'> 			hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-			return IXGBE_ERR_EEPROM;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (length == 0xFFFF || length == 0)</div><div class='hunk'>@@ -1733,7 +1720,7 @@ s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		for (j = pointer + 1; j &lt;= pointer + length; j++) {</div><div class='ctx'> 			if (hw-&gt;eeprom.ops.read(hw, j, &amp;word)) {</div><div class='ctx'> 				hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-				return IXGBE_ERR_EEPROM;</div><div class='add'>+				return -EIO;</div><div class='ctx'> 			}</div><div class='ctx'> 			checksum += word;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -1786,7 +1773,7 @@ s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,</div><div class='ctx'> 	 * calculated checksum</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (read_checksum != checksum)</div><div class='del'>-		status = IXGBE_ERR_EEPROM_CHECKSUM;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> </div><div class='ctx'> 	/* If the user cares, return the calculated checksum */</div><div class='ctx'> 	if (checksum_val)</div><div class='hunk'>@@ -1845,7 +1832,7 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (index &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", index);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* setup VMDq pool selection before this RAR gets enabled */</div><div class='hunk'>@@ -1897,7 +1884,7 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (index &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", index);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2146,7 +2133,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Validate the water mark configuration. */</div><div class='ctx'> 	if (!hw-&gt;fc.pause_time)</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Low water mark of zero causes XOFF floods */</div><div class='ctx'> 	for (i = 0; i &lt; MAX_TRAFFIC_CLASS; i++) {</div><div class='hunk'>@@ -2155,7 +2142,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 			if (!hw-&gt;fc.low_water[i] ||</div><div class='ctx'> 			    hw-&gt;fc.low_water[i] &gt;= hw-&gt;fc.high_water[i]) {</div><div class='ctx'> 				hw_dbg(hw, "Invalid water mark configuration\n");</div><div class='del'>-				return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+				return -EINVAL;</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2212,7 +2199,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_dbg(hw, "Flow control param set incorrectly\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set 802.3x based flow control settings. */</div><div class='hunk'>@@ -2269,7 +2256,7 @@ s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,</div><div class='ctx'> 		       u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)</div><div class='ctx'> {</div><div class='ctx'> 	if ((!(adv_reg)) ||  (!(lp_reg)))</div><div class='del'>-		return IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if ((adv_reg &amp; adv_sym) &amp;&amp; (lp_reg &amp; lp_sym)) {</div><div class='ctx'> 		/*</div><div class='hunk'>@@ -2321,7 +2308,7 @@ static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)</div><div class='ctx'> 	linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);</div><div class='ctx'> 	if ((!!(linkstat &amp; IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||</div><div class='ctx'> 	    (!!(linkstat &amp; IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))</div><div class='del'>-		return IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);</div><div class='ctx'> 	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);</div><div class='hunk'>@@ -2353,12 +2340,12 @@ static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)</div><div class='ctx'> 	 */</div><div class='ctx'> 	links = IXGBE_READ_REG(hw, IXGBE_LINKS);</div><div class='ctx'> 	if ((links &amp; IXGBE_LINKS_KX_AN_COMP) == 0)</div><div class='del'>-		return IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.type == ixgbe_mac_82599EB) {</div><div class='ctx'> 		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);</div><div class='ctx'> 		if ((links2 &amp; IXGBE_LINKS2_AN_SUPPORTED) == 0)</div><div class='del'>-			return IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Read the 10g AN autoc and LP ability registers and resolve</div><div class='hunk'>@@ -2407,8 +2394,8 @@ static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)</div><div class='ctx'>  **/</div><div class='ctx'> void ixgbe_fc_autoneg(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='ctx'> 	ixgbe_link_speed speed;</div><div class='add'>+	s32 ret_val = -EIO;</div><div class='ctx'> 	bool link_up;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -2510,7 +2497,7 @@ static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)</div><div class='ctx'>  *  @hw: pointer to hardware structure</div><div class='ctx'>  *</div><div class='ctx'>  *  Disables PCI-Express primary access and verifies there are no pending</div><div class='del'>- *  requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable</div><div class='add'>+ *  requests. -EALREADY is returned if primary disable</div><div class='ctx'>  *  bit hasn't caused the primary requests to be disabled, else 0</div><div class='ctx'>  *  is returned signifying primary requests disabled.</div><div class='ctx'>  **/</div><div class='hunk'>@@ -2575,7 +2562,7 @@ gio_disable_fail:</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");</div><div class='del'>-	return IXGBE_ERR_PRIMARY_REQUESTS_PENDING;</div><div class='add'>+	return -EALREADY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2600,7 +2587,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 		 * SW_FW_SYNC bits (not just NVM)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (ixgbe_get_eeprom_semaphore(hw))</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);</div><div class='ctx'> 		if (!(gssr &amp; (fwmask | swmask))) {</div><div class='hunk'>@@ -2620,7 +2607,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 		ixgbe_release_swfw_sync(hw, gssr &amp; (fwmask | swmask));</div><div class='ctx'> </div><div class='ctx'> 	usleep_range(5000, 10000);</div><div class='del'>-	return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+	return -EBUSY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2757,7 +2744,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Link must be up to auto-blink the LEDs;</div><div class='hunk'>@@ -2803,7 +2790,7 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	ret_val = hw-&gt;mac.ops.prot_autoc_read(hw, &amp;locked, &amp;autoc_reg);</div><div class='ctx'> 	if (ret_val)</div><div class='hunk'>@@ -2963,7 +2950,7 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (rar &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));</div><div class='hunk'>@@ -3014,7 +3001,7 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)</div><div class='ctx'> 	/* Make sure we are using a valid rar index range */</div><div class='ctx'> 	if (rar &gt;= rar_entries) {</div><div class='ctx'> 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (vmdq &lt; 32) {</div><div class='hunk'>@@ -3091,7 +3078,7 @@ static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)</div><div class='ctx'> 	 * will simply bypass the VLVF if there are no entries present in the</div><div class='ctx'> 	 * VLVF that contain our VLAN</div><div class='ctx'> 	 */</div><div class='del'>-	first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;</div><div class='add'>+	first_empty_slot = vlvf_bypass ? -ENOSPC : 0;</div><div class='ctx'> </div><div class='ctx'> 	/* add VLAN enable bit for comparison */</div><div class='ctx'> 	vlan |= IXGBE_VLVF_VIEN;</div><div class='hunk'>@@ -3115,7 +3102,7 @@ static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)</div><div class='ctx'> 	if (!first_empty_slot)</div><div class='ctx'> 		hw_dbg(hw, "No space in VLVF.\n");</div><div class='ctx'> </div><div class='del'>-	return first_empty_slot ? : IXGBE_ERR_NO_SPACE;</div><div class='add'>+	return first_empty_slot ? : -ENOSPC;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3135,7 +3122,7 @@ s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,</div><div class='ctx'> 	s32 vlvf_index;</div><div class='ctx'> </div><div class='ctx'> 	if ((vlan &gt; 4095) || (vind &gt; 63))</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * this is a 2 part operation - first the VFTA, then the</div><div class='hunk'>@@ -3611,7 +3598,8 @@ u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)</div><div class='ctx'>  *</div><div class='ctx'>  *  Communicates with the manageability block. On success return 0</div><div class='ctx'>  *  else returns semaphore error when encountering an error acquiring</div><div class='del'>- *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.</div><div class='add'>+ *  semaphore, -EINVAL when incorrect parameters passed or -EIO when</div><div class='add'>+ *  command fails.</div><div class='ctx'>  *</div><div class='ctx'>  *  This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held</div><div class='ctx'>  *  by the caller.</div><div class='hunk'>@@ -3624,7 +3612,7 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,</div><div class='ctx'> </div><div class='ctx'> 	if (!length || length &gt; IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {</div><div class='ctx'> 		hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);</div><div class='del'>-		return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Set bit 9 of FWSTS clearing FW reset indication */</div><div class='hunk'>@@ -3635,13 +3623,13 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,</div><div class='ctx'> 	hicr = IXGBE_READ_REG(hw, IXGBE_HICR);</div><div class='ctx'> 	if (!(hicr &amp; IXGBE_HICR_EN)) {</div><div class='ctx'> 		hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");</div><div class='del'>-		return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Calculate length in DWORDs. We must be DWORD aligned */</div><div class='ctx'> 	if (length % sizeof(u32)) {</div><div class='ctx'> 		hw_dbg(hw, "Buffer length failure, not aligned to dword");</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dword_len = length &gt;&gt; 2;</div><div class='hunk'>@@ -3666,7 +3654,7 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,</div><div class='ctx'> 	/* Check command successful completion. */</div><div class='ctx'> 	if ((timeout &amp;&amp; i == timeout) ||</div><div class='ctx'> 	    !(IXGBE_READ_REG(hw, IXGBE_HICR) &amp; IXGBE_HICR_SV))</div><div class='del'>-		return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3686,7 +3674,7 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,</div><div class='ctx'>  *  in these cases.</div><div class='ctx'>  *</div><div class='ctx'>  *  Communicates with the manageability block.  On success return 0</div><div class='del'>- *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.</div><div class='add'>+ *  else return -EIO or -EINVAL.</div><div class='ctx'>  **/</div><div class='ctx'> s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,</div><div class='ctx'> 				 u32 length, u32 timeout,</div><div class='hunk'>@@ -3701,7 +3689,7 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,</div><div class='ctx'> </div><div class='ctx'> 	if (!length || length &gt; IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {</div><div class='ctx'> 		hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);</div><div class='del'>-		return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> 	/* Take management host interface semaphore */</div><div class='ctx'> 	status = hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);</div><div class='hunk'>@@ -3731,7 +3719,7 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,</div><div class='ctx'> </div><div class='ctx'> 	if (length &lt; round_up(buf_len, 4) + hdr_size) {</div><div class='ctx'> 		hw_dbg(hw, "Buffer not large enough for reply message.\n");</div><div class='del'>-		status = IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		goto rel_out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3762,8 +3750,8 @@ rel_out:</div><div class='ctx'>  *</div><div class='ctx'>  *  Sends driver version number to firmware through the manageability</div><div class='ctx'>  *  block.  On success return 0</div><div class='del'>- *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring</div><div class='del'>- *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.</div><div class='add'>+ *  else returns -EBUSY when encountering an error acquiring</div><div class='add'>+ *  semaphore or -EIO when command fails.</div><div class='ctx'>  **/</div><div class='ctx'> s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,</div><div class='ctx'> 				 u8 build, u8 sub, __always_unused u16 len,</div><div class='hunk'>@@ -3799,7 +3787,7 @@ s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,</div><div class='ctx'> 		    FW_CEM_RESP_STATUS_SUCCESS)</div><div class='ctx'> 			ret_val = 0;</div><div class='ctx'> 		else</div><div class='del'>-			ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+			ret_val = -EIO;</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3897,14 +3885,14 @@ static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))</div><div class='del'>-		return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	status = hw-&gt;eeprom.ops.read(hw, *ets_offset, ets_cfg);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	if ((*ets_cfg &amp; IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)</div><div class='del'>-		return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -3927,7 +3915,7 @@ s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Only support thermal sensors attached to physical port 0 */</div><div class='ctx'> 	if ((IXGBE_READ_REG(hw, IXGBE_STATUS) &amp; IXGBE_STATUS_LAN_ID_1))</div><div class='del'>-		return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_get_ets_data(hw, &amp;ets_cfg, &amp;ets_offset);</div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -3946,10 +3934,10 @@ s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		if (status)</div><div class='ctx'> 			return status;</div><div class='ctx'> </div><div class='del'>-		sensor_index = ((ets_sensor &amp; IXGBE_ETS_DATA_INDEX_MASK) &gt;&gt;</div><div class='del'>-				IXGBE_ETS_DATA_INDEX_SHIFT);</div><div class='del'>-		sensor_location = ((ets_sensor &amp; IXGBE_ETS_DATA_LOC_MASK) &gt;&gt;</div><div class='del'>-				   IXGBE_ETS_DATA_LOC_SHIFT);</div><div class='add'>+		sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK,</div><div class='add'>+					 ets_sensor);</div><div class='add'>+		sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK,</div><div class='add'>+					    ets_sensor);</div><div class='ctx'> </div><div class='ctx'> 		if (sensor_location != 0) {</div><div class='ctx'> 			status = hw-&gt;phy.ops.read_i2c_byte(hw,</div><div class='hunk'>@@ -3987,14 +3975,13 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Only support thermal sensors attached to physical port 0 */</div><div class='ctx'> 	if ((IXGBE_READ_REG(hw, IXGBE_STATUS) &amp; IXGBE_STATUS_LAN_ID_1))</div><div class='del'>-		return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_get_ets_data(hw, &amp;ets_cfg, &amp;ets_offset);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='del'>-	low_thresh_delta = ((ets_cfg &amp; IXGBE_ETS_LTHRES_DELTA_MASK) &gt;&gt;</div><div class='del'>-			     IXGBE_ETS_LTHRES_DELTA_SHIFT);</div><div class='add'>+	low_thresh_delta = FIELD_GET(IXGBE_ETS_LTHRES_DELTA_MASK, ets_cfg);</div><div class='ctx'> 	num_sensors = (ets_cfg &amp; IXGBE_ETS_NUM_SENSORS_MASK);</div><div class='ctx'> 	if (num_sensors &gt; IXGBE_MAX_SENSORS)</div><div class='ctx'> 		num_sensors = IXGBE_MAX_SENSORS;</div><div class='hunk'>@@ -4008,10 +3995,10 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 			       ets_offset + 1 + i);</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='del'>-		sensor_index = ((ets_sensor &amp; IXGBE_ETS_DATA_INDEX_MASK) &gt;&gt;</div><div class='del'>-				IXGBE_ETS_DATA_INDEX_SHIFT);</div><div class='del'>-		sensor_location = ((ets_sensor &amp; IXGBE_ETS_DATA_LOC_MASK) &gt;&gt;</div><div class='del'>-				   IXGBE_ETS_DATA_LOC_SHIFT);</div><div class='add'>+		sensor_index = FIELD_GET(IXGBE_ETS_DATA_INDEX_MASK,</div><div class='add'>+					 ets_sensor);</div><div class='add'>+		sensor_location = FIELD_GET(IXGBE_ETS_DATA_LOC_MASK,</div><div class='add'>+					    ets_sensor);</div><div class='ctx'> 		therm_limit = ets_sensor &amp; IXGBE_ETS_DATA_HTHRESH_MASK;</div><div class='ctx'> </div><div class='ctx'> 		hw-&gt;phy.ops.write_i2c_byte(hw,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c<br/>index 4dd897806fa5..9a63457712c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c</a></div><div class='hunk'>@@ -1413,12 +1413,11 @@ static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,</div><div class='ctx'> 	switch (stringset) {</div><div class='ctx'> 	case ETH_SS_TEST:</div><div class='ctx'> 		for (i = 0; i &lt; IXGBE_TEST_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s", ixgbe_gstrings_test[i]);</div><div class='add'>+			ethtool_puts(&amp;p, ixgbe_gstrings_test[i]);</div><div class='ctx'> 		break;</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; IXGBE_GLOBAL_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, "%s",</div><div class='del'>-					ixgbe_gstrings_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, ixgbe_gstrings_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; netdev-&gt;num_tx_queues; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_packets", i);</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_bytes", i);</div><div class='hunk'>@@ -3108,35 +3107,37 @@ static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)</div><div class='ctx'> 		indir[i] = adapter-&gt;rss_indir_tbl[i] &amp; rss_m;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int ixgbe_get_rxfh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	if (indir)</div><div class='del'>-		ixgbe_get_reta(adapter, indir);</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		ixgbe_get_reta(adapter, rxfh-&gt;indir);</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, adapter-&gt;rss_key, ixgbe_get_rxfh_key_size(netdev));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, adapter-&gt;rss_key,</div><div class='add'>+		       ixgbe_get_rxfh_key_size(netdev));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int ixgbe_set_rxfh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> 	u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/* Fill out the redirection table */</div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		int max_queues = min_t(int, adapter-&gt;num_rx_queues,</div><div class='ctx'> 				       ixgbe_rss_indir_tbl_max(adapter));</div><div class='ctx'> </div><div class='hunk'>@@ -3147,18 +3148,19 @@ static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='ctx'> </div><div class='ctx'> 		/* Verify user input. */</div><div class='ctx'> 		for (i = 0; i &lt; reta_entries; i++)</div><div class='del'>-			if (indir[i] &gt;= max_queues)</div><div class='add'>+			if (rxfh-&gt;indir[i] &gt;= max_queues)</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; reta_entries; i++)</div><div class='del'>-			adapter-&gt;rss_indir_tbl[i] = indir[i];</div><div class='add'>+			adapter-&gt;rss_indir_tbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 		ixgbe_store_reta(adapter);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Fill out the rss hash key */</div><div class='del'>-	if (key) {</div><div class='del'>-		memcpy(adapter-&gt;rss_key, key, ixgbe_get_rxfh_key_size(netdev));</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(adapter-&gt;rss_key, rxfh-&gt;key,</div><div class='add'>+		       ixgbe_get_rxfh_key_size(netdev));</div><div class='ctx'> 		ixgbe_store_key(adapter);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3370,7 +3372,7 @@ static int ixgbe_get_module_eeprom(struct net_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_adapter *adapter = netdev_priv(dev);</div><div class='ctx'> 	struct ixgbe_hw *hw = &amp;adapter-&gt;hw;</div><div class='del'>-	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;</div><div class='add'>+	s32 status = -EFAULT;</div><div class='ctx'> 	u8 databyte = 0xFF;</div><div class='ctx'> 	int i = 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c<br/>index 7311bd545acf..18d63c8c2ff4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c</a></div><div class='hunk'>@@ -670,8 +670,8 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)</div><div class='ctx'> 			int fcoe_i_h = fcoe-&gt;offset + ((i + fcreta_size) %</div><div class='ctx'> 							fcoe-&gt;indices);</div><div class='ctx'> 			fcoe_q_h = adapter-&gt;rx_ring[fcoe_i_h]-&gt;reg_idx;</div><div class='del'>-			fcoe_q_h = (fcoe_q_h &lt;&lt; IXGBE_FCRETA_ENTRY_HIGH_SHIFT) &amp;</div><div class='del'>-				   IXGBE_FCRETA_ENTRY_HIGH_MASK;</div><div class='add'>+			fcoe_q_h = FIELD_PREP(IXGBE_FCRETA_ENTRY_HIGH_MASK,</div><div class='add'>+					      fcoe_q_h);</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		fcoe_i = fcoe-&gt;offset + (i % fcoe-&gt;indices);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c<br/>index 94bde2cad0f4..bd541527c8c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_main.c</a></div><div class='hunk'>@@ -2756,7 +2756,6 @@ static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_hw *hw = &amp;adapter-&gt;hw;</div><div class='ctx'> 	u32 eicr = adapter-&gt;interrupt_event;</div><div class='del'>-	s32 rc;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(__IXGBE_DOWN, &amp;adapter-&gt;state))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -2790,14 +2789,13 @@ static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Check if this is not due to overtemp */</div><div class='del'>-		if (hw-&gt;phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)</div><div class='add'>+		if (!hw-&gt;phy.ops.check_overtemp(hw))</div><div class='ctx'> 			return;</div><div class='ctx'> </div><div class='ctx'> 		break;</div><div class='ctx'> 	case IXGBE_DEV_ID_X550EM_A_1G_T:</div><div class='ctx'> 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:</div><div class='del'>-		rc = hw-&gt;phy.ops.check_overtemp(hw);</div><div class='del'>-		if (rc != IXGBE_ERR_OVERTEMP)</div><div class='add'>+		if (!hw-&gt;phy.ops.check_overtemp(hw))</div><div class='ctx'> 			return;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -5512,7 +5510,7 @@ static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u32 speed;</div><div class='ctx'> 	bool autoneg, link_up = false;</div><div class='del'>-	int ret = IXGBE_ERR_LINK_SETUP;</div><div class='add'>+	int ret = -EIO;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.check_link)</div><div class='ctx'> 		ret = hw-&gt;mac.ops.check_link(hw, &amp;speed, &amp;link_up, false);</div><div class='hunk'>@@ -5983,13 +5981,13 @@ void ixgbe_reset(struct ixgbe_adapter *adapter)</div><div class='ctx'> 	err = hw-&gt;mac.ops.init_hw(hw);</div><div class='ctx'> 	switch (err) {</div><div class='ctx'> 	case 0:</div><div class='del'>-	case IXGBE_ERR_SFP_NOT_PRESENT:</div><div class='del'>-	case IXGBE_ERR_SFP_NOT_SUPPORTED:</div><div class='add'>+	case -ENOENT:</div><div class='add'>+	case -EOPNOTSUPP:</div><div class='ctx'> 		break;</div><div class='del'>-	case IXGBE_ERR_PRIMARY_REQUESTS_PENDING:</div><div class='add'>+	case -EALREADY:</div><div class='ctx'> 		e_dev_err("primary disable timed out\n");</div><div class='ctx'> 		break;</div><div class='del'>-	case IXGBE_ERR_EEPROM_VERSION:</div><div class='add'>+	case -EACCES:</div><div class='ctx'> 		/* We are running on a pre-production device, log a warning */</div><div class='ctx'> 		e_dev_warn("This device is a pre-production adapter/LOM. "</div><div class='ctx'> 			   "Please be aware there may be issues associated with "</div><div class='hunk'>@@ -7829,10 +7827,10 @@ static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> 	adapter-&gt;sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;</div><div class='ctx'> </div><div class='ctx'> 	err = hw-&gt;phy.ops.identify_sfp(hw);</div><div class='del'>-	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+	if (err == -EOPNOTSUPP)</div><div class='ctx'> 		goto sfp_out;</div><div class='ctx'> </div><div class='del'>-	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {</div><div class='add'>+	if (err == -ENOENT) {</div><div class='ctx'> 		/* If no cable is present, then we need to reset</div><div class='ctx'> 		 * the next time we find a good cable. */</div><div class='ctx'> 		adapter-&gt;flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;</div><div class='hunk'>@@ -7858,7 +7856,7 @@ static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> 	else</div><div class='ctx'> 		err = hw-&gt;mac.ops.setup_sfp(hw);</div><div class='ctx'> </div><div class='del'>-	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+	if (err == -EOPNOTSUPP)</div><div class='ctx'> 		goto sfp_out;</div><div class='ctx'> </div><div class='ctx'> 	adapter-&gt;flags |= IXGBE_FLAG_NEED_LINK_CONFIG;</div><div class='hunk'>@@ -7867,8 +7865,8 @@ static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> sfp_out:</div><div class='ctx'> 	clear_bit(__IXGBE_IN_SFP_INIT, &amp;adapter-&gt;state);</div><div class='ctx'> </div><div class='del'>-	if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &amp;&amp;</div><div class='del'>-	    (adapter-&gt;netdev-&gt;reg_state == NETREG_REGISTERED)) {</div><div class='add'>+	if (err == -EOPNOTSUPP &amp;&amp;</div><div class='add'>+	    adapter-&gt;netdev-&gt;reg_state == NETREG_REGISTERED) {</div><div class='ctx'> 		e_dev_err("failed to initialize because an unsupported "</div><div class='ctx'> 			  "SFP+ module type was detected.\n");</div><div class='ctx'> 		e_dev_err("Reload the driver after installing a "</div><div class='hunk'>@@ -7938,7 +7936,7 @@ static void ixgbe_service_timer(struct timer_list *t)</div><div class='ctx'> static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_hw *hw = &amp;adapter-&gt;hw;</div><div class='del'>-	u32 status;</div><div class='add'>+	bool overtemp;</div><div class='ctx'> </div><div class='ctx'> 	if (!(adapter-&gt;flags2 &amp; IXGBE_FLAG2_PHY_INTERRUPT))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -7948,11 +7946,9 @@ static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)</div><div class='ctx'> 	if (!hw-&gt;phy.ops.handle_lasi)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	status = hw-&gt;phy.ops.handle_lasi(&amp;adapter-&gt;hw);</div><div class='del'>-	if (status != IXGBE_ERR_OVERTEMP)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	e_crit(drv, "%s\n", ixgbe_overheat_msg);</div><div class='add'>+	hw-&gt;phy.ops.handle_lasi(&amp;adapter-&gt;hw, &amp;overtemp);</div><div class='add'>+	if (overtemp)</div><div class='add'>+		e_crit(drv, "%s\n", ixgbe_overheat_msg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)</div><div class='hunk'>@@ -10922,9 +10918,9 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	err = hw-&gt;mac.ops.reset_hw(hw);</div><div class='ctx'> 	hw-&gt;phy.reset_if_overtemp = false;</div><div class='ctx'> 	ixgbe_set_eee_capable(adapter);</div><div class='del'>-	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {</div><div class='add'>+	if (err == -ENOENT) {</div><div class='ctx'> 		err = 0;</div><div class='del'>-	} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {</div><div class='add'>+	} else if (err == -EOPNOTSUPP) {</div><div class='ctx'> 		e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");</div><div class='ctx'> 		e_dev_err("Reload the driver after installing a supported module.\n");</div><div class='ctx'> 		goto err_sw_init;</div><div class='hunk'>@@ -11143,7 +11139,7 @@ skip_sriov:</div><div class='ctx'> </div><div class='ctx'> 	/* reset the hardware with the new settings */</div><div class='ctx'> 	err = hw-&gt;mac.ops.start_hw(hw);</div><div class='del'>-	if (err == IXGBE_ERR_EEPROM_VERSION) {</div><div class='add'>+	if (err == -EACCES) {</div><div class='ctx'> 		/* We are running on a pre-production device, log a warning */</div><div class='ctx'> 		e_dev_warn("This device is a pre-production adapter/LOM. "</div><div class='ctx'> 			   "Please be aware there may be issues associated "</div><div class='hunk'>@@ -11371,7 +11367,7 @@ static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,</div><div class='ctx'> 	if ((pf_func &amp; 1) == (pdev-&gt;devfn &amp; 1)) {</div><div class='ctx'> 		unsigned int device_id;</div><div class='ctx'> </div><div class='del'>-		vf = (req_id &amp; 0x7F) &gt;&gt; 1;</div><div class='add'>+		vf = FIELD_GET(0x7F, req_id);</div><div class='ctx'> 		e_dev_err("VF %d has caused a PCIe error\n", vf);</div><div class='ctx'> 		e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "</div><div class='ctx'> 				"%8.8x\tdw3: %8.8x\n",</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c<br/>index 5679293e53f7..fe7ef5773369 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c</a></div><div class='hunk'>@@ -24,7 +24,7 @@ s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)</div><div class='ctx'> 		size = mbx-&gt;size;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return mbx-&gt;ops-&gt;read(hw, msg, size, mbx_id);</div><div class='ctx'> }</div><div class='hunk'>@@ -43,10 +43,10 @@ s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)</div><div class='ctx'> 	struct ixgbe_mbx_info *mbx = &amp;hw-&gt;mbx;</div><div class='ctx'> </div><div class='ctx'> 	if (size &gt; mbx-&gt;size)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return mbx-&gt;ops-&gt;write(hw, msg, size, mbx_id);</div><div class='ctx'> }</div><div class='hunk'>@@ -63,7 +63,7 @@ s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)</div><div class='ctx'> 	struct ixgbe_mbx_info *mbx = &amp;hw-&gt;mbx;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return mbx-&gt;ops-&gt;check_for_msg(hw, mbx_id);</div><div class='ctx'> }</div><div class='hunk'>@@ -80,7 +80,7 @@ s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)</div><div class='ctx'> 	struct ixgbe_mbx_info *mbx = &amp;hw-&gt;mbx;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return mbx-&gt;ops-&gt;check_for_ack(hw, mbx_id);</div><div class='ctx'> }</div><div class='hunk'>@@ -97,7 +97,7 @@ s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)</div><div class='ctx'> 	struct ixgbe_mbx_info *mbx = &amp;hw-&gt;mbx;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	return mbx-&gt;ops-&gt;check_for_rst(hw, mbx_id);</div><div class='ctx'> }</div><div class='hunk'>@@ -115,12 +115,12 @@ static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)</div><div class='ctx'> 	int countdown = mbx-&gt;timeout;</div><div class='ctx'> </div><div class='ctx'> 	if (!countdown || !mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	while (mbx-&gt;ops-&gt;check_for_msg(hw, mbx_id)) {</div><div class='ctx'> 		countdown--;</div><div class='ctx'> 		if (!countdown)</div><div class='del'>-			return IXGBE_ERR_MBX;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		udelay(mbx-&gt;usec_delay);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -140,12 +140,12 @@ static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)</div><div class='ctx'> 	int countdown = mbx-&gt;timeout;</div><div class='ctx'> </div><div class='ctx'> 	if (!countdown || !mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	while (mbx-&gt;ops-&gt;check_for_ack(hw, mbx_id)) {</div><div class='ctx'> 		countdown--;</div><div class='ctx'> 		if (!countdown)</div><div class='del'>-			return IXGBE_ERR_MBX;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		udelay(mbx-&gt;usec_delay);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -169,7 +169,7 @@ static s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,</div><div class='ctx'> 	s32 ret_val;</div><div class='ctx'> </div><div class='ctx'> 	if (!mbx-&gt;ops)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	ret_val = ixgbe_poll_for_msg(hw, mbx_id);</div><div class='ctx'> 	if (ret_val)</div><div class='hunk'>@@ -197,7 +197,7 @@ static s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,</div><div class='ctx'> </div><div class='ctx'> 	/* exit if either we can't write or there isn't a defined timeout */</div><div class='ctx'> 	if (!mbx-&gt;ops || !mbx-&gt;timeout)</div><div class='del'>-		return IXGBE_ERR_MBX;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	/* send msg */</div><div class='ctx'> 	ret_val = mbx-&gt;ops-&gt;write(hw, msg, size, mbx_id);</div><div class='hunk'>@@ -217,7 +217,7 @@ static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_MBX;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -238,7 +238,7 @@ static s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_MBX;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -259,7 +259,7 @@ static s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_MBX;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -295,7 +295,7 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_MBX;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -317,7 +317,7 @@ static s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)</div><div class='ctx'> 	if (p2v_mailbox &amp; IXGBE_PFMAILBOX_PFU)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_MBX;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h<br/>index 8f4316b19278..6434c190e7a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.h</a></div><div class='hunk'>@@ -7,7 +7,6 @@</div><div class='ctx'> #include "ixgbe_type.h"</div><div class='ctx'> </div><div class='ctx'> #define IXGBE_VFMAILBOX_SIZE        16 /* 16 32 bit words - 64 bytes */</div><div class='del'>-#define IXGBE_ERR_MBX               -100</div><div class='ctx'> </div><div class='ctx'> #define IXGBE_VFMAILBOX             0x002FC</div><div class='ctx'> #define IXGBE_VFMBMEM               0x00200</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c<br/>index 689470c1e8ad..f28140a05f09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c</a></div><div class='hunk'>@@ -102,7 +102,7 @@ s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,</div><div class='ctx'> 	csum = ~csum;</div><div class='ctx'> 	do {</div><div class='ctx'> 		if (lock &amp;&amp; hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask))</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> 		ixgbe_i2c_start(hw);</div><div class='ctx'> 		/* Device Address and write indication */</div><div class='ctx'> 		if (ixgbe_out_i2c_byte_ack(hw, addr))</div><div class='hunk'>@@ -150,7 +150,7 @@ fail:</div><div class='ctx'> 			hw_dbg(hw, "I2C byte read combined error.\n");</div><div class='ctx'> 	} while (retry &lt; max_retry);</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_I2C;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -179,7 +179,7 @@ s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,</div><div class='ctx'> 	csum = ~csum;</div><div class='ctx'> 	do {</div><div class='ctx'> 		if (lock &amp;&amp; hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask))</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> 		ixgbe_i2c_start(hw);</div><div class='ctx'> 		/* Device Address and write indication */</div><div class='ctx'> 		if (ixgbe_out_i2c_byte_ack(hw, addr))</div><div class='hunk'>@@ -215,7 +215,7 @@ fail:</div><div class='ctx'> 			hw_dbg(hw, "I2C byte write combined error.\n");</div><div class='ctx'> 	} while (retry &lt; max_retry);</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_I2C;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -262,8 +262,8 @@ static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)</div><div class='ctx'>  **/</div><div class='ctx'> s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='add'>+	u32 status = -EFAULT;</div><div class='ctx'> 	u32 phy_addr;</div><div class='del'>-	u32 status = IXGBE_ERR_PHY_ADDR_INVALID;</div><div class='ctx'> </div><div class='ctx'> 	if (!hw-&gt;phy.phy_semaphore_mask) {</div><div class='ctx'> 		if (hw-&gt;bus.lan_id)</div><div class='hunk'>@@ -276,13 +276,12 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.nw_mng_if_sel) {</div><div class='del'>-		phy_addr = (hw-&gt;phy.nw_mng_if_sel &amp;</div><div class='del'>-			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) &gt;&gt;</div><div class='del'>-			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;</div><div class='add'>+		phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,</div><div class='add'>+				     hw-&gt;phy.nw_mng_if_sel);</div><div class='ctx'> 		if (ixgbe_probe_phy(hw, phy_addr))</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		else</div><div class='del'>-			return IXGBE_ERR_PHY_ADDR_INVALID;</div><div class='add'>+			return -EFAULT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (phy_addr = 0; phy_addr &lt; IXGBE_MAX_PHY_ADDR; phy_addr++) {</div><div class='hunk'>@@ -408,8 +407,7 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	/* Don't reset PHY if it's shut down due to overtemp. */</div><div class='del'>-	if (!hw-&gt;phy.reset_if_overtemp &amp;&amp;</div><div class='del'>-	    (IXGBE_ERR_OVERTEMP == hw-&gt;phy.ops.check_overtemp(hw)))</div><div class='add'>+	if (!hw-&gt;phy.reset_if_overtemp &amp;&amp; hw-&gt;phy.ops.check_overtemp(hw))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Blocked by MNG FW so bail */</div><div class='hunk'>@@ -457,7 +455,7 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl &amp; MDIO_CTRL1_RESET) {</div><div class='ctx'> 		hw_dbg(hw, "PHY reset polling failed to complete.\n");</div><div class='del'>-		return IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -500,7 +498,7 @@ s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_MSCA_MDI_COMMAND) != 0) {</div><div class='ctx'> 		hw_dbg(hw, "PHY address command did not complete.\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Address cycle complete, setup and write the read</div><div class='hunk'>@@ -527,7 +525,7 @@ s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_MSCA_MDI_COMMAND) != 0) {</div><div class='ctx'> 		hw_dbg(hw, "PHY read command didn't complete\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Read operation is complete.  Get the data</div><div class='hunk'>@@ -559,7 +557,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 						phy_data);</div><div class='ctx'> 		hw-&gt;mac.ops.release_swfw_sync(hw, gssr);</div><div class='ctx'> 	} else {</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -604,7 +602,7 @@ s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_MSCA_MDI_COMMAND) != 0) {</div><div class='ctx'> 		hw_dbg(hw, "PHY address cmd didn't complete\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='hunk'>@@ -632,7 +630,7 @@ s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_MSCA_MDI_COMMAND) != 0) {</div><div class='ctx'> 		hw_dbg(hw, "PHY write cmd didn't complete\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -657,7 +655,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 						 phy_data);</div><div class='ctx'> 		hw-&gt;mac.ops.release_swfw_sync(hw, gssr);</div><div class='ctx'> 	} else {</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -1430,7 +1428,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if ((phy_data &amp; MDIO_CTRL1_RESET) != 0) {</div><div class='ctx'> 		hw_dbg(hw, "PHY reset did not complete.\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Get init offsets */</div><div class='hunk'>@@ -1448,8 +1446,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)</div><div class='ctx'> 		ret_val = hw-&gt;eeprom.ops.read(hw, data_offset, &amp;eword);</div><div class='ctx'> 		if (ret_val)</div><div class='ctx'> 			goto err_eeprom;</div><div class='del'>-		control = (eword &amp; IXGBE_CONTROL_MASK_NL) &gt;&gt;</div><div class='del'>-			   IXGBE_CONTROL_SHIFT_NL;</div><div class='add'>+		control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword);</div><div class='ctx'> 		edata = eword &amp; IXGBE_DATA_MASK_NL;</div><div class='ctx'> 		switch (control) {</div><div class='ctx'> 		case IXGBE_DELAY_NL:</div><div class='hunk'>@@ -1487,12 +1484,12 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)</div><div class='ctx'> 				hw_dbg(hw, "SOL\n");</div><div class='ctx'> 			} else {</div><div class='ctx'> 				hw_dbg(hw, "Bad control value\n");</div><div class='del'>-				return IXGBE_ERR_PHY;</div><div class='add'>+				return -EIO;</div><div class='ctx'> 			}</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			hw_dbg(hw, "Bad control type\n");</div><div class='del'>-			return IXGBE_ERR_PHY;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1500,7 +1497,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> err_eeprom:</div><div class='ctx'> 	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);</div><div class='del'>-	return IXGBE_ERR_PHY;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1518,10 +1515,10 @@ s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		return ixgbe_identify_qsfp_module_generic(hw);</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw-&gt;phy.sfp_type = ixgbe_sfp_type_not_present;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+	return -ENOENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1546,7 +1543,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {</div><div class='ctx'> 		hw-&gt;phy.sfp_type = ixgbe_sfp_type_not_present;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* LAN ID is needed for sfp_type determination */</div><div class='hunk'>@@ -1561,7 +1558,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {</div><div class='ctx'> 		hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> 	status = hw-&gt;phy.ops.read_i2c_eeprom(hw,</div><div class='ctx'> 					     IXGBE_SFF_1GBE_COMP_CODES,</div><div class='hunk'>@@ -1752,7 +1749,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 	      hw-&gt;phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||</div><div class='ctx'> 	      hw-&gt;phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {</div><div class='ctx'> 		hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Anything else 82598-based is supported */</div><div class='hunk'>@@ -1776,7 +1773,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		}</div><div class='ctx'> 		hw_dbg(hw, "SFP+ module not supported\n");</div><div class='ctx'> 		hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -1786,7 +1783,7 @@ err_read_i2c_eeprom:</div><div class='ctx'> 		hw-&gt;phy.id = 0;</div><div class='ctx'> 		hw-&gt;phy.type = ixgbe_phy_unknown;</div><div class='ctx'> 	}</div><div class='del'>-	return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+	return -ENOENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1813,7 +1810,7 @@ static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {</div><div class='ctx'> 		hw-&gt;phy.sfp_type = ixgbe_sfp_type_not_present;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* LAN ID is needed for sfp_type determination */</div><div class='hunk'>@@ -1827,7 +1824,7 @@ static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {</div><div class='ctx'> 		hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;phy.id = identifier;</div><div class='hunk'>@@ -1895,7 +1892,7 @@ static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* unsupported module type */</div><div class='ctx'> 			hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-			return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1955,7 +1952,7 @@ static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)</div><div class='ctx'> 			}</div><div class='ctx'> 			hw_dbg(hw, "QSFP module not supported\n");</div><div class='ctx'> 			hw-&gt;phy.type = ixgbe_phy_sfp_unsupported;</div><div class='del'>-			return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='ctx'> 		}</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1966,7 +1963,7 @@ err_read_i2c_eeprom:</div><div class='ctx'> 	hw-&gt;phy.id = 0;</div><div class='ctx'> 	hw-&gt;phy.type = ixgbe_phy_unknown;</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+	return -ENOENT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1986,14 +1983,14 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,</div><div class='ctx'> 	u16 sfp_type = hw-&gt;phy.sfp_type;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.sfp_type == ixgbe_sfp_type_unknown)</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.sfp_type == ixgbe_sfp_type_not_present)</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> </div><div class='ctx'> 	if ((hw-&gt;device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &amp;&amp;</div><div class='ctx'> 	    (hw-&gt;phy.sfp_type == ixgbe_sfp_type_da_cu))</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Limiting active cables and 1G Phys must be initialized as</div><div class='hunk'>@@ -2014,11 +2011,11 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,</div><div class='ctx'> 	if (hw-&gt;eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {</div><div class='ctx'> 		hw_err(hw, "eeprom read at %d failed\n",</div><div class='ctx'> 		       IXGBE_PHY_INIT_OFFSET_NL);</div><div class='del'>-		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if ((!*list_offset) || (*list_offset == 0xFFFF))</div><div class='del'>-		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	/* Shift offset to first ID word */</div><div class='ctx'> 	(*list_offset)++;</div><div class='hunk'>@@ -2037,7 +2034,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,</div><div class='ctx'> 				goto err_phy;</div><div class='ctx'> 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {</div><div class='ctx'> 				hw_dbg(hw, "SFP+ module not supported\n");</div><div class='del'>-				return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+				return -EOPNOTSUPP;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='hunk'>@@ -2050,14 +2047,14 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {</div><div class='ctx'> 		hw_dbg(hw, "No matching SFP+ module found\n");</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_phy:</div><div class='ctx'> 	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);</div><div class='del'>-	return IXGBE_ERR_PHY;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2152,7 +2149,7 @@ static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		if (lock &amp;&amp; hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask))</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		ixgbe_i2c_start(hw);</div><div class='ctx'> </div><div class='hunk'>@@ -2268,7 +2265,7 @@ static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='ctx'> 	u32 swfw_mask = hw-&gt;phy.phy_semaphore_mask;</div><div class='ctx'> </div><div class='ctx'> 	if (lock &amp;&amp; hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	do {</div><div class='ctx'> 		ixgbe_i2c_start(hw);</div><div class='hunk'>@@ -2510,7 +2507,7 @@ static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (ack == 1) {</div><div class='ctx'> 		hw_dbg(hw, "I2C ack was not received.\n");</div><div class='del'>-		status = IXGBE_ERR_I2C;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ixgbe_lower_i2c_clk(hw, &amp;i2cctl);</div><div class='hunk'>@@ -2582,7 +2579,7 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)</div><div class='ctx'> 		udelay(IXGBE_I2C_T_LOW);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		hw_dbg(hw, "I2C data was not set to %X\n", data);</div><div class='del'>-		return IXGBE_ERR_I2C;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2678,7 +2675,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)</div><div class='ctx'> 	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));</div><div class='ctx'> 	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {</div><div class='ctx'> 		hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);</div><div class='del'>-		return IXGBE_ERR_I2C;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -2748,22 +2745,24 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)</div><div class='ctx'>  *  @hw: pointer to hardware structure</div><div class='ctx'>  *</div><div class='ctx'>  *  Checks if the LASI temp alarm status was triggered due to overtemp</div><div class='add'>+ *</div><div class='add'>+ *  Return true when an overtemp event detected, otherwise false.</div><div class='ctx'>  **/</div><div class='del'>-s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)</div><div class='add'>+bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u16 phy_data = 0;</div><div class='add'>+	u32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;device_id != IXGBE_DEV_ID_82599_T3_LOM)</div><div class='del'>-		return 0;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* Check that the LASI temp alarm status was triggered */</div><div class='del'>-	hw-&gt;phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,</div><div class='del'>-			     MDIO_MMD_PMAPMD, &amp;phy_data);</div><div class='del'>-</div><div class='del'>-	if (!(phy_data &amp; IXGBE_TN_LASI_STATUS_TEMP_ALARM))</div><div class='del'>-		return 0;</div><div class='add'>+	status = hw-&gt;phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,</div><div class='add'>+				      MDIO_MMD_PMAPMD, &amp;phy_data);</div><div class='add'>+	if (status)</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_OVERTEMP;</div><div class='add'>+	return !!(phy_data &amp; IXGBE_TN_LASI_STATUS_TEMP_ALARM);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /** ixgbe_set_copper_phy_power - Control power for copper phy</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h<br/>index 6544c4539c0d..ef72729d7c93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h</a></div><div class='hunk'>@@ -155,7 +155,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);</div><div class='ctx'> s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,</div><div class='ctx'> 					u16 *list_offset,</div><div class='ctx'> 					u16 *data_offset);</div><div class='del'>-s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);</div><div class='add'>+bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);</div><div class='ctx'> s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='ctx'> 				u8 dev_addr, u8 *data);</div><div class='ctx'> s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c<br/>index 9cfdfa8a4355..7299a830f6e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c</a></div><div class='hunk'>@@ -363,8 +363,7 @@ int ixgbe_pci_sriov_configure(struct pci_dev *dev, int num_vfs)</div><div class='ctx'> static int ixgbe_set_vf_multicasts(struct ixgbe_adapter *adapter,</div><div class='ctx'> 				   u32 *msgbuf, u32 vf)</div><div class='ctx'> {</div><div class='del'>-	int entries = (msgbuf[0] &amp; IXGBE_VT_MSGINFO_MASK)</div><div class='del'>-		       &gt;&gt; IXGBE_VT_MSGINFO_SHIFT;</div><div class='add'>+	int entries = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]);</div><div class='ctx'> 	u16 *hash_list = (u16 *)&amp;msgbuf[1];</div><div class='ctx'> 	struct vf_data_storage *vfinfo = &amp;adapter-&gt;vfinfo[vf];</div><div class='ctx'> 	struct ixgbe_hw *hw = &amp;adapter-&gt;hw;</div><div class='hunk'>@@ -969,7 +968,7 @@ static int ixgbe_set_vf_mac_addr(struct ixgbe_adapter *adapter,</div><div class='ctx'> static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter,</div><div class='ctx'> 				 u32 *msgbuf, u32 vf)</div><div class='ctx'> {</div><div class='del'>-	u32 add = (msgbuf[0] &amp; IXGBE_VT_MSGINFO_MASK) &gt;&gt; IXGBE_VT_MSGINFO_SHIFT;</div><div class='add'>+	u32 add = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]);</div><div class='ctx'> 	u32 vid = (msgbuf[1] &amp; IXGBE_VLVF_VLANID_MASK);</div><div class='ctx'> 	u8 tcs = adapter-&gt;hw_tcs;</div><div class='ctx'> </div><div class='hunk'>@@ -992,8 +991,7 @@ static int ixgbe_set_vf_macvlan_msg(struct ixgbe_adapter *adapter,</div><div class='ctx'> 				    u32 *msgbuf, u32 vf)</div><div class='ctx'> {</div><div class='ctx'> 	u8 *new_mac = ((u8 *)(&amp;msgbuf[1]));</div><div class='del'>-	int index = (msgbuf[0] &amp; IXGBE_VT_MSGINFO_MASK) &gt;&gt;</div><div class='del'>-		    IXGBE_VT_MSGINFO_SHIFT;</div><div class='add'>+	int index = FIELD_GET(IXGBE_VT_MSGINFO_MASK, msgbuf[0]);</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (adapter-&gt;vfinfo[vf].pf_set_mac &amp;&amp; !adapter-&gt;vfinfo[vf].trusted &amp;&amp;</div><div class='hunk'>@@ -1327,7 +1325,7 @@ static int ixgbe_rcv_msg_from_vf(struct ixgbe_adapter *adapter, u32 vf)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		e_err(drv, "Unhandled Msg %8.8x\n", msgbuf[0]);</div><div class='del'>-		retval = IXGBE_ERR_MBX;</div><div class='add'>+		retval = -EIO;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1849,5 +1847,6 @@ int ixgbe_ndo_get_vf_config(struct net_device *netdev,</div><div class='ctx'> 	ivi-&gt;spoofchk = adapter-&gt;vfinfo[vf].spoofchk_enabled;</div><div class='ctx'> 	ivi-&gt;rss_query_en = adapter-&gt;vfinfo[vf].rss_query_enabled;</div><div class='ctx'> 	ivi-&gt;trusted = adapter-&gt;vfinfo[vf].trusted;</div><div class='add'>+	ivi-&gt;linkstate = adapter-&gt;vfinfo[vf].link_state;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h<br/>index 2b00db92b08f..61b9774b3d31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_type.h</a></div><div class='hunk'>@@ -3509,10 +3509,10 @@ struct ixgbe_phy_operations {</div><div class='ctx'> 	s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);</div><div class='ctx'> 	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);</div><div class='ctx'> 	s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);</div><div class='del'>-	s32 (*check_overtemp)(struct ixgbe_hw *);</div><div class='add'>+	bool (*check_overtemp)(struct ixgbe_hw *);</div><div class='ctx'> 	s32 (*set_phy_power)(struct ixgbe_hw *, bool on);</div><div class='ctx'> 	s32 (*enter_lplu)(struct ixgbe_hw *);</div><div class='del'>-	s32 (*handle_lasi)(struct ixgbe_hw *hw);</div><div class='add'>+	s32 (*handle_lasi)(struct ixgbe_hw *hw, bool *);</div><div class='ctx'> 	s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,</div><div class='ctx'> 				      u8 *value);</div><div class='ctx'> 	s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,</div><div class='hunk'>@@ -3665,45 +3665,6 @@ struct ixgbe_info {</div><div class='ctx'> 	const u32			*mvals;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-</div><div class='del'>-/* Error Codes */</div><div class='del'>-#define IXGBE_ERR_EEPROM                        -1</div><div class='del'>-#define IXGBE_ERR_EEPROM_CHECKSUM               -2</div><div class='del'>-#define IXGBE_ERR_PHY                           -3</div><div class='del'>-#define IXGBE_ERR_CONFIG                        -4</div><div class='del'>-#define IXGBE_ERR_PARAM                         -5</div><div class='del'>-#define IXGBE_ERR_MAC_TYPE                      -6</div><div class='del'>-#define IXGBE_ERR_UNKNOWN_PHY                   -7</div><div class='del'>-#define IXGBE_ERR_LINK_SETUP                    -8</div><div class='del'>-#define IXGBE_ERR_ADAPTER_STOPPED               -9</div><div class='del'>-#define IXGBE_ERR_INVALID_MAC_ADDR              -10</div><div class='del'>-#define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11</div><div class='del'>-#define IXGBE_ERR_PRIMARY_REQUESTS_PENDING      -12</div><div class='del'>-#define IXGBE_ERR_INVALID_LINK_SETTINGS         -13</div><div class='del'>-#define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14</div><div class='del'>-#define IXGBE_ERR_RESET_FAILED                  -15</div><div class='del'>-#define IXGBE_ERR_SWFW_SYNC                     -16</div><div class='del'>-#define IXGBE_ERR_PHY_ADDR_INVALID              -17</div><div class='del'>-#define IXGBE_ERR_I2C                           -18</div><div class='del'>-#define IXGBE_ERR_SFP_NOT_SUPPORTED             -19</div><div class='del'>-#define IXGBE_ERR_SFP_NOT_PRESENT               -20</div><div class='del'>-#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21</div><div class='del'>-#define IXGBE_ERR_NO_SAN_ADDR_PTR               -22</div><div class='del'>-#define IXGBE_ERR_FDIR_REINIT_FAILED            -23</div><div class='del'>-#define IXGBE_ERR_EEPROM_VERSION                -24</div><div class='del'>-#define IXGBE_ERR_NO_SPACE                      -25</div><div class='del'>-#define IXGBE_ERR_OVERTEMP                      -26</div><div class='del'>-#define IXGBE_ERR_FC_NOT_NEGOTIATED             -27</div><div class='del'>-#define IXGBE_ERR_FC_NOT_SUPPORTED              -28</div><div class='del'>-#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30</div><div class='del'>-#define IXGBE_ERR_PBA_SECTION                   -31</div><div class='del'>-#define IXGBE_ERR_INVALID_ARGUMENT              -32</div><div class='del'>-#define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33</div><div class='del'>-#define IXGBE_ERR_FDIR_CMD_INCOMPLETE		-38</div><div class='del'>-#define IXGBE_ERR_FW_RESP_INVALID		-39</div><div class='del'>-#define IXGBE_ERR_TOKEN_RETRY			-40</div><div class='del'>-#define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF</div><div class='del'>-</div><div class='ctx'> #define IXGBE_FUSES0_GROUP(_i)		(0x11158 + ((_i) * 4))</div><div class='ctx'> #define IXGBE_FUSES0_300MHZ		BIT(5)</div><div class='ctx'> #define IXGBE_FUSES0_REV_MASK		(3u &lt;&lt; 6)</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c<br/>index d5cfb51ff648..57a912e4653f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c</a></div><div class='hunk'>@@ -84,7 +84,7 @@ mac_reset_top:</div><div class='ctx'> 	status = hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		hw_dbg(hw, "semaphore failed with %d", status);</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ctrl = IXGBE_CTRL_RST;</div><div class='hunk'>@@ -103,7 +103,7 @@ mac_reset_top:</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl &amp; IXGBE_CTRL_RST_MASK) {</div><div class='del'>-		status = IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		hw_dbg(hw, "Reset polling failed to complete.\n");</div><div class='ctx'> 	}</div><div class='ctx'> 	msleep(100);</div><div class='hunk'>@@ -187,16 +187,16 @@ s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)</div><div class='ctx'> s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_eeprom_info *eeprom = &amp;hw-&gt;eeprom;</div><div class='del'>-	u32 eec;</div><div class='del'>-	u16 eeprom_size;</div><div class='ctx'> </div><div class='ctx'> 	if (eeprom-&gt;type == ixgbe_eeprom_uninitialized) {</div><div class='add'>+		u16 eeprom_size;</div><div class='add'>+		u32 eec;</div><div class='add'>+</div><div class='ctx'> 		eeprom-&gt;semaphore_delay = 10;</div><div class='ctx'> 		eeprom-&gt;type = ixgbe_flash;</div><div class='ctx'> </div><div class='ctx'> 		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));</div><div class='del'>-		eeprom_size = (u16)((eec &amp; IXGBE_EEC_SIZE) &gt;&gt;</div><div class='del'>-				    IXGBE_EEC_SIZE_SHIFT);</div><div class='add'>+		eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);</div><div class='ctx'> 		eeprom-&gt;word_size = BIT(eeprom_size +</div><div class='ctx'> 					IXGBE_EEPROM_WORD_SIZE_SHIFT);</div><div class='ctx'> </div><div class='hunk'>@@ -220,7 +220,7 @@ static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_read_eerd_generic(hw, offset, data);</div><div class='ctx'> </div><div class='hunk'>@@ -243,7 +243,7 @@ static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);</div><div class='ctx'> </div><div class='hunk'>@@ -264,7 +264,7 @@ static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_write_eewr_generic(hw, offset, data);</div><div class='ctx'> </div><div class='hunk'>@@ -287,7 +287,7 @@ static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);</div><div class='ctx'> </div><div class='hunk'>@@ -324,7 +324,7 @@ static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)</div><div class='ctx'> 	for (i = 0; i &lt; checksum_last_word; i++) {</div><div class='ctx'> 		if (ixgbe_read_eerd_generic(hw, i, &amp;word)) {</div><div class='ctx'> 			hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-			return IXGBE_ERR_EEPROM;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 		checksum += word;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -349,7 +349,7 @@ static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 		if (ixgbe_read_eerd_generic(hw, pointer, &amp;length)) {</div><div class='ctx'> 			hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-			return IXGBE_ERR_EEPROM;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		/* Skip pointer section if length is invalid. */</div><div class='hunk'>@@ -360,7 +360,7 @@ static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)</div><div class='ctx'> 		for (j = pointer + 1; j &lt;= pointer + length; j++) {</div><div class='ctx'> 			if (ixgbe_read_eerd_generic(hw, j, &amp;word)) {</div><div class='ctx'> 				hw_dbg(hw, "EEPROM read failed\n");</div><div class='del'>-				return IXGBE_ERR_EEPROM;</div><div class='add'>+				return -EIO;</div><div class='ctx'> 			}</div><div class='ctx'> 			checksum += word;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -397,7 +397,7 @@ static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = hw-&gt;eeprom.ops.calc_checksum(hw);</div><div class='ctx'> 	if (status &lt; 0)</div><div class='hunk'>@@ -418,7 +418,7 @@ static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (read_checksum != checksum) {</div><div class='ctx'> 		hw_dbg(hw, "Invalid EEPROM checksum");</div><div class='del'>-		status = IXGBE_ERR_EEPROM_CHECKSUM;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* If the user cares, return the calculated checksum */</div><div class='hunk'>@@ -455,7 +455,7 @@ static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))</div><div class='del'>-		return  IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return  -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = hw-&gt;eeprom.ops.calc_checksum(hw);</div><div class='ctx'> 	if (status &lt; 0)</div><div class='hunk'>@@ -490,7 +490,7 @@ static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_poll_flash_update_done_X540(hw);</div><div class='del'>-	if (status == IXGBE_ERR_EEPROM) {</div><div class='add'>+	if (status == -EIO) {</div><div class='ctx'> 		hw_dbg(hw, "Flash update time out\n");</div><div class='ctx'> 		return status;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -540,7 +540,7 @@ static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		udelay(5);</div><div class='ctx'> 	}</div><div class='del'>-	return IXGBE_ERR_EEPROM;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -575,7 +575,7 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 		 * SW_FW_SYNC bits (not just NVM)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (ixgbe_get_swfw_sync_semaphore(hw))</div><div class='del'>-			return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+			return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 		swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));</div><div class='ctx'> 		if (!(swfw_sync &amp; (fwmask | swmask | hwmask))) {</div><div class='hunk'>@@ -599,7 +599,7 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 	 * bits in the SW_FW_SYNC register.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ixgbe_get_swfw_sync_semaphore(hw))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));</div><div class='ctx'> 	if (swfw_sync &amp; (fwmask | hwmask)) {</div><div class='ctx'> 		swfw_sync |= swmask;</div><div class='hunk'>@@ -622,11 +622,11 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 			rmask |= IXGBE_GSSR_I2C_MASK;</div><div class='ctx'> 		ixgbe_release_swfw_sync_X540(hw, rmask);</div><div class='ctx'> 		ixgbe_release_swfw_sync_semaphore(hw);</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> 	ixgbe_release_swfw_sync_semaphore(hw);</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+	return -EBUSY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -680,7 +680,7 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)</div><div class='ctx'> 	if (i == timeout) {</div><div class='ctx'> 		hw_dbg(hw,</div><div class='ctx'> 		       "Software semaphore SMBI between device drivers not granted.\n");</div><div class='del'>-		return IXGBE_ERR_EEPROM;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* Now get the semaphore between SW/FW through the REGSMP bit */</div><div class='hunk'>@@ -697,7 +697,7 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)</div><div class='ctx'> 	 */</div><div class='ctx'> 	hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");</div><div class='ctx'> 	ixgbe_release_swfw_sync_semaphore(hw);</div><div class='del'>-	return IXGBE_ERR_EEPROM;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -768,7 +768,7 @@ s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	bool link_up;</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Link should be up in order for the blink bit in the LED control</div><div class='ctx'> 	 * register to work. Force link and speed in the MAC if link is down.</div><div class='hunk'>@@ -804,7 +804,7 @@ s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)</div><div class='ctx'> 	u32 ledctl_reg;</div><div class='ctx'> </div><div class='ctx'> 	if (index &gt; 3)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Restore the LED to its default value. */</div><div class='ctx'> 	ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c<br/>index aa4bf6c9a2f7..6208923e29a2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c</a></div><div class='hunk'>@@ -206,13 +206,13 @@ static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)</div><div class='ctx'> 	}</div><div class='ctx'> 	if (retry == IXGBE_CS4227_RETRIES) {</div><div class='ctx'> 		hw_err(hw, "CS4227 reset did not complete\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &amp;value);</div><div class='ctx'> 	if (status || !(value &amp; IXGBE_CS4227_EEPROM_LOAD_OK)) {</div><div class='ctx'> 		hw_err(hw, "CS4227 EEPROM did not load successfully\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -350,13 +350,13 @@ static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 				     u32 device_type, u16 *phy_data)</div><div class='ctx'> {</div><div class='del'>-	return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 				      u32 device_type, u16 phy_data)</div><div class='ctx'> {</div><div class='del'>-	return IXGBE_NOT_IMPLEMENTED;</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -463,7 +463,7 @@ s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,</div><div class='ctx'> 		--retries;</div><div class='ctx'> 	} while (retries &gt; 0);</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct {</div><div class='hunk'>@@ -511,7 +511,7 @@ static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)</div><div class='ctx'> 	hw-&gt;phy.id |= phy_id_lo &amp; IXGBE_PHY_REVISION_MASK;</div><div class='ctx'> 	hw-&gt;phy.revision = phy_id_lo &amp; ~IXGBE_PHY_REVISION_MASK;</div><div class='ctx'> 	if (!hw-&gt;phy.id || hw-&gt;phy.id == IXGBE_PHY_REVISION_MASK)</div><div class='del'>-		return IXGBE_ERR_PHY_ADDR_INVALID;</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> </div><div class='ctx'> 	hw-&gt;phy.autoneg_advertised = hw-&gt;phy.speeds_supported;</div><div class='ctx'> 	hw-&gt;phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |</div><div class='hunk'>@@ -568,7 +568,7 @@ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;fc.strict_ieee &amp;&amp; hw-&gt;fc.requested_mode == ixgbe_fc_rx_pause) {</div><div class='ctx'> 		hw_err(hw, "rx_pause not valid in strict IEEE mode\n");</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (hw-&gt;fc.requested_mode) {</div><div class='hunk'>@@ -600,8 +600,10 @@ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)</div><div class='ctx'> 	rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &amp;setup);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='add'>+</div><div class='ctx'> 	if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)</div><div class='del'>-		return IXGBE_ERR_OVERTEMP;</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -628,16 +630,16 @@ static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)</div><div class='ctx'> static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_eeprom_info *eeprom = &amp;hw-&gt;eeprom;</div><div class='del'>-	u32 eec;</div><div class='del'>-	u16 eeprom_size;</div><div class='ctx'> </div><div class='ctx'> 	if (eeprom-&gt;type == ixgbe_eeprom_uninitialized) {</div><div class='add'>+		u16 eeprom_size;</div><div class='add'>+		u32 eec;</div><div class='add'>+</div><div class='ctx'> 		eeprom-&gt;semaphore_delay = 10;</div><div class='ctx'> 		eeprom-&gt;type = ixgbe_flash;</div><div class='ctx'> </div><div class='ctx'> 		eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));</div><div class='del'>-		eeprom_size = (u16)((eec &amp; IXGBE_EEC_SIZE) &gt;&gt;</div><div class='del'>-				    IXGBE_EEC_SIZE_SHIFT);</div><div class='add'>+		eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);</div><div class='ctx'> 		eeprom-&gt;word_size = BIT(eeprom_size +</div><div class='ctx'> 					IXGBE_EEPROM_WORD_SIZE_SHIFT);</div><div class='ctx'> </div><div class='hunk'>@@ -675,7 +677,7 @@ static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)</div><div class='ctx'> 		*ctrl = command;</div><div class='ctx'> 	if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {</div><div class='ctx'> 		hw_dbg(hw, "IOSF wait timed out\n");</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -712,10 +714,9 @@ static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 	ret = ixgbe_iosf_wait(hw, &amp;command);</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {</div><div class='del'>-		error = (command &amp; IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) &gt;&gt;</div><div class='del'>-			 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;</div><div class='add'>+		error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);</div><div class='ctx'> 		hw_dbg(hw, "Failed to read, error %x\n", error);</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!ret)</div><div class='hunk'>@@ -750,9 +751,9 @@ static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)</div><div class='ctx'> 	if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)</div><div class='del'>-		return IXGBE_ERR_FW_RESP_INVALID;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='del'>-	return IXGBE_ERR_TOKEN_RETRY;</div><div class='add'>+	return -EAGAIN;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -778,7 +779,7 @@ static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)</div><div class='ctx'> 		return status;</div><div class='ctx'> 	if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)</div><div class='ctx'> 		return 0;</div><div class='del'>-	return IXGBE_ERR_FW_RESP_INVALID;</div><div class='add'>+	return -EIO;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -942,7 +943,7 @@ static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,</div><div class='ctx'> 		local_buffer = buf;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (buffer_size &lt; ptr)</div><div class='del'>-			return  IXGBE_ERR_PARAM;</div><div class='add'>+			return  -EINVAL;</div><div class='ctx'> 		local_buffer = &amp;buffer[ptr];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -960,7 +961,7 @@ static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (buffer &amp;&amp; ((u32)start + (u32)length &gt; buffer_size))</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	for (i = start; length; i++, length--) {</div><div class='ctx'> 		if (i == bufsz &amp;&amp; !buffer) {</div><div class='hunk'>@@ -1012,7 +1013,7 @@ static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,</div><div class='ctx'> 		local_buffer = eeprom_ptrs;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (buffer_size &lt; IXGBE_EEPROM_LAST_WORD)</div><div class='del'>-			return IXGBE_ERR_PARAM;</div><div class='add'>+			return -EINVAL;</div><div class='ctx'> 		local_buffer = buffer;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1148,7 +1149,7 @@ static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,</div><div class='ctx'> 	 * calculated checksum</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (read_checksum != checksum) {</div><div class='del'>-		status = IXGBE_ERR_EEPROM_CHECKSUM;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		hw_dbg(hw, "Invalid EEPROM checksum");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1203,7 +1204,7 @@ static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)</div><div class='ctx'> 		hw-&gt;mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		hw_dbg(hw, "write ee hostif failed to get semaphore");</div><div class='del'>-		status = IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		status = -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return status;</div><div class='hunk'>@@ -1412,10 +1413,9 @@ static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 	ret = ixgbe_iosf_wait(hw, &amp;command);</div><div class='ctx'> </div><div class='ctx'> 	if ((command &amp; IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {</div><div class='del'>-		error = (command &amp; IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) &gt;&gt;</div><div class='del'>-			 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;</div><div class='add'>+		error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);</div><div class='ctx'> 		hw_dbg(hw, "Failed to write, error %x\n", error);</div><div class='del'>-		return IXGBE_ERR_PHY;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='hunk'>@@ -1558,7 +1558,7 @@ static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)</div><div class='ctx'> </div><div class='ctx'> 	/* iXFI is only supported with X552 */</div><div class='ctx'> 	if (mac-&gt;type != ixgbe_mac_X550EM_x)</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	/* Disable AN and force speed to 10G Serial. */</div><div class='ctx'> 	status = ixgbe_read_iosf_sb_reg_x550(hw,</div><div class='hunk'>@@ -1580,7 +1580,7 @@ static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* Other link speeds are not supported by internal KR PHY. */</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_write_iosf_sb_reg_x550(hw,</div><div class='hunk'>@@ -1611,7 +1611,7 @@ static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)</div><div class='ctx'> {</div><div class='ctx'> 	switch (hw-&gt;phy.sfp_type) {</div><div class='ctx'> 	case ixgbe_sfp_type_not_present:</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_PRESENT;</div><div class='add'>+		return -ENOENT;</div><div class='ctx'> 	case ixgbe_sfp_type_da_cu_core0:</div><div class='ctx'> 	case ixgbe_sfp_type_da_cu_core1:</div><div class='ctx'> 		*linear = true;</div><div class='hunk'>@@ -1630,7 +1630,7 @@ static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)</div><div class='ctx'> 	case ixgbe_sfp_type_1g_cu_core0:</div><div class='ctx'> 	case ixgbe_sfp_type_1g_cu_core1:</div><div class='ctx'> 	default:</div><div class='del'>-		return IXGBE_ERR_SFP_NOT_SUPPORTED;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1660,7 +1660,7 @@ ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,</div><div class='ctx'> 	 * there is no reason to configure CS4227 and SFP not present error is</div><div class='ctx'> 	 * not accepted in the setup MAC link flow.</div><div class='ctx'> 	 */</div><div class='del'>-	if (status == IXGBE_ERR_SFP_NOT_PRESENT)</div><div class='add'>+	if (status == -ENOENT)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (status)</div><div class='hunk'>@@ -1718,7 +1718,7 @@ static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* Other link speeds are not supported by internal PHY. */</div><div class='del'>-		return IXGBE_ERR_LINK_SETUP;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	(void)mac-&gt;ops.write_iosf_sb_reg(hw,</div><div class='hunk'>@@ -1803,7 +1803,7 @@ ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,</div><div class='ctx'> 	/* If no SFP module present, then return success. Return success since</div><div class='ctx'> 	 * SFP not present error is not excepted in the setup MAC link flow.</div><div class='ctx'> 	 */</div><div class='del'>-	if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)</div><div class='add'>+	if (ret_val == -ENOENT)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (ret_val)</div><div class='hunk'>@@ -1853,7 +1853,7 @@ ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,</div><div class='ctx'> 	/* If no SFP module present, then return success. Return success since</div><div class='ctx'> 	 * SFP not present error is not excepted in the setup MAC link flow.</div><div class='ctx'> 	 */</div><div class='del'>-	if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)</div><div class='add'>+	if (ret_val == -ENOENT)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	if (ret_val)</div><div class='hunk'>@@ -1863,7 +1863,7 @@ ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,</div><div class='ctx'> 	ixgbe_setup_kr_speed_x550em(hw, speed);</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;phy.mdio.prtad == MDIO_PRTAD_NONE)</div><div class='del'>-		return IXGBE_ERR_PHY_ADDR_INVALID;</div><div class='add'>+		return -EFAULT;</div><div class='ctx'> </div><div class='ctx'> 	/* Get external PHY SKU id */</div><div class='ctx'> 	ret_val = hw-&gt;phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,</div><div class='hunk'>@@ -1962,7 +1962,7 @@ static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,</div><div class='ctx'> 	u16 i, autoneg_status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.get_media_type(hw) != ixgbe_media_type_copper)</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_check_mac_link_generic(hw, speed, link_up,</div><div class='ctx'> 					      link_up_wait_to_complete);</div><div class='hunk'>@@ -2145,9 +2145,9 @@ static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,</div><div class='ctx'>  */</div><div class='ctx'> static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='ctx'> 	u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };</div><div class='ctx'> 	ixgbe_link_speed speed;</div><div class='add'>+	s32 status = -EIO;</div><div class='ctx'> 	bool link_up;</div><div class='ctx'> </div><div class='ctx'> 	/* AN should have completed when the cable was plugged in.</div><div class='hunk'>@@ -2165,7 +2165,7 @@ static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> 	/* Check if auto-negotiation has completed */</div><div class='ctx'> 	status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &amp;info);</div><div class='ctx'> 	if (status || !(info[0] &amp; FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {</div><div class='del'>-		status = IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2369,18 +2369,18 @@ static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,</div><div class='ctx'>  * @hw: pointer to hardware structure</div><div class='ctx'>  * @lsc: pointer to boolean flag which indicates whether external Base T</div><div class='ctx'>  *	 PHY interrupt is lsc</div><div class='add'>+ * @is_overtemp: indicate whether an overtemp event encountered</div><div class='ctx'>  *</div><div class='ctx'>  * Determime if external Base T PHY interrupt cause is high temperature</div><div class='ctx'>  * failure alarm or link status change.</div><div class='del'>- *</div><div class='del'>- * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature</div><div class='del'>- * failure alarm, else return PHY access status.</div><div class='ctx'>  **/</div><div class='del'>-static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)</div><div class='add'>+static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,</div><div class='add'>+				       bool *is_overtemp)</div><div class='ctx'> {</div><div class='ctx'> 	u32 status;</div><div class='ctx'> 	u16 reg;</div><div class='ctx'> </div><div class='add'>+	*is_overtemp = false;</div><div class='ctx'> 	*lsc = false;</div><div class='ctx'> </div><div class='ctx'> 	/* Vendor alarm triggered */</div><div class='hunk'>@@ -2412,7 +2412,8 @@ static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)</div><div class='ctx'> 	if (reg &amp; IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {</div><div class='ctx'> 		/* power down the PHY in case the PHY FW didn't already */</div><div class='ctx'> 		ixgbe_set_copper_phy_power(hw, false);</div><div class='del'>-		return IXGBE_ERR_OVERTEMP;</div><div class='add'>+		*is_overtemp = true;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (reg &amp; IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {</div><div class='ctx'> 		/*  device fault alarm triggered */</div><div class='hunk'>@@ -2426,7 +2427,8 @@ static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)</div><div class='ctx'> 		if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {</div><div class='ctx'> 			/* power down the PHY in case the PHY FW didn't */</div><div class='ctx'> 			ixgbe_set_copper_phy_power(hw, false);</div><div class='del'>-			return IXGBE_ERR_OVERTEMP;</div><div class='add'>+			*is_overtemp = true;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2462,12 +2464,12 @@ static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)</div><div class='ctx'>  **/</div><div class='ctx'> static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='add'>+	bool lsc, overtemp;</div><div class='ctx'> 	u32 status;</div><div class='ctx'> 	u16 reg;</div><div class='del'>-	bool lsc;</div><div class='ctx'> </div><div class='ctx'> 	/* Clear interrupt flags */</div><div class='del'>-	status = ixgbe_get_lasi_ext_t_x550em(hw, &amp;lsc);</div><div class='add'>+	status = ixgbe_get_lasi_ext_t_x550em(hw, &amp;lsc, &amp;overtemp);</div><div class='ctx'> </div><div class='ctx'> 	/* Enable link status change alarm */</div><div class='ctx'> </div><div class='hunk'>@@ -2546,21 +2548,20 @@ static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt</div><div class='ctx'>  * @hw: pointer to hardware structure</div><div class='add'>+ * @is_overtemp: indicate whether an overtemp event encountered</div><div class='ctx'>  *</div><div class='ctx'>  * Handle external Base T PHY interrupt. If high temperature</div><div class='ctx'>  * failure alarm then return error, else if link status change</div><div class='ctx'>  * then setup internal/external PHY link</div><div class='del'>- *</div><div class='del'>- * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature</div><div class='del'>- * failure alarm, else return PHY access status.</div><div class='ctx'>  **/</div><div class='del'>-static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)</div><div class='add'>+static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,</div><div class='add'>+					  bool *is_overtemp)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbe_phy_info *phy = &amp;hw-&gt;phy;</div><div class='ctx'> 	bool lsc;</div><div class='ctx'> 	u32 status;</div><div class='ctx'> </div><div class='del'>-	status = ixgbe_get_lasi_ext_t_x550em(hw, &amp;lsc);</div><div class='add'>+	status = ixgbe_get_lasi_ext_t_x550em(hw, &amp;lsc, is_overtemp);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='hunk'>@@ -2692,7 +2693,7 @@ static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> 	u16 speed;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.get_media_type(hw) != ixgbe_media_type_copper)</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> </div><div class='ctx'> 	if (!(hw-&gt;mac.type == ixgbe_mac_X550EM_x &amp;&amp;</div><div class='ctx'> 	      !(hw-&gt;phy.nw_mng_if_sel &amp; IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {</div><div class='hunk'>@@ -2735,7 +2736,7 @@ static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		/* Internal PHY does not support anything else */</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ixgbe_setup_ixfi_x550em(hw, &amp;force_speed);</div><div class='hunk'>@@ -2767,7 +2768,7 @@ static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)</div><div class='ctx'> 	u16 phy_data;</div><div class='ctx'> </div><div class='ctx'> 	if (led_idx &gt;= IXGBE_X557_MAX_LED_INDEX)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* To turn on the LED, set mode to ON. */</div><div class='ctx'> 	hw-&gt;phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,</div><div class='hunk'>@@ -2789,7 +2790,7 @@ static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)</div><div class='ctx'> 	u16 phy_data;</div><div class='ctx'> </div><div class='ctx'> 	if (led_idx &gt;= IXGBE_X557_MAX_LED_INDEX)</div><div class='del'>-		return IXGBE_ERR_PARAM;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* To turn on the LED, set mode to ON. */</div><div class='ctx'> 	hw-&gt;phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,</div><div class='hunk'>@@ -2813,8 +2814,9 @@ static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)</div><div class='ctx'>  *</div><div class='ctx'>  *  Sends driver version number to firmware through the manageability</div><div class='ctx'>  *  block.  On success return 0</div><div class='del'>- *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring</div><div class='del'>- *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.</div><div class='add'>+ *  else returns -EBUSY when encountering an error acquiring</div><div class='add'>+ *  semaphore, -EIO when command fails or -ENIVAL when incorrect</div><div class='add'>+ *  params passed.</div><div class='ctx'>  **/</div><div class='ctx'> static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,</div><div class='ctx'> 				     u8 build, u8 sub, u16 len,</div><div class='hunk'>@@ -2825,7 +2827,7 @@ static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!len || !driver_ver || (len &gt; sizeof(fw_cmd.driver_string)))</div><div class='del'>-		return IXGBE_ERR_INVALID_ARGUMENT;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;</div><div class='ctx'> 	fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;</div><div class='hunk'>@@ -2850,7 +2852,7 @@ static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,</div><div class='ctx'> </div><div class='ctx'> 		if (fw_cmd.hdr.cmd_or_resp.ret_status !=</div><div class='ctx'> 		    FW_CEM_RESP_STATUS_SUCCESS)</div><div class='del'>-			return IXGBE_ERR_HOST_INTERFACE_COMMAND;</div><div class='add'>+			return -EIO;</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -2907,7 +2909,7 @@ static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> 	/* Validate the requested mode */</div><div class='ctx'> 	if (hw-&gt;fc.strict_ieee &amp;&amp; hw-&gt;fc.requested_mode == ixgbe_fc_rx_pause) {</div><div class='ctx'> 		hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* 10gig parts do not have a word in the EEPROM to determine the</div><div class='hunk'>@@ -2942,7 +2944,7 @@ static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_err(hw, "Flow control param set incorrectly\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	switch (hw-&gt;device_id) {</div><div class='hunk'>@@ -2986,8 +2988,8 @@ static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u32 link_s1, lp_an_page_low, an_cntl_1;</div><div class='del'>-	s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='ctx'> 	ixgbe_link_speed speed;</div><div class='add'>+	s32 status = -EIO;</div><div class='ctx'> 	bool link_up;</div><div class='ctx'> </div><div class='ctx'> 	/* AN should have completed when the cable was plugged in.</div><div class='hunk'>@@ -3013,7 +3015,7 @@ static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	if (status || (link_s1 &amp; IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {</div><div class='ctx'> 		hw_dbg(hw, "Auto-Negotiation did not complete\n");</div><div class='del'>-		status = IXGBE_ERR_FC_NOT_NEGOTIATED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		goto out;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3187,21 +3189,23 @@ static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)</div><div class='ctx'> /**</div><div class='ctx'>  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp</div><div class='ctx'>  * @hw: pointer to hardware structure</div><div class='add'>+ *</div><div class='add'>+ * Return true when an overtemp event detected, otherwise false.</div><div class='ctx'>  */</div><div class='del'>-static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)</div><div class='add'>+static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)</div><div class='ctx'> {</div><div class='ctx'> 	u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };</div><div class='ctx'> 	s32 rc;</div><div class='ctx'> </div><div class='ctx'> 	rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &amp;store);</div><div class='ctx'> 	if (rc)</div><div class='del'>-		return rc;</div><div class='add'>+		return false;</div><div class='ctx'> </div><div class='ctx'> 	if (store[0] &amp; FW_PHY_ACT_GET_LINK_INFO_TEMP) {</div><div class='ctx'> 		ixgbe_shutdown_fw_phy(hw);</div><div class='del'>-		return IXGBE_ERR_OVERTEMP;</div><div class='add'>+		return true;</div><div class='ctx'> 	}</div><div class='del'>-	return 0;</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -3222,9 +3226,8 @@ static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (hw-&gt;mac.type == ixgbe_mac_x550em_a &amp;&amp;</div><div class='ctx'> 	    hw-&gt;phy.nw_mng_if_sel &amp; IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {</div><div class='del'>-		hw-&gt;phy.mdio.prtad = (hw-&gt;phy.nw_mng_if_sel &amp;</div><div class='del'>-				      IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) &gt;&gt;</div><div class='del'>-				     IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;</div><div class='add'>+		hw-&gt;phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,</div><div class='add'>+					       hw-&gt;phy.nw_mng_if_sel);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3251,8 +3254,7 @@ static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* Identify the PHY or SFP module */</div><div class='ctx'> 	ret_val = phy-&gt;ops.identify(hw);</div><div class='del'>-	if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED ||</div><div class='del'>-	    ret_val == IXGBE_ERR_PHY_ADDR_INVALID)</div><div class='add'>+	if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)</div><div class='ctx'> 		return ret_val;</div><div class='ctx'> </div><div class='ctx'> 	/* Setup function pointers based on detected hardware */</div><div class='hunk'>@@ -3460,8 +3462,7 @@ static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)</div><div class='ctx'> </div><div class='ctx'> 	/* PHY ops must be identified and initialized prior to reset */</div><div class='ctx'> 	status = hw-&gt;phy.ops.init(hw);</div><div class='del'>-	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED ||</div><div class='del'>-	    status == IXGBE_ERR_PHY_ADDR_INVALID)</div><div class='add'>+	if (status == -EOPNOTSUPP || status == -EFAULT)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	/* start the external PHY */</div><div class='hunk'>@@ -3477,7 +3478,7 @@ static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)</div><div class='ctx'> 		hw-&gt;phy.sfp_setup_needed = false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)</div><div class='add'>+	if (status == -EOPNOTSUPP)</div><div class='ctx'> 		return status;</div><div class='ctx'> </div><div class='ctx'> 	/* Reset PHY */</div><div class='hunk'>@@ -3501,7 +3502,7 @@ mac_reset_top:</div><div class='ctx'> 	status = hw-&gt;mac.ops.acquire_swfw_sync(hw, swfw_mask);</div><div class='ctx'> 	if (status) {</div><div class='ctx'> 		hw_dbg(hw, "semaphore failed with %d", status);</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);</div><div class='hunk'>@@ -3519,7 +3520,7 @@ mac_reset_top:</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ctrl &amp; IXGBE_CTRL_RST_MASK) {</div><div class='del'>-		status = IXGBE_ERR_RESET_FAILED;</div><div class='add'>+		status = -EIO;</div><div class='ctx'> 		hw_dbg(hw, "Reset polling failed to complete.\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3615,7 +3616,7 @@ static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> 	/* Validate the requested mode */</div><div class='ctx'> 	if (hw-&gt;fc.strict_ieee &amp;&amp; hw-&gt;fc.requested_mode == ixgbe_fc_rx_pause) {</div><div class='ctx'> 		hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");</div><div class='del'>-		return IXGBE_ERR_INVALID_LINK_SETTINGS;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;fc.requested_mode == ixgbe_fc_default)</div><div class='hunk'>@@ -3672,7 +3673,7 @@ static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		hw_err(hw, "Flow control param set incorrectly\n");</div><div class='del'>-		return IXGBE_ERR_CONFIG;</div><div class='add'>+		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	status = hw-&gt;mac.ops.write_iosf_sb_reg(hw,</div><div class='hunk'>@@ -3768,7 +3769,7 @@ static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)</div><div class='ctx'> 			return 0;</div><div class='ctx'> 		if (hmask)</div><div class='ctx'> 			ixgbe_release_swfw_sync_X540(hw, hmask);</div><div class='del'>-		if (status != IXGBE_ERR_TOKEN_RETRY)</div><div class='add'>+		if (status != -EAGAIN)</div><div class='ctx'> 			return status;</div><div class='ctx'> 		msleep(FW_PHY_TOKEN_DELAY);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3812,7 +3813,7 @@ static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, mask))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = hw-&gt;phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);</div><div class='ctx'> </div><div class='hunk'>@@ -3838,7 +3839,7 @@ static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,</div><div class='ctx'> 	s32 status;</div><div class='ctx'> </div><div class='ctx'> 	if (hw-&gt;mac.ops.acquire_swfw_sync(hw, mask))</div><div class='del'>-		return IXGBE_ERR_SWFW_SYNC;</div><div class='add'>+		return -EBUSY;</div><div class='ctx'> </div><div class='ctx'> 	status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);</div><div class='ctx'> 	hw-&gt;mac.ops.release_swfw_sync(hw, mask);</div><div class='head'>diff --git a/drivers/net/ethernet/intel/ixgbevf/ethtool.c b/drivers/net/ethernet/intel/ixgbevf/ethtool.c<br/>index 296915414a7c..7ac53171b041 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbevf/ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/intel/ixgbevf/ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/intel/ixgbevf/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/intel/ixgbevf/ethtool.c</a></div><div class='hunk'>@@ -897,40 +897,41 @@ static u32 ixgbevf_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return IXGBEVF_RSS_HASH_KEY_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ixgbevf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			    u8 *hfunc)</div><div class='add'>+static int ixgbevf_get_rxfh(struct net_device *netdev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ixgbevf_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	if (adapter-&gt;hw.mac.type &gt;= ixgbe_mac_X550_vf) {</div><div class='del'>-		if (key)</div><div class='del'>-			memcpy(key, adapter-&gt;rss_key,</div><div class='add'>+		if (rxfh-&gt;key)</div><div class='add'>+			memcpy(rxfh-&gt;key, adapter-&gt;rss_key,</div><div class='ctx'> 			       ixgbevf_get_rxfh_key_size(netdev));</div><div class='ctx'> </div><div class='del'>-		if (indir) {</div><div class='add'>+		if (rxfh-&gt;indir) {</div><div class='ctx'> 			int i;</div><div class='ctx'> </div><div class='ctx'> 			for (i = 0; i &lt; IXGBEVF_X550_VFRETA_SIZE; i++)</div><div class='del'>-				indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='add'>+				rxfh-&gt;indir[i] = adapter-&gt;rss_indir_tbl[i];</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* If neither indirection table nor hash key was requested</div><div class='ctx'> 		 *  - just return a success avoiding taking any locks.</div><div class='ctx'> 		 */</div><div class='del'>-		if (!indir &amp;&amp; !key)</div><div class='add'>+		if (!rxfh-&gt;indir &amp;&amp; !rxfh-&gt;key)</div><div class='ctx'> 			return 0;</div><div class='ctx'> </div><div class='ctx'> 		spin_lock_bh(&amp;adapter-&gt;mbx_lock);</div><div class='del'>-		if (indir)</div><div class='del'>-			err = ixgbevf_get_reta_locked(&amp;adapter-&gt;hw, indir,</div><div class='add'>+		if (rxfh-&gt;indir)</div><div class='add'>+			err = ixgbevf_get_reta_locked(&amp;adapter-&gt;hw,</div><div class='add'>+						      rxfh-&gt;indir,</div><div class='ctx'> 						      adapter-&gt;num_rx_queues);</div><div class='ctx'> </div><div class='del'>-		if (!err &amp;&amp; key)</div><div class='del'>-			err = ixgbevf_get_rss_key_locked(&amp;adapter-&gt;hw, key);</div><div class='add'>+		if (!err &amp;&amp; rxfh-&gt;key)</div><div class='add'>+			err = ixgbevf_get_rss_key_locked(&amp;adapter-&gt;hw,</div><div class='add'>+							 rxfh-&gt;key);</div><div class='ctx'> </div><div class='ctx'> 		spin_unlock_bh(&amp;adapter-&gt;mbx_lock);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/mvmdio.c b/drivers/net/ethernet/marvell/mvmdio.c<br/>index 89f26402f8fb..9190eff6c0bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvmdio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/mvmdio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvmdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvmdio.c</a></div><div class='hunk'>@@ -23,6 +23,7 @@</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='ctx'> #include &lt;linux/mod_devicetable.h&gt;</div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -52,17 +53,19 @@</div><div class='ctx'> #define  MVMDIO_XSMI_BUSY		BIT(30)</div><div class='ctx'> #define MVMDIO_XSMI_ADDR_REG		0x8</div><div class='ctx'> </div><div class='add'>+#define MVMDIO_XSMI_CFG_REG		0xc</div><div class='add'>+#define  MVMDIO_XSMI_CLKDIV_MASK	0x3</div><div class='add'>+#define  MVMDIO_XSMI_CLKDIV_256		0x0</div><div class='add'>+#define  MVMDIO_XSMI_CLKDIV_64		0x1</div><div class='add'>+#define  MVMDIO_XSMI_CLKDIV_32		0x2</div><div class='add'>+#define  MVMDIO_XSMI_CLKDIV_8		0x3</div><div class='add'>+</div><div class='ctx'> /*</div><div class='ctx'>  * SMI Timeout measurements:</div><div class='ctx'>  * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)</div><div class='ctx'>  * - Armada 370       (Globalscale Mirabox):   41us to 43us (Polled)</div><div class='ctx'>  */</div><div class='ctx'> #define MVMDIO_SMI_TIMEOUT		1000 /* 1000us = 1ms */</div><div class='del'>-#define MVMDIO_SMI_POLL_INTERVAL_MIN	45</div><div class='del'>-#define MVMDIO_SMI_POLL_INTERVAL_MAX	55</div><div class='del'>-</div><div class='del'>-#define MVMDIO_XSMI_POLL_INTERVAL_MIN	150</div><div class='del'>-#define MVMDIO_XSMI_POLL_INTERVAL_MAX	160</div><div class='ctx'> </div><div class='ctx'> struct orion_mdio_dev {</div><div class='ctx'> 	void __iomem *regs;</div><div class='hunk'>@@ -84,8 +87,6 @@ enum orion_mdio_bus_type {</div><div class='ctx'> </div><div class='ctx'> struct orion_mdio_ops {</div><div class='ctx'> 	int (*is_done)(struct orion_mdio_dev *);</div><div class='del'>-	unsigned int poll_interval_min;</div><div class='del'>-	unsigned int poll_interval_max;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Wait for the SMI unit to be ready for another operation</div><div class='hunk'>@@ -94,34 +95,23 @@ static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,</div><div class='ctx'> 				 struct mii_bus *bus)</div><div class='ctx'> {</div><div class='ctx'> 	struct orion_mdio_dev *dev = bus-&gt;priv;</div><div class='del'>-	unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);</div><div class='del'>-	unsigned long end = jiffies + timeout;</div><div class='del'>-	int timedout = 0;</div><div class='add'>+	unsigned long timeout;</div><div class='add'>+	int done;</div><div class='ctx'> </div><div class='del'>-	while (1) {</div><div class='del'>-	        if (ops-&gt;is_done(dev))</div><div class='add'>+	if (dev-&gt;err_interrupt &lt;= 0) {</div><div class='add'>+		if (!read_poll_timeout_atomic(ops-&gt;is_done, done, done, 2,</div><div class='add'>+					      MVMDIO_SMI_TIMEOUT, false, dev))</div><div class='add'>+			return 0;</div><div class='add'>+	} else {</div><div class='add'>+		/* wait_event_timeout does not guarantee a delay of at</div><div class='add'>+		 * least one whole jiffie, so timeout must be no less</div><div class='add'>+		 * than two.</div><div class='add'>+		 */</div><div class='add'>+		timeout = max(usecs_to_jiffies(MVMDIO_SMI_TIMEOUT), 2);</div><div class='add'>+</div><div class='add'>+		if (wait_event_timeout(dev-&gt;smi_busy_wait,</div><div class='add'>+				       ops-&gt;is_done(dev), timeout))</div><div class='ctx'> 			return 0;</div><div class='del'>-	        else if (timedout)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-	        if (dev-&gt;err_interrupt &lt;= 0) {</div><div class='del'>-			usleep_range(ops-&gt;poll_interval_min,</div><div class='del'>-				     ops-&gt;poll_interval_max);</div><div class='del'>-</div><div class='del'>-			if (time_is_before_jiffies(end))</div><div class='del'>-				++timedout;</div><div class='del'>-	        } else {</div><div class='del'>-			/* wait_event_timeout does not guarantee a delay of at</div><div class='del'>-			 * least one whole jiffie, so timeout must be no less</div><div class='del'>-			 * than two.</div><div class='del'>-			 */</div><div class='del'>-			if (timeout &lt; 2)</div><div class='del'>-				timeout = 2;</div><div class='del'>-			wait_event_timeout(dev-&gt;smi_busy_wait,</div><div class='del'>-				           ops-&gt;is_done(dev), timeout);</div><div class='del'>-</div><div class='del'>-			++timedout;</div><div class='del'>-	        }</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dev_err(bus-&gt;parent, "Timeout: SMI busy for too long\n");</div><div class='hunk'>@@ -135,8 +125,6 @@ static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)</div><div class='ctx'> </div><div class='ctx'> static const struct orion_mdio_ops orion_mdio_smi_ops = {</div><div class='ctx'> 	.is_done = orion_mdio_smi_is_done,</div><div class='del'>-	.poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,</div><div class='del'>-	.poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,</div><div class='hunk'>@@ -194,8 +182,6 @@ static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)</div><div class='ctx'> </div><div class='ctx'> static const struct orion_mdio_ops orion_mdio_xsmi_ops = {</div><div class='ctx'> 	.is_done = orion_mdio_xsmi_is_done,</div><div class='del'>-	.poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,</div><div class='del'>-	.poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int orion_mdio_xsmi_read_c45(struct mii_bus *bus, int mii_id,</div><div class='hunk'>@@ -246,6 +232,40 @@ static int orion_mdio_xsmi_write_c45(struct mii_bus *bus, int mii_id,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void orion_mdio_xsmi_set_mdc_freq(struct mii_bus *bus)</div><div class='add'>+{</div><div class='add'>+	struct orion_mdio_dev *dev = bus-&gt;priv;</div><div class='add'>+	struct clk *mg_core;</div><div class='add'>+	u32 div, freq, cfg;</div><div class='add'>+</div><div class='add'>+	if (device_property_read_u32(bus-&gt;parent, "clock-frequency", &amp;freq))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mg_core = of_clk_get_by_name(bus-&gt;parent-&gt;of_node, "mg_core_clk");</div><div class='add'>+	if (IS_ERR(mg_core)) {</div><div class='add'>+		dev_err(bus-&gt;parent,</div><div class='add'>+			"MG core clock unknown, not changing MDC frequency");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	div = clk_get_rate(mg_core) / (freq + 1) + 1;</div><div class='add'>+	clk_put(mg_core);</div><div class='add'>+</div><div class='add'>+	if (div &lt;= 8)</div><div class='add'>+		div = MVMDIO_XSMI_CLKDIV_8;</div><div class='add'>+	else if (div &lt;= 32)</div><div class='add'>+		div = MVMDIO_XSMI_CLKDIV_32;</div><div class='add'>+	else if (div &lt;= 64)</div><div class='add'>+		div = MVMDIO_XSMI_CLKDIV_64;</div><div class='add'>+	else</div><div class='add'>+		div = MVMDIO_XSMI_CLKDIV_256;</div><div class='add'>+</div><div class='add'>+	cfg = readl(dev-&gt;regs + MVMDIO_XSMI_CFG_REG);</div><div class='add'>+	cfg &amp;= ~MVMDIO_XSMI_CLKDIV_MASK;</div><div class='add'>+	cfg |= div;</div><div class='add'>+	writel(cfg, dev-&gt;regs + MVMDIO_XSMI_CFG_REG);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct orion_mdio_dev *dev = dev_id;</div><div class='hunk'>@@ -324,6 +344,9 @@ static int orion_mdio_probe(struct platform_device *pdev)</div><div class='ctx'> 			dev_warn(&amp;pdev-&gt;dev,</div><div class='ctx'> 				 "unsupported number of clocks, limiting to the first "</div><div class='ctx'> 				 __stringify(ARRAY_SIZE(dev-&gt;clk)) "\n");</div><div class='add'>+</div><div class='add'>+		if (type == BUS_TYPE_XSMI)</div><div class='add'>+			orion_mdio_xsmi_set_mdc_freq(bus);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dev-&gt;clk[0] = clk_get(&amp;pdev-&gt;dev, NULL);</div><div class='ctx'> 		if (PTR_ERR(dev-&gt;clk[0]) == -EPROBE_DEFER) {</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c<br/>index 29aac327574d..a641b3534ca3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvneta.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/mvneta.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvneta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvneta.c</a></div><div class='hunk'>@@ -5030,8 +5030,9 @@ static int  mvneta_config_rss(struct mvneta_port *pp)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-				   const u8 *key, const u8 hfunc)</div><div class='add'>+static int mvneta_ethtool_set_rxfh(struct net_device *dev,</div><div class='add'>+				   struct ethtool_rxfh_param *rxfh,</div><div class='add'>+				   struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct mvneta_port *pp = netdev_priv(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -5042,20 +5043,21 @@ static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 	/* We require at least one supported parameter to be changed</div><div class='ctx'> 	 * and no change in any of the unsupported parameters</div><div class='ctx'> 	 */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	memcpy(pp-&gt;indir, indir, MVNETA_RSS_LU_TABLE_SIZE);</div><div class='add'>+	memcpy(pp-&gt;indir, rxfh-&gt;indir, MVNETA_RSS_LU_TABLE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return mvneta_config_rss(pp);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-				   u8 *hfunc)</div><div class='add'>+static int mvneta_ethtool_get_rxfh(struct net_device *dev,</div><div class='add'>+				   struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct mvneta_port *pp = netdev_priv(dev);</div><div class='ctx'> </div><div class='hunk'>@@ -5063,13 +5065,12 @@ static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='ctx'> 	if (pp-&gt;neta_armada3700)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	memcpy(indir, pp-&gt;indir, MVNETA_RSS_LU_TABLE_SIZE);</div><div class='add'>+	memcpy(rxfh-&gt;indir, pp-&gt;indir, MVNETA_RSS_LU_TABLE_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c<br/>index 93137606869e..820b1fabe297 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c</a></div><div class='hunk'>@@ -1513,10 +1513,21 @@ static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)</div><div class='ctx'> 	regmap_write(priv-&gt;sysctrl_base, GENCONF_PORT_CTRL0, val);</div><div class='ctx'> </div><div class='ctx'> 	regmap_read(priv-&gt;sysctrl_base, GENCONF_CTRL0, &amp;val);</div><div class='del'>-	if (port-&gt;gop_id == 2)</div><div class='add'>+	if (port-&gt;gop_id == 2) {</div><div class='ctx'> 		val |= GENCONF_CTRL0_PORT2_RGMII;</div><div class='del'>-	else if (port-&gt;gop_id == 3)</div><div class='add'>+	} else if (port-&gt;gop_id == 3) {</div><div class='ctx'> 		val |= GENCONF_CTRL0_PORT3_RGMII_MII;</div><div class='add'>+</div><div class='add'>+		/* According to the specification, GENCONF_CTRL0_PORT3_RGMII</div><div class='add'>+		 * should be set to 1 for RGMII and 0 for MII. However, tests</div><div class='add'>+		 * show that it is the other way around. This is also what</div><div class='add'>+		 * U-Boot does for mvpp2, so it is assumed to be correct.</div><div class='add'>+		 */</div><div class='add'>+		if (port-&gt;phy_interface == PHY_INTERFACE_MODE_MII)</div><div class='add'>+			val |= GENCONF_CTRL0_PORT3_RGMII;</div><div class='add'>+		else</div><div class='add'>+			val &amp;= ~GENCONF_CTRL0_PORT3_RGMII;</div><div class='add'>+	}</div><div class='ctx'> 	regmap_write(priv-&gt;sysctrl_base, GENCONF_CTRL0, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1615,6 +1626,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	switch (interface) {</div><div class='add'>+	case PHY_INTERFACE_MODE_MII:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_RGMII:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_RGMII_ID:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_RGMII_RXID:</div><div class='hunk'>@@ -5634,49 +5646,11 @@ static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-				  u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	struct mvpp2_port *port = netdev_priv(dev);</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	if (!mvpp22_rss_is_supported(port))</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	if (indir)</div><div class='del'>-		ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);</div><div class='del'>-</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_CRC32;</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-				  const u8 *key, const u8 hfunc)</div><div class='del'>-{</div><div class='del'>-	struct mvpp2_port *port = netdev_priv(dev);</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	if (!mvpp22_rss_is_supported(port))</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_CRC32)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	if (key)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	if (indir)</div><div class='del'>-		ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,</div><div class='del'>-					  u8 *key, u8 *hfunc, u32 rss_context)</div><div class='add'>+static int mvpp2_ethtool_get_rxfh(struct net_device *dev,</div><div class='add'>+				  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct mvpp2_port *port = netdev_priv(dev);</div><div class='add'>+	u32 rss_context = rxfh-&gt;rss_context;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!mvpp22_rss_is_supported(port))</div><div class='hunk'>@@ -5684,33 +5658,34 @@ static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,</div><div class='ctx'> 	if (rss_context &gt;= MVPP22_N_RSS_TABLES)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_CRC32;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_CRC32;</div><div class='ctx'> </div><div class='del'>-	if (indir)</div><div class='del'>-		ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		ret = mvpp22_port_rss_ctx_indir_get(port, rss_context,</div><div class='add'>+						    rxfh-&gt;indir);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,</div><div class='del'>-					  const u32 *indir, const u8 *key,</div><div class='del'>-					  const u8 hfunc, u32 *rss_context,</div><div class='del'>-					  bool delete)</div><div class='add'>+static int mvpp2_ethtool_set_rxfh(struct net_device *dev,</div><div class='add'>+				  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+				  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct mvpp2_port *port = netdev_priv(dev);</div><div class='del'>-	int ret;</div><div class='add'>+	u32 *rss_context = &amp;rxfh-&gt;rss_context;</div><div class='add'>+	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!mvpp22_rss_is_supported(port))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_CRC32)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_CRC32)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (delete)</div><div class='add'>+	if (*rss_context &amp;&amp; rxfh-&gt;rss_delete)</div><div class='ctx'> 		return mvpp22_port_rss_ctx_delete(port, *rss_context);</div><div class='ctx'> </div><div class='ctx'> 	if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {</div><div class='hunk'>@@ -5719,8 +5694,13 @@ static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		ret = mvpp22_port_rss_ctx_indir_set(port, *rss_context,</div><div class='add'>+						    rxfh-&gt;indir);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='add'>+</div><div class='ctx'> /* Device ops */</div><div class='ctx'> </div><div class='ctx'> static const struct net_device_ops mvpp2_netdev_ops = {</div><div class='hunk'>@@ -5740,6 +5720,7 @@ static const struct net_device_ops mvpp2_netdev_ops = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops mvpp2_eth_tool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_MAX_FRAMES,</div><div class='ctx'> 	.nway_reset		= mvpp2_ethtool_nway_reset,</div><div class='hunk'>@@ -5762,8 +5743,6 @@ static const struct ethtool_ops mvpp2_eth_tool_ops = {</div><div class='ctx'> 	.get_rxfh_indir_size	= mvpp2_ethtool_get_rxfh_indir_size,</div><div class='ctx'> 	.get_rxfh		= mvpp2_ethtool_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= mvpp2_ethtool_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= mvpp2_ethtool_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= mvpp2_ethtool_set_rxfh_context,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that</div><div class='hunk'>@@ -6898,7 +6877,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,</div><div class='ctx'> 	dev-&gt;min_mtu = ETH_MIN_MTU;</div><div class='ctx'> 	/* 9704 == 9728 - 20 and rounding to 8 */</div><div class='ctx'> 	dev-&gt;max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;</div><div class='del'>-	dev-&gt;dev.of_node = port_node;</div><div class='add'>+	device_set_node(&amp;dev-&gt;dev, port_fwnode);</div><div class='ctx'> </div><div class='ctx'> 	port-&gt;pcs_gmac.ops = &amp;mvpp2_phylink_gmac_pcs_ops;</div><div class='ctx'> 	port-&gt;pcs_gmac.neg_mode = true;</div><div class='hunk'>@@ -6948,8 +6927,11 @@ static int mvpp2_port_probe(struct platform_device *pdev,</div><div class='ctx'> 					MAC_10000FD;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		if (mvpp2_port_supports_rgmii(port))</div><div class='add'>+		if (mvpp2_port_supports_rgmii(port)) {</div><div class='ctx'> 			phy_interface_set_rgmii(port-&gt;phylink_config.supported_interfaces);</div><div class='add'>+			__set_bit(PHY_INTERFACE_MODE_MII,</div><div class='add'>+				  port-&gt;phylink_config.supported_interfaces);</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		if (comphy) {</div><div class='ctx'> 			/* If a COMPHY is present, we can support any of the</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/Makefile b/drivers/net/ethernet/marvell/octeon_ep/Makefile<br/>index 2026c8118158..62162ed63f34 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/Makefile</a></div><div class='hunk'>@@ -6,4 +6,5 @@</div><div class='ctx'> obj-$(CONFIG_OCTEON_EP) += octeon_ep.o</div><div class='ctx'> </div><div class='ctx'> octeon_ep-y := octep_main.o octep_cn9k_pf.o octep_tx.o octep_rx.o \</div><div class='del'>-	       octep_ethtool.o octep_ctrl_mbox.o octep_ctrl_net.o</div><div class='add'>+	       octep_ethtool.o octep_ctrl_mbox.o octep_ctrl_net.o \</div><div class='add'>+	       octep_pfvf_mbox.o octep_cnxk_pf.o</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c<br/>index d4ee2454675b..b5805969404f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c</a></div><div class='hunk'>@@ -216,16 +216,21 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)</div><div class='ctx'> 	conf-&gt;sriov_cfg.vf_srn = CN93_SDP_EPF_RINFO_SRN(val);</div><div class='ctx'> </div><div class='ctx'> 	val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct-&gt;pcie_port));</div><div class='del'>-	conf-&gt;pf_ring_cfg.srn =  CN93_SDP_MAC_PF_RING_CTL_SRN(val);</div><div class='del'>-	conf-&gt;pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);</div><div class='del'>-	conf-&gt;pf_ring_cfg.active_io_rings = conf-&gt;pf_ring_cfg.max_io_rings;</div><div class='add'>+	if (oct-&gt;chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF) {</div><div class='add'>+		conf-&gt;pf_ring_cfg.srn =  CN98_SDP_MAC_PF_RING_CTL_SRN(val);</div><div class='add'>+		conf-&gt;pf_ring_cfg.max_io_rings = CN98_SDP_MAC_PF_RING_CTL_RPPF(val);</div><div class='add'>+		conf-&gt;pf_ring_cfg.active_io_rings = conf-&gt;pf_ring_cfg.max_io_rings;</div><div class='add'>+	} else {</div><div class='add'>+		conf-&gt;pf_ring_cfg.srn =  CN93_SDP_MAC_PF_RING_CTL_SRN(val);</div><div class='add'>+		conf-&gt;pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);</div><div class='add'>+		conf-&gt;pf_ring_cfg.active_io_rings = conf-&gt;pf_ring_cfg.max_io_rings;</div><div class='add'>+	}</div><div class='ctx'> 	dev_info(&amp;pdev-&gt;dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n",</div><div class='ctx'> 		 conf-&gt;pf_ring_cfg.srn, conf-&gt;sriov_cfg.active_rings_per_vf,</div><div class='ctx'> 		 conf-&gt;sriov_cfg.active_vfs, conf-&gt;pf_ring_cfg.active_io_rings);</div><div class='ctx'> </div><div class='ctx'> 	conf-&gt;iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS;</div><div class='ctx'> 	conf-&gt;iq.instr_type = OCTEP_64BYTE_INSTR;</div><div class='del'>-	conf-&gt;iq.pkind = 0;</div><div class='ctx'> 	conf-&gt;iq.db_min = OCTEP_DB_MIN;</div><div class='ctx'> 	conf-&gt;iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD;</div><div class='ctx'> </div><div class='hunk'>@@ -357,16 +362,55 @@ static void octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no)</div><div class='ctx'> {</div><div class='ctx'> 	struct octep_mbox *mbox = oct-&gt;mbox[q_no];</div><div class='ctx'> </div><div class='del'>-	mbox-&gt;q_no = q_no;</div><div class='del'>-</div><div class='del'>-	/* PF mbox interrupt reg */</div><div class='del'>-	mbox-&gt;mbox_int_reg = oct-&gt;mmio[0].hw_addr + CN93_SDP_EPF_MBOX_RINT(0);</div><div class='del'>-</div><div class='ctx'> 	/* PF to VF DATA reg. PF writes into this reg */</div><div class='del'>-	mbox-&gt;mbox_write_reg = oct-&gt;mmio[0].hw_addr + CN93_SDP_R_MBOX_PF_VF_DATA(q_no);</div><div class='add'>+	mbox-&gt;pf_vf_data_reg = oct-&gt;mmio[0].hw_addr + CN93_SDP_MBOX_PF_VF_DATA(q_no);</div><div class='ctx'> </div><div class='ctx'> 	/* VF to PF DATA reg. PF reads from this reg */</div><div class='del'>-	mbox-&gt;mbox_read_reg = oct-&gt;mmio[0].hw_addr + CN93_SDP_R_MBOX_VF_PF_DATA(q_no);</div><div class='add'>+	mbox-&gt;vf_pf_data_reg = oct-&gt;mmio[0].hw_addr + CN93_SDP_MBOX_VF_PF_DATA(q_no);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Poll for mailbox messages from VF */</div><div class='add'>+static void octep_poll_pfvf_mailbox(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u32 vf, active_vfs, active_rings_per_vf, vf_mbox_queue;</div><div class='add'>+	u64 reg0, reg1;</div><div class='add'>+</div><div class='add'>+	reg0 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0));</div><div class='add'>+	reg1 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1));</div><div class='add'>+	if (reg0 || reg1) {</div><div class='add'>+		active_vfs = CFG_GET_ACTIVE_VFS(oct-&gt;conf);</div><div class='add'>+		active_rings_per_vf = CFG_GET_ACTIVE_RPVF(oct-&gt;conf);</div><div class='add'>+		for (vf = 0; vf &lt; active_vfs; vf++) {</div><div class='add'>+			vf_mbox_queue = vf * active_rings_per_vf;</div><div class='add'>+</div><div class='add'>+			if (vf_mbox_queue &lt; 64) {</div><div class='add'>+				if (!(reg0 &amp; (0x1UL &lt;&lt; vf_mbox_queue)))</div><div class='add'>+					continue;</div><div class='add'>+			} else {</div><div class='add'>+				if (!(reg1 &amp; (0x1UL &lt;&lt; (vf_mbox_queue - 64))))</div><div class='add'>+					continue;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (!oct-&gt;mbox[vf_mbox_queue]) {</div><div class='add'>+				dev_err(&amp;oct-&gt;pdev-&gt;dev, "bad mbox vf %d\n", vf);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+			schedule_work(&amp;oct-&gt;mbox[vf_mbox_queue]-&gt;wk.work);</div><div class='add'>+		}</div><div class='add'>+		if (reg0)</div><div class='add'>+			octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0), reg0);</div><div class='add'>+		if (reg1)</div><div class='add'>+			octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1), reg1);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* PF-VF mailbox interrupt handler */</div><div class='add'>+static irqreturn_t octep_pfvf_mbox_intr_handler_cn93_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+</div><div class='add'>+	octep_poll_pfvf_mailbox(oct);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Poll OEI events like heartbeat */</div><div class='hunk'>@@ -398,6 +442,7 @@ static irqreturn_t octep_oei_intr_handler_cn93_pf(void *dev)</div><div class='ctx'>  */</div><div class='ctx'> static void octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct)</div><div class='ctx'> {</div><div class='add'>+	octep_poll_pfvf_mailbox(oct);</div><div class='ctx'> 	octep_poll_oei_cn93_pf(oct);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -578,6 +623,13 @@ static irqreturn_t octep_ioq_intr_handler_cn93_pf(void *data)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* soft reset of 98xx */</div><div class='add'>+static int octep_soft_reset_cn98_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	dev_info(&amp;oct-&gt;pdev-&gt;dev, "CN98XX: skip soft reset\n");</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* soft reset of 93xx */</div><div class='ctx'> static int octep_soft_reset_cn93_pf(struct octep_device *oct)</div><div class='ctx'> {</div><div class='hunk'>@@ -634,6 +686,8 @@ static void octep_enable_interrupts_cn93_pf(struct octep_device *oct)</div><div class='ctx'> </div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask);</div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(1), -1ULL);</div><div class='ctx'> </div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL);</div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL);</div><div class='hunk'>@@ -660,6 +714,8 @@ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)</div><div class='ctx'> </div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask);</div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(1), -1ULL);</div><div class='ctx'> </div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL);</div><div class='ctx'> 	octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL);</div><div class='hunk'>@@ -795,6 +851,7 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)</div><div class='ctx'> 	oct-&gt;hw_ops.setup_oq_regs = octep_setup_oq_regs_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cn93_pf;</div><div class='ctx'> </div><div class='add'>+	oct-&gt;hw_ops.mbox_intr_handler = octep_pfvf_mbox_intr_handler_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.oei_intr_handler = octep_oei_intr_handler_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.ire_intr_handler = octep_ire_intr_handler_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.ore_intr_handler = octep_ore_intr_handler_cn93_pf;</div><div class='hunk'>@@ -806,7 +863,10 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)</div><div class='ctx'> 	oct-&gt;hw_ops.misc_intr_handler = octep_misc_intr_handler_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf;</div><div class='del'>-	oct-&gt;hw_ops.soft_reset = octep_soft_reset_cn93_pf;</div><div class='add'>+	if (oct-&gt;chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)</div><div class='add'>+		oct-&gt;hw_ops.soft_reset = octep_soft_reset_cn98_pf;</div><div class='add'>+	else</div><div class='add'>+		oct-&gt;hw_ops.soft_reset = octep_soft_reset_cn93_pf;</div><div class='ctx'> 	oct-&gt;hw_ops.reinit_regs = octep_reinit_regs_cn93_pf;</div><div class='ctx'> </div><div class='ctx'> 	oct-&gt;hw_ops.enable_interrupts = octep_enable_interrupts_cn93_pf;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c<br/>new file mode 100644<br/>index 000000000000..5de0b5ecbc5f<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c</a></div><div class='hunk'>@@ -0,0 +1,925 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Marvell Octeon EP (EndPoint) Ethernet Driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2020 Marvell.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/netdevice.h&gt;</div><div class='add'>+#include &lt;linux/etherdevice.h&gt;</div><div class='add'>+</div><div class='add'>+#include "octep_config.h"</div><div class='add'>+#include "octep_main.h"</div><div class='add'>+#include "octep_regs_cnxk_pf.h"</div><div class='add'>+</div><div class='add'>+/* We will support 128 pf's in control mbox */</div><div class='add'>+#define CTRL_MBOX_MAX_PF	128</div><div class='add'>+#define CTRL_MBOX_SZ		((size_t)(0x400000 / CTRL_MBOX_MAX_PF))</div><div class='add'>+</div><div class='add'>+/* Names of Hardware non-queue generic interrupts */</div><div class='add'>+static char *cnxk_non_ioq_msix_names[] = {</div><div class='add'>+	"epf_ire_rint",</div><div class='add'>+	"epf_ore_rint",</div><div class='add'>+	"epf_vfire_rint",</div><div class='add'>+	"epf_rsvd0",</div><div class='add'>+	"epf_vfore_rint",</div><div class='add'>+	"epf_rsvd1",</div><div class='add'>+	"epf_mbox_rint",</div><div class='add'>+	"epf_rsvd2_0",</div><div class='add'>+	"epf_rsvd2_1",</div><div class='add'>+	"epf_dma_rint",</div><div class='add'>+	"epf_dma_vf_rint",</div><div class='add'>+	"epf_rsvd3",</div><div class='add'>+	"epf_pp_vf_rint",</div><div class='add'>+	"epf_rsvd3",</div><div class='add'>+	"epf_misc_rint",</div><div class='add'>+	"epf_rsvd5",</div><div class='add'>+	/* Next 16 are for OEI_RINT */</div><div class='add'>+	"epf_oei_rint0",</div><div class='add'>+	"epf_oei_rint1",</div><div class='add'>+	"epf_oei_rint2",</div><div class='add'>+	"epf_oei_rint3",</div><div class='add'>+	"epf_oei_rint4",</div><div class='add'>+	"epf_oei_rint5",</div><div class='add'>+	"epf_oei_rint6",</div><div class='add'>+	"epf_oei_rint7",</div><div class='add'>+	"epf_oei_rint8",</div><div class='add'>+	"epf_oei_rint9",</div><div class='add'>+	"epf_oei_rint10",</div><div class='add'>+	"epf_oei_rint11",</div><div class='add'>+	"epf_oei_rint12",</div><div class='add'>+	"epf_oei_rint13",</div><div class='add'>+	"epf_oei_rint14",</div><div class='add'>+	"epf_oei_rint15",</div><div class='add'>+	/* IOQ interrupt */</div><div class='add'>+	"octeon_ep"</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Dump useful hardware CSRs for debug purpose */</div><div class='add'>+static void cnxk_dump_regs(struct octep_device *oct, int qno)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;oct-&gt;pdev-&gt;dev;</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "IQ-%d register dump\n", qno);</div><div class='add'>+	dev_info(dev, "R[%d]_IN_INSTR_DBELL[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_INSTR_DBELL(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_CONTROL[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_CONTROL(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_ENABLE[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_ENABLE(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_INSTR_BADDR[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_INSTR_BADDR(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_INSTR_RSIZE[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_INSTR_RSIZE(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_CNTS[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_CNTS(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_CNTS(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_INT_LEVELS[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_INT_LEVELS(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_PKT_CNT[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_PKT_CNT(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_PKT_CNT(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_IN_BYTE_CNT[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_IN_BYTE_CNT(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_IN_BYTE_CNT(qno)));</div><div class='add'>+</div><div class='add'>+	dev_info(dev, "OQ-%d register dump\n", qno);</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_SLIST_DBELL[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_SLIST_DBELL(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_CONTROL[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_CONTROL(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_ENABLE[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_ENABLE(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_SLIST_BADDR[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_SLIST_BADDR(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_SLIST_RSIZE[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_SLIST_RSIZE(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_CNTS[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_CNTS(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_CNTS(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_INT_LEVELS[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_INT_LEVELS(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_PKT_CNT[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_PKT_CNT(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_PKT_CNT(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_OUT_BYTE_CNT[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_OUT_BYTE_CNT(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_OUT_BYTE_CNT(qno)));</div><div class='add'>+	dev_info(dev, "R[%d]_ERR_TYPE[0x%llx]: 0x%016llx\n",</div><div class='add'>+		 qno, CNXK_SDP_R_ERR_TYPE(qno),</div><div class='add'>+		 octep_read_csr64(oct, CNXK_SDP_R_ERR_TYPE(qno)));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Reset Hardware Tx queue */</div><div class='add'>+static int cnxk_reset_iq(struct octep_device *oct, int q_no)</div><div class='add'>+{</div><div class='add'>+	struct octep_config *conf = oct-&gt;conf;</div><div class='add'>+	u64 val = 0ULL;</div><div class='add'>+</div><div class='add'>+	dev_dbg(&amp;oct-&gt;pdev-&gt;dev, "Reset PF IQ-%d\n", q_no);</div><div class='add'>+</div><div class='add'>+	/* Get absolute queue number */</div><div class='add'>+	q_no += conf-&gt;pf_ring_cfg.srn;</div><div class='add'>+</div><div class='add'>+	/* Disable the Tx/Instruction Ring */</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(q_no), val);</div><div class='add'>+</div><div class='add'>+	/* clear the Instruction Ring packet/byte counts and doorbell CSRs */</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_CNTS(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_PKT_CNT(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_BYTE_CNT(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(q_no), val);</div><div class='add'>+</div><div class='add'>+	val = 0xFFFFFFFF;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(q_no), val);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Reset Hardware Rx queue */</div><div class='add'>+static void cnxk_reset_oq(struct octep_device *oct, int q_no)</div><div class='add'>+{</div><div class='add'>+	u64 val = 0ULL;</div><div class='add'>+</div><div class='add'>+	q_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	/* Disable Output (Rx) Ring */</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(q_no), val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(q_no), val);</div><div class='add'>+</div><div class='add'>+	/* Clear count CSRs */</div><div class='add'>+	val = octep_read_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no));</div><div class='add'>+	octep_write_csr(oct, CNXK_SDP_R_OUT_CNTS(q_no), val);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_PKT_CNT(q_no), 0xFFFFFFFFFULL);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(q_no), 0xFFFFFFFF);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Reset all hardware Tx/Rx queues */</div><div class='add'>+static void octep_reset_io_queues_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	int q;</div><div class='add'>+</div><div class='add'>+	dev_dbg(&amp;pdev-&gt;dev, "Reset OCTEP_CNXK PF IO Queues\n");</div><div class='add'>+</div><div class='add'>+	for (q = 0; q &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); q++) {</div><div class='add'>+		cnxk_reset_iq(oct, q);</div><div class='add'>+		cnxk_reset_oq(oct, q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Initialize windowed addresses to access some hardware registers */</div><div class='add'>+static void octep_setup_pci_window_regs_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u8 __iomem *bar0_pciaddr = oct-&gt;mmio[0].hw_addr;</div><div class='add'>+</div><div class='add'>+	oct-&gt;pci_win_regs.pci_win_wr_addr = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_WR_ADDR64);</div><div class='add'>+	oct-&gt;pci_win_regs.pci_win_rd_addr = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_RD_ADDR64);</div><div class='add'>+	oct-&gt;pci_win_regs.pci_win_wr_data = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_WR_DATA64);</div><div class='add'>+	oct-&gt;pci_win_regs.pci_win_rd_data = (u8 __iomem *)(bar0_pciaddr + CNXK_SDP_WIN_RD_DATA64);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Configure Hardware mapping: inform hardware which rings belong to PF. */</div><div class='add'>+static void octep_configure_ring_mapping_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	struct octep_config *conf = oct-&gt;conf;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 pf_srn = CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	int q;</div><div class='add'>+</div><div class='add'>+	for (q = 0; q &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(conf); q++) {</div><div class='add'>+		u64 regval = 0;</div><div class='add'>+</div><div class='add'>+		if (oct-&gt;pcie_port)</div><div class='add'>+			regval = 8 &lt;&lt; CNXK_SDP_FUNC_SEL_EPF_BIT_POS;</div><div class='add'>+</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q), regval);</div><div class='add'>+</div><div class='add'>+		regval = octep_read_csr64(oct, CNXK_SDP_EPVF_RING(pf_srn + q));</div><div class='add'>+		dev_dbg(&amp;pdev-&gt;dev, "Write SDP_EPVF_RING[0x%llx] = 0x%llx\n",</div><div class='add'>+			CNXK_SDP_EPVF_RING(pf_srn + q), regval);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Initialize configuration limits and initial active config */</div><div class='add'>+static void octep_init_config_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	struct octep_config *conf = oct-&gt;conf;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u8 link = 0;</div><div class='add'>+	u64 val;</div><div class='add'>+	int pos;</div><div class='add'>+</div><div class='add'>+	/* Read ring configuration:</div><div class='add'>+	 * PF ring count, number of VFs and rings per VF supported</div><div class='add'>+	 */</div><div class='add'>+	val = octep_read_csr64(oct, CNXK_SDP_EPF_RINFO);</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "SDP_EPF_RINFO[0x%x]:0x%llx\n", CNXK_SDP_EPF_RINFO, val);</div><div class='add'>+	conf-&gt;sriov_cfg.max_rings_per_vf = CNXK_SDP_EPF_RINFO_RPVF(val);</div><div class='add'>+	conf-&gt;sriov_cfg.active_rings_per_vf = conf-&gt;sriov_cfg.max_rings_per_vf;</div><div class='add'>+	conf-&gt;sriov_cfg.max_vfs = CNXK_SDP_EPF_RINFO_NVFS(val);</div><div class='add'>+	conf-&gt;sriov_cfg.active_vfs = conf-&gt;sriov_cfg.max_vfs;</div><div class='add'>+	conf-&gt;sriov_cfg.vf_srn = CNXK_SDP_EPF_RINFO_SRN(val);</div><div class='add'>+</div><div class='add'>+	val = octep_read_csr64(oct, CNXK_SDP_MAC_PF_RING_CTL(oct-&gt;pcie_port));</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "SDP_MAC_PF_RING_CTL[%d]:0x%llx\n", oct-&gt;pcie_port, val);</div><div class='add'>+	conf-&gt;pf_ring_cfg.srn =  CNXK_SDP_MAC_PF_RING_CTL_SRN(val);</div><div class='add'>+	conf-&gt;pf_ring_cfg.max_io_rings = CNXK_SDP_MAC_PF_RING_CTL_RPPF(val);</div><div class='add'>+	conf-&gt;pf_ring_cfg.active_io_rings = conf-&gt;pf_ring_cfg.max_io_rings;</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n",</div><div class='add'>+		 conf-&gt;pf_ring_cfg.srn, conf-&gt;sriov_cfg.active_rings_per_vf,</div><div class='add'>+		 conf-&gt;sriov_cfg.active_vfs, conf-&gt;pf_ring_cfg.active_io_rings);</div><div class='add'>+</div><div class='add'>+	conf-&gt;iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS;</div><div class='add'>+	conf-&gt;iq.instr_type = OCTEP_64BYTE_INSTR;</div><div class='add'>+	conf-&gt;iq.db_min = OCTEP_DB_MIN;</div><div class='add'>+	conf-&gt;iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD;</div><div class='add'>+</div><div class='add'>+	conf-&gt;oq.num_descs = OCTEP_OQ_MAX_DESCRIPTORS;</div><div class='add'>+	conf-&gt;oq.buf_size = OCTEP_OQ_BUF_SIZE;</div><div class='add'>+	conf-&gt;oq.refill_threshold = OCTEP_OQ_REFILL_THRESHOLD;</div><div class='add'>+	conf-&gt;oq.oq_intr_pkt = OCTEP_OQ_INTR_PKT_THRESHOLD;</div><div class='add'>+	conf-&gt;oq.oq_intr_time = OCTEP_OQ_INTR_TIME_THRESHOLD;</div><div class='add'>+	conf-&gt;oq.wmark = OCTEP_OQ_WMARK_MIN;</div><div class='add'>+</div><div class='add'>+	conf-&gt;msix_cfg.non_ioq_msix = CNXK_NUM_NON_IOQ_INTR;</div><div class='add'>+	conf-&gt;msix_cfg.ioq_msix = conf-&gt;pf_ring_cfg.active_io_rings;</div><div class='add'>+	conf-&gt;msix_cfg.non_ioq_msix_names = cnxk_non_ioq_msix_names;</div><div class='add'>+</div><div class='add'>+	pos = pci_find_ext_capability(oct-&gt;pdev, PCI_EXT_CAP_ID_SRIOV);</div><div class='add'>+	if (pos) {</div><div class='add'>+		pci_read_config_byte(oct-&gt;pdev,</div><div class='add'>+				     pos + PCI_SRIOV_FUNC_LINK,</div><div class='add'>+				     &amp;link);</div><div class='add'>+		link = PCI_DEVFN(PCI_SLOT(oct-&gt;pdev-&gt;devfn), link);</div><div class='add'>+	}</div><div class='add'>+	conf-&gt;ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct-&gt;mmio[2].hw_addr +</div><div class='add'>+					   CNXK_PEM_BAR4_INDEX_OFFSET +</div><div class='add'>+					   (link * CTRL_MBOX_SZ);</div><div class='add'>+</div><div class='add'>+	conf-&gt;fw_info.hb_interval = OCTEP_DEFAULT_FW_HB_INTERVAL;</div><div class='add'>+	conf-&gt;fw_info.hb_miss_count = OCTEP_DEFAULT_FW_HB_MISS_COUNT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Setup registers for a hardware Tx Queue  */</div><div class='add'>+static void octep_setup_iq_regs_cnxk_pf(struct octep_device *oct, int iq_no)</div><div class='add'>+{</div><div class='add'>+	struct octep_iq *iq = oct-&gt;iq[iq_no];</div><div class='add'>+	u32 reset_instr_cnt;</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	iq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));</div><div class='add'>+</div><div class='add'>+	/* wait for IDLE to set to 1 */</div><div class='add'>+	if (!(reg_val &amp; CNXK_R_IN_CTL_IDLE)) {</div><div class='add'>+		do {</div><div class='add'>+			reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));</div><div class='add'>+		} while (!(reg_val &amp; CNXK_R_IN_CTL_IDLE));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_val |= CNXK_R_IN_CTL_RDSIZE;</div><div class='add'>+	reg_val |= CNXK_R_IN_CTL_IS_64B;</div><div class='add'>+	reg_val |= CNXK_R_IN_CTL_ESR;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val);</div><div class='add'>+</div><div class='add'>+	/* Write the start of the input queue's ring and its size  */</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_BADDR(iq_no),</div><div class='add'>+			  iq-&gt;desc_ring_dma);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_RSIZE(iq_no),</div><div class='add'>+			  iq-&gt;max_count);</div><div class='add'>+</div><div class='add'>+	/* Remember the doorbell &amp; instruction count register addr</div><div class='add'>+	 * for this queue</div><div class='add'>+	 */</div><div class='add'>+	iq-&gt;doorbell_reg = oct-&gt;mmio[0].hw_addr +</div><div class='add'>+			   CNXK_SDP_R_IN_INSTR_DBELL(iq_no);</div><div class='add'>+	iq-&gt;inst_cnt_reg = oct-&gt;mmio[0].hw_addr +</div><div class='add'>+			   CNXK_SDP_R_IN_CNTS(iq_no);</div><div class='add'>+	iq-&gt;intr_lvl_reg = oct-&gt;mmio[0].hw_addr +</div><div class='add'>+			   CNXK_SDP_R_IN_INT_LEVELS(iq_no);</div><div class='add'>+</div><div class='add'>+	/* Store the current instruction counter (used in flush_iq calculation) */</div><div class='add'>+	reset_instr_cnt = readl(iq-&gt;inst_cnt_reg);</div><div class='add'>+	writel(reset_instr_cnt, iq-&gt;inst_cnt_reg);</div><div class='add'>+</div><div class='add'>+	/* INTR_THRESHOLD is set to max(FFFFFFFF) to disable the INTR */</div><div class='add'>+	reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct-&gt;conf) &amp; 0xffffffff;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Setup registers for a hardware Rx Queue  */</div><div class='add'>+static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val;</div><div class='add'>+	u64 oq_ctl = 0ULL;</div><div class='add'>+	u32 time_threshold = 0;</div><div class='add'>+	struct octep_oq *oq = oct-&gt;oq[oq_no];</div><div class='add'>+</div><div class='add'>+	oq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no));</div><div class='add'>+</div><div class='add'>+	/* wait for IDLE to set to 1 */</div><div class='add'>+	if (!(reg_val &amp; CNXK_R_OUT_CTL_IDLE)) {</div><div class='add'>+		do {</div><div class='add'>+			reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no));</div><div class='add'>+		} while (!(reg_val &amp; CNXK_R_OUT_CTL_IDLE));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_IMODE);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_ROR_P);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_NSR_P);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_ROR_I);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_NSR_I);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_ES_I);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_ROR_D);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_NSR_D);</div><div class='add'>+	reg_val &amp;= ~(CNXK_R_OUT_CTL_ES_D);</div><div class='add'>+	reg_val |= (CNXK_R_OUT_CTL_ES_P);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no),</div><div class='add'>+			  oq-&gt;desc_ring_dma);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no),</div><div class='add'>+			  oq-&gt;max_count);</div><div class='add'>+</div><div class='add'>+	oq_ctl = octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no));</div><div class='add'>+</div><div class='add'>+	/* Clear the ISIZE and BSIZE (22-0) */</div><div class='add'>+	oq_ctl &amp;= ~0x7fffffULL;</div><div class='add'>+</div><div class='add'>+	/* Populate the BSIZE (15-0) */</div><div class='add'>+	oq_ctl |= (oq-&gt;buffer_size &amp; 0xffff);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), oq_ctl);</div><div class='add'>+</div><div class='add'>+	/* Get the mapped address of the pkt_sent and pkts_credit regs */</div><div class='add'>+	oq-&gt;pkts_sent_reg = oct-&gt;mmio[0].hw_addr + CNXK_SDP_R_OUT_CNTS(oq_no);</div><div class='add'>+	oq-&gt;pkts_credit_reg = oct-&gt;mmio[0].hw_addr +</div><div class='add'>+			      CNXK_SDP_R_OUT_SLIST_DBELL(oq_no);</div><div class='add'>+</div><div class='add'>+	time_threshold = CFG_GET_OQ_INTR_TIME(oct-&gt;conf);</div><div class='add'>+	reg_val = ((u64)time_threshold &lt;&lt; 32) |</div><div class='add'>+		  CFG_GET_OQ_INTR_PKT(oct-&gt;conf);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);</div><div class='add'>+</div><div class='add'>+	/* set watermark for backpressure */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no));</div><div class='add'>+	reg_val &amp;= ~0xFFFFFFFFULL;</div><div class='add'>+	reg_val |= CFG_GET_OQ_WMARK(oct-&gt;conf);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Setup registers for a PF mailbox */</div><div class='add'>+static void octep_setup_mbox_regs_cnxk_pf(struct octep_device *oct, int q_no)</div><div class='add'>+{</div><div class='add'>+	struct octep_mbox *mbox = oct-&gt;mbox[q_no];</div><div class='add'>+</div><div class='add'>+	/* PF to VF DATA reg. PF writes into this reg */</div><div class='add'>+	mbox-&gt;pf_vf_data_reg = oct-&gt;mmio[0].hw_addr + CNXK_SDP_MBOX_PF_VF_DATA(q_no);</div><div class='add'>+</div><div class='add'>+	/* VF to PF DATA reg. PF reads from this reg */</div><div class='add'>+	mbox-&gt;vf_pf_data_reg = oct-&gt;mmio[0].hw_addr + CNXK_SDP_MBOX_VF_PF_DATA(q_no);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_poll_pfvf_mailbox_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u32 vf, active_vfs, active_rings_per_vf, vf_mbox_queue;</div><div class='add'>+	u64 reg0;</div><div class='add'>+</div><div class='add'>+	reg0 = octep_read_csr64(oct, CNXK_SDP_EPF_MBOX_RINT(0));</div><div class='add'>+	if (reg0) {</div><div class='add'>+		active_vfs = CFG_GET_ACTIVE_VFS(oct-&gt;conf);</div><div class='add'>+		active_rings_per_vf = CFG_GET_ACTIVE_RPVF(oct-&gt;conf);</div><div class='add'>+		for (vf = 0; vf &lt; active_vfs; vf++) {</div><div class='add'>+			vf_mbox_queue = vf * active_rings_per_vf;</div><div class='add'>+			if (!(reg0 &amp; (0x1UL &lt;&lt; vf_mbox_queue)))</div><div class='add'>+				continue;</div><div class='add'>+</div><div class='add'>+			if (!oct-&gt;mbox[vf_mbox_queue]) {</div><div class='add'>+				dev_err(&amp;oct-&gt;pdev-&gt;dev, "bad mbox vf %d\n", vf);</div><div class='add'>+				continue;</div><div class='add'>+			}</div><div class='add'>+			schedule_work(&amp;oct-&gt;mbox[vf_mbox_queue]-&gt;wk.work);</div><div class='add'>+		}</div><div class='add'>+		if (reg0)</div><div class='add'>+			octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT(0), reg0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t octep_pfvf_mbox_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+</div><div class='add'>+	octep_poll_pfvf_mailbox_cnxk_pf(oct);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Poll OEI events like heartbeat */</div><div class='add'>+static void octep_poll_oei_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u64 reg0;</div><div class='add'>+</div><div class='add'>+	/* Check for OEI INTR */</div><div class='add'>+	reg0 = octep_read_csr64(oct, CNXK_SDP_EPF_OEI_RINT);</div><div class='add'>+	if (reg0) {</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT, reg0);</div><div class='add'>+		if (reg0 &amp; CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)</div><div class='add'>+			queue_work(octep_wq, &amp;oct-&gt;ctrl_mbox_task);</div><div class='add'>+		if (reg0 &amp; CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT)</div><div class='add'>+			atomic_set(&amp;oct-&gt;hb_miss_cnt, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* OEI interrupt handler */</div><div class='add'>+static irqreturn_t octep_oei_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+</div><div class='add'>+	octep_poll_oei_cnxk_pf(oct);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Process non-ioq interrupts required to keep pf interface running.</div><div class='add'>+ * OEI_RINT is needed for control mailbox</div><div class='add'>+ * MBOX_RINT is needed for pfvf mailbox</div><div class='add'>+ */</div><div class='add'>+static void octep_poll_non_ioq_interrupts_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	octep_poll_pfvf_mailbox_cnxk_pf(oct);</div><div class='add'>+	octep_poll_oei_cnxk_pf(oct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for input ring error interrupts. */</div><div class='add'>+static irqreturn_t octep_ire_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for IRERR INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_IRERR_RINT);</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "received IRERR_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT, reg_val);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); i++) {</div><div class='add'>+			reg_val = octep_read_csr64(oct,</div><div class='add'>+						   CNXK_SDP_R_ERR_TYPE(i));</div><div class='add'>+			if (reg_val) {</div><div class='add'>+				dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+					 "Received err type on IQ-%d: 0x%llx\n",</div><div class='add'>+					 i, reg_val);</div><div class='add'>+				octep_write_csr64(oct, CNXK_SDP_R_ERR_TYPE(i),</div><div class='add'>+						  reg_val);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for output ring error interrupts. */</div><div class='add'>+static irqreturn_t octep_ore_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+	int i = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for ORERR INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_ORERR_RINT);</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received ORERR_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT, reg_val);</div><div class='add'>+		for (i = 0; i &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); i++) {</div><div class='add'>+			reg_val = octep_read_csr64(oct, CNXK_SDP_R_ERR_TYPE(i));</div><div class='add'>+			if (reg_val) {</div><div class='add'>+				dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+					 "Received err type on OQ-%d: 0x%llx\n",</div><div class='add'>+					 i, reg_val);</div><div class='add'>+				octep_write_csr64(oct, CNXK_SDP_R_ERR_TYPE(i),</div><div class='add'>+						  reg_val);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for vf input ring error interrupts. */</div><div class='add'>+static irqreturn_t octep_vfire_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for VFIRE INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0));</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received VFIRE_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT(0), reg_val);</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for vf output ring error interrupts. */</div><div class='add'>+static irqreturn_t octep_vfore_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for VFORE INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0));</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received VFORE_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT(0), reg_val);</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for dpi dma related interrupts. */</div><div class='add'>+static irqreturn_t octep_dma_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for DMA INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_RINT);</div><div class='add'>+	if (reg_val)</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT, reg_val);</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for dpi dma transaction error interrupts for VFs  */</div><div class='add'>+static irqreturn_t octep_dma_vf_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for DMA VF INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0));</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received DMA_VF_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT(0), reg_val);</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for pp transaction error interrupts for VFs  */</div><div class='add'>+static irqreturn_t octep_pp_vf_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for PPVF INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0));</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received PP_VF_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT(0), reg_val);</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupt handler for mac related interrupts. */</div><div class='add'>+static irqreturn_t octep_misc_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	u64 reg_val = 0;</div><div class='add'>+</div><div class='add'>+	/* Check for MISC INTR */</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_MISC_RINT);</div><div class='add'>+	if (reg_val) {</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+			 "Received MISC_RINT intr: 0x%llx\n", reg_val);</div><div class='add'>+		octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT, reg_val);</div><div class='add'>+	}</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Interrupts handler for all reserved interrupts. */</div><div class='add'>+static irqreturn_t octep_rsvd_intr_handler_cnxk_pf(void *dev)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = (struct octep_device *)dev;</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+</div><div class='add'>+	dev_info(&amp;pdev-&gt;dev, "Reserved interrupts raised; Ignore\n");</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Tx/Rx queue interrupt handler */</div><div class='add'>+static irqreturn_t octep_ioq_intr_handler_cnxk_pf(void *data)</div><div class='add'>+{</div><div class='add'>+	struct octep_ioq_vector *vector = (struct octep_ioq_vector *)data;</div><div class='add'>+	struct octep_oq *oq = vector-&gt;oq;</div><div class='add'>+</div><div class='add'>+	napi_schedule_irqoff(oq-&gt;napi);</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* soft reset */</div><div class='add'>+static int octep_soft_reset_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	dev_info(&amp;oct-&gt;pdev-&gt;dev, "CNXKXX: Doing soft reset\n");</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_WIN_WR_MASK_REG, 0xFF);</div><div class='add'>+</div><div class='add'>+	/* Firmware status CSR is supposed to be cleared by</div><div class='add'>+	 * core domain reset, but due to a hw bug, it is not.</div><div class='add'>+	 * Set it to RUNNING right before reset so that it is not</div><div class='add'>+	 * left in READY (1) state after a reset.  This is required</div><div class='add'>+	 * in addition to the early setting to handle the case where</div><div class='add'>+	 * the OcteonTX is unexpectedly reset, reboots, and then</div><div class='add'>+	 * the module is removed.</div><div class='add'>+	 */</div><div class='add'>+	OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL),</div><div class='add'>+			    FW_STATUS_RUNNING);</div><div class='add'>+</div><div class='add'>+	/* Set chip domain reset bit */</div><div class='add'>+	OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1);</div><div class='add'>+	/* Wait till Octeon resets. */</div><div class='add'>+	mdelay(10);</div><div class='add'>+	/* restore the  reset value */</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_WIN_WR_MASK_REG, 0xFF);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Re-initialize Octeon hardware registers */</div><div class='add'>+static void octep_reinit_regs_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); i++)</div><div class='add'>+		oct-&gt;hw_ops.setup_iq_regs(oct, i);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); i++)</div><div class='add'>+		oct-&gt;hw_ops.setup_oq_regs(oct, i);</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.enable_interrupts(oct);</div><div class='add'>+	oct-&gt;hw_ops.enable_io_queues(oct);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); i++)</div><div class='add'>+		writel(oct-&gt;oq[i]-&gt;max_count, oct-&gt;oq[i]-&gt;pkts_credit_reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable all interrupts */</div><div class='add'>+static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u64 intr_mask = 0ULL;</div><div class='add'>+	int srn, num_rings, i;</div><div class='add'>+</div><div class='add'>+	srn = CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_rings; i++)</div><div class='add'>+		intr_mask |= (0x1ULL &lt;&lt; (srn + i));</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1S, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1S, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT_ENA_W1S, -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Disable all interrupts */</div><div class='add'>+static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u64 intr_mask = 0ULL;</div><div class='add'>+	int srn, num_rings, i;</div><div class='add'>+</div><div class='add'>+	srn = CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_rings; i++)</div><div class='add'>+		intr_mask |= (0x1ULL &lt;&lt; (srn + i));</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT_ENA_W1C, -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_VFORE_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Get new Octeon Read Index: index of descriptor that Octeon reads next. */</div><div class='add'>+static u32 octep_update_iq_read_index_cnxk_pf(struct octep_iq *iq)</div><div class='add'>+{</div><div class='add'>+	u32 pkt_in_done = readl(iq-&gt;inst_cnt_reg);</div><div class='add'>+	u32 last_done, new_idx;</div><div class='add'>+</div><div class='add'>+	last_done = pkt_in_done - iq-&gt;pkt_in_done;</div><div class='add'>+	iq-&gt;pkt_in_done = pkt_in_done;</div><div class='add'>+</div><div class='add'>+	new_idx = (iq-&gt;octep_read_index + last_done) % iq-&gt;max_count;</div><div class='add'>+</div><div class='add'>+	return new_idx;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable a hardware Tx Queue */</div><div class='add'>+static void octep_enable_iq_cnxk_pf(struct octep_device *oct, int iq_no)</div><div class='add'>+{</div><div class='add'>+	u64 loop = HZ;</div><div class='add'>+	u64 reg_val;</div><div class='add'>+</div><div class='add'>+	iq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(iq_no), 0xFFFFFFFF);</div><div class='add'>+</div><div class='add'>+	while (octep_read_csr64(oct, CNXK_SDP_R_IN_INSTR_DBELL(iq_no)) &amp;&amp;</div><div class='add'>+	       loop--) {</div><div class='add'>+		schedule_timeout_interruptible(1);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	reg_val = octep_read_csr64(oct,  CNXK_SDP_R_IN_INT_LEVELS(iq_no));</div><div class='add'>+	reg_val |= (0x1ULL &lt;&lt; 62);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(iq_no), reg_val);</div><div class='add'>+</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no));</div><div class='add'>+	reg_val |= 0x1ULL;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable a hardware Rx Queue */</div><div class='add'>+static void octep_enable_oq_cnxk_pf(struct octep_device *oct, int oq_no)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val = 0ULL;</div><div class='add'>+</div><div class='add'>+	oq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	reg_val = octep_read_csr64(oct,  CNXK_SDP_R_OUT_INT_LEVELS(oq_no));</div><div class='add'>+	reg_val |= (0x1ULL &lt;&lt; 62);</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);</div><div class='add'>+</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_DBELL(oq_no), 0xFFFFFFFF);</div><div class='add'>+</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no));</div><div class='add'>+	reg_val |= 0x1ULL;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Enable all hardware Tx/Rx Queues assined to PF */</div><div class='add'>+static void octep_enable_io_queues_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u8 q;</div><div class='add'>+</div><div class='add'>+	for (q = 0; q &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); q++) {</div><div class='add'>+		octep_enable_iq_cnxk_pf(oct, q);</div><div class='add'>+		octep_enable_oq_cnxk_pf(oct, q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Disable a hardware Tx Queue assined to PF */</div><div class='add'>+static void octep_disable_iq_cnxk_pf(struct octep_device *oct, int iq_no)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val = 0ULL;</div><div class='add'>+</div><div class='add'>+	iq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no));</div><div class='add'>+	reg_val &amp;= ~0x1ULL;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_IN_ENABLE(iq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Disable a hardware Rx Queue assined to PF */</div><div class='add'>+static void octep_disable_oq_cnxk_pf(struct octep_device *oct, int oq_no)</div><div class='add'>+{</div><div class='add'>+	u64 reg_val = 0ULL;</div><div class='add'>+</div><div class='add'>+	oq_no += CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no));</div><div class='add'>+	reg_val &amp;= ~0x1ULL;</div><div class='add'>+	octep_write_csr64(oct, CNXK_SDP_R_OUT_ENABLE(oq_no), reg_val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Disable all hardware Tx/Rx Queues assined to PF */</div><div class='add'>+static void octep_disable_io_queues_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	int q = 0;</div><div class='add'>+</div><div class='add'>+	for (q = 0; q &lt; CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf); q++) {</div><div class='add'>+		octep_disable_iq_cnxk_pf(oct, q);</div><div class='add'>+		octep_disable_oq_cnxk_pf(oct, q);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* Dump hardware registers (including Tx/Rx queues) for debugging. */</div><div class='add'>+static void octep_dump_registers_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	u8 srn, num_rings, q;</div><div class='add'>+</div><div class='add'>+	srn = CFG_GET_PORTS_PF_SRN(oct-&gt;conf);</div><div class='add'>+	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	for (q = srn; q &lt; srn + num_rings; q++)</div><div class='add'>+		cnxk_dump_regs(oct, q);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * octep_device_setup_cnxk_pf() - Setup Octeon device.</div><div class='add'>+ *</div><div class='add'>+ * @oct: Octeon device private data structure.</div><div class='add'>+ *</div><div class='add'>+ * - initialize hardware operations.</div><div class='add'>+ * - get target side pcie port number for the device.</div><div class='add'>+ * - setup window access to hardware registers.</div><div class='add'>+ * - set initial configuration and max limits.</div><div class='add'>+ * - setup hardware mapping of rings to the PF device.</div><div class='add'>+ */</div><div class='add'>+void octep_device_setup_cnxk_pf(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	oct-&gt;hw_ops.setup_iq_regs = octep_setup_iq_regs_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.setup_oq_regs = octep_setup_oq_regs_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.mbox_intr_handler = octep_pfvf_mbox_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.oei_intr_handler = octep_oei_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.ire_intr_handler = octep_ire_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.ore_intr_handler = octep_ore_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.vfire_intr_handler = octep_vfire_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.vfore_intr_handler = octep_vfore_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.dma_intr_handler = octep_dma_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.dma_vf_intr_handler = octep_dma_vf_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.pp_vf_intr_handler = octep_pp_vf_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.misc_intr_handler = octep_misc_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.soft_reset = octep_soft_reset_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.reinit_regs = octep_reinit_regs_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.enable_interrupts = octep_enable_interrupts_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.disable_interrupts = octep_disable_interrupts_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.poll_non_ioq_interrupts = octep_poll_non_ioq_interrupts_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.update_iq_read_idx = octep_update_iq_read_index_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.enable_iq = octep_enable_iq_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.enable_oq = octep_enable_oq_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.enable_io_queues = octep_enable_io_queues_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.disable_iq = octep_disable_iq_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.disable_oq = octep_disable_oq_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.disable_io_queues = octep_disable_io_queues_cnxk_pf;</div><div class='add'>+	oct-&gt;hw_ops.reset_io_queues = octep_reset_io_queues_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	oct-&gt;hw_ops.dump_registers = octep_dump_registers_cnxk_pf;</div><div class='add'>+</div><div class='add'>+	octep_setup_pci_window_regs_cnxk_pf(oct);</div><div class='add'>+</div><div class='add'>+	oct-&gt;pcie_port = octep_read_csr64(oct, CNXK_SDP_MAC_NUMBER) &amp; 0xff;</div><div class='add'>+	dev_info(&amp;oct-&gt;pdev-&gt;dev,</div><div class='add'>+		 "Octeon device using PCIE Port %d\n", oct-&gt;pcie_port);</div><div class='add'>+</div><div class='add'>+	octep_init_config_cnxk_pf(oct);</div><div class='add'>+	octep_configure_ring_mapping_cnxk_pf(oct);</div><div class='add'>+</div><div class='add'>+	/* Firmware status CSR is supposed to be cleared by</div><div class='add'>+	 * core domain reset, but due to IPBUPEM-38842, it is not.</div><div class='add'>+	 * Set it to RUNNING early in boot, so that unexpected resets</div><div class='add'>+	 * leave it in a state that is not READY (1).</div><div class='add'>+	 */</div><div class='add'>+	OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL),</div><div class='add'>+			    FW_STATUS_RUNNING);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_config.h b/drivers/net/ethernet/marvell/octeon_ep/octep_config.h<br/>index 1622a6ebf036..1627660175c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_config.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_config.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_config.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_config.h</a></div><div class='hunk'>@@ -13,12 +13,16 @@</div><div class='ctx'> #define OCTEP_64BYTE_INSTR  64</div><div class='ctx'> </div><div class='ctx'> /* Tx Queue: maximum descriptors per ring */</div><div class='add'>+/* This needs to be a power of 2 */</div><div class='ctx'> #define OCTEP_IQ_MAX_DESCRIPTORS    1024</div><div class='ctx'> /* Minimum input (Tx) requests to be enqueued to ring doorbell */</div><div class='del'>-#define OCTEP_DB_MIN                1</div><div class='add'>+#define OCTEP_DB_MIN                8</div><div class='ctx'> /* Packet threshold for Tx queue interrupt */</div><div class='ctx'> #define OCTEP_IQ_INTR_THRESHOLD     0x0</div><div class='ctx'> </div><div class='add'>+/* Minimum watermark for backpressure */</div><div class='add'>+#define OCTEP_OQ_WMARK_MIN 256</div><div class='add'>+</div><div class='ctx'> /* Rx Queue: maximum descriptors per ring */</div><div class='ctx'> #define OCTEP_OQ_MAX_DESCRIPTORS   1024</div><div class='ctx'> </div><div class='hunk'>@@ -44,8 +48,6 @@</div><div class='ctx'> </div><div class='ctx'> /* Minimum MTU supported by Octeon network interface */</div><div class='ctx'> #define OCTEP_MIN_MTU        ETH_MIN_MTU</div><div class='del'>-/* Maximum MTU supported by Octeon interface*/</div><div class='del'>-#define OCTEP_MAX_MTU        (10000 - (ETH_HLEN + ETH_FCS_LEN))</div><div class='ctx'> /* Default MTU */</div><div class='ctx'> #define OCTEP_DEFAULT_MTU    1500</div><div class='ctx'> </div><div class='hunk'>@@ -58,7 +60,6 @@</div><div class='ctx'> #define CFG_GET_IQ_CFG(cfg)             ((cfg)-&gt;iq)</div><div class='ctx'> #define CFG_GET_IQ_NUM_DESC(cfg)        ((cfg)-&gt;iq.num_descs)</div><div class='ctx'> #define CFG_GET_IQ_INSTR_TYPE(cfg)      ((cfg)-&gt;iq.instr_type)</div><div class='del'>-#define CFG_GET_IQ_PKIND(cfg)           ((cfg)-&gt;iq.pkind)</div><div class='ctx'> #define CFG_GET_IQ_INSTR_SIZE(cfg)      (64)</div><div class='ctx'> #define CFG_GET_IQ_DB_MIN(cfg)          ((cfg)-&gt;iq.db_min)</div><div class='ctx'> #define CFG_GET_IQ_INTR_THRESHOLD(cfg)  ((cfg)-&gt;iq.intr_threshold)</div><div class='hunk'>@@ -68,12 +69,12 @@</div><div class='ctx'> #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)  ((cfg)-&gt;oq.refill_threshold)</div><div class='ctx'> #define CFG_GET_OQ_INTR_PKT(cfg)          ((cfg)-&gt;oq.oq_intr_pkt)</div><div class='ctx'> #define CFG_GET_OQ_INTR_TIME(cfg)         ((cfg)-&gt;oq.oq_intr_time)</div><div class='add'>+#define CFG_GET_OQ_WMARK(cfg)             ((cfg)-&gt;oq.wmark)</div><div class='ctx'> </div><div class='ctx'> #define CFG_GET_PORTS_MAX_IO_RINGS(cfg)    ((cfg)-&gt;pf_ring_cfg.max_io_rings)</div><div class='ctx'> #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)-&gt;pf_ring_cfg.active_io_rings)</div><div class='ctx'> #define CFG_GET_PORTS_PF_SRN(cfg)          ((cfg)-&gt;pf_ring_cfg.srn)</div><div class='ctx'> </div><div class='del'>-#define CFG_GET_DPI_PKIND(cfg)            ((cfg)-&gt;core_cfg.dpi_pkind)</div><div class='ctx'> #define CFG_GET_CORE_TICS_PER_US(cfg)     ((cfg)-&gt;core_cfg.core_tics_per_us)</div><div class='ctx'> #define CFG_GET_COPROC_TICS_PER_US(cfg)   ((cfg)-&gt;core_cfg.coproc_tics_per_us)</div><div class='ctx'> </div><div class='hunk'>@@ -97,9 +98,6 @@ struct octep_iq_config {</div><div class='ctx'> 	/* Command size - 32 or 64 bytes */</div><div class='ctx'> 	u16 instr_type;</div><div class='ctx'> </div><div class='del'>-	/* pkind for packets sent to Octeon */</div><div class='del'>-	u16 pkind;</div><div class='del'>-</div><div class='ctx'> 	/* Minimum number of commands pending to be posted to Octeon before driver</div><div class='ctx'> 	 * hits the Input queue doorbell.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -137,6 +135,12 @@ struct octep_oq_config {</div><div class='ctx'> 	 * default. The time is specified in microseconds.</div><div class='ctx'> 	 */</div><div class='ctx'> 	u32 oq_intr_time;</div><div class='add'>+</div><div class='add'>+	/* Water mark for backpressure.</div><div class='add'>+	 * Output queue sends backpressure signal to source when</div><div class='add'>+	 * free buffer count falls below wmark.</div><div class='add'>+	 */</div><div class='add'>+	u32 wmark;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Tx/Rx configuration */</div><div class='hunk'>@@ -189,11 +193,37 @@ struct octep_ctrl_mbox_config {</div><div class='ctx'> /* Info from firmware */</div><div class='ctx'> struct octep_fw_info {</div><div class='ctx'> 	/* interface pkind */</div><div class='del'>-	u16 pkind;</div><div class='add'>+	u8 pkind;</div><div class='add'>+</div><div class='add'>+	/* front size data */</div><div class='add'>+	u8 fsz;</div><div class='add'>+</div><div class='ctx'> 	/* heartbeat interval in milliseconds */</div><div class='ctx'> 	u16 hb_interval;</div><div class='add'>+</div><div class='ctx'> 	/* heartbeat miss count */</div><div class='ctx'> 	u16 hb_miss_count;</div><div class='add'>+</div><div class='add'>+	/* reserved */</div><div class='add'>+	u16 reserved1;</div><div class='add'>+</div><div class='add'>+	/* supported rx offloads OCTEP_ETH_RX_OFFLOAD_* */</div><div class='add'>+	u16 rx_ol_flags;</div><div class='add'>+</div><div class='add'>+	/* supported tx offloads OCTEP_ETH_TX_OFFLOAD_* */</div><div class='add'>+	u16 tx_ol_flags;</div><div class='add'>+</div><div class='add'>+	/* reserved */</div><div class='add'>+	u32 reserved_offloads;</div><div class='add'>+</div><div class='add'>+	/* extra offload flags */</div><div class='add'>+	u64 ext_ol_flags;</div><div class='add'>+</div><div class='add'>+	/* supported features */</div><div class='add'>+	u64 features[2];</div><div class='add'>+</div><div class='add'>+	/* reserved */</div><div class='add'>+	u64 reserved2[3];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Data Structure to hold configuration limits and active config */</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h b/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h<br/>index 7f8135788efc..6da32d40f926 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.h</a></div><div class='hunk'>@@ -16,10 +16,12 @@</div><div class='ctx'>  * |reserved (4 bytes)                         |</div><div class='ctx'>  * |-------------------------------------------|</div><div class='ctx'>  * |host version (8 bytes)                     |</div><div class='add'>+ * |    low 32 bits                            |</div><div class='ctx'>  * |host status (8 bytes)                      |</div><div class='ctx'>  * |host reserved (104 bytes)                  |</div><div class='ctx'>  * |-------------------------------------------|</div><div class='del'>- * |fw version (8 bytes)                       |</div><div class='add'>+ * |fw version's (8 bytes)                     |</div><div class='add'>+ * |    min=high 32 bits, max=low 32 bits      |</div><div class='ctx'>  * |fw status (8 bytes)                        |</div><div class='ctx'>  * |fw reserved (104 bytes)                    |</div><div class='ctx'>  * |===========================================|</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c b/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c<br/>index 0594607a2585..01b7be154c38 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c</a></div><div class='hunk'>@@ -13,6 +13,7 @@</div><div class='ctx'> #include "octep_config.h"</div><div class='ctx'> #include "octep_main.h"</div><div class='ctx'> #include "octep_ctrl_net.h"</div><div class='add'>+#include "octep_pfvf_mbox.h"</div><div class='ctx'> </div><div class='ctx'> /* Control plane version */</div><div class='ctx'> #define OCTEP_CP_VERSION_CURRENT	OCTEP_CP_VERSION(1, 0, 0)</div><div class='hunk'>@@ -22,12 +23,15 @@ static const u32 mtu_sz = sizeof(struct octep_ctrl_net_h2f_req_cmd_mtu);</div><div class='ctx'> static const u32 mac_sz = sizeof(struct octep_ctrl_net_h2f_req_cmd_mac);</div><div class='ctx'> static const u32 state_sz = sizeof(struct octep_ctrl_net_h2f_req_cmd_state);</div><div class='ctx'> static const u32 link_info_sz = sizeof(struct octep_ctrl_net_link_info);</div><div class='add'>+static const u32 offloads_sz = sizeof(struct octep_ctrl_net_offloads);</div><div class='ctx'> static atomic_t ctrl_net_msg_id;</div><div class='ctx'> </div><div class='ctx'> /* Control plane version in which OCTEP_CTRL_NET_H2F_CMD was added */</div><div class='ctx'> static const u32 octep_ctrl_net_h2f_cmd_versions[OCTEP_CTRL_NET_H2F_CMD_MAX] = {</div><div class='del'>-	[OCTEP_CTRL_NET_H2F_CMD_INVALID ... OCTEP_CTRL_NET_H2F_CMD_GET_INFO] =</div><div class='del'>-	 OCTEP_CP_VERSION(1, 0, 0)</div><div class='add'>+	[OCTEP_CTRL_NET_H2F_CMD_INVALID ... OCTEP_CTRL_NET_H2F_CMD_DEV_REMOVE] =</div><div class='add'>+	 OCTEP_CP_VERSION(1, 0, 0),</div><div class='add'>+	[OCTEP_CTRL_NET_H2F_CMD_OFFLOADS] = OCTEP_CP_VERSION(1, 0, 1)</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Control plane version in which OCTEP_CTRL_NET_F2H_CMD was added */</div><div class='hunk'>@@ -122,7 +126,7 @@ int octep_ctrl_net_init(struct octep_device *oct)</div><div class='ctx'> </div><div class='ctx'> int octep_ctrl_net_get_link_status(struct octep_device *oct, int vfid)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -139,7 +143,7 @@ int octep_ctrl_net_get_link_status(struct octep_device *oct, int vfid)</div><div class='ctx'> int octep_ctrl_net_set_link_status(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> 				   bool wait_for_response)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> </div><div class='ctx'> 	init_send_req(&amp;d.msg, req, state_sz, vfid);</div><div class='hunk'>@@ -154,7 +158,7 @@ int octep_ctrl_net_set_link_status(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> int octep_ctrl_net_set_rx_state(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> 				bool wait_for_response)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> </div><div class='ctx'> 	init_send_req(&amp;d.msg, req, state_sz, vfid);</div><div class='hunk'>@@ -168,7 +172,7 @@ int octep_ctrl_net_set_rx_state(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> </div><div class='ctx'> int octep_ctrl_net_get_mac_addr(struct octep_device *oct, int vfid, u8 *addr)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -187,7 +191,7 @@ int octep_ctrl_net_get_mac_addr(struct octep_device *oct, int vfid, u8 *addr)</div><div class='ctx'> int octep_ctrl_net_set_mac_addr(struct octep_device *oct, int vfid, u8 *addr,</div><div class='ctx'> 				bool wait_for_response)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> </div><div class='ctx'> 	init_send_req(&amp;d.msg, req, mac_sz, vfid);</div><div class='hunk'>@@ -198,10 +202,28 @@ int octep_ctrl_net_set_mac_addr(struct octep_device *oct, int vfid, u8 *addr,</div><div class='ctx'> 	return octep_send_mbox_req(oct, &amp;d, wait_for_response);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int octep_ctrl_net_get_mtu(struct octep_device *oct, int vfid)</div><div class='add'>+{</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='add'>+	struct octep_ctrl_net_h2f_req *req;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	req = &amp;d.data.req;</div><div class='add'>+	init_send_req(&amp;d.msg, req, mtu_sz, vfid);</div><div class='add'>+	req-&gt;hdr.s.cmd = OCTEP_CTRL_NET_H2F_CMD_MTU;</div><div class='add'>+	req-&gt;mtu.cmd = OCTEP_CTRL_NET_CMD_GET;</div><div class='add'>+</div><div class='add'>+	err = octep_send_mbox_req(oct, &amp;d, true);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return d.data.resp.mtu.val;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int octep_ctrl_net_set_mtu(struct octep_device *oct, int vfid, int mtu,</div><div class='ctx'> 			   bool wait_for_response)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> </div><div class='ctx'> 	init_send_req(&amp;d.msg, req, mtu_sz, vfid);</div><div class='hunk'>@@ -216,7 +238,7 @@ int octep_ctrl_net_get_if_stats(struct octep_device *oct, int vfid,</div><div class='ctx'> 				struct octep_iface_rx_stats *rx_stats,</div><div class='ctx'> 				struct octep_iface_tx_stats *tx_stats)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> 	struct octep_ctrl_net_h2f_resp *resp;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -236,7 +258,7 @@ int octep_ctrl_net_get_if_stats(struct octep_device *oct, int vfid,</div><div class='ctx'> int octep_ctrl_net_get_link_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 				 struct octep_iface_link_info *link_info)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> 	struct octep_ctrl_net_h2f_resp *resp;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -262,7 +284,7 @@ int octep_ctrl_net_set_link_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 				 struct octep_iface_link_info *link_info,</div><div class='ctx'> 				 bool wait_for_response)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req = &amp;d.data.req;</div><div class='ctx'> </div><div class='ctx'> 	init_send_req(&amp;d.msg, req, link_info_sz, vfid);</div><div class='hunk'>@@ -308,6 +330,11 @@ static int process_mbox_notify(struct octep_device *oct,</div><div class='ctx'> 	    octep_ctrl_net_f2h_cmd_versions[cmd] &lt; OCTEP_CP_VERSION_CURRENT)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='add'>+	if (msg-&gt;hdr.s.is_vf) {</div><div class='add'>+		octep_pfvf_notify(oct, msg);</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	switch (cmd) {</div><div class='ctx'> 	case OCTEP_CTRL_NET_F2H_CMD_LINK_STATUS:</div><div class='ctx'> 		if (netif_running(netdev)) {</div><div class='hunk'>@@ -331,8 +358,8 @@ static int process_mbox_notify(struct octep_device *oct,</div><div class='ctx'> void octep_ctrl_net_recv_fw_messages(struct octep_device *oct)</div><div class='ctx'> {</div><div class='ctx'> 	static u16 msg_sz = sizeof(union octep_ctrl_net_max_data);</div><div class='del'>-	union octep_ctrl_net_max_data data = {0};</div><div class='del'>-	struct octep_ctrl_mbox_msg msg = {0};</div><div class='add'>+	union octep_ctrl_net_max_data data = {};</div><div class='add'>+	struct octep_ctrl_mbox_msg msg = {};</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	msg.hdr.s.sz = msg_sz;</div><div class='hunk'>@@ -356,7 +383,7 @@ void octep_ctrl_net_recv_fw_messages(struct octep_device *oct)</div><div class='ctx'> int octep_ctrl_net_get_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 			    struct octep_fw_info *info)</div><div class='ctx'> {</div><div class='del'>-	struct octep_ctrl_net_wait_data d = {0};</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='ctx'> 	struct octep_ctrl_net_h2f_resp *resp;</div><div class='ctx'> 	struct octep_ctrl_net_h2f_req *req;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -375,10 +402,41 @@ int octep_ctrl_net_get_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int octep_ctrl_net_dev_remove(struct octep_device *oct, int vfid)</div><div class='add'>+{</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='add'>+	struct octep_ctrl_net_h2f_req *req;</div><div class='add'>+</div><div class='add'>+	req = &amp;d.data.req;</div><div class='add'>+	dev_dbg(&amp;oct-&gt;pdev-&gt;dev, "Sending dev_unload msg to fw\n");</div><div class='add'>+	init_send_req(&amp;d.msg, req, sizeof(int), vfid);</div><div class='add'>+	req-&gt;hdr.s.cmd = OCTEP_CTRL_NET_H2F_CMD_DEV_REMOVE;</div><div class='add'>+</div><div class='add'>+	return octep_send_mbox_req(oct, &amp;d, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int octep_ctrl_net_set_offloads(struct octep_device *oct, int vfid,</div><div class='add'>+				struct octep_ctrl_net_offloads *offloads,</div><div class='add'>+				bool wait_for_response)</div><div class='add'>+{</div><div class='add'>+	struct octep_ctrl_net_wait_data d = {};</div><div class='add'>+	struct octep_ctrl_net_h2f_req *req;</div><div class='add'>+</div><div class='add'>+	req = &amp;d.data.req;</div><div class='add'>+	init_send_req(&amp;d.msg, req, offloads_sz, vfid);</div><div class='add'>+	req-&gt;hdr.s.cmd = OCTEP_CTRL_NET_H2F_CMD_OFFLOADS;</div><div class='add'>+	req-&gt;offloads.cmd = OCTEP_CTRL_NET_CMD_SET;</div><div class='add'>+	req-&gt;offloads.offloads = *offloads;</div><div class='add'>+</div><div class='add'>+	return octep_send_mbox_req(oct, &amp;d, wait_for_response);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int octep_ctrl_net_uninit(struct octep_device *oct)</div><div class='ctx'> {</div><div class='ctx'> 	struct octep_ctrl_net_wait_data *pos, *n;</div><div class='ctx'> </div><div class='add'>+	octep_ctrl_net_dev_remove(oct, OCTEP_CTRL_NET_INVALID_VFID);</div><div class='add'>+</div><div class='ctx'> 	list_for_each_entry_safe(pos, n, &amp;oct-&gt;ctrl_req_wait_list, list)</div><div class='ctx'> 		pos-&gt;done = 1;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h b/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h<br/>index b330f370131b..0b823bea9cd8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h</a></div><div class='hunk'>@@ -42,6 +42,8 @@ enum octep_ctrl_net_h2f_cmd {</div><div class='ctx'> 	OCTEP_CTRL_NET_H2F_CMD_RX_STATE,</div><div class='ctx'> 	OCTEP_CTRL_NET_H2F_CMD_LINK_INFO,</div><div class='ctx'> 	OCTEP_CTRL_NET_H2F_CMD_GET_INFO,</div><div class='add'>+	OCTEP_CTRL_NET_H2F_CMD_DEV_REMOVE,</div><div class='add'>+	OCTEP_CTRL_NET_H2F_CMD_OFFLOADS,</div><div class='ctx'> 	OCTEP_CTRL_NET_H2F_CMD_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -112,6 +114,26 @@ struct octep_ctrl_net_h2f_req_cmd_link_info {</div><div class='ctx'> 	struct octep_ctrl_net_link_info info;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* offloads */</div><div class='add'>+struct octep_ctrl_net_offloads {</div><div class='add'>+	/* supported rx offloads OCTEP_RX_OFFLOAD_* */</div><div class='add'>+	u16 rx_offloads;</div><div class='add'>+	/* supported tx offloads OCTEP_TX_OFFLOAD_* */</div><div class='add'>+	u16 tx_offloads;</div><div class='add'>+	/* reserved */</div><div class='add'>+	u32 reserved_offloads;</div><div class='add'>+	/* extra offloads */</div><div class='add'>+	u64 ext_offloads;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* get/set offloads */</div><div class='add'>+struct octep_ctrl_net_h2f_req_cmd_offloads {</div><div class='add'>+	/* enum octep_ctrl_net_cmd */</div><div class='add'>+	u16 cmd;</div><div class='add'>+	/* struct octep_ctrl_net_offloads */</div><div class='add'>+	struct octep_ctrl_net_offloads offloads;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Host to fw request data */</div><div class='ctx'> struct octep_ctrl_net_h2f_req {</div><div class='ctx'> 	union octep_ctrl_net_req_hdr hdr;</div><div class='hunk'>@@ -121,6 +143,7 @@ struct octep_ctrl_net_h2f_req {</div><div class='ctx'> 		struct octep_ctrl_net_h2f_req_cmd_state link;</div><div class='ctx'> 		struct octep_ctrl_net_h2f_req_cmd_state rx;</div><div class='ctx'> 		struct octep_ctrl_net_h2f_req_cmd_link_info link_info;</div><div class='add'>+		struct octep_ctrl_net_h2f_req_cmd_offloads offloads;</div><div class='ctx'> 	};</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='hunk'>@@ -178,6 +201,7 @@ struct octep_ctrl_net_h2f_resp {</div><div class='ctx'> 		struct octep_ctrl_net_h2f_resp_cmd_state rx;</div><div class='ctx'> 		struct octep_ctrl_net_link_info link_info;</div><div class='ctx'> 		struct octep_ctrl_net_h2f_resp_cmd_get_info info;</div><div class='add'>+		struct octep_ctrl_net_offloads offloads;</div><div class='ctx'> 	};</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='hunk'>@@ -218,87 +242,105 @@ struct octep_ctrl_net_wait_data {</div><div class='ctx'> 	} data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/** Initialize data for ctrl net.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_init() - Initialize data for ctrl net.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on error.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_init(struct octep_device *oct);</div><div class='ctx'> </div><div class='del'>-/** Get link status from firmware.</div><div class='add'>+/** </div><div class='add'>+ * octep_ctrl_net_get_link_status() - Get link status from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: link status 0=down, 1=up.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_get_link_status(struct octep_device *oct, int vfid);</div><div class='ctx'> </div><div class='del'>-/** Set link status in firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_set_link_status() - Set link status in firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param up: boolean status.</div><div class='del'>- * @param wait_for_response: poll for response.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @up: boolean status.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_set_link_status(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> 				   bool wait_for_response);</div><div class='ctx'> </div><div class='del'>-/** Set rx state in firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_set_rx_state() - Set rx state in firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param up: boolean status.</div><div class='del'>- * @param wait_for_response: poll for response.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @up: boolean status.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_set_rx_state(struct octep_device *oct, int vfid, bool up,</div><div class='ctx'> 				bool wait_for_response);</div><div class='ctx'> </div><div class='del'>-/** Get mac address from firmware.</div><div class='add'>+/** </div><div class='add'>+ * octep_ctrl_net_get_mac_addr() - Get mac address from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param addr: non-null pointer to mac address.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @addr: non-null pointer to mac address.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_get_mac_addr(struct octep_device *oct, int vfid, u8 *addr);</div><div class='ctx'> </div><div class='del'>-/** Set mac address in firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_set_mac_addr() - Set mac address in firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param addr: non-null pointer to mac address.</div><div class='del'>- * @param wait_for_response: poll for response.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @addr: non-null pointer to mac address.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_set_mac_addr(struct octep_device *oct, int vfid, u8 *addr,</div><div class='ctx'> 				bool wait_for_response);</div><div class='ctx'> </div><div class='del'>-/** Set mtu in firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_get_mtu() - Get max MTU from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param mtu: mtu.</div><div class='del'>- * @param wait_for_response: poll for response.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ *</div><div class='add'>+ * return value: mtu on success, -errno on failure.</div><div class='add'>+ */</div><div class='add'>+int octep_ctrl_net_get_mtu(struct octep_device *oct, int vfid);</div><div class='add'>+</div><div class='add'>+/** </div><div class='add'>+ * octep_ctrl_net_set_mtu() - Set mtu in firmware.</div><div class='add'>+ *</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @mtu: mtu.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_set_mtu(struct octep_device *oct, int vfid, int mtu,</div><div class='ctx'> 			   bool wait_for_response);</div><div class='ctx'> </div><div class='del'>-/** Get interface statistics from firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_get_if_stats() - Get interface statistics from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param rx_stats: non-null pointer struct octep_iface_rx_stats.</div><div class='del'>- * @param tx_stats: non-null pointer struct octep_iface_tx_stats.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @rx_stats: non-null pointer struct octep_iface_rx_stats.</div><div class='add'>+ * @tx_stats: non-null pointer struct octep_iface_tx_stats.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='hunk'>@@ -306,23 +348,25 @@ int octep_ctrl_net_get_if_stats(struct octep_device *oct, int vfid,</div><div class='ctx'> 				struct octep_iface_rx_stats *rx_stats,</div><div class='ctx'> 				struct octep_iface_tx_stats *tx_stats);</div><div class='ctx'> </div><div class='del'>-/** Get link info from firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_get_link_info() - Get link info from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param link_info: non-null pointer to struct octep_iface_link_info.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @link_info: non-null pointer to struct octep_iface_link_info.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_get_link_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 				 struct octep_iface_link_info *link_info);</div><div class='ctx'> </div><div class='del'>-/** Set link info in firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_set_link_info() - Set link info in firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param link_info: non-null pointer to struct octep_iface_link_info.</div><div class='del'>- * @param wait_for_response: poll for response.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @link_info: non-null pointer to struct octep_iface_link_info.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='hunk'>@@ -331,26 +375,53 @@ int octep_ctrl_net_set_link_info(struct octep_device *oct,</div><div class='ctx'> 				 struct octep_iface_link_info *link_info,</div><div class='ctx'> 				 bool wait_for_response);</div><div class='ctx'> </div><div class='del'>-/** Poll for firmware messages and process them.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_recv_fw_messages() - Poll for firmware messages and process them.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='ctx'>  */</div><div class='ctx'> void octep_ctrl_net_recv_fw_messages(struct octep_device *oct);</div><div class='ctx'> </div><div class='del'>-/** Get info from firmware.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_get_info() - Get info from firmware.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='del'>- * @param vfid: Index of virtual function.</div><div class='del'>- * @param info: non-null pointer to struct octep_fw_info.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @info: non-null pointer to struct octep_fw_info.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on failure.</div><div class='ctx'>  */</div><div class='ctx'> int octep_ctrl_net_get_info(struct octep_device *oct, int vfid,</div><div class='ctx'> 			    struct octep_fw_info *info);</div><div class='ctx'> </div><div class='del'>-/** Uninitialize data for ctrl net.</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_dev_remove() - Indicate to firmware that a device unload has happened.</div><div class='add'>+ *</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ *</div><div class='add'>+ * return value: 0 on success, -errno on failure.</div><div class='add'>+ */</div><div class='add'>+int octep_ctrl_net_dev_remove(struct octep_device *oct, int vfid);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_set_offloads() - Set offloads in firmware.</div><div class='add'>+ *</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @vfid: Index of virtual function.</div><div class='add'>+ * @offloads: non-null pointer to struct octep_ctrl_net_offloads.</div><div class='add'>+ * @wait_for_response: poll for response.</div><div class='add'>+ *</div><div class='add'>+ * return value: 0 on success, -errno on failure.</div><div class='add'>+ */</div><div class='add'>+int octep_ctrl_net_set_offloads(struct octep_device *oct, int vfid,</div><div class='add'>+				struct octep_ctrl_net_offloads *offloads,</div><div class='add'>+				bool wait_for_response);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * octep_ctrl_net_uninit() - Uninitialize data for ctrl net.</div><div class='ctx'>  *</div><div class='del'>- * @param oct: non-null pointer to struct octep_device.</div><div class='add'>+ * @oct: non-null pointer to struct octep_device.</div><div class='ctx'>  *</div><div class='ctx'>  * return value: 0 on success, -errno on error.</div><div class='ctx'>  */</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.c b/drivers/net/ethernet/marvell/octeon_ep/octep_main.c<br/>index 552970c7dec0..7c9faa714a10 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_main.c</a></div><div class='hunk'>@@ -16,14 +16,20 @@</div><div class='ctx'> #include "octep_config.h"</div><div class='ctx'> #include "octep_main.h"</div><div class='ctx'> #include "octep_ctrl_net.h"</div><div class='add'>+#include "octep_pfvf_mbox.h"</div><div class='ctx'> </div><div class='ctx'> #define OCTEP_INTR_POLL_TIME_MSECS    100</div><div class='ctx'> struct workqueue_struct *octep_wq;</div><div class='ctx'> </div><div class='ctx'> /* Supported Devices */</div><div class='ctx'> static const struct pci_device_id octep_pci_id_tbl[] = {</div><div class='add'>+	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN98_PF)},</div><div class='ctx'> 	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN93_PF)},</div><div class='ctx'> 	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF95N_PF)},</div><div class='add'>+	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN10KA_PF)},</div><div class='add'>+	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF10KA_PF)},</div><div class='add'>+	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF10KB_PF)},</div><div class='add'>+	{PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN10KB_PF)},</div><div class='ctx'> 	{0, },</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(pci, octep_pci_id_tbl);</div><div class='hunk'>@@ -155,6 +161,21 @@ static void octep_disable_msix(struct octep_device *oct)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * octep_mbox_intr_handler() - common handler for pfvf mbox interrupts.</div><div class='add'>+ *</div><div class='add'>+ * @irq: Interrupt number.</div><div class='add'>+ * @data: interrupt data.</div><div class='add'>+ *</div><div class='add'>+ * this is common handler for pfvf mbox interrupts.</div><div class='add'>+ */</div><div class='add'>+static irqreturn_t octep_mbox_intr_handler(int irq, void *data)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = data;</div><div class='add'>+</div><div class='add'>+	return oct-&gt;hw_ops.mbox_intr_handler(oct);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * octep_oei_intr_handler() - common handler for output endpoint interrupts.</div><div class='ctx'>  *</div><div class='ctx'>  * @irq: Interrupt number.</div><div class='hunk'>@@ -357,8 +378,12 @@ static int octep_request_irqs(struct octep_device *oct)</div><div class='ctx'> </div><div class='ctx'> 		snprintf(irq_name, OCTEP_MSIX_NAME_SIZE,</div><div class='ctx'> 			 "%s-%s", netdev-&gt;name, non_ioq_msix_names[i]);</div><div class='del'>-		if (!strncmp(non_ioq_msix_names[i], "epf_oei_rint",</div><div class='del'>-			     strlen("epf_oei_rint"))) {</div><div class='add'>+		if (!strncmp(non_ioq_msix_names[i], "epf_mbox_rint", strlen("epf_mbox_rint"))) {</div><div class='add'>+			ret = request_irq(msix_entry-&gt;vector,</div><div class='add'>+					  octep_mbox_intr_handler, 0,</div><div class='add'>+					  irq_name, oct);</div><div class='add'>+		} else if (!strncmp(non_ioq_msix_names[i], "epf_oei_rint",</div><div class='add'>+			   strlen("epf_oei_rint"))) {</div><div class='ctx'> 			ret = request_irq(msix_entry-&gt;vector,</div><div class='ctx'> 					  octep_oei_intr_handler, 0,</div><div class='ctx'> 					  irq_name, oct);</div><div class='hunk'>@@ -777,17 +802,24 @@ static int octep_stop(struct net_device *netdev)</div><div class='ctx'>  */</div><div class='ctx'> static inline int octep_iq_full_check(struct octep_iq *iq)</div><div class='ctx'> {</div><div class='del'>-	if (likely((iq-&gt;max_count - atomic_read(&amp;iq-&gt;instr_pending)) &gt;=</div><div class='add'>+	if (likely((IQ_INSTR_SPACE(iq)) &gt;</div><div class='ctx'> 		   OCTEP_WAKE_QUEUE_THRESHOLD))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	/* Stop the queue if unable to send */</div><div class='ctx'> 	netif_stop_subqueue(iq-&gt;netdev, iq-&gt;q_no);</div><div class='ctx'> </div><div class='add'>+	/* Allow for pending updates in write index</div><div class='add'>+	 * from iq_process_completion in other cpus</div><div class='add'>+	 * to reflect, in case queue gets free</div><div class='add'>+	 * entries.</div><div class='add'>+	 */</div><div class='add'>+	smp_mb();</div><div class='add'>+</div><div class='ctx'> 	/* check again and restart the queue, in case NAPI has just freed</div><div class='ctx'> 	 * enough Tx ring entries.</div><div class='ctx'> 	 */</div><div class='del'>-	if (unlikely((iq-&gt;max_count - atomic_read(&amp;iq-&gt;instr_pending)) &gt;=</div><div class='add'>+	if (unlikely(IQ_INSTR_SPACE(iq) &gt;</div><div class='ctx'> 		     OCTEP_WAKE_QUEUE_THRESHOLD)) {</div><div class='ctx'> 		netif_start_subqueue(iq-&gt;netdev, iq-&gt;q_no);</div><div class='ctx'> 		iq-&gt;stats.restart_cnt++;</div><div class='hunk'>@@ -810,6 +842,7 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 				    struct net_device *netdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct octep_device *oct = netdev_priv(netdev);</div><div class='add'>+	netdev_features_t feat  = netdev-&gt;features;</div><div class='ctx'> 	struct octep_tx_sglist_desc *sglist;</div><div class='ctx'> 	struct octep_tx_buffer *tx_buffer;</div><div class='ctx'> 	struct octep_tx_desc_hw *hw_desc;</div><div class='hunk'>@@ -818,8 +851,12 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 	struct octep_iq *iq;</div><div class='ctx'> 	skb_frag_t *frag;</div><div class='ctx'> 	u16 nr_frags, si;</div><div class='add'>+	int xmit_more;</div><div class='ctx'> 	u16 q_no, wi;</div><div class='ctx'> </div><div class='add'>+	if (skb_put_padto(skb, ETH_ZLEN))</div><div class='add'>+		return NETDEV_TX_OK;</div><div class='add'>+</div><div class='ctx'> 	q_no = skb_get_queue_mapping(skb);</div><div class='ctx'> 	if (q_no &gt;= oct-&gt;num_iqs) {</div><div class='ctx'> 		netdev_err(netdev, "Invalid Tx skb-&gt;queue_mapping=%d\n", q_no);</div><div class='hunk'>@@ -827,10 +864,6 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	iq = oct-&gt;iq[q_no];</div><div class='del'>-	if (octep_iq_full_check(iq)) {</div><div class='del'>-		iq-&gt;stats.tx_busy++;</div><div class='del'>-		return NETDEV_TX_BUSY;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	shinfo = skb_shinfo(skb);</div><div class='ctx'> 	nr_frags = shinfo-&gt;nr_frags;</div><div class='hunk'>@@ -843,8 +876,9 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 	tx_buffer-&gt;skb = skb;</div><div class='ctx'> </div><div class='ctx'> 	ih = &amp;hw_desc-&gt;ih;</div><div class='del'>-	ih-&gt;tlen = skb-&gt;len;</div><div class='del'>-	ih-&gt;pkind = oct-&gt;pkind;</div><div class='add'>+	ih-&gt;pkind = oct-&gt;conf-&gt;fw_info.pkind;</div><div class='add'>+	ih-&gt;fsz = oct-&gt;conf-&gt;fw_info.fsz;</div><div class='add'>+	ih-&gt;tlen = skb-&gt;len + ih-&gt;fsz;</div><div class='ctx'> </div><div class='ctx'> 	if (!nr_frags) {</div><div class='ctx'> 		tx_buffer-&gt;gather = 0;</div><div class='hunk'>@@ -869,9 +903,6 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 		if (dma_mapping_error(iq-&gt;dev, dma))</div><div class='ctx'> 			goto dma_map_err;</div><div class='ctx'> </div><div class='del'>-		dma_sync_single_for_cpu(iq-&gt;dev, tx_buffer-&gt;sglist_dma,</div><div class='del'>-					OCTEP_SGLIST_SIZE_PER_PKT,</div><div class='del'>-					DMA_TO_DEVICE);</div><div class='ctx'> 		memset(sglist, 0, OCTEP_SGLIST_SIZE_PER_PKT);</div><div class='ctx'> 		sglist[0].len[3] = len;</div><div class='ctx'> 		sglist[0].dma_ptr[0] = dma;</div><div class='hunk'>@@ -891,26 +922,46 @@ static netdev_tx_t octep_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 			frag++;</div><div class='ctx'> 			si++;</div><div class='ctx'> 		}</div><div class='del'>-		dma_sync_single_for_device(iq-&gt;dev, tx_buffer-&gt;sglist_dma,</div><div class='del'>-					   OCTEP_SGLIST_SIZE_PER_PKT,</div><div class='del'>-					   DMA_TO_DEVICE);</div><div class='del'>-</div><div class='ctx'> 		hw_desc-&gt;dptr = tx_buffer-&gt;sglist_dma;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	netdev_tx_sent_queue(iq-&gt;netdev_q, skb-&gt;len);</div><div class='add'>+	if (oct-&gt;conf-&gt;fw_info.tx_ol_flags) {</div><div class='add'>+		if ((feat &amp; (NETIF_F_TSO)) &amp;&amp; (skb_is_gso(skb))) {</div><div class='add'>+			hw_desc-&gt;txm.ol_flags = OCTEP_TX_OFFLOAD_CKSUM;</div><div class='add'>+			hw_desc-&gt;txm.ol_flags |= OCTEP_TX_OFFLOAD_TSO;</div><div class='add'>+			hw_desc-&gt;txm.gso_size =  skb_shinfo(skb)-&gt;gso_size;</div><div class='add'>+			hw_desc-&gt;txm.gso_segs =  skb_shinfo(skb)-&gt;gso_segs;</div><div class='add'>+		} else if (feat &amp; (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {</div><div class='add'>+			hw_desc-&gt;txm.ol_flags = OCTEP_TX_OFFLOAD_CKSUM;</div><div class='add'>+		}</div><div class='add'>+		/* due to ESR txm will be swapped by hw */</div><div class='add'>+		hw_desc-&gt;txm64[0] = (__force u64)cpu_to_be64(hw_desc-&gt;txm64[0]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	xmit_more = netdev_xmit_more();</div><div class='add'>+</div><div class='add'>+	__netdev_tx_sent_queue(iq-&gt;netdev_q, skb-&gt;len, xmit_more);</div><div class='add'>+</div><div class='ctx'> 	skb_tx_timestamp(skb);</div><div class='del'>-	atomic_inc(&amp;iq-&gt;instr_pending);</div><div class='add'>+	iq-&gt;fill_cnt++;</div><div class='ctx'> 	wi++;</div><div class='del'>-	if (wi == iq-&gt;max_count)</div><div class='del'>-		wi = 0;</div><div class='del'>-	iq-&gt;host_write_index = wi;</div><div class='add'>+	iq-&gt;host_write_index = wi &amp; iq-&gt;ring_size_mask;</div><div class='add'>+</div><div class='add'>+	/* octep_iq_full_check stops the queue and returns</div><div class='add'>+	 * true if so, in case the queue has become full</div><div class='add'>+	 * by inserting current packet. If so, we can</div><div class='add'>+	 * go ahead and ring doorbell.</div><div class='add'>+	 */</div><div class='add'>+	if (!octep_iq_full_check(iq) &amp;&amp; xmit_more &amp;&amp;</div><div class='add'>+	    iq-&gt;fill_cnt &lt; iq-&gt;fill_threshold)</div><div class='add'>+		return NETDEV_TX_OK;</div><div class='add'>+</div><div class='ctx'> 	/* Flush the hw descriptor before writing to doorbell */</div><div class='ctx'> 	wmb();</div><div class='del'>-</div><div class='del'>-	/* Ring Doorbell to notify the NIC there is a new packet */</div><div class='del'>-	writel(1, iq-&gt;doorbell_reg);</div><div class='del'>-	iq-&gt;stats.instr_posted++;</div><div class='add'>+	/* Ring Doorbell to notify the NIC of new packets */</div><div class='add'>+	writel(iq-&gt;fill_cnt, iq-&gt;doorbell_reg);</div><div class='add'>+	iq-&gt;stats.instr_posted += iq-&gt;fill_cnt;</div><div class='add'>+	iq-&gt;fill_cnt = 0;</div><div class='ctx'> 	return NETDEV_TX_OK;</div><div class='ctx'> </div><div class='ctx'> dma_map_sg_err:</div><div class='hunk'>@@ -1051,6 +1102,41 @@ static int octep_change_mtu(struct net_device *netdev, int new_mtu)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int octep_set_features(struct net_device *dev, netdev_features_t features)</div><div class='add'>+{</div><div class='add'>+	struct octep_ctrl_net_offloads offloads = { 0 };</div><div class='add'>+	struct octep_device *oct = netdev_priv(dev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	/* We only support features received from firmware */</div><div class='add'>+	if ((features &amp; dev-&gt;hw_features) != features)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (features &amp; NETIF_F_TSO)</div><div class='add'>+		offloads.tx_offloads |= OCTEP_TX_OFFLOAD_TSO;</div><div class='add'>+</div><div class='add'>+	if (features &amp; NETIF_F_TSO6)</div><div class='add'>+		offloads.tx_offloads |= OCTEP_TX_OFFLOAD_TSO;</div><div class='add'>+</div><div class='add'>+	if (features &amp; NETIF_F_IP_CSUM)</div><div class='add'>+		offloads.tx_offloads |= OCTEP_TX_OFFLOAD_CKSUM;</div><div class='add'>+</div><div class='add'>+	if (features &amp; NETIF_F_IPV6_CSUM)</div><div class='add'>+		offloads.tx_offloads |= OCTEP_TX_OFFLOAD_CKSUM;</div><div class='add'>+</div><div class='add'>+	if (features &amp; NETIF_F_RXCSUM)</div><div class='add'>+		offloads.rx_offloads |= OCTEP_RX_OFFLOAD_CKSUM;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_offloads(oct,</div><div class='add'>+					  OCTEP_CTRL_NET_INVALID_VFID,</div><div class='add'>+					  &amp;offloads,</div><div class='add'>+					  true);</div><div class='add'>+	if (!err)</div><div class='add'>+		dev-&gt;features = features;</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops octep_netdev_ops = {</div><div class='ctx'> 	.ndo_open                = octep_open,</div><div class='ctx'> 	.ndo_stop                = octep_stop,</div><div class='hunk'>@@ -1059,6 +1145,7 @@ static const struct net_device_ops octep_netdev_ops = {</div><div class='ctx'> 	.ndo_tx_timeout          = octep_tx_timeout,</div><div class='ctx'> 	.ndo_set_mac_address     = octep_set_mac,</div><div class='ctx'> 	.ndo_change_mtu          = octep_change_mtu,</div><div class='add'>+	.ndo_set_features        = octep_set_features,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -1132,10 +1219,20 @@ static void octep_ctrl_mbox_task(struct work_struct *work)</div><div class='ctx'> static const char *octep_devid_to_str(struct octep_device *oct)</div><div class='ctx'> {</div><div class='ctx'> 	switch (oct-&gt;chip_id) {</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN98_PF:</div><div class='add'>+		return "CN98XX";</div><div class='ctx'> 	case OCTEP_PCI_DEVICE_ID_CN93_PF:</div><div class='ctx'> 		return "CN93XX";</div><div class='ctx'> 	case OCTEP_PCI_DEVICE_ID_CNF95N_PF:</div><div class='ctx'> 		return "CNF95N";</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN10KA_PF:</div><div class='add'>+		return "CN10KA";</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CNF10KA_PF:</div><div class='add'>+		return "CNF10KA";</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CNF10KB_PF:</div><div class='add'>+		return "CNF10KB";</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN10KB_PF:</div><div class='add'>+		return "CN10KB";</div><div class='ctx'> 	default:</div><div class='ctx'> 		return "Unsupported";</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1174,6 +1271,7 @@ int octep_device_setup(struct octep_device *oct)</div><div class='ctx'> 	dev_info(&amp;pdev-&gt;dev, "chip_id = 0x%x\n", pdev-&gt;device);</div><div class='ctx'> </div><div class='ctx'> 	switch (oct-&gt;chip_id) {</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN98_PF:</div><div class='ctx'> 	case OCTEP_PCI_DEVICE_ID_CN93_PF:</div><div class='ctx'> 	case OCTEP_PCI_DEVICE_ID_CNF95N_PF:</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "Setting up OCTEON %s PF PASS%d.%d\n",</div><div class='hunk'>@@ -1181,18 +1279,32 @@ int octep_device_setup(struct octep_device *oct)</div><div class='ctx'> 			 OCTEP_MINOR_REV(oct));</div><div class='ctx'> 		octep_device_setup_cn93_pf(oct);</div><div class='ctx'> 		break;</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CNF10KA_PF:</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN10KA_PF:</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CNF10KB_PF:</div><div class='add'>+	case OCTEP_PCI_DEVICE_ID_CN10KB_PF:</div><div class='add'>+		dev_info(&amp;pdev-&gt;dev, "Setting up OCTEON %s PF PASS%d.%d\n",</div><div class='add'>+			 octep_devid_to_str(oct), OCTEP_MAJOR_REV(oct), OCTEP_MINOR_REV(oct));</div><div class='add'>+		octep_device_setup_cnxk_pf(oct);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev,</div><div class='ctx'> 			"%s: unsupported device\n", __func__);</div><div class='ctx'> 		goto unsupported_dev;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	oct-&gt;pkind = CFG_GET_IQ_PKIND(oct-&gt;conf);</div><div class='ctx'> </div><div class='ctx'> 	ret = octep_ctrl_net_init(oct);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	INIT_WORK(&amp;oct-&gt;tx_timeout_task, octep_tx_timeout_task);</div><div class='add'>+	INIT_WORK(&amp;oct-&gt;ctrl_mbox_task, octep_ctrl_mbox_task);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;oct-&gt;intr_poll_task, octep_intr_poll_task);</div><div class='add'>+	oct-&gt;poll_non_ioq_intr = true;</div><div class='add'>+	queue_delayed_work(octep_wq, &amp;oct-&gt;intr_poll_task,</div><div class='add'>+			   msecs_to_jiffies(OCTEP_INTR_POLL_TIME_MSECS));</div><div class='add'>+</div><div class='ctx'> 	atomic_set(&amp;oct-&gt;hb_miss_cnt, 0);</div><div class='ctx'> 	INIT_DELAYED_WORK(&amp;oct-&gt;hb_task, octep_hb_timeout_task);</div><div class='ctx'> </div><div class='hunk'>@@ -1230,6 +1342,7 @@ static void octep_device_cleanup(struct octep_device *oct)</div><div class='ctx'> 		oct-&gt;mbox[i] = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	octep_delete_pfvf_mbox(oct);</div><div class='ctx'> 	octep_ctrl_net_uninit(oct);</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;oct-&gt;hb_task);</div><div class='ctx'> </div><div class='hunk'>@@ -1258,7 +1371,8 @@ static bool get_fw_ready_status(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 		pci_read_config_byte(pdev, (pos + 8), &amp;status);</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "Firmware ready status = %u\n", status);</div><div class='del'>-		return status;</div><div class='add'>+#define FW_STATUS_READY 1ULL</div><div class='add'>+		return status == FW_STATUS_READY;</div><div class='ctx'> 	}</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -1276,6 +1390,7 @@ static int octep_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> {</div><div class='ctx'> 	struct octep_device *octep_dev = NULL;</div><div class='ctx'> 	struct net_device *netdev;</div><div class='add'>+	int max_rx_pktlen;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = pci_enable_device(pdev);</div><div class='hunk'>@@ -1325,31 +1440,52 @@ static int octep_probe(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 		goto err_octep_config;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	octep_ctrl_net_get_info(octep_dev, OCTEP_CTRL_NET_INVALID_VFID,</div><div class='del'>-				&amp;octep_dev-&gt;conf-&gt;fw_info);</div><div class='add'>+	err = octep_setup_pfvf_mbox(octep_dev);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "PF-VF mailbox setup failed\n");</div><div class='add'>+		goto register_dev_err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_get_info(octep_dev, OCTEP_CTRL_NET_INVALID_VFID,</div><div class='add'>+				      &amp;octep_dev-&gt;conf-&gt;fw_info);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to get firmware info\n");</div><div class='add'>+		goto register_dev_err;</div><div class='add'>+	}</div><div class='ctx'> 	dev_info(&amp;octep_dev-&gt;pdev-&gt;dev, "Heartbeat interval %u msecs Heartbeat miss count %u\n",</div><div class='ctx'> 		 octep_dev-&gt;conf-&gt;fw_info.hb_interval,</div><div class='ctx'> 		 octep_dev-&gt;conf-&gt;fw_info.hb_miss_count);</div><div class='ctx'> 	queue_delayed_work(octep_wq, &amp;octep_dev-&gt;hb_task,</div><div class='ctx'> 			   msecs_to_jiffies(octep_dev-&gt;conf-&gt;fw_info.hb_interval));</div><div class='ctx'> </div><div class='del'>-	INIT_WORK(&amp;octep_dev-&gt;tx_timeout_task, octep_tx_timeout_task);</div><div class='del'>-	INIT_WORK(&amp;octep_dev-&gt;ctrl_mbox_task, octep_ctrl_mbox_task);</div><div class='del'>-	INIT_DELAYED_WORK(&amp;octep_dev-&gt;intr_poll_task, octep_intr_poll_task);</div><div class='del'>-	octep_dev-&gt;poll_non_ioq_intr = true;</div><div class='del'>-	queue_delayed_work(octep_wq, &amp;octep_dev-&gt;intr_poll_task,</div><div class='del'>-			   msecs_to_jiffies(OCTEP_INTR_POLL_TIME_MSECS));</div><div class='del'>-</div><div class='ctx'> 	netdev-&gt;netdev_ops = &amp;octep_netdev_ops;</div><div class='ctx'> 	octep_set_ethtool_ops(netdev);</div><div class='ctx'> 	netif_carrier_off(netdev);</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;hw_features = NETIF_F_SG;</div><div class='del'>-	netdev-&gt;features |= netdev-&gt;hw_features;</div><div class='add'>+	if (OCTEP_TX_IP_CSUM(octep_dev-&gt;conf-&gt;fw_info.tx_ol_flags))</div><div class='add'>+		netdev-&gt;hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);</div><div class='add'>+</div><div class='add'>+	if (OCTEP_RX_IP_CSUM(octep_dev-&gt;conf-&gt;fw_info.rx_ol_flags))</div><div class='add'>+		netdev-&gt;hw_features |= NETIF_F_RXCSUM;</div><div class='add'>+</div><div class='add'>+	max_rx_pktlen = octep_ctrl_net_get_mtu(octep_dev, OCTEP_CTRL_NET_INVALID_VFID);</div><div class='add'>+	if (max_rx_pktlen &lt; 0) {</div><div class='add'>+		dev_err(&amp;octep_dev-&gt;pdev-&gt;dev,</div><div class='add'>+			"Failed to get max receive packet size; err = %d\n", max_rx_pktlen);</div><div class='add'>+		err = max_rx_pktlen;</div><div class='add'>+		goto register_dev_err;</div><div class='add'>+	}</div><div class='ctx'> 	netdev-&gt;min_mtu = OCTEP_MIN_MTU;</div><div class='del'>-	netdev-&gt;max_mtu = OCTEP_MAX_MTU;</div><div class='add'>+	netdev-&gt;max_mtu = max_rx_pktlen - (ETH_HLEN + ETH_FCS_LEN);</div><div class='ctx'> 	netdev-&gt;mtu = OCTEP_DEFAULT_MTU;</div><div class='ctx'> </div><div class='add'>+	if (OCTEP_TX_TSO(octep_dev-&gt;conf-&gt;fw_info.tx_ol_flags)) {</div><div class='add'>+		netdev-&gt;hw_features |= NETIF_F_TSO;</div><div class='add'>+		netif_set_tso_max_size(netdev, netdev-&gt;max_mtu);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	netdev-&gt;features |= netdev-&gt;hw_features;</div><div class='ctx'> 	err = octep_ctrl_net_get_mac_addr(octep_dev, OCTEP_CTRL_NET_INVALID_VFID,</div><div class='ctx'> 					  octep_dev-&gt;mac_addr);</div><div class='ctx'> 	if (err) {</div><div class='hunk'>@@ -1378,6 +1514,21 @@ err_dma_mask:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int octep_sriov_disable(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+</div><div class='add'>+	if (pci_vfs_assigned(oct-&gt;pdev)) {</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "Can't disable SRIOV while VFs are assigned\n");</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pci_disable_sriov(pdev);</div><div class='add'>+	CFG_GET_ACTIVE_VFS(oct-&gt;conf) = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * octep_remove() - Remove Octeon PCI device from driver control.</div><div class='ctx'>  *</div><div class='hunk'>@@ -1395,6 +1546,7 @@ static void octep_remove(struct pci_dev *pdev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	netdev = oct-&gt;netdev;</div><div class='add'>+	octep_sriov_disable(oct);</div><div class='ctx'> 	if (netdev-&gt;reg_state == NETREG_REGISTERED)</div><div class='ctx'> 		unregister_netdev(netdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1405,11 +1557,47 @@ static void octep_remove(struct pci_dev *pdev)</div><div class='ctx'> 	pci_disable_device(pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int octep_sriov_enable(struct octep_device *oct, int num_vfs)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = oct-&gt;pdev;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	CFG_GET_ACTIVE_VFS(oct-&gt;conf) = num_vfs;</div><div class='add'>+	err = pci_enable_sriov(pdev, num_vfs);</div><div class='add'>+	if (err) {</div><div class='add'>+		dev_warn(&amp;pdev-&gt;dev, "Failed to enable SRIOV err=%d\n", err);</div><div class='add'>+		CFG_GET_ACTIVE_VFS(oct-&gt;conf) = 0;</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return num_vfs;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int octep_sriov_configure(struct pci_dev *pdev, int num_vfs)</div><div class='add'>+{</div><div class='add'>+	struct octep_device *oct = pci_get_drvdata(pdev);</div><div class='add'>+	int max_nvfs;</div><div class='add'>+</div><div class='add'>+	if (num_vfs == 0)</div><div class='add'>+		return octep_sriov_disable(oct);</div><div class='add'>+</div><div class='add'>+	max_nvfs = CFG_GET_MAX_VFS(oct-&gt;conf);</div><div class='add'>+</div><div class='add'>+	if (num_vfs &gt; max_nvfs) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Invalid VF count Max supported VFs = %d\n",</div><div class='add'>+			max_nvfs);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return octep_sriov_enable(oct, num_vfs);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct pci_driver octep_driver = {</div><div class='ctx'> 	.name = OCTEP_DRV_NAME,</div><div class='ctx'> 	.id_table = octep_pci_id_tbl,</div><div class='ctx'> 	.probe = octep_probe,</div><div class='ctx'> 	.remove = octep_remove,</div><div class='add'>+	.sriov_configure = octep_sriov_configure,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h<br/>index 6df902ebb7f3..fee59e0e0138 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_main.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_main.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_main.h</a></div><div class='hunk'>@@ -18,11 +18,17 @@</div><div class='ctx'> #define  OCTEP_PCIID_CN93_PF  0xB200177d</div><div class='ctx'> #define  OCTEP_PCIID_CN93_VF  0xB203177d</div><div class='ctx'> </div><div class='add'>+#define  OCTEP_PCI_DEVICE_ID_CN98_PF 0xB100</div><div class='ctx'> #define  OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200</div><div class='ctx'> #define  OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203</div><div class='ctx'> </div><div class='ctx'> #define  OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400    //95N PF</div><div class='ctx'> </div><div class='add'>+#define  OCTEP_PCI_DEVICE_ID_CN10KA_PF  0xB900   //CN10KA PF</div><div class='add'>+#define  OCTEP_PCI_DEVICE_ID_CNF10KA_PF 0xBA00   //CNF10KA PF</div><div class='add'>+#define  OCTEP_PCI_DEVICE_ID_CNF10KB_PF 0xBC00   //CNF10KB PF</div><div class='add'>+#define  OCTEP_PCI_DEVICE_ID_CN10KB_PF  0xBD00   //CN10KB PF</div><div class='add'>+</div><div class='ctx'> #define  OCTEP_MAX_QUEUES   63</div><div class='ctx'> #define  OCTEP_MAX_IQ       OCTEP_MAX_QUEUES</div><div class='ctx'> #define  OCTEP_MAX_OQ       OCTEP_MAX_QUEUES</div><div class='hunk'>@@ -40,6 +46,15 @@</div><div class='ctx'> #define  OCTEP_OQ_INTR_RESEND_BIT  59</div><div class='ctx'> </div><div class='ctx'> #define  OCTEP_MMIO_REGIONS     3</div><div class='add'>+</div><div class='add'>+#define  IQ_INSTR_PENDING(iq)  ({ typeof(iq) iq__ = (iq); \</div><div class='add'>+				  ((iq__)-&gt;host_write_index - (iq__)-&gt;flush_index) &amp; \</div><div class='add'>+				  (iq__)-&gt;ring_size_mask; \</div><div class='add'>+				})</div><div class='add'>+#define  IQ_INSTR_SPACE(iq)    ({ typeof(iq) iq_ = (iq); \</div><div class='add'>+				  (iq_)-&gt;max_count - IQ_INSTR_PENDING(iq_); \</div><div class='add'>+				})</div><div class='add'>+</div><div class='ctx'> /* PCI address space mapping information.</div><div class='ctx'>  * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of</div><div class='ctx'>  * Octeon gets mapped to different physical address spaces in</div><div class='hunk'>@@ -65,6 +80,7 @@ struct octep_hw_ops {</div><div class='ctx'> 	void (*setup_oq_regs)(struct octep_device *oct, int q);</div><div class='ctx'> 	void (*setup_mbox_regs)(struct octep_device *oct, int mbox);</div><div class='ctx'> </div><div class='add'>+	irqreturn_t (*mbox_intr_handler)(void *ioq_vector);</div><div class='ctx'> 	irqreturn_t (*oei_intr_handler)(void *ioq_vector);</div><div class='ctx'> 	irqreturn_t (*ire_intr_handler)(void *ioq_vector);</div><div class='ctx'> 	irqreturn_t (*ore_intr_handler)(void *ioq_vector);</div><div class='hunk'>@@ -103,28 +119,27 @@ struct octep_mbox_data {</div><div class='ctx'> 	u64 *data;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define MAX_VF_PF_MBOX_DATA_SIZE 384</div><div class='add'>+/* wrappers around work structs */</div><div class='add'>+struct octep_pfvf_mbox_wk {</div><div class='add'>+	struct work_struct work;</div><div class='add'>+	void *ctxptr;</div><div class='add'>+	u64 ctxul;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Octeon device mailbox */</div><div class='ctx'> struct octep_mbox {</div><div class='del'>-	/* A spinlock to protect access to this q_mbox. */</div><div class='del'>-	spinlock_t lock;</div><div class='del'>-</div><div class='del'>-	u32 q_no;</div><div class='del'>-	u32 state;</div><div class='del'>-</div><div class='del'>-	/* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */</div><div class='del'>-	u8 __iomem *mbox_int_reg;</div><div class='del'>-</div><div class='del'>-	/* SLI_PKT_PF_VF_MBOX_SIG(0) for PF,</div><div class='del'>-	 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF.</div><div class='del'>-	 */</div><div class='del'>-	u8 __iomem *mbox_write_reg;</div><div class='del'>-</div><div class='del'>-	/* SLI_PKT_PF_VF_MBOX_SIG(1) for PF,</div><div class='del'>-	 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF.</div><div class='del'>-	 */</div><div class='del'>-	u8 __iomem *mbox_read_reg;</div><div class='del'>-</div><div class='add'>+	/* A mutex to protect access to this q_mbox. */</div><div class='add'>+	struct mutex lock;</div><div class='add'>+	u32 vf_id;</div><div class='add'>+	u32 config_data_index;</div><div class='add'>+	u32 message_len;</div><div class='add'>+	u8 __iomem *pf_vf_data_reg;</div><div class='add'>+	u8 __iomem *vf_pf_data_reg;</div><div class='add'>+	struct octep_pfvf_mbox_wk wk;</div><div class='add'>+	struct octep_device *oct;</div><div class='ctx'> 	struct octep_mbox_data mbox_data;</div><div class='add'>+	u8 config_data[MAX_VF_PF_MBOX_DATA_SIZE];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Tx/Rx queue vector per interrupt. */</div><div class='hunk'>@@ -202,6 +217,12 @@ struct octep_iface_link_info {</div><div class='ctx'> 	u8  oper_up;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/* The Octeon VF device specific info data structure.*/</div><div class='add'>+struct octep_pfvf_info {</div><div class='add'>+	u8 mac_addr[ETH_ALEN];</div><div class='add'>+	u32 mbox_version;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* The Octeon device specific private data structure.</div><div class='ctx'>  * Each Octeon device has this structure to represent all its components.</div><div class='ctx'>  */</div><div class='hunk'>@@ -232,8 +253,7 @@ struct octep_device {</div><div class='ctx'> </div><div class='ctx'> 	/* Tx queues (IQ: Instruction Queue) */</div><div class='ctx'> 	u16 num_iqs;</div><div class='del'>-	/* pkind value to be used in every Tx hardware descriptor */</div><div class='del'>-	u8 pkind;</div><div class='add'>+</div><div class='ctx'> 	/* Pointers to Octeon Tx queues */</div><div class='ctx'> 	struct octep_iq *iq[OCTEP_MAX_IQ];</div><div class='ctx'> </div><div class='hunk'>@@ -268,6 +288,8 @@ struct octep_device {</div><div class='ctx'> </div><div class='ctx'> 	/* Mailbox to talk to VFs */</div><div class='ctx'> 	struct octep_mbox *mbox[OCTEP_MAX_VF];</div><div class='add'>+	/* VFs info */</div><div class='add'>+	struct octep_pfvf_info vf_info[OCTEP_MAX_VF];</div><div class='ctx'> </div><div class='ctx'> 	/* Work entry to handle Tx timeout */</div><div class='ctx'> 	struct work_struct tx_timeout_task;</div><div class='hunk'>@@ -377,6 +399,7 @@ int octep_setup_oqs(struct octep_device *oct);</div><div class='ctx'> void octep_free_oqs(struct octep_device *oct);</div><div class='ctx'> void octep_oq_dbell_init(struct octep_device *oct);</div><div class='ctx'> void octep_device_setup_cn93_pf(struct octep_device *oct);</div><div class='add'>+void octep_device_setup_cnxk_pf(struct octep_device *oct);</div><div class='ctx'> int octep_iq_process_completions(struct octep_iq *iq, u16 budget);</div><div class='ctx'> int octep_oq_process_rx(struct octep_oq *oq, int budget);</div><div class='ctx'> void octep_set_ethtool_ops(struct net_device *netdev);</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c b/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c<br/>new file mode 100644<br/>index 000000000000..2e2c3be8a0b4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.c</a></div><div class='hunk'>@@ -0,0 +1,449 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Marvell Octeon EP (EndPoint) Ethernet Driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2020 Marvell.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/errno.h&gt;</div><div class='add'>+#include &lt;linux/string.h&gt;</div><div class='add'>+#include &lt;linux/mutex.h&gt;</div><div class='add'>+#include &lt;linux/jiffies.h&gt;</div><div class='add'>+#include &lt;linux/sched.h&gt;</div><div class='add'>+#include &lt;linux/sched/signal.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/pci.h&gt;</div><div class='add'>+#include &lt;linux/etherdevice.h&gt;</div><div class='add'>+</div><div class='add'>+#include "octep_config.h"</div><div class='add'>+#include "octep_main.h"</div><div class='add'>+#include "octep_pfvf_mbox.h"</div><div class='add'>+#include "octep_ctrl_net.h"</div><div class='add'>+</div><div class='add'>+/* When a new command is implemented, the below table should be updated</div><div class='add'>+ * with new command and it's version info.</div><div class='add'>+ */</div><div class='add'>+static u32 pfvf_cmd_versions[OCTEP_PFVF_MBOX_CMD_MAX] = {</div><div class='add'>+	[0 ... OCTEP_PFVF_MBOX_CMD_DEV_REMOVE] = OCTEP_PFVF_MBOX_VERSION_V1,</div><div class='add'>+	[OCTEP_PFVF_MBOX_CMD_GET_FW_INFO ... OCTEP_PFVF_MBOX_NOTIF_LINK_STATUS] =</div><div class='add'>+		OCTEP_PFVF_MBOX_VERSION_V2</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_validate_version(struct octep_device *oct,  u32 vf_id,</div><div class='add'>+					union octep_pfvf_mbox_word cmd,</div><div class='add'>+					union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	u32 vf_version = (u32)cmd.s_version.version;</div><div class='add'>+</div><div class='add'>+	dev_dbg(&amp;oct-&gt;pdev-&gt;dev, "VF id:%d VF version:%d PF version:%d\n",</div><div class='add'>+		vf_id, vf_version, OCTEP_PFVF_MBOX_VERSION_CURRENT);</div><div class='add'>+	if (vf_version &lt; OCTEP_PFVF_MBOX_VERSION_CURRENT)</div><div class='add'>+		rsp-&gt;s_version.version = vf_version;</div><div class='add'>+	else</div><div class='add'>+		rsp-&gt;s_version.version = OCTEP_PFVF_MBOX_VERSION_CURRENT;</div><div class='add'>+</div><div class='add'>+	oct-&gt;vf_info[vf_id].mbox_version = rsp-&gt;s_version.version;</div><div class='add'>+	dev_dbg(&amp;oct-&gt;pdev-&gt;dev, "VF id:%d negotiated VF version:%d\n",</div><div class='add'>+		vf_id, oct-&gt;vf_info[vf_id].mbox_version);</div><div class='add'>+</div><div class='add'>+	rsp-&gt;s_version.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_get_link_status(struct octep_device *oct, u32 vf_id,</div><div class='add'>+				       union octep_pfvf_mbox_word cmd,</div><div class='add'>+				       union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int status;</div><div class='add'>+</div><div class='add'>+	status = octep_ctrl_net_get_link_status(oct, vf_id);</div><div class='add'>+	if (status &lt; 0) {</div><div class='add'>+		rsp-&gt;s_link_status.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Get VF link status failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_link_status.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+	rsp-&gt;s_link_status.status = status;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_set_link_status(struct octep_device *oct, u32 vf_id,</div><div class='add'>+				       union octep_pfvf_mbox_word cmd,</div><div class='add'>+				       union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_link_status(oct, vf_id, cmd.s_link_status.status, true);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_link_status.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Set VF link status failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_link_status.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_set_rx_state(struct octep_device *oct, u32 vf_id,</div><div class='add'>+				    union octep_pfvf_mbox_word cmd,</div><div class='add'>+				    union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_rx_state(oct, vf_id, cmd.s_link_state.state, true);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_link_state.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Set VF Rx link state failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_link_state.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int octep_send_notification(struct octep_device *oct, u32 vf_id,</div><div class='add'>+				   union octep_pfvf_mbox_word cmd)</div><div class='add'>+{</div><div class='add'>+	u32 max_rings_per_vf, vf_mbox_queue;</div><div class='add'>+	struct octep_mbox *mbox;</div><div class='add'>+</div><div class='add'>+	/* check if VF PF Mailbox is compatible for this notification */</div><div class='add'>+	if (pfvf_cmd_versions[cmd.s.opcode] &gt; oct-&gt;vf_info[vf_id].mbox_version) {</div><div class='add'>+		dev_dbg(&amp;oct-&gt;pdev-&gt;dev, "VF Mbox doesn't support Notification:%d on VF ver:%d\n",</div><div class='add'>+			cmd.s.opcode, oct-&gt;vf_info[vf_id].mbox_version);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	max_rings_per_vf = CFG_GET_MAX_RPVF(oct-&gt;conf);</div><div class='add'>+	vf_mbox_queue = vf_id * max_rings_per_vf;</div><div class='add'>+	if (!oct-&gt;mbox[vf_mbox_queue]) {</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Notif obtained for bad mbox vf %d\n", vf_id);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	mbox = oct-&gt;mbox[vf_mbox_queue];</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mbox-&gt;lock);</div><div class='add'>+	writeq(cmd.u64, mbox-&gt;pf_vf_data_reg);</div><div class='add'>+	mutex_unlock(&amp;mbox-&gt;lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_set_mtu(struct octep_device *oct, u32 vf_id,</div><div class='add'>+			       union octep_pfvf_mbox_word cmd,</div><div class='add'>+			       union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_mtu(oct, vf_id, cmd.s_set_mtu.mtu, true);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_set_mtu.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Set VF MTU failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_set_mtu.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_get_mtu(struct octep_device *oct, u32 vf_id,</div><div class='add'>+			       union octep_pfvf_mbox_word cmd,</div><div class='add'>+			       union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int max_rx_pktlen = oct-&gt;netdev-&gt;max_mtu + (ETH_HLEN + ETH_FCS_LEN);</div><div class='add'>+</div><div class='add'>+	rsp-&gt;s_set_mtu.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+	rsp-&gt;s_get_mtu.mtu = max_rx_pktlen;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_set_mac_addr(struct octep_device *oct,  u32 vf_id,</div><div class='add'>+				    union octep_pfvf_mbox_word cmd,</div><div class='add'>+				    union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_mac_addr(oct, vf_id, cmd.s_set_mac.mac_addr, true);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_set_mac.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Set VF MAC address failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_set_mac.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_get_mac_addr(struct octep_device *oct,  u32 vf_id,</div><div class='add'>+				    union octep_pfvf_mbox_word cmd,</div><div class='add'>+				    union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_get_mac_addr(oct, vf_id, rsp-&gt;s_set_mac.mac_addr);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_set_mac.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Get VF MAC address failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_set_mac.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_dev_remove(struct octep_device *oct,  u32 vf_id,</div><div class='add'>+				  union octep_pfvf_mbox_word cmd,</div><div class='add'>+				  union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_dev_remove(oct, vf_id);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Failed to acknowledge fw of vf %d removal\n",</div><div class='add'>+			vf_id);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_get_fw_info(struct octep_device *oct,  u32 vf_id,</div><div class='add'>+				   union octep_pfvf_mbox_word cmd,</div><div class='add'>+				   union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	struct octep_fw_info fw_info;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_get_info(oct, vf_id, &amp;fw_info);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_fw_info.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Get VF info failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rsp-&gt;s_fw_info.pkind = fw_info.pkind;</div><div class='add'>+	rsp-&gt;s_fw_info.fsz = fw_info.fsz;</div><div class='add'>+	rsp-&gt;s_fw_info.rx_ol_flags = fw_info.rx_ol_flags;</div><div class='add'>+	rsp-&gt;s_fw_info.tx_ol_flags = fw_info.tx_ol_flags;</div><div class='add'>+</div><div class='add'>+	rsp-&gt;s_fw_info.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_set_offloads(struct octep_device *oct, u32 vf_id,</div><div class='add'>+				    union octep_pfvf_mbox_word cmd,</div><div class='add'>+				    union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	struct octep_ctrl_net_offloads offloads = {</div><div class='add'>+		.rx_offloads = cmd.s_offloads.rx_ol_flags,</div><div class='add'>+		.tx_offloads = cmd.s_offloads.tx_ol_flags</div><div class='add'>+	};</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = octep_ctrl_net_set_offloads(oct, vf_id, &amp;offloads, true);</div><div class='add'>+	if (err) {</div><div class='add'>+		rsp-&gt;s_offloads.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "Set VF offloads failed via host control Mbox\n");</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+	rsp-&gt;s_offloads.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int octep_setup_pfvf_mbox(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	int i = 0, num_vfs = 0, rings_per_vf = 0;</div><div class='add'>+	int ring = 0;</div><div class='add'>+</div><div class='add'>+	num_vfs = oct-&gt;conf-&gt;sriov_cfg.active_vfs;</div><div class='add'>+	rings_per_vf = oct-&gt;conf-&gt;sriov_cfg.max_rings_per_vf;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_vfs; i++) {</div><div class='add'>+		ring  = rings_per_vf * i;</div><div class='add'>+		oct-&gt;mbox[ring] = vzalloc(sizeof(*oct-&gt;mbox[ring]));</div><div class='add'>+</div><div class='add'>+		if (!oct-&gt;mbox[ring])</div><div class='add'>+			goto free_mbox;</div><div class='add'>+</div><div class='add'>+		memset(oct-&gt;mbox[ring], 0, sizeof(struct octep_mbox));</div><div class='add'>+		memset(&amp;oct-&gt;vf_info[i], 0, sizeof(struct octep_pfvf_info));</div><div class='add'>+		mutex_init(&amp;oct-&gt;mbox[ring]-&gt;lock);</div><div class='add'>+		INIT_WORK(&amp;oct-&gt;mbox[ring]-&gt;wk.work, octep_pfvf_mbox_work);</div><div class='add'>+		oct-&gt;mbox[ring]-&gt;wk.ctxptr = oct-&gt;mbox[ring];</div><div class='add'>+		oct-&gt;mbox[ring]-&gt;oct = oct;</div><div class='add'>+		oct-&gt;mbox[ring]-&gt;vf_id = i;</div><div class='add'>+		oct-&gt;hw_ops.setup_mbox_regs(oct, ring);</div><div class='add'>+	}</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_mbox:</div><div class='add'>+	while (i) {</div><div class='add'>+		i--;</div><div class='add'>+		ring  = rings_per_vf * i;</div><div class='add'>+		cancel_work_sync(&amp;oct-&gt;mbox[ring]-&gt;wk.work);</div><div class='add'>+		mutex_destroy(&amp;oct-&gt;mbox[ring]-&gt;lock);</div><div class='add'>+		vfree(oct-&gt;mbox[ring]);</div><div class='add'>+		oct-&gt;mbox[ring] = NULL;</div><div class='add'>+	}</div><div class='add'>+	return -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void octep_delete_pfvf_mbox(struct octep_device *oct)</div><div class='add'>+{</div><div class='add'>+	int rings_per_vf = oct-&gt;conf-&gt;sriov_cfg.max_rings_per_vf;</div><div class='add'>+	int num_vfs = oct-&gt;conf-&gt;sriov_cfg.active_vfs;</div><div class='add'>+	int i = 0, ring = 0, vf_srn = 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; num_vfs; i++) {</div><div class='add'>+		ring  = vf_srn + rings_per_vf * i;</div><div class='add'>+		if (!oct-&gt;mbox[ring])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (work_pending(&amp;oct-&gt;mbox[ring]-&gt;wk.work))</div><div class='add'>+			cancel_work_sync(&amp;oct-&gt;mbox[ring]-&gt;wk.work);</div><div class='add'>+</div><div class='add'>+		mutex_destroy(&amp;oct-&gt;mbox[ring]-&gt;lock);</div><div class='add'>+		vfree(oct-&gt;mbox[ring]);</div><div class='add'>+		oct-&gt;mbox[ring] = NULL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void octep_pfvf_pf_get_data(struct octep_device *oct,</div><div class='add'>+				   struct octep_mbox *mbox, int vf_id,</div><div class='add'>+				   union octep_pfvf_mbox_word cmd,</div><div class='add'>+				   union octep_pfvf_mbox_word *rsp)</div><div class='add'>+{</div><div class='add'>+	int length = 0;</div><div class='add'>+	int i = 0;</div><div class='add'>+	int err;</div><div class='add'>+	struct octep_iface_link_info link_info;</div><div class='add'>+	struct octep_iface_rx_stats rx_stats;</div><div class='add'>+	struct octep_iface_tx_stats tx_stats;</div><div class='add'>+</div><div class='add'>+	rsp-&gt;s_data.type = OCTEP_PFVF_MBOX_TYPE_RSP_ACK;</div><div class='add'>+</div><div class='add'>+	if (cmd.s_data.frag != OCTEP_PFVF_MBOX_MORE_FRAG_FLAG) {</div><div class='add'>+		mbox-&gt;config_data_index = 0;</div><div class='add'>+		memset(mbox-&gt;config_data, 0, MAX_VF_PF_MBOX_DATA_SIZE);</div><div class='add'>+		/* Based on the OPCODE CMD the PF driver</div><div class='add'>+		 * specific API should be called to fetch</div><div class='add'>+		 * the requested data</div><div class='add'>+		 */</div><div class='add'>+		switch (cmd.s.opcode) {</div><div class='add'>+		case OCTEP_PFVF_MBOX_CMD_GET_LINK_INFO:</div><div class='add'>+			memset(&amp;link_info, 0, sizeof(link_info));</div><div class='add'>+			err = octep_ctrl_net_get_link_info(oct, vf_id, &amp;link_info);</div><div class='add'>+			if (!err) {</div><div class='add'>+				mbox-&gt;message_len = sizeof(link_info);</div><div class='add'>+				*((int32_t *)rsp-&gt;s_data.data) = mbox-&gt;message_len;</div><div class='add'>+				memcpy(mbox-&gt;config_data, (u8 *)&amp;link_info, sizeof(link_info));</div><div class='add'>+			} else {</div><div class='add'>+				rsp-&gt;s_data.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		case OCTEP_PFVF_MBOX_CMD_GET_STATS:</div><div class='add'>+			memset(&amp;rx_stats, 0, sizeof(rx_stats));</div><div class='add'>+			memset(&amp;tx_stats, 0, sizeof(tx_stats));</div><div class='add'>+			err = octep_ctrl_net_get_if_stats(oct, vf_id, &amp;rx_stats, &amp;tx_stats);</div><div class='add'>+			if (!err) {</div><div class='add'>+				mbox-&gt;message_len = sizeof(rx_stats) + sizeof(tx_stats);</div><div class='add'>+				*((int32_t *)rsp-&gt;s_data.data) = mbox-&gt;message_len;</div><div class='add'>+				memcpy(mbox-&gt;config_data, (u8 *)&amp;rx_stats, sizeof(rx_stats));</div><div class='add'>+				memcpy(mbox-&gt;config_data + sizeof(rx_stats), (u8 *)&amp;tx_stats,</div><div class='add'>+				       sizeof(tx_stats));</div><div class='add'>+</div><div class='add'>+			} else {</div><div class='add'>+				rsp-&gt;s_data.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		*((int32_t *)rsp-&gt;s_data.data) = mbox-&gt;message_len;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mbox-&gt;message_len &gt; OCTEP_PFVF_MBOX_MAX_DATA_SIZE)</div><div class='add'>+		length = OCTEP_PFVF_MBOX_MAX_DATA_SIZE;</div><div class='add'>+	else</div><div class='add'>+		length = mbox-&gt;message_len;</div><div class='add'>+</div><div class='add'>+	mbox-&gt;message_len -= length;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; length; i++) {</div><div class='add'>+		rsp-&gt;s_data.data[i] =</div><div class='add'>+			mbox-&gt;config_data[mbox-&gt;config_data_index];</div><div class='add'>+		mbox-&gt;config_data_index++;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void octep_pfvf_notify(struct octep_device *oct, struct octep_ctrl_mbox_msg *msg)</div><div class='add'>+{</div><div class='add'>+	union octep_pfvf_mbox_word notif = { 0 };</div><div class='add'>+	struct octep_ctrl_net_f2h_req *req;</div><div class='add'>+</div><div class='add'>+	req = (struct octep_ctrl_net_f2h_req *)msg-&gt;sg_list[0].msg;</div><div class='add'>+	switch (req-&gt;hdr.s.cmd) {</div><div class='add'>+	case OCTEP_CTRL_NET_F2H_CMD_LINK_STATUS:</div><div class='add'>+		notif.s_link_status.opcode = OCTEP_PFVF_MBOX_NOTIF_LINK_STATUS;</div><div class='add'>+		notif.s_link_status.status = req-&gt;link.state;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		pr_info("Unknown mbox notif for vf: %u\n",</div><div class='add'>+			req-&gt;hdr.s.cmd);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	notif.s.type = OCTEP_PFVF_MBOX_TYPE_CMD;</div><div class='add'>+	octep_send_notification(oct, msg-&gt;hdr.s.vf_idx, notif);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void octep_pfvf_mbox_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct octep_pfvf_mbox_wk *wk = container_of(work, struct octep_pfvf_mbox_wk, work);</div><div class='add'>+	union octep_pfvf_mbox_word cmd = { 0 };</div><div class='add'>+	union octep_pfvf_mbox_word rsp = { 0 };</div><div class='add'>+	struct octep_mbox *mbox = NULL;</div><div class='add'>+	struct octep_device *oct = NULL;</div><div class='add'>+	int vf_id;</div><div class='add'>+</div><div class='add'>+	mbox = (struct octep_mbox *)wk-&gt;ctxptr;</div><div class='add'>+	oct = (struct octep_device *)mbox-&gt;oct;</div><div class='add'>+	vf_id = mbox-&gt;vf_id;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mbox-&gt;lock);</div><div class='add'>+	cmd.u64 = readq(mbox-&gt;vf_pf_data_reg);</div><div class='add'>+	rsp.u64 = 0;</div><div class='add'>+</div><div class='add'>+	switch (cmd.s.opcode) {</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_VERSION:</div><div class='add'>+		octep_pfvf_validate_version(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_LINK_STATUS:</div><div class='add'>+		octep_pfvf_get_link_status(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_SET_LINK_STATUS:</div><div class='add'>+		octep_pfvf_set_link_status(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_SET_RX_STATE:</div><div class='add'>+		octep_pfvf_set_rx_state(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_SET_MTU:</div><div class='add'>+		octep_pfvf_set_mtu(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_SET_MAC_ADDR:</div><div class='add'>+		octep_pfvf_set_mac_addr(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_MAC_ADDR:</div><div class='add'>+		octep_pfvf_get_mac_addr(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_LINK_INFO:</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_STATS:</div><div class='add'>+		octep_pfvf_pf_get_data(oct, mbox, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_MTU:</div><div class='add'>+		octep_pfvf_get_mtu(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_DEV_REMOVE:</div><div class='add'>+		octep_pfvf_dev_remove(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_GET_FW_INFO:</div><div class='add'>+		octep_pfvf_get_fw_info(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	case OCTEP_PFVF_MBOX_CMD_SET_OFFLOADS:</div><div class='add'>+		octep_pfvf_set_offloads(oct, vf_id, cmd, &amp;rsp);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(&amp;oct-&gt;pdev-&gt;dev, "PF-VF mailbox: invalid opcode %d\n", cmd.s.opcode);</div><div class='add'>+		rsp.s.type = OCTEP_PFVF_MBOX_TYPE_RSP_NACK;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+	writeq(rsp.u64, mbox-&gt;vf_pf_data_reg);</div><div class='add'>+	mutex_unlock(&amp;mbox-&gt;lock);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h b/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h<br/>new file mode 100644<br/>index 000000000000..0dc6eead292a<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_pfvf_mbox.h</a></div><div class='hunk'>@@ -0,0 +1,167 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Marvell Octeon EP (EndPoint) Ethernet Driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2020 Marvell.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _OCTEP_PFVF_MBOX_H_</div><div class='add'>+#define _OCTEP_PFVF_MBOX_H_</div><div class='add'>+</div><div class='add'>+/* VF flags */</div><div class='add'>+#define OCTEON_PFVF_FLAG_MAC_SET_BY_PF  BIT_ULL(0) /* PF has set VF MAC address */</div><div class='add'>+#define OCTEON_SDP_16K_HW_FRS  16380UL</div><div class='add'>+#define OCTEON_SDP_64K_HW_FRS  65531UL</div><div class='add'>+</div><div class='add'>+/* When a new command is implemented,PF Mbox version should be bumped.</div><div class='add'>+ */</div><div class='add'>+enum octep_pfvf_mbox_version {</div><div class='add'>+	OCTEP_PFVF_MBOX_VERSION_V0,</div><div class='add'>+	OCTEP_PFVF_MBOX_VERSION_V1,</div><div class='add'>+	OCTEP_PFVF_MBOX_VERSION_V2,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define OCTEP_PFVF_MBOX_VERSION_CURRENT	OCTEP_PFVF_MBOX_VERSION_V2</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_mbox_opcode {</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_VERSION,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_SET_MTU,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_SET_MAC_ADDR,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_MAC_ADDR,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_LINK_INFO,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_STATS,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_SET_RX_STATE,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_SET_LINK_STATUS,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_LINK_STATUS,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_MTU,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_DEV_REMOVE,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_GET_FW_INFO,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_SET_OFFLOADS,</div><div class='add'>+	OCTEP_PFVF_MBOX_NOTIF_LINK_STATUS,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_MAX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_mbox_word_type {</div><div class='add'>+	OCTEP_PFVF_MBOX_TYPE_CMD,</div><div class='add'>+	OCTEP_PFVF_MBOX_TYPE_RSP_ACK,</div><div class='add'>+	OCTEP_PFVF_MBOX_TYPE_RSP_NACK,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_mbox_cmd_status {</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_STATUS_NOT_SETUP = 1,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_STATUS_TIMEDOUT = 2,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_STATUS_NACK = 3,</div><div class='add'>+	OCTEP_PFVF_MBOX_CMD_STATUS_BUSY = 4</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_mbox_state {</div><div class='add'>+	OCTEP_PFVF_MBOX_STATE_IDLE = 0,</div><div class='add'>+	OCTEP_PFVF_MBOX_STATE_BUSY = 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_link_status {</div><div class='add'>+	OCTEP_PFVF_LINK_STATUS_DOWN,</div><div class='add'>+	OCTEP_PFVF_LINK_STATUS_UP,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_link_speed {</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_NONE,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_1000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_10000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_25000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_40000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_50000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_100000,</div><div class='add'>+	OCTEP_PFVF_LINK_SPEED_LAST,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_link_duplex {</div><div class='add'>+	OCTEP_PFVF_LINK_HALF_DUPLEX,</div><div class='add'>+	OCTEP_PFVF_LINK_FULL_DUPLEX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum octep_pfvf_link_autoneg {</div><div class='add'>+	OCTEP_PFVF_LINK_AUTONEG,</div><div class='add'>+	OCTEP_PFVF_LINK_FIXED,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define OCTEP_PFVF_MBOX_TIMEOUT_MS     500</div><div class='add'>+#define OCTEP_PFVF_MBOX_MAX_RETRIES    2</div><div class='add'>+#define OCTEP_PFVF_MBOX_MAX_DATA_SIZE  6</div><div class='add'>+#define OCTEP_PFVF_MBOX_MORE_FRAG_FLAG 1</div><div class='add'>+#define OCTEP_PFVF_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1)</div><div class='add'>+</div><div class='add'>+union octep_pfvf_mbox_word {</div><div class='add'>+	u64 u64;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+		u64 data:48;</div><div class='add'>+	} s;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 frag:1;</div><div class='add'>+		u64 rsvd:5;</div><div class='add'>+		u8 data[6];</div><div class='add'>+	} s_data;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+		u64 version:48;</div><div class='add'>+	} s_version;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+		u8 mac_addr[6];</div><div class='add'>+	} s_set_mac;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+		u64 mtu:48;</div><div class='add'>+	} s_set_mtu;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+		u64 mtu:48;</div><div class='add'>+	} s_get_mtu;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 state:1;</div><div class='add'>+		u64 rsvd:53;</div><div class='add'>+	} s_link_state;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 status:1;</div><div class='add'>+		u64 rsvd:53;</div><div class='add'>+	} s_link_status;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 pkind:8;</div><div class='add'>+		u64 fsz:8;</div><div class='add'>+		u64 rx_ol_flags:16;</div><div class='add'>+		u64 tx_ol_flags:16;</div><div class='add'>+		u64 rsvd:6;</div><div class='add'>+	} s_fw_info;</div><div class='add'>+	struct {</div><div class='add'>+		u64 opcode:8;</div><div class='add'>+		u64 type:2;</div><div class='add'>+		u64 rsvd:22;</div><div class='add'>+		u64 rx_ol_flags:16;</div><div class='add'>+		u64 tx_ol_flags:16;</div><div class='add'>+	} s_offloads;</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+void octep_pfvf_mbox_work(struct work_struct *work);</div><div class='add'>+int octep_setup_pfvf_mbox(struct octep_device *oct);</div><div class='add'>+void octep_delete_pfvf_mbox(struct octep_device *oct);</div><div class='add'>+void octep_pfvf_notify(struct octep_device *oct, struct octep_ctrl_mbox_msg *msg);</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h<br/>index 0a43983e9101..ca473502d7a0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h</a></div><div class='hunk'>@@ -208,6 +208,9 @@</div><div class='ctx'> #define    CN93_SDP_R_MBOX_PF_VF_INT_START        0x10220</div><div class='ctx'> #define    CN93_SDP_R_MBOX_VF_PF_DATA_START       0x10230</div><div class='ctx'> </div><div class='add'>+#define    CN93_SDP_MBOX_VF_PF_DATA_START       0x24000</div><div class='add'>+#define    CN93_SDP_MBOX_PF_VF_DATA_START       0x22000</div><div class='add'>+</div><div class='ctx'> #define    CN93_SDP_R_MBOX_PF_VF_DATA(ring)		\</div><div class='ctx'> 	(CN93_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_RING_OFFSET))</div><div class='ctx'> </div><div class='hunk'>@@ -217,6 +220,12 @@</div><div class='ctx'> #define    CN93_SDP_R_MBOX_VF_PF_DATA(ring)		\</div><div class='ctx'> 	(CN93_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_RING_OFFSET))</div><div class='ctx'> </div><div class='add'>+#define    CN93_SDP_MBOX_VF_PF_DATA(ring)          \</div><div class='add'>+	(CN93_SDP_MBOX_VF_PF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CN93_SDP_MBOX_PF_VF_DATA(ring)      \</div><div class='add'>+	(CN93_SDP_MBOX_PF_VF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET))</div><div class='add'>+</div><div class='ctx'> /* ##################### Interrupt Registers ########################## */</div><div class='ctx'> #define	   CN93_SDP_R_ERR_TYPE_START	          0x10400</div><div class='ctx'> </div><div class='hunk'>@@ -362,6 +371,10 @@</div><div class='ctx'> #define    CN93_SDP_MAC_PF_RING_CTL_SRN(val)   (((val) &gt;&gt; 8) &amp; 0xFF)</div><div class='ctx'> #define    CN93_SDP_MAC_PF_RING_CTL_RPPF(val)  (((val) &gt;&gt; 16) &amp; 0x3F)</div><div class='ctx'> </div><div class='add'>+#define    CN98_SDP_MAC_PF_RING_CTL_NPFS(val)  (((val) &gt;&gt; 48) &amp; 0xF)</div><div class='add'>+#define    CN98_SDP_MAC_PF_RING_CTL_SRN(val)   ((val) &amp; 0xFF)</div><div class='add'>+#define    CN98_SDP_MAC_PF_RING_CTL_RPPF(val)  (((val) &gt;&gt; 32) &amp; 0x3F)</div><div class='add'>+</div><div class='ctx'> /* Number of non-queue interrupts in CN93xx */</div><div class='ctx'> #define    CN93_NUM_NON_IOQ_INTR    16</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h<br/>new file mode 100644<br/>index 000000000000..e637d7c8224d<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h</a></div><div class='hunk'>@@ -0,0 +1,416 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* Marvell Octeon EP (EndPoint) Ethernet Driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright (C) 2020 Marvell.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#ifndef _OCTEP_REGS_CNXK_PF_H_</div><div class='add'>+#define _OCTEP_REGS_CNXK_PF_H_</div><div class='add'>+</div><div class='add'>+/* ############################ RST ######################### */</div><div class='add'>+#define    CNXK_RST_BOOT               0x000087E006001600ULL</div><div class='add'>+#define    CNXK_RST_CHIP_DOMAIN_W1S    0x000087E006001810ULL</div><div class='add'>+#define    CNXK_RST_CORE_DOMAIN_W1S    0x000087E006001820ULL</div><div class='add'>+#define    CNXK_RST_CORE_DOMAIN_W1C    0x000087E006001828ULL</div><div class='add'>+</div><div class='add'>+#define     CNXK_CONFIG_XPANSION_BAR             0x38</div><div class='add'>+#define     CNXK_CONFIG_PCIE_CAP                 0x70</div><div class='add'>+#define     CNXK_CONFIG_PCIE_DEVCAP              0x74</div><div class='add'>+#define     CNXK_CONFIG_PCIE_DEVCTL              0x78</div><div class='add'>+#define     CNXK_CONFIG_PCIE_LINKCAP             0x7C</div><div class='add'>+#define     CNXK_CONFIG_PCIE_LINKCTL             0x80</div><div class='add'>+#define     CNXK_CONFIG_PCIE_SLOTCAP             0x84</div><div class='add'>+#define     CNXK_CONFIG_PCIE_SLOTCTL             0x88</div><div class='add'>+</div><div class='add'>+#define     CNXK_PCIE_SRIOV_FDL                  0x188      /* 0x98 */</div><div class='add'>+#define     CNXK_PCIE_SRIOV_FDL_BIT_POS          0x10</div><div class='add'>+#define     CNXK_PCIE_SRIOV_FDL_MASK             0xFF</div><div class='add'>+</div><div class='add'>+#define     CNXK_CONFIG_PCIE_FLTMSK              0x720</div><div class='add'>+</div><div class='add'>+/* ################# Offsets of RING, EPF, MAC ######################### */</div><div class='add'>+#define    CNXK_RING_OFFSET                      (0x1ULL &lt;&lt; 17)</div><div class='add'>+#define    CNXK_EPF_OFFSET                       (0x1ULL &lt;&lt; 25)</div><div class='add'>+#define    CNXK_MAC_OFFSET                       (0x1ULL &lt;&lt; 4)</div><div class='add'>+#define    CNXK_BIT_ARRAY_OFFSET                 (0x1ULL &lt;&lt; 4)</div><div class='add'>+#define    CNXK_EPVF_RING_OFFSET                 (0x1ULL &lt;&lt; 4)</div><div class='add'>+</div><div class='add'>+/* ################# Scratch Registers ######################### */</div><div class='add'>+#define    CNXK_SDP_EPF_SCRATCH                  0x209E0</div><div class='add'>+</div><div class='add'>+/* ################# Window Registers ######################### */</div><div class='add'>+#define    CNXK_SDP_WIN_WR_ADDR64                0x20000</div><div class='add'>+#define    CNXK_SDP_WIN_RD_ADDR64                0x20010</div><div class='add'>+#define    CNXK_SDP_WIN_WR_DATA64                0x20020</div><div class='add'>+#define    CNXK_SDP_WIN_WR_MASK_REG              0x20030</div><div class='add'>+#define    CNXK_SDP_WIN_RD_DATA64                0x20040</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_MAC_NUMBER                   0x2C100</div><div class='add'>+</div><div class='add'>+/* ################# Global Previliged registers ######################### */</div><div class='add'>+#define    CNXK_SDP_EPF_RINFO                    0x209F0</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_EPF_RINFO_SRN(val)           ((val) &amp; 0x7F)</div><div class='add'>+#define    CNXK_SDP_EPF_RINFO_RPVF(val)          (((val) &gt;&gt; 32) &amp; 0xF)</div><div class='add'>+#define    CNXK_SDP_EPF_RINFO_NVFS(val)          (((val) &gt;&gt; 48) &amp; 0x7F)</div><div class='add'>+</div><div class='add'>+/* SDP Function select */</div><div class='add'>+#define    CNXK_SDP_FUNC_SEL_EPF_BIT_POS         7</div><div class='add'>+#define    CNXK_SDP_FUNC_SEL_FUNC_BIT_POS        0</div><div class='add'>+</div><div class='add'>+/* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */</div><div class='add'>+#define    CNXK_SDP_R_IN_CONTROL_START           0x10000</div><div class='add'>+#define    CNXK_SDP_R_IN_ENABLE_START            0x10010</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_BADDR_START       0x10020</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_RSIZE_START       0x10030</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_DBELL_START       0x10040</div><div class='add'>+#define    CNXK_SDP_R_IN_CNTS_START              0x10050</div><div class='add'>+#define    CNXK_SDP_R_IN_INT_LEVELS_START        0x10060</div><div class='add'>+#define    CNXK_SDP_R_IN_PKT_CNT_START           0x10080</div><div class='add'>+#define    CNXK_SDP_R_IN_BYTE_CNT_START          0x10090</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_CONTROL(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_CONTROL_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_ENABLE(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_ENABLE_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_BADDR(ring)	\</div><div class='add'>+	(CNXK_SDP_R_IN_INSTR_BADDR_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_RSIZE(ring)	\</div><div class='add'>+	(CNXK_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INSTR_DBELL(ring)	\</div><div class='add'>+	(CNXK_SDP_R_IN_INSTR_DBELL_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_CNTS(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_CNTS_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INT_LEVELS(ring)	\</div><div class='add'>+	(CNXK_SDP_R_IN_INT_LEVELS_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_PKT_CNT(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_PKT_CNT_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_BYTE_CNT(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_BYTE_CNT_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+/* Rings per Virtual Function */</div><div class='add'>+#define    CNXK_R_IN_CTL_RPVF_MASK	(0xF)</div><div class='add'>+#define    CNXK_R_IN_CTL_RPVF_POS	(48)</div><div class='add'>+</div><div class='add'>+/* Number of instructions to be read in one MAC read request.</div><div class='add'>+ * setting to Max value(4)</div><div class='add'>+ */</div><div class='add'>+#define    CNXK_R_IN_CTL_IDLE                    (0x1ULL &lt;&lt; 28)</div><div class='add'>+#define    CNXK_R_IN_CTL_RDSIZE                  (0x3ULL &lt;&lt; 25)</div><div class='add'>+#define    CNXK_R_IN_CTL_IS_64B                  (0x1ULL &lt;&lt; 24)</div><div class='add'>+#define    CNXK_R_IN_CTL_D_NSR                   (0x1ULL &lt;&lt; 8)</div><div class='add'>+#define    CNXK_R_IN_CTL_D_ESR                   (0x1ULL &lt;&lt; 6)</div><div class='add'>+#define    CNXK_R_IN_CTL_D_ROR                   (0x1ULL &lt;&lt; 5)</div><div class='add'>+#define    CNXK_R_IN_CTL_NSR                     (0x1ULL &lt;&lt; 3)</div><div class='add'>+#define    CNXK_R_IN_CTL_ESR                     (0x1ULL &lt;&lt; 1)</div><div class='add'>+#define    CNXK_R_IN_CTL_ROR                     (0x1ULL &lt;&lt; 0)</div><div class='add'>+</div><div class='add'>+#define    CNXK_R_IN_CTL_MASK  (CNXK_R_IN_CTL_RDSIZE | CNXK_R_IN_CTL_IS_64B)</div><div class='add'>+</div><div class='add'>+/* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */</div><div class='add'>+#define    CNXK_SDP_R_OUT_CNTS_START              0x10100</div><div class='add'>+#define    CNXK_SDP_R_OUT_INT_LEVELS_START        0x10110</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_BADDR_START       0x10120</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_RSIZE_START       0x10130</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_DBELL_START       0x10140</div><div class='add'>+#define    CNXK_SDP_R_OUT_CONTROL_START           0x10150</div><div class='add'>+#define    CNXK_SDP_R_OUT_WMARK_START             0x10160</div><div class='add'>+#define    CNXK_SDP_R_OUT_ENABLE_START            0x10170</div><div class='add'>+#define    CNXK_SDP_R_OUT_PKT_CNT_START           0x10180</div><div class='add'>+#define    CNXK_SDP_R_OUT_BYTE_CNT_START          0x10190</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_CONTROL(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_CONTROL_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_ENABLE(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_ENABLE_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_BADDR(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_RSIZE(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_SLIST_DBELL(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_WMARK(ring)         \</div><div class='add'>+	(CNXK_SDP_R_OUT_WMARK_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_CNTS(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_CNTS_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_INT_LEVELS(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_INT_LEVELS_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_PKT_CNT(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_PKT_CNT_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_BYTE_CNT(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_BYTE_CNT_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+/*------------------ R_OUT Masks ----------------*/</div><div class='add'>+#define    CNXK_R_OUT_INT_LEVELS_BMODE            BIT_ULL(63)</div><div class='add'>+#define    CNXK_R_OUT_INT_LEVELS_TIMET            (32)</div><div class='add'>+</div><div class='add'>+#define    CNXK_R_OUT_CTL_IDLE                    BIT_ULL(40)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ES_I                    BIT_ULL(34)</div><div class='add'>+#define    CNXK_R_OUT_CTL_NSR_I                   BIT_ULL(33)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ROR_I                   BIT_ULL(32)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ES_D                    BIT_ULL(30)</div><div class='add'>+#define    CNXK_R_OUT_CTL_NSR_D                   BIT_ULL(29)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ROR_D                   BIT_ULL(28)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ES_P                    BIT_ULL(26)</div><div class='add'>+#define    CNXK_R_OUT_CTL_NSR_P                   BIT_ULL(25)</div><div class='add'>+#define    CNXK_R_OUT_CTL_ROR_P                   BIT_ULL(24)</div><div class='add'>+#define    CNXK_R_OUT_CTL_IMODE                   BIT_ULL(23)</div><div class='add'>+</div><div class='add'>+/* ############### Interrupt Moderation Registers ############### */</div><div class='add'>+#define CNXK_SDP_R_IN_INT_MDRT_CTL0_START         0x10280</div><div class='add'>+#define CNXK_SDP_R_IN_INT_MDRT_CTL1_START         0x102A0</div><div class='add'>+#define CNXK_SDP_R_IN_INT_MDRT_DBG_START          0x102C0</div><div class='add'>+</div><div class='add'>+#define CNXK_SDP_R_OUT_INT_MDRT_CTL0_START        0x10380</div><div class='add'>+#define CNXK_SDP_R_OUT_INT_MDRT_CTL1_START        0x103A0</div><div class='add'>+#define CNXK_SDP_R_OUT_INT_MDRT_DBG_START         0x103C0</div><div class='add'>+</div><div class='add'>+#define CNXK_SDP_R_MBOX_ISM_START                 0x10500</div><div class='add'>+#define CNXK_SDP_R_OUT_CNTS_ISM_START             0x10510</div><div class='add'>+#define CNXK_SDP_R_IN_CNTS_ISM_START              0x10520</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INT_MDRT_CTL0(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_INT_MDRT_CTL0_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INT_MDRT_CTL1(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_INT_MDRT_CTL1_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_INT_MDRT_DBG(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_INT_MDRT_DBG_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_INT_MDRT_CTL0(ring)		\</div><div class='add'>+	(CNXK_SDP_R_OUT_INT_MDRT_CTL0_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_INT_MDRT_CTL1(ring)		\</div><div class='add'>+	(CNXK_SDP_R_OUT_INT_MDRT_CTL1_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_INT_MDRT_DBG(ring)		\</div><div class='add'>+	(CNXK_SDP_R_OUT_INT_MDRT_DBG_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_ISM(ring)          \</div><div class='add'>+	(CNXK_SDP_R_MBOX_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_CNTS_ISM(ring)          \</div><div class='add'>+	(CNXK_SDP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_CNTS_ISM(ring)          \</div><div class='add'>+	(CNXK_SDP_R_IN_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+/* ##################### Mail Box Registers ########################## */</div><div class='add'>+/* INT register for VF. when a MBOX write from PF happed to a VF,</div><div class='add'>+ * corresponding bit will be set in this register as well as in</div><div class='add'>+ * PF_VF_INT register.</div><div class='add'>+ *</div><div class='add'>+ * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT</div><div class='add'>+ */</div><div class='add'>+/* Basically first 3 are from PF to VF. The last one is data from VF to PF */</div><div class='add'>+#define    CNXK_SDP_R_MBOX_PF_VF_DATA_START       0x10210</div><div class='add'>+#define    CNXK_SDP_R_MBOX_PF_VF_INT_START        0x10220</div><div class='add'>+#define    CNXK_SDP_R_MBOX_VF_PF_DATA_START       0x10230</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_MBOX_VF_PF_DATA_START       0x24000</div><div class='add'>+#define    CNXK_SDP_MBOX_PF_VF_DATA_START       0x22000</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_PF_VF_DATA(ring)		\</div><div class='add'>+	(CNXK_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_PF_VF_INT(ring)		\</div><div class='add'>+	(CNXK_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_VF_PF_DATA(ring)		\</div><div class='add'>+	(CNXK_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_MBOX_VF_PF_DATA(ring)          \</div><div class='add'>+	(CNXK_SDP_MBOX_VF_PF_DATA_START + ((ring) * CNXK_EPVF_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_MBOX_PF_VF_DATA(ring)      \</div><div class='add'>+	(CNXK_SDP_MBOX_PF_VF_DATA_START + ((ring) * CNXK_EPVF_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+/* ##################### Interrupt Registers ########################## */</div><div class='add'>+#define	   CNXK_SDP_R_ERR_TYPE_START	          0x10400</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_ERR_TYPE(ring)		\</div><div class='add'>+	(CNXK_SDP_R_ERR_TYPE_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_ISM_START              0x10500</div><div class='add'>+#define    CNXK_SDP_R_OUT_CNTS_ISM_START          0x10510</div><div class='add'>+#define    CNXK_SDP_R_IN_CNTS_ISM_START           0x10520</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_MBOX_ISM(ring)		\</div><div class='add'>+	(CNXK_SDP_R_MBOX_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_OUT_CNTS_ISM(ring)	\</div><div class='add'>+	(CNXK_SDP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_R_IN_CNTS_ISM(ring)		\</div><div class='add'>+	(CNXK_SDP_R_IN_CNTS_ISM_START + ((ring) * CNXK_RING_OFFSET))</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_START	          0x20100</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_W1S_START	  0x20120</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_ENA_W1C_START   0x20140</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_ENA_W1S_START   0x20160</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_START          0x20180</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_W1S_START      0x201A0</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C_START  0x201C0</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S_START  0x201E0</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_IRERR_RINT                0x20200</div><div class='add'>+#define	   CNXK_SDP_EPF_IRERR_RINT_W1S            0x20210</div><div class='add'>+#define	   CNXK_SDP_EPF_IRERR_RINT_ENA_W1C        0x20220</div><div class='add'>+#define	   CNXK_SDP_EPF_IRERR_RINT_ENA_W1S        0x20230</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_START          0x20240</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_W1S_START      0x20260</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_ENA_W1C_START  0x20280</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_ENA_W1S_START  0x202A0</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_ORERR_RINT                0x20320</div><div class='add'>+#define	   CNXK_SDP_EPF_ORERR_RINT_W1S            0x20330</div><div class='add'>+#define	   CNXK_SDP_EPF_ORERR_RINT_ENA_W1C        0x20340</div><div class='add'>+#define	   CNXK_SDP_EPF_ORERR_RINT_ENA_W1S        0x20350</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_OEI_RINT                  0x20400</div><div class='add'>+#define	   CNXK_SDP_EPF_OEI_RINT_W1S              0x20500</div><div class='add'>+#define	   CNXK_SDP_EPF_OEI_RINT_ENA_W1C          0x20600</div><div class='add'>+#define	   CNXK_SDP_EPF_OEI_RINT_ENA_W1S          0x20700</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_RINT                  0x20800</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_RINT_W1S              0x20810</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_RINT_ENA_W1C          0x20820</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_RINT_ENA_W1S          0x20830</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_INT_LEVEL_START	    0x20840</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_CNT_START	            0x20860</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_TIM_START	            0x20880</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_MISC_RINT                 0x208A0</div><div class='add'>+#define	   CNXK_SDP_EPF_MISC_RINT_W1S	            0x208B0</div><div class='add'>+#define	   CNXK_SDP_EPF_MISC_RINT_ENA_W1C         0x208C0</div><div class='add'>+#define	   CNXK_SDP_EPF_MISC_RINT_ENA_W1S         0x208D0</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_START           0x208E0</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_W1S_START       0x20900</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C_START   0x20920</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S_START   0x20940</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_START            0x20960</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_W1S_START        0x20980</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C_START    0x209A0</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S_START    0x209C0</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_MBOX_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_W1S(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_ENA_W1C(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_MBOX_RINT_ENA_W1S(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_VFIRE_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_W1S(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_VFORE_RINT_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_W1S(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_ENA_W1C(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_VFORE_RINT_ENA_W1S(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_DMA_VF_RINT_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_W1S(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_PP_VF_RINT_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_W1S(index)		\</div><div class='add'>+		(CNXK_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S(index)	\</div><div class='add'>+		(CNXK_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CNXK_BIT_ARRAY_OFFSET))</div><div class='add'>+</div><div class='add'>+/*------------------ Interrupt Masks ----------------*/</div><div class='add'>+#define	   CNXK_INTR_R_SEND_ISM       BIT_ULL(63)</div><div class='add'>+#define	   CNXK_INTR_R_OUT_INT        BIT_ULL(62)</div><div class='add'>+#define    CNXK_INTR_R_IN_INT         BIT_ULL(61)</div><div class='add'>+#define    CNXK_INTR_R_MBOX_INT       BIT_ULL(60)</div><div class='add'>+#define    CNXK_INTR_R_RESEND         BIT_ULL(59)</div><div class='add'>+#define    CNXK_INTR_R_CLR_TIM        BIT_ULL(58)</div><div class='add'>+</div><div class='add'>+/* ####################### Ring Mapping Registers ################################## */</div><div class='add'>+#define    CNXK_SDP_EPVF_RING_START          0x26000</div><div class='add'>+#define    CNXK_SDP_IN_RING_TB_MAP_START     0x28000</div><div class='add'>+#define    CNXK_SDP_IN_RATE_LIMIT_START      0x2A000</div><div class='add'>+#define    CNXK_SDP_MAC_PF_RING_CTL_START    0x2C000</div><div class='add'>+</div><div class='add'>+#define	   CNXK_SDP_EPVF_RING(ring)		\</div><div class='add'>+		(CNXK_SDP_EPVF_RING_START + ((ring) * CNXK_EPVF_RING_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_IN_RING_TB_MAP(ring)	\</div><div class='add'>+		(CNXK_SDP_N_RING_TB_MAP_START + ((ring) * CNXK_EPVF_RING_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_IN_RATE_LIMIT(ring)		\</div><div class='add'>+		(CNXK_SDP_IN_RATE_LIMIT_START + ((ring) * CNXK_EPVF_RING_OFFSET))</div><div class='add'>+#define	   CNXK_SDP_MAC_PF_RING_CTL(mac)	\</div><div class='add'>+		(CNXK_SDP_MAC_PF_RING_CTL_START + ((mac) * CNXK_MAC_OFFSET))</div><div class='add'>+</div><div class='add'>+#define    CNXK_SDP_MAC_PF_RING_CTL_NPFS(val)  ((val) &amp; 0x3)</div><div class='add'>+#define    CNXK_SDP_MAC_PF_RING_CTL_SRN(val)   (((val) &gt;&gt; 8) &amp; 0x7F)</div><div class='add'>+#define    CNXK_SDP_MAC_PF_RING_CTL_RPPF(val)  (((val) &gt;&gt; 16) &amp; 0x3F)</div><div class='add'>+</div><div class='add'>+/* Number of non-queue interrupts in CNXKxx */</div><div class='add'>+#define    CNXK_NUM_NON_IOQ_INTR    32</div><div class='add'>+</div><div class='add'>+/* bit 0 for control mbox interrupt */</div><div class='add'>+#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX	BIT_ULL(0)</div><div class='add'>+/* bit 1 for firmware heartbeat interrupt */</div><div class='add'>+#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT	BIT_ULL(1)</div><div class='add'>+#define FW_STATUS_RUNNING      2ULL</div><div class='add'>+#define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)      ({ typeof(offset) _off = (offset); \</div><div class='add'>+							  ((0x8e0000008000 | \</div><div class='add'>+							    (uint64_t)(pem) &lt;&lt; 36 \</div><div class='add'>+							    | (pf) &lt;&lt; 18 \</div><div class='add'>+							    | ((_off &gt;&gt; 16) &amp; 1) &lt;&lt; 16 \</div><div class='add'>+							    | (_off &gt;&gt; 3) &lt;&lt; 3) \</div><div class='add'>+							   + (((_off &gt;&gt; 2) &amp; 1) &lt;&lt; 2)); \</div><div class='add'>+							})</div><div class='add'>+</div><div class='add'>+/* Register defines for use with CNXK_PEMX_PFX_CSX_PFCFGX */</div><div class='add'>+#define CNXK_PCIEEP_VSECST_CTL  0x418</div><div class='add'>+</div><div class='add'>+#define CNXK_PEM_BAR4_INDEX		7</div><div class='add'>+#define CNXK_PEM_BAR4_INDEX_SIZE	0x400000ULL</div><div class='add'>+#define CNXK_PEM_BAR4_INDEX_OFFSET	(CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_INDEX_SIZE)</div><div class='add'>+</div><div class='add'>+#endif /* _OCTEP_REGS_CNXK_PF_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c b/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c<br/>index 3c43f8078528..4746a6b258f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.c</a></div><div class='hunk'>@@ -143,7 +143,7 @@ static int octep_setup_oq(struct octep_device *oct, int q_no)</div><div class='ctx'> 	 * additional header is filled-in by Octeon after length field in</div><div class='ctx'> 	 * Rx packets. this header contains additional packet information.</div><div class='ctx'> 	 */</div><div class='del'>-	if (oct-&gt;caps_enabled)</div><div class='add'>+	if (oct-&gt;conf-&gt;fw_info.rx_ol_flags)</div><div class='ctx'> 		oq-&gt;max_single_buffer_size -= OCTEP_OQ_RESP_HW_EXT_SIZE;</div><div class='ctx'> </div><div class='ctx'> 	oq-&gt;refill_threshold = CFG_GET_OQ_REFILL_THRESHOLD(oct-&gt;conf);</div><div class='hunk'>@@ -353,11 +353,13 @@ static int __octep_oq_process_rx(struct octep_device *oct,</div><div class='ctx'> 				 struct octep_oq *oq, u16 pkts_to_process)</div><div class='ctx'> {</div><div class='ctx'> 	struct octep_oq_resp_hw_ext *resp_hw_ext = NULL;</div><div class='add'>+	netdev_features_t feat = oq-&gt;netdev-&gt;features;</div><div class='ctx'> 	struct octep_rx_buffer *buff_info;</div><div class='ctx'> 	struct octep_oq_resp_hw *resp_hw;</div><div class='ctx'> 	u32 pkt, rx_bytes, desc_used;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	u16 data_offset;</div><div class='add'>+	u16 rx_ol_flags;</div><div class='ctx'> 	u32 read_idx;</div><div class='ctx'> </div><div class='ctx'> 	read_idx = oq-&gt;host_read_idx;</div><div class='hunk'>@@ -372,7 +374,7 @@ static int __octep_oq_process_rx(struct octep_device *oct,</div><div class='ctx'> </div><div class='ctx'> 		/* Swap the length field that is in Big-Endian to CPU */</div><div class='ctx'> 		buff_info-&gt;len = be64_to_cpu(resp_hw-&gt;length);</div><div class='del'>-		if (oct-&gt;caps_enabled &amp; OCTEP_CAP_RX_CHECKSUM) {</div><div class='add'>+		if (oct-&gt;conf-&gt;fw_info.rx_ol_flags) {</div><div class='ctx'> 			/* Extended response header is immediately after</div><div class='ctx'> 			 * response header (resp_hw)</div><div class='ctx'> 			 */</div><div class='hunk'>@@ -384,11 +386,13 @@ static int __octep_oq_process_rx(struct octep_device *oct,</div><div class='ctx'> 			 */</div><div class='ctx'> 			data_offset = OCTEP_OQ_RESP_HW_SIZE +</div><div class='ctx'> 				      OCTEP_OQ_RESP_HW_EXT_SIZE;</div><div class='add'>+			rx_ol_flags = resp_hw_ext-&gt;rx_ol_flags;</div><div class='ctx'> 		} else {</div><div class='ctx'> 			/* Data is immediately after</div><div class='ctx'> 			 * Hardware Rx response header.</div><div class='ctx'> 			 */</div><div class='ctx'> 			data_offset = OCTEP_OQ_RESP_HW_SIZE;</div><div class='add'>+			rx_ol_flags = 0;</div><div class='ctx'> 		}</div><div class='ctx'> 		rx_bytes += buff_info-&gt;len;</div><div class='ctx'> </div><div class='hunk'>@@ -444,8 +448,8 @@ static int __octep_oq_process_rx(struct octep_device *oct,</div><div class='ctx'> </div><div class='ctx'> 		skb-&gt;dev = oq-&gt;netdev;</div><div class='ctx'> 		skb-&gt;protocol =  eth_type_trans(skb, skb-&gt;dev);</div><div class='del'>-		if (resp_hw_ext &amp;&amp;</div><div class='del'>-		    resp_hw_ext-&gt;csum_verified == OCTEP_CSUM_VERIFIED)</div><div class='add'>+		if (feat &amp; NETIF_F_RXCSUM &amp;&amp;</div><div class='add'>+		    OCTEP_RX_CSUM_VERIFIED(rx_ol_flags))</div><div class='ctx'> 			skb-&gt;ip_summed = CHECKSUM_UNNECESSARY;</div><div class='ctx'> 		else</div><div class='ctx'> 			skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.h b/drivers/net/ethernet/marvell/octeon_ep/octep_rx.h<br/>index 49feae80d7d2..3b08e2d560dc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_rx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_rx.h</a></div><div class='hunk'>@@ -20,13 +20,33 @@ struct octep_oq_desc_hw {</div><div class='ctx'> 	dma_addr_t buffer_ptr;</div><div class='ctx'> 	u64 info_ptr;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_oq_desc_hw) == 16);</div><div class='ctx'> </div><div class='ctx'> #define OCTEP_OQ_DESC_SIZE    (sizeof(struct octep_oq_desc_hw))</div><div class='ctx'> </div><div class='del'>-#define OCTEP_CSUM_L4_VERIFIED 0x1</div><div class='del'>-#define OCTEP_CSUM_IP_VERIFIED 0x2</div><div class='del'>-#define OCTEP_CSUM_VERIFIED (OCTEP_CSUM_L4_VERIFIED | OCTEP_CSUM_IP_VERIFIED)</div><div class='add'>+/* Rx offload flags */</div><div class='add'>+#define OCTEP_RX_OFFLOAD_VLAN_STRIP	BIT(0)</div><div class='add'>+#define OCTEP_RX_OFFLOAD_IPV4_CKSUM	BIT(1)</div><div class='add'>+#define OCTEP_RX_OFFLOAD_UDP_CKSUM	BIT(2)</div><div class='add'>+#define OCTEP_RX_OFFLOAD_TCP_CKSUM	BIT(3)</div><div class='add'>+</div><div class='add'>+#define OCTEP_RX_OFFLOAD_CKSUM		(OCTEP_RX_OFFLOAD_IPV4_CKSUM | \</div><div class='add'>+					 OCTEP_RX_OFFLOAD_UDP_CKSUM | \</div><div class='add'>+					 OCTEP_RX_OFFLOAD_TCP_CKSUM)</div><div class='add'>+</div><div class='add'>+#define OCTEP_RX_IP_CSUM(flags)		((flags) &amp; \</div><div class='add'>+					 (OCTEP_RX_OFFLOAD_IPV4_CKSUM | \</div><div class='add'>+					  OCTEP_RX_OFFLOAD_TCP_CKSUM | \</div><div class='add'>+					  OCTEP_RX_OFFLOAD_UDP_CKSUM))</div><div class='add'>+</div><div class='add'>+/* bit 0 is vlan strip */</div><div class='add'>+#define OCTEP_RX_CSUM_IP_VERIFIED	BIT(1)</div><div class='add'>+#define OCTEP_RX_CSUM_L4_VERIFIED	BIT(2)</div><div class='add'>+</div><div class='add'>+#define OCTEP_RX_CSUM_VERIFIED(flags)	((flags) &amp; \</div><div class='add'>+					 (OCTEP_RX_CSUM_L4_VERIFIED | \</div><div class='add'>+					  OCTEP_RX_CSUM_IP_VERIFIED))</div><div class='ctx'> </div><div class='ctx'> /* Extended Response Header in packet data received from Hardware.</div><div class='ctx'>  * Includes metadata like checksum status.</div><div class='hunk'>@@ -35,11 +55,12 @@ static_assert(sizeof(struct octep_oq_desc_hw) == 16);</div><div class='ctx'>  */</div><div class='ctx'> struct octep_oq_resp_hw_ext {</div><div class='ctx'> 	/* Reserved. */</div><div class='del'>-	u64 reserved:62;</div><div class='add'>+	u64 rsvd:48;</div><div class='ctx'> </div><div class='del'>-	/* checksum verified. */</div><div class='del'>-	u64 csum_verified:2;</div><div class='add'>+	/* offload flags */</div><div class='add'>+	u16 rx_ol_flags;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_oq_resp_hw_ext) == 8);</div><div class='ctx'> </div><div class='ctx'> #define  OCTEP_OQ_RESP_HW_EXT_SIZE   (sizeof(struct octep_oq_resp_hw_ext))</div><div class='hunk'>@@ -52,6 +73,7 @@ struct octep_oq_resp_hw {</div><div class='ctx'> 	/* The Length of the packet. */</div><div class='ctx'> 	__be64 length;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_oq_resp_hw) == 8);</div><div class='ctx'> </div><div class='ctx'> #define OCTEP_OQ_RESP_HW_SIZE   (sizeof(struct octep_oq_resp_hw))</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c<br/>index d0adb82d65c3..06851b78aa28 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@ static void octep_iq_reset_indices(struct octep_iq *iq)</div><div class='ctx'> 	iq-&gt;flush_index = 0;</div><div class='ctx'> 	iq-&gt;pkts_processed = 0;</div><div class='ctx'> 	iq-&gt;pkt_in_done = 0;</div><div class='del'>-	atomic_set(&amp;iq-&gt;instr_pending, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -82,7 +81,6 @@ int octep_iq_process_completions(struct octep_iq *iq, u16 budget)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	iq-&gt;pkts_processed += compl_pkts;</div><div class='del'>-	atomic_sub(compl_pkts, &amp;iq-&gt;instr_pending);</div><div class='ctx'> 	iq-&gt;stats.instr_completed += compl_pkts;</div><div class='ctx'> 	iq-&gt;stats.bytes_sent += compl_bytes;</div><div class='ctx'> 	iq-&gt;stats.sgentry_sent += compl_sg;</div><div class='hunk'>@@ -91,7 +89,7 @@ int octep_iq_process_completions(struct octep_iq *iq, u16 budget)</div><div class='ctx'> 	netdev_tx_completed_queue(iq-&gt;netdev_q, compl_pkts, compl_bytes);</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(__netif_subqueue_stopped(iq-&gt;netdev, iq-&gt;q_no)) &amp;&amp;</div><div class='del'>-	    ((iq-&gt;max_count - atomic_read(&amp;iq-&gt;instr_pending)) &gt;</div><div class='add'>+	    (IQ_INSTR_SPACE(iq) &gt;</div><div class='ctx'> 	     OCTEP_WAKE_QUEUE_THRESHOLD))</div><div class='ctx'> 		netif_wake_subqueue(iq-&gt;netdev, iq-&gt;q_no);</div><div class='ctx'> 	return !budget;</div><div class='hunk'>@@ -144,7 +142,6 @@ static void octep_iq_free_pending(struct octep_iq *iq)</div><div class='ctx'> 		dev_kfree_skb_any(skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	atomic_set(&amp;iq-&gt;instr_pending, 0);</div><div class='ctx'> 	iq-&gt;flush_index = fi;</div><div class='ctx'> 	netdev_tx_reset_queue(netdev_get_tx_queue(iq-&gt;netdev, iq-&gt;q_no));</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_tx.h b/drivers/net/ethernet/marvell/octeon_ep/octep_tx.h<br/>index 86c98b13fc44..875a2c34091f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_tx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeon_ep/octep_tx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeon_ep/octep_tx.h</a></div><div class='hunk'>@@ -36,6 +36,7 @@ struct octep_tx_sglist_desc {</div><div class='ctx'> 	u16 len[4];</div><div class='ctx'> 	dma_addr_t dma_ptr[4];</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_tx_sglist_desc) == 40);</div><div class='ctx'> </div><div class='ctx'> /* Each Scatter/Gather entry sent to hardwar hold four pointers.</div><div class='hunk'>@@ -60,6 +61,18 @@ struct octep_tx_buffer {</div><div class='ctx'> </div><div class='ctx'> /* Hardware interface Tx statistics */</div><div class='ctx'> struct octep_iface_tx_stats {</div><div class='add'>+	/* Total frames sent on the interface */</div><div class='add'>+	u64 pkts;</div><div class='add'>+</div><div class='add'>+	/* Total octets sent on the interface */</div><div class='add'>+	u64 octs;</div><div class='add'>+</div><div class='add'>+	/* Packets sent to a broadcast DMAC */</div><div class='add'>+	u64 bcst;</div><div class='add'>+</div><div class='add'>+	/* Packets sent to the multicast DMAC */</div><div class='add'>+	u64 mcst;</div><div class='add'>+</div><div class='ctx'> 	/* Packets dropped due to excessive collisions */</div><div class='ctx'> 	u64 xscol;</div><div class='ctx'> </div><div class='hunk'>@@ -76,12 +89,6 @@ struct octep_iface_tx_stats {</div><div class='ctx'> 	 */</div><div class='ctx'> 	u64 scol;</div><div class='ctx'> </div><div class='del'>-	/* Total octets sent on the interface */</div><div class='del'>-	u64 octs;</div><div class='del'>-</div><div class='del'>-	/* Total frames sent on the interface */</div><div class='del'>-	u64 pkts;</div><div class='del'>-</div><div class='ctx'> 	/* Packets sent with an octet count &lt; 64 */</div><div class='ctx'> 	u64 hist_lt64;</div><div class='ctx'> </div><div class='hunk'>@@ -106,12 +113,6 @@ struct octep_iface_tx_stats {</div><div class='ctx'> 	/* Packets sent with an octet count of &gt; 1518 */</div><div class='ctx'> 	u64 hist_gt1518;</div><div class='ctx'> </div><div class='del'>-	/* Packets sent to a broadcast DMAC */</div><div class='del'>-	u64 bcst;</div><div class='del'>-</div><div class='del'>-	/* Packets sent to the multicast DMAC */</div><div class='del'>-	u64 mcst;</div><div class='del'>-</div><div class='ctx'> 	/* Packets sent that experienced a transmit underflow and were</div><div class='ctx'> 	 * truncated</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -172,9 +173,6 @@ struct octep_iq {</div><div class='ctx'> 	/* Statistics for this input queue. */</div><div class='ctx'> 	struct octep_iq_stats stats;</div><div class='ctx'> </div><div class='del'>-	/* This field keeps track of the instructions pending in this queue. */</div><div class='del'>-	atomic_t instr_pending;</div><div class='del'>-</div><div class='ctx'> 	/* Pointer to the Virtual Base addr of the input ring. */</div><div class='ctx'> 	struct octep_tx_desc_hw *desc_ring;</div><div class='ctx'> </div><div class='hunk'>@@ -240,32 +238,53 @@ struct octep_instr_hdr {</div><div class='ctx'> 	/* Reserved3 */</div><div class='ctx'> 	u64 reserved3:1;</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_instr_hdr) == 8);</div><div class='ctx'> </div><div class='del'>-/* Hardware Tx completion response header */</div><div class='del'>-struct octep_instr_resp_hdr {</div><div class='del'>-	/* Request ID  */</div><div class='del'>-	u64 rid:16;</div><div class='add'>+/* Tx offload flags */</div><div class='add'>+#define OCTEP_TX_OFFLOAD_VLAN_INSERT   BIT(0)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_IPV4_CKSUM    BIT(1)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_UDP_CKSUM     BIT(2)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_TCP_CKSUM     BIT(3)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_SCTP_CKSUM    BIT(4)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_TCP_TSO       BIT(5)</div><div class='add'>+#define OCTEP_TX_OFFLOAD_UDP_TSO       BIT(6)</div><div class='add'>+</div><div class='add'>+#define OCTEP_TX_OFFLOAD_CKSUM         (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \</div><div class='add'>+					OCTEP_TX_OFFLOAD_UDP_CKSUM | \</div><div class='add'>+					OCTEP_TX_OFFLOAD_TCP_CKSUM)</div><div class='add'>+</div><div class='add'>+#define OCTEP_TX_OFFLOAD_TSO           (OCTEP_TX_OFFLOAD_TCP_TSO | \</div><div class='add'>+					OCTEP_TX_OFFLOAD_UDP_TSO)</div><div class='add'>+</div><div class='add'>+#define OCTEP_TX_IP_CSUM(flags)		((flags) &amp; \</div><div class='add'>+					 (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \</div><div class='add'>+					  OCTEP_TX_OFFLOAD_TCP_CKSUM | \</div><div class='add'>+					  OCTEP_TX_OFFLOAD_UDP_CKSUM))</div><div class='ctx'> </div><div class='del'>-	/* PCIe port to use for response */</div><div class='del'>-	u64 pcie_port:3;</div><div class='add'>+#define OCTEP_TX_TSO(flags)		((flags) &amp; \</div><div class='add'>+					 (OCTEP_TX_OFFLOAD_TCP_TSO | \</div><div class='add'>+					  OCTEP_TX_OFFLOAD_UDP_TSO))</div><div class='ctx'> </div><div class='del'>-	/* Scatter indicator  1=scatter */</div><div class='del'>-	u64 scatter:1;</div><div class='add'>+struct tx_mdata {</div><div class='ctx'> </div><div class='del'>-	/* Size of Expected result OR no. of entries in scatter list */</div><div class='del'>-	u64 rlenssz:14;</div><div class='add'>+	/* offload flags */</div><div class='add'>+	u16 ol_flags;</div><div class='ctx'> </div><div class='del'>-	/* Desired destination port for result */</div><div class='del'>-	u64 dport:6;</div><div class='add'>+	/* gso size */</div><div class='add'>+	u16 gso_size;</div><div class='ctx'> </div><div class='del'>-	/* Opcode Specific parameters */</div><div class='del'>-	u64 param:8;</div><div class='add'>+	/* gso flags */</div><div class='add'>+	u16 gso_segs;</div><div class='ctx'> </div><div class='del'>-	/* Opcode for the return packet  */</div><div class='del'>-	u64 opcode:16;</div><div class='add'>+	/* reserved */</div><div class='add'>+	u16 rsvd1;</div><div class='add'>+</div><div class='add'>+	/* reserved */</div><div class='add'>+	u64 rsvd2;</div><div class='ctx'> };</div><div class='del'>-static_assert(sizeof(struct octep_instr_hdr) == 8);</div><div class='add'>+</div><div class='add'>+static_assert(sizeof(struct tx_mdata) == 16);</div><div class='ctx'> </div><div class='ctx'> /* 64-byte Tx instruction format.</div><div class='ctx'>  * Format of instruction for a 64-byte mode input queue.</div><div class='hunk'>@@ -284,18 +303,14 @@ struct octep_tx_desc_hw {</div><div class='ctx'> 		struct octep_instr_hdr ih;</div><div class='ctx'> 		u64 ih64;</div><div class='ctx'> 	};</div><div class='del'>-</div><div class='del'>-	/* Pointer where the response for a RAW mode packet will be written</div><div class='del'>-	 * by Octeon.</div><div class='del'>-	 */</div><div class='del'>-	u64 rptr;</div><div class='del'>-</div><div class='del'>-	/* Input Instruction Response Header. */</div><div class='del'>-	struct octep_instr_resp_hdr irh;</div><div class='del'>-</div><div class='add'>+	union  {</div><div class='add'>+		u64 txm64[2];</div><div class='add'>+		struct tx_mdata txm;</div><div class='add'>+	};</div><div class='ctx'> 	/* Additional headers available in a 64-byte instruction. */</div><div class='del'>-	u64 exhdr[4];</div><div class='add'>+	u64 exthdr[4];</div><div class='ctx'> };</div><div class='add'>+</div><div class='ctx'> static_assert(sizeof(struct octep_tx_desc_hw) == 64);</div><div class='ctx'> </div><div class='ctx'> #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h<br/>index 6845556581c3..edeb0f737312 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mbox.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/mbox.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mbox.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mbox.h</a></div><div class='hunk'>@@ -304,6 +304,13 @@ M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,		\</div><div class='ctx'> 				nix_bandprof_get_hwinfo_rsp)		    \</div><div class='ctx'> M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg,		\</div><div class='ctx'> 				msg_req, nix_inline_ipsec_cfg)		\</div><div class='add'>+M(NIX_MCAST_GRP_CREATE,	0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req,	\</div><div class='add'>+				nix_mcast_grp_create_rsp)			\</div><div class='add'>+M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req,	\</div><div class='add'>+				msg_rsp)					\</div><div class='add'>+M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update,				\</div><div class='add'>+				nix_mcast_grp_update_req,			\</div><div class='add'>+				nix_mcast_grp_update_rsp)			\</div><div class='ctx'> /* MCS mbox IDs (range 0xA000 - 0xBFFF) */					\</div><div class='ctx'> M(MCS_ALLOC_RESOURCES,	0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,	\</div><div class='ctx'> 				mcs_alloc_rsrc_rsp)				\</div><div class='hunk'>@@ -830,6 +837,9 @@ enum nix_af_status {</div><div class='ctx'> 	NIX_AF_ERR_CQ_CTX_WRITE_ERR  = -429,</div><div class='ctx'> 	NIX_AF_ERR_AQ_CTX_RETRY_WRITE  = -430,</div><div class='ctx'> 	NIX_AF_ERR_LINK_CREDITS  = -431,</div><div class='add'>+	NIX_AF_ERR_INVALID_MCAST_GRP	= -436,</div><div class='add'>+	NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,</div><div class='add'>+	NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* For NIX RX vtag action  */</div><div class='hunk'>@@ -1204,6 +1214,68 @@ struct nix_bp_cfg_rsp {</div><div class='ctx'> 	u8	chan_cnt; /* Number of channel for which bpids are assigned */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct nix_mcast_grp_create_req {</div><div class='add'>+	struct mbox_msghdr hdr;</div><div class='add'>+#define NIX_MCAST_INGRESS	0</div><div class='add'>+#define NIX_MCAST_EGRESS	1</div><div class='add'>+	u8 dir;</div><div class='add'>+	u8 reserved[11];</div><div class='add'>+	/* Reserving few bytes for future requirement */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nix_mcast_grp_create_rsp {</div><div class='add'>+	struct mbox_msghdr hdr;</div><div class='add'>+	/* This mcast_grp_idx should be passed during MCAM</div><div class='add'>+	 * write entry for multicast. AF will identify the</div><div class='add'>+	 * corresponding multicast table index associated</div><div class='add'>+	 * with the group id and program the same to MCAM entry.</div><div class='add'>+	 * This group id is also needed during group delete</div><div class='add'>+	 * and update request.</div><div class='add'>+	 */</div><div class='add'>+	u32 mcast_grp_idx;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nix_mcast_grp_destroy_req {</div><div class='add'>+	struct mbox_msghdr hdr;</div><div class='add'>+	/* Group id returned by nix_mcast_grp_create_rsp */</div><div class='add'>+	u32 mcast_grp_idx;</div><div class='add'>+	/* If AF is requesting for destroy, then set</div><div class='add'>+	 * it to '1'. Otherwise keep it to '0'</div><div class='add'>+	 */</div><div class='add'>+	u8 is_af;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nix_mcast_grp_update_req {</div><div class='add'>+	struct mbox_msghdr hdr;</div><div class='add'>+	/* Group id returned by nix_mcast_grp_create_rsp */</div><div class='add'>+	u32 mcast_grp_idx;</div><div class='add'>+	/* Number of multicast/mirror entries requested */</div><div class='add'>+	u32 num_mce_entry;</div><div class='add'>+#define NIX_MCE_ENTRY_MAX 64</div><div class='add'>+#define NIX_RX_RQ	0</div><div class='add'>+#define NIX_RX_RSS	1</div><div class='add'>+	/* Receive queue or RSS index within pf_func */</div><div class='add'>+	u32 rq_rss_index[NIX_MCE_ENTRY_MAX];</div><div class='add'>+	/* pcifunc is required for both ingress and egress multicast */</div><div class='add'>+	u16 pcifunc[NIX_MCE_ENTRY_MAX];</div><div class='add'>+	/* channel is required for egress multicast */</div><div class='add'>+	u16 channel[NIX_MCE_ENTRY_MAX];</div><div class='add'>+#define NIX_MCAST_OP_ADD_ENTRY	0</div><div class='add'>+#define NIX_MCAST_OP_DEL_ENTRY	1</div><div class='add'>+	/* Destination type. 0:Receive queue, 1:RSS*/</div><div class='add'>+	u8 dest_type[NIX_MCE_ENTRY_MAX];</div><div class='add'>+	u8 op;</div><div class='add'>+	/* If AF is requesting for update, then set</div><div class='add'>+	 * it to '1'. Otherwise keep it to '0'</div><div class='add'>+	 */</div><div class='add'>+	u8 is_af;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nix_mcast_grp_update_rsp {</div><div class='add'>+	struct mbox_msghdr hdr;</div><div class='add'>+	u32 mce_start_index;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Global NIX inline IPSec configuration */</div><div class='ctx'> struct nix_inline_ipsec_cfg {</div><div class='ctx'> 	struct mbox_msghdr hdr;</div><div class='hunk'>@@ -1479,6 +1551,8 @@ struct flow_msg {</div><div class='ctx'> #define OTX2_FLOWER_MASK_MPLS_TTL		GENMASK(7, 0)</div><div class='ctx'> #define OTX2_FLOWER_MASK_MPLS_NON_TTL		GENMASK(31, 8)</div><div class='ctx'> 	u32 mpls_lse[4];</div><div class='add'>+	u8 icmp_type;</div><div class='add'>+	u8 icmp_code;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct npc_install_flow_req {</div><div class='hunk'>@@ -1945,7 +2019,7 @@ struct mcs_hw_info {</div><div class='ctx'> 	u8 tcam_entries;	/* RX/TX Tcam entries per mcs block */</div><div class='ctx'> 	u8 secy_entries;	/* RX/TX SECY entries per mcs block */</div><div class='ctx'> 	u8 sc_entries;		/* RX/TX SC CAM entries per mcs block */</div><div class='del'>-	u8 sa_entries;		/* PN table entries = SA entries */</div><div class='add'>+	u16 sa_entries;		/* PN table entries = SA entries */</div><div class='ctx'> 	u64 rsvd[16];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c<br/>index c43f19dfbd74..c1775bd01c2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/mcs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs.c</a></div><div class='hunk'>@@ -117,7 +117,7 @@ void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id</div><div class='ctx'> 	reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(id);</div><div class='ctx'> 	stats-&gt;pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg);</div><div class='ctx'> </div><div class='del'>-	reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(id);</div><div class='add'>+	reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(id);</div><div class='ctx'> 	stats-&gt;pkt_untaged_cnt = mcs_reg_read(mcs, reg);</div><div class='ctx'> </div><div class='ctx'> 	reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(id);</div><div class='hunk'>@@ -215,7 +215,7 @@ void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats,</div><div class='ctx'> 		reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(id);</div><div class='ctx'> 		stats-&gt;pkt_notvalid_cnt = mcs_reg_read(mcs, reg);</div><div class='ctx'> </div><div class='del'>-		reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(id);</div><div class='add'>+		reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(id);</div><div class='ctx'> 		stats-&gt;pkt_unchecked_cnt = mcs_reg_read(mcs, reg);</div><div class='ctx'> </div><div class='ctx'> 		if (mcs-&gt;hw-&gt;mcs_blks &gt; 1) {</div><div class='hunk'>@@ -1219,6 +1219,17 @@ struct mcs *mcs_get_pdata(int mcs_id)</div><div class='ctx'> 	return NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool is_mcs_bypass(int mcs_id)</div><div class='add'>+{</div><div class='add'>+	struct mcs *mcs_dev;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(mcs_dev, &amp;mcs_list, mcs_list) {</div><div class='add'>+		if (mcs_dev-&gt;mcs_id == mcs_id)</div><div class='add'>+			return mcs_dev-&gt;bypass;</div><div class='add'>+	}</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req)</div><div class='ctx'> {</div><div class='ctx'> 	u64 val = 0;</div><div class='hunk'>@@ -1436,7 +1447,7 @@ static int mcs_x2p_calibration(struct mcs *mcs)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mcs_set_external_bypass(struct mcs *mcs, u8 bypass)</div><div class='add'>+static void mcs_set_external_bypass(struct mcs *mcs, bool bypass)</div><div class='ctx'> {</div><div class='ctx'> 	u64 val;</div><div class='ctx'> </div><div class='hunk'>@@ -1447,6 +1458,7 @@ static void mcs_set_external_bypass(struct mcs *mcs, u8 bypass)</div><div class='ctx'> 	else</div><div class='ctx'> 		val &amp;= ~BIT_ULL(6);</div><div class='ctx'> 	mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);</div><div class='add'>+	mcs-&gt;bypass = bypass;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mcs_global_cfg(struct mcs *mcs)</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.h b/drivers/net/ethernet/marvell/octeontx2/af/mcs.h<br/>index 0f89dcb76465..f927cc61dfd2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/mcs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs.h</a></div><div class='hunk'>@@ -149,6 +149,7 @@ struct mcs {</div><div class='ctx'> 	u16			num_vec;</div><div class='ctx'> 	void			*rvu;</div><div class='ctx'> 	u16			*tx_sa_active;</div><div class='add'>+	bool                      bypass;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mcs_ops {</div><div class='hunk'>@@ -206,6 +207,7 @@ void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *</div><div class='ctx'> int mcs_alloc_ctrlpktrule(struct rsrc_bmap *rsrc, u16 *pf_map, u16 offset, u16 pcifunc);</div><div class='ctx'> int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req);</div><div class='ctx'> int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req);</div><div class='add'>+bool is_mcs_bypass(int mcs_id);</div><div class='ctx'> </div><div class='ctx'> /* CN10K-B APIs */</div><div class='ctx'> void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs);</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h<br/>index f3ab01fc363c..f4c6de89002c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h</a></div><div class='hunk'>@@ -810,14 +810,37 @@</div><div class='ctx'> 		offset = 0x9d8ull;			\</div><div class='ctx'> 	offset; })</div><div class='ctx'> </div><div class='add'>+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(a) ({	\</div><div class='add'>+	u64 offset;					\</div><div class='add'>+							\</div><div class='add'>+	offset = 0xee80ull;				\</div><div class='add'>+	if (mcs-&gt;hw-&gt;mcs_blks &gt; 1)			\</div><div class='add'>+		offset = 0xe818ull;			\</div><div class='add'>+	offset += (a) * 0x8ull;				\</div><div class='add'>+	offset; })</div><div class='add'>+</div><div class='add'>+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) ({	\</div><div class='add'>+	u64 offset;					\</div><div class='add'>+							\</div><div class='add'>+	offset = 0xa680ull;				\</div><div class='add'>+	if (mcs-&gt;hw-&gt;mcs_blks &gt; 1)			\</div><div class='add'>+		offset = 0xd018ull;			\</div><div class='add'>+	offset += (a) * 0x8ull;				\</div><div class='add'>+	offset; })</div><div class='add'>+</div><div class='add'>+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a)	({	\</div><div class='add'>+	u64 offset;						\</div><div class='add'>+								\</div><div class='add'>+	offset = 0xf680ull;					\</div><div class='add'>+	if (mcs-&gt;hw-&gt;mcs_blks &gt; 1)				\</div><div class='add'>+		offset = 0xe018ull;				\</div><div class='add'>+	offset += (a) * 0x8ull;					\</div><div class='add'>+	offset; })</div><div class='add'>+</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a)	(0xe680ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a)	(0xde80ull + (a) * 0x8ull)</div><div class='del'>-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(a)	(0xa680ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a)	(0xd218 + (a) * 0x8ull)</div><div class='del'>-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a)	(0xd018ull + (a) * 0x8ull)</div><div class='del'>-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(a)	(0xee80ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a)		(0xb680ull + (a) * 0x8ull)</div><div class='del'>-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) (0xf680ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a)	(0x12680ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a) * 0x8ull)</div><div class='ctx'> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a)	(0x13680ull + (a) * 0x8ull)</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/npc.h<br/>index ab3e39eef2eb..b0b4dea548e1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/npc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/npc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/npc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/npc.h</a></div><div class='hunk'>@@ -214,6 +214,8 @@ enum key_fields {</div><div class='ctx'> 	NPC_MPLS3_TTL,</div><div class='ctx'> 	NPC_MPLS4_LBTCBOS,</div><div class='ctx'> 	NPC_MPLS4_TTL,</div><div class='add'>+	NPC_TYPE_ICMP,</div><div class='add'>+	NPC_CODE_ICMP,</div><div class='ctx'> 	NPC_HEADER_FIELDS_MAX,</div><div class='ctx'> 	NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */</div><div class='ctx'> 	NPC_PF_FUNC, /* Valid when Tx */</div><div class='hunk'>@@ -528,7 +530,7 @@ struct npc_lt_def {</div><div class='ctx'> 	u8	ltype_mask;</div><div class='ctx'> 	u8	ltype_match;</div><div class='ctx'> 	u8	lid;</div><div class='del'>-};</div><div class='add'>+} __packed;</div><div class='ctx'> </div><div class='ctx'> struct npc_lt_def_ipsec {</div><div class='ctx'> 	u8	ltype_mask;</div><div class='hunk'>@@ -536,7 +538,7 @@ struct npc_lt_def_ipsec {</div><div class='ctx'> 	u8	lid;</div><div class='ctx'> 	u8	spi_offset;</div><div class='ctx'> 	u8	spi_nz;</div><div class='del'>-};</div><div class='add'>+} __packed;</div><div class='ctx'> </div><div class='ctx'> struct npc_lt_def_apad {</div><div class='ctx'> 	u8	ltype_mask;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c<br/>index af21e2030cff..76218f1cb459 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rpm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rpm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rpm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rpm.c</a></div><div class='hunk'>@@ -373,6 +373,11 @@ void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)</div><div class='ctx'> 	cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;</div><div class='ctx'> 	rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);</div><div class='ctx'> </div><div class='add'>+	/* Disable forward pause to driver */</div><div class='add'>+	cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);</div><div class='add'>+	cfg &amp;= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD;</div><div class='add'>+	rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);</div><div class='add'>+</div><div class='ctx'> 	/* Enable channel mask for all LMACS */</div><div class='ctx'> 	if (is_dev_rpm2(rpm))</div><div class='ctx'> 		rpm_write(rpm, lmac_id, RPM2_CMR_CHAN_MSK_OR, 0xffff);</div><div class='hunk'>@@ -501,6 +506,7 @@ u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id)</div><div class='ctx'> 	rpm_t *rpm = rpmd;</div><div class='ctx'> 	u8 num_lmacs;</div><div class='ctx'> 	u32 fifo_len;</div><div class='add'>+	u16 max_lmac;</div><div class='ctx'> </div><div class='ctx'> 	lmac_info = rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS);</div><div class='ctx'> 	/* LMACs are divided into two groups and each group</div><div class='hunk'>@@ -508,7 +514,11 @@ u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id)</div><div class='ctx'> 	 * Group0 lmac_id range {0..3}</div><div class='ctx'> 	 * Group1 lmac_id range {4..7}</div><div class='ctx'> 	 */</div><div class='del'>-	fifo_len = rpm-&gt;mac_ops-&gt;fifo_len / 2;</div><div class='add'>+	max_lmac = (rpm_read(rpm, 0, CGX_CONST) &gt;&gt; 24) &amp; 0xFF;</div><div class='add'>+	if (max_lmac &gt; 4)</div><div class='add'>+		fifo_len = rpm-&gt;mac_ops-&gt;fifo_len / 2;</div><div class='add'>+	else</div><div class='add'>+		fifo_len = rpm-&gt;mac_ops-&gt;fifo_len;</div><div class='ctx'> </div><div class='ctx'> 	if (lmac_id &lt; 4) {</div><div class='ctx'> 		num_lmacs = hweight8(lmac_info &amp; 0xF);</div><div class='hunk'>@@ -616,12 +626,10 @@ int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 p</div><div class='ctx'> </div><div class='ctx'> 	if (rx_pause) {</div><div class='ctx'> 		cfg &amp;= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |</div><div class='del'>-				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |</div><div class='del'>-				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);</div><div class='add'>+			 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE |</div><div class='del'>-				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE |</div><div class='del'>-				RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD);</div><div class='add'>+			RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (tx_pause) {</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c<br/>index 22c395c7d040..5c1d04a3c559 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu.c</a></div><div class='hunk'>@@ -156,7 +156,7 @@ int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)</div><div class='ctx'> 	return start;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)</div><div class='add'>+void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)</div><div class='ctx'> {</div><div class='ctx'> 	if (!rsrc-&gt;bmap)</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -935,6 +935,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu)</div><div class='ctx'> 	hw-&gt;total_vfs = (cfg &gt;&gt; 20) &amp; 0xFFF;</div><div class='ctx'> 	hw-&gt;max_vfs_per_pf = (cfg &gt;&gt; 40) &amp; 0xFF;</div><div class='ctx'> </div><div class='add'>+	if (!is_rvu_otx2(rvu))</div><div class='add'>+		rvu_apr_block_cn10k_init(rvu);</div><div class='add'>+</div><div class='ctx'> 	/* Init NPA LF's bitmap */</div><div class='ctx'> 	block = &amp;hw-&gt;block[BLKADDR_NPA];</div><div class='ctx'> 	if (!block-&gt;implemented)</div><div class='hunk'>@@ -2614,6 +2617,10 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)</div><div class='ctx'> 	 * 2. Flush and reset SSO/SSOW</div><div class='ctx'> 	 * 3. Cleanup pools (NPA)</div><div class='ctx'> 	 */</div><div class='add'>+</div><div class='add'>+	/* Free multicast/mirror node associated with the 'pcifunc' */</div><div class='add'>+	rvu_nix_mcast_flr_free_entries(rvu, pcifunc);</div><div class='add'>+</div><div class='ctx'> 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);</div><div class='ctx'> 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);</div><div class='ctx'> 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);</div><div class='hunk'>@@ -2631,6 +2638,9 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)</div><div class='ctx'> 	rvu_npc_free_mcam_entries(rvu, pcifunc, -1);</div><div class='ctx'> 	rvu_mac_reset(rvu, pcifunc);</div><div class='ctx'> </div><div class='add'>+	if (rvu-&gt;mcs_blk_cnt)</div><div class='add'>+		rvu_mcs_flr_handler(rvu, pcifunc);</div><div class='add'>+</div><div class='ctx'> 	mutex_unlock(&amp;rvu-&gt;flr_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h<br/>index c4d999ef5ab4..43be37dd1f32 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu.h</a></div><div class='hunk'>@@ -116,11 +116,12 @@ struct rvu_block {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct nix_mcast {</div><div class='del'>-	struct qmem	*mce_ctx;</div><div class='del'>-	struct qmem	*mcast_buf;</div><div class='del'>-	int		replay_pkind;</div><div class='del'>-	int		next_free_mce;</div><div class='del'>-	struct mutex	mce_lock; /* Serialize MCE updates */</div><div class='add'>+	struct qmem		*mce_ctx;</div><div class='add'>+	struct qmem		*mcast_buf;</div><div class='add'>+	int			replay_pkind;</div><div class='add'>+	struct rsrc_bmap	mce_counter[2];</div><div class='add'>+	/* Counters for both ingress and egress mcast lists */</div><div class='add'>+	struct mutex		mce_lock; /* Serialize MCE updates */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct nix_mce_list {</div><div class='hunk'>@@ -129,6 +130,23 @@ struct nix_mce_list {</div><div class='ctx'> 	int			max;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct nix_mcast_grp_elem {</div><div class='add'>+	struct nix_mce_list	mcast_mce_list;</div><div class='add'>+	u32			mcast_grp_idx;</div><div class='add'>+	u32			pcifunc;</div><div class='add'>+	int			mcam_index;</div><div class='add'>+	int			mce_start_index;</div><div class='add'>+	struct list_head	list;</div><div class='add'>+	u8			dir;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nix_mcast_grp {</div><div class='add'>+	struct list_head	mcast_grp_head;</div><div class='add'>+	int			count;</div><div class='add'>+	int			next_grp_index;</div><div class='add'>+	struct mutex		mcast_grp_lock; /* Serialize MCE updates */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* layer metadata to uniquely identify a packet header field */</div><div class='ctx'> struct npc_layer_mdata {</div><div class='ctx'> 	u8 lid;</div><div class='hunk'>@@ -339,12 +357,14 @@ struct nix_hw {</div><div class='ctx'> 	struct rvu *rvu;</div><div class='ctx'> 	struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */</div><div class='ctx'> 	struct nix_mcast mcast;</div><div class='add'>+	struct nix_mcast_grp mcast_grp;</div><div class='ctx'> 	struct nix_flowkey flowkey;</div><div class='ctx'> 	struct nix_mark_format mark_format;</div><div class='ctx'> 	struct nix_lso lso;</div><div class='ctx'> 	struct nix_txvlan txvlan;</div><div class='ctx'> 	struct nix_ipolicer *ipolicer;</div><div class='ctx'> 	u64    *tx_credits;</div><div class='add'>+	u8	cc_mcs_cnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* RVU block's capabilities or functionality,</div><div class='hunk'>@@ -741,6 +761,7 @@ void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);</div><div class='ctx'> bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);</div><div class='ctx'> int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);</div><div class='ctx'> int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);</div><div class='add'>+void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start);</div><div class='ctx'> bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);</div><div class='ctx'> u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);</div><div class='ctx'> int rvu_get_pf(u16 pcifunc);</div><div class='hunk'>@@ -847,6 +868,11 @@ u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);</div><div class='ctx'> u32 convert_bytes_to_dwrr_mtu(u32 bytes);</div><div class='ctx'> void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,</div><div class='ctx'> 			struct nix_txsch *txsch, bool enable);</div><div class='add'>+void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc);</div><div class='add'>+int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,</div><div class='add'>+				u32 mcast_grp_idx);</div><div class='add'>+int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,</div><div class='add'>+				    u32 mcast_grp_idx, u16 mcam_index);</div><div class='ctx'> </div><div class='ctx'> /* NPC APIs */</div><div class='ctx'> void rvu_npc_freemem(struct rvu *rvu);</div><div class='hunk'>@@ -895,6 +921,10 @@ void npc_mcam_enable_flows(struct rvu *rvu, u16 target);</div><div class='ctx'> void npc_mcam_disable_flows(struct rvu *rvu, u16 target);</div><div class='ctx'> void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 			   int blkaddr, int index, bool enable);</div><div class='add'>+u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='add'>+			int blkaddr, int index);</div><div class='add'>+void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='add'>+			 int blkaddr, int index, u64 cfg);</div><div class='ctx'> void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 			 int blkaddr, u16 src, struct mcam_entry *entry,</div><div class='ctx'> 			 u8 *intf, u8 *ena);</div><div class='hunk'>@@ -904,6 +934,7 @@ u32  rvu_cgx_get_fifolen(struct rvu *rvu);</div><div class='ctx'> void *rvu_first_cgx_pdata(struct rvu *rvu);</div><div class='ctx'> int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);</div><div class='ctx'> int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);</div><div class='add'>+int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);</div><div class='ctx'> int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,</div><div class='ctx'> 			       u16 pfc_en);</div><div class='ctx'> int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);</div><div class='hunk'>@@ -919,6 +950,8 @@ int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,</div><div class='ctx'> 			       u64 bcast_mcast_val, u64 bcast_mcast_mask);</div><div class='ctx'> void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);</div><div class='ctx'> bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);</div><div class='add'>+int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr);</div><div class='add'>+void npc_mcam_rsrcs_deinit(struct rvu *rvu);</div><div class='ctx'> </div><div class='ctx'> /* CPT APIs */</div><div class='ctx'> int rvu_cpt_register_interrupts(struct rvu *rvu);</div><div class='hunk'>@@ -940,6 +973,7 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);</div><div class='ctx'> </div><div class='ctx'> /* CN10K RVU - LMT*/</div><div class='ctx'> void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);</div><div class='add'>+void rvu_apr_block_cn10k_init(struct rvu *rvu);</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_DEBUG_FS</div><div class='ctx'> void rvu_dbg_init(struct rvu *rvu);</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c<br/>index 15a319684ed3..38acdc7a73bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c</a></div><div class='hunk'>@@ -465,6 +465,23 @@ int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)</div><div class='ctx'> 	return mac_ops-&gt;mac_rx_tx_enable(cgxd, lmac_id, start);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)</div><div class='add'>+{</div><div class='add'>+	int pf = rvu_get_pf(pcifunc);</div><div class='add'>+	struct mac_ops *mac_ops;</div><div class='add'>+	u8 cgx_id, lmac_id;</div><div class='add'>+	void *cgxd;</div><div class='add'>+</div><div class='add'>+	if (!is_cgx_config_permitted(rvu, pcifunc))</div><div class='add'>+		return LMAC_AF_ERR_PERM_DENIED;</div><div class='add'>+</div><div class='add'>+	rvu_get_cgx_lmac_id(rvu-&gt;pf2cgxlmac_map[pf], &amp;cgx_id, &amp;lmac_id);</div><div class='add'>+	cgxd = rvu_cgx_pdata(cgx_id, rvu);</div><div class='add'>+	mac_ops = get_mac_ops(cgxd);</div><div class='add'>+</div><div class='add'>+	return mac_ops-&gt;mac_tx_enable(cgxd, lmac_id, enable);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	struct mac_ops *mac_ops;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c<br/>index 0e74c5a2231e..7fa98aeb3663 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c</a></div><div class='hunk'>@@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> 	cfg |= BIT_ULL(1) | BIT_ULL(2);</div><div class='ctx'> 	rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+void rvu_apr_block_cn10k_init(struct rvu *rvu)</div><div class='add'>+{</div><div class='add'>+	u64 reg;</div><div class='add'>+</div><div class='add'>+	reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);</div><div class='add'>+	reg |=	FIELD_PREP(LMTST_THROTTLE_MASK, LMTST_WR_PEND_MAX);</div><div class='add'>+	rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c<br/>index bd817ee88735..e6d7914ce61c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c</a></div><div class='hunk'>@@ -1825,6 +1825,8 @@ static void print_nix_rq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)</div><div class='ctx'> static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)</div><div class='ctx'> {</div><div class='ctx'> 	struct nix_cq_ctx_s *cq_ctx = &amp;rsp-&gt;cq;</div><div class='add'>+	struct nix_hw *nix_hw = m-&gt;private;</div><div class='add'>+	struct rvu *rvu = nix_hw-&gt;rvu;</div><div class='ctx'> </div><div class='ctx'> 	seq_printf(m, "W0: base \t\t\t%llx\n\n", cq_ctx-&gt;base);</div><div class='ctx'> </div><div class='hunk'>@@ -1836,6 +1838,16 @@ static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)</div><div class='ctx'> 	seq_printf(m, "W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n\n",</div><div class='ctx'> 		   cq_ctx-&gt;bpid, cq_ctx-&gt;bp_ena);</div><div class='ctx'> </div><div class='add'>+	if (!is_rvu_otx2(rvu)) {</div><div class='add'>+		seq_printf(m, "W1: lbpid_high \t\t\t0x%03x\n", cq_ctx-&gt;lbpid_high);</div><div class='add'>+		seq_printf(m, "W1: lbpid_med \t\t\t0x%03x\n", cq_ctx-&gt;lbpid_med);</div><div class='add'>+		seq_printf(m, "W1: lbpid_low \t\t\t0x%03x\n", cq_ctx-&gt;lbpid_low);</div><div class='add'>+		seq_printf(m, "(W1: lbpid) \t\t\t0x%03x\n",</div><div class='add'>+			   cq_ctx-&gt;lbpid_high &lt;&lt; 6 | cq_ctx-&gt;lbpid_med &lt;&lt; 3 |</div><div class='add'>+			   cq_ctx-&gt;lbpid_low);</div><div class='add'>+		seq_printf(m, "W1: lbp_ena \t\t\t\t%d\n\n", cq_ctx-&gt;lbp_ena);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	seq_printf(m, "W2: update_time \t\t%d\nW2:avg_level \t\t\t%d\n",</div><div class='ctx'> 		   cq_ctx-&gt;update_time, cq_ctx-&gt;avg_level);</div><div class='ctx'> 	seq_printf(m, "W2: head \t\t\t%d\nW2:tail \t\t\t%d\n\n",</div><div class='hunk'>@@ -1847,6 +1859,11 @@ static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)</div><div class='ctx'> 		   cq_ctx-&gt;qsize, cq_ctx-&gt;caching);</div><div class='ctx'> 	seq_printf(m, "W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d\n",</div><div class='ctx'> 		   cq_ctx-&gt;substream, cq_ctx-&gt;ena);</div><div class='add'>+	if (!is_rvu_otx2(rvu)) {</div><div class='add'>+		seq_printf(m, "W3: lbp_frac \t\t\t%d\n", cq_ctx-&gt;lbp_frac);</div><div class='add'>+		seq_printf(m, "W3: cpt_drop_err_en \t\t\t%d\n",</div><div class='add'>+			   cq_ctx-&gt;cpt_drop_err_en);</div><div class='add'>+	}</div><div class='ctx'> 	seq_printf(m, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d\n",</div><div class='ctx'> 		   cq_ctx-&gt;drop_ena, cq_ctx-&gt;drop);</div><div class='ctx'> 	seq_printf(m, "W3: bp \t\t\t\t%d\n\n", cq_ctx-&gt;bp);</div><div class='hunk'>@@ -2889,6 +2906,14 @@ static void rvu_dbg_npc_mcam_show_flows(struct seq_file *s,</div><div class='ctx'> 			RVU_DBG_PRINT_MPLS_TTL(rule-&gt;packet.mpls_lse[3],</div><div class='ctx'> 					       rule-&gt;mask.mpls_lse[3]);</div><div class='ctx'> 			break;</div><div class='add'>+		case NPC_TYPE_ICMP:</div><div class='add'>+			seq_printf(s, "%d ", rule-&gt;packet.icmp_type);</div><div class='add'>+			seq_printf(s, "mask 0x%x\n", rule-&gt;mask.icmp_type);</div><div class='add'>+			break;</div><div class='add'>+		case NPC_CODE_ICMP:</div><div class='add'>+			seq_printf(s, "%d ", rule-&gt;packet.icmp_code);</div><div class='add'>+			seq_printf(s, "mask 0x%x\n", rule-&gt;mask.icmp_code);</div><div class='add'>+			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			seq_puts(s, "\n");</div><div class='ctx'> 			break;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c<br/>index c70932625d0d..1e6fbd98423d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c</a></div><div class='hunk'>@@ -5,7 +5,7 @@</div><div class='ctx'>  *</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='del'>-#include&lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "rvu.h"</div><div class='ctx'> #include "rvu_reg.h"</div><div class='hunk'>@@ -538,7 +538,7 @@ static int rvu_nix_register_reporters(struct rvu_devlink *rvu_dl)</div><div class='ctx'> </div><div class='ctx'> 	rvu_dl-&gt;devlink_wq = create_workqueue("rvu_devlink_wq");</div><div class='ctx'> 	if (!rvu_dl-&gt;devlink_wq)</div><div class='del'>-		goto err;</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;intr_work, rvu_nix_intr_work);</div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;gen_work, rvu_nix_gen_work);</div><div class='hunk'>@@ -546,9 +546,6 @@ static int rvu_nix_register_reporters(struct rvu_devlink *rvu_dl)</div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;ras_work, rvu_nix_ras_work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-err:</div><div class='del'>-	rvu_nix_health_reporters_destroy(rvu_dl);</div><div class='del'>-	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rvu_nix_health_reporters_create(struct rvu_devlink *rvu_dl)</div><div class='hunk'>@@ -1087,7 +1084,7 @@ static int rvu_npa_register_reporters(struct rvu_devlink *rvu_dl)</div><div class='ctx'> </div><div class='ctx'> 	rvu_dl-&gt;devlink_wq = create_workqueue("rvu_devlink_wq");</div><div class='ctx'> 	if (!rvu_dl-&gt;devlink_wq)</div><div class='del'>-		goto err;</div><div class='add'>+		return -ENOMEM;</div><div class='ctx'> </div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;intr_work, rvu_npa_intr_work);</div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;err_work, rvu_npa_err_work);</div><div class='hunk'>@@ -1095,9 +1092,6 @@ static int rvu_npa_register_reporters(struct rvu_devlink *rvu_dl)</div><div class='ctx'> 	INIT_WORK(&amp;rvu_reporters-&gt;ras_work, rvu_npa_ras_work);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-err:</div><div class='del'>-	rvu_npa_health_reporters_destroy(rvu_dl);</div><div class='del'>-	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rvu_npa_health_reporters_create(struct rvu_devlink *rvu_dl)</div><div class='hunk'>@@ -1243,6 +1237,7 @@ enum rvu_af_dl_param_id {</div><div class='ctx'> 	RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU,</div><div class='ctx'> 	RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE,</div><div class='ctx'> 	RVU_AF_DEVLINK_PARAM_ID_NPC_MCAM_ZONE_PERCENT,</div><div class='add'>+	RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int rvu_af_npc_exact_feature_get(struct devlink *devlink, u32 id,</div><div class='hunk'>@@ -1360,6 +1355,79 @@ static int rvu_af_dl_npc_mcam_high_zone_percent_validate(struct devlink *devlink</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int rvu_af_dl_nix_maxlf_get(struct devlink *devlink, u32 id,</div><div class='add'>+				   struct devlink_param_gset_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct rvu_devlink *rvu_dl = devlink_priv(devlink);</div><div class='add'>+	struct rvu *rvu = rvu_dl-&gt;rvu;</div><div class='add'>+</div><div class='add'>+	ctx-&gt;val.vu16 = (u16)rvu_get_nixlf_count(rvu);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rvu_af_dl_nix_maxlf_set(struct devlink *devlink, u32 id,</div><div class='add'>+				   struct devlink_param_gset_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	struct rvu_devlink *rvu_dl = devlink_priv(devlink);</div><div class='add'>+	struct rvu *rvu = rvu_dl-&gt;rvu;</div><div class='add'>+	struct rvu_block *block;</div><div class='add'>+	int blkaddr = 0;</div><div class='add'>+</div><div class='add'>+	npc_mcam_rsrcs_deinit(rvu);</div><div class='add'>+	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);</div><div class='add'>+	while (blkaddr) {</div><div class='add'>+		block = &amp;rvu-&gt;hw-&gt;block[blkaddr];</div><div class='add'>+		block-&gt;lf.max = ctx-&gt;val.vu16;</div><div class='add'>+		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);</div><div class='add'>+	npc_mcam_rsrcs_init(rvu, blkaddr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rvu_af_dl_nix_maxlf_validate(struct devlink *devlink, u32 id,</div><div class='add'>+					union devlink_param_value val,</div><div class='add'>+					struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct rvu_devlink *rvu_dl = devlink_priv(devlink);</div><div class='add'>+	struct rvu *rvu = rvu_dl-&gt;rvu;</div><div class='add'>+	u16 max_nix0_lf, max_nix1_lf;</div><div class='add'>+	struct npc_mcam *mcam;</div><div class='add'>+	u64 cfg;</div><div class='add'>+</div><div class='add'>+	cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2);</div><div class='add'>+	max_nix0_lf = cfg &amp; 0xFFF;</div><div class='add'>+	cfg = rvu_read64(rvu, BLKADDR_NIX1, NIX_AF_CONST2);</div><div class='add'>+	max_nix1_lf = cfg &amp; 0xFFF;</div><div class='add'>+</div><div class='add'>+	/* Do not allow user to modify maximum NIX LFs while mcam entries</div><div class='add'>+	 * have already been assigned.</div><div class='add'>+	 */</div><div class='add'>+	mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='add'>+	if (mcam-&gt;bmap_fcnt &lt; mcam-&gt;bmap_entries) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "mcam entries have already been assigned, can't resize");</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (max_nix0_lf &amp;&amp; val.vu16 &gt; max_nix0_lf) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "requested nixlf is greater than the max supported nix0_lf");</div><div class='add'>+		return -EPERM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (max_nix1_lf &amp;&amp; val.vu16 &gt; max_nix1_lf) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "requested nixlf is greater than the max supported nix1_lf");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct devlink_param rvu_af_dl_params[] = {</div><div class='ctx'> 	DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU,</div><div class='ctx'> 			     "dwrr_mtu", DEVLINK_PARAM_TYPE_U32,</div><div class='hunk'>@@ -1381,6 +1449,12 @@ static const struct devlink_param rvu_af_dl_param_exact_match[] = {</div><div class='ctx'> 			     rvu_af_dl_npc_mcam_high_zone_percent_get,</div><div class='ctx'> 			     rvu_af_dl_npc_mcam_high_zone_percent_set,</div><div class='ctx'> 			     rvu_af_dl_npc_mcam_high_zone_percent_validate),</div><div class='add'>+	DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF,</div><div class='add'>+			     "nix_maxlf", DEVLINK_PARAM_TYPE_U16,</div><div class='add'>+			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),</div><div class='add'>+			     rvu_af_dl_nix_maxlf_get,</div><div class='add'>+			     rvu_af_dl_nix_maxlf_set,</div><div class='add'>+			     rvu_af_dl_nix_maxlf_validate),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Devlink switch mode */</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c<br/>index 23c2f2ed2fb8..66203a90f052 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c</a></div><div class='hunk'>@@ -12,6 +12,7 @@</div><div class='ctx'> #include "rvu_reg.h"</div><div class='ctx'> #include "rvu.h"</div><div class='ctx'> #include "npc.h"</div><div class='add'>+#include "mcs.h"</div><div class='ctx'> #include "cgx.h"</div><div class='ctx'> #include "lmac_common.h"</div><div class='ctx'> #include "rvu_npc_hash.h"</div><div class='hunk'>@@ -71,12 +72,19 @@ enum nix_makr_fmt_indexes {</div><div class='ctx'> /* For now considering MC resources needed for broadcast</div><div class='ctx'>  * pkt replication only. i.e 256 HWVFs + 12 PFs.</div><div class='ctx'>  */</div><div class='del'>-#define MC_TBL_SIZE	MC_TBL_SZ_512</div><div class='del'>-#define MC_BUF_CNT	MC_BUF_CNT_128</div><div class='add'>+#define MC_TBL_SIZE	MC_TBL_SZ_2K</div><div class='add'>+#define MC_BUF_CNT	MC_BUF_CNT_1024</div><div class='add'>+</div><div class='add'>+#define MC_TX_MAX	2048</div><div class='ctx'> </div><div class='ctx'> struct mce {</div><div class='ctx'> 	struct hlist_node	node;</div><div class='add'>+	u32			rq_rss_index;</div><div class='ctx'> 	u16			pcifunc;</div><div class='add'>+	u16			channel;</div><div class='add'>+	u8			dest_type;</div><div class='add'>+	u8			is_active;</div><div class='add'>+	u8			reserved[2];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr)</div><div class='hunk'>@@ -164,18 +172,33 @@ static void nix_mce_list_init(struct nix_mce_list *list, int max)</div><div class='ctx'> 	list-&gt;max = max;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count)</div><div class='add'>+static int nix_alloc_mce_list(struct nix_mcast *mcast, int count, u8 dir)</div><div class='ctx'> {</div><div class='add'>+	struct rsrc_bmap *mce_counter;</div><div class='ctx'> 	int idx;</div><div class='ctx'> </div><div class='ctx'> 	if (!mcast)</div><div class='del'>-		return 0;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	idx = mcast-&gt;next_free_mce;</div><div class='del'>-	mcast-&gt;next_free_mce += count;</div><div class='add'>+	mce_counter = &amp;mcast-&gt;mce_counter[dir];</div><div class='add'>+	if (!rvu_rsrc_check_contig(mce_counter, count))</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+</div><div class='add'>+	idx = rvu_alloc_rsrc_contig(mce_counter, count);</div><div class='ctx'> 	return idx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nix_free_mce_list(struct nix_mcast *mcast, int count, int start, u8 dir)</div><div class='add'>+{</div><div class='add'>+	struct rsrc_bmap *mce_counter;</div><div class='add'>+</div><div class='add'>+	if (!mcast)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mce_counter = &amp;mcast-&gt;mce_counter[dir];</div><div class='add'>+	rvu_free_rsrc_contig(mce_counter, count, start);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)</div><div class='ctx'> {</div><div class='ctx'> 	int nix_blkaddr = 0, i = 0;</div><div class='hunk'>@@ -2955,7 +2978,8 @@ int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw,</div><div class='del'>-			     int mce, u8 op, u16 pcifunc, int next, bool eol)</div><div class='add'>+			     int mce, u8 op, u16 pcifunc, int next,</div><div class='add'>+			     int index, u8 mce_op, bool eol)</div><div class='ctx'> {</div><div class='ctx'> 	struct nix_aq_enq_req aq_req;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -2966,8 +2990,8 @@ static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw,</div><div class='ctx'> 	aq_req.qidx = mce;</div><div class='ctx'> </div><div class='ctx'> 	/* Use RSS with RSS index 0 */</div><div class='del'>-	aq_req.mce.op = 1;</div><div class='del'>-	aq_req.mce.index = 0;</div><div class='add'>+	aq_req.mce.op = mce_op;</div><div class='add'>+	aq_req.mce.index = index;</div><div class='ctx'> 	aq_req.mce.eol = eol;</div><div class='ctx'> 	aq_req.mce.pf_func = pcifunc;</div><div class='ctx'> 	aq_req.mce.next = next;</div><div class='hunk'>@@ -2984,6 +3008,206 @@ static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nix_delete_mcast_mce_list(struct nix_mce_list *mce_list)</div><div class='add'>+{</div><div class='add'>+	struct hlist_node *tmp;</div><div class='add'>+	struct mce *mce;</div><div class='add'>+</div><div class='add'>+	/* Scan through the current list */</div><div class='add'>+	hlist_for_each_entry_safe(mce, tmp, &amp;mce_list-&gt;head, node) {</div><div class='add'>+		hlist_del(&amp;mce-&gt;node);</div><div class='add'>+		kfree(mce);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mce_list-&gt;count = 0;</div><div class='add'>+	mce_list-&gt;max = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nix_get_last_mce_list_index(struct nix_mcast_grp_elem *elem)</div><div class='add'>+{</div><div class='add'>+	return elem-&gt;mce_start_index + elem-&gt;mcast_mce_list.count - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nix_update_ingress_mce_list_hw(struct rvu *rvu,</div><div class='add'>+					  struct nix_hw *nix_hw,</div><div class='add'>+					  struct nix_mcast_grp_elem *elem)</div><div class='add'>+{</div><div class='add'>+	int idx, last_idx, next_idx, err;</div><div class='add'>+	struct nix_mce_list *mce_list;</div><div class='add'>+	struct mce *mce, *prev_mce;</div><div class='add'>+</div><div class='add'>+	mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+	idx = elem-&gt;mce_start_index;</div><div class='add'>+	last_idx = nix_get_last_mce_list_index(elem);</div><div class='add'>+	hlist_for_each_entry(mce, &amp;mce_list-&gt;head, node) {</div><div class='add'>+		if (idx &gt; last_idx)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (!mce-&gt;is_active) {</div><div class='add'>+			if (idx == elem-&gt;mce_start_index) {</div><div class='add'>+				idx++;</div><div class='add'>+				prev_mce = mce;</div><div class='add'>+				elem-&gt;mce_start_index = idx;</div><div class='add'>+				continue;</div><div class='add'>+			} else if (idx == last_idx) {</div><div class='add'>+				err = nix_blk_setup_mce(rvu, nix_hw, idx - 1, NIX_AQ_INSTOP_WRITE,</div><div class='add'>+							prev_mce-&gt;pcifunc, next_idx,</div><div class='add'>+							prev_mce-&gt;rq_rss_index,</div><div class='add'>+							prev_mce-&gt;dest_type,</div><div class='add'>+							false);</div><div class='add'>+				if (err)</div><div class='add'>+					return err;</div><div class='add'>+</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		next_idx = idx + 1;</div><div class='add'>+		/* EOL should be set in last MCE */</div><div class='add'>+		err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE,</div><div class='add'>+					mce-&gt;pcifunc, next_idx,</div><div class='add'>+					mce-&gt;rq_rss_index, mce-&gt;dest_type,</div><div class='add'>+					(next_idx &gt; last_idx) ? true : false);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		idx++;</div><div class='add'>+		prev_mce = mce;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nix_update_egress_mce_list_hw(struct rvu *rvu,</div><div class='add'>+					  struct nix_hw *nix_hw,</div><div class='add'>+					  struct nix_mcast_grp_elem *elem)</div><div class='add'>+{</div><div class='add'>+	struct nix_mce_list *mce_list;</div><div class='add'>+	int idx, last_idx, next_idx;</div><div class='add'>+	struct mce *mce, *prev_mce;</div><div class='add'>+	u64 regval;</div><div class='add'>+	u8 eol;</div><div class='add'>+</div><div class='add'>+	mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+	idx = elem-&gt;mce_start_index;</div><div class='add'>+	last_idx = nix_get_last_mce_list_index(elem);</div><div class='add'>+	hlist_for_each_entry(mce, &amp;mce_list-&gt;head, node) {</div><div class='add'>+		if (idx &gt; last_idx)</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		if (!mce-&gt;is_active) {</div><div class='add'>+			if (idx == elem-&gt;mce_start_index) {</div><div class='add'>+				idx++;</div><div class='add'>+				prev_mce = mce;</div><div class='add'>+				elem-&gt;mce_start_index = idx;</div><div class='add'>+				continue;</div><div class='add'>+			} else if (idx == last_idx) {</div><div class='add'>+				regval = (next_idx &lt;&lt; 16) | (1 &lt;&lt; 12) | prev_mce-&gt;channel;</div><div class='add'>+				rvu_write64(rvu, nix_hw-&gt;blkaddr,</div><div class='add'>+					    NIX_AF_TX_MCASTX(idx - 1),</div><div class='add'>+					    regval);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		eol = 0;</div><div class='add'>+		next_idx = idx + 1;</div><div class='add'>+		/* EOL should be set in last MCE */</div><div class='add'>+		if (next_idx &gt; last_idx)</div><div class='add'>+			eol = 1;</div><div class='add'>+</div><div class='add'>+		regval = (next_idx &lt;&lt; 16) | (eol &lt;&lt; 12) | mce-&gt;channel;</div><div class='add'>+		rvu_write64(rvu, nix_hw-&gt;blkaddr,</div><div class='add'>+			    NIX_AF_TX_MCASTX(idx),</div><div class='add'>+			    regval);</div><div class='add'>+		idx++;</div><div class='add'>+		prev_mce = mce;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nix_del_mce_list_entry(struct rvu *rvu,</div><div class='add'>+				  struct nix_hw *nix_hw,</div><div class='add'>+				  struct nix_mcast_grp_elem *elem,</div><div class='add'>+				  struct nix_mcast_grp_update_req *req)</div><div class='add'>+{</div><div class='add'>+	u32 num_entry = req-&gt;num_mce_entry;</div><div class='add'>+	struct nix_mce_list *mce_list;</div><div class='add'>+	struct mce *mce;</div><div class='add'>+	bool is_found;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+	for (i = 0; i &lt; num_entry; i++) {</div><div class='add'>+		is_found = false;</div><div class='add'>+		hlist_for_each_entry(mce, &amp;mce_list-&gt;head, node) {</div><div class='add'>+			/* If already exists, then delete */</div><div class='add'>+			if (mce-&gt;pcifunc == req-&gt;pcifunc[i]) {</div><div class='add'>+				hlist_del(&amp;mce-&gt;node);</div><div class='add'>+				kfree(mce);</div><div class='add'>+				mce_list-&gt;count--;</div><div class='add'>+				is_found = true;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (!is_found)</div><div class='add'>+			return NIX_AF_ERR_INVALID_MCAST_DEL_REQ;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mce_list-&gt;max = mce_list-&gt;count;</div><div class='add'>+	/* Dump the updated list to HW */</div><div class='add'>+	if (elem-&gt;dir == NIX_MCAST_INGRESS)</div><div class='add'>+		return nix_update_ingress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+</div><div class='add'>+	nix_update_egress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nix_add_mce_list_entry(struct rvu *rvu,</div><div class='add'>+				  struct nix_hw *nix_hw,</div><div class='add'>+				  struct nix_mcast_grp_elem *elem,</div><div class='add'>+				  struct nix_mcast_grp_update_req *req)</div><div class='add'>+{</div><div class='add'>+	u32 num_entry = req-&gt;num_mce_entry;</div><div class='add'>+	struct nix_mce_list *mce_list;</div><div class='add'>+	struct hlist_node *tmp;</div><div class='add'>+	struct mce *mce;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+	for (i = 0; i &lt; num_entry; i++) {</div><div class='add'>+		mce = kzalloc(sizeof(*mce), GFP_KERNEL);</div><div class='add'>+		if (!mce)</div><div class='add'>+			goto free_mce;</div><div class='add'>+</div><div class='add'>+		mce-&gt;pcifunc = req-&gt;pcifunc[i];</div><div class='add'>+		mce-&gt;channel = req-&gt;channel[i];</div><div class='add'>+		mce-&gt;rq_rss_index = req-&gt;rq_rss_index[i];</div><div class='add'>+		mce-&gt;dest_type = req-&gt;dest_type[i];</div><div class='add'>+		mce-&gt;is_active = 1;</div><div class='add'>+		hlist_add_head(&amp;mce-&gt;node, &amp;mce_list-&gt;head);</div><div class='add'>+		mce_list-&gt;count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mce_list-&gt;max += num_entry;</div><div class='add'>+</div><div class='add'>+	/* Dump the updated list to HW */</div><div class='add'>+	if (elem-&gt;dir == NIX_MCAST_INGRESS)</div><div class='add'>+		return nix_update_ingress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+</div><div class='add'>+	nix_update_egress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_mce:</div><div class='add'>+	hlist_for_each_entry_safe(mce, tmp, &amp;mce_list-&gt;head, node) {</div><div class='add'>+		hlist_del(&amp;mce-&gt;node);</div><div class='add'>+		kfree(mce);</div><div class='add'>+		mce_list-&gt;count--;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ENOMEM;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int nix_update_mce_list_entry(struct nix_mce_list *mce_list,</div><div class='ctx'> 				     u16 pcifunc, bool add)</div><div class='ctx'> {</div><div class='hunk'>@@ -3079,6 +3303,7 @@ int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 		/* EOL should be set in last MCE */</div><div class='ctx'> 		err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE,</div><div class='ctx'> 					mce-&gt;pcifunc, next_idx,</div><div class='add'>+					0, 1,</div><div class='ctx'> 					(next_idx &gt; last_idx) ? true : false);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto end;</div><div class='hunk'>@@ -3159,6 +3384,16 @@ static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nix_setup_mcast_grp(struct nix_hw *nix_hw)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp *mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;mcast_grp-&gt;mcast_grp_head);</div><div class='add'>+	mutex_init(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	mcast_grp-&gt;next_grp_index = 1;</div><div class='add'>+	mcast_grp-&gt;count = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> {</div><div class='ctx'> 	struct nix_mcast *mcast = &amp;nix_hw-&gt;mcast;</div><div class='hunk'>@@ -3183,15 +3418,15 @@ static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		/* save start idx of broadcast mce list */</div><div class='del'>-		pfvf-&gt;bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);</div><div class='add'>+		pfvf-&gt;bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1, NIX_MCAST_INGRESS);</div><div class='ctx'> 		nix_mce_list_init(&amp;pfvf-&gt;bcast_mce_list, numvfs + 1);</div><div class='ctx'> </div><div class='ctx'> 		/* save start idx of multicast mce list */</div><div class='del'>-		pfvf-&gt;mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);</div><div class='add'>+		pfvf-&gt;mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1, NIX_MCAST_INGRESS);</div><div class='ctx'> 		nix_mce_list_init(&amp;pfvf-&gt;mcast_mce_list, numvfs + 1);</div><div class='ctx'> </div><div class='ctx'> 		/* save the start idx of promisc mce list */</div><div class='del'>-		pfvf-&gt;promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);</div><div class='add'>+		pfvf-&gt;promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1, NIX_MCAST_INGRESS);</div><div class='ctx'> 		nix_mce_list_init(&amp;pfvf-&gt;promisc_mce_list, numvfs + 1);</div><div class='ctx'> </div><div class='ctx'> 		for (idx = 0; idx &lt; (numvfs + 1); idx++) {</div><div class='hunk'>@@ -3206,7 +3441,7 @@ static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> 			err = nix_blk_setup_mce(rvu, nix_hw,</div><div class='ctx'> 						pfvf-&gt;bcast_mce_idx + idx,</div><div class='ctx'> 						NIX_AQ_INSTOP_INIT,</div><div class='del'>-						pcifunc, 0, true);</div><div class='add'>+						pcifunc, 0, 0, 1, true);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='ctx'> </div><div class='hunk'>@@ -3214,7 +3449,7 @@ static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> 			err = nix_blk_setup_mce(rvu, nix_hw,</div><div class='ctx'> 						pfvf-&gt;mcast_mce_idx + idx,</div><div class='ctx'> 						NIX_AQ_INSTOP_INIT,</div><div class='del'>-						pcifunc, 0, true);</div><div class='add'>+						pcifunc, 0, 0, 1, true);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='ctx'> </div><div class='hunk'>@@ -3222,7 +3457,7 @@ static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)</div><div class='ctx'> 			err = nix_blk_setup_mce(rvu, nix_hw,</div><div class='ctx'> 						pfvf-&gt;promisc_mce_idx + idx,</div><div class='ctx'> 						NIX_AQ_INSTOP_INIT,</div><div class='del'>-						pcifunc, 0, true);</div><div class='add'>+						pcifunc, 0, 0, 1, true);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='ctx'> 		}</div><div class='hunk'>@@ -3237,13 +3472,30 @@ static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)</div><div class='ctx'> 	int err, size;</div><div class='ctx'> </div><div class='ctx'> 	size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) &gt;&gt; 16) &amp; 0x0F;</div><div class='del'>-	size = (1ULL &lt;&lt; size);</div><div class='add'>+	size = BIT_ULL(size);</div><div class='add'>+</div><div class='add'>+	/* Allocate bitmap for rx mce entries */</div><div class='add'>+	mcast-&gt;mce_counter[NIX_MCAST_INGRESS].max = 256UL &lt;&lt; MC_TBL_SIZE;</div><div class='add'>+	err = rvu_alloc_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_INGRESS]);</div><div class='add'>+	if (err)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	/* Allocate bitmap for tx mce entries */</div><div class='add'>+	mcast-&gt;mce_counter[NIX_MCAST_EGRESS].max = MC_TX_MAX;</div><div class='add'>+	err = rvu_alloc_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_EGRESS]);</div><div class='add'>+	if (err) {</div><div class='add'>+		rvu_free_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_INGRESS]);</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Alloc memory for multicast/mirror replication entries */</div><div class='ctx'> 	err = qmem_alloc(rvu-&gt;dev, &amp;mcast-&gt;mce_ctx,</div><div class='del'>-			 (256UL &lt;&lt; MC_TBL_SIZE), size);</div><div class='del'>-	if (err)</div><div class='add'>+			 mcast-&gt;mce_counter[NIX_MCAST_INGRESS].max, size);</div><div class='add'>+	if (err) {</div><div class='add'>+		rvu_free_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_INGRESS]);</div><div class='add'>+		rvu_free_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_EGRESS]);</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE,</div><div class='ctx'> 		    (u64)mcast-&gt;mce_ctx-&gt;iova);</div><div class='hunk'>@@ -3256,8 +3508,11 @@ static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)</div><div class='ctx'> 	size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) &amp; 0xFFFF;</div><div class='ctx'> 	err = qmem_alloc(rvu-&gt;dev, &amp;mcast-&gt;mcast_buf,</div><div class='ctx'> 			 (8UL &lt;&lt; MC_BUF_CNT), size);</div><div class='del'>-	if (err)</div><div class='add'>+	if (err) {</div><div class='add'>+		rvu_free_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_INGRESS]);</div><div class='add'>+		rvu_free_bitmap(&amp;mcast-&gt;mce_counter[NIX_MCAST_EGRESS]);</div><div class='ctx'> 		return -ENOMEM;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE,</div><div class='ctx'> 		    (u64)mcast-&gt;mcast_buf-&gt;iova);</div><div class='hunk'>@@ -3271,6 +3526,8 @@ static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;mcast-&gt;mce_lock);</div><div class='ctx'> </div><div class='add'>+	nix_setup_mcast_grp(nix_hw);</div><div class='add'>+</div><div class='ctx'> 	return nix_setup_mce_tables(rvu, nix_hw);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -4142,90 +4399,18 @@ static void nix_find_link_frs(struct rvu *rvu,</div><div class='ctx'> 		req-&gt;minlen = minlen;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int</div><div class='del'>-nix_config_link_credits(struct rvu *rvu, int blkaddr, int link,</div><div class='del'>-			u16 pcifunc, u64 tx_credits)</div><div class='del'>-{</div><div class='del'>-	struct rvu_hwinfo *hw = rvu-&gt;hw;</div><div class='del'>-	int pf = rvu_get_pf(pcifunc);</div><div class='del'>-	u8 cgx_id = 0, lmac_id = 0;</div><div class='del'>-	unsigned long poll_tmo;</div><div class='del'>-	bool restore_tx_en = 0;</div><div class='del'>-	struct nix_hw *nix_hw;</div><div class='del'>-	u64 cfg, sw_xoff = 0;</div><div class='del'>-	u32 schq = 0;</div><div class='del'>-	u32 credits;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	nix_hw = get_nix_hw(rvu-&gt;hw, blkaddr);</div><div class='del'>-	if (!nix_hw)</div><div class='del'>-		return NIX_AF_ERR_INVALID_NIXBLK;</div><div class='del'>-</div><div class='del'>-	if (tx_credits == nix_hw-&gt;tx_credits[link])</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Enable cgx tx if disabled for credits to be back */</div><div class='del'>-	if (is_pf_cgxmapped(rvu, pf)) {</div><div class='del'>-		rvu_get_cgx_lmac_id(rvu-&gt;pf2cgxlmac_map[pf], &amp;cgx_id, &amp;lmac_id);</div><div class='del'>-		restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu),</div><div class='del'>-						    lmac_id, true);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;rvu-&gt;rsrc_lock);</div><div class='del'>-	/* Disable new traffic to link */</div><div class='del'>-	if (hw-&gt;cap.nix_shaping) {</div><div class='del'>-		schq = nix_get_tx_link(rvu, pcifunc);</div><div class='del'>-		sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq));</div><div class='del'>-		rvu_write64(rvu, blkaddr,</div><div class='del'>-			    NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rc = NIX_AF_ERR_LINK_CREDITS;</div><div class='del'>-	poll_tmo = jiffies + usecs_to_jiffies(200000);</div><div class='del'>-	/* Wait for credits to return */</div><div class='del'>-	do {</div><div class='del'>-		if (time_after(jiffies, poll_tmo))</div><div class='del'>-			goto exit;</div><div class='del'>-		usleep_range(100, 200);</div><div class='del'>-</div><div class='del'>-		cfg = rvu_read64(rvu, blkaddr,</div><div class='del'>-				 NIX_AF_TX_LINKX_NORM_CREDIT(link));</div><div class='del'>-		credits = (cfg &gt;&gt; 12) &amp; 0xFFFFFULL;</div><div class='del'>-	} while (credits != nix_hw-&gt;tx_credits[link]);</div><div class='del'>-</div><div class='del'>-	cfg &amp;= ~(0xFFFFFULL &lt;&lt; 12);</div><div class='del'>-	cfg |= (tx_credits &lt;&lt; 12);</div><div class='del'>-	rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg);</div><div class='del'>-	rc = 0;</div><div class='del'>-</div><div class='del'>-	nix_hw-&gt;tx_credits[link] = tx_credits;</div><div class='del'>-</div><div class='del'>-exit:</div><div class='del'>-	/* Enable traffic back */</div><div class='del'>-	if (hw-&gt;cap.nix_shaping &amp;&amp; !sw_xoff)</div><div class='del'>-		rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0);</div><div class='del'>-</div><div class='del'>-	/* Restore state of cgx tx */</div><div class='del'>-	if (restore_tx_en)</div><div class='del'>-		rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false);</div><div class='del'>-</div><div class='del'>-	mutex_unlock(&amp;rvu-&gt;rsrc_lock);</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,</div><div class='ctx'> 				    struct msg_rsp *rsp)</div><div class='ctx'> {</div><div class='ctx'> 	struct rvu_hwinfo *hw = rvu-&gt;hw;</div><div class='ctx'> 	u16 pcifunc = req-&gt;hdr.pcifunc;</div><div class='ctx'> 	int pf = rvu_get_pf(pcifunc);</div><div class='del'>-	int blkaddr, schq, link = -1;</div><div class='del'>-	struct nix_txsch *txsch;</div><div class='del'>-	u64 cfg, lmac_fifo_len;</div><div class='add'>+	int blkaddr, link = -1;</div><div class='ctx'> 	struct nix_hw *nix_hw;</div><div class='ctx'> 	struct rvu_pfvf *pfvf;</div><div class='ctx'> 	u8 cgx = 0, lmac = 0;</div><div class='ctx'> 	u16 max_mtu;</div><div class='add'>+	u64 cfg;</div><div class='ctx'> </div><div class='ctx'> 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);</div><div class='ctx'> 	if (blkaddr &lt; 0)</div><div class='hunk'>@@ -4246,25 +4431,6 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,</div><div class='ctx'> 	if (req-&gt;update_minlen &amp;&amp; req-&gt;minlen &lt; NIC_HW_MIN_FRS)</div><div class='ctx'> 		return NIX_AF_ERR_FRS_INVALID;</div><div class='ctx'> </div><div class='del'>-	/* Check if requester wants to update SMQ's */</div><div class='del'>-	if (!req-&gt;update_smq)</div><div class='del'>-		goto rx_frscfg;</div><div class='del'>-</div><div class='del'>-	/* Update min/maxlen in each of the SMQ attached to this PF/VF */</div><div class='del'>-	txsch = &amp;nix_hw-&gt;txsch[NIX_TXSCH_LVL_SMQ];</div><div class='del'>-	mutex_lock(&amp;rvu-&gt;rsrc_lock);</div><div class='del'>-	for (schq = 0; schq &lt; txsch-&gt;schq.max; schq++) {</div><div class='del'>-		if (TXSCH_MAP_FUNC(txsch-&gt;pfvf_map[schq]) != pcifunc)</div><div class='del'>-			continue;</div><div class='del'>-		cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq));</div><div class='del'>-		cfg = (cfg &amp; ~(0xFFFFULL &lt;&lt; 8)) | ((u64)req-&gt;maxlen &lt;&lt; 8);</div><div class='del'>-		if (req-&gt;update_minlen)</div><div class='del'>-			cfg = (cfg &amp; ~0x7FULL) | ((u64)req-&gt;minlen &amp; 0x7F);</div><div class='del'>-		rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg);</div><div class='del'>-	}</div><div class='del'>-	mutex_unlock(&amp;rvu-&gt;rsrc_lock);</div><div class='del'>-</div><div class='del'>-rx_frscfg:</div><div class='ctx'> 	/* Check if config is for SDP link */</div><div class='ctx'> 	if (req-&gt;sdp_link) {</div><div class='ctx'> 		if (!hw-&gt;sdp_links)</div><div class='hunk'>@@ -4287,7 +4453,6 @@ rx_frscfg:</div><div class='ctx'> 	if (link &lt; 0)</div><div class='ctx'> 		return NIX_AF_ERR_RX_LINK_INVALID;</div><div class='ctx'> </div><div class='del'>-</div><div class='ctx'> linkcfg:</div><div class='ctx'> 	nix_find_link_frs(rvu, req, pcifunc);</div><div class='ctx'> </div><div class='hunk'>@@ -4297,19 +4462,7 @@ linkcfg:</div><div class='ctx'> 		cfg = (cfg &amp; ~0xFFFFULL) | req-&gt;minlen;</div><div class='ctx'> 	rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg);</div><div class='ctx'> </div><div class='del'>-	if (req-&gt;sdp_link || pf == 0)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	/* Update transmit credits for CGX links */</div><div class='del'>-	lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac);</div><div class='del'>-	if (!lmac_fifo_len) {</div><div class='del'>-		dev_err(rvu-&gt;dev,</div><div class='del'>-			"%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n",</div><div class='del'>-			__func__, cgx, lmac);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-	return nix_config_link_credits(rvu, blkaddr, link, pcifunc,</div><div class='del'>-				       (lmac_fifo_len - req-&gt;maxlen) / 16);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,</div><div class='hunk'>@@ -4389,6 +4542,12 @@ static void nix_link_config(struct rvu *rvu, int blkaddr,</div><div class='ctx'> 			    SDP_HW_MAX_FRS &lt;&lt; 16 | NIC_HW_MIN_FRS);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Get MCS external bypass status for CN10K-B */</div><div class='add'>+	if (mcs_get_blkcnt() == 1) {</div><div class='add'>+		/* Adjust for 2 credits when external bypass is disabled */</div><div class='add'>+		nix_hw-&gt;cc_mcs_cnt = is_mcs_bypass(0) ? 0 : 2;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Set credits for Tx links assuming max packet length allowed.</div><div class='ctx'> 	 * This will be reconfigured based on MTU set for PF/VF.</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -4412,6 +4571,7 @@ static void nix_link_config(struct rvu *rvu, int blkaddr,</div><div class='ctx'> 			tx_credits = (lmac_fifo_len - lmac_max_frs) / 16;</div><div class='ctx'> 			/* Enable credits and set credit pkt count to max allowed */</div><div class='ctx'> 			cfg =  (tx_credits &lt;&lt; 12) | (0x1FF &lt;&lt; 2) | BIT_ULL(1);</div><div class='add'>+			cfg |= FIELD_PREP(NIX_AF_LINKX_MCS_CNT_MASK, nix_hw-&gt;cc_mcs_cnt);</div><div class='ctx'> </div><div class='ctx'> 			link = iter + slink;</div><div class='ctx'> 			nix_hw-&gt;tx_credits[link] = tx_credits;</div><div class='hunk'>@@ -4794,6 +4954,74 @@ void rvu_nix_freemem(struct rvu *rvu)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nix_mcast_update_action(struct rvu *rvu,</div><div class='add'>+				    struct nix_mcast_grp_elem *elem)</div><div class='add'>+{</div><div class='add'>+	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='add'>+	struct nix_rx_action rx_action = { 0 };</div><div class='add'>+	struct nix_tx_action tx_action = { 0 };</div><div class='add'>+	int npc_blkaddr;</div><div class='add'>+</div><div class='add'>+	npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);</div><div class='add'>+	if (elem-&gt;dir == NIX_MCAST_INGRESS) {</div><div class='add'>+		*(u64 *)&amp;rx_action = npc_get_mcam_action(rvu, mcam,</div><div class='add'>+							 npc_blkaddr,</div><div class='add'>+							 elem-&gt;mcam_index);</div><div class='add'>+		rx_action.index = elem-&gt;mce_start_index;</div><div class='add'>+		npc_set_mcam_action(rvu, mcam, npc_blkaddr, elem-&gt;mcam_index,</div><div class='add'>+				    *(u64 *)&amp;rx_action);</div><div class='add'>+	} else {</div><div class='add'>+		*(u64 *)&amp;tx_action = npc_get_mcam_action(rvu, mcam,</div><div class='add'>+							 npc_blkaddr,</div><div class='add'>+							 elem-&gt;mcam_index);</div><div class='add'>+		tx_action.index = elem-&gt;mce_start_index;</div><div class='add'>+		npc_set_mcam_action(rvu, mcam, npc_blkaddr, elem-&gt;mcam_index,</div><div class='add'>+				    *(u64 *)&amp;tx_action);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nix_mcast_update_mce_entry(struct rvu *rvu, u16 pcifunc, u8 is_active)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int blkaddr;</div><div class='add'>+</div><div class='add'>+	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);</div><div class='add'>+	nix_hw = get_nix_hw(rvu-&gt;hw, blkaddr);</div><div class='add'>+	if (!nix_hw)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	list_for_each_entry(elem, &amp;mcast_grp-&gt;mcast_grp_head, list) {</div><div class='add'>+		struct nix_mce_list *mce_list;</div><div class='add'>+		struct mce *mce;</div><div class='add'>+</div><div class='add'>+		/* Iterate the group elements and disable the element which</div><div class='add'>+		 * received the disable request.</div><div class='add'>+		 */</div><div class='add'>+		mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+		hlist_for_each_entry(mce, &amp;mce_list-&gt;head, node) {</div><div class='add'>+			if (mce-&gt;pcifunc == pcifunc) {</div><div class='add'>+				mce-&gt;is_active = is_active;</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Dump the updated list to HW */</div><div class='add'>+		if (elem-&gt;dir == NIX_MCAST_INGRESS)</div><div class='add'>+			nix_update_ingress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+		else</div><div class='add'>+			nix_update_egress_mce_list_hw(rvu, nix_hw, elem);</div><div class='add'>+</div><div class='add'>+		/* Update the multicast index in NPC rule */</div><div class='add'>+		nix_mcast_update_action(rvu, elem);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req,</div><div class='ctx'> 				     struct msg_rsp *rsp)</div><div class='ctx'> {</div><div class='hunk'>@@ -4805,6 +5033,9 @@ int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='add'>+	/* Enable the interface if it is in any multicast list */</div><div class='add'>+	nix_mcast_update_mce_entry(rvu, pcifunc, 1);</div><div class='add'>+</div><div class='ctx'> 	rvu_npc_enable_default_entries(rvu, pcifunc, nixlf);</div><div class='ctx'> </div><div class='ctx'> 	npc_mcam_enable_flows(rvu, pcifunc);</div><div class='hunk'>@@ -4829,11 +5060,20 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req,</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);</div><div class='add'>+	/* Disable the interface if it is in any multicast list */</div><div class='add'>+	nix_mcast_update_mce_entry(rvu, pcifunc, 0);</div><div class='add'>+</div><div class='ctx'> </div><div class='ctx'> 	pfvf = rvu_get_pfvf(rvu, pcifunc);</div><div class='ctx'> 	clear_bit(NIXLF_INITIALIZED, &amp;pfvf-&gt;flags);</div><div class='ctx'> </div><div class='del'>-	return rvu_cgx_start_stop_io(rvu, pcifunc, false);</div><div class='add'>+	err = rvu_cgx_start_stop_io(rvu, pcifunc, false);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	rvu_cgx_tx_enable(rvu, pcifunc, true);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #define RX_SA_BASE  GENMASK_ULL(52, 7)</div><div class='hunk'>@@ -5505,6 +5745,8 @@ int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu,</div><div class='ctx'> </div><div class='ctx'> 		ipolicer = &amp;nix_hw-&gt;ipolicer[layer];</div><div class='ctx'> 		for (idx = 0; idx &lt; req-&gt;prof_count[layer]; idx++) {</div><div class='add'>+			if (idx == MAX_BANDPROF_PER_PFFUNC)</div><div class='add'>+				break;</div><div class='ctx'> 			prof_idx = req-&gt;prof_idx[layer][idx];</div><div class='ctx'> 			if (prof_idx &gt;= ipolicer-&gt;band_prof.max ||</div><div class='ctx'> 			    ipolicer-&gt;pfvf_map[prof_idx] != pcifunc)</div><div class='hunk'>@@ -5518,8 +5760,6 @@ int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu,</div><div class='ctx'> 			ipolicer-&gt;pfvf_map[prof_idx] = 0x00;</div><div class='ctx'> 			ipolicer-&gt;match_id[prof_idx] = 0;</div><div class='ctx'> 			rvu_free_rsrc(&amp;ipolicer-&gt;band_prof, prof_idx);</div><div class='del'>-			if (idx == MAX_BANDPROF_PER_PFFUNC)</div><div class='del'>-				break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> 	mutex_unlock(&amp;rvu-&gt;rsrc_lock);</div><div class='hunk'>@@ -5797,3 +6037,361 @@ int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *re</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static struct nix_mcast_grp_elem *rvu_nix_mcast_find_grp_elem(struct nix_mcast_grp *mcast_grp,</div><div class='add'>+							      u32 mcast_grp_idx)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_elem *iter;</div><div class='add'>+	bool is_found = false;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(iter, &amp;mcast_grp-&gt;mcast_grp_head, list) {</div><div class='add'>+		if (iter-&gt;mcast_grp_idx == mcast_grp_idx) {</div><div class='add'>+			is_found = true;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (is_found)</div><div class='add'>+		return iter;</div><div class='add'>+</div><div class='add'>+	return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, u32 mcast_grp_idx)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int blkaddr, ret;</div><div class='add'>+</div><div class='add'>+	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);</div><div class='add'>+	nix_hw = get_nix_hw(rvu-&gt;hw, blkaddr);</div><div class='add'>+	if (!nix_hw)</div><div class='add'>+		return NIX_AF_ERR_INVALID_NIXBLK;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+	mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	elem = rvu_nix_mcast_find_grp_elem(mcast_grp, mcast_grp_idx);</div><div class='add'>+	if (!elem)</div><div class='add'>+		ret = NIX_AF_ERR_INVALID_MCAST_GRP;</div><div class='add'>+	else</div><div class='add'>+		ret = elem-&gt;mce_start_index;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_destroy_req dreq = { 0 };</div><div class='add'>+	struct nix_mcast_grp_update_req ureq = { 0 };</div><div class='add'>+	struct nix_mcast_grp_update_rsp ursp = { 0 };</div><div class='add'>+	struct nix_mcast_grp_elem *elem, *tmp;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int blkaddr;</div><div class='add'>+</div><div class='add'>+	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);</div><div class='add'>+	nix_hw = get_nix_hw(rvu-&gt;hw, blkaddr);</div><div class='add'>+	if (!nix_hw)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	list_for_each_entry_safe(elem, tmp, &amp;mcast_grp-&gt;mcast_grp_head, list) {</div><div class='add'>+		struct nix_mce_list *mce_list;</div><div class='add'>+		struct hlist_node *tmp;</div><div class='add'>+		struct mce *mce;</div><div class='add'>+</div><div class='add'>+		/* If the pcifunc which created the multicast/mirror</div><div class='add'>+		 * group received an FLR, then delete the entire group.</div><div class='add'>+		 */</div><div class='add'>+		if (elem-&gt;pcifunc == pcifunc) {</div><div class='add'>+			/* Delete group */</div><div class='add'>+			dreq.hdr.pcifunc = elem-&gt;pcifunc;</div><div class='add'>+			dreq.mcast_grp_idx = elem-&gt;mcast_grp_idx;</div><div class='add'>+			dreq.is_af = 1;</div><div class='add'>+			rvu_mbox_handler_nix_mcast_grp_destroy(rvu, &amp;dreq, NULL);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		/* Iterate the group elements and delete the element which</div><div class='add'>+		 * received the FLR.</div><div class='add'>+		 */</div><div class='add'>+		mce_list = &amp;elem-&gt;mcast_mce_list;</div><div class='add'>+		hlist_for_each_entry_safe(mce, tmp, &amp;mce_list-&gt;head, node) {</div><div class='add'>+			if (mce-&gt;pcifunc == pcifunc) {</div><div class='add'>+				ureq.hdr.pcifunc = pcifunc;</div><div class='add'>+				ureq.num_mce_entry = 1;</div><div class='add'>+				ureq.mcast_grp_idx = elem-&gt;mcast_grp_idx;</div><div class='add'>+				ureq.op = NIX_MCAST_OP_DEL_ENTRY;</div><div class='add'>+				ureq.pcifunc[0] = pcifunc;</div><div class='add'>+				ureq.is_af = 1;</div><div class='add'>+				rvu_mbox_handler_nix_mcast_grp_update(rvu, &amp;ureq, &amp;ursp);</div><div class='add'>+				break;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,</div><div class='add'>+				    u32 mcast_grp_idx, u16 mcam_index)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int blkaddr, ret = 0;</div><div class='add'>+</div><div class='add'>+	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);</div><div class='add'>+	nix_hw = get_nix_hw(rvu-&gt;hw, blkaddr);</div><div class='add'>+	if (!nix_hw)</div><div class='add'>+		return NIX_AF_ERR_INVALID_NIXBLK;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+	mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	elem = rvu_nix_mcast_find_grp_elem(mcast_grp, mcast_grp_idx);</div><div class='add'>+	if (!elem)</div><div class='add'>+		ret = NIX_AF_ERR_INVALID_MCAST_GRP;</div><div class='add'>+	else</div><div class='add'>+		elem-&gt;mcam_index = mcam_index;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rvu_mbox_handler_nix_mcast_grp_create(struct rvu *rvu,</div><div class='add'>+					  struct nix_mcast_grp_create_req *req,</div><div class='add'>+					  struct nix_mcast_grp_create_rsp *rsp)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int blkaddr, err;</div><div class='add'>+</div><div class='add'>+	err = nix_get_struct_ptrs(rvu, req-&gt;hdr.pcifunc, &amp;nix_hw, &amp;blkaddr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+	elem = kzalloc(sizeof(*elem), GFP_KERNEL);</div><div class='add'>+	if (!elem)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	INIT_HLIST_HEAD(&amp;elem-&gt;mcast_mce_list.head);</div><div class='add'>+	elem-&gt;mcam_index = -1;</div><div class='add'>+	elem-&gt;mce_start_index = -1;</div><div class='add'>+	elem-&gt;pcifunc = req-&gt;hdr.pcifunc;</div><div class='add'>+	elem-&gt;dir = req-&gt;dir;</div><div class='add'>+	elem-&gt;mcast_grp_idx = mcast_grp-&gt;next_grp_index++;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+	list_add_tail(&amp;elem-&gt;list, &amp;mcast_grp-&gt;mcast_grp_head);</div><div class='add'>+	mcast_grp-&gt;count++;</div><div class='add'>+	mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+</div><div class='add'>+	rsp-&gt;mcast_grp_idx = elem-&gt;mcast_grp_idx;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rvu_mbox_handler_nix_mcast_grp_destroy(struct rvu *rvu,</div><div class='add'>+					   struct nix_mcast_grp_destroy_req *req,</div><div class='add'>+					   struct msg_rsp *rsp)</div><div class='add'>+{</div><div class='add'>+	struct npc_delete_flow_req uninstall_req = { 0 };</div><div class='add'>+	struct npc_delete_flow_rsp uninstall_rsp = { 0 };</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	int blkaddr, err, ret = 0;</div><div class='add'>+	struct nix_mcast *mcast;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+</div><div class='add'>+	err = nix_get_struct_ptrs(rvu, req-&gt;hdr.pcifunc, &amp;nix_hw, &amp;blkaddr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+</div><div class='add'>+	/* If AF is requesting for the deletion,</div><div class='add'>+	 * then AF is already taking the lock</div><div class='add'>+	 */</div><div class='add'>+	if (!req-&gt;is_af)</div><div class='add'>+		mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+</div><div class='add'>+	elem = rvu_nix_mcast_find_grp_elem(mcast_grp, req-&gt;mcast_grp_idx);</div><div class='add'>+	if (!elem) {</div><div class='add'>+		ret = NIX_AF_ERR_INVALID_MCAST_GRP;</div><div class='add'>+		goto unlock_grp;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If no mce entries are associated with the group</div><div class='add'>+	 * then just remove it from the global list.</div><div class='add'>+	 */</div><div class='add'>+	if (!elem-&gt;mcast_mce_list.count)</div><div class='add'>+		goto delete_grp;</div><div class='add'>+</div><div class='add'>+	/* Delete the associated mcam entry and</div><div class='add'>+	 * remove all mce entries from the group</div><div class='add'>+	 */</div><div class='add'>+	mcast = &amp;nix_hw-&gt;mcast;</div><div class='add'>+	mutex_lock(&amp;mcast-&gt;mce_lock);</div><div class='add'>+	if (elem-&gt;mcam_index != -1) {</div><div class='add'>+		uninstall_req.hdr.pcifunc = req-&gt;hdr.pcifunc;</div><div class='add'>+		uninstall_req.entry = elem-&gt;mcam_index;</div><div class='add'>+		rvu_mbox_handler_npc_delete_flow(rvu, &amp;uninstall_req, &amp;uninstall_rsp);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nix_free_mce_list(mcast, elem-&gt;mcast_mce_list.count,</div><div class='add'>+			  elem-&gt;mce_start_index, elem-&gt;dir);</div><div class='add'>+	nix_delete_mcast_mce_list(&amp;elem-&gt;mcast_mce_list);</div><div class='add'>+	mutex_unlock(&amp;mcast-&gt;mce_lock);</div><div class='add'>+</div><div class='add'>+delete_grp:</div><div class='add'>+	list_del(&amp;elem-&gt;list);</div><div class='add'>+	kfree(elem);</div><div class='add'>+	mcast_grp-&gt;count--;</div><div class='add'>+</div><div class='add'>+unlock_grp:</div><div class='add'>+	if (!req-&gt;is_af)</div><div class='add'>+		mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rvu_mbox_handler_nix_mcast_grp_update(struct rvu *rvu,</div><div class='add'>+					  struct nix_mcast_grp_update_req *req,</div><div class='add'>+					  struct nix_mcast_grp_update_rsp *rsp)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_destroy_req dreq = { 0 };</div><div class='add'>+	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='add'>+	struct nix_mcast_grp_elem *elem;</div><div class='add'>+	struct nix_mcast_grp *mcast_grp;</div><div class='add'>+	int blkaddr, err, npc_blkaddr;</div><div class='add'>+	u16 prev_count, new_count;</div><div class='add'>+	struct nix_mcast *mcast;</div><div class='add'>+	struct nix_hw *nix_hw;</div><div class='add'>+	int i, ret;</div><div class='add'>+</div><div class='add'>+	if (!req-&gt;num_mce_entry)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = nix_get_struct_ptrs(rvu, req-&gt;hdr.pcifunc, &amp;nix_hw, &amp;blkaddr);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	mcast_grp = &amp;nix_hw-&gt;mcast_grp;</div><div class='add'>+</div><div class='add'>+	/* If AF is requesting for the updation,</div><div class='add'>+	 * then AF is already taking the lock</div><div class='add'>+	 */</div><div class='add'>+	if (!req-&gt;is_af)</div><div class='add'>+		mutex_lock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+</div><div class='add'>+	elem = rvu_nix_mcast_find_grp_elem(mcast_grp, req-&gt;mcast_grp_idx);</div><div class='add'>+	if (!elem) {</div><div class='add'>+		ret = NIX_AF_ERR_INVALID_MCAST_GRP;</div><div class='add'>+		goto unlock_grp;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* If any pcifunc matches the group's pcifunc, then we can</div><div class='add'>+	 * delete the entire group.</div><div class='add'>+	 */</div><div class='add'>+	if (req-&gt;op == NIX_MCAST_OP_DEL_ENTRY) {</div><div class='add'>+		for (i = 0; i &lt; req-&gt;num_mce_entry; i++) {</div><div class='add'>+			if (elem-&gt;pcifunc == req-&gt;pcifunc[i]) {</div><div class='add'>+				/* Delete group */</div><div class='add'>+				dreq.hdr.pcifunc = elem-&gt;pcifunc;</div><div class='add'>+				dreq.mcast_grp_idx = elem-&gt;mcast_grp_idx;</div><div class='add'>+				dreq.is_af = 1;</div><div class='add'>+				rvu_mbox_handler_nix_mcast_grp_destroy(rvu, &amp;dreq, NULL);</div><div class='add'>+				ret = 0;</div><div class='add'>+				goto unlock_grp;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mcast = &amp;nix_hw-&gt;mcast;</div><div class='add'>+	mutex_lock(&amp;mcast-&gt;mce_lock);</div><div class='add'>+	npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);</div><div class='add'>+	if (elem-&gt;mcam_index != -1)</div><div class='add'>+		npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, elem-&gt;mcam_index, false);</div><div class='add'>+</div><div class='add'>+	prev_count = elem-&gt;mcast_mce_list.count;</div><div class='add'>+	if (req-&gt;op == NIX_MCAST_OP_ADD_ENTRY) {</div><div class='add'>+		new_count = prev_count + req-&gt;num_mce_entry;</div><div class='add'>+		if (prev_count)</div><div class='add'>+			nix_free_mce_list(mcast, prev_count, elem-&gt;mce_start_index, elem-&gt;dir);</div><div class='add'>+</div><div class='add'>+		elem-&gt;mce_start_index = nix_alloc_mce_list(mcast, new_count, elem-&gt;dir);</div><div class='add'>+</div><div class='add'>+		/* It is possible not to get contiguous memory */</div><div class='add'>+		if (elem-&gt;mce_start_index &lt; 0) {</div><div class='add'>+			if (elem-&gt;mcam_index != -1) {</div><div class='add'>+				npc_enable_mcam_entry(rvu, mcam, npc_blkaddr,</div><div class='add'>+						      elem-&gt;mcam_index, true);</div><div class='add'>+				ret = NIX_AF_ERR_NON_CONTIG_MCE_LIST;</div><div class='add'>+				goto unlock_mce;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = nix_add_mce_list_entry(rvu, nix_hw, elem, req);</div><div class='add'>+		if (ret) {</div><div class='add'>+			nix_free_mce_list(mcast, new_count, elem-&gt;mce_start_index, elem-&gt;dir);</div><div class='add'>+			if (prev_count)</div><div class='add'>+				elem-&gt;mce_start_index = nix_alloc_mce_list(mcast,</div><div class='add'>+									   prev_count,</div><div class='add'>+									   elem-&gt;dir);</div><div class='add'>+</div><div class='add'>+			if (elem-&gt;mcam_index != -1)</div><div class='add'>+				npc_enable_mcam_entry(rvu, mcam, npc_blkaddr,</div><div class='add'>+						      elem-&gt;mcam_index, true);</div><div class='add'>+</div><div class='add'>+			goto unlock_mce;</div><div class='add'>+		}</div><div class='add'>+	} else {</div><div class='add'>+		if (!prev_count || prev_count &lt; req-&gt;num_mce_entry) {</div><div class='add'>+			if (elem-&gt;mcam_index != -1)</div><div class='add'>+				npc_enable_mcam_entry(rvu, mcam, npc_blkaddr,</div><div class='add'>+						      elem-&gt;mcam_index, true);</div><div class='add'>+			ret = NIX_AF_ERR_INVALID_MCAST_DEL_REQ;</div><div class='add'>+			goto unlock_mce;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		nix_free_mce_list(mcast, prev_count, elem-&gt;mce_start_index, elem-&gt;dir);</div><div class='add'>+		new_count = prev_count - req-&gt;num_mce_entry;</div><div class='add'>+		elem-&gt;mce_start_index = nix_alloc_mce_list(mcast, new_count, elem-&gt;dir);</div><div class='add'>+		ret = nix_del_mce_list_entry(rvu, nix_hw, elem, req);</div><div class='add'>+		if (ret) {</div><div class='add'>+			nix_free_mce_list(mcast, new_count, elem-&gt;mce_start_index, elem-&gt;dir);</div><div class='add'>+			elem-&gt;mce_start_index = nix_alloc_mce_list(mcast, prev_count, elem-&gt;dir);</div><div class='add'>+			if (elem-&gt;mcam_index != -1)</div><div class='add'>+				npc_enable_mcam_entry(rvu, mcam,</div><div class='add'>+						      npc_blkaddr,</div><div class='add'>+						      elem-&gt;mcam_index,</div><div class='add'>+						      true);</div><div class='add'>+</div><div class='add'>+			goto unlock_mce;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (elem-&gt;mcam_index == -1) {</div><div class='add'>+		rsp-&gt;mce_start_index = elem-&gt;mce_start_index;</div><div class='add'>+		ret = 0;</div><div class='add'>+		goto unlock_mce;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nix_mcast_update_action(rvu, elem);</div><div class='add'>+	npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, elem-&gt;mcam_index, true);</div><div class='add'>+	rsp-&gt;mce_start_index = elem-&gt;mce_start_index;</div><div class='add'>+	ret = 0;</div><div class='add'>+</div><div class='add'>+unlock_mce:</div><div class='add'>+	mutex_unlock(&amp;mcast-&gt;mce_lock);</div><div class='add'>+</div><div class='add'>+unlock_grp:</div><div class='add'>+	if (!req-&gt;is_af)</div><div class='add'>+		mutex_unlock(&amp;mcast_grp-&gt;mcast_grp_lock);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c<br/>index 16cfc802e348..167145bdcb75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c</a></div><div class='hunk'>@@ -389,7 +389,13 @@ static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 	int bank, nixlf, index;</div><div class='ctx'> </div><div class='ctx'> 	/* get ucast entry rule entry index */</div><div class='del'>-	nix_get_nixlf(rvu, pf_func, &amp;nixlf, NULL);</div><div class='add'>+	if (nix_get_nixlf(rvu, pf_func, &amp;nixlf, NULL)) {</div><div class='add'>+		dev_err(rvu-&gt;dev, "%s: nixlf not attached to pcifunc:0x%x\n",</div><div class='add'>+			__func__, pf_func);</div><div class='add'>+		/* Action 0 is drop */</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf,</div><div class='ctx'> 					 NIXLF_UCAST_ENTRY);</div><div class='ctx'> 	bank = npc_get_bank(mcam, index);</div><div class='hunk'>@@ -589,8 +595,8 @@ static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 		    NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='del'>-			       int blkaddr, int index)</div><div class='add'>+u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='add'>+			int blkaddr, int index)</div><div class='ctx'> {</div><div class='ctx'> 	int bank = npc_get_bank(mcam, index);</div><div class='ctx'> </div><div class='hunk'>@@ -599,6 +605,16 @@ static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 			  NPC_AF_MCAMEX_BANKX_ACTION(index, bank));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='add'>+			 int blkaddr, int index, u64 cfg)</div><div class='add'>+{</div><div class='add'>+	int bank = npc_get_bank(mcam, index);</div><div class='add'>+</div><div class='add'>+	index &amp;= (mcam-&gt;banksize - 1);</div><div class='add'>+	return rvu_write64(rvu, blkaddr,</div><div class='add'>+			   NPC_AF_MCAMEX_BANKX_ACTION(index, bank), cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 				 int nixlf, u64 chan, u8 *mac_addr)</div><div class='ctx'> {</div><div class='hunk'>@@ -665,6 +681,7 @@ void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 	int blkaddr, ucast_idx, index;</div><div class='ctx'> 	struct nix_rx_action action = { 0 };</div><div class='ctx'> 	u64 relaxed_mask;</div><div class='add'>+	u8 flow_key_alg;</div><div class='ctx'> </div><div class='ctx'> 	if (!hw-&gt;cap.nix_rx_multicast &amp;&amp; is_cgx_vf(rvu, pcifunc))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -695,6 +712,8 @@ void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 		action.op = NIX_RX_ACTIONOP_UCAST;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	flow_key_alg = action.flow_key_alg;</div><div class='add'>+</div><div class='ctx'> 	/* RX_ACTION set to MCAST for CGX PF's */</div><div class='ctx'> 	if (hw-&gt;cap.nix_rx_multicast &amp;&amp; pfvf-&gt;use_mce_list &amp;&amp;</div><div class='ctx'> 	    is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {</div><div class='hunk'>@@ -734,7 +753,7 @@ void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 	req.vf = pcifunc;</div><div class='ctx'> 	req.index = action.index;</div><div class='ctx'> 	req.match_id = action.match_id;</div><div class='del'>-	req.flow_key_alg = action.flow_key_alg;</div><div class='add'>+	req.flow_key_alg = flow_key_alg;</div><div class='ctx'> </div><div class='ctx'> 	rvu_mbox_handler_npc_install_flow(rvu, &amp;req, &amp;rsp);</div><div class='ctx'> }</div><div class='hunk'>@@ -848,6 +867,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,</div><div class='ctx'> 	u8 mac_addr[ETH_ALEN] = { 0 };</div><div class='ctx'> 	struct nix_rx_action action = { 0 };</div><div class='ctx'> 	struct rvu_pfvf *pfvf;</div><div class='add'>+	u8 flow_key_alg;</div><div class='ctx'> 	u16 vf_func;</div><div class='ctx'> </div><div class='ctx'> 	/* Only CGX PF/VF can add allmulticast entry */</div><div class='hunk'>@@ -882,6 +902,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,</div><div class='ctx'> 		*(u64 *)&amp;action = npc_get_mcam_action(rvu, mcam,</div><div class='ctx'> 							blkaddr, ucast_idx);</div><div class='ctx'> </div><div class='add'>+	flow_key_alg = action.flow_key_alg;</div><div class='ctx'> 	if (action.op != NIX_RX_ACTIONOP_RSS) {</div><div class='ctx'> 		*(u64 *)&amp;action = 0;</div><div class='ctx'> 		action.op = NIX_RX_ACTIONOP_UCAST;</div><div class='hunk'>@@ -918,7 +939,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,</div><div class='ctx'> 	req.vf = pcifunc | vf_func;</div><div class='ctx'> 	req.index = action.index;</div><div class='ctx'> 	req.match_id = action.match_id;</div><div class='del'>-	req.flow_key_alg = action.flow_key_alg;</div><div class='add'>+	req.flow_key_alg = flow_key_alg;</div><div class='ctx'> </div><div class='ctx'> 	rvu_mbox_handler_npc_install_flow(rvu, &amp;req, &amp;rsp);</div><div class='ctx'> }</div><div class='hunk'>@@ -984,11 +1005,38 @@ static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam,</div><div class='ctx'> 	mutex_unlock(&amp;mcam-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action,</div><div class='add'>+					      struct rvu_pfvf *pfvf, int mcam_index, int blkaddr,</div><div class='add'>+					      int alg_idx)</div><div class='add'>+</div><div class='add'>+{</div><div class='add'>+	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='add'>+	struct rvu_hwinfo *hw = rvu-&gt;hw;</div><div class='add'>+	int bank, op_rss;</div><div class='add'>+</div><div class='add'>+	if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_index))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	op_rss = (!hw-&gt;cap.nix_rx_multicast || !pfvf-&gt;use_mce_list);</div><div class='add'>+</div><div class='add'>+	bank = npc_get_bank(mcam, mcam_index);</div><div class='add'>+	mcam_index &amp;= (mcam-&gt;banksize - 1);</div><div class='add'>+</div><div class='add'>+	/* If Rx action is MCAST update only RSS algorithm index */</div><div class='add'>+	if (!op_rss) {</div><div class='add'>+		*(u64 *)&amp;action = rvu_read64(rvu, blkaddr,</div><div class='add'>+				NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank));</div><div class='add'>+</div><div class='add'>+		action.flow_key_alg = alg_idx;</div><div class='add'>+	}</div><div class='add'>+	rvu_write64(rvu, blkaddr,</div><div class='add'>+		    NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&amp;action);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,</div><div class='ctx'> 				    int group, int alg_idx, int mcam_index)</div><div class='ctx'> {</div><div class='ctx'> 	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='del'>-	struct rvu_hwinfo *hw = rvu-&gt;hw;</div><div class='ctx'> 	struct nix_rx_action action;</div><div class='ctx'> 	int blkaddr, index, bank;</div><div class='ctx'> 	struct rvu_pfvf *pfvf;</div><div class='hunk'>@@ -1044,15 +1092,16 @@ void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,</div><div class='ctx'> 	/* If PF's promiscuous entry is enabled,</div><div class='ctx'> 	 * Set RSS action for that entry as well</div><div class='ctx'> 	 */</div><div class='del'>-	if ((!hw-&gt;cap.nix_rx_multicast || !pfvf-&gt;use_mce_list) &amp;&amp;</div><div class='del'>-	    is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {</div><div class='del'>-		bank = npc_get_bank(mcam, index);</div><div class='del'>-		index &amp;= (mcam-&gt;banksize - 1);</div><div class='add'>+	npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr,</div><div class='add'>+					  alg_idx);</div><div class='ctx'> </div><div class='del'>-		rvu_write64(rvu, blkaddr,</div><div class='del'>-			    NPC_AF_MCAMEX_BANKX_ACTION(index, bank),</div><div class='del'>-			    *(u64 *)&amp;action);</div><div class='del'>-	}</div><div class='add'>+	index = npc_get_nixlf_mcam_index(mcam, pcifunc,</div><div class='add'>+					 nixlf, NIXLF_ALLMULTI_ENTRY);</div><div class='add'>+	/* If PF's allmulti  entry is enabled,</div><div class='add'>+	 * Set RSS action for that entry as well</div><div class='add'>+	 */</div><div class='add'>+	npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr,</div><div class='add'>+					  alg_idx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,</div><div class='hunk'>@@ -1797,7 +1846,21 @@ static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)</div><div class='ctx'> 		npc_program_kpu_profile(rvu, blkaddr, idx, &amp;rvu-&gt;kpu.kpu[idx]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)</div><div class='add'>+void npc_mcam_rsrcs_deinit(struct rvu *rvu)</div><div class='add'>+{</div><div class='add'>+	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='add'>+</div><div class='add'>+	kfree(mcam-&gt;bmap);</div><div class='add'>+	kfree(mcam-&gt;bmap_reverse);</div><div class='add'>+	kfree(mcam-&gt;entry2pfvf_map);</div><div class='add'>+	kfree(mcam-&gt;cntr2pfvf_map);</div><div class='add'>+	kfree(mcam-&gt;entry2cntr_map);</div><div class='add'>+	kfree(mcam-&gt;cntr_refcnt);</div><div class='add'>+	kfree(mcam-&gt;entry2target_pffunc);</div><div class='add'>+	kfree(mcam-&gt;counters.bmap);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)</div><div class='ctx'> {</div><div class='ctx'> 	int nixlf_count = rvu_get_nixlf_count(rvu);</div><div class='ctx'> 	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='hunk'>@@ -1841,24 +1904,23 @@ static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)</div><div class='ctx'> 	mcam-&gt;pf_offset = mcam-&gt;nixlf_offset + nixlf_count;</div><div class='ctx'> </div><div class='ctx'> 	/* Allocate bitmaps for managing MCAM entries */</div><div class='del'>-	mcam-&gt;bmap = devm_kcalloc(rvu-&gt;dev, BITS_TO_LONGS(mcam-&gt;bmap_entries),</div><div class='del'>-				  sizeof(long), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;bmap = kmalloc_array(BITS_TO_LONGS(mcam-&gt;bmap_entries),</div><div class='add'>+				   sizeof(long), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;bmap)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	mcam-&gt;bmap_reverse = devm_kcalloc(rvu-&gt;dev,</div><div class='del'>-					  BITS_TO_LONGS(mcam-&gt;bmap_entries),</div><div class='del'>-					  sizeof(long), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;bmap_reverse = kmalloc_array(BITS_TO_LONGS(mcam-&gt;bmap_entries),</div><div class='add'>+					   sizeof(long), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;bmap_reverse)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+		goto free_bmap;</div><div class='ctx'> </div><div class='ctx'> 	mcam-&gt;bmap_fcnt = mcam-&gt;bmap_entries;</div><div class='ctx'> </div><div class='ctx'> 	/* Alloc memory for saving entry to RVU PFFUNC allocation mapping */</div><div class='del'>-	mcam-&gt;entry2pfvf_map = devm_kcalloc(rvu-&gt;dev, mcam-&gt;bmap_entries,</div><div class='del'>-					    sizeof(u16), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;entry2pfvf_map = kmalloc_array(mcam-&gt;bmap_entries,</div><div class='add'>+					     sizeof(u16), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;entry2pfvf_map)</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+		goto free_bmap_reverse;</div><div class='ctx'> </div><div class='ctx'> 	/* Reserve 1/8th of MCAM entries at the bottom for low priority</div><div class='ctx'> 	 * allocations and another 1/8th at the top for high priority</div><div class='hunk'>@@ -1877,31 +1939,31 @@ static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)</div><div class='ctx'> 	 */</div><div class='ctx'> 	err = rvu_alloc_bitmap(&amp;mcam-&gt;counters);</div><div class='ctx'> 	if (err)</div><div class='del'>-		return err;</div><div class='add'>+		goto free_entry_map;</div><div class='ctx'> </div><div class='del'>-	mcam-&gt;cntr2pfvf_map = devm_kcalloc(rvu-&gt;dev, mcam-&gt;counters.max,</div><div class='del'>-					   sizeof(u16), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;cntr2pfvf_map = kmalloc_array(mcam-&gt;counters.max,</div><div class='add'>+					    sizeof(u16), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;cntr2pfvf_map)</div><div class='del'>-		goto free_mem;</div><div class='add'>+		goto free_cntr_bmap;</div><div class='ctx'> </div><div class='ctx'> 	/* Alloc memory for MCAM entry to counter mapping and for tracking</div><div class='ctx'> 	 * counter's reference count.</div><div class='ctx'> 	 */</div><div class='del'>-	mcam-&gt;entry2cntr_map = devm_kcalloc(rvu-&gt;dev, mcam-&gt;bmap_entries,</div><div class='del'>-					    sizeof(u16), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;entry2cntr_map = kmalloc_array(mcam-&gt;bmap_entries,</div><div class='add'>+					     sizeof(u16), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;entry2cntr_map)</div><div class='del'>-		goto free_mem;</div><div class='add'>+		goto free_cntr_map;</div><div class='ctx'> </div><div class='del'>-	mcam-&gt;cntr_refcnt = devm_kcalloc(rvu-&gt;dev, mcam-&gt;counters.max,</div><div class='del'>-					 sizeof(u16), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;cntr_refcnt = kmalloc_array(mcam-&gt;counters.max,</div><div class='add'>+					  sizeof(u16), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;cntr_refcnt)</div><div class='del'>-		goto free_mem;</div><div class='add'>+		goto free_entry_cntr_map;</div><div class='ctx'> </div><div class='ctx'> 	/* Alloc memory for saving target device of mcam rule */</div><div class='del'>-	mcam-&gt;entry2target_pffunc = devm_kcalloc(rvu-&gt;dev, mcam-&gt;total_entries,</div><div class='del'>-						 sizeof(u16), GFP_KERNEL);</div><div class='add'>+	mcam-&gt;entry2target_pffunc = kmalloc_array(mcam-&gt;total_entries,</div><div class='add'>+						  sizeof(u16), GFP_KERNEL);</div><div class='ctx'> 	if (!mcam-&gt;entry2target_pffunc)</div><div class='del'>-		goto free_mem;</div><div class='add'>+		goto free_cntr_refcnt;</div><div class='ctx'> </div><div class='ctx'> 	for (index = 0; index &lt; mcam-&gt;bmap_entries; index++) {</div><div class='ctx'> 		mcam-&gt;entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;</div><div class='hunk'>@@ -1915,8 +1977,21 @@ static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-free_mem:</div><div class='add'>+free_cntr_refcnt:</div><div class='add'>+	kfree(mcam-&gt;cntr_refcnt);</div><div class='add'>+free_entry_cntr_map:</div><div class='add'>+	kfree(mcam-&gt;entry2cntr_map);</div><div class='add'>+free_cntr_map:</div><div class='add'>+	kfree(mcam-&gt;cntr2pfvf_map);</div><div class='add'>+free_cntr_bmap:</div><div class='ctx'> 	kfree(mcam-&gt;counters.bmap);</div><div class='add'>+free_entry_map:</div><div class='add'>+	kfree(mcam-&gt;entry2pfvf_map);</div><div class='add'>+free_bmap_reverse:</div><div class='add'>+	kfree(mcam-&gt;bmap_reverse);</div><div class='add'>+free_bmap:</div><div class='add'>+	kfree(mcam-&gt;bmap);</div><div class='add'>+</div><div class='ctx'> 	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2124,6 +2199,7 @@ void rvu_npc_freemem(struct rvu *rvu)</div><div class='ctx'> 	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='ctx'> </div><div class='ctx'> 	kfree(pkind-&gt;rsrc.bmap);</div><div class='add'>+	npc_mcam_rsrcs_deinit(rvu);</div><div class='ctx'> 	kfree(mcam-&gt;counters.bmap);</div><div class='ctx'> 	if (rvu-&gt;kpu_prfl_addr)</div><div class='ctx'> 		iounmap(rvu-&gt;kpu_prfl_addr);</div><div class='hunk'>@@ -2639,18 +2715,17 @@ int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,</div><div class='ctx'> 	rsp-&gt;entry = NPC_MCAM_ENTRY_INVALID;</div><div class='ctx'> 	rsp-&gt;free_count = 0;</div><div class='ctx'> </div><div class='del'>-	/* Check if ref_entry is within range */</div><div class='del'>-	if (req-&gt;priority &amp;&amp; req-&gt;ref_entry &gt;= mcam-&gt;bmap_entries) {</div><div class='del'>-		dev_err(rvu-&gt;dev, "%s: reference entry %d is out of range\n",</div><div class='del'>-			__func__, req-&gt;ref_entry);</div><div class='del'>-		return NPC_MCAM_INVALID_REQ;</div><div class='del'>-	}</div><div class='add'>+	/* Check if ref_entry is greater that the range</div><div class='add'>+	 * then set it to max value.</div><div class='add'>+	 */</div><div class='add'>+	if (req-&gt;ref_entry &gt; mcam-&gt;bmap_entries)</div><div class='add'>+		req-&gt;ref_entry = mcam-&gt;bmap_entries;</div><div class='ctx'> </div><div class='ctx'> 	/* ref_entry can't be '0' if requested priority is high.</div><div class='ctx'> 	 * Can't be last entry if requested priority is low.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if ((!req-&gt;ref_entry &amp;&amp; req-&gt;priority == NPC_MCAM_HIGHER_PRIO) ||</div><div class='del'>-	    ((req-&gt;ref_entry == (mcam-&gt;bmap_entries - 1)) &amp;&amp;</div><div class='add'>+	    ((req-&gt;ref_entry == mcam-&gt;bmap_entries) &amp;&amp;</div><div class='ctx'> 	     req-&gt;priority == NPC_MCAM_LOWER_PRIO))</div><div class='ctx'> 		return NPC_MCAM_INVALID_REQ;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c<br/>index 114e4ec21802..c75669c8fde7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c</a></div><div class='hunk'>@@ -51,6 +51,8 @@ static const char * const npc_flow_names[] = {</div><div class='ctx'> 	[NPC_MPLS3_TTL]     = "lse depth 3 ttl",</div><div class='ctx'> 	[NPC_MPLS4_LBTCBOS] = "lse depth 4 label tc bos",</div><div class='ctx'> 	[NPC_MPLS4_TTL]     = "lse depth 4",</div><div class='add'>+	[NPC_TYPE_ICMP] = "icmp type",</div><div class='add'>+	[NPC_CODE_ICMP] = "icmp code",</div><div class='ctx'> 	[NPC_UNKNOWN]	= "unknown",</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -526,6 +528,8 @@ do {									       \</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2);</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2);</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2);</div><div class='add'>+	NPC_SCAN_HDR(NPC_TYPE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 0, 1);</div><div class='add'>+	NPC_SCAN_HDR(NPC_CODE_ICMP, NPC_LID_LD, NPC_LT_LD_ICMP, 1, 1);</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2);</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2);</div><div class='ctx'> 	NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2);</div><div class='hunk'>@@ -555,7 +559,7 @@ static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)</div><div class='ctx'> {</div><div class='ctx'> 	struct npc_mcam *mcam = &amp;rvu-&gt;hw-&gt;mcam;</div><div class='ctx'> 	u64 *features = &amp;mcam-&gt;rx_features;</div><div class='del'>-	u64 tcp_udp_sctp;</div><div class='add'>+	u64 proto_flags;</div><div class='ctx'> 	int hdr;</div><div class='ctx'> </div><div class='ctx'> 	if (is_npc_intf_tx(intf))</div><div class='hunk'>@@ -566,18 +570,21 @@ static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf)</div><div class='ctx'> 			*features |= BIT_ULL(hdr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	tcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |</div><div class='add'>+	proto_flags = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) |</div><div class='ctx'> 		       BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) |</div><div class='del'>-		       BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP);</div><div class='add'>+		       BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) |</div><div class='add'>+		       BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP) |</div><div class='add'>+		       BIT_ULL(NPC_TYPE_ICMP) | BIT_ULL(NPC_CODE_ICMP);</div><div class='ctx'> </div><div class='ctx'> 	/* for tcp/udp/sctp corresponding layer type should be in the key */</div><div class='del'>-	if (*features &amp; tcp_udp_sctp) {</div><div class='add'>+	if (*features &amp; proto_flags) {</div><div class='ctx'> 		if (!npc_check_field(rvu, blkaddr, NPC_LD, intf))</div><div class='del'>-			*features &amp;= ~tcp_udp_sctp;</div><div class='add'>+			*features &amp;= ~proto_flags;</div><div class='ctx'> 		else</div><div class='ctx'> 			*features |= BIT_ULL(NPC_IPPROTO_TCP) |</div><div class='ctx'> 				     BIT_ULL(NPC_IPPROTO_UDP) |</div><div class='del'>-				     BIT_ULL(NPC_IPPROTO_SCTP);</div><div class='add'>+				     BIT_ULL(NPC_IPPROTO_SCTP) |</div><div class='add'>+				     BIT_ULL(NPC_IPPROTO_ICMP);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */</div><div class='hunk'>@@ -971,6 +978,10 @@ do {									      \</div><div class='ctx'> 		       ntohs(mask-&gt;sport), 0);</div><div class='ctx'> 	NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt-&gt;dport), 0,</div><div class='ctx'> 		       ntohs(mask-&gt;dport), 0);</div><div class='add'>+	NPC_WRITE_FLOW(NPC_TYPE_ICMP, icmp_type, pkt-&gt;icmp_type, 0,</div><div class='add'>+		       mask-&gt;icmp_type, 0);</div><div class='add'>+	NPC_WRITE_FLOW(NPC_CODE_ICMP, icmp_code, pkt-&gt;icmp_code, 0,</div><div class='add'>+		       mask-&gt;icmp_code, 0);</div><div class='ctx'> </div><div class='ctx'> 	NPC_WRITE_FLOW(NPC_IPSEC_SPI, spi, ntohl(pkt-&gt;spi), 0,</div><div class='ctx'> 		       ntohl(mask-&gt;spi), 0);</div><div class='hunk'>@@ -1106,13 +1117,40 @@ static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='del'>-				struct mcam_entry *entry,</div><div class='del'>-				struct npc_install_flow_req *req,</div><div class='del'>-				u16 target, bool pf_set_vfs_mac)</div><div class='add'>+static int npc_mcast_update_action_index(struct rvu *rvu, struct npc_install_flow_req *req,</div><div class='add'>+					 u64 op, void *action)</div><div class='add'>+{</div><div class='add'>+	int mce_index;</div><div class='add'>+</div><div class='add'>+	/* If a PF/VF is installing a multicast rule then it is expected</div><div class='add'>+	 * that the PF/VF should have created a group for the multicast/mirror</div><div class='add'>+	 * list. Otherwise reject the configuration.</div><div class='add'>+	 * During this scenario, req-&gt;index is set as multicast/mirror</div><div class='add'>+	 * group index.</div><div class='add'>+	 */</div><div class='add'>+	if (req-&gt;hdr.pcifunc &amp;&amp;</div><div class='add'>+	    (op == NIX_RX_ACTIONOP_MCAST || op == NIX_TX_ACTIONOP_MCAST)) {</div><div class='add'>+		mce_index = rvu_nix_mcast_get_mce_index(rvu, req-&gt;hdr.pcifunc, req-&gt;index);</div><div class='add'>+		if (mce_index &lt; 0)</div><div class='add'>+			return mce_index;</div><div class='add'>+</div><div class='add'>+		if (op == NIX_RX_ACTIONOP_MCAST)</div><div class='add'>+			((struct nix_rx_action *)action)-&gt;index = mce_index;</div><div class='add'>+		else</div><div class='add'>+			((struct nix_tx_action *)action)-&gt;index = mce_index;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='add'>+			       struct mcam_entry *entry,</div><div class='add'>+			       struct npc_install_flow_req *req,</div><div class='add'>+			       u16 target, bool pf_set_vfs_mac)</div><div class='ctx'> {</div><div class='ctx'> 	struct rvu_switch *rswitch = &amp;rvu-&gt;rswitch;</div><div class='ctx'> 	struct nix_rx_action action;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (rswitch-&gt;mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &amp;&amp; pf_set_vfs_mac)</div><div class='ctx'> 		req-&gt;chan_mask = 0x0; /* Do not care channel */</div><div class='hunk'>@@ -1124,6 +1162,11 @@ static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='ctx'> 	action.pf_func = target;</div><div class='ctx'> 	action.op = req-&gt;op;</div><div class='ctx'> 	action.index = req-&gt;index;</div><div class='add'>+</div><div class='add'>+	ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&amp;action);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	action.match_id = req-&gt;match_id;</div><div class='ctx'> 	action.flow_key_alg = req-&gt;flow_key_alg;</div><div class='ctx'> </div><div class='hunk'>@@ -1155,14 +1198,17 @@ static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='ctx'> 			     FIELD_PREP(RX_VTAG1_TYPE_MASK, req-&gt;vtag1_type) |</div><div class='ctx'> 			     FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) |</div><div class='ctx'> 			     FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='del'>-				struct mcam_entry *entry,</div><div class='del'>-				struct npc_install_flow_req *req, u16 target)</div><div class='add'>+static int npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='add'>+			       struct mcam_entry *entry,</div><div class='add'>+			       struct npc_install_flow_req *req, u16 target)</div><div class='ctx'> {</div><div class='ctx'> 	struct nix_tx_action action;</div><div class='ctx'> 	u64 mask = ~0ULL;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	/* If AF is installing then do not care about</div><div class='ctx'> 	 * PF_FUNC in Send Descriptor</div><div class='hunk'>@@ -1176,6 +1222,11 @@ static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='ctx'> 	*(u64 *)&amp;action = 0x00;</div><div class='ctx'> 	action.op = req-&gt;op;</div><div class='ctx'> 	action.index = req-&gt;index;</div><div class='add'>+</div><div class='add'>+	ret = npc_mcast_update_action_index(rvu, req, action.op, (void *)&amp;action);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	action.match_id = req-&gt;match_id;</div><div class='ctx'> </div><div class='ctx'> 	entry-&gt;action = *(u64 *)&amp;action;</div><div class='hunk'>@@ -1191,6 +1242,8 @@ static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf,</div><div class='ctx'> 			     FIELD_PREP(TX_VTAG1_OP_MASK, req-&gt;vtag1_op) |</div><div class='ctx'> 			     FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) |</div><div class='ctx'> 			     FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target,</div><div class='hunk'>@@ -1220,10 +1273,15 @@ static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target,</div><div class='ctx'> 	npc_update_flow(rvu, entry, features, &amp;req-&gt;packet, &amp;req-&gt;mask, &amp;dummy,</div><div class='ctx'> 			req-&gt;intf, blkaddr);</div><div class='ctx'> </div><div class='del'>-	if (is_npc_intf_rx(req-&gt;intf))</div><div class='del'>-		npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac);</div><div class='del'>-	else</div><div class='del'>-		npc_update_tx_entry(rvu, pfvf, entry, req, target);</div><div class='add'>+	if (is_npc_intf_rx(req-&gt;intf)) {</div><div class='add'>+		err = npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	} else {</div><div class='add'>+		err = npc_update_tx_entry(rvu, pfvf, entry, req, target);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Default unicast rules do not exist for TX */</div><div class='ctx'> 	if (is_npc_intf_tx(req-&gt;intf))</div><div class='hunk'>@@ -1340,6 +1398,10 @@ find_rule:</div><div class='ctx'> 		return rvu_nix_setup_ratelimit_aggr(rvu, req-&gt;hdr.pcifunc,</div><div class='ctx'> 					     req-&gt;index, req-&gt;match_id);</div><div class='ctx'> </div><div class='add'>+	if (owner &amp;&amp; req-&gt;op == NIX_RX_ACTIONOP_MCAST)</div><div class='add'>+		return rvu_nix_mcast_update_mcam_entry(rvu, req-&gt;hdr.pcifunc,</div><div class='add'>+						       req-&gt;index, entry_index);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c<br/>index b3150f053291..d46ac29adb96 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c</a></div><div class='hunk'>@@ -31,8 +31,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {</div><div class='ctx'> 	{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},</div><div class='ctx'> 			      {0x1200, 0x12E0} } },</div><div class='ctx'> 	{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},</div><div class='del'>-			      {0x1610, 0x1618}, {0x1700, 0x17B0} } },</div><div class='del'>-	{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },</div><div class='add'>+			      {0x1610, 0x1618}, {0x1700, 0x17C8} } },</div><div class='add'>+	{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },</div><div class='ctx'> 	{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h<br/>index b42e631e52d0..6f73ad9807f0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h</a></div><div class='hunk'>@@ -437,6 +437,7 @@</div><div class='ctx'> </div><div class='ctx'> #define NIX_AF_LINKX_BASE_MASK		GENMASK_ULL(11, 0)</div><div class='ctx'> #define NIX_AF_LINKX_RANGE_MASK		GENMASK_ULL(19, 16)</div><div class='add'>+#define NIX_AF_LINKX_MCS_CNT_MASK	GENMASK_ULL(33, 32)</div><div class='ctx'> </div><div class='ctx'> /* SSO */</div><div class='ctx'> #define SSO_AF_CONST			(0x1000)</div><div class='hunk'>@@ -733,5 +734,7 @@</div><div class='ctx'> #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT	23</div><div class='ctx'> #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT		22</div><div class='ctx'> #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT	21</div><div class='add'>+#define LMTST_THROTTLE_MASK		GENMASK_ULL(38, 35)</div><div class='add'>+#define LMTST_WR_PEND_MAX		15</div><div class='ctx'> </div><div class='ctx'> #endif /* RVU_REG_H */</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h<br/>index edc9367b1b95..5ef406c7e8a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h</a></div><div class='hunk'>@@ -340,11 +340,12 @@ struct nix_aq_res_s {</div><div class='ctx'> /* NIX Completion queue context structure */</div><div class='ctx'> struct nix_cq_ctx_s {</div><div class='ctx'> 	u64 base;</div><div class='del'>-	u64 rsvd_64_67		: 4;</div><div class='add'>+	u64 lbp_ena             : 1;</div><div class='add'>+	u64 lbpid_low           : 3;</div><div class='ctx'> 	u64 bp_ena		: 1;</div><div class='del'>-	u64 rsvd_69_71		: 3;</div><div class='add'>+	u64 lbpid_med           : 3;</div><div class='ctx'> 	u64 bpid		: 9;</div><div class='del'>-	u64 rsvd_81_83		: 3;</div><div class='add'>+	u64 lbpid_high          : 3;</div><div class='ctx'> 	u64 qint_idx		: 7;</div><div class='ctx'> 	u64 cq_err		: 1;</div><div class='ctx'> 	u64 cint_idx		: 7;</div><div class='hunk'>@@ -358,10 +359,14 @@ struct nix_cq_ctx_s {</div><div class='ctx'> 	u64 drop		: 8;</div><div class='ctx'> 	u64 drop_ena		: 1;</div><div class='ctx'> 	u64 ena			: 1;</div><div class='del'>-	u64 rsvd_210_211	: 2;</div><div class='del'>-	u64 substream		: 20;</div><div class='add'>+	u64 cpt_drop_err_en     : 1;</div><div class='add'>+	u64 rsvd_211	        : 1;</div><div class='add'>+	u64 substream           : 12;</div><div class='add'>+	u64 stash_thresh        : 4;</div><div class='add'>+	u64 lbp_frac            : 4;</div><div class='ctx'> 	u64 caching		: 1;</div><div class='del'>-	u64 rsvd_233_235	: 3;</div><div class='add'>+	u64 stashing            : 1;</div><div class='add'>+	u64 rsvd_234_235	: 2;</div><div class='ctx'> 	u64 qsize		: 4;</div><div class='ctx'> 	u64 cq_err_int		: 8;</div><div class='ctx'> 	u64 cq_err_int_ena	: 8;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c<br/>index a4a258da8dd5..c1c99d7054f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c</a></div><div class='hunk'>@@ -450,6 +450,9 @@ int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile,</div><div class='ctx'> 	aq-&gt;prof.pebs_mantissa = 0;</div><div class='ctx'> 	aq-&gt;prof_mask.pebs_mantissa = 0xFF;</div><div class='ctx'> </div><div class='add'>+	aq-&gt;prof.hl_en = 0;</div><div class='add'>+	aq-&gt;prof_mask.hl_en = 1;</div><div class='add'>+</div><div class='ctx'> 	/* Fill AQ info */</div><div class='ctx'> 	aq-&gt;qidx = profile;</div><div class='ctx'> 	aq-&gt;ctype = NIX_AQ_CTYPE_BANDPROF;</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h<br/>index e7c69b57147e..06910307085e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h</a></div><div class='hunk'>@@ -1070,6 +1070,8 @@ int otx2_init_tc(struct otx2_nic *nic);</div><div class='ctx'> void otx2_shutdown_tc(struct otx2_nic *nic);</div><div class='ctx'> int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,</div><div class='ctx'> 		  void *type_data);</div><div class='add'>+void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic);</div><div class='add'>+</div><div class='ctx'> /* CGX/RPM DMAC filters support */</div><div class='ctx'> int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);</div><div class='ctx'> int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos);</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c<br/>index bfddbff7bcdf..28fb643d2917 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c</a></div><div class='hunk'>@@ -399,9 +399,10 @@ static int otx2_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc)</div><div class='ctx'> static int otx2_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)</div><div class='ctx'> {</div><div class='ctx'> 	struct otx2_nic *pfvf = netdev_priv(dev);</div><div class='add'>+	u8 old_pfc_en;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	/* Save PFC configuration to interface */</div><div class='add'>+	old_pfc_en = pfvf-&gt;pfc_en;</div><div class='ctx'> 	pfvf-&gt;pfc_en = pfc-&gt;pfc_en;</div><div class='ctx'> </div><div class='ctx'> 	if (pfvf-&gt;hw.tx_queues &gt;= NIX_PF_PFC_PRIO_MAX)</div><div class='hunk'>@@ -411,13 +412,17 @@ static int otx2_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)</div><div class='ctx'> 	 * supported by the tx queue configuration</div><div class='ctx'> 	 */</div><div class='ctx'> 	err = otx2_check_pfc_config(pfvf);</div><div class='del'>-	if (err)</div><div class='add'>+	if (err) {</div><div class='add'>+		pfvf-&gt;pfc_en = old_pfc_en;</div><div class='ctx'> 		return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> process_pfc:</div><div class='ctx'> 	err = otx2_config_priority_flow_ctrl(pfvf);</div><div class='del'>-	if (err)</div><div class='add'>+	if (err) {</div><div class='add'>+		pfvf-&gt;pfc_en = old_pfc_en;</div><div class='ctx'> 		return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Request Per channel Bpids */</div><div class='ctx'> 	if (pfc-&gt;pfc_en)</div><div class='hunk'>@@ -425,6 +430,12 @@ process_pfc:</div><div class='ctx'> </div><div class='ctx'> 	err = otx2_pfc_txschq_update(pfvf);</div><div class='ctx'> 	if (err) {</div><div class='add'>+		if (pfc-&gt;pfc_en)</div><div class='add'>+			otx2_nix_config_bp(pfvf, false);</div><div class='add'>+</div><div class='add'>+		otx2_pfc_txschq_stop(pfvf);</div><div class='add'>+		pfvf-&gt;pfc_en = old_pfc_en;</div><div class='add'>+		otx2_config_priority_flow_ctrl(pfvf);</div><div class='ctx'> 		dev_err(pfvf-&gt;dev, "%s failed to update TX schedulers\n", __func__);</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c<br/>index 9efcec549834..2928898c7f8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c</a></div><div class='hunk'>@@ -334,9 +334,12 @@ static void otx2_get_pauseparam(struct net_device *netdev,</div><div class='ctx'> 	if (is_otx2_lbkvf(pfvf-&gt;pdev))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	mutex_lock(&amp;pfvf-&gt;mbox.lock);</div><div class='ctx'> 	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&amp;pfvf-&gt;mbox);</div><div class='del'>-	if (!req)</div><div class='add'>+	if (!req) {</div><div class='add'>+		mutex_unlock(&amp;pfvf-&gt;mbox.lock);</div><div class='ctx'> 		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (!otx2_sync_mbox_msg(&amp;pfvf-&gt;mbox)) {</div><div class='ctx'> 		rsp = (struct cgx_pause_frm_cfg *)</div><div class='hunk'>@@ -344,6 +347,7 @@ static void otx2_get_pauseparam(struct net_device *netdev,</div><div class='ctx'> 		pause-&gt;rx_pause = rsp-&gt;rx_pause;</div><div class='ctx'> 		pause-&gt;tx_pause = rsp-&gt;tx_pause;</div><div class='ctx'> 	}</div><div class='add'>+	mutex_unlock(&amp;pfvf-&gt;mbox.lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int otx2_set_pauseparam(struct net_device *netdev,</div><div class='hunk'>@@ -831,21 +835,26 @@ static int otx2_rss_ctx_create(struct otx2_nic *pfvf,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* RSS context configuration */</div><div class='del'>-static int otx2_set_rxfh_context(struct net_device *dev, const u32 *indir,</div><div class='del'>-				 const u8 *hkey, const u8 hfunc,</div><div class='del'>-				 u32 *rss_context, bool delete)</div><div class='add'>+/* Configure RSS table and hash key */</div><div class='add'>+static int otx2_set_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='add'>+	u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP;</div><div class='ctx'> 	struct otx2_nic *pfvf = netdev_priv(dev);</div><div class='ctx'> 	struct otx2_rss_ctx *rss_ctx;</div><div class='ctx'> 	struct otx2_rss_info *rss;</div><div class='ctx'> 	int ret, idx;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (*rss_context != ETH_RXFH_CONTEXT_ALLOC &amp;&amp;</div><div class='del'>-	    *rss_context &gt;= MAX_RSS_GROUPS)</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		rss_context = rxfh-&gt;rss_context;</div><div class='add'>+</div><div class='add'>+	if (rss_context != ETH_RXFH_CONTEXT_ALLOC &amp;&amp;</div><div class='add'>+	    rss_context &gt;= MAX_RSS_GROUPS)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	rss = &amp;pfvf-&gt;hw.rss_info;</div><div class='hunk'>@@ -855,40 +864,45 @@ static int otx2_set_rxfh_context(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 		return -EIO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hkey) {</div><div class='del'>-		memcpy(rss-&gt;key, hkey, sizeof(rss-&gt;key));</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(rss-&gt;key, rxfh-&gt;key, sizeof(rss-&gt;key));</div><div class='ctx'> 		otx2_set_rss_key(pfvf);</div><div class='ctx'> 	}</div><div class='del'>-	if (delete)</div><div class='del'>-		return otx2_rss_ctx_delete(pfvf, *rss_context);</div><div class='add'>+	if (rxfh-&gt;rss_delete)</div><div class='add'>+		return otx2_rss_ctx_delete(pfvf, rss_context);</div><div class='ctx'> </div><div class='del'>-	if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {</div><div class='del'>-		ret = otx2_rss_ctx_create(pfvf, rss_context);</div><div class='add'>+	if (rss_context == ETH_RXFH_CONTEXT_ALLOC) {</div><div class='add'>+		ret = otx2_rss_ctx_create(pfvf, &amp;rss_context);</div><div class='add'>+		rxfh-&gt;rss_context = rss_context;</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='del'>-	if (indir) {</div><div class='del'>-		rss_ctx = rss-&gt;rss_ctx[*rss_context];</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='add'>+		rss_ctx = rss-&gt;rss_ctx[rss_context];</div><div class='ctx'> 		for (idx = 0; idx &lt; rss-&gt;rss_size; idx++)</div><div class='del'>-			rss_ctx-&gt;ind_tbl[idx] = indir[idx];</div><div class='add'>+			rss_ctx-&gt;ind_tbl[idx] = rxfh-&gt;indir[idx];</div><div class='ctx'> 	}</div><div class='del'>-	otx2_set_rss_table(pfvf, *rss_context);</div><div class='add'>+	otx2_set_rss_table(pfvf, rss_context);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int otx2_get_rxfh_context(struct net_device *dev, u32 *indir,</div><div class='del'>-				 u8 *hkey, u8 *hfunc, u32 rss_context)</div><div class='add'>+/* Get RSS configuration */</div><div class='add'>+static int otx2_get_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='add'>+	u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP;</div><div class='ctx'> 	struct otx2_nic *pfvf = netdev_priv(dev);</div><div class='ctx'> 	struct otx2_rss_ctx *rss_ctx;</div><div class='ctx'> 	struct otx2_rss_info *rss;</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='ctx'> 	int idx, rx_queues;</div><div class='ctx'> </div><div class='ctx'> 	rss = &amp;pfvf-&gt;hw.rss_info;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		rss_context = rxfh-&gt;rss_context;</div><div class='ctx'> </div><div class='ctx'> 	if (!indir)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -910,30 +924,12 @@ static int otx2_get_rxfh_context(struct net_device *dev, u32 *indir,</div><div class='ctx'> 		for (idx = 0; idx &lt; rss-&gt;rss_size; idx++)</div><div class='ctx'> 			indir[idx] = rss_ctx-&gt;ind_tbl[idx];</div><div class='ctx'> 	}</div><div class='del'>-	if (hkey)</div><div class='del'>-		memcpy(hkey, rss-&gt;key, sizeof(rss-&gt;key));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, rss-&gt;key, sizeof(rss-&gt;key));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* Get RSS configuration */</div><div class='del'>-static int otx2_get_rxfh(struct net_device *dev, u32 *indir,</div><div class='del'>-			 u8 *hkey, u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	return otx2_get_rxfh_context(dev, indir, hkey, hfunc,</div><div class='del'>-				     DEFAULT_RSS_CONTEXT_GROUP);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Configure RSS table and hash key */</div><div class='del'>-static int otx2_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			 const u8 *hkey, const u8 hfunc)</div><div class='del'>-{</div><div class='del'>-</div><div class='del'>-	u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP;</div><div class='del'>-</div><div class='del'>-	return otx2_set_rxfh_context(dev, indir, hkey, hfunc, &amp;rss_context, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static u32 otx2_get_msglevel(struct net_device *netdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct otx2_nic *pfvf = netdev_priv(netdev);</div><div class='hunk'>@@ -1314,6 +1310,7 @@ static void otx2_get_fec_stats(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops otx2_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_MAX_FRAMES |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE,</div><div class='hunk'>@@ -1336,8 +1333,6 @@ static const struct ethtool_ops otx2_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_indir_size	= otx2_get_rxfh_indir_size,</div><div class='ctx'> 	.get_rxfh		= otx2_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= otx2_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= otx2_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= otx2_set_rxfh_context,</div><div class='ctx'> 	.get_msglevel		= otx2_get_msglevel,</div><div class='ctx'> 	.set_msglevel		= otx2_set_msglevel,</div><div class='ctx'> 	.get_pauseparam		= otx2_get_pauseparam,</div><div class='hunk'>@@ -1437,6 +1432,7 @@ static int otx2vf_get_link_ksettings(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops otx2vf_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_MAX_FRAMES |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE,</div><div class='hunk'>@@ -1455,8 +1451,6 @@ static const struct ethtool_ops otx2vf_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_indir_size	= otx2_get_rxfh_indir_size,</div><div class='ctx'> 	.get_rxfh		= otx2_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= otx2_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= otx2_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= otx2_set_rxfh_context,</div><div class='ctx'> 	.get_ringparam		= otx2_get_ringparam,</div><div class='ctx'> 	.set_ringparam		= otx2_set_ringparam,</div><div class='ctx'> 	.get_coalesce		= otx2_get_coalesce,</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c<br/>index ba95ac913274..a57455aebff6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c</a></div><div class='hunk'>@@ -566,7 +566,9 @@ static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)</div><div class='ctx'> 		otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);</div><div class='ctx'> 		otx2_queue_work(mbox, pf-&gt;mbox_pfvf_wq, 64, vfs, intr,</div><div class='ctx'> 				TYPE_PFVF);</div><div class='del'>-		vfs -= 64;</div><div class='add'>+		if (intr)</div><div class='add'>+			trace_otx2_msg_interrupt(mbox-&gt;mbox.pdev, "VF(s) to PF", intr);</div><div class='add'>+		vfs = 64;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));</div><div class='hunk'>@@ -574,7 +576,8 @@ static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)</div><div class='ctx'> </div><div class='ctx'> 	otx2_queue_work(mbox, pf-&gt;mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);</div><div class='ctx'> </div><div class='del'>-	trace_otx2_msg_interrupt(mbox-&gt;mbox.pdev, "VF(s) to PF", intr);</div><div class='add'>+	if (intr)</div><div class='add'>+		trace_otx2_msg_interrupt(mbox-&gt;mbox.pdev, "VF(s) to PF", intr);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='hunk'>@@ -1647,6 +1650,21 @@ static void otx2_free_hw_resources(struct otx2_nic *pf)</div><div class='ctx'> 	mutex_unlock(&amp;mbox-&gt;lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf)</div><div class='add'>+{</div><div class='add'>+	int vf;</div><div class='add'>+</div><div class='add'>+	/* The AF driver will determine whether to allow the VF netdev or not */</div><div class='add'>+	if (is_otx2_vf(pfvf-&gt;pcifunc))</div><div class='add'>+		return true;</div><div class='add'>+</div><div class='add'>+	/* check if there are any trusted VFs associated with the PF netdev */</div><div class='add'>+	for (vf = 0; vf &lt; pci_num_vf(pfvf-&gt;pdev); vf++)</div><div class='add'>+		if (pfvf-&gt;vf_configs[vf].trusted)</div><div class='add'>+			return true;</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void otx2_do_set_rx_mode(struct otx2_nic *pf)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *netdev = pf-&gt;netdev;</div><div class='hunk'>@@ -1679,12 +1697,21 @@ static void otx2_do_set_rx_mode(struct otx2_nic *pf)</div><div class='ctx'> 	if (netdev-&gt;flags &amp; (IFF_ALLMULTI | IFF_MULTICAST))</div><div class='ctx'> 		req-&gt;mode |= NIX_RX_MODE_ALLMULTI;</div><div class='ctx'> </div><div class='del'>-	req-&gt;mode |= NIX_RX_MODE_USE_MCE;</div><div class='add'>+	if (otx2_promisc_use_mce_list(pf))</div><div class='add'>+		req-&gt;mode |= NIX_RX_MODE_USE_MCE;</div><div class='ctx'> </div><div class='ctx'> 	otx2_sync_mbox_msg(&amp;pf-&gt;mbox);</div><div class='ctx'> 	mutex_unlock(&amp;pf-&gt;mbox.lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void otx2_set_irq_coalesce(struct otx2_nic *pfvf)</div><div class='add'>+{</div><div class='add'>+	int cint;</div><div class='add'>+</div><div class='add'>+	for (cint = 0; cint &lt; pfvf-&gt;hw.cint_cnt; cint++)</div><div class='add'>+		otx2_config_irq_coalescing(pfvf, cint);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void otx2_dim_work(struct work_struct *w)</div><div class='ctx'> {</div><div class='ctx'> 	struct dim_cq_moder cur_moder;</div><div class='hunk'>@@ -1700,6 +1727,7 @@ static void otx2_dim_work(struct work_struct *w)</div><div class='ctx'> 		CQ_TIMER_THRESH_MAX : cur_moder.usec;</div><div class='ctx'> 	pfvf-&gt;hw.cq_ecount_wait = (cur_moder.pkts &gt; NAPI_POLL_WEIGHT) ?</div><div class='ctx'> 		NAPI_POLL_WEIGHT : cur_moder.pkts;</div><div class='add'>+	otx2_set_irq_coalesce(pfvf);</div><div class='ctx'> 	dim-&gt;state = DIM_START_MEASURE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1870,6 +1898,8 @@ int otx2_open(struct net_device *netdev)</div><div class='ctx'> 	if (pf-&gt;flags &amp; OTX2_FLAG_DMACFLTR_SUPPORT)</div><div class='ctx'> 		otx2_dmacflt_reinstall_flows(pf);</div><div class='ctx'> </div><div class='add'>+	otx2_tc_apply_ingress_police_rules(pf);</div><div class='add'>+</div><div class='ctx'> 	err = otx2_rxtx_enable(pf, true);</div><div class='ctx'> 	/* If a mbox communication error happens at this point then interface</div><div class='ctx'> 	 * will end up in a state such that it is in down state but hardware</div><div class='hunk'>@@ -2677,11 +2707,14 @@ static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf,</div><div class='ctx'> 	pf-&gt;vf_configs[vf].trusted = enable;</div><div class='ctx'> 	rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);</div><div class='ctx'> </div><div class='del'>-	if (rc)</div><div class='add'>+	if (rc) {</div><div class='ctx'> 		pf-&gt;vf_configs[vf].trusted = !enable;</div><div class='del'>-	else</div><div class='add'>+	} else {</div><div class='ctx'> 		netdev_info(pf-&gt;netdev, "VF %d is %strusted\n",</div><div class='ctx'> 			    vf, enable ? "" : "not ");</div><div class='add'>+		otx2_set_rx_mode(netdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c<br/>index 8a5e3987a482..4fd44b6eecea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c</a></div><div class='hunk'>@@ -29,6 +29,8 @@</div><div class='ctx'> </div><div class='ctx'> #define OTX2_UNSUPP_LSE_DEPTH		GENMASK(6, 4)</div><div class='ctx'> </div><div class='add'>+#define MCAST_INVALID_GRP		(-1U)</div><div class='add'>+</div><div class='ctx'> struct otx2_tc_flow_stats {</div><div class='ctx'> 	u64 bytes;</div><div class='ctx'> 	u64 pkts;</div><div class='hunk'>@@ -47,6 +49,10 @@ struct otx2_tc_flow {</div><div class='ctx'> 	bool				is_act_police;</div><div class='ctx'> 	u32				prio;</div><div class='ctx'> 	struct npc_install_flow_req	req;</div><div class='add'>+	u32				mcast_grp_idx;</div><div class='add'>+	u64				rate;</div><div class='add'>+	u32				burst;</div><div class='add'>+	bool				is_pps;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void otx2_get_egress_burst_cfg(struct otx2_nic *nic, u32 burst,</div><div class='hunk'>@@ -284,6 +290,41 @@ static int otx2_tc_egress_matchall_delete(struct otx2_nic *nic,</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int otx2_tc_act_set_hw_police(struct otx2_nic *nic,</div><div class='add'>+				     struct otx2_tc_flow *node)</div><div class='add'>+{</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+</div><div class='add'>+	rc = cn10k_alloc_leaf_profile(nic, &amp;node-&gt;leaf_profile);</div><div class='add'>+	if (rc) {</div><div class='add'>+		mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+		return rc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rc = cn10k_set_ipolicer_rate(nic, node-&gt;leaf_profile,</div><div class='add'>+				     node-&gt;burst, node-&gt;rate, node-&gt;is_pps);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto free_leaf;</div><div class='add'>+</div><div class='add'>+	rc = cn10k_map_unmap_rq_policer(nic, node-&gt;rq, node-&gt;leaf_profile, true);</div><div class='add'>+	if (rc)</div><div class='add'>+		goto free_leaf;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+free_leaf:</div><div class='add'>+	if (cn10k_free_leaf_profile(nic, node-&gt;leaf_profile))</div><div class='add'>+		netdev_err(nic-&gt;netdev,</div><div class='add'>+			   "Unable to free leaf bandwidth profile(%d)\n",</div><div class='add'>+			   node-&gt;leaf_profile);</div><div class='add'>+	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int otx2_tc_act_set_police(struct otx2_nic *nic,</div><div class='ctx'> 				  struct otx2_tc_flow *node,</div><div class='ctx'> 				  struct flow_cls_offload *f,</div><div class='hunk'>@@ -300,38 +341,92 @@ static int otx2_tc_act_set_police(struct otx2_nic *nic,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	req-&gt;match_id = mark &amp; 0xFFFFULL;</div><div class='add'>+	req-&gt;index = rq_idx;</div><div class='add'>+	req-&gt;op = NIX_RX_ACTIONOP_UCAST;</div><div class='add'>+</div><div class='add'>+	node-&gt;is_act_police = true;</div><div class='add'>+	node-&gt;rq = rq_idx;</div><div class='add'>+	node-&gt;burst = burst;</div><div class='add'>+	node-&gt;rate = rate;</div><div class='add'>+	node-&gt;is_pps = pps;</div><div class='add'>+</div><div class='add'>+	rc = otx2_tc_act_set_hw_police(nic, node);</div><div class='add'>+	if (!rc)</div><div class='add'>+		set_bit(rq_idx, &amp;nic-&gt;rq_bmap);</div><div class='add'>+</div><div class='add'>+	return rc;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int otx2_tc_update_mcast(struct otx2_nic *nic,</div><div class='add'>+				struct npc_install_flow_req *req,</div><div class='add'>+				struct netlink_ext_ack *extack,</div><div class='add'>+				struct otx2_tc_flow *node,</div><div class='add'>+				struct nix_mcast_grp_update_req *ureq,</div><div class='add'>+				u8 num_intf)</div><div class='add'>+{</div><div class='add'>+	struct nix_mcast_grp_update_req *grp_update_req;</div><div class='add'>+	struct nix_mcast_grp_create_req *creq;</div><div class='add'>+	struct nix_mcast_grp_create_rsp *crsp;</div><div class='add'>+	u32 grp_index;</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+	creq = otx2_mbox_alloc_msg_nix_mcast_grp_create(&amp;nic-&gt;mbox);</div><div class='add'>+	if (!creq) {</div><div class='add'>+		rc = -ENOMEM;</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	rc = cn10k_alloc_leaf_profile(nic, &amp;node-&gt;leaf_profile);</div><div class='add'>+	creq-&gt;dir = NIX_MCAST_INGRESS;</div><div class='add'>+	/* Send message to AF */</div><div class='add'>+	rc = otx2_sync_mbox_msg(&amp;nic-&gt;mbox);</div><div class='ctx'> 	if (rc) {</div><div class='del'>-		mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='del'>-		return rc;</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Failed to create multicast group");</div><div class='add'>+		goto error;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	rc = cn10k_set_ipolicer_rate(nic, node-&gt;leaf_profile, burst, rate, pps);</div><div class='del'>-	if (rc)</div><div class='del'>-		goto free_leaf;</div><div class='add'>+	crsp = (struct nix_mcast_grp_create_rsp *)otx2_mbox_get_rsp(&amp;nic-&gt;mbox.mbox,</div><div class='add'>+			0,</div><div class='add'>+			&amp;creq-&gt;hdr);</div><div class='add'>+	if (IS_ERR(crsp)) {</div><div class='add'>+		rc = PTR_ERR(crsp);</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	rc = cn10k_map_unmap_rq_policer(nic, rq_idx, node-&gt;leaf_profile, true);</div><div class='del'>-	if (rc)</div><div class='del'>-		goto free_leaf;</div><div class='add'>+	grp_index = crsp-&gt;mcast_grp_idx;</div><div class='add'>+	grp_update_req = otx2_mbox_alloc_msg_nix_mcast_grp_update(&amp;nic-&gt;mbox);</div><div class='add'>+	if (!grp_update_req) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Failed to update multicast group");</div><div class='add'>+		rc = -ENOMEM;</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+	ureq-&gt;op = NIX_MCAST_OP_ADD_ENTRY;</div><div class='add'>+	ureq-&gt;mcast_grp_idx = grp_index;</div><div class='add'>+	ureq-&gt;num_mce_entry = num_intf;</div><div class='add'>+	ureq-&gt;pcifunc[0] = nic-&gt;pcifunc;</div><div class='add'>+	ureq-&gt;channel[0] = nic-&gt;hw.tx_chan_base;</div><div class='ctx'> </div><div class='del'>-	req-&gt;match_id = mark &amp; 0xFFFFULL;</div><div class='del'>-	req-&gt;index = rq_idx;</div><div class='del'>-	req-&gt;op = NIX_RX_ACTIONOP_UCAST;</div><div class='del'>-	set_bit(rq_idx, &amp;nic-&gt;rq_bmap);</div><div class='del'>-	node-&gt;is_act_police = true;</div><div class='del'>-	node-&gt;rq = rq_idx;</div><div class='add'>+	ureq-&gt;dest_type[0] = NIX_RX_RSS;</div><div class='add'>+	ureq-&gt;rq_rss_index[0] = 0;</div><div class='add'>+	memcpy(&amp;ureq-&gt;hdr, &amp;grp_update_req-&gt;hdr, sizeof(struct mbox_msghdr));</div><div class='add'>+	memcpy(grp_update_req, ureq, sizeof(struct nix_mcast_grp_update_req));</div><div class='add'>+</div><div class='add'>+	/* Send message to AF */</div><div class='add'>+	rc = otx2_sync_mbox_msg(&amp;nic-&gt;mbox);</div><div class='add'>+	if (rc) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Failed to update multicast group");</div><div class='add'>+		goto error;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='add'>+	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+	req-&gt;op = NIX_RX_ACTIONOP_MCAST;</div><div class='add'>+	req-&gt;index = grp_index;</div><div class='add'>+	node-&gt;mcast_grp_idx = grp_index;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-free_leaf:</div><div class='del'>-	if (cn10k_free_leaf_profile(nic, node-&gt;leaf_profile))</div><div class='del'>-		netdev_err(nic-&gt;netdev,</div><div class='del'>-			   "Unable to free leaf bandwidth profile(%d)\n",</div><div class='del'>-			   node-&gt;leaf_profile);</div><div class='add'>+error:</div><div class='ctx'> 	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='hunk'>@@ -342,16 +437,17 @@ static int otx2_tc_parse_actions(struct otx2_nic *nic,</div><div class='ctx'> 				 struct flow_cls_offload *f,</div><div class='ctx'> 				 struct otx2_tc_flow *node)</div><div class='ctx'> {</div><div class='add'>+	struct nix_mcast_grp_update_req dummy_grp_update_req = { 0 };</div><div class='ctx'> 	struct netlink_ext_ack *extack = f-&gt;common.extack;</div><div class='add'>+	bool pps = false, mcast = false;</div><div class='ctx'> 	struct flow_action_entry *act;</div><div class='ctx'> 	struct net_device *target;</div><div class='ctx'> 	struct otx2_nic *priv;</div><div class='ctx'> 	u32 burst, mark = 0;</div><div class='ctx'> 	u8 nr_police = 0;</div><div class='del'>-	bool pps = false;</div><div class='add'>+	u8 num_intf = 1;</div><div class='add'>+	int err, i;</div><div class='ctx'> 	u64 rate;</div><div class='del'>-	int err;</div><div class='del'>-	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!flow_action_has_entries(flow_action)) {</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(extack, "no tc actions specified");</div><div class='hunk'>@@ -423,11 +519,30 @@ static int otx2_tc_parse_actions(struct otx2_nic *nic,</div><div class='ctx'> 			req-&gt;index = act-&gt;rx_queue;</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='add'>+		case FLOW_ACTION_MIRRED_INGRESS:</div><div class='add'>+			target = act-&gt;dev;</div><div class='add'>+			priv = netdev_priv(target);</div><div class='add'>+			dummy_grp_update_req.pcifunc[num_intf] = priv-&gt;pcifunc;</div><div class='add'>+			dummy_grp_update_req.channel[num_intf] = priv-&gt;hw.tx_chan_base;</div><div class='add'>+			dummy_grp_update_req.dest_type[num_intf] = NIX_RX_RSS;</div><div class='add'>+			dummy_grp_update_req.rq_rss_index[num_intf] = 0;</div><div class='add'>+			mcast = true;</div><div class='add'>+			num_intf++;</div><div class='add'>+			break;</div><div class='add'>+</div><div class='ctx'> 		default:</div><div class='ctx'> 			return -EOPNOTSUPP;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (mcast) {</div><div class='add'>+		err = otx2_tc_update_mcast(nic, req, extack, node,</div><div class='add'>+					   &amp;dummy_grp_update_req,</div><div class='add'>+					   num_intf);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (nr_police &gt; 1) {</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(extack,</div><div class='ctx'> 				   "rate limit police offload requires a single action");</div><div class='hunk'>@@ -522,6 +637,7 @@ static int otx2_tc_prepare_flow(struct otx2_nic *nic, struct otx2_tc_flow *node,</div><div class='ctx'> 	      BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |</div><div class='ctx'> 	      BIT(FLOW_DISSECTOR_KEY_IPSEC) |</div><div class='ctx'> 	      BIT_ULL(FLOW_DISSECTOR_KEY_MPLS) |</div><div class='add'>+	      BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |</div><div class='ctx'> 	      BIT_ULL(FLOW_DISSECTOR_KEY_IP))))  {</div><div class='ctx'> 		netdev_info(nic-&gt;netdev, "unsupported flow used key 0x%llx",</div><div class='ctx'> 			    dissector-&gt;used_keys);</div><div class='hunk'>@@ -796,6 +912,19 @@ static int otx2_tc_prepare_flow(struct otx2_nic *nic, struct otx2_tc_flow *node,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {</div><div class='add'>+		struct flow_match_icmp match;</div><div class='add'>+</div><div class='add'>+		flow_rule_match_icmp(rule, &amp;match);</div><div class='add'>+</div><div class='add'>+		flow_spec-&gt;icmp_type = match.key-&gt;type;</div><div class='add'>+		flow_mask-&gt;icmp_type = match.mask-&gt;type;</div><div class='add'>+		req-&gt;features |= BIT_ULL(NPC_TYPE_ICMP);</div><div class='add'>+</div><div class='add'>+		flow_spec-&gt;icmp_code = match.key-&gt;code;</div><div class='add'>+		flow_mask-&gt;icmp_code = match.mask-&gt;code;</div><div class='add'>+		req-&gt;features |= BIT_ULL(NPC_CODE_ICMP);</div><div class='add'>+	}</div><div class='ctx'> 	return otx2_tc_parse_actions(nic, &amp;rule-&gt;action, req, f, node);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1033,6 +1162,7 @@ static int otx2_tc_del_flow(struct otx2_nic *nic,</div><div class='ctx'> 			    struct flow_cls_offload *tc_flow_cmd)</div><div class='ctx'> {</div><div class='ctx'> 	struct otx2_flow_config *flow_cfg = nic-&gt;flow_cfg;</div><div class='add'>+	struct nix_mcast_grp_destroy_req *grp_destroy_req;</div><div class='ctx'> 	struct otx2_tc_flow *flow_node;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -1044,6 +1174,11 @@ static int otx2_tc_del_flow(struct otx2_nic *nic,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (flow_node-&gt;is_act_police) {</div><div class='add'>+		__clear_bit(flow_node-&gt;rq, &amp;nic-&gt;rq_bmap);</div><div class='add'>+</div><div class='add'>+		if (nic-&gt;flags &amp; OTX2_FLAG_INTF_DOWN)</div><div class='add'>+			goto free_mcam_flow;</div><div class='add'>+</div><div class='ctx'> 		mutex_lock(&amp;nic-&gt;mbox.lock);</div><div class='ctx'> </div><div class='ctx'> 		err = cn10k_map_unmap_rq_policer(nic, flow_node-&gt;rq,</div><div class='hunk'>@@ -1059,11 +1194,19 @@ static int otx2_tc_del_flow(struct otx2_nic *nic,</div><div class='ctx'> 				   "Unable to free leaf bandwidth profile(%d)\n",</div><div class='ctx'> 				   flow_node-&gt;leaf_profile);</div><div class='ctx'> </div><div class='del'>-		__clear_bit(flow_node-&gt;rq, &amp;nic-&gt;rq_bmap);</div><div class='del'>-</div><div class='ctx'> 		mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='ctx'> 	}</div><div class='add'>+	/* Remove the multicast/mirror related nodes */</div><div class='add'>+	if (flow_node-&gt;mcast_grp_idx != MCAST_INVALID_GRP) {</div><div class='add'>+		mutex_lock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+		grp_destroy_req = otx2_mbox_alloc_msg_nix_mcast_grp_destroy(&amp;nic-&gt;mbox);</div><div class='add'>+		grp_destroy_req-&gt;mcast_grp_idx = flow_node-&gt;mcast_grp_idx;</div><div class='add'>+		otx2_sync_mbox_msg(&amp;nic-&gt;mbox);</div><div class='add'>+		mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> </div><div class='add'>+free_mcam_flow:</div><div class='ctx'> 	otx2_del_mcam_flow_entry(nic, flow_node-&gt;entry, NULL);</div><div class='ctx'> 	otx2_tc_update_mcam_table(nic, flow_cfg, flow_node, false);</div><div class='ctx'> 	kfree_rcu(flow_node, rcu);</div><div class='hunk'>@@ -1083,6 +1226,11 @@ static int otx2_tc_add_flow(struct otx2_nic *nic,</div><div class='ctx'> 	if (!(nic-&gt;flags &amp; OTX2_FLAG_TC_FLOWER_SUPPORT))</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	if (nic-&gt;flags &amp; OTX2_FLAG_INTF_DOWN) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Interface not initialized");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (flow_cfg-&gt;nr_flows == flow_cfg-&gt;max_flows) {</div><div class='ctx'> 		NL_SET_ERR_MSG_MOD(extack,</div><div class='ctx'> 				   "Free MCAM entry not available to add the flow");</div><div class='hunk'>@@ -1096,6 +1244,7 @@ static int otx2_tc_add_flow(struct otx2_nic *nic,</div><div class='ctx'> 	spin_lock_init(&amp;new_node-&gt;lock);</div><div class='ctx'> 	new_node-&gt;cookie = tc_flow_cmd-&gt;cookie;</div><div class='ctx'> 	new_node-&gt;prio = tc_flow_cmd-&gt;common.prio;</div><div class='add'>+	new_node-&gt;mcast_grp_idx = MCAST_INVALID_GRP;</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;dummy, 0, sizeof(struct npc_install_flow_req));</div><div class='ctx'> </div><div class='hunk'>@@ -1442,3 +1591,45 @@ void otx2_shutdown_tc(struct otx2_nic *nic)</div><div class='ctx'> 	otx2_destroy_tc_flow_list(nic);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(otx2_shutdown_tc);</div><div class='add'>+</div><div class='add'>+static void otx2_tc_config_ingress_rule(struct otx2_nic *nic,</div><div class='add'>+					struct otx2_tc_flow *node)</div><div class='add'>+{</div><div class='add'>+	struct npc_install_flow_req *req;</div><div class='add'>+</div><div class='add'>+	if (otx2_tc_act_set_hw_police(nic, node))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+</div><div class='add'>+	req = otx2_mbox_alloc_msg_npc_install_flow(&amp;nic-&gt;mbox);</div><div class='add'>+	if (!req)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	memcpy(req, &amp;node-&gt;req, sizeof(struct npc_install_flow_req));</div><div class='add'>+</div><div class='add'>+	if (otx2_sync_mbox_msg(&amp;nic-&gt;mbox))</div><div class='add'>+		netdev_err(nic-&gt;netdev,</div><div class='add'>+			   "Failed to install MCAM flow entry for ingress rule");</div><div class='add'>+err:</div><div class='add'>+	mutex_unlock(&amp;nic-&gt;mbox.lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void otx2_tc_apply_ingress_police_rules(struct otx2_nic *nic)</div><div class='add'>+{</div><div class='add'>+	struct otx2_flow_config *flow_cfg = nic-&gt;flow_cfg;</div><div class='add'>+	struct otx2_tc_flow *node;</div><div class='add'>+</div><div class='add'>+	/* If any ingress policer rules exist for the interface then</div><div class='add'>+	 * apply those rules. Ingress policer rules depend on bandwidth</div><div class='add'>+	 * profiles linked to the receive queues. Since no receive queues</div><div class='add'>+	 * exist when interface is down, ingress policer rules are stored</div><div class='add'>+	 * and configured in hardware after all receive queues are allocated</div><div class='add'>+	 * in otx2_open.</div><div class='add'>+	 */</div><div class='add'>+	list_for_each_entry(node, &amp;flow_cfg-&gt;flow_list_tc, list) {</div><div class='add'>+		if (node-&gt;is_act_police)</div><div class='add'>+			otx2_tc_config_ingress_rule(nic, node);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(otx2_tc_apply_ingress_police_rules);</div><div class='head'>diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c<br/>index 6ee15f3c25ed..4d519ea833b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c</a></div><div class='hunk'>@@ -512,11 +512,18 @@ static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_p</div><div class='ctx'> {</div><div class='ctx'> 	struct dim_sample dim_sample;</div><div class='ctx'> 	u64 rx_frames, rx_bytes;</div><div class='add'>+	u64 tx_frames, tx_bytes;</div><div class='ctx'> </div><div class='ctx'> 	rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) +</div><div class='ctx'> 		OTX2_GET_RX_STATS(RX_UCAST);</div><div class='ctx'> 	rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);</div><div class='del'>-	dim_update_sample(pfvf-&gt;napi_events, rx_frames, rx_bytes, &amp;dim_sample);</div><div class='add'>+	tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);</div><div class='add'>+	tx_frames = OTX2_GET_TX_STATS(TX_UCAST);</div><div class='add'>+</div><div class='add'>+	dim_update_sample(pfvf-&gt;napi_events,</div><div class='add'>+			  rx_frames + tx_frames,</div><div class='add'>+			  rx_bytes + tx_bytes,</div><div class='add'>+			  &amp;dim_sample);</div><div class='ctx'> 	net_dim(&amp;cq_poll-&gt;dim, dim_sample);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -558,16 +565,9 @@ int otx2_napi_handler(struct napi_struct *napi, int budget)</div><div class='ctx'> 		if (pfvf-&gt;flags &amp; OTX2_FLAG_INTF_DOWN)</div><div class='ctx'> 			return workdone;</div><div class='ctx'> </div><div class='del'>-		/* Check for adaptive interrupt coalesce */</div><div class='del'>-		if (workdone != 0 &amp;&amp;</div><div class='del'>-		    ((pfvf-&gt;flags &amp; OTX2_FLAG_ADPTV_INT_COAL_ENABLED) ==</div><div class='del'>-		     OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) {</div><div class='del'>-			/* Adjust irq coalese using net_dim */</div><div class='add'>+		/* Adjust irq coalese using net_dim */</div><div class='add'>+		if (pfvf-&gt;flags &amp; OTX2_FLAG_ADPTV_INT_COAL_ENABLED)</div><div class='ctx'> 			otx2_adjust_adaptive_coalese(pfvf, cq_poll);</div><div class='del'>-			/* Update irq coalescing */</div><div class='del'>-			for (i = 0; i &lt; pfvf-&gt;hw.cint_cnt; i++)</div><div class='del'>-				otx2_config_irq_coalescing(pfvf, i);</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(!filled_cnt)) {</div><div class='ctx'> 			struct refill_work *work;</div><div class='head'>diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c<br/>index 3cf6589cfdac..a6e91573f8da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_eth_soc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mediatek/mtk_eth_soc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_eth_soc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_eth_soc.c</a></div><div class='hunk'>@@ -1159,15 +1159,18 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)</div><div class='ctx'> 	phy_ring_tail = eth-&gt;phy_scratch_ring + soc-&gt;txrx.txd_size * (cnt - 1);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; cnt; i++) {</div><div class='add'>+		dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;</div><div class='ctx'> 		struct mtk_tx_dma_v2 *txd;</div><div class='ctx'> </div><div class='ctx'> 		txd = eth-&gt;scratch_ring + i * soc-&gt;txrx.txd_size;</div><div class='del'>-		txd-&gt;txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;</div><div class='add'>+		txd-&gt;txd1 = addr;</div><div class='ctx'> 		if (i &lt; cnt - 1)</div><div class='ctx'> 			txd-&gt;txd2 = eth-&gt;phy_scratch_ring +</div><div class='ctx'> 				    (i + 1) * soc-&gt;txrx.txd_size;</div><div class='ctx'> </div><div class='ctx'> 		txd-&gt;txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);</div><div class='add'>+		if (MTK_HAS_CAPS(soc-&gt;caps, MTK_36BIT_DMA))</div><div class='add'>+			txd-&gt;txd3 |= TX_DMA_PREP_ADDR64(addr);</div><div class='ctx'> 		txd-&gt;txd4 = 0;</div><div class='ctx'> 		if (mtk_is_netsys_v2_or_greater(eth)) {</div><div class='ctx'> 			txd-&gt;txd5 = 0;</div><div class='head'>diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c<br/>index 9a6744c0d458..c895e265ae0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_wed.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mediatek/mtk_wed.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_wed.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_wed.c</a></div><div class='hunk'>@@ -670,7 +670,7 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)</div><div class='ctx'> 		void *buf;</div><div class='ctx'> 		int s;</div><div class='ctx'> </div><div class='del'>-		page = __dev_alloc_pages(GFP_KERNEL, 0);</div><div class='add'>+		page = __dev_alloc_page(GFP_KERNEL);</div><div class='ctx'> 		if (!page)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)</div><div class='ctx'> </div><div class='ctx'> 		for (s = 0; s &lt; MTK_WED_BUF_PER_PAGE; s++) {</div><div class='ctx'> 			struct mtk_wdma_desc *desc = desc_ptr;</div><div class='add'>+			u32 ctrl;</div><div class='ctx'> </div><div class='ctx'> 			desc-&gt;buf0 = cpu_to_le32(buf_phys);</div><div class='ctx'> 			if (!mtk_wed_is_v3_or_greater(dev-&gt;hw)) {</div><div class='del'>-				u32 txd_size, ctrl;</div><div class='add'>+				u32 txd_size;</div><div class='ctx'> </div><div class='ctx'> 				txd_size = dev-&gt;wlan.init_buf(buf, buf_phys,</div><div class='ctx'> 							      token++);</div><div class='hunk'>@@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)</div><div class='ctx'> 					ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |</div><div class='ctx'> 						FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,</div><div class='ctx'> 							   MTK_WED_BUF_SIZE - txd_size);</div><div class='del'>-				desc-&gt;ctrl = cpu_to_le32(ctrl);</div><div class='ctx'> 				desc-&gt;info = 0;</div><div class='ctx'> 			} else {</div><div class='del'>-				desc-&gt;ctrl = cpu_to_le32(token &lt;&lt; 16);</div><div class='add'>+				ctrl = token &lt;&lt; 16 | TX_DMA_PREP_ADDR64(buf_phys);</div><div class='ctx'> 			}</div><div class='add'>+			desc-&gt;ctrl = cpu_to_le32(ctrl);</div><div class='ctx'> </div><div class='ctx'> 			desc_ptr += desc_size;</div><div class='ctx'> 			buf += MTK_WED_BUF_SIZE;</div><div class='hunk'>@@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_wed_device *dev)</div><div class='ctx'> 		buf_phys = page_phys;</div><div class='ctx'> 		for (s = 0; s &lt; MTK_WED_RX_BUF_PER_PAGE; s++) {</div><div class='ctx'> 			desc-&gt;buf0 = cpu_to_le32(buf_phys);</div><div class='add'>+			desc-&gt;token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));</div><div class='ctx'> 			buf_phys += MTK_WED_PAGE_BUF_SIZE;</div><div class='ctx'> 			desc++;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/net/ethernet/mediatek/mtk_wed_wo.c b/drivers/net/ethernet/mediatek/mtk_wed_wo.c<br/>index 3bd51a3d6650..d58b07e7e123 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_wed_wo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mediatek/mtk_wed_wo.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mediatek/mtk_wed_wo.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mediatek/mtk_wed_wo.c</a></div><div class='hunk'>@@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q,</div><div class='ctx'> 		dma_addr_t addr;</div><div class='ctx'> 		void *buf;</div><div class='ctx'> </div><div class='del'>-		buf = page_frag_alloc(&amp;q-&gt;cache, q-&gt;buf_size, GFP_ATOMIC);</div><div class='add'>+		buf = page_frag_alloc(&amp;q-&gt;cache, q-&gt;buf_size,</div><div class='add'>+				      GFP_ATOMIC | GFP_DMA32);</div><div class='ctx'> 		if (!buf)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='hunk'>@@ -291,6 +292,9 @@ mtk_wed_wo_queue_tx_clean(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)</div><div class='ctx'> 	for (i = 0; i &lt; q-&gt;n_desc; i++) {</div><div class='ctx'> 		struct mtk_wed_wo_queue_entry *entry = &amp;q-&gt;entry[i];</div><div class='ctx'> </div><div class='add'>+		if (!entry-&gt;buf)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='ctx'> 		dma_unmap_single(wo-&gt;hw-&gt;dev, entry-&gt;addr, entry-&gt;len,</div><div class='ctx'> 				 DMA_TO_DEVICE);</div><div class='ctx'> 		skb_free_frag(entry-&gt;buf);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c<br/>index 164a13272faa..619e1c3ef7f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx4/en_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx4/en_ethtool.c</a></div><div class='hunk'>@@ -1258,8 +1258,8 @@ static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)</div><div class='ctx'> 	return -EINVAL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,</div><div class='del'>-			    u8 *hfunc)</div><div class='add'>+static int mlx4_en_get_rxfh(struct net_device *dev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx4_en_priv *priv = netdev_priv(dev);</div><div class='ctx'> 	u32 n = mlx4_en_get_rxfh_indir_size(dev);</div><div class='hunk'>@@ -1269,19 +1269,19 @@ static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,</div><div class='ctx'> 	rss_rings = rounddown_pow_of_two(rss_rings);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; n; i++) {</div><div class='del'>-		if (!ring_index)</div><div class='add'>+		if (!rxfh-&gt;indir)</div><div class='ctx'> 			break;</div><div class='del'>-		ring_index[i] = i % rss_rings;</div><div class='add'>+		rxfh-&gt;indir[i] = i % rss_rings;</div><div class='ctx'> 	}</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, priv-&gt;rss_key, MLX4_EN_RSS_KEY_SIZE);</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = priv-&gt;rss_hash_fn;</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, priv-&gt;rss_key, MLX4_EN_RSS_KEY_SIZE);</div><div class='add'>+	rxfh-&gt;hfunc = priv-&gt;rss_hash_fn;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,</div><div class='del'>-			    const u8 *key, const u8 hfunc)</div><div class='add'>+static int mlx4_en_set_rxfh(struct net_device *dev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx4_en_priv *priv = netdev_priv(dev);</div><div class='ctx'> 	u32 n = mlx4_en_get_rxfh_indir_size(dev);</div><div class='hunk'>@@ -1295,12 +1295,12 @@ static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,</div><div class='ctx'> 	 * between rings</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = 0; i &lt; n; i++) {</div><div class='del'>-		if (!ring_index)</div><div class='add'>+		if (!rxfh-&gt;indir)</div><div class='ctx'> 			break;</div><div class='del'>-		if (i &gt; 0 &amp;&amp; !ring_index[i] &amp;&amp; !rss_rings)</div><div class='add'>+		if (i &gt; 0 &amp;&amp; !rxfh-&gt;indir[i] &amp;&amp; !rss_rings)</div><div class='ctx'> 			rss_rings = i;</div><div class='ctx'> </div><div class='del'>-		if (ring_index[i] != (i % (rss_rings ?: n)))</div><div class='add'>+		if (rxfh-&gt;indir[i] != (i % (rss_rings ?: n)))</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1311,8 +1311,8 @@ static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,</div><div class='ctx'> 	if (!is_power_of_2(rss_rings))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE) {</div><div class='del'>-		err = mlx4_en_check_rxfh_func(dev, hfunc);</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE) {</div><div class='add'>+		err = mlx4_en_check_rxfh_func(dev, rxfh-&gt;hfunc);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return err;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1323,12 +1323,12 @@ static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,</div><div class='ctx'> 		mlx4_en_stop_port(dev, 1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ring_index)</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='ctx'> 		priv-&gt;prof-&gt;rss_rings = rss_rings;</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(priv-&gt;rss_key, key, MLX4_EN_RSS_KEY_SIZE);</div><div class='del'>-	if (hfunc !=  ETH_RSS_HASH_NO_CHANGE)</div><div class='del'>-		priv-&gt;rss_hash_fn = hfunc;</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(priv-&gt;rss_key, rxfh-&gt;key, MLX4_EN_RSS_KEY_SIZE);</div><div class='add'>+	if (rxfh-&gt;hfunc !=  ETH_RSS_HASH_NO_CHANGE)</div><div class='add'>+		priv-&gt;rss_hash_fn = rxfh-&gt;hfunc;</div><div class='ctx'> </div><div class='ctx'> 	if (port_up) {</div><div class='ctx'> 		err = mlx4_en_start_port(dev);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c<br/>index f8f0a712c943..a7b1f9686c09 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/cmd.c</a></div><div class='hunk'>@@ -156,15 +156,18 @@ static u8 alloc_token(struct mlx5_cmd *cmd)</div><div class='ctx'> 	return token;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cmd_alloc_index(struct mlx5_cmd *cmd)</div><div class='add'>+static int cmd_alloc_index(struct mlx5_cmd *cmd, struct mlx5_cmd_work_ent *ent)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;cmd-&gt;alloc_lock, flags);</div><div class='ctx'> 	ret = find_first_bit(&amp;cmd-&gt;vars.bitmask, cmd-&gt;vars.max_reg_cmds);</div><div class='del'>-	if (ret &lt; cmd-&gt;vars.max_reg_cmds)</div><div class='add'>+	if (ret &lt; cmd-&gt;vars.max_reg_cmds) {</div><div class='ctx'> 		clear_bit(ret, &amp;cmd-&gt;vars.bitmask);</div><div class='add'>+		ent-&gt;idx = ret;</div><div class='add'>+		cmd-&gt;ent_arr[ent-&gt;idx] = ent;</div><div class='add'>+	}</div><div class='ctx'> 	spin_unlock_irqrestore(&amp;cmd-&gt;alloc_lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	return ret &lt; cmd-&gt;vars.max_reg_cmds ? ret : -ENOMEM;</div><div class='hunk'>@@ -979,7 +982,7 @@ static void cmd_work_handler(struct work_struct *work)</div><div class='ctx'> 	sem = ent-&gt;page_queue ? &amp;cmd-&gt;vars.pages_sem : &amp;cmd-&gt;vars.sem;</div><div class='ctx'> 	down(sem);</div><div class='ctx'> 	if (!ent-&gt;page_queue) {</div><div class='del'>-		alloc_ret = cmd_alloc_index(cmd);</div><div class='add'>+		alloc_ret = cmd_alloc_index(cmd, ent);</div><div class='ctx'> 		if (alloc_ret &lt; 0) {</div><div class='ctx'> 			mlx5_core_err_rl(dev, "failed to allocate command entry\n");</div><div class='ctx'> 			if (ent-&gt;callback) {</div><div class='hunk'>@@ -994,15 +997,14 @@ static void cmd_work_handler(struct work_struct *work)</div><div class='ctx'> 			up(sem);</div><div class='ctx'> 			return;</div><div class='ctx'> 		}</div><div class='del'>-		ent-&gt;idx = alloc_ret;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ent-&gt;idx = cmd-&gt;vars.max_reg_cmds;</div><div class='ctx'> 		spin_lock_irqsave(&amp;cmd-&gt;alloc_lock, flags);</div><div class='ctx'> 		clear_bit(ent-&gt;idx, &amp;cmd-&gt;vars.bitmask);</div><div class='add'>+		cmd-&gt;ent_arr[ent-&gt;idx] = ent;</div><div class='ctx'> 		spin_unlock_irqrestore(&amp;cmd-&gt;alloc_lock, flags);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	cmd-&gt;ent_arr[ent-&gt;idx] = ent;</div><div class='ctx'> 	lay = get_inst(cmd, ent-&gt;idx);</div><div class='ctx'> 	ent-&gt;lay = lay;</div><div class='ctx'> 	memset(lay, 0, sizeof(*lay));</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c<br/>index 28d02749d3c4..7659ad21e6e5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/diag/crdump.c</a></div><div class='hunk'>@@ -55,7 +55,10 @@ int mlx5_crdump_collect(struct mlx5_core_dev *dev, u32 *cr_data)</div><div class='ctx'> 	ret = mlx5_vsc_sem_set_space(dev, MLX5_SEMAPHORE_SW_RESET,</div><div class='ctx'> 				     MLX5_VSC_LOCK);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		mlx5_core_warn(dev, "Failed to lock SW reset semaphore\n");</div><div class='add'>+		if (ret == -EBUSY)</div><div class='add'>+			mlx5_core_info(dev, "SW reset semaphore is already in use\n");</div><div class='add'>+		else</div><div class='add'>+			mlx5_core_warn(dev, "Failed to lock SW reset semaphore\n");</div><div class='ctx'> 		goto unlock_gw;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c<br/>index 76d27d2ee40c..080e7eab52c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c</a></div><div class='hunk'>@@ -718,7 +718,7 @@ static void mlx5_fw_tracer_handle_traces(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	while (block_timestamp &gt; tracer-&gt;last_timestamp) {</div><div class='ctx'> 		/* Check block override if it's not the first block */</div><div class='del'>-		if (!tracer-&gt;last_timestamp) {</div><div class='add'>+		if (tracer-&gt;last_timestamp) {</div><div class='ctx'> 			u64 *ts_event;</div><div class='ctx'> 			/* To avoid block override be the HW in case of buffer</div><div class='ctx'> 			 * wraparound, the time stamp of the previous block</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c<br/>index 2cd81bb32c66..18fed2b34fb1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/dpll.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/dpll.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/dpll.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/dpll.c</a></div><div class='hunk'>@@ -36,11 +36,17 @@ static int mlx5_dpll_clock_id_get(struct mlx5_core_dev *mdev, u64 *clock_id)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+struct mlx5_dpll_synce_status {</div><div class='add'>+	enum mlx5_msees_admin_status admin_status;</div><div class='add'>+	enum mlx5_msees_oper_status oper_status;</div><div class='add'>+	bool ho_acq;</div><div class='add'>+	bool oper_freq_measure;</div><div class='add'>+	s32 frequency_diff;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int</div><div class='ctx'> mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev,</div><div class='del'>-			   enum mlx5_msees_admin_status *admin_status,</div><div class='del'>-			   enum mlx5_msees_oper_status *oper_status,</div><div class='del'>-			   bool *ho_acq)</div><div class='add'>+			   struct mlx5_dpll_synce_status *synce_status)</div><div class='ctx'> {</div><div class='ctx'> 	u32 out[MLX5_ST_SZ_DW(msees_reg)] = {};</div><div class='ctx'> 	u32 in[MLX5_ST_SZ_DW(msees_reg)] = {};</div><div class='hunk'>@@ -50,11 +56,11 @@ mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev,</div><div class='ctx'> 				   MLX5_REG_MSEES, 0, 0);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='del'>-	if (admin_status)</div><div class='del'>-		*admin_status = MLX5_GET(msees_reg, out, admin_status);</div><div class='del'>-	*oper_status = MLX5_GET(msees_reg, out, oper_status);</div><div class='del'>-	if (ho_acq)</div><div class='del'>-		*ho_acq = MLX5_GET(msees_reg, out, ho_acq);</div><div class='add'>+	synce_status-&gt;admin_status = MLX5_GET(msees_reg, out, admin_status);</div><div class='add'>+	synce_status-&gt;oper_status = MLX5_GET(msees_reg, out, oper_status);</div><div class='add'>+	synce_status-&gt;ho_acq = MLX5_GET(msees_reg, out, ho_acq);</div><div class='add'>+	synce_status-&gt;oper_freq_measure = MLX5_GET(msees_reg, out, oper_freq_measure);</div><div class='add'>+	synce_status-&gt;frequency_diff = MLX5_GET(msees_reg, out, frequency_diff);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -67,21 +73,23 @@ mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev,</div><div class='ctx'> </div><div class='ctx'> 	MLX5_SET(msees_reg, in, field_select,</div><div class='ctx'> 		 MLX5_MSEES_FIELD_SELECT_ENABLE |</div><div class='add'>+		 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE |</div><div class='ctx'> 		 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS);</div><div class='ctx'> 	MLX5_SET(msees_reg, in, admin_status, admin_status);</div><div class='add'>+	MLX5_SET(msees_reg, in, admin_freq_measure, true);</div><div class='ctx'> 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),</div><div class='ctx'> 				    MLX5_REG_MSEES, 0, 1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum dpll_lock_status</div><div class='del'>-mlx5_dpll_lock_status_get(enum mlx5_msees_oper_status oper_status, bool ho_acq)</div><div class='add'>+mlx5_dpll_lock_status_get(struct mlx5_dpll_synce_status *synce_status)</div><div class='ctx'> {</div><div class='del'>-	switch (oper_status) {</div><div class='add'>+	switch (synce_status-&gt;oper_status) {</div><div class='ctx'> 	case MLX5_MSEES_OPER_STATUS_SELF_TRACK:</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case MLX5_MSEES_OPER_STATUS_OTHER_TRACK:</div><div class='del'>-		return ho_acq ? DPLL_LOCK_STATUS_LOCKED_HO_ACQ :</div><div class='del'>-				DPLL_LOCK_STATUS_LOCKED;</div><div class='add'>+		return synce_status-&gt;ho_acq ? DPLL_LOCK_STATUS_LOCKED_HO_ACQ :</div><div class='add'>+					      DPLL_LOCK_STATUS_LOCKED;</div><div class='ctx'> 	case MLX5_MSEES_OPER_STATUS_HOLDOVER:</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> 	case MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER:</div><div class='hunk'>@@ -92,31 +100,37 @@ mlx5_dpll_lock_status_get(enum mlx5_msees_oper_status oper_status, bool ho_acq)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum dpll_pin_state</div><div class='del'>-mlx5_dpll_pin_state_get(enum mlx5_msees_admin_status admin_status,</div><div class='del'>-			enum mlx5_msees_oper_status oper_status)</div><div class='add'>+mlx5_dpll_pin_state_get(struct mlx5_dpll_synce_status *synce_status)</div><div class='ctx'> {</div><div class='del'>-	return (admin_status == MLX5_MSEES_ADMIN_STATUS_TRACK &amp;&amp;</div><div class='del'>-		(oper_status == MLX5_MSEES_OPER_STATUS_SELF_TRACK ||</div><div class='del'>-		 oper_status == MLX5_MSEES_OPER_STATUS_OTHER_TRACK)) ?</div><div class='add'>+	return (synce_status-&gt;admin_status == MLX5_MSEES_ADMIN_STATUS_TRACK &amp;&amp;</div><div class='add'>+		(synce_status-&gt;oper_status == MLX5_MSEES_OPER_STATUS_SELF_TRACK ||</div><div class='add'>+		 synce_status-&gt;oper_status == MLX5_MSEES_OPER_STATUS_OTHER_TRACK)) ?</div><div class='ctx'> 	       DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int</div><div class='add'>+mlx5_dpll_pin_ffo_get(struct mlx5_dpll_synce_status *synce_status,</div><div class='add'>+		      s64 *ffo)</div><div class='add'>+{</div><div class='add'>+	if (!synce_status-&gt;oper_freq_measure)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+	*ffo = synce_status-&gt;frequency_diff;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll,</div><div class='ctx'> 					    void *priv,</div><div class='ctx'> 					    enum dpll_lock_status *status,</div><div class='ctx'> 					    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='del'>-	enum mlx5_msees_oper_status oper_status;</div><div class='add'>+	struct mlx5_dpll_synce_status synce_status;</div><div class='ctx'> 	struct mlx5_dpll *mdpll = priv;</div><div class='del'>-	bool ho_acq;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, NULL,</div><div class='del'>-					 &amp;oper_status, &amp;ho_acq);</div><div class='add'>+	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;synce_status);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='del'>-</div><div class='del'>-	*status = mlx5_dpll_lock_status_get(oper_status, ho_acq);</div><div class='add'>+	*status = mlx5_dpll_lock_status_get(&amp;synce_status);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -128,18 +142,9 @@ static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool mlx5_dpll_device_mode_supported(const struct dpll_device *dpll,</div><div class='del'>-					    void *priv,</div><div class='del'>-					    enum dpll_mode mode,</div><div class='del'>-					    struct netlink_ext_ack *extack)</div><div class='del'>-{</div><div class='del'>-	return mode == DPLL_MODE_MANUAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static const struct dpll_device_ops mlx5_dpll_device_ops = {</div><div class='ctx'> 	.lock_status_get = mlx5_dpll_device_lock_status_get,</div><div class='ctx'> 	.mode_get = mlx5_dpll_device_mode_get,</div><div class='del'>-	.mode_supported = mlx5_dpll_device_mode_supported,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int mlx5_dpll_pin_direction_get(const struct dpll_pin *pin,</div><div class='hunk'>@@ -160,16 +165,14 @@ static int mlx5_dpll_state_on_dpll_get(const struct dpll_pin *pin,</div><div class='ctx'> 				       enum dpll_pin_state *state,</div><div class='ctx'> 				       struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='del'>-	enum mlx5_msees_admin_status admin_status;</div><div class='del'>-	enum mlx5_msees_oper_status oper_status;</div><div class='add'>+	struct mlx5_dpll_synce_status synce_status;</div><div class='ctx'> 	struct mlx5_dpll *mdpll = pin_priv;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;admin_status,</div><div class='del'>-					 &amp;oper_status, NULL);</div><div class='add'>+	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;synce_status);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='del'>-	*state = mlx5_dpll_pin_state_get(admin_status, oper_status);</div><div class='add'>+	*state = mlx5_dpll_pin_state_get(&amp;synce_status);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -188,10 +191,25 @@ static int mlx5_dpll_state_on_dpll_set(const struct dpll_pin *pin,</div><div class='ctx'> 					  MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mlx5_dpll_ffo_get(const struct dpll_pin *pin, void *pin_priv,</div><div class='add'>+			     const struct dpll_device *dpll, void *dpll_priv,</div><div class='add'>+			     s64 *ffo, struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_dpll_synce_status synce_status;</div><div class='add'>+	struct mlx5_dpll *mdpll = pin_priv;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;synce_status);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+	return mlx5_dpll_pin_ffo_get(&amp;synce_status, ffo);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct dpll_pin_ops mlx5_dpll_pins_ops = {</div><div class='ctx'> 	.direction_get = mlx5_dpll_pin_direction_get,</div><div class='ctx'> 	.state_on_dpll_get = mlx5_dpll_state_on_dpll_get,</div><div class='ctx'> 	.state_on_dpll_set = mlx5_dpll_state_on_dpll_set,</div><div class='add'>+	.ffo_get = mlx5_dpll_ffo_get,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct dpll_pin_properties mlx5_dpll_pin_properties = {</div><div class='hunk'>@@ -211,19 +229,16 @@ static void mlx5_dpll_periodic_work(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5_dpll *mdpll = container_of(work, struct mlx5_dpll,</div><div class='ctx'> 					       work.work);</div><div class='del'>-	enum mlx5_msees_admin_status admin_status;</div><div class='del'>-	enum mlx5_msees_oper_status oper_status;</div><div class='add'>+	struct mlx5_dpll_synce_status synce_status;</div><div class='ctx'> 	enum dpll_lock_status lock_status;</div><div class='ctx'> 	enum dpll_pin_state pin_state;</div><div class='del'>-	bool ho_acq;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;admin_status,</div><div class='del'>-					 &amp;oper_status, &amp;ho_acq);</div><div class='add'>+	err = mlx5_dpll_synce_status_get(mdpll-&gt;mdev, &amp;synce_status);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_out;</div><div class='del'>-	lock_status = mlx5_dpll_lock_status_get(oper_status, ho_acq);</div><div class='del'>-	pin_state = mlx5_dpll_pin_state_get(admin_status, oper_status);</div><div class='add'>+	lock_status = mlx5_dpll_lock_status_get(&amp;synce_status);</div><div class='add'>+	pin_state = mlx5_dpll_pin_state_get(&amp;synce_status);</div><div class='ctx'> </div><div class='ctx'> 	if (!mdpll-&gt;last.valid)</div><div class='ctx'> 		goto invalid_out;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h<br/>index b2a5da9739d2..0bfe1ca8a364 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en.h</a></div><div class='hunk'>@@ -72,7 +72,6 @@ struct page_pool;</div><div class='ctx'> #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)-&gt;hard_mtu))</div><div class='ctx'> #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)-&gt;hard_mtu))</div><div class='ctx'> </div><div class='del'>-#define MLX5E_MAX_NUM_TC	8</div><div class='ctx'> #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE</div><div class='ctx'> </div><div class='ctx'> #define MLX5_RX_HEADROOM NET_SKB_PAD</div><div class='hunk'>@@ -364,7 +363,7 @@ struct mlx5e_cq {</div><div class='ctx'> 	/* control */</div><div class='ctx'> 	struct net_device         *netdev;</div><div class='ctx'> 	struct mlx5_core_dev      *mdev;</div><div class='del'>-	struct mlx5e_priv         *priv;</div><div class='add'>+	struct workqueue_struct   *workqueue;</div><div class='ctx'> 	struct mlx5_wq_ctrl        wq_ctrl;</div><div class='ctx'> } ____cacheline_aligned_in_smp;</div><div class='ctx'> </div><div class='hunk'>@@ -484,10 +483,12 @@ struct mlx5e_xdp_info_fifo {</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_xdpsq;</div><div class='ctx'> struct mlx5e_xmit_data;</div><div class='add'>+struct xsk_tx_metadata;</div><div class='ctx'> typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);</div><div class='ctx'> typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,</div><div class='ctx'> 					struct mlx5e_xmit_data *,</div><div class='del'>-					int);</div><div class='add'>+					int,</div><div class='add'>+					struct xsk_tx_metadata *);</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_xdpsq {</div><div class='ctx'> 	/* data path */</div><div class='hunk'>@@ -756,7 +757,7 @@ struct mlx5e_channel {</div><div class='ctx'> 	/* data path */</div><div class='ctx'> 	struct mlx5e_rq            rq;</div><div class='ctx'> 	struct mlx5e_xdpsq         rq_xdpsq;</div><div class='del'>-	struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];</div><div class='add'>+	struct mlx5e_txqsq         sq[MLX5_MAX_NUM_TC];</div><div class='ctx'> 	struct mlx5e_icosq         icosq;   /* internal control operations */</div><div class='ctx'> 	struct mlx5e_txqsq __rcu * __rcu *qos_sqs;</div><div class='ctx'> 	bool                       xdp;</div><div class='hunk'>@@ -806,7 +807,7 @@ struct mlx5e_channels {</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_channel_stats {</div><div class='ctx'> 	struct mlx5e_ch_stats ch;</div><div class='del'>-	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];</div><div class='add'>+	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];</div><div class='ctx'> 	struct mlx5e_rq_stats rq;</div><div class='ctx'> 	struct mlx5e_rq_stats xskrq;</div><div class='ctx'> 	struct mlx5e_xdpsq_stats rq_xdpsq;</div><div class='hunk'>@@ -816,8 +817,8 @@ struct mlx5e_channel_stats {</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_ptp_stats {</div><div class='ctx'> 	struct mlx5e_ch_stats ch;</div><div class='del'>-	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];</div><div class='del'>-	struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];</div><div class='add'>+	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];</div><div class='add'>+	struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];</div><div class='ctx'> 	struct mlx5e_rq_stats rq;</div><div class='ctx'> } ____cacheline_aligned_in_smp;</div><div class='ctx'> </div><div class='hunk'>@@ -826,6 +827,7 @@ enum {</div><div class='ctx'> 	MLX5E_STATE_DESTROYING,</div><div class='ctx'> 	MLX5E_STATE_XDP_TX_ENABLED,</div><div class='ctx'> 	MLX5E_STATE_XDP_ACTIVE,</div><div class='add'>+	MLX5E_STATE_CHANNELS_ACTIVE,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_modify_sq_param {</div><div class='hunk'>@@ -884,7 +886,6 @@ struct mlx5e_priv {</div><div class='ctx'> 	struct mlx5e_rq            drop_rq;</div><div class='ctx'> </div><div class='ctx'> 	struct mlx5e_channels      channels;</div><div class='del'>-	u32                        tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];</div><div class='ctx'> 	struct mlx5e_rx_res       *rx_res;</div><div class='ctx'> 	u32                       *tx_rates;</div><div class='ctx'> </div><div class='hunk'>@@ -982,6 +983,8 @@ struct mlx5e_profile {</div><div class='ctx'> 	void	(*update_stats)(struct mlx5e_priv *priv);</div><div class='ctx'> 	void	(*update_carrier)(struct mlx5e_priv *priv);</div><div class='ctx'> 	int	(*max_nch_limit)(struct mlx5_core_dev *mdev);</div><div class='add'>+	u32	(*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,</div><div class='add'>+			    u8 lag_port, u8 tc);</div><div class='ctx'> 	unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);</div><div class='ctx'> 	mlx5e_stats_grp_t *stats_grps;</div><div class='ctx'> 	const struct mlx5e_rx_handlers *rx_handlers;</div><div class='hunk'>@@ -989,6 +992,11 @@ struct mlx5e_profile {</div><div class='ctx'> 	u32     features;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,</div><div class='add'>+			   struct mlx5e_priv *priv,</div><div class='add'>+			   const struct mlx5e_profile *profile,</div><div class='add'>+			   u8 lag_port, u8 tc);</div><div class='add'>+</div><div class='ctx'> #define mlx5e_profile_feature_cap(profile, feature)	\</div><div class='ctx'> 	((profile)-&gt;features &amp; BIT(MLX5E_PROFILE_FEATURE_##feature))</div><div class='ctx'> </div><div class='hunk'>@@ -1036,6 +1044,8 @@ int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,</div><div class='ctx'> void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_create_cq_param {</div><div class='add'>+	struct net_device *netdev;</div><div class='add'>+	struct workqueue_struct *wq;</div><div class='ctx'> 	struct napi_struct *napi;</div><div class='ctx'> 	struct mlx5e_ch_stats *ch_stats;</div><div class='ctx'> 	int node;</div><div class='hunk'>@@ -1043,7 +1053,7 @@ struct mlx5e_create_cq_param {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_cq_param;</div><div class='del'>-int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,</div><div class='add'>+int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,</div><div class='ctx'> 		  struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,</div><div class='ctx'> 		  struct mlx5e_cq *cq);</div><div class='ctx'> void mlx5e_close_cq(struct mlx5e_cq *cq);</div><div class='hunk'>@@ -1130,8 +1140,6 @@ void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);</div><div class='ctx'> int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);</div><div class='ctx'> void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);</div><div class='ctx'> </div><div class='del'>-int mlx5e_create_tises(struct mlx5e_priv *priv);</div><div class='del'>-void mlx5e_destroy_tises(struct mlx5e_priv *priv);</div><div class='ctx'> int mlx5e_update_nic_rx(struct mlx5e_priv *priv);</div><div class='ctx'> void mlx5e_update_carrier(struct mlx5e_priv *priv);</div><div class='ctx'> int mlx5e_close(struct net_device *netdev);</div><div class='hunk'>@@ -1173,9 +1181,9 @@ int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,</div><div class='ctx'> 				     struct ethtool_link_ksettings *link_ksettings);</div><div class='ctx'> int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,</div><div class='ctx'> 				     const struct ethtool_link_ksettings *link_ksettings);</div><div class='del'>-int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);</div><div class='del'>-int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,</div><div class='del'>-		   const u8 hfunc);</div><div class='add'>+int mlx5e_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh);</div><div class='add'>+int mlx5e_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+		   struct netlink_ext_ack *extack);</div><div class='ctx'> u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);</div><div class='ctx'> u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);</div><div class='ctx'> int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c b/drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c<br/>index be83ad9db82a..e1283531e0b8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/fs_tt_redirect.c</a></div><div class='hunk'>@@ -154,6 +154,7 @@ static int fs_udp_create_groups(struct mlx5e_flow_table *ft, enum fs_udp_type ty</div><div class='ctx'> 	in = kvzalloc(inlen, GFP_KERNEL);</div><div class='ctx'> 	if  (!in || !ft-&gt;g) {</div><div class='ctx'> 		kfree(ft-&gt;g);</div><div class='add'>+		ft-&gt;g = NULL;</div><div class='ctx'> 		kvfree(in);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c<br/>index 254c84739046..40c8df111754 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.c</a></div><div class='hunk'>@@ -36,7 +36,7 @@ int mlx5e_monitor_counter_supported(struct mlx5e_priv *priv)</div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mlx5e_monitor_counter_arm(struct mlx5e_priv *priv)</div><div class='add'>+static void mlx5e_monitor_counter_arm(struct mlx5e_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	u32 in[MLX5_ST_SZ_DW(arm_monitor_counter_in)] = {};</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h<br/>index e1ac4b3d22fb..6beba7f075c1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/monitor_stats.h</a></div><div class='hunk'>@@ -7,6 +7,5 @@</div><div class='ctx'> int  mlx5e_monitor_counter_supported(struct mlx5e_priv *priv);</div><div class='ctx'> void mlx5e_monitor_counter_init(struct mlx5e_priv *priv);</div><div class='ctx'> void mlx5e_monitor_counter_cleanup(struct mlx5e_priv *priv);</div><div class='del'>-void mlx5e_monitor_counter_arm(struct mlx5e_priv *priv);</div><div class='ctx'> </div><div class='ctx'> #endif /* __MLX5_MONITOR_H__ */</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c<br/>index e097f336e1c4..284253b79266 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/params.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/params.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/params.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/params.c</a></div><div class='hunk'>@@ -669,6 +669,8 @@ void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,</div><div class='ctx'> void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c)</div><div class='ctx'> {</div><div class='ctx'> 	*ccp = (struct mlx5e_create_cq_param) {</div><div class='add'>+		.netdev = c-&gt;netdev,</div><div class='add'>+		.wq = c-&gt;priv-&gt;wq,</div><div class='ctx'> 		.napi = &amp;c-&gt;napi,</div><div class='ctx'> 		.ch_stats = c-&gt;stats,</div><div class='ctx'> 		.node = cpu_to_node(c-&gt;cpu),</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c<br/>index af3928eddafd..c206cc0a8483 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c</a></div><div class='hunk'>@@ -518,9 +518,11 @@ static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c,</div><div class='ctx'> </div><div class='ctx'> 	for (tc = 0; tc &lt; num_tc; tc++) {</div><div class='ctx'> 		int txq_ix = ix_base + tc;</div><div class='add'>+		u32 tisn;</div><div class='ctx'> </div><div class='del'>-		err = mlx5e_ptp_open_txqsq(c, c-&gt;priv-&gt;tisn[c-&gt;lag_port][tc], txq_ix,</div><div class='del'>-					   cparams, tc, &amp;c-&gt;ptpsq[tc]);</div><div class='add'>+		tisn = mlx5e_profile_get_tisn(c-&gt;mdev, c-&gt;priv, c-&gt;priv-&gt;profile,</div><div class='add'>+					      c-&gt;lag_port, tc);</div><div class='add'>+		err = mlx5e_ptp_open_txqsq(c, tisn, txq_ix, cparams, tc, &amp;c-&gt;ptpsq[tc]);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto close_txqsq;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -555,6 +557,8 @@ static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,</div><div class='ctx'> </div><div class='ctx'> 	num_tc = mlx5e_get_dcb_num_tc(params);</div><div class='ctx'> </div><div class='add'>+	ccp.netdev   = c-&gt;netdev;</div><div class='add'>+	ccp.wq       = c-&gt;priv-&gt;wq;</div><div class='ctx'> 	ccp.node     = dev_to_node(mlx5_core_dma_dev(c-&gt;mdev));</div><div class='ctx'> 	ccp.ch_stats = c-&gt;stats;</div><div class='ctx'> 	ccp.napi     = &amp;c-&gt;napi;</div><div class='hunk'>@@ -565,7 +569,7 @@ static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,</div><div class='ctx'> 	for (tc = 0; tc &lt; num_tc; tc++) {</div><div class='ctx'> 		struct mlx5e_cq *cq = &amp;c-&gt;ptpsq[tc].txqsq.cq;</div><div class='ctx'> </div><div class='del'>-		err = mlx5e_open_cq(c-&gt;priv, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='add'>+		err = mlx5e_open_cq(c-&gt;mdev, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out_err_txqsq_cq;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -574,7 +578,7 @@ static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,</div><div class='ctx'> 		struct mlx5e_cq *cq = &amp;c-&gt;ptpsq[tc].ts_cq;</div><div class='ctx'> 		struct mlx5e_ptpsq *ptpsq = &amp;c-&gt;ptpsq[tc];</div><div class='ctx'> </div><div class='del'>-		err = mlx5e_open_cq(c-&gt;priv, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='add'>+		err = mlx5e_open_cq(c-&gt;mdev, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out_err_ts_cq;</div><div class='ctx'> </div><div class='hunk'>@@ -602,6 +606,8 @@ static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,</div><div class='ctx'> 	struct mlx5e_cq_param *cq_param;</div><div class='ctx'> 	struct mlx5e_cq *cq = &amp;c-&gt;rq.cq;</div><div class='ctx'> </div><div class='add'>+	ccp.netdev   = c-&gt;netdev;</div><div class='add'>+	ccp.wq       = c-&gt;priv-&gt;wq;</div><div class='ctx'> 	ccp.node     = dev_to_node(mlx5_core_dma_dev(c-&gt;mdev));</div><div class='ctx'> 	ccp.ch_stats = c-&gt;stats;</div><div class='ctx'> 	ccp.napi     = &amp;c-&gt;napi;</div><div class='hunk'>@@ -609,7 +615,7 @@ static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,</div><div class='ctx'> </div><div class='ctx'> 	cq_param = &amp;cparams-&gt;rq_param.cqp;</div><div class='ctx'> </div><div class='del'>-	return mlx5e_open_cq(c-&gt;priv, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='add'>+	return mlx5e_open_cq(c-&gt;mdev, ptp_moder, cq_param, &amp;ccp, cq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp *c)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h<br/>index 7b700d0f956a..86f1854698b4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h</a></div><div class='hunk'>@@ -49,7 +49,7 @@ enum {</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_ptp {</div><div class='ctx'> 	/* data path */</div><div class='del'>-	struct mlx5e_ptpsq         ptpsq[MLX5E_MAX_NUM_TC];</div><div class='add'>+	struct mlx5e_ptpsq         ptpsq[MLX5_MAX_NUM_TC];</div><div class='ctx'> 	struct mlx5e_rq            rq;</div><div class='ctx'> 	struct napi_struct         napi;</div><div class='ctx'> 	struct device             *pdev;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/en/qos.c<br/>index 244bc15a42ab..34adf8c3f81a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/qos.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/qos.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/qos.c</a></div><div class='hunk'>@@ -77,6 +77,7 @@ int mlx5e_open_qos_sq(struct mlx5e_priv *priv, struct mlx5e_channels *chs,</div><div class='ctx'> 	struct mlx5e_params *params;</div><div class='ctx'> 	struct mlx5e_channel *c;</div><div class='ctx'> 	struct mlx5e_txqsq *sq;</div><div class='add'>+	u32 tisn;</div><div class='ctx'> </div><div class='ctx'> 	params = &amp;chs-&gt;params;</div><div class='ctx'> </div><div class='hunk'>@@ -123,11 +124,13 @@ int mlx5e_open_qos_sq(struct mlx5e_priv *priv, struct mlx5e_channels *chs,</div><div class='ctx'> 	memset(&amp;param_cq, 0, sizeof(param_cq));</div><div class='ctx'> 	mlx5e_build_sq_param(priv-&gt;mdev, params, &amp;param_sq);</div><div class='ctx'> 	mlx5e_build_tx_cq_param(priv-&gt;mdev, params, &amp;param_cq);</div><div class='del'>-	err = mlx5e_open_cq(priv, params-&gt;tx_cq_moderation, &amp;param_cq, &amp;ccp, &amp;sq-&gt;cq);</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, params-&gt;tx_cq_moderation, &amp;param_cq, &amp;ccp, &amp;sq-&gt;cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_free_sq;</div><div class='del'>-	err = mlx5e_open_txqsq(c, priv-&gt;tisn[c-&gt;lag_port][0], txq_ix, params,</div><div class='del'>-			       &amp;param_sq, sq, 0, hw_id,</div><div class='add'>+</div><div class='add'>+	tisn = mlx5e_profile_get_tisn(c-&gt;mdev, c-&gt;priv, c-&gt;priv-&gt;profile,</div><div class='add'>+				      c-&gt;lag_port, 0);</div><div class='add'>+	err = mlx5e_open_txqsq(c, tisn, txq_ix, params, &amp;param_sq, sq, 0, hw_id,</div><div class='ctx'> 			       priv-&gt;htb_qos_sq_stats[node_qid]);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_cq;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c<br/>index b12fe3c5a258..a55452c69f06 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c</a></div><div class='hunk'>@@ -147,6 +147,20 @@ mlx5e_rep_setup_tc_cls_flower(struct mlx5e_priv *priv,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,</div><div class='add'>+				    struct tc_cls_matchall_offload *ma)</div><div class='add'>+{</div><div class='add'>+	struct mlx5e_rep_priv *rpriv = priv-&gt;ppriv;</div><div class='add'>+	u64 dbytes;</div><div class='add'>+	u64 dpkts;</div><div class='add'>+</div><div class='add'>+	dpkts = priv-&gt;stats.rep_stats.vport_rx_packets - rpriv-&gt;prev_vf_vport_stats.rx_packets;</div><div class='add'>+	dbytes = priv-&gt;stats.rep_stats.vport_rx_bytes - rpriv-&gt;prev_vf_vport_stats.rx_bytes;</div><div class='add'>+	mlx5e_stats_copy_rep_stats(&amp;rpriv-&gt;prev_vf_vport_stats, &amp;priv-&gt;stats.rep_stats);</div><div class='add'>+	flow_stats_update(&amp;ma-&gt;stats, dbytes, dpkts, 0, jiffies,</div><div class='add'>+			  FLOW_ACTION_HW_STATS_DELAYED);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static</div><div class='ctx'> int mlx5e_rep_setup_tc_cls_matchall(struct mlx5e_priv *priv,</div><div class='ctx'> 				    struct tc_cls_matchall_offload *ma)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c<br/>index f63402c48028..1b418095b79a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/mirred.c</a></div><div class='hunk'>@@ -197,7 +197,7 @@ parse_mirred_encap(struct mlx5e_tc_act_parse_state *parse_state,</div><div class='ctx'> 	}</div><div class='ctx'> 	esw_attr-&gt;dests[esw_attr-&gt;out_count].flags |= MLX5_ESW_DEST_ENCAP;</div><div class='ctx'> 	esw_attr-&gt;out_count++;</div><div class='del'>-	/* attr-&gt;dests[].rep is resolved when we handle encap */</div><div class='add'>+	/* attr-&gt;dests[].vport is resolved when we handle encap */</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -270,7 +270,8 @@ parse_mirred(struct mlx5e_tc_act_parse_state *parse_state,</div><div class='ctx'> </div><div class='ctx'> 	out_priv = netdev_priv(out_dev);</div><div class='ctx'> 	rpriv = out_priv-&gt;ppriv;</div><div class='del'>-	esw_attr-&gt;dests[esw_attr-&gt;out_count].rep = rpriv-&gt;rep;</div><div class='add'>+	esw_attr-&gt;dests[esw_attr-&gt;out_count].vport_valid = true;</div><div class='add'>+	esw_attr-&gt;dests[esw_attr-&gt;out_count].vport = rpriv-&gt;rep-&gt;vport;</div><div class='ctx'> 	esw_attr-&gt;dests[esw_attr-&gt;out_count].mdev = out_priv-&gt;mdev;</div><div class='ctx'> </div><div class='ctx'> 	esw_attr-&gt;out_count++;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c<br/>index 368a95fa77d3..b14cd62edffc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/pedit.c</a></div><div class='hunk'>@@ -48,7 +48,8 @@ mlx5e_tc_act_pedit_parse_action(struct mlx5e_priv *priv,</div><div class='ctx'> 				struct pedit_headers_action *hdrs,</div><div class='ctx'> 				struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='del'>-	u8 cmd = (act-&gt;id == FLOW_ACTION_MANGLE) ? 0 : 1;</div><div class='add'>+	u8 cmd = (act-&gt;id == FLOW_ACTION_MANGLE) ? TCA_PEDIT_KEY_EX_CMD_SET :</div><div class='add'>+						   TCA_PEDIT_KEY_EX_CMD_ADD;</div><div class='ctx'> 	u8 htype = act-&gt;mangle.htype;</div><div class='ctx'> 	int err = -EOPNOTSUPP;</div><div class='ctx'> 	u32 mask, val, offset;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c<br/>index 4e923a2874ae..86bf007fd05b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc/post_act.c</a></div><div class='hunk'>@@ -83,6 +83,9 @@ mlx5e_tc_post_act_offload(struct mlx5e_post_act *post_act,</div><div class='ctx'> 	struct mlx5_flow_spec *spec;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='add'>+	if (IS_ERR(post_act))</div><div class='add'>+		return PTR_ERR(post_act);</div><div class='add'>+</div><div class='ctx'> 	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='ctx'> 	if (!spec)</div><div class='ctx'> 		return -ENOMEM;</div><div class='hunk'>@@ -111,6 +114,9 @@ mlx5e_tc_post_act_add(struct mlx5e_post_act *post_act, struct mlx5_flow_attr *po</div><div class='ctx'> 	struct mlx5e_post_act_handle *handle;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='add'>+	if (IS_ERR(post_act))</div><div class='add'>+		return ERR_CAST(post_act);</div><div class='add'>+</div><div class='ctx'> 	handle = kzalloc(sizeof(*handle), GFP_KERNEL);</div><div class='ctx'> 	if (!handle)</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c<br/>index 668da5c70e63..8dfb57f712b0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c</a></div><div class='hunk'>@@ -300,6 +300,10 @@ int mlx5e_tc_tun_create_header_ipv4(struct mlx5e_priv *priv,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto destroy_neigh_entry;</div><div class='ctx'> </div><div class='add'>+	e-&gt;encap_size = ipv4_encap_size;</div><div class='add'>+	e-&gt;encap_header = encap_header;</div><div class='add'>+	encap_header = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (!(nud_state &amp; NUD_VALID)) {</div><div class='ctx'> 		neigh_event_send(attr.n, NULL);</div><div class='ctx'> 		/* the encap entry will be made valid on neigh update event</div><div class='hunk'>@@ -310,8 +314,8 @@ int mlx5e_tc_tun_create_header_ipv4(struct mlx5e_priv *priv,</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;reformat_params, 0, sizeof(reformat_params));</div><div class='ctx'> 	reformat_params.type = e-&gt;reformat_type;</div><div class='del'>-	reformat_params.size = ipv4_encap_size;</div><div class='del'>-	reformat_params.data = encap_header;</div><div class='add'>+	reformat_params.size = e-&gt;encap_size;</div><div class='add'>+	reformat_params.data = e-&gt;encap_header;</div><div class='ctx'> 	e-&gt;pkt_reformat = mlx5_packet_reformat_alloc(priv-&gt;mdev, &amp;reformat_params,</div><div class='ctx'> 						     MLX5_FLOW_NAMESPACE_FDB);</div><div class='ctx'> 	if (IS_ERR(e-&gt;pkt_reformat)) {</div><div class='hunk'>@@ -319,8 +323,6 @@ int mlx5e_tc_tun_create_header_ipv4(struct mlx5e_priv *priv,</div><div class='ctx'> 		goto destroy_neigh_entry;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	e-&gt;encap_size = ipv4_encap_size;</div><div class='del'>-	e-&gt;encap_header = encap_header;</div><div class='ctx'> 	e-&gt;flags |= MLX5_ENCAP_ENTRY_VALID;</div><div class='ctx'> 	mlx5e_rep_queue_neigh_stats_work(netdev_priv(attr.out_dev));</div><div class='ctx'> 	mlx5e_route_lookup_ipv4_put(&amp;attr);</div><div class='hunk'>@@ -403,18 +405,23 @@ int mlx5e_tc_tun_update_header_ipv4(struct mlx5e_priv *priv,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto free_encap;</div><div class='ctx'> </div><div class='add'>+	e-&gt;encap_size = ipv4_encap_size;</div><div class='add'>+	kfree(e-&gt;encap_header);</div><div class='add'>+	e-&gt;encap_header = encap_header;</div><div class='add'>+	encap_header = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (!(nud_state &amp; NUD_VALID)) {</div><div class='ctx'> 		neigh_event_send(attr.n, NULL);</div><div class='ctx'> 		/* the encap entry will be made valid on neigh update event</div><div class='ctx'> 		 * and not used before that.</div><div class='ctx'> 		 */</div><div class='del'>-		goto free_encap;</div><div class='add'>+		goto release_neigh;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;reformat_params, 0, sizeof(reformat_params));</div><div class='ctx'> 	reformat_params.type = e-&gt;reformat_type;</div><div class='del'>-	reformat_params.size = ipv4_encap_size;</div><div class='del'>-	reformat_params.data = encap_header;</div><div class='add'>+	reformat_params.size = e-&gt;encap_size;</div><div class='add'>+	reformat_params.data = e-&gt;encap_header;</div><div class='ctx'> 	e-&gt;pkt_reformat = mlx5_packet_reformat_alloc(priv-&gt;mdev, &amp;reformat_params,</div><div class='ctx'> 						     MLX5_FLOW_NAMESPACE_FDB);</div><div class='ctx'> 	if (IS_ERR(e-&gt;pkt_reformat)) {</div><div class='hunk'>@@ -422,10 +429,6 @@ int mlx5e_tc_tun_update_header_ipv4(struct mlx5e_priv *priv,</div><div class='ctx'> 		goto free_encap;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	e-&gt;encap_size = ipv4_encap_size;</div><div class='del'>-	kfree(e-&gt;encap_header);</div><div class='del'>-	e-&gt;encap_header = encap_header;</div><div class='del'>-</div><div class='ctx'> 	e-&gt;flags |= MLX5_ENCAP_ENTRY_VALID;</div><div class='ctx'> 	mlx5e_rep_queue_neigh_stats_work(netdev_priv(attr.out_dev));</div><div class='ctx'> 	mlx5e_route_lookup_ipv4_put(&amp;attr);</div><div class='hunk'>@@ -567,6 +570,10 @@ int mlx5e_tc_tun_create_header_ipv6(struct mlx5e_priv *priv,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto destroy_neigh_entry;</div><div class='ctx'> </div><div class='add'>+	e-&gt;encap_size = ipv6_encap_size;</div><div class='add'>+	e-&gt;encap_header = encap_header;</div><div class='add'>+	encap_header = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (!(nud_state &amp; NUD_VALID)) {</div><div class='ctx'> 		neigh_event_send(attr.n, NULL);</div><div class='ctx'> 		/* the encap entry will be made valid on neigh update event</div><div class='hunk'>@@ -577,8 +584,8 @@ int mlx5e_tc_tun_create_header_ipv6(struct mlx5e_priv *priv,</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;reformat_params, 0, sizeof(reformat_params));</div><div class='ctx'> 	reformat_params.type = e-&gt;reformat_type;</div><div class='del'>-	reformat_params.size = ipv6_encap_size;</div><div class='del'>-	reformat_params.data = encap_header;</div><div class='add'>+	reformat_params.size = e-&gt;encap_size;</div><div class='add'>+	reformat_params.data = e-&gt;encap_header;</div><div class='ctx'> 	e-&gt;pkt_reformat = mlx5_packet_reformat_alloc(priv-&gt;mdev, &amp;reformat_params,</div><div class='ctx'> 						     MLX5_FLOW_NAMESPACE_FDB);</div><div class='ctx'> 	if (IS_ERR(e-&gt;pkt_reformat)) {</div><div class='hunk'>@@ -586,8 +593,6 @@ int mlx5e_tc_tun_create_header_ipv6(struct mlx5e_priv *priv,</div><div class='ctx'> 		goto destroy_neigh_entry;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	e-&gt;encap_size = ipv6_encap_size;</div><div class='del'>-	e-&gt;encap_header = encap_header;</div><div class='ctx'> 	e-&gt;flags |= MLX5_ENCAP_ENTRY_VALID;</div><div class='ctx'> 	mlx5e_rep_queue_neigh_stats_work(netdev_priv(attr.out_dev));</div><div class='ctx'> 	mlx5e_route_lookup_ipv6_put(&amp;attr);</div><div class='hunk'>@@ -669,18 +674,23 @@ int mlx5e_tc_tun_update_header_ipv6(struct mlx5e_priv *priv,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto free_encap;</div><div class='ctx'> </div><div class='add'>+	e-&gt;encap_size = ipv6_encap_size;</div><div class='add'>+	kfree(e-&gt;encap_header);</div><div class='add'>+	e-&gt;encap_header = encap_header;</div><div class='add'>+	encap_header = NULL;</div><div class='add'>+</div><div class='ctx'> 	if (!(nud_state &amp; NUD_VALID)) {</div><div class='ctx'> 		neigh_event_send(attr.n, NULL);</div><div class='ctx'> 		/* the encap entry will be made valid on neigh update event</div><div class='ctx'> 		 * and not used before that.</div><div class='ctx'> 		 */</div><div class='del'>-		goto free_encap;</div><div class='add'>+		goto release_neigh;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	memset(&amp;reformat_params, 0, sizeof(reformat_params));</div><div class='ctx'> 	reformat_params.type = e-&gt;reformat_type;</div><div class='del'>-	reformat_params.size = ipv6_encap_size;</div><div class='del'>-	reformat_params.data = encap_header;</div><div class='add'>+	reformat_params.size = e-&gt;encap_size;</div><div class='add'>+	reformat_params.data = e-&gt;encap_header;</div><div class='ctx'> 	e-&gt;pkt_reformat = mlx5_packet_reformat_alloc(priv-&gt;mdev, &amp;reformat_params,</div><div class='ctx'> 						     MLX5_FLOW_NAMESPACE_FDB);</div><div class='ctx'> 	if (IS_ERR(e-&gt;pkt_reformat)) {</div><div class='hunk'>@@ -688,10 +698,6 @@ int mlx5e_tc_tun_update_header_ipv6(struct mlx5e_priv *priv,</div><div class='ctx'> 		goto free_encap;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	e-&gt;encap_size = ipv6_encap_size;</div><div class='del'>-	kfree(e-&gt;encap_header);</div><div class='del'>-	e-&gt;encap_header = encap_header;</div><div class='del'>-</div><div class='ctx'> 	e-&gt;flags |= MLX5_ENCAP_ENTRY_VALID;</div><div class='ctx'> 	mlx5e_rep_queue_neigh_stats_work(netdev_priv(attr.out_dev));</div><div class='ctx'> 	mlx5e_route_lookup_ipv6_put(&amp;attr);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c<br/>index b10e40e1a9c1..f1d1e1542e81 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c</a></div><div class='hunk'>@@ -1064,7 +1064,8 @@ int mlx5e_tc_tun_encap_dests_set(struct mlx5e_priv *priv,</div><div class='ctx'> </div><div class='ctx'> 		out_priv = netdev_priv(encap_dev);</div><div class='ctx'> 		rpriv = out_priv-&gt;ppriv;</div><div class='del'>-		esw_attr-&gt;dests[out_index].rep = rpriv-&gt;rep;</div><div class='add'>+		esw_attr-&gt;dests[out_index].vport_valid = true;</div><div class='add'>+		esw_attr-&gt;dests[out_index].vport = rpriv-&gt;rep-&gt;vport;</div><div class='ctx'> 		esw_attr-&gt;dests[out_index].mdev = out_priv-&gt;mdev;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c b/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c<br/>index 5620d9f97518..ac458a8d10e0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/trap.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/trap.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/trap.c</a></div><div class='hunk'>@@ -68,11 +68,13 @@ static int mlx5e_open_trap_rq(struct mlx5e_priv *priv, struct mlx5e_trap *t)</div><div class='ctx'> </div><div class='ctx'> 	node = dev_to_node(mdev-&gt;device);</div><div class='ctx'> </div><div class='add'>+	ccp.netdev   = priv-&gt;netdev;</div><div class='add'>+	ccp.wq       = priv-&gt;wq;</div><div class='ctx'> 	ccp.node     = node;</div><div class='ctx'> 	ccp.ch_stats = t-&gt;stats;</div><div class='ctx'> 	ccp.napi     = &amp;t-&gt;napi;</div><div class='ctx'> 	ccp.ix       = 0;</div><div class='del'>-	err = mlx5e_open_cq(priv, trap_moder, &amp;rq_param-&gt;cqp, &amp;ccp, &amp;rq-&gt;cq);</div><div class='add'>+	err = mlx5e_open_cq(priv-&gt;mdev, trap_moder, &amp;rq_param-&gt;cqp, &amp;ccp, &amp;rq-&gt;cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c<br/>index 7decc81ed33a..82b5ca1be4f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c</a></div><div class='hunk'>@@ -103,7 +103,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,</div><div class='ctx'> 		xdptxd-&gt;dma_addr = dma_addr;</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(!INDIRECT_CALL_2(sq-&gt;xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,</div><div class='del'>-					      mlx5e_xmit_xdp_frame, sq, xdptxd, 0)))</div><div class='add'>+					      mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL)))</div><div class='ctx'> 			return false;</div><div class='ctx'> </div><div class='ctx'> 		/* xmit_mode == MLX5E_XDP_XMIT_MODE_FRAME */</div><div class='hunk'>@@ -145,7 +145,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq,</div><div class='ctx'> 	xdptxd-&gt;dma_addr = dma_addr;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(!INDIRECT_CALL_2(sq-&gt;xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,</div><div class='del'>-				      mlx5e_xmit_xdp_frame, sq, xdptxd, 0)))</div><div class='add'>+				      mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL)))</div><div class='ctx'> 		return false;</div><div class='ctx'> </div><div class='ctx'> 	/* xmit_mode == MLX5E_XDP_XMIT_MODE_PAGE */</div><div class='hunk'>@@ -256,9 +256,55 @@ static int mlx5e_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mlx5e_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,</div><div class='add'>+				 u16 *vlan_tci)</div><div class='add'>+{</div><div class='add'>+	const struct mlx5e_xdp_buff *_ctx = (void *)ctx;</div><div class='add'>+	const struct mlx5_cqe64 *cqe = _ctx-&gt;cqe;</div><div class='add'>+</div><div class='add'>+	if (!cqe_has_vlan(cqe))</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	*vlan_proto = htons(ETH_P_8021Q);</div><div class='add'>+	*vlan_tci = be16_to_cpu(cqe-&gt;vlan_info);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct xdp_metadata_ops mlx5e_xdp_metadata_ops = {</div><div class='ctx'> 	.xmo_rx_timestamp		= mlx5e_xdp_rx_timestamp,</div><div class='ctx'> 	.xmo_rx_hash			= mlx5e_xdp_rx_hash,</div><div class='add'>+	.xmo_rx_vlan_tag		= mlx5e_xdp_rx_vlan_tag,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mlx5e_xsk_tx_complete {</div><div class='add'>+	struct mlx5_cqe64 *cqe;</div><div class='add'>+	struct mlx5e_cq *cq;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u64 mlx5e_xsk_fill_timestamp(void *_priv)</div><div class='add'>+{</div><div class='add'>+	struct mlx5e_xsk_tx_complete *priv = _priv;</div><div class='add'>+	u64 ts;</div><div class='add'>+</div><div class='add'>+	ts = get_cqe_ts(priv-&gt;cqe);</div><div class='add'>+</div><div class='add'>+	if (mlx5_is_real_time_rq(priv-&gt;cq-&gt;mdev) || mlx5_is_real_time_sq(priv-&gt;cq-&gt;mdev))</div><div class='add'>+		return mlx5_real_time_cyc2time(&amp;priv-&gt;cq-&gt;mdev-&gt;clock, ts);</div><div class='add'>+</div><div class='add'>+	return  mlx5_timecounter_cyc2time(&amp;priv-&gt;cq-&gt;mdev-&gt;clock, ts);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlx5e_xsk_request_checksum(u16 csum_start, u16 csum_offset, void *priv)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_wqe_eth_seg *eseg = priv;</div><div class='add'>+</div><div class='add'>+	/* HW/FW is doing parsing, so offsets are largely ignored. */</div><div class='add'>+	eseg-&gt;cs_flags |= MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct xsk_tx_metadata_ops mlx5e_xsk_tx_metadata_ops = {</div><div class='add'>+	.tmo_fill_timestamp		= mlx5e_xsk_fill_timestamp,</div><div class='add'>+	.tmo_request_checksum		= mlx5e_xsk_request_checksum,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* returns true if packet was consumed by xdp */</div><div class='hunk'>@@ -398,11 +444,11 @@ INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq</div><div class='ctx'> </div><div class='ctx'> INDIRECT_CALLABLE_SCOPE bool</div><div class='ctx'> mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='del'>-		     int check_result);</div><div class='add'>+		     int check_result, struct xsk_tx_metadata *meta);</div><div class='ctx'> </div><div class='ctx'> INDIRECT_CALLABLE_SCOPE bool</div><div class='ctx'> mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='del'>-			   int check_result)</div><div class='add'>+			   int check_result, struct xsk_tx_metadata *meta)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_tx_mpwqe *session = &amp;sq-&gt;mpwqe;</div><div class='ctx'> 	struct mlx5e_xdpsq_stats *stats = sq-&gt;stats;</div><div class='hunk'>@@ -420,7 +466,7 @@ mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptx</div><div class='ctx'> 			 */</div><div class='ctx'> 			if (unlikely(sq-&gt;mpwqe.wqe))</div><div class='ctx'> 				mlx5e_xdp_mpwqe_complete(sq);</div><div class='del'>-			return mlx5e_xmit_xdp_frame(sq, xdptxd, 0);</div><div class='add'>+			return mlx5e_xmit_xdp_frame(sq, xdptxd, 0, meta);</div><div class='ctx'> 		}</div><div class='ctx'> 		if (!xdptxd-&gt;len) {</div><div class='ctx'> 			skb_frag_t *frag = &amp;xdptxdf-&gt;sinfo-&gt;frags[0];</div><div class='hunk'>@@ -450,6 +496,7 @@ mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptx</div><div class='ctx'> 		 * and it's safe to complete it at any time.</div><div class='ctx'> 		 */</div><div class='ctx'> 		mlx5e_xdp_mpwqe_session_start(sq);</div><div class='add'>+		xsk_tx_metadata_request(meta, &amp;mlx5e_xsk_tx_metadata_ops, &amp;session-&gt;wqe-&gt;eth);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_xdp_mpwqe_add_dseg(sq, p, stats);</div><div class='hunk'>@@ -480,7 +527,7 @@ INDIRECT_CALLABLE_SCOPE int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)</div><div class='ctx'> </div><div class='ctx'> INDIRECT_CALLABLE_SCOPE bool</div><div class='ctx'> mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='del'>-		     int check_result)</div><div class='add'>+		     int check_result, struct xsk_tx_metadata *meta)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_xmit_data_frags *xdptxdf =</div><div class='ctx'> 		container_of(xdptxd, struct mlx5e_xmit_data_frags, xd);</div><div class='hunk'>@@ -493,6 +540,7 @@ mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='ctx'> 	dma_addr_t dma_addr = xdptxd-&gt;dma_addr;</div><div class='ctx'> 	u32 dma_len = xdptxd-&gt;len;</div><div class='ctx'> 	u16 ds_cnt, inline_hdr_sz;</div><div class='add'>+	unsigned int frags_size;</div><div class='ctx'> 	u8 num_wqebbs = 1;</div><div class='ctx'> 	int num_frags = 0;</div><div class='ctx'> 	bool inline_ok;</div><div class='hunk'>@@ -503,8 +551,9 @@ mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='ctx'> </div><div class='ctx'> 	inline_ok = sq-&gt;min_inline_mode == MLX5_INLINE_MODE_NONE ||</div><div class='ctx'> 		dma_len &gt;= MLX5E_XDP_MIN_INLINE;</div><div class='add'>+	frags_size = xdptxd-&gt;has_frags ? xdptxdf-&gt;sinfo-&gt;xdp_frags_size : 0;</div><div class='ctx'> </div><div class='del'>-	if (unlikely(!inline_ok || sq-&gt;hw_mtu &lt; dma_len)) {</div><div class='add'>+	if (unlikely(!inline_ok || sq-&gt;hw_mtu &lt; dma_len + frags_size)) {</div><div class='ctx'> 		stats-&gt;err++;</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -599,6 +648,8 @@ mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='ctx'> 		sq-&gt;pc++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	xsk_tx_metadata_request(meta, &amp;mlx5e_xsk_tx_metadata_ops, eseg);</div><div class='add'>+</div><div class='ctx'> 	sq-&gt;doorbell_cseg = cseg;</div><div class='ctx'> </div><div class='ctx'> 	stats-&gt;xmit++;</div><div class='hunk'>@@ -608,7 +659,9 @@ mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, struct mlx5e_xmit_data *xdptxd,</div><div class='ctx'> static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,</div><div class='ctx'> 				  struct mlx5e_xdp_wqe_info *wi,</div><div class='ctx'> 				  u32 *xsk_frames,</div><div class='del'>-				  struct xdp_frame_bulk *bq)</div><div class='add'>+				  struct xdp_frame_bulk *bq,</div><div class='add'>+				  struct mlx5e_cq *cq,</div><div class='add'>+				  struct mlx5_cqe64 *cqe)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_xdp_info_fifo *xdpi_fifo = &amp;sq-&gt;db.xdpi_fifo;</div><div class='ctx'> 	u16 i;</div><div class='hunk'>@@ -668,10 +721,24 @@ static void mlx5e_free_xdpsq_desc(struct mlx5e_xdpsq *sq,</div><div class='ctx'> </div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='del'>-		case MLX5E_XDP_XMIT_MODE_XSK:</div><div class='add'>+		case MLX5E_XDP_XMIT_MODE_XSK: {</div><div class='ctx'> 			/* AF_XDP send */</div><div class='add'>+			struct xsk_tx_metadata_compl *compl = NULL;</div><div class='add'>+			struct mlx5e_xsk_tx_complete priv = {</div><div class='add'>+				.cqe = cqe,</div><div class='add'>+				.cq = cq,</div><div class='add'>+			};</div><div class='add'>+</div><div class='add'>+			if (xp_tx_metadata_enabled(sq-&gt;xsk_pool)) {</div><div class='add'>+				xdpi = mlx5e_xdpi_fifo_pop(xdpi_fifo);</div><div class='add'>+				compl = &amp;xdpi.xsk_meta;</div><div class='add'>+</div><div class='add'>+				xsk_tx_metadata_complete(compl, &amp;mlx5e_xsk_tx_metadata_ops, &amp;priv);</div><div class='add'>+			}</div><div class='add'>+</div><div class='ctx'> 			(*xsk_frames)++;</div><div class='ctx'> 			break;</div><div class='add'>+		}</div><div class='ctx'> 		default:</div><div class='ctx'> 			WARN_ON_ONCE(true);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -720,7 +787,7 @@ bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)</div><div class='ctx'> </div><div class='ctx'> 			sqcc += wi-&gt;num_wqebbs;</div><div class='ctx'> </div><div class='del'>-			mlx5e_free_xdpsq_desc(sq, wi, &amp;xsk_frames, &amp;bq);</div><div class='add'>+			mlx5e_free_xdpsq_desc(sq, wi, &amp;xsk_frames, &amp;bq, cq, cqe);</div><div class='ctx'> 		} while (!last_wqe);</div><div class='ctx'> </div><div class='ctx'> 		if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {</div><div class='hunk'>@@ -767,7 +834,7 @@ void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)</div><div class='ctx'> </div><div class='ctx'> 		sq-&gt;cc += wi-&gt;num_wqebbs;</div><div class='ctx'> </div><div class='del'>-		mlx5e_free_xdpsq_desc(sq, wi, &amp;xsk_frames, &amp;bq);</div><div class='add'>+		mlx5e_free_xdpsq_desc(sq, wi, &amp;xsk_frames, &amp;bq, NULL, NULL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	xdp_flush_frame_bulk(&amp;bq);</div><div class='hunk'>@@ -840,7 +907,7 @@ int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = INDIRECT_CALL_2(sq-&gt;xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,</div><div class='del'>-				      mlx5e_xmit_xdp_frame, sq, xdptxd, 0);</div><div class='add'>+				      mlx5e_xmit_xdp_frame, sq, xdptxd, 0, NULL);</div><div class='ctx'> 		if (unlikely(!ret)) {</div><div class='ctx'> 			int j;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h<br/>index ecfe93a479da..e054db1e10f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h</a></div><div class='hunk'>@@ -33,6 +33,7 @@</div><div class='ctx'> #define __MLX5_EN_XDP_H__</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/indirect_call_wrapper.h&gt;</div><div class='add'>+#include &lt;net/xdp_sock.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "en.h"</div><div class='ctx'> #include "en/txrx.h"</div><div class='hunk'>@@ -82,7 +83,7 @@ enum mlx5e_xdp_xmit_mode {</div><div class='ctx'>  *    num, page_1, page_2, ... , page_num.</div><div class='ctx'>  *</div><div class='ctx'>  * MLX5E_XDP_XMIT_MODE_XSK:</div><div class='del'>- *    none.</div><div class='add'>+ *    frame.xsk_meta.</div><div class='ctx'>  */</div><div class='ctx'> #define MLX5E_XDP_FIFO_ENTRIES2DS_MAX_RATIO 4</div><div class='ctx'> </div><div class='hunk'>@@ -97,6 +98,7 @@ union mlx5e_xdp_info {</div><div class='ctx'> 		u8 num;</div><div class='ctx'> 		struct page *page;</div><div class='ctx'> 	} page;</div><div class='add'>+	struct xsk_tx_metadata_compl xsk_meta;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_xsk_param;</div><div class='hunk'>@@ -112,13 +114,16 @@ int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,</div><div class='ctx'> 		   u32 flags);</div><div class='ctx'> </div><div class='ctx'> extern const struct xdp_metadata_ops mlx5e_xdp_metadata_ops;</div><div class='add'>+extern const struct xsk_tx_metadata_ops mlx5e_xsk_tx_metadata_ops;</div><div class='ctx'> </div><div class='ctx'> INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq,</div><div class='ctx'> 							  struct mlx5e_xmit_data *xdptxd,</div><div class='del'>-							  int check_result));</div><div class='add'>+							  int check_result,</div><div class='add'>+							  struct xsk_tx_metadata *meta));</div><div class='ctx'> INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq,</div><div class='ctx'> 						    struct mlx5e_xmit_data *xdptxd,</div><div class='del'>-						    int check_result));</div><div class='add'>+						    int check_result,</div><div class='add'>+						    struct xsk_tx_metadata *meta));</div><div class='ctx'> INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq));</div><div class='ctx'> INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq));</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c<br/>index 36826b582484..82e6abbc1734 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c</a></div><div class='hunk'>@@ -127,7 +127,7 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params,</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_build_xsk_cparam(priv-&gt;mdev, params, xsk, priv-&gt;q_counter, cparam);</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, params-&gt;rx_cq_moderation, &amp;cparam-&gt;rq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, params-&gt;rx_cq_moderation, &amp;cparam-&gt;rq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;xskrq.cq);</div><div class='ctx'> 	if (unlikely(err))</div><div class='ctx'> 		goto err_free_cparam;</div><div class='hunk'>@@ -136,7 +136,7 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params,</div><div class='ctx'> 	if (unlikely(err))</div><div class='ctx'> 		goto err_close_rx_cq;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;xsksq.cq);</div><div class='ctx'> 	if (unlikely(err))</div><div class='ctx'> 		goto err_close_rq;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c<br/>index 597f319d4770..a59199ed590d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en/xsk/tx.c</a></div><div class='hunk'>@@ -55,12 +55,16 @@ static void mlx5e_xsk_tx_post_err(struct mlx5e_xdpsq *sq,</div><div class='ctx'> </div><div class='ctx'> 	nopwqe = mlx5e_post_nop(&amp;sq-&gt;wq, sq-&gt;sqn, &amp;sq-&gt;pc);</div><div class='ctx'> 	mlx5e_xdpi_fifo_push(&amp;sq-&gt;db.xdpi_fifo, *xdpi);</div><div class='add'>+	if (xp_tx_metadata_enabled(sq-&gt;xsk_pool))</div><div class='add'>+		mlx5e_xdpi_fifo_push(&amp;sq-&gt;db.xdpi_fifo,</div><div class='add'>+				     (union mlx5e_xdp_info) { .xsk_meta = {} });</div><div class='ctx'> 	sq-&gt;doorbell_cseg = &amp;nopwqe-&gt;ctrl;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool mlx5e_xsk_tx(struct mlx5e_xdpsq *sq, unsigned int budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct xsk_buff_pool *pool = sq-&gt;xsk_pool;</div><div class='add'>+	struct xsk_tx_metadata *meta = NULL;</div><div class='ctx'> 	union mlx5e_xdp_info xdpi;</div><div class='ctx'> 	bool work_done = true;</div><div class='ctx'> 	bool flush = false;</div><div class='hunk'>@@ -93,12 +97,13 @@ bool mlx5e_xsk_tx(struct mlx5e_xdpsq *sq, unsigned int budget)</div><div class='ctx'> 		xdptxd.dma_addr = xsk_buff_raw_get_dma(pool, desc.addr);</div><div class='ctx'> 		xdptxd.data = xsk_buff_raw_get_data(pool, desc.addr);</div><div class='ctx'> 		xdptxd.len = desc.len;</div><div class='add'>+		meta = xsk_buff_get_metadata(pool, desc.addr);</div><div class='ctx'> </div><div class='ctx'> 		xsk_buff_raw_dma_sync_for_device(pool, xdptxd.dma_addr, xdptxd.len);</div><div class='ctx'> </div><div class='ctx'> 		ret = INDIRECT_CALL_2(sq-&gt;xmit_xdp_frame, mlx5e_xmit_xdp_frame_mpwqe,</div><div class='ctx'> 				      mlx5e_xmit_xdp_frame, sq, &amp;xdptxd,</div><div class='del'>-				      check_result);</div><div class='add'>+				      check_result, meta);</div><div class='ctx'> 		if (unlikely(!ret)) {</div><div class='ctx'> 			if (sq-&gt;mpwqe.wqe)</div><div class='ctx'> 				mlx5e_xdp_mpwqe_complete(sq);</div><div class='hunk'>@@ -106,6 +111,16 @@ bool mlx5e_xsk_tx(struct mlx5e_xdpsq *sq, unsigned int budget)</div><div class='ctx'> 			mlx5e_xsk_tx_post_err(sq, &amp;xdpi);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			mlx5e_xdpi_fifo_push(&amp;sq-&gt;db.xdpi_fifo, xdpi);</div><div class='add'>+			if (xp_tx_metadata_enabled(sq-&gt;xsk_pool)) {</div><div class='add'>+				struct xsk_tx_metadata_compl compl;</div><div class='add'>+</div><div class='add'>+				xsk_tx_metadata_to_compl(meta, &amp;compl);</div><div class='add'>+				XSK_TX_COMPL_FITS(void *);</div><div class='add'>+</div><div class='add'>+				mlx5e_xdpi_fifo_push(&amp;sq-&gt;db.xdpi_fifo,</div><div class='add'>+						     (union mlx5e_xdp_info)</div><div class='add'>+						     { .xsk_meta = compl });</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		flush = true;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c<br/>index 655496598c68..161c5190c236 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c</a></div><div class='hunk'>@@ -121,7 +121,14 @@ static bool mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> 	if (x-&gt;xso.type == XFRM_DEV_OFFLOAD_CRYPTO)</div><div class='ctx'> 		esn_msb = xfrm_replay_seqhi(x, htonl(seq_bottom));</div><div class='ctx'> </div><div class='del'>-	sa_entry-&gt;esn_state.esn = esn;</div><div class='add'>+	if (sa_entry-&gt;esn_state.esn_msb)</div><div class='add'>+		sa_entry-&gt;esn_state.esn = esn;</div><div class='add'>+	else</div><div class='add'>+		/* According to RFC4303, section "3.3.3. Sequence Number Generation",</div><div class='add'>+		 * the first packet sent using a given SA will contain a sequence</div><div class='add'>+		 * number of 1.</div><div class='add'>+		 */</div><div class='add'>+		sa_entry-&gt;esn_state.esn = max_t(u32, esn, 1);</div><div class='ctx'> 	sa_entry-&gt;esn_state.esn_msb = esn_msb;</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(overlap &amp;&amp; seq_bottom &lt; MLX5E_IPSEC_ESN_SCOPE_MID)) {</div><div class='hunk'>@@ -335,6 +342,27 @@ void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry,</div><div class='ctx'> 		attrs-&gt;replay_esn.esn = sa_entry-&gt;esn_state.esn;</div><div class='ctx'> 		attrs-&gt;replay_esn.esn_msb = sa_entry-&gt;esn_state.esn_msb;</div><div class='ctx'> 		attrs-&gt;replay_esn.overlap = sa_entry-&gt;esn_state.overlap;</div><div class='add'>+		switch (x-&gt;replay_esn-&gt;replay_window) {</div><div class='add'>+		case 32:</div><div class='add'>+			attrs-&gt;replay_esn.replay_window =</div><div class='add'>+				MLX5_IPSEC_ASO_REPLAY_WIN_32BIT;</div><div class='add'>+			break;</div><div class='add'>+		case 64:</div><div class='add'>+			attrs-&gt;replay_esn.replay_window =</div><div class='add'>+				MLX5_IPSEC_ASO_REPLAY_WIN_64BIT;</div><div class='add'>+			break;</div><div class='add'>+		case 128:</div><div class='add'>+			attrs-&gt;replay_esn.replay_window =</div><div class='add'>+				MLX5_IPSEC_ASO_REPLAY_WIN_128BIT;</div><div class='add'>+			break;</div><div class='add'>+		case 256:</div><div class='add'>+			attrs-&gt;replay_esn.replay_window =</div><div class='add'>+				MLX5_IPSEC_ASO_REPLAY_WIN_256BIT;</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			WARN_ON(true);</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	attrs-&gt;dir = x-&gt;xso.dir;</div><div class='hunk'>@@ -907,9 +935,11 @@ void mlx5e_ipsec_cleanup(struct mlx5e_priv *priv)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_accel_ipsec_fs_cleanup(ipsec);</div><div class='del'>-	if (mlx5_ipsec_device_caps(priv-&gt;mdev) &amp; MLX5_IPSEC_CAP_TUNNEL)</div><div class='add'>+	if (ipsec-&gt;netevent_nb.notifier_call) {</div><div class='ctx'> 		unregister_netevent_notifier(&amp;ipsec-&gt;netevent_nb);</div><div class='del'>-	if (mlx5_ipsec_device_caps(priv-&gt;mdev) &amp; MLX5_IPSEC_CAP_PACKET_OFFLOAD)</div><div class='add'>+		ipsec-&gt;netevent_nb.notifier_call = NULL;</div><div class='add'>+	}</div><div class='add'>+	if (ipsec-&gt;aso)</div><div class='ctx'> 		mlx5e_ipsec_aso_cleanup(ipsec);</div><div class='ctx'> 	destroy_workqueue(ipsec-&gt;wq);</div><div class='ctx'> 	kfree(ipsec);</div><div class='hunk'>@@ -1018,6 +1048,12 @@ static int mlx5e_xfrm_validate_policy(struct mlx5_core_dev *mdev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (x-&gt;xdo.type == XFRM_DEV_OFFLOAD_PACKET &amp;&amp;</div><div class='add'>+	    !(mlx5_ipsec_device_caps(mdev) &amp; MLX5_IPSEC_CAP_PACKET_OFFLOAD)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Packet offload is not supported");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1113,14 +1149,6 @@ static const struct xfrmdev_ops mlx5e_ipsec_xfrmdev_ops = {</div><div class='ctx'> 	.xdo_dev_state_free	= mlx5e_xfrm_free_state,</div><div class='ctx'> 	.xdo_dev_offload_ok	= mlx5e_ipsec_offload_ok,</div><div class='ctx'> 	.xdo_dev_state_advance_esn = mlx5e_xfrm_advance_esn_state,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct xfrmdev_ops mlx5e_ipsec_packet_xfrmdev_ops = {</div><div class='del'>-	.xdo_dev_state_add	= mlx5e_xfrm_add_state,</div><div class='del'>-	.xdo_dev_state_delete	= mlx5e_xfrm_del_state,</div><div class='del'>-	.xdo_dev_state_free	= mlx5e_xfrm_free_state,</div><div class='del'>-	.xdo_dev_offload_ok	= mlx5e_ipsec_offload_ok,</div><div class='del'>-	.xdo_dev_state_advance_esn = mlx5e_xfrm_advance_esn_state,</div><div class='ctx'> </div><div class='ctx'> 	.xdo_dev_state_update_curlft = mlx5e_xfrm_update_curlft,</div><div class='ctx'> 	.xdo_dev_policy_add = mlx5e_xfrm_add_policy,</div><div class='hunk'>@@ -1138,11 +1166,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)</div><div class='ctx'> </div><div class='ctx'> 	mlx5_core_info(mdev, "mlx5e: IPSec ESP acceleration enabled\n");</div><div class='ctx'> </div><div class='del'>-	if (mlx5_ipsec_device_caps(mdev) &amp; MLX5_IPSEC_CAP_PACKET_OFFLOAD)</div><div class='del'>-		netdev-&gt;xfrmdev_ops = &amp;mlx5e_ipsec_packet_xfrmdev_ops;</div><div class='del'>-	else</div><div class='del'>-		netdev-&gt;xfrmdev_ops = &amp;mlx5e_ipsec_xfrmdev_ops;</div><div class='del'>-</div><div class='add'>+	netdev-&gt;xfrmdev_ops = &amp;mlx5e_ipsec_xfrmdev_ops;</div><div class='ctx'> 	netdev-&gt;features |= NETIF_F_HW_ESP;</div><div class='ctx'> 	netdev-&gt;hw_enc_features |= NETIF_F_HW_ESP;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h<br/>index 8f4a37bceaf4..adaea3493193 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h</a></div><div class='hunk'>@@ -189,11 +189,19 @@ struct mlx5e_ipsec_ft {</div><div class='ctx'> 	u32 refcnt;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mlx5e_ipsec_drop {</div><div class='add'>+	struct mlx5_flow_handle *rule;</div><div class='add'>+	struct mlx5_fc *fc;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mlx5e_ipsec_rule {</div><div class='ctx'> 	struct mlx5_flow_handle *rule;</div><div class='ctx'> 	struct mlx5_modify_hdr *modify_hdr;</div><div class='ctx'> 	struct mlx5_pkt_reformat *pkt_reformat;</div><div class='ctx'> 	struct mlx5_fc *fc;</div><div class='add'>+	struct mlx5e_ipsec_drop replay;</div><div class='add'>+	struct mlx5e_ipsec_drop auth;</div><div class='add'>+	struct mlx5e_ipsec_drop trailer;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_ipsec_miss {</div><div class='hunk'>@@ -201,19 +209,6 @@ struct mlx5e_ipsec_miss {</div><div class='ctx'> 	struct mlx5_flow_handle *rule;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct mlx5e_ipsec_rx {</div><div class='del'>-	struct mlx5e_ipsec_ft ft;</div><div class='del'>-	struct mlx5e_ipsec_miss pol;</div><div class='del'>-	struct mlx5e_ipsec_miss sa;</div><div class='del'>-	struct mlx5e_ipsec_rule status;</div><div class='del'>-	struct mlx5e_ipsec_miss status_drop;</div><div class='del'>-	struct mlx5_fc *status_drop_cnt;</div><div class='del'>-	struct mlx5e_ipsec_fc *fc;</div><div class='del'>-	struct mlx5_fs_chains *chains;</div><div class='del'>-	u8 allow_tunnel_mode : 1;</div><div class='del'>-	struct xarray ipsec_obj_id_map;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> struct mlx5e_ipsec_tx_create_attr {</div><div class='ctx'> 	int prio;</div><div class='ctx'> 	int pol_level;</div><div class='hunk'>@@ -248,6 +243,7 @@ struct mlx5e_ipsec {</div><div class='ctx'> 	struct mlx5_ipsec_fs *roce;</div><div class='ctx'> 	u8 is_uplink_rep: 1;</div><div class='ctx'> 	struct mlx5e_ipsec_mpv_work mpv_work;</div><div class='add'>+	struct xarray ipsec_obj_id_map;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_ipsec_esn_state {</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c<br/>index f41c976dc33f..41a2543a52cd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c</a></div><div class='hunk'>@@ -32,6 +32,22 @@ struct mlx5e_ipsec_tx {</div><div class='ctx'> 	u8 allow_tunnel_mode : 1;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mlx5e_ipsec_status_checks {</div><div class='add'>+	struct mlx5_flow_group *drop_all_group;</div><div class='add'>+	struct mlx5e_ipsec_drop all;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mlx5e_ipsec_rx {</div><div class='add'>+	struct mlx5e_ipsec_ft ft;</div><div class='add'>+	struct mlx5e_ipsec_miss pol;</div><div class='add'>+	struct mlx5e_ipsec_miss sa;</div><div class='add'>+	struct mlx5e_ipsec_rule status;</div><div class='add'>+	struct mlx5e_ipsec_status_checks status_drops;</div><div class='add'>+	struct mlx5e_ipsec_fc *fc;</div><div class='add'>+	struct mlx5_fs_chains *chains;</div><div class='add'>+	u8 allow_tunnel_mode : 1;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* IPsec RX flow steering */</div><div class='ctx'> static enum mlx5_traffic_types family2tt(u32 family)</div><div class='ctx'> {</div><div class='hunk'>@@ -128,14 +144,37 @@ static struct mlx5_flow_table *ipsec_ft_create(struct mlx5_flow_namespace *ns,</div><div class='ctx'> 	return mlx5_create_auto_grouped_flow_table(ns, &amp;ft_attr);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ipsec_status_rule(struct mlx5_core_dev *mdev,</div><div class='del'>-			     struct mlx5e_ipsec_rx *rx,</div><div class='del'>-			     struct mlx5_flow_destination *dest)</div><div class='add'>+static void ipsec_rx_status_drop_destroy(struct mlx5e_ipsec *ipsec,</div><div class='add'>+					 struct mlx5e_ipsec_rx *rx)</div><div class='add'>+{</div><div class='add'>+	mlx5_del_flow_rules(rx-&gt;status_drops.all.rule);</div><div class='add'>+	mlx5_fc_destroy(ipsec-&gt;mdev, rx-&gt;status_drops.all.fc);</div><div class='add'>+	mlx5_destroy_flow_group(rx-&gt;status_drops.drop_all_group);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ipsec_rx_status_pass_destroy(struct mlx5e_ipsec *ipsec,</div><div class='add'>+					 struct mlx5e_ipsec_rx *rx)</div><div class='ctx'> {</div><div class='del'>-	u8 action[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};</div><div class='add'>+	mlx5_del_flow_rules(rx-&gt;status.rule);</div><div class='add'>+</div><div class='add'>+	if (rx != ipsec-&gt;rx_esw)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+#ifdef CONFIG_MLX5_ESWITCH</div><div class='add'>+	mlx5_chains_put_table(esw_chains(ipsec-&gt;mdev-&gt;priv.eswitch), 0, 1, 0);</div><div class='add'>+#endif</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rx_add_rule_drop_auth_trailer(struct mlx5e_ipsec_sa_entry *sa_entry,</div><div class='add'>+					 struct mlx5e_ipsec_rx *rx)</div><div class='add'>+{</div><div class='add'>+	struct mlx5e_ipsec *ipsec = sa_entry-&gt;ipsec;</div><div class='add'>+	struct mlx5_flow_table *ft = rx-&gt;ft.status;</div><div class='add'>+	struct mlx5_core_dev *mdev = ipsec-&gt;mdev;</div><div class='add'>+	struct mlx5_flow_destination dest = {};</div><div class='ctx'> 	struct mlx5_flow_act flow_act = {};</div><div class='del'>-	struct mlx5_modify_hdr *modify_hdr;</div><div class='del'>-	struct mlx5_flow_handle *fte;</div><div class='add'>+	struct mlx5_flow_handle *rule;</div><div class='add'>+	struct mlx5_fc *flow_counter;</div><div class='ctx'> 	struct mlx5_flow_spec *spec;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -143,48 +182,273 @@ static int ipsec_status_rule(struct mlx5_core_dev *mdev,</div><div class='ctx'> 	if (!spec)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	/* Action to copy 7 bit ipsec_syndrome to regB[24:30] */</div><div class='del'>-	MLX5_SET(copy_action_in, action, action_type, MLX5_ACTION_TYPE_COPY);</div><div class='del'>-	MLX5_SET(copy_action_in, action, src_field, MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME);</div><div class='del'>-	MLX5_SET(copy_action_in, action, src_offset, 0);</div><div class='del'>-	MLX5_SET(copy_action_in, action, length, 7);</div><div class='del'>-	MLX5_SET(copy_action_in, action, dst_field, MLX5_ACTION_IN_FIELD_METADATA_REG_B);</div><div class='del'>-	MLX5_SET(copy_action_in, action, dst_offset, 24);</div><div class='add'>+	flow_counter = mlx5_fc_create(mdev, true);</div><div class='add'>+	if (IS_ERR(flow_counter)) {</div><div class='add'>+		err = PTR_ERR(flow_counter);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule counter, err=%d\n", err);</div><div class='add'>+		goto err_cnt;</div><div class='add'>+	}</div><div class='add'>+	sa_entry-&gt;ipsec_rule.auth.fc = flow_counter;</div><div class='ctx'> </div><div class='del'>-	modify_hdr = mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_KERNEL,</div><div class='del'>-					      1, action);</div><div class='add'>+	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP | MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='add'>+	flow_act.flags = FLOW_ACT_NO_APPEND;</div><div class='add'>+	dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;</div><div class='add'>+	dest.counter_id = mlx5_fc_id(flow_counter);</div><div class='add'>+	if (rx == ipsec-&gt;rx_esw)</div><div class='add'>+		spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='ctx'> </div><div class='del'>-	if (IS_ERR(modify_hdr)) {</div><div class='del'>-		err = PTR_ERR(modify_hdr);</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria, misc_parameters_2.ipsec_syndrome);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value, misc_parameters_2.ipsec_syndrome, 1);</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria, misc_parameters_2.metadata_reg_c_2);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='add'>+		 misc_parameters_2.metadata_reg_c_2,</div><div class='add'>+		 sa_entry-&gt;ipsec_obj_id | BIT(31));</div><div class='add'>+	spec-&gt;match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;</div><div class='add'>+	rule = mlx5_add_flow_rules(ft, spec, &amp;flow_act, &amp;dest, 1);</div><div class='add'>+	if (IS_ERR(rule)) {</div><div class='add'>+		err = PTR_ERR(rule);</div><div class='ctx'> 		mlx5_core_err(mdev,</div><div class='del'>-			      "fail to alloc ipsec copy modify_header_id err=%d\n", err);</div><div class='del'>-		goto out_spec;</div><div class='add'>+			      "Failed to add ipsec rx status drop rule, err=%d\n", err);</div><div class='add'>+		goto err_rule;</div><div class='ctx'> 	}</div><div class='add'>+	sa_entry-&gt;ipsec_rule.auth.rule = rule;</div><div class='ctx'> </div><div class='del'>-	/* create fte */</div><div class='del'>-	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |</div><div class='del'>-			  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |</div><div class='add'>+	flow_counter = mlx5_fc_create(mdev, true);</div><div class='add'>+	if (IS_ERR(flow_counter)) {</div><div class='add'>+		err = PTR_ERR(flow_counter);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule counter, err=%d\n", err);</div><div class='add'>+		goto err_cnt_2;</div><div class='add'>+	}</div><div class='add'>+	sa_entry-&gt;ipsec_rule.trailer.fc = flow_counter;</div><div class='add'>+</div><div class='add'>+	dest.counter_id = mlx5_fc_id(flow_counter);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value, misc_parameters_2.ipsec_syndrome, 2);</div><div class='add'>+	rule = mlx5_add_flow_rules(ft, spec, &amp;flow_act, &amp;dest, 1);</div><div class='add'>+	if (IS_ERR(rule)) {</div><div class='add'>+		err = PTR_ERR(rule);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule, err=%d\n", err);</div><div class='add'>+		goto err_rule_2;</div><div class='add'>+	}</div><div class='add'>+	sa_entry-&gt;ipsec_rule.trailer.rule = rule;</div><div class='add'>+</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_rule_2:</div><div class='add'>+	mlx5_fc_destroy(mdev, sa_entry-&gt;ipsec_rule.trailer.fc);</div><div class='add'>+err_cnt_2:</div><div class='add'>+	mlx5_del_flow_rules(sa_entry-&gt;ipsec_rule.auth.rule);</div><div class='add'>+err_rule:</div><div class='add'>+	mlx5_fc_destroy(mdev, sa_entry-&gt;ipsec_rule.auth.fc);</div><div class='add'>+err_cnt:</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rx_add_rule_drop_replay(struct mlx5e_ipsec_sa_entry *sa_entry, struct mlx5e_ipsec_rx *rx)</div><div class='add'>+{</div><div class='add'>+	struct mlx5e_ipsec *ipsec = sa_entry-&gt;ipsec;</div><div class='add'>+	struct mlx5_flow_table *ft = rx-&gt;ft.status;</div><div class='add'>+	struct mlx5_core_dev *mdev = ipsec-&gt;mdev;</div><div class='add'>+	struct mlx5_flow_destination dest = {};</div><div class='add'>+	struct mlx5_flow_act flow_act = {};</div><div class='add'>+	struct mlx5_flow_handle *rule;</div><div class='add'>+	struct mlx5_fc *flow_counter;</div><div class='add'>+	struct mlx5_flow_spec *spec;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='add'>+	if (!spec)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	flow_counter = mlx5_fc_create(mdev, true);</div><div class='add'>+	if (IS_ERR(flow_counter)) {</div><div class='add'>+		err = PTR_ERR(flow_counter);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule counter, err=%d\n", err);</div><div class='add'>+		goto err_cnt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP | MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='add'>+	flow_act.flags = FLOW_ACT_NO_APPEND;</div><div class='add'>+	dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;</div><div class='add'>+	dest.counter_id = mlx5_fc_id(flow_counter);</div><div class='add'>+	if (rx == ipsec-&gt;rx_esw)</div><div class='add'>+		spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='add'>+</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria, misc_parameters_2.metadata_reg_c_4);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value, misc_parameters_2.metadata_reg_c_4, 1);</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria, misc_parameters_2.metadata_reg_c_2);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value,  misc_parameters_2.metadata_reg_c_2,</div><div class='add'>+		 sa_entry-&gt;ipsec_obj_id | BIT(31));</div><div class='add'>+	spec-&gt;match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;</div><div class='add'>+	rule = mlx5_add_flow_rules(ft, spec, &amp;flow_act, &amp;dest, 1);</div><div class='add'>+	if (IS_ERR(rule)) {</div><div class='add'>+		err = PTR_ERR(rule);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule, err=%d\n", err);</div><div class='add'>+		goto err_rule;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	sa_entry-&gt;ipsec_rule.replay.rule = rule;</div><div class='add'>+	sa_entry-&gt;ipsec_rule.replay.fc = flow_counter;</div><div class='add'>+</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_rule:</div><div class='add'>+	mlx5_fc_destroy(mdev, flow_counter);</div><div class='add'>+err_cnt:</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ipsec_rx_status_drop_all_create(struct mlx5e_ipsec *ipsec,</div><div class='add'>+					   struct mlx5e_ipsec_rx *rx)</div><div class='add'>+{</div><div class='add'>+	int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);</div><div class='add'>+	struct mlx5_flow_table *ft = rx-&gt;ft.status;</div><div class='add'>+	struct mlx5_core_dev *mdev = ipsec-&gt;mdev;</div><div class='add'>+	struct mlx5_flow_destination dest = {};</div><div class='add'>+	struct mlx5_flow_act flow_act = {};</div><div class='add'>+	struct mlx5_flow_handle *rule;</div><div class='add'>+	struct mlx5_fc *flow_counter;</div><div class='add'>+	struct mlx5_flow_spec *spec;</div><div class='add'>+	struct mlx5_flow_group *g;</div><div class='add'>+	u32 *flow_group_in;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	flow_group_in = kvzalloc(inlen, GFP_KERNEL);</div><div class='add'>+	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='add'>+	if (!flow_group_in || !spec) {</div><div class='add'>+		err = -ENOMEM;</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ft-&gt;max_fte - 1);</div><div class='add'>+	MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ft-&gt;max_fte - 1);</div><div class='add'>+	g = mlx5_create_flow_group(ft, flow_group_in);</div><div class='add'>+	if (IS_ERR(g)) {</div><div class='add'>+		err = PTR_ERR(g);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop flow group, err=%d\n", err);</div><div class='add'>+		goto err_out;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	flow_counter = mlx5_fc_create(mdev, false);</div><div class='add'>+	if (IS_ERR(flow_counter)) {</div><div class='add'>+		err = PTR_ERR(flow_counter);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule counter, err=%d\n", err);</div><div class='add'>+		goto err_cnt;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP | MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='add'>+	dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;</div><div class='add'>+	dest.counter_id = mlx5_fc_id(flow_counter);</div><div class='add'>+	if (rx == ipsec-&gt;rx_esw)</div><div class='add'>+		spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='add'>+	rule = mlx5_add_flow_rules(ft, spec, &amp;flow_act, &amp;dest, 1);</div><div class='add'>+	if (IS_ERR(rule)) {</div><div class='add'>+		err = PTR_ERR(rule);</div><div class='add'>+		mlx5_core_err(mdev,</div><div class='add'>+			      "Failed to add ipsec rx status drop rule, err=%d\n", err);</div><div class='add'>+		goto err_rule;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rx-&gt;status_drops.drop_all_group = g;</div><div class='add'>+	rx-&gt;status_drops.all.rule = rule;</div><div class='add'>+	rx-&gt;status_drops.all.fc = flow_counter;</div><div class='add'>+</div><div class='add'>+	kvfree(flow_group_in);</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_rule:</div><div class='add'>+	mlx5_fc_destroy(mdev, flow_counter);</div><div class='add'>+err_cnt:</div><div class='add'>+	mlx5_destroy_flow_group(g);</div><div class='add'>+err_out:</div><div class='add'>+	kvfree(flow_group_in);</div><div class='add'>+	kvfree(spec);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ipsec_rx_status_pass_create(struct mlx5e_ipsec *ipsec,</div><div class='add'>+				       struct mlx5e_ipsec_rx *rx,</div><div class='add'>+				       struct mlx5_flow_destination *dest)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_flow_act flow_act = {};</div><div class='add'>+	struct mlx5_flow_handle *rule;</div><div class='add'>+	struct mlx5_flow_spec *spec;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='add'>+	if (!spec)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria,</div><div class='add'>+			 misc_parameters_2.ipsec_syndrome);</div><div class='add'>+	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria,</div><div class='add'>+			 misc_parameters_2.metadata_reg_c_4);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='add'>+		 misc_parameters_2.ipsec_syndrome, 0);</div><div class='add'>+	MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='add'>+		 misc_parameters_2.metadata_reg_c_4, 0);</div><div class='add'>+	if (rx == ipsec-&gt;rx_esw)</div><div class='add'>+		spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='add'>+	spec-&gt;match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;</div><div class='add'>+	flow_act.flags = FLOW_ACT_NO_APPEND;</div><div class='add'>+	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |</div><div class='ctx'> 			  MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='del'>-	flow_act.modify_hdr = modify_hdr;</div><div class='del'>-	fte = mlx5_add_flow_rules(rx-&gt;ft.status, spec, &amp;flow_act, dest, 2);</div><div class='del'>-	if (IS_ERR(fte)) {</div><div class='del'>-		err = PTR_ERR(fte);</div><div class='del'>-		mlx5_core_err(mdev, "fail to add ipsec rx err copy rule err=%d\n", err);</div><div class='del'>-		goto out;</div><div class='add'>+	rule = mlx5_add_flow_rules(rx-&gt;ft.status, spec, &amp;flow_act, dest, 2);</div><div class='add'>+	if (IS_ERR(rule)) {</div><div class='add'>+		err = PTR_ERR(rule);</div><div class='add'>+		mlx5_core_warn(ipsec-&gt;mdev,</div><div class='add'>+			       "Failed to add ipsec rx status pass rule, err=%d\n", err);</div><div class='add'>+		goto err_rule;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	rx-&gt;status.rule = rule;</div><div class='ctx'> 	kvfree(spec);</div><div class='del'>-	rx-&gt;status.rule = fte;</div><div class='del'>-	rx-&gt;status.modify_hdr = modify_hdr;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-out:</div><div class='del'>-	mlx5_modify_header_dealloc(mdev, modify_hdr);</div><div class='del'>-out_spec:</div><div class='add'>+err_rule:</div><div class='ctx'> 	kvfree(spec);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mlx5_ipsec_rx_status_destroy(struct mlx5e_ipsec *ipsec,</div><div class='add'>+					 struct mlx5e_ipsec_rx *rx)</div><div class='add'>+{</div><div class='add'>+	ipsec_rx_status_pass_destroy(ipsec, rx);</div><div class='add'>+	ipsec_rx_status_drop_destroy(ipsec, rx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx5_ipsec_rx_status_create(struct mlx5e_ipsec *ipsec,</div><div class='add'>+				       struct mlx5e_ipsec_rx *rx,</div><div class='add'>+				       struct mlx5_flow_destination *dest)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = ipsec_rx_status_drop_all_create(ipsec, rx);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = ipsec_rx_status_pass_create(ipsec, rx, dest);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_pass_create;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_pass_create:</div><div class='add'>+	ipsec_rx_status_drop_destroy(ipsec, rx);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ipsec_miss_create(struct mlx5_core_dev *mdev,</div><div class='ctx'> 			     struct mlx5_flow_table *ft,</div><div class='ctx'> 			     struct mlx5e_ipsec_miss *miss,</div><div class='hunk'>@@ -333,12 +597,7 @@ static void rx_destroy(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 	mlx5_destroy_flow_table(rx-&gt;ft.sa);</div><div class='ctx'> 	if (rx-&gt;allow_tunnel_mode)</div><div class='ctx'> 		mlx5_eswitch_unblock_encap(mdev);</div><div class='del'>-	if (rx == ipsec-&gt;rx_esw) {</div><div class='del'>-		mlx5_esw_ipsec_rx_status_destroy(ipsec, rx);</div><div class='del'>-	} else {</div><div class='del'>-		mlx5_del_flow_rules(rx-&gt;status.rule);</div><div class='del'>-		mlx5_modify_header_dealloc(mdev, rx-&gt;status.modify_hdr);</div><div class='del'>-	}</div><div class='add'>+	mlx5_ipsec_rx_status_destroy(ipsec, rx);</div><div class='ctx'> 	mlx5_destroy_flow_table(rx-&gt;ft.status);</div><div class='ctx'> </div><div class='ctx'> 	mlx5_ipsec_fs_roce_rx_destroy(ipsec-&gt;roce, family, mdev);</div><div class='hunk'>@@ -419,7 +678,7 @@ static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	ft = ipsec_ft_create(attr.ns, attr.status_level, attr.prio, 1, 0);</div><div class='add'>+	ft = ipsec_ft_create(attr.ns, attr.status_level, attr.prio, 3, 0);</div><div class='ctx'> 	if (IS_ERR(ft)) {</div><div class='ctx'> 		err = PTR_ERR(ft);</div><div class='ctx'> 		goto err_fs_ft_status;</div><div class='hunk'>@@ -428,10 +687,7 @@ static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec,</div><div class='ctx'> </div><div class='ctx'> 	dest[1].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;</div><div class='ctx'> 	dest[1].counter_id = mlx5_fc_id(rx-&gt;fc-&gt;cnt);</div><div class='del'>-	if (rx == ipsec-&gt;rx_esw)</div><div class='del'>-		err = mlx5_esw_ipsec_rx_status_create(ipsec, rx, dest);</div><div class='del'>-	else</div><div class='del'>-		err = ipsec_status_rule(mdev, rx, dest);</div><div class='add'>+	err = mlx5_ipsec_rx_status_create(ipsec, rx, dest);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_add;</div><div class='ctx'> </div><div class='hunk'>@@ -956,13 +1212,22 @@ static void setup_fte_esp(struct mlx5_flow_spec *spec)</div><div class='ctx'> 	MLX5_SET(fte_match_param, spec-&gt;match_value, outer_headers.ip_protocol, IPPROTO_ESP);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void setup_fte_spi(struct mlx5_flow_spec *spec, u32 spi)</div><div class='add'>+static void setup_fte_spi(struct mlx5_flow_spec *spec, u32 spi, bool encap)</div><div class='ctx'> {</div><div class='ctx'> 	/* SPI number */</div><div class='ctx'> 	spec-&gt;match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;</div><div class='ctx'> </div><div class='del'>-	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria, misc_parameters.outer_esp_spi);</div><div class='del'>-	MLX5_SET(fte_match_param, spec-&gt;match_value, misc_parameters.outer_esp_spi, spi);</div><div class='add'>+	if (encap) {</div><div class='add'>+		MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria,</div><div class='add'>+				 misc_parameters.inner_esp_spi);</div><div class='add'>+		MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='add'>+			 misc_parameters.inner_esp_spi, spi);</div><div class='add'>+	} else {</div><div class='add'>+		MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria,</div><div class='add'>+				 misc_parameters.outer_esp_spi);</div><div class='add'>+		MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='add'>+			 misc_parameters.outer_esp_spi, spi);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void setup_fte_no_frags(struct mlx5_flow_spec *spec)</div><div class='hunk'>@@ -1052,29 +1317,48 @@ static int setup_modify_header(struct mlx5e_ipsec *ipsec, int type, u32 val, u8</div><div class='ctx'> 			       struct mlx5_flow_act *flow_act)</div><div class='ctx'> {</div><div class='ctx'> 	enum mlx5_flow_namespace_type ns_type = ipsec_fs_get_ns(ipsec, type, dir);</div><div class='del'>-	u8 action[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};</div><div class='add'>+	u8 action[3][MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};</div><div class='ctx'> 	struct mlx5_core_dev *mdev = ipsec-&gt;mdev;</div><div class='ctx'> 	struct mlx5_modify_hdr *modify_hdr;</div><div class='add'>+	u8 num_of_actions = 1;</div><div class='ctx'> </div><div class='del'>-	MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);</div><div class='add'>+	MLX5_SET(set_action_in, action[0], action_type, MLX5_ACTION_TYPE_SET);</div><div class='ctx'> 	switch (dir) {</div><div class='ctx'> 	case XFRM_DEV_OFFLOAD_IN:</div><div class='del'>-		MLX5_SET(set_action_in, action, field,</div><div class='add'>+		MLX5_SET(set_action_in, action[0], field,</div><div class='ctx'> 			 MLX5_ACTION_IN_FIELD_METADATA_REG_B);</div><div class='add'>+</div><div class='add'>+		num_of_actions++;</div><div class='add'>+		MLX5_SET(set_action_in, action[1], action_type, MLX5_ACTION_TYPE_SET);</div><div class='add'>+		MLX5_SET(set_action_in, action[1], field, MLX5_ACTION_IN_FIELD_METADATA_REG_C_2);</div><div class='add'>+		MLX5_SET(set_action_in, action[1], data, val);</div><div class='add'>+		MLX5_SET(set_action_in, action[1], offset, 0);</div><div class='add'>+		MLX5_SET(set_action_in, action[1], length, 32);</div><div class='add'>+</div><div class='add'>+		if (type == XFRM_DEV_OFFLOAD_CRYPTO) {</div><div class='add'>+			num_of_actions++;</div><div class='add'>+			MLX5_SET(set_action_in, action[2], action_type,</div><div class='add'>+				 MLX5_ACTION_TYPE_SET);</div><div class='add'>+			MLX5_SET(set_action_in, action[2], field,</div><div class='add'>+				 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4);</div><div class='add'>+			MLX5_SET(set_action_in, action[2], data, 0);</div><div class='add'>+			MLX5_SET(set_action_in, action[2], offset, 0);</div><div class='add'>+			MLX5_SET(set_action_in, action[2], length, 32);</div><div class='add'>+		}</div><div class='ctx'> 		break;</div><div class='ctx'> 	case XFRM_DEV_OFFLOAD_OUT:</div><div class='del'>-		MLX5_SET(set_action_in, action, field,</div><div class='add'>+		MLX5_SET(set_action_in, action[0], field,</div><div class='ctx'> 			 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4);</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	MLX5_SET(set_action_in, action, data, val);</div><div class='del'>-	MLX5_SET(set_action_in, action, offset, 0);</div><div class='del'>-	MLX5_SET(set_action_in, action, length, 32);</div><div class='add'>+	MLX5_SET(set_action_in, action[0], data, val);</div><div class='add'>+	MLX5_SET(set_action_in, action[0], offset, 0);</div><div class='add'>+	MLX5_SET(set_action_in, action[0], length, 32);</div><div class='ctx'> </div><div class='del'>-	modify_hdr = mlx5_modify_header_alloc(mdev, ns_type, 1, action);</div><div class='add'>+	modify_hdr = mlx5_modify_header_alloc(mdev, ns_type, num_of_actions, action);</div><div class='ctx'> 	if (IS_ERR(modify_hdr)) {</div><div class='ctx'> 		mlx5_core_err(mdev, "Failed to allocate modify_header %ld\n",</div><div class='ctx'> 			      PTR_ERR(modify_hdr));</div><div class='hunk'>@@ -1321,8 +1605,9 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> 	else</div><div class='ctx'> 		setup_fte_addr6(spec, attrs-&gt;saddr.a6, attrs-&gt;daddr.a6);</div><div class='ctx'> </div><div class='del'>-	setup_fte_spi(spec, attrs-&gt;spi);</div><div class='del'>-	setup_fte_esp(spec);</div><div class='add'>+	setup_fte_spi(spec, attrs-&gt;spi, attrs-&gt;encap);</div><div class='add'>+	if (!attrs-&gt;encap)</div><div class='add'>+		setup_fte_esp(spec);</div><div class='ctx'> 	setup_fte_no_frags(spec);</div><div class='ctx'> 	setup_fte_upper_proto_match(spec, &amp;attrs-&gt;upspec);</div><div class='ctx'> </div><div class='hunk'>@@ -1372,6 +1657,15 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> 		mlx5_core_err(mdev, "fail to add RX ipsec rule err=%d\n", err);</div><div class='ctx'> 		goto err_add_flow;</div><div class='ctx'> 	}</div><div class='add'>+	if (attrs-&gt;type == XFRM_DEV_OFFLOAD_PACKET)</div><div class='add'>+		err = rx_add_rule_drop_replay(sa_entry, rx);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_add_replay;</div><div class='add'>+</div><div class='add'>+	err = rx_add_rule_drop_auth_trailer(sa_entry, rx);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_drop_reason;</div><div class='add'>+</div><div class='ctx'> 	kvfree(spec);</div><div class='ctx'> </div><div class='ctx'> 	sa_entry-&gt;ipsec_rule.rule = rule;</div><div class='hunk'>@@ -1380,6 +1674,13 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> 	sa_entry-&gt;ipsec_rule.pkt_reformat = flow_act.pkt_reformat;</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+err_drop_reason:</div><div class='add'>+	if (sa_entry-&gt;ipsec_rule.replay.rule) {</div><div class='add'>+		mlx5_del_flow_rules(sa_entry-&gt;ipsec_rule.replay.rule);</div><div class='add'>+		mlx5_fc_destroy(mdev, sa_entry-&gt;ipsec_rule.replay.fc);</div><div class='add'>+	}</div><div class='add'>+err_add_replay:</div><div class='add'>+	mlx5_del_flow_rules(rule);</div><div class='ctx'> err_add_flow:</div><div class='ctx'> 	mlx5_fc_destroy(mdev, counter);</div><div class='ctx'> err_add_cnt:</div><div class='hunk'>@@ -1428,7 +1729,7 @@ static int tx_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> </div><div class='ctx'> 	switch (attrs-&gt;type) {</div><div class='ctx'> 	case XFRM_DEV_OFFLOAD_CRYPTO:</div><div class='del'>-		setup_fte_spi(spec, attrs-&gt;spi);</div><div class='add'>+		setup_fte_spi(spec, attrs-&gt;spi, false);</div><div class='ctx'> 		setup_fte_esp(spec);</div><div class='ctx'> 		setup_fte_reg_a(spec);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1809,8 +2110,11 @@ static int mlx5e_ipsec_block_tc_offload(struct mlx5_core_dev *mdev)</div><div class='ctx'> 	struct mlx5_eswitch *esw = mdev-&gt;priv.eswitch;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='del'>-	if (esw)</div><div class='del'>-		down_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+	if (esw) {</div><div class='add'>+		err = mlx5_esw_lock(esw);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (mdev-&gt;num_block_ipsec) {</div><div class='ctx'> 		err = -EBUSY;</div><div class='hunk'>@@ -1821,7 +2125,7 @@ static int mlx5e_ipsec_block_tc_offload(struct mlx5_core_dev *mdev)</div><div class='ctx'> </div><div class='ctx'> unlock:</div><div class='ctx'> 	if (esw)</div><div class='del'>-		up_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+		mlx5_esw_unlock(esw);</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='hunk'>@@ -1838,7 +2142,7 @@ static int mlx5e_ipsec_block_tc_offload(struct mlx5_core_dev *mdev)</div><div class='ctx'> </div><div class='ctx'> static void mlx5e_ipsec_unblock_tc_offload(struct mlx5_core_dev *mdev)</div><div class='ctx'> {</div><div class='del'>-	mdev-&gt;num_block_tc++;</div><div class='add'>+	mdev-&gt;num_block_tc--;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mlx5e_accel_ipsec_fs_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='hunk'>@@ -1887,6 +2191,17 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> </div><div class='ctx'> 	if (ipsec_rule-&gt;modify_hdr)</div><div class='ctx'> 		mlx5_modify_header_dealloc(mdev, ipsec_rule-&gt;modify_hdr);</div><div class='add'>+</div><div class='add'>+	mlx5_del_flow_rules(ipsec_rule-&gt;trailer.rule);</div><div class='add'>+	mlx5_fc_destroy(mdev, ipsec_rule-&gt;trailer.fc);</div><div class='add'>+</div><div class='add'>+	mlx5_del_flow_rules(ipsec_rule-&gt;auth.rule);</div><div class='add'>+	mlx5_fc_destroy(mdev, ipsec_rule-&gt;auth.fc);</div><div class='add'>+</div><div class='add'>+	if (ipsec_rule-&gt;replay.rule) {</div><div class='add'>+		mlx5_del_flow_rules(ipsec_rule-&gt;replay.rule);</div><div class='add'>+		mlx5_fc_destroy(mdev, ipsec_rule-&gt;replay.fc);</div><div class='add'>+	}</div><div class='ctx'> 	mlx5_esw_ipsec_rx_id_mapping_remove(sa_entry);</div><div class='ctx'> 	rx_ft_put(sa_entry-&gt;ipsec, sa_entry-&gt;attrs.family, sa_entry-&gt;attrs.type);</div><div class='ctx'> }</div><div class='hunk'>@@ -1957,7 +2272,7 @@ void mlx5e_accel_ipsec_fs_cleanup(struct mlx5e_ipsec *ipsec)</div><div class='ctx'> 	kfree(ipsec-&gt;rx_ipv6);</div><div class='ctx'> </div><div class='ctx'> 	if (ipsec-&gt;is_uplink_rep) {</div><div class='del'>-		xa_destroy(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map);</div><div class='add'>+		xa_destroy(&amp;ipsec-&gt;ipsec_obj_id_map);</div><div class='ctx'> </div><div class='ctx'> 		mutex_destroy(&amp;ipsec-&gt;tx_esw-&gt;ft.mutex);</div><div class='ctx'> 		WARN_ON(ipsec-&gt;tx_esw-&gt;ft.refcnt);</div><div class='hunk'>@@ -2020,7 +2335,7 @@ int mlx5e_accel_ipsec_fs_init(struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 		mutex_init(&amp;ipsec-&gt;tx_esw-&gt;ft.mutex);</div><div class='ctx'> 		mutex_init(&amp;ipsec-&gt;rx_esw-&gt;ft.mutex);</div><div class='ctx'> 		ipsec-&gt;tx_esw-&gt;ns = ns_esw;</div><div class='del'>-		xa_init_flags(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map, XA_FLAGS_ALLOC1);</div><div class='add'>+		xa_init_flags(&amp;ipsec-&gt;ipsec_obj_id_map, XA_FLAGS_ALLOC1);</div><div class='ctx'> 	} else if (mlx5_ipsec_device_caps(mdev) &amp; MLX5_IPSEC_CAP_ROCE) {</div><div class='ctx'> 		ipsec-&gt;roce = mlx5_ipsec_fs_roce_init(mdev, devcom);</div><div class='ctx'> 	} else {</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c<br/>index a91f772dc981..6e00afe4671b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c</a></div><div class='hunk'>@@ -6,6 +6,8 @@</div><div class='ctx'> #include "ipsec.h"</div><div class='ctx'> #include "lib/crypto.h"</div><div class='ctx'> #include "lib/ipsec_fs_roce.h"</div><div class='add'>+#include "fs_core.h"</div><div class='add'>+#include "eswitch.h"</div><div class='ctx'> </div><div class='ctx'> enum {</div><div class='ctx'> 	MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET,</div><div class='hunk'>@@ -38,7 +40,10 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)</div><div class='ctx'> 	    MLX5_CAP_ETH(mdev, insert_trailer) &amp;&amp; MLX5_CAP_ETH(mdev, swp))</div><div class='ctx'> 		caps |= MLX5_IPSEC_CAP_CRYPTO;</div><div class='ctx'> </div><div class='del'>-	if (MLX5_CAP_IPSEC(mdev, ipsec_full_offload)) {</div><div class='add'>+	if (MLX5_CAP_IPSEC(mdev, ipsec_full_offload) &amp;&amp;</div><div class='add'>+	    (mdev-&gt;priv.steering-&gt;mode == MLX5_FLOW_STEERING_MODE_DMFS ||</div><div class='add'>+	     (mdev-&gt;priv.steering-&gt;mode == MLX5_FLOW_STEERING_MODE_SMFS &amp;&amp;</div><div class='add'>+	     is_mdev_legacy_mode(mdev)))) {</div><div class='ctx'> 		if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,</div><div class='ctx'> 					      reformat_add_esp_trasport) &amp;&amp;</div><div class='ctx'> 		    MLX5_CAP_FLOWTABLE_NIC_RX(mdev,</div><div class='hunk'>@@ -95,7 +100,7 @@ static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn,</div><div class='ctx'> </div><div class='ctx'> 		if (attrs-&gt;dir == XFRM_DEV_OFFLOAD_IN) {</div><div class='ctx'> 			MLX5_SET(ipsec_aso, aso_ctx, window_sz,</div><div class='del'>-				 attrs-&gt;replay_esn.replay_window / 64);</div><div class='add'>+				 attrs-&gt;replay_esn.replay_window);</div><div class='ctx'> 			MLX5_SET(ipsec_aso, aso_ctx, mode,</div><div class='ctx'> 				 MLX5_IPSEC_ASO_REPLAY_PROTECTION);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -559,6 +564,7 @@ void mlx5e_ipsec_aso_cleanup(struct mlx5e_ipsec *ipsec)</div><div class='ctx'> 	dma_unmap_single(pdev, aso-&gt;dma_addr, sizeof(aso-&gt;ctx),</div><div class='ctx'> 			 DMA_BIDIRECTIONAL);</div><div class='ctx'> 	kfree(aso);</div><div class='add'>+	ipsec-&gt;aso = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mlx5e_ipsec_aso_copy(struct mlx5_wqe_aso_ctrl_seg *ctrl,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c<br/>index 41c396e76457..67f546683e85 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_common.c</a></div><div class='hunk'>@@ -74,6 +74,72 @@ int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)</div><div class='add'>+{</div><div class='add'>+	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);</div><div class='add'>+</div><div class='add'>+	MLX5_SET(tisc, tisc, transport_domain, mdev-&gt;mlx5e_res.hw_objs.td.tdn);</div><div class='add'>+</div><div class='add'>+	if (mlx5_lag_is_lacp_owner(mdev))</div><div class='add'>+		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);</div><div class='add'>+</div><div class='add'>+	return mlx5_core_create_tis(mdev, in, tisn);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)</div><div class='add'>+{</div><div class='add'>+	mlx5_core_destroy_tis(mdev, tisn);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])</div><div class='add'>+{</div><div class='add'>+	int tc, i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MLX5_MAX_PORTS; i++)</div><div class='add'>+		for (tc = 0; tc &lt; MLX5_MAX_NUM_TC; tc++)</div><div class='add'>+			mlx5e_destroy_tis(mdev, tisn[i][tc]);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool mlx5_lag_should_assign_affinity(struct mlx5_core_dev *mdev)</div><div class='add'>+{</div><div class='add'>+	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) &amp;&amp; mlx5e_get_num_lag_ports(mdev) &gt; 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])</div><div class='add'>+{</div><div class='add'>+	int tc, i;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MLX5_MAX_PORTS; i++) {</div><div class='add'>+		for (tc = 0; tc &lt; MLX5_MAX_NUM_TC; tc++) {</div><div class='add'>+			u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};</div><div class='add'>+			void *tisc;</div><div class='add'>+</div><div class='add'>+			tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);</div><div class='add'>+</div><div class='add'>+			MLX5_SET(tisc, tisc, prio, tc &lt;&lt; 1);</div><div class='add'>+</div><div class='add'>+			if (mlx5_lag_should_assign_affinity(mdev))</div><div class='add'>+				MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);</div><div class='add'>+</div><div class='add'>+			err = mlx5e_create_tis(mdev, in, &amp;tisn[i][tc]);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_close_tises;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_close_tises:</div><div class='add'>+	for (; i &gt;= 0; i--) {</div><div class='add'>+		for (tc--; tc &gt;= 0; tc--)</div><div class='add'>+			mlx5e_destroy_tis(mdev, tisn[i][tc]);</div><div class='add'>+		tc = MLX5_MAX_NUM_TC;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_hw_objs *res = &amp;mdev-&gt;mlx5e_res.hw_objs;</div><div class='hunk'>@@ -103,6 +169,11 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)</div><div class='ctx'> 		goto err_destroy_mkey;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	err = mlx5e_create_tises(mdev, res-&gt;tisn);</div><div class='add'>+	if (err) {</div><div class='add'>+		mlx5_core_err(mdev, "alloc tises failed, %d\n", err);</div><div class='add'>+		goto err_destroy_bfreg;</div><div class='add'>+	}</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;res-&gt;td.tirs_list);</div><div class='ctx'> 	mutex_init(&amp;res-&gt;td.list_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -115,6 +186,8 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+err_destroy_bfreg:</div><div class='add'>+	mlx5_free_bfreg(mdev, &amp;res-&gt;bfreg);</div><div class='ctx'> err_destroy_mkey:</div><div class='ctx'> 	mlx5_core_destroy_mkey(mdev, res-&gt;mkey);</div><div class='ctx'> err_dealloc_transport_domain:</div><div class='hunk'>@@ -130,6 +203,7 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)</div><div class='ctx'> </div><div class='ctx'> 	mlx5_crypto_dek_cleanup(mdev-&gt;mlx5e_res.dek_priv);</div><div class='ctx'> 	mdev-&gt;mlx5e_res.dek_priv = NULL;</div><div class='add'>+	mlx5e_destroy_tises(mdev, res-&gt;tisn);</div><div class='ctx'> 	mlx5_free_bfreg(mdev, &amp;res-&gt;bfreg);</div><div class='ctx'> 	mlx5_core_destroy_mkey(mdev, res-&gt;mkey);</div><div class='ctx'> 	mlx5_core_dealloc_transport_domain(mdev, res-&gt;td.tdn);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c<br/>index 792a0ea544cd..cc51ce16df14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c</a></div><div class='hunk'>@@ -49,7 +49,7 @@ void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,</div><div class='ctx'> 	count = snprintf(drvinfo-&gt;fw_version, sizeof(drvinfo-&gt;fw_version),</div><div class='ctx'> 			 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),</div><div class='ctx'> 			 fw_rev_min(mdev), fw_rev_sub(mdev), mdev-&gt;board_id);</div><div class='del'>-	if (count == sizeof(drvinfo-&gt;fw_version))</div><div class='add'>+	if (count &gt;= sizeof(drvinfo-&gt;fw_version))</div><div class='ctx'> 		snprintf(drvinfo-&gt;fw_version, sizeof(drvinfo-&gt;fw_version),</div><div class='ctx'> 			 "%d.%d.%04d", fw_rev_maj(mdev),</div><div class='ctx'> 			 fw_rev_min(mdev), fw_rev_sub(mdev));</div><div class='hunk'>@@ -1262,27 +1262,29 @@ static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> 	return mlx5e_ethtool_get_rxfh_indir_size(priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_get_rxfh_context(struct net_device *dev, u32 *indir,</div><div class='del'>-				  u8 *key, u8 *hfunc, u32 rss_context)</div><div class='add'>+int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='del'>-	struct mlx5e_priv *priv = netdev_priv(dev);</div><div class='add'>+	struct mlx5e_priv *priv = netdev_priv(netdev);</div><div class='add'>+	u32 rss_context = rxfh-&gt;rss_context;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;state_lock);</div><div class='del'>-	err = mlx5e_rx_res_rss_get_rxfh(priv-&gt;rx_res, rss_context, indir, key, hfunc);</div><div class='add'>+	err = mlx5e_rx_res_rss_get_rxfh(priv-&gt;rx_res, rss_context,</div><div class='add'>+					rxfh-&gt;indir, rxfh-&gt;key, &amp;rxfh-&gt;hfunc);</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;state_lock);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_set_rxfh_context(struct net_device *dev, const u32 *indir,</div><div class='del'>-				  const u8 *key, const u8 hfunc,</div><div class='del'>-				  u32 *rss_context, bool delete)</div><div class='add'>+int mlx5e_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+		   struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_priv *priv = netdev_priv(dev);</div><div class='add'>+	u32 *rss_context = &amp;rxfh-&gt;rss_context;</div><div class='add'>+	u8 hfunc = rxfh-&gt;hfunc;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;state_lock);</div><div class='del'>-	if (delete) {</div><div class='add'>+	if (*rss_context &amp;&amp; rxfh-&gt;rss_delete) {</div><div class='ctx'> 		err = mlx5e_rx_res_rss_destroy(priv-&gt;rx_res, *rss_context);</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1295,7 +1297,8 @@ static int mlx5e_set_rxfh_context(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 			goto unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_rx_res_rss_set_rxfh(priv-&gt;rx_res, *rss_context, indir, key,</div><div class='add'>+	err = mlx5e_rx_res_rss_set_rxfh(priv-&gt;rx_res, *rss_context,</div><div class='add'>+					rxfh-&gt;indir, rxfh-&gt;key,</div><div class='ctx'> 					hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &amp;hfunc);</div><div class='ctx'> </div><div class='ctx'> unlock:</div><div class='hunk'>@@ -1303,25 +1306,6 @@ unlock:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-		   u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	return mlx5e_get_rxfh_context(netdev, indir, key, hfunc, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-		   const u8 *key, const u8 hfunc)</div><div class='del'>-{</div><div class='del'>-	struct mlx5e_priv *priv = netdev_priv(dev);</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;priv-&gt;state_lock);</div><div class='del'>-	err = mlx5e_rx_res_rss_set_rxfh(priv-&gt;rx_res, 0, indir, key,</div><div class='del'>-					hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &amp;hfunc);</div><div class='del'>-	mutex_unlock(&amp;priv-&gt;state_lock);</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC		100</div><div class='ctx'> #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC		8000</div><div class='ctx'> #define MLX5E_PFC_PREVEN_MINOR_PRECENT		85</div><div class='hunk'>@@ -2398,6 +2382,7 @@ static void mlx5e_get_rmon_stats(struct net_device *netdev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct ethtool_ops mlx5e_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_MAX_FRAMES |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE |</div><div class='hunk'>@@ -2420,8 +2405,6 @@ const struct ethtool_ops mlx5e_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,</div><div class='ctx'> 	.get_rxfh          = mlx5e_get_rxfh,</div><div class='ctx'> 	.set_rxfh          = mlx5e_set_rxfh,</div><div class='del'>-	.get_rxfh_context  = mlx5e_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context  = mlx5e_set_rxfh_context,</div><div class='ctx'> 	.get_rxnfc         = mlx5e_get_rxnfc,</div><div class='ctx'> 	.set_rxnfc         = mlx5e_set_rxnfc,</div><div class='ctx'> 	.get_tunable       = mlx5e_get_tunable,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c<br/>index ea58c6917433..b5f1c4ca38ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_main.c</a></div><div class='hunk'>@@ -902,6 +902,7 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params,</div><div class='ctx'> 		pp_params.nid       = node;</div><div class='ctx'> 		pp_params.dev       = rq-&gt;pdev;</div><div class='ctx'> 		pp_params.napi      = rq-&gt;cq.napi;</div><div class='add'>+		pp_params.netdev    = rq-&gt;netdev;</div><div class='ctx'> 		pp_params.dma_dir   = rq-&gt;buff.map_dir;</div><div class='ctx'> 		pp_params.max_len   = PAGE_SIZE;</div><div class='ctx'> </div><div class='hunk'>@@ -1351,6 +1352,17 @@ void mlx5e_close_rq(struct mlx5e_rq *rq)</div><div class='ctx'> 	mlx5e_free_rq(rq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,</div><div class='add'>+			   struct mlx5e_priv *priv,</div><div class='add'>+			   const struct mlx5e_profile *profile,</div><div class='add'>+			   u8 lag_port, u8 tc)</div><div class='add'>+{</div><div class='add'>+	if (profile-&gt;get_tisn)</div><div class='add'>+		return profile-&gt;get_tisn(mdev, priv, lag_port, tc);</div><div class='add'>+</div><div class='add'>+	return mdev-&gt;mlx5e_res.hw_objs.tisn[lag_port][tc];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)</div><div class='ctx'> {</div><div class='ctx'> 	kvfree(sq-&gt;db.xdpi_fifo.xi);</div><div class='hunk'>@@ -1919,7 +1931,8 @@ int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='ctx'> 	csp.tis_lst_sz      = 1;</div><div class='del'>-	csp.tisn            = c-&gt;priv-&gt;tisn[c-&gt;lag_port][0]; /* tc = 0 */</div><div class='add'>+	csp.tisn            = mlx5e_profile_get_tisn(c-&gt;mdev, c-&gt;priv, c-&gt;priv-&gt;profile,</div><div class='add'>+						     c-&gt;lag_port, 0); /* tc = 0 */</div><div class='ctx'> 	csp.cqn             = sq-&gt;cq.mcq.cqn;</div><div class='ctx'> 	csp.wq_ctrl         = &amp;sq-&gt;wq_ctrl;</div><div class='ctx'> 	csp.min_inline_mode = sq-&gt;min_inline_mode;</div><div class='hunk'>@@ -1981,11 +1994,12 @@ void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)</div><div class='ctx'> 	mlx5e_free_xdpsq(sq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,</div><div class='add'>+static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,</div><div class='add'>+				 struct net_device *netdev,</div><div class='add'>+				 struct workqueue_struct *workqueue,</div><div class='ctx'> 				 struct mlx5e_cq_param *param,</div><div class='ctx'> 				 struct mlx5e_cq *cq)</div><div class='ctx'> {</div><div class='del'>-	struct mlx5_core_dev *mdev = priv-&gt;mdev;</div><div class='ctx'> 	struct mlx5_core_cq *mcq = &amp;cq-&gt;mcq;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	u32 i;</div><div class='hunk'>@@ -2012,13 +2026,13 @@ static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	cq-&gt;mdev = mdev;</div><div class='del'>-	cq-&gt;netdev = priv-&gt;netdev;</div><div class='del'>-	cq-&gt;priv = priv;</div><div class='add'>+	cq-&gt;netdev = netdev;</div><div class='add'>+	cq-&gt;workqueue = workqueue;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_alloc_cq(struct mlx5e_priv *priv,</div><div class='add'>+static int mlx5e_alloc_cq(struct mlx5_core_dev *mdev,</div><div class='ctx'> 			  struct mlx5e_cq_param *param,</div><div class='ctx'> 			  struct mlx5e_create_cq_param *ccp,</div><div class='ctx'> 			  struct mlx5e_cq *cq)</div><div class='hunk'>@@ -2029,7 +2043,7 @@ static int mlx5e_alloc_cq(struct mlx5e_priv *priv,</div><div class='ctx'> 	param-&gt;wq.db_numa_node  = ccp-&gt;node;</div><div class='ctx'> 	param-&gt;eq_ix            = ccp-&gt;ix;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_alloc_cq_common(priv, param, cq);</div><div class='add'>+	err = mlx5e_alloc_cq_common(mdev, ccp-&gt;netdev, ccp-&gt;wq, param, cq);</div><div class='ctx'> </div><div class='ctx'> 	cq-&gt;napi     = ccp-&gt;napi;</div><div class='ctx'> 	cq-&gt;ch_stats = ccp-&gt;ch_stats;</div><div class='hunk'>@@ -2095,14 +2109,13 @@ static void mlx5e_destroy_cq(struct mlx5e_cq *cq)</div><div class='ctx'> 	mlx5_core_destroy_cq(cq-&gt;mdev, &amp;cq-&gt;mcq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,</div><div class='add'>+int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,</div><div class='ctx'> 		  struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,</div><div class='ctx'> 		  struct mlx5e_cq *cq)</div><div class='ctx'> {</div><div class='del'>-	struct mlx5_core_dev *mdev = priv-&gt;mdev;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_alloc_cq(priv, param, ccp, cq);</div><div class='add'>+	err = mlx5e_alloc_cq(mdev, param, ccp, cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -2135,7 +2148,7 @@ static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,</div><div class='ctx'> 	int tc;</div><div class='ctx'> </div><div class='ctx'> 	for (tc = 0; tc &lt; c-&gt;num_tc; tc++) {</div><div class='del'>-		err = mlx5e_open_cq(c-&gt;priv, params-&gt;tx_cq_moderation, &amp;cparam-&gt;txq_sq.cqp,</div><div class='add'>+		err = mlx5e_open_cq(c-&gt;mdev, params-&gt;tx_cq_moderation, &amp;cparam-&gt;txq_sq.cqp,</div><div class='ctx'> 				    ccp, &amp;c-&gt;sq[tc].cq);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto err_close_tx_cqs;</div><div class='hunk'>@@ -2203,12 +2216,15 @@ static int mlx5e_open_sqs(struct mlx5e_channel *c,</div><div class='ctx'> 	for (tc = 0; tc &lt; mlx5e_get_dcb_num_tc(params); tc++) {</div><div class='ctx'> 		int txq_ix = c-&gt;ix + tc * params-&gt;num_channels;</div><div class='ctx'> 		u32 qos_queue_group_id;</div><div class='add'>+		u32 tisn;</div><div class='ctx'> </div><div class='add'>+		tisn = mlx5e_profile_get_tisn(c-&gt;mdev, c-&gt;priv, c-&gt;priv-&gt;profile,</div><div class='add'>+					      c-&gt;lag_port, tc);</div><div class='ctx'> 		err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &amp;qos_queue_group_id);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto err_close_sqs;</div><div class='ctx'> </div><div class='del'>-		err = mlx5e_open_txqsq(c, c-&gt;priv-&gt;tisn[c-&gt;lag_port][tc], txq_ix,</div><div class='add'>+		err = mlx5e_open_txqsq(c, tisn, txq_ix,</div><div class='ctx'> 				       params, &amp;cparam-&gt;txq_sq, &amp;c-&gt;sq[tc], tc,</div><div class='ctx'> 				       qos_queue_group_id,</div><div class='ctx'> 				       &amp;c-&gt;priv-&gt;channel_stats[c-&gt;ix]-&gt;sq[tc]);</div><div class='hunk'>@@ -2336,12 +2352,12 @@ static int mlx5e_open_queues(struct mlx5e_channel *c,</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_build_create_cq_param(&amp;ccp, c);</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, icocq_moder, &amp;cparam-&gt;async_icosq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, icocq_moder, &amp;cparam-&gt;async_icosq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;async_icosq.cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, icocq_moder, &amp;cparam-&gt;icosq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, icocq_moder, &amp;cparam-&gt;icosq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;icosq.cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_async_icosq_cq;</div><div class='hunk'>@@ -2350,17 +2366,17 @@ static int mlx5e_open_queues(struct mlx5e_channel *c,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_icosq_cq;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;xdpsq.cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_tx_cqs;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_open_cq(c-&gt;priv, params-&gt;rx_cq_moderation, &amp;cparam-&gt;rq.cqp, &amp;ccp,</div><div class='add'>+	err = mlx5e_open_cq(c-&gt;mdev, params-&gt;rx_cq_moderation, &amp;cparam-&gt;rq.cqp, &amp;ccp,</div><div class='ctx'> 			    &amp;c-&gt;rq.cq);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_xdp_tx_cqs;</div><div class='ctx'> </div><div class='del'>-	err = c-&gt;xdp ? mlx5e_open_cq(c-&gt;priv, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp,</div><div class='add'>+	err = c-&gt;xdp ? mlx5e_open_cq(c-&gt;mdev, params-&gt;tx_cq_moderation, &amp;cparam-&gt;xdp_sq.cqp,</div><div class='ctx'> 				     &amp;ccp, &amp;c-&gt;rq_xdpsq.cq) : 0;</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_close_rx_cq;</div><div class='hunk'>@@ -2731,6 +2747,7 @@ void mlx5e_close_channels(struct mlx5e_channels *chs)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	ASSERT_RTNL();</div><div class='ctx'> 	if (chs-&gt;ptp) {</div><div class='ctx'> 		mlx5e_ptp_close(chs-&gt;ptp);</div><div class='ctx'> 		chs-&gt;ptp = NULL;</div><div class='hunk'>@@ -3012,17 +3029,29 @@ void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)</div><div class='ctx'> 	if (mlx5e_is_vport_rep(priv))</div><div class='ctx'> 		mlx5e_rep_activate_channels(priv);</div><div class='ctx'> </div><div class='add'>+	set_bit(MLX5E_STATE_CHANNELS_ACTIVE, &amp;priv-&gt;state);</div><div class='add'>+</div><div class='ctx'> 	mlx5e_wait_channels_min_rx_wqes(&amp;priv-&gt;channels);</div><div class='ctx'> </div><div class='ctx'> 	if (priv-&gt;rx_res)</div><div class='ctx'> 		mlx5e_rx_res_channels_activate(priv-&gt;rx_res, &amp;priv-&gt;channels);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mlx5e_cancel_tx_timeout_work(struct mlx5e_priv *priv)</div><div class='add'>+{</div><div class='add'>+	WARN_ON_ONCE(test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &amp;priv-&gt;state));</div><div class='add'>+	if (current_work() != &amp;priv-&gt;tx_timeout_work)</div><div class='add'>+		cancel_work_sync(&amp;priv-&gt;tx_timeout_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	if (priv-&gt;rx_res)</div><div class='ctx'> 		mlx5e_rx_res_channels_deactivate(priv-&gt;rx_res);</div><div class='ctx'> </div><div class='add'>+	clear_bit(MLX5E_STATE_CHANNELS_ACTIVE, &amp;priv-&gt;state);</div><div class='add'>+	mlx5e_cancel_tx_timeout_work(priv);</div><div class='add'>+</div><div class='ctx'> 	if (mlx5e_is_vport_rep(priv))</div><div class='ctx'> 		mlx5e_rep_deactivate_channels(priv);</div><div class='ctx'> </div><div class='hunk'>@@ -3294,7 +3323,7 @@ static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,</div><div class='ctx'> 	param-&gt;wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));</div><div class='ctx'> 	param-&gt;wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));</div><div class='ctx'> </div><div class='del'>-	return mlx5e_alloc_cq_common(priv, param, cq);</div><div class='add'>+	return mlx5e_alloc_cq_common(priv-&gt;mdev, priv-&gt;netdev, priv-&gt;wq, param, cq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mlx5e_open_drop_rq(struct mlx5e_priv *priv,</div><div class='hunk'>@@ -3350,75 +3379,6 @@ void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)</div><div class='ctx'> 	mlx5e_free_cq(&amp;drop_rq-&gt;cq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)</div><div class='del'>-{</div><div class='del'>-	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);</div><div class='del'>-</div><div class='del'>-	MLX5_SET(tisc, tisc, transport_domain, mdev-&gt;mlx5e_res.hw_objs.td.tdn);</div><div class='del'>-</div><div class='del'>-	if (MLX5_GET(tisc, tisc, tls_en))</div><div class='del'>-		MLX5_SET(tisc, tisc, pd, mdev-&gt;mlx5e_res.hw_objs.pdn);</div><div class='del'>-</div><div class='del'>-	if (mlx5_lag_is_lacp_owner(mdev))</div><div class='del'>-		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);</div><div class='del'>-</div><div class='del'>-	return mlx5_core_create_tis(mdev, in, tisn);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)</div><div class='del'>-{</div><div class='del'>-	mlx5_core_destroy_tis(mdev, tisn);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void mlx5e_destroy_tises(struct mlx5e_priv *priv)</div><div class='del'>-{</div><div class='del'>-	int tc, i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mlx5e_get_num_lag_ports(priv-&gt;mdev); i++)</div><div class='del'>-		for (tc = 0; tc &lt; priv-&gt;profile-&gt;max_tc; tc++)</div><div class='del'>-			mlx5e_destroy_tis(priv-&gt;mdev, priv-&gt;tisn[i][tc]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)</div><div class='del'>-{</div><div class='del'>-	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) &amp;&amp; mlx5e_get_num_lag_ports(mdev) &gt; 1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int mlx5e_create_tises(struct mlx5e_priv *priv)</div><div class='del'>-{</div><div class='del'>-	int tc, i;</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; mlx5e_get_num_lag_ports(priv-&gt;mdev); i++) {</div><div class='del'>-		for (tc = 0; tc &lt; priv-&gt;profile-&gt;max_tc; tc++) {</div><div class='del'>-			u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};</div><div class='del'>-			void *tisc;</div><div class='del'>-</div><div class='del'>-			tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);</div><div class='del'>-</div><div class='del'>-			MLX5_SET(tisc, tisc, prio, tc &lt;&lt; 1);</div><div class='del'>-</div><div class='del'>-			if (mlx5e_lag_should_assign_affinity(priv-&gt;mdev))</div><div class='del'>-				MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);</div><div class='del'>-</div><div class='del'>-			err = mlx5e_create_tis(priv-&gt;mdev, in, &amp;priv-&gt;tisn[i][tc]);</div><div class='del'>-			if (err)</div><div class='del'>-				goto err_close_tises;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err_close_tises:</div><div class='del'>-	for (; i &gt;= 0; i--) {</div><div class='del'>-		for (tc--; tc &gt;= 0; tc--)</div><div class='del'>-			mlx5e_destroy_tis(priv-&gt;mdev, priv-&gt;tisn[i][tc]);</div><div class='del'>-		tc = priv-&gt;profile-&gt;max_tc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	if (priv-&gt;mqprio_rl) {</div><div class='hunk'>@@ -3427,7 +3387,6 @@ static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)</div><div class='ctx'> 		priv-&gt;mqprio_rl = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	mlx5e_accel_cleanup_tx(priv);</div><div class='del'>-	mlx5e_destroy_tises(priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)</div><div class='hunk'>@@ -3529,7 +3488,7 @@ static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,</div><div class='ctx'> </div><div class='ctx'> 	mqprio-&gt;hw = TC_MQPRIO_HW_OFFLOAD_TCS;</div><div class='ctx'> </div><div class='del'>-	if (tc &amp;&amp; tc != MLX5E_MAX_NUM_TC)</div><div class='add'>+	if (tc &amp;&amp; tc != MLX5_MAX_NUM_TC)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	new_params = priv-&gt;channels.params;</div><div class='hunk'>@@ -4801,8 +4760,17 @@ static void mlx5e_tx_timeout_work(struct work_struct *work)</div><div class='ctx'> 	struct net_device *netdev = priv-&gt;netdev;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	rtnl_lock();</div><div class='del'>-	mutex_lock(&amp;priv-&gt;state_lock);</div><div class='add'>+	/* Take rtnl_lock to ensure no change in netdev-&gt;real_num_tx_queues</div><div class='add'>+	 * through this flow. However, channel closing flows have to wait for</div><div class='add'>+	 * this work to finish while holding rtnl lock too. So either get the</div><div class='add'>+	 * lock or find that channels are being closed for other reason and</div><div class='add'>+	 * this work is not relevant anymore.</div><div class='add'>+	 */</div><div class='add'>+	while (!rtnl_trylock()) {</div><div class='add'>+		if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &amp;priv-&gt;state))</div><div class='add'>+			return;</div><div class='add'>+		msleep(20);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (!test_bit(MLX5E_STATE_OPENED, &amp;priv-&gt;state))</div><div class='ctx'> 		goto unlock;</div><div class='hunk'>@@ -4821,7 +4789,6 @@ static void mlx5e_tx_timeout_work(struct work_struct *work)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> unlock:</div><div class='del'>-	mutex_unlock(&amp;priv-&gt;state_lock);</div><div class='ctx'> 	rtnl_unlock();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5164,6 +5131,7 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev)</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;netdev_ops = &amp;mlx5e_netdev_ops;</div><div class='ctx'> 	netdev-&gt;xdp_metadata_ops = &amp;mlx5e_xdp_metadata_ops;</div><div class='add'>+	netdev-&gt;xsk_tx_metadata_ops = &amp;mlx5e_xsk_tx_metadata_ops;</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_dcbnl_build_netdev(netdev);</div><div class='ctx'> </div><div class='hunk'>@@ -5244,7 +5212,6 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev)</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;gso_partial_features             |= NETIF_F_GSO_UDP_L4;</div><div class='ctx'> 	netdev-&gt;hw_features                      |= NETIF_F_GSO_UDP_L4;</div><div class='del'>-	netdev-&gt;features                         |= NETIF_F_GSO_UDP_L4;</div><div class='ctx'> </div><div class='ctx'> 	mlx5_query_port_fcs(mdev, &amp;fcs_supported, &amp;fcs_enabled);</div><div class='ctx'> </div><div class='hunk'>@@ -5484,23 +5451,13 @@ static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_create_tises(priv);</div><div class='del'>-	if (err) {</div><div class='del'>-		mlx5_core_warn(priv-&gt;mdev, "create tises failed, %d\n", err);</div><div class='del'>-		return err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	err = mlx5e_accel_init_tx(priv);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto err_destroy_tises;</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_set_mqprio_rl(priv);</div><div class='ctx'> 	mlx5e_dcbnl_initialize(priv);</div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='del'>-err_destroy_tises:</div><div class='del'>-	mlx5e_destroy_tises(priv);</div><div class='del'>-	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mlx5e_nic_enable(struct mlx5e_priv *priv)</div><div class='hunk'>@@ -5595,7 +5552,7 @@ static const struct mlx5e_profile mlx5e_nic_profile = {</div><div class='ctx'> 	.update_stats	   = mlx5e_stats_update_ndo_stats,</div><div class='ctx'> 	.update_carrier	   = mlx5e_update_carrier,</div><div class='ctx'> 	.rx_handlers       = &amp;mlx5e_rx_handlers_nic,</div><div class='del'>-	.max_tc		   = MLX5E_MAX_NUM_TC,</div><div class='add'>+	.max_tc		   = MLX5_MAX_NUM_TC,</div><div class='ctx'> 	.stats_grps	   = mlx5e_nic_stats_grps,</div><div class='ctx'> 	.stats_grps_num	   = mlx5e_nic_stats_grps_num,</div><div class='ctx'> 	.features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |</div><div class='hunk'>@@ -6048,7 +6005,7 @@ static int mlx5e_resume(struct auxiliary_device *adev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)</div><div class='add'>+static int _mlx5e_suspend(struct auxiliary_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);</div><div class='ctx'> 	struct mlx5e_priv *priv = mlx5e_dev-&gt;priv;</div><div class='hunk'>@@ -6066,15 +6023,18 @@ static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlx5e_probe(struct auxiliary_device *adev,</div><div class='del'>-		       const struct auxiliary_device_id *id)</div><div class='add'>+static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)</div><div class='add'>+{</div><div class='add'>+	return _mlx5e_suspend(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int _mlx5e_probe(struct auxiliary_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);</div><div class='ctx'> 	const struct mlx5e_profile *profile = &amp;mlx5e_nic_profile;</div><div class='ctx'> 	struct mlx5_core_dev *mdev = edev-&gt;mdev;</div><div class='ctx'> 	struct mlx5e_dev *mlx5e_dev;</div><div class='ctx'> 	struct net_device *netdev;</div><div class='del'>-	pm_message_t state = {};</div><div class='ctx'> 	struct mlx5e_priv *priv;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -6129,7 +6089,7 @@ static int mlx5e_probe(struct auxiliary_device *adev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_resume:</div><div class='del'>-	mlx5e_suspend(adev, state);</div><div class='add'>+	_mlx5e_suspend(adev);</div><div class='ctx'> err_profile_cleanup:</div><div class='ctx'> 	profile-&gt;cleanup(priv);</div><div class='ctx'> err_destroy_netdev:</div><div class='hunk'>@@ -6141,16 +6101,21 @@ err_devlink_unregister:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mlx5e_probe(struct auxiliary_device *adev,</div><div class='add'>+		       const struct auxiliary_device_id *id)</div><div class='add'>+{</div><div class='add'>+	return _mlx5e_probe(adev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mlx5e_remove(struct auxiliary_device *adev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5e_dev *mlx5e_dev = auxiliary_get_drvdata(adev);</div><div class='ctx'> 	struct mlx5e_priv *priv = mlx5e_dev-&gt;priv;</div><div class='del'>-	pm_message_t state = {};</div><div class='ctx'> </div><div class='ctx'> 	mlx5_core_uplink_netdev_set(priv-&gt;mdev, NULL);</div><div class='ctx'> 	mlx5e_dcbnl_delete_app(priv);</div><div class='ctx'> 	unregister_netdev(priv-&gt;netdev);</div><div class='del'>-	mlx5e_suspend(adev, state);</div><div class='add'>+	_mlx5e_suspend(adev);</div><div class='ctx'> 	priv-&gt;profile-&gt;cleanup(priv);</div><div class='ctx'> 	mlx5e_destroy_netdev(priv);</div><div class='ctx'> 	mlx5e_devlink_port_unregister(mlx5e_dev);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c<br/>index 3ab682bbcf86..05527418fa64 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_rep.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_rep.c</a></div><div class='hunk'>@@ -78,7 +78,7 @@ static void mlx5e_rep_get_drvinfo(struct net_device *dev,</div><div class='ctx'> 	count = snprintf(drvinfo-&gt;fw_version, sizeof(drvinfo-&gt;fw_version),</div><div class='ctx'> 			 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev),</div><div class='ctx'> 			 fw_rev_min(mdev), fw_rev_sub(mdev), mdev-&gt;board_id);</div><div class='del'>-	if (count == sizeof(drvinfo-&gt;fw_version))</div><div class='add'>+	if (count &gt;= sizeof(drvinfo-&gt;fw_version))</div><div class='ctx'> 		snprintf(drvinfo-&gt;fw_version, sizeof(drvinfo-&gt;fw_version),</div><div class='ctx'> 			 "%d.%d.%04d", fw_rev_maj(mdev),</div><div class='ctx'> 			 fw_rev_min(mdev), fw_rev_sub(mdev));</div><div class='hunk'>@@ -112,8 +112,18 @@ static const struct counter_desc vport_rep_stats_desc[] = {</div><div class='ctx'> 			     tx_vport_rdma_multicast_bytes) },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct counter_desc vport_rep_loopback_stats_desc[] = {</div><div class='add'>+	{ MLX5E_DECLARE_STAT(struct mlx5e_rep_stats,</div><div class='add'>+			     vport_loopback_packets) },</div><div class='add'>+	{ MLX5E_DECLARE_STAT(struct mlx5e_rep_stats,</div><div class='add'>+			     vport_loopback_bytes) },</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define NUM_VPORT_REP_SW_COUNTERS ARRAY_SIZE(sw_rep_stats_desc)</div><div class='ctx'> #define NUM_VPORT_REP_HW_COUNTERS ARRAY_SIZE(vport_rep_stats_desc)</div><div class='add'>+#define NUM_VPORT_REP_LOOPBACK_COUNTERS(dev) \</div><div class='add'>+	(MLX5_CAP_GEN(dev, vport_counter_local_loopback) ? \</div><div class='add'>+	 ARRAY_SIZE(vport_rep_loopback_stats_desc) : 0)</div><div class='ctx'> </div><div class='ctx'> static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw_rep)</div><div class='ctx'> {</div><div class='hunk'>@@ -157,7 +167,8 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw_rep)</div><div class='ctx'> </div><div class='ctx'> static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport_rep)</div><div class='ctx'> {</div><div class='del'>-	return NUM_VPORT_REP_HW_COUNTERS;</div><div class='add'>+	return NUM_VPORT_REP_HW_COUNTERS +</div><div class='add'>+	       NUM_VPORT_REP_LOOPBACK_COUNTERS(priv-&gt;mdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport_rep)</div><div class='hunk'>@@ -166,6 +177,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport_rep)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NUM_VPORT_REP_HW_COUNTERS; i++)</div><div class='ctx'> 		strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_rep_stats_desc[i].format);</div><div class='add'>+	for (i = 0; i &lt; NUM_VPORT_REP_LOOPBACK_COUNTERS(priv-&gt;mdev); i++)</div><div class='add'>+		strcpy(data + (idx++) * ETH_GSTRING_LEN,</div><div class='add'>+		       vport_rep_loopback_stats_desc[i].format);</div><div class='ctx'> 	return idx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -176,6 +190,9 @@ static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport_rep)</div><div class='ctx'> 	for (i = 0; i &lt; NUM_VPORT_REP_HW_COUNTERS; i++)</div><div class='ctx'> 		data[idx++] = MLX5E_READ_CTR64_CPU(&amp;priv-&gt;stats.rep_stats,</div><div class='ctx'> 						   vport_rep_stats_desc, i);</div><div class='add'>+	for (i = 0; i &lt; NUM_VPORT_REP_LOOPBACK_COUNTERS(priv-&gt;mdev); i++)</div><div class='add'>+		data[idx++] = MLX5E_READ_CTR64_CPU(&amp;priv-&gt;stats.rep_stats,</div><div class='add'>+						   vport_rep_loopback_stats_desc, i);</div><div class='ctx'> 	return idx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -247,6 +264,13 @@ static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport_rep)</div><div class='ctx'> 	rep_stats-&gt;tx_vport_rdma_multicast_bytes =</div><div class='ctx'> 		MLX5_GET_CTR(out, received_ib_multicast.octets);</div><div class='ctx'> </div><div class='add'>+	if (MLX5_CAP_GEN(priv-&gt;mdev, vport_counter_local_loopback)) {</div><div class='add'>+		rep_stats-&gt;vport_loopback_packets =</div><div class='add'>+			MLX5_GET_CTR(out, local_loopback.packets);</div><div class='add'>+		rep_stats-&gt;vport_loopback_bytes =</div><div class='add'>+			MLX5_GET_CTR(out, local_loopback.octets);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> out:</div><div class='ctx'> 	kvfree(out);</div><div class='ctx'> }</div><div class='hunk'>@@ -1156,12 +1180,6 @@ static int mlx5e_init_rep_tx(struct mlx5e_priv *priv)</div><div class='ctx'> 	struct mlx5e_rep_priv *rpriv = priv-&gt;ppriv;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = mlx5e_create_tises(priv);</div><div class='del'>-	if (err) {</div><div class='del'>-		mlx5_core_warn(priv-&gt;mdev, "create tises failed, %d\n", err);</div><div class='del'>-		return err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	err = mlx5e_rep_neigh_init(rpriv);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_neigh_init;</div><div class='hunk'>@@ -1184,7 +1202,6 @@ err_ht_init:</div><div class='ctx'> err_init_tx:</div><div class='ctx'> 	mlx5e_rep_neigh_cleanup(rpriv);</div><div class='ctx'> err_neigh_init:</div><div class='del'>-	mlx5e_destroy_tises(priv);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1198,7 +1215,6 @@ static void mlx5e_cleanup_rep_tx(struct mlx5e_priv *priv)</div><div class='ctx'> 		mlx5e_cleanup_uplink_rep_tx(rpriv);</div><div class='ctx'> </div><div class='ctx'> 	mlx5e_rep_neigh_cleanup(rpriv);</div><div class='del'>-	mlx5e_destroy_tises(priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void mlx5e_rep_enable(struct mlx5e_priv *priv)</div><div class='hunk'>@@ -1428,7 +1444,7 @@ static const struct mlx5e_profile mlx5e_uplink_rep_profile = {</div><div class='ctx'> 	.update_stats           = mlx5e_stats_update_ndo_stats,</div><div class='ctx'> 	.update_carrier	        = mlx5e_update_carrier,</div><div class='ctx'> 	.rx_handlers            = &amp;mlx5e_rx_handlers_rep,</div><div class='del'>-	.max_tc			= MLX5E_MAX_NUM_TC,</div><div class='add'>+	.max_tc			= MLX5_MAX_NUM_TC,</div><div class='ctx'> 	.stats_grps		= mlx5e_ul_rep_stats_grps,</div><div class='ctx'> 	.stats_grps_num		= mlx5e_ul_rep_stats_grps_num,</div><div class='ctx'> };</div><div class='hunk'>@@ -1497,7 +1513,7 @@ mlx5e_vport_vf_rep_load(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep)</div><div class='ctx'> </div><div class='ctx'> 	dl_port = mlx5_esw_offloads_devlink_port(dev-&gt;priv.eswitch,</div><div class='ctx'> 						 rpriv-&gt;rep-&gt;vport);</div><div class='del'>-	if (dl_port) {</div><div class='add'>+	if (!IS_ERR(dl_port)) {</div><div class='ctx'> 		SET_NETDEV_DEVLINK_PORT(netdev, dl_port);</div><div class='ctx'> 		mlx5e_rep_vnic_reporter_create(priv, dl_port);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c<br/>index 8d9743a5e42c..d601b5faaed5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_rx.c</a></div><div class='hunk'>@@ -298,8 +298,8 @@ static void mlx5e_page_release_fragmented(struct mlx5e_rq *rq,</div><div class='ctx'> 	u16 drain_count = MLX5E_PAGECNT_BIAS_MAX - frag_page-&gt;frags;</div><div class='ctx'> 	struct page *page = frag_page-&gt;page;</div><div class='ctx'> </div><div class='del'>-	if (page_pool_defrag_page(page, drain_count) == 0)</div><div class='del'>-		page_pool_put_defragged_page(rq-&gt;page_pool, page, -1, true);</div><div class='add'>+	if (page_pool_unref_page(page, drain_count) == 0)</div><div class='add'>+		page_pool_put_unrefed_page(rq-&gt;page_pool, page, -1, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,</div><div class='hunk'>@@ -1039,7 +1039,7 @@ int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)</div><div class='ctx'> 						     (struct mlx5_err_cqe *)cqe);</div><div class='ctx'> 				mlx5_wq_cyc_wqe_dump(&amp;sq-&gt;wq, ci, wi-&gt;num_wqebbs);</div><div class='ctx'> 				if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &amp;sq-&gt;state))</div><div class='del'>-					queue_work(cq-&gt;priv-&gt;wq, &amp;sq-&gt;recover_work);</div><div class='add'>+					queue_work(cq-&gt;workqueue, &amp;sq-&gt;recover_work);</div><div class='ctx'> 				break;</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h<br/>index 477c547dcc04..12b3607afecd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_stats.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_stats.h</a></div><div class='hunk'>@@ -476,6 +476,8 @@ struct mlx5e_rep_stats {</div><div class='ctx'> 	u64 tx_vport_rdma_multicast_packets;</div><div class='ctx'> 	u64 rx_vport_rdma_multicast_bytes;</div><div class='ctx'> 	u64 tx_vport_rdma_multicast_bytes;</div><div class='add'>+	u64 vport_loopback_packets;</div><div class='add'>+	u64 vport_loopback_bytes;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_stats {</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c<br/>index 7ca9e5b86778..30932c9c9a8f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.c</a></div><div class='hunk'>@@ -444,6 +444,9 @@ mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,</div><div class='ctx'> 	struct mlx5e_flow_meter_handle *meter;</div><div class='ctx'> 	enum mlx5e_post_meter_type type;</div><div class='ctx'> </div><div class='add'>+	if (IS_ERR(post_act))</div><div class='add'>+		return PTR_ERR(post_act);</div><div class='add'>+</div><div class='ctx'> 	meter = mlx5e_tc_meter_replace(priv-&gt;mdev, &amp;attr-&gt;meter_attr.params);</div><div class='ctx'> 	if (IS_ERR(meter)) {</div><div class='ctx'> 		mlx5_core_err(priv-&gt;mdev, "Failed to get flow meter\n");</div><div class='hunk'>@@ -3206,10 +3209,10 @@ static int offload_pedit_fields(struct mlx5e_priv *priv,</div><div class='ctx'> 	headers_c = mlx5e_get_match_headers_criteria(*action_flags, &amp;parse_attr-&gt;spec);</div><div class='ctx'> 	headers_v = mlx5e_get_match_headers_value(*action_flags, &amp;parse_attr-&gt;spec);</div><div class='ctx'> </div><div class='del'>-	set_masks = &amp;hdrs[0].masks;</div><div class='del'>-	add_masks = &amp;hdrs[1].masks;</div><div class='del'>-	set_vals = &amp;hdrs[0].vals;</div><div class='del'>-	add_vals = &amp;hdrs[1].vals;</div><div class='add'>+	set_masks = &amp;hdrs[TCA_PEDIT_KEY_EX_CMD_SET].masks;</div><div class='add'>+	add_masks = &amp;hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].masks;</div><div class='add'>+	set_vals = &amp;hdrs[TCA_PEDIT_KEY_EX_CMD_SET].vals;</div><div class='add'>+	add_vals = &amp;hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].vals;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(fields); i++) {</div><div class='ctx'> 		bool skip;</div><div class='hunk'>@@ -3739,6 +3742,20 @@ out_free:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='add'>+set_branch_dest_ft(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr)</div><div class='add'>+{</div><div class='add'>+	struct mlx5e_post_act *post_act = get_post_action(priv);</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(post_act))</div><div class='add'>+		return PTR_ERR(post_act);</div><div class='add'>+</div><div class='add'>+	attr-&gt;action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;</div><div class='add'>+	attr-&gt;dest_ft = mlx5e_tc_post_act_get_ft(post_act);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='ctx'> alloc_branch_attr(struct mlx5e_tc_flow *flow,</div><div class='ctx'> 		  struct mlx5e_tc_act_branch_ctrl *cond,</div><div class='ctx'> 		  struct mlx5_flow_attr **cond_attr,</div><div class='hunk'>@@ -3761,8 +3778,9 @@ alloc_branch_attr(struct mlx5e_tc_flow *flow,</div><div class='ctx'> 		break;</div><div class='ctx'> 	case FLOW_ACTION_ACCEPT:</div><div class='ctx'> 	case FLOW_ACTION_PIPE:</div><div class='del'>-		attr-&gt;action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;</div><div class='del'>-		attr-&gt;dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow-&gt;priv));</div><div class='add'>+		err = set_branch_dest_ft(flow-&gt;priv, attr);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_err;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case FLOW_ACTION_JUMP:</div><div class='ctx'> 		if (*jump_count) {</div><div class='hunk'>@@ -3771,8 +3789,9 @@ alloc_branch_attr(struct mlx5e_tc_flow *flow,</div><div class='ctx'> 			goto out_err;</div><div class='ctx'> 		}</div><div class='ctx'> 		*jump_count = cond-&gt;extval;</div><div class='del'>-		attr-&gt;action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;</div><div class='del'>-		attr-&gt;dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow-&gt;priv));</div><div class='add'>+		err = set_branch_dest_ft(flow-&gt;priv, attr);</div><div class='add'>+		if (err)</div><div class='add'>+			goto out_err;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		err = -EOPNOTSUPP;</div><div class='hunk'>@@ -5011,22 +5030,6 @@ int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,</div><div class='ctx'> 	return apply_police_params(priv, 0, extack);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,</div><div class='del'>-			     struct tc_cls_matchall_offload *ma)</div><div class='del'>-{</div><div class='del'>-	struct mlx5e_rep_priv *rpriv = priv-&gt;ppriv;</div><div class='del'>-	struct rtnl_link_stats64 cur_stats;</div><div class='del'>-	u64 dbytes;</div><div class='del'>-	u64 dpkts;</div><div class='del'>-</div><div class='del'>-	mlx5e_stats_copy_rep_stats(&amp;cur_stats, &amp;priv-&gt;stats.rep_stats);</div><div class='del'>-	dpkts = cur_stats.rx_packets - rpriv-&gt;prev_vf_vport_stats.rx_packets;</div><div class='del'>-	dbytes = cur_stats.rx_bytes - rpriv-&gt;prev_vf_vport_stats.rx_bytes;</div><div class='del'>-	rpriv-&gt;prev_vf_vport_stats = cur_stats;</div><div class='del'>-	flow_stats_update(&amp;ma-&gt;stats, dbytes, dpkts, 0, jiffies,</div><div class='del'>-			  FLOW_ACTION_HW_STATS_DELAYED);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,</div><div class='ctx'> 					      struct mlx5e_priv *peer_priv)</div><div class='ctx'> {</div><div class='hunk'>@@ -5719,8 +5722,10 @@ int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_a</div><div class='ctx'> </div><div class='ctx'> 	esw = priv-&gt;mdev-&gt;priv.eswitch;</div><div class='ctx'> 	attr-&gt;act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);</div><div class='del'>-	if (IS_ERR(attr-&gt;act_id_restore_rule))</div><div class='add'>+	if (IS_ERR(attr-&gt;act_id_restore_rule)) {</div><div class='add'>+		err = PTR_ERR(attr-&gt;act_id_restore_rule);</div><div class='ctx'> 		goto err_rule;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h<br/>index adb39e30f90f..c24bda56b2b5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tc.h</a></div><div class='hunk'>@@ -203,8 +203,6 @@ int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,</div><div class='ctx'> 				struct tc_cls_matchall_offload *f);</div><div class='ctx'> int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,</div><div class='ctx'> 			     struct tc_cls_matchall_offload *f);</div><div class='del'>-void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,</div><div class='del'>-			     struct tc_cls_matchall_offload *ma);</div><div class='ctx'> </div><div class='ctx'> struct mlx5e_encap_entry;</div><div class='ctx'> void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c<br/>index f0b506e562df..5c166d9d2dca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/en_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/en_tx.c</a></div><div class='hunk'>@@ -861,7 +861,7 @@ bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)</div><div class='ctx'> 				mlx5e_dump_error_cqe(&amp;sq-&gt;cq, sq-&gt;sqn,</div><div class='ctx'> 						     (struct mlx5_err_cqe *)cqe);</div><div class='ctx'> 				mlx5_wq_cyc_wqe_dump(&amp;sq-&gt;wq, ci, wi-&gt;num_wqebbs);</div><div class='del'>-				queue_work(cq-&gt;priv-&gt;wq, &amp;sq-&gt;recover_work);</div><div class='add'>+				queue_work(cq-&gt;workqueue, &amp;sq-&gt;recover_work);</div><div class='ctx'> 			}</div><div class='ctx'> 			stats-&gt;cqe_err++;</div><div class='ctx'> 		}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c<br/>index 095f31f380fa..190f10aba170 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c</a></div><div class='hunk'>@@ -21,158 +21,6 @@ enum {</div><div class='ctx'> 	MLX5_ESW_IPSEC_TX_ESP_FT_CNT_LEVEL,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void esw_ipsec_rx_status_drop_destroy(struct mlx5e_ipsec *ipsec,</div><div class='del'>-					     struct mlx5e_ipsec_rx *rx)</div><div class='del'>-{</div><div class='del'>-	mlx5_del_flow_rules(rx-&gt;status_drop.rule);</div><div class='del'>-	mlx5_destroy_flow_group(rx-&gt;status_drop.group);</div><div class='del'>-	mlx5_fc_destroy(ipsec-&gt;mdev, rx-&gt;status_drop_cnt);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void esw_ipsec_rx_status_pass_destroy(struct mlx5e_ipsec *ipsec,</div><div class='del'>-					     struct mlx5e_ipsec_rx *rx)</div><div class='del'>-{</div><div class='del'>-	mlx5_del_flow_rules(rx-&gt;status.rule);</div><div class='del'>-	mlx5_chains_put_table(esw_chains(ipsec-&gt;mdev-&gt;priv.eswitch), 0, 1, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int esw_ipsec_rx_status_drop_create(struct mlx5e_ipsec *ipsec,</div><div class='del'>-					   struct mlx5e_ipsec_rx *rx)</div><div class='del'>-{</div><div class='del'>-	int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);</div><div class='del'>-	struct mlx5_flow_table *ft = rx-&gt;ft.status;</div><div class='del'>-	struct mlx5_core_dev *mdev = ipsec-&gt;mdev;</div><div class='del'>-	struct mlx5_flow_destination dest = {};</div><div class='del'>-	struct mlx5_flow_act flow_act = {};</div><div class='del'>-	struct mlx5_flow_handle *rule;</div><div class='del'>-	struct mlx5_fc *flow_counter;</div><div class='del'>-	struct mlx5_flow_spec *spec;</div><div class='del'>-	struct mlx5_flow_group *g;</div><div class='del'>-	u32 *flow_group_in;</div><div class='del'>-	int err = 0;</div><div class='del'>-</div><div class='del'>-	flow_group_in = kvzalloc(inlen, GFP_KERNEL);</div><div class='del'>-	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='del'>-	if (!flow_group_in || !spec) {</div><div class='del'>-		err = -ENOMEM;</div><div class='del'>-		goto err_out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ft-&gt;max_fte - 1);</div><div class='del'>-	MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ft-&gt;max_fte - 1);</div><div class='del'>-	g = mlx5_create_flow_group(ft, flow_group_in);</div><div class='del'>-	if (IS_ERR(g)) {</div><div class='del'>-		err = PTR_ERR(g);</div><div class='del'>-		mlx5_core_err(mdev,</div><div class='del'>-			      "Failed to add ipsec rx status drop flow group, err=%d\n", err);</div><div class='del'>-		goto err_out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	flow_counter = mlx5_fc_create(mdev, false);</div><div class='del'>-	if (IS_ERR(flow_counter)) {</div><div class='del'>-		err = PTR_ERR(flow_counter);</div><div class='del'>-		mlx5_core_err(mdev,</div><div class='del'>-			      "Failed to add ipsec rx status drop rule counter, err=%d\n", err);</div><div class='del'>-		goto err_cnt;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP | MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='del'>-	dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;</div><div class='del'>-	dest.counter_id = mlx5_fc_id(flow_counter);</div><div class='del'>-	spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='del'>-	rule = mlx5_add_flow_rules(ft, spec, &amp;flow_act, &amp;dest, 1);</div><div class='del'>-	if (IS_ERR(rule)) {</div><div class='del'>-		err = PTR_ERR(rule);</div><div class='del'>-		mlx5_core_err(mdev,</div><div class='del'>-			      "Failed to add ipsec rx status drop rule, err=%d\n", err);</div><div class='del'>-		goto err_rule;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rx-&gt;status_drop.group = g;</div><div class='del'>-	rx-&gt;status_drop.rule = rule;</div><div class='del'>-	rx-&gt;status_drop_cnt = flow_counter;</div><div class='del'>-</div><div class='del'>-	kvfree(flow_group_in);</div><div class='del'>-	kvfree(spec);</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err_rule:</div><div class='del'>-	mlx5_fc_destroy(mdev, flow_counter);</div><div class='del'>-err_cnt:</div><div class='del'>-	mlx5_destroy_flow_group(g);</div><div class='del'>-err_out:</div><div class='del'>-	kvfree(flow_group_in);</div><div class='del'>-	kvfree(spec);</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int esw_ipsec_rx_status_pass_create(struct mlx5e_ipsec *ipsec,</div><div class='del'>-					   struct mlx5e_ipsec_rx *rx,</div><div class='del'>-					   struct mlx5_flow_destination *dest)</div><div class='del'>-{</div><div class='del'>-	struct mlx5_flow_act flow_act = {};</div><div class='del'>-	struct mlx5_flow_handle *rule;</div><div class='del'>-	struct mlx5_flow_spec *spec;</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);</div><div class='del'>-	if (!spec)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	MLX5_SET_TO_ONES(fte_match_param, spec-&gt;match_criteria,</div><div class='del'>-			 misc_parameters_2.ipsec_syndrome);</div><div class='del'>-	MLX5_SET(fte_match_param, spec-&gt;match_value,</div><div class='del'>-		 misc_parameters_2.ipsec_syndrome, 0);</div><div class='del'>-	spec-&gt;flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;</div><div class='del'>-	spec-&gt;match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;</div><div class='del'>-	flow_act.flags = FLOW_ACT_NO_APPEND;</div><div class='del'>-	flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |</div><div class='del'>-			  MLX5_FLOW_CONTEXT_ACTION_COUNT;</div><div class='del'>-	rule = mlx5_add_flow_rules(rx-&gt;ft.status, spec, &amp;flow_act, dest, 2);</div><div class='del'>-	if (IS_ERR(rule)) {</div><div class='del'>-		err = PTR_ERR(rule);</div><div class='del'>-		mlx5_core_warn(ipsec-&gt;mdev,</div><div class='del'>-			       "Failed to add ipsec rx status pass rule, err=%d\n", err);</div><div class='del'>-		goto err_rule;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rx-&gt;status.rule = rule;</div><div class='del'>-	kvfree(spec);</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err_rule:</div><div class='del'>-	kvfree(spec);</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void mlx5_esw_ipsec_rx_status_destroy(struct mlx5e_ipsec *ipsec,</div><div class='del'>-				      struct mlx5e_ipsec_rx *rx)</div><div class='del'>-{</div><div class='del'>-	esw_ipsec_rx_status_pass_destroy(ipsec, rx);</div><div class='del'>-	esw_ipsec_rx_status_drop_destroy(ipsec, rx);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int mlx5_esw_ipsec_rx_status_create(struct mlx5e_ipsec *ipsec,</div><div class='del'>-				    struct mlx5e_ipsec_rx *rx,</div><div class='del'>-				    struct mlx5_flow_destination *dest)</div><div class='del'>-{</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	err = esw_ipsec_rx_status_drop_create(ipsec, rx);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='del'>-</div><div class='del'>-	err = esw_ipsec_rx_status_pass_create(ipsec, rx, dest);</div><div class='del'>-	if (err)</div><div class='del'>-		goto err_pass_create;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err_pass_create:</div><div class='del'>-	esw_ipsec_rx_status_drop_destroy(ipsec, rx);</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void mlx5_esw_ipsec_rx_create_attr_set(struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 				       struct mlx5e_ipsec_rx_create_attr *attr)</div><div class='ctx'> {</div><div class='hunk'>@@ -202,7 +50,7 @@ int mlx5_esw_ipsec_rx_setup_modify_header(struct mlx5e_ipsec_sa_entry *sa_entry,</div><div class='ctx'> 	u32 mapped_id;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = xa_alloc_bh(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map, &amp;mapped_id,</div><div class='add'>+	err = xa_alloc_bh(&amp;ipsec-&gt;ipsec_obj_id_map, &amp;mapped_id,</div><div class='ctx'> 			  xa_mk_value(sa_entry-&gt;ipsec_obj_id),</div><div class='ctx'> 			  XA_LIMIT(1, ESW_IPSEC_RX_MAPPED_ID_MASK), 0);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -233,7 +81,7 @@ int mlx5_esw_ipsec_rx_setup_modify_header(struct mlx5e_ipsec_sa_entry *sa_entry,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_header_alloc:</div><div class='del'>-	xa_erase_bh(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map, mapped_id);</div><div class='add'>+	xa_erase_bh(&amp;ipsec-&gt;ipsec_obj_id_map, mapped_id);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -242,7 +90,7 @@ void mlx5_esw_ipsec_rx_id_mapping_remove(struct mlx5e_ipsec_sa_entry *sa_entry)</div><div class='ctx'> 	struct mlx5e_ipsec *ipsec = sa_entry-&gt;ipsec;</div><div class='ctx'> </div><div class='ctx'> 	if (sa_entry-&gt;rx_mapped_id)</div><div class='del'>-		xa_erase_bh(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map,</div><div class='add'>+		xa_erase_bh(&amp;ipsec-&gt;ipsec_obj_id_map,</div><div class='ctx'> 			    sa_entry-&gt;rx_mapped_id);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -252,7 +100,7 @@ int mlx5_esw_ipsec_rx_ipsec_obj_id_search(struct mlx5e_priv *priv, u32 id,</div><div class='ctx'> 	struct mlx5e_ipsec *ipsec = priv-&gt;ipsec;</div><div class='ctx'> 	void *val;</div><div class='ctx'> </div><div class='del'>-	val = xa_load(&amp;ipsec-&gt;rx_esw-&gt;ipsec_obj_id_map, id);</div><div class='add'>+	val = xa_load(&amp;ipsec-&gt;ipsec_obj_id_map, id);</div><div class='ctx'> 	if (!val)</div><div class='ctx'> 		return -ENOENT;</div><div class='ctx'> </div><div class='hunk'>@@ -304,7 +152,7 @@ void mlx5_esw_ipsec_restore_dest_uplink(struct mlx5_core_dev *mdev)</div><div class='ctx'> </div><div class='ctx'> 	xa_for_each(&amp;esw-&gt;offloads.vport_reps, i, rep) {</div><div class='ctx'> 		rpriv = rep-&gt;rep_data[REP_ETH].priv;</div><div class='del'>-		if (!rpriv || !rpriv-&gt;netdev)</div><div class='add'>+		if (!rpriv || !rpriv-&gt;netdev || !atomic_read(&amp;rpriv-&gt;tc_ht.nelems))</div><div class='ctx'> 			continue;</div><div class='ctx'> </div><div class='ctx'> 		rhashtable_walk_enter(&amp;rpriv-&gt;tc_ht, &amp;iter);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h<br/>index 0c90f7a8b0d3..ac9c65b89166 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.h</a></div><div class='hunk'>@@ -8,11 +8,6 @@ struct mlx5e_ipsec;</div><div class='ctx'> struct mlx5e_ipsec_sa_entry;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_MLX5_ESWITCH</div><div class='del'>-void mlx5_esw_ipsec_rx_status_destroy(struct mlx5e_ipsec *ipsec,</div><div class='del'>-				      struct mlx5e_ipsec_rx *rx);</div><div class='del'>-int mlx5_esw_ipsec_rx_status_create(struct mlx5e_ipsec *ipsec,</div><div class='del'>-				    struct mlx5e_ipsec_rx *rx,</div><div class='del'>-				    struct mlx5_flow_destination *dest);</div><div class='ctx'> void mlx5_esw_ipsec_rx_create_attr_set(struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 				       struct mlx5e_ipsec_rx_create_attr *attr);</div><div class='ctx'> int mlx5_esw_ipsec_rx_status_pass_dest_get(struct mlx5e_ipsec *ipsec,</div><div class='hunk'>@@ -26,16 +21,6 @@ void mlx5_esw_ipsec_tx_create_attr_set(struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 				       struct mlx5e_ipsec_tx_create_attr *attr);</div><div class='ctx'> void mlx5_esw_ipsec_restore_dest_uplink(struct mlx5_core_dev *mdev);</div><div class='ctx'> #else</div><div class='del'>-static inline void mlx5_esw_ipsec_rx_status_destroy(struct mlx5e_ipsec *ipsec,</div><div class='del'>-						    struct mlx5e_ipsec_rx *rx) {}</div><div class='del'>-</div><div class='del'>-static inline int mlx5_esw_ipsec_rx_status_create(struct mlx5e_ipsec *ipsec,</div><div class='del'>-						  struct mlx5e_ipsec_rx *rx,</div><div class='del'>-						  struct mlx5_flow_destination *dest)</div><div class='del'>-{</div><div class='del'>-	return  -EINVAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline void mlx5_esw_ipsec_rx_create_attr_set(struct mlx5e_ipsec *ipsec,</div><div class='ctx'> 						     struct mlx5e_ipsec_rx_create_attr *attr) {}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c<br/>index 8d0b915a3121..3047d7015c52 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.c</a></div><div class='hunk'>@@ -1463,7 +1463,7 @@ int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	lockdep_assert_held(&amp;esw-&gt;mode_lock);</div><div class='add'>+	devl_assert_locked(priv_to_devlink(esw-&gt;dev));</div><div class='ctx'> </div><div class='ctx'> 	if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw-&gt;dev, ft_support)) {</div><div class='ctx'> 		esw_warn(esw-&gt;dev, "FDB is not supported, aborting ...\n");</div><div class='hunk'>@@ -1531,7 +1531,6 @@ int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs)</div><div class='ctx'> 	if (toggle_lag)</div><div class='ctx'> 		mlx5_lag_disable_change(esw-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	down_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	if (!mlx5_esw_is_fdb_created(esw)) {</div><div class='ctx'> 		ret = mlx5_eswitch_enable_locked(esw, num_vfs);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1554,8 +1553,6 @@ int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	up_write(&amp;esw-&gt;mode_lock);</div><div class='del'>-</div><div class='ctx'> 	if (toggle_lag)</div><div class='ctx'> 		mlx5_lag_enable_change(esw-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -1569,12 +1566,11 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	devl_assert_locked(priv_to_devlink(esw-&gt;dev));</div><div class='del'>-	down_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	/* If driver is unloaded, this function is called twice by remove_one()</div><div class='ctx'> 	 * and mlx5_unload(). Prevent the second call.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (!esw-&gt;esw_funcs.num_vfs &amp;&amp; !esw-&gt;esw_funcs.num_ec_vfs &amp;&amp; !clear_vf)</div><div class='del'>-		goto unlock;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	esw_info(esw-&gt;dev, "Unload vfs: mode(%s), nvfs(%d), necvfs(%d), active vports(%d)\n",</div><div class='ctx'> 		 esw-&gt;mode == MLX5_ESWITCH_LEGACY ? "LEGACY" : "OFFLOADS",</div><div class='hunk'>@@ -1603,9 +1599,6 @@ void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf)</div><div class='ctx'> 		esw-&gt;esw_funcs.num_vfs = 0;</div><div class='ctx'> 	else</div><div class='ctx'> 		esw-&gt;esw_funcs.num_ec_vfs = 0;</div><div class='del'>-</div><div class='del'>-unlock:</div><div class='del'>-	up_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Free resources for corresponding eswitch mode. It is called by devlink</div><div class='hunk'>@@ -1647,10 +1640,8 @@ void mlx5_eswitch_disable(struct mlx5_eswitch *esw)</div><div class='ctx'> </div><div class='ctx'> 	devl_assert_locked(priv_to_devlink(esw-&gt;dev));</div><div class='ctx'> 	mlx5_lag_disable_change(esw-&gt;dev);</div><div class='del'>-	down_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	mlx5_eswitch_disable_locked(esw);</div><div class='ctx'> 	esw-&gt;mode = MLX5_ESWITCH_LEGACY;</div><div class='del'>-	up_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	mlx5_lag_enable_change(esw-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2254,8 +2245,13 @@ bool mlx5_esw_hold(struct mlx5_core_dev *mdev)</div><div class='ctx'> 	if (!mlx5_esw_allowed(esw))</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='del'>-	if (down_read_trylock(&amp;esw-&gt;mode_lock) != 0)</div><div class='add'>+	if (down_read_trylock(&amp;esw-&gt;mode_lock) != 0) {</div><div class='add'>+		if (esw-&gt;eswitch_operation_in_progress) {</div><div class='add'>+			up_read(&amp;esw-&gt;mode_lock);</div><div class='add'>+			return false;</div><div class='add'>+		}</div><div class='ctx'> 		return true;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='hunk'>@@ -2312,7 +2308,8 @@ int mlx5_esw_try_lock(struct mlx5_eswitch *esw)</div><div class='ctx'> 	if (down_write_trylock(&amp;esw-&gt;mode_lock) == 0)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (atomic64_read(&amp;esw-&gt;user_count) &gt; 0) {</div><div class='add'>+	if (esw-&gt;eswitch_operation_in_progress ||</div><div class='add'>+	    atomic64_read(&amp;esw-&gt;user_count) &gt; 0) {</div><div class='ctx'> 		up_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 		return -EBUSY;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2320,6 +2317,18 @@ int mlx5_esw_try_lock(struct mlx5_eswitch *esw)</div><div class='ctx'> 	return esw-&gt;mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int mlx5_esw_lock(struct mlx5_eswitch *esw)</div><div class='add'>+{</div><div class='add'>+	down_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+</div><div class='add'>+	if (esw-&gt;eswitch_operation_in_progress) {</div><div class='add'>+		up_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+		return -EBUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * mlx5_esw_unlock() - Release write lock on esw mode lock</div><div class='ctx'>  * @esw: eswitch device.</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h<br/>index 37ab66e7b403..349e28a6dd8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch.h</a></div><div class='hunk'>@@ -383,6 +383,7 @@ struct mlx5_eswitch {</div><div class='ctx'> 	struct xarray paired;</div><div class='ctx'> 	struct mlx5_devcom_comp_dev *devcom;</div><div class='ctx'> 	u16 enabled_ipsec_vf_count;</div><div class='add'>+	bool eswitch_operation_in_progress;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void esw_offloads_disable(struct mlx5_eswitch *esw);</div><div class='hunk'>@@ -525,7 +526,8 @@ struct mlx5_esw_flow_attr {</div><div class='ctx'> 	u8	total_vlan;</div><div class='ctx'> 	struct {</div><div class='ctx'> 		u32 flags;</div><div class='del'>-		struct mlx5_eswitch_rep *rep;</div><div class='add'>+		bool vport_valid;</div><div class='add'>+		u16 vport;</div><div class='ctx'> 		struct mlx5_pkt_reformat *pkt_reformat;</div><div class='ctx'> 		struct mlx5_core_dev *mdev;</div><div class='ctx'> 		struct mlx5_termtbl_handle *termtbl;</div><div class='hunk'>@@ -616,13 +618,6 @@ static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw)</div><div class='ctx'> 	return esw &amp;&amp; MLX5_ESWITCH_MANAGER(esw-&gt;dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-/* The returned number is valid only when the dev is eswitch manager. */</div><div class='del'>-static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)</div><div class='del'>-{</div><div class='del'>-	return mlx5_core_is_ecpf_esw_manager(dev) ?</div><div class='del'>-		MLX5_VPORT_ECPF : MLX5_VPORT_PF;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static inline bool</div><div class='ctx'> mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)</div><div class='ctx'> {</div><div class='hunk'>@@ -827,6 +822,7 @@ void mlx5_esw_release(struct mlx5_core_dev *dev);</div><div class='ctx'> void mlx5_esw_get(struct mlx5_core_dev *dev);</div><div class='ctx'> void mlx5_esw_put(struct mlx5_core_dev *dev);</div><div class='ctx'> int mlx5_esw_try_lock(struct mlx5_eswitch *esw);</div><div class='add'>+int mlx5_esw_lock(struct mlx5_eswitch *esw);</div><div class='ctx'> void mlx5_esw_unlock(struct mlx5_eswitch *esw);</div><div class='ctx'> </div><div class='ctx'> void esw_vport_change_handle_locked(struct mlx5_vport *vport);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c<br/>index 88236e75fd90..b0455134c98e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c</a></div><div class='hunk'>@@ -287,10 +287,9 @@ static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_</div><div class='ctx'> 	for (i = from; i &lt; to; i++)</div><div class='ctx'> 		if (esw_attr-&gt;dests[i].flags &amp; MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)</div><div class='ctx'> 			mlx5_chains_put_table(chains, 0, 1, 0);</div><div class='del'>-		else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr-&gt;dests[i].rep-&gt;vport,</div><div class='add'>+		else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr-&gt;dests[i].vport,</div><div class='ctx'> 						     esw_attr-&gt;dests[i].mdev))</div><div class='del'>-			mlx5_esw_indir_table_put(esw, esw_attr-&gt;dests[i].rep-&gt;vport,</div><div class='del'>-						 false);</div><div class='add'>+			mlx5_esw_indir_table_put(esw, esw_attr-&gt;dests[i].vport, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool</div><div class='hunk'>@@ -358,8 +357,8 @@ esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)</div><div class='ctx'> 	 * this criteria.</div><div class='ctx'> 	 */</div><div class='ctx'> 	for (i = esw_attr-&gt;split_count; i &lt; esw_attr-&gt;out_count; i++) {</div><div class='del'>-		if (esw_attr-&gt;dests[i].rep &amp;&amp;</div><div class='del'>-		    mlx5_esw_indir_table_needed(esw, attr, esw_attr-&gt;dests[i].rep-&gt;vport,</div><div class='add'>+		if (esw_attr-&gt;dests[i].vport_valid &amp;&amp;</div><div class='add'>+		    mlx5_esw_indir_table_needed(esw, attr, esw_attr-&gt;dests[i].vport,</div><div class='ctx'> 						esw_attr-&gt;dests[i].mdev)) {</div><div class='ctx'> 			result = true;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -388,7 +387,7 @@ esw_setup_indir_table(struct mlx5_flow_destination *dest,</div><div class='ctx'> 		dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;</div><div class='ctx'> </div><div class='ctx'> 		dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,</div><div class='del'>-						       esw_attr-&gt;dests[j].rep-&gt;vport, false);</div><div class='add'>+						       esw_attr-&gt;dests[j].vport, false);</div><div class='ctx'> 		if (IS_ERR(dest[*i].ft)) {</div><div class='ctx'> 			err = PTR_ERR(dest[*i].ft);</div><div class='ctx'> 			goto err_indir_tbl_get;</div><div class='hunk'>@@ -432,11 +431,11 @@ static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,</div><div class='ctx'> 					      int attr_idx)</div><div class='ctx'> {</div><div class='ctx'> 	if (esw-&gt;offloads.ft_ipsec_tx_pol &amp;&amp;</div><div class='del'>-	    esw_attr-&gt;dests[attr_idx].rep &amp;&amp;</div><div class='del'>-	    esw_attr-&gt;dests[attr_idx].rep-&gt;vport == MLX5_VPORT_UPLINK &amp;&amp;</div><div class='add'>+	    esw_attr-&gt;dests[attr_idx].vport_valid &amp;&amp;</div><div class='add'>+	    esw_attr-&gt;dests[attr_idx].vport == MLX5_VPORT_UPLINK &amp;&amp;</div><div class='ctx'> 	    /* To be aligned with software, encryption is needed only for tunnel device */</div><div class='ctx'> 	    (esw_attr-&gt;dests[attr_idx].flags &amp; MLX5_ESW_DEST_ENCAP_VALID) &amp;&amp;</div><div class='del'>-	    esw_attr-&gt;dests[attr_idx].rep != esw_attr-&gt;in_rep &amp;&amp;</div><div class='add'>+	    esw_attr-&gt;dests[attr_idx].vport != esw_attr-&gt;in_rep-&gt;vport &amp;&amp;</div><div class='ctx'> 	    esw_same_vhca_id(esw_attr-&gt;dests[attr_idx].mdev, esw-&gt;dev))</div><div class='ctx'> 		return true;</div><div class='ctx'> </div><div class='hunk'>@@ -469,7 +468,7 @@ esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_ac</div><div class='ctx'> 			 int attr_idx, int dest_idx, bool pkt_reformat)</div><div class='ctx'> {</div><div class='ctx'> 	dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;</div><div class='del'>-	dest[dest_idx].vport.num = esw_attr-&gt;dests[attr_idx].rep-&gt;vport;</div><div class='add'>+	dest[dest_idx].vport.num = esw_attr-&gt;dests[attr_idx].vport;</div><div class='ctx'> 	if (MLX5_CAP_ESW(esw-&gt;dev, merged_eswitch)) {</div><div class='ctx'> 		dest[dest_idx].vport.vhca_id =</div><div class='ctx'> 			MLX5_CAP_GEN(esw_attr-&gt;dests[attr_idx].mdev, vhca_id);</div><div class='hunk'>@@ -1177,9 +1176,9 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,</div><div class='ctx'> 	struct mlx5_flow_handle *flow;</div><div class='ctx'> 	struct mlx5_flow_spec *spec;</div><div class='ctx'> 	struct mlx5_vport *vport;</div><div class='add'>+	int err, pfindex;</div><div class='ctx'> 	unsigned long i;</div><div class='ctx'> 	void *misc;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!MLX5_VPORT_MANAGER(esw-&gt;dev) &amp;&amp; !mlx5_core_is_ecpf_esw_manager(esw-&gt;dev))</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -1255,7 +1254,15 @@ static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,</div><div class='ctx'> 			flows[vport-&gt;index] = flow;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	esw-&gt;fdb_table.offloads.peer_miss_rules[mlx5_get_dev_index(peer_dev)] = flows;</div><div class='add'>+</div><div class='add'>+	pfindex = mlx5_get_dev_index(peer_dev);</div><div class='add'>+	if (pfindex &gt;= MLX5_MAX_PORTS) {</div><div class='add'>+		esw_warn(esw-&gt;dev, "Peer dev index(%d) is over the max num defined(%d)\n",</div><div class='add'>+			 pfindex, MLX5_MAX_PORTS);</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto add_ec_vf_flow_err;</div><div class='add'>+	}</div><div class='add'>+	esw-&gt;fdb_table.offloads.peer_miss_rules[pfindex] = flows;</div><div class='ctx'> </div><div class='ctx'> 	kvfree(spec);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -3653,14 +3660,18 @@ static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)</div><div class='ctx'> </div><div class='ctx'> static bool esw_offloads_devlink_ns_eq_netdev_ns(struct devlink *devlink)</div><div class='ctx'> {</div><div class='add'>+	struct mlx5_core_dev *dev = devlink_priv(devlink);</div><div class='ctx'> 	struct net *devl_net, *netdev_net;</div><div class='del'>-	struct mlx5_eswitch *esw;</div><div class='del'>-</div><div class='del'>-	esw = mlx5_devlink_eswitch_nocheck_get(devlink);</div><div class='del'>-	netdev_net = dev_net(esw-&gt;dev-&gt;mlx5e_res.uplink_netdev);</div><div class='del'>-	devl_net = devlink_net(devlink);</div><div class='add'>+	bool ret = false;</div><div class='ctx'> </div><div class='del'>-	return net_eq(devl_net, netdev_net);</div><div class='add'>+	mutex_lock(&amp;dev-&gt;mlx5e_res.uplink_netdev_lock);</div><div class='add'>+	if (dev-&gt;mlx5e_res.uplink_netdev) {</div><div class='add'>+		netdev_net = dev_net(dev-&gt;mlx5e_res.uplink_netdev);</div><div class='add'>+		devl_net = devlink_net(devlink);</div><div class='add'>+		ret = net_eq(devl_net, netdev_net);</div><div class='add'>+	}</div><div class='add'>+	mutex_unlock(&amp;dev-&gt;mlx5e_res.uplink_netdev_lock);</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev)</div><div class='hunk'>@@ -3733,13 +3744,16 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = true;</div><div class='add'>+	up_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+</div><div class='ctx'> 	mlx5_eswitch_disable_locked(esw);</div><div class='ctx'> 	if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {</div><div class='ctx'> 		if (mlx5_devlink_trap_get_num_active(esw-&gt;dev)) {</div><div class='ctx'> 			NL_SET_ERR_MSG_MOD(extack,</div><div class='ctx'> 					   "Can't change mode while devlink traps are active");</div><div class='ctx'> 			err = -EOPNOTSUPP;</div><div class='del'>-			goto unlock;</div><div class='add'>+			goto skip;</div><div class='ctx'> 		}</div><div class='ctx'> 		err = esw_offloads_start(esw, extack);</div><div class='ctx'> 	} else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {</div><div class='hunk'>@@ -3749,6 +3763,9 @@ int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,</div><div class='ctx'> 		err = -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+skip:</div><div class='add'>+	down_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = false;</div><div class='ctx'> unlock:</div><div class='ctx'> 	mlx5_esw_unlock(esw);</div><div class='ctx'> enable_lag:</div><div class='hunk'>@@ -3759,16 +3776,12 @@ enable_lag:</div><div class='ctx'> int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5_eswitch *esw;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	esw = mlx5_devlink_eswitch_get(devlink);</div><div class='ctx'> 	if (IS_ERR(esw))</div><div class='ctx'> 		return PTR_ERR(esw);</div><div class='ctx'> </div><div class='del'>-	down_read(&amp;esw-&gt;mode_lock);</div><div class='del'>-	err = esw_mode_to_devlink(esw-&gt;mode, mode);</div><div class='del'>-	up_read(&amp;esw-&gt;mode_lock);</div><div class='del'>-	return err;</div><div class='add'>+	return esw_mode_to_devlink(esw-&gt;mode, mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,</div><div class='hunk'>@@ -3862,11 +3875,15 @@ int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = true;</div><div class='add'>+	up_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+</div><div class='ctx'> 	err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);</div><div class='del'>-	if (err)</div><div class='del'>-		goto out;</div><div class='add'>+	if (!err)</div><div class='add'>+		esw-&gt;offloads.inline_mode = mlx5_mode;</div><div class='ctx'> </div><div class='del'>-	esw-&gt;offloads.inline_mode = mlx5_mode;</div><div class='add'>+	down_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = false;</div><div class='ctx'> 	up_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -3878,16 +3895,12 @@ out:</div><div class='ctx'> int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5_eswitch *esw;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	esw = mlx5_devlink_eswitch_get(devlink);</div><div class='ctx'> 	if (IS_ERR(esw))</div><div class='ctx'> 		return PTR_ERR(esw);</div><div class='ctx'> </div><div class='del'>-	down_read(&amp;esw-&gt;mode_lock);</div><div class='del'>-	err = esw_inline_mode_to_devlink(esw-&gt;offloads.inline_mode, mode);</div><div class='del'>-	up_read(&amp;esw-&gt;mode_lock);</div><div class='del'>-	return err;</div><div class='add'>+	return esw_inline_mode_to_devlink(esw-&gt;offloads.inline_mode, mode);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)</div><div class='hunk'>@@ -3969,6 +3982,9 @@ int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,</div><div class='ctx'> 		goto unlock;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = true;</div><div class='add'>+	up_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+</div><div class='ctx'> 	esw_destroy_offloads_fdb_tables(esw);</div><div class='ctx'> </div><div class='ctx'> 	esw-&gt;offloads.encap = encap;</div><div class='hunk'>@@ -3982,6 +3998,9 @@ int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,</div><div class='ctx'> 		(void)esw_create_offloads_fdb_tables(esw);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	down_write(&amp;esw-&gt;mode_lock);</div><div class='add'>+	esw-&gt;eswitch_operation_in_progress = false;</div><div class='add'>+</div><div class='ctx'> unlock:</div><div class='ctx'> 	up_write(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -3996,9 +4015,7 @@ int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,</div><div class='ctx'> 	if (IS_ERR(esw))</div><div class='ctx'> 		return PTR_ERR(esw);</div><div class='ctx'> </div><div class='del'>-	down_read(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	*encap = esw-&gt;offloads.encap;</div><div class='del'>-	up_read(&amp;esw-&gt;mode_lock);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c<br/>index edd910258314..40bdc677f051 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads_termtbl.c</a></div><div class='hunk'>@@ -233,8 +233,8 @@ mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,</div><div class='ctx'> </div><div class='ctx'> 	/* hairpin */</div><div class='ctx'> 	for (i = esw_attr-&gt;split_count; i &lt; esw_attr-&gt;out_count; i++)</div><div class='del'>-		if (!esw_attr-&gt;dest_int_port &amp;&amp; esw_attr-&gt;dests[i].rep &amp;&amp;</div><div class='del'>-		    esw_attr-&gt;dests[i].rep-&gt;vport == MLX5_VPORT_UPLINK)</div><div class='add'>+		if (!esw_attr-&gt;dest_int_port &amp;&amp; esw_attr-&gt;dests[i].vport_valid &amp;&amp;</div><div class='add'>+		    esw_attr-&gt;dests[i].vport == MLX5_VPORT_UPLINK)</div><div class='ctx'> 			return true;</div><div class='ctx'> </div><div class='ctx'> 	return false;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c<br/>index a4b925331661..1616a6144f7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c</a></div><div class='hunk'>@@ -1144,3 +1144,37 @@ const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default(enum fs_flow_table_type typ</div><div class='ctx'> 		return mlx5_fs_cmd_get_stub_cmds();</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int mlx5_fs_cmd_set_l2table_entry_silent(struct mlx5_core_dev *dev, u8 silent_mode)</div><div class='add'>+{</div><div class='add'>+	u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {};</div><div class='add'>+</div><div class='add'>+	if (silent_mode &amp;&amp; !MLX5_CAP_GEN(dev, silent_mode))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	MLX5_SET(set_l2_table_entry_in, in, opcode, MLX5_CMD_OP_SET_L2_TABLE_ENTRY);</div><div class='add'>+	MLX5_SET(set_l2_table_entry_in, in, silent_mode_valid, 1);</div><div class='add'>+	MLX5_SET(set_l2_table_entry_in, in, silent_mode, silent_mode);</div><div class='add'>+</div><div class='add'>+	return mlx5_cmd_exec_in(dev, set_l2_table_entry, in);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int mlx5_fs_cmd_set_tx_flow_table_root(struct mlx5_core_dev *dev, u32 ft_id, bool disconnect)</div><div class='add'>+{</div><div class='add'>+	u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};</div><div class='add'>+	u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};</div><div class='add'>+</div><div class='add'>+	if (disconnect &amp;&amp; MLX5_CAP_FLOWTABLE_NIC_TX(dev, reset_root_to_default))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	MLX5_SET(set_flow_table_root_in, in, opcode,</div><div class='add'>+		 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);</div><div class='add'>+	MLX5_SET(set_flow_table_root_in, in, table_type,</div><div class='add'>+		 FS_FT_NIC_TX);</div><div class='add'>+	if (disconnect)</div><div class='add'>+		MLX5_SET(set_flow_table_root_in, in, op_mod, 1);</div><div class='add'>+	else</div><div class='add'>+		MLX5_SET(set_flow_table_root_in, in, table_id, ft_id);</div><div class='add'>+</div><div class='add'>+	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h<br/>index 7790ae5531e1..53e0e5137d3f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.h</a></div><div class='hunk'>@@ -122,4 +122,6 @@ int mlx5_cmd_fc_bulk_query(struct mlx5_core_dev *dev, u32 base_id, int bulk_len,</div><div class='ctx'> const struct mlx5_flow_cmds *mlx5_fs_cmd_get_default(enum fs_flow_table_type type);</div><div class='ctx'> const struct mlx5_flow_cmds *mlx5_fs_cmd_get_fw_cmds(void);</div><div class='ctx'> </div><div class='add'>+int mlx5_fs_cmd_set_l2table_entry_silent(struct mlx5_core_dev *dev, u8 silent_mode);</div><div class='add'>+int mlx5_fs_cmd_set_tx_flow_table_root(struct mlx5_core_dev *dev, u32 ft_id, bool disconnect);</div><div class='ctx'> #endif</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h<br/>index 4aed1768b85f..78eb6b7097e1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/fs_core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_core.h</a></div><div class='hunk'>@@ -181,7 +181,7 @@ struct mlx5_flow_rule {</div><div class='ctx'> </div><div class='ctx'> struct mlx5_flow_handle {</div><div class='ctx'> 	int num_rules;</div><div class='del'>-	struct mlx5_flow_rule *rule[];</div><div class='add'>+	struct mlx5_flow_rule *rule[] __counted_by(num_rules);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Type of children is mlx5_flow_group */</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c<br/>index 17fe30a4c06c..0c26d707eed2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c</a></div><div class='hunk'>@@ -539,7 +539,7 @@ struct mlx5_fc_bulk {</div><div class='ctx'> 	u32 base_id;</div><div class='ctx'> 	int bulk_len;</div><div class='ctx'> 	unsigned long *bitmask;</div><div class='del'>-	struct mlx5_fc fcs[];</div><div class='add'>+	struct mlx5_fc fcs[] __counted_by(bulk_len);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void mlx5_fc_init(struct mlx5_fc *counter, struct mlx5_fc_bulk *bulk,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c<br/>index b568988e92e3..f27eab6e4929 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c</a></div><div class='hunk'>@@ -325,6 +325,48 @@ static void mlx5_fw_live_patch_event(struct work_struct *work)</div><div class='ctx'> 		mlx5_core_err(dev, "Failed to reload FW tracer\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)</div><div class='add'>+static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *bridge = dev-&gt;pdev-&gt;bus-&gt;self;</div><div class='add'>+	u16 reg16;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!bridge)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, &amp;reg16);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if ((reg16 &amp; PCI_EXP_SLTCTL_HPIE) &amp;&amp; (reg16 &amp; PCI_EXP_SLTCTL_DLLSCE)) {</div><div class='add'>+		mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+static const struct pci_device_id mgt_ifc_device_ids[] = {</div><div class='add'>+	{ PCI_VDEVICE(MELLANOX, 0xc2d2) }, /* BlueField1 MGT interface device ID */</div><div class='add'>+	{ PCI_VDEVICE(MELLANOX, 0xc2d3) }, /* BlueField2 MGT interface device ID */</div><div class='add'>+	{ PCI_VDEVICE(MELLANOX, 0xc2d4) }, /* BlueField3-Lx MGT interface device ID */</div><div class='add'>+	{ PCI_VDEVICE(MELLANOX, 0xc2d5) }, /* BlueField3 MGT interface device ID */</div><div class='add'>+	{ PCI_VDEVICE(MELLANOX, 0xc2d6) }, /* BlueField4 MGT interface device ID */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static bool mlx5_is_mgt_ifc_pci_device(struct mlx5_core_dev *dev, u16 dev_id)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(mgt_ifc_device_ids); ++i)</div><div class='add'>+		if (mgt_ifc_device_ids[i].device == dev_id)</div><div class='add'>+			return true;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_bus *bridge_bus = dev-&gt;pdev-&gt;bus;</div><div class='hunk'>@@ -339,10 +381,15 @@ static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)</div><div class='ctx'> 		err = pci_read_config_word(sdev, PCI_DEVICE_ID, &amp;sdev_id);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			return pcibios_err_to_errno(err);</div><div class='del'>-		if (sdev_id != dev_id) {</div><div class='del'>-			mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);</div><div class='del'>-			return -EPERM;</div><div class='del'>-		}</div><div class='add'>+</div><div class='add'>+		if (sdev_id == dev_id)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (mlx5_is_mgt_ifc_pci_device(dev, sdev_id))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);</div><div class='add'>+		return -EPERM;</div><div class='ctx'> 	}</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -357,6 +404,12 @@ static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev)</div><div class='ctx'> 		return false;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+#if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)</div><div class='add'>+	err = mlx5_check_hotplug_interrupt(dev);</div><div class='add'>+	if (err)</div><div class='add'>+		return false;</div><div class='add'>+#endif</div><div class='add'>+</div><div class='ctx'> 	err = pci_read_config_word(dev-&gt;pdev, PCI_DEVICE_ID, &amp;dev_id);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return false;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c<br/>index 2bf77a5251b4..58845121954c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c</a></div><div class='hunk'>@@ -339,7 +339,7 @@ static int mlx5i_init_tx(struct mlx5e_priv *priv)</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = mlx5i_create_tis(priv-&gt;mdev, ipriv-&gt;qpn, &amp;priv-&gt;tisn[0][0]);</div><div class='add'>+	err = mlx5i_create_tis(priv-&gt;mdev, ipriv-&gt;qpn, &amp;ipriv-&gt;tisn);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		mlx5_core_warn(priv-&gt;mdev, "create tis failed, %d\n", err);</div><div class='ctx'> 		goto err_destroy_underlay_qp;</div><div class='hunk'>@@ -356,7 +356,7 @@ static void mlx5i_cleanup_tx(struct mlx5e_priv *priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5i_priv *ipriv = priv-&gt;ppriv;</div><div class='ctx'> </div><div class='del'>-	mlx5e_destroy_tis(priv-&gt;mdev, priv-&gt;tisn[0][0]);</div><div class='add'>+	mlx5e_destroy_tis(priv-&gt;mdev, ipriv-&gt;tisn);</div><div class='ctx'> 	mlx5i_destroy_underlay_qp(priv-&gt;mdev, ipriv-&gt;qpn);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -483,6 +483,18 @@ static unsigned int mlx5i_stats_grps_num(struct mlx5e_priv *priv)</div><div class='ctx'> 	return ARRAY_SIZE(mlx5i_stats_grps);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+u32 mlx5i_get_tisn(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, u8 lag_port, u8 tc)</div><div class='add'>+{</div><div class='add'>+	struct mlx5i_priv *ipriv = priv-&gt;ppriv;</div><div class='add'>+</div><div class='add'>+	if (WARN(lag_port || tc,</div><div class='add'>+		 "IPoIB unexpected non-zero value: lag_port (%u), tc (%u)\n",</div><div class='add'>+		 lag_port, tc))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return ipriv-&gt;tisn;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct mlx5e_profile mlx5i_nic_profile = {</div><div class='ctx'> 	.init		   = mlx5i_init,</div><div class='ctx'> 	.cleanup	   = mlx5i_cleanup,</div><div class='hunk'>@@ -499,6 +511,7 @@ static const struct mlx5e_profile mlx5i_nic_profile = {</div><div class='ctx'> 	.max_tc		   = MLX5I_MAX_NUM_TC,</div><div class='ctx'> 	.stats_grps        = mlx5i_stats_grps,</div><div class='ctx'> 	.stats_grps_num    = mlx5i_stats_grps_num,</div><div class='add'>+	.get_tisn          = mlx5i_get_tisn,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* mlx5i netdev NDos */</div><div class='hunk'>@@ -829,7 +842,7 @@ int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,</div><div class='ctx'> 	*params = (struct rdma_netdev_alloc_params){</div><div class='ctx'> 		.sizeof_priv = sizeof(struct mlx5i_priv) +</div><div class='ctx'> 			       sizeof(struct mlx5e_priv),</div><div class='del'>-		.txqs = nch * MLX5E_MAX_NUM_TC,</div><div class='add'>+		.txqs = nch * MLX5_MAX_NUM_TC,</div><div class='ctx'> 		.rxqs = nch,</div><div class='ctx'> 		.param = mdev,</div><div class='ctx'> 		.initialize_rdma_netdev = mlx5_rdma_setup_rn,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h<br/>index f3f2af972020..2ab6437a1c49 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.h</a></div><div class='hunk'>@@ -53,6 +53,7 @@ extern const struct mlx5e_rx_handlers mlx5i_rx_handlers;</div><div class='ctx'> struct mlx5i_priv {</div><div class='ctx'> 	struct rdma_netdev rn; /* keep this first */</div><div class='ctx'> 	u32 qpn;</div><div class='add'>+	u32 tisn;</div><div class='ctx'> 	bool   sub_interface;</div><div class='ctx'> 	u32    num_sub_interfaces;</div><div class='ctx'> 	u32    qkey;</div><div class='hunk'>@@ -63,6 +64,7 @@ struct mlx5i_priv {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn);</div><div class='add'>+u32 mlx5i_get_tisn(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, u8 lag_port, u8 tc);</div><div class='ctx'> </div><div class='ctx'> /* Underlay QP create/destroy functions */</div><div class='ctx'> int mlx5i_create_underlay_qp(struct mlx5e_priv *priv);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c<br/>index 03e681297937..f87471306f6b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib_vlan.c</a></div><div class='hunk'>@@ -218,7 +218,7 @@ static int mlx5i_pkey_open(struct net_device *netdev)</div><div class='ctx'> 		goto err_unint_underlay_qp;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = mlx5i_create_tis(mdev, ipriv-&gt;qpn, &amp;epriv-&gt;tisn[0][0]);</div><div class='add'>+	err = mlx5i_create_tis(mdev, ipriv-&gt;qpn, &amp;ipriv-&gt;tisn);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		mlx5_core_warn(mdev, "create child tis failed, %d\n", err);</div><div class='ctx'> 		goto err_remove_rx_uderlay_qp;</div><div class='hunk'>@@ -240,7 +240,7 @@ static int mlx5i_pkey_open(struct net_device *netdev)</div><div class='ctx'> err_close_channels:</div><div class='ctx'> 	mlx5e_close_channels(&amp;epriv-&gt;channels);</div><div class='ctx'> err_clear_state_opened_flag:</div><div class='del'>-	mlx5e_destroy_tis(mdev, epriv-&gt;tisn[0][0]);</div><div class='add'>+	mlx5e_destroy_tis(mdev, ipriv-&gt;tisn);</div><div class='ctx'> err_remove_rx_uderlay_qp:</div><div class='ctx'> 	mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv-&gt;qpn);</div><div class='ctx'> err_unint_underlay_qp:</div><div class='hunk'>@@ -269,7 +269,7 @@ static int mlx5i_pkey_close(struct net_device *netdev)</div><div class='ctx'> 	mlx5i_uninit_underlay_qp(priv);</div><div class='ctx'> 	mlx5e_deactivate_priv_channels(priv);</div><div class='ctx'> 	mlx5e_close_channels(&amp;priv-&gt;channels);</div><div class='del'>-	mlx5e_destroy_tis(mdev, priv-&gt;tisn[0][0]);</div><div class='add'>+	mlx5e_destroy_tis(mdev, ipriv-&gt;tisn);</div><div class='ctx'> unlock:</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;state_lock);</div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -361,6 +361,7 @@ static const struct mlx5e_profile mlx5i_pkey_nic_profile = {</div><div class='ctx'> 	.update_stats	   = NULL,</div><div class='ctx'> 	.rx_handlers       = &amp;mlx5i_rx_handlers,</div><div class='ctx'> 	.max_tc		   = MLX5I_MAX_NUM_TC,</div><div class='add'>+	.get_tisn          = mlx5i_get_tisn,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct mlx5e_profile *mlx5i_pkey_get_profile(void)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c<br/>index 0c83ef174275..0361741632a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c</a></div><div class='hunk'>@@ -266,9 +266,6 @@ static int mlx5_ptp_settime_real_time(struct mlx5_core_dev *mdev,</div><div class='ctx'> {</div><div class='ctx'> 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};</div><div class='ctx'> </div><div class='del'>-	if (!mlx5_modify_mtutc_allowed(mdev))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	if (ts-&gt;tv_sec &lt; 0 || ts-&gt;tv_sec &gt; U32_MAX ||</div><div class='ctx'> 	    ts-&gt;tv_nsec &lt; 0 || ts-&gt;tv_nsec &gt; NSEC_PER_SEC)</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -286,12 +283,15 @@ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64</div><div class='ctx'> 	struct mlx5_timer *timer = &amp;clock-&gt;timer;</div><div class='ctx'> 	struct mlx5_core_dev *mdev;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	mdev = container_of(clock, struct mlx5_core_dev, clock);</div><div class='del'>-	err = mlx5_ptp_settime_real_time(mdev, ts);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='add'>+</div><div class='add'>+	if (mlx5_modify_mtutc_allowed(mdev)) {</div><div class='add'>+		int err = mlx5_ptp_settime_real_time(mdev, ts);</div><div class='add'>+</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	write_seqlock_irqsave(&amp;clock-&gt;lock, flags);</div><div class='ctx'> 	timecounter_init(&amp;timer-&gt;tc, &amp;timer-&gt;cycles, timespec64_to_ns(ts));</div><div class='hunk'>@@ -341,9 +341,6 @@ static int mlx5_ptp_adjtime_real_time(struct mlx5_core_dev *mdev, s64 delta)</div><div class='ctx'> {</div><div class='ctx'> 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};</div><div class='ctx'> </div><div class='del'>-	if (!mlx5_modify_mtutc_allowed(mdev))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	/* HW time adjustment range is checked. If out of range, settime instead */</div><div class='ctx'> 	if (!mlx5_is_mtutc_time_adj_cap(mdev, delta)) {</div><div class='ctx'> 		struct timespec64 ts;</div><div class='hunk'>@@ -367,13 +364,16 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)</div><div class='ctx'> 	struct mlx5_timer *timer = &amp;clock-&gt;timer;</div><div class='ctx'> 	struct mlx5_core_dev *mdev;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	mdev = container_of(clock, struct mlx5_core_dev, clock);</div><div class='ctx'> </div><div class='del'>-	err = mlx5_ptp_adjtime_real_time(mdev, delta);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='add'>+	if (mlx5_modify_mtutc_allowed(mdev)) {</div><div class='add'>+		int err = mlx5_ptp_adjtime_real_time(mdev, delta);</div><div class='add'>+</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	write_seqlock_irqsave(&amp;clock-&gt;lock, flags);</div><div class='ctx'> 	timecounter_adjtime(&amp;timer-&gt;tc, delta);</div><div class='ctx'> 	mlx5_update_clock_info_page(mdev);</div><div class='hunk'>@@ -396,15 +396,14 @@ static int mlx5_ptp_freq_adj_real_time(struct mlx5_core_dev *mdev, long scaled_p</div><div class='ctx'> {</div><div class='ctx'> 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};</div><div class='ctx'> </div><div class='del'>-	if (!mlx5_modify_mtutc_allowed(mdev))</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='ctx'> 	MLX5_SET(mtutc_reg, in, operation, MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC);</div><div class='ctx'> </div><div class='del'>-	if (MLX5_CAP_MCAM_FEATURE(mdev, mtutc_freq_adj_units)) {</div><div class='add'>+	if (MLX5_CAP_MCAM_FEATURE(mdev, mtutc_freq_adj_units) &amp;&amp;</div><div class='add'>+	    scaled_ppm &lt;= S32_MAX &amp;&amp; scaled_ppm &gt;= S32_MIN) {</div><div class='add'>+		/* HW scaled_ppm support on mlx5 devices only supports a 32-bit value */</div><div class='ctx'> 		MLX5_SET(mtutc_reg, in, freq_adj_units,</div><div class='ctx'> 			 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM);</div><div class='del'>-		MLX5_SET(mtutc_reg, in, freq_adjustment, scaled_ppm);</div><div class='add'>+		MLX5_SET(mtutc_reg, in, freq_adjustment, (s32)scaled_ppm);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		MLX5_SET(mtutc_reg, in, freq_adj_units, MLX5_MTUTC_FREQ_ADJ_UNITS_PPB);</div><div class='ctx'> 		MLX5_SET(mtutc_reg, in, freq_adjustment, scaled_ppm_to_ppb(scaled_ppm));</div><div class='hunk'>@@ -420,13 +419,15 @@ static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)</div><div class='ctx'> 	struct mlx5_core_dev *mdev;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 mult;</div><div class='del'>-	int err;</div><div class='ctx'> </div><div class='ctx'> 	mdev = container_of(clock, struct mlx5_core_dev, clock);</div><div class='ctx'> </div><div class='del'>-	err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='add'>+	if (mlx5_modify_mtutc_allowed(mdev)) {</div><div class='add'>+		int err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm);</div><div class='add'>+</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	mult = (u32)adjust_by_scaled_ppm(timer-&gt;nominal_c_mult, scaled_ppm);</div><div class='ctx'> </div><div class='hunk'>@@ -1004,14 +1005,38 @@ static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)</div><div class='ctx'> 	info-&gt;frac = timer-&gt;tc.frac;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mlx5_init_timer_max_freq_adjustment(struct mlx5_core_dev *mdev)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_clock *clock = &amp;mdev-&gt;clock;</div><div class='add'>+	u32 out[MLX5_ST_SZ_DW(mtutc_reg)] = {};</div><div class='add'>+	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};</div><div class='add'>+	u8 log_max_freq_adjustment = 0;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),</div><div class='add'>+				   MLX5_REG_MTUTC, 0, 0);</div><div class='add'>+	if (!err)</div><div class='add'>+		log_max_freq_adjustment =</div><div class='add'>+			MLX5_GET(mtutc_reg, out, log_max_freq_adjustment);</div><div class='add'>+</div><div class='add'>+	if (log_max_freq_adjustment)</div><div class='add'>+		clock-&gt;ptp_info.max_adj =</div><div class='add'>+			min(S32_MAX, 1 &lt;&lt; log_max_freq_adjustment);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlx5_clock *clock = &amp;mdev-&gt;clock;</div><div class='ctx'> </div><div class='add'>+	/* Configure the PHC */</div><div class='add'>+	clock-&gt;ptp_info = mlx5_ptp_clock_info;</div><div class='add'>+</div><div class='add'>+	if (MLX5_CAP_MCAM_REG(mdev, mtutc))</div><div class='add'>+		mlx5_init_timer_max_freq_adjustment(mdev);</div><div class='add'>+</div><div class='ctx'> 	mlx5_timecounter_init(mdev);</div><div class='ctx'> 	mlx5_init_clock_info(mdev);</div><div class='ctx'> 	mlx5_init_overflow_period(clock);</div><div class='del'>-	clock-&gt;ptp_info = mlx5_ptp_clock_info;</div><div class='ctx'> </div><div class='ctx'> 	if (mlx5_real_time_mode(mdev)) {</div><div class='ctx'> 		struct timespec64 ts;</div><div class='hunk'>@@ -1042,11 +1067,10 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	seqlock_init(&amp;clock-&gt;lock);</div><div class='del'>-	mlx5_init_timer_clock(mdev);</div><div class='ctx'> 	INIT_WORK(&amp;clock-&gt;pps_info.out_work, mlx5_pps_out);</div><div class='ctx'> </div><div class='del'>-	/* Configure the PHC */</div><div class='del'>-	clock-&gt;ptp_info = mlx5_ptp_clock_info;</div><div class='add'>+	/* Initialize the device clock */</div><div class='add'>+	mlx5_init_timer_clock(mdev);</div><div class='ctx'> </div><div class='ctx'> 	/* Initialize 1PPS data structures */</div><div class='ctx'> 	mlx5_init_pps(mdev);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c<br/>index e8e50563e956..e7d59cfa8708 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c</a></div><div class='hunk'>@@ -256,6 +256,13 @@ void mlx5_devcom_unregister_component(struct mlx5_devcom_comp_dev *devcom)</div><div class='ctx'> 		devcom_free_comp_dev(devcom);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int mlx5_devcom_comp_get_size(struct mlx5_devcom_comp_dev *devcom)</div><div class='add'>+{</div><div class='add'>+	struct mlx5_devcom_comp *comp = devcom-&gt;comp;</div><div class='add'>+</div><div class='add'>+	return kref_read(&amp;comp-&gt;ref);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom,</div><div class='ctx'> 			   int event, int rollback_event,</div><div class='ctx'> 			   void *event_data)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h<br/>index fc23bbef87b4..ec32b686f586 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.h</a></div><div class='hunk'>@@ -31,6 +31,7 @@ void mlx5_devcom_unregister_component(struct mlx5_devcom_comp_dev *devcom);</div><div class='ctx'> int mlx5_devcom_send_event(struct mlx5_devcom_comp_dev *devcom,</div><div class='ctx'> 			   int event, int rollback_event,</div><div class='ctx'> 			   void *event_data);</div><div class='add'>+int mlx5_devcom_comp_get_size(struct mlx5_devcom_comp_dev *devcom);</div><div class='ctx'> </div><div class='ctx'> void mlx5_devcom_comp_set_ready(struct mlx5_devcom_comp_dev *devcom, bool ready);</div><div class='ctx'> bool mlx5_devcom_comp_is_ready(struct mlx5_devcom_comp_dev *devcom);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c<br/>index 9482e51ac82a..7c5516b0a844 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/lib/dm.c</a></div><div class='hunk'>@@ -13,11 +13,13 @@ struct mlx5_dm {</div><div class='ctx'> 	unsigned long *steering_sw_icm_alloc_blocks;</div><div class='ctx'> 	unsigned long *header_modify_sw_icm_alloc_blocks;</div><div class='ctx'> 	unsigned long *header_modify_pattern_sw_icm_alloc_blocks;</div><div class='add'>+	unsigned long *header_encap_sw_icm_alloc_blocks;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)</div><div class='ctx'> {</div><div class='ctx'> 	u64 header_modify_pattern_icm_blocks = 0;</div><div class='add'>+	u64 header_sw_encap_icm_blocks = 0;</div><div class='ctx'> 	u64 header_modify_icm_blocks = 0;</div><div class='ctx'> 	u64 steering_icm_blocks = 0;</div><div class='ctx'> 	struct mlx5_dm *dm;</div><div class='hunk'>@@ -54,6 +56,17 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)</div><div class='ctx'> 			goto err_modify_hdr;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (MLX5_CAP_DEV_MEM(dev, log_indirect_encap_sw_icm_size)) {</div><div class='add'>+		header_sw_encap_icm_blocks =</div><div class='add'>+			BIT(MLX5_CAP_DEV_MEM(dev, log_indirect_encap_sw_icm_size) -</div><div class='add'>+			    MLX5_LOG_SW_ICM_BLOCK_SIZE(dev));</div><div class='add'>+</div><div class='add'>+		dm-&gt;header_encap_sw_icm_alloc_blocks =</div><div class='add'>+			bitmap_zalloc(header_sw_encap_icm_blocks, GFP_KERNEL);</div><div class='add'>+		if (!dm-&gt;header_encap_sw_icm_alloc_blocks)</div><div class='add'>+			goto err_pattern;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	support_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(dev, sw_owner_v2) &amp;&amp;</div><div class='ctx'> 		     MLX5_CAP_FLOWTABLE_NIC_TX(dev, sw_owner_v2) &amp;&amp;</div><div class='ctx'> 		     MLX5_CAP64_DEV_MEM(dev, header_modify_pattern_sw_icm_start_address);</div><div class='hunk'>@@ -66,11 +79,14 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)</div><div class='ctx'> 		dm-&gt;header_modify_pattern_sw_icm_alloc_blocks =</div><div class='ctx'> 			bitmap_zalloc(header_modify_pattern_icm_blocks, GFP_KERNEL);</div><div class='ctx'> 		if (!dm-&gt;header_modify_pattern_sw_icm_alloc_blocks)</div><div class='del'>-			goto err_pattern;</div><div class='add'>+			goto err_sw_encap;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return dm;</div><div class='ctx'> </div><div class='add'>+err_sw_encap:</div><div class='add'>+	bitmap_free(dm-&gt;header_encap_sw_icm_alloc_blocks);</div><div class='add'>+</div><div class='ctx'> err_pattern:</div><div class='ctx'> 	bitmap_free(dm-&gt;header_modify_sw_icm_alloc_blocks);</div><div class='ctx'> </div><div class='hunk'>@@ -105,6 +121,14 @@ void mlx5_dm_cleanup(struct mlx5_core_dev *dev)</div><div class='ctx'> 		bitmap_free(dm-&gt;header_modify_sw_icm_alloc_blocks);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dm-&gt;header_encap_sw_icm_alloc_blocks) {</div><div class='add'>+		WARN_ON(!bitmap_empty(dm-&gt;header_encap_sw_icm_alloc_blocks,</div><div class='add'>+				      BIT(MLX5_CAP_DEV_MEM(dev,</div><div class='add'>+							   log_indirect_encap_sw_icm_size) -</div><div class='add'>+				      MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))));</div><div class='add'>+		bitmap_free(dm-&gt;header_encap_sw_icm_alloc_blocks);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (dm-&gt;header_modify_pattern_sw_icm_alloc_blocks) {</div><div class='ctx'> 		WARN_ON(!bitmap_empty(dm-&gt;header_modify_pattern_sw_icm_alloc_blocks,</div><div class='ctx'> 				      BIT(MLX5_CAP_DEV_MEM(dev,</div><div class='hunk'>@@ -164,6 +188,13 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,</div><div class='ctx'> 						log_header_modify_pattern_sw_icm_size);</div><div class='ctx'> 		block_map = dm-&gt;header_modify_pattern_sw_icm_alloc_blocks;</div><div class='ctx'> 		break;</div><div class='add'>+	case MLX5_SW_ICM_TYPE_SW_ENCAP:</div><div class='add'>+		icm_start_addr = MLX5_CAP64_DEV_MEM(dev,</div><div class='add'>+						    indirect_encap_sw_icm_start_address);</div><div class='add'>+		log_icm_size = MLX5_CAP_DEV_MEM(dev,</div><div class='add'>+						log_indirect_encap_sw_icm_size);</div><div class='add'>+		block_map = dm-&gt;header_encap_sw_icm_alloc_blocks;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -242,6 +273,11 @@ int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type</div><div class='ctx'> 						    header_modify_pattern_sw_icm_start_address);</div><div class='ctx'> 		block_map = dm-&gt;header_modify_pattern_sw_icm_alloc_blocks;</div><div class='ctx'> 		break;</div><div class='add'>+	case MLX5_SW_ICM_TYPE_SW_ENCAP:</div><div class='add'>+		icm_start_addr = MLX5_CAP64_DEV_MEM(dev,</div><div class='add'>+						    indirect_encap_sw_icm_start_address);</div><div class='add'>+		block_map = dm-&gt;header_encap_sw_icm_alloc_blocks;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c<br/>index a17152c1cbb2..bccf6e53556c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/main.c</a></div><div class='hunk'>@@ -219,7 +219,6 @@ static void mlx5_set_driver_version(struct mlx5_core_dev *dev)</div><div class='ctx'> 	int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,</div><div class='ctx'> 					      driver_version);</div><div class='ctx'> 	u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};</div><div class='del'>-	int remaining_size = driver_ver_sz;</div><div class='ctx'> 	char *string;</div><div class='ctx'> </div><div class='ctx'> 	if (!MLX5_CAP_GEN(dev, driver_version))</div><div class='hunk'>@@ -227,22 +226,9 @@ static void mlx5_set_driver_version(struct mlx5_core_dev *dev)</div><div class='ctx'> </div><div class='ctx'> 	string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);</div><div class='ctx'> </div><div class='del'>-	strncpy(string, "Linux", remaining_size);</div><div class='del'>-</div><div class='del'>-	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));</div><div class='del'>-	strncat(string, ",", remaining_size);</div><div class='del'>-</div><div class='del'>-	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));</div><div class='del'>-	strncat(string, KBUILD_MODNAME, remaining_size);</div><div class='del'>-</div><div class='del'>-	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));</div><div class='del'>-	strncat(string, ",", remaining_size);</div><div class='del'>-</div><div class='del'>-	remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));</div><div class='del'>-</div><div class='del'>-	snprintf(string + strlen(string), remaining_size, "%u.%u.%u",</div><div class='del'>-		LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,</div><div class='del'>-		LINUX_VERSION_SUBLEVEL);</div><div class='add'>+	snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",</div><div class='add'>+		 KBUILD_MODNAME, LINUX_VERSION_MAJOR,</div><div class='add'>+		 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);</div><div class='ctx'> </div><div class='ctx'> 	/*Send the command*/</div><div class='ctx'> 	MLX5_SET(set_driver_version_in, in, opcode,</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h<br/>index 6b14e347d914..a79b7959361b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h</a></div><div class='hunk'>@@ -243,6 +243,7 @@ int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,</div><div class='ctx'> 			u8 access_reg_group);</div><div class='ctx'> int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,</div><div class='ctx'> 			u8 feature_group, u8 access_reg_group);</div><div class='add'>+int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir);</div><div class='ctx'> </div><div class='ctx'> void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);</div><div class='ctx'> void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c<br/>index 7d8c732818f2..7fba1c46e2ac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/port.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/port.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/port.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/port.c</a></div><div class='hunk'>@@ -1206,3 +1206,13 @@ int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)</div><div class='ctx'> 	*speed = max_speed;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir)</div><div class='add'>+{</div><div class='add'>+	u32 in[MLX5_ST_SZ_DW(mpir_reg)] = {};</div><div class='add'>+	int sz = MLX5_ST_SZ_BYTES(mpir_reg);</div><div class='add'>+</div><div class='add'>+	MLX5_SET(mpir_reg, in, local_port, 1);</div><div class='add'>+</div><div class='add'>+	return mlx5_core_access_reg(dev, in, sz, mpir, sz, MLX5_REG_MPIR, 0, 0);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c<br/>index e3ec559369fa..6f9790e97fed 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c</a></div><div class='hunk'>@@ -1170,7 +1170,6 @@ mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,</div><div class='ctx'> 				   bool ignore_flow_level,</div><div class='ctx'> 				   u32 flow_source)</div><div class='ctx'> {</div><div class='del'>-	struct mlx5dr_cmd_flow_destination_hw_info tmp_hw_dest;</div><div class='ctx'> 	struct mlx5dr_cmd_flow_destination_hw_info *hw_dests;</div><div class='ctx'> 	struct mlx5dr_action **ref_actions;</div><div class='ctx'> 	struct mlx5dr_action *action;</div><div class='hunk'>@@ -1249,11 +1248,8 @@ mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,</div><div class='ctx'> 	 * one that done in the TX.</div><div class='ctx'> 	 * So, if one of the ft target is wire, put it at the end of the dest list.</div><div class='ctx'> 	 */</div><div class='del'>-	if (is_ft_wire &amp;&amp; num_dst_ft &gt; 1) {</div><div class='del'>-		tmp_hw_dest = hw_dests[last_dest];</div><div class='del'>-		hw_dests[last_dest] = hw_dests[num_of_dests - 1];</div><div class='del'>-		hw_dests[num_of_dests - 1] = tmp_hw_dest;</div><div class='del'>-	}</div><div class='add'>+	if (is_ft_wire &amp;&amp; num_dst_ft &gt; 1)</div><div class='add'>+		swap(hw_dests[last_dest], hw_dests[num_of_dests - 1]);</div><div class='ctx'> </div><div class='ctx'> 	action = dr_action_create_generic(DR_ACTION_TYP_FT);</div><div class='ctx'> 	if (!action)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/vport.c b/drivers/net/ethernet/mellanox/mlx5/core/vport.c<br/>index 5a31fb47ffa5..21753f327868 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/vport.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlx5/core/vport.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlx5/core/vport.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlx5/core/vport.c</a></div><div class='hunk'>@@ -277,7 +277,7 @@ int mlx5_query_nic_vport_mac_list(struct mlx5_core_dev *dev,</div><div class='ctx'> 		req_list_size = max_list_size;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	out_sz = MLX5_ST_SZ_BYTES(query_nic_vport_context_in) +</div><div class='add'>+	out_sz = MLX5_ST_SZ_BYTES(query_nic_vport_context_out) +</div><div class='ctx'> 			req_list_size * MLX5_ST_SZ_BYTES(mac_address_layout);</div><div class='ctx'> </div><div class='ctx'> 	out = kvzalloc(out_sz, GFP_KERNEL);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c<br/>index 954ba0826c61..3d09fa54598f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c</a></div><div class='hunk'>@@ -130,9 +130,15 @@ static int mlxbf_gige_open(struct net_device *netdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxbf_gige *priv = netdev_priv(netdev);</div><div class='ctx'> 	struct phy_device *phydev = netdev-&gt;phydev;</div><div class='add'>+	u64 control;</div><div class='ctx'> 	u64 int_en;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='add'>+	/* Perform general init of GigE block */</div><div class='add'>+	control = readq(priv-&gt;base + MLXBF_GIGE_CONTROL);</div><div class='add'>+	control |= MLXBF_GIGE_CONTROL_PORT_EN;</div><div class='add'>+	writeq(control, priv-&gt;base + MLXBF_GIGE_CONTROL);</div><div class='add'>+</div><div class='ctx'> 	err = mlxbf_gige_request_irqs(priv);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='hunk'>@@ -147,14 +153,14 @@ static int mlxbf_gige_open(struct net_device *netdev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	priv-&gt;valid_polarity = 0;</div><div class='ctx'> </div><div class='del'>-	err = mlxbf_gige_rx_init(priv);</div><div class='add'>+	phy_start(phydev);</div><div class='add'>+</div><div class='add'>+	err = mlxbf_gige_tx_init(priv);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto free_irqs;</div><div class='del'>-	err = mlxbf_gige_tx_init(priv);</div><div class='add'>+	err = mlxbf_gige_rx_init(priv);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto rx_deinit;</div><div class='del'>-</div><div class='del'>-	phy_start(phydev);</div><div class='add'>+		goto tx_deinit;</div><div class='ctx'> </div><div class='ctx'> 	netif_napi_add(netdev, &amp;priv-&gt;napi, mlxbf_gige_poll);</div><div class='ctx'> 	napi_enable(&amp;priv-&gt;napi);</div><div class='hunk'>@@ -176,8 +182,8 @@ static int mlxbf_gige_open(struct net_device *netdev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-rx_deinit:</div><div class='del'>-	mlxbf_gige_rx_deinit(priv);</div><div class='add'>+tx_deinit:</div><div class='add'>+	mlxbf_gige_tx_deinit(priv);</div><div class='ctx'> </div><div class='ctx'> free_irqs:</div><div class='ctx'> 	mlxbf_gige_free_irqs(priv);</div><div class='hunk'>@@ -365,7 +371,6 @@ static int mlxbf_gige_probe(struct platform_device *pdev)</div><div class='ctx'> 	void __iomem *plu_base;</div><div class='ctx'> 	void __iomem *base;</div><div class='ctx'> 	int addr, phy_irq;</div><div class='del'>-	u64 control;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC);</div><div class='hunk'>@@ -380,11 +385,6 @@ static int mlxbf_gige_probe(struct platform_device *pdev)</div><div class='ctx'> 	if (IS_ERR(plu_base))</div><div class='ctx'> 		return PTR_ERR(plu_base);</div><div class='ctx'> </div><div class='del'>-	/* Perform general init of GigE block */</div><div class='del'>-	control = readq(base + MLXBF_GIGE_CONTROL);</div><div class='del'>-	control |= MLXBF_GIGE_CONTROL_PORT_EN;</div><div class='del'>-	writeq(control, base + MLXBF_GIGE_CONTROL);</div><div class='del'>-</div><div class='ctx'> 	netdev = devm_alloc_etherdev(&amp;pdev-&gt;dev, sizeof(*priv));</div><div class='ctx'> 	if (!netdev)</div><div class='ctx'> 		return -ENOMEM;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c<br/>index 0d5a41a2ae01..699984358493 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c</a></div><div class='hunk'>@@ -142,6 +142,9 @@ int mlxbf_gige_rx_init(struct mlxbf_gige *priv)</div><div class='ctx'> 	writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN,</div><div class='ctx'> 	       priv-&gt;base + MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS);</div><div class='ctx'> </div><div class='add'>+	writeq(ilog2(priv-&gt;rx_q_entries),</div><div class='add'>+	       priv-&gt;base + MLXBF_GIGE_RX_WQE_SIZE_LOG2);</div><div class='add'>+</div><div class='ctx'> 	/* Clear MLXBF_GIGE_INT_MASK 'receive pkt' bit to</div><div class='ctx'> 	 * indicate readiness to receive interrupts</div><div class='ctx'> 	 */</div><div class='hunk'>@@ -154,9 +157,6 @@ int mlxbf_gige_rx_init(struct mlxbf_gige *priv)</div><div class='ctx'> 	data |= MLXBF_GIGE_RX_DMA_EN;</div><div class='ctx'> 	writeq(data, priv-&gt;base + MLXBF_GIGE_RX_DMA);</div><div class='ctx'> </div><div class='del'>-	writeq(ilog2(priv-&gt;rx_q_entries),</div><div class='del'>-	       priv-&gt;base + MLXBF_GIGE_RX_WQE_SIZE_LOG2);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> free_wqe_and_skb:</div><div class='hunk'>@@ -267,6 +267,13 @@ static bool mlxbf_gige_rx_packet(struct mlxbf_gige *priv, int *rx_pkts)</div><div class='ctx'> 		priv-&gt;stats.rx_truncate_errors++;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Read receive consumer index before replenish so that this routine</div><div class='add'>+	 * returns accurate return value even if packet is received into</div><div class='add'>+	 * just-replenished buffer prior to exiting this routine.</div><div class='add'>+	 */</div><div class='add'>+	rx_ci = readq(priv-&gt;base + MLXBF_GIGE_RX_CQE_PACKET_CI);</div><div class='add'>+	rx_ci_rem = rx_ci % priv-&gt;rx_q_entries;</div><div class='add'>+</div><div class='ctx'> 	/* Let hardware know we've replenished one buffer */</div><div class='ctx'> 	rx_pi++;</div><div class='ctx'> </div><div class='hunk'>@@ -279,8 +286,6 @@ static bool mlxbf_gige_rx_packet(struct mlxbf_gige *priv, int *rx_pkts)</div><div class='ctx'> 	rx_pi_rem = rx_pi % priv-&gt;rx_q_entries;</div><div class='ctx'> 	if (rx_pi_rem == 0)</div><div class='ctx'> 		priv-&gt;valid_polarity ^= 1;</div><div class='del'>-	rx_ci = readq(priv-&gt;base + MLXBF_GIGE_RX_CQE_PACKET_CI);</div><div class='del'>-	rx_ci_rem = rx_ci % priv-&gt;rx_q_entries;</div><div class='ctx'> </div><div class='ctx'> 	if (skb)</div><div class='ctx'> 		netif_receive_skb(skb);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h<br/>index e827c78be114..e3271c845ee6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/cmd.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/cmd.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/cmd.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/cmd.h</a></div><div class='hunk'>@@ -282,6 +282,12 @@ MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(cmd_mbox, query_fw, lag_mode_support, 0x18, 1, 1);</div><div class='ctx'> </div><div class='add'>+/* cmd_mbox_query_fw_cff_support</div><div class='add'>+ * 0: CONFIG_PROFILE.flood_mode = 5 (CFF) is not supported by FW</div><div class='add'>+ * 1: CONFIG_PROFILE.flood_mode = 5 (CFF) is supported by FW</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(cmd_mbox, query_fw, cff_support, 0x18, 2, 1);</div><div class='add'>+</div><div class='ctx'> /* cmd_mbox_query_fw_clr_int_base_offset</div><div class='ctx'>  * Clear Interrupt register's offset from clr_int_bar register</div><div class='ctx'>  * in PCI address space.</div><div class='hunk'>@@ -779,6 +785,11 @@ enum mlxsw_cmd_mbox_config_profile_flood_mode {</div><div class='ctx'> 	 * used.</div><div class='ctx'> 	 */</div><div class='ctx'> 	MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED = 4,</div><div class='add'>+	/* CFF - Compressed FID Flood (CFF) mode.</div><div class='add'>+	 * Reserved when legacy bridge model is used.</div><div class='add'>+	 * Supported only by Spectrum-2+.</div><div class='add'>+	 */</div><div class='add'>+	MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CFF = 5,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* cmd_mbox_config_profile_flood_mode</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c<br/>index f23421f038f3..e4d7739bd7c8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/core.c</a></div><div class='hunk'>@@ -211,6 +211,13 @@ mlxsw_core_lag_mode(struct mlxsw_core *mlxsw_core)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(mlxsw_core_lag_mode);</div><div class='ctx'> </div><div class='add'>+enum mlxsw_cmd_mbox_config_profile_flood_mode</div><div class='add'>+mlxsw_core_flood_mode(struct mlxsw_core *mlxsw_core)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_core-&gt;bus-&gt;flood_mode(mlxsw_core-&gt;bus_priv);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(mlxsw_core_flood_mode);</div><div class='add'>+</div><div class='ctx'> void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core)</div><div class='ctx'> {</div><div class='ctx'> 	return mlxsw_core-&gt;driver_priv;</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h<br/>index 764d14bd5bc0..6d11225594dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/core.h</a></div><div class='hunk'>@@ -38,6 +38,8 @@ unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core);</div><div class='ctx'> int mlxsw_core_max_lag(struct mlxsw_core *mlxsw_core, u16 *p_max_lag);</div><div class='ctx'> enum mlxsw_cmd_mbox_config_profile_lag_mode</div><div class='ctx'> mlxsw_core_lag_mode(struct mlxsw_core *mlxsw_core);</div><div class='add'>+enum mlxsw_cmd_mbox_config_profile_flood_mode</div><div class='add'>+mlxsw_core_flood_mode(struct mlxsw_core *mlxsw_core);</div><div class='ctx'> </div><div class='ctx'> void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core);</div><div class='ctx'> </div><div class='hunk'>@@ -322,7 +324,12 @@ struct mlxsw_config_profile {</div><div class='ctx'> 	u16	max_regions;</div><div class='ctx'> 	u8	max_flood_tables;</div><div class='ctx'> 	u8	max_vid_flood_tables;</div><div class='add'>+</div><div class='add'>+	/* Flood mode to use if used_flood_mode. If flood_mode_prefer_cff,</div><div class='add'>+	 * the backup flood mode (if any) when CFF unsupported.</div><div class='add'>+	 */</div><div class='ctx'> 	u8	flood_mode;</div><div class='add'>+</div><div class='ctx'> 	u8	max_fid_offset_flood_tables;</div><div class='ctx'> 	u16	fid_offset_flood_table_size;</div><div class='ctx'> 	u8	max_fid_flood_tables;</div><div class='hunk'>@@ -338,6 +345,7 @@ struct mlxsw_config_profile {</div><div class='ctx'> 	u8	kvd_hash_double_parts;</div><div class='ctx'> 	u8	cqe_time_stamp_type;</div><div class='ctx'> 	bool	lag_mode_prefer_sw;</div><div class='add'>+	bool	flood_mode_prefer_cff;</div><div class='ctx'> 	struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -489,6 +497,7 @@ struct mlxsw_bus {</div><div class='ctx'> 	u32 (*read_utc_sec)(void *bus_priv);</div><div class='ctx'> 	u32 (*read_utc_nsec)(void *bus_priv);</div><div class='ctx'> 	enum mlxsw_cmd_mbox_config_profile_lag_mode (*lag_mode)(void *bus_priv);</div><div class='add'>+	enum mlxsw_cmd_mbox_config_profile_flood_mode (*flood_mode)(void *priv);</div><div class='ctx'> 	u8 features;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c<br/>index e4b25e187467..af99bf17eb36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/pci.c</a></div><div class='hunk'>@@ -106,7 +106,9 @@ struct mlxsw_pci {</div><div class='ctx'> 	u64 utc_sec_offset;</div><div class='ctx'> 	u64 utc_nsec_offset;</div><div class='ctx'> 	bool lag_mode_support;</div><div class='add'>+	bool cff_support;</div><div class='ctx'> 	enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode;</div><div class='add'>+	enum mlxsw_cmd_mbox_config_profile_flood_mode flood_mode;</div><div class='ctx'> 	struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];</div><div class='ctx'> 	u32 doorbell_offset;</div><div class='ctx'> 	struct mlxsw_core *core;</div><div class='hunk'>@@ -130,6 +132,7 @@ struct mlxsw_pci {</div><div class='ctx'> 	const struct pci_device_id *id;</div><div class='ctx'> 	enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */</div><div class='ctx'> 	u8 num_sdq_cqs; /* Number of CQs used for SDQs */</div><div class='add'>+	bool skip_reset;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)</div><div class='hunk'>@@ -1245,11 +1248,22 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,</div><div class='ctx'> 		mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(</div><div class='ctx'> 			mbox, profile-&gt;fid_flood_table_size);</div><div class='ctx'> 	}</div><div class='del'>-	if (profile-&gt;used_flood_mode) {</div><div class='add'>+	if (profile-&gt;flood_mode_prefer_cff &amp;&amp; mlxsw_pci-&gt;cff_support) {</div><div class='add'>+		enum mlxsw_cmd_mbox_config_profile_flood_mode flood_mode =</div><div class='add'>+			MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CFF;</div><div class='add'>+</div><div class='add'>+		mlxsw_cmd_mbox_config_profile_set_flood_mode_set(mbox, 1);</div><div class='add'>+		mlxsw_cmd_mbox_config_profile_flood_mode_set(mbox, flood_mode);</div><div class='add'>+		mlxsw_pci-&gt;flood_mode = flood_mode;</div><div class='add'>+	} else if (profile-&gt;used_flood_mode) {</div><div class='ctx'> 		mlxsw_cmd_mbox_config_profile_set_flood_mode_set(</div><div class='ctx'> 			mbox, 1);</div><div class='ctx'> 		mlxsw_cmd_mbox_config_profile_flood_mode_set(</div><div class='ctx'> 			mbox, profile-&gt;flood_mode);</div><div class='add'>+		mlxsw_pci-&gt;flood_mode = profile-&gt;flood_mode;</div><div class='add'>+	} else {</div><div class='add'>+		WARN_ON(1);</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> 	if (profile-&gt;used_max_ib_mc) {</div><div class='ctx'> 		mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(</div><div class='hunk'>@@ -1476,11 +1490,47 @@ static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci,</div><div class='ctx'> 	return -EBUSY;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,</div><div class='del'>-			      const struct pci_device_id *id)</div><div class='add'>+static int mlxsw_pci_reset_at_pci_disable(struct mlxsw_pci *mlxsw_pci)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev = mlxsw_pci-&gt;pdev;</div><div class='ctx'> 	char mrsr_pl[MLXSW_REG_MRSR_LEN];</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	mlxsw_reg_mrsr_pack(mrsr_pl,</div><div class='add'>+			    MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE);</div><div class='add'>+	err = mlxsw_reg_write(mlxsw_pci-&gt;core, MLXSW_REG(mrsr), mrsr_pl);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	device_lock_assert(&amp;pdev-&gt;dev);</div><div class='add'>+</div><div class='add'>+	pci_cfg_access_lock(pdev);</div><div class='add'>+	pci_save_state(pdev);</div><div class='add'>+</div><div class='add'>+	err = __pci_reset_function_locked(pdev);</div><div class='add'>+	if (err)</div><div class='add'>+		pci_err(pdev, "PCI function reset failed with %d\n", err);</div><div class='add'>+</div><div class='add'>+	pci_restore_state(pdev);</div><div class='add'>+	pci_cfg_access_unlock(pdev);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_pci_reset_sw(struct mlxsw_pci *mlxsw_pci)</div><div class='add'>+{</div><div class='add'>+	char mrsr_pl[MLXSW_REG_MRSR_LEN];</div><div class='add'>+</div><div class='add'>+	mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET);</div><div class='add'>+	return mlxsw_reg_write(mlxsw_pci-&gt;core, MLXSW_REG(mrsr), mrsr_pl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = mlxsw_pci-&gt;pdev;</div><div class='add'>+	char mcam_pl[MLXSW_REG_MCAM_LEN];</div><div class='add'>+	bool pci_reset_supported;</div><div class='ctx'> 	u32 sys_status;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='hunk'>@@ -1491,8 +1541,26 @@ static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,</div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	mlxsw_reg_mrsr_pack(mrsr_pl);</div><div class='del'>-	err = mlxsw_reg_write(mlxsw_pci-&gt;core, MLXSW_REG(mrsr), mrsr_pl);</div><div class='add'>+	/* PCI core already issued a PCI reset, do not issue another reset. */</div><div class='add'>+	if (mlxsw_pci-&gt;skip_reset)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	mlxsw_reg_mcam_pack(mcam_pl,</div><div class='add'>+			    MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES);</div><div class='add'>+	err = mlxsw_reg_query(mlxsw_pci-&gt;core, MLXSW_REG(mcam), mcam_pl);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET,</div><div class='add'>+			      &amp;pci_reset_supported);</div><div class='add'>+</div><div class='add'>+	if (pci_reset_supported) {</div><div class='add'>+		pci_dbg(pdev, "Starting PCI reset flow\n");</div><div class='add'>+		err = mlxsw_pci_reset_at_pci_disable(mlxsw_pci);</div><div class='add'>+	} else {</div><div class='add'>+		pci_dbg(pdev, "Starting software reset flow\n");</div><div class='add'>+		err = mlxsw_pci_reset_sw(mlxsw_pci);</div><div class='add'>+	}</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1537,9 +1605,9 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 	if (!mbox)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci-&gt;id);</div><div class='add'>+	err = mlxsw_pci_reset(mlxsw_pci, mlxsw_pci-&gt;id);</div><div class='ctx'> 	if (err)</div><div class='del'>-		goto err_sw_reset;</div><div class='add'>+		goto err_reset;</div><div class='ctx'> </div><div class='ctx'> 	err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);</div><div class='ctx'> 	if (err &lt; 0) {</div><div class='hunk'>@@ -1601,6 +1669,9 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,</div><div class='ctx'> </div><div class='ctx'> 	mlxsw_pci-&gt;lag_mode_support =</div><div class='ctx'> 		mlxsw_cmd_mbox_query_fw_lag_mode_support_get(mbox);</div><div class='add'>+	mlxsw_pci-&gt;cff_support =</div><div class='add'>+		mlxsw_cmd_mbox_query_fw_cff_support_get(mbox);</div><div class='add'>+</div><div class='ctx'> 	num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);</div><div class='ctx'> 	err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -1672,7 +1743,7 @@ err_iface_rev:</div><div class='ctx'> err_query_fw:</div><div class='ctx'> 	mlxsw_pci_free_irq_vectors(mlxsw_pci);</div><div class='ctx'> err_alloc_irq:</div><div class='del'>-err_sw_reset:</div><div class='add'>+err_reset:</div><div class='ctx'> mbox_put:</div><div class='ctx'> 	mlxsw_cmd_mbox_free(mbox);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -1917,6 +1988,14 @@ mlxsw_pci_lag_mode(void *bus_priv)</div><div class='ctx'> 	return mlxsw_pci-&gt;lag_mode;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum mlxsw_cmd_mbox_config_profile_flood_mode</div><div class='add'>+mlxsw_pci_flood_mode(void *bus_priv)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_pci *mlxsw_pci = bus_priv;</div><div class='add'>+</div><div class='add'>+	return mlxsw_pci-&gt;flood_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct mlxsw_bus mlxsw_pci_bus = {</div><div class='ctx'> 	.kind			= "pci",</div><div class='ctx'> 	.init			= mlxsw_pci_init,</div><div class='hunk'>@@ -1929,6 +2008,7 @@ static const struct mlxsw_bus mlxsw_pci_bus = {</div><div class='ctx'> 	.read_utc_sec		= mlxsw_pci_read_utc_sec,</div><div class='ctx'> 	.read_utc_nsec		= mlxsw_pci_read_utc_nsec,</div><div class='ctx'> 	.lag_mode		= mlxsw_pci_lag_mode,</div><div class='add'>+	.flood_mode		= mlxsw_pci_flood_mode,</div><div class='ctx'> 	.features		= MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -2059,11 +2139,34 @@ static void mlxsw_pci_remove(struct pci_dev *pdev)</div><div class='ctx'> 	kfree(mlxsw_pci);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void mlxsw_pci_reset_prepare(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	mlxsw_core_bus_device_unregister(mlxsw_pci-&gt;core, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlxsw_pci_reset_done(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	mlxsw_pci-&gt;skip_reset = true;</div><div class='add'>+	mlxsw_core_bus_device_register(&amp;mlxsw_pci-&gt;bus_info, &amp;mlxsw_pci_bus,</div><div class='add'>+				       mlxsw_pci, false, NULL, NULL);</div><div class='add'>+	mlxsw_pci-&gt;skip_reset = false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct pci_error_handlers mlxsw_pci_err_handler = {</div><div class='add'>+	.reset_prepare = mlxsw_pci_reset_prepare,</div><div class='add'>+	.reset_done = mlxsw_pci_reset_done,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> int mlxsw_pci_driver_register(struct pci_driver *pci_driver)</div><div class='ctx'> {</div><div class='ctx'> 	pci_driver-&gt;probe = mlxsw_pci_probe;</div><div class='ctx'> 	pci_driver-&gt;remove = mlxsw_pci_remove;</div><div class='ctx'> 	pci_driver-&gt;shutdown = mlxsw_pci_remove;</div><div class='add'>+	pci_driver-&gt;err_handler = &amp;mlxsw_pci_err_handler;</div><div class='ctx'> 	return pci_register_driver(pci_driver);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(mlxsw_pci_driver_register);</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h<br/>index 25b294fdeb3d..8892654c685f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/reg.h</a></div><div class='hunk'>@@ -1024,6 +1024,8 @@ static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,</div><div class='ctx'>  * ------------------------------------------</div><div class='ctx'>  * The following register controls the association of flooding tables and MIDs</div><div class='ctx'>  * to packet types used for flooding.</div><div class='add'>+ *</div><div class='add'>+ * Reserved when CONFIG_PROFILE.flood_mode = CFF.</div><div class='ctx'>  */</div><div class='ctx'> #define MLXSW_REG_SFGC_ID 0x2011</div><div class='ctx'> #define MLXSW_REG_SFGC_LEN 0x14</div><div class='hunk'>@@ -1862,6 +1864,7 @@ MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);</div><div class='ctx'>  * Access: RW</div><div class='ctx'>  *</div><div class='ctx'>  * Note: Reserved when legacy bridge model is used.</div><div class='add'>+ * Reserved when CONFIG_PROFILE.flood_mode = CFF.</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);</div><div class='ctx'> </div><div class='hunk'>@@ -1872,6 +1875,7 @@ MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);</div><div class='ctx'>  * Access: RW</div><div class='ctx'>  *</div><div class='ctx'>  * Note: Reserved when legacy bridge model is used and when flood_rsp=1.</div><div class='add'>+ * Reserved when CONFIG_PROFILE.flood_mode = CFF</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);</div><div class='ctx'> </div><div class='hunk'>@@ -1880,6 +1884,8 @@ MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);</div><div class='ctx'>  * Used to point into the flooding table selected by SFGC register if</div><div class='ctx'>  * the table is of type FID-Offset. Otherwise, this field is reserved.</div><div class='ctx'>  * Access: RW</div><div class='add'>+ *</div><div class='add'>+ * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);</div><div class='ctx'> </div><div class='hunk'>@@ -1938,6 +1944,35 @@ MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);</div><div class='ctx'> </div><div class='add'>+/* reg_sfmr_cff_mid_base</div><div class='add'>+ * Pointer to PGT table.</div><div class='add'>+ * Range: 0..(cap_max_pgt-1)</div><div class='add'>+ * Access: RW</div><div class='add'>+ *</div><div class='add'>+ * Note: Reserved when SwitchX/-2 and Spectrum-1.</div><div class='add'>+ * Supported when CONFIG_PROFILE.flood_mode = CFF.</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);</div><div class='add'>+</div><div class='add'>+/* reg_sfmr_nve_flood_prf_id</div><div class='add'>+ * FID flooding profile_id for NVE Encap</div><div class='add'>+ * Range 0..(max_cap_nve_flood_prf-1)</div><div class='add'>+ * Access: RW</div><div class='add'>+ *</div><div class='add'>+ * Note: Reserved when SwitchX/-2 and Spectrum-1</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2);</div><div class='add'>+</div><div class='add'>+/* reg_sfmr_cff_prf_id</div><div class='add'>+ * Compressed Fid Flooding profile_id</div><div class='add'>+ * Range 0..(max_cap_nve_flood_prf-1)</div><div class='add'>+ * Access: RW</div><div class='add'>+ *</div><div class='add'>+ * Note: Reserved when SwitchX/-2 and Spectrum-1</div><div class='add'>+ * Supported only when CONFIG_PROFLE.flood_mode = CFF.</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);</div><div class='add'>+</div><div class='ctx'> /* reg_sfmr_smpe_valid</div><div class='ctx'>  * SMPE is valid.</div><div class='ctx'>  * Access: RW</div><div class='hunk'>@@ -1959,18 +1994,11 @@ MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);</div><div class='ctx'> </div><div class='ctx'> static inline void mlxsw_reg_sfmr_pack(char *payload,</div><div class='ctx'> 				       enum mlxsw_reg_sfmr_op op, u16 fid,</div><div class='del'>-				       u16 fid_offset, bool flood_rsp,</div><div class='del'>-				       enum mlxsw_reg_bridge_type bridge_type,</div><div class='ctx'> 				       bool smpe_valid, u16 smpe)</div><div class='ctx'> {</div><div class='ctx'> 	MLXSW_REG_ZERO(sfmr, payload);</div><div class='ctx'> 	mlxsw_reg_sfmr_op_set(payload, op);</div><div class='ctx'> 	mlxsw_reg_sfmr_fid_set(payload, fid);</div><div class='del'>-	mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);</div><div class='del'>-	mlxsw_reg_sfmr_vtfp_set(payload, false);</div><div class='del'>-	mlxsw_reg_sfmr_vv_set(payload, false);</div><div class='del'>-	mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp);</div><div class='del'>-	mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type);</div><div class='ctx'> 	mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);</div><div class='ctx'> 	mlxsw_reg_sfmr_smpe_set(payload, smpe);</div><div class='ctx'> }</div><div class='hunk'>@@ -2168,6 +2196,50 @@ static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,</div><div class='ctx'> 	mlxsw_reg_spvc_et0_set(payload, et0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* SFFP - Switch FID Flooding Profiles Register</div><div class='add'>+ * --------------------------------------------</div><div class='add'>+ * The SFFP register populates the fid flooding profile tables used for the NVE</div><div class='add'>+ * flooding and Compressed-FID Flooding (CFF).</div><div class='add'>+ *</div><div class='add'>+ * Reserved on Spectrum-1.</div><div class='add'>+ */</div><div class='add'>+#define MLXSW_REG_SFFP_ID 0x2029</div><div class='add'>+#define MLXSW_REG_SFFP_LEN 0x0C</div><div class='add'>+</div><div class='add'>+MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN);</div><div class='add'>+</div><div class='add'>+/* reg_sffp_profile_id</div><div class='add'>+ * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id</div><div class='add'>+ * Range 0..max_cap_nve_flood_prf-1</div><div class='add'>+ * Access: Index</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);</div><div class='add'>+</div><div class='add'>+/* reg_sffp_type</div><div class='add'>+ * The traffic type to reach the flooding table.</div><div class='add'>+ * Same as SFGC.type</div><div class='add'>+ * Access: Index</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);</div><div class='add'>+</div><div class='add'>+/* reg_sffp_flood_offset</div><div class='add'>+ * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address</div><div class='add'>+ * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD</div><div class='add'>+ * pointer for NVE underlay.</div><div class='add'>+ * Access: RW</div><div class='add'>+ */</div><div class='add'>+MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);</div><div class='add'>+</div><div class='add'>+static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id,</div><div class='add'>+				       enum mlxsw_reg_sfgc_type type,</div><div class='add'>+				       u8 flood_offset)</div><div class='add'>+{</div><div class='add'>+	MLXSW_REG_ZERO(sffp, payload);</div><div class='add'>+	mlxsw_reg_sffp_profile_id_set(payload, profile_id);</div><div class='add'>+	mlxsw_reg_sffp_type_set(payload, type);</div><div class='add'>+	mlxsw_reg_sffp_flood_offset_set(payload, flood_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /* SPEVET - Switch Port Egress VLAN EtherType</div><div class='ctx'>  * ------------------------------------------</div><div class='ctx'>  * The switch port egress VLAN EtherType configures which EtherType to push at</div><div class='hunk'>@@ -10122,6 +10194,15 @@ mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,</div><div class='ctx'> </div><div class='ctx'> MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);</div><div class='ctx'> </div><div class='add'>+enum mlxsw_reg_mrsr_command {</div><div class='add'>+	/* Switch soft reset, does not reset PCI firmware. */</div><div class='add'>+	MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1,</div><div class='add'>+	/* Reset will be done when PCI link will be disabled.</div><div class='add'>+	 * This command will reset PCI firmware also.</div><div class='add'>+	 */</div><div class='add'>+	MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* reg_mrsr_command</div><div class='ctx'>  * Reset/shutdown command</div><div class='ctx'>  * 0 - do nothing</div><div class='hunk'>@@ -10130,10 +10211,11 @@ MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);</div><div class='ctx'>  */</div><div class='ctx'> MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);</div><div class='ctx'> </div><div class='del'>-static inline void mlxsw_reg_mrsr_pack(char *payload)</div><div class='add'>+static inline void mlxsw_reg_mrsr_pack(char *payload,</div><div class='add'>+				       enum mlxsw_reg_mrsr_command command)</div><div class='ctx'> {</div><div class='ctx'> 	MLXSW_REG_ZERO(mrsr, payload);</div><div class='del'>-	mlxsw_reg_mrsr_command_set(payload, 1);</div><div class='add'>+	mlxsw_reg_mrsr_command_set(payload, command);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* MLCR - Management LED Control Register</div><div class='hunk'>@@ -10584,6 +10666,8 @@ MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);</div><div class='ctx'> enum mlxsw_reg_mcam_mng_feature_cap_mask_bits {</div><div class='ctx'> 	/* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */</div><div class='ctx'> 	MLXSW_REG_MCAM_MCIA_128B = 34,</div><div class='add'>+	/* If set, MRSR.command=6 is supported. */</div><div class='add'>+	MLXSW_REG_MCAM_PCI_RESET = 48,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define MLXSW_REG_BYTES_PER_DWORD 0x4</div><div class='hunk'>@@ -12934,6 +13018,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {</div><div class='ctx'> 	MLXSW_REG(spvmlr),</div><div class='ctx'> 	MLXSW_REG(spfsr),</div><div class='ctx'> 	MLXSW_REG(spvc),</div><div class='add'>+	MLXSW_REG(sffp),</div><div class='ctx'> 	MLXSW_REG(spevet),</div><div class='ctx'> 	MLXSW_REG(smpe),</div><div class='ctx'> 	MLXSW_REG(smid2),</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/resources.h b/drivers/net/ethernet/mellanox/mlxsw/resources.h<br/>index 89dd2777ec4d..9d7977ebe186 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/resources.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/resources.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/resources.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/resources.h</a></div><div class='hunk'>@@ -27,6 +27,7 @@ enum mlxsw_res_id {</div><div class='ctx'> 	MLXSW_RES_ID_FID,</div><div class='ctx'> 	MLXSW_RES_ID_MAX_LAG,</div><div class='ctx'> 	MLXSW_RES_ID_MAX_LAG_MEMBERS,</div><div class='add'>+	MLXSW_RES_ID_MAX_NVE_FLOOD_PRF,</div><div class='ctx'> 	MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,</div><div class='ctx'> 	MLXSW_RES_ID_CELL_SIZE,</div><div class='ctx'> 	MLXSW_RES_ID_MAX_HEADROOM_SIZE,</div><div class='hunk'>@@ -88,6 +89,7 @@ static u16 mlxsw_res_ids[] = {</div><div class='ctx'> 	[MLXSW_RES_ID_FID] = 0x2512,</div><div class='ctx'> 	[MLXSW_RES_ID_MAX_LAG] = 0x2520,</div><div class='ctx'> 	[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,</div><div class='add'>+	[MLXSW_RES_ID_MAX_NVE_FLOOD_PRF] = 0x2522,</div><div class='ctx'> 	[MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805,	/* Bytes */</div><div class='ctx'> 	[MLXSW_RES_ID_CELL_SIZE] = 0x2803,	/* Bytes */</div><div class='ctx'> 	[MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811,	/* Bytes */</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c<br/>index cec72d99d9c9..5d3413636a62 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum.c</a></div><div class='hunk'>@@ -3190,10 +3190,10 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 		goto err_lag_init;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = mlxsw_sp_fids_init(mlxsw_sp);</div><div class='add'>+	err = mlxsw_sp-&gt;fid_core_ops-&gt;init(mlxsw_sp);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		dev_err(mlxsw_sp-&gt;bus_info-&gt;dev, "Failed to initialize FIDs\n");</div><div class='del'>-		goto err_fids_init;</div><div class='add'>+		goto err_fid_core_init;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = mlxsw_sp_policers_init(mlxsw_sp);</div><div class='hunk'>@@ -3379,8 +3379,8 @@ err_devlink_traps_init:</div><div class='ctx'> err_traps_init:</div><div class='ctx'> 	mlxsw_sp_policers_fini(mlxsw_sp);</div><div class='ctx'> err_policers_init:</div><div class='del'>-	mlxsw_sp_fids_fini(mlxsw_sp);</div><div class='del'>-err_fids_init:</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops-&gt;fini(mlxsw_sp);</div><div class='add'>+err_fid_core_init:</div><div class='ctx'> 	mlxsw_sp_lag_fini(mlxsw_sp);</div><div class='ctx'> err_lag_init:</div><div class='ctx'> 	mlxsw_sp_pgt_fini(mlxsw_sp);</div><div class='hunk'>@@ -3416,7 +3416,7 @@ static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 	mlxsw_sp-&gt;router_ops = &amp;mlxsw_sp1_router_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners = mlxsw_sp1_listener;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);</div><div class='del'>-	mlxsw_sp-&gt;fid_family_arr = mlxsw_sp1_fid_family_arr;</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops = &amp;mlxsw_sp1_fid_core_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;</div><div class='ctx'> 	mlxsw_sp-&gt;pgt_smpe_index_valid = true;</div><div class='ctx'> </div><div class='hunk'>@@ -3450,7 +3450,7 @@ static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 	mlxsw_sp-&gt;router_ops = &amp;mlxsw_sp2_router_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners = mlxsw_sp2_listener;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);</div><div class='del'>-	mlxsw_sp-&gt;fid_family_arr = mlxsw_sp2_fid_family_arr;</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops = &amp;mlxsw_sp2_fid_core_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;</div><div class='ctx'> 	mlxsw_sp-&gt;pgt_smpe_index_valid = false;</div><div class='ctx'> </div><div class='hunk'>@@ -3484,7 +3484,7 @@ static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 	mlxsw_sp-&gt;router_ops = &amp;mlxsw_sp2_router_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners = mlxsw_sp2_listener;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);</div><div class='del'>-	mlxsw_sp-&gt;fid_family_arr = mlxsw_sp2_fid_family_arr;</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops = &amp;mlxsw_sp2_fid_core_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;</div><div class='ctx'> 	mlxsw_sp-&gt;pgt_smpe_index_valid = false;</div><div class='ctx'> </div><div class='hunk'>@@ -3518,7 +3518,7 @@ static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core,</div><div class='ctx'> 	mlxsw_sp-&gt;router_ops = &amp;mlxsw_sp2_router_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners = mlxsw_sp2_listener;</div><div class='ctx'> 	mlxsw_sp-&gt;listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);</div><div class='del'>-	mlxsw_sp-&gt;fid_family_arr = mlxsw_sp2_fid_family_arr;</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops = &amp;mlxsw_sp2_fid_core_ops;</div><div class='ctx'> 	mlxsw_sp-&gt;lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;</div><div class='ctx'> 	mlxsw_sp-&gt;pgt_smpe_index_valid = false;</div><div class='ctx'> </div><div class='hunk'>@@ -3552,7 +3552,7 @@ static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)</div><div class='ctx'> 	mlxsw_sp_devlink_traps_fini(mlxsw_sp);</div><div class='ctx'> 	mlxsw_sp_traps_fini(mlxsw_sp);</div><div class='ctx'> 	mlxsw_sp_policers_fini(mlxsw_sp);</div><div class='del'>-	mlxsw_sp_fids_fini(mlxsw_sp);</div><div class='add'>+	mlxsw_sp-&gt;fid_core_ops-&gt;fini(mlxsw_sp);</div><div class='ctx'> 	mlxsw_sp_lag_fini(mlxsw_sp);</div><div class='ctx'> 	mlxsw_sp_pgt_fini(mlxsw_sp);</div><div class='ctx'> 	mlxsw_sp_kvdl_fini(mlxsw_sp);</div><div class='hunk'>@@ -3598,6 +3598,7 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {</div><div class='ctx'> 	.used_cqe_time_stamp_type	= 1,</div><div class='ctx'> 	.cqe_time_stamp_type		= MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,</div><div class='ctx'> 	.lag_mode_prefer_sw		= true,</div><div class='add'>+	.flood_mode_prefer_cff		= true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs</div><div class='hunk'>@@ -3626,6 +3627,7 @@ static const struct mlxsw_config_profile mlxsw_sp4_config_profile = {</div><div class='ctx'> 	.used_cqe_time_stamp_type	= 1,</div><div class='ctx'> 	.cqe_time_stamp_type		= MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,</div><div class='ctx'> 	.lag_mode_prefer_sw		= true,</div><div class='add'>+	.flood_mode_prefer_cff		= true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -4515,6 +4517,10 @@ static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,</div><div class='ctx'> 	mlxsw_sp_port-&gt;lagged = 1;</div><div class='ctx'> 	lag-&gt;ref_count++;</div><div class='ctx'> </div><div class='add'>+	err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_fid_port_join_lag;</div><div class='add'>+</div><div class='ctx'> 	/* Port is no longer usable as a router interface */</div><div class='ctx'> 	if (mlxsw_sp_port-&gt;default_vlan-&gt;fid)</div><div class='ctx'> 		mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port-&gt;default_vlan);</div><div class='hunk'>@@ -4534,6 +4540,8 @@ static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,</div><div class='ctx'> err_replay:</div><div class='ctx'> 	mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev);</div><div class='ctx'> err_router_join:</div><div class='add'>+	mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);</div><div class='add'>+err_fid_port_join_lag:</div><div class='ctx'> 	lag-&gt;ref_count--;</div><div class='ctx'> 	mlxsw_sp_port-&gt;lagged = 0;</div><div class='ctx'> 	mlxsw_core_lag_mapping_clear(mlxsw_sp-&gt;core, lag_id,</div><div class='hunk'>@@ -4569,6 +4577,8 @@ static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,</div><div class='ctx'> 	 */</div><div class='ctx'> 	mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);</div><div class='ctx'> </div><div class='add'>+	mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);</div><div class='add'>+</div><div class='ctx'> 	if (lag-&gt;ref_count == 1)</div><div class='ctx'> 		mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h<br/>index c70333b460ea..a0c9775fa955 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum.h</a></div><div class='hunk'>@@ -205,7 +205,7 @@ struct mlxsw_sp {</div><div class='ctx'> 	const struct mlxsw_sp_mall_ops *mall_ops;</div><div class='ctx'> 	const struct mlxsw_sp_router_ops *router_ops;</div><div class='ctx'> 	const struct mlxsw_listener *listeners;</div><div class='del'>-	const struct mlxsw_sp_fid_family **fid_family_arr;</div><div class='add'>+	const struct mlxsw_sp_fid_core_ops *fid_core_ops;</div><div class='ctx'> 	size_t listeners_count;</div><div class='ctx'> 	u32 lowest_shaper_bs;</div><div class='ctx'> 	struct rhashtable ipv6_addr_ht;</div><div class='hunk'>@@ -252,6 +252,11 @@ struct mlxsw_sp_ptp_ops {</div><div class='ctx'> 			       const struct mlxsw_tx_info *tx_info);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mlxsw_sp_fid_core_ops {</div><div class='add'>+	int (*init)(struct mlxsw_sp *mlxsw_sp);</div><div class='add'>+	void (*fini)(struct mlxsw_sp *mlxsw_sp);</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static inline struct mlxsw_sp_upper *</div><div class='ctx'> mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)</div><div class='ctx'> {</div><div class='hunk'>@@ -508,6 +513,10 @@ enum mlxsw_sp_flood_type {</div><div class='ctx'> 	MLXSW_SP_FLOOD_TYPE_UC,</div><div class='ctx'> 	MLXSW_SP_FLOOD_TYPE_BC,</div><div class='ctx'> 	MLXSW_SP_FLOOD_TYPE_MC,</div><div class='add'>+	/* For RSP FIDs in CFF mode. */</div><div class='add'>+	MLXSW_SP_FLOOD_TYPE_NOT_UC,</div><div class='add'>+	/* For NVE traffic. */</div><div class='add'>+	MLXSW_SP_FLOOD_TYPE_ANY,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,</div><div class='hunk'>@@ -753,6 +762,8 @@ union mlxsw_sp_l3addr {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> u16 mlxsw_sp_rif_index(const struct mlxsw_sp_rif *rif);</div><div class='add'>+int mlxsw_sp_rif_subport_port(const struct mlxsw_sp_rif *rif,</div><div class='add'>+			      u16 *port, bool *is_lag);</div><div class='ctx'> int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 			 struct netlink_ext_ack *extack);</div><div class='ctx'> void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);</div><div class='hunk'>@@ -1319,11 +1330,11 @@ struct mlxsw_sp_fid *mlxsw_sp_fid_dummy_get(struct mlxsw_sp *mlxsw_sp);</div><div class='ctx'> void mlxsw_sp_fid_put(struct mlxsw_sp_fid *fid);</div><div class='ctx'> int mlxsw_sp_port_fids_init(struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='ctx'> void mlxsw_sp_port_fids_fini(struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='del'>-int mlxsw_sp_fids_init(struct mlxsw_sp *mlxsw_sp);</div><div class='del'>-void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp);</div><div class='add'>+int mlxsw_sp_fid_port_join_lag(const struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='add'>+void mlxsw_sp_fid_port_leave_lag(const struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='ctx'> </div><div class='del'>-extern const struct mlxsw_sp_fid_family *mlxsw_sp1_fid_family_arr[];</div><div class='del'>-extern const struct mlxsw_sp_fid_family *mlxsw_sp2_fid_family_arr[];</div><div class='add'>+extern const struct mlxsw_sp_fid_core_ops mlxsw_sp1_fid_core_ops;</div><div class='add'>+extern const struct mlxsw_sp_fid_core_ops mlxsw_sp2_fid_core_ops;</div><div class='ctx'> </div><div class='ctx'> /* spectrum_mr.c */</div><div class='ctx'> enum mlxsw_sp_mr_route_prio {</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c<br/>index 4c98950380d5..d231f4d2888b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c</a></div><div class='hunk'>@@ -301,6 +301,7 @@ mlxsw_sp_acl_erp_table_alloc(struct mlxsw_sp_acl_erp_core *erp_core,</div><div class='ctx'> 			     unsigned long *p_index)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int num_rows, entry_size;</div><div class='add'>+	unsigned long index;</div><div class='ctx'> </div><div class='ctx'> 	/* We only allow allocations of entire rows */</div><div class='ctx'> 	if (num_erps % erp_core-&gt;num_erp_banks != 0)</div><div class='hunk'>@@ -309,10 +310,11 @@ mlxsw_sp_acl_erp_table_alloc(struct mlxsw_sp_acl_erp_core *erp_core,</div><div class='ctx'> 	entry_size = erp_core-&gt;erpt_entries_size[region_type];</div><div class='ctx'> 	num_rows = num_erps / erp_core-&gt;num_erp_banks;</div><div class='ctx'> </div><div class='del'>-	*p_index = gen_pool_alloc(erp_core-&gt;erp_tables, num_rows * entry_size);</div><div class='del'>-	if (*p_index == 0)</div><div class='add'>+	index = gen_pool_alloc(erp_core-&gt;erp_tables, num_rows * entry_size);</div><div class='add'>+	if (!index)</div><div class='ctx'> 		return -ENOBUFS;</div><div class='del'>-	*p_index -= MLXSW_SP_ACL_ERP_GENALLOC_OFFSET;</div><div class='add'>+</div><div class='add'>+	*p_index = index - MLXSW_SP_ACL_ERP_GENALLOC_OFFSET;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c<br/>index d50786b0a6ce..50ea1eff02b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.c</a></div><div class='hunk'>@@ -681,13 +681,13 @@ static void</div><div class='ctx'> mlxsw_sp_acl_tcam_region_destroy(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 				 struct mlxsw_sp_acl_tcam_region *region)</div><div class='ctx'> {</div><div class='add'>+	struct mlxsw_sp_acl_tcam *tcam = mlxsw_sp_acl_to_tcam(mlxsw_sp-&gt;acl);</div><div class='ctx'> 	const struct mlxsw_sp_acl_tcam_ops *ops = mlxsw_sp-&gt;acl_tcam_ops;</div><div class='ctx'> </div><div class='ctx'> 	ops-&gt;region_fini(mlxsw_sp, region-&gt;priv);</div><div class='ctx'> 	mlxsw_sp_acl_tcam_region_disable(mlxsw_sp, region);</div><div class='ctx'> 	mlxsw_sp_acl_tcam_region_free(mlxsw_sp, region);</div><div class='del'>-	mlxsw_sp_acl_tcam_region_id_put(region-&gt;group-&gt;tcam,</div><div class='del'>-					region-&gt;id);</div><div class='add'>+	mlxsw_sp_acl_tcam_region_id_put(tcam, region-&gt;id);</div><div class='ctx'> 	kfree(region);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1564,6 +1564,8 @@ int mlxsw_sp_acl_tcam_init(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	tcam-&gt;max_groups = max_groups;</div><div class='ctx'> 	tcam-&gt;max_group_size = MLXSW_CORE_RES_GET(mlxsw_sp-&gt;core,</div><div class='ctx'> 						  ACL_MAX_GROUP_SIZE);</div><div class='add'>+	tcam-&gt;max_group_size = min_t(unsigned int, tcam-&gt;max_group_size,</div><div class='add'>+				     MLXSW_REG_PAGT_ACL_MAX_NUM);</div><div class='ctx'> </div><div class='ctx'> 	err = ops-&gt;init(mlxsw_sp, tcam-&gt;priv, tcam);</div><div class='ctx'> 	if (err)</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c<br/>index e954b8cd2ee8..65562ab208b3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include &lt;linux/refcount.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "spectrum.h"</div><div class='add'>+#include "spectrum_router.h"</div><div class='ctx'> #include "reg.h"</div><div class='ctx'> </div><div class='ctx'> struct mlxsw_sp_fid_family;</div><div class='hunk'>@@ -71,12 +72,12 @@ static const struct rhashtable_params mlxsw_sp_fid_vni_ht_params = {</div><div class='ctx'> </div><div class='ctx'> struct mlxsw_sp_flood_table {</div><div class='ctx'> 	enum mlxsw_sp_flood_type packet_type;</div><div class='del'>-	enum mlxsw_flood_table_type table_type;</div><div class='add'>+	enum mlxsw_flood_table_type table_type;	/* For flood_mode!=CFF. */</div><div class='ctx'> 	int table_index;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlxsw_sp_fid_ops {</div><div class='del'>-	void (*setup)(struct mlxsw_sp_fid *fid, const void *arg);</div><div class='add'>+	int (*setup)(struct mlxsw_sp_fid *fid, const void *arg);</div><div class='ctx'> 	int (*configure)(struct mlxsw_sp_fid *fid);</div><div class='ctx'> 	void (*deconfigure)(struct mlxsw_sp_fid *fid);</div><div class='ctx'> 	int (*index_alloc)(struct mlxsw_sp_fid *fid, const void *arg,</div><div class='hunk'>@@ -95,6 +96,34 @@ struct mlxsw_sp_fid_ops {</div><div class='ctx'> 				  const struct net_device *nve_dev);</div><div class='ctx'> 	int (*vid_to_fid_rif_update)(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> 				     const struct mlxsw_sp_rif *rif);</div><div class='add'>+	int (*flood_table_init)(struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				const struct mlxsw_sp_flood_table *flood_table);</div><div class='add'>+	int (*pgt_size)(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			u16 *p_pgt_size);</div><div class='add'>+	u16 (*fid_mid)(const struct mlxsw_sp_fid *fid,</div><div class='add'>+		       const struct mlxsw_sp_flood_table *flood_table);</div><div class='add'>+	void (*fid_pack)(char *sfmr_pl, const struct mlxsw_sp_fid *fid,</div><div class='add'>+			 enum mlxsw_reg_sfmr_op op);</div><div class='add'>+</div><div class='add'>+	/* These are specific to RFID families and we assume are only</div><div class='add'>+	 * implemented by RFID families, if at all.</div><div class='add'>+	 */</div><div class='add'>+	int (*fid_port_init)(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			     const struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='add'>+	void (*fid_port_fini)(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			      const struct mlxsw_sp_port *mlxsw_sp_port);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum mlxsw_sp_fid_flood_profile_id {</div><div class='add'>+	MLXSW_SP_FID_FLOOD_PROFILE_ID_BRIDGE = 1,</div><div class='add'>+	MLXSW_SP_FID_FLOOD_PROFILE_ID_RSP,</div><div class='add'>+	MLXSW_SP_FID_FLOOD_PROFILE_ID_NVE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct mlxsw_sp_fid_flood_profile {</div><div class='add'>+	const struct mlxsw_sp_flood_table *flood_tables;</div><div class='add'>+	int nr_flood_tables;</div><div class='add'>+	const enum mlxsw_sp_fid_flood_profile_id profile_id; /* For CFF mode. */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlxsw_sp_fid_family {</div><div class='hunk'>@@ -104,12 +133,11 @@ struct mlxsw_sp_fid_family {</div><div class='ctx'> 	u16 end_index;</div><div class='ctx'> 	struct list_head fids_list;</div><div class='ctx'> 	unsigned long *fids_bitmap;</div><div class='del'>-	const struct mlxsw_sp_flood_table *flood_tables;</div><div class='del'>-	int nr_flood_tables;</div><div class='add'>+	const struct mlxsw_sp_fid_flood_profile *flood_profile;</div><div class='ctx'> 	enum mlxsw_sp_rif_type rif_type;</div><div class='ctx'> 	const struct mlxsw_sp_fid_ops *ops;</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp;</div><div class='del'>-	bool flood_rsp;</div><div class='add'>+	bool flood_rsp;	/* For flood_mode!=CFF. */</div><div class='ctx'> 	enum mlxsw_reg_bridge_type bridge_type;</div><div class='ctx'> 	u16 pgt_base;</div><div class='ctx'> 	bool smpe_index_valid;</div><div class='hunk'>@@ -131,10 +159,31 @@ static const int mlxsw_sp_sfgc_mc_packet_types[MLXSW_REG_SFGC_TYPE_MAX] = {</div><div class='ctx'> 	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4]	= 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const int mlxsw_sp_sfgc_not_uc_packet_types[MLXSW_REG_SFGC_TYPE_MAX] = {</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_BROADCAST]				= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP]	= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL]			= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST]			= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6]	= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4]	= 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const int mlxsw_sp_sfgc_any_packet_types[MLXSW_REG_SFGC_TYPE_MAX] = {</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST]			= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_BROADCAST]				= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP]	= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL]			= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST]			= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6]	= 1,</div><div class='add'>+	[MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4]	= 1,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const int *mlxsw_sp_packet_type_sfgc_types[] = {</div><div class='ctx'> 	[MLXSW_SP_FLOOD_TYPE_UC]	= mlxsw_sp_sfgc_uc_packet_types,</div><div class='ctx'> 	[MLXSW_SP_FLOOD_TYPE_BC]	= mlxsw_sp_sfgc_bc_packet_types,</div><div class='ctx'> 	[MLXSW_SP_FLOOD_TYPE_MC]	= mlxsw_sp_sfgc_mc_packet_types,</div><div class='add'>+	[MLXSW_SP_FLOOD_TYPE_NOT_UC]	= mlxsw_sp_sfgc_not_uc_packet_types,</div><div class='add'>+	[MLXSW_SP_FLOOD_TYPE_ANY]	= mlxsw_sp_sfgc_any_packet_types,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct mlxsw_sp_fid *mlxsw_sp_fid_lookup_by_index(struct mlxsw_sp *mlxsw_sp,</div><div class='hunk'>@@ -305,10 +354,13 @@ mlxsw_sp_fid_flood_table_lookup(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> 	struct mlxsw_sp_fid_family *fid_family = fid-&gt;fid_family;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; fid_family-&gt;nr_flood_tables; i++) {</div><div class='del'>-		if (fid_family-&gt;flood_tables[i].packet_type != packet_type)</div><div class='add'>+	for (i = 0; i &lt; fid_family-&gt;flood_profile-&gt;nr_flood_tables; i++) {</div><div class='add'>+		const struct mlxsw_sp_flood_table *flood_table;</div><div class='add'>+</div><div class='add'>+		flood_table = &amp;fid_family-&gt;flood_profile-&gt;flood_tables[i];</div><div class='add'>+		if (flood_table-&gt;packet_type != packet_type)</div><div class='ctx'> 			continue;</div><div class='del'>-		return &amp;fid_family-&gt;flood_tables[i];</div><div class='add'>+		return flood_table;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return NULL;</div><div class='hunk'>@@ -320,24 +372,62 @@ mlxsw_sp_fid_family_num_fids(const struct mlxsw_sp_fid_family *fid_family)</div><div class='ctx'> 	return fid_family-&gt;end_index - fid_family-&gt;start_index + 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u16</div><div class='del'>-mlxsw_sp_fid_family_pgt_size(const struct mlxsw_sp_fid_family *fid_family)</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_8021d_pgt_size(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			    u16 *p_pgt_size)</div><div class='ctx'> {</div><div class='ctx'> 	u16 num_fids = mlxsw_sp_fid_family_num_fids(fid_family);</div><div class='ctx'> </div><div class='del'>-	return num_fids * fid_family-&gt;nr_flood_tables;</div><div class='add'>+	*p_pgt_size = num_fids * fid_family-&gt;flood_profile-&gt;nr_flood_tables;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static unsigned int mlxsw_sp_fid_rfid_port_offset_cff(unsigned int local_port)</div><div class='add'>+{</div><div class='add'>+	/* Port 0 is the CPU port. Since we never create RIFs based off that</div><div class='add'>+	 * port, we don't need to count it.</div><div class='add'>+	 */</div><div class='add'>+	return WARN_ON_ONCE(!local_port) ? 0 : local_port - 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_rfid_pgt_size_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			       u16 *p_pgt_size)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_core *core = fid_family-&gt;mlxsw_sp-&gt;core;</div><div class='add'>+	unsigned int max_ports;</div><div class='add'>+	u16 pgt_size;</div><div class='add'>+	u16 max_lags;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	max_ports = mlxsw_core_max_ports(core);</div><div class='add'>+</div><div class='add'>+	err = mlxsw_core_max_lag(core, &amp;max_lags);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	pgt_size = (mlxsw_sp_fid_rfid_port_offset_cff(max_ports) + max_lags) *</div><div class='add'>+		   fid_family-&gt;flood_profile-&gt;nr_flood_tables;</div><div class='add'>+	*p_pgt_size = pgt_size;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u16</div><div class='del'>-mlxsw_sp_fid_flood_table_mid(const struct mlxsw_sp_fid_family *fid_family,</div><div class='del'>-			     const struct mlxsw_sp_flood_table *flood_table,</div><div class='del'>-			     u16 fid_offset)</div><div class='add'>+mlxsw_sp_fid_pgt_base_ctl(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			  const struct mlxsw_sp_flood_table *flood_table)</div><div class='ctx'> {</div><div class='ctx'> 	u16 num_fids;</div><div class='ctx'> </div><div class='ctx'> 	num_fids = mlxsw_sp_fid_family_num_fids(fid_family);</div><div class='del'>-	return fid_family-&gt;pgt_base + num_fids * flood_table-&gt;table_index +</div><div class='del'>-	       fid_offset;</div><div class='add'>+	return fid_family-&gt;pgt_base + num_fids * flood_table-&gt;table_index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16</div><div class='add'>+mlxsw_sp_fid_fid_mid_ctl(const struct mlxsw_sp_fid *fid,</div><div class='add'>+			 const struct mlxsw_sp_flood_table *flood_table)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fid_pgt_base_ctl(fid-&gt;fid_family, flood_table) +</div><div class='add'>+	       fid-&gt;fid_offset;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mlxsw_sp_fid_flood_set(struct mlxsw_sp_fid *fid,</div><div class='hunk'>@@ -348,15 +438,14 @@ int mlxsw_sp_fid_flood_set(struct mlxsw_sp_fid *fid,</div><div class='ctx'> 	const struct mlxsw_sp_flood_table *flood_table;</div><div class='ctx'> 	u16 mid_index;</div><div class='ctx'> </div><div class='del'>-	if (WARN_ON(!fid_family-&gt;flood_tables))</div><div class='add'>+	if (WARN_ON(!fid_family-&gt;flood_profile))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	flood_table = mlxsw_sp_fid_flood_table_lookup(fid, packet_type);</div><div class='ctx'> 	if (!flood_table)</div><div class='ctx'> 		return -ESRCH;</div><div class='ctx'> </div><div class='del'>-	mid_index = mlxsw_sp_fid_flood_table_mid(fid_family, flood_table,</div><div class='del'>-						 fid-&gt;fid_offset);</div><div class='add'>+	mid_index = fid_family-&gt;ops-&gt;fid_mid(fid, flood_table);</div><div class='ctx'> 	return mlxsw_sp_pgt_entry_port_set(fid_family-&gt;mlxsw_sp, mid_index,</div><div class='ctx'> 					   fid-&gt;fid_index, local_port, member);</div><div class='ctx'> }</div><div class='hunk'>@@ -410,12 +499,13 @@ u16 mlxsw_sp_fid_8021q_vid(const struct mlxsw_sp_fid *fid)</div><div class='ctx'> 	return mlxsw_sp_fid_8021q_fid(fid)-&gt;vid;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mlxsw_sp_fid_8021q_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='add'>+static int mlxsw_sp_fid_8021q_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	u16 vid = *(u16 *) arg;</div><div class='ctx'> </div><div class='ctx'> 	mlxsw_sp_fid_8021q_fid(fid)-&gt;vid = vid;</div><div class='ctx'> 	fid-&gt;fid_offset = fid-&gt;fid_index - fid-&gt;fid_family-&gt;start_index;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static enum mlxsw_reg_sfmr_op mlxsw_sp_sfmr_op(bool valid)</div><div class='hunk'>@@ -424,18 +514,76 @@ static enum mlxsw_reg_sfmr_op mlxsw_sp_sfmr_op(bool valid)</div><div class='ctx'> 		       MLXSW_REG_SFMR_OP_DESTROY_FID;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mlxsw_sp_fid_op(const struct mlxsw_sp_fid *fid, bool valid)</div><div class='add'>+static void mlxsw_sp_fid_pack(char *sfmr_pl,</div><div class='add'>+			      const struct mlxsw_sp_fid *fid,</div><div class='add'>+			      enum mlxsw_reg_sfmr_op op)</div><div class='ctx'> {</div><div class='del'>-	struct mlxsw_sp *mlxsw_sp = fid-&gt;fid_family-&gt;mlxsw_sp;</div><div class='del'>-	char sfmr_pl[MLXSW_REG_SFMR_LEN];</div><div class='ctx'> 	u16 smpe;</div><div class='ctx'> </div><div class='ctx'> 	smpe = fid-&gt;fid_family-&gt;smpe_index_valid ? fid-&gt;fid_index : 0;</div><div class='ctx'> </div><div class='del'>-	mlxsw_reg_sfmr_pack(sfmr_pl, mlxsw_sp_sfmr_op(valid), fid-&gt;fid_index,</div><div class='del'>-			    fid-&gt;fid_offset, fid-&gt;fid_family-&gt;flood_rsp,</div><div class='del'>-			    fid-&gt;fid_family-&gt;bridge_type,</div><div class='add'>+	mlxsw_reg_sfmr_pack(sfmr_pl, op, fid-&gt;fid_index,</div><div class='ctx'> 			    fid-&gt;fid_family-&gt;smpe_index_valid, smpe);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlxsw_sp_fid_pack_ctl(char *sfmr_pl,</div><div class='add'>+				  const struct mlxsw_sp_fid *fid,</div><div class='add'>+				  enum mlxsw_reg_sfmr_op op)</div><div class='add'>+{</div><div class='add'>+	mlxsw_sp_fid_pack(sfmr_pl, fid, op);</div><div class='add'>+	mlxsw_reg_sfmr_fid_offset_set(sfmr_pl, fid-&gt;fid_offset);</div><div class='add'>+	mlxsw_reg_sfmr_flood_rsp_set(sfmr_pl, fid-&gt;fid_family-&gt;flood_rsp);</div><div class='add'>+	mlxsw_reg_sfmr_flood_bridge_type_set(sfmr_pl,</div><div class='add'>+					     fid-&gt;fid_family-&gt;bridge_type);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16</div><div class='add'>+mlxsw_sp_fid_off_pgt_base_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+			      u16 fid_offset)</div><div class='add'>+{</div><div class='add'>+	return fid_family-&gt;pgt_base +</div><div class='add'>+		fid_offset * fid_family-&gt;flood_profile-&gt;nr_flood_tables;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16 mlxsw_sp_fid_pgt_base_cff(const struct mlxsw_sp_fid *fid)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fid_off_pgt_base_cff(fid-&gt;fid_family, fid-&gt;fid_offset);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlxsw_sp_fid_fid_pack_cff(char *sfmr_pl,</div><div class='add'>+				      const struct mlxsw_sp_fid *fid,</div><div class='add'>+				      enum mlxsw_reg_sfmr_op op)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_sp_fid_family *fid_family = fid-&gt;fid_family;</div><div class='add'>+	u16 pgt_base = mlxsw_sp_fid_pgt_base_cff(fid);</div><div class='add'>+</div><div class='add'>+	mlxsw_sp_fid_pack(sfmr_pl, fid, op);</div><div class='add'>+	mlxsw_reg_sfmr_cff_mid_base_set(sfmr_pl, pgt_base);</div><div class='add'>+	mlxsw_reg_sfmr_cff_prf_id_set(sfmr_pl,</div><div class='add'>+				      fid_family-&gt;flood_profile-&gt;profile_id);</div><div class='add'>+	mlxsw_reg_sfmr_nve_flood_prf_id_set(sfmr_pl,</div><div class='add'>+					    MLXSW_SP_FID_FLOOD_PROFILE_ID_NVE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16 mlxsw_sp_fid_rfid_fid_offset_cff(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+					    u16 port_lag_id, bool is_lag)</div><div class='add'>+{</div><div class='add'>+	u16 max_ports = mlxsw_core_max_ports(mlxsw_sp-&gt;core);</div><div class='add'>+</div><div class='add'>+	if (is_lag)</div><div class='add'>+		return mlxsw_sp_fid_rfid_port_offset_cff(max_ports) +</div><div class='add'>+		       port_lag_id;</div><div class='add'>+	else</div><div class='add'>+		return mlxsw_sp_fid_rfid_port_offset_cff(port_lag_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp_fid_op(const struct mlxsw_sp_fid *fid, bool valid)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = fid-&gt;fid_family-&gt;mlxsw_sp;</div><div class='add'>+	char sfmr_pl[MLXSW_REG_SFMR_LEN];</div><div class='add'>+</div><div class='add'>+	fid-&gt;fid_family-&gt;ops-&gt;fid_pack(sfmr_pl, fid,</div><div class='add'>+				       mlxsw_sp_sfmr_op(valid));</div><div class='ctx'> 	return mlxsw_reg_write(mlxsw_sp-&gt;core, MLXSW_REG(sfmr), sfmr_pl);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -444,15 +592,10 @@ static int mlxsw_sp_fid_edit_op(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp = fid-&gt;fid_family-&gt;mlxsw_sp;</div><div class='ctx'> 	char sfmr_pl[MLXSW_REG_SFMR_LEN];</div><div class='del'>-	u16 smpe;</div><div class='ctx'> </div><div class='del'>-	smpe = fid-&gt;fid_family-&gt;smpe_index_valid ? fid-&gt;fid_index : 0;</div><div class='add'>+	fid-&gt;fid_family-&gt;ops-&gt;fid_pack(sfmr_pl, fid,</div><div class='add'>+				       MLXSW_REG_SFMR_OP_CREATE_FID);</div><div class='ctx'> </div><div class='del'>-	mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID,</div><div class='del'>-			    fid-&gt;fid_index, fid-&gt;fid_offset,</div><div class='del'>-			    fid-&gt;fid_family-&gt;flood_rsp,</div><div class='del'>-			    fid-&gt;fid_family-&gt;bridge_type,</div><div class='del'>-			    fid-&gt;fid_family-&gt;smpe_index_valid, smpe);</div><div class='ctx'> 	mlxsw_reg_sfmr_vv_set(sfmr_pl, fid-&gt;vni_valid);</div><div class='ctx'> 	mlxsw_reg_sfmr_vni_set(sfmr_pl, be32_to_cpu(fid-&gt;vni));</div><div class='ctx'> 	mlxsw_reg_sfmr_vtfp_set(sfmr_pl, fid-&gt;nve_flood_index_valid);</div><div class='hunk'>@@ -768,12 +911,13 @@ mlxsw_sp_fid_8021d_fid(const struct mlxsw_sp_fid *fid)</div><div class='ctx'> 	return container_of(fid, struct mlxsw_sp_fid_8021d, common);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mlxsw_sp_fid_8021d_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='add'>+static int mlxsw_sp_fid_8021d_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	int br_ifindex = *(int *) arg;</div><div class='ctx'> </div><div class='ctx'> 	mlxsw_sp_fid_8021d_fid(fid)-&gt;br_ifindex = br_ifindex;</div><div class='ctx'> 	fid-&gt;fid_offset = fid-&gt;fid_index - fid-&gt;fid_family-&gt;start_index;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mlxsw_sp_fid_8021d_configure(struct mlxsw_sp_fid *fid)</div><div class='hunk'>@@ -1058,7 +1202,37 @@ mlxsw_sp_fid_8021d_vid_to_fid_rif_update(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops = {</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_flood_table_init_ctl(struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				  const struct mlxsw_sp_flood_table *flood_table)</div><div class='add'>+{</div><div class='add'>+	enum mlxsw_sp_flood_type packet_type = flood_table-&gt;packet_type;</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = fid_family-&gt;mlxsw_sp;</div><div class='add'>+	const int *sfgc_packet_types;</div><div class='add'>+	u16 mid_base;</div><div class='add'>+	int err, i;</div><div class='add'>+</div><div class='add'>+	mid_base = mlxsw_sp_fid_pgt_base_ctl(fid_family, flood_table);</div><div class='add'>+</div><div class='add'>+	sfgc_packet_types = mlxsw_sp_packet_type_sfgc_types[packet_type];</div><div class='add'>+	for (i = 0; i &lt; MLXSW_REG_SFGC_TYPE_MAX; i++) {</div><div class='add'>+		char sfgc_pl[MLXSW_REG_SFGC_LEN];</div><div class='add'>+</div><div class='add'>+		if (!sfgc_packet_types[i])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		mlxsw_reg_sfgc_pack(sfgc_pl, i, fid_family-&gt;bridge_type,</div><div class='add'>+				    flood_table-&gt;table_type, 0, mid_base);</div><div class='add'>+</div><div class='add'>+		err = mlxsw_reg_write(mlxsw_sp-&gt;core, MLXSW_REG(sfgc), sfgc_pl);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops_ctl = {</div><div class='ctx'> 	.setup			= mlxsw_sp_fid_8021d_setup,</div><div class='ctx'> 	.configure		= mlxsw_sp_fid_8021d_configure,</div><div class='ctx'> 	.deconfigure		= mlxsw_sp_fid_8021d_deconfigure,</div><div class='hunk'>@@ -1072,6 +1246,36 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops = {</div><div class='ctx'> 	.nve_flood_index_clear	= mlxsw_sp_fid_8021d_nve_flood_index_clear,</div><div class='ctx'> 	.fdb_clear_offload	= mlxsw_sp_fid_8021d_fdb_clear_offload,</div><div class='ctx'> 	.vid_to_fid_rif_update  = mlxsw_sp_fid_8021d_vid_to_fid_rif_update,</div><div class='add'>+	.flood_table_init	= mlxsw_sp_fid_flood_table_init_ctl,</div><div class='add'>+	.pgt_size		= mlxsw_sp_fid_8021d_pgt_size,</div><div class='add'>+	.fid_mid		= mlxsw_sp_fid_fid_mid_ctl,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_pack_ctl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u16</div><div class='add'>+mlxsw_sp_fid_fid_mid_cff(const struct mlxsw_sp_fid *fid,</div><div class='add'>+			 const struct mlxsw_sp_flood_table *flood_table)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fid_pgt_base_cff(fid) + flood_table-&gt;table_index;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops_cff = {</div><div class='add'>+	.setup			= mlxsw_sp_fid_8021d_setup,</div><div class='add'>+	.configure		= mlxsw_sp_fid_8021d_configure,</div><div class='add'>+	.deconfigure		= mlxsw_sp_fid_8021d_deconfigure,</div><div class='add'>+	.index_alloc		= mlxsw_sp_fid_8021d_index_alloc,</div><div class='add'>+	.compare		= mlxsw_sp_fid_8021d_compare,</div><div class='add'>+	.port_vid_map		= mlxsw_sp_fid_8021d_port_vid_map,</div><div class='add'>+	.port_vid_unmap		= mlxsw_sp_fid_8021d_port_vid_unmap,</div><div class='add'>+	.vni_set		= mlxsw_sp_fid_8021d_vni_set,</div><div class='add'>+	.vni_clear		= mlxsw_sp_fid_8021d_vni_clear,</div><div class='add'>+	.nve_flood_index_set	= mlxsw_sp_fid_8021d_nve_flood_index_set,</div><div class='add'>+	.nve_flood_index_clear	= mlxsw_sp_fid_8021d_nve_flood_index_clear,</div><div class='add'>+	.fdb_clear_offload	= mlxsw_sp_fid_8021d_fdb_clear_offload,</div><div class='add'>+	.vid_to_fid_rif_update	= mlxsw_sp_fid_8021d_vid_to_fid_rif_update,</div><div class='add'>+	.pgt_size		= mlxsw_sp_fid_8021d_pgt_size,</div><div class='add'>+	.fid_mid		= mlxsw_sp_fid_fid_mid_cff,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_fid_pack_cff,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define MLXSW_SP_FID_8021Q_MAX (VLAN_N_VID - 2)</div><div class='hunk'>@@ -1095,6 +1299,45 @@ static const struct mlxsw_sp_flood_table mlxsw_sp_fid_8021d_flood_tables[] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const</div><div class='add'>+struct mlxsw_sp_fid_flood_profile mlxsw_sp_fid_8021d_flood_profile = {</div><div class='add'>+	.flood_tables		= mlxsw_sp_fid_8021d_flood_tables,</div><div class='add'>+	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_8021d_flood_tables),</div><div class='add'>+	.profile_id		= MLXSW_SP_FID_FLOOD_PROFILE_ID_BRIDGE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_flood_table mlxsw_sp_fid_rsp_flood_tables_cff[] = {</div><div class='add'>+	{</div><div class='add'>+		.packet_type	= MLXSW_SP_FLOOD_TYPE_UC,</div><div class='add'>+		.table_index	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.packet_type	= MLXSW_SP_FLOOD_TYPE_NOT_UC,</div><div class='add'>+		.table_index	= 1,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const</div><div class='add'>+struct mlxsw_sp_fid_flood_profile mlxsw_sp_fid_rsp_flood_profile_cff = {</div><div class='add'>+	.flood_tables		= mlxsw_sp_fid_rsp_flood_tables_cff,</div><div class='add'>+	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_rsp_flood_tables_cff),</div><div class='add'>+	.profile_id		= MLXSW_SP_FID_FLOOD_PROFILE_ID_RSP,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_flood_table mlxsw_sp_fid_nve_flood_tables_cff[] = {</div><div class='add'>+	{</div><div class='add'>+		.packet_type	= MLXSW_SP_FLOOD_TYPE_ANY,</div><div class='add'>+		.table_index	= 0,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const</div><div class='add'>+struct mlxsw_sp_fid_flood_profile mlxsw_sp_fid_nve_flood_profile_cff = {</div><div class='add'>+	.flood_tables		= mlxsw_sp_fid_nve_flood_tables_cff,</div><div class='add'>+	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_nve_flood_tables_cff),</div><div class='add'>+	.profile_id		= MLXSW_SP_FID_FLOOD_PROFILE_ID_NVE,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static bool</div><div class='ctx'> mlxsw_sp_fid_8021q_compare(const struct mlxsw_sp_fid *fid, const void *arg)</div><div class='ctx'> {</div><div class='hunk'>@@ -1110,9 +1353,35 @@ mlxsw_sp_fid_8021q_fdb_clear_offload(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> 	br_fdb_clear_offload(nve_dev, mlxsw_sp_fid_8021q_vid(fid));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void mlxsw_sp_fid_rfid_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='add'>+static int mlxsw_sp_fid_rfid_setup_ctl(struct mlxsw_sp_fid *fid,</div><div class='add'>+				       const void *arg)</div><div class='ctx'> {</div><div class='add'>+	/* In controlled mode, the FW takes care of FID placement. */</div><div class='ctx'> 	fid-&gt;fid_offset = 0;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp_fid_rfid_setup_cff(struct mlxsw_sp_fid *fid,</div><div class='add'>+				       const void *arg)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = fid-&gt;fid_family-&gt;mlxsw_sp;</div><div class='add'>+	u16 rif_index = *(const u16 *)arg;</div><div class='add'>+	struct mlxsw_sp_rif *rif;</div><div class='add'>+	bool is_lag;</div><div class='add'>+	u16 port;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	rif = mlxsw_sp_rif_by_index(mlxsw_sp, rif_index);</div><div class='add'>+	if (!rif)</div><div class='add'>+		return -ENOENT;</div><div class='add'>+</div><div class='add'>+	err = mlxsw_sp_rif_subport_port(rif, &amp;port, &amp;is_lag);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	fid-&gt;fid_offset = mlxsw_sp_fid_rfid_fid_offset_cff(mlxsw_sp, port,</div><div class='add'>+							   is_lag);</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mlxsw_sp_fid_rfid_configure(struct mlxsw_sp_fid *fid)</div><div class='hunk'>@@ -1238,8 +1507,8 @@ mlxsw_sp_fid_rfid_vid_to_fid_rif_update(const struct mlxsw_sp_fid *fid,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_rfid_ops = {</div><div class='del'>-	.setup			= mlxsw_sp_fid_rfid_setup,</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_rfid_ops_ctl = {</div><div class='add'>+	.setup			= mlxsw_sp_fid_rfid_setup_ctl,</div><div class='ctx'> 	.configure		= mlxsw_sp_fid_rfid_configure,</div><div class='ctx'> 	.deconfigure		= mlxsw_sp_fid_rfid_deconfigure,</div><div class='ctx'> 	.index_alloc		= mlxsw_sp_fid_rfid_index_alloc,</div><div class='hunk'>@@ -1251,11 +1520,146 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_rfid_ops = {</div><div class='ctx'> 	.nve_flood_index_set	= mlxsw_sp_fid_rfid_nve_flood_index_set,</div><div class='ctx'> 	.nve_flood_index_clear	= mlxsw_sp_fid_rfid_nve_flood_index_clear,</div><div class='ctx'> 	.vid_to_fid_rif_update  = mlxsw_sp_fid_rfid_vid_to_fid_rif_update,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_pack_ctl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_rfid_port_add_cff(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+			       const struct mlxsw_sp_flood_table *flood_table,</div><div class='add'>+			       u16 pgt_addr, u16 smpe, unsigned int local_port)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = mlxsw_sp_pgt_entry_port_set(mlxsw_sp, pgt_addr, smpe,</div><div class='add'>+					  local_port, true);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (flood_table-&gt;packet_type == MLXSW_SP_FLOOD_TYPE_NOT_UC) {</div><div class='add'>+		u16 router_port = mlxsw_sp_router_port(mlxsw_sp);</div><div class='add'>+</div><div class='add'>+		err = mlxsw_sp_pgt_entry_port_set(mlxsw_sp, pgt_addr, smpe,</div><div class='add'>+						  router_port, true);</div><div class='add'>+		if (err)</div><div class='add'>+			goto err_entry_port_set;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_entry_port_set:</div><div class='add'>+	mlxsw_sp_pgt_entry_port_set(mlxsw_sp, pgt_addr, smpe, local_port,</div><div class='add'>+				    false);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mlxsw_sp_fid_rfid_port_del_cff(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+			       const struct mlxsw_sp_flood_table *flood_table,</div><div class='add'>+			       u16 pgt_addr, u16 smpe, u16 local_port)</div><div class='add'>+{</div><div class='add'>+	if (flood_table-&gt;packet_type == MLXSW_SP_FLOOD_TYPE_NOT_UC) {</div><div class='add'>+		u16 router_port = mlxsw_sp_router_port(mlxsw_sp);</div><div class='add'>+</div><div class='add'>+		mlxsw_sp_pgt_entry_port_set(mlxsw_sp, pgt_addr, smpe,</div><div class='add'>+					    router_port, false);</div><div class='add'>+	}</div><div class='add'>+	mlxsw_sp_pgt_entry_port_set(mlxsw_sp, pgt_addr, smpe, local_port,</div><div class='add'>+				    false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_rfid_port_memb_ft_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				   const struct mlxsw_sp_flood_table *flood_table,</div><div class='add'>+				   const struct mlxsw_sp_port *mlxsw_sp_port,</div><div class='add'>+				   bool member)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = fid_family-&gt;mlxsw_sp;</div><div class='add'>+	u16 local_port = mlxsw_sp_port-&gt;local_port;</div><div class='add'>+	u16 fid_pgt_base;</div><div class='add'>+	u16 fid_offset;</div><div class='add'>+	u16 pgt_addr;</div><div class='add'>+	u16 smpe;</div><div class='add'>+	u16 port;</div><div class='add'>+</div><div class='add'>+	/* In-PGT SMPE is only valid on Spectrum-1, CFF only on Spectrum&gt;1. */</div><div class='add'>+	smpe = 0;</div><div class='add'>+</div><div class='add'>+	port = mlxsw_sp_port-&gt;lagged ? mlxsw_sp_port-&gt;lag_id : local_port;</div><div class='add'>+	fid_offset = mlxsw_sp_fid_rfid_fid_offset_cff(mlxsw_sp, port,</div><div class='add'>+						      mlxsw_sp_port-&gt;lagged);</div><div class='add'>+	fid_pgt_base = mlxsw_sp_fid_off_pgt_base_cff(fid_family, fid_offset);</div><div class='add'>+	pgt_addr = fid_pgt_base + flood_table-&gt;table_index;</div><div class='add'>+</div><div class='add'>+	if (member)</div><div class='add'>+		return mlxsw_sp_fid_rfid_port_add_cff(mlxsw_sp, flood_table,</div><div class='add'>+						      pgt_addr, smpe,</div><div class='add'>+						      local_port);</div><div class='add'>+</div><div class='add'>+	mlxsw_sp_fid_rfid_port_del_cff(mlxsw_sp, flood_table, pgt_addr, smpe,</div><div class='add'>+				       local_port);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_rfid_port_memb_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				const struct mlxsw_sp_port *mlxsw_sp_port,</div><div class='add'>+				bool member)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fid_family-&gt;flood_profile-&gt;nr_flood_tables; i++) {</div><div class='add'>+		const struct mlxsw_sp_flood_table *flood_table =</div><div class='add'>+			&amp;fid_family-&gt;flood_profile-&gt;flood_tables[i];</div><div class='add'>+		int err;</div><div class='add'>+</div><div class='add'>+		err = mlxsw_sp_fid_rfid_port_memb_ft_cff(fid_family,</div><div class='add'>+							 flood_table,</div><div class='add'>+							 mlxsw_sp_port, member);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fid_rfid_port_init_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fid_rfid_port_memb_cff(fid_family, mlxsw_sp_port, true);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+mlxsw_sp_fid_rfid_port_fini_cff(const struct mlxsw_sp_fid_family *fid_family,</div><div class='add'>+				const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	mlxsw_sp_fid_rfid_port_memb_cff(fid_family, mlxsw_sp_port, false);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_rfid_ops_cff = {</div><div class='add'>+	.setup			= mlxsw_sp_fid_rfid_setup_cff,</div><div class='add'>+	.configure		= mlxsw_sp_fid_rfid_configure,</div><div class='add'>+	.deconfigure		= mlxsw_sp_fid_rfid_deconfigure,</div><div class='add'>+	.index_alloc		= mlxsw_sp_fid_rfid_index_alloc,</div><div class='add'>+	.compare		= mlxsw_sp_fid_rfid_compare,</div><div class='add'>+	.port_vid_map		= mlxsw_sp_fid_rfid_port_vid_map,</div><div class='add'>+	.port_vid_unmap		= mlxsw_sp_fid_rfid_port_vid_unmap,</div><div class='add'>+	.vni_set		= mlxsw_sp_fid_rfid_vni_set,</div><div class='add'>+	.vni_clear		= mlxsw_sp_fid_rfid_vni_clear,</div><div class='add'>+	.nve_flood_index_set	= mlxsw_sp_fid_rfid_nve_flood_index_set,</div><div class='add'>+	.nve_flood_index_clear	= mlxsw_sp_fid_rfid_nve_flood_index_clear,</div><div class='add'>+	.vid_to_fid_rif_update	= mlxsw_sp_fid_rfid_vid_to_fid_rif_update,</div><div class='add'>+	.pgt_size		= mlxsw_sp_fid_rfid_pgt_size_cff,</div><div class='add'>+	.fid_port_init		= mlxsw_sp_fid_rfid_port_init_cff,</div><div class='add'>+	.fid_port_fini		= mlxsw_sp_fid_rfid_port_fini_cff,</div><div class='add'>+	.fid_mid		= mlxsw_sp_fid_fid_mid_cff,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_fid_pack_cff,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void mlxsw_sp_fid_dummy_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='add'>+static int mlxsw_sp_fid_dummy_setup(struct mlxsw_sp_fid *fid, const void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	fid-&gt;fid_offset = 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mlxsw_sp_fid_dummy_configure(struct mlxsw_sp_fid *fid)</div><div class='hunk'>@@ -1312,6 +1716,7 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_dummy_ops = {</div><div class='ctx'> 	.vni_clear		= mlxsw_sp_fid_dummy_vni_clear,</div><div class='ctx'> 	.nve_flood_index_set	= mlxsw_sp_fid_dummy_nve_flood_index_set,</div><div class='ctx'> 	.nve_flood_index_clear	= mlxsw_sp_fid_dummy_nve_flood_index_clear,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_pack,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int mlxsw_sp_fid_8021q_configure(struct mlxsw_sp_fid *fid)</div><div class='hunk'>@@ -1395,7 +1800,7 @@ mlxsw_sp_fid_8021q_port_vid_unmap(struct mlxsw_sp_fid *fid,</div><div class='ctx'> 		__mlxsw_sp_fid_port_vid_map(fid, local_port, vid, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021q_ops = {</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021q_ops_ctl = {</div><div class='ctx'> 	.setup			= mlxsw_sp_fid_8021q_setup,</div><div class='ctx'> 	.configure		= mlxsw_sp_fid_8021q_configure,</div><div class='ctx'> 	.deconfigure		= mlxsw_sp_fid_8021q_deconfigure,</div><div class='hunk'>@@ -1409,6 +1814,29 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021q_ops = {</div><div class='ctx'> 	.nve_flood_index_clear	= mlxsw_sp_fid_8021d_nve_flood_index_clear,</div><div class='ctx'> 	.fdb_clear_offload	= mlxsw_sp_fid_8021q_fdb_clear_offload,</div><div class='ctx'> 	.vid_to_fid_rif_update  = mlxsw_sp_fid_8021q_vid_to_fid_rif_update,</div><div class='add'>+	.flood_table_init	= mlxsw_sp_fid_flood_table_init_ctl,</div><div class='add'>+	.pgt_size		= mlxsw_sp_fid_8021d_pgt_size,</div><div class='add'>+	.fid_mid		= mlxsw_sp_fid_fid_mid_ctl,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_pack_ctl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021q_ops_cff = {</div><div class='add'>+	.setup			= mlxsw_sp_fid_8021q_setup,</div><div class='add'>+	.configure		= mlxsw_sp_fid_8021q_configure,</div><div class='add'>+	.deconfigure		= mlxsw_sp_fid_8021q_deconfigure,</div><div class='add'>+	.index_alloc		= mlxsw_sp_fid_8021d_index_alloc,</div><div class='add'>+	.compare		= mlxsw_sp_fid_8021q_compare,</div><div class='add'>+	.port_vid_map		= mlxsw_sp_fid_8021q_port_vid_map,</div><div class='add'>+	.port_vid_unmap		= mlxsw_sp_fid_8021q_port_vid_unmap,</div><div class='add'>+	.vni_set		= mlxsw_sp_fid_8021d_vni_set,</div><div class='add'>+	.vni_clear		= mlxsw_sp_fid_8021d_vni_clear,</div><div class='add'>+	.nve_flood_index_set	= mlxsw_sp_fid_8021d_nve_flood_index_set,</div><div class='add'>+	.nve_flood_index_clear	= mlxsw_sp_fid_8021d_nve_flood_index_clear,</div><div class='add'>+	.fdb_clear_offload	= mlxsw_sp_fid_8021q_fdb_clear_offload,</div><div class='add'>+	.vid_to_fid_rif_update	= mlxsw_sp_fid_8021q_vid_to_fid_rif_update,</div><div class='add'>+	.pgt_size		= mlxsw_sp_fid_8021d_pgt_size,</div><div class='add'>+	.fid_mid		= mlxsw_sp_fid_fid_mid_cff,</div><div class='add'>+	.fid_pack		= mlxsw_sp_fid_fid_pack_cff,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* There are 4K-2 802.1Q FIDs */</div><div class='hunk'>@@ -1434,10 +1862,9 @@ static const struct mlxsw_sp_fid_family mlxsw_sp1_fid_8021q_family = {</div><div class='ctx'> 	.fid_size		= sizeof(struct mlxsw_sp_fid_8021q),</div><div class='ctx'> 	.start_index		= MLXSW_SP_FID_8021Q_START,</div><div class='ctx'> 	.end_index		= MLXSW_SP_FID_8021Q_END,</div><div class='del'>-	.flood_tables		= mlxsw_sp_fid_8021d_flood_tables,</div><div class='del'>-	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_8021d_flood_tables),</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='ctx'> 	.rif_type		= MLXSW_SP_RIF_TYPE_VLAN,</div><div class='del'>-	.ops			= &amp;mlxsw_sp_fid_8021q_ops,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021q_ops_ctl,</div><div class='ctx'> 	.flood_rsp              = false,</div><div class='ctx'> 	.bridge_type            = MLXSW_REG_BRIDGE_TYPE_0,</div><div class='ctx'> 	.smpe_index_valid	= false,</div><div class='hunk'>@@ -1448,10 +1875,9 @@ static const struct mlxsw_sp_fid_family mlxsw_sp1_fid_8021d_family = {</div><div class='ctx'> 	.fid_size		= sizeof(struct mlxsw_sp_fid_8021d),</div><div class='ctx'> 	.start_index		= MLXSW_SP_FID_8021D_START,</div><div class='ctx'> 	.end_index		= MLXSW_SP_FID_8021D_END,</div><div class='del'>-	.flood_tables		= mlxsw_sp_fid_8021d_flood_tables,</div><div class='del'>-	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_8021d_flood_tables),</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='ctx'> 	.rif_type		= MLXSW_SP_RIF_TYPE_FID,</div><div class='del'>-	.ops			= &amp;mlxsw_sp_fid_8021d_ops,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021d_ops_ctl,</div><div class='ctx'> 	.bridge_type            = MLXSW_REG_BRIDGE_TYPE_1,</div><div class='ctx'> 	.smpe_index_valid       = false,</div><div class='ctx'> };</div><div class='hunk'>@@ -1465,47 +1891,45 @@ static const struct mlxsw_sp_fid_family mlxsw_sp1_fid_dummy_family = {</div><div class='ctx'> 	.smpe_index_valid       = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_family mlxsw_sp_fid_rfid_family = {</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp_fid_rfid_family_ctl = {</div><div class='ctx'> 	.type			= MLXSW_SP_FID_TYPE_RFID,</div><div class='ctx'> 	.fid_size		= sizeof(struct mlxsw_sp_fid),</div><div class='ctx'> 	.start_index		= MLXSW_SP_RFID_START,</div><div class='ctx'> 	.end_index		= MLXSW_SP_RFID_END,</div><div class='ctx'> 	.rif_type		= MLXSW_SP_RIF_TYPE_SUBPORT,</div><div class='del'>-	.ops			= &amp;mlxsw_sp_fid_rfid_ops,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_rfid_ops_ctl,</div><div class='ctx'> 	.flood_rsp              = true,</div><div class='ctx'> 	.smpe_index_valid       = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-const struct mlxsw_sp_fid_family *mlxsw_sp1_fid_family_arr[] = {</div><div class='add'>+static const struct mlxsw_sp_fid_family *mlxsw_sp1_fid_family_arr[] = {</div><div class='ctx'> 	[MLXSW_SP_FID_TYPE_8021Q]	= &amp;mlxsw_sp1_fid_8021q_family,</div><div class='ctx'> 	[MLXSW_SP_FID_TYPE_8021D]	= &amp;mlxsw_sp1_fid_8021d_family,</div><div class='ctx'> 	[MLXSW_SP_FID_TYPE_DUMMY]	= &amp;mlxsw_sp1_fid_dummy_family,</div><div class='del'>-	[MLXSW_SP_FID_TYPE_RFID]	= &amp;mlxsw_sp_fid_rfid_family,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_RFID]	= &amp;mlxsw_sp_fid_rfid_family_ctl,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021q_family = {</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021q_family_ctl = {</div><div class='ctx'> 	.type			= MLXSW_SP_FID_TYPE_8021Q,</div><div class='ctx'> 	.fid_size		= sizeof(struct mlxsw_sp_fid_8021q),</div><div class='ctx'> 	.start_index		= MLXSW_SP_FID_8021Q_START,</div><div class='ctx'> 	.end_index		= MLXSW_SP_FID_8021Q_END,</div><div class='del'>-	.flood_tables		= mlxsw_sp_fid_8021d_flood_tables,</div><div class='del'>-	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_8021d_flood_tables),</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='ctx'> 	.rif_type		= MLXSW_SP_RIF_TYPE_VLAN,</div><div class='del'>-	.ops			= &amp;mlxsw_sp_fid_8021q_ops,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021q_ops_ctl,</div><div class='ctx'> 	.flood_rsp              = false,</div><div class='ctx'> 	.bridge_type            = MLXSW_REG_BRIDGE_TYPE_0,</div><div class='ctx'> 	.smpe_index_valid	= true,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021d_family = {</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021d_family_ctl = {</div><div class='ctx'> 	.type			= MLXSW_SP_FID_TYPE_8021D,</div><div class='ctx'> 	.fid_size		= sizeof(struct mlxsw_sp_fid_8021d),</div><div class='ctx'> 	.start_index		= MLXSW_SP_FID_8021D_START,</div><div class='ctx'> 	.end_index		= MLXSW_SP_FID_8021D_END,</div><div class='del'>-	.flood_tables		= mlxsw_sp_fid_8021d_flood_tables,</div><div class='del'>-	.nr_flood_tables	= ARRAY_SIZE(mlxsw_sp_fid_8021d_flood_tables),</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='ctx'> 	.rif_type		= MLXSW_SP_RIF_TYPE_FID,</div><div class='del'>-	.ops			= &amp;mlxsw_sp_fid_8021d_ops,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021d_ops_ctl,</div><div class='ctx'> 	.bridge_type            = MLXSW_REG_BRIDGE_TYPE_1,</div><div class='ctx'> 	.smpe_index_valid       = true,</div><div class='ctx'> };</div><div class='hunk'>@@ -1519,11 +1943,51 @@ static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_dummy_family = {</div><div class='ctx'> 	.smpe_index_valid       = false,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-const struct mlxsw_sp_fid_family *mlxsw_sp2_fid_family_arr[] = {</div><div class='del'>-	[MLXSW_SP_FID_TYPE_8021Q]	= &amp;mlxsw_sp2_fid_8021q_family,</div><div class='del'>-	[MLXSW_SP_FID_TYPE_8021D]	= &amp;mlxsw_sp2_fid_8021d_family,</div><div class='add'>+static const struct mlxsw_sp_fid_family *mlxsw_sp2_fid_family_arr_ctl[] = {</div><div class='add'>+	[MLXSW_SP_FID_TYPE_8021Q]	= &amp;mlxsw_sp2_fid_8021q_family_ctl,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_8021D]	= &amp;mlxsw_sp2_fid_8021d_family_ctl,</div><div class='ctx'> 	[MLXSW_SP_FID_TYPE_DUMMY]	= &amp;mlxsw_sp2_fid_dummy_family,</div><div class='del'>-	[MLXSW_SP_FID_TYPE_RFID]	= &amp;mlxsw_sp_fid_rfid_family,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_RFID]	= &amp;mlxsw_sp_fid_rfid_family_ctl,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021q_family_cff = {</div><div class='add'>+	.type			= MLXSW_SP_FID_TYPE_8021Q,</div><div class='add'>+	.fid_size		= sizeof(struct mlxsw_sp_fid_8021q),</div><div class='add'>+	.start_index		= MLXSW_SP_FID_8021Q_START,</div><div class='add'>+	.end_index		= MLXSW_SP_FID_8021Q_END,</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='add'>+	.rif_type		= MLXSW_SP_RIF_TYPE_VLAN,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021q_ops_cff,</div><div class='add'>+	.smpe_index_valid	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021d_family_cff = {</div><div class='add'>+	.type			= MLXSW_SP_FID_TYPE_8021D,</div><div class='add'>+	.fid_size		= sizeof(struct mlxsw_sp_fid_8021d),</div><div class='add'>+	.start_index		= MLXSW_SP_FID_8021D_START,</div><div class='add'>+	.end_index		= MLXSW_SP_FID_8021D_END,</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='add'>+	.rif_type		= MLXSW_SP_RIF_TYPE_FID,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_8021d_ops_cff,</div><div class='add'>+	.smpe_index_valid	= true,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_family mlxsw_sp_fid_rfid_family_cff = {</div><div class='add'>+	.type			= MLXSW_SP_FID_TYPE_RFID,</div><div class='add'>+	.fid_size		= sizeof(struct mlxsw_sp_fid),</div><div class='add'>+	.start_index		= MLXSW_SP_RFID_START,</div><div class='add'>+	.end_index		= MLXSW_SP_RFID_END,</div><div class='add'>+	.flood_profile		= &amp;mlxsw_sp_fid_rsp_flood_profile_cff,</div><div class='add'>+	.rif_type		= MLXSW_SP_RIF_TYPE_SUBPORT,</div><div class='add'>+	.ops			= &amp;mlxsw_sp_fid_rfid_ops_cff,</div><div class='add'>+	.smpe_index_valid	= false,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mlxsw_sp_fid_family *mlxsw_sp2_fid_family_arr_cff[] = {</div><div class='add'>+	[MLXSW_SP_FID_TYPE_8021Q]	= &amp;mlxsw_sp2_fid_8021q_family_cff,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_8021D]	= &amp;mlxsw_sp2_fid_8021d_family_cff,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_DUMMY]	= &amp;mlxsw_sp2_fid_dummy_family,</div><div class='add'>+	[MLXSW_SP_FID_TYPE_RFID]	= &amp;mlxsw_sp_fid_rfid_family_cff,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct mlxsw_sp_fid *mlxsw_sp_fid_lookup(struct mlxsw_sp *mlxsw_sp,</div><div class='hunk'>@@ -1571,7 +2035,9 @@ static struct mlxsw_sp_fid *mlxsw_sp_fid_get(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	fid-&gt;fid_index = fid_index;</div><div class='ctx'> 	__set_bit(fid_index - fid_family-&gt;start_index, fid_family-&gt;fids_bitmap);</div><div class='ctx'> </div><div class='del'>-	fid-&gt;fid_family-&gt;ops-&gt;setup(fid, arg);</div><div class='add'>+	err = fid-&gt;fid_family-&gt;ops-&gt;setup(fid, arg);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_setup;</div><div class='ctx'> </div><div class='ctx'> 	err = fid-&gt;fid_family-&gt;ops-&gt;configure(fid);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -1589,6 +2055,7 @@ static struct mlxsw_sp_fid *mlxsw_sp_fid_get(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> err_rhashtable_insert:</div><div class='ctx'> 	fid-&gt;fid_family-&gt;ops-&gt;deconfigure(fid);</div><div class='ctx'> err_configure:</div><div class='add'>+err_setup:</div><div class='ctx'> 	__clear_bit(fid_index - fid_family-&gt;start_index,</div><div class='ctx'> 		    fid_family-&gt;fids_bitmap);</div><div class='ctx'> err_index_alloc:</div><div class='hunk'>@@ -1650,36 +2117,6 @@ struct mlxsw_sp_fid *mlxsw_sp_fid_dummy_get(struct mlxsw_sp *mlxsw_sp)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-mlxsw_sp_fid_flood_table_init(struct mlxsw_sp_fid_family *fid_family,</div><div class='del'>-			      const struct mlxsw_sp_flood_table *flood_table)</div><div class='del'>-{</div><div class='del'>-	enum mlxsw_sp_flood_type packet_type = flood_table-&gt;packet_type;</div><div class='del'>-	struct mlxsw_sp *mlxsw_sp = fid_family-&gt;mlxsw_sp;</div><div class='del'>-	const int *sfgc_packet_types;</div><div class='del'>-	u16 mid_base;</div><div class='del'>-	int err, i;</div><div class='del'>-</div><div class='del'>-	mid_base = mlxsw_sp_fid_flood_table_mid(fid_family, flood_table, 0);</div><div class='del'>-</div><div class='del'>-	sfgc_packet_types = mlxsw_sp_packet_type_sfgc_types[packet_type];</div><div class='del'>-	for (i = 0; i &lt; MLXSW_REG_SFGC_TYPE_MAX; i++) {</div><div class='del'>-		char sfgc_pl[MLXSW_REG_SFGC_LEN];</div><div class='del'>-</div><div class='del'>-		if (!sfgc_packet_types[i])</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		mlxsw_reg_sfgc_pack(sfgc_pl, i, fid_family-&gt;bridge_type,</div><div class='del'>-				    flood_table-&gt;table_type, 0, mid_base);</div><div class='del'>-</div><div class='del'>-		err = mlxsw_reg_write(mlxsw_sp-&gt;core, MLXSW_REG(sfgc), sfgc_pl);</div><div class='del'>-		if (err)</div><div class='del'>-			return err;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int</div><div class='ctx'> mlxsw_sp_fid_flood_tables_init(struct mlxsw_sp_fid_family *fid_family)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp = fid_family-&gt;mlxsw_sp;</div><div class='hunk'>@@ -1687,22 +2124,28 @@ mlxsw_sp_fid_flood_tables_init(struct mlxsw_sp_fid_family *fid_family)</div><div class='ctx'> 	int err;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (!fid_family-&gt;nr_flood_tables)</div><div class='del'>-		return 0;</div><div class='add'>+	err = fid_family-&gt;ops-&gt;pgt_size(fid_family, &amp;pgt_size);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='del'>-	pgt_size = mlxsw_sp_fid_family_pgt_size(fid_family);</div><div class='ctx'> 	err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &amp;fid_family-&gt;pgt_base,</div><div class='ctx'> 					   pgt_size);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; fid_family-&gt;nr_flood_tables; i++) {</div><div class='add'>+	if (!fid_family-&gt;flood_profile)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; fid_family-&gt;flood_profile-&gt;nr_flood_tables; i++) {</div><div class='ctx'> 		const struct mlxsw_sp_flood_table *flood_table;</div><div class='ctx'> </div><div class='del'>-		flood_table = &amp;fid_family-&gt;flood_tables[i];</div><div class='del'>-		err = mlxsw_sp_fid_flood_table_init(fid_family, flood_table);</div><div class='del'>-		if (err)</div><div class='del'>-			goto err_flood_table_init;</div><div class='add'>+		flood_table = &amp;fid_family-&gt;flood_profile-&gt;flood_tables[i];</div><div class='add'>+		if (fid_family-&gt;ops-&gt;flood_table_init) {</div><div class='add'>+			err = fid_family-&gt;ops-&gt;flood_table_init(fid_family,</div><div class='add'>+								flood_table);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err_flood_table_init;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -1717,11 +2160,12 @@ mlxsw_sp_fid_flood_tables_fini(struct mlxsw_sp_fid_family *fid_family)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp = fid_family-&gt;mlxsw_sp;</div><div class='ctx'> 	u16 pgt_size;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-	if (!fid_family-&gt;nr_flood_tables)</div><div class='add'>+	err = fid_family-&gt;ops-&gt;pgt_size(fid_family, &amp;pgt_size);</div><div class='add'>+	if (WARN_ON_ONCE(err))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	pgt_size = mlxsw_sp_fid_family_pgt_size(fid_family);</div><div class='ctx'> 	mlxsw_sp_pgt_mid_free_range(mlxsw_sp, fid_family-&gt;pgt_base, pgt_size);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1744,7 +2188,7 @@ static int mlxsw_sp_fid_family_register(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 		goto err_alloc_fids_bitmap;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (fid_family-&gt;flood_tables) {</div><div class='add'>+	if (fid_family-&gt;flood_profile) {</div><div class='ctx'> 		err = mlxsw_sp_fid_flood_tables_init(fid_family);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto err_fid_flood_tables_init;</div><div class='hunk'>@@ -1767,7 +2211,7 @@ mlxsw_sp_fid_family_unregister(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> {</div><div class='ctx'> 	mlxsw_sp-&gt;fid_core-&gt;fid_family_arr[fid_family-&gt;type] = NULL;</div><div class='ctx'> </div><div class='del'>-	if (fid_family-&gt;flood_tables)</div><div class='add'>+	if (fid_family-&gt;flood_profile)</div><div class='ctx'> 		mlxsw_sp_fid_flood_tables_fini(fid_family);</div><div class='ctx'> </div><div class='ctx'> 	bitmap_free(fid_family-&gt;fids_bitmap);</div><div class='hunk'>@@ -1775,9 +2219,34 @@ mlxsw_sp_fid_family_unregister(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	kfree(fid_family);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mlxsw_sp_fid_port_init(const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	const enum mlxsw_sp_fid_type type_rfid = MLXSW_SP_FID_TYPE_RFID;</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port-&gt;mlxsw_sp;</div><div class='add'>+	struct mlxsw_sp_fid_family *rfid_family;</div><div class='add'>+</div><div class='add'>+	rfid_family = mlxsw_sp-&gt;fid_core-&gt;fid_family_arr[type_rfid];</div><div class='add'>+	if (rfid_family-&gt;ops-&gt;fid_port_init)</div><div class='add'>+		return rfid_family-&gt;ops-&gt;fid_port_init(rfid_family,</div><div class='add'>+						       mlxsw_sp_port);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void mlxsw_sp_fid_port_fini(const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	const enum mlxsw_sp_fid_type type_rfid = MLXSW_SP_FID_TYPE_RFID;</div><div class='add'>+	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port-&gt;mlxsw_sp;</div><div class='add'>+	struct mlxsw_sp_fid_family *rfid_family;</div><div class='add'>+</div><div class='add'>+	rfid_family = mlxsw_sp-&gt;fid_core-&gt;fid_family_arr[type_rfid];</div><div class='add'>+	if (rfid_family-&gt;ops-&gt;fid_port_fini)</div><div class='add'>+		rfid_family-&gt;ops-&gt;fid_port_fini(rfid_family, mlxsw_sp_port);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int mlxsw_sp_port_fids_init(struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port-&gt;mlxsw_sp;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	/* Track number of FIDs configured on the port with mapping type</div><div class='ctx'> 	 * PORT_VID_TO_FID, so that we know when to transition the port</div><div class='hunk'>@@ -1785,17 +2254,42 @@ int mlxsw_sp_port_fids_init(struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='ctx'> 	 */</div><div class='ctx'> 	mlxsw_sp-&gt;fid_core-&gt;port_fid_mappings[mlxsw_sp_port-&gt;local_port] = 0;</div><div class='ctx'> </div><div class='del'>-	return mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);</div><div class='add'>+	err = mlxsw_sp_fid_port_init(mlxsw_sp_port);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_vp_mode_set;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_vp_mode_set:</div><div class='add'>+	mlxsw_sp_fid_port_fini(mlxsw_sp_port);</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void mlxsw_sp_port_fids_fini(struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port-&gt;mlxsw_sp;</div><div class='ctx'> </div><div class='add'>+	mlxsw_sp_fid_port_fini(mlxsw_sp_port);</div><div class='ctx'> 	mlxsw_sp-&gt;fid_core-&gt;port_fid_mappings[mlxsw_sp_port-&gt;local_port] = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int mlxsw_sp_fids_init(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+int mlxsw_sp_fid_port_join_lag(const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fid_port_init(mlxsw_sp_port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void mlxsw_sp_fid_port_leave_lag(const struct mlxsw_sp_port *mlxsw_sp_port)</div><div class='add'>+{</div><div class='add'>+	mlxsw_sp_fid_port_fini(mlxsw_sp_port);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp_fids_init(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+		   const struct mlxsw_sp_fid_family *fid_family_arr[])</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp-&gt;core);</div><div class='ctx'> 	struct mlxsw_sp_fid_core *fid_core;</div><div class='hunk'>@@ -1822,8 +2316,7 @@ int mlxsw_sp_fids_init(struct mlxsw_sp *mlxsw_sp)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; MLXSW_SP_FID_TYPE_MAX; i++) {</div><div class='del'>-		err = mlxsw_sp_fid_family_register(mlxsw_sp,</div><div class='del'>-						   mlxsw_sp-&gt;fid_family_arr[i]);</div><div class='add'>+		err = mlxsw_sp_fid_family_register(mlxsw_sp, fid_family_arr[i]);</div><div class='ctx'> </div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto err_fid_ops_register;</div><div class='hunk'>@@ -1848,7 +2341,7 @@ err_rhashtable_fid_init:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+static void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp_fid_core *fid_core = mlxsw_sp-&gt;fid_core;</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1861,3 +2354,143 @@ void mlxsw_sp_fids_fini(struct mlxsw_sp *mlxsw_sp)</div><div class='ctx'> 	rhashtable_destroy(&amp;fid_core-&gt;fid_ht);</div><div class='ctx'> 	kfree(fid_core);</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp1_fids_init(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fids_init(mlxsw_sp, mlxsw_sp1_fid_family_arr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct mlxsw_sp_fid_core_ops mlxsw_sp1_fid_core_ops = {</div><div class='add'>+	.init = mlxsw_sp1_fids_init,</div><div class='add'>+	.fini = mlxsw_sp_fids_fini,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp_fid_check_flood_profile_id(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+					       int profile_id)</div><div class='add'>+{</div><div class='add'>+	u32 max_profiles;</div><div class='add'>+</div><div class='add'>+	if (!MLXSW_CORE_RES_VALID(mlxsw_sp-&gt;core, MAX_NVE_FLOOD_PRF))</div><div class='add'>+		return -EIO;</div><div class='add'>+</div><div class='add'>+	max_profiles = MLXSW_CORE_RES_GET(mlxsw_sp-&gt;core, MAX_NVE_FLOOD_PRF);</div><div class='add'>+	if (WARN_ON_ONCE(!profile_id) ||</div><div class='add'>+	    WARN_ON_ONCE(profile_id &gt;= max_profiles))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp2_fids_init_flood_table(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+				enum mlxsw_sp_fid_flood_profile_id profile_id,</div><div class='add'>+				const struct mlxsw_sp_flood_table *flood_table)</div><div class='add'>+{</div><div class='add'>+	enum mlxsw_sp_flood_type packet_type = flood_table-&gt;packet_type;</div><div class='add'>+	const int *sfgc_packet_types;</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	sfgc_packet_types = mlxsw_sp_packet_type_sfgc_types[packet_type];</div><div class='add'>+	for (i = 0; i &lt; MLXSW_REG_SFGC_TYPE_MAX; i++) {</div><div class='add'>+		char sffp_pl[MLXSW_REG_SFFP_LEN];</div><div class='add'>+</div><div class='add'>+		if (!sfgc_packet_types[i])</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		mlxsw_reg_sffp_pack(sffp_pl, profile_id, i,</div><div class='add'>+				    flood_table-&gt;table_index);</div><div class='add'>+		err = mlxsw_reg_write(mlxsw_sp-&gt;core, MLXSW_REG(sffp), sffp_pl);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp2_fids_init_flood_profile(struct mlxsw_sp *mlxsw_sp,</div><div class='add'>+				  const struct mlxsw_sp_fid_flood_profile *</div><div class='add'>+					flood_profile)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	err = mlxsw_sp_fid_check_flood_profile_id(mlxsw_sp,</div><div class='add'>+						  flood_profile-&gt;profile_id);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; flood_profile-&gt;nr_flood_tables; i++) {</div><div class='add'>+		const struct mlxsw_sp_flood_table *flood_table;</div><div class='add'>+</div><div class='add'>+		flood_table = &amp;flood_profile-&gt;flood_tables[i];</div><div class='add'>+		err = mlxsw_sp2_fids_init_flood_table(mlxsw_sp,</div><div class='add'>+						      flood_profile-&gt;profile_id,</div><div class='add'>+						      flood_table);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const</div><div class='add'>+struct mlxsw_sp_fid_flood_profile *mlxsw_sp_fid_flood_profiles[] = {</div><div class='add'>+	&amp;mlxsw_sp_fid_8021d_flood_profile,</div><div class='add'>+	&amp;mlxsw_sp_fid_rsp_flood_profile_cff,</div><div class='add'>+	&amp;mlxsw_sp_fid_nve_flood_profile_cff,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+mlxsw_sp2_fids_init_flood_profiles(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(mlxsw_sp_fid_flood_profiles); i++) {</div><div class='add'>+		const struct mlxsw_sp_fid_flood_profile *flood_profile;</div><div class='add'>+</div><div class='add'>+		flood_profile = mlxsw_sp_fid_flood_profiles[i];</div><div class='add'>+		err = mlxsw_sp2_fids_init_flood_profile(mlxsw_sp,</div><div class='add'>+							flood_profile);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp2_fids_init_ctl(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+{</div><div class='add'>+	return mlxsw_sp_fids_init(mlxsw_sp, mlxsw_sp2_fid_family_arr_ctl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp2_fids_init_cff(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = mlxsw_sp2_fids_init_flood_profiles(mlxsw_sp);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return mlxsw_sp_fids_init(mlxsw_sp, mlxsw_sp2_fid_family_arr_cff);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mlxsw_sp2_fids_init(struct mlxsw_sp *mlxsw_sp)</div><div class='add'>+{</div><div class='add'>+	switch (mlxsw_core_flood_mode(mlxsw_sp-&gt;core)) {</div><div class='add'>+	case MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED:</div><div class='add'>+		return mlxsw_sp2_fids_init_ctl(mlxsw_sp);</div><div class='add'>+	case MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CFF:</div><div class='add'>+		return mlxsw_sp2_fids_init_cff(mlxsw_sp);</div><div class='add'>+	default:</div><div class='add'>+		WARN_ON_ONCE(1);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct mlxsw_sp_fid_core_ops mlxsw_sp2_fid_core_ops = {</div><div class='add'>+	.init = mlxsw_sp2_fids_init,</div><div class='add'>+	.fini = mlxsw_sp_fids_fini,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c<br/>index 82a95125d9ca..7164f9e6370f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c</a></div><div class='hunk'>@@ -8419,6 +8419,9 @@ mlxsw_sp_rif_create(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	rif-&gt;ops = ops;</div><div class='ctx'> 	rif-&gt;rif_entries = rif_entries;</div><div class='ctx'> </div><div class='add'>+	if (ops-&gt;setup)</div><div class='add'>+		ops-&gt;setup(rif, params);</div><div class='add'>+</div><div class='ctx'> 	if (ops-&gt;fid_get) {</div><div class='ctx'> 		fid = ops-&gt;fid_get(rif, params, extack);</div><div class='ctx'> 		if (IS_ERR(fid)) {</div><div class='hunk'>@@ -8428,9 +8431,6 @@ mlxsw_sp_rif_create(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 		rif-&gt;fid = fid;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ops-&gt;setup)</div><div class='del'>-		ops-&gt;setup(rif, params);</div><div class='del'>-</div><div class='ctx'> 	err = ops-&gt;configure(rif, extack);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_configure;</div><div class='hunk'>@@ -8660,6 +8660,20 @@ mlxsw_sp_rif_subport_rif(const struct mlxsw_sp_rif *rif)</div><div class='ctx'> 	return container_of(rif, struct mlxsw_sp_rif_subport, common);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int mlxsw_sp_rif_subport_port(const struct mlxsw_sp_rif *rif,</div><div class='add'>+			      u16 *port, bool *is_lag)</div><div class='add'>+{</div><div class='add'>+	struct mlxsw_sp_rif_subport *rif_subport;</div><div class='add'>+</div><div class='add'>+	if (WARN_ON(rif-&gt;ops-&gt;type != MLXSW_SP_RIF_TYPE_SUBPORT))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	rif_subport = mlxsw_sp_rif_subport_rif(rif);</div><div class='add'>+	*is_lag = rif_subport-&gt;lag;</div><div class='add'>+	*port = *is_lag ? rif_subport-&gt;lag_id : rif_subport-&gt;system_port;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static struct mlxsw_sp_rif *</div><div class='ctx'> mlxsw_sp_rif_subport_get(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 			 const struct mlxsw_sp_rif_params *params,</div><div class='hunk'>@@ -11458,6 +11472,13 @@ int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_register_netevent_notifier;</div><div class='ctx'> </div><div class='add'>+	mlxsw_sp-&gt;router-&gt;netdevice_nb.notifier_call =</div><div class='add'>+		mlxsw_sp_router_netdevice_event;</div><div class='add'>+	err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),</div><div class='add'>+					      &amp;mlxsw_sp-&gt;router-&gt;netdevice_nb);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err_register_netdev_notifier;</div><div class='add'>+</div><div class='ctx'> 	mlxsw_sp-&gt;router-&gt;nexthop_nb.notifier_call =</div><div class='ctx'> 		mlxsw_sp_nexthop_obj_event;</div><div class='ctx'> 	err = register_nexthop_notifier(mlxsw_sp_net(mlxsw_sp),</div><div class='hunk'>@@ -11473,22 +11494,15 @@ int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp,</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_register_fib_notifier;</div><div class='ctx'> </div><div class='del'>-	mlxsw_sp-&gt;router-&gt;netdevice_nb.notifier_call =</div><div class='del'>-		mlxsw_sp_router_netdevice_event;</div><div class='del'>-	err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),</div><div class='del'>-					      &amp;mlxsw_sp-&gt;router-&gt;netdevice_nb);</div><div class='del'>-	if (err)</div><div class='del'>-		goto err_register_netdev_notifier;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='del'>-err_register_netdev_notifier:</div><div class='del'>-	unregister_fib_notifier(mlxsw_sp_net(mlxsw_sp),</div><div class='del'>-				&amp;mlxsw_sp-&gt;router-&gt;fib_nb);</div><div class='ctx'> err_register_fib_notifier:</div><div class='ctx'> 	unregister_nexthop_notifier(mlxsw_sp_net(mlxsw_sp),</div><div class='ctx'> 				    &amp;mlxsw_sp-&gt;router-&gt;nexthop_nb);</div><div class='ctx'> err_register_nexthop_notifier:</div><div class='add'>+	unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),</div><div class='add'>+					  &amp;router-&gt;netdevice_nb);</div><div class='add'>+err_register_netdev_notifier:</div><div class='ctx'> 	unregister_netevent_notifier(&amp;mlxsw_sp-&gt;router-&gt;netevent_nb);</div><div class='ctx'> err_register_netevent_notifier:</div><div class='ctx'> 	unregister_inet6addr_validator_notifier(&amp;router-&gt;inet6addr_valid_nb);</div><div class='hunk'>@@ -11536,11 +11550,11 @@ void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp)</div><div class='ctx'> {</div><div class='ctx'> 	struct mlxsw_sp_router *router = mlxsw_sp-&gt;router;</div><div class='ctx'> </div><div class='del'>-	unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),</div><div class='del'>-					  &amp;router-&gt;netdevice_nb);</div><div class='ctx'> 	unregister_fib_notifier(mlxsw_sp_net(mlxsw_sp), &amp;router-&gt;fib_nb);</div><div class='ctx'> 	unregister_nexthop_notifier(mlxsw_sp_net(mlxsw_sp),</div><div class='ctx'> 				    &amp;router-&gt;nexthop_nb);</div><div class='add'>+	unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),</div><div class='add'>+					  &amp;router-&gt;netdevice_nb);</div><div class='ctx'> 	unregister_netevent_notifier(&amp;router-&gt;netevent_nb);</div><div class='ctx'> 	unregister_inet6addr_validator_notifier(&amp;router-&gt;inet6addr_valid_nb);</div><div class='ctx'> 	unregister_inetaddr_validator_notifier(&amp;router-&gt;inetaddr_valid_nb);</div><div class='head'>diff --git a/drivers/net/ethernet/micrel/ks8851.h b/drivers/net/ethernet/micrel/ks8851.h<br/>index fecd43754cea..e5ec0a363aff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/micrel/ks8851.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851.h</a></div><div class='hunk'>@@ -350,6 +350,8 @@ union ks8851_tx_hdr {</div><div class='ctx'>  * @rxd: Space for receiving SPI data, in DMA-able space.</div><div class='ctx'>  * @txd: Space for transmitting SPI data, in DMA-able space.</div><div class='ctx'>  * @msg_enable: The message flags controlling driver output (see ethtool).</div><div class='add'>+ * @tx_space: Free space in the hardware TX buffer (cached copy of KS_TXMIR).</div><div class='add'>+ * @queued_len: Space required in hardware TX buffer for queued packets in txq.</div><div class='ctx'>  * @fid: Incrementing frame id tag.</div><div class='ctx'>  * @rc_ier: Cached copy of KS_IER.</div><div class='ctx'>  * @rc_ccr: Cached copy of KS_CCR.</div><div class='hunk'>@@ -399,6 +401,7 @@ struct ks8851_net {</div><div class='ctx'> 	struct work_struct	rxctrl_work;</div><div class='ctx'> </div><div class='ctx'> 	struct sk_buff_head	txq;</div><div class='add'>+	unsigned int		queued_len;</div><div class='ctx'> </div><div class='ctx'> 	struct eeprom_93cx6	eeprom;</div><div class='ctx'> 	struct regulator	*vdd_reg;</div><div class='head'>diff --git a/drivers/net/ethernet/micrel/ks8851_common.c b/drivers/net/ethernet/micrel/ks8851_common.c<br/>index cfbc900d4aeb..0bf13b38b8f5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/micrel/ks8851_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851_common.c</a></div><div class='hunk'>@@ -362,16 +362,18 @@ static irqreturn_t ks8851_irq(int irq, void *_ks)</div><div class='ctx'> 		handled |= IRQ_RXPSI;</div><div class='ctx'> </div><div class='ctx'> 	if (status &amp; IRQ_TXI) {</div><div class='del'>-		handled |= IRQ_TXI;</div><div class='add'>+		unsigned short tx_space = ks8851_rdreg16(ks, KS_TXMIR);</div><div class='ctx'> </div><div class='del'>-		/* no lock here, tx queue should have been stopped */</div><div class='add'>+		netif_dbg(ks, intr, ks-&gt;netdev,</div><div class='add'>+			  "%s: txspace %d\n", __func__, tx_space);</div><div class='ctx'> </div><div class='del'>-		/* update our idea of how much tx space is available to the</div><div class='del'>-		 * system */</div><div class='del'>-		ks-&gt;tx_space = ks8851_rdreg16(ks, KS_TXMIR);</div><div class='add'>+		spin_lock(&amp;ks-&gt;statelock);</div><div class='add'>+		ks-&gt;tx_space = tx_space;</div><div class='add'>+		if (netif_queue_stopped(ks-&gt;netdev))</div><div class='add'>+			netif_wake_queue(ks-&gt;netdev);</div><div class='add'>+		spin_unlock(&amp;ks-&gt;statelock);</div><div class='ctx'> </div><div class='del'>-		netif_dbg(ks, intr, ks-&gt;netdev,</div><div class='del'>-			  "%s: txspace %d\n", __func__, ks-&gt;tx_space);</div><div class='add'>+		handled |= IRQ_TXI;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (status &amp; IRQ_RXI)</div><div class='hunk'>@@ -414,9 +416,6 @@ static irqreturn_t ks8851_irq(int irq, void *_ks)</div><div class='ctx'> 	if (status &amp; IRQ_LCI)</div><div class='ctx'> 		mii_check_link(&amp;ks-&gt;mii);</div><div class='ctx'> </div><div class='del'>-	if (status &amp; IRQ_TXI)</div><div class='del'>-		netif_wake_queue(ks-&gt;netdev);</div><div class='del'>-</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -500,6 +499,7 @@ static int ks8851_net_open(struct net_device *dev)</div><div class='ctx'> 	ks8851_wrreg16(ks, KS_ISR, ks-&gt;rc_ier);</div><div class='ctx'> 	ks8851_wrreg16(ks, KS_IER, ks-&gt;rc_ier);</div><div class='ctx'> </div><div class='add'>+	ks-&gt;queued_len = 0;</div><div class='ctx'> 	netif_start_queue(ks-&gt;netdev);</div><div class='ctx'> </div><div class='ctx'> 	netif_dbg(ks, ifup, ks-&gt;netdev, "network device up\n");</div><div class='head'>diff --git a/drivers/net/ethernet/micrel/ks8851_spi.c b/drivers/net/ethernet/micrel/ks8851_spi.c<br/>index 70bc7253454f..54f2eac11a63 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851_spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/micrel/ks8851_spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/micrel/ks8851_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/micrel/ks8851_spi.c</a></div><div class='hunk'>@@ -156,7 +156,7 @@ static void ks8851_rdreg(struct ks8851_net *ks, unsigned int op,</div><div class='ctx'> </div><div class='ctx'> 	txb[0] = cpu_to_le16(op | KS_SPIOP_RD);</div><div class='ctx'> </div><div class='del'>-	if (kss-&gt;spidev-&gt;master-&gt;flags &amp; SPI_MASTER_HALF_DUPLEX) {</div><div class='add'>+	if (kss-&gt;spidev-&gt;master-&gt;flags &amp; SPI_CONTROLLER_HALF_DUPLEX) {</div><div class='ctx'> 		msg = &amp;kss-&gt;spi_msg2;</div><div class='ctx'> 		xfer = kss-&gt;spi_xfer2;</div><div class='ctx'> </div><div class='hunk'>@@ -180,7 +180,7 @@ static void ks8851_rdreg(struct ks8851_net *ks, unsigned int op,</div><div class='ctx'> 	ret = spi_sync(kss-&gt;spidev, msg);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		netdev_err(ks-&gt;netdev, "read: spi_sync() failed\n");</div><div class='del'>-	else if (kss-&gt;spidev-&gt;master-&gt;flags &amp; SPI_MASTER_HALF_DUPLEX)</div><div class='add'>+	else if (kss-&gt;spidev-&gt;master-&gt;flags &amp; SPI_CONTROLLER_HALF_DUPLEX)</div><div class='ctx'> 		memcpy(rxb, trx, rxl);</div><div class='ctx'> 	else</div><div class='ctx'> 		memcpy(rxb, trx + 2, rxl);</div><div class='hunk'>@@ -287,6 +287,18 @@ static void ks8851_wrfifo_spi(struct ks8851_net *ks, struct sk_buff *txp,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * calc_txlen - calculate size of message to send packet</div><div class='add'>+ * @len: Length of data</div><div class='add'>+ *</div><div class='add'>+ * Returns the size of the TXFIFO message needed to send</div><div class='add'>+ * this packet.</div><div class='add'>+ */</div><div class='add'>+static unsigned int calc_txlen(unsigned int len)</div><div class='add'>+{</div><div class='add'>+	return ALIGN(len + 4, 4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * ks8851_rx_skb_spi - receive skbuff</div><div class='ctx'>  * @ks: The device state</div><div class='ctx'>  * @skb: The skbuff</div><div class='hunk'>@@ -305,7 +317,9 @@ static void ks8851_rx_skb_spi(struct ks8851_net *ks, struct sk_buff *skb)</div><div class='ctx'>  */</div><div class='ctx'> static void ks8851_tx_work(struct work_struct *work)</div><div class='ctx'> {</div><div class='add'>+	unsigned int dequeued_len = 0;</div><div class='ctx'> 	struct ks8851_net_spi *kss;</div><div class='add'>+	unsigned short tx_space;</div><div class='ctx'> 	struct ks8851_net *ks;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	struct sk_buff *txb;</div><div class='hunk'>@@ -322,6 +336,8 @@ static void ks8851_tx_work(struct work_struct *work)</div><div class='ctx'> 		last = skb_queue_empty(&amp;ks-&gt;txq);</div><div class='ctx'> </div><div class='ctx'> 		if (txb) {</div><div class='add'>+			dequeued_len += calc_txlen(txb-&gt;len);</div><div class='add'>+</div><div class='ctx'> 			ks8851_wrreg16_spi(ks, KS_RXQCR,</div><div class='ctx'> 					   ks-&gt;rc_rxqcr | RXQCR_SDA);</div><div class='ctx'> 			ks8851_wrfifo_spi(ks, txb, last);</div><div class='hunk'>@@ -332,6 +348,13 @@ static void ks8851_tx_work(struct work_struct *work)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	tx_space = ks8851_rdreg16_spi(ks, KS_TXMIR);</div><div class='add'>+</div><div class='add'>+	spin_lock(&amp;ks-&gt;statelock);</div><div class='add'>+	ks-&gt;queued_len -= dequeued_len;</div><div class='add'>+	ks-&gt;tx_space = tx_space;</div><div class='add'>+	spin_unlock(&amp;ks-&gt;statelock);</div><div class='add'>+</div><div class='ctx'> 	ks8851_unlock_spi(ks, &amp;flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -347,18 +370,6 @@ static void ks8851_flush_tx_work_spi(struct ks8851_net *ks)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * calc_txlen - calculate size of message to send packet</div><div class='del'>- * @len: Length of data</div><div class='del'>- *</div><div class='del'>- * Returns the size of the TXFIFO message needed to send</div><div class='del'>- * this packet.</div><div class='del'>- */</div><div class='del'>-static unsigned int calc_txlen(unsigned int len)</div><div class='del'>-{</div><div class='del'>-	return ALIGN(len + 4, 4);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ks8851_start_xmit_spi - transmit packet using SPI</div><div class='ctx'>  * @skb: The buffer to transmit</div><div class='ctx'>  * @dev: The device used to transmit the packet.</div><div class='hunk'>@@ -386,16 +397,17 @@ static netdev_tx_t ks8851_start_xmit_spi(struct sk_buff *skb,</div><div class='ctx'> </div><div class='ctx'> 	spin_lock(&amp;ks-&gt;statelock);</div><div class='ctx'> </div><div class='del'>-	if (needed &gt; ks-&gt;tx_space) {</div><div class='add'>+	if (ks-&gt;queued_len + needed &gt; ks-&gt;tx_space) {</div><div class='ctx'> 		netif_stop_queue(dev);</div><div class='ctx'> 		ret = NETDEV_TX_BUSY;</div><div class='ctx'> 	} else {</div><div class='del'>-		ks-&gt;tx_space -= needed;</div><div class='add'>+		ks-&gt;queued_len += needed;</div><div class='ctx'> 		skb_queue_tail(&amp;ks-&gt;txq, skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	spin_unlock(&amp;ks-&gt;statelock);</div><div class='del'>-	schedule_work(&amp;kss-&gt;tx_work);</div><div class='add'>+	if (ret == NETDEV_TX_OK)</div><div class='add'>+		schedule_work(&amp;kss-&gt;tx_work);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/microchip/lan743x_ethtool.c b/drivers/net/ethernet/microchip/lan743x_ethtool.c<br/>index 6961cfc55fb9..a2b3f4433ca8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/lan743x_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microchip/lan743x_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/lan743x_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/lan743x_ethtool.c</a></div><div class='hunk'>@@ -934,11 +934,11 @@ static u32 lan743x_ethtool_get_rxfh_indir_size(struct net_device *netdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int lan743x_ethtool_get_rxfh(struct net_device *netdev,</div><div class='del'>-				    u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+				    struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct lan743x_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		int dw_index;</div><div class='ctx'> 		int byte_index = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -947,17 +947,17 @@ static int lan743x_ethtool_get_rxfh(struct net_device *netdev,</div><div class='ctx'> 				lan743x_csr_read(adapter, RFE_INDX(dw_index));</div><div class='ctx'> </div><div class='ctx'> 			byte_index = dw_index &lt;&lt; 2;</div><div class='del'>-			indir[byte_index + 0] =</div><div class='add'>+			rxfh-&gt;indir[byte_index + 0] =</div><div class='ctx'> 				((four_entries &gt;&gt; 0) &amp; 0x000000FF);</div><div class='del'>-			indir[byte_index + 1] =</div><div class='add'>+			rxfh-&gt;indir[byte_index + 1] =</div><div class='ctx'> 				((four_entries &gt;&gt; 8) &amp; 0x000000FF);</div><div class='del'>-			indir[byte_index + 2] =</div><div class='add'>+			rxfh-&gt;indir[byte_index + 2] =</div><div class='ctx'> 				((four_entries &gt;&gt; 16) &amp; 0x000000FF);</div><div class='del'>-			indir[byte_index + 3] =</div><div class='add'>+			rxfh-&gt;indir[byte_index + 3] =</div><div class='ctx'> 				((four_entries &gt;&gt; 24) &amp; 0x000000FF);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (key) {</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='ctx'> 		int dword_index;</div><div class='ctx'> 		int byte_index = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -967,28 +967,30 @@ static int lan743x_ethtool_get_rxfh(struct net_device *netdev,</div><div class='ctx'> 						 RFE_HASH_KEY(dword_index));</div><div class='ctx'> </div><div class='ctx'> 			byte_index = dword_index &lt;&lt; 2;</div><div class='del'>-			key[byte_index + 0] =</div><div class='add'>+			rxfh-&gt;key[byte_index + 0] =</div><div class='ctx'> 				((four_entries &gt;&gt; 0) &amp; 0x000000FF);</div><div class='del'>-			key[byte_index + 1] =</div><div class='add'>+			rxfh-&gt;key[byte_index + 1] =</div><div class='ctx'> 				((four_entries &gt;&gt; 8) &amp; 0x000000FF);</div><div class='del'>-			key[byte_index + 2] =</div><div class='add'>+			rxfh-&gt;key[byte_index + 2] =</div><div class='ctx'> 				((four_entries &gt;&gt; 16) &amp; 0x000000FF);</div><div class='del'>-			key[byte_index + 3] =</div><div class='add'>+			rxfh-&gt;key[byte_index + 3] =</div><div class='ctx'> 				((four_entries &gt;&gt; 24) &amp; 0x000000FF);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='del'>-	if (hfunc)</div><div class='del'>-		(*hfunc) = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int lan743x_ethtool_set_rxfh(struct net_device *netdev,</div><div class='del'>-				    const u32 *indir, const u8 *key,</div><div class='del'>-				    const u8 hfunc)</div><div class='add'>+				    struct ethtool_rxfh_param *rxfh,</div><div class='add'>+				    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct lan743x_adapter *adapter = netdev_priv(netdev);</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	if (indir) {</div><div class='hunk'>@@ -1075,7 +1077,6 @@ static int lan743x_ethtool_get_eee(struct net_device *netdev,</div><div class='ctx'> 	buf = lan743x_csr_read(adapter, MAC_CR);</div><div class='ctx'> 	if (buf &amp; MAC_CR_EEE_EN_) {</div><div class='ctx'> 		eee-&gt;eee_enabled = true;</div><div class='del'>-		eee-&gt;eee_active = !!(eee-&gt;advertised &amp; eee-&gt;lp_advertised);</div><div class='ctx'> 		eee-&gt;tx_lpi_enabled = true;</div><div class='ctx'> 		/* EEE_TX_LPI_REQ_DLY &amp; tx_lpi_timer are same uSec unit */</div><div class='ctx'> 		buf = lan743x_csr_read(adapter, MAC_EEE_TX_LPI_REQ_DLY_CNT);</div><div class='head'>diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h<br/>index b648461787d2..be79cb0ae5af 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/lan743x_main.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microchip/lan743x_main.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/lan743x_main.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/lan743x_main.h</a></div><div class='hunk'>@@ -1075,7 +1075,7 @@ struct lan743x_adapter {</div><div class='ctx'> #define DMA_DESCRIPTOR_SPACING_32       (32)</div><div class='ctx'> #define DMA_DESCRIPTOR_SPACING_64       (64)</div><div class='ctx'> #define DMA_DESCRIPTOR_SPACING_128      (128)</div><div class='del'>-#define DEFAULT_DMA_DESCRIPTOR_SPACING  (L1_CACHE_BYTES)</div><div class='add'>+#define DEFAULT_DMA_DESCRIPTOR_SPACING  (DMA_DESCRIPTOR_SPACING_16)</div><div class='ctx'> </div><div class='ctx'> #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \</div><div class='ctx'> 	(((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))</div><div class='head'>diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c<br/>index 37d2584b48a7..a06dc5a9b355 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c</a></div><div class='hunk'>@@ -1012,7 +1012,7 @@ static void sparx5_get_sset_strings(struct net_device *ndev, u32 sset, u8 *data)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	for (idx = 0; idx &lt; sparx5-&gt;num_ethtool_stats; idx++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", sparx5-&gt;stats_layout[idx]);</div><div class='add'>+		ethtool_puts(&amp;data, sparx5-&gt;stats_layout[idx]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sparx5_get_sset_data(struct net_device *ndev,</div><div class='head'>diff --git a/drivers/net/ethernet/microsoft/Kconfig b/drivers/net/ethernet/microsoft/Kconfig<br/>index 090e6b983243..01eb7445ead9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microsoft/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/Kconfig</a></div><div class='hunk'>@@ -20,6 +20,7 @@ config MICROSOFT_MANA</div><div class='ctx'> 	depends on PCI_MSI &amp;&amp; X86_64</div><div class='ctx'> 	depends on PCI_HYPERV</div><div class='ctx'> 	select AUXILIARY_BUS</div><div class='add'>+	select PAGE_POOL</div><div class='ctx'> 	help</div><div class='ctx'> 	  This driver supports Microsoft Azure Network Adapter (MANA).</div><div class='ctx'> 	  So far, the driver is only supported on X86_64.</div><div class='head'>diff --git a/drivers/net/ethernet/microsoft/mana/gdma_main.c b/drivers/net/ethernet/microsoft/mana/gdma_main.c<br/>index 6367de0c2c2e..d33b27214539 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/gdma_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microsoft/mana/gdma_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/gdma_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/gdma_main.c</a></div><div class='hunk'>@@ -158,6 +158,9 @@ static int mana_gd_detect_devices(struct pci_dev *pdev)</div><div class='ctx'> 		if (dev_type == GDMA_DEVICE_MANA) {</div><div class='ctx'> 			gc-&gt;mana.gdma_context = gc;</div><div class='ctx'> 			gc-&gt;mana.dev_id = dev;</div><div class='add'>+		} else if (dev_type == GDMA_DEVICE_MANA_IB) {</div><div class='add'>+			gc-&gt;mana_ib.dev_id = dev;</div><div class='add'>+			gc-&gt;mana_ib.gdma_context = gc;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -414,8 +417,12 @@ static void mana_gd_process_eq_events(void *arg)</div><div class='ctx'> </div><div class='ctx'> 		old_bits = (eq-&gt;head / num_eqe - 1) &amp; GDMA_EQE_OWNER_MASK;</div><div class='ctx'> 		/* No more entries */</div><div class='del'>-		if (owner_bits == old_bits)</div><div class='add'>+		if (owner_bits == old_bits) {</div><div class='add'>+			/* return here without ringing the doorbell */</div><div class='add'>+			if (i == 0)</div><div class='add'>+				return;</div><div class='ctx'> 			break;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		new_bits = (eq-&gt;head / num_eqe) &amp; GDMA_EQE_OWNER_MASK;</div><div class='ctx'> 		if (owner_bits != new_bits) {</div><div class='hunk'>@@ -445,42 +452,29 @@ static int mana_gd_register_irq(struct gdma_queue *queue,</div><div class='ctx'> 	struct gdma_dev *gd = queue-&gt;gdma_dev;</div><div class='ctx'> 	struct gdma_irq_context *gic;</div><div class='ctx'> 	struct gdma_context *gc;</div><div class='del'>-	struct gdma_resource *r;</div><div class='ctx'> 	unsigned int msi_index;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	struct device *dev;</div><div class='ctx'> 	int err = 0;</div><div class='ctx'> </div><div class='ctx'> 	gc = gd-&gt;gdma_context;</div><div class='del'>-	r = &amp;gc-&gt;msix_resource;</div><div class='ctx'> 	dev = gc-&gt;dev;</div><div class='add'>+	msi_index = spec-&gt;eq.msix_index;</div><div class='ctx'> </div><div class='del'>-	spin_lock_irqsave(&amp;r-&gt;lock, flags);</div><div class='del'>-</div><div class='del'>-	msi_index = find_first_zero_bit(r-&gt;map, r-&gt;size);</div><div class='del'>-	if (msi_index &gt;= r-&gt;size || msi_index &gt;= gc-&gt;num_msix_usable) {</div><div class='add'>+	if (msi_index &gt;= gc-&gt;num_msix_usable) {</div><div class='ctx'> 		err = -ENOSPC;</div><div class='del'>-	} else {</div><div class='del'>-		bitmap_set(r-&gt;map, msi_index, 1);</div><div class='del'>-		queue-&gt;eq.msix_index = msi_index;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;r-&gt;lock, flags);</div><div class='del'>-</div><div class='del'>-	if (err) {</div><div class='del'>-		dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u",</div><div class='del'>-			err, msi_index, r-&gt;size, gc-&gt;num_msix_usable);</div><div class='add'>+		dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u",</div><div class='add'>+			err, msi_index, gc-&gt;num_msix_usable);</div><div class='ctx'> </div><div class='ctx'> 		return err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	queue-&gt;eq.msix_index = msi_index;</div><div class='ctx'> 	gic = &amp;gc-&gt;irq_contexts[msi_index];</div><div class='ctx'> </div><div class='del'>-	WARN_ON(gic-&gt;handler || gic-&gt;arg);</div><div class='del'>-</div><div class='del'>-	gic-&gt;arg = queue;</div><div class='del'>-</div><div class='del'>-	gic-&gt;handler = mana_gd_process_eq_events;</div><div class='add'>+	spin_lock_irqsave(&amp;gic-&gt;lock, flags);</div><div class='add'>+	list_add_rcu(&amp;queue-&gt;entry, &amp;gic-&gt;eq_list);</div><div class='add'>+	spin_unlock_irqrestore(&amp;gic-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -490,12 +484,11 @@ static void mana_gd_deregiser_irq(struct gdma_queue *queue)</div><div class='ctx'> 	struct gdma_dev *gd = queue-&gt;gdma_dev;</div><div class='ctx'> 	struct gdma_irq_context *gic;</div><div class='ctx'> 	struct gdma_context *gc;</div><div class='del'>-	struct gdma_resource *r;</div><div class='ctx'> 	unsigned int msix_index;</div><div class='ctx'> 	unsigned long flags;</div><div class='add'>+	struct gdma_queue *eq;</div><div class='ctx'> </div><div class='ctx'> 	gc = gd-&gt;gdma_context;</div><div class='del'>-	r = &amp;gc-&gt;msix_resource;</div><div class='ctx'> </div><div class='ctx'> 	/* At most num_online_cpus() + 1 interrupts are used. */</div><div class='ctx'> 	msix_index = queue-&gt;eq.msix_index;</div><div class='hunk'>@@ -503,14 +496,17 @@ static void mana_gd_deregiser_irq(struct gdma_queue *queue)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	gic = &amp;gc-&gt;irq_contexts[msix_index];</div><div class='del'>-	gic-&gt;handler = NULL;</div><div class='del'>-	gic-&gt;arg = NULL;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;r-&gt;lock, flags);</div><div class='del'>-	bitmap_clear(r-&gt;map, msix_index, 1);</div><div class='del'>-	spin_unlock_irqrestore(&amp;r-&gt;lock, flags);</div><div class='add'>+	spin_lock_irqsave(&amp;gic-&gt;lock, flags);</div><div class='add'>+	list_for_each_entry_rcu(eq, &amp;gic-&gt;eq_list, entry) {</div><div class='add'>+		if (queue == eq) {</div><div class='add'>+			list_del_rcu(&amp;eq-&gt;entry);</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	spin_unlock_irqrestore(&amp;gic-&gt;lock, flags);</div><div class='ctx'> </div><div class='ctx'> 	queue-&gt;eq.msix_index = INVALID_PCI_MSIX_INDEX;</div><div class='add'>+	synchronize_rcu();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq)</div><div class='hunk'>@@ -588,6 +584,7 @@ static int mana_gd_create_eq(struct gdma_dev *gd,</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	queue-&gt;eq.msix_index = INVALID_PCI_MSIX_INDEX;</div><div class='add'>+	queue-&gt;id = INVALID_QUEUE_ID;</div><div class='ctx'> </div><div class='ctx'> 	log2_num_entries = ilog2(queue-&gt;queue_size / GDMA_EQE_SIZE);</div><div class='ctx'> </div><div class='hunk'>@@ -819,6 +816,7 @@ free_q:</div><div class='ctx'> 	kfree(queue);</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, NET_MANA);</div><div class='ctx'> </div><div class='ctx'> int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,</div><div class='ctx'> 			      const struct gdma_queue_spec *spec,</div><div class='hunk'>@@ -895,6 +893,7 @@ void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)</div><div class='ctx'> 	mana_gd_free_memory(gmi);</div><div class='ctx'> 	kfree(queue);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS(mana_gd_destroy_queue, NET_MANA);</div><div class='ctx'> </div><div class='ctx'> int mana_gd_verify_vf_version(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='hunk'>@@ -971,6 +970,7 @@ int mana_gd_register_device(struct gdma_dev *gd)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS(mana_gd_register_device, NET_MANA);</div><div class='ctx'> </div><div class='ctx'> int mana_gd_deregister_device(struct gdma_dev *gd)</div><div class='ctx'> {</div><div class='hunk'>@@ -1001,6 +1001,7 @@ int mana_gd_deregister_device(struct gdma_dev *gd)</div><div class='ctx'> </div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_NS(mana_gd_deregister_device, NET_MANA);</div><div class='ctx'> </div><div class='ctx'> u32 mana_gd_wq_avail_space(struct gdma_queue *wq)</div><div class='ctx'> {</div><div class='hunk'>@@ -1217,9 +1218,14 @@ int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe)</div><div class='ctx'> static irqreturn_t mana_gd_intr(int irq, void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct gdma_irq_context *gic = arg;</div><div class='add'>+	struct list_head *eq_list = &amp;gic-&gt;eq_list;</div><div class='add'>+	struct gdma_queue *eq;</div><div class='ctx'> </div><div class='del'>-	if (gic-&gt;handler)</div><div class='del'>-		gic-&gt;handler(gic-&gt;arg);</div><div class='add'>+	rcu_read_lock();</div><div class='add'>+	list_for_each_entry_rcu(eq, eq_list, entry) {</div><div class='add'>+		gic-&gt;handler(eq);</div><div class='add'>+	}</div><div class='add'>+	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='hunk'>@@ -1271,8 +1277,9 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; nvec; i++) {</div><div class='ctx'> 		gic = &amp;gc-&gt;irq_contexts[i];</div><div class='del'>-		gic-&gt;handler = NULL;</div><div class='del'>-		gic-&gt;arg = NULL;</div><div class='add'>+		gic-&gt;handler = mana_gd_process_eq_events;</div><div class='add'>+		INIT_LIST_HEAD(&amp;gic-&gt;eq_list);</div><div class='add'>+		spin_lock_init(&amp;gic-&gt;lock);</div><div class='ctx'> </div><div class='ctx'> 		if (!i)</div><div class='ctx'> 			snprintf(gic-&gt;name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s",</div><div class='hunk'>@@ -1295,10 +1302,6 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev)</div><div class='ctx'> 		irq_set_affinity_and_hint(irq, cpumask_of(cpu));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = mana_gd_alloc_res_map(nvec, &amp;gc-&gt;msix_resource);</div><div class='del'>-	if (err)</div><div class='del'>-		goto free_irq;</div><div class='del'>-</div><div class='ctx'> 	gc-&gt;max_num_msix = nvec;</div><div class='ctx'> 	gc-&gt;num_msix_usable = nvec;</div><div class='ctx'> </div><div class='hunk'>@@ -1329,8 +1332,6 @@ static void mana_gd_remove_irqs(struct pci_dev *pdev)</div><div class='ctx'> 	if (gc-&gt;max_num_msix &lt; 1)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	mana_gd_free_res_map(&amp;gc-&gt;msix_resource);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; gc-&gt;max_num_msix; i++) {</div><div class='ctx'> 		irq = pci_irq_vector(pdev, i);</div><div class='ctx'> 		if (irq &lt; 0)</div><div class='head'>diff --git a/drivers/net/ethernet/microsoft/mana/hw_channel.c b/drivers/net/ethernet/microsoft/mana/hw_channel.c<br/>index 9d1cd3bfcf66..2729a2c5acf9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/hw_channel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microsoft/mana/hw_channel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/hw_channel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/hw_channel.c</a></div><div class='hunk'>@@ -300,6 +300,7 @@ static int mana_hwc_create_gdma_eq(struct hw_channel_context *hwc,</div><div class='ctx'> 	spec.eq.context = ctx;</div><div class='ctx'> 	spec.eq.callback = cb;</div><div class='ctx'> 	spec.eq.log2_throttle_limit = DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ;</div><div class='add'>+	spec.eq.msix_index = 0;</div><div class='ctx'> </div><div class='ctx'> 	return mana_gd_create_hwc_queue(hwc-&gt;gdma_dev, &amp;spec, queue);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/microsoft/mana/mana_en.c b/drivers/net/ethernet/microsoft/mana/mana_en.c<br/>index fc3d2903a80f..59287c6e6cee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/mana_en.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microsoft/mana/mana_en.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/mana_en.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/mana_en.c</a></div><div class='hunk'>@@ -1244,6 +1244,7 @@ static int mana_create_eq(struct mana_context *ac)</div><div class='ctx'> 	spec.eq.log2_throttle_limit = LOG2_EQ_THROTTLE;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; gc-&gt;max_num_queues; i++) {</div><div class='add'>+		spec.eq.msix_index = (i + 1) % gc-&gt;num_msix_usable;</div><div class='ctx'> 		err = mana_gd_create_mana_eq(gd, &amp;spec, &amp;ac-&gt;eqs[i].eq);</div><div class='ctx'> 		if (err)</div><div class='ctx'> 			goto out;</div><div class='hunk'>@@ -2137,6 +2138,7 @@ static int mana_create_page_pool(struct mana_rxq *rxq, struct gdma_context *gc)</div><div class='ctx'> 	pprm.pool_size = RX_BUFFERS_PER_QUEUE;</div><div class='ctx'> 	pprm.nid = gc-&gt;numa_node;</div><div class='ctx'> 	pprm.napi = &amp;rxq-&gt;rx_cq.napi;</div><div class='add'>+	pprm.netdev = rxq-&gt;ndev;</div><div class='ctx'> </div><div class='ctx'> 	rxq-&gt;page_pool = page_pool_create(&amp;pprm);</div><div class='ctx'> </div><div class='hunk'>@@ -2385,13 +2387,33 @@ void mana_query_gf_stats(struct mana_port_context *apc)</div><div class='ctx'> </div><div class='ctx'> 	mana_gd_init_req_hdr(&amp;req.hdr, MANA_QUERY_GF_STAT,</div><div class='ctx'> 			     sizeof(req), sizeof(resp));</div><div class='del'>-	req.req_stats = STATISTICS_FLAGS_HC_TX_BYTES |</div><div class='add'>+	req.req_stats = STATISTICS_FLAGS_RX_DISCARDS_NO_WQE |</div><div class='add'>+			STATISTICS_FLAGS_RX_ERRORS_VPORT_DISABLED |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_BYTES |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_UCAST_PACKETS |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_UCAST_BYTES |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_MCAST_PACKETS |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_MCAST_BYTES |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_BCAST_PACKETS |</div><div class='add'>+			STATISTICS_FLAGS_HC_RX_BCAST_BYTES |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_GF_DISABLED |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_VPORT_DISABLED |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_INVAL_VPORT_OFFSET_PACKETS |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_VLAN_ENFORCEMENT |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_ETH_TYPE_ENFORCEMENT |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_SA_ENFORCEMENT |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_SQPDID_ENFORCEMENT |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_CQPDID_ENFORCEMENT |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_MTU_VIOLATION |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_INVALID_OOB |</div><div class='add'>+			STATISTICS_FLAGS_HC_TX_BYTES |</div><div class='ctx'> 			STATISTICS_FLAGS_HC_TX_UCAST_PACKETS |</div><div class='ctx'> 			STATISTICS_FLAGS_HC_TX_UCAST_BYTES |</div><div class='ctx'> 			STATISTICS_FLAGS_HC_TX_MCAST_PACKETS |</div><div class='ctx'> 			STATISTICS_FLAGS_HC_TX_MCAST_BYTES |</div><div class='ctx'> 			STATISTICS_FLAGS_HC_TX_BCAST_PACKETS |</div><div class='del'>-			STATISTICS_FLAGS_HC_TX_BCAST_BYTES;</div><div class='add'>+			STATISTICS_FLAGS_HC_TX_BCAST_BYTES |</div><div class='add'>+			STATISTICS_FLAGS_TX_ERRORS_GDMA_ERROR;</div><div class='ctx'> </div><div class='ctx'> 	err = mana_send_request(apc-&gt;ac, &amp;req, sizeof(req), &amp;resp,</div><div class='ctx'> 				sizeof(resp));</div><div class='hunk'>@@ -2407,6 +2429,30 @@ void mana_query_gf_stats(struct mana_port_context *apc)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	apc-&gt;eth_stats.hc_rx_discards_no_wqe = resp.rx_discards_nowqe;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_err_vport_disabled = resp.rx_err_vport_disabled;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_bytes = resp.hc_rx_bytes;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_ucast_pkts = resp.hc_rx_ucast_pkts;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_ucast_bytes = resp.hc_rx_ucast_bytes;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_bcast_pkts = resp.hc_rx_bcast_pkts;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_bcast_bytes = resp.hc_rx_bcast_bytes;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_mcast_pkts = resp.hc_rx_mcast_pkts;</div><div class='add'>+	apc-&gt;eth_stats.hc_rx_mcast_bytes = resp.hc_rx_mcast_bytes;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_gf_disabled = resp.tx_err_gf_disabled;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_vport_disabled = resp.tx_err_vport_disabled;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_inval_vportoffset_pkt =</div><div class='add'>+					     resp.tx_err_inval_vport_offset_pkt;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_vlan_enforcement =</div><div class='add'>+					     resp.tx_err_vlan_enforcement;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_eth_type_enforcement =</div><div class='add'>+					     resp.tx_err_ethtype_enforcement;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_sa_enforcement = resp.tx_err_SA_enforcement;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_sqpdid_enforcement =</div><div class='add'>+					     resp.tx_err_SQPDID_enforcement;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_cqpdid_enforcement =</div><div class='add'>+					     resp.tx_err_CQPDID_enforcement;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_mtu_violation = resp.tx_err_mtu_violation;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_inval_oob = resp.tx_err_inval_oob;</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_bytes = resp.hc_tx_bytes;</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_ucast_pkts = resp.hc_tx_ucast_pkts;</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_ucast_bytes = resp.hc_tx_ucast_bytes;</div><div class='hunk'>@@ -2414,6 +2460,7 @@ void mana_query_gf_stats(struct mana_port_context *apc)</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_bcast_bytes = resp.hc_tx_bcast_bytes;</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_mcast_pkts = resp.hc_tx_mcast_pkts;</div><div class='ctx'> 	apc-&gt;eth_stats.hc_tx_mcast_bytes = resp.hc_tx_mcast_bytes;</div><div class='add'>+	apc-&gt;eth_stats.hc_tx_err_gdma = resp.tx_err_gdma;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mana_init_port(struct net_device *ndev)</div><div class='head'>diff --git a/drivers/net/ethernet/microsoft/mana/mana_ethtool.c b/drivers/net/ethernet/microsoft/mana/mana_ethtool.c<br/>index 607150165ab4..ab2413d71f6c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/mana_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/microsoft/mana/mana_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/microsoft/mana/mana_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/microsoft/mana/mana_ethtool.c</a></div><div class='hunk'>@@ -13,6 +13,46 @@ static const struct {</div><div class='ctx'> } mana_eth_stats[] = {</div><div class='ctx'> 	{"stop_queue", offsetof(struct mana_ethtool_stats, stop_queue)},</div><div class='ctx'> 	{"wake_queue", offsetof(struct mana_ethtool_stats, wake_queue)},</div><div class='add'>+	{"hc_rx_discards_no_wqe", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					   hc_rx_discards_no_wqe)},</div><div class='add'>+	{"hc_rx_err_vport_disabled", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					      hc_rx_err_vport_disabled)},</div><div class='add'>+	{"hc_rx_bytes", offsetof(struct mana_ethtool_stats, hc_rx_bytes)},</div><div class='add'>+	{"hc_rx_ucast_pkts", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				      hc_rx_ucast_pkts)},</div><div class='add'>+	{"hc_rx_ucast_bytes", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				       hc_rx_ucast_bytes)},</div><div class='add'>+	{"hc_rx_bcast_pkts", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				      hc_rx_bcast_pkts)},</div><div class='add'>+	{"hc_rx_bcast_bytes", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				       hc_rx_bcast_bytes)},</div><div class='add'>+	{"hc_rx_mcast_pkts", offsetof(struct mana_ethtool_stats,</div><div class='add'>+			hc_rx_mcast_pkts)},</div><div class='add'>+	{"hc_rx_mcast_bytes", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				       hc_rx_mcast_bytes)},</div><div class='add'>+	{"hc_tx_err_gf_disabled", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					   hc_tx_err_gf_disabled)},</div><div class='add'>+	{"hc_tx_err_vport_disabled", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					      hc_tx_err_vport_disabled)},</div><div class='add'>+	{"hc_tx_err_inval_vportoffset_pkt",</div><div class='add'>+	 offsetof(struct mana_ethtool_stats,</div><div class='add'>+		  hc_tx_err_inval_vportoffset_pkt)},</div><div class='add'>+	{"hc_tx_err_vlan_enforcement", offsetof(struct mana_ethtool_stats,</div><div class='add'>+						hc_tx_err_vlan_enforcement)},</div><div class='add'>+	{"hc_tx_err_eth_type_enforcement",</div><div class='add'>+	 offsetof(struct mana_ethtool_stats, hc_tx_err_eth_type_enforcement)},</div><div class='add'>+	{"hc_tx_err_sa_enforcement", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					      hc_tx_err_sa_enforcement)},</div><div class='add'>+	{"hc_tx_err_sqpdid_enforcement",</div><div class='add'>+	 offsetof(struct mana_ethtool_stats, hc_tx_err_sqpdid_enforcement)},</div><div class='add'>+	{"hc_tx_err_cqpdid_enforcement",</div><div class='add'>+	 offsetof(struct mana_ethtool_stats, hc_tx_err_cqpdid_enforcement)},</div><div class='add'>+	{"hc_tx_err_mtu_violation", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					     hc_tx_err_mtu_violation)},</div><div class='add'>+	{"hc_tx_err_inval_oob", offsetof(struct mana_ethtool_stats,</div><div class='add'>+					 hc_tx_err_inval_oob)},</div><div class='add'>+	{"hc_tx_err_gdma", offsetof(struct mana_ethtool_stats,</div><div class='add'>+				    hc_tx_err_gdma)},</div><div class='ctx'> 	{"hc_tx_bytes", offsetof(struct mana_ethtool_stats, hc_tx_bytes)},</div><div class='ctx'> 	{"hc_tx_ucast_pkts", offsetof(struct mana_ethtool_stats,</div><div class='ctx'> 					hc_tx_ucast_pkts)},</div><div class='hunk'>@@ -208,28 +248,28 @@ static u32 mana_rss_indir_size(struct net_device *ndev)</div><div class='ctx'> 	return MANA_INDIRECT_TABLE_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mana_get_rxfh(struct net_device *ndev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='add'>+static int mana_get_rxfh(struct net_device *ndev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct mana_port_context *apc = netdev_priv(ndev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; MANA_INDIRECT_TABLE_SIZE; i++)</div><div class='del'>-			indir[i] = apc-&gt;indir_table[i];</div><div class='add'>+			rxfh-&gt;indir[i] = apc-&gt;indir_table[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, apc-&gt;hashkey, MANA_HASH_KEY_SIZE);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, apc-&gt;hashkey, MANA_HASH_KEY_SIZE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mana_set_rxfh(struct net_device *ndev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int mana_set_rxfh(struct net_device *ndev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct mana_port_context *apc = netdev_priv(ndev);</div><div class='ctx'> 	bool update_hash = false, update_table = false;</div><div class='hunk'>@@ -240,25 +280,26 @@ static int mana_set_rxfh(struct net_device *ndev, const u32 *indir,</div><div class='ctx'> 	if (!apc-&gt;port_is_up)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; MANA_INDIRECT_TABLE_SIZE; i++)</div><div class='del'>-			if (indir[i] &gt;= apc-&gt;num_queues)</div><div class='add'>+			if (rxfh-&gt;indir[i] &gt;= apc-&gt;num_queues)</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		update_table = true;</div><div class='ctx'> 		for (i = 0; i &lt; MANA_INDIRECT_TABLE_SIZE; i++) {</div><div class='ctx'> 			save_table[i] = apc-&gt;indir_table[i];</div><div class='del'>-			apc-&gt;indir_table[i] = indir[i];</div><div class='add'>+			apc-&gt;indir_table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='ctx'> 		update_hash = true;</div><div class='ctx'> 		memcpy(save_key, apc-&gt;hashkey, MANA_HASH_KEY_SIZE);</div><div class='del'>-		memcpy(apc-&gt;hashkey, key, MANA_HASH_KEY_SIZE);</div><div class='add'>+		memcpy(apc-&gt;hashkey, rxfh-&gt;key, MANA_HASH_KEY_SIZE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	err = mana_config_rss(apc, TRI_STATE_TRUE, update_hash, update_table);</div><div class='head'>diff --git a/drivers/net/ethernet/mscc/ocelot_stats.c b/drivers/net/ethernet/mscc/ocelot_stats.c<br/>index 5c55197c7327..c018783757fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mscc/ocelot_stats.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/mscc/ocelot_stats.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/mscc/ocelot_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/mscc/ocelot_stats.c</a></div><div class='hunk'>@@ -582,10 +582,10 @@ static void ocelot_port_rmon_stats_cb(struct ocelot *ocelot, int port, void *pri</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[0] = s[OCELOT_STAT_TX_64];</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[1] = s[OCELOT_STAT_TX_65_127];</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[2] = s[OCELOT_STAT_TX_128_255];</div><div class='del'>-	rmon_stats-&gt;hist_tx[3] = s[OCELOT_STAT_TX_128_255];</div><div class='del'>-	rmon_stats-&gt;hist_tx[4] = s[OCELOT_STAT_TX_256_511];</div><div class='del'>-	rmon_stats-&gt;hist_tx[5] = s[OCELOT_STAT_TX_512_1023];</div><div class='del'>-	rmon_stats-&gt;hist_tx[6] = s[OCELOT_STAT_TX_1024_1526];</div><div class='add'>+	rmon_stats-&gt;hist_tx[3] = s[OCELOT_STAT_TX_256_511];</div><div class='add'>+	rmon_stats-&gt;hist_tx[4] = s[OCELOT_STAT_TX_512_1023];</div><div class='add'>+	rmon_stats-&gt;hist_tx[5] = s[OCELOT_STAT_TX_1024_1526];</div><div class='add'>+	rmon_stats-&gt;hist_tx[6] = s[OCELOT_STAT_TX_1527_MAX];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ocelot_port_pmac_rmon_stats_cb(struct ocelot *ocelot, int port,</div><div class='hunk'>@@ -610,10 +610,10 @@ static void ocelot_port_pmac_rmon_stats_cb(struct ocelot *ocelot, int port,</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[0] = s[OCELOT_STAT_TX_PMAC_64];</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[1] = s[OCELOT_STAT_TX_PMAC_65_127];</div><div class='ctx'> 	rmon_stats-&gt;hist_tx[2] = s[OCELOT_STAT_TX_PMAC_128_255];</div><div class='del'>-	rmon_stats-&gt;hist_tx[3] = s[OCELOT_STAT_TX_PMAC_128_255];</div><div class='del'>-	rmon_stats-&gt;hist_tx[4] = s[OCELOT_STAT_TX_PMAC_256_511];</div><div class='del'>-	rmon_stats-&gt;hist_tx[5] = s[OCELOT_STAT_TX_PMAC_512_1023];</div><div class='del'>-	rmon_stats-&gt;hist_tx[6] = s[OCELOT_STAT_TX_PMAC_1024_1526];</div><div class='add'>+	rmon_stats-&gt;hist_tx[3] = s[OCELOT_STAT_TX_PMAC_256_511];</div><div class='add'>+	rmon_stats-&gt;hist_tx[4] = s[OCELOT_STAT_TX_PMAC_512_1023];</div><div class='add'>+	rmon_stats-&gt;hist_tx[5] = s[OCELOT_STAT_TX_PMAC_1024_1526];</div><div class='add'>+	rmon_stats-&gt;hist_tx[6] = s[OCELOT_STAT_TX_PMAC_1527_MAX];</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port,</div><div class='head'>diff --git a/drivers/net/ethernet/neterion/s2io.c b/drivers/net/ethernet/neterion/s2io.c<br/>index 61d8bfd12d5f..55408f16fbbc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/neterion/s2io.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/neterion/s2io.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/neterion/s2io.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/neterion/s2io.c</a></div><div class='hunk'>@@ -414,6 +414,7 @@ static const u64 fix_mac[] = {</div><div class='ctx'> 	END_SIGN</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("Neterion 10GbE driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_VERSION(DRV_VERSION);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/flower/lag_conf.c b/drivers/net/ethernet/netronome/nfp/flower/lag_conf.c<br/>index 88d6d992e7d0..361d7c495e2d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/flower/lag_conf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/flower/lag_conf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/flower/lag_conf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/flower/lag_conf.c</a></div><div class='hunk'>@@ -76,7 +76,7 @@ struct nfp_fl_lag_group {</div><div class='ctx'> /* Use this ID with zero members to ack a batch config */</div><div class='ctx'> #define NFP_FL_LAG_SYNC_ID		0</div><div class='ctx'> #define NFP_FL_LAG_GROUP_MIN		1 /* ID 0 reserved */</div><div class='del'>-#define NFP_FL_LAG_GROUP_MAX		32 /* IDs 1 to 31 are valid */</div><div class='add'>+#define NFP_FL_LAG_GROUP_MAX		31 /* IDs 1 to 31 are valid */</div><div class='ctx'> </div><div class='ctx'> /* wait for more config */</div><div class='ctx'> #define NFP_FL_LAG_DELAY		(msecs_to_jiffies(2))</div><div class='hunk'>@@ -111,8 +111,8 @@ nfp_fl_lag_group_create(struct nfp_fl_lag *lag, struct net_device *master)</div><div class='ctx'> </div><div class='ctx'> 	priv = container_of(lag, struct nfp_flower_priv, nfp_lag);</div><div class='ctx'> </div><div class='del'>-	id = ida_simple_get(&amp;lag-&gt;ida_handle, NFP_FL_LAG_GROUP_MIN,</div><div class='del'>-			    NFP_FL_LAG_GROUP_MAX, GFP_KERNEL);</div><div class='add'>+	id = ida_alloc_range(&amp;lag-&gt;ida_handle, NFP_FL_LAG_GROUP_MIN,</div><div class='add'>+			     NFP_FL_LAG_GROUP_MAX, GFP_KERNEL);</div><div class='ctx'> 	if (id &lt; 0) {</div><div class='ctx'> 		nfp_flower_cmsg_warn(priv-&gt;app,</div><div class='ctx'> 				     "No more bonding groups available\n");</div><div class='hunk'>@@ -121,7 +121,7 @@ nfp_fl_lag_group_create(struct nfp_fl_lag *lag, struct net_device *master)</div><div class='ctx'> </div><div class='ctx'> 	group = kmalloc(sizeof(*group), GFP_KERNEL);</div><div class='ctx'> 	if (!group) {</div><div class='del'>-		ida_simple_remove(&amp;lag-&gt;ida_handle, id);</div><div class='add'>+		ida_free(&amp;lag-&gt;ida_handle, id);</div><div class='ctx'> 		return ERR_PTR(-ENOMEM);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -328,8 +328,7 @@ static void nfp_fl_lag_do_work(struct work_struct *work)</div><div class='ctx'> 			}</div><div class='ctx'> </div><div class='ctx'> 			if (entry-&gt;to_destroy) {</div><div class='del'>-				ida_simple_remove(&amp;lag-&gt;ida_handle,</div><div class='del'>-						  entry-&gt;group_id);</div><div class='add'>+				ida_free(&amp;lag-&gt;ida_handle, entry-&gt;group_id);</div><div class='ctx'> 				list_del(&amp;entry-&gt;list);</div><div class='ctx'> 				kfree(entry);</div><div class='ctx'> 			}</div><div class='hunk'>@@ -415,7 +414,7 @@ nfp_fl_lag_put_unprocessed(struct nfp_fl_lag *lag, struct sk_buff *skb)</div><div class='ctx'> 	struct nfp_flower_cmsg_lag_config *cmsg_payload;</div><div class='ctx'> </div><div class='ctx'> 	cmsg_payload = nfp_flower_cmsg_get_data(skb);</div><div class='del'>-	if (be32_to_cpu(cmsg_payload-&gt;group_id) &gt;= NFP_FL_LAG_GROUP_MAX)</div><div class='add'>+	if (be32_to_cpu(cmsg_payload-&gt;group_id) &gt; NFP_FL_LAG_GROUP_MAX)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	/* Drop cmsg retrans if storage limit is exceeded to prevent</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c b/drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c<br/>index 060a77f2265d..e522845c7c21 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c</a></div><div class='hunk'>@@ -160,6 +160,18 @@ struct nfp_tun_mac_addr_offload {</div><div class='ctx'> 	u8 addr[ETH_ALEN];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * struct nfp_neigh_update_work - update neighbour information to nfp</div><div class='add'>+ * @work:	Work queue for writing neigh to the nfp</div><div class='add'>+ * @n:		neighbour entry</div><div class='add'>+ * @app:	Back pointer to app</div><div class='add'>+ */</div><div class='add'>+struct nfp_neigh_update_work {</div><div class='add'>+	struct work_struct work;</div><div class='add'>+	struct neighbour *n;</div><div class='add'>+	struct nfp_app *app;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum nfp_flower_mac_offload_cmd {</div><div class='ctx'> 	NFP_TUNNEL_MAC_OFFLOAD_ADD =		0,</div><div class='ctx'> 	NFP_TUNNEL_MAC_OFFLOAD_DEL =		1,</div><div class='hunk'>@@ -607,38 +619,30 @@ err:</div><div class='ctx'> 	nfp_flower_cmsg_warn(app, "Neighbour configuration failed.\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int</div><div class='del'>-nfp_tun_neigh_event_handler(struct notifier_block *nb, unsigned long event,</div><div class='del'>-			    void *ptr)</div><div class='add'>+static void</div><div class='add'>+nfp_tun_release_neigh_update_work(struct nfp_neigh_update_work *update_work)</div><div class='ctx'> {</div><div class='del'>-	struct nfp_flower_priv *app_priv;</div><div class='del'>-	struct netevent_redirect *redir;</div><div class='del'>-	struct neighbour *n;</div><div class='add'>+	neigh_release(update_work-&gt;n);</div><div class='add'>+	kfree(update_work);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nfp_tun_neigh_update(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct nfp_neigh_update_work *update_work;</div><div class='ctx'> 	struct nfp_app *app;</div><div class='add'>+	struct neighbour *n;</div><div class='ctx'> 	bool neigh_invalid;</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	switch (event) {</div><div class='del'>-	case NETEVENT_REDIRECT:</div><div class='del'>-		redir = (struct netevent_redirect *)ptr;</div><div class='del'>-		n = redir-&gt;neigh;</div><div class='del'>-		break;</div><div class='del'>-	case NETEVENT_NEIGH_UPDATE:</div><div class='del'>-		n = (struct neighbour *)ptr;</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		return NOTIFY_DONE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	neigh_invalid = !(n-&gt;nud_state &amp; NUD_VALID) || n-&gt;dead;</div><div class='del'>-</div><div class='del'>-	app_priv = container_of(nb, struct nfp_flower_priv, tun.neigh_nb);</div><div class='del'>-	app = app_priv-&gt;app;</div><div class='add'>+	update_work = container_of(work, struct nfp_neigh_update_work, work);</div><div class='add'>+	app = update_work-&gt;app;</div><div class='add'>+	n = update_work-&gt;n;</div><div class='ctx'> </div><div class='ctx'> 	if (!nfp_flower_get_port_id_from_netdev(app, n-&gt;dev))</div><div class='del'>-		return NOTIFY_DONE;</div><div class='add'>+		goto out;</div><div class='ctx'> </div><div class='ctx'> #if IS_ENABLED(CONFIG_INET)</div><div class='add'>+	neigh_invalid = !(n-&gt;nud_state &amp; NUD_VALID) || n-&gt;dead;</div><div class='ctx'> 	if (n-&gt;tbl-&gt;family == AF_INET6) {</div><div class='ctx'> #if IS_ENABLED(CONFIG_IPV6)</div><div class='ctx'> 		struct flowi6 flow6 = {};</div><div class='hunk'>@@ -655,13 +659,11 @@ nfp_tun_neigh_event_handler(struct notifier_block *nb, unsigned long event,</div><div class='ctx'> 			dst = ip6_dst_lookup_flow(dev_net(n-&gt;dev), NULL,</div><div class='ctx'> 						  &amp;flow6, NULL);</div><div class='ctx'> 			if (IS_ERR(dst))</div><div class='del'>-				return NOTIFY_DONE;</div><div class='add'>+				goto out;</div><div class='ctx'> </div><div class='ctx'> 			dst_release(dst);</div><div class='ctx'> 		}</div><div class='ctx'> 		nfp_tun_write_neigh(n-&gt;dev, app, &amp;flow6, n, true, false);</div><div class='del'>-#else</div><div class='del'>-		return NOTIFY_DONE;</div><div class='ctx'> #endif /* CONFIG_IPV6 */</div><div class='ctx'> 	} else {</div><div class='ctx'> 		struct flowi4 flow4 = {};</div><div class='hunk'>@@ -678,17 +680,71 @@ nfp_tun_neigh_event_handler(struct notifier_block *nb, unsigned long event,</div><div class='ctx'> 			rt = ip_route_output_key(dev_net(n-&gt;dev), &amp;flow4);</div><div class='ctx'> 			err = PTR_ERR_OR_ZERO(rt);</div><div class='ctx'> 			if (err)</div><div class='del'>-				return NOTIFY_DONE;</div><div class='add'>+				goto out;</div><div class='ctx'> </div><div class='ctx'> 			ip_rt_put(rt);</div><div class='ctx'> 		}</div><div class='ctx'> 		nfp_tun_write_neigh(n-&gt;dev, app, &amp;flow4, n, false, false);</div><div class='ctx'> 	}</div><div class='del'>-#else</div><div class='del'>-	return NOTIFY_DONE;</div><div class='ctx'> #endif /* CONFIG_INET */</div><div class='add'>+out:</div><div class='add'>+	nfp_tun_release_neigh_update_work(update_work);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	return NOTIFY_OK;</div><div class='add'>+static struct nfp_neigh_update_work *</div><div class='add'>+nfp_tun_alloc_neigh_update_work(struct nfp_app *app, struct neighbour *n)</div><div class='add'>+{</div><div class='add'>+	struct nfp_neigh_update_work *update_work;</div><div class='add'>+</div><div class='add'>+	update_work = kzalloc(sizeof(*update_work), GFP_ATOMIC);</div><div class='add'>+	if (!update_work)</div><div class='add'>+		return NULL;</div><div class='add'>+</div><div class='add'>+	INIT_WORK(&amp;update_work-&gt;work, nfp_tun_neigh_update);</div><div class='add'>+	neigh_hold(n);</div><div class='add'>+	update_work-&gt;n = n;</div><div class='add'>+	update_work-&gt;app = app;</div><div class='add'>+</div><div class='add'>+	return update_work;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int</div><div class='add'>+nfp_tun_neigh_event_handler(struct notifier_block *nb, unsigned long event,</div><div class='add'>+			    void *ptr)</div><div class='add'>+{</div><div class='add'>+	struct nfp_neigh_update_work *update_work;</div><div class='add'>+	struct nfp_flower_priv *app_priv;</div><div class='add'>+	struct netevent_redirect *redir;</div><div class='add'>+	struct neighbour *n;</div><div class='add'>+	struct nfp_app *app;</div><div class='add'>+</div><div class='add'>+	switch (event) {</div><div class='add'>+	case NETEVENT_REDIRECT:</div><div class='add'>+		redir = (struct netevent_redirect *)ptr;</div><div class='add'>+		n = redir-&gt;neigh;</div><div class='add'>+		break;</div><div class='add'>+	case NETEVENT_NEIGH_UPDATE:</div><div class='add'>+		n = (struct neighbour *)ptr;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+	}</div><div class='add'>+#if IS_ENABLED(CONFIG_IPV6)</div><div class='add'>+	if (n-&gt;tbl != ipv6_stub-&gt;nd_tbl &amp;&amp; n-&gt;tbl != &amp;arp_tbl)</div><div class='add'>+#else</div><div class='add'>+	if (n-&gt;tbl != &amp;arp_tbl)</div><div class='add'>+#endif</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+</div><div class='add'>+	app_priv = container_of(nb, struct nfp_flower_priv, tun.neigh_nb);</div><div class='add'>+	app = app_priv-&gt;app;</div><div class='add'>+	update_work = nfp_tun_alloc_neigh_update_work(app, n);</div><div class='add'>+	if (!update_work)</div><div class='add'>+		return NOTIFY_DONE;</div><div class='add'>+</div><div class='add'>+	queue_work(system_highpri_wq, &amp;update_work-&gt;work);</div><div class='add'>+</div><div class='add'>+	return NOTIFY_DONE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void nfp_tunnel_request_route_v4(struct nfp_app *app, struct sk_buff *skb)</div><div class='hunk'>@@ -706,6 +762,7 @@ void nfp_tunnel_request_route_v4(struct nfp_app *app, struct sk_buff *skb)</div><div class='ctx'> 	netdev = nfp_app_dev_get(app, be32_to_cpu(payload-&gt;ingress_port), NULL);</div><div class='ctx'> 	if (!netdev)</div><div class='ctx'> 		goto fail_rcu_unlock;</div><div class='add'>+	dev_hold(netdev);</div><div class='ctx'> </div><div class='ctx'> 	flow.daddr = payload-&gt;ipv4_addr;</div><div class='ctx'> 	flow.flowi4_proto = IPPROTO_UDP;</div><div class='hunk'>@@ -725,13 +782,16 @@ void nfp_tunnel_request_route_v4(struct nfp_app *app, struct sk_buff *skb)</div><div class='ctx'> 	ip_rt_put(rt);</div><div class='ctx'> 	if (!n)</div><div class='ctx'> 		goto fail_rcu_unlock;</div><div class='add'>+	rcu_read_unlock();</div><div class='add'>+</div><div class='ctx'> 	nfp_tun_write_neigh(n-&gt;dev, app, &amp;flow, n, false, true);</div><div class='ctx'> 	neigh_release(n);</div><div class='del'>-	rcu_read_unlock();</div><div class='add'>+	dev_put(netdev);</div><div class='ctx'> 	return;</div><div class='ctx'> </div><div class='ctx'> fail_rcu_unlock:</div><div class='ctx'> 	rcu_read_unlock();</div><div class='add'>+	dev_put(netdev);</div><div class='ctx'> 	nfp_flower_cmsg_warn(app, "Requested route not found.\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -749,6 +809,7 @@ void nfp_tunnel_request_route_v6(struct nfp_app *app, struct sk_buff *skb)</div><div class='ctx'> 	netdev = nfp_app_dev_get(app, be32_to_cpu(payload-&gt;ingress_port), NULL);</div><div class='ctx'> 	if (!netdev)</div><div class='ctx'> 		goto fail_rcu_unlock;</div><div class='add'>+	dev_hold(netdev);</div><div class='ctx'> </div><div class='ctx'> 	flow.daddr = payload-&gt;ipv6_addr;</div><div class='ctx'> 	flow.flowi6_proto = IPPROTO_UDP;</div><div class='hunk'>@@ -766,14 +827,16 @@ void nfp_tunnel_request_route_v6(struct nfp_app *app, struct sk_buff *skb)</div><div class='ctx'> 	dst_release(dst);</div><div class='ctx'> 	if (!n)</div><div class='ctx'> 		goto fail_rcu_unlock;</div><div class='add'>+	rcu_read_unlock();</div><div class='ctx'> </div><div class='ctx'> 	nfp_tun_write_neigh(n-&gt;dev, app, &amp;flow, n, true, true);</div><div class='ctx'> 	neigh_release(n);</div><div class='del'>-	rcu_read_unlock();</div><div class='add'>+	dev_put(netdev);</div><div class='ctx'> 	return;</div><div class='ctx'> </div><div class='ctx'> fail_rcu_unlock:</div><div class='ctx'> 	rcu_read_unlock();</div><div class='add'>+	dev_put(netdev);</div><div class='ctx'> 	nfp_flower_cmsg_warn(app, "Requested IPv6 route not found.\n");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfd3/dp.c b/drivers/net/ethernet/netronome/nfp/nfd3/dp.c<br/>index 17381bfc15d7..d215efc6cad0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfd3/dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfd3/dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfd3/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfd3/dp.c</a></div><div class='hunk'>@@ -74,7 +74,7 @@ static void</div><div class='ctx'> nfp_nfd3_tx_tso(struct nfp_net_r_vector *r_vec, struct nfp_nfd3_tx_buf *txbuf,</div><div class='ctx'> 		struct nfp_nfd3_tx_desc *txd, struct sk_buff *skb, u32 md_bytes)</div><div class='ctx'> {</div><div class='del'>-	u32 l3_offset, l4_offset, hdrlen;</div><div class='add'>+	u32 l3_offset, l4_offset, hdrlen, l4_hdrlen;</div><div class='ctx'> 	u16 mss;</div><div class='ctx'> </div><div class='ctx'> 	if (!skb_is_gso(skb))</div><div class='hunk'>@@ -83,13 +83,16 @@ nfp_nfd3_tx_tso(struct nfp_net_r_vector *r_vec, struct nfp_nfd3_tx_buf *txbuf,</div><div class='ctx'> 	if (!skb-&gt;encapsulation) {</div><div class='ctx'> 		l3_offset = skb_network_offset(skb);</div><div class='ctx'> 		l4_offset = skb_transport_offset(skb);</div><div class='del'>-		hdrlen = skb_tcp_all_headers(skb);</div><div class='add'>+		l4_hdrlen = (skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4) ?</div><div class='add'>+			    sizeof(struct udphdr) : tcp_hdrlen(skb);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		l3_offset = skb_inner_network_offset(skb);</div><div class='ctx'> 		l4_offset = skb_inner_transport_offset(skb);</div><div class='del'>-		hdrlen = skb_inner_tcp_all_headers(skb);</div><div class='add'>+		l4_hdrlen = (skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4) ?</div><div class='add'>+			    sizeof(struct udphdr) : inner_tcp_hdrlen(skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	hdrlen = l4_offset + l4_hdrlen;</div><div class='ctx'> 	txbuf-&gt;pkt_cnt = skb_shinfo(skb)-&gt;gso_segs;</div><div class='ctx'> 	txbuf-&gt;real_len += hdrlen * (txbuf-&gt;pkt_cnt - 1);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfdk/dp.c b/drivers/net/ethernet/netronome/nfp/nfdk/dp.c<br/>index 8d78c6faefa8..dae5af7d1845 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfdk/dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfdk/dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfdk/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfdk/dp.c</a></div><div class='hunk'>@@ -40,20 +40,23 @@ static __le64</div><div class='ctx'> nfp_nfdk_tx_tso(struct nfp_net_r_vector *r_vec, struct nfp_nfdk_tx_buf *txbuf,</div><div class='ctx'> 		struct sk_buff *skb)</div><div class='ctx'> {</div><div class='del'>-	u32 segs, hdrlen, l3_offset, l4_offset;</div><div class='add'>+	u32 segs, hdrlen, l3_offset, l4_offset, l4_hdrlen;</div><div class='ctx'> 	struct nfp_nfdk_tx_desc txd;</div><div class='ctx'> 	u16 mss;</div><div class='ctx'> </div><div class='ctx'> 	if (!skb-&gt;encapsulation) {</div><div class='ctx'> 		l3_offset = skb_network_offset(skb);</div><div class='ctx'> 		l4_offset = skb_transport_offset(skb);</div><div class='del'>-		hdrlen = skb_tcp_all_headers(skb);</div><div class='add'>+		l4_hdrlen = (skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4) ?</div><div class='add'>+			    sizeof(struct udphdr) : tcp_hdrlen(skb);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		l3_offset = skb_inner_network_offset(skb);</div><div class='ctx'> 		l4_offset = skb_inner_transport_offset(skb);</div><div class='del'>-		hdrlen = skb_inner_tcp_all_headers(skb);</div><div class='add'>+		l4_hdrlen = (skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4) ?</div><div class='add'>+			    sizeof(struct udphdr) : inner_tcp_hdrlen(skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	hdrlen = l4_offset + l4_hdrlen;</div><div class='ctx'> 	segs = skb_shinfo(skb)-&gt;gso_segs;</div><div class='ctx'> 	mss = skb_shinfo(skb)-&gt;gso_size &amp; NFDK_DESC_TX_MSS_MASK;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfp_devlink.c b/drivers/net/ethernet/netronome/nfp/nfp_devlink.c<br/>index 8c6954c58a88..635d33c0d6d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_devlink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfp_devlink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_devlink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_devlink.c</a></div><div class='hunk'>@@ -75,8 +75,10 @@ nfp_devlink_port_split(struct devlink *devlink, struct devlink_port *port,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (eth_port.port_lanes % count)</div><div class='add'>+	if (eth_port.port_lanes % count) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "invalid count");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Special case the 100G CXP -&gt; 2x40G split */</div><div class='ctx'> 	lanes = eth_port.port_lanes / count;</div><div class='hunk'>@@ -101,8 +103,10 @@ nfp_devlink_port_unsplit(struct devlink *devlink, struct devlink_port *port,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (!eth_port.is_split)</div><div class='add'>+	if (!eth_port.is_split) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "port is not split");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Special case the 100G CXP -&gt; 2x40G unsplit */</div><div class='ctx'> 	lanes = eth_port.port_lanes;</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net.h b/drivers/net/ethernet/netronome/nfp/nfp_net.h<br/>index 939cfce15830..46764aeccb37 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfp_net.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net.h</a></div><div class='hunk'>@@ -621,6 +621,9 @@ struct nfp_net_dp {</div><div class='ctx'>  * @mbox_amsg.lock:	Protect message list</div><div class='ctx'>  * @mbox_amsg.list:	List of message to process</div><div class='ctx'>  * @mbox_amsg.work:	Work to process message asynchronously</div><div class='add'>+ * @fs:			Flow steering</div><div class='add'>+ * @fs.count:		Flow count</div><div class='add'>+ * @fs.list:		List of flows</div><div class='ctx'>  * @app_priv:		APP private data for this vNIC</div><div class='ctx'>  */</div><div class='ctx'> struct nfp_net {</div><div class='hunk'>@@ -728,9 +731,39 @@ struct nfp_net {</div><div class='ctx'> 		struct work_struct work;</div><div class='ctx'> 	} mbox_amsg;</div><div class='ctx'> </div><div class='add'>+	struct {</div><div class='add'>+		u16 count;</div><div class='add'>+		struct list_head list;</div><div class='add'>+	} fs;</div><div class='add'>+</div><div class='ctx'> 	void *app_priv;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct nfp_fs_entry {</div><div class='add'>+	struct list_head node;</div><div class='add'>+	u32 flow_type;</div><div class='add'>+	u32 loc;</div><div class='add'>+	struct {</div><div class='add'>+		union {</div><div class='add'>+			struct {</div><div class='add'>+				__be32 sip4;</div><div class='add'>+				__be32 dip4;</div><div class='add'>+			};</div><div class='add'>+			struct {</div><div class='add'>+				__be32 sip6[4];</div><div class='add'>+				__be32 dip6[4];</div><div class='add'>+			};</div><div class='add'>+		};</div><div class='add'>+		union {</div><div class='add'>+			__be16 l3_proto;</div><div class='add'>+			u8 l4_proto;</div><div class='add'>+		};</div><div class='add'>+		__be16 sport;</div><div class='add'>+		__be16 dport;</div><div class='add'>+	} key, msk;</div><div class='add'>+	u64 action;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct nfp_mbox_amsg_entry {</div><div class='ctx'> 	struct list_head list;</div><div class='ctx'> 	int (*cfg)(struct nfp_net *nn, struct nfp_mbox_amsg_entry *entry);</div><div class='hunk'>@@ -933,9 +966,9 @@ static inline bool nfp_netdev_is_nfp_net(struct net_device *netdev)</div><div class='ctx'> 	       netdev-&gt;netdev_ops == &amp;nfp_nfdk_netdev_ops;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline int nfp_net_coalesce_para_check(u32 usecs, u32 pkts)</div><div class='add'>+static inline int nfp_net_coalesce_para_check(u32 param)</div><div class='ctx'> {</div><div class='del'>-	if ((usecs &gt;= ((1 &lt;&lt; 16) - 1)) || (pkts &gt;= ((1 &lt;&lt; 16) - 1)))</div><div class='add'>+	if (param &gt;= ((1 &lt;&lt; 16) - 1))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -987,6 +1020,9 @@ struct nfp_net_dp *nfp_net_clone_dp(struct nfp_net *nn);</div><div class='ctx'> int nfp_net_ring_reconfig(struct nfp_net *nn, struct nfp_net_dp *new,</div><div class='ctx'> 			  struct netlink_ext_ack *extack);</div><div class='ctx'> </div><div class='add'>+int nfp_net_fs_add_hw(struct nfp_net *nn, struct nfp_fs_entry *entry);</div><div class='add'>+int nfp_net_fs_del_hw(struct nfp_net *nn, struct nfp_fs_entry *entry);</div><div class='add'>+</div><div class='ctx'> #ifdef CONFIG_NFP_DEBUG</div><div class='ctx'> void nfp_net_debugfs_create(void);</div><div class='ctx'> void nfp_net_debugfs_destroy(void);</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_common.c b/drivers/net/ethernet/netronome/nfp/nfp_net_common.c<br/>index de0a5d5ded30..3b3210d823e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfp_net_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_common.c</a></div><div class='hunk'>@@ -1176,7 +1176,8 @@ static void nfp_net_rx_dim_work(struct work_struct *work)</div><div class='ctx'> 	 * count.</div><div class='ctx'> 	 */</div><div class='ctx'> 	factor = nn-&gt;tlv_caps.me_freq_mhz / 16;</div><div class='del'>-	if (nfp_net_coalesce_para_check(factor * moder.usec, moder.pkts))</div><div class='add'>+	if (nfp_net_coalesce_para_check(factor * moder.usec) ||</div><div class='add'>+	    nfp_net_coalesce_para_check(moder.pkts))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* copy RX interrupt coalesce parameters */</div><div class='hunk'>@@ -1205,7 +1206,8 @@ static void nfp_net_tx_dim_work(struct work_struct *work)</div><div class='ctx'> 	 * count.</div><div class='ctx'> 	 */</div><div class='ctx'> 	factor = nn-&gt;tlv_caps.me_freq_mhz / 16;</div><div class='del'>-	if (nfp_net_coalesce_para_check(factor * moder.usec, moder.pkts))</div><div class='add'>+	if (nfp_net_coalesce_para_check(factor * moder.usec) ||</div><div class='add'>+	    nfp_net_coalesce_para_check(moder.pkts))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	/* copy TX interrupt coalesce parameters */</div><div class='hunk'>@@ -1763,6 +1765,186 @@ nfp_net_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)</div><div class='ctx'> 	return nfp_net_mbox_reconfig_and_unlock(nn, cmd);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void</div><div class='add'>+nfp_net_fs_fill_v4(struct nfp_net *nn, struct nfp_fs_entry *entry, u32 op, u32 *addr)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			__be16 loc;</div><div class='add'>+			u8 k_proto, m_proto;</div><div class='add'>+			__be32 k_sip, m_sip, k_dip, m_dip;</div><div class='add'>+			__be16 k_sport, m_sport, k_dport, m_dport;</div><div class='add'>+		};</div><div class='add'>+		__be32 val[7];</div><div class='add'>+	} v4_rule;</div><div class='add'>+</div><div class='add'>+	nn_writel(nn, *addr, op);</div><div class='add'>+	*addr += sizeof(u32);</div><div class='add'>+</div><div class='add'>+	v4_rule.loc     = cpu_to_be16(entry-&gt;loc);</div><div class='add'>+	v4_rule.k_proto = entry-&gt;key.l4_proto;</div><div class='add'>+	v4_rule.m_proto = entry-&gt;msk.l4_proto;</div><div class='add'>+	v4_rule.k_sip   = entry-&gt;key.sip4;</div><div class='add'>+	v4_rule.m_sip   = entry-&gt;msk.sip4;</div><div class='add'>+	v4_rule.k_dip   = entry-&gt;key.dip4;</div><div class='add'>+	v4_rule.m_dip   = entry-&gt;msk.dip4;</div><div class='add'>+	v4_rule.k_sport = entry-&gt;key.sport;</div><div class='add'>+	v4_rule.m_sport = entry-&gt;msk.sport;</div><div class='add'>+	v4_rule.k_dport = entry-&gt;key.dport;</div><div class='add'>+	v4_rule.m_dport = entry-&gt;msk.dport;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(v4_rule.val); i++, *addr += sizeof(__be32))</div><div class='add'>+		nn_writel(nn, *addr, be32_to_cpu(v4_rule.val[i]));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void</div><div class='add'>+nfp_net_fs_fill_v6(struct nfp_net *nn, struct nfp_fs_entry *entry, u32 op, u32 *addr)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		struct {</div><div class='add'>+			__be16 loc;</div><div class='add'>+			u8 k_proto, m_proto;</div><div class='add'>+			__be32 k_sip[4], m_sip[4], k_dip[4], m_dip[4];</div><div class='add'>+			__be16 k_sport, m_sport, k_dport, m_dport;</div><div class='add'>+		};</div><div class='add'>+		__be32 val[19];</div><div class='add'>+	} v6_rule;</div><div class='add'>+</div><div class='add'>+	nn_writel(nn, *addr, op);</div><div class='add'>+	*addr += sizeof(u32);</div><div class='add'>+</div><div class='add'>+	v6_rule.loc     = cpu_to_be16(entry-&gt;loc);</div><div class='add'>+	v6_rule.k_proto = entry-&gt;key.l4_proto;</div><div class='add'>+	v6_rule.m_proto = entry-&gt;msk.l4_proto;</div><div class='add'>+	for (i = 0; i &lt; 4; i++) {</div><div class='add'>+		v6_rule.k_sip[i] = entry-&gt;key.sip6[i];</div><div class='add'>+		v6_rule.m_sip[i] = entry-&gt;msk.sip6[i];</div><div class='add'>+		v6_rule.k_dip[i] = entry-&gt;key.dip6[i];</div><div class='add'>+		v6_rule.m_dip[i] = entry-&gt;msk.dip6[i];</div><div class='add'>+	}</div><div class='add'>+	v6_rule.k_sport = entry-&gt;key.sport;</div><div class='add'>+	v6_rule.m_sport = entry-&gt;msk.sport;</div><div class='add'>+	v6_rule.k_dport = entry-&gt;key.dport;</div><div class='add'>+	v6_rule.m_dport = entry-&gt;msk.dport;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(v6_rule.val); i++, *addr += sizeof(__be32))</div><div class='add'>+		nn_writel(nn, *addr, be32_to_cpu(v6_rule.val[i]));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+#define NFP_FS_QUEUE_ID	GENMASK(22, 16)</div><div class='add'>+#define NFP_FS_ACT	GENMASK(15, 0)</div><div class='add'>+#define NFP_FS_ACT_DROP	BIT(0)</div><div class='add'>+#define NFP_FS_ACT_Q	BIT(1)</div><div class='add'>+static void</div><div class='add'>+nfp_net_fs_fill_act(struct nfp_net *nn, struct nfp_fs_entry *entry, u32 addr)</div><div class='add'>+{</div><div class='add'>+	u32 action = 0; /* 0 means default passthrough */</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;action == RX_CLS_FLOW_DISC)</div><div class='add'>+		action = NFP_FS_ACT_DROP;</div><div class='add'>+	else if (!(entry-&gt;flow_type &amp; FLOW_RSS))</div><div class='add'>+		action = FIELD_PREP(NFP_FS_QUEUE_ID, entry-&gt;action) | NFP_FS_ACT_Q;</div><div class='add'>+</div><div class='add'>+	nn_writel(nn, addr, action);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int nfp_net_fs_add_hw(struct nfp_net *nn, struct nfp_fs_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 addr = nn-&gt;tlv_caps.mbox_off + NFP_NET_CFG_MBOX_SIMPLE_VAL;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = nfp_net_mbox_lock(nn, NFP_NET_CFG_FS_SZ);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+	case IPV4_USER_FLOW:</div><div class='add'>+		nfp_net_fs_fill_v4(nn, entry, NFP_NET_CFG_MBOX_CMD_FS_ADD_V4, &amp;addr);</div><div class='add'>+		break;</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+	case IPV6_USER_FLOW:</div><div class='add'>+		nfp_net_fs_fill_v6(nn, entry, NFP_NET_CFG_MBOX_CMD_FS_ADD_V6, &amp;addr);</div><div class='add'>+		break;</div><div class='add'>+	case ETHER_FLOW:</div><div class='add'>+		nn_writel(nn, addr, NFP_NET_CFG_MBOX_CMD_FS_ADD_ETHTYPE);</div><div class='add'>+		addr += sizeof(u32);</div><div class='add'>+		nn_writew(nn, addr, be16_to_cpu(entry-&gt;key.l3_proto));</div><div class='add'>+		addr += sizeof(u32);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nfp_net_fs_fill_act(nn, entry, addr);</div><div class='add'>+</div><div class='add'>+	err = nfp_net_mbox_reconfig_and_unlock(nn, NFP_NET_CFG_MBOX_CMD_FLOW_STEER);</div><div class='add'>+	if (err) {</div><div class='add'>+		nn_err(nn, "Add new fs rule failed with %d\n", err);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int nfp_net_fs_del_hw(struct nfp_net *nn, struct nfp_fs_entry *entry)</div><div class='add'>+{</div><div class='add'>+	u32 addr = nn-&gt;tlv_caps.mbox_off + NFP_NET_CFG_MBOX_SIMPLE_VAL;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = nfp_net_mbox_lock(nn, NFP_NET_CFG_FS_SZ);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+	case IPV4_USER_FLOW:</div><div class='add'>+		nfp_net_fs_fill_v4(nn, entry, NFP_NET_CFG_MBOX_CMD_FS_DEL_V4, &amp;addr);</div><div class='add'>+		break;</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+	case IPV6_USER_FLOW:</div><div class='add'>+		nfp_net_fs_fill_v6(nn, entry, NFP_NET_CFG_MBOX_CMD_FS_DEL_V6, &amp;addr);</div><div class='add'>+		break;</div><div class='add'>+	case ETHER_FLOW:</div><div class='add'>+		nn_writel(nn, addr, NFP_NET_CFG_MBOX_CMD_FS_DEL_ETHTYPE);</div><div class='add'>+		addr += sizeof(u32);</div><div class='add'>+		nn_writew(nn, addr, be16_to_cpu(entry-&gt;key.l3_proto));</div><div class='add'>+		addr += sizeof(u32);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nfp_net_fs_fill_act(nn, entry, addr);</div><div class='add'>+</div><div class='add'>+	err = nfp_net_mbox_reconfig_and_unlock(nn, NFP_NET_CFG_MBOX_CMD_FLOW_STEER);</div><div class='add'>+	if (err) {</div><div class='add'>+		nn_err(nn, "Delete fs rule failed with %d\n", err);</div><div class='add'>+		return -EIO;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nfp_net_fs_clean(struct nfp_net *nn)</div><div class='add'>+{</div><div class='add'>+	struct nfp_fs_entry *entry, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(entry, tmp, &amp;nn-&gt;fs.list, node) {</div><div class='add'>+		nfp_net_fs_del_hw(nn, entry);</div><div class='add'>+		list_del(&amp;entry-&gt;node);</div><div class='add'>+		kfree(entry);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void nfp_net_stat64(struct net_device *netdev,</div><div class='ctx'> 			   struct rtnl_link_stats64 *stats)</div><div class='ctx'> {</div><div class='hunk'>@@ -1934,7 +2116,10 @@ nfp_net_features_check(struct sk_buff *skb, struct net_device *dev,</div><div class='ctx'> 	if (skb_is_gso(skb)) {</div><div class='ctx'> 		u32 hdrlen;</div><div class='ctx'> </div><div class='del'>-		hdrlen = skb_inner_tcp_all_headers(skb);</div><div class='add'>+		if (skb_shinfo(skb)-&gt;gso_type &amp; SKB_GSO_UDP_L4)</div><div class='add'>+			hdrlen = skb_inner_transport_offset(skb) + sizeof(struct udphdr);</div><div class='add'>+		else</div><div class='add'>+			hdrlen = skb_inner_tcp_all_headers(skb);</div><div class='ctx'> </div><div class='ctx'> 		/* Assume worst case scenario of having longest possible</div><div class='ctx'> 		 * metadata prepend - 8B</div><div class='hunk'>@@ -2237,7 +2422,7 @@ void nfp_net_info(struct nfp_net *nn)</div><div class='ctx'> 		nn-&gt;fw_ver.extend, nn-&gt;fw_ver.class,</div><div class='ctx'> 		nn-&gt;fw_ver.major, nn-&gt;fw_ver.minor,</div><div class='ctx'> 		nn-&gt;max_mtu);</div><div class='del'>-	nn_info(nn, "CAP: %#x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",</div><div class='add'>+	nn_info(nn, "CAP: %#x %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",</div><div class='ctx'> 		nn-&gt;cap,</div><div class='ctx'> 		nn-&gt;cap &amp; NFP_NET_CFG_CTRL_PROMISC  ? "PROMISC "  : "",</div><div class='ctx'> 		nn-&gt;cap &amp; NFP_NET_CFG_CTRL_L2BC     ? "L2BCFILT " : "",</div><div class='hunk'>@@ -2266,6 +2451,7 @@ void nfp_net_info(struct nfp_net *nn)</div><div class='ctx'> 						      "RXCSUM_COMPLETE " : "",</div><div class='ctx'> 		nn-&gt;cap &amp; NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR " : "",</div><div class='ctx'> 		nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_MCAST_FILTER ? "MULTICAST_FILTER " : "",</div><div class='add'>+		nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_USO ? "USO " : "",</div><div class='ctx'> 		nfp_app_extra_cap(nn-&gt;app, nn));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2514,6 +2700,8 @@ static void nfp_net_netdev_init(struct nfp_net *nn)</div><div class='ctx'> 	if ((nn-&gt;cap &amp; NFP_NET_CFG_CTRL_LSO &amp;&amp; nn-&gt;fw_ver.major &gt; 2) ||</div><div class='ctx'> 	    nn-&gt;cap &amp; NFP_NET_CFG_CTRL_LSO2) {</div><div class='ctx'> 		netdev-&gt;hw_features |= NETIF_F_TSO | NETIF_F_TSO6;</div><div class='add'>+		if (nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_USO)</div><div class='add'>+			netdev-&gt;hw_features |= NETIF_F_GSO_UDP_L4;</div><div class='ctx'> 		nn-&gt;dp.ctrl |= nn-&gt;cap &amp; NFP_NET_CFG_CTRL_LSO2 ?:</div><div class='ctx'> 					 NFP_NET_CFG_CTRL_LSO;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2740,6 +2928,8 @@ int nfp_net_init(struct nfp_net *nn)</div><div class='ctx'> 	INIT_LIST_HEAD(&amp;nn-&gt;mbox_amsg.list);</div><div class='ctx'> 	INIT_WORK(&amp;nn-&gt;mbox_amsg.work, nfp_net_mbox_amsg_work);</div><div class='ctx'> </div><div class='add'>+	INIT_LIST_HEAD(&amp;nn-&gt;fs.list);</div><div class='add'>+</div><div class='ctx'> 	return register_netdev(nn-&gt;dp.netdev);</div><div class='ctx'> </div><div class='ctx'> err_clean_mbox:</div><div class='hunk'>@@ -2759,6 +2949,7 @@ void nfp_net_clean(struct nfp_net *nn)</div><div class='ctx'> 	unregister_netdev(nn-&gt;dp.netdev);</div><div class='ctx'> 	nfp_net_ipsec_clean(nn);</div><div class='ctx'> 	nfp_ccm_mbox_clean(nn);</div><div class='add'>+	nfp_net_fs_clean(nn);</div><div class='ctx'> 	flush_work(&amp;nn-&gt;mbox_amsg.work);</div><div class='ctx'> 	nfp_net_reconfig_wait_posted(nn);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h b/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h<br/>index 3e63f6d6a563..634c63c7f7eb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h</a></div><div class='hunk'>@@ -269,6 +269,8 @@</div><div class='ctx'> #define   NFP_NET_CFG_CTRL_IPSEC	  (0x1 &lt;&lt; 1) /* IPsec offload */</div><div class='ctx'> #define   NFP_NET_CFG_CTRL_MCAST_FILTER	  (0x1 &lt;&lt; 2) /* Multicast Filter */</div><div class='ctx'> #define   NFP_NET_CFG_CTRL_FREELIST_EN	  (0x1 &lt;&lt; 6) /* Freelist enable flag bit */</div><div class='add'>+#define   NFP_NET_CFG_CTRL_FLOW_STEER	  (0x1 &lt;&lt; 8) /* Flow steering */</div><div class='add'>+#define   NFP_NET_CFG_CTRL_USO		  (0x1 &lt;&lt; 16) /* UDP segmentation offload */</div><div class='ctx'> </div><div class='ctx'> #define NFP_NET_CFG_CAP_WORD1		0x00a4</div><div class='ctx'> </div><div class='hunk'>@@ -418,6 +420,8 @@</div><div class='ctx'> #define NFP_NET_CFG_MBOX_CMD_MULTICAST_ADD		8</div><div class='ctx'> #define NFP_NET_CFG_MBOX_CMD_MULTICAST_DEL		9</div><div class='ctx'> </div><div class='add'>+#define NFP_NET_CFG_MBOX_CMD_FLOW_STEER			10</div><div class='add'>+</div><div class='ctx'> /* VLAN filtering using general use mailbox</div><div class='ctx'>  * %NFP_NET_CFG_VLAN_FILTER:		Base address of VLAN filter mailbox</div><div class='ctx'>  * %NFP_NET_CFG_VLAN_FILTER_VID:	VLAN ID to filter</div><div class='hunk'>@@ -440,6 +444,18 @@</div><div class='ctx'> #define NFP_NET_CFG_MULTICAST_MAC_LO	(NFP_NET_CFG_MULTICAST + 6)</div><div class='ctx'> #define NFP_NET_CFG_MULTICAST_SZ	0x0006</div><div class='ctx'> </div><div class='add'>+/* Max size of FS rules in bytes */</div><div class='add'>+#define NFP_NET_CFG_FS_SZ		0x0054</div><div class='add'>+/* Sub commands for FS */</div><div class='add'>+enum {</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_ADD_V4,</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_DEL_V4,</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_ADD_V6,</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_DEL_V6,</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_ADD_ETHTYPE,</div><div class='add'>+	NFP_NET_CFG_MBOX_CMD_FS_DEL_ETHTYPE,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* TLV capabilities</div><div class='ctx'>  * %NFP_NET_CFG_TLV_TYPE:	Offset of type within the TLV</div><div class='ctx'>  * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c b/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c<br/>index e75cbb287625..fbca8d0efd85 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c</a></div><div class='hunk'>@@ -633,7 +633,8 @@ static void nfp_net_get_ringparam(struct net_device *netdev,</div><div class='ctx'> 	ring-&gt;tx_pending = nn-&gt;dp.txd_cnt;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nfp_net_set_ring_size(struct nfp_net *nn, u32 rxd_cnt, u32 txd_cnt)</div><div class='add'>+static int nfp_net_set_ring_size(struct nfp_net *nn, u32 rxd_cnt, u32 txd_cnt,</div><div class='add'>+				 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct nfp_net_dp *dp;</div><div class='ctx'> </div><div class='hunk'>@@ -644,7 +645,7 @@ static int nfp_net_set_ring_size(struct nfp_net *nn, u32 rxd_cnt, u32 txd_cnt)</div><div class='ctx'> 	dp-&gt;rxd_cnt = rxd_cnt;</div><div class='ctx'> 	dp-&gt;txd_cnt = txd_cnt;</div><div class='ctx'> </div><div class='del'>-	return nfp_net_ring_reconfig(nn, dp, NULL);</div><div class='add'>+	return nfp_net_ring_reconfig(nn, dp, extack);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nfp_net_set_ringparam(struct net_device *netdev,</div><div class='hunk'>@@ -657,7 +658,7 @@ static int nfp_net_set_ringparam(struct net_device *netdev,</div><div class='ctx'> </div><div class='ctx'> 	/* We don't have separate queues/rings for small/large frames. */</div><div class='ctx'> 	if (ring-&gt;rx_mini_pending || ring-&gt;rx_jumbo_pending)</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	qc_min = nn-&gt;dev_info-&gt;min_qc_size;</div><div class='ctx'> 	qc_max = nn-&gt;dev_info-&gt;max_qc_size;</div><div class='hunk'>@@ -666,9 +667,15 @@ static int nfp_net_set_ringparam(struct net_device *netdev,</div><div class='ctx'> 	rxd_cnt = roundup_pow_of_two(ring-&gt;rx_pending);</div><div class='ctx'> 	txd_cnt = roundup_pow_of_two(ring-&gt;tx_pending);</div><div class='ctx'> </div><div class='del'>-	if (rxd_cnt &lt; qc_min || rxd_cnt &gt; qc_max ||</div><div class='del'>-	    txd_cnt &lt; qc_min / tx_dpp || txd_cnt &gt; qc_max / tx_dpp)</div><div class='add'>+	if (rxd_cnt &lt; qc_min || rxd_cnt &gt; qc_max) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "rx parameter out of bounds");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (txd_cnt &lt; qc_min / tx_dpp || txd_cnt &gt; qc_max / tx_dpp) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "tx parameter out of bounds");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (nn-&gt;dp.rxd_cnt == rxd_cnt &amp;&amp; nn-&gt;dp.txd_cnt == txd_cnt)</div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -676,7 +683,7 @@ static int nfp_net_set_ringparam(struct net_device *netdev,</div><div class='ctx'> 	nn_dbg(nn, "Change ring size: RxQ %u-&gt;%u, TxQ %u-&gt;%u\n",</div><div class='ctx'> 	       nn-&gt;dp.rxd_cnt, rxd_cnt, nn-&gt;dp.txd_cnt, txd_cnt);</div><div class='ctx'> </div><div class='del'>-	return nfp_net_set_ring_size(nn, rxd_cnt, txd_cnt);</div><div class='add'>+	return nfp_net_set_ring_size(nn, rxd_cnt, txd_cnt, extack);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nfp_test_link(struct net_device *netdev)</div><div class='hunk'>@@ -800,7 +807,7 @@ static void nfp_get_self_test_strings(struct net_device *netdev, u8 *data)</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NFP_TEST_TOTAL_NUM; i++)</div><div class='ctx'> 		if (nfp_self_test[i].is_supported(netdev))</div><div class='del'>-			ethtool_sprintf(&amp;data, nfp_self_test[i].name);</div><div class='add'>+			ethtool_puts(&amp;data, nfp_self_test[i].name);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nfp_get_self_test_count(struct net_device *netdev)</div><div class='hunk'>@@ -852,24 +859,24 @@ static u8 *nfp_vnic_get_sw_stats_strings(struct net_device *netdev, u8 *data)</div><div class='ctx'> 		ethtool_sprintf(&amp;data, "rvec_%u_tx_busy", i);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_rx_csum_ok");</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_rx_csum_inner_ok");</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_rx_csum_complete");</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_rx_csum_err");</div><div class='del'>-	ethtool_sprintf(&amp;data, "rx_replace_buf_alloc_fail");</div><div class='del'>-	ethtool_sprintf(&amp;data, "rx_tls_decrypted_packets");</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_tx_csum");</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_tx_inner_csum");</div><div class='del'>-	ethtool_sprintf(&amp;data, "tx_gather");</div><div class='del'>-	ethtool_sprintf(&amp;data, "tx_lso");</div><div class='del'>-	ethtool_sprintf(&amp;data, "tx_tls_encrypted_packets");</div><div class='del'>-	ethtool_sprintf(&amp;data, "tx_tls_ooo");</div><div class='del'>-	ethtool_sprintf(&amp;data, "tx_tls_drop_no_sync_data");</div><div class='del'>-</div><div class='del'>-	ethtool_sprintf(&amp;data, "hw_tls_no_space");</div><div class='del'>-	ethtool_sprintf(&amp;data, "rx_tls_resync_req_ok");</div><div class='del'>-	ethtool_sprintf(&amp;data, "rx_tls_resync_req_ign");</div><div class='del'>-	ethtool_sprintf(&amp;data, "rx_tls_resync_sent");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_rx_csum_ok");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_rx_csum_inner_ok");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_rx_csum_complete");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_rx_csum_err");</div><div class='add'>+	ethtool_puts(&amp;data, "rx_replace_buf_alloc_fail");</div><div class='add'>+	ethtool_puts(&amp;data, "rx_tls_decrypted_packets");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_tx_csum");</div><div class='add'>+	ethtool_puts(&amp;data, "hw_tx_inner_csum");</div><div class='add'>+	ethtool_puts(&amp;data, "tx_gather");</div><div class='add'>+	ethtool_puts(&amp;data, "tx_lso");</div><div class='add'>+	ethtool_puts(&amp;data, "tx_tls_encrypted_packets");</div><div class='add'>+	ethtool_puts(&amp;data, "tx_tls_ooo");</div><div class='add'>+	ethtool_puts(&amp;data, "tx_tls_drop_no_sync_data");</div><div class='add'>+</div><div class='add'>+	ethtool_puts(&amp;data, "hw_tls_no_space");</div><div class='add'>+	ethtool_puts(&amp;data, "rx_tls_resync_req_ok");</div><div class='add'>+	ethtool_puts(&amp;data, "rx_tls_resync_req_ign");</div><div class='add'>+	ethtool_puts(&amp;data, "rx_tls_resync_sent");</div><div class='ctx'> </div><div class='ctx'> 	return data;</div><div class='ctx'> }</div><div class='hunk'>@@ -943,13 +950,13 @@ nfp_vnic_get_hw_stats_strings(u8 *data, unsigned int num_vecs, bool repr)</div><div class='ctx'> 	swap_off = repr * NN_ET_SWITCH_STATS_LEN;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; NN_ET_SWITCH_STATS_LEN; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, nfp_net_et_stats[i + swap_off].name);</div><div class='add'>+		ethtool_puts(&amp;data, nfp_net_et_stats[i + swap_off].name);</div><div class='ctx'> </div><div class='ctx'> 	for (i = NN_ET_SWITCH_STATS_LEN; i &lt; NN_ET_SWITCH_STATS_LEN * 2; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, nfp_net_et_stats[i - swap_off].name);</div><div class='add'>+		ethtool_puts(&amp;data, nfp_net_et_stats[i - swap_off].name);</div><div class='ctx'> </div><div class='ctx'> 	for (i = NN_ET_SWITCH_STATS_LEN * 2; i &lt; NN_ET_GLOBAL_STATS_LEN; i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, nfp_net_et_stats[i].name);</div><div class='add'>+		ethtool_puts(&amp;data, nfp_net_et_stats[i].name);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num_vecs; i++) {</div><div class='ctx'> 		ethtool_sprintf(&amp;data, "rxq_%u_pkts", i);</div><div class='hunk'>@@ -1317,6 +1324,116 @@ static int nfp_net_get_rss_hash_opts(struct nfp_net *nn,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define NFP_FS_MAX_ENTRY	1024</div><div class='add'>+</div><div class='add'>+static int nfp_net_fs_to_ethtool(struct nfp_fs_entry *entry, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct ethtool_rx_flow_spec *fs = &amp;cmd-&gt;fs;</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	switch (entry-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+		fs-&gt;h_u.tcp_ip4_spec.ip4src = entry-&gt;key.sip4;</div><div class='add'>+		fs-&gt;h_u.tcp_ip4_spec.ip4dst = entry-&gt;key.dip4;</div><div class='add'>+		fs-&gt;h_u.tcp_ip4_spec.psrc   = entry-&gt;key.sport;</div><div class='add'>+		fs-&gt;h_u.tcp_ip4_spec.pdst   = entry-&gt;key.dport;</div><div class='add'>+		fs-&gt;m_u.tcp_ip4_spec.ip4src = entry-&gt;msk.sip4;</div><div class='add'>+		fs-&gt;m_u.tcp_ip4_spec.ip4dst = entry-&gt;msk.dip4;</div><div class='add'>+		fs-&gt;m_u.tcp_ip4_spec.psrc   = entry-&gt;msk.sport;</div><div class='add'>+		fs-&gt;m_u.tcp_ip4_spec.pdst   = entry-&gt;msk.dport;</div><div class='add'>+		break;</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+		for (i = 0; i &lt; 4; i++) {</div><div class='add'>+			fs-&gt;h_u.tcp_ip6_spec.ip6src[i] = entry-&gt;key.sip6[i];</div><div class='add'>+			fs-&gt;h_u.tcp_ip6_spec.ip6dst[i] = entry-&gt;key.dip6[i];</div><div class='add'>+			fs-&gt;m_u.tcp_ip6_spec.ip6src[i] = entry-&gt;msk.sip6[i];</div><div class='add'>+			fs-&gt;m_u.tcp_ip6_spec.ip6dst[i] = entry-&gt;msk.dip6[i];</div><div class='add'>+		}</div><div class='add'>+		fs-&gt;h_u.tcp_ip6_spec.psrc = entry-&gt;key.sport;</div><div class='add'>+		fs-&gt;h_u.tcp_ip6_spec.pdst = entry-&gt;key.dport;</div><div class='add'>+		fs-&gt;m_u.tcp_ip6_spec.psrc = entry-&gt;msk.sport;</div><div class='add'>+		fs-&gt;m_u.tcp_ip6_spec.pdst = entry-&gt;msk.dport;</div><div class='add'>+		break;</div><div class='add'>+	case IPV4_USER_FLOW:</div><div class='add'>+		fs-&gt;h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;</div><div class='add'>+		fs-&gt;h_u.usr_ip4_spec.ip4src = entry-&gt;key.sip4;</div><div class='add'>+		fs-&gt;h_u.usr_ip4_spec.ip4dst = entry-&gt;key.dip4;</div><div class='add'>+		fs-&gt;h_u.usr_ip4_spec.proto  = entry-&gt;key.l4_proto;</div><div class='add'>+		fs-&gt;m_u.usr_ip4_spec.ip4src = entry-&gt;msk.sip4;</div><div class='add'>+		fs-&gt;m_u.usr_ip4_spec.ip4dst = entry-&gt;msk.dip4;</div><div class='add'>+		fs-&gt;m_u.usr_ip4_spec.proto  = entry-&gt;msk.l4_proto;</div><div class='add'>+		break;</div><div class='add'>+	case IPV6_USER_FLOW:</div><div class='add'>+		for (i = 0; i &lt; 4; i++) {</div><div class='add'>+			fs-&gt;h_u.usr_ip6_spec.ip6src[i] = entry-&gt;key.sip6[i];</div><div class='add'>+			fs-&gt;h_u.usr_ip6_spec.ip6dst[i] = entry-&gt;key.dip6[i];</div><div class='add'>+			fs-&gt;m_u.usr_ip6_spec.ip6src[i] = entry-&gt;msk.sip6[i];</div><div class='add'>+			fs-&gt;m_u.usr_ip6_spec.ip6dst[i] = entry-&gt;msk.dip6[i];</div><div class='add'>+		}</div><div class='add'>+		fs-&gt;h_u.usr_ip6_spec.l4_proto = entry-&gt;key.l4_proto;</div><div class='add'>+		fs-&gt;m_u.usr_ip6_spec.l4_proto = entry-&gt;msk.l4_proto;</div><div class='add'>+		break;</div><div class='add'>+	case ETHER_FLOW:</div><div class='add'>+		fs-&gt;h_u.ether_spec.h_proto = entry-&gt;key.l3_proto;</div><div class='add'>+		fs-&gt;m_u.ether_spec.h_proto = entry-&gt;msk.l3_proto;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fs-&gt;flow_type   = entry-&gt;flow_type;</div><div class='add'>+	fs-&gt;ring_cookie = entry-&gt;action;</div><div class='add'>+</div><div class='add'>+	if (fs-&gt;flow_type &amp; FLOW_RSS) {</div><div class='add'>+		/* Only rss_context of 0 is supported. */</div><div class='add'>+		cmd-&gt;rss_context = 0;</div><div class='add'>+		/* RSS is used, mask the ring. */</div><div class='add'>+		fs-&gt;ring_cookie |= ETHTOOL_RX_FLOW_SPEC_RING;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nfp_net_get_fs_rule(struct nfp_net *nn, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct nfp_fs_entry *entry;</div><div class='add'>+</div><div class='add'>+	if (!(nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_FLOW_STEER))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (cmd-&gt;fs.location &gt;= NFP_FS_MAX_ENTRY)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(entry, &amp;nn-&gt;fs.list, node) {</div><div class='add'>+		if (entry-&gt;loc == cmd-&gt;fs.location)</div><div class='add'>+			return nfp_net_fs_to_ethtool(entry, cmd);</div><div class='add'>+</div><div class='add'>+		if (entry-&gt;loc &gt; cmd-&gt;fs.location)</div><div class='add'>+			/* no need to continue */</div><div class='add'>+			return -ENOENT;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ENOENT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nfp_net_get_fs_loc(struct nfp_net *nn, u32 *rule_locs)</div><div class='add'>+{</div><div class='add'>+	struct nfp_fs_entry *entry;</div><div class='add'>+	u32 count = 0;</div><div class='add'>+</div><div class='add'>+	if (!(nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_FLOW_STEER))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(entry, &amp;nn-&gt;fs.list, node)</div><div class='add'>+		rule_locs[count++] = entry-&gt;loc;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int nfp_net_get_rxnfc(struct net_device *netdev,</div><div class='ctx'> 			     struct ethtool_rxnfc *cmd, u32 *rule_locs)</div><div class='ctx'> {</div><div class='hunk'>@@ -1326,6 +1443,14 @@ static int nfp_net_get_rxnfc(struct net_device *netdev,</div><div class='ctx'> 	case ETHTOOL_GRXRINGS:</div><div class='ctx'> 		cmd-&gt;data = nn-&gt;dp.num_rx_rings;</div><div class='ctx'> 		return 0;</div><div class='add'>+	case ETHTOOL_GRXCLSRLCNT:</div><div class='add'>+		cmd-&gt;rule_cnt = nn-&gt;fs.count;</div><div class='add'>+		return 0;</div><div class='add'>+	case ETHTOOL_GRXCLSRULE:</div><div class='add'>+		return nfp_net_get_fs_rule(nn, cmd);</div><div class='add'>+	case ETHTOOL_GRXCLSRLALL:</div><div class='add'>+		cmd-&gt;data = NFP_FS_MAX_ENTRY;</div><div class='add'>+		return nfp_net_get_fs_loc(nn, rule_locs);</div><div class='ctx'> 	case ETHTOOL_GRXFH:</div><div class='ctx'> 		return nfp_net_get_rss_hash_opts(nn, cmd);</div><div class='ctx'> 	default:</div><div class='hunk'>@@ -1385,6 +1510,253 @@ static int nfp_net_set_rss_hash_opt(struct nfp_net *nn,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int nfp_net_fs_from_ethtool(struct nfp_fs_entry *entry, struct ethtool_rx_flow_spec *fs)</div><div class='add'>+{</div><div class='add'>+	unsigned int i;</div><div class='add'>+</div><div class='add'>+	/* FLOW_EXT/FLOW_MAC_EXT is not supported. */</div><div class='add'>+	switch (fs-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+		entry-&gt;msk.sip4  = fs-&gt;m_u.tcp_ip4_spec.ip4src;</div><div class='add'>+		entry-&gt;msk.dip4  = fs-&gt;m_u.tcp_ip4_spec.ip4dst;</div><div class='add'>+		entry-&gt;msk.sport = fs-&gt;m_u.tcp_ip4_spec.psrc;</div><div class='add'>+		entry-&gt;msk.dport = fs-&gt;m_u.tcp_ip4_spec.pdst;</div><div class='add'>+		entry-&gt;key.sip4  = fs-&gt;h_u.tcp_ip4_spec.ip4src &amp; entry-&gt;msk.sip4;</div><div class='add'>+		entry-&gt;key.dip4  = fs-&gt;h_u.tcp_ip4_spec.ip4dst &amp; entry-&gt;msk.dip4;</div><div class='add'>+		entry-&gt;key.sport = fs-&gt;h_u.tcp_ip4_spec.psrc &amp; entry-&gt;msk.sport;</div><div class='add'>+		entry-&gt;key.dport = fs-&gt;h_u.tcp_ip4_spec.pdst &amp; entry-&gt;msk.dport;</div><div class='add'>+		break;</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+		for (i = 0; i &lt; 4; i++) {</div><div class='add'>+			entry-&gt;msk.sip6[i] = fs-&gt;m_u.tcp_ip6_spec.ip6src[i];</div><div class='add'>+			entry-&gt;msk.dip6[i] = fs-&gt;m_u.tcp_ip6_spec.ip6dst[i];</div><div class='add'>+			entry-&gt;key.sip6[i] = fs-&gt;h_u.tcp_ip6_spec.ip6src[i] &amp; entry-&gt;msk.sip6[i];</div><div class='add'>+			entry-&gt;key.dip6[i] = fs-&gt;h_u.tcp_ip6_spec.ip6dst[i] &amp; entry-&gt;msk.dip6[i];</div><div class='add'>+		}</div><div class='add'>+		entry-&gt;msk.sport = fs-&gt;m_u.tcp_ip6_spec.psrc;</div><div class='add'>+		entry-&gt;msk.dport = fs-&gt;m_u.tcp_ip6_spec.pdst;</div><div class='add'>+		entry-&gt;key.sport = fs-&gt;h_u.tcp_ip6_spec.psrc &amp; entry-&gt;msk.sport;</div><div class='add'>+		entry-&gt;key.dport = fs-&gt;h_u.tcp_ip6_spec.pdst &amp; entry-&gt;msk.dport;</div><div class='add'>+		break;</div><div class='add'>+	case IPV4_USER_FLOW:</div><div class='add'>+		entry-&gt;msk.sip4     = fs-&gt;m_u.usr_ip4_spec.ip4src;</div><div class='add'>+		entry-&gt;msk.dip4     = fs-&gt;m_u.usr_ip4_spec.ip4dst;</div><div class='add'>+		entry-&gt;msk.l4_proto = fs-&gt;m_u.usr_ip4_spec.proto;</div><div class='add'>+		entry-&gt;key.sip4     = fs-&gt;h_u.usr_ip4_spec.ip4src &amp; entry-&gt;msk.sip4;</div><div class='add'>+		entry-&gt;key.dip4     = fs-&gt;h_u.usr_ip4_spec.ip4dst &amp; entry-&gt;msk.dip4;</div><div class='add'>+		entry-&gt;key.l4_proto = fs-&gt;h_u.usr_ip4_spec.proto &amp; entry-&gt;msk.l4_proto;</div><div class='add'>+		break;</div><div class='add'>+	case IPV6_USER_FLOW:</div><div class='add'>+		for (i = 0; i &lt; 4; i++) {</div><div class='add'>+			entry-&gt;msk.sip6[i] = fs-&gt;m_u.usr_ip6_spec.ip6src[i];</div><div class='add'>+			entry-&gt;msk.dip6[i] = fs-&gt;m_u.usr_ip6_spec.ip6dst[i];</div><div class='add'>+			entry-&gt;key.sip6[i] = fs-&gt;h_u.usr_ip6_spec.ip6src[i] &amp; entry-&gt;msk.sip6[i];</div><div class='add'>+			entry-&gt;key.dip6[i] = fs-&gt;h_u.usr_ip6_spec.ip6dst[i] &amp; entry-&gt;msk.dip6[i];</div><div class='add'>+		}</div><div class='add'>+		entry-&gt;msk.l4_proto = fs-&gt;m_u.usr_ip6_spec.l4_proto;</div><div class='add'>+		entry-&gt;key.l4_proto = fs-&gt;h_u.usr_ip6_spec.l4_proto &amp; entry-&gt;msk.l4_proto;</div><div class='add'>+		break;</div><div class='add'>+	case ETHER_FLOW:</div><div class='add'>+		entry-&gt;msk.l3_proto = fs-&gt;m_u.ether_spec.h_proto;</div><div class='add'>+		entry-&gt;key.l3_proto = fs-&gt;h_u.ether_spec.h_proto &amp; entry-&gt;msk.l3_proto;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (fs-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+		entry-&gt;key.l4_proto = IPPROTO_TCP;</div><div class='add'>+		entry-&gt;msk.l4_proto = 0xff;</div><div class='add'>+		break;</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+		entry-&gt;key.l4_proto = IPPROTO_UDP;</div><div class='add'>+		entry-&gt;msk.l4_proto = 0xff;</div><div class='add'>+		break;</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+		entry-&gt;key.l4_proto = IPPROTO_SCTP;</div><div class='add'>+		entry-&gt;msk.l4_proto = 0xff;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	entry-&gt;flow_type = fs-&gt;flow_type;</div><div class='add'>+	entry-&gt;action    = fs-&gt;ring_cookie;</div><div class='add'>+	entry-&gt;loc       = fs-&gt;location;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nfp_net_fs_check_existing(struct nfp_net *nn, struct nfp_fs_entry *new)</div><div class='add'>+{</div><div class='add'>+	struct nfp_fs_entry *entry;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(entry, &amp;nn-&gt;fs.list, node) {</div><div class='add'>+		if (new-&gt;loc != entry-&gt;loc &amp;&amp;</div><div class='add'>+		    !((new-&gt;flow_type ^ entry-&gt;flow_type) &amp; ~FLOW_RSS) &amp;&amp;</div><div class='add'>+		    !memcmp(&amp;new-&gt;key, &amp;entry-&gt;key, sizeof(new-&gt;key)) &amp;&amp;</div><div class='add'>+		    !memcmp(&amp;new-&gt;msk, &amp;entry-&gt;msk, sizeof(new-&gt;msk)))</div><div class='add'>+			return entry-&gt;loc;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* -1 means no duplicates */</div><div class='add'>+	return -1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nfp_net_fs_add(struct nfp_net *nn, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct ethtool_rx_flow_spec *fs = &amp;cmd-&gt;fs;</div><div class='add'>+	struct nfp_fs_entry *new, *entry;</div><div class='add'>+	bool unsupp_mask;</div><div class='add'>+	int err, id;</div><div class='add'>+</div><div class='add'>+	if (!(nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_FLOW_STEER))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* Only default RSS context(0) is supported. */</div><div class='add'>+	if ((fs-&gt;flow_type &amp; FLOW_RSS) &amp;&amp; cmd-&gt;rss_context)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (fs-&gt;location &gt;= NFP_FS_MAX_ENTRY)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (fs-&gt;ring_cookie != RX_CLS_FLOW_DISC &amp;&amp;</div><div class='add'>+	    fs-&gt;ring_cookie &gt;= nn-&gt;dp.num_rx_rings)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* FLOW_EXT/FLOW_MAC_EXT is not supported. */</div><div class='add'>+	switch (fs-&gt;flow_type &amp; ~FLOW_RSS) {</div><div class='add'>+	case TCP_V4_FLOW:</div><div class='add'>+	case UDP_V4_FLOW:</div><div class='add'>+	case SCTP_V4_FLOW:</div><div class='add'>+		unsupp_mask = !!fs-&gt;m_u.tcp_ip4_spec.tos;</div><div class='add'>+		break;</div><div class='add'>+	case TCP_V6_FLOW:</div><div class='add'>+	case UDP_V6_FLOW:</div><div class='add'>+	case SCTP_V6_FLOW:</div><div class='add'>+		unsupp_mask = !!fs-&gt;m_u.tcp_ip6_spec.tclass;</div><div class='add'>+		break;</div><div class='add'>+	case IPV4_USER_FLOW:</div><div class='add'>+		unsupp_mask = !!fs-&gt;m_u.usr_ip4_spec.l4_4_bytes ||</div><div class='add'>+			      !!fs-&gt;m_u.usr_ip4_spec.tos ||</div><div class='add'>+			      !!fs-&gt;m_u.usr_ip4_spec.ip_ver;</div><div class='add'>+		/* ip_ver must be ETH_RX_NFC_IP4. */</div><div class='add'>+		unsupp_mask |= fs-&gt;h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4;</div><div class='add'>+		break;</div><div class='add'>+	case IPV6_USER_FLOW:</div><div class='add'>+		unsupp_mask = !!fs-&gt;m_u.usr_ip6_spec.l4_4_bytes ||</div><div class='add'>+			      !!fs-&gt;m_u.usr_ip6_spec.tclass;</div><div class='add'>+		break;</div><div class='add'>+	case ETHER_FLOW:</div><div class='add'>+		if (fs-&gt;h_u.ether_spec.h_proto == htons(ETH_P_IP) ||</div><div class='add'>+		    fs-&gt;h_u.ether_spec.h_proto == htons(ETH_P_IPV6)) {</div><div class='add'>+			nn_err(nn, "Please use ip4/ip6 flow type instead.\n");</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+		}</div><div class='add'>+		/* Only unmasked ethtype is supported. */</div><div class='add'>+		unsupp_mask = !is_zero_ether_addr(fs-&gt;m_u.ether_spec.h_dest) ||</div><div class='add'>+			      !is_zero_ether_addr(fs-&gt;m_u.ether_spec.h_source) ||</div><div class='add'>+			      (fs-&gt;m_u.ether_spec.h_proto != htons(0xffff));</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (unsupp_mask)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	new = kzalloc(sizeof(*new), GFP_KERNEL);</div><div class='add'>+	if (!new)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	nfp_net_fs_from_ethtool(new, fs);</div><div class='add'>+</div><div class='add'>+	id = nfp_net_fs_check_existing(nn, new);</div><div class='add'>+	if (id &gt;= 0) {</div><div class='add'>+		nn_err(nn, "Identical rule is existing in %d.\n", id);</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Insert to list in ascending order of location. */</div><div class='add'>+	list_for_each_entry(entry, &amp;nn-&gt;fs.list, node) {</div><div class='add'>+		if (entry-&gt;loc == fs-&gt;location) {</div><div class='add'>+			err = nfp_net_fs_del_hw(nn, entry);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err;</div><div class='add'>+</div><div class='add'>+			nn-&gt;fs.count--;</div><div class='add'>+			err = nfp_net_fs_add_hw(nn, new);</div><div class='add'>+			if (err)</div><div class='add'>+				goto err;</div><div class='add'>+</div><div class='add'>+			nn-&gt;fs.count++;</div><div class='add'>+			list_replace(&amp;entry-&gt;node, &amp;new-&gt;node);</div><div class='add'>+			kfree(entry);</div><div class='add'>+</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (entry-&gt;loc &gt; fs-&gt;location)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (nn-&gt;fs.count == NFP_FS_MAX_ENTRY) {</div><div class='add'>+		err = -ENOSPC;</div><div class='add'>+		goto err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = nfp_net_fs_add_hw(nn, new);</div><div class='add'>+	if (err)</div><div class='add'>+		goto err;</div><div class='add'>+</div><div class='add'>+	list_add_tail(&amp;new-&gt;node, &amp;entry-&gt;node);</div><div class='add'>+	nn-&gt;fs.count++;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err:</div><div class='add'>+	kfree(new);</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nfp_net_fs_del(struct nfp_net *nn, struct ethtool_rxnfc *cmd)</div><div class='add'>+{</div><div class='add'>+	struct nfp_fs_entry *entry;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!(nn-&gt;cap_w1 &amp; NFP_NET_CFG_CTRL_FLOW_STEER))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (!nn-&gt;fs.count || cmd-&gt;fs.location &gt;= NFP_FS_MAX_ENTRY)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(entry, &amp;nn-&gt;fs.list, node) {</div><div class='add'>+		if (entry-&gt;loc == cmd-&gt;fs.location) {</div><div class='add'>+			err = nfp_net_fs_del_hw(nn, entry);</div><div class='add'>+			if (err)</div><div class='add'>+				return err;</div><div class='add'>+</div><div class='add'>+			list_del(&amp;entry-&gt;node);</div><div class='add'>+			kfree(entry);</div><div class='add'>+			nn-&gt;fs.count--;</div><div class='add'>+</div><div class='add'>+			return 0;</div><div class='add'>+		} else if (entry-&gt;loc &gt; cmd-&gt;fs.location) {</div><div class='add'>+			/* no need to continue */</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return -ENOENT;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int nfp_net_set_rxnfc(struct net_device *netdev,</div><div class='ctx'> 			     struct ethtool_rxnfc *cmd)</div><div class='ctx'> {</div><div class='hunk'>@@ -1393,6 +1765,10 @@ static int nfp_net_set_rxnfc(struct net_device *netdev,</div><div class='ctx'> 	switch (cmd-&gt;cmd) {</div><div class='ctx'> 	case ETHTOOL_SRXFH:</div><div class='ctx'> 		return nfp_net_set_rss_hash_opt(nn, cmd);</div><div class='add'>+	case ETHTOOL_SRXCLSRLINS:</div><div class='add'>+		return nfp_net_fs_add(nn, cmd);</div><div class='add'>+	case ETHTOOL_SRXCLSRLDEL:</div><div class='add'>+		return nfp_net_fs_del(nn, cmd);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1418,8 +1794,8 @@ static u32 nfp_net_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return nfp_net_rss_key_sz(nn);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int nfp_net_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			    u8 *hfunc)</div><div class='add'>+static int nfp_net_get_rxfh(struct net_device *netdev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct nfp_net *nn = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='hunk'>@@ -1427,41 +1803,41 @@ static int nfp_net_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='ctx'> 	if (!(nn-&gt;cap &amp; NFP_NET_CFG_CTRL_RSS_ANY))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir)</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(nn-&gt;rss_itbl); i++)</div><div class='del'>-			indir[i] = nn-&gt;rss_itbl[i];</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, nn-&gt;rss_key, nfp_net_rss_key_sz(nn));</div><div class='del'>-	if (hfunc) {</div><div class='del'>-		*hfunc = nn-&gt;rss_hfunc;</div><div class='del'>-		if (*hfunc &gt;= 1 &lt;&lt; ETH_RSS_HASH_FUNCS_COUNT)</div><div class='del'>-			*hfunc = ETH_RSS_HASH_UNKNOWN;</div><div class='del'>-	}</div><div class='add'>+			rxfh-&gt;indir[i] = nn-&gt;rss_itbl[i];</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, nn-&gt;rss_key, nfp_net_rss_key_sz(nn));</div><div class='add'>+</div><div class='add'>+	rxfh-&gt;hfunc = nn-&gt;rss_hfunc;</div><div class='add'>+	if (rxfh-&gt;hfunc &gt;= 1 &lt;&lt; ETH_RSS_HASH_FUNCS_COUNT)</div><div class='add'>+		rxfh-&gt;hfunc = ETH_RSS_HASH_UNKNOWN;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nfp_net_set_rxfh(struct net_device *netdev,</div><div class='del'>-			    const u32 *indir, const u8 *key,</div><div class='del'>-			    const u8 hfunc)</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct nfp_net *nn = netdev_priv(netdev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!(nn-&gt;cap &amp; NFP_NET_CFG_CTRL_RSS_ANY) ||</div><div class='del'>-	    !(hfunc == ETH_RSS_HASH_NO_CHANGE || hfunc == nn-&gt;rss_hfunc))</div><div class='add'>+	    !(rxfh-&gt;hfunc == ETH_RSS_HASH_NO_CHANGE ||</div><div class='add'>+	      rxfh-&gt;hfunc == nn-&gt;rss_hfunc))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!key &amp;&amp; !indir)</div><div class='add'>+	if (!rxfh-&gt;key &amp;&amp; !rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='del'>-		memcpy(nn-&gt;rss_key, key, nfp_net_rss_key_sz(nn));</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(nn-&gt;rss_key, rxfh-&gt;key, nfp_net_rss_key_sz(nn));</div><div class='ctx'> 		nfp_net_rss_write_key(nn);</div><div class='ctx'> 	}</div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(nn-&gt;rss_itbl); i++)</div><div class='del'>-			nn-&gt;rss_itbl[i] = indir[i];</div><div class='add'>+			nn-&gt;rss_itbl[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 		nfp_net_rss_write_itbl(nn);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1497,7 +1873,7 @@ static int nfp_net_get_coalesce(struct net_device *netdev,</div><div class='ctx'> 	struct nfp_net *nn = netdev_priv(netdev);</div><div class='ctx'> </div><div class='ctx'> 	if (!(nn-&gt;cap &amp; NFP_NET_CFG_CTRL_IRQMOD))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	ec-&gt;use_adaptive_rx_coalesce = nn-&gt;rx_coalesce_adapt_on;</div><div class='ctx'> 	ec-&gt;use_adaptive_tx_coalesce = nn-&gt;tx_coalesce_adapt_on;</div><div class='hunk'>@@ -1776,22 +2152,40 @@ static int nfp_net_set_coalesce(struct net_device *netdev,</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	if (!(nn-&gt;cap &amp; NFP_NET_CFG_CTRL_IRQMOD))</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	/* ensure valid configuration */</div><div class='del'>-	if (!ec-&gt;rx_coalesce_usecs &amp;&amp; !ec-&gt;rx_max_coalesced_frames)</div><div class='add'>+	if (!ec-&gt;rx_coalesce_usecs &amp;&amp; !ec-&gt;rx_max_coalesced_frames) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "rx-usecs and rx-frames cannot both be zero");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (!ec-&gt;tx_coalesce_usecs &amp;&amp; !ec-&gt;tx_max_coalesced_frames)</div><div class='add'>+	if (!ec-&gt;tx_coalesce_usecs &amp;&amp; !ec-&gt;tx_max_coalesced_frames) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "tx-usecs and tx-frames cannot both be zero");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (nfp_net_coalesce_para_check(ec-&gt;rx_coalesce_usecs * factor,</div><div class='del'>-					ec-&gt;rx_max_coalesced_frames))</div><div class='add'>+	if (nfp_net_coalesce_para_check(ec-&gt;rx_coalesce_usecs * factor)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "rx-usecs too large");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (nfp_net_coalesce_para_check(ec-&gt;tx_coalesce_usecs * factor,</div><div class='del'>-					ec-&gt;tx_max_coalesced_frames))</div><div class='add'>+	if (nfp_net_coalesce_para_check(ec-&gt;rx_max_coalesced_frames)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "rx-frames too large");</div><div class='ctx'> 		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (nfp_net_coalesce_para_check(ec-&gt;tx_coalesce_usecs * factor)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "tx-usecs too large");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (nfp_net_coalesce_para_check(ec-&gt;tx_max_coalesced_frames)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "tx-frames too large");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* configuration is valid */</div><div class='ctx'> 	nn-&gt;rx_coalesce_adapt_on = !!ec-&gt;use_adaptive_rx_coalesce;</div><div class='hunk'>@@ -1866,6 +2260,30 @@ static int nfp_net_set_channels(struct net_device *netdev,</div><div class='ctx'> 	return nfp_net_set_num_rings(nn, total_rx, total_tx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int nfp_port_set_pauseparam(struct net_device *netdev,</div><div class='add'>+				   struct ethtool_pauseparam *pause)</div><div class='add'>+{</div><div class='add'>+	struct nfp_eth_table_port *eth_port;</div><div class='add'>+	struct nfp_port *port;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	port = nfp_port_from_netdev(netdev);</div><div class='add'>+	eth_port = nfp_port_get_eth_port(port);</div><div class='add'>+	if (!eth_port)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (pause-&gt;autoneg != AUTONEG_DISABLE)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	err = nfp_eth_set_pauseparam(port-&gt;app-&gt;cpp, eth_port-&gt;index,</div><div class='add'>+				     pause-&gt;tx_pause, pause-&gt;rx_pause);</div><div class='add'>+	if (!err)</div><div class='add'>+		/* Only refresh if we did something */</div><div class='add'>+		nfp_net_refresh_port_table(port);</div><div class='add'>+</div><div class='add'>+	return err &lt; 0 ? err : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void nfp_port_get_pauseparam(struct net_device *netdev,</div><div class='ctx'> 				    struct ethtool_pauseparam *pause)</div><div class='ctx'> {</div><div class='hunk'>@@ -1877,10 +2295,10 @@ static void nfp_port_get_pauseparam(struct net_device *netdev,</div><div class='ctx'> 	if (!eth_port)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	/* Currently pause frame support is fixed */</div><div class='add'>+	/* Currently pause frame autoneg is fixed */</div><div class='ctx'> 	pause-&gt;autoneg = AUTONEG_DISABLE;</div><div class='del'>-	pause-&gt;rx_pause = 1;</div><div class='del'>-	pause-&gt;tx_pause = 1;</div><div class='add'>+	pause-&gt;rx_pause = eth_port-&gt;rx_pause;</div><div class='add'>+	pause-&gt;tx_pause = eth_port-&gt;tx_pause;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nfp_net_set_phys_id(struct net_device *netdev,</div><div class='hunk'>@@ -2106,8 +2524,10 @@ static const struct ethtool_ops nfp_net_ethtool_ops = {</div><div class='ctx'> 	.set_link_ksettings	= nfp_net_set_link_ksettings,</div><div class='ctx'> 	.get_fecparam		= nfp_port_get_fecparam,</div><div class='ctx'> 	.set_fecparam		= nfp_port_set_fecparam,</div><div class='add'>+	.set_pauseparam		= nfp_port_set_pauseparam,</div><div class='ctx'> 	.get_pauseparam		= nfp_port_get_pauseparam,</div><div class='ctx'> 	.set_phys_id		= nfp_net_set_phys_id,</div><div class='add'>+	.get_ts_info		= ethtool_op_get_ts_info,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct ethtool_ops nfp_port_ethtool_ops = {</div><div class='hunk'>@@ -2130,6 +2550,7 @@ const struct ethtool_ops nfp_port_ethtool_ops = {</div><div class='ctx'> 	.set_link_ksettings	= nfp_net_set_link_ksettings,</div><div class='ctx'> 	.get_fecparam		= nfp_port_get_fecparam,</div><div class='ctx'> 	.set_fecparam		= nfp_port_set_fecparam,</div><div class='add'>+	.set_pauseparam		= nfp_port_set_pauseparam,</div><div class='ctx'> 	.get_pauseparam		= nfp_port_get_pauseparam,</div><div class='ctx'> 	.set_phys_id		= nfp_net_set_phys_id,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h b/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h<br/>index 00264af13b49..dc0e405c1349 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h</a></div><div class='hunk'>@@ -189,6 +189,8 @@ enum nfp_ethtool_link_mode_list {</div><div class='ctx'>  * @ports.enabled:	is enabled?</div><div class='ctx'>  * @ports.tx_enabled:	is TX enabled?</div><div class='ctx'>  * @ports.rx_enabled:	is RX enabled?</div><div class='add'>+ * @ports.rx_pause:	Switch of RX pause frame</div><div class='add'>+ * @ports.tx_pause:	Switch of Tx pause frame</div><div class='ctx'>  * @ports.override_changed: is media reconfig pending?</div><div class='ctx'>  *</div><div class='ctx'>  * @ports.port_type:	one of %PORT_* defines for ethtool</div><div class='hunk'>@@ -227,6 +229,8 @@ struct nfp_eth_table {</div><div class='ctx'> 		bool tx_enabled;</div><div class='ctx'> 		bool rx_enabled;</div><div class='ctx'> 		bool supp_aneg;</div><div class='add'>+		bool rx_pause;</div><div class='add'>+		bool tx_pause;</div><div class='ctx'> </div><div class='ctx'> 		bool override_changed;</div><div class='ctx'> </div><div class='hunk'>@@ -255,6 +259,8 @@ int</div><div class='ctx'> nfp_eth_set_fec(struct nfp_cpp *cpp, unsigned int idx, enum nfp_eth_fec mode);</div><div class='ctx'> </div><div class='ctx'> int nfp_eth_set_idmode(struct nfp_cpp *cpp, unsigned int idx, bool state);</div><div class='add'>+int nfp_eth_set_pauseparam(struct nfp_cpp *cpp, unsigned int idx,</div><div class='add'>+			   unsigned int tx_pause, unsigned int rx_pause);</div><div class='ctx'> </div><div class='ctx'> static inline bool nfp_eth_can_support_fec(struct nfp_eth_table_port *eth_port)</div><div class='ctx'> {</div><div class='head'>diff --git a/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c b/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c<br/>index 9d62085d772a..5cfddc9a5d87 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c</a></div><div class='hunk'>@@ -42,6 +42,8 @@</div><div class='ctx'> #define NSP_ETH_STATE_ANEG		GENMASK_ULL(25, 23)</div><div class='ctx'> #define NSP_ETH_STATE_FEC		GENMASK_ULL(27, 26)</div><div class='ctx'> #define NSP_ETH_STATE_ACT_FEC		GENMASK_ULL(29, 28)</div><div class='add'>+#define NSP_ETH_STATE_TX_PAUSE		BIT_ULL(31)</div><div class='add'>+#define NSP_ETH_STATE_RX_PAUSE		BIT_ULL(32)</div><div class='ctx'> </div><div class='ctx'> #define NSP_ETH_CTRL_CONFIGURED		BIT_ULL(0)</div><div class='ctx'> #define NSP_ETH_CTRL_ENABLED		BIT_ULL(1)</div><div class='hunk'>@@ -52,6 +54,8 @@</div><div class='ctx'> #define NSP_ETH_CTRL_SET_ANEG		BIT_ULL(6)</div><div class='ctx'> #define NSP_ETH_CTRL_SET_FEC		BIT_ULL(7)</div><div class='ctx'> #define NSP_ETH_CTRL_SET_IDMODE		BIT_ULL(8)</div><div class='add'>+#define NSP_ETH_CTRL_SET_TX_PAUSE	BIT_ULL(10)</div><div class='add'>+#define NSP_ETH_CTRL_SET_RX_PAUSE	BIT_ULL(11)</div><div class='ctx'> </div><div class='ctx'> enum nfp_eth_raw {</div><div class='ctx'> 	NSP_ETH_RAW_PORT = 0,</div><div class='hunk'>@@ -180,6 +184,15 @@ nfp_eth_port_translate(struct nfp_nsp *nsp, const union eth_table_entry *src,</div><div class='ctx'> </div><div class='ctx'> 	dst-&gt;act_fec = FIELD_GET(NSP_ETH_STATE_ACT_FEC, state);</div><div class='ctx'> 	dst-&gt;supp_aneg = FIELD_GET(NSP_ETH_PORT_SUPP_ANEG, port);</div><div class='add'>+</div><div class='add'>+	if (nfp_nsp_get_abi_ver_minor(nsp) &lt; 37) {</div><div class='add'>+		dst-&gt;tx_pause = true;</div><div class='add'>+		dst-&gt;rx_pause = true;</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dst-&gt;tx_pause = FIELD_GET(NSP_ETH_STATE_TX_PAUSE, state);</div><div class='add'>+	dst-&gt;rx_pause = FIELD_GET(NSP_ETH_STATE_RX_PAUSE, state);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -497,7 +510,7 @@ int nfp_eth_set_configured(struct nfp_cpp *cpp, unsigned int idx, bool configed)</div><div class='ctx'> static int</div><div class='ctx'> nfp_eth_set_bit_config(struct nfp_nsp *nsp, unsigned int raw_idx,</div><div class='ctx'> 		       const u64 mask, const unsigned int shift,</div><div class='del'>-		       unsigned int val, const u64 ctrl_bit)</div><div class='add'>+		       u64 val, const u64 ctrl_bit)</div><div class='ctx'> {</div><div class='ctx'> 	union eth_table_entry *entries = nfp_nsp_config_entries(nsp);</div><div class='ctx'> 	unsigned int idx = nfp_nsp_config_idx(nsp);</div><div class='hunk'>@@ -630,6 +643,81 @@ nfp_eth_set_fec(struct nfp_cpp *cpp, unsigned int idx, enum nfp_eth_fec mode)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * __nfp_eth_set_txpause() - set tx pause control bit</div><div class='add'>+ * @nsp:	NFP NSP handle returned from nfp_eth_config_start()</div><div class='add'>+ * @tx_pause:	TX pause switch</div><div class='add'>+ *</div><div class='add'>+ * Set TX pause switch.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 or -ERRNO.</div><div class='add'>+ */</div><div class='add'>+static int __nfp_eth_set_txpause(struct nfp_nsp *nsp, unsigned int tx_pause)</div><div class='add'>+{</div><div class='add'>+	return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_STATE, NSP_ETH_STATE_TX_PAUSE,</div><div class='add'>+				      tx_pause, NSP_ETH_CTRL_SET_TX_PAUSE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __nfp_eth_set_rxpause() - set rx pause control bit</div><div class='add'>+ * @nsp:	NFP NSP handle returned from nfp_eth_config_start()</div><div class='add'>+ * @rx_pause:	RX pause switch</div><div class='add'>+ *</div><div class='add'>+ * Set RX pause switch.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 or -ERRNO.</div><div class='add'>+ */</div><div class='add'>+static int __nfp_eth_set_rxpause(struct nfp_nsp *nsp, unsigned int rx_pause)</div><div class='add'>+{</div><div class='add'>+	return NFP_ETH_SET_BIT_CONFIG(nsp, NSP_ETH_RAW_STATE, NSP_ETH_STATE_RX_PAUSE,</div><div class='add'>+				      rx_pause, NSP_ETH_CTRL_SET_RX_PAUSE);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * nfp_eth_set_pauseparam() - Set TX/RX pause switch.</div><div class='add'>+ * @cpp:	NFP CPP handle</div><div class='add'>+ * @idx:	NFP chip-wide port index</div><div class='add'>+ * @tx_pause:	TX pause switch</div><div class='add'>+ * @rx_pause:	RX pause switch</div><div class='add'>+ *</div><div class='add'>+ * Return:</div><div class='add'>+ * 0 - configuration successful;</div><div class='add'>+ * 1 - no changes were needed;</div><div class='add'>+ * -ERRNO - configuration failed.</div><div class='add'>+ */</div><div class='add'>+int</div><div class='add'>+nfp_eth_set_pauseparam(struct nfp_cpp *cpp, unsigned int idx,</div><div class='add'>+		       unsigned int tx_pause, unsigned int rx_pause)</div><div class='add'>+{</div><div class='add'>+	struct nfp_nsp *nsp;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	nsp = nfp_eth_config_start(cpp, idx);</div><div class='add'>+	if (IS_ERR(nsp))</div><div class='add'>+		return PTR_ERR(nsp);</div><div class='add'>+</div><div class='add'>+	if (nfp_nsp_get_abi_ver_minor(nsp) &lt; 37) {</div><div class='add'>+		nfp_err(nfp_nsp_cpp(nsp),</div><div class='add'>+			"set pause parameter operation not supported, please update flash\n");</div><div class='add'>+		nfp_eth_config_cleanup_end(nsp);</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = __nfp_eth_set_txpause(nsp, tx_pause);</div><div class='add'>+	if (err) {</div><div class='add'>+		nfp_eth_config_cleanup_end(nsp);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	err = __nfp_eth_set_rxpause(nsp, rx_pause);</div><div class='add'>+	if (err) {</div><div class='add'>+		nfp_eth_config_cleanup_end(nsp);</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return nfp_eth_config_commit_end(nsp);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * __nfp_eth_set_speed() - set interface speed/rate</div><div class='ctx'>  * @nsp:	NFP NSP handle returned from nfp_eth_config_start()</div><div class='ctx'>  * @speed:	Desired speed (per lane)</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h<br/>index 2453a40f6ee8..9ffef2e06885 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic.h</a></div><div class='hunk'>@@ -91,6 +91,4 @@ int ionic_port_identify(struct ionic *ionic);</div><div class='ctx'> int ionic_port_init(struct ionic *ionic);</div><div class='ctx'> int ionic_port_reset(struct ionic *ionic);</div><div class='ctx'> </div><div class='del'>-const char *ionic_vf_attr_to_str(enum ionic_vf_attr attr);</div><div class='del'>-</div><div class='ctx'> #endif /* _IONIC_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c<br/>index d6ce113a4210..c49aa358e424 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c</a></div><div class='hunk'>@@ -215,9 +215,16 @@ out:</div><div class='ctx'> </div><div class='ctx'> static void ionic_clear_pci(struct ionic *ionic)</div><div class='ctx'> {</div><div class='add'>+	ionic-&gt;idev.dev_info_regs = NULL;</div><div class='add'>+	ionic-&gt;idev.dev_cmd_regs = NULL;</div><div class='add'>+	ionic-&gt;idev.intr_status = NULL;</div><div class='add'>+	ionic-&gt;idev.intr_ctrl = NULL;</div><div class='add'>+</div><div class='ctx'> 	ionic_unmap_bars(ionic);</div><div class='ctx'> 	pci_release_regions(ionic-&gt;pdev);</div><div class='del'>-	pci_disable_device(ionic-&gt;pdev);</div><div class='add'>+</div><div class='add'>+	if (atomic_read(&amp;ionic-&gt;pdev-&gt;enable_cnt) &gt; 0)</div><div class='add'>+		pci_disable_device(ionic-&gt;pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ionic_setup_one(struct ionic *ionic)</div><div class='hunk'>@@ -389,9 +396,13 @@ static void ionic_remove(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic *ionic = pci_get_drvdata(pdev);</div><div class='ctx'> </div><div class='del'>-	del_timer_sync(&amp;ionic-&gt;watchdog_timer);</div><div class='add'>+	timer_shutdown_sync(&amp;ionic-&gt;watchdog_timer);</div><div class='ctx'> </div><div class='ctx'> 	if (ionic-&gt;lif) {</div><div class='add'>+		/* prevent adminq cmds if already known as down */</div><div class='add'>+		if (test_and_clear_bit(IONIC_LIF_F_FW_RESET, ionic-&gt;lif-&gt;state))</div><div class='add'>+			set_bit(IONIC_LIF_F_FW_STOPPING, ionic-&gt;lif-&gt;state);</div><div class='add'>+</div><div class='ctx'> 		ionic_lif_unregister(ionic-&gt;lif);</div><div class='ctx'> 		ionic_devlink_unregister(ionic);</div><div class='ctx'> 		ionic_lif_deinit(ionic-&gt;lif);</div><div class='hunk'>@@ -416,6 +427,8 @@ static void ionic_reset_prepare(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(ionic-&gt;dev, "%s: device stopping\n", __func__);</div><div class='ctx'> </div><div class='add'>+	set_bit(IONIC_LIF_F_FW_RESET, lif-&gt;state);</div><div class='add'>+</div><div class='ctx'> 	del_timer_sync(&amp;ionic-&gt;watchdog_timer);</div><div class='ctx'> 	cancel_work_sync(&amp;lif-&gt;deferred.work);</div><div class='ctx'> </div><div class='hunk'>@@ -424,6 +437,7 @@ static void ionic_reset_prepare(struct pci_dev *pdev)</div><div class='ctx'> 	ionic_txrx_free(lif);</div><div class='ctx'> 	ionic_lif_deinit(lif);</div><div class='ctx'> 	ionic_qcqs_free(lif);</div><div class='add'>+	ionic_debugfs_del_lif(lif);</div><div class='ctx'> 	mutex_unlock(&amp;lif-&gt;queue_lock);</div><div class='ctx'> </div><div class='ctx'> 	ionic_dev_teardown(ionic);</div><div class='hunk'>@@ -455,10 +469,35 @@ err_out:</div><div class='ctx'> 		__func__, err ? "failed" : "done");</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static pci_ers_result_t ionic_pci_error_detected(struct pci_dev *pdev,</div><div class='add'>+						 pci_channel_state_t error)</div><div class='add'>+{</div><div class='add'>+	if (error == pci_channel_io_frozen) {</div><div class='add'>+		ionic_reset_prepare(pdev);</div><div class='add'>+		return PCI_ERS_RESULT_NEED_RESET;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return PCI_ERS_RESULT_NONE;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ionic_pci_error_resume(struct pci_dev *pdev)</div><div class='add'>+{</div><div class='add'>+	struct ionic *ionic = pci_get_drvdata(pdev);</div><div class='add'>+	struct ionic_lif *lif = ionic-&gt;lif;</div><div class='add'>+</div><div class='add'>+	if (lif &amp;&amp; test_bit(IONIC_LIF_F_FW_RESET, lif-&gt;state))</div><div class='add'>+		pci_reset_function_locked(pdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct pci_error_handlers ionic_err_handler = {</div><div class='ctx'> 	/* FLR handling */</div><div class='ctx'> 	.reset_prepare      = ionic_reset_prepare,</div><div class='ctx'> 	.reset_done         = ionic_reset_done,</div><div class='add'>+</div><div class='add'>+	/* PCI bus error detected on this device */</div><div class='add'>+	.error_detected     = ionic_pci_error_detected,</div><div class='add'>+	.resume		    = ionic_pci_error_resume,</div><div class='add'>+</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static struct pci_driver ionic_driver = {</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c<br/>index c58217027564..91327ef670c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_debugfs.c</a></div><div class='hunk'>@@ -287,6 +287,9 @@ void ionic_debugfs_add_lif(struct ionic_lif *lif)</div><div class='ctx'> </div><div class='ctx'> void ionic_debugfs_del_lif(struct ionic_lif *lif)</div><div class='ctx'> {</div><div class='add'>+	if (!lif-&gt;dentry)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	debugfs_remove_recursive(lif-&gt;dentry);</div><div class='ctx'> 	lif-&gt;dentry = NULL;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c<br/>index c06576f43916..1e7c71f7f081 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_dev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_dev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_dev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_dev.c</a></div><div class='hunk'>@@ -165,9 +165,19 @@ void ionic_dev_teardown(struct ionic *ionic)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Devcmd Interface */</div><div class='del'>-bool ionic_is_fw_running(struct ionic_dev *idev)</div><div class='add'>+static bool __ionic_is_fw_running(struct ionic_dev *idev, u8 *status_ptr)</div><div class='ctx'> {</div><div class='del'>-	u8 fw_status = ioread8(&amp;idev-&gt;dev_info_regs-&gt;fw_status);</div><div class='add'>+	u8 fw_status;</div><div class='add'>+</div><div class='add'>+	if (!idev-&gt;dev_info_regs) {</div><div class='add'>+		if (status_ptr)</div><div class='add'>+			*status_ptr = 0xff;</div><div class='add'>+		return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	fw_status = ioread8(&amp;idev-&gt;dev_info_regs-&gt;fw_status);</div><div class='add'>+	if (status_ptr)</div><div class='add'>+		*status_ptr = fw_status;</div><div class='ctx'> </div><div class='ctx'> 	/* firmware is useful only if the running bit is set and</div><div class='ctx'> 	 * fw_status != 0xff (bad PCI read)</div><div class='hunk'>@@ -175,6 +185,11 @@ bool ionic_is_fw_running(struct ionic_dev *idev)</div><div class='ctx'> 	return (fw_status != 0xff) &amp;&amp; (fw_status &amp; IONIC_FW_STS_F_RUNNING);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+bool ionic_is_fw_running(struct ionic_dev *idev)</div><div class='add'>+{</div><div class='add'>+	return __ionic_is_fw_running(idev, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int ionic_heartbeat_check(struct ionic *ionic)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned long check_time, last_check_time;</div><div class='hunk'>@@ -199,10 +214,8 @@ do_check_time:</div><div class='ctx'> 		goto do_check_time;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	fw_status = ioread8(&amp;idev-&gt;dev_info_regs-&gt;fw_status);</div><div class='del'>-</div><div class='ctx'> 	/* If fw_status is not ready don't bother with the generation */</div><div class='del'>-	if (!ionic_is_fw_running(idev)) {</div><div class='add'>+	if (!__ionic_is_fw_running(idev, &amp;fw_status)) {</div><div class='ctx'> 		fw_status_ready = false;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		fw_generation = fw_status &amp; IONIC_FW_STS_F_GENERATION;</div><div class='hunk'>@@ -321,6 +334,7 @@ void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)</div><div class='ctx'> </div><div class='ctx'> void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)</div><div class='ctx'> {</div><div class='add'>+	idev-&gt;opcode = cmd-&gt;cmd.opcode;</div><div class='ctx'> 	memcpy_toio(&amp;idev-&gt;dev_cmd_regs-&gt;cmd, cmd, sizeof(*cmd));</div><div class='ctx'> 	iowrite32(0, &amp;idev-&gt;dev_cmd_regs-&gt;done);</div><div class='ctx'> 	iowrite32(1, &amp;idev-&gt;dev_cmd_regs-&gt;doorbell);</div><div class='hunk'>@@ -469,46 +483,6 @@ int ionic_set_vf_config(struct ionic *ionic, int vf,</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ionic_dev_cmd_vf_getattr(struct ionic *ionic, int vf, u8 attr,</div><div class='del'>-			     struct ionic_vf_getattr_comp *comp)</div><div class='del'>-{</div><div class='del'>-	union ionic_dev_cmd cmd = {</div><div class='del'>-		.vf_getattr.opcode = IONIC_CMD_VF_GETATTR,</div><div class='del'>-		.vf_getattr.attr = attr,</div><div class='del'>-		.vf_getattr.vf_index = cpu_to_le16(vf),</div><div class='del'>-	};</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	if (vf &gt;= ionic-&gt;num_vfs)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	switch (attr) {</div><div class='del'>-	case IONIC_VF_ATTR_SPOOFCHK:</div><div class='del'>-	case IONIC_VF_ATTR_TRUST:</div><div class='del'>-	case IONIC_VF_ATTR_LINKSTATE:</div><div class='del'>-	case IONIC_VF_ATTR_MAC:</div><div class='del'>-	case IONIC_VF_ATTR_VLAN:</div><div class='del'>-	case IONIC_VF_ATTR_RATE:</div><div class='del'>-		break;</div><div class='del'>-	case IONIC_VF_ATTR_STATSADDR:</div><div class='del'>-	default:</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mutex_lock(&amp;ionic-&gt;dev_cmd_lock);</div><div class='del'>-	ionic_dev_cmd_go(&amp;ionic-&gt;idev, &amp;cmd);</div><div class='del'>-	err = ionic_dev_cmd_wait_nomsg(ionic, DEVCMD_TIMEOUT);</div><div class='del'>-	memcpy_fromio(comp, &amp;ionic-&gt;idev.dev_cmd_regs-&gt;comp.vf_getattr,</div><div class='del'>-		      sizeof(*comp));</div><div class='del'>-	mutex_unlock(&amp;ionic-&gt;dev_cmd_lock);</div><div class='del'>-</div><div class='del'>-	if (err &amp;&amp; comp-&gt;status != IONIC_RC_ENOSUPP)</div><div class='del'>-		ionic_dev_cmd_dev_err_print(ionic, cmd.vf_getattr.opcode,</div><div class='del'>-					    comp-&gt;status, err);</div><div class='del'>-</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> void ionic_vf_start(struct ionic *ionic)</div><div class='ctx'> {</div><div class='ctx'> 	union ionic_dev_cmd cmd = {</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h<br/>index 1dbc3cb50b1d..2667e1cde16b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_dev.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_dev.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_dev.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_dev.h</a></div><div class='hunk'>@@ -153,6 +153,7 @@ struct ionic_dev {</div><div class='ctx'> 	bool fw_hb_ready;</div><div class='ctx'> 	bool fw_status_ready;</div><div class='ctx'> 	u8 fw_generation;</div><div class='add'>+	u8 opcode;</div><div class='ctx'> </div><div class='ctx'> 	u64 __iomem *db_pages;</div><div class='ctx'> 	dma_addr_t phy_db_pages;</div><div class='hunk'>@@ -223,7 +224,7 @@ struct ionic_desc_info {</div><div class='ctx'> 	void *cb_arg;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-#define IONIC_QUEUE_NAME_MAX_SZ		32</div><div class='add'>+#define IONIC_QUEUE_NAME_MAX_SZ		16</div><div class='ctx'> </div><div class='ctx'> struct ionic_queue {</div><div class='ctx'> 	struct device *dev;</div><div class='hunk'>@@ -269,12 +270,12 @@ struct ionic_queue {</div><div class='ctx'> </div><div class='ctx'> struct ionic_intr_info {</div><div class='ctx'> 	char name[IONIC_INTR_NAME_MAX_SZ];</div><div class='add'>+	u64 rearm_count;</div><div class='ctx'> 	unsigned int index;</div><div class='ctx'> 	unsigned int vector;</div><div class='del'>-	u64 rearm_count;</div><div class='ctx'> 	unsigned int cpu;</div><div class='del'>-	cpumask_t affinity_mask;</div><div class='ctx'> 	u32 dim_coal_hw;</div><div class='add'>+	cpumask_t affinity_mask;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ionic_cq {</div><div class='hunk'>@@ -341,8 +342,7 @@ void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);</div><div class='ctx'> </div><div class='ctx'> int ionic_set_vf_config(struct ionic *ionic, int vf,</div><div class='ctx'> 			struct ionic_vf_setattr_cmd *vfc);</div><div class='del'>-int ionic_dev_cmd_vf_getattr(struct ionic *ionic, int vf, u8 attr,</div><div class='del'>-			     struct ionic_vf_getattr_comp *comp);</div><div class='add'>+</div><div class='ctx'> void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,</div><div class='ctx'> 				  u16 lif_type, u8 qtype, u8 qver);</div><div class='ctx'> void ionic_vf_start(struct ionic *ionic);</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c<br/>index 3a6b0a9bc241..cd3c0b01402e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_ethtool.c</a></div><div class='hunk'>@@ -823,36 +823,38 @@ static u32 ionic_get_rxfh_key_size(struct net_device *netdev)</div><div class='ctx'> 	return IONIC_RSS_HASH_KEY_SIZE;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ionic_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,</div><div class='del'>-			  u8 *hfunc)</div><div class='add'>+static int ionic_get_rxfh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic_lif *lif = netdev_priv(netdev);</div><div class='ctx'> 	unsigned int i, tbl_sz;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		tbl_sz = le16_to_cpu(lif-&gt;ionic-&gt;ident.lif.eth.rss_ind_tbl_sz);</div><div class='ctx'> 		for (i = 0; i &lt; tbl_sz; i++)</div><div class='del'>-			indir[i] = lif-&gt;rss_ind_tbl[i];</div><div class='add'>+			rxfh-&gt;indir[i] = lif-&gt;rss_ind_tbl[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, lif-&gt;rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, lif-&gt;rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ionic_set_rxfh(struct net_device *netdev, const u32 *indir,</div><div class='del'>-			  const u8 *key, const u8 hfunc)</div><div class='add'>+static int ionic_set_rxfh(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			  struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic_lif *lif = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	return ionic_lif_rss_config(lif, lif-&gt;rss_types, key, indir);</div><div class='add'>+	return ionic_lif_rss_config(lif, lif-&gt;rss_types,</div><div class='add'>+				    rxfh-&gt;key, rxfh-&gt;indir);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ionic_set_tunable(struct net_device *dev,</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c<br/>index edc14730ce88..cf2d5ad7b68c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_lif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_lif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_lif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_lif.c</a></div><div class='hunk'>@@ -49,24 +49,24 @@ static void ionic_lif_queue_identify(struct ionic_lif *lif);</div><div class='ctx'> static void ionic_dim_work(struct work_struct *work)</div><div class='ctx'> {</div><div class='ctx'> 	struct dim *dim = container_of(work, struct dim, work);</div><div class='add'>+	struct ionic_intr_info *intr;</div><div class='ctx'> 	struct dim_cq_moder cur_moder;</div><div class='ctx'> 	struct ionic_qcq *qcq;</div><div class='add'>+	struct ionic_lif *lif;</div><div class='ctx'> 	u32 new_coal;</div><div class='ctx'> </div><div class='ctx'> 	cur_moder = net_dim_get_rx_moderation(dim-&gt;mode, dim-&gt;profile_ix);</div><div class='ctx'> 	qcq = container_of(dim, struct ionic_qcq, dim);</div><div class='del'>-	new_coal = ionic_coal_usec_to_hw(qcq-&gt;q.lif-&gt;ionic, cur_moder.usec);</div><div class='add'>+	lif = qcq-&gt;q.lif;</div><div class='add'>+	new_coal = ionic_coal_usec_to_hw(lif-&gt;ionic, cur_moder.usec);</div><div class='ctx'> 	new_coal = new_coal ? new_coal : 1;</div><div class='ctx'> </div><div class='del'>-	if (qcq-&gt;intr.dim_coal_hw != new_coal) {</div><div class='del'>-		unsigned int qi = qcq-&gt;cq.bound_q-&gt;index;</div><div class='del'>-		struct ionic_lif *lif = qcq-&gt;q.lif;</div><div class='del'>-</div><div class='del'>-		qcq-&gt;intr.dim_coal_hw = new_coal;</div><div class='add'>+	intr = &amp;qcq-&gt;intr;</div><div class='add'>+	if (intr-&gt;dim_coal_hw != new_coal) {</div><div class='add'>+		intr-&gt;dim_coal_hw = new_coal;</div><div class='ctx'> </div><div class='ctx'> 		ionic_intr_coal_init(lif-&gt;ionic-&gt;idev.intr_ctrl,</div><div class='del'>-				     lif-&gt;rxqcqs[qi]-&gt;intr.index,</div><div class='del'>-				     qcq-&gt;intr.dim_coal_hw);</div><div class='add'>+				     intr-&gt;index, intr-&gt;dim_coal_hw);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	dim-&gt;state = DIM_START_MEASURE;</div><div class='hunk'>@@ -424,14 +424,10 @@ static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)</div><div class='ctx'> </div><div class='ctx'> 	ionic_qcq_intr_free(lif, qcq);</div><div class='ctx'> </div><div class='del'>-	if (qcq-&gt;cq.info) {</div><div class='del'>-		vfree(qcq-&gt;cq.info);</div><div class='del'>-		qcq-&gt;cq.info = NULL;</div><div class='del'>-	}</div><div class='del'>-	if (qcq-&gt;q.info) {</div><div class='del'>-		vfree(qcq-&gt;q.info);</div><div class='del'>-		qcq-&gt;q.info = NULL;</div><div class='del'>-	}</div><div class='add'>+	vfree(qcq-&gt;cq.info);</div><div class='add'>+	qcq-&gt;cq.info = NULL;</div><div class='add'>+	vfree(qcq-&gt;q.info);</div><div class='add'>+	qcq-&gt;q.info = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void ionic_qcqs_free(struct ionic_lif *lif)</div><div class='hunk'>@@ -2332,82 +2328,11 @@ static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ionic_get_fw_vf_config(struct ionic *ionic, int vf, struct ionic_vf *vfdata)</div><div class='del'>-{</div><div class='del'>-	struct ionic_vf_getattr_comp comp = { 0 };</div><div class='del'>-	int err;</div><div class='del'>-	u8 attr;</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_VLAN;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err)</div><div class='del'>-		vfdata-&gt;vlanid = comp.vlanid;</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_SPOOFCHK;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err)</div><div class='del'>-		vfdata-&gt;spoofchk = comp.spoofchk;</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_LINKSTATE;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err) {</div><div class='del'>-		switch (comp.linkstate) {</div><div class='del'>-		case IONIC_VF_LINK_STATUS_UP:</div><div class='del'>-			vfdata-&gt;linkstate = IFLA_VF_LINK_STATE_ENABLE;</div><div class='del'>-			break;</div><div class='del'>-		case IONIC_VF_LINK_STATUS_DOWN:</div><div class='del'>-			vfdata-&gt;linkstate = IFLA_VF_LINK_STATE_DISABLE;</div><div class='del'>-			break;</div><div class='del'>-		case IONIC_VF_LINK_STATUS_AUTO:</div><div class='del'>-			vfdata-&gt;linkstate = IFLA_VF_LINK_STATE_AUTO;</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			dev_warn(ionic-&gt;dev, "Unexpected link state %u\n", comp.linkstate);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_RATE;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err)</div><div class='del'>-		vfdata-&gt;maxrate = comp.maxrate;</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_TRUST;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err)</div><div class='del'>-		vfdata-&gt;trusted = comp.trust;</div><div class='del'>-</div><div class='del'>-	attr = IONIC_VF_ATTR_MAC;</div><div class='del'>-	err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &amp;comp);</div><div class='del'>-	if (err &amp;&amp; comp.status != IONIC_RC_ENOSUPP)</div><div class='del'>-		goto err_out;</div><div class='del'>-	if (!err)</div><div class='del'>-		ether_addr_copy(vfdata-&gt;macaddr, comp.macaddr);</div><div class='del'>-</div><div class='del'>-err_out:</div><div class='del'>-	if (err)</div><div class='del'>-		dev_err(ionic-&gt;dev, "Failed to get %s for VF %d\n",</div><div class='del'>-			ionic_vf_attr_to_str(attr), vf);</div><div class='del'>-</div><div class='del'>-	return err;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int ionic_get_vf_config(struct net_device *netdev,</div><div class='ctx'> 			       int vf, struct ifla_vf_info *ivf)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic_lif *lif = netdev_priv(netdev);</div><div class='ctx'> 	struct ionic *ionic = lif-&gt;ionic;</div><div class='del'>-	struct ionic_vf vfdata = { 0 };</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (!netif_device_present(netdev))</div><div class='hunk'>@@ -2418,18 +2343,16 @@ static int ionic_get_vf_config(struct net_device *netdev,</div><div class='ctx'> 	if (vf &gt;= pci_num_vf(ionic-&gt;pdev) || !ionic-&gt;vfs) {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 	} else {</div><div class='del'>-		ivf-&gt;vf = vf;</div><div class='del'>-		ivf-&gt;qos = 0;</div><div class='del'>-</div><div class='del'>-		ret = ionic_get_fw_vf_config(ionic, vf, &amp;vfdata);</div><div class='del'>-		if (!ret) {</div><div class='del'>-			ivf-&gt;vlan         = le16_to_cpu(vfdata.vlanid);</div><div class='del'>-			ivf-&gt;spoofchk     = vfdata.spoofchk;</div><div class='del'>-			ivf-&gt;linkstate    = vfdata.linkstate;</div><div class='del'>-			ivf-&gt;max_tx_rate  = le32_to_cpu(vfdata.maxrate);</div><div class='del'>-			ivf-&gt;trusted      = vfdata.trusted;</div><div class='del'>-			ether_addr_copy(ivf-&gt;mac, vfdata.macaddr);</div><div class='del'>-		}</div><div class='add'>+		struct ionic_vf *vfdata = &amp;ionic-&gt;vfs[vf];</div><div class='add'>+</div><div class='add'>+		ivf-&gt;vf		  = vf;</div><div class='add'>+		ivf-&gt;qos	  = 0;</div><div class='add'>+		ivf-&gt;vlan         = le16_to_cpu(vfdata-&gt;vlanid);</div><div class='add'>+		ivf-&gt;spoofchk     = vfdata-&gt;spoofchk;</div><div class='add'>+		ivf-&gt;linkstate    = vfdata-&gt;linkstate;</div><div class='add'>+		ivf-&gt;max_tx_rate  = le32_to_cpu(vfdata-&gt;maxrate);</div><div class='add'>+		ivf-&gt;trusted      = vfdata-&gt;trusted;</div><div class='add'>+		ether_addr_copy(ivf-&gt;mac, vfdata-&gt;macaddr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	up_read(&amp;ionic-&gt;vf_op_lock);</div><div class='hunk'>@@ -3127,6 +3050,7 @@ int ionic_lif_alloc(struct ionic *ionic)</div><div class='ctx'> 	lif = netdev_priv(netdev);</div><div class='ctx'> 	lif-&gt;netdev = netdev;</div><div class='ctx'> 	ionic-&gt;lif = lif;</div><div class='add'>+	lif-&gt;ionic = ionic;</div><div class='ctx'> 	netdev-&gt;netdev_ops = &amp;ionic_netdev_ops;</div><div class='ctx'> 	ionic_ethtool_set_ops(netdev);</div><div class='ctx'> </div><div class='hunk'>@@ -3149,7 +3073,6 @@ int ionic_lif_alloc(struct ionic *ionic)</div><div class='ctx'> 	lif-&gt;neqs = ionic-&gt;neqs_per_lif;</div><div class='ctx'> 	lif-&gt;nxqs = ionic-&gt;ntxqs_per_lif;</div><div class='ctx'> </div><div class='del'>-	lif-&gt;ionic = ionic;</div><div class='ctx'> 	lif-&gt;index = 0;</div><div class='ctx'> </div><div class='ctx'> 	if (is_kdump_kernel()) {</div><div class='hunk'>@@ -3238,6 +3161,9 @@ static void ionic_lif_reset(struct ionic_lif *lif)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic_dev *idev = &amp;lif-&gt;ionic-&gt;idev;</div><div class='ctx'> </div><div class='add'>+	if (!ionic_is_fw_running(idev))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	mutex_lock(&amp;lif-&gt;ionic-&gt;dev_cmd_lock);</div><div class='ctx'> 	ionic_dev_cmd_lif_reset(idev, lif-&gt;index);</div><div class='ctx'> 	ionic_dev_cmd_wait(lif-&gt;ionic, DEVCMD_TIMEOUT);</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h<br/>index 457c24195ca6..61548b3eea93 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_lif.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_lif.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_lif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_lif.h</a></div><div class='hunk'>@@ -312,6 +312,11 @@ static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs)</div><div class='ctx'> 	return (usecs * mult) / div;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static inline bool ionic_txq_hwstamp_enabled(struct ionic_queue *q)</div><div class='add'>+{</div><div class='add'>+	return unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep);</div><div class='ctx'> void ionic_get_stats64(struct net_device *netdev,</div><div class='ctx'> 		       struct rtnl_link_stats64 *ns);</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c<br/>index 835577392178..165ab08ad2dd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_main.c</a></div><div class='hunk'>@@ -188,28 +188,6 @@ static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-const char *ionic_vf_attr_to_str(enum ionic_vf_attr attr)</div><div class='del'>-{</div><div class='del'>-	switch (attr) {</div><div class='del'>-	case IONIC_VF_ATTR_SPOOFCHK:</div><div class='del'>-		return "IONIC_VF_ATTR_SPOOFCHK";</div><div class='del'>-	case IONIC_VF_ATTR_TRUST:</div><div class='del'>-		return "IONIC_VF_ATTR_TRUST";</div><div class='del'>-	case IONIC_VF_ATTR_LINKSTATE:</div><div class='del'>-		return "IONIC_VF_ATTR_LINKSTATE";</div><div class='del'>-	case IONIC_VF_ATTR_MAC:</div><div class='del'>-		return "IONIC_VF_ATTR_MAC";</div><div class='del'>-	case IONIC_VF_ATTR_VLAN:</div><div class='del'>-		return "IONIC_VF_ATTR_VLAN";</div><div class='del'>-	case IONIC_VF_ATTR_RATE:</div><div class='del'>-		return "IONIC_VF_ATTR_RATE";</div><div class='del'>-	case IONIC_VF_ATTR_STATSADDR:</div><div class='del'>-		return "IONIC_VF_ATTR_STATSADDR";</div><div class='del'>-	default:</div><div class='del'>-		return "IONIC_VF_ATTR_UNKNOWN";</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void ionic_adminq_flush(struct ionic_lif *lif)</div><div class='ctx'> {</div><div class='ctx'> 	struct ionic_desc_info *desc_info;</div><div class='hunk'>@@ -410,22 +388,28 @@ int ionic_adminq_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx,</div><div class='ctx'> 				      do_msg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)</div><div class='add'>+static int __ionic_adminq_post_wait(struct ionic_lif *lif,</div><div class='add'>+				    struct ionic_admin_ctx *ctx,</div><div class='add'>+				    const bool do_msg)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='add'>+	if (!ionic_is_fw_running(&amp;lif-&gt;ionic-&gt;idev))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='ctx'> 	err = ionic_adminq_post(lif, ctx);</div><div class='ctx'> </div><div class='del'>-	return ionic_adminq_wait(lif, ctx, err, true);</div><div class='add'>+	return ionic_adminq_wait(lif, ctx, err, do_msg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ionic_adminq_post_wait_nomsg(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)</div><div class='add'>+int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)</div><div class='ctx'> {</div><div class='del'>-	int err;</div><div class='del'>-</div><div class='del'>-	err = ionic_adminq_post(lif, ctx);</div><div class='add'>+	return __ionic_adminq_post_wait(lif, ctx, true);</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	return ionic_adminq_wait(lif, ctx, err, false);</div><div class='add'>+int ionic_adminq_post_wait_nomsg(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)</div><div class='add'>+{</div><div class='add'>+	return __ionic_adminq_post_wait(lif, ctx, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ionic_dev_cmd_clean(struct ionic *ionic)</div><div class='hunk'>@@ -465,7 +449,7 @@ static int __ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds,</div><div class='ctx'> 	 */</div><div class='ctx'> 	max_wait = jiffies + (max_seconds * HZ);</div><div class='ctx'> try_again:</div><div class='del'>-	opcode = readb(&amp;idev-&gt;dev_cmd_regs-&gt;cmd.cmd.opcode);</div><div class='add'>+	opcode = idev-&gt;opcode;</div><div class='ctx'> 	start_time = jiffies;</div><div class='ctx'> 	for (fw_up = ionic_is_fw_running(idev);</div><div class='ctx'> 	     !done &amp;&amp; fw_up &amp;&amp; time_before(jiffies, max_wait);</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_stats.c b/drivers/net/ethernet/pensando/ionic/ionic_stats.c<br/>index 9859a4432985..1f6022fb7679 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_stats.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_stats.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_stats.c</a></div><div class='hunk'>@@ -258,10 +258,10 @@ static void ionic_sw_stats_get_strings(struct ionic_lif *lif, u8 **buf)</div><div class='ctx'> 	int i, q_num;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IONIC_NUM_LIF_STATS; i++)</div><div class='del'>-		ethtool_sprintf(buf, ionic_lif_stats_desc[i].name);</div><div class='add'>+		ethtool_puts(buf, ionic_lif_stats_desc[i].name);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; IONIC_NUM_PORT_STATS; i++)</div><div class='del'>-		ethtool_sprintf(buf, ionic_port_stats_desc[i].name);</div><div class='add'>+		ethtool_puts(buf, ionic_port_stats_desc[i].name);</div><div class='ctx'> </div><div class='ctx'> 	for (q_num = 0; q_num &lt; MAX_Q(lif); q_num++)</div><div class='ctx'> 		ionic_sw_stats_get_tx_strings(lif, buf, q_num);</div><div class='head'>diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.c b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c<br/>index ccc1b1d407e4..54cd96b035d6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/pensando/ionic/ionic_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/pensando/ionic/ionic_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/pensando/ionic/ionic_txrx.c</a></div><div class='hunk'>@@ -803,7 +803,7 @@ static void ionic_tx_clean(struct ionic_queue *q,</div><div class='ctx'> </div><div class='ctx'> 	qi = skb_get_queue_mapping(skb);</div><div class='ctx'> </div><div class='del'>-	if (unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP)) {</div><div class='add'>+	if (ionic_txq_hwstamp_enabled(q)) {</div><div class='ctx'> 		if (cq_info) {</div><div class='ctx'> 			struct skb_shared_hwtstamps hwts = {};</div><div class='ctx'> 			__le64 *cq_desc_hwstamp;</div><div class='hunk'>@@ -870,7 +870,7 @@ bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info)</div><div class='ctx'> 		desc_info-&gt;cb_arg = NULL;</div><div class='ctx'> 	} while (index != le16_to_cpu(comp-&gt;comp_index));</div><div class='ctx'> </div><div class='del'>-	if (pkts &amp;&amp; bytes &amp;&amp; !unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP))</div><div class='add'>+	if (pkts &amp;&amp; bytes &amp;&amp; !ionic_txq_hwstamp_enabled(q))</div><div class='ctx'> 		netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='hunk'>@@ -908,7 +908,7 @@ void ionic_tx_empty(struct ionic_queue *q)</div><div class='ctx'> 		desc_info-&gt;cb_arg = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (pkts &amp;&amp; bytes &amp;&amp; !unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP))</div><div class='add'>+	if (pkts &amp;&amp; bytes &amp;&amp; !ionic_txq_hwstamp_enabled(q))</div><div class='ctx'> 		netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -986,7 +986,7 @@ static void ionic_tx_tso_post(struct ionic_queue *q,</div><div class='ctx'> </div><div class='ctx'> 	if (start) {</div><div class='ctx'> 		skb_tx_timestamp(skb);</div><div class='del'>-		if (!unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP))</div><div class='add'>+		if (!ionic_txq_hwstamp_enabled(q))</div><div class='ctx'> 			netdev_tx_sent_queue(q_to_ndq(q), skb-&gt;len);</div><div class='ctx'> 		ionic_txq_post(q, false, ionic_tx_clean, skb);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1233,7 +1233,7 @@ static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb)</div><div class='ctx'> 	stats-&gt;pkts++;</div><div class='ctx'> 	stats-&gt;bytes += skb-&gt;len;</div><div class='ctx'> </div><div class='del'>-	if (!unlikely(q-&gt;features &amp; IONIC_TXQ_F_HWSTAMP))</div><div class='add'>+	if (!ionic_txq_hwstamp_enabled(q))</div><div class='ctx'> 		netdev_tx_sent_queue(q_to_ndq(q), skb-&gt;len);</div><div class='ctx'> 	ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c<br/>index 65e20693c549..33f4f58ee51c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qed/qed_cxt.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qlogic/qed/qed_cxt.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qed/qed_cxt.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qed/qed_cxt.c</a></div><div class='hunk'>@@ -933,6 +933,7 @@ static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn)</div><div class='ctx'> 		p_dma-&gt;virt_addr = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> 	kfree(p_mngr-&gt;ilt_shadow);</div><div class='add'>+	p_mngr-&gt;ilt_shadow = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn,</div><div class='head'>diff --git a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c<br/>index b6b849a079ed..0e240b5ab8d4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qede/qede_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qlogic/qede/qede_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qede/qede_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qede/qede_ethtool.c</a></div><div class='hunk'>@@ -1370,28 +1370,29 @@ static u32 qede_get_rxfh_key_size(struct net_device *dev)</div><div class='ctx'> 	return sizeof(edev-&gt;rss_key);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qede_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+static int qede_get_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct qede_dev *edev = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; QED_RSS_IND_TABLE_SIZE; i++)</div><div class='del'>-		indir[i] = edev-&gt;rss_ind_table[i];</div><div class='add'>+		rxfh-&gt;indir[i] = edev-&gt;rss_ind_table[i];</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, edev-&gt;rss_key, qede_get_rxfh_key_size(dev));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, edev-&gt;rss_key, qede_get_rxfh_key_size(dev));</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qede_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='add'>+static int qede_set_rxfh(struct net_device *dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct qed_update_vport_params *vport_update_params;</div><div class='ctx'> 	struct qede_dev *edev = netdev_priv(dev);</div><div class='hunk'>@@ -1403,20 +1404,21 @@ static int qede_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (!indir &amp;&amp; !key)</div><div class='add'>+	if (!rxfh-&gt;indir &amp;&amp; !rxfh-&gt;key)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; QED_RSS_IND_TABLE_SIZE; i++)</div><div class='del'>-			edev-&gt;rss_ind_table[i] = indir[i];</div><div class='add'>+			edev-&gt;rss_ind_table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 		edev-&gt;rss_params_inited |= QEDE_RSS_INDIR_INITED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key) {</div><div class='del'>-		memcpy(&amp;edev-&gt;rss_key, key, qede_get_rxfh_key_size(dev));</div><div class='add'>+	if (rxfh-&gt;key) {</div><div class='add'>+		memcpy(&amp;edev-&gt;rss_key, rxfh-&gt;key, qede_get_rxfh_key_size(dev));</div><div class='ctx'> 		edev-&gt;rss_params_inited |= QEDE_RSS_KEY_INITED;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/qlogic/qla3xxx.c b/drivers/net/ethernet/qlogic/qla3xxx.c<br/>index 0d57ffcedf0c..fc78bc959ded 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qla3xxx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qlogic/qla3xxx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qla3xxx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qla3xxx.c</a></div><div class='hunk'>@@ -2591,6 +2591,7 @@ static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)</div><div class='ctx'> </div><div class='ctx'> 	if (qdev-&gt;lrg_buf_q_alloc_virt_addr == NULL) {</div><div class='ctx'> 		netdev_err(qdev-&gt;ndev, "lBufQ failed\n");</div><div class='add'>+		kfree(qdev-&gt;lrg_buf);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> 	qdev-&gt;lrg_buf_q_virt_addr = qdev-&gt;lrg_buf_q_alloc_virt_addr;</div><div class='hunk'>@@ -2615,6 +2616,7 @@ static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)</div><div class='ctx'> 				  qdev-&gt;lrg_buf_q_alloc_size,</div><div class='ctx'> 				  qdev-&gt;lrg_buf_q_alloc_virt_addr,</div><div class='ctx'> 				  qdev-&gt;lrg_buf_q_alloc_phy_addr);</div><div class='add'>+		kfree(qdev-&gt;lrg_buf);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c<br/>index c95d56e56c59..b733374b4dc5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c</a></div><div class='hunk'>@@ -2092,8 +2092,8 @@ static int qlcnic_83xx_run_post(struct qlcnic_adapter *adapter)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	strncpy(fw_info-&gt;fw_file_name, QLC_83XX_POST_FW_FILE_NAME,</div><div class='del'>-		QLC_FW_FILE_NAME_LEN);</div><div class='add'>+	strscpy(fw_info-&gt;fw_file_name, QLC_83XX_POST_FW_FILE_NAME,</div><div class='add'>+		sizeof(fw_info-&gt;fw_file_name));</div><div class='ctx'> </div><div class='ctx'> 	ret = request_firmware(&amp;fw_info-&gt;fw, fw_info-&gt;fw_file_name, dev);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -2396,12 +2396,12 @@ static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)</div><div class='ctx'> 		switch (pdev-&gt;device) {</div><div class='ctx'> 		case PCI_DEVICE_ID_QLOGIC_QLE834X:</div><div class='ctx'> 		case PCI_DEVICE_ID_QLOGIC_QLE8830:</div><div class='del'>-			strncpy(fw_info-&gt;fw_file_name, QLC_83XX_FW_FILE_NAME,</div><div class='del'>-				QLC_FW_FILE_NAME_LEN);</div><div class='add'>+			strscpy(fw_info-&gt;fw_file_name, QLC_83XX_FW_FILE_NAME,</div><div class='add'>+				sizeof(fw_info-&gt;fw_file_name));</div><div class='ctx'> 			break;</div><div class='ctx'> 		case PCI_DEVICE_ID_QLOGIC_QLE844X:</div><div class='del'>-			strncpy(fw_info-&gt;fw_file_name, QLC_84XX_FW_FILE_NAME,</div><div class='del'>-				QLC_FW_FILE_NAME_LEN);</div><div class='add'>+			strscpy(fw_info-&gt;fw_file_name, QLC_84XX_FW_FILE_NAME,</div><div class='add'>+				sizeof(fw_info-&gt;fw_file_name));</div><div class='ctx'> 			break;</div><div class='ctx'> 		default:</div><div class='ctx'> 			dev_err(&amp;pdev-&gt;dev, "%s: Invalid device id\n",</div><div class='head'>diff --git a/drivers/net/ethernet/qualcomm/qca_debug.c b/drivers/net/ethernet/qualcomm/qca_debug.c<br/>index 6f2fa2a42770..1822f2ad8f0d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qualcomm/qca_debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_debug.c</a></div><div class='hunk'>@@ -30,6 +30,8 @@</div><div class='ctx'> </div><div class='ctx'> #define QCASPI_MAX_REGS 0x20</div><div class='ctx'> </div><div class='add'>+#define QCASPI_RX_MAX_FRAMES 4</div><div class='add'>+</div><div class='ctx'> static const u16 qcaspi_spi_regs[] = {</div><div class='ctx'> 	SPI_REG_BFR_SIZE,</div><div class='ctx'> 	SPI_REG_WRBUF_SPC_AVA,</div><div class='hunk'>@@ -252,9 +254,9 @@ qcaspi_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring,</div><div class='ctx'> {</div><div class='ctx'> 	struct qcaspi *qca = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	ring-&gt;rx_max_pending = 4;</div><div class='add'>+	ring-&gt;rx_max_pending = QCASPI_RX_MAX_FRAMES;</div><div class='ctx'> 	ring-&gt;tx_max_pending = TX_RING_MAX_LEN;</div><div class='del'>-	ring-&gt;rx_pending = 4;</div><div class='add'>+	ring-&gt;rx_pending = QCASPI_RX_MAX_FRAMES;</div><div class='ctx'> 	ring-&gt;tx_pending = qca-&gt;txr.count;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -263,22 +265,21 @@ qcaspi_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ring,</div><div class='ctx'> 		     struct kernel_ethtool_ringparam *kernel_ring,</div><div class='ctx'> 		     struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='del'>-	const struct net_device_ops *ops = dev-&gt;netdev_ops;</div><div class='ctx'> 	struct qcaspi *qca = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	if ((ring-&gt;rx_pending) ||</div><div class='add'>+	if (ring-&gt;rx_pending != QCASPI_RX_MAX_FRAMES ||</div><div class='ctx'> 	    (ring-&gt;rx_mini_pending) ||</div><div class='ctx'> 	    (ring-&gt;rx_jumbo_pending))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (netif_running(dev))</div><div class='del'>-		ops-&gt;ndo_stop(dev);</div><div class='add'>+	if (qca-&gt;spi_thread)</div><div class='add'>+		kthread_park(qca-&gt;spi_thread);</div><div class='ctx'> </div><div class='ctx'> 	qca-&gt;txr.count = max_t(u32, ring-&gt;tx_pending, TX_RING_MIN_LEN);</div><div class='ctx'> 	qca-&gt;txr.count = min_t(u16, qca-&gt;txr.count, TX_RING_MAX_LEN);</div><div class='ctx'> </div><div class='del'>-	if (netif_running(dev))</div><div class='del'>-		ops-&gt;ndo_open(dev);</div><div class='add'>+	if (qca-&gt;spi_thread)</div><div class='add'>+		kthread_unpark(qca-&gt;spi_thread);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/qualcomm/qca_spi.c b/drivers/net/ethernet/qualcomm/qca_spi.c<br/>index bec723028e96..5f3c11fb3fa2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_spi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qualcomm/qca_spi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_spi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_spi.c</a></div><div class='hunk'>@@ -580,6 +580,18 @@ qcaspi_spi_thread(void *data)</div><div class='ctx'> 	netdev_info(qca-&gt;net_dev, "SPI thread created\n");</div><div class='ctx'> 	while (!kthread_should_stop()) {</div><div class='ctx'> 		set_current_state(TASK_INTERRUPTIBLE);</div><div class='add'>+		if (kthread_should_park()) {</div><div class='add'>+			netif_tx_disable(qca-&gt;net_dev);</div><div class='add'>+			netif_carrier_off(qca-&gt;net_dev);</div><div class='add'>+			qcaspi_flush_tx_ring(qca);</div><div class='add'>+			kthread_parkme();</div><div class='add'>+			if (qca-&gt;sync == QCASPI_SYNC_READY) {</div><div class='add'>+				netif_carrier_on(qca-&gt;net_dev);</div><div class='add'>+				netif_wake_queue(qca-&gt;net_dev);</div><div class='add'>+			}</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		if ((qca-&gt;intr_req == qca-&gt;intr_svc) &amp;&amp;</div><div class='ctx'> 		    !qca-&gt;txr.skb[qca-&gt;txr.head])</div><div class='ctx'> 			schedule();</div><div class='hunk'>@@ -608,11 +620,17 @@ qcaspi_spi_thread(void *data)</div><div class='ctx'> 			if (intr_cause &amp; SPI_INT_CPU_ON) {</div><div class='ctx'> 				qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);</div><div class='ctx'> </div><div class='add'>+				/* Frame decoding in progress */</div><div class='add'>+				if (qca-&gt;frm_handle.state != qca-&gt;frm_handle.init)</div><div class='add'>+					qca-&gt;net_dev-&gt;stats.rx_dropped++;</div><div class='add'>+</div><div class='add'>+				qcafrm_fsm_init_spi(&amp;qca-&gt;frm_handle);</div><div class='add'>+				qca-&gt;stats.device_reset++;</div><div class='add'>+</div><div class='ctx'> 				/* not synced. */</div><div class='ctx'> 				if (qca-&gt;sync != QCASPI_SYNC_READY)</div><div class='ctx'> 					continue;</div><div class='ctx'> </div><div class='del'>-				qca-&gt;stats.device_reset++;</div><div class='ctx'> 				netif_wake_queue(qca-&gt;net_dev);</div><div class='ctx'> 				netif_carrier_on(qca-&gt;net_dev);</div><div class='ctx'> 			}</div><div class='head'>diff --git a/drivers/net/ethernet/qualcomm/qca_uart.c b/drivers/net/ethernet/qualcomm/qca_uart.c<br/>index 9adec91f35e9..223321897b96 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_uart.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qualcomm/qca_uart.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/qca_uart.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/qca_uart.c</a></div><div class='hunk'>@@ -58,9 +58,8 @@ struct qcauart {</div><div class='ctx'> 	unsigned char *tx_buffer;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int</div><div class='del'>-qca_tty_receive(struct serdev_device *serdev, const unsigned char *data,</div><div class='del'>-		size_t count)</div><div class='add'>+static ssize_t</div><div class='add'>+qca_tty_receive(struct serdev_device *serdev, const u8 *data, size_t count)</div><div class='ctx'> {</div><div class='ctx'> 	struct qcauart *qca = serdev_device_get_drvdata(serdev);</div><div class='ctx'> 	struct net_device *netdev = qca-&gt;net_dev;</div><div class='head'>diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c<br/>index 39d24e07f306..5b69b9268c75 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c</a></div><div class='hunk'>@@ -396,7 +396,7 @@ nla_put_failure:</div><div class='ctx'> </div><div class='ctx'> struct rtnl_link_ops rmnet_link_ops __read_mostly = {</div><div class='ctx'> 	.kind		= "rmnet",</div><div class='del'>-	.maxtype	= __IFLA_RMNET_MAX,</div><div class='add'>+	.maxtype	= IFLA_RMNET_MAX,</div><div class='ctx'> 	.priv_size	= sizeof(struct rmnet_priv),</div><div class='ctx'> 	.setup		= rmnet_vnd_setup,</div><div class='ctx'> 	.validate	= rmnet_rtnl_validate,</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/Kconfig b/drivers/net/ethernet/realtek/Kconfig<br/>index 93d9df55b361..03015b665f4e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/realtek/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/Kconfig</a></div><div class='hunk'>@@ -113,4 +113,11 @@ config R8169</div><div class='ctx'> 	  To compile this driver as a module, choose M here: the module</div><div class='ctx'> 	  will be called r8169.  This is recommended.</div><div class='ctx'> </div><div class='add'>+config R8169_LEDS</div><div class='add'>+	def_bool R8169 &amp;&amp; LEDS_TRIGGER_NETDEV</div><div class='add'>+	depends on !(R8169=y &amp;&amp; LEDS_CLASS=m)</div><div class='add'>+	help</div><div class='add'>+	  Optional support for controlling the NIC LED's with the netdev</div><div class='add'>+	  LED trigger.</div><div class='add'>+</div><div class='ctx'> endif # NET_VENDOR_REALTEK</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/Makefile b/drivers/net/ethernet/realtek/Makefile<br/>index 2e1d78b106b0..635491d8826e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/realtek/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/Makefile</a></div><div class='hunk'>@@ -6,5 +6,6 @@</div><div class='ctx'> obj-$(CONFIG_8139CP) += 8139cp.o</div><div class='ctx'> obj-$(CONFIG_8139TOO) += 8139too.o</div><div class='ctx'> obj-$(CONFIG_ATP) += atp.o</div><div class='del'>-r8169-objs += r8169_main.o r8169_firmware.o r8169_phy_config.o</div><div class='add'>+r8169-y += r8169_main.o r8169_firmware.o r8169_phy_config.o</div><div class='add'>+r8169-$(CONFIG_R8169_LEDS) += r8169_leds.o</div><div class='ctx'> obj-$(CONFIG_R8169) += r8169.o</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/r8169.h b/drivers/net/ethernet/realtek/r8169.h<br/>index 55ef8251feb5..81567fcf3957 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/realtek/r8169.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169.h</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'>  * See MAINTAINERS file for support contact information.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='add'>+#include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='ctx'> #include &lt;linux/phy.h&gt;</div><div class='ctx'> </div><div class='hunk'>@@ -77,3 +78,9 @@ u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp);</div><div class='ctx'> u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr);</div><div class='ctx'> void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,</div><div class='ctx'> 			 enum mac_version ver);</div><div class='add'>+</div><div class='add'>+void r8169_get_led_name(struct rtl8169_private *tp, int idx,</div><div class='add'>+			char *buf, int buf_len);</div><div class='add'>+int rtl8168_get_led_mode(struct rtl8169_private *tp);</div><div class='add'>+int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val);</div><div class='add'>+void rtl8168_init_leds(struct net_device *ndev);</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/r8169_firmware.c b/drivers/net/ethernet/realtek/r8169_firmware.c<br/>index cbc6b846ded5..ed6e721b1555 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169_firmware.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/realtek/r8169_firmware.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169_firmware.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_firmware.c</a></div><div class='hunk'>@@ -151,9 +151,6 @@ void rtl_fw_write_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)</div><div class='ctx'> 		u32 regno = (action &amp; 0x0fff0000) &gt;&gt; 16;</div><div class='ctx'> 		enum rtl_fw_opcode opcode = action &gt;&gt; 28;</div><div class='ctx'> </div><div class='del'>-		if (!action)</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		switch (opcode) {</div><div class='ctx'> 		case PHY_READ:</div><div class='ctx'> 			predata = fw_read(tp, regno);</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/r8169_leds.c b/drivers/net/ethernet/realtek/r8169_leds.c<br/>new file mode 100644<br/>index 000000000000..007d077edcad<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169_leds.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_leds.c</a></div><div class='hunk'>@@ -0,0 +1,157 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/* r8169_leds.c: Realtek 8169/8168/8101/8125 ethernet driver.</div><div class='add'>+ *</div><div class='add'>+ * Copyright (c) 2023 Heiner Kallweit &lt;hkallweit1@gmail.com&gt;</div><div class='add'>+ *</div><div class='add'>+ * See MAINTAINERS file for support contact information.</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/leds.h&gt;</div><div class='add'>+#include &lt;linux/netdevice.h&gt;</div><div class='add'>+#include &lt;uapi/linux/uleds.h&gt;</div><div class='add'>+</div><div class='add'>+#include "r8169.h"</div><div class='add'>+</div><div class='add'>+#define RTL8168_LED_CTRL_OPTION2	BIT(15)</div><div class='add'>+#define RTL8168_LED_CTRL_ACT		BIT(3)</div><div class='add'>+#define RTL8168_LED_CTRL_LINK_1000	BIT(2)</div><div class='add'>+#define RTL8168_LED_CTRL_LINK_100	BIT(1)</div><div class='add'>+#define RTL8168_LED_CTRL_LINK_10	BIT(0)</div><div class='add'>+</div><div class='add'>+#define RTL8168_NUM_LEDS		3</div><div class='add'>+</div><div class='add'>+#define RTL8168_SUPPORTED_MODES \</div><div class='add'>+	(BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK_100) | \</div><div class='add'>+	 BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_RX) | \</div><div class='add'>+	 BIT(TRIGGER_NETDEV_TX))</div><div class='add'>+</div><div class='add'>+struct r8169_led_classdev {</div><div class='add'>+	struct led_classdev led;</div><div class='add'>+	struct net_device *ndev;</div><div class='add'>+	int index;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define lcdev_to_r8169_ldev(lcdev) container_of(lcdev, struct r8169_led_classdev, led)</div><div class='add'>+</div><div class='add'>+static int rtl8168_led_hw_control_is_supported(struct led_classdev *led_cdev,</div><div class='add'>+					       unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	struct r8169_led_classdev *ldev = lcdev_to_r8169_ldev(led_cdev);</div><div class='add'>+	struct rtl8169_private *tp = netdev_priv(ldev-&gt;ndev);</div><div class='add'>+	int shift = ldev-&gt;index * 4;</div><div class='add'>+	bool rx, tx;</div><div class='add'>+</div><div class='add'>+	if (flags &amp; ~RTL8168_SUPPORTED_MODES)</div><div class='add'>+		goto nosupp;</div><div class='add'>+</div><div class='add'>+	rx = flags &amp; BIT(TRIGGER_NETDEV_RX);</div><div class='add'>+	tx = flags &amp; BIT(TRIGGER_NETDEV_TX);</div><div class='add'>+	if (rx != tx)</div><div class='add'>+		goto nosupp;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+nosupp:</div><div class='add'>+	/* Switch LED off to indicate that mode isn't supported */</div><div class='add'>+	rtl8168_led_mod_ctrl(tp, 0x000f &lt;&lt; shift, 0);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtl8168_led_hw_control_set(struct led_classdev *led_cdev,</div><div class='add'>+				      unsigned long flags)</div><div class='add'>+{</div><div class='add'>+	struct r8169_led_classdev *ldev = lcdev_to_r8169_ldev(led_cdev);</div><div class='add'>+	struct rtl8169_private *tp = netdev_priv(ldev-&gt;ndev);</div><div class='add'>+	int shift = ldev-&gt;index * 4;</div><div class='add'>+	u16 mode = 0;</div><div class='add'>+</div><div class='add'>+	if (flags &amp; BIT(TRIGGER_NETDEV_LINK_10))</div><div class='add'>+		mode |= RTL8168_LED_CTRL_LINK_10;</div><div class='add'>+	if (flags &amp; BIT(TRIGGER_NETDEV_LINK_100))</div><div class='add'>+		mode |= RTL8168_LED_CTRL_LINK_100;</div><div class='add'>+	if (flags &amp; BIT(TRIGGER_NETDEV_LINK_1000))</div><div class='add'>+		mode |= RTL8168_LED_CTRL_LINK_1000;</div><div class='add'>+	if (flags &amp; BIT(TRIGGER_NETDEV_TX))</div><div class='add'>+		mode |= RTL8168_LED_CTRL_ACT;</div><div class='add'>+</div><div class='add'>+	return rtl8168_led_mod_ctrl(tp, 0x000f &lt;&lt; shift, mode &lt;&lt; shift);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int rtl8168_led_hw_control_get(struct led_classdev *led_cdev,</div><div class='add'>+				      unsigned long *flags)</div><div class='add'>+{</div><div class='add'>+	struct r8169_led_classdev *ldev = lcdev_to_r8169_ldev(led_cdev);</div><div class='add'>+	struct rtl8169_private *tp = netdev_priv(ldev-&gt;ndev);</div><div class='add'>+	int shift = ldev-&gt;index * 4;</div><div class='add'>+	int mode;</div><div class='add'>+</div><div class='add'>+	mode = rtl8168_get_led_mode(tp);</div><div class='add'>+	if (mode &lt; 0)</div><div class='add'>+		return mode;</div><div class='add'>+</div><div class='add'>+	if (mode &amp; RTL8168_LED_CTRL_OPTION2) {</div><div class='add'>+		rtl8168_led_mod_ctrl(tp, RTL8168_LED_CTRL_OPTION2, 0);</div><div class='add'>+		netdev_notice(ldev-&gt;ndev, "Deactivating unsupported Option2 LED mode\n");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mode = (mode &gt;&gt; shift) &amp; 0x000f;</div><div class='add'>+</div><div class='add'>+	if (mode &amp; RTL8168_LED_CTRL_ACT)</div><div class='add'>+		*flags |= BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX);</div><div class='add'>+</div><div class='add'>+	if (mode &amp; RTL8168_LED_CTRL_LINK_10)</div><div class='add'>+		*flags |= BIT(TRIGGER_NETDEV_LINK_10);</div><div class='add'>+	if (mode &amp; RTL8168_LED_CTRL_LINK_100)</div><div class='add'>+		*flags |= BIT(TRIGGER_NETDEV_LINK_100);</div><div class='add'>+	if (mode &amp; RTL8168_LED_CTRL_LINK_1000)</div><div class='add'>+		*flags |= BIT(TRIGGER_NETDEV_LINK_1000);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct device *</div><div class='add'>+	r8169_led_hw_control_get_device(struct led_classdev *led_cdev)</div><div class='add'>+{</div><div class='add'>+	struct r8169_led_classdev *ldev = lcdev_to_r8169_ldev(led_cdev);</div><div class='add'>+</div><div class='add'>+	return &amp;ldev-&gt;ndev-&gt;dev;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void rtl8168_setup_ldev(struct r8169_led_classdev *ldev,</div><div class='add'>+			       struct net_device *ndev, int index)</div><div class='add'>+{</div><div class='add'>+	struct rtl8169_private *tp = netdev_priv(ndev);</div><div class='add'>+	struct led_classdev *led_cdev = &amp;ldev-&gt;led;</div><div class='add'>+	char led_name[LED_MAX_NAME_SIZE];</div><div class='add'>+</div><div class='add'>+	ldev-&gt;ndev = ndev;</div><div class='add'>+	ldev-&gt;index = index;</div><div class='add'>+</div><div class='add'>+	r8169_get_led_name(tp, index, led_name, LED_MAX_NAME_SIZE);</div><div class='add'>+	led_cdev-&gt;name = led_name;</div><div class='add'>+	led_cdev-&gt;default_trigger = "netdev";</div><div class='add'>+	led_cdev-&gt;hw_control_trigger = "netdev";</div><div class='add'>+	led_cdev-&gt;flags |= LED_RETAIN_AT_SHUTDOWN;</div><div class='add'>+	led_cdev-&gt;hw_control_is_supported = rtl8168_led_hw_control_is_supported;</div><div class='add'>+	led_cdev-&gt;hw_control_set = rtl8168_led_hw_control_set;</div><div class='add'>+	led_cdev-&gt;hw_control_get = rtl8168_led_hw_control_get;</div><div class='add'>+	led_cdev-&gt;hw_control_get_device = r8169_led_hw_control_get_device;</div><div class='add'>+</div><div class='add'>+	/* ignore errors */</div><div class='add'>+	devm_led_classdev_register(&amp;ndev-&gt;dev, led_cdev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void rtl8168_init_leds(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	/* bind resource mgmt to netdev */</div><div class='add'>+	struct device *dev = &amp;ndev-&gt;dev;</div><div class='add'>+	struct r8169_led_classdev *leds;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	leds = devm_kcalloc(dev, RTL8168_NUM_LEDS, sizeof(*leds), GFP_KERNEL);</div><div class='add'>+	if (!leds)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; RTL8168_NUM_LEDS; i++)</div><div class='add'>+		rtl8168_setup_ldev(leds + i, ndev, i);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c<br/>index 295366a85c63..dd73df6b17b0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/realtek/r8169_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/realtek/r8169_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/realtek/r8169_main.c</a></div><div class='hunk'>@@ -56,10 +56,6 @@</div><div class='ctx'> #define FIRMWARE_8125A_3	"rtl_nic/rtl8125a-3.fw"</div><div class='ctx'> #define FIRMWARE_8125B_2	"rtl_nic/rtl8125b-2.fw"</div><div class='ctx'> </div><div class='del'>-/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).</div><div class='del'>-   The RTL chips use a 64 element hash table based on the Ethernet CRC. */</div><div class='del'>-#define	MC_FILTER_LIMIT	32</div><div class='del'>-</div><div class='ctx'> #define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */</div><div class='ctx'> #define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */</div><div class='ctx'> </div><div class='hunk'>@@ -196,6 +192,7 @@ enum rtl_registers {</div><div class='ctx'> 					/* No threshold before first PCI xfer */</div><div class='ctx'> #define	RX_FIFO_THRESH			(7 &lt;&lt; RXCFG_FIFO_SHIFT)</div><div class='ctx'> #define	RX_EARLY_OFF			(1 &lt;&lt; 11)</div><div class='add'>+#define	RX_PAUSE_SLOT_ON		(1 &lt;&lt; 11)	/* 8125b and later */</div><div class='ctx'> #define	RXCFG_DMA_SHIFT			8</div><div class='ctx'> 					/* Unlimited maximum PCI burst. */</div><div class='ctx'> #define	RX_DMA_BURST			(7 &lt;&lt; RXCFG_DMA_SHIFT)</div><div class='hunk'>@@ -288,6 +285,7 @@ enum rtl8168_8101_registers {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum rtl8168_registers {</div><div class='add'>+	LED_CTRL		= 0x18,</div><div class='ctx'> 	LED_FREQ		= 0x1a,</div><div class='ctx'> 	EEE_LED			= 0x1b,</div><div class='ctx'> 	ERIDR			= 0x70,</div><div class='hunk'>@@ -579,6 +577,7 @@ struct rtl8169_tc_offsets {</div><div class='ctx'> enum rtl_flag {</div><div class='ctx'> 	RTL_FLAG_TASK_ENABLED = 0,</div><div class='ctx'> 	RTL_FLAG_TASK_RESET_PENDING,</div><div class='add'>+	RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,</div><div class='ctx'> 	RTL_FLAG_TASK_TX_TIMEOUT,</div><div class='ctx'> 	RTL_FLAG_MAX</div><div class='ctx'> };</div><div class='hunk'>@@ -618,6 +617,7 @@ struct rtl8169_private {</div><div class='ctx'> </div><div class='ctx'> 	raw_spinlock_t config25_lock;</div><div class='ctx'> 	raw_spinlock_t mac_ocp_lock;</div><div class='add'>+	struct mutex led_lock;	/* serialize LED ctrl RMW access */</div><div class='ctx'> </div><div class='ctx'> 	raw_spinlock_t cfg9346_usage_lock;</div><div class='ctx'> 	int cfg9346_usage_count;</div><div class='hunk'>@@ -790,6 +790,62 @@ static const struct rtl_cond name = {			\</div><div class='ctx'> 							\</div><div class='ctx'> static bool name ## _check(struct rtl8169_private *tp)</div><div class='ctx'> </div><div class='add'>+int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = tp_to_dev(tp);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;tp-&gt;led_lock);</div><div class='add'>+	RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) &amp; ~mask) | val);</div><div class='add'>+	mutex_unlock(&amp;tp-&gt;led_lock);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_sync(dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int rtl8168_get_led_mode(struct rtl8169_private *tp)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = tp_to_dev(tp);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_resume_and_get(dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = RTL_R16(tp, LED_CTRL);</div><div class='add'>+</div><div class='add'>+	pm_runtime_put_sync(dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void r8169_get_led_name(struct rtl8169_private *tp, int idx,</div><div class='add'>+			char *buf, int buf_len)</div><div class='add'>+{</div><div class='add'>+	struct pci_dev *pdev = tp-&gt;pci_dev;</div><div class='add'>+	char pdom[8], pfun[8];</div><div class='add'>+	int domain;</div><div class='add'>+</div><div class='add'>+	domain = pci_domain_nr(pdev-&gt;bus);</div><div class='add'>+	if (domain)</div><div class='add'>+		snprintf(pdom, sizeof(pdom), "P%d", domain);</div><div class='add'>+	else</div><div class='add'>+		pdom[0] = '\0';</div><div class='add'>+</div><div class='add'>+	if (pdev-&gt;multifunction)</div><div class='add'>+		snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev-&gt;devfn));</div><div class='add'>+	else</div><div class='add'>+		pfun[0] = '\0';</div><div class='add'>+</div><div class='add'>+	snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev-&gt;bus-&gt;number,</div><div class='add'>+		 PCI_SLOT(pdev-&gt;devfn), pfun, idx);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)</div><div class='ctx'> {</div><div class='ctx'> 	/* based on RTL8168FP_OOBMAC_BASE in vendor driver */</div><div class='hunk'>@@ -1209,7 +1265,7 @@ static void rtl8168ep_driver_start(struct rtl8169_private *tp)</div><div class='ctx'> {</div><div class='ctx'> 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);</div><div class='ctx'> 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);</div><div class='del'>-	rtl_loop_wait_high(tp, &amp;rtl_ep_ocp_read_cond, 10000, 10);</div><div class='add'>+	rtl_loop_wait_high(tp, &amp;rtl_ep_ocp_read_cond, 10000, 30);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rtl8168_driver_start(struct rtl8169_private *tp)</div><div class='hunk'>@@ -2231,6 +2287,9 @@ u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)</div><div class='ctx'> </div><div class='ctx'> static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)</div><div class='ctx'> {</div><div class='add'>+	if (!test_bit(RTL_FLAG_TASK_ENABLED, tp-&gt;wk.flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	set_bit(flag, tp-&gt;wk.flags);</div><div class='ctx'> 	schedule_work(&amp;tp-&gt;wk.work);</div><div class='ctx'> }</div><div class='hunk'>@@ -2305,9 +2364,13 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)</div><div class='ctx'> 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:</div><div class='ctx'> 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);</div><div class='ctx'> 		break;</div><div class='del'>-	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:</div><div class='add'>+	case RTL_GIGA_MAC_VER_61:</div><div class='ctx'> 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);</div><div class='ctx'> 		break;</div><div class='add'>+	case RTL_GIGA_MAC_VER_63:</div><div class='add'>+		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |</div><div class='add'>+			RX_PAUSE_SLOT_ON);</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -2597,8 +2660,7 @@ static void rtl_set_rx_mode(struct net_device *dev)</div><div class='ctx'> 		rx_mode |= AcceptAllPhys;</div><div class='ctx'> 	} else if (!(dev-&gt;flags &amp; IFF_MULTICAST)) {</div><div class='ctx'> 		rx_mode &amp;= ~AcceptMulticast;</div><div class='del'>-	} else if (netdev_mc_count(dev) &gt; MC_FILTER_LIMIT ||</div><div class='del'>-		   dev-&gt;flags &amp; IFF_ALLMULTI ||</div><div class='add'>+	} else if (dev-&gt;flags &amp; IFF_ALLMULTI ||</div><div class='ctx'> 		   tp-&gt;mac_version == RTL_GIGA_MAC_VER_35) {</div><div class='ctx'> 		/* accept all multicasts */</div><div class='ctx'> 	} else if (netdev_mc_empty(dev)) {</div><div class='hunk'>@@ -3100,6 +3162,33 @@ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)</div><div class='ctx'> 	rtl_ephy_init(tp, e_info_8168g_2);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)</div><div class='add'>+{</div><div class='add'>+	static const u16 fix_data[] = {</div><div class='add'>+/* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,</div><div class='add'>+/* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,</div><div class='add'>+/* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,</div><div class='add'>+/* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,</div><div class='add'>+/* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,</div><div class='add'>+/* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,</div><div class='add'>+/* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,</div><div class='add'>+/* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,</div><div class='add'>+/* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,</div><div class='add'>+/* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,</div><div class='add'>+/* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,</div><div class='add'>+/* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,</div><div class='add'>+/* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,</div><div class='add'>+/* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132</div><div class='add'>+	};</div><div class='add'>+	unsigned long flags;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	raw_spin_lock_irqsave(&amp;tp-&gt;mac_ocp_lock, flags);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(fix_data); i++)</div><div class='add'>+		__r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);</div><div class='add'>+	raw_spin_unlock_irqrestore(&amp;tp-&gt;mac_ocp_lock, flags);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void rtl_hw_start_8411_2(struct rtl8169_private *tp)</div><div class='ctx'> {</div><div class='ctx'> 	static const struct ephy_info e_info_8411_2[] = {</div><div class='hunk'>@@ -3133,117 +3222,7 @@ static void rtl_hw_start_8411_2(struct rtl8169_private *tp)</div><div class='ctx'> 	mdelay(3);</div><div class='ctx'> 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);</div><div class='ctx'> </div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF800, 0xE008);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF808, 0xE027);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF810, 0xC602);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF814, 0x0000);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF816, 0xC502);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF820, 0x080A);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF822, 0x6420);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF828, 0xC516);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF846, 0xC404);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF852, 0xE434);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF860, 0xF007);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF876, 0xC516);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF880, 0xC512);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF888, 0x483F);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF892, 0xC505);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF896, 0xC502);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);</div><div class='del'>-	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);</div><div class='add'>+	rtl8411b_fix_phy_down(tp);</div><div class='ctx'> </div><div class='ctx'> 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);</div><div class='ctx'> </div><div class='hunk'>@@ -4555,8 +4534,7 @@ static void rtl_task(struct work_struct *work)</div><div class='ctx'> </div><div class='ctx'> 	rtnl_lock();</div><div class='ctx'> </div><div class='del'>-	if (!netif_running(tp-&gt;dev) ||</div><div class='del'>-	    !test_bit(RTL_FLAG_TASK_ENABLED, tp-&gt;wk.flags))</div><div class='add'>+	if (!test_bit(RTL_FLAG_TASK_ENABLED, tp-&gt;wk.flags))</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='ctx'> 	if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp-&gt;wk.flags)) {</div><div class='hunk'>@@ -4582,6 +4560,8 @@ static void rtl_task(struct work_struct *work)</div><div class='ctx'> reset:</div><div class='ctx'> 		rtl_reset_work(tp);</div><div class='ctx'> 		netif_wake_queue(tp-&gt;dev);</div><div class='add'>+	} else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp-&gt;wk.flags)) {</div><div class='add'>+		rtl_reset_work(tp);</div><div class='ctx'> 	}</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	rtnl_unlock();</div><div class='hunk'>@@ -4615,7 +4595,7 @@ static void r8169_phylink_handler(struct net_device *ndev)</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* In few cases rx is broken after link-down otherwise */</div><div class='ctx'> 		if (rtl_is_8125(tp))</div><div class='del'>-			rtl_reset_work(tp);</div><div class='add'>+			rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);</div><div class='ctx'> 		pm_runtime_idle(d);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -4691,7 +4671,7 @@ static int rtl8169_close(struct net_device *dev)</div><div class='ctx'> 	rtl8169_down(tp);</div><div class='ctx'> 	rtl8169_rx_clear(tp);</div><div class='ctx'> </div><div class='del'>-	cancel_work_sync(&amp;tp-&gt;wk.work);</div><div class='add'>+	cancel_work(&amp;tp-&gt;wk.work);</div><div class='ctx'> </div><div class='ctx'> 	free_irq(tp-&gt;irq, tp);</div><div class='ctx'> </div><div class='hunk'>@@ -4925,6 +4905,8 @@ static void rtl_remove_one(struct pci_dev *pdev)</div><div class='ctx'> 	if (pci_dev_run_wake(pdev))</div><div class='ctx'> 		pm_runtime_get_noresume(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='add'>+	cancel_work_sync(&amp;tp-&gt;wk.work);</div><div class='add'>+</div><div class='ctx'> 	unregister_netdev(tp-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	if (tp-&gt;dash_type != RTL_DASH_NONE)</div><div class='hunk'>@@ -5217,6 +5199,7 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	raw_spin_lock_init(&amp;tp-&gt;cfg9346_usage_lock);</div><div class='ctx'> 	raw_spin_lock_init(&amp;tp-&gt;config25_lock);</div><div class='ctx'> 	raw_spin_lock_init(&amp;tp-&gt;mac_ocp_lock);</div><div class='add'>+	mutex_init(&amp;tp-&gt;led_lock);</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;tstats = devm_netdev_alloc_pcpu_stats(&amp;pdev-&gt;dev,</div><div class='ctx'> 						   struct pcpu_sw_netstats);</div><div class='hunk'>@@ -5373,6 +5356,11 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return rc;</div><div class='ctx'> </div><div class='add'>+	if (IS_ENABLED(CONFIG_R8169_LEDS) &amp;&amp;</div><div class='add'>+	    tp-&gt;mac_version &gt; RTL_GIGA_MAC_VER_06 &amp;&amp;</div><div class='add'>+	    tp-&gt;mac_version &lt; RTL_GIGA_MAC_VER_61)</div><div class='add'>+		rtl8168_init_leds(dev);</div><div class='add'>+</div><div class='ctx'> 	netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",</div><div class='ctx'> 		    rtl_chip_infos[chipset].name, dev-&gt;dev_addr, xid, tp-&gt;irq);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig<br/>index 8ef5b0241e64..d6136fe5c206 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/Kconfig</a></div><div class='hunk'>@@ -40,11 +40,21 @@ config RAVB</div><div class='ctx'> config RENESAS_ETHER_SWITCH</div><div class='ctx'> 	tristate "Renesas Ethernet Switch support"</div><div class='ctx'> 	depends on ARCH_RENESAS || COMPILE_TEST</div><div class='del'>-	depends on PTP_1588_CLOCK_OPTIONAL</div><div class='add'>+	depends on PTP_1588_CLOCK</div><div class='ctx'> 	select CRC32</div><div class='ctx'> 	select MII</div><div class='ctx'> 	select PHYLINK</div><div class='add'>+	select RENESAS_GEN4_PTP</div><div class='ctx'> 	help</div><div class='ctx'> 	  Renesas Ethernet Switch device driver.</div><div class='ctx'> </div><div class='add'>+config RENESAS_GEN4_PTP</div><div class='add'>+	tristate "Renesas R-Car Gen4 gPTP support" if COMPILE_TEST</div><div class='add'>+	depends on PTP_1588_CLOCK</div><div class='add'>+	select CRC32</div><div class='add'>+	select MII</div><div class='add'>+	select PHYLIB</div><div class='add'>+	help</div><div class='add'>+	  Renesas R-Car Gen4 gPTP device driver.</div><div class='add'>+</div><div class='ctx'> endif # NET_VENDOR_RENESAS</div><div class='head'>diff --git a/drivers/net/ethernet/renesas/Makefile b/drivers/net/ethernet/renesas/Makefile<br/>index e8fd85b5fe8f..9070acfd6aaf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/Makefile</a></div><div class='hunk'>@@ -8,5 +8,6 @@ obj-$(CONFIG_SH_ETH) += sh_eth.o</div><div class='ctx'> ravb-objs := ravb_main.o ravb_ptp.o</div><div class='ctx'> obj-$(CONFIG_RAVB) += ravb.o</div><div class='ctx'> </div><div class='del'>-rswitch_drv-objs := rswitch.o rcar_gen4_ptp.o</div><div class='del'>-obj-$(CONFIG_RENESAS_ETHER_SWITCH) += rswitch_drv.o</div><div class='add'>+obj-$(CONFIG_RENESAS_ETHER_SWITCH) += rswitch.o</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_RENESAS_GEN4_PTP) += rcar_gen4_ptp.o</div><div class='head'>diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c<br/>index c70cff80cc99..0e3731f50fc2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/ravb_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/ravb_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/ravb_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/ravb_main.c</a></div><div class='hunk'>@@ -66,16 +66,27 @@ int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)</div><div class='ctx'> 	return -ETIMEDOUT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ravb_config(struct net_device *ndev)</div><div class='add'>+static int ravb_set_opmode(struct net_device *ndev, u32 opmode)</div><div class='ctx'> {</div><div class='add'>+	u32 csr_ops = 1U &lt;&lt; (opmode &amp; CCC_OPC);</div><div class='add'>+	u32 ccc_mask = CCC_OPC;</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='del'>-	/* Set config mode */</div><div class='del'>-	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);</div><div class='del'>-	/* Check if the operating mode is changed to the config mode */</div><div class='del'>-	error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);</div><div class='del'>-	if (error)</div><div class='del'>-		netdev_err(ndev, "failed to switch device to config mode\n");</div><div class='add'>+	/* If gPTP active in config mode is supported it needs to be configured</div><div class='add'>+	 * along with CSEL and operating mode in the same access. This is a</div><div class='add'>+	 * hardware limitation.</div><div class='add'>+	 */</div><div class='add'>+	if (opmode &amp; CCC_GAC)</div><div class='add'>+		ccc_mask |= CCC_GAC | CCC_CSEL;</div><div class='add'>+</div><div class='add'>+	/* Set operating mode */</div><div class='add'>+	ravb_modify(ndev, CCC, ccc_mask, opmode);</div><div class='add'>+	/* Check if the operating mode is changed to the requested one */</div><div class='add'>+	error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops);</div><div class='add'>+	if (error) {</div><div class='add'>+		netdev_err(ndev, "failed to switch device to requested mode (%u)\n",</div><div class='add'>+			   opmode &amp; CCC_OPC);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='hunk'>@@ -515,6 +526,15 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ravb_private *priv = netdev_priv(ndev);</div><div class='ctx'> </div><div class='add'>+	if (priv-&gt;phy_interface == PHY_INTERFACE_MODE_MII) {</div><div class='add'>+		ravb_write(ndev, (1000 &lt;&lt; 16) | CXR35_SEL_XMII_MII, CXR35);</div><div class='add'>+		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);</div><div class='add'>+	} else {</div><div class='add'>+		ravb_write(ndev, (1000 &lt;&lt; 16) | CXR35_SEL_XMII_RGMII, CXR35);</div><div class='add'>+		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,</div><div class='add'>+			    CXR31_SEL_LINK0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	/* Receive frame limit set register */</div><div class='ctx'> 	ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);</div><div class='ctx'> </div><div class='hunk'>@@ -537,14 +557,6 @@ static void ravb_emac_init_gbeth(struct net_device *ndev)</div><div class='ctx'> </div><div class='ctx'> 	/* E-MAC interrupt enable register */</div><div class='ctx'> 	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;phy_interface == PHY_INTERFACE_MODE_MII) {</div><div class='del'>-		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);</div><div class='del'>-		ravb_write(ndev, (1000 &lt;&lt; 16) | CXR35_SEL_XMII_MII, CXR35);</div><div class='del'>-	} else {</div><div class='del'>-		ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,</div><div class='del'>-			    CXR31_SEL_LINK0);</div><div class='del'>-	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ravb_emac_init_rcar(struct net_device *ndev)</div><div class='hunk'>@@ -672,7 +684,7 @@ static int ravb_dmac_init(struct net_device *ndev)</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='ctx'> 	/* Set CONFIG mode */</div><div class='del'>-	error = ravb_config(ndev);</div><div class='add'>+	error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='hunk'>@@ -681,9 +693,7 @@ static int ravb_dmac_init(struct net_device *ndev)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='ctx'> 	/* Setting the control will start the AVB-DMAC process. */</div><div class='del'>-	ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return ravb_set_opmode(ndev, CCC_OPC_OPERATION);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ravb_get_tx_tstamp(struct net_device *ndev)</div><div class='hunk'>@@ -1045,7 +1055,7 @@ static int ravb_stop_dma(struct net_device *ndev)</div><div class='ctx'> 		return error;</div><div class='ctx'> </div><div class='ctx'> 	/* Stop AVB-DMAC process */</div><div class='del'>-	return ravb_config(ndev);</div><div class='add'>+	return ravb_set_opmode(ndev, CCC_OPC_CONFIG);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* E-MAC interrupt handler */</div><div class='hunk'>@@ -1811,19 +1821,20 @@ static int ravb_open(struct net_device *ndev)</div><div class='ctx'> 	if (info-&gt;gptp)</div><div class='ctx'> 		ravb_ptp_init(ndev, priv-&gt;pdev);</div><div class='ctx'> </div><div class='del'>-	netif_tx_start_all_queues(ndev);</div><div class='del'>-</div><div class='ctx'> 	/* PHY control start */</div><div class='ctx'> 	error = ravb_phy_start(ndev);</div><div class='ctx'> 	if (error)</div><div class='ctx'> 		goto out_ptp_stop;</div><div class='ctx'> </div><div class='add'>+	netif_tx_start_all_queues(ndev);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> out_ptp_stop:</div><div class='ctx'> 	/* Stop PTP Clock driver */</div><div class='ctx'> 	if (info-&gt;gptp)</div><div class='ctx'> 		ravb_ptp_stop(ndev);</div><div class='add'>+	ravb_stop_dma(ndev);</div><div class='ctx'> out_free_irq_mgmta:</div><div class='ctx'> 	if (!info-&gt;multi_irqs)</div><div class='ctx'> 		goto out_free_irq;</div><div class='hunk'>@@ -1874,6 +1885,12 @@ static void ravb_tx_timeout_work(struct work_struct *work)</div><div class='ctx'> 	struct net_device *ndev = priv-&gt;ndev;</div><div class='ctx'> 	int error;</div><div class='ctx'> </div><div class='add'>+	if (!rtnl_trylock()) {</div><div class='add'>+		usleep_range(1000, 2000);</div><div class='add'>+		schedule_work(&amp;priv-&gt;work);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	netif_tx_stop_all_queues(ndev);</div><div class='ctx'> </div><div class='ctx'> 	/* Stop PTP Clock driver */</div><div class='hunk'>@@ -1907,7 +1924,7 @@ static void ravb_tx_timeout_work(struct work_struct *work)</div><div class='ctx'> 		 */</div><div class='ctx'> 		netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",</div><div class='ctx'> 			   __func__, error);</div><div class='del'>-		return;</div><div class='add'>+		goto out_unlock;</div><div class='ctx'> 	}</div><div class='ctx'> 	ravb_emac_init(ndev);</div><div class='ctx'> </div><div class='hunk'>@@ -1917,6 +1934,9 @@ out:</div><div class='ctx'> 		ravb_ptp_init(ndev, priv-&gt;pdev);</div><div class='ctx'> </div><div class='ctx'> 	netif_tx_start_all_queues(ndev);</div><div class='add'>+</div><div class='add'>+out_unlock:</div><div class='add'>+	rtnl_unlock();</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Packet transmit function for Ethernet AVB */</div><div class='hunk'>@@ -1929,7 +1949,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)</div><div class='ctx'> 	struct ravb_tstamp_skb *ts_skb;</div><div class='ctx'> 	struct ravb_tx_desc *desc;</div><div class='ctx'> 	unsigned long flags;</div><div class='del'>-	u32 dma_addr;</div><div class='add'>+	dma_addr_t dma_addr;</div><div class='ctx'> 	void *buffer;</div><div class='ctx'> 	u32 entry;</div><div class='ctx'> 	u32 len;</div><div class='hunk'>@@ -2549,21 +2569,25 @@ static int ravb_set_gti(struct net_device *ndev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ravb_set_config_mode(struct net_device *ndev)</div><div class='add'>+static int ravb_set_config_mode(struct net_device *ndev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ravb_private *priv = netdev_priv(ndev);</div><div class='ctx'> 	const struct ravb_hw_info *info = priv-&gt;info;</div><div class='add'>+	int error;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;gptp) {</div><div class='del'>-		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);</div><div class='add'>+		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);</div><div class='add'>+		if (error)</div><div class='add'>+			return error;</div><div class='ctx'> 		/* Set CSEL value */</div><div class='ctx'> 		ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);</div><div class='ctx'> 	} else if (info-&gt;ccc_gac) {</div><div class='del'>-		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |</div><div class='del'>-			    CCC_GAC | CCC_CSEL_HPB);</div><div class='add'>+		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB);</div><div class='ctx'> 	} else {</div><div class='del'>-		ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);</div><div class='add'>+		error = ravb_set_opmode(ndev, CCC_OPC_CONFIG);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Set tx and rx clock internal delay modes */</div><div class='hunk'>@@ -2645,9 +2669,14 @@ static int ravb_probe(struct platform_device *pdev)</div><div class='ctx'> 	ndev-&gt;features = info-&gt;net_features;</div><div class='ctx'> 	ndev-&gt;hw_features = info-&gt;net_hw_features;</div><div class='ctx'> </div><div class='del'>-	reset_control_deassert(rstc);</div><div class='add'>+	error = reset_control_deassert(rstc);</div><div class='add'>+	if (error)</div><div class='add'>+		goto out_free_netdev;</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_enable(&amp;pdev-&gt;dev);</div><div class='del'>-	pm_runtime_get_sync(&amp;pdev-&gt;dev);</div><div class='add'>+	error = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='add'>+	if (error &lt; 0)</div><div class='add'>+		goto out_rpm_disable;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;multi_irqs) {</div><div class='ctx'> 		if (info-&gt;err_mgmt_irqs)</div><div class='hunk'>@@ -2778,7 +2807,9 @@ static int ravb_probe(struct platform_device *pdev)</div><div class='ctx'> 	ndev-&gt;ethtool_ops = &amp;ravb_ethtool_ops;</div><div class='ctx'> </div><div class='ctx'> 	/* Set AVB config mode */</div><div class='del'>-	ravb_set_config_mode(ndev);</div><div class='add'>+	error = ravb_set_config_mode(ndev);</div><div class='add'>+	if (error)</div><div class='add'>+		goto out_disable_gptp_clk;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;gptp || info-&gt;ccc_gac) {</div><div class='ctx'> 		/* Set GTI value */</div><div class='hunk'>@@ -2872,11 +2903,12 @@ out_disable_gptp_clk:</div><div class='ctx'> out_disable_refclk:</div><div class='ctx'> 	clk_disable_unprepare(priv-&gt;refclk);</div><div class='ctx'> out_release:</div><div class='del'>-	free_netdev(ndev);</div><div class='del'>-</div><div class='ctx'> 	pm_runtime_put(&amp;pdev-&gt;dev);</div><div class='add'>+out_rpm_disable:</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	reset_control_assert(rstc);</div><div class='add'>+out_free_netdev:</div><div class='add'>+	free_netdev(ndev);</div><div class='ctx'> 	return error;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2886,22 +2918,25 @@ static void ravb_remove(struct platform_device *pdev)</div><div class='ctx'> 	struct ravb_private *priv = netdev_priv(ndev);</div><div class='ctx'> 	const struct ravb_hw_info *info = priv-&gt;info;</div><div class='ctx'> </div><div class='del'>-	/* Stop PTP Clock driver */</div><div class='del'>-	if (info-&gt;ccc_gac)</div><div class='del'>-		ravb_ptp_stop(ndev);</div><div class='del'>-</div><div class='del'>-	clk_disable_unprepare(priv-&gt;gptp_clk);</div><div class='del'>-	clk_disable_unprepare(priv-&gt;refclk);</div><div class='del'>-</div><div class='del'>-	/* Set reset mode */</div><div class='del'>-	ravb_write(ndev, CCC_OPC_RESET, CCC);</div><div class='ctx'> 	unregister_netdev(ndev);</div><div class='ctx'> 	if (info-&gt;nc_queues)</div><div class='ctx'> 		netif_napi_del(&amp;priv-&gt;napi[RAVB_NC]);</div><div class='ctx'> 	netif_napi_del(&amp;priv-&gt;napi[RAVB_BE]);</div><div class='add'>+</div><div class='ctx'> 	ravb_mdio_release(priv);</div><div class='add'>+</div><div class='add'>+	/* Stop PTP Clock driver */</div><div class='add'>+	if (info-&gt;ccc_gac)</div><div class='add'>+		ravb_ptp_stop(ndev);</div><div class='add'>+</div><div class='ctx'> 	dma_free_coherent(ndev-&gt;dev.parent, priv-&gt;desc_bat_size, priv-&gt;desc_bat,</div><div class='ctx'> 			  priv-&gt;desc_bat_dma);</div><div class='add'>+</div><div class='add'>+	ravb_set_opmode(ndev, CCC_OPC_RESET);</div><div class='add'>+</div><div class='add'>+	clk_disable_unprepare(priv-&gt;gptp_clk);</div><div class='add'>+	clk_disable_unprepare(priv-&gt;refclk);</div><div class='add'>+</div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='ctx'> 	reset_control_assert(priv-&gt;rstc);</div><div class='hunk'>@@ -2979,8 +3014,11 @@ static int __maybe_unused ravb_resume(struct device *dev)</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* If WoL is enabled set reset mode to rearm the WoL logic */</div><div class='del'>-	if (priv-&gt;wol_enabled)</div><div class='del'>-		ravb_write(ndev, CCC_OPC_RESET, CCC);</div><div class='add'>+	if (priv-&gt;wol_enabled) {</div><div class='add'>+		ret = ravb_set_opmode(ndev, CCC_OPC_RESET);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* All register have been reset to default values.</div><div class='ctx'> 	 * Restore all registers which where setup at probe time and</div><div class='hunk'>@@ -2988,7 +3026,9 @@ static int __maybe_unused ravb_resume(struct device *dev)</div><div class='ctx'> 	 */</div><div class='ctx'> </div><div class='ctx'> 	/* Set AVB config mode */</div><div class='del'>-	ravb_set_config_mode(ndev);</div><div class='add'>+	ret = ravb_set_config_mode(ndev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	if (info-&gt;gptp || info-&gt;ccc_gac) {</div><div class='ctx'> 		/* Set GTI value */</div><div class='head'>diff --git a/drivers/net/ethernet/renesas/rcar_gen4_ptp.c b/drivers/net/ethernet/renesas/rcar_gen4_ptp.c<br/>index c007e33c47e1..72e7fcc56693 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rcar_gen4_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/rcar_gen4_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rcar_gen4_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rcar_gen4_ptp.c</a></div><div class='hunk'>@@ -14,7 +14,7 @@</div><div class='ctx'> #include "rcar_gen4_ptp.h"</div><div class='ctx'> #define ptp_to_priv(ptp)	container_of(ptp, struct rcar_gen4_ptp_private, info)</div><div class='ctx'> </div><div class='del'>-static const struct rcar_gen4_ptp_reg_offset s4_offs = {</div><div class='add'>+static const struct rcar_gen4_ptp_reg_offset gen4_offs = {</div><div class='ctx'> 	.enable = PTPTMEC,</div><div class='ctx'> 	.disable = PTPTMDC,</div><div class='ctx'> 	.increment = PTPTIVC0,</div><div class='hunk'>@@ -130,25 +130,42 @@ static struct ptp_clock_info rcar_gen4_ptp_info = {</div><div class='ctx'> 	.enable = rcar_gen4_ptp_enable,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void rcar_gen4_ptp_set_offs(struct rcar_gen4_ptp_private *ptp_priv,</div><div class='del'>-				   enum rcar_gen4_ptp_reg_layout layout)</div><div class='add'>+static int rcar_gen4_ptp_set_offs(struct rcar_gen4_ptp_private *ptp_priv,</div><div class='add'>+				  enum rcar_gen4_ptp_reg_layout layout)</div><div class='ctx'> {</div><div class='del'>-	WARN_ON(layout != RCAR_GEN4_PTP_REG_LAYOUT_S4);</div><div class='add'>+	if (layout != RCAR_GEN4_PTP_REG_LAYOUT)</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	ptp_priv-&gt;offs = &amp;s4_offs;</div><div class='add'>+	ptp_priv-&gt;offs = &amp;gen4_offs;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static s64 rcar_gen4_ptp_rate_to_increment(u32 rate)</div><div class='add'>+{</div><div class='add'>+	/* Timer increment in ns.</div><div class='add'>+	 * bit[31:27] - integer</div><div class='add'>+	 * bit[26:0]  - decimal</div><div class='add'>+	 * increment[ns] = perid[ns] * 2^27 =&gt; (1ns * 2^27) / rate[hz]</div><div class='add'>+	 */</div><div class='add'>+	return div_s64(1000000000LL &lt;&lt; 27, rate);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,</div><div class='del'>-			   enum rcar_gen4_ptp_reg_layout layout, u32 clock)</div><div class='add'>+			   enum rcar_gen4_ptp_reg_layout layout, u32 rate)</div><div class='ctx'> {</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='ctx'> 	if (ptp_priv-&gt;initialized)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_init(&amp;ptp_priv-&gt;lock);</div><div class='ctx'> </div><div class='del'>-	rcar_gen4_ptp_set_offs(ptp_priv, layout);</div><div class='add'>+	ret = rcar_gen4_ptp_set_offs(ptp_priv, layout);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-	ptp_priv-&gt;default_addend = clock;</div><div class='add'>+	ptp_priv-&gt;default_addend = rcar_gen4_ptp_rate_to_increment(rate);</div><div class='ctx'> 	iowrite32(ptp_priv-&gt;default_addend, ptp_priv-&gt;addr + ptp_priv-&gt;offs-&gt;increment);</div><div class='ctx'> 	ptp_priv-&gt;clock = ptp_clock_register(&amp;ptp_priv-&gt;info, NULL);</div><div class='ctx'> 	if (IS_ERR(ptp_priv-&gt;clock))</div><div class='hunk'>@@ -159,6 +176,7 @@ int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(rcar_gen4_ptp_register);</div><div class='ctx'> </div><div class='ctx'> int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv)</div><div class='ctx'> {</div><div class='hunk'>@@ -166,6 +184,7 @@ int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv)</div><div class='ctx'> </div><div class='ctx'> 	return ptp_clock_unregister(ptp_priv-&gt;clock);</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(rcar_gen4_ptp_unregister);</div><div class='ctx'> </div><div class='ctx'> struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='hunk'>@@ -179,3 +198,8 @@ struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	return ptp;</div><div class='ctx'> }</div><div class='add'>+EXPORT_SYMBOL_GPL(rcar_gen4_ptp_alloc);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Yoshihiro Shimoda");</div><div class='add'>+MODULE_DESCRIPTION("Renesas R-Car Gen4 gPTP driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/net/ethernet/renesas/rcar_gen4_ptp.h b/drivers/net/ethernet/renesas/rcar_gen4_ptp.h<br/>index b1bbea8d3a52..e22da5acd53d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rcar_gen4_ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/rcar_gen4_ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rcar_gen4_ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rcar_gen4_ptp.h</a></div><div class='hunk'>@@ -9,13 +9,10 @@</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/ptp_clock_kernel.h&gt;</div><div class='ctx'> </div><div class='del'>-#define PTPTIVC_INIT			0x19000000	/* 320MHz */</div><div class='del'>-#define RCAR_GEN4_PTP_CLOCK_S4		PTPTIVC_INIT</div><div class='ctx'> #define RCAR_GEN4_GPTP_OFFSET_S4	0x00018000</div><div class='ctx'> </div><div class='del'>-/* for rcar_gen4_ptp_init */</div><div class='ctx'> enum rcar_gen4_ptp_reg_layout {</div><div class='del'>-	RCAR_GEN4_PTP_REG_LAYOUT_S4</div><div class='add'>+	RCAR_GEN4_PTP_REG_LAYOUT</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* driver's definitions */</div><div class='hunk'>@@ -28,7 +25,7 @@ enum rcar_gen4_ptp_reg_layout {</div><div class='ctx'> </div><div class='ctx'> #define PTPRO				0</div><div class='ctx'> </div><div class='del'>-enum rcar_gen4_ptp_reg_s4 {</div><div class='add'>+enum rcar_gen4_ptp_reg {</div><div class='ctx'> 	PTPTMEC		= PTPRO + 0x0010,</div><div class='ctx'> 	PTPTMDC		= PTPRO + 0x0014,</div><div class='ctx'> 	PTPTIVC0	= PTPRO + 0x0020,</div><div class='hunk'>@@ -65,7 +62,7 @@ struct rcar_gen4_ptp_private {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> int rcar_gen4_ptp_register(struct rcar_gen4_ptp_private *ptp_priv,</div><div class='del'>-			   enum rcar_gen4_ptp_reg_layout layout, u32 clock);</div><div class='add'>+			   enum rcar_gen4_ptp_reg_layout layout, u32 rate);</div><div class='ctx'> int rcar_gen4_ptp_unregister(struct rcar_gen4_ptp_private *ptp_priv);</div><div class='ctx'> struct rcar_gen4_ptp_private *rcar_gen4_ptp_alloc(struct platform_device *pdev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c<br/>index 43a7795d6591..dcab638c57fe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rswitch.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/rswitch.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rswitch.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rswitch.c</a></div><div class='hunk'>@@ -56,7 +56,8 @@ static void rswitch_clock_disable(struct rswitch_private *priv)</div><div class='ctx'> 	iowrite32(RCDC_RCD, priv-&gt;addr + RCDC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port)</div><div class='add'>+static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr,</div><div class='add'>+					   unsigned int port)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val = ioread32(coma_addr + RCEC);</div><div class='ctx'> </div><div class='hunk'>@@ -66,7 +67,8 @@ static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port)</div><div class='ctx'> 		return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable)</div><div class='add'>+static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, unsigned int port,</div><div class='add'>+				     int enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='hunk'>@@ -100,7 +102,7 @@ static void rswitch_coma_init(struct rswitch_private *priv)</div><div class='ctx'> /* R-Switch-2 block (TOP) */</div><div class='ctx'> static void rswitch_top_init(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; RSWITCH_MAX_NUM_QUEUES; i++)</div><div class='ctx'> 		iowrite32((i / 16) &lt;&lt; (GWCA_INDEX * 8), priv-&gt;addr + TPEMIMC7(i));</div><div class='hunk'>@@ -109,7 +111,7 @@ static void rswitch_top_init(struct rswitch_private *priv)</div><div class='ctx'> /* Forwarding engine block (MFWD) */</div><div class='ctx'> static void rswitch_fwd_init(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	/* For ETHA */</div><div class='ctx'> 	for (i = 0; i &lt; RSWITCH_NUM_PORTS; i++) {</div><div class='hunk'>@@ -166,7 +168,7 @@ static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv)</div><div class='ctx'> static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx)</div><div class='ctx'> {</div><div class='ctx'> 	u32 *mask = tx ? priv-&gt;gwca.tx_irq_bits : priv-&gt;gwca.rx_irq_bits;</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; RSWITCH_NUM_IRQ_REGS; i++) {</div><div class='ctx'> 		if (dis[i] &amp; mask[i])</div><div class='hunk'>@@ -178,7 +180,7 @@ static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool</div><div class='ctx'> </div><div class='ctx'> static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; RSWITCH_NUM_IRQ_REGS; i++) {</div><div class='ctx'> 		dis[i] = ioread32(priv-&gt;addr + GWDIS(i));</div><div class='hunk'>@@ -186,23 +188,26 @@ static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable)</div><div class='add'>+static void rswitch_enadis_data_irq(struct rswitch_private *priv,</div><div class='add'>+				    unsigned int index, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32);</div><div class='ctx'> </div><div class='ctx'> 	iowrite32(BIT(index % 32), priv-&gt;addr + offs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rswitch_ack_data_irq(struct rswitch_private *priv, int index)</div><div class='add'>+static void rswitch_ack_data_irq(struct rswitch_private *priv,</div><div class='add'>+				 unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	u32 offs = GWDIS(index / 32);</div><div class='ctx'> </div><div class='ctx'> 	iowrite32(BIT(index % 32), priv-&gt;addr + offs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num)</div><div class='add'>+static unsigned int rswitch_next_queue_index(struct rswitch_gwca_queue *gq,</div><div class='add'>+					     bool cur, unsigned int num)</div><div class='ctx'> {</div><div class='del'>-	int index = cur ? gq-&gt;cur : gq-&gt;dirty;</div><div class='add'>+	unsigned int index = cur ? gq-&gt;cur : gq-&gt;dirty;</div><div class='ctx'> </div><div class='ctx'> 	if (index + num &gt;= gq-&gt;ring_size)</div><div class='ctx'> 		index = (index + num) % gq-&gt;ring_size;</div><div class='hunk'>@@ -212,7 +217,7 @@ static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int</div><div class='ctx'> 	return index;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq)</div><div class='add'>+static unsigned int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq)</div><div class='ctx'> {</div><div class='ctx'> 	if (gq-&gt;cur &gt;= gq-&gt;dirty)</div><div class='ctx'> 		return gq-&gt;cur - gq-&gt;dirty;</div><div class='hunk'>@@ -230,28 +235,28 @@ static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq,</div><div class='del'>-					int start_index, int num)</div><div class='add'>+static int rswitch_gwca_queue_alloc_rx_buf(struct rswitch_gwca_queue *gq,</div><div class='add'>+					   unsigned int start_index,</div><div class='add'>+					   unsigned int num)</div><div class='ctx'> {</div><div class='del'>-	int i, index;</div><div class='add'>+	unsigned int i, index;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num; i++) {</div><div class='ctx'> 		index = (i + start_index) % gq-&gt;ring_size;</div><div class='del'>-		if (gq-&gt;skbs[index])</div><div class='add'>+		if (gq-&gt;rx_bufs[index])</div><div class='ctx'> 			continue;</div><div class='del'>-		gq-&gt;skbs[index] = netdev_alloc_skb_ip_align(gq-&gt;ndev,</div><div class='del'>-							    PKT_BUF_SZ + RSWITCH_ALIGN - 1);</div><div class='del'>-		if (!gq-&gt;skbs[index])</div><div class='add'>+		gq-&gt;rx_bufs[index] = netdev_alloc_frag(RSWITCH_BUF_SIZE);</div><div class='add'>+		if (!gq-&gt;rx_bufs[index])</div><div class='ctx'> 			goto err;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='del'>-	for (i--; i &gt;= 0; i--) {</div><div class='add'>+	for (; i-- &gt; 0; ) {</div><div class='ctx'> 		index = (i + start_index) % gq-&gt;ring_size;</div><div class='del'>-		dev_kfree_skb(gq-&gt;skbs[index]);</div><div class='del'>-		gq-&gt;skbs[index] = NULL;</div><div class='add'>+		skb_free_frag(gq-&gt;rx_bufs[index]);</div><div class='add'>+		gq-&gt;rx_bufs[index] = NULL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return -ENOMEM;</div><div class='hunk'>@@ -260,7 +265,7 @@ err:</div><div class='ctx'> static void rswitch_gwca_queue_free(struct net_device *ndev,</div><div class='ctx'> 				    struct rswitch_gwca_queue *gq)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!gq-&gt;dir_tx) {</div><div class='ctx'> 		dma_free_coherent(ndev-&gt;dev.parent,</div><div class='hunk'>@@ -269,16 +274,19 @@ static void rswitch_gwca_queue_free(struct net_device *ndev,</div><div class='ctx'> 		gq-&gt;rx_ring = NULL;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; gq-&gt;ring_size; i++)</div><div class='del'>-			dev_kfree_skb(gq-&gt;skbs[i]);</div><div class='add'>+			skb_free_frag(gq-&gt;rx_bufs[i]);</div><div class='add'>+		kfree(gq-&gt;rx_bufs);</div><div class='add'>+		gq-&gt;rx_bufs = NULL;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		dma_free_coherent(ndev-&gt;dev.parent,</div><div class='ctx'> 				  sizeof(struct rswitch_ext_desc) *</div><div class='ctx'> 				  (gq-&gt;ring_size + 1), gq-&gt;tx_ring, gq-&gt;ring_dma);</div><div class='ctx'> 		gq-&gt;tx_ring = NULL;</div><div class='add'>+		kfree(gq-&gt;skbs);</div><div class='add'>+		gq-&gt;skbs = NULL;</div><div class='add'>+		kfree(gq-&gt;unmap_addrs);</div><div class='add'>+		gq-&gt;unmap_addrs = NULL;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	kfree(gq-&gt;skbs);</div><div class='del'>-	gq-&gt;skbs = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv)</div><div class='hunk'>@@ -294,25 +302,31 @@ static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv)</div><div class='ctx'> static int rswitch_gwca_queue_alloc(struct net_device *ndev,</div><div class='ctx'> 				    struct rswitch_private *priv,</div><div class='ctx'> 				    struct rswitch_gwca_queue *gq,</div><div class='del'>-				    bool dir_tx, int ring_size)</div><div class='add'>+				    bool dir_tx, unsigned int ring_size)</div><div class='ctx'> {</div><div class='del'>-	int i, bit;</div><div class='add'>+	unsigned int i, bit;</div><div class='ctx'> </div><div class='ctx'> 	gq-&gt;dir_tx = dir_tx;</div><div class='ctx'> 	gq-&gt;ring_size = ring_size;</div><div class='ctx'> 	gq-&gt;ndev = ndev;</div><div class='ctx'> </div><div class='del'>-	gq-&gt;skbs = kcalloc(gq-&gt;ring_size, sizeof(*gq-&gt;skbs), GFP_KERNEL);</div><div class='del'>-	if (!gq-&gt;skbs)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='ctx'> 	if (!dir_tx) {</div><div class='del'>-		rswitch_gwca_queue_alloc_skb(gq, 0, gq-&gt;ring_size);</div><div class='add'>+		gq-&gt;rx_bufs = kcalloc(gq-&gt;ring_size, sizeof(*gq-&gt;rx_bufs), GFP_KERNEL);</div><div class='add'>+		if (!gq-&gt;rx_bufs)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		if (rswitch_gwca_queue_alloc_rx_buf(gq, 0, gq-&gt;ring_size) &lt; 0)</div><div class='add'>+			goto out;</div><div class='ctx'> </div><div class='ctx'> 		gq-&gt;rx_ring = dma_alloc_coherent(ndev-&gt;dev.parent,</div><div class='ctx'> 						 sizeof(struct rswitch_ext_ts_desc) *</div><div class='ctx'> 						 (gq-&gt;ring_size + 1), &amp;gq-&gt;ring_dma, GFP_KERNEL);</div><div class='ctx'> 	} else {</div><div class='add'>+		gq-&gt;skbs = kcalloc(gq-&gt;ring_size, sizeof(*gq-&gt;skbs), GFP_KERNEL);</div><div class='add'>+		if (!gq-&gt;skbs)</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		gq-&gt;unmap_addrs = kcalloc(gq-&gt;ring_size, sizeof(*gq-&gt;unmap_addrs), GFP_KERNEL);</div><div class='add'>+		if (!gq-&gt;unmap_addrs)</div><div class='add'>+			goto out;</div><div class='ctx'> 		gq-&gt;tx_ring = dma_alloc_coherent(ndev-&gt;dev.parent,</div><div class='ctx'> 						 sizeof(struct rswitch_ext_desc) *</div><div class='ctx'> 						 (gq-&gt;ring_size + 1), &amp;gq-&gt;ring_dma, GFP_KERNEL);</div><div class='hunk'>@@ -351,22 +365,23 @@ static int rswitch_gwca_queue_format(struct net_device *ndev,</div><div class='ctx'> 				     struct rswitch_private *priv,</div><div class='ctx'> 				     struct rswitch_gwca_queue *gq)</div><div class='ctx'> {</div><div class='del'>-	int ring_size = sizeof(struct rswitch_ext_desc) * gq-&gt;ring_size;</div><div class='add'>+	unsigned int ring_size = sizeof(struct rswitch_ext_desc) * gq-&gt;ring_size;</div><div class='ctx'> 	struct rswitch_ext_desc *desc;</div><div class='ctx'> 	struct rswitch_desc *linkfix;</div><div class='ctx'> 	dma_addr_t dma_addr;</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	memset(gq-&gt;tx_ring, 0, ring_size);</div><div class='ctx'> 	for (i = 0, desc = gq-&gt;tx_ring; i &lt; gq-&gt;ring_size; i++, desc++) {</div><div class='ctx'> 		if (!gq-&gt;dir_tx) {</div><div class='ctx'> 			dma_addr = dma_map_single(ndev-&gt;dev.parent,</div><div class='del'>-						  gq-&gt;skbs[i]-&gt;data, PKT_BUF_SZ,</div><div class='add'>+						  gq-&gt;rx_bufs[i] + RSWITCH_HEADROOM,</div><div class='add'>+						  RSWITCH_MAP_BUF_SIZE,</div><div class='ctx'> 						  DMA_FROM_DEVICE);</div><div class='ctx'> 			if (dma_mapping_error(ndev-&gt;dev.parent, dma_addr))</div><div class='ctx'> 				goto err;</div><div class='ctx'> </div><div class='del'>-			desc-&gt;desc.info_ds = cpu_to_le16(PKT_BUF_SZ);</div><div class='add'>+			desc-&gt;desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE);</div><div class='ctx'> 			rswitch_desc_set_dptr(&amp;desc-&gt;desc, dma_addr);</div><div class='ctx'> 			desc-&gt;desc.die_dt = DT_FEMPTY | DIE;</div><div class='ctx'> 		} else {</div><div class='hunk'>@@ -387,10 +402,10 @@ static int rswitch_gwca_queue_format(struct net_device *ndev,</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='ctx'> 	if (!gq-&gt;dir_tx) {</div><div class='del'>-		for (i--, desc = gq-&gt;tx_ring; i &gt;= 0; i--, desc++) {</div><div class='add'>+		for (desc = gq-&gt;tx_ring; i-- &gt; 0; desc++) {</div><div class='ctx'> 			dma_addr = rswitch_desc_get_dptr(&amp;desc-&gt;desc);</div><div class='del'>-			dma_unmap_single(ndev-&gt;dev.parent, dma_addr, PKT_BUF_SZ,</div><div class='del'>-					 DMA_FROM_DEVICE);</div><div class='add'>+			dma_unmap_single(ndev-&gt;dev.parent, dma_addr,</div><div class='add'>+					 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -398,11 +413,12 @@ err:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv,</div><div class='del'>-				       int start_index, int num)</div><div class='add'>+				       unsigned int start_index,</div><div class='add'>+				       unsigned int num)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_gwca_queue *gq = &amp;priv-&gt;gwca.ts_queue;</div><div class='ctx'> 	struct rswitch_ts_desc *desc;</div><div class='del'>-	int i, index;</div><div class='add'>+	unsigned int i, index;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num; i++) {</div><div class='ctx'> 		index = (i + start_index) % gq-&gt;ring_size;</div><div class='hunk'>@@ -413,24 +429,26 @@ static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv,</div><div class='ctx'> </div><div class='ctx'> static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev,</div><div class='ctx'> 					  struct rswitch_gwca_queue *gq,</div><div class='del'>-					  int start_index, int num)</div><div class='add'>+					  unsigned int start_index,</div><div class='add'>+					  unsigned int num)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = netdev_priv(ndev);</div><div class='ctx'> 	struct rswitch_ext_ts_desc *desc;</div><div class='add'>+	unsigned int i, index;</div><div class='ctx'> 	dma_addr_t dma_addr;</div><div class='del'>-	int i, index;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; num; i++) {</div><div class='ctx'> 		index = (i + start_index) % gq-&gt;ring_size;</div><div class='ctx'> 		desc = &amp;gq-&gt;rx_ring[index];</div><div class='ctx'> 		if (!gq-&gt;dir_tx) {</div><div class='ctx'> 			dma_addr = dma_map_single(ndev-&gt;dev.parent,</div><div class='del'>-						  gq-&gt;skbs[index]-&gt;data, PKT_BUF_SZ,</div><div class='add'>+						  gq-&gt;rx_bufs[index] + RSWITCH_HEADROOM,</div><div class='add'>+						  RSWITCH_MAP_BUF_SIZE,</div><div class='ctx'> 						  DMA_FROM_DEVICE);</div><div class='ctx'> 			if (dma_mapping_error(ndev-&gt;dev.parent, dma_addr))</div><div class='ctx'> 				goto err;</div><div class='ctx'> </div><div class='del'>-			desc-&gt;desc.info_ds = cpu_to_le16(PKT_BUF_SZ);</div><div class='add'>+			desc-&gt;desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE);</div><div class='ctx'> 			rswitch_desc_set_dptr(&amp;desc-&gt;desc, dma_addr);</div><div class='ctx'> 			dma_wmb();</div><div class='ctx'> 			desc-&gt;desc.die_dt = DT_FEMPTY | DIE;</div><div class='hunk'>@@ -444,12 +462,12 @@ static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev,</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='ctx'> 	if (!gq-&gt;dir_tx) {</div><div class='del'>-		for (i--; i &gt;= 0; i--) {</div><div class='add'>+		for (; i-- &gt; 0; ) {</div><div class='ctx'> 			index = (i + start_index) % gq-&gt;ring_size;</div><div class='ctx'> 			desc = &amp;gq-&gt;rx_ring[index];</div><div class='ctx'> 			dma_addr = rswitch_desc_get_dptr(&amp;desc-&gt;desc);</div><div class='del'>-			dma_unmap_single(ndev-&gt;dev.parent, dma_addr, PKT_BUF_SZ,</div><div class='del'>-					 DMA_FROM_DEVICE);</div><div class='add'>+			dma_unmap_single(ndev-&gt;dev.parent, dma_addr,</div><div class='add'>+					 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -460,7 +478,7 @@ static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev,</div><div class='ctx'> 					    struct rswitch_private *priv,</div><div class='ctx'> 					    struct rswitch_gwca_queue *gq)</div><div class='ctx'> {</div><div class='del'>-	int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq-&gt;ring_size;</div><div class='add'>+	unsigned int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq-&gt;ring_size;</div><div class='ctx'> 	struct rswitch_ext_ts_desc *desc;</div><div class='ctx'> 	struct rswitch_desc *linkfix;</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -487,7 +505,7 @@ static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev,</div><div class='ctx'> </div><div class='ctx'> static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='del'>-	int i, num_queues = priv-&gt;gwca.num_queues;</div><div class='add'>+	unsigned int i, num_queues = priv-&gt;gwca.num_queues;</div><div class='ctx'> 	struct rswitch_gwca *gwca = &amp;priv-&gt;gwca;</div><div class='ctx'> 	struct device *dev = &amp;priv-&gt;pdev-&gt;dev;</div><div class='ctx'> </div><div class='hunk'>@@ -537,7 +555,7 @@ static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv)</div><div class='ctx'> static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_gwca_queue *gq;</div><div class='del'>-	int index;</div><div class='add'>+	unsigned int index;</div><div class='ctx'> </div><div class='ctx'> 	index = find_first_zero_bit(priv-&gt;gwca.used, priv-&gt;gwca.num_queues);</div><div class='ctx'> 	if (index &gt;= priv-&gt;gwca.num_queues)</div><div class='hunk'>@@ -583,7 +601,7 @@ static void rswitch_txdmac_free(struct net_device *ndev)</div><div class='ctx'> 	rswitch_gwca_put(rdev-&gt;priv, rdev-&gt;tx_queue);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_txdmac_init(struct rswitch_private *priv, int index)</div><div class='add'>+static int rswitch_txdmac_init(struct rswitch_private *priv, unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = priv-&gt;rdev[index];</div><div class='ctx'> </div><div class='hunk'>@@ -617,7 +635,7 @@ static void rswitch_rxdmac_free(struct net_device *ndev)</div><div class='ctx'> 	rswitch_gwca_put(rdev-&gt;priv, rdev-&gt;rx_queue);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_rxdmac_init(struct rswitch_private *priv, int index)</div><div class='add'>+static int rswitch_rxdmac_init(struct rswitch_private *priv, unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = priv-&gt;rdev[index];</div><div class='ctx'> 	struct net_device *ndev = rdev-&gt;ndev;</div><div class='hunk'>@@ -627,7 +645,8 @@ static int rswitch_rxdmac_init(struct rswitch_private *priv, int index)</div><div class='ctx'> </div><div class='ctx'> static int rswitch_gwca_hw_init(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='del'>-	int i, err;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='ctx'> 	err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='hunk'>@@ -649,6 +668,8 @@ static int rswitch_gwca_hw_init(struct rswitch_private *priv)</div><div class='ctx'> 	iowrite32(upper_32_bits(priv-&gt;gwca.linkfix_table_dma), priv-&gt;addr + GWDCBAC0);</div><div class='ctx'> 	iowrite32(lower_32_bits(priv-&gt;gwca.ts_queue.ring_dma), priv-&gt;addr + GWTDCAC10);</div><div class='ctx'> 	iowrite32(upper_32_bits(priv-&gt;gwca.ts_queue.ring_dma), priv-&gt;addr + GWTDCAC00);</div><div class='add'>+	iowrite32(GWMDNC_TSDMN(1) | GWMDNC_TXDMN(0x1e) | GWMDNC_RXDMN(0x1f),</div><div class='add'>+		  priv-&gt;addr + GWMDNC);</div><div class='ctx'> 	iowrite32(GWCA_TS_IRQ_BIT, priv-&gt;addr + GWTSDCC0);</div><div class='ctx'> </div><div class='ctx'> 	iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv-&gt;addr + GWTPC0);</div><div class='hunk'>@@ -693,15 +714,88 @@ static int rswitch_gwca_halt(struct rswitch_private *priv)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static struct sk_buff *rswitch_rx_handle_desc(struct net_device *ndev,</div><div class='add'>+					      struct rswitch_gwca_queue *gq,</div><div class='add'>+					      struct rswitch_ext_ts_desc *desc)</div><div class='add'>+{</div><div class='add'>+	dma_addr_t dma_addr = rswitch_desc_get_dptr(&amp;desc-&gt;desc);</div><div class='add'>+	u16 pkt_len = le16_to_cpu(desc-&gt;desc.info_ds) &amp; RX_DS;</div><div class='add'>+	u8 die_dt = desc-&gt;desc.die_dt &amp; DT_MASK;</div><div class='add'>+	struct sk_buff *skb = NULL;</div><div class='add'>+</div><div class='add'>+	dma_unmap_single(ndev-&gt;dev.parent, dma_addr, RSWITCH_MAP_BUF_SIZE,</div><div class='add'>+			 DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='add'>+	/* The RX descriptor order will be one of the following:</div><div class='add'>+	 * - FSINGLE</div><div class='add'>+	 * - FSTART -&gt; FEND</div><div class='add'>+	 * - FSTART -&gt; FMID -&gt; FEND</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	/* Check whether the descriptor is unexpected order */</div><div class='add'>+	switch (die_dt) {</div><div class='add'>+	case DT_FSTART:</div><div class='add'>+	case DT_FSINGLE:</div><div class='add'>+		if (gq-&gt;skb_fstart) {</div><div class='add'>+			dev_kfree_skb_any(gq-&gt;skb_fstart);</div><div class='add'>+			gq-&gt;skb_fstart = NULL;</div><div class='add'>+			ndev-&gt;stats.rx_dropped++;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case DT_FMID:</div><div class='add'>+	case DT_FEND:</div><div class='add'>+		if (!gq-&gt;skb_fstart) {</div><div class='add'>+			ndev-&gt;stats.rx_dropped++;</div><div class='add'>+			return NULL;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Handle the descriptor */</div><div class='add'>+	switch (die_dt) {</div><div class='add'>+	case DT_FSTART:</div><div class='add'>+	case DT_FSINGLE:</div><div class='add'>+		skb = build_skb(gq-&gt;rx_bufs[gq-&gt;cur], RSWITCH_BUF_SIZE);</div><div class='add'>+		if (skb) {</div><div class='add'>+			skb_reserve(skb, RSWITCH_HEADROOM);</div><div class='add'>+			skb_put(skb, pkt_len);</div><div class='add'>+			gq-&gt;pkt_len = pkt_len;</div><div class='add'>+			if (die_dt == DT_FSTART) {</div><div class='add'>+				gq-&gt;skb_fstart = skb;</div><div class='add'>+				skb = NULL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case DT_FMID:</div><div class='add'>+	case DT_FEND:</div><div class='add'>+		skb_add_rx_frag(gq-&gt;skb_fstart, skb_shinfo(gq-&gt;skb_fstart)-&gt;nr_frags,</div><div class='add'>+				virt_to_page(gq-&gt;rx_bufs[gq-&gt;cur]),</div><div class='add'>+				offset_in_page(gq-&gt;rx_bufs[gq-&gt;cur]) + RSWITCH_HEADROOM,</div><div class='add'>+				pkt_len, RSWITCH_BUF_SIZE);</div><div class='add'>+		if (die_dt == DT_FEND) {</div><div class='add'>+			skb = gq-&gt;skb_fstart;</div><div class='add'>+			gq-&gt;skb_fstart = NULL;</div><div class='add'>+		}</div><div class='add'>+		gq-&gt;pkt_len += pkt_len;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		netdev_err(ndev, "%s: unexpected value (%x)\n", __func__, die_dt);</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return skb;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static bool rswitch_rx(struct net_device *ndev, int *quota)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = netdev_priv(ndev);</div><div class='ctx'> 	struct rswitch_gwca_queue *gq = rdev-&gt;rx_queue;</div><div class='ctx'> 	struct rswitch_ext_ts_desc *desc;</div><div class='del'>-	int limit, boguscnt, num, ret;</div><div class='add'>+	int limit, boguscnt, ret;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='del'>-	dma_addr_t dma_addr;</div><div class='del'>-	u16 pkt_len;</div><div class='add'>+	unsigned int num;</div><div class='ctx'> 	u32 get_ts;</div><div class='ctx'> </div><div class='ctx'> 	if (*quota &lt;= 0)</div><div class='hunk'>@@ -713,11 +807,10 @@ static bool rswitch_rx(struct net_device *ndev, int *quota)</div><div class='ctx'> 	desc = &amp;gq-&gt;rx_ring[gq-&gt;cur];</div><div class='ctx'> 	while ((desc-&gt;desc.die_dt &amp; DT_MASK) != DT_FEMPTY) {</div><div class='ctx'> 		dma_rmb();</div><div class='del'>-		pkt_len = le16_to_cpu(desc-&gt;desc.info_ds) &amp; RX_DS;</div><div class='del'>-		skb = gq-&gt;skbs[gq-&gt;cur];</div><div class='del'>-		gq-&gt;skbs[gq-&gt;cur] = NULL;</div><div class='del'>-		dma_addr = rswitch_desc_get_dptr(&amp;desc-&gt;desc);</div><div class='del'>-		dma_unmap_single(ndev-&gt;dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE);</div><div class='add'>+		skb = rswitch_rx_handle_desc(ndev, gq, desc);</div><div class='add'>+		if (!skb)</div><div class='add'>+			goto out;</div><div class='add'>+</div><div class='ctx'> 		get_ts = rdev-&gt;priv-&gt;ptp_priv-&gt;tstamp_rx_ctrl &amp; RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT;</div><div class='ctx'> 		if (get_ts) {</div><div class='ctx'> 			struct skb_shared_hwtstamps *shhwtstamps;</div><div class='hunk'>@@ -729,12 +822,13 @@ static bool rswitch_rx(struct net_device *ndev, int *quota)</div><div class='ctx'> 			ts.tv_nsec = __le32_to_cpu(desc-&gt;ts_nsec &amp; cpu_to_le32(0x3fffffff));</div><div class='ctx'> 			shhwtstamps-&gt;hwtstamp = timespec64_to_ktime(ts);</div><div class='ctx'> 		}</div><div class='del'>-		skb_put(skb, pkt_len);</div><div class='ctx'> 		skb-&gt;protocol = eth_type_trans(skb, ndev);</div><div class='ctx'> 		napi_gro_receive(&amp;rdev-&gt;napi, skb);</div><div class='ctx'> 		rdev-&gt;ndev-&gt;stats.rx_packets++;</div><div class='del'>-		rdev-&gt;ndev-&gt;stats.rx_bytes += pkt_len;</div><div class='add'>+		rdev-&gt;ndev-&gt;stats.rx_bytes += gq-&gt;pkt_len;</div><div class='ctx'> </div><div class='add'>+out:</div><div class='add'>+		gq-&gt;rx_bufs[gq-&gt;cur] = NULL;</div><div class='ctx'> 		gq-&gt;cur = rswitch_next_queue_index(gq, true, 1);</div><div class='ctx'> 		desc = &amp;gq-&gt;rx_ring[gq-&gt;cur];</div><div class='ctx'> </div><div class='hunk'>@@ -743,7 +837,7 @@ static bool rswitch_rx(struct net_device *ndev, int *quota)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	num = rswitch_get_num_cur_queues(gq);</div><div class='del'>-	ret = rswitch_gwca_queue_alloc_skb(gq, gq-&gt;dirty, num);</div><div class='add'>+	ret = rswitch_gwca_queue_alloc_rx_buf(gq, gq-&gt;dirty, num);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto err;</div><div class='ctx'> 	ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq-&gt;dirty, num);</div><div class='hunk'>@@ -761,39 +855,32 @@ err:</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only)</div><div class='add'>+static void rswitch_tx_free(struct net_device *ndev)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = netdev_priv(ndev);</div><div class='ctx'> 	struct rswitch_gwca_queue *gq = rdev-&gt;tx_queue;</div><div class='ctx'> 	struct rswitch_ext_desc *desc;</div><div class='del'>-	dma_addr_t dma_addr;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='del'>-	int free_num = 0;</div><div class='del'>-	int size;</div><div class='ctx'> </div><div class='ctx'> 	for (; rswitch_get_num_cur_queues(gq) &gt; 0;</div><div class='ctx'> 	     gq-&gt;dirty = rswitch_next_queue_index(gq, false, 1)) {</div><div class='ctx'> 		desc = &amp;gq-&gt;tx_ring[gq-&gt;dirty];</div><div class='del'>-		if (free_txed_only &amp;&amp; (desc-&gt;desc.die_dt &amp; DT_MASK) != DT_FEMPTY)</div><div class='add'>+		if ((desc-&gt;desc.die_dt &amp; DT_MASK) != DT_FEMPTY)</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		dma_rmb();</div><div class='del'>-		size = le16_to_cpu(desc-&gt;desc.info_ds) &amp; TX_DS;</div><div class='ctx'> 		skb = gq-&gt;skbs[gq-&gt;dirty];</div><div class='ctx'> 		if (skb) {</div><div class='del'>-			dma_addr = rswitch_desc_get_dptr(&amp;desc-&gt;desc);</div><div class='del'>-			dma_unmap_single(ndev-&gt;dev.parent, dma_addr,</div><div class='del'>-					 size, DMA_TO_DEVICE);</div><div class='add'>+			dma_unmap_single(ndev-&gt;dev.parent,</div><div class='add'>+					 gq-&gt;unmap_addrs[gq-&gt;dirty],</div><div class='add'>+					 skb-&gt;len, DMA_TO_DEVICE);</div><div class='ctx'> 			dev_kfree_skb_any(gq-&gt;skbs[gq-&gt;dirty]);</div><div class='ctx'> 			gq-&gt;skbs[gq-&gt;dirty] = NULL;</div><div class='del'>-			free_num++;</div><div class='add'>+			rdev-&gt;ndev-&gt;stats.tx_packets++;</div><div class='add'>+			rdev-&gt;ndev-&gt;stats.tx_bytes += skb-&gt;len;</div><div class='ctx'> 		}</div><div class='ctx'> 		desc-&gt;desc.die_dt = DT_EEMPTY;</div><div class='del'>-		rdev-&gt;ndev-&gt;stats.tx_packets++;</div><div class='del'>-		rdev-&gt;ndev-&gt;stats.tx_bytes += size;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	return free_num;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int rswitch_poll(struct napi_struct *napi, int budget)</div><div class='hunk'>@@ -808,7 +895,7 @@ static int rswitch_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> 	priv = rdev-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> retry:</div><div class='del'>-	rswitch_tx_free(ndev, true);</div><div class='add'>+	rswitch_tx_free(ndev);</div><div class='ctx'> </div><div class='ctx'> 	if (rswitch_rx(ndev, &amp;quota))</div><div class='ctx'> 		goto out;</div><div class='hunk'>@@ -851,7 +938,7 @@ static void rswitch_queue_interrupt(struct net_device *ndev)</div><div class='ctx'> static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_gwca_queue *gq;</div><div class='del'>-	int i, index, bit;</div><div class='add'>+	unsigned int i, index, bit;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; priv-&gt;gwca.num_queues; i++) {</div><div class='ctx'> 		gq = &amp;priv-&gt;gwca.queues[i];</div><div class='hunk'>@@ -918,8 +1005,8 @@ static void rswitch_ts(struct rswitch_private *priv)</div><div class='ctx'> 	struct skb_shared_hwtstamps shhwtstamps;</div><div class='ctx'> 	struct rswitch_ts_desc *desc;</div><div class='ctx'> 	struct timespec64 ts;</div><div class='add'>+	unsigned int num;</div><div class='ctx'> 	u32 tag, port;</div><div class='del'>-	int num;</div><div class='ctx'> </div><div class='ctx'> 	desc = &amp;gq-&gt;ts_ring[gq-&gt;cur];</div><div class='ctx'> 	while ((desc-&gt;desc.die_dt &amp; DT_MASK) != DT_FEMPTY_ND) {</div><div class='hunk'>@@ -1438,7 +1525,7 @@ err_init_one:</div><div class='ctx'> </div><div class='ctx'> static void rswitch_ether_port_deinit_all(struct rswitch_private *priv)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='add'>+	unsigned int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; RSWITCH_NUM_PORTS; i++) {</div><div class='ctx'> 		phy_exit(priv-&gt;rdev[i]-&gt;serdes);</div><div class='hunk'>@@ -1500,43 +1587,18 @@ static int rswitch_stop(struct net_device *ndev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev)</div><div class='add'>+static bool rswitch_ext_desc_set_info1(struct rswitch_device *rdev,</div><div class='add'>+				       struct sk_buff *skb,</div><div class='add'>+				       struct rswitch_ext_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	struct rswitch_device *rdev = netdev_priv(ndev);</div><div class='del'>-	struct rswitch_gwca_queue *gq = rdev-&gt;tx_queue;</div><div class='del'>-	struct rswitch_ext_desc *desc;</div><div class='del'>-	int ret = NETDEV_TX_OK;</div><div class='del'>-	dma_addr_t dma_addr;</div><div class='del'>-</div><div class='del'>-	if (rswitch_get_num_cur_queues(gq) &gt;= gq-&gt;ring_size - 1) {</div><div class='del'>-		netif_stop_subqueue(ndev, 0);</div><div class='del'>-		return NETDEV_TX_BUSY;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (skb_put_padto(skb, ETH_ZLEN))</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	dma_addr = dma_map_single(ndev-&gt;dev.parent, skb-&gt;data, skb-&gt;len, DMA_TO_DEVICE);</div><div class='del'>-	if (dma_mapping_error(ndev-&gt;dev.parent, dma_addr)) {</div><div class='del'>-		dev_kfree_skb_any(skb);</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	gq-&gt;skbs[gq-&gt;cur] = skb;</div><div class='del'>-	desc = &amp;gq-&gt;tx_ring[gq-&gt;cur];</div><div class='del'>-	rswitch_desc_set_dptr(&amp;desc-&gt;desc, dma_addr);</div><div class='del'>-	desc-&gt;desc.info_ds = cpu_to_le16(skb-&gt;len);</div><div class='del'>-</div><div class='ctx'> 	desc-&gt;info1 = cpu_to_le64(INFO1_DV(BIT(rdev-&gt;etha-&gt;index)) |</div><div class='ctx'> 				  INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT);</div><div class='ctx'> 	if (skb_shinfo(skb)-&gt;tx_flags &amp; SKBTX_HW_TSTAMP) {</div><div class='ctx'> 		struct rswitch_gwca_ts_info *ts_info;</div><div class='ctx'> </div><div class='ctx'> 		ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC);</div><div class='del'>-		if (!ts_info) {</div><div class='del'>-			dma_unmap_single(ndev-&gt;dev.parent, dma_addr, skb-&gt;len, DMA_TO_DEVICE);</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-		}</div><div class='add'>+		if (!ts_info)</div><div class='add'>+			return false;</div><div class='ctx'> </div><div class='ctx'> 		skb_shinfo(skb)-&gt;tx_flags |= SKBTX_IN_PROGRESS;</div><div class='ctx'> 		rdev-&gt;ts_tag++;</div><div class='hunk'>@@ -1550,15 +1612,102 @@ static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *nd</div><div class='ctx'> 		skb_tx_timestamp(skb);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool rswitch_ext_desc_set(struct rswitch_device *rdev,</div><div class='add'>+				 struct sk_buff *skb,</div><div class='add'>+				 struct rswitch_ext_desc *desc,</div><div class='add'>+				 dma_addr_t dma_addr, u16 len, u8 die_dt)</div><div class='add'>+{</div><div class='add'>+	rswitch_desc_set_dptr(&amp;desc-&gt;desc, dma_addr);</div><div class='add'>+	desc-&gt;desc.info_ds = cpu_to_le16(len);</div><div class='add'>+	if (!rswitch_ext_desc_set_info1(rdev, skb, desc))</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='ctx'> 	dma_wmb();</div><div class='ctx'> </div><div class='del'>-	desc-&gt;desc.die_dt = DT_FSINGLE | DIE;</div><div class='add'>+	desc-&gt;desc.die_dt = die_dt;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u8 rswitch_ext_desc_get_die_dt(unsigned int nr_desc, unsigned int index)</div><div class='add'>+{</div><div class='add'>+	if (nr_desc == 1)</div><div class='add'>+		return DT_FSINGLE | DIE;</div><div class='add'>+	if (index == 0)</div><div class='add'>+		return DT_FSTART;</div><div class='add'>+	if (nr_desc - 1 == index)</div><div class='add'>+		return DT_FEND | DIE;</div><div class='add'>+	return DT_FMID;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u16 rswitch_ext_desc_get_len(u8 die_dt, unsigned int orig_len)</div><div class='add'>+{</div><div class='add'>+	switch (die_dt &amp; DT_MASK) {</div><div class='add'>+	case DT_FSINGLE:</div><div class='add'>+	case DT_FEND:</div><div class='add'>+		return (orig_len % RSWITCH_DESC_BUF_SIZE) ?: RSWITCH_DESC_BUF_SIZE;</div><div class='add'>+	case DT_FSTART:</div><div class='add'>+	case DT_FMID:</div><div class='add'>+		return RSWITCH_DESC_BUF_SIZE;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct rswitch_device *rdev = netdev_priv(ndev);</div><div class='add'>+	struct rswitch_gwca_queue *gq = rdev-&gt;tx_queue;</div><div class='add'>+	dma_addr_t dma_addr, dma_addr_orig;</div><div class='add'>+	netdev_tx_t ret = NETDEV_TX_OK;</div><div class='add'>+	struct rswitch_ext_desc *desc;</div><div class='add'>+	unsigned int i, nr_desc;</div><div class='add'>+	u8 die_dt;</div><div class='add'>+	u16 len;</div><div class='add'>+</div><div class='add'>+	nr_desc = (skb-&gt;len - 1) / RSWITCH_DESC_BUF_SIZE + 1;</div><div class='add'>+	if (rswitch_get_num_cur_queues(gq) &gt;= gq-&gt;ring_size - nr_desc) {</div><div class='add'>+		netif_stop_subqueue(ndev, 0);</div><div class='add'>+		return NETDEV_TX_BUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (skb_put_padto(skb, ETH_ZLEN))</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	dma_addr_orig = dma_map_single(ndev-&gt;dev.parent, skb-&gt;data, skb-&gt;len, DMA_TO_DEVICE);</div><div class='add'>+	if (dma_mapping_error(ndev-&gt;dev.parent, dma_addr_orig))</div><div class='add'>+		goto err_kfree;</div><div class='add'>+</div><div class='add'>+	gq-&gt;skbs[gq-&gt;cur] = skb;</div><div class='add'>+	gq-&gt;unmap_addrs[gq-&gt;cur] = dma_addr_orig;</div><div class='add'>+</div><div class='add'>+	/* DT_FSTART should be set at last. So, this is reverse order. */</div><div class='add'>+	for (i = nr_desc; i-- &gt; 0; ) {</div><div class='add'>+		desc = &amp;gq-&gt;tx_ring[rswitch_next_queue_index(gq, true, i)];</div><div class='add'>+		die_dt = rswitch_ext_desc_get_die_dt(nr_desc, i);</div><div class='add'>+		dma_addr = dma_addr_orig + i * RSWITCH_DESC_BUF_SIZE;</div><div class='add'>+		len = rswitch_ext_desc_get_len(die_dt, skb-&gt;len);</div><div class='add'>+		if (!rswitch_ext_desc_set(rdev, skb, desc, dma_addr, len, die_dt))</div><div class='add'>+			goto err_unmap;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	wmb();	/* gq-&gt;cur must be incremented after die_dt was set */</div><div class='ctx'> </div><div class='del'>-	gq-&gt;cur = rswitch_next_queue_index(gq, true, 1);</div><div class='add'>+	gq-&gt;cur = rswitch_next_queue_index(gq, true, nr_desc);</div><div class='ctx'> 	rswitch_modify(rdev-&gt;addr, GWTRC(gq-&gt;index), 0, BIT(gq-&gt;index % 32));</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='add'>+</div><div class='add'>+err_unmap:</div><div class='add'>+	dma_unmap_single(ndev-&gt;dev.parent, dma_addr_orig, skb-&gt;len, DMA_TO_DEVICE);</div><div class='add'>+</div><div class='add'>+err_kfree:</div><div class='add'>+	dev_kfree_skb_any(skb);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct net_device_stats *rswitch_get_stats(struct net_device *ndev)</div><div class='hunk'>@@ -1689,7 +1838,7 @@ static const struct of_device_id renesas_eth_sw_of_table[] = {</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table);</div><div class='ctx'> </div><div class='del'>-static void rswitch_etha_init(struct rswitch_private *priv, int index)</div><div class='add'>+static void rswitch_etha_init(struct rswitch_private *priv, unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_etha *etha = &amp;priv-&gt;etha[index];</div><div class='ctx'> </div><div class='hunk'>@@ -1705,7 +1854,7 @@ static void rswitch_etha_init(struct rswitch_private *priv, int index)</div><div class='ctx'> 	etha-&gt;psmcs = clk_get_rate(priv-&gt;clk) / 100000 / (25 * 2) - 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int rswitch_device_alloc(struct rswitch_private *priv, int index)</div><div class='add'>+static int rswitch_device_alloc(struct rswitch_private *priv, unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct platform_device *pdev = priv-&gt;pdev;</div><div class='ctx'> 	struct rswitch_device *rdev;</div><div class='hunk'>@@ -1734,6 +1883,8 @@ static int rswitch_device_alloc(struct rswitch_private *priv, int index)</div><div class='ctx'> 	snprintf(ndev-&gt;name, IFNAMSIZ, "tsn%d", index);</div><div class='ctx'> 	ndev-&gt;netdev_ops = &amp;rswitch_netdev_ops;</div><div class='ctx'> 	ndev-&gt;ethtool_ops = &amp;rswitch_ethtool_ops;</div><div class='add'>+	ndev-&gt;max_mtu = RSWITCH_MAX_MTU;</div><div class='add'>+	ndev-&gt;min_mtu = ETH_MIN_MTU;</div><div class='ctx'> </div><div class='ctx'> 	netif_napi_add(ndev, &amp;rdev-&gt;napi, rswitch_poll);</div><div class='ctx'> </div><div class='hunk'>@@ -1776,7 +1927,7 @@ out_get_params:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void rswitch_device_free(struct rswitch_private *priv, int index)</div><div class='add'>+static void rswitch_device_free(struct rswitch_private *priv, unsigned int index)</div><div class='ctx'> {</div><div class='ctx'> 	struct rswitch_device *rdev = priv-&gt;rdev[index];</div><div class='ctx'> 	struct net_device *ndev = rdev-&gt;ndev;</div><div class='hunk'>@@ -1828,8 +1979,8 @@ static int rswitch_init(struct rswitch_private *priv)</div><div class='ctx'> </div><div class='ctx'> 	rswitch_fwd_init(priv);</div><div class='ctx'> </div><div class='del'>-	err = rcar_gen4_ptp_register(priv-&gt;ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4,</div><div class='del'>-				     RCAR_GEN4_PTP_CLOCK_S4);</div><div class='add'>+	err = rcar_gen4_ptp_register(priv-&gt;ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT,</div><div class='add'>+				     clk_get_rate(priv-&gt;clk));</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		goto err_ptp_register;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h<br/>index 27c9d3872c0e..72e3ff596d31 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rswitch.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/renesas/rswitch.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/renesas/rswitch.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/renesas/rswitch.h</a></div><div class='hunk'>@@ -26,11 +26,17 @@</div><div class='ctx'> 		else</div><div class='ctx'> </div><div class='ctx'> #define TX_RING_SIZE		1024</div><div class='del'>-#define RX_RING_SIZE		1024</div><div class='add'>+#define RX_RING_SIZE		4096</div><div class='ctx'> #define TS_RING_SIZE		(TX_RING_SIZE * RSWITCH_NUM_PORTS)</div><div class='ctx'> </div><div class='del'>-#define PKT_BUF_SZ		1584</div><div class='add'>+#define RSWITCH_MAX_MTU		9600</div><div class='add'>+#define RSWITCH_HEADROOM	(NET_SKB_PAD + NET_IP_ALIGN)</div><div class='add'>+#define RSWITCH_DESC_BUF_SIZE	2048</div><div class='add'>+#define RSWITCH_TAILROOM	SKB_DATA_ALIGN(sizeof(struct skb_shared_info))</div><div class='ctx'> #define RSWITCH_ALIGN		128</div><div class='add'>+#define RSWITCH_BUF_SIZE	(RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \</div><div class='add'>+				 RSWITCH_TAILROOM + RSWITCH_ALIGN)</div><div class='add'>+#define RSWITCH_MAP_BUF_SIZE	(RSWITCH_BUF_SIZE - RSWITCH_HEADROOM)</div><div class='ctx'> #define RSWITCH_MAX_CTAG_PCP	7</div><div class='ctx'> </div><div class='ctx'> #define RSWITCH_TIMEOUT_US	100000</div><div class='hunk'>@@ -768,6 +774,10 @@ enum rswitch_gwca_mode {</div><div class='ctx'> #define GWARIRM_ARIOG		BIT(0)</div><div class='ctx'> #define GWARIRM_ARR		BIT(1)</div><div class='ctx'> </div><div class='add'>+#define GWMDNC_TSDMN(num)	(((num) &lt;&lt; 16) &amp; GENMASK(17, 16))</div><div class='add'>+#define GWMDNC_TXDMN(num)	(((num) &lt;&lt; 8) &amp; GENMASK(12, 8))</div><div class='add'>+#define GWMDNC_RXDMN(num)	((num) &amp; GENMASK(4, 0))</div><div class='add'>+</div><div class='ctx'> #define GWDCC_BALR		BIT(24)</div><div class='ctx'> #define GWDCC_DCP_MASK		GENMASK(18, 16)</div><div class='ctx'> #define GWDCC_DCP(prio)		FIELD_PREP(GWDCC_DCP_MASK, (prio))</div><div class='hunk'>@@ -909,7 +919,7 @@ struct rswitch_ext_ts_desc {</div><div class='ctx'> } __packed;</div><div class='ctx'> </div><div class='ctx'> struct rswitch_etha {</div><div class='del'>-	int index;</div><div class='add'>+	unsigned int index;</div><div class='ctx'> 	void __iomem *addr;</div><div class='ctx'> 	void __iomem *coma_addr;</div><div class='ctx'> 	bool external_phy;</div><div class='hunk'>@@ -938,15 +948,28 @@ struct rswitch_gwca_queue {</div><div class='ctx'> </div><div class='ctx'> 	/* Common */</div><div class='ctx'> 	dma_addr_t ring_dma;</div><div class='del'>-	int ring_size;</div><div class='del'>-	int cur;</div><div class='del'>-	int dirty;</div><div class='add'>+	unsigned int ring_size;</div><div class='add'>+	unsigned int cur;</div><div class='add'>+	unsigned int dirty;</div><div class='ctx'> </div><div class='del'>-	/* For [rt]_ring */</div><div class='del'>-	int index;</div><div class='add'>+	/* For [rt]x_ring */</div><div class='add'>+	unsigned int index;</div><div class='ctx'> 	bool dir_tx;</div><div class='del'>-	struct sk_buff **skbs;</div><div class='ctx'> 	struct net_device *ndev;	/* queue to ndev for irq */</div><div class='add'>+</div><div class='add'>+	union {</div><div class='add'>+		/* For TX */</div><div class='add'>+		struct {</div><div class='add'>+			struct sk_buff **skbs;</div><div class='add'>+			dma_addr_t *unmap_addrs;</div><div class='add'>+		};</div><div class='add'>+		/* For RX */</div><div class='add'>+		struct {</div><div class='add'>+			void **rx_bufs;</div><div class='add'>+			struct sk_buff *skb_fstart;</div><div class='add'>+			u16 pkt_len;</div><div class='add'>+		};</div><div class='add'>+	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct rswitch_gwca_ts_info {</div><div class='hunk'>@@ -959,7 +982,7 @@ struct rswitch_gwca_ts_info {</div><div class='ctx'> </div><div class='ctx'> #define RSWITCH_NUM_IRQ_REGS	(RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))</div><div class='ctx'> struct rswitch_gwca {</div><div class='del'>-	int index;</div><div class='add'>+	unsigned int index;</div><div class='ctx'> 	struct rswitch_desc *linkfix_table;</div><div class='ctx'> 	dma_addr_t linkfix_table_dma;</div><div class='ctx'> 	u32 linkfix_table_size;</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/ef10.c<br/>index 6dfa062feebc..8fa6c0e9195b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ef10.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ef10.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ef10.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ef10.c</a></div><div class='hunk'>@@ -3706,13 +3706,13 @@ static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,</div><div class='del'>-					 struct hwtstamp_config *init)</div><div class='add'>+					 struct kernel_hwtstamp_config *init)</div><div class='ctx'> {</div><div class='ctx'> 	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,</div><div class='del'>-				      struct hwtstamp_config *init)</div><div class='add'>+				      struct kernel_hwtstamp_config *init)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ef100_ethtool.c b/drivers/net/ethernet/sfc/ef100_ethtool.c<br/>index 702abbe59b76..cf55202b3a7b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ef100_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ef100_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ef100_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ef100_ethtool.c</a></div><div class='hunk'>@@ -37,6 +37,7 @@ ef100_ethtool_get_ringparam(struct net_device *net_dev,</div><div class='ctx'> /*	Ethtool options available</div><div class='ctx'>  */</div><div class='ctx'> const struct ethtool_ops ef100_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.get_drvinfo		= efx_ethtool_get_drvinfo,</div><div class='ctx'> 	.get_msglevel		= efx_ethtool_get_msglevel,</div><div class='ctx'> 	.set_msglevel		= efx_ethtool_set_msglevel,</div><div class='hunk'>@@ -60,8 +61,6 @@ const struct ethtool_ops ef100_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_key_size	= efx_ethtool_get_rxfh_key_size,</div><div class='ctx'> 	.get_rxfh		= efx_ethtool_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= efx_ethtool_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= efx_ethtool_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= efx_ethtool_set_rxfh_context,</div><div class='ctx'> </div><div class='ctx'> 	.get_module_info	= efx_ethtool_get_module_info,</div><div class='ctx'> 	.get_module_eeprom	= efx_ethtool_get_module_eeprom,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c<br/>index 19f4b4d0b851..e9d9de8e648a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/efx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/efx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/efx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/efx.c</a></div><div class='hunk'>@@ -495,11 +495,6 @@ static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)</div><div class='ctx'> 	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='ctx'> 	struct mii_ioctl_data *data = if_mii(ifr);</div><div class='ctx'> </div><div class='del'>-	if (cmd == SIOCSHWTSTAMP)</div><div class='del'>-		return efx_ptp_set_ts_config(efx, ifr);</div><div class='del'>-	if (cmd == SIOCGHWTSTAMP)</div><div class='del'>-		return efx_ptp_get_ts_config(efx, ifr);</div><div class='del'>-</div><div class='ctx'> 	/* Convert phy_id from older PRTAD/DEVAD format */</div><div class='ctx'> 	if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &amp;&amp;</div><div class='ctx'> 	    (data-&gt;phy_id &amp; 0xfc00) == 0x0400)</div><div class='hunk'>@@ -581,6 +576,23 @@ static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vi</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int efx_hwtstamp_set(struct net_device *net_dev,</div><div class='add'>+			    struct kernel_hwtstamp_config *config,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='add'>+</div><div class='add'>+	return efx_ptp_set_ts_config(efx, config, extack);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int efx_hwtstamp_get(struct net_device *net_dev,</div><div class='add'>+			    struct kernel_hwtstamp_config *config)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='add'>+</div><div class='add'>+	return efx_ptp_get_ts_config(efx, config);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops efx_netdev_ops = {</div><div class='ctx'> 	.ndo_open		= efx_net_open,</div><div class='ctx'> 	.ndo_stop		= efx_net_stop,</div><div class='hunk'>@@ -596,6 +608,8 @@ static const struct net_device_ops efx_netdev_ops = {</div><div class='ctx'> 	.ndo_features_check	= efx_features_check,</div><div class='ctx'> 	.ndo_vlan_rx_add_vid	= efx_vlan_rx_add_vid,</div><div class='ctx'> 	.ndo_vlan_rx_kill_vid	= efx_vlan_rx_kill_vid,</div><div class='add'>+	.ndo_hwtstamp_set	= efx_hwtstamp_set,</div><div class='add'>+	.ndo_hwtstamp_get	= efx_hwtstamp_get,</div><div class='ctx'> #ifdef CONFIG_SFC_SRIOV</div><div class='ctx'> 	.ndo_set_vf_mac		= efx_sriov_set_vf_mac,</div><div class='ctx'> 	.ndo_set_vf_vlan	= efx_sriov_set_vf_vlan,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ethtool.c b/drivers/net/ethernet/sfc/ethtool.c<br/>index 364323599f7b..37c69c8d90b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool.c</a></div><div class='hunk'>@@ -240,6 +240,7 @@ static int efx_ethtool_get_ts_info(struct net_device *net_dev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct ethtool_ops efx_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USECS_IRQ |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX,</div><div class='hunk'>@@ -269,8 +270,6 @@ const struct ethtool_ops efx_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_key_size	= efx_ethtool_get_rxfh_key_size,</div><div class='ctx'> 	.get_rxfh		= efx_ethtool_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= efx_ethtool_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= efx_ethtool_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= efx_ethtool_set_rxfh_context,</div><div class='ctx'> 	.get_ts_info		= efx_ethtool_get_ts_info,</div><div class='ctx'> 	.get_module_info	= efx_ethtool_get_module_info,</div><div class='ctx'> 	.get_module_eeprom	= efx_ethtool_get_module_eeprom,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ethtool_common.c b/drivers/net/ethernet/sfc/ethtool_common.c<br/>index a8cbceeb301b..7d5e5db4eac5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ethtool_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool_common.c</a></div><div class='hunk'>@@ -1163,48 +1163,8 @@ u32 efx_ethtool_get_rxfh_key_size(struct net_device *net_dev)</div><div class='ctx'> 	return efx-&gt;type-&gt;rx_hash_key_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_ethtool_get_rxfh(struct net_device *net_dev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	rc = efx-&gt;type-&gt;rx_pull_rss_config(efx);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, efx-&gt;rss_context.rx_indir_table,</div><div class='del'>-		       sizeof(efx-&gt;rss_context.rx_indir_table));</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, efx-&gt;rss_context.rx_hash_key,</div><div class='del'>-		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int efx_ethtool_set_rxfh(struct net_device *net_dev, const u32 *indir,</div><div class='del'>-			 const u8 *key, const u8 hfunc)</div><div class='del'>-{</div><div class='del'>-	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='del'>-</div><div class='del'>-	/* Hash function is Toeplitz, cannot be changed */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	if (!indir &amp;&amp; !key)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (!key)</div><div class='del'>-		key = efx-&gt;rss_context.rx_hash_key;</div><div class='del'>-	if (!indir)</div><div class='del'>-		indir = efx-&gt;rss_context.rx_indir_table;</div><div class='del'>-</div><div class='del'>-	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, indir, key);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int efx_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='del'>-				 u8 *key, u8 *hfunc, u32 rss_context)</div><div class='add'>+static int efx_ethtool_get_rxfh_context(struct net_device *net_dev,</div><div class='add'>+					struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='ctx'> 	struct efx_rss_context *ctx;</div><div class='hunk'>@@ -1214,7 +1174,7 @@ int efx_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;efx-&gt;rss_lock);</div><div class='del'>-	ctx = efx_find_rss_context_entry(efx, rss_context);</div><div class='add'>+	ctx = efx_find_rss_context_entry(efx, rxfh-&gt;rss_context);</div><div class='ctx'> 	if (!ctx) {</div><div class='ctx'> 		rc = -ENOENT;</div><div class='ctx'> 		goto out_unlock;</div><div class='hunk'>@@ -1223,37 +1183,60 @@ int efx_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, ctx-&gt;rx_indir_table, sizeof(ctx-&gt;rx_indir_table));</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, ctx-&gt;rx_hash_key, efx-&gt;type-&gt;rx_hash_key_size);</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, ctx-&gt;rx_indir_table,</div><div class='add'>+		       sizeof(ctx-&gt;rx_indir_table));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, ctx-&gt;rx_hash_key,</div><div class='add'>+		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;efx-&gt;rss_lock);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='del'>-				 const u32 *indir, const u8 *key,</div><div class='del'>-				 const u8 hfunc, u32 *rss_context,</div><div class='del'>-				 bool delete)</div><div class='add'>+int efx_ethtool_get_rxfh(struct net_device *net_dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		return efx_ethtool_get_rxfh_context(net_dev, rxfh);</div><div class='add'>+</div><div class='add'>+	rc = efx-&gt;type-&gt;rx_pull_rss_config(efx);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, efx-&gt;rss_context.rx_indir_table,</div><div class='add'>+		       sizeof(efx-&gt;rss_context.rx_indir_table));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, efx-&gt;rss_context.rx_hash_key,</div><div class='add'>+		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int efx_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='add'>+					struct ethtool_rxfh_param *rxfh,</div><div class='add'>+					struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='add'>+	u32 *rss_context = &amp;rxfh-&gt;rss_context;</div><div class='ctx'> 	struct efx_rss_context *ctx;</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='ctx'> 	bool allocated = false;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (!efx-&gt;type-&gt;rx_push_rss_context_config)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	/* Hash function is Toeplitz, cannot be changed */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;efx-&gt;rss_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {</div><div class='del'>-		if (delete) {</div><div class='add'>+		if (rxfh-&gt;rss_delete) {</div><div class='ctx'> 			/* alloc + delete == Nothing to do */</div><div class='ctx'> 			rc = -EINVAL;</div><div class='ctx'> 			goto out_unlock;</div><div class='hunk'>@@ -1276,7 +1259,7 @@ int efx_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (delete) {</div><div class='add'>+	if (rxfh-&gt;rss_delete) {</div><div class='ctx'> 		/* delete this context */</div><div class='ctx'> 		rc = efx-&gt;type-&gt;rx_push_rss_context_config(efx, ctx, NULL, NULL);</div><div class='ctx'> 		if (!rc)</div><div class='hunk'>@@ -1299,6 +1282,33 @@ out_unlock:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int efx_ethtool_set_rxfh(struct net_device *net_dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='add'>+</div><div class='add'>+	/* Hash function is Toeplitz, cannot be changed */</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		return efx_ethtool_set_rxfh_context(net_dev, rxfh, extack);</div><div class='add'>+</div><div class='add'>+	if (!indir &amp;&amp; !key)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!key)</div><div class='add'>+		key = efx-&gt;rss_context.rx_hash_key;</div><div class='add'>+	if (!indir)</div><div class='add'>+		indir = efx-&gt;rss_context.rx_indir_table;</div><div class='add'>+</div><div class='add'>+	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, indir, key);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int efx_ethtool_reset(struct net_device *net_dev, u32 *flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = efx_netdev_priv(net_dev);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ethtool_common.h b/drivers/net/ethernet/sfc/ethtool_common.h<br/>index 659491932101..a680e5980213 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ethtool_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ethtool_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ethtool_common.h</a></div><div class='hunk'>@@ -44,16 +44,11 @@ int efx_ethtool_set_rxnfc(struct net_device *net_dev,</div><div class='ctx'> 			  struct ethtool_rxnfc *info);</div><div class='ctx'> u32 efx_ethtool_get_rxfh_indir_size(struct net_device *net_dev);</div><div class='ctx'> u32 efx_ethtool_get_rxfh_key_size(struct net_device *net_dev);</div><div class='del'>-int efx_ethtool_get_rxfh(struct net_device *net_dev, u32 *indir, u8 *key,</div><div class='del'>-			 u8 *hfunc);</div><div class='add'>+int efx_ethtool_get_rxfh(struct net_device *net_dev,</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh);</div><div class='ctx'> int efx_ethtool_set_rxfh(struct net_device *net_dev,</div><div class='del'>-			 const u32 *indir, const u8 *key, const u8 hfunc);</div><div class='del'>-int efx_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='del'>-				 u8 *key, u8 *hfunc, u32 rss_context);</div><div class='del'>-int efx_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='del'>-				 const u32 *indir, const u8 *key,</div><div class='del'>-				 const u8 hfunc, u32 *rss_context,</div><div class='del'>-				 bool delete);</div><div class='add'>+			 struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			 struct netlink_ext_ack *extack);</div><div class='ctx'> int efx_ethtool_reset(struct net_device *net_dev, u32 *flags);</div><div class='ctx'> int efx_ethtool_get_module_eeprom(struct net_device *net_dev,</div><div class='ctx'> 				  struct ethtool_eeprom *ee,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/falcon/ethtool.c b/drivers/net/ethernet/sfc/falcon/ethtool.c<br/>index 3976a333f7e3..f4db683b80f7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/falcon/ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/falcon/ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/falcon/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/falcon/ethtool.c</a></div><div class='hunk'>@@ -1257,31 +1257,33 @@ static u32 ef4_ethtool_get_rxfh_indir_size(struct net_device *net_dev)</div><div class='ctx'> 		0 : ARRAY_SIZE(efx-&gt;rx_indir_table));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ef4_ethtool_get_rxfh(struct net_device *net_dev, u32 *indir, u8 *key,</div><div class='del'>-				u8 *hfunc)</div><div class='add'>+static int ef4_ethtool_get_rxfh(struct net_device *net_dev,</div><div class='add'>+				struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct ef4_nic *efx = netdev_priv(net_dev);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, efx-&gt;rx_indir_table, sizeof(efx-&gt;rx_indir_table));</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, efx-&gt;rx_indir_table,</div><div class='add'>+		       sizeof(efx-&gt;rx_indir_table));</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ef4_ethtool_set_rxfh(struct net_device *net_dev, const u32 *indir,</div><div class='del'>-				const u8 *key, const u8 hfunc)</div><div class='add'>+static int ef4_ethtool_set_rxfh(struct net_device *net_dev,</div><div class='add'>+				struct ethtool_rxfh_param *rxfh,</div><div class='add'>+				struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct ef4_nic *efx = netdev_priv(net_dev);</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	if (!indir)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, indir);</div><div class='add'>+	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, rxfh-&gt;indir);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ef4_ethtool_get_module_eeprom(struct net_device *net_dev,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/net_driver.h b/drivers/net/ethernet/sfc/net_driver.h<br/>index 27d86e90a3bb..f2dd7feb0e0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/net_driver.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/net_driver.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/net_driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/net_driver.h</a></div><div class='hunk'>@@ -1473,7 +1473,7 @@ struct efx_nic_type {</div><div class='ctx'> 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);</div><div class='ctx'> 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);</div><div class='ctx'> 	int (*ptp_set_ts_config)(struct efx_nic *efx,</div><div class='del'>-				 struct hwtstamp_config *init);</div><div class='add'>+				 struct kernel_hwtstamp_config *init);</div><div class='ctx'> 	int (*sriov_configure)(struct efx_nic *efx, int num_vfs);</div><div class='ctx'> 	int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);</div><div class='ctx'> 	int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ptp.c b/drivers/net/ethernet/sfc/ptp.c<br/>index b04fdbb8aece..c3bffbf0ba2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ptp.c</a></div><div class='hunk'>@@ -301,7 +301,7 @@ struct efx_ptp_data {</div><div class='ctx'> 	bool reset_required;</div><div class='ctx'> 	struct list_head rxfilters_mcast;</div><div class='ctx'> 	struct list_head rxfilters_ucast;</div><div class='del'>-	struct hwtstamp_config config;</div><div class='add'>+	struct kernel_hwtstamp_config config;</div><div class='ctx'> 	bool enabled;</div><div class='ctx'> 	unsigned int mode;</div><div class='ctx'> 	void (*ns_to_nic_time)(s64 ns, u32 *nic_major, u32 *nic_minor);</div><div class='hunk'>@@ -1848,7 +1848,7 @@ int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int efx_ptp_ts_init(struct efx_nic *efx, struct hwtstamp_config *init)</div><div class='add'>+static int efx_ptp_ts_init(struct efx_nic *efx, struct kernel_hwtstamp_config *init)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='hunk'>@@ -1895,33 +1895,25 @@ void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info)</div><div class='ctx'> 	ts_info-&gt;rx_filters = ptp-&gt;efx-&gt;type-&gt;hwtstamp_filters;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr)</div><div class='add'>+int efx_ptp_set_ts_config(struct efx_nic *efx,</div><div class='add'>+			  struct kernel_hwtstamp_config *config,</div><div class='add'>+			  struct netlink_ext_ack __always_unused *extack)</div><div class='ctx'> {</div><div class='del'>-	struct hwtstamp_config config;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='ctx'> 	/* Not a PTP enabled port */</div><div class='ctx'> 	if (!efx-&gt;ptp_data)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;config, ifr-&gt;ifr_data, sizeof(config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	rc = efx_ptp_ts_init(efx, &amp;config);</div><div class='del'>-	if (rc != 0)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;config, sizeof(config))</div><div class='del'>-		? -EFAULT : 0;</div><div class='add'>+	return efx_ptp_ts_init(efx, config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr)</div><div class='add'>+int efx_ptp_get_ts_config(struct efx_nic *efx,</div><div class='add'>+			  struct kernel_hwtstamp_config *config)</div><div class='ctx'> {</div><div class='add'>+	/* Not a PTP enabled port */</div><div class='ctx'> 	if (!efx-&gt;ptp_data)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;efx-&gt;ptp_data-&gt;config,</div><div class='del'>-			    sizeof(efx-&gt;ptp_data-&gt;config)) ? -EFAULT : 0;</div><div class='add'>+	*config = efx-&gt;ptp_data-&gt;config;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ptp_event_failure(struct efx_nic *efx, int expected_frag_len)</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/ptp.h b/drivers/net/ethernet/sfc/ptp.h<br/>index 7b1ef7002b3f..2f30dbb490d2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/ptp.h</a></div><div class='hunk'>@@ -18,8 +18,11 @@ void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);</div><div class='ctx'> struct efx_channel *efx_ptp_channel(struct efx_nic *efx);</div><div class='ctx'> void efx_ptp_update_channel(struct efx_nic *efx, struct efx_channel *channel);</div><div class='ctx'> void efx_ptp_remove(struct efx_nic *efx);</div><div class='del'>-int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);</div><div class='del'>-int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);</div><div class='add'>+int efx_ptp_set_ts_config(struct efx_nic *efx,</div><div class='add'>+			  struct kernel_hwtstamp_config *config,</div><div class='add'>+			  struct netlink_ext_ack *extack);</div><div class='add'>+int efx_ptp_get_ts_config(struct efx_nic *efx,</div><div class='add'>+			  struct kernel_hwtstamp_config *config);</div><div class='ctx'> void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);</div><div class='ctx'> bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);</div><div class='ctx'> int efx_ptp_get_mode(struct efx_nic *efx);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/rx_common.c b/drivers/net/ethernet/sfc/rx_common.c<br/>index d2f35ee15eff..fac227d372db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/rx_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/rx_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/rx_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/rx_common.c</a></div><div class='hunk'>@@ -823,8 +823,10 @@ int efx_probe_filters(struct efx_nic *efx)</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (!success) {</div><div class='del'>-			efx_for_each_channel(channel, efx)</div><div class='add'>+			efx_for_each_channel(channel, efx) {</div><div class='ctx'> 				kfree(channel-&gt;rps_flow_id);</div><div class='add'>+				channel-&gt;rps_flow_id = NULL;</div><div class='add'>+			}</div><div class='ctx'> 			efx-&gt;type-&gt;filter_table_remove(efx);</div><div class='ctx'> 			rc = -ENOMEM;</div><div class='ctx'> 			goto out_unlock;</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/efx.c b/drivers/net/ethernet/sfc/siena/efx.c<br/>index 8c557f6a183c..59d3a6043379 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/efx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/efx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/efx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/efx.c</a></div><div class='hunk'>@@ -495,11 +495,6 @@ static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)</div><div class='ctx'> 	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='ctx'> 	struct mii_ioctl_data *data = if_mii(ifr);</div><div class='ctx'> </div><div class='del'>-	if (cmd == SIOCSHWTSTAMP)</div><div class='del'>-		return efx_siena_ptp_set_ts_config(efx, ifr);</div><div class='del'>-	if (cmd == SIOCGHWTSTAMP)</div><div class='del'>-		return efx_siena_ptp_get_ts_config(efx, ifr);</div><div class='del'>-</div><div class='ctx'> 	/* Convert phy_id from older PRTAD/DEVAD format */</div><div class='ctx'> 	if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &amp;&amp;</div><div class='ctx'> 	    (data-&gt;phy_id &amp; 0xfc00) == 0x0400)</div><div class='hunk'>@@ -579,6 +574,23 @@ static int efx_vlan_rx_kill_vid(struct net_device *net_dev, __be16 proto, u16 vi</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int efx_siena_hwtstamp_set(struct net_device *net_dev,</div><div class='add'>+				  struct kernel_hwtstamp_config *config,</div><div class='add'>+				  struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='add'>+</div><div class='add'>+	return efx_siena_ptp_set_ts_config(efx, config, extack);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int efx_siena_hwtstamp_get(struct net_device *net_dev,</div><div class='add'>+				  struct kernel_hwtstamp_config *config)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='add'>+</div><div class='add'>+	return efx_siena_ptp_get_ts_config(efx, config);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops efx_netdev_ops = {</div><div class='ctx'> 	.ndo_open		= efx_net_open,</div><div class='ctx'> 	.ndo_stop		= efx_net_stop,</div><div class='hunk'>@@ -594,6 +606,8 @@ static const struct net_device_ops efx_netdev_ops = {</div><div class='ctx'> 	.ndo_features_check	= efx_siena_features_check,</div><div class='ctx'> 	.ndo_vlan_rx_add_vid	= efx_vlan_rx_add_vid,</div><div class='ctx'> 	.ndo_vlan_rx_kill_vid	= efx_vlan_rx_kill_vid,</div><div class='add'>+	.ndo_hwtstamp_set	= efx_siena_hwtstamp_set,</div><div class='add'>+	.ndo_hwtstamp_get	= efx_siena_hwtstamp_get,</div><div class='ctx'> #ifdef CONFIG_SFC_SIENA_SRIOV</div><div class='ctx'> 	.ndo_set_vf_mac		= efx_sriov_set_vf_mac,</div><div class='ctx'> 	.ndo_set_vf_vlan	= efx_sriov_set_vf_vlan,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/ethtool.c b/drivers/net/ethernet/sfc/siena/ethtool.c<br/>index e4ec589216c1..14dd3893bdef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool.c</a></div><div class='hunk'>@@ -240,6 +240,7 @@ static int efx_ethtool_get_ts_info(struct net_device *net_dev,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct ethtool_ops efx_siena_ethtool_ops = {</div><div class='add'>+	.cap_rss_ctx_supported	= true,</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USECS_IRQ |</div><div class='ctx'> 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX,</div><div class='hunk'>@@ -269,8 +270,6 @@ const struct ethtool_ops efx_siena_ethtool_ops = {</div><div class='ctx'> 	.get_rxfh_key_size	= efx_siena_ethtool_get_rxfh_key_size,</div><div class='ctx'> 	.get_rxfh		= efx_siena_ethtool_get_rxfh,</div><div class='ctx'> 	.set_rxfh		= efx_siena_ethtool_set_rxfh,</div><div class='del'>-	.get_rxfh_context	= efx_siena_ethtool_get_rxfh_context,</div><div class='del'>-	.set_rxfh_context	= efx_siena_ethtool_set_rxfh_context,</div><div class='ctx'> 	.get_ts_info		= efx_ethtool_get_ts_info,</div><div class='ctx'> 	.get_module_info	= efx_siena_ethtool_get_module_info,</div><div class='ctx'> 	.get_module_eeprom	= efx_siena_ethtool_get_module_eeprom,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/ethtool_common.c b/drivers/net/ethernet/sfc/siena/ethtool_common.c<br/>index f590e87e5a23..5f0a8127e967 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool_common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/ethtool_common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool_common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool_common.c</a></div><div class='hunk'>@@ -1164,48 +1164,8 @@ u32 efx_siena_ethtool_get_rxfh_key_size(struct net_device *net_dev)</div><div class='ctx'> 	return efx-&gt;type-&gt;rx_hash_key_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_siena_ethtool_get_rxfh(struct net_device *net_dev, u32 *indir, u8 *key,</div><div class='del'>-			       u8 *hfunc)</div><div class='del'>-{</div><div class='del'>-	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	rc = efx-&gt;type-&gt;rx_pull_rss_config(efx);</div><div class='del'>-	if (rc)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, efx-&gt;rss_context.rx_indir_table,</div><div class='del'>-		       sizeof(efx-&gt;rss_context.rx_indir_table));</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, efx-&gt;rss_context.rx_hash_key,</div><div class='del'>-		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int efx_siena_ethtool_set_rxfh(struct net_device *net_dev, const u32 *indir,</div><div class='del'>-			       const u8 *key, const u8 hfunc)</div><div class='del'>-{</div><div class='del'>-	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='del'>-</div><div class='del'>-	/* Hash function is Toeplitz, cannot be changed */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	if (!indir &amp;&amp; !key)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (!key)</div><div class='del'>-		key = efx-&gt;rss_context.rx_hash_key;</div><div class='del'>-	if (!indir)</div><div class='del'>-		indir = efx-&gt;rss_context.rx_indir_table;</div><div class='del'>-</div><div class='del'>-	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, indir, key);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int efx_siena_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='del'>-				       u8 *key, u8 *hfunc, u32 rss_context)</div><div class='add'>+static int efx_siena_ethtool_get_rxfh_context(struct net_device *net_dev,</div><div class='add'>+					      struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='ctx'> 	struct efx_rss_context *ctx;</div><div class='hunk'>@@ -1215,7 +1175,7 @@ int efx_siena_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;efx-&gt;rss_lock);</div><div class='del'>-	ctx = efx_siena_find_rss_context_entry(efx, rss_context);</div><div class='add'>+	ctx = efx_siena_find_rss_context_entry(efx, rxfh-&gt;rss_context);</div><div class='ctx'> 	if (!ctx) {</div><div class='ctx'> 		rc = -ENOENT;</div><div class='ctx'> 		goto out_unlock;</div><div class='hunk'>@@ -1224,37 +1184,60 @@ int efx_siena_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		goto out_unlock;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (indir)</div><div class='del'>-		memcpy(indir, ctx-&gt;rx_indir_table, sizeof(ctx-&gt;rx_indir_table));</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, ctx-&gt;rx_hash_key, efx-&gt;type-&gt;rx_hash_key_size);</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, ctx-&gt;rx_indir_table,</div><div class='add'>+		       sizeof(ctx-&gt;rx_indir_table));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, ctx-&gt;rx_hash_key,</div><div class='add'>+		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='ctx'> out_unlock:</div><div class='ctx'> 	mutex_unlock(&amp;efx-&gt;rss_lock);</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_siena_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='del'>-				       const u32 *indir, const u8 *key,</div><div class='del'>-				       const u8 hfunc, u32 *rss_context,</div><div class='del'>-				       bool delete)</div><div class='add'>+int efx_siena_ethtool_get_rxfh(struct net_device *net_dev,</div><div class='add'>+			       struct ethtool_rxfh_param *rxfh)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='add'>+	int rc;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		return efx_siena_ethtool_get_rxfh_context(net_dev, rxfh);</div><div class='add'>+</div><div class='add'>+	rc = efx-&gt;type-&gt;rx_pull_rss_config(efx);</div><div class='add'>+	if (rc)</div><div class='add'>+		return rc;</div><div class='add'>+</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;indir)</div><div class='add'>+		memcpy(rxfh-&gt;indir, efx-&gt;rss_context.rx_indir_table,</div><div class='add'>+		       sizeof(efx-&gt;rss_context.rx_indir_table));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, efx-&gt;rss_context.rx_hash_key,</div><div class='add'>+		       efx-&gt;type-&gt;rx_hash_key_size);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int efx_siena_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='add'>+					      struct ethtool_rxfh_param *rxfh,</div><div class='add'>+					      struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='add'>+	u32 *rss_context = &amp;rxfh-&gt;rss_context;</div><div class='ctx'> 	struct efx_rss_context *ctx;</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='ctx'> 	bool allocated = false;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='ctx'> 	if (!efx-&gt;type-&gt;rx_push_rss_context_config)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	/* Hash function is Toeplitz, cannot be changed */</div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;efx-&gt;rss_lock);</div><div class='ctx'> </div><div class='ctx'> 	if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {</div><div class='del'>-		if (delete) {</div><div class='add'>+		if (rxfh-&gt;rss_delete) {</div><div class='ctx'> 			/* alloc + delete == Nothing to do */</div><div class='ctx'> 			rc = -EINVAL;</div><div class='ctx'> 			goto out_unlock;</div><div class='hunk'>@@ -1277,7 +1260,7 @@ int efx_siena_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (delete) {</div><div class='add'>+	if (rxfh-&gt;rss_delete) {</div><div class='ctx'> 		/* delete this context */</div><div class='ctx'> 		rc = efx-&gt;type-&gt;rx_push_rss_context_config(efx, ctx, NULL, NULL);</div><div class='ctx'> 		if (!rc)</div><div class='hunk'>@@ -1300,6 +1283,33 @@ out_unlock:</div><div class='ctx'> 	return rc;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+int efx_siena_ethtool_set_rxfh(struct net_device *net_dev,</div><div class='add'>+			       struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			       struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='add'>+	u32 *indir = rxfh-&gt;indir;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='add'>+</div><div class='add'>+	/* Hash function is Toeplitz, cannot be changed */</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (rxfh-&gt;rss_context)</div><div class='add'>+		efx_siena_ethtool_set_rxfh_context(net_dev, rxfh, extack);</div><div class='add'>+</div><div class='add'>+	if (!indir &amp;&amp; !key)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!key)</div><div class='add'>+		key = efx-&gt;rss_context.rx_hash_key;</div><div class='add'>+	if (!indir)</div><div class='add'>+		indir = efx-&gt;rss_context.rx_indir_table;</div><div class='add'>+</div><div class='add'>+	return efx-&gt;type-&gt;rx_push_rss_config(efx, true, indir, key);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int efx_siena_ethtool_reset(struct net_device *net_dev, u32 *flags)</div><div class='ctx'> {</div><div class='ctx'> 	struct efx_nic *efx = netdev_priv(net_dev);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/ethtool_common.h b/drivers/net/ethernet/sfc/siena/ethtool_common.h<br/>index 04b375dc6800..d674bab0f65b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool_common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/ethtool_common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ethtool_common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ethtool_common.h</a></div><div class='hunk'>@@ -41,16 +41,11 @@ int efx_siena_ethtool_set_rxnfc(struct net_device *net_dev,</div><div class='ctx'> 				struct ethtool_rxnfc *info);</div><div class='ctx'> u32 efx_siena_ethtool_get_rxfh_indir_size(struct net_device *net_dev);</div><div class='ctx'> u32 efx_siena_ethtool_get_rxfh_key_size(struct net_device *net_dev);</div><div class='del'>-int efx_siena_ethtool_get_rxfh(struct net_device *net_dev, u32 *indir, u8 *key,</div><div class='del'>-			       u8 *hfunc);</div><div class='add'>+int efx_siena_ethtool_get_rxfh(struct net_device *net_dev,</div><div class='add'>+			       struct ethtool_rxfh_param *rxfh);</div><div class='ctx'> int efx_siena_ethtool_set_rxfh(struct net_device *net_dev,</div><div class='del'>-			       const u32 *indir, const u8 *key, const u8 hfunc);</div><div class='del'>-int efx_siena_ethtool_get_rxfh_context(struct net_device *net_dev, u32 *indir,</div><div class='del'>-				       u8 *key, u8 *hfunc, u32 rss_context);</div><div class='del'>-int efx_siena_ethtool_set_rxfh_context(struct net_device *net_dev,</div><div class='del'>-				       const u32 *indir, const u8 *key,</div><div class='del'>-				       const u8 hfunc, u32 *rss_context,</div><div class='del'>-				       bool delete);</div><div class='add'>+			       struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			       struct netlink_ext_ack *extack);</div><div class='ctx'> int efx_siena_ethtool_reset(struct net_device *net_dev, u32 *flags);</div><div class='ctx'> int efx_siena_ethtool_get_module_eeprom(struct net_device *net_dev,</div><div class='ctx'> 					struct ethtool_eeprom *ee,</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/net_driver.h b/drivers/net/ethernet/sfc/siena/net_driver.h<br/>index ff7bbc325952..94152f595acd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/net_driver.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/net_driver.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/net_driver.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/net_driver.h</a></div><div class='hunk'>@@ -1424,7 +1424,7 @@ struct efx_nic_type {</div><div class='ctx'> 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);</div><div class='ctx'> 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);</div><div class='ctx'> 	int (*ptp_set_ts_config)(struct efx_nic *efx,</div><div class='del'>-				 struct hwtstamp_config *init);</div><div class='add'>+				 struct kernel_hwtstamp_config *init);</div><div class='ctx'> 	int (*sriov_configure)(struct efx_nic *efx, int num_vfs);</div><div class='ctx'> 	int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);</div><div class='ctx'> 	int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/ptp.c b/drivers/net/ethernet/sfc/siena/ptp.c<br/>index 38e666561bcd..4b5e2f0ba350 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ptp.c</a></div><div class='hunk'>@@ -297,7 +297,7 @@ struct efx_ptp_data {</div><div class='ctx'> 	u32 rxfilter_event;</div><div class='ctx'> 	u32 rxfilter_general;</div><div class='ctx'> 	bool rxfilter_installed;</div><div class='del'>-	struct hwtstamp_config config;</div><div class='add'>+	struct kernel_hwtstamp_config config;</div><div class='ctx'> 	bool enabled;</div><div class='ctx'> 	unsigned int mode;</div><div class='ctx'> 	void (*ns_to_nic_time)(s64 ns, u32 *nic_major, u32 *nic_minor);</div><div class='hunk'>@@ -1762,7 +1762,8 @@ int efx_siena_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int efx_ptp_ts_init(struct efx_nic *efx, struct hwtstamp_config *init)</div><div class='add'>+static int efx_ptp_ts_init(struct efx_nic *efx,</div><div class='add'>+			   struct kernel_hwtstamp_config *init)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='hunk'>@@ -1799,33 +1800,26 @@ void efx_siena_ptp_get_ts_info(struct efx_nic *efx,</div><div class='ctx'> 	ts_info-&gt;rx_filters = ptp-&gt;efx-&gt;type-&gt;hwtstamp_filters;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_siena_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr)</div><div class='add'>+int efx_siena_ptp_set_ts_config(struct efx_nic *efx,</div><div class='add'>+				struct kernel_hwtstamp_config *config,</div><div class='add'>+				struct netlink_ext_ack __always_unused *extack)</div><div class='ctx'> {</div><div class='del'>-	struct hwtstamp_config config;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='ctx'> 	/* Not a PTP enabled port */</div><div class='ctx'> 	if (!efx-&gt;ptp_data)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;config, ifr-&gt;ifr_data, sizeof(config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	rc = efx_ptp_ts_init(efx, &amp;config);</div><div class='del'>-	if (rc != 0)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;config, sizeof(config))</div><div class='del'>-		? -EFAULT : 0;</div><div class='add'>+	return efx_ptp_ts_init(efx, config);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int efx_siena_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr)</div><div class='add'>+int efx_siena_ptp_get_ts_config(struct efx_nic *efx,</div><div class='add'>+				struct kernel_hwtstamp_config *config)</div><div class='ctx'> {</div><div class='add'>+	/* Not a PTP enabled port */</div><div class='ctx'> 	if (!efx-&gt;ptp_data)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;efx-&gt;ptp_data-&gt;config,</div><div class='del'>-			    sizeof(efx-&gt;ptp_data-&gt;config)) ? -EFAULT : 0;</div><div class='add'>+	*config = efx-&gt;ptp_data-&gt;config;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ptp_event_failure(struct efx_nic *efx, int expected_frag_len)</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/ptp.h b/drivers/net/ethernet/sfc/siena/ptp.h<br/>index 4172f90e9f6f..6352f84424f6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ptp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/ptp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/ptp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/ptp.h</a></div><div class='hunk'>@@ -15,8 +15,11 @@</div><div class='ctx'> struct ethtool_ts_info;</div><div class='ctx'> void efx_siena_ptp_defer_probe_with_channel(struct efx_nic *efx);</div><div class='ctx'> struct efx_channel *efx_siena_ptp_channel(struct efx_nic *efx);</div><div class='del'>-int efx_siena_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);</div><div class='del'>-int efx_siena_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);</div><div class='add'>+int efx_siena_ptp_set_ts_config(struct efx_nic *efx,</div><div class='add'>+				struct kernel_hwtstamp_config *config,</div><div class='add'>+				struct netlink_ext_ack *extack);</div><div class='add'>+int efx_siena_ptp_get_ts_config(struct efx_nic *efx,</div><div class='add'>+				struct kernel_hwtstamp_config *config);</div><div class='ctx'> void efx_siena_ptp_get_ts_info(struct efx_nic *efx,</div><div class='ctx'> 			       struct ethtool_ts_info *ts_info);</div><div class='ctx'> bool efx_siena_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);</div><div class='head'>diff --git a/drivers/net/ethernet/sfc/siena/siena.c b/drivers/net/ethernet/sfc/siena/siena.c<br/>index a44c8fa25748..ca33dc08e555 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/siena.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/sfc/siena/siena.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/sfc/siena/siena.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/sfc/siena/siena.c</a></div><div class='hunk'>@@ -136,7 +136,7 @@ static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int siena_ptp_set_ts_config(struct efx_nic *efx,</div><div class='del'>-				   struct hwtstamp_config *init)</div><div class='add'>+				   struct kernel_hwtstamp_config *init)</div><div class='ctx'> {</div><div class='ctx'> 	int rc;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c<br/>index 0891e9e49ecb..5ab8b81b84e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/socionext/netsec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/socionext/netsec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/socionext/netsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/socionext/netsec.c</a></div><div class='hunk'>@@ -1302,6 +1302,8 @@ static int netsec_setup_rx_dring(struct netsec_priv *priv)</div><div class='ctx'> 		.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,</div><div class='ctx'> 		.offset = NETSEC_RXBUF_HEADROOM,</div><div class='ctx'> 		.max_len = NETSEC_RX_BUF_SIZE,</div><div class='add'>+		.napi = &amp;priv-&gt;napi,</div><div class='add'>+		.netdev = priv-&gt;ndev,</div><div class='ctx'> 	};</div><div class='ctx'> 	int i, err;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile<br/>index 80e598bd4255..26cad4344701 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/Makefile</a></div><div class='hunk'>@@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\</div><div class='ctx'> 	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\</div><div class='ctx'> 	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \</div><div class='ctx'> 	      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \</div><div class='del'>-	      stmmac_xdp.o \</div><div class='add'>+	      stmmac_xdp.o stmmac_est.o \</div><div class='ctx'> 	      $(stmmac-y)</div><div class='ctx'> </div><div class='ctx'> stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h<br/>index e3f650e88f82..721c1f8e892f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/common.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/common.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/common.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/common.h</a></div><div class='hunk'>@@ -563,6 +563,7 @@ struct mac_device_info {</div><div class='ctx'> 	const struct stmmac_hwtimestamp *ptp;</div><div class='ctx'> 	const struct stmmac_tc_ops *tc;</div><div class='ctx'> 	const struct stmmac_mmc_ops *mmc;</div><div class='add'>+	const struct stmmac_est_ops *est;</div><div class='ctx'> 	struct dw_xpcs *xpcs;</div><div class='ctx'> 	struct phylink_pcs *lynx_pcs; /* Lynx external PCS */</div><div class='ctx'> 	struct mii_regs mii;	/* MII register Addresses */</div><div class='hunk'>@@ -580,6 +581,7 @@ struct mac_device_info {</div><div class='ctx'> 	u32 vlan_filter[32];</div><div class='ctx'> 	bool vlan_fail_q_en;</div><div class='ctx'> 	u8 vlan_fail_q;</div><div class='add'>+	bool hw_vlan_en;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct stmmac_rx_routing {</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c<br/>index 2cd6fce5c993..9e40c28d453a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c</a></div><div class='hunk'>@@ -59,26 +59,19 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!of_device_is_compatible(np, "loongson, pci-gmac")) {</div><div class='del'>-		pr_info("dwmac_loongson_pci: Incompatible OF node\n");</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	plat = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*plat), GFP_KERNEL);</div><div class='ctx'> 	if (!plat)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	plat-&gt;mdio_bus_data = devm_kzalloc(&amp;pdev-&gt;dev,</div><div class='add'>+					   sizeof(*plat-&gt;mdio_bus_data),</div><div class='add'>+					   GFP_KERNEL);</div><div class='add'>+	if (!plat-&gt;mdio_bus_data)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='ctx'> 	plat-&gt;mdio_node = of_get_child_by_name(np, "mdio");</div><div class='ctx'> 	if (plat-&gt;mdio_node) {</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "Found MDIO subnode\n");</div><div class='del'>-</div><div class='del'>-		plat-&gt;mdio_bus_data = devm_kzalloc(&amp;pdev-&gt;dev,</div><div class='del'>-						   sizeof(*plat-&gt;mdio_bus_data),</div><div class='del'>-						   GFP_KERNEL);</div><div class='del'>-		if (!plat-&gt;mdio_bus_data) {</div><div class='del'>-			ret = -ENOMEM;</div><div class='del'>-			goto err_put_node;</div><div class='del'>-		}</div><div class='ctx'> 		plat-&gt;mdio_bus_data-&gt;needs_reset = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c<br/>index d3bf42d0fceb..31631e3f89d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c</a></div><div class='hunk'>@@ -34,6 +34,7 @@</div><div class='ctx'> #define RGMII_CONFIG_LOOPBACK_EN		BIT(2)</div><div class='ctx'> #define RGMII_CONFIG_PROG_SWAP			BIT(1)</div><div class='ctx'> #define RGMII_CONFIG_DDR_MODE			BIT(0)</div><div class='add'>+#define RGMII_CONFIG_SGMII_CLK_DVDR		GENMASK(18, 10)</div><div class='ctx'> </div><div class='ctx'> /* SDCC_HC_REG_DLL_CONFIG fields */</div><div class='ctx'> #define SDCC_DLL_CONFIG_DLL_RST			BIT(30)</div><div class='hunk'>@@ -78,6 +79,8 @@</div><div class='ctx'> #define ETHQOS_MAC_CTRL_SPEED_MODE		BIT(14)</div><div class='ctx'> #define ETHQOS_MAC_CTRL_PORT_SEL		BIT(15)</div><div class='ctx'> </div><div class='add'>+#define SGMII_10M_RX_CLK_DVDR			0x31</div><div class='add'>+</div><div class='ctx'> struct ethqos_emac_por {</div><div class='ctx'> 	unsigned int offset;</div><div class='ctx'> 	unsigned int value;</div><div class='hunk'>@@ -598,6 +601,9 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* On interface toggle MAC registers gets reset.</div><div class='add'>+ * Configure MAC block for SGMII on ethernet phy link up</div><div class='add'>+ */</div><div class='ctx'> static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)</div><div class='ctx'> {</div><div class='ctx'> 	int val;</div><div class='hunk'>@@ -617,6 +623,10 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)</div><div class='ctx'> 	case SPEED_10:</div><div class='ctx'> 		val |= ETHQOS_MAC_CTRL_PORT_SEL;</div><div class='ctx'> 		val &amp;= ~ETHQOS_MAC_CTRL_SPEED_MODE;</div><div class='add'>+		rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,</div><div class='add'>+			      FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,</div><div class='add'>+					 SGMII_10M_RX_CLK_DVDR),</div><div class='add'>+			      RGMII_IO_MACRO_CONFIG);</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c<br/>index c6ff1fa0e04d..6b6d0de09619 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c</a></div><div class='hunk'>@@ -1134,6 +1134,35 @@ static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void dwmac4_rx_hw_vlan(struct mac_device_info *hw,</div><div class='add'>+			      struct dma_desc *rx_desc, struct sk_buff *skb)</div><div class='add'>+{</div><div class='add'>+	if (hw-&gt;desc-&gt;get_rx_vlan_valid(rx_desc)) {</div><div class='add'>+		u16 vid = hw-&gt;desc-&gt;get_rx_vlan_tci(rx_desc);</div><div class='add'>+</div><div class='add'>+		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void dwmac4_set_hw_vlan_mode(struct mac_device_info *hw)</div><div class='add'>+{</div><div class='add'>+	void __iomem *ioaddr = hw-&gt;pcsr;</div><div class='add'>+	u32 value = readl(ioaddr + GMAC_VLAN_TAG);</div><div class='add'>+</div><div class='add'>+	value &amp;= ~GMAC_VLAN_TAG_CTRL_EVLS_MASK;</div><div class='add'>+</div><div class='add'>+	if (hw-&gt;hw_vlan_en)</div><div class='add'>+		/* Always strip VLAN on Receive */</div><div class='add'>+		value |= GMAC_VLAN_TAG_STRIP_ALL;</div><div class='add'>+	else</div><div class='add'>+		/* Do not strip VLAN on Receive */</div><div class='add'>+		value |= GMAC_VLAN_TAG_STRIP_NONE;</div><div class='add'>+</div><div class='add'>+	/* Enable outer VLAN Tag in Rx DMA descriptor */</div><div class='add'>+	value |= GMAC_VLAN_TAG_CTRL_EVLRXS;</div><div class='add'>+	writel(value, ioaddr + GMAC_VLAN_TAG);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct stmmac_ops dwmac4_ops = {</div><div class='ctx'> 	.core_init = dwmac4_core_init,</div><div class='ctx'> 	.phylink_get_caps = dwmac4_phylink_get_caps,</div><div class='hunk'>@@ -1175,6 +1204,8 @@ const struct stmmac_ops dwmac4_ops = {</div><div class='ctx'> 	.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,</div><div class='ctx'> 	.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,</div><div class='ctx'> 	.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,</div><div class='add'>+	.rx_hw_vlan = dwmac4_rx_hw_vlan,</div><div class='add'>+	.set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct stmmac_ops dwmac410_ops = {</div><div class='hunk'>@@ -1216,14 +1247,14 @@ const struct stmmac_ops dwmac410_ops = {</div><div class='ctx'> 	.set_arp_offload = dwmac4_set_arp_offload,</div><div class='ctx'> 	.config_l3_filter = dwmac4_config_l3_filter,</div><div class='ctx'> 	.config_l4_filter = dwmac4_config_l4_filter,</div><div class='del'>-	.est_configure = dwmac5_est_configure,</div><div class='del'>-	.est_irq_status = dwmac5_est_irq_status,</div><div class='ctx'> 	.fpe_configure = dwmac5_fpe_configure,</div><div class='ctx'> 	.fpe_send_mpacket = dwmac5_fpe_send_mpacket,</div><div class='ctx'> 	.fpe_irq_status = dwmac5_fpe_irq_status,</div><div class='ctx'> 	.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,</div><div class='ctx'> 	.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,</div><div class='ctx'> 	.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,</div><div class='add'>+	.rx_hw_vlan = dwmac4_rx_hw_vlan,</div><div class='add'>+	.set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> const struct stmmac_ops dwmac510_ops = {</div><div class='hunk'>@@ -1269,14 +1300,14 @@ const struct stmmac_ops dwmac510_ops = {</div><div class='ctx'> 	.set_arp_offload = dwmac4_set_arp_offload,</div><div class='ctx'> 	.config_l3_filter = dwmac4_config_l3_filter,</div><div class='ctx'> 	.config_l4_filter = dwmac4_config_l4_filter,</div><div class='del'>-	.est_configure = dwmac5_est_configure,</div><div class='del'>-	.est_irq_status = dwmac5_est_irq_status,</div><div class='ctx'> 	.fpe_configure = dwmac5_fpe_configure,</div><div class='ctx'> 	.fpe_send_mpacket = dwmac5_fpe_send_mpacket,</div><div class='ctx'> 	.fpe_irq_status = dwmac5_fpe_irq_status,</div><div class='ctx'> 	.add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,</div><div class='ctx'> 	.del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,</div><div class='ctx'> 	.restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,</div><div class='add'>+	.rx_hw_vlan = dwmac4_rx_hw_vlan,</div><div class='add'>+	.set_hw_vlan_mode = dwmac4_set_hw_vlan_mode,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c<br/>index 89a14084c611..1c5802e0d7f4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c</a></div><div class='hunk'>@@ -198,6 +198,17 @@ static int dwmac4_get_tx_ls(struct dma_desc *p)</div><div class='ctx'> 		&gt;&gt; TDES3_LAST_DESCRIPTOR_SHIFT;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)</div><div class='add'>+{</div><div class='add'>+	return (le32_to_cpu(p-&gt;des0) &amp; RDES0_VLAN_TAG_MASK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)</div><div class='add'>+{</div><div class='add'>+	return ((le32_to_cpu(p-&gt;des3) &amp; RDES3_LAST_DESCRIPTOR) &amp;&amp;</div><div class='add'>+		(le32_to_cpu(p-&gt;des3) &amp; RDES3_RDES0_VALID));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)</div><div class='ctx'> {</div><div class='ctx'> 	return (le32_to_cpu(p-&gt;des3) &amp; RDES3_PACKET_SIZE_MASK);</div><div class='hunk'>@@ -551,6 +562,8 @@ const struct stmmac_desc_ops dwmac4_desc_ops = {</div><div class='ctx'> 	.set_tx_owner = dwmac4_set_tx_owner,</div><div class='ctx'> 	.set_rx_owner = dwmac4_set_rx_owner,</div><div class='ctx'> 	.get_tx_ls = dwmac4_get_tx_ls,</div><div class='add'>+	.get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,</div><div class='add'>+	.get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,</div><div class='ctx'> 	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,</div><div class='ctx'> 	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,</div><div class='ctx'> 	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c<br/>index e95d35f1e5a0..e02cebc3f1b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac5.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac5.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac5.c</a></div><div class='hunk'>@@ -573,165 +573,22 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)</div><div class='del'>-{</div><div class='del'>-	u32 ctrl;</div><div class='del'>-</div><div class='del'>-	writel(val, ioaddr + MTL_EST_GCL_DATA);</div><div class='del'>-</div><div class='del'>-	ctrl = (reg &lt;&lt; ADDR_SHIFT);</div><div class='del'>-	ctrl |= gcl ? 0 : GCRR;</div><div class='del'>-</div><div class='del'>-	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);</div><div class='del'>-</div><div class='del'>-	ctrl |= SRWO;</div><div class='del'>-	writel(ctrl, ioaddr + MTL_EST_GCL_CONTROL);</div><div class='del'>-</div><div class='del'>-	return readl_poll_timeout(ioaddr + MTL_EST_GCL_CONTROL,</div><div class='del'>-				  ctrl, !(ctrl &amp; SRWO), 100, 5000);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,</div><div class='del'>-			 unsigned int ptp_rate)</div><div class='del'>-{</div><div class='del'>-	int i, ret = 0x0;</div><div class='del'>-	u32 ctrl;</div><div class='del'>-</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, BTR_LOW, cfg-&gt;btr[0], false);</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, BTR_HIGH, cfg-&gt;btr[1], false);</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, TER, cfg-&gt;ter, false);</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, LLR, cfg-&gt;gcl_size, false);</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, CTR_LOW, cfg-&gt;ctr[0], false);</div><div class='del'>-	ret |= dwmac5_est_write(ioaddr, CTR_HIGH, cfg-&gt;ctr[1], false);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; cfg-&gt;gcl_size; i++) {</div><div class='del'>-		ret = dwmac5_est_write(ioaddr, i, cfg-&gt;gcl[i], true);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ctrl = readl(ioaddr + MTL_EST_CONTROL);</div><div class='del'>-	ctrl &amp;= ~PTOV;</div><div class='del'>-	ctrl |= ((1000000000 / ptp_rate) * 6) &lt;&lt; PTOV_SHIFT;</div><div class='del'>-	if (cfg-&gt;enable)</div><div class='del'>-		ctrl |= EEST | SSWL;</div><div class='del'>-	else</div><div class='del'>-		ctrl &amp;= ~EEST;</div><div class='del'>-</div><div class='del'>-	writel(ctrl, ioaddr + MTL_EST_CONTROL);</div><div class='del'>-</div><div class='del'>-	/* Configure EST interrupt */</div><div class='del'>-	if (cfg-&gt;enable)</div><div class='del'>-		ctrl = (IECGCE | IEHS | IEHF | IEBE | IECC);</div><div class='del'>-	else</div><div class='del'>-		ctrl = 0;</div><div class='del'>-</div><div class='del'>-	writel(ctrl, ioaddr + MTL_EST_INT_EN);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,</div><div class='del'>-			  struct stmmac_extra_stats *x, u32 txqcnt)</div><div class='del'>-{</div><div class='del'>-	u32 status, value, feqn, hbfq, hbfs, btrl;</div><div class='del'>-	u32 txqcnt_mask = (1 &lt;&lt; txqcnt) - 1;</div><div class='del'>-</div><div class='del'>-	status = readl(ioaddr + MTL_EST_STATUS);</div><div class='del'>-</div><div class='del'>-	value = (CGCE | HLBS | HLBF | BTRE | SWLC);</div><div class='del'>-</div><div class='del'>-	/* Return if there is no error */</div><div class='del'>-	if (!(status &amp; value))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (status &amp; CGCE) {</div><div class='del'>-		/* Clear Interrupt */</div><div class='del'>-		writel(CGCE, ioaddr + MTL_EST_STATUS);</div><div class='del'>-</div><div class='del'>-		x-&gt;mtl_est_cgce++;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; HLBS) {</div><div class='del'>-		value = readl(ioaddr + MTL_EST_SCH_ERR);</div><div class='del'>-		value &amp;= txqcnt_mask;</div><div class='del'>-</div><div class='del'>-		x-&gt;mtl_est_hlbs++;</div><div class='del'>-</div><div class='del'>-		/* Clear Interrupt */</div><div class='del'>-		writel(value, ioaddr + MTL_EST_SCH_ERR);</div><div class='del'>-</div><div class='del'>-		/* Collecting info to shows all the queues that has HLBS</div><div class='del'>-		 * issue. The only way to clear this is to clear the</div><div class='del'>-		 * statistic</div><div class='del'>-		 */</div><div class='del'>-		if (net_ratelimit())</div><div class='del'>-			netdev_err(dev, "EST: HLB(sched) Queue 0x%x\n", value);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; HLBF) {</div><div class='del'>-		value = readl(ioaddr + MTL_EST_FRM_SZ_ERR);</div><div class='del'>-		feqn = value &amp; txqcnt_mask;</div><div class='del'>-</div><div class='del'>-		value = readl(ioaddr + MTL_EST_FRM_SZ_CAP);</div><div class='del'>-		hbfq = (value &amp; SZ_CAP_HBFQ_MASK(txqcnt)) &gt;&gt; SZ_CAP_HBFQ_SHIFT;</div><div class='del'>-		hbfs = value &amp; SZ_CAP_HBFS_MASK;</div><div class='del'>-</div><div class='del'>-		x-&gt;mtl_est_hlbf++;</div><div class='del'>-</div><div class='del'>-		/* Clear Interrupt */</div><div class='del'>-		writel(feqn, ioaddr + MTL_EST_FRM_SZ_ERR);</div><div class='del'>-</div><div class='del'>-		if (net_ratelimit())</div><div class='del'>-			netdev_err(dev, "EST: HLB(size) Queue %u Size %u\n",</div><div class='del'>-				   hbfq, hbfs);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; BTRE) {</div><div class='del'>-		if ((status &amp; BTRL) == BTRL_MAX)</div><div class='del'>-			x-&gt;mtl_est_btrlm++;</div><div class='del'>-		else</div><div class='del'>-			x-&gt;mtl_est_btre++;</div><div class='del'>-</div><div class='del'>-		btrl = (status &amp; BTRL) &gt;&gt; BTRL_SHIFT;</div><div class='del'>-</div><div class='del'>-		if (net_ratelimit())</div><div class='del'>-			netdev_info(dev, "EST: BTR Error Loop Count %u\n",</div><div class='del'>-				    btrl);</div><div class='del'>-</div><div class='del'>-		writel(BTRE, ioaddr + MTL_EST_STATUS);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status &amp; SWLC) {</div><div class='del'>-		writel(SWLC, ioaddr + MTL_EST_STATUS);</div><div class='del'>-		netdev_info(dev, "EST: SWOL has been switched\n");</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,</div><div class='add'>+void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,</div><div class='add'>+			  u32 num_txq, u32 num_rxq,</div><div class='ctx'> 			  bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 value;</div><div class='ctx'> </div><div class='del'>-	if (!enable) {</div><div class='del'>-		value = readl(ioaddr + MAC_FPE_CTRL_STS);</div><div class='del'>-</div><div class='del'>-		value &amp;= ~EFPE;</div><div class='del'>-</div><div class='del'>-		writel(value, ioaddr + MAC_FPE_CTRL_STS);</div><div class='del'>-		return;</div><div class='add'>+	if (enable) {</div><div class='add'>+		cfg-&gt;fpe_csr = EFPE;</div><div class='add'>+		value = readl(ioaddr + GMAC_RXQ_CTRL1);</div><div class='add'>+		value &amp;= ~GMAC_RXQCTRL_FPRQ;</div><div class='add'>+		value |= (num_rxq - 1) &lt;&lt; GMAC_RXQCTRL_FPRQ_SHIFT;</div><div class='add'>+		writel(value, ioaddr + GMAC_RXQ_CTRL1);</div><div class='add'>+	} else {</div><div class='add'>+		cfg-&gt;fpe_csr = 0;</div><div class='ctx'> 	}</div><div class='del'>-</div><div class='del'>-	value = readl(ioaddr + GMAC_RXQ_CTRL1);</div><div class='del'>-	value &amp;= ~GMAC_RXQCTRL_FPRQ;</div><div class='del'>-	value |= (num_rxq - 1) &lt;&lt; GMAC_RXQCTRL_FPRQ_SHIFT;</div><div class='del'>-	writel(value, ioaddr + GMAC_RXQ_CTRL1);</div><div class='del'>-</div><div class='del'>-	value = readl(ioaddr + MAC_FPE_CTRL_STS);</div><div class='del'>-	value |= EFPE;</div><div class='del'>-	writel(value, ioaddr + MAC_FPE_CTRL_STS);</div><div class='add'>+	writel(cfg-&gt;fpe_csr, ioaddr + MAC_FPE_CTRL_STS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)</div><div class='hunk'>@@ -741,6 +598,9 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)</div><div class='ctx'> </div><div class='ctx'> 	status = FPE_EVENT_UNKNOWN;</div><div class='ctx'> </div><div class='add'>+	/* Reads from the MAC_FPE_CTRL_STS register should only be performed</div><div class='add'>+	 * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read"</div><div class='add'>+	 */</div><div class='ctx'> 	value = readl(ioaddr + MAC_FPE_CTRL_STS);</div><div class='ctx'> </div><div class='ctx'> 	if (value &amp; TRSP) {</div><div class='hunk'>@@ -766,19 +626,15 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)</div><div class='ctx'> 	return status;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, enum stmmac_mpacket_type type)</div><div class='add'>+void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,</div><div class='add'>+			     enum stmmac_mpacket_type type)</div><div class='ctx'> {</div><div class='del'>-	u32 value;</div><div class='add'>+	u32 value = cfg-&gt;fpe_csr;</div><div class='ctx'> </div><div class='del'>-	value = readl(ioaddr + MAC_FPE_CTRL_STS);</div><div class='del'>-</div><div class='del'>-	if (type == MPACKET_VERIFY) {</div><div class='del'>-		value &amp;= ~SRSP;</div><div class='add'>+	if (type == MPACKET_VERIFY)</div><div class='ctx'> 		value |= SVER;</div><div class='del'>-	} else {</div><div class='del'>-		value &amp;= ~SVER;</div><div class='add'>+	else if (type == MPACKET_RESPONSE)</div><div class='ctx'> 		value |= SRSP;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	writel(value, ioaddr + MAC_FPE_CTRL_STS);</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.h b/drivers/net/ethernet/stmicro/stmmac/dwmac5.h<br/>index 53c138d0ff48..bf33a51d229e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac5.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwmac5.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwmac5.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwmac5.h</a></div><div class='hunk'>@@ -39,53 +39,6 @@</div><div class='ctx'> #define MAC_PPSx_INTERVAL(x)		(0x00000b88 + ((x) * 0x10))</div><div class='ctx'> #define MAC_PPSx_WIDTH(x)		(0x00000b8c + ((x) * 0x10))</div><div class='ctx'> </div><div class='del'>-#define MTL_EST_CONTROL			0x00000c50</div><div class='del'>-#define PTOV				GENMASK(31, 24)</div><div class='del'>-#define PTOV_SHIFT			24</div><div class='del'>-#define SSWL				BIT(1)</div><div class='del'>-#define EEST				BIT(0)</div><div class='del'>-</div><div class='del'>-#define MTL_EST_STATUS			0x00000c58</div><div class='del'>-#define BTRL				GENMASK(11, 8)</div><div class='del'>-#define BTRL_SHIFT			8</div><div class='del'>-#define BTRL_MAX			(0xF &lt;&lt; BTRL_SHIFT)</div><div class='del'>-#define SWOL				BIT(7)</div><div class='del'>-#define SWOL_SHIFT			7</div><div class='del'>-#define CGCE				BIT(4)</div><div class='del'>-#define HLBS				BIT(3)</div><div class='del'>-#define HLBF				BIT(2)</div><div class='del'>-#define BTRE				BIT(1)</div><div class='del'>-#define SWLC				BIT(0)</div><div class='del'>-</div><div class='del'>-#define MTL_EST_SCH_ERR			0x00000c60</div><div class='del'>-#define MTL_EST_FRM_SZ_ERR		0x00000c64</div><div class='del'>-#define MTL_EST_FRM_SZ_CAP		0x00000c68</div><div class='del'>-#define SZ_CAP_HBFS_MASK		GENMASK(14, 0)</div><div class='del'>-#define SZ_CAP_HBFQ_SHIFT		16</div><div class='del'>-#define SZ_CAP_HBFQ_MASK(_val)		({ typeof(_val) (val) = (_val);	\</div><div class='del'>-					((val) &gt; 4 ? GENMASK(18, 16) :	\</div><div class='del'>-					 (val) &gt; 2 ? GENMASK(17, 16) :	\</div><div class='del'>-					 BIT(16)); })</div><div class='del'>-</div><div class='del'>-#define MTL_EST_INT_EN			0x00000c70</div><div class='del'>-#define IECGCE				CGCE</div><div class='del'>-#define IEHS				HLBS</div><div class='del'>-#define IEHF				HLBF</div><div class='del'>-#define IEBE				BTRE</div><div class='del'>-#define IECC				SWLC</div><div class='del'>-</div><div class='del'>-#define MTL_EST_GCL_CONTROL		0x00000c80</div><div class='del'>-#define BTR_LOW				0x0</div><div class='del'>-#define BTR_HIGH			0x1</div><div class='del'>-#define CTR_LOW				0x2</div><div class='del'>-#define CTR_HIGH			0x3</div><div class='del'>-#define TER				0x4</div><div class='del'>-#define LLR				0x5</div><div class='del'>-#define ADDR_SHIFT			8</div><div class='del'>-#define GCRR				BIT(2)</div><div class='del'>-#define SRWO				BIT(0)</div><div class='del'>-#define MTL_EST_GCL_DATA		0x00000c84</div><div class='del'>-</div><div class='ctx'> #define MTL_RXP_CONTROL_STATUS		0x00000ca0</div><div class='ctx'> #define RXPI				BIT(31)</div><div class='ctx'> #define NPE				GENMASK(23, 16)</div><div class='hunk'>@@ -149,13 +102,11 @@ int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,</div><div class='ctx'> int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,</div><div class='ctx'> 			   struct stmmac_pps_cfg *cfg, bool enable,</div><div class='ctx'> 			   u32 sub_second_inc, u32 systime_flags);</div><div class='del'>-int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,</div><div class='del'>-			 unsigned int ptp_rate);</div><div class='del'>-void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,</div><div class='del'>-			   struct stmmac_extra_stats *x, u32 txqcnt);</div><div class='del'>-void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,</div><div class='add'>+void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,</div><div class='add'>+			  u32 num_txq, u32 num_rxq,</div><div class='ctx'> 			  bool enable);</div><div class='ctx'> void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,</div><div class='add'>+			     struct stmmac_fpe_cfg *cfg,</div><div class='ctx'> 			     enum stmmac_mpacket_type type);</div><div class='ctx'> int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h<br/>index a4e8b498dea9..207ff1799f2c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h</a></div><div class='hunk'>@@ -284,22 +284,6 @@</div><div class='ctx'> #define XGMAC_TC_PRTY_MAP1		0x00001044</div><div class='ctx'> #define XGMAC_PSTC(x)			GENMASK((x) * 8 + 7, (x) * 8)</div><div class='ctx'> #define XGMAC_PSTC_SHIFT(x)		((x) * 8)</div><div class='del'>-#define XGMAC_MTL_EST_CONTROL		0x00001050</div><div class='del'>-#define XGMAC_PTOV			GENMASK(31, 23)</div><div class='del'>-#define XGMAC_PTOV_SHIFT		23</div><div class='del'>-#define XGMAC_SSWL			BIT(1)</div><div class='del'>-#define XGMAC_EEST			BIT(0)</div><div class='del'>-#define XGMAC_MTL_EST_GCL_CONTROL	0x00001080</div><div class='del'>-#define XGMAC_BTR_LOW			0x0</div><div class='del'>-#define XGMAC_BTR_HIGH			0x1</div><div class='del'>-#define XGMAC_CTR_LOW			0x2</div><div class='del'>-#define XGMAC_CTR_HIGH			0x3</div><div class='del'>-#define XGMAC_TER			0x4</div><div class='del'>-#define XGMAC_LLR			0x5</div><div class='del'>-#define XGMAC_ADDR_SHIFT		8</div><div class='del'>-#define XGMAC_GCRR			BIT(2)</div><div class='del'>-#define XGMAC_SRWO			BIT(0)</div><div class='del'>-#define XGMAC_MTL_EST_GCL_DATA		0x00001084</div><div class='ctx'> #define XGMAC_MTL_RXP_CONTROL_STATUS	0x000010a0</div><div class='ctx'> #define XGMAC_RXPI			BIT(31)</div><div class='ctx'> #define XGMAC_NPE			GENMASK(23, 16)</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c<br/>index 453e88b75be0..eb48211d9b0e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c</a></div><div class='hunk'>@@ -1433,58 +1433,8 @@ static void dwxgmac2_set_arp_offload(struct mac_device_info *hw, bool en,</div><div class='ctx'> 	writel(value, ioaddr + XGMAC_RX_CONFIG);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)</div><div class='del'>-{</div><div class='del'>-	u32 ctrl;</div><div class='del'>-</div><div class='del'>-	writel(val, ioaddr + XGMAC_MTL_EST_GCL_DATA);</div><div class='del'>-</div><div class='del'>-	ctrl = (reg &lt;&lt; XGMAC_ADDR_SHIFT);</div><div class='del'>-	ctrl |= gcl ? 0 : XGMAC_GCRR;</div><div class='del'>-</div><div class='del'>-	writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);</div><div class='del'>-</div><div class='del'>-	ctrl |= XGMAC_SRWO;</div><div class='del'>-	writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);</div><div class='del'>-</div><div class='del'>-	return readl_poll_timeout_atomic(ioaddr + XGMAC_MTL_EST_GCL_CONTROL,</div><div class='del'>-					 ctrl, !(ctrl &amp; XGMAC_SRWO), 100, 5000);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,</div><div class='del'>-				  unsigned int ptp_rate)</div><div class='del'>-{</div><div class='del'>-	int i, ret = 0x0;</div><div class='del'>-	u32 ctrl;</div><div class='del'>-</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_LOW, cfg-&gt;btr[0], false);</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_HIGH, cfg-&gt;btr[1], false);</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_TER, cfg-&gt;ter, false);</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_LLR, cfg-&gt;gcl_size, false);</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_LOW, cfg-&gt;ctr[0], false);</div><div class='del'>-	ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_HIGH, cfg-&gt;ctr[1], false);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; cfg-&gt;gcl_size; i++) {</div><div class='del'>-		ret = dwxgmac3_est_write(ioaddr, i, cfg-&gt;gcl[i], true);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ctrl = readl(ioaddr + XGMAC_MTL_EST_CONTROL);</div><div class='del'>-	ctrl &amp;= ~XGMAC_PTOV;</div><div class='del'>-	ctrl |= ((1000000000 / ptp_rate) * 9) &lt;&lt; XGMAC_PTOV_SHIFT;</div><div class='del'>-	if (cfg-&gt;enable)</div><div class='del'>-		ctrl |= XGMAC_EEST | XGMAC_SSWL;</div><div class='del'>-	else</div><div class='del'>-		ctrl &amp;= ~XGMAC_EEST;</div><div class='del'>-</div><div class='del'>-	writel(ctrl, ioaddr + XGMAC_MTL_EST_CONTROL);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 num_txq,</div><div class='add'>+static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,</div><div class='add'>+				   u32 num_txq,</div><div class='ctx'> 				   u32 num_rxq, bool enable)</div><div class='ctx'> {</div><div class='ctx'> 	u32 value;</div><div class='hunk'>@@ -1552,7 +1502,6 @@ const struct stmmac_ops dwxgmac210_ops = {</div><div class='ctx'> 	.config_l3_filter = dwxgmac2_config_l3_filter,</div><div class='ctx'> 	.config_l4_filter = dwxgmac2_config_l4_filter,</div><div class='ctx'> 	.set_arp_offload = dwxgmac2_set_arp_offload,</div><div class='del'>-	.est_configure = dwxgmac3_est_configure,</div><div class='ctx'> 	.fpe_configure = dwxgmac3_fpe_configure,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -1614,7 +1563,6 @@ const struct stmmac_ops dwxlgmac2_ops = {</div><div class='ctx'> 	.config_l3_filter = dwxgmac2_config_l3_filter,</div><div class='ctx'> 	.config_l4_filter = dwxgmac2_config_l4_filter,</div><div class='ctx'> 	.set_arp_offload = dwxgmac2_set_arp_offload,</div><div class='del'>-	.est_configure = dwxgmac3_est_configure,</div><div class='ctx'> 	.fpe_configure = dwxgmac3_fpe_configure,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c<br/>index b8ba8f2d8041..1bd34b2a47e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/hwif.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/hwif.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/hwif.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/hwif.c</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> #include "common.h"</div><div class='ctx'> #include "stmmac.h"</div><div class='ctx'> #include "stmmac_ptp.h"</div><div class='add'>+#include "stmmac_est.h"</div><div class='ctx'> </div><div class='ctx'> static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)</div><div class='ctx'> {</div><div class='hunk'>@@ -114,6 +115,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 	const void *mode;</div><div class='ctx'> 	const void *tc;</div><div class='ctx'> 	const void *mmc;</div><div class='add'>+	const void *est;</div><div class='ctx'> 	int (*setup)(struct stmmac_priv *priv);</div><div class='ctx'> 	int (*quirks)(struct stmmac_priv *priv);</div><div class='ctx'> } stmmac_hw[] = {</div><div class='hunk'>@@ -162,6 +164,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_GMAC4_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_GMAC4_OFFSET,</div><div class='add'>+			.est_off = EST_GMAC4_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwmac4_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwmac4_dma_ops,</div><div class='hunk'>@@ -170,6 +173,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = NULL,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwmac4_setup,</div><div class='ctx'> 		.quirks = stmmac_dwmac4_quirks,</div><div class='ctx'> 	}, {</div><div class='hunk'>@@ -180,6 +184,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_GMAC4_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_GMAC4_OFFSET,</div><div class='add'>+			.est_off = EST_GMAC4_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwmac4_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwmac4_dma_ops,</div><div class='hunk'>@@ -188,6 +193,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = &amp;dwmac4_ring_mode_ops,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwmac4_setup,</div><div class='ctx'> 		.quirks = NULL,</div><div class='ctx'> 	}, {</div><div class='hunk'>@@ -198,6 +204,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_GMAC4_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_GMAC4_OFFSET,</div><div class='add'>+			.est_off = EST_GMAC4_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwmac4_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwmac410_dma_ops,</div><div class='hunk'>@@ -206,6 +213,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = &amp;dwmac4_ring_mode_ops,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwmac4_setup,</div><div class='ctx'> 		.quirks = NULL,</div><div class='ctx'> 	}, {</div><div class='hunk'>@@ -216,6 +224,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_GMAC4_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_GMAC4_OFFSET,</div><div class='add'>+			.est_off = EST_XGMAC_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwmac4_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwmac410_dma_ops,</div><div class='hunk'>@@ -224,6 +233,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = &amp;dwmac4_ring_mode_ops,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwmac4_setup,</div><div class='ctx'> 		.quirks = NULL,</div><div class='ctx'> 	}, {</div><div class='hunk'>@@ -235,6 +245,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_XGMAC_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_XGMAC_OFFSET,</div><div class='add'>+			.est_off = EST_XGMAC_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwxgmac210_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwxgmac210_dma_ops,</div><div class='hunk'>@@ -243,6 +254,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = NULL,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwxgmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwxgmac2_setup,</div><div class='ctx'> 		.quirks = NULL,</div><div class='ctx'> 	}, {</div><div class='hunk'>@@ -254,6 +266,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.regs = {</div><div class='ctx'> 			.ptp_off = PTP_XGMAC_OFFSET,</div><div class='ctx'> 			.mmc_off = MMC_XGMAC_OFFSET,</div><div class='add'>+			.est_off = EST_XGMAC_OFFSET,</div><div class='ctx'> 		},</div><div class='ctx'> 		.desc = &amp;dwxgmac210_desc_ops,</div><div class='ctx'> 		.dma = &amp;dwxgmac210_dma_ops,</div><div class='hunk'>@@ -262,6 +275,7 @@ static const struct stmmac_hwif_entry {</div><div class='ctx'> 		.mode = NULL,</div><div class='ctx'> 		.tc = &amp;dwmac510_tc_ops,</div><div class='ctx'> 		.mmc = &amp;dwxgmac_mmc_ops,</div><div class='add'>+		.est = &amp;dwmac510_est_ops,</div><div class='ctx'> 		.setup = dwxlgmac2_setup,</div><div class='ctx'> 		.quirks = stmmac_dwxlgmac_quirks,</div><div class='ctx'> 	},</div><div class='hunk'>@@ -296,6 +310,10 @@ int stmmac_hwif_init(struct stmmac_priv *priv)</div><div class='ctx'> 		(needs_gmac4 ? PTP_GMAC4_OFFSET : PTP_GMAC3_X_OFFSET);</div><div class='ctx'> 	priv-&gt;mmcaddr = priv-&gt;ioaddr +</div><div class='ctx'> 		(needs_gmac4 ? MMC_GMAC4_OFFSET : MMC_GMAC3_X_OFFSET);</div><div class='add'>+	if (needs_gmac4)</div><div class='add'>+		priv-&gt;estaddr = priv-&gt;ioaddr + EST_GMAC4_OFFSET;</div><div class='add'>+	else if (needs_xgmac)</div><div class='add'>+		priv-&gt;estaddr = priv-&gt;ioaddr + EST_XGMAC_OFFSET;</div><div class='ctx'> </div><div class='ctx'> 	/* Check for HW specific setup first */</div><div class='ctx'> 	if (priv-&gt;plat-&gt;setup) {</div><div class='hunk'>@@ -332,10 +350,13 @@ int stmmac_hwif_init(struct stmmac_priv *priv)</div><div class='ctx'> 		mac-&gt;mode = mac-&gt;mode ? : entry-&gt;mode;</div><div class='ctx'> 		mac-&gt;tc = mac-&gt;tc ? : entry-&gt;tc;</div><div class='ctx'> 		mac-&gt;mmc = mac-&gt;mmc ? : entry-&gt;mmc;</div><div class='add'>+		mac-&gt;est = mac-&gt;est ? : entry-&gt;est;</div><div class='ctx'> </div><div class='ctx'> 		priv-&gt;hw = mac;</div><div class='ctx'> 		priv-&gt;ptpaddr = priv-&gt;ioaddr + entry-&gt;regs.ptp_off;</div><div class='ctx'> 		priv-&gt;mmcaddr = priv-&gt;ioaddr + entry-&gt;regs.mmc_off;</div><div class='add'>+		if (entry-&gt;est)</div><div class='add'>+			priv-&gt;estaddr = priv-&gt;ioaddr + entry-&gt;regs.est_off;</div><div class='ctx'> </div><div class='ctx'> 		/* Entry found */</div><div class='ctx'> 		if (needs_setup) {</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h<br/>index b95d3e137813..7be04b54738b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/hwif.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/hwif.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/hwif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/hwif.h</a></div><div class='hunk'>@@ -56,6 +56,10 @@ struct stmmac_desc_ops {</div><div class='ctx'> 	void (*set_tx_ic)(struct dma_desc *p);</div><div class='ctx'> 	/* Last tx segment reports the transmit status */</div><div class='ctx'> 	int (*get_tx_ls)(struct dma_desc *p);</div><div class='add'>+	/* Get the tag of the descriptor */</div><div class='add'>+	u16 (*get_rx_vlan_tci)(struct dma_desc *p);</div><div class='add'>+	/* Get the valid status of descriptor */</div><div class='add'>+	bool (*get_rx_vlan_valid)(struct dma_desc *p);</div><div class='ctx'> 	/* Return the transmit status looking at the TDES1 */</div><div class='ctx'> 	int (*tx_status)(struct stmmac_extra_stats *x,</div><div class='ctx'> 			 struct dma_desc *p, void __iomem *ioaddr);</div><div class='hunk'>@@ -117,6 +121,10 @@ struct stmmac_desc_ops {</div><div class='ctx'> 	stmmac_do_void_callback(__priv, desc, set_tx_ic, __args)</div><div class='ctx'> #define stmmac_get_tx_ls(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_callback(__priv, desc, get_tx_ls, __args)</div><div class='add'>+#define stmmac_get_rx_vlan_tci(__priv, __args...) \</div><div class='add'>+	stmmac_do_callback(__priv, desc, get_rx_vlan_tci, __args)</div><div class='add'>+#define stmmac_get_rx_vlan_valid(__priv, __args...) \</div><div class='add'>+	stmmac_do_callback(__priv, desc, get_rx_vlan_valid, __args)</div><div class='ctx'> #define stmmac_tx_status(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_callback(__priv, desc, tx_status, __args)</div><div class='ctx'> #define stmmac_get_tx_len(__priv, __args...) \</div><div class='hunk'>@@ -388,6 +396,9 @@ struct stmmac_ops {</div><div class='ctx'> 	void (*update_vlan_hash)(struct mac_device_info *hw, u32 hash,</div><div class='ctx'> 				 __le16 perfect_match, bool is_double);</div><div class='ctx'> 	void (*enable_vlan)(struct mac_device_info *hw, u32 type);</div><div class='add'>+	void (*rx_hw_vlan)(struct mac_device_info *hw, struct dma_desc *rx_desc,</div><div class='add'>+			   struct sk_buff *skb);</div><div class='add'>+	void (*set_hw_vlan_mode)(struct mac_device_info *hw);</div><div class='ctx'> 	int (*add_hw_vlan_rx_fltr)(struct net_device *dev,</div><div class='ctx'> 				   struct mac_device_info *hw,</div><div class='ctx'> 				   __be16 proto, u16 vid);</div><div class='hunk'>@@ -408,13 +419,11 @@ struct stmmac_ops {</div><div class='ctx'> 				bool en, bool udp, bool sa, bool inv,</div><div class='ctx'> 				u32 match);</div><div class='ctx'> 	void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr);</div><div class='del'>-	int (*est_configure)(void __iomem *ioaddr, struct stmmac_est *cfg,</div><div class='del'>-			     unsigned int ptp_rate);</div><div class='del'>-	void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev,</div><div class='del'>-			       struct stmmac_extra_stats *x, u32 txqcnt);</div><div class='del'>-	void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,</div><div class='add'>+	void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,</div><div class='add'>+			      u32 num_txq, u32 num_rxq,</div><div class='ctx'> 			      bool enable);</div><div class='ctx'> 	void (*fpe_send_mpacket)(void __iomem *ioaddr,</div><div class='add'>+				 struct stmmac_fpe_cfg *cfg,</div><div class='ctx'> 				 enum stmmac_mpacket_type type);</div><div class='ctx'> 	int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev);</div><div class='ctx'> };</div><div class='hunk'>@@ -497,6 +506,10 @@ struct stmmac_ops {</div><div class='ctx'> 	stmmac_do_void_callback(__priv, mac, update_vlan_hash, __args)</div><div class='ctx'> #define stmmac_enable_vlan(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_void_callback(__priv, mac, enable_vlan, __args)</div><div class='add'>+#define stmmac_rx_hw_vlan(__priv, __args...) \</div><div class='add'>+	stmmac_do_void_callback(__priv, mac, rx_hw_vlan, __args)</div><div class='add'>+#define stmmac_set_hw_vlan_mode(__priv, __args...) \</div><div class='add'>+	stmmac_do_void_callback(__priv, mac, set_hw_vlan_mode, __args)</div><div class='ctx'> #define stmmac_add_hw_vlan_rx_fltr(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_callback(__priv, mac, add_hw_vlan_rx_fltr, __args)</div><div class='ctx'> #define stmmac_del_hw_vlan_rx_fltr(__priv, __args...) \</div><div class='hunk'>@@ -513,10 +526,6 @@ struct stmmac_ops {</div><div class='ctx'> 	stmmac_do_callback(__priv, mac, config_l4_filter, __args)</div><div class='ctx'> #define stmmac_set_arp_offload(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_void_callback(__priv, mac, set_arp_offload, __args)</div><div class='del'>-#define stmmac_est_configure(__priv, __args...) \</div><div class='del'>-	stmmac_do_callback(__priv, mac, est_configure, __args)</div><div class='del'>-#define stmmac_est_irq_status(__priv, __args...) \</div><div class='del'>-	stmmac_do_void_callback(__priv, mac, est_irq_status, __args)</div><div class='ctx'> #define stmmac_fpe_configure(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_void_callback(__priv, mac, fpe_configure, __args)</div><div class='ctx'> #define stmmac_fpe_send_mpacket(__priv, __args...) \</div><div class='hunk'>@@ -642,9 +651,22 @@ struct stmmac_mmc_ops {</div><div class='ctx'> #define stmmac_mmc_read(__priv, __args...) \</div><div class='ctx'> 	stmmac_do_void_callback(__priv, mmc, read, __args)</div><div class='ctx'> </div><div class='add'>+struct stmmac_est_ops {</div><div class='add'>+	int (*configure)(struct stmmac_priv *priv, struct stmmac_est *cfg,</div><div class='add'>+			 unsigned int ptp_rate);</div><div class='add'>+	void (*irq_status)(struct stmmac_priv *priv, struct net_device *dev,</div><div class='add'>+			   struct stmmac_extra_stats *x, u32 txqcnt);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#define stmmac_est_configure(__priv, __args...) \</div><div class='add'>+	stmmac_do_callback(__priv, est, configure, __args)</div><div class='add'>+#define stmmac_est_irq_status(__priv, __args...) \</div><div class='add'>+	stmmac_do_void_callback(__priv, est, irq_status, __args)</div><div class='add'>+</div><div class='ctx'> struct stmmac_regs_off {</div><div class='ctx'> 	u32 ptp_off;</div><div class='ctx'> 	u32 mmc_off;</div><div class='add'>+	u32 est_off;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern const struct stmmac_ops dwmac100_ops;</div><div class='hunk'>@@ -663,6 +685,7 @@ extern const struct stmmac_dma_ops dwxgmac210_dma_ops;</div><div class='ctx'> extern const struct stmmac_desc_ops dwxgmac210_desc_ops;</div><div class='ctx'> extern const struct stmmac_mmc_ops dwmac_mmc_ops;</div><div class='ctx'> extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;</div><div class='add'>+extern const struct stmmac_est_ops dwmac510_est_ops;</div><div class='ctx'> </div><div class='ctx'> #define GMAC_VERSION		0x00000020	/* GMAC CORE Version */</div><div class='ctx'> #define GMAC4_VERSION		0x00000110	/* GMAC4+ CORE Version */</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc.h b/drivers/net/ethernet/stmicro/stmmac/mmc.h<br/>index a0c05925883e..14c9d2637dfe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/mmc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/mmc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/mmc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/mmc.h</a></div><div class='hunk'>@@ -52,6 +52,8 @@ struct stmmac_counters {</div><div class='ctx'> 	unsigned int mmc_tx_excessdef;</div><div class='ctx'> 	unsigned int mmc_tx_pause_frame;</div><div class='ctx'> 	unsigned int mmc_tx_vlan_frame_g;</div><div class='add'>+	unsigned int mmc_tx_lpi_usec;</div><div class='add'>+	unsigned int mmc_tx_lpi_tran;</div><div class='ctx'> </div><div class='ctx'> 	/* MMC RX counter registers */</div><div class='ctx'> 	unsigned int mmc_rx_framecount_gb;</div><div class='hunk'>@@ -78,9 +80,16 @@ struct stmmac_counters {</div><div class='ctx'> 	unsigned int mmc_rx_fifo_overflow;</div><div class='ctx'> 	unsigned int mmc_rx_vlan_frames_gb;</div><div class='ctx'> 	unsigned int mmc_rx_watchdog_error;</div><div class='add'>+	unsigned int mmc_rx_lpi_usec;</div><div class='add'>+	unsigned int mmc_rx_lpi_tran;</div><div class='add'>+	unsigned int mmc_rx_discard_frames_gb;</div><div class='add'>+	unsigned int mmc_rx_discard_octets_gb;</div><div class='add'>+	unsigned int mmc_rx_align_err_frames;</div><div class='add'>+</div><div class='ctx'> 	/* IPC */</div><div class='ctx'> 	unsigned int mmc_rx_ipc_intr_mask;</div><div class='ctx'> 	unsigned int mmc_rx_ipc_intr;</div><div class='add'>+</div><div class='ctx'> 	/* IPv4 */</div><div class='ctx'> 	unsigned int mmc_rx_ipv4_gd;</div><div class='ctx'> 	unsigned int mmc_rx_ipv4_hderr;</div><div class='hunk'>@@ -118,9 +127,14 @@ struct stmmac_counters {</div><div class='ctx'> 	unsigned int mmc_rx_icmp_gd_octets;</div><div class='ctx'> 	unsigned int mmc_rx_icmp_err_octets;</div><div class='ctx'> </div><div class='add'>+	/* Stream-Gate Filter */</div><div class='add'>+	unsigned int mmc_sgf_pass_fragment_cntr;</div><div class='add'>+	unsigned int mmc_sgf_fail_fragment_cntr;</div><div class='add'>+</div><div class='ctx'> 	/* FPE */</div><div class='ctx'> 	unsigned int mmc_tx_fpe_fragment_cntr;</div><div class='ctx'> 	unsigned int mmc_tx_hold_req_cntr;</div><div class='add'>+	unsigned int mmc_tx_gate_overrun_cntr;</div><div class='ctx'> 	unsigned int mmc_rx_packet_assembly_err_cntr;</div><div class='ctx'> 	unsigned int mmc_rx_packet_smd_err_cntr;</div><div class='ctx'> 	unsigned int mmc_rx_packet_assembly_ok_cntr;</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c<br/>index ea4910ae0921..8597c6abae8d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/mmc_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/mmc_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/mmc_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/mmc_core.c</a></div><div class='hunk'>@@ -177,14 +177,53 @@</div><div class='ctx'> #define MMC_XGMAC_RX_DISCARD_OCT_GB	0x1b4</div><div class='ctx'> #define MMC_XGMAC_RX_ALIGN_ERR_PKT	0x1bc</div><div class='ctx'> </div><div class='add'>+#define MMC_XGMAC_SGF_PASS_PKT		0x1f0</div><div class='add'>+#define MMC_XGMAC_SGF_FAIL_PKT		0x1f4</div><div class='add'>+#define MMC_XGMAC_TX_FPE_INTR_MASK	0x204</div><div class='ctx'> #define MMC_XGMAC_TX_FPE_FRAG		0x208</div><div class='ctx'> #define MMC_XGMAC_TX_HOLD_REQ		0x20c</div><div class='add'>+#define MMC_XGMAC_TX_GATE_OVERRUN	0x210</div><div class='add'>+#define MMC_XGMAC_RX_FPE_INTR_MASK	0x224</div><div class='ctx'> #define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR	0x228</div><div class='ctx'> #define MMC_XGMAC_RX_PKT_SMD_ERR	0x22c</div><div class='ctx'> #define MMC_XGMAC_RX_PKT_ASSEMBLY_OK	0x230</div><div class='ctx'> #define MMC_XGMAC_RX_FPE_FRAG		0x234</div><div class='ctx'> #define MMC_XGMAC_RX_IPC_INTR_MASK	0x25c</div><div class='ctx'> </div><div class='add'>+#define MMC_XGMAC_RX_IPV4_GD		0x264</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_HDERR		0x26c</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_NOPAY		0x274</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_FRAG		0x27c</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_UDSBL		0x284</div><div class='add'>+</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_GD		0x28c</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_HDERR		0x294</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_NOPAY		0x29c</div><div class='add'>+</div><div class='add'>+#define MMC_XGMAC_RX_UDP_GD		0x2a4</div><div class='add'>+#define MMC_XGMAC_RX_UDP_ERR		0x2ac</div><div class='add'>+#define MMC_XGMAC_RX_TCP_GD		0x2b4</div><div class='add'>+#define MMC_XGMAC_RX_TCP_ERR		0x2bc</div><div class='add'>+#define MMC_XGMAC_RX_ICMP_GD		0x2c4</div><div class='add'>+#define MMC_XGMAC_RX_ICMP_ERR		0x2cc</div><div class='add'>+</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_GD_OCTETS	0x2d4</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_HDERR_OCTETS	0x2dc</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_NOPAY_OCTETS	0x2e4</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_FRAG_OCTETS	0x2ec</div><div class='add'>+#define MMC_XGMAC_RX_IPV4_UDSBL_OCTETS	0x2f4</div><div class='add'>+</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_GD_OCTETS	0x2fc</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_HDERR_OCTETS	0x304</div><div class='add'>+#define MMC_XGMAC_RX_IPV6_NOPAY_OCTETS	0x30c</div><div class='add'>+</div><div class='add'>+#define MMC_XGMAC_RX_UDP_GD_OCTETS	0x314</div><div class='add'>+#define MMC_XGMAC_RX_UDP_ERR_OCTETS	0x31c</div><div class='add'>+#define MMC_XGMAC_RX_TCP_GD_OCTETS	0x324</div><div class='add'>+#define MMC_XGMAC_RX_TCP_ERR_OCTETS	0x32c</div><div class='add'>+#define MMC_XGMAC_RX_ICMP_GD_OCTETS	0x334</div><div class='add'>+#define MMC_XGMAC_RX_ICMP_ERR_OCTETS	0x33c</div><div class='add'>+</div><div class='ctx'> static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)</div><div class='ctx'> {</div><div class='ctx'> 	u32 value = readl(mmcaddr + MMC_CNTRL);</div><div class='hunk'>@@ -352,6 +391,8 @@ static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)</div><div class='ctx'> {</div><div class='ctx'> 	writel(0x0, mmcaddr + MMC_RX_INTR_MASK);</div><div class='ctx'> 	writel(0x0, mmcaddr + MMC_TX_INTR_MASK);</div><div class='add'>+	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK);</div><div class='add'>+	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK);</div><div class='ctx'> 	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -410,6 +451,8 @@ static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)</div><div class='ctx'> 			     &amp;mmc-&gt;mmc_tx_pause_frame);</div><div class='ctx'> 	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,</div><div class='ctx'> 			     &amp;mmc-&gt;mmc_tx_vlan_frame_g);</div><div class='add'>+	mmc-&gt;mmc_tx_lpi_usec += readl(mmcaddr + MMC_XGMAC_TX_LPI_USEC);</div><div class='add'>+	mmc-&gt;mmc_tx_lpi_tran += readl(mmcaddr + MMC_XGMAC_TX_LPI_TRAN);</div><div class='ctx'> </div><div class='ctx'> 	/* MMC RX counter registers */</div><div class='ctx'> 	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,</div><div class='hunk'>@@ -455,9 +498,23 @@ static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)</div><div class='ctx'> 	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,</div><div class='ctx'> 			     &amp;mmc-&gt;mmc_rx_vlan_frames_gb);</div><div class='ctx'> 	mmc-&gt;mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);</div><div class='del'>-</div><div class='add'>+	mmc-&gt;mmc_rx_lpi_usec += readl(mmcaddr + MMC_XGMAC_RX_LPI_USEC);</div><div class='add'>+	mmc-&gt;mmc_rx_lpi_tran += readl(mmcaddr + MMC_XGMAC_RX_LPI_TRAN);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_PKT_GB,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_discard_frames_gb);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_DISCARD_OCT_GB,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_discard_octets_gb);</div><div class='add'>+	mmc-&gt;mmc_rx_align_err_frames +=</div><div class='add'>+		readl(mmcaddr + MMC_XGMAC_RX_ALIGN_ERR_PKT);</div><div class='add'>+</div><div class='add'>+	mmc-&gt;mmc_sgf_pass_fragment_cntr +=</div><div class='add'>+		readl(mmcaddr + MMC_XGMAC_SGF_PASS_PKT);</div><div class='add'>+	mmc-&gt;mmc_sgf_fail_fragment_cntr +=</div><div class='add'>+		readl(mmcaddr + MMC_XGMAC_SGF_FAIL_PKT);</div><div class='ctx'> 	mmc-&gt;mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);</div><div class='ctx'> 	mmc-&gt;mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_GATE_OVERRUN,</div><div class='add'>+			     &amp;mmc-&gt;mmc_tx_gate_overrun_cntr);</div><div class='ctx'> 	mmc-&gt;mmc_rx_packet_assembly_err_cntr +=</div><div class='ctx'> 		readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);</div><div class='ctx'> 	mmc-&gt;mmc_rx_packet_smd_err_cntr +=</div><div class='hunk'>@@ -466,6 +523,68 @@ static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)</div><div class='ctx'> 		readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);</div><div class='ctx'> 	mmc-&gt;mmc_rx_fpe_fragment_cntr +=</div><div class='ctx'> 		readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_gd);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_hderr);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_nopay);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_frag);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_udsbl);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_gd);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_hderr);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_nopay);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_udp_gd);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_udp_err);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_tcp_gd);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_tcp_err);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_icmp_gd);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_icmp_err);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_GD_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_gd_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_HDERR_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_hderr_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_NOPAY_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_nopay_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_FRAG_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_frag_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV4_UDSBL_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv4_udsbl_octets);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_GD_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_gd_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_HDERR_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_hderr_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_IPV6_NOPAY_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_ipv6_nopay_octets);</div><div class='add'>+</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_GD_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_udp_gd_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UDP_ERR_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_udp_err_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_GD_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_tcp_gd_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_TCP_ERR_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_tcp_err_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_GD_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_icmp_gd_octets);</div><div class='add'>+	dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_ICMP_ERR_OCTETS,</div><div class='add'>+			     &amp;mmc-&gt;mmc_rx_icmp_err_octets);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> const struct stmmac_mmc_ops dwxgmac_mmc_ops = {</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h<br/>index cd7a9768de5f..f155e4841c62 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac.h</a></div><div class='hunk'>@@ -51,6 +51,7 @@ struct stmmac_tx_info {</div><div class='ctx'> 	bool last_segment;</div><div class='ctx'> 	bool is_jumbo;</div><div class='ctx'> 	enum stmmac_txbuf_type buf_type;</div><div class='add'>+	struct xsk_tx_metadata_compl xsk_meta;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define STMMAC_TBS_AVAIL	BIT(0)</div><div class='hunk'>@@ -100,6 +101,17 @@ struct stmmac_xdp_buff {</div><div class='ctx'> 	struct dma_desc *ndesc;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct stmmac_metadata_request {</div><div class='add'>+	struct stmmac_priv *priv;</div><div class='add'>+	struct dma_desc *tx_desc;</div><div class='add'>+	bool *set_ic;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct stmmac_xsk_tx_complete {</div><div class='add'>+	struct stmmac_priv *priv;</div><div class='add'>+	struct dma_desc *desc;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct stmmac_rx_queue {</div><div class='ctx'> 	u32 rx_count_frames;</div><div class='ctx'> 	u32 queue_index;</div><div class='hunk'>@@ -255,6 +267,7 @@ struct stmmac_priv {</div><div class='ctx'> 	u32 msg_enable;</div><div class='ctx'> 	int wolopts;</div><div class='ctx'> 	int wol_irq;</div><div class='add'>+	bool wol_irq_disabled;</div><div class='ctx'> 	int clk_csr;</div><div class='ctx'> 	struct timer_list eee_ctrl_timer;</div><div class='ctx'> 	int lpi_irq;</div><div class='hunk'>@@ -283,6 +296,7 @@ struct stmmac_priv {</div><div class='ctx'> </div><div class='ctx'> 	void __iomem *mmcaddr;</div><div class='ctx'> 	void __iomem *ptpaddr;</div><div class='add'>+	void __iomem *estaddr;</div><div class='ctx'> 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];</div><div class='ctx'> 	int sfty_ce_irq;</div><div class='ctx'> 	int sfty_ue_irq;</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_est.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_est.c<br/>new file mode 100644<br/>index 000000000000..4da6ccc17c20<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_est.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_est.c</a></div><div class='hunk'>@@ -0,0 +1,165 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023, Intel Corporation</div><div class='add'>+ * stmmac EST(802.3 Qbv) handling</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/iopoll.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include "stmmac.h"</div><div class='add'>+#include "stmmac_est.h"</div><div class='add'>+</div><div class='add'>+static int est_write(void __iomem *est_addr, u32 reg, u32 val, bool gcl)</div><div class='add'>+{</div><div class='add'>+	u32 ctrl;</div><div class='add'>+</div><div class='add'>+	writel(val, est_addr + EST_GCL_DATA);</div><div class='add'>+</div><div class='add'>+	ctrl = (reg &lt;&lt; EST_ADDR_SHIFT);</div><div class='add'>+	ctrl |= gcl ? 0 : EST_GCRR;</div><div class='add'>+	writel(ctrl, est_addr + EST_GCL_CONTROL);</div><div class='add'>+</div><div class='add'>+	ctrl |= EST_SRWO;</div><div class='add'>+	writel(ctrl, est_addr + EST_GCL_CONTROL);</div><div class='add'>+</div><div class='add'>+	return readl_poll_timeout(est_addr + EST_GCL_CONTROL, ctrl,</div><div class='add'>+				  !(ctrl &amp; EST_SRWO), 100, 5000);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int est_configure(struct stmmac_priv *priv, struct stmmac_est *cfg,</div><div class='add'>+			 unsigned int ptp_rate)</div><div class='add'>+{</div><div class='add'>+	void __iomem *est_addr = priv-&gt;estaddr;</div><div class='add'>+	int i, ret = 0;</div><div class='add'>+	u32 ctrl;</div><div class='add'>+</div><div class='add'>+	ret |= est_write(est_addr, EST_BTR_LOW, cfg-&gt;btr[0], false);</div><div class='add'>+	ret |= est_write(est_addr, EST_BTR_HIGH, cfg-&gt;btr[1], false);</div><div class='add'>+	ret |= est_write(est_addr, EST_TER, cfg-&gt;ter, false);</div><div class='add'>+	ret |= est_write(est_addr, EST_LLR, cfg-&gt;gcl_size, false);</div><div class='add'>+	ret |= est_write(est_addr, EST_CTR_LOW, cfg-&gt;ctr[0], false);</div><div class='add'>+	ret |= est_write(est_addr, EST_CTR_HIGH, cfg-&gt;ctr[1], false);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; cfg-&gt;gcl_size; i++) {</div><div class='add'>+		ret = est_write(est_addr, i, cfg-&gt;gcl[i], true);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ctrl = readl(est_addr + EST_CONTROL);</div><div class='add'>+	if (priv-&gt;plat-&gt;has_xgmac) {</div><div class='add'>+		ctrl &amp;= ~EST_XGMAC_PTOV;</div><div class='add'>+		ctrl |= ((NSEC_PER_SEC / ptp_rate) * EST_XGMAC_PTOV_MUL) &lt;&lt;</div><div class='add'>+			 EST_XGMAC_PTOV_SHIFT;</div><div class='add'>+	} else {</div><div class='add'>+		ctrl &amp;= ~EST_GMAC5_PTOV;</div><div class='add'>+		ctrl |= ((NSEC_PER_SEC / ptp_rate) * EST_GMAC5_PTOV_MUL) &lt;&lt;</div><div class='add'>+			 EST_GMAC5_PTOV_SHIFT;</div><div class='add'>+	}</div><div class='add'>+	if (cfg-&gt;enable)</div><div class='add'>+		ctrl |= EST_EEST | EST_SSWL;</div><div class='add'>+	else</div><div class='add'>+		ctrl &amp;= ~EST_EEST;</div><div class='add'>+</div><div class='add'>+	writel(ctrl, est_addr + EST_CONTROL);</div><div class='add'>+</div><div class='add'>+	/* Configure EST interrupt */</div><div class='add'>+	if (cfg-&gt;enable)</div><div class='add'>+		ctrl = EST_IECGCE | EST_IEHS | EST_IEHF | EST_IEBE | EST_IECC;</div><div class='add'>+	else</div><div class='add'>+		ctrl = 0;</div><div class='add'>+</div><div class='add'>+	writel(ctrl, est_addr + EST_INT_EN);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void est_irq_status(struct stmmac_priv *priv, struct net_device *dev,</div><div class='add'>+			   struct stmmac_extra_stats *x, u32 txqcnt)</div><div class='add'>+{</div><div class='add'>+	u32 status, value, feqn, hbfq, hbfs, btrl, btrl_max;</div><div class='add'>+	void __iomem *est_addr = priv-&gt;estaddr;</div><div class='add'>+	u32 txqcnt_mask = BIT(txqcnt) - 1;</div><div class='add'>+</div><div class='add'>+	status = readl(est_addr + EST_STATUS);</div><div class='add'>+</div><div class='add'>+	value = EST_CGCE | EST_HLBS | EST_HLBF | EST_BTRE | EST_SWLC;</div><div class='add'>+</div><div class='add'>+	/* Return if there is no error */</div><div class='add'>+	if (!(status &amp; value))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (status &amp; EST_CGCE) {</div><div class='add'>+		/* Clear Interrupt */</div><div class='add'>+		writel(EST_CGCE, est_addr + EST_STATUS);</div><div class='add'>+</div><div class='add'>+		x-&gt;mtl_est_cgce++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (status &amp; EST_HLBS) {</div><div class='add'>+		value = readl(est_addr + EST_SCH_ERR);</div><div class='add'>+		value &amp;= txqcnt_mask;</div><div class='add'>+</div><div class='add'>+		x-&gt;mtl_est_hlbs++;</div><div class='add'>+</div><div class='add'>+		/* Clear Interrupt */</div><div class='add'>+		writel(value, est_addr + EST_SCH_ERR);</div><div class='add'>+</div><div class='add'>+		/* Collecting info to shows all the queues that has HLBS</div><div class='add'>+		 * issue. The only way to clear this is to clear the</div><div class='add'>+		 * statistic</div><div class='add'>+		 */</div><div class='add'>+		if (net_ratelimit())</div><div class='add'>+			netdev_err(dev, "EST: HLB(sched) Queue 0x%x\n", value);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (status &amp; EST_HLBF) {</div><div class='add'>+		value = readl(est_addr + EST_FRM_SZ_ERR);</div><div class='add'>+		feqn = value &amp; txqcnt_mask;</div><div class='add'>+</div><div class='add'>+		value = readl(est_addr + EST_FRM_SZ_CAP);</div><div class='add'>+		hbfq = (value &amp; EST_SZ_CAP_HBFQ_MASK(txqcnt)) &gt;&gt;</div><div class='add'>+			EST_SZ_CAP_HBFQ_SHIFT;</div><div class='add'>+		hbfs = value &amp; EST_SZ_CAP_HBFS_MASK;</div><div class='add'>+</div><div class='add'>+		x-&gt;mtl_est_hlbf++;</div><div class='add'>+</div><div class='add'>+		/* Clear Interrupt */</div><div class='add'>+		writel(feqn, est_addr + EST_FRM_SZ_ERR);</div><div class='add'>+</div><div class='add'>+		if (net_ratelimit())</div><div class='add'>+			netdev_err(dev, "EST: HLB(size) Queue %u Size %u\n",</div><div class='add'>+				   hbfq, hbfs);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (status &amp; EST_BTRE) {</div><div class='add'>+		if (priv-&gt;plat-&gt;has_xgmac) {</div><div class='add'>+			btrl = FIELD_GET(EST_XGMAC_BTRL, status);</div><div class='add'>+			btrl_max = FIELD_MAX(EST_XGMAC_BTRL);</div><div class='add'>+		} else {</div><div class='add'>+			btrl = FIELD_GET(EST_GMAC5_BTRL, status);</div><div class='add'>+			btrl_max = FIELD_MAX(EST_GMAC5_BTRL);</div><div class='add'>+		}</div><div class='add'>+		if (btrl == btrl_max)</div><div class='add'>+			x-&gt;mtl_est_btrlm++;</div><div class='add'>+		else</div><div class='add'>+			x-&gt;mtl_est_btre++;</div><div class='add'>+</div><div class='add'>+		if (net_ratelimit())</div><div class='add'>+			netdev_info(dev, "EST: BTR Error Loop Count %u\n",</div><div class='add'>+				    btrl);</div><div class='add'>+</div><div class='add'>+		writel(EST_BTRE, est_addr + EST_STATUS);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (status &amp; EST_SWLC) {</div><div class='add'>+		writel(EST_SWLC, est_addr + EST_STATUS);</div><div class='add'>+		netdev_info(dev, "EST: SWOL has been switched\n");</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const struct stmmac_est_ops dwmac510_est_ops = {</div><div class='add'>+	.configure = est_configure,</div><div class='add'>+	.irq_status = est_irq_status,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_est.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_est.h<br/>new file mode 100644<br/>index 000000000000..7a858c566e7e<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_est.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_est.h</a></div><div class='hunk'>@@ -0,0 +1,64 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0-only */</div><div class='add'>+/*</div><div class='add'>+ * Copyright (C) 2023, Intel Corporation</div><div class='add'>+ * stmmac EST(802.3 Qbv) handling</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#define EST_GMAC4_OFFSET		0x00000c50</div><div class='add'>+#define EST_XGMAC_OFFSET		0x00001050</div><div class='add'>+</div><div class='add'>+#define EST_CONTROL			0x00000000</div><div class='add'>+#define EST_GMAC5_PTOV			GENMASK(31, 24)</div><div class='add'>+#define EST_GMAC5_PTOV_SHIFT		24</div><div class='add'>+#define EST_GMAC5_PTOV_MUL		6</div><div class='add'>+#define EST_XGMAC_PTOV			GENMASK(31, 23)</div><div class='add'>+#define EST_XGMAC_PTOV_SHIFT		23</div><div class='add'>+#define EST_XGMAC_PTOV_MUL		9</div><div class='add'>+#define EST_SSWL			BIT(1)</div><div class='add'>+#define EST_EEST			BIT(0)</div><div class='add'>+</div><div class='add'>+#define EST_STATUS			0x00000008</div><div class='add'>+#define EST_GMAC5_BTRL			GENMASK(11, 8)</div><div class='add'>+#define EST_XGMAC_BTRL			GENMASK(15, 8)</div><div class='add'>+#define EST_SWOL			BIT(7)</div><div class='add'>+#define EST_SWOL_SHIFT			7</div><div class='add'>+#define EST_CGCE			BIT(4)</div><div class='add'>+#define EST_HLBS			BIT(3)</div><div class='add'>+#define EST_HLBF			BIT(2)</div><div class='add'>+#define EST_BTRE			BIT(1)</div><div class='add'>+#define EST_SWLC			BIT(0)</div><div class='add'>+</div><div class='add'>+#define EST_SCH_ERR			0x00000010</div><div class='add'>+</div><div class='add'>+#define EST_FRM_SZ_ERR			0x00000014</div><div class='add'>+</div><div class='add'>+#define EST_FRM_SZ_CAP			0x00000018</div><div class='add'>+#define EST_SZ_CAP_HBFS_MASK		GENMASK(14, 0)</div><div class='add'>+#define EST_SZ_CAP_HBFQ_SHIFT		16</div><div class='add'>+#define EST_SZ_CAP_HBFQ_MASK(val)		\</div><div class='add'>+	({					\</div><div class='add'>+		typeof(val) _val = (val);	\</div><div class='add'>+		(_val &gt; 4 ? GENMASK(18, 16) :	\</div><div class='add'>+		 _val &gt; 2 ? GENMASK(17, 16) :	\</div><div class='add'>+		 BIT(16));			\</div><div class='add'>+	})</div><div class='add'>+</div><div class='add'>+#define EST_INT_EN			0x00000020</div><div class='add'>+#define EST_IECGCE			EST_CGCE</div><div class='add'>+#define EST_IEHS			EST_HLBS</div><div class='add'>+#define EST_IEHF			EST_HLBF</div><div class='add'>+#define EST_IEBE			EST_BTRE</div><div class='add'>+#define EST_IECC			EST_SWLC</div><div class='add'>+</div><div class='add'>+#define EST_GCL_CONTROL			0x00000030</div><div class='add'>+#define EST_BTR_LOW			0x0</div><div class='add'>+#define EST_BTR_HIGH			0x1</div><div class='add'>+#define EST_CTR_LOW			0x2</div><div class='add'>+#define EST_CTR_HIGH			0x3</div><div class='add'>+#define EST_TER				0x4</div><div class='add'>+#define EST_LLR				0x5</div><div class='add'>+#define EST_ADDR_SHIFT			8</div><div class='add'>+#define EST_GCRR			BIT(2)</div><div class='add'>+#define EST_SRWO			BIT(0)</div><div class='add'>+</div><div class='add'>+#define EST_GCL_DATA			0x00000034</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c<br/>index f628411ae4ae..42d27b97dd1d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c</a></div><div class='hunk'>@@ -212,6 +212,8 @@ static const struct stmmac_stats stmmac_mmc[] = {</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_tx_excessdef),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_tx_pause_frame),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_tx_lpi_usec),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_tx_lpi_tran),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_framecount_gb),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_octetcount_gb),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_octetcount_g),</div><div class='hunk'>@@ -236,6 +238,11 @@ static const struct stmmac_stats stmmac_mmc[] = {</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_fifo_overflow),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_watchdog_error),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_rx_lpi_usec),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_rx_lpi_tran),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_rx_discard_frames_gb),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_rx_discard_octets_gb),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_rx_align_err_frames),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_ipc_intr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_ipv4_gd),</div><div class='hunk'>@@ -266,8 +273,11 @@ static const struct stmmac_stats stmmac_mmc[] = {</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),</div><div class='add'>+	STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),</div><div class='ctx'> 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),</div><div class='hunk'>@@ -311,8 +321,9 @@ static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct stmmac_priv *priv = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_RGMII ||</div><div class='del'>-	    priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_SGMII) {</div><div class='add'>+	if (!(priv-&gt;plat-&gt;flags &amp; STMMAC_FLAG_HAS_INTEGRATED_PCS) &amp;&amp;</div><div class='add'>+	    (priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_RGMII ||</div><div class='add'>+	     priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_SGMII)) {</div><div class='ctx'> 		struct rgmii_adv adv;</div><div class='ctx'> 		u32 supported, advertising, lp_advertising;</div><div class='ctx'> </div><div class='hunk'>@@ -397,8 +408,9 @@ stmmac_ethtool_set_link_ksettings(struct net_device *dev,</div><div class='ctx'> {</div><div class='ctx'> 	struct stmmac_priv *priv = netdev_priv(dev);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_RGMII ||</div><div class='del'>-	    priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_SGMII) {</div><div class='add'>+	if (!(priv-&gt;plat-&gt;flags &amp; STMMAC_FLAG_HAS_INTEGRATED_PCS) &amp;&amp;</div><div class='add'>+	    (priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_RGMII ||</div><div class='add'>+	     priv-&gt;hw-&gt;pcs &amp; STMMAC_PCS_SGMII)) {</div><div class='ctx'> 		/* Only support ANE */</div><div class='ctx'> 		if (cmd-&gt;base.autoneg != AUTONEG_ENABLE)</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -543,15 +555,12 @@ static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)</div><div class='ctx'> 	u32 rx_cnt = priv-&gt;plat-&gt;rx_queues_to_use;</div><div class='ctx'> 	unsigned int start;</div><div class='ctx'> 	int q, stat;</div><div class='del'>-	u64 *pos;</div><div class='ctx'> 	char *p;</div><div class='ctx'> </div><div class='del'>-	pos = data;</div><div class='ctx'> 	for (q = 0; q &lt; tx_cnt; q++) {</div><div class='ctx'> 		struct stmmac_txq_stats *txq_stats = &amp;priv-&gt;xstats.txq_stats[q];</div><div class='ctx'> 		struct stmmac_txq_stats snapshot;</div><div class='ctx'> </div><div class='del'>-		data = pos;</div><div class='ctx'> 		do {</div><div class='ctx'> 			start = u64_stats_fetch_begin(&amp;txq_stats-&gt;syncp);</div><div class='ctx'> 			snapshot = *txq_stats;</div><div class='hunk'>@@ -559,17 +568,15 @@ static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)</div><div class='ctx'> </div><div class='ctx'> 		p = (char *)&amp;snapshot + offsetof(struct stmmac_txq_stats, tx_pkt_n);</div><div class='ctx'> 		for (stat = 0; stat &lt; STMMAC_TXQ_STATS; stat++) {</div><div class='del'>-			*data++ += (*(u64 *)p);</div><div class='add'>+			*data++ = (*(u64 *)p);</div><div class='ctx'> 			p += sizeof(u64);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	pos = data;</div><div class='ctx'> 	for (q = 0; q &lt; rx_cnt; q++) {</div><div class='ctx'> 		struct stmmac_rxq_stats *rxq_stats = &amp;priv-&gt;xstats.rxq_stats[q];</div><div class='ctx'> 		struct stmmac_rxq_stats snapshot;</div><div class='ctx'> </div><div class='del'>-		data = pos;</div><div class='ctx'> 		do {</div><div class='ctx'> 			start = u64_stats_fetch_begin(&amp;rxq_stats-&gt;syncp);</div><div class='ctx'> 			snapshot = *rxq_stats;</div><div class='hunk'>@@ -577,7 +584,7 @@ static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)</div><div class='ctx'> </div><div class='ctx'> 		p = (char *)&amp;snapshot + offsetof(struct stmmac_rxq_stats, rx_pkt_n);</div><div class='ctx'> 		for (stat = 0; stat &lt; STMMAC_RXQ_STATS; stat++) {</div><div class='del'>-			*data++ += (*(u64 *)p);</div><div class='add'>+			*data++ = (*(u64 *)p);</div><div class='ctx'> 			p += sizeof(u64);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -825,10 +832,16 @@ static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)</div><div class='ctx'> 	if (wol-&gt;wolopts) {</div><div class='ctx'> 		pr_info("stmmac: wakeup enable\n");</div><div class='ctx'> 		device_set_wakeup_enable(priv-&gt;device, 1);</div><div class='del'>-		enable_irq_wake(priv-&gt;wol_irq);</div><div class='add'>+		/* Avoid unbalanced enable_irq_wake calls */</div><div class='add'>+		if (priv-&gt;wol_irq_disabled)</div><div class='add'>+			enable_irq_wake(priv-&gt;wol_irq);</div><div class='add'>+		priv-&gt;wol_irq_disabled = false;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		device_set_wakeup_enable(priv-&gt;device, 0);</div><div class='del'>-		disable_irq_wake(priv-&gt;wol_irq);</div><div class='add'>+		/* Avoid unbalanced disable_irq_wake calls */</div><div class='add'>+		if (!priv-&gt;wol_irq_disabled)</div><div class='add'>+			disable_irq_wake(priv-&gt;wol_irq);</div><div class='add'>+		priv-&gt;wol_irq_disabled = true;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;lock);</div><div class='hunk'>@@ -1077,41 +1090,42 @@ static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return ARRAY_SIZE(priv-&gt;rss.table);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-			   u8 *hfunc)</div><div class='add'>+static int stmmac_get_rxfh(struct net_device *dev,</div><div class='add'>+			   struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct stmmac_priv *priv = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(priv-&gt;rss.table); i++)</div><div class='del'>-			indir[i] = priv-&gt;rss.table[i];</div><div class='add'>+			rxfh-&gt;indir[i] = priv-&gt;rss.table[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, priv-&gt;rss.key, sizeof(priv-&gt;rss.key));</div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, priv-&gt;rss.key, sizeof(priv-&gt;rss.key));</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			   const u8 *key, const u8 hfunc)</div><div class='add'>+static int stmmac_set_rxfh(struct net_device *dev,</div><div class='add'>+			   struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			   struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct stmmac_priv *priv = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &amp;&amp; (hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(priv-&gt;rss.table); i++)</div><div class='del'>-			priv-&gt;rss.table[i] = indir[i];</div><div class='add'>+			priv-&gt;rss.table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(priv-&gt;rss.key, key, sizeof(priv-&gt;rss.key));</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(priv-&gt;rss.key, rxfh-&gt;key, sizeof(priv-&gt;rss.key));</div><div class='ctx'> </div><div class='ctx'> 	return stmmac_rss_configure(priv, priv-&gt;hw, &amp;priv-&gt;rss,</div><div class='ctx'> 				    priv-&gt;plat-&gt;rx_queues_to_use);</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c<br/>index 540f6a4ec0b8..f05bd757dfe5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c</a></div><div class='hunk'>@@ -237,7 +237,7 @@ static void timestamp_interrupt(struct stmmac_priv *priv)</div><div class='ctx'> 	 */</div><div class='ctx'> 	ts_status = readl(priv-&gt;ioaddr + GMAC_TIMESTAMP_STATUS);</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;plat-&gt;flags &amp; STMMAC_FLAG_EXT_SNAPSHOT_EN)</div><div class='add'>+	if (!(priv-&gt;plat-&gt;flags &amp; STMMAC_FLAG_EXT_SNAPSHOT_EN))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	num_snapshot = (ts_status &amp; GMAC_TIMESTAMP_ATSNS_MASK) &gt;&gt;</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c<br/>index 2afb2bd25977..a0e46369ae15 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_main.c</a></div><div class='hunk'>@@ -964,7 +964,8 @@ static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)</div><div class='ctx'> 	bool *hs_enable = &amp;fpe_cfg-&gt;hs_enable;</div><div class='ctx'> </div><div class='ctx'> 	if (is_up &amp;&amp; *hs_enable) {</div><div class='del'>-		stmmac_fpe_send_mpacket(priv, priv-&gt;ioaddr, MPACKET_VERIFY);</div><div class='add'>+		stmmac_fpe_send_mpacket(priv, priv-&gt;ioaddr, fpe_cfg,</div><div class='add'>+					MPACKET_VERIFY);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		*lo_state = FPE_STATE_OFF;</div><div class='ctx'> 		*lp_state = FPE_STATE_OFF;</div><div class='hunk'>@@ -2430,6 +2431,46 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void stmmac_xsk_request_timestamp(void *_priv)</div><div class='add'>+{</div><div class='add'>+	struct stmmac_metadata_request *meta_req = _priv;</div><div class='add'>+</div><div class='add'>+	stmmac_enable_tx_timestamp(meta_req-&gt;priv, meta_req-&gt;tx_desc);</div><div class='add'>+	*meta_req-&gt;set_ic = true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static u64 stmmac_xsk_fill_timestamp(void *_priv)</div><div class='add'>+{</div><div class='add'>+	struct stmmac_xsk_tx_complete *tx_compl = _priv;</div><div class='add'>+	struct stmmac_priv *priv = tx_compl-&gt;priv;</div><div class='add'>+	struct dma_desc *desc = tx_compl-&gt;desc;</div><div class='add'>+	bool found = false;</div><div class='add'>+	u64 ns = 0;</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;hwts_tx_en)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* check tx tstamp status */</div><div class='add'>+	if (stmmac_get_tx_timestamp_status(priv, desc)) {</div><div class='add'>+		stmmac_get_timestamp(priv, desc, priv-&gt;adv_ts, &amp;ns);</div><div class='add'>+		found = true;</div><div class='add'>+	} else if (!stmmac_get_mac_tx_timestamp(priv, priv-&gt;hw, &amp;ns)) {</div><div class='add'>+		found = true;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (found) {</div><div class='add'>+		ns -= priv-&gt;plat-&gt;cdc_error_adj;</div><div class='add'>+		return ns_to_ktime(ns);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct xsk_tx_metadata_ops stmmac_xsk_tx_metadata_ops = {</div><div class='add'>+	.tmo_request_timestamp		= stmmac_xsk_request_timestamp,</div><div class='add'>+	.tmo_fill_timestamp		= stmmac_xsk_fill_timestamp,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct netdev_queue *nq = netdev_get_tx_queue(priv-&gt;dev, queue);</div><div class='hunk'>@@ -2449,6 +2490,8 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)</div><div class='ctx'> 	budget = min(budget, stmmac_tx_avail(priv, queue));</div><div class='ctx'> </div><div class='ctx'> 	while (budget-- &gt; 0) {</div><div class='add'>+		struct stmmac_metadata_request meta_req;</div><div class='add'>+		struct xsk_tx_metadata *meta = NULL;</div><div class='ctx'> 		dma_addr_t dma_addr;</div><div class='ctx'> 		bool set_ic;</div><div class='ctx'> </div><div class='hunk'>@@ -2472,6 +2515,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)</div><div class='ctx'> 			tx_desc = tx_q-&gt;dma_tx + entry;</div><div class='ctx'> </div><div class='ctx'> 		dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);</div><div class='add'>+		meta = xsk_buff_get_metadata(pool, xdp_desc.addr);</div><div class='ctx'> 		xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);</div><div class='ctx'> </div><div class='ctx'> 		tx_q-&gt;tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;</div><div class='hunk'>@@ -2499,6 +2543,11 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)</div><div class='ctx'> 		else</div><div class='ctx'> 			set_ic = false;</div><div class='ctx'> </div><div class='add'>+		meta_req.priv = priv;</div><div class='add'>+		meta_req.tx_desc = tx_desc;</div><div class='add'>+		meta_req.set_ic = &amp;set_ic;</div><div class='add'>+		xsk_tx_metadata_request(meta, &amp;stmmac_xsk_tx_metadata_ops,</div><div class='add'>+					&amp;meta_req);</div><div class='ctx'> 		if (set_ic) {</div><div class='ctx'> 			tx_q-&gt;tx_count_frames = 0;</div><div class='ctx'> 			stmmac_set_tx_ic(priv, tx_desc);</div><div class='hunk'>@@ -2511,6 +2560,9 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)</div><div class='ctx'> </div><div class='ctx'> 		stmmac_enable_dma_transmission(priv, priv-&gt;ioaddr);</div><div class='ctx'> </div><div class='add'>+		xsk_tx_metadata_to_compl(meta,</div><div class='add'>+					 &amp;tx_q-&gt;tx_skbuff_dma[entry].xsk_meta);</div><div class='add'>+</div><div class='ctx'> 		tx_q-&gt;cur_tx = STMMAC_GET_ENTRY(tx_q-&gt;cur_tx, priv-&gt;dma_conf.dma_tx_size);</div><div class='ctx'> 		entry = tx_q-&gt;cur_tx;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -2620,8 +2672,18 @@ static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue,</div><div class='ctx'> 			} else {</div><div class='ctx'> 				tx_packets++;</div><div class='ctx'> 			}</div><div class='del'>-			if (skb)</div><div class='add'>+			if (skb) {</div><div class='ctx'> 				stmmac_get_tx_hwtstamp(priv, p, skb);</div><div class='add'>+			} else {</div><div class='add'>+				struct stmmac_xsk_tx_complete tx_compl = {</div><div class='add'>+					.priv = priv,</div><div class='add'>+					.desc = p,</div><div class='add'>+				};</div><div class='add'>+</div><div class='add'>+				xsk_tx_metadata_complete(&amp;tx_q-&gt;tx_skbuff_dma[entry].xsk_meta,</div><div class='add'>+							 &amp;stmmac_xsk_tx_metadata_ops,</div><div class='add'>+							 &amp;tx_compl);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (likely(tx_q-&gt;tx_skbuff_dma[entry].buf &amp;&amp;</div><div class='hunk'>@@ -3469,6 +3531,8 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)</div><div class='ctx'> 	/* Start the ball rolling... */</div><div class='ctx'> 	stmmac_start_all_dma(priv);</div><div class='ctx'> </div><div class='add'>+	stmmac_set_hw_vlan_mode(priv, priv-&gt;hw);</div><div class='add'>+</div><div class='ctx'> 	if (priv-&gt;dma_cap.fpesel) {</div><div class='ctx'> 		stmmac_fpe_start_wq(priv);</div><div class='ctx'> </div><div class='hunk'>@@ -3564,6 +3628,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)</div><div class='ctx'> 	/* Request the Wake IRQ in case of another line</div><div class='ctx'> 	 * is used for WoL</div><div class='ctx'> 	 */</div><div class='add'>+	priv-&gt;wol_irq_disabled = true;</div><div class='ctx'> 	if (priv-&gt;wol_irq &gt; 0 &amp;&amp; priv-&gt;wol_irq != dev-&gt;irq) {</div><div class='ctx'> 		int_name = priv-&gt;int_name_wol;</div><div class='ctx'> 		sprintf(int_name, "%s:%s", dev-&gt;name, "wol");</div><div class='hunk'>@@ -4371,6 +4436,28 @@ dma_map_err:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * stmmac_has_ip_ethertype() - Check if packet has IP ethertype</div><div class='add'>+ * @skb: socket buffer to check</div><div class='add'>+ *</div><div class='add'>+ * Check if a packet has an ethertype that will trigger the IP header checks</div><div class='add'>+ * and IP/TCP checksum engine of the stmmac core.</div><div class='add'>+ *</div><div class='add'>+ * Return: true if the ethertype can trigger the checksum engine, false</div><div class='add'>+ * otherwise</div><div class='add'>+ */</div><div class='add'>+static bool stmmac_has_ip_ethertype(struct sk_buff *skb)</div><div class='add'>+{</div><div class='add'>+	int depth = 0;</div><div class='add'>+	__be16 proto;</div><div class='add'>+</div><div class='add'>+	proto = __vlan_get_protocol(skb, eth_header_parse_protocol(skb),</div><div class='add'>+				    &amp;depth);</div><div class='add'>+</div><div class='add'>+	return (depth &lt;= ETH_HLEN) &amp;&amp;</div><div class='add'>+		(proto == htons(ETH_P_IP) || proto == htons(ETH_P_IPV6));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  *  stmmac_xmit - Tx entry point of the driver</div><div class='ctx'>  *  @skb : the socket buffer</div><div class='ctx'>  *  @dev : device pointer</div><div class='hunk'>@@ -4434,9 +4521,13 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 	/* DWMAC IPs can be synthesized to support tx coe only for a few tx</div><div class='ctx'> 	 * queues. In that case, checksum offloading for those queues that don't</div><div class='ctx'> 	 * support tx coe needs to fallback to software checksum calculation.</div><div class='add'>+	 *</div><div class='add'>+	 * Packets that won't trigger the COE e.g. most DSA-tagged packets will</div><div class='add'>+	 * also have to be checksummed in software.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (csum_insertion &amp;&amp;</div><div class='del'>-	    priv-&gt;plat-&gt;tx_queues_cfg[queue].coe_unsupported) {</div><div class='add'>+	    (priv-&gt;plat-&gt;tx_queues_cfg[queue].coe_unsupported ||</div><div class='add'>+	     !stmmac_has_ip_ethertype(skb))) {</div><div class='ctx'> 		if (unlikely(skb_checksum_help(skb)))</div><div class='ctx'> 			goto dma_map_err;</div><div class='ctx'> 		csum_insertion = !csum_insertion;</div><div class='hunk'>@@ -4993,10 +5084,15 @@ static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	stmmac_get_rx_hwtstamp(priv, p, np, skb);</div><div class='del'>-	stmmac_rx_vlan(priv-&gt;dev, skb);</div><div class='add'>+	if (priv-&gt;hw-&gt;hw_vlan_en)</div><div class='add'>+		/* MAC level stripping. */</div><div class='add'>+		stmmac_rx_hw_vlan(priv, priv-&gt;hw, p, skb);</div><div class='add'>+	else</div><div class='add'>+		/* Driver level stripping. */</div><div class='add'>+		stmmac_rx_vlan(priv-&gt;dev, skb);</div><div class='ctx'> 	skb-&gt;protocol = eth_type_trans(skb, priv-&gt;dev);</div><div class='ctx'> </div><div class='del'>-	if (unlikely(!coe))</div><div class='add'>+	if (unlikely(!coe) || !stmmac_has_ip_ethertype(skb))</div><div class='ctx'> 		skb_checksum_none_assert(skb);</div><div class='ctx'> 	else</div><div class='ctx'> 		skb-&gt;ip_summed = CHECKSUM_UNNECESSARY;</div><div class='hunk'>@@ -5509,10 +5605,17 @@ drain_data:</div><div class='ctx'> 		/* Got entire packet into SKB. Finish it. */</div><div class='ctx'> </div><div class='ctx'> 		stmmac_get_rx_hwtstamp(priv, p, np, skb);</div><div class='del'>-		stmmac_rx_vlan(priv-&gt;dev, skb);</div><div class='add'>+</div><div class='add'>+		if (priv-&gt;hw-&gt;hw_vlan_en)</div><div class='add'>+			/* MAC level stripping. */</div><div class='add'>+			stmmac_rx_hw_vlan(priv, priv-&gt;hw, p, skb);</div><div class='add'>+		else</div><div class='add'>+			/* Driver level stripping. */</div><div class='add'>+			stmmac_rx_vlan(priv-&gt;dev, skb);</div><div class='add'>+</div><div class='ctx'> 		skb-&gt;protocol = eth_type_trans(skb, priv-&gt;dev);</div><div class='ctx'> </div><div class='del'>-		if (unlikely(!coe))</div><div class='add'>+		if (unlikely(!coe) || !stmmac_has_ip_ethertype(skb))</div><div class='ctx'> 			skb_checksum_none_assert(skb);</div><div class='ctx'> 		else</div><div class='ctx'> 			skb-&gt;ip_summed = CHECKSUM_UNNECESSARY;</div><div class='hunk'>@@ -5818,6 +5921,13 @@ static int stmmac_set_features(struct net_device *netdev,</div><div class='ctx'> 			stmmac_enable_sph(priv, priv-&gt;ioaddr, sph_en, chan);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (features &amp; NETIF_F_HW_VLAN_CTAG_RX)</div><div class='add'>+		priv-&gt;hw-&gt;hw_vlan_en = true;</div><div class='add'>+	else</div><div class='add'>+		priv-&gt;hw-&gt;hw_vlan_en = false;</div><div class='add'>+</div><div class='add'>+	stmmac_set_hw_vlan_mode(priv, priv-&gt;hw);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5839,6 +5949,7 @@ static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)</div><div class='ctx'> 		/* If user has requested FPE enable, quickly response */</div><div class='ctx'> 		if (*hs_enable)</div><div class='ctx'> 			stmmac_fpe_send_mpacket(priv, priv-&gt;ioaddr,</div><div class='add'>+						fpe_cfg,</div><div class='ctx'> 						MPACKET_RESPONSE);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -5878,7 +5989,7 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv)</div><div class='ctx'> 		pm_wakeup_event(priv-&gt;device, 0);</div><div class='ctx'> </div><div class='ctx'> 	if (priv-&gt;dma_cap.estsel)</div><div class='del'>-		stmmac_est_irq_status(priv, priv-&gt;ioaddr, priv-&gt;dev,</div><div class='add'>+		stmmac_est_irq_status(priv, priv, priv-&gt;dev,</div><div class='ctx'> 				      &amp;priv-&gt;xstats, tx_cnt);</div><div class='ctx'> </div><div class='ctx'> 	if (priv-&gt;dma_cap.fpesel) {</div><div class='hunk'>@@ -6180,30 +6291,23 @@ static struct dentry *stmmac_fs_dir;</div><div class='ctx'> static void sysfs_display_ring(void *head, int size, int extend_desc,</div><div class='ctx'> 			       struct seq_file *seq, dma_addr_t dma_phy_addr)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='ctx'> 	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;</div><div class='ctx'> 	struct dma_desc *p = (struct dma_desc *)head;</div><div class='add'>+	unsigned int desc_size;</div><div class='ctx'> 	dma_addr_t dma_addr;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='add'>+	desc_size = extend_desc ? sizeof(*ep) : sizeof(*p);</div><div class='ctx'> 	for (i = 0; i &lt; size; i++) {</div><div class='del'>-		if (extend_desc) {</div><div class='del'>-			dma_addr = dma_phy_addr + i * sizeof(*ep);</div><div class='del'>-			seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",</div><div class='del'>-				   i, &amp;dma_addr,</div><div class='del'>-				   le32_to_cpu(ep-&gt;basic.des0),</div><div class='del'>-				   le32_to_cpu(ep-&gt;basic.des1),</div><div class='del'>-				   le32_to_cpu(ep-&gt;basic.des2),</div><div class='del'>-				   le32_to_cpu(ep-&gt;basic.des3));</div><div class='del'>-			ep++;</div><div class='del'>-		} else {</div><div class='del'>-			dma_addr = dma_phy_addr + i * sizeof(*p);</div><div class='del'>-			seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",</div><div class='del'>-				   i, &amp;dma_addr,</div><div class='del'>-				   le32_to_cpu(p-&gt;des0), le32_to_cpu(p-&gt;des1),</div><div class='del'>-				   le32_to_cpu(p-&gt;des2), le32_to_cpu(p-&gt;des3));</div><div class='add'>+		dma_addr = dma_phy_addr + i * desc_size;</div><div class='add'>+		seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",</div><div class='add'>+				i, &amp;dma_addr,</div><div class='add'>+				le32_to_cpu(p-&gt;des0), le32_to_cpu(p-&gt;des1),</div><div class='add'>+				le32_to_cpu(p-&gt;des2), le32_to_cpu(p-&gt;des3));</div><div class='add'>+		if (extend_desc)</div><div class='add'>+			p = &amp;(++ep)-&gt;basic;</div><div class='add'>+		else</div><div class='ctx'> 			p++;</div><div class='del'>-		}</div><div class='del'>-		seq_printf(seq, "\n");</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -7263,6 +7367,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work)</div><div class='ctx'> 		if (*lo_state == FPE_STATE_ENTERING_ON &amp;&amp;</div><div class='ctx'> 		    *lp_state == FPE_STATE_ENTERING_ON) {</div><div class='ctx'> 			stmmac_fpe_configure(priv, priv-&gt;ioaddr,</div><div class='add'>+					     fpe_cfg,</div><div class='ctx'> 					     priv-&gt;plat-&gt;tx_queues_to_use,</div><div class='ctx'> 					     priv-&gt;plat-&gt;rx_queues_to_use,</div><div class='ctx'> 					     *enable);</div><div class='hunk'>@@ -7281,6 +7386,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work)</div><div class='ctx'> 			netdev_info(priv-&gt;dev, SEND_VERIFY_MPAKCET_FMT,</div><div class='ctx'> 				    *lo_state, *lp_state);</div><div class='ctx'> 			stmmac_fpe_send_mpacket(priv, priv-&gt;ioaddr,</div><div class='add'>+						fpe_cfg,</div><div class='ctx'> 						MPACKET_VERIFY);</div><div class='ctx'> 		}</div><div class='ctx'> 		/* Sleep then retry */</div><div class='hunk'>@@ -7295,6 +7401,7 @@ void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)</div><div class='ctx'> 	if (priv-&gt;plat-&gt;fpe_cfg-&gt;hs_enable != enable) {</div><div class='ctx'> 		if (enable) {</div><div class='ctx'> 			stmmac_fpe_send_mpacket(priv, priv-&gt;ioaddr,</div><div class='add'>+						priv-&gt;plat-&gt;fpe_cfg,</div><div class='ctx'> 						MPACKET_VERIFY);</div><div class='ctx'> 		} else {</div><div class='ctx'> 			priv-&gt;plat-&gt;fpe_cfg-&gt;lo_fpe_state = FPE_STATE_OFF;</div><div class='hunk'>@@ -7450,6 +7557,7 @@ int stmmac_dvr_probe(struct device *device,</div><div class='ctx'> 	ndev-&gt;netdev_ops = &amp;stmmac_netdev_ops;</div><div class='ctx'> </div><div class='ctx'> 	ndev-&gt;xdp_metadata_ops = &amp;stmmac_xdp_metadata_ops;</div><div class='add'>+	ndev-&gt;xsk_tx_metadata_ops = &amp;stmmac_xsk_tx_metadata_ops;</div><div class='ctx'> </div><div class='ctx'> 	ndev-&gt;hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |</div><div class='ctx'> 			    NETIF_F_RXCSUM;</div><div class='hunk'>@@ -7516,6 +7624,9 @@ int stmmac_dvr_probe(struct device *device,</div><div class='ctx'> #ifdef STMMAC_VLAN_TAG_USED</div><div class='ctx'> 	/* Both mac100 and gmac support receive VLAN tag detection */</div><div class='ctx'> 	ndev-&gt;features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;</div><div class='add'>+	ndev-&gt;hw_features |= NETIF_F_HW_VLAN_CTAG_RX;</div><div class='add'>+	priv-&gt;hw-&gt;hw_vlan_en = true;</div><div class='add'>+</div><div class='ctx'> 	if (priv-&gt;dma_cap.vlhash) {</div><div class='ctx'> 		ndev-&gt;features |= NETIF_F_HW_VLAN_CTAG_FILTER;</div><div class='ctx'> 		ndev-&gt;features |= NETIF_F_HW_VLAN_STAG_FILTER;</div><div class='hunk'>@@ -7755,6 +7866,7 @@ int stmmac_suspend(struct device *dev)</div><div class='ctx'> 	if (priv-&gt;dma_cap.fpesel) {</div><div class='ctx'> 		/* Disable FPE */</div><div class='ctx'> 		stmmac_fpe_configure(priv, priv-&gt;ioaddr,</div><div class='add'>+				     priv-&gt;plat-&gt;fpe_cfg,</div><div class='ctx'> 				     priv-&gt;plat-&gt;tx_queues_to_use,</div><div class='ctx'> 				     priv-&gt;plat-&gt;rx_queues_to_use, false);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c<br/>index fa9e7e7040b9..0542cfd1817e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c</a></div><div class='hunk'>@@ -591,7 +591,11 @@ int stmmac_mdio_register(struct net_device *ndev)</div><div class='ctx'> 	new_bus-&gt;parent = priv-&gt;device;</div><div class='ctx'> </div><div class='ctx'> 	err = of_mdiobus_register(new_bus, mdio_node);</div><div class='del'>-	if (err != 0) {</div><div class='add'>+	if (err == -ENODEV) {</div><div class='add'>+		err = 0;</div><div class='add'>+		dev_info(dev, "MDIO bus is disabled\n");</div><div class='add'>+		goto bus_register_fail;</div><div class='add'>+	} else if (err) {</div><div class='ctx'> 		dev_err_probe(dev, err, "Cannot register the MDIO bus\n");</div><div class='ctx'> 		goto bus_register_fail;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c<br/>index 1ffde555da47..70eadc83ca68 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c</a></div><div class='hunk'>@@ -296,62 +296,80 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * stmmac_dt_phy - parse device-tree driver parameters to allocate PHY resources</div><div class='del'>- * @plat: driver data platform structure</div><div class='del'>- * @np: device tree node</div><div class='del'>- * @dev: device pointer</div><div class='del'>- * Description:</div><div class='del'>- * The mdio bus will be allocated in case of a phy transceiver is on board;</div><div class='del'>- * it will be NULL if the fixed-link is configured.</div><div class='del'>- * If there is the "snps,dwmac-mdio" sub-node the mdio will be allocated</div><div class='del'>- * in any case (for DSA, mdio must be registered even if fixed-link).</div><div class='del'>- * The table below sums the supported configurations:</div><div class='del'>- *	-------------------------------</div><div class='del'>- *	snps,phy-addr	|     Y</div><div class='del'>- *	-------------------------------</div><div class='del'>- *	phy-handle	|     Y</div><div class='del'>- *	-------------------------------</div><div class='del'>- *	fixed-link	|     N</div><div class='del'>- *	-------------------------------</div><div class='del'>- *	snps,dwmac-mdio	|</div><div class='del'>- *	  even if	|     Y</div><div class='del'>- *	fixed-link	|</div><div class='del'>- *	-------------------------------</div><div class='add'>+ * stmmac_of_get_mdio() - Gets the MDIO bus from the devicetree.</div><div class='add'>+ * @np: devicetree node</div><div class='ctx'>  *</div><div class='del'>- * It returns 0 in case of success otherwise -ENODEV.</div><div class='add'>+ * The MDIO bus will be searched for in the following ways:</div><div class='add'>+ * 1. The compatible is "snps,dwc-qos-ethernet-4.10" &amp;&amp; a "mdio" named</div><div class='add'>+ *    child node exists</div><div class='add'>+ * 2. A child node with the "snps,dwmac-mdio" compatible is present</div><div class='add'>+ *</div><div class='add'>+ * Return: The MDIO node if present otherwise NULL</div><div class='ctx'>  */</div><div class='del'>-static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,</div><div class='del'>-			 struct device_node *np, struct device *dev)</div><div class='add'>+static struct device_node *stmmac_of_get_mdio(struct device_node *np)</div><div class='ctx'> {</div><div class='del'>-	bool mdio = !of_phy_is_fixed_link(np);</div><div class='ctx'> 	static const struct of_device_id need_mdio_ids[] = {</div><div class='ctx'> 		{ .compatible = "snps,dwc-qos-ethernet-4.10" },</div><div class='ctx'> 		{},</div><div class='ctx'> 	};</div><div class='add'>+	struct device_node *mdio_node = NULL;</div><div class='ctx'> </div><div class='ctx'> 	if (of_match_node(need_mdio_ids, np)) {</div><div class='del'>-		plat-&gt;mdio_node = of_get_child_by_name(np, "mdio");</div><div class='add'>+		mdio_node = of_get_child_by_name(np, "mdio");</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/**</div><div class='ctx'> 		 * If snps,dwmac-mdio is passed from DT, always register</div><div class='ctx'> 		 * the MDIO</div><div class='ctx'> 		 */</div><div class='del'>-		for_each_child_of_node(np, plat-&gt;mdio_node) {</div><div class='del'>-			if (of_device_is_compatible(plat-&gt;mdio_node,</div><div class='add'>+		for_each_child_of_node(np, mdio_node) {</div><div class='add'>+			if (of_device_is_compatible(mdio_node,</div><div class='ctx'> 						    "snps,dwmac-mdio"))</div><div class='ctx'> 				break;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (plat-&gt;mdio_node) {</div><div class='add'>+	return mdio_node;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * stmmac_mdio_setup() - Populate platform related MDIO structures.</div><div class='add'>+ * @plat: driver data platform structure</div><div class='add'>+ * @np: devicetree node</div><div class='add'>+ * @dev: device pointer</div><div class='add'>+ *</div><div class='add'>+ * This searches for MDIO information from the devicetree.</div><div class='add'>+ * If an MDIO node is found, it's assigned to plat-&gt;mdio_node and</div><div class='add'>+ * plat-&gt;mdio_bus_data is allocated.</div><div class='add'>+ * If no connection can be determined, just plat-&gt;mdio_bus_data is allocated</div><div class='add'>+ * to indicate a bus should be created and scanned for a phy.</div><div class='add'>+ * If it's determined there's no MDIO bus needed, both are left NULL.</div><div class='add'>+ *</div><div class='add'>+ * This expects that plat-&gt;phy_node has already been searched for.</div><div class='add'>+ *</div><div class='add'>+ * Return: 0 on success, errno otherwise.</div><div class='add'>+ */</div><div class='add'>+static int stmmac_mdio_setup(struct plat_stmmacenet_data *plat,</div><div class='add'>+			     struct device_node *np, struct device *dev)</div><div class='add'>+{</div><div class='add'>+	bool legacy_mdio;</div><div class='add'>+</div><div class='add'>+	plat-&gt;mdio_node = stmmac_of_get_mdio(np);</div><div class='add'>+	if (plat-&gt;mdio_node)</div><div class='ctx'> 		dev_dbg(dev, "Found MDIO subnode\n");</div><div class='del'>-		mdio = true;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	if (mdio) {</div><div class='del'>-		plat-&gt;mdio_bus_data =</div><div class='del'>-			devm_kzalloc(dev, sizeof(struct stmmac_mdio_bus_data),</div><div class='del'>-				     GFP_KERNEL);</div><div class='add'>+	/* Legacy devicetrees allowed for no MDIO bus description and expect</div><div class='add'>+	 * the bus to be scanned for devices. If there's no phy or fixed-link</div><div class='add'>+	 * described assume this is the case since there must be something</div><div class='add'>+	 * connected to the MAC.</div><div class='add'>+	 */</div><div class='add'>+	legacy_mdio = !of_phy_is_fixed_link(np) &amp;&amp; !plat-&gt;phy_node;</div><div class='add'>+	if (legacy_mdio)</div><div class='add'>+		dev_info(dev, "Deprecated MDIO bus assumption used\n");</div><div class='add'>+</div><div class='add'>+	if (plat-&gt;mdio_node || legacy_mdio) {</div><div class='add'>+		plat-&gt;mdio_bus_data = devm_kzalloc(dev,</div><div class='add'>+						   sizeof(*plat-&gt;mdio_bus_data),</div><div class='add'>+						   GFP_KERNEL);</div><div class='ctx'> 		if (!plat-&gt;mdio_bus_data)</div><div class='ctx'> 			return -ENOMEM;</div><div class='ctx'> </div><div class='hunk'>@@ -471,8 +489,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)</div><div class='ctx'> 	if (of_property_read_u32(np, "snps,phy-addr", &amp;plat-&gt;phy_addr) == 0)</div><div class='ctx'> 		dev_warn(&amp;pdev-&gt;dev, "snps,phy-addr property is deprecated\n");</div><div class='ctx'> </div><div class='del'>-	/* To Configure PHY by using all device-tree supported properties */</div><div class='del'>-	rc = stmmac_dt_phy(plat, np, &amp;pdev-&gt;dev);</div><div class='add'>+	rc = stmmac_mdio_setup(plat, np, &amp;pdev-&gt;dev);</div><div class='ctx'> 	if (rc)</div><div class='ctx'> 		return ERR_PTR(rc);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c<br/>index bffa5c017032..e04830a3a1fb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c</a></div><div class='hunk'>@@ -72,7 +72,7 @@ static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)</div><div class='ctx'> 		est_rst = true;</div><div class='ctx'> 		mutex_lock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 		priv-&gt;plat-&gt;est-&gt;enable = false;</div><div class='del'>-		stmmac_est_configure(priv, priv-&gt;ioaddr, priv-&gt;plat-&gt;est,</div><div class='add'>+		stmmac_est_configure(priv, priv, priv-&gt;plat-&gt;est,</div><div class='ctx'> 				     priv-&gt;plat-&gt;clk_ptp_rate);</div><div class='ctx'> 		mutex_unlock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -102,7 +102,7 @@ static int stmmac_adjust_time(struct ptp_clock_info *ptp, s64 delta)</div><div class='ctx'> 		priv-&gt;plat-&gt;est-&gt;btr[0] = (u32)time.tv_nsec;</div><div class='ctx'> 		priv-&gt;plat-&gt;est-&gt;btr[1] = (u32)time.tv_sec;</div><div class='ctx'> 		priv-&gt;plat-&gt;est-&gt;enable = true;</div><div class='del'>-		ret = stmmac_est_configure(priv, priv-&gt;ioaddr, priv-&gt;plat-&gt;est,</div><div class='add'>+		ret = stmmac_est_configure(priv, priv, priv-&gt;plat-&gt;est,</div><div class='ctx'> 					   priv-&gt;plat-&gt;clk_ptp_rate);</div><div class='ctx'> 		mutex_unlock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 		if (ret)</div><div class='head'>diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c<br/>index ac41ef4cbd2f..26fa33e5ec34 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c</a></div><div class='hunk'>@@ -975,6 +975,8 @@ static int tc_setup_taprio(struct stmmac_priv *priv,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	if (!qopt-&gt;cycle_time)</div><div class='ctx'> 		return -ERANGE;</div><div class='add'>+	if (qopt-&gt;cycle_time_extension &gt;= BIT(wid + 7))</div><div class='add'>+		return -ERANGE;</div><div class='ctx'> </div><div class='ctx'> 	if (!plat-&gt;est) {</div><div class='ctx'> 		plat-&gt;est = devm_kzalloc(priv-&gt;device, sizeof(*plat-&gt;est),</div><div class='hunk'>@@ -1041,6 +1043,8 @@ static int tc_setup_taprio(struct stmmac_priv *priv,</div><div class='ctx'> 	priv-&gt;plat-&gt;est-&gt;ctr[0] = do_div(ctr, NSEC_PER_SEC);</div><div class='ctx'> 	priv-&gt;plat-&gt;est-&gt;ctr[1] = (u32)ctr;</div><div class='ctx'> </div><div class='add'>+	priv-&gt;plat-&gt;est-&gt;ter = qopt-&gt;cycle_time_extension;</div><div class='add'>+</div><div class='ctx'> 	if (fpe &amp;&amp; !priv-&gt;dma_cap.fpesel) {</div><div class='ctx'> 		mutex_unlock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='hunk'>@@ -1051,7 +1055,7 @@ static int tc_setup_taprio(struct stmmac_priv *priv,</div><div class='ctx'> 	 */</div><div class='ctx'> 	priv-&gt;plat-&gt;fpe_cfg-&gt;enable = fpe;</div><div class='ctx'> </div><div class='del'>-	ret = stmmac_est_configure(priv, priv-&gt;ioaddr, priv-&gt;plat-&gt;est,</div><div class='add'>+	ret = stmmac_est_configure(priv, priv, priv-&gt;plat-&gt;est,</div><div class='ctx'> 				   priv-&gt;plat-&gt;clk_ptp_rate);</div><div class='ctx'> 	mutex_unlock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -1072,13 +1076,14 @@ disable:</div><div class='ctx'> 	if (priv-&gt;plat-&gt;est) {</div><div class='ctx'> 		mutex_lock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 		priv-&gt;plat-&gt;est-&gt;enable = false;</div><div class='del'>-		stmmac_est_configure(priv, priv-&gt;ioaddr, priv-&gt;plat-&gt;est,</div><div class='add'>+		stmmac_est_configure(priv, priv, priv-&gt;plat-&gt;est,</div><div class='ctx'> 				     priv-&gt;plat-&gt;clk_ptp_rate);</div><div class='ctx'> 		mutex_unlock(&amp;priv-&gt;plat-&gt;est-&gt;lock);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	priv-&gt;plat-&gt;fpe_cfg-&gt;enable = false;</div><div class='ctx'> 	stmmac_fpe_configure(priv, priv-&gt;ioaddr,</div><div class='add'>+			     priv-&gt;plat-&gt;fpe_cfg,</div><div class='ctx'> 			     priv-&gt;plat-&gt;tx_queues_to_use,</div><div class='ctx'> 			     priv-&gt;plat-&gt;rx_queues_to_use,</div><div class='ctx'> 			     false);</div><div class='head'>diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig<br/>index e60b557d59b9..be01450c20dc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/Kconfig</a></div><div class='hunk'>@@ -134,14 +134,16 @@ config TI_K3_AM65_CPTS</div><div class='ctx'> 	  protocol, Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn)</div><div class='ctx'> 	  and PCIe Subsystem Precision Time Measurement (PTM).</div><div class='ctx'> </div><div class='del'>-config TI_AM65_CPSW_TAS</div><div class='del'>-	bool "Enable TAS offload in AM65 CPSW"</div><div class='add'>+config TI_AM65_CPSW_QOS</div><div class='add'>+	bool "Enable QoS offload features in AM65 CPSW"</div><div class='ctx'> 	depends on TI_K3_AM65_CPSW_NUSS &amp;&amp; NET_SCH_TAPRIO &amp;&amp; TI_K3_AM65_CPTS</div><div class='ctx'> 	help</div><div class='del'>-	  Say y here to support Time Aware Shaper(TAS) offload in AM65 CPSW.</div><div class='del'>-	  AM65 CPSW hardware supports Enhanced Scheduled Traffic (EST)</div><div class='del'>-	  defined in IEEE 802.1Q 2018. The EST scheduler runs on CPTS and the</div><div class='del'>-	  TAS/EST schedule is updated in the Fetch RAM memory of the CPSW.</div><div class='add'>+	  This option enables QoS offload features in AM65 CPSW like</div><div class='add'>+	  Time Aware Shaper (TAS) / Enhanced Scheduled Traffic (EST),</div><div class='add'>+	  MQPRIO qdisc offload and Frame-Preemption MAC Merge / Interspersing</div><div class='add'>+	  Express Traffic (IET).</div><div class='add'>+	  The EST scheduler runs on CPTS and the TAS/EST schedule is</div><div class='add'>+	  updated in the Fetch RAM memory of the CPSW.</div><div class='ctx'> </div><div class='ctx'> config TI_KEYSTONE_NETCP</div><div class='ctx'> 	tristate "TI Keystone NETCP Core Support"</div><div class='head'>diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile<br/>index 27de1d697134..d8590304f3df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/Makefile</a></div><div class='hunk'>@@ -26,7 +26,8 @@ keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o cpsw_ale.</div><div class='ctx'> obj-$(CONFIG_TI_K3_CPPI_DESC_POOL) += k3-cppi-desc-pool.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o</div><div class='del'>-ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o am65-cpsw-qos.o</div><div class='add'>+ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o</div><div class='add'>+ti-am65-cpsw-nuss-$(CONFIG_TI_AM65_CPSW_QOS) += am65-cpsw-qos.o</div><div class='ctx'> ti-am65-cpsw-nuss-$(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV) += am65-cpsw-switchdev.o</div><div class='ctx'> obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c<br/>index c51e2af91f69..35fceba01ea4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/am65-cpsw-ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-ethtool.c</a></div><div class='hunk'>@@ -11,6 +11,7 @@</div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "am65-cpsw-nuss.h"</div><div class='add'>+#include "am65-cpsw-qos.h"</div><div class='ctx'> #include "cpsw_ale.h"</div><div class='ctx'> #include "am65-cpts.h"</div><div class='ctx'> </div><div class='hunk'>@@ -662,6 +663,34 @@ static void am65_cpsw_get_ethtool_stats(struct net_device *ndev,</div><div class='ctx'> 					hw_stats[i].offset);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void am65_cpsw_get_eth_mac_stats(struct net_device *ndev,</div><div class='add'>+					struct ethtool_eth_mac_stats *s)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	struct am65_cpsw_stats_regs __iomem *stats;</div><div class='add'>+</div><div class='add'>+	stats = port-&gt;stat_base;</div><div class='add'>+</div><div class='add'>+	if (s-&gt;src != ETHTOOL_MAC_STATS_SRC_AGGREGATE)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	s-&gt;FramesTransmittedOK = readl_relaxed(&amp;stats-&gt;tx_good_frames);</div><div class='add'>+	s-&gt;SingleCollisionFrames = readl_relaxed(&amp;stats-&gt;tx_single_coll_frames);</div><div class='add'>+	s-&gt;MultipleCollisionFrames = readl_relaxed(&amp;stats-&gt;tx_mult_coll_frames);</div><div class='add'>+	s-&gt;FramesReceivedOK = readl_relaxed(&amp;stats-&gt;rx_good_frames);</div><div class='add'>+	s-&gt;FrameCheckSequenceErrors = readl_relaxed(&amp;stats-&gt;rx_crc_errors);</div><div class='add'>+	s-&gt;AlignmentErrors = readl_relaxed(&amp;stats-&gt;rx_align_code_errors);</div><div class='add'>+	s-&gt;OctetsTransmittedOK = readl_relaxed(&amp;stats-&gt;tx_octets);</div><div class='add'>+	s-&gt;FramesWithDeferredXmissions = readl_relaxed(&amp;stats-&gt;tx_deferred_frames);</div><div class='add'>+	s-&gt;LateCollisions = readl_relaxed(&amp;stats-&gt;tx_late_collisions);</div><div class='add'>+	s-&gt;CarrierSenseErrors = readl_relaxed(&amp;stats-&gt;tx_carrier_sense_errors);</div><div class='add'>+	s-&gt;OctetsReceivedOK = readl_relaxed(&amp;stats-&gt;rx_octets);</div><div class='add'>+	s-&gt;MulticastFramesXmittedOK = readl_relaxed(&amp;stats-&gt;tx_multicast_frames);</div><div class='add'>+	s-&gt;BroadcastFramesXmittedOK = readl_relaxed(&amp;stats-&gt;tx_broadcast_frames);</div><div class='add'>+	s-&gt;MulticastFramesReceivedOK = readl_relaxed(&amp;stats-&gt;rx_multicast_frames);</div><div class='add'>+	s-&gt;BroadcastFramesReceivedOK = readl_relaxed(&amp;stats-&gt;rx_broadcast_frames);</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static int am65_cpsw_get_ethtool_ts_info(struct net_device *ndev,</div><div class='ctx'> 					 struct ethtool_ts_info *info)</div><div class='ctx'> {</div><div class='hunk'>@@ -715,6 +744,240 @@ static int am65_cpsw_set_ethtool_priv_flags(struct net_device *ndev, u32 flags)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void am65_cpsw_port_iet_rx_enable(struct am65_cpsw_port *port, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_CTL);</div><div class='add'>+	if (enable)</div><div class='add'>+		val |= AM65_CPSW_PN_CTL_IET_PORT_EN;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~AM65_CPSW_PN_CTL_IET_PORT_EN;</div><div class='add'>+</div><div class='add'>+	writel(val, port-&gt;port_base + AM65_CPSW_PN_REG_CTL);</div><div class='add'>+	am65_cpsw_iet_common_enable(port-&gt;common);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_port_iet_tx_enable(struct am65_cpsw_port *port, bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+	if (enable)</div><div class='add'>+		val |= AM65_CPSW_PN_IET_MAC_PENABLE;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~AM65_CPSW_PN_IET_MAC_PENABLE;</div><div class='add'>+</div><div class='add'>+	writel(val, port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_get_mm(struct net_device *ndev, struct ethtool_mm_state *state)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	struct am65_cpsw_ndev_priv *priv = netdev_priv(ndev);</div><div class='add'>+	u32 port_ctrl, iet_ctrl, iet_status;</div><div class='add'>+	u32 add_frag_size;</div><div class='add'>+</div><div class='add'>+	if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;priv-&gt;mm_lock);</div><div class='add'>+</div><div class='add'>+	iet_ctrl = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+	port_ctrl = readl(port-&gt;port_base + AM65_CPSW_PN_REG_CTL);</div><div class='add'>+</div><div class='add'>+	state-&gt;tx_enabled = !!(iet_ctrl &amp; AM65_CPSW_PN_IET_MAC_PENABLE);</div><div class='add'>+	state-&gt;pmac_enabled = !!(port_ctrl &amp; AM65_CPSW_PN_CTL_IET_PORT_EN);</div><div class='add'>+</div><div class='add'>+	iet_status = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_STATUS);</div><div class='add'>+</div><div class='add'>+	if (iet_ctrl &amp; AM65_CPSW_PN_IET_MAC_DISABLEVERIFY)</div><div class='add'>+		state-&gt;verify_status = ETHTOOL_MM_VERIFY_STATUS_DISABLED;</div><div class='add'>+	else if (iet_status &amp; AM65_CPSW_PN_MAC_VERIFIED)</div><div class='add'>+		state-&gt;verify_status = ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED;</div><div class='add'>+	else if (iet_status &amp; AM65_CPSW_PN_MAC_VERIFY_FAIL)</div><div class='add'>+		state-&gt;verify_status = ETHTOOL_MM_VERIFY_STATUS_FAILED;</div><div class='add'>+	else</div><div class='add'>+		state-&gt;verify_status = ETHTOOL_MM_VERIFY_STATUS_UNKNOWN;</div><div class='add'>+</div><div class='add'>+	add_frag_size = AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(iet_ctrl);</div><div class='add'>+	state-&gt;tx_min_frag_size = ethtool_mm_frag_size_add_to_min(add_frag_size);</div><div class='add'>+</div><div class='add'>+	/* Errata i2208: RX min fragment size cannot be less than 124 */</div><div class='add'>+	state-&gt;rx_min_frag_size = 124;</div><div class='add'>+</div><div class='add'>+	/* FPE active if common tx_enabled and verification success or disabled (forced) */</div><div class='add'>+	state-&gt;tx_active = state-&gt;tx_enabled &amp;&amp;</div><div class='add'>+			   (state-&gt;verify_status == ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED ||</div><div class='add'>+			    state-&gt;verify_status == ETHTOOL_MM_VERIFY_STATUS_DISABLED);</div><div class='add'>+	state-&gt;verify_enabled = !(iet_ctrl &amp; AM65_CPSW_PN_IET_MAC_DISABLEVERIFY);</div><div class='add'>+</div><div class='add'>+	state-&gt;verify_time = port-&gt;qos.iet.verify_time_ms;</div><div class='add'>+</div><div class='add'>+	/* 802.3-2018 clause 30.14.1.6, says that the aMACMergeVerifyTime</div><div class='add'>+	 * variable has a range between 1 and 128 ms inclusive. Limit to that.</div><div class='add'>+	 */</div><div class='add'>+	state-&gt;max_verify_time = 128;</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;mm_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	struct am65_cpsw_ndev_priv *priv = netdev_priv(ndev);</div><div class='add'>+	struct am65_cpsw_iet *iet = &amp;port-&gt;qos.iet;</div><div class='add'>+	u32 val, add_frag_size;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	err = ethtool_mm_frag_size_min_to_add(cfg-&gt;tx_min_frag_size, &amp;add_frag_size, extack);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;priv-&gt;mm_lock);</div><div class='add'>+</div><div class='add'>+	if (cfg-&gt;pmac_enabled) {</div><div class='add'>+		/* change TX &amp; RX FIFO MAX_BLKS as per TRM recommendation */</div><div class='add'>+		if (!iet-&gt;original_max_blks)</div><div class='add'>+			iet-&gt;original_max_blks = readl(port-&gt;port_base + AM65_CPSW_PN_REG_MAX_BLKS);</div><div class='add'>+</div><div class='add'>+		writel(AM65_CPSW_PN_TX_RX_MAX_BLKS_IET,</div><div class='add'>+		       port-&gt;port_base + AM65_CPSW_PN_REG_MAX_BLKS);</div><div class='add'>+	} else if (iet-&gt;original_max_blks) {</div><div class='add'>+		/* restore RX &amp; TX FIFO MAX_BLKS */</div><div class='add'>+		writel(iet-&gt;original_max_blks,</div><div class='add'>+		       port-&gt;port_base + AM65_CPSW_PN_REG_MAX_BLKS);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	am65_cpsw_port_iet_rx_enable(port, cfg-&gt;pmac_enabled);</div><div class='add'>+	am65_cpsw_port_iet_tx_enable(port, cfg-&gt;tx_enabled);</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+	if (cfg-&gt;verify_enabled) {</div><div class='add'>+		val &amp;= ~AM65_CPSW_PN_IET_MAC_DISABLEVERIFY;</div><div class='add'>+		/* Reset Verify state machine. Verification won't start here.</div><div class='add'>+		 * Verification will be done once link-up.</div><div class='add'>+		 */</div><div class='add'>+		val |= AM65_CPSW_PN_IET_MAC_LINKFAIL;</div><div class='add'>+	} else {</div><div class='add'>+		val |= AM65_CPSW_PN_IET_MAC_DISABLEVERIFY;</div><div class='add'>+		/* Clear LINKFAIL to allow verify/response packets */</div><div class='add'>+		val &amp;= ~AM65_CPSW_PN_IET_MAC_LINKFAIL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val &amp;= ~AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK;</div><div class='add'>+	val |= AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(add_frag_size);</div><div class='add'>+	writel(val, port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+</div><div class='add'>+	/* verify_timeout_count can only be set at valid link */</div><div class='add'>+	port-&gt;qos.iet.verify_time_ms = cfg-&gt;verify_time;</div><div class='add'>+</div><div class='add'>+	/* enable/disable preemption based on link status */</div><div class='add'>+	am65_cpsw_iet_commit_preemptible_tcs(port);</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;mm_lock);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_get_mm_stats(struct net_device *ndev,</div><div class='add'>+				   struct ethtool_mm_stats *s)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	void __iomem *base = port-&gt;stat_base;</div><div class='add'>+</div><div class='add'>+	s-&gt;MACMergeFrameAssOkCount = readl(base + AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK);</div><div class='add'>+	s-&gt;MACMergeFrameAssErrorCount = readl(base + AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR);</div><div class='add'>+	s-&gt;MACMergeFrameSmdErrorCount = readl(base + AM65_CPSW_STATN_IET_RX_SMD_ERROR);</div><div class='add'>+	/* CPSW Functional Spec states:</div><div class='add'>+	 * "The IET stat aMACMergeFragCountRx is derived by adding the</div><div class='add'>+	 *  Receive Assembly Error count to this value. i.e. AM65_CPSW_STATN_IET_RX_FRAG"</div><div class='add'>+	 */</div><div class='add'>+	s-&gt;MACMergeFragCountRx = readl(base + AM65_CPSW_STATN_IET_RX_FRAG) + s-&gt;MACMergeFrameAssErrorCount;</div><div class='add'>+	s-&gt;MACMergeFragCountTx = readl(base + AM65_CPSW_STATN_IET_TX_FRAG);</div><div class='add'>+	s-&gt;MACMergeHoldCount = readl(base + AM65_CPSW_STATN_IET_TX_HOLD);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,</div><div class='add'>+				  struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+				  struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chn;</div><div class='add'>+</div><div class='add'>+	tx_chn = &amp;common-&gt;tx_chns[0];</div><div class='add'>+</div><div class='add'>+	coal-&gt;rx_coalesce_usecs = common-&gt;rx_pace_timeout / 1000;</div><div class='add'>+	coal-&gt;tx_coalesce_usecs = tx_chn-&gt;tx_pace_timeout / 1000;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_get_per_queue_coalesce(struct net_device *ndev, u32 queue,</div><div class='add'>+					    struct ethtool_coalesce *coal)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chn;</div><div class='add'>+</div><div class='add'>+	if (queue &gt;= AM65_CPSW_MAX_TX_QUEUES)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	tx_chn = &amp;common-&gt;tx_chns[queue];</div><div class='add'>+</div><div class='add'>+	coal-&gt;tx_coalesce_usecs = tx_chn-&gt;tx_pace_timeout / 1000;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,</div><div class='add'>+				  struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+				  struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chn;</div><div class='add'>+</div><div class='add'>+	tx_chn = &amp;common-&gt;tx_chns[0];</div><div class='add'>+</div><div class='add'>+	if (coal-&gt;rx_coalesce_usecs &amp;&amp; coal-&gt;rx_coalesce_usecs &lt; 20)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (coal-&gt;tx_coalesce_usecs &amp;&amp; coal-&gt;tx_coalesce_usecs &lt; 20)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	common-&gt;rx_pace_timeout = coal-&gt;rx_coalesce_usecs * 1000;</div><div class='add'>+	tx_chn-&gt;tx_pace_timeout = coal-&gt;tx_coalesce_usecs * 1000;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_set_per_queue_coalesce(struct net_device *ndev, u32 queue,</div><div class='add'>+					    struct ethtool_coalesce *coal)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chn;</div><div class='add'>+</div><div class='add'>+	if (queue &gt;= AM65_CPSW_MAX_TX_QUEUES)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	tx_chn = &amp;common-&gt;tx_chns[queue];</div><div class='add'>+</div><div class='add'>+	if (coal-&gt;tx_coalesce_usecs &amp;&amp; coal-&gt;tx_coalesce_usecs &lt; 20) {</div><div class='add'>+		dev_info(common-&gt;dev, "defaulting to min value of 20us for tx-usecs for tx-%u\n",</div><div class='add'>+			 queue);</div><div class='add'>+		coal-&gt;tx_coalesce_usecs = 20;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tx_chn-&gt;tx_pace_timeout = coal-&gt;tx_coalesce_usecs * 1000;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {</div><div class='ctx'> 	.begin			= am65_cpsw_ethtool_op_begin,</div><div class='ctx'> 	.complete		= am65_cpsw_ethtool_op_complete,</div><div class='hunk'>@@ -729,9 +992,15 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {</div><div class='ctx'> 	.get_sset_count		= am65_cpsw_get_sset_count,</div><div class='ctx'> 	.get_strings		= am65_cpsw_get_strings,</div><div class='ctx'> 	.get_ethtool_stats	= am65_cpsw_get_ethtool_stats,</div><div class='add'>+	.get_eth_mac_stats	= am65_cpsw_get_eth_mac_stats,</div><div class='ctx'> 	.get_ts_info		= am65_cpsw_get_ethtool_ts_info,</div><div class='ctx'> 	.get_priv_flags		= am65_cpsw_get_ethtool_priv_flags,</div><div class='ctx'> 	.set_priv_flags		= am65_cpsw_set_ethtool_priv_flags,</div><div class='add'>+	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,</div><div class='add'>+	.get_coalesce           = am65_cpsw_get_coalesce,</div><div class='add'>+	.set_coalesce           = am65_cpsw_set_coalesce,</div><div class='add'>+	.get_per_queue_coalesce = am65_cpsw_get_per_queue_coalesce,</div><div class='add'>+	.set_per_queue_coalesce = am65_cpsw_set_per_queue_coalesce,</div><div class='ctx'> </div><div class='ctx'> 	.get_link		= ethtool_op_get_link,</div><div class='ctx'> 	.get_link_ksettings	= am65_cpsw_get_link_ksettings,</div><div class='hunk'>@@ -743,4 +1012,7 @@ const struct ethtool_ops am65_cpsw_ethtool_ops_slave = {</div><div class='ctx'> 	.get_eee		= am65_cpsw_get_eee,</div><div class='ctx'> 	.set_eee		= am65_cpsw_set_eee,</div><div class='ctx'> 	.nway_reset		= am65_cpsw_nway_reset,</div><div class='add'>+	.get_mm			= am65_cpsw_get_mm,</div><div class='add'>+	.set_mm			= am65_cpsw_set_mm,</div><div class='add'>+	.get_mm_stats		= am65_cpsw_get_mm_stats,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c<br/>index ece9f8df98ae..9d2f4ac783e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-nuss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/am65-cpsw-nuss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-nuss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-nuss.c</a></div><div class='hunk'>@@ -56,7 +56,7 @@</div><div class='ctx'> #define AM65_CPSW_MAX_PORTS	8</div><div class='ctx'> </div><div class='ctx'> #define AM65_CPSW_MIN_PACKET_SIZE	VLAN_ETH_ZLEN</div><div class='del'>-#define AM65_CPSW_MAX_PACKET_SIZE	(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)</div><div class='add'>+#define AM65_CPSW_MAX_PACKET_SIZE	2024</div><div class='ctx'> </div><div class='ctx'> #define AM65_CPSW_REG_CTL		0x004</div><div class='ctx'> #define AM65_CPSW_REG_STAT_PORT_EN	0x014</div><div class='hunk'>@@ -136,6 +136,8 @@</div><div class='ctx'> 			 NETIF_MSG_IFUP	| NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \</div><div class='ctx'> 			 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)</div><div class='ctx'> </div><div class='add'>+#define AM65_CPSW_DEFAULT_TX_CHNS	8</div><div class='add'>+</div><div class='ctx'> static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,</div><div class='ctx'> 				      const u8 *dev_addr)</div><div class='ctx'> {</div><div class='hunk'>@@ -367,10 +369,81 @@ static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common);</div><div class='ctx'> static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port);</div><div class='ctx'> static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port);</div><div class='ctx'> </div><div class='add'>+static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_rx_chn *rx_chn = data;</div><div class='add'>+	struct cppi5_host_desc_t *desc_rx;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	dma_addr_t buf_dma;</div><div class='add'>+	u32 buf_dma_len;</div><div class='add'>+	void **swdata;</div><div class='add'>+</div><div class='add'>+	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn-&gt;desc_pool, desc_dma);</div><div class='add'>+	swdata = cppi5_hdesc_get_swdata(desc_rx);</div><div class='add'>+	skb = *swdata;</div><div class='add'>+	cppi5_hdesc_get_obuf(desc_rx, &amp;buf_dma, &amp;buf_dma_len);</div><div class='add'>+	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn-&gt;rx_chn, &amp;buf_dma);</div><div class='add'>+</div><div class='add'>+	dma_unmap_single(rx_chn-&gt;dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);</div><div class='add'>+	k3_cppi_desc_pool_free(rx_chn-&gt;desc_pool, desc_rx);</div><div class='add'>+</div><div class='add'>+	dev_kfree_skb_any(skb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,</div><div class='add'>+				     struct cppi5_host_desc_t *desc)</div><div class='add'>+{</div><div class='add'>+	struct cppi5_host_desc_t *first_desc, *next_desc;</div><div class='add'>+	dma_addr_t buf_dma, next_desc_dma;</div><div class='add'>+	u32 buf_dma_len;</div><div class='add'>+</div><div class='add'>+	first_desc = desc;</div><div class='add'>+	next_desc = first_desc;</div><div class='add'>+</div><div class='add'>+	cppi5_hdesc_get_obuf(first_desc, &amp;buf_dma, &amp;buf_dma_len);</div><div class='add'>+	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;buf_dma);</div><div class='add'>+</div><div class='add'>+	dma_unmap_single(tx_chn-&gt;dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE);</div><div class='add'>+</div><div class='add'>+	next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);</div><div class='add'>+	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;next_desc_dma);</div><div class='add'>+	while (next_desc_dma) {</div><div class='add'>+		next_desc = k3_cppi_desc_pool_dma2virt(tx_chn-&gt;desc_pool,</div><div class='add'>+						       next_desc_dma);</div><div class='add'>+		cppi5_hdesc_get_obuf(next_desc, &amp;buf_dma, &amp;buf_dma_len);</div><div class='add'>+		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;buf_dma);</div><div class='add'>+</div><div class='add'>+		dma_unmap_page(tx_chn-&gt;dma_dev, buf_dma, buf_dma_len,</div><div class='add'>+			       DMA_TO_DEVICE);</div><div class='add'>+</div><div class='add'>+		next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);</div><div class='add'>+		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;next_desc_dma);</div><div class='add'>+</div><div class='add'>+		k3_cppi_desc_pool_free(tx_chn-&gt;desc_pool, next_desc);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	k3_cppi_desc_pool_free(tx_chn-&gt;desc_pool, first_desc);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chn = data;</div><div class='add'>+	struct cppi5_host_desc_t *desc_tx;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	void **swdata;</div><div class='add'>+</div><div class='add'>+	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn-&gt;desc_pool, desc_dma);</div><div class='add'>+	swdata = cppi5_hdesc_get_swdata(desc_tx);</div><div class='add'>+	skb = *(swdata);</div><div class='add'>+	am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);</div><div class='add'>+</div><div class='add'>+	dev_kfree_skb_any(skb);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)</div><div class='ctx'> {</div><div class='ctx'> 	struct am65_cpsw_host *host_p = am65_common_get_host(common);</div><div class='del'>-	int port_idx, i, ret;</div><div class='add'>+	int port_idx, i, ret, tx;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	u32 val, port_mask;</div><div class='ctx'> </div><div class='hunk'>@@ -437,8 +510,12 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)</div><div class='ctx'> 						  AM65_CPSW_MAX_PACKET_SIZE,</div><div class='ctx'> 						  GFP_KERNEL);</div><div class='ctx'> 		if (!skb) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='ctx'> 			dev_err(common-&gt;dev, "cannot allocate skb\n");</div><div class='del'>-			return -ENOMEM;</div><div class='add'>+			if (i)</div><div class='add'>+				goto fail_rx;</div><div class='add'>+</div><div class='add'>+			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		ret = am65_cpsw_nuss_rx_push(common, skb);</div><div class='hunk'>@@ -447,17 +524,28 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)</div><div class='ctx'> 				"cannot submit skb to channel rx, error %d\n",</div><div class='ctx'> 				ret);</div><div class='ctx'> 			kfree_skb(skb);</div><div class='add'>+			if (i)</div><div class='add'>+				goto fail_rx;</div><div class='add'>+</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='del'>-		kmemleak_not_leak(skb);</div><div class='ctx'> 	}</div><div class='del'>-	k3_udma_glue_enable_rx_chn(common-&gt;rx_chns.rx_chn);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; common-&gt;tx_ch_num; i++) {</div><div class='del'>-		ret = k3_udma_glue_enable_tx_chn(common-&gt;tx_chns[i].tx_chn);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-		napi_enable(&amp;common-&gt;tx_chns[i].napi_tx);</div><div class='add'>+	ret = k3_udma_glue_enable_rx_chn(common-&gt;rx_chns.rx_chn);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(common-&gt;dev, "couldn't enable rx chn: %d\n", ret);</div><div class='add'>+		goto fail_rx;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (tx = 0; tx &lt; common-&gt;tx_ch_num; tx++) {</div><div class='add'>+		ret = k3_udma_glue_enable_tx_chn(common-&gt;tx_chns[tx].tx_chn);</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(common-&gt;dev, "couldn't enable tx chn %d: %d\n",</div><div class='add'>+				tx, ret);</div><div class='add'>+			tx--;</div><div class='add'>+			goto fail_tx;</div><div class='add'>+		}</div><div class='add'>+		napi_enable(&amp;common-&gt;tx_chns[tx].napi_tx);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	napi_enable(&amp;common-&gt;napi_rx);</div><div class='hunk'>@@ -468,10 +556,22 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common)</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(common-&gt;dev, "cpsw_nuss started\n");</div><div class='ctx'> 	return 0;</div><div class='del'>-}</div><div class='ctx'> </div><div class='del'>-static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma);</div><div class='del'>-static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma);</div><div class='add'>+fail_tx:</div><div class='add'>+	while (tx &gt;= 0) {</div><div class='add'>+		napi_disable(&amp;common-&gt;tx_chns[tx].napi_tx);</div><div class='add'>+		k3_udma_glue_disable_tx_chn(common-&gt;tx_chns[tx].tx_chn);</div><div class='add'>+		tx--;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	k3_udma_glue_disable_rx_chn(common-&gt;rx_chns.rx_chn);</div><div class='add'>+</div><div class='add'>+fail_rx:</div><div class='add'>+	k3_udma_glue_reset_rx_chn(common-&gt;rx_chns.rx_chn, 0,</div><div class='add'>+				  &amp;common-&gt;rx_chns,</div><div class='add'>+				  am65_cpsw_nuss_rx_cleanup, 0);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)</div><div class='ctx'> {</div><div class='hunk'>@@ -496,8 +596,10 @@ static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)</div><div class='ctx'> 					msecs_to_jiffies(1000));</div><div class='ctx'> 	if (!i)</div><div class='ctx'> 		dev_err(common-&gt;dev, "tx timeout\n");</div><div class='del'>-	for (i = 0; i &lt; common-&gt;tx_ch_num; i++)</div><div class='add'>+	for (i = 0; i &lt; common-&gt;tx_ch_num; i++) {</div><div class='ctx'> 		napi_disable(&amp;common-&gt;tx_chns[i].napi_tx);</div><div class='add'>+		hrtimer_cancel(&amp;common-&gt;tx_chns[i].tx_hrtimer);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; common-&gt;tx_ch_num; i++) {</div><div class='ctx'> 		k3_udma_glue_reset_tx_chn(common-&gt;tx_chns[i].tx_chn,</div><div class='hunk'>@@ -516,6 +618,7 @@ static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	napi_disable(&amp;common-&gt;napi_rx);</div><div class='add'>+	hrtimer_cancel(&amp;common-&gt;rx_hrtimer);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; AM65_CPSW_MAX_RX_FLOWS; i++)</div><div class='ctx'> 		k3_udma_glue_reset_rx_chn(common-&gt;rx_chns.rx_chn, i,</div><div class='hunk'>@@ -646,27 +749,6 @@ runtime_put:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)</div><div class='del'>-{</div><div class='del'>-	struct am65_cpsw_rx_chn *rx_chn = data;</div><div class='del'>-	struct cppi5_host_desc_t *desc_rx;</div><div class='del'>-	struct sk_buff *skb;</div><div class='del'>-	dma_addr_t buf_dma;</div><div class='del'>-	u32 buf_dma_len;</div><div class='del'>-	void **swdata;</div><div class='del'>-</div><div class='del'>-	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn-&gt;desc_pool, desc_dma);</div><div class='del'>-	swdata = cppi5_hdesc_get_swdata(desc_rx);</div><div class='del'>-	skb = *swdata;</div><div class='del'>-	cppi5_hdesc_get_obuf(desc_rx, &amp;buf_dma, &amp;buf_dma_len);</div><div class='del'>-	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn-&gt;rx_chn, &amp;buf_dma);</div><div class='del'>-</div><div class='del'>-	dma_unmap_single(rx_chn-&gt;dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);</div><div class='del'>-	k3_cppi_desc_pool_free(rx_chn-&gt;desc_pool, desc_rx);</div><div class='del'>-</div><div class='del'>-	dev_kfree_skb_any(skb);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)</div><div class='ctx'> {</div><div class='ctx'> 	struct skb_shared_hwtstamps *ssh;</div><div class='hunk'>@@ -806,6 +888,15 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_common *common =</div><div class='add'>+			container_of(timer, struct am65_cpsw_common, rx_hrtimer);</div><div class='add'>+</div><div class='add'>+	enable_irq(common-&gt;rx_chns.irq);</div><div class='add'>+	return HRTIMER_NORESTART;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx);</div><div class='hunk'>@@ -833,63 +924,19 @@ static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)</div><div class='ctx'> 	if (num_rx &lt; budget &amp;&amp; napi_complete_done(napi_rx, num_rx)) {</div><div class='ctx'> 		if (common-&gt;rx_irq_disabled) {</div><div class='ctx'> 			common-&gt;rx_irq_disabled = false;</div><div class='del'>-			enable_irq(common-&gt;rx_chns.irq);</div><div class='add'>+			if (unlikely(common-&gt;rx_pace_timeout)) {</div><div class='add'>+				hrtimer_start(&amp;common-&gt;rx_hrtimer,</div><div class='add'>+					      ns_to_ktime(common-&gt;rx_pace_timeout),</div><div class='add'>+					      HRTIMER_MODE_REL_PINNED);</div><div class='add'>+			} else {</div><div class='add'>+				enable_irq(common-&gt;rx_chns.irq);</div><div class='add'>+			}</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return num_rx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,</div><div class='del'>-				     struct cppi5_host_desc_t *desc)</div><div class='del'>-{</div><div class='del'>-	struct cppi5_host_desc_t *first_desc, *next_desc;</div><div class='del'>-	dma_addr_t buf_dma, next_desc_dma;</div><div class='del'>-	u32 buf_dma_len;</div><div class='del'>-</div><div class='del'>-	first_desc = desc;</div><div class='del'>-	next_desc = first_desc;</div><div class='del'>-</div><div class='del'>-	cppi5_hdesc_get_obuf(first_desc, &amp;buf_dma, &amp;buf_dma_len);</div><div class='del'>-	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;buf_dma);</div><div class='del'>-</div><div class='del'>-	dma_unmap_single(tx_chn-&gt;dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE);</div><div class='del'>-</div><div class='del'>-	next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);</div><div class='del'>-	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;next_desc_dma);</div><div class='del'>-	while (next_desc_dma) {</div><div class='del'>-		next_desc = k3_cppi_desc_pool_dma2virt(tx_chn-&gt;desc_pool,</div><div class='del'>-						       next_desc_dma);</div><div class='del'>-		cppi5_hdesc_get_obuf(next_desc, &amp;buf_dma, &amp;buf_dma_len);</div><div class='del'>-		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;buf_dma);</div><div class='del'>-</div><div class='del'>-		dma_unmap_page(tx_chn-&gt;dma_dev, buf_dma, buf_dma_len,</div><div class='del'>-			       DMA_TO_DEVICE);</div><div class='del'>-</div><div class='del'>-		next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);</div><div class='del'>-		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn-&gt;tx_chn, &amp;next_desc_dma);</div><div class='del'>-</div><div class='del'>-		k3_cppi_desc_pool_free(tx_chn-&gt;desc_pool, next_desc);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	k3_cppi_desc_pool_free(tx_chn-&gt;desc_pool, first_desc);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)</div><div class='del'>-{</div><div class='del'>-	struct am65_cpsw_tx_chn *tx_chn = data;</div><div class='del'>-	struct cppi5_host_desc_t *desc_tx;</div><div class='del'>-	struct sk_buff *skb;</div><div class='del'>-	void **swdata;</div><div class='del'>-</div><div class='del'>-	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn-&gt;desc_pool, desc_dma);</div><div class='del'>-	swdata = cppi5_hdesc_get_swdata(desc_tx);</div><div class='del'>-	skb = *(swdata);</div><div class='del'>-	am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);</div><div class='del'>-</div><div class='del'>-	dev_kfree_skb_any(skb);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static struct sk_buff *</div><div class='ctx'> am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn,</div><div class='ctx'> 			       dma_addr_t desc_dma)</div><div class='hunk'>@@ -939,7 +986,7 @@ static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_d</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,</div><div class='del'>-					   int chn, unsigned int budget)</div><div class='add'>+					   int chn, unsigned int budget, bool *tdown)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = common-&gt;dev;</div><div class='ctx'> 	struct am65_cpsw_tx_chn *tx_chn;</div><div class='hunk'>@@ -962,6 +1009,7 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,</div><div class='ctx'> 		if (cppi5_desc_is_tdcm(desc_dma)) {</div><div class='ctx'> 			if (atomic_dec_and_test(&amp;common-&gt;tdown_cnt))</div><div class='ctx'> 				complete(&amp;common-&gt;tdown_complete);</div><div class='add'>+			*tdown = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -984,7 +1032,7 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,</div><div class='del'>-					      int chn, unsigned int budget)</div><div class='add'>+					      int chn, unsigned int budget, bool *tdown)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = common-&gt;dev;</div><div class='ctx'> 	struct am65_cpsw_tx_chn *tx_chn;</div><div class='hunk'>@@ -1005,6 +1053,7 @@ static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,</div><div class='ctx'> 		if (cppi5_desc_is_tdcm(desc_dma)) {</div><div class='ctx'> 			if (atomic_dec_and_test(&amp;common-&gt;tdown_cnt))</div><div class='ctx'> 				complete(&amp;common-&gt;tdown_complete);</div><div class='add'>+			*tdown = true;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1030,21 +1079,40 @@ static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,</div><div class='ctx'> 	return num_tx;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_tx_chn *tx_chns =</div><div class='add'>+			container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer);</div><div class='add'>+</div><div class='add'>+	enable_irq(tx_chns-&gt;irq);</div><div class='add'>+	return HRTIMER_NORESTART;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);</div><div class='add'>+	bool tdown = false;</div><div class='ctx'> 	int num_tx;</div><div class='ctx'> </div><div class='ctx'> 	if (AM65_CPSW_IS_CPSW2G(tx_chn-&gt;common))</div><div class='del'>-		num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn-&gt;common, tx_chn-&gt;id, budget);</div><div class='add'>+		num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn-&gt;common, tx_chn-&gt;id,</div><div class='add'>+							    budget, &amp;tdown);</div><div class='ctx'> 	else</div><div class='del'>-		num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn-&gt;common, tx_chn-&gt;id, budget);</div><div class='add'>+		num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn-&gt;common,</div><div class='add'>+							 tx_chn-&gt;id, budget, &amp;tdown);</div><div class='ctx'> </div><div class='ctx'> 	if (num_tx &gt;= budget)</div><div class='ctx'> 		return budget;</div><div class='ctx'> </div><div class='del'>-	if (napi_complete_done(napi_tx, num_tx))</div><div class='del'>-		enable_irq(tx_chn-&gt;irq);</div><div class='add'>+	if (napi_complete_done(napi_tx, num_tx)) {</div><div class='add'>+		if (unlikely(tx_chn-&gt;tx_pace_timeout &amp;&amp; !tdown)) {</div><div class='add'>+			hrtimer_start(&amp;tx_chn-&gt;tx_hrtimer,</div><div class='add'>+				      ns_to_ktime(tx_chn-&gt;tx_pace_timeout),</div><div class='add'>+				      HRTIMER_MODE_REL_PINNED);</div><div class='add'>+		} else {</div><div class='add'>+			enable_irq(tx_chn-&gt;irq);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1676,6 +1744,8 @@ static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common)</div><div class='ctx'> </div><div class='ctx'> 		netif_napi_add_tx(common-&gt;dma_ndev, &amp;tx_chn-&gt;napi_tx,</div><div class='ctx'> 				  am65_cpsw_nuss_tx_poll);</div><div class='add'>+		hrtimer_init(&amp;tx_chn-&gt;tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);</div><div class='add'>+		tx_chn-&gt;tx_hrtimer.function = &amp;am65_cpsw_nuss_tx_timer_callback;</div><div class='ctx'> </div><div class='ctx'> 		ret = devm_request_irq(dev, tx_chn-&gt;irq,</div><div class='ctx'> 				       am65_cpsw_nuss_tx_irq,</div><div class='hunk'>@@ -1901,6 +1971,8 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)</div><div class='ctx'> </div><div class='ctx'> 	netif_napi_add(common-&gt;dma_ndev, &amp;common-&gt;napi_rx,</div><div class='ctx'> 		       am65_cpsw_nuss_rx_poll);</div><div class='add'>+	hrtimer_init(&amp;common-&gt;rx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);</div><div class='add'>+	common-&gt;rx_hrtimer.function = &amp;am65_cpsw_nuss_rx_timer_callback;</div><div class='ctx'> </div><div class='ctx'> 	ret = devm_request_irq(dev, rx_chn-&gt;irq,</div><div class='ctx'> 			       am65_cpsw_nuss_rx_irq,</div><div class='hunk'>@@ -2098,6 +2170,9 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)</div><div class='ctx'> 				dev_err(dev, "Use random MAC address\n");</div><div class='ctx'> 			}</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		/* Reset all Queue priorities to 0 */</div><div class='add'>+		writel(0, port-&gt;port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);</div><div class='ctx'> 	}</div><div class='ctx'> 	of_node_put(node);</div><div class='ctx'> </div><div class='hunk'>@@ -2162,12 +2237,15 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)</div><div class='ctx'> 	ndev_priv = netdev_priv(port-&gt;ndev);</div><div class='ctx'> 	ndev_priv-&gt;port = port;</div><div class='ctx'> 	ndev_priv-&gt;msg_enable = AM65_CPSW_DEBUG;</div><div class='add'>+	mutex_init(&amp;ndev_priv-&gt;mm_lock);</div><div class='add'>+	port-&gt;qos.link_speed = SPEED_UNKNOWN;</div><div class='ctx'> 	SET_NETDEV_DEV(port-&gt;ndev, dev);</div><div class='ctx'> </div><div class='ctx'> 	eth_hw_addr_set(port-&gt;ndev, port-&gt;slave.mac_addr);</div><div class='ctx'> </div><div class='ctx'> 	port-&gt;ndev-&gt;min_mtu = AM65_CPSW_MIN_PACKET_SIZE;</div><div class='del'>-	port-&gt;ndev-&gt;max_mtu = AM65_CPSW_MAX_PACKET_SIZE;</div><div class='add'>+	port-&gt;ndev-&gt;max_mtu = AM65_CPSW_MAX_PACKET_SIZE -</div><div class='add'>+			      (VLAN_ETH_HLEN + ETH_FCS_LEN);</div><div class='ctx'> 	port-&gt;ndev-&gt;hw_features = NETIF_F_SG |</div><div class='ctx'> 				  NETIF_F_RXCSUM |</div><div class='ctx'> 				  NETIF_F_HW_CSUM |</div><div class='hunk'>@@ -2897,7 +2975,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	common-&gt;rx_flow_id_base = -1;</div><div class='ctx'> 	init_completion(&amp;common-&gt;tdown_complete);</div><div class='del'>-	common-&gt;tx_ch_num = 1;</div><div class='add'>+	common-&gt;tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS;</div><div class='ctx'> 	common-&gt;pf_p0_rx_ptype_rrobin = false;</div><div class='ctx'> 	common-&gt;default_vlan = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -2999,7 +3077,7 @@ err_pm_clear:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int am65_cpsw_nuss_remove(struct platform_device *pdev)</div><div class='add'>+static void am65_cpsw_nuss_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device *dev = &amp;pdev-&gt;dev;</div><div class='ctx'> 	struct am65_cpsw_common *common;</div><div class='hunk'>@@ -3008,8 +3086,14 @@ static int am65_cpsw_nuss_remove(struct platform_device *pdev)</div><div class='ctx'> 	common = dev_get_drvdata(dev);</div><div class='ctx'> </div><div class='ctx'> 	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		/* Note, if this error path is taken, we're leaking some</div><div class='add'>+		 * resources.</div><div class='add'>+		 */</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to resume device (%pe)\n",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	am65_cpsw_unregister_devlink(common);</div><div class='ctx'> 	am65_cpsw_unregister_notifiers(common);</div><div class='hunk'>@@ -3027,7 +3111,6 @@ static int am65_cpsw_nuss_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_nuss_suspend(struct device *dev)</div><div class='hunk'>@@ -3127,7 +3210,7 @@ static struct platform_driver am65_cpsw_nuss_driver = {</div><div class='ctx'> 		.pm = &amp;am65_cpsw_nuss_dev_pm_ops,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = am65_cpsw_nuss_probe,</div><div class='del'>-	.remove = am65_cpsw_nuss_remove,</div><div class='add'>+	.remove_new = am65_cpsw_nuss_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(am65_cpsw_nuss_driver);</div><div class='head'>diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h<br/>index f3dad2ab9828..7da0492dc091 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-nuss.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/am65-cpsw-nuss.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-nuss.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-nuss.h</a></div><div class='hunk'>@@ -75,6 +75,8 @@ struct am65_cpsw_tx_chn {</div><div class='ctx'> 	struct k3_cppi_desc_pool *desc_pool;</div><div class='ctx'> 	struct k3_udma_glue_tx_channel *tx_chn;</div><div class='ctx'> 	spinlock_t lock; /* protect TX rings in multi-port mode */</div><div class='add'>+	struct hrtimer tx_hrtimer;</div><div class='add'>+	unsigned long tx_pace_timeout;</div><div class='ctx'> 	int irq;</div><div class='ctx'> 	u32 id;</div><div class='ctx'> 	u32 descs_num;</div><div class='hunk'>@@ -138,6 +140,8 @@ struct am65_cpsw_common {</div><div class='ctx'> 	struct napi_struct	napi_rx;</div><div class='ctx'> </div><div class='ctx'> 	bool			rx_irq_disabled;</div><div class='add'>+	struct hrtimer		rx_hrtimer;</div><div class='add'>+	unsigned long		rx_pace_timeout;</div><div class='ctx'> </div><div class='ctx'> 	u32			nuss_ver;</div><div class='ctx'> 	u32			cpsw_ver;</div><div class='hunk'>@@ -145,6 +149,7 @@ struct am65_cpsw_common {</div><div class='ctx'> 	bool			pf_p0_rx_ptype_rrobin;</div><div class='ctx'> 	struct am65_cpts	*cpts;</div><div class='ctx'> 	int			est_enabled;</div><div class='add'>+	bool			iet_enabled;</div><div class='ctx'> </div><div class='ctx'> 	bool		is_emac_mode;</div><div class='ctx'> 	u16			br_members;</div><div class='hunk'>@@ -170,6 +175,10 @@ struct am65_cpsw_ndev_priv {</div><div class='ctx'> 	struct am65_cpsw_port	*port;</div><div class='ctx'> 	struct am65_cpsw_ndev_stats __percpu *stats;</div><div class='ctx'> 	bool offload_fwd_mark;</div><div class='add'>+	/* Serialize access to MAC Merge state between ethtool requests</div><div class='add'>+	 * and link state updates</div><div class='add'>+	 */</div><div class='add'>+	struct mutex		mm_lock;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define am65_ndev_to_priv(ndev) \</div><div class='head'>diff --git a/drivers/net/ethernet/ti/am65-cpsw-qos.c b/drivers/net/ethernet/ti/am65-cpsw-qos.c<br/>index 9ac2ff05d501..816e73a3d6e4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-qos.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/am65-cpsw-qos.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-qos.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-qos.c</a></div><div class='hunk'>@@ -4,10 +4,13 @@</div><div class='ctx'>  *</div><div class='ctx'>  * quality of service module includes:</div><div class='ctx'>  * Enhanced Scheduler Traffic (EST - P802.1Qbv/D2.2)</div><div class='add'>+ * Interspersed Express Traffic (IET - P802.3br/D2.0)</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/math.h&gt;</div><div class='ctx'> #include &lt;linux/time.h&gt;</div><div class='add'>+#include &lt;linux/units.h&gt;</div><div class='ctx'> #include &lt;net/pkt_cls.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "am65-cpsw-nuss.h"</div><div class='hunk'>@@ -15,40 +18,7 @@</div><div class='ctx'> #include "am65-cpts.h"</div><div class='ctx'> #include "cpsw_ale.h"</div><div class='ctx'> </div><div class='del'>-#define AM65_CPSW_REG_CTL			0x004</div><div class='del'>-#define AM65_CPSW_PN_REG_CTL			0x004</div><div class='del'>-#define AM65_CPSW_PN_REG_FIFO_STATUS		0x050</div><div class='del'>-#define AM65_CPSW_PN_REG_EST_CTL		0x060</div><div class='del'>-#define AM65_CPSW_PN_REG_PRI_CIR(pri)		(0x140 + 4 * (pri))</div><div class='del'>-</div><div class='del'>-/* AM65_CPSW_REG_CTL register fields */</div><div class='del'>-#define AM65_CPSW_CTL_EST_EN			BIT(18)</div><div class='del'>-</div><div class='del'>-/* AM65_CPSW_PN_REG_CTL register fields */</div><div class='del'>-#define AM65_CPSW_PN_CTL_EST_PORT_EN		BIT(17)</div><div class='del'>-</div><div class='del'>-/* AM65_CPSW_PN_REG_EST_CTL register fields */</div><div class='del'>-#define AM65_CPSW_PN_EST_ONEBUF			BIT(0)</div><div class='del'>-#define AM65_CPSW_PN_EST_BUFSEL			BIT(1)</div><div class='del'>-#define AM65_CPSW_PN_EST_TS_EN			BIT(2)</div><div class='del'>-#define AM65_CPSW_PN_EST_TS_FIRST		BIT(3)</div><div class='del'>-#define AM65_CPSW_PN_EST_ONEPRI			BIT(4)</div><div class='del'>-#define AM65_CPSW_PN_EST_TS_PRI_MSK		GENMASK(7, 5)</div><div class='del'>-</div><div class='del'>-/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */</div><div class='del'>-#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK	GENMASK(7, 0)</div><div class='del'>-#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK	GENMASK(15, 8)</div><div class='del'>-#define AM65_CPSW_PN_FST_EST_CNT_ERR		BIT(16)</div><div class='del'>-#define AM65_CPSW_PN_FST_EST_ADD_ERR		BIT(17)</div><div class='del'>-#define AM65_CPSW_PN_FST_EST_BUFACT		BIT(18)</div><div class='del'>-</div><div class='del'>-/* EST FETCH COMMAND RAM */</div><div class='del'>-#define AM65_CPSW_FETCH_RAM_CMD_NUM		0x80</div><div class='del'>-#define AM65_CPSW_FETCH_CNT_MSK			GENMASK(21, 8)</div><div class='del'>-#define AM65_CPSW_FETCH_CNT_MAX			(AM65_CPSW_FETCH_CNT_MSK &gt;&gt; 8)</div><div class='del'>-#define AM65_CPSW_FETCH_CNT_OFFSET		8</div><div class='del'>-#define AM65_CPSW_FETCH_ALLOW_MSK		GENMASK(7, 0)</div><div class='del'>-#define AM65_CPSW_FETCH_ALLOW_MAX		AM65_CPSW_FETCH_ALLOW_MSK</div><div class='add'>+#define TO_MBPS(x)	DIV_ROUND_UP((x), BYTES_PER_MBIT)</div><div class='ctx'> </div><div class='ctx'> enum timer_act {</div><div class='ctx'> 	TACT_PROG,		/* need program timer */</div><div class='hunk'>@@ -56,6 +26,412 @@ enum timer_act {</div><div class='ctx'> 	TACT_SKIP_PROG,		/* just buffer can be updated */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static void am65_cpsw_iet_change_preemptible_tcs(struct am65_cpsw_port *port, u8 preemptible_tcs);</div><div class='add'>+</div><div class='add'>+static u32</div><div class='add'>+am65_cpsw_qos_tx_rate_calc(u32 rate_mbps, unsigned long bus_freq)</div><div class='add'>+{</div><div class='add'>+	u32 ir;</div><div class='add'>+</div><div class='add'>+	bus_freq /= 1000000;</div><div class='add'>+	ir = DIV_ROUND_UP(((u64)rate_mbps * 32768),  bus_freq);</div><div class='add'>+	return ir;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_tx_pn_shaper_reset(struct am65_cpsw_port *port)</div><div class='add'>+{</div><div class='add'>+	int prio;</div><div class='add'>+</div><div class='add'>+	for (prio = 0; prio &lt; AM65_CPSW_PN_FIFO_PRIO_NUM; prio++) {</div><div class='add'>+		writel(0, port-&gt;port_base + AM65_CPSW_PN_REG_PRI_CIR(prio));</div><div class='add'>+		writel(0, port-&gt;port_base + AM65_CPSW_PN_REG_PRI_EIR(prio));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_tx_pn_shaper_apply(struct am65_cpsw_port *port)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_mqprio *p_mqprio = &amp;port-&gt;qos.mqprio;</div><div class='add'>+	struct am65_cpsw_common *common = port-&gt;common;</div><div class='add'>+	struct tc_mqprio_qopt_offload *mqprio;</div><div class='add'>+	bool enable, shaper_susp = false;</div><div class='add'>+	u32 rate_mbps;</div><div class='add'>+	int tc, prio;</div><div class='add'>+</div><div class='add'>+	mqprio = &amp;p_mqprio-&gt;mqprio_hw;</div><div class='add'>+	/* takes care of no link case as well */</div><div class='add'>+	if (p_mqprio-&gt;max_rate_total &gt; port-&gt;qos.link_speed)</div><div class='add'>+		shaper_susp = true;</div><div class='add'>+</div><div class='add'>+	am65_cpsw_tx_pn_shaper_reset(port);</div><div class='add'>+</div><div class='add'>+	enable = p_mqprio-&gt;shaper_en &amp;&amp; !shaper_susp;</div><div class='add'>+	if (!enable)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Rate limit is specified per Traffic Class but</div><div class='add'>+	 * for CPSW, rate limit can be applied per priority</div><div class='add'>+	 * at port FIFO.</div><div class='add'>+	 *</div><div class='add'>+	 * We have assigned the same priority (TCn) to all queues</div><div class='add'>+	 * of a Traffic Class so they share the same shaper</div><div class='add'>+	 * bandwidth.</div><div class='add'>+	 */</div><div class='add'>+	for (tc = 0; tc &lt; mqprio-&gt;qopt.num_tc; tc++) {</div><div class='add'>+		prio = tc;</div><div class='add'>+</div><div class='add'>+		rate_mbps = TO_MBPS(mqprio-&gt;min_rate[tc]);</div><div class='add'>+		rate_mbps = am65_cpsw_qos_tx_rate_calc(rate_mbps,</div><div class='add'>+						       common-&gt;bus_freq);</div><div class='add'>+		writel(rate_mbps,</div><div class='add'>+		       port-&gt;port_base + AM65_CPSW_PN_REG_PRI_CIR(prio));</div><div class='add'>+</div><div class='add'>+		rate_mbps = 0;</div><div class='add'>+</div><div class='add'>+		if (mqprio-&gt;max_rate[tc]) {</div><div class='add'>+			rate_mbps = mqprio-&gt;max_rate[tc] - mqprio-&gt;min_rate[tc];</div><div class='add'>+			rate_mbps = TO_MBPS(rate_mbps);</div><div class='add'>+			rate_mbps = am65_cpsw_qos_tx_rate_calc(rate_mbps,</div><div class='add'>+							       common-&gt;bus_freq);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		writel(rate_mbps,</div><div class='add'>+		       port-&gt;port_base + AM65_CPSW_PN_REG_PRI_EIR(prio));</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_mqprio_verify_shaper(struct am65_cpsw_port *port,</div><div class='add'>+					  struct tc_mqprio_qopt_offload *mqprio)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_mqprio *p_mqprio = &amp;port-&gt;qos.mqprio;</div><div class='add'>+	struct netlink_ext_ack *extack = mqprio-&gt;extack;</div><div class='add'>+	u64 min_rate_total = 0, max_rate_total = 0;</div><div class='add'>+	u32 min_rate_msk = 0, max_rate_msk = 0;</div><div class='add'>+	bool has_min_rate, has_max_rate;</div><div class='add'>+	int num_tc, i;</div><div class='add'>+</div><div class='add'>+	if (!(mqprio-&gt;flags &amp; TC_MQPRIO_F_SHAPER))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (mqprio-&gt;shaper != TC_MQPRIO_SHAPER_BW_RATE)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	has_min_rate = !!(mqprio-&gt;flags &amp; TC_MQPRIO_F_MIN_RATE);</div><div class='add'>+	has_max_rate = !!(mqprio-&gt;flags &amp; TC_MQPRIO_F_MAX_RATE);</div><div class='add'>+</div><div class='add'>+	if (!has_min_rate &amp;&amp; has_max_rate) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "min_rate is required with max_rate");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!has_min_rate)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	num_tc = mqprio-&gt;qopt.num_tc;</div><div class='add'>+</div><div class='add'>+	for (i = num_tc - 1; i &gt;= 0; i--) {</div><div class='add'>+		u32 ch_msk;</div><div class='add'>+</div><div class='add'>+		if (mqprio-&gt;min_rate[i])</div><div class='add'>+			min_rate_msk |= BIT(i);</div><div class='add'>+		min_rate_total +=  mqprio-&gt;min_rate[i];</div><div class='add'>+</div><div class='add'>+		if (has_max_rate) {</div><div class='add'>+			if (mqprio-&gt;max_rate[i])</div><div class='add'>+				max_rate_msk |= BIT(i);</div><div class='add'>+			max_rate_total +=  mqprio-&gt;max_rate[i];</div><div class='add'>+</div><div class='add'>+			if (!mqprio-&gt;min_rate[i] &amp;&amp; mqprio-&gt;max_rate[i]) {</div><div class='add'>+				NL_SET_ERR_MSG_FMT_MOD(extack,</div><div class='add'>+						       "TX tc%d rate max&gt;0 but min=0",</div><div class='add'>+						       i);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+</div><div class='add'>+			if (mqprio-&gt;max_rate[i] &amp;&amp;</div><div class='add'>+			    mqprio-&gt;max_rate[i] &lt; mqprio-&gt;min_rate[i]) {</div><div class='add'>+				NL_SET_ERR_MSG_FMT_MOD(extack,</div><div class='add'>+						       "TX tc%d rate min(%llu)&gt;max(%llu)",</div><div class='add'>+						       i, mqprio-&gt;min_rate[i],</div><div class='add'>+						       mqprio-&gt;max_rate[i]);</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ch_msk = GENMASK(num_tc - 1, i);</div><div class='add'>+		if ((min_rate_msk &amp; BIT(i)) &amp;&amp; (min_rate_msk ^ ch_msk)) {</div><div class='add'>+			NL_SET_ERR_MSG_FMT_MOD(extack,</div><div class='add'>+					       "Min rate must be set sequentially hi-&gt;lo tx_rate_msk%x",</div><div class='add'>+					       min_rate_msk);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if ((max_rate_msk &amp; BIT(i)) &amp;&amp; (max_rate_msk ^ ch_msk)) {</div><div class='add'>+			NL_SET_ERR_MSG_FMT_MOD(extack,</div><div class='add'>+					       "Max rate must be set sequentially hi-&gt;lo tx_rate_msk%x",</div><div class='add'>+					       max_rate_msk);</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	min_rate_total = TO_MBPS(min_rate_total);</div><div class='add'>+	max_rate_total = TO_MBPS(max_rate_total);</div><div class='add'>+</div><div class='add'>+	p_mqprio-&gt;shaper_en = true;</div><div class='add'>+	p_mqprio-&gt;max_rate_total = max_t(u64, min_rate_total, max_rate_total);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_reset_tc_mqprio(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	struct am65_cpsw_mqprio *p_mqprio = &amp;port-&gt;qos.mqprio;</div><div class='add'>+</div><div class='add'>+	p_mqprio-&gt;shaper_en = false;</div><div class='add'>+	p_mqprio-&gt;max_rate_total = 0;</div><div class='add'>+</div><div class='add'>+	am65_cpsw_tx_pn_shaper_reset(port);</div><div class='add'>+	netdev_reset_tc(ndev);</div><div class='add'>+</div><div class='add'>+	/* Reset all Queue priorities to 0 */</div><div class='add'>+	writel(0, port-&gt;port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);</div><div class='add'>+</div><div class='add'>+	am65_cpsw_iet_change_preemptible_tcs(port, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_setup_mqprio(struct net_device *ndev, void *type_data)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+	struct am65_cpsw_mqprio *p_mqprio = &amp;port-&gt;qos.mqprio;</div><div class='add'>+	struct tc_mqprio_qopt_offload *mqprio = type_data;</div><div class='add'>+	struct am65_cpsw_common *common = port-&gt;common;</div><div class='add'>+	struct tc_mqprio_qopt *qopt = &amp;mqprio-&gt;qopt;</div><div class='add'>+	int i, tc, offset, count, prio, ret;</div><div class='add'>+	u8 num_tc = qopt-&gt;num_tc;</div><div class='add'>+	u32 tx_prio_map = 0;</div><div class='add'>+</div><div class='add'>+	memcpy(&amp;p_mqprio-&gt;mqprio_hw, mqprio, sizeof(*mqprio));</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_get_sync(common-&gt;dev);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		pm_runtime_put_noidle(common-&gt;dev);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!num_tc) {</div><div class='add'>+		am65_cpsw_reset_tc_mqprio(ndev);</div><div class='add'>+		ret = 0;</div><div class='add'>+		goto exit_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = am65_cpsw_mqprio_verify_shaper(port, mqprio);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto exit_put;</div><div class='add'>+</div><div class='add'>+	netdev_set_num_tc(ndev, num_tc);</div><div class='add'>+</div><div class='add'>+	/* Multiple Linux priorities can map to a Traffic Class</div><div class='add'>+	 * A Traffic Class can have multiple contiguous Queues,</div><div class='add'>+	 * Queues get mapped to Channels (thread_id),</div><div class='add'>+	 *	if not VLAN tagged, thread_id is used as packet_priority</div><div class='add'>+	 *	if VLAN tagged. VLAN priority is used as packet_priority</div><div class='add'>+	 * packet_priority gets mapped to header_priority in p0_rx_pri_map,</div><div class='add'>+	 * header_priority gets mapped to switch_priority in pn_tx_pri_map.</div><div class='add'>+	 * As p0_rx_pri_map is left at defaults (0x76543210), we can</div><div class='add'>+	 * assume that Queue_n gets mapped to header_priority_n. We can then</div><div class='add'>+	 * set the switch priority in pn_tx_pri_map.</div><div class='add'>+	 */</div><div class='add'>+</div><div class='add'>+	for (tc = 0; tc &lt; num_tc; tc++) {</div><div class='add'>+		prio = tc;</div><div class='add'>+</div><div class='add'>+		/* For simplicity we assign the same priority (TCn) to</div><div class='add'>+		 * all queues of a Traffic Class.</div><div class='add'>+		 */</div><div class='add'>+		for (i = qopt-&gt;offset[tc]; i &lt; qopt-&gt;offset[tc] + qopt-&gt;count[tc]; i++)</div><div class='add'>+			tx_prio_map |= prio &lt;&lt; (4 * i);</div><div class='add'>+</div><div class='add'>+		count = qopt-&gt;count[tc];</div><div class='add'>+		offset = qopt-&gt;offset[tc];</div><div class='add'>+		netdev_set_tc_queue(ndev, tc, count, offset);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	writel(tx_prio_map, port-&gt;port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);</div><div class='add'>+</div><div class='add'>+	am65_cpsw_tx_pn_shaper_apply(port);</div><div class='add'>+	am65_cpsw_iet_change_preemptible_tcs(port, mqprio-&gt;preemptible_tcs);</div><div class='add'>+</div><div class='add'>+exit_put:</div><div class='add'>+	pm_runtime_put(common-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_iet_set_verify_timeout_count(struct am65_cpsw_port *port)</div><div class='add'>+{</div><div class='add'>+	int verify_time_ms = port-&gt;qos.iet.verify_time_ms;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	/* The number of wireside clocks contained in the verify</div><div class='add'>+	 * timeout counter. The default is 0x1312d0</div><div class='add'>+	 * (10ms at 125Mhz in 1G mode).</div><div class='add'>+	 */</div><div class='add'>+	val = 125 * HZ_PER_MHZ;	/* assuming 125MHz wireside clock */</div><div class='add'>+</div><div class='add'>+	val /= MILLIHZ_PER_HZ;		/* count per ms timeout */</div><div class='add'>+	val *= verify_time_ms;		/* count for timeout ms */</div><div class='add'>+</div><div class='add'>+	if (val &gt; AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	writel(val, port-&gt;port_base + AM65_CPSW_PN_REG_IET_VERIFY);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_iet_verify_wait(struct am65_cpsw_port *port)</div><div class='add'>+{</div><div class='add'>+	u32 ctrl, status;</div><div class='add'>+	int try;</div><div class='add'>+</div><div class='add'>+	try = 20;</div><div class='add'>+	do {</div><div class='add'>+		/* Reset the verify state machine by writing 1</div><div class='add'>+		 * to LINKFAIL</div><div class='add'>+		 */</div><div class='add'>+		ctrl = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+		ctrl |= AM65_CPSW_PN_IET_MAC_LINKFAIL;</div><div class='add'>+		writel(ctrl, port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+</div><div class='add'>+		/* Clear MAC_LINKFAIL bit to start Verify. */</div><div class='add'>+		ctrl = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+		ctrl &amp;= ~AM65_CPSW_PN_IET_MAC_LINKFAIL;</div><div class='add'>+		writel(ctrl, port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+</div><div class='add'>+		msleep(port-&gt;qos.iet.verify_time_ms);</div><div class='add'>+</div><div class='add'>+		status = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_STATUS);</div><div class='add'>+		if (status &amp; AM65_CPSW_PN_MAC_VERIFIED)</div><div class='add'>+			return 0;</div><div class='add'>+</div><div class='add'>+		if (status &amp; AM65_CPSW_PN_MAC_VERIFY_FAIL) {</div><div class='add'>+			netdev_dbg(port-&gt;ndev,</div><div class='add'>+				   "MAC Merge verify failed, trying again\n");</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (status &amp; AM65_CPSW_PN_MAC_RESPOND_ERR) {</div><div class='add'>+			netdev_dbg(port-&gt;ndev, "MAC Merge respond error\n");</div><div class='add'>+			return -ENODEV;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (status &amp; AM65_CPSW_PN_MAC_VERIFY_ERR) {</div><div class='add'>+			netdev_dbg(port-&gt;ndev, "MAC Merge verify error\n");</div><div class='add'>+			return -ENODEV;</div><div class='add'>+		}</div><div class='add'>+	} while (try-- &gt; 0);</div><div class='add'>+</div><div class='add'>+	netdev_dbg(port-&gt;ndev, "MAC Merge verify timeout\n");</div><div class='add'>+	return -ETIMEDOUT;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_iet_set_preempt_mask(struct am65_cpsw_port *port, u8 preemptible_tcs)</div><div class='add'>+{</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+	val &amp;= ~AM65_CPSW_PN_IET_MAC_PREMPT_MASK;</div><div class='add'>+	val |= AM65_CPSW_PN_IET_MAC_SET_PREEMPT(preemptible_tcs);</div><div class='add'>+	writel(val, port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* enable common IET_ENABLE only if at least 1 port has rx IET enabled.</div><div class='add'>+ * UAPI doesn't allow tx enable without rx enable.</div><div class='add'>+ */</div><div class='add'>+void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port;</div><div class='add'>+	bool rx_enable = false;</div><div class='add'>+	u32 val;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; common-&gt;port_num; i++) {</div><div class='add'>+		port = &amp;common-&gt;ports[i];</div><div class='add'>+		val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_CTL);</div><div class='add'>+		rx_enable = !!(val &amp; AM65_CPSW_PN_CTL_IET_PORT_EN);</div><div class='add'>+		if (rx_enable)</div><div class='add'>+			break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = readl(common-&gt;cpsw_base + AM65_CPSW_REG_CTL);</div><div class='add'>+</div><div class='add'>+	if (rx_enable)</div><div class='add'>+		val |= AM65_CPSW_CTL_IET_EN;</div><div class='add'>+	else</div><div class='add'>+		val &amp;= ~AM65_CPSW_CTL_IET_EN;</div><div class='add'>+</div><div class='add'>+	writel(val, common-&gt;cpsw_base + AM65_CPSW_REG_CTL);</div><div class='add'>+	common-&gt;iet_enabled = rx_enable;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* CPSW does not have an IRQ to notify changes to the MAC Merge TX status</div><div class='add'>+ * (active/inactive), but the preemptible traffic classes should only be</div><div class='add'>+ * committed to hardware once TX is active. Resort to polling.</div><div class='add'>+ */</div><div class='add'>+void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)</div><div class='add'>+{</div><div class='add'>+	u8 preemptible_tcs;</div><div class='add'>+	int err;</div><div class='add'>+	u32 val;</div><div class='add'>+</div><div class='add'>+	if (port-&gt;qos.link_speed == SPEED_UNKNOWN)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_CTL);</div><div class='add'>+	if (!(val &amp; AM65_CPSW_PN_CTL_IET_PORT_EN))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* update common IET enable */</div><div class='add'>+	am65_cpsw_iet_common_enable(port-&gt;common);</div><div class='add'>+</div><div class='add'>+	/* update verify count */</div><div class='add'>+	err = am65_cpsw_iet_set_verify_timeout_count(port);</div><div class='add'>+	if (err) {</div><div class='add'>+		netdev_err(port-&gt;ndev, "couldn't set verify count: %d\n", err);</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	val = readl(port-&gt;port_base + AM65_CPSW_PN_REG_IET_CTRL);</div><div class='add'>+	if (!(val &amp; AM65_CPSW_PN_IET_MAC_DISABLEVERIFY)) {</div><div class='add'>+		err = am65_cpsw_iet_verify_wait(port);</div><div class='add'>+		if (err)</div><div class='add'>+			return;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	preemptible_tcs = port-&gt;qos.iet.preemptible_tcs;</div><div class='add'>+	am65_cpsw_iet_set_preempt_mask(port, preemptible_tcs);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_iet_change_preemptible_tcs(struct am65_cpsw_port *port, u8 preemptible_tcs)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(port-&gt;ndev);</div><div class='add'>+</div><div class='add'>+	port-&gt;qos.iet.preemptible_tcs = preemptible_tcs;</div><div class='add'>+	mutex_lock(&amp;priv-&gt;mm_lock);</div><div class='add'>+	am65_cpsw_iet_commit_preemptible_tcs(port);</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;mm_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void am65_cpsw_iet_link_state_update(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;priv-&gt;mm_lock);</div><div class='add'>+	am65_cpsw_iet_commit_preemptible_tcs(port);</div><div class='add'>+	mutex_unlock(&amp;priv-&gt;mm_lock);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int am65_cpsw_port_est_enabled(struct am65_cpsw_port *port)</div><div class='ctx'> {</div><div class='ctx'> 	return port-&gt;qos.est_oper || port-&gt;qos.est_admin;</div><div class='hunk'>@@ -428,7 +804,7 @@ static void am65_cpsw_stop_est(struct net_device *ndev)</div><div class='ctx'> 	am65_cpsw_timer_stop(ndev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void am65_cpsw_purge_est(struct net_device *ndev)</div><div class='add'>+static void am65_cpsw_taprio_destroy(struct net_device *ndev)</div><div class='ctx'> {</div><div class='ctx'> 	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='ctx'> </div><div class='hunk'>@@ -439,31 +815,74 @@ static void am65_cpsw_purge_est(struct net_device *ndev)</div><div class='ctx'> </div><div class='ctx'> 	port-&gt;qos.est_oper = NULL;</div><div class='ctx'> 	port-&gt;qos.est_admin = NULL;</div><div class='add'>+</div><div class='add'>+	am65_cpsw_reset_tc_mqprio(ndev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int am65_cpsw_configure_taprio(struct net_device *ndev,</div><div class='del'>-				      struct am65_cpsw_est *est_new)</div><div class='add'>+static void am65_cpsw_cp_taprio(struct tc_taprio_qopt_offload *from,</div><div class='add'>+				struct tc_taprio_qopt_offload *to)</div><div class='add'>+{</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	*to = *from;</div><div class='add'>+	for (i = 0; i &lt; from-&gt;num_entries; i++)</div><div class='add'>+		to-&gt;entries[i] = from-&gt;entries[i];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int am65_cpsw_taprio_replace(struct net_device *ndev,</div><div class='add'>+				    struct tc_taprio_qopt_offload *taprio)</div><div class='ctx'> {</div><div class='ctx'> 	struct am65_cpsw_common *common = am65_ndev_to_common(ndev);</div><div class='add'>+	struct netlink_ext_ack *extack = taprio-&gt;mqprio.extack;</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='ctx'> 	struct am65_cpts *cpts = common-&gt;cpts;</div><div class='del'>-	int ret = 0, tact = TACT_PROG;</div><div class='add'>+	struct am65_cpsw_est *est_new;</div><div class='add'>+	int ret, tact;</div><div class='ctx'> </div><div class='del'>-	am65_cpsw_est_update_state(ndev);</div><div class='add'>+	if (!netif_running(ndev)) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "interface is down, link speed unknown");</div><div class='add'>+		return -ENETDOWN;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	if (est_new-&gt;taprio.cmd == TAPRIO_CMD_DESTROY) {</div><div class='del'>-		am65_cpsw_stop_est(ndev);</div><div class='del'>-		return ret;</div><div class='add'>+	if (common-&gt;pf_p0_rx_ptype_rrobin) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "p0-rx-ptype-rrobin flag conflicts with taprio qdisc");</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (port-&gt;qos.link_speed == SPEED_UNKNOWN)</div><div class='add'>+		return -ENOLINK;</div><div class='add'>+</div><div class='add'>+	if (taprio-&gt;cycle_time_extension) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "cycle time extension not supported");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	est_new = devm_kzalloc(&amp;ndev-&gt;dev,</div><div class='add'>+			       struct_size(est_new, taprio.entries, taprio-&gt;num_entries),</div><div class='add'>+			       GFP_KERNEL);</div><div class='add'>+	if (!est_new)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ret = am65_cpsw_setup_mqprio(ndev, &amp;taprio-&gt;mqprio);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	am65_cpsw_cp_taprio(taprio, &amp;est_new-&gt;taprio);</div><div class='add'>+</div><div class='add'>+	am65_cpsw_est_update_state(ndev);</div><div class='add'>+</div><div class='ctx'> 	ret = am65_cpsw_est_check_scheds(ndev, est_new);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+		goto fail;</div><div class='ctx'> </div><div class='ctx'> 	tact = am65_cpsw_timer_act(ndev, est_new);</div><div class='ctx'> 	if (tact == TACT_NEED_STOP) {</div><div class='del'>-		dev_err(&amp;ndev-&gt;dev,</div><div class='del'>-			"Can't toggle estf timer, stop taprio first");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+				   "Can't toggle estf timer, stop taprio first");</div><div class='add'>+		ret = -EINVAL;</div><div class='add'>+		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (tact == TACT_PROG)</div><div class='hunk'>@@ -476,62 +895,26 @@ static int am65_cpsw_configure_taprio(struct net_device *ndev,</div><div class='ctx'> 	am65_cpsw_est_set_sched_list(ndev, est_new);</div><div class='ctx'> 	am65_cpsw_port_est_assign_buf_num(ndev, est_new-&gt;buf);</div><div class='ctx'> </div><div class='del'>-	am65_cpsw_est_set(ndev, est_new-&gt;taprio.cmd == TAPRIO_CMD_REPLACE);</div><div class='add'>+	am65_cpsw_est_set(ndev, 1);</div><div class='ctx'> </div><div class='ctx'> 	if (tact == TACT_PROG) {</div><div class='ctx'> 		ret = am65_cpsw_timer_set(ndev, est_new);</div><div class='ctx'> 		if (ret) {</div><div class='del'>-			dev_err(&amp;ndev-&gt;dev, "Failed to set cycle time");</div><div class='del'>-			return ret;</div><div class='add'>+			NL_SET_ERR_MSG_MOD(extack,</div><div class='add'>+					   "Failed to set cycle time");</div><div class='add'>+			goto fail;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void am65_cpsw_cp_taprio(struct tc_taprio_qopt_offload *from,</div><div class='del'>-				struct tc_taprio_qopt_offload *to)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	*to = *from;</div><div class='del'>-	for (i = 0; i &lt; from-&gt;num_entries; i++)</div><div class='del'>-		to-&gt;entries[i] = from-&gt;entries[i];</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int am65_cpsw_set_taprio(struct net_device *ndev, void *type_data)</div><div class='del'>-{</div><div class='del'>-	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='del'>-	struct tc_taprio_qopt_offload *taprio = type_data;</div><div class='del'>-	struct am65_cpsw_est *est_new;</div><div class='del'>-	int ret = 0;</div><div class='del'>-</div><div class='del'>-	if (taprio-&gt;cycle_time_extension) {</div><div class='del'>-		dev_err(&amp;ndev-&gt;dev, "Failed to set cycle time extension");</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	est_new = devm_kzalloc(&amp;ndev-&gt;dev,</div><div class='del'>-			       struct_size(est_new, taprio.entries, taprio-&gt;num_entries),</div><div class='del'>-			       GFP_KERNEL);</div><div class='del'>-	if (!est_new)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	am65_cpsw_cp_taprio(taprio, &amp;est_new-&gt;taprio);</div><div class='del'>-	ret = am65_cpsw_configure_taprio(ndev, est_new);</div><div class='del'>-	if (!ret) {</div><div class='del'>-		if (taprio-&gt;cmd == TAPRIO_CMD_REPLACE) {</div><div class='del'>-			devm_kfree(&amp;ndev-&gt;dev, port-&gt;qos.est_admin);</div><div class='add'>+	devm_kfree(&amp;ndev-&gt;dev, port-&gt;qos.est_admin);</div><div class='add'>+	port-&gt;qos.est_admin = est_new;</div><div class='add'>+	am65_cpsw_iet_change_preemptible_tcs(port, taprio-&gt;mqprio.preemptible_tcs);</div><div class='ctx'> </div><div class='del'>-			port-&gt;qos.est_admin = est_new;</div><div class='del'>-		} else {</div><div class='del'>-			devm_kfree(&amp;ndev-&gt;dev, est_new);</div><div class='del'>-			am65_cpsw_purge_est(ndev);</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		devm_kfree(&amp;ndev-&gt;dev, est_new);</div><div class='del'>-	}</div><div class='add'>+	return 0;</div><div class='ctx'> </div><div class='add'>+fail:</div><div class='add'>+	am65_cpsw_reset_tc_mqprio(ndev);</div><div class='add'>+	devm_kfree(&amp;ndev-&gt;dev, est_new);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -541,7 +924,6 @@ static void am65_cpsw_est_link_up(struct net_device *ndev, int link_speed)</div><div class='ctx'> 	ktime_t cur_time;</div><div class='ctx'> 	s64 delta;</div><div class='ctx'> </div><div class='del'>-	port-&gt;qos.link_speed = link_speed;</div><div class='ctx'> 	if (!am65_cpsw_port_est_enabled(port))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -558,37 +940,26 @@ static void am65_cpsw_est_link_up(struct net_device *ndev, int link_speed)</div><div class='ctx'> 	return;</div><div class='ctx'> </div><div class='ctx'> purge_est:</div><div class='del'>-	am65_cpsw_purge_est(ndev);</div><div class='add'>+	am65_cpsw_taprio_destroy(ndev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_setup_taprio(struct net_device *ndev, void *type_data)</div><div class='ctx'> {</div><div class='del'>-	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='ctx'> 	struct tc_taprio_qopt_offload *taprio = type_data;</div><div class='del'>-	struct am65_cpsw_common *common = port-&gt;common;</div><div class='del'>-</div><div class='del'>-	if (taprio-&gt;cmd != TAPRIO_CMD_REPLACE &amp;&amp;</div><div class='del'>-	    taprio-&gt;cmd != TAPRIO_CMD_DESTROY)</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-</div><div class='del'>-	if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	if (!netif_running(ndev)) {</div><div class='del'>-		dev_err(&amp;ndev-&gt;dev, "interface is down, link speed unknown\n");</div><div class='del'>-		return -ENETDOWN;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (common-&gt;pf_p0_rx_ptype_rrobin) {</div><div class='del'>-		dev_err(&amp;ndev-&gt;dev,</div><div class='del'>-			"p0-rx-ptype-rrobin flag conflicts with taprio qdisc\n");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+	int err = 0;</div><div class='add'>+</div><div class='add'>+	switch (taprio-&gt;cmd) {</div><div class='add'>+	case TAPRIO_CMD_REPLACE:</div><div class='add'>+		err = am65_cpsw_taprio_replace(ndev, taprio);</div><div class='add'>+		break;</div><div class='add'>+	case TAPRIO_CMD_DESTROY:</div><div class='add'>+		am65_cpsw_taprio_destroy(ndev);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		err = -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (port-&gt;qos.link_speed == SPEED_UNKNOWN)</div><div class='del'>-		return -ENOLINK;</div><div class='del'>-</div><div class='del'>-	return am65_cpsw_set_taprio(ndev, type_data);</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int am65_cpsw_tc_query_caps(struct net_device *ndev, void *type_data)</div><div class='hunk'>@@ -596,12 +967,17 @@ static int am65_cpsw_tc_query_caps(struct net_device *ndev, void *type_data)</div><div class='ctx'> 	struct tc_query_caps_base *base = type_data;</div><div class='ctx'> </div><div class='ctx'> 	switch (base-&gt;type) {</div><div class='add'>+	case TC_SETUP_QDISC_MQPRIO: {</div><div class='add'>+		struct tc_mqprio_caps *caps = base-&gt;caps;</div><div class='add'>+</div><div class='add'>+		caps-&gt;validate_queue_counts = true;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	case TC_SETUP_QDISC_TAPRIO: {</div><div class='ctx'> 		struct tc_taprio_caps *caps = base-&gt;caps;</div><div class='ctx'> </div><div class='del'>-		if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))</div><div class='del'>-			return -EOPNOTSUPP;</div><div class='del'>-</div><div class='ctx'> 		caps-&gt;gate_mask_per_txq = true;</div><div class='ctx'> </div><div class='ctx'> 		return 0;</div><div class='hunk'>@@ -787,55 +1163,6 @@ static int am65_cpsw_qos_setup_tc_block(struct net_device *ndev, struct flow_blo</div><div class='ctx'> 					  port, port, true);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,</div><div class='del'>-			       void *type_data)</div><div class='del'>-{</div><div class='del'>-	switch (type) {</div><div class='del'>-	case TC_QUERY_CAPS:</div><div class='del'>-		return am65_cpsw_tc_query_caps(ndev, type_data);</div><div class='del'>-	case TC_SETUP_QDISC_TAPRIO:</div><div class='del'>-		return am65_cpsw_setup_taprio(ndev, type_data);</div><div class='del'>-	case TC_SETUP_BLOCK:</div><div class='del'>-		return am65_cpsw_qos_setup_tc_block(ndev, type_data);</div><div class='del'>-	default:</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed)</div><div class='del'>-{</div><div class='del'>-	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='del'>-</div><div class='del'>-	if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	am65_cpsw_est_link_up(ndev, link_speed);</div><div class='del'>-	port-&gt;qos.link_down_time = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void am65_cpsw_qos_link_down(struct net_device *ndev)</div><div class='del'>-{</div><div class='del'>-	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='del'>-</div><div class='del'>-	if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (!port-&gt;qos.link_down_time)</div><div class='del'>-		port-&gt;qos.link_down_time = ktime_get();</div><div class='del'>-</div><div class='del'>-	port-&gt;qos.link_speed = SPEED_UNKNOWN;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u32</div><div class='del'>-am65_cpsw_qos_tx_rate_calc(u32 rate_mbps, unsigned long bus_freq)</div><div class='del'>-{</div><div class='del'>-	u32 ir;</div><div class='del'>-</div><div class='del'>-	bus_freq /= 1000000;</div><div class='del'>-	ir = DIV_ROUND_UP(((u64)rate_mbps * 32768),  bus_freq);</div><div class='del'>-	return ir;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void</div><div class='ctx'> am65_cpsw_qos_tx_p0_rate_apply(struct am65_cpsw_common *common,</div><div class='ctx'> 			       int tx_ch, u32 rate_mbps)</div><div class='hunk'>@@ -937,3 +1264,44 @@ void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)</div><div class='ctx'> 		       host-&gt;port_base + AM65_CPSW_PN_REG_PRI_CIR(tx_ch));</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='add'>+</div><div class='add'>+int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,</div><div class='add'>+			       void *type_data)</div><div class='add'>+{</div><div class='add'>+	switch (type) {</div><div class='add'>+	case TC_QUERY_CAPS:</div><div class='add'>+		return am65_cpsw_tc_query_caps(ndev, type_data);</div><div class='add'>+	case TC_SETUP_QDISC_TAPRIO:</div><div class='add'>+		return am65_cpsw_setup_taprio(ndev, type_data);</div><div class='add'>+	case TC_SETUP_QDISC_MQPRIO:</div><div class='add'>+		return am65_cpsw_setup_mqprio(ndev, type_data);</div><div class='add'>+	case TC_SETUP_BLOCK:</div><div class='add'>+		return am65_cpsw_qos_setup_tc_block(ndev, type_data);</div><div class='add'>+	default:</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+</div><div class='add'>+	port-&gt;qos.link_speed = link_speed;</div><div class='add'>+	am65_cpsw_tx_pn_shaper_apply(port);</div><div class='add'>+	am65_cpsw_iet_link_state_update(ndev);</div><div class='add'>+</div><div class='add'>+	am65_cpsw_est_link_up(ndev, link_speed);</div><div class='add'>+	port-&gt;qos.link_down_time = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void am65_cpsw_qos_link_down(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct am65_cpsw_port *port = am65_ndev_to_port(ndev);</div><div class='add'>+</div><div class='add'>+	port-&gt;qos.link_speed = SPEED_UNKNOWN;</div><div class='add'>+	am65_cpsw_tx_pn_shaper_apply(port);</div><div class='add'>+	am65_cpsw_iet_link_state_update(ndev);</div><div class='add'>+</div><div class='add'>+	if (!port-&gt;qos.link_down_time)</div><div class='add'>+		port-&gt;qos.link_down_time = ktime_get();</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/ethernet/ti/am65-cpsw-qos.h b/drivers/net/ethernet/ti/am65-cpsw-qos.h<br/>index 0cc2a3b3d7f9..b328e56c5b2b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-qos.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/am65-cpsw-qos.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/am65-cpsw-qos.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/am65-cpsw-qos.h</a></div><div class='hunk'>@@ -9,6 +9,7 @@</div><div class='ctx'> #include &lt;net/pkt_sched.h&gt;</div><div class='ctx'> </div><div class='ctx'> struct am65_cpsw_common;</div><div class='add'>+struct am65_cpsw_port;</div><div class='ctx'> </div><div class='ctx'> struct am65_cpsw_est {</div><div class='ctx'> 	int buf;</div><div class='hunk'>@@ -16,6 +17,18 @@ struct am65_cpsw_est {</div><div class='ctx'> 	struct tc_taprio_qopt_offload taprio;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct am65_cpsw_mqprio {</div><div class='add'>+	struct tc_mqprio_qopt_offload mqprio_hw;</div><div class='add'>+	u64 max_rate_total;</div><div class='add'>+	bool shaper_en;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct am65_cpsw_iet {</div><div class='add'>+	u8 preemptible_tcs;</div><div class='add'>+	u32 original_max_blks;</div><div class='add'>+	int verify_time_ms;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct am65_cpsw_ale_ratelimit {</div><div class='ctx'> 	unsigned long cookie;</div><div class='ctx'> 	u64 rate_packet_ps;</div><div class='hunk'>@@ -26,16 +39,189 @@ struct am65_cpsw_qos {</div><div class='ctx'> 	struct am65_cpsw_est *est_oper;</div><div class='ctx'> 	ktime_t link_down_time;</div><div class='ctx'> 	int link_speed;</div><div class='add'>+	struct am65_cpsw_mqprio mqprio;</div><div class='add'>+	struct am65_cpsw_iet iet;</div><div class='ctx'> </div><div class='ctx'> 	struct am65_cpsw_ale_ratelimit ale_bc_ratelimit;</div><div class='ctx'> 	struct am65_cpsw_ale_ratelimit ale_mc_ratelimit;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+#define AM65_CPSW_REG_CTL			0x004</div><div class='add'>+#define AM65_CPSW_PN_REG_CTL			0x004</div><div class='add'>+#define AM65_CPSW_PN_REG_FIFO_STATUS		0x050</div><div class='add'>+#define AM65_CPSW_PN_REG_EST_CTL		0x060</div><div class='add'>+#define AM65_CPSW_PN_REG_PRI_CIR(pri)		(0x140 + 4 * (pri))</div><div class='add'>+#define AM65_CPSW_P0_REG_PRI_EIR(pri)		(0x160 + 4 * (pri))</div><div class='add'>+</div><div class='add'>+#define AM65_CPSW_PN_REG_CTL			0x004</div><div class='add'>+#define AM65_CPSW_PN_REG_TX_PRI_MAP		0x018</div><div class='add'>+#define AM65_CPSW_PN_REG_RX_PRI_MAP		0x020</div><div class='add'>+#define AM65_CPSW_PN_REG_FIFO_STATUS		0x050</div><div class='add'>+#define AM65_CPSW_PN_REG_EST_CTL		0x060</div><div class='add'>+#define AM65_CPSW_PN_REG_PRI_CIR(pri)		(0x140 + 4 * (pri))</div><div class='add'>+#define AM65_CPSW_PN_REG_PRI_EIR(pri)		(0x160 + 4 * (pri))</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_REG_CTL register fields */</div><div class='add'>+#define AM65_CPSW_CTL_EST_EN			BIT(18)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_CTL register fields */</div><div class='add'>+#define AM65_CPSW_PN_CTL_EST_PORT_EN		BIT(17)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_EST_CTL register fields */</div><div class='add'>+#define AM65_CPSW_PN_EST_ONEBUF			BIT(0)</div><div class='add'>+#define AM65_CPSW_PN_EST_BUFSEL			BIT(1)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_EN			BIT(2)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_FIRST		BIT(3)</div><div class='add'>+#define AM65_CPSW_PN_EST_ONEPRI			BIT(4)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_PRI_MSK		GENMASK(7, 5)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */</div><div class='add'>+#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK	GENMASK(7, 0)</div><div class='add'>+#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK	GENMASK(15, 8)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_CNT_ERR		BIT(16)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_ADD_ERR		BIT(17)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_BUFACT		BIT(18)</div><div class='add'>+</div><div class='add'>+/* EST FETCH COMMAND RAM */</div><div class='add'>+#define AM65_CPSW_FETCH_RAM_CMD_NUM		0x80</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_MSK			GENMASK(21, 8)</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_MAX			(AM65_CPSW_FETCH_CNT_MSK &gt;&gt; 8)</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_OFFSET		8</div><div class='add'>+#define AM65_CPSW_FETCH_ALLOW_MSK		GENMASK(7, 0)</div><div class='add'>+#define AM65_CPSW_FETCH_ALLOW_MAX		AM65_CPSW_FETCH_ALLOW_MSK</div><div class='add'>+</div><div class='add'>+/* number of priority queues per port FIFO */</div><div class='add'>+#define AM65_CPSW_PN_FIFO_PRIO_NUM		8</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_TI_AM65_CPSW_QOS)</div><div class='ctx'> int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,</div><div class='ctx'> 			       void *type_data);</div><div class='ctx'> void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);</div><div class='ctx'> void am65_cpsw_qos_link_down(struct net_device *ndev);</div><div class='ctx'> int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev, int queue, u32 rate_mbps);</div><div class='ctx'> void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common);</div><div class='add'>+void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port);</div><div class='add'>+void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common);</div><div class='add'>+#else</div><div class='add'>+static inline int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev,</div><div class='add'>+					     enum tc_setup_type type,</div><div class='add'>+					     void *type_data)</div><div class='add'>+{</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void am65_cpsw_qos_link_up(struct net_device *ndev,</div><div class='add'>+					 int link_speed)</div><div class='add'>+{ }</div><div class='add'>+</div><div class='add'>+static inline void am65_cpsw_qos_link_down(struct net_device *ndev)</div><div class='add'>+{ }</div><div class='add'>+</div><div class='add'>+static inline int am65_cpsw_qos_ndo_tx_p0_set_maxrate(struct net_device *ndev,</div><div class='add'>+						      int queue,</div><div class='add'>+						      u32 rate_mbps)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline void am65_cpsw_qos_tx_p0_rate_init(struct am65_cpsw_common *common)</div><div class='add'>+{ }</div><div class='add'>+static inline void am65_cpsw_iet_commit_preemptible_tcs(struct am65_cpsw_port *port)</div><div class='add'>+{ }</div><div class='add'>+static inline void am65_cpsw_iet_common_enable(struct am65_cpsw_common *common)</div><div class='add'>+{ }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+#define AM65_CPSW_REG_CTL			0x004</div><div class='add'>+#define AM65_CPSW_PN_REG_CTL			0x004</div><div class='add'>+#define AM65_CPSW_PN_REG_MAX_BLKS		0x008</div><div class='add'>+#define AM65_CPSW_PN_REG_TX_PRI_MAP		0x018</div><div class='add'>+#define AM65_CPSW_PN_REG_RX_PRI_MAP		0x020</div><div class='add'>+#define AM65_CPSW_PN_REG_IET_CTRL		0x040</div><div class='add'>+#define AM65_CPSW_PN_REG_IET_STATUS		0x044</div><div class='add'>+#define AM65_CPSW_PN_REG_IET_VERIFY		0x048</div><div class='add'>+#define AM65_CPSW_PN_REG_FIFO_STATUS		0x050</div><div class='add'>+#define AM65_CPSW_PN_REG_EST_CTL		0x060</div><div class='add'>+#define AM65_CPSW_PN_REG_PRI_CIR(pri)		(0x140 + 4 * (pri))</div><div class='add'>+#define AM65_CPSW_PN_REG_PRI_EIR(pri)		(0x160 + 4 * (pri))</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_REG_CTL register fields */</div><div class='add'>+#define AM65_CPSW_CTL_IET_EN			BIT(17)</div><div class='add'>+#define AM65_CPSW_CTL_EST_EN			BIT(18)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_CTL register fields */</div><div class='add'>+#define AM65_CPSW_PN_CTL_IET_PORT_EN		BIT(16)</div><div class='add'>+#define AM65_CPSW_PN_CTL_EST_PORT_EN		BIT(17)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_EST_CTL register fields */</div><div class='add'>+#define AM65_CPSW_PN_EST_ONEBUF			BIT(0)</div><div class='add'>+#define AM65_CPSW_PN_EST_BUFSEL			BIT(1)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_EN			BIT(2)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_FIRST		BIT(3)</div><div class='add'>+#define AM65_CPSW_PN_EST_ONEPRI			BIT(4)</div><div class='add'>+#define AM65_CPSW_PN_EST_TS_PRI_MSK		GENMASK(7, 5)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_IET_CTRL register fields */</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_PENABLE		BIT(0)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_DISABLEVERIFY	BIT(2)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_LINKFAIL		BIT(3)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK	GENMASK(10, 8)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET	8</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_PREMPT_MASK		GENMASK(23, 16)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET		16</div><div class='add'>+</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_SET_ADDFRAGSIZE(n)	(((n) &lt;&lt; AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET) &amp; \</div><div class='add'>+						  AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_GET_ADDFRAGSIZE(n)	(((n) &amp; AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_MASK) &gt;&gt; \</div><div class='add'>+						  AM65_CPSW_PN_IET_MAC_MAC_ADDFRAGSIZE_OFFSET)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_SET_PREEMPT(n)	(((n) &lt;&lt; AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET) &amp; \</div><div class='add'>+						 AM65_CPSW_PN_IET_MAC_PREMPT_MASK)</div><div class='add'>+#define AM65_CPSW_PN_IET_MAC_GET_PREEMPT(n)	(((n) &amp; AM65_CPSW_PN_IET_MAC_PREMPT_MASK) &gt;&gt; \</div><div class='add'>+						 AM65_CPSW_PN_IET_MAC_PREMPT_OFFSET)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_IET_STATUS register fields */</div><div class='add'>+#define AM65_CPSW_PN_MAC_STATUS			GENMASK(3, 0)</div><div class='add'>+#define AM65_CPSW_PN_MAC_VERIFIED		BIT(0)</div><div class='add'>+#define AM65_CPSW_PN_MAC_VERIFY_FAIL		BIT(1)</div><div class='add'>+#define AM65_CPSW_PN_MAC_RESPOND_ERR		BIT(2)</div><div class='add'>+#define AM65_CPSW_PN_MAC_VERIFY_ERR		BIT(3)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_IET_VERIFY register fields */</div><div class='add'>+#define AM65_CPSW_PN_MAC_VERIFY_CNT_MASK	GENMASK(23, 0)</div><div class='add'>+#define AM65_CPSW_PN_MAC_GET_VERIFY_CNT(n)	((n) &amp; AM65_CPSW_PN_MAC_VERIFY_CNT_MASK)</div><div class='add'>+/* 10 msec converted to NSEC */</div><div class='add'>+#define AM65_CPSW_IET_VERIFY_CNT_MS		(10)</div><div class='add'>+#define AM65_CPSW_IET_VERIFY_CNT_NS		(AM65_CPSW_IET_VERIFY_CNT_MS * \</div><div class='add'>+						 NSEC_PER_MSEC)</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */</div><div class='add'>+#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK	GENMASK(7, 0)</div><div class='add'>+#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK	GENMASK(15, 8)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_CNT_ERR		BIT(16)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_ADD_ERR		BIT(17)</div><div class='add'>+#define AM65_CPSW_PN_FST_EST_BUFACT		BIT(18)</div><div class='add'>+</div><div class='add'>+/* EST FETCH COMMAND RAM */</div><div class='add'>+#define AM65_CPSW_FETCH_RAM_CMD_NUM		0x80</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_MSK			GENMASK(21, 8)</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_MAX			(AM65_CPSW_FETCH_CNT_MSK &gt;&gt; 8)</div><div class='add'>+#define AM65_CPSW_FETCH_CNT_OFFSET		8</div><div class='add'>+#define AM65_CPSW_FETCH_ALLOW_MSK		GENMASK(7, 0)</div><div class='add'>+#define AM65_CPSW_FETCH_ALLOW_MAX		AM65_CPSW_FETCH_ALLOW_MSK</div><div class='add'>+</div><div class='add'>+/* AM65_CPSW_PN_REG_MAX_BLKS fields for IET and No IET cases */</div><div class='add'>+/* 7 blocks for pn_rx_max_blks, 13 for pn_tx_max_blks*/</div><div class='add'>+#define AM65_CPSW_PN_TX_RX_MAX_BLKS_IET		0xD07</div><div class='add'>+</div><div class='add'>+/* Slave IET Stats. register offsets */</div><div class='add'>+#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_ERROR	0x140</div><div class='add'>+#define AM65_CPSW_STATN_IET_RX_ASSEMBLY_OK	0x144</div><div class='add'>+#define AM65_CPSW_STATN_IET_RX_SMD_ERROR	0x148</div><div class='add'>+#define AM65_CPSW_STATN_IET_RX_FRAG		0x14c</div><div class='add'>+#define AM65_CPSW_STATN_IET_TX_HOLD		0x150</div><div class='add'>+#define AM65_CPSW_STATN_IET_TX_FRAG		0x154</div><div class='add'>+</div><div class='add'>+/* number of priority queues per port FIFO */</div><div class='add'>+#define AM65_CPSW_PN_FIFO_PRIO_NUM		8</div><div class='ctx'> </div><div class='ctx'> #endif /* AM65_CPSW_QOS_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c<br/>index ca4d4548f85e..ea85c6dd5484 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/cpsw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/cpsw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/cpsw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/cpsw.c</a></div><div class='hunk'>@@ -1722,14 +1722,20 @@ clean_runtime_disable_ret:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cpsw_remove(struct platform_device *pdev)</div><div class='add'>+static void cpsw_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct cpsw_common *cpsw = platform_get_drvdata(pdev);</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		/* Note, if this error path is taken, we're leaking some</div><div class='add'>+		 * resources.</div><div class='add'>+		 */</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to resume device (%pe)\n",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; cpsw-&gt;data.slaves; i++)</div><div class='ctx'> 		if (cpsw-&gt;slaves[i].ndev)</div><div class='hunk'>@@ -1740,7 +1746,6 @@ static int cpsw_remove(struct platform_device *pdev)</div><div class='ctx'> 	cpsw_remove_dt(pdev);</div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_PM_SLEEP</div><div class='hunk'>@@ -1795,7 +1800,7 @@ static struct platform_driver cpsw_driver = {</div><div class='ctx'> 		.of_match_table = cpsw_of_mtable,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = cpsw_probe,</div><div class='del'>-	.remove = cpsw_remove,</div><div class='add'>+	.remove_new = cpsw_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(cpsw_driver);</div><div class='head'>diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c<br/>index 0e4f526b1753..498c50c6d1a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/cpsw_new.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/cpsw_new.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/cpsw_new.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/cpsw_new.c</a></div><div class='hunk'>@@ -2037,14 +2037,20 @@ clean_dt_ret:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int cpsw_remove(struct platform_device *pdev)</div><div class='add'>+static void cpsw_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct cpsw_common *cpsw = platform_get_drvdata(pdev);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = pm_runtime_resume_and_get(&amp;pdev-&gt;dev);</div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		/* Note, if this error path is taken, we're leaking some</div><div class='add'>+		 * resources.</div><div class='add'>+		 */</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to resume device (%pe)\n",</div><div class='add'>+			ERR_PTR(ret));</div><div class='add'>+		return;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	cpsw_unregister_notifiers(cpsw);</div><div class='ctx'> 	cpsw_unregister_devlink(cpsw);</div><div class='hunk'>@@ -2055,7 +2061,6 @@ static int cpsw_remove(struct platform_device *pdev)</div><div class='ctx'> 	cpsw_remove_dt(cpsw);</div><div class='ctx'> 	pm_runtime_put_sync(&amp;pdev-&gt;dev);</div><div class='ctx'> 	pm_runtime_disable(&amp;pdev-&gt;dev);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int __maybe_unused cpsw_suspend(struct device *dev)</div><div class='hunk'>@@ -2116,7 +2121,7 @@ static struct platform_driver cpsw_driver = {</div><div class='ctx'> 		.of_match_table = cpsw_of_mtable,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = cpsw_probe,</div><div class='del'>-	.remove = cpsw_remove,</div><div class='add'>+	.remove_new = cpsw_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> module_platform_driver(cpsw_driver);</div><div class='head'>diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c<br/>index 628c87dc1d28..8e07d4a1b6ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/davinci_mdio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/ti/davinci_mdio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/ti/davinci_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/ti/davinci_mdio.c</a></div><div class='hunk'>@@ -511,16 +511,12 @@ static const struct k3_mdio_soc_data am65_mdio_soc_data = {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static const struct soc_device_attribute k3_mdio_socinfo[] = {</div><div class='del'>-	{ .family = "AM62X", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "AM64X", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "AM64X", .revision = "SR2.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "AM65X", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "AM65X", .revision = "SR2.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "J7200", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "J7200", .revision = "SR2.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "J721E", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "J721E", .revision = "SR2.0", .data = &amp;am65_mdio_soc_data },</div><div class='del'>-	{ .family = "J721S2", .revision = "SR1.0", .data = &amp;am65_mdio_soc_data},</div><div class='add'>+	{ .family = "AM62X", .data = &amp;am65_mdio_soc_data },</div><div class='add'>+	{ .family = "AM64X", .data = &amp;am65_mdio_soc_data },</div><div class='add'>+	{ .family = "AM65X", .data = &amp;am65_mdio_soc_data },</div><div class='add'>+	{ .family = "J7200", .data = &amp;am65_mdio_soc_data },</div><div class='add'>+	{ .family = "J721E", .data = &amp;am65_mdio_soc_data },</div><div class='add'>+	{ .family = "J721S2", .data = &amp;am65_mdio_soc_data },</div><div class='ctx'> 	{ /* sentinel */ },</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c<br/>index 9d535ae59626..d5b75af163d3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/toshiba/ps3_gelic_net.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/toshiba/ps3_gelic_net.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/toshiba/ps3_gelic_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/toshiba/ps3_gelic_net.c</a></div><div class='hunk'>@@ -93,12 +93,13 @@ static void gelic_card_get_ether_port_status(struct gelic_card *card,</div><div class='ctx'>  * gelic_descr_get_status -- returns the status of a descriptor</div><div class='ctx'>  * @descr: descriptor to look at</div><div class='ctx'>  *</div><div class='del'>- * returns the status as in the dmac_cmd_status field of the descriptor</div><div class='add'>+ * returns the status as in the hw_regs.dmac_cmd_status field of the descriptor</div><div class='ctx'>  */</div><div class='ctx'> static enum gelic_descr_dma_status</div><div class='ctx'> gelic_descr_get_status(struct gelic_descr *descr)</div><div class='ctx'> {</div><div class='del'>-	return be32_to_cpu(descr-&gt;dmac_cmd_status) &amp; GELIC_DESCR_DMA_STAT_MASK;</div><div class='add'>+	return be32_to_cpu(descr-&gt;hw_regs.dmac_cmd_status) &amp;</div><div class='add'>+		GELIC_DESCR_DMA_STAT_MASK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int gelic_card_set_link_mode(struct gelic_card *card, int mode)</div><div class='hunk'>@@ -152,15 +153,15 @@ static void gelic_card_enable_rxdmac(struct gelic_card *card)</div><div class='ctx'> 	if (gelic_descr_get_status(card-&gt;rx_chain.head) !=</div><div class='ctx'> 	    GELIC_DESCR_DMA_CARDOWNED) {</div><div class='ctx'> 		printk(KERN_ERR "%s: status=%x\n", __func__,</div><div class='del'>-		       be32_to_cpu(card-&gt;rx_chain.head-&gt;dmac_cmd_status));</div><div class='add'>+		       be32_to_cpu(card-&gt;rx_chain.head-&gt;hw_regs.dmac_cmd_status));</div><div class='ctx'> 		printk(KERN_ERR "%s: nextphy=%x\n", __func__,</div><div class='del'>-		       be32_to_cpu(card-&gt;rx_chain.head-&gt;next_descr_addr));</div><div class='add'>+		       be32_to_cpu(card-&gt;rx_chain.head-&gt;hw_regs.next_descr_addr));</div><div class='ctx'> 		printk(KERN_ERR "%s: head=%p\n", __func__,</div><div class='ctx'> 		       card-&gt;rx_chain.head);</div><div class='ctx'> 	}</div><div class='ctx'> #endif</div><div class='ctx'> 	status = lv1_net_start_rx_dma(bus_id(card), dev_id(card),</div><div class='del'>-				card-&gt;rx_chain.head-&gt;bus_addr, 0);</div><div class='add'>+				card-&gt;rx_chain.head-&gt;link.cpu_addr, 0);</div><div class='ctx'> 	if (status)</div><div class='ctx'> 		dev_info(ctodev(card),</div><div class='ctx'> 			 "lv1_net_start_rx_dma failed, status=%d\n", status);</div><div class='hunk'>@@ -195,8 +196,8 @@ static void gelic_card_disable_rxdmac(struct gelic_card *card)</div><div class='ctx'> static void gelic_descr_set_status(struct gelic_descr *descr,</div><div class='ctx'> 				   enum gelic_descr_dma_status status)</div><div class='ctx'> {</div><div class='del'>-	descr-&gt;dmac_cmd_status = cpu_to_be32(status |</div><div class='del'>-			(be32_to_cpu(descr-&gt;dmac_cmd_status) &amp;</div><div class='add'>+	descr-&gt;hw_regs.dmac_cmd_status = cpu_to_be32(status |</div><div class='add'>+			(be32_to_cpu(descr-&gt;hw_regs.dmac_cmd_status) &amp;</div><div class='ctx'> 			 ~GELIC_DESCR_DMA_STAT_MASK));</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * dma_cmd_status field is used to indicate whether the descriptor</div><div class='hunk'>@@ -224,13 +225,14 @@ static void gelic_card_reset_chain(struct gelic_card *card,</div><div class='ctx'> </div><div class='ctx'> 	for (descr = start_descr; start_descr != descr-&gt;next; descr++) {</div><div class='ctx'> 		gelic_descr_set_status(descr, GELIC_DESCR_DMA_CARDOWNED);</div><div class='del'>-		descr-&gt;next_descr_addr = cpu_to_be32(descr-&gt;next-&gt;bus_addr);</div><div class='add'>+		descr-&gt;hw_regs.next_descr_addr</div><div class='add'>+			= cpu_to_be32(descr-&gt;next-&gt;link.cpu_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	chain-&gt;head = start_descr;</div><div class='ctx'> 	chain-&gt;tail = (descr - 1);</div><div class='ctx'> </div><div class='del'>-	(descr - 1)-&gt;next_descr_addr = 0;</div><div class='add'>+	(descr - 1)-&gt;hw_regs.next_descr_addr = 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void gelic_card_up(struct gelic_card *card)</div><div class='hunk'>@@ -286,10 +288,12 @@ static void gelic_card_free_chain(struct gelic_card *card,</div><div class='ctx'> {</div><div class='ctx'> 	struct gelic_descr *descr;</div><div class='ctx'> </div><div class='del'>-	for (descr = descr_in; descr &amp;&amp; descr-&gt;bus_addr; descr = descr-&gt;next) {</div><div class='del'>-		dma_unmap_single(ctodev(card), descr-&gt;bus_addr,</div><div class='del'>-				 GELIC_DESCR_SIZE, DMA_BIDIRECTIONAL);</div><div class='del'>-		descr-&gt;bus_addr = 0;</div><div class='add'>+	for (descr = descr_in; descr &amp;&amp; descr-&gt;link.cpu_addr;</div><div class='add'>+		descr = descr-&gt;next) {</div><div class='add'>+		dma_unmap_single(ctodev(card), descr-&gt;link.cpu_addr,</div><div class='add'>+				 descr-&gt;link.size, DMA_BIDIRECTIONAL);</div><div class='add'>+		descr-&gt;link.cpu_addr = 0;</div><div class='add'>+		descr-&gt;link.size = 0;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -317,17 +321,21 @@ static int gelic_card_init_chain(struct gelic_card *card,</div><div class='ctx'> </div><div class='ctx'> 	/* set up the hardware pointers in each descriptor */</div><div class='ctx'> 	for (i = 0; i &lt; no; i++, descr++) {</div><div class='del'>-		dma_addr_t cpu_addr;</div><div class='del'>-</div><div class='ctx'> 		gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE);</div><div class='ctx'> </div><div class='del'>-		cpu_addr = dma_map_single(ctodev(card), descr,</div><div class='del'>-					  GELIC_DESCR_SIZE, DMA_BIDIRECTIONAL);</div><div class='add'>+		descr-&gt;link.size = sizeof(struct gelic_hw_regs);</div><div class='add'>+		descr-&gt;link.cpu_addr = dma_map_single(ctodev(card), descr,</div><div class='add'>+					  descr-&gt;link.size, DMA_BIDIRECTIONAL);</div><div class='ctx'> </div><div class='del'>-		if (dma_mapping_error(ctodev(card), cpu_addr))</div><div class='del'>-			goto iommu_error;</div><div class='add'>+		if (dma_mapping_error(ctodev(card), descr-&gt;link.cpu_addr)) {</div><div class='add'>+			for (i--, descr--; 0 &lt;= i; i--, descr--) {</div><div class='add'>+				dma_unmap_single(ctodev(card),</div><div class='add'>+					descr-&gt;link.cpu_addr, descr-&gt;link.size,</div><div class='add'>+					DMA_BIDIRECTIONAL);</div><div class='add'>+			}</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='del'>-		descr-&gt;bus_addr = cpu_to_be32(cpu_addr);</div><div class='ctx'> 		descr-&gt;next = descr + 1;</div><div class='ctx'> 		descr-&gt;prev = descr - 1;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -338,24 +346,17 @@ static int gelic_card_init_chain(struct gelic_card *card,</div><div class='ctx'> 	/* chain bus addr of hw descriptor */</div><div class='ctx'> 	descr = start_descr;</div><div class='ctx'> 	for (i = 0; i &lt; no; i++, descr++) {</div><div class='del'>-		descr-&gt;next_descr_addr = cpu_to_be32(descr-&gt;next-&gt;bus_addr);</div><div class='add'>+		descr-&gt;hw_regs.next_descr_addr =</div><div class='add'>+			cpu_to_be32(descr-&gt;next-&gt;link.cpu_addr);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	chain-&gt;head = start_descr;</div><div class='ctx'> 	chain-&gt;tail = start_descr;</div><div class='ctx'> </div><div class='ctx'> 	/* do not chain last hw descriptor */</div><div class='del'>-	(descr - 1)-&gt;next_descr_addr = 0;</div><div class='add'>+	(descr - 1)-&gt;hw_regs.next_descr_addr = 0;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='del'>-</div><div class='del'>-iommu_error:</div><div class='del'>-	for (i--, descr--; 0 &lt;= i; i--, descr--)</div><div class='del'>-		if (descr-&gt;bus_addr)</div><div class='del'>-			dma_unmap_single(ctodev(card), descr-&gt;bus_addr,</div><div class='del'>-					 GELIC_DESCR_SIZE,</div><div class='del'>-					 DMA_BIDIRECTIONAL);</div><div class='del'>-	return -ENOMEM;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -385,14 +386,16 @@ static int gelic_descr_prepare_rx(struct gelic_card *card,</div><div class='ctx'> </div><div class='ctx'> 	descr-&gt;skb = netdev_alloc_skb(*card-&gt;netdev, rx_skb_size);</div><div class='ctx'> 	if (!descr-&gt;skb) {</div><div class='del'>-		descr-&gt;buf_addr = 0; /* tell DMAC don't touch memory */</div><div class='add'>+		descr-&gt;hw_regs.payload.dev_addr = 0; /* tell DMAC don't touch memory */</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='del'>-	descr-&gt;buf_size = cpu_to_be32(rx_skb_size);</div><div class='del'>-	descr-&gt;dmac_cmd_status = 0;</div><div class='del'>-	descr-&gt;result_size = 0;</div><div class='del'>-	descr-&gt;valid_size = 0;</div><div class='del'>-	descr-&gt;data_error = 0;</div><div class='add'>+	descr-&gt;hw_regs.dmac_cmd_status = 0;</div><div class='add'>+	descr-&gt;hw_regs.result_size = 0;</div><div class='add'>+	descr-&gt;hw_regs.valid_size = 0;</div><div class='add'>+	descr-&gt;hw_regs.data_error = 0;</div><div class='add'>+	descr-&gt;hw_regs.payload.dev_addr = 0;</div><div class='add'>+	descr-&gt;hw_regs.payload.size = 0;</div><div class='add'>+	descr-&gt;skb = NULL;</div><div class='ctx'> </div><div class='ctx'> 	offset = ((unsigned long)descr-&gt;skb-&gt;data) &amp;</div><div class='ctx'> 		(GELIC_NET_RXBUF_ALIGN - 1);</div><div class='hunk'>@@ -401,7 +404,7 @@ static int gelic_descr_prepare_rx(struct gelic_card *card,</div><div class='ctx'> 	/* io-mmu-map the skb */</div><div class='ctx'> 	cpu_addr = dma_map_single(ctodev(card), descr-&gt;skb-&gt;data,</div><div class='ctx'> 				  GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE);</div><div class='del'>-	descr-&gt;buf_addr = cpu_to_be32(cpu_addr);</div><div class='add'>+	descr-&gt;hw_regs.payload.dev_addr = cpu_to_be32(cpu_addr);</div><div class='ctx'> 	if (dma_mapping_error(ctodev(card), cpu_addr)) {</div><div class='ctx'> 		dev_kfree_skb_any(descr-&gt;skb);</div><div class='ctx'> 		descr-&gt;skb = NULL;</div><div class='hunk'>@@ -409,10 +412,14 @@ static int gelic_descr_prepare_rx(struct gelic_card *card,</div><div class='ctx'> 			 "%s:Could not iommu-map rx buffer\n", __func__);</div><div class='ctx'> 		gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE);</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	} else {</div><div class='del'>-		gelic_descr_set_status(descr, GELIC_DESCR_DMA_CARDOWNED);</div><div class='del'>-		return 0;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	descr-&gt;hw_regs.payload.size = cpu_to_be32(GELIC_NET_MAX_FRAME);</div><div class='add'>+	descr-&gt;hw_regs.payload.dev_addr = cpu_to_be32(cpu_addr);</div><div class='add'>+</div><div class='add'>+	gelic_descr_set_status(descr, GELIC_DESCR_DMA_CARDOWNED);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -427,14 +434,15 @@ static void gelic_card_release_rx_chain(struct gelic_card *card)</div><div class='ctx'> 	do {</div><div class='ctx'> 		if (descr-&gt;skb) {</div><div class='ctx'> 			dma_unmap_single(ctodev(card),</div><div class='del'>-					 be32_to_cpu(descr-&gt;buf_addr),</div><div class='del'>-					 descr-&gt;skb-&gt;len,</div><div class='del'>-					 DMA_FROM_DEVICE);</div><div class='del'>-			descr-&gt;buf_addr = 0;</div><div class='add'>+				be32_to_cpu(descr-&gt;hw_regs.payload.dev_addr),</div><div class='add'>+				descr-&gt;skb-&gt;len,</div><div class='add'>+				DMA_FROM_DEVICE);</div><div class='add'>+			descr-&gt;hw_regs.payload.dev_addr = 0;</div><div class='add'>+			descr-&gt;hw_regs.payload.size = 0;</div><div class='ctx'> 			dev_kfree_skb_any(descr-&gt;skb);</div><div class='ctx'> 			descr-&gt;skb = NULL;</div><div class='ctx'> 			gelic_descr_set_status(descr,</div><div class='del'>-					       GELIC_DESCR_DMA_NOT_IN_USE);</div><div class='add'>+				GELIC_DESCR_DMA_NOT_IN_USE);</div><div class='ctx'> 		}</div><div class='ctx'> 		descr = descr-&gt;next;</div><div class='ctx'> 	} while (descr != card-&gt;rx_chain.head);</div><div class='hunk'>@@ -496,19 +504,20 @@ static void gelic_descr_release_tx(struct gelic_card *card,</div><div class='ctx'> {</div><div class='ctx'> 	struct sk_buff *skb = descr-&gt;skb;</div><div class='ctx'> </div><div class='del'>-	BUG_ON(!(be32_to_cpu(descr-&gt;data_status) &amp; GELIC_DESCR_TX_TAIL));</div><div class='add'>+	BUG_ON(!(be32_to_cpu(descr-&gt;hw_regs.data_status) &amp; GELIC_DESCR_TX_TAIL));</div><div class='ctx'> </div><div class='del'>-	dma_unmap_single(ctodev(card), be32_to_cpu(descr-&gt;buf_addr), skb-&gt;len,</div><div class='del'>-			 DMA_TO_DEVICE);</div><div class='add'>+	dma_unmap_single(ctodev(card),</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.payload.dev_addr), skb-&gt;len,</div><div class='add'>+		DMA_TO_DEVICE);</div><div class='ctx'> 	dev_kfree_skb_any(skb);</div><div class='ctx'> </div><div class='del'>-	descr-&gt;buf_addr = 0;</div><div class='del'>-	descr-&gt;buf_size = 0;</div><div class='del'>-	descr-&gt;next_descr_addr = 0;</div><div class='del'>-	descr-&gt;result_size = 0;</div><div class='del'>-	descr-&gt;valid_size = 0;</div><div class='del'>-	descr-&gt;data_status = 0;</div><div class='del'>-	descr-&gt;data_error = 0;</div><div class='add'>+	descr-&gt;hw_regs.payload.dev_addr = 0;</div><div class='add'>+	descr-&gt;hw_regs.payload.size = 0;</div><div class='add'>+	descr-&gt;hw_regs.next_descr_addr = 0;</div><div class='add'>+	descr-&gt;hw_regs.result_size = 0;</div><div class='add'>+	descr-&gt;hw_regs.valid_size = 0;</div><div class='add'>+	descr-&gt;hw_regs.data_status = 0;</div><div class='add'>+	descr-&gt;hw_regs.data_error = 0;</div><div class='ctx'> 	descr-&gt;skb = NULL;</div><div class='ctx'> </div><div class='ctx'> 	/* set descr status */</div><div class='hunk'>@@ -701,7 +710,7 @@ static void gelic_descr_set_tx_cmdstat(struct gelic_descr *descr,</div><div class='ctx'> 				       struct sk_buff *skb)</div><div class='ctx'> {</div><div class='ctx'> 	if (skb-&gt;ip_summed != CHECKSUM_PARTIAL)</div><div class='del'>-		descr-&gt;dmac_cmd_status =</div><div class='add'>+		descr-&gt;hw_regs.dmac_cmd_status =</div><div class='ctx'> 			cpu_to_be32(GELIC_DESCR_DMA_CMD_NO_CHKSUM |</div><div class='ctx'> 				    GELIC_DESCR_TX_DMA_FRAME_TAIL);</div><div class='ctx'> 	else {</div><div class='hunk'>@@ -709,19 +718,19 @@ static void gelic_descr_set_tx_cmdstat(struct gelic_descr *descr,</div><div class='ctx'> 		 * if yes: tcp? udp? */</div><div class='ctx'> 		if (skb-&gt;protocol == htons(ETH_P_IP)) {</div><div class='ctx'> 			if (ip_hdr(skb)-&gt;protocol == IPPROTO_TCP)</div><div class='del'>-				descr-&gt;dmac_cmd_status =</div><div class='add'>+				descr-&gt;hw_regs.dmac_cmd_status =</div><div class='ctx'> 				cpu_to_be32(GELIC_DESCR_DMA_CMD_TCP_CHKSUM |</div><div class='ctx'> 					    GELIC_DESCR_TX_DMA_FRAME_TAIL);</div><div class='ctx'> </div><div class='ctx'> 			else if (ip_hdr(skb)-&gt;protocol == IPPROTO_UDP)</div><div class='del'>-				descr-&gt;dmac_cmd_status =</div><div class='add'>+				descr-&gt;hw_regs.dmac_cmd_status =</div><div class='ctx'> 				cpu_to_be32(GELIC_DESCR_DMA_CMD_UDP_CHKSUM |</div><div class='ctx'> 					    GELIC_DESCR_TX_DMA_FRAME_TAIL);</div><div class='ctx'> 			else	/*</div><div class='ctx'> 				 * the stack should checksum non-tcp and non-udp</div><div class='ctx'> 				 * packets on his own: NETIF_F_IP_CSUM</div><div class='ctx'> 				 */</div><div class='del'>-				descr-&gt;dmac_cmd_status =</div><div class='add'>+				descr-&gt;hw_regs.dmac_cmd_status =</div><div class='ctx'> 				cpu_to_be32(GELIC_DESCR_DMA_CMD_NO_CHKSUM |</div><div class='ctx'> 					    GELIC_DESCR_TX_DMA_FRAME_TAIL);</div><div class='ctx'> 		}</div><div class='hunk'>@@ -789,11 +798,11 @@ static int gelic_descr_prepare_tx(struct gelic_card *card,</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	descr-&gt;buf_addr = cpu_to_be32(buf);</div><div class='del'>-	descr-&gt;buf_size = cpu_to_be32(skb-&gt;len);</div><div class='add'>+	descr-&gt;hw_regs.payload.dev_addr = cpu_to_be32(buf);</div><div class='add'>+	descr-&gt;hw_regs.payload.size = cpu_to_be32(skb-&gt;len);</div><div class='ctx'> 	descr-&gt;skb = skb;</div><div class='del'>-	descr-&gt;data_status = 0;</div><div class='del'>-	descr-&gt;next_descr_addr = 0; /* terminate hw descr */</div><div class='add'>+	descr-&gt;hw_regs.data_status = 0;</div><div class='add'>+	descr-&gt;hw_regs.next_descr_addr = 0; /* terminate hw descr */</div><div class='ctx'> 	gelic_descr_set_tx_cmdstat(descr, skb);</div><div class='ctx'> </div><div class='ctx'> 	/* bump free descriptor pointer */</div><div class='hunk'>@@ -818,7 +827,7 @@ static int gelic_card_kick_txdma(struct gelic_card *card,</div><div class='ctx'> 	if (gelic_descr_get_status(descr) == GELIC_DESCR_DMA_CARDOWNED) {</div><div class='ctx'> 		card-&gt;tx_dma_progress = 1;</div><div class='ctx'> 		status = lv1_net_start_tx_dma(bus_id(card), dev_id(card),</div><div class='del'>-					      descr-&gt;bus_addr, 0);</div><div class='add'>+			descr-&gt;link.cpu_addr, 0);</div><div class='ctx'> 		if (status) {</div><div class='ctx'> 			card-&gt;tx_dma_progress = 0;</div><div class='ctx'> 			dev_info(ctodev(card), "lv1_net_start_txdma failed," \</div><div class='hunk'>@@ -871,7 +880,8 @@ netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev)</div><div class='ctx'> 	 * link this prepared descriptor to previous one</div><div class='ctx'> 	 * to achieve high performance</div><div class='ctx'> 	 */</div><div class='del'>-	descr-&gt;prev-&gt;next_descr_addr = cpu_to_be32(descr-&gt;bus_addr);</div><div class='add'>+	descr-&gt;prev-&gt;hw_regs.next_descr_addr =</div><div class='add'>+		cpu_to_be32(descr-&gt;link.cpu_addr);</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * as hardware descriptor is modified in the above lines,</div><div class='ctx'> 	 * ensure that the hardware sees it</div><div class='hunk'>@@ -884,12 +894,12 @@ netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev)</div><div class='ctx'> 		 */</div><div class='ctx'> 		netdev-&gt;stats.tx_dropped++;</div><div class='ctx'> 		/* don't trigger BUG_ON() in gelic_descr_release_tx */</div><div class='del'>-		descr-&gt;data_status = cpu_to_be32(GELIC_DESCR_TX_TAIL);</div><div class='add'>+		descr-&gt;hw_regs.data_status = cpu_to_be32(GELIC_DESCR_TX_TAIL);</div><div class='ctx'> 		gelic_descr_release_tx(card, descr);</div><div class='ctx'> 		/* reset head */</div><div class='ctx'> 		card-&gt;tx_chain.head = descr;</div><div class='ctx'> 		/* reset hw termination */</div><div class='del'>-		descr-&gt;prev-&gt;next_descr_addr = 0;</div><div class='add'>+		descr-&gt;prev-&gt;hw_regs.next_descr_addr = 0;</div><div class='ctx'> 		dev_info(ctodev(card), "%s: kick failure\n", __func__);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -914,21 +924,21 @@ static void gelic_net_pass_skb_up(struct gelic_descr *descr,</div><div class='ctx'> 	struct sk_buff *skb = descr-&gt;skb;</div><div class='ctx'> 	u32 data_status, data_error;</div><div class='ctx'> </div><div class='del'>-	data_status = be32_to_cpu(descr-&gt;data_status);</div><div class='del'>-	data_error = be32_to_cpu(descr-&gt;data_error);</div><div class='add'>+	data_status = be32_to_cpu(descr-&gt;hw_regs.data_status);</div><div class='add'>+	data_error = be32_to_cpu(descr-&gt;hw_regs.data_error);</div><div class='ctx'> 	/* unmap skb buffer */</div><div class='del'>-	dma_unmap_single(ctodev(card), be32_to_cpu(descr-&gt;buf_addr),</div><div class='del'>-			 GELIC_NET_MAX_FRAME,</div><div class='del'>-			 DMA_FROM_DEVICE);</div><div class='del'>-</div><div class='del'>-	skb_put(skb, be32_to_cpu(descr-&gt;valid_size)?</div><div class='del'>-		be32_to_cpu(descr-&gt;valid_size) :</div><div class='del'>-		be32_to_cpu(descr-&gt;result_size));</div><div class='del'>-	if (!descr-&gt;valid_size)</div><div class='add'>+	dma_unmap_single(ctodev(card),</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.payload.dev_addr),</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.payload.size), DMA_FROM_DEVICE);</div><div class='add'>+</div><div class='add'>+	skb_put(skb, be32_to_cpu(descr-&gt;hw_regs.valid_size)?</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.valid_size) :</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.result_size));</div><div class='add'>+	if (!descr-&gt;hw_regs.valid_size)</div><div class='ctx'> 		dev_info(ctodev(card), "buffer full %x %x %x\n",</div><div class='del'>-			 be32_to_cpu(descr-&gt;result_size),</div><div class='del'>-			 be32_to_cpu(descr-&gt;buf_size),</div><div class='del'>-			 be32_to_cpu(descr-&gt;dmac_cmd_status));</div><div class='add'>+			 be32_to_cpu(descr-&gt;hw_regs.result_size),</div><div class='add'>+			 be32_to_cpu(descr-&gt;hw_regs.payload.size),</div><div class='add'>+			 be32_to_cpu(descr-&gt;hw_regs.dmac_cmd_status));</div><div class='ctx'> </div><div class='ctx'> 	descr-&gt;skb = NULL;</div><div class='ctx'> 	/*</div><div class='hunk'>@@ -1039,14 +1049,14 @@ refill:</div><div class='ctx'> </div><div class='ctx'> 	/* is the current descriptor terminated with next_descr == NULL? */</div><div class='ctx'> 	dmac_chain_ended =</div><div class='del'>-		be32_to_cpu(descr-&gt;dmac_cmd_status) &amp;</div><div class='add'>+		be32_to_cpu(descr-&gt;hw_regs.dmac_cmd_status) &amp;</div><div class='ctx'> 		GELIC_DESCR_RX_DMA_CHAIN_END;</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * So that always DMAC can see the end</div><div class='ctx'> 	 * of the descriptor chain to avoid</div><div class='ctx'> 	 * from unwanted DMAC overrun.</div><div class='ctx'> 	 */</div><div class='del'>-	descr-&gt;next_descr_addr = 0;</div><div class='add'>+	descr-&gt;hw_regs.next_descr_addr = 0;</div><div class='ctx'> </div><div class='ctx'> 	/* change the descriptor state: */</div><div class='ctx'> 	gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE);</div><div class='hunk'>@@ -1063,7 +1073,8 @@ refill:</div><div class='ctx'> 	/*</div><div class='ctx'> 	 * Set this descriptor the end of the chain.</div><div class='ctx'> 	 */</div><div class='del'>-	descr-&gt;prev-&gt;next_descr_addr = cpu_to_be32(descr-&gt;bus_addr);</div><div class='add'>+	descr-&gt;prev-&gt;hw_regs.next_descr_addr =</div><div class='add'>+		cpu_to_be32(descr-&gt;link.cpu_addr);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If dmac chain was met, DMAC stopped.</div><div class='head'>diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.h b/drivers/net/ethernet/toshiba/ps3_gelic_net.h<br/>index 0d98defb011e..f7d7931e51b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/toshiba/ps3_gelic_net.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/toshiba/ps3_gelic_net.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/toshiba/ps3_gelic_net.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/toshiba/ps3_gelic_net.h</a></div><div class='hunk'>@@ -221,29 +221,35 @@ enum gelic_lv1_phy {</div><div class='ctx'> 	GELIC_LV1_PHY_ETHERNET_0	= 0x0000000000000002L,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-/* size of hardware part of gelic descriptor */</div><div class='del'>-#define GELIC_DESCR_SIZE	(32)</div><div class='del'>-</div><div class='ctx'> enum gelic_port_type {</div><div class='ctx'> 	GELIC_PORT_ETHERNET_0	= 0,</div><div class='ctx'> 	GELIC_PORT_WIRELESS	= 1,</div><div class='ctx'> 	GELIC_PORT_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct gelic_descr {</div><div class='del'>-	/* as defined by the hardware */</div><div class='del'>-	__be32 buf_addr;</div><div class='del'>-	__be32 buf_size;</div><div class='add'>+/* As defined by the gelic hardware device. */</div><div class='add'>+struct gelic_hw_regs {</div><div class='add'>+	struct  {</div><div class='add'>+		__be32 dev_addr;</div><div class='add'>+		__be32 size;</div><div class='add'>+	} __packed payload;</div><div class='ctx'> 	__be32 next_descr_addr;</div><div class='ctx'> 	__be32 dmac_cmd_status;</div><div class='ctx'> 	__be32 result_size;</div><div class='ctx'> 	__be32 valid_size;	/* all zeroes for tx */</div><div class='ctx'> 	__be32 data_status;</div><div class='ctx'> 	__be32 data_error;	/* all zeroes for tx */</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+struct gelic_chain_link {</div><div class='add'>+	dma_addr_t cpu_addr;</div><div class='add'>+	unsigned int size;</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	/* used in the driver */</div><div class='add'>+struct gelic_descr {</div><div class='add'>+	struct gelic_hw_regs hw_regs;</div><div class='add'>+	struct gelic_chain_link link;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='del'>-	dma_addr_t bus_addr;</div><div class='ctx'> 	struct gelic_descr *next;</div><div class='ctx'> 	struct gelic_descr *prev;</div><div class='ctx'> } __attribute__((aligned(32)));</div><div class='hunk'>@@ -346,12 +352,6 @@ static inline void *port_priv(struct gelic_port *port)</div><div class='ctx'> 	return port-&gt;priv;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-#ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC</div><div class='del'>-void udbg_shutdown_ps3gelic(void);</div><div class='del'>-#else</div><div class='del'>-static inline void udbg_shutdown_ps3gelic(void) {}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='ctx'> int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);</div><div class='ctx'> /* shared netdev ops */</div><div class='ctx'> void gelic_card_up(struct gelic_card *card);</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/Kconfig b/drivers/net/ethernet/wangxun/Kconfig<br/>index 23cd610bd376..85cdbdd44fec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/Kconfig</a></div><div class='hunk'>@@ -26,7 +26,7 @@ config NGBE</div><div class='ctx'> 	tristate "Wangxun(R) GbE PCI Express adapters support"</div><div class='ctx'> 	depends on PCI</div><div class='ctx'> 	select LIBWX</div><div class='del'>-	select PHYLIB</div><div class='add'>+	select PHYLINK</div><div class='ctx'> 	help</div><div class='ctx'> 	  This driver supports Wangxun(R) GbE PCI Express family of</div><div class='ctx'> 	  adapters.</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c b/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c<br/>index ddc5f6d20b9c..cc3bec42ed8e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.c</a></div><div class='hunk'>@@ -8,6 +8,7 @@</div><div class='ctx'> #include "wx_type.h"</div><div class='ctx'> #include "wx_ethtool.h"</div><div class='ctx'> #include "wx_hw.h"</div><div class='add'>+#include "wx_lib.h"</div><div class='ctx'> </div><div class='ctx'> struct wx_stats {</div><div class='ctx'> 	char stat_string[ETH_GSTRING_LEN];</div><div class='hunk'>@@ -75,7 +76,7 @@ void wx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)</div><div class='ctx'> 	switch (stringset) {</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; WX_GLOBAL_STATS_LEN; i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, wx_gstrings_stats[i].stat_string);</div><div class='add'>+			ethtool_puts(&amp;p, wx_gstrings_stats[i].stat_string);</div><div class='ctx'> 		for (i = 0; i &lt; netdev-&gt;num_tx_queues; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_packets", i);</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_bytes", i);</div><div class='hunk'>@@ -185,3 +186,238 @@ void wx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_get_drvinfo);</div><div class='add'>+</div><div class='add'>+int wx_nway_reset(struct net_device *netdev)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	return phylink_ethtool_nway_reset(wx-&gt;phylink);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_nway_reset);</div><div class='add'>+</div><div class='add'>+int wx_get_link_ksettings(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_link_ksettings *cmd)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	return phylink_ethtool_ksettings_get(wx-&gt;phylink, cmd);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_link_ksettings);</div><div class='add'>+</div><div class='add'>+int wx_set_link_ksettings(struct net_device *netdev,</div><div class='add'>+			  const struct ethtool_link_ksettings *cmd)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	return phylink_ethtool_ksettings_set(wx-&gt;phylink, cmd);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_link_ksettings);</div><div class='add'>+</div><div class='add'>+void wx_get_pauseparam(struct net_device *netdev,</div><div class='add'>+		       struct ethtool_pauseparam *pause)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	phylink_ethtool_get_pauseparam(wx-&gt;phylink, pause);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_pauseparam);</div><div class='add'>+</div><div class='add'>+int wx_set_pauseparam(struct net_device *netdev,</div><div class='add'>+		      struct ethtool_pauseparam *pause)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	return phylink_ethtool_set_pauseparam(wx-&gt;phylink, pause);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_pauseparam);</div><div class='add'>+</div><div class='add'>+void wx_get_ringparam(struct net_device *netdev,</div><div class='add'>+		      struct ethtool_ringparam *ring,</div><div class='add'>+		      struct kernel_ethtool_ringparam *kernel_ring,</div><div class='add'>+		      struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	ring-&gt;rx_max_pending = WX_MAX_RXD;</div><div class='add'>+	ring-&gt;tx_max_pending = WX_MAX_TXD;</div><div class='add'>+	ring-&gt;rx_mini_max_pending = 0;</div><div class='add'>+	ring-&gt;rx_jumbo_max_pending = 0;</div><div class='add'>+	ring-&gt;rx_pending = wx-&gt;rx_ring_count;</div><div class='add'>+	ring-&gt;tx_pending = wx-&gt;tx_ring_count;</div><div class='add'>+	ring-&gt;rx_mini_pending = 0;</div><div class='add'>+	ring-&gt;rx_jumbo_pending = 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_ringparam);</div><div class='add'>+</div><div class='add'>+int wx_get_coalesce(struct net_device *netdev,</div><div class='add'>+		    struct ethtool_coalesce *ec,</div><div class='add'>+		    struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+		    struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	ec-&gt;tx_max_coalesced_frames_irq = wx-&gt;tx_work_limit;</div><div class='add'>+	/* only valid if in constant ITR mode */</div><div class='add'>+	if (wx-&gt;rx_itr_setting &lt;= 1)</div><div class='add'>+		ec-&gt;rx_coalesce_usecs = wx-&gt;rx_itr_setting;</div><div class='add'>+	else</div><div class='add'>+		ec-&gt;rx_coalesce_usecs = wx-&gt;rx_itr_setting &gt;&gt; 2;</div><div class='add'>+</div><div class='add'>+	/* if in mixed tx/rx queues per vector mode, report only rx settings */</div><div class='add'>+	if (wx-&gt;q_vector[0]-&gt;tx.count &amp;&amp; wx-&gt;q_vector[0]-&gt;rx.count)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	/* only valid if in constant ITR mode */</div><div class='add'>+	if (wx-&gt;tx_itr_setting &lt;= 1)</div><div class='add'>+		ec-&gt;tx_coalesce_usecs = wx-&gt;tx_itr_setting;</div><div class='add'>+	else</div><div class='add'>+		ec-&gt;tx_coalesce_usecs = wx-&gt;tx_itr_setting &gt;&gt; 2;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_coalesce);</div><div class='add'>+</div><div class='add'>+int wx_set_coalesce(struct net_device *netdev,</div><div class='add'>+		    struct ethtool_coalesce *ec,</div><div class='add'>+		    struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+		    struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+	u16 tx_itr_param, rx_itr_param;</div><div class='add'>+	struct wx_q_vector *q_vector;</div><div class='add'>+	u16 max_eitr;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (wx-&gt;q_vector[0]-&gt;tx.count &amp;&amp; wx-&gt;q_vector[0]-&gt;rx.count) {</div><div class='add'>+		/* reject Tx specific changes in case of mixed RxTx vectors */</div><div class='add'>+		if (ec-&gt;tx_coalesce_usecs)</div><div class='add'>+			return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ec-&gt;tx_max_coalesced_frames_irq)</div><div class='add'>+		wx-&gt;tx_work_limit = ec-&gt;tx_max_coalesced_frames_irq;</div><div class='add'>+</div><div class='add'>+	if (wx-&gt;mac.type == wx_mac_sp)</div><div class='add'>+		max_eitr = WX_SP_MAX_EITR;</div><div class='add'>+	else</div><div class='add'>+		max_eitr = WX_EM_MAX_EITR;</div><div class='add'>+</div><div class='add'>+	if ((ec-&gt;rx_coalesce_usecs &gt; (max_eitr &gt;&gt; 2)) ||</div><div class='add'>+	    (ec-&gt;tx_coalesce_usecs &gt; (max_eitr &gt;&gt; 2)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (ec-&gt;rx_coalesce_usecs &gt; 1)</div><div class='add'>+		wx-&gt;rx_itr_setting = ec-&gt;rx_coalesce_usecs &lt;&lt; 2;</div><div class='add'>+	else</div><div class='add'>+		wx-&gt;rx_itr_setting = ec-&gt;rx_coalesce_usecs;</div><div class='add'>+</div><div class='add'>+	if (wx-&gt;rx_itr_setting == 1)</div><div class='add'>+		rx_itr_param = WX_20K_ITR;</div><div class='add'>+	else</div><div class='add'>+		rx_itr_param = wx-&gt;rx_itr_setting;</div><div class='add'>+</div><div class='add'>+	if (ec-&gt;tx_coalesce_usecs &gt; 1)</div><div class='add'>+		wx-&gt;tx_itr_setting = ec-&gt;tx_coalesce_usecs &lt;&lt; 2;</div><div class='add'>+	else</div><div class='add'>+		wx-&gt;tx_itr_setting = ec-&gt;tx_coalesce_usecs;</div><div class='add'>+</div><div class='add'>+	if (wx-&gt;tx_itr_setting == 1) {</div><div class='add'>+		if (wx-&gt;mac.type == wx_mac_sp)</div><div class='add'>+			tx_itr_param = WX_12K_ITR;</div><div class='add'>+		else</div><div class='add'>+			tx_itr_param = WX_20K_ITR;</div><div class='add'>+	} else {</div><div class='add'>+		tx_itr_param = wx-&gt;tx_itr_setting;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* mixed Rx/Tx */</div><div class='add'>+	if (wx-&gt;q_vector[0]-&gt;tx.count &amp;&amp; wx-&gt;q_vector[0]-&gt;rx.count)</div><div class='add'>+		wx-&gt;tx_itr_setting = wx-&gt;rx_itr_setting;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; wx-&gt;num_q_vectors; i++) {</div><div class='add'>+		q_vector = wx-&gt;q_vector[i];</div><div class='add'>+		if (q_vector-&gt;tx.count &amp;&amp; !q_vector-&gt;rx.count)</div><div class='add'>+			/* tx only */</div><div class='add'>+			q_vector-&gt;itr = tx_itr_param;</div><div class='add'>+		else</div><div class='add'>+			/* rx only or mixed */</div><div class='add'>+			q_vector-&gt;itr = rx_itr_param;</div><div class='add'>+		wx_write_eitr(q_vector);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_coalesce);</div><div class='add'>+</div><div class='add'>+static unsigned int wx_max_channels(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	unsigned int max_combined;</div><div class='add'>+</div><div class='add'>+	if (!wx-&gt;msix_q_entries) {</div><div class='add'>+		/* We only support one q_vector without MSI-X */</div><div class='add'>+		max_combined = 1;</div><div class='add'>+	} else {</div><div class='add'>+		/* support up to max allowed queues with RSS */</div><div class='add'>+		if (wx-&gt;mac.type == wx_mac_sp)</div><div class='add'>+			max_combined = 63;</div><div class='add'>+		else</div><div class='add'>+			max_combined = 8;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return max_combined;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void wx_get_channels(struct net_device *dev,</div><div class='add'>+		     struct ethtool_channels *ch)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	/* report maximum channels */</div><div class='add'>+	ch-&gt;max_combined = wx_max_channels(wx);</div><div class='add'>+</div><div class='add'>+	/* report info for other vector */</div><div class='add'>+	if (wx-&gt;msix_q_entries) {</div><div class='add'>+		ch-&gt;max_other = 1;</div><div class='add'>+		ch-&gt;other_count = 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* record RSS queues */</div><div class='add'>+	ch-&gt;combined_count = wx-&gt;ring_feature[RING_F_RSS].indices;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_channels);</div><div class='add'>+</div><div class='add'>+int wx_set_channels(struct net_device *dev,</div><div class='add'>+		    struct ethtool_channels *ch)</div><div class='add'>+{</div><div class='add'>+	unsigned int count = ch-&gt;combined_count;</div><div class='add'>+	struct wx *wx = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	/* verify other_count has not changed */</div><div class='add'>+	if (ch-&gt;other_count != 1)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	/* verify the number of channels does not exceed hardware limits */</div><div class='add'>+	if (count &gt; wx_max_channels(wx))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	wx-&gt;ring_feature[RING_F_RSS].limit = count;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_channels);</div><div class='add'>+</div><div class='add'>+u32 wx_get_msglevel(struct net_device *netdev)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	return wx-&gt;msg_enable;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_get_msglevel);</div><div class='add'>+</div><div class='add'>+void wx_set_msglevel(struct net_device *netdev, u32 data)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+</div><div class='add'>+	wx-&gt;msg_enable = data;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_msglevel);</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_ethtool.h b/drivers/net/ethernet/wangxun/libwx/wx_ethtool.h<br/>index 16d1a09369a6..600c3b597d1a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_ethtool.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_ethtool.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_ethtool.h</a></div><div class='hunk'>@@ -13,4 +13,31 @@ void wx_get_mac_stats(struct net_device *netdev,</div><div class='ctx'> void wx_get_pause_stats(struct net_device *netdev,</div><div class='ctx'> 			struct ethtool_pause_stats *stats);</div><div class='ctx'> void wx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info);</div><div class='add'>+int wx_nway_reset(struct net_device *netdev);</div><div class='add'>+int wx_get_link_ksettings(struct net_device *netdev,</div><div class='add'>+			  struct ethtool_link_ksettings *cmd);</div><div class='add'>+int wx_set_link_ksettings(struct net_device *netdev,</div><div class='add'>+			  const struct ethtool_link_ksettings *cmd);</div><div class='add'>+void wx_get_pauseparam(struct net_device *netdev,</div><div class='add'>+		       struct ethtool_pauseparam *pause);</div><div class='add'>+int wx_set_pauseparam(struct net_device *netdev,</div><div class='add'>+		      struct ethtool_pauseparam *pause);</div><div class='add'>+void wx_get_ringparam(struct net_device *netdev,</div><div class='add'>+		      struct ethtool_ringparam *ring,</div><div class='add'>+		      struct kernel_ethtool_ringparam *kernel_ring,</div><div class='add'>+		      struct netlink_ext_ack *extack);</div><div class='add'>+int wx_get_coalesce(struct net_device *netdev,</div><div class='add'>+		    struct ethtool_coalesce *ec,</div><div class='add'>+		    struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+		    struct netlink_ext_ack *extack);</div><div class='add'>+int wx_set_coalesce(struct net_device *netdev,</div><div class='add'>+		    struct ethtool_coalesce *ec,</div><div class='add'>+		    struct kernel_ethtool_coalesce *kernel_coal,</div><div class='add'>+		    struct netlink_ext_ack *extack);</div><div class='add'>+void wx_get_channels(struct net_device *dev,</div><div class='add'>+		     struct ethtool_channels *ch);</div><div class='add'>+int wx_set_channels(struct net_device *dev,</div><div class='add'>+		    struct ethtool_channels *ch);</div><div class='add'>+u32 wx_get_msglevel(struct net_device *netdev);</div><div class='add'>+void wx_set_msglevel(struct net_device *netdev, u32 data);</div><div class='ctx'> #endif /* _WX_ETHTOOL_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_hw.c b/drivers/net/ethernet/wangxun/libwx/wx_hw.c<br/>index 533e912af089..1db754615cca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_hw.c</a></div><div class='hunk'>@@ -149,9 +149,9 @@ void wx_irq_disable(struct wx *wx)</div><div class='ctx'> 		int vector;</div><div class='ctx'> </div><div class='ctx'> 		for (vector = 0; vector &lt; wx-&gt;num_q_vectors; vector++)</div><div class='del'>-			synchronize_irq(wx-&gt;msix_entries[vector].vector);</div><div class='add'>+			synchronize_irq(wx-&gt;msix_q_entries[vector].vector);</div><div class='ctx'> </div><div class='del'>-		synchronize_irq(wx-&gt;msix_entries[vector].vector);</div><div class='add'>+		synchronize_irq(wx-&gt;msix_entry-&gt;vector);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		synchronize_irq(pdev-&gt;irq);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -1158,6 +1158,81 @@ static void wx_set_rxpba(struct wx *wx)</div><div class='ctx'> 	wr32(wx, WX_TDM_PB_THRE(0), txpbthresh);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+#define WX_ETH_FRAMING 20</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * wx_hpbthresh - calculate high water mark for flow control</div><div class='add'>+ *</div><div class='add'>+ * @wx: board private structure to calculate for</div><div class='add'>+ **/</div><div class='add'>+static int wx_hpbthresh(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	struct net_device *dev = wx-&gt;netdev;</div><div class='add'>+	int link, tc, kb, marker;</div><div class='add'>+	u32 dv_id, rx_pba;</div><div class='add'>+</div><div class='add'>+	/* Calculate max LAN frame size */</div><div class='add'>+	link = dev-&gt;mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING;</div><div class='add'>+	tc = link;</div><div class='add'>+</div><div class='add'>+	/* Calculate delay value for device */</div><div class='add'>+	dv_id = WX_DV(link, tc);</div><div class='add'>+</div><div class='add'>+	/* Delay value is calculated in bit times convert to KB */</div><div class='add'>+	kb = WX_BT2KB(dv_id);</div><div class='add'>+	rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) &gt;&gt; WX_RDB_PB_SZ_SHIFT;</div><div class='add'>+</div><div class='add'>+	marker = rx_pba - kb;</div><div class='add'>+</div><div class='add'>+	/* It is possible that the packet buffer is not large enough</div><div class='add'>+	 * to provide required headroom. In this case throw an error</div><div class='add'>+	 * to user and a do the best we can.</div><div class='add'>+	 */</div><div class='add'>+	if (marker &lt; 0) {</div><div class='add'>+		dev_warn(&amp;wx-&gt;pdev-&gt;dev,</div><div class='add'>+			 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n");</div><div class='add'>+		marker = tc + 1;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return marker;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * wx_lpbthresh - calculate low water mark for flow control</div><div class='add'>+ *</div><div class='add'>+ * @wx: board private structure to calculate for</div><div class='add'>+ **/</div><div class='add'>+static int wx_lpbthresh(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	struct net_device *dev = wx-&gt;netdev;</div><div class='add'>+	u32 dv_id;</div><div class='add'>+	int tc;</div><div class='add'>+</div><div class='add'>+	/* Calculate max LAN frame size */</div><div class='add'>+	tc = dev-&gt;mtu + ETH_HLEN + ETH_FCS_LEN;</div><div class='add'>+</div><div class='add'>+	/* Calculate delay value for device */</div><div class='add'>+	dv_id = WX_LOW_DV(tc);</div><div class='add'>+</div><div class='add'>+	/* Delay value is calculated in bit times convert to KB */</div><div class='add'>+	return WX_BT2KB(dv_id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * wx_pbthresh_setup - calculate and setup high low water marks</div><div class='add'>+ *</div><div class='add'>+ * @wx: board private structure to calculate for</div><div class='add'>+ **/</div><div class='add'>+static void wx_pbthresh_setup(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	wx-&gt;fc.high_water = wx_hpbthresh(wx);</div><div class='add'>+	wx-&gt;fc.low_water = wx_lpbthresh(wx);</div><div class='add'>+</div><div class='add'>+	/* Low water marks must not be larger than high water marks */</div><div class='add'>+	if (wx-&gt;fc.low_water &gt; wx-&gt;fc.high_water)</div><div class='add'>+		wx-&gt;fc.low_water = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void wx_configure_port(struct wx *wx)</div><div class='ctx'> {</div><div class='ctx'> 	u32 value, i;</div><div class='hunk'>@@ -1522,6 +1597,72 @@ static void wx_restore_vlan(struct wx *wx)</div><div class='ctx'> 		wx_vlan_rx_add_vid(wx-&gt;netdev, htons(ETH_P_8021Q), vid);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void wx_store_reta(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	u8 *indir_tbl = wx-&gt;rss_indir_tbl;</div><div class='add'>+	u32 reta = 0;</div><div class='add'>+	u32 i;</div><div class='add'>+</div><div class='add'>+	/* Fill out the redirection table as follows:</div><div class='add'>+	 *  - 8 bit wide entries containing 4 bit RSS index</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; WX_MAX_RETA_ENTRIES; i++) {</div><div class='add'>+		reta |= indir_tbl[i] &lt;&lt; (i &amp; 0x3) * 8;</div><div class='add'>+		if ((i &amp; 3) == 3) {</div><div class='add'>+			wr32(wx, WX_RDB_RSSTBL(i &gt;&gt; 2), reta);</div><div class='add'>+			reta = 0;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wx_setup_reta(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	u16 rss_i = wx-&gt;ring_feature[RING_F_RSS].indices;</div><div class='add'>+	u32 random_key_size = WX_RSS_KEY_SIZE / 4;</div><div class='add'>+	u32 i, j;</div><div class='add'>+</div><div class='add'>+	/* Fill out hash function seeds */</div><div class='add'>+	for (i = 0; i &lt; random_key_size; i++)</div><div class='add'>+		wr32(wx, WX_RDB_RSSRK(i), wx-&gt;rss_key[i]);</div><div class='add'>+</div><div class='add'>+	/* Fill out redirection table */</div><div class='add'>+	memset(wx-&gt;rss_indir_tbl, 0, sizeof(wx-&gt;rss_indir_tbl));</div><div class='add'>+</div><div class='add'>+	for (i = 0, j = 0; i &lt; WX_MAX_RETA_ENTRIES; i++, j++) {</div><div class='add'>+		if (j == rss_i)</div><div class='add'>+			j = 0;</div><div class='add'>+</div><div class='add'>+		wx-&gt;rss_indir_tbl[i] = j;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wx_store_reta(wx);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wx_setup_mrqc(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	u32 rss_field = 0;</div><div class='add'>+</div><div class='add'>+	/* Disable indicating checksum in descriptor, enables RSS hash */</div><div class='add'>+	wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD);</div><div class='add'>+</div><div class='add'>+	/* Perform hash on these packet types */</div><div class='add'>+	rss_field = WX_RDB_RA_CTL_RSS_IPV4 |</div><div class='add'>+		    WX_RDB_RA_CTL_RSS_IPV4_TCP |</div><div class='add'>+		    WX_RDB_RA_CTL_RSS_IPV4_UDP |</div><div class='add'>+		    WX_RDB_RA_CTL_RSS_IPV6 |</div><div class='add'>+		    WX_RDB_RA_CTL_RSS_IPV6_TCP |</div><div class='add'>+		    WX_RDB_RA_CTL_RSS_IPV6_UDP;</div><div class='add'>+</div><div class='add'>+	netdev_rss_key_fill(wx-&gt;rss_key, sizeof(wx-&gt;rss_key));</div><div class='add'>+</div><div class='add'>+	wx_setup_reta(wx);</div><div class='add'>+</div><div class='add'>+	if (wx-&gt;rss_enabled)</div><div class='add'>+		rss_field |= WX_RDB_RA_CTL_RSS_EN;</div><div class='add'>+</div><div class='add'>+	wr32(wx, WX_RDB_RA_CTL, rss_field);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * wx_configure_rx - Configure Receive Unit after Reset</div><div class='ctx'>  * @wx: pointer to private structure</div><div class='hunk'>@@ -1554,6 +1695,8 @@ void wx_configure_rx(struct wx *wx)</div><div class='ctx'> 		wr32(wx, WX_PSR_CTL, psrctl);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	wx_setup_mrqc(wx);</div><div class='add'>+</div><div class='ctx'> 	/* set_rx_buffer_len must be called before ring initialization */</div><div class='ctx'> 	wx_set_rx_buffer_len(wx);</div><div class='ctx'> </div><div class='hunk'>@@ -1584,6 +1727,7 @@ static void wx_configure_isb(struct wx *wx)</div><div class='ctx'> void wx_configure(struct wx *wx)</div><div class='ctx'> {</div><div class='ctx'> 	wx_set_rxpba(wx);</div><div class='add'>+	wx_pbthresh_setup(wx);</div><div class='ctx'> 	wx_configure_port(wx);</div><div class='ctx'> </div><div class='ctx'> 	wx_set_rx_mode(wx-&gt;netdev);</div><div class='hunk'>@@ -1750,6 +1894,28 @@ int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_get_pcie_msix_counts);</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * wx_init_rss_key - Initialize wx RSS key</div><div class='add'>+ * @wx: device handle</div><div class='add'>+ *</div><div class='add'>+ * Allocates and initializes the RSS key if it is not allocated.</div><div class='add'>+ **/</div><div class='add'>+static int wx_init_rss_key(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	u32 *rss_key;</div><div class='add'>+</div><div class='add'>+	if (!wx-&gt;rss_key) {</div><div class='add'>+		rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL);</div><div class='add'>+		if (unlikely(!rss_key))</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+</div><div class='add'>+		netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE);</div><div class='add'>+		wx-&gt;rss_key = rss_key;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> int wx_sw_init(struct wx *wx)</div><div class='ctx'> {</div><div class='ctx'> 	struct pci_dev *pdev = wx-&gt;pdev;</div><div class='hunk'>@@ -1777,14 +1943,23 @@ int wx_sw_init(struct wx *wx)</div><div class='ctx'> 		wx-&gt;subsystem_device_id = swab16((u16)ssid);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	err = wx_init_rss_key(wx);</div><div class='add'>+	if (err &lt; 0) {</div><div class='add'>+		wx_err(wx, "rss key allocation failed\n");</div><div class='add'>+		return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	wx-&gt;mac_table = kcalloc(wx-&gt;mac.num_rar_entries,</div><div class='ctx'> 				sizeof(struct wx_mac_addr),</div><div class='ctx'> 				GFP_KERNEL);</div><div class='ctx'> 	if (!wx-&gt;mac_table) {</div><div class='ctx'> 		wx_err(wx, "mac_table allocation failed\n");</div><div class='add'>+		kfree(wx-&gt;rss_key);</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	wx-&gt;msix_in_use = false;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_sw_init);</div><div class='hunk'>@@ -2003,6 +2178,102 @@ int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_vlan_rx_kill_vid);</div><div class='ctx'> </div><div class='add'>+static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u16 reg_idx = ring-&gt;reg_idx;</div><div class='add'>+	u32 srrctl;</div><div class='add'>+</div><div class='add'>+	srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));</div><div class='add'>+	srrctl |= WX_PX_RR_CFG_DROP_EN;</div><div class='add'>+</div><div class='add'>+	wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring)</div><div class='add'>+{</div><div class='add'>+	u16 reg_idx = ring-&gt;reg_idx;</div><div class='add'>+	u32 srrctl;</div><div class='add'>+</div><div class='add'>+	srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx));</div><div class='add'>+	srrctl &amp;= ~WX_PX_RR_CFG_DROP_EN;</div><div class='add'>+</div><div class='add'>+	wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause)</div><div class='add'>+{</div><div class='add'>+	u16 pause_time = WX_DEFAULT_FCPAUSE;</div><div class='add'>+	u32 mflcn_reg, fccfg_reg, reg;</div><div class='add'>+	u32 fcrtl, fcrth;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	/* Low water mark of zero causes XOFF floods */</div><div class='add'>+	if (tx_pause &amp;&amp; wx-&gt;fc.high_water) {</div><div class='add'>+		if (!wx-&gt;fc.low_water || wx-&gt;fc.low_water &gt;= wx-&gt;fc.high_water) {</div><div class='add'>+			wx_err(wx, "Invalid water mark configuration\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Disable any previous flow control settings */</div><div class='add'>+	mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL);</div><div class='add'>+	mflcn_reg &amp;= ~WX_MAC_RX_FLOW_CTRL_RFE;</div><div class='add'>+</div><div class='add'>+	fccfg_reg = rd32(wx, WX_RDB_RFCC);</div><div class='add'>+	fccfg_reg &amp;= ~WX_RDB_RFCC_RFCE_802_3X;</div><div class='add'>+</div><div class='add'>+	if (rx_pause)</div><div class='add'>+		mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE;</div><div class='add'>+	if (tx_pause)</div><div class='add'>+		fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X;</div><div class='add'>+</div><div class='add'>+	/* Set 802.3x based flow control settings. */</div><div class='add'>+	wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg);</div><div class='add'>+	wr32(wx, WX_RDB_RFCC, fccfg_reg);</div><div class='add'>+</div><div class='add'>+	/* Set up and enable Rx high/low water mark thresholds, enable XON. */</div><div class='add'>+	if (tx_pause &amp;&amp; wx-&gt;fc.high_water) {</div><div class='add'>+		fcrtl = (wx-&gt;fc.low_water &lt;&lt; 10) | WX_RDB_RFCL_XONE;</div><div class='add'>+		wr32(wx, WX_RDB_RFCL, fcrtl);</div><div class='add'>+		fcrth = (wx-&gt;fc.high_water &lt;&lt; 10) | WX_RDB_RFCH_XOFFE;</div><div class='add'>+	} else {</div><div class='add'>+		wr32(wx, WX_RDB_RFCL, 0);</div><div class='add'>+		/* In order to prevent Tx hangs when the internal Tx</div><div class='add'>+		 * switch is enabled we must set the high water mark</div><div class='add'>+		 * to the Rx packet buffer size - 24KB.  This allows</div><div class='add'>+		 * the Tx switch to function even under heavy Rx</div><div class='add'>+		 * workloads.</div><div class='add'>+		 */</div><div class='add'>+		fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	wr32(wx, WX_RDB_RFCH, fcrth);</div><div class='add'>+</div><div class='add'>+	/* Configure pause time */</div><div class='add'>+	reg = pause_time * 0x00010001;</div><div class='add'>+	wr32(wx, WX_RDB_RFCV, reg);</div><div class='add'>+</div><div class='add'>+	/* Configure flow control refresh threshold value */</div><div class='add'>+	wr32(wx, WX_RDB_RFCRT, pause_time / 2);</div><div class='add'>+</div><div class='add'>+	/*  We should set the drop enable bit if:</div><div class='add'>+	 *  Number of Rx queues &gt; 1 and flow control is disabled</div><div class='add'>+	 *</div><div class='add'>+	 *  This allows us to avoid head of line blocking for security</div><div class='add'>+	 *  and performance reasons.</div><div class='add'>+	 */</div><div class='add'>+	if (wx-&gt;num_rx_queues &gt; 1 &amp;&amp; !tx_pause) {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++)</div><div class='add'>+			wx_enable_rx_drop(wx, wx-&gt;rx_ring[i]);</div><div class='add'>+	} else {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++)</div><div class='add'>+			wx_disable_rx_drop(wx, wx-&gt;rx_ring[i]);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_fc_enable);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * wx_update_stats - Update the board statistics counters.</div><div class='ctx'>  * @wx: board private structure</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_hw.h b/drivers/net/ethernet/wangxun/libwx/wx_hw.h<br/>index 12c20a7c364d..9e219fa717a2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_hw.h</a></div><div class='hunk'>@@ -41,6 +41,7 @@ int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count);</div><div class='ctx'> int wx_sw_init(struct wx *wx);</div><div class='ctx'> int wx_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid);</div><div class='ctx'> int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid);</div><div class='add'>+int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause);</div><div class='ctx'> void wx_update_stats(struct wx *wx);</div><div class='ctx'> void wx_clear_hw_cntrs(struct wx *wx);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_lib.c b/drivers/net/ethernet/wangxun/libwx/wx_lib.c<br/>index 2823861e5a92..8706223a6e5a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_lib.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_lib.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_lib.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_lib.c</a></div><div class='hunk'>@@ -160,60 +160,6 @@ static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,</div><div class='ctx'> 	return rx_desc-&gt;wb.upper.status_error &amp; cpu_to_le32(stat_err_bits);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static bool wx_can_reuse_rx_page(struct wx_rx_buffer *rx_buffer,</div><div class='del'>-				 int rx_buffer_pgcnt)</div><div class='del'>-{</div><div class='del'>-	unsigned int pagecnt_bias = rx_buffer-&gt;pagecnt_bias;</div><div class='del'>-	struct page *page = rx_buffer-&gt;page;</div><div class='del'>-</div><div class='del'>-	/* avoid re-using remote and pfmemalloc pages */</div><div class='del'>-	if (!dev_page_is_reusable(page))</div><div class='del'>-		return false;</div><div class='del'>-</div><div class='del'>-#if (PAGE_SIZE &lt; 8192)</div><div class='del'>-	/* if we are only owner of page we can reuse it */</div><div class='del'>-	if (unlikely((rx_buffer_pgcnt - pagecnt_bias) &gt; 1))</div><div class='del'>-		return false;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-	/* If we have drained the page fragment pool we need to update</div><div class='del'>-	 * the pagecnt_bias and page count so that we fully restock the</div><div class='del'>-	 * number of references the driver holds.</div><div class='del'>-	 */</div><div class='del'>-	if (unlikely(pagecnt_bias == 1)) {</div><div class='del'>-		page_ref_add(page, USHRT_MAX - 1);</div><div class='del'>-		rx_buffer-&gt;pagecnt_bias = USHRT_MAX;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return true;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='del'>- * wx_reuse_rx_page - page flip buffer and store it back on the ring</div><div class='del'>- * @rx_ring: rx descriptor ring to store buffers on</div><div class='del'>- * @old_buff: donor buffer to have page reused</div><div class='del'>- *</div><div class='del'>- * Synchronizes page for reuse by the adapter</div><div class='del'>- **/</div><div class='del'>-static void wx_reuse_rx_page(struct wx_ring *rx_ring,</div><div class='del'>-			     struct wx_rx_buffer *old_buff)</div><div class='del'>-{</div><div class='del'>-	u16 nta = rx_ring-&gt;next_to_alloc;</div><div class='del'>-	struct wx_rx_buffer *new_buff;</div><div class='del'>-</div><div class='del'>-	new_buff = &amp;rx_ring-&gt;rx_buffer_info[nta];</div><div class='del'>-</div><div class='del'>-	/* update, and store next to alloc */</div><div class='del'>-	nta++;</div><div class='del'>-	rx_ring-&gt;next_to_alloc = (nta &lt; rx_ring-&gt;count) ? nta : 0;</div><div class='del'>-</div><div class='del'>-	/* transfer page from old buffer to new buffer */</div><div class='del'>-	new_buff-&gt;page = old_buff-&gt;page;</div><div class='del'>-	new_buff-&gt;page_dma = old_buff-&gt;page_dma;</div><div class='del'>-	new_buff-&gt;page_offset = old_buff-&gt;page_offset;</div><div class='del'>-	new_buff-&gt;pagecnt_bias	= old_buff-&gt;pagecnt_bias;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void wx_dma_sync_frag(struct wx_ring *rx_ring,</div><div class='ctx'> 			     struct wx_rx_buffer *rx_buffer)</div><div class='ctx'> {</div><div class='hunk'>@@ -270,8 +216,6 @@ static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,</div><div class='ctx'> 				      size,</div><div class='ctx'> 				      DMA_FROM_DEVICE);</div><div class='ctx'> skip_sync:</div><div class='del'>-	rx_buffer-&gt;pagecnt_bias--;</div><div class='del'>-</div><div class='ctx'> 	return rx_buffer;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -280,19 +224,9 @@ static void wx_put_rx_buffer(struct wx_ring *rx_ring,</div><div class='ctx'> 			     struct sk_buff *skb,</div><div class='ctx'> 			     int rx_buffer_pgcnt)</div><div class='ctx'> {</div><div class='del'>-	if (wx_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {</div><div class='del'>-		/* hand second half of page back to the ring */</div><div class='del'>-		wx_reuse_rx_page(rx_ring, rx_buffer);</div><div class='del'>-	} else {</div><div class='del'>-		if (!IS_ERR(skb) &amp;&amp; WX_CB(skb)-&gt;dma == rx_buffer-&gt;dma)</div><div class='del'>-			/* the page has been released from the ring */</div><div class='del'>-			WX_CB(skb)-&gt;page_released = true;</div><div class='del'>-		else</div><div class='del'>-			page_pool_put_full_page(rx_ring-&gt;page_pool, rx_buffer-&gt;page, false);</div><div class='del'>-</div><div class='del'>-		__page_frag_cache_drain(rx_buffer-&gt;page,</div><div class='del'>-					rx_buffer-&gt;pagecnt_bias);</div><div class='del'>-	}</div><div class='add'>+	if (!IS_ERR(skb) &amp;&amp; WX_CB(skb)-&gt;dma == rx_buffer-&gt;dma)</div><div class='add'>+		/* the page has been released from the ring */</div><div class='add'>+		WX_CB(skb)-&gt;page_released = true;</div><div class='ctx'> </div><div class='ctx'> 	/* clear contents of rx_buffer */</div><div class='ctx'> 	rx_buffer-&gt;page = NULL;</div><div class='hunk'>@@ -335,11 +269,12 @@ static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,</div><div class='ctx'> 		if (size &lt;= WX_RXBUFFER_256) {</div><div class='ctx'> 			memcpy(__skb_put(skb, size), page_addr,</div><div class='ctx'> 			       ALIGN(size, sizeof(long)));</div><div class='del'>-			rx_buffer-&gt;pagecnt_bias++;</div><div class='del'>-</div><div class='add'>+			page_pool_put_full_page(rx_ring-&gt;page_pool, rx_buffer-&gt;page, true);</div><div class='ctx'> 			return skb;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		skb_mark_for_recycle(skb);</div><div class='add'>+</div><div class='ctx'> 		if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))</div><div class='ctx'> 			WX_CB(skb)-&gt;dma = rx_buffer-&gt;dma;</div><div class='ctx'> </div><div class='hunk'>@@ -382,8 +317,6 @@ static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,</div><div class='ctx'> 	bi-&gt;page_dma = dma;</div><div class='ctx'> 	bi-&gt;page = page;</div><div class='ctx'> 	bi-&gt;page_offset = 0;</div><div class='del'>-	page_ref_add(page, USHRT_MAX - 1);</div><div class='del'>-	bi-&gt;pagecnt_bias = USHRT_MAX;</div><div class='ctx'> </div><div class='ctx'> 	return true;</div><div class='ctx'> }</div><div class='hunk'>@@ -723,7 +656,6 @@ static int wx_clean_rx_irq(struct wx_q_vector *q_vector,</div><div class='ctx'> 		/* exit if we failed to retrieve a buffer */</div><div class='ctx'> 		if (!skb) {</div><div class='ctx'> 			rx_ring-&gt;rx_stats.alloc_rx_buff_failed++;</div><div class='del'>-			rx_buffer-&gt;pagecnt_bias++;</div><div class='ctx'> 			break;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -1636,8 +1568,14 @@ EXPORT_SYMBOL(wx_napi_disable_all);</div><div class='ctx'>  **/</div><div class='ctx'> static void wx_set_rss_queues(struct wx *wx)</div><div class='ctx'> {</div><div class='del'>-	wx-&gt;num_rx_queues = wx-&gt;mac.max_rx_queues;</div><div class='del'>-	wx-&gt;num_tx_queues = wx-&gt;mac.max_tx_queues;</div><div class='add'>+	struct wx_ring_feature *f;</div><div class='add'>+</div><div class='add'>+	/* set mask for 16 queue limit of RSS */</div><div class='add'>+	f = &amp;wx-&gt;ring_feature[RING_F_RSS];</div><div class='add'>+	f-&gt;indices = f-&gt;limit;</div><div class='add'>+</div><div class='add'>+	wx-&gt;num_rx_queues = f-&gt;limit;</div><div class='add'>+	wx-&gt;num_tx_queues = f-&gt;limit;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void wx_set_num_queues(struct wx *wx)</div><div class='hunk'>@@ -1663,35 +1601,51 @@ static int wx_acquire_msix_vectors(struct wx *wx)</div><div class='ctx'> 	struct irq_affinity affd = {0, };</div><div class='ctx'> 	int nvecs, i;</div><div class='ctx'> </div><div class='del'>-	nvecs = min_t(int, num_online_cpus(), wx-&gt;mac.max_msix_vectors);</div><div class='add'>+	/* We start by asking for one vector per queue pair */</div><div class='add'>+	nvecs = max(wx-&gt;num_rx_queues, wx-&gt;num_tx_queues);</div><div class='add'>+	nvecs = min_t(int, nvecs, num_online_cpus());</div><div class='add'>+	nvecs = min_t(int, nvecs, wx-&gt;mac.max_msix_vectors);</div><div class='ctx'> </div><div class='del'>-	wx-&gt;msix_entries = kcalloc(nvecs,</div><div class='del'>-				   sizeof(struct msix_entry),</div><div class='del'>-				   GFP_KERNEL);</div><div class='del'>-	if (!wx-&gt;msix_entries)</div><div class='add'>+	wx-&gt;msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry),</div><div class='add'>+				     GFP_KERNEL);</div><div class='add'>+	if (!wx-&gt;msix_q_entries)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	/* One for non-queue interrupts */</div><div class='add'>+	nvecs += 1;</div><div class='add'>+</div><div class='add'>+	if (!wx-&gt;msix_in_use) {</div><div class='add'>+		wx-&gt;msix_entry = kcalloc(1, sizeof(struct msix_entry),</div><div class='add'>+					 GFP_KERNEL);</div><div class='add'>+		if (!wx-&gt;msix_entry) {</div><div class='add'>+			kfree(wx-&gt;msix_q_entries);</div><div class='add'>+			wx-&gt;msix_q_entries = NULL;</div><div class='add'>+			return -ENOMEM;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	nvecs = pci_alloc_irq_vectors_affinity(wx-&gt;pdev, nvecs,</div><div class='ctx'> 					       nvecs,</div><div class='ctx'> 					       PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,</div><div class='ctx'> 					       &amp;affd);</div><div class='ctx'> 	if (nvecs &lt; 0) {</div><div class='ctx'> 		wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);</div><div class='del'>-		kfree(wx-&gt;msix_entries);</div><div class='del'>-		wx-&gt;msix_entries = NULL;</div><div class='add'>+		kfree(wx-&gt;msix_q_entries);</div><div class='add'>+		wx-&gt;msix_q_entries = NULL;</div><div class='add'>+		kfree(wx-&gt;msix_entry);</div><div class='add'>+		wx-&gt;msix_entry = NULL;</div><div class='ctx'> 		return nvecs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	wx-&gt;msix_entry-&gt;entry = 0;</div><div class='add'>+	wx-&gt;msix_entry-&gt;vector = pci_irq_vector(wx-&gt;pdev, 0);</div><div class='add'>+	nvecs -= 1;</div><div class='ctx'> 	for (i = 0; i &lt; nvecs; i++) {</div><div class='del'>-		wx-&gt;msix_entries[i].entry = i;</div><div class='del'>-		wx-&gt;msix_entries[i].vector = pci_irq_vector(wx-&gt;pdev, i);</div><div class='add'>+		wx-&gt;msix_q_entries[i].entry = i;</div><div class='add'>+		wx-&gt;msix_q_entries[i].vector = pci_irq_vector(wx-&gt;pdev, i + 1);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* one for msix_other */</div><div class='del'>-	nvecs -= 1;</div><div class='ctx'> 	wx-&gt;num_q_vectors = nvecs;</div><div class='del'>-	wx-&gt;num_rx_queues = nvecs;</div><div class='del'>-	wx-&gt;num_tx_queues = nvecs;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1713,9 +1667,11 @@ static int wx_set_interrupt_capability(struct wx *wx)</div><div class='ctx'> 	if (ret == 0 || (ret == -ENOMEM))</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	wx-&gt;num_rx_queues = 1;</div><div class='del'>-	wx-&gt;num_tx_queues = 1;</div><div class='del'>-	wx-&gt;num_q_vectors = 1;</div><div class='add'>+	/* Disable RSS */</div><div class='add'>+	dev_warn(&amp;wx-&gt;pdev-&gt;dev, "Disabling RSS support\n");</div><div class='add'>+	wx-&gt;ring_feature[RING_F_RSS].limit = 1;</div><div class='add'>+</div><div class='add'>+	wx_set_num_queues(wx);</div><div class='ctx'> </div><div class='ctx'> 	/* minmum one for queue, one for misc*/</div><div class='ctx'> 	nvecs = 1;</div><div class='hunk'>@@ -1972,11 +1928,15 @@ void wx_reset_interrupt_capability(struct wx *wx)</div><div class='ctx'> 	if (!pdev-&gt;msi_enabled &amp;&amp; !pdev-&gt;msix_enabled)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	pci_free_irq_vectors(wx-&gt;pdev);</div><div class='ctx'> 	if (pdev-&gt;msix_enabled) {</div><div class='del'>-		kfree(wx-&gt;msix_entries);</div><div class='del'>-		wx-&gt;msix_entries = NULL;</div><div class='add'>+		kfree(wx-&gt;msix_q_entries);</div><div class='add'>+		wx-&gt;msix_q_entries = NULL;</div><div class='add'>+		if (!wx-&gt;msix_in_use) {</div><div class='add'>+			kfree(wx-&gt;msix_entry);</div><div class='add'>+			wx-&gt;msix_entry = NULL;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='add'>+	pci_free_irq_vectors(wx-&gt;pdev);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_reset_interrupt_capability);</div><div class='ctx'> </div><div class='hunk'>@@ -2046,7 +2006,7 @@ void wx_free_irq(struct wx *wx)</div><div class='ctx'> </div><div class='ctx'> 	for (vector = 0; vector &lt; wx-&gt;num_q_vectors; vector++) {</div><div class='ctx'> 		struct wx_q_vector *q_vector = wx-&gt;q_vector[vector];</div><div class='del'>-		struct msix_entry *entry = &amp;wx-&gt;msix_entries[vector];</div><div class='add'>+		struct msix_entry *entry = &amp;wx-&gt;msix_q_entries[vector];</div><div class='ctx'> </div><div class='ctx'> 		/* free only the irqs that were actually requested */</div><div class='ctx'> 		if (!q_vector-&gt;rx.ring &amp;&amp; !q_vector-&gt;tx.ring)</div><div class='hunk'>@@ -2056,7 +2016,7 @@ void wx_free_irq(struct wx *wx)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (wx-&gt;mac.type == wx_mac_em)</div><div class='del'>-		free_irq(wx-&gt;msix_entries[vector].vector, wx);</div><div class='add'>+		free_irq(wx-&gt;msix_entry-&gt;vector, wx);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_free_irq);</div><div class='ctx'> </div><div class='hunk'>@@ -2133,6 +2093,7 @@ static void wx_set_ivar(struct wx *wx, s8 direction,</div><div class='ctx'> 		wr32(wx, WX_PX_MISC_IVAR, ivar);</div><div class='ctx'> 	} else {</div><div class='ctx'> 		/* tx or rx causes */</div><div class='add'>+		msix_vector += 1; /* offset for queue vectors */</div><div class='ctx'> 		msix_vector |= WX_PX_IVAR_ALLOC_VAL;</div><div class='ctx'> 		index = ((16 * (queue &amp; 1)) + (8 * direction));</div><div class='ctx'> 		ivar = rd32(wx, WX_PX_IVAR(queue &gt;&gt; 1));</div><div class='hunk'>@@ -2150,7 +2111,7 @@ static void wx_set_ivar(struct wx *wx, s8 direction,</div><div class='ctx'>  * when it needs to update EITR registers at runtime.  Hardware</div><div class='ctx'>  * specific quirks/differences are taken care of here.</div><div class='ctx'>  */</div><div class='del'>-static void wx_write_eitr(struct wx_q_vector *q_vector)</div><div class='add'>+void wx_write_eitr(struct wx_q_vector *q_vector)</div><div class='ctx'> {</div><div class='ctx'> 	struct wx *wx = q_vector-&gt;wx;</div><div class='ctx'> 	int v_idx = q_vector-&gt;v_idx;</div><div class='hunk'>@@ -2163,7 +2124,7 @@ static void wx_write_eitr(struct wx_q_vector *q_vector)</div><div class='ctx'> </div><div class='ctx'> 	itr_reg |= WX_PX_ITR_CNT_WDIS;</div><div class='ctx'> </div><div class='del'>-	wr32(wx, WX_PX_ITR(v_idx), itr_reg);</div><div class='add'>+	wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -2209,9 +2170,9 @@ void wx_configure_vectors(struct wx *wx)</div><div class='ctx'> 		wx_write_eitr(q_vector);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	wx_set_ivar(wx, -1, 0, v_idx);</div><div class='add'>+	wx_set_ivar(wx, -1, 0, 0);</div><div class='ctx'> 	if (pdev-&gt;msix_enabled)</div><div class='del'>-		wr32(wx, WX_PX_ITR(v_idx), 1950);</div><div class='add'>+		wr32(wx, WX_PX_ITR(0), 1950);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_configure_vectors);</div><div class='ctx'> </div><div class='hunk'>@@ -2248,8 +2209,6 @@ static void wx_clean_rx_ring(struct wx_ring *rx_ring)</div><div class='ctx'> </div><div class='ctx'> 		/* free resources associated with mapping */</div><div class='ctx'> 		page_pool_put_full_page(rx_ring-&gt;page_pool, rx_buffer-&gt;page, false);</div><div class='del'>-		__page_frag_cache_drain(rx_buffer-&gt;page,</div><div class='del'>-					rx_buffer-&gt;pagecnt_bias);</div><div class='ctx'> </div><div class='ctx'> 		i++;</div><div class='ctx'> 		rx_buffer++;</div><div class='hunk'>@@ -2726,11 +2685,14 @@ int wx_set_features(struct net_device *netdev, netdev_features_t features)</div><div class='ctx'> 	netdev_features_t changed = netdev-&gt;features ^ features;</div><div class='ctx'> 	struct wx *wx = netdev_priv(netdev);</div><div class='ctx'> </div><div class='del'>-	if (changed &amp; NETIF_F_RXHASH)</div><div class='add'>+	if (features &amp; NETIF_F_RXHASH) {</div><div class='ctx'> 		wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,</div><div class='ctx'> 		      WX_RDB_RA_CTL_RSS_EN);</div><div class='del'>-	else</div><div class='add'>+		wx-&gt;rss_enabled = true;</div><div class='add'>+	} else {</div><div class='ctx'> 		wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);</div><div class='add'>+		wx-&gt;rss_enabled = false;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (changed &amp;</div><div class='ctx'> 	    (NETIF_F_HW_VLAN_CTAG_RX |</div><div class='hunk'>@@ -2741,4 +2703,71 @@ int wx_set_features(struct net_device *netdev, netdev_features_t features)</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(wx_set_features);</div><div class='ctx'> </div><div class='add'>+void wx_set_ring(struct wx *wx, u32 new_tx_count,</div><div class='add'>+		 u32 new_rx_count, struct wx_ring *temp_ring)</div><div class='add'>+{</div><div class='add'>+	int i, err = 0;</div><div class='add'>+</div><div class='add'>+	/* Setup new Tx resources and free the old Tx resources in that order.</div><div class='add'>+	 * We can then assign the new resources to the rings via a memcpy.</div><div class='add'>+	 * The advantage to this approach is that we are guaranteed to still</div><div class='add'>+	 * have resources even in the case of an allocation failure.</div><div class='add'>+	 */</div><div class='add'>+	if (new_tx_count != wx-&gt;tx_ring_count) {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_tx_queues; i++) {</div><div class='add'>+			memcpy(&amp;temp_ring[i], wx-&gt;tx_ring[i],</div><div class='add'>+			       sizeof(struct wx_ring));</div><div class='add'>+</div><div class='add'>+			temp_ring[i].count = new_tx_count;</div><div class='add'>+			err = wx_setup_tx_resources(&amp;temp_ring[i]);</div><div class='add'>+			if (err) {</div><div class='add'>+				wx_err(wx, "setup new tx resources failed, keep using the old config\n");</div><div class='add'>+				while (i) {</div><div class='add'>+					i--;</div><div class='add'>+					wx_free_tx_resources(&amp;temp_ring[i]);</div><div class='add'>+				}</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_tx_queues; i++) {</div><div class='add'>+			wx_free_tx_resources(wx-&gt;tx_ring[i]);</div><div class='add'>+</div><div class='add'>+			memcpy(wx-&gt;tx_ring[i], &amp;temp_ring[i],</div><div class='add'>+			       sizeof(struct wx_ring));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		wx-&gt;tx_ring_count = new_tx_count;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Repeat the process for the Rx rings if needed */</div><div class='add'>+	if (new_rx_count != wx-&gt;rx_ring_count) {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++) {</div><div class='add'>+			memcpy(&amp;temp_ring[i], wx-&gt;rx_ring[i],</div><div class='add'>+			       sizeof(struct wx_ring));</div><div class='add'>+</div><div class='add'>+			temp_ring[i].count = new_rx_count;</div><div class='add'>+			err = wx_setup_rx_resources(&amp;temp_ring[i]);</div><div class='add'>+			if (err) {</div><div class='add'>+				wx_err(wx, "setup new rx resources failed, keep using the old config\n");</div><div class='add'>+				while (i) {</div><div class='add'>+					i--;</div><div class='add'>+					wx_free_rx_resources(&amp;temp_ring[i]);</div><div class='add'>+				}</div><div class='add'>+				return;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++) {</div><div class='add'>+			wx_free_rx_resources(wx-&gt;rx_ring[i]);</div><div class='add'>+			memcpy(wx-&gt;rx_ring[i], &amp;temp_ring[i],</div><div class='add'>+			       sizeof(struct wx_ring));</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		wx-&gt;rx_ring_count = new_rx_count;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(wx_set_ring);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers.");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_lib.h b/drivers/net/ethernet/wangxun/libwx/wx_lib.h<br/>index df1f4a5951f0..ec909e876720 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_lib.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_lib.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_lib.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_lib.h</a></div><div class='hunk'>@@ -21,6 +21,7 @@ void wx_free_irq(struct wx *wx);</div><div class='ctx'> int wx_setup_isb_resources(struct wx *wx);</div><div class='ctx'> void wx_free_isb_resources(struct wx *wx);</div><div class='ctx'> u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx);</div><div class='add'>+void wx_write_eitr(struct wx_q_vector *q_vector);</div><div class='ctx'> void wx_configure_vectors(struct wx *wx);</div><div class='ctx'> void wx_clean_all_rx_rings(struct wx *wx);</div><div class='ctx'> void wx_clean_all_tx_rings(struct wx *wx);</div><div class='hunk'>@@ -29,5 +30,7 @@ int wx_setup_resources(struct wx *wx);</div><div class='ctx'> void wx_get_stats64(struct net_device *netdev,</div><div class='ctx'> 		    struct rtnl_link_stats64 *stats);</div><div class='ctx'> int wx_set_features(struct net_device *netdev, netdev_features_t features);</div><div class='add'>+void wx_set_ring(struct wx *wx, u32 new_tx_count,</div><div class='add'>+		 u32 new_rx_count, struct wx_ring *temp_ring);</div><div class='ctx'> </div><div class='ctx'> #endif /* _NGBE_LIB_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/libwx/wx_type.h b/drivers/net/ethernet/wangxun/libwx/wx_type.h<br/>index 165e82de772e..b4dc4f341117 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/libwx/wx_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/libwx/wx_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/libwx/wx_type.h</a></div><div class='hunk'>@@ -7,6 +7,7 @@</div><div class='ctx'> #include &lt;linux/bitfield.h&gt;</div><div class='ctx'> #include &lt;linux/netdevice.h&gt;</div><div class='ctx'> #include &lt;linux/if_vlan.h&gt;</div><div class='add'>+#include &lt;linux/phylink.h&gt;</div><div class='ctx'> #include &lt;net/ip.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define WX_NCSI_SUP                             0x8000</div><div class='hunk'>@@ -130,6 +131,15 @@</div><div class='ctx'> #define WX_RDB_PFCMACDAH             0x19214</div><div class='ctx'> #define WX_RDB_LXOFFTXC              0x19218</div><div class='ctx'> #define WX_RDB_LXONTXC               0x1921C</div><div class='add'>+/* Flow Control Registers */</div><div class='add'>+#define WX_RDB_RFCV                  0x19200</div><div class='add'>+#define WX_RDB_RFCL                  0x19220</div><div class='add'>+#define WX_RDB_RFCL_XONE             BIT(31)</div><div class='add'>+#define WX_RDB_RFCH                  0x19260</div><div class='add'>+#define WX_RDB_RFCH_XOFFE            BIT(31)</div><div class='add'>+#define WX_RDB_RFCRT                 0x192A0</div><div class='add'>+#define WX_RDB_RFCC                  0x192A4</div><div class='add'>+#define WX_RDB_RFCC_RFCE_802_3X      BIT(3)</div><div class='ctx'> /* ring assignment */</div><div class='ctx'> #define WX_RDB_PL_CFG(_i)            (0x19300 + ((_i) * 4))</div><div class='ctx'> #define WX_RDB_PL_CFG_L4HDR          BIT(1)</div><div class='hunk'>@@ -137,8 +147,16 @@</div><div class='ctx'> #define WX_RDB_PL_CFG_L2HDR          BIT(3)</div><div class='ctx'> #define WX_RDB_PL_CFG_TUN_TUNHDR     BIT(4)</div><div class='ctx'> #define WX_RDB_PL_CFG_TUN_OUTL2HDR   BIT(5)</div><div class='add'>+#define WX_RDB_RSSTBL(_i)            (0x19400 + ((_i) * 4))</div><div class='add'>+#define WX_RDB_RSSRK(_i)             (0x19480 + ((_i) * 4))</div><div class='ctx'> #define WX_RDB_RA_CTL                0x194F4</div><div class='ctx'> #define WX_RDB_RA_CTL_RSS_EN         BIT(2) /* RSS Enable */</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV4_TCP   BIT(16)</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV4       BIT(17)</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV6       BIT(20)</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV6_TCP   BIT(21)</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV4_UDP   BIT(22)</div><div class='add'>+#define WX_RDB_RA_CTL_RSS_IPV6_UDP   BIT(23)</div><div class='ctx'> </div><div class='ctx'> /******************************* PSR Registers *******************************/</div><div class='ctx'> /* psr control */</div><div class='hunk'>@@ -305,6 +323,7 @@ enum WX_MSCA_CMD_value {</div><div class='ctx'> #define WX_PX_IVAR_ALLOC_VAL         0x80 /* Interrupt Allocation valid */</div><div class='ctx'> #define WX_7K_ITR                    595</div><div class='ctx'> #define WX_12K_ITR                   336</div><div class='add'>+#define WX_20K_ITR                   200</div><div class='ctx'> #define WX_SP_MAX_EITR               0x00000FF8U</div><div class='ctx'> #define WX_EM_MAX_EITR               0x00007FFCU</div><div class='ctx'> </div><div class='hunk'>@@ -330,6 +349,7 @@ enum WX_MSCA_CMD_value {</div><div class='ctx'> #define WX_PX_MPRC(_i)               (0x01020 + ((_i) * 0x40))</div><div class='ctx'> /* PX_RR_CFG bit definitions */</div><div class='ctx'> #define WX_PX_RR_CFG_VLAN            BIT(31)</div><div class='add'>+#define WX_PX_RR_CFG_DROP_EN         BIT(30)</div><div class='ctx'> #define WX_PX_RR_CFG_SPLIT_MODE      BIT(26)</div><div class='ctx'> #define WX_PX_RR_CFG_RR_THER_SHIFT   16</div><div class='ctx'> #define WX_PX_RR_CFG_RR_HDR_SZ       GENMASK(15, 12)</div><div class='hunk'>@@ -367,8 +387,46 @@ enum WX_MSCA_CMD_value {</div><div class='ctx'> #define WX_MAC_STATE_MODIFIED        0x2</div><div class='ctx'> #define WX_MAC_STATE_IN_USE          0x4</div><div class='ctx'> </div><div class='add'>+/* BitTimes (BT) conversion */</div><div class='add'>+#define WX_BT2KB(BT)         (((BT) + (8 * 1024 - 1)) / (8 * 1024))</div><div class='add'>+#define WX_B2BT(BT)          ((BT) * 8)</div><div class='add'>+</div><div class='add'>+/* Calculate Delay to respond to PFC */</div><div class='add'>+#define WX_PFC_D     672</div><div class='add'>+/* Calculate Cable Delay */</div><div class='add'>+#define WX_CABLE_DC  5556 /* Delay Copper */</div><div class='add'>+/* Calculate Delay incurred from higher layer */</div><div class='add'>+#define WX_HD        6144</div><div class='add'>+</div><div class='add'>+/* Calculate Interface Delay */</div><div class='add'>+#define WX_PHY_D     12800</div><div class='add'>+#define WX_MAC_D     4096</div><div class='add'>+#define WX_XAUI_D    (2 * 1024)</div><div class='add'>+#define WX_ID        (WX_MAC_D + WX_XAUI_D + WX_PHY_D)</div><div class='add'>+/* Calculate PCI Bus delay for low thresholds */</div><div class='add'>+#define WX_PCI_DELAY 10000</div><div class='add'>+</div><div class='add'>+/* Calculate delay value in bit times */</div><div class='add'>+#define WX_DV(_max_frame_link, _max_frame_tc) \</div><div class='add'>+	((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \</div><div class='add'>+		(2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \</div><div class='add'>+	 2 * WX_B2BT(_max_frame_tc))</div><div class='add'>+</div><div class='add'>+/* Calculate low threshold delay values */</div><div class='add'>+#define WX_LOW_DV(_max_frame_tc) \</div><div class='add'>+	(2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))</div><div class='add'>+</div><div class='add'>+/* flow control */</div><div class='add'>+#define WX_DEFAULT_FCPAUSE           0xFFFF</div><div class='add'>+</div><div class='ctx'> #define WX_MAX_RXD                   8192</div><div class='ctx'> #define WX_MAX_TXD                   8192</div><div class='add'>+#define WX_MIN_RXD                   128</div><div class='add'>+#define WX_MIN_TXD                   128</div><div class='add'>+</div><div class='add'>+/* Number of Transmit and Receive Descriptors must be a multiple of 8 */</div><div class='add'>+#define WX_REQ_RX_DESCRIPTOR_MULTIPLE   8</div><div class='add'>+#define WX_REQ_TX_DESCRIPTOR_MULTIPLE   8</div><div class='ctx'> </div><div class='ctx'> #define WX_MAX_JUMBO_FRAME_SIZE      9432 /* max payload 9414 */</div><div class='ctx'> #define VMDQ_P(p)                    p</div><div class='hunk'>@@ -787,7 +845,6 @@ struct wx_rx_buffer {</div><div class='ctx'> 	dma_addr_t page_dma;</div><div class='ctx'> 	struct page *page;</div><div class='ctx'> 	unsigned int page_offset;</div><div class='del'>-	u16 pagecnt_bias;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct wx_queue_stats {</div><div class='hunk'>@@ -872,6 +929,19 @@ struct wx_q_vector {</div><div class='ctx'> 	struct wx_ring ring[] ____cacheline_internodealigned_in_smp;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct wx_ring_feature {</div><div class='add'>+	u16 limit;      /* upper limit on feature indices */</div><div class='add'>+	u16 indices;    /* current value of indices */</div><div class='add'>+	u16 mask;       /* Mask used for feature to ring mapping */</div><div class='add'>+	u16 offset;     /* offset to start of feature */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+enum wx_ring_f_enum {</div><div class='add'>+	RING_F_NONE = 0,</div><div class='add'>+	RING_F_RSS,</div><div class='add'>+	RING_F_ARRAY_SIZE  /* must be last in enum set */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> enum wx_isb_idx {</div><div class='ctx'> 	WX_ISB_HEADER,</div><div class='ctx'> 	WX_ISB_MISC,</div><div class='hunk'>@@ -880,6 +950,11 @@ enum wx_isb_idx {</div><div class='ctx'> 	WX_ISB_MAX</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct wx_fc_info {</div><div class='add'>+	u32 high_water; /* Flow Ctrl High-water */</div><div class='add'>+	u32 low_water; /* Flow Ctrl Low-water */</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /* Statistics counters collected by the MAC */</div><div class='ctx'> struct wx_hw_stats {</div><div class='ctx'> 	u64 gprc;</div><div class='hunk'>@@ -920,6 +995,7 @@ struct wx {</div><div class='ctx'> 	enum sp_media_type media_type;</div><div class='ctx'> 	struct wx_eeprom_info eeprom;</div><div class='ctx'> 	struct wx_addr_filter_info addr_ctrl;</div><div class='add'>+	struct wx_fc_info fc;</div><div class='ctx'> 	struct wx_mac_addr *mac_table;</div><div class='ctx'> 	u16 device_id;</div><div class='ctx'> 	u16 vendor_id;</div><div class='hunk'>@@ -940,6 +1016,8 @@ struct wx {</div><div class='ctx'> 	int speed;</div><div class='ctx'> 	int duplex;</div><div class='ctx'> 	struct phy_device *phydev;</div><div class='add'>+	struct phylink *phylink;</div><div class='add'>+	struct phylink_config phylink_config;</div><div class='ctx'> </div><div class='ctx'> 	bool wol_hw_supported;</div><div class='ctx'> 	bool ncsi_enabled;</div><div class='hunk'>@@ -967,7 +1045,10 @@ struct wx {</div><div class='ctx'> 	struct wx_q_vector *q_vector[64];</div><div class='ctx'> </div><div class='ctx'> 	unsigned int queues_per_pool;</div><div class='del'>-	struct msix_entry *msix_entries;</div><div class='add'>+	struct msix_entry *msix_q_entries;</div><div class='add'>+	struct msix_entry *msix_entry;</div><div class='add'>+	bool msix_in_use;</div><div class='add'>+	struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];</div><div class='ctx'> </div><div class='ctx'> 	/* misc interrupt status block */</div><div class='ctx'> 	dma_addr_t isb_dma;</div><div class='hunk'>@@ -975,8 +1056,9 @@ struct wx {</div><div class='ctx'> 	u32 isb_tag[WX_ISB_MAX];</div><div class='ctx'> </div><div class='ctx'> #define WX_MAX_RETA_ENTRIES 128</div><div class='add'>+#define WX_RSS_INDIR_TBL_MAX 64</div><div class='ctx'> 	u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];</div><div class='del'>-</div><div class='add'>+	bool rss_enabled;</div><div class='ctx'> #define WX_RSS_KEY_SIZE     40  /* size of RSS Hash Key in bytes */</div><div class='ctx'> 	u32 *rss_key;</div><div class='ctx'> 	u32 wol;</div><div class='hunk'>@@ -993,7 +1075,7 @@ struct wx {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define WX_INTR_ALL (~0ULL)</div><div class='del'>-#define WX_INTR_Q(i) BIT(i)</div><div class='add'>+#define WX_INTR_Q(i) BIT((i) + 1)</div><div class='ctx'> </div><div class='ctx'> /* register operations */</div><div class='ctx'> #define wr32(a, reg, value)	writel((value), ((a)-&gt;hw_addr + (reg)))</div><div class='hunk'>@@ -1045,4 +1127,9 @@ rd64(struct wx *wx, u32 reg)</div><div class='ctx'> #define wx_dbg(wx, fmt, arg...) \</div><div class='ctx'> 	dev_dbg(&amp;(wx)-&gt;pdev-&gt;dev, fmt, ##arg)</div><div class='ctx'> </div><div class='add'>+static inline struct wx *phylink_to_wx(struct phylink_config *config)</div><div class='add'>+{</div><div class='add'>+	return container_of(config, struct wx, phylink_config);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> #endif /* _WX_TYPE_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c b/drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c<br/>index afbdf6919071..786a652ae64f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_ethtool.c</a></div><div class='hunk'>@@ -7,7 +7,10 @@</div><div class='ctx'> </div><div class='ctx'> #include "../libwx/wx_ethtool.h"</div><div class='ctx'> #include "../libwx/wx_type.h"</div><div class='add'>+#include "../libwx/wx_lib.h"</div><div class='add'>+#include "../libwx/wx_hw.h"</div><div class='ctx'> #include "ngbe_ethtool.h"</div><div class='add'>+#include "ngbe_type.h"</div><div class='ctx'> </div><div class='ctx'> static void ngbe_get_wol(struct net_device *netdev,</div><div class='ctx'> 			 struct ethtool_wolinfo *wol)</div><div class='hunk'>@@ -41,12 +44,75 @@ static int ngbe_set_wol(struct net_device *netdev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ngbe_set_ringparam(struct net_device *netdev,</div><div class='add'>+			      struct ethtool_ringparam *ring,</div><div class='add'>+			      struct kernel_ethtool_ringparam *kernel_ring,</div><div class='add'>+			      struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+	u32 new_rx_count, new_tx_count;</div><div class='add'>+	struct wx_ring *temp_ring;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	new_tx_count = clamp_t(u32, ring-&gt;tx_pending, WX_MIN_TXD, WX_MAX_TXD);</div><div class='add'>+	new_tx_count = ALIGN(new_tx_count, WX_REQ_TX_DESCRIPTOR_MULTIPLE);</div><div class='add'>+</div><div class='add'>+	new_rx_count = clamp_t(u32, ring-&gt;rx_pending, WX_MIN_RXD, WX_MAX_RXD);</div><div class='add'>+	new_rx_count = ALIGN(new_rx_count, WX_REQ_RX_DESCRIPTOR_MULTIPLE);</div><div class='add'>+</div><div class='add'>+	if (new_tx_count == wx-&gt;tx_ring_count &amp;&amp;</div><div class='add'>+	    new_rx_count == wx-&gt;rx_ring_count)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!netif_running(wx-&gt;netdev)) {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_tx_queues; i++)</div><div class='add'>+			wx-&gt;tx_ring[i]-&gt;count = new_tx_count;</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++)</div><div class='add'>+			wx-&gt;rx_ring[i]-&gt;count = new_rx_count;</div><div class='add'>+		wx-&gt;tx_ring_count = new_tx_count;</div><div class='add'>+		wx-&gt;rx_ring_count = new_rx_count;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* allocate temporary buffer to store rings in */</div><div class='add'>+	i = max_t(int, wx-&gt;num_tx_queues, wx-&gt;num_rx_queues);</div><div class='add'>+	temp_ring = kvmalloc_array(i, sizeof(struct wx_ring), GFP_KERNEL);</div><div class='add'>+	if (!temp_ring)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	ngbe_down(wx);</div><div class='add'>+</div><div class='add'>+	wx_set_ring(wx, new_tx_count, new_rx_count, temp_ring);</div><div class='add'>+	kvfree(temp_ring);</div><div class='add'>+</div><div class='add'>+	wx_configure(wx);</div><div class='add'>+	ngbe_up(wx);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int ngbe_set_channels(struct net_device *dev,</div><div class='add'>+			     struct ethtool_channels *ch)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = wx_set_channels(dev, ch);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	/* use setup TC to update any traffic class queue mapping */</div><div class='add'>+	return ngbe_setup_tc(dev, netdev_get_num_tc(dev));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct ethtool_ops ngbe_ethtool_ops = {</div><div class='add'>+	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='add'>+				     ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ,</div><div class='ctx'> 	.get_drvinfo		= wx_get_drvinfo,</div><div class='ctx'> 	.get_link		= ethtool_op_get_link,</div><div class='del'>-	.get_link_ksettings	= phy_ethtool_get_link_ksettings,</div><div class='del'>-	.set_link_ksettings	= phy_ethtool_set_link_ksettings,</div><div class='del'>-	.nway_reset		= phy_ethtool_nway_reset,</div><div class='add'>+	.get_link_ksettings	= wx_get_link_ksettings,</div><div class='add'>+	.set_link_ksettings	= wx_set_link_ksettings,</div><div class='add'>+	.nway_reset		= wx_nway_reset,</div><div class='ctx'> 	.get_wol		= ngbe_get_wol,</div><div class='ctx'> 	.set_wol		= ngbe_set_wol,</div><div class='ctx'> 	.get_sset_count		= wx_get_sset_count,</div><div class='hunk'>@@ -54,6 +120,16 @@ static const struct ethtool_ops ngbe_ethtool_ops = {</div><div class='ctx'> 	.get_ethtool_stats	= wx_get_ethtool_stats,</div><div class='ctx'> 	.get_eth_mac_stats	= wx_get_mac_stats,</div><div class='ctx'> 	.get_pause_stats	= wx_get_pause_stats,</div><div class='add'>+	.get_pauseparam		= wx_get_pauseparam,</div><div class='add'>+	.set_pauseparam		= wx_set_pauseparam,</div><div class='add'>+	.get_ringparam		= wx_get_ringparam,</div><div class='add'>+	.set_ringparam		= ngbe_set_ringparam,</div><div class='add'>+	.get_coalesce		= wx_get_coalesce,</div><div class='add'>+	.set_coalesce		= wx_set_coalesce,</div><div class='add'>+	.get_channels		= wx_get_channels,</div><div class='add'>+	.set_channels		= ngbe_set_channels,</div><div class='add'>+	.get_msglevel		= wx_get_msglevel,</div><div class='add'>+	.set_msglevel		= wx_set_msglevel,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void ngbe_set_ethtool_ops(struct net_device *netdev)</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/ngbe/ngbe_main.c b/drivers/net/ethernet/wangxun/ngbe/ngbe_main.c<br/>index 8db804543e66..fdd6b4f70b7a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/ngbe/ngbe_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_main.c</a></div><div class='hunk'>@@ -80,28 +80,6 @@ static void ngbe_init_type_code(struct wx *wx)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * ngbe_init_rss_key - Initialize wx RSS key</div><div class='del'>- * @wx: device handle</div><div class='del'>- *</div><div class='del'>- * Allocates and initializes the RSS key if it is not allocated.</div><div class='del'>- **/</div><div class='del'>-static inline int ngbe_init_rss_key(struct wx *wx)</div><div class='del'>-{</div><div class='del'>-	u32 *rss_key;</div><div class='del'>-</div><div class='del'>-	if (!wx-&gt;rss_key) {</div><div class='del'>-		rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL);</div><div class='del'>-		if (unlikely(!rss_key))</div><div class='del'>-			return -ENOMEM;</div><div class='del'>-</div><div class='del'>-		netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE);</div><div class='del'>-		wx-&gt;rss_key = rss_key;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/**</div><div class='ctx'>  * ngbe_sw_init - Initialize general software structures</div><div class='ctx'>  * @wx: board private structure to initialize</div><div class='ctx'>  **/</div><div class='hunk'>@@ -134,8 +112,9 @@ static int ngbe_sw_init(struct wx *wx)</div><div class='ctx'> 		dev_err(&amp;pdev-&gt;dev, "Do not support MSI-X\n");</div><div class='ctx'> 	wx-&gt;mac.max_msix_vectors = msix_count;</div><div class='ctx'> </div><div class='del'>-	if (ngbe_init_rss_key(wx))</div><div class='del'>-		return -ENOMEM;</div><div class='add'>+	wx-&gt;ring_feature[RING_F_RSS].limit = min_t(int, NGBE_MAX_RSS_INDICES,</div><div class='add'>+						   num_online_cpus());</div><div class='add'>+	wx-&gt;rss_enabled = true;</div><div class='ctx'> </div><div class='ctx'> 	/* enable itr by default in dynamic mode */</div><div class='ctx'> 	wx-&gt;rx_itr_setting = 1;</div><div class='hunk'>@@ -175,7 +154,7 @@ static void ngbe_irq_enable(struct wx *wx, bool queues)</div><div class='ctx'> 	if (queues)</div><div class='ctx'> 		wx_intr_enable(wx, NGBE_INTR_ALL);</div><div class='ctx'> 	else</div><div class='del'>-		wx_intr_enable(wx, NGBE_INTR_MISC(wx));</div><div class='add'>+		wx_intr_enable(wx, NGBE_INTR_MISC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -241,7 +220,7 @@ static int ngbe_request_msix_irqs(struct wx *wx)</div><div class='ctx'> </div><div class='ctx'> 	for (vector = 0; vector &lt; wx-&gt;num_q_vectors; vector++) {</div><div class='ctx'> 		struct wx_q_vector *q_vector = wx-&gt;q_vector[vector];</div><div class='del'>-		struct msix_entry *entry = &amp;wx-&gt;msix_entries[vector];</div><div class='add'>+		struct msix_entry *entry = &amp;wx-&gt;msix_q_entries[vector];</div><div class='ctx'> </div><div class='ctx'> 		if (q_vector-&gt;tx.ring &amp;&amp; q_vector-&gt;rx.ring)</div><div class='ctx'> 			snprintf(q_vector-&gt;name, sizeof(q_vector-&gt;name) - 1,</div><div class='hunk'>@@ -259,7 +238,7 @@ static int ngbe_request_msix_irqs(struct wx *wx)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	err = request_irq(wx-&gt;msix_entries[vector].vector,</div><div class='add'>+	err = request_irq(wx-&gt;msix_entry-&gt;vector,</div><div class='ctx'> 			  ngbe_msix_other, 0, netdev-&gt;name, wx);</div><div class='ctx'> </div><div class='ctx'> 	if (err) {</div><div class='hunk'>@@ -272,7 +251,7 @@ static int ngbe_request_msix_irqs(struct wx *wx)</div><div class='ctx'> free_queue_irqs:</div><div class='ctx'> 	while (vector) {</div><div class='ctx'> 		vector--;</div><div class='del'>-		free_irq(wx-&gt;msix_entries[vector].vector,</div><div class='add'>+		free_irq(wx-&gt;msix_q_entries[vector].vector,</div><div class='ctx'> 			 wx-&gt;q_vector[vector]);</div><div class='ctx'> 	}</div><div class='ctx'> 	wx_reset_interrupt_capability(wx);</div><div class='hunk'>@@ -334,15 +313,15 @@ static void ngbe_disable_device(struct wx *wx)</div><div class='ctx'> 	wx_update_stats(wx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ngbe_down(struct wx *wx)</div><div class='add'>+void ngbe_down(struct wx *wx)</div><div class='ctx'> {</div><div class='del'>-	phy_stop(wx-&gt;phydev);</div><div class='add'>+	phylink_stop(wx-&gt;phylink);</div><div class='ctx'> 	ngbe_disable_device(wx);</div><div class='ctx'> 	wx_clean_all_tx_rings(wx);</div><div class='ctx'> 	wx_clean_all_rx_rings(wx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ngbe_up(struct wx *wx)</div><div class='add'>+void ngbe_up(struct wx *wx)</div><div class='ctx'> {</div><div class='ctx'> 	wx_configure_vectors(wx);</div><div class='ctx'> </div><div class='hunk'>@@ -359,7 +338,7 @@ static void ngbe_up(struct wx *wx)</div><div class='ctx'> 	if (wx-&gt;gpio_ctrl)</div><div class='ctx'> 		ngbe_sfp_modules_txrx_powerctl(wx, true);</div><div class='ctx'> </div><div class='del'>-	phy_start(wx-&gt;phydev);</div><div class='add'>+	phylink_start(wx-&gt;phylink);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -388,7 +367,7 @@ static int ngbe_open(struct net_device *netdev)</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_free_resources;</div><div class='ctx'> </div><div class='del'>-	err = ngbe_phy_connect(wx);</div><div class='add'>+	err = phylink_connect_phy(wx-&gt;phylink, wx-&gt;phydev);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		goto err_free_irq;</div><div class='ctx'> </div><div class='hunk'>@@ -404,7 +383,7 @@ static int ngbe_open(struct net_device *netdev)</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> err_dis_phy:</div><div class='del'>-	phy_disconnect(wx-&gt;phydev);</div><div class='add'>+	phylink_disconnect_phy(wx-&gt;phylink);</div><div class='ctx'> err_free_irq:</div><div class='ctx'> 	wx_free_irq(wx);</div><div class='ctx'> err_free_resources:</div><div class='hunk'>@@ -430,7 +409,7 @@ static int ngbe_close(struct net_device *netdev)</div><div class='ctx'> 	ngbe_down(wx);</div><div class='ctx'> 	wx_free_irq(wx);</div><div class='ctx'> 	wx_free_resources(wx);</div><div class='del'>-	phy_disconnect(wx-&gt;phydev);</div><div class='add'>+	phylink_disconnect_phy(wx-&gt;phylink);</div><div class='ctx'> 	wx_control_hw(wx, false);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='hunk'>@@ -480,6 +459,39 @@ static void ngbe_shutdown(struct pci_dev *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * ngbe_setup_tc - routine to configure net_device for multiple traffic</div><div class='add'>+ * classes.</div><div class='add'>+ *</div><div class='add'>+ * @dev: net device to configure</div><div class='add'>+ * @tc: number of traffic classes to enable</div><div class='add'>+ */</div><div class='add'>+int ngbe_setup_tc(struct net_device *dev, u8 tc)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	/* Hardware has to reinitialize queues and interrupts to</div><div class='add'>+	 * match packet buffer alignment. Unfortunately, the</div><div class='add'>+	 * hardware is not flexible enough to do this dynamically.</div><div class='add'>+	 */</div><div class='add'>+	if (netif_running(dev))</div><div class='add'>+		ngbe_close(dev);</div><div class='add'>+</div><div class='add'>+	wx_clear_interrupt_scheme(wx);</div><div class='add'>+</div><div class='add'>+	if (tc)</div><div class='add'>+		netdev_set_num_tc(dev, tc);</div><div class='add'>+	else</div><div class='add'>+		netdev_reset_tc(dev);</div><div class='add'>+</div><div class='add'>+	wx_init_interrupt_scheme(wx);</div><div class='add'>+</div><div class='add'>+	if (netif_running(dev))</div><div class='add'>+		ngbe_open(dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops ngbe_netdev_ops = {</div><div class='ctx'> 	.ndo_open               = ngbe_open,</div><div class='ctx'> 	.ndo_stop               = ngbe_close,</div><div class='hunk'>@@ -582,6 +594,7 @@ static int ngbe_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;priv_flags |= IFF_UNICAST_FLT;</div><div class='ctx'> 	netdev-&gt;priv_flags |= IFF_SUPP_NOFCS;</div><div class='add'>+	netdev-&gt;priv_flags |= IFF_LIVE_ADDR_CHANGE;</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;min_mtu = ETH_MIN_MTU;</div><div class='ctx'> 	netdev-&gt;max_mtu = WX_MAX_JUMBO_FRAME_SIZE -</div><div class='hunk'>@@ -680,6 +693,7 @@ static int ngbe_probe(struct pci_dev *pdev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_register:</div><div class='add'>+	phylink_destroy(wx-&gt;phylink);</div><div class='ctx'> 	wx_control_hw(wx, false);</div><div class='ctx'> err_clear_interrupt_scheme:</div><div class='ctx'> 	wx_clear_interrupt_scheme(wx);</div><div class='hunk'>@@ -709,9 +723,11 @@ static void ngbe_remove(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> 	netdev = wx-&gt;netdev;</div><div class='ctx'> 	unregister_netdev(netdev);</div><div class='add'>+	phylink_destroy(wx-&gt;phylink);</div><div class='ctx'> 	pci_release_selected_regions(pdev,</div><div class='ctx'> 				     pci_select_bars(pdev, IORESOURCE_MEM));</div><div class='ctx'> </div><div class='add'>+	kfree(wx-&gt;rss_key);</div><div class='ctx'> 	kfree(wx-&gt;mac_table);</div><div class='ctx'> 	wx_clear_interrupt_scheme(wx);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c b/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c<br/>index 6302ecca71bb..ec54b18c5fe7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c</a></div><div class='hunk'>@@ -56,22 +56,28 @@ static int ngbe_phy_write_reg_c22(struct mii_bus *bus, int phy_addr,</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void ngbe_handle_link_change(struct net_device *dev)</div><div class='add'>+static void ngbe_mac_config(struct phylink_config *config, unsigned int mode,</div><div class='add'>+			    const struct phylink_link_state *state)</div><div class='ctx'> {</div><div class='del'>-	struct wx *wx = netdev_priv(dev);</div><div class='del'>-	struct phy_device *phydev;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ngbe_mac_link_down(struct phylink_config *config,</div><div class='add'>+			       unsigned int mode, phy_interface_t interface)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void ngbe_mac_link_up(struct phylink_config *config,</div><div class='add'>+			     struct phy_device *phy,</div><div class='add'>+			     unsigned int mode, phy_interface_t interface,</div><div class='add'>+			     int speed, int duplex,</div><div class='add'>+			     bool tx_pause, bool rx_pause)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='ctx'> 	u32 lan_speed, reg;</div><div class='ctx'> </div><div class='del'>-	phydev = wx-&gt;phydev;</div><div class='del'>-	if (!(wx-&gt;link != phydev-&gt;link ||</div><div class='del'>-	      wx-&gt;speed != phydev-&gt;speed ||</div><div class='del'>-	      wx-&gt;duplex != phydev-&gt;duplex))</div><div class='del'>-		return;</div><div class='add'>+	wx_fc_enable(wx, tx_pause, rx_pause);</div><div class='ctx'> </div><div class='del'>-	wx-&gt;link = phydev-&gt;link;</div><div class='del'>-	wx-&gt;speed = phydev-&gt;speed;</div><div class='del'>-	wx-&gt;duplex = phydev-&gt;duplex;</div><div class='del'>-	switch (phydev-&gt;speed) {</div><div class='add'>+	switch (speed) {</div><div class='ctx'> 	case SPEED_10:</div><div class='ctx'> 		lan_speed = 0;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -83,54 +89,51 @@ static void ngbe_handle_link_change(struct net_device *dev)</div><div class='ctx'> 		lan_speed = 2;</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	wr32m(wx, NGBE_CFG_LAN_SPEED, 0x3, lan_speed);</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;link) {</div><div class='del'>-		reg = rd32(wx, WX_MAC_TX_CFG);</div><div class='del'>-		reg &amp;= ~WX_MAC_TX_CFG_SPEED_MASK;</div><div class='del'>-		reg |= WX_MAC_TX_CFG_SPEED_1G | WX_MAC_TX_CFG_TE;</div><div class='del'>-		wr32(wx, WX_MAC_TX_CFG, reg);</div><div class='del'>-		/* Re configure MAC RX */</div><div class='del'>-		reg = rd32(wx, WX_MAC_RX_CFG);</div><div class='del'>-		wr32(wx, WX_MAC_RX_CFG, reg);</div><div class='del'>-		wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);</div><div class='del'>-		reg = rd32(wx, WX_MAC_WDG_TIMEOUT);</div><div class='del'>-		wr32(wx, WX_MAC_WDG_TIMEOUT, reg);</div><div class='del'>-	}</div><div class='del'>-	phy_print_status(phydev);</div><div class='add'>+	reg = rd32(wx, WX_MAC_TX_CFG);</div><div class='add'>+	reg &amp;= ~WX_MAC_TX_CFG_SPEED_MASK;</div><div class='add'>+	reg |= WX_MAC_TX_CFG_SPEED_1G | WX_MAC_TX_CFG_TE;</div><div class='add'>+	wr32(wx, WX_MAC_TX_CFG, reg);</div><div class='add'>+</div><div class='add'>+	/* Re configure MAC Rx */</div><div class='add'>+	reg = rd32(wx, WX_MAC_RX_CFG);</div><div class='add'>+	wr32(wx, WX_MAC_RX_CFG, reg);</div><div class='add'>+	wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);</div><div class='add'>+	reg = rd32(wx, WX_MAC_WDG_TIMEOUT);</div><div class='add'>+	wr32(wx, WX_MAC_WDG_TIMEOUT, reg);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-int ngbe_phy_connect(struct wx *wx)</div><div class='add'>+static const struct phylink_mac_ops ngbe_mac_ops = {</div><div class='add'>+	.mac_config = ngbe_mac_config,</div><div class='add'>+	.mac_link_down = ngbe_mac_link_down,</div><div class='add'>+	.mac_link_up = ngbe_mac_link_up,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int ngbe_phylink_init(struct wx *wx)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='add'>+	struct phylink_config *config;</div><div class='add'>+	phy_interface_t phy_mode;</div><div class='add'>+	struct phylink *phylink;</div><div class='ctx'> </div><div class='del'>-	ret = phy_connect_direct(wx-&gt;netdev,</div><div class='del'>-				 wx-&gt;phydev,</div><div class='del'>-				 ngbe_handle_link_change,</div><div class='del'>-				 PHY_INTERFACE_MODE_RGMII_ID);</div><div class='del'>-	if (ret) {</div><div class='del'>-		wx_err(wx, "PHY connect failed.\n");</div><div class='del'>-		return ret;</div><div class='del'>-	}</div><div class='add'>+	config = &amp;wx-&gt;phylink_config;</div><div class='add'>+	config-&gt;dev = &amp;wx-&gt;netdev-&gt;dev;</div><div class='add'>+	config-&gt;type = PHYLINK_NETDEV;</div><div class='add'>+	config-&gt;mac_capabilities = MAC_1000FD | MAC_100FD | MAC_10FD |</div><div class='add'>+				   MAC_SYM_PAUSE | MAC_ASYM_PAUSE;</div><div class='add'>+	config-&gt;mac_managed_pm = true;</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+	phy_mode = PHY_INTERFACE_MODE_RGMII_ID;</div><div class='add'>+	__set_bit(PHY_INTERFACE_MODE_RGMII_ID, config-&gt;supported_interfaces);</div><div class='ctx'> </div><div class='del'>-static void ngbe_phy_fixup(struct wx *wx)</div><div class='del'>-{</div><div class='del'>-	struct phy_device *phydev = wx-&gt;phydev;</div><div class='del'>-	struct ethtool_eee eee;</div><div class='del'>-</div><div class='del'>-	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);</div><div class='del'>-	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);</div><div class='del'>-	phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);</div><div class='del'>-</div><div class='del'>-	phydev-&gt;mac_managed_pm = true;</div><div class='del'>-	if (wx-&gt;mac_type != em_mac_type_mdi)</div><div class='del'>-		return;</div><div class='del'>-	/* disable EEE, internal phy does not support eee */</div><div class='del'>-	memset(&amp;eee, 0, sizeof(eee));</div><div class='del'>-	phy_ethtool_set_eee(phydev, &amp;eee);</div><div class='add'>+	phylink = phylink_create(config, NULL, phy_mode, &amp;ngbe_mac_ops);</div><div class='add'>+	if (IS_ERR(phylink))</div><div class='add'>+		return PTR_ERR(phylink);</div><div class='add'>+</div><div class='add'>+	wx-&gt;phylink = phylink;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int ngbe_mdio_init(struct wx *wx)</div><div class='hunk'>@@ -165,11 +168,16 @@ int ngbe_mdio_init(struct wx *wx)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='ctx'> 	phy_attached_info(wx-&gt;phydev);</div><div class='del'>-	ngbe_phy_fixup(wx);</div><div class='ctx'> </div><div class='ctx'> 	wx-&gt;link = 0;</div><div class='ctx'> 	wx-&gt;speed = 0;</div><div class='ctx'> 	wx-&gt;duplex = 0;</div><div class='ctx'> </div><div class='add'>+	ret = ngbe_phylink_init(wx);</div><div class='add'>+	if (ret) {</div><div class='add'>+		wx_err(wx, "failed to init phylink: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h b/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h<br/>index 0a6400dd89c4..f610b771888a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.h</a></div><div class='hunk'>@@ -7,6 +7,5 @@</div><div class='ctx'> #ifndef _NGBE_MDIO_H_</div><div class='ctx'> #define _NGBE_MDIO_H_</div><div class='ctx'> </div><div class='del'>-int ngbe_phy_connect(struct wx *wx);</div><div class='ctx'> int ngbe_mdio_init(struct wx *wx);</div><div class='ctx'> #endif /* _NGBE_MDIO_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/ngbe/ngbe_type.h b/drivers/net/ethernet/wangxun/ngbe/ngbe_type.h<br/>index ff754d69bdf6..f48ed7fc1805 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/ngbe/ngbe_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/ngbe/ngbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/ngbe/ngbe_type.h</a></div><div class='hunk'>@@ -80,7 +80,7 @@</div><div class='ctx'> 				NGBE_PX_MISC_IEN_GPIO)</div><div class='ctx'> </div><div class='ctx'> #define NGBE_INTR_ALL				0x1FF</div><div class='del'>-#define NGBE_INTR_MISC(A)			BIT((A)-&gt;num_q_vectors)</div><div class='add'>+#define NGBE_INTR_MISC				BIT(0)</div><div class='ctx'> </div><div class='ctx'> #define NGBE_PHY_CONFIG(reg_offset)		(0x14000 + ((reg_offset) * 4))</div><div class='ctx'> #define NGBE_CFG_LAN_SPEED			0x14440</div><div class='hunk'>@@ -105,6 +105,7 @@</div><div class='ctx'> #define NGBE_FW_CMD_ST_FAIL			0x70657376</div><div class='ctx'> </div><div class='ctx'> #define NGBE_MAX_FDIR_INDICES			7</div><div class='add'>+#define NGBE_MAX_RSS_INDICES			8</div><div class='ctx'> </div><div class='ctx'> #define NGBE_MAX_RX_QUEUES			(NGBE_MAX_FDIR_INDICES + 1)</div><div class='ctx'> #define NGBE_MAX_TX_QUEUES			(NGBE_MAX_FDIR_INDICES + 1)</div><div class='hunk'>@@ -130,4 +131,8 @@</div><div class='ctx'> </div><div class='ctx'> extern char ngbe_driver_name[];</div><div class='ctx'> </div><div class='add'>+void ngbe_down(struct wx *wx);</div><div class='add'>+void ngbe_up(struct wx *wx);</div><div class='add'>+int ngbe_setup_tc(struct net_device *dev, u8 tc);</div><div class='add'>+</div><div class='ctx'> #endif /* _NGBE_TYPE_H_ */</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c b/drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c<br/>index 3f336a088e43..db675512ce4d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_ethtool.c</a></div><div class='hunk'>@@ -7,43 +7,93 @@</div><div class='ctx'> </div><div class='ctx'> #include "../libwx/wx_ethtool.h"</div><div class='ctx'> #include "../libwx/wx_type.h"</div><div class='add'>+#include "../libwx/wx_lib.h"</div><div class='ctx'> #include "txgbe_type.h"</div><div class='ctx'> #include "txgbe_ethtool.h"</div><div class='ctx'> </div><div class='del'>-static int txgbe_nway_reset(struct net_device *netdev)</div><div class='add'>+static int txgbe_set_ringparam(struct net_device *netdev,</div><div class='add'>+			       struct ethtool_ringparam *ring,</div><div class='add'>+			       struct kernel_ethtool_ringparam *kernel_ring,</div><div class='add'>+			       struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='del'>-	struct txgbe *txgbe = netdev_to_txgbe(netdev);</div><div class='add'>+	struct wx *wx = netdev_priv(netdev);</div><div class='add'>+	u32 new_rx_count, new_tx_count;</div><div class='add'>+	struct wx_ring *temp_ring;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='del'>-	return phylink_ethtool_nway_reset(txgbe-&gt;phylink);</div><div class='del'>-}</div><div class='add'>+	new_tx_count = clamp_t(u32, ring-&gt;tx_pending, WX_MIN_TXD, WX_MAX_TXD);</div><div class='add'>+	new_tx_count = ALIGN(new_tx_count, WX_REQ_TX_DESCRIPTOR_MULTIPLE);</div><div class='ctx'> </div><div class='del'>-static int txgbe_get_link_ksettings(struct net_device *netdev,</div><div class='del'>-				    struct ethtool_link_ksettings *cmd)</div><div class='del'>-{</div><div class='del'>-	struct txgbe *txgbe = netdev_to_txgbe(netdev);</div><div class='add'>+	new_rx_count = clamp_t(u32, ring-&gt;rx_pending, WX_MIN_RXD, WX_MAX_RXD);</div><div class='add'>+	new_rx_count = ALIGN(new_rx_count, WX_REQ_RX_DESCRIPTOR_MULTIPLE);</div><div class='add'>+</div><div class='add'>+	if (new_tx_count == wx-&gt;tx_ring_count &amp;&amp;</div><div class='add'>+	    new_rx_count == wx-&gt;rx_ring_count)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	if (!netif_running(wx-&gt;netdev)) {</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_tx_queues; i++)</div><div class='add'>+			wx-&gt;tx_ring[i]-&gt;count = new_tx_count;</div><div class='add'>+		for (i = 0; i &lt; wx-&gt;num_rx_queues; i++)</div><div class='add'>+			wx-&gt;rx_ring[i]-&gt;count = new_rx_count;</div><div class='add'>+		wx-&gt;tx_ring_count = new_tx_count;</div><div class='add'>+		wx-&gt;rx_ring_count = new_rx_count;</div><div class='add'>+</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	return phylink_ethtool_ksettings_get(txgbe-&gt;phylink, cmd);</div><div class='add'>+	/* allocate temporary buffer to store rings in */</div><div class='add'>+	i = max_t(int, wx-&gt;num_tx_queues, wx-&gt;num_rx_queues);</div><div class='add'>+	temp_ring = kvmalloc_array(i, sizeof(struct wx_ring), GFP_KERNEL);</div><div class='add'>+	if (!temp_ring)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	txgbe_down(wx);</div><div class='add'>+</div><div class='add'>+	wx_set_ring(wx, new_tx_count, new_rx_count, temp_ring);</div><div class='add'>+	kvfree(temp_ring);</div><div class='add'>+</div><div class='add'>+	txgbe_up(wx);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int txgbe_set_link_ksettings(struct net_device *netdev,</div><div class='del'>-				    const struct ethtool_link_ksettings *cmd)</div><div class='add'>+static int txgbe_set_channels(struct net_device *dev,</div><div class='add'>+			      struct ethtool_channels *ch)</div><div class='ctx'> {</div><div class='del'>-	struct txgbe *txgbe = netdev_to_txgbe(netdev);</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = wx_set_channels(dev, ch);</div><div class='add'>+	if (err &lt; 0)</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='del'>-	return phylink_ethtool_ksettings_set(txgbe-&gt;phylink, cmd);</div><div class='add'>+	/* use setup TC to update any traffic class queue mapping */</div><div class='add'>+	return txgbe_setup_tc(dev, netdev_get_num_tc(dev));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops txgbe_ethtool_ops = {</div><div class='add'>+	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |</div><div class='add'>+				     ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ,</div><div class='ctx'> 	.get_drvinfo		= wx_get_drvinfo,</div><div class='del'>-	.nway_reset		= txgbe_nway_reset,</div><div class='add'>+	.nway_reset		= wx_nway_reset,</div><div class='ctx'> 	.get_link		= ethtool_op_get_link,</div><div class='del'>-	.get_link_ksettings	= txgbe_get_link_ksettings,</div><div class='del'>-	.set_link_ksettings	= txgbe_set_link_ksettings,</div><div class='add'>+	.get_link_ksettings	= wx_get_link_ksettings,</div><div class='add'>+	.set_link_ksettings	= wx_set_link_ksettings,</div><div class='ctx'> 	.get_sset_count		= wx_get_sset_count,</div><div class='ctx'> 	.get_strings		= wx_get_strings,</div><div class='ctx'> 	.get_ethtool_stats	= wx_get_ethtool_stats,</div><div class='ctx'> 	.get_eth_mac_stats	= wx_get_mac_stats,</div><div class='ctx'> 	.get_pause_stats	= wx_get_pause_stats,</div><div class='add'>+	.get_pauseparam		= wx_get_pauseparam,</div><div class='add'>+	.set_pauseparam		= wx_set_pauseparam,</div><div class='add'>+	.get_ringparam		= wx_get_ringparam,</div><div class='add'>+	.set_ringparam		= txgbe_set_ringparam,</div><div class='add'>+	.get_coalesce		= wx_get_coalesce,</div><div class='add'>+	.set_coalesce		= wx_set_coalesce,</div><div class='add'>+	.get_channels		= wx_get_channels,</div><div class='add'>+	.set_channels		= txgbe_set_channels,</div><div class='add'>+	.get_msglevel		= wx_get_msglevel,</div><div class='add'>+	.set_msglevel		= wx_set_msglevel,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> void txgbe_set_ethtool_ops(struct net_device *netdev)</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/txgbe/txgbe_main.c b/drivers/net/ethernet/wangxun/txgbe/txgbe_main.c<br/>index 526250102db2..3b151c410a5c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/txgbe/txgbe_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_main.c</a></div><div class='hunk'>@@ -86,7 +86,7 @@ static void txgbe_irq_enable(struct wx *wx, bool queues)</div><div class='ctx'> 	wr32(wx, WX_PX_MISC_IEN, TXGBE_PX_MISC_IEN_MASK);</div><div class='ctx'> </div><div class='ctx'> 	/* unmask interrupt */</div><div class='del'>-	wx_intr_enable(wx, TXGBE_INTR_MISC(wx));</div><div class='add'>+	wx_intr_enable(wx, TXGBE_INTR_MISC);</div><div class='ctx'> 	if (queues)</div><div class='ctx'> 		wx_intr_enable(wx, TXGBE_INTR_QALL(wx));</div><div class='ctx'> }</div><div class='hunk'>@@ -145,7 +145,7 @@ static int txgbe_request_msix_irqs(struct wx *wx)</div><div class='ctx'> </div><div class='ctx'> 	for (vector = 0; vector &lt; wx-&gt;num_q_vectors; vector++) {</div><div class='ctx'> 		struct wx_q_vector *q_vector = wx-&gt;q_vector[vector];</div><div class='del'>-		struct msix_entry *entry = &amp;wx-&gt;msix_entries[vector];</div><div class='add'>+		struct msix_entry *entry = &amp;wx-&gt;msix_q_entries[vector];</div><div class='ctx'> </div><div class='ctx'> 		if (q_vector-&gt;tx.ring &amp;&amp; q_vector-&gt;rx.ring)</div><div class='ctx'> 			snprintf(q_vector-&gt;name, sizeof(q_vector-&gt;name) - 1,</div><div class='hunk'>@@ -168,7 +168,7 @@ static int txgbe_request_msix_irqs(struct wx *wx)</div><div class='ctx'> free_queue_irqs:</div><div class='ctx'> 	while (vector) {</div><div class='ctx'> 		vector--;</div><div class='del'>-		free_irq(wx-&gt;msix_entries[vector].vector,</div><div class='add'>+		free_irq(wx-&gt;msix_q_entries[vector].vector,</div><div class='ctx'> 			 wx-&gt;q_vector[vector]);</div><div class='ctx'> 	}</div><div class='ctx'> 	wx_reset_interrupt_capability(wx);</div><div class='hunk'>@@ -206,7 +206,6 @@ static int txgbe_request_irq(struct wx *wx)</div><div class='ctx'> static void txgbe_up_complete(struct wx *wx)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *netdev = wx-&gt;netdev;</div><div class='del'>-	struct txgbe *txgbe;</div><div class='ctx'> </div><div class='ctx'> 	wx_control_hw(wx, true);</div><div class='ctx'> 	wx_configure_vectors(wx);</div><div class='hunk'>@@ -215,8 +214,7 @@ static void txgbe_up_complete(struct wx *wx)</div><div class='ctx'> 	smp_mb__before_atomic();</div><div class='ctx'> 	wx_napi_enable_all(wx);</div><div class='ctx'> </div><div class='del'>-	txgbe = netdev_to_txgbe(netdev);</div><div class='del'>-	phylink_start(txgbe-&gt;phylink);</div><div class='add'>+	phylink_start(wx-&gt;phylink);</div><div class='ctx'> </div><div class='ctx'> 	/* clear any pending interrupts, may auto mask */</div><div class='ctx'> 	rd32(wx, WX_PX_IC(0));</div><div class='hunk'>@@ -290,18 +288,22 @@ static void txgbe_disable_device(struct wx *wx)</div><div class='ctx'> 	wx_update_stats(wx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void txgbe_down(struct wx *wx)</div><div class='add'>+void txgbe_down(struct wx *wx)</div><div class='ctx'> {</div><div class='del'>-	struct txgbe *txgbe = netdev_to_txgbe(wx-&gt;netdev);</div><div class='del'>-</div><div class='ctx'> 	txgbe_disable_device(wx);</div><div class='ctx'> 	txgbe_reset(wx);</div><div class='del'>-	phylink_stop(txgbe-&gt;phylink);</div><div class='add'>+	phylink_stop(wx-&gt;phylink);</div><div class='ctx'> </div><div class='ctx'> 	wx_clean_all_tx_rings(wx);</div><div class='ctx'> 	wx_clean_all_rx_rings(wx);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+void txgbe_up(struct wx *wx)</div><div class='add'>+{</div><div class='add'>+	wx_configure(wx);</div><div class='add'>+	txgbe_up_complete(wx);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  *  txgbe_init_type_code - Initialize the shared code</div><div class='ctx'>  *  @wx: pointer to hardware structure</div><div class='hunk'>@@ -376,6 +378,10 @@ static int txgbe_sw_init(struct wx *wx)</div><div class='ctx'> 		wx_err(wx, "Do not support MSI-X\n");</div><div class='ctx'> 	wx-&gt;mac.max_msix_vectors = msix_count;</div><div class='ctx'> </div><div class='add'>+	wx-&gt;ring_feature[RING_F_RSS].limit = min_t(int, TXGBE_MAX_RSS_INDICES,</div><div class='add'>+						   num_online_cpus());</div><div class='add'>+	wx-&gt;rss_enabled = true;</div><div class='add'>+</div><div class='ctx'> 	/* enable itr by default in dynamic mode */</div><div class='ctx'> 	wx-&gt;rx_itr_setting = 1;</div><div class='ctx'> 	wx-&gt;tx_itr_setting = 1;</div><div class='hunk'>@@ -502,6 +508,41 @@ static void txgbe_shutdown(struct pci_dev *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * txgbe_setup_tc - routine to configure net_device for multiple traffic</div><div class='add'>+ * classes.</div><div class='add'>+ *</div><div class='add'>+ * @dev: net device to configure</div><div class='add'>+ * @tc: number of traffic classes to enable</div><div class='add'>+ */</div><div class='add'>+int txgbe_setup_tc(struct net_device *dev, u8 tc)</div><div class='add'>+{</div><div class='add'>+	struct wx *wx = netdev_priv(dev);</div><div class='add'>+</div><div class='add'>+	/* Hardware has to reinitialize queues and interrupts to</div><div class='add'>+	 * match packet buffer alignment. Unfortunately, the</div><div class='add'>+	 * hardware is not flexible enough to do this dynamically.</div><div class='add'>+	 */</div><div class='add'>+	if (netif_running(dev))</div><div class='add'>+		txgbe_close(dev);</div><div class='add'>+	else</div><div class='add'>+		txgbe_reset(wx);</div><div class='add'>+</div><div class='add'>+	wx_clear_interrupt_scheme(wx);</div><div class='add'>+</div><div class='add'>+	if (tc)</div><div class='add'>+		netdev_set_num_tc(dev, tc);</div><div class='add'>+	else</div><div class='add'>+		netdev_reset_tc(dev);</div><div class='add'>+</div><div class='add'>+	wx_init_interrupt_scheme(wx);</div><div class='add'>+</div><div class='add'>+	if (netif_running(dev))</div><div class='add'>+		txgbe_open(dev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops txgbe_netdev_ops = {</div><div class='ctx'> 	.ndo_open               = txgbe_open,</div><div class='ctx'> 	.ndo_stop               = txgbe_close,</div><div class='hunk'>@@ -638,6 +679,7 @@ static int txgbe_probe(struct pci_dev *pdev,</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;priv_flags |= IFF_UNICAST_FLT;</div><div class='ctx'> 	netdev-&gt;priv_flags |= IFF_SUPP_NOFCS;</div><div class='add'>+	netdev-&gt;priv_flags |= IFF_LIVE_ADDR_CHANGE;</div><div class='ctx'> </div><div class='ctx'> 	netdev-&gt;min_mtu = ETH_MIN_MTU;</div><div class='ctx'> 	netdev-&gt;max_mtu = WX_MAX_JUMBO_FRAME_SIZE -</div><div class='hunk'>@@ -775,6 +817,7 @@ static void txgbe_remove(struct pci_dev *pdev)</div><div class='ctx'> 	pci_release_selected_regions(pdev,</div><div class='ctx'> 				     pci_select_bars(pdev, IORESOURCE_MEM));</div><div class='ctx'> </div><div class='add'>+	kfree(wx-&gt;rss_key);</div><div class='ctx'> 	kfree(wx-&gt;mac_table);</div><div class='ctx'> 	wx_clear_interrupt_scheme(wx);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c b/drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c<br/>index b6c06adb8656..1b84d495d14e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c</a></div><div class='hunk'>@@ -159,7 +159,8 @@ static int txgbe_mdio_pcs_init(struct txgbe *txgbe)</div><div class='ctx'> static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,</div><div class='ctx'> 						    phy_interface_t interface)</div><div class='ctx'> {</div><div class='del'>-	struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config-&gt;dev));</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='add'>+	struct txgbe *txgbe = wx-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	if (interface == PHY_INTERFACE_MODE_10GBASER)</div><div class='ctx'> 		return &amp;txgbe-&gt;xpcs-&gt;pcs;</div><div class='hunk'>@@ -175,7 +176,7 @@ static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,</div><div class='ctx'> static void txgbe_mac_link_down(struct phylink_config *config,</div><div class='ctx'> 				unsigned int mode, phy_interface_t interface)</div><div class='ctx'> {</div><div class='del'>-	struct wx *wx = netdev_priv(to_net_dev(config-&gt;dev));</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='ctx'> </div><div class='ctx'> 	wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);</div><div class='ctx'> }</div><div class='hunk'>@@ -186,9 +187,11 @@ static void txgbe_mac_link_up(struct phylink_config *config,</div><div class='ctx'> 			      int speed, int duplex,</div><div class='ctx'> 			      bool tx_pause, bool rx_pause)</div><div class='ctx'> {</div><div class='del'>-	struct wx *wx = netdev_priv(to_net_dev(config-&gt;dev));</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='ctx'> 	u32 txcfg, wdg;</div><div class='ctx'> </div><div class='add'>+	wx_fc_enable(wx, tx_pause, rx_pause);</div><div class='add'>+</div><div class='ctx'> 	txcfg = rd32(wx, WX_MAC_TX_CFG);</div><div class='ctx'> 	txcfg &amp;= ~WX_MAC_TX_CFG_SPEED_MASK;</div><div class='ctx'> </div><div class='hunk'>@@ -217,7 +220,7 @@ static void txgbe_mac_link_up(struct phylink_config *config,</div><div class='ctx'> static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,</div><div class='ctx'> 			     phy_interface_t interface)</div><div class='ctx'> {</div><div class='del'>-	struct wx *wx = netdev_priv(to_net_dev(config-&gt;dev));</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='ctx'> </div><div class='ctx'> 	wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);</div><div class='ctx'> 	wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);</div><div class='hunk'>@@ -228,7 +231,7 @@ static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,</div><div class='ctx'> static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,</div><div class='ctx'> 			    phy_interface_t interface)</div><div class='ctx'> {</div><div class='del'>-	struct wx *wx = netdev_priv(to_net_dev(config-&gt;dev));</div><div class='add'>+	struct wx *wx = phylink_to_wx(config);</div><div class='ctx'> </div><div class='ctx'> 	txgbe_enable_sec_tx_path(wx);</div><div class='ctx'> 	wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);</div><div class='hunk'>@@ -253,10 +256,7 @@ static int txgbe_phylink_init(struct txgbe *txgbe)</div><div class='ctx'> 	phy_interface_t phy_mode;</div><div class='ctx'> 	struct phylink *phylink;</div><div class='ctx'> </div><div class='del'>-	config = devm_kzalloc(&amp;wx-&gt;pdev-&gt;dev, sizeof(*config), GFP_KERNEL);</div><div class='del'>-	if (!config)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='add'>+	config = &amp;wx-&gt;phylink_config;</div><div class='ctx'> 	config-&gt;dev = &amp;wx-&gt;netdev-&gt;dev;</div><div class='ctx'> 	config-&gt;type = PHYLINK_NETDEV;</div><div class='ctx'> 	config-&gt;mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |</div><div class='hunk'>@@ -287,7 +287,7 @@ static int txgbe_phylink_init(struct txgbe *txgbe)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	txgbe-&gt;phylink = phylink;</div><div class='add'>+	wx-&gt;phylink = phylink;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -483,11 +483,11 @@ static void txgbe_irq_handler(struct irq_desc *desc)</div><div class='ctx'> 		    TXGBE_PX_MISC_ETH_AN)) {</div><div class='ctx'> 		u32 reg = rd32(wx, TXGBE_CFG_PORT_ST);</div><div class='ctx'> </div><div class='del'>-		phylink_mac_change(txgbe-&gt;phylink, !!(reg &amp; TXGBE_CFG_PORT_ST_LINK_UP));</div><div class='add'>+		phylink_mac_change(wx-&gt;phylink, !!(reg &amp; TXGBE_CFG_PORT_ST_LINK_UP));</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* unmask interrupt */</div><div class='del'>-	wx_intr_enable(wx, TXGBE_INTR_MISC(wx));</div><div class='add'>+	wx_intr_enable(wx, TXGBE_INTR_MISC);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int txgbe_gpio_init(struct txgbe *txgbe)</div><div class='hunk'>@@ -531,7 +531,12 @@ static int txgbe_gpio_init(struct txgbe *txgbe)</div><div class='ctx'> 				     sizeof(*girq-&gt;parents), GFP_KERNEL);</div><div class='ctx'> 	if (!girq-&gt;parents)</div><div class='ctx'> 		return -ENOMEM;</div><div class='del'>-	girq-&gt;parents[0] = wx-&gt;msix_entries[wx-&gt;num_q_vectors].vector;</div><div class='add'>+</div><div class='add'>+	/* now only suuported on MSI-X interrupt */</div><div class='add'>+	if (!wx-&gt;msix_entry)</div><div class='add'>+		return -EPERM;</div><div class='add'>+</div><div class='add'>+	girq-&gt;parents[0] = wx-&gt;msix_entry-&gt;vector;</div><div class='ctx'> 	girq-&gt;default_type = IRQ_TYPE_NONE;</div><div class='ctx'> 	girq-&gt;handler = handle_bad_irq;</div><div class='ctx'> </div><div class='hunk'>@@ -701,6 +706,7 @@ static int txgbe_ext_phy_init(struct txgbe *txgbe)</div><div class='ctx'> </div><div class='ctx'> int txgbe_init_phy(struct txgbe *txgbe)</div><div class='ctx'> {</div><div class='add'>+	struct wx *wx = txgbe-&gt;wx;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	if (txgbe-&gt;wx-&gt;media_type == sp_media_copper)</div><div class='hunk'>@@ -708,46 +714,48 @@ int txgbe_init_phy(struct txgbe *txgbe)</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_swnodes_register(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to register software nodes\n");</div><div class='add'>+		wx_err(wx, "failed to register software nodes\n");</div><div class='ctx'> 		return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_mdio_pcs_init(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to init mdio pcs: %d\n", ret);</div><div class='add'>+		wx_err(wx, "failed to init mdio pcs: %d\n", ret);</div><div class='ctx'> 		goto err_unregister_swnode;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_phylink_init(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to init phylink\n");</div><div class='add'>+		wx_err(wx, "failed to init phylink\n");</div><div class='ctx'> 		goto err_destroy_xpcs;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_gpio_init(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to init gpio\n");</div><div class='add'>+		wx_err(wx, "failed to init gpio\n");</div><div class='ctx'> 		goto err_destroy_phylink;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_clock_register(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to register clock: %d\n", ret);</div><div class='add'>+		wx_err(wx, "failed to register clock: %d\n", ret);</div><div class='ctx'> 		goto err_destroy_phylink;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_i2c_register(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to init i2c interface: %d\n", ret);</div><div class='add'>+		wx_err(wx, "failed to init i2c interface: %d\n", ret);</div><div class='ctx'> 		goto err_unregister_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = txgbe_sfp_register(txgbe);</div><div class='ctx'> 	if (ret) {</div><div class='del'>-		wx_err(txgbe-&gt;wx, "failed to register sfp\n");</div><div class='add'>+		wx_err(wx, "failed to register sfp\n");</div><div class='ctx'> 		goto err_unregister_i2c;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	wx-&gt;msix_in_use = true;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_unregister_i2c:</div><div class='hunk'>@@ -756,7 +764,7 @@ err_unregister_clk:</div><div class='ctx'> 	clkdev_drop(txgbe-&gt;clock);</div><div class='ctx'> 	clk_unregister(txgbe-&gt;clk);</div><div class='ctx'> err_destroy_phylink:</div><div class='del'>-	phylink_destroy(txgbe-&gt;phylink);</div><div class='add'>+	phylink_destroy(wx-&gt;phylink);</div><div class='ctx'> err_destroy_xpcs:</div><div class='ctx'> 	xpcs_destroy(txgbe-&gt;xpcs);</div><div class='ctx'> err_unregister_swnode:</div><div class='hunk'>@@ -768,8 +776,8 @@ err_unregister_swnode:</div><div class='ctx'> void txgbe_remove_phy(struct txgbe *txgbe)</div><div class='ctx'> {</div><div class='ctx'> 	if (txgbe-&gt;wx-&gt;media_type == sp_media_copper) {</div><div class='del'>-		phylink_disconnect_phy(txgbe-&gt;phylink);</div><div class='del'>-		phylink_destroy(txgbe-&gt;phylink);</div><div class='add'>+		phylink_disconnect_phy(txgbe-&gt;wx-&gt;phylink);</div><div class='add'>+		phylink_destroy(txgbe-&gt;wx-&gt;phylink);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -777,7 +785,8 @@ void txgbe_remove_phy(struct txgbe *txgbe)</div><div class='ctx'> 	platform_device_unregister(txgbe-&gt;i2c_dev);</div><div class='ctx'> 	clkdev_drop(txgbe-&gt;clock);</div><div class='ctx'> 	clk_unregister(txgbe-&gt;clk);</div><div class='del'>-	phylink_destroy(txgbe-&gt;phylink);</div><div class='add'>+	phylink_destroy(txgbe-&gt;wx-&gt;phylink);</div><div class='ctx'> 	xpcs_destroy(txgbe-&gt;xpcs);</div><div class='ctx'> 	software_node_unregister_node_group(txgbe-&gt;nodes.group);</div><div class='add'>+	txgbe-&gt;wx-&gt;msix_in_use = false;</div><div class='ctx'> }</div><div class='head'>diff --git a/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h b/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h<br/>index 3ba9ce43f394..270a6fd9ad0b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/wangxun/txgbe/txgbe_type.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/wangxun/txgbe/txgbe_type.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/wangxun/txgbe/txgbe_type.h</a></div><div class='hunk'>@@ -98,6 +98,7 @@</div><div class='ctx'> </div><div class='ctx'> #define TXGBE_MAX_MSIX_VECTORS          64</div><div class='ctx'> #define TXGBE_MAX_FDIR_INDICES          63</div><div class='add'>+#define TXGBE_MAX_RSS_INDICES           63</div><div class='ctx'> </div><div class='ctx'> #define TXGBE_MAX_RX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)</div><div class='ctx'> #define TXGBE_MAX_TX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)</div><div class='hunk'>@@ -122,19 +123,16 @@</div><div class='ctx'> #define TXGBE_DEFAULT_RX_WORK           128</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='del'>-#define TXGBE_INTR_MISC(A)    BIT((A)-&gt;num_q_vectors)</div><div class='del'>-#define TXGBE_INTR_QALL(A)    (TXGBE_INTR_MISC(A) - 1)</div><div class='add'>+#define TXGBE_INTR_MISC       BIT(0)</div><div class='add'>+#define TXGBE_INTR_QALL(A)    GENMASK((A)-&gt;num_q_vectors, 1)</div><div class='ctx'> </div><div class='ctx'> #define TXGBE_MAX_EITR        GENMASK(11, 3)</div><div class='ctx'> </div><div class='ctx'> extern char txgbe_driver_name[];</div><div class='ctx'> </div><div class='del'>-static inline struct txgbe *netdev_to_txgbe(struct net_device *netdev)</div><div class='del'>-{</div><div class='del'>-	struct wx *wx = netdev_priv(netdev);</div><div class='del'>-</div><div class='del'>-	return wx-&gt;priv;</div><div class='del'>-}</div><div class='add'>+void txgbe_down(struct wx *wx);</div><div class='add'>+void txgbe_up(struct wx *wx);</div><div class='add'>+int txgbe_setup_tc(struct net_device *dev, u8 tc);</div><div class='ctx'> </div><div class='ctx'> #define NODE_PROP(_NAME, _PROP)			\</div><div class='ctx'> 	(const struct software_node) {		\</div><div class='hunk'>@@ -175,7 +173,6 @@ struct txgbe {</div><div class='ctx'> 	struct wx *wx;</div><div class='ctx'> 	struct txgbe_nodes nodes;</div><div class='ctx'> 	struct dw_xpcs *xpcs;</div><div class='del'>-	struct phylink *phylink;</div><div class='ctx'> 	struct platform_device *sfp_dev;</div><div class='ctx'> 	struct platform_device *i2c_dev;</div><div class='ctx'> 	struct clk_lookup *clock;</div><div class='head'>diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig<br/>index 0014729b8865..35d96c633a33 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/xilinx/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/Kconfig</a></div><div class='hunk'>@@ -26,6 +26,7 @@ config XILINX_EMACLITE</div><div class='ctx'> config XILINX_AXI_EMAC</div><div class='ctx'> 	tristate "Xilinx 10/100/1000 AXI Ethernet support"</div><div class='ctx'> 	depends on HAS_IOMEM</div><div class='add'>+	depends on XILINX_DMA</div><div class='ctx'> 	select PHYLINK</div><div class='ctx'> 	help</div><div class='ctx'> 	  This driver supports the 10/100/1000 Ethernet from Xilinx for the</div><div class='head'>diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h<br/>index 575ff9de8985..807ead678551 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/xilinx_axienet.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/xilinx/xilinx_axienet.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/xilinx_axienet.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/xilinx_axienet.h</a></div><div class='hunk'>@@ -14,6 +14,7 @@</div><div class='ctx'> #include &lt;linux/interrupt.h&gt;</div><div class='ctx'> #include &lt;linux/if_vlan.h&gt;</div><div class='ctx'> #include &lt;linux/phylink.h&gt;</div><div class='add'>+#include &lt;linux/skbuff.h&gt;</div><div class='ctx'> </div><div class='ctx'> /* Packet size info */</div><div class='ctx'> #define XAE_HDR_SIZE			14 /* Size of Ethernet header */</div><div class='hunk'>@@ -379,6 +380,22 @@ struct axidma_bd {</div><div class='ctx'> #define XAE_NUM_MISC_CLOCKS 3</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * struct skbuf_dma_descriptor - skb for each dma descriptor</div><div class='add'>+ * @sgl: Pointer for sglist.</div><div class='add'>+ * @desc: Pointer to dma descriptor.</div><div class='add'>+ * @dma_address: dma address of sglist.</div><div class='add'>+ * @skb: Pointer to SKB transferred using DMA</div><div class='add'>+ * @sg_len: number of entries in the sglist.</div><div class='add'>+ */</div><div class='add'>+struct skbuf_dma_descriptor {</div><div class='add'>+	struct scatterlist sgl[MAX_SKB_FRAGS + 1];</div><div class='add'>+	struct dma_async_tx_descriptor *desc;</div><div class='add'>+	dma_addr_t dma_address;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	int sg_len;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * struct axienet_local - axienet private per device data</div><div class='ctx'>  * @ndev:	Pointer for net_device to which it will be attached.</div><div class='ctx'>  * @dev:	Pointer to device structure</div><div class='hunk'>@@ -435,6 +452,15 @@ struct axidma_bd {</div><div class='ctx'>  * @coalesce_usec_rx:	IRQ coalesce delay for RX</div><div class='ctx'>  * @coalesce_count_tx:	Store the irq coalesce on TX side.</div><div class='ctx'>  * @coalesce_usec_tx:	IRQ coalesce delay for TX</div><div class='add'>+ * @use_dmaengine: flag to check dmaengine framework usage.</div><div class='add'>+ * @tx_chan:	TX DMA channel.</div><div class='add'>+ * @rx_chan:	RX DMA channel.</div><div class='add'>+ * @tx_skb_ring: Pointer to TX skb ring buffer array.</div><div class='add'>+ * @rx_skb_ring: Pointer to RX skb ring buffer array.</div><div class='add'>+ * @tx_ring_head: TX skb ring buffer head index.</div><div class='add'>+ * @tx_ring_tail: TX skb ring buffer tail index.</div><div class='add'>+ * @rx_ring_head: RX skb ring buffer head index.</div><div class='add'>+ * @rx_ring_tail: RX skb ring buffer tail index.</div><div class='ctx'>  */</div><div class='ctx'> struct axienet_local {</div><div class='ctx'> 	struct net_device *ndev;</div><div class='hunk'>@@ -499,6 +525,15 @@ struct axienet_local {</div><div class='ctx'> 	u32 coalesce_usec_rx;</div><div class='ctx'> 	u32 coalesce_count_tx;</div><div class='ctx'> 	u32 coalesce_usec_tx;</div><div class='add'>+	u8  use_dmaengine;</div><div class='add'>+	struct dma_chan *tx_chan;</div><div class='add'>+	struct dma_chan *rx_chan;</div><div class='add'>+	struct skbuf_dma_descriptor **tx_skb_ring;</div><div class='add'>+	struct skbuf_dma_descriptor **rx_skb_ring;</div><div class='add'>+	int tx_ring_head;</div><div class='add'>+	int tx_ring_tail;</div><div class='add'>+	int rx_ring_head;</div><div class='add'>+	int rx_ring_tail;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c<br/>index bf6e33990490..aaf780fd4f5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/xilinx_axienet_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ethernet/xilinx/xilinx_axienet_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ethernet/xilinx/xilinx_axienet_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ethernet/xilinx/xilinx_axienet_main.c</a></div><div class='hunk'>@@ -38,6 +38,11 @@</div><div class='ctx'> #include &lt;linux/phy.h&gt;</div><div class='ctx'> #include &lt;linux/mii.h&gt;</div><div class='ctx'> #include &lt;linux/ethtool.h&gt;</div><div class='add'>+#include &lt;linux/dmaengine.h&gt;</div><div class='add'>+#include &lt;linux/dma-mapping.h&gt;</div><div class='add'>+#include &lt;linux/dma/xilinx_dma.h&gt;</div><div class='add'>+#include &lt;linux/circ_buf.h&gt;</div><div class='add'>+#include &lt;net/netdev_queues.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "xilinx_axienet.h"</div><div class='ctx'> </div><div class='hunk'>@@ -47,6 +52,9 @@</div><div class='ctx'> #define TX_BD_NUM_MIN			(MAX_SKB_FRAGS + 1)</div><div class='ctx'> #define TX_BD_NUM_MAX			4096</div><div class='ctx'> #define RX_BD_NUM_MAX			4096</div><div class='add'>+#define DMA_NUM_APP_WORDS		5</div><div class='add'>+#define LEN_APP				4</div><div class='add'>+#define RX_BUF_NUM_DEFAULT		128</div><div class='ctx'> </div><div class='ctx'> /* Must be shorter than length of ethtool_drvinfo.driver field to fit */</div><div class='ctx'> #define DRIVER_NAME		"xaxienet"</div><div class='hunk'>@@ -55,6 +63,8 @@</div><div class='ctx'> </div><div class='ctx'> #define AXIENET_REGS_N		40</div><div class='ctx'> </div><div class='add'>+static void axienet_rx_submit_desc(struct net_device *ndev);</div><div class='add'>+</div><div class='ctx'> /* Match table for of_platform binding */</div><div class='ctx'> static const struct of_device_id axienet_of_match[] = {</div><div class='ctx'> 	{ .compatible = "xlnx,axi-ethernet-1.00.a", },</div><div class='hunk'>@@ -120,6 +130,16 @@ static struct axienet_option axienet_options[] = {</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct skbuf_dma_descriptor *axienet_get_rx_desc(struct axienet_local *lp, int i)</div><div class='add'>+{</div><div class='add'>+	return lp-&gt;rx_skb_ring[i &amp; (RX_BUF_NUM_DEFAULT - 1)];</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct skbuf_dma_descriptor *axienet_get_tx_desc(struct axienet_local *lp, int i)</div><div class='add'>+{</div><div class='add'>+	return lp-&gt;tx_skb_ring[i &amp; (TX_BD_NUM_MAX - 1)];</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * axienet_dma_in32 - Memory mapped Axi DMA register read</div><div class='ctx'>  * @lp:		Pointer to axienet local structure</div><div class='hunk'>@@ -589,10 +609,6 @@ static int axienet_device_reset(struct net_device *ndev)</div><div class='ctx'> 	struct axienet_local *lp = netdev_priv(ndev);</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = __axienet_device_reset(lp);</div><div class='del'>-	if (ret)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='ctx'> 	lp-&gt;max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;</div><div class='ctx'> 	lp-&gt;options |= XAE_OPTION_VLAN;</div><div class='ctx'> 	lp-&gt;options &amp;= (~XAE_OPTION_JUMBO);</div><div class='hunk'>@@ -606,11 +622,17 @@ static int axienet_device_reset(struct net_device *ndev)</div><div class='ctx'> 			lp-&gt;options |= XAE_OPTION_JUMBO;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = axienet_dma_bd_init(ndev);</div><div class='del'>-	if (ret) {</div><div class='del'>-		netdev_err(ndev, "%s: descriptor allocation failed\n",</div><div class='del'>-			   __func__);</div><div class='del'>-		return ret;</div><div class='add'>+	if (!lp-&gt;use_dmaengine) {</div><div class='add'>+		ret = __axienet_device_reset(lp);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		ret = axienet_dma_bd_init(ndev);</div><div class='add'>+		if (ret) {</div><div class='add'>+			netdev_err(ndev, "%s: descriptor allocation failed\n",</div><div class='add'>+				   __func__);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);</div><div class='hunk'>@@ -726,6 +748,128 @@ static inline int axienet_check_tx_bd_space(struct axienet_local *lp,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * axienet_dma_tx_cb - DMA engine callback for TX channel.</div><div class='add'>+ * @data:       Pointer to the axienet_local structure.</div><div class='add'>+ * @result:     error reporting through dmaengine_result.</div><div class='add'>+ * This function is called by dmaengine driver for TX channel to notify</div><div class='add'>+ * that the transmit is done.</div><div class='add'>+ */</div><div class='add'>+static void axienet_dma_tx_cb(void *data, const struct dmaengine_result *result)</div><div class='add'>+{</div><div class='add'>+	struct skbuf_dma_descriptor *skbuf_dma;</div><div class='add'>+	struct axienet_local *lp = data;</div><div class='add'>+	struct netdev_queue *txq;</div><div class='add'>+	int len;</div><div class='add'>+</div><div class='add'>+	skbuf_dma = axienet_get_tx_desc(lp, lp-&gt;tx_ring_tail++);</div><div class='add'>+	len = skbuf_dma-&gt;skb-&gt;len;</div><div class='add'>+	txq = skb_get_tx_queue(lp-&gt;ndev, skbuf_dma-&gt;skb);</div><div class='add'>+	u64_stats_update_begin(&amp;lp-&gt;tx_stat_sync);</div><div class='add'>+	u64_stats_add(&amp;lp-&gt;tx_bytes, len);</div><div class='add'>+	u64_stats_add(&amp;lp-&gt;tx_packets, 1);</div><div class='add'>+	u64_stats_update_end(&amp;lp-&gt;tx_stat_sync);</div><div class='add'>+	dma_unmap_sg(lp-&gt;dev, skbuf_dma-&gt;sgl, skbuf_dma-&gt;sg_len, DMA_TO_DEVICE);</div><div class='add'>+	dev_consume_skb_any(skbuf_dma-&gt;skb);</div><div class='add'>+	netif_txq_completed_wake(txq, 1, len,</div><div class='add'>+				 CIRC_SPACE(lp-&gt;tx_ring_head, lp-&gt;tx_ring_tail, TX_BD_NUM_MAX),</div><div class='add'>+				 2 * MAX_SKB_FRAGS);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * axienet_start_xmit_dmaengine - Starts the transmission.</div><div class='add'>+ * @skb:        sk_buff pointer that contains data to be Txed.</div><div class='add'>+ * @ndev:       Pointer to net_device structure.</div><div class='add'>+ *</div><div class='add'>+ * Return: NETDEV_TX_OK on success or any non space errors.</div><div class='add'>+ *         NETDEV_TX_BUSY when free element in TX skb ring buffer</div><div class='add'>+ *         is not available.</div><div class='add'>+ *</div><div class='add'>+ * This function is invoked to initiate transmission. The</div><div class='add'>+ * function sets the skbs, register dma callback API and submit</div><div class='add'>+ * the dma transaction.</div><div class='add'>+ * Additionally if checksum offloading is supported,</div><div class='add'>+ * it populates AXI Stream Control fields with appropriate values.</div><div class='add'>+ */</div><div class='add'>+static netdev_tx_t</div><div class='add'>+axienet_start_xmit_dmaengine(struct sk_buff *skb, struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct dma_async_tx_descriptor *dma_tx_desc = NULL;</div><div class='add'>+	struct axienet_local *lp = netdev_priv(ndev);</div><div class='add'>+	u32 app_metadata[DMA_NUM_APP_WORDS] = {0};</div><div class='add'>+	struct skbuf_dma_descriptor *skbuf_dma;</div><div class='add'>+	struct dma_device *dma_dev;</div><div class='add'>+	struct netdev_queue *txq;</div><div class='add'>+	u32 csum_start_off;</div><div class='add'>+	u32 csum_index_off;</div><div class='add'>+	int sg_len;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	dma_dev = lp-&gt;tx_chan-&gt;device;</div><div class='add'>+	sg_len = skb_shinfo(skb)-&gt;nr_frags + 1;</div><div class='add'>+	if (CIRC_SPACE(lp-&gt;tx_ring_head, lp-&gt;tx_ring_tail, TX_BD_NUM_MAX) &lt;= sg_len) {</div><div class='add'>+		netif_stop_queue(ndev);</div><div class='add'>+		if (net_ratelimit())</div><div class='add'>+			netdev_warn(ndev, "TX ring unexpectedly full\n");</div><div class='add'>+		return NETDEV_TX_BUSY;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	skbuf_dma = axienet_get_tx_desc(lp, lp-&gt;tx_ring_head);</div><div class='add'>+	if (!skbuf_dma)</div><div class='add'>+		goto xmit_error_drop_skb;</div><div class='add'>+</div><div class='add'>+	lp-&gt;tx_ring_head++;</div><div class='add'>+	sg_init_table(skbuf_dma-&gt;sgl, sg_len);</div><div class='add'>+	ret = skb_to_sgvec(skb, skbuf_dma-&gt;sgl, 0, skb-&gt;len);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		goto xmit_error_drop_skb;</div><div class='add'>+</div><div class='add'>+	ret = dma_map_sg(lp-&gt;dev, skbuf_dma-&gt;sgl, sg_len, DMA_TO_DEVICE);</div><div class='add'>+	if (!ret)</div><div class='add'>+		goto xmit_error_drop_skb;</div><div class='add'>+</div><div class='add'>+	/* Fill up app fields for checksum */</div><div class='add'>+	if (skb-&gt;ip_summed == CHECKSUM_PARTIAL) {</div><div class='add'>+		if (lp-&gt;features &amp; XAE_FEATURE_FULL_TX_CSUM) {</div><div class='add'>+			/* Tx Full Checksum Offload Enabled */</div><div class='add'>+			app_metadata[0] |= 2;</div><div class='add'>+		} else if (lp-&gt;features &amp; XAE_FEATURE_PARTIAL_TX_CSUM) {</div><div class='add'>+			csum_start_off = skb_transport_offset(skb);</div><div class='add'>+			csum_index_off = csum_start_off + skb-&gt;csum_offset;</div><div class='add'>+			/* Tx Partial Checksum Offload Enabled */</div><div class='add'>+			app_metadata[0] |= 1;</div><div class='add'>+			app_metadata[1] = (csum_start_off &lt;&lt; 16) | csum_index_off;</div><div class='add'>+		}</div><div class='add'>+	} else if (skb-&gt;ip_summed == CHECKSUM_UNNECESSARY) {</div><div class='add'>+		app_metadata[0] |= 2; /* Tx Full Checksum Offload Enabled */</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dma_tx_desc = dma_dev-&gt;device_prep_slave_sg(lp-&gt;tx_chan, skbuf_dma-&gt;sgl,</div><div class='add'>+			sg_len, DMA_MEM_TO_DEV,</div><div class='add'>+			DMA_PREP_INTERRUPT, (void *)app_metadata);</div><div class='add'>+	if (!dma_tx_desc)</div><div class='add'>+		goto xmit_error_unmap_sg;</div><div class='add'>+</div><div class='add'>+	skbuf_dma-&gt;skb = skb;</div><div class='add'>+	skbuf_dma-&gt;sg_len = sg_len;</div><div class='add'>+	dma_tx_desc-&gt;callback_param = lp;</div><div class='add'>+	dma_tx_desc-&gt;callback_result = axienet_dma_tx_cb;</div><div class='add'>+	dmaengine_submit(dma_tx_desc);</div><div class='add'>+	dma_async_issue_pending(lp-&gt;tx_chan);</div><div class='add'>+	txq = skb_get_tx_queue(lp-&gt;ndev, skb);</div><div class='add'>+	netdev_tx_sent_queue(txq, skb-&gt;len);</div><div class='add'>+	netif_txq_maybe_stop(txq, CIRC_SPACE(lp-&gt;tx_ring_head, lp-&gt;tx_ring_tail, TX_BD_NUM_MAX),</div><div class='add'>+			     MAX_SKB_FRAGS + 1, 2 * MAX_SKB_FRAGS);</div><div class='add'>+</div><div class='add'>+	return NETDEV_TX_OK;</div><div class='add'>+</div><div class='add'>+xmit_error_unmap_sg:</div><div class='add'>+	dma_unmap_sg(lp-&gt;dev, skbuf_dma-&gt;sgl, sg_len, DMA_TO_DEVICE);</div><div class='add'>+xmit_error_drop_skb:</div><div class='add'>+	dev_kfree_skb_any(skb);</div><div class='add'>+	return NETDEV_TX_OK;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * axienet_tx_poll - Invoked once a transmit is completed by the</div><div class='ctx'>  * Axi DMA Tx channel.</div><div class='ctx'>  * @napi:	Pointer to NAPI structure.</div><div class='hunk'>@@ -892,6 +1036,42 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * axienet_dma_rx_cb - DMA engine callback for RX channel.</div><div class='add'>+ * @data:       Pointer to the skbuf_dma_descriptor structure.</div><div class='add'>+ * @result:     error reporting through dmaengine_result.</div><div class='add'>+ * This function is called by dmaengine driver for RX channel to notify</div><div class='add'>+ * that the packet is received.</div><div class='add'>+ */</div><div class='add'>+static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *result)</div><div class='add'>+{</div><div class='add'>+	struct skbuf_dma_descriptor *skbuf_dma;</div><div class='add'>+	size_t meta_len, meta_max_len, rx_len;</div><div class='add'>+	struct axienet_local *lp = data;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	u32 *app_metadata;</div><div class='add'>+</div><div class='add'>+	skbuf_dma = axienet_get_rx_desc(lp, lp-&gt;rx_ring_tail++);</div><div class='add'>+	skb = skbuf_dma-&gt;skb;</div><div class='add'>+	app_metadata = dmaengine_desc_get_metadata_ptr(skbuf_dma-&gt;desc, &amp;meta_len,</div><div class='add'>+						       &amp;meta_max_len);</div><div class='add'>+	dma_unmap_single(lp-&gt;dev, skbuf_dma-&gt;dma_address, lp-&gt;max_frm_size,</div><div class='add'>+			 DMA_FROM_DEVICE);</div><div class='add'>+	/* TODO: Derive app word index programmatically */</div><div class='add'>+	rx_len = (app_metadata[LEN_APP] &amp; 0xFFFF);</div><div class='add'>+	skb_put(skb, rx_len);</div><div class='add'>+	skb-&gt;protocol = eth_type_trans(skb, lp-&gt;ndev);</div><div class='add'>+	skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='add'>+</div><div class='add'>+	__netif_rx(skb);</div><div class='add'>+	u64_stats_update_begin(&amp;lp-&gt;rx_stat_sync);</div><div class='add'>+	u64_stats_add(&amp;lp-&gt;rx_packets, 1);</div><div class='add'>+	u64_stats_add(&amp;lp-&gt;rx_bytes, rx_len);</div><div class='add'>+	u64_stats_update_end(&amp;lp-&gt;rx_stat_sync);</div><div class='add'>+	axienet_rx_submit_desc(lp-&gt;ndev);</div><div class='add'>+	dma_async_issue_pending(lp-&gt;rx_chan);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * axienet_rx_poll - Triggered by RX ISR to complete the BD processing.</div><div class='ctx'>  * @napi:	Pointer to NAPI structure.</div><div class='ctx'>  * @budget:	Max number of RX packets to process.</div><div class='hunk'>@@ -1125,40 +1305,158 @@ static irqreturn_t axienet_eth_irq(int irq, void *_ndev)</div><div class='ctx'> static void axienet_dma_err_handler(struct work_struct *work);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='del'>- * axienet_open - Driver open routine.</div><div class='del'>- * @ndev:	Pointer to net_device structure</div><div class='add'>+ * axienet_rx_submit_desc - Submit the rx descriptors to dmaengine.</div><div class='add'>+ * allocate skbuff, map the scatterlist and obtain a descriptor</div><div class='add'>+ * and then add the callback information and submit descriptor.</div><div class='add'>+ *</div><div class='add'>+ * @ndev:	net_device pointer</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static void axienet_rx_submit_desc(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	struct dma_async_tx_descriptor *dma_rx_desc = NULL;</div><div class='add'>+	struct axienet_local *lp = netdev_priv(ndev);</div><div class='add'>+	struct skbuf_dma_descriptor *skbuf_dma;</div><div class='add'>+	struct sk_buff *skb;</div><div class='add'>+	dma_addr_t addr;</div><div class='add'>+</div><div class='add'>+	skbuf_dma = axienet_get_rx_desc(lp, lp-&gt;rx_ring_head);</div><div class='add'>+	if (!skbuf_dma)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	lp-&gt;rx_ring_head++;</div><div class='add'>+	skb = netdev_alloc_skb(ndev, lp-&gt;max_frm_size);</div><div class='add'>+	if (!skb)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	sg_init_table(skbuf_dma-&gt;sgl, 1);</div><div class='add'>+	addr = dma_map_single(lp-&gt;dev, skb-&gt;data, lp-&gt;max_frm_size, DMA_FROM_DEVICE);</div><div class='add'>+	if (unlikely(dma_mapping_error(lp-&gt;dev, addr))) {</div><div class='add'>+		if (net_ratelimit())</div><div class='add'>+			netdev_err(ndev, "DMA mapping error\n");</div><div class='add'>+		goto rx_submit_err_free_skb;</div><div class='add'>+	}</div><div class='add'>+	sg_dma_address(skbuf_dma-&gt;sgl) = addr;</div><div class='add'>+	sg_dma_len(skbuf_dma-&gt;sgl) = lp-&gt;max_frm_size;</div><div class='add'>+	dma_rx_desc = dmaengine_prep_slave_sg(lp-&gt;rx_chan, skbuf_dma-&gt;sgl,</div><div class='add'>+					      1, DMA_DEV_TO_MEM,</div><div class='add'>+					      DMA_PREP_INTERRUPT);</div><div class='add'>+	if (!dma_rx_desc)</div><div class='add'>+		goto rx_submit_err_unmap_skb;</div><div class='add'>+</div><div class='add'>+	skbuf_dma-&gt;skb = skb;</div><div class='add'>+	skbuf_dma-&gt;dma_address = sg_dma_address(skbuf_dma-&gt;sgl);</div><div class='add'>+	skbuf_dma-&gt;desc = dma_rx_desc;</div><div class='add'>+	dma_rx_desc-&gt;callback_param = lp;</div><div class='add'>+	dma_rx_desc-&gt;callback_result = axienet_dma_rx_cb;</div><div class='add'>+	dmaengine_submit(dma_rx_desc);</div><div class='add'>+</div><div class='add'>+	return;</div><div class='add'>+</div><div class='add'>+rx_submit_err_unmap_skb:</div><div class='add'>+	dma_unmap_single(lp-&gt;dev, addr, lp-&gt;max_frm_size, DMA_FROM_DEVICE);</div><div class='add'>+rx_submit_err_free_skb:</div><div class='add'>+	dev_kfree_skb(skb);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * axienet_init_dmaengine - init the dmaengine code.</div><div class='add'>+ * @ndev:       Pointer to net_device structure</div><div class='ctx'>  *</div><div class='ctx'>  * Return: 0, on success.</div><div class='del'>- *	    non-zero error value on failure</div><div class='add'>+ *          non-zero error value on failure</div><div class='ctx'>  *</div><div class='del'>- * This is the driver open routine. It calls phylink_start to start the</div><div class='del'>- * PHY device.</div><div class='del'>- * It also allocates interrupt service routines, enables the interrupt lines</div><div class='del'>- * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer</div><div class='del'>- * descriptors are initialized.</div><div class='add'>+ * This is the dmaengine initialization code.</div><div class='ctx'>  */</div><div class='del'>-static int axienet_open(struct net_device *ndev)</div><div class='add'>+static int axienet_init_dmaengine(struct net_device *ndev)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='ctx'> 	struct axienet_local *lp = netdev_priv(ndev);</div><div class='add'>+	struct skbuf_dma_descriptor *skbuf_dma;</div><div class='add'>+	int i, ret;</div><div class='ctx'> </div><div class='del'>-	dev_dbg(&amp;ndev-&gt;dev, "axienet_open()\n");</div><div class='add'>+	lp-&gt;tx_chan = dma_request_chan(lp-&gt;dev, "tx_chan0");</div><div class='add'>+	if (IS_ERR(lp-&gt;tx_chan)) {</div><div class='add'>+		dev_err(lp-&gt;dev, "No Ethernet DMA (TX) channel found\n");</div><div class='add'>+		return PTR_ERR(lp-&gt;tx_chan);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	/* When we do an Axi Ethernet reset, it resets the complete core</div><div class='del'>-	 * including the MDIO. MDIO must be disabled before resetting.</div><div class='del'>-	 * Hold MDIO bus lock to avoid MDIO accesses during the reset.</div><div class='del'>-	 */</div><div class='del'>-	axienet_lock_mii(lp);</div><div class='del'>-	ret = axienet_device_reset(ndev);</div><div class='del'>-	axienet_unlock_mii(lp);</div><div class='add'>+	lp-&gt;rx_chan = dma_request_chan(lp-&gt;dev, "rx_chan0");</div><div class='add'>+	if (IS_ERR(lp-&gt;rx_chan)) {</div><div class='add'>+		ret = PTR_ERR(lp-&gt;rx_chan);</div><div class='add'>+		dev_err(lp-&gt;dev, "No Ethernet DMA (RX) channel found\n");</div><div class='add'>+		goto err_dma_release_tx;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	ret = phylink_of_phy_connect(lp-&gt;phylink, lp-&gt;dev-&gt;of_node, 0);</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(lp-&gt;dev, "phylink_of_phy_connect() failed: %d\n", ret);</div><div class='del'>-		return ret;</div><div class='add'>+	lp-&gt;tx_ring_tail = 0;</div><div class='add'>+	lp-&gt;tx_ring_head = 0;</div><div class='add'>+	lp-&gt;rx_ring_tail = 0;</div><div class='add'>+	lp-&gt;rx_ring_head = 0;</div><div class='add'>+	lp-&gt;tx_skb_ring = kcalloc(TX_BD_NUM_MAX, sizeof(*lp-&gt;tx_skb_ring),</div><div class='add'>+				  GFP_KERNEL);</div><div class='add'>+	if (!lp-&gt;tx_skb_ring) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_dma_release_rx;</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; TX_BD_NUM_MAX; i++) {</div><div class='add'>+		skbuf_dma = kzalloc(sizeof(*skbuf_dma), GFP_KERNEL);</div><div class='add'>+		if (!skbuf_dma) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto err_free_tx_skb_ring;</div><div class='add'>+		}</div><div class='add'>+		lp-&gt;tx_skb_ring[i] = skbuf_dma;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	phylink_start(lp-&gt;phylink);</div><div class='add'>+	lp-&gt;rx_skb_ring = kcalloc(RX_BUF_NUM_DEFAULT, sizeof(*lp-&gt;rx_skb_ring),</div><div class='add'>+				  GFP_KERNEL);</div><div class='add'>+	if (!lp-&gt;rx_skb_ring) {</div><div class='add'>+		ret = -ENOMEM;</div><div class='add'>+		goto err_free_tx_skb_ring;</div><div class='add'>+	}</div><div class='add'>+	for (i = 0; i &lt; RX_BUF_NUM_DEFAULT; i++) {</div><div class='add'>+		skbuf_dma = kzalloc(sizeof(*skbuf_dma), GFP_KERNEL);</div><div class='add'>+		if (!skbuf_dma) {</div><div class='add'>+			ret = -ENOMEM;</div><div class='add'>+			goto err_free_rx_skb_ring;</div><div class='add'>+		}</div><div class='add'>+		lp-&gt;rx_skb_ring[i] = skbuf_dma;</div><div class='add'>+	}</div><div class='add'>+	/* TODO: Instead of BD_NUM_DEFAULT use runtime support */</div><div class='add'>+	for (i = 0; i &lt; RX_BUF_NUM_DEFAULT; i++)</div><div class='add'>+		axienet_rx_submit_desc(ndev);</div><div class='add'>+	dma_async_issue_pending(lp-&gt;rx_chan);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_free_rx_skb_ring:</div><div class='add'>+	for (i = 0; i &lt; RX_BUF_NUM_DEFAULT; i++)</div><div class='add'>+		kfree(lp-&gt;rx_skb_ring[i]);</div><div class='add'>+	kfree(lp-&gt;rx_skb_ring);</div><div class='add'>+err_free_tx_skb_ring:</div><div class='add'>+	for (i = 0; i &lt; TX_BD_NUM_MAX; i++)</div><div class='add'>+		kfree(lp-&gt;tx_skb_ring[i]);</div><div class='add'>+	kfree(lp-&gt;tx_skb_ring);</div><div class='add'>+err_dma_release_rx:</div><div class='add'>+	dma_release_channel(lp-&gt;rx_chan);</div><div class='add'>+err_dma_release_tx:</div><div class='add'>+	dma_release_channel(lp-&gt;tx_chan);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * axienet_init_legacy_dma - init the dma legacy code.</div><div class='add'>+ * @ndev:       Pointer to net_device structure</div><div class='add'>+ *</div><div class='add'>+ * Return: 0, on success.</div><div class='add'>+ *          non-zero error value on failure</div><div class='add'>+ *</div><div class='add'>+ * This is the dma  initialization code. It also allocates interrupt</div><div class='add'>+ * service routines, enables the interrupt lines and ISR handling.</div><div class='add'>+ *</div><div class='add'>+ */</div><div class='add'>+static int axienet_init_legacy_dma(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct axienet_local *lp = netdev_priv(ndev);</div><div class='ctx'> </div><div class='ctx'> 	/* Enable worker thread for Axi DMA error handling */</div><div class='ctx'> 	INIT_WORK(&amp;lp-&gt;dma_err_task, axienet_dma_err_handler);</div><div class='hunk'>@@ -1193,14 +1491,77 @@ err_rx_irq:</div><div class='ctx'> err_tx_irq:</div><div class='ctx'> 	napi_disable(&amp;lp-&gt;napi_tx);</div><div class='ctx'> 	napi_disable(&amp;lp-&gt;napi_rx);</div><div class='del'>-	phylink_stop(lp-&gt;phylink);</div><div class='del'>-	phylink_disconnect_phy(lp-&gt;phylink);</div><div class='ctx'> 	cancel_work_sync(&amp;lp-&gt;dma_err_task);</div><div class='ctx'> 	dev_err(lp-&gt;dev, "request_irq() failed\n");</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * axienet_open - Driver open routine.</div><div class='add'>+ * @ndev:	Pointer to net_device structure</div><div class='add'>+ *</div><div class='add'>+ * Return: 0, on success.</div><div class='add'>+ *	    non-zero error value on failure</div><div class='add'>+ *</div><div class='add'>+ * This is the driver open routine. It calls phylink_start to start the</div><div class='add'>+ * PHY device.</div><div class='add'>+ * It also allocates interrupt service routines, enables the interrupt lines</div><div class='add'>+ * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer</div><div class='add'>+ * descriptors are initialized.</div><div class='add'>+ */</div><div class='add'>+static int axienet_open(struct net_device *ndev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+	struct axienet_local *lp = netdev_priv(ndev);</div><div class='add'>+</div><div class='add'>+	dev_dbg(&amp;ndev-&gt;dev, "%s\n", __func__);</div><div class='add'>+</div><div class='add'>+	/* When we do an Axi Ethernet reset, it resets the complete core</div><div class='add'>+	 * including the MDIO. MDIO must be disabled before resetting.</div><div class='add'>+	 * Hold MDIO bus lock to avoid MDIO accesses during the reset.</div><div class='add'>+	 */</div><div class='add'>+	axienet_lock_mii(lp);</div><div class='add'>+	ret = axienet_device_reset(ndev);</div><div class='add'>+	axienet_unlock_mii(lp);</div><div class='add'>+</div><div class='add'>+	ret = phylink_of_phy_connect(lp-&gt;phylink, lp-&gt;dev-&gt;of_node, 0);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(lp-&gt;dev, "phylink_of_phy_connect() failed: %d\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	phylink_start(lp-&gt;phylink);</div><div class='add'>+</div><div class='add'>+	if (lp-&gt;use_dmaengine) {</div><div class='add'>+		/* Enable interrupts for Axi Ethernet core (if defined) */</div><div class='add'>+		if (lp-&gt;eth_irq &gt; 0) {</div><div class='add'>+			ret = request_irq(lp-&gt;eth_irq, axienet_eth_irq, IRQF_SHARED,</div><div class='add'>+					  ndev-&gt;name, ndev);</div><div class='add'>+			if (ret)</div><div class='add'>+				goto err_phy;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		ret = axienet_init_dmaengine(ndev);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			goto err_free_eth_irq;</div><div class='add'>+	} else {</div><div class='add'>+		ret = axienet_init_legacy_dma(ndev);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto err_phy;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_free_eth_irq:</div><div class='add'>+	if (lp-&gt;eth_irq &gt; 0)</div><div class='add'>+		free_irq(lp-&gt;eth_irq, ndev);</div><div class='add'>+err_phy:</div><div class='add'>+	phylink_stop(lp-&gt;phylink);</div><div class='add'>+	phylink_disconnect_phy(lp-&gt;phylink);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * axienet_stop - Driver stop routine.</div><div class='ctx'>  * @ndev:	Pointer to net_device structure</div><div class='ctx'>  *</div><div class='hunk'>@@ -1213,11 +1574,14 @@ err_tx_irq:</div><div class='ctx'> static int axienet_stop(struct net_device *ndev)</div><div class='ctx'> {</div><div class='ctx'> 	struct axienet_local *lp = netdev_priv(ndev);</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	dev_dbg(&amp;ndev-&gt;dev, "axienet_close()\n");</div><div class='ctx'> </div><div class='del'>-	napi_disable(&amp;lp-&gt;napi_tx);</div><div class='del'>-	napi_disable(&amp;lp-&gt;napi_rx);</div><div class='add'>+	if (!lp-&gt;use_dmaengine) {</div><div class='add'>+		napi_disable(&amp;lp-&gt;napi_tx);</div><div class='add'>+		napi_disable(&amp;lp-&gt;napi_rx);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	phylink_stop(lp-&gt;phylink);</div><div class='ctx'> 	phylink_disconnect_phy(lp-&gt;phylink);</div><div class='hunk'>@@ -1225,18 +1589,33 @@ static int axienet_stop(struct net_device *ndev)</div><div class='ctx'> 	axienet_setoptions(ndev, lp-&gt;options &amp;</div><div class='ctx'> 			   ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));</div><div class='ctx'> </div><div class='del'>-	axienet_dma_stop(lp);</div><div class='add'>+	if (!lp-&gt;use_dmaengine) {</div><div class='add'>+		axienet_dma_stop(lp);</div><div class='add'>+		cancel_work_sync(&amp;lp-&gt;dma_err_task);</div><div class='add'>+		free_irq(lp-&gt;tx_irq, ndev);</div><div class='add'>+		free_irq(lp-&gt;rx_irq, ndev);</div><div class='add'>+		axienet_dma_bd_release(ndev);</div><div class='add'>+	} else {</div><div class='add'>+		dmaengine_terminate_sync(lp-&gt;tx_chan);</div><div class='add'>+		dmaengine_synchronize(lp-&gt;tx_chan);</div><div class='add'>+		dmaengine_terminate_sync(lp-&gt;rx_chan);</div><div class='add'>+		dmaengine_synchronize(lp-&gt;rx_chan);</div><div class='add'>+</div><div class='add'>+		for (i = 0; i &lt; TX_BD_NUM_MAX; i++)</div><div class='add'>+			kfree(lp-&gt;tx_skb_ring[i]);</div><div class='add'>+		kfree(lp-&gt;tx_skb_ring);</div><div class='add'>+		for (i = 0; i &lt; RX_BUF_NUM_DEFAULT; i++)</div><div class='add'>+			kfree(lp-&gt;rx_skb_ring[i]);</div><div class='add'>+		kfree(lp-&gt;rx_skb_ring);</div><div class='add'>+</div><div class='add'>+		dma_release_channel(lp-&gt;rx_chan);</div><div class='add'>+		dma_release_channel(lp-&gt;tx_chan);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	axienet_iow(lp, XAE_IE_OFFSET, 0);</div><div class='ctx'> </div><div class='del'>-	cancel_work_sync(&amp;lp-&gt;dma_err_task);</div><div class='del'>-</div><div class='ctx'> 	if (lp-&gt;eth_irq &gt; 0)</div><div class='ctx'> 		free_irq(lp-&gt;eth_irq, ndev);</div><div class='del'>-	free_irq(lp-&gt;tx_irq, ndev);</div><div class='del'>-	free_irq(lp-&gt;rx_irq, ndev);</div><div class='del'>-</div><div class='del'>-	axienet_dma_bd_release(ndev);</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1333,6 +1712,18 @@ static const struct net_device_ops axienet_netdev_ops = {</div><div class='ctx'> #endif</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct net_device_ops axienet_netdev_dmaengine_ops = {</div><div class='add'>+	.ndo_open = axienet_open,</div><div class='add'>+	.ndo_stop = axienet_stop,</div><div class='add'>+	.ndo_start_xmit = axienet_start_xmit_dmaengine,</div><div class='add'>+	.ndo_get_stats64 = axienet_get_stats64,</div><div class='add'>+	.ndo_change_mtu	= axienet_change_mtu,</div><div class='add'>+	.ndo_set_mac_address = netdev_set_mac_address,</div><div class='add'>+	.ndo_validate_addr = eth_validate_addr,</div><div class='add'>+	.ndo_eth_ioctl = axienet_ioctl,</div><div class='add'>+	.ndo_set_rx_mode = axienet_set_multicast_list,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.</div><div class='ctx'>  * @ndev:	Pointer to net_device structure</div><div class='hunk'>@@ -1412,14 +1803,16 @@ static void axienet_ethtools_get_regs(struct net_device *ndev,</div><div class='ctx'> 	data[29] = axienet_ior(lp, XAE_FMI_OFFSET);</div><div class='ctx'> 	data[30] = axienet_ior(lp, XAE_AF0_OFFSET);</div><div class='ctx'> 	data[31] = axienet_ior(lp, XAE_AF1_OFFSET);</div><div class='del'>-	data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);</div><div class='del'>-	data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);</div><div class='del'>-	data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET);</div><div class='del'>-	data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET);</div><div class='del'>-	data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);</div><div class='del'>-	data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);</div><div class='del'>-	data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET);</div><div class='del'>-	data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET);</div><div class='add'>+	if (!lp-&gt;use_dmaengine) {</div><div class='add'>+		data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);</div><div class='add'>+		data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);</div><div class='add'>+		data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET);</div><div class='add'>+		data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET);</div><div class='add'>+		data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);</div><div class='add'>+		data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);</div><div class='add'>+		data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET);</div><div class='add'>+		data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void</div><div class='hunk'>@@ -1863,7 +2256,6 @@ static int axienet_probe(struct platform_device *pdev)</div><div class='ctx'> 	SET_NETDEV_DEV(ndev, &amp;pdev-&gt;dev);</div><div class='ctx'> 	ndev-&gt;flags &amp;= ~IFF_MULTICAST;  /* clear multicast */</div><div class='ctx'> 	ndev-&gt;features = NETIF_F_SG;</div><div class='del'>-	ndev-&gt;netdev_ops = &amp;axienet_netdev_ops;</div><div class='ctx'> 	ndev-&gt;ethtool_ops = &amp;axienet_ethtool_ops;</div><div class='ctx'> </div><div class='ctx'> 	/* MTU range: 64 - 9000 */</div><div class='hunk'>@@ -1880,9 +2272,6 @@ static int axienet_probe(struct platform_device *pdev)</div><div class='ctx'> 	u64_stats_init(&amp;lp-&gt;rx_stat_sync);</div><div class='ctx'> 	u64_stats_init(&amp;lp-&gt;tx_stat_sync);</div><div class='ctx'> </div><div class='del'>-	netif_napi_add(ndev, &amp;lp-&gt;napi_rx, axienet_rx_poll);</div><div class='del'>-	netif_napi_add(ndev, &amp;lp-&gt;napi_tx, axienet_tx_poll);</div><div class='del'>-</div><div class='ctx'> 	lp-&gt;axi_clk = devm_clk_get_optional(&amp;pdev-&gt;dev, "s_axi_lite_clk");</div><div class='ctx'> 	if (!lp-&gt;axi_clk) {</div><div class='ctx'> 		/* For backward compatibility, if named AXI clock is not present,</div><div class='hunk'>@@ -2008,82 +2397,118 @@ static int axienet_probe(struct platform_device *pdev)</div><div class='ctx'> 		goto cleanup_clk;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */</div><div class='del'>-	np = of_parse_phandle(pdev-&gt;dev.of_node, "axistream-connected", 0);</div><div class='del'>-	if (np) {</div><div class='del'>-		struct resource dmares;</div><div class='add'>+	if (!of_find_property(pdev-&gt;dev.of_node, "dmas", NULL)) {</div><div class='add'>+		/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */</div><div class='add'>+		np = of_parse_phandle(pdev-&gt;dev.of_node, "axistream-connected", 0);</div><div class='ctx'> </div><div class='del'>-		ret = of_address_to_resource(np, 0, &amp;dmares);</div><div class='del'>-		if (ret) {</div><div class='del'>-			dev_err(&amp;pdev-&gt;dev,</div><div class='del'>-				"unable to get DMA resource\n");</div><div class='add'>+		if (np) {</div><div class='add'>+			struct resource dmares;</div><div class='add'>+</div><div class='add'>+			ret = of_address_to_resource(np, 0, &amp;dmares);</div><div class='add'>+			if (ret) {</div><div class='add'>+				dev_err(&amp;pdev-&gt;dev,</div><div class='add'>+					"unable to get DMA resource\n");</div><div class='add'>+				of_node_put(np);</div><div class='add'>+				goto cleanup_clk;</div><div class='add'>+			}</div><div class='add'>+			lp-&gt;dma_regs = devm_ioremap_resource(&amp;pdev-&gt;dev,</div><div class='add'>+							     &amp;dmares);</div><div class='add'>+			lp-&gt;rx_irq = irq_of_parse_and_map(np, 1);</div><div class='add'>+			lp-&gt;tx_irq = irq_of_parse_and_map(np, 0);</div><div class='ctx'> 			of_node_put(np);</div><div class='add'>+			lp-&gt;eth_irq = platform_get_irq_optional(pdev, 0);</div><div class='add'>+		} else {</div><div class='add'>+			/* Check for these resources directly on the Ethernet node. */</div><div class='add'>+			lp-&gt;dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);</div><div class='add'>+			lp-&gt;rx_irq = platform_get_irq(pdev, 1);</div><div class='add'>+			lp-&gt;tx_irq = platform_get_irq(pdev, 0);</div><div class='add'>+			lp-&gt;eth_irq = platform_get_irq_optional(pdev, 2);</div><div class='add'>+		}</div><div class='add'>+		if (IS_ERR(lp-&gt;dma_regs)) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "could not map DMA regs\n");</div><div class='add'>+			ret = PTR_ERR(lp-&gt;dma_regs);</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+		}</div><div class='add'>+		if (lp-&gt;rx_irq &lt;= 0 || lp-&gt;tx_irq &lt;= 0) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "could not determine irqs\n");</div><div class='add'>+			ret = -ENOMEM;</div><div class='ctx'> 			goto cleanup_clk;</div><div class='ctx'> 		}</div><div class='del'>-		lp-&gt;dma_regs = devm_ioremap_resource(&amp;pdev-&gt;dev,</div><div class='del'>-						     &amp;dmares);</div><div class='del'>-		lp-&gt;rx_irq = irq_of_parse_and_map(np, 1);</div><div class='del'>-		lp-&gt;tx_irq = irq_of_parse_and_map(np, 0);</div><div class='del'>-		of_node_put(np);</div><div class='del'>-		lp-&gt;eth_irq = platform_get_irq_optional(pdev, 0);</div><div class='del'>-	} else {</div><div class='del'>-		/* Check for these resources directly on the Ethernet node. */</div><div class='del'>-		lp-&gt;dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);</div><div class='del'>-		lp-&gt;rx_irq = platform_get_irq(pdev, 1);</div><div class='del'>-		lp-&gt;tx_irq = platform_get_irq(pdev, 0);</div><div class='del'>-		lp-&gt;eth_irq = platform_get_irq_optional(pdev, 2);</div><div class='del'>-	}</div><div class='del'>-	if (IS_ERR(lp-&gt;dma_regs)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "could not map DMA regs\n");</div><div class='del'>-		ret = PTR_ERR(lp-&gt;dma_regs);</div><div class='del'>-		goto cleanup_clk;</div><div class='del'>-	}</div><div class='del'>-	if ((lp-&gt;rx_irq &lt;= 0) || (lp-&gt;tx_irq &lt;= 0)) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "could not determine irqs\n");</div><div class='del'>-		ret = -ENOMEM;</div><div class='del'>-		goto cleanup_clk;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	/* Reset core now that clocks are enabled, prior to accessing MDIO */</div><div class='del'>-	ret = __axienet_device_reset(lp);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto cleanup_clk;</div><div class='add'>+		/* Reset core now that clocks are enabled, prior to accessing MDIO */</div><div class='add'>+		ret = __axienet_device_reset(lp);</div><div class='add'>+		if (ret)</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+</div><div class='add'>+		/* Autodetect the need for 64-bit DMA pointers.</div><div class='add'>+		 * When the IP is configured for a bus width bigger than 32 bits,</div><div class='add'>+		 * writing the MSB registers is mandatory, even if they are all 0.</div><div class='add'>+		 * We can detect this case by writing all 1's to one such register</div><div class='add'>+		 * and see if that sticks: when the IP is configured for 32 bits</div><div class='add'>+		 * only, those registers are RES0.</div><div class='add'>+		 * Those MSB registers were introduced in IP v7.1, which we check first.</div><div class='add'>+		 */</div><div class='add'>+		if ((axienet_ior(lp, XAE_ID_OFFSET) &gt;&gt; 24) &gt;= 0x9) {</div><div class='add'>+			void __iomem *desc = lp-&gt;dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;</div><div class='ctx'> </div><div class='del'>-	/* Autodetect the need for 64-bit DMA pointers.</div><div class='del'>-	 * When the IP is configured for a bus width bigger than 32 bits,</div><div class='del'>-	 * writing the MSB registers is mandatory, even if they are all 0.</div><div class='del'>-	 * We can detect this case by writing all 1's to one such register</div><div class='del'>-	 * and see if that sticks: when the IP is configured for 32 bits</div><div class='del'>-	 * only, those registers are RES0.</div><div class='del'>-	 * Those MSB registers were introduced in IP v7.1, which we check first.</div><div class='del'>-	 */</div><div class='del'>-	if ((axienet_ior(lp, XAE_ID_OFFSET) &gt;&gt; 24) &gt;= 0x9) {</div><div class='del'>-		void __iomem *desc = lp-&gt;dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;</div><div class='del'>-</div><div class='del'>-		iowrite32(0x0, desc);</div><div class='del'>-		if (ioread32(desc) == 0) {	/* sanity check */</div><div class='del'>-			iowrite32(0xffffffff, desc);</div><div class='del'>-			if (ioread32(desc) &gt; 0) {</div><div class='del'>-				lp-&gt;features |= XAE_FEATURE_DMA_64BIT;</div><div class='del'>-				addr_width = 64;</div><div class='del'>-				dev_info(&amp;pdev-&gt;dev,</div><div class='del'>-					 "autodetected 64-bit DMA range\n");</div><div class='del'>-			}</div><div class='ctx'> 			iowrite32(0x0, desc);</div><div class='add'>+			if (ioread32(desc) == 0) {	/* sanity check */</div><div class='add'>+				iowrite32(0xffffffff, desc);</div><div class='add'>+				if (ioread32(desc) &gt; 0) {</div><div class='add'>+					lp-&gt;features |= XAE_FEATURE_DMA_64BIT;</div><div class='add'>+					addr_width = 64;</div><div class='add'>+					dev_info(&amp;pdev-&gt;dev,</div><div class='add'>+						 "autodetected 64-bit DMA range\n");</div><div class='add'>+				}</div><div class='add'>+				iowrite32(0x0, desc);</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (!IS_ENABLED(CONFIG_64BIT) &amp;&amp; lp-&gt;features &amp; XAE_FEATURE_DMA_64BIT) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n");</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto cleanup_clk;</div><div class='ctx'> 		}</div><div class='del'>-	}</div><div class='del'>-	if (!IS_ENABLED(CONFIG_64BIT) &amp;&amp; lp-&gt;features &amp; XAE_FEATURE_DMA_64BIT) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n");</div><div class='del'>-		ret = -EINVAL;</div><div class='del'>-		goto cleanup_clk;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='del'>-	ret = dma_set_mask_and_coherent(&amp;pdev-&gt;dev, DMA_BIT_MASK(addr_width));</div><div class='del'>-	if (ret) {</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "No suitable DMA available\n");</div><div class='del'>-		goto cleanup_clk;</div><div class='add'>+		ret = dma_set_mask_and_coherent(&amp;pdev-&gt;dev, DMA_BIT_MASK(addr_width));</div><div class='add'>+		if (ret) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "No suitable DMA available\n");</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+		}</div><div class='add'>+		netif_napi_add(ndev, &amp;lp-&gt;napi_rx, axienet_rx_poll);</div><div class='add'>+		netif_napi_add(ndev, &amp;lp-&gt;napi_tx, axienet_tx_poll);</div><div class='add'>+	} else {</div><div class='add'>+		struct xilinx_vdma_config cfg;</div><div class='add'>+		struct dma_chan *tx_chan;</div><div class='add'>+</div><div class='add'>+		lp-&gt;eth_irq = platform_get_irq_optional(pdev, 0);</div><div class='add'>+		if (lp-&gt;eth_irq &lt; 0 &amp;&amp; lp-&gt;eth_irq != -ENXIO) {</div><div class='add'>+			ret = lp-&gt;eth_irq;</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+		}</div><div class='add'>+		tx_chan = dma_request_chan(lp-&gt;dev, "tx_chan0");</div><div class='add'>+		if (IS_ERR(tx_chan)) {</div><div class='add'>+			ret = PTR_ERR(tx_chan);</div><div class='add'>+			dev_err_probe(lp-&gt;dev, ret, "No Ethernet DMA (TX) channel found\n");</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		cfg.reset = 1;</div><div class='add'>+		/* As name says VDMA but it has support for DMA channel reset */</div><div class='add'>+		ret = xilinx_vdma_channel_set_config(tx_chan, &amp;cfg);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(&amp;pdev-&gt;dev, "Reset channel failed\n");</div><div class='add'>+			dma_release_channel(tx_chan);</div><div class='add'>+			goto cleanup_clk;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		dma_release_channel(tx_chan);</div><div class='add'>+		lp-&gt;use_dmaengine = 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (lp-&gt;use_dmaengine)</div><div class='add'>+		ndev-&gt;netdev_ops = &amp;axienet_netdev_dmaengine_ops;</div><div class='add'>+	else</div><div class='add'>+		ndev-&gt;netdev_ops = &amp;axienet_netdev_ops;</div><div class='ctx'> 	/* Check for Ethernet core IRQ (optional) */</div><div class='ctx'> 	if (lp-&gt;eth_irq &lt;= 0)</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "Ethernet core IRQ not defined\n");</div><div class='hunk'>@@ -2099,8 +2524,8 @@ static int axienet_probe(struct platform_device *pdev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	lp-&gt;coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;</div><div class='del'>-	lp-&gt;coalesce_usec_rx = XAXIDMA_DFT_RX_USEC;</div><div class='ctx'> 	lp-&gt;coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;</div><div class='add'>+	lp-&gt;coalesce_usec_rx = XAXIDMA_DFT_RX_USEC;</div><div class='ctx'> 	lp-&gt;coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;</div><div class='ctx'> </div><div class='ctx'> 	ret = axienet_mdio_setup(lp);</div><div class='head'>diff --git a/drivers/net/fjes/fjes_main.c b/drivers/net/fjes/fjes_main.c<br/>index cd8cf08477ec..5fbe33a09bb0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/fjes/fjes_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/fjes/fjes_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/fjes/fjes_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/fjes/fjes_main.c</a></div><div class='hunk'>@@ -1438,7 +1438,7 @@ err_out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* fjes_remove - Device Removal Routine */</div><div class='del'>-static int fjes_remove(struct platform_device *plat_dev)</div><div class='add'>+static void fjes_remove(struct platform_device *plat_dev)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *netdev = dev_get_drvdata(&amp;plat_dev-&gt;dev);</div><div class='ctx'> 	struct fjes_adapter *adapter = netdev_priv(netdev);</div><div class='hunk'>@@ -1462,8 +1462,6 @@ static int fjes_remove(struct platform_device *plat_dev)</div><div class='ctx'> 	netif_napi_del(&amp;adapter-&gt;napi);</div><div class='ctx'> </div><div class='ctx'> 	free_netdev(netdev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver fjes_driver = {</div><div class='hunk'>@@ -1471,7 +1469,7 @@ static struct platform_driver fjes_driver = {</div><div class='ctx'> 		.name = DRV_NAME,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = fjes_probe,</div><div class='del'>-	.remove = fjes_remove,</div><div class='add'>+	.remove_new = fjes_remove,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static acpi_status</div><div class='head'>diff --git a/drivers/net/geneve.c b/drivers/net/geneve.c<br/>index acd9c615d1f4..32c51c244153 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/geneve.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/geneve.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/geneve.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/geneve.c</a></div><div class='hunk'>@@ -234,7 +234,7 @@ static void geneve_rx(struct geneve_dev *geneve, struct geneve_sock *gs,</div><div class='ctx'> 					 vni_to_tunnel_id(gnvh-&gt;vni),</div><div class='ctx'> 					 gnvh-&gt;opt_len * 4);</div><div class='ctx'> 		if (!tun_dst) {</div><div class='del'>-			geneve-&gt;dev-&gt;stats.rx_dropped++;</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_dropped);</div><div class='ctx'> 			goto drop;</div><div class='ctx'> 		}</div><div class='ctx'> 		/* Update tunnel dst according to Geneve options. */</div><div class='hunk'>@@ -246,8 +246,8 @@ static void geneve_rx(struct geneve_dev *geneve, struct geneve_sock *gs,</div><div class='ctx'> 		 * since we don't support any...</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (gnvh-&gt;critical) {</div><div class='del'>-			geneve-&gt;dev-&gt;stats.rx_frame_errors++;</div><div class='del'>-			geneve-&gt;dev-&gt;stats.rx_errors++;</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_frame_errors);</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_errors);</div><div class='ctx'> 			goto drop;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -263,7 +263,7 @@ static void geneve_rx(struct geneve_dev *geneve, struct geneve_sock *gs,</div><div class='ctx'> 		/* Ignore packet loops (and multicast echo) */</div><div class='ctx'> 		if (ether_addr_equal(eth_hdr(skb)-&gt;h_source,</div><div class='ctx'> 				     geneve-&gt;dev-&gt;dev_addr)) {</div><div class='del'>-			geneve-&gt;dev-&gt;stats.rx_errors++;</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_errors);</div><div class='ctx'> 			goto drop;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -296,8 +296,8 @@ static void geneve_rx(struct geneve_dev *geneve, struct geneve_sock *gs,</div><div class='ctx'> #endif</div><div class='ctx'> 		}</div><div class='ctx'> 		if (err &gt; 1) {</div><div class='del'>-			++geneve-&gt;dev-&gt;stats.rx_frame_errors;</div><div class='del'>-			++geneve-&gt;dev-&gt;stats.rx_errors;</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_frame_errors);</div><div class='add'>+			DEV_STATS_INC(geneve-&gt;dev, rx_errors);</div><div class='ctx'> 			goto drop;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='hunk'>@@ -377,14 +377,14 @@ static int geneve_udp_encap_recv(struct sock *sk, struct sk_buff *skb)</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely((!geneve-&gt;cfg.inner_proto_inherit &amp;&amp;</div><div class='ctx'> 		      inner_proto != htons(ETH_P_TEB)))) {</div><div class='del'>-		geneve-&gt;dev-&gt;stats.rx_dropped++;</div><div class='add'>+		DEV_STATS_INC(geneve-&gt;dev, rx_dropped);</div><div class='ctx'> 		goto drop;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	opts_len = geneveh-&gt;opt_len * 4;</div><div class='ctx'> 	if (iptunnel_pull_header(skb, GENEVE_BASE_HLEN + opts_len, inner_proto,</div><div class='ctx'> 				 !net_eq(geneve-&gt;net, dev_net(geneve-&gt;dev)))) {</div><div class='del'>-		geneve-&gt;dev-&gt;stats.rx_dropped++;</div><div class='add'>+		DEV_STATS_INC(geneve-&gt;dev, rx_dropped);</div><div class='ctx'> 		goto drop;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1007,7 +1007,7 @@ static netdev_tx_t geneve_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 		if (unlikely(!info || !(info-&gt;mode &amp; IP_TUNNEL_INFO_TX))) {</div><div class='ctx'> 			netdev_dbg(dev, "no tunnel metadata\n");</div><div class='ctx'> 			dev_kfree_skb(skb);</div><div class='del'>-			dev-&gt;stats.tx_dropped++;</div><div class='add'>+			DEV_STATS_INC(dev, tx_dropped);</div><div class='ctx'> 			return NETDEV_TX_OK;</div><div class='ctx'> 		}</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1030,11 +1030,11 @@ static netdev_tx_t geneve_xmit(struct sk_buff *skb, struct net_device *dev)</div><div class='ctx'> 		dev_kfree_skb(skb);</div><div class='ctx'> </div><div class='ctx'> 	if (err == -ELOOP)</div><div class='del'>-		dev-&gt;stats.collisions++;</div><div class='add'>+		DEV_STATS_INC(dev, collisions);</div><div class='ctx'> 	else if (err == -ENETUNREACH)</div><div class='del'>-		dev-&gt;stats.tx_carrier_errors++;</div><div class='add'>+		DEV_STATS_INC(dev, tx_carrier_errors);</div><div class='ctx'> </div><div class='del'>-	dev-&gt;stats.tx_errors++;</div><div class='add'>+	DEV_STATS_INC(dev, tx_errors);</div><div class='ctx'> 	return NETDEV_TX_OK;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/hyperv/Kconfig b/drivers/net/hyperv/Kconfig<br/>index ca7bf7f897d3..c8cbd85adcf9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/hyperv/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/hyperv/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/hyperv/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/Kconfig</a></div><div class='hunk'>@@ -3,5 +3,6 @@ config HYPERV_NET</div><div class='ctx'> 	tristate "Microsoft Hyper-V virtual network driver"</div><div class='ctx'> 	depends on HYPERV</div><div class='ctx'> 	select UCS2_STRING</div><div class='add'>+	select NLS</div><div class='ctx'> 	help</div><div class='ctx'> 	  Select this option to enable the Hyper-V virtual network driver.</div><div class='head'>diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c<br/>index 706ea5263e87..4406427d4617 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/hyperv/netvsc_drv.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/hyperv/netvsc_drv.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/hyperv/netvsc_drv.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/netvsc_drv.c</a></div><div class='hunk'>@@ -1582,10 +1582,10 @@ static void netvsc_get_strings(struct net_device *dev, u32 stringset, u8 *data)</div><div class='ctx'> 	switch (stringset) {</div><div class='ctx'> 	case ETH_SS_STATS:</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(netvsc_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, netvsc_stats[i].name);</div><div class='add'>+			ethtool_puts(&amp;p, netvsc_stats[i].name);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(vf_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;p, vf_stats[i].name);</div><div class='add'>+			ethtool_puts(&amp;p, vf_stats[i].name);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; nvdev-&gt;num_chn; i++) {</div><div class='ctx'> 			ethtool_sprintf(&amp;p, "tx_queue_%u_packets", i);</div><div class='hunk'>@@ -1752,8 +1752,8 @@ static u32 netvsc_rss_indir_size(struct net_device *dev)</div><div class='ctx'> 	return ndc-&gt;rx_table_sz;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int netvsc_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='del'>-			   u8 *hfunc)</div><div class='add'>+static int netvsc_get_rxfh(struct net_device *dev,</div><div class='add'>+			   struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device_context *ndc = netdev_priv(dev);</div><div class='ctx'> 	struct netvsc_device *ndev = rtnl_dereference(ndc-&gt;nvdev);</div><div class='hunk'>@@ -1763,47 +1763,49 @@ static int netvsc_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,</div><div class='ctx'> 	if (!ndev)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;	/* Toeplitz */</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;	/* Toeplitz */</div><div class='ctx'> </div><div class='ctx'> 	rndis_dev = ndev-&gt;extension;</div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ndc-&gt;rx_table_sz; i++)</div><div class='del'>-			indir[i] = ndc-&gt;rx_table[i];</div><div class='add'>+			rxfh-&gt;indir[i] = ndc-&gt;rx_table[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, rndis_dev-&gt;rss_key, NETVSC_HASH_KEYLEN);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, rndis_dev-&gt;rss_key, NETVSC_HASH_KEYLEN);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int netvsc_set_rxfh(struct net_device *dev, const u32 *indir,</div><div class='del'>-			   const u8 *key, const u8 hfunc)</div><div class='add'>+static int netvsc_set_rxfh(struct net_device *dev,</div><div class='add'>+			   struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			   struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device_context *ndc = netdev_priv(dev);</div><div class='ctx'> 	struct netvsc_device *ndev = rtnl_dereference(ndc-&gt;nvdev);</div><div class='ctx'> 	struct rndis_device *rndis_dev;</div><div class='add'>+	u8 *key = rxfh-&gt;key;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	if (!ndev)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='ctx'> 	rndis_dev = ndev-&gt;extension;</div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; ndc-&gt;rx_table_sz; i++)</div><div class='del'>-			if (indir[i] &gt;= ndev-&gt;num_chn)</div><div class='add'>+			if (rxfh-&gt;indir[i] &gt;= ndev-&gt;num_chn)</div><div class='ctx'> 				return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; ndc-&gt;rx_table_sz; i++)</div><div class='del'>-			ndc-&gt;rx_table[i] = indir[i];</div><div class='add'>+			ndc-&gt;rx_table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (!key) {</div><div class='del'>-		if (!indir)</div><div class='add'>+		if (!rxfh-&gt;indir)</div><div class='ctx'> 			return 0;</div><div class='ctx'> </div><div class='ctx'> 		key = rndis_dev-&gt;rss_key;</div><div class='head'>diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c<br/>index af95947a87c5..ecc2128ca9b7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/hyperv/rndis_filter.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/hyperv/rndis_filter.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/hyperv/rndis_filter.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/hyperv/rndis_filter.c</a></div><div class='hunk'>@@ -21,7 +21,6 @@</div><div class='ctx'> #include &lt;linux/rtnetlink.h&gt;</div><div class='ctx'> #include &lt;linux/ucs2_string.h&gt;</div><div class='ctx'> #include &lt;linux/string.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='ctx'> </div><div class='ctx'> #include "hyperv_net.h"</div><div class='ctx'> #include "netvsc_trace.h"</div><div class='head'>diff --git a/drivers/net/ieee802154/fakelb.c b/drivers/net/ieee802154/fakelb.c<br/>index 523d13ee02bf..35e55f198e05 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ieee802154/fakelb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ieee802154/fakelb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ieee802154/fakelb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ieee802154/fakelb.c</a></div><div class='hunk'>@@ -221,7 +221,7 @@ err_slave:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int fakelb_remove(struct platform_device *pdev)</div><div class='add'>+static void fakelb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct fakelb_phy *phy, *tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -229,14 +229,13 @@ static int fakelb_remove(struct platform_device *pdev)</div><div class='ctx'> 	list_for_each_entry_safe(phy, tmp, &amp;fakelb_phys, list)</div><div class='ctx'> 		fakelb_del(phy);</div><div class='ctx'> 	mutex_unlock(&amp;fakelb_phys_lock);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_device *ieee802154fake_dev;</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ieee802154fake_driver = {</div><div class='ctx'> 	.probe = fakelb_probe,</div><div class='del'>-	.remove = fakelb_remove,</div><div class='add'>+	.remove_new = fakelb_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 			.name = "ieee802154fakelb",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/net/ieee802154/mac802154_hwsim.c b/drivers/net/ieee802154/mac802154_hwsim.c<br/>index 31cba9aa7636..2c2483bbe780 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ieee802154/mac802154_hwsim.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ieee802154/mac802154_hwsim.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ieee802154/mac802154_hwsim.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ieee802154/mac802154_hwsim.c</a></div><div class='hunk'>@@ -1035,7 +1035,7 @@ err_slave:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int hwsim_remove(struct platform_device *pdev)</div><div class='add'>+static void hwsim_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct hwsim_phy *phy, *tmp;</div><div class='ctx'> </div><div class='hunk'>@@ -1043,13 +1043,11 @@ static int hwsim_remove(struct platform_device *pdev)</div><div class='ctx'> 	list_for_each_entry_safe(phy, tmp, &amp;hwsim_phys, list)</div><div class='ctx'> 		hwsim_del(phy);</div><div class='ctx'> 	mutex_unlock(&amp;hwsim_phys_lock);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver mac802154hwsim_driver = {</div><div class='ctx'> 	.probe = hwsim_probe,</div><div class='del'>-	.remove = hwsim_remove,</div><div class='add'>+	.remove_new = hwsim_remove,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 			.name = "mac802154_hwsim",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile<br/>index 7293d5cc2b2b..d3abb38633e0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/Makefile</a></div><div class='hunk'>@@ -2,12 +2,12 @@</div><div class='ctx'> #</div><div class='ctx'> # Makefile for the Qualcomm IPA driver.</div><div class='ctx'> </div><div class='del'>-IPA_REG_VERSIONS	:=	3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0</div><div class='add'>+IPA_REG_VERSIONS	:=	3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5</div><div class='ctx'> </div><div class='ctx'> # Some IPA versions can reuse another set of GSI register definitions.</div><div class='ctx'> GSI_REG_VERSIONS	:=	3.1 3.5.1 4.0 4.5 4.9 4.11 5.0</div><div class='ctx'> </div><div class='del'>-IPA_DATA_VERSIONS	:=	3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0</div><div class='add'>+IPA_DATA_VERSIONS	:=	3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0 5.5</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_QCOM_IPA)	+=	ipa.o</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ipa/data/ipa_data-v5.5.c b/drivers/net/ipa/data/ipa_data-v5.5.c<br/>new file mode 100644<br/>index 000000000000..2c6390f11354<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/data/ipa_data-v5.5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/data/ipa_data-v5.5.c</a></div><div class='hunk'>@@ -0,0 +1,487 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+/* Copyright (C) 2023 Linaro Ltd. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/log2.h&gt;</div><div class='add'>+</div><div class='add'>+#include "../ipa_data.h"</div><div class='add'>+#include "../ipa_endpoint.h"</div><div class='add'>+#include "../ipa_mem.h"</div><div class='add'>+</div><div class='add'>+/** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.5 */</div><div class='add'>+enum ipa_resource_type {</div><div class='add'>+	/* Source resource types; first must have value 0 */</div><div class='add'>+	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,</div><div class='add'>+	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,</div><div class='add'>+	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,</div><div class='add'>+	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,</div><div class='add'>+	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,</div><div class='add'>+</div><div class='add'>+	/* Destination resource types; first must have value 0 */</div><div class='add'>+	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,</div><div class='add'>+	IPA_RESOURCE_TYPE_DST_DPS_DMARS,</div><div class='add'>+	IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Resource groups used for an SoC having IPA v5.5 */</div><div class='add'>+enum ipa_rsrc_group_id {</div><div class='add'>+	/* Source resource group identifiers */</div><div class='add'>+	IPA_RSRC_GROUP_SRC_UL				= 0,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_DL,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_UNUSED_2,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_UNUSED_3,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_URLLC,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_U_RX_QC,</div><div class='add'>+	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */</div><div class='add'>+</div><div class='add'>+	/* Destination resource group identifiers */</div><div class='add'>+	IPA_RSRC_GROUP_DST_UL				= 0,</div><div class='add'>+	IPA_RSRC_GROUP_DST_DL,</div><div class='add'>+	IPA_RSRC_GROUP_DST_UNUSED_2,</div><div class='add'>+	IPA_RSRC_GROUP_DST_UNUSED_3,</div><div class='add'>+	IPA_RSRC_GROUP_DST_UNUSED_4,</div><div class='add'>+	IPA_RSRC_GROUP_DST_UC,</div><div class='add'>+	IPA_RSRC_GROUP_DST_DRB_IP,</div><div class='add'>+	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* QSB configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_qsb_data ipa_qsb_data[] = {</div><div class='add'>+	[IPA_QSB_MASTER_DDR] = {</div><div class='add'>+		.max_writes		= 0,	/* Unlimited */</div><div class='add'>+		.max_reads		= 12,</div><div class='add'>+		.max_reads_beats	= 0,</div><div class='add'>+	},</div><div class='add'>+	[IPA_QSB_MASTER_PCIE] = {</div><div class='add'>+		.max_writes		= 0,	/* Unlimited */</div><div class='add'>+		.max_reads		= 8,</div><div class='add'>+		.max_reads_beats	= 0,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Endpoint configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {</div><div class='add'>+	[IPA_ENDPOINT_AP_COMMAND_TX] = {</div><div class='add'>+		.ee_id		= GSI_EE_AP,</div><div class='add'>+		.channel_id	= 12,</div><div class='add'>+		.endpoint_id	= 14,</div><div class='add'>+		.toward_ipa	= true,</div><div class='add'>+		.channel = {</div><div class='add'>+			.tre_count	= 256,</div><div class='add'>+			.event_count	= 256,</div><div class='add'>+			.tlv_count	= 20,</div><div class='add'>+		},</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.config = {</div><div class='add'>+				.resource_group	= IPA_RSRC_GROUP_SRC_UL,</div><div class='add'>+				.dma_mode	= true,</div><div class='add'>+				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,</div><div class='add'>+				.tx = {</div><div class='add'>+					.seq_type = IPA_SEQ_DMA,</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_AP_LAN_RX] = {</div><div class='add'>+		.ee_id		= GSI_EE_AP,</div><div class='add'>+		.channel_id	= 13,</div><div class='add'>+		.endpoint_id	= 16,</div><div class='add'>+		.toward_ipa	= false,</div><div class='add'>+		.channel = {</div><div class='add'>+			.tre_count	= 256,</div><div class='add'>+			.event_count	= 256,</div><div class='add'>+			.tlv_count	= 9,</div><div class='add'>+		},</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.config = {</div><div class='add'>+				.resource_group	= IPA_RSRC_GROUP_DST_UL,</div><div class='add'>+				.aggregation	= true,</div><div class='add'>+				.status_enable	= true,</div><div class='add'>+				.rx = {</div><div class='add'>+					.buffer_size	= 8192,</div><div class='add'>+					.pad_align	= ilog2(sizeof(u32)),</div><div class='add'>+					.aggr_time_limit = 500,</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_AP_MODEM_TX] = {</div><div class='add'>+		.ee_id		= GSI_EE_AP,</div><div class='add'>+		.channel_id	= 11,</div><div class='add'>+		.endpoint_id	= 2,</div><div class='add'>+		.toward_ipa	= true,</div><div class='add'>+		.channel = {</div><div class='add'>+			.tre_count	= 512,</div><div class='add'>+			.event_count	= 512,</div><div class='add'>+			.tlv_count	= 25,</div><div class='add'>+		},</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.filter_support	= true,</div><div class='add'>+			.config = {</div><div class='add'>+				.resource_group	= IPA_RSRC_GROUP_SRC_UL,</div><div class='add'>+				.checksum       = true,</div><div class='add'>+				.qmap		= true,</div><div class='add'>+				.status_enable	= true,</div><div class='add'>+				.tx = {</div><div class='add'>+					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,</div><div class='add'>+					.status_endpoint =</div><div class='add'>+						IPA_ENDPOINT_MODEM_AP_RX,</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_AP_MODEM_RX] = {</div><div class='add'>+		.ee_id		= GSI_EE_AP,</div><div class='add'>+		.channel_id	= 1,</div><div class='add'>+		.endpoint_id	= 23,</div><div class='add'>+		.toward_ipa	= false,</div><div class='add'>+		.channel = {</div><div class='add'>+			.tre_count	= 256,</div><div class='add'>+			.event_count	= 256,</div><div class='add'>+			.tlv_count	= 9,</div><div class='add'>+		},</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.config = {</div><div class='add'>+				.resource_group	= IPA_RSRC_GROUP_DST_DL,</div><div class='add'>+				.checksum       = true,</div><div class='add'>+				.qmap		= true,</div><div class='add'>+				.aggregation	= true,</div><div class='add'>+				.rx = {</div><div class='add'>+					.buffer_size	= 8192,</div><div class='add'>+					.aggr_time_limit = 500,</div><div class='add'>+					.aggr_close_eof	= true,</div><div class='add'>+				},</div><div class='add'>+			},</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_MODEM_AP_TX] = {</div><div class='add'>+		.ee_id		= GSI_EE_MODEM,</div><div class='add'>+		.channel_id	= 0,</div><div class='add'>+		.endpoint_id	= 12,</div><div class='add'>+		.toward_ipa	= true,</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.filter_support	= true,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_MODEM_AP_RX] = {</div><div class='add'>+		.ee_id		= GSI_EE_MODEM,</div><div class='add'>+		.channel_id	= 7,</div><div class='add'>+		.endpoint_id	= 21,</div><div class='add'>+		.toward_ipa	= false,</div><div class='add'>+	},</div><div class='add'>+	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {</div><div class='add'>+		.ee_id		= GSI_EE_MODEM,</div><div class='add'>+		.channel_id	= 2,</div><div class='add'>+		.endpoint_id	= 15,</div><div class='add'>+		.toward_ipa	= true,</div><div class='add'>+		.endpoint = {</div><div class='add'>+			.filter_support	= true,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Source resource configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_resource ipa_resource_src[] = {</div><div class='add'>+	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_UL] = {</div><div class='add'>+			.min = 3,	.max = 9,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_DL] = {</div><div class='add'>+			.min = 4,	.max = 10,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {</div><div class='add'>+			.min = 1,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_UL] = {</div><div class='add'>+			.min = 9,	.max = 9,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_DL] = {</div><div class='add'>+			.min = 12,	.max = 12,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {</div><div class='add'>+			.min = 10,	.max = 10,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_UL] = {</div><div class='add'>+			.min = 9,	.max = 9,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_DL] = {</div><div class='add'>+			.min = 24,	.max = 24,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {</div><div class='add'>+			.min = 20,	.max = 20,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_UL] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_DL] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {</div><div class='add'>+			.min = 1,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_UL] = {</div><div class='add'>+			.min = 22,	.max = 22,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_DL] = {</div><div class='add'>+			.min = 16,	.max = 16,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {</div><div class='add'>+			.min = 16,	.max = 16,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Destination resource configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_resource ipa_resource_dst[] = {</div><div class='add'>+	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_UL] = {</div><div class='add'>+			.min = 6,	.max = 6,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_DL] = {</div><div class='add'>+			.min = 5,	.max = 5,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {</div><div class='add'>+			.min = 39,	.max = 39,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_UL] = {</div><div class='add'>+			.min = 0,	.max = 3,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_DL] = {</div><div class='add'>+			.min = 0,	.max = 3,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+	[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_UL] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+		.limits[IPA_RSRC_GROUP_DST_DL] = {</div><div class='add'>+			.min = 0,	.max = 63,</div><div class='add'>+		},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Resource configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_resource_data ipa_resource_data = {</div><div class='add'>+	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,</div><div class='add'>+	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,</div><div class='add'>+	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),</div><div class='add'>+	.resource_src		= ipa_resource_src,</div><div class='add'>+	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),</div><div class='add'>+	.resource_dst		= ipa_resource_dst,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* IPA-resident memory region data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_mem ipa_mem_local_data[] = {</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_UC_EVENT_RING,</div><div class='add'>+		.offset		= 0x0000,</div><div class='add'>+		.size		= 0x1000,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_UC_SHARED,</div><div class='add'>+		.offset		= 0x1000,</div><div class='add'>+		.size		= 0x0080,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_UC_INFO,</div><div class='add'>+		.offset		= 0x1080,</div><div class='add'>+		.size		= 0x0200,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V4_FILTER_HASHED,</div><div class='add'>+		.offset		= 0x1288,</div><div class='add'>+		.size		= 0x0078,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V4_FILTER,</div><div class='add'>+		.offset		= 0x1308,</div><div class='add'>+		.size		= 0x0078,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V6_FILTER_HASHED,</div><div class='add'>+		.offset		= 0x1388,</div><div class='add'>+		.size		= 0x0078,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V6_FILTER,</div><div class='add'>+		.offset		= 0x1408,</div><div class='add'>+		.size		= 0x0078,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V4_ROUTE_HASHED,</div><div class='add'>+		.offset		= 0x1488,</div><div class='add'>+		.size		= 0x0098,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V4_ROUTE,</div><div class='add'>+		.offset		= 0x1528,</div><div class='add'>+		.size		= 0x0098,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V6_ROUTE_HASHED,</div><div class='add'>+		.offset		= 0x15c8,</div><div class='add'>+		.size		= 0x0098,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_V6_ROUTE,</div><div class='add'>+		.offset		= 0x1668,</div><div class='add'>+		.size		= 0x0098,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_MODEM_HEADER,</div><div class='add'>+		.offset		= 0x1708,</div><div class='add'>+		.size		= 0x0240,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_AP_HEADER,</div><div class='add'>+		.offset		= 0x1948,</div><div class='add'>+		.size		= 0x01e0,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_MODEM_PROC_CTX,</div><div class='add'>+		.offset		= 0x1b40,</div><div class='add'>+		.size		= 0x0b20,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_AP_PROC_CTX,</div><div class='add'>+		.offset		= 0x2660,</div><div class='add'>+		.size		= 0x0200,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_STATS_QUOTA_MODEM,</div><div class='add'>+		.offset		= 0x2868,</div><div class='add'>+		.size		= 0x0060,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_STATS_QUOTA_AP,</div><div class='add'>+		.offset		= 0x28c8,</div><div class='add'>+		.size		= 0x0048,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_STATS_TETHERING,</div><div class='add'>+		.offset		= 0x2910,</div><div class='add'>+		.size		= 0x03c0,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_AP_V4_FILTER,</div><div class='add'>+		.offset		= 0x29b8,</div><div class='add'>+		.size		= 0x0188,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_AP_V6_FILTER,</div><div class='add'>+		.offset		= 0x2b40,</div><div class='add'>+		.size		= 0x0228,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_STATS_FILTER_ROUTE,</div><div class='add'>+		.offset		= 0x2cd0,</div><div class='add'>+		.size		= 0x0ba0,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_STATS_DROP,</div><div class='add'>+		.offset		= 0x3870,</div><div class='add'>+		.size		= 0x0020,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_MODEM,</div><div class='add'>+		.offset		= 0x3898,</div><div class='add'>+		.size		= 0x0d48,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_NAT_TABLE,</div><div class='add'>+		.offset		= 0x45e0,</div><div class='add'>+		.size		= 0x0900,</div><div class='add'>+		.canary_count	= 0,</div><div class='add'>+	},</div><div class='add'>+	{</div><div class='add'>+		.id		= IPA_MEM_PDN_CONFIG,</div><div class='add'>+		.offset		= 0x4ee8,</div><div class='add'>+		.size		= 0x0100,</div><div class='add'>+		.canary_count	= 2,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Memory configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_mem_data ipa_mem_data = {</div><div class='add'>+	.local_count	= ARRAY_SIZE(ipa_mem_local_data),</div><div class='add'>+	.local		= ipa_mem_local_data,</div><div class='add'>+	.imem_addr	= 0x14688000,</div><div class='add'>+	.imem_size	= 0x00002000,</div><div class='add'>+	.smem_id	= 497,</div><div class='add'>+	.smem_size	= 0x0000b000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Interconnect rates are in 1000 byte/second units */</div><div class='add'>+static const struct ipa_interconnect_data ipa_interconnect_data[] = {</div><div class='add'>+	{</div><div class='add'>+		.name			= "memory",</div><div class='add'>+		.peak_bandwidth		= 1900000,	/* 1.9 GBps */</div><div class='add'>+		.average_bandwidth	= 600000,	/* 600 MBps */</div><div class='add'>+	},</div><div class='add'>+	/* Average rate is unused for the next interconnect */</div><div class='add'>+	{</div><div class='add'>+		.name			= "config",</div><div class='add'>+		.peak_bandwidth		= 76800,	/* 76.8 MBps */</div><div class='add'>+		.average_bandwidth	= 0,		/* unused */</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Clock and interconnect configuration data for an SoC having IPA v5.5 */</div><div class='add'>+static const struct ipa_power_data ipa_power_data = {</div><div class='add'>+	.core_clock_rate	= 120 * 1000 * 1000,	/* Hz */</div><div class='add'>+	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),</div><div class='add'>+	.interconnect_data	= ipa_interconnect_data,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Configuration data for an SoC having IPA v5.5. */</div><div class='add'>+const struct ipa_data ipa_data_v5_5 = {</div><div class='add'>+	.version		= IPA_VERSION_5_5,</div><div class='add'>+	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),</div><div class='add'>+	.qsb_data		= ipa_qsb_data,</div><div class='add'>+	.modem_route_count	= 11,</div><div class='add'>+	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),</div><div class='add'>+	.endpoint_data		= ipa_gsi_endpoint_data,</div><div class='add'>+	.resource_data		= &amp;ipa_resource_data,</div><div class='add'>+	.mem_data		= &amp;ipa_mem_data,</div><div class='add'>+	.power_data		= &amp;ipa_power_data,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c<br/>index c5458e28b12f..106c43884aef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/gsi_reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/gsi_reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/gsi_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/gsi_reg.c</a></div><div class='hunk'>@@ -110,6 +110,7 @@ static const struct regs *gsi_regs(struct gsi *gsi)</div><div class='ctx'> 		return &amp;gsi_regs_v4_11;</div><div class='ctx'> </div><div class='ctx'> 	case IPA_VERSION_5_0:</div><div class='add'>+	case IPA_VERSION_5_5:</div><div class='ctx'> 		return &amp;gsi_regs_v5_0;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='head'>diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h<br/>index ce82b00fdc49..2a1605e67b65 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_data.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_data.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_data.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_data.h</a></div><div class='hunk'>@@ -250,5 +250,6 @@ extern const struct ipa_data ipa_data_v4_7;</div><div class='ctx'> extern const struct ipa_data ipa_data_v4_9;</div><div class='ctx'> extern const struct ipa_data ipa_data_v4_11;</div><div class='ctx'> extern const struct ipa_data ipa_data_v5_0;</div><div class='add'>+extern const struct ipa_data ipa_data_v5_5;</div><div class='ctx'> </div><div class='ctx'> #endif /* _IPA_DATA_H_ */</div><div class='head'>diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c<br/>index da853353a5c7..00475fd7a205 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_main.c</a></div><div class='hunk'>@@ -74,6 +74,7 @@</div><div class='ctx'> #define IPA_PAS_ID		15</div><div class='ctx'> </div><div class='ctx'> /* Shift of 19.2 MHz timestamp to achieve lower resolution timestamps */</div><div class='add'>+/* IPA v5.5+ does not specify Qtime timestamp config for DPL */</div><div class='ctx'> #define DPL_TIMESTAMP_SHIFT	14	/* ~1.172 kHz, ~853 usec per tick */</div><div class='ctx'> #define TAG_TIMESTAMP_SHIFT	14</div><div class='ctx'> #define NAT_TIMESTAMP_SHIFT	24	/* ~1.144 Hz, ~874 msec per tick */</div><div class='hunk'>@@ -376,9 +377,11 @@ static void ipa_qtime_config(struct ipa *ipa)</div><div class='ctx'> 	iowrite32(0, ipa-&gt;reg_virt + reg_offset(reg));</div><div class='ctx'> </div><div class='ctx'> 	reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG);</div><div class='del'>-	/* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */</div><div class='del'>-	val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);</div><div class='del'>-	val |= reg_bit(reg, DPL_TIMESTAMP_SEL);</div><div class='add'>+	if (ipa-&gt;version &lt; IPA_VERSION_5_5) {</div><div class='add'>+		/* Set DPL time stamp resolution to use Qtime (not 1 msec) */</div><div class='add'>+		val = reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);</div><div class='add'>+		val |= reg_bit(reg, DPL_TIMESTAMP_SEL);</div><div class='add'>+	}</div><div class='ctx'> 	/* Configure tag and NAT Qtime timestamp resolution as well */</div><div class='ctx'> 	val = reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);</div><div class='ctx'> 	val = reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);</div><div class='hunk'>@@ -688,6 +691,10 @@ static const struct of_device_id ipa_match[] = {</div><div class='ctx'> 		.compatible	= "qcom,sdx65-ipa",</div><div class='ctx'> 		.data		= &amp;ipa_data_v5_0,</div><div class='ctx'> 	},</div><div class='add'>+	{</div><div class='add'>+		.compatible	= "qcom,sm8550-ipa",</div><div class='add'>+		.data		= &amp;ipa_data_v5_5,</div><div class='add'>+	},</div><div class='ctx'> 	{ },</div><div class='ctx'> };</div><div class='ctx'> MODULE_DEVICE_TABLE(of, ipa_match);</div><div class='hunk'>@@ -936,7 +943,7 @@ err_power_exit:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ipa_remove(struct platform_device *pdev)</div><div class='add'>+static void ipa_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ipa *ipa = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct ipa_power *power = ipa-&gt;power;</div><div class='hunk'>@@ -959,8 +966,16 @@ static int ipa_remove(struct platform_device *pdev)</div><div class='ctx'> 			usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);</div><div class='ctx'> 			ret = ipa_modem_stop(ipa);</div><div class='ctx'> 		}</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='add'>+		if (ret) {</div><div class='add'>+			/*</div><div class='add'>+			 * Not cleaning up here properly might also yield a</div><div class='add'>+			 * crash later on. As the device is still unregistered</div><div class='add'>+			 * in this case, this might even yield a crash later on.</div><div class='add'>+			 */</div><div class='add'>+			dev_err(dev, "Failed to stop modem (%pe), leaking resources\n",</div><div class='add'>+				ERR_PTR(ret));</div><div class='add'>+			return;</div><div class='add'>+		}</div><div class='ctx'> </div><div class='ctx'> 		ipa_teardown(ipa);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -978,17 +993,6 @@ out_power_put:</div><div class='ctx'> 	ipa_power_exit(power);</div><div class='ctx'> </div><div class='ctx'> 	dev_info(dev, "IPA driver removed");</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void ipa_shutdown(struct platform_device *pdev)</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	ret = ipa_remove(pdev);</div><div class='del'>-	if (ret)</div><div class='del'>-		dev_err(&amp;pdev-&gt;dev, "shutdown: remove returned %d\n", ret);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct attribute_group *ipa_attribute_groups[] = {</div><div class='hunk'>@@ -1001,8 +1005,8 @@ static const struct attribute_group *ipa_attribute_groups[] = {</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ipa_driver = {</div><div class='ctx'> 	.probe		= ipa_probe,</div><div class='del'>-	.remove		= ipa_remove,</div><div class='del'>-	.shutdown	= ipa_shutdown,</div><div class='add'>+	.remove_new	= ipa_remove,</div><div class='add'>+	.shutdown	= ipa_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name		= "ipa",</div><div class='ctx'> 		.pm		= &amp;ipa_pm_ops,</div><div class='head'>diff --git a/drivers/net/ipa/ipa_mem.c b/drivers/net/ipa/ipa_mem.c<br/>index db6ada2343af..694960537ecd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_mem.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_mem.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_mem.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_mem.c</a></div><div class='hunk'>@@ -165,7 +165,7 @@ static bool ipa_mem_id_valid(struct ipa *ipa, enum ipa_mem_id mem_id)</div><div class='ctx'> </div><div class='ctx'> 	case IPA_MEM_AP_V4_FILTER:</div><div class='ctx'> 	case IPA_MEM_AP_V6_FILTER:</div><div class='del'>-		if (version != IPA_VERSION_5_0)</div><div class='add'>+		if (version &lt; IPA_VERSION_5_0)</div><div class='ctx'> 			return false;</div><div class='ctx'> 		break;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ipa/ipa_reg.c b/drivers/net/ipa/ipa_reg.c<br/>index 818a84f7c42d..6a3203ae6f1e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_reg.c</a></div><div class='hunk'>@@ -44,12 +44,12 @@ static bool ipa_reg_id_valid(struct ipa *ipa, enum ipa_reg_id reg_id)</div><div class='ctx'> 	case DST_RSRC_GRP_45_RSRC_TYPE:</div><div class='ctx'> 		return version &lt;= IPA_VERSION_3_1 ||</div><div class='ctx'> 		       version == IPA_VERSION_4_5 ||</div><div class='del'>-		       version == IPA_VERSION_5_0;</div><div class='add'>+		       version &gt;= IPA_VERSION_5_0;</div><div class='ctx'> </div><div class='ctx'> 	case SRC_RSRC_GRP_67_RSRC_TYPE:</div><div class='ctx'> 	case DST_RSRC_GRP_67_RSRC_TYPE:</div><div class='ctx'> 		return version &lt;= IPA_VERSION_3_1 ||</div><div class='del'>-		       version == IPA_VERSION_5_0;</div><div class='add'>+		       version &gt;= IPA_VERSION_5_0;</div><div class='ctx'> </div><div class='ctx'> 	case ENDP_FILTER_ROUTER_HSH_CFG:</div><div class='ctx'> 		return version &lt; IPA_VERSION_5_0 &amp;&amp;</div><div class='hunk'>@@ -125,6 +125,8 @@ static const struct regs *ipa_regs(enum ipa_version version)</div><div class='ctx'> 		return &amp;ipa_regs_v4_11;</div><div class='ctx'> 	case IPA_VERSION_5_0:</div><div class='ctx'> 		return &amp;ipa_regs_v5_0;</div><div class='add'>+	case IPA_VERSION_5_5:</div><div class='add'>+		return &amp;ipa_regs_v5_5;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return NULL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h<br/>index 3ac48dea865b..2998f115f12c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_reg.h</a></div><div class='hunk'>@@ -240,25 +240,25 @@ enum ipa_reg_local_pkt_proc_cntxt_field_id {</div><div class='ctx'> </div><div class='ctx'> /* COUNTER_CFG register */</div><div class='ctx'> enum ipa_reg_counter_cfg_field_id {</div><div class='del'>-	EOT_COAL_GRANULARITY,				/* Not v3.5+ */</div><div class='add'>+	EOT_COAL_GRANULARITY,				/* Not IPA v3.5+ */</div><div class='ctx'> 	AGGR_GRANULARITY,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* IPA_TX_CFG register */</div><div class='ctx'> enum ipa_reg_ipa_tx_cfg_field_id {</div><div class='del'>-	TX0_PREFETCH_DISABLE,				/* Not v4.0+ */</div><div class='del'>-	TX1_PREFETCH_DISABLE,				/* Not v4.0+ */</div><div class='del'>-	PREFETCH_ALMOST_EMPTY_SIZE,			/* Not v4.0+ */</div><div class='del'>-	PREFETCH_ALMOST_EMPTY_SIZE_TX0,			/* v4.0+ */</div><div class='del'>-	DMAW_SCND_OUTSD_PRED_THRESHOLD,			/* v4.0+ */</div><div class='del'>-	DMAW_SCND_OUTSD_PRED_EN,			/* v4.0+ */</div><div class='del'>-	DMAW_MAX_BEATS_256_DIS,				/* v4.0+ */</div><div class='del'>-	PA_MASK_EN,					/* v4.0+ */</div><div class='del'>-	PREFETCH_ALMOST_EMPTY_SIZE_TX1,			/* v4.0+ */</div><div class='del'>-	DUAL_TX_ENABLE,					/* v4.5+ */</div><div class='del'>-	SSPND_PA_NO_START_STATE,			/* v4,2+, not v4.5 */</div><div class='del'>-	SSPND_PA_NO_BQ_STATE,				/* v4.2 only */</div><div class='del'>-	HOLB_STICKY_DROP_EN,				/* v5.0+ */</div><div class='add'>+	TX0_PREFETCH_DISABLE,				/* Not IPA v4.0+ */</div><div class='add'>+	TX1_PREFETCH_DISABLE,				/* Not IPA v4.0+ */</div><div class='add'>+	PREFETCH_ALMOST_EMPTY_SIZE,			/* Not IPA v4.0+ */</div><div class='add'>+	PREFETCH_ALMOST_EMPTY_SIZE_TX0,			/* IPA v4.0+ */</div><div class='add'>+	DMAW_SCND_OUTSD_PRED_THRESHOLD,			/* IPA v4.0+ */</div><div class='add'>+	DMAW_SCND_OUTSD_PRED_EN,			/* IPA v4.0+ */</div><div class='add'>+	DMAW_MAX_BEATS_256_DIS,				/* IPA v4.0+ */</div><div class='add'>+	PA_MASK_EN,					/* IPA v4.0+ */</div><div class='add'>+	PREFETCH_ALMOST_EMPTY_SIZE_TX1,			/* IPA v4.0+ */</div><div class='add'>+	DUAL_TX_ENABLE,					/* IPA v4.5+ */</div><div class='add'>+	SSPND_PA_NO_START_STATE,		/* IPA v4,2+, not IPA v4.5 */</div><div class='add'>+	SSPND_PA_NO_BQ_STATE,				/* IPA v4.2 only */</div><div class='add'>+	HOLB_STICKY_DROP_EN,				/* IPA v5.0+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* FLAVOR_0 register */</div><div class='hunk'>@@ -277,8 +277,8 @@ enum ipa_reg_idle_indication_cfg_field_id {</div><div class='ctx'> </div><div class='ctx'> /* QTIME_TIMESTAMP_CFG register */</div><div class='ctx'> enum ipa_reg_qtime_timestamp_cfg_field_id {</div><div class='del'>-	DPL_TIMESTAMP_LSB,</div><div class='del'>-	DPL_TIMESTAMP_SEL,</div><div class='add'>+	DPL_TIMESTAMP_LSB,				/* Not IPA v5.5+ */</div><div class='add'>+	DPL_TIMESTAMP_SEL,				/* Not IPA v5.5+ */</div><div class='ctx'> 	TAG_TIMESTAMP_LSB,</div><div class='ctx'> 	NAT_TIMESTAMP_LSB,</div><div class='ctx'> };</div><div class='hunk'>@@ -319,8 +319,8 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id {</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_CTRL register */</div><div class='ctx'> enum ipa_reg_endp_init_ctrl_field_id {</div><div class='del'>-	ENDP_SUSPEND,					/* Not v4.0+ */</div><div class='del'>-	ENDP_DELAY,					/* Not v4.2+ */</div><div class='add'>+	ENDP_SUSPEND,					/* Not IPA v4.0+ */</div><div class='add'>+	ENDP_DELAY,					/* Not IPA v4.2+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_CFG register */</div><div class='hunk'>@@ -329,6 +329,7 @@ enum ipa_reg_endp_init_cfg_field_id {</div><div class='ctx'> 	CS_OFFLOAD_EN,</div><div class='ctx'> 	CS_METADATA_HDR_OFFSET,</div><div class='ctx'> 	CS_GEN_QMB_MASTER_SEL,</div><div class='add'>+	PIPE_REPLICATE_EN,				/* IPA v5.5+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */</div><div class='hunk'>@@ -359,11 +360,11 @@ enum ipa_reg_endp_init_hdr_field_id {</div><div class='ctx'> 	HDR_ADDITIONAL_CONST_LEN,</div><div class='ctx'> 	HDR_OFST_PKT_SIZE_VALID,</div><div class='ctx'> 	HDR_OFST_PKT_SIZE,</div><div class='del'>-	HDR_A5_MUX,					/* Not v4.9+ */</div><div class='add'>+	HDR_A5_MUX,					/* Not IPA v4.9+ */</div><div class='ctx'> 	HDR_LEN_INC_DEAGG_HDR,</div><div class='del'>-	HDR_METADATA_REG_VALID,				/* Not v4.5+ */</div><div class='del'>-	HDR_LEN_MSB,					/* v4.5+ */</div><div class='del'>-	HDR_OFST_METADATA_MSB,				/* v4.5+ */</div><div class='add'>+	HDR_METADATA_REG_VALID,				/* Not IPA v4.5+ */</div><div class='add'>+	HDR_LEN_MSB,					/* IPA v4.5+ */</div><div class='add'>+	HDR_OFST_METADATA_MSB,				/* IPA v4.5+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_HDR_EXT register */</div><div class='hunk'>@@ -374,23 +375,23 @@ enum ipa_reg_endp_init_hdr_ext_field_id {</div><div class='ctx'> 	HDR_PAYLOAD_LEN_INC_PADDING,</div><div class='ctx'> 	HDR_TOTAL_LEN_OR_PAD_OFFSET,</div><div class='ctx'> 	HDR_PAD_TO_ALIGNMENT,</div><div class='del'>-	HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB,		/* v4.5+ */</div><div class='del'>-	HDR_OFST_PKT_SIZE_MSB,				/* v4.5+ */</div><div class='del'>-	HDR_ADDITIONAL_CONST_LEN_MSB,			/* v4.5+ */</div><div class='del'>-	HDR_BYTES_TO_REMOVE_VALID,			/* v5.0+ */</div><div class='del'>-	HDR_BYTES_TO_REMOVE,				/* v5.0+ */</div><div class='add'>+	HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB,		/* IPA v4.5+ */</div><div class='add'>+	HDR_OFST_PKT_SIZE_MSB,				/* IPA v4.5+ */</div><div class='add'>+	HDR_ADDITIONAL_CONST_LEN_MSB,			/* IPA v4.5+ */</div><div class='add'>+	HDR_BYTES_TO_REMOVE_VALID,			/* IPA v5.0+ */</div><div class='add'>+	HDR_BYTES_TO_REMOVE,				/* IPA v5.0+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_MODE register */</div><div class='ctx'> enum ipa_reg_endp_init_mode_field_id {</div><div class='ctx'> 	ENDP_MODE,</div><div class='del'>-	DCPH_ENABLE,					/* v4.5+ */</div><div class='add'>+	DCPH_ENABLE,					/* IPA v4.5+ */</div><div class='ctx'> 	DEST_PIPE_INDEX,</div><div class='ctx'> 	BYTE_THRESHOLD,</div><div class='del'>-	PIPE_REPLICATION_EN,</div><div class='add'>+	PIPE_REPLICATION_EN,				/* Not IPA v5.5+ */</div><div class='ctx'> 	PAD_EN,</div><div class='del'>-	HDR_FTCH_DISABLE,				/* v4.5+ */</div><div class='del'>-	DRBIP_ACL_ENABLE,				/* v4.9+ */</div><div class='add'>+	HDR_FTCH_DISABLE,				/* IPA v4.5+ */</div><div class='add'>+	DRBIP_ACL_ENABLE,				/* IPA v4.9+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */</div><div class='hunk'>@@ -412,6 +413,7 @@ enum ipa_reg_endp_init_aggr_field_id {</div><div class='ctx'> 	FORCE_CLOSE,</div><div class='ctx'> 	HARD_BYTE_LIMIT_EN,</div><div class='ctx'> 	AGGR_GRAN_SEL,</div><div class='add'>+	AGGR_COAL_L2,					/* IPA v5.5+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */</div><div class='hunk'>@@ -439,10 +441,10 @@ enum ipa_reg_endp_init_hol_block_en_field_id {</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_HOL_BLOCK_TIMER register */</div><div class='ctx'> enum ipa_reg_endp_init_hol_block_timer_field_id {</div><div class='del'>-	TIMER_BASE_VALUE,				/* Not v4.5+ */</div><div class='del'>-	TIMER_SCALE,					/* v4.2 only */</div><div class='del'>-	TIMER_LIMIT,					/* v4.5+ */</div><div class='del'>-	TIMER_GRAN_SEL,					/* v4.5+ */</div><div class='add'>+	TIMER_BASE_VALUE,				/* Not IPA v4.5+ */</div><div class='add'>+	TIMER_SCALE,					/* IPA v4.2 only */</div><div class='add'>+	TIMER_LIMIT,					/* IPA v4.5+ */</div><div class='add'>+	TIMER_GRAN_SEL,					/* IPA v4.5+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ENDP_INIT_DEAGGR register */</div><div class='hunk'>@@ -463,7 +465,7 @@ enum ipa_reg_endp_init_rsrc_grp_field_id {</div><div class='ctx'> /* ENDP_INIT_SEQ register */</div><div class='ctx'> enum ipa_reg_endp_init_seq_field_id {</div><div class='ctx'> 	SEQ_TYPE,</div><div class='del'>-	SEQ_REP_TYPE,					/* Not v4.5+ */</div><div class='add'>+	SEQ_REP_TYPE,					/* Not IPA v4.5+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -512,8 +514,8 @@ enum ipa_seq_rep_type {</div><div class='ctx'> enum ipa_reg_endp_status_field_id {</div><div class='ctx'> 	STATUS_EN,</div><div class='ctx'> 	STATUS_ENDP,</div><div class='del'>-	STATUS_LOCATION,				/* Not v4.5+ */</div><div class='del'>-	STATUS_PKT_SUPPRESS,				/* v4.0+ */</div><div class='add'>+	STATUS_LOCATION,				/* Not IPA v4.5+ */</div><div class='add'>+	STATUS_PKT_SUPPRESS,				/* IPA v4.0+ */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /* ENDP_FILTER_ROUTER_HSH_CFG register */</div><div class='hunk'>@@ -585,11 +587,12 @@ enum ipa_reg_endp_cache_cfg_field_id {</div><div class='ctx'>  * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used)</div><div class='ctx'>  * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used)</div><div class='ctx'>  * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used)</div><div class='add'>+ * @IPA_IRQ_ERROR_NON_FATAL:		(Not currently used)</div><div class='add'>+ * @IPA_IRQ_ERROR_FATAL:		(Not currently used)</div><div class='ctx'>  */</div><div class='ctx'> enum ipa_irq_id {</div><div class='del'>-	IPA_IRQ_BAD_SNOC_ACCESS			= 0x0,</div><div class='del'>-	/* The next bit is not present for IPA v3.5+ */</div><div class='del'>-	IPA_IRQ_EOT_COAL			= 0x1,</div><div class='add'>+	IPA_IRQ_BAD_SNOC_ACCESS			= 0x0,	/* Not IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_EOT_COAL			= 0x1,	/* Not IPA v3.5+ */</div><div class='ctx'> 	IPA_IRQ_UC_0				= 0x2,</div><div class='ctx'> 	IPA_IRQ_UC_1				= 0x3,</div><div class='ctx'> 	IPA_IRQ_UC_2				= 0x4,</div><div class='hunk'>@@ -597,11 +600,11 @@ enum ipa_irq_id {</div><div class='ctx'> 	IPA_IRQ_UC_IN_Q_NOT_EMPTY		= 0x6,</div><div class='ctx'> 	IPA_IRQ_UC_RX_CMD_Q_NOT_FULL		= 0x7,</div><div class='ctx'> 	IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY		= 0x8,</div><div class='del'>-	IPA_IRQ_RX_ERR				= 0x9,</div><div class='del'>-	IPA_IRQ_DEAGGR_ERR			= 0xa,</div><div class='del'>-	IPA_IRQ_TX_ERR				= 0xb,</div><div class='del'>-	IPA_IRQ_STEP_MODE			= 0xc,</div><div class='del'>-	IPA_IRQ_PROC_ERR			= 0xd,</div><div class='add'>+	IPA_IRQ_RX_ERR				= 0x9,	/* Not IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_DEAGGR_ERR			= 0xa,	/* Not IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_TX_ERR				= 0xb,	/* Not IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_STEP_MODE			= 0xc,	/* Not IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_PROC_ERR			= 0xd,	/* Not IPA v5.5+ */</div><div class='ctx'> 	IPA_IRQ_TX_SUSPEND			= 0xe,</div><div class='ctx'> 	IPA_IRQ_TX_HOLB_DROP			= 0xf,</div><div class='ctx'> 	IPA_IRQ_BAM_GSI_IDLE			= 0x10,</div><div class='hunk'>@@ -610,17 +613,16 @@ enum ipa_irq_id {</div><div class='ctx'> 	IPA_IRQ_PIPE_YELLOW_ABOVE		= 0x13,</div><div class='ctx'> 	IPA_IRQ_PIPE_RED_ABOVE			= 0x14,</div><div class='ctx'> 	IPA_IRQ_UCP				= 0x15,</div><div class='del'>-	/* The next bit is not present for IPA v4.5+ */</div><div class='del'>-	IPA_IRQ_DCMP				= 0x16,</div><div class='add'>+	IPA_IRQ_DCMP				= 0x16,	/* Not IPA v4.5+ */</div><div class='ctx'> 	IPA_IRQ_GSI_EE				= 0x17,</div><div class='ctx'> 	IPA_IRQ_GSI_IPA_IF_TLV_RCVD		= 0x18,</div><div class='ctx'> 	IPA_IRQ_GSI_UC				= 0x19,</div><div class='del'>-	/* The next bit is present for IPA v4.5+ */</div><div class='del'>-	IPA_IRQ_TLV_LEN_MIN_DSM			= 0x1a,</div><div class='del'>-	/* The next three bits are present for IPA v4.9+ */</div><div class='del'>-	IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN	= 0x1b,</div><div class='del'>-	IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN	= 0x1c,</div><div class='del'>-	IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN	= 0x1d,</div><div class='add'>+	IPA_IRQ_TLV_LEN_MIN_DSM			= 0x1a,	/* IPA v4.5-v5.2 */</div><div class='add'>+	IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN	= 0x1b,	/* IPA v4.9-v5.2 */</div><div class='add'>+	IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN	= 0x1c,	/* IPA v4.9-v5.2 */</div><div class='add'>+	IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN	= 0x1d,	/* IPA v4.9-v5.2 */</div><div class='add'>+	IPA_IRQ_ERROR_NON_FATAL			= 0x1e,	/* IPA v5.5+ */</div><div class='add'>+	IPA_IRQ_ERROR_FATAL			= 0x1f,	/* IPA v5.5+ */</div><div class='ctx'> 	IPA_IRQ_COUNT,				/* Last; not an id */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -637,6 +639,7 @@ extern const struct regs ipa_regs_v4_7;</div><div class='ctx'> extern const struct regs ipa_regs_v4_9;</div><div class='ctx'> extern const struct regs ipa_regs_v4_11;</div><div class='ctx'> extern const struct regs ipa_regs_v5_0;</div><div class='add'>+extern const struct regs ipa_regs_v5_5;</div><div class='ctx'> </div><div class='ctx'> const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h<br/>index 06e75b8ece7e..38150345b607 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_version.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipa/ipa_version.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/ipa_version.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/ipa_version.h</a></div><div class='hunk'>@@ -56,6 +56,7 @@ static inline bool ipa_version_supported(enum ipa_version version)</div><div class='ctx'> 	case IPA_VERSION_4_9:</div><div class='ctx'> 	case IPA_VERSION_4_11:</div><div class='ctx'> 	case IPA_VERSION_5_0:</div><div class='add'>+	case IPA_VERSION_5_5:</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='head'>diff --git a/drivers/net/ipa/reg/ipa_reg-v5.5.c b/drivers/net/ipa/reg/ipa_reg-v5.5.c<br/>new file mode 100644<br/>index 000000000000..26ca9c9bac59<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipa/reg/ipa_reg-v5.5.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipa/reg/ipa_reg-v5.5.c</a></div><div class='hunk'>@@ -0,0 +1,565 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+/* Copyright (C) 2023 Linaro Ltd. */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/types.h&gt;</div><div class='add'>+#include &lt;linux/bits.h&gt;</div><div class='add'>+</div><div class='add'>+#include "../ipa_reg.h"</div><div class='add'>+#include "../ipa_version.h"</div><div class='add'>+</div><div class='add'>+static const u32 reg_flavor_0_fmask[] = {</div><div class='add'>+	[MAX_PIPES]					= GENMASK(7, 0),</div><div class='add'>+	[MAX_CONS_PIPES]				= GENMASK(15, 8),</div><div class='add'>+	[MAX_PROD_PIPES]				= GENMASK(23, 16),</div><div class='add'>+	[PROD_LOWEST]					= GENMASK(31, 24),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);</div><div class='add'>+</div><div class='add'>+static const u32 reg_comp_cfg_fmask[] = {</div><div class='add'>+	[RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS]		= BIT(0),</div><div class='add'>+	[GSI_SNOC_BYPASS_DIS]				= BIT(1),</div><div class='add'>+	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),</div><div class='add'>+	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),</div><div class='add'>+						/* Bit 4 reserved */</div><div class='add'>+	[IPA_QMB_SELECT_CONS_EN]			= BIT(5),</div><div class='add'>+	[IPA_QMB_SELECT_PROD_EN]			= BIT(6),</div><div class='add'>+	[GSI_MULTI_INORDER_RD_DIS]			= BIT(7),</div><div class='add'>+	[GSI_MULTI_INORDER_WR_DIS]			= BIT(8),</div><div class='add'>+	[GEN_QMB_0_MULTI_INORDER_RD_DIS]		= BIT(9),</div><div class='add'>+	[GEN_QMB_1_MULTI_INORDER_RD_DIS]		= BIT(10),</div><div class='add'>+	[GEN_QMB_0_MULTI_INORDER_WR_DIS]		= BIT(11),</div><div class='add'>+	[GEN_QMB_1_MULTI_INORDER_WR_DIS]		= BIT(12),</div><div class='add'>+	[GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS]		= BIT(13),</div><div class='add'>+	[GSI_SNOC_CNOC_LOOP_PROT_DISABLE]		= BIT(14),</div><div class='add'>+	[GSI_MULTI_AXI_MASTERS_DIS]			= BIT(15),</div><div class='add'>+	[IPA_QMB_SELECT_GLOBAL_EN]			= BIT(16),</div><div class='add'>+						/* Bits 17-18 reserved */</div><div class='add'>+	[QMB_RAM_RD_CACHE_DISABLE]			= BIT(19),</div><div class='add'>+	[GENQMB_AOOOWR]					= BIT(20),</div><div class='add'>+	[IF_OUT_OF_BUF_STOP_RESET_MASK_EN]		= BIT(21),</div><div class='add'>+	[ATOMIC_FETCHER_ARB_LOCK_DIS]			= GENMASK(27, 22),</div><div class='add'>+						/* Bits 28-29 reserved */</div><div class='add'>+	[GEN_QMB_1_DYNAMIC_ASIZE]			= BIT(30),</div><div class='add'>+	[GEN_QMB_0_DYNAMIC_ASIZE]			= BIT(31),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(COMP_CFG, comp_cfg, 0x00000048);</div><div class='add'>+</div><div class='add'>+static const u32 reg_clkon_cfg_fmask[] = {</div><div class='add'>+	[CLKON_RX]					= BIT(0),</div><div class='add'>+	[CLKON_PROC]					= BIT(1),</div><div class='add'>+	[TX_WRAPPER]					= BIT(2),</div><div class='add'>+	[CLKON_MISC]					= BIT(3),</div><div class='add'>+	[RAM_ARB]					= BIT(4),</div><div class='add'>+	[FTCH_HPS]					= BIT(5),</div><div class='add'>+	[FTCH_DPS]					= BIT(6),</div><div class='add'>+	[CLKON_HPS]					= BIT(7),</div><div class='add'>+	[CLKON_DPS]					= BIT(8),</div><div class='add'>+	[RX_HPS_CMDQS]					= BIT(9),</div><div class='add'>+	[HPS_DPS_CMDQS]					= BIT(10),</div><div class='add'>+	[DPS_TX_CMDQS]					= BIT(11),</div><div class='add'>+	[RSRC_MNGR]					= BIT(12),</div><div class='add'>+	[CTX_HANDLER]					= BIT(13),</div><div class='add'>+	[ACK_MNGR]					= BIT(14),</div><div class='add'>+	[D_DCPH]					= BIT(15),</div><div class='add'>+	[H_DCPH]					= BIT(16),</div><div class='add'>+						/* Bit 17 reserved */</div><div class='add'>+	[NTF_TX_CMDQS]					= BIT(18),</div><div class='add'>+	[CLKON_TX_0]					= BIT(19),</div><div class='add'>+	[CLKON_TX_1]					= BIT(20),</div><div class='add'>+	[CLKON_FNR]					= BIT(21),</div><div class='add'>+	[QSB2AXI_CMDQ_L]				= BIT(22),</div><div class='add'>+	[AGGR_WRAPPER]					= BIT(23),</div><div class='add'>+	[RAM_SLAVEWAY]					= BIT(24),</div><div class='add'>+	[CLKON_QMB]					= BIT(25),</div><div class='add'>+	[WEIGHT_ARB]					= BIT(26),</div><div class='add'>+	[GSI_IF]					= BIT(27),</div><div class='add'>+	[CLKON_GLOBAL]					= BIT(28),</div><div class='add'>+	[GLOBAL_2X_CLK]					= BIT(29),</div><div class='add'>+	[DPL_FIFO]					= BIT(30),</div><div class='add'>+	[DRBIP]						= BIT(31),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000050);</div><div class='add'>+</div><div class='add'>+static const u32 reg_route_fmask[] = {</div><div class='add'>+	[ROUTE_DEF_PIPE]				= GENMASK(7, 0),</div><div class='add'>+	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(15, 8),</div><div class='add'>+	[ROUTE_DEF_HDR_OFST]				= GENMASK(25, 16),</div><div class='add'>+	[ROUTE_DEF_HDR_TABLE]				= BIT(26),</div><div class='add'>+	[ROUTE_DEF_RETAIN_HDR]				= BIT(27),</div><div class='add'>+	[ROUTE_DIS]					= BIT(28),</div><div class='add'>+						/* Bits 29-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(ROUTE, route, 0x00000054);</div><div class='add'>+</div><div class='add'>+static const u32 reg_shared_mem_size_fmask[] = {</div><div class='add'>+	[MEM_SIZE]					= GENMASK(15, 0),</div><div class='add'>+	[MEM_BADDR]					= GENMASK(31, 16),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x0000005c);</div><div class='add'>+</div><div class='add'>+static const u32 reg_qsb_max_writes_fmask[] = {</div><div class='add'>+	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),</div><div class='add'>+	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),</div><div class='add'>+						/* Bits 8-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000070);</div><div class='add'>+</div><div class='add'>+static const u32 reg_qsb_max_reads_fmask[] = {</div><div class='add'>+	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),</div><div class='add'>+	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),</div><div class='add'>+						/* Bits 8-15 reserved */</div><div class='add'>+	[GEN_QMB_0_MAX_READS_BEATS]			= GENMASK(23, 16),</div><div class='add'>+	[GEN_QMB_1_MAX_READS_BEATS]			= GENMASK(31, 24),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000074);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by ipa-&gt;available */</div><div class='add'>+</div><div class='add'>+REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000120, 0x0004);</div><div class='add'>+</div><div class='add'>+static const u32 reg_filt_rout_cache_flush_fmask[] = {</div><div class='add'>+	[ROUTER_CACHE]					= BIT(0),</div><div class='add'>+						/* Bits 1-3 reserved */</div><div class='add'>+	[FILTER_CACHE]					= BIT(4),</div><div class='add'>+						/* Bits 5-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);</div><div class='add'>+</div><div class='add'>+static const u32 reg_local_pkt_proc_cntxt_fmask[] = {</div><div class='add'>+	[IPA_BASE_ADDR]					= GENMASK(17, 0),</div><div class='add'>+						/* Bits 18-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* Offset must be a multiple of 8 */</div><div class='add'>+REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);</div><div class='add'>+</div><div class='add'>+static const u32 reg_ipa_tx_cfg_fmask[] = {</div><div class='add'>+						/* Bits 0-1 reserved */</div><div class='add'>+	[PREFETCH_ALMOST_EMPTY_SIZE_TX0]		= GENMASK(5, 2),</div><div class='add'>+	[DMAW_SCND_OUTSD_PRED_THRESHOLD]		= GENMASK(9, 6),</div><div class='add'>+	[DMAW_SCND_OUTSD_PRED_EN]			= BIT(10),</div><div class='add'>+	[DMAW_MAX_BEATS_256_DIS]			= BIT(11),</div><div class='add'>+	[PA_MASK_EN]					= BIT(12),</div><div class='add'>+	[PREFETCH_ALMOST_EMPTY_SIZE_TX1]		= GENMASK(16, 13),</div><div class='add'>+	[DUAL_TX_ENABLE]				= BIT(17),</div><div class='add'>+	[SSPND_PA_NO_START_STATE]			= BIT(18),</div><div class='add'>+						/* Bit 19 reserved */</div><div class='add'>+	[HOLB_STICKY_DROP_EN]				= BIT(20),</div><div class='add'>+						/* Bits 21-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);</div><div class='add'>+</div><div class='add'>+static const u32 reg_idle_indication_cfg_fmask[] = {</div><div class='add'>+	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),</div><div class='add'>+	[CONST_NON_IDLE_ENABLE]				= BIT(16),</div><div class='add'>+						/* Bits 17-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);</div><div class='add'>+</div><div class='add'>+static const u32 reg_qtime_timestamp_cfg_fmask[] = {</div><div class='add'>+						/* Bits 0-7 reserved */</div><div class='add'>+	[TAG_TIMESTAMP_LSB]				= GENMASK(12, 8),</div><div class='add'>+						/* Bits 13-15 reserved */</div><div class='add'>+	[NAT_TIMESTAMP_LSB]				= GENMASK(20, 16),</div><div class='add'>+						/* Bits 21-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);</div><div class='add'>+</div><div class='add'>+static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {</div><div class='add'>+	[DIV_VALUE]					= GENMASK(8, 0),</div><div class='add'>+						/* Bits 9-30 reserved */</div><div class='add'>+	[DIV_ENABLE]					= BIT(31),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);</div><div class='add'>+</div><div class='add'>+static const u32 reg_timers_pulse_gran_cfg_fmask[] = {</div><div class='add'>+	[PULSE_GRAN_0]					= GENMASK(2, 0),</div><div class='add'>+	[PULSE_GRAN_1]					= GENMASK(5, 3),</div><div class='add'>+	[PULSE_GRAN_2]					= GENMASK(8, 6),</div><div class='add'>+	[PULSE_GRAN_3]					= GENMASK(11, 9),</div><div class='add'>+						/* Bits 12-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);</div><div class='add'>+</div><div class='add'>+static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,</div><div class='add'>+		  0x00000500, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,</div><div class='add'>+		  0x00000504, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,</div><div class='add'>+		  0x00000508, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,</div><div class='add'>+		  0x0000050c, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,</div><div class='add'>+		  0x00000600, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,</div><div class='add'>+		  0x00000604, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,</div><div class='add'>+		  0x00000608, 0x0020);</div><div class='add'>+</div><div class='add'>+static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {</div><div class='add'>+	[X_MIN_LIM]					= GENMASK(5, 0),</div><div class='add'>+						/* Bits 6-7 reserved */</div><div class='add'>+	[X_MAX_LIM]					= GENMASK(13, 8),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[Y_MIN_LIM]					= GENMASK(21, 16),</div><div class='add'>+						/* Bits 22-23 reserved */</div><div class='add'>+	[Y_MAX_LIM]					= GENMASK(29, 24),</div><div class='add'>+						/* Bits 30-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,</div><div class='add'>+		  0x0000060c, 0x0020);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by ipa-&gt;available */</div><div class='add'>+</div><div class='add'>+REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_cfg_fmask[] = {</div><div class='add'>+	[FRAG_OFFLOAD_EN]				= BIT(0),</div><div class='add'>+	[CS_OFFLOAD_EN]					= GENMASK(2, 1),</div><div class='add'>+	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),</div><div class='add'>+						/* Bit 7 reserved */</div><div class='add'>+	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),</div><div class='add'>+	[PIPE_REPLICATE_EN]				= BIT(9),</div><div class='add'>+						/* Bits 10-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_nat_fmask[] = {</div><div class='add'>+	[NAT_EN]					= GENMASK(1, 0),</div><div class='add'>+						/* Bits 2-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_hdr_fmask[] = {</div><div class='add'>+	[HDR_LEN]					= GENMASK(5, 0),</div><div class='add'>+	[HDR_OFST_METADATA_VALID]			= BIT(6),</div><div class='add'>+	[HDR_OFST_METADATA]				= GENMASK(12, 7),</div><div class='add'>+	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),</div><div class='add'>+	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),</div><div class='add'>+	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),</div><div class='add'>+						/* Bit 26 reserved */</div><div class='add'>+	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),</div><div class='add'>+	[HDR_LEN_MSB]					= GENMASK(29, 28),</div><div class='add'>+	[HDR_OFST_METADATA_MSB]				= GENMASK(31, 30),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_hdr_ext_fmask[] = {</div><div class='add'>+	[HDR_ENDIANNESS]				= BIT(0),</div><div class='add'>+	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),</div><div class='add'>+	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),</div><div class='add'>+	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),</div><div class='add'>+	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),</div><div class='add'>+	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),</div><div class='add'>+						/* Bits 14-15 reserved */</div><div class='add'>+	[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB]		= GENMASK(17, 16),</div><div class='add'>+	[HDR_OFST_PKT_SIZE_MSB]				= GENMASK(19, 18),</div><div class='add'>+	[HDR_ADDITIONAL_CONST_LEN_MSB]			= GENMASK(21, 20),</div><div class='add'>+	[HDR_BYTES_TO_REMOVE_VALID]			= BIT(22),</div><div class='add'>+						/* Bit 23 reserved */</div><div class='add'>+	[HDR_BYTES_TO_REMOVE]				= GENMASK(31, 24),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);</div><div class='add'>+</div><div class='add'>+REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,</div><div class='add'>+	   0x00001018, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_mode_fmask[] = {</div><div class='add'>+	[ENDP_MODE]					= GENMASK(2, 0),</div><div class='add'>+	[DCPH_ENABLE]					= BIT(3),</div><div class='add'>+	[DEST_PIPE_INDEX]				= GENMASK(11, 4),</div><div class='add'>+	[BYTE_THRESHOLD]				= GENMASK(27, 12),</div><div class='add'>+						/* Bit 28 reserved */</div><div class='add'>+	[PAD_EN]					= BIT(29),</div><div class='add'>+	[DRBIP_ACL_ENABLE]				= BIT(30),</div><div class='add'>+						/* Bit 31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_aggr_fmask[] = {</div><div class='add'>+	[AGGR_EN]					= GENMASK(1, 0),</div><div class='add'>+	[AGGR_TYPE]					= GENMASK(4, 2),</div><div class='add'>+	[BYTE_LIMIT]					= GENMASK(10, 5),</div><div class='add'>+						/* Bit 11 reserved */</div><div class='add'>+	[TIME_LIMIT]					= GENMASK(16, 12),</div><div class='add'>+	[PKT_LIMIT]					= GENMASK(22, 17),</div><div class='add'>+	[SW_EOF_ACTIVE]					= BIT(23),</div><div class='add'>+	[FORCE_CLOSE]					= BIT(24),</div><div class='add'>+						/* Bit 25 reserved */</div><div class='add'>+	[HARD_BYTE_LIMIT_EN]				= BIT(26),</div><div class='add'>+	[AGGR_GRAN_SEL]					= BIT(27),</div><div class='add'>+	[AGGR_COAL_L2]					= BIT(28),</div><div class='add'>+						/* Bits 27-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_hol_block_en_fmask[] = {</div><div class='add'>+	[HOL_BLOCK_EN]					= BIT(0),</div><div class='add'>+						/* Bits 1-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,</div><div class='add'>+		  0x0000102c, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_hol_block_timer_fmask[] = {</div><div class='add'>+	[TIMER_LIMIT]					= GENMASK(4, 0),</div><div class='add'>+						/* Bits 5-7 reserved */</div><div class='add'>+	[TIMER_GRAN_SEL]				= GENMASK(9, 8),</div><div class='add'>+						/* Bits 10-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,</div><div class='add'>+		  0x00001030, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_deaggr_fmask[] = {</div><div class='add'>+	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),</div><div class='add'>+	[SYSPIPE_ERR_DETECTION]				= BIT(6),</div><div class='add'>+	[PACKET_OFFSET_VALID]				= BIT(7),</div><div class='add'>+	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),</div><div class='add'>+	[IGNORE_MIN_PKT_ERR]				= BIT(14),</div><div class='add'>+						/* Bit 15 reserved */</div><div class='add'>+	[MAX_PACKET_LEN]				= GENMASK(31, 16),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_rsrc_grp_fmask[] = {</div><div class='add'>+	[ENDP_RSRC_GRP]					= GENMASK(2, 0),</div><div class='add'>+						/* Bits 3-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_init_seq_fmask[] = {</div><div class='add'>+	[SEQ_TYPE]					= GENMASK(7, 0),</div><div class='add'>+						/* Bits 8-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_status_fmask[] = {</div><div class='add'>+	[STATUS_EN]					= BIT(0),</div><div class='add'>+	[STATUS_ENDP]					= GENMASK(8, 1),</div><div class='add'>+	[STATUS_PKT_SUPPRESS]				= BIT(9),</div><div class='add'>+						/* Bits 10-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_filter_cache_cfg_fmask[] = {</div><div class='add'>+	[CACHE_MSK_SRC_ID]				= BIT(0),</div><div class='add'>+	[CACHE_MSK_SRC_IP]				= BIT(1),</div><div class='add'>+	[CACHE_MSK_DST_IP]				= BIT(2),</div><div class='add'>+	[CACHE_MSK_SRC_PORT]				= BIT(3),</div><div class='add'>+	[CACHE_MSK_DST_PORT]				= BIT(4),</div><div class='add'>+	[CACHE_MSK_PROTOCOL]				= BIT(5),</div><div class='add'>+	[CACHE_MSK_METADATA]				= BIT(6),</div><div class='add'>+						/* Bits 7-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,</div><div class='add'>+		  0x0000105c, 0x0080);</div><div class='add'>+</div><div class='add'>+static const u32 reg_endp_router_cache_cfg_fmask[] = {</div><div class='add'>+	[CACHE_MSK_SRC_ID]				= BIT(0),</div><div class='add'>+	[CACHE_MSK_SRC_IP]				= BIT(1),</div><div class='add'>+	[CACHE_MSK_DST_IP]				= BIT(2),</div><div class='add'>+	[CACHE_MSK_SRC_PORT]				= BIT(3),</div><div class='add'>+	[CACHE_MSK_DST_PORT]				= BIT(4),</div><div class='add'>+	[CACHE_MSK_PROTOCOL]				= BIT(5),</div><div class='add'>+	[CACHE_MSK_METADATA]				= BIT(6),</div><div class='add'>+						/* Bits 7-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,</div><div class='add'>+		  0x00001060, 0x0080);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */</div><div class='add'>+REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */</div><div class='add'>+REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */</div><div class='add'>+REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);</div><div class='add'>+</div><div class='add'>+static const u32 reg_ipa_irq_uc_fmask[] = {</div><div class='add'>+	[UC_INTR]					= BIT(0),</div><div class='add'>+						/* Bits 1-31 reserved */</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by ipa-&gt;available */</div><div class='add'>+</div><div class='add'>+REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,</div><div class='add'>+	   0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by ipa-&gt;available */</div><div class='add'>+</div><div class='add'>+REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,</div><div class='add'>+	   0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);</div><div class='add'>+</div><div class='add'>+/* Valid bits defined by ipa-&gt;available */</div><div class='add'>+</div><div class='add'>+REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,</div><div class='add'>+	   0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);</div><div class='add'>+</div><div class='add'>+static const struct reg *reg_array[] = {</div><div class='add'>+	[COMP_CFG]			= &amp;reg_comp_cfg,</div><div class='add'>+	[CLKON_CFG]			= &amp;reg_clkon_cfg,</div><div class='add'>+	[ROUTE]				= &amp;reg_route,</div><div class='add'>+	[SHARED_MEM_SIZE]		= &amp;reg_shared_mem_size,</div><div class='add'>+	[QSB_MAX_WRITES]		= &amp;reg_qsb_max_writes,</div><div class='add'>+	[QSB_MAX_READS]			= &amp;reg_qsb_max_reads,</div><div class='add'>+	[FILT_ROUT_CACHE_FLUSH]		= &amp;reg_filt_rout_cache_flush,</div><div class='add'>+	[STATE_AGGR_ACTIVE]		= &amp;reg_state_aggr_active,</div><div class='add'>+	[LOCAL_PKT_PROC_CNTXT]		= &amp;reg_local_pkt_proc_cntxt,</div><div class='add'>+	[AGGR_FORCE_CLOSE]		= &amp;reg_aggr_force_close,</div><div class='add'>+	[IPA_TX_CFG]			= &amp;reg_ipa_tx_cfg,</div><div class='add'>+	[FLAVOR_0]			= &amp;reg_flavor_0,</div><div class='add'>+	[IDLE_INDICATION_CFG]		= &amp;reg_idle_indication_cfg,</div><div class='add'>+	[QTIME_TIMESTAMP_CFG]		= &amp;reg_qtime_timestamp_cfg,</div><div class='add'>+	[TIMERS_XO_CLK_DIV_CFG]		= &amp;reg_timers_xo_clk_div_cfg,</div><div class='add'>+	[TIMERS_PULSE_GRAN_CFG]		= &amp;reg_timers_pulse_gran_cfg,</div><div class='add'>+	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &amp;reg_src_rsrc_grp_01_rsrc_type,</div><div class='add'>+	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &amp;reg_src_rsrc_grp_23_rsrc_type,</div><div class='add'>+	[SRC_RSRC_GRP_45_RSRC_TYPE]	= &amp;reg_src_rsrc_grp_45_rsrc_type,</div><div class='add'>+	[SRC_RSRC_GRP_67_RSRC_TYPE]	= &amp;reg_src_rsrc_grp_67_rsrc_type,</div><div class='add'>+	[DST_RSRC_GRP_01_RSRC_TYPE]	= &amp;reg_dst_rsrc_grp_01_rsrc_type,</div><div class='add'>+	[DST_RSRC_GRP_23_RSRC_TYPE]	= &amp;reg_dst_rsrc_grp_23_rsrc_type,</div><div class='add'>+	[DST_RSRC_GRP_45_RSRC_TYPE]	= &amp;reg_dst_rsrc_grp_45_rsrc_type,</div><div class='add'>+	[DST_RSRC_GRP_67_RSRC_TYPE]	= &amp;reg_dst_rsrc_grp_67_rsrc_type,</div><div class='add'>+	[ENDP_INIT_CFG]			= &amp;reg_endp_init_cfg,</div><div class='add'>+	[ENDP_INIT_NAT]			= &amp;reg_endp_init_nat,</div><div class='add'>+	[ENDP_INIT_HDR]			= &amp;reg_endp_init_hdr,</div><div class='add'>+	[ENDP_INIT_HDR_EXT]		= &amp;reg_endp_init_hdr_ext,</div><div class='add'>+	[ENDP_INIT_HDR_METADATA_MASK]	= &amp;reg_endp_init_hdr_metadata_mask,</div><div class='add'>+	[ENDP_INIT_MODE]		= &amp;reg_endp_init_mode,</div><div class='add'>+	[ENDP_INIT_AGGR]		= &amp;reg_endp_init_aggr,</div><div class='add'>+	[ENDP_INIT_HOL_BLOCK_EN]	= &amp;reg_endp_init_hol_block_en,</div><div class='add'>+	[ENDP_INIT_HOL_BLOCK_TIMER]	= &amp;reg_endp_init_hol_block_timer,</div><div class='add'>+	[ENDP_INIT_DEAGGR]		= &amp;reg_endp_init_deaggr,</div><div class='add'>+	[ENDP_INIT_RSRC_GRP]		= &amp;reg_endp_init_rsrc_grp,</div><div class='add'>+	[ENDP_INIT_SEQ]			= &amp;reg_endp_init_seq,</div><div class='add'>+	[ENDP_STATUS]			= &amp;reg_endp_status,</div><div class='add'>+	[ENDP_FILTER_CACHE_CFG]		= &amp;reg_endp_filter_cache_cfg,</div><div class='add'>+	[ENDP_ROUTER_CACHE_CFG]		= &amp;reg_endp_router_cache_cfg,</div><div class='add'>+	[IPA_IRQ_STTS]			= &amp;reg_ipa_irq_stts,</div><div class='add'>+	[IPA_IRQ_EN]			= &amp;reg_ipa_irq_en,</div><div class='add'>+	[IPA_IRQ_CLR]			= &amp;reg_ipa_irq_clr,</div><div class='add'>+	[IPA_IRQ_UC]			= &amp;reg_ipa_irq_uc,</div><div class='add'>+	[IRQ_SUSPEND_INFO]		= &amp;reg_irq_suspend_info,</div><div class='add'>+	[IRQ_SUSPEND_EN]		= &amp;reg_irq_suspend_en,</div><div class='add'>+	[IRQ_SUSPEND_CLR]		= &amp;reg_irq_suspend_clr,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+const struct regs ipa_regs_v5_5 = {</div><div class='add'>+	.reg_count	= ARRAY_SIZE(reg_array),</div><div class='add'>+	.reg		= reg_array,</div><div class='add'>+};</div><div class='head'>diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c<br/>index 57c79f5f2991..df7c43a109e1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ipvlan/ipvlan_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ipvlan/ipvlan_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ipvlan/ipvlan_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ipvlan/ipvlan_main.c</a></div><div class='hunk'>@@ -387,6 +387,7 @@ static const struct header_ops ipvlan_header_ops = {</div><div class='ctx'> 	.parse		= eth_header_parse,</div><div class='ctx'> 	.cache		= eth_header_cache,</div><div class='ctx'> 	.cache_update	= eth_header_cache_update,</div><div class='add'>+	.parse_protocol	= eth_header_parse_protocol,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static void ipvlan_adjust_mtu(struct ipvl_dev *ipvlan, struct net_device *dev)</div><div class='hunk'>@@ -600,15 +601,15 @@ int ipvlan_link_new(struct net *src_net, struct net_device *dev,</div><div class='ctx'> 		port-&gt;dev_id_start = 0x1;</div><div class='ctx'> </div><div class='ctx'> 	/* Since L2 address is shared among all IPvlan slaves including</div><div class='del'>-	 * master, use unique 16 bit dev-ids to diffentiate among them.</div><div class='add'>+	 * master, use unique 16 bit dev-ids to differentiate among them.</div><div class='ctx'> 	 * Assign IDs between 0x1 and 0xFFFE (used by the master) to each</div><div class='ctx'> 	 * slave link [see addrconf_ifid_eui48()].</div><div class='ctx'> 	 */</div><div class='del'>-	err = ida_simple_get(&amp;port-&gt;ida, port-&gt;dev_id_start, 0xFFFE,</div><div class='del'>-			     GFP_KERNEL);</div><div class='add'>+	err = ida_alloc_range(&amp;port-&gt;ida, port-&gt;dev_id_start, 0xFFFD,</div><div class='add'>+			      GFP_KERNEL);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='del'>-		err = ida_simple_get(&amp;port-&gt;ida, 0x1, port-&gt;dev_id_start,</div><div class='del'>-				     GFP_KERNEL);</div><div class='add'>+		err = ida_alloc_range(&amp;port-&gt;ida, 0x1, port-&gt;dev_id_start - 1,</div><div class='add'>+				      GFP_KERNEL);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		goto unregister_netdev;</div><div class='ctx'> 	dev-&gt;dev_id = err;</div><div class='hunk'>@@ -640,7 +641,7 @@ int ipvlan_link_new(struct net *src_net, struct net_device *dev,</div><div class='ctx'> unlink_netdev:</div><div class='ctx'> 	netdev_upper_dev_unlink(phy_dev, dev);</div><div class='ctx'> remove_ida:</div><div class='del'>-	ida_simple_remove(&amp;port-&gt;ida, dev-&gt;dev_id);</div><div class='add'>+	ida_free(&amp;port-&gt;ida, dev-&gt;dev_id);</div><div class='ctx'> unregister_netdev:</div><div class='ctx'> 	unregister_netdevice(dev);</div><div class='ctx'> 	return err;</div><div class='hunk'>@@ -660,7 +661,7 @@ void ipvlan_link_delete(struct net_device *dev, struct list_head *head)</div><div class='ctx'> 	}</div><div class='ctx'> 	spin_unlock_bh(&amp;ipvlan-&gt;addrs_lock);</div><div class='ctx'> </div><div class='del'>-	ida_simple_remove(&amp;ipvlan-&gt;port-&gt;ida, dev-&gt;dev_id);</div><div class='add'>+	ida_free(&amp;ipvlan-&gt;port-&gt;ida, dev-&gt;dev_id);</div><div class='ctx'> 	list_del_rcu(&amp;ipvlan-&gt;pnode);</div><div class='ctx'> 	unregister_netdevice_queue(dev, head);</div><div class='ctx'> 	netdev_upper_dev_unlink(ipvlan-&gt;phy_dev, dev);</div><div class='head'>diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c<br/>index 9663050a852d..e34816638569 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/macsec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/macsec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/macsec.c</a></div><div class='hunk'>@@ -93,6 +93,8 @@ struct pcpu_secy_stats {</div><div class='ctx'>  * @secys: linked list of SecY's on the underlying device</div><div class='ctx'>  * @gro_cells: pointer to the Generic Receive Offload cell</div><div class='ctx'>  * @offload: status of offloading on the MACsec device</div><div class='add'>+ * @insert_tx_tag: when offloading, device requires to insert an</div><div class='add'>+ *	additional tag</div><div class='ctx'>  */</div><div class='ctx'> struct macsec_dev {</div><div class='ctx'> 	struct macsec_secy secy;</div><div class='hunk'>@@ -102,6 +104,7 @@ struct macsec_dev {</div><div class='ctx'> 	struct list_head secys;</div><div class='ctx'> 	struct gro_cells gro_cells;</div><div class='ctx'> 	enum macsec_offload offload;</div><div class='add'>+	bool insert_tx_tag;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -604,26 +607,11 @@ static struct sk_buff *macsec_encrypt(struct sk_buff *skb,</div><div class='ctx'> 		return ERR_PTR(-EINVAL);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (unlikely(skb_headroom(skb) &lt; MACSEC_NEEDED_HEADROOM ||</div><div class='del'>-		     skb_tailroom(skb) &lt; MACSEC_NEEDED_TAILROOM)) {</div><div class='del'>-		struct sk_buff *nskb = skb_copy_expand(skb,</div><div class='del'>-						       MACSEC_NEEDED_HEADROOM,</div><div class='del'>-						       MACSEC_NEEDED_TAILROOM,</div><div class='del'>-						       GFP_ATOMIC);</div><div class='del'>-		if (likely(nskb)) {</div><div class='del'>-			consume_skb(skb);</div><div class='del'>-			skb = nskb;</div><div class='del'>-		} else {</div><div class='del'>-			macsec_txsa_put(tx_sa);</div><div class='del'>-			kfree_skb(skb);</div><div class='del'>-			return ERR_PTR(-ENOMEM);</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		skb = skb_unshare(skb, GFP_ATOMIC);</div><div class='del'>-		if (!skb) {</div><div class='del'>-			macsec_txsa_put(tx_sa);</div><div class='del'>-			return ERR_PTR(-ENOMEM);</div><div class='del'>-		}</div><div class='add'>+	ret = skb_ensure_writable_head_tail(skb, dev);</div><div class='add'>+	if (unlikely(ret &lt; 0)) {</div><div class='add'>+		macsec_txsa_put(tx_sa);</div><div class='add'>+		kfree_skb(skb);</div><div class='add'>+		return ERR_PTR(ret);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	unprotected_len = skb-&gt;len;</div><div class='hunk'>@@ -2583,6 +2571,33 @@ static bool macsec_is_configured(struct macsec_dev *macsec)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static bool macsec_needs_tx_tag(struct macsec_dev *macsec,</div><div class='add'>+				const struct macsec_ops *ops)</div><div class='add'>+{</div><div class='add'>+	return macsec-&gt;offload == MACSEC_OFFLOAD_PHY &amp;&amp;</div><div class='add'>+		ops-&gt;mdo_insert_tx_tag;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void macsec_set_head_tail_room(struct net_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct macsec_dev *macsec = macsec_priv(dev);</div><div class='add'>+	struct net_device *real_dev = macsec-&gt;real_dev;</div><div class='add'>+	int needed_headroom, needed_tailroom;</div><div class='add'>+	const struct macsec_ops *ops;</div><div class='add'>+</div><div class='add'>+	ops = macsec_get_ops(macsec, NULL);</div><div class='add'>+	if (ops) {</div><div class='add'>+		needed_headroom = ops-&gt;needed_headroom;</div><div class='add'>+		needed_tailroom = ops-&gt;needed_tailroom;</div><div class='add'>+	} else {</div><div class='add'>+		needed_headroom = MACSEC_NEEDED_HEADROOM;</div><div class='add'>+		needed_tailroom = MACSEC_NEEDED_TAILROOM;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dev-&gt;needed_headroom = real_dev-&gt;needed_headroom + needed_headroom;</div><div class='add'>+	dev-&gt;needed_tailroom = real_dev-&gt;needed_tailroom + needed_tailroom;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int macsec_update_offload(struct net_device *dev, enum macsec_offload offload)</div><div class='ctx'> {</div><div class='ctx'> 	enum macsec_offload prev_offload;</div><div class='hunk'>@@ -2620,8 +2635,13 @@ static int macsec_update_offload(struct net_device *dev, enum macsec_offload off</div><div class='ctx'> 	ctx.secy = &amp;macsec-&gt;secy;</div><div class='ctx'> 	ret = offload == MACSEC_OFFLOAD_OFF ? macsec_offload(ops-&gt;mdo_del_secy, &amp;ctx)</div><div class='ctx'> 					    : macsec_offload(ops-&gt;mdo_add_secy, &amp;ctx);</div><div class='del'>-	if (ret)</div><div class='add'>+	if (ret) {</div><div class='ctx'> 		macsec-&gt;offload = prev_offload;</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	macsec_set_head_tail_room(dev);</div><div class='add'>+	macsec-&gt;insert_tx_tag = macsec_needs_tx_tag(macsec, ops);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -3379,6 +3399,40 @@ static struct genl_family macsec_fam __ro_after_init = {</div><div class='ctx'> 	.resv_start_op	= MACSEC_CMD_UPD_OFFLOAD + 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static struct sk_buff *macsec_insert_tx_tag(struct sk_buff *skb,</div><div class='add'>+					    struct net_device *dev)</div><div class='add'>+{</div><div class='add'>+	struct macsec_dev *macsec = macsec_priv(dev);</div><div class='add'>+	const struct macsec_ops *ops;</div><div class='add'>+	struct phy_device *phydev;</div><div class='add'>+	struct macsec_context ctx;</div><div class='add'>+	int skb_final_len;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	ops = macsec_get_ops(macsec, &amp;ctx);</div><div class='add'>+	skb_final_len = skb-&gt;len - ETH_HLEN + ops-&gt;needed_headroom +</div><div class='add'>+		ops-&gt;needed_tailroom;</div><div class='add'>+	if (unlikely(skb_final_len &gt; macsec-&gt;real_dev-&gt;mtu)) {</div><div class='add'>+		err = -EINVAL;</div><div class='add'>+		goto cleanup;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	phydev = macsec-&gt;real_dev-&gt;phydev;</div><div class='add'>+</div><div class='add'>+	err = skb_ensure_writable_head_tail(skb, dev);</div><div class='add'>+	if (unlikely(err &lt; 0))</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	err = ops-&gt;mdo_insert_tx_tag(phydev, skb);</div><div class='add'>+	if (unlikely(err))</div><div class='add'>+		goto cleanup;</div><div class='add'>+</div><div class='add'>+	return skb;</div><div class='add'>+cleanup:</div><div class='add'>+	kfree_skb(skb);</div><div class='add'>+	return ERR_PTR(err);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 				     struct net_device *dev)</div><div class='ctx'> {</div><div class='hunk'>@@ -3393,6 +3447,15 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb,</div><div class='ctx'> 		skb_dst_drop(skb);</div><div class='ctx'> 		dst_hold(&amp;md_dst-&gt;dst);</div><div class='ctx'> 		skb_dst_set(skb, &amp;md_dst-&gt;dst);</div><div class='add'>+</div><div class='add'>+		if (macsec-&gt;insert_tx_tag) {</div><div class='add'>+			skb = macsec_insert_tx_tag(skb, dev);</div><div class='add'>+			if (IS_ERR(skb)) {</div><div class='add'>+				DEV_STATS_INC(dev, tx_dropped);</div><div class='add'>+				return NETDEV_TX_OK;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='ctx'> 		skb-&gt;dev = macsec-&gt;real_dev;</div><div class='ctx'> 		return dev_queue_xmit(skb);</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3454,10 +3517,7 @@ static int macsec_dev_init(struct net_device *dev)</div><div class='ctx'> 	dev-&gt;features = real_dev-&gt;features &amp; MACSEC_FEATURES;</div><div class='ctx'> 	dev-&gt;features |= NETIF_F_LLTX | NETIF_F_GSO_SOFTWARE;</div><div class='ctx'> </div><div class='del'>-	dev-&gt;needed_headroom = real_dev-&gt;needed_headroom +</div><div class='del'>-			       MACSEC_NEEDED_HEADROOM;</div><div class='del'>-	dev-&gt;needed_tailroom = real_dev-&gt;needed_tailroom +</div><div class='del'>-			       MACSEC_NEEDED_TAILROOM;</div><div class='add'>+	macsec_set_head_tail_room(dev);</div><div class='ctx'> </div><div class='ctx'> 	if (is_zero_ether_addr(dev-&gt;dev_addr))</div><div class='ctx'> 		eth_hw_addr_inherit(dev, real_dev);</div><div class='hunk'>@@ -3604,21 +3664,19 @@ static int macsec_set_mac_address(struct net_device *dev, void *p)</div><div class='ctx'> 	struct macsec_dev *macsec = macsec_priv(dev);</div><div class='ctx'> 	struct net_device *real_dev = macsec-&gt;real_dev;</div><div class='ctx'> 	struct sockaddr *addr = p;</div><div class='add'>+	u8  old_addr[ETH_ALEN];</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='ctx'> 	if (!is_valid_ether_addr(addr-&gt;sa_data))</div><div class='ctx'> 		return -EADDRNOTAVAIL;</div><div class='ctx'> </div><div class='del'>-	if (!(dev-&gt;flags &amp; IFF_UP))</div><div class='del'>-		goto out;</div><div class='del'>-</div><div class='del'>-	err = dev_uc_add(real_dev, addr-&gt;sa_data);</div><div class='del'>-	if (err &lt; 0)</div><div class='del'>-		return err;</div><div class='del'>-</div><div class='del'>-	dev_uc_del(real_dev, dev-&gt;dev_addr);</div><div class='add'>+	if (dev-&gt;flags &amp; IFF_UP) {</div><div class='add'>+		err = dev_uc_add(real_dev, addr-&gt;sa_data);</div><div class='add'>+		if (err &lt; 0)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-out:</div><div class='add'>+	ether_addr_copy(old_addr, dev-&gt;dev_addr);</div><div class='ctx'> 	eth_hw_addr_set(dev, addr-&gt;sa_data);</div><div class='ctx'> </div><div class='ctx'> 	/* If h/w offloading is available, propagate to the device */</div><div class='hunk'>@@ -3627,13 +3685,29 @@ out:</div><div class='ctx'> 		struct macsec_context ctx;</div><div class='ctx'> </div><div class='ctx'> 		ops = macsec_get_ops(macsec, &amp;ctx);</div><div class='del'>-		if (ops) {</div><div class='del'>-			ctx.secy = &amp;macsec-&gt;secy;</div><div class='del'>-			macsec_offload(ops-&gt;mdo_upd_secy, &amp;ctx);</div><div class='add'>+		if (!ops) {</div><div class='add'>+			err = -EOPNOTSUPP;</div><div class='add'>+			goto restore_old_addr;</div><div class='ctx'> 		}</div><div class='add'>+</div><div class='add'>+		ctx.secy = &amp;macsec-&gt;secy;</div><div class='add'>+		err = macsec_offload(ops-&gt;mdo_upd_secy, &amp;ctx);</div><div class='add'>+		if (err)</div><div class='add'>+			goto restore_old_addr;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (dev-&gt;flags &amp; IFF_UP)</div><div class='add'>+		dev_uc_del(real_dev, old_addr);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='add'>+</div><div class='add'>+restore_old_addr:</div><div class='add'>+	if (dev-&gt;flags &amp; IFF_UP)</div><div class='add'>+		dev_uc_del(real_dev, addr-&gt;sa_data);</div><div class='add'>+</div><div class='add'>+	eth_hw_addr_set(dev, old_addr);</div><div class='add'>+</div><div class='add'>+	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int macsec_change_mtu(struct net_device *dev, int new_mtu)</div><div class='hunk'>@@ -4126,6 +4200,9 @@ static int macsec_newlink(struct net *net, struct net_device *dev,</div><div class='ctx'> 			err = macsec_offload(ops-&gt;mdo_add_secy, &amp;ctx);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				goto del_dev;</div><div class='add'>+</div><div class='add'>+			macsec-&gt;insert_tx_tag =</div><div class='add'>+				macsec_needs_tx_tag(macsec, ops);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c<br/>index c8da94af4161..a3cc665757e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/macvlan.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/macvlan.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/macvlan.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/macvlan.c</a></div><div class='hunk'>@@ -609,6 +609,7 @@ static const struct header_ops macvlan_hard_header_ops = {</div><div class='ctx'> 	.parse		= eth_header_parse,</div><div class='ctx'> 	.cache		= eth_header_cache,</div><div class='ctx'> 	.cache_update	= eth_header_cache_update,</div><div class='add'>+	.parse_protocol	= eth_header_parse_protocol,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int macvlan_open(struct net_device *dev)</div><div class='hunk'>@@ -1086,20 +1087,8 @@ static int macvlan_ethtool_get_ts_info(struct net_device *dev,</div><div class='ctx'> 				       struct ethtool_ts_info *info)</div><div class='ctx'> {</div><div class='ctx'> 	struct net_device *real_dev = macvlan_dev_real_dev(dev);</div><div class='del'>-	const struct ethtool_ops *ops = real_dev-&gt;ethtool_ops;</div><div class='del'>-	struct phy_device *phydev = real_dev-&gt;phydev;</div><div class='ctx'> </div><div class='del'>-	if (phy_has_tsinfo(phydev)) {</div><div class='del'>-		return phy_ts_info(phydev, info);</div><div class='del'>-	} else if (ops-&gt;get_ts_info) {</div><div class='del'>-		return ops-&gt;get_ts_info(real_dev, info);</div><div class='del'>-	} else {</div><div class='del'>-		info-&gt;so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |</div><div class='del'>-			SOF_TIMESTAMPING_SOFTWARE;</div><div class='del'>-		info-&gt;phc_index = -1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return ethtool_get_ts_info_by_layer(real_dev, info);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static netdev_features_t macvlan_fix_features(struct net_device *dev,</div><div class='head'>diff --git a/drivers/net/mdio/mdio-bcm-unimac.c b/drivers/net/mdio/mdio-bcm-unimac.c<br/>index e8cd8eef319b..68f8ee0ec8ba 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-bcm-unimac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/mdio/mdio-bcm-unimac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-bcm-unimac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-bcm-unimac.c</a></div><div class='hunk'>@@ -73,24 +73,19 @@ static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)</div><div class='ctx'> 	unimac_mdio_writel(priv, reg, MDIO_CMD);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)</div><div class='del'>-{</div><div class='del'>-	return unimac_mdio_readl(priv, MDIO_CMD) &amp; MDIO_START_BUSY;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int unimac_mdio_poll(void *wait_func_data)</div><div class='ctx'> {</div><div class='ctx'> 	struct unimac_mdio_priv *priv = wait_func_data;</div><div class='del'>-	unsigned int timeout = 1000;</div><div class='add'>+	u32 val;</div><div class='ctx'> </div><div class='del'>-	do {</div><div class='del'>-		if (!unimac_mdio_busy(priv))</div><div class='del'>-			return 0;</div><div class='del'>-</div><div class='del'>-		usleep_range(1000, 2000);</div><div class='del'>-	} while (--timeout);</div><div class='add'>+	/*</div><div class='add'>+	 * C22 transactions should take ~25 usec, will need to adjust</div><div class='add'>+	 * if C45 support is added.</div><div class='add'>+	 */</div><div class='add'>+	udelay(30);</div><div class='ctx'> </div><div class='del'>-	return -ETIMEDOUT;</div><div class='add'>+	return read_poll_timeout(unimac_mdio_readl, val, !(val &amp; MDIO_START_BUSY),</div><div class='add'>+				 2000, 100000, false, priv, MDIO_CMD);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)</div><div class='head'>diff --git a/drivers/net/mdio/mdio-gpio.c b/drivers/net/mdio/mdio-gpio.c<br/>index 897b88c50bbb..778db310a28d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-gpio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/mdio/mdio-gpio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-gpio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-gpio.c</a></div><div class='hunk'>@@ -123,9 +123,9 @@ static struct mii_bus *mdio_gpio_bus_init(struct device *dev,</div><div class='ctx'> 	new_bus-&gt;parent = dev;</div><div class='ctx'> </div><div class='ctx'> 	if (bus_id != -1)</div><div class='del'>-		snprintf(new_bus-&gt;id, MII_BUS_ID_SIZE, "gpio-%x", bus_id);</div><div class='add'>+		snprintf(new_bus-&gt;id, sizeof(new_bus-&gt;id), "gpio-%x", bus_id);</div><div class='ctx'> 	else</div><div class='del'>-		strncpy(new_bus-&gt;id, "gpio", MII_BUS_ID_SIZE);</div><div class='add'>+		strscpy(new_bus-&gt;id, "gpio", sizeof(new_bus-&gt;id));</div><div class='ctx'> </div><div class='ctx'> 	if (pdata) {</div><div class='ctx'> 		new_bus-&gt;phy_mask = pdata-&gt;phy_mask;</div><div class='head'>diff --git a/drivers/net/mdio/mdio-mux-bcm-iproc.c b/drivers/net/mdio/mdio-mux-bcm-iproc.c<br/>index a750bd4c77a0..1ce7d67ba72e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-mux-bcm-iproc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/mdio/mdio-mux-bcm-iproc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-mux-bcm-iproc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-mux-bcm-iproc.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright 2016 Broadcom</div><div class='ctx'>  */</div><div class='add'>+#include &lt;linux/align.h&gt;</div><div class='ctx'> #include &lt;linux/clk.h&gt;</div><div class='ctx'> #include &lt;linux/delay.h&gt;</div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='hunk'>@@ -11,6 +12,7 @@</div><div class='ctx'> #include &lt;linux/of_mdio.h&gt;</div><div class='ctx'> #include &lt;linux/phy.h&gt;</div><div class='ctx'> #include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/sizes.h&gt;</div><div class='ctx'> </div><div class='ctx'> #define MDIO_RATE_ADJ_EXT_OFFSET	0x000</div><div class='ctx'> #define MDIO_RATE_ADJ_INT_OFFSET	0x004</div><div class='hunk'>@@ -220,12 +222,12 @@ static int mdio_mux_iproc_probe(struct platform_device *pdev)</div><div class='ctx'> 	md-&gt;base = devm_platform_get_and_ioremap_resource(pdev, 0, &amp;res);</div><div class='ctx'> 	if (IS_ERR(md-&gt;base))</div><div class='ctx'> 		return PTR_ERR(md-&gt;base);</div><div class='del'>-	if (res-&gt;start &amp; 0xfff) {</div><div class='add'>+	if (!IS_ALIGNED(res-&gt;start, SZ_4K)) {</div><div class='ctx'> 		/* For backward compatibility in case the</div><div class='ctx'> 		 * base address is specified with an offset.</div><div class='ctx'> 		 */</div><div class='ctx'> 		dev_info(&amp;pdev-&gt;dev, "fix base address in dt-blob\n");</div><div class='del'>-		res-&gt;start &amp;= ~0xfff;</div><div class='add'>+		res-&gt;start = ALIGN_DOWN(res-&gt;start, SZ_4K);</div><div class='ctx'> 		res-&gt;end = res-&gt;start + MDIO_REG_ADDR_SPACE_SIZE - 1;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/mdio/mdio-mux.c b/drivers/net/mdio/mdio-mux.c<br/>index bef4cce71287..fe0e46bd7964 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-mux.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/mdio/mdio-mux.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/mdio/mdio-mux.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/mdio/mdio-mux.c</a></div><div class='hunk'>@@ -190,8 +190,8 @@ int mdio_mux_init(struct device *dev,</div><div class='ctx'> 		r = of_property_read_u32(child_bus_node, "reg", &amp;v);</div><div class='ctx'> 		if (r) {</div><div class='ctx'> 			dev_err(dev,</div><div class='del'>-				"Error: Failed to find reg for child %pOF\n",</div><div class='del'>-				child_bus_node);</div><div class='add'>+				"Error: Failed to find reg for child %pOF: %pe\n",</div><div class='add'>+				child_bus_node, ERR_PTR(r));</div><div class='ctx'> 			continue;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='hunk'>@@ -214,8 +214,10 @@ int mdio_mux_init(struct device *dev,</div><div class='ctx'> 		snprintf(cb-&gt;mii_bus-&gt;id, MII_BUS_ID_SIZE, "%s-%x.%x",</div><div class='ctx'> 			 cb-&gt;mii_bus-&gt;name, pb-&gt;parent_id, v);</div><div class='ctx'> 		cb-&gt;mii_bus-&gt;parent = dev;</div><div class='del'>-		cb-&gt;mii_bus-&gt;read = mdio_mux_read;</div><div class='del'>-		cb-&gt;mii_bus-&gt;write = mdio_mux_write;</div><div class='add'>+		if (parent_bus-&gt;read)</div><div class='add'>+			cb-&gt;mii_bus-&gt;read = mdio_mux_read;</div><div class='add'>+		if (parent_bus-&gt;write)</div><div class='add'>+			cb-&gt;mii_bus-&gt;write = mdio_mux_write;</div><div class='ctx'> 		if (parent_bus-&gt;read_c45)</div><div class='ctx'> 			cb-&gt;mii_bus-&gt;read_c45 = mdio_mux_read_c45;</div><div class='ctx'> 		if (parent_bus-&gt;write_c45)</div><div class='hunk'>@@ -229,8 +231,8 @@ int mdio_mux_init(struct device *dev,</div><div class='ctx'> 			}</div><div class='ctx'> 			devm_kfree(dev, cb);</div><div class='ctx'> 			dev_err(dev,</div><div class='del'>-				"Error: Failed to register MDIO bus for child %pOF\n",</div><div class='del'>-				child_bus_node);</div><div class='add'>+				"Error: Failed to register MDIO bus for child %pOF: %pe\n",</div><div class='add'>+				child_bus_node, ERR_PTR(r));</div><div class='ctx'> 		} else {</div><div class='ctx'> 			cb-&gt;next = pb-&gt;children;</div><div class='ctx'> 			pb-&gt;children = cb;</div><div class='head'>diff --git a/drivers/net/netdevsim/bpf.c b/drivers/net/netdevsim/bpf.c<br/>index f60eb97e3a62..608953d4f98d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/bpf.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/netdevsim/bpf.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/bpf.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/bpf.c</a></div><div class='hunk'>@@ -93,7 +93,7 @@ static void nsim_prog_set_loaded(struct bpf_prog *prog, bool loaded)</div><div class='ctx'> {</div><div class='ctx'> 	struct nsim_bpf_bound_prog *state;</div><div class='ctx'> </div><div class='del'>-	if (!prog || !prog-&gt;aux-&gt;offload)</div><div class='add'>+	if (!prog || !bpf_prog_is_offloaded(prog-&gt;aux))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	state = prog-&gt;aux-&gt;offload-&gt;dev_priv;</div><div class='hunk'>@@ -311,7 +311,7 @@ nsim_setup_prog_hw_checks(struct netdevsim *ns, struct netdev_bpf *bpf)</div><div class='ctx'> 	if (!bpf-&gt;prog)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='del'>-	if (!bpf-&gt;prog-&gt;aux-&gt;offload) {</div><div class='add'>+	if (!bpf_prog_is_offloaded(bpf-&gt;prog-&gt;aux)) {</div><div class='ctx'> 		NSIM_EA(bpf-&gt;extack, "xdpoffload of non-bound program");</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/netdevsim/macsec.c b/drivers/net/netdevsim/macsec.c<br/>index 0d5f50430dd3..aa007b1e4b78 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/macsec.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/netdevsim/macsec.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/macsec.c</a></div><div class='hunk'>@@ -3,11 +3,6 @@</div><div class='ctx'> #include &lt;net/macsec.h&gt;</div><div class='ctx'> #include "netdevsim.h"</div><div class='ctx'> </div><div class='del'>-static inline u64 sci_to_cpu(sci_t sci)</div><div class='del'>-{</div><div class='del'>-	return be64_to_cpu((__force __be64)sci);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static int nsim_macsec_find_secy(struct netdevsim *ns, sci_t sci)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='head'>diff --git a/drivers/net/netdevsim/netdev.c b/drivers/net/netdevsim/netdev.c<br/>index aecaf5f44374..77e8250282a5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/netdev.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/netdevsim/netdev.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/netdevsim/netdev.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netdevsim/netdev.c</a></div><div class='hunk'>@@ -369,6 +369,12 @@ static int nsim_init_netdevsim_vf(struct netdevsim *ns)</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void nsim_exit_netdevsim(struct netdevsim *ns)</div><div class='add'>+{</div><div class='add'>+	nsim_udp_tunnels_info_destroy(ns-&gt;netdev);</div><div class='add'>+	mock_phc_destroy(ns-&gt;phc);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> struct netdevsim *</div><div class='ctx'> nsim_create(struct nsim_dev *nsim_dev, struct nsim_dev_port *nsim_dev_port)</div><div class='ctx'> {</div><div class='hunk'>@@ -417,8 +423,7 @@ void nsim_destroy(struct netdevsim *ns)</div><div class='ctx'> 	}</div><div class='ctx'> 	rtnl_unlock();</div><div class='ctx'> 	if (nsim_dev_port_is_pf(ns-&gt;nsim_dev_port))</div><div class='del'>-		nsim_udp_tunnels_info_destroy(dev);</div><div class='del'>-	mock_phc_destroy(ns-&gt;phc);</div><div class='add'>+		nsim_exit_netdevsim(ns);</div><div class='ctx'> 	free_netdev(dev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/netkit.c b/drivers/net/netkit.c<br/>index 97bd6705c241..39171380ccf2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/netkit.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/netkit.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/netkit.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/netkit.c</a></div><div class='hunk'>@@ -851,6 +851,12 @@ static int netkit_change_link(struct net_device *dev, struct nlattr *tb[],</div><div class='ctx'> 		return -EACCES;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (data[IFLA_NETKIT_PEER_INFO]) {</div><div class='add'>+		NL_SET_ERR_MSG_ATTR(extack, data[IFLA_NETKIT_PEER_INFO],</div><div class='add'>+				    "netkit peer info cannot be changed after device creation");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (data[IFLA_NETKIT_POLICY]) {</div><div class='ctx'> 		attr = data[IFLA_NETKIT_POLICY];</div><div class='ctx'> 		policy = nla_get_u32(attr);</div><div class='head'>diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c<br/>index 97139c07130f..d93f84fbb1fd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/pcs/pcs-rzn1-miic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/pcs/pcs-rzn1-miic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/pcs/pcs-rzn1-miic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/pcs/pcs-rzn1-miic.c</a></div><div class='hunk'>@@ -505,11 +505,9 @@ disable_runtime_pm:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int miic_remove(struct platform_device *pdev)</div><div class='add'>+static void miic_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	pm_runtime_put(&amp;pdev-&gt;dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id miic_of_mtable[] = {</div><div class='hunk'>@@ -525,7 +523,7 @@ static struct platform_driver miic_driver = {</div><div class='ctx'> 		.of_match_table = miic_of_mtable,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe = miic_probe,</div><div class='del'>-	.remove = miic_remove,</div><div class='add'>+	.remove_new = miic_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(miic_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig<br/>index 421d2b62918f..9e2672800f0b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/Kconfig</a></div><div class='hunk'>@@ -60,6 +60,14 @@ config FIXED_PHY</div><div class='ctx'> </div><div class='ctx'> 	  Currently tested with mpc866ads and mpc8349e-mitx.</div><div class='ctx'> </div><div class='add'>+config RUST_PHYLIB_ABSTRACTIONS</div><div class='add'>+        bool "Rust PHYLIB abstractions support"</div><div class='add'>+        depends on RUST</div><div class='add'>+        depends on PHYLIB=y</div><div class='add'>+        help</div><div class='add'>+          Adds support needed for PHY drivers written in Rust. It provides</div><div class='add'>+          a wrapper around the C phylib core.</div><div class='add'>+</div><div class='ctx'> config SFP</div><div class='ctx'> 	tristate "SFP cage support"</div><div class='ctx'> 	depends on I2C &amp;&amp; PHYLINK</div><div class='hunk'>@@ -96,10 +104,7 @@ config ADIN1100_PHY</div><div class='ctx'> 	  Currently supports the:</div><div class='ctx'> 	  - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY</div><div class='ctx'> </div><div class='del'>-config AQUANTIA_PHY</div><div class='del'>-	tristate "Aquantia PHYs"</div><div class='del'>-	help</div><div class='del'>-	  Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405</div><div class='add'>+source "drivers/net/phy/aquantia/Kconfig"</div><div class='ctx'> </div><div class='ctx'> config AX88796B_PHY</div><div class='ctx'> 	tristate "Asix PHYs"</div><div class='hunk'>@@ -107,6 +112,14 @@ config AX88796B_PHY</div><div class='ctx'> 	  Currently supports the Asix Electronics PHY found in the X-Surf 100</div><div class='ctx'> 	  AX88796B package.</div><div class='ctx'> </div><div class='add'>+config AX88796B_RUST_PHY</div><div class='add'>+	bool "Rust reference driver for Asix PHYs"</div><div class='add'>+	depends on RUST_PHYLIB_ABSTRACTIONS &amp;&amp; AX88796B_PHY</div><div class='add'>+	help</div><div class='add'>+	  Uses the Rust reference driver for Asix PHYs (ax88796b_rust.ko).</div><div class='add'>+	  The features are equivalent. It supports the Asix Electronics PHY</div><div class='add'>+	  found in the X-Surf 100 AX88796B package.</div><div class='add'>+</div><div class='ctx'> config BROADCOM_PHY</div><div class='ctx'> 	tristate "Broadcom 54XX PHYs"</div><div class='ctx'> 	select BCM_NET_PHYLIB</div><div class='hunk'>@@ -304,9 +317,10 @@ config NXP_CBTX_PHY</div><div class='ctx'> config NXP_C45_TJA11XX_PHY</div><div class='ctx'> 	tristate "NXP C45 TJA11XX PHYs"</div><div class='ctx'> 	depends on PTP_1588_CLOCK_OPTIONAL</div><div class='add'>+	depends on MACSEC || !MACSEC</div><div class='ctx'> 	help</div><div class='ctx'> 	  Enable support for NXP C45 TJA11XX PHYs.</div><div class='del'>-	  Currently supports the TJA1103 and TJA1120 PHYs.</div><div class='add'>+	  Currently supports the TJA1103, TJA1104 and TJA1120 PHYs.</div><div class='ctx'> </div><div class='ctx'> config NXP_TJA11XX_PHY</div><div class='ctx'> 	tristate "NXP TJA11xx PHYs support"</div><div class='hunk'>@@ -397,6 +411,19 @@ config DP83TD510_PHY</div><div class='ctx'> 	  Support for the DP83TD510 Ethernet 10Base-T1L PHY. This PHY supports</div><div class='ctx'> 	  a 10M single pair Ethernet connection for up to 1000 meter cable.</div><div class='ctx'> </div><div class='add'>+config DP83TG720_PHY</div><div class='add'>+	tristate "Texas Instruments DP83TG720 Ethernet 1000Base-T1 PHY"</div><div class='add'>+	help</div><div class='add'>+	  The DP83TG720S-Q1 is an automotive Ethernet physical layer</div><div class='add'>+	  transceiver compliant with IEEE 802.3bp and Open Alliance</div><div class='add'>+	  standards. It supports key functions necessary for</div><div class='add'>+	  transmitting and receiving data over both unshielded and</div><div class='add'>+	  shielded single twisted-pair cables. This device offers</div><div class='add'>+	  flexible xMII interface options, including support for both</div><div class='add'>+	  RGMII and SGMII MAC interfaces. It's suitable for applications</div><div class='add'>+	  requiring high-speed data transmission in automotive</div><div class='add'>+	  networking environments.</div><div class='add'>+</div><div class='ctx'> config VITESSE_PHY</div><div class='ctx'> 	tristate "Vitesse PHYs"</div><div class='ctx'> 	help</div><div class='head'>diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile<br/>index c945ed9bd14b..6097afd44392 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/Makefile</a></div><div class='hunk'>@@ -35,13 +35,13 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)</div><div class='ctx'> obj-$(CONFIG_ADIN_PHY)		+= adin.o</div><div class='ctx'> obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o</div><div class='ctx'> obj-$(CONFIG_AMD_PHY)		+= amd.o</div><div class='del'>-aquantia-objs			+= aquantia_main.o</div><div class='del'>-ifdef CONFIG_HWMON</div><div class='del'>-aquantia-objs			+= aquantia_hwmon.o</div><div class='del'>-endif</div><div class='del'>-obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o</div><div class='add'>+obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/</div><div class='ctx'> obj-$(CONFIG_AT803X_PHY)	+= at803x.o</div><div class='del'>-obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o</div><div class='add'>+ifdef CONFIG_AX88796B_RUST_PHY</div><div class='add'>+  obj-$(CONFIG_AX88796B_PHY)	+= ax88796b_rust.o</div><div class='add'>+else</div><div class='add'>+  obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o</div><div class='add'>+endif</div><div class='ctx'> obj-$(CONFIG_BCM54140_PHY)	+= bcm54140.o</div><div class='ctx'> obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o</div><div class='ctx'> obj-$(CONFIG_BCM7XXX_PHY)	+= bcm7xxx.o</div><div class='hunk'>@@ -61,6 +61,7 @@ obj-$(CONFIG_DP83867_PHY)	+= dp83867.o</div><div class='ctx'> obj-$(CONFIG_DP83869_PHY)	+= dp83869.o</div><div class='ctx'> obj-$(CONFIG_DP83TC811_PHY)	+= dp83tc811.o</div><div class='ctx'> obj-$(CONFIG_DP83TD510_PHY)	+= dp83td510.o</div><div class='add'>+obj-$(CONFIG_DP83TG720_PHY)	+= dp83tg720.o</div><div class='ctx'> obj-$(CONFIG_FIXED_PHY)		+= fixed_phy.o</div><div class='ctx'> obj-$(CONFIG_ICPLUS_PHY)	+= icplus.o</div><div class='ctx'> obj-$(CONFIG_INTEL_XWAY_PHY)	+= intel-xway.o</div><div class='hunk'>@@ -83,7 +84,11 @@ obj-$(CONFIG_MICROSEMI_PHY)	+= mscc/</div><div class='ctx'> obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm.o</div><div class='ctx'> obj-$(CONFIG_NATIONAL_PHY)	+= national.o</div><div class='ctx'> obj-$(CONFIG_NCN26000_PHY)	+= ncn26000.o</div><div class='del'>-obj-$(CONFIG_NXP_C45_TJA11XX_PHY)	+= nxp-c45-tja11xx.o</div><div class='add'>+nxp-c45-tja-objs		+= nxp-c45-tja11xx.o</div><div class='add'>+ifdef CONFIG_MACSEC</div><div class='add'>+nxp-c45-tja-objs		+= nxp-c45-tja11xx-macsec.o</div><div class='add'>+endif</div><div class='add'>+obj-$(CONFIG_NXP_C45_TJA11XX_PHY)	+= nxp-c45-tja.o</div><div class='ctx'> obj-$(CONFIG_NXP_CBTX_PHY)	+= nxp-cbtx.o</div><div class='ctx'> obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o</div><div class='ctx'> obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o</div><div class='head'>diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c<br/>index 134637584a83..2e1a46e121d9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/adin.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/adin.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/adin.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/adin.c</a></div><div class='hunk'>@@ -68,6 +68,24 @@</div><div class='ctx'> #define ADIN1300_EEE_CAP_REG			0x8000</div><div class='ctx'> #define ADIN1300_EEE_ADV_REG			0x8001</div><div class='ctx'> #define ADIN1300_EEE_LPABLE_REG			0x8002</div><div class='add'>+</div><div class='add'>+#define ADIN1300_FLD_EN_REG			0x8E27</div><div class='add'>+#define   ADIN1300_FLD_PCS_ERR_100_EN		BIT(7)</div><div class='add'>+#define   ADIN1300_FLD_PCS_ERR_1000_EN		BIT(6)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_OUT_STUCK_100_EN	BIT(5)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN	BIT(4)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_IN_ZDET_100_EN	BIT(3)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_IN_ZDET_1000_EN	BIT(2)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_IN_INVLD_100_EN	BIT(1)</div><div class='add'>+#define   ADIN1300_FLD_SLCR_IN_INVLD_1000_EN	BIT(0)</div><div class='add'>+/* These bits are the ones which are enabled by default. */</div><div class='add'>+#define ADIN1300_FLD_EN_ON	\</div><div class='add'>+	(ADIN1300_FLD_SLCR_OUT_STUCK_100_EN | \</div><div class='add'>+	 ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN | \</div><div class='add'>+	 ADIN1300_FLD_SLCR_IN_ZDET_100_EN | \</div><div class='add'>+	 ADIN1300_FLD_SLCR_IN_ZDET_1000_EN | \</div><div class='add'>+	 ADIN1300_FLD_SLCR_IN_INVLD_1000_EN)</div><div class='add'>+</div><div class='ctx'> #define ADIN1300_CLOCK_STOP_REG			0x9400</div><div class='ctx'> #define ADIN1300_LPI_WAKE_ERR_CNT_REG		0xa000</div><div class='ctx'> </div><div class='hunk'>@@ -416,6 +434,37 @@ static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)</div><div class='ctx'> 			  val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int adin_get_fast_down(struct phy_device *phydev, u8 *msecs)</div><div class='add'>+{</div><div class='add'>+	int reg;</div><div class='add'>+</div><div class='add'>+	reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);</div><div class='add'>+	if (reg &lt; 0)</div><div class='add'>+		return reg;</div><div class='add'>+</div><div class='add'>+	if (reg &amp; ADIN1300_FLD_EN_ON)</div><div class='add'>+		*msecs = ETHTOOL_PHY_FAST_LINK_DOWN_ON;</div><div class='add'>+	else</div><div class='add'>+		*msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int adin_set_fast_down(struct phy_device *phydev, const u8 *msecs)</div><div class='add'>+{</div><div class='add'>+	if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_ON)</div><div class='add'>+		return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+					ADIN1300_FLD_EN_REG,</div><div class='add'>+					ADIN1300_FLD_EN_ON);</div><div class='add'>+</div><div class='add'>+	if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)</div><div class='add'>+		return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+					  ADIN1300_FLD_EN_REG,</div><div class='add'>+					  ADIN1300_FLD_EN_ON);</div><div class='add'>+</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int adin_get_tunable(struct phy_device *phydev,</div><div class='ctx'> 			    struct ethtool_tunable *tuna, void *data)</div><div class='ctx'> {</div><div class='hunk'>@@ -424,6 +473,8 @@ static int adin_get_tunable(struct phy_device *phydev,</div><div class='ctx'> 		return adin_get_downshift(phydev, data);</div><div class='ctx'> 	case ETHTOOL_PHY_EDPD:</div><div class='ctx'> 		return adin_get_edpd(phydev, data);</div><div class='add'>+	case ETHTOOL_PHY_FAST_LINK_DOWN:</div><div class='add'>+		return adin_get_fast_down(phydev, data);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -437,6 +488,8 @@ static int adin_set_tunable(struct phy_device *phydev,</div><div class='ctx'> 		return adin_set_downshift(phydev, *(const u8 *)data);</div><div class='ctx'> 	case ETHTOOL_PHY_EDPD:</div><div class='ctx'> 		return adin_set_edpd(phydev, *(const u16 *)data);</div><div class='add'>+	case ETHTOOL_PHY_FAST_LINK_DOWN:</div><div class='add'>+		return adin_set_fast_down(phydev, data);</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/phy/aquantia.h b/drivers/net/phy/aquantia.h<br/>deleted file mode 100644<br/>index c684b65c642c..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/aquantia.h</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,16 +0,0 @@</div><div class='del'>-/* SPDX-License-Identifier: GPL-2.0 */</div><div class='del'>-/* HWMON driver for Aquantia PHY</div><div class='del'>- *</div><div class='del'>- * Author: Nikita Yushchenko &lt;nikita.yoush@cogentembedded.com&gt;</div><div class='del'>- * Author: Andrew Lunn &lt;andrew@lunn.ch&gt;</div><div class='del'>- * Author: Heiner Kallweit &lt;hkallweit1@gmail.com&gt;</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/phy.h&gt;</div><div class='del'>-</div><div class='del'>-#if IS_REACHABLE(CONFIG_HWMON)</div><div class='del'>-int aqr_hwmon_probe(struct phy_device *phydev);</div><div class='del'>-#else</div><div class='del'>-static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }</div><div class='del'>-#endif</div><div class='head'>diff --git a/drivers/net/phy/aquantia/Kconfig b/drivers/net/phy/aquantia/Kconfig<br/>new file mode 100644<br/>index 000000000000..1a65678583cf<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+config AQUANTIA_PHY</div><div class='add'>+	tristate "Aquantia PHYs"</div><div class='add'>+	select CRC_ITU_T</div><div class='add'>+	help</div><div class='add'>+	  Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405</div><div class='head'>diff --git a/drivers/net/phy/aquantia/Makefile b/drivers/net/phy/aquantia/Makefile<br/>new file mode 100644<br/>index 000000000000..aa77fb63c8ec<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/Makefile</a></div><div class='hunk'>@@ -0,0 +1,6 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+aquantia-objs			+= aquantia_main.o aquantia_firmware.o</div><div class='add'>+ifdef CONFIG_HWMON</div><div class='add'>+aquantia-objs			+= aquantia_hwmon.o</div><div class='add'>+endif</div><div class='add'>+obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o</div><div class='head'>diff --git a/drivers/net/phy/aquantia/aquantia.h b/drivers/net/phy/aquantia/aquantia.h<br/>new file mode 100644<br/>index 000000000000..1c19ae74ad2b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/aquantia.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia.h</a></div><div class='hunk'>@@ -0,0 +1,122 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* HWMON driver for Aquantia PHY</div><div class='add'>+ *</div><div class='add'>+ * Author: Nikita Yushchenko &lt;nikita.yoush@cogentembedded.com&gt;</div><div class='add'>+ * Author: Andrew Lunn &lt;andrew@lunn.ch&gt;</div><div class='add'>+ * Author: Heiner Kallweit &lt;hkallweit1@gmail.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/phy.h&gt;</div><div class='add'>+</div><div class='add'>+/* Vendor specific 1, MDIO_MMD_VEND1 */</div><div class='add'>+#define VEND1_GLOBAL_SC				0x0</div><div class='add'>+#define VEND1_GLOBAL_SC_SOFT_RESET		BIT(15)</div><div class='add'>+#define VEND1_GLOBAL_SC_LOW_POWER		BIT(11)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_FW_ID			0x0020</div><div class='add'>+#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)</div><div class='add'>+#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE1			0x0200</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE		BIT(15)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE		BIT(14)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET	BIT(12)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY		BIT(8)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE2			0x0201</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE3			0x0202</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK	GENMASK(15, 0)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) &gt;&gt; 16))</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE4			0x0203</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK	GENMASK(15, 2)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE5			0x0204</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK	GENMASK(15, 0)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) &gt;&gt; 16))</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE6			0x0205</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK	GENMASK(15, 0)</div><div class='add'>+#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))</div><div class='add'>+</div><div class='add'>+/* The following registers all have similar layouts; first the registers... */</div><div class='add'>+#define VEND1_GLOBAL_CFG_10M			0x0310</div><div class='add'>+#define VEND1_GLOBAL_CFG_100M			0x031b</div><div class='add'>+#define VEND1_GLOBAL_CFG_1G			0x031c</div><div class='add'>+#define VEND1_GLOBAL_CFG_2_5G			0x031d</div><div class='add'>+#define VEND1_GLOBAL_CFG_5G			0x031e</div><div class='add'>+#define VEND1_GLOBAL_CFG_10G			0x031f</div><div class='add'>+/* ...and now the fields */</div><div class='add'>+#define VEND1_GLOBAL_CFG_SERDES_MODE		GENMASK(2, 0)</div><div class='add'>+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI	0</div><div class='add'>+#define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII	3</div><div class='add'>+#define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII	4</div><div class='add'>+#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G	6</div><div class='add'>+#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)</div><div class='add'>+#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0</div><div class='add'>+#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1</div><div class='add'>+#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2</div><div class='add'>+</div><div class='add'>+/* Vendor specific 1, MDIO_MMD_VEND2 */</div><div class='add'>+#define VEND1_GLOBAL_CONTROL2			0xc001</div><div class='add'>+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST	BIT(15)</div><div class='add'>+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD	BIT(6)</div><div class='add'>+#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL	BIT(0)</div><div class='add'>+</div><div class='add'>+#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421</div><div class='add'>+#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422</div><div class='add'>+#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423</div><div class='add'>+#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424</div><div class='add'>+#define VEND1_THERMAL_STAT1			0xc820</div><div class='add'>+#define VEND1_THERMAL_STAT2			0xc821</div><div class='add'>+#define VEND1_THERMAL_STAT2_VALID		BIT(0)</div><div class='add'>+#define VEND1_GENERAL_STAT1			0xc830</div><div class='add'>+#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)</div><div class='add'>+#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)</div><div class='add'>+#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)</div><div class='add'>+#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_GEN_STAT2			0xc831</div><div class='add'>+#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT1			0xc885</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT9			0xc88d</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)</div><div class='add'>+#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK		0xff00</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)</div><div class='add'>+#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)</div><div class='add'>+</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK		0xff01</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)</div><div class='add'>+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)</div><div class='add'>+</div><div class='add'>+#if IS_REACHABLE(CONFIG_HWMON)</div><div class='add'>+int aqr_hwmon_probe(struct phy_device *phydev);</div><div class='add'>+#else</div><div class='add'>+static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }</div><div class='add'>+#endif</div><div class='add'>+</div><div class='add'>+int aqr_firmware_load(struct phy_device *phydev);</div><div class='head'>diff --git a/drivers/net/phy/aquantia/aquantia_firmware.c b/drivers/net/phy/aquantia/aquantia_firmware.c<br/>new file mode 100644<br/>index 000000000000..0c9640ef153b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/aquantia_firmware.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_firmware.c</a></div><div class='hunk'>@@ -0,0 +1,374 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/firmware.h&gt;</div><div class='add'>+#include &lt;linux/crc-itu-t.h&gt;</div><div class='add'>+#include &lt;linux/nvmem-consumer.h&gt;</div><div class='add'>+</div><div class='add'>+#include &lt;asm/unaligned.h&gt;</div><div class='add'>+</div><div class='add'>+#include "aquantia.h"</div><div class='add'>+</div><div class='add'>+#define UP_RESET_SLEEP		100</div><div class='add'>+</div><div class='add'>+/* addresses of memory segments in the phy */</div><div class='add'>+#define DRAM_BASE_ADDR		0x3FFE0000</div><div class='add'>+#define IRAM_BASE_ADDR		0x40000000</div><div class='add'>+</div><div class='add'>+/* firmware image format constants */</div><div class='add'>+#define VERSION_STRING_SIZE		0x40</div><div class='add'>+#define VERSION_STRING_OFFSET		0x0200</div><div class='add'>+/* primary offset is written at an offset from the start of the fw blob */</div><div class='add'>+#define PRIMARY_OFFSET_OFFSET		0x8</div><div class='add'>+/* primary offset needs to be then added to a base offset */</div><div class='add'>+#define PRIMARY_OFFSET_SHIFT		12</div><div class='add'>+#define PRIMARY_OFFSET(x)		((x) &lt;&lt; PRIMARY_OFFSET_SHIFT)</div><div class='add'>+#define HEADER_OFFSET			0x300</div><div class='add'>+</div><div class='add'>+struct aqr_fw_header {</div><div class='add'>+	u32 padding;</div><div class='add'>+	u8 iram_offset[3];</div><div class='add'>+	u8 iram_size[3];</div><div class='add'>+	u8 dram_offset[3];</div><div class='add'>+	u8 dram_size[3];</div><div class='add'>+} __packed;</div><div class='add'>+</div><div class='add'>+enum aqr_fw_src {</div><div class='add'>+	AQR_FW_SRC_NVMEM = 0,</div><div class='add'>+	AQR_FW_SRC_FS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const char * const aqr_fw_src_string[] = {</div><div class='add'>+	[AQR_FW_SRC_NVMEM] = "NVMEM",</div><div class='add'>+	[AQR_FW_SRC_FS] = "FS",</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+/* AQR firmware doesn't have fixed offsets for iram and dram section</div><div class='add'>+ * but instead provide an header with the offset to use on reading</div><div class='add'>+ * and parsing the firmware.</div><div class='add'>+ *</div><div class='add'>+ * AQR firmware can't be trusted and each offset is validated to be</div><div class='add'>+ * not negative and be in the size of the firmware itself.</div><div class='add'>+ */</div><div class='add'>+static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)</div><div class='add'>+{</div><div class='add'>+	return offset + get_size &lt;= size;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)</div><div class='add'>+{</div><div class='add'>+	if (!aqr_fw_validate_get(size, offset, sizeof(u16)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*value = get_unaligned_be16(data + offset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)</div><div class='add'>+{</div><div class='add'>+	if (!aqr_fw_validate_get(size, offset, sizeof(u16)))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*value = get_unaligned_le16(data + offset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)</div><div class='add'>+{</div><div class='add'>+	if (!aqr_fw_validate_get(size, offset, sizeof(u8) * 3))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	*value = get_unaligned_le24(data + offset);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* load data into the phy's memory */</div><div class='add'>+static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,</div><div class='add'>+			      const u8 *data, size_t len)</div><div class='add'>+{</div><div class='add'>+	u16 crc = 0, up_crc;</div><div class='add'>+	size_t pos;</div><div class='add'>+</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE1,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE3,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(addr));</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE4,</div><div class='add'>+		      VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(addr));</div><div class='add'>+</div><div class='add'>+	/* We assume and enforce the size to be word aligned.</div><div class='add'>+	 * If a firmware that is not word aligned is found, please report upstream.</div><div class='add'>+	 */</div><div class='add'>+	for (pos = 0; pos &lt; len; pos += sizeof(u32)) {</div><div class='add'>+		u8 crc_data[4];</div><div class='add'>+		u32 word;</div><div class='add'>+</div><div class='add'>+		/* FW data is always stored in little-endian */</div><div class='add'>+		word = get_unaligned_le32((const u32 *)(data + pos));</div><div class='add'>+</div><div class='add'>+		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,</div><div class='add'>+			      VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));</div><div class='add'>+		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,</div><div class='add'>+			      VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(word));</div><div class='add'>+</div><div class='add'>+		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,</div><div class='add'>+			      VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |</div><div class='add'>+			      VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);</div><div class='add'>+</div><div class='add'>+		/* Word is swapped internally and MAILBOX CRC is calculated</div><div class='add'>+		 * using big-endian order. Mimic what the PHY does to have a</div><div class='add'>+		 * matching CRC...</div><div class='add'>+		 */</div><div class='add'>+		crc_data[0] = word &gt;&gt; 24;</div><div class='add'>+		crc_data[1] = word &gt;&gt; 16;</div><div class='add'>+		crc_data[2] = word &gt;&gt; 8;</div><div class='add'>+		crc_data[3] = word;</div><div class='add'>+</div><div class='add'>+		/* ...calculate CRC as we load data... */</div><div class='add'>+		crc = crc_itu_t(crc, crc_data, sizeof(crc_data));</div><div class='add'>+	}</div><div class='add'>+	/* ...gets CRC from MAILBOX after we have loaded the entire section... */</div><div class='add'>+	up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);</div><div class='add'>+	/* ...and make sure it does match our calculated CRC */</div><div class='add'>+	if (crc != up_crc) {</div><div class='add'>+		phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",</div><div class='add'>+			   crc, up_crc);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,</div><div class='add'>+		       enum aqr_fw_src fw_src)</div><div class='add'>+{</div><div class='add'>+	u16 calculated_crc, read_crc, read_primary_offset;</div><div class='add'>+	u32 iram_offset = 0, iram_size = 0;</div><div class='add'>+	u32 dram_offset = 0, dram_size = 0;</div><div class='add'>+	char version[VERSION_STRING_SIZE];</div><div class='add'>+	u32 primary_offset = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* extract saved CRC at the end of the fw</div><div class='add'>+	 * CRC is saved in big-endian as PHY is BE</div><div class='add'>+	 */</div><div class='add'>+	ret = aqr_fw_get_be16(data, size - sizeof(u16), size, &amp;read_crc);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "bad firmware CRC in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	calculated_crc = crc_itu_t(0, data, size - sizeof(u16));</div><div class='add'>+	if (read_crc != calculated_crc) {</div><div class='add'>+		phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",</div><div class='add'>+			   read_crc, calculated_crc);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Get the primary offset to extract DRAM and IRAM sections. */</div><div class='add'>+	ret = aqr_fw_get_le16(data, PRIMARY_OFFSET_OFFSET, size, &amp;read_primary_offset);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "bad primary offset in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	primary_offset = PRIMARY_OFFSET(read_primary_offset);</div><div class='add'>+</div><div class='add'>+	/* Find the DRAM and IRAM sections within the firmware file.</div><div class='add'>+	 * Make sure the fw_header is correctly in the firmware.</div><div class='add'>+	 */</div><div class='add'>+	if (!aqr_fw_validate_get(size, primary_offset + HEADER_OFFSET,</div><div class='add'>+				 sizeof(struct aqr_fw_header))) {</div><div class='add'>+		phydev_err(phydev, "bad fw_header in firmware\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* offset are in LE and values needs to be converted to cpu endian */</div><div class='add'>+	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +</div><div class='add'>+			      offsetof(struct aqr_fw_header, iram_offset),</div><div class='add'>+			      size, &amp;iram_offset);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "bad iram offset in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +</div><div class='add'>+			      offsetof(struct aqr_fw_header, iram_size),</div><div class='add'>+			      size, &amp;iram_size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "invalid iram size in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +</div><div class='add'>+			      offsetof(struct aqr_fw_header, dram_offset),</div><div class='add'>+			      size, &amp;dram_offset);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "bad dram offset in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +</div><div class='add'>+			      offsetof(struct aqr_fw_header, dram_size),</div><div class='add'>+			      size, &amp;dram_size);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "invalid dram size in firmware\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Increment the offset with the primary offset.</div><div class='add'>+	 * Validate iram/dram offset and size.</div><div class='add'>+	 */</div><div class='add'>+	iram_offset += primary_offset;</div><div class='add'>+	if (iram_size % sizeof(u32)) {</div><div class='add'>+		phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	if (!aqr_fw_validate_get(size, iram_offset, iram_size)) {</div><div class='add'>+		phydev_err(phydev, "invalid iram offset for iram size\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	dram_offset += primary_offset;</div><div class='add'>+	if (dram_size % sizeof(u32)) {</div><div class='add'>+		phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	if (!aqr_fw_validate_get(size, dram_offset, dram_size)) {</div><div class='add'>+		phydev_err(phydev, "invalid iram offset for iram size\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",</div><div class='add'>+		   primary_offset, iram_offset, iram_size, dram_offset, dram_size);</div><div class='add'>+</div><div class='add'>+	if (!aqr_fw_validate_get(size, dram_offset + VERSION_STRING_OFFSET,</div><div class='add'>+				 VERSION_STRING_SIZE)) {</div><div class='add'>+		phydev_err(phydev, "invalid version in firmware\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	strscpy(version, (char *)data + dram_offset + VERSION_STRING_OFFSET,</div><div class='add'>+		VERSION_STRING_SIZE);</div><div class='add'>+	if (version[0] == '\0') {</div><div class='add'>+		phydev_err(phydev, "invalid version in firmware\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	phydev_info(phydev, "loading firmware version '%s' from '%s'\n", version,</div><div class='add'>+		    aqr_fw_src_string[fw_src]);</div><div class='add'>+</div><div class='add'>+	/* stall the microcprocessor */</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,</div><div class='add'>+		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL | VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",</div><div class='add'>+		   DRAM_BASE_ADDR, dram_offset, dram_size);</div><div class='add'>+	ret = aqr_fw_load_memory(phydev, DRAM_BASE_ADDR, data + dram_offset,</div><div class='add'>+				 dram_size);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",</div><div class='add'>+		   IRAM_BASE_ADDR, iram_offset, iram_size);</div><div class='add'>+	ret = aqr_fw_load_memory(phydev, IRAM_BASE_ADDR, data + iram_offset,</div><div class='add'>+				 iram_size);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* make sure soft reset and low power mode are clear */</div><div class='add'>+	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,</div><div class='add'>+			   VEND1_GLOBAL_SC_SOFT_RESET | VEND1_GLOBAL_SC_LOW_POWER);</div><div class='add'>+</div><div class='add'>+	/* Release the microprocessor. UP_RESET must be held for 100 usec. */</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,</div><div class='add'>+		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL |</div><div class='add'>+		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD |</div><div class='add'>+		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST);</div><div class='add'>+	usleep_range(UP_RESET_SLEEP, UP_RESET_SLEEP * 2);</div><div class='add'>+</div><div class='add'>+	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,</div><div class='add'>+		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_firmware_load_nvmem(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct nvmem_cell *cell;</div><div class='add'>+	size_t size;</div><div class='add'>+	u8 *buf;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	cell = nvmem_cell_get(&amp;phydev-&gt;mdio.dev, "firmware");</div><div class='add'>+	if (IS_ERR(cell))</div><div class='add'>+		return PTR_ERR(cell);</div><div class='add'>+</div><div class='add'>+	buf = nvmem_cell_read(cell, &amp;size);</div><div class='add'>+	if (IS_ERR(buf)) {</div><div class='add'>+		ret = PTR_ERR(buf);</div><div class='add'>+		goto exit;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = aqr_fw_boot(phydev, buf, size, AQR_FW_SRC_NVMEM);</div><div class='add'>+	if (ret)</div><div class='add'>+		phydev_err(phydev, "firmware loading failed: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	kfree(buf);</div><div class='add'>+exit:</div><div class='add'>+	nvmem_cell_put(cell);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr_firmware_load_fs(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct device *dev = &amp;phydev-&gt;mdio.dev;</div><div class='add'>+	const struct firmware *fw;</div><div class='add'>+	const char *fw_name;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = of_property_read_string(dev-&gt;of_node, "firmware-name",</div><div class='add'>+				      &amp;fw_name);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = request_firmware(&amp;fw, fw_name, dev);</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "failed to find FW file %s (%d)\n",</div><div class='add'>+			   fw_name, ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = aqr_fw_boot(phydev, fw-&gt;data, fw-&gt;size, AQR_FW_SRC_FS);</div><div class='add'>+	if (ret)</div><div class='add'>+		phydev_err(phydev, "firmware loading failed: %d\n", ret);</div><div class='add'>+</div><div class='add'>+	release_firmware(fw);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int aqr_firmware_load(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Check if the firmware is not already loaded by pooling</div><div class='add'>+	 * the current version returned by the PHY. If 0 is returned,</div><div class='add'>+	 * no firmware is loaded.</div><div class='add'>+	 */</div><div class='add'>+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);</div><div class='add'>+	if (ret &gt; 0)</div><div class='add'>+		goto exit;</div><div class='add'>+</div><div class='add'>+	ret = aqr_firmware_load_nvmem(phydev);</div><div class='add'>+	if (!ret)</div><div class='add'>+		goto exit;</div><div class='add'>+</div><div class='add'>+	ret = aqr_firmware_load_fs(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+exit:</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/phy/aquantia_hwmon.c b/drivers/net/phy/aquantia/aquantia_hwmon.c<br/>index 0da451e46f69..7b3c49c3bf49 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia_hwmon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/aquantia_hwmon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/aquantia_hwmon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_hwmon.c</a></div><div class='hunk'>@@ -13,20 +13,6 @@</div><div class='ctx'> </div><div class='ctx'> #include "aquantia.h"</div><div class='ctx'> </div><div class='del'>-/* Vendor specific 1, MDIO_MMD_VEND2 */</div><div class='del'>-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421</div><div class='del'>-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422</div><div class='del'>-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423</div><div class='del'>-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424</div><div class='del'>-#define VEND1_THERMAL_STAT1			0xc820</div><div class='del'>-#define VEND1_THERMAL_STAT2			0xc821</div><div class='del'>-#define VEND1_THERMAL_STAT2_VALID		BIT(0)</div><div class='del'>-#define VEND1_GENERAL_STAT1			0xc830</div><div class='del'>-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)</div><div class='del'>-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)</div><div class='del'>-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)</div><div class='del'>-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)</div><div class='del'>-</div><div class='ctx'> #if IS_REACHABLE(CONFIG_HWMON)</div><div class='ctx'> </div><div class='ctx'> static umode_t aqr_hwmon_is_visible(const void *data,</div><div class='head'>diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c<br/>index 334a6904ca5a..97a2fafa15ca 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/aquantia_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/aquantia/aquantia_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/aquantia/aquantia_main.c</a></div><div class='hunk'>@@ -91,61 +91,6 @@</div><div class='ctx'> #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a</div><div class='ctx'> #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b</div><div class='ctx'> </div><div class='del'>-/* Vendor specific 1, MDIO_MMD_VEND1 */</div><div class='del'>-#define VEND1_GLOBAL_FW_ID			0x0020</div><div class='del'>-#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)</div><div class='del'>-#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_GEN_STAT2			0xc831</div><div class='del'>-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)</div><div class='del'>-</div><div class='del'>-/* The following registers all have similar layouts; first the registers... */</div><div class='del'>-#define VEND1_GLOBAL_CFG_10M			0x0310</div><div class='del'>-#define VEND1_GLOBAL_CFG_100M			0x031b</div><div class='del'>-#define VEND1_GLOBAL_CFG_1G			0x031c</div><div class='del'>-#define VEND1_GLOBAL_CFG_2_5G			0x031d</div><div class='del'>-#define VEND1_GLOBAL_CFG_5G			0x031e</div><div class='del'>-#define VEND1_GLOBAL_CFG_10G			0x031f</div><div class='del'>-/* ...and now the fields */</div><div class='del'>-#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)</div><div class='del'>-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0</div><div class='del'>-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1</div><div class='del'>-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT1			0xc885</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT9			0xc88d</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)</div><div class='del'>-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK		0xff00</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)</div><div class='del'>-#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)</div><div class='del'>-</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK		0xff01</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)</div><div class='del'>-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)</div><div class='del'>-</div><div class='ctx'> /* Sleep and timeout for checking if the Processor-Intensive</div><div class='ctx'>  * MDIO operation is finished</div><div class='ctx'>  */</div><div class='hunk'>@@ -711,13 +656,93 @@ static int aqr107_resume(struct phy_device *phydev)</div><div class='ctx'> 	return aqr107_wait_processor_intensive_op(phydev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const u16 aqr_global_cfg_regs[] = {</div><div class='add'>+	VEND1_GLOBAL_CFG_10M,</div><div class='add'>+	VEND1_GLOBAL_CFG_100M,</div><div class='add'>+	VEND1_GLOBAL_CFG_1G,</div><div class='add'>+	VEND1_GLOBAL_CFG_2_5G,</div><div class='add'>+	VEND1_GLOBAL_CFG_5G,</div><div class='add'>+	VEND1_GLOBAL_CFG_10G</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int aqr107_fill_interface_modes(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	unsigned long *possible = phydev-&gt;possible_interfaces;</div><div class='add'>+	unsigned int serdes_mode, rate_adapt;</div><div class='add'>+	phy_interface_t interface;</div><div class='add'>+	int i, val;</div><div class='add'>+</div><div class='add'>+	/* Walk the media-speed configuration registers to determine which</div><div class='add'>+	 * host-side serdes modes may be used by the PHY depending on the</div><div class='add'>+	 * negotiated media speed.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(aqr_global_cfg_regs); i++) {</div><div class='add'>+		val = phy_read_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+				   aqr_global_cfg_regs[i]);</div><div class='add'>+		if (val &lt; 0)</div><div class='add'>+			return val;</div><div class='add'>+</div><div class='add'>+		serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);</div><div class='add'>+		rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);</div><div class='add'>+</div><div class='add'>+		switch (serdes_mode) {</div><div class='add'>+		case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:</div><div class='add'>+			if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)</div><div class='add'>+				interface = PHY_INTERFACE_MODE_USXGMII;</div><div class='add'>+			else</div><div class='add'>+				interface = PHY_INTERFACE_MODE_10GBASER;</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:</div><div class='add'>+			interface = PHY_INTERFACE_MODE_5GBASER;</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:</div><div class='add'>+			interface = PHY_INTERFACE_MODE_2500BASEX;</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:</div><div class='add'>+			interface = PHY_INTERFACE_MODE_SGMII;</div><div class='add'>+			break;</div><div class='add'>+</div><div class='add'>+		default:</div><div class='add'>+			phydev_warn(phydev, "unrecognised serdes mode %u\n",</div><div class='add'>+				    serdes_mode);</div><div class='add'>+			interface = PHY_INTERFACE_MODE_NA;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (interface != PHY_INTERFACE_MODE_NA)</div><div class='add'>+			__set_bit(interface, possible);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int aqr113c_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = aqr107_config_init(phydev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return aqr107_fill_interface_modes(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int aqr107_probe(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='ctx'> 	phydev-&gt;priv = devm_kzalloc(&amp;phydev-&gt;mdio.dev,</div><div class='ctx'> 				    sizeof(struct aqr107_priv), GFP_KERNEL);</div><div class='ctx'> 	if (!phydev-&gt;priv)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='add'>+	ret = aqr_firmware_load(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='ctx'> 	return aqr_hwmon_probe(phydev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -843,7 +868,7 @@ static struct phy_driver aqr_driver[] = {</div><div class='ctx'> 	.name           = "Aquantia AQR113C",</div><div class='ctx'> 	.probe          = aqr107_probe,</div><div class='ctx'> 	.get_rate_matching = aqr107_get_rate_matching,</div><div class='del'>-	.config_init    = aqr107_config_init,</div><div class='add'>+	.config_init    = aqr113c_config_init,</div><div class='ctx'> 	.config_aneg    = aqr_config_aneg,</div><div class='ctx'> 	.config_intr    = aqr_config_intr,</div><div class='ctx'> 	.handle_interrupt       = aqr_handle_interrupt,</div><div class='head'>diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c<br/>index 37fb033e1c29..a62442a55774 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/at803x.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/at803x.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/at803x.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/at803x.c</a></div><div class='hunk'>@@ -254,6 +254,7 @@</div><div class='ctx'> </div><div class='ctx'> #define QCA808X_CDT_ENABLE_TEST			BIT(15)</div><div class='ctx'> #define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)</div><div class='add'>+#define QCA808X_CDT_STATUS			BIT(11)</div><div class='ctx'> #define QCA808X_CDT_LENGTH_UNIT			BIT(10)</div><div class='ctx'> </div><div class='ctx'> #define QCA808X_MMD3_CDT_STATUS			0x8064</div><div class='hunk'>@@ -261,16 +262,44 @@</div><div class='ctx'> #define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066</div><div class='ctx'> #define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067</div><div class='ctx'> #define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068</div><div class='del'>-#define QCA808X_CDT_DIAG_LENGTH			GENMASK(7, 0)</div><div class='add'>+#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)</div><div class='add'>+#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)</div><div class='ctx'> </div><div class='ctx'> #define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)</div><div class='ctx'> #define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)</div><div class='ctx'> #define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)</div><div class='ctx'> #define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)</div><div class='del'>-#define QCA808X_CDT_STATUS_STAT_FAIL		0</div><div class='del'>-#define QCA808X_CDT_STATUS_STAT_NORMAL		1</div><div class='del'>-#define QCA808X_CDT_STATUS_STAT_OPEN		2</div><div class='del'>-#define QCA808X_CDT_STATUS_STAT_SHORT		3</div><div class='add'>+</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)</div><div class='add'>+</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)</div><div class='add'>+</div><div class='add'>+/* NORMAL are MDI with type set to 0 */</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI1)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI1)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI2)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI2)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI3)</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\</div><div class='add'>+									 QCA808X_CDT_STATUS_STAT_MDI3)</div><div class='add'>+</div><div class='add'>+/* Added for reference of existence but should be handled by wait_for_completion already */</div><div class='add'>+#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))</div><div class='ctx'> </div><div class='ctx'> /* QCA808X 1G chip type */</div><div class='ctx'> #define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d</div><div class='hunk'>@@ -295,12 +324,17 @@ struct at803x_hw_stat {</div><div class='ctx'> 	enum stat_access_type access_type;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static struct at803x_hw_stat at803x_hw_stats[] = {</div><div class='add'>+static struct at803x_hw_stat qca83xx_hw_stats[] = {</div><div class='ctx'> 	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},</div><div class='ctx'> 	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},</div><div class='ctx'> 	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct at803x_ss_mask {</div><div class='add'>+	u16 speed_mask;</div><div class='add'>+	u8 speed_shift;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct at803x_priv {</div><div class='ctx'> 	int flags;</div><div class='ctx'> 	u16 clk_25m_reg;</div><div class='hunk'>@@ -311,7 +345,7 @@ struct at803x_priv {</div><div class='ctx'> 	bool is_1000basex;</div><div class='ctx'> 	struct regulator_dev *vddio_rdev;</div><div class='ctx'> 	struct regulator_dev *vddh_rdev;</div><div class='del'>-	u64 stats[ARRAY_SIZE(at803x_hw_stats)];</div><div class='add'>+	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct at803x_context {</div><div class='hunk'>@@ -457,7 +491,7 @@ static int at803x_set_wol(struct phy_device *phydev,</div><div class='ctx'> 		if (!ndev)</div><div class='ctx'> 			return -ENODEV;</div><div class='ctx'> </div><div class='del'>-		mac = (const u8 *) ndev-&gt;dev_addr;</div><div class='add'>+		mac = (const u8 *)ndev-&gt;dev_addr;</div><div class='ctx'> </div><div class='ctx'> 		if (!is_valid_ether_addr(mac))</div><div class='ctx'> 			return -EINVAL;</div><div class='hunk'>@@ -466,27 +500,11 @@ static int at803x_set_wol(struct phy_device *phydev,</div><div class='ctx'> 			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],</div><div class='ctx'> 				      mac[(i * 2) + 1] | (mac[(i * 2)] &lt;&lt; 8));</div><div class='ctx'> </div><div class='del'>-		/* Enable WOL function for 1588 */</div><div class='del'>-		if (phydev-&gt;drv-&gt;phy_id == ATH8031_PHY_ID) {</div><div class='del'>-			ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='del'>-					     AT803X_PHY_MMD3_WOL_CTRL,</div><div class='del'>-					     0, AT803X_WOL_EN);</div><div class='del'>-			if (ret)</div><div class='del'>-				return ret;</div><div class='del'>-		}</div><div class='ctx'> 		/* Enable WOL interrupt */</div><div class='ctx'> 		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);</div><div class='ctx'> 		if (ret)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	} else {</div><div class='del'>-		/* Disable WoL function for 1588 */</div><div class='del'>-		if (phydev-&gt;drv-&gt;phy_id == ATH8031_PHY_ID) {</div><div class='del'>-			ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='del'>-					     AT803X_PHY_MMD3_WOL_CTRL,</div><div class='del'>-					     AT803X_WOL_EN, 0);</div><div class='del'>-			if (ret)</div><div class='del'>-				return ret;</div><div class='del'>-		}</div><div class='ctx'> 		/* Disable WOL interrupt */</div><div class='ctx'> 		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);</div><div class='ctx'> 		if (ret)</div><div class='hunk'>@@ -529,24 +547,24 @@ static void at803x_get_wol(struct phy_device *phydev,</div><div class='ctx'> 		wol-&gt;wolopts |= WAKE_MAGIC;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_get_sset_count(struct phy_device *phydev)</div><div class='add'>+static int qca83xx_get_sset_count(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	return ARRAY_SIZE(at803x_hw_stats);</div><div class='add'>+	return ARRAY_SIZE(qca83xx_hw_stats);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void at803x_get_strings(struct phy_device *phydev, u8 *data)</div><div class='add'>+static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(at803x_hw_stats); i++) {</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(qca83xx_hw_stats); i++) {</div><div class='ctx'> 		strscpy(data + i * ETH_GSTRING_LEN,</div><div class='del'>-			at803x_hw_stats[i].string, ETH_GSTRING_LEN);</div><div class='add'>+			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static u64 at803x_get_stat(struct phy_device *phydev, int i)</div><div class='add'>+static u64 qca83xx_get_stat(struct phy_device *phydev, int i)</div><div class='ctx'> {</div><div class='del'>-	struct at803x_hw_stat stat = at803x_hw_stats[i];</div><div class='add'>+	struct at803x_hw_stat stat = qca83xx_hw_stats[i];</div><div class='ctx'> 	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='ctx'> 	int val;</div><div class='ctx'> 	u64 ret;</div><div class='hunk'>@@ -567,13 +585,13 @@ static u64 at803x_get_stat(struct phy_device *phydev, int i)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void at803x_get_stats(struct phy_device *phydev,</div><div class='del'>-			     struct ethtool_stats *stats, u64 *data)</div><div class='add'>+static void qca83xx_get_stats(struct phy_device *phydev,</div><div class='add'>+			      struct ethtool_stats *stats, u64 *data)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(at803x_hw_stats); i++)</div><div class='del'>-		data[i] = at803x_get_stat(phydev, i);</div><div class='add'>+	for (i = 0; i &lt; ARRAY_SIZE(qca83xx_hw_stats); i++)</div><div class='add'>+		data[i] = qca83xx_get_stat(phydev, i);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int at803x_suspend(struct phy_device *phydev)</div><div class='hunk'>@@ -599,139 +617,6 @@ static int at803x_resume(struct phy_device *phydev)</div><div class='ctx'> 	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,</div><div class='del'>-					    unsigned int selector)</div><div class='del'>-{</div><div class='del'>-	struct phy_device *phydev = rdev_get_drvdata(rdev);</div><div class='del'>-</div><div class='del'>-	if (selector)</div><div class='del'>-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,</div><div class='del'>-					     0, AT803X_DEBUG_RGMII_1V8);</div><div class='del'>-	else</div><div class='del'>-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,</div><div class='del'>-					     AT803X_DEBUG_RGMII_1V8, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)</div><div class='del'>-{</div><div class='del'>-	struct phy_device *phydev = rdev_get_drvdata(rdev);</div><div class='del'>-	int val;</div><div class='del'>-</div><div class='del'>-	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);</div><div class='del'>-	if (val &lt; 0)</div><div class='del'>-		return val;</div><div class='del'>-</div><div class='del'>-	return (val &amp; AT803X_DEBUG_RGMII_1V8) ? 1 : 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct regulator_ops vddio_regulator_ops = {</div><div class='del'>-	.list_voltage = regulator_list_voltage_table,</div><div class='del'>-	.set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,</div><div class='del'>-	.get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const unsigned int vddio_voltage_table[] = {</div><div class='del'>-	1500000,</div><div class='del'>-	1800000,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct regulator_desc vddio_desc = {</div><div class='del'>-	.name = "vddio",</div><div class='del'>-	.of_match = of_match_ptr("vddio-regulator"),</div><div class='del'>-	.n_voltages = ARRAY_SIZE(vddio_voltage_table),</div><div class='del'>-	.volt_table = vddio_voltage_table,</div><div class='del'>-	.ops = &amp;vddio_regulator_ops,</div><div class='del'>-	.type = REGULATOR_VOLTAGE,</div><div class='del'>-	.owner = THIS_MODULE,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct regulator_ops vddh_regulator_ops = {</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct regulator_desc vddh_desc = {</div><div class='del'>-	.name = "vddh",</div><div class='del'>-	.of_match = of_match_ptr("vddh-regulator"),</div><div class='del'>-	.n_voltages = 1,</div><div class='del'>-	.fixed_uV = 2500000,</div><div class='del'>-	.ops = &amp;vddh_regulator_ops,</div><div class='del'>-	.type = REGULATOR_VOLTAGE,</div><div class='del'>-	.owner = THIS_MODULE,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int at8031_register_regulators(struct phy_device *phydev)</div><div class='del'>-{</div><div class='del'>-	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='del'>-	struct device *dev = &amp;phydev-&gt;mdio.dev;</div><div class='del'>-	struct regulator_config config = { };</div><div class='del'>-</div><div class='del'>-	config.dev = dev;</div><div class='del'>-	config.driver_data = phydev;</div><div class='del'>-</div><div class='del'>-	priv-&gt;vddio_rdev = devm_regulator_register(dev, &amp;vddio_desc, &amp;config);</div><div class='del'>-	if (IS_ERR(priv-&gt;vddio_rdev)) {</div><div class='del'>-		phydev_err(phydev, "failed to register VDDIO regulator\n");</div><div class='del'>-		return PTR_ERR(priv-&gt;vddio_rdev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	priv-&gt;vddh_rdev = devm_regulator_register(dev, &amp;vddh_desc, &amp;config);</div><div class='del'>-	if (IS_ERR(priv-&gt;vddh_rdev)) {</div><div class='del'>-		phydev_err(phydev, "failed to register VDDH regulator\n");</div><div class='del'>-		return PTR_ERR(priv-&gt;vddh_rdev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)</div><div class='del'>-{</div><div class='del'>-	struct phy_device *phydev = upstream;</div><div class='del'>-	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);</div><div class='del'>-	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);</div><div class='del'>-	DECLARE_PHY_INTERFACE_MASK(interfaces);</div><div class='del'>-	phy_interface_t iface;</div><div class='del'>-</div><div class='del'>-	linkmode_zero(phy_support);</div><div class='del'>-	phylink_set(phy_support, 1000baseX_Full);</div><div class='del'>-	phylink_set(phy_support, 1000baseT_Full);</div><div class='del'>-	phylink_set(phy_support, Autoneg);</div><div class='del'>-	phylink_set(phy_support, Pause);</div><div class='del'>-	phylink_set(phy_support, Asym_Pause);</div><div class='del'>-</div><div class='del'>-	linkmode_zero(sfp_support);</div><div class='del'>-	sfp_parse_support(phydev-&gt;sfp_bus, id, sfp_support, interfaces);</div><div class='del'>-	/* Some modules support 10G modes as well as others we support.</div><div class='del'>-	 * Mask out non-supported modes so the correct interface is picked.</div><div class='del'>-	 */</div><div class='del'>-	linkmode_and(sfp_support, phy_support, sfp_support);</div><div class='del'>-</div><div class='del'>-	if (linkmode_empty(sfp_support)) {</div><div class='del'>-		dev_err(&amp;phydev-&gt;mdio.dev, "incompatible SFP module inserted\n");</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	iface = sfp_select_interface(phydev-&gt;sfp_bus, sfp_support);</div><div class='del'>-</div><div class='del'>-	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes</div><div class='del'>-	 * interface for use with SFP modules.</div><div class='del'>-	 * However, some copper modules detected as having a preferred SGMII</div><div class='del'>-	 * interface do default to and function in 1000Base-X mode, so just</div><div class='del'>-	 * print a warning and allow such modules, as they may have some chance</div><div class='del'>-	 * of working.</div><div class='del'>-	 */</div><div class='del'>-	if (iface == PHY_INTERFACE_MODE_SGMII)</div><div class='del'>-		dev_warn(&amp;phydev-&gt;mdio.dev, "module may not function if 1000Base-X not supported\n");</div><div class='del'>-	else if (iface != PHY_INTERFACE_MODE_1000BASEX)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct sfp_upstream_ops at803x_sfp_ops = {</div><div class='del'>-	.attach = phy_sfp_attach,</div><div class='del'>-	.detach = phy_sfp_detach,</div><div class='del'>-	.module_insert = at803x_sfp_insert,</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static int at803x_parse_dt(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	struct device_node *node = phydev-&gt;mdio.dev.of_node;</div><div class='hunk'>@@ -787,23 +672,6 @@ static int at803x_parse_dt(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 		priv-&gt;clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);</div><div class='ctx'> 		priv-&gt;clk_25m_mask |= AT803X_CLK_OUT_MASK;</div><div class='del'>-</div><div class='del'>-		/* Fixup for the AR8030/AR8035. This chip has another mask and</div><div class='del'>-		 * doesn't support the DSP reference. Eg. the lowest bit of the</div><div class='del'>-		 * mask. The upper two bits select the same frequencies. Mask</div><div class='del'>-		 * the lowest bit here.</div><div class='del'>-		 *</div><div class='del'>-		 * Warning:</div><div class='del'>-		 *   There was no datasheet for the AR8030 available so this is</div><div class='del'>-		 *   just a guess. But the AR8035 is listed as pin compatible</div><div class='del'>-		 *   to the AR8030 so there might be a good chance it works on</div><div class='del'>-		 *   the AR8030 too.</div><div class='del'>-		 */</div><div class='del'>-		if (phydev-&gt;drv-&gt;phy_id == ATH8030_PHY_ID ||</div><div class='del'>-		    phydev-&gt;drv-&gt;phy_id == ATH8035_PHY_ID) {</div><div class='del'>-			priv-&gt;clk_25m_reg &amp;= AT8035_CLK_OUT_MASK;</div><div class='del'>-			priv-&gt;clk_25m_mask &amp;= AT8035_CLK_OUT_MASK;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = of_property_read_u32(node, "qca,clk-out-strength", &amp;strength);</div><div class='hunk'>@@ -825,30 +693,6 @@ static int at803x_parse_dt(struct phy_device *phydev)</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping</div><div class='del'>-	 * options.</div><div class='del'>-	 */</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == ATH8031_PHY_ID) {</div><div class='del'>-		if (of_property_read_bool(node, "qca,keep-pll-enabled"))</div><div class='del'>-			priv-&gt;flags |= AT803X_KEEP_PLL_ENABLED;</div><div class='del'>-</div><div class='del'>-		ret = at8031_register_regulators(phydev);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		ret = devm_regulator_get_enable_optional(&amp;phydev-&gt;mdio.dev,</div><div class='del'>-							 "vddio");</div><div class='del'>-		if (ret) {</div><div class='del'>-			phydev_err(phydev, "failed to get VDDIO regulator\n");</div><div class='del'>-			return ret;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Only AR8031/8033 support 1000Base-X for SFP modules */</div><div class='del'>-		ret = phy_sfp_probe(phydev, &amp;at803x_sfp_ops);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -868,35 +712,6 @@ static int at803x_probe(struct phy_device *phydev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == ATH8031_PHY_ID) {</div><div class='del'>-		int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);</div><div class='del'>-		int mode_cfg;</div><div class='del'>-</div><div class='del'>-		if (ccr &lt; 0)</div><div class='del'>-			return ccr;</div><div class='del'>-		mode_cfg = ccr &amp; AT803X_MODE_CFG_MASK;</div><div class='del'>-</div><div class='del'>-		switch (mode_cfg) {</div><div class='del'>-		case AT803X_MODE_CFG_BX1000_RGMII_50OHM:</div><div class='del'>-		case AT803X_MODE_CFG_BX1000_RGMII_75OHM:</div><div class='del'>-			priv-&gt;is_1000basex = true;</div><div class='del'>-			fallthrough;</div><div class='del'>-		case AT803X_MODE_CFG_FX100_RGMII_50OHM:</div><div class='del'>-		case AT803X_MODE_CFG_FX100_RGMII_75OHM:</div><div class='del'>-			priv-&gt;is_fiber = true;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Disable WoL in 1588 register which is enabled</div><div class='del'>-		 * by default</div><div class='del'>-		 */</div><div class='del'>-		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='del'>-				     AT803X_PHY_MMD3_WOL_CTRL,</div><div class='del'>-				     AT803X_WOL_EN, 0);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1004,27 +819,8 @@ static int at803x_hibernation_mode_config(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> static int at803x_config_init(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == ATH8031_PHY_ID) {</div><div class='del'>-		/* Some bootloaders leave the fiber page selected.</div><div class='del'>-		 * Switch to the appropriate page (fiber or copper), as otherwise we</div><div class='del'>-		 * read the PHY capabilities from the wrong page.</div><div class='del'>-		 */</div><div class='del'>-		phy_lock_mdio_bus(phydev);</div><div class='del'>-		ret = at803x_write_page(phydev,</div><div class='del'>-					priv-&gt;is_fiber ? AT803X_PAGE_FIBER :</div><div class='del'>-							 AT803X_PAGE_COPPER);</div><div class='del'>-		phy_unlock_mdio_bus(phydev);</div><div class='del'>-		if (ret)</div><div class='del'>-			return ret;</div><div class='del'>-</div><div class='del'>-		ret = at8031_pll_config(phydev);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	/* The RX and TX delay default is:</div><div class='ctx'> 	 *   after HW reset: RX delay enabled and TX delay disabled</div><div class='ctx'> 	 *   after SW reset: RX delay enabled, while TX delay retains the</div><div class='hunk'>@@ -1078,7 +874,6 @@ static int at803x_ack_interrupt(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> static int at803x_config_intr(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='ctx'> 	int err;</div><div class='ctx'> 	int value;</div><div class='ctx'> </div><div class='hunk'>@@ -1095,10 +890,6 @@ static int at803x_config_intr(struct phy_device *phydev)</div><div class='ctx'> 		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;</div><div class='ctx'> 		value |= AT803X_INTR_ENABLE_LINK_FAIL;</div><div class='ctx'> 		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;</div><div class='del'>-		if (priv-&gt;is_fiber) {</div><div class='del'>-			value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;</div><div class='del'>-			value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;</div><div class='del'>-		}</div><div class='ctx'> </div><div class='ctx'> 		err = phy_write(phydev, AT803X_INTR_ENABLE, value);</div><div class='ctx'> 	} else {</div><div class='hunk'>@@ -1154,9 +945,9 @@ static void at803x_link_change_notify(struct phy_device *phydev)</div><div class='ctx'> 		at803x_context_save(phydev, &amp;context);</div><div class='ctx'> </div><div class='ctx'> 		phy_device_reset(phydev, 1);</div><div class='del'>-		msleep(1);</div><div class='add'>+		usleep_range(1000, 2000);</div><div class='ctx'> 		phy_device_reset(phydev, 0);</div><div class='del'>-		msleep(1);</div><div class='add'>+		usleep_range(1000, 2000);</div><div class='ctx'> </div><div class='ctx'> 		at803x_context_restore(phydev, &amp;context);</div><div class='ctx'> </div><div class='hunk'>@@ -1164,7 +955,8 @@ static void at803x_link_change_notify(struct phy_device *phydev)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_read_specific_status(struct phy_device *phydev)</div><div class='add'>+static int at803x_read_specific_status(struct phy_device *phydev,</div><div class='add'>+				       struct at803x_ss_mask ss_mask)</div><div class='ctx'> {</div><div class='ctx'> 	int ss;</div><div class='ctx'> </div><div class='hunk'>@@ -1183,11 +975,8 @@ static int at803x_read_specific_status(struct phy_device *phydev)</div><div class='ctx'> 		if (sfc &lt; 0)</div><div class='ctx'> 			return sfc;</div><div class='ctx'> </div><div class='del'>-		/* qca8081 takes the different bits for speed value from at803x */</div><div class='del'>-		if (phydev-&gt;drv-&gt;phy_id == QCA8081_PHY_ID)</div><div class='del'>-			speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);</div><div class='del'>-		else</div><div class='del'>-			speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);</div><div class='add'>+		speed = ss &amp; ss_mask.speed_mask;</div><div class='add'>+		speed &gt;&gt;= ss_mask.speed_shift;</div><div class='ctx'> </div><div class='ctx'> 		switch (speed) {</div><div class='ctx'> 		case AT803X_SS_SPEED_10:</div><div class='hunk'>@@ -1231,12 +1020,9 @@ static int at803x_read_specific_status(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> static int at803x_read_status(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	struct at803x_ss_mask ss_mask = { 0 };</div><div class='ctx'> 	int err, old_link = phydev-&gt;link;</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;is_1000basex)</div><div class='del'>-		return genphy_c37_read_status(phydev);</div><div class='del'>-</div><div class='ctx'> 	/* Update the link, but return if there was an error */</div><div class='ctx'> 	err = genphy_update_link(phydev);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -1255,7 +1041,9 @@ static int at803x_read_status(struct phy_device *phydev)</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	err = at803x_read_specific_status(phydev);</div><div class='add'>+	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;</div><div class='add'>+	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);</div><div class='add'>+	err = at803x_read_specific_status(phydev, ss_mask);</div><div class='ctx'> 	if (err &lt; 0)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='hunk'>@@ -1288,9 +1076,8 @@ static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)</div><div class='ctx'> 			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_config_aneg(struct phy_device *phydev)</div><div class='add'>+static int at803x_prepare_config_aneg(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = at803x_config_mdix(phydev, phydev-&gt;mdix_ctrl);</div><div class='hunk'>@@ -1307,33 +1094,22 @@ static int at803x_config_aneg(struct phy_device *phydev)</div><div class='ctx'> 			return ret;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (priv-&gt;is_1000basex)</div><div class='del'>-		return genphy_c37_config_aneg(phydev);</div><div class='del'>-</div><div class='del'>-	/* Do not restart auto-negotiation by setting ret to 0 defautly,</div><div class='del'>-	 * when calling __genphy_config_aneg later.</div><div class='del'>-	 */</div><div class='del'>-	ret = 0;</div><div class='del'>-</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8081_PHY_ID) {</div><div class='del'>-		int phy_ctrl = 0;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-		/* The reg MII_BMCR also needs to be configured for force mode, the</div><div class='del'>-		 * genphy_config_aneg is also needed.</div><div class='del'>-		 */</div><div class='del'>-		if (phydev-&gt;autoneg == AUTONEG_DISABLE)</div><div class='del'>-			genphy_c45_pma_setup_forced(phydev);</div><div class='add'>+static int at803x_config_aneg(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='del'>-		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev-&gt;advertising))</div><div class='del'>-			phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;</div><div class='add'>+	ret = at803x_prepare_config_aneg(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='del'>-		ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,</div><div class='del'>-				MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);</div><div class='del'>-		if (ret &lt; 0)</div><div class='del'>-			return ret;</div><div class='del'>-	}</div><div class='add'>+	if (priv-&gt;is_1000basex)</div><div class='add'>+		return genphy_c37_config_aneg(phydev);</div><div class='ctx'> </div><div class='del'>-	return __genphy_config_aneg(phydev, ret);</div><div class='add'>+	return genphy_config_aneg(phydev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int at803x_get_downshift(struct phy_device *phydev, u8 *d)</div><div class='hunk'>@@ -1441,10 +1217,8 @@ static bool at803x_cdt_fault_length_valid(u16 status)</div><div class='ctx'> 	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_cdt_fault_length(u16 status)</div><div class='add'>+static int at803x_cdt_fault_length(int dt)</div><div class='ctx'> {</div><div class='del'>-	int dt;</div><div class='del'>-</div><div class='ctx'> 	/* According to the datasheet the distance to the fault is</div><div class='ctx'> 	 * DELTA_TIME * 0.824 meters.</div><div class='ctx'> 	 *</div><div class='hunk'>@@ -1460,36 +1234,19 @@ static int at803x_cdt_fault_length(u16 status)</div><div class='ctx'> 	 * With a VF of 0.69 we get the factor 0.824 mentioned in the</div><div class='ctx'> 	 * datasheet.</div><div class='ctx'> 	 */</div><div class='del'>-	dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);</div><div class='del'>-</div><div class='ctx'> 	return (dt * 824) / 10;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_cdt_start(struct phy_device *phydev, int pair)</div><div class='add'>+static int at803x_cdt_start(struct phy_device *phydev,</div><div class='add'>+			    u32 cdt_start)</div><div class='ctx'> {</div><div class='del'>-	u16 cdt;</div><div class='del'>-</div><div class='del'>-	/* qca8081 takes the different bit 15 to enable CDT test */</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8081_PHY_ID)</div><div class='del'>-		cdt = QCA808X_CDT_ENABLE_TEST |</div><div class='del'>-			QCA808X_CDT_LENGTH_UNIT |</div><div class='del'>-			QCA808X_CDT_INTER_CHECK_DIS;</div><div class='del'>-	else</div><div class='del'>-		cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |</div><div class='del'>-			AT803X_CDT_ENABLE_TEST;</div><div class='del'>-</div><div class='del'>-	return phy_write(phydev, AT803X_CDT, cdt);</div><div class='add'>+	return phy_write(phydev, AT803X_CDT, cdt_start);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_cdt_wait_for_completion(struct phy_device *phydev)</div><div class='add'>+static int at803x_cdt_wait_for_completion(struct phy_device *phydev,</div><div class='add'>+					  u32 cdt_en)</div><div class='ctx'> {</div><div class='ctx'> 	int val, ret;</div><div class='del'>-	u16 cdt_en;</div><div class='del'>-</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8081_PHY_ID)</div><div class='del'>-		cdt_en = QCA808X_CDT_ENABLE_TEST;</div><div class='del'>-	else</div><div class='del'>-		cdt_en = AT803X_CDT_ENABLE_TEST;</div><div class='ctx'> </div><div class='ctx'> 	/* One test run takes about 25ms */</div><div class='ctx'> 	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,</div><div class='hunk'>@@ -1509,11 +1266,13 @@ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)</div><div class='ctx'> 	};</div><div class='ctx'> 	int ret, val;</div><div class='ctx'> </div><div class='del'>-	ret = at803x_cdt_start(phydev, pair);</div><div class='add'>+	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |</div><div class='add'>+	      AT803X_CDT_ENABLE_TEST;</div><div class='add'>+	ret = at803x_cdt_start(phydev, val);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	ret = at803x_cdt_wait_for_completion(phydev);</div><div class='add'>+	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1527,27 +1286,21 @@ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)</div><div class='ctx'> 	ethnl_cable_test_result(phydev, ethtool_pair[pair],</div><div class='ctx'> 				at803x_cable_test_result_trans(val));</div><div class='ctx'> </div><div class='del'>-	if (at803x_cdt_fault_length_valid(val))</div><div class='add'>+	if (at803x_cdt_fault_length_valid(val)) {</div><div class='add'>+		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);</div><div class='ctx'> 		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],</div><div class='ctx'> 					      at803x_cdt_fault_length(val));</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int at803x_cable_test_get_status(struct phy_device *phydev,</div><div class='del'>-					bool *finished)</div><div class='add'>+					bool *finished, unsigned long pair_mask)</div><div class='ctx'> {</div><div class='del'>-	unsigned long pair_mask;</div><div class='ctx'> 	int retries = 20;</div><div class='ctx'> 	int pair, ret;</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;phy_id == ATH9331_PHY_ID ||</div><div class='del'>-	    phydev-&gt;phy_id == ATH8032_PHY_ID ||</div><div class='del'>-	    phydev-&gt;phy_id == QCA9561_PHY_ID)</div><div class='del'>-		pair_mask = 0x3;</div><div class='del'>-	else</div><div class='del'>-		pair_mask = 0xf;</div><div class='del'>-</div><div class='ctx'> 	*finished = false;</div><div class='ctx'> </div><div class='ctx'> 	/* According to the datasheet the CDT can be performed when</div><div class='hunk'>@@ -1574,7 +1327,7 @@ static int at803x_cable_test_get_status(struct phy_device *phydev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int at803x_cable_test_start(struct phy_device *phydev)</div><div class='add'>+static void at803x_cable_test_autoneg(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	/* Enable auto-negotiation, but advertise no capabilities, no link</div><div class='ctx'> 	 * will be established. A restart of the auto-negotiation is not</div><div class='hunk'>@@ -1582,15 +1335,358 @@ static int at803x_cable_test_start(struct phy_device *phydev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);</div><div class='ctx'> 	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);</div><div class='del'>-	if (phydev-&gt;phy_id != ATH9331_PHY_ID &amp;&amp;</div><div class='del'>-	    phydev-&gt;phy_id != ATH8032_PHY_ID &amp;&amp;</div><div class='del'>-	    phydev-&gt;phy_id != QCA9561_PHY_ID)</div><div class='del'>-		phy_write(phydev, MII_CTRL1000, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at803x_cable_test_start(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	at803x_cable_test_autoneg(phydev);</div><div class='add'>+	/* we do all the (time consuming) work later */</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,</div><div class='add'>+					    unsigned int selector)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = rdev_get_drvdata(rdev);</div><div class='add'>+</div><div class='add'>+	if (selector)</div><div class='add'>+		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,</div><div class='add'>+					     0, AT803X_DEBUG_RGMII_1V8);</div><div class='add'>+	else</div><div class='add'>+		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,</div><div class='add'>+					     AT803X_DEBUG_RGMII_1V8, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = rdev_get_drvdata(rdev);</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);</div><div class='add'>+	if (val &lt; 0)</div><div class='add'>+		return val;</div><div class='add'>+</div><div class='add'>+	return (val &amp; AT803X_DEBUG_RGMII_1V8) ? 1 : 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct regulator_ops vddio_regulator_ops = {</div><div class='add'>+	.list_voltage = regulator_list_voltage_table,</div><div class='add'>+	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,</div><div class='add'>+	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const unsigned int vddio_voltage_table[] = {</div><div class='add'>+	1500000,</div><div class='add'>+	1800000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regulator_desc vddio_desc = {</div><div class='add'>+	.name = "vddio",</div><div class='add'>+	.of_match = of_match_ptr("vddio-regulator"),</div><div class='add'>+	.n_voltages = ARRAY_SIZE(vddio_voltage_table),</div><div class='add'>+	.volt_table = vddio_voltage_table,</div><div class='add'>+	.ops = &amp;vddio_regulator_ops,</div><div class='add'>+	.type = REGULATOR_VOLTAGE,</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regulator_ops vddh_regulator_ops = {</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct regulator_desc vddh_desc = {</div><div class='add'>+	.name = "vddh",</div><div class='add'>+	.of_match = of_match_ptr("vddh-regulator"),</div><div class='add'>+	.n_voltages = 1,</div><div class='add'>+	.fixed_uV = 2500000,</div><div class='add'>+	.ops = &amp;vddh_regulator_ops,</div><div class='add'>+	.type = REGULATOR_VOLTAGE,</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int at8031_register_regulators(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	struct device *dev = &amp;phydev-&gt;mdio.dev;</div><div class='add'>+	struct regulator_config config = { };</div><div class='add'>+</div><div class='add'>+	config.dev = dev;</div><div class='add'>+	config.driver_data = phydev;</div><div class='add'>+</div><div class='add'>+	priv-&gt;vddio_rdev = devm_regulator_register(dev, &amp;vddio_desc, &amp;config);</div><div class='add'>+	if (IS_ERR(priv-&gt;vddio_rdev)) {</div><div class='add'>+		phydev_err(phydev, "failed to register VDDIO regulator\n");</div><div class='add'>+		return PTR_ERR(priv-&gt;vddio_rdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	priv-&gt;vddh_rdev = devm_regulator_register(dev, &amp;vddh_desc, &amp;config);</div><div class='add'>+	if (IS_ERR(priv-&gt;vddh_rdev)) {</div><div class='add'>+		phydev_err(phydev, "failed to register VDDH regulator\n");</div><div class='add'>+		return PTR_ERR(priv-&gt;vddh_rdev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = upstream;</div><div class='add'>+	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);</div><div class='add'>+	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);</div><div class='add'>+	DECLARE_PHY_INTERFACE_MASK(interfaces);</div><div class='add'>+	phy_interface_t iface;</div><div class='add'>+</div><div class='add'>+	linkmode_zero(phy_support);</div><div class='add'>+	phylink_set(phy_support, 1000baseX_Full);</div><div class='add'>+	phylink_set(phy_support, 1000baseT_Full);</div><div class='add'>+	phylink_set(phy_support, Autoneg);</div><div class='add'>+	phylink_set(phy_support, Pause);</div><div class='add'>+	phylink_set(phy_support, Asym_Pause);</div><div class='add'>+</div><div class='add'>+	linkmode_zero(sfp_support);</div><div class='add'>+	sfp_parse_support(phydev-&gt;sfp_bus, id, sfp_support, interfaces);</div><div class='add'>+	/* Some modules support 10G modes as well as others we support.</div><div class='add'>+	 * Mask out non-supported modes so the correct interface is picked.</div><div class='add'>+	 */</div><div class='add'>+	linkmode_and(sfp_support, phy_support, sfp_support);</div><div class='add'>+</div><div class='add'>+	if (linkmode_empty(sfp_support)) {</div><div class='add'>+		dev_err(&amp;phydev-&gt;mdio.dev, "incompatible SFP module inserted\n");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	iface = sfp_select_interface(phydev-&gt;sfp_bus, sfp_support);</div><div class='add'>+</div><div class='add'>+	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes</div><div class='add'>+	 * interface for use with SFP modules.</div><div class='add'>+	 * However, some copper modules detected as having a preferred SGMII</div><div class='add'>+	 * interface do default to and function in 1000Base-X mode, so just</div><div class='add'>+	 * print a warning and allow such modules, as they may have some chance</div><div class='add'>+	 * of working.</div><div class='add'>+	 */</div><div class='add'>+	if (iface == PHY_INTERFACE_MODE_SGMII)</div><div class='add'>+		dev_warn(&amp;phydev-&gt;mdio.dev, "module may not function if 1000Base-X not supported\n");</div><div class='add'>+	else if (iface != PHY_INTERFACE_MODE_1000BASEX)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct sfp_upstream_ops at8031_sfp_ops = {</div><div class='add'>+	.attach = phy_sfp_attach,</div><div class='add'>+	.detach = phy_sfp_detach,</div><div class='add'>+	.module_insert = at8031_sfp_insert,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int at8031_parse_dt(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct device_node *node = phydev-&gt;mdio.dev.of_node;</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (of_property_read_bool(node, "qca,keep-pll-enabled"))</div><div class='add'>+		priv-&gt;flags |= AT803X_KEEP_PLL_ENABLED;</div><div class='add'>+</div><div class='add'>+	ret = at8031_register_regulators(phydev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = devm_regulator_get_enable_optional(&amp;phydev-&gt;mdio.dev,</div><div class='add'>+						 "vddio");</div><div class='add'>+	if (ret) {</div><div class='add'>+		phydev_err(phydev, "failed to get VDDIO regulator\n");</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Only AR8031/8033 support 1000Base-X for SFP modules */</div><div class='add'>+	return phy_sfp_probe(phydev, &amp;at8031_sfp_ops);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_probe(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	int mode_cfg;</div><div class='add'>+	int ccr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = at803x_probe(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping</div><div class='add'>+	 * options.</div><div class='add'>+	 */</div><div class='add'>+	ret = at8031_parse_dt(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);</div><div class='add'>+	if (ccr &lt; 0)</div><div class='add'>+		return ccr;</div><div class='add'>+	mode_cfg = ccr &amp; AT803X_MODE_CFG_MASK;</div><div class='add'>+</div><div class='add'>+	switch (mode_cfg) {</div><div class='add'>+	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:</div><div class='add'>+	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:</div><div class='add'>+		priv-&gt;is_1000basex = true;</div><div class='add'>+		fallthrough;</div><div class='add'>+	case AT803X_MODE_CFG_FX100_RGMII_50OHM:</div><div class='add'>+	case AT803X_MODE_CFG_FX100_RGMII_75OHM:</div><div class='add'>+		priv-&gt;is_fiber = true;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Disable WoL in 1588 register which is enabled</div><div class='add'>+	 * by default</div><div class='add'>+	 */</div><div class='add'>+	return phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='add'>+			      AT803X_PHY_MMD3_WOL_CTRL,</div><div class='add'>+			      AT803X_WOL_EN, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Some bootloaders leave the fiber page selected.</div><div class='add'>+	 * Switch to the appropriate page (fiber or copper), as otherwise we</div><div class='add'>+	 * read the PHY capabilities from the wrong page.</div><div class='add'>+	 */</div><div class='add'>+	phy_lock_mdio_bus(phydev);</div><div class='add'>+	ret = at803x_write_page(phydev,</div><div class='add'>+				priv-&gt;is_fiber ? AT803X_PAGE_FIBER :</div><div class='add'>+						 AT803X_PAGE_COPPER);</div><div class='add'>+	phy_unlock_mdio_bus(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = at8031_pll_config(phydev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return at803x_config_init(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_set_wol(struct phy_device *phydev,</div><div class='add'>+			  struct ethtool_wolinfo *wol)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* First setup MAC address and enable WOL interrupt */</div><div class='add'>+	ret = at803x_set_wol(phydev, wol);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	if (wol-&gt;wolopts &amp; WAKE_MAGIC)</div><div class='add'>+		/* Enable WOL function for 1588 */</div><div class='add'>+		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='add'>+				     AT803X_PHY_MMD3_WOL_CTRL,</div><div class='add'>+				     0, AT803X_WOL_EN);</div><div class='add'>+	else</div><div class='add'>+		/* Disable WoL function for 1588 */</div><div class='add'>+		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,</div><div class='add'>+				     AT803X_PHY_MMD3_WOL_CTRL,</div><div class='add'>+				     AT803X_WOL_EN, 0);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8031_config_intr(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+	int err, value = 0;</div><div class='add'>+</div><div class='add'>+	if (phydev-&gt;interrupts == PHY_INTERRUPT_ENABLED &amp;&amp;</div><div class='add'>+	    priv-&gt;is_fiber) {</div><div class='add'>+		/* Clear any pending interrupts */</div><div class='add'>+		err = at803x_ack_interrupt(phydev);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+</div><div class='add'>+		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;</div><div class='add'>+		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;</div><div class='add'>+</div><div class='add'>+		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);</div><div class='add'>+		if (err)</div><div class='add'>+			return err;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return at803x_config_intr(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* AR8031 and AR8033 share the same read status logic */</div><div class='add'>+static int at8031_read_status(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+</div><div class='add'>+	if (priv-&gt;is_1000basex)</div><div class='add'>+		return genphy_c37_read_status(phydev);</div><div class='ctx'> </div><div class='add'>+	return at803x_read_status(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* AR8031 and AR8035 share the same cable test get status reg */</div><div class='add'>+static int at8031_cable_test_get_status(struct phy_device *phydev,</div><div class='add'>+					bool *finished)</div><div class='add'>+{</div><div class='add'>+	return at803x_cable_test_get_status(phydev, finished, 0xf);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* AR8031 and AR8035 share the same cable test start logic */</div><div class='add'>+static int at8031_cable_test_start(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	at803x_cable_test_autoneg(phydev);</div><div class='add'>+	phy_write(phydev, MII_CTRL1000, 0);</div><div class='ctx'> 	/* we do all the (time consuming) work later */</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */</div><div class='add'>+static int at8032_cable_test_get_status(struct phy_device *phydev,</div><div class='add'>+					bool *finished)</div><div class='add'>+{</div><div class='add'>+	return at803x_cable_test_get_status(phydev, finished, 0x3);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int at8035_parse_dt(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct at803x_priv *priv = phydev-&gt;priv;</div><div class='add'>+</div><div class='add'>+	/* Mask is set by the generic at803x_parse_dt</div><div class='add'>+	 * if property is set. Assume property is set</div><div class='add'>+	 * with the mask not zero.</div><div class='add'>+	 */</div><div class='add'>+	if (priv-&gt;clk_25m_mask) {</div><div class='add'>+		/* Fixup for the AR8030/AR8035. This chip has another mask and</div><div class='add'>+		 * doesn't support the DSP reference. Eg. the lowest bit of the</div><div class='add'>+		 * mask. The upper two bits select the same frequencies. Mask</div><div class='add'>+		 * the lowest bit here.</div><div class='add'>+		 *</div><div class='add'>+		 * Warning:</div><div class='add'>+		 *   There was no datasheet for the AR8030 available so this is</div><div class='add'>+		 *   just a guess. But the AR8035 is listed as pin compatible</div><div class='add'>+		 *   to the AR8030 so there might be a good chance it works on</div><div class='add'>+		 *   the AR8030 too.</div><div class='add'>+		 */</div><div class='add'>+		priv-&gt;clk_25m_reg &amp;= AT8035_CLK_OUT_MASK;</div><div class='add'>+		priv-&gt;clk_25m_mask &amp;= AT8035_CLK_OUT_MASK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/* AR8030 and AR8035 shared the same special mask for clk_25m */</div><div class='add'>+static int at8035_probe(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = at803x_probe(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return at8035_parse_dt(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int qca83xx_config_init(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	u8 switch_revision;</div><div class='hunk'>@@ -1616,27 +1712,26 @@ static int qca83xx_config_init(struct phy_device *phydev)</div><div class='ctx'> 		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* Following original QCA sourcecode set port to prefer master */</div><div class='add'>+	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int qca8327_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='ctx'> 	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.</div><div class='ctx'> 	 * Disable on init and enable only with 100m speed following</div><div class='ctx'> 	 * qca original source code.</div><div class='ctx'> 	 */</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8327_A_PHY_ID ||</div><div class='del'>-	    phydev-&gt;drv-&gt;phy_id == QCA8327_B_PHY_ID)</div><div class='del'>-		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,</div><div class='del'>-				      QCA8327_DEBUG_MANU_CTRL_EN, 0);</div><div class='add'>+	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,</div><div class='add'>+			      QCA8327_DEBUG_MANU_CTRL_EN, 0);</div><div class='ctx'> </div><div class='del'>-	/* Following original QCA sourcecode set port to prefer master */</div><div class='del'>-	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return qca83xx_config_init(phydev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void qca83xx_link_change_notify(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	/* QCA8337 doesn't require DAC Amplitude adjustement */</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8337_PHY_ID)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	/* Set DAC Amplitude adjustment to +6% for 100m on link running */</div><div class='ctx'> 	if (phydev-&gt;state == PHY_RUNNING) {</div><div class='ctx'> 		if (phydev-&gt;speed == SPEED_100)</div><div class='hunk'>@@ -1672,26 +1767,13 @@ static int qca83xx_resume(struct phy_device *phydev)</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	msleep(1);</div><div class='add'>+	usleep_range(1000, 2000);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qca83xx_suspend(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	u16 mask = 0;</div><div class='del'>-</div><div class='del'>-	/* Only QCA8337 support actual suspend.</div><div class='del'>-	 * QCA8327 cause port unreliability when phy suspend</div><div class='del'>-	 * is set.</div><div class='del'>-	 */</div><div class='del'>-	if (phydev-&gt;drv-&gt;phy_id == QCA8337_PHY_ID) {</div><div class='del'>-		genphy_suspend(phydev);</div><div class='del'>-	} else {</div><div class='del'>-		mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);</div><div class='del'>-		phy_modify(phydev, MII_BMCR, mask, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='ctx'> 	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,</div><div class='ctx'> 			      AT803X_DEBUG_GATE_CLK_IN1000, 0);</div><div class='ctx'> </div><div class='hunk'>@@ -1702,6 +1784,27 @@ static int qca83xx_suspend(struct phy_device *phydev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int qca8337_suspend(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	/* Only QCA8337 support actual suspend. */</div><div class='add'>+	genphy_suspend(phydev);</div><div class='add'>+</div><div class='add'>+	return qca83xx_suspend(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int qca8327_suspend(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	u16 mask = 0;</div><div class='add'>+</div><div class='add'>+	/* QCA8327 cause port unreliability when phy suspend</div><div class='add'>+	 * is set.</div><div class='add'>+	 */</div><div class='add'>+	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);</div><div class='add'>+	phy_modify(phydev, MII_BMCR, mask, 0);</div><div class='add'>+</div><div class='add'>+	return qca83xx_suspend(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1712,27 +1815,27 @@ static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,</div><div class='del'>-			QCA808X_TOP_OPTION1_DATA);</div><div class='add'>+		      QCA808X_TOP_OPTION1_DATA);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,</div><div class='del'>-			QCA808X_MSE_THRESHOLD_20DB_VALUE);</div><div class='add'>+		      QCA808X_MSE_THRESHOLD_20DB_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,</div><div class='del'>-			QCA808X_MSE_THRESHOLD_17DB_VALUE);</div><div class='add'>+		      QCA808X_MSE_THRESHOLD_17DB_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,</div><div class='del'>-			QCA808X_MSE_THRESHOLD_27DB_VALUE);</div><div class='add'>+		      QCA808X_MSE_THRESHOLD_27DB_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,</div><div class='del'>-			QCA808X_MSE_THRESHOLD_28DB_VALUE);</div><div class='add'>+		      QCA808X_MSE_THRESHOLD_28DB_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,</div><div class='del'>-			QCA808X_MMD3_DEBUG_1_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_1_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,</div><div class='del'>-			QCA808X_MMD3_DEBUG_4_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_4_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,</div><div class='del'>-			QCA808X_MMD3_DEBUG_5_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_5_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,</div><div class='del'>-			QCA808X_MMD3_DEBUG_3_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_3_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,</div><div class='del'>-			QCA808X_MMD3_DEBUG_6_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_6_VALUE);</div><div class='ctx'> 	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,</div><div class='del'>-			QCA808X_MMD3_DEBUG_2_VALUE);</div><div class='add'>+		      QCA808X_MMD3_DEBUG_2_VALUE);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -1769,13 +1872,14 @@ static int qca808x_config_init(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	/* Active adc&amp;vga on 802.3az for the link 1000M and 100M */</div><div class='ctx'> 	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,</div><div class='del'>-			QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);</div><div class='add'>+			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	/* Adjust the threshold on 802.3az for the link 1000M */</div><div class='ctx'> 	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,</div><div class='del'>-			QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);</div><div class='add'>+			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,</div><div class='add'>+			    QCA808X_MMD3_AZ_TRAINING_VAL);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1801,11 +1905,13 @@ static int qca808x_config_init(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	/* Configure adc threshold as 100mv for the link 10M */</div><div class='ctx'> 	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,</div><div class='del'>-			QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);</div><div class='add'>+				     QCA808X_ADC_THRESHOLD_MASK,</div><div class='add'>+				     QCA808X_ADC_THRESHOLD_100MV);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qca808x_read_status(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='add'>+	struct at803x_ss_mask ss_mask = { 0 };</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);</div><div class='hunk'>@@ -1813,13 +1919,16 @@ static int qca808x_read_status(struct phy_device *phydev)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='ctx'> 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev-&gt;lp_advertising,</div><div class='del'>-			ret &amp; MDIO_AN_10GBT_STAT_LP2_5G);</div><div class='add'>+			 ret &amp; MDIO_AN_10GBT_STAT_LP2_5G);</div><div class='ctx'> </div><div class='ctx'> 	ret = genphy_read_status(phydev);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	ret = at803x_read_specific_status(phydev);</div><div class='add'>+	/* qca8081 takes the different bits for speed value from at803x */</div><div class='add'>+	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;</div><div class='add'>+	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);</div><div class='add'>+	ret = at803x_read_specific_status(phydev, ss_mask);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1840,7 +1949,7 @@ static int qca808x_read_status(struct phy_device *phydev)</div><div class='ctx'> 		 */</div><div class='ctx'> 		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {</div><div class='ctx'> 			if (phydev-&gt;master_slave_state == MASTER_SLAVE_STATE_ERR ||</div><div class='del'>-					qca808x_is_prefer_master(phydev)) {</div><div class='add'>+			    qca808x_is_prefer_master(phydev)) {</div><div class='ctx'> 				qca808x_phy_ms_seed_enable(phydev, false);</div><div class='ctx'> 			} else {</div><div class='ctx'> 				qca808x_phy_ms_seed_enable(phydev, true);</div><div class='hunk'>@@ -1868,8 +1977,17 @@ static int qca808x_soft_reset(struct phy_device *phydev)</div><div class='ctx'> static bool qca808x_cdt_fault_length_valid(int cdt_code)</div><div class='ctx'> {</div><div class='ctx'> 	switch (cdt_code) {</div><div class='del'>-	case QCA808X_CDT_STATUS_STAT_SHORT:</div><div class='del'>-	case QCA808X_CDT_STATUS_STAT_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:</div><div class='ctx'> 		return true;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return false;</div><div class='hunk'>@@ -1881,17 +1999,28 @@ static int qca808x_cable_test_result_trans(int cdt_code)</div><div class='ctx'> 	switch (cdt_code) {</div><div class='ctx'> 	case QCA808X_CDT_STATUS_STAT_NORMAL:</div><div class='ctx'> 		return ETHTOOL_A_CABLE_RESULT_CODE_OK;</div><div class='del'>-	case QCA808X_CDT_STATUS_STAT_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:</div><div class='ctx'> 		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;</div><div class='del'>-	case QCA808X_CDT_STATUS_STAT_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:</div><div class='ctx'> 		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:</div><div class='add'>+	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:</div><div class='add'>+		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;</div><div class='ctx'> 	case QCA808X_CDT_STATUS_STAT_FAIL:</div><div class='ctx'> 	default:</div><div class='ctx'> 		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)</div><div class='add'>+static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,</div><div class='add'>+				    int result)</div><div class='ctx'> {</div><div class='ctx'> 	int val;</div><div class='ctx'> 	u32 cdt_length_reg = 0;</div><div class='hunk'>@@ -1917,7 +2046,12 @@ static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)</div><div class='ctx'> 	if (val &lt; 0)</div><div class='ctx'> 		return val;</div><div class='ctx'> </div><div class='del'>-	return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;</div><div class='add'>+	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)</div><div class='add'>+		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);</div><div class='add'>+	else</div><div class='add'>+		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);</div><div class='add'>+</div><div class='add'>+	return at803x_cdt_fault_length(val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int qca808x_cable_test_start(struct phy_device *phydev)</div><div class='hunk'>@@ -1961,18 +2095,53 @@ static int qca808x_cable_test_start(struct phy_device *phydev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,</div><div class='add'>+					      u16 status)</div><div class='add'>+{</div><div class='add'>+	int length, result;</div><div class='add'>+	u16 pair_code;</div><div class='add'>+</div><div class='add'>+	switch (pair) {</div><div class='add'>+	case ETHTOOL_A_CABLE_PAIR_A:</div><div class='add'>+		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);</div><div class='add'>+		break;</div><div class='add'>+	case ETHTOOL_A_CABLE_PAIR_B:</div><div class='add'>+		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);</div><div class='add'>+		break;</div><div class='add'>+	case ETHTOOL_A_CABLE_PAIR_C:</div><div class='add'>+		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);</div><div class='add'>+		break;</div><div class='add'>+	case ETHTOOL_A_CABLE_PAIR_D:</div><div class='add'>+		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	result = qca808x_cable_test_result_trans(pair_code);</div><div class='add'>+	ethnl_cable_test_result(phydev, pair, result);</div><div class='add'>+</div><div class='add'>+	if (qca808x_cdt_fault_length_valid(pair_code)) {</div><div class='add'>+		length = qca808x_cdt_fault_length(phydev, pair, result);</div><div class='add'>+		ethnl_cable_test_fault_length(phydev, pair, length);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)</div><div class='ctx'> {</div><div class='ctx'> 	int ret, val;</div><div class='del'>-	int pair_a, pair_b, pair_c, pair_d;</div><div class='ctx'> </div><div class='ctx'> 	*finished = false;</div><div class='ctx'> </div><div class='del'>-	ret = at803x_cdt_start(phydev, 0);</div><div class='add'>+	val = QCA808X_CDT_ENABLE_TEST |</div><div class='add'>+	      QCA808X_CDT_LENGTH_UNIT;</div><div class='add'>+	ret = at803x_cdt_start(phydev, val);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='del'>-	ret = at803x_cdt_wait_for_completion(phydev);</div><div class='add'>+	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='hunk'>@@ -1980,32 +2149,21 @@ static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finish</div><div class='ctx'> 	if (val &lt; 0)</div><div class='ctx'> 		return val;</div><div class='ctx'> </div><div class='del'>-	pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);</div><div class='del'>-	pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);</div><div class='del'>-	pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);</div><div class='del'>-	pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);</div><div class='del'>-</div><div class='del'>-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,</div><div class='del'>-				qca808x_cable_test_result_trans(pair_a));</div><div class='del'>-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,</div><div class='del'>-				qca808x_cable_test_result_trans(pair_b));</div><div class='del'>-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,</div><div class='del'>-				qca808x_cable_test_result_trans(pair_c));</div><div class='del'>-	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,</div><div class='del'>-				qca808x_cable_test_result_trans(pair_d));</div><div class='del'>-</div><div class='del'>-	if (qca808x_cdt_fault_length_valid(pair_a))</div><div class='del'>-		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,</div><div class='del'>-				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));</div><div class='del'>-	if (qca808x_cdt_fault_length_valid(pair_b))</div><div class='del'>-		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,</div><div class='del'>-				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));</div><div class='del'>-	if (qca808x_cdt_fault_length_valid(pair_c))</div><div class='del'>-		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,</div><div class='del'>-				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));</div><div class='del'>-	if (qca808x_cdt_fault_length_valid(pair_d))</div><div class='del'>-		ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,</div><div class='del'>-				qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));</div><div class='add'>+	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	*finished = true;</div><div class='ctx'> </div><div class='hunk'>@@ -2040,14 +2198,41 @@ static int qca808x_get_features(struct phy_device *phydev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int qca808x_config_aneg(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int phy_ctrl = 0;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = at803x_prepare_config_aneg(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* The reg MII_BMCR also needs to be configured for force mode, the</div><div class='add'>+	 * genphy_config_aneg is also needed.</div><div class='add'>+	 */</div><div class='add'>+	if (phydev-&gt;autoneg == AUTONEG_DISABLE)</div><div class='add'>+		genphy_c45_pma_setup_forced(phydev);</div><div class='add'>+</div><div class='add'>+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev-&gt;advertising))</div><div class='add'>+		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;</div><div class='add'>+</div><div class='add'>+	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,</div><div class='add'>+				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return __genphy_config_aneg(phydev, ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void qca808x_link_change_notify(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	/* Assert interface sgmii fifo on link down, deassert it on link up,</div><div class='ctx'> 	 * the interface device address is always phy address added by 1.</div><div class='ctx'> 	 */</div><div class='ctx'> 	mdiobus_c45_modify_changed(phydev-&gt;mdio.bus, phydev-&gt;mdio.addr + 1,</div><div class='del'>-			MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,</div><div class='del'>-			QCA8081_PHY_FIFO_RSTN, phydev-&gt;link ? QCA8081_PHY_FIFO_RSTN : 0);</div><div class='add'>+				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,</div><div class='add'>+				   QCA8081_PHY_FIFO_RSTN,</div><div class='add'>+				   phydev-&gt;link ? QCA8081_PHY_FIFO_RSTN : 0);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct phy_driver at803x_driver[] = {</div><div class='hunk'>@@ -2056,7 +2241,7 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),</div><div class='ctx'> 	.name			= "Qualcomm Atheros AR8035",</div><div class='ctx'> 	.flags			= PHY_POLL_CABLE_TEST,</div><div class='del'>-	.probe			= at803x_probe,</div><div class='add'>+	.probe			= at8035_probe,</div><div class='ctx'> 	.config_aneg		= at803x_config_aneg,</div><div class='ctx'> 	.config_init		= at803x_config_init,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='hunk'>@@ -2070,14 +2255,14 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.handle_interrupt	= at803x_handle_interrupt,</div><div class='ctx'> 	.get_tunable		= at803x_get_tunable,</div><div class='ctx'> 	.set_tunable		= at803x_set_tunable,</div><div class='del'>-	.cable_test_start	= at803x_cable_test_start,</div><div class='del'>-	.cable_test_get_status	= at803x_cable_test_get_status,</div><div class='add'>+	.cable_test_start	= at8031_cable_test_start,</div><div class='add'>+	.cable_test_get_status	= at8031_cable_test_get_status,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* Qualcomm Atheros AR8030 */</div><div class='ctx'> 	.phy_id			= ATH8030_PHY_ID,</div><div class='ctx'> 	.name			= "Qualcomm Atheros AR8030",</div><div class='ctx'> 	.phy_id_mask		= AT8030_PHY_ID_MASK,</div><div class='del'>-	.probe			= at803x_probe,</div><div class='add'>+	.probe			= at8035_probe,</div><div class='ctx'> 	.config_init		= at803x_config_init,</div><div class='ctx'> 	.link_change_notify	= at803x_link_change_notify,</div><div class='ctx'> 	.set_wol		= at803x_set_wol,</div><div class='hunk'>@@ -2092,24 +2277,24 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),</div><div class='ctx'> 	.name			= "Qualcomm Atheros AR8031/AR8033",</div><div class='ctx'> 	.flags			= PHY_POLL_CABLE_TEST,</div><div class='del'>-	.probe			= at803x_probe,</div><div class='del'>-	.config_init		= at803x_config_init,</div><div class='add'>+	.probe			= at8031_probe,</div><div class='add'>+	.config_init		= at8031_config_init,</div><div class='ctx'> 	.config_aneg		= at803x_config_aneg,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='del'>-	.set_wol		= at803x_set_wol,</div><div class='add'>+	.set_wol		= at8031_set_wol,</div><div class='ctx'> 	.get_wol		= at803x_get_wol,</div><div class='ctx'> 	.suspend		= at803x_suspend,</div><div class='ctx'> 	.resume			= at803x_resume,</div><div class='ctx'> 	.read_page		= at803x_read_page,</div><div class='ctx'> 	.write_page		= at803x_write_page,</div><div class='ctx'> 	.get_features		= at803x_get_features,</div><div class='del'>-	.read_status		= at803x_read_status,</div><div class='del'>-	.config_intr		= &amp;at803x_config_intr,</div><div class='add'>+	.read_status		= at8031_read_status,</div><div class='add'>+	.config_intr		= at8031_config_intr,</div><div class='ctx'> 	.handle_interrupt	= at803x_handle_interrupt,</div><div class='ctx'> 	.get_tunable		= at803x_get_tunable,</div><div class='ctx'> 	.set_tunable		= at803x_set_tunable,</div><div class='del'>-	.cable_test_start	= at803x_cable_test_start,</div><div class='del'>-	.cable_test_get_status	= at803x_cable_test_get_status,</div><div class='add'>+	.cable_test_start	= at8031_cable_test_start,</div><div class='add'>+	.cable_test_get_status	= at8031_cable_test_get_status,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* Qualcomm Atheros AR8032 */</div><div class='ctx'> 	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),</div><div class='hunk'>@@ -2124,7 +2309,7 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.config_intr		= at803x_config_intr,</div><div class='ctx'> 	.handle_interrupt	= at803x_handle_interrupt,</div><div class='ctx'> 	.cable_test_start	= at803x_cable_test_start,</div><div class='del'>-	.cable_test_get_status	= at803x_cable_test_get_status,</div><div class='add'>+	.cable_test_get_status	= at8032_cable_test_get_status,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* ATHEROS AR9331 */</div><div class='ctx'> 	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),</div><div class='hunk'>@@ -2134,10 +2319,10 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.resume			= at803x_resume,</div><div class='ctx'> 	.flags			= PHY_POLL_CABLE_TEST,</div><div class='ctx'> 	/* PHY_BASIC_FEATURES */</div><div class='del'>-	.config_intr		= &amp;at803x_config_intr,</div><div class='add'>+	.config_intr		= at803x_config_intr,</div><div class='ctx'> 	.handle_interrupt	= at803x_handle_interrupt,</div><div class='ctx'> 	.cable_test_start	= at803x_cable_test_start,</div><div class='del'>-	.cable_test_get_status	= at803x_cable_test_get_status,</div><div class='add'>+	.cable_test_get_status	= at8032_cable_test_get_status,</div><div class='ctx'> 	.read_status		= at803x_read_status,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='ctx'> 	.config_aneg		= at803x_config_aneg,</div><div class='hunk'>@@ -2150,10 +2335,10 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.resume			= at803x_resume,</div><div class='ctx'> 	.flags			= PHY_POLL_CABLE_TEST,</div><div class='ctx'> 	/* PHY_BASIC_FEATURES */</div><div class='del'>-	.config_intr		= &amp;at803x_config_intr,</div><div class='add'>+	.config_intr		= at803x_config_intr,</div><div class='ctx'> 	.handle_interrupt	= at803x_handle_interrupt,</div><div class='ctx'> 	.cable_test_start	= at803x_cable_test_start,</div><div class='del'>-	.cable_test_get_status	= at803x_cable_test_get_status,</div><div class='add'>+	.cable_test_get_status	= at8032_cable_test_get_status,</div><div class='ctx'> 	.read_status		= at803x_read_status,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='ctx'> 	.config_aneg		= at803x_config_aneg,</div><div class='hunk'>@@ -2163,15 +2348,14 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.phy_id_mask		= QCA8K_PHY_ID_MASK,</div><div class='ctx'> 	.name			= "Qualcomm Atheros 8337 internal PHY",</div><div class='ctx'> 	/* PHY_GBIT_FEATURES */</div><div class='del'>-	.link_change_notify	= qca83xx_link_change_notify,</div><div class='ctx'> 	.probe			= at803x_probe,</div><div class='ctx'> 	.flags			= PHY_IS_INTERNAL,</div><div class='ctx'> 	.config_init		= qca83xx_config_init,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='del'>-	.get_sset_count		= at803x_get_sset_count,</div><div class='del'>-	.get_strings		= at803x_get_strings,</div><div class='del'>-	.get_stats		= at803x_get_stats,</div><div class='del'>-	.suspend		= qca83xx_suspend,</div><div class='add'>+	.get_sset_count		= qca83xx_get_sset_count,</div><div class='add'>+	.get_strings		= qca83xx_get_strings,</div><div class='add'>+	.get_stats		= qca83xx_get_stats,</div><div class='add'>+	.suspend		= qca8337_suspend,</div><div class='ctx'> 	.resume			= qca83xx_resume,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* QCA8327-A from switch QCA8327-AL1A */</div><div class='hunk'>@@ -2182,12 +2366,12 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.link_change_notify	= qca83xx_link_change_notify,</div><div class='ctx'> 	.probe			= at803x_probe,</div><div class='ctx'> 	.flags			= PHY_IS_INTERNAL,</div><div class='del'>-	.config_init		= qca83xx_config_init,</div><div class='add'>+	.config_init		= qca8327_config_init,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='del'>-	.get_sset_count		= at803x_get_sset_count,</div><div class='del'>-	.get_strings		= at803x_get_strings,</div><div class='del'>-	.get_stats		= at803x_get_stats,</div><div class='del'>-	.suspend		= qca83xx_suspend,</div><div class='add'>+	.get_sset_count		= qca83xx_get_sset_count,</div><div class='add'>+	.get_strings		= qca83xx_get_strings,</div><div class='add'>+	.get_stats		= qca83xx_get_stats,</div><div class='add'>+	.suspend		= qca8327_suspend,</div><div class='ctx'> 	.resume			= qca83xx_resume,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* QCA8327-B from switch QCA8327-BL1A */</div><div class='hunk'>@@ -2198,12 +2382,12 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.link_change_notify	= qca83xx_link_change_notify,</div><div class='ctx'> 	.probe			= at803x_probe,</div><div class='ctx'> 	.flags			= PHY_IS_INTERNAL,</div><div class='del'>-	.config_init		= qca83xx_config_init,</div><div class='add'>+	.config_init		= qca8327_config_init,</div><div class='ctx'> 	.soft_reset		= genphy_soft_reset,</div><div class='del'>-	.get_sset_count		= at803x_get_sset_count,</div><div class='del'>-	.get_strings		= at803x_get_strings,</div><div class='del'>-	.get_stats		= at803x_get_stats,</div><div class='del'>-	.suspend		= qca83xx_suspend,</div><div class='add'>+	.get_sset_count		= qca83xx_get_sset_count,</div><div class='add'>+	.get_strings		= qca83xx_get_strings,</div><div class='add'>+	.get_stats		= qca83xx_get_stats,</div><div class='add'>+	.suspend		= qca8327_suspend,</div><div class='ctx'> 	.resume			= qca83xx_resume,</div><div class='ctx'> }, {</div><div class='ctx'> 	/* Qualcomm QCA8081 */</div><div class='hunk'>@@ -2218,7 +2402,7 @@ static struct phy_driver at803x_driver[] = {</div><div class='ctx'> 	.set_wol		= at803x_set_wol,</div><div class='ctx'> 	.get_wol		= at803x_get_wol,</div><div class='ctx'> 	.get_features		= qca808x_get_features,</div><div class='del'>-	.config_aneg		= at803x_config_aneg,</div><div class='add'>+	.config_aneg		= qca808x_config_aneg,</div><div class='ctx'> 	.suspend		= genphy_suspend,</div><div class='ctx'> 	.resume			= genphy_resume,</div><div class='ctx'> 	.read_status		= qca808x_read_status,</div><div class='head'>diff --git a/drivers/net/phy/ax88796b_rust.rs b/drivers/net/phy/ax88796b_rust.rs<br/>new file mode 100644<br/>index 000000000000..5c92572962dc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/ax88796b_rust.rs?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/ax88796b_rust.rs</a></div><div class='hunk'>@@ -0,0 +1,135 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+// Copyright (C) 2023 FUJITA Tomonori &lt;fujita.tomonori@gmail.com&gt;</div><div class='add'>+</div><div class='add'>+//! Rust Asix PHYs driver</div><div class='add'>+//!</div><div class='add'>+//! C version of this driver: [`drivers/net/phy/ax88796b.c`](./ax88796b.c)</div><div class='add'>+use kernel::{</div><div class='add'>+    c_str,</div><div class='add'>+    net::phy::{self, DeviceId, Driver},</div><div class='add'>+    prelude::*,</div><div class='add'>+    uapi,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+kernel::module_phy_driver! {</div><div class='add'>+    drivers: [PhyAX88772A, PhyAX88772C, PhyAX88796B],</div><div class='add'>+    device_table: [</div><div class='add'>+        DeviceId::new_with_driver::&lt;PhyAX88772A&gt;(),</div><div class='add'>+        DeviceId::new_with_driver::&lt;PhyAX88772C&gt;(),</div><div class='add'>+        DeviceId::new_with_driver::&lt;PhyAX88796B&gt;()</div><div class='add'>+    ],</div><div class='add'>+    name: "rust_asix_phy",</div><div class='add'>+    author: "FUJITA Tomonori &lt;fujita.tomonori@gmail.com&gt;",</div><div class='add'>+    description: "Rust Asix PHYs driver",</div><div class='add'>+    license: "GPL",</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+const MII_BMCR: u16 = uapi::MII_BMCR as u16;</div><div class='add'>+const BMCR_SPEED100: u16 = uapi::BMCR_SPEED100 as u16;</div><div class='add'>+const BMCR_FULLDPLX: u16 = uapi::BMCR_FULLDPLX as u16;</div><div class='add'>+</div><div class='add'>+// Performs a software PHY reset using the standard</div><div class='add'>+// BMCR_RESET bit and poll for the reset bit to be cleared.</div><div class='add'>+// Toggle BMCR_RESET bit off to accommodate broken AX8796B PHY implementation</div><div class='add'>+// such as used on the Individual Computers' X-Surf 100 Zorro card.</div><div class='add'>+fn asix_soft_reset(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+    dev.write(uapi::MII_BMCR as u16, 0)?;</div><div class='add'>+    dev.genphy_soft_reset()</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct PhyAX88772A;</div><div class='add'>+</div><div class='add'>+#[vtable]</div><div class='add'>+impl Driver for PhyAX88772A {</div><div class='add'>+    const FLAGS: u32 = phy::flags::IS_INTERNAL;</div><div class='add'>+    const NAME: &amp;'static CStr = c_str!("Asix Electronics AX88772A");</div><div class='add'>+    const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_exact_mask(0x003b1861);</div><div class='add'>+</div><div class='add'>+    // AX88772A is not working properly with some old switches (NETGEAR EN 108TP):</div><div class='add'>+    // after autoneg is done and the link status is reported as active, the MII_LPA</div><div class='add'>+    // register is 0. This issue is not reproducible on AX88772C.</div><div class='add'>+    fn read_status(dev: &amp;mut phy::Device) -&gt; Result&lt;u16&gt; {</div><div class='add'>+        dev.genphy_update_link()?;</div><div class='add'>+        if !dev.is_link_up() {</div><div class='add'>+            return Ok(0);</div><div class='add'>+        }</div><div class='add'>+        // If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve</div><div class='add'>+        // linkmode so use MII_BMCR as default values.</div><div class='add'>+        let ret = dev.read(MII_BMCR)?;</div><div class='add'>+</div><div class='add'>+        if ret &amp; BMCR_SPEED100 != 0 {</div><div class='add'>+            dev.set_speed(uapi::SPEED_100);</div><div class='add'>+        } else {</div><div class='add'>+            dev.set_speed(uapi::SPEED_10);</div><div class='add'>+        }</div><div class='add'>+</div><div class='add'>+        let duplex = if ret &amp; BMCR_FULLDPLX != 0 {</div><div class='add'>+            phy::DuplexMode::Full</div><div class='add'>+        } else {</div><div class='add'>+            phy::DuplexMode::Half</div><div class='add'>+        };</div><div class='add'>+        dev.set_duplex(duplex);</div><div class='add'>+</div><div class='add'>+        dev.genphy_read_lpa()?;</div><div class='add'>+</div><div class='add'>+        if dev.is_autoneg_enabled() &amp;&amp; dev.is_autoneg_completed() {</div><div class='add'>+            dev.resolve_aneg_linkmode();</div><div class='add'>+        }</div><div class='add'>+</div><div class='add'>+        Ok(0)</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn suspend(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        dev.genphy_suspend()</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn resume(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        dev.genphy_resume()</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn soft_reset(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        asix_soft_reset(dev)</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn link_change_notify(dev: &amp;mut phy::Device) {</div><div class='add'>+        // Reset PHY, otherwise MII_LPA will provide outdated information.</div><div class='add'>+        // This issue is reproducible only with some link partner PHYs.</div><div class='add'>+        if dev.state() == phy::DeviceState::NoLink {</div><div class='add'>+            let _ = dev.init_hw();</div><div class='add'>+            let _ = dev.start_aneg();</div><div class='add'>+        }</div><div class='add'>+    }</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct PhyAX88772C;</div><div class='add'>+</div><div class='add'>+#[vtable]</div><div class='add'>+impl Driver for PhyAX88772C {</div><div class='add'>+    const FLAGS: u32 = phy::flags::IS_INTERNAL;</div><div class='add'>+    const NAME: &amp;'static CStr = c_str!("Asix Electronics AX88772C");</div><div class='add'>+    const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_exact_mask(0x003b1881);</div><div class='add'>+</div><div class='add'>+    fn suspend(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        dev.genphy_suspend()</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn resume(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        dev.genphy_resume()</div><div class='add'>+    }</div><div class='add'>+</div><div class='add'>+    fn soft_reset(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        asix_soft_reset(dev)</div><div class='add'>+    }</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct PhyAX88796B;</div><div class='add'>+</div><div class='add'>+#[vtable]</div><div class='add'>+impl Driver for PhyAX88796B {</div><div class='add'>+    const NAME: &amp;'static CStr = c_str!("Asix Electronics AX88796B");</div><div class='add'>+    const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_model_mask(0x003b1841);</div><div class='add'>+</div><div class='add'>+    fn soft_reset(dev: &amp;mut phy::Device) -&gt; Result {</div><div class='add'>+        asix_soft_reset(dev)</div><div class='add'>+    }</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/phy/bcm-phy-ptp.c b/drivers/net/phy/bcm-phy-ptp.c<br/>index cb4b91af5e17..617d384d4551 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm-phy-ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/bcm-phy-ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm-phy-ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm-phy-ptp.c</a></div><div class='hunk'>@@ -782,16 +782,13 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bcm_ptp_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='del'>-			    struct ifreq *ifr)</div><div class='add'>+			    struct kernel_hwtstamp_config *cfg,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct bcm_ptp_private *priv = mii2priv(mii_ts);</div><div class='del'>-	struct hwtstamp_config cfg;</div><div class='ctx'> 	u16 mode, ctrl;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;cfg, ifr-&gt;ifr_data, sizeof(cfg)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	switch (cfg.rx_filter) {</div><div class='add'>+	switch (cfg-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		priv-&gt;hwts_rx = false;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -804,14 +801,14 @@ static int bcm_ptp_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_EVENT:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_SYNC:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;</div><div class='ctx'> 		priv-&gt;hwts_rx = true;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	priv-&gt;tx_type = cfg.tx_type;</div><div class='add'>+	priv-&gt;tx_type = cfg-&gt;tx_type;</div><div class='ctx'> </div><div class='ctx'> 	ctrl  = priv-&gt;hwts_rx ? SLICE_RX_EN : 0;</div><div class='ctx'> 	ctrl |= priv-&gt;tx_type != HWTSTAMP_TX_OFF ? SLICE_TX_EN : 0;</div><div class='hunk'>@@ -840,7 +837,7 @@ static int bcm_ptp_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='ctx'> 	/* purge existing data */</div><div class='ctx'> 	skb_queue_purge(&amp;priv-&gt;tx_queue);</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;cfg, sizeof(cfg)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int bcm_ptp_ts_info(struct mii_timestamper *mii_ts,</div><div class='head'>diff --git a/drivers/net/phy/bcm54140.c b/drivers/net/phy/bcm54140.c<br/>index d43076592f81..2eea3d09b1e6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm54140.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/bcm54140.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm54140.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm54140.c</a></div><div class='hunk'>@@ -128,6 +128,10 @@</div><div class='ctx'> #define BCM54140_DEFAULT_DOWNSHIFT 5</div><div class='ctx'> #define BCM54140_MAX_DOWNSHIFT 9</div><div class='ctx'> </div><div class='add'>+enum bcm54140_global_phy {</div><div class='add'>+	BCM54140_BASE_ADDR = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct bcm54140_priv {</div><div class='ctx'> 	int port;</div><div class='ctx'> 	int base_addr;</div><div class='hunk'>@@ -429,11 +433,13 @@ static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	phy_lock_mdio_bus(phydev);</div><div class='del'>-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);</div><div class='add'>+	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,</div><div class='add'>+				  MII_BCM54XX_RDB_ADDR, rdb);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);</div><div class='add'>+	ret = __phy_package_read(phydev, BCM54140_BASE_ADDR,</div><div class='add'>+				 MII_BCM54XX_RDB_DATA);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	phy_unlock_mdio_bus(phydev);</div><div class='hunk'>@@ -446,11 +452,13 @@ static int bcm54140_base_write_rdb(struct phy_device *phydev,</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	phy_lock_mdio_bus(phydev);</div><div class='del'>-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);</div><div class='add'>+	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,</div><div class='add'>+				  MII_BCM54XX_RDB_ADDR, rdb);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		goto out;</div><div class='ctx'> </div><div class='del'>-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);</div><div class='add'>+	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,</div><div class='add'>+				  MII_BCM54XX_RDB_DATA, val);</div><div class='ctx'> </div><div class='ctx'> out:</div><div class='ctx'> 	phy_unlock_mdio_bus(phydev);</div><div class='head'>diff --git a/drivers/net/phy/bcm84881.c b/drivers/net/phy/bcm84881.c<br/>index 9717a1626f3f..f1d47c264058 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm84881.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/bcm84881.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/bcm84881.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/bcm84881.c</a></div><div class='hunk'>@@ -29,8 +29,19 @@ static int bcm84881_wait_init(struct phy_device *phydev)</div><div class='ctx'> 					 100000, 2000000, false);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void bcm84881_fill_possible_interfaces(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	unsigned long *possible = phydev-&gt;possible_interfaces;</div><div class='add'>+</div><div class='add'>+	__set_bit(PHY_INTERFACE_MODE_SGMII, possible);</div><div class='add'>+	__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);</div><div class='add'>+	__set_bit(PHY_INTERFACE_MODE_10GBASER, possible);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int bcm84881_config_init(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='add'>+	bcm84881_fill_possible_interfaces(phydev);</div><div class='add'>+</div><div class='ctx'> 	switch (phydev-&gt;interface) {</div><div class='ctx'> 	case PHY_INTERFACE_MODE_SGMII:</div><div class='ctx'> 	case PHY_INTERFACE_MODE_2500BASEX:</div><div class='hunk'>@@ -39,6 +50,7 @@ static int bcm84881_config_init(struct phy_device *phydev)</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c<br/>index 3a627105675a..312a8bb35d78 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/broadcom.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/broadcom.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/broadcom.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/broadcom.c</a></div><div class='hunk'>@@ -1135,6 +1135,8 @@ static struct phy_driver broadcom_drivers[] = {</div><div class='ctx'> 	.handle_interrupt = bcm_phy_handle_interrupt,</div><div class='ctx'> 	.link_change_notify	= bcm54xx_link_change_notify,</div><div class='ctx'> 	.led_brightness_set	= bcm_phy_led_brightness_set,</div><div class='add'>+	.suspend	= bcm54xx_suspend,</div><div class='add'>+	.resume		= bcm54xx_resume,</div><div class='ctx'> }, {</div><div class='ctx'> 	.phy_id		= PHY_ID_BCM54616S,</div><div class='ctx'> 	.phy_id_mask	= 0xfffffff0,</div><div class='head'>diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c<br/>index 2657be7cc049..5c42c47dc564 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/dp83640.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/dp83640.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/dp83640.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/dp83640.c</a></div><div class='hunk'>@@ -1207,22 +1207,20 @@ static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)</div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='add'>+static int dp83640_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='add'>+			    struct kernel_hwtstamp_config *cfg,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct dp83640_private *dp83640 =</div><div class='ctx'> 		container_of(mii_ts, struct dp83640_private, mii_ts);</div><div class='del'>-	struct hwtstamp_config cfg;</div><div class='ctx'> 	u16 txcfg0, rxcfg0;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;cfg, ifr-&gt;ifr_data, sizeof(cfg)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	if (cfg.tx_type &lt; 0 || cfg.tx_type &gt; HWTSTAMP_TX_ONESTEP_SYNC)</div><div class='add'>+	if (cfg-&gt;tx_type &lt; 0 || cfg-&gt;tx_type &gt; HWTSTAMP_TX_ONESTEP_SYNC)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> </div><div class='del'>-	dp83640-&gt;hwts_tx_en = cfg.tx_type;</div><div class='add'>+	dp83640-&gt;hwts_tx_en = cfg-&gt;tx_type;</div><div class='ctx'> </div><div class='del'>-	switch (cfg.rx_filter) {</div><div class='add'>+	switch (cfg-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		dp83640-&gt;hwts_rx_en = 0;</div><div class='ctx'> 		dp83640-&gt;layer = 0;</div><div class='hunk'>@@ -1234,7 +1232,7 @@ static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		dp83640-&gt;hwts_rx_en = 1;</div><div class='ctx'> 		dp83640-&gt;layer = PTP_CLASS_L4;</div><div class='ctx'> 		dp83640-&gt;version = PTP_CLASS_V1;</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:</div><div class='hunk'>@@ -1242,7 +1240,7 @@ static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		dp83640-&gt;hwts_rx_en = 1;</div><div class='ctx'> 		dp83640-&gt;layer = PTP_CLASS_L4;</div><div class='ctx'> 		dp83640-&gt;version = PTP_CLASS_V2;</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:</div><div class='hunk'>@@ -1250,7 +1248,7 @@ static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		dp83640-&gt;hwts_rx_en = 1;</div><div class='ctx'> 		dp83640-&gt;layer = PTP_CLASS_L2;</div><div class='ctx'> 		dp83640-&gt;version = PTP_CLASS_V2;</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_EVENT:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_SYNC:</div><div class='hunk'>@@ -1258,7 +1256,7 @@ static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		dp83640-&gt;hwts_rx_en = 1;</div><div class='ctx'> 		dp83640-&gt;layer = PTP_CLASS_L4 | PTP_CLASS_L2;</div><div class='ctx'> 		dp83640-&gt;version = PTP_CLASS_V2;</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ERANGE;</div><div class='hunk'>@@ -1292,7 +1290,7 @@ static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;dp83640-&gt;clock-&gt;extreg_lock);</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;cfg, sizeof(cfg)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void rx_timestamp_work(struct work_struct *work)</div><div class='head'>diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c<br/>new file mode 100644<br/>index 000000000000..326c9770a6dc<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/dp83tg720.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/dp83tg720.c</a></div><div class='hunk'>@@ -0,0 +1,188 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* Driver for the Texas Instruments DP83TG720 PHY</div><div class='add'>+ * Copyright (c) 2023 Pengutronix, Oleksij Rempel &lt;kernel@pengutronix.de&gt;</div><div class='add'>+ */</div><div class='add'>+#include &lt;linux/bitfield.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/phy.h&gt;</div><div class='add'>+</div><div class='add'>+#define DP83TG720S_PHY_ID			0x2000a284</div><div class='add'>+</div><div class='add'>+/* MDIO_MMD_VEND2 registers */</div><div class='add'>+#define DP83TG720S_MII_REG_10			0x10</div><div class='add'>+#define DP83TG720S_STS_MII_INT			BIT(7)</div><div class='add'>+#define DP83TG720S_LINK_STATUS			BIT(0)</div><div class='add'>+</div><div class='add'>+#define DP83TG720S_PHY_RESET			0x1f</div><div class='add'>+#define DP83TG720S_HW_RESET			BIT(15)</div><div class='add'>+</div><div class='add'>+#define DP83TG720S_RGMII_DELAY_CTRL		0x602</div><div class='add'>+/* In RGMII mode, Enable or disable the internal delay for RXD */</div><div class='add'>+#define DP83TG720S_RGMII_RX_CLK_SEL		BIT(1)</div><div class='add'>+/* In RGMII mode, Enable or disable the internal delay for TXD */</div><div class='add'>+#define DP83TG720S_RGMII_TX_CLK_SEL		BIT(0)</div><div class='add'>+</div><div class='add'>+#define DP83TG720S_SQI_REG_1			0x871</div><div class='add'>+#define DP83TG720S_SQI_OUT_WORST		GENMASK(7, 5)</div><div class='add'>+#define DP83TG720S_SQI_OUT			GENMASK(3, 1)</div><div class='add'>+</div><div class='add'>+#define DP83TG720_SQI_MAX			7</div><div class='add'>+</div><div class='add'>+static int dp83tg720_config_aneg(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	/* Autoneg is not supported and this PHY supports only one speed.</div><div class='add'>+	 * We need to care only about master/slave configuration if it was</div><div class='add'>+	 * changed by user.</div><div class='add'>+	 */</div><div class='add'>+	return genphy_c45_pma_baset1_setup_master_slave(phydev);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp83tg720_read_status(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	u16 phy_sts;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	phydev-&gt;pause = 0;</div><div class='add'>+	phydev-&gt;asym_pause = 0;</div><div class='add'>+</div><div class='add'>+	/* Most of Clause 45 registers are not present, so we can't use</div><div class='add'>+	 * genphy_c45_read_status() here.</div><div class='add'>+	 */</div><div class='add'>+	phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10);</div><div class='add'>+	phydev-&gt;link = !!(phy_sts &amp; DP83TG720S_LINK_STATUS);</div><div class='add'>+	if (!phydev-&gt;link) {</div><div class='add'>+		/* According to the "DP83TC81x, DP83TG72x Software</div><div class='add'>+		 * Implementation Guide", the PHY needs to be reset after a</div><div class='add'>+		 * link loss or if no link is created after at least 100ms.</div><div class='add'>+		 *</div><div class='add'>+		 * Currently we are polling with the PHY_STATE_TIME (1000ms)</div><div class='add'>+		 * interval, which is still enough for not automotive use cases.</div><div class='add'>+		 */</div><div class='add'>+		ret = phy_init_hw(phydev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		/* After HW reset we need to restore master/slave configuration.</div><div class='add'>+		 */</div><div class='add'>+		ret = dp83tg720_config_aneg(phydev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		phydev-&gt;speed = SPEED_UNKNOWN;</div><div class='add'>+		phydev-&gt;duplex = DUPLEX_UNKNOWN;</div><div class='add'>+	} else {</div><div class='add'>+		/* PMA/PMD control 1 register (Register 1.0) is present, but it</div><div class='add'>+		 * doesn't contain the link speed information.</div><div class='add'>+		 * So genphy_c45_read_pma() can't be used here.</div><div class='add'>+		 */</div><div class='add'>+		ret = genphy_c45_pma_baset1_read_master_slave(phydev);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='add'>+		phydev-&gt;duplex = DUPLEX_FULL;</div><div class='add'>+		phydev-&gt;speed = SPEED_1000;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp83tg720_get_sqi(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!phydev-&gt;link)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return FIELD_GET(DP83TG720S_SQI_OUT, ret);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp83tg720_get_sqi_max(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	return DP83TG720_SQI_MAX;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	u16 rgmii_delay_mask;</div><div class='add'>+	u16 rgmii_delay = 0;</div><div class='add'>+</div><div class='add'>+	switch (phydev-&gt;interface) {</div><div class='add'>+	case PHY_INTERFACE_MODE_RGMII:</div><div class='add'>+		rgmii_delay = 0;</div><div class='add'>+		break;</div><div class='add'>+	case PHY_INTERFACE_MODE_RGMII_ID:</div><div class='add'>+		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL |</div><div class='add'>+				DP83TG720S_RGMII_TX_CLK_SEL;</div><div class='add'>+		break;</div><div class='add'>+	case PHY_INTERFACE_MODE_RGMII_RXID:</div><div class='add'>+		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL;</div><div class='add'>+		break;</div><div class='add'>+	case PHY_INTERFACE_MODE_RGMII_TXID:</div><div class='add'>+		rgmii_delay = DP83TG720S_RGMII_TX_CLK_SEL;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rgmii_delay_mask = DP83TG720S_RGMII_RX_CLK_SEL |</div><div class='add'>+		DP83TG720S_RGMII_TX_CLK_SEL;</div><div class='add'>+</div><div class='add'>+	return phy_modify_mmd(phydev, MDIO_MMD_VEND2,</div><div class='add'>+			      DP83TG720S_RGMII_DELAY_CTRL, rgmii_delay_mask,</div><div class='add'>+			      rgmii_delay);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int dp83tg720_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Software Restart is not enough to recover from a link failure.</div><div class='add'>+	 * Using Hardware Reset instead.</div><div class='add'>+	 */</div><div class='add'>+	ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Wait until MDC can be used again.</div><div class='add'>+	 * The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1</div><div class='add'>+	 * Automotive Ethernet PHY with SGMII and RGMII" datasheet.</div><div class='add'>+	 */</div><div class='add'>+	usleep_range(1000, 2000);</div><div class='add'>+</div><div class='add'>+	if (phy_interface_is_rgmii(phydev))</div><div class='add'>+		return dp83tg720_config_rgmii_delay(phydev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct phy_driver dp83tg720_driver[] = {</div><div class='add'>+{</div><div class='add'>+	PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID),</div><div class='add'>+	.name		= "TI DP83TG720S",</div><div class='add'>+</div><div class='add'>+	.config_aneg	= dp83tg720_config_aneg,</div><div class='add'>+	.read_status	= dp83tg720_read_status,</div><div class='add'>+	.get_features	= genphy_c45_pma_read_ext_abilities,</div><div class='add'>+	.config_init	= dp83tg720_config_init,</div><div class='add'>+	.get_sqi	= dp83tg720_get_sqi,</div><div class='add'>+	.get_sqi_max	= dp83tg720_get_sqi_max,</div><div class='add'>+</div><div class='add'>+	.suspend	= genphy_suspend,</div><div class='add'>+	.resume		= genphy_resume,</div><div class='add'>+} };</div><div class='add'>+module_phy_driver(dp83tg720_driver);</div><div class='add'>+</div><div class='add'>+static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {</div><div class='add'>+	{ PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) },</div><div class='add'>+	{ }</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl);</div><div class='add'>+</div><div class='add'>+MODULE_DESCRIPTION("Texas Instruments DP83TG720S PHY driver");</div><div class='add'>+MODULE_AUTHOR("Oleksij Rempel &lt;kernel@pengutronix.de&gt;");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c<br/>index d4bb90d76881..ad43e280930c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/marvell10g.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/marvell10g.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/marvell10g.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/marvell10g.c</a></div><div class='hunk'>@@ -141,13 +141,21 @@ enum {</div><div class='ctx'> 	MV_V2_TEMP_UNKNOWN	= 0x9600, /* unknown function */</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct mv3310_mactype {</div><div class='add'>+	bool valid;</div><div class='add'>+	bool fixed_interface;</div><div class='add'>+	phy_interface_t interface_10g;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct mv3310_chip {</div><div class='ctx'> 	bool (*has_downshift)(struct phy_device *phydev);</div><div class='ctx'> 	void (*init_supported_interfaces)(unsigned long *mask);</div><div class='ctx'> 	int (*get_mactype)(struct phy_device *phydev);</div><div class='ctx'> 	int (*set_mactype)(struct phy_device *phydev, int mactype);</div><div class='ctx'> 	int (*select_mactype)(unsigned long *interfaces);</div><div class='del'>-	int (*init_interface)(struct phy_device *phydev, int mactype);</div><div class='add'>+</div><div class='add'>+	const struct mv3310_mactype *mactypes;</div><div class='add'>+	size_t n_mactypes;</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_HWMON</div><div class='ctx'> 	int (*hwmon_read_temp_reg)(struct phy_device *phydev);</div><div class='hunk'>@@ -156,11 +164,10 @@ struct mv3310_chip {</div><div class='ctx'> </div><div class='ctx'> struct mv3310_priv {</div><div class='ctx'> 	DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);</div><div class='add'>+	const struct mv3310_mactype *mactype;</div><div class='ctx'> </div><div class='ctx'> 	u32 firmware_ver;</div><div class='ctx'> 	bool has_downshift;</div><div class='del'>-	bool rate_match;</div><div class='del'>-	phy_interface_t const_interface;</div><div class='ctx'> </div><div class='ctx'> 	struct device *hwmon_dev;</div><div class='ctx'> 	char *hwmon_name;</div><div class='hunk'>@@ -702,70 +709,114 @@ static int mv3310_select_mactype(unsigned long *interfaces)</div><div class='ctx'> 		return -1;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int mv2110_init_interface(struct phy_device *phydev, int mactype)</div><div class='del'>-{</div><div class='del'>-	struct mv3310_priv *priv = dev_get_drvdata(&amp;phydev-&gt;mdio.dev);</div><div class='del'>-</div><div class='del'>-	priv-&gt;rate_match = false;</div><div class='del'>-</div><div class='del'>-	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)</div><div class='del'>-		priv-&gt;rate_match = true;</div><div class='del'>-</div><div class='del'>-	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_USXGMII;</div><div class='del'>-	else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_10GBASER;</div><div class='del'>-	else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||</div><div class='del'>-		 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_NA;</div><div class='del'>-	else</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int mv3310_init_interface(struct phy_device *phydev, int mactype)</div><div class='del'>-{</div><div class='del'>-	struct mv3310_priv *priv = dev_get_drvdata(&amp;phydev-&gt;mdio.dev);</div><div class='add'>+static const struct mv3310_mactype mv2110_mactypes[] = {</div><div class='add'>+	[MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_USXGMII,</div><div class='add'>+	},</div><div class='add'>+	[MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_NA,</div><div class='add'>+	},</div><div class='add'>+	[MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_NA,</div><div class='add'>+	},</div><div class='add'>+	[MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	priv-&gt;rate_match = false;</div><div class='del'>-</div><div class='del'>-	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||</div><div class='del'>-	    mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||</div><div class='del'>-	    mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)</div><div class='del'>-		priv-&gt;rate_match = true;</div><div class='del'>-</div><div class='del'>-	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_USXGMII;</div><div class='del'>-	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||</div><div class='del'>-		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||</div><div class='del'>-		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_10GBASER;</div><div class='del'>-	else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||</div><div class='del'>-		 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_RXAUI;</div><div class='del'>-	else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||</div><div class='del'>-		 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_XAUI;</div><div class='del'>-	else</div><div class='del'>-		return -EINVAL;</div><div class='add'>+static const struct mv3310_mactype mv3310_mactypes[] = {</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_RXAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_XAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_RXAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_3310_PORT_CTRL_MACTYPE_XAUI] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_XAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_USXGMII,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='add'>+static const struct mv3310_mactype mv3340_mactypes[] = {</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_RXAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_RXAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_RXAUI,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	},</div><div class='add'>+	[MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII] = {</div><div class='add'>+		.valid = true,</div><div class='add'>+		.fixed_interface = true,</div><div class='add'>+		.interface_10g = PHY_INTERFACE_MODE_USXGMII,</div><div class='add'>+	},</div><div class='add'>+};</div><div class='ctx'> </div><div class='del'>-static int mv3340_init_interface(struct phy_device *phydev, int mactype)</div><div class='add'>+static void mv3310_fill_possible_interfaces(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	struct mv3310_priv *priv = dev_get_drvdata(&amp;phydev-&gt;mdio.dev);</div><div class='del'>-	int err = 0;</div><div class='del'>-</div><div class='del'>-	priv-&gt;rate_match = false;</div><div class='add'>+	unsigned long *possible = phydev-&gt;possible_interfaces;</div><div class='add'>+	const struct mv3310_mactype *mactype = priv-&gt;mactype;</div><div class='ctx'> </div><div class='del'>-	if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)</div><div class='del'>-		priv-&gt;const_interface = PHY_INTERFACE_MODE_RXAUI;</div><div class='del'>-	else</div><div class='del'>-		err = mv3310_init_interface(phydev, mactype);</div><div class='add'>+	if (mactype-&gt;interface_10g != PHY_INTERFACE_MODE_NA)</div><div class='add'>+		__set_bit(priv-&gt;mactype-&gt;interface_10g, possible);</div><div class='ctx'> </div><div class='del'>-	return err;</div><div class='add'>+	if (!mactype-&gt;fixed_interface) {</div><div class='add'>+		__set_bit(PHY_INTERFACE_MODE_5GBASER, possible);</div><div class='add'>+		__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);</div><div class='add'>+		__set_bit(PHY_INTERFACE_MODE_SGMII, possible);</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int mv3310_config_init(struct phy_device *phydev)</div><div class='hunk'>@@ -803,12 +854,15 @@ static int mv3310_config_init(struct phy_device *phydev)</div><div class='ctx'> 	if (mactype &lt; 0)</div><div class='ctx'> 		return mactype;</div><div class='ctx'> </div><div class='del'>-	err = chip-&gt;init_interface(phydev, mactype);</div><div class='del'>-	if (err) {</div><div class='add'>+	if (mactype &gt;= chip-&gt;n_mactypes || !chip-&gt;mactypes[mactype].valid) {</div><div class='ctx'> 		phydev_err(phydev, "MACTYPE configuration invalid\n");</div><div class='del'>-		return err;</div><div class='add'>+		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	priv-&gt;mactype = &amp;chip-&gt;mactypes[mactype];</div><div class='add'>+</div><div class='add'>+	mv3310_fill_possible_interfaces(phydev);</div><div class='add'>+</div><div class='ctx'> 	/* Enable EDPD mode - saving 600mW */</div><div class='ctx'> 	err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);</div><div class='ctx'> 	if (err)</div><div class='hunk'>@@ -935,9 +989,8 @@ static void mv3310_update_interface(struct phy_device *phydev)</div><div class='ctx'> 	 *</div><div class='ctx'> 	 * In USXGMII mode the PHY interface mode is also fixed.</div><div class='ctx'> 	 */</div><div class='del'>-	if (priv-&gt;rate_match ||</div><div class='del'>-	    priv-&gt;const_interface == PHY_INTERFACE_MODE_USXGMII) {</div><div class='del'>-		phydev-&gt;interface = priv-&gt;const_interface;</div><div class='add'>+	if (priv-&gt;mactype-&gt;fixed_interface) {</div><div class='add'>+		phydev-&gt;interface = priv-&gt;mactype-&gt;interface_10g;</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -949,7 +1002,7 @@ static void mv3310_update_interface(struct phy_device *phydev)</div><div class='ctx'> 	 */</div><div class='ctx'> 	switch (phydev-&gt;speed) {</div><div class='ctx'> 	case SPEED_10000:</div><div class='del'>-		phydev-&gt;interface = priv-&gt;const_interface;</div><div class='add'>+		phydev-&gt;interface = priv-&gt;mactype-&gt;interface_10g;</div><div class='ctx'> 		break;</div><div class='ctx'> 	case SPEED_5000:</div><div class='ctx'> 		phydev-&gt;interface = PHY_INTERFACE_MODE_5GBASER;</div><div class='hunk'>@@ -1163,7 +1216,9 @@ static const struct mv3310_chip mv3310_type = {</div><div class='ctx'> 	.get_mactype = mv3310_get_mactype,</div><div class='ctx'> 	.set_mactype = mv3310_set_mactype,</div><div class='ctx'> 	.select_mactype = mv3310_select_mactype,</div><div class='del'>-	.init_interface = mv3310_init_interface,</div><div class='add'>+</div><div class='add'>+	.mactypes = mv3310_mactypes,</div><div class='add'>+	.n_mactypes = ARRAY_SIZE(mv3310_mactypes),</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_HWMON</div><div class='ctx'> 	.hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,</div><div class='hunk'>@@ -1176,7 +1231,9 @@ static const struct mv3310_chip mv3340_type = {</div><div class='ctx'> 	.get_mactype = mv3310_get_mactype,</div><div class='ctx'> 	.set_mactype = mv3310_set_mactype,</div><div class='ctx'> 	.select_mactype = mv3310_select_mactype,</div><div class='del'>-	.init_interface = mv3340_init_interface,</div><div class='add'>+</div><div class='add'>+	.mactypes = mv3340_mactypes,</div><div class='add'>+	.n_mactypes = ARRAY_SIZE(mv3340_mactypes),</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_HWMON</div><div class='ctx'> 	.hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,</div><div class='hunk'>@@ -1188,7 +1245,9 @@ static const struct mv3310_chip mv2110_type = {</div><div class='ctx'> 	.get_mactype = mv2110_get_mactype,</div><div class='ctx'> 	.set_mactype = mv2110_set_mactype,</div><div class='ctx'> 	.select_mactype = mv2110_select_mactype,</div><div class='del'>-	.init_interface = mv2110_init_interface,</div><div class='add'>+</div><div class='add'>+	.mactypes = mv2110_mactypes,</div><div class='add'>+	.n_mactypes = ARRAY_SIZE(mv2110_mactypes),</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_HWMON</div><div class='ctx'> 	.hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,</div><div class='hunk'>@@ -1200,7 +1259,9 @@ static const struct mv3310_chip mv2111_type = {</div><div class='ctx'> 	.get_mactype = mv2110_get_mactype,</div><div class='ctx'> 	.set_mactype = mv2110_set_mactype,</div><div class='ctx'> 	.select_mactype = mv2110_select_mactype,</div><div class='del'>-	.init_interface = mv2110_init_interface,</div><div class='add'>+</div><div class='add'>+	.mactypes = mv2110_mactypes,</div><div class='add'>+	.n_mactypes = ARRAY_SIZE(mv2110_mactypes),</div><div class='ctx'> </div><div class='ctx'> #ifdef CONFIG_HWMON</div><div class='ctx'> 	.hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,</div><div class='head'>diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c<br/>index 25dcaa49ab8b..afbad1ad8683 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/mdio_bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/mdio_bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/mdio_bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mdio_bus.c</a></div><div class='hunk'>@@ -193,6 +193,10 @@ static void mdiobus_release(struct device *d)</div><div class='ctx'> 	     bus-&gt;state != MDIOBUS_ALLOCATED,</div><div class='ctx'> 	     "%s: not in RELEASED or ALLOCATED state\n",</div><div class='ctx'> 	     bus-&gt;id);</div><div class='add'>+</div><div class='add'>+	if (bus-&gt;state == MDIOBUS_RELEASED)</div><div class='add'>+		fwnode_handle_put(dev_fwnode(d));</div><div class='add'>+</div><div class='ctx'> 	kfree(bus);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -506,7 +510,7 @@ static int mdiobus_create_device(struct mii_bus *bus,</div><div class='ctx'> 	if (IS_ERR(mdiodev))</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	strncpy(mdiodev-&gt;modalias, bi-&gt;modalias,</div><div class='add'>+	strscpy(mdiodev-&gt;modalias, bi-&gt;modalias,</div><div class='ctx'> 		sizeof(mdiodev-&gt;modalias));</div><div class='ctx'> 	mdiodev-&gt;bus_match = mdio_device_bus_match;</div><div class='ctx'> 	mdiodev-&gt;dev.platform_data = (void *)bi-&gt;platform_data;</div><div class='hunk'>@@ -684,6 +688,15 @@ int __mdiobus_register(struct mii_bus *bus, struct module *owner)</div><div class='ctx'> 	bus-&gt;dev.groups = NULL;</div><div class='ctx'> 	dev_set_name(&amp;bus-&gt;dev, "%s", bus-&gt;id);</div><div class='ctx'> </div><div class='add'>+	/* If the bus state is allocated, we're registering a fresh bus</div><div class='add'>+	 * that may have a fwnode associated with it. Grab a reference</div><div class='add'>+	 * to the fwnode. This will be dropped when the bus is released.</div><div class='add'>+	 * If the bus was set to unregistered, it means that the bus was</div><div class='add'>+	 * previously registered, and we've already grabbed a reference.</div><div class='add'>+	 */</div><div class='add'>+	if (bus-&gt;state == MDIOBUS_ALLOCATED)</div><div class='add'>+		fwnode_handle_get(dev_fwnode(&amp;bus-&gt;dev));</div><div class='add'>+</div><div class='ctx'> 	/* We need to set state to MDIOBUS_UNREGISTERED to correctly release</div><div class='ctx'> 	 * the device in mdiobus_free()</div><div class='ctx'> 	 *</div><div class='head'>diff --git a/drivers/net/phy/mdio_device.c b/drivers/net/phy/mdio_device.c<br/>index 044828d081d2..73f6539b9e50 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/mdio_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/mdio_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/mdio_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mdio_device.c</a></div><div class='hunk'>@@ -62,6 +62,7 @@ struct mdio_device *mdio_device_create(struct mii_bus *bus, int addr)</div><div class='ctx'> 	mdiodev-&gt;device_remove = mdio_device_remove;</div><div class='ctx'> 	mdiodev-&gt;bus = bus;</div><div class='ctx'> 	mdiodev-&gt;addr = addr;</div><div class='add'>+	mdiodev-&gt;reset_state = -1;</div><div class='ctx'> </div><div class='ctx'> 	dev_set_name(&amp;mdiodev-&gt;dev, PHY_ID_FMT, bus-&gt;id, addr);</div><div class='ctx'> </div><div class='hunk'>@@ -122,6 +123,9 @@ void mdio_device_reset(struct mdio_device *mdiodev, int value)</div><div class='ctx'> 	if (!mdiodev-&gt;reset_gpio &amp;&amp; !mdiodev-&gt;reset_ctrl)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='add'>+	if (mdiodev-&gt;reset_state == value)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	if (mdiodev-&gt;reset_gpio)</div><div class='ctx'> 		gpiod_set_value_cansleep(mdiodev-&gt;reset_gpio, value);</div><div class='ctx'> </div><div class='hunk'>@@ -135,6 +139,8 @@ void mdio_device_reset(struct mdio_device *mdiodev, int value)</div><div class='ctx'> 	d = value ? mdiodev-&gt;reset_assert_delay : mdiodev-&gt;reset_deassert_delay;</div><div class='ctx'> 	if (d)</div><div class='ctx'> 		fsleep(d);</div><div class='add'>+</div><div class='add'>+	mdiodev-&gt;reset_state = value;</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(mdio_device_reset);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c<br/>index 08e3915001c3..81c20eb4b54b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/micrel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/micrel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/micrel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/micrel.c</a></div><div class='hunk'>@@ -2001,7 +2001,7 @@ static int kszphy_probe(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	kszphy_parse_led_mode(phydev);</div><div class='ctx'> </div><div class='del'>-	clk = devm_clk_get(&amp;phydev-&gt;mdio.dev, "rmii-ref");</div><div class='add'>+	clk = devm_clk_get_optional_enabled(&amp;phydev-&gt;mdio.dev, "rmii-ref");</div><div class='ctx'> 	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */</div><div class='ctx'> 	if (!IS_ERR_OR_NULL(clk)) {</div><div class='ctx'> 		unsigned long rate = clk_get_rate(clk);</div><div class='hunk'>@@ -2021,6 +2021,11 @@ static int kszphy_probe(struct phy_device *phydev)</div><div class='ctx'> 				   rate);</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='add'>+	} else if (!clk) {</div><div class='add'>+		/* unnamed clock from the generic ethernet-phy binding */</div><div class='add'>+		clk = devm_clk_get_optional_enabled(&amp;phydev-&gt;mdio.dev, NULL);</div><div class='add'>+		if (IS_ERR(clk))</div><div class='add'>+			return PTR_ERR(clk);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ksz8041_fiber_mode(phydev))</div><div class='hunk'>@@ -2395,24 +2400,22 @@ static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)</div><div class='ctx'> 	lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='add'>+static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='add'>+			    struct kernel_hwtstamp_config *config,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct kszphy_ptp_priv *ptp_priv =</div><div class='ctx'> 			  container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);</div><div class='ctx'> 	struct phy_device *phydev = ptp_priv-&gt;phydev;</div><div class='ctx'> 	struct lan8814_shared_priv *shared = phydev-&gt;shared-&gt;priv;</div><div class='ctx'> 	struct lan8814_ptp_rx_ts *rx_ts, *tmp;</div><div class='del'>-	struct hwtstamp_config config;</div><div class='ctx'> 	int txcfg = 0, rxcfg = 0;</div><div class='ctx'> 	int pkt_ts_enable;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;config, ifr-&gt;ifr_data, sizeof(config)))</div><div class='del'>-		return -EFAULT;</div><div class='add'>+	ptp_priv-&gt;hwts_tx_type = config-&gt;tx_type;</div><div class='add'>+	ptp_priv-&gt;rx_filter = config-&gt;rx_filter;</div><div class='ctx'> </div><div class='del'>-	ptp_priv-&gt;hwts_tx_type = config.tx_type;</div><div class='del'>-	ptp_priv-&gt;rx_filter = config.rx_filter;</div><div class='del'>-</div><div class='del'>-	switch (config.rx_filter) {</div><div class='add'>+	switch (config-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		ptp_priv-&gt;layer = 0;</div><div class='ctx'> 		ptp_priv-&gt;version = 0;</div><div class='hunk'>@@ -2458,13 +2461,13 @@ static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		lanphy_write_page_reg(ptp_priv-&gt;phydev, 5, PTP_TX_MOD,</div><div class='ctx'> 				      PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);</div><div class='ctx'> </div><div class='del'>-	if (config.rx_filter != HWTSTAMP_FILTER_NONE)</div><div class='add'>+	if (config-&gt;rx_filter != HWTSTAMP_FILTER_NONE)</div><div class='ctx'> 		lan8814_config_ts_intr(ptp_priv-&gt;phydev, true);</div><div class='ctx'> 	else</div><div class='ctx'> 		lan8814_config_ts_intr(ptp_priv-&gt;phydev, false);</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;shared-&gt;shared_lock);</div><div class='del'>-	if (config.rx_filter != HWTSTAMP_FILTER_NONE)</div><div class='add'>+	if (config-&gt;rx_filter != HWTSTAMP_FILTER_NONE)</div><div class='ctx'> 		shared-&gt;ref++;</div><div class='ctx'> 	else</div><div class='ctx'> 		shared-&gt;ref--;</div><div class='hunk'>@@ -2488,7 +2491,7 @@ static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 	lan8814_flush_fifo(ptp_priv-&gt;phydev, false);</div><div class='ctx'> 	lan8814_flush_fifo(ptp_priv-&gt;phydev, true);</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;config, sizeof(config)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void lan8814_txtstamp(struct mii_timestamper *mii_ts,</div><div class='hunk'>@@ -3335,8 +3338,10 @@ static int lan8814_probe(struct phy_device *phydev)</div><div class='ctx'> #define LAN8841_ADC_CHANNEL_MASK		198</div><div class='ctx'> #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN		370</div><div class='ctx'> #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN		371</div><div class='add'>+#define LAN8841_PTP_RX_VERSION			374</div><div class='ctx'> #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN		434</div><div class='ctx'> #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN		435</div><div class='add'>+#define LAN8841_PTP_TX_VERSION			438</div><div class='ctx'> #define LAN8841_PTP_CMD_CTL			256</div><div class='ctx'> #define LAN8841_PTP_CMD_CTL_PTP_ENABLE		BIT(2)</div><div class='ctx'> #define LAN8841_PTP_CMD_CTL_PTP_DISABLE		BIT(1)</div><div class='hunk'>@@ -3380,6 +3385,12 @@ static int lan8841_config_init(struct phy_device *phydev)</div><div class='ctx'> 	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,</div><div class='ctx'> 		      LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);</div><div class='ctx'> </div><div class='add'>+	/* Disable checking for minorVersionPTP field */</div><div class='add'>+	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,</div><div class='add'>+		      LAN8841_PTP_RX_VERSION, 0xff00);</div><div class='add'>+	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,</div><div class='add'>+		      LAN8841_PTP_TX_VERSION, 0xff00);</div><div class='add'>+</div><div class='ctx'> 	/* 100BT Clause 40 improvenent errata */</div><div class='ctx'> 	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,</div><div class='ctx'> 		      LAN8841_ANALOG_CONTROL_1,</div><div class='hunk'>@@ -3631,12 +3642,8 @@ static int lan8841_ts_info(struct mii_timestamper *mii_ts,</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;phc_index = ptp_priv-&gt;ptp_clock ?</div><div class='ctx'> 				ptp_clock_index(ptp_priv-&gt;ptp_clock) : -1;</div><div class='del'>-	if (info-&gt;phc_index == -1) {</div><div class='del'>-		info-&gt;so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |</div><div class='del'>-					 SOF_TIMESTAMPING_RX_SOFTWARE |</div><div class='del'>-					 SOF_TIMESTAMPING_SOFTWARE;</div><div class='add'>+	if (info-&gt;phc_index == -1)</div><div class='ctx'> 		return 0;</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	info-&gt;so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |</div><div class='ctx'> 				SOF_TIMESTAMPING_RX_HARDWARE |</div><div class='hunk'>@@ -3703,21 +3710,19 @@ static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,</div><div class='ctx'> #define LAN8841_PTP_TX_TIMESTAMP_EN		443</div><div class='ctx'> #define LAN8841_PTP_TX_MOD			445</div><div class='ctx'> </div><div class='del'>-static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='add'>+static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='add'>+			    struct kernel_hwtstamp_config *config,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);</div><div class='ctx'> 	struct phy_device *phydev = ptp_priv-&gt;phydev;</div><div class='del'>-	struct hwtstamp_config config;</div><div class='ctx'> 	int txcfg = 0, rxcfg = 0;</div><div class='ctx'> 	int pkt_ts_enable;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;config, ifr-&gt;ifr_data, sizeof(config)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	ptp_priv-&gt;hwts_tx_type = config.tx_type;</div><div class='del'>-	ptp_priv-&gt;rx_filter = config.rx_filter;</div><div class='add'>+	ptp_priv-&gt;hwts_tx_type = config-&gt;tx_type;</div><div class='add'>+	ptp_priv-&gt;rx_filter = config-&gt;rx_filter;</div><div class='ctx'> </div><div class='del'>-	switch (config.rx_filter) {</div><div class='add'>+	switch (config-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		ptp_priv-&gt;layer = 0;</div><div class='ctx'> 		ptp_priv-&gt;version = 0;</div><div class='hunk'>@@ -3771,13 +3776,13 @@ static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> </div><div class='ctx'> 	/* Now enable/disable the timestamping */</div><div class='ctx'> 	lan8841_ptp_enable_processing(ptp_priv,</div><div class='del'>-				      config.rx_filter != HWTSTAMP_FILTER_NONE);</div><div class='add'>+				      config-&gt;rx_filter != HWTSTAMP_FILTER_NONE);</div><div class='ctx'> </div><div class='ctx'> 	skb_queue_purge(&amp;ptp_priv-&gt;tx_queue);</div><div class='ctx'> </div><div class='ctx'> 	lan8841_ptp_flush_fifo(ptp_priv);</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;config, sizeof(config)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,</div><div class='hunk'>@@ -4842,6 +4847,7 @@ static struct phy_driver ksphy_driver[] = {</div><div class='ctx'> 	.flags		= PHY_POLL_CABLE_TEST,</div><div class='ctx'> 	.driver_data	= &amp;ksz9131_type,</div><div class='ctx'> 	.probe		= kszphy_probe,</div><div class='add'>+	.soft_reset	= genphy_soft_reset,</div><div class='ctx'> 	.config_init	= ksz9131_config_init,</div><div class='ctx'> 	.config_intr	= kszphy_config_intr,</div><div class='ctx'> 	.config_aneg	= ksz9131_config_aneg,</div><div class='head'>diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h<br/>index 7a962050a4d4..6a3d8a754eb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/mscc/mscc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc.h</a></div><div class='hunk'>@@ -416,6 +416,11 @@ struct vsc8531_private {</div><div class='ctx'>  * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO</div><div class='ctx'>  * is shared.</div><div class='ctx'>  */</div><div class='add'>+</div><div class='add'>+enum vsc85xx_global_phy {</div><div class='add'>+	VSC88XX_BASE_ADDR = 0,</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> struct vsc85xx_shared_private {</div><div class='ctx'> 	struct mutex gpio_lock;</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c<br/>index 4171f01d34e5..6f74ce0ab1aa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc_main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/mscc/mscc_main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc_main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc_main.c</a></div><div class='hunk'>@@ -711,7 +711,7 @@ int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)</div><div class='ctx'> 		dump_stack();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return __phy_package_write(phydev, regnum, val);</div><div class='add'>+	return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* phydev-&gt;bus-&gt;mdio_lock should be locked when using this function */</div><div class='hunk'>@@ -722,7 +722,7 @@ int phy_base_read(struct phy_device *phydev, u32 regnum)</div><div class='ctx'> 		dump_stack();</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	return __phy_package_read(phydev, regnum);</div><div class='add'>+	return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> u32 vsc85xx_csr_read(struct phy_device *phydev,</div><div class='head'>diff --git a/drivers/net/phy/mscc/mscc_ptp.c b/drivers/net/phy/mscc/mscc_ptp.c<br/>index cf728bfd83e2..eb0b032cb613 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc_ptp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/mscc/mscc_ptp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/mscc/mscc_ptp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/mscc/mscc_ptp.c</a></div><div class='hunk'>@@ -1045,19 +1045,17 @@ static void vsc85xx_ts_reset_fifo(struct phy_device *phydev)</div><div class='ctx'> 			     val);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='add'>+static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='add'>+			    struct kernel_hwtstamp_config *cfg,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct vsc8531_private *vsc8531 =</div><div class='ctx'> 		container_of(mii_ts, struct vsc8531_private, mii_ts);</div><div class='ctx'> 	struct phy_device *phydev = vsc8531-&gt;ptp-&gt;phydev;</div><div class='del'>-	struct hwtstamp_config cfg;</div><div class='ctx'> 	bool one_step = false;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='del'>-	if (copy_from_user(&amp;cfg, ifr-&gt;ifr_data, sizeof(cfg)))</div><div class='del'>-		return -EFAULT;</div><div class='del'>-</div><div class='del'>-	switch (cfg.tx_type) {</div><div class='add'>+	switch (cfg-&gt;tx_type) {</div><div class='ctx'> 	case HWTSTAMP_TX_ONESTEP_SYNC:</div><div class='ctx'> 		one_step = true;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1069,9 +1067,9 @@ static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	vsc8531-&gt;ptp-&gt;tx_type = cfg.tx_type;</div><div class='add'>+	vsc8531-&gt;ptp-&gt;tx_type = cfg-&gt;tx_type;</div><div class='ctx'> </div><div class='del'>-	switch (cfg.rx_filter) {</div><div class='add'>+	switch (cfg-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:</div><div class='hunk'>@@ -1084,7 +1082,7 @@ static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	vsc8531-&gt;ptp-&gt;rx_filter = cfg.rx_filter;</div><div class='add'>+	vsc8531-&gt;ptp-&gt;rx_filter = cfg-&gt;rx_filter;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;vsc8531-&gt;ts_lock);</div><div class='ctx'> </div><div class='hunk'>@@ -1132,7 +1130,7 @@ static int vsc85xx_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)</div><div class='ctx'> 	vsc8531-&gt;ptp-&gt;configured = 1;</div><div class='ctx'> 	mutex_unlock(&amp;vsc8531-&gt;ts_lock);</div><div class='ctx'> </div><div class='del'>-	return copy_to_user(ifr-&gt;ifr_data, &amp;cfg, sizeof(cfg)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int vsc85xx_ts_info(struct mii_timestamper *mii_ts,</div><div class='head'>diff --git a/drivers/net/phy/nxp-c45-tja11xx-macsec.c b/drivers/net/phy/nxp-c45-tja11xx-macsec.c<br/>new file mode 100644<br/>index 000000000000..550ef08970f4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-c45-tja11xx-macsec.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx-macsec.c</a></div><div class='hunk'>@@ -0,0 +1,1729 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/* NXP C45 PTP PHY driver interface</div><div class='add'>+ * Copyright 2023 NXP</div><div class='add'>+ * Author: Radu Pirea &lt;radu-nicolae.pirea@oss.nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/delay.h&gt;</div><div class='add'>+#include &lt;linux/ethtool_netlink.h&gt;</div><div class='add'>+#include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/mii.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/phy.h&gt;</div><div class='add'>+#include &lt;linux/processor.h&gt;</div><div class='add'>+#include &lt;net/dst_metadata.h&gt;</div><div class='add'>+#include &lt;net/macsec.h&gt;</div><div class='add'>+</div><div class='add'>+#include "nxp-c45-tja11xx.h"</div><div class='add'>+</div><div class='add'>+#define MACSEC_REG_SIZE			32</div><div class='add'>+#define TX_SC_MAX			4</div><div class='add'>+</div><div class='add'>+#define TX_SC_BIT(secy_id)		BIT(MACSEC_REG_SIZE - (secy_id) - 1)</div><div class='add'>+</div><div class='add'>+#define VEND1_MACSEC_BASE		0x9000</div><div class='add'>+</div><div class='add'>+#define MACSEC_CFG			0x0000</div><div class='add'>+#define MACSEC_CFG_BYPASS		BIT(1)</div><div class='add'>+#define MACSEC_CFG_S0I			BIT(0)</div><div class='add'>+</div><div class='add'>+#define MACSEC_TPNET			0x0044</div><div class='add'>+#define PN_WRAP_THRESHOLD		0xffffffff</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSCA			0x0080</div><div class='add'>+#define MACSEC_RXSCKA			0x0084</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSCA			0x00C0</div><div class='add'>+#define MACSEC_TXSCKA			0x00C4</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSC_SCI_1H		0x0100</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSC_CFG			0x0128</div><div class='add'>+#define MACSEC_RXSC_CFG_XPN		BIT(25)</div><div class='add'>+#define MACSEC_RXSC_CFG_AES_256		BIT(24)</div><div class='add'>+#define MACSEC_RXSC_CFG_SCI_EN		BIT(11)</div><div class='add'>+#define MACSEC_RXSC_CFG_RP		BIT(10)</div><div class='add'>+#define MACSEC_RXSC_CFG_VF_MASK		GENMASK(9, 8)</div><div class='add'>+#define MACSEC_RXSC_CFG_VF_OFF		8</div><div class='add'>+</div><div class='add'>+#define MACSEC_RPW			0x012C</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSA_A_CS		0x0180</div><div class='add'>+#define MACSEC_RXSA_A_NPN		0x0184</div><div class='add'>+#define MACSEC_RXSA_A_XNPN		0x0188</div><div class='add'>+#define MACSEC_RXSA_A_LNPN		0x018C</div><div class='add'>+#define MACSEC_RXSA_A_LXNPN		0x0190</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSA_B_CS		0x01C0</div><div class='add'>+#define MACSEC_RXSA_B_NPN		0x01C4</div><div class='add'>+#define MACSEC_RXSA_B_XNPN		0x01C8</div><div class='add'>+#define MACSEC_RXSA_B_LNPN		0x01CC</div><div class='add'>+#define MACSEC_RXSA_B_LXNPN		0x01D0</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSA_CS_AN_OFF		1</div><div class='add'>+#define MACSEC_RXSA_CS_EN		BIT(0)</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSC_SCI_1H		0x0200</div><div class='add'>+#define MACSEC_TXSC_CFG			0x0228</div><div class='add'>+#define MACSEC_TXSC_CFG_XPN		BIT(25)</div><div class='add'>+#define MACSEC_TXSC_CFG_AES_256		BIT(24)</div><div class='add'>+#define MACSEC_TXSC_CFG_AN_MASK		GENMASK(19, 18)</div><div class='add'>+#define MACSEC_TXSC_CFG_AN_OFF		18</div><div class='add'>+#define MACSEC_TXSC_CFG_ASA		BIT(17)</div><div class='add'>+#define MACSEC_TXSC_CFG_SCE		BIT(16)</div><div class='add'>+#define MACSEC_TXSC_CFG_ENCRYPT		BIT(4)</div><div class='add'>+#define MACSEC_TXSC_CFG_PROTECT		BIT(3)</div><div class='add'>+#define MACSEC_TXSC_CFG_SEND_SCI	BIT(2)</div><div class='add'>+#define MACSEC_TXSC_CFG_END_STATION	BIT(1)</div><div class='add'>+#define MACSEC_TXSC_CFG_SCB		BIT(0)</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSA_A_CS		0x0280</div><div class='add'>+#define MACSEC_TXSA_A_NPN		0x0284</div><div class='add'>+#define MACSEC_TXSA_A_XNPN		0x0288</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSA_B_CS		0x02C0</div><div class='add'>+#define MACSEC_TXSA_B_NPN		0x02C4</div><div class='add'>+#define MACSEC_TXSA_B_XNPN		0x02C8</div><div class='add'>+</div><div class='add'>+#define MACSEC_SA_CS_A			BIT(31)</div><div class='add'>+</div><div class='add'>+#define MACSEC_EVR			0x0400</div><div class='add'>+#define MACSEC_EVER			0x0404</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSA_A_KA		0x0700</div><div class='add'>+#define MACSEC_RXSA_A_SSCI		0x0720</div><div class='add'>+#define MACSEC_RXSA_A_SALT		0x0724</div><div class='add'>+</div><div class='add'>+#define MACSEC_RXSA_B_KA		0x0740</div><div class='add'>+#define MACSEC_RXSA_B_SSCI		0x0760</div><div class='add'>+#define MACSEC_RXSA_B_SALT		0x0764</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSA_A_KA		0x0780</div><div class='add'>+#define MACSEC_TXSA_A_SSCI		0x07A0</div><div class='add'>+#define MACSEC_TXSA_A_SALT		0x07A4</div><div class='add'>+</div><div class='add'>+#define MACSEC_TXSA_B_KA		0x07C0</div><div class='add'>+#define MACSEC_TXSA_B_SSCI		0x07E0</div><div class='add'>+#define MACSEC_TXSA_B_SALT		0x07E4</div><div class='add'>+</div><div class='add'>+#define MACSEC_UPFR0D2			0x0A08</div><div class='add'>+#define MACSEC_UPFR0M1			0x0A10</div><div class='add'>+#define MACSEC_OVP			BIT(12)</div><div class='add'>+</div><div class='add'>+#define	MACSEC_UPFR0M2			0x0A14</div><div class='add'>+#define ETYPE_MASK			0xffff</div><div class='add'>+</div><div class='add'>+#define MACSEC_UPFR0R			0x0A18</div><div class='add'>+#define MACSEC_UPFR_EN			BIT(0)</div><div class='add'>+</div><div class='add'>+#define ADPTR_CNTRL			0x0F00</div><div class='add'>+#define ADPTR_CNTRL_CONFIG_EN		BIT(14)</div><div class='add'>+#define ADPTR_CNTRL_ADPTR_EN		BIT(12)</div><div class='add'>+#define ADPTR_TX_TAG_CNTRL		0x0F0C</div><div class='add'>+#define ADPTR_TX_TAG_CNTRL_ENA		BIT(31)</div><div class='add'>+</div><div class='add'>+#define TX_SC_FLT_BASE			0x800</div><div class='add'>+#define TX_SC_FLT_SIZE			0x10</div><div class='add'>+#define TX_FLT_BASE(flt_id)		(TX_SC_FLT_BASE + \</div><div class='add'>+	TX_SC_FLT_SIZE * (flt_id))</div><div class='add'>+</div><div class='add'>+#define TX_SC_FLT_OFF_MAC_DA_SA		0x04</div><div class='add'>+#define TX_SC_FLT_OFF_MAC_SA		0x08</div><div class='add'>+#define TX_SC_FLT_OFF_MAC_CFG		0x0C</div><div class='add'>+#define TX_SC_FLT_BY_SA			BIT(14)</div><div class='add'>+#define TX_SC_FLT_EN			BIT(8)</div><div class='add'>+</div><div class='add'>+#define TX_SC_FLT_MAC_DA_SA(base)	((base) + TX_SC_FLT_OFF_MAC_DA_SA)</div><div class='add'>+#define TX_SC_FLT_MAC_SA(base)		((base) + TX_SC_FLT_OFF_MAC_SA)</div><div class='add'>+#define TX_SC_FLT_MAC_CFG(base)		((base) + TX_SC_FLT_OFF_MAC_CFG)</div><div class='add'>+</div><div class='add'>+#define ADAPTER_EN	BIT(6)</div><div class='add'>+#define MACSEC_EN	BIT(5)</div><div class='add'>+</div><div class='add'>+#define MACSEC_INOV1HS			0x0140</div><div class='add'>+#define MACSEC_INOV2HS			0x0144</div><div class='add'>+#define MACSEC_INOD1HS			0x0148</div><div class='add'>+#define MACSEC_INOD2HS			0x014C</div><div class='add'>+#define MACSEC_RXSCIPUS			0x0150</div><div class='add'>+#define MACSEC_RXSCIPDS			0x0154</div><div class='add'>+#define MACSEC_RXSCIPLS			0x0158</div><div class='add'>+#define MACSEC_RXAN0INUSS		0x0160</div><div class='add'>+#define MACSEC_RXAN0IPUSS		0x0170</div><div class='add'>+#define MACSEC_RXSA_A_IPOS		0x0194</div><div class='add'>+#define MACSEC_RXSA_A_IPIS		0x01B0</div><div class='add'>+#define MACSEC_RXSA_A_IPNVS		0x01B4</div><div class='add'>+#define MACSEC_RXSA_B_IPOS		0x01D4</div><div class='add'>+#define MACSEC_RXSA_B_IPIS		0x01F0</div><div class='add'>+#define MACSEC_RXSA_B_IPNVS		0x01F4</div><div class='add'>+#define MACSEC_OPUS			0x021C</div><div class='add'>+#define MACSEC_OPTLS			0x022C</div><div class='add'>+#define MACSEC_OOP1HS			0x0240</div><div class='add'>+#define MACSEC_OOP2HS			0x0244</div><div class='add'>+#define MACSEC_OOE1HS			0x0248</div><div class='add'>+#define MACSEC_OOE2HS			0x024C</div><div class='add'>+#define MACSEC_TXSA_A_OPPS		0x028C</div><div class='add'>+#define MACSEC_TXSA_A_OPES		0x0290</div><div class='add'>+#define MACSEC_TXSA_B_OPPS		0x02CC</div><div class='add'>+#define MACSEC_TXSA_B_OPES		0x02D0</div><div class='add'>+#define MACSEC_INPWTS			0x0630</div><div class='add'>+#define MACSEC_INPBTS			0x0638</div><div class='add'>+#define MACSEC_IPSNFS			0x063C</div><div class='add'>+</div><div class='add'>+#define TJA11XX_TLV_TX_NEEDED_HEADROOM	(32)</div><div class='add'>+#define TJA11XX_TLV_NEEDED_TAILROOM	(0)</div><div class='add'>+</div><div class='add'>+#define ETH_P_TJA11XX_TLV		(0x4e58)</div><div class='add'>+</div><div class='add'>+enum nxp_c45_sa_type {</div><div class='add'>+	TX_SA,</div><div class='add'>+	RX_SA,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nxp_c45_sa {</div><div class='add'>+	void *sa;</div><div class='add'>+	const struct nxp_c45_sa_regs *regs;</div><div class='add'>+	enum nxp_c45_sa_type type;</div><div class='add'>+	bool is_key_a;</div><div class='add'>+	u8 an;</div><div class='add'>+	struct list_head list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nxp_c45_secy {</div><div class='add'>+	struct macsec_secy *secy;</div><div class='add'>+	struct macsec_rx_sc *rx_sc;</div><div class='add'>+	struct list_head sa_list;</div><div class='add'>+	int secy_id;</div><div class='add'>+	bool rx_sc0_impl;</div><div class='add'>+	struct list_head list;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nxp_c45_macsec {</div><div class='add'>+	struct list_head secy_list;</div><div class='add'>+	DECLARE_BITMAP(secy_bitmap, TX_SC_MAX);</div><div class='add'>+	DECLARE_BITMAP(tx_sc_bitmap, TX_SC_MAX);</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct nxp_c45_sa_regs {</div><div class='add'>+	u16 cs;</div><div class='add'>+	u16 npn;</div><div class='add'>+	u16 xnpn;</div><div class='add'>+	u16 lnpn;</div><div class='add'>+	u16 lxnpn;</div><div class='add'>+	u16 ka;</div><div class='add'>+	u16 ssci;</div><div class='add'>+	u16 salt;</div><div class='add'>+	u16 ipis;</div><div class='add'>+	u16 ipnvs;</div><div class='add'>+	u16 ipos;</div><div class='add'>+	u16 opps;</div><div class='add'>+	u16 opes;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct nxp_c45_sa_regs rx_sa_a_regs = {</div><div class='add'>+	.cs	= MACSEC_RXSA_A_CS,</div><div class='add'>+	.npn	= MACSEC_RXSA_A_NPN,</div><div class='add'>+	.xnpn	= MACSEC_RXSA_A_XNPN,</div><div class='add'>+	.lnpn	= MACSEC_RXSA_A_LNPN,</div><div class='add'>+	.lxnpn	= MACSEC_RXSA_A_LXNPN,</div><div class='add'>+	.ka	= MACSEC_RXSA_A_KA,</div><div class='add'>+	.ssci	= MACSEC_RXSA_A_SSCI,</div><div class='add'>+	.salt	= MACSEC_RXSA_A_SALT,</div><div class='add'>+	.ipis	= MACSEC_RXSA_A_IPIS,</div><div class='add'>+	.ipnvs	= MACSEC_RXSA_A_IPNVS,</div><div class='add'>+	.ipos	= MACSEC_RXSA_A_IPOS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct nxp_c45_sa_regs rx_sa_b_regs = {</div><div class='add'>+	.cs	= MACSEC_RXSA_B_CS,</div><div class='add'>+	.npn	= MACSEC_RXSA_B_NPN,</div><div class='add'>+	.xnpn	= MACSEC_RXSA_B_XNPN,</div><div class='add'>+	.lnpn	= MACSEC_RXSA_B_LNPN,</div><div class='add'>+	.lxnpn	= MACSEC_RXSA_B_LXNPN,</div><div class='add'>+	.ka	= MACSEC_RXSA_B_KA,</div><div class='add'>+	.ssci	= MACSEC_RXSA_B_SSCI,</div><div class='add'>+	.salt	= MACSEC_RXSA_B_SALT,</div><div class='add'>+	.ipis	= MACSEC_RXSA_B_IPIS,</div><div class='add'>+	.ipnvs	= MACSEC_RXSA_B_IPNVS,</div><div class='add'>+	.ipos	= MACSEC_RXSA_B_IPOS,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct nxp_c45_sa_regs tx_sa_a_regs = {</div><div class='add'>+	.cs	= MACSEC_TXSA_A_CS,</div><div class='add'>+	.npn	= MACSEC_TXSA_A_NPN,</div><div class='add'>+	.xnpn	= MACSEC_TXSA_A_XNPN,</div><div class='add'>+	.ka	= MACSEC_TXSA_A_KA,</div><div class='add'>+	.ssci	= MACSEC_TXSA_A_SSCI,</div><div class='add'>+	.salt	= MACSEC_TXSA_A_SALT,</div><div class='add'>+	.opps	= MACSEC_TXSA_A_OPPS,</div><div class='add'>+	.opes	= MACSEC_TXSA_A_OPES,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct nxp_c45_sa_regs tx_sa_b_regs = {</div><div class='add'>+	.cs	= MACSEC_TXSA_B_CS,</div><div class='add'>+	.npn	= MACSEC_TXSA_B_NPN,</div><div class='add'>+	.xnpn	= MACSEC_TXSA_B_XNPN,</div><div class='add'>+	.ka	= MACSEC_TXSA_B_KA,</div><div class='add'>+	.ssci	= MACSEC_TXSA_B_SSCI,</div><div class='add'>+	.salt	= MACSEC_TXSA_B_SALT,</div><div class='add'>+	.opps	= MACSEC_TXSA_B_OPPS,</div><div class='add'>+	.opes	= MACSEC_TXSA_B_OPES,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const</div><div class='add'>+struct nxp_c45_sa_regs *nxp_c45_sa_regs_get(enum nxp_c45_sa_type sa_type,</div><div class='add'>+					    bool key_a)</div><div class='add'>+{</div><div class='add'>+	if (sa_type == RX_SA)</div><div class='add'>+		if (key_a)</div><div class='add'>+			return &amp;rx_sa_a_regs;</div><div class='add'>+		else</div><div class='add'>+			return &amp;rx_sa_b_regs;</div><div class='add'>+	else if (sa_type == TX_SA)</div><div class='add'>+		if (key_a)</div><div class='add'>+			return &amp;tx_sa_a_regs;</div><div class='add'>+		else</div><div class='add'>+			return &amp;tx_sa_b_regs;</div><div class='add'>+	else</div><div class='add'>+		return NULL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value)</div><div class='add'>+{</div><div class='add'>+	u32 lvalue = value;</div><div class='add'>+	u16 laddr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(addr % 4);</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value);</div><div class='add'>+</div><div class='add'>+	laddr = VEND1_MACSEC_BASE + addr / 2;</div><div class='add'>+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	laddr += 1;</div><div class='add'>+	lvalue &gt;&gt;= 16;</div><div class='add'>+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_macsec_read(struct phy_device *phydev, u16 addr, u32 *value)</div><div class='add'>+{</div><div class='add'>+	u32 lvalue;</div><div class='add'>+	u16 laddr;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	WARN_ON_ONCE(addr % 4);</div><div class='add'>+</div><div class='add'>+	laddr = VEND1_MACSEC_BASE + addr / 2;</div><div class='add'>+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	laddr += 1;</div><div class='add'>+	lvalue = (u32)ret &amp; 0xffff;</div><div class='add'>+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	lvalue |= (u32)ret &lt;&lt; 16;</div><div class='add'>+	*value = lvalue;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr,</div><div class='add'>+				     u64 *value)</div><div class='add'>+{</div><div class='add'>+	u32 lvalue;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, addr, &amp;lvalue);</div><div class='add'>+	*value = lvalue;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_macsec_read64(struct phy_device *phydev, u16 addr,</div><div class='add'>+				  u64 *value)</div><div class='add'>+{</div><div class='add'>+	u32 lvalue;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, addr, &amp;lvalue);</div><div class='add'>+	*value = (u64)lvalue &lt;&lt; 32;</div><div class='add'>+	nxp_c45_macsec_read(phydev, addr + 4, &amp;lvalue);</div><div class='add'>+	*value |= lvalue;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_secy_irq_en(struct phy_device *phydev,</div><div class='add'>+				struct nxp_c45_secy *phy_secy, bool en)</div><div class='add'>+{</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_EVER, &amp;reg);</div><div class='add'>+	if (en)</div><div class='add'>+		reg |= TX_SC_BIT(phy_secy-&gt;secy_id);</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~TX_SC_BIT(phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_EVER, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct nxp_c45_secy *nxp_c45_find_secy(struct list_head *secy_list,</div><div class='add'>+					      sci_t sci)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_secy *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, secy_list, list)</div><div class='add'>+		if (pos-&gt;secy-&gt;sci == sci)</div><div class='add'>+			return pos;</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-EINVAL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct</div><div class='add'>+nxp_c45_secy *nxp_c45_find_secy_by_id(struct list_head *secy_list,</div><div class='add'>+				      int id)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_secy *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, secy_list, list)</div><div class='add'>+		if (pos-&gt;secy_id == id)</div><div class='add'>+			return pos;</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-EINVAL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_secy_free(struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;phy_secy-&gt;list);</div><div class='add'>+	kfree(phy_secy);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct nxp_c45_sa *nxp_c45_find_sa(struct list_head *sa_list,</div><div class='add'>+					  enum nxp_c45_sa_type sa_type, u8 an)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, sa_list, list)</div><div class='add'>+		if (pos-&gt;an == an &amp;&amp; pos-&gt;type == sa_type)</div><div class='add'>+			return pos;</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-EINVAL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct nxp_c45_sa *nxp_c45_sa_alloc(struct list_head *sa_list, void *sa,</div><div class='add'>+					   enum nxp_c45_sa_type sa_type, u8 an)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *first = NULL, *pos, *tmp;</div><div class='add'>+	int occurrences = 0;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, sa_list, list) {</div><div class='add'>+		if (pos-&gt;type != sa_type)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (pos-&gt;an == an)</div><div class='add'>+			return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+		first = pos;</div><div class='add'>+		occurrences++;</div><div class='add'>+		if (occurrences &gt;= 2)</div><div class='add'>+			return ERR_PTR(-ENOSPC);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);</div><div class='add'>+	if (!tmp)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	if (first)</div><div class='add'>+		tmp-&gt;is_key_a = !first-&gt;is_key_a;</div><div class='add'>+	else</div><div class='add'>+		tmp-&gt;is_key_a = true;</div><div class='add'>+</div><div class='add'>+	tmp-&gt;sa = sa;</div><div class='add'>+	tmp-&gt;type = sa_type;</div><div class='add'>+	tmp-&gt;an = an;</div><div class='add'>+	tmp-&gt;regs = nxp_c45_sa_regs_get(tmp-&gt;type, tmp-&gt;is_key_a);</div><div class='add'>+	list_add_tail(&amp;tmp-&gt;list, sa_list);</div><div class='add'>+</div><div class='add'>+	return tmp;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_sa_free(struct nxp_c45_sa *sa)</div><div class='add'>+{</div><div class='add'>+	list_del(&amp;sa-&gt;list);</div><div class='add'>+	kfree(sa);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_sa_list_free(struct list_head *sa_list)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, sa_list, list)</div><div class='add'>+		nxp_c45_sa_free(pos);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_sa_set_pn(struct phy_device *phydev,</div><div class='add'>+			      struct nxp_c45_sa *sa, u64 pn,</div><div class='add'>+			      u32 replay_window)</div><div class='add'>+{</div><div class='add'>+	const struct nxp_c45_sa_regs *sa_regs = sa-&gt;regs;</div><div class='add'>+	pn_t npn = {.full64 = pn};</div><div class='add'>+	pn_t lnpn;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;npn, npn.lower);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;xnpn, npn.upper);</div><div class='add'>+	if (sa-&gt;type != RX_SA)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	if (pn &gt; replay_window)</div><div class='add'>+		lnpn.full64 = pn - replay_window;</div><div class='add'>+	else</div><div class='add'>+		lnpn.full64 = 1;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;lnpn, lnpn.lower);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;lxnpn, lnpn.upper);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_sa_set_key(struct macsec_context *ctx,</div><div class='add'>+			       const struct nxp_c45_sa_regs *sa_regs,</div><div class='add'>+			       u8 *salt, ssci_t ssci)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	u32 key_size = ctx-&gt;secy-&gt;key_len / 4;</div><div class='add'>+	u32 salt_size = MACSEC_SALT_LEN / 4;</div><div class='add'>+	u32 *key_u32 = (u32 *)ctx-&gt;sa.key;</div><div class='add'>+	u32 *salt_u32 = (u32 *)salt;</div><div class='add'>+	u32 reg, value;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; key_size; i++) {</div><div class='add'>+		reg = sa_regs-&gt;ka + i * 4;</div><div class='add'>+		value = (__force u32)cpu_to_be32(key_u32[i]);</div><div class='add'>+		nxp_c45_macsec_write(phydev, reg, value);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (ctx-&gt;secy-&gt;xpn) {</div><div class='add'>+		for (i = 0; i &lt; salt_size; i++) {</div><div class='add'>+			reg = sa_regs-&gt;salt + (2 - i) * 4;</div><div class='add'>+			value = (__force u32)cpu_to_be32(salt_u32[i]);</div><div class='add'>+			nxp_c45_macsec_write(phydev, reg, value);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		value = (__force u32)cpu_to_be32((__force u32)ssci);</div><div class='add'>+		nxp_c45_macsec_write(phydev, sa_regs-&gt;ssci, value);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;cs, MACSEC_SA_CS_A);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sa_clear_stats(struct phy_device *phydev,</div><div class='add'>+				      struct nxp_c45_sa *sa)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa-&gt;regs-&gt;ipis, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa-&gt;regs-&gt;ipnvs, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa-&gt;regs-&gt;ipos, 0);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa-&gt;an * 4, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa-&gt;an * 4, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sa_read_stats(struct phy_device *phydev,</div><div class='add'>+				     struct nxp_c45_sa *sa,</div><div class='add'>+				     struct macsec_rx_sa_stats *stats)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_read(phydev, sa-&gt;regs-&gt;ipis, &amp;stats-&gt;InPktsInvalid);</div><div class='add'>+	nxp_c45_macsec_read(phydev, sa-&gt;regs-&gt;ipnvs, &amp;stats-&gt;InPktsNotValid);</div><div class='add'>+	nxp_c45_macsec_read(phydev, sa-&gt;regs-&gt;ipos, &amp;stats-&gt;InPktsOK);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sa_clear_stats(struct phy_device *phydev,</div><div class='add'>+				      struct nxp_c45_sa *sa)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa-&gt;regs-&gt;opps, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa-&gt;regs-&gt;opes, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sa_read_stats(struct phy_device *phydev,</div><div class='add'>+				     struct nxp_c45_sa *sa,</div><div class='add'>+				     struct macsec_tx_sa_stats *stats)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_read(phydev, sa-&gt;regs-&gt;opps, &amp;stats-&gt;OutPktsProtected);</div><div class='add'>+	nxp_c45_macsec_read(phydev, sa-&gt;regs-&gt;opes, &amp;stats-&gt;OutPktsEncrypted);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sa_update(struct phy_device *phydev,</div><div class='add'>+				 struct nxp_c45_sa *sa, bool en)</div><div class='add'>+{</div><div class='add'>+	const struct nxp_c45_sa_regs *sa_regs = sa-&gt;regs;</div><div class='add'>+	u32 cfg;</div><div class='add'>+</div><div class='add'>+	cfg = sa-&gt;an &lt;&lt; MACSEC_RXSA_CS_AN_OFF;</div><div class='add'>+	cfg |= en ? MACSEC_RXSA_CS_EN : 0;</div><div class='add'>+	nxp_c45_macsec_write(phydev, sa_regs-&gt;cs, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sa_update(struct phy_device *phydev,</div><div class='add'>+				 struct nxp_c45_sa *sa, bool en)</div><div class='add'>+{</div><div class='add'>+	u32 cfg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &amp;cfg);</div><div class='add'>+</div><div class='add'>+	cfg &amp;= ~MACSEC_TXSC_CFG_AN_MASK;</div><div class='add'>+	cfg |= sa-&gt;an &lt;&lt; MACSEC_TXSC_CFG_AN_OFF;</div><div class='add'>+</div><div class='add'>+	if (sa-&gt;is_key_a)</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_ASA;</div><div class='add'>+	else</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_ASA;</div><div class='add'>+</div><div class='add'>+	if (en)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_SCE;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_SCE;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_set_sci(struct phy_device *phydev, u16 sci_base_addr,</div><div class='add'>+			    sci_t sci)</div><div class='add'>+{</div><div class='add'>+	u64 lsci = sci_to_cpu(sci);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, sci_base_addr, lsci &gt;&gt; 32);</div><div class='add'>+	nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool nxp_c45_port_is_1(sci_t sci)</div><div class='add'>+{</div><div class='add'>+	u16 port = sci_to_cpu(sci);</div><div class='add'>+</div><div class='add'>+	return port == 1;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_select_secy(struct phy_device *phydev, u8 id)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool nxp_c45_secy_valid(struct nxp_c45_secy *phy_secy,</div><div class='add'>+			       bool can_rx_sc0_impl)</div><div class='add'>+{</div><div class='add'>+	bool end_station = phy_secy-&gt;secy-&gt;tx_sc.end_station;</div><div class='add'>+	bool scb = phy_secy-&gt;secy-&gt;tx_sc.scb;</div><div class='add'>+</div><div class='add'>+	phy_secy-&gt;rx_sc0_impl = false;</div><div class='add'>+</div><div class='add'>+	if (end_station) {</div><div class='add'>+		if (!nxp_c45_port_is_1(phy_secy-&gt;secy-&gt;sci))</div><div class='add'>+			return false;</div><div class='add'>+		if (!phy_secy-&gt;rx_sc)</div><div class='add'>+			return true;</div><div class='add'>+		return nxp_c45_port_is_1(phy_secy-&gt;rx_sc-&gt;sci);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (scb)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (!can_rx_sc0_impl)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;secy_id != 0)</div><div class='add'>+		return false;</div><div class='add'>+</div><div class='add'>+	phy_secy-&gt;rx_sc0_impl = true;</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool nxp_c45_rx_sc0_impl(struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	bool end_station = phy_secy-&gt;secy-&gt;tx_sc.end_station;</div><div class='add'>+	bool send_sci = phy_secy-&gt;secy-&gt;tx_sc.send_sci;</div><div class='add'>+	bool scb = phy_secy-&gt;secy-&gt;tx_sc.scb;</div><div class='add'>+</div><div class='add'>+	return !end_station &amp;&amp; !send_sci &amp;&amp; !scb;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool nxp_c45_mac_addr_free(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_phy *priv = ctx-&gt;phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;priv-&gt;macsec-&gt;secy_list, list) {</div><div class='add'>+		if (pos-&gt;secy == ctx-&gt;secy)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (memcmp(pos-&gt;secy-&gt;netdev-&gt;dev_addr,</div><div class='add'>+			   ctx-&gt;secy-&gt;netdev-&gt;dev_addr, ETH_ALEN) == 0)</div><div class='add'>+			return false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return true;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sc_en_flt(struct phy_device *phydev, int secy_id,</div><div class='add'>+				 bool en)</div><div class='add'>+{</div><div class='add'>+	u32 tx_flt_base = TX_FLT_BASE(secy_id);</div><div class='add'>+	u32 reg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), &amp;reg);</div><div class='add'>+	if (en)</div><div class='add'>+		reg |= TX_SC_FLT_EN;</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~TX_SC_FLT_EN;</div><div class='add'>+	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sc_set_flt(struct phy_device *phydev,</div><div class='add'>+				  struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	const u8 *dev_addr = phy_secy-&gt;secy-&gt;netdev-&gt;dev_addr;</div><div class='add'>+	u32 tx_flt_base = TX_FLT_BASE(phy_secy-&gt;secy_id);</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	reg = dev_addr[0] &lt;&lt; 8 | dev_addr[1];</div><div class='add'>+	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg);</div><div class='add'>+	reg = dev_addr[5] | dev_addr[4] &lt;&lt; 8 | dev_addr[3] &lt;&lt; 16 |</div><div class='add'>+		dev_addr[2] &lt;&lt; 24;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg);</div><div class='add'>+	nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), &amp;reg);</div><div class='add'>+	reg &amp;= TX_SC_FLT_EN;</div><div class='add'>+	reg |= TX_SC_FLT_BY_SA | phy_secy-&gt;secy_id;</div><div class='add'>+	nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sc_update(struct phy_device *phydev,</div><div class='add'>+				 struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	u32 cfg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &amp;cfg);</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "XPN %s\n", phy_secy-&gt;secy-&gt;xpn ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;xpn)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_XPN;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_XPN;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "key len %u\n", phy_secy-&gt;secy-&gt;key_len);</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;key_len == 32)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_AES_256;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_AES_256;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "encryption %s\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;tx_sc.encrypt ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;tx_sc.encrypt)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_ENCRYPT;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_ENCRYPT;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "protect frames %s\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;protect_frames ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;protect_frames)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_PROTECT;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_PROTECT;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "send sci %s\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;tx_sc.send_sci ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;tx_sc.send_sci)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_SEND_SCI;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_SEND_SCI;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "end station %s\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;tx_sc.end_station ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;tx_sc.end_station)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_END_STATION;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_END_STATION;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "scb %s\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;tx_sc.scb ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;tx_sc.scb)</div><div class='add'>+		cfg |= MACSEC_TXSC_CFG_SCB;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_TXSC_CFG_SCB;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sc_clear_stats(struct phy_device *phydev,</div><div class='add'>+				      struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;phy_secy-&gt;sa_list, list)</div><div class='add'>+		if (pos-&gt;type == TX_SA)</div><div class='add'>+			nxp_c45_tx_sa_clear_stats(phydev, pos);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_set_rx_sc0_impl(struct phy_device *phydev,</div><div class='add'>+				    bool enable)</div><div class='add'>+{</div><div class='add'>+	u32 reg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_CFG, &amp;reg);</div><div class='add'>+	if (enable)</div><div class='add'>+		reg |= MACSEC_CFG_S0I;</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~MACSEC_CFG_S0I;</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool nxp_c45_is_rx_sc0_impl(struct list_head *secy_list)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_secy *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, secy_list, list)</div><div class='add'>+		if (pos-&gt;rx_sc0_impl)</div><div class='add'>+			return pos-&gt;rx_sc0_impl;</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sc_en(struct phy_device *phydev,</div><div class='add'>+			     struct macsec_rx_sc *rx_sc, bool en)</div><div class='add'>+{</div><div class='add'>+	u32 reg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, &amp;reg);</div><div class='add'>+	if (rx_sc-&gt;active &amp;&amp; en)</div><div class='add'>+		reg |= MACSEC_RXSC_CFG_SCI_EN;</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~MACSEC_RXSC_CFG_SCI_EN;</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sc_update(struct phy_device *phydev,</div><div class='add'>+				 struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	struct macsec_rx_sc *rx_sc = phy_secy-&gt;rx_sc;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	u32 cfg = 0;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, &amp;cfg);</div><div class='add'>+	cfg &amp;= ~MACSEC_RXSC_CFG_VF_MASK;</div><div class='add'>+	cfg = phy_secy-&gt;secy-&gt;validate_frames &lt;&lt; MACSEC_RXSC_CFG_VF_OFF;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "validate frames %u\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;validate_frames);</div><div class='add'>+	phydev_dbg(phydev, "replay_protect %s window %u\n",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;replay_protect ? "on" : "off",</div><div class='add'>+		   phy_secy-&gt;secy-&gt;replay_window);</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;replay_protect) {</div><div class='add'>+		cfg |= MACSEC_RXSC_CFG_RP;</div><div class='add'>+		nxp_c45_macsec_write(phydev, MACSEC_RPW,</div><div class='add'>+				     phy_secy-&gt;secy-&gt;replay_window);</div><div class='add'>+	} else {</div><div class='add'>+		cfg &amp;= ~MACSEC_RXSC_CFG_RP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "rx_sc-&gt;active %s\n",</div><div class='add'>+		   rx_sc-&gt;active ? "on" : "off");</div><div class='add'>+	if (rx_sc-&gt;active &amp;&amp;</div><div class='add'>+	    test_bit(phy_secy-&gt;secy_id, priv-&gt;macsec-&gt;secy_bitmap))</div><div class='add'>+		cfg |= MACSEC_RXSC_CFG_SCI_EN;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_RXSC_CFG_SCI_EN;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "key len %u\n", phy_secy-&gt;secy-&gt;key_len);</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;key_len == 32)</div><div class='add'>+		cfg |= MACSEC_RXSC_CFG_AES_256;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_RXSC_CFG_AES_256;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "XPN %s\n", phy_secy-&gt;secy-&gt;xpn ? "on" : "off");</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;xpn)</div><div class='add'>+		cfg |= MACSEC_RXSC_CFG_XPN;</div><div class='add'>+	else</div><div class='add'>+		cfg &amp;= ~MACSEC_RXSC_CFG_XPN;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sc_clear_stats(struct phy_device *phydev,</div><div class='add'>+				      struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;phy_secy-&gt;sa_list, list)</div><div class='add'>+		if (pos-&gt;type == RX_SA)</div><div class='add'>+			nxp_c45_rx_sa_clear_stats(phydev, pos);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0);</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MACSEC_NUM_AN; i++) {</div><div class='add'>+		nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0);</div><div class='add'>+		nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_rx_sc_del(struct phy_device *phydev,</div><div class='add'>+			      struct nxp_c45_secy *phy_secy)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_RPW, 0);</div><div class='add'>+	nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, 0);</div><div class='add'>+</div><div class='add'>+	nxp_c45_rx_sc_clear_stats(phydev, phy_secy);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;phy_secy-&gt;sa_list, list) {</div><div class='add'>+		if (pos-&gt;type == RX_SA) {</div><div class='add'>+			nxp_c45_rx_sa_update(phydev, pos, false);</div><div class='add'>+			nxp_c45_sa_free(pos);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_clear_global_stats(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0);</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_macsec_en(struct phy_device *phydev, bool en)</div><div class='add'>+{</div><div class='add'>+	u32 reg;</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_CFG, &amp;reg);</div><div class='add'>+	if (en)</div><div class='add'>+		reg |= MACSEC_CFG_BYPASS;</div><div class='add'>+	else</div><div class='add'>+		reg &amp;= ~MACSEC_CFG_BYPASS;</div><div class='add'>+	nxp_c45_macsec_write(phydev, MACSEC_CFG, reg);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_dev_open(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	int any_bit_set;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_tx_sc_en_flt(phydev, phy_secy-&gt;secy_id, true);</div><div class='add'>+	nxp_c45_set_rx_sc0_impl(phydev, phy_secy-&gt;rx_sc0_impl);</div><div class='add'>+	if (phy_secy-&gt;rx_sc)</div><div class='add'>+		nxp_c45_rx_sc_en(phydev, phy_secy-&gt;rx_sc, true);</div><div class='add'>+</div><div class='add'>+	any_bit_set = find_first_bit(priv-&gt;macsec-&gt;secy_bitmap, TX_SC_MAX);</div><div class='add'>+	if (any_bit_set == TX_SC_MAX)</div><div class='add'>+		nxp_c45_macsec_en(phydev, true);</div><div class='add'>+</div><div class='add'>+	set_bit(phy_secy-&gt;secy_id, priv-&gt;macsec-&gt;secy_bitmap);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_dev_stop(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	int any_bit_set;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_tx_sc_en_flt(phydev, phy_secy-&gt;secy_id, false);</div><div class='add'>+	if (phy_secy-&gt;rx_sc)</div><div class='add'>+		nxp_c45_rx_sc_en(phydev, phy_secy-&gt;rx_sc, false);</div><div class='add'>+	nxp_c45_set_rx_sc0_impl(phydev, false);</div><div class='add'>+</div><div class='add'>+	clear_bit(phy_secy-&gt;secy_id, priv-&gt;macsec-&gt;secy_bitmap);</div><div class='add'>+	any_bit_set = find_first_bit(priv-&gt;macsec-&gt;secy_bitmap, TX_SC_MAX);</div><div class='add'>+	if (any_bit_set == TX_SC_MAX)</div><div class='add'>+		nxp_c45_macsec_en(phydev, false);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_add_secy(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	bool can_rx_sc0_impl;</div><div class='add'>+	int idx;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "add SecY SCI %016llx\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	if (!nxp_c45_mac_addr_free(ctx))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	if (nxp_c45_is_rx_sc0_impl(&amp;priv-&gt;macsec-&gt;secy_list))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	idx = find_first_zero_bit(priv-&gt;macsec-&gt;tx_sc_bitmap, TX_SC_MAX);</div><div class='add'>+	if (idx == TX_SC_MAX)</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+</div><div class='add'>+	phy_secy = kzalloc(sizeof(*phy_secy), GFP_KERNEL);</div><div class='add'>+	if (!phy_secy)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;phy_secy-&gt;sa_list);</div><div class='add'>+	phy_secy-&gt;secy = ctx-&gt;secy;</div><div class='add'>+	phy_secy-&gt;secy_id = idx;</div><div class='add'>+</div><div class='add'>+	/* If the point to point mode should be enabled, we should have no</div><div class='add'>+	 * SecY added yet.</div><div class='add'>+	 */</div><div class='add'>+	can_rx_sc0_impl = list_count_nodes(&amp;priv-&gt;macsec-&gt;secy_list) == 0;</div><div class='add'>+	if (!nxp_c45_secy_valid(phy_secy, can_rx_sc0_impl)) {</div><div class='add'>+		kfree(phy_secy);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	phy_secy-&gt;rx_sc0_impl = nxp_c45_rx_sc0_impl(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_set_sci(phydev, MACSEC_TXSC_SCI_1H, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	nxp_c45_tx_sc_set_flt(phydev, phy_secy);</div><div class='add'>+	nxp_c45_tx_sc_update(phydev, phy_secy);</div><div class='add'>+	if (phy_interrupt_is_valid(phydev))</div><div class='add'>+		nxp_c45_secy_irq_en(phydev, phy_secy, true);</div><div class='add'>+</div><div class='add'>+	set_bit(idx, priv-&gt;macsec-&gt;tx_sc_bitmap);</div><div class='add'>+	list_add_tail(&amp;phy_secy-&gt;list, &amp;priv-&gt;macsec-&gt;secy_list);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void nxp_c45_tx_sa_next(struct nxp_c45_secy *phy_secy,</div><div class='add'>+			       struct nxp_c45_sa *next_sa, u8 encoding_sa)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, TX_SA, encoding_sa);</div><div class='add'>+	if (!IS_ERR(sa)) {</div><div class='add'>+		memcpy(next_sa, sa, sizeof(*sa));</div><div class='add'>+	} else {</div><div class='add'>+		next_sa-&gt;is_key_a = true;</div><div class='add'>+		next_sa-&gt;an = encoding_sa;</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_upd_secy(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	u8 encoding_sa = ctx-&gt;secy-&gt;tx_sc.encoding_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	struct nxp_c45_sa next_sa;</div><div class='add'>+	bool can_rx_sc0_impl;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "update SecY SCI %016llx\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	if (!nxp_c45_mac_addr_free(ctx))</div><div class='add'>+		return -EBUSY;</div><div class='add'>+</div><div class='add'>+	/* If the point to point mode should be enabled, we should have only</div><div class='add'>+	 * one SecY added, respectively the updated one.</div><div class='add'>+	 */</div><div class='add'>+	can_rx_sc0_impl = list_count_nodes(&amp;priv-&gt;macsec-&gt;secy_list) == 1;</div><div class='add'>+	if (!nxp_c45_secy_valid(phy_secy, can_rx_sc0_impl))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	phy_secy-&gt;rx_sc0_impl = nxp_c45_rx_sc0_impl(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_tx_sc_set_flt(phydev, phy_secy);</div><div class='add'>+	nxp_c45_tx_sc_update(phydev, phy_secy);</div><div class='add'>+	nxp_c45_tx_sa_next(phy_secy, &amp;next_sa, encoding_sa);</div><div class='add'>+	nxp_c45_tx_sa_update(phydev, &amp;next_sa, ctx-&gt;secy-&gt;operational);</div><div class='add'>+</div><div class='add'>+	nxp_c45_set_rx_sc0_impl(phydev, phy_secy-&gt;rx_sc0_impl);</div><div class='add'>+	if (phy_secy-&gt;rx_sc)</div><div class='add'>+		nxp_c45_rx_sc_update(phydev, phy_secy);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_del_secy(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	u8 encoding_sa = ctx-&gt;secy-&gt;tx_sc.encoding_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	struct nxp_c45_sa next_sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "delete SecY SCI %016llx\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_mdo_dev_stop(ctx);</div><div class='add'>+	nxp_c45_tx_sa_next(phy_secy, &amp;next_sa, encoding_sa);</div><div class='add'>+	nxp_c45_tx_sa_update(phydev, &amp;next_sa, false);</div><div class='add'>+	nxp_c45_tx_sc_clear_stats(phydev, phy_secy);</div><div class='add'>+	if (phy_secy-&gt;rx_sc)</div><div class='add'>+		nxp_c45_rx_sc_del(phydev, phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_sa_list_free(&amp;phy_secy-&gt;sa_list);</div><div class='add'>+	if (phy_interrupt_is_valid(phydev))</div><div class='add'>+		nxp_c45_secy_irq_en(phydev, phy_secy, false);</div><div class='add'>+</div><div class='add'>+	clear_bit(phy_secy-&gt;secy_id, priv-&gt;macsec-&gt;tx_sc_bitmap);</div><div class='add'>+	nxp_c45_secy_free(phy_secy);</div><div class='add'>+</div><div class='add'>+	if (list_empty(&amp;priv-&gt;macsec-&gt;secy_list))</div><div class='add'>+		nxp_c45_clear_global_stats(phydev);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_add_rxsc(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "add RX SC SCI %016llx %s\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;rx_sc-&gt;sci),</div><div class='add'>+		   ctx-&gt;rx_sc-&gt;active ? "enabled" : "disabled");</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;rx_sc)</div><div class='add'>+		return -ENOSPC;</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;tx_sc.end_station &amp;&amp;</div><div class='add'>+	    !nxp_c45_port_is_1(ctx-&gt;rx_sc-&gt;sci))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	phy_secy-&gt;rx_sc = ctx-&gt;rx_sc;</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, ctx-&gt;rx_sc-&gt;sci);</div><div class='add'>+	nxp_c45_rx_sc_update(phydev, phy_secy);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_upd_rxsc(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "update RX SC SCI %016llx %s\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;rx_sc-&gt;sci),</div><div class='add'>+		   ctx-&gt;rx_sc-&gt;active ? "enabled" : "disabled");</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_rx_sc_update(phydev, phy_secy);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_del_rxsc(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "delete RX SC SCI %016llx %s\n",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;rx_sc-&gt;sci),</div><div class='add'>+		   ctx-&gt;rx_sc-&gt;active ? "enabled" : "disabled");</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_rx_sc_del(phydev, phy_secy);</div><div class='add'>+	phy_secy-&gt;rx_sc = NULL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_add_rxsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct macsec_rx_sa *rx_sa = ctx-&gt;sa.rx_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "add RX SA %u %s to RX SC SCI %016llx\n",</div><div class='add'>+		   an, rx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(rx_sa-&gt;sc-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_sa_alloc(&amp;phy_secy-&gt;sa_list, rx_sa, RX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_sa_set_pn(phydev, sa, rx_sa-&gt;next_pn,</div><div class='add'>+			  ctx-&gt;secy-&gt;replay_window);</div><div class='add'>+	nxp_c45_sa_set_key(ctx, sa-&gt;regs, rx_sa-&gt;key.salt.bytes, rx_sa-&gt;ssci);</div><div class='add'>+	nxp_c45_rx_sa_update(phydev, sa, rx_sa-&gt;active);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_upd_rxsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct macsec_rx_sa *rx_sa = ctx-&gt;sa.rx_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "update RX SA %u %s to RX SC SCI %016llx\n",</div><div class='add'>+		   an, rx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(rx_sa-&gt;sc-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, RX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	if (ctx-&gt;sa.update_pn)</div><div class='add'>+		nxp_c45_sa_set_pn(phydev, sa, rx_sa-&gt;next_pn,</div><div class='add'>+				  ctx-&gt;secy-&gt;replay_window);</div><div class='add'>+	nxp_c45_rx_sa_update(phydev, sa, rx_sa-&gt;active);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_del_rxsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct macsec_rx_sa *rx_sa = ctx-&gt;sa.rx_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "delete RX SA %u %s to RX SC SCI %016llx\n",</div><div class='add'>+		   an, rx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(rx_sa-&gt;sc-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, RX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_rx_sa_update(phydev, sa, false);</div><div class='add'>+	nxp_c45_rx_sa_clear_stats(phydev, sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_sa_free(sa);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_add_txsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct macsec_tx_sa *tx_sa = ctx-&gt;sa.tx_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "add TX SA %u %s to TX SC %016llx\n",</div><div class='add'>+		   an, ctx-&gt;sa.tx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_sa_alloc(&amp;phy_secy-&gt;sa_list, tx_sa, TX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_sa_set_pn(phydev, sa, tx_sa-&gt;next_pn, 0);</div><div class='add'>+	nxp_c45_sa_set_key(ctx, sa-&gt;regs, tx_sa-&gt;key.salt.bytes, tx_sa-&gt;ssci);</div><div class='add'>+	if (ctx-&gt;secy-&gt;tx_sc.encoding_sa == sa-&gt;an)</div><div class='add'>+		nxp_c45_tx_sa_update(phydev, sa, tx_sa-&gt;active);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_upd_txsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct macsec_tx_sa *tx_sa = ctx-&gt;sa.tx_sa;</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "update TX SA %u %s to TX SC %016llx\n",</div><div class='add'>+		   an, ctx-&gt;sa.tx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, TX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	if (ctx-&gt;sa.update_pn)</div><div class='add'>+		nxp_c45_sa_set_pn(phydev, sa, tx_sa-&gt;next_pn, 0);</div><div class='add'>+	if (ctx-&gt;secy-&gt;tx_sc.encoding_sa == sa-&gt;an)</div><div class='add'>+		nxp_c45_tx_sa_update(phydev, sa, tx_sa-&gt;active);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_del_txsa(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phydev_dbg(phydev, "delete TX SA %u %s to TX SC %016llx\n",</div><div class='add'>+		   an, ctx-&gt;sa.tx_sa-&gt;active ? "enabled" : "disabled",</div><div class='add'>+		   sci_to_cpu(ctx-&gt;secy-&gt;sci));</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, TX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	if (ctx-&gt;secy-&gt;tx_sc.encoding_sa == sa-&gt;an)</div><div class='add'>+		nxp_c45_tx_sa_update(phydev, sa, false);</div><div class='add'>+	nxp_c45_tx_sa_clear_stats(phydev, sa);</div><div class='add'>+</div><div class='add'>+	nxp_c45_sa_free(sa);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_get_dev_stats(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct macsec_dev_stats  *dev_stats;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	dev_stats = ctx-&gt;stats.dev_stats;</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_OPUS,</div><div class='add'>+				 &amp;dev_stats-&gt;OutPktsUntagged);</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_OPTLS,</div><div class='add'>+				 &amp;dev_stats-&gt;OutPktsTooLong);</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_INPBTS,</div><div class='add'>+				 &amp;dev_stats-&gt;InPktsBadTag);</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;validate_frames == MACSEC_VALIDATE_STRICT)</div><div class='add'>+		nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS,</div><div class='add'>+					 &amp;dev_stats-&gt;InPktsNoTag);</div><div class='add'>+	else</div><div class='add'>+		nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS,</div><div class='add'>+					 &amp;dev_stats-&gt;InPktsUntagged);</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;secy-&gt;validate_frames == MACSEC_VALIDATE_STRICT)</div><div class='add'>+		nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS,</div><div class='add'>+					 &amp;dev_stats-&gt;InPktsNoSCI);</div><div class='add'>+	else</div><div class='add'>+		nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS,</div><div class='add'>+					 &amp;dev_stats-&gt;InPktsUnknownSCI);</div><div class='add'>+</div><div class='add'>+	/* Always 0. */</div><div class='add'>+	dev_stats-&gt;InPktsOverrun = 0;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_get_tx_sc_stats(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct macsec_tx_sa_stats tx_sa_stats;</div><div class='add'>+	struct macsec_tx_sc_stats *stats;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	stats = ctx-&gt;stats.tx_sc_stats;</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read64(phydev, MACSEC_OOE1HS,</div><div class='add'>+			      &amp;stats-&gt;OutOctetsEncrypted);</div><div class='add'>+	nxp_c45_macsec_read64(phydev, MACSEC_OOP1HS,</div><div class='add'>+			      &amp;stats-&gt;OutOctetsProtected);</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;phy_secy-&gt;sa_list, list) {</div><div class='add'>+		if (pos-&gt;type != TX_SA)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		memset(&amp;tx_sa_stats, 0, sizeof(tx_sa_stats));</div><div class='add'>+		nxp_c45_tx_sa_read_stats(phydev, pos, &amp;tx_sa_stats);</div><div class='add'>+</div><div class='add'>+		stats-&gt;OutPktsEncrypted += tx_sa_stats.OutPktsEncrypted;</div><div class='add'>+		stats-&gt;OutPktsProtected += tx_sa_stats.OutPktsProtected;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_get_tx_sa_stats(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct macsec_tx_sa_stats *stats;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, TX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	stats = ctx-&gt;stats.tx_sa_stats;</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+	nxp_c45_tx_sa_read_stats(phydev, sa, stats);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_get_rx_sc_stats(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct macsec_rx_sa_stats rx_sa_stats;</div><div class='add'>+	struct macsec_rx_sc_stats *stats;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	struct nxp_c45_sa *pos, *tmp;</div><div class='add'>+	u32 reg = 0;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	if (phy_secy-&gt;rx_sc != ctx-&gt;rx_sc)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	stats = ctx-&gt;stats.rx_sc_stats;</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(pos, tmp, &amp;phy_secy-&gt;sa_list, list) {</div><div class='add'>+		if (pos-&gt;type != RX_SA)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		memset(&amp;rx_sa_stats, 0, sizeof(rx_sa_stats));</div><div class='add'>+		nxp_c45_rx_sa_read_stats(phydev, pos, &amp;rx_sa_stats);</div><div class='add'>+</div><div class='add'>+		stats-&gt;InPktsInvalid += rx_sa_stats.InPktsInvalid;</div><div class='add'>+		stats-&gt;InPktsNotValid += rx_sa_stats.InPktsNotValid;</div><div class='add'>+		stats-&gt;InPktsOK += rx_sa_stats.InPktsOK;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; MACSEC_NUM_AN; i++) {</div><div class='add'>+		nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + i * 4, &amp;reg);</div><div class='add'>+		stats-&gt;InPktsNotUsingSA += reg;</div><div class='add'>+		nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + i * 4, &amp;reg);</div><div class='add'>+		stats-&gt;InPktsUnusedSA += reg;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read64(phydev, MACSEC_INOD1HS,</div><div class='add'>+			      &amp;stats-&gt;InOctetsDecrypted);</div><div class='add'>+	nxp_c45_macsec_read64(phydev, MACSEC_INOV1HS,</div><div class='add'>+			      &amp;stats-&gt;InOctetsValidated);</div><div class='add'>+</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPDS,</div><div class='add'>+				 &amp;stats-&gt;InPktsDelayed);</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPLS,</div><div class='add'>+				 &amp;stats-&gt;InPktsLate);</div><div class='add'>+	nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPUS,</div><div class='add'>+				 &amp;stats-&gt;InPktsUnchecked);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_get_rx_sa_stats(struct macsec_context *ctx)</div><div class='add'>+{</div><div class='add'>+	struct phy_device *phydev = ctx-&gt;phydev;</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct macsec_rx_sa_stats *stats;</div><div class='add'>+	struct nxp_c45_secy *phy_secy;</div><div class='add'>+	u8 an = ctx-&gt;sa.assoc_num;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+</div><div class='add'>+	phy_secy = nxp_c45_find_secy(&amp;priv-&gt;macsec-&gt;secy_list, ctx-&gt;secy-&gt;sci);</div><div class='add'>+	if (IS_ERR(phy_secy))</div><div class='add'>+		return PTR_ERR(phy_secy);</div><div class='add'>+</div><div class='add'>+	sa = nxp_c45_find_sa(&amp;phy_secy-&gt;sa_list, RX_SA, an);</div><div class='add'>+	if (IS_ERR(sa))</div><div class='add'>+		return PTR_ERR(sa);</div><div class='add'>+</div><div class='add'>+	stats = ctx-&gt;stats.rx_sa_stats;</div><div class='add'>+	nxp_c45_select_secy(phydev, phy_secy-&gt;secy_id);</div><div class='add'>+</div><div class='add'>+	nxp_c45_rx_sa_read_stats(phydev, sa, stats);</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + an * 4,</div><div class='add'>+			    &amp;stats-&gt;InPktsNotUsingSA);</div><div class='add'>+	nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + an * 4,</div><div class='add'>+			    &amp;stats-&gt;InPktsUnusedSA);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+struct tja11xx_tlv_header {</div><div class='add'>+	struct ethhdr eth;</div><div class='add'>+	u8 subtype;</div><div class='add'>+	u8 len;</div><div class='add'>+	u8 payload[28];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int nxp_c45_mdo_insert_tx_tag(struct phy_device *phydev,</div><div class='add'>+				     struct sk_buff *skb)</div><div class='add'>+{</div><div class='add'>+	struct tja11xx_tlv_header *tlv;</div><div class='add'>+	struct ethhdr *eth;</div><div class='add'>+</div><div class='add'>+	eth = eth_hdr(skb);</div><div class='add'>+	tlv = skb_push(skb, TJA11XX_TLV_TX_NEEDED_HEADROOM);</div><div class='add'>+	memmove(tlv, eth, sizeof(*eth));</div><div class='add'>+	skb_reset_mac_header(skb);</div><div class='add'>+	tlv-&gt;eth.h_proto = htons(ETH_P_TJA11XX_TLV);</div><div class='add'>+	tlv-&gt;subtype = 1;</div><div class='add'>+	tlv-&gt;len = sizeof(tlv-&gt;payload);</div><div class='add'>+	memset(tlv-&gt;payload, 0, sizeof(tlv-&gt;payload));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct macsec_ops nxp_c45_macsec_ops = {</div><div class='add'>+	.mdo_dev_open = nxp_c45_mdo_dev_open,</div><div class='add'>+	.mdo_dev_stop = nxp_c45_mdo_dev_stop,</div><div class='add'>+	.mdo_add_secy = nxp_c45_mdo_add_secy,</div><div class='add'>+	.mdo_upd_secy = nxp_c45_mdo_upd_secy,</div><div class='add'>+	.mdo_del_secy = nxp_c45_mdo_del_secy,</div><div class='add'>+	.mdo_add_rxsc = nxp_c45_mdo_add_rxsc,</div><div class='add'>+	.mdo_upd_rxsc = nxp_c45_mdo_upd_rxsc,</div><div class='add'>+	.mdo_del_rxsc = nxp_c45_mdo_del_rxsc,</div><div class='add'>+	.mdo_add_rxsa = nxp_c45_mdo_add_rxsa,</div><div class='add'>+	.mdo_upd_rxsa = nxp_c45_mdo_upd_rxsa,</div><div class='add'>+	.mdo_del_rxsa = nxp_c45_mdo_del_rxsa,</div><div class='add'>+	.mdo_add_txsa = nxp_c45_mdo_add_txsa,</div><div class='add'>+	.mdo_upd_txsa = nxp_c45_mdo_upd_txsa,</div><div class='add'>+	.mdo_del_txsa = nxp_c45_mdo_del_txsa,</div><div class='add'>+	.mdo_get_dev_stats = nxp_c45_mdo_get_dev_stats,</div><div class='add'>+	.mdo_get_tx_sc_stats = nxp_c45_mdo_get_tx_sc_stats,</div><div class='add'>+	.mdo_get_tx_sa_stats = nxp_c45_mdo_get_tx_sa_stats,</div><div class='add'>+	.mdo_get_rx_sc_stats = nxp_c45_mdo_get_rx_sc_stats,</div><div class='add'>+	.mdo_get_rx_sa_stats = nxp_c45_mdo_get_rx_sa_stats,</div><div class='add'>+	.mdo_insert_tx_tag = nxp_c45_mdo_insert_tx_tag,</div><div class='add'>+	.needed_headroom = TJA11XX_TLV_TX_NEEDED_HEADROOM,</div><div class='add'>+	.needed_tailroom = TJA11XX_TLV_NEEDED_TAILROOM,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+int nxp_c45_macsec_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;macsec)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,</div><div class='add'>+			       MACSEC_EN | ADAPTER_EN);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN |</div><div class='add'>+				   ADPTR_CNTRL_ADPTR_EN);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL,</div><div class='add'>+				   ADPTR_TX_TAG_CNTRL_ENA);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Set MKA filter. */</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int nxp_c45_macsec_probe(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct device *dev = &amp;phydev-&gt;mdio.dev;</div><div class='add'>+</div><div class='add'>+	priv-&gt;macsec = devm_kzalloc(dev, sizeof(*priv-&gt;macsec), GFP_KERNEL);</div><div class='add'>+	if (!priv-&gt;macsec)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	INIT_LIST_HEAD(&amp;priv-&gt;macsec-&gt;secy_list);</div><div class='add'>+	phydev-&gt;macsec_ops = &amp;nxp_c45_macsec_ops;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void nxp_c45_macsec_remove(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *secy_p, *secy_t;</div><div class='add'>+	struct nxp_c45_sa *sa_p, *sa_t;</div><div class='add'>+	struct list_head *secy_list;</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;macsec)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	secy_list = &amp;priv-&gt;macsec-&gt;secy_list;</div><div class='add'>+	nxp_c45_macsec_en(phydev, false);</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(secy_p, secy_t, secy_list, list) {</div><div class='add'>+		list_for_each_entry_safe(sa_p, sa_t, &amp;secy_p-&gt;sa_list, list)</div><div class='add'>+			nxp_c45_sa_free(sa_p);</div><div class='add'>+		nxp_c45_secy_free(secy_p);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev,</div><div class='add'>+				     irqreturn_t *ret)</div><div class='add'>+{</div><div class='add'>+	struct nxp_c45_phy *priv = phydev-&gt;priv;</div><div class='add'>+	struct nxp_c45_secy *secy;</div><div class='add'>+	struct nxp_c45_sa *sa;</div><div class='add'>+	u8 encoding_sa;</div><div class='add'>+	int secy_id;</div><div class='add'>+	u32 reg = 0;</div><div class='add'>+</div><div class='add'>+	if (!priv-&gt;macsec)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	do {</div><div class='add'>+		nxp_c45_macsec_read(phydev, MACSEC_EVR, &amp;reg);</div><div class='add'>+		if (!reg)</div><div class='add'>+			return;</div><div class='add'>+</div><div class='add'>+		secy_id = MACSEC_REG_SIZE - ffs(reg);</div><div class='add'>+		secy = nxp_c45_find_secy_by_id(&amp;priv-&gt;macsec-&gt;secy_list,</div><div class='add'>+					       secy_id);</div><div class='add'>+		if (IS_ERR(secy)) {</div><div class='add'>+			WARN_ON(1);</div><div class='add'>+			goto macsec_ack_irq;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		encoding_sa = secy-&gt;secy-&gt;tx_sc.encoding_sa;</div><div class='add'>+		phydev_dbg(phydev, "pn_wrapped: TX SC %d, encoding_sa %u\n",</div><div class='add'>+			   secy-&gt;secy_id, encoding_sa);</div><div class='add'>+</div><div class='add'>+		sa = nxp_c45_find_sa(&amp;secy-&gt;sa_list, TX_SA, encoding_sa);</div><div class='add'>+		if (!IS_ERR(sa))</div><div class='add'>+			macsec_pn_wrapped(secy-&gt;secy, sa-&gt;sa);</div><div class='add'>+		else</div><div class='add'>+			WARN_ON(1);</div><div class='add'>+</div><div class='add'>+macsec_ack_irq:</div><div class='add'>+		nxp_c45_macsec_write(phydev, MACSEC_EVR,</div><div class='add'>+				     TX_SC_BIT(secy_id));</div><div class='add'>+		*ret = IRQ_HANDLED;</div><div class='add'>+	} while (reg);</div><div class='add'>+}</div><div class='head'>diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c<br/>index 7ab080ff02df..3cf614b4cd52 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-c45-tja11xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/nxp-c45-tja11xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-c45-tja11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx.c</a></div><div class='hunk'>@@ -1,6 +1,6 @@</div><div class='ctx'> // SPDX-License-Identifier: GPL-2.0</div><div class='ctx'> /* NXP C45 PHY driver</div><div class='del'>- * Copyright (C) 2021 NXP</div><div class='add'>+ * Copyright 2021-2023 NXP</div><div class='ctx'>  * Author: Radu Pirea &lt;radu-nicolae.pirea@oss.nxp.com&gt;</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='hunk'>@@ -14,9 +14,10 @@</div><div class='ctx'> #include &lt;linux/processor.h&gt;</div><div class='ctx'> #include &lt;linux/property.h&gt;</div><div class='ctx'> #include &lt;linux/ptp_classify.h&gt;</div><div class='del'>-#include &lt;linux/ptp_clock_kernel.h&gt;</div><div class='ctx'> #include &lt;linux/net_tstamp.h&gt;</div><div class='ctx'> </div><div class='add'>+#include "nxp-c45-tja11xx.h"</div><div class='add'>+</div><div class='ctx'> #define PHY_ID_TJA_1103			0x001BB010</div><div class='ctx'> #define PHY_ID_TJA_1120			0x001BB031</div><div class='ctx'> </div><div class='hunk'>@@ -75,9 +76,11 @@</div><div class='ctx'> #define PORT_CONTROL_EN			BIT(14)</div><div class='ctx'> </div><div class='ctx'> #define VEND1_PORT_ABILITIES		0x8046</div><div class='add'>+#define MACSEC_ABILITY			BIT(5)</div><div class='ctx'> #define PTP_ABILITY			BIT(3)</div><div class='ctx'> </div><div class='ctx'> #define VEND1_PORT_FUNC_IRQ_EN		0x807A</div><div class='add'>+#define MACSEC_IRQS			BIT(5)</div><div class='ctx'> #define PTP_IRQS			BIT(3)</div><div class='ctx'> </div><div class='ctx'> #define VEND1_PTP_IRQ_ACK		0x9008</div><div class='hunk'>@@ -148,7 +151,6 @@</div><div class='ctx'> </div><div class='ctx'> #define TS_SEC_MASK			GENMASK(1, 0)</div><div class='ctx'> </div><div class='del'>-#define VEND1_PORT_FUNC_ENABLES		0x8048</div><div class='ctx'> #define PTP_ENABLE			BIT(3)</div><div class='ctx'> #define PHY_TEST_ENABLE			BIT(0)</div><div class='ctx'> </div><div class='hunk'>@@ -281,25 +283,6 @@ struct nxp_c45_phy_data {</div><div class='ctx'> 			    irqreturn_t *irq_status);</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct nxp_c45_phy {</div><div class='del'>-	const struct nxp_c45_phy_data *phy_data;</div><div class='del'>-	struct phy_device *phydev;</div><div class='del'>-	struct mii_timestamper mii_ts;</div><div class='del'>-	struct ptp_clock *ptp_clock;</div><div class='del'>-	struct ptp_clock_info caps;</div><div class='del'>-	struct sk_buff_head tx_queue;</div><div class='del'>-	struct sk_buff_head rx_queue;</div><div class='del'>-	/* used to access the PTP registers atomic */</div><div class='del'>-	struct mutex ptp_lock;</div><div class='del'>-	int hwts_tx;</div><div class='del'>-	int hwts_rx;</div><div class='del'>-	u32 tx_delay;</div><div class='del'>-	u32 rx_delay;</div><div class='del'>-	struct timespec64 extts_ts;</div><div class='del'>-	int extts_index;</div><div class='del'>-	bool extts;</div><div class='del'>-};</div><div class='del'>-</div><div class='ctx'> static const</div><div class='ctx'> struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='hunk'>@@ -1022,24 +1005,21 @@ static bool nxp_c45_rxtstamp(struct mii_timestamper *mii_ts,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nxp_c45_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='del'>-			    struct ifreq *ifreq)</div><div class='add'>+			    struct kernel_hwtstamp_config *cfg,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct nxp_c45_phy *priv = container_of(mii_ts, struct nxp_c45_phy,</div><div class='ctx'> 						mii_ts);</div><div class='ctx'> 	struct phy_device *phydev = priv-&gt;phydev;</div><div class='ctx'> 	const struct nxp_c45_phy_data *data;</div><div class='del'>-	struct hwtstamp_config cfg;</div><div class='del'>-</div><div class='del'>-	if (copy_from_user(&amp;cfg, ifreq-&gt;ifr_data, sizeof(cfg)))</div><div class='del'>-		return -EFAULT;</div><div class='ctx'> </div><div class='del'>-	if (cfg.tx_type &lt; 0 || cfg.tx_type &gt; HWTSTAMP_TX_ON)</div><div class='add'>+	if (cfg-&gt;tx_type &lt; 0 || cfg-&gt;tx_type &gt; HWTSTAMP_TX_ON)</div><div class='ctx'> 		return -ERANGE;</div><div class='ctx'> </div><div class='ctx'> 	data = nxp_c45_get_data(phydev);</div><div class='del'>-	priv-&gt;hwts_tx = cfg.tx_type;</div><div class='add'>+	priv-&gt;hwts_tx = cfg-&gt;tx_type;</div><div class='ctx'> </div><div class='del'>-	switch (cfg.rx_filter) {</div><div class='add'>+	switch (cfg-&gt;rx_filter) {</div><div class='ctx'> 	case HWTSTAMP_FILTER_NONE:</div><div class='ctx'> 		priv-&gt;hwts_rx = 0;</div><div class='ctx'> 		break;</div><div class='hunk'>@@ -1047,7 +1027,7 @@ static int nxp_c45_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:</div><div class='ctx'> 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:</div><div class='ctx'> 		priv-&gt;hwts_rx = 1;</div><div class='del'>-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;</div><div class='add'>+		cfg-&gt;rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;</div><div class='ctx'> 		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return -ERANGE;</div><div class='hunk'>@@ -1074,7 +1054,7 @@ static int nxp_c45_hwtstamp(struct mii_timestamper *mii_ts,</div><div class='ctx'> 		nxp_c45_clear_reg_field(phydev, &amp;data-&gt;regmap-&gt;irq_egr_ts_en);</div><div class='ctx'> </div><div class='ctx'> nxp_c45_no_ptp_irq:</div><div class='del'>-	return copy_to_user(ifreq-&gt;ifr_data, &amp;cfg, sizeof(cfg)) ? -EFAULT : 0;</div><div class='add'>+	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int nxp_c45_ts_info(struct mii_timestamper *mii_ts,</div><div class='hunk'>@@ -1218,12 +1198,25 @@ static int nxp_c45_start_op(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> static int nxp_c45_config_intr(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='del'>-	if (phydev-&gt;interrupts == PHY_INTERRUPT_ENABLED)</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (phydev-&gt;interrupts == PHY_INTERRUPT_ENABLED) {</div><div class='add'>+		ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+				       VEND1_PORT_FUNC_IRQ_EN, MACSEC_IRQS);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='ctx'> 		return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='ctx'> 					VEND1_PHY_IRQ_EN, PHY_IRQ_LINK_EVENT);</div><div class='del'>-	else</div><div class='del'>-		return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='del'>-					  VEND1_PHY_IRQ_EN, PHY_IRQ_LINK_EVENT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+				 VEND1_PORT_FUNC_IRQ_EN, MACSEC_IRQS);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+				  VEND1_PHY_IRQ_EN, PHY_IRQ_LINK_EVENT);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int tja1103_config_intr(struct phy_device *phydev)</div><div class='hunk'>@@ -1289,6 +1282,7 @@ static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	data-&gt;nmi_handler(phydev, &amp;ret);</div><div class='add'>+	nxp_c45_handle_macsec_interrupt(phydev, &amp;ret);</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1614,6 +1608,9 @@ static int nxp_c45_config_init(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	nxp_c45_counters_enable(phydev);</div><div class='ctx'> 	nxp_c45_ptp_init(phydev);</div><div class='add'>+	ret = nxp_c45_macsec_config_init(phydev);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	return nxp_c45_start_op(phydev);</div><div class='ctx'> }</div><div class='hunk'>@@ -1629,7 +1626,9 @@ static int nxp_c45_get_features(struct phy_device *phydev)</div><div class='ctx'> static int nxp_c45_probe(struct phy_device *phydev)</div><div class='ctx'> {</div><div class='ctx'> 	struct nxp_c45_phy *priv;</div><div class='del'>-	int ptp_ability;</div><div class='add'>+	bool macsec_ability;</div><div class='add'>+	int phy_abilities;</div><div class='add'>+	bool ptp_ability;</div><div class='ctx'> 	int ret = 0;</div><div class='ctx'> </div><div class='ctx'> 	priv = devm_kzalloc(&amp;phydev-&gt;mdio.dev, sizeof(*priv), GFP_KERNEL);</div><div class='hunk'>@@ -1645,9 +1644,9 @@ static int nxp_c45_probe(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_init(&amp;priv-&gt;ptp_lock);</div><div class='ctx'> </div><div class='del'>-	ptp_ability = phy_read_mmd(phydev, MDIO_MMD_VEND1,</div><div class='del'>-				   VEND1_PORT_ABILITIES);</div><div class='del'>-	ptp_ability = !!(ptp_ability &amp; PTP_ABILITY);</div><div class='add'>+	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,</div><div class='add'>+				     VEND1_PORT_ABILITIES);</div><div class='add'>+	ptp_ability = !!(phy_abilities &amp; PTP_ABILITY);</div><div class='ctx'> 	if (!ptp_ability) {</div><div class='ctx'> 		phydev_dbg(phydev, "the phy does not support PTP");</div><div class='ctx'> 		goto no_ptp_support;</div><div class='hunk'>@@ -1666,6 +1665,20 @@ static int nxp_c45_probe(struct phy_device *phydev)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> no_ptp_support:</div><div class='add'>+	macsec_ability = !!(phy_abilities &amp; MACSEC_ABILITY);</div><div class='add'>+	if (!macsec_ability) {</div><div class='add'>+		phydev_info(phydev, "the phy does not support MACsec\n");</div><div class='add'>+		goto no_macsec_support;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_ENABLED(CONFIG_MACSEC)) {</div><div class='add'>+		ret = nxp_c45_macsec_probe(phydev);</div><div class='add'>+		phydev_dbg(phydev, "MACsec support enabled.");</div><div class='add'>+	} else {</div><div class='add'>+		phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it");</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+no_macsec_support:</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='hunk'>@@ -1679,6 +1692,7 @@ static void nxp_c45_remove(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	skb_queue_purge(&amp;priv-&gt;tx_queue);</div><div class='ctx'> 	skb_queue_purge(&amp;priv-&gt;rx_queue);</div><div class='add'>+	nxp_c45_macsec_remove(phydev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void tja1103_counters_enable(struct phy_device *phydev)</div><div class='head'>diff --git a/drivers/net/phy/nxp-c45-tja11xx.h b/drivers/net/phy/nxp-c45-tja11xx.h<br/>new file mode 100644<br/>index 000000000000..f364fca68f0b<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-c45-tja11xx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-c45-tja11xx.h</a></div><div class='hunk'>@@ -0,0 +1,62 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/* NXP C45 PHY driver header file</div><div class='add'>+ * Copyright 2023 NXP</div><div class='add'>+ * Author: Radu Pirea &lt;radu-nicolae.pirea@oss.nxp.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/ptp_clock_kernel.h&gt;</div><div class='add'>+</div><div class='add'>+#define VEND1_PORT_FUNC_ENABLES		0x8048</div><div class='add'>+</div><div class='add'>+struct nxp_c45_macsec;</div><div class='add'>+</div><div class='add'>+struct nxp_c45_phy {</div><div class='add'>+	const struct nxp_c45_phy_data *phy_data;</div><div class='add'>+	struct phy_device *phydev;</div><div class='add'>+	struct mii_timestamper mii_ts;</div><div class='add'>+	struct ptp_clock *ptp_clock;</div><div class='add'>+	struct ptp_clock_info caps;</div><div class='add'>+	struct sk_buff_head tx_queue;</div><div class='add'>+	struct sk_buff_head rx_queue;</div><div class='add'>+	/* used to access the PTP registers atomic */</div><div class='add'>+	struct mutex ptp_lock;</div><div class='add'>+	int hwts_tx;</div><div class='add'>+	int hwts_rx;</div><div class='add'>+	u32 tx_delay;</div><div class='add'>+	u32 rx_delay;</div><div class='add'>+	struct timespec64 extts_ts;</div><div class='add'>+	int extts_index;</div><div class='add'>+	bool extts;</div><div class='add'>+	struct nxp_c45_macsec *macsec;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+#if IS_ENABLED(CONFIG_MACSEC)</div><div class='add'>+int nxp_c45_macsec_config_init(struct phy_device *phydev);</div><div class='add'>+int nxp_c45_macsec_probe(struct phy_device *phydev);</div><div class='add'>+void nxp_c45_macsec_remove(struct phy_device *phydev);</div><div class='add'>+void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev,</div><div class='add'>+				     irqreturn_t *ret);</div><div class='add'>+#else</div><div class='add'>+static inline</div><div class='add'>+int nxp_c45_macsec_config_init(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+int nxp_c45_macsec_probe(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+void nxp_c45_macsec_remove(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static inline</div><div class='add'>+void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev,</div><div class='add'>+				     irqreturn_t *ret)</div><div class='add'>+{</div><div class='add'>+}</div><div class='add'>+#endif</div><div class='head'>diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c<br/>index a71399965142..2c263ae44b4f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-tja11xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/nxp-tja11xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/nxp-tja11xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/nxp-tja11xx.c</a></div><div class='hunk'>@@ -415,7 +415,7 @@ static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(tja11xx_hw_stats); i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", tja11xx_hw_stats[i].string);</div><div class='add'>+		ethtool_puts(&amp;data, tja11xx_hw_stats[i].string);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void tja11xx_get_stats(struct phy_device *phydev,</div><div class='head'>diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c<br/>index 8e6fd4962c48..747d14bf152c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/phy-c45.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/phy-c45.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/phy-c45.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy-c45.c</a></div><div class='hunk'>@@ -920,6 +920,79 @@ int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)</div><div class='ctx'> EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA</div><div class='add'>+ * @phydev: target phy_device struct</div><div class='add'>+ *</div><div class='add'>+ * Read the supported link modes from the PMA/PMD extended ability register</div><div class='add'>+ * (Register 1.11).</div><div class='add'>+ */</div><div class='add'>+int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev)</div><div class='add'>+{</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);</div><div class='add'>+	if (val &lt; 0)</div><div class='add'>+		return val;</div><div class='add'>+</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10GBLRM);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10GBT);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10GBKX4);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10GBKR);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_1000BT);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_1000BKX);</div><div class='add'>+</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_100BTX);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_100BTX);</div><div class='add'>+</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10BT);</div><div class='add'>+	linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,</div><div class='add'>+			 phydev-&gt;supported,</div><div class='add'>+			 val &amp; MDIO_PMA_EXTABLE_10BT);</div><div class='add'>+</div><div class='add'>+	if (val &amp; MDIO_PMA_EXTABLE_NBT) {</div><div class='add'>+		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,</div><div class='add'>+				   MDIO_PMA_NG_EXTABLE);</div><div class='add'>+		if (val &lt; 0)</div><div class='add'>+			return val;</div><div class='add'>+</div><div class='add'>+		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,</div><div class='add'>+				 phydev-&gt;supported,</div><div class='add'>+				 val &amp; MDIO_PMA_NG_EXTABLE_2_5GBT);</div><div class='add'>+</div><div class='add'>+		linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,</div><div class='add'>+				 phydev-&gt;supported,</div><div class='add'>+				 val &amp; MDIO_PMA_NG_EXTABLE_5GBT);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (val &amp; MDIO_PMA_EXTABLE_BT1) {</div><div class='add'>+		val = genphy_c45_pma_baset1_read_abilities(phydev);</div><div class='add'>+		if (val &lt; 0)</div><div class='add'>+			return val;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * genphy_c45_pma_read_abilities - read supported link modes from PMA</div><div class='ctx'>  * @phydev: target phy_device struct</div><div class='ctx'>  *</div><div class='hunk'>@@ -962,63 +1035,9 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev)</div><div class='ctx'> 			 val &amp; MDIO_PMA_STAT2_10GBER);</div><div class='ctx'> </div><div class='ctx'> 	if (val &amp; MDIO_PMA_STAT2_EXTABLE) {</div><div class='del'>-		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);</div><div class='add'>+		val = genphy_c45_pma_read_ext_abilities(phydev);</div><div class='ctx'> 		if (val &lt; 0)</div><div class='ctx'> 			return val;</div><div class='del'>-</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10GBLRM);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10GBT);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10GBKX4);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10GBKR);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_1000BT);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_1000BKX);</div><div class='del'>-</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_100BTX);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_100BTX);</div><div class='del'>-</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10BT);</div><div class='del'>-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,</div><div class='del'>-				 phydev-&gt;supported,</div><div class='del'>-				 val &amp; MDIO_PMA_EXTABLE_10BT);</div><div class='del'>-</div><div class='del'>-		if (val &amp; MDIO_PMA_EXTABLE_NBT) {</div><div class='del'>-			val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,</div><div class='del'>-					   MDIO_PMA_NG_EXTABLE);</div><div class='del'>-			if (val &lt; 0)</div><div class='del'>-				return val;</div><div class='del'>-</div><div class='del'>-			linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,</div><div class='del'>-					 phydev-&gt;supported,</div><div class='del'>-					 val &amp; MDIO_PMA_NG_EXTABLE_2_5GBT);</div><div class='del'>-</div><div class='del'>-			linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,</div><div class='del'>-					 phydev-&gt;supported,</div><div class='del'>-					 val &amp; MDIO_PMA_NG_EXTABLE_5GBT);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (val &amp; MDIO_PMA_EXTABLE_BT1) {</div><div class='del'>-			val = genphy_c45_pma_baset1_read_abilities(phydev);</div><div class='del'>-			if (val &lt; 0)</div><div class='del'>-				return val;</div><div class='del'>-		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* This is optional functionality. If not supported, we may get an error</div><div class='head'>diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c<br/>index 966c93cbe616..15f349e5995a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/phy-core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/phy-core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/phy-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy-core.c</a></div><div class='hunk'>@@ -540,6 +540,28 @@ static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,</div><div class='ctx'> 			devad | MII_MMD_CTRL_NOINCR);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,</div><div class='add'>+			int devad, u32 regnum)</div><div class='add'>+{</div><div class='add'>+	if (is_c45)</div><div class='add'>+		return __mdiobus_c45_read(bus, phy_addr, devad, regnum);</div><div class='add'>+</div><div class='add'>+	mmd_phy_indirect(bus, phy_addr, devad, regnum);</div><div class='add'>+	/* Read the content of the MMD's selected register */</div><div class='add'>+	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,</div><div class='add'>+			 int devad, u32 regnum, u16 val)</div><div class='add'>+{</div><div class='add'>+	if (is_c45)</div><div class='add'>+		return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);</div><div class='add'>+</div><div class='add'>+	mmd_phy_indirect(bus, phy_addr, devad, regnum);</div><div class='add'>+	/* Write the data into MMD's selected register */</div><div class='add'>+	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * __phy_read_mmd - Convenience function for reading a register</div><div class='ctx'>  * from an MMD on a given PHY.</div><div class='hunk'>@@ -551,26 +573,14 @@ static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,</div><div class='ctx'>  */</div><div class='ctx'> int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)</div><div class='ctx'> {</div><div class='del'>-	int val;</div><div class='del'>-</div><div class='ctx'> 	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;drv &amp;&amp; phydev-&gt;drv-&gt;read_mmd) {</div><div class='del'>-		val = phydev-&gt;drv-&gt;read_mmd(phydev, devad, regnum);</div><div class='del'>-	} else if (phydev-&gt;is_c45) {</div><div class='del'>-		val = __mdiobus_c45_read(phydev-&gt;mdio.bus, phydev-&gt;mdio.addr,</div><div class='del'>-					 devad, regnum);</div><div class='del'>-	} else {</div><div class='del'>-		struct mii_bus *bus = phydev-&gt;mdio.bus;</div><div class='del'>-		int phy_addr = phydev-&gt;mdio.addr;</div><div class='del'>-</div><div class='del'>-		mmd_phy_indirect(bus, phy_addr, devad, regnum);</div><div class='add'>+	if (phydev-&gt;drv &amp;&amp; phydev-&gt;drv-&gt;read_mmd)</div><div class='add'>+		return phydev-&gt;drv-&gt;read_mmd(phydev, devad, regnum);</div><div class='ctx'> </div><div class='del'>-		/* Read the content of the MMD's selected register */</div><div class='del'>-		val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);</div><div class='del'>-	}</div><div class='del'>-	return val;</div><div class='add'>+	return mmd_phy_read(phydev-&gt;mdio.bus, phydev-&gt;mdio.addr,</div><div class='add'>+			    phydev-&gt;is_c45, devad, regnum);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(__phy_read_mmd);</div><div class='ctx'> </div><div class='hunk'>@@ -607,28 +617,14 @@ EXPORT_SYMBOL(phy_read_mmd);</div><div class='ctx'>  */</div><div class='ctx'> int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)</div><div class='ctx'> {</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='ctx'> 	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	if (phydev-&gt;drv &amp;&amp; phydev-&gt;drv-&gt;write_mmd) {</div><div class='del'>-		ret = phydev-&gt;drv-&gt;write_mmd(phydev, devad, regnum, val);</div><div class='del'>-	} else if (phydev-&gt;is_c45) {</div><div class='del'>-		ret = __mdiobus_c45_write(phydev-&gt;mdio.bus, phydev-&gt;mdio.addr,</div><div class='del'>-					  devad, regnum, val);</div><div class='del'>-	} else {</div><div class='del'>-		struct mii_bus *bus = phydev-&gt;mdio.bus;</div><div class='del'>-		int phy_addr = phydev-&gt;mdio.addr;</div><div class='del'>-</div><div class='del'>-		mmd_phy_indirect(bus, phy_addr, devad, regnum);</div><div class='add'>+	if (phydev-&gt;drv &amp;&amp; phydev-&gt;drv-&gt;write_mmd)</div><div class='add'>+		return phydev-&gt;drv-&gt;write_mmd(phydev, devad, regnum, val);</div><div class='ctx'> </div><div class='del'>-		/* Write the data into MMD's selected register */</div><div class='del'>-		__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);</div><div class='del'>-</div><div class='del'>-		ret = 0;</div><div class='del'>-	}</div><div class='del'>-	return ret;</div><div class='add'>+	return mmd_phy_write(phydev-&gt;mdio.bus, phydev-&gt;mdio.addr,</div><div class='add'>+			     phydev-&gt;is_c45, devad, regnum, val);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(__phy_write_mmd);</div><div class='ctx'> </div><div class='hunk'>@@ -655,6 +651,146 @@ int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)</div><div class='ctx'> EXPORT_SYMBOL(phy_write_mmd);</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='add'>+ * __phy_package_read_mmd - read MMD reg relative to PHY package base addr</div><div class='add'>+ * @phydev: The phy_device struct</div><div class='add'>+ * @addr_offset: The offset to be added to PHY package base_addr</div><div class='add'>+ * @devad: The MMD to read from</div><div class='add'>+ * @regnum: The register on the MMD to read</div><div class='add'>+ *</div><div class='add'>+ * Convenience helper for reading a register of an MMD on a given PHY</div><div class='add'>+ * using the PHY package base address. The base address is added to</div><div class='add'>+ * the addr_offset value.</div><div class='add'>+ *</div><div class='add'>+ * Same calling rules as for __phy_read();</div><div class='add'>+ *</div><div class='add'>+ * NOTE: It's assumed that the entire PHY package is either C22 or C45.</div><div class='add'>+ */</div><div class='add'>+int __phy_package_read_mmd(struct phy_device *phydev,</div><div class='add'>+			   unsigned int addr_offset, int devad,</div><div class='add'>+			   u32 regnum)</div><div class='add'>+{</div><div class='add'>+	int addr = phy_package_address(phydev, addr_offset);</div><div class='add'>+</div><div class='add'>+	if (addr &lt; 0)</div><div class='add'>+		return addr;</div><div class='add'>+</div><div class='add'>+	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return mmd_phy_read(phydev-&gt;mdio.bus, addr, phydev-&gt;is_c45, devad,</div><div class='add'>+			    regnum);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(__phy_package_read_mmd);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * phy_package_read_mmd - read MMD reg relative to PHY package base addr</div><div class='add'>+ * @phydev: The phy_device struct</div><div class='add'>+ * @addr_offset: The offset to be added to PHY package base_addr</div><div class='add'>+ * @devad: The MMD to read from</div><div class='add'>+ * @regnum: The register on the MMD to read</div><div class='add'>+ *</div><div class='add'>+ * Convenience helper for reading a register of an MMD on a given PHY</div><div class='add'>+ * using the PHY package base address. The base address is added to</div><div class='add'>+ * the addr_offset value.</div><div class='add'>+ *</div><div class='add'>+ * Same calling rules as for phy_read();</div><div class='add'>+ *</div><div class='add'>+ * NOTE: It's assumed that the entire PHY package is either C22 or C45.</div><div class='add'>+ */</div><div class='add'>+int phy_package_read_mmd(struct phy_device *phydev,</div><div class='add'>+			 unsigned int addr_offset, int devad,</div><div class='add'>+			 u32 regnum)</div><div class='add'>+{</div><div class='add'>+	int addr = phy_package_address(phydev, addr_offset);</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	if (addr &lt; 0)</div><div class='add'>+		return addr;</div><div class='add'>+</div><div class='add'>+	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	phy_lock_mdio_bus(phydev);</div><div class='add'>+	val = mmd_phy_read(phydev-&gt;mdio.bus, addr, phydev-&gt;is_c45, devad,</div><div class='add'>+			   regnum);</div><div class='add'>+	phy_unlock_mdio_bus(phydev);</div><div class='add'>+</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(phy_package_read_mmd);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __phy_package_write_mmd - write MMD reg relative to PHY package base addr</div><div class='add'>+ * @phydev: The phy_device struct</div><div class='add'>+ * @addr_offset: The offset to be added to PHY package base_addr</div><div class='add'>+ * @devad: The MMD to write to</div><div class='add'>+ * @regnum: The register on the MMD to write</div><div class='add'>+ * @val: value to write to @regnum</div><div class='add'>+ *</div><div class='add'>+ * Convenience helper for writing a register of an MMD on a given PHY</div><div class='add'>+ * using the PHY package base address. The base address is added to</div><div class='add'>+ * the addr_offset value.</div><div class='add'>+ *</div><div class='add'>+ * Same calling rules as for __phy_write();</div><div class='add'>+ *</div><div class='add'>+ * NOTE: It's assumed that the entire PHY package is either C22 or C45.</div><div class='add'>+ */</div><div class='add'>+int __phy_package_write_mmd(struct phy_device *phydev,</div><div class='add'>+			    unsigned int addr_offset, int devad,</div><div class='add'>+			    u32 regnum, u16 val)</div><div class='add'>+{</div><div class='add'>+	int addr = phy_package_address(phydev, addr_offset);</div><div class='add'>+</div><div class='add'>+	if (addr &lt; 0)</div><div class='add'>+		return addr;</div><div class='add'>+</div><div class='add'>+	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return mmd_phy_write(phydev-&gt;mdio.bus, addr, phydev-&gt;is_c45, devad,</div><div class='add'>+			     regnum, val);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(__phy_package_write_mmd);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * phy_package_write_mmd - write MMD reg relative to PHY package base addr</div><div class='add'>+ * @phydev: The phy_device struct</div><div class='add'>+ * @addr_offset: The offset to be added to PHY package base_addr</div><div class='add'>+ * @devad: The MMD to write to</div><div class='add'>+ * @regnum: The register on the MMD to write</div><div class='add'>+ * @val: value to write to @regnum</div><div class='add'>+ *</div><div class='add'>+ * Convenience helper for writing a register of an MMD on a given PHY</div><div class='add'>+ * using the PHY package base address. The base address is added to</div><div class='add'>+ * the addr_offset value.</div><div class='add'>+ *</div><div class='add'>+ * Same calling rules as for phy_write();</div><div class='add'>+ *</div><div class='add'>+ * NOTE: It's assumed that the entire PHY package is either C22 or C45.</div><div class='add'>+ */</div><div class='add'>+int phy_package_write_mmd(struct phy_device *phydev,</div><div class='add'>+			  unsigned int addr_offset, int devad,</div><div class='add'>+			  u32 regnum, u16 val)</div><div class='add'>+{</div><div class='add'>+	int addr = phy_package_address(phydev, addr_offset);</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (addr &lt; 0)</div><div class='add'>+		return addr;</div><div class='add'>+</div><div class='add'>+	if (regnum &gt; (u16)~0 || devad &gt; 32)</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	phy_lock_mdio_bus(phydev);</div><div class='add'>+	ret = mmd_phy_write(phydev-&gt;mdio.bus, addr, phydev-&gt;is_c45, devad,</div><div class='add'>+			    regnum, val);</div><div class='add'>+	phy_unlock_mdio_bus(phydev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL(phy_package_write_mmd);</div><div class='add'>+</div><div class='add'>+/**</div><div class='ctx'>  * phy_modify_changed - Function for modifying a PHY register</div><div class='ctx'>  * @phydev: the phy_device struct</div><div class='ctx'>  * @regnum: register number to modify</div><div class='head'>diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c<br/>index a5fa077650e8..3376e58e2b88 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/phy.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/phy.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/phy.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy.c</a></div><div class='hunk'>@@ -325,9 +325,13 @@ EXPORT_SYMBOL(phy_ethtool_ksettings_get);</div><div class='ctx'> int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)</div><div class='ctx'> {</div><div class='ctx'> 	struct mii_ioctl_data *mii_data = if_mii(ifr);</div><div class='add'>+	struct kernel_hwtstamp_config kernel_cfg;</div><div class='add'>+	struct netlink_ext_ack extack = {};</div><div class='ctx'> 	u16 val = mii_data-&gt;val_in;</div><div class='ctx'> 	bool change_autoneg = false;</div><div class='add'>+	struct hwtstamp_config cfg;</div><div class='ctx'> 	int prtad, devad;</div><div class='add'>+	int ret;</div><div class='ctx'> </div><div class='ctx'> 	switch (cmd) {</div><div class='ctx'> 	case SIOCGMIIPHY:</div><div class='hunk'>@@ -411,8 +415,21 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='ctx'> 	case SIOCSHWTSTAMP:</div><div class='del'>-		if (phydev-&gt;mii_ts &amp;&amp; phydev-&gt;mii_ts-&gt;hwtstamp)</div><div class='del'>-			return phydev-&gt;mii_ts-&gt;hwtstamp(phydev-&gt;mii_ts, ifr);</div><div class='add'>+		if (phydev-&gt;mii_ts &amp;&amp; phydev-&gt;mii_ts-&gt;hwtstamp) {</div><div class='add'>+			if (copy_from_user(&amp;cfg, ifr-&gt;ifr_data, sizeof(cfg)))</div><div class='add'>+				return -EFAULT;</div><div class='add'>+</div><div class='add'>+			hwtstamp_config_to_kernel(&amp;kernel_cfg, &amp;cfg);</div><div class='add'>+			ret = phydev-&gt;mii_ts-&gt;hwtstamp(phydev-&gt;mii_ts, &amp;kernel_cfg, &amp;extack);</div><div class='add'>+			if (ret)</div><div class='add'>+				return ret;</div><div class='add'>+</div><div class='add'>+			hwtstamp_config_from_kernel(&amp;cfg, &amp;kernel_cfg);</div><div class='add'>+			if (copy_to_user(ifr-&gt;ifr_data, &amp;cfg, sizeof(cfg)))</div><div class='add'>+				return -EFAULT;</div><div class='add'>+</div><div class='add'>+			return 0;</div><div class='add'>+		}</div><div class='ctx'> 		fallthrough;</div><div class='ctx'> </div><div class='ctx'> 	default:</div><div class='hunk'>@@ -469,7 +486,7 @@ int __phy_hwtstamp_get(struct phy_device *phydev,</div><div class='ctx'> 	if (!phydev)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	return phy_mii_ioctl(phydev, config-&gt;ifr, SIOCGHWTSTAMP);</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='hunk'>@@ -486,7 +503,10 @@ int __phy_hwtstamp_set(struct phy_device *phydev,</div><div class='ctx'> 	if (!phydev)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	return phy_mii_ioctl(phydev, config-&gt;ifr, SIOCSHWTSTAMP);</div><div class='add'>+	if (phydev-&gt;mii_ts &amp;&amp; phydev-&gt;mii_ts-&gt;hwtstamp)</div><div class='add'>+		return phydev-&gt;mii_ts-&gt;hwtstamp(phydev-&gt;mii_ts, config, extack);</div><div class='add'>+</div><div class='add'>+	return -EOPNOTSUPP;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /**</div><div class='head'>diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c<br/>index 2ce74593d6e4..3611ea64875e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/phy_device.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/phy_device.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/phy_device.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phy_device.c</a></div><div class='hunk'>@@ -654,6 +654,7 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,</div><div class='ctx'> 	mdiodev-&gt;flags = MDIO_DEVICE_FLAG_PHY;</div><div class='ctx'> 	mdiodev-&gt;device_free = phy_mdio_device_free;</div><div class='ctx'> 	mdiodev-&gt;device_remove = phy_mdio_device_remove;</div><div class='add'>+	mdiodev-&gt;reset_state = -1;</div><div class='ctx'> </div><div class='ctx'> 	dev-&gt;speed = SPEED_UNKNOWN;</div><div class='ctx'> 	dev-&gt;duplex = DUPLEX_UNKNOWN;</div><div class='hunk'>@@ -1235,18 +1236,19 @@ int phy_init_hw(struct phy_device *phydev)</div><div class='ctx'> </div><div class='ctx'> 	if (phydev-&gt;drv-&gt;soft_reset) {</div><div class='ctx'> 		ret = phydev-&gt;drv-&gt;soft_reset(phydev);</div><div class='add'>+		if (ret &lt; 0)</div><div class='add'>+			return ret;</div><div class='add'>+</div><div class='ctx'> 		/* see comment in genphy_soft_reset for an explanation */</div><div class='del'>-		if (!ret)</div><div class='del'>-			phydev-&gt;suspended = 0;</div><div class='add'>+		phydev-&gt;suspended = 0;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (ret &lt; 0)</div><div class='del'>-		return ret;</div><div class='del'>-</div><div class='ctx'> 	ret = phy_scan_fixups(phydev);</div><div class='ctx'> 	if (ret &lt; 0)</div><div class='ctx'> 		return ret;</div><div class='ctx'> </div><div class='add'>+	phy_interface_zero(phydev-&gt;possible_interfaces);</div><div class='add'>+</div><div class='ctx'> 	if (phydev-&gt;drv-&gt;config_init) {</div><div class='ctx'> 		ret = phydev-&gt;drv-&gt;config_init(phydev);</div><div class='ctx'> 		if (ret &lt; 0)</div><div class='hunk'>@@ -1548,7 +1550,8 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,</div><div class='ctx'> 		goto error;</div><div class='ctx'> </div><div class='ctx'> 	phy_resume(phydev);</div><div class='del'>-	phy_led_triggers_register(phydev);</div><div class='add'>+	if (!phydev-&gt;is_on_sfp_module)</div><div class='add'>+		phy_led_triggers_register(phydev);</div><div class='ctx'> </div><div class='ctx'> 	/**</div><div class='ctx'> 	 * If the external phy used by current mac interface is managed by</div><div class='hunk'>@@ -1649,20 +1652,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);</div><div class='ctx'> /**</div><div class='ctx'>  * phy_package_join - join a common PHY group</div><div class='ctx'>  * @phydev: target phy_device struct</div><div class='del'>- * @addr: cookie and PHY address for global register access</div><div class='add'>+ * @base_addr: cookie and base PHY address of PHY package for offset</div><div class='add'>+ *   calculation of global register access</div><div class='ctx'>  * @priv_size: if non-zero allocate this amount of bytes for private data</div><div class='ctx'>  *</div><div class='ctx'>  * This joins a PHY group and provides a shared storage for all phydevs in</div><div class='ctx'>  * this group. This is intended to be used for packages which contain</div><div class='ctx'>  * more than one PHY, for example a quad PHY transceiver.</div><div class='ctx'>  *</div><div class='del'>- * The addr parameter serves as a cookie which has to have the same value</div><div class='del'>- * for all members of one group and as a PHY address to access generic</div><div class='del'>- * registers of a PHY package. Usually, one of the PHY addresses of the</div><div class='del'>- * different PHYs in the package provides access to these global registers.</div><div class='add'>+ * The base_addr parameter serves as cookie which has to have the same values</div><div class='add'>+ * for all members of one group and as the base PHY address of the PHY package</div><div class='add'>+ * for offset calculation to access generic registers of a PHY package.</div><div class='add'>+ * Usually, one of the PHY addresses of the different PHYs in the package</div><div class='add'>+ * provides access to these global registers.</div><div class='ctx'>  * The address which is given here, will be used in the phy_package_read()</div><div class='del'>- * and phy_package_write() convenience functions. If your PHY doesn't have</div><div class='del'>- * global registers you can just pick any of the PHY addresses.</div><div class='add'>+ * and phy_package_write() convenience functions as base and added to the</div><div class='add'>+ * passed offset in those functions.</div><div class='ctx'>  *</div><div class='ctx'>  * This will set the shared pointer of the phydev to the shared storage.</div><div class='ctx'>  * If this is the first call for a this cookie the shared storage will be</div><div class='hunk'>@@ -1672,17 +1677,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);</div><div class='ctx'>  * Returns &lt; 1 on error, 0 on success. Esp. calling phy_package_join()</div><div class='ctx'>  * with the same cookie but a different priv_size is an error.</div><div class='ctx'>  */</div><div class='del'>-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)</div><div class='add'>+int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct mii_bus *bus = phydev-&gt;mdio.bus;</div><div class='ctx'> 	struct phy_package_shared *shared;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	if (addr &lt; 0 || addr &gt;= PHY_MAX_ADDR)</div><div class='add'>+	if (base_addr &lt; 0 || base_addr &gt;= PHY_MAX_ADDR)</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;bus-&gt;shared_lock);</div><div class='del'>-	shared = bus-&gt;shared[addr];</div><div class='add'>+	shared = bus-&gt;shared[base_addr];</div><div class='ctx'> 	if (!shared) {</div><div class='ctx'> 		ret = -ENOMEM;</div><div class='ctx'> 		shared = kzalloc(sizeof(*shared), GFP_KERNEL);</div><div class='hunk'>@@ -1694,9 +1699,9 @@ int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)</div><div class='ctx'> 				goto err_free;</div><div class='ctx'> 			shared-&gt;priv_size = priv_size;</div><div class='ctx'> 		}</div><div class='del'>-		shared-&gt;addr = addr;</div><div class='add'>+		shared-&gt;base_addr = base_addr;</div><div class='ctx'> 		refcount_set(&amp;shared-&gt;refcnt, 1);</div><div class='del'>-		bus-&gt;shared[addr] = shared;</div><div class='add'>+		bus-&gt;shared[base_addr] = shared;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ret = -EINVAL;</div><div class='ctx'> 		if (priv_size &amp;&amp; priv_size != shared-&gt;priv_size)</div><div class='hunk'>@@ -1734,7 +1739,7 @@ void phy_package_leave(struct phy_device *phydev)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='ctx'> 	if (refcount_dec_and_mutex_lock(&amp;shared-&gt;refcnt, &amp;bus-&gt;shared_lock)) {</div><div class='del'>-		bus-&gt;shared[shared-&gt;addr] = NULL;</div><div class='add'>+		bus-&gt;shared[shared-&gt;base_addr] = NULL;</div><div class='ctx'> 		mutex_unlock(&amp;bus-&gt;shared_lock);</div><div class='ctx'> 		kfree(shared-&gt;priv);</div><div class='ctx'> 		kfree(shared);</div><div class='hunk'>@@ -1753,7 +1758,8 @@ static void devm_phy_package_leave(struct device *dev, void *res)</div><div class='ctx'>  * devm_phy_package_join - resource managed phy_package_join()</div><div class='ctx'>  * @dev: device that is registering this PHY package</div><div class='ctx'>  * @phydev: target phy_device struct</div><div class='del'>- * @addr: cookie and PHY address for global register access</div><div class='add'>+ * @base_addr: cookie and base PHY address of PHY package for offset</div><div class='add'>+ *   calculation of global register access</div><div class='ctx'>  * @priv_size: if non-zero allocate this amount of bytes for private data</div><div class='ctx'>  *</div><div class='ctx'>  * Managed phy_package_join(). Shared storage fetched by this function,</div><div class='hunk'>@@ -1761,7 +1767,7 @@ static void devm_phy_package_leave(struct device *dev, void *res)</div><div class='ctx'>  * phy_package_join() for more information.</div><div class='ctx'>  */</div><div class='ctx'> int devm_phy_package_join(struct device *dev, struct phy_device *phydev,</div><div class='del'>-			  int addr, size_t priv_size)</div><div class='add'>+			  int base_addr, size_t priv_size)</div><div class='ctx'> {</div><div class='ctx'> 	struct phy_device **ptr;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -1771,7 +1777,7 @@ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,</div><div class='ctx'> 	if (!ptr)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	ret = phy_package_join(phydev, addr, priv_size);</div><div class='add'>+	ret = phy_package_join(phydev, base_addr, priv_size);</div><div class='ctx'> </div><div class='ctx'> 	if (!ret) {</div><div class='ctx'> 		*ptr = phydev;</div><div class='hunk'>@@ -1817,7 +1823,8 @@ void phy_detach(struct phy_device *phydev)</div><div class='ctx'> 	}</div><div class='ctx'> 	phydev-&gt;phylink = NULL;</div><div class='ctx'> </div><div class='del'>-	phy_led_triggers_unregister(phydev);</div><div class='add'>+	if (!phydev-&gt;is_on_sfp_module)</div><div class='add'>+		phy_led_triggers_unregister(phydev);</div><div class='ctx'> </div><div class='ctx'> 	if (phydev-&gt;mdio.dev.driver)</div><div class='ctx'> 		module_put(phydev-&gt;mdio.dev.driver-&gt;owner);</div><div class='head'>diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c<br/>index 25c19496a336..ed0b4ccaa6a6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/phylink.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/phylink.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/phylink.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/phylink.c</a></div><div class='hunk'>@@ -121,6 +121,19 @@ do {									\</div><div class='ctx'> })</div><div class='ctx'> #endif</div><div class='ctx'> </div><div class='add'>+static const phy_interface_t phylink_sfp_interface_preference[] = {</div><div class='add'>+	PHY_INTERFACE_MODE_25GBASER,</div><div class='add'>+	PHY_INTERFACE_MODE_USXGMII,</div><div class='add'>+	PHY_INTERFACE_MODE_10GBASER,</div><div class='add'>+	PHY_INTERFACE_MODE_5GBASER,</div><div class='add'>+	PHY_INTERFACE_MODE_2500BASEX,</div><div class='add'>+	PHY_INTERFACE_MODE_SGMII,</div><div class='add'>+	PHY_INTERFACE_MODE_1000BASEX,</div><div class='add'>+	PHY_INTERFACE_MODE_100BASEX,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);</div><div class='add'>+</div><div class='ctx'> /**</div><div class='ctx'>  * phylink_set_port_modes() - set the port type modes in the ethtool mask</div><div class='ctx'>  * @mask: ethtool link mode mask</div><div class='hunk'>@@ -689,28 +702,48 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,</div><div class='ctx'> 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int phylink_validate_mask(struct phylink *pl, unsigned long *supported,</div><div class='add'>+static void phylink_validate_one(struct phylink *pl, struct phy_device *phy,</div><div class='add'>+				 const unsigned long *supported,</div><div class='add'>+				 const struct phylink_link_state *state,</div><div class='add'>+				 phy_interface_t interface,</div><div class='add'>+				 unsigned long *accum_supported,</div><div class='add'>+				 unsigned long *accum_advertising)</div><div class='add'>+{</div><div class='add'>+	__ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_supported);</div><div class='add'>+	struct phylink_link_state tmp_state;</div><div class='add'>+</div><div class='add'>+	linkmode_copy(tmp_supported, supported);</div><div class='add'>+</div><div class='add'>+	tmp_state = *state;</div><div class='add'>+	tmp_state.interface = interface;</div><div class='add'>+</div><div class='add'>+	if (phy)</div><div class='add'>+		tmp_state.rate_matching = phy_get_rate_matching(phy, interface);</div><div class='add'>+</div><div class='add'>+	if (!phylink_validate_mac_and_pcs(pl, tmp_supported, &amp;tmp_state)) {</div><div class='add'>+		phylink_dbg(pl, " interface %u (%s) rate match %s supports %*pbl\n",</div><div class='add'>+			    interface, phy_modes(interface),</div><div class='add'>+			    phy_rate_matching_to_str(tmp_state.rate_matching),</div><div class='add'>+			    __ETHTOOL_LINK_MODE_MASK_NBITS, tmp_supported);</div><div class='add'>+</div><div class='add'>+		linkmode_or(accum_supported, accum_supported, tmp_supported);</div><div class='add'>+		linkmode_or(accum_advertising, accum_advertising,</div><div class='add'>+			    tmp_state.advertising);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,</div><div class='add'>+				 unsigned long *supported,</div><div class='ctx'> 				 struct phylink_link_state *state,</div><div class='ctx'> 				 const unsigned long *interfaces)</div><div class='ctx'> {</div><div class='ctx'> 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_adv) = { 0, };</div><div class='ctx'> 	__ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, };</div><div class='del'>-	__ETHTOOL_DECLARE_LINK_MODE_MASK(s);</div><div class='del'>-	struct phylink_link_state t;</div><div class='del'>-	int intf;</div><div class='del'>-</div><div class='del'>-	for (intf = 0; intf &lt; PHY_INTERFACE_MODE_MAX; intf++) {</div><div class='del'>-		if (test_bit(intf, interfaces)) {</div><div class='del'>-			linkmode_copy(s, supported);</div><div class='del'>-</div><div class='del'>-			t = *state;</div><div class='del'>-			t.interface = intf;</div><div class='del'>-			if (!phylink_validate_mac_and_pcs(pl, s, &amp;t)) {</div><div class='del'>-				linkmode_or(all_s, all_s, s);</div><div class='del'>-				linkmode_or(all_adv, all_adv, t.advertising);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='add'>+	int interface;</div><div class='add'>+</div><div class='add'>+	for_each_set_bit(interface, interfaces, PHY_INTERFACE_MODE_MAX)</div><div class='add'>+		phylink_validate_one(pl, phy, supported, state, interface,</div><div class='add'>+				     all_s, all_adv);</div><div class='ctx'> </div><div class='ctx'> 	linkmode_copy(supported, all_s);</div><div class='ctx'> 	linkmode_copy(state-&gt;advertising, all_adv);</div><div class='hunk'>@@ -724,7 +757,8 @@ static int phylink_validate(struct phylink *pl, unsigned long *supported,</div><div class='ctx'> 	const unsigned long *interfaces = pl-&gt;config-&gt;supported_interfaces;</div><div class='ctx'> </div><div class='ctx'> 	if (state-&gt;interface == PHY_INTERFACE_MODE_NA)</div><div class='del'>-		return phylink_validate_mask(pl, supported, state, interfaces);</div><div class='add'>+		return phylink_validate_mask(pl, NULL, supported, state,</div><div class='add'>+					     interfaces);</div><div class='ctx'> </div><div class='ctx'> 	if (!test_bit(state-&gt;interface, interfaces))</div><div class='ctx'> 		return -EINVAL;</div><div class='hunk'>@@ -805,7 +839,7 @@ static int phylink_parse_fixedlink(struct phylink *pl,</div><div class='ctx'> 		phylink_warn(pl, "fixed link specifies half duplex for %dMbps link?\n",</div><div class='ctx'> 			     pl-&gt;link_config.speed);</div><div class='ctx'> </div><div class='del'>-	bitmap_fill(pl-&gt;supported, __ETHTOOL_LINK_MODE_MASK_NBITS);</div><div class='add'>+	linkmode_fill(pl-&gt;supported);</div><div class='ctx'> 	linkmode_copy(pl-&gt;link_config.advertising, pl-&gt;supported);</div><div class='ctx'> 	phylink_validate(pl, pl-&gt;supported, &amp;pl-&gt;link_config);</div><div class='ctx'> </div><div class='hunk'>@@ -849,6 +883,7 @@ static int phylink_parse_mode(struct phylink *pl,</div><div class='ctx'> {</div><div class='ctx'> 	struct fwnode_handle *dn;</div><div class='ctx'> 	const char *managed;</div><div class='add'>+	unsigned long caps;</div><div class='ctx'> </div><div class='ctx'> 	dn = fwnode_get_named_child_node(fwnode, "fixed-link");</div><div class='ctx'> 	if (dn || fwnode_property_present(fwnode, "fixed-link"))</div><div class='hunk'>@@ -881,80 +916,18 @@ static int phylink_parse_mode(struct phylink *pl,</div><div class='ctx'> 		case PHY_INTERFACE_MODE_RGMII_RXID:</div><div class='ctx'> 		case PHY_INTERFACE_MODE_RGMII_TXID:</div><div class='ctx'> 		case PHY_INTERFACE_MODE_RTBI:</div><div class='del'>-			phylink_set(pl-&gt;supported, 10baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseT_Full);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		case PHY_INTERFACE_MODE_1000BASEX:</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseX_Full);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		case PHY_INTERFACE_MODE_2500BASEX:</div><div class='del'>-			phylink_set(pl-&gt;supported, 2500baseX_Full);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		case PHY_INTERFACE_MODE_5GBASER:</div><div class='del'>-			phylink_set(pl-&gt;supported, 5000baseT_Full);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		case PHY_INTERFACE_MODE_25GBASER:</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseCR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseKR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseSR_Full);</div><div class='del'>-			fallthrough;</div><div class='ctx'> 		case PHY_INTERFACE_MODE_USXGMII:</div><div class='ctx'> 		case PHY_INTERFACE_MODE_10GKR:</div><div class='ctx'> 		case PHY_INTERFACE_MODE_10GBASER:</div><div class='del'>-			phylink_set(pl-&gt;supported, 10baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseT_Half);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseX_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 1000baseKX_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 2500baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 2500baseX_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 5000baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseT_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseKR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseKX4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseCR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseSR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseLR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseLRM_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 10000baseER_Full);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='ctx'> 		case PHY_INTERFACE_MODE_XLGMII:</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseCR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseKR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 25000baseSR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 40000baseKR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 40000baseCR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 40000baseSR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 40000baseLR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseCR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseKR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseSR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseKR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseSR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseCR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseLR_ER_FR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 50000baseDR_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseKR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseSR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseCR4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseLR4_ER4_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseKR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseSR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseCR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseLR2_ER2_FR2_Full);</div><div class='del'>-			phylink_set(pl-&gt;supported, 100000baseDR2_Full);</div><div class='add'>+			caps = ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE);</div><div class='add'>+			caps = phylink_get_capabilities(pl-&gt;link_config.interface, caps,</div><div class='add'>+							RATE_MATCH_NONE);</div><div class='add'>+			phylink_caps_to_linkmodes(pl-&gt;supported, caps);</div><div class='ctx'> 			break;</div><div class='ctx'> </div><div class='ctx'> 		default:</div><div class='hunk'>@@ -1101,6 +1074,72 @@ static void phylink_pcs_an_restart(struct phylink *pl)</div><div class='ctx'> 		pl-&gt;pcs-&gt;ops-&gt;pcs_an_restart(pl-&gt;pcs);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+/**</div><div class='add'>+ * phylink_pcs_neg_mode() - helper to determine PCS inband mode</div><div class='add'>+ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.</div><div class='add'>+ * @interface: interface mode to be used</div><div class='add'>+ * @advertising: adertisement ethtool link mode mask</div><div class='add'>+ *</div><div class='add'>+ * Determines the negotiation mode to be used by the PCS, and returns</div><div class='add'>+ * one of:</div><div class='add'>+ *</div><div class='add'>+ * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband</div><div class='add'>+ * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)</div><div class='add'>+ *   will be used.</div><div class='add'>+ * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg</div><div class='add'>+ *   disabled</div><div class='add'>+ * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled</div><div class='add'>+ *</div><div class='add'>+ * Note: this is for cases where the PCS itself is involved in negotiation</div><div class='add'>+ * (e.g. Clause 37, SGMII and similar) not Clause 73.</div><div class='add'>+ */</div><div class='add'>+static unsigned int phylink_pcs_neg_mode(unsigned int mode,</div><div class='add'>+					 phy_interface_t interface,</div><div class='add'>+					 const unsigned long *advertising)</div><div class='add'>+{</div><div class='add'>+	unsigned int neg_mode;</div><div class='add'>+</div><div class='add'>+	switch (interface) {</div><div class='add'>+	case PHY_INTERFACE_MODE_SGMII:</div><div class='add'>+	case PHY_INTERFACE_MODE_QSGMII:</div><div class='add'>+	case PHY_INTERFACE_MODE_QUSGMII:</div><div class='add'>+	case PHY_INTERFACE_MODE_USXGMII:</div><div class='add'>+		/* These protocols are designed for use with a PHY which</div><div class='add'>+		 * communicates its negotiation result back to the MAC via</div><div class='add'>+		 * inband communication. Note: there exist PHYs that run</div><div class='add'>+		 * with SGMII but do not send the inband data.</div><div class='add'>+		 */</div><div class='add'>+		if (!phylink_autoneg_inband(mode))</div><div class='add'>+			neg_mode = PHYLINK_PCS_NEG_OUTBAND;</div><div class='add'>+		else</div><div class='add'>+			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	case PHY_INTERFACE_MODE_1000BASEX:</div><div class='add'>+	case PHY_INTERFACE_MODE_2500BASEX:</div><div class='add'>+		/* 1000base-X is designed for use media-side for Fibre</div><div class='add'>+		 * connections, and thus the Autoneg bit needs to be</div><div class='add'>+		 * taken into account. We also do this for 2500base-X</div><div class='add'>+		 * as well, but drivers may not support this, so may</div><div class='add'>+		 * need to override this.</div><div class='add'>+		 */</div><div class='add'>+		if (!phylink_autoneg_inband(mode))</div><div class='add'>+			neg_mode = PHYLINK_PCS_NEG_OUTBAND;</div><div class='add'>+		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,</div><div class='add'>+					   advertising))</div><div class='add'>+			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;</div><div class='add'>+		else</div><div class='add'>+			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;</div><div class='add'>+		break;</div><div class='add'>+</div><div class='add'>+	default:</div><div class='add'>+		neg_mode = PHYLINK_PCS_NEG_NONE;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return neg_mode;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void phylink_major_config(struct phylink *pl, bool restart,</div><div class='ctx'> 				  const struct phylink_link_state *state)</div><div class='ctx'> {</div><div class='hunk'>@@ -1640,7 +1679,7 @@ struct phylink *phylink_create(struct phylink_config *config,</div><div class='ctx'> 	__set_bit(PHYLINK_DISABLE_STOPPED, &amp;pl-&gt;phylink_disable_state);</div><div class='ctx'> 	timer_setup(&amp;pl-&gt;link_poll, phylink_fixed_poll, 0);</div><div class='ctx'> </div><div class='del'>-	bitmap_fill(pl-&gt;supported, __ETHTOOL_LINK_MODE_MASK_NBITS);</div><div class='add'>+	linkmode_fill(pl-&gt;supported);</div><div class='ctx'> 	linkmode_copy(pl-&gt;link_config.advertising, pl-&gt;supported);</div><div class='ctx'> 	phylink_validate(pl, pl-&gt;supported, &amp;pl-&gt;link_config);</div><div class='ctx'> </div><div class='hunk'>@@ -1739,31 +1778,55 @@ static void phylink_phy_change(struct phy_device *phydev, bool up)</div><div class='ctx'> 		    phylink_pause_to_str(pl-&gt;phy_state.pause));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,</div><div class='del'>-			       phy_interface_t interface)</div><div class='add'>+static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,</div><div class='add'>+				unsigned long *supported,</div><div class='add'>+				struct phylink_link_state *state)</div><div class='ctx'> {</div><div class='del'>-	struct phylink_link_state config;</div><div class='del'>-	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);</div><div class='del'>-	char *irq_str;</div><div class='del'>-	int ret;</div><div class='add'>+	DECLARE_PHY_INTERFACE_MASK(interfaces);</div><div class='ctx'> </div><div class='del'>-	/*</div><div class='del'>-	 * This is the new way of dealing with flow control for PHYs,</div><div class='del'>-	 * as described by Timur Tabi in commit 529ed1275263 ("net: phy:</div><div class='del'>-	 * phy drivers should not set SUPPORTED_[Asym_]Pause") except</div><div class='del'>-	 * using our validate call to the MAC, we rely upon the MAC</div><div class='del'>-	 * clearing the bits from both supported and advertising fields.</div><div class='add'>+	/* If the PHY provides a bitmap of the interfaces it will be using</div><div class='add'>+	 * depending on the negotiated media speeds, use this to validate</div><div class='add'>+	 * which ethtool link modes can be used.</div><div class='ctx'> 	 */</div><div class='del'>-	phy_support_asym_pause(phy);</div><div class='add'>+	if (!phy_interface_empty(phy-&gt;possible_interfaces)) {</div><div class='add'>+		/* We only care about the union of the PHY's interfaces and</div><div class='add'>+		 * those which the host supports.</div><div class='add'>+		 */</div><div class='add'>+		phy_interface_and(interfaces, phy-&gt;possible_interfaces,</div><div class='add'>+				  pl-&gt;config-&gt;supported_interfaces);</div><div class='ctx'> </div><div class='del'>-	memset(&amp;config, 0, sizeof(config));</div><div class='del'>-	linkmode_copy(supported, phy-&gt;supported);</div><div class='del'>-	linkmode_copy(config.advertising, phy-&gt;advertising);</div><div class='add'>+		if (phy_interface_empty(interfaces)) {</div><div class='add'>+			phylink_err(pl, "PHY has no common interfaces\n");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (phy_on_sfp(phy)) {</div><div class='add'>+			/* If the PHY is on a SFP, limit the interfaces to</div><div class='add'>+			 * those that can be used with a SFP module.</div><div class='add'>+			 */</div><div class='add'>+			phy_interface_and(interfaces, interfaces,</div><div class='add'>+					  phylink_sfp_interfaces);</div><div class='add'>+</div><div class='add'>+			if (phy_interface_empty(interfaces)) {</div><div class='add'>+				phylink_err(pl, "SFP PHY's possible interfaces becomes empty\n");</div><div class='add'>+				return -EINVAL;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		phylink_dbg(pl, "PHY %s uses interfaces %*pbl, validating %*pbl\n",</div><div class='add'>+			    phydev_name(phy),</div><div class='add'>+			    (int)PHY_INTERFACE_MODE_MAX,</div><div class='add'>+			    phy-&gt;possible_interfaces,</div><div class='add'>+			    (int)PHY_INTERFACE_MODE_MAX, interfaces);</div><div class='add'>+</div><div class='add'>+		return phylink_validate_mask(pl, phy, supported, state,</div><div class='add'>+					     interfaces);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	/* Check whether we would use rate matching for the proposed interface</div><div class='ctx'> 	 * mode.</div><div class='ctx'> 	 */</div><div class='del'>-	config.rate_matching = phy_get_rate_matching(phy, interface);</div><div class='add'>+	state-&gt;rate_matching = phy_get_rate_matching(phy, state-&gt;interface);</div><div class='ctx'> </div><div class='ctx'> 	/* Clause 45 PHYs may switch their Serdes lane between, e.g. 10GBASE-R,</div><div class='ctx'> 	 * 5GBASE-R, 2500BASE-X and SGMII if they are not using rate matching.</div><div class='hunk'>@@ -1776,15 +1839,38 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,</div><div class='ctx'> 	 * against all interface modes, which may lead to more ethtool link</div><div class='ctx'> 	 * modes being advertised than are actually supported.</div><div class='ctx'> 	 */</div><div class='del'>-	if (phy-&gt;is_c45 &amp;&amp; config.rate_matching == RATE_MATCH_NONE &amp;&amp;</div><div class='del'>-	    interface != PHY_INTERFACE_MODE_RXAUI &amp;&amp;</div><div class='del'>-	    interface != PHY_INTERFACE_MODE_XAUI &amp;&amp;</div><div class='del'>-	    interface != PHY_INTERFACE_MODE_USXGMII)</div><div class='del'>-		config.interface = PHY_INTERFACE_MODE_NA;</div><div class='del'>-	else</div><div class='del'>-		config.interface = interface;</div><div class='add'>+	if (phy-&gt;is_c45 &amp;&amp; state-&gt;rate_matching == RATE_MATCH_NONE &amp;&amp;</div><div class='add'>+	    state-&gt;interface != PHY_INTERFACE_MODE_RXAUI &amp;&amp;</div><div class='add'>+	    state-&gt;interface != PHY_INTERFACE_MODE_XAUI &amp;&amp;</div><div class='add'>+	    state-&gt;interface != PHY_INTERFACE_MODE_USXGMII)</div><div class='add'>+		state-&gt;interface = PHY_INTERFACE_MODE_NA;</div><div class='ctx'> </div><div class='del'>-	ret = phylink_validate(pl, supported, &amp;config);</div><div class='add'>+	return phylink_validate(pl, supported, state);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,</div><div class='add'>+			       phy_interface_t interface)</div><div class='add'>+{</div><div class='add'>+	struct phylink_link_state config;</div><div class='add'>+	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);</div><div class='add'>+	char *irq_str;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/*</div><div class='add'>+	 * This is the new way of dealing with flow control for PHYs,</div><div class='add'>+	 * as described by Timur Tabi in commit 529ed1275263 ("net: phy:</div><div class='add'>+	 * phy drivers should not set SUPPORTED_[Asym_]Pause") except</div><div class='add'>+	 * using our validate call to the MAC, we rely upon the MAC</div><div class='add'>+	 * clearing the bits from both supported and advertising fields.</div><div class='add'>+	 */</div><div class='add'>+	phy_support_asym_pause(phy);</div><div class='add'>+</div><div class='add'>+	memset(&amp;config, 0, sizeof(config));</div><div class='add'>+	linkmode_copy(supported, phy-&gt;supported);</div><div class='add'>+	linkmode_copy(config.advertising, phy-&gt;advertising);</div><div class='add'>+	config.interface = interface;</div><div class='add'>+</div><div class='add'>+	ret = phylink_validate_phy(pl, phy, supported, &amp;config);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		phylink_warn(pl, "validation of %s with support %*pb and advertisement %*pb failed: %pe\n",</div><div class='ctx'> 			     phy_modes(config.interface),</div><div class='hunk'>@@ -3005,19 +3091,6 @@ static void phylink_sfp_detach(void *upstream, struct sfp_bus *bus)</div><div class='ctx'> 	pl-&gt;netdev-&gt;sfp_bus = NULL;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static const phy_interface_t phylink_sfp_interface_preference[] = {</div><div class='del'>-	PHY_INTERFACE_MODE_25GBASER,</div><div class='del'>-	PHY_INTERFACE_MODE_USXGMII,</div><div class='del'>-	PHY_INTERFACE_MODE_10GBASER,</div><div class='del'>-	PHY_INTERFACE_MODE_5GBASER,</div><div class='del'>-	PHY_INTERFACE_MODE_2500BASEX,</div><div class='del'>-	PHY_INTERFACE_MODE_SGMII,</div><div class='del'>-	PHY_INTERFACE_MODE_1000BASEX,</div><div class='del'>-	PHY_INTERFACE_MODE_100BASEX,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);</div><div class='del'>-</div><div class='ctx'> static phy_interface_t phylink_choose_sfp_interface(struct phylink *pl,</div><div class='ctx'> 						    const unsigned long *intf)</div><div class='ctx'> {</div><div class='hunk'>@@ -3160,7 +3233,8 @@ static int phylink_sfp_config_optical(struct phylink *pl)</div><div class='ctx'> 	/* For all the interfaces that are supported, reduce the sfp_support</div><div class='ctx'> 	 * mask to only those link modes that can be supported.</div><div class='ctx'> 	 */</div><div class='del'>-	ret = phylink_validate_mask(pl, pl-&gt;sfp_support, &amp;config, interfaces);</div><div class='add'>+	ret = phylink_validate_mask(pl, NULL, pl-&gt;sfp_support, &amp;config,</div><div class='add'>+				    interfaces);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		phylink_err(pl, "unsupported SFP module: validation with support %*pb failed\n",</div><div class='ctx'> 			    __ETHTOOL_LINK_MODE_MASK_NBITS, support);</div><div class='head'>diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c<br/>index 208a9393c2df..db39dec7f247 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/sfp-bus.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/sfp-bus.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/sfp-bus.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/sfp-bus.c</a></div><div class='hunk'>@@ -151,10 +151,6 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,</div><div class='ctx'> 	unsigned int br_min, br_nom, br_max;</div><div class='ctx'> 	__ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = { 0, };</div><div class='ctx'> </div><div class='del'>-	phylink_set(modes, Autoneg);</div><div class='del'>-	phylink_set(modes, Pause);</div><div class='del'>-	phylink_set(modes, Asym_Pause);</div><div class='del'>-</div><div class='ctx'> 	/* Decode the bitrate information to MBd */</div><div class='ctx'> 	br_min = br_nom = br_max = 0;</div><div class='ctx'> 	if (id-&gt;base.br_nominal) {</div><div class='hunk'>@@ -328,7 +324,7 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,</div><div class='ctx'> 	 * modules use 2500Mbaud rather than 3100 or 3200Mbaud for</div><div class='ctx'> 	 * 2500BASE-X, so we allow some slack here.</div><div class='ctx'> 	 */</div><div class='del'>-	if (bitmap_empty(modes, __ETHTOOL_LINK_MODE_MASK_NBITS) &amp;&amp; br_nom) {</div><div class='add'>+	if (linkmode_empty(modes) &amp;&amp; br_nom) {</div><div class='ctx'> 		if (br_min &lt;= 1300 &amp;&amp; br_max &gt;= 1200) {</div><div class='ctx'> 			phylink_set(modes, 1000baseX_Full);</div><div class='ctx'> 			__set_bit(PHY_INTERFACE_MODE_1000BASEX, interfaces);</div><div class='hunk'>@@ -339,6 +335,10 @@ void sfp_parse_support(struct sfp_bus *bus, const struct sfp_eeprom_id *id,</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	phylink_set(modes, Autoneg);</div><div class='add'>+	phylink_set(modes, Pause);</div><div class='add'>+	phylink_set(modes, Asym_Pause);</div><div class='add'>+</div><div class='ctx'> 	if (bus-&gt;sfp_quirk &amp;&amp; bus-&gt;sfp_quirk-&gt;modes)</div><div class='ctx'> 		bus-&gt;sfp_quirk-&gt;modes(id, modes, interfaces);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c<br/>index 5468bd209fab..f75c9eb3958e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/sfp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/sfp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/sfp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/sfp.c</a></div><div class='hunk'>@@ -191,7 +191,7 @@ static const enum gpiod_flags gpio_flags[] = {</div><div class='ctx'>  * R_PHY_RETRY is the number of attempts.</div><div class='ctx'>  */</div><div class='ctx'> #define T_PHY_RETRY		msecs_to_jiffies(50)</div><div class='del'>-#define R_PHY_RETRY		12</div><div class='add'>+#define R_PHY_RETRY		25</div><div class='ctx'> </div><div class='ctx'> /* SFP module presence detection is poor: the three MOD DEF signals are</div><div class='ctx'>  * the same length on the PCB, which means it's possible for MOD DEF 0 to</div><div class='hunk'>@@ -275,6 +275,7 @@ struct sfp {</div><div class='ctx'> 	unsigned int module_power_mW;</div><div class='ctx'> 	unsigned int module_t_start_up;</div><div class='ctx'> 	unsigned int module_t_wait;</div><div class='add'>+	unsigned int phy_t_retry;</div><div class='ctx'> </div><div class='ctx'> 	unsigned int rate_kbd;</div><div class='ctx'> 	unsigned int rs_threshold_kbd;</div><div class='hunk'>@@ -372,18 +373,28 @@ static void sfp_fixup_10gbaset_30m(struct sfp *sfp)</div><div class='ctx'> 	sfp-&gt;id.base.extended_cc = SFF8024_ECC_10GBASE_T_SR;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sfp_fixup_rollball_proto(struct sfp *sfp, unsigned int secs)</div><div class='add'>+static void sfp_fixup_rollball(struct sfp *sfp)</div><div class='ctx'> {</div><div class='ctx'> 	sfp-&gt;mdio_protocol = MDIO_I2C_ROLLBALL;</div><div class='del'>-	sfp-&gt;module_t_wait = msecs_to_jiffies(secs * 1000);</div><div class='add'>+</div><div class='add'>+	/* RollBall modules may disallow access to PHY registers for up to 25</div><div class='add'>+	 * seconds, and the reads return 0xffff before that. Increase the time</div><div class='add'>+	 * between PHY probe retries from 50ms to 1s so that we will wait for</div><div class='add'>+	 * the PHY for a sufficient amount of time.</div><div class='add'>+	 */</div><div class='add'>+	sfp-&gt;phy_t_retry = msecs_to_jiffies(1000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sfp_fixup_fs_10gt(struct sfp *sfp)</div><div class='ctx'> {</div><div class='ctx'> 	sfp_fixup_10gbaset_30m(sfp);</div><div class='add'>+	sfp_fixup_rollball(sfp);</div><div class='ctx'> </div><div class='del'>-	// These SFPs need 4 seconds before the PHY can be accessed</div><div class='del'>-	sfp_fixup_rollball_proto(sfp, 4);</div><div class='add'>+	/* The RollBall fixup is not enough for FS modules, the AQR chip inside</div><div class='add'>+	 * them does not return 0xffff for PHY ID registers in all MMDs for the</div><div class='add'>+	 * while initializing. They need a 4 second wait before accessing PHY.</div><div class='add'>+	 */</div><div class='add'>+	sfp-&gt;module_t_wait = msecs_to_jiffies(4000);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sfp_fixup_halny_gsfp(struct sfp *sfp)</div><div class='hunk'>@@ -395,12 +406,6 @@ static void sfp_fixup_halny_gsfp(struct sfp *sfp)</div><div class='ctx'> 	sfp-&gt;state_hw_mask &amp;= ~(SFP_F_TX_FAULT | SFP_F_LOS);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void sfp_fixup_rollball(struct sfp *sfp)</div><div class='del'>-{</div><div class='del'>-	// Rollball SFPs need 25 seconds before the PHY can be accessed</div><div class='del'>-	sfp_fixup_rollball_proto(sfp, 25);</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void sfp_fixup_rollball_cc(struct sfp *sfp)</div><div class='ctx'> {</div><div class='ctx'> 	sfp_fixup_rollball(sfp);</div><div class='hunk'>@@ -2332,6 +2337,7 @@ static int sfp_sm_mod_probe(struct sfp *sfp, bool report)</div><div class='ctx'> </div><div class='ctx'> 	sfp-&gt;module_t_start_up = T_START_UP;</div><div class='ctx'> 	sfp-&gt;module_t_wait = T_WAIT;</div><div class='add'>+	sfp-&gt;phy_t_retry = T_PHY_RETRY;</div><div class='ctx'> </div><div class='ctx'> 	sfp-&gt;state_ignore_mask = 0;</div><div class='ctx'> </div><div class='hunk'>@@ -2629,7 +2635,11 @@ static void sfp_sm_main(struct sfp *sfp, unsigned int event)</div><div class='ctx'> 		ret = sfp_sm_probe_for_phy(sfp);</div><div class='ctx'> 		if (ret == -ENODEV) {</div><div class='ctx'> 			if (--sfp-&gt;sm_phy_retries) {</div><div class='del'>-				sfp_sm_next(sfp, SFP_S_INIT_PHY, T_PHY_RETRY);</div><div class='add'>+				sfp_sm_next(sfp, SFP_S_INIT_PHY,</div><div class='add'>+					    sfp-&gt;phy_t_retry);</div><div class='add'>+				dev_dbg(sfp-&gt;dev,</div><div class='add'>+					"no PHY detected, %u tries left\n",</div><div class='add'>+					sfp-&gt;sm_phy_retries);</div><div class='ctx'> 				break;</div><div class='ctx'> 			} else {</div><div class='ctx'> 				dev_info(sfp-&gt;dev, "no PHY detected\n");</div><div class='hunk'>@@ -3096,7 +3106,7 @@ static int sfp_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int sfp_remove(struct platform_device *pdev)</div><div class='add'>+static void sfp_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct sfp *sfp = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -3106,8 +3116,6 @@ static int sfp_remove(struct platform_device *pdev)</div><div class='ctx'> 	rtnl_lock();</div><div class='ctx'> 	sfp_sm_event(sfp, SFP_E_REMOVE);</div><div class='ctx'> 	rtnl_unlock();</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void sfp_shutdown(struct platform_device *pdev)</div><div class='hunk'>@@ -3128,7 +3136,7 @@ static void sfp_shutdown(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver sfp_driver = {</div><div class='ctx'> 	.probe = sfp_probe,</div><div class='del'>-	.remove = sfp_remove,</div><div class='add'>+	.remove_new = sfp_remove,</div><div class='ctx'> 	.shutdown = sfp_shutdown,</div><div class='ctx'> 	.driver = {</div><div class='ctx'> 		.name = "sfp",</div><div class='head'>diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c<br/>index 1c7306a1af13..150aea7c9c36 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/phy/smsc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/phy/smsc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/phy/smsc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/phy/smsc.c</a></div><div class='hunk'>@@ -508,7 +508,7 @@ static void smsc_get_strings(struct phy_device *phydev, u8 *data)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(smsc_hw_stats); i++)</div><div class='del'>-		ethtool_sprintf(&amp;data, "%s", smsc_hw_stats[i].string);</div><div class='add'>+		ethtool_puts(&amp;data, smsc_hw_stats[i].string);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static u64 smsc_get_stat(struct phy_device *phydev, int i)</div><div class='head'>diff --git a/drivers/net/ppp/ppp_async.c b/drivers/net/ppp/ppp_async.c<br/>index fbaaa8c102a1..840da924708b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/ppp/ppp_async.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/ppp/ppp_async.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/ppp/ppp_async.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/ppp/ppp_async.c</a></div><div class='hunk'>@@ -533,7 +533,7 @@ ppp_async_encode(struct asyncppp *ap)</div><div class='ctx'> 	proto = get_unaligned_be16(data);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='del'>-	 * LCP packets with code values between 1 (configure-reqest)</div><div class='add'>+	 * LCP packets with code values between 1 (configure-request)</div><div class='ctx'> 	 * and 7 (code-reject) must be sent as though no options</div><div class='ctx'> 	 * had been negotiated.</div><div class='ctx'> 	 */</div><div class='head'>diff --git a/drivers/net/slip/slhc.c b/drivers/net/slip/slhc.c<br/>index ba93bab948e0..18df7ca66198 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/slip/slhc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/slip/slhc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/slip/slhc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/slip/slhc.c</a></div><div class='hunk'>@@ -752,4 +752,5 @@ EXPORT_SYMBOL(slhc_compress);</div><div class='ctx'> EXPORT_SYMBOL(slhc_uncompress);</div><div class='ctx'> EXPORT_SYMBOL(slhc_toss);</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("Compression helpers for SLIP (serial line)");</div><div class='ctx'> MODULE_LICENSE("Dual BSD/GPL");</div><div class='head'>diff --git a/drivers/net/slip/slip.c b/drivers/net/slip/slip.c<br/>index e4280e37fec9..0aba3569ccc0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/slip/slip.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/slip/slip.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/slip/slip.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/slip/slip.c</a></div><div class='hunk'>@@ -1437,5 +1437,6 @@ out:</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> #endif</div><div class='add'>+MODULE_DESCRIPTION("SLIP (serial line) protocol module");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_ALIAS_LDISC(N_SLIP);</div><div class='head'>diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c<br/>index 508d9a392ab1..f575f225d417 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/team/team.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/team/team.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/team/team.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/team/team.c</a></div><div class='hunk'>@@ -281,8 +281,10 @@ static int __team_options_register(struct team *team,</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> inst_rollback:</div><div class='del'>-	for (i--; i &gt;= 0; i--)</div><div class='add'>+	for (i--; i &gt;= 0; i--) {</div><div class='ctx'> 		__team_option_inst_del_option(team, dst_opts[i]);</div><div class='add'>+		list_del(&amp;dst_opts[i]-&gt;list);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	i = option_count;</div><div class='ctx'> alloc_rollback:</div><div class='head'>diff --git a/drivers/net/usb/ax88172a.c b/drivers/net/usb/ax88172a.c<br/>index 3777c7e2e6fc..e47bb125048d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/usb/ax88172a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/usb/ax88172a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/usb/ax88172a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/ax88172a.c</a></div><div class='hunk'>@@ -161,7 +161,9 @@ static int ax88172a_bind(struct usbnet *dev, struct usb_interface *intf)</div><div class='ctx'> 	u8 buf[ETH_ALEN];</div><div class='ctx'> 	struct ax88172a_private *priv;</div><div class='ctx'> </div><div class='del'>-	usbnet_get_endpoints(dev, intf);</div><div class='add'>+	ret = usbnet_get_endpoints(dev, intf);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='ctx'> </div><div class='ctx'> 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);</div><div class='ctx'> 	if (!priv)</div><div class='head'>diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c<br/>index 4ea0e155bb0d..d837c1887416 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/usb/ax88179_178a.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/usb/ax88179_178a.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/usb/ax88179_178a.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/ax88179_178a.c</a></div><div class='hunk'>@@ -173,6 +173,7 @@ struct ax88179_data {</div><div class='ctx'> 	u8 in_pm;</div><div class='ctx'> 	u32 wol_supported;</div><div class='ctx'> 	u32 wolopts;</div><div class='add'>+	u8 disconnecting;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ax88179_int_data {</div><div class='hunk'>@@ -208,6 +209,7 @@ static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);</div><div class='add'>+	struct ax88179_data *ax179_data = dev-&gt;driver_priv;</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(!dev);</div><div class='ctx'> </div><div class='hunk'>@@ -219,7 +221,7 @@ static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,</div><div class='ctx'> 	ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,</div><div class='ctx'> 		 value, index, data, size);</div><div class='ctx'> </div><div class='del'>-	if (unlikely(ret &lt; 0))</div><div class='add'>+	if (unlikely((ret &lt; 0) &amp;&amp; !(ret == -ENODEV &amp;&amp; ax179_data-&gt;disconnecting)))</div><div class='ctx'> 		netdev_warn(dev-&gt;net, "Failed to read reg index 0x%04x: %d\n",</div><div class='ctx'> 			    index, ret);</div><div class='ctx'> </div><div class='hunk'>@@ -231,6 +233,7 @@ static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,</div><div class='ctx'> {</div><div class='ctx'> 	int ret;</div><div class='ctx'> 	int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);</div><div class='add'>+	struct ax88179_data *ax179_data = dev-&gt;driver_priv;</div><div class='ctx'> </div><div class='ctx'> 	BUG_ON(!dev);</div><div class='ctx'> </div><div class='hunk'>@@ -242,7 +245,7 @@ static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,</div><div class='ctx'> 	ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,</div><div class='ctx'> 		 value, index, data, size);</div><div class='ctx'> </div><div class='del'>-	if (unlikely(ret &lt; 0))</div><div class='add'>+	if (unlikely((ret &lt; 0) &amp;&amp; !(ret == -ENODEV &amp;&amp; ax179_data-&gt;disconnecting)))</div><div class='ctx'> 		netdev_warn(dev-&gt;net, "Failed to write reg index 0x%04x: %d\n",</div><div class='ctx'> 			    index, ret);</div><div class='ctx'> </div><div class='hunk'>@@ -492,6 +495,20 @@ static int ax88179_resume(struct usb_interface *intf)</div><div class='ctx'> 	return usbnet_resume(intf);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void ax88179_disconnect(struct usb_interface *intf)</div><div class='add'>+{</div><div class='add'>+	struct usbnet *dev = usb_get_intfdata(intf);</div><div class='add'>+	struct ax88179_data *ax179_data;</div><div class='add'>+</div><div class='add'>+	if (!dev)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	ax179_data = dev-&gt;driver_priv;</div><div class='add'>+	ax179_data-&gt;disconnecting = 1;</div><div class='add'>+</div><div class='add'>+	usbnet_disconnect(intf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void</div><div class='ctx'> ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)</div><div class='ctx'> {</div><div class='hunk'>@@ -1298,8 +1315,6 @@ static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf)</div><div class='ctx'> </div><div class='ctx'> 	netif_set_tso_max_size(dev-&gt;net, 16384);</div><div class='ctx'> </div><div class='del'>-	ax88179_reset(dev);</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -1906,7 +1921,7 @@ static struct usb_driver ax88179_178a_driver = {</div><div class='ctx'> 	.suspend =	ax88179_suspend,</div><div class='ctx'> 	.resume =	ax88179_resume,</div><div class='ctx'> 	.reset_resume =	ax88179_resume,</div><div class='del'>-	.disconnect =	usbnet_disconnect,</div><div class='add'>+	.disconnect =	ax88179_disconnect,</div><div class='ctx'> 	.supports_autosuspend = 1,</div><div class='ctx'> 	.disable_hub_initiated_lpm = 1,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c<br/>index 83b8452220ec..f088ea2ba6f3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/usb/hso.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/usb/hso.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/usb/hso.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/hso.c</a></div><div class='hunk'>@@ -363,7 +363,6 @@ static int disable_net;</div><div class='ctx'> /* driver info */</div><div class='ctx'> static const char driver_name[] = "hso";</div><div class='ctx'> static const char tty_filename[] = "ttyHS";</div><div class='del'>-static const char *version = __FILE__ ": " MOD_AUTHOR;</div><div class='ctx'> /* the usb driver itself (registered in hso_init) */</div><div class='ctx'> static struct usb_driver hso_driver;</div><div class='ctx'> /* serial structures */</div><div class='hunk'>@@ -3228,16 +3227,8 @@ static struct usb_driver hso_driver = {</div><div class='ctx'> </div><div class='ctx'> static int __init hso_init(void)</div><div class='ctx'> {</div><div class='del'>-	int i;</div><div class='ctx'> 	int result;</div><div class='ctx'> </div><div class='del'>-	/* put it in the log */</div><div class='del'>-	pr_info("%s\n", version);</div><div class='del'>-</div><div class='del'>-	/* Initialise the serial table semaphore and table */</div><div class='del'>-	for (i = 0; i &lt; HSO_SERIAL_TTY_MINORS; i++)</div><div class='del'>-		serial_table[i] = NULL;</div><div class='del'>-</div><div class='ctx'> 	/* allocate our driver using the proper amount of supported minors */</div><div class='ctx'> 	tty_drv = tty_alloc_driver(HSO_SERIAL_TTY_MINORS, TTY_DRIVER_REAL_RAW |</div><div class='ctx'> 			TTY_DRIVER_DYNAMIC_DEV);</div><div class='hunk'>@@ -3285,8 +3276,6 @@ err_free_tty:</div><div class='ctx'> </div><div class='ctx'> static void __exit hso_exit(void)</div><div class='ctx'> {</div><div class='del'>-	pr_info("unloaded\n");</div><div class='del'>-</div><div class='ctx'> 	tty_unregister_driver(tty_drv);</div><div class='ctx'> 	/* deregister the usb driver */</div><div class='ctx'> 	usb_deregister(&amp;hso_driver);</div><div class='head'>diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c<br/>index 5add4145d9fc..a6d653ff552a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/usb/lan78xx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/usb/lan78xx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/usb/lan78xx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/lan78xx.c</a></div><div class='hunk'>@@ -1691,8 +1691,6 @@ static int lan78xx_get_eee(struct net_device *net, struct ethtool_eee *edata)</div><div class='ctx'> 	ret = lan78xx_read_reg(dev, MAC_CR, &amp;buf);</div><div class='ctx'> 	if (buf &amp; MAC_CR_EEE_EN_) {</div><div class='ctx'> 		edata-&gt;eee_enabled = true;</div><div class='del'>-		edata-&gt;eee_active = !!(edata-&gt;advertised &amp;</div><div class='del'>-				       edata-&gt;lp_advertised);</div><div class='ctx'> 		edata-&gt;tx_lpi_enabled = true;</div><div class='ctx'> 		/* EEE_TX_LPI_REQ_DLY &amp; tx_lpi_timer are same uSec unit */</div><div class='ctx'> 		ret = lan78xx_read_reg(dev, EEE_TX_LPI_REQ_DLY, &amp;buf);</div><div class='head'>diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c<br/>index 2c5c1e91ded6..0d0672d2a654 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/usb/r8152.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/usb/r8152.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/usb/r8152.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/usb/r8152.c</a></div><div class='hunk'>@@ -3000,6 +3000,8 @@ static void rtl8152_nic_reset(struct r8152 *tp)</div><div class='ctx'> 		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; 1000; i++) {</div><div class='add'>+			if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+				break;</div><div class='ctx'> 			if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) &amp; CR_RST))</div><div class='ctx'> 				break;</div><div class='ctx'> 			usleep_range(100, 400);</div><div class='hunk'>@@ -3329,6 +3331,8 @@ static void rtl_disable(struct r8152 *tp)</div><div class='ctx'> 	rxdy_gated_en(tp, true);</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; 1000; i++) {</div><div class='add'>+		if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+			break;</div><div class='ctx'> 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);</div><div class='ctx'> 		if ((ocp_data &amp; FIFO_EMPTY) == FIFO_EMPTY)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -3336,6 +3340,8 @@ static void rtl_disable(struct r8152 *tp)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; 1000; i++) {</div><div class='add'>+		if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+			break;</div><div class='ctx'> 		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) &amp; TCR0_TX_EMPTY)</div><div class='ctx'> 			break;</div><div class='ctx'> 		usleep_range(1000, 2000);</div><div class='hunk'>@@ -5499,6 +5505,8 @@ static void wait_oob_link_list_ready(struct r8152 *tp)</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; 1000; i++) {</div><div class='add'>+		if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+			break;</div><div class='ctx'> 		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);</div><div class='ctx'> 		if (ocp_data &amp; LINK_LIST_READY)</div><div class='ctx'> 			break;</div><div class='hunk'>@@ -5513,6 +5521,8 @@ static void r8156b_wait_loading_flash(struct r8152 *tp)</div><div class='ctx'> 		int i;</div><div class='ctx'> </div><div class='ctx'> 		for (i = 0; i &lt; 100; i++) {</div><div class='add'>+			if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+				break;</div><div class='ctx'> 			if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) &amp; GPHY_PATCH_DONE)</div><div class='ctx'> 				break;</div><div class='ctx'> 			usleep_range(1000, 2000);</div><div class='hunk'>@@ -5635,6 +5645,8 @@ static int r8153_pre_firmware_1(struct r8152 *tp)</div><div class='ctx'> 	for (i = 0; i &lt; 104; i++) {</div><div class='ctx'> 		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);</div><div class='ctx'> </div><div class='add'>+		if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+			return -ENODEV;</div><div class='ctx'> 		if (!(ocp_data &amp; WTD1_EN))</div><div class='ctx'> 			break;</div><div class='ctx'> 		usleep_range(1000, 2000);</div><div class='hunk'>@@ -5791,6 +5803,8 @@ static void r8153_aldps_en(struct r8152 *tp, bool enable)</div><div class='ctx'> 		data &amp;= ~EN_ALDPS;</div><div class='ctx'> 		ocp_reg_write(tp, OCP_POWER_CFG, data);</div><div class='ctx'> 		for (i = 0; i &lt; 20; i++) {</div><div class='add'>+			if (test_bit(RTL8152_INACCESSIBLE, &amp;tp-&gt;flags))</div><div class='add'>+				return;</div><div class='ctx'> 			usleep_range(1000, 2000);</div><div class='ctx'> 			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) &amp; 0x0100)</div><div class='ctx'> 				break;</div><div class='hunk'>@@ -8397,6 +8411,8 @@ static int rtl8152_pre_reset(struct usb_interface *intf)</div><div class='ctx'> 	struct r8152 *tp = usb_get_intfdata(intf);</div><div class='ctx'> 	struct net_device *netdev;</div><div class='ctx'> </div><div class='add'>+	rtnl_lock();</div><div class='add'>+</div><div class='ctx'> 	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &amp;tp-&gt;flags))</div><div class='ctx'> 		return 0;</div><div class='ctx'> </div><div class='hunk'>@@ -8428,20 +8444,17 @@ static int rtl8152_post_reset(struct usb_interface *intf)</div><div class='ctx'> 	struct sockaddr sa;</div><div class='ctx'> </div><div class='ctx'> 	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &amp;tp-&gt;flags))</div><div class='del'>-		return 0;</div><div class='add'>+		goto exit;</div><div class='ctx'> </div><div class='ctx'> 	rtl_set_accessible(tp);</div><div class='ctx'> </div><div class='ctx'> 	/* reset the MAC address in case of policy change */</div><div class='del'>-	if (determine_ethernet_addr(tp, &amp;sa) &gt;= 0) {</div><div class='del'>-		rtnl_lock();</div><div class='add'>+	if (determine_ethernet_addr(tp, &amp;sa) &gt;= 0)</div><div class='ctx'> 		dev_set_mac_address (tp-&gt;netdev, &amp;sa, NULL);</div><div class='del'>-		rtnl_unlock();</div><div class='del'>-	}</div><div class='ctx'> </div><div class='ctx'> 	netdev = tp-&gt;netdev;</div><div class='ctx'> 	if (!netif_running(netdev))</div><div class='del'>-		return 0;</div><div class='add'>+		goto exit;</div><div class='ctx'> </div><div class='ctx'> 	set_bit(WORK_ENABLE, &amp;tp-&gt;flags);</div><div class='ctx'> 	if (netif_carrier_ok(netdev)) {</div><div class='hunk'>@@ -8460,6 +8473,8 @@ static int rtl8152_post_reset(struct usb_interface *intf)</div><div class='ctx'> 	if (!list_empty(&amp;tp-&gt;rx_done))</div><div class='ctx'> 		napi_schedule(&amp;tp-&gt;napi);</div><div class='ctx'> </div><div class='add'>+exit:</div><div class='add'>+	rtnl_unlock();</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -10034,6 +10049,7 @@ static const struct usb_device_id rtl8152_table[] = {</div><div class='ctx'> 	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },</div><div class='ctx'> 	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },</div><div class='ctx'> 	{ USB_DEVICE(VENDOR_ID_DLINK,   0xb301) },</div><div class='add'>+	{ USB_DEVICE(VENDOR_ID_ASUS,    0x1976) },</div><div class='ctx'> 	{}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -10053,7 +10069,7 @@ static struct usb_driver rtl8152_driver = {</div><div class='ctx'> 	.disable_hub_initiated_lpm = 1,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static int rtl8152_cfgselector_probe(struct usb_device *udev)</div><div class='add'>+static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)</div><div class='ctx'> {</div><div class='ctx'> 	struct usb_host_config *c;</div><div class='ctx'> 	int i, num_configs;</div><div class='hunk'>@@ -10080,19 +10096,13 @@ static int rtl8152_cfgselector_probe(struct usb_device *udev)</div><div class='ctx'> 	if (i == num_configs)</div><div class='ctx'> 		return -ENODEV;</div><div class='ctx'> </div><div class='del'>-	if (usb_set_configuration(udev, c-&gt;desc.bConfigurationValue)) {</div><div class='del'>-		dev_err(&amp;udev-&gt;dev, "Failed to set configuration %d\n",</div><div class='del'>-			c-&gt;desc.bConfigurationValue);</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='add'>+	return c-&gt;desc.bConfigurationValue;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct usb_device_driver rtl8152_cfgselector_driver = {</div><div class='del'>-	.name =		MODULENAME "-cfgselector",</div><div class='del'>-	.probe =	rtl8152_cfgselector_probe,</div><div class='del'>-	.id_table =	rtl8152_table,</div><div class='add'>+	.name =	MODULENAME "-cfgselector",</div><div class='add'>+	.choose_configuration = rtl8152_cfgselector_choose_configuration,</div><div class='add'>+	.id_table = rtl8152_table,</div><div class='ctx'> 	.generic_subclass = 1,</div><div class='ctx'> 	.supports_autosuspend = 1,</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/veth.c b/drivers/net/veth.c<br/>index 57efb3454c57..578e36ea1589 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/veth.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/veth.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/veth.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/veth.c</a></div><div class='hunk'>@@ -790,7 +790,8 @@ static int veth_convert_skb_to_xdp_buff(struct veth_rq *rq,</div><div class='ctx'> </div><div class='ctx'> 			skb_add_rx_frag(nskb, i, page, page_offset, size,</div><div class='ctx'> 					truesize);</div><div class='del'>-			if (skb_copy_bits(skb, off, page_address(page),</div><div class='add'>+			if (skb_copy_bits(skb, off,</div><div class='add'>+					  page_address(page) + page_offset,</div><div class='ctx'> 					  size)) {</div><div class='ctx'> 				consume_skb(nskb);</div><div class='ctx'> 				goto drop;</div><div class='hunk'>@@ -1722,6 +1723,24 @@ static int veth_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int veth_xdp_rx_vlan_tag(const struct xdp_md *ctx, __be16 *vlan_proto,</div><div class='add'>+				u16 *vlan_tci)</div><div class='add'>+{</div><div class='add'>+	const struct veth_xdp_buff *_ctx = (void *)ctx;</div><div class='add'>+	const struct sk_buff *skb = _ctx-&gt;skb;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (!skb)</div><div class='add'>+		return -ENODATA;</div><div class='add'>+</div><div class='add'>+	err = __vlan_hwaccel_get_tag(skb, vlan_tci);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	*vlan_proto = skb-&gt;vlan_proto;</div><div class='add'>+	return err;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct net_device_ops veth_netdev_ops = {</div><div class='ctx'> 	.ndo_init            = veth_dev_init,</div><div class='ctx'> 	.ndo_open            = veth_open,</div><div class='hunk'>@@ -1746,6 +1765,7 @@ static const struct net_device_ops veth_netdev_ops = {</div><div class='ctx'> static const struct xdp_metadata_ops veth_xdp_metadata_ops = {</div><div class='ctx'> 	.xmo_rx_timestamp		= veth_xdp_rx_timestamp,</div><div class='ctx'> 	.xmo_rx_hash			= veth_xdp_rx_hash,</div><div class='add'>+	.xmo_rx_vlan_tag		= veth_xdp_rx_vlan_tag,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> #define VETH_FEATURES (NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HW_CSUM | \</div><div class='head'>diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c<br/>index d16f592c2061..d7ce4a1011ea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/virtio_net.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/virtio_net.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/virtio_net.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/virtio_net.c</a></div><div class='hunk'>@@ -19,6 +19,7 @@</div><div class='ctx'> #include &lt;linux/average.h&gt;</div><div class='ctx'> #include &lt;linux/filter.h&gt;</div><div class='ctx'> #include &lt;linux/kernel.h&gt;</div><div class='add'>+#include &lt;linux/dim.h&gt;</div><div class='ctx'> #include &lt;net/route.h&gt;</div><div class='ctx'> #include &lt;net/xdp.h&gt;</div><div class='ctx'> #include &lt;net/net_failover.h&gt;</div><div class='hunk'>@@ -172,6 +173,17 @@ struct receive_queue {</div><div class='ctx'> </div><div class='ctx'> 	struct virtnet_rq_stats stats;</div><div class='ctx'> </div><div class='add'>+	/* The number of rx notifications */</div><div class='add'>+	u16 calls;</div><div class='add'>+</div><div class='add'>+	/* Is dynamic interrupt moderation enabled? */</div><div class='add'>+	bool dim_enabled;</div><div class='add'>+</div><div class='add'>+	/* Dynamic Interrupt Moderation */</div><div class='add'>+	struct dim dim;</div><div class='add'>+</div><div class='add'>+	u32 packets_in_napi;</div><div class='add'>+</div><div class='ctx'> 	struct virtnet_interrupt_coalesce intr_coal;</div><div class='ctx'> </div><div class='ctx'> 	/* Chain pages by the private ptr. */</div><div class='hunk'>@@ -305,6 +317,9 @@ struct virtnet_info {</div><div class='ctx'> 	u8 duplex;</div><div class='ctx'> 	u32 speed;</div><div class='ctx'> </div><div class='add'>+	/* Is rx dynamic interrupt moderation enabled? */</div><div class='add'>+	bool rx_dim_enabled;</div><div class='add'>+</div><div class='ctx'> 	/* Interrupt coalescing settings */</div><div class='ctx'> 	struct virtnet_interrupt_coalesce intr_coal_tx;</div><div class='ctx'> 	struct virtnet_interrupt_coalesce intr_coal_rx;</div><div class='hunk'>@@ -334,7 +349,6 @@ struct virtio_net_common_hdr {</div><div class='ctx'> 	};</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf);</div><div class='ctx'> static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf);</div><div class='ctx'> </div><div class='ctx'> static bool is_xdp_frame(void *ptr)</div><div class='hunk'>@@ -408,6 +422,17 @@ static struct page *get_a_page(struct receive_queue *rq, gfp_t gfp_mask)</div><div class='ctx'> 	return p;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void virtnet_rq_free_buf(struct virtnet_info *vi,</div><div class='add'>+				struct receive_queue *rq, void *buf)</div><div class='add'>+{</div><div class='add'>+	if (vi-&gt;mergeable_rx_bufs)</div><div class='add'>+		put_page(virt_to_head_page(buf));</div><div class='add'>+	else if (vi-&gt;big_packets)</div><div class='add'>+		give_pages(rq, buf);</div><div class='add'>+	else</div><div class='add'>+		put_page(virt_to_head_page(buf));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void enable_delayed_refill(struct virtnet_info *vi)</div><div class='ctx'> {</div><div class='ctx'> 	spin_lock_bh(&amp;vi-&gt;refill_lock);</div><div class='hunk'>@@ -431,7 +456,7 @@ static void virtqueue_napi_schedule(struct napi_struct *napi,</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void virtqueue_napi_complete(struct napi_struct *napi,</div><div class='add'>+static bool virtqueue_napi_complete(struct napi_struct *napi,</div><div class='ctx'> 				    struct virtqueue *vq, int processed)</div><div class='ctx'> {</div><div class='ctx'> 	int opaque;</div><div class='hunk'>@@ -440,9 +465,13 @@ static void virtqueue_napi_complete(struct napi_struct *napi,</div><div class='ctx'> 	if (napi_complete_done(napi, processed)) {</div><div class='ctx'> 		if (unlikely(virtqueue_poll(vq, opaque)))</div><div class='ctx'> 			virtqueue_napi_schedule(napi, vq);</div><div class='add'>+		else</div><div class='add'>+			return true;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		virtqueue_disable_cb(vq);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	return false;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void skb_xmit_done(struct virtqueue *vq)</div><div class='hunk'>@@ -634,17 +663,6 @@ static void *virtnet_rq_get_buf(struct receive_queue *rq, u32 *len, void **ctx)</div><div class='ctx'> 	return buf;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void *virtnet_rq_detach_unused_buf(struct receive_queue *rq)</div><div class='del'>-{</div><div class='del'>-	void *buf;</div><div class='del'>-</div><div class='del'>-	buf = virtqueue_detach_unused_buf(rq-&gt;vq);</div><div class='del'>-	if (buf &amp;&amp; rq-&gt;do_dma)</div><div class='del'>-		virtnet_rq_unmap(rq, buf, 0);</div><div class='del'>-</div><div class='del'>-	return buf;</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void virtnet_rq_init_one_sg(struct receive_queue *rq, void *buf, u32 len)</div><div class='ctx'> {</div><div class='ctx'> 	struct virtnet_rq_dma *dma;</div><div class='hunk'>@@ -744,6 +762,20 @@ static void virtnet_rq_set_premapped(struct virtnet_info *vi)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void virtnet_rq_unmap_free_buf(struct virtqueue *vq, void *buf)</div><div class='add'>+{</div><div class='add'>+	struct virtnet_info *vi = vq-&gt;vdev-&gt;priv;</div><div class='add'>+	struct receive_queue *rq;</div><div class='add'>+	int i = vq2rxq(vq);</div><div class='add'>+</div><div class='add'>+	rq = &amp;vi-&gt;rq[i];</div><div class='add'>+</div><div class='add'>+	if (rq-&gt;do_dma)</div><div class='add'>+		virtnet_rq_unmap(rq, buf, 0);</div><div class='add'>+</div><div class='add'>+	virtnet_rq_free_buf(vi, rq, buf);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void free_old_xmit_skbs(struct send_queue *sq, bool in_napi)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int len;</div><div class='hunk'>@@ -1764,7 +1796,7 @@ static void receive_buf(struct virtnet_info *vi, struct receive_queue *rq,</div><div class='ctx'> 	if (unlikely(len &lt; vi-&gt;hdr_len + ETH_HLEN)) {</div><div class='ctx'> 		pr_debug("%s: short packet %i\n", dev-&gt;name, len);</div><div class='ctx'> 		DEV_STATS_INC(dev, rx_length_errors);</div><div class='del'>-		virtnet_rq_free_unused_buf(rq-&gt;vq, buf);</div><div class='add'>+		virtnet_rq_free_buf(vi, rq, buf);</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -1997,6 +2029,7 @@ static void skb_recv_done(struct virtqueue *rvq)</div><div class='ctx'> 	struct virtnet_info *vi = rvq-&gt;vdev-&gt;priv;</div><div class='ctx'> 	struct receive_queue *rq = &amp;vi-&gt;rq[vq2rxq(rvq)];</div><div class='ctx'> </div><div class='add'>+	rq-&gt;calls++;</div><div class='ctx'> 	virtqueue_napi_schedule(&amp;rq-&gt;napi, rvq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2137,6 +2170,24 @@ static void virtnet_poll_cleantx(struct receive_queue *rq)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void virtnet_rx_dim_update(struct virtnet_info *vi, struct receive_queue *rq)</div><div class='add'>+{</div><div class='add'>+	struct dim_sample cur_sample = {};</div><div class='add'>+</div><div class='add'>+	if (!rq-&gt;packets_in_napi)</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	u64_stats_update_begin(&amp;rq-&gt;stats.syncp);</div><div class='add'>+	dim_update_sample(rq-&gt;calls,</div><div class='add'>+			  u64_stats_read(&amp;rq-&gt;stats.packets),</div><div class='add'>+			  u64_stats_read(&amp;rq-&gt;stats.bytes),</div><div class='add'>+			  &amp;cur_sample);</div><div class='add'>+	u64_stats_update_end(&amp;rq-&gt;stats.syncp);</div><div class='add'>+</div><div class='add'>+	net_dim(&amp;rq-&gt;dim, cur_sample);</div><div class='add'>+	rq-&gt;packets_in_napi = 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int virtnet_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> {</div><div class='ctx'> 	struct receive_queue *rq =</div><div class='hunk'>@@ -2145,17 +2196,22 @@ static int virtnet_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> 	struct send_queue *sq;</div><div class='ctx'> 	unsigned int received;</div><div class='ctx'> 	unsigned int xdp_xmit = 0;</div><div class='add'>+	bool napi_complete;</div><div class='ctx'> </div><div class='ctx'> 	virtnet_poll_cleantx(rq);</div><div class='ctx'> </div><div class='ctx'> 	received = virtnet_receive(rq, budget, &amp;xdp_xmit);</div><div class='add'>+	rq-&gt;packets_in_napi += received;</div><div class='ctx'> </div><div class='ctx'> 	if (xdp_xmit &amp; VIRTIO_XDP_REDIR)</div><div class='ctx'> 		xdp_do_flush();</div><div class='ctx'> </div><div class='ctx'> 	/* Out of packets? */</div><div class='del'>-	if (received &lt; budget)</div><div class='del'>-		virtqueue_napi_complete(napi, rq-&gt;vq, received);</div><div class='add'>+	if (received &lt; budget) {</div><div class='add'>+		napi_complete = virtqueue_napi_complete(napi, rq-&gt;vq, received);</div><div class='add'>+		if (napi_complete &amp;&amp; rq-&gt;dim_enabled)</div><div class='add'>+			virtnet_rx_dim_update(vi, rq);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	if (xdp_xmit &amp; VIRTIO_XDP_TX) {</div><div class='ctx'> 		sq = virtnet_xdp_get_sq(vi);</div><div class='hunk'>@@ -2226,8 +2282,11 @@ err_enable_qp:</div><div class='ctx'> 	disable_delayed_refill(vi);</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;vi-&gt;refill);</div><div class='ctx'> </div><div class='del'>-	for (i--; i &gt;= 0; i--)</div><div class='add'>+	for (i--; i &gt;= 0; i--) {</div><div class='ctx'> 		virtnet_disable_queue_pair(vi, i);</div><div class='add'>+		cancel_work_sync(&amp;vi-&gt;rq[i].dim.work);</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -2389,10 +2448,12 @@ static int virtnet_rx_resize(struct virtnet_info *vi,</div><div class='ctx'> </div><div class='ctx'> 	qindex = rq - vi-&gt;rq;</div><div class='ctx'> </div><div class='del'>-	if (running)</div><div class='add'>+	if (running) {</div><div class='ctx'> 		napi_disable(&amp;rq-&gt;napi);</div><div class='add'>+		cancel_work_sync(&amp;rq-&gt;dim.work);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='del'>-	err = virtqueue_resize(rq-&gt;vq, ring_num, virtnet_rq_free_unused_buf);</div><div class='add'>+	err = virtqueue_resize(rq-&gt;vq, ring_num, virtnet_rq_unmap_free_buf);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		netdev_err(vi-&gt;dev, "resize rx fail: rx queue index: %d err: %d\n", qindex, err);</div><div class='ctx'> </div><div class='hunk'>@@ -2637,8 +2698,10 @@ static int virtnet_close(struct net_device *dev)</div><div class='ctx'> 	/* Make sure refill_work doesn't re-enable napi! */</div><div class='ctx'> 	cancel_delayed_work_sync(&amp;vi-&gt;refill);</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++)</div><div class='add'>+	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++) {</div><div class='ctx'> 		virtnet_disable_queue_pair(vi, i);</div><div class='add'>+		cancel_work_sync(&amp;vi-&gt;rq[i].dim.work);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -2845,6 +2908,58 @@ static void virtnet_cpu_notif_remove(struct virtnet_info *vi)</div><div class='ctx'> 					    &amp;vi-&gt;node_dead);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int virtnet_send_ctrl_coal_vq_cmd(struct virtnet_info *vi,</div><div class='add'>+					 u16 vqn, u32 max_usecs, u32 max_packets)</div><div class='add'>+{</div><div class='add'>+	struct scatterlist sgs;</div><div class='add'>+</div><div class='add'>+	vi-&gt;ctrl-&gt;coal_vq.vqn = cpu_to_le16(vqn);</div><div class='add'>+	vi-&gt;ctrl-&gt;coal_vq.coal.max_usecs = cpu_to_le32(max_usecs);</div><div class='add'>+	vi-&gt;ctrl-&gt;coal_vq.coal.max_packets = cpu_to_le32(max_packets);</div><div class='add'>+	sg_init_one(&amp;sgs, &amp;vi-&gt;ctrl-&gt;coal_vq, sizeof(vi-&gt;ctrl-&gt;coal_vq));</div><div class='add'>+</div><div class='add'>+	if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_NOTF_COAL,</div><div class='add'>+				  VIRTIO_NET_CTRL_NOTF_COAL_VQ_SET,</div><div class='add'>+				  &amp;sgs))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int virtnet_send_rx_ctrl_coal_vq_cmd(struct virtnet_info *vi,</div><div class='add'>+					    u16 queue, u32 max_usecs,</div><div class='add'>+					    u32 max_packets)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = virtnet_send_ctrl_coal_vq_cmd(vi, rxq2vq(queue),</div><div class='add'>+					    max_usecs, max_packets);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	vi-&gt;rq[queue].intr_coal.max_usecs = max_usecs;</div><div class='add'>+	vi-&gt;rq[queue].intr_coal.max_packets = max_packets;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int virtnet_send_tx_ctrl_coal_vq_cmd(struct virtnet_info *vi,</div><div class='add'>+					    u16 queue, u32 max_usecs,</div><div class='add'>+					    u32 max_packets)</div><div class='add'>+{</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	err = virtnet_send_ctrl_coal_vq_cmd(vi, txq2vq(queue),</div><div class='add'>+					    max_usecs, max_packets);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	vi-&gt;sq[queue].intr_coal.max_usecs = max_usecs;</div><div class='add'>+	vi-&gt;sq[queue].intr_coal.max_packets = max_packets;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void virtnet_get_ringparam(struct net_device *dev,</div><div class='ctx'> 				  struct ethtool_ringparam *ring,</div><div class='ctx'> 				  struct kernel_ethtool_ringparam *kernel_ring,</div><div class='hunk'>@@ -2858,9 +2973,6 @@ static void virtnet_get_ringparam(struct net_device *dev,</div><div class='ctx'> 	ring-&gt;tx_pending = virtqueue_get_vring_size(vi-&gt;sq[0].vq);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int virtnet_send_ctrl_coal_vq_cmd(struct virtnet_info *vi,</div><div class='del'>-					 u16 vqn, u32 max_usecs, u32 max_packets);</div><div class='del'>-</div><div class='ctx'> static int virtnet_set_ringparam(struct net_device *dev,</div><div class='ctx'> 				 struct ethtool_ringparam *ring,</div><div class='ctx'> 				 struct kernel_ethtool_ringparam *kernel_ring,</div><div class='hunk'>@@ -2902,14 +3014,11 @@ static int virtnet_set_ringparam(struct net_device *dev,</div><div class='ctx'> 			 * through the VIRTIO_NET_CTRL_NOTF_COAL_TX_SET command, or, if the driver</div><div class='ctx'> 			 * did not set any TX coalescing parameters, to 0.</div><div class='ctx'> 			 */</div><div class='del'>-			err = virtnet_send_ctrl_coal_vq_cmd(vi, txq2vq(i),</div><div class='del'>-							    vi-&gt;intr_coal_tx.max_usecs,</div><div class='del'>-							    vi-&gt;intr_coal_tx.max_packets);</div><div class='add'>+			err = virtnet_send_tx_ctrl_coal_vq_cmd(vi, i,</div><div class='add'>+							       vi-&gt;intr_coal_tx.max_usecs,</div><div class='add'>+							       vi-&gt;intr_coal_tx.max_packets);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='del'>-</div><div class='del'>-			vi-&gt;sq[i].intr_coal.max_usecs = vi-&gt;intr_coal_tx.max_usecs;</div><div class='del'>-			vi-&gt;sq[i].intr_coal.max_packets = vi-&gt;intr_coal_tx.max_packets;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='ctx'> 		if (ring-&gt;rx_pending != rx_pending) {</div><div class='hunk'>@@ -2918,14 +3027,11 @@ static int virtnet_set_ringparam(struct net_device *dev,</div><div class='ctx'> 				return err;</div><div class='ctx'> </div><div class='ctx'> 			/* The reason is same as the transmit virtqueue reset */</div><div class='del'>-			err = virtnet_send_ctrl_coal_vq_cmd(vi, rxq2vq(i),</div><div class='del'>-							    vi-&gt;intr_coal_rx.max_usecs,</div><div class='del'>-							    vi-&gt;intr_coal_rx.max_packets);</div><div class='add'>+			err = virtnet_send_rx_ctrl_coal_vq_cmd(vi, i,</div><div class='add'>+							       vi-&gt;intr_coal_rx.max_usecs,</div><div class='add'>+							       vi-&gt;intr_coal_rx.max_packets);</div><div class='ctx'> 			if (err)</div><div class='ctx'> 				return err;</div><div class='del'>-</div><div class='del'>-			vi-&gt;rq[i].intr_coal.max_usecs = vi-&gt;intr_coal_rx.max_usecs;</div><div class='del'>-			vi-&gt;rq[i].intr_coal.max_packets = vi-&gt;intr_coal_rx.max_packets;</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -3262,10 +3368,10 @@ static int virtnet_get_link_ksettings(struct net_device *dev,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='del'>-				       struct ethtool_coalesce *ec)</div><div class='add'>+static int virtnet_send_tx_notf_coal_cmds(struct virtnet_info *vi,</div><div class='add'>+					  struct ethtool_coalesce *ec)</div><div class='ctx'> {</div><div class='del'>-	struct scatterlist sgs_tx, sgs_rx;</div><div class='add'>+	struct scatterlist sgs_tx;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='ctx'> 	vi-&gt;ctrl-&gt;coal_tx.tx_usecs = cpu_to_le32(ec-&gt;tx_coalesce_usecs);</div><div class='hunk'>@@ -3277,7 +3383,6 @@ static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='ctx'> 				  &amp;sgs_tx))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	/* Save parameters */</div><div class='ctx'> 	vi-&gt;intr_coal_tx.max_usecs = ec-&gt;tx_coalesce_usecs;</div><div class='ctx'> 	vi-&gt;intr_coal_tx.max_packets = ec-&gt;tx_max_coalesced_frames;</div><div class='ctx'> 	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++) {</div><div class='hunk'>@@ -3285,6 +3390,40 @@ static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='ctx'> 		vi-&gt;sq[i].intr_coal.max_packets = ec-&gt;tx_max_coalesced_frames;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int virtnet_send_rx_notf_coal_cmds(struct virtnet_info *vi,</div><div class='add'>+					  struct ethtool_coalesce *ec)</div><div class='add'>+{</div><div class='add'>+	bool rx_ctrl_dim_on = !!ec-&gt;use_adaptive_rx_coalesce;</div><div class='add'>+	struct scatterlist sgs_rx;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (rx_ctrl_dim_on &amp;&amp; !virtio_has_feature(vi-&gt;vdev, VIRTIO_NET_F_VQ_NOTF_COAL))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	if (rx_ctrl_dim_on &amp;&amp; (ec-&gt;rx_coalesce_usecs != vi-&gt;intr_coal_rx.max_usecs ||</div><div class='add'>+			       ec-&gt;rx_max_coalesced_frames != vi-&gt;intr_coal_rx.max_packets))</div><div class='add'>+		return -EINVAL;</div><div class='add'>+</div><div class='add'>+	if (rx_ctrl_dim_on &amp;&amp; !vi-&gt;rx_dim_enabled) {</div><div class='add'>+		vi-&gt;rx_dim_enabled = true;</div><div class='add'>+		for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++)</div><div class='add'>+			vi-&gt;rq[i].dim_enabled = true;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!rx_ctrl_dim_on &amp;&amp; vi-&gt;rx_dim_enabled) {</div><div class='add'>+		vi-&gt;rx_dim_enabled = false;</div><div class='add'>+		for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++)</div><div class='add'>+			vi-&gt;rq[i].dim_enabled = false;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Since the per-queue coalescing params can be set,</div><div class='add'>+	 * we need apply the global new params even if they</div><div class='add'>+	 * are not updated.</div><div class='add'>+	 */</div><div class='ctx'> 	vi-&gt;ctrl-&gt;coal_rx.rx_usecs = cpu_to_le32(ec-&gt;rx_coalesce_usecs);</div><div class='ctx'> 	vi-&gt;ctrl-&gt;coal_rx.rx_max_packets = cpu_to_le32(ec-&gt;rx_max_coalesced_frames);</div><div class='ctx'> 	sg_init_one(&amp;sgs_rx, &amp;vi-&gt;ctrl-&gt;coal_rx, sizeof(vi-&gt;ctrl-&gt;coal_rx));</div><div class='hunk'>@@ -3294,7 +3433,6 @@ static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='ctx'> 				  &amp;sgs_rx))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='del'>-	/* Save parameters */</div><div class='ctx'> 	vi-&gt;intr_coal_rx.max_usecs = ec-&gt;rx_coalesce_usecs;</div><div class='ctx'> 	vi-&gt;intr_coal_rx.max_packets = ec-&gt;rx_max_coalesced_frames;</div><div class='ctx'> 	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++) {</div><div class='hunk'>@@ -3305,21 +3443,55 @@ static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int virtnet_send_ctrl_coal_vq_cmd(struct virtnet_info *vi,</div><div class='del'>-					 u16 vqn, u32 max_usecs, u32 max_packets)</div><div class='add'>+static int virtnet_send_notf_coal_cmds(struct virtnet_info *vi,</div><div class='add'>+				       struct ethtool_coalesce *ec)</div><div class='ctx'> {</div><div class='del'>-	struct scatterlist sgs;</div><div class='add'>+	int err;</div><div class='ctx'> </div><div class='del'>-	vi-&gt;ctrl-&gt;coal_vq.vqn = cpu_to_le16(vqn);</div><div class='del'>-	vi-&gt;ctrl-&gt;coal_vq.coal.max_usecs = cpu_to_le32(max_usecs);</div><div class='del'>-	vi-&gt;ctrl-&gt;coal_vq.coal.max_packets = cpu_to_le32(max_packets);</div><div class='del'>-	sg_init_one(&amp;sgs, &amp;vi-&gt;ctrl-&gt;coal_vq, sizeof(vi-&gt;ctrl-&gt;coal_vq));</div><div class='add'>+	err = virtnet_send_tx_notf_coal_cmds(vi, ec);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='ctx'> </div><div class='del'>-	if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_NOTF_COAL,</div><div class='del'>-				  VIRTIO_NET_CTRL_NOTF_COAL_VQ_SET,</div><div class='del'>-				  &amp;sgs))</div><div class='add'>+	err = virtnet_send_rx_notf_coal_cmds(vi, ec);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int virtnet_send_rx_notf_coal_vq_cmds(struct virtnet_info *vi,</div><div class='add'>+					     struct ethtool_coalesce *ec,</div><div class='add'>+					     u16 queue)</div><div class='add'>+{</div><div class='add'>+	bool rx_ctrl_dim_on = !!ec-&gt;use_adaptive_rx_coalesce;</div><div class='add'>+	bool cur_rx_dim = vi-&gt;rq[queue].dim_enabled;</div><div class='add'>+	u32 max_usecs, max_packets;</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	max_usecs = vi-&gt;rq[queue].intr_coal.max_usecs;</div><div class='add'>+	max_packets = vi-&gt;rq[queue].intr_coal.max_packets;</div><div class='add'>+</div><div class='add'>+	if (rx_ctrl_dim_on &amp;&amp; (ec-&gt;rx_coalesce_usecs != max_usecs ||</div><div class='add'>+			       ec-&gt;rx_max_coalesced_frames != max_packets))</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> </div><div class='add'>+	if (rx_ctrl_dim_on &amp;&amp; !cur_rx_dim) {</div><div class='add'>+		vi-&gt;rq[queue].dim_enabled = true;</div><div class='add'>+		return 0;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!rx_ctrl_dim_on &amp;&amp; cur_rx_dim)</div><div class='add'>+		vi-&gt;rq[queue].dim_enabled = false;</div><div class='add'>+</div><div class='add'>+	/* If no params are updated, userspace ethtool will</div><div class='add'>+	 * reject the modification.</div><div class='add'>+	 */</div><div class='add'>+	err = virtnet_send_rx_ctrl_coal_vq_cmd(vi, queue,</div><div class='add'>+					       ec-&gt;rx_coalesce_usecs,</div><div class='add'>+					       ec-&gt;rx_max_coalesced_frames);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -3329,27 +3501,62 @@ static int virtnet_send_notf_coal_vq_cmds(struct virtnet_info *vi,</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='ctx'> </div><div class='del'>-	err = virtnet_send_ctrl_coal_vq_cmd(vi, rxq2vq(queue),</div><div class='del'>-					    ec-&gt;rx_coalesce_usecs,</div><div class='del'>-					    ec-&gt;rx_max_coalesced_frames);</div><div class='add'>+	err = virtnet_send_rx_notf_coal_vq_cmds(vi, ec, queue);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	vi-&gt;rq[queue].intr_coal.max_usecs = ec-&gt;rx_coalesce_usecs;</div><div class='del'>-	vi-&gt;rq[queue].intr_coal.max_packets = ec-&gt;rx_max_coalesced_frames;</div><div class='del'>-</div><div class='del'>-	err = virtnet_send_ctrl_coal_vq_cmd(vi, txq2vq(queue),</div><div class='del'>-					    ec-&gt;tx_coalesce_usecs,</div><div class='del'>-					    ec-&gt;tx_max_coalesced_frames);</div><div class='add'>+	err = virtnet_send_tx_ctrl_coal_vq_cmd(vi, queue,</div><div class='add'>+					       ec-&gt;tx_coalesce_usecs,</div><div class='add'>+					       ec-&gt;tx_max_coalesced_frames);</div><div class='ctx'> 	if (err)</div><div class='ctx'> 		return err;</div><div class='ctx'> </div><div class='del'>-	vi-&gt;sq[queue].intr_coal.max_usecs = ec-&gt;tx_coalesce_usecs;</div><div class='del'>-	vi-&gt;sq[queue].intr_coal.max_packets = ec-&gt;tx_max_coalesced_frames;</div><div class='del'>-</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static void virtnet_rx_dim_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct dim *dim = container_of(work, struct dim, work);</div><div class='add'>+	struct receive_queue *rq = container_of(dim,</div><div class='add'>+			struct receive_queue, dim);</div><div class='add'>+	struct virtnet_info *vi = rq-&gt;vq-&gt;vdev-&gt;priv;</div><div class='add'>+	struct net_device *dev = vi-&gt;dev;</div><div class='add'>+	struct dim_cq_moder update_moder;</div><div class='add'>+	int i, qnum, err;</div><div class='add'>+</div><div class='add'>+	if (!rtnl_trylock())</div><div class='add'>+		return;</div><div class='add'>+</div><div class='add'>+	/* Each rxq's work is queued by "net_dim()-&gt;schedule_work()"</div><div class='add'>+	 * in response to NAPI traffic changes. Note that dim-&gt;profile_ix</div><div class='add'>+	 * for each rxq is updated prior to the queuing action.</div><div class='add'>+	 * So we only need to traverse and update profiles for all rxqs</div><div class='add'>+	 * in the work which is holding rtnl_lock.</div><div class='add'>+	 */</div><div class='add'>+	for (i = 0; i &lt; vi-&gt;curr_queue_pairs; i++) {</div><div class='add'>+		rq = &amp;vi-&gt;rq[i];</div><div class='add'>+		dim = &amp;rq-&gt;dim;</div><div class='add'>+		qnum = rq - vi-&gt;rq;</div><div class='add'>+</div><div class='add'>+		if (!rq-&gt;dim_enabled)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		update_moder = net_dim_get_rx_moderation(dim-&gt;mode, dim-&gt;profile_ix);</div><div class='add'>+		if (update_moder.usec != rq-&gt;intr_coal.max_usecs ||</div><div class='add'>+		    update_moder.pkts != rq-&gt;intr_coal.max_packets) {</div><div class='add'>+			err = virtnet_send_rx_ctrl_coal_vq_cmd(vi, qnum,</div><div class='add'>+							       update_moder.usec,</div><div class='add'>+							       update_moder.pkts);</div><div class='add'>+			if (err)</div><div class='add'>+				pr_debug("%s: Failed to send dim parameters on rxq%d\n",</div><div class='add'>+					 dev-&gt;name, qnum);</div><div class='add'>+			dim-&gt;state = DIM_START_MEASURE;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	rtnl_unlock();</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int virtnet_coal_params_supported(struct ethtool_coalesce *ec)</div><div class='ctx'> {</div><div class='ctx'> 	/* usecs coalescing is supported only if VIRTIO_NET_F_NOTF_COAL</div><div class='hunk'>@@ -3431,6 +3638,7 @@ static int virtnet_get_coalesce(struct net_device *dev,</div><div class='ctx'> 		ec-&gt;tx_coalesce_usecs = vi-&gt;intr_coal_tx.max_usecs;</div><div class='ctx'> 		ec-&gt;tx_max_coalesced_frames = vi-&gt;intr_coal_tx.max_packets;</div><div class='ctx'> 		ec-&gt;rx_max_coalesced_frames = vi-&gt;intr_coal_rx.max_packets;</div><div class='add'>+		ec-&gt;use_adaptive_rx_coalesce = vi-&gt;rx_dim_enabled;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ec-&gt;rx_max_coalesced_frames = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -3488,6 +3696,7 @@ static int virtnet_get_per_queue_coalesce(struct net_device *dev,</div><div class='ctx'> 		ec-&gt;tx_coalesce_usecs = vi-&gt;sq[queue].intr_coal.max_usecs;</div><div class='ctx'> 		ec-&gt;tx_max_coalesced_frames = vi-&gt;sq[queue].intr_coal.max_packets;</div><div class='ctx'> 		ec-&gt;rx_max_coalesced_frames = vi-&gt;rq[queue].intr_coal.max_packets;</div><div class='add'>+		ec-&gt;use_adaptive_rx_coalesce = vi-&gt;rq[queue].dim_enabled;</div><div class='ctx'> 	} else {</div><div class='ctx'> 		ec-&gt;rx_max_coalesced_frames = 1;</div><div class='ctx'> </div><div class='hunk'>@@ -3535,39 +3744,42 @@ static u32 virtnet_get_rxfh_indir_size(struct net_device *dev)</div><div class='ctx'> 	return ((struct virtnet_info *)netdev_priv(dev))-&gt;rss_indir_table_size;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int virtnet_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)</div><div class='add'>+static int virtnet_get_rxfh(struct net_device *dev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct virtnet_info *vi = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; vi-&gt;rss_indir_table_size; ++i)</div><div class='del'>-			indir[i] = vi-&gt;ctrl-&gt;rss.indirection_table[i];</div><div class='add'>+			rxfh-&gt;indir[i] = vi-&gt;ctrl-&gt;rss.indirection_table[i];</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(key, vi-&gt;ctrl-&gt;rss.key, vi-&gt;rss_key_size);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(rxfh-&gt;key, vi-&gt;ctrl-&gt;rss.key, vi-&gt;rss_key_size);</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int virtnet_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, const u8 hfunc)</div><div class='add'>+static int virtnet_set_rxfh(struct net_device *dev,</div><div class='add'>+			    struct ethtool_rxfh_param *rxfh,</div><div class='add'>+			    struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	struct virtnet_info *vi = netdev_priv(dev);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	if (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP)</div><div class='add'>+	if (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	    rxfh-&gt;hfunc != ETH_RSS_HASH_TOP)</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='ctx'> </div><div class='del'>-	if (indir) {</div><div class='add'>+	if (rxfh-&gt;indir) {</div><div class='ctx'> 		for (i = 0; i &lt; vi-&gt;rss_indir_table_size; ++i)</div><div class='del'>-			vi-&gt;ctrl-&gt;rss.indirection_table[i] = indir[i];</div><div class='add'>+			vi-&gt;ctrl-&gt;rss.indirection_table[i] = rxfh-&gt;indir[i];</div><div class='ctx'> 	}</div><div class='del'>-	if (key)</div><div class='del'>-		memcpy(vi-&gt;ctrl-&gt;rss.key, key, vi-&gt;rss_key_size);</div><div class='add'>+	if (rxfh-&gt;key)</div><div class='add'>+		memcpy(vi-&gt;ctrl-&gt;rss.key, rxfh-&gt;key, vi-&gt;rss_key_size);</div><div class='ctx'> </div><div class='ctx'> 	virtnet_commit_rss_command(vi);</div><div class='ctx'> </div><div class='hunk'>@@ -3613,7 +3825,7 @@ static int virtnet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)</div><div class='ctx'> </div><div class='ctx'> static const struct ethtool_ops virtnet_ethtool_ops = {</div><div class='ctx'> 	.supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES |</div><div class='del'>-		ETHTOOL_COALESCE_USECS,</div><div class='add'>+		ETHTOOL_COALESCE_USECS | ETHTOOL_COALESCE_USE_ADAPTIVE_RX,</div><div class='ctx'> 	.get_drvinfo = virtnet_get_drvinfo,</div><div class='ctx'> 	.get_link = ethtool_op_get_link,</div><div class='ctx'> 	.get_ringparam = virtnet_get_ringparam,</div><div class='hunk'>@@ -4031,19 +4243,6 @@ static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf)</div><div class='ctx'> 		xdp_return_frame(ptr_to_xdp(buf));</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf)</div><div class='del'>-{</div><div class='del'>-	struct virtnet_info *vi = vq-&gt;vdev-&gt;priv;</div><div class='del'>-	int i = vq2rxq(vq);</div><div class='del'>-</div><div class='del'>-	if (vi-&gt;mergeable_rx_bufs)</div><div class='del'>-		put_page(virt_to_head_page(buf));</div><div class='del'>-	else if (vi-&gt;big_packets)</div><div class='del'>-		give_pages(&amp;vi-&gt;rq[i], buf);</div><div class='del'>-	else</div><div class='del'>-		put_page(virt_to_head_page(buf));</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> static void free_unused_bufs(struct virtnet_info *vi)</div><div class='ctx'> {</div><div class='ctx'> 	void *buf;</div><div class='hunk'>@@ -4057,10 +4256,10 @@ static void free_unused_bufs(struct virtnet_info *vi)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++) {</div><div class='del'>-		struct receive_queue *rq = &amp;vi-&gt;rq[i];</div><div class='add'>+		struct virtqueue *vq = vi-&gt;rq[i].vq;</div><div class='ctx'> </div><div class='del'>-		while ((buf = virtnet_rq_detach_unused_buf(rq)) != NULL)</div><div class='del'>-			virtnet_rq_free_unused_buf(rq-&gt;vq, buf);</div><div class='add'>+		while ((buf = virtqueue_detach_unused_buf(vq)) != NULL)</div><div class='add'>+			virtnet_rq_unmap_free_buf(vq, buf);</div><div class='ctx'> 		cond_resched();</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='hunk'>@@ -4096,10 +4295,11 @@ static int virtnet_find_vqs(struct virtnet_info *vi)</div><div class='ctx'> {</div><div class='ctx'> 	vq_callback_t **callbacks;</div><div class='ctx'> 	struct virtqueue **vqs;</div><div class='del'>-	int ret = -ENOMEM;</div><div class='del'>-	int i, total_vqs;</div><div class='ctx'> 	const char **names;</div><div class='add'>+	int ret = -ENOMEM;</div><div class='add'>+	int total_vqs;</div><div class='ctx'> 	bool *ctx;</div><div class='add'>+	u16 i;</div><div class='ctx'> </div><div class='ctx'> 	/* We expect 1 RX virtqueue followed by 1 TX virtqueue, followed by</div><div class='ctx'> 	 * possible N-1 RX/TX queue pairs used in multiqueue mode, followed by</div><div class='hunk'>@@ -4136,8 +4336,8 @@ static int virtnet_find_vqs(struct virtnet_info *vi)</div><div class='ctx'> 	for (i = 0; i &lt; vi-&gt;max_queue_pairs; i++) {</div><div class='ctx'> 		callbacks[rxq2vq(i)] = skb_recv_done;</div><div class='ctx'> 		callbacks[txq2vq(i)] = skb_xmit_done;</div><div class='del'>-		sprintf(vi-&gt;rq[i].name, "input.%d", i);</div><div class='del'>-		sprintf(vi-&gt;sq[i].name, "output.%d", i);</div><div class='add'>+		sprintf(vi-&gt;rq[i].name, "input.%u", i);</div><div class='add'>+		sprintf(vi-&gt;sq[i].name, "output.%u", i);</div><div class='ctx'> 		names[rxq2vq(i)] = vi-&gt;rq[i].name;</div><div class='ctx'> 		names[txq2vq(i)] = vi-&gt;sq[i].name;</div><div class='ctx'> 		if (ctx)</div><div class='hunk'>@@ -4203,6 +4403,9 @@ static int virtnet_alloc_queues(struct virtnet_info *vi)</div><div class='ctx'> 					 virtnet_poll_tx,</div><div class='ctx'> 					 napi_tx ? napi_weight : 0);</div><div class='ctx'> </div><div class='add'>+		INIT_WORK(&amp;vi-&gt;rq[i].dim.work, virtnet_rx_dim_work);</div><div class='add'>+		vi-&gt;rq[i].dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;</div><div class='add'>+</div><div class='ctx'> 		sg_init_table(vi-&gt;rq[i].sg, ARRAY_SIZE(vi-&gt;rq[i].sg));</div><div class='ctx'> 		ewma_pkt_len_init(&amp;vi-&gt;rq[i].mrg_avg_pkt_len);</div><div class='ctx'> 		sg_init_table(vi-&gt;sq[i].sg, ARRAY_SIZE(vi-&gt;sq[i].sg));</div><div class='head'>diff --git a/drivers/net/vmxnet3/vmxnet3_ethtool.c b/drivers/net/vmxnet3/vmxnet3_ethtool.c<br/>index 98c22d7d87a2..7e8008d5378a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/vmxnet3/vmxnet3_ethtool.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/vmxnet3/vmxnet3_ethtool.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/vmxnet3/vmxnet3_ethtool.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vmxnet3/vmxnet3_ethtool.c</a></div><div class='hunk'>@@ -245,20 +245,20 @@ vmxnet3_get_strings(struct net_device *netdev, u32 stringset, u8 *buf)</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adapter-&gt;num_tx_queues; j++) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(vmxnet3_tq_dev_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;buf, vmxnet3_tq_dev_stats[i].desc);</div><div class='add'>+			ethtool_puts(&amp;buf, vmxnet3_tq_dev_stats[i].desc);</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(vmxnet3_tq_driver_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;buf, vmxnet3_tq_driver_stats[i].desc);</div><div class='add'>+			ethtool_puts(&amp;buf, vmxnet3_tq_driver_stats[i].desc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (j = 0; j &lt; adapter-&gt;num_rx_queues; j++) {</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(vmxnet3_rq_dev_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;buf, vmxnet3_rq_dev_stats[i].desc);</div><div class='add'>+			ethtool_puts(&amp;buf, vmxnet3_rq_dev_stats[i].desc);</div><div class='ctx'> 		for (i = 0; i &lt; ARRAY_SIZE(vmxnet3_rq_driver_stats); i++)</div><div class='del'>-			ethtool_sprintf(&amp;buf, vmxnet3_rq_driver_stats[i].desc);</div><div class='add'>+			ethtool_puts(&amp;buf, vmxnet3_rq_driver_stats[i].desc);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	for (i = 0; i &lt; ARRAY_SIZE(vmxnet3_global_stats); i++)</div><div class='del'>-		ethtool_sprintf(&amp;buf, vmxnet3_global_stats[i].desc);</div><div class='add'>+		ethtool_puts(&amp;buf, vmxnet3_global_stats[i].desc);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> netdev_features_t vmxnet3_fix_features(struct net_device *netdev,</div><div class='hunk'>@@ -1136,27 +1136,26 @@ vmxnet3_get_rss_indir_size(struct net_device *netdev)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-vmxnet3_get_rss(struct net_device *netdev, u32 *p, u8 *key, u8 *hfunc)</div><div class='add'>+vmxnet3_get_rss(struct net_device *netdev, struct ethtool_rxfh_param *rxfh)</div><div class='ctx'> {</div><div class='ctx'> 	struct vmxnet3_adapter *adapter = netdev_priv(netdev);</div><div class='ctx'> 	struct UPT1_RSSConf *rssConf = adapter-&gt;rss_conf;</div><div class='ctx'> 	unsigned int n = rssConf-&gt;indTableSize;</div><div class='ctx'> </div><div class='del'>-	if (hfunc)</div><div class='del'>-		*hfunc = ETH_RSS_HASH_TOP;</div><div class='del'>-	if (!p)</div><div class='add'>+	rxfh-&gt;hfunc = ETH_RSS_HASH_TOP;</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	if (n &gt; UPT1_RSS_MAX_IND_TABLE_SIZE)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	while (n--)</div><div class='del'>-		p[n] = rssConf-&gt;indTable[n];</div><div class='add'>+		rxfh-&gt;indir[n] = rssConf-&gt;indTable[n];</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int</div><div class='del'>-vmxnet3_set_rss(struct net_device *netdev, const u32 *p, const u8 *key,</div><div class='del'>-		const u8 hfunc)</div><div class='add'>+vmxnet3_set_rss(struct net_device *netdev, struct ethtool_rxfh_param *rxfh,</div><div class='add'>+		struct netlink_ext_ack *extack)</div><div class='ctx'> {</div><div class='ctx'> 	unsigned int i;</div><div class='ctx'> 	unsigned long flags;</div><div class='hunk'>@@ -1164,13 +1163,14 @@ vmxnet3_set_rss(struct net_device *netdev, const u32 *p, const u8 *key,</div><div class='ctx'> 	struct UPT1_RSSConf *rssConf = adapter-&gt;rss_conf;</div><div class='ctx'> </div><div class='ctx'> 	/* We do not allow change in unsupported parameters */</div><div class='del'>-	if (key ||</div><div class='del'>-	    (hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp; hfunc != ETH_RSS_HASH_TOP))</div><div class='add'>+	if (rxfh-&gt;key ||</div><div class='add'>+	    (rxfh-&gt;hfunc != ETH_RSS_HASH_NO_CHANGE &amp;&amp;</div><div class='add'>+	     rxfh-&gt;hfunc != ETH_RSS_HASH_TOP))</div><div class='ctx'> 		return -EOPNOTSUPP;</div><div class='del'>-	if (!p)</div><div class='add'>+	if (!rxfh-&gt;indir)</div><div class='ctx'> 		return 0;</div><div class='ctx'> 	for (i = 0; i &lt; rssConf-&gt;indTableSize; i++)</div><div class='del'>-		rssConf-&gt;indTable[i] = p[i];</div><div class='add'>+		rssConf-&gt;indTable[i] = rxfh-&gt;indir[i];</div><div class='ctx'> </div><div class='ctx'> 	spin_lock_irqsave(&amp;adapter-&gt;cmd_lock, flags);</div><div class='ctx'> 	VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,</div><div class='head'>diff --git a/drivers/net/vxlan/vxlan_core.c b/drivers/net/vxlan/vxlan_core.c<br/>index 412c3c0b6990..16106e088c63 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/vxlan/vxlan_core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_core.c</a></div><div class='hunk'>@@ -2379,7 +2379,17 @@ void vxlan_xmit_one(struct sk_buff *skb, struct net_device *dev,</div><div class='ctx'> 		else</div><div class='ctx'> 			udp_sum = !(flags &amp; VXLAN_F_UDP_ZERO_CSUM6_TX);</div><div class='ctx'> #if IS_ENABLED(CONFIG_IPV6)</div><div class='del'>-		key.label = vxlan-&gt;cfg.label;</div><div class='add'>+		switch (vxlan-&gt;cfg.label_policy) {</div><div class='add'>+		case VXLAN_LABEL_FIXED:</div><div class='add'>+			key.label = vxlan-&gt;cfg.label;</div><div class='add'>+			break;</div><div class='add'>+		case VXLAN_LABEL_INHERIT:</div><div class='add'>+			key.label = ip_tunnel_get_flowlabel(old_iph, skb);</div><div class='add'>+			break;</div><div class='add'>+		default:</div><div class='add'>+			DEBUG_NET_WARN_ON_ONCE(1);</div><div class='add'>+			goto drop;</div><div class='add'>+		}</div><div class='ctx'> #endif</div><div class='ctx'> 	} else {</div><div class='ctx'> 		if (!info) {</div><div class='hunk'>@@ -3225,6 +3235,7 @@ static const struct net_device_ops vxlan_netdev_ether_ops = {</div><div class='ctx'> 	.ndo_fdb_get		= vxlan_fdb_get,</div><div class='ctx'> 	.ndo_mdb_add		= vxlan_mdb_add,</div><div class='ctx'> 	.ndo_mdb_del		= vxlan_mdb_del,</div><div class='add'>+	.ndo_mdb_del_bulk	= vxlan_mdb_del_bulk,</div><div class='ctx'> 	.ndo_mdb_dump		= vxlan_mdb_dump,</div><div class='ctx'> 	.ndo_mdb_get		= vxlan_mdb_get,</div><div class='ctx'> 	.ndo_fill_metadata_dst	= vxlan_fill_metadata_dst,</div><div class='hunk'>@@ -3366,6 +3377,7 @@ static const struct nla_policy vxlan_policy[IFLA_VXLAN_MAX + 1] = {</div><div class='ctx'> 	[IFLA_VXLAN_DF]		= { .type = NLA_U8 },</div><div class='ctx'> 	[IFLA_VXLAN_VNIFILTER]	= { .type = NLA_U8 },</div><div class='ctx'> 	[IFLA_VXLAN_LOCALBYPASS]	= NLA_POLICY_MAX(NLA_U8, 1),</div><div class='add'>+	[IFLA_VXLAN_LABEL_POLICY]       = NLA_POLICY_MAX(NLA_U32, VXLAN_LABEL_MAX),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> static int vxlan_validate(struct nlattr *tb[], struct nlattr *data[],</div><div class='hunk'>@@ -3740,6 +3752,12 @@ static int vxlan_config_validate(struct net *src_net, struct vxlan_config *conf,</div><div class='ctx'> 		return -EINVAL;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (conf-&gt;label_policy &amp;&amp; !use_ipv6) {</div><div class='add'>+		NL_SET_ERR_MSG(extack,</div><div class='add'>+			       "Label policy only applies to IPv6 VXLAN devices");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	if (conf-&gt;remote_ifindex) {</div><div class='ctx'> 		struct net_device *lowerdev;</div><div class='ctx'> </div><div class='hunk'>@@ -4082,6 +4100,8 @@ static int vxlan_nl2conf(struct nlattr *tb[], struct nlattr *data[],</div><div class='ctx'> 	if (data[IFLA_VXLAN_LABEL])</div><div class='ctx'> 		conf-&gt;label = nla_get_be32(data[IFLA_VXLAN_LABEL]) &amp;</div><div class='ctx'> 			     IPV6_FLOWLABEL_MASK;</div><div class='add'>+	if (data[IFLA_VXLAN_LABEL_POLICY])</div><div class='add'>+		conf-&gt;label_policy = nla_get_u32(data[IFLA_VXLAN_LABEL_POLICY]);</div><div class='ctx'> </div><div class='ctx'> 	if (data[IFLA_VXLAN_LEARNING]) {</div><div class='ctx'> 		err = vxlan_nl2flag(conf, data, IFLA_VXLAN_LEARNING,</div><div class='hunk'>@@ -4398,6 +4418,7 @@ static size_t vxlan_get_size(const struct net_device *dev)</div><div class='ctx'> 		nla_total_size(sizeof(__u8)) +	/* IFLA_VXLAN_TOS */</div><div class='ctx'> 		nla_total_size(sizeof(__u8)) +	/* IFLA_VXLAN_DF */</div><div class='ctx'> 		nla_total_size(sizeof(__be32)) + /* IFLA_VXLAN_LABEL */</div><div class='add'>+		nla_total_size(sizeof(__u32)) +  /* IFLA_VXLAN_LABEL_POLICY */</div><div class='ctx'> 		nla_total_size(sizeof(__u8)) +	/* IFLA_VXLAN_LEARNING */</div><div class='ctx'> 		nla_total_size(sizeof(__u8)) +	/* IFLA_VXLAN_PROXY */</div><div class='ctx'> 		nla_total_size(sizeof(__u8)) +	/* IFLA_VXLAN_RSC */</div><div class='hunk'>@@ -4471,6 +4492,7 @@ static int vxlan_fill_info(struct sk_buff *skb, const struct net_device *dev)</div><div class='ctx'> 	    nla_put_u8(skb, IFLA_VXLAN_TOS, vxlan-&gt;cfg.tos) ||</div><div class='ctx'> 	    nla_put_u8(skb, IFLA_VXLAN_DF, vxlan-&gt;cfg.df) ||</div><div class='ctx'> 	    nla_put_be32(skb, IFLA_VXLAN_LABEL, vxlan-&gt;cfg.label) ||</div><div class='add'>+	    nla_put_u32(skb, IFLA_VXLAN_LABEL_POLICY, vxlan-&gt;cfg.label_policy) ||</div><div class='ctx'> 	    nla_put_u8(skb, IFLA_VXLAN_LEARNING,</div><div class='ctx'> 		       !!(vxlan-&gt;cfg.flags &amp; VXLAN_F_LEARN)) ||</div><div class='ctx'> 	    nla_put_u8(skb, IFLA_VXLAN_PROXY,</div><div class='head'>diff --git a/drivers/net/vxlan/vxlan_mdb.c b/drivers/net/vxlan/vxlan_mdb.c<br/>index eb4c580b5cee..60eb95a06d55 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_mdb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/vxlan/vxlan_mdb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_mdb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_mdb.c</a></div><div class='hunk'>@@ -74,6 +74,14 @@ struct vxlan_mdb_config {</div><div class='ctx'> 	u8 rt_protocol;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct vxlan_mdb_flush_desc {</div><div class='add'>+	union vxlan_addr remote_ip;</div><div class='add'>+	__be32 src_vni;</div><div class='add'>+	__be32 remote_vni;</div><div class='add'>+	__be16 remote_port;</div><div class='add'>+	u8 rt_protocol;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const struct rhashtable_params vxlan_mdb_rht_params = {</div><div class='ctx'> 	.head_offset = offsetof(struct vxlan_mdb_entry, rhnode),</div><div class='ctx'> 	.key_offset = offsetof(struct vxlan_mdb_entry, key),</div><div class='hunk'>@@ -1306,6 +1314,145 @@ int vxlan_mdb_del(struct net_device *dev, struct nlattr *tb[],</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static const struct nla_policy</div><div class='add'>+vxlan_mdbe_attrs_del_bulk_pol[MDBE_ATTR_MAX + 1] = {</div><div class='add'>+	[MDBE_ATTR_RTPROT] = NLA_POLICY_MIN(NLA_U8, RTPROT_STATIC),</div><div class='add'>+	[MDBE_ATTR_DST] = NLA_POLICY_RANGE(NLA_BINARY,</div><div class='add'>+					   sizeof(struct in_addr),</div><div class='add'>+					   sizeof(struct in6_addr)),</div><div class='add'>+	[MDBE_ATTR_DST_PORT] = { .type = NLA_U16 },</div><div class='add'>+	[MDBE_ATTR_VNI] = NLA_POLICY_FULL_RANGE(NLA_U32, &amp;vni_range),</div><div class='add'>+	[MDBE_ATTR_SRC_VNI] = NLA_POLICY_FULL_RANGE(NLA_U32, &amp;vni_range),</div><div class='add'>+	[MDBE_ATTR_STATE_MASK] = NLA_POLICY_MASK(NLA_U8, MDB_PERMANENT),</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int vxlan_mdb_flush_desc_init(struct vxlan_dev *vxlan,</div><div class='add'>+				     struct vxlan_mdb_flush_desc *desc,</div><div class='add'>+				     struct nlattr *tb[],</div><div class='add'>+				     struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct br_mdb_entry *entry = nla_data(tb[MDBA_SET_ENTRY]);</div><div class='add'>+	struct nlattr *mdbe_attrs[MDBE_ATTR_MAX + 1];</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;ifindex &amp;&amp; entry-&gt;ifindex != vxlan-&gt;dev-&gt;ifindex) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "Invalid port net device");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (entry-&gt;vid) {</div><div class='add'>+		NL_SET_ERR_MSG_MOD(extack, "VID must not be specified");</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!tb[MDBA_SET_ENTRY_ATTRS])</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	err = nla_parse_nested(mdbe_attrs, MDBE_ATTR_MAX,</div><div class='add'>+			       tb[MDBA_SET_ENTRY_ATTRS],</div><div class='add'>+			       vxlan_mdbe_attrs_del_bulk_pol, extack);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_STATE_MASK]) {</div><div class='add'>+		u8 state_mask = nla_get_u8(mdbe_attrs[MDBE_ATTR_STATE_MASK]);</div><div class='add'>+</div><div class='add'>+		if ((state_mask &amp; MDB_PERMANENT) &amp;&amp; !(entry-&gt;state &amp; MDB_PERMANENT)) {</div><div class='add'>+			NL_SET_ERR_MSG_MOD(extack, "Only permanent MDB entries are supported");</div><div class='add'>+			return -EINVAL;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_RTPROT])</div><div class='add'>+		desc-&gt;rt_protocol = nla_get_u8(mdbe_attrs[MDBE_ATTR_RTPROT]);</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_DST])</div><div class='add'>+		vxlan_nla_get_addr(&amp;desc-&gt;remote_ip, mdbe_attrs[MDBE_ATTR_DST]);</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_DST_PORT])</div><div class='add'>+		desc-&gt;remote_port =</div><div class='add'>+			cpu_to_be16(nla_get_u16(mdbe_attrs[MDBE_ATTR_DST_PORT]));</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_VNI])</div><div class='add'>+		desc-&gt;remote_vni =</div><div class='add'>+			cpu_to_be32(nla_get_u32(mdbe_attrs[MDBE_ATTR_VNI]));</div><div class='add'>+</div><div class='add'>+	if (mdbe_attrs[MDBE_ATTR_SRC_VNI])</div><div class='add'>+		desc-&gt;src_vni =</div><div class='add'>+			cpu_to_be32(nla_get_u32(mdbe_attrs[MDBE_ATTR_SRC_VNI]));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vxlan_mdb_remotes_flush(struct vxlan_dev *vxlan,</div><div class='add'>+				    struct vxlan_mdb_entry *mdb_entry,</div><div class='add'>+				    const struct vxlan_mdb_flush_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct vxlan_mdb_remote *remote, *tmp;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry_safe(remote, tmp, &amp;mdb_entry-&gt;remotes, list) {</div><div class='add'>+		struct vxlan_rdst *rd = rtnl_dereference(remote-&gt;rd);</div><div class='add'>+		__be32 remote_vni;</div><div class='add'>+</div><div class='add'>+		if (desc-&gt;remote_ip.sa.sa_family &amp;&amp;</div><div class='add'>+		    !vxlan_addr_equal(&amp;desc-&gt;remote_ip, &amp;rd-&gt;remote_ip))</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		/* Encapsulation is performed with source VNI if remote VNI</div><div class='add'>+		 * is not set.</div><div class='add'>+		 */</div><div class='add'>+		remote_vni = rd-&gt;remote_vni ? : mdb_entry-&gt;key.vni;</div><div class='add'>+		if (desc-&gt;remote_vni &amp;&amp; desc-&gt;remote_vni != remote_vni)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (desc-&gt;remote_port &amp;&amp; desc-&gt;remote_port != rd-&gt;remote_port)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		if (desc-&gt;rt_protocol &amp;&amp;</div><div class='add'>+		    desc-&gt;rt_protocol != remote-&gt;rt_protocol)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vxlan_mdb_remote_del(vxlan, mdb_entry, remote);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void vxlan_mdb_flush(struct vxlan_dev *vxlan,</div><div class='add'>+			    const struct vxlan_mdb_flush_desc *desc)</div><div class='add'>+{</div><div class='add'>+	struct vxlan_mdb_entry *mdb_entry;</div><div class='add'>+	struct hlist_node *tmp;</div><div class='add'>+</div><div class='add'>+	/* The removal of an entry cannot trigger the removal of another entry</div><div class='add'>+	 * since entries are always added to the head of the list.</div><div class='add'>+	 */</div><div class='add'>+	hlist_for_each_entry_safe(mdb_entry, tmp, &amp;vxlan-&gt;mdb_list, mdb_node) {</div><div class='add'>+		if (desc-&gt;src_vni &amp;&amp; desc-&gt;src_vni != mdb_entry-&gt;key.vni)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		vxlan_mdb_remotes_flush(vxlan, mdb_entry, desc);</div><div class='add'>+		/* Entry will only be removed if its remotes list is empty. */</div><div class='add'>+		vxlan_mdb_entry_put(vxlan, mdb_entry);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+int vxlan_mdb_del_bulk(struct net_device *dev, struct nlattr *tb[],</div><div class='add'>+		       struct netlink_ext_ack *extack)</div><div class='add'>+{</div><div class='add'>+	struct vxlan_dev *vxlan = netdev_priv(dev);</div><div class='add'>+	struct vxlan_mdb_flush_desc desc = {};</div><div class='add'>+	int err;</div><div class='add'>+</div><div class='add'>+	ASSERT_RTNL();</div><div class='add'>+</div><div class='add'>+	err = vxlan_mdb_flush_desc_init(vxlan, &amp;desc, tb, extack);</div><div class='add'>+	if (err)</div><div class='add'>+		return err;</div><div class='add'>+</div><div class='add'>+	vxlan_mdb_flush(vxlan, &amp;desc);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static const struct nla_policy vxlan_mdbe_attrs_get_pol[MDBE_ATTR_MAX + 1] = {</div><div class='ctx'> 	[MDBE_ATTR_SOURCE] = NLA_POLICY_RANGE(NLA_BINARY,</div><div class='ctx'> 					      sizeof(struct in_addr),</div><div class='hunk'>@@ -1575,29 +1722,6 @@ static void vxlan_mdb_check_empty(void *ptr, void *arg)</div><div class='ctx'> 	WARN_ON_ONCE(1);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static void vxlan_mdb_remotes_flush(struct vxlan_dev *vxlan,</div><div class='del'>-				    struct vxlan_mdb_entry *mdb_entry)</div><div class='del'>-{</div><div class='del'>-	struct vxlan_mdb_remote *remote, *tmp;</div><div class='del'>-</div><div class='del'>-	list_for_each_entry_safe(remote, tmp, &amp;mdb_entry-&gt;remotes, list)</div><div class='del'>-		vxlan_mdb_remote_del(vxlan, mdb_entry, remote);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void vxlan_mdb_entries_flush(struct vxlan_dev *vxlan)</div><div class='del'>-{</div><div class='del'>-	struct vxlan_mdb_entry *mdb_entry;</div><div class='del'>-	struct hlist_node *tmp;</div><div class='del'>-</div><div class='del'>-	/* The removal of an entry cannot trigger the removal of another entry</div><div class='del'>-	 * since entries are always added to the head of the list.</div><div class='del'>-	 */</div><div class='del'>-	hlist_for_each_entry_safe(mdb_entry, tmp, &amp;vxlan-&gt;mdb_list, mdb_node) {</div><div class='del'>-		vxlan_mdb_remotes_flush(vxlan, mdb_entry);</div><div class='del'>-		vxlan_mdb_entry_put(vxlan, mdb_entry);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='ctx'> int vxlan_mdb_init(struct vxlan_dev *vxlan)</div><div class='ctx'> {</div><div class='ctx'> 	int err;</div><div class='hunk'>@@ -1613,7 +1737,9 @@ int vxlan_mdb_init(struct vxlan_dev *vxlan)</div><div class='ctx'> </div><div class='ctx'> void vxlan_mdb_fini(struct vxlan_dev *vxlan)</div><div class='ctx'> {</div><div class='del'>-	vxlan_mdb_entries_flush(vxlan);</div><div class='add'>+	struct vxlan_mdb_flush_desc desc = {};</div><div class='add'>+</div><div class='add'>+	vxlan_mdb_flush(vxlan, &amp;desc);</div><div class='ctx'> 	WARN_ON_ONCE(vxlan-&gt;cfg.flags &amp; VXLAN_F_MDB);</div><div class='ctx'> 	rhashtable_free_and_destroy(&amp;vxlan-&gt;mdb_tbl, vxlan_mdb_check_empty,</div><div class='ctx'> 				    NULL);</div><div class='head'>diff --git a/drivers/net/vxlan/vxlan_private.h b/drivers/net/vxlan/vxlan_private.h<br/>index db679c380955..b35d96b78843 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_private.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/vxlan/vxlan_private.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/vxlan/vxlan_private.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/vxlan/vxlan_private.h</a></div><div class='hunk'>@@ -235,6 +235,8 @@ int vxlan_mdb_add(struct net_device *dev, struct nlattr *tb[], u16 nlmsg_flags,</div><div class='ctx'> 		  struct netlink_ext_ack *extack);</div><div class='ctx'> int vxlan_mdb_del(struct net_device *dev, struct nlattr *tb[],</div><div class='ctx'> 		  struct netlink_ext_ack *extack);</div><div class='add'>+int vxlan_mdb_del_bulk(struct net_device *dev, struct nlattr *tb[],</div><div class='add'>+		       struct netlink_ext_ack *extack);</div><div class='ctx'> int vxlan_mdb_get(struct net_device *dev, struct nlattr *tb[], u32 portid,</div><div class='ctx'> 		  u32 seq, struct netlink_ext_ack *extack);</div><div class='ctx'> struct vxlan_mdb_entry *vxlan_mdb_entry_skb_get(struct vxlan_dev *vxlan,</div><div class='head'>diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig<br/>index dcb069dde66b..7dda87756d3f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wan/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wan/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/Kconfig</a></div><div class='hunk'>@@ -95,6 +95,8 @@ config HDLC_X25</div><div class='ctx'> comment "X.25/LAPB support is disabled"</div><div class='ctx'> 	depends on HDLC &amp;&amp; (LAPB!=m || HDLC!=m) &amp;&amp; LAPB!=y</div><div class='ctx'> </div><div class='add'>+source "drivers/net/wan/framer/Kconfig"</div><div class='add'>+</div><div class='ctx'> config PCI200SYN</div><div class='ctx'> 	tristate "Goramo PCI200SYN support"</div><div class='ctx'> 	depends on HDLC &amp;&amp; PCI</div><div class='head'>diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile<br/>index 5bec8fae47f8..8119b49d1da9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wan/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wan/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/Makefile</a></div><div class='hunk'>@@ -14,6 +14,8 @@ obj-$(CONFIG_HDLC_FR)		+= hdlc_fr.o</div><div class='ctx'> obj-$(CONFIG_HDLC_PPP)		+= hdlc_ppp.o</div><div class='ctx'> obj-$(CONFIG_HDLC_X25)		+= hdlc_x25.o</div><div class='ctx'> </div><div class='add'>+obj-y				+= framer/</div><div class='add'>+</div><div class='ctx'> obj-$(CONFIG_FARSYNC)		+= farsync.o</div><div class='ctx'> </div><div class='ctx'> obj-$(CONFIG_LAPBETHER)		+= lapbether.o</div><div class='head'>diff --git a/drivers/net/wan/framer/Kconfig b/drivers/net/wan/framer/Kconfig<br/>new file mode 100644<br/>index 000000000000..dc83caef9485<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/Kconfig</a></div><div class='hunk'>@@ -0,0 +1,42 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0-only</div><div class='add'>+#</div><div class='add'>+# FRAMER</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+menuconfig FRAMER</div><div class='add'>+	tristate "Framer Subsystem"</div><div class='add'>+	help</div><div class='add'>+	  A framer is a component in charge of an E1/T1 line interface.</div><div class='add'>+	  Connected usually to a TDM bus, it converts TDM frames to/from E1/T1</div><div class='add'>+	  frames. It also provides information related to the E1/T1 line.</div><div class='add'>+	  Used with HDLC, the network can be reached through the E1/T1 line.</div><div class='add'>+</div><div class='add'>+	  This framework is designed to provide a generic interface for framer</div><div class='add'>+	  devices present in the kernel. This layer will have the generic</div><div class='add'>+	  API by which framer drivers can create framer using the framer</div><div class='add'>+	  framework and framer users can obtain reference to the framer.</div><div class='add'>+	  All the users of this framework should select this config.</div><div class='add'>+</div><div class='add'>+if FRAMER</div><div class='add'>+</div><div class='add'>+config GENERIC_FRAMER</div><div class='add'>+	bool</div><div class='add'>+</div><div class='add'>+config FRAMER_PEF2256</div><div class='add'>+	tristate "Lantiq PEF2256"</div><div class='add'>+	depends on OF</div><div class='add'>+	depends on HAS_IOMEM</div><div class='add'>+	select GENERIC_FRAMER</div><div class='add'>+	select MFD_CORE</div><div class='add'>+	select REGMAP_MMIO</div><div class='add'>+	help</div><div class='add'>+	  Enable support for the Lantiq PEF2256 (FALC56) framer.</div><div class='add'>+	  The PEF2256 is a framer and line interface between analog E1/T1/J1</div><div class='add'>+	  line and a digital PCM bus.</div><div class='add'>+</div><div class='add'>+	  If unsure, say N.</div><div class='add'>+</div><div class='add'>+	  To compile this driver as a module, choose M here: the</div><div class='add'>+	  module will be called framer-pef2256.</div><div class='add'>+</div><div class='add'>+endif # FRAMER</div><div class='head'>diff --git a/drivers/net/wan/framer/Makefile b/drivers/net/wan/framer/Makefile<br/>new file mode 100644<br/>index 000000000000..3403f2b14534<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/Makefile</a></div><div class='hunk'>@@ -0,0 +1,7 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# Makefile for the framer drivers.</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_GENERIC_FRAMER)			+= framer-core.o</div><div class='add'>+obj-$(CONFIG_FRAMER_PEF2256)			+= pef2256/</div><div class='head'>diff --git a/drivers/net/wan/framer/framer-core.c b/drivers/net/wan/framer/framer-core.c<br/>new file mode 100644<br/>index 000000000000..c04dc88bda6c<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/framer-core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/framer-core.c</a></div><div class='hunk'>@@ -0,0 +1,882 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='add'>+/*</div><div class='add'>+ * Generic Framer framework.</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 CS GROUP France</div><div class='add'>+ *</div><div class='add'>+ * Author: Herve Codina &lt;herve.codina@bootlin.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/device.h&gt;</div><div class='add'>+#include &lt;linux/framer/framer.h&gt;</div><div class='add'>+#include &lt;linux/framer/framer-provider.h&gt;</div><div class='add'>+#include &lt;linux/idr.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/notifier.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/pm_runtime.h&gt;</div><div class='add'>+#include &lt;linux/regulator/consumer.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+</div><div class='add'>+static struct class *framer_class;</div><div class='add'>+static DEFINE_MUTEX(framer_provider_mutex);</div><div class='add'>+static LIST_HEAD(framer_provider_list);</div><div class='add'>+static DEFINE_IDA(framer_ida);</div><div class='add'>+</div><div class='add'>+#define dev_to_framer(a)	(container_of((a), struct framer, dev))</div><div class='add'>+</div><div class='add'>+int framer_pm_runtime_get(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pm_runtime_enabled(&amp;framer-&gt;dev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_get(&amp;framer-&gt;dev);</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EINPROGRESS)</div><div class='add'>+		pm_runtime_put_noidle(&amp;framer-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_pm_runtime_get);</div><div class='add'>+</div><div class='add'>+int framer_pm_runtime_get_sync(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!pm_runtime_enabled(&amp;framer-&gt;dev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	ret = pm_runtime_get_sync(&amp;framer-&gt;dev);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		pm_runtime_put_sync(&amp;framer-&gt;dev);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_pm_runtime_get_sync);</div><div class='add'>+</div><div class='add'>+int framer_pm_runtime_put(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	if (!pm_runtime_enabled(&amp;framer-&gt;dev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return pm_runtime_put(&amp;framer-&gt;dev);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_pm_runtime_put);</div><div class='add'>+</div><div class='add'>+int framer_pm_runtime_put_sync(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	if (!pm_runtime_enabled(&amp;framer-&gt;dev))</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	return pm_runtime_put_sync(&amp;framer-&gt;dev);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_pm_runtime_put_sync);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_init - framer internal initialization before framer operation</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ *</div><div class='add'>+ * Used to allow framer's driver to perform framer internal initialization,</div><div class='add'>+ * such as PLL block powering, clock initialization or anything that's</div><div class='add'>+ * is required by the framer to perform the start of operation.</div><div class='add'>+ * Must be called before framer_power_on().</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_init(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	bool start_polling = false;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = framer_pm_runtime_get_sync(framer);</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = 0; /* Override possible ret == -EOPNOTSUPP */</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	if (framer-&gt;power_count &gt; framer-&gt;init_count)</div><div class='add'>+		dev_warn(&amp;framer-&gt;dev, "framer_power_on was called before framer init\n");</div><div class='add'>+</div><div class='add'>+	if (framer-&gt;init_count == 0) {</div><div class='add'>+		if (framer-&gt;ops-&gt;init) {</div><div class='add'>+			ret = framer-&gt;ops-&gt;init(framer);</div><div class='add'>+			if (ret &lt; 0) {</div><div class='add'>+				dev_err(&amp;framer-&gt;dev, "framer init failed --&gt; %d\n", ret);</div><div class='add'>+				goto out;</div><div class='add'>+			}</div><div class='add'>+		}</div><div class='add'>+		if (framer-&gt;ops-&gt;flags &amp; FRAMER_FLAG_POLL_STATUS)</div><div class='add'>+			start_polling = true;</div><div class='add'>+	}</div><div class='add'>+	++framer-&gt;init_count;</div><div class='add'>+</div><div class='add'>+out:</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	if (!ret &amp;&amp; start_polling) {</div><div class='add'>+		ret = framer_get_status(framer, &amp;framer-&gt;prev_status);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_warn(&amp;framer-&gt;dev, "framer get status failed --&gt; %d\n", ret);</div><div class='add'>+			/* Will be retried on polling_work */</div><div class='add'>+			ret = 0;</div><div class='add'>+		}</div><div class='add'>+		queue_delayed_work(system_power_efficient_wq, &amp;framer-&gt;polling_work, 1 * HZ);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	framer_pm_runtime_put(framer);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_init);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_exit - Framer internal un-initialization</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ *</div><div class='add'>+ * Must be called after framer_power_off().</div><div class='add'>+ */</div><div class='add'>+int framer_exit(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = framer_pm_runtime_get_sync(framer);</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+		return ret;</div><div class='add'>+	ret = 0; /* Override possible ret == -EOPNOTSUPP */</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	--framer-&gt;init_count;</div><div class='add'>+	if (framer-&gt;init_count == 0) {</div><div class='add'>+		if (framer-&gt;ops-&gt;flags &amp; FRAMER_FLAG_POLL_STATUS) {</div><div class='add'>+			mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+			cancel_delayed_work_sync(&amp;framer-&gt;polling_work);</div><div class='add'>+			mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		if (framer-&gt;ops-&gt;exit)</div><div class='add'>+			framer-&gt;ops-&gt;exit(framer);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+	framer_pm_runtime_put(framer);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_exit);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_power_on - Enable the framer and enter proper operation</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ *</div><div class='add'>+ * Must be called after framer_init().</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_power_on(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (framer-&gt;pwr) {</div><div class='add'>+		ret = regulator_enable(framer-&gt;pwr);</div><div class='add'>+		if (ret)</div><div class='add'>+			return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = framer_pm_runtime_get_sync(framer);</div><div class='add'>+	if (ret &lt; 0 &amp;&amp; ret != -EOPNOTSUPP)</div><div class='add'>+		goto err_pm_sync;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	if (framer-&gt;power_count == 0 &amp;&amp; framer-&gt;ops-&gt;power_on) {</div><div class='add'>+		ret = framer-&gt;ops-&gt;power_on(framer);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(&amp;framer-&gt;dev, "framer poweron failed --&gt; %d\n", ret);</div><div class='add'>+			goto err_pwr_on;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	++framer-&gt;power_count;</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+	return 0;</div><div class='add'>+</div><div class='add'>+err_pwr_on:</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+	framer_pm_runtime_put_sync(framer);</div><div class='add'>+err_pm_sync:</div><div class='add'>+	if (framer-&gt;pwr)</div><div class='add'>+		regulator_disable(framer-&gt;pwr);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_power_on);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_power_off - Disable the framer.</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ *</div><div class='add'>+ * Must be called before framer_exit().</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_power_off(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	if (framer-&gt;power_count == 1 &amp;&amp; framer-&gt;ops-&gt;power_off) {</div><div class='add'>+		ret = framer-&gt;ops-&gt;power_off(framer);</div><div class='add'>+		if (ret &lt; 0) {</div><div class='add'>+			dev_err(&amp;framer-&gt;dev, "framer poweroff failed --&gt; %d\n", ret);</div><div class='add'>+			mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+			return ret;</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+	--framer-&gt;power_count;</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+	framer_pm_runtime_put(framer);</div><div class='add'>+</div><div class='add'>+	if (framer-&gt;pwr)</div><div class='add'>+		regulator_disable(framer-&gt;pwr);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_power_off);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_get_status() - Gets the framer status</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ * @status: the status to retrieve</div><div class='add'>+ *</div><div class='add'>+ * Used to get the framer status. framer_init() must have been called</div><div class='add'>+ * on the framer.</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_get_status(struct framer *framer, struct framer_status *status)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!framer-&gt;ops-&gt;get_status)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	/* Be sure to have known values (struct padding and future extensions) */</div><div class='add'>+	memset(status, 0, sizeof(*status));</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	ret = framer-&gt;ops-&gt;get_status(framer, status);</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_get_status);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_set_config() - Sets the framer configuration</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ * @config: the configuration to set</div><div class='add'>+ *</div><div class='add'>+ * Used to set the framer configuration. framer_init() must have been called</div><div class='add'>+ * on the framer.</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_set_config(struct framer *framer, const struct framer_config *config)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!framer-&gt;ops-&gt;set_config)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	ret = framer-&gt;ops-&gt;set_config(framer, config);</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_set_config);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_get_config() - Gets the framer configuration</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ * @config: the configuration to retrieve</div><div class='add'>+ *</div><div class='add'>+ * Used to get the framer configuration. framer_init() must have been called</div><div class='add'>+ * on the framer.</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_get_config(struct framer *framer, struct framer_config *config)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (!framer-&gt;ops-&gt;get_config)</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer-&gt;mutex);</div><div class='add'>+	ret = framer-&gt;ops-&gt;get_config(framer, config);</div><div class='add'>+	mutex_unlock(&amp;framer-&gt;mutex);</div><div class='add'>+</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_get_config);</div><div class='add'>+</div><div class='add'>+static void framer_polling_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = container_of(work, struct framer, polling_work.work);</div><div class='add'>+	struct framer_status status;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = framer_get_status(framer, &amp;status);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(&amp;framer-&gt;dev, "polling, get status failed (%d)\n", ret);</div><div class='add'>+		goto end;</div><div class='add'>+	}</div><div class='add'>+	if (memcmp(&amp;framer-&gt;prev_status, &amp;status, sizeof(status))) {</div><div class='add'>+		blocking_notifier_call_chain(&amp;framer-&gt;notifier_list,</div><div class='add'>+					     FRAMER_EVENT_STATUS, NULL);</div><div class='add'>+		memcpy(&amp;framer-&gt;prev_status, &amp;status, sizeof(status));</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+end:</div><div class='add'>+	/* Re-schedule task in 1 sec */</div><div class='add'>+	queue_delayed_work(system_power_efficient_wq, &amp;framer-&gt;polling_work, 1 * HZ);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_notifier_register() - Registers a notifier</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ * @nb: the notifier block to register</div><div class='add'>+ *</div><div class='add'>+ * Used to register a notifier block on framer events. framer_init() must have</div><div class='add'>+ * been called on the framer.</div><div class='add'>+ * The available framer events are present in enum framer_events.</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_notifier_register(struct framer *framer, struct notifier_block *nb)</div><div class='add'>+{</div><div class='add'>+	return blocking_notifier_chain_register(&amp;framer-&gt;notifier_list, nb);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_notifier_register);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_notifier_unregister() - Unregisters a notifier</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ * @nb: the notifier block to unregister</div><div class='add'>+ *</div><div class='add'>+ * Used to unregister a notifier block. framer_init() must have</div><div class='add'>+ * been called on the framer.</div><div class='add'>+ *</div><div class='add'>+ * Return: %0 if successful, a negative error code otherwise</div><div class='add'>+ */</div><div class='add'>+int framer_notifier_unregister(struct framer *framer, struct notifier_block *nb)</div><div class='add'>+{</div><div class='add'>+	return blocking_notifier_chain_unregister(&amp;framer-&gt;notifier_list, nb);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_notifier_unregister);</div><div class='add'>+</div><div class='add'>+static struct framer_provider *framer_provider_of_lookup(const struct device_node *node)</div><div class='add'>+{</div><div class='add'>+	struct framer_provider *framer_provider;</div><div class='add'>+</div><div class='add'>+	list_for_each_entry(framer_provider, &amp;framer_provider_list, list) {</div><div class='add'>+		if (device_match_of_node(framer_provider-&gt;dev, node))</div><div class='add'>+			return framer_provider;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-EPROBE_DEFER);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct framer *framer_of_get_from_provider(struct of_phandle_args *args)</div><div class='add'>+{</div><div class='add'>+	struct framer_provider *framer_provider;</div><div class='add'>+	struct framer *framer;</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer_provider_mutex);</div><div class='add'>+	framer_provider = framer_provider_of_lookup(args-&gt;np);</div><div class='add'>+	if (IS_ERR(framer_provider) || !try_module_get(framer_provider-&gt;owner)) {</div><div class='add'>+		framer = ERR_PTR(-EPROBE_DEFER);</div><div class='add'>+		goto end;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	framer = framer_provider-&gt;of_xlate(framer_provider-&gt;dev, args);</div><div class='add'>+</div><div class='add'>+	module_put(framer_provider-&gt;owner);</div><div class='add'>+</div><div class='add'>+end:</div><div class='add'>+	mutex_unlock(&amp;framer_provider_mutex);</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct framer *framer_of_get_byphandle(struct device_node *np, const char *propname,</div><div class='add'>+					      int index)</div><div class='add'>+{</div><div class='add'>+	struct of_phandle_args args;</div><div class='add'>+	struct framer *framer;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	ret = of_parse_phandle_with_optional_args(np, propname, "#framer-cells", index, &amp;args);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ERR_PTR(-ENODEV);</div><div class='add'>+</div><div class='add'>+	if (!of_device_is_available(args.np)) {</div><div class='add'>+		framer = ERR_PTR(-ENODEV);</div><div class='add'>+		goto out_node_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	framer = framer_of_get_from_provider(&amp;args);</div><div class='add'>+</div><div class='add'>+out_node_put:</div><div class='add'>+	of_node_put(args.np);</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static struct framer *framer_of_get_byparent(struct device_node *np, int index)</div><div class='add'>+{</div><div class='add'>+	struct of_phandle_args args;</div><div class='add'>+	struct framer *framer;</div><div class='add'>+</div><div class='add'>+	args.np = of_get_parent(np);</div><div class='add'>+	args.args_count = 1;</div><div class='add'>+	args.args[0] = index;</div><div class='add'>+</div><div class='add'>+	while (args.np) {</div><div class='add'>+		framer = framer_of_get_from_provider(&amp;args);</div><div class='add'>+		if (IS_ERR(framer) &amp;&amp; PTR_ERR(framer) != -EPROBE_DEFER) {</div><div class='add'>+			args.np = of_get_next_parent(args.np);</div><div class='add'>+			continue;</div><div class='add'>+		}</div><div class='add'>+		of_node_put(args.np);</div><div class='add'>+		return framer;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return ERR_PTR(-ENODEV);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_get() - lookup and obtain a reference to a framer.</div><div class='add'>+ * @dev: device that requests the framer</div><div class='add'>+ * @con_id: name of the framer from device's point of view</div><div class='add'>+ *</div><div class='add'>+ * Returns the framer driver, after getting a refcount to it; or</div><div class='add'>+ * -ENODEV if there is no such framer. The caller is responsible for</div><div class='add'>+ * calling framer_put() to release that count.</div><div class='add'>+ */</div><div class='add'>+struct framer *framer_get(struct device *dev, const char *con_id)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = ERR_PTR(-ENODEV);</div><div class='add'>+	struct device_link *link;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	if (dev-&gt;of_node) {</div><div class='add'>+		if (con_id)</div><div class='add'>+			framer = framer_of_get_byphandle(dev-&gt;of_node, con_id, 0);</div><div class='add'>+		else</div><div class='add'>+			framer = framer_of_get_byparent(dev-&gt;of_node, 0);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (IS_ERR(framer))</div><div class='add'>+		return framer;</div><div class='add'>+</div><div class='add'>+	get_device(&amp;framer-&gt;dev);</div><div class='add'>+</div><div class='add'>+	if (!try_module_get(framer-&gt;ops-&gt;owner)) {</div><div class='add'>+		ret = -EPROBE_DEFER;</div><div class='add'>+		goto err_put_device;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	link = device_link_add(dev, &amp;framer-&gt;dev, DL_FLAG_STATELESS);</div><div class='add'>+	if (!link) {</div><div class='add'>+		dev_err(dev, "failed to create device_link to %s\n", dev_name(&amp;framer-&gt;dev));</div><div class='add'>+		ret = -EPROBE_DEFER;</div><div class='add'>+		goto err_module_put;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+</div><div class='add'>+err_module_put:</div><div class='add'>+	module_put(framer-&gt;ops-&gt;owner);</div><div class='add'>+err_put_device:</div><div class='add'>+	put_device(&amp;framer-&gt;dev);</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_get);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_put() - release the framer</div><div class='add'>+ * @dev: device that wants to release this framer</div><div class='add'>+ * @framer: the framer returned by framer_get()</div><div class='add'>+ *</div><div class='add'>+ * Releases a refcount the caller received from framer_get().</div><div class='add'>+ */</div><div class='add'>+void framer_put(struct device *dev, struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	device_link_remove(dev, &amp;framer-&gt;dev);</div><div class='add'>+</div><div class='add'>+	module_put(framer-&gt;ops-&gt;owner);</div><div class='add'>+	put_device(&amp;framer-&gt;dev);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_put);</div><div class='add'>+</div><div class='add'>+static void devm_framer_put(struct device *dev, void *res)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = *(struct framer **)res;</div><div class='add'>+</div><div class='add'>+	framer_put(dev, framer);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * devm_framer_get() - lookup and obtain a reference to a framer.</div><div class='add'>+ * @dev: device that requests this framer</div><div class='add'>+ * @con_id: name of the framer from device's point of view</div><div class='add'>+ *</div><div class='add'>+ * Gets the framer using framer_get(), and associates a device with it using</div><div class='add'>+ * devres. On driver detach, framer_put() function is invoked on the devres</div><div class='add'>+ * data, then, devres data is freed.</div><div class='add'>+ */</div><div class='add'>+struct framer *devm_framer_get(struct device *dev, const char *con_id)</div><div class='add'>+{</div><div class='add'>+	struct framer **ptr, *framer;</div><div class='add'>+</div><div class='add'>+	ptr = devres_alloc(devm_framer_put, sizeof(*ptr), GFP_KERNEL);</div><div class='add'>+	if (!ptr)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	framer = framer_get(dev, con_id);</div><div class='add'>+	if (!IS_ERR(framer)) {</div><div class='add'>+		*ptr = framer;</div><div class='add'>+		devres_add(dev, ptr);</div><div class='add'>+	} else {</div><div class='add'>+		devres_free(ptr);</div><div class='add'>+		return framer;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(devm_framer_get);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * devm_framer_optional_get() - lookup and obtain a reference to an optional</div><div class='add'>+ * framer.</div><div class='add'>+ * @dev: device that requests this framer</div><div class='add'>+ * @con_id: name of the framer from device's point of view</div><div class='add'>+ *</div><div class='add'>+ * Same as devm_framer_get() except that if the framer does not exist, it is not</div><div class='add'>+ * considered an error and -ENODEV will not be returned. Instead the NULL framer</div><div class='add'>+ * is returned.</div><div class='add'>+ */</div><div class='add'>+struct framer *devm_framer_optional_get(struct device *dev, const char *con_id)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = devm_framer_get(dev, con_id);</div><div class='add'>+</div><div class='add'>+	if (PTR_ERR(framer) == -ENODEV)</div><div class='add'>+		framer = NULL;</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(devm_framer_optional_get);</div><div class='add'>+</div><div class='add'>+static void framer_notify_status_work(struct work_struct *work)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = container_of(work, struct framer, notify_status_work);</div><div class='add'>+</div><div class='add'>+	blocking_notifier_call_chain(&amp;framer-&gt;notifier_list, FRAMER_EVENT_STATUS, NULL);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+void framer_notify_status_change(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	/* Can be called from atomic context -&gt; just schedule a task to call</div><div class='add'>+	 * blocking notifiers</div><div class='add'>+	 */</div><div class='add'>+	queue_work(system_power_efficient_wq, &amp;framer-&gt;notify_status_work);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_notify_status_change);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_create() - create a new framer</div><div class='add'>+ * @dev: device that is creating the new framer</div><div class='add'>+ * @node: device node of the framer. default to dev-&gt;of_node.</div><div class='add'>+ * @ops: function pointers for performing framer operations</div><div class='add'>+ *</div><div class='add'>+ * Called to create a framer using framer framework.</div><div class='add'>+ */</div><div class='add'>+struct framer *framer_create(struct device *dev, struct device_node *node,</div><div class='add'>+			     const struct framer_ops *ops)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer;</div><div class='add'>+	int ret;</div><div class='add'>+	int id;</div><div class='add'>+</div><div class='add'>+	/* get_status() is mandatory if the provider ask for polling status */</div><div class='add'>+	if (WARN_ON((ops-&gt;flags &amp; FRAMER_FLAG_POLL_STATUS) &amp;&amp; !ops-&gt;get_status))</div><div class='add'>+		return ERR_PTR(-EINVAL);</div><div class='add'>+</div><div class='add'>+	framer = kzalloc(sizeof(*framer), GFP_KERNEL);</div><div class='add'>+	if (!framer)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	id = ida_alloc(&amp;framer_ida, GFP_KERNEL);</div><div class='add'>+	if (id &lt; 0) {</div><div class='add'>+		dev_err(dev, "unable to get id\n");</div><div class='add'>+		ret = id;</div><div class='add'>+		goto free_framer;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	device_initialize(&amp;framer-&gt;dev);</div><div class='add'>+	mutex_init(&amp;framer-&gt;mutex);</div><div class='add'>+	INIT_WORK(&amp;framer-&gt;notify_status_work, framer_notify_status_work);</div><div class='add'>+	INIT_DELAYED_WORK(&amp;framer-&gt;polling_work, framer_polling_work);</div><div class='add'>+	BLOCKING_INIT_NOTIFIER_HEAD(&amp;framer-&gt;notifier_list);</div><div class='add'>+</div><div class='add'>+	framer-&gt;dev.class = framer_class;</div><div class='add'>+	framer-&gt;dev.parent = dev;</div><div class='add'>+	framer-&gt;dev.of_node = node ? node : dev-&gt;of_node;</div><div class='add'>+	framer-&gt;id = id;</div><div class='add'>+	framer-&gt;ops = ops;</div><div class='add'>+</div><div class='add'>+	ret = dev_set_name(&amp;framer-&gt;dev, "framer-%s.%d", dev_name(dev), id);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto put_dev;</div><div class='add'>+</div><div class='add'>+	/* framer-supply */</div><div class='add'>+	framer-&gt;pwr = regulator_get_optional(&amp;framer-&gt;dev, "framer");</div><div class='add'>+	if (IS_ERR(framer-&gt;pwr)) {</div><div class='add'>+		ret = PTR_ERR(framer-&gt;pwr);</div><div class='add'>+		if (ret == -EPROBE_DEFER)</div><div class='add'>+			goto put_dev;</div><div class='add'>+</div><div class='add'>+		framer-&gt;pwr = NULL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = device_add(&amp;framer-&gt;dev);</div><div class='add'>+	if (ret)</div><div class='add'>+		goto put_dev;</div><div class='add'>+</div><div class='add'>+	if (pm_runtime_enabled(dev)) {</div><div class='add'>+		pm_runtime_enable(&amp;framer-&gt;dev);</div><div class='add'>+		pm_runtime_no_callbacks(&amp;framer-&gt;dev);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+</div><div class='add'>+put_dev:</div><div class='add'>+	put_device(&amp;framer-&gt;dev);  /* calls framer_release() which frees resources */</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+</div><div class='add'>+free_framer:</div><div class='add'>+	kfree(framer);</div><div class='add'>+	return ERR_PTR(ret);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_create);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_destroy() - destroy the framer</div><div class='add'>+ * @framer: the framer to be destroyed</div><div class='add'>+ *</div><div class='add'>+ * Called to destroy the framer.</div><div class='add'>+ */</div><div class='add'>+void framer_destroy(struct framer *framer)</div><div class='add'>+{</div><div class='add'>+	/* polling_work should already be stopped but if framer_exit() was not</div><div class='add'>+	 * called (bug), here it's the last time to do that ...</div><div class='add'>+	 */</div><div class='add'>+	cancel_delayed_work_sync(&amp;framer-&gt;polling_work);</div><div class='add'>+	cancel_work_sync(&amp;framer-&gt;notify_status_work);</div><div class='add'>+	pm_runtime_disable(&amp;framer-&gt;dev);</div><div class='add'>+	device_unregister(&amp;framer-&gt;dev); /* calls framer_release() which frees resources */</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_destroy);</div><div class='add'>+</div><div class='add'>+static void devm_framer_destroy(struct device *dev, void *res)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer = *(struct framer **)res;</div><div class='add'>+</div><div class='add'>+	framer_destroy(framer);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * devm_framer_create() - create a new framer</div><div class='add'>+ * @dev: device that is creating the new framer</div><div class='add'>+ * @node: device node of the framer</div><div class='add'>+ * @ops: function pointers for performing framer operations</div><div class='add'>+ *</div><div class='add'>+ * Creates a new framer device adding it to the framer class.</div><div class='add'>+ * While at that, it also associates the device with the framer using devres.</div><div class='add'>+ * On driver detach, release function is invoked on the devres data,</div><div class='add'>+ * then, devres data is freed.</div><div class='add'>+ */</div><div class='add'>+struct framer *devm_framer_create(struct device *dev, struct device_node *node,</div><div class='add'>+				  const struct framer_ops *ops)</div><div class='add'>+{</div><div class='add'>+	struct framer **ptr, *framer;</div><div class='add'>+</div><div class='add'>+	ptr = devres_alloc(devm_framer_destroy, sizeof(*ptr), GFP_KERNEL);</div><div class='add'>+	if (!ptr)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	framer = framer_create(dev, node, ops);</div><div class='add'>+	if (!IS_ERR(framer)) {</div><div class='add'>+		*ptr = framer;</div><div class='add'>+		devres_add(dev, ptr);</div><div class='add'>+	} else {</div><div class='add'>+		devres_free(ptr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return framer;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(devm_framer_create);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_provider_simple_of_xlate() - returns the framer instance from framer provider</div><div class='add'>+ * @dev: the framer provider device</div><div class='add'>+ * @args: of_phandle_args (not used here)</div><div class='add'>+ *</div><div class='add'>+ * Intended to be used by framer provider for the common case where #framer-cells is</div><div class='add'>+ * 0. For other cases where #framer-cells is greater than '0', the framer provider</div><div class='add'>+ * should provide a custom of_xlate function that reads the *args* and returns</div><div class='add'>+ * the appropriate framer.</div><div class='add'>+ */</div><div class='add'>+struct framer *framer_provider_simple_of_xlate(struct device *dev, struct of_phandle_args *args)</div><div class='add'>+{</div><div class='add'>+	struct class_dev_iter iter;</div><div class='add'>+	struct framer *framer;</div><div class='add'>+</div><div class='add'>+	class_dev_iter_init(&amp;iter, framer_class, NULL, NULL);</div><div class='add'>+	while ((dev = class_dev_iter_next(&amp;iter))) {</div><div class='add'>+		framer = dev_to_framer(dev);</div><div class='add'>+		if (args-&gt;np != framer-&gt;dev.of_node)</div><div class='add'>+			continue;</div><div class='add'>+</div><div class='add'>+		class_dev_iter_exit(&amp;iter);</div><div class='add'>+		return framer;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	class_dev_iter_exit(&amp;iter);</div><div class='add'>+	return ERR_PTR(-ENODEV);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_provider_simple_of_xlate);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __framer_provider_of_register() - create/register framer provider with the framework</div><div class='add'>+ * @dev: struct device of the framer provider</div><div class='add'>+ * @owner: the module owner containing of_xlate</div><div class='add'>+ * @of_xlate: function pointer to obtain framer instance from framer provider</div><div class='add'>+ *</div><div class='add'>+ * Creates struct framer_provider from dev and of_xlate function pointer.</div><div class='add'>+ * This is used in the case of dt boot for finding the framer instance from</div><div class='add'>+ * framer provider.</div><div class='add'>+ */</div><div class='add'>+struct framer_provider *</div><div class='add'>+__framer_provider_of_register(struct device *dev, struct module *owner,</div><div class='add'>+			      struct framer *(*of_xlate)(struct device *dev,</div><div class='add'>+							 struct of_phandle_args *args))</div><div class='add'>+{</div><div class='add'>+	struct framer_provider *framer_provider;</div><div class='add'>+</div><div class='add'>+	framer_provider = kzalloc(sizeof(*framer_provider), GFP_KERNEL);</div><div class='add'>+	if (!framer_provider)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	framer_provider-&gt;dev = dev;</div><div class='add'>+	framer_provider-&gt;owner = owner;</div><div class='add'>+	framer_provider-&gt;of_xlate = of_xlate;</div><div class='add'>+</div><div class='add'>+	of_node_get(framer_provider-&gt;dev-&gt;of_node);</div><div class='add'>+</div><div class='add'>+	mutex_lock(&amp;framer_provider_mutex);</div><div class='add'>+	list_add_tail(&amp;framer_provider-&gt;list, &amp;framer_provider_list);</div><div class='add'>+	mutex_unlock(&amp;framer_provider_mutex);</div><div class='add'>+</div><div class='add'>+	return framer_provider;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__framer_provider_of_register);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_provider_of_unregister() - unregister framer provider from the framework</div><div class='add'>+ * @framer_provider: framer provider returned by framer_provider_of_register()</div><div class='add'>+ *</div><div class='add'>+ * Removes the framer_provider created using framer_provider_of_register().</div><div class='add'>+ */</div><div class='add'>+void framer_provider_of_unregister(struct framer_provider *framer_provider)</div><div class='add'>+{</div><div class='add'>+	mutex_lock(&amp;framer_provider_mutex);</div><div class='add'>+	list_del(&amp;framer_provider-&gt;list);</div><div class='add'>+	mutex_unlock(&amp;framer_provider_mutex);</div><div class='add'>+</div><div class='add'>+	of_node_put(framer_provider-&gt;dev-&gt;of_node);</div><div class='add'>+	kfree(framer_provider);</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(framer_provider_of_unregister);</div><div class='add'>+</div><div class='add'>+static void devm_framer_provider_of_unregister(struct device *dev, void *res)</div><div class='add'>+{</div><div class='add'>+	struct framer_provider *framer_provider = *(struct framer_provider **)res;</div><div class='add'>+</div><div class='add'>+	framer_provider_of_unregister(framer_provider);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * __devm_framer_provider_of_register() - create/register framer provider with</div><div class='add'>+ * the framework</div><div class='add'>+ * @dev: struct device of the framer provider</div><div class='add'>+ * @owner: the module owner containing of_xlate</div><div class='add'>+ * @of_xlate: function pointer to obtain framer instance from framer provider</div><div class='add'>+ *</div><div class='add'>+ * Creates struct framer_provider from dev and of_xlate function pointer.</div><div class='add'>+ * This is used in the case of dt boot for finding the framer instance from</div><div class='add'>+ * framer provider. While at that, it also associates the device with the</div><div class='add'>+ * framer provider using devres. On driver detach, release function is invoked</div><div class='add'>+ * on the devres data, then, devres data is freed.</div><div class='add'>+ */</div><div class='add'>+struct framer_provider *</div><div class='add'>+__devm_framer_provider_of_register(struct device *dev, struct module *owner,</div><div class='add'>+				   struct framer *(*of_xlate)(struct device *dev,</div><div class='add'>+							      struct of_phandle_args *args))</div><div class='add'>+{</div><div class='add'>+	struct framer_provider **ptr, *framer_provider;</div><div class='add'>+</div><div class='add'>+	ptr = devres_alloc(devm_framer_provider_of_unregister, sizeof(*ptr), GFP_KERNEL);</div><div class='add'>+	if (!ptr)</div><div class='add'>+		return ERR_PTR(-ENOMEM);</div><div class='add'>+</div><div class='add'>+	framer_provider = __framer_provider_of_register(dev, owner, of_xlate);</div><div class='add'>+	if (!IS_ERR(framer_provider)) {</div><div class='add'>+		*ptr = framer_provider;</div><div class='add'>+		devres_add(dev, ptr);</div><div class='add'>+	} else {</div><div class='add'>+		devres_free(ptr);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return framer_provider;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(__devm_framer_provider_of_register);</div><div class='add'>+</div><div class='add'>+/**</div><div class='add'>+ * framer_release() - release the framer</div><div class='add'>+ * @dev: the dev member within framer</div><div class='add'>+ *</div><div class='add'>+ * When the last reference to the device is removed, it is called</div><div class='add'>+ * from the embedded kobject as release method.</div><div class='add'>+ */</div><div class='add'>+static void framer_release(struct device *dev)</div><div class='add'>+{</div><div class='add'>+	struct framer *framer;</div><div class='add'>+</div><div class='add'>+	framer = dev_to_framer(dev);</div><div class='add'>+	regulator_put(framer-&gt;pwr);</div><div class='add'>+	ida_free(&amp;framer_ida, framer-&gt;id);</div><div class='add'>+	kfree(framer);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int __init framer_core_init(void)</div><div class='add'>+{</div><div class='add'>+	framer_class = class_create("framer");</div><div class='add'>+	if (IS_ERR(framer_class)) {</div><div class='add'>+		pr_err("failed to create framer class (%pe)\n", framer_class);</div><div class='add'>+		return PTR_ERR(framer_class);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	framer_class-&gt;dev_release = framer_release;</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+device_initcall(framer_core_init);</div><div class='head'>diff --git a/drivers/net/wan/framer/pef2256/Makefile b/drivers/net/wan/framer/pef2256/Makefile<br/>new file mode 100644<br/>index 000000000000..f4d1208dd8a4<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/pef2256/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/Makefile</a></div><div class='hunk'>@@ -0,0 +1,8 @@</div><div class='add'>+# SPDX-License-Identifier: GPL-2.0</div><div class='add'>+#</div><div class='add'>+# Makefile for the pef2256 driver.</div><div class='add'>+#</div><div class='add'>+</div><div class='add'>+obj-$(CONFIG_FRAMER_PEF2256)		+= framer-pef2256.o</div><div class='add'>+</div><div class='add'>+framer-pef2256-objs	:= pef2256.o</div><div class='head'>diff --git a/drivers/net/wan/framer/pef2256/pef2256-regs.h b/drivers/net/wan/framer/pef2256/pef2256-regs.h<br/>new file mode 100644<br/>index 000000000000..5d3183c91714<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/pef2256/pef2256-regs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/pef2256-regs.h</a></div><div class='hunk'>@@ -0,0 +1,250 @@</div><div class='add'>+/* SPDX-License-Identifier: GPL-2.0 */</div><div class='add'>+/*</div><div class='add'>+ * PEF2256 registers definition</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 CS GROUP France</div><div class='add'>+ *</div><div class='add'>+ * Author: Herve Codina &lt;herve.codina@bootlin.com&gt;</div><div class='add'>+ */</div><div class='add'>+#ifndef __PEF2256_REGS_H__</div><div class='add'>+#define __PEF2256_REGS_H__</div><div class='add'>+</div><div class='add'>+#include "linux/bitfield.h"</div><div class='add'>+</div><div class='add'>+/* Command Register */</div><div class='add'>+#define PEF2256_CMDR		0x02</div><div class='add'>+#define PEF2256_CMDR_RRES	BIT(6)</div><div class='add'>+#define PEF2256_CMDR_XRES	BIT(4)</div><div class='add'>+#define PEF2256_CMDR_SRES	BIT(0)</div><div class='add'>+</div><div class='add'>+/* Interrupt Mask Register 0..5 */</div><div class='add'>+#define PEF2256_IMR0	        0x14</div><div class='add'>+#define PEF2256_IMR1	        0x15</div><div class='add'>+#define PEF2256_IMR2	        0x16</div><div class='add'>+#define PEF2256_IMR3	        0x17</div><div class='add'>+#define PEF2256_IMR4	        0x18</div><div class='add'>+#define PEF2256_IMR5	        0x19</div><div class='add'>+</div><div class='add'>+/* Framer Mode Register 0 */</div><div class='add'>+#define PEF2256_FMR0		0x1C</div><div class='add'>+#define PEF2256_FMR0_XC_MASK	GENMASK(7, 6)</div><div class='add'>+#define PEF2256_FMR0_XC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)</div><div class='add'>+#define PEF2256_FMR0_XC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)</div><div class='add'>+#define PEF2256_FMR0_XC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)</div><div class='add'>+#define PEF2256_FMR0_XC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)</div><div class='add'>+#define PEF2256_FMR0_RC_MASK	GENMASK(5, 4)</div><div class='add'>+#define PEF2256_FMR0_RC_NRZ	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)</div><div class='add'>+#define PEF2256_FMR0_RC_CMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)</div><div class='add'>+#define PEF2256_FMR0_RC_AMI	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)</div><div class='add'>+#define PEF2256_FMR0_RC_HDB3	FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)</div><div class='add'>+</div><div class='add'>+/* Framer Mode Register 1 */</div><div class='add'>+#define PEF2256_FMR1		0x1D</div><div class='add'>+#define PEF2256_FMR1_XFS	BIT(3)</div><div class='add'>+#define PEF2256_FMR1_ECM	BIT(2)</div><div class='add'>+/* SSD is defined on 2 bits. The other bit is on SIC1 register */</div><div class='add'>+#define PEF2256_FMR1_SSD_MASK	GENMASK(1, 1)</div><div class='add'>+#define PEF2256_FMR1_SSD_2048	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)</div><div class='add'>+#define PEF2256_FMR1_SSD_4096	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)</div><div class='add'>+#define PEF2256_FMR1_SSD_8192	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)</div><div class='add'>+#define PEF2256_FMR1_SSD_16384	FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)</div><div class='add'>+</div><div class='add'>+/* Framer Mode Register 2 */</div><div class='add'>+#define PEF2256_FMR2			  0x1E</div><div class='add'>+#define PEF2256_FMR2_RFS_MASK		  GENMASK(7, 6)</div><div class='add'>+#define PEF2256_FMR2_RFS_DOUBLEFRAME	  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0)</div><div class='add'>+#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2)</div><div class='add'>+#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME  FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)</div><div class='add'>+#define PEF2256_FMR2_AXRA		  BIT(1)</div><div class='add'>+</div><div class='add'>+/* Transmit Service Word */</div><div class='add'>+#define PEF2256_XSW		0x20</div><div class='add'>+#define PEF2256_XSW_XSIS	BIT(7)</div><div class='add'>+#define PEF2256_XSW_XTM		BIT(6)</div><div class='add'>+#define PEF2256_XSW_XY_MASK	GENMASK(5, 0)</div><div class='add'>+#define PEF2256_XSW_XY(_v)	FIELD_PREP(PEF2256_XSW_XY_MASK, _v)</div><div class='add'>+</div><div class='add'>+/* Transmit Spare Bits */</div><div class='add'>+#define PEF2256_XSP	        0x21</div><div class='add'>+#define PEF2256_XSP_XSIF	BIT(2)</div><div class='add'>+</div><div class='add'>+/* Transmit Control 0..1 */</div><div class='add'>+#define PEF2256_XC0		0x22</div><div class='add'>+#define PEF2256_XC1		0x23</div><div class='add'>+</div><div class='add'>+/* Receive Control 0 */</div><div class='add'>+#define PEF2256_RC0		0x24</div><div class='add'>+#define PEF2256_RC0_SWD		BIT(7)</div><div class='add'>+#define PEF2256_RC0_ASY4	BIT(6)</div><div class='add'>+</div><div class='add'>+/* Receive Control 1 */</div><div class='add'>+#define PEF2256_RC1		0x25</div><div class='add'>+</div><div class='add'>+/* Transmit Pulse Mask 0..1 */</div><div class='add'>+#define PEF2256_XPM0		0x26</div><div class='add'>+#define PEF2256_XPM1		0x27</div><div class='add'>+</div><div class='add'>+/* Transmit Pulse Mask 2 */</div><div class='add'>+#define PEF2256_XPM2		0x28</div><div class='add'>+#define PEF2256_XPM2_XLT	BIT(6)</div><div class='add'>+</div><div class='add'>+/* Transparent Service Word Mask */</div><div class='add'>+#define PEF2256_TSWM		0x29</div><div class='add'>+</div><div class='add'>+/* Line Interface Mode 0 */</div><div class='add'>+#define PEF2256_LIM0		0x36</div><div class='add'>+#define PEF2256_2X_LIM0_BIT3	BIT(3) /* v2.x, described as a forced '1' bit */</div><div class='add'>+#define PEF2256_LIM0_MAS	BIT(0)</div><div class='add'>+</div><div class='add'>+/* Line Interface Mode 1 */</div><div class='add'>+#define PEF2256_LIM1		  0x37</div><div class='add'>+#define PEF2256_12_LIM1_RIL_MASK  GENMASK(6, 4)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_910	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x0)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_740	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x1)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_590	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x2)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_420	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_320	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x4)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_210	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x5)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_160	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x6)</div><div class='add'>+#define PEF2256_12_LIM1_RIL_100	  FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x7)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_MASK  GENMASK(6, 4)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_2250  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x0)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_1100  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x1)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_600	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x2)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_350	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_210	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x4)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_140	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x5)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_100	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x6)</div><div class='add'>+#define PEF2256_2X_LIM1_RIL_50	  FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x7)</div><div class='add'>+</div><div class='add'>+/* Pulse Count Detection */</div><div class='add'>+#define PEF2256_PCD		0x38</div><div class='add'>+</div><div class='add'>+ /* Pulse Count Recovery */</div><div class='add'>+#define PEF2256_PCR		0x39</div><div class='add'>+</div><div class='add'>+ /* Line Interface Mode 2 */</div><div class='add'>+#define PEF2256_LIM2		0x3A</div><div class='add'>+#define PEF2256_LIM2_SLT_MASK	GENMASK(5, 4)</div><div class='add'>+#define PEF2256_LIM2_SLT_THR55	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x0)</div><div class='add'>+#define PEF2256_LIM2_SLT_THR67	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x1)</div><div class='add'>+#define PEF2256_LIM2_SLT_THR50	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x2)</div><div class='add'>+#define PEF2256_LIM2_SLT_THR45	FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3)</div><div class='add'>+#define PEF2256_LIM2_ELT	BIT(2)</div><div class='add'>+</div><div class='add'>+/* System Interface Control 1 */</div><div class='add'>+#define PEF2256_SIC1	          0x3E</div><div class='add'>+#define PEF2256_SIC1_SSC_MASK	  (BIT(7) |  BIT(3))</div><div class='add'>+#define PEF2256_SIC1_SSC_2048	  (0)</div><div class='add'>+#define PEF2256_SIC1_SSC_4096	  BIT(3)</div><div class='add'>+#define PEF2256_SIC1_SSC_8192	  BIT(7)</div><div class='add'>+#define PEF2256_SIC1_SSC_16384	  (BIT(7) |  BIT(3))</div><div class='add'>+/* SSD is defined on 2 bits. The other bit is on FMR1 register */</div><div class='add'>+#define PEF2256_SIC1_SSD_MASK	  GENMASK(6, 6)</div><div class='add'>+#define PEF2256_SIC1_SSD_2048	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)</div><div class='add'>+#define PEF2256_SIC1_SSD_4096	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)</div><div class='add'>+#define PEF2256_SIC1_SSD_8192	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)</div><div class='add'>+#define PEF2256_SIC1_SSD_16384	  FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)</div><div class='add'>+#define PEF2256_SIC1_RBS_MASK	  GENMASK(5, 4)</div><div class='add'>+#define PEF2256_SIC1_RBS_2FRAMES  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x0)</div><div class='add'>+#define PEF2256_SIC1_RBS_1FRAME	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x1)</div><div class='add'>+#define PEF2256_SIC1_RBS_96BITS	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x2)</div><div class='add'>+#define PEF2256_SIC1_RBS_BYPASS	  FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3)</div><div class='add'>+#define PEF2256_SIC1_XBS_MASK	  GENMASK(1, 0)</div><div class='add'>+#define PEF2256_SIC1_XBS_BYPASS	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x0)</div><div class='add'>+#define PEF2256_SIC1_XBS_1FRAME	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x1)</div><div class='add'>+#define PEF2256_SIC1_XBS_2FRAMES  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x2)</div><div class='add'>+#define PEF2256_SIC1_XBS_96BITS	  FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3)</div><div class='add'>+</div><div class='add'>+/* System Interface Control 2 */</div><div class='add'>+#define PEF2256_SIC2		0x3F</div><div class='add'>+#define PEF2256_SIC2_SICS_MASK	GENMASK(3, 1)</div><div class='add'>+#define PEF2256_SIC2_SICS(_v)	FIELD_PREP(PEF2256_SIC2_SICS_MASK, _v)</div><div class='add'>+</div><div class='add'>+/* System Interface Control 3 */</div><div class='add'>+#define PEF2256_SIC3		0x40</div><div class='add'>+#define PEF2256_SIC3_RTRI	BIT(5)</div><div class='add'>+#define PEF2256_SIC3_RESX	BIT(3)</div><div class='add'>+#define PEF2256_SIC3_RESR	BIT(2)</div><div class='add'>+</div><div class='add'>+/* Clock Mode Register 1 */</div><div class='add'>+#define PEF2256_CMR1			0x44</div><div class='add'>+#define PEF2256_CMR1_RS_MASK		GENMASK(5, 4)</div><div class='add'>+#define PEF2256_CMR1_RS_DPLL		FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x0)</div><div class='add'>+#define PEF2256_CMR1_RS_DPLL_LOS_HIGH	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x1)</div><div class='add'>+#define PEF2256_CMR1_RS_DCOR_2048	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x2)</div><div class='add'>+#define PEF2256_CMR1_RS_DCOR_8192	FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3)</div><div class='add'>+#define PEF2256_CMR1_DCS		BIT(3)</div><div class='add'>+</div><div class='add'>+/* Clock Mode Register 2 */</div><div class='add'>+#define PEF2256_CMR2		0x45</div><div class='add'>+#define PEF2256_CMR2_DCOXC	BIT(5)</div><div class='add'>+</div><div class='add'>+/* Global Configuration Register */</div><div class='add'>+#define PEF2256_GCR		0x46</div><div class='add'>+#define PEF2256_GCR_SCI		BIT(6)</div><div class='add'>+#define PEF2256_GCR_ECMC	BIT(4)</div><div class='add'>+</div><div class='add'>+/* Port Configuration 5 */</div><div class='add'>+#define PEF2256_PC5		0x84</div><div class='add'>+#define PEF2256_PC5_CRP         BIT(0)</div><div class='add'>+</div><div class='add'>+/* Global Port Configuration 1 */</div><div class='add'>+#define PEF2256_GPC1			0x85</div><div class='add'>+#define PEF2256_GPC1_CSFP_MASK		GENMASK(7, 5)</div><div class='add'>+#define PEF2256_GPC1_CSFP_SEC_IN_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x0)</div><div class='add'>+#define PEF2256_GPC1_CSFP_SEC_OUT_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x1)</div><div class='add'>+#define PEF2256_GPC1_CSFP_FSC_OUT_HIGH	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x2)</div><div class='add'>+#define PEF2256_GPC1_CSFP_FSC_OUT_LOW	FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3)</div><div class='add'>+</div><div class='add'>+/* Port Configuration 6 */</div><div class='add'>+#define PEF2256_PC6		0x86</div><div class='add'>+</div><div class='add'>+/* Global Counter Mode n=1..8 */</div><div class='add'>+#define PEF2256_GCM(_n)         (0x92 + (_n) - 1)</div><div class='add'>+#define PEF2256_GCM1	        0x92</div><div class='add'>+#define PEF2256_GCM2	        0x93</div><div class='add'>+#define PEF2256_GCM3	        0x94</div><div class='add'>+#define PEF2256_GCM4	        0x95</div><div class='add'>+#define PEF2256_GCM5	        0x96</div><div class='add'>+#define PEF2256_GCM6	        0x97</div><div class='add'>+#define PEF2256_GCM7	        0x98</div><div class='add'>+#define PEF2256_GCM8	        0x99</div><div class='add'>+</div><div class='add'>+/* Version Status Register */</div><div class='add'>+#define PEF2256_VSTR		 0x4A</div><div class='add'>+#define PEF2256_VSTR_VERSION_12	 0x00</div><div class='add'>+#define PEF2256_VSTR_VERSION_21	 0x10</div><div class='add'>+#define PEF2256_VSTR_VERSION_2x	 0x05</div><div class='add'>+</div><div class='add'>+/* Framer Receive Status 0 */</div><div class='add'>+#define PEF2256_FRS0		0x4C</div><div class='add'>+#define PEF2256_FRS0_LOS	BIT(7)</div><div class='add'>+#define PEF2256_FRS0_AIS	BIT(6)</div><div class='add'>+</div><div class='add'>+/* Interrupt Status Register 0..5 */</div><div class='add'>+#define PEF2256_ISR(_n)		(0x68 + (_n))</div><div class='add'>+#define PEF2256_ISR0		0x68</div><div class='add'>+#define PEF2256_ISR1		0x69</div><div class='add'>+#define PEF2256_ISR2		0x6A</div><div class='add'>+#define PEF2256_ISR3		0x6B</div><div class='add'>+#define PEF2256_ISR4		0x6C</div><div class='add'>+#define PEF2256_ISR5		0x6D</div><div class='add'>+</div><div class='add'>+/* Global Interrupt Status */</div><div class='add'>+#define PEF2256_GIS		0x6E</div><div class='add'>+#define PEF2256_GIS_ISR(_n)	BIT(_n)</div><div class='add'>+</div><div class='add'>+/* Wafer Identification Register */</div><div class='add'>+#define PEF2256_WID		   0xEC</div><div class='add'>+#define PEF2256_12_WID_MASK	   GENMASK(1, 0)</div><div class='add'>+#define PEF2256_12_WID_VERSION_12  FIELD_PREP_CONST(PEF2256_12_WID_MASK, 0x3)</div><div class='add'>+#define PEF2256_2X_WID_MASK	   GENMASK(7, 6)</div><div class='add'>+#define PEF2256_2X_WID_VERSION_21  FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x0)</div><div class='add'>+#define PEF2256_2X_WID_VERSION_22  FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x1)</div><div class='add'>+</div><div class='add'>+/* IMR2/ISR2 Interrupts common bits */</div><div class='add'>+#define PEF2256_INT2_AIS	BIT(3)</div><div class='add'>+#define PEF2256_INT2_LOS	BIT(2)</div><div class='add'>+</div><div class='add'>+#endif /* __PEF2256_REGS_H__ */</div><div class='head'>diff --git a/drivers/net/wan/framer/pef2256/pef2256.c b/drivers/net/wan/framer/pef2256/pef2256.c<br/>new file mode 100644<br/>index 000000000000..4f81053ee4f0<br/>--- /dev/null<br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/framer/pef2256/pef2256.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/framer/pef2256/pef2256.c</a></div><div class='hunk'>@@ -0,0 +1,880 @@</div><div class='add'>+// SPDX-License-Identifier: GPL-2.0</div><div class='add'>+/*</div><div class='add'>+ * PEF2256 also known as FALC56 driver</div><div class='add'>+ *</div><div class='add'>+ * Copyright 2023 CS GROUP France</div><div class='add'>+ *</div><div class='add'>+ * Author: Herve Codina &lt;herve.codina@bootlin.com&gt;</div><div class='add'>+ */</div><div class='add'>+</div><div class='add'>+#include &lt;linux/framer/pef2256.h&gt;</div><div class='add'>+#include &lt;linux/clk.h&gt;</div><div class='add'>+#include &lt;linux/framer/framer-provider.h&gt;</div><div class='add'>+#include &lt;linux/gpio/consumer.h&gt;</div><div class='add'>+#include &lt;linux/interrupt.h&gt;</div><div class='add'>+#include &lt;linux/io.h&gt;</div><div class='add'>+#include &lt;linux/mfd/core.h&gt;</div><div class='add'>+#include &lt;linux/module.h&gt;</div><div class='add'>+#include &lt;linux/notifier.h&gt;</div><div class='add'>+#include &lt;linux/of.h&gt;</div><div class='add'>+#include &lt;linux/of_platform.h&gt;</div><div class='add'>+#include &lt;linux/platform_device.h&gt;</div><div class='add'>+#include &lt;linux/regmap.h&gt;</div><div class='add'>+#include &lt;linux/slab.h&gt;</div><div class='add'>+#include "pef2256-regs.h"</div><div class='add'>+</div><div class='add'>+enum pef2256_frame_type {</div><div class='add'>+	PEF2256_FRAME_E1_DOUBLEFRAME,</div><div class='add'>+	PEF2256_FRAME_E1_CRC4_MULTIFRAME,</div><div class='add'>+	PEF2256_FRAME_E1_AUTO_MULTIFRAME,</div><div class='add'>+	PEF2256_FRAME_T1J1_4FRAME,</div><div class='add'>+	PEF2256_FRAME_T1J1_12FRAME,</div><div class='add'>+	PEF2256_FRAME_T1J1_24FRAME,</div><div class='add'>+	PEF2256_FRAME_T1J1_72FRAME,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct pef2256 {</div><div class='add'>+	struct device *dev;</div><div class='add'>+	struct regmap *regmap;</div><div class='add'>+	enum pef2256_version version;</div><div class='add'>+	struct clk *mclk;</div><div class='add'>+	struct clk *sclkr;</div><div class='add'>+	struct clk *sclkx;</div><div class='add'>+	struct gpio_desc *reset_gpio;</div><div class='add'>+	unsigned long sysclk_rate;</div><div class='add'>+	u32 data_rate;</div><div class='add'>+	bool is_tx_falling_edge;</div><div class='add'>+	bool is_subordinate;</div><div class='add'>+	enum pef2256_frame_type frame_type;</div><div class='add'>+	u8 channel_phase;</div><div class='add'>+	atomic_t carrier;</div><div class='add'>+	struct framer *framer;</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static u8 pef2256_read8(struct pef2256 *pef2256, int offset)</div><div class='add'>+{</div><div class='add'>+	int val;</div><div class='add'>+</div><div class='add'>+	regmap_read(pef2256-&gt;regmap, offset, &amp;val);</div><div class='add'>+	return val;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)</div><div class='add'>+{</div><div class='add'>+	regmap_write(pef2256-&gt;regmap, offset, val);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr)</div><div class='add'>+{</div><div class='add'>+	regmap_clear_bits(pef2256-&gt;regmap, offset, clr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set)</div><div class='add'>+{</div><div class='add'>+	regmap_set_bits(pef2256-&gt;regmap, offset, set);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set)</div><div class='add'>+{</div><div class='add'>+	regmap_update_bits(pef2256-&gt;regmap, offset, clr | set, set);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+enum pef2256_version pef2256_get_version(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	enum pef2256_version version = PEF2256_VERSION_UNKNOWN;</div><div class='add'>+	u8 vstr, wid;</div><div class='add'>+</div><div class='add'>+	vstr = pef2256_read8(pef2256, PEF2256_VSTR);</div><div class='add'>+	wid = pef2256_read8(pef2256, PEF2256_WID);</div><div class='add'>+</div><div class='add'>+	switch (vstr) {</div><div class='add'>+	case PEF2256_VSTR_VERSION_12:</div><div class='add'>+		if ((wid &amp; PEF2256_12_WID_MASK) == PEF2256_12_WID_VERSION_12)</div><div class='add'>+			version = PEF2256_VERSION_1_2;</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_VSTR_VERSION_2x:</div><div class='add'>+		switch (wid &amp; PEF2256_2X_WID_MASK) {</div><div class='add'>+		case PEF2256_2X_WID_VERSION_21:</div><div class='add'>+			version = PEF2256_VERSION_2_1;</div><div class='add'>+			break;</div><div class='add'>+		case PEF2256_2X_WID_VERSION_22:</div><div class='add'>+			version = PEF2256_VERSION_2_2;</div><div class='add'>+			break;</div><div class='add'>+		}</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_VSTR_VERSION_21:</div><div class='add'>+		version = PEF2256_VERSION_2_1;</div><div class='add'>+		break;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (version == PEF2256_VERSION_UNKNOWN)</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid);</div><div class='add'>+</div><div class='add'>+	return version;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(pef2256_get_version);</div><div class='add'>+</div><div class='add'>+enum pef2256_gcm_config_item {</div><div class='add'>+	PEF2256_GCM_CONFIG_1544000 = 0,</div><div class='add'>+	PEF2256_GCM_CONFIG_2048000,</div><div class='add'>+	PEF2256_GCM_CONFIG_8192000,</div><div class='add'>+	PEF2256_GCM_CONFIG_10000000,</div><div class='add'>+	PEF2256_GCM_CONFIG_12352000,</div><div class='add'>+	PEF2256_GCM_CONFIG_16384000,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+struct pef2256_gcm_config {</div><div class='add'>+	u8 gcm_12[6];</div><div class='add'>+	u8 gcm_2x[8];</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct pef2256_gcm_config pef2256_gcm_configs[] = {</div><div class='add'>+	[PEF2256_GCM_CONFIG_1544000] = {</div><div class='add'>+		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x00, 0x15},</div><div class='add'>+		.gcm_2x = {0x00, 0x15, 0x00, 0x08, 0x00, 0x3F, 0x9C, 0xDF},</div><div class='add'>+	},</div><div class='add'>+	[PEF2256_GCM_CONFIG_2048000] = {</div><div class='add'>+		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x00, 0x10},</div><div class='add'>+		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x2F, 0xDB, 0xDF},</div><div class='add'>+	},</div><div class='add'>+	[PEF2256_GCM_CONFIG_8192000] = {</div><div class='add'>+		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x03, 0x10},</div><div class='add'>+		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x0B, 0xDB, 0xDF},</div><div class='add'>+	},</div><div class='add'>+	[PEF2256_GCM_CONFIG_10000000] = {</div><div class='add'>+		.gcm_12 = {0x90, 0x51, 0x81, 0x8F, 0x04, 0x10},</div><div class='add'>+		.gcm_2x = {0x40, 0x1B, 0x3D, 0x0A, 0x00, 0x07, 0xC9, 0xDC},</div><div class='add'>+	},</div><div class='add'>+	[PEF2256_GCM_CONFIG_12352000] = {</div><div class='add'>+		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x07, 0x15},</div><div class='add'>+		.gcm_2x = {0x00, 0x19, 0x00, 0x08, 0x01, 0x0A, 0x98, 0xDA},</div><div class='add'>+	},</div><div class='add'>+	[PEF2256_GCM_CONFIG_16384000] = {</div><div class='add'>+		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x07, 0x10},</div><div class='add'>+		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x01, 0x0B, 0xDB, 0xDF},</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int pef2256_setup_gcm(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	enum pef2256_gcm_config_item item;</div><div class='add'>+	unsigned long mclk_rate;</div><div class='add'>+	const u8 *gcm;</div><div class='add'>+	int i, count;</div><div class='add'>+</div><div class='add'>+	mclk_rate = clk_get_rate(pef2256-&gt;mclk);</div><div class='add'>+	switch (mclk_rate) {</div><div class='add'>+	case 1544000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_1544000;</div><div class='add'>+		break;</div><div class='add'>+	case 2048000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_2048000;</div><div class='add'>+		break;</div><div class='add'>+	case 8192000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_8192000;</div><div class='add'>+		break;</div><div class='add'>+	case 10000000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_10000000;</div><div class='add'>+		break;</div><div class='add'>+	case 12352000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_12352000;</div><div class='add'>+		break;</div><div class='add'>+	case 16384000:</div><div class='add'>+		item = PEF2256_GCM_CONFIG_16384000;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	BUILD_BUG_ON(item &gt;= ARRAY_SIZE(pef2256_gcm_configs));</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;version == PEF2256_VERSION_1_2) {</div><div class='add'>+		gcm = pef2256_gcm_configs[item].gcm_12;</div><div class='add'>+		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_12);</div><div class='add'>+	} else {</div><div class='add'>+		gcm = pef2256_gcm_configs[item].gcm_2x;</div><div class='add'>+		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_2x);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++)</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_GCM(i + 1), *(gcm + i));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_setup_e1_line(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	u8 fmr1, fmr2;</div><div class='add'>+</div><div class='add'>+	/* RCLK output : DPLL clock, DCO-X enabled, DCO-X internal ref clock */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_CMR1, 0x00);</div><div class='add'>+</div><div class='add'>+	/* SCLKR selected, SCLKX selected,</div><div class='add'>+	 * receive synchro pulse sourced by SYPR,</div><div class='add'>+	 * transmit synchro pulse sourced by SYPX,</div><div class='add'>+	 * DCO-X center frequency enabled</div><div class='add'>+	 */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC);</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;is_subordinate) {</div><div class='add'>+		/* select RCLK source = 2M,  disable switching from RCLK to SYNC */</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK,</div><div class='add'>+				    PEF2256_CMR1_RS_DCOR_2048 | PEF2256_CMR1_DCS);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* slave mode, local loop off, mode short-haul</div><div class='add'>+	 * In v2.x, bit3 is a forced 1 bit in the datasheet -&gt; Need to be set.</div><div class='add'>+	 */</div><div class='add'>+	if (pef2256-&gt;version == PEF2256_VERSION_1_2)</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_LIM0, 0x00);</div><div class='add'>+	else</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3);</div><div class='add'>+</div><div class='add'>+	/* "master" mode */</div><div class='add'>+	if (!pef2256-&gt;is_subordinate)</div><div class='add'>+		pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS);</div><div class='add'>+</div><div class='add'>+	/* analog interface selected, remote loop off */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_LIM1, 0x00);</div><div class='add'>+</div><div class='add'>+	/* receive input threshold = 0,21V */</div><div class='add'>+	if (pef2256-&gt;version == PEF2256_VERSION_1_2)</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK,</div><div class='add'>+				    PEF2256_12_LIM1_RIL_210);</div><div class='add'>+	else</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK,</div><div class='add'>+				    PEF2256_2X_LIM1_RIL_210);</div><div class='add'>+</div><div class='add'>+	/* transmit pulse mask, default value from datasheet</div><div class='add'>+	 * transmit line in normal operation</div><div class='add'>+	 */</div><div class='add'>+	if (pef2256-&gt;version == PEF2256_VERSION_1_2)</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_XPM0, 0x7B);</div><div class='add'>+	else</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_XPM0, 0x9C);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XPM1, 0x03);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XPM2, 0x00);</div><div class='add'>+</div><div class='add'>+	/* HDB3 coding, no alarm simulation */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_HDB3 | PEF2256_FMR0_RC_HDB3);</div><div class='add'>+</div><div class='add'>+	/* E1, frame format, 2 Mbit/s system data rate, no AIS</div><div class='add'>+	 * transmission to remote end or system interface, payload loop</div><div class='add'>+	 * off, transmit remote alarm on</div><div class='add'>+	 */</div><div class='add'>+	fmr1 = 0x00;</div><div class='add'>+	fmr2 = PEF2256_FMR2_AXRA;</div><div class='add'>+	switch (pef2256-&gt;frame_type) {</div><div class='add'>+	case PEF2256_FRAME_E1_DOUBLEFRAME:</div><div class='add'>+		fmr2 |= PEF2256_FMR2_RFS_DOUBLEFRAME;</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_FRAME_E1_CRC4_MULTIFRAME:</div><div class='add'>+		fmr1 |= PEF2256_FMR1_XFS;</div><div class='add'>+		fmr2 |= PEF2256_FMR2_RFS_CRC4_MULTIFRAME;</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_FRAME_E1_AUTO_MULTIFRAME:</div><div class='add'>+		fmr1 |= PEF2256_FMR1_XFS;</div><div class='add'>+		fmr2 |= PEF2256_FMR2_RFS_AUTO_MULTIFRAME;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unsupported frame type %d\n", pef2256-&gt;frame_type);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_XFS, fmr1);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_FMR2, fmr2);</div><div class='add'>+</div><div class='add'>+	if (!pef2256-&gt;is_subordinate) {</div><div class='add'>+		/* SEC input, active high */</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH);</div><div class='add'>+	} else {</div><div class='add'>+		/* FSC output, active high */</div><div class='add'>+		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* SCLKR, SCLKX, RCLK configured to inputs,</div><div class='add'>+	 * XFMS active low, CLK1 and CLK2 pin configuration</div><div class='add'>+	 */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_PC5, 0x00);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_PC6, 0x00);</div><div class='add'>+</div><div class='add'>+	/* port RCLK is output */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_setup_e1_los(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	/* detection of LOS alarm = 176 pulses (ie (10 + 1) * 16) */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_PCD, 10);</div><div class='add'>+	/* recovery of LOS alarm = 22 pulses (ie 21 + 1) */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_PCR, 21);</div><div class='add'>+	/* E1 default for the receive slicer threshold */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50);</div><div class='add'>+	if (pef2256-&gt;is_subordinate) {</div><div class='add'>+		/* Loop-timed */</div><div class='add'>+		pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_setup_e1_system(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	u8 sic1, fmr1;</div><div class='add'>+</div><div class='add'>+	/* 2.048 MHz system clocking rate, receive buffer 2 frames, transmit</div><div class='add'>+	 * buffer bypass, data sampled and transmitted on the falling edge of</div><div class='add'>+	 * SCLKR/X, automatic freeze signaling, data is active in the first</div><div class='add'>+	 * channel phase</div><div class='add'>+	 */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_SIC1, 0x00);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_SIC2, 0x00);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_SIC3, 0x00);</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;is_subordinate) {</div><div class='add'>+		/* transmit buffer size = 2 frames, transparent mode */</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK,</div><div class='add'>+				    PEF2256_SIC1_XBS_2FRAMES);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;version != PEF2256_VERSION_1_2) {</div><div class='add'>+		/* during inactive channel phase switch RDO/RSIG into tri-state */</div><div class='add'>+		pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;is_tx_falling_edge) {</div><div class='add'>+		/* falling edge sync pulse transmit, rising edge sync pulse receive */</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESX, PEF2256_SIC3_RESR);</div><div class='add'>+	} else {</div><div class='add'>+		/* rising edge sync pulse transmit, falling edge sync pulse receive */</div><div class='add'>+		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESR, PEF2256_SIC3_RESX);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* transmit offset counter (XCO10..0) = 4 */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XC0, 0);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XC1, 4);</div><div class='add'>+	/* receive offset counter (RCO10..0) = 4 */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_RC0, 0);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_RC1, 4);</div><div class='add'>+</div><div class='add'>+	/* system clock rate */</div><div class='add'>+	switch (pef2256-&gt;sysclk_rate) {</div><div class='add'>+	case 2048000:</div><div class='add'>+		sic1 = PEF2256_SIC1_SSC_2048;</div><div class='add'>+		break;</div><div class='add'>+	case 4096000:</div><div class='add'>+		sic1 = PEF2256_SIC1_SSC_4096;</div><div class='add'>+		break;</div><div class='add'>+	case 8192000:</div><div class='add'>+		sic1 = PEF2256_SIC1_SSC_8192;</div><div class='add'>+		break;</div><div class='add'>+	case 16384000:</div><div class='add'>+		sic1 = PEF2256_SIC1_SSC_16384;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unsupported sysclk rate %lu\n", pef2256-&gt;sysclk_rate);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1);</div><div class='add'>+</div><div class='add'>+	/* data clock rate */</div><div class='add'>+	switch (pef2256-&gt;data_rate) {</div><div class='add'>+	case 2048000:</div><div class='add'>+		fmr1 = PEF2256_FMR1_SSD_2048;</div><div class='add'>+		sic1 = PEF2256_SIC1_SSD_2048;</div><div class='add'>+		break;</div><div class='add'>+	case 4096000:</div><div class='add'>+		fmr1 = PEF2256_FMR1_SSD_4096;</div><div class='add'>+		sic1 = PEF2256_SIC1_SSD_4096;</div><div class='add'>+		break;</div><div class='add'>+	case 8192000:</div><div class='add'>+		fmr1 = PEF2256_FMR1_SSD_8192;</div><div class='add'>+		sic1 = PEF2256_SIC1_SSD_8192;</div><div class='add'>+		break;</div><div class='add'>+	case 16384000:</div><div class='add'>+		fmr1 = PEF2256_FMR1_SSD_16384;</div><div class='add'>+		sic1 = PEF2256_SIC1_SSD_16384;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unsupported data rate %u\n", pef2256-&gt;data_rate);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1);</div><div class='add'>+	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1);</div><div class='add'>+</div><div class='add'>+	/* channel phase */</div><div class='add'>+	pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK,</div><div class='add'>+			    PEF2256_SIC2_SICS(pef2256-&gt;channel_phase));</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_setup_e1_signaling(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	/* All bits of the transmitted service word are cleared */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F));</div><div class='add'>+</div><div class='add'>+	/* CAS disabled and clear spare bit values */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_XSP, 0x00);</div><div class='add'>+</div><div class='add'>+	if (pef2256-&gt;is_subordinate) {</div><div class='add'>+		/* transparent mode */</div><div class='add'>+		pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Si-Bit, Spare bit For International, FAS word */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS);</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF);</div><div class='add'>+</div><div class='add'>+	/* no transparent mode active */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_TSWM, 0x00);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_setup_e1_errors(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	/* error counter latched every 1s */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM);</div><div class='add'>+</div><div class='add'>+	/* error counter mode COFA */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC);</div><div class='add'>+</div><div class='add'>+	/* errors in service words have no influence */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD);</div><div class='add'>+</div><div class='add'>+	/* 4 consecutive incorrect FAS causes loss of sync */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_setup_e1(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	/* Setup, Master clocking mode (GCM8..1) */</div><div class='add'>+	ret = pef2256_setup_gcm(pef2256);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Select E1 mode */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_FMR1, 0x00);</div><div class='add'>+</div><div class='add'>+	/* internal second timer, power on */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_GCR, 0x00);</div><div class='add'>+</div><div class='add'>+	/* Setup line interface */</div><div class='add'>+	ret = pef2256_setup_e1_line(pef2256);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Setup Loss-of-signal detection and recovery */</div><div class='add'>+	pef2256_setup_e1_los(pef2256);</div><div class='add'>+</div><div class='add'>+	/* Setup system interface */</div><div class='add'>+	ret = pef2256_setup_e1_system(pef2256);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Setup signaling */</div><div class='add'>+	pef2256_setup_e1_signaling(pef2256);</div><div class='add'>+</div><div class='add'>+	/* Setup errors counters and condition */</div><div class='add'>+	pef2256_setup_e1_errors(pef2256);</div><div class='add'>+</div><div class='add'>+	/* status changed interrupt at both up and down */</div><div class='add'>+	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI);</div><div class='add'>+</div><div class='add'>+	/* Clear any ISR2 pending interrupts and unmask needed interrupts */</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR2);</div><div class='add'>+	pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS);</div><div class='add'>+</div><div class='add'>+	/* reset lines */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)</div><div class='add'>+{</div><div class='add'>+	dev_warn_ratelimited(pef2256-&gt;dev, "ISR%u: 0x%02x not handled\n", nbr, isr);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static bool pef2256_is_carrier_on(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	u8 frs0;</div><div class='add'>+</div><div class='add'>+	frs0 = pef2256_read8(pef2256, PEF2256_FRS0);</div><div class='add'>+	return !(frs0 &amp; (PEF2256_FRS0_LOS | PEF2256_FRS0_AIS));</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)</div><div class='add'>+{</div><div class='add'>+	bool carrier;</div><div class='add'>+</div><div class='add'>+	if (isr &amp; (PEF2256_INT2_LOS | PEF2256_INT2_AIS)) {</div><div class='add'>+		carrier = pef2256_is_carrier_on(pef2256);</div><div class='add'>+		if (atomic_xchg(&amp;pef2256-&gt;carrier, carrier) != carrier)</div><div class='add'>+			framer_notify_status_change(pef2256-&gt;framer);</div><div class='add'>+	}</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static irqreturn_t pef2256_irq_handler(int irq, void *priv)</div><div class='add'>+{</div><div class='add'>+	static void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = {</div><div class='add'>+		[0] = pef2256_isr_default_handler,</div><div class='add'>+		[1] = pef2256_isr_default_handler,</div><div class='add'>+		[2] = pef2256_isr2_handler,</div><div class='add'>+		[3] = pef2256_isr_default_handler,</div><div class='add'>+		[4] = pef2256_isr_default_handler,</div><div class='add'>+		[5] = pef2256_isr_default_handler</div><div class='add'>+	};</div><div class='add'>+	struct pef2256 *pef2256 = (struct pef2256 *)priv;</div><div class='add'>+	u8 gis;</div><div class='add'>+	u8 isr;</div><div class='add'>+	u8 n;</div><div class='add'>+</div><div class='add'>+	gis = pef2256_read8(pef2256, PEF2256_GIS);</div><div class='add'>+</div><div class='add'>+	for (n = 0; n &lt; ARRAY_SIZE(pef2256_isr_handler); n++) {</div><div class='add'>+		if (gis &amp; PEF2256_GIS_ISR(n)) {</div><div class='add'>+			isr = pef2256_read8(pef2256, PEF2256_ISR(n));</div><div class='add'>+			pef2256_isr_handler[n](pef2256, n, isr);</div><div class='add'>+		}</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return IRQ_HANDLED;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate,</div><div class='add'>+			       unsigned long data_rate)</div><div class='add'>+{</div><div class='add'>+	unsigned long rate;</div><div class='add'>+</div><div class='add'>+	switch (sysclk_rate) {</div><div class='add'>+	case 2048000:</div><div class='add'>+	case 4096000:</div><div class='add'>+	case 8192000:</div><div class='add'>+	case 16384000:</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Unsupported system clock rate %lu\n", sysclk_rate);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	for (rate = data_rate; rate &lt;= data_rate * 4; rate *= 2) {</div><div class='add'>+		if (rate == sysclk_rate)</div><div class='add'>+			return 0;</div><div class='add'>+	}</div><div class='add'>+	dev_err(pef2256-&gt;dev, "Unsupported data rate %lu with system clock rate %lu\n",</div><div class='add'>+		data_rate, sysclk_rate);</div><div class='add'>+	return -EINVAL;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np)</div><div class='add'>+{</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;data_rate = 2048000;</div><div class='add'>+	ret = of_property_read_u32(np, "lantiq,data-rate-bps", &amp;pef2256-&gt;data_rate);</div><div class='add'>+	if (ret &amp;&amp; ret != -EINVAL) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "%pOF: failed to read lantiq,data-rate-bps\n", np);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret =  pef2256_check_rates(pef2256, pef2256-&gt;sysclk_rate, pef2256-&gt;data_rate);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge");</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;channel_phase = 0;</div><div class='add'>+	ret = of_property_read_u8(np, "lantiq,channel-phase", &amp;pef2256-&gt;channel_phase);</div><div class='add'>+	if (ret &amp;&amp; ret != -EINVAL) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "%pOF: failed to read lantiq,channel-phase\n",</div><div class='add'>+			np);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+	if (pef2256-&gt;channel_phase &gt;= pef2256-&gt;sysclk_rate / pef2256-&gt;data_rate) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "%pOF: Invalid lantiq,channel-phase %u\n",</div><div class='add'>+			np, pef2256-&gt;channel_phase);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct regmap_config pef2256_regmap_config = {</div><div class='add'>+	.reg_bits = 32,</div><div class='add'>+	.val_bits = 8,</div><div class='add'>+	.max_register = 0xff,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static const struct mfd_cell pef2256_devs[] = {</div><div class='add'>+	{ .name = "lantiq-pef2256-pinctrl", },</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int pef2256_add_audio_devices(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	const char *compatible = "lantiq,pef2256-codec";</div><div class='add'>+	struct mfd_cell *audio_devs;</div><div class='add'>+	struct device_node *np;</div><div class='add'>+	unsigned int count = 0;</div><div class='add'>+	unsigned int i;</div><div class='add'>+	int ret;</div><div class='add'>+</div><div class='add'>+	for_each_available_child_of_node(pef2256-&gt;dev-&gt;of_node, np) {</div><div class='add'>+		if (of_device_is_compatible(np, compatible))</div><div class='add'>+			count++;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	if (!count)</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	audio_devs = kcalloc(count, sizeof(*audio_devs), GFP_KERNEL);</div><div class='add'>+	if (!audio_devs)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	for (i = 0; i &lt; count; i++) {</div><div class='add'>+		audio_devs[i].name = "framer-codec";</div><div class='add'>+		audio_devs[i].of_compatible = compatible;</div><div class='add'>+		audio_devs[i].id = i;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = mfd_add_devices(pef2256-&gt;dev, 0, audio_devs, count, NULL, 0, NULL);</div><div class='add'>+	kfree(audio_devs);</div><div class='add'>+	return ret;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_framer_get_status(struct framer *framer, struct framer_status *status)</div><div class='add'>+{</div><div class='add'>+	struct pef2256 *pef2256 = framer_get_drvdata(framer);</div><div class='add'>+</div><div class='add'>+	status-&gt;link_is_on = !!atomic_read(&amp;pef2256-&gt;carrier);</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_framer_set_config(struct framer *framer, const struct framer_config *config)</div><div class='add'>+{</div><div class='add'>+	struct pef2256 *pef2256 = framer_get_drvdata(framer);</div><div class='add'>+</div><div class='add'>+	if (config-&gt;iface != FRAMER_IFACE_E1) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "Only E1 line is currently supported\n");</div><div class='add'>+		return -EOPNOTSUPP;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	switch (config-&gt;clock_type) {</div><div class='add'>+	case FRAMER_CLOCK_EXT:</div><div class='add'>+		pef2256-&gt;is_subordinate = true;</div><div class='add'>+		break;</div><div class='add'>+	case FRAMER_CLOCK_INT:</div><div class='add'>+		pef2256-&gt;is_subordinate = false;</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	/* Apply the new settings */</div><div class='add'>+	return pef2256_setup_e1(pef2256);</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_framer_get_config(struct framer *framer, struct framer_config *config)</div><div class='add'>+{</div><div class='add'>+	struct pef2256 *pef2256 = framer_get_drvdata(framer);</div><div class='add'>+</div><div class='add'>+	config-&gt;iface = FRAMER_IFACE_E1;</div><div class='add'>+	config-&gt;clock_type = pef2256-&gt;is_subordinate ? FRAMER_CLOCK_EXT : FRAMER_CLOCK_INT;</div><div class='add'>+	config-&gt;line_clock_rate = 2048000;</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct framer_ops pef2256_framer_ops = {</div><div class='add'>+	.owner = THIS_MODULE,</div><div class='add'>+	.get_status = pef2256_framer_get_status,</div><div class='add'>+	.get_config = pef2256_framer_get_config,</div><div class='add'>+	.set_config = pef2256_framer_set_config,</div><div class='add'>+};</div><div class='add'>+</div><div class='add'>+static int pef2256_probe(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct device_node *np = pdev-&gt;dev.of_node;</div><div class='add'>+	unsigned long sclkr_rate, sclkx_rate;</div><div class='add'>+	struct framer_provider *framer_provider;</div><div class='add'>+	struct pef2256 *pef2256;</div><div class='add'>+	const char *version_txt;</div><div class='add'>+	void __iomem *iomem;</div><div class='add'>+	int ret;</div><div class='add'>+	int irq;</div><div class='add'>+</div><div class='add'>+	pef2256 = devm_kzalloc(&amp;pdev-&gt;dev, sizeof(*pef2256), GFP_KERNEL);</div><div class='add'>+	if (!pef2256)</div><div class='add'>+		return -ENOMEM;</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;dev = &amp;pdev-&gt;dev;</div><div class='add'>+	atomic_set(&amp;pef2256-&gt;carrier, 0);</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;is_subordinate = true;</div><div class='add'>+	pef2256-&gt;frame_type = PEF2256_FRAME_E1_DOUBLEFRAME;</div><div class='add'>+</div><div class='add'>+	iomem = devm_platform_ioremap_resource(pdev, 0);</div><div class='add'>+	if (IS_ERR(iomem))</div><div class='add'>+		return PTR_ERR(iomem);</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;regmap = devm_regmap_init_mmio(&amp;pdev-&gt;dev, iomem,</div><div class='add'>+						&amp;pef2256_regmap_config);</div><div class='add'>+	if (IS_ERR(pef2256-&gt;regmap)) {</div><div class='add'>+		dev_err(&amp;pdev-&gt;dev, "Failed to initialise Regmap (%ld)\n",</div><div class='add'>+			PTR_ERR(pef2256-&gt;regmap));</div><div class='add'>+		return PTR_ERR(pef2256-&gt;regmap);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;mclk = devm_clk_get_enabled(&amp;pdev-&gt;dev, "mclk");</div><div class='add'>+	if (IS_ERR(pef2256-&gt;mclk))</div><div class='add'>+		return PTR_ERR(pef2256-&gt;mclk);</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;sclkr = devm_clk_get_enabled(&amp;pdev-&gt;dev, "sclkr");</div><div class='add'>+	if (IS_ERR(pef2256-&gt;sclkr))</div><div class='add'>+		return PTR_ERR(pef2256-&gt;sclkr);</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;sclkx = devm_clk_get_enabled(&amp;pdev-&gt;dev, "sclkx");</div><div class='add'>+	if (IS_ERR(pef2256-&gt;sclkx))</div><div class='add'>+		return PTR_ERR(pef2256-&gt;sclkx);</div><div class='add'>+</div><div class='add'>+	/* Both SCLKR (receive) and SCLKX (transmit) must have the same rate,</div><div class='add'>+	 * stored as sysclk_rate.</div><div class='add'>+	 * The exact value will be checked at pef2256_check_rates()</div><div class='add'>+	 */</div><div class='add'>+	sclkr_rate = clk_get_rate(pef2256-&gt;sclkr);</div><div class='add'>+	sclkx_rate = clk_get_rate(pef2256-&gt;sclkx);</div><div class='add'>+	if (sclkr_rate != sclkx_rate) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "clk rate mismatch. sclkr %lu Hz, sclkx %lu Hz\n",</div><div class='add'>+			sclkr_rate, sclkx_rate);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+	pef2256-&gt;sysclk_rate = sclkr_rate;</div><div class='add'>+</div><div class='add'>+	/* Reset the component. The MCLK clock must be active during reset */</div><div class='add'>+	pef2256-&gt;reset_gpio = devm_gpiod_get_optional(&amp;pdev-&gt;dev, "reset", GPIOD_OUT_LOW);</div><div class='add'>+	if (IS_ERR(pef2256-&gt;reset_gpio))</div><div class='add'>+		return PTR_ERR(pef2256-&gt;reset_gpio);</div><div class='add'>+	if (pef2256-&gt;reset_gpio) {</div><div class='add'>+		gpiod_set_value_cansleep(pef2256-&gt;reset_gpio, 1);</div><div class='add'>+		usleep_range(10, 20);</div><div class='add'>+		gpiod_set_value_cansleep(pef2256-&gt;reset_gpio, 0);</div><div class='add'>+		usleep_range(10, 20);</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	pef2256-&gt;version = pef2256_get_version(pef2256);</div><div class='add'>+	switch (pef2256-&gt;version) {</div><div class='add'>+	case PEF2256_VERSION_1_2:</div><div class='add'>+		version_txt = "1.2";</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_VERSION_2_1:</div><div class='add'>+		version_txt = "2.1";</div><div class='add'>+		break;</div><div class='add'>+	case PEF2256_VERSION_2_2:</div><div class='add'>+		version_txt = "2.2";</div><div class='add'>+		break;</div><div class='add'>+	default:</div><div class='add'>+		return -ENODEV;</div><div class='add'>+	}</div><div class='add'>+	dev_info(pef2256-&gt;dev, "Version %s detected\n", version_txt);</div><div class='add'>+</div><div class='add'>+	ret = pef2556_of_parse(pef2256, np);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	/* Create the framer. It can be used on interrupts */</div><div class='add'>+	pef2256-&gt;framer = devm_framer_create(pef2256-&gt;dev, NULL, &amp;pef2256_framer_ops);</div><div class='add'>+	if (IS_ERR(pef2256-&gt;framer))</div><div class='add'>+		return PTR_ERR(pef2256-&gt;framer);</div><div class='add'>+</div><div class='add'>+	framer_set_drvdata(pef2256-&gt;framer, pef2256);</div><div class='add'>+</div><div class='add'>+	/* Disable interrupts */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);</div><div class='add'>+</div><div class='add'>+	/* Clear any pending interrupts */</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR0);</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR1);</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR2);</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR3);</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR4);</div><div class='add'>+	pef2256_read8(pef2256, PEF2256_ISR5);</div><div class='add'>+</div><div class='add'>+	irq = platform_get_irq(pdev, 0);</div><div class='add'>+	if (irq &lt; 0)</div><div class='add'>+		return irq;</div><div class='add'>+	ret = devm_request_irq(pef2256-&gt;dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256);</div><div class='add'>+	if (ret &lt; 0)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	platform_set_drvdata(pdev, pef2256);</div><div class='add'>+</div><div class='add'>+	ret = mfd_add_devices(pef2256-&gt;dev, 0, pef2256_devs,</div><div class='add'>+			      ARRAY_SIZE(pef2256_devs), NULL, 0, NULL);</div><div class='add'>+	if (ret) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "add devices failed (%d)\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ret = pef2256_setup_e1(pef2256);</div><div class='add'>+	if (ret)</div><div class='add'>+		return ret;</div><div class='add'>+</div><div class='add'>+	framer_provider = devm_framer_provider_of_register(pef2256-&gt;dev,</div><div class='add'>+							   framer_provider_simple_of_xlate);</div><div class='add'>+	if (IS_ERR(framer_provider))</div><div class='add'>+		return PTR_ERR(framer_provider);</div><div class='add'>+</div><div class='add'>+	/* Add audio devices */</div><div class='add'>+	ret = pef2256_add_audio_devices(pef2256);</div><div class='add'>+	if (ret &lt; 0) {</div><div class='add'>+		dev_err(pef2256-&gt;dev, "add audio devices failed (%d)\n", ret);</div><div class='add'>+		return ret;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static int pef2256_remove(struct platform_device *pdev)</div><div class='add'>+{</div><div class='add'>+	struct pef2256 *pef2256 = platform_get_drvdata(pdev);</div><div class='add'>+</div><div class='add'>+	/* Disable interrupts */</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);</div><div class='add'>+	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='add'>+static const struct of_device_id pef2256_id_table[] = {</div><div class='add'>+	{ .compatible = "lantiq,pef2256" },</div><div class='add'>+	{} /* sentinel */</div><div class='add'>+};</div><div class='add'>+MODULE_DEVICE_TABLE(of, pef2256_id_table);</div><div class='add'>+</div><div class='add'>+static struct platform_driver pef2256_driver = {</div><div class='add'>+	.driver = {</div><div class='add'>+		.name = "lantiq-pef2256",</div><div class='add'>+		.of_match_table = pef2256_id_table,</div><div class='add'>+	},</div><div class='add'>+	.probe = pef2256_probe,</div><div class='add'>+	.remove = pef2256_remove,</div><div class='add'>+};</div><div class='add'>+module_platform_driver(pef2256_driver);</div><div class='add'>+</div><div class='add'>+struct regmap *pef2256_get_regmap(struct pef2256 *pef2256)</div><div class='add'>+{</div><div class='add'>+	return pef2256-&gt;regmap;</div><div class='add'>+}</div><div class='add'>+EXPORT_SYMBOL_GPL(pef2256_get_regmap);</div><div class='add'>+</div><div class='add'>+MODULE_AUTHOR("Herve Codina &lt;herve.codina@bootlin.com&gt;");</div><div class='add'>+MODULE_DESCRIPTION("PEF2256 driver");</div><div class='add'>+MODULE_LICENSE("GPL");</div><div class='head'>diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c<br/>index fd50bb313b92..605e70f7baac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wan/fsl_ucc_hdlc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wan/fsl_ucc_hdlc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/fsl_ucc_hdlc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/fsl_ucc_hdlc.c</a></div><div class='hunk'>@@ -1259,7 +1259,7 @@ free_uhdlc_priv:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ucc_hdlc_remove(struct platform_device *pdev)</div><div class='add'>+static void ucc_hdlc_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ucc_hdlc_private *priv = dev_get_drvdata(&amp;pdev-&gt;dev);</div><div class='ctx'> </div><div class='hunk'>@@ -1277,8 +1277,6 @@ static int ucc_hdlc_remove(struct platform_device *pdev)</div><div class='ctx'> 	kfree(priv);</div><div class='ctx'> </div><div class='ctx'> 	dev_info(&amp;pdev-&gt;dev, "UCC based hdlc module removed\n");</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id fsl_ucc_hdlc_of_match[] = {</div><div class='hunk'>@@ -1292,7 +1290,7 @@ MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ucc_hdlc_driver = {</div><div class='ctx'> 	.probe	= ucc_hdlc_probe,</div><div class='del'>-	.remove	= ucc_hdlc_remove,</div><div class='add'>+	.remove_new = ucc_hdlc_remove,</div><div class='ctx'> 	.driver	= {</div><div class='ctx'> 		.name		= DRV_NAME,</div><div class='ctx'> 		.pm		= HDLC_PM_OPS,</div><div class='head'>diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c<br/>index b09f4c235142..931c5ca79ea5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wan/ixp4xx_hss.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wan/ixp4xx_hss.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/ixp4xx_hss.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/ixp4xx_hss.c</a></div><div class='hunk'>@@ -1522,20 +1522,19 @@ err_plat:</div><div class='ctx'> 	return err;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ixp4xx_hss_remove(struct platform_device *pdev)</div><div class='add'>+static void ixp4xx_hss_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct port *port = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='ctx'> 	unregister_hdlc_device(port-&gt;netdev);</div><div class='ctx'> 	free_netdev(port-&gt;netdev);</div><div class='ctx'> 	npe_release(port-&gt;npe);</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ixp4xx_hss_driver = {</div><div class='ctx'> 	.driver.name	= DRV_NAME,</div><div class='ctx'> 	.probe		= ixp4xx_hss_probe,</div><div class='del'>-	.remove		= ixp4xx_hss_remove,</div><div class='add'>+	.remove_new	= ixp4xx_hss_remove,</div><div class='ctx'> };</div><div class='ctx'> module_platform_driver(ixp4xx_hss_driver);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wan/slic_ds26522.c b/drivers/net/wan/slic_ds26522.c<br/>index 8a51cfcff99e..cbb99fc5ea9f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wan/slic_ds26522.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wan/slic_ds26522.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wan/slic_ds26522.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wan/slic_ds26522.c</a></div><div class='hunk'>@@ -28,6 +28,7 @@</div><div class='ctx'> </div><div class='ctx'> static struct spi_device *g_spi;</div><div class='ctx'> </div><div class='add'>+MODULE_DESCRIPTION("Slic Maxim DS26522 driver");</div><div class='ctx'> MODULE_LICENSE("GPL");</div><div class='ctx'> MODULE_AUTHOR("Zhao Qiang&lt;B45475@freescale.com&gt;");</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig<br/>index 7555af5195ec..c6599594dc99 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/Kconfig</a></div><div class='hunk'>@@ -22,7 +22,6 @@ source "drivers/net/wireless/admtek/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/ath/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/atmel/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/broadcom/Kconfig"</div><div class='del'>-source "drivers/net/wireless/cisco/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/intel/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/intersil/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/marvell/Kconfig"</div><div class='hunk'>@@ -38,8 +37,6 @@ source "drivers/net/wireless/ti/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/zydas/Kconfig"</div><div class='ctx'> source "drivers/net/wireless/quantenna/Kconfig"</div><div class='ctx'> </div><div class='del'>-source "drivers/net/wireless/legacy/Kconfig"</div><div class='del'>-</div><div class='ctx'> source "drivers/net/wireless/virtual/Kconfig"</div><div class='ctx'> </div><div class='ctx'> endif # WLAN</div><div class='head'>diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile<br/>index 4d7374d567d1..e1c4141c6004 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/Makefile</a></div><div class='hunk'>@@ -7,7 +7,6 @@ obj-$(CONFIG_WLAN_VENDOR_ADMTEK) += admtek/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_ATH) += ath/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_ATMEL) += atmel/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_BROADCOM) += broadcom/</div><div class='del'>-obj-$(CONFIG_WLAN_VENDOR_CISCO) += cisco/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_INTEL) += intel/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_INTERSIL) += intersil/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_MARVELL) += marvell/</div><div class='hunk'>@@ -23,5 +22,4 @@ obj-$(CONFIG_WLAN_VENDOR_ST) += st/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_TI) += ti/</div><div class='ctx'> obj-$(CONFIG_WLAN_VENDOR_ZYDAS) += zydas/</div><div class='ctx'> </div><div class='del'>-obj-$(CONFIG_WLAN) += legacy/</div><div class='ctx'> obj-$(CONFIG_WLAN) += virtual/</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/bmi.c b/drivers/net/wireless/ath/ath10k/bmi.c<br/>index af6546572df2..9a4f8e815412 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/bmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/bmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/bmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/bmi.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2014,2016-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "bmi.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/ce.c b/drivers/net/wireless/ath/ath10k/ce.c<br/>index c27b8204718a..afae4a8027f8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/ce.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/ce.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/ce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/ce.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "hif.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c<br/>index 6cdb225b7eac..0032f8aa892f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/core.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -100,6 +101,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA988X_HW_2_0_VERSION,</div><div class='hunk'>@@ -140,6 +142,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9887_HW_1_0_VERSION,</div><div class='hunk'>@@ -181,6 +184,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA6174_HW_3_2_VERSION,</div><div class='hunk'>@@ -217,6 +221,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA6174_HW_2_1_VERSION,</div><div class='hunk'>@@ -257,6 +262,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA6174_HW_2_1_VERSION,</div><div class='hunk'>@@ -297,6 +303,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA6174_HW_3_0_VERSION,</div><div class='hunk'>@@ -337,6 +344,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA6174_HW_3_2_VERSION,</div><div class='hunk'>@@ -381,6 +389,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = true,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA99X0_HW_2_0_DEV_VERSION,</div><div class='hunk'>@@ -427,6 +436,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9984_HW_1_0_DEV_VERSION,</div><div class='hunk'>@@ -480,6 +490,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9888_HW_2_0_DEV_VERSION,</div><div class='hunk'>@@ -530,6 +541,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9377_HW_1_0_DEV_VERSION,</div><div class='hunk'>@@ -570,6 +582,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9377_HW_1_1_DEV_VERSION,</div><div class='hunk'>@@ -612,6 +625,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA9377_HW_1_1_DEV_VERSION,</div><div class='hunk'>@@ -645,6 +659,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = QCA4019_HW_1_0_DEV_VERSION,</div><div class='hunk'>@@ -692,6 +707,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = false,</div><div class='ctx'> 		.use_fw_tx_credits = true,</div><div class='ctx'> 		.delay_unmap_buffer = false,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> 	{</div><div class='ctx'> 		.id = WCN3990_HW_1_0_DEV_VERSION,</div><div class='hunk'>@@ -725,6 +741,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {</div><div class='ctx'> 		.hw_restart_disconnect = true,</div><div class='ctx'> 		.use_fw_tx_credits = false,</div><div class='ctx'> 		.delay_unmap_buffer = true,</div><div class='add'>+		.mcast_frame_registration = false,</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h<br/>index 4b5239de4018..c110d15528bd 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/core.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _CORE_H_</div><div class='hunk'>@@ -607,7 +608,7 @@ struct ath10k_vif {</div><div class='ctx'> 			u8 tim_bitmap[64];</div><div class='ctx'> 			u8 tim_len;</div><div class='ctx'> 			u32 ssid_len;</div><div class='del'>-			u8 ssid[IEEE80211_MAX_SSID_LEN];</div><div class='add'>+			u8 ssid[IEEE80211_MAX_SSID_LEN] __nonstring;</div><div class='ctx'> 			bool hidden_ssid;</div><div class='ctx'> 			/* P2P_IE with NoA attribute for P2P_GO case */</div><div class='ctx'> 			u32 noa_len;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/coredump.c b/drivers/net/wireless/ath/ath10k/coredump.c<br/>index 2d1634a890dd..bb3a276b7ed5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/coredump.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/coredump.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/coredump.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/coredump.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "coredump.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/coredump.h b/drivers/net/wireless/ath/ath10k/coredump.h<br/>index 437b9759f05d..e5ef0352e319 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/coredump.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/coredump.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/coredump.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/coredump.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: ISC */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _COREDUMP_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/debug.c b/drivers/net/wireless/ath/ath10k/debug.c<br/>index ad9cf953a2fc..b93a64bf8190 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/debug.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/debugfs_sta.c b/drivers/net/wireless/ath/ath10k/debugfs_sta.c<br/>index 87a3365330ff..394bf3c32abf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/debugfs_sta.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/debugfs_sta.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/debugfs_sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/debugfs_sta.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/htc.c b/drivers/net/wireless/ath/ath10k/htc.c<br/>index 5bfeecb95fca..a6e21ce90bad 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/htc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htc.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/htc.h b/drivers/net/wireless/ath/ath10k/htc.h<br/>index 0d180faf3b77..7ff665020015 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/htc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htc.h</a></div><div class='hunk'>@@ -246,26 +246,12 @@ struct ath10k_htc_lookahead_bundle {</div><div class='ctx'> struct ath10k_htc_record {</div><div class='ctx'> 	struct ath10k_ath10k_htc_record_hdr hdr;</div><div class='ctx'> 	union {</div><div class='del'>-		struct ath10k_htc_credit_report credit_report[0];</div><div class='del'>-		struct ath10k_htc_lookahead_report lookahead_report[0];</div><div class='del'>-		struct ath10k_htc_lookahead_bundle lookahead_bundle[0];</div><div class='del'>-		u8 pauload[0];</div><div class='add'>+		DECLARE_FLEX_ARRAY(struct ath10k_htc_credit_report, credit_report);</div><div class='add'>+		DECLARE_FLEX_ARRAY(struct ath10k_htc_lookahead_report, lookahead_report);</div><div class='add'>+		DECLARE_FLEX_ARRAY(struct ath10k_htc_lookahead_bundle, lookahead_bundle);</div><div class='ctx'> 	};</div><div class='ctx'> } __packed __aligned(4);</div><div class='ctx'> </div><div class='del'>-/*</div><div class='del'>- * note: the trailer offset is dynamic depending</div><div class='del'>- * on payload length. this is only a struct layout draft</div><div class='del'>- */</div><div class='del'>-struct ath10k_htc_frame {</div><div class='del'>-	struct ath10k_htc_hdr hdr;</div><div class='del'>-	union {</div><div class='del'>-		struct ath10k_htc_msg msg;</div><div class='del'>-		u8 payload[0];</div><div class='del'>-	};</div><div class='del'>-	struct ath10k_htc_record trailer[0];</div><div class='del'>-} __packed __aligned(4);</div><div class='del'>-</div><div class='ctx'> /*******************/</div><div class='ctx'> /* Host-side stuff */</div><div class='ctx'> /*******************/</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/htt.h b/drivers/net/wireless/ath/ath10k/htt.h<br/>index c80470e8886a..4a9270e2a4c8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/htt.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _HTT_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c<br/>index b261d6371c0f..7d28ae5453cf 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/htt_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt_rx.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='hunk'>@@ -1294,7 +1295,7 @@ static void ath10k_htt_rx_h_ppdu(struct ath10k *ar,</div><div class='ctx'> 		status-&gt;encoding = RX_ENC_LEGACY;</div><div class='ctx'> 		status-&gt;bw = RATE_INFO_BW_20;</div><div class='ctx'> </div><div class='del'>-		status-&gt;flag &amp;= ~RX_FLAG_MACTIME_END;</div><div class='add'>+		status-&gt;flag &amp;= ~RX_FLAG_MACTIME;</div><div class='ctx'> 		status-&gt;flag |= RX_FLAG_NO_SIGNAL_VAL;</div><div class='ctx'> </div><div class='ctx'> 		status-&gt;flag &amp;= ~(RX_FLAG_AMPDU_IS_LAST);</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/htt_tx.c b/drivers/net/wireless/ath/ath10k/htt_tx.c<br/>index be4d4536aaa8..9725feecefd6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/htt_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/htt_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/htt_tx.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/etherdevice.h&gt;</div><div class='hunk'>@@ -40,7 +41,6 @@ static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,</div><div class='ctx'> 	struct ath10k *ar = hw-&gt;priv;</div><div class='ctx'> 	struct ath10k_sta *arsta;</div><div class='ctx'> 	struct ath10k_vif *arvif = (void *)txq-&gt;vif-&gt;drv_priv;</div><div class='del'>-	unsigned long frame_cnt;</div><div class='ctx'> 	unsigned long byte_cnt;</div><div class='ctx'> 	int idx;</div><div class='ctx'> 	u32 bit;</div><div class='hunk'>@@ -67,7 +67,7 @@ static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,</div><div class='ctx'> 	bit = BIT(peer_id % 32);</div><div class='ctx'> 	idx = peer_id / 32;</div><div class='ctx'> </div><div class='del'>-	ieee80211_txq_get_depth(txq, &amp;frame_cnt, &amp;byte_cnt);</div><div class='add'>+	ieee80211_txq_get_depth(txq, NULL, &amp;byte_cnt);</div><div class='ctx'> 	count = ath10k_htt_tx_txq_calc_size(byte_cnt);</div><div class='ctx'> </div><div class='ctx'> 	if (unlikely(peer_id &gt;= ar-&gt;htt.tx_q_state.num_peers) ||</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/hw.c b/drivers/net/wireless/ath/ath10k/hw.c<br/>index 6d32b43a4da6..8fafe096adff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/hw.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: ISC</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h<br/>index 9643031a4427..93c073091996 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/hw.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _HW_H_</div><div class='hunk'>@@ -639,6 +640,9 @@ struct ath10k_hw_params {</div><div class='ctx'> 	bool use_fw_tx_credits;</div><div class='ctx'> </div><div class='ctx'> 	bool delay_unmap_buffer;</div><div class='add'>+</div><div class='add'>+	/* The hardware support multicast frame registrations */</div><div class='add'>+	bool mcast_frame_registration;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct htt_resp;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/mac.c b/drivers/net/wireless/ath/ath10k/mac.c<br/>index 2cf693f3fea9..090bcf148d0c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/mac.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "mac.h"</div><div class='hunk'>@@ -1242,7 +1243,7 @@ static bool ath10k_mac_monitor_vdev_is_needed(struct ath10k *ar)</div><div class='ctx'> 	return ar-&gt;monitor ||</div><div class='ctx'> 	       (!test_bit(ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST,</div><div class='ctx'> 			  ar-&gt;running_fw-&gt;fw_file.fw_features) &amp;&amp;</div><div class='del'>-		(ar-&gt;filter_flags &amp; FIF_OTHER_BSS)) ||</div><div class='add'>+		(ar-&gt;filter_flags &amp; (FIF_OTHER_BSS | FIF_MCAST_ACTION))) ||</div><div class='ctx'> 	       test_bit(ATH10K_CAC_RUNNING, &amp;ar-&gt;dev_flags);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -6025,10 +6026,15 @@ static void ath10k_configure_filter(struct ieee80211_hw *hw,</div><div class='ctx'> {</div><div class='ctx'> 	struct ath10k *ar = hw-&gt;priv;</div><div class='ctx'> 	int ret;</div><div class='add'>+	unsigned int supported = SUPPORTED_FILTERS;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;ar-&gt;conf_mutex);</div><div class='ctx'> </div><div class='del'>-	*total_flags &amp;= SUPPORTED_FILTERS;</div><div class='add'>+	if (ar-&gt;hw_params.mcast_frame_registration)</div><div class='add'>+		supported |= FIF_MCAST_ACTION;</div><div class='add'>+</div><div class='add'>+	*total_flags &amp;= supported;</div><div class='add'>+</div><div class='ctx'> 	ar-&gt;filter_flags = *total_flags;</div><div class='ctx'> </div><div class='ctx'> 	ret = ath10k_monitor_recalc(ar);</div><div class='hunk'>@@ -6121,9 +6127,8 @@ static void ath10k_bss_info_changed(struct ieee80211_hw *hw,</div><div class='ctx'> </div><div class='ctx'> 		if (ieee80211_vif_is_mesh(vif)) {</div><div class='ctx'> 			/* mesh doesn't use SSID but firmware needs it */</div><div class='del'>-			strncpy(arvif-&gt;u.ap.ssid, "mesh",</div><div class='del'>-				sizeof(arvif-&gt;u.ap.ssid));</div><div class='ctx'> 			arvif-&gt;u.ap.ssid_len = 4;</div><div class='add'>+			memcpy(arvif-&gt;u.ap.ssid, "mesh", arvif-&gt;u.ap.ssid_len);</div><div class='ctx'> 		}</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='hunk'>@@ -10118,6 +10123,10 @@ int ath10k_mac_register(struct ath10k *ar)</div><div class='ctx'> 			      NL80211_EXT_FEATURE_SET_SCAN_DWELL);</div><div class='ctx'> 	wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy, NL80211_EXT_FEATURE_AQL);</div><div class='ctx'> </div><div class='add'>+	if (ar-&gt;hw_params.mcast_frame_registration)</div><div class='add'>+		wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy,</div><div class='add'>+				      NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);</div><div class='add'>+</div><div class='ctx'> 	if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI, ar-&gt;wmi.svc_map) ||</div><div class='ctx'> 	    test_bit(WMI_SERVICE_HTT_MGMT_TX_COMP_VALID_FLAGS, ar-&gt;wmi.svc_map))</div><div class='ctx'> 		wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c<br/>index 2f8c785277af..3de2de6d44bc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/pci.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/pci.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h<br/>index 480cd97ab739..27bb4cf2dfea 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/pci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/pci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/pci.h</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _PCI_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c<br/>index 52c1a3de8da6..38e939f572a9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/qmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: ISC</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/completion.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c b/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c<br/>index 1c81e454f943..0e85c75d2278 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: ISC</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/soc/qcom/qmi.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h b/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h<br/>index f0db991408dc..9f311f3bc9e7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: ISC */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef WCN3990_QMI_SVC_V01_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/rx_desc.h b/drivers/net/wireless/ath/ath10k/rx_desc.h<br/>index 777e53aa69dc..564293df1e9a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/rx_desc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/rx_desc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/rx_desc.h</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _RX_DESC_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/sdio.c b/drivers/net/wireless/ath/ath10k/sdio.c<br/>index 56fbcfb80bf8..0ab5433f6cf6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/sdio.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/sdio.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/sdio.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/sdio.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2004-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2016-2017 Erik Stromdahl &lt;erik.stromdahl@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/thermal.c b/drivers/net/wireless/ath/ath10k/thermal.c<br/>index cefd97323dfe..31c8d7fbb095 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/thermal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/thermal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/thermal.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: ISC</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/usb.h b/drivers/net/wireless/ath/ath10k/usb.h<br/>index 48e066ba8162..7e4cfbb673c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/usb.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/usb.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/usb.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/usb.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2004-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2016-2017 Erik Stromdahl &lt;erik.stromdahl@gmail.com&gt;</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _USB_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/wmi-tlv.h b/drivers/net/wireless/ath/ath10k/wmi-tlv.h<br/>index dbb48d70f2e9..83a8f07a687f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi-tlv.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/wmi-tlv.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi-tlv.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi-tlv.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef _WMI_TLV_H</div><div class='ctx'> #define _WMI_TLV_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/wmi.c b/drivers/net/wireless/ath/ath10k/wmi.c<br/>index 05fa7d4c0e1a..88befe92f95d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/wmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi.c</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/skbuff.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/wmi.h b/drivers/net/wireless/ath/ath10k/wmi.h<br/>index b112e8826093..9146df98fcee 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/wmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wmi.h</a></div><div class='hunk'>@@ -3,6 +3,7 @@</div><div class='ctx'>  * Copyright (c) 2005-2011 Atheros Communications Inc.</div><div class='ctx'>  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _WMI_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath10k/wow.c b/drivers/net/wireless/ath/ath10k/wow.c<br/>index 20b9aa8ddf7d..aa7b2e703f3d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wow.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath10k/wow.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath10k/wow.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath10k/wow.c</a></div><div class='hunk'>@@ -2,6 +2,7 @@</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2015-2017 Qualcomm Atheros, Inc.</div><div class='ctx'>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "mac.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/Kconfig b/drivers/net/wireless/ath/ath11k/Kconfig<br/>index ad5cc6cac05b..27f0523bf967 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/Kconfig</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> config ATH11K</div><div class='ctx'> 	tristate "Qualcomm Technologies 802.11ax chipset support"</div><div class='ctx'> 	depends on MAC80211 &amp;&amp; HAS_DMA</div><div class='del'>-	depends on CRYPTO_MICHAEL_MIC</div><div class='add'>+	select CRYPTO_MICHAEL_MIC</div><div class='ctx'> 	select ATH_COMMON</div><div class='ctx'> 	select QCOM_QMI_HELPERS</div><div class='ctx'> 	help</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c<br/>index 235336ef2a7a..7c0a23517949 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ahb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/ahb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ahb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ahb.c</a></div><div class='hunk'>@@ -803,8 +803,8 @@ static int ath11k_core_get_rproc(struct ath11k_base *ab)</div><div class='ctx'> </div><div class='ctx'> 	prproc = rproc_get_by_phandle(rproc_phandle);</div><div class='ctx'> 	if (!prproc) {</div><div class='del'>-		ath11k_err(ab, "failed to get rproc\n");</div><div class='del'>-		return -EINVAL;</div><div class='add'>+		ath11k_dbg(ab, ATH11K_DBG_AHB, "failed to get rproc, deferring\n");</div><div class='add'>+		return -EPROBE_DEFER;</div><div class='ctx'> 	}</div><div class='ctx'> 	ab_ahb-&gt;tgt_rproc = prproc;</div><div class='ctx'> </div><div class='hunk'>@@ -1251,7 +1251,7 @@ static void ath11k_ahb_free_resources(struct ath11k_base *ab)</div><div class='ctx'> 	platform_set_drvdata(pdev, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ath11k_ahb_remove(struct platform_device *pdev)</div><div class='add'>+static void ath11k_ahb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath11k_base *ab = platform_get_drvdata(pdev);</div><div class='ctx'> </div><div class='hunk'>@@ -1267,8 +1267,6 @@ static int ath11k_ahb_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> qmi_fail:</div><div class='ctx'> 	ath11k_ahb_free_resources(ab);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath11k_ahb_shutdown(struct platform_device *pdev)</div><div class='hunk'>@@ -1296,7 +1294,7 @@ static struct platform_driver ath11k_ahb_driver = {</div><div class='ctx'> 		.of_match_table = ath11k_ahb_of_match,</div><div class='ctx'> 	},</div><div class='ctx'> 	.probe  = ath11k_ahb_probe,</div><div class='del'>-	.remove = ath11k_ahb_remove,</div><div class='add'>+	.remove_new = ath11k_ahb_remove,</div><div class='ctx'> 	.shutdown = ath11k_ahb_shutdown,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/ce.c b/drivers/net/wireless/ath/ath11k/ce.c<br/>index 289d47ae92af..e66e86bdec20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ce.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/ce.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ce.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ce.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "dp_rx.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/ce.h b/drivers/net/wireless/ath/ath11k/ce.h<br/>index c0f6a0ba86df..69946fc70077 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ce.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/ce.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/ce.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/ce.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_CE_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h<br/>index f12b606e2d2e..7e3b6779f4e9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/core.h</a></div><div class='hunk'>@@ -599,7 +599,6 @@ struct ath11k {</div><div class='ctx'> 	struct ath11k_base *ab;</div><div class='ctx'> 	struct ath11k_pdev *pdev;</div><div class='ctx'> 	struct ieee80211_hw *hw;</div><div class='del'>-	struct ieee80211_ops *ops;</div><div class='ctx'> 	struct ath11k_pdev_wmi *wmi;</div><div class='ctx'> 	struct ath11k_pdev_dp dp;</div><div class='ctx'> 	u8 mac_addr[ETH_ALEN];</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dbring.c b/drivers/net/wireless/ath/ath11k/dbring.c<br/>index 5536e8642331..fbb6e8d8a476 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dbring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dbring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dbring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dbring.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dbring.h b/drivers/net/wireless/ath/ath11k/dbring.h<br/>index ef906c687b8c..2f93b78a50df 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dbring.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dbring.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dbring.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dbring.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_DBRING_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debug.c b/drivers/net/wireless/ath/ath11k/debug.c<br/>index f5c8a34c8802..2b8544355fc1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debug.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debug.h b/drivers/net/wireless/ath/ath11k/debug.h<br/>index 9c52804ef8ac..cc8934d15697 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debug.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debug.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debug.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debug.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _ATH11K_DEBUG_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs.c b/drivers/net/wireless/ath/ath11k/debugfs.c<br/>index be76e7d1c436..a847bc0d50c0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs.h b/drivers/net/wireless/ath/ath11k/debugfs.h<br/>index 3af0169f6cf2..44d15845f39a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _ATH11K_DEBUGFS_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c<br/>index 0207fc4910f3..870e86a31bf8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h b/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h<br/>index 96219301f05b..476689bbd4da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_htt_stats.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef DEBUG_HTT_STATS_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs_sta.c b/drivers/net/wireless/ath/ath11k/debugfs_sta.c<br/>index 8c177fba6f14..f56a24b6c8da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_sta.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs_sta.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_sta.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_sta.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/debugfs_sta.h b/drivers/net/wireless/ath/ath11k/debugfs_sta.h<br/>index e6c11b3a40aa..ace877e19275 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_sta.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/debugfs_sta.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/debugfs_sta.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/debugfs_sta.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _ATH11K_DEBUGFS_STA_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dp.c b/drivers/net/wireless/ath/ath11k/dp.c<br/>index a7252b52555c..8975dc57ad77 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;crypto/hash.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dp.h b/drivers/net/wireless/ath/ath11k/dp.h<br/>index 15815af453b2..2f6dd69d3be2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_DP_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dp_rx.c b/drivers/net/wireless/ath/ath11k/dp_rx.c<br/>index 7eac93ce7a1d..afd481f5858f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dp_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_rx.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/ieee80211.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dp_tx.c b/drivers/net/wireless/ath/ath11k/dp_tx.c<br/>index a5fa08bc623b..c1072e66e3e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dp_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_tx.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/dp_tx.h b/drivers/net/wireless/ath/ath11k/dp_tx.h<br/>index 68a21ea9b934..61be2265e09f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_tx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/dp_tx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/dp_tx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/dp_tx.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_DP_TX_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/fw.c b/drivers/net/wireless/ath/ath11k/fw.c<br/>index 8f84fba29886..4e36292a79db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/fw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/fw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/fw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/fw.c</a></div><div class='hunk'>@@ -133,7 +133,7 @@ static int ath11k_fw_request_firmware_api_n(struct ath11k_base *ab,</div><div class='ctx'> </div><div class='ctx'> 		len -= ie_len;</div><div class='ctx'> 		data += ie_len;</div><div class='del'>-	};</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hal.c b/drivers/net/wireless/ath/ath11k/hal.c<br/>index 23f3af8e372d..c060c4b5c0cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include "hal_tx.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h<br/>index 1942d41d6de5..80447f488954 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_HAL_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hal_desc.h b/drivers/net/wireless/ath/ath11k/hal_desc.h<br/>index d895ea878d9f..b2fd180bd28e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_desc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hal_desc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_desc.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include "core.h"</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.c b/drivers/net/wireless/ath/ath11k/hal_rx.c<br/>index 41946795d620..e758ee8e17c9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hal_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_rx.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "debug.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.h b/drivers/net/wireless/ath/ath11k/hal_rx.h<br/>index 472a52cf5889..0fa9aef9d533 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_rx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hal_rx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hal_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hal_rx.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_HAL_RX_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hif.h b/drivers/net/wireless/ath/ath11k/hif.h<br/>index d68ed4214dec..877a4073fed6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hif.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hif.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hif.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _HIF_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/htc.c b/drivers/net/wireless/ath/ath11k/htc.c<br/>index 2c2e425c8665..23054ab29a5e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/htc.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/htc.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/htc.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/htc.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/skbuff.h&gt;</div><div class='ctx'> #include &lt;linux/ctype.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/htc.h b/drivers/net/wireless/ath/ath11k/htc.h<br/>index d31e501c807c..86f77eacaea7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/htc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/htc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/htc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/htc.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_HTC_H</div><div class='hunk'>@@ -150,10 +151,7 @@ struct ath11k_htc_credit_report {</div><div class='ctx'> </div><div class='ctx'> struct ath11k_htc_record {</div><div class='ctx'> 	struct ath11k_htc_record_hdr hdr;</div><div class='del'>-	union {</div><div class='del'>-		struct ath11k_htc_credit_report credit_report[0];</div><div class='del'>-		u8 pauload[0];</div><div class='del'>-	};</div><div class='add'>+	struct ath11k_htc_credit_report credit_report[];</div><div class='ctx'> } __packed __aligned(4);</div><div class='ctx'> </div><div class='ctx'> enum ath11k_htc_svc_gid {</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c<br/>index d7b5ec6e6904..77d8f9237680 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hw.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h<br/>index d51a99669dd6..1b070747a5db 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/hw.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_HW_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/mac.c b/drivers/net/wireless/ath/ath11k/mac.c<br/>index 7f7b39817773..db241589424d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mac.c</a></div><div class='hunk'>@@ -4654,6 +4654,14 @@ static int ath11k_station_disassoc(struct ath11k *ar,</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static u32 ath11k_mac_max_nss(const u8 *ht_mcs_mask, const u16 *vht_mcs_mask,</div><div class='add'>+			      const u16 *he_mcs_mask)</div><div class='add'>+{</div><div class='add'>+	return max3(ath11k_mac_max_ht_nss(ht_mcs_mask),</div><div class='add'>+		    ath11k_mac_max_vht_nss(vht_mcs_mask),</div><div class='add'>+		    ath11k_mac_max_he_nss(he_mcs_mask));</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static void ath11k_sta_rc_update_wk(struct work_struct *wk)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath11k *ar;</div><div class='hunk'>@@ -4699,9 +4707,7 @@ static void ath11k_sta_rc_update_wk(struct work_struct *wk)</div><div class='ctx'> 	mutex_lock(&amp;ar-&gt;conf_mutex);</div><div class='ctx'> </div><div class='ctx'> 	nss = max_t(u32, 1, nss);</div><div class='del'>-	nss = min(nss, max(max(ath11k_mac_max_ht_nss(ht_mcs_mask),</div><div class='del'>-			       ath11k_mac_max_vht_nss(vht_mcs_mask)),</div><div class='del'>-			   ath11k_mac_max_he_nss(he_mcs_mask)));</div><div class='add'>+	nss = min(nss, ath11k_mac_max_nss(ht_mcs_mask, vht_mcs_mask, he_mcs_mask));</div><div class='ctx'> </div><div class='ctx'> 	if (changed &amp; IEEE80211_RC_BW_CHANGED) {</div><div class='ctx'> 		/* Get the peer phymode */</div><div class='hunk'>@@ -8391,9 +8397,7 @@ ath11k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw,</div><div class='ctx'> 			ath11k_warn(ar-&gt;ab,</div><div class='ctx'> 				    "could not update fixed rate settings to all peers due to mcs/nss incompatibility\n");</div><div class='ctx'> 		nss = min_t(u32, ar-&gt;num_tx_chains,</div><div class='del'>-			    max(max(ath11k_mac_max_ht_nss(ht_mcs_mask),</div><div class='del'>-				    ath11k_mac_max_vht_nss(vht_mcs_mask)),</div><div class='del'>-				ath11k_mac_max_he_nss(he_mcs_mask)));</div><div class='add'>+			    ath11k_mac_max_nss(ht_mcs_mask, vht_mcs_mask, he_mcs_mask));</div><div class='ctx'> </div><div class='ctx'> 		/* If multiple rates across different preambles are given</div><div class='ctx'> 		 * we can reconfigure this info with all peers using PEER_ASSOC</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/mac.h b/drivers/net/wireless/ath/ath11k/mac.h<br/>index 0231783ad754..0dfdeed5177b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/mac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mac.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_MAC_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c<br/>index afeabd6ecc67..6835c14b82cc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mhi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/mhi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mhi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/msi.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/mhi.h b/drivers/net/wireless/ath/ath11k/mhi.h<br/>index 8d9f852da695..f81fba2644a4 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mhi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/mhi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/mhi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/mhi.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef _ATH11K_MHI_H</div><div class='ctx'> #define _ATH11K_MHI_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/pcic.c b/drivers/net/wireless/ath/ath11k/pcic.c<br/>index 16d1e332193f..15e2ceb22a44 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/pcic.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/pcic.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/pcic.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/pcic.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='hunk'>@@ -460,8 +460,6 @@ void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='del'>-</div><div class='ctx'> 	for (i = 0; i &lt; ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {</div><div class='ctx'> 		struct ath11k_ext_irq_grp *irq_grp = &amp;ab-&gt;ext_irq_grp[i];</div><div class='ctx'> </div><div class='hunk'>@@ -471,6 +469,8 @@ void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab)</div><div class='ctx'> 		}</div><div class='ctx'> 		ath11k_pcic_ext_grp_enable(irq_grp);</div><div class='ctx'> 	}</div><div class='add'>+</div><div class='add'>+	set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='ctx'> }</div><div class='ctx'> EXPORT_SYMBOL(ath11k_pcic_ext_irq_enable);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/peer.c b/drivers/net/wireless/ath/ath11k/peer.c<br/>index 1c79a932d17f..6d0126c39301 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/peer.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/peer.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/peer.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/peer.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/peer.h b/drivers/net/wireless/ath/ath11k/peer.h<br/>index 9bd385d0a38c..3ad2f3355b14 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/peer.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/peer.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/peer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/peer.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_PEER_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c<br/>index c270dc46d506..2c7cab62b9bb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/qmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/qmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/qmi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/elf.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/qmi.h b/drivers/net/wireless/ath/ath11k/qmi.h<br/>index d477e2be814b..7e06d100af57 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/qmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/qmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/qmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/qmi.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_QMI_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/reg.c b/drivers/net/wireless/ath/ath11k/reg.c<br/>index 3c7debae800a..b4fd4d2107c7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/reg.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/rtnetlink.h&gt;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/reg.h b/drivers/net/wireless/ath/ath11k/reg.h<br/>index 84daa6543b6a..f28902f85e41 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/reg.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_REG_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/rx_desc.h b/drivers/net/wireless/ath/ath11k/rx_desc.h<br/>index 786d5f36f5e5..2da6da727278 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/rx_desc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/rx_desc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/rx_desc.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef ATH11K_RX_DESC_H</div><div class='ctx'> #define ATH11K_RX_DESC_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/spectral.c b/drivers/net/wireless/ath/ath11k/spectral.c<br/>index 0b7b7122cc05..79e091134515 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/spectral.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/spectral.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/spectral.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/spectral.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/relay.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/spectral.h b/drivers/net/wireless/ath/ath11k/spectral.h<br/>index 96bfa16e18e9..789cff7c64a7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/spectral.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/spectral.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/spectral.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/spectral.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_SPECTRAL_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/thermal.c b/drivers/net/wireless/ath/ath11k/thermal.c<br/>index c9b012f97ba5..c29b11ab5bfa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/thermal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/thermal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/thermal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/thermal.c</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/device.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/thermal.h b/drivers/net/wireless/ath/ath11k/thermal.h<br/>index 83cb67686733..cdaf4e01d92e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/thermal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/thermal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/thermal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/thermal.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _ATH11K_THERMAL_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/trace.h b/drivers/net/wireless/ath/ath11k/trace.h<br/>index 9535745fe026..235ab8ea715f 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/trace.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/trace.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/trace.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/trace.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #if !defined(_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c<br/>index 2845b4313d3a..8a65fa04b48d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/wmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wmi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/skbuff.h&gt;</div><div class='ctx'> #include &lt;linux/ctype.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/wmi.h b/drivers/net/wireless/ath/ath11k/wmi.h<br/>index 100bb816b592..ff0a9a92beeb 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/wmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wmi.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH11K_WMI_H</div><div class='hunk'>@@ -1096,25 +1096,27 @@ enum wmi_tlv_vdev_param {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum wmi_tlv_peer_flags {</div><div class='del'>-	WMI_TLV_PEER_AUTH = 0x00000001,</div><div class='del'>-	WMI_TLV_PEER_QOS = 0x00000002,</div><div class='del'>-	WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004,</div><div class='del'>-	WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010,</div><div class='del'>-	WMI_TLV_PEER_APSD = 0x00000800,</div><div class='del'>-	WMI_TLV_PEER_HT = 0x00001000,</div><div class='del'>-	WMI_TLV_PEER_40MHZ = 0x00002000,</div><div class='del'>-	WMI_TLV_PEER_STBC = 0x00008000,</div><div class='del'>-	WMI_TLV_PEER_LDPC = 0x00010000,</div><div class='del'>-	WMI_TLV_PEER_DYN_MIMOPS = 0x00020000,</div><div class='del'>-	WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000,</div><div class='del'>-	WMI_TLV_PEER_SPATIAL_MUX = 0x00200000,</div><div class='del'>-	WMI_TLV_PEER_VHT = 0x02000000,</div><div class='del'>-	WMI_TLV_PEER_80MHZ = 0x04000000,</div><div class='del'>-	WMI_TLV_PEER_PMF = 0x08000000,</div><div class='add'>+	WMI_PEER_AUTH		= 0x00000001,</div><div class='add'>+	WMI_PEER_QOS		= 0x00000002,</div><div class='add'>+	WMI_PEER_NEED_PTK_4_WAY	= 0x00000004,</div><div class='add'>+	WMI_PEER_NEED_GTK_2_WAY	= 0x00000010,</div><div class='add'>+	WMI_PEER_HE		= 0x00000400,</div><div class='add'>+	WMI_PEER_APSD		= 0x00000800,</div><div class='add'>+	WMI_PEER_HT		= 0x00001000,</div><div class='add'>+	WMI_PEER_40MHZ		= 0x00002000,</div><div class='add'>+	WMI_PEER_STBC		= 0x00008000,</div><div class='add'>+	WMI_PEER_LDPC		= 0x00010000,</div><div class='add'>+	WMI_PEER_DYN_MIMOPS	= 0x00020000,</div><div class='add'>+	WMI_PEER_STATIC_MIMOPS	= 0x00040000,</div><div class='add'>+	WMI_PEER_SPATIAL_MUX	= 0x00200000,</div><div class='add'>+	WMI_PEER_TWT_REQ	= 0x00400000,</div><div class='add'>+	WMI_PEER_TWT_RESP	= 0x00800000,</div><div class='add'>+	WMI_PEER_VHT		= 0x02000000,</div><div class='add'>+	WMI_PEER_80MHZ		= 0x04000000,</div><div class='add'>+	WMI_PEER_PMF		= 0x08000000,</div><div class='ctx'> 	WMI_PEER_IS_P2P_CAPABLE = 0x20000000,</div><div class='ctx'> 	WMI_PEER_160MHZ         = 0x40000000,</div><div class='ctx'> 	WMI_PEER_SAFEMODE_EN    = 0x80000000,</div><div class='del'>-</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> /** Enum list of TLV Tags for each parameter structure type. */</div><div class='hunk'>@@ -2580,7 +2582,6 @@ struct wmi_service_available_event {</div><div class='ctx'> struct ath11k_pdev_wmi {</div><div class='ctx'> 	struct ath11k_wmi_base *wmi_ab;</div><div class='ctx'> 	enum ath11k_htc_ep_id eid;</div><div class='del'>-	const struct wmi_peer_flags_map *peer_flags;</div><div class='ctx'> 	u32 rx_decap_mode;</div><div class='ctx'> 	wait_queue_head_t tx_ce_desc_wq;</div><div class='ctx'> };</div><div class='hunk'>@@ -4062,31 +4063,6 @@ struct wmi_unit_test_cmd {</div><div class='ctx'> </div><div class='ctx'> #define MAX_SUPPORTED_RATES 128</div><div class='ctx'> </div><div class='del'>-#define WMI_PEER_AUTH		0x00000001</div><div class='del'>-#define WMI_PEER_QOS		0x00000002</div><div class='del'>-#define WMI_PEER_NEED_PTK_4_WAY	0x00000004</div><div class='del'>-#define WMI_PEER_NEED_GTK_2_WAY	0x00000010</div><div class='del'>-#define WMI_PEER_HE		0x00000400</div><div class='del'>-#define WMI_PEER_APSD		0x00000800</div><div class='del'>-#define WMI_PEER_HT		0x00001000</div><div class='del'>-#define WMI_PEER_40MHZ		0x00002000</div><div class='del'>-#define WMI_PEER_STBC		0x00008000</div><div class='del'>-#define WMI_PEER_LDPC		0x00010000</div><div class='del'>-#define WMI_PEER_DYN_MIMOPS	0x00020000</div><div class='del'>-#define WMI_PEER_STATIC_MIMOPS	0x00040000</div><div class='del'>-#define WMI_PEER_SPATIAL_MUX	0x00200000</div><div class='del'>-#define WMI_PEER_TWT_REQ	0x00400000</div><div class='del'>-#define WMI_PEER_TWT_RESP	0x00800000</div><div class='del'>-#define WMI_PEER_VHT		0x02000000</div><div class='del'>-#define WMI_PEER_80MHZ		0x04000000</div><div class='del'>-#define WMI_PEER_PMF		0x08000000</div><div class='del'>-/* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000.</div><div class='del'>- * Need to be cleaned up</div><div class='del'>- */</div><div class='del'>-#define WMI_PEER_IS_P2P_CAPABLE	0x20000000</div><div class='del'>-#define WMI_PEER_160MHZ		0x40000000</div><div class='del'>-#define WMI_PEER_SAFEMODE_EN	0x80000000</div><div class='del'>-</div><div class='ctx'> struct beacon_tmpl_params {</div><div class='ctx'> 	u8 vdev_id;</div><div class='ctx'> 	u32 tim_ie_offset;</div><div class='hunk'>@@ -5754,7 +5730,6 @@ struct ath11k_wmi_base {</div><div class='ctx'> 	struct completion unified_ready;</div><div class='ctx'> 	DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);</div><div class='ctx'> 	wait_queue_head_t tx_credits_wq;</div><div class='del'>-	const struct wmi_peer_flags_map *peer_flags;</div><div class='ctx'> 	u32 num_mem_chunks;</div><div class='ctx'> 	u32 rx_decap_mode;</div><div class='ctx'> 	struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath11k/wow.h b/drivers/net/wireless/ath/ath11k/wow.h<br/>index 553ba850d910..c85811e3f42b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wow.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath11k/wow.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath11k/wow.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath11k/wow.h</a></div><div class='hunk'>@@ -1,6 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020 The Linux Foundation. All rights reserved.</div><div class='add'>+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef _WOW_H_</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/Kconfig b/drivers/net/wireless/ath/ath12k/Kconfig<br/>index 4f9c514c13e7..e135d2b1b61d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/Kconfig</a></div><div class='hunk'>@@ -2,7 +2,7 @@</div><div class='ctx'> config ATH12K</div><div class='ctx'> 	tristate "Qualcomm Technologies Wi-Fi 7 support (ath12k)"</div><div class='ctx'> 	depends on MAC80211 &amp;&amp; HAS_DMA &amp;&amp; PCI</div><div class='del'>-	depends on CRYPTO_MICHAEL_MIC</div><div class='add'>+	select CRYPTO_MICHAEL_MIC</div><div class='ctx'> 	select QCOM_QMI_HELPERS</div><div class='ctx'> 	select MHI_BUS</div><div class='ctx'> 	select QRTR</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/core.c b/drivers/net/wireless/ath/ath12k/core.c<br/>index b936760b5140..6c01b282fcd3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/core.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/core.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/core.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/core.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -698,13 +698,15 @@ int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab)</div><div class='ctx'> 	ret = ath12k_core_rfkill_config(ab);</div><div class='ctx'> 	if (ret &amp;&amp; ret != -EOPNOTSUPP) {</div><div class='ctx'> 		ath12k_err(ab, "failed to config rfkill: %d\n", ret);</div><div class='del'>-		goto err_core_stop;</div><div class='add'>+		goto err_core_pdev_destroy;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	mutex_unlock(&amp;ab-&gt;core_lock);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='add'>+err_core_pdev_destroy:</div><div class='add'>+	ath12k_core_pdev_destroy(ab);</div><div class='ctx'> err_core_stop:</div><div class='ctx'> 	ath12k_core_stop(ab);</div><div class='ctx'> 	ath12k_mac_destroy(ab);</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/core.h b/drivers/net/wireless/ath/ath12k/core.h<br/>index 68c42ca44fcb..8458dc292821 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/core.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/core.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/core.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/core.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_CORE_H</div><div class='hunk'>@@ -199,6 +199,8 @@ enum ath12k_dev_flags {</div><div class='ctx'> 	ATH12K_FLAG_REGISTERED,</div><div class='ctx'> 	ATH12K_FLAG_QMI_FAIL,</div><div class='ctx'> 	ATH12K_FLAG_HTC_SUSPEND_COMPLETE,</div><div class='add'>+	ATH12K_FLAG_CE_IRQ_ENABLED,</div><div class='add'>+	ATH12K_FLAG_EXT_IRQ_ENABLED,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum ath12k_monitor_flags {</div><div class='hunk'>@@ -467,7 +469,6 @@ struct ath12k {</div><div class='ctx'> 	struct ath12k_base *ab;</div><div class='ctx'> 	struct ath12k_pdev *pdev;</div><div class='ctx'> 	struct ieee80211_hw *hw;</div><div class='del'>-	struct ieee80211_ops *ops;</div><div class='ctx'> 	struct ath12k_wmi_pdev *wmi;</div><div class='ctx'> 	struct ath12k_pdev_dp dp;</div><div class='ctx'> 	u8 mac_addr[ETH_ALEN];</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dbring.c b/drivers/net/wireless/ath/ath12k/dbring.c<br/>index 8fbf868e6f7e..788160c84c68 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dbring.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dbring.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dbring.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dbring.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/debug.c b/drivers/net/wireless/ath/ath12k/debug.c<br/>index 45d33279e665..fe5a732ba9ec 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/debug.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/vmalloc.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp.c b/drivers/net/wireless/ath/ath12k/dp.c<br/>index 6893466f61f0..a6f81f2f97ef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;crypto/hash.h&gt;</div><div class='hunk'>@@ -961,9 +961,7 @@ int ath12k_dp_service_srng(struct ath12k_base *ab,</div><div class='ctx'> 		struct ath12k_dp *dp = &amp;ab-&gt;dp;</div><div class='ctx'> 		struct dp_rxdma_ring *rx_ring = &amp;dp-&gt;rx_refill_buf_ring;</div><div class='ctx'> </div><div class='del'>-		ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, 0,</div><div class='del'>-					    ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm,</div><div class='del'>-					    true);</div><div class='add'>+		ath12k_dp_rx_bufs_replenish(ab, rx_ring, 0);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: Implement handler for other interrupts */</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp.h b/drivers/net/wireless/ath/ath12k/dp.h<br/>index 61f765432516..1df3cdd46140 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_DP_H</div><div class='hunk'>@@ -31,7 +31,7 @@ struct dp_srng {</div><div class='ctx'> 	u32 ring_id;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-struct dp_rxdma_ring {</div><div class='add'>+struct dp_rxdma_mon_ring {</div><div class='ctx'> 	struct dp_srng refill_buf_ring;</div><div class='ctx'> 	struct idr bufs_idr;</div><div class='ctx'> 	/* Protects bufs_idr */</div><div class='hunk'>@@ -39,6 +39,11 @@ struct dp_rxdma_ring {</div><div class='ctx'> 	int bufs_max;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+struct dp_rxdma_ring {</div><div class='add'>+	struct dp_srng refill_buf_ring;</div><div class='add'>+	int bufs_max;</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> #define ATH12K_TX_COMPL_NEXT(x)	(((x) + 1) % DP_TX_COMP_RING_SIZE)</div><div class='ctx'> </div><div class='ctx'> struct dp_tx_ring {</div><div class='hunk'>@@ -353,8 +358,8 @@ struct ath12k_dp {</div><div class='ctx'> 	struct dp_rxdma_ring rx_refill_buf_ring;</div><div class='ctx'> 	struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];</div><div class='ctx'> 	struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];</div><div class='del'>-	struct dp_rxdma_ring rxdma_mon_buf_ring;</div><div class='del'>-	struct dp_rxdma_ring tx_mon_buf_ring;</div><div class='add'>+	struct dp_rxdma_mon_ring rxdma_mon_buf_ring;</div><div class='add'>+	struct dp_rxdma_mon_ring tx_mon_buf_ring;</div><div class='ctx'> 	struct ath12k_reo_q_addr_lut reoq_lut;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp_mon.c b/drivers/net/wireless/ath/ath12k/dp_mon.c<br/>index f44bc5494ce7..be4b39f5fa80 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_mon.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp_mon.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_mon.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_mon.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "dp_mon.h"</div><div class='hunk'>@@ -797,7 +797,7 @@ ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab,</div><div class='ctx'> 		/* TODO: add msdu start parsing logic */</div><div class='ctx'> 		break;</div><div class='ctx'> 	case HAL_MON_BUF_ADDR: {</div><div class='del'>-		struct dp_rxdma_ring *buf_ring = &amp;ab-&gt;dp.rxdma_mon_buf_ring;</div><div class='add'>+		struct dp_rxdma_mon_ring *buf_ring = &amp;ab-&gt;dp.rxdma_mon_buf_ring;</div><div class='ctx'> 		struct dp_mon_packet_info *packet_info =</div><div class='ctx'> 			(struct dp_mon_packet_info *)tlv_data;</div><div class='ctx'> 		int buf_id = u32_get_bits(packet_info-&gt;cookie,</div><div class='hunk'>@@ -1091,7 +1091,7 @@ static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct</div><div class='ctx'> 	spin_unlock_bh(&amp;ar-&gt;ab-&gt;base_lock);</div><div class='ctx'> </div><div class='ctx'> 	ath12k_dbg(ar-&gt;ab, ATH12K_DBG_DATA,</div><div class='del'>-		   "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",</div><div class='add'>+		   "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",</div><div class='ctx'> 		   msdu,</div><div class='ctx'> 		   msdu-&gt;len,</div><div class='ctx'> 		   peer ? peer-&gt;addr : NULL,</div><div class='hunk'>@@ -1104,6 +1104,7 @@ static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_40) ? "40" : "",</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_80) ? "80" : "",</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_160) ? "160" : "",</div><div class='add'>+		   (status-&gt;bw == RATE_INFO_BW_320) ? "320" : "",</div><div class='ctx'> 		   status-&gt;enc_flags &amp; RX_ENC_FLAG_SHORT_GI ? "sgi " : "",</div><div class='ctx'> 		   status-&gt;rate_idx,</div><div class='ctx'> 		   status-&gt;nss,</div><div class='hunk'>@@ -1259,7 +1260,7 @@ ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,</div><div class='del'>-				struct dp_rxdma_ring *buf_ring,</div><div class='add'>+				struct dp_rxdma_mon_ring *buf_ring,</div><div class='ctx'> 				int req_entries)</div><div class='ctx'> {</div><div class='ctx'> 	struct hal_mon_buf_ring *mon_buf;</div><div class='hunk'>@@ -1902,7 +1903,7 @@ ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	case HAL_MON_BUF_ADDR: {</div><div class='del'>-		struct dp_rxdma_ring *buf_ring = &amp;ab-&gt;dp.tx_mon_buf_ring;</div><div class='add'>+		struct dp_rxdma_mon_ring *buf_ring = &amp;ab-&gt;dp.tx_mon_buf_ring;</div><div class='ctx'> 		struct dp_mon_packet_info *packet_info =</div><div class='ctx'> 			(struct dp_mon_packet_info *)tlv_data;</div><div class='ctx'> 		int buf_id = u32_get_bits(packet_info-&gt;cookie,</div><div class='hunk'>@@ -2067,7 +2068,7 @@ int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget,</div><div class='ctx'> 	struct ath12k_skb_rxcb *rxcb;</div><div class='ctx'> 	struct dp_srng *mon_dst_ring;</div><div class='ctx'> 	struct hal_srng *srng;</div><div class='del'>-	struct dp_rxdma_ring *buf_ring;</div><div class='add'>+	struct dp_rxdma_mon_ring *buf_ring;</div><div class='ctx'> 	u64 cookie;</div><div class='ctx'> 	u32 ppdu_id;</div><div class='ctx'> 	int num_buffs_reaped = 0, srng_id, buf_id;</div><div class='hunk'>@@ -2480,7 +2481,7 @@ int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id,</div><div class='ctx'> 	struct ath12k_skb_rxcb *rxcb;</div><div class='ctx'> 	struct dp_srng *mon_dst_ring;</div><div class='ctx'> 	struct hal_srng *srng;</div><div class='del'>-	struct dp_rxdma_ring *buf_ring;</div><div class='add'>+	struct dp_rxdma_mon_ring *buf_ring;</div><div class='ctx'> 	struct ath12k_sta *arsta = NULL;</div><div class='ctx'> 	struct ath12k_peer *peer;</div><div class='ctx'> 	u64 cookie;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp_mon.h b/drivers/net/wireless/ath/ath12k/dp_mon.h<br/>index c18c385798a1..fb9e9c176ce5 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_mon.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp_mon.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_mon.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_mon.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_DP_MON_H</div><div class='hunk'>@@ -80,7 +80,7 @@ ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar,</div><div class='ctx'> 				  int mac_id, struct sk_buff *skb,</div><div class='ctx'> 				  struct napi_struct *napi);</div><div class='ctx'> int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab,</div><div class='del'>-				struct dp_rxdma_ring *buf_ring,</div><div class='add'>+				struct dp_rxdma_mon_ring *buf_ring,</div><div class='ctx'> 				int req_entries);</div><div class='ctx'> int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id,</div><div class='ctx'> 			       int *budget, enum dp_monitor_mode monitor_mode,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.c b/drivers/net/wireless/ath/ath12k/dp_rx.c<br/>index 3543fadac4a5..1ee83f765929 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_rx.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/ieee80211.h&gt;</div><div class='hunk'>@@ -256,22 +256,20 @@ static int ath12k_dp_purge_mon_ring(struct ath12k_base *ab)</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> /* Returns number of Rx buffers replenished */</div><div class='del'>-int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id,</div><div class='add'>+int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,</div><div class='ctx'> 				struct dp_rxdma_ring *rx_ring,</div><div class='del'>-				int req_entries,</div><div class='del'>-				enum hal_rx_buf_return_buf_manager mgr,</div><div class='del'>-				bool hw_cc)</div><div class='add'>+				int req_entries)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_buffer_addr *desc;</div><div class='ctx'> 	struct hal_srng *srng;</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	int num_free;</div><div class='ctx'> 	int num_remain;</div><div class='del'>-	int buf_id;</div><div class='ctx'> 	u32 cookie;</div><div class='ctx'> 	dma_addr_t paddr;</div><div class='ctx'> 	struct ath12k_dp *dp = &amp;ab-&gt;dp;</div><div class='ctx'> 	struct ath12k_rx_desc_info *rx_desc;</div><div class='add'>+	enum hal_rx_buf_return_buf_manager mgr = ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm;</div><div class='ctx'> </div><div class='ctx'> 	req_entries = min(req_entries, rx_ring-&gt;bufs_max);</div><div class='ctx'> </div><div class='hunk'>@@ -307,42 +305,29 @@ int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id,</div><div class='ctx'> 		if (dma_mapping_error(ab-&gt;dev, paddr))</div><div class='ctx'> 			goto fail_free_skb;</div><div class='ctx'> </div><div class='del'>-		if (hw_cc) {</div><div class='del'>-			spin_lock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='del'>-</div><div class='del'>-			/* Get desc from free list and store in used list</div><div class='del'>-			 * for cleanup purposes</div><div class='del'>-			 *</div><div class='del'>-			 * TODO: pass the removed descs rather than</div><div class='del'>-			 * add/read to optimize</div><div class='del'>-			 */</div><div class='del'>-			rx_desc = list_first_entry_or_null(&amp;dp-&gt;rx_desc_free_list,</div><div class='del'>-							   struct ath12k_rx_desc_info,</div><div class='del'>-							   list);</div><div class='del'>-			if (!rx_desc) {</div><div class='del'>-				spin_unlock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='del'>-				goto fail_dma_unmap;</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			rx_desc-&gt;skb = skb;</div><div class='del'>-			cookie = rx_desc-&gt;cookie;</div><div class='del'>-			list_del(&amp;rx_desc-&gt;list);</div><div class='del'>-			list_add_tail(&amp;rx_desc-&gt;list, &amp;dp-&gt;rx_desc_used_list);</div><div class='add'>+		spin_lock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='ctx'> </div><div class='add'>+		/* Get desc from free list and store in used list</div><div class='add'>+		 * for cleanup purposes</div><div class='add'>+		 *</div><div class='add'>+		 * TODO: pass the removed descs rather than</div><div class='add'>+		 * add/read to optimize</div><div class='add'>+		 */</div><div class='add'>+		rx_desc = list_first_entry_or_null(&amp;dp-&gt;rx_desc_free_list,</div><div class='add'>+						   struct ath12k_rx_desc_info,</div><div class='add'>+						   list);</div><div class='add'>+		if (!rx_desc) {</div><div class='ctx'> 			spin_unlock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='del'>-		} else {</div><div class='del'>-			spin_lock_bh(&amp;rx_ring-&gt;idr_lock);</div><div class='del'>-			buf_id = idr_alloc(&amp;rx_ring-&gt;bufs_idr, skb, 0,</div><div class='del'>-					   rx_ring-&gt;bufs_max * 3, GFP_ATOMIC);</div><div class='del'>-			spin_unlock_bh(&amp;rx_ring-&gt;idr_lock);</div><div class='del'>-			if (buf_id &lt; 0)</div><div class='del'>-				goto fail_dma_unmap;</div><div class='del'>-			cookie = u32_encode_bits(mac_id,</div><div class='del'>-						 DP_RXDMA_BUF_COOKIE_PDEV_ID) |</div><div class='del'>-				 u32_encode_bits(buf_id,</div><div class='del'>-						 DP_RXDMA_BUF_COOKIE_BUF_ID);</div><div class='add'>+			goto fail_dma_unmap;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='add'>+		rx_desc-&gt;skb = skb;</div><div class='add'>+		cookie = rx_desc-&gt;cookie;</div><div class='add'>+		list_del(&amp;rx_desc-&gt;list);</div><div class='add'>+		list_add_tail(&amp;rx_desc-&gt;list, &amp;dp-&gt;rx_desc_used_list);</div><div class='add'>+</div><div class='add'>+		spin_unlock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='add'>+</div><div class='ctx'> 		desc = ath12k_hal_srng_src_get_next_entry(ab, srng);</div><div class='ctx'> 		if (!desc)</div><div class='ctx'> 			goto fail_buf_unassign;</div><div class='hunk'>@@ -361,17 +346,11 @@ int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id,</div><div class='ctx'> 	return req_entries - num_remain;</div><div class='ctx'> </div><div class='ctx'> fail_buf_unassign:</div><div class='del'>-	if (hw_cc) {</div><div class='del'>-		spin_lock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='del'>-		list_del(&amp;rx_desc-&gt;list);</div><div class='del'>-		list_add_tail(&amp;rx_desc-&gt;list, &amp;dp-&gt;rx_desc_free_list);</div><div class='del'>-		rx_desc-&gt;skb = NULL;</div><div class='del'>-		spin_unlock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='del'>-	} else {</div><div class='del'>-		spin_lock_bh(&amp;rx_ring-&gt;idr_lock);</div><div class='del'>-		idr_remove(&amp;rx_ring-&gt;bufs_idr, buf_id);</div><div class='del'>-		spin_unlock_bh(&amp;rx_ring-&gt;idr_lock);</div><div class='del'>-	}</div><div class='add'>+	spin_lock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='add'>+	list_del(&amp;rx_desc-&gt;list);</div><div class='add'>+	list_add_tail(&amp;rx_desc-&gt;list, &amp;dp-&gt;rx_desc_free_list);</div><div class='add'>+	rx_desc-&gt;skb = NULL;</div><div class='add'>+	spin_unlock_bh(&amp;dp-&gt;rx_desc_lock);</div><div class='ctx'> fail_dma_unmap:</div><div class='ctx'> 	dma_unmap_single(ab-&gt;dev, paddr, skb-&gt;len + skb_tailroom(skb),</div><div class='ctx'> 			 DMA_FROM_DEVICE);</div><div class='hunk'>@@ -385,8 +364,8 @@ fail_free_skb:</div><div class='ctx'> 	return req_entries - num_remain;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ath12k_dp_rxdma_buf_ring_free(struct ath12k_base *ab,</div><div class='del'>-					 struct dp_rxdma_ring *rx_ring)</div><div class='add'>+static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,</div><div class='add'>+					     struct dp_rxdma_mon_ring *rx_ring)</div><div class='ctx'> {</div><div class='ctx'> 	struct sk_buff *skb;</div><div class='ctx'> 	int buf_id;</div><div class='hunk'>@@ -411,46 +390,49 @@ static int ath12k_dp_rxdma_buf_ring_free(struct ath12k_base *ab,</div><div class='ctx'> static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_dp *dp = &amp;ab-&gt;dp;</div><div class='del'>-	struct dp_rxdma_ring *rx_ring = &amp;dp-&gt;rx_refill_buf_ring;</div><div class='ctx'> </div><div class='del'>-	ath12k_dp_rxdma_buf_ring_free(ab, rx_ring);</div><div class='add'>+	ath12k_dp_rxdma_mon_buf_ring_free(ab, &amp;dp-&gt;rxdma_mon_buf_ring);</div><div class='add'>+</div><div class='add'>+	ath12k_dp_rxdma_mon_buf_ring_free(ab, &amp;dp-&gt;tx_mon_buf_ring);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='ctx'> </div><div class='del'>-	rx_ring = &amp;dp-&gt;rxdma_mon_buf_ring;</div><div class='del'>-	ath12k_dp_rxdma_buf_ring_free(ab, rx_ring);</div><div class='add'>+static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,</div><div class='add'>+					      struct dp_rxdma_mon_ring *rx_ring,</div><div class='add'>+					      u32 ringtype)</div><div class='add'>+{</div><div class='add'>+	int num_entries;</div><div class='ctx'> </div><div class='del'>-	rx_ring = &amp;dp-&gt;tx_mon_buf_ring;</div><div class='del'>-	ath12k_dp_rxdma_buf_ring_free(ab, rx_ring);</div><div class='add'>+	num_entries = rx_ring-&gt;refill_buf_ring.size /</div><div class='add'>+		ath12k_hal_srng_get_entrysize(ab, ringtype);</div><div class='add'>+</div><div class='add'>+	rx_ring-&gt;bufs_max = num_entries;</div><div class='add'>+	ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,</div><div class='del'>-					  struct dp_rxdma_ring *rx_ring,</div><div class='del'>-					  u32 ringtype)</div><div class='add'>+					  struct dp_rxdma_ring *rx_ring)</div><div class='ctx'> {</div><div class='ctx'> 	int num_entries;</div><div class='ctx'> </div><div class='ctx'> 	num_entries = rx_ring-&gt;refill_buf_ring.size /</div><div class='del'>-		ath12k_hal_srng_get_entrysize(ab, ringtype);</div><div class='add'>+		ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);</div><div class='ctx'> </div><div class='ctx'> 	rx_ring-&gt;bufs_max = num_entries;</div><div class='del'>-	if ((ringtype == HAL_RXDMA_MONITOR_BUF) || (ringtype == HAL_TX_MONITOR_BUF))</div><div class='del'>-		ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);</div><div class='del'>-	else</div><div class='del'>-		ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_entries,</div><div class='del'>-					    ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm,</div><div class='del'>-					    ringtype == HAL_RXDMA_BUF);</div><div class='add'>+	ath12k_dp_rx_bufs_replenish(ab, rx_ring, num_entries);</div><div class='add'>+</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_dp *dp = &amp;ab-&gt;dp;</div><div class='del'>-	struct dp_rxdma_ring *rx_ring = &amp;dp-&gt;rx_refill_buf_ring;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='del'>-	ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring,</div><div class='del'>-					     HAL_RXDMA_BUF);</div><div class='add'>+	ret = ath12k_dp_rxdma_ring_buf_setup(ab, &amp;dp-&gt;rx_refill_buf_ring);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ath12k_warn(ab,</div><div class='ctx'> 			    "failed to setup HAL_RXDMA_BUF\n");</div><div class='hunk'>@@ -458,18 +440,18 @@ static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ab-&gt;hw_params-&gt;rxdma1_enable) {</div><div class='del'>-		rx_ring = &amp;dp-&gt;rxdma_mon_buf_ring;</div><div class='del'>-		ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring,</div><div class='del'>-						     HAL_RXDMA_MONITOR_BUF);</div><div class='add'>+		ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,</div><div class='add'>+							 &amp;dp-&gt;rxdma_mon_buf_ring,</div><div class='add'>+							 HAL_RXDMA_MONITOR_BUF);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			ath12k_warn(ab,</div><div class='ctx'> 				    "failed to setup HAL_RXDMA_MONITOR_BUF\n");</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		rx_ring = &amp;dp-&gt;tx_mon_buf_ring;</div><div class='del'>-		ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring,</div><div class='del'>-						     HAL_TX_MONITOR_BUF);</div><div class='add'>+		ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,</div><div class='add'>+							 &amp;dp-&gt;tx_mon_buf_ring,</div><div class='add'>+							 HAL_TX_MONITOR_BUF);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			ath12k_warn(ab,</div><div class='ctx'> 				    "failed to setup HAL_TX_MONITOR_BUF\n");</div><div class='hunk'>@@ -1339,9 +1321,6 @@ ath12k_update_per_peer_tx_stats(struct ath12k *ar,</div><div class='ctx'> 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;</div><div class='ctx'> 	bool is_ampdu = false;</div><div class='ctx'> </div><div class='del'>-	if (!usr_stats)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='ctx'> 	if (!(usr_stats-&gt;tlv_flags &amp; BIT(HTT_PPDU_STATS_TAG_USR_RATE)))</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='hunk'>@@ -2438,7 +2417,7 @@ static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *nap</div><div class='ctx'> 	spin_unlock_bh(&amp;ab-&gt;base_lock);</div><div class='ctx'> </div><div class='ctx'> 	ath12k_dbg(ab, ATH12K_DBG_DATA,</div><div class='del'>-		   "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",</div><div class='add'>+		   "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",</div><div class='ctx'> 		   msdu,</div><div class='ctx'> 		   msdu-&gt;len,</div><div class='ctx'> 		   peer ? peer-&gt;addr : NULL,</div><div class='hunk'>@@ -2452,6 +2431,7 @@ static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *nap</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_40) ? "40" : "",</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_80) ? "80" : "",</div><div class='ctx'> 		   (status-&gt;bw == RATE_INFO_BW_160) ? "160" : "",</div><div class='add'>+		   (status-&gt;bw == RATE_INFO_BW_320) ? "320" : "",</div><div class='ctx'> 		   status-&gt;enc_flags &amp; RX_ENC_FLAG_SHORT_GI ? "sgi " : "",</div><div class='ctx'> 		   status-&gt;rate_idx,</div><div class='ctx'> 		   status-&gt;nss,</div><div class='hunk'>@@ -2714,9 +2694,7 @@ try_again:</div><div class='ctx'> 	if (!total_msdu_reaped)</div><div class='ctx'> 		goto exit;</div><div class='ctx'> </div><div class='del'>-	/* TODO: Move to implicit BM? */</div><div class='del'>-	ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped,</div><div class='del'>-				    ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm, true);</div><div class='add'>+	ath12k_dp_rx_bufs_replenish(ab, rx_ring, num_buffs_reaped);</div><div class='ctx'> </div><div class='ctx'> 	ath12k_dp_rx_process_received_packets(ab, napi, &amp;msdu_list,</div><div class='ctx'> 					      ring_id);</div><div class='hunk'>@@ -3494,8 +3472,7 @@ exit:</div><div class='ctx'> </div><div class='ctx'> 	rx_ring = &amp;dp-&gt;rx_refill_buf_ring;</div><div class='ctx'> </div><div class='del'>-	ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, tot_n_bufs_reaped,</div><div class='del'>-				    ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm, true);</div><div class='add'>+	ath12k_dp_rx_bufs_replenish(ab, rx_ring, tot_n_bufs_reaped);</div><div class='ctx'> </div><div class='ctx'> 	return tot_n_bufs_reaped;</div><div class='ctx'> }</div><div class='hunk'>@@ -3808,8 +3785,7 @@ int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,</div><div class='ctx'> 	if (!num_buffs_reaped)</div><div class='ctx'> 		goto done;</div><div class='ctx'> </div><div class='del'>-	ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped,</div><div class='del'>-				    ab-&gt;hw_params-&gt;hal_params-&gt;rx_buf_rbm, true);</div><div class='add'>+	ath12k_dp_rx_bufs_replenish(ab, rx_ring, num_buffs_reaped);</div><div class='ctx'> </div><div class='ctx'> 	rcu_read_lock();</div><div class='ctx'> 	for (i = 0; i &lt;  ab-&gt;num_radios; i++) {</div><div class='hunk'>@@ -4090,9 +4066,6 @@ int ath12k_dp_rx_alloc(struct ath12k_base *ab)</div><div class='ctx'> 	struct ath12k_dp *dp = &amp;ab-&gt;dp;</div><div class='ctx'> 	int i, ret;</div><div class='ctx'> </div><div class='del'>-	idr_init(&amp;dp-&gt;rx_refill_buf_ring.bufs_idr);</div><div class='del'>-	spin_lock_init(&amp;dp-&gt;rx_refill_buf_ring.idr_lock);</div><div class='del'>-</div><div class='ctx'> 	idr_init(&amp;dp-&gt;rxdma_mon_buf_ring.bufs_idr);</div><div class='ctx'> 	spin_lock_init(&amp;dp-&gt;rxdma_mon_buf_ring.idr_lock);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp_rx.h b/drivers/net/wireless/ath/ath12k/dp_rx.h<br/>index c955b5c859d1..05b3d5581dbe 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_rx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp_rx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_rx.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef ATH12K_DP_RX_H</div><div class='ctx'> #define ATH12K_DP_RX_H</div><div class='hunk'>@@ -116,11 +116,9 @@ int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,</div><div class='ctx'> int ath12k_dp_rx_process(struct ath12k_base *ab, int mac_id,</div><div class='ctx'> 			 struct napi_struct *napi,</div><div class='ctx'> 			 int budget);</div><div class='del'>-int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id,</div><div class='add'>+int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,</div><div class='ctx'> 				struct dp_rxdma_ring *rx_ring,</div><div class='del'>-				int req_entries,</div><div class='del'>-				enum hal_rx_buf_return_buf_manager mgr,</div><div class='del'>-				bool hw_cc);</div><div class='add'>+				int req_entries);</div><div class='ctx'> int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar);</div><div class='ctx'> int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/dp_tx.c b/drivers/net/wireless/ath/ath12k/dp_tx.c<br/>index 492ca6ce6714..62f9cdbb811c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_tx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/dp_tx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/dp_tx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/dp_tx.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "core.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hal.c b/drivers/net/wireless/ath/ath12k/hal.c<br/>index eca86fc25a60..a489369d8068 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hal.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/dma-mapping.h&gt;</div><div class='ctx'> #include "hal_tx.h"</div><div class='hunk'>@@ -889,8 +889,8 @@ static u8 *ath12k_hw_wcn7850_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)</div><div class='ctx'> </div><div class='ctx'> static bool ath12k_hw_wcn7850_rx_desc_is_da_mcbc(struct hal_rx_desc *desc)</div><div class='ctx'> {</div><div class='del'>-	return __le16_to_cpu(desc-&gt;u.wcn7850.msdu_end.info5) &amp;</div><div class='del'>-	       RX_MSDU_END_INFO5_DA_IS_MCBC;</div><div class='add'>+	return __le32_to_cpu(desc-&gt;u.wcn7850.msdu_end.info13) &amp;</div><div class='add'>+	       RX_MSDU_END_INFO13_MCAST_BCAST;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath12k_hw_wcn7850_rx_desc_get_dot11_hdr(struct hal_rx_desc *desc,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hal.h b/drivers/net/wireless/ath/ath12k/hal.h<br/>index 66035a787c72..fc47e7e6b498 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hal.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_HAL_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hal_rx.c b/drivers/net/wireless/ath/ath12k/hal_rx.c<br/>index f6afbd8196bf..4f25eb9f7745 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal_rx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hal_rx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal_rx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal_rx.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include "debug.h"</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hal_rx.h b/drivers/net/wireless/ath/ath12k/hal_rx.h<br/>index fcfb6c819047..095216eabc01 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal_rx.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hal_rx.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hal_rx.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hal_rx.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_HAL_RX_H</div><div class='hunk'>@@ -61,6 +61,7 @@ enum hal_rx_bw {</div><div class='ctx'> 	HAL_RX_BW_40MHZ,</div><div class='ctx'> 	HAL_RX_BW_80MHZ,</div><div class='ctx'> 	HAL_RX_BW_160MHZ,</div><div class='add'>+	HAL_RX_BW_320MHZ,</div><div class='ctx'> 	HAL_RX_BW_MAX,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hif.h b/drivers/net/wireless/ath/ath12k/hif.h<br/>index 4095fd82b1b3..c653ca1f59b2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hif.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hif.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hif.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hif.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_HIF_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hw.c b/drivers/net/wireless/ath/ath12k/hw.c<br/>index 2245fb510ba2..de60d988d860 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hw.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hw.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hw.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hw.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/types.h&gt;</div><div class='hunk'>@@ -949,7 +949,8 @@ static const struct ath12k_hw_params ath12k_hw_params[] = {</div><div class='ctx'> 		.rx_mac_buf_ring = true,</div><div class='ctx'> 		.vdev_start_delay = true,</div><div class='ctx'> </div><div class='del'>-		.interface_modes = BIT(NL80211_IFTYPE_STATION),</div><div class='add'>+		.interface_modes = BIT(NL80211_IFTYPE_STATION) |</div><div class='add'>+				   BIT(NL80211_IFTYPE_AP),</div><div class='ctx'> 		.supports_monitor = false,</div><div class='ctx'> </div><div class='ctx'> 		.idle_ps = true,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/hw.h b/drivers/net/wireless/ath/ath12k/hw.h<br/>index 2d6427cf41a4..d2622bfef942 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hw.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/hw.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/hw.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/hw.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_HW_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c<br/>index fc0d14ea328e..88cec54c6c2e 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mac.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/mac.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mac.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mac.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;net/mac80211.h&gt;</div><div class='hunk'>@@ -343,6 +343,9 @@ ath12k_mac_bw_to_mac80211_bw(enum ath12k_supported_bw bw)</div><div class='ctx'> 	case ATH12K_BW_160:</div><div class='ctx'> 		ret = RATE_INFO_BW_160;</div><div class='ctx'> 		break;</div><div class='add'>+	case ATH12K_BW_320:</div><div class='add'>+		ret = RATE_INFO_BW_320;</div><div class='add'>+		break;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return ret;</div><div class='hunk'>@@ -359,6 +362,8 @@ enum ath12k_supported_bw ath12k_mac_mac80211_bw_to_ath12k_bw(enum rate_info_bw b</div><div class='ctx'> 		return ATH12K_BW_80;</div><div class='ctx'> 	case RATE_INFO_BW_160:</div><div class='ctx'> 		return ATH12K_BW_160;</div><div class='add'>+	case RATE_INFO_BW_320:</div><div class='add'>+		return ATH12K_BW_320;</div><div class='ctx'> 	default:</div><div class='ctx'> 		return ATH12K_BW_20;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -3726,6 +3731,9 @@ static u32 ath12k_mac_ieee80211_sta_bw_to_wmi(struct ath12k *ar,</div><div class='ctx'> 	case IEEE80211_STA_RX_BW_160:</div><div class='ctx'> 		bw = WMI_PEER_CHWIDTH_160MHZ;</div><div class='ctx'> 		break;</div><div class='add'>+	case IEEE80211_STA_RX_BW_320:</div><div class='add'>+		bw = WMI_PEER_CHWIDTH_320MHZ;</div><div class='add'>+		break;</div><div class='ctx'> 	default:</div><div class='ctx'> 		ath12k_warn(ar-&gt;ab, "Invalid bandwidth %d in rc update for %pM\n",</div><div class='ctx'> 			    sta-&gt;deflink.bandwidth, sta-&gt;addr);</div><div class='hunk'>@@ -4987,7 +4995,7 @@ static void ath12k_mac_op_tx(struct ieee80211_hw *hw,</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			ath12k_warn(ar-&gt;ab, "failed to queue management frame %d\n",</div><div class='ctx'> 				    ret);</div><div class='del'>-			ieee80211_free_txskb(ar-&gt;hw, skb);</div><div class='add'>+			ieee80211_free_txskb(hw, skb);</div><div class='ctx'> 		}</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -4995,7 +5003,7 @@ static void ath12k_mac_op_tx(struct ieee80211_hw *hw,</div><div class='ctx'> 	ret = ath12k_dp_tx(ar, arvif, skb);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ath12k_warn(ar-&gt;ab, "failed to transmit frame %d\n", ret);</div><div class='del'>-		ieee80211_free_txskb(ar-&gt;hw, skb);</div><div class='add'>+		ieee80211_free_txskb(hw, skb);</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -5596,7 +5604,7 @@ static int ath12k_mac_op_add_interface(struct ieee80211_hw *hw,</div><div class='ctx'> 		goto err_peer_del;</div><div class='ctx'> </div><div class='ctx'> 	param_id = WMI_VDEV_PARAM_RTS_THRESHOLD;</div><div class='del'>-	param_value = ar-&gt;hw-&gt;wiphy-&gt;rts_threshold;</div><div class='add'>+	param_value = hw-&gt;wiphy-&gt;rts_threshold;</div><div class='ctx'> 	ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif-&gt;vdev_id,</div><div class='ctx'> 					    param_id, param_value);</div><div class='ctx'> 	if (ret) {</div><div class='hunk'>@@ -6258,10 +6266,11 @@ ath12k_mac_update_active_vif_chan(struct ath12k *ar,</div><div class='ctx'> 				  struct ieee80211_chanctx_conf *ctx)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_mac_change_chanctx_arg arg = { .ctx = ctx };</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='ctx'> </div><div class='ctx'> 	lockdep_assert_held(&amp;ar-&gt;conf_mutex);</div><div class='ctx'> </div><div class='del'>-	ieee80211_iterate_active_interfaces_atomic(ar-&gt;hw,</div><div class='add'>+	ieee80211_iterate_active_interfaces_atomic(hw,</div><div class='ctx'> 						   IEEE80211_IFACE_ITER_NORMAL,</div><div class='ctx'> 						   ath12k_mac_change_chanctx_cnt_iter,</div><div class='ctx'> 						   &amp;arg);</div><div class='hunk'>@@ -6272,7 +6281,7 @@ ath12k_mac_update_active_vif_chan(struct ath12k *ar,</div><div class='ctx'> 	if (!arg.vifs)</div><div class='ctx'> 		return;</div><div class='ctx'> </div><div class='del'>-	ieee80211_iterate_active_interfaces_atomic(ar-&gt;hw,</div><div class='add'>+	ieee80211_iterate_active_interfaces_atomic(hw,</div><div class='ctx'> 						   IEEE80211_IFACE_ITER_NORMAL,</div><div class='ctx'> 						   ath12k_mac_change_chanctx_fill_iter,</div><div class='ctx'> 						   &amp;arg);</div><div class='hunk'>@@ -6380,8 +6389,8 @@ ath12k_mac_op_assign_vif_chanctx(struct ieee80211_hw *hw,</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (ab-&gt;hw_params-&gt;vdev_start_delay &amp;&amp;</div><div class='del'>-	    (arvif-&gt;vdev_type == WMI_VDEV_TYPE_AP ||</div><div class='del'>-	    arvif-&gt;vdev_type == WMI_VDEV_TYPE_MONITOR)) {</div><div class='add'>+	    arvif-&gt;vdev_type != WMI_VDEV_TYPE_AP &amp;&amp;</div><div class='add'>+	    arvif-&gt;vdev_type != WMI_VDEV_TYPE_MONITOR) {</div><div class='ctx'> 		param.vdev_id = arvif-&gt;vdev_id;</div><div class='ctx'> 		param.peer_type = WMI_PEER_TYPE_DEFAULT;</div><div class='ctx'> 		param.peer_addr = ar-&gt;mac_addr;</div><div class='hunk'>@@ -6836,7 +6845,7 @@ ath12k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw,</div><div class='ctx'> 				    arvif-&gt;vdev_id, ret);</div><div class='ctx'> 			return ret;</div><div class='ctx'> 		}</div><div class='del'>-		ieee80211_iterate_stations_atomic(ar-&gt;hw,</div><div class='add'>+		ieee80211_iterate_stations_atomic(hw,</div><div class='ctx'> 						  ath12k_mac_disable_peer_fixed_rate,</div><div class='ctx'> 						  arvif);</div><div class='ctx'> 	} else if (ath12k_mac_bitrate_mask_get_single_nss(ar, band, mask,</div><div class='hunk'>@@ -6882,14 +6891,14 @@ ath12k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw,</div><div class='ctx'> 			return -EINVAL;</div><div class='ctx'> 		}</div><div class='ctx'> </div><div class='del'>-		ieee80211_iterate_stations_atomic(ar-&gt;hw,</div><div class='add'>+		ieee80211_iterate_stations_atomic(hw,</div><div class='ctx'> 						  ath12k_mac_disable_peer_fixed_rate,</div><div class='ctx'> 						  arvif);</div><div class='ctx'> </div><div class='ctx'> 		mutex_lock(&amp;ar-&gt;conf_mutex);</div><div class='ctx'> </div><div class='ctx'> 		arvif-&gt;bitrate_mask = *mask;</div><div class='del'>-		ieee80211_iterate_stations_atomic(ar-&gt;hw,</div><div class='add'>+		ieee80211_iterate_stations_atomic(hw,</div><div class='ctx'> 						  ath12k_mac_set_bitrate_mask_iter,</div><div class='ctx'> 						  arvif);</div><div class='ctx'> </div><div class='hunk'>@@ -6927,7 +6936,7 @@ ath12k_mac_op_reconfig_complete(struct ieee80211_hw *hw,</div><div class='ctx'> 		ath12k_warn(ar-&gt;ab, "pdev %d successfully recovered\n",</div><div class='ctx'> 			    ar-&gt;pdev-&gt;pdev_id);</div><div class='ctx'> 		ar-&gt;state = ATH12K_STATE_ON;</div><div class='del'>-		ieee80211_wake_queues(ar-&gt;hw);</div><div class='add'>+		ieee80211_wake_queues(hw);</div><div class='ctx'> </div><div class='ctx'> 		if (ab-&gt;is_reset) {</div><div class='ctx'> 			recovery_count = atomic_inc_return(&amp;ab-&gt;recovery_count);</div><div class='hunk'>@@ -7151,6 +7160,7 @@ static u32 ath12k_get_phy_id(struct ath12k *ar, u32 band)</div><div class='ctx'> static int ath12k_mac_setup_channels_rates(struct ath12k *ar,</div><div class='ctx'> 					   u32 supported_bands)</div><div class='ctx'> {</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='ctx'> 	struct ieee80211_supported_band *band;</div><div class='ctx'> 	struct ath12k_wmi_hal_reg_capabilities_ext_arg *reg_cap;</div><div class='ctx'> 	void *channels;</div><div class='hunk'>@@ -7176,7 +7186,7 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar,</div><div class='ctx'> 		band-&gt;channels = channels;</div><div class='ctx'> 		band-&gt;n_bitrates = ath12k_g_rates_size;</div><div class='ctx'> 		band-&gt;bitrates = ath12k_g_rates;</div><div class='del'>-		ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_2GHZ] = band;</div><div class='add'>+		hw-&gt;wiphy-&gt;bands[NL80211_BAND_2GHZ] = band;</div><div class='ctx'> </div><div class='ctx'> 		if (ar-&gt;ab-&gt;hw_params-&gt;single_pdev_only) {</div><div class='ctx'> 			phy_id = ath12k_get_phy_id(ar, WMI_HOST_WLAN_2G_CAP);</div><div class='hunk'>@@ -7203,7 +7213,7 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar,</div><div class='ctx'> 			band-&gt;channels = channels;</div><div class='ctx'> 			band-&gt;n_bitrates = ath12k_a_rates_size;</div><div class='ctx'> 			band-&gt;bitrates = ath12k_a_rates;</div><div class='del'>-			ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_6GHZ] = band;</div><div class='add'>+			hw-&gt;wiphy-&gt;bands[NL80211_BAND_6GHZ] = band;</div><div class='ctx'> 			ath12k_mac_update_ch_list(ar, band,</div><div class='ctx'> 						  reg_cap-&gt;low_5ghz_chan,</div><div class='ctx'> 						  reg_cap-&gt;high_5ghz_chan);</div><div class='hunk'>@@ -7225,7 +7235,7 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar,</div><div class='ctx'> 			band-&gt;channels = channels;</div><div class='ctx'> 			band-&gt;n_bitrates = ath12k_a_rates_size;</div><div class='ctx'> 			band-&gt;bitrates = ath12k_a_rates;</div><div class='del'>-			ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_5GHZ] = band;</div><div class='add'>+			hw-&gt;wiphy-&gt;bands[NL80211_BAND_5GHZ] = band;</div><div class='ctx'> </div><div class='ctx'> 			if (ar-&gt;ab-&gt;hw_params-&gt;single_pdev_only) {</div><div class='ctx'> 				phy_id = ath12k_get_phy_id(ar, WMI_HOST_WLAN_5G_CAP);</div><div class='hunk'>@@ -7244,6 +7254,8 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar,</div><div class='ctx'> static int ath12k_mac_setup_iface_combinations(struct ath12k *ar)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_base *ab = ar-&gt;ab;</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='add'>+	struct wiphy *wiphy = hw-&gt;wiphy;</div><div class='ctx'> 	struct ieee80211_iface_combination *combinations;</div><div class='ctx'> 	struct ieee80211_iface_limit *limits;</div><div class='ctx'> 	int n_limits, max_interfaces;</div><div class='hunk'>@@ -7294,8 +7306,8 @@ static int ath12k_mac_setup_iface_combinations(struct ath12k *ar)</div><div class='ctx'> 						BIT(NL80211_CHAN_WIDTH_40) |</div><div class='ctx'> 						BIT(NL80211_CHAN_WIDTH_80);</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;iface_combinations = combinations;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;n_iface_combinations = 1;</div><div class='add'>+	wiphy-&gt;iface_combinations = combinations;</div><div class='add'>+	wiphy-&gt;n_iface_combinations = 1;</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='hunk'>@@ -7339,9 +7351,12 @@ static const struct wiphy_iftype_ext_capab ath12k_iftypes_ext_capa[] = {</div><div class='ctx'> </div><div class='ctx'> static void __ath12k_mac_unregister(struct ath12k *ar)</div><div class='ctx'> {</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='add'>+	struct wiphy *wiphy = hw-&gt;wiphy;</div><div class='add'>+</div><div class='ctx'> 	cancel_work_sync(&amp;ar-&gt;regd_update_work);</div><div class='ctx'> </div><div class='del'>-	ieee80211_unregister_hw(ar-&gt;hw);</div><div class='add'>+	ieee80211_unregister_hw(hw);</div><div class='ctx'> </div><div class='ctx'> 	idr_for_each(&amp;ar-&gt;txmgmt_idr, ath12k_mac_tx_mgmt_pending_free, ar);</div><div class='ctx'> 	idr_destroy(&amp;ar-&gt;txmgmt_idr);</div><div class='hunk'>@@ -7350,10 +7365,10 @@ static void __ath12k_mac_unregister(struct ath12k *ar)</div><div class='ctx'> 	kfree(ar-&gt;mac.sbands[NL80211_BAND_5GHZ].channels);</div><div class='ctx'> 	kfree(ar-&gt;mac.sbands[NL80211_BAND_6GHZ].channels);</div><div class='ctx'> </div><div class='del'>-	kfree(ar-&gt;hw-&gt;wiphy-&gt;iface_combinations[0].limits);</div><div class='del'>-	kfree(ar-&gt;hw-&gt;wiphy-&gt;iface_combinations);</div><div class='add'>+	kfree(wiphy-&gt;iface_combinations[0].limits);</div><div class='add'>+	kfree(wiphy-&gt;iface_combinations);</div><div class='ctx'> </div><div class='del'>-	SET_IEEE80211_DEV(ar-&gt;hw, NULL);</div><div class='add'>+	SET_IEEE80211_DEV(hw, NULL);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void ath12k_mac_unregister(struct ath12k_base *ab)</div><div class='hunk'>@@ -7375,6 +7390,8 @@ void ath12k_mac_unregister(struct ath12k_base *ab)</div><div class='ctx'> static int __ath12k_mac_register(struct ath12k *ar)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_base *ab = ar-&gt;ab;</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='add'>+	struct wiphy *wiphy = hw-&gt;wiphy;</div><div class='ctx'> 	struct ath12k_pdev_cap *cap = &amp;ar-&gt;pdev-&gt;cap;</div><div class='ctx'> 	static const u32 cipher_suites[] = {</div><div class='ctx'> 		WLAN_CIPHER_SUITE_TKIP,</div><div class='hunk'>@@ -7392,9 +7409,9 @@ static int __ath12k_mac_register(struct ath12k *ar)</div><div class='ctx'> </div><div class='ctx'> 	ath12k_pdev_caps_update(ar);</div><div class='ctx'> </div><div class='del'>-	SET_IEEE80211_PERM_ADDR(ar-&gt;hw, ar-&gt;mac_addr);</div><div class='add'>+	SET_IEEE80211_PERM_ADDR(hw, ar-&gt;mac_addr);</div><div class='ctx'> </div><div class='del'>-	SET_IEEE80211_DEV(ar-&gt;hw, ab-&gt;dev);</div><div class='add'>+	SET_IEEE80211_DEV(hw, ab-&gt;dev);</div><div class='ctx'> </div><div class='ctx'> 	ret = ath12k_mac_setup_channels_rates(ar,</div><div class='ctx'> 					      cap-&gt;supported_bands);</div><div class='hunk'>@@ -7410,103 +7427,102 @@ static int __ath12k_mac_register(struct ath12k *ar)</div><div class='ctx'> 		goto err_free_channels;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;available_antennas_rx = cap-&gt;rx_chain_mask;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;available_antennas_tx = cap-&gt;tx_chain_mask;</div><div class='add'>+	wiphy-&gt;available_antennas_rx = cap-&gt;rx_chain_mask;</div><div class='add'>+	wiphy-&gt;available_antennas_tx = cap-&gt;tx_chain_mask;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;interface_modes = ab-&gt;hw_params-&gt;interface_modes;</div><div class='add'>+	wiphy-&gt;interface_modes = ab-&gt;hw_params-&gt;interface_modes;</div><div class='ctx'> </div><div class='del'>-	if (ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_2GHZ] &amp;&amp;</div><div class='del'>-	    ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_5GHZ] &amp;&amp;</div><div class='del'>-	    ar-&gt;hw-&gt;wiphy-&gt;bands[NL80211_BAND_6GHZ])</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, SINGLE_SCAN_ON_ALL_BANDS);</div><div class='add'>+	if (wiphy-&gt;bands[NL80211_BAND_2GHZ] &amp;&amp;</div><div class='add'>+	    wiphy-&gt;bands[NL80211_BAND_5GHZ] &amp;&amp;</div><div class='add'>+	    wiphy-&gt;bands[NL80211_BAND_6GHZ])</div><div class='add'>+		ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);</div><div class='ctx'> </div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SIGNAL_DBM);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SUPPORTS_PS);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SUPPORTS_DYNAMIC_PS);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, MFP_CAPABLE);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, REPORTS_TX_ACK_STATUS);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, HAS_RATE_CONTROL);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, AP_LINK_PS);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SPECTRUM_MGMT);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, CONNECTION_MONITOR);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SUPPORTS_PER_STA_GTK);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, CHANCTX_STA_CSA);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, QUEUE_CONTROL);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, SUPPORTS_TX_FRAG);</div><div class='del'>-	ieee80211_hw_set(ar-&gt;hw, REPORTS_LOW_ACK);</div><div class='add'>+	ieee80211_hw_set(hw, SIGNAL_DBM);</div><div class='add'>+	ieee80211_hw_set(hw, SUPPORTS_PS);</div><div class='add'>+	ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);</div><div class='add'>+	ieee80211_hw_set(hw, MFP_CAPABLE);</div><div class='add'>+	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);</div><div class='add'>+	ieee80211_hw_set(hw, HAS_RATE_CONTROL);</div><div class='add'>+	ieee80211_hw_set(hw, AP_LINK_PS);</div><div class='add'>+	ieee80211_hw_set(hw, SPECTRUM_MGMT);</div><div class='add'>+	ieee80211_hw_set(hw, CONNECTION_MONITOR);</div><div class='add'>+	ieee80211_hw_set(hw, SUPPORTS_PER_STA_GTK);</div><div class='add'>+	ieee80211_hw_set(hw, CHANCTX_STA_CSA);</div><div class='add'>+	ieee80211_hw_set(hw, QUEUE_CONTROL);</div><div class='add'>+	ieee80211_hw_set(hw, SUPPORTS_TX_FRAG);</div><div class='add'>+	ieee80211_hw_set(hw, REPORTS_LOW_ACK);</div><div class='ctx'> </div><div class='ctx'> 	if (ht_cap &amp; WMI_HT_CAP_ENABLED) {</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, AMPDU_AGGREGATION);</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, TX_AMPDU_SETUP_IN_HW);</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, SUPPORTS_REORDERING_BUFFER);</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, SUPPORTS_AMSDU_IN_AMPDU);</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, USES_RSS);</div><div class='add'>+		ieee80211_hw_set(hw, AMPDU_AGGREGATION);</div><div class='add'>+		ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW);</div><div class='add'>+		ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);</div><div class='add'>+		ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);</div><div class='add'>+		ieee80211_hw_set(hw, USES_RSS);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;features |= NL80211_FEATURE_STATIC_SMPS;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;flags |= WIPHY_FLAG_IBSS_RSN;</div><div class='add'>+	wiphy-&gt;features |= NL80211_FEATURE_STATIC_SMPS;</div><div class='add'>+	wiphy-&gt;flags |= WIPHY_FLAG_IBSS_RSN;</div><div class='ctx'> </div><div class='ctx'> 	/* TODO: Check if HT capability advertised from firmware is different</div><div class='ctx'> 	 * for each band for a dual band capable radio. It will be tricky to</div><div class='ctx'> 	 * handle it when the ht capability different for each band.</div><div class='ctx'> 	 */</div><div class='ctx'> 	if (ht_cap &amp; WMI_HT_CAP_DYNAMIC_SMPS)</div><div class='del'>-		ar-&gt;hw-&gt;wiphy-&gt;features |= NL80211_FEATURE_DYNAMIC_SMPS;</div><div class='add'>+		wiphy-&gt;features |= NL80211_FEATURE_DYNAMIC_SMPS;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;max_scan_ssids = WLAN_SCAN_PARAMS_MAX_SSID;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;max_scan_ie_len = WLAN_SCAN_PARAMS_MAX_IE_LEN;</div><div class='add'>+	wiphy-&gt;max_scan_ssids = WLAN_SCAN_PARAMS_MAX_SSID;</div><div class='add'>+	wiphy-&gt;max_scan_ie_len = WLAN_SCAN_PARAMS_MAX_IE_LEN;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;max_listen_interval = ATH12K_MAX_HW_LISTEN_INTERVAL;</div><div class='add'>+	hw-&gt;max_listen_interval = ATH12K_MAX_HW_LISTEN_INTERVAL;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;max_remain_on_channel_duration = 5000;</div><div class='add'>+	wiphy-&gt;flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;</div><div class='add'>+	wiphy-&gt;flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;</div><div class='add'>+	wiphy-&gt;max_remain_on_channel_duration = 5000;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;flags |= WIPHY_FLAG_AP_UAPSD;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |</div><div class='add'>+	wiphy-&gt;flags |= WIPHY_FLAG_AP_UAPSD;</div><div class='add'>+	wiphy-&gt;features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |</div><div class='ctx'> 				   NL80211_FEATURE_AP_SCAN;</div><div class='ctx'> </div><div class='ctx'> 	ar-&gt;max_num_stations = TARGET_NUM_STATIONS;</div><div class='ctx'> 	ar-&gt;max_num_peers = TARGET_NUM_PEERS_PDEV;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;max_ap_assoc_sta = ar-&gt;max_num_stations;</div><div class='add'>+	wiphy-&gt;max_ap_assoc_sta = ar-&gt;max_num_stations;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;queues = ATH12K_HW_MAX_QUEUES;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;tx_queue_len = ATH12K_QUEUE_LEN;</div><div class='del'>-	ar-&gt;hw-&gt;offchannel_tx_hw_queue = ATH12K_HW_MAX_QUEUES - 1;</div><div class='del'>-	ar-&gt;hw-&gt;max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;</div><div class='add'>+	hw-&gt;queues = ATH12K_HW_MAX_QUEUES;</div><div class='add'>+	wiphy-&gt;tx_queue_len = ATH12K_QUEUE_LEN;</div><div class='add'>+	hw-&gt;offchannel_tx_hw_queue = ATH12K_HW_MAX_QUEUES - 1;</div><div class='add'>+	hw-&gt;max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;vif_data_size = sizeof(struct ath12k_vif);</div><div class='del'>-	ar-&gt;hw-&gt;sta_data_size = sizeof(struct ath12k_sta);</div><div class='add'>+	hw-&gt;vif_data_size = sizeof(struct ath12k_vif);</div><div class='add'>+	hw-&gt;sta_data_size = sizeof(struct ath12k_sta);</div><div class='ctx'> </div><div class='del'>-	wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);</div><div class='del'>-	wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);</div><div class='add'>+	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);</div><div class='add'>+	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;cipher_suites = cipher_suites;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;n_cipher_suites = ARRAY_SIZE(cipher_suites);</div><div class='add'>+	wiphy-&gt;cipher_suites = cipher_suites;</div><div class='add'>+	wiphy-&gt;n_cipher_suites = ARRAY_SIZE(cipher_suites);</div><div class='ctx'> </div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;iftype_ext_capab = ath12k_iftypes_ext_capa;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;num_iftype_ext_capab =</div><div class='del'>-		ARRAY_SIZE(ath12k_iftypes_ext_capa);</div><div class='add'>+	wiphy-&gt;iftype_ext_capab = ath12k_iftypes_ext_capa;</div><div class='add'>+	wiphy-&gt;num_iftype_ext_capab = ARRAY_SIZE(ath12k_iftypes_ext_capa);</div><div class='ctx'> </div><div class='ctx'> 	if (ar-&gt;supports_6ghz) {</div><div class='del'>-		wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy,</div><div class='add'>+		wiphy_ext_feature_set(wiphy,</div><div class='ctx'> 				      NL80211_EXT_FEATURE_FILS_DISCOVERY);</div><div class='del'>-		wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy,</div><div class='add'>+		wiphy_ext_feature_set(wiphy,</div><div class='ctx'> 				      NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	wiphy_ext_feature_set(ar-&gt;hw-&gt;wiphy, NL80211_EXT_FEATURE_PUNCT);</div><div class='add'>+	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_PUNCT);</div><div class='ctx'> </div><div class='del'>-	ath12k_reg_init(ar);</div><div class='add'>+	ath12k_reg_init(hw);</div><div class='ctx'> </div><div class='ctx'> 	if (!test_bit(ATH12K_FLAG_RAW_MODE, &amp;ab-&gt;dev_flags)) {</div><div class='del'>-		ar-&gt;hw-&gt;netdev_features = NETIF_F_HW_CSUM;</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, SW_CRYPTO_CONTROL);</div><div class='del'>-		ieee80211_hw_set(ar-&gt;hw, SUPPORT_FAST_XMIT);</div><div class='add'>+		hw-&gt;netdev_features = NETIF_F_HW_CSUM;</div><div class='add'>+		ieee80211_hw_set(hw, SW_CRYPTO_CONTROL);</div><div class='add'>+		ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	ret = ieee80211_register_hw(ar-&gt;hw);</div><div class='add'>+	ret = ieee80211_register_hw(hw);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ath12k_err(ar-&gt;ab, "ieee80211 registration failed: %d\n", ret);</div><div class='ctx'> 		goto err_free_if_combs;</div><div class='hunk'>@@ -7518,7 +7534,7 @@ static int __ath12k_mac_register(struct ath12k *ar)</div><div class='ctx'> 		 * while. But that time is so short and in practise it make</div><div class='ctx'> 		 * a difference in real life.</div><div class='ctx'> 		 */</div><div class='del'>-		ar-&gt;hw-&gt;wiphy-&gt;interface_modes &amp;= ~BIT(NL80211_IFTYPE_MONITOR);</div><div class='add'>+		wiphy-&gt;interface_modes &amp;= ~BIT(NL80211_IFTYPE_MONITOR);</div><div class='ctx'> </div><div class='ctx'> 	/* Apply the regd received during initialization */</div><div class='ctx'> 	ret = ath12k_regd_update(ar, true);</div><div class='hunk'>@@ -7530,11 +7546,11 @@ static int __ath12k_mac_register(struct ath12k *ar)</div><div class='ctx'> 	return 0;</div><div class='ctx'> </div><div class='ctx'> err_unregister_hw:</div><div class='del'>-	ieee80211_unregister_hw(ar-&gt;hw);</div><div class='add'>+	ieee80211_unregister_hw(hw);</div><div class='ctx'> </div><div class='ctx'> err_free_if_combs:</div><div class='del'>-	kfree(ar-&gt;hw-&gt;wiphy-&gt;iface_combinations[0].limits);</div><div class='del'>-	kfree(ar-&gt;hw-&gt;wiphy-&gt;iface_combinations);</div><div class='add'>+	kfree(wiphy-&gt;iface_combinations[0].limits);</div><div class='add'>+	kfree(wiphy-&gt;iface_combinations);</div><div class='ctx'> </div><div class='ctx'> err_free_channels:</div><div class='ctx'> 	kfree(ar-&gt;mac.sbands[NL80211_BAND_2GHZ].channels);</div><div class='hunk'>@@ -7542,7 +7558,7 @@ err_free_channels:</div><div class='ctx'> 	kfree(ar-&gt;mac.sbands[NL80211_BAND_6GHZ].channels);</div><div class='ctx'> </div><div class='ctx'> err:</div><div class='del'>-	SET_IEEE80211_DEV(ar-&gt;hw, NULL);</div><div class='add'>+	SET_IEEE80211_DEV(hw, NULL);</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/mac.h b/drivers/net/wireless/ath/ath12k/mac.h<br/>index 59b4e8f5eee0..7c63bb628adc 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mac.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/mac.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mac.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mac.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_MAC_H</div><div class='hunk'>@@ -43,6 +43,7 @@ enum ath12k_supported_bw {</div><div class='ctx'> 	ATH12K_BW_40    = 1,</div><div class='ctx'> 	ATH12K_BW_80    = 2,</div><div class='ctx'> 	ATH12K_BW_160   = 3,</div><div class='add'>+	ATH12K_BW_320   = 4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> extern const struct htt_rx_ring_tlv_filter ath12k_mac_mon_status_filter_default;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/mhi.c b/drivers/net/wireless/ath/ath12k/mhi.c<br/>index 39e640293cdc..d5441ddb374b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mhi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/mhi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/mhi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/mhi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/msi.h&gt;</div><div class='hunk'>@@ -251,6 +251,7 @@ static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)</div><div class='ctx'> 	u32 user_base_data, base_vector;</div><div class='ctx'> 	int ret, num_vectors, i;</div><div class='ctx'> 	int *irq;</div><div class='add'>+	unsigned int msi_data;</div><div class='ctx'> </div><div class='ctx'> 	ret = ath12k_pci_get_user_msi_assignment(ab,</div><div class='ctx'> 						 "MHI", &amp;num_vectors,</div><div class='hunk'>@@ -265,9 +266,15 @@ static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)</div><div class='ctx'> 	if (!irq)</div><div class='ctx'> 		return -ENOMEM;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; num_vectors; i++)</div><div class='del'>-		irq[i] = ath12k_pci_get_msi_irq(ab-&gt;dev,</div><div class='del'>-						base_vector + i);</div><div class='add'>+	msi_data = base_vector;</div><div class='add'>+	for (i = 0; i &lt; num_vectors; i++) {</div><div class='add'>+		if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+			irq[i] = ath12k_pci_get_msi_irq(ab-&gt;dev,</div><div class='add'>+							msi_data++);</div><div class='add'>+		else</div><div class='add'>+			irq[i] = ath12k_pci_get_msi_irq(ab-&gt;dev,</div><div class='add'>+							msi_data);</div><div class='add'>+	}</div><div class='ctx'> </div><div class='ctx'> 	ab_pci-&gt;mhi_ctrl-&gt;irq = irq;</div><div class='ctx'> 	ab_pci-&gt;mhi_ctrl-&gt;nr_irqs = num_vectors;</div><div class='hunk'>@@ -374,6 +381,9 @@ int ath12k_mhi_register(struct ath12k_pci *ab_pci)</div><div class='ctx'> 		goto free_controller;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		mhi_ctrl-&gt;irq_flags = IRQF_SHARED | IRQF_NOBALANCING;</div><div class='add'>+</div><div class='ctx'> 	mhi_ctrl-&gt;iova_start = 0;</div><div class='ctx'> 	mhi_ctrl-&gt;iova_stop = 0xffffffff;</div><div class='ctx'> 	mhi_ctrl-&gt;sbl_size = SZ_512K;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c<br/>index 3006cd3fbe11..f0d2e2d8719c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/pci.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/module.h&gt;</div><div class='hunk'>@@ -60,6 +60,17 @@ static const struct ath12k_msi_config ath12k_msi_config[] = {</div><div class='ctx'> 	},</div><div class='ctx'> };</div><div class='ctx'> </div><div class='add'>+static const struct ath12k_msi_config msi_config_one_msi = {</div><div class='add'>+	.total_vectors = 1,</div><div class='add'>+	.total_users = 4,</div><div class='add'>+	.users = (struct ath12k_msi_user[]) {</div><div class='add'>+		{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },</div><div class='add'>+		{ .name = "CE", .num_vectors = 1, .base_vector = 0 },</div><div class='add'>+		{ .name = "WAKE", .num_vectors = 1, .base_vector = 0 },</div><div class='add'>+		{ .name = "DP", .num_vectors = 1, .base_vector = 0 },</div><div class='add'>+	},</div><div class='add'>+};</div><div class='add'>+</div><div class='ctx'> static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {</div><div class='ctx'> 	"bhi",</div><div class='ctx'> 	"mhi-er0",</div><div class='hunk'>@@ -355,16 +366,30 @@ static void ath12k_pci_free_irq(struct ath12k_base *ab)</div><div class='ctx'> </div><div class='ctx'> static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> 	u32 irq_idx;</div><div class='ctx'> </div><div class='add'>+	/* In case of one MSI vector, we handle irq enable/disable in a</div><div class='add'>+	 * uniform way since we only have one irq</div><div class='add'>+	 */</div><div class='add'>+	if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;</div><div class='ctx'> 	enable_irq(ab-&gt;irq_num[irq_idx]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> 	u32 irq_idx;</div><div class='ctx'> </div><div class='add'>+	/* In case of one MSI vector, we handle irq enable/disable in a</div><div class='add'>+	 * uniform way since we only have one irq</div><div class='add'>+	 */</div><div class='add'>+	if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;</div><div class='ctx'> 	disable_irq_nosync(ab-&gt;irq_num[irq_idx]);</div><div class='ctx'> }</div><div class='hunk'>@@ -373,6 +398,8 @@ static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ab-&gt;hw_params-&gt;ce_count; i++) {</div><div class='ctx'> 		if (ath12k_ce_get_attr_flags(ab, i) &amp; CE_ATTR_DIS_INTR)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -397,20 +424,27 @@ static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)</div><div class='ctx'> static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);</div><div class='add'>+	int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe-&gt;pipe_num;</div><div class='ctx'> </div><div class='ctx'> 	ath12k_ce_per_engine_service(ce_pipe-&gt;ab, ce_pipe-&gt;pipe_num);</div><div class='ctx'> </div><div class='del'>-	ath12k_pci_ce_irq_enable(ce_pipe-&gt;ab, ce_pipe-&gt;pipe_num);</div><div class='add'>+	enable_irq(ce_pipe-&gt;ab-&gt;irq_num[irq_idx]);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_ce_pipe *ce_pipe = arg;</div><div class='add'>+	struct ath12k_base *ab = ce_pipe-&gt;ab;</div><div class='add'>+	int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe-&gt;pipe_num;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &amp;ab-&gt;dev_flags))</div><div class='add'>+		return IRQ_HANDLED;</div><div class='ctx'> </div><div class='ctx'> 	/* last interrupt received for this CE */</div><div class='ctx'> 	ce_pipe-&gt;timestamp = jiffies;</div><div class='ctx'> </div><div class='del'>-	ath12k_pci_ce_irq_disable(ce_pipe-&gt;ab, ce_pipe-&gt;pipe_num);</div><div class='add'>+	disable_irq_nosync(ab-&gt;irq_num[irq_idx]);</div><div class='add'>+</div><div class='ctx'> 	tasklet_schedule(&amp;ce_pipe-&gt;intr_tq);</div><div class='ctx'> </div><div class='ctx'> 	return IRQ_HANDLED;</div><div class='hunk'>@@ -418,8 +452,15 @@ static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)</div><div class='ctx'> </div><div class='ctx'> static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp-&gt;ab);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/* In case of one MSI vector, we handle irq enable/disable</div><div class='add'>+	 * in a uniform way since we only have one irq</div><div class='add'>+	 */</div><div class='add'>+	if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; irq_grp-&gt;num_irq; i++)</div><div class='ctx'> 		disable_irq_nosync(irq_grp-&gt;ab-&gt;irq_num[irq_grp-&gt;irqs[i]]);</div><div class='ctx'> }</div><div class='hunk'>@@ -428,6 +469,8 @@ static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {</div><div class='ctx'> 		struct ath12k_ext_irq_grp *irq_grp = &amp;ab-&gt;ext_irq_grp[i];</div><div class='ctx'> </div><div class='hunk'>@@ -440,8 +483,15 @@ static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)</div><div class='ctx'> </div><div class='ctx'> static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp-&gt;ab);</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	/* In case of one MSI vector, we handle irq enable/disable in a</div><div class='add'>+	 * uniform way since we only have one irq</div><div class='add'>+	 */</div><div class='add'>+	if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		return;</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; irq_grp-&gt;num_irq; i++)</div><div class='ctx'> 		enable_irq(irq_grp-&gt;ab-&gt;irq_num[irq_grp-&gt;irqs[i]]);</div><div class='ctx'> }</div><div class='hunk'>@@ -467,11 +517,13 @@ static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> 						napi);</div><div class='ctx'> 	struct ath12k_base *ab = irq_grp-&gt;ab;</div><div class='ctx'> 	int work_done;</div><div class='add'>+	int i;</div><div class='ctx'> </div><div class='ctx'> 	work_done = ath12k_dp_service_srng(ab, irq_grp, budget);</div><div class='ctx'> 	if (work_done &lt; budget) {</div><div class='ctx'> 		napi_complete_done(napi, work_done);</div><div class='del'>-		ath12k_pci_ext_grp_enable(irq_grp);</div><div class='add'>+		for (i = 0; i &lt; irq_grp-&gt;num_irq; i++)</div><div class='add'>+			enable_irq(irq_grp-&gt;ab-&gt;irq_num[irq_grp-&gt;irqs[i]]);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	if (work_done &gt; budget)</div><div class='hunk'>@@ -483,13 +535,19 @@ static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)</div><div class='ctx'> static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_ext_irq_grp *irq_grp = arg;</div><div class='add'>+	struct ath12k_base *ab = irq_grp-&gt;ab;</div><div class='add'>+	int i;</div><div class='add'>+</div><div class='add'>+	if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &amp;ab-&gt;dev_flags))</div><div class='add'>+		return IRQ_HANDLED;</div><div class='ctx'> </div><div class='ctx'> 	ath12k_dbg(irq_grp-&gt;ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);</div><div class='ctx'> </div><div class='ctx'> 	/* last interrupt received for this group */</div><div class='ctx'> 	irq_grp-&gt;timestamp = jiffies;</div><div class='ctx'> </div><div class='del'>-	ath12k_pci_ext_grp_disable(irq_grp);</div><div class='add'>+	for (i = 0; i &lt; irq_grp-&gt;num_irq; i++)</div><div class='add'>+		disable_irq_nosync(irq_grp-&gt;ab-&gt;irq_num[irq_grp-&gt;irqs[i]]);</div><div class='ctx'> </div><div class='ctx'> 	napi_schedule(&amp;irq_grp-&gt;napi);</div><div class='ctx'> </div><div class='hunk'>@@ -498,6 +556,7 @@ static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)</div><div class='ctx'> </div><div class='ctx'> static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> 	int i, j, ret, num_vectors = 0;</div><div class='ctx'> 	u32 user_base_data = 0, base_vector = 0, base_idx;</div><div class='ctx'> </div><div class='hunk'>@@ -544,23 +603,32 @@ static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)</div><div class='ctx'> </div><div class='ctx'> 			irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);</div><div class='ctx'> 			ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,</div><div class='del'>-					  IRQF_SHARED,</div><div class='add'>+					  ab_pci-&gt;irq_flags,</div><div class='ctx'> 					  "DP_EXT_IRQ", irq_grp);</div><div class='ctx'> 			if (ret) {</div><div class='ctx'> 				ath12k_err(ab, "failed request irq %d: %d\n",</div><div class='ctx'> 					   vector, ret);</div><div class='ctx'> 				return ret;</div><div class='ctx'> 			}</div><div class='del'>-</div><div class='del'>-			disable_irq_nosync(ab-&gt;irq_num[irq_idx]);</div><div class='ctx'> 		}</div><div class='add'>+		ath12k_pci_ext_grp_disable(irq_grp);</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci,</div><div class='add'>+					    const struct cpumask *m)</div><div class='add'>+{</div><div class='add'>+	if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		return 0;</div><div class='add'>+</div><div class='add'>+	return irq_set_affinity_hint(ab_pci-&gt;pdev-&gt;irq, m);</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ath12k_pci_config_irq(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> 	struct ath12k_ce_pipe *ce_pipe;</div><div class='ctx'> 	u32 msi_data_start;</div><div class='ctx'> 	u32 msi_data_count, msi_data_idx;</div><div class='hunk'>@@ -589,7 +657,7 @@ static int ath12k_pci_config_irq(struct ath12k_base *ab)</div><div class='ctx'> 		tasklet_setup(&amp;ce_pipe-&gt;intr_tq, ath12k_pci_ce_tasklet);</div><div class='ctx'> </div><div class='ctx'> 		ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,</div><div class='del'>-				  IRQF_SHARED, irq_name[irq_idx],</div><div class='add'>+				  ab_pci-&gt;irq_flags, irq_name[irq_idx],</div><div class='ctx'> 				  ce_pipe);</div><div class='ctx'> 		if (ret) {</div><div class='ctx'> 			ath12k_err(ab, "failed to request irq %d: %d\n",</div><div class='hunk'>@@ -626,6 +694,8 @@ static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ab-&gt;hw_params-&gt;ce_count; i++) {</div><div class='ctx'> 		if (ath12k_ce_get_attr_flags(ab, i) &amp; CE_ATTR_DIS_INTR)</div><div class='ctx'> 			continue;</div><div class='hunk'>@@ -670,16 +740,27 @@ static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)</div><div class='ctx'> 					    msi_config-&gt;total_vectors,</div><div class='ctx'> 					    msi_config-&gt;total_vectors,</div><div class='ctx'> 					    PCI_IRQ_MSI);</div><div class='del'>-	if (num_vectors != msi_config-&gt;total_vectors) {</div><div class='del'>-		ath12k_err(ab, "failed to get %d MSI vectors, only %d available",</div><div class='del'>-			   msi_config-&gt;total_vectors, num_vectors);</div><div class='ctx'> </div><div class='del'>-		if (num_vectors &gt;= 0)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		else</div><div class='del'>-			return num_vectors;</div><div class='add'>+	if (num_vectors == msi_config-&gt;total_vectors) {</div><div class='add'>+		set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags);</div><div class='add'>+		ab_pci-&gt;irq_flags = IRQF_SHARED;</div><div class='add'>+	} else {</div><div class='add'>+		num_vectors = pci_alloc_irq_vectors(ab_pci-&gt;pdev,</div><div class='add'>+						    1,</div><div class='add'>+						    1,</div><div class='add'>+						    PCI_IRQ_MSI);</div><div class='add'>+		if (num_vectors &lt; 0) {</div><div class='add'>+			ret = -EINVAL;</div><div class='add'>+			goto reset_msi_config;</div><div class='add'>+		}</div><div class='add'>+		clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags);</div><div class='add'>+		ab_pci-&gt;msi_config = &amp;msi_config_one_msi;</div><div class='add'>+		ab_pci-&gt;irq_flags = IRQF_SHARED | IRQF_NOBALANCING;</div><div class='add'>+		ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n");</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	ath12k_info(ab, "MSI vectors: %d\n", num_vectors);</div><div class='add'>+</div><div class='ctx'> 	ath12k_pci_msi_disable(ab_pci);</div><div class='ctx'> </div><div class='ctx'> 	msi_desc = irq_get_msi_desc(ab_pci-&gt;pdev-&gt;irq);</div><div class='hunk'>@@ -700,6 +781,7 @@ static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)</div><div class='ctx'> free_msi_vector:</div><div class='ctx'> 	pci_free_irq_vectors(ab_pci-&gt;pdev);</div><div class='ctx'> </div><div class='add'>+reset_msi_config:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='hunk'>@@ -708,6 +790,25 @@ static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)</div><div class='ctx'> 	pci_free_irq_vectors(ab_pci-&gt;pdev);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='add'>+static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci)</div><div class='add'>+{</div><div class='add'>+	struct msi_desc *msi_desc;</div><div class='add'>+</div><div class='add'>+	msi_desc = irq_get_msi_desc(ab_pci-&gt;pdev-&gt;irq);</div><div class='add'>+	if (!msi_desc) {</div><div class='add'>+		ath12k_err(ab_pci-&gt;ab, "msi_desc is NULL!\n");</div><div class='add'>+		pci_free_irq_vectors(ab_pci-&gt;pdev);</div><div class='add'>+		return -EINVAL;</div><div class='add'>+	}</div><div class='add'>+</div><div class='add'>+	ab_pci-&gt;msi_ep_base_data = msi_desc-&gt;msg.data;</div><div class='add'>+</div><div class='add'>+	ath12k_dbg(ab_pci-&gt;ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",</div><div class='add'>+		   ab_pci-&gt;msi_ep_base_data);</div><div class='add'>+</div><div class='add'>+	return 0;</div><div class='add'>+}</div><div class='add'>+</div><div class='ctx'> static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_base *ab = ab_pci-&gt;ab;</div><div class='hunk'>@@ -891,11 +992,11 @@ int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,</div><div class='ctx'> 	for (idx = 0; idx &lt; msi_config-&gt;total_users; idx++) {</div><div class='ctx'> 		if (strcmp(user_name, msi_config-&gt;users[idx].name) == 0) {</div><div class='ctx'> 			*num_vectors = msi_config-&gt;users[idx].num_vectors;</div><div class='del'>-			*user_base_data = msi_config-&gt;users[idx].base_vector</div><div class='del'>-				+ ab_pci-&gt;msi_ep_base_data;</div><div class='del'>-			*base_vector = msi_config-&gt;users[idx].base_vector;</div><div class='add'>+			*base_vector =  msi_config-&gt;users[idx].base_vector;</div><div class='add'>+			*user_base_data = *base_vector + ab_pci-&gt;msi_ep_base_data;</div><div class='ctx'> </div><div class='del'>-			ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",</div><div class='add'>+			ath12k_dbg(ab, ATH12K_DBG_PCI,</div><div class='add'>+				   "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",</div><div class='ctx'> 				   user_name, *num_vectors, *user_base_data,</div><div class='ctx'> 				   *base_vector);</div><div class='ctx'> </div><div class='hunk'>@@ -956,6 +1057,8 @@ void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)</div><div class='ctx'> {</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='add'>+	set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &amp;ab-&gt;dev_flags);</div><div class='add'>+</div><div class='ctx'> 	for (i = 0; i &lt; ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {</div><div class='ctx'> 		struct ath12k_ext_irq_grp *irq_grp = &amp;ab-&gt;ext_irq_grp[i];</div><div class='ctx'> </div><div class='hunk'>@@ -1000,7 +1103,10 @@ int ath12k_pci_start(struct ath12k_base *ab)</div><div class='ctx'> </div><div class='ctx'> 	set_bit(ATH12K_PCI_FLAG_INIT_DONE, &amp;ab_pci-&gt;flags);</div><div class='ctx'> </div><div class='del'>-	ath12k_pci_aspm_restore(ab_pci);</div><div class='add'>+	if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &amp;ab_pci-&gt;flags))</div><div class='add'>+		ath12k_pci_aspm_restore(ab_pci);</div><div class='add'>+	else</div><div class='add'>+		ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");</div><div class='ctx'> </div><div class='ctx'> 	ath12k_pci_ce_irqs_enable(ab);</div><div class='ctx'> 	ath12k_ce_rx_post_buf(ab);</div><div class='hunk'>@@ -1262,10 +1368,16 @@ static int ath12k_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 	if (ret)</div><div class='ctx'> 		goto err_pci_msi_free;</div><div class='ctx'> </div><div class='add'>+	ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));</div><div class='add'>+	if (ret) {</div><div class='add'>+		ath12k_err(ab, "failed to set irq affinity %d\n", ret);</div><div class='add'>+		goto err_pci_msi_free;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = ath12k_mhi_register(ab_pci);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ath12k_err(ab, "failed to register mhi: %d\n", ret);</div><div class='del'>-		goto err_pci_msi_free;</div><div class='add'>+		goto err_irq_affinity_cleanup;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	ret = ath12k_hal_srng_init(ab);</div><div class='hunk'>@@ -1286,6 +1398,17 @@ static int ath12k_pci_probe(struct pci_dev *pdev,</div><div class='ctx'> 		goto err_ce_free;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='add'>+	/* kernel may allocate a dummy vector before request_irq and</div><div class='add'>+	 * then allocate a real vector when request_irq is called.</div><div class='add'>+	 * So get msi_data here again to avoid spurious interrupt</div><div class='add'>+	 * as msi_data will configured to srngs.</div><div class='add'>+	 */</div><div class='add'>+	ret = ath12k_pci_config_msi_data(ab_pci);</div><div class='add'>+	if (ret) {</div><div class='add'>+		ath12k_err(ab, "failed to config msi_data: %d\n", ret);</div><div class='add'>+		goto err_free_irq;</div><div class='add'>+	}</div><div class='add'>+</div><div class='ctx'> 	ret = ath12k_core_init(ab);</div><div class='ctx'> 	if (ret) {</div><div class='ctx'> 		ath12k_err(ab, "failed to init core: %d\n", ret);</div><div class='hunk'>@@ -1308,6 +1431,9 @@ err_mhi_unregister:</div><div class='ctx'> err_pci_msi_free:</div><div class='ctx'> 	ath12k_pci_msi_free(ab_pci);</div><div class='ctx'> </div><div class='add'>+err_irq_affinity_cleanup:</div><div class='add'>+	ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);</div><div class='add'>+</div><div class='ctx'> err_pci_free_region:</div><div class='ctx'> 	ath12k_pci_free_region(ab_pci);</div><div class='ctx'> </div><div class='hunk'>@@ -1322,6 +1448,8 @@ static void ath12k_pci_remove(struct pci_dev *pdev)</div><div class='ctx'> 	struct ath12k_base *ab = pci_get_drvdata(pdev);</div><div class='ctx'> 	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> </div><div class='add'>+	ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);</div><div class='add'>+</div><div class='ctx'> 	if (test_bit(ATH12K_FLAG_QMI_FAIL, &amp;ab-&gt;dev_flags)) {</div><div class='ctx'> 		ath12k_pci_power_down(ab);</div><div class='ctx'> 		ath12k_qmi_deinit_service(ab);</div><div class='hunk'>@@ -1348,7 +1476,9 @@ qmi_fail:</div><div class='ctx'> static void ath12k_pci_shutdown(struct pci_dev *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath12k_base *ab = pci_get_drvdata(pdev);</div><div class='add'>+	struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);</div><div class='ctx'> </div><div class='add'>+	ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);</div><div class='ctx'> 	ath12k_pci_power_down(ab);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/pci.h b/drivers/net/wireless/ath/ath12k/pci.h<br/>index 0f24fd9395cd..b2edf32ada20 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/pci.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/pci.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/pci.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/pci.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef ATH12K_PCI_H</div><div class='ctx'> #define ATH12K_PCI_H</div><div class='hunk'>@@ -84,6 +84,7 @@ enum ath12k_pci_flags {</div><div class='ctx'> 	ATH12K_PCI_FLAG_INIT_DONE,</div><div class='ctx'> 	ATH12K_PCI_FLAG_IS_MSI_64,</div><div class='ctx'> 	ATH12K_PCI_ASPM_RESTORE,</div><div class='add'>+	ATH12K_PCI_FLAG_MULTI_MSI_VECTORS,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> struct ath12k_pci_ops {</div><div class='hunk'>@@ -108,6 +109,7 @@ struct ath12k_pci {</div><div class='ctx'> 	/* enum ath12k_pci_flags */</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u16 link_ctl;</div><div class='add'>+	unsigned long irq_flags;</div><div class='ctx'> 	const struct ath12k_pci_ops *pci_ops;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/peer.h b/drivers/net/wireless/ath/ath12k/peer.h<br/>index c6edb24cbedd..7b3500b5c8c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/peer.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/peer.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/peer.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/peer.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_PEER_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/qmi.c b/drivers/net/wireless/ath/ath12k/qmi.c<br/>index f6e949c618d0..77a132f6bbd1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/qmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/qmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/qmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/qmi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #include &lt;linux/elf.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/qmi.h b/drivers/net/wireless/ath/ath12k/qmi.h<br/>index e20d6511d1ca..e25bbaa125e8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/qmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/qmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/qmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/qmi.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_QMI_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/reg.c b/drivers/net/wireless/ath/ath12k/reg.c<br/>index 5c006256c82a..f924bc13ccff 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/reg.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/reg.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/reg.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/reg.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/rtnetlink.h&gt;</div><div class='ctx'> #include "core.h"</div><div class='hunk'>@@ -28,11 +28,11 @@ static const struct ieee80211_regdomain ath12k_world_regd = {</div><div class='ctx'> 	}</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-static bool ath12k_regdom_changes(struct ath12k *ar, char *alpha2)</div><div class='add'>+static bool ath12k_regdom_changes(struct ieee80211_hw *hw, char *alpha2)</div><div class='ctx'> {</div><div class='ctx'> 	const struct ieee80211_regdomain *regd;</div><div class='ctx'> </div><div class='del'>-	regd = rcu_dereference_rtnl(ar-&gt;hw-&gt;wiphy-&gt;regd);</div><div class='add'>+	regd = rcu_dereference_rtnl(hw-&gt;wiphy-&gt;regd);</div><div class='ctx'> 	/* This can happen during wiphy registration where the previous</div><div class='ctx'> 	 * user request is received before we update the regd received</div><div class='ctx'> 	 * from firmware.</div><div class='hunk'>@@ -71,7 +71,7 @@ ath12k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	if (!ath12k_regdom_changes(ar, request-&gt;alpha2)) {</div><div class='add'>+	if (!ath12k_regdom_changes(hw, request-&gt;alpha2)) {</div><div class='ctx'> 		ath12k_dbg(ar-&gt;ab, ATH12K_DBG_REG, "Country is already set\n");</div><div class='ctx'> 		return;</div><div class='ctx'> 	}</div><div class='hunk'>@@ -199,6 +199,7 @@ static void ath12k_copy_regd(struct ieee80211_regdomain *regd_orig,</div><div class='ctx'> </div><div class='ctx'> int ath12k_regd_update(struct ath12k *ar, bool init)</div><div class='ctx'> {</div><div class='add'>+	struct ieee80211_hw *hw = ar-&gt;hw;</div><div class='ctx'> 	struct ieee80211_regdomain *regd, *regd_copy = NULL;</div><div class='ctx'> 	int ret, regd_len, pdev_id;</div><div class='ctx'> 	struct ath12k_base *ab;</div><div class='hunk'>@@ -246,9 +247,9 @@ int ath12k_regd_update(struct ath12k *ar, bool init)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	rtnl_lock();</div><div class='del'>-	wiphy_lock(ar-&gt;hw-&gt;wiphy);</div><div class='del'>-	ret = regulatory_set_wiphy_regd_sync(ar-&gt;hw-&gt;wiphy, regd_copy);</div><div class='del'>-	wiphy_unlock(ar-&gt;hw-&gt;wiphy);</div><div class='add'>+	wiphy_lock(hw-&gt;wiphy);</div><div class='add'>+	ret = regulatory_set_wiphy_regd_sync(hw-&gt;wiphy, regd_copy);</div><div class='add'>+	wiphy_unlock(hw-&gt;wiphy);</div><div class='ctx'> 	rtnl_unlock();</div><div class='ctx'> </div><div class='ctx'> 	kfree(regd_copy);</div><div class='hunk'>@@ -729,10 +730,10 @@ void ath12k_regd_update_work(struct work_struct *work)</div><div class='ctx'> 	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-void ath12k_reg_init(struct ath12k *ar)</div><div class='add'>+void ath12k_reg_init(struct ieee80211_hw *hw)</div><div class='ctx'> {</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED;</div><div class='del'>-	ar-&gt;hw-&gt;wiphy-&gt;reg_notifier = ath12k_reg_notifier;</div><div class='add'>+	hw-&gt;wiphy-&gt;regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED;</div><div class='add'>+	hw-&gt;wiphy-&gt;reg_notifier = ath12k_reg_notifier;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> void ath12k_reg_free(struct ath12k_base *ab)</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/reg.h b/drivers/net/wireless/ath/ath12k/reg.h<br/>index 35569f03042d..29c7ec3260da 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/reg.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/reg.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/reg.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/reg.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_REG_H</div><div class='hunk'>@@ -89,7 +89,7 @@ enum ath12k_reg_phy_bitmap {</div><div class='ctx'> 	ATH12K_REG_PHY_BITMAP_NO11BE	= BIT(6),</div><div class='ctx'> };</div><div class='ctx'> </div><div class='del'>-void ath12k_reg_init(struct ath12k *ar);</div><div class='add'>+void ath12k_reg_init(struct ieee80211_hw *hw);</div><div class='ctx'> void ath12k_reg_free(struct ath12k_base *ab);</div><div class='ctx'> void ath12k_regd_update_work(struct work_struct *work);</div><div class='ctx'> struct ieee80211_regdomain *ath12k_reg_build_regd(struct ath12k_base *ab,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/rx_desc.h b/drivers/net/wireless/ath/ath12k/rx_desc.h<br/>index c4058abc516e..55f20c446ca9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/rx_desc.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/rx_desc.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/rx_desc.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/rx_desc.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #ifndef ATH12K_RX_DESC_H</div><div class='ctx'> #define ATH12K_RX_DESC_H</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/wmi.c b/drivers/net/wireless/ath/ath12k/wmi.c<br/>index 0e5bf5ce8d4c..11cc3005c0f9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/wmi.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/wmi.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/wmi.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/wmi.c</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> // SPDX-License-Identifier: BSD-3-Clause-Clear</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> #include &lt;linux/skbuff.h&gt;</div><div class='ctx'> #include &lt;linux/ctype.h&gt;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath12k/wmi.h b/drivers/net/wireless/ath/ath12k/wmi.h<br/>index 629373d67421..06e5b9b4049b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/wmi.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath12k/wmi.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath12k/wmi.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath12k/wmi.h</a></div><div class='hunk'>@@ -1,7 +1,7 @@</div><div class='ctx'> /* SPDX-License-Identifier: BSD-3-Clause-Clear */</div><div class='ctx'> /*</div><div class='ctx'>  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.</div><div class='del'>- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='add'>+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.</div><div class='ctx'>  */</div><div class='ctx'> </div><div class='ctx'> #ifndef ATH12K_WMI_H</div><div class='hunk'>@@ -1146,25 +1146,27 @@ enum wmi_tlv_vdev_param {</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum wmi_tlv_peer_flags {</div><div class='del'>-	WMI_TLV_PEER_AUTH = 0x00000001,</div><div class='del'>-	WMI_TLV_PEER_QOS = 0x00000002,</div><div class='del'>-	WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004,</div><div class='del'>-	WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010,</div><div class='del'>-	WMI_TLV_PEER_APSD = 0x00000800,</div><div class='del'>-	WMI_TLV_PEER_HT = 0x00001000,</div><div class='del'>-	WMI_TLV_PEER_40MHZ = 0x00002000,</div><div class='del'>-	WMI_TLV_PEER_STBC = 0x00008000,</div><div class='del'>-	WMI_TLV_PEER_LDPC = 0x00010000,</div><div class='del'>-	WMI_TLV_PEER_DYN_MIMOPS = 0x00020000,</div><div class='del'>-	WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000,</div><div class='del'>-	WMI_TLV_PEER_SPATIAL_MUX = 0x00200000,</div><div class='del'>-	WMI_TLV_PEER_VHT = 0x02000000,</div><div class='del'>-	WMI_TLV_PEER_80MHZ = 0x04000000,</div><div class='del'>-	WMI_TLV_PEER_PMF = 0x08000000,</div><div class='add'>+	WMI_PEER_AUTH		= 0x00000001,</div><div class='add'>+	WMI_PEER_QOS		= 0x00000002,</div><div class='add'>+	WMI_PEER_NEED_PTK_4_WAY	= 0x00000004,</div><div class='add'>+	WMI_PEER_NEED_GTK_2_WAY	= 0x00000010,</div><div class='add'>+	WMI_PEER_HE		= 0x00000400,</div><div class='add'>+	WMI_PEER_APSD		= 0x00000800,</div><div class='add'>+	WMI_PEER_HT		= 0x00001000,</div><div class='add'>+	WMI_PEER_40MHZ		= 0x00002000,</div><div class='add'>+	WMI_PEER_STBC		= 0x00008000,</div><div class='add'>+	WMI_PEER_LDPC		= 0x00010000,</div><div class='add'>+	WMI_PEER_DYN_MIMOPS	= 0x00020000,</div><div class='add'>+	WMI_PEER_STATIC_MIMOPS	= 0x00040000,</div><div class='add'>+	WMI_PEER_SPATIAL_MUX	= 0x00200000,</div><div class='add'>+	WMI_PEER_TWT_REQ	= 0x00400000,</div><div class='add'>+	WMI_PEER_TWT_RESP	= 0x00800000,</div><div class='add'>+	WMI_PEER_VHT		= 0x02000000,</div><div class='add'>+	WMI_PEER_80MHZ		= 0x04000000,</div><div class='add'>+	WMI_PEER_PMF		= 0x08000000,</div><div class='ctx'> 	WMI_PEER_IS_P2P_CAPABLE = 0x20000000,</div><div class='ctx'> 	WMI_PEER_160MHZ         = 0x40000000,</div><div class='ctx'> 	WMI_PEER_SAFEMODE_EN    = 0x80000000,</div><div class='del'>-</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum wmi_tlv_peer_flags_ext {</div><div class='hunk'>@@ -2220,6 +2222,7 @@ enum wmi_peer_chwidth {</div><div class='ctx'> 	WMI_PEER_CHWIDTH_40MHZ = 1,</div><div class='ctx'> 	WMI_PEER_CHWIDTH_80MHZ = 2,</div><div class='ctx'> 	WMI_PEER_CHWIDTH_160MHZ = 3,</div><div class='add'>+	WMI_PEER_CHWIDTH_320MHZ = 4,</div><div class='ctx'> };</div><div class='ctx'> </div><div class='ctx'> enum wmi_beacon_gen_mode {</div><div class='hunk'>@@ -3844,31 +3847,6 @@ struct wmi_unit_test_cmd {</div><div class='ctx'> </div><div class='ctx'> #define MAX_SUPPORTED_RATES 128</div><div class='ctx'> </div><div class='del'>-#define WMI_PEER_AUTH		0x00000001</div><div class='del'>-#define WMI_PEER_QOS		0x00000002</div><div class='del'>-#define WMI_PEER_NEED_PTK_4_WAY	0x00000004</div><div class='del'>-#define WMI_PEER_NEED_GTK_2_WAY	0x00000010</div><div class='del'>-#define WMI_PEER_HE		0x00000400</div><div class='del'>-#define WMI_PEER_APSD		0x00000800</div><div class='del'>-#define WMI_PEER_HT		0x00001000</div><div class='del'>-#define WMI_PEER_40MHZ		0x00002000</div><div class='del'>-#define WMI_PEER_STBC		0x00008000</div><div class='del'>-#define WMI_PEER_LDPC		0x00010000</div><div class='del'>-#define WMI_PEER_DYN_MIMOPS	0x00020000</div><div class='del'>-#define WMI_PEER_STATIC_MIMOPS	0x00040000</div><div class='del'>-#define WMI_PEER_SPATIAL_MUX	0x00200000</div><div class='del'>-#define WMI_PEER_TWT_REQ	0x00400000</div><div class='del'>-#define WMI_PEER_TWT_RESP	0x00800000</div><div class='del'>-#define WMI_PEER_VHT		0x02000000</div><div class='del'>-#define WMI_PEER_80MHZ		0x04000000</div><div class='del'>-#define WMI_PEER_PMF		0x08000000</div><div class='del'>-/* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000.</div><div class='del'>- * Need to be cleaned up</div><div class='del'>- */</div><div class='del'>-#define WMI_PEER_IS_P2P_CAPABLE	0x20000000</div><div class='del'>-#define WMI_PEER_160MHZ		0x40000000</div><div class='del'>-#define WMI_PEER_SAFEMODE_EN	0x80000000</div><div class='del'>-</div><div class='ctx'> struct ath12k_wmi_vht_rate_set_params {</div><div class='ctx'> 	__le32 tlv_header;</div><div class='ctx'> 	__le32 rx_max_rate;</div><div class='hunk'>@@ -4770,7 +4748,6 @@ struct wmi_probe_tmpl_cmd {</div><div class='ctx'> struct ath12k_wmi_pdev {</div><div class='ctx'> 	struct ath12k_wmi_base *wmi_ab;</div><div class='ctx'> 	enum ath12k_htc_ep_id eid;</div><div class='del'>-	const struct wmi_peer_flags_map *peer_flags;</div><div class='ctx'> 	u32 rx_decap_mode;</div><div class='ctx'> };</div><div class='ctx'> </div><div class='hunk'>@@ -4784,7 +4761,6 @@ struct ath12k_wmi_base {</div><div class='ctx'> 	struct completion unified_ready;</div><div class='ctx'> 	DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);</div><div class='ctx'> 	wait_queue_head_t tx_credits_wq;</div><div class='del'>-	const struct wmi_peer_flags_map *peer_flags;</div><div class='ctx'> 	u32 num_mem_chunks;</div><div class='ctx'> 	u32 rx_decap_mode;</div><div class='ctx'> 	struct ath12k_wmi_host_mem_chunk_arg mem_chunks[WMI_MAX_MEM_REQS];</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c<br/>index 08bd5d3b00f1..f27308ccb2f1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath5k/ahb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath5k/ahb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath5k/ahb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath5k/ahb.c</a></div><div class='hunk'>@@ -185,7 +185,7 @@ static int ath_ahb_probe(struct platform_device *pdev)</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int ath_ahb_remove(struct platform_device *pdev)</div><div class='add'>+static void ath_ahb_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ar231x_board_config *bcfg = dev_get_platdata(&amp;pdev-&gt;dev);</div><div class='ctx'> 	struct ieee80211_hw *hw = platform_get_drvdata(pdev);</div><div class='hunk'>@@ -193,7 +193,7 @@ static int ath_ahb_remove(struct platform_device *pdev)</div><div class='ctx'> 	u32 reg;</div><div class='ctx'> </div><div class='ctx'> 	if (!hw)</div><div class='del'>-		return 0;</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='ctx'> 	ah = hw-&gt;priv;</div><div class='ctx'> </div><div class='hunk'>@@ -215,13 +215,11 @@ static int ath_ahb_remove(struct platform_device *pdev)</div><div class='ctx'> 	ath5k_deinit_ah(ah);</div><div class='ctx'> 	iounmap(ah-&gt;iobase);</div><div class='ctx'> 	ieee80211_free_hw(hw);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver ath_ahb_driver = {</div><div class='ctx'> 	.probe      = ath_ahb_probe,</div><div class='del'>-	.remove     = ath_ahb_remove,</div><div class='add'>+	.remove_new = ath_ahb_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= "ar231x-wmac",</div><div class='ctx'> 	},</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h<br/>index 693296ee9693..e85b713950b1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath5k/eeprom.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath5k/eeprom.h</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath5k/eeprom.h?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath5k/eeprom.h</a></div><div class='hunk'>@@ -489,7 +489,4 @@ struct ath5k_eeprom_info {</div><div class='ctx'> </div><div class='ctx'> 	/* Spur mitigation data (fbin values for spur channels) */</div><div class='ctx'> 	u16	ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];</div><div class='del'>-</div><div class='del'>-	/* Antenna raw switch tables */</div><div class='del'>-	u32	ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];</div><div class='ctx'> };</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig<br/>index e150d82eddb6..0c47be06c153 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/Kconfig</a></div><div class='hunk'>@@ -57,8 +57,7 @@ config ATH9K_AHB</div><div class='ctx'> </div><div class='ctx'> config ATH9K_DEBUGFS</div><div class='ctx'> 	bool "Atheros ath9k debugging"</div><div class='del'>-	depends on ATH9K &amp;&amp; DEBUG_FS</div><div class='del'>-	select MAC80211_DEBUGFS</div><div class='add'>+	depends on ATH9K &amp;&amp; DEBUG_FS &amp;&amp; MAC80211_DEBUGFS</div><div class='ctx'> 	select ATH9K_COMMON_DEBUG</div><div class='ctx'> 	help</div><div class='ctx'> 	  Say Y, if you need access to ath9k's statistics for</div><div class='hunk'>@@ -70,7 +69,6 @@ config ATH9K_DEBUGFS</div><div class='ctx'> config ATH9K_STATION_STATISTICS</div><div class='ctx'> 	bool "Detailed station statistics"</div><div class='ctx'> 	depends on ATH9K &amp;&amp; ATH9K_DEBUGFS &amp;&amp; DEBUG_FS</div><div class='del'>-	select MAC80211_DEBUGFS</div><div class='ctx'> 	default n</div><div class='ctx'> 	help</div><div class='ctx'> 	  This option enables detailed statistics for association stations.</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c b/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c<br/>index 708c8969b503..a5eb43f30320 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c</a></div><div class='hunk'>@@ -125,7 +125,7 @@ static void owl_rescan(struct pci_dev *pdev)</div><div class='ctx'> </div><div class='ctx'> static void owl_fw_cb(const struct firmware *fw, void *context)</div><div class='ctx'> {</div><div class='del'>-	struct owl_ctx *ctx = (struct owl_ctx *)context;</div><div class='add'>+	struct owl_ctx *ctx = context;</div><div class='ctx'> </div><div class='ctx'> 	complete(&amp;ctx-&gt;eeprom_load);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/common-init.c b/drivers/net/wireless/ath/ath9k/common-init.c<br/>index 82de0fadbc95..7c13a1deb3ac 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/common-init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/common-init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/common-init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/common-init.c</a></div><div class='hunk'>@@ -124,7 +124,7 @@ static struct ieee80211_rate ath9k_legacy_rates[] = {</div><div class='ctx'> </div><div class='ctx'> int ath9k_cmn_init_channels_rates(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	struct ath_hw *ah = (struct ath_hw *)common-&gt;ah;</div><div class='add'>+	struct ath_hw *ah = common-&gt;ah;</div><div class='ctx'> 	void *channels;</div><div class='ctx'> </div><div class='ctx'> 	BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/common-spectral.c b/drivers/net/wireless/ath/ath9k/common-spectral.c<br/>index a5349c72c332..4b27445a5fb8 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/common-spectral.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/common-spectral.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/common-spectral.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/common-spectral.c</a></div><div class='hunk'>@@ -471,7 +471,7 @@ int ath_cmn_process_fft(struct ath_spec_scan_priv *spec_priv, struct ieee80211_h</div><div class='ctx'> 	u8 sample_buf[SPECTRAL_SAMPLE_MAX_LEN] = {0};</div><div class='ctx'> 	struct ath_hw *ah = spec_priv-&gt;ah;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(spec_priv-&gt;ah);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *)common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	u8 num_bins, *vdata = (u8 *)hdr;</div><div class='ctx'> 	struct ath_radar_info *radar_info;</div><div class='ctx'> 	int len = rs-&gt;rs_datalen;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c<br/>index a0376a6787b8..d84e3ee7b5d9 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/debug.c</a></div><div class='hunk'>@@ -1376,7 +1376,7 @@ void ath9k_deinit_debug(struct ath_softc *sc)</div><div class='ctx'> int ath9k_init_debug(struct ath_hw *ah)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	sc-&gt;debug.debugfs_phy = debugfs_create_dir("ath9k",</div><div class='ctx'> 						   sc-&gt;hw-&gt;wiphy-&gt;debugfsdir);</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c<br/>index 90cfe39aa433..0c7841f95228 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/hif_usb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/hif_usb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/hif_usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/hif_usb.c</a></div><div class='hunk'>@@ -70,7 +70,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev);</div><div class='ctx'> </div><div class='ctx'> static void hif_usb_regout_cb(struct urb *urb)</div><div class='ctx'> {</div><div class='del'>-	struct cmd_buf *cmd = (struct cmd_buf *)urb-&gt;context;</div><div class='add'>+	struct cmd_buf *cmd = urb-&gt;context;</div><div class='ctx'> </div><div class='ctx'> 	switch (urb-&gt;status) {</div><div class='ctx'> 	case 0:</div><div class='hunk'>@@ -134,7 +134,7 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,</div><div class='ctx'> </div><div class='ctx'> static void hif_usb_mgmt_cb(struct urb *urb)</div><div class='ctx'> {</div><div class='del'>-	struct cmd_buf *cmd = (struct cmd_buf *)urb-&gt;context;</div><div class='add'>+	struct cmd_buf *cmd = urb-&gt;context;</div><div class='ctx'> 	struct hif_device_usb *hif_dev;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	bool txok = true;</div><div class='hunk'>@@ -252,7 +252,7 @@ static inline void ath9k_skb_queue_complete(struct hif_device_usb *hif_dev,</div><div class='ctx'> </div><div class='ctx'> static void hif_usb_tx_cb(struct urb *urb)</div><div class='ctx'> {</div><div class='del'>-	struct tx_buf *tx_buf = (struct tx_buf *) urb-&gt;context;</div><div class='add'>+	struct tx_buf *tx_buf = urb-&gt;context;</div><div class='ctx'> 	struct hif_device_usb *hif_dev;</div><div class='ctx'> 	bool txok = true;</div><div class='ctx'> </div><div class='hunk'>@@ -687,7 +687,7 @@ invalid_pkt:</div><div class='ctx'> </div><div class='ctx'> static void ath9k_hif_usb_rx_cb(struct urb *urb)</div><div class='ctx'> {</div><div class='del'>-	struct rx_buf *rx_buf = (struct rx_buf *)urb-&gt;context;</div><div class='add'>+	struct rx_buf *rx_buf = urb-&gt;context;</div><div class='ctx'> 	struct hif_device_usb *hif_dev = rx_buf-&gt;hif_dev;</div><div class='ctx'> 	struct sk_buff *skb = rx_buf-&gt;skb;</div><div class='ctx'> 	int ret;</div><div class='hunk'>@@ -734,7 +734,7 @@ free:</div><div class='ctx'> </div><div class='ctx'> static void ath9k_hif_usb_reg_in_cb(struct urb *urb)</div><div class='ctx'> {</div><div class='del'>-	struct rx_buf *rx_buf = (struct rx_buf *)urb-&gt;context;</div><div class='add'>+	struct rx_buf *rx_buf = urb-&gt;context;</div><div class='ctx'> 	struct hif_device_usb *hif_dev = rx_buf-&gt;hif_dev;</div><div class='ctx'> 	struct sk_buff *skb = rx_buf-&gt;skb;</div><div class='ctx'> 	int ret;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c<br/>index 278ddc713fdc..f7c6d9bc9311 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_debug.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/htc_drv_debug.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_debug.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_debug.c</a></div><div class='hunk'>@@ -482,7 +482,7 @@ void ath9k_htc_deinit_debug(struct ath9k_htc_priv *priv)</div><div class='ctx'> int ath9k_htc_init_debug(struct ath_hw *ah)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	priv-&gt;debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME,</div><div class='ctx'> 					     priv-&gt;hw-&gt;wiphy-&gt;debugfsdir);</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c<br/>index dae3d9c7b640..0aa5bdeb44a1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/htc_drv_init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_init.c</a></div><div class='hunk'>@@ -63,12 +63,12 @@ static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {</div><div class='ctx'> </div><div class='ctx'> static void ath9k_htc_op_ps_wakeup(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	ath9k_htc_ps_wakeup((struct ath9k_htc_priv *) common-&gt;priv);</div><div class='add'>+	ath9k_htc_ps_wakeup(common-&gt;priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath9k_htc_op_ps_restore(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	ath9k_htc_ps_restore((struct ath9k_htc_priv *) common-&gt;priv);</div><div class='add'>+	ath9k_htc_ps_restore(common-&gt;priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ath_ps_ops ath9k_htc_ps_ops = {</div><div class='hunk'>@@ -235,7 +235,7 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	__be32 val, reg = cpu_to_be32(reg_offset);</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -257,7 +257,7 @@ static void ath9k_multi_regread(void *hw_priv, u32 *addr,</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	__be32 tmpaddr[8];</div><div class='ctx'> 	__be32 tmpval[8];</div><div class='ctx'> 	int i, ret;</div><div class='hunk'>@@ -282,7 +282,7 @@ static void ath9k_multi_regread(void *hw_priv, u32 *addr,</div><div class='ctx'> </div><div class='ctx'> static void ath9k_regwrite_multi(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	u32 rsp_status;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -303,7 +303,7 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	const __be32 buf[2] = {</div><div class='ctx'> 		cpu_to_be32(reg_offset),</div><div class='ctx'> 		cpu_to_be32(val),</div><div class='hunk'>@@ -324,7 +324,7 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	mutex_lock(&amp;priv-&gt;wmi-&gt;multi_write_mutex);</div><div class='ctx'> </div><div class='hunk'>@@ -347,7 +347,7 @@ static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	if (atomic_read(&amp;priv-&gt;wmi-&gt;mwrite_cnt))</div><div class='ctx'> 		ath9k_regwrite_buffer(hw_priv, val, reg_offset);</div><div class='hunk'>@@ -359,7 +359,7 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	atomic_inc(&amp;priv-&gt;wmi-&gt;mwrite_cnt);</div><div class='ctx'> }</div><div class='hunk'>@@ -368,7 +368,7 @@ static void ath9k_regwrite_flush(void *hw_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	atomic_dec(&amp;priv-&gt;wmi-&gt;mwrite_cnt);</div><div class='ctx'> </div><div class='hunk'>@@ -385,7 +385,7 @@ static void ath9k_reg_rmw_buffer(void *hw_priv,</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	u32 rsp_status;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -423,7 +423,7 @@ static void ath9k_reg_rmw_flush(void *hw_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	u32 rsp_status;</div><div class='ctx'> 	int r;</div><div class='ctx'> </div><div class='hunk'>@@ -455,7 +455,7 @@ static void ath9k_enable_rmw_buffer(void *hw_priv)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(HTC_FWFLAG_NO_RMW, &amp;priv-&gt;fw_flags))</div><div class='ctx'> 		return;</div><div class='hunk'>@@ -468,7 +468,7 @@ static void ath9k_reg_rmw_single(void *hw_priv,</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> 	struct register_rmw buf, buf_ret;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='hunk'>@@ -490,7 +490,7 @@ static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common-&gt;priv;</div><div class='add'>+	struct ath9k_htc_priv *priv = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	if (test_bit(HTC_FWFLAG_NO_RMW, &amp;priv-&gt;fw_flags)) {</div><div class='ctx'> 		u32 val;</div><div class='hunk'>@@ -518,7 +518,7 @@ static void ath_usb_read_cachesize(struct ath_common *common, int *csz)</div><div class='ctx'> </div><div class='ctx'> static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)</div><div class='ctx'> {</div><div class='del'>-	struct ath_hw *ah = (struct ath_hw *) common-&gt;ah;</div><div class='add'>+	struct ath_hw *ah = common-&gt;ah;</div><div class='ctx'> </div><div class='ctx'> 	(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off &lt;&lt; AR5416_EEPROM_S));</div><div class='ctx'> </div><div class='hunk'>@@ -970,7 +970,7 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,</div><div class='ctx'> </div><div class='ctx'> err_init:</div><div class='ctx'> 	ath9k_stop_wmi(priv);</div><div class='del'>-	hif_dev = (struct hif_device_usb *)htc_handle-&gt;hif_dev;</div><div class='add'>+	hif_dev = htc_handle-&gt;hif_dev;</div><div class='ctx'> 	ath9k_hif_usb_dealloc_urbs(hif_dev);</div><div class='ctx'> 	ath9k_destroy_wmi(priv);</div><div class='ctx'> err_free:</div><div class='hunk'>@@ -988,7 +988,7 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)</div><div class='ctx'> </div><div class='ctx'> 		ath9k_deinit_device(htc_handle-&gt;drv_priv);</div><div class='ctx'> 		ath9k_stop_wmi(htc_handle-&gt;drv_priv);</div><div class='del'>-		ath9k_hif_usb_dealloc_urbs((struct hif_device_usb *)htc_handle-&gt;hif_dev);</div><div class='add'>+		ath9k_hif_usb_dealloc_urbs(htc_handle-&gt;hif_dev);</div><div class='ctx'> 		ath9k_destroy_wmi(htc_handle-&gt;drv_priv);</div><div class='ctx'> 		ieee80211_free_hw(htc_handle-&gt;drv_priv-&gt;hw);</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c<br/>index 800177021baf..efcaeccb055a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/htc_drv_txrx.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_drv_txrx.c</a></div><div class='hunk'>@@ -652,9 +652,10 @@ void ath9k_htc_txstatus(struct ath9k_htc_priv *priv, void *wmi_event)</div><div class='ctx'> 	struct ath9k_htc_tx_event *tx_pend;</div><div class='ctx'> 	int i;</div><div class='ctx'> </div><div class='del'>-	for (i = 0; i &lt; txs-&gt;cnt; i++) {</div><div class='del'>-		WARN_ON(txs-&gt;cnt &gt; HTC_MAX_TX_STATUS);</div><div class='add'>+	if (WARN_ON_ONCE(txs-&gt;cnt &gt; HTC_MAX_TX_STATUS))</div><div class='add'>+		return;</div><div class='ctx'> </div><div class='add'>+	for (i = 0; i &lt; txs-&gt;cnt; i++) {</div><div class='ctx'> 		__txs = &amp;txs-&gt;txstatus[i];</div><div class='ctx'> </div><div class='ctx'> 		skb = ath9k_htc_tx_get_packet(priv, __txs);</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c<br/>index 99667aba289d..eb631fd3336d 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_hst.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/htc_hst.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/htc_hst.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/htc_hst.c</a></div><div class='hunk'>@@ -89,7 +89,7 @@ static void htc_process_target_rdy(struct htc_target *target,</div><div class='ctx'> 				   void *buf)</div><div class='ctx'> {</div><div class='ctx'> 	struct htc_endpoint *endpoint;</div><div class='del'>-	struct htc_ready_msg *htc_ready_msg = (struct htc_ready_msg *) buf;</div><div class='add'>+	struct htc_ready_msg *htc_ready_msg = buf;</div><div class='ctx'> </div><div class='ctx'> 	target-&gt;credit_size = be16_to_cpu(htc_ready_msg-&gt;credit_size);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c<br/>index 4f00400c7ffb..7fad7e75af6a 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/init.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/init.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/init.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/init.c</a></div><div class='hunk'>@@ -151,12 +151,12 @@ static void ath9k_deinit_softc(struct ath_softc *sc);</div><div class='ctx'> </div><div class='ctx'> static void ath9k_op_ps_wakeup(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	ath9k_ps_wakeup((struct ath_softc *) common-&gt;priv);</div><div class='add'>+	ath9k_ps_wakeup(common-&gt;priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath9k_op_ps_restore(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	ath9k_ps_restore((struct ath_softc *) common-&gt;priv);</div><div class='add'>+	ath9k_ps_restore(common-&gt;priv);</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct ath_ps_ops ath9k_ps_ops = {</div><div class='hunk'>@@ -174,7 +174,7 @@ static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> </div><div class='ctx'> 	if (NR_CPUS &gt; 1 &amp;&amp; ah-&gt;config.serialize_regmode == SER_REG_MODE_ON) {</div><div class='ctx'> 		unsigned long flags;</div><div class='hunk'>@@ -189,7 +189,7 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='ctx'> 	if (NR_CPUS &gt; 1 &amp;&amp; ah-&gt;config.serialize_regmode == SER_REG_MODE_ON) {</div><div class='hunk'>@@ -229,7 +229,7 @@ static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 cl</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_hw *ah = hw_priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(ah);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	unsigned long flags;</div><div class='ctx'> 	u32 val;</div><div class='ctx'> </div><div class='hunk'>@@ -608,7 +608,7 @@ static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* devres manages the calibration values release on shutdown */</div><div class='del'>-	ah-&gt;nvmem_blob = (u16 *)devm_kmemdup(sc-&gt;dev, buf, len, GFP_KERNEL);</div><div class='add'>+	ah-&gt;nvmem_blob = devm_kmemdup(sc-&gt;dev, buf, len, GFP_KERNEL);</div><div class='ctx'> 	kfree(buf);</div><div class='ctx'> 	if (!ah-&gt;nvmem_blob)</div><div class='ctx'> 		return -ENOMEM;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c<br/>index 9d84003db800..d1e5767aab3c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/link.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/link.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/link.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/link.c</a></div><div class='hunk'>@@ -304,7 +304,7 @@ fail_paprd:</div><div class='ctx'> void ath_ani_calibrate(struct timer_list *t)</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_common *common = from_timer(common, t, ani.timer);</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *)common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	struct ath_hw *ah = sc-&gt;sc_ah;</div><div class='ctx'> 	bool longcal = false;</div><div class='ctx'> 	bool shortcal = false;</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c<br/>index 1494feedb27d..c48ff0ffbfef 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/main.c</a></div><div class='hunk'>@@ -2383,7 +2383,22 @@ static void ath9k_sw_scan_start(struct ieee80211_hw *hw,</div><div class='ctx'> {</div><div class='ctx'> 	struct ath_softc *sc = hw-&gt;priv;</div><div class='ctx'> 	struct ath_common *common = ath9k_hw_common(sc-&gt;sc_ah);</div><div class='add'>+	struct cfg80211_chan_def *chandef = &amp;sc-&gt;cur_chan-&gt;chandef;</div><div class='add'>+	struct ieee80211_channel *chan = chandef-&gt;chan;</div><div class='add'>+	int pos = chan-&gt;hw_value;</div><div class='ctx'> 	set_bit(ATH_OP_SCANNING, &amp;common-&gt;op_flags);</div><div class='add'>+</div><div class='add'>+	/* Reset current survey */</div><div class='add'>+	if (!sc-&gt;cur_chan-&gt;offchannel) {</div><div class='add'>+		if (sc-&gt;cur_survey != &amp;sc-&gt;survey[pos]) {</div><div class='add'>+			if (sc-&gt;cur_survey)</div><div class='add'>+				sc-&gt;cur_survey-&gt;filled &amp;= ~SURVEY_INFO_IN_USE;</div><div class='add'>+			sc-&gt;cur_survey = &amp;sc-&gt;survey[pos];</div><div class='add'>+		}</div><div class='add'>+</div><div class='add'>+		memset(sc-&gt;cur_survey, 0, sizeof(struct survey_info));</div><div class='add'>+		sc-&gt;cur_survey-&gt;filled |= SURVEY_INFO_IN_USE;</div><div class='add'>+	}</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,</div><div class='head'>diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c<br/>index 0633589b85c2..e655cd8bbf94 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/ath9k/pci.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/ath9k/pci.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/ath9k/pci.c</a></div><div class='hunk'>@@ -781,7 +781,7 @@ static const struct pci_device_id ath_pci_id_table[] = {</div><div class='ctx'> /* return bus cachesize in 4B word units */</div><div class='ctx'> static void ath_pci_read_cachesize(struct ath_common *common, int *csz)</div><div class='ctx'> {</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	u8 u8tmp;</div><div class='ctx'> </div><div class='ctx'> 	pci_read_config_byte(to_pci_dev(sc-&gt;dev), PCI_CACHE_LINE_SIZE, &amp;u8tmp);</div><div class='hunk'>@@ -799,7 +799,7 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)</div><div class='ctx'> </div><div class='ctx'> static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)</div><div class='ctx'> {</div><div class='del'>-	struct ath_hw *ah = (struct ath_hw *) common-&gt;ah;</div><div class='add'>+	struct ath_hw *ah = common-&gt;ah;</div><div class='ctx'> </div><div class='ctx'> 	common-&gt;ops-&gt;read(ah, AR5416_EEPROM_OFFSET + (off &lt;&lt; AR5416_EEPROM_S));</div><div class='ctx'> </div><div class='hunk'>@@ -820,7 +820,7 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)</div><div class='ctx'> /* Need to be called after we discover btcoex capabilities */</div><div class='ctx'> static void ath_pci_aspm_init(struct ath_common *common)</div><div class='ctx'> {</div><div class='del'>-	struct ath_softc *sc = (struct ath_softc *) common-&gt;priv;</div><div class='add'>+	struct ath_softc *sc = common-&gt;priv;</div><div class='ctx'> 	struct ath_hw *ah = sc-&gt;sc_ah;</div><div class='ctx'> 	struct pci_dev *pdev = to_pci_dev(sc-&gt;dev);</div><div class='ctx'> 	struct pci_dev *parent;</div><div class='head'>diff --git a/drivers/net/wireless/ath/wcn36xx/main.c b/drivers/net/wireless/ath/wcn36xx/main.c<br/>index 2bd1163177f0..41119fb177e3 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/wcn36xx/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/ath/wcn36xx/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/ath/wcn36xx/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/ath/wcn36xx/main.c</a></div><div class='hunk'>@@ -1644,7 +1644,7 @@ out_err:</div><div class='ctx'> 	return ret;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int wcn36xx_remove(struct platform_device *pdev)</div><div class='add'>+static void wcn36xx_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	struct ieee80211_hw *hw = platform_get_drvdata(pdev);</div><div class='ctx'> 	struct wcn36xx *wcn = hw-&gt;priv;</div><div class='hunk'>@@ -1666,8 +1666,6 @@ static int wcn36xx_remove(struct platform_device *pdev)</div><div class='ctx'> </div><div class='ctx'> 	mutex_destroy(&amp;wcn-&gt;hal_mutex);</div><div class='ctx'> 	ieee80211_free_hw(hw);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static const struct of_device_id wcn36xx_of_match[] = {</div><div class='hunk'>@@ -1678,7 +1676,7 @@ MODULE_DEVICE_TABLE(of, wcn36xx_of_match);</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver wcn36xx_driver = {</div><div class='ctx'> 	.probe      = wcn36xx_probe,</div><div class='del'>-	.remove     = wcn36xx_remove,</div><div class='add'>+	.remove_new = wcn36xx_remove,</div><div class='ctx'> 	.driver         = {</div><div class='ctx'> 		.name   = "wcn36xx",</div><div class='ctx'> 		.of_match_table = wcn36xx_of_match,</div><div class='head'>diff --git a/drivers/net/wireless/atmel/Kconfig b/drivers/net/wireless/atmel/Kconfig<br/>index bafdd57b049a..7a2bb7a58ab7 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/Kconfig</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/Kconfig?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/Kconfig</a></div><div class='hunk'>@@ -12,41 +12,6 @@ config WLAN_VENDOR_ATMEL</div><div class='ctx'> </div><div class='ctx'> if WLAN_VENDOR_ATMEL</div><div class='ctx'> </div><div class='del'>-config ATMEL</div><div class='del'>-	tristate "Atmel at76c50x chipset  802.11b support"</div><div class='del'>-	depends on CFG80211 &amp;&amp; (PCI || PCMCIA) &amp;&amp; HAS_IOPORT</div><div class='del'>-	select WIRELESS_EXT</div><div class='del'>-	select WEXT_PRIV</div><div class='del'>-	select FW_LOADER</div><div class='del'>-	select CRC32</div><div class='del'>-	help</div><div class='del'>-	  A driver 802.11b wireless cards based on the Atmel fast-vnet</div><div class='del'>-	  chips. This driver supports standard Linux wireless extensions.</div><div class='del'>-</div><div class='del'>-	  Many  cards based on this chipset do not have flash memory</div><div class='del'>-	  and need their firmware loaded at start-up. If yours is</div><div class='del'>-	  one of these, you will need to provide a firmware image</div><div class='del'>-	  to be loaded into the card by the driver. The Atmel</div><div class='del'>-	  firmware package can be downloaded from</div><div class='del'>-	  &lt;http://www.thekelleys.org.uk/atmel&gt;</div><div class='del'>-</div><div class='del'>-config PCI_ATMEL</div><div class='del'>-	tristate "Atmel at76c506 PCI cards"</div><div class='del'>-	depends on ATMEL &amp;&amp; PCI</div><div class='del'>-	help</div><div class='del'>-	  Enable support for PCI and mini-PCI cards containing the</div><div class='del'>-	  Atmel at76c506 chip.</div><div class='del'>-</div><div class='del'>-config PCMCIA_ATMEL</div><div class='del'>-	tristate "Atmel at76c502/at76c504 PCMCIA cards"</div><div class='del'>-	depends on ATMEL &amp;&amp; PCMCIA</div><div class='del'>-	select WIRELESS_EXT</div><div class='del'>-	select FW_LOADER</div><div class='del'>-	select CRC32</div><div class='del'>-	help</div><div class='del'>-	  Enable support for PCMCIA cards containing the</div><div class='del'>-	  Atmel at76c502 and at76c504 chips.</div><div class='del'>-</div><div class='ctx'> config AT76C50X_USB</div><div class='ctx'> 	tristate "Atmel at76c503/at76c505/at76c505a USB cards"</div><div class='ctx'> 	depends on MAC80211 &amp;&amp; USB</div><div class='head'>diff --git a/drivers/net/wireless/atmel/Makefile b/drivers/net/wireless/atmel/Makefile<br/>index 17e62805677d..8338d7098ba6 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/Makefile</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/Makefile?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/atmel/Makefile</a></div><div class='hunk'>@@ -1,6 +1,2 @@</div><div class='ctx'> # SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-obj-$(CONFIG_ATMEL)             += atmel.o</div><div class='del'>-obj-$(CONFIG_PCI_ATMEL)         += atmel_pci.o </div><div class='del'>-obj-$(CONFIG_PCMCIA_ATMEL)      += atmel_cs.o</div><div class='del'>-</div><div class='ctx'> obj-$(CONFIG_AT76C50X_USB)      += at76c50x-usb.o</div><div class='head'>diff --git a/drivers/net/wireless/atmel/atmel.c b/drivers/net/wireless/atmel/atmel.c<br/>deleted file mode 100644<br/>index 461dce21de2b..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/atmel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/atmel.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,4452 +0,0 @@</div><div class='del'>-/*** -*- linux-c -*- **********************************************************</div><div class='del'>-</div><div class='del'>-     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.</div><div class='del'>-</div><div class='del'>-	Copyright 2000-2001 ATMEL Corporation.</div><div class='del'>-	Copyright 2003-2004 Simon Kelley.</div><div class='del'>-</div><div class='del'>-    This code was developed from version 2.1.1 of the Atmel drivers,</div><div class='del'>-    released by Atmel corp. under the GPL in December 2002. It also</div><div class='del'>-    includes code from the Linux aironet drivers (C) Benjamin Reed,</div><div class='del'>-    and the Linux PCMCIA package, (C) David Hinds and the Linux wireless</div><div class='del'>-    extensions, (C) Jean Tourrilhes.</div><div class='del'>-</div><div class='del'>-    The firmware module for reading the MAC address of the card comes from</div><div class='del'>-    net.russotto.AtmelMACFW, written by Matthew T. Russotto and copyright</div><div class='del'>-    by him. net.russotto.AtmelMACFW is used under the GPL license version 2.</div><div class='del'>-    This file contains the module in binary form and, under the terms</div><div class='del'>-    of the GPL, in source form. The source is located at the end of the file.</div><div class='del'>-</div><div class='del'>-    This program is free software; you can redistribute it and/or modify</div><div class='del'>-    it under the terms of the GNU General Public License as published by</div><div class='del'>-    the Free Software Foundation; either version 2 of the License, or</div><div class='del'>-    (at your option) any later version.</div><div class='del'>-</div><div class='del'>-    This software is distributed in the hope that it will be useful,</div><div class='del'>-    but WITHOUT ANY WARRANTY; without even the implied warranty of</div><div class='del'>-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>-    GNU General Public License for more details.</div><div class='del'>-</div><div class='del'>-    You should have received a copy of the GNU General Public License</div><div class='del'>-    along with Atmel wireless lan drivers; if not, see</div><div class='del'>-    &lt;http://www.gnu.org/licenses/&gt;.</div><div class='del'>-</div><div class='del'>-    For all queries about this code, please contact the current author,</div><div class='del'>-    Simon Kelley &lt;simon@thekelleys.org.uk&gt; and not Atmel Corporation.</div><div class='del'>-</div><div class='del'>-    Credit is due to HP UK and Cambridge Online Systems Ltd for supplying</div><div class='del'>-    hardware used during development of this driver.</div><div class='del'>-</div><div class='del'>-******************************************************************************/</div><div class='del'>-</div><div class='del'>-#include &lt;linux/interrupt.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/ptrace.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/string.h&gt;</div><div class='del'>-#include &lt;linux/timer.h&gt;</div><div class='del'>-#include &lt;asm/byteorder.h&gt;</div><div class='del'>-#include &lt;asm/io.h&gt;</div><div class='del'>-#include &lt;linux/uaccess.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/netdevice.h&gt;</div><div class='del'>-#include &lt;linux/etherdevice.h&gt;</div><div class='del'>-#include &lt;linux/skbuff.h&gt;</div><div class='del'>-#include &lt;linux/if_arp.h&gt;</div><div class='del'>-#include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/fcntl.h&gt;</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-#include &lt;linux/wireless.h&gt;</div><div class='del'>-#include &lt;net/iw_handler.h&gt;</div><div class='del'>-#include &lt;linux/crc32.h&gt;</div><div class='del'>-#include &lt;linux/proc_fs.h&gt;</div><div class='del'>-#include &lt;linux/seq_file.h&gt;</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-#include &lt;linux/moduleparam.h&gt;</div><div class='del'>-#include &lt;linux/firmware.h&gt;</div><div class='del'>-#include &lt;linux/jiffies.h&gt;</div><div class='del'>-#include &lt;net/cfg80211.h&gt;</div><div class='del'>-#include "atmel.h"</div><div class='del'>-</div><div class='del'>-#define DRIVER_MAJOR 0</div><div class='del'>-#define DRIVER_MINOR 98</div><div class='del'>-</div><div class='del'>-MODULE_AUTHOR("Simon Kelley");</div><div class='del'>-MODULE_DESCRIPTION("Support for Atmel at76c50x 802.11 wireless ethernet cards.");</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-</div><div class='del'>-/* The name of the firmware file to be loaded</div><div class='del'>-   over-rides any automatic selection */</div><div class='del'>-static char *firmware = NULL;</div><div class='del'>-module_param(firmware, charp, 0);</div><div class='del'>-</div><div class='del'>-/* table of firmware file names */</div><div class='del'>-static struct {</div><div class='del'>-	AtmelFWType fw_type;</div><div class='del'>-	const char *fw_file;</div><div class='del'>-	const char *fw_file_ext;</div><div class='del'>-} fw_table[] = {</div><div class='del'>-	{ ATMEL_FW_TYPE_502,		"atmel_at76c502",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_502D,		"atmel_at76c502d",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_502E,		"atmel_at76c502e",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_502_3COM,	"atmel_at76c502_3com",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_504,		"atmel_at76c504",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_504_2958,	"atmel_at76c504_2958",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_504A_2958,	"atmel_at76c504a_2958",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_506,		"atmel_at76c506",	"bin" },</div><div class='del'>-	{ ATMEL_FW_TYPE_NONE,		NULL,			NULL }</div><div class='del'>-};</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502d-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502d.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502e-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502e.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502_3com-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c502_3com.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504_2958-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504_2958.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504a_2958-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c504a_2958.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c506-wpa.bin");</div><div class='del'>-MODULE_FIRMWARE("atmel_at76c506.bin");</div><div class='del'>-</div><div class='del'>-#define MAX_SSID_LENGTH 32</div><div class='del'>-#define MGMT_JIFFIES (256 * HZ / 100)</div><div class='del'>-</div><div class='del'>-#define MAX_BSS_ENTRIES	64</div><div class='del'>-</div><div class='del'>-/* registers */</div><div class='del'>-#define GCR  0x00    /* (SIR0)  General Configuration Register */</div><div class='del'>-#define BSR  0x02    /* (SIR1)  Bank Switching Select Register */</div><div class='del'>-#define AR   0x04</div><div class='del'>-#define DR   0x08</div><div class='del'>-#define MR1  0x12    /* Mirror Register 1 */</div><div class='del'>-#define MR2  0x14    /* Mirror Register 2 */</div><div class='del'>-#define MR3  0x16    /* Mirror Register 3 */</div><div class='del'>-#define MR4  0x18    /* Mirror Register 4 */</div><div class='del'>-</div><div class='del'>-#define GPR1                            0x0c</div><div class='del'>-#define GPR2                            0x0e</div><div class='del'>-#define GPR3                            0x10</div><div class='del'>-/*</div><div class='del'>- * Constants for the GCR register.</div><div class='del'>- */</div><div class='del'>-#define GCR_REMAP     0x0400          /* Remap internal SRAM to 0 */</div><div class='del'>-#define GCR_SWRES     0x0080          /* BIU reset (ARM and PAI are NOT reset) */</div><div class='del'>-#define GCR_CORES     0x0060          /* Core Reset (ARM and PAI are reset) */</div><div class='del'>-#define GCR_ENINT     0x0002          /* Enable Interrupts */</div><div class='del'>-#define GCR_ACKINT    0x0008          /* Acknowledge Interrupts */</div><div class='del'>-</div><div class='del'>-#define BSS_SRAM      0x0200          /* AMBA module selection --&gt; SRAM */</div><div class='del'>-#define BSS_IRAM      0x0100          /* AMBA module selection --&gt; IRAM */</div><div class='del'>-/*</div><div class='del'>- *Constants for the MR registers.</div><div class='del'>- */</div><div class='del'>-#define MAC_INIT_COMPLETE       0x0001        /* MAC init has been completed */</div><div class='del'>-#define MAC_BOOT_COMPLETE       0x0010        /* MAC boot has been completed */</div><div class='del'>-#define MAC_INIT_OK             0x0002        /* MAC boot has been completed */</div><div class='del'>-</div><div class='del'>-#define MIB_MAX_DATA_BYTES    212</div><div class='del'>-#define MIB_HEADER_SIZE       4    /* first four fields */</div><div class='del'>-</div><div class='del'>-struct get_set_mib {</div><div class='del'>-	u8 type;</div><div class='del'>-	u8 size;</div><div class='del'>-	u8 index;</div><div class='del'>-	u8 reserved;</div><div class='del'>-	u8 data[MIB_MAX_DATA_BYTES];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct rx_desc {</div><div class='del'>-	u32          Next;</div><div class='del'>-	u16          MsduPos;</div><div class='del'>-	u16          MsduSize;</div><div class='del'>-</div><div class='del'>-	u8           State;</div><div class='del'>-	u8           Status;</div><div class='del'>-	u8           Rate;</div><div class='del'>-	u8           Rssi;</div><div class='del'>-	u8           LinkQuality;</div><div class='del'>-	u8           PreambleType;</div><div class='del'>-	u16          Duration;</div><div class='del'>-	u32          RxTime;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define RX_DESC_FLAG_VALID       0x80</div><div class='del'>-#define RX_DESC_FLAG_CONSUMED    0x40</div><div class='del'>-#define RX_DESC_FLAG_IDLE        0x00</div><div class='del'>-</div><div class='del'>-#define RX_STATUS_SUCCESS        0x00</div><div class='del'>-</div><div class='del'>-#define RX_DESC_MSDU_POS_OFFSET      4</div><div class='del'>-#define RX_DESC_MSDU_SIZE_OFFSET     6</div><div class='del'>-#define RX_DESC_FLAGS_OFFSET         8</div><div class='del'>-#define RX_DESC_STATUS_OFFSET        9</div><div class='del'>-#define RX_DESC_RSSI_OFFSET          11</div><div class='del'>-#define RX_DESC_LINK_QUALITY_OFFSET  12</div><div class='del'>-#define RX_DESC_PREAMBLE_TYPE_OFFSET 13</div><div class='del'>-#define RX_DESC_DURATION_OFFSET      14</div><div class='del'>-#define RX_DESC_RX_TIME_OFFSET       16</div><div class='del'>-</div><div class='del'>-struct tx_desc {</div><div class='del'>-	u32       NextDescriptor;</div><div class='del'>-	u16       TxStartOfFrame;</div><div class='del'>-	u16       TxLength;</div><div class='del'>-</div><div class='del'>-	u8        TxState;</div><div class='del'>-	u8        TxStatus;</div><div class='del'>-	u8        RetryCount;</div><div class='del'>-</div><div class='del'>-	u8        TxRate;</div><div class='del'>-</div><div class='del'>-	u8        KeyIndex;</div><div class='del'>-	u8        ChiperType;</div><div class='del'>-	u8        ChipreLength;</div><div class='del'>-	u8        Reserved1;</div><div class='del'>-</div><div class='del'>-	u8        Reserved;</div><div class='del'>-	u8        PacketType;</div><div class='del'>-	u16       HostTxLength;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define TX_DESC_NEXT_OFFSET          0</div><div class='del'>-#define TX_DESC_POS_OFFSET           4</div><div class='del'>-#define TX_DESC_SIZE_OFFSET          6</div><div class='del'>-#define TX_DESC_FLAGS_OFFSET         8</div><div class='del'>-#define TX_DESC_STATUS_OFFSET        9</div><div class='del'>-#define TX_DESC_RETRY_OFFSET         10</div><div class='del'>-#define TX_DESC_RATE_OFFSET          11</div><div class='del'>-#define TX_DESC_KEY_INDEX_OFFSET     12</div><div class='del'>-#define TX_DESC_CIPHER_TYPE_OFFSET   13</div><div class='del'>-#define TX_DESC_CIPHER_LENGTH_OFFSET 14</div><div class='del'>-#define TX_DESC_PACKET_TYPE_OFFSET   17</div><div class='del'>-#define TX_DESC_HOST_LENGTH_OFFSET   18</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Host-MAC interface</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define TX_STATUS_SUCCESS       0x00</div><div class='del'>-</div><div class='del'>-#define TX_FIRM_OWN             0x80</div><div class='del'>-#define TX_DONE                 0x40</div><div class='del'>-</div><div class='del'>-#define TX_ERROR                0x01</div><div class='del'>-</div><div class='del'>-#define TX_PACKET_TYPE_DATA     0x01</div><div class='del'>-#define TX_PACKET_TYPE_MGMT     0x02</div><div class='del'>-</div><div class='del'>-#define ISR_EMPTY               0x00        /* no bits set in ISR */</div><div class='del'>-#define ISR_TxCOMPLETE          0x01        /* packet transmitted */</div><div class='del'>-#define ISR_RxCOMPLETE          0x02        /* packet received */</div><div class='del'>-#define ISR_RxFRAMELOST         0x04        /* Rx Frame lost */</div><div class='del'>-#define ISR_FATAL_ERROR         0x08        /* Fatal error */</div><div class='del'>-#define ISR_COMMAND_COMPLETE    0x10        /* command completed */</div><div class='del'>-#define ISR_OUT_OF_RANGE        0x20        /* command completed */</div><div class='del'>-#define ISR_IBSS_MERGE          0x40        /* (4.1.2.30): IBSS merge */</div><div class='del'>-#define ISR_GENERIC_IRQ         0x80</div><div class='del'>-</div><div class='del'>-#define Local_Mib_Type          0x01</div><div class='del'>-#define Mac_Address_Mib_Type    0x02</div><div class='del'>-#define Mac_Mib_Type            0x03</div><div class='del'>-#define Statistics_Mib_Type     0x04</div><div class='del'>-#define Mac_Mgmt_Mib_Type       0x05</div><div class='del'>-#define Mac_Wep_Mib_Type        0x06</div><div class='del'>-#define Phy_Mib_Type            0x07</div><div class='del'>-#define Multi_Domain_MIB        0x08</div><div class='del'>-</div><div class='del'>-#define MAC_MGMT_MIB_CUR_BSSID_POS            14</div><div class='del'>-#define MAC_MIB_FRAG_THRESHOLD_POS            8</div><div class='del'>-#define MAC_MIB_RTS_THRESHOLD_POS             10</div><div class='del'>-#define MAC_MIB_SHORT_RETRY_POS               16</div><div class='del'>-#define MAC_MIB_LONG_RETRY_POS                17</div><div class='del'>-#define MAC_MIB_SHORT_RETRY_LIMIT_POS         16</div><div class='del'>-#define MAC_MGMT_MIB_BEACON_PER_POS           0</div><div class='del'>-#define MAC_MGMT_MIB_STATION_ID_POS           6</div><div class='del'>-#define MAC_MGMT_MIB_CUR_PRIVACY_POS          11</div><div class='del'>-#define MAC_MGMT_MIB_CUR_BSSID_POS            14</div><div class='del'>-#define MAC_MGMT_MIB_PS_MODE_POS              53</div><div class='del'>-#define MAC_MGMT_MIB_LISTEN_INTERVAL_POS      54</div><div class='del'>-#define MAC_MGMT_MIB_MULTI_DOMAIN_IMPLEMENTED 56</div><div class='del'>-#define MAC_MGMT_MIB_MULTI_DOMAIN_ENABLED     57</div><div class='del'>-#define PHY_MIB_CHANNEL_POS                   14</div><div class='del'>-#define PHY_MIB_RATE_SET_POS                  20</div><div class='del'>-#define PHY_MIB_REG_DOMAIN_POS                26</div><div class='del'>-#define LOCAL_MIB_AUTO_TX_RATE_POS            3</div><div class='del'>-#define LOCAL_MIB_SSID_SIZE                   5</div><div class='del'>-#define LOCAL_MIB_TX_PROMISCUOUS_POS          6</div><div class='del'>-#define LOCAL_MIB_TX_MGMT_RATE_POS            7</div><div class='del'>-#define LOCAL_MIB_TX_CONTROL_RATE_POS         8</div><div class='del'>-#define LOCAL_MIB_PREAMBLE_TYPE               9</div><div class='del'>-#define MAC_ADDR_MIB_MAC_ADDR_POS             0</div><div class='del'>-</div><div class='del'>-#define         CMD_Set_MIB_Vars              0x01</div><div class='del'>-#define         CMD_Get_MIB_Vars              0x02</div><div class='del'>-#define         CMD_Scan                      0x03</div><div class='del'>-#define         CMD_Join                      0x04</div><div class='del'>-#define         CMD_Start                     0x05</div><div class='del'>-#define         CMD_EnableRadio               0x06</div><div class='del'>-#define         CMD_DisableRadio              0x07</div><div class='del'>-#define         CMD_SiteSurvey                0x0B</div><div class='del'>-</div><div class='del'>-#define         CMD_STATUS_IDLE                   0x00</div><div class='del'>-#define         CMD_STATUS_COMPLETE               0x01</div><div class='del'>-#define         CMD_STATUS_UNKNOWN                0x02</div><div class='del'>-#define         CMD_STATUS_INVALID_PARAMETER      0x03</div><div class='del'>-#define         CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04</div><div class='del'>-#define         CMD_STATUS_TIME_OUT               0x07</div><div class='del'>-#define         CMD_STATUS_IN_PROGRESS            0x08</div><div class='del'>-#define         CMD_STATUS_REJECTED_RADIO_OFF     0x09</div><div class='del'>-#define         CMD_STATUS_HOST_ERROR             0xFF</div><div class='del'>-#define         CMD_STATUS_BUSY                   0xFE</div><div class='del'>-</div><div class='del'>-#define CMD_BLOCK_COMMAND_OFFSET        0</div><div class='del'>-#define CMD_BLOCK_STATUS_OFFSET         1</div><div class='del'>-#define CMD_BLOCK_PARAMETERS_OFFSET     4</div><div class='del'>-</div><div class='del'>-#define SCAN_OPTIONS_SITE_SURVEY        0x80</div><div class='del'>-</div><div class='del'>-#define MGMT_FRAME_BODY_OFFSET		24</div><div class='del'>-#define MAX_AUTHENTICATION_RETRIES	3</div><div class='del'>-#define MAX_ASSOCIATION_RETRIES		3</div><div class='del'>-</div><div class='del'>-#define AUTHENTICATION_RESPONSE_TIME_OUT  1000</div><div class='del'>-</div><div class='del'>-#define MAX_WIRELESS_BODY  2316 /* mtu is 2312, CRC is 4 */</div><div class='del'>-#define LOOP_RETRY_LIMIT   500000</div><div class='del'>-</div><div class='del'>-#define ACTIVE_MODE	1</div><div class='del'>-#define PS_MODE		2</div><div class='del'>-</div><div class='del'>-#define MAX_ENCRYPTION_KEYS 4</div><div class='del'>-#define MAX_ENCRYPTION_KEY_SIZE 40</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * 802.11 related definitions</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Regulatory Domains</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#define REG_DOMAIN_FCC		0x10	/* Channels	1-11	USA				*/</div><div class='del'>-#define REG_DOMAIN_DOC		0x20	/* Channel	1-11	Canada				*/</div><div class='del'>-#define REG_DOMAIN_ETSI		0x30	/* Channel	1-13	Europe (ex Spain/France)	*/</div><div class='del'>-#define REG_DOMAIN_SPAIN	0x31	/* Channel	10-11	Spain				*/</div><div class='del'>-#define REG_DOMAIN_FRANCE	0x32	/* Channel	10-13	France				*/</div><div class='del'>-#define REG_DOMAIN_MKK		0x40	/* Channel	14	Japan				*/</div><div class='del'>-#define REG_DOMAIN_MKK1		0x41	/* Channel	1-14	Japan(MKK1)			*/</div><div class='del'>-#define REG_DOMAIN_ISRAEL	0x50	/* Channel	3-9	ISRAEL				*/</div><div class='del'>-</div><div class='del'>-#define BSS_TYPE_AD_HOC		1</div><div class='del'>-#define BSS_TYPE_INFRASTRUCTURE 2</div><div class='del'>-</div><div class='del'>-#define SCAN_TYPE_ACTIVE	0</div><div class='del'>-#define SCAN_TYPE_PASSIVE	1</div><div class='del'>-</div><div class='del'>-#define LONG_PREAMBLE		0</div><div class='del'>-#define SHORT_PREAMBLE		1</div><div class='del'>-#define AUTO_PREAMBLE		2</div><div class='del'>-</div><div class='del'>-#define DATA_FRAME_WS_HEADER_SIZE   30</div><div class='del'>-</div><div class='del'>-/* promiscuous mode control */</div><div class='del'>-#define PROM_MODE_OFF			0x0</div><div class='del'>-#define PROM_MODE_UNKNOWN		0x1</div><div class='del'>-#define PROM_MODE_CRC_FAILED		0x2</div><div class='del'>-#define PROM_MODE_DUPLICATED		0x4</div><div class='del'>-#define PROM_MODE_MGMT			0x8</div><div class='del'>-#define PROM_MODE_CTRL			0x10</div><div class='del'>-#define PROM_MODE_BAD_PROTOCOL		0x20</div><div class='del'>-</div><div class='del'>-#define IFACE_INT_STATUS_OFFSET		0</div><div class='del'>-#define IFACE_INT_MASK_OFFSET		1</div><div class='del'>-#define IFACE_LOCKOUT_HOST_OFFSET	2</div><div class='del'>-#define IFACE_LOCKOUT_MAC_OFFSET	3</div><div class='del'>-#define IFACE_FUNC_CTRL_OFFSET		28</div><div class='del'>-#define IFACE_MAC_STAT_OFFSET		30</div><div class='del'>-#define IFACE_GENERIC_INT_TYPE_OFFSET	32</div><div class='del'>-</div><div class='del'>-#define CIPHER_SUITE_NONE     0</div><div class='del'>-#define CIPHER_SUITE_WEP_64   1</div><div class='del'>-#define CIPHER_SUITE_TKIP     2</div><div class='del'>-#define CIPHER_SUITE_AES      3</div><div class='del'>-#define CIPHER_SUITE_CCX      4</div><div class='del'>-#define CIPHER_SUITE_WEP_128  5</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * IFACE MACROS &amp; definitions</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * FuncCtrl field:</div><div class='del'>- */</div><div class='del'>-#define FUNC_CTRL_TxENABLE		0x10</div><div class='del'>-#define FUNC_CTRL_RxENABLE		0x20</div><div class='del'>-#define FUNC_CTRL_INIT_COMPLETE		0x01</div><div class='del'>-</div><div class='del'>-/* A stub firmware image which reads the MAC address from NVRAM on the card.</div><div class='del'>-   For copyright information and source see the end of this file. */</div><div class='del'>-static u8 mac_reader[] = {</div><div class='del'>-	0x06, 0x00, 0x00, 0xea, 0x04, 0x00, 0x00, 0xea, 0x03, 0x00, 0x00, 0xea, 0x02, 0x00, 0x00, 0xea,</div><div class='del'>-	0x01, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xff, 0xea, 0xfe, 0xff, 0xff, 0xea,</div><div class='del'>-	0xd3, 0x00, 0xa0, 0xe3, 0x00, 0xf0, 0x21, 0xe1, 0x0e, 0x04, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,</div><div class='del'>-	0x81, 0x11, 0xa0, 0xe1, 0x00, 0x10, 0x81, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x1c, 0x10, 0x90, 0xe5,</div><div class='del'>-	0x10, 0x10, 0xc1, 0xe3, 0x1c, 0x10, 0x80, 0xe5, 0x01, 0x10, 0xa0, 0xe3, 0x08, 0x10, 0x80, 0xe5,</div><div class='del'>-	0x02, 0x03, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3, 0xb0, 0x10, 0xc0, 0xe1, 0xb4, 0x10, 0xc0, 0xe1,</div><div class='del'>-	0xb8, 0x10, 0xc0, 0xe1, 0xbc, 0x10, 0xc0, 0xe1, 0x56, 0xdc, 0xa0, 0xe3, 0x21, 0x00, 0x00, 0xeb,</div><div class='del'>-	0x0a, 0x00, 0xa0, 0xe3, 0x1a, 0x00, 0x00, 0xeb, 0x10, 0x00, 0x00, 0xeb, 0x07, 0x00, 0x00, 0xeb,</div><div class='del'>-	0x02, 0x03, 0xa0, 0xe3, 0x02, 0x14, 0xa0, 0xe3, 0xb4, 0x10, 0xc0, 0xe1, 0x4c, 0x10, 0x9f, 0xe5,</div><div class='del'>-	0xbc, 0x10, 0xc0, 0xe1, 0x10, 0x10, 0xa0, 0xe3, 0xb8, 0x10, 0xc0, 0xe1, 0xfe, 0xff, 0xff, 0xea,</div><div class='del'>-	0x00, 0x40, 0x2d, 0xe9, 0x00, 0x20, 0xa0, 0xe3, 0x02, 0x3c, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,</div><div class='del'>-	0x28, 0x00, 0x9f, 0xe5, 0x37, 0x00, 0x00, 0xeb, 0x00, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1,</div><div class='del'>-	0x00, 0x40, 0x2d, 0xe9, 0x12, 0x2e, 0xa0, 0xe3, 0x06, 0x30, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3,</div><div class='del'>-	0x02, 0x04, 0xa0, 0xe3, 0x2f, 0x00, 0x00, 0xeb, 0x00, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1,</div><div class='del'>-	0x00, 0x02, 0x00, 0x02, 0x80, 0x01, 0x90, 0xe0, 0x01, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x50, 0xe2,</div><div class='del'>-	0xfc, 0xff, 0xff, 0xea, 0x1e, 0xff, 0x2f, 0xe1, 0x80, 0x10, 0xa0, 0xe3, 0xf3, 0x06, 0xa0, 0xe3,</div><div class='del'>-	0x00, 0x10, 0x80, 0xe5, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x01, 0x10, 0xa0, 0xe3,</div><div class='del'>-	0x04, 0x10, 0x80, 0xe5, 0x00, 0x10, 0x80, 0xe5, 0x0e, 0x34, 0xa0, 0xe3, 0x1c, 0x10, 0x93, 0xe5,</div><div class='del'>-	0x02, 0x1a, 0x81, 0xe3, 0x1c, 0x10, 0x83, 0xe5, 0x58, 0x11, 0x9f, 0xe5, 0x30, 0x10, 0x80, 0xe5,</div><div class='del'>-	0x54, 0x11, 0x9f, 0xe5, 0x34, 0x10, 0x80, 0xe5, 0x38, 0x10, 0x80, 0xe5, 0x3c, 0x10, 0x80, 0xe5,</div><div class='del'>-	0x10, 0x10, 0x90, 0xe5, 0x08, 0x00, 0x90, 0xe5, 0x1e, 0xff, 0x2f, 0xe1, 0xf3, 0x16, 0xa0, 0xe3,</div><div class='del'>-	0x08, 0x00, 0x91, 0xe5, 0x05, 0x00, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5, 0x10, 0x00, 0x91, 0xe5,</div><div class='del'>-	0x02, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0xff, 0x00, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5,</div><div class='del'>-	0x10, 0x00, 0x91, 0xe5, 0x02, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x91, 0xe5,</div><div class='del'>-	0x10, 0x00, 0x91, 0xe5, 0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x91, 0xe5,</div><div class='del'>-	0xff, 0x00, 0x00, 0xe2, 0x1e, 0xff, 0x2f, 0xe1, 0x30, 0x40, 0x2d, 0xe9, 0x00, 0x50, 0xa0, 0xe1,</div><div class='del'>-	0x03, 0x40, 0xa0, 0xe1, 0xa2, 0x02, 0xa0, 0xe1, 0x08, 0x00, 0x00, 0xe2, 0x03, 0x00, 0x80, 0xe2,</div><div class='del'>-	0xd8, 0x10, 0x9f, 0xe5, 0x00, 0x00, 0xc1, 0xe5, 0x01, 0x20, 0xc1, 0xe5, 0xe2, 0xff, 0xff, 0xeb,</div><div class='del'>-	0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x1a, 0x14, 0x00, 0xa0, 0xe3, 0xc4, 0xff, 0xff, 0xeb,</div><div class='del'>-	0x04, 0x20, 0xa0, 0xe1, 0x05, 0x10, 0xa0, 0xe1, 0x02, 0x00, 0xa0, 0xe3, 0x01, 0x00, 0x00, 0xeb,</div><div class='del'>-	0x30, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1, 0x70, 0x40, 0x2d, 0xe9, 0xf3, 0x46, 0xa0, 0xe3,</div><div class='del'>-	0x00, 0x30, 0xa0, 0xe3, 0x00, 0x00, 0x50, 0xe3, 0x08, 0x00, 0x00, 0x9a, 0x8c, 0x50, 0x9f, 0xe5,</div><div class='del'>-	0x03, 0x60, 0xd5, 0xe7, 0x0c, 0x60, 0x84, 0xe5, 0x10, 0x60, 0x94, 0xe5, 0x02, 0x00, 0x16, 0xe3,</div><div class='del'>-	0xfc, 0xff, 0xff, 0x0a, 0x01, 0x30, 0x83, 0xe2, 0x00, 0x00, 0x53, 0xe1, 0xf7, 0xff, 0xff, 0x3a,</div><div class='del'>-	0xff, 0x30, 0xa0, 0xe3, 0x0c, 0x30, 0x84, 0xe5, 0x08, 0x00, 0x94, 0xe5, 0x10, 0x00, 0x94, 0xe5,</div><div class='del'>-	0x01, 0x00, 0x10, 0xe3, 0xfc, 0xff, 0xff, 0x0a, 0x08, 0x00, 0x94, 0xe5, 0x00, 0x00, 0xa0, 0xe3,</div><div class='del'>-	0x00, 0x00, 0x52, 0xe3, 0x0b, 0x00, 0x00, 0x9a, 0x10, 0x50, 0x94, 0xe5, 0x02, 0x00, 0x15, 0xe3,</div><div class='del'>-	0xfc, 0xff, 0xff, 0x0a, 0x0c, 0x30, 0x84, 0xe5, 0x10, 0x50, 0x94, 0xe5, 0x01, 0x00, 0x15, 0xe3,</div><div class='del'>-	0xfc, 0xff, 0xff, 0x0a, 0x08, 0x50, 0x94, 0xe5, 0x01, 0x50, 0xc1, 0xe4, 0x01, 0x00, 0x80, 0xe2,</div><div class='del'>-	0x02, 0x00, 0x50, 0xe1, 0xf3, 0xff, 0xff, 0x3a, 0xc8, 0x00, 0xa0, 0xe3, 0x98, 0xff, 0xff, 0xeb,</div><div class='del'>-	0x70, 0x40, 0xbd, 0xe8, 0x1e, 0xff, 0x2f, 0xe1, 0x01, 0x0c, 0x00, 0x02, 0x01, 0x02, 0x00, 0x02,</div><div class='del'>-	0x00, 0x01, 0x00, 0x02</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct atmel_private {</div><div class='del'>-	void *card; /* Bus dependent structure varies for PCcard */</div><div class='del'>-	int (*present_callback)(void *); /* And callback which uses it */</div><div class='del'>-	char firmware_id[32];</div><div class='del'>-	AtmelFWType firmware_type;</div><div class='del'>-	u8 *firmware;</div><div class='del'>-	int firmware_length;</div><div class='del'>-	struct timer_list management_timer;</div><div class='del'>-	struct net_device *dev;</div><div class='del'>-	struct device *sys_dev;</div><div class='del'>-	struct iw_statistics wstats;</div><div class='del'>-	spinlock_t irqlock, timerlock;	/* spinlocks */</div><div class='del'>-	enum { BUS_TYPE_PCCARD, BUS_TYPE_PCI } bus_type;</div><div class='del'>-	enum {</div><div class='del'>-		CARD_TYPE_PARALLEL_FLASH,</div><div class='del'>-		CARD_TYPE_SPI_FLASH,</div><div class='del'>-		CARD_TYPE_EEPROM</div><div class='del'>-	} card_type;</div><div class='del'>-	int do_rx_crc; /* If we need to CRC incoming packets */</div><div class='del'>-	int probe_crc; /* set if we don't yet know */</div><div class='del'>-	int crc_ok_cnt, crc_ko_cnt; /* counters for probing */</div><div class='del'>-	u16 rx_desc_head;</div><div class='del'>-	u16 tx_desc_free, tx_desc_head, tx_desc_tail, tx_desc_previous;</div><div class='del'>-	u16 tx_free_mem, tx_buff_head, tx_buff_tail;</div><div class='del'>-</div><div class='del'>-	u16 frag_seq, frag_len, frag_no;</div><div class='del'>-	u8 frag_source[6];</div><div class='del'>-</div><div class='del'>-	u8 wep_is_on, default_key, exclude_unencrypted, encryption_level;</div><div class='del'>-	u8 group_cipher_suite, pairwise_cipher_suite;</div><div class='del'>-	u8 wep_keys[MAX_ENCRYPTION_KEYS][MAX_ENCRYPTION_KEY_SIZE];</div><div class='del'>-	int wep_key_len[MAX_ENCRYPTION_KEYS];</div><div class='del'>-	int use_wpa, radio_on_broken; /* firmware dependent stuff. */</div><div class='del'>-</div><div class='del'>-	u16 host_info_base;</div><div class='del'>-	struct host_info_struct {</div><div class='del'>-		/* NB this is matched to the hardware, don't change. */</div><div class='del'>-		u8 volatile int_status;</div><div class='del'>-		u8 volatile int_mask;</div><div class='del'>-		u8 volatile lockout_host;</div><div class='del'>-		u8 volatile lockout_mac;</div><div class='del'>-</div><div class='del'>-		u16 tx_buff_pos;</div><div class='del'>-		u16 tx_buff_size;</div><div class='del'>-		u16 tx_desc_pos;</div><div class='del'>-		u16 tx_desc_count;</div><div class='del'>-</div><div class='del'>-		u16 rx_buff_pos;</div><div class='del'>-		u16 rx_buff_size;</div><div class='del'>-		u16 rx_desc_pos;</div><div class='del'>-		u16 rx_desc_count;</div><div class='del'>-</div><div class='del'>-		u16 build_version;</div><div class='del'>-		u16 command_pos;</div><div class='del'>-</div><div class='del'>-		u16 major_version;</div><div class='del'>-		u16 minor_version;</div><div class='del'>-</div><div class='del'>-		u16 func_ctrl;</div><div class='del'>-		u16 mac_status;</div><div class='del'>-		u16 generic_IRQ_type;</div><div class='del'>-		u8  reserved[2];</div><div class='del'>-	} host_info;</div><div class='del'>-</div><div class='del'>-	enum {</div><div class='del'>-		STATION_STATE_SCANNING,</div><div class='del'>-		STATION_STATE_JOINNING,</div><div class='del'>-		STATION_STATE_AUTHENTICATING,</div><div class='del'>-		STATION_STATE_ASSOCIATING,</div><div class='del'>-		STATION_STATE_READY,</div><div class='del'>-		STATION_STATE_REASSOCIATING,</div><div class='del'>-		STATION_STATE_DOWN,</div><div class='del'>-		STATION_STATE_MGMT_ERROR</div><div class='del'>-	} station_state;</div><div class='del'>-</div><div class='del'>-	int operating_mode, power_mode;</div><div class='del'>-	unsigned long last_qual;</div><div class='del'>-	int beacons_this_sec;</div><div class='del'>-	int channel;</div><div class='del'>-	int reg_domain, config_reg_domain;</div><div class='del'>-	int tx_rate;</div><div class='del'>-	int auto_tx_rate;</div><div class='del'>-	int rts_threshold;</div><div class='del'>-	int frag_threshold;</div><div class='del'>-	int long_retry, short_retry;</div><div class='del'>-	int preamble;</div><div class='del'>-	int default_beacon_period, beacon_period, listen_interval;</div><div class='del'>-	int CurrentAuthentTransactionSeqNum, ExpectedAuthentTransactionSeqNum;</div><div class='del'>-	int AuthenticationRequestRetryCnt, AssociationRequestRetryCnt, ReAssociationRequestRetryCnt;</div><div class='del'>-	enum {</div><div class='del'>-		SITE_SURVEY_IDLE,</div><div class='del'>-		SITE_SURVEY_IN_PROGRESS,</div><div class='del'>-		SITE_SURVEY_COMPLETED</div><div class='del'>-	} site_survey_state;</div><div class='del'>-	unsigned long last_survey;</div><div class='del'>-</div><div class='del'>-	int station_was_associated, station_is_associated;</div><div class='del'>-	int fast_scan;</div><div class='del'>-</div><div class='del'>-	struct bss_info {</div><div class='del'>-		int channel;</div><div class='del'>-		int SSIDsize;</div><div class='del'>-		int RSSI;</div><div class='del'>-		int UsingWEP;</div><div class='del'>-		int preamble;</div><div class='del'>-		int beacon_period;</div><div class='del'>-		int BSStype;</div><div class='del'>-		u8 BSSID[6];</div><div class='del'>-		u8 SSID[MAX_SSID_LENGTH];</div><div class='del'>-	} BSSinfo[MAX_BSS_ENTRIES];</div><div class='del'>-	int BSS_list_entries, current_BSS;</div><div class='del'>-	int connect_to_any_BSS;</div><div class='del'>-	int SSID_size, new_SSID_size;</div><div class='del'>-	u8 CurrentBSSID[6], BSSID[6];</div><div class='del'>-	u8 SSID[MAX_SSID_LENGTH], new_SSID[MAX_SSID_LENGTH];</div><div class='del'>-	u64 last_beacon_timestamp;</div><div class='del'>-	u8 rx_buf[MAX_WIRELESS_BODY];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static u8 atmel_basic_rates[4] = {0x82, 0x84, 0x0b, 0x16};</div><div class='del'>-</div><div class='del'>-static const struct {</div><div class='del'>-	int reg_domain;</div><div class='del'>-	int min, max;</div><div class='del'>-	char *name;</div><div class='del'>-} channel_table[] = { { REG_DOMAIN_FCC, 1, 11, "USA" },</div><div class='del'>-		      { REG_DOMAIN_DOC, 1, 11, "Canada" },</div><div class='del'>-		      { REG_DOMAIN_ETSI, 1, 13, "Europe" },</div><div class='del'>-		      { REG_DOMAIN_SPAIN, 10, 11, "Spain" },</div><div class='del'>-		      { REG_DOMAIN_FRANCE, 10, 13, "France" },</div><div class='del'>-		      { REG_DOMAIN_MKK, 14, 14, "MKK" },</div><div class='del'>-		      { REG_DOMAIN_MKK1, 1, 14, "MKK1" },</div><div class='del'>-		      { REG_DOMAIN_ISRAEL, 3, 9, "Israel"} };</div><div class='del'>-</div><div class='del'>-static void build_wpa_mib(struct atmel_private *priv);</div><div class='del'>-static void atmel_copy_to_card(struct net_device *dev, u16 dest,</div><div class='del'>-			       const unsigned char *src, u16 len);</div><div class='del'>-static void atmel_copy_to_host(struct net_device *dev, unsigned char *dest,</div><div class='del'>-			       u16 src, u16 len);</div><div class='del'>-static void atmel_set_gcr(struct net_device *dev, u16 mask);</div><div class='del'>-static void atmel_clear_gcr(struct net_device *dev, u16 mask);</div><div class='del'>-static int atmel_lock_mac(struct atmel_private *priv);</div><div class='del'>-static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data);</div><div class='del'>-static void atmel_command_irq(struct atmel_private *priv);</div><div class='del'>-static int atmel_validate_channel(struct atmel_private *priv, int channel);</div><div class='del'>-static void atmel_management_frame(struct atmel_private *priv,</div><div class='del'>-				   struct ieee80211_hdr *header,</div><div class='del'>-				   u16 frame_len, u8 rssi);</div><div class='del'>-static void atmel_management_timer(struct timer_list *t);</div><div class='del'>-static void atmel_send_command(struct atmel_private *priv, int command,</div><div class='del'>-			       void *cmd, int cmd_size);</div><div class='del'>-static int atmel_send_command_wait(struct atmel_private *priv, int command,</div><div class='del'>-				   void *cmd, int cmd_size);</div><div class='del'>-static void atmel_transmit_management_frame(struct atmel_private *priv,</div><div class='del'>-					    struct ieee80211_hdr *header,</div><div class='del'>-					    u8 *body, int body_len);</div><div class='del'>-</div><div class='del'>-static u8 atmel_get_mib8(struct atmel_private *priv, u8 type, u8 index);</div><div class='del'>-static void atmel_set_mib8(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			   u8 data);</div><div class='del'>-static void atmel_set_mib16(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			    u16 data);</div><div class='del'>-static void atmel_set_mib(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			  const u8 *data, int data_len);</div><div class='del'>-static void atmel_get_mib(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			  u8 *data, int data_len);</div><div class='del'>-static void atmel_scan(struct atmel_private *priv, int specific_ssid);</div><div class='del'>-static void atmel_join_bss(struct atmel_private *priv, int bss_index);</div><div class='del'>-static void atmel_smooth_qual(struct atmel_private *priv);</div><div class='del'>-static void atmel_writeAR(struct net_device *dev, u16 data);</div><div class='del'>-static int probe_atmel_card(struct net_device *dev);</div><div class='del'>-static int reset_atmel_card(struct net_device *dev);</div><div class='del'>-static void atmel_enter_state(struct atmel_private *priv, int new_state);</div><div class='del'>-int atmel_open (struct net_device *dev);</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_hi(struct atmel_private *priv, u16 offset)</div><div class='del'>-{</div><div class='del'>-	return priv-&gt;host_info_base + offset;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_co(struct atmel_private *priv, u16 offset)</div><div class='del'>-{</div><div class='del'>-	return priv-&gt;host_info.command_pos + offset;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_rx(struct atmel_private *priv, u16 offset, u16 desc)</div><div class='del'>-{</div><div class='del'>-	return priv-&gt;host_info.rx_desc_pos + (sizeof(struct rx_desc) * desc) + offset;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_tx(struct atmel_private *priv, u16 offset, u16 desc)</div><div class='del'>-{</div><div class='del'>-	return priv-&gt;host_info.tx_desc_pos + (sizeof(struct tx_desc) * desc) + offset;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u8 atmel_read8(struct net_device *dev, u16 offset)</div><div class='del'>-{</div><div class='del'>-	return inb(dev-&gt;base_addr + offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void atmel_write8(struct net_device *dev, u16 offset, u8 data)</div><div class='del'>-{</div><div class='del'>-	outb(data, dev-&gt;base_addr + offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_read16(struct net_device *dev, u16 offset)</div><div class='del'>-{</div><div class='del'>-	return inw(dev-&gt;base_addr + offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void atmel_write16(struct net_device *dev, u16 offset, u16 data)</div><div class='del'>-{</div><div class='del'>-	outw(data, dev-&gt;base_addr + offset);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u8 atmel_rmem8(struct atmel_private *priv, u16 pos)</div><div class='del'>-{</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, pos);</div><div class='del'>-	return atmel_read8(priv-&gt;dev, DR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void atmel_wmem8(struct atmel_private *priv, u16 pos, u16 data)</div><div class='del'>-{</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, pos);</div><div class='del'>-	atmel_write8(priv-&gt;dev, DR, data);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline u16 atmel_rmem16(struct atmel_private *priv, u16 pos)</div><div class='del'>-{</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, pos);</div><div class='del'>-	return atmel_read16(priv-&gt;dev, DR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void atmel_wmem16(struct atmel_private *priv, u16 pos, u16 data)</div><div class='del'>-{</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, pos);</div><div class='del'>-	atmel_write16(priv-&gt;dev, DR, data);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct iw_handler_def atmel_handler_def;</div><div class='del'>-</div><div class='del'>-static void tx_done_irq(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0;</div><div class='del'>-	     atmel_rmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv-&gt;tx_desc_head)) == TX_DONE &amp;&amp;</div><div class='del'>-		     i &lt; priv-&gt;host_info.tx_desc_count;</div><div class='del'>-	     i++) {</div><div class='del'>-		u8 status = atmel_rmem8(priv, atmel_tx(priv, TX_DESC_STATUS_OFFSET, priv-&gt;tx_desc_head));</div><div class='del'>-		u16 msdu_size = atmel_rmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, priv-&gt;tx_desc_head));</div><div class='del'>-		u8 type = atmel_rmem8(priv, atmel_tx(priv, TX_DESC_PACKET_TYPE_OFFSET, priv-&gt;tx_desc_head));</div><div class='del'>-</div><div class='del'>-		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv-&gt;tx_desc_head), 0);</div><div class='del'>-</div><div class='del'>-		priv-&gt;tx_free_mem += msdu_size;</div><div class='del'>-		priv-&gt;tx_desc_free++;</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;tx_buff_head + msdu_size &gt; (priv-&gt;host_info.tx_buff_pos + priv-&gt;host_info.tx_buff_size))</div><div class='del'>-			priv-&gt;tx_buff_head = 0;</div><div class='del'>-		else</div><div class='del'>-			priv-&gt;tx_buff_head += msdu_size;</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;tx_desc_head &lt; (priv-&gt;host_info.tx_desc_count - 1))</div><div class='del'>-			priv-&gt;tx_desc_head++ ;</div><div class='del'>-		else</div><div class='del'>-			priv-&gt;tx_desc_head = 0;</div><div class='del'>-</div><div class='del'>-		if (type == TX_PACKET_TYPE_DATA) {</div><div class='del'>-			if (status == TX_STATUS_SUCCESS)</div><div class='del'>-				priv-&gt;dev-&gt;stats.tx_packets++;</div><div class='del'>-			else</div><div class='del'>-				priv-&gt;dev-&gt;stats.tx_errors++;</div><div class='del'>-			netif_wake_queue(priv-&gt;dev);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u16 find_tx_buff(struct atmel_private *priv, u16 len)</div><div class='del'>-{</div><div class='del'>-	u16 bottom_free = priv-&gt;host_info.tx_buff_size - priv-&gt;tx_buff_tail;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;tx_desc_free == 3 || priv-&gt;tx_free_mem &lt; len)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	if (bottom_free &gt;= len)</div><div class='del'>-		return priv-&gt;host_info.tx_buff_pos + priv-&gt;tx_buff_tail;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;tx_free_mem - bottom_free &gt;= len) {</div><div class='del'>-		priv-&gt;tx_buff_tail = 0;</div><div class='del'>-		return priv-&gt;host_info.tx_buff_pos;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void tx_update_descriptor(struct atmel_private *priv, int is_bcast,</div><div class='del'>-				 u16 len, u16 buff, u8 type)</div><div class='del'>-{</div><div class='del'>-	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_POS_OFFSET, priv-&gt;tx_desc_tail), buff);</div><div class='del'>-	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, priv-&gt;tx_desc_tail), len);</div><div class='del'>-	if (!priv-&gt;use_wpa)</div><div class='del'>-		atmel_wmem16(priv, atmel_tx(priv, TX_DESC_HOST_LENGTH_OFFSET, priv-&gt;tx_desc_tail), len);</div><div class='del'>-	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_PACKET_TYPE_OFFSET, priv-&gt;tx_desc_tail), type);</div><div class='del'>-	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_RATE_OFFSET, priv-&gt;tx_desc_tail), priv-&gt;tx_rate);</div><div class='del'>-	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_RETRY_OFFSET, priv-&gt;tx_desc_tail), 0);</div><div class='del'>-	if (priv-&gt;use_wpa) {</div><div class='del'>-		int cipher_type, cipher_length;</div><div class='del'>-		if (is_bcast) {</div><div class='del'>-			cipher_type = priv-&gt;group_cipher_suite;</div><div class='del'>-			if (cipher_type == CIPHER_SUITE_WEP_64 ||</div><div class='del'>-			    cipher_type == CIPHER_SUITE_WEP_128)</div><div class='del'>-				cipher_length = 8;</div><div class='del'>-			else if (cipher_type == CIPHER_SUITE_TKIP)</div><div class='del'>-				cipher_length = 12;</div><div class='del'>-			else if (priv-&gt;pairwise_cipher_suite == CIPHER_SUITE_WEP_64 ||</div><div class='del'>-				 priv-&gt;pairwise_cipher_suite == CIPHER_SUITE_WEP_128) {</div><div class='del'>-				cipher_type = priv-&gt;pairwise_cipher_suite;</div><div class='del'>-				cipher_length = 8;</div><div class='del'>-			} else {</div><div class='del'>-				cipher_type = CIPHER_SUITE_NONE;</div><div class='del'>-				cipher_length = 0;</div><div class='del'>-			}</div><div class='del'>-		} else {</div><div class='del'>-			cipher_type = priv-&gt;pairwise_cipher_suite;</div><div class='del'>-			if (cipher_type == CIPHER_SUITE_WEP_64 ||</div><div class='del'>-			    cipher_type == CIPHER_SUITE_WEP_128)</div><div class='del'>-				cipher_length = 8;</div><div class='del'>-			else if (cipher_type == CIPHER_SUITE_TKIP)</div><div class='del'>-				cipher_length = 12;</div><div class='del'>-			else if (priv-&gt;group_cipher_suite == CIPHER_SUITE_WEP_64 ||</div><div class='del'>-				 priv-&gt;group_cipher_suite == CIPHER_SUITE_WEP_128) {</div><div class='del'>-				cipher_type = priv-&gt;group_cipher_suite;</div><div class='del'>-				cipher_length = 8;</div><div class='del'>-			} else {</div><div class='del'>-				cipher_type = CIPHER_SUITE_NONE;</div><div class='del'>-				cipher_length = 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_CIPHER_TYPE_OFFSET, priv-&gt;tx_desc_tail),</div><div class='del'>-			    cipher_type);</div><div class='del'>-		atmel_wmem8(priv, atmel_tx(priv, TX_DESC_CIPHER_LENGTH_OFFSET, priv-&gt;tx_desc_tail),</div><div class='del'>-			    cipher_length);</div><div class='del'>-	}</div><div class='del'>-	atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, priv-&gt;tx_desc_tail), 0x80000000L);</div><div class='del'>-	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, priv-&gt;tx_desc_tail), TX_FIRM_OWN);</div><div class='del'>-	if (priv-&gt;tx_desc_previous != priv-&gt;tx_desc_tail)</div><div class='del'>-		atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, priv-&gt;tx_desc_previous), 0);</div><div class='del'>-	priv-&gt;tx_desc_previous = priv-&gt;tx_desc_tail;</div><div class='del'>-	if (priv-&gt;tx_desc_tail &lt; (priv-&gt;host_info.tx_desc_count - 1))</div><div class='del'>-		priv-&gt;tx_desc_tail++;</div><div class='del'>-	else</div><div class='del'>-		priv-&gt;tx_desc_tail = 0;</div><div class='del'>-	priv-&gt;tx_desc_free--;</div><div class='del'>-	priv-&gt;tx_free_mem -= len;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct ieee80211_hdr header;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	u16 buff, frame_ctl, len = (ETH_ZLEN &lt; skb-&gt;len) ? skb-&gt;len : ETH_ZLEN;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;card &amp;&amp; priv-&gt;present_callback &amp;&amp;</div><div class='del'>-	    !(*priv-&gt;present_callback)(priv-&gt;card)) {</div><div class='del'>-		dev-&gt;stats.tx_errors++;</div><div class='del'>-		dev_kfree_skb(skb);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;station_state != STATION_STATE_READY) {</div><div class='del'>-		dev-&gt;stats.tx_errors++;</div><div class='del'>-		dev_kfree_skb(skb);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* first ensure the timer func cannot run */</div><div class='del'>-	spin_lock_bh(&amp;priv-&gt;timerlock);</div><div class='del'>-	/* then stop the hardware ISR */</div><div class='del'>-	spin_lock_irqsave(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-	/* nb doing the above in the opposite order will deadlock */</div><div class='del'>-</div><div class='del'>-	/* The Wireless Header is 30 bytes. In the Ethernet packet we "cut" the</div><div class='del'>-	   12 first bytes (containing DA/SA) and put them in the appropriate</div><div class='del'>-	   fields of the Wireless Header. Thus the packet length is then the</div><div class='del'>-	   initial + 18 (+30-12) */</div><div class='del'>-</div><div class='del'>-	if (!(buff = find_tx_buff(priv, len + 18))) {</div><div class='del'>-		dev-&gt;stats.tx_dropped++;</div><div class='del'>-		spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-		spin_unlock_bh(&amp;priv-&gt;timerlock);</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-		return NETDEV_TX_BUSY;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	frame_ctl = IEEE80211_FTYPE_DATA;</div><div class='del'>-	header.duration_id = 0;</div><div class='del'>-	header.seq_ctrl = 0;</div><div class='del'>-	if (priv-&gt;wep_is_on)</div><div class='del'>-		frame_ctl |= IEEE80211_FCTL_PROTECTED;</div><div class='del'>-	if (priv-&gt;operating_mode == IW_MODE_ADHOC) {</div><div class='del'>-		skb_copy_from_linear_data(skb, &amp;header.addr1, ETH_ALEN);</div><div class='del'>-		memcpy(&amp;header.addr2, dev-&gt;dev_addr, ETH_ALEN);</div><div class='del'>-		memcpy(&amp;header.addr3, priv-&gt;BSSID, ETH_ALEN);</div><div class='del'>-	} else {</div><div class='del'>-		frame_ctl |= IEEE80211_FCTL_TODS;</div><div class='del'>-		memcpy(&amp;header.addr1, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-		memcpy(&amp;header.addr2, dev-&gt;dev_addr, ETH_ALEN);</div><div class='del'>-		skb_copy_from_linear_data(skb, &amp;header.addr3, ETH_ALEN);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;use_wpa)</div><div class='del'>-		memcpy(&amp;header.addr4, rfc1042_header, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	header.frame_control = cpu_to_le16(frame_ctl);</div><div class='del'>-	/* Copy the wireless header into the card */</div><div class='del'>-	atmel_copy_to_card(dev, buff, (unsigned char *)&amp;header, DATA_FRAME_WS_HEADER_SIZE);</div><div class='del'>-	/* Copy the packet sans its 802.3 header addresses which have been replaced */</div><div class='del'>-	atmel_copy_to_card(dev, buff + DATA_FRAME_WS_HEADER_SIZE, skb-&gt;data + 12, len - 12);</div><div class='del'>-	priv-&gt;tx_buff_tail += len - 12 + DATA_FRAME_WS_HEADER_SIZE;</div><div class='del'>-</div><div class='del'>-	/* low bit of first byte of destination tells us if broadcast */</div><div class='del'>-	tx_update_descriptor(priv, *(skb-&gt;data) &amp; 0x01, len + 18, buff, TX_PACKET_TYPE_DATA);</div><div class='del'>-	dev-&gt;stats.tx_bytes += len;</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-	spin_unlock_bh(&amp;priv-&gt;timerlock);</div><div class='del'>-	dev_kfree_skb(skb);</div><div class='del'>-</div><div class='del'>-	return NETDEV_TX_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_transmit_management_frame(struct atmel_private *priv,</div><div class='del'>-					    struct ieee80211_hdr *header,</div><div class='del'>-					    u8 *body, int body_len)</div><div class='del'>-{</div><div class='del'>-	u16 buff;</div><div class='del'>-	int len = MGMT_FRAME_BODY_OFFSET + body_len;</div><div class='del'>-</div><div class='del'>-	if (!(buff = find_tx_buff(priv, len)))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	atmel_copy_to_card(priv-&gt;dev, buff, (u8 *)header, MGMT_FRAME_BODY_OFFSET);</div><div class='del'>-	atmel_copy_to_card(priv-&gt;dev, buff + MGMT_FRAME_BODY_OFFSET, body, body_len);</div><div class='del'>-	priv-&gt;tx_buff_tail += len;</div><div class='del'>-	tx_update_descriptor(priv, header-&gt;addr1[0] &amp; 0x01, len, buff, TX_PACKET_TYPE_MGMT);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void fast_rx_path(struct atmel_private *priv,</div><div class='del'>-			 struct ieee80211_hdr *header,</div><div class='del'>-			 u16 msdu_size, u16 rx_packet_loc, u32 crc)</div><div class='del'>-{</div><div class='del'>-	/* fast path: unfragmented packet copy directly into skbuf */</div><div class='del'>-	u8 mac4[6];</div><div class='del'>-	struct sk_buff	*skb;</div><div class='del'>-	unsigned char *skbp;</div><div class='del'>-</div><div class='del'>-	/* get the final, mac 4 header field, this tells us encapsulation */</div><div class='del'>-	atmel_copy_to_host(priv-&gt;dev, mac4, rx_packet_loc + 24, 6);</div><div class='del'>-	msdu_size -= 6;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;do_rx_crc) {</div><div class='del'>-		crc = crc32_le(crc, mac4, 6);</div><div class='del'>-		msdu_size -= 4;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!(skb = dev_alloc_skb(msdu_size + 14))) {</div><div class='del'>-		priv-&gt;dev-&gt;stats.rx_dropped++;</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	skb_reserve(skb, 2);</div><div class='del'>-	skbp = skb_put(skb, msdu_size + 12);</div><div class='del'>-	atmel_copy_to_host(priv-&gt;dev, skbp + 12, rx_packet_loc + 30, msdu_size);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;do_rx_crc) {</div><div class='del'>-		u32 netcrc;</div><div class='del'>-		crc = crc32_le(crc, skbp + 12, msdu_size);</div><div class='del'>-		atmel_copy_to_host(priv-&gt;dev, (void *)&amp;netcrc, rx_packet_loc + 30 + msdu_size, 4);</div><div class='del'>-		if ((crc ^ 0xffffffff) != netcrc) {</div><div class='del'>-			priv-&gt;dev-&gt;stats.rx_crc_errors++;</div><div class='del'>-			dev_kfree_skb(skb);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memcpy(skbp, header-&gt;addr1, ETH_ALEN); /* destination address */</div><div class='del'>-	if (le16_to_cpu(header-&gt;frame_control) &amp; IEEE80211_FCTL_FROMDS)</div><div class='del'>-		memcpy(&amp;skbp[ETH_ALEN], header-&gt;addr3, ETH_ALEN);</div><div class='del'>-	else</div><div class='del'>-		memcpy(&amp;skbp[ETH_ALEN], header-&gt;addr2, ETH_ALEN); /* source address */</div><div class='del'>-</div><div class='del'>-	skb-&gt;protocol = eth_type_trans(skb, priv-&gt;dev);</div><div class='del'>-	skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='del'>-	netif_rx(skb);</div><div class='del'>-	priv-&gt;dev-&gt;stats.rx_bytes += 12 + msdu_size;</div><div class='del'>-	priv-&gt;dev-&gt;stats.rx_packets++;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Test to see if the packet in card memory at packet_loc has a valid CRC</div><div class='del'>-   It doesn't matter that this is slow: it is only used to proble the first few</div><div class='del'>-   packets. */</div><div class='del'>-static int probe_crc(struct atmel_private *priv, u16 packet_loc, u16 msdu_size)</div><div class='del'>-{</div><div class='del'>-	int i = msdu_size - 4;</div><div class='del'>-	u32 netcrc, crc = 0xffffffff;</div><div class='del'>-</div><div class='del'>-	if (msdu_size &lt; 4)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	atmel_copy_to_host(priv-&gt;dev, (void *)&amp;netcrc, packet_loc + i, 4);</div><div class='del'>-</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, packet_loc);</div><div class='del'>-	while (i--) {</div><div class='del'>-		u8 octet = atmel_read8(priv-&gt;dev, DR);</div><div class='del'>-		crc = crc32_le(crc, &amp;octet, 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return (crc ^ 0xffffffff) == netcrc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void frag_rx_path(struct atmel_private *priv,</div><div class='del'>-			 struct ieee80211_hdr *header,</div><div class='del'>-			 u16 msdu_size, u16 rx_packet_loc, u32 crc, u16 seq_no,</div><div class='del'>-			 u8 frag_no, int more_frags)</div><div class='del'>-{</div><div class='del'>-	u8 mac4[ETH_ALEN];</div><div class='del'>-	u8 source[ETH_ALEN];</div><div class='del'>-	struct sk_buff *skb;</div><div class='del'>-</div><div class='del'>-	if (le16_to_cpu(header-&gt;frame_control) &amp; IEEE80211_FCTL_FROMDS)</div><div class='del'>-		memcpy(source, header-&gt;addr3, ETH_ALEN);</div><div class='del'>-	else</div><div class='del'>-		memcpy(source, header-&gt;addr2, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	rx_packet_loc += 24; /* skip header */</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;do_rx_crc)</div><div class='del'>-		msdu_size -= 4;</div><div class='del'>-</div><div class='del'>-	if (frag_no == 0) { /* first fragment */</div><div class='del'>-		atmel_copy_to_host(priv-&gt;dev, mac4, rx_packet_loc, ETH_ALEN);</div><div class='del'>-		msdu_size -= ETH_ALEN;</div><div class='del'>-		rx_packet_loc += ETH_ALEN;</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;do_rx_crc)</div><div class='del'>-			crc = crc32_le(crc, mac4, 6);</div><div class='del'>-</div><div class='del'>-		priv-&gt;frag_seq = seq_no;</div><div class='del'>-		priv-&gt;frag_no = 1;</div><div class='del'>-		priv-&gt;frag_len = msdu_size;</div><div class='del'>-		memcpy(priv-&gt;frag_source, source, ETH_ALEN);</div><div class='del'>-		memcpy(&amp;priv-&gt;rx_buf[ETH_ALEN], source, ETH_ALEN);</div><div class='del'>-		memcpy(priv-&gt;rx_buf, header-&gt;addr1, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-		atmel_copy_to_host(priv-&gt;dev, &amp;priv-&gt;rx_buf[12], rx_packet_loc, msdu_size);</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;do_rx_crc) {</div><div class='del'>-			u32 netcrc;</div><div class='del'>-			crc = crc32_le(crc, &amp;priv-&gt;rx_buf[12], msdu_size);</div><div class='del'>-			atmel_copy_to_host(priv-&gt;dev, (void *)&amp;netcrc, rx_packet_loc + msdu_size, 4);</div><div class='del'>-			if ((crc ^ 0xffffffff) != netcrc) {</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_crc_errors++;</div><div class='del'>-				eth_broadcast_addr(priv-&gt;frag_source);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	} else if (priv-&gt;frag_no == frag_no &amp;&amp;</div><div class='del'>-		   priv-&gt;frag_seq == seq_no &amp;&amp;</div><div class='del'>-		   memcmp(priv-&gt;frag_source, source, ETH_ALEN) == 0) {</div><div class='del'>-</div><div class='del'>-		atmel_copy_to_host(priv-&gt;dev, &amp;priv-&gt;rx_buf[12 + priv-&gt;frag_len],</div><div class='del'>-				   rx_packet_loc, msdu_size);</div><div class='del'>-		if (priv-&gt;do_rx_crc) {</div><div class='del'>-			u32 netcrc;</div><div class='del'>-			crc = crc32_le(crc,</div><div class='del'>-				       &amp;priv-&gt;rx_buf[12 + priv-&gt;frag_len],</div><div class='del'>-				       msdu_size);</div><div class='del'>-			atmel_copy_to_host(priv-&gt;dev, (void *)&amp;netcrc, rx_packet_loc + msdu_size, 4);</div><div class='del'>-			if ((crc ^ 0xffffffff) != netcrc) {</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_crc_errors++;</div><div class='del'>-				eth_broadcast_addr(priv-&gt;frag_source);</div><div class='del'>-				more_frags = 1; /* don't send broken assembly */</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		priv-&gt;frag_len += msdu_size;</div><div class='del'>-		priv-&gt;frag_no++;</div><div class='del'>-</div><div class='del'>-		if (!more_frags) { /* last one */</div><div class='del'>-			eth_broadcast_addr(priv-&gt;frag_source);</div><div class='del'>-			if (!(skb = dev_alloc_skb(priv-&gt;frag_len + 14))) {</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_dropped++;</div><div class='del'>-			} else {</div><div class='del'>-				skb_reserve(skb, 2);</div><div class='del'>-				skb_put_data(skb, priv-&gt;rx_buf,</div><div class='del'>-				             priv-&gt;frag_len + 12);</div><div class='del'>-				skb-&gt;protocol = eth_type_trans(skb, priv-&gt;dev);</div><div class='del'>-				skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='del'>-				netif_rx(skb);</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_bytes += priv-&gt;frag_len + 12;</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_packets++;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	} else</div><div class='del'>-		priv-&gt;wstats.discard.fragment++;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void rx_done_irq(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct ieee80211_hdr header;</div><div class='del'>-</div><div class='del'>-	for (i = 0;</div><div class='del'>-	     atmel_rmem8(priv, atmel_rx(priv, RX_DESC_FLAGS_OFFSET, priv-&gt;rx_desc_head)) == RX_DESC_FLAG_VALID &amp;&amp;</div><div class='del'>-		     i &lt; priv-&gt;host_info.rx_desc_count;</div><div class='del'>-	     i++) {</div><div class='del'>-</div><div class='del'>-		u16 msdu_size, rx_packet_loc, frame_ctl, seq_control;</div><div class='del'>-		u8 status = atmel_rmem8(priv, atmel_rx(priv, RX_DESC_STATUS_OFFSET, priv-&gt;rx_desc_head));</div><div class='del'>-		u32 crc = 0xffffffff;</div><div class='del'>-</div><div class='del'>-		if (status != RX_STATUS_SUCCESS) {</div><div class='del'>-			if (status == 0xc1) /* determined by experiment */</div><div class='del'>-				priv-&gt;wstats.discard.nwid++;</div><div class='del'>-			else</div><div class='del'>-				priv-&gt;dev-&gt;stats.rx_errors++;</div><div class='del'>-			goto next;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		msdu_size = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_SIZE_OFFSET, priv-&gt;rx_desc_head));</div><div class='del'>-		rx_packet_loc = atmel_rmem16(priv, atmel_rx(priv, RX_DESC_MSDU_POS_OFFSET, priv-&gt;rx_desc_head));</div><div class='del'>-</div><div class='del'>-		if (msdu_size &lt; 30) {</div><div class='del'>-			priv-&gt;dev-&gt;stats.rx_errors++;</div><div class='del'>-			goto next;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Get header as far as end of seq_ctrl */</div><div class='del'>-		atmel_copy_to_host(priv-&gt;dev, (char *)&amp;header, rx_packet_loc, 24);</div><div class='del'>-		frame_ctl = le16_to_cpu(header.frame_control);</div><div class='del'>-		seq_control = le16_to_cpu(header.seq_ctrl);</div><div class='del'>-</div><div class='del'>-		/* probe for CRC use here if needed  once five packets have</div><div class='del'>-		   arrived with the same crc status, we assume we know what's</div><div class='del'>-		   happening and stop probing */</div><div class='del'>-		if (priv-&gt;probe_crc) {</div><div class='del'>-			if (!priv-&gt;wep_is_on || !(frame_ctl &amp; IEEE80211_FCTL_PROTECTED)) {</div><div class='del'>-				priv-&gt;do_rx_crc = probe_crc(priv, rx_packet_loc, msdu_size);</div><div class='del'>-			} else {</div><div class='del'>-				priv-&gt;do_rx_crc = probe_crc(priv, rx_packet_loc + 24, msdu_size - 24);</div><div class='del'>-			}</div><div class='del'>-			if (priv-&gt;do_rx_crc) {</div><div class='del'>-				if (priv-&gt;crc_ok_cnt++ &gt; 5)</div><div class='del'>-					priv-&gt;probe_crc = 0;</div><div class='del'>-			} else {</div><div class='del'>-				if (priv-&gt;crc_ko_cnt++ &gt; 5)</div><div class='del'>-					priv-&gt;probe_crc = 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* don't CRC header when WEP in use */</div><div class='del'>-		if (priv-&gt;do_rx_crc &amp;&amp; (!priv-&gt;wep_is_on || !(frame_ctl &amp; IEEE80211_FCTL_PROTECTED))) {</div><div class='del'>-			crc = crc32_le(0xffffffff, (unsigned char *)&amp;header, 24);</div><div class='del'>-		}</div><div class='del'>-		msdu_size -= 24; /* header */</div><div class='del'>-</div><div class='del'>-		if ((frame_ctl &amp; IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) {</div><div class='del'>-			int more_fragments = frame_ctl &amp; IEEE80211_FCTL_MOREFRAGS;</div><div class='del'>-			u8 packet_fragment_no = seq_control &amp; IEEE80211_SCTL_FRAG;</div><div class='del'>-			u16 packet_sequence_no = (seq_control &amp; IEEE80211_SCTL_SEQ) &gt;&gt; 4;</div><div class='del'>-</div><div class='del'>-			if (!more_fragments &amp;&amp; packet_fragment_no == 0) {</div><div class='del'>-				fast_rx_path(priv, &amp;header, msdu_size, rx_packet_loc, crc);</div><div class='del'>-			} else {</div><div class='del'>-				frag_rx_path(priv, &amp;header, msdu_size, rx_packet_loc, crc,</div><div class='del'>-					     packet_sequence_no, packet_fragment_no, more_fragments);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if ((frame_ctl &amp; IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {</div><div class='del'>-			/* copy rest of packet into buffer */</div><div class='del'>-			atmel_copy_to_host(priv-&gt;dev, (unsigned char *)&amp;priv-&gt;rx_buf, rx_packet_loc + 24, msdu_size);</div><div class='del'>-</div><div class='del'>-			/* we use the same buffer for frag reassembly and control packets */</div><div class='del'>-			eth_broadcast_addr(priv-&gt;frag_source);</div><div class='del'>-</div><div class='del'>-			if (priv-&gt;do_rx_crc) {</div><div class='del'>-				/* last 4 octets is crc */</div><div class='del'>-				msdu_size -= 4;</div><div class='del'>-				crc = crc32_le(crc, (unsigned char *)&amp;priv-&gt;rx_buf, msdu_size);</div><div class='del'>-				if ((crc ^ 0xffffffff) != (*((u32 *)&amp;priv-&gt;rx_buf[msdu_size]))) {</div><div class='del'>-					priv-&gt;dev-&gt;stats.rx_crc_errors++;</div><div class='del'>-					goto next;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			atmel_management_frame(priv, &amp;header, msdu_size,</div><div class='del'>-					       atmel_rmem8(priv, atmel_rx(priv, RX_DESC_RSSI_OFFSET, priv-&gt;rx_desc_head)));</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-next:</div><div class='del'>-		/* release descriptor */</div><div class='del'>-		atmel_wmem8(priv, atmel_rx(priv, RX_DESC_FLAGS_OFFSET, priv-&gt;rx_desc_head), RX_DESC_FLAG_CONSUMED);</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;rx_desc_head &lt; (priv-&gt;host_info.rx_desc_count - 1))</div><div class='del'>-			priv-&gt;rx_desc_head++;</div><div class='del'>-		else</div><div class='del'>-			priv-&gt;rx_desc_head = 0;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static irqreturn_t service_interrupt(int irq, void *dev_id)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev = (struct net_device *) dev_id;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	u8 isr;</div><div class='del'>-	int i = -1;</div><div class='del'>-	static const u8 irq_order[] = {</div><div class='del'>-		ISR_OUT_OF_RANGE,</div><div class='del'>-		ISR_RxCOMPLETE,</div><div class='del'>-		ISR_TxCOMPLETE,</div><div class='del'>-		ISR_RxFRAMELOST,</div><div class='del'>-		ISR_FATAL_ERROR,</div><div class='del'>-		ISR_COMMAND_COMPLETE,</div><div class='del'>-		ISR_IBSS_MERGE,</div><div class='del'>-		ISR_GENERIC_IRQ</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;card &amp;&amp; priv-&gt;present_callback &amp;&amp;</div><div class='del'>-	    !(*priv-&gt;present_callback)(priv-&gt;card))</div><div class='del'>-		return IRQ_HANDLED;</div><div class='del'>-</div><div class='del'>-	/* In this state upper-level code assumes it can mess with</div><div class='del'>-	   the card unhampered by interrupts which may change register state.</div><div class='del'>-	   Note that even though the card shouldn't generate interrupts</div><div class='del'>-	   the inturrupt line may be shared. This allows card setup</div><div class='del'>-	   to go on without disabling interrupts for a long time. */</div><div class='del'>-	if (priv-&gt;station_state == STATION_STATE_DOWN)</div><div class='del'>-		return IRQ_NONE;</div><div class='del'>-</div><div class='del'>-	atmel_clear_gcr(dev, GCR_ENINT); /* disable interrupts */</div><div class='del'>-</div><div class='del'>-	while (1) {</div><div class='del'>-		if (!atmel_lock_mac(priv)) {</div><div class='del'>-			/* failed to contact card */</div><div class='del'>-			printk(KERN_ALERT "%s: failed to contact MAC.\n", dev-&gt;name);</div><div class='del'>-			return IRQ_HANDLED;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		isr = atmel_rmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET));</div><div class='del'>-		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);</div><div class='del'>-</div><div class='del'>-		if (!isr) {</div><div class='del'>-			atmel_set_gcr(dev, GCR_ENINT); /* enable interrupts */</div><div class='del'>-			return i == -1 ? IRQ_NONE : IRQ_HANDLED;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		atmel_set_gcr(dev, GCR_ACKINT); /* acknowledge interrupt */</div><div class='del'>-</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(irq_order); i++)</div><div class='del'>-			if (isr &amp; irq_order[i])</div><div class='del'>-				break;</div><div class='del'>-</div><div class='del'>-		if (!atmel_lock_mac(priv)) {</div><div class='del'>-			/* failed to contact card */</div><div class='del'>-			printk(KERN_ALERT "%s: failed to contact MAC.\n", dev-&gt;name);</div><div class='del'>-			return IRQ_HANDLED;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		isr = atmel_rmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET));</div><div class='del'>-		isr ^= irq_order[i];</div><div class='del'>-		atmel_wmem8(priv, atmel_hi(priv, IFACE_INT_STATUS_OFFSET), isr);</div><div class='del'>-		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);</div><div class='del'>-</div><div class='del'>-		switch (irq_order[i]) {</div><div class='del'>-</div><div class='del'>-		case ISR_OUT_OF_RANGE:</div><div class='del'>-			if (priv-&gt;operating_mode == IW_MODE_INFRA &amp;&amp;</div><div class='del'>-			    priv-&gt;station_state == STATION_STATE_READY) {</div><div class='del'>-				priv-&gt;station_is_associated = 0;</div><div class='del'>-				atmel_scan(priv, 1);</div><div class='del'>-			}</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		case ISR_RxFRAMELOST:</div><div class='del'>-			priv-&gt;wstats.discard.misc++;</div><div class='del'>-			fallthrough;</div><div class='del'>-		case ISR_RxCOMPLETE:</div><div class='del'>-			rx_done_irq(priv);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		case ISR_TxCOMPLETE:</div><div class='del'>-			tx_done_irq(priv);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		case ISR_FATAL_ERROR:</div><div class='del'>-			printk(KERN_ALERT "%s: *** FATAL error interrupt ***\n", dev-&gt;name);</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		case ISR_COMMAND_COMPLETE:</div><div class='del'>-			atmel_command_irq(priv);</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		case ISR_IBSS_MERGE:</div><div class='del'>-			atmel_get_mib(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_BSSID_POS,</div><div class='del'>-				      priv-&gt;CurrentBSSID, 6);</div><div class='del'>-			/* The WPA stuff cares about the current AP address */</div><div class='del'>-			if (priv-&gt;use_wpa)</div><div class='del'>-				build_wpa_mib(priv);</div><div class='del'>-			break;</div><div class='del'>-		case ISR_GENERIC_IRQ:</div><div class='del'>-			printk(KERN_INFO "%s: Generic_irq received.\n", dev-&gt;name);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct iw_statistics *atmel_get_wireless_stats(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* update the link quality here in case we are seeing no beacons</div><div class='del'>-	   at all to drive the process */</div><div class='del'>-	atmel_smooth_qual(priv);</div><div class='del'>-</div><div class='del'>-	priv-&gt;wstats.status = priv-&gt;station_state;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;operating_mode == IW_MODE_INFRA) {</div><div class='del'>-		if (priv-&gt;station_state != STATION_STATE_READY) {</div><div class='del'>-			priv-&gt;wstats.qual.qual = 0;</div><div class='del'>-			priv-&gt;wstats.qual.level = 0;</div><div class='del'>-			priv-&gt;wstats.qual.updated = (IW_QUAL_QUAL_INVALID</div><div class='del'>-					| IW_QUAL_LEVEL_INVALID);</div><div class='del'>-		}</div><div class='del'>-		priv-&gt;wstats.qual.noise = 0;</div><div class='del'>-		priv-&gt;wstats.qual.updated |= IW_QUAL_NOISE_INVALID;</div><div class='del'>-	} else {</div><div class='del'>-		/* Quality levels cannot be determined in ad-hoc mode,</div><div class='del'>-		   because we can 'hear' more that one remote station. */</div><div class='del'>-		priv-&gt;wstats.qual.qual = 0;</div><div class='del'>-		priv-&gt;wstats.qual.level	= 0;</div><div class='del'>-		priv-&gt;wstats.qual.noise	= 0;</div><div class='del'>-		priv-&gt;wstats.qual.updated = IW_QUAL_QUAL_INVALID</div><div class='del'>-					| IW_QUAL_LEVEL_INVALID</div><div class='del'>-					| IW_QUAL_NOISE_INVALID;</div><div class='del'>-		priv-&gt;wstats.miss.beacon = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return &amp;priv-&gt;wstats;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_mac_address(struct net_device *dev, void *p)</div><div class='del'>-{</div><div class='del'>-	struct sockaddr *addr = p;</div><div class='del'>-</div><div class='del'>-	eth_hw_addr_set(dev, addr-&gt;sa_data);</div><div class='del'>-	return atmel_open(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(atmel_open);</div><div class='del'>-</div><div class='del'>-int atmel_open(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int i, channel, err;</div><div class='del'>-</div><div class='del'>-	/* any scheduled timer is no longer needed and might screw things up.. */</div><div class='del'>-	del_timer_sync(&amp;priv-&gt;management_timer);</div><div class='del'>-</div><div class='del'>-	/* Interrupts will not touch the card once in this state... */</div><div class='del'>-	priv-&gt;station_state = STATION_STATE_DOWN;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;new_SSID_size) {</div><div class='del'>-		memcpy(priv-&gt;SSID, priv-&gt;new_SSID, priv-&gt;new_SSID_size);</div><div class='del'>-		priv-&gt;SSID_size = priv-&gt;new_SSID_size;</div><div class='del'>-		priv-&gt;new_SSID_size = 0;</div><div class='del'>-	}</div><div class='del'>-	priv-&gt;BSS_list_entries = 0;</div><div class='del'>-</div><div class='del'>-	priv-&gt;AuthenticationRequestRetryCnt = 0;</div><div class='del'>-	priv-&gt;AssociationRequestRetryCnt = 0;</div><div class='del'>-	priv-&gt;ReAssociationRequestRetryCnt = 0;</div><div class='del'>-	priv-&gt;CurrentAuthentTransactionSeqNum = 0x0001;</div><div class='del'>-	priv-&gt;ExpectedAuthentTransactionSeqNum = 0x0002;</div><div class='del'>-</div><div class='del'>-	priv-&gt;site_survey_state = SITE_SURVEY_IDLE;</div><div class='del'>-	priv-&gt;station_is_associated = 0;</div><div class='del'>-</div><div class='del'>-	err = reset_atmel_card(dev);</div><div class='del'>-	if (err)</div><div class='del'>-		return err;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;config_reg_domain) {</div><div class='del'>-		priv-&gt;reg_domain = priv-&gt;config_reg_domain;</div><div class='del'>-		atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS, priv-&gt;reg_domain);</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;reg_domain = atmel_get_mib8(priv, Phy_Mib_Type, PHY_MIB_REG_DOMAIN_POS);</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(channel_table); i++)</div><div class='del'>-			if (priv-&gt;reg_domain == channel_table[i].reg_domain)</div><div class='del'>-				break;</div><div class='del'>-		if (i == ARRAY_SIZE(channel_table)) {</div><div class='del'>-			priv-&gt;reg_domain = REG_DOMAIN_MKK1;</div><div class='del'>-			printk(KERN_ALERT "%s: failed to get regulatory domain: assuming MKK1.\n", dev-&gt;name);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if ((channel = atmel_validate_channel(priv, priv-&gt;channel)))</div><div class='del'>-		priv-&gt;channel = channel;</div><div class='del'>-</div><div class='del'>-	/* this moves station_state on.... */</div><div class='del'>-	atmel_scan(priv, 1);</div><div class='del'>-</div><div class='del'>-	atmel_set_gcr(priv-&gt;dev, GCR_ENINT); /* enable interrupts */</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_close(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* Send event to userspace that we are disassociating */</div><div class='del'>-	if (priv-&gt;station_state == STATION_STATE_READY) {</div><div class='del'>-		union iwreq_data wrqu;</div><div class='del'>-</div><div class='del'>-		wrqu.data.length = 0;</div><div class='del'>-		wrqu.data.flags = 0;</div><div class='del'>-		wrqu.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-		eth_zero_addr(wrqu.ap_addr.sa_data);</div><div class='del'>-		wireless_send_event(priv-&gt;dev, SIOCGIWAP, &amp;wrqu, NULL);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	atmel_enter_state(priv, STATION_STATE_DOWN);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-		atmel_write16(dev, GCR, 0x0060);</div><div class='del'>-	atmel_write16(dev, GCR, 0x0040);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_validate_channel(struct atmel_private *priv, int channel)</div><div class='del'>-{</div><div class='del'>-	/* check that channel is OK, if so return zero,</div><div class='del'>-	   else return suitable default channel */</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; ARRAY_SIZE(channel_table); i++)</div><div class='del'>-		if (priv-&gt;reg_domain == channel_table[i].reg_domain) {</div><div class='del'>-			if (channel &gt;= channel_table[i].min &amp;&amp;</div><div class='del'>-			    channel &lt;= channel_table[i].max)</div><div class='del'>-				return 0;</div><div class='del'>-			else</div><div class='del'>-				return channel_table[i].min;</div><div class='del'>-		}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_PROC_FS</div><div class='del'>-static int atmel_proc_show(struct seq_file *m, void *v)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = m-&gt;private;</div><div class='del'>-	int i;</div><div class='del'>-	char *s, *r, *c;</div><div class='del'>-</div><div class='del'>-	seq_printf(m, "Driver version:\t\t%d.%d\n", DRIVER_MAJOR, DRIVER_MINOR);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;station_state != STATION_STATE_DOWN) {</div><div class='del'>-		seq_printf(m,</div><div class='del'>-			   "Firmware version:\t%d.%d build %d\n"</div><div class='del'>-			   "Firmware location:\t",</div><div class='del'>-			   priv-&gt;host_info.major_version,</div><div class='del'>-			   priv-&gt;host_info.minor_version,</div><div class='del'>-			   priv-&gt;host_info.build_version);</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;card_type != CARD_TYPE_EEPROM)</div><div class='del'>-			seq_puts(m, "on card\n");</div><div class='del'>-		else if (priv-&gt;firmware)</div><div class='del'>-			seq_printf(m, "%s loaded by host\n", priv-&gt;firmware_id);</div><div class='del'>-		else</div><div class='del'>-			seq_printf(m, "%s loaded by hotplug\n", priv-&gt;firmware_id);</div><div class='del'>-</div><div class='del'>-		switch (priv-&gt;card_type) {</div><div class='del'>-		case CARD_TYPE_PARALLEL_FLASH:</div><div class='del'>-			c = "Parallel flash";</div><div class='del'>-			break;</div><div class='del'>-		case CARD_TYPE_SPI_FLASH:</div><div class='del'>-			c = "SPI flash\n";</div><div class='del'>-			break;</div><div class='del'>-		case CARD_TYPE_EEPROM:</div><div class='del'>-			c = "EEPROM";</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			c = "&lt;unknown&gt;";</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		r = "&lt;unknown&gt;";</div><div class='del'>-		for (i = 0; i &lt; ARRAY_SIZE(channel_table); i++)</div><div class='del'>-			if (priv-&gt;reg_domain == channel_table[i].reg_domain)</div><div class='del'>-				r = channel_table[i].name;</div><div class='del'>-</div><div class='del'>-		seq_printf(m, "MAC memory type:\t%s\n", c);</div><div class='del'>-		seq_printf(m, "Regulatory domain:\t%s\n", r);</div><div class='del'>-		seq_printf(m, "Host CRC checking:\t%s\n",</div><div class='del'>-			 priv-&gt;do_rx_crc ? "On" : "Off");</div><div class='del'>-		seq_printf(m, "WPA-capable firmware:\t%s\n",</div><div class='del'>-			 priv-&gt;use_wpa ? "Yes" : "No");</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	switch (priv-&gt;station_state) {</div><div class='del'>-	case STATION_STATE_SCANNING:</div><div class='del'>-		s = "Scanning";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_JOINNING:</div><div class='del'>-		s = "Joining";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_AUTHENTICATING:</div><div class='del'>-		s = "Authenticating";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_ASSOCIATING:</div><div class='del'>-		s = "Associating";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_READY:</div><div class='del'>-		s = "Ready";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_REASSOCIATING:</div><div class='del'>-		s = "Reassociating";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_MGMT_ERROR:</div><div class='del'>-		s = "Management error";</div><div class='del'>-		break;</div><div class='del'>-	case STATION_STATE_DOWN:</div><div class='del'>-		s = "Down";</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		s = "&lt;unknown&gt;";</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	seq_printf(m, "Current state:\t\t%s\n", s);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-static const struct net_device_ops atmel_netdev_ops = {</div><div class='del'>-	.ndo_open 		= atmel_open,</div><div class='del'>-	.ndo_stop		= atmel_close,</div><div class='del'>-	.ndo_set_mac_address 	= atmel_set_mac_address,</div><div class='del'>-	.ndo_start_xmit 	= start_tx,</div><div class='del'>-	.ndo_validate_addr	= eth_validate_addr,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct net_device *init_atmel_card(unsigned short irq, unsigned long port,</div><div class='del'>-				   const AtmelFWType fw_type,</div><div class='del'>-				   struct device *sys_dev,</div><div class='del'>-				   int (*card_present)(void *), void *card)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev;</div><div class='del'>-	struct atmel_private *priv;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	/* Create the network device object. */</div><div class='del'>-	dev = alloc_etherdev(sizeof(*priv));</div><div class='del'>-	if (!dev)</div><div class='del'>-		return NULL;</div><div class='del'>-</div><div class='del'>-	if (dev_alloc_name(dev, dev-&gt;name) &lt; 0) {</div><div class='del'>-		printk(KERN_ERR "atmel: Couldn't get name!\n");</div><div class='del'>-		goto err_out_free;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	priv = netdev_priv(dev);</div><div class='del'>-	priv-&gt;dev = dev;</div><div class='del'>-	priv-&gt;sys_dev = sys_dev;</div><div class='del'>-	priv-&gt;present_callback = card_present;</div><div class='del'>-	priv-&gt;card = card;</div><div class='del'>-	priv-&gt;firmware = NULL;</div><div class='del'>-	priv-&gt;firmware_type = fw_type;</div><div class='del'>-	if (firmware) /* module parameter */</div><div class='del'>-		strscpy(priv-&gt;firmware_id, firmware, sizeof(priv-&gt;firmware_id));</div><div class='del'>-	priv-&gt;bus_type = card_present ? BUS_TYPE_PCCARD : BUS_TYPE_PCI;</div><div class='del'>-	priv-&gt;station_state = STATION_STATE_DOWN;</div><div class='del'>-	priv-&gt;do_rx_crc = 0;</div><div class='del'>-	/* For PCMCIA cards, some chips need CRC, some don't</div><div class='del'>-	   so we have to probe. */</div><div class='del'>-	if (priv-&gt;bus_type == BUS_TYPE_PCCARD) {</div><div class='del'>-		priv-&gt;probe_crc = 1;</div><div class='del'>-		priv-&gt;crc_ok_cnt = priv-&gt;crc_ko_cnt = 0;</div><div class='del'>-	} else</div><div class='del'>-		priv-&gt;probe_crc = 0;</div><div class='del'>-	priv-&gt;last_qual = jiffies;</div><div class='del'>-	priv-&gt;last_beacon_timestamp = 0;</div><div class='del'>-	memset(priv-&gt;frag_source, 0xff, sizeof(priv-&gt;frag_source));</div><div class='del'>-	eth_zero_addr(priv-&gt;BSSID);</div><div class='del'>-	priv-&gt;CurrentBSSID[0] = 0xFF; /* Initialize to something invalid.... */</div><div class='del'>-	priv-&gt;station_was_associated = 0;</div><div class='del'>-</div><div class='del'>-	priv-&gt;last_survey = jiffies;</div><div class='del'>-	priv-&gt;preamble = LONG_PREAMBLE;</div><div class='del'>-	priv-&gt;operating_mode = IW_MODE_INFRA;</div><div class='del'>-	priv-&gt;connect_to_any_BSS = 0;</div><div class='del'>-	priv-&gt;config_reg_domain = 0;</div><div class='del'>-	priv-&gt;reg_domain = 0;</div><div class='del'>-	priv-&gt;tx_rate = 3;</div><div class='del'>-	priv-&gt;auto_tx_rate = 1;</div><div class='del'>-	priv-&gt;channel = 4;</div><div class='del'>-	priv-&gt;power_mode = 0;</div><div class='del'>-	priv-&gt;SSID[0] = '\0';</div><div class='del'>-	priv-&gt;SSID_size = 0;</div><div class='del'>-	priv-&gt;new_SSID_size = 0;</div><div class='del'>-	priv-&gt;frag_threshold = 2346;</div><div class='del'>-	priv-&gt;rts_threshold = 2347;</div><div class='del'>-	priv-&gt;short_retry = 7;</div><div class='del'>-	priv-&gt;long_retry = 4;</div><div class='del'>-</div><div class='del'>-	priv-&gt;wep_is_on = 0;</div><div class='del'>-	priv-&gt;default_key = 0;</div><div class='del'>-	priv-&gt;encryption_level = 0;</div><div class='del'>-	priv-&gt;exclude_unencrypted = 0;</div><div class='del'>-	priv-&gt;group_cipher_suite = priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_NONE;</div><div class='del'>-	priv-&gt;use_wpa = 0;</div><div class='del'>-	memset(priv-&gt;wep_keys, 0, sizeof(priv-&gt;wep_keys));</div><div class='del'>-	memset(priv-&gt;wep_key_len, 0, sizeof(priv-&gt;wep_key_len));</div><div class='del'>-</div><div class='del'>-	priv-&gt;default_beacon_period = priv-&gt;beacon_period = 100;</div><div class='del'>-	priv-&gt;listen_interval = 1;</div><div class='del'>-</div><div class='del'>-	timer_setup(&amp;priv-&gt;management_timer, atmel_management_timer, 0);</div><div class='del'>-	spin_lock_init(&amp;priv-&gt;irqlock);</div><div class='del'>-	spin_lock_init(&amp;priv-&gt;timerlock);</div><div class='del'>-</div><div class='del'>-	dev-&gt;netdev_ops = &amp;atmel_netdev_ops;</div><div class='del'>-	dev-&gt;wireless_handlers = &amp;atmel_handler_def;</div><div class='del'>-	dev-&gt;irq = irq;</div><div class='del'>-	dev-&gt;base_addr = port;</div><div class='del'>-</div><div class='del'>-	/* MTU range: 68 - 2312 */</div><div class='del'>-	dev-&gt;min_mtu = 68;</div><div class='del'>-	dev-&gt;max_mtu = MAX_WIRELESS_BODY - ETH_FCS_LEN;</div><div class='del'>-</div><div class='del'>-	SET_NETDEV_DEV(dev, sys_dev);</div><div class='del'>-</div><div class='del'>-	if ((rc = request_irq(dev-&gt;irq, service_interrupt, IRQF_SHARED, dev-&gt;name, dev))) {</div><div class='del'>-		printk(KERN_ERR "%s: register interrupt %d failed, rc %d\n", dev-&gt;name, irq, rc);</div><div class='del'>-		goto err_out_free;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!request_region(dev-&gt;base_addr, 32,</div><div class='del'>-			    priv-&gt;bus_type == BUS_TYPE_PCCARD ?  "atmel_cs" : "atmel_pci")) {</div><div class='del'>-		goto err_out_irq;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (register_netdev(dev))</div><div class='del'>-		goto err_out_res;</div><div class='del'>-</div><div class='del'>-	if (!probe_atmel_card(dev)) {</div><div class='del'>-		unregister_netdev(dev);</div><div class='del'>-		goto err_out_res;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	netif_carrier_off(dev);</div><div class='del'>-</div><div class='del'>-	if (!proc_create_single_data("driver/atmel", 0, NULL, atmel_proc_show,</div><div class='del'>-			priv))</div><div class='del'>-		printk(KERN_WARNING "atmel: unable to create /proc entry.\n");</div><div class='del'>-</div><div class='del'>-	printk(KERN_INFO "%s: Atmel at76c50x. Version %d.%d. MAC %pM\n",</div><div class='del'>-	       dev-&gt;name, DRIVER_MAJOR, DRIVER_MINOR, dev-&gt;dev_addr);</div><div class='del'>-</div><div class='del'>-	return dev;</div><div class='del'>-</div><div class='del'>-err_out_res:</div><div class='del'>-	release_region(dev-&gt;base_addr, 32);</div><div class='del'>-err_out_irq:</div><div class='del'>-	free_irq(dev-&gt;irq, dev);</div><div class='del'>-err_out_free:</div><div class='del'>-	free_netdev(dev);</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(init_atmel_card);</div><div class='del'>-</div><div class='del'>-void stop_atmel_card(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* put a brick on it... */</div><div class='del'>-	if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-		atmel_write16(dev, GCR, 0x0060);</div><div class='del'>-	atmel_write16(dev, GCR, 0x0040);</div><div class='del'>-</div><div class='del'>-	del_timer_sync(&amp;priv-&gt;management_timer);</div><div class='del'>-	unregister_netdev(dev);</div><div class='del'>-	remove_proc_entry("driver/atmel", NULL);</div><div class='del'>-	free_irq(dev-&gt;irq, dev);</div><div class='del'>-	kfree(priv-&gt;firmware);</div><div class='del'>-	release_region(dev-&gt;base_addr, 32);</div><div class='del'>-	free_netdev(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(stop_atmel_card);</div><div class='del'>-</div><div class='del'>-static int atmel_set_essid(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;essid;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* Check if we asked for `any' */</div><div class='del'>-	if (dwrq-&gt;flags == 0) {</div><div class='del'>-		priv-&gt;connect_to_any_BSS = 1;</div><div class='del'>-	} else {</div><div class='del'>-		int index = (dwrq-&gt;flags &amp; IW_ENCODE_INDEX) - 1;</div><div class='del'>-</div><div class='del'>-		priv-&gt;connect_to_any_BSS = 0;</div><div class='del'>-</div><div class='del'>-		/* Check the size of the string */</div><div class='del'>-		if (dwrq-&gt;length &gt; MAX_SSID_LENGTH)</div><div class='del'>-			 return -E2BIG;</div><div class='del'>-		if (index != 0)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='del'>-		memcpy(priv-&gt;new_SSID, extra, dwrq-&gt;length);</div><div class='del'>-		priv-&gt;new_SSID_size = dwrq-&gt;length;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_essid(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;essid;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* Get the current SSID */</div><div class='del'>-	if (priv-&gt;new_SSID_size != 0) {</div><div class='del'>-		memcpy(extra, priv-&gt;new_SSID, priv-&gt;new_SSID_size);</div><div class='del'>-		dwrq-&gt;length = priv-&gt;new_SSID_size;</div><div class='del'>-	} else {</div><div class='del'>-		memcpy(extra, priv-&gt;SSID, priv-&gt;SSID_size);</div><div class='del'>-		dwrq-&gt;length = priv-&gt;SSID_size;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	dwrq-&gt;flags = !priv-&gt;connect_to_any_BSS; /* active */</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_wap(struct net_device *dev,</div><div class='del'>-			 struct iw_request_info *info,</div><div class='del'>-			 union iwreq_data *wrqu,</div><div class='del'>-			 char *extra)</div><div class='del'>-{</div><div class='del'>-	struct sockaddr *awrq = &amp;wrqu-&gt;ap_addr;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	memcpy(awrq-&gt;sa_data, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-	awrq-&gt;sa_family = ARPHRD_ETHER;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_encode(struct net_device *dev,</div><div class='del'>-			    struct iw_request_info *info,</div><div class='del'>-			    union iwreq_data *wrqu,</div><div class='del'>-			    char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;encoding;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	/* Basic checking: do we have a key to set ?</div><div class='del'>-	 * Note : with the new API, it's impossible to get a NULL pointer.</div><div class='del'>-	 * Therefore, we need to check a key size == 0 instead.</div><div class='del'>-	 * New version of iwconfig properly set the IW_ENCODE_NOKEY flag</div><div class='del'>-	 * when no key is present (only change flags), but older versions</div><div class='del'>-	 * don't do it. - Jean II */</div><div class='del'>-	if (dwrq-&gt;length &gt; 0) {</div><div class='del'>-		int index = (dwrq-&gt;flags &amp; IW_ENCODE_INDEX) - 1;</div><div class='del'>-		int current_index = priv-&gt;default_key;</div><div class='del'>-		/* Check the size of the key */</div><div class='del'>-		if (dwrq-&gt;length &gt; 13) {</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-		/* Check the index (none -&gt; use current) */</div><div class='del'>-		if (index &lt; 0 || index &gt;= 4)</div><div class='del'>-			index = current_index;</div><div class='del'>-		else</div><div class='del'>-			priv-&gt;default_key = index;</div><div class='del'>-		/* Set the length */</div><div class='del'>-		if (dwrq-&gt;length &gt; 5)</div><div class='del'>-			priv-&gt;wep_key_len[index] = 13;</div><div class='del'>-		else</div><div class='del'>-			if (dwrq-&gt;length &gt; 0)</div><div class='del'>-				priv-&gt;wep_key_len[index] = 5;</div><div class='del'>-			else</div><div class='del'>-				/* Disable the key */</div><div class='del'>-				priv-&gt;wep_key_len[index] = 0;</div><div class='del'>-		/* Check if the key is not marked as invalid */</div><div class='del'>-		if (!(dwrq-&gt;flags &amp; IW_ENCODE_NOKEY)) {</div><div class='del'>-			/* Cleanup */</div><div class='del'>-			memset(priv-&gt;wep_keys[index], 0, 13);</div><div class='del'>-			/* Copy the key in the driver */</div><div class='del'>-			memcpy(priv-&gt;wep_keys[index], extra, dwrq-&gt;length);</div><div class='del'>-		}</div><div class='del'>-		/* WE specify that if a valid key is set, encryption</div><div class='del'>-		 * should be enabled (user may turn it off later)</div><div class='del'>-		 * This is also how "iwconfig ethX key on" works */</div><div class='del'>-		if (index == current_index &amp;&amp;</div><div class='del'>-		    priv-&gt;wep_key_len[index] &gt; 0) {</div><div class='del'>-			priv-&gt;wep_is_on = 1;</div><div class='del'>-			priv-&gt;exclude_unencrypted = 1;</div><div class='del'>-			if (priv-&gt;wep_key_len[index] &gt; 5) {</div><div class='del'>-				priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_128;</div><div class='del'>-				priv-&gt;encryption_level = 2;</div><div class='del'>-			} else {</div><div class='del'>-				priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_64;</div><div class='del'>-				priv-&gt;encryption_level = 1;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		/* Do we want to just set the transmit key index ? */</div><div class='del'>-		int index = (dwrq-&gt;flags &amp; IW_ENCODE_INDEX) - 1;</div><div class='del'>-		if (index &gt;= 0 &amp;&amp; index &lt; 4) {</div><div class='del'>-			priv-&gt;default_key = index;</div><div class='del'>-		} else</div><div class='del'>-			/* Don't complain if only change the mode */</div><div class='del'>-			if (!(dwrq-&gt;flags &amp; IW_ENCODE_MODE))</div><div class='del'>-				return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-	/* Read the flags */</div><div class='del'>-	if (dwrq-&gt;flags &amp; IW_ENCODE_DISABLED) {</div><div class='del'>-		priv-&gt;wep_is_on = 0;</div><div class='del'>-		priv-&gt;encryption_level = 0;</div><div class='del'>-		priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_NONE;</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;wep_is_on = 1;</div><div class='del'>-		if (priv-&gt;wep_key_len[priv-&gt;default_key] &gt; 5) {</div><div class='del'>-			priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_128;</div><div class='del'>-			priv-&gt;encryption_level = 2;</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_64;</div><div class='del'>-			priv-&gt;encryption_level = 1;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if (dwrq-&gt;flags &amp; IW_ENCODE_RESTRICTED)</div><div class='del'>-		priv-&gt;exclude_unencrypted = 1;</div><div class='del'>-	if (dwrq-&gt;flags &amp; IW_ENCODE_OPEN)</div><div class='del'>-		priv-&gt;exclude_unencrypted = 0;</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;		/* Call commit handler */</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_encode(struct net_device *dev,</div><div class='del'>-			    struct iw_request_info *info,</div><div class='del'>-			    union iwreq_data *wrqu,</div><div class='del'>-			    char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;encoding;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int index = (dwrq-&gt;flags &amp; IW_ENCODE_INDEX) - 1;</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;wep_is_on)</div><div class='del'>-		dwrq-&gt;flags = IW_ENCODE_DISABLED;</div><div class='del'>-	else {</div><div class='del'>-		if (priv-&gt;exclude_unencrypted)</div><div class='del'>-			dwrq-&gt;flags = IW_ENCODE_RESTRICTED;</div><div class='del'>-		else</div><div class='del'>-			dwrq-&gt;flags = IW_ENCODE_OPEN;</div><div class='del'>-	}</div><div class='del'>-		/* Which key do we want ? -1 -&gt; tx index */</div><div class='del'>-	if (index &lt; 0 || index &gt;= 4)</div><div class='del'>-		index = priv-&gt;default_key;</div><div class='del'>-	dwrq-&gt;flags |= index + 1;</div><div class='del'>-	/* Copy the key to the user buffer */</div><div class='del'>-	dwrq-&gt;length = priv-&gt;wep_key_len[index];</div><div class='del'>-	if (dwrq-&gt;length &gt; 16) {</div><div class='del'>-		dwrq-&gt;length = 0;</div><div class='del'>-	} else {</div><div class='del'>-		memset(extra, 0, 16);</div><div class='del'>-		memcpy(extra, priv-&gt;wep_keys[index], dwrq-&gt;length);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_encodeext(struct net_device *dev,</div><div class='del'>-			    struct iw_request_info *info,</div><div class='del'>-			    union iwreq_data *wrqu,</div><div class='del'>-			    char *extra)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct iw_point *encoding = &amp;wrqu-&gt;encoding;</div><div class='del'>-	struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;</div><div class='del'>-	int idx, key_len, alg = ext-&gt;alg, set_key = 1;</div><div class='del'>-</div><div class='del'>-	/* Determine and validate the key index */</div><div class='del'>-	idx = encoding-&gt;flags &amp; IW_ENCODE_INDEX;</div><div class='del'>-	if (idx) {</div><div class='del'>-		if (idx &lt; 1 || idx &gt; 4)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		idx--;</div><div class='del'>-	} else</div><div class='del'>-		idx = priv-&gt;default_key;</div><div class='del'>-</div><div class='del'>-	if (encoding-&gt;flags &amp; IW_ENCODE_DISABLED)</div><div class='del'>-	    alg = IW_ENCODE_ALG_NONE;</div><div class='del'>-</div><div class='del'>-	if (ext-&gt;ext_flags &amp; IW_ENCODE_EXT_SET_TX_KEY) {</div><div class='del'>-		priv-&gt;default_key = idx;</div><div class='del'>-		set_key = ext-&gt;key_len &gt; 0 ? 1 : 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (set_key) {</div><div class='del'>-		/* Set the requested key first */</div><div class='del'>-		switch (alg) {</div><div class='del'>-		case IW_ENCODE_ALG_NONE:</div><div class='del'>-			priv-&gt;wep_is_on = 0;</div><div class='del'>-			priv-&gt;encryption_level = 0;</div><div class='del'>-			priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_NONE;</div><div class='del'>-			break;</div><div class='del'>-		case IW_ENCODE_ALG_WEP:</div><div class='del'>-			if (ext-&gt;key_len &gt; 5) {</div><div class='del'>-				priv-&gt;wep_key_len[idx] = 13;</div><div class='del'>-				priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_128;</div><div class='del'>-				priv-&gt;encryption_level = 2;</div><div class='del'>-			} else if (ext-&gt;key_len &gt; 0) {</div><div class='del'>-				priv-&gt;wep_key_len[idx] = 5;</div><div class='del'>-				priv-&gt;pairwise_cipher_suite = CIPHER_SUITE_WEP_64;</div><div class='del'>-				priv-&gt;encryption_level = 1;</div><div class='del'>-			} else {</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			}</div><div class='del'>-			priv-&gt;wep_is_on = 1;</div><div class='del'>-			memset(priv-&gt;wep_keys[idx], 0, 13);</div><div class='del'>-			key_len = min ((int)ext-&gt;key_len, priv-&gt;wep_key_len[idx]);</div><div class='del'>-			memcpy(priv-&gt;wep_keys[idx], ext-&gt;key, key_len);</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_encodeext(struct net_device *dev,</div><div class='del'>-			    struct iw_request_info *info,</div><div class='del'>-			    union iwreq_data *wrqu,</div><div class='del'>-			    char *extra)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct iw_point *encoding = &amp;wrqu-&gt;encoding;</div><div class='del'>-	struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;</div><div class='del'>-	int idx, max_key_len;</div><div class='del'>-</div><div class='del'>-	max_key_len = encoding-&gt;length - sizeof(*ext);</div><div class='del'>-	if (max_key_len &lt; 0)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	idx = encoding-&gt;flags &amp; IW_ENCODE_INDEX;</div><div class='del'>-	if (idx) {</div><div class='del'>-		if (idx &lt; 1 || idx &gt; 4)</div><div class='del'>-			return -EINVAL;</div><div class='del'>-		idx--;</div><div class='del'>-	} else</div><div class='del'>-		idx = priv-&gt;default_key;</div><div class='del'>-</div><div class='del'>-	encoding-&gt;flags = idx + 1;</div><div class='del'>-	memset(ext, 0, sizeof(*ext));</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;wep_is_on) {</div><div class='del'>-		ext-&gt;alg = IW_ENCODE_ALG_NONE;</div><div class='del'>-		ext-&gt;key_len = 0;</div><div class='del'>-		encoding-&gt;flags |= IW_ENCODE_DISABLED;</div><div class='del'>-	} else {</div><div class='del'>-		if (priv-&gt;encryption_level &gt; 0)</div><div class='del'>-			ext-&gt;alg = IW_ENCODE_ALG_WEP;</div><div class='del'>-		else</div><div class='del'>-			return -EINVAL;</div><div class='del'>-</div><div class='del'>-		ext-&gt;key_len = priv-&gt;wep_key_len[idx];</div><div class='del'>-		memcpy(ext-&gt;key, priv-&gt;wep_keys[idx], ext-&gt;key_len);</div><div class='del'>-		encoding-&gt;flags |= IW_ENCODE_ENABLED;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_auth(struct net_device *dev,</div><div class='del'>-			       struct iw_request_info *info,</div><div class='del'>-			       union iwreq_data *wrqu, char *extra)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct iw_param *param = &amp;wrqu-&gt;param;</div><div class='del'>-</div><div class='del'>-	switch (param-&gt;flags &amp; IW_AUTH_INDEX) {</div><div class='del'>-	case IW_AUTH_WPA_VERSION:</div><div class='del'>-	case IW_AUTH_CIPHER_PAIRWISE:</div><div class='del'>-	case IW_AUTH_CIPHER_GROUP:</div><div class='del'>-	case IW_AUTH_KEY_MGMT:</div><div class='del'>-	case IW_AUTH_RX_UNENCRYPTED_EAPOL:</div><div class='del'>-	case IW_AUTH_PRIVACY_INVOKED:</div><div class='del'>-		/*</div><div class='del'>-		 * atmel does not use these parameters</div><div class='del'>-		 */</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IW_AUTH_DROP_UNENCRYPTED:</div><div class='del'>-		priv-&gt;exclude_unencrypted = param-&gt;value ? 1 : 0;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IW_AUTH_80211_AUTH_ALG: {</div><div class='del'>-			if (param-&gt;value &amp; IW_AUTH_ALG_SHARED_KEY) {</div><div class='del'>-				priv-&gt;exclude_unencrypted = 1;</div><div class='del'>-			} else if (param-&gt;value &amp; IW_AUTH_ALG_OPEN_SYSTEM) {</div><div class='del'>-				priv-&gt;exclude_unencrypted = 0;</div><div class='del'>-			} else</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-	case IW_AUTH_WPA_ENABLED:</div><div class='del'>-		/* Silently accept disable of WPA */</div><div class='del'>-		if (param-&gt;value &gt; 0)</div><div class='del'>-			return -EOPNOTSUPP;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	}</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_auth(struct net_device *dev,</div><div class='del'>-			       struct iw_request_info *info,</div><div class='del'>-			       union iwreq_data *wrqu, char *extra)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct iw_param *param = &amp;wrqu-&gt;param;</div><div class='del'>-</div><div class='del'>-	switch (param-&gt;flags &amp; IW_AUTH_INDEX) {</div><div class='del'>-	case IW_AUTH_DROP_UNENCRYPTED:</div><div class='del'>-		param-&gt;value = priv-&gt;exclude_unencrypted;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IW_AUTH_80211_AUTH_ALG:</div><div class='del'>-		if (priv-&gt;exclude_unencrypted == 1)</div><div class='del'>-			param-&gt;value = IW_AUTH_ALG_SHARED_KEY;</div><div class='del'>-		else</div><div class='del'>-			param-&gt;value = IW_AUTH_ALG_OPEN_SYSTEM;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IW_AUTH_WPA_ENABLED:</div><div class='del'>-		param-&gt;value = 0;</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		return -EOPNOTSUPP;</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static int atmel_get_name(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	strcpy(wrqu-&gt;name, "IEEE 802.11-DS");</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_rate(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;bitrate;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	if (vwrq-&gt;fixed == 0) {</div><div class='del'>-		priv-&gt;tx_rate = 3;</div><div class='del'>-		priv-&gt;auto_tx_rate = 1;</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;auto_tx_rate = 0;</div><div class='del'>-</div><div class='del'>-		/* Which type of value ? */</div><div class='del'>-		if ((vwrq-&gt;value &lt; 4) &amp;&amp; (vwrq-&gt;value &gt;= 0)) {</div><div class='del'>-			/* Setting by rate index */</div><div class='del'>-			priv-&gt;tx_rate = vwrq-&gt;value;</div><div class='del'>-		} else {</div><div class='del'>-		/* Setting by frequency value */</div><div class='del'>-			switch (vwrq-&gt;value) {</div><div class='del'>-			case  1000000:</div><div class='del'>-				priv-&gt;tx_rate = 0;</div><div class='del'>-				break;</div><div class='del'>-			case  2000000:</div><div class='del'>-				priv-&gt;tx_rate = 1;</div><div class='del'>-				break;</div><div class='del'>-			case  5500000:</div><div class='del'>-				priv-&gt;tx_rate = 2;</div><div class='del'>-				break;</div><div class='del'>-			case 11000000:</div><div class='del'>-				priv-&gt;tx_rate = 3;</div><div class='del'>-				break;</div><div class='del'>-			default:</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_mode(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	__u32 *uwrq = &amp;wrqu-&gt;mode;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	if (*uwrq != IW_MODE_ADHOC &amp;&amp; *uwrq != IW_MODE_INFRA)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	priv-&gt;operating_mode = *uwrq;</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_mode(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	__u32 *uwrq = &amp;wrqu-&gt;mode;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	*uwrq = priv-&gt;operating_mode;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_rate(struct net_device *dev,</div><div class='del'>-			 struct iw_request_info *info,</div><div class='del'>-			 union iwreq_data *wrqu,</div><div class='del'>-			 char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;bitrate;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;auto_tx_rate) {</div><div class='del'>-		vwrq-&gt;fixed = 0;</div><div class='del'>-		vwrq-&gt;value = 11000000;</div><div class='del'>-	} else {</div><div class='del'>-		vwrq-&gt;fixed = 1;</div><div class='del'>-		switch (priv-&gt;tx_rate) {</div><div class='del'>-		case 0:</div><div class='del'>-			vwrq-&gt;value =  1000000;</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-			vwrq-&gt;value =  2000000;</div><div class='del'>-			break;</div><div class='del'>-		case 2:</div><div class='del'>-			vwrq-&gt;value =  5500000;</div><div class='del'>-			break;</div><div class='del'>-		case 3:</div><div class='del'>-			vwrq-&gt;value = 11000000;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_power(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;power;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	priv-&gt;power_mode = vwrq-&gt;disabled ? 0 : 1;</div><div class='del'>-	return -EINPROGRESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_power(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;power;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	vwrq-&gt;disabled = priv-&gt;power_mode ? 0 : 1;</div><div class='del'>-	vwrq-&gt;flags = IW_POWER_ON;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_retry(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;retry;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	if (!vwrq-&gt;disabled &amp;&amp; (vwrq-&gt;flags &amp; IW_RETRY_LIMIT)) {</div><div class='del'>-		if (vwrq-&gt;flags &amp; IW_RETRY_LONG)</div><div class='del'>-			priv-&gt;long_retry = vwrq-&gt;value;</div><div class='del'>-		else if (vwrq-&gt;flags &amp; IW_RETRY_SHORT)</div><div class='del'>-			priv-&gt;short_retry = vwrq-&gt;value;</div><div class='del'>-		else {</div><div class='del'>-			/* No modifier : set both */</div><div class='del'>-			priv-&gt;long_retry = vwrq-&gt;value;</div><div class='del'>-			priv-&gt;short_retry = vwrq-&gt;value;</div><div class='del'>-		}</div><div class='del'>-		return -EINPROGRESS;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -EINVAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_retry(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;retry;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	vwrq-&gt;disabled = 0;      /* Can't be disabled */</div><div class='del'>-</div><div class='del'>-	/* Note : by default, display the short retry number */</div><div class='del'>-	if (vwrq-&gt;flags &amp; IW_RETRY_LONG) {</div><div class='del'>-		vwrq-&gt;flags = IW_RETRY_LIMIT | IW_RETRY_LONG;</div><div class='del'>-		vwrq-&gt;value = priv-&gt;long_retry;</div><div class='del'>-	} else {</div><div class='del'>-		vwrq-&gt;flags = IW_RETRY_LIMIT;</div><div class='del'>-		vwrq-&gt;value = priv-&gt;short_retry;</div><div class='del'>-		if (priv-&gt;long_retry != priv-&gt;short_retry)</div><div class='del'>-			vwrq-&gt;flags |= IW_RETRY_SHORT;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_rts(struct net_device *dev,</div><div class='del'>-			 struct iw_request_info *info,</div><div class='del'>-			 union iwreq_data *wrqu,</div><div class='del'>-			 char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;rts;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int rthr = vwrq-&gt;value;</div><div class='del'>-</div><div class='del'>-	if (vwrq-&gt;disabled)</div><div class='del'>-		rthr = 2347;</div><div class='del'>-	if ((rthr &lt; 0) || (rthr &gt; 2347)) {</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-	priv-&gt;rts_threshold = rthr;</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;		/* Call commit handler */</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_rts(struct net_device *dev,</div><div class='del'>-			 struct iw_request_info *info,</div><div class='del'>-			 union iwreq_data *wrqu,</div><div class='del'>-			 char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;rts;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	vwrq-&gt;value = priv-&gt;rts_threshold;</div><div class='del'>-	vwrq-&gt;disabled = (vwrq-&gt;value &gt;= 2347);</div><div class='del'>-	vwrq-&gt;fixed = 1;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_frag(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;frag;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int fthr = vwrq-&gt;value;</div><div class='del'>-</div><div class='del'>-	if (vwrq-&gt;disabled)</div><div class='del'>-		fthr = 2346;</div><div class='del'>-	if ((fthr &lt; 256) || (fthr &gt; 2346)) {</div><div class='del'>-		return -EINVAL;</div><div class='del'>-	}</div><div class='del'>-	fthr &amp;= ~0x1;	/* Get an even value - is it really needed ??? */</div><div class='del'>-	priv-&gt;frag_threshold = fthr;</div><div class='del'>-</div><div class='del'>-	return -EINPROGRESS;		/* Call commit handler */</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_frag(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_param *vwrq = &amp;wrqu-&gt;frag;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	vwrq-&gt;value = priv-&gt;frag_threshold;</div><div class='del'>-	vwrq-&gt;disabled = (vwrq-&gt;value &gt;= 2346);</div><div class='del'>-	vwrq-&gt;fixed = 1;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_freq(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_freq *fwrq = &amp;wrqu-&gt;freq;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int rc = -EINPROGRESS;		/* Call commit handler */</div><div class='del'>-</div><div class='del'>-	/* If setting by frequency, convert to a channel */</div><div class='del'>-	if (fwrq-&gt;e == 1) {</div><div class='del'>-		int f = fwrq-&gt;m / 100000;</div><div class='del'>-</div><div class='del'>-		/* Hack to fall through... */</div><div class='del'>-		fwrq-&gt;e = 0;</div><div class='del'>-		fwrq-&gt;m = ieee80211_frequency_to_channel(f);</div><div class='del'>-	}</div><div class='del'>-	/* Setting by channel number */</div><div class='del'>-	if (fwrq-&gt;m &lt; 0 || fwrq-&gt;m &gt; 1000 || fwrq-&gt;e &gt; 0)</div><div class='del'>-		rc = -EOPNOTSUPP;</div><div class='del'>-	else {</div><div class='del'>-		int channel = fwrq-&gt;m;</div><div class='del'>-		if (atmel_validate_channel(priv, channel) == 0) {</div><div class='del'>-			priv-&gt;channel = channel;</div><div class='del'>-		} else {</div><div class='del'>-			rc = -EINVAL;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_freq(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_freq *fwrq = &amp;wrqu-&gt;freq;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-</div><div class='del'>-	fwrq-&gt;m = priv-&gt;channel;</div><div class='del'>-	fwrq-&gt;e = 0;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_scan(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *dwrq,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	/* Note : you may have realised that, as this is a SET operation,</div><div class='del'>-	 * this is privileged and therefore a normal user can't</div><div class='del'>-	 * perform scanning.</div><div class='del'>-	 * This is not an error, while the device perform scanning,</div><div class='del'>-	 * traffic doesn't flow, so it's a perfect DoS...</div><div class='del'>-	 * Jean II */</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;station_state == STATION_STATE_DOWN)</div><div class='del'>-		return -EAGAIN;</div><div class='del'>-</div><div class='del'>-	/* Timeout old surveys. */</div><div class='del'>-	if (time_after(jiffies, priv-&gt;last_survey + 20 * HZ))</div><div class='del'>-		priv-&gt;site_survey_state = SITE_SURVEY_IDLE;</div><div class='del'>-	priv-&gt;last_survey = jiffies;</div><div class='del'>-</div><div class='del'>-	/* Initiate a scan command */</div><div class='del'>-	if (priv-&gt;site_survey_state == SITE_SURVEY_IN_PROGRESS)</div><div class='del'>-		return -EBUSY;</div><div class='del'>-</div><div class='del'>-	del_timer_sync(&amp;priv-&gt;management_timer);</div><div class='del'>-	spin_lock_irqsave(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-</div><div class='del'>-	priv-&gt;site_survey_state = SITE_SURVEY_IN_PROGRESS;</div><div class='del'>-	priv-&gt;fast_scan = 0;</div><div class='del'>-	atmel_scan(priv, 0);</div><div class='del'>-	spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_scan(struct net_device *dev,</div><div class='del'>-			  struct iw_request_info *info,</div><div class='del'>-			  union iwreq_data *wrqu,</div><div class='del'>-			  char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;data;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int i;</div><div class='del'>-	char *current_ev = extra;</div><div class='del'>-	struct iw_event	iwe;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;site_survey_state != SITE_SURVEY_COMPLETED)</div><div class='del'>-		return -EAGAIN;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; priv-&gt;BSS_list_entries; i++) {</div><div class='del'>-		iwe.cmd = SIOCGIWAP;</div><div class='del'>-		iwe.u.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-		memcpy(iwe.u.ap_addr.sa_data, priv-&gt;BSSinfo[i].BSSID, ETH_ALEN);</div><div class='del'>-		current_ev = iwe_stream_add_event(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, IW_EV_ADDR_LEN);</div><div class='del'>-</div><div class='del'>-		iwe.u.data.length =  priv-&gt;BSSinfo[i].SSIDsize;</div><div class='del'>-		if (iwe.u.data.length &gt; 32)</div><div class='del'>-			iwe.u.data.length = 32;</div><div class='del'>-		iwe.cmd = SIOCGIWESSID;</div><div class='del'>-		iwe.u.data.flags = 1;</div><div class='del'>-		current_ev = iwe_stream_add_point(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, priv-&gt;BSSinfo[i].SSID);</div><div class='del'>-</div><div class='del'>-		iwe.cmd = SIOCGIWMODE;</div><div class='del'>-		iwe.u.mode = priv-&gt;BSSinfo[i].BSStype;</div><div class='del'>-		current_ev = iwe_stream_add_event(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, IW_EV_UINT_LEN);</div><div class='del'>-</div><div class='del'>-		iwe.cmd = SIOCGIWFREQ;</div><div class='del'>-		iwe.u.freq.m = priv-&gt;BSSinfo[i].channel;</div><div class='del'>-		iwe.u.freq.e = 0;</div><div class='del'>-		current_ev = iwe_stream_add_event(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, IW_EV_FREQ_LEN);</div><div class='del'>-</div><div class='del'>-		/* Add quality statistics */</div><div class='del'>-		iwe.cmd = IWEVQUAL;</div><div class='del'>-		iwe.u.qual.level = priv-&gt;BSSinfo[i].RSSI;</div><div class='del'>-		iwe.u.qual.qual  = iwe.u.qual.level;</div><div class='del'>-		/* iwe.u.qual.noise  = SOMETHING */</div><div class='del'>-		current_ev = iwe_stream_add_event(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, IW_EV_QUAL_LEN);</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-		iwe.cmd = SIOCGIWENCODE;</div><div class='del'>-		if (priv-&gt;BSSinfo[i].UsingWEP)</div><div class='del'>-			iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;</div><div class='del'>-		else</div><div class='del'>-			iwe.u.data.flags = IW_ENCODE_DISABLED;</div><div class='del'>-		iwe.u.data.length = 0;</div><div class='del'>-		current_ev = iwe_stream_add_point(info, current_ev,</div><div class='del'>-						  extra + IW_SCAN_MAX_DATA,</div><div class='del'>-						  &amp;iwe, NULL);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Length of data */</div><div class='del'>-	dwrq-&gt;length = (current_ev - extra);</div><div class='del'>-	dwrq-&gt;flags = 0;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_get_range(struct net_device *dev,</div><div class='del'>-			   struct iw_request_info *info,</div><div class='del'>-			   union iwreq_data *wrqu,</div><div class='del'>-			   char *extra)</div><div class='del'>-{</div><div class='del'>-	struct iw_point *dwrq = &amp;wrqu-&gt;data;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	struct iw_range *range = (struct iw_range *) extra;</div><div class='del'>-	int k, i, j;</div><div class='del'>-</div><div class='del'>-	dwrq-&gt;length = sizeof(struct iw_range);</div><div class='del'>-	memset(range, 0, sizeof(struct iw_range));</div><div class='del'>-	range-&gt;min_nwid = 0x0000;</div><div class='del'>-	range-&gt;max_nwid = 0x0000;</div><div class='del'>-	range-&gt;num_channels = 0;</div><div class='del'>-	for (j = 0; j &lt; ARRAY_SIZE(channel_table); j++)</div><div class='del'>-		if (priv-&gt;reg_domain == channel_table[j].reg_domain) {</div><div class='del'>-			range-&gt;num_channels = channel_table[j].max - channel_table[j].min + 1;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	if (range-&gt;num_channels != 0) {</div><div class='del'>-		for (k = 0, i = channel_table[j].min; i &lt;= channel_table[j].max; i++) {</div><div class='del'>-			range-&gt;freq[k].i = i; /* List index */</div><div class='del'>-</div><div class='del'>-			/* Values in MHz -&gt; * 10^5 * 10 */</div><div class='del'>-			range-&gt;freq[k].m = 100000 *</div><div class='del'>-			 ieee80211_channel_to_frequency(i, NL80211_BAND_2GHZ);</div><div class='del'>-			range-&gt;freq[k++].e = 1;</div><div class='del'>-		}</div><div class='del'>-		range-&gt;num_frequency = k;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	range-&gt;max_qual.qual = 100;</div><div class='del'>-	range-&gt;max_qual.level = 100;</div><div class='del'>-	range-&gt;max_qual.noise = 0;</div><div class='del'>-	range-&gt;max_qual.updated = IW_QUAL_NOISE_INVALID;</div><div class='del'>-</div><div class='del'>-	range-&gt;avg_qual.qual = 50;</div><div class='del'>-	range-&gt;avg_qual.level = 50;</div><div class='del'>-	range-&gt;avg_qual.noise = 0;</div><div class='del'>-	range-&gt;avg_qual.updated = IW_QUAL_NOISE_INVALID;</div><div class='del'>-</div><div class='del'>-	range-&gt;sensitivity = 0;</div><div class='del'>-</div><div class='del'>-	range-&gt;bitrate[0] =  1000000;</div><div class='del'>-	range-&gt;bitrate[1] =  2000000;</div><div class='del'>-	range-&gt;bitrate[2] =  5500000;</div><div class='del'>-	range-&gt;bitrate[3] = 11000000;</div><div class='del'>-	range-&gt;num_bitrates = 4;</div><div class='del'>-</div><div class='del'>-	range-&gt;min_rts = 0;</div><div class='del'>-	range-&gt;max_rts = 2347;</div><div class='del'>-	range-&gt;min_frag = 256;</div><div class='del'>-	range-&gt;max_frag = 2346;</div><div class='del'>-</div><div class='del'>-	range-&gt;encoding_size[0] = 5;</div><div class='del'>-	range-&gt;encoding_size[1] = 13;</div><div class='del'>-	range-&gt;num_encoding_sizes = 2;</div><div class='del'>-	range-&gt;max_encoding_tokens = 4;</div><div class='del'>-</div><div class='del'>-	range-&gt;pmp_flags = IW_POWER_ON;</div><div class='del'>-	range-&gt;pmt_flags = IW_POWER_ON;</div><div class='del'>-	range-&gt;pm_capa = 0;</div><div class='del'>-</div><div class='del'>-	range-&gt;we_version_source = WIRELESS_EXT;</div><div class='del'>-	range-&gt;we_version_compiled = WIRELESS_EXT;</div><div class='del'>-	range-&gt;retry_capa = IW_RETRY_LIMIT ;</div><div class='del'>-	range-&gt;retry_flags = IW_RETRY_LIMIT;</div><div class='del'>-	range-&gt;r_time_flags = 0;</div><div class='del'>-	range-&gt;min_retry = 1;</div><div class='del'>-	range-&gt;max_retry = 65535;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_set_wap(struct net_device *dev,</div><div class='del'>-			 struct iw_request_info *info,</div><div class='del'>-			 union iwreq_data *wrqu,</div><div class='del'>-			 char *extra)</div><div class='del'>-{</div><div class='del'>-	struct sockaddr *awrq = &amp;wrqu-&gt;ap_addr;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	int i;</div><div class='del'>-	static const u8 any[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };</div><div class='del'>-	static const u8 off[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	if (awrq-&gt;sa_family != ARPHRD_ETHER)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	if (!memcmp(any, awrq-&gt;sa_data, 6) ||</div><div class='del'>-	    !memcmp(off, awrq-&gt;sa_data, 6)) {</div><div class='del'>-		del_timer_sync(&amp;priv-&gt;management_timer);</div><div class='del'>-		spin_lock_irqsave(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-		atmel_scan(priv, 1);</div><div class='del'>-		spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; priv-&gt;BSS_list_entries; i++) {</div><div class='del'>-		if (memcmp(priv-&gt;BSSinfo[i].BSSID, awrq-&gt;sa_data, 6) == 0) {</div><div class='del'>-			if (!priv-&gt;wep_is_on &amp;&amp; priv-&gt;BSSinfo[i].UsingWEP) {</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			} else if  (priv-&gt;wep_is_on &amp;&amp; !priv-&gt;BSSinfo[i].UsingWEP) {</div><div class='del'>-				return -EINVAL;</div><div class='del'>-			} else {</div><div class='del'>-				del_timer_sync(&amp;priv-&gt;management_timer);</div><div class='del'>-				spin_lock_irqsave(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-				atmel_join_bss(priv, i);</div><div class='del'>-				spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-				return 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return -EINVAL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_config_commit(struct net_device *dev,</div><div class='del'>-			       struct iw_request_info *info,	/* NULL */</div><div class='del'>-			       union iwreq_data *zwrq,		/* NULL */</div><div class='del'>-			       char *extra)			/* NULL */</div><div class='del'>-{</div><div class='del'>-	return atmel_open(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const iw_handler atmel_handler[] =</div><div class='del'>-{</div><div class='del'>-	IW_HANDLER(SIOCSIWCOMMIT,	atmel_config_commit),</div><div class='del'>-	IW_HANDLER(SIOCGIWNAME,		atmel_get_name),</div><div class='del'>-	IW_HANDLER(SIOCSIWFREQ,		atmel_set_freq),</div><div class='del'>-	IW_HANDLER(SIOCGIWFREQ,		atmel_get_freq),</div><div class='del'>-	IW_HANDLER(SIOCSIWMODE,		atmel_set_mode),</div><div class='del'>-	IW_HANDLER(SIOCGIWMODE,		atmel_get_mode),</div><div class='del'>-	IW_HANDLER(SIOCGIWRANGE,	atmel_get_range),</div><div class='del'>-	IW_HANDLER(SIOCSIWAP,		atmel_set_wap),</div><div class='del'>-	IW_HANDLER(SIOCGIWAP,		atmel_get_wap),</div><div class='del'>-	IW_HANDLER(SIOCSIWSCAN,		atmel_set_scan),</div><div class='del'>-	IW_HANDLER(SIOCGIWSCAN,		atmel_get_scan),</div><div class='del'>-	IW_HANDLER(SIOCSIWESSID,	atmel_set_essid),</div><div class='del'>-	IW_HANDLER(SIOCGIWESSID,	atmel_get_essid),</div><div class='del'>-	IW_HANDLER(SIOCSIWRATE,		atmel_set_rate),</div><div class='del'>-	IW_HANDLER(SIOCGIWRATE,		atmel_get_rate),</div><div class='del'>-	IW_HANDLER(SIOCSIWRTS,		atmel_set_rts),</div><div class='del'>-	IW_HANDLER(SIOCGIWRTS,		atmel_get_rts),</div><div class='del'>-	IW_HANDLER(SIOCSIWFRAG,		atmel_set_frag),</div><div class='del'>-	IW_HANDLER(SIOCGIWFRAG,		atmel_get_frag),</div><div class='del'>-	IW_HANDLER(SIOCSIWRETRY,	atmel_set_retry),</div><div class='del'>-	IW_HANDLER(SIOCGIWRETRY,	atmel_get_retry),</div><div class='del'>-	IW_HANDLER(SIOCSIWENCODE,	atmel_set_encode),</div><div class='del'>-	IW_HANDLER(SIOCGIWENCODE,	atmel_get_encode),</div><div class='del'>-	IW_HANDLER(SIOCSIWPOWER,	atmel_set_power),</div><div class='del'>-	IW_HANDLER(SIOCGIWPOWER,	atmel_get_power),</div><div class='del'>-	IW_HANDLER(SIOCSIWAUTH,		atmel_set_auth),</div><div class='del'>-	IW_HANDLER(SIOCGIWAUTH,		atmel_get_auth),</div><div class='del'>-	IW_HANDLER(SIOCSIWENCODEEXT,	atmel_set_encodeext),</div><div class='del'>-	IW_HANDLER(SIOCGIWENCODEEXT,	atmel_get_encodeext),</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const iw_handler atmel_private_handler[] =</div><div class='del'>-{</div><div class='del'>-	NULL,				/* SIOCIWFIRSTPRIV */</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct atmel_priv_ioctl {</div><div class='del'>-	char id[32];</div><div class='del'>-	unsigned char __user *data;</div><div class='del'>-	unsigned short len;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-#define ATMELFWL	SIOCIWFIRSTPRIV</div><div class='del'>-#define ATMELIDIFC	ATMELFWL + 1</div><div class='del'>-#define ATMELRD		ATMELFWL + 2</div><div class='del'>-#define ATMELMAGIC 0x51807</div><div class='del'>-#define REGDOMAINSZ 20</div><div class='del'>-</div><div class='del'>-static const struct iw_priv_args atmel_private_args[] = {</div><div class='del'>-	{</div><div class='del'>-		.cmd = ATMELFWL,</div><div class='del'>-		.set_args = IW_PRIV_TYPE_BYTE</div><div class='del'>-				| IW_PRIV_SIZE_FIXED</div><div class='del'>-				| sizeof(struct atmel_priv_ioctl),</div><div class='del'>-		.get_args = IW_PRIV_TYPE_NONE,</div><div class='del'>-		.name = "atmelfwl"</div><div class='del'>-	}, {</div><div class='del'>-		.cmd = ATMELIDIFC,</div><div class='del'>-		.set_args = IW_PRIV_TYPE_NONE,</div><div class='del'>-		.get_args = IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,</div><div class='del'>-		.name = "atmelidifc"</div><div class='del'>-	}, {</div><div class='del'>-		.cmd = ATMELRD,</div><div class='del'>-		.set_args = IW_PRIV_TYPE_CHAR | REGDOMAINSZ,</div><div class='del'>-		.get_args = IW_PRIV_TYPE_NONE,</div><div class='del'>-		.name = "regdomain"</div><div class='del'>-	},</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct iw_handler_def atmel_handler_def = {</div><div class='del'>-	.num_standard	= ARRAY_SIZE(atmel_handler),</div><div class='del'>-	.num_private	= ARRAY_SIZE(atmel_private_handler),</div><div class='del'>-	.num_private_args = ARRAY_SIZE(atmel_private_args),</div><div class='del'>-	.standard	= atmel_handler,</div><div class='del'>-	.private	= atmel_private_handler,</div><div class='del'>-	.private_args	= (struct iw_priv_args *) atmel_private_args,</div><div class='del'>-	.get_wireless_stats = atmel_get_wireless_stats</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-struct auth_body {</div><div class='del'>-	__le16 alg;</div><div class='del'>-	__le16 trans_seq;</div><div class='del'>-	__le16 status;</div><div class='del'>-	u8 el_id;</div><div class='del'>-	u8 chall_text_len;</div><div class='del'>-	u8 chall_text[253];</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void atmel_enter_state(struct atmel_private *priv, int new_state)</div><div class='del'>-{</div><div class='del'>-	int old_state = priv-&gt;station_state;</div><div class='del'>-</div><div class='del'>-	if (new_state == old_state)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	priv-&gt;station_state = new_state;</div><div class='del'>-</div><div class='del'>-	if (new_state == STATION_STATE_READY) {</div><div class='del'>-		netif_start_queue(priv-&gt;dev);</div><div class='del'>-		netif_carrier_on(priv-&gt;dev);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (old_state == STATION_STATE_READY) {</div><div class='del'>-		netif_carrier_off(priv-&gt;dev);</div><div class='del'>-		if (netif_running(priv-&gt;dev))</div><div class='del'>-			netif_stop_queue(priv-&gt;dev);</div><div class='del'>-		priv-&gt;last_beacon_timestamp = 0;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_scan(struct atmel_private *priv, int specific_ssid)</div><div class='del'>-{</div><div class='del'>-	struct {</div><div class='del'>-		u8 BSSID[ETH_ALEN];</div><div class='del'>-		u8 SSID[MAX_SSID_LENGTH];</div><div class='del'>-		u8 scan_type;</div><div class='del'>-		u8 channel;</div><div class='del'>-		__le16 BSS_type;</div><div class='del'>-		__le16 min_channel_time;</div><div class='del'>-		__le16 max_channel_time;</div><div class='del'>-		u8 options;</div><div class='del'>-		u8 SSID_size;</div><div class='del'>-	} cmd;</div><div class='del'>-</div><div class='del'>-	eth_broadcast_addr(cmd.BSSID);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;fast_scan) {</div><div class='del'>-		cmd.SSID_size = priv-&gt;SSID_size;</div><div class='del'>-		memcpy(cmd.SSID, priv-&gt;SSID, priv-&gt;SSID_size);</div><div class='del'>-		cmd.min_channel_time = cpu_to_le16(10);</div><div class='del'>-		cmd.max_channel_time = cpu_to_le16(50);</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;BSS_list_entries = 0;</div><div class='del'>-		cmd.SSID_size = 0;</div><div class='del'>-		cmd.min_channel_time = cpu_to_le16(10);</div><div class='del'>-		cmd.max_channel_time = cpu_to_le16(120);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	cmd.options = 0;</div><div class='del'>-</div><div class='del'>-	if (!specific_ssid)</div><div class='del'>-		cmd.options |= SCAN_OPTIONS_SITE_SURVEY;</div><div class='del'>-</div><div class='del'>-	cmd.channel = (priv-&gt;channel &amp; 0x7f);</div><div class='del'>-	cmd.scan_type = SCAN_TYPE_ACTIVE;</div><div class='del'>-	cmd.BSS_type = cpu_to_le16(priv-&gt;operating_mode == IW_MODE_ADHOC ?</div><div class='del'>-		BSS_TYPE_AD_HOC : BSS_TYPE_INFRASTRUCTURE);</div><div class='del'>-</div><div class='del'>-	atmel_send_command(priv, CMD_Scan, &amp;cmd, sizeof(cmd));</div><div class='del'>-</div><div class='del'>-	/* This must come after all hardware access to avoid being messed up</div><div class='del'>-	   by stuff happening in interrupt context after we leave STATE_DOWN */</div><div class='del'>-	atmel_enter_state(priv, STATION_STATE_SCANNING);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void join(struct atmel_private *priv, int type)</div><div class='del'>-{</div><div class='del'>-	struct {</div><div class='del'>-		u8 BSSID[6];</div><div class='del'>-		u8 SSID[MAX_SSID_LENGTH];</div><div class='del'>-		u8 BSS_type; /* this is a short in a scan command - weird */</div><div class='del'>-		u8 channel;</div><div class='del'>-		__le16 timeout;</div><div class='del'>-		u8 SSID_size;</div><div class='del'>-		u8 reserved;</div><div class='del'>-	} cmd;</div><div class='del'>-</div><div class='del'>-	cmd.SSID_size = priv-&gt;SSID_size;</div><div class='del'>-	memcpy(cmd.SSID, priv-&gt;SSID, priv-&gt;SSID_size);</div><div class='del'>-	memcpy(cmd.BSSID, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-	cmd.channel = (priv-&gt;channel &amp; 0x7f);</div><div class='del'>-	cmd.BSS_type = type;</div><div class='del'>-	cmd.timeout = cpu_to_le16(2000);</div><div class='del'>-</div><div class='del'>-	atmel_send_command(priv, CMD_Join, &amp;cmd, sizeof(cmd));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void start(struct atmel_private *priv, int type)</div><div class='del'>-{</div><div class='del'>-	struct {</div><div class='del'>-		u8 BSSID[6];</div><div class='del'>-		u8 SSID[MAX_SSID_LENGTH];</div><div class='del'>-		u8 BSS_type;</div><div class='del'>-		u8 channel;</div><div class='del'>-		u8 SSID_size;</div><div class='del'>-		u8 reserved[3];</div><div class='del'>-	} cmd;</div><div class='del'>-</div><div class='del'>-	cmd.SSID_size = priv-&gt;SSID_size;</div><div class='del'>-	memcpy(cmd.SSID, priv-&gt;SSID, priv-&gt;SSID_size);</div><div class='del'>-	memcpy(cmd.BSSID, priv-&gt;BSSID, ETH_ALEN);</div><div class='del'>-	cmd.BSS_type = type;</div><div class='del'>-	cmd.channel = (priv-&gt;channel &amp; 0x7f);</div><div class='del'>-</div><div class='del'>-	atmel_send_command(priv, CMD_Start, &amp;cmd, sizeof(cmd));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void handle_beacon_probe(struct atmel_private *priv, u16 capability,</div><div class='del'>-				u8 channel)</div><div class='del'>-{</div><div class='del'>-	int rejoin = 0;</div><div class='del'>-	int new = capability &amp; WLAN_CAPABILITY_SHORT_PREAMBLE ?</div><div class='del'>-		SHORT_PREAMBLE : LONG_PREAMBLE;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;preamble != new) {</div><div class='del'>-		priv-&gt;preamble = new;</div><div class='del'>-		rejoin = 1;</div><div class='del'>-		atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_PREAMBLE_TYPE, new);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;channel != channel) {</div><div class='del'>-		priv-&gt;channel = channel;</div><div class='del'>-		rejoin = 1;</div><div class='del'>-		atmel_set_mib8(priv, Phy_Mib_Type, PHY_MIB_CHANNEL_POS, channel);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (rejoin) {</div><div class='del'>-		priv-&gt;station_is_associated = 0;</div><div class='del'>-		atmel_enter_state(priv, STATION_STATE_JOINNING);</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;operating_mode == IW_MODE_INFRA)</div><div class='del'>-			join(priv, BSS_TYPE_INFRASTRUCTURE);</div><div class='del'>-		else</div><div class='del'>-			join(priv, BSS_TYPE_AD_HOC);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void send_authentication_request(struct atmel_private *priv, u16 system,</div><div class='del'>-					u8 *challenge, int challenge_len)</div><div class='del'>-{</div><div class='del'>-	struct ieee80211_hdr header;</div><div class='del'>-	struct auth_body auth;</div><div class='del'>-</div><div class='del'>-	header.frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_AUTH);</div><div class='del'>-	header.duration_id = cpu_to_le16(0x8000);</div><div class='del'>-	header.seq_ctrl = 0;</div><div class='del'>-	memcpy(header.addr1, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-	memcpy(header.addr2, priv-&gt;dev-&gt;dev_addr, ETH_ALEN);</div><div class='del'>-	memcpy(header.addr3, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;wep_is_on &amp;&amp; priv-&gt;CurrentAuthentTransactionSeqNum != 1)</div><div class='del'>-		/* no WEP for authentication frames with TrSeqNo 1 */</div><div class='del'>-		header.frame_control |=  cpu_to_le16(IEEE80211_FCTL_PROTECTED);</div><div class='del'>-</div><div class='del'>-	auth.alg = cpu_to_le16(system);</div><div class='del'>-</div><div class='del'>-	auth.status = 0;</div><div class='del'>-	auth.trans_seq = cpu_to_le16(priv-&gt;CurrentAuthentTransactionSeqNum);</div><div class='del'>-	priv-&gt;ExpectedAuthentTransactionSeqNum = priv-&gt;CurrentAuthentTransactionSeqNum+1;</div><div class='del'>-	priv-&gt;CurrentAuthentTransactionSeqNum += 2;</div><div class='del'>-</div><div class='del'>-	if (challenge_len != 0)	{</div><div class='del'>-		auth.el_id = 16; /* challenge_text */</div><div class='del'>-		auth.chall_text_len = challenge_len;</div><div class='del'>-		memcpy(auth.chall_text, challenge, challenge_len);</div><div class='del'>-		atmel_transmit_management_frame(priv, &amp;header, (u8 *)&amp;auth, 8 + challenge_len);</div><div class='del'>-	} else {</div><div class='del'>-		atmel_transmit_management_frame(priv, &amp;header, (u8 *)&amp;auth, 6);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void send_association_request(struct atmel_private *priv, int is_reassoc)</div><div class='del'>-{</div><div class='del'>-	u8 *ssid_el_p;</div><div class='del'>-	int bodysize;</div><div class='del'>-	struct ieee80211_hdr header;</div><div class='del'>-	struct ass_req_format {</div><div class='del'>-		__le16 capability;</div><div class='del'>-		__le16 listen_interval;</div><div class='del'>-		u8 ap[ETH_ALEN]; /* nothing after here directly accessible */</div><div class='del'>-		u8 ssid_el_id;</div><div class='del'>-		u8 ssid_len;</div><div class='del'>-		u8 ssid[MAX_SSID_LENGTH];</div><div class='del'>-		u8 sup_rates_el_id;</div><div class='del'>-		u8 sup_rates_len;</div><div class='del'>-		u8 rates[4];</div><div class='del'>-	} body;</div><div class='del'>-</div><div class='del'>-	header.frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |</div><div class='del'>-		(is_reassoc ? IEEE80211_STYPE_REASSOC_REQ : IEEE80211_STYPE_ASSOC_REQ));</div><div class='del'>-	header.duration_id = cpu_to_le16(0x8000);</div><div class='del'>-	header.seq_ctrl = 0;</div><div class='del'>-</div><div class='del'>-	memcpy(header.addr1, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-	memcpy(header.addr2, priv-&gt;dev-&gt;dev_addr, ETH_ALEN);</div><div class='del'>-	memcpy(header.addr3, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	body.capability = cpu_to_le16(WLAN_CAPABILITY_ESS);</div><div class='del'>-	if (priv-&gt;wep_is_on)</div><div class='del'>-		body.capability |= cpu_to_le16(WLAN_CAPABILITY_PRIVACY);</div><div class='del'>-	if (priv-&gt;preamble == SHORT_PREAMBLE)</div><div class='del'>-		body.capability |= cpu_to_le16(WLAN_CAPABILITY_SHORT_PREAMBLE);</div><div class='del'>-</div><div class='del'>-	body.listen_interval = cpu_to_le16(priv-&gt;listen_interval * priv-&gt;beacon_period);</div><div class='del'>-</div><div class='del'>-	/* current AP address - only in reassoc frame */</div><div class='del'>-	if (is_reassoc) {</div><div class='del'>-		memcpy(body.ap, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-		ssid_el_p = &amp;body.ssid_el_id;</div><div class='del'>-		bodysize = 18 + priv-&gt;SSID_size;</div><div class='del'>-	} else {</div><div class='del'>-		ssid_el_p = &amp;body.ap[0];</div><div class='del'>-		bodysize = 12 + priv-&gt;SSID_size;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ssid_el_p[0] = WLAN_EID_SSID;</div><div class='del'>-	ssid_el_p[1] = priv-&gt;SSID_size;</div><div class='del'>-	memcpy(ssid_el_p + 2, priv-&gt;SSID, priv-&gt;SSID_size);</div><div class='del'>-	ssid_el_p[2 + priv-&gt;SSID_size] = WLAN_EID_SUPP_RATES;</div><div class='del'>-	ssid_el_p[3 + priv-&gt;SSID_size] = 4; /* len of supported rates */</div><div class='del'>-	memcpy(ssid_el_p + 4 + priv-&gt;SSID_size, atmel_basic_rates, 4);</div><div class='del'>-</div><div class='del'>-	atmel_transmit_management_frame(priv, &amp;header, (void *)&amp;body, bodysize);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int is_frame_from_current_bss(struct atmel_private *priv,</div><div class='del'>-				     struct ieee80211_hdr *header)</div><div class='del'>-{</div><div class='del'>-	if (le16_to_cpu(header-&gt;frame_control) &amp; IEEE80211_FCTL_FROMDS)</div><div class='del'>-		return memcmp(header-&gt;addr3, priv-&gt;CurrentBSSID, 6) == 0;</div><div class='del'>-	else</div><div class='del'>-		return memcmp(header-&gt;addr2, priv-&gt;CurrentBSSID, 6) == 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int retrieve_bss(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	int max_rssi = -128;</div><div class='del'>-	int max_index = -1;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;BSS_list_entries == 0)</div><div class='del'>-		return -1;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;connect_to_any_BSS) {</div><div class='del'>-		/* Select a BSS with the max-RSSI but of the same type and of</div><div class='del'>-		   the same WEP mode and that it is not marked as 'bad' (i.e.</div><div class='del'>-		   we had previously failed to connect to this BSS with the</div><div class='del'>-		   settings that we currently use) */</div><div class='del'>-		priv-&gt;current_BSS = 0;</div><div class='del'>-		for (i = 0; i &lt; priv-&gt;BSS_list_entries; i++) {</div><div class='del'>-			if (priv-&gt;operating_mode == priv-&gt;BSSinfo[i].BSStype &amp;&amp;</div><div class='del'>-			    ((!priv-&gt;wep_is_on &amp;&amp; !priv-&gt;BSSinfo[i].UsingWEP) ||</div><div class='del'>-			     (priv-&gt;wep_is_on &amp;&amp; priv-&gt;BSSinfo[i].UsingWEP)) &amp;&amp;</div><div class='del'>-			    !(priv-&gt;BSSinfo[i].channel &amp; 0x80)) {</div><div class='del'>-				max_rssi = priv-&gt;BSSinfo[i].RSSI;</div><div class='del'>-				priv-&gt;current_BSS = max_index = i;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		return max_index;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; priv-&gt;BSS_list_entries; i++) {</div><div class='del'>-		if (priv-&gt;SSID_size == priv-&gt;BSSinfo[i].SSIDsize &amp;&amp;</div><div class='del'>-		    memcmp(priv-&gt;SSID, priv-&gt;BSSinfo[i].SSID, priv-&gt;SSID_size) == 0 &amp;&amp;</div><div class='del'>-		    priv-&gt;operating_mode == priv-&gt;BSSinfo[i].BSStype &amp;&amp;</div><div class='del'>-		    atmel_validate_channel(priv, priv-&gt;BSSinfo[i].channel) == 0) {</div><div class='del'>-			if (priv-&gt;BSSinfo[i].RSSI &gt;= max_rssi) {</div><div class='del'>-				max_rssi = priv-&gt;BSSinfo[i].RSSI;</div><div class='del'>-				max_index = i;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	return max_index;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void store_bss_info(struct atmel_private *priv,</div><div class='del'>-			   struct ieee80211_hdr *header, u16 capability,</div><div class='del'>-			   u16 beacon_period, u8 channel, u8 rssi, u8 ssid_len,</div><div class='del'>-			   u8 *ssid, int is_beacon)</div><div class='del'>-{</div><div class='del'>-	u8 *bss = capability &amp; WLAN_CAPABILITY_ESS ? header-&gt;addr2 : header-&gt;addr3;</div><div class='del'>-	int i, index;</div><div class='del'>-</div><div class='del'>-	for (index = -1, i = 0; i &lt; priv-&gt;BSS_list_entries; i++)</div><div class='del'>-		if (memcmp(bss, priv-&gt;BSSinfo[i].BSSID, ETH_ALEN) == 0)</div><div class='del'>-			index = i;</div><div class='del'>-</div><div class='del'>-	/* If we process a probe and an entry from this BSS exists</div><div class='del'>-	   we will update the BSS entry with the info from this BSS.</div><div class='del'>-	   If we process a beacon we will only update RSSI */</div><div class='del'>-</div><div class='del'>-	if (index == -1) {</div><div class='del'>-		if (priv-&gt;BSS_list_entries == MAX_BSS_ENTRIES)</div><div class='del'>-			return;</div><div class='del'>-		index = priv-&gt;BSS_list_entries++;</div><div class='del'>-		memcpy(priv-&gt;BSSinfo[index].BSSID, bss, ETH_ALEN);</div><div class='del'>-		priv-&gt;BSSinfo[index].RSSI = rssi;</div><div class='del'>-	} else {</div><div class='del'>-		if (rssi &gt; priv-&gt;BSSinfo[index].RSSI)</div><div class='del'>-			priv-&gt;BSSinfo[index].RSSI = rssi;</div><div class='del'>-		if (is_beacon)</div><div class='del'>-			return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	priv-&gt;BSSinfo[index].channel = channel;</div><div class='del'>-	priv-&gt;BSSinfo[index].beacon_period = beacon_period;</div><div class='del'>-	priv-&gt;BSSinfo[index].UsingWEP = capability &amp; WLAN_CAPABILITY_PRIVACY;</div><div class='del'>-	memcpy(priv-&gt;BSSinfo[index].SSID, ssid, ssid_len);</div><div class='del'>-	priv-&gt;BSSinfo[index].SSIDsize = ssid_len;</div><div class='del'>-</div><div class='del'>-	if (capability &amp; WLAN_CAPABILITY_IBSS)</div><div class='del'>-		priv-&gt;BSSinfo[index].BSStype = IW_MODE_ADHOC;</div><div class='del'>-	else if (capability &amp; WLAN_CAPABILITY_ESS)</div><div class='del'>-		priv-&gt;BSSinfo[index].BSStype = IW_MODE_INFRA;</div><div class='del'>-</div><div class='del'>-	priv-&gt;BSSinfo[index].preamble = capability &amp; WLAN_CAPABILITY_SHORT_PREAMBLE ?</div><div class='del'>-		SHORT_PREAMBLE : LONG_PREAMBLE;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void authenticate(struct atmel_private *priv, u16 frame_len)</div><div class='del'>-{</div><div class='del'>-	struct auth_body *auth = (struct auth_body *)priv-&gt;rx_buf;</div><div class='del'>-	u16 status = le16_to_cpu(auth-&gt;status);</div><div class='del'>-	u16 trans_seq_no = le16_to_cpu(auth-&gt;trans_seq);</div><div class='del'>-	u16 system = le16_to_cpu(auth-&gt;alg);</div><div class='del'>-</div><div class='del'>-	if (status == WLAN_STATUS_SUCCESS &amp;&amp; !priv-&gt;wep_is_on) {</div><div class='del'>-		/* no WEP */</div><div class='del'>-		if (priv-&gt;station_was_associated) {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_REASSOCIATING);</div><div class='del'>-			send_association_request(priv, 1);</div><div class='del'>-			return;</div><div class='del'>-		} else {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_ASSOCIATING);</div><div class='del'>-			send_association_request(priv, 0);</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status == WLAN_STATUS_SUCCESS &amp;&amp; priv-&gt;wep_is_on) {</div><div class='del'>-		int should_associate = 0;</div><div class='del'>-		/* WEP */</div><div class='del'>-		if (trans_seq_no != priv-&gt;ExpectedAuthentTransactionSeqNum)</div><div class='del'>-			return;</div><div class='del'>-</div><div class='del'>-		if (system == WLAN_AUTH_OPEN) {</div><div class='del'>-			if (trans_seq_no == 0x0002) {</div><div class='del'>-				should_associate = 1;</div><div class='del'>-			}</div><div class='del'>-		} else if (system == WLAN_AUTH_SHARED_KEY) {</div><div class='del'>-			if (trans_seq_no == 0x0002 &amp;&amp;</div><div class='del'>-			    auth-&gt;el_id == WLAN_EID_CHALLENGE) {</div><div class='del'>-				send_authentication_request(priv, system, auth-&gt;chall_text, auth-&gt;chall_text_len);</div><div class='del'>-				return;</div><div class='del'>-			} else if (trans_seq_no == 0x0004) {</div><div class='del'>-				should_associate = 1;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (should_associate) {</div><div class='del'>-			if (priv-&gt;station_was_associated) {</div><div class='del'>-				atmel_enter_state(priv, STATION_STATE_REASSOCIATING);</div><div class='del'>-				send_association_request(priv, 1);</div><div class='del'>-				return;</div><div class='del'>-			} else {</div><div class='del'>-				atmel_enter_state(priv, STATION_STATE_ASSOCIATING);</div><div class='del'>-				send_association_request(priv, 0);</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (status == WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG) {</div><div class='del'>-		/* Flip back and forth between WEP auth modes until the max</div><div class='del'>-		 * authentication tries has been exceeded.</div><div class='del'>-		 */</div><div class='del'>-		if (system == WLAN_AUTH_OPEN) {</div><div class='del'>-			priv-&gt;CurrentAuthentTransactionSeqNum = 0x001;</div><div class='del'>-			priv-&gt;exclude_unencrypted = 1;</div><div class='del'>-			send_authentication_request(priv, WLAN_AUTH_SHARED_KEY, NULL, 0);</div><div class='del'>-			return;</div><div class='del'>-		} else if (system == WLAN_AUTH_SHARED_KEY</div><div class='del'>-			   &amp;&amp; priv-&gt;wep_is_on) {</div><div class='del'>-			priv-&gt;CurrentAuthentTransactionSeqNum = 0x001;</div><div class='del'>-			priv-&gt;exclude_unencrypted = 0;</div><div class='del'>-			send_authentication_request(priv, WLAN_AUTH_OPEN, NULL, 0);</div><div class='del'>-			return;</div><div class='del'>-		} else if (priv-&gt;connect_to_any_BSS) {</div><div class='del'>-			int bss_index;</div><div class='del'>-</div><div class='del'>-			priv-&gt;BSSinfo[(int)(priv-&gt;current_BSS)].channel |= 0x80;</div><div class='del'>-</div><div class='del'>-			if ((bss_index  = retrieve_bss(priv)) != -1) {</div><div class='del'>-				atmel_join_bss(priv, bss_index);</div><div class='del'>-				return;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	priv-&gt;AuthenticationRequestRetryCnt = 0;</div><div class='del'>-	atmel_enter_state(priv,  STATION_STATE_MGMT_ERROR);</div><div class='del'>-	priv-&gt;station_is_associated = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void associate(struct atmel_private *priv, u16 frame_len, u16 subtype)</div><div class='del'>-{</div><div class='del'>-	struct ass_resp_format {</div><div class='del'>-		__le16 capability;</div><div class='del'>-		__le16 status;</div><div class='del'>-		__le16 ass_id;</div><div class='del'>-		u8 el_id;</div><div class='del'>-		u8 length;</div><div class='del'>-		u8 rates[4];</div><div class='del'>-	} *ass_resp = (struct ass_resp_format *)priv-&gt;rx_buf;</div><div class='del'>-</div><div class='del'>-	u16 status = le16_to_cpu(ass_resp-&gt;status);</div><div class='del'>-	u16 ass_id = le16_to_cpu(ass_resp-&gt;ass_id);</div><div class='del'>-	u16 rates_len = ass_resp-&gt;length &gt; 4 ? 4 : ass_resp-&gt;length;</div><div class='del'>-</div><div class='del'>-	union iwreq_data wrqu;</div><div class='del'>-</div><div class='del'>-	if (frame_len &lt; 8 + rates_len)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (status == WLAN_STATUS_SUCCESS) {</div><div class='del'>-		if (subtype == IEEE80211_STYPE_ASSOC_RESP)</div><div class='del'>-			priv-&gt;AssociationRequestRetryCnt = 0;</div><div class='del'>-		else</div><div class='del'>-			priv-&gt;ReAssociationRequestRetryCnt = 0;</div><div class='del'>-</div><div class='del'>-		atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-				MAC_MGMT_MIB_STATION_ID_POS, ass_id &amp; 0x3fff);</div><div class='del'>-		atmel_set_mib(priv, Phy_Mib_Type,</div><div class='del'>-			      PHY_MIB_RATE_SET_POS, ass_resp-&gt;rates, rates_len);</div><div class='del'>-		if (priv-&gt;power_mode == 0) {</div><div class='del'>-			priv-&gt;listen_interval = 1;</div><div class='del'>-			atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-				       MAC_MGMT_MIB_PS_MODE_POS, ACTIVE_MODE);</div><div class='del'>-			atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-					MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;listen_interval = 2;</div><div class='del'>-			atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-				       MAC_MGMT_MIB_PS_MODE_POS,  PS_MODE);</div><div class='del'>-			atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-					MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 2);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		priv-&gt;station_is_associated = 1;</div><div class='del'>-		priv-&gt;station_was_associated = 1;</div><div class='del'>-		atmel_enter_state(priv, STATION_STATE_READY);</div><div class='del'>-</div><div class='del'>-		/* Send association event to userspace */</div><div class='del'>-		wrqu.data.length = 0;</div><div class='del'>-		wrqu.data.flags = 0;</div><div class='del'>-		memcpy(wrqu.ap_addr.sa_data, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-		wrqu.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-		wireless_send_event(priv-&gt;dev, SIOCGIWAP, &amp;wrqu, NULL);</div><div class='del'>-</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (subtype == IEEE80211_STYPE_ASSOC_RESP &amp;&amp;</div><div class='del'>-	    status != WLAN_STATUS_ASSOC_DENIED_RATES &amp;&amp;</div><div class='del'>-	    status != WLAN_STATUS_CAPS_UNSUPPORTED &amp;&amp;</div><div class='del'>-	    priv-&gt;AssociationRequestRetryCnt &lt; MAX_ASSOCIATION_RETRIES) {</div><div class='del'>-		mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-		priv-&gt;AssociationRequestRetryCnt++;</div><div class='del'>-		send_association_request(priv, 0);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (subtype == IEEE80211_STYPE_REASSOC_RESP &amp;&amp;</div><div class='del'>-	    status != WLAN_STATUS_ASSOC_DENIED_RATES &amp;&amp;</div><div class='del'>-	    status != WLAN_STATUS_CAPS_UNSUPPORTED &amp;&amp;</div><div class='del'>-	    priv-&gt;ReAssociationRequestRetryCnt &lt; MAX_ASSOCIATION_RETRIES) {</div><div class='del'>-		mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-		priv-&gt;ReAssociationRequestRetryCnt++;</div><div class='del'>-		send_association_request(priv, 1);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	atmel_enter_state(priv,  STATION_STATE_MGMT_ERROR);</div><div class='del'>-	priv-&gt;station_is_associated = 0;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;connect_to_any_BSS) {</div><div class='del'>-		int bss_index;</div><div class='del'>-		priv-&gt;BSSinfo[(int)(priv-&gt;current_BSS)].channel |= 0x80;</div><div class='del'>-</div><div class='del'>-		if ((bss_index = retrieve_bss(priv)) != -1)</div><div class='del'>-			atmel_join_bss(priv, bss_index);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_join_bss(struct atmel_private *priv, int bss_index)</div><div class='del'>-{</div><div class='del'>-	struct bss_info *bss =  &amp;priv-&gt;BSSinfo[bss_index];</div><div class='del'>-</div><div class='del'>-	memcpy(priv-&gt;CurrentBSSID, bss-&gt;BSSID, ETH_ALEN);</div><div class='del'>-	memcpy(priv-&gt;SSID, bss-&gt;SSID, priv-&gt;SSID_size = bss-&gt;SSIDsize);</div><div class='del'>-</div><div class='del'>-	/* The WPA stuff cares about the current AP address */</div><div class='del'>-	if (priv-&gt;use_wpa)</div><div class='del'>-		build_wpa_mib(priv);</div><div class='del'>-</div><div class='del'>-	/* When switching to AdHoc turn OFF Power Save if needed */</div><div class='del'>-</div><div class='del'>-	if (bss-&gt;BSStype == IW_MODE_ADHOC &amp;&amp;</div><div class='del'>-	    priv-&gt;operating_mode != IW_MODE_ADHOC &amp;&amp;</div><div class='del'>-	    priv-&gt;power_mode) {</div><div class='del'>-		priv-&gt;power_mode = 0;</div><div class='del'>-		priv-&gt;listen_interval = 1;</div><div class='del'>-		atmel_set_mib8(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-			       MAC_MGMT_MIB_PS_MODE_POS,  ACTIVE_MODE);</div><div class='del'>-		atmel_set_mib16(priv, Mac_Mgmt_Mib_Type,</div><div class='del'>-				MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	priv-&gt;operating_mode = bss-&gt;BSStype;</div><div class='del'>-	priv-&gt;channel = bss-&gt;channel &amp; 0x7f;</div><div class='del'>-	priv-&gt;beacon_period = bss-&gt;beacon_period;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;preamble != bss-&gt;preamble) {</div><div class='del'>-		priv-&gt;preamble = bss-&gt;preamble;</div><div class='del'>-		atmel_set_mib8(priv, Local_Mib_Type,</div><div class='del'>-			       LOCAL_MIB_PREAMBLE_TYPE, bss-&gt;preamble);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;wep_is_on &amp;&amp; bss-&gt;UsingWEP) {</div><div class='del'>-		atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-		priv-&gt;station_is_associated = 0;</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;wep_is_on &amp;&amp; !bss-&gt;UsingWEP) {</div><div class='del'>-		atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-		priv-&gt;station_is_associated = 0;</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	atmel_enter_state(priv, STATION_STATE_JOINNING);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;operating_mode == IW_MODE_INFRA)</div><div class='del'>-		join(priv, BSS_TYPE_INFRASTRUCTURE);</div><div class='del'>-	else</div><div class='del'>-		join(priv, BSS_TYPE_AD_HOC);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void restart_search(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	int bss_index;</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;connect_to_any_BSS) {</div><div class='del'>-		atmel_scan(priv, 1);</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;BSSinfo[(int)(priv-&gt;current_BSS)].channel |= 0x80;</div><div class='del'>-</div><div class='del'>-		if ((bss_index = retrieve_bss(priv)) != -1)</div><div class='del'>-			atmel_join_bss(priv, bss_index);</div><div class='del'>-		else</div><div class='del'>-			atmel_scan(priv, 0);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void smooth_rssi(struct atmel_private *priv, u8 rssi)</div><div class='del'>-{</div><div class='del'>-	u8 old = priv-&gt;wstats.qual.level;</div><div class='del'>-	u8 max_rssi = 42; /* 502-rmfd-revd max by experiment, default for now */</div><div class='del'>-</div><div class='del'>-	switch (priv-&gt;firmware_type) {</div><div class='del'>-	case ATMEL_FW_TYPE_502E:</div><div class='del'>-		max_rssi = 63; /* 502-rmfd-reve max by experiment */</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rssi = rssi * 100 / max_rssi;</div><div class='del'>-	if ((rssi + old) % 2)</div><div class='del'>-		priv-&gt;wstats.qual.level = (rssi + old) / 2 + 1;</div><div class='del'>-	else</div><div class='del'>-		priv-&gt;wstats.qual.level = (rssi + old) / 2;</div><div class='del'>-	priv-&gt;wstats.qual.updated |= IW_QUAL_LEVEL_UPDATED;</div><div class='del'>-	priv-&gt;wstats.qual.updated &amp;= ~IW_QUAL_LEVEL_INVALID;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_smooth_qual(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	unsigned long time_diff = (jiffies - priv-&gt;last_qual) / HZ;</div><div class='del'>-	while (time_diff--) {</div><div class='del'>-		priv-&gt;last_qual += HZ;</div><div class='del'>-		priv-&gt;wstats.qual.qual = priv-&gt;wstats.qual.qual / 2;</div><div class='del'>-		priv-&gt;wstats.qual.qual +=</div><div class='del'>-			priv-&gt;beacons_this_sec * priv-&gt;beacon_period * (priv-&gt;wstats.qual.level + 100) / 4000;</div><div class='del'>-		priv-&gt;beacons_this_sec = 0;</div><div class='del'>-	}</div><div class='del'>-	priv-&gt;wstats.qual.updated |= IW_QUAL_QUAL_UPDATED;</div><div class='del'>-	priv-&gt;wstats.qual.updated &amp;= ~IW_QUAL_QUAL_INVALID;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* deals with incoming management frames. */</div><div class='del'>-static void atmel_management_frame(struct atmel_private *priv,</div><div class='del'>-				   struct ieee80211_hdr *header,</div><div class='del'>-				   u16 frame_len, u8 rssi)</div><div class='del'>-{</div><div class='del'>-	u16 subtype;</div><div class='del'>-</div><div class='del'>-	subtype = le16_to_cpu(header-&gt;frame_control) &amp; IEEE80211_FCTL_STYPE;</div><div class='del'>-	switch (subtype) {</div><div class='del'>-	case IEEE80211_STYPE_BEACON:</div><div class='del'>-	case IEEE80211_STYPE_PROBE_RESP:</div><div class='del'>-</div><div class='del'>-		/* beacon frame has multiple variable-length fields -</div><div class='del'>-		   never let an engineer loose with a data structure design. */</div><div class='del'>-		{</div><div class='del'>-			struct beacon_format {</div><div class='del'>-				__le64 timestamp;</div><div class='del'>-				__le16 interval;</div><div class='del'>-				__le16 capability;</div><div class='del'>-				u8 ssid_el_id;</div><div class='del'>-				u8 ssid_length;</div><div class='del'>-				/* ssid here */</div><div class='del'>-				u8 rates_el_id;</div><div class='del'>-				u8 rates_length;</div><div class='del'>-				/* rates here */</div><div class='del'>-				u8 ds_el_id;</div><div class='del'>-				u8 ds_length;</div><div class='del'>-				/* ds here */</div><div class='del'>-			} *beacon = (struct beacon_format *)priv-&gt;rx_buf;</div><div class='del'>-</div><div class='del'>-			u8 channel, rates_length, ssid_length;</div><div class='del'>-			u64 timestamp = le64_to_cpu(beacon-&gt;timestamp);</div><div class='del'>-			u16 beacon_interval = le16_to_cpu(beacon-&gt;interval);</div><div class='del'>-			u16 capability = le16_to_cpu(beacon-&gt;capability);</div><div class='del'>-			u8 *beaconp = priv-&gt;rx_buf;</div><div class='del'>-			ssid_length = beacon-&gt;ssid_length;</div><div class='del'>-			/* this blows chunks. */</div><div class='del'>-			if (frame_len &lt; 14 || frame_len &lt; ssid_length + 15)</div><div class='del'>-				return;</div><div class='del'>-			rates_length = beaconp[beacon-&gt;ssid_length + 15];</div><div class='del'>-			if (frame_len &lt; ssid_length + rates_length + 18)</div><div class='del'>-				return;</div><div class='del'>-			if (ssid_length &gt;  MAX_SSID_LENGTH)</div><div class='del'>-				return;</div><div class='del'>-			channel = beaconp[ssid_length + rates_length + 18];</div><div class='del'>-</div><div class='del'>-			if (priv-&gt;station_state == STATION_STATE_READY) {</div><div class='del'>-				smooth_rssi(priv, rssi);</div><div class='del'>-				if (is_frame_from_current_bss(priv, header)) {</div><div class='del'>-					priv-&gt;beacons_this_sec++;</div><div class='del'>-					atmel_smooth_qual(priv);</div><div class='del'>-					if (priv-&gt;last_beacon_timestamp) {</div><div class='del'>-						/* Note truncate this to 32 bits - kernel can't divide a long */</div><div class='del'>-						u32 beacon_delay = timestamp - priv-&gt;last_beacon_timestamp;</div><div class='del'>-						int beacons = beacon_delay / (beacon_interval * 1000);</div><div class='del'>-						if (beacons &gt; 1)</div><div class='del'>-							priv-&gt;wstats.miss.beacon += beacons - 1;</div><div class='del'>-					}</div><div class='del'>-					priv-&gt;last_beacon_timestamp = timestamp;</div><div class='del'>-					handle_beacon_probe(priv, capability, channel);</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if (priv-&gt;station_state == STATION_STATE_SCANNING)</div><div class='del'>-				store_bss_info(priv, header, capability,</div><div class='del'>-					       beacon_interval, channel, rssi,</div><div class='del'>-					       ssid_length,</div><div class='del'>-					       &amp;beacon-&gt;rates_el_id,</div><div class='del'>-					       subtype == IEEE80211_STYPE_BEACON);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IEEE80211_STYPE_AUTH:</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;station_state == STATION_STATE_AUTHENTICATING)</div><div class='del'>-			authenticate(priv, frame_len);</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IEEE80211_STYPE_ASSOC_RESP:</div><div class='del'>-	case IEEE80211_STYPE_REASSOC_RESP:</div><div class='del'>-</div><div class='del'>-		if (priv-&gt;station_state == STATION_STATE_ASSOCIATING ||</div><div class='del'>-		    priv-&gt;station_state == STATION_STATE_REASSOCIATING)</div><div class='del'>-			associate(priv, frame_len, subtype);</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IEEE80211_STYPE_DISASSOC:</div><div class='del'>-		if (priv-&gt;station_is_associated &amp;&amp;</div><div class='del'>-		    priv-&gt;operating_mode == IW_MODE_INFRA &amp;&amp;</div><div class='del'>-		    is_frame_from_current_bss(priv, header)) {</div><div class='del'>-			priv-&gt;station_was_associated = 0;</div><div class='del'>-			priv-&gt;station_is_associated = 0;</div><div class='del'>-</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_JOINNING);</div><div class='del'>-			join(priv, BSS_TYPE_INFRASTRUCTURE);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case IEEE80211_STYPE_DEAUTH:</div><div class='del'>-		if (priv-&gt;operating_mode == IW_MODE_INFRA &amp;&amp;</div><div class='del'>-		    is_frame_from_current_bss(priv, header)) {</div><div class='del'>-			priv-&gt;station_was_associated = 0;</div><div class='del'>-</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_JOINNING);</div><div class='del'>-			join(priv, BSS_TYPE_INFRASTRUCTURE);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* run when timer expires */</div><div class='del'>-static void atmel_management_timer(struct timer_list *t)</div><div class='del'>-{</div><div class='del'>-	struct atmel_private *priv = from_timer(priv, t, management_timer);</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	/* Check if the card has been yanked. */</div><div class='del'>-	if (priv-&gt;card &amp;&amp; priv-&gt;present_callback &amp;&amp;</div><div class='del'>-		!(*priv-&gt;present_callback)(priv-&gt;card))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-</div><div class='del'>-	switch (priv-&gt;station_state) {</div><div class='del'>-</div><div class='del'>-	case STATION_STATE_AUTHENTICATING:</div><div class='del'>-		if (priv-&gt;AuthenticationRequestRetryCnt &gt;= MAX_AUTHENTICATION_RETRIES) {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-			priv-&gt;station_is_associated = 0;</div><div class='del'>-			priv-&gt;AuthenticationRequestRetryCnt = 0;</div><div class='del'>-			restart_search(priv);</div><div class='del'>-		} else {</div><div class='del'>-			int auth = WLAN_AUTH_OPEN;</div><div class='del'>-			priv-&gt;AuthenticationRequestRetryCnt++;</div><div class='del'>-			priv-&gt;CurrentAuthentTransactionSeqNum = 0x0001;</div><div class='del'>-			mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-			if (priv-&gt;wep_is_on &amp;&amp; priv-&gt;exclude_unencrypted)</div><div class='del'>-				auth = WLAN_AUTH_SHARED_KEY;</div><div class='del'>-			send_authentication_request(priv, auth, NULL, 0);</div><div class='del'>-	  }</div><div class='del'>-	  break;</div><div class='del'>-</div><div class='del'>-	case STATION_STATE_ASSOCIATING:</div><div class='del'>-		if (priv-&gt;AssociationRequestRetryCnt == MAX_ASSOCIATION_RETRIES) {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-			priv-&gt;station_is_associated = 0;</div><div class='del'>-			priv-&gt;AssociationRequestRetryCnt = 0;</div><div class='del'>-			restart_search(priv);</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;AssociationRequestRetryCnt++;</div><div class='del'>-			mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-			send_association_request(priv, 0);</div><div class='del'>-		}</div><div class='del'>-	  break;</div><div class='del'>-</div><div class='del'>-	case STATION_STATE_REASSOCIATING:</div><div class='del'>-		if (priv-&gt;ReAssociationRequestRetryCnt == MAX_ASSOCIATION_RETRIES) {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_MGMT_ERROR);</div><div class='del'>-			priv-&gt;station_is_associated = 0;</div><div class='del'>-			priv-&gt;ReAssociationRequestRetryCnt = 0;</div><div class='del'>-			restart_search(priv);</div><div class='del'>-		} else {</div><div class='del'>-			priv-&gt;ReAssociationRequestRetryCnt++;</div><div class='del'>-			mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-			send_association_request(priv, 1);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	default:</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	spin_unlock_irqrestore(&amp;priv-&gt;irqlock, flags);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_command_irq(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	u8 status = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET));</div><div class='del'>-	u8 command = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_COMMAND_OFFSET));</div><div class='del'>-	int fast_scan;</div><div class='del'>-	union iwreq_data wrqu;</div><div class='del'>-</div><div class='del'>-	if (status == CMD_STATUS_IDLE ||</div><div class='del'>-	    status == CMD_STATUS_IN_PROGRESS)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	switch (command) {</div><div class='del'>-	case CMD_Start:</div><div class='del'>-		if (status == CMD_STATUS_COMPLETE) {</div><div class='del'>-			priv-&gt;station_was_associated = priv-&gt;station_is_associated;</div><div class='del'>-			atmel_get_mib(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_BSSID_POS,</div><div class='del'>-				      (u8 *)priv-&gt;CurrentBSSID, 6);</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_READY);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case CMD_Scan:</div><div class='del'>-		fast_scan = priv-&gt;fast_scan;</div><div class='del'>-		priv-&gt;fast_scan = 0;</div><div class='del'>-</div><div class='del'>-		if (status != CMD_STATUS_COMPLETE) {</div><div class='del'>-			atmel_scan(priv, 1);</div><div class='del'>-		} else {</div><div class='del'>-			int bss_index = retrieve_bss(priv);</div><div class='del'>-			int notify_scan_complete = 1;</div><div class='del'>-			if (bss_index != -1) {</div><div class='del'>-				atmel_join_bss(priv, bss_index);</div><div class='del'>-			} else if (priv-&gt;operating_mode == IW_MODE_ADHOC &amp;&amp;</div><div class='del'>-				   priv-&gt;SSID_size != 0) {</div><div class='del'>-				start(priv, BSS_TYPE_AD_HOC);</div><div class='del'>-			} else {</div><div class='del'>-				priv-&gt;fast_scan = !fast_scan;</div><div class='del'>-				atmel_scan(priv, 1);</div><div class='del'>-				notify_scan_complete = 0;</div><div class='del'>-			}</div><div class='del'>-			priv-&gt;site_survey_state = SITE_SURVEY_COMPLETED;</div><div class='del'>-			if (notify_scan_complete) {</div><div class='del'>-				wrqu.data.length = 0;</div><div class='del'>-				wrqu.data.flags = 0;</div><div class='del'>-				wireless_send_event(priv-&gt;dev, SIOCGIWSCAN, &amp;wrqu, NULL);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case CMD_SiteSurvey:</div><div class='del'>-		priv-&gt;fast_scan = 0;</div><div class='del'>-</div><div class='del'>-		if (status != CMD_STATUS_COMPLETE)</div><div class='del'>-			return;</div><div class='del'>-</div><div class='del'>-		priv-&gt;site_survey_state = SITE_SURVEY_COMPLETED;</div><div class='del'>-		if (priv-&gt;station_is_associated) {</div><div class='del'>-			atmel_enter_state(priv, STATION_STATE_READY);</div><div class='del'>-			wrqu.data.length = 0;</div><div class='del'>-			wrqu.data.flags = 0;</div><div class='del'>-			wireless_send_event(priv-&gt;dev, SIOCGIWSCAN, &amp;wrqu, NULL);</div><div class='del'>-		} else {</div><div class='del'>-			atmel_scan(priv, 1);</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-</div><div class='del'>-	case CMD_Join:</div><div class='del'>-		if (status == CMD_STATUS_COMPLETE) {</div><div class='del'>-			if (priv-&gt;operating_mode == IW_MODE_ADHOC) {</div><div class='del'>-				priv-&gt;station_was_associated = priv-&gt;station_is_associated;</div><div class='del'>-				atmel_enter_state(priv, STATION_STATE_READY);</div><div class='del'>-			} else {</div><div class='del'>-				int auth = WLAN_AUTH_OPEN;</div><div class='del'>-				priv-&gt;AuthenticationRequestRetryCnt = 0;</div><div class='del'>-				atmel_enter_state(priv, STATION_STATE_AUTHENTICATING);</div><div class='del'>-</div><div class='del'>-				mod_timer(&amp;priv-&gt;management_timer, jiffies + MGMT_JIFFIES);</div><div class='del'>-				priv-&gt;CurrentAuthentTransactionSeqNum = 0x0001;</div><div class='del'>-				if (priv-&gt;wep_is_on &amp;&amp; priv-&gt;exclude_unencrypted)</div><div class='del'>-					auth = WLAN_AUTH_SHARED_KEY;</div><div class='del'>-				send_authentication_request(priv, auth, NULL, 0);</div><div class='del'>-			}</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		atmel_scan(priv, 1);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_wakeup_firmware(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	struct host_info_struct *iface = &amp;priv-&gt;host_info;</div><div class='del'>-	u16 mr1, mr3;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;card_type == CARD_TYPE_SPI_FLASH)</div><div class='del'>-		atmel_set_gcr(priv-&gt;dev, GCR_REMAP);</div><div class='del'>-</div><div class='del'>-	/* wake up on-board processor */</div><div class='del'>-	atmel_clear_gcr(priv-&gt;dev, 0x0040);</div><div class='del'>-	atmel_write16(priv-&gt;dev, BSR, BSS_SRAM);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;card_type == CARD_TYPE_SPI_FLASH)</div><div class='del'>-		mdelay(100);</div><div class='del'>-</div><div class='del'>-	/* and wait for it */</div><div class='del'>-	for (i = LOOP_RETRY_LIMIT; i; i--) {</div><div class='del'>-		mr1 = atmel_read16(priv-&gt;dev, MR1);</div><div class='del'>-		mr3 = atmel_read16(priv-&gt;dev, MR3);</div><div class='del'>-</div><div class='del'>-		if (mr3 &amp; MAC_BOOT_COMPLETE)</div><div class='del'>-			break;</div><div class='del'>-		if (mr1 &amp; MAC_BOOT_COMPLETE &amp;&amp;</div><div class='del'>-		    priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-			break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (i == 0) {</div><div class='del'>-		printk(KERN_ALERT "%s: MAC failed to boot.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if ((priv-&gt;host_info_base = atmel_read16(priv-&gt;dev, MR2)) == 0xffff) {</div><div class='del'>-		printk(KERN_ALERT "%s: card missing.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* now check for completion of MAC initialization through</div><div class='del'>-	   the FunCtrl field of the IFACE, poll MR1 to detect completion of</div><div class='del'>-	   MAC initialization, check completion status, set interrupt mask,</div><div class='del'>-	   enables interrupts and calls Tx and Rx initialization functions */</div><div class='del'>-</div><div class='del'>-	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET), FUNC_CTRL_INIT_COMPLETE);</div><div class='del'>-</div><div class='del'>-	for (i = LOOP_RETRY_LIMIT; i; i--) {</div><div class='del'>-		mr1 = atmel_read16(priv-&gt;dev, MR1);</div><div class='del'>-		mr3 = atmel_read16(priv-&gt;dev, MR3);</div><div class='del'>-</div><div class='del'>-		if (mr3 &amp; MAC_INIT_COMPLETE)</div><div class='del'>-			break;</div><div class='del'>-		if (mr1 &amp; MAC_INIT_COMPLETE &amp;&amp;</div><div class='del'>-		    priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-			break;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (i == 0) {</div><div class='del'>-		printk(KERN_ALERT "%s: MAC failed to initialise.\n",</div><div class='del'>-				priv-&gt;dev-&gt;name);</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Check for MAC_INIT_OK only on the register that the MAC_INIT_OK was set */</div><div class='del'>-	if ((mr3 &amp; MAC_INIT_COMPLETE) &amp;&amp;</div><div class='del'>-	    !(atmel_read16(priv-&gt;dev, MR3) &amp; MAC_INIT_OK)) {</div><div class='del'>-		printk(KERN_ALERT "%s: MAC failed MR3 self-test.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-	if ((mr1 &amp; MAC_INIT_COMPLETE) &amp;&amp;</div><div class='del'>-	    !(atmel_read16(priv-&gt;dev, MR1) &amp; MAC_INIT_OK)) {</div><div class='del'>-		printk(KERN_ALERT "%s: MAC failed MR1 self-test.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-		return -EIO;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	atmel_copy_to_host(priv-&gt;dev, (unsigned char *)iface,</div><div class='del'>-			   priv-&gt;host_info_base, sizeof(*iface));</div><div class='del'>-</div><div class='del'>-	iface-&gt;tx_buff_pos = le16_to_cpu(iface-&gt;tx_buff_pos);</div><div class='del'>-	iface-&gt;tx_buff_size = le16_to_cpu(iface-&gt;tx_buff_size);</div><div class='del'>-	iface-&gt;tx_desc_pos = le16_to_cpu(iface-&gt;tx_desc_pos);</div><div class='del'>-	iface-&gt;tx_desc_count = le16_to_cpu(iface-&gt;tx_desc_count);</div><div class='del'>-	iface-&gt;rx_buff_pos = le16_to_cpu(iface-&gt;rx_buff_pos);</div><div class='del'>-	iface-&gt;rx_buff_size = le16_to_cpu(iface-&gt;rx_buff_size);</div><div class='del'>-	iface-&gt;rx_desc_pos = le16_to_cpu(iface-&gt;rx_desc_pos);</div><div class='del'>-	iface-&gt;rx_desc_count = le16_to_cpu(iface-&gt;rx_desc_count);</div><div class='del'>-	iface-&gt;build_version = le16_to_cpu(iface-&gt;build_version);</div><div class='del'>-	iface-&gt;command_pos = le16_to_cpu(iface-&gt;command_pos);</div><div class='del'>-	iface-&gt;major_version = le16_to_cpu(iface-&gt;major_version);</div><div class='del'>-	iface-&gt;minor_version = le16_to_cpu(iface-&gt;minor_version);</div><div class='del'>-	iface-&gt;func_ctrl = le16_to_cpu(iface-&gt;func_ctrl);</div><div class='del'>-	iface-&gt;mac_status = le16_to_cpu(iface-&gt;mac_status);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* determine type of memory and MAC address */</div><div class='del'>-static int probe_atmel_card(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	int rc = 0;</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	u8 addr[ETH_ALEN] = {};</div><div class='del'>-</div><div class='del'>-	/* reset pccard */</div><div class='del'>-	if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-		atmel_write16(dev, GCR, 0x0060);</div><div class='del'>-</div><div class='del'>-	atmel_write16(dev, GCR, 0x0040);</div><div class='del'>-	msleep(500);</div><div class='del'>-</div><div class='del'>-	if (atmel_read16(dev, MR2) == 0) {</div><div class='del'>-		/* No stored firmware so load a small stub which just</div><div class='del'>-		   tells us the MAC address */</div><div class='del'>-		int i;</div><div class='del'>-		priv-&gt;card_type = CARD_TYPE_EEPROM;</div><div class='del'>-		atmel_write16(dev, BSR, BSS_IRAM);</div><div class='del'>-		atmel_copy_to_card(dev, 0, mac_reader, sizeof(mac_reader));</div><div class='del'>-		atmel_set_gcr(dev, GCR_REMAP);</div><div class='del'>-		atmel_clear_gcr(priv-&gt;dev, 0x0040);</div><div class='del'>-		atmel_write16(dev, BSR, BSS_SRAM);</div><div class='del'>-		for (i = LOOP_RETRY_LIMIT; i; i--)</div><div class='del'>-			if (atmel_read16(dev, MR3) &amp; MAC_BOOT_COMPLETE)</div><div class='del'>-				break;</div><div class='del'>-		if (i == 0) {</div><div class='del'>-			printk(KERN_ALERT "%s: MAC failed to boot MAC address reader.\n", dev-&gt;name);</div><div class='del'>-		} else {</div><div class='del'>-</div><div class='del'>-			atmel_copy_to_host(dev, addr, atmel_read16(dev, MR2), 6);</div><div class='del'>-			eth_hw_addr_set(dev, addr);</div><div class='del'>-			/* got address, now squash it again until the network</div><div class='del'>-			   interface is opened */</div><div class='del'>-			if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-				atmel_write16(dev, GCR, 0x0060);</div><div class='del'>-			atmel_write16(dev, GCR, 0x0040);</div><div class='del'>-			rc = 1;</div><div class='del'>-		}</div><div class='del'>-	} else if (atmel_read16(dev, MR4) == 0) {</div><div class='del'>-		/* Mac address easy in this case. */</div><div class='del'>-		priv-&gt;card_type = CARD_TYPE_PARALLEL_FLASH;</div><div class='del'>-		atmel_write16(dev,  BSR, 1);</div><div class='del'>-		atmel_copy_to_host(dev, addr, 0xc000, 6);</div><div class='del'>-		eth_hw_addr_set(dev, addr);</div><div class='del'>-		atmel_write16(dev,  BSR, 0x200);</div><div class='del'>-		rc = 1;</div><div class='del'>-	} else {</div><div class='del'>-		/* Standard firmware in flash, boot it up and ask</div><div class='del'>-		   for the Mac Address */</div><div class='del'>-		priv-&gt;card_type = CARD_TYPE_SPI_FLASH;</div><div class='del'>-		if (atmel_wakeup_firmware(priv) == 0) {</div><div class='del'>-			atmel_get_mib(priv, Mac_Address_Mib_Type, 0, addr, 6);</div><div class='del'>-			eth_hw_addr_set(dev, addr);</div><div class='del'>-</div><div class='del'>-			/* got address, now squash it again until the network</div><div class='del'>-			   interface is opened */</div><div class='del'>-			if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-				atmel_write16(dev, GCR, 0x0060);</div><div class='del'>-			atmel_write16(dev, GCR, 0x0040);</div><div class='del'>-			rc = 1;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (rc) {</div><div class='del'>-		if (dev-&gt;dev_addr[0] == 0xFF) {</div><div class='del'>-			static const u8 default_mac[] = {</div><div class='del'>-				0x00, 0x04, 0x25, 0x00, 0x00, 0x00</div><div class='del'>-			};</div><div class='del'>-			printk(KERN_ALERT "%s: *** Invalid MAC address. UPGRADE Firmware ****\n", dev-&gt;name);</div><div class='del'>-			eth_hw_addr_set(dev, default_mac);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Move the encyption information on the MIB structure.</div><div class='del'>-   This routine is for the pre-WPA firmware: later firmware has</div><div class='del'>-   a different format MIB and a different routine. */</div><div class='del'>-static void build_wep_mib(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	struct { /* NB this is matched to the hardware, don't change. */</div><div class='del'>-		u8 wep_is_on;</div><div class='del'>-		u8 default_key; /* 0..3 */</div><div class='del'>-		u8 reserved;</div><div class='del'>-		u8 exclude_unencrypted;</div><div class='del'>-</div><div class='del'>-		u32 WEPICV_error_count;</div><div class='del'>-		u32 WEP_excluded_count;</div><div class='del'>-</div><div class='del'>-		u8 wep_keys[MAX_ENCRYPTION_KEYS][13];</div><div class='del'>-		u8 encryption_level; /* 0, 1, 2 */</div><div class='del'>-		u8 reserved2[3];</div><div class='del'>-	} mib;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	mib.wep_is_on = priv-&gt;wep_is_on;</div><div class='del'>-	if (priv-&gt;wep_is_on) {</div><div class='del'>-		if (priv-&gt;wep_key_len[priv-&gt;default_key] &gt; 5)</div><div class='del'>-			mib.encryption_level = 2;</div><div class='del'>-		else</div><div class='del'>-			mib.encryption_level = 1;</div><div class='del'>-	} else {</div><div class='del'>-		mib.encryption_level = 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	mib.default_key = priv-&gt;default_key;</div><div class='del'>-	mib.exclude_unencrypted = priv-&gt;exclude_unencrypted;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_ENCRYPTION_KEYS; i++)</div><div class='del'>-		memcpy(mib.wep_keys[i], priv-&gt;wep_keys[i], 13);</div><div class='del'>-</div><div class='del'>-	atmel_set_mib(priv, Mac_Wep_Mib_Type, 0, (u8 *)&amp;mib, sizeof(mib));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void build_wpa_mib(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	/* This is for the later (WPA enabled) firmware. */</div><div class='del'>-</div><div class='del'>-	struct { /* NB this is matched to the hardware, don't change. */</div><div class='del'>-		u8 cipher_default_key_value[MAX_ENCRYPTION_KEYS][MAX_ENCRYPTION_KEY_SIZE];</div><div class='del'>-		u8 receiver_address[ETH_ALEN];</div><div class='del'>-		u8 wep_is_on;</div><div class='del'>-		u8 default_key; /* 0..3 */</div><div class='del'>-		u8 group_key;</div><div class='del'>-		u8 exclude_unencrypted;</div><div class='del'>-		u8 encryption_type;</div><div class='del'>-		u8 reserved;</div><div class='del'>-</div><div class='del'>-		u32 WEPICV_error_count;</div><div class='del'>-		u32 WEP_excluded_count;</div><div class='del'>-</div><div class='del'>-		u8 key_RSC[4][8];</div><div class='del'>-	} mib;</div><div class='del'>-</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	mib.wep_is_on = priv-&gt;wep_is_on;</div><div class='del'>-	mib.exclude_unencrypted = priv-&gt;exclude_unencrypted;</div><div class='del'>-	memcpy(mib.receiver_address, priv-&gt;CurrentBSSID, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	/* zero all the keys before adding in valid ones. */</div><div class='del'>-	memset(mib.cipher_default_key_value, 0, sizeof(mib.cipher_default_key_value));</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;wep_is_on) {</div><div class='del'>-		/* There's a comment in the Atmel code to the effect that this</div><div class='del'>-		   is only valid when still using WEP, it may need to be set to</div><div class='del'>-		   something to use WPA */</div><div class='del'>-		memset(mib.key_RSC, 0, sizeof(mib.key_RSC));</div><div class='del'>-</div><div class='del'>-		mib.default_key = mib.group_key = 255;</div><div class='del'>-		for (i = 0; i &lt; MAX_ENCRYPTION_KEYS; i++) {</div><div class='del'>-			if (priv-&gt;wep_key_len[i] &gt; 0) {</div><div class='del'>-				memcpy(mib.cipher_default_key_value[i], priv-&gt;wep_keys[i], MAX_ENCRYPTION_KEY_SIZE);</div><div class='del'>-				if (i == priv-&gt;default_key) {</div><div class='del'>-					mib.default_key = i;</div><div class='del'>-					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-1] = 7;</div><div class='del'>-					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-2] = priv-&gt;pairwise_cipher_suite;</div><div class='del'>-				} else {</div><div class='del'>-					mib.group_key = i;</div><div class='del'>-					priv-&gt;group_cipher_suite = priv-&gt;pairwise_cipher_suite;</div><div class='del'>-					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-1] = 1;</div><div class='del'>-					mib.cipher_default_key_value[i][MAX_ENCRYPTION_KEY_SIZE-2] = priv-&gt;group_cipher_suite;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		if (mib.default_key == 255)</div><div class='del'>-			mib.default_key = mib.group_key != 255 ? mib.group_key : 0;</div><div class='del'>-		if (mib.group_key == 255)</div><div class='del'>-			mib.group_key = mib.default_key;</div><div class='del'>-</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	atmel_set_mib(priv, Mac_Wep_Mib_Type, 0, (u8 *)&amp;mib, sizeof(mib));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int reset_atmel_card(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	/* do everything necessary to wake up the hardware, including</div><div class='del'>-	   waiting for the lightning strike and throwing the knife switch....</div><div class='del'>-</div><div class='del'>-	   set all the Mib values which matter in the card to match</div><div class='del'>-	   their settings in the atmel_private structure. Some of these</div><div class='del'>-	   can be altered on the fly, but many (WEP, infrastructure or ad-hoc)</div><div class='del'>-	   can only be changed by tearing down the world and coming back through</div><div class='del'>-	   here.</div><div class='del'>-</div><div class='del'>-	   This routine is also responsible for initialising some</div><div class='del'>-	   hardware-specific fields in the atmel_private structure,</div><div class='del'>-	   including a copy of the firmware's hostinfo structure</div><div class='del'>-	   which is the route into the rest of the firmware datastructures. */</div><div class='del'>-</div><div class='del'>-	struct atmel_private *priv = netdev_priv(dev);</div><div class='del'>-	u8 configuration;</div><div class='del'>-	int old_state = priv-&gt;station_state;</div><div class='del'>-	int err = 0;</div><div class='del'>-</div><div class='del'>-	/* data to add to the firmware names, in priority order</div><div class='del'>-	   this implemenents firmware versioning */</div><div class='del'>-</div><div class='del'>-	static char *firmware_modifier[] = {</div><div class='del'>-		"-wpa",</div><div class='del'>-		"",</div><div class='del'>-		NULL</div><div class='del'>-	};</div><div class='del'>-</div><div class='del'>-	/* reset pccard */</div><div class='del'>-	if (priv-&gt;bus_type == BUS_TYPE_PCCARD)</div><div class='del'>-		atmel_write16(priv-&gt;dev, GCR, 0x0060);</div><div class='del'>-</div><div class='del'>-	/* stop card , disable interrupts */</div><div class='del'>-	atmel_write16(priv-&gt;dev, GCR, 0x0040);</div><div class='del'>-</div><div class='del'>-	if (priv-&gt;card_type == CARD_TYPE_EEPROM) {</div><div class='del'>-		/* copy in firmware if needed */</div><div class='del'>-		const struct firmware *fw_entry = NULL;</div><div class='del'>-		const unsigned char *fw;</div><div class='del'>-		int len = priv-&gt;firmware_length;</div><div class='del'>-		if (!(fw = priv-&gt;firmware)) {</div><div class='del'>-			if (priv-&gt;firmware_type == ATMEL_FW_TYPE_NONE) {</div><div class='del'>-				if (strlen(priv-&gt;firmware_id) == 0) {</div><div class='del'>-					printk(KERN_INFO</div><div class='del'>-					       "%s: card type is unknown: assuming at76c502 firmware is OK.\n",</div><div class='del'>-					       dev-&gt;name);</div><div class='del'>-					printk(KERN_INFO</div><div class='del'>-					       "%s: if not, use the firmware= module parameter.\n",</div><div class='del'>-					       dev-&gt;name);</div><div class='del'>-					strcpy(priv-&gt;firmware_id, "atmel_at76c502.bin");</div><div class='del'>-				}</div><div class='del'>-				err = request_firmware(&amp;fw_entry, priv-&gt;firmware_id, priv-&gt;sys_dev);</div><div class='del'>-				if (err != 0) {</div><div class='del'>-					printk(KERN_ALERT</div><div class='del'>-					       "%s: firmware %s is missing, cannot continue.\n",</div><div class='del'>-					       dev-&gt;name, priv-&gt;firmware_id);</div><div class='del'>-					return err;</div><div class='del'>-				}</div><div class='del'>-			} else {</div><div class='del'>-				int fw_index = 0;</div><div class='del'>-				int success = 0;</div><div class='del'>-</div><div class='del'>-				/* get firmware filename entry based on firmware type ID */</div><div class='del'>-				while (fw_table[fw_index].fw_type != priv-&gt;firmware_type</div><div class='del'>-						&amp;&amp; fw_table[fw_index].fw_type != ATMEL_FW_TYPE_NONE)</div><div class='del'>-					fw_index++;</div><div class='del'>-</div><div class='del'>-				/* construct the actual firmware file name */</div><div class='del'>-				if (fw_table[fw_index].fw_type != ATMEL_FW_TYPE_NONE) {</div><div class='del'>-					int i;</div><div class='del'>-					for (i = 0; firmware_modifier[i]; i++) {</div><div class='del'>-						snprintf(priv-&gt;firmware_id, 32, "%s%s.%s", fw_table[fw_index].fw_file,</div><div class='del'>-							firmware_modifier[i], fw_table[fw_index].fw_file_ext);</div><div class='del'>-						priv-&gt;firmware_id[31] = '\0';</div><div class='del'>-						if (request_firmware(&amp;fw_entry, priv-&gt;firmware_id, priv-&gt;sys_dev) == 0) {</div><div class='del'>-							success = 1;</div><div class='del'>-							break;</div><div class='del'>-						}</div><div class='del'>-					}</div><div class='del'>-				}</div><div class='del'>-				if (!success) {</div><div class='del'>-					printk(KERN_ALERT</div><div class='del'>-					       "%s: firmware %s is missing, cannot start.\n",</div><div class='del'>-					       dev-&gt;name, priv-&gt;firmware_id);</div><div class='del'>-					priv-&gt;firmware_id[0] = '\0';</div><div class='del'>-					return -ENOENT;</div><div class='del'>-				}</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			fw = fw_entry-&gt;data;</div><div class='del'>-			len = fw_entry-&gt;size;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (len &lt;= 0x6000) {</div><div class='del'>-			atmel_write16(priv-&gt;dev, BSR, BSS_IRAM);</div><div class='del'>-			atmel_copy_to_card(priv-&gt;dev, 0, fw, len);</div><div class='del'>-			atmel_set_gcr(priv-&gt;dev, GCR_REMAP);</div><div class='del'>-		} else {</div><div class='del'>-			/* Remap */</div><div class='del'>-			atmel_set_gcr(priv-&gt;dev, GCR_REMAP);</div><div class='del'>-			atmel_write16(priv-&gt;dev, BSR, BSS_IRAM);</div><div class='del'>-			atmel_copy_to_card(priv-&gt;dev, 0, fw, 0x6000);</div><div class='del'>-			atmel_write16(priv-&gt;dev, BSR, 0x2ff);</div><div class='del'>-			atmel_copy_to_card(priv-&gt;dev, 0x8000, &amp;fw[0x6000], len - 0x6000);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		release_firmware(fw_entry);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	err = atmel_wakeup_firmware(priv);</div><div class='del'>-	if (err != 0)</div><div class='del'>-		return err;</div><div class='del'>-</div><div class='del'>-	/* Check the version and set the correct flag for wpa stuff,</div><div class='del'>-	   old and new firmware is incompatible.</div><div class='del'>-	   The pre-wpa 3com firmware reports major version 5,</div><div class='del'>-	   the wpa 3com firmware is major version 4 and doesn't need</div><div class='del'>-	   the 3com broken-ness filter. */</div><div class='del'>-	priv-&gt;use_wpa = (priv-&gt;host_info.major_version == 4);</div><div class='del'>-	priv-&gt;radio_on_broken = (priv-&gt;host_info.major_version == 5);</div><div class='del'>-</div><div class='del'>-	/* unmask all irq sources */</div><div class='del'>-	atmel_wmem8(priv, atmel_hi(priv, IFACE_INT_MASK_OFFSET), 0xff);</div><div class='del'>-</div><div class='del'>-	/* int Tx system and enable Tx */</div><div class='del'>-	atmel_wmem8(priv, atmel_tx(priv, TX_DESC_FLAGS_OFFSET, 0), 0);</div><div class='del'>-	atmel_wmem32(priv, atmel_tx(priv, TX_DESC_NEXT_OFFSET, 0), 0x80000000L);</div><div class='del'>-	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_POS_OFFSET, 0), 0);</div><div class='del'>-	atmel_wmem16(priv, atmel_tx(priv, TX_DESC_SIZE_OFFSET, 0), 0);</div><div class='del'>-</div><div class='del'>-	priv-&gt;tx_desc_free = priv-&gt;host_info.tx_desc_count;</div><div class='del'>-	priv-&gt;tx_desc_head = 0;</div><div class='del'>-	priv-&gt;tx_desc_tail = 0;</div><div class='del'>-	priv-&gt;tx_desc_previous = 0;</div><div class='del'>-	priv-&gt;tx_free_mem = priv-&gt;host_info.tx_buff_size;</div><div class='del'>-	priv-&gt;tx_buff_head = 0;</div><div class='del'>-	priv-&gt;tx_buff_tail = 0;</div><div class='del'>-</div><div class='del'>-	configuration = atmel_rmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET));</div><div class='del'>-	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET),</div><div class='del'>-				   configuration | FUNC_CTRL_TxENABLE);</div><div class='del'>-</div><div class='del'>-	/* init Rx system and enable */</div><div class='del'>-	priv-&gt;rx_desc_head = 0;</div><div class='del'>-</div><div class='del'>-	configuration = atmel_rmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET));</div><div class='del'>-	atmel_wmem8(priv, atmel_hi(priv, IFACE_FUNC_CTRL_OFFSET),</div><div class='del'>-				   configuration | FUNC_CTRL_RxENABLE);</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;radio_on_broken) {</div><div class='del'>-		if (atmel_send_command_wait(priv, CMD_EnableRadio, NULL, 0) ==</div><div class='del'>-		    CMD_STATUS_REJECTED_RADIO_OFF) {</div><div class='del'>-			printk(KERN_INFO "%s: cannot turn the radio on.\n",</div><div class='del'>-			       dev-&gt;name);</div><div class='del'>-			return -EIO;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* set up enough MIB values to run. */</div><div class='del'>-	atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_AUTO_TX_RATE_POS, priv-&gt;auto_tx_rate);</div><div class='del'>-	atmel_set_mib8(priv, Local_Mib_Type,  LOCAL_MIB_TX_PROMISCUOUS_POS,  PROM_MODE_OFF);</div><div class='del'>-	atmel_set_mib16(priv, Mac_Mib_Type, MAC_MIB_RTS_THRESHOLD_POS, priv-&gt;rts_threshold);</div><div class='del'>-	atmel_set_mib16(priv, Mac_Mib_Type, MAC_MIB_FRAG_THRESHOLD_POS, priv-&gt;frag_threshold);</div><div class='del'>-	atmel_set_mib8(priv, Mac_Mib_Type, MAC_MIB_SHORT_RETRY_POS, priv-&gt;short_retry);</div><div class='del'>-	atmel_set_mib8(priv, Mac_Mib_Type, MAC_MIB_LONG_RETRY_POS, priv-&gt;long_retry);</div><div class='del'>-	atmel_set_mib8(priv, Local_Mib_Type, LOCAL_MIB_PREAMBLE_TYPE, priv-&gt;preamble);</div><div class='del'>-	atmel_set_mib(priv, Mac_Address_Mib_Type, MAC_ADDR_MIB_MAC_ADDR_POS,</div><div class='del'>-		      priv-&gt;dev-&gt;dev_addr, 6);</div><div class='del'>-	atmel_set_mib8(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_PS_MODE_POS, ACTIVE_MODE);</div><div class='del'>-	atmel_set_mib16(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_LISTEN_INTERVAL_POS, 1);</div><div class='del'>-	atmel_set_mib16(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_BEACON_PER_POS, priv-&gt;default_beacon_period);</div><div class='del'>-	atmel_set_mib(priv, Phy_Mib_Type, PHY_MIB_RATE_SET_POS, atmel_basic_rates, 4);</div><div class='del'>-	atmel_set_mib8(priv, Mac_Mgmt_Mib_Type, MAC_MGMT_MIB_CUR_PRIVACY_POS, priv-&gt;wep_is_on);</div><div class='del'>-	if (priv-&gt;use_wpa)</div><div class='del'>-		build_wpa_mib(priv);</div><div class='del'>-	else</div><div class='del'>-		build_wep_mib(priv);</div><div class='del'>-</div><div class='del'>-	if (old_state == STATION_STATE_READY) {</div><div class='del'>-		union iwreq_data wrqu;</div><div class='del'>-</div><div class='del'>-		wrqu.data.length = 0;</div><div class='del'>-		wrqu.data.flags = 0;</div><div class='del'>-		wrqu.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-		eth_zero_addr(wrqu.ap_addr.sa_data);</div><div class='del'>-		wireless_send_event(priv-&gt;dev, SIOCGIWAP, &amp;wrqu, NULL);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_send_command(struct atmel_private *priv, int command,</div><div class='del'>-			       void *cmd, int cmd_size)</div><div class='del'>-{</div><div class='del'>-	if (cmd)</div><div class='del'>-		atmel_copy_to_card(priv-&gt;dev, atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET),</div><div class='del'>-				   cmd, cmd_size);</div><div class='del'>-</div><div class='del'>-	atmel_wmem8(priv, atmel_co(priv, CMD_BLOCK_COMMAND_OFFSET), command);</div><div class='del'>-	atmel_wmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET), 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_send_command_wait(struct atmel_private *priv, int command,</div><div class='del'>-				   void *cmd, int cmd_size)</div><div class='del'>-{</div><div class='del'>-	int i, status;</div><div class='del'>-</div><div class='del'>-	atmel_send_command(priv, command, cmd, cmd_size);</div><div class='del'>-</div><div class='del'>-	for (i = 5000; i; i--) {</div><div class='del'>-		status = atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_STATUS_OFFSET));</div><div class='del'>-		if (status != CMD_STATUS_IDLE &amp;&amp;</div><div class='del'>-		    status != CMD_STATUS_IN_PROGRESS)</div><div class='del'>-			break;</div><div class='del'>-		udelay(20);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (i == 0) {</div><div class='del'>-		printk(KERN_ALERT "%s: failed to contact MAC.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-		status =  CMD_STATUS_HOST_ERROR;</div><div class='del'>-	} else {</div><div class='del'>-		if (command != CMD_EnableRadio)</div><div class='del'>-			status = CMD_STATUS_COMPLETE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return status;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u8 atmel_get_mib8(struct atmel_private *priv, u8 type, u8 index)</div><div class='del'>-{</div><div class='del'>-	struct get_set_mib m;</div><div class='del'>-	m.type = type;</div><div class='del'>-	m.size = 1;</div><div class='del'>-	m.index = index;</div><div class='del'>-</div><div class='del'>-	atmel_send_command_wait(priv, CMD_Get_MIB_Vars, &amp;m, MIB_HEADER_SIZE + 1);</div><div class='del'>-	return atmel_rmem8(priv, atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET + MIB_HEADER_SIZE));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_set_mib8(struct atmel_private *priv, u8 type, u8 index, u8 data)</div><div class='del'>-{</div><div class='del'>-	struct get_set_mib m;</div><div class='del'>-	m.type = type;</div><div class='del'>-	m.size = 1;</div><div class='del'>-	m.index = index;</div><div class='del'>-	m.data[0] = data;</div><div class='del'>-</div><div class='del'>-	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &amp;m, MIB_HEADER_SIZE + 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_set_mib16(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			    u16 data)</div><div class='del'>-{</div><div class='del'>-	struct get_set_mib m;</div><div class='del'>-	m.type = type;</div><div class='del'>-	m.size = 2;</div><div class='del'>-	m.index = index;</div><div class='del'>-	m.data[0] = data;</div><div class='del'>-	m.data[1] = data &gt;&gt; 8;</div><div class='del'>-</div><div class='del'>-	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &amp;m, MIB_HEADER_SIZE + 2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_set_mib(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			  const u8 *data, int data_len)</div><div class='del'>-{</div><div class='del'>-	struct get_set_mib m;</div><div class='del'>-	m.type = type;</div><div class='del'>-	m.size = data_len;</div><div class='del'>-	m.index = index;</div><div class='del'>-</div><div class='del'>-	if (data_len &gt; MIB_MAX_DATA_BYTES)</div><div class='del'>-		printk(KERN_ALERT "%s: MIB buffer too small.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-</div><div class='del'>-	memcpy(m.data, data, data_len);</div><div class='del'>-	atmel_send_command_wait(priv, CMD_Set_MIB_Vars, &amp;m, MIB_HEADER_SIZE + data_len);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_get_mib(struct atmel_private *priv, u8 type, u8 index,</div><div class='del'>-			  u8 *data, int data_len)</div><div class='del'>-{</div><div class='del'>-	struct get_set_mib m;</div><div class='del'>-	m.type = type;</div><div class='del'>-	m.size = data_len;</div><div class='del'>-	m.index = index;</div><div class='del'>-</div><div class='del'>-	if (data_len &gt; MIB_MAX_DATA_BYTES)</div><div class='del'>-		printk(KERN_ALERT "%s: MIB buffer too small.\n", priv-&gt;dev-&gt;name);</div><div class='del'>-</div><div class='del'>-	atmel_send_command_wait(priv, CMD_Get_MIB_Vars, &amp;m, MIB_HEADER_SIZE + data_len);</div><div class='del'>-	atmel_copy_to_host(priv-&gt;dev, data,</div><div class='del'>-			   atmel_co(priv, CMD_BLOCK_PARAMETERS_OFFSET + MIB_HEADER_SIZE), data_len);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_writeAR(struct net_device *dev, u16 data)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	outw(data, dev-&gt;base_addr + AR);</div><div class='del'>-	/* Address register appears to need some convincing..... */</div><div class='del'>-	for (i = 0; data != inw(dev-&gt;base_addr + AR) &amp;&amp; i &lt; 10; i++)</div><div class='del'>-		outw(data, dev-&gt;base_addr + AR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_copy_to_card(struct net_device *dev, u16 dest,</div><div class='del'>-			       const unsigned char *src, u16 len)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	atmel_writeAR(dev, dest);</div><div class='del'>-	if (dest % 2) {</div><div class='del'>-		atmel_write8(dev, DR, *src);</div><div class='del'>-		src++; len--;</div><div class='del'>-	}</div><div class='del'>-	for (i = len; i &gt; 1 ; i -= 2) {</div><div class='del'>-		u8 lb = *src++;</div><div class='del'>-		u8 hb = *src++;</div><div class='del'>-		atmel_write16(dev, DR, lb | (hb &lt;&lt; 8));</div><div class='del'>-	}</div><div class='del'>-	if (i)</div><div class='del'>-		atmel_write8(dev, DR, *src);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_copy_to_host(struct net_device *dev, unsigned char *dest,</div><div class='del'>-			       u16 src, u16 len)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	atmel_writeAR(dev, src);</div><div class='del'>-	if (src % 2) {</div><div class='del'>-		*dest = atmel_read8(dev, DR);</div><div class='del'>-		dest++; len--;</div><div class='del'>-	}</div><div class='del'>-	for (i = len; i &gt; 1 ; i -= 2) {</div><div class='del'>-		u16 hw = atmel_read16(dev, DR);</div><div class='del'>-		*dest++ = hw;</div><div class='del'>-		*dest++ = hw &gt;&gt; 8;</div><div class='del'>-	}</div><div class='del'>-	if (i)</div><div class='del'>-		*dest = atmel_read8(dev, DR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_set_gcr(struct net_device *dev, u16 mask)</div><div class='del'>-{</div><div class='del'>-	outw(inw(dev-&gt;base_addr + GCR) | mask, dev-&gt;base_addr + GCR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_clear_gcr(struct net_device *dev, u16 mask)</div><div class='del'>-{</div><div class='del'>-	outw(inw(dev-&gt;base_addr + GCR) &amp; ~mask, dev-&gt;base_addr + GCR);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_lock_mac(struct atmel_private *priv)</div><div class='del'>-{</div><div class='del'>-	int i, j = 20;</div><div class='del'>- retry:</div><div class='del'>-	for (i = 5000; i; i--) {</div><div class='del'>-		if (!atmel_rmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_HOST_OFFSET)))</div><div class='del'>-			break;</div><div class='del'>-		udelay(20);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (!i)</div><div class='del'>-		return 0; /* timed out */</div><div class='del'>-</div><div class='del'>-	atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 1);</div><div class='del'>-	if (atmel_rmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_HOST_OFFSET))) {</div><div class='del'>-		atmel_wmem8(priv, atmel_hi(priv, IFACE_LOCKOUT_MAC_OFFSET), 0);</div><div class='del'>-		if (!j--)</div><div class='del'>-			return 0; /* timed out */</div><div class='del'>-		goto retry;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data)</div><div class='del'>-{</div><div class='del'>-	atmel_writeAR(priv-&gt;dev, pos);</div><div class='del'>-	atmel_write16(priv-&gt;dev, DR, data); /* card is little-endian */</div><div class='del'>-	atmel_write16(priv-&gt;dev, DR, data &gt;&gt; 16);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/***************************************************************************/</div><div class='del'>-/* There follows the source form of the MAC address reading firmware       */</div><div class='del'>-/***************************************************************************/</div><div class='del'>-#if 0</div><div class='del'>-</div><div class='del'>-/* Copyright 2003 Matthew T. Russotto                                      */</div><div class='del'>-/* But derived from the Atmel 76C502 firmware written by Atmel and         */</div><div class='del'>-/* included in "atmel wireless lan drivers" package                        */</div><div class='del'>-/*</div><div class='del'>-    This file is part of net.russotto.AtmelMACFW, hereto referred to</div><div class='del'>-    as AtmelMACFW</div><div class='del'>-</div><div class='del'>-    AtmelMACFW is free software; you can redistribute it and/or modify</div><div class='del'>-    it under the terms of the GNU General Public License version 2</div><div class='del'>-    as published by the Free Software Foundation.</div><div class='del'>-</div><div class='del'>-    AtmelMACFW is distributed in the hope that it will be useful,</div><div class='del'>-    but WITHOUT ANY WARRANTY; without even the implied warranty of</div><div class='del'>-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>-    GNU General Public License for more details.</div><div class='del'>-</div><div class='del'>-    You should have received a copy of the GNU General Public License</div><div class='del'>-    along with AtmelMACFW; if not, see &lt;http://www.gnu.org/licenses/&gt;.</div><div class='del'>-</div><div class='del'>-****************************************************************************/</div><div class='del'>-/* This firmware should work on the 76C502 RFMD, RFMD_D, and RFMD_E        */</div><div class='del'>-/* It will probably work on the 76C504 and 76C502 RFMD_3COM                */</div><div class='del'>-/* It only works on SPI EEPROM versions of the card.                       */</div><div class='del'>-</div><div class='del'>-/* This firmware initializes the SPI controller and clock, reads the MAC   */</div><div class='del'>-/* address from the EEPROM into SRAM, and puts the SRAM offset of the MAC  */</div><div class='del'>-/* address in MR2, and sets MR3 to 0x10 to indicate it is done             */</div><div class='del'>-/* It also puts a complete copy of the EEPROM in SRAM with the offset in   */</div><div class='del'>-/* MR4, for investigational purposes (maybe we can determine chip type     */</div><div class='del'>-/* from that?)                                                             */</div><div class='del'>-</div><div class='del'>-	.org 0</div><div class='del'>-    .set MRBASE, 0x8000000</div><div class='del'>-	.set CPSR_INITIAL, 0xD3 /* IRQ/FIQ disabled, ARM mode, Supervisor state */</div><div class='del'>-	.set CPSR_USER, 0xD1 /* IRQ/FIQ disabled, ARM mode, USER state */</div><div class='del'>-	.set SRAM_BASE,  0x02000000</div><div class='del'>-	.set SP_BASE,    0x0F300000</div><div class='del'>-	.set UNK_BASE,   0x0F000000 /* Some internal device, but which one? */</div><div class='del'>-	.set SPI_CGEN_BASE,  0x0E000000 /* Some internal device, but which one? */</div><div class='del'>-	.set UNK3_BASE,  0x02014000 /* Some internal device, but which one? */</div><div class='del'>-	.set STACK_BASE, 0x5600</div><div class='del'>-	.set SP_SR, 0x10</div><div class='del'>-	.set SP_TDRE, 2 /* status register bit -- TDR empty */</div><div class='del'>-	.set SP_RDRF, 1 /* status register bit -- RDR full */</div><div class='del'>-	.set SP_SWRST, 0x80</div><div class='del'>-	.set SP_SPIEN, 0x1</div><div class='del'>-	.set SP_CR, 0   /* control register */</div><div class='del'>-	.set SP_MR, 4   /* mode register */</div><div class='del'>-	.set SP_RDR, 0x08 /* Read Data Register */</div><div class='del'>-	.set SP_TDR, 0x0C /* Transmit Data Register */</div><div class='del'>-	.set SP_CSR0, 0x30 /* chip select registers */</div><div class='del'>-	.set SP_CSR1, 0x34</div><div class='del'>-	.set SP_CSR2, 0x38</div><div class='del'>-	.set SP_CSR3, 0x3C</div><div class='del'>-	.set NVRAM_CMD_RDSR, 5 /* read status register */</div><div class='del'>-	.set NVRAM_CMD_READ, 3 /* read data */</div><div class='del'>-	.set NVRAM_SR_RDY, 1 /* RDY bit.  This bit is inverted */</div><div class='del'>-	.set SPI_8CLOCKS, 0xFF /* Writing this to the TDR doesn't do anything to the</div><div class='del'>-				  serial output, since SO is normally high.  But it</div><div class='del'>-				  does cause 8 clock cycles and thus 8 bits to be</div><div class='del'>-				  clocked in to the chip.  See Atmel's SPI</div><div class='del'>-				  controller (e.g. AT91M55800) timing and 4K</div><div class='del'>-				  SPI EEPROM manuals */</div><div class='del'>-</div><div class='del'>-	.set NVRAM_SCRATCH, 0x02000100  /* arbitrary area for scratchpad memory */</div><div class='del'>-	.set NVRAM_IMAGE, 0x02000200</div><div class='del'>-	.set NVRAM_LENGTH, 0x0200</div><div class='del'>-	.set MAC_ADDRESS_MIB, SRAM_BASE</div><div class='del'>-	.set MAC_ADDRESS_LENGTH, 6</div><div class='del'>-	.set MAC_BOOT_FLAG, 0x10</div><div class='del'>-	.set MR1, 0</div><div class='del'>-	.set MR2, 4</div><div class='del'>-	.set MR3, 8</div><div class='del'>-	.set MR4, 0xC</div><div class='del'>-RESET_VECTOR:</div><div class='del'>-	b RESET_HANDLER</div><div class='del'>-UNDEF_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-SWI_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-IABORT_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-DABORT_VECTOR:</div><div class='del'>-RESERVED_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-IRQ_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-FIQ_VECTOR:</div><div class='del'>-	b HALT1</div><div class='del'>-HALT1:	b HALT1</div><div class='del'>-RESET_HANDLER:</div><div class='del'>-	mov     r0, #CPSR_INITIAL</div><div class='del'>-	msr	CPSR_c, r0	/* This is probably unnecessary */</div><div class='del'>-</div><div class='del'>-/* I'm guessing this is initializing clock generator electronics for SPI */</div><div class='del'>-	ldr	r0, =SPI_CGEN_BASE</div><div class='del'>-	mov	r1, #0</div><div class='del'>-	mov	r1, r1, lsl #3</div><div class='del'>-	orr	r1, r1, #0</div><div class='del'>-	str	r1, [r0]</div><div class='del'>-	ldr	r1, [r0, #28]</div><div class='del'>-	bic	r1, r1, #16</div><div class='del'>-	str	r1, [r0, #28]</div><div class='del'>-	mov	r1, #1</div><div class='del'>-	str	r1, [r0, #8]</div><div class='del'>-</div><div class='del'>-	ldr	r0, =MRBASE</div><div class='del'>-	mov	r1, #0</div><div class='del'>-	strh	r1, [r0, #MR1]</div><div class='del'>-	strh	r1, [r0, #MR2]</div><div class='del'>-	strh	r1, [r0, #MR3]</div><div class='del'>-	strh	r1, [r0, #MR4]</div><div class='del'>-</div><div class='del'>-	mov	sp, #STACK_BASE</div><div class='del'>-	bl	SP_INIT</div><div class='del'>-	mov	r0, #10</div><div class='del'>-	bl	DELAY9</div><div class='del'>-	bl	GET_MAC_ADDR</div><div class='del'>-	bl	GET_WHOLE_NVRAM</div><div class='del'>-	ldr	r0, =MRBASE</div><div class='del'>-	ldr	r1, =MAC_ADDRESS_MIB</div><div class='del'>-	strh	r1, [r0, #MR2]</div><div class='del'>-	ldr	r1, =NVRAM_IMAGE</div><div class='del'>-	strh	r1, [r0, #MR4]</div><div class='del'>-	mov	r1, #MAC_BOOT_FLAG</div><div class='del'>-	strh	r1, [r0, #MR3]</div><div class='del'>-HALT2:	b HALT2</div><div class='del'>-.func Get_Whole_NVRAM, GET_WHOLE_NVRAM</div><div class='del'>-GET_WHOLE_NVRAM:</div><div class='del'>-	stmdb	sp!, {lr}</div><div class='del'>-	mov	r2, #0 /* 0th bytes of NVRAM */</div><div class='del'>-	mov	r3, #NVRAM_LENGTH</div><div class='del'>-	mov	r1, #0		/* not used in routine */</div><div class='del'>-	ldr	r0, =NVRAM_IMAGE</div><div class='del'>-	bl	NVRAM_XFER</div><div class='del'>-	ldmia	sp!, {lr}</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-</div><div class='del'>-.func Get_MAC_Addr, GET_MAC_ADDR</div><div class='del'>-GET_MAC_ADDR:</div><div class='del'>-	stmdb	sp!, {lr}</div><div class='del'>-	mov	r2, #0x120	/* address of MAC Address within NVRAM */</div><div class='del'>-	mov	r3, #MAC_ADDRESS_LENGTH</div><div class='del'>-	mov	r1, #0		/* not used in routine */</div><div class='del'>-	ldr	r0, =MAC_ADDRESS_MIB</div><div class='del'>-	bl	NVRAM_XFER</div><div class='del'>-	ldmia	sp!, {lr}</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-.ltorg</div><div class='del'>-.func Delay9, DELAY9</div><div class='del'>-DELAY9:</div><div class='del'>-	adds	r0, r0, r0, LSL #3   /* r0 = r0 * 9 */</div><div class='del'>-DELAYLOOP:</div><div class='del'>-	beq	DELAY9_done</div><div class='del'>-	subs	r0, r0, #1</div><div class='del'>-	b	DELAYLOOP</div><div class='del'>-DELAY9_done:</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-</div><div class='del'>-.func SP_Init, SP_INIT</div><div class='del'>-SP_INIT:</div><div class='del'>-	mov	r1, #SP_SWRST</div><div class='del'>-	ldr	r0, =SP_BASE</div><div class='del'>-	str	r1, [r0, #SP_CR] /* reset the SPI */</div><div class='del'>-	mov	r1, #0</div><div class='del'>-	str	r1, [r0, #SP_CR] /* release SPI from reset state */</div><div class='del'>-	mov	r1, #SP_SPIEN</div><div class='del'>-	str	r1, [r0, #SP_MR] /* set the SPI to MASTER mode*/</div><div class='del'>-	str	r1, [r0, #SP_CR] /* enable the SPI */</div><div class='del'>-</div><div class='del'>-/*  My guess would be this turns on the SPI clock */</div><div class='del'>-	ldr	r3, =SPI_CGEN_BASE</div><div class='del'>-	ldr	r1, [r3, #28]</div><div class='del'>-	orr	r1, r1, #0x2000</div><div class='del'>-	str	r1, [r3, #28]</div><div class='del'>-</div><div class='del'>-	ldr	r1, =0x2000c01</div><div class='del'>-	str	r1, [r0, #SP_CSR0]</div><div class='del'>-	ldr	r1, =0x2000201</div><div class='del'>-	str	r1, [r0, #SP_CSR1]</div><div class='del'>-	str	r1, [r0, #SP_CSR2]</div><div class='del'>-	str	r1, [r0, #SP_CSR3]</div><div class='del'>-	ldr	r1, [r0, #SP_SR]</div><div class='del'>-	ldr	r0, [r0, #SP_RDR]</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-.func NVRAM_Init, NVRAM_INIT</div><div class='del'>-NVRAM_INIT:</div><div class='del'>-	ldr	r1, =SP_BASE</div><div class='del'>-	ldr	r0, [r1, #SP_RDR]</div><div class='del'>-	mov	r0, #NVRAM_CMD_RDSR</div><div class='del'>-	str	r0, [r1, #SP_TDR]</div><div class='del'>-SP_loop1:</div><div class='del'>-	ldr	r0, [r1, #SP_SR]</div><div class='del'>-	tst	r0, #SP_TDRE</div><div class='del'>-	beq	SP_loop1</div><div class='del'>-</div><div class='del'>-	mov	r0, #SPI_8CLOCKS</div><div class='del'>-	str	r0, [r1, #SP_TDR]</div><div class='del'>-SP_loop2:</div><div class='del'>-	ldr	r0, [r1, #SP_SR]</div><div class='del'>-	tst	r0, #SP_TDRE</div><div class='del'>-	beq	SP_loop2</div><div class='del'>-</div><div class='del'>-	ldr	r0, [r1, #SP_RDR]</div><div class='del'>-SP_loop3:</div><div class='del'>-	ldr	r0, [r1, #SP_SR]</div><div class='del'>-	tst	r0, #SP_RDRF</div><div class='del'>-	beq	SP_loop3</div><div class='del'>-</div><div class='del'>-	ldr	r0, [r1, #SP_RDR]</div><div class='del'>-	and	r0, r0, #255</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-</div><div class='del'>-.func NVRAM_Xfer, NVRAM_XFER</div><div class='del'>-	/* r0 = dest address */</div><div class='del'>-	/* r1 = not used */</div><div class='del'>-	/* r2 = src address within NVRAM */</div><div class='del'>-	/* r3 = length */</div><div class='del'>-NVRAM_XFER:</div><div class='del'>-	stmdb	sp!, {r4, r5, lr}</div><div class='del'>-	mov	r5, r0		/* save r0 (dest address) */</div><div class='del'>-	mov	r4, r3		/* save r3 (length) */</div><div class='del'>-	mov	r0, r2, LSR #5 /*  SPI memories put A8 in the command field */</div><div class='del'>-	and	r0, r0, #8</div><div class='del'>-	add	r0, r0, #NVRAM_CMD_READ</div><div class='del'>-	ldr	r1, =NVRAM_SCRATCH</div><div class='del'>-	strb	r0, [r1, #0]	/* save command in NVRAM_SCRATCH[0] */</div><div class='del'>-	strb	r2, [r1, #1]    /* save low byte of source address in NVRAM_SCRATCH[1] */</div><div class='del'>-_local1:</div><div class='del'>-	bl	NVRAM_INIT</div><div class='del'>-	tst	r0, #NVRAM_SR_RDY</div><div class='del'>-	bne	_local1</div><div class='del'>-	mov	r0, #20</div><div class='del'>-	bl	DELAY9</div><div class='del'>-	mov	r2, r4		/* length */</div><div class='del'>-	mov	r1, r5		/* dest address */</div><div class='del'>-	mov	r0, #2		/* bytes to transfer in command */</div><div class='del'>-	bl	NVRAM_XFER2</div><div class='del'>-	ldmia	sp!, {r4, r5, lr}</div><div class='del'>-	bx	lr</div><div class='del'>-.endfunc</div><div class='del'>-</div><div class='del'>-.func NVRAM_Xfer2, NVRAM_XFER2</div><div class='del'>-NVRAM_XFER2:</div><div class='del'>-	stmdb	sp!, {r4, r5, r6, lr}</div><div class='del'>-	ldr	r4, =SP_BASE</div><div class='del'>-	mov	r3, #0</div><div class='del'>-	cmp	r0, #0</div><div class='del'>-	bls	_local2</div><div class='del'>-	ldr	r5, =NVRAM_SCRATCH</div><div class='del'>-_local4:</div><div class='del'>-	ldrb	r6, [r5, r3]</div><div class='del'>-	str	r6, [r4, #SP_TDR]</div><div class='del'>-_local3:</div><div class='del'>-	ldr	r6, [r4, #SP_SR]</div><div class='del'>-	tst	r6, #SP_TDRE</div><div class='del'>-	beq	_local3</div><div class='del'>-	add	r3, r3, #1</div><div class='del'>-	cmp	r3, r0 /* r0 is # of bytes to send out (command+addr) */</div><div class='del'>-	blo	_local4</div><div class='del'>-_local2:</div><div class='del'>-	mov	r3, #SPI_8CLOCKS</div><div class='del'>-	str	r3, [r4, #SP_TDR]</div><div class='del'>-	ldr	r0, [r4, #SP_RDR]</div><div class='del'>-_local5:</div><div class='del'>-	ldr	r0, [r4, #SP_SR]</div><div class='del'>-	tst	r0, #SP_RDRF</div><div class='del'>-	beq	_local5</div><div class='del'>-	ldr	r0, [r4, #SP_RDR] /* what's this byte?  It's the byte read while writing the TDR -- nonsense, because the NVRAM doesn't read and write at the same time */</div><div class='del'>-	mov	r0, #0</div><div class='del'>-	cmp	r2, #0  /* r2 is # of bytes to copy in */</div><div class='del'>-	bls	_local6</div><div class='del'>-_local7:</div><div class='del'>-	ldr	r5, [r4, #SP_SR]</div><div class='del'>-	tst	r5, #SP_TDRE</div><div class='del'>-	beq	_local7</div><div class='del'>-	str	r3, [r4, #SP_TDR]  /* r3 has SPI_8CLOCKS */</div><div class='del'>-_local8:</div><div class='del'>-	ldr	r5, [r4, #SP_SR]</div><div class='del'>-	tst	r5, #SP_RDRF</div><div class='del'>-	beq	_local8</div><div class='del'>-	ldr	r5, [r4, #SP_RDR] /* but didn't we read this byte above? */</div><div class='del'>-	strb	r5, [r1], #1 /* postindexed */</div><div class='del'>-	add	r0, r0, #1</div><div class='del'>-	cmp	r0, r2</div><div class='del'>-	blo	_local7 /* since we don't send another address, the NVRAM must be capable of sequential reads */</div><div class='del'>-_local6:</div><div class='del'>-	mov	r0, #200</div><div class='del'>-	bl	DELAY9</div><div class='del'>-	ldmia	sp!, {r4, r5, r6, lr}</div><div class='del'>-	bx	lr</div><div class='del'>-#endif</div><div class='head'>diff --git a/drivers/net/wireless/atmel/atmel.h b/drivers/net/wireless/atmel/atmel.h<br/>deleted file mode 100644<br/>index d2aa52cf6e8b..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/atmel.h?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/atmel.h</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,31 +0,0 @@</div><div class='del'>-/* SPDX-License-Identifier: GPL-2.0-or-later */</div><div class='del'>-/*** -*- linux-c -*- **********************************************************</div><div class='del'>-</div><div class='del'>-     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.</div><div class='del'>-</div><div class='del'>-         Copyright 2005 Dan Williams and Red Hat, Inc.</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-******************************************************************************/</div><div class='del'>-</div><div class='del'>-#ifndef _ATMEL_H</div><div class='del'>-#define _ATMEL_H</div><div class='del'>-</div><div class='del'>-typedef enum {</div><div class='del'>-	ATMEL_FW_TYPE_NONE = 0,</div><div class='del'>-	ATMEL_FW_TYPE_502,</div><div class='del'>-	ATMEL_FW_TYPE_502D,</div><div class='del'>-	ATMEL_FW_TYPE_502E,</div><div class='del'>-	ATMEL_FW_TYPE_502_3COM,</div><div class='del'>-	ATMEL_FW_TYPE_504,</div><div class='del'>-	ATMEL_FW_TYPE_504_2958,</div><div class='del'>-	ATMEL_FW_TYPE_504A_2958,</div><div class='del'>-	ATMEL_FW_TYPE_506</div><div class='del'>-} AtmelFWType;</div><div class='del'>-</div><div class='del'>-struct net_device *init_atmel_card(unsigned short, unsigned long, const AtmelFWType, struct device *, </div><div class='del'>-				    int (*present_func)(void *), void * );</div><div class='del'>-void stop_atmel_card( struct net_device *);</div><div class='del'>-int atmel_open( struct net_device * );</div><div class='del'>-</div><div class='del'>-#endif</div><div class='head'>diff --git a/drivers/net/wireless/atmel/atmel_cs.c b/drivers/net/wireless/atmel/atmel_cs.c<br/>deleted file mode 100644<br/>index 58bba9875d36..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/atmel_cs.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/atmel_cs.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,292 +0,0 @@</div><div class='del'>-/*** -*- linux-c -*- **********************************************************</div><div class='del'>-</div><div class='del'>-     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.</div><div class='del'>-</div><div class='del'>-        Copyright 2000-2001 ATMEL Corporation.</div><div class='del'>-        Copyright 2003 Simon Kelley.</div><div class='del'>-</div><div class='del'>-    This code was developed from version 2.1.1 of the Atmel drivers,</div><div class='del'>-    released by Atmel corp. under the GPL in December 2002. It also</div><div class='del'>-    includes code from the Linux aironet drivers (C) Benjamin Reed,</div><div class='del'>-    and the Linux PCMCIA package, (C) David Hinds.</div><div class='del'>-</div><div class='del'>-    For all queries about this code, please contact the current author,</div><div class='del'>-    Simon Kelley &lt;simon@thekelleys.org.uk&gt; and not Atmel Corporation.</div><div class='del'>-</div><div class='del'>-    This program is free software; you can redistribute it and/or modify</div><div class='del'>-    it under the terms of the GNU General Public License as published by</div><div class='del'>-    the Free Software Foundation; either version 2 of the License, or</div><div class='del'>-    (at your option) any later version.</div><div class='del'>-</div><div class='del'>-    This software is distributed in the hope that it will be useful,</div><div class='del'>-    but WITHOUT ANY WARRANTY; without even the implied warranty of</div><div class='del'>-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>-    GNU General Public License for more details.</div><div class='del'>-</div><div class='del'>-    You should have received a copy of the GNU General Public License</div><div class='del'>-    along with Atmel wireless lan drivers; if not, see</div><div class='del'>-    &lt;http://www.gnu.org/licenses/&gt;.</div><div class='del'>-</div><div class='del'>-******************************************************************************/</div><div class='del'>-</div><div class='del'>-#ifdef __IN_PCMCIA_PACKAGE__</div><div class='del'>-#include &lt;pcmcia/k_compat.h&gt;</div><div class='del'>-#endif</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/ptrace.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/string.h&gt;</div><div class='del'>-#include &lt;linux/netdevice.h&gt;</div><div class='del'>-#include &lt;linux/moduleparam.h&gt;</div><div class='del'>-#include &lt;linux/device.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;pcmcia/cistpl.h&gt;</div><div class='del'>-#include &lt;pcmcia/cisreg.h&gt;</div><div class='del'>-#include &lt;pcmcia/ds.h&gt;</div><div class='del'>-#include &lt;pcmcia/ciscode.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;asm/io.h&gt;</div><div class='del'>-#include &lt;linux/wireless.h&gt;</div><div class='del'>-</div><div class='del'>-#include "atmel.h"</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/*====================================================================*/</div><div class='del'>-</div><div class='del'>-MODULE_AUTHOR("Simon Kelley");</div><div class='del'>-MODULE_DESCRIPTION("Support for Atmel at76c50x 802.11 wireless ethernet cards.");</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-</div><div class='del'>-/*====================================================================*/</div><div class='del'>-</div><div class='del'>-static int atmel_config(struct pcmcia_device *link);</div><div class='del'>-static void atmel_release(struct pcmcia_device *link);</div><div class='del'>-</div><div class='del'>-static void atmel_detach(struct pcmcia_device *p_dev);</div><div class='del'>-</div><div class='del'>-struct local_info {</div><div class='del'>-	struct net_device *eth_dev;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int atmel_probe(struct pcmcia_device *p_dev)</div><div class='del'>-{</div><div class='del'>-	struct local_info *local;</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;p_dev-&gt;dev, "atmel_attach()\n");</div><div class='del'>-</div><div class='del'>-	/* Allocate space for private device-specific data */</div><div class='del'>-	local = kzalloc(sizeof(*local), GFP_KERNEL);</div><div class='del'>-	if (!local)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-</div><div class='del'>-	p_dev-&gt;priv = local;</div><div class='del'>-</div><div class='del'>-	ret = atmel_config(p_dev);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto err_free_priv;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-err_free_priv:</div><div class='del'>-	kfree(p_dev-&gt;priv);</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_detach(struct pcmcia_device *link)</div><div class='del'>-{</div><div class='del'>-	dev_dbg(&amp;link-&gt;dev, "atmel_detach\n");</div><div class='del'>-</div><div class='del'>-	atmel_release(link);</div><div class='del'>-</div><div class='del'>-	kfree(link-&gt;priv);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Call-back function to interrogate PCMCIA-specific information</div><div class='del'>-   about the current existence of the card */</div><div class='del'>-static int card_present(void *arg)</div><div class='del'>-{</div><div class='del'>-	struct pcmcia_device *link = (struct pcmcia_device *)arg;</div><div class='del'>-</div><div class='del'>-	if (pcmcia_dev_present(link))</div><div class='del'>-		return 1;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_config_check(struct pcmcia_device *p_dev, void *priv_data)</div><div class='del'>-{</div><div class='del'>-	if (p_dev-&gt;config_index == 0)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return pcmcia_request_io(p_dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_config(struct pcmcia_device *link)</div><div class='del'>-{</div><div class='del'>-	int ret;</div><div class='del'>-	const struct pcmcia_device_id *did;</div><div class='del'>-</div><div class='del'>-	did = dev_get_drvdata(&amp;link-&gt;dev);</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;link-&gt;dev, "atmel_config\n");</div><div class='del'>-</div><div class='del'>-	link-&gt;config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_VPP |</div><div class='del'>-		CONF_AUTO_AUDIO | CONF_AUTO_SET_IO;</div><div class='del'>-</div><div class='del'>-	if (pcmcia_loop_config(link, atmel_config_check, NULL))</div><div class='del'>-		goto failed;</div><div class='del'>-</div><div class='del'>-	if (!link-&gt;irq) {</div><div class='del'>-		dev_err(&amp;link-&gt;dev, "atmel: cannot assign IRQ: check that CONFIG_ISA is set in kernel config.");</div><div class='del'>-		goto failed;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ret = pcmcia_enable_device(link);</div><div class='del'>-	if (ret)</div><div class='del'>-		goto failed;</div><div class='del'>-</div><div class='del'>-	((struct local_info *)link-&gt;priv)-&gt;eth_dev =</div><div class='del'>-		init_atmel_card(link-&gt;irq,</div><div class='del'>-				link-&gt;resource[0]-&gt;start,</div><div class='del'>-				did ? did-&gt;driver_info : ATMEL_FW_TYPE_NONE,</div><div class='del'>-				&amp;link-&gt;dev,</div><div class='del'>-				card_present,</div><div class='del'>-				link);</div><div class='del'>-	if (!((struct local_info *)link-&gt;priv)-&gt;eth_dev)</div><div class='del'>-			goto failed;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>- failed:</div><div class='del'>-	atmel_release(link);</div><div class='del'>-	return -ENODEV;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_release(struct pcmcia_device *link)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev = ((struct local_info *)link-&gt;priv)-&gt;eth_dev;</div><div class='del'>-</div><div class='del'>-	dev_dbg(&amp;link-&gt;dev, "atmel_release\n");</div><div class='del'>-</div><div class='del'>-	if (dev)</div><div class='del'>-		stop_atmel_card(dev);</div><div class='del'>-	((struct local_info *)link-&gt;priv)-&gt;eth_dev = NULL;</div><div class='del'>-</div><div class='del'>-	pcmcia_disable_device(link);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_suspend(struct pcmcia_device *link)</div><div class='del'>-{</div><div class='del'>-	struct local_info *local = link-&gt;priv;</div><div class='del'>-</div><div class='del'>-	netif_device_detach(local-&gt;eth_dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int atmel_resume(struct pcmcia_device *link)</div><div class='del'>-{</div><div class='del'>-	struct local_info *local = link-&gt;priv;</div><div class='del'>-</div><div class='del'>-	atmel_open(local-&gt;eth_dev);</div><div class='del'>-	netif_device_attach(local-&gt;eth_dev);</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*====================================================================*/</div><div class='del'>-/* We use the driver_info field to store the correct firmware type for a card. */</div><div class='del'>-</div><div class='del'>-#define PCMCIA_DEVICE_MANF_CARD_INFO(manf, card, info) { \</div><div class='del'>-	.match_flags = PCMCIA_DEV_ID_MATCH_MANF_ID| \</div><div class='del'>-			PCMCIA_DEV_ID_MATCH_CARD_ID, \</div><div class='del'>-	.manf_id = (manf), \</div><div class='del'>-	.card_id = (card), \</div><div class='del'>-        .driver_info = (kernel_ulong_t)(info), }</div><div class='del'>-</div><div class='del'>-#define PCMCIA_DEVICE_PROD_ID12_INFO(v1, v2, vh1, vh2, info) { \</div><div class='del'>-	.match_flags = PCMCIA_DEV_ID_MATCH_PROD_ID1| \</div><div class='del'>-			PCMCIA_DEV_ID_MATCH_PROD_ID2, \</div><div class='del'>-	.prod_id = { (v1), (v2), NULL, NULL }, \</div><div class='del'>-	.prod_id_hash = { (vh1), (vh2), 0, 0 }, \</div><div class='del'>-        .driver_info = (kernel_ulong_t)(info), }</div><div class='del'>-</div><div class='del'>-static const struct pcmcia_device_id atmel_ids[] = {</div><div class='del'>-	PCMCIA_DEVICE_MANF_CARD_INFO(0x0101, 0x0620, ATMEL_FW_TYPE_502_3COM),</div><div class='del'>-	PCMCIA_DEVICE_MANF_CARD_INFO(0x0101, 0x0696, ATMEL_FW_TYPE_502_3COM),</div><div class='del'>-	PCMCIA_DEVICE_MANF_CARD_INFO(0x01bf, 0x3302, ATMEL_FW_TYPE_502E),</div><div class='del'>-	PCMCIA_DEVICE_MANF_CARD_INFO(0xd601, 0x0007, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("11WAVE", "11WP611AL-E", 0x9eb2da1f, 0xc9a0d3f9, ATMEL_FW_TYPE_502E),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C502AR", 0xabda4164, 0x41b37e1f, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C502AR_D", 0xabda4164, 0x3675d704, ATMEL_FW_TYPE_502D),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C502AR_E", 0xabda4164, 0x4172e792, ATMEL_FW_TYPE_502E),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C504_R", 0xabda4164, 0x917f3d72, ATMEL_FW_TYPE_504_2958),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C504", 0xabda4164, 0x5040670a, ATMEL_FW_TYPE_504),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("ATMEL", "AT76C504A", 0xabda4164, 0xe15ed87f, ATMEL_FW_TYPE_504A_2958),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("BT", "Voyager 1020 Laptop Adapter", 0xae49b86a, 0x1e957cd5, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("CNet", "CNWLC 11Mbps Wireless PC Card V-5", 0xbc477dde, 0x502fae6b, ATMEL_FW_TYPE_502E),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("IEEE 802.11b", "Wireless LAN PC Card", 0x5b878724, 0x122f1df6, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("IEEE 802.11b", "Wireless LAN Card S", 0x5b878724, 0x5fba533a, ATMEL_FW_TYPE_504_2958),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("OEM", "11Mbps Wireless LAN PC Card V-3", 0xfea54c90, 0x1c5b0f68, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("SMC", "2632W", 0xc4f8b18b, 0x30f38774, ATMEL_FW_TYPE_502D),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("SMC", "2632W-V2", 0xc4f8b18b, 0x172d1377, ATMEL_FW_TYPE_502),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("Wireless", "PC_CARD", 0xa407ecdd, 0x119f6314, ATMEL_FW_TYPE_502D),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("WLAN", "802.11b PC CARD", 0x575c516c, 0xb1f6dbc4, ATMEL_FW_TYPE_502D),</div><div class='del'>-	PCMCIA_DEVICE_PROD_ID12_INFO("LG", "LW2100N", 0xb474d43a, 0x6b1fec94, ATMEL_FW_TYPE_502E),</div><div class='del'>-	PCMCIA_DEVICE_NULL</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-MODULE_DEVICE_TABLE(pcmcia, atmel_ids);</div><div class='del'>-</div><div class='del'>-static struct pcmcia_driver atmel_driver = {</div><div class='del'>-	.owner		= THIS_MODULE,</div><div class='del'>-	.name		= "atmel_cs",</div><div class='del'>-	.probe          = atmel_probe,</div><div class='del'>-	.remove		= atmel_detach,</div><div class='del'>-	.id_table	= atmel_ids,</div><div class='del'>-	.suspend	= atmel_suspend,</div><div class='del'>-	.resume		= atmel_resume,</div><div class='del'>-};</div><div class='del'>-module_pcmcia_driver(atmel_driver);</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>-    This program is free software; you can redistribute it and/or</div><div class='del'>-    modify it under the terms of the GNU General Public License</div><div class='del'>-    as published by the Free Software Foundation; either version 2</div><div class='del'>-    of the License, or (at your option) any later version.</div><div class='del'>-</div><div class='del'>-    This program is distributed in the hope that it will be useful,</div><div class='del'>-    but WITHOUT ANY WARRANTY; without even the implied warranty of</div><div class='del'>-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the</div><div class='del'>-    GNU General Public License for more details.</div><div class='del'>-</div><div class='del'>-    In addition:</div><div class='del'>-</div><div class='del'>-    Redistribution and use in source and binary forms, with or without</div><div class='del'>-    modification, are permitted provided that the following conditions</div><div class='del'>-    are met:</div><div class='del'>-</div><div class='del'>-    1. Redistributions of source code must retain the above copyright</div><div class='del'>-       notice, this list of conditions and the following disclaimer.</div><div class='del'>-    2. Redistributions in binary form must reproduce the above copyright</div><div class='del'>-       notice, this list of conditions and the following disclaimer in the</div><div class='del'>-       documentation and/or other materials provided with the distribution.</div><div class='del'>-    3. The name of the author may not be used to endorse or promote</div><div class='del'>-       products derived from this software without specific prior written</div><div class='del'>-       permission.</div><div class='del'>-</div><div class='del'>-    THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR</div><div class='del'>-    IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED</div><div class='del'>-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</div><div class='del'>-    ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,</div><div class='del'>-    INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</div><div class='del'>-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</div><div class='del'>-    SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)</div><div class='del'>-    HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,</div><div class='del'>-    STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING</div><div class='del'>-    IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE</div><div class='del'>-    POSSIBILITY OF SUCH DAMAGE.</div><div class='del'>-*/</div><div class='head'>diff --git a/drivers/net/wireless/atmel/atmel_pci.c b/drivers/net/wireless/atmel/atmel_pci.c<br/>deleted file mode 100644<br/>index f428dc79d916..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/atmel/atmel_pci.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/atmel/atmel_pci.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,65 +0,0 @@</div><div class='del'>-// SPDX-License-Identifier: GPL-2.0-or-later</div><div class='del'>-/*** -*- linux-c -*- **********************************************************</div><div class='del'>-</div><div class='del'>-     Driver for Atmel at76c502 at76c504 and at76c506 wireless cards.</div><div class='del'>-</div><div class='del'>-         Copyright 2004 Simon Kelley.</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-******************************************************************************/</div><div class='del'>-#include &lt;linux/pci.h&gt;</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/netdevice.h&gt;</div><div class='del'>-#include "atmel.h"</div><div class='del'>-</div><div class='del'>-MODULE_AUTHOR("Simon Kelley");</div><div class='del'>-MODULE_DESCRIPTION("Support for Atmel at76c50x 802.11 wireless ethernet cards.");</div><div class='del'>-MODULE_LICENSE("GPL");</div><div class='del'>-</div><div class='del'>-static const struct pci_device_id card_ids[] = {</div><div class='del'>-	{ 0x1114, 0x0506, PCI_ANY_ID, PCI_ANY_ID },</div><div class='del'>-	{ 0, }</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-MODULE_DEVICE_TABLE(pci, card_ids);</div><div class='del'>-</div><div class='del'>-static int atmel_pci_probe(struct pci_dev *, const struct pci_device_id *);</div><div class='del'>-static void atmel_pci_remove(struct pci_dev *);</div><div class='del'>-</div><div class='del'>-static struct pci_driver atmel_driver = {</div><div class='del'>-	.name     = "atmel",</div><div class='del'>-	.id_table = card_ids,</div><div class='del'>-	.probe    = atmel_pci_probe,</div><div class='del'>-	.remove   = atmel_pci_remove,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static int atmel_pci_probe(struct pci_dev *pdev,</div><div class='del'>-				     const struct pci_device_id *pent)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev;</div><div class='del'>-</div><div class='del'>-	if (pci_enable_device(pdev))</div><div class='del'>-		return -ENODEV;</div><div class='del'>-</div><div class='del'>-	pci_set_master(pdev);</div><div class='del'>-</div><div class='del'>-	dev = init_atmel_card(pdev-&gt;irq, pdev-&gt;resource[1].start,</div><div class='del'>-			      ATMEL_FW_TYPE_506,</div><div class='del'>-			      &amp;pdev-&gt;dev, NULL, NULL);</div><div class='del'>-	if (!dev) {</div><div class='del'>-		pci_disable_device(pdev);</div><div class='del'>-		return -ENODEV;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	pci_set_drvdata(pdev, dev);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void atmel_pci_remove(struct pci_dev *pdev)</div><div class='del'>-{</div><div class='del'>-	stop_atmel_card(pci_get_drvdata(pdev));</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-module_pci_driver(atmel_driver);</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c<br/>index 667462369a32..133c5ea6429c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c</a></div><div class='hunk'>@@ -866,7 +866,7 @@ struct wireless_dev *brcmf_apsta_add_vif(struct wiphy *wiphy, const char *name,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	strncpy(ifp-&gt;ndev-&gt;name, name, sizeof(ifp-&gt;ndev-&gt;name) - 1);</div><div class='add'>+	strscpy(ifp-&gt;ndev-&gt;name, name, sizeof(ifp-&gt;ndev-&gt;name));</div><div class='ctx'> 	err = brcmf_net_attach(ifp, true);</div><div class='ctx'> 	if (err) {</div><div class='ctx'> 		bphy_err(drvr, "Registering netdevice failed\n");</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c<br/>index a194b0e68eb5..b6d458e022fa 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c</a></div><div class='hunk'>@@ -578,18 +578,16 @@ static int __init brcmf_common_pd_probe(struct platform_device *pdev)</div><div class='ctx'> 	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='del'>-static int brcmf_common_pd_remove(struct platform_device *pdev)</div><div class='add'>+static void brcmf_common_pd_remove(struct platform_device *pdev)</div><div class='ctx'> {</div><div class='ctx'> 	brcmf_dbg(INFO, "Enter\n");</div><div class='ctx'> </div><div class='ctx'> 	if (brcmfmac_pdata-&gt;power_off)</div><div class='ctx'> 		brcmfmac_pdata-&gt;power_off();</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='ctx'> }</div><div class='ctx'> </div><div class='ctx'> static struct platform_driver brcmf_pd = {</div><div class='del'>-	.remove		= brcmf_common_pd_remove,</div><div class='add'>+	.remove_new	= brcmf_common_pd_remove,</div><div class='ctx'> 	.driver		= {</div><div class='ctx'> 		.name	= BRCMFMAC_PDATA_NAME,</div><div class='ctx'> 	}</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c<br/>index d4492d02e4ea..6e0c90f4718b 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c</a></div><div class='hunk'>@@ -2334,7 +2334,7 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,</div><div class='ctx'> 		goto fail;</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='del'>-	strncpy(ifp-&gt;ndev-&gt;name, name, sizeof(ifp-&gt;ndev-&gt;name) - 1);</div><div class='add'>+	strscpy(ifp-&gt;ndev-&gt;name, name, sizeof(ifp-&gt;ndev-&gt;name));</div><div class='ctx'> 	ifp-&gt;ndev-&gt;name_assign_type = name_assign_type;</div><div class='ctx'> 	err = brcmf_net_attach(ifp, true);</div><div class='ctx'> 	if (err) {</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c<br/>index 80220685f5e4..d7fb88bb6ae1 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c</a></div><div class='hunk'>@@ -2707,7 +2707,6 @@ MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);</div><div class='ctx'> </div><div class='ctx'> </div><div class='ctx'> static struct pci_driver brcmf_pciedrvr = {</div><div class='del'>-	.node = {},</div><div class='ctx'> 	.name = KBUILD_MODNAME,</div><div class='ctx'> 	.id_table = brcmf_pcie_devid_table,</div><div class='ctx'> 	.probe = brcmf_pcie_probe,</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c<br/>index 2178675ae1a4..0ccf735316c2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmfmac/usb.c</a></div><div class='hunk'>@@ -1581,7 +1581,7 @@ static int brcmf_usb_reset_device(struct device *dev, void *notused)</div><div class='ctx'> </div><div class='ctx'> void brcmf_usb_exit(void)</div><div class='ctx'> {</div><div class='del'>-	struct device_driver *drv = &amp;brcmf_usbdrvr.drvwrap.driver;</div><div class='add'>+	struct device_driver *drv = &amp;brcmf_usbdrvr.driver;</div><div class='ctx'> 	int ret;</div><div class='ctx'> </div><div class='ctx'> 	brcmf_dbg(USB, "Enter\n");</div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c<br/>index 5a6d9c86552a..f6962e558d7c 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c</a></div><div class='hunk'>@@ -341,7 +341,7 @@ struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)</div><div class='ctx'> 	/* store the country code for passing up as a regulatory hint */</div><div class='ctx'> 	wlc_cm-&gt;world_regd = brcms_world_regd(ccode, ccode_len);</div><div class='ctx'> 	if (brcms_c_country_valid(ccode))</div><div class='del'>-		strncpy(wlc-&gt;pub-&gt;srom_ccode, ccode, ccode_len);</div><div class='add'>+		memcpy(wlc-&gt;pub-&gt;srom_ccode, ccode, ccode_len);</div><div class='ctx'> </div><div class='ctx'> 	/*</div><div class='ctx'> 	 * If no custom world domain is found in the SROM, use the</div><div class='hunk'>@@ -354,10 +354,10 @@ struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)</div><div class='ctx'> 	}</div><div class='ctx'> </div><div class='ctx'> 	/* save default country for exiting 11d regulatory mode */</div><div class='del'>-	strncpy(wlc-&gt;country_default, ccode, ccode_len);</div><div class='add'>+	memcpy(wlc-&gt;country_default, ccode, ccode_len);</div><div class='ctx'> </div><div class='ctx'> 	/* initialize autocountry_default to driver default */</div><div class='del'>-	strncpy(wlc-&gt;autocountry_default, ccode, ccode_len);</div><div class='add'>+	memcpy(wlc-&gt;autocountry_default, ccode, ccode_len);</div><div class='ctx'> </div><div class='ctx'> 	brcms_c_set_country(wlc_cm, wlc_cm-&gt;world_regd);</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c<br/>index b7df576bb84d..3d5c1ef8f7f2 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c</a></div><div class='hunk'>@@ -584,8 +584,7 @@ struct dma_pub *dma_attach(char *name, struct brcms_c_info *wlc,</div><div class='ctx'> 		      rxextheadroom, nrxpost, rxoffset, txregbase, rxregbase);</div><div class='ctx'> </div><div class='ctx'> 	/* make a private copy of our callers name */</div><div class='del'>-	strncpy(di-&gt;name, name, MAXNAMEL);</div><div class='del'>-	di-&gt;name[MAXNAMEL - 1] = '\0';</div><div class='add'>+	strscpy(di-&gt;name, name, sizeof(di-&gt;name));</div><div class='ctx'> </div><div class='ctx'> 	di-&gt;dmadev = core-&gt;dma_dev;</div><div class='ctx'> </div><div class='head'>diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c<br/>index b3663c5ef382..34460b5815d0 100644<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c</a><br/>+++ b/<a href='/cgit/linux.git/tree/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c?id=4db102dcb0396a4ccf89b1eac0f4eb3fd167a080'>drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c</a></div><div class='hunk'>@@ -5551,8 +5551,8 @@ int brcms_c_module_register(struct brcms_pub *pub,</div><div class='ctx'> 	/* find an empty entry and just add, no duplication check! */</div><div class='ctx'> 	for (i = 0; i &lt; BRCMS_MAXMODULES; i++) {</div><div class='ctx'> 		if (wlc-&gt;modulecb[i].name[0] == '\0') {</div><div class='del'>-			strncpy(wlc-&gt;modulecb[i].name, name,</div><div class='del'>-				sizeof(wlc-&gt;modulecb[i].name) - 1);</div><div class='add'>+			strscpy(wlc-&gt;modulecb[i].name, name,</div><div class='add'>+				sizeof(wlc-&gt;modulecb[i].name));</div><div class='ctx'> 			wlc-&gt;modulecb[i].hdl = hdl;</div><div class='ctx'> 			wlc-&gt;modulecb[i].down_fn = d_fn;</div><div class='ctx'> 			return 0;</div><div class='head'>diff --git a/drivers/net/wireless/cisco/Kconfig b/drivers/net/wireless/cisco/Kconfig<br/>deleted file mode 100644<br/>index b40ee25aca99..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/cisco/Kconfig?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/cisco/Kconfig</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,59 +0,0 @@</div><div class='del'>-# SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-config WLAN_VENDOR_CISCO</div><div class='del'>-	bool "Cisco devices"</div><div class='del'>-	default y</div><div class='del'>-	help</div><div class='del'>-	  If you have a wireless card belonging to this class, say Y.</div><div class='del'>-</div><div class='del'>-	  Note that the answer to this question doesn't directly affect the</div><div class='del'>-	  kernel: saying N will just cause the configurator to skip all the</div><div class='del'>-	  questions about these cards. If you say Y, you will be asked for</div><div class='del'>-	  your specific card in the following questions.</div><div class='del'>-</div><div class='del'>-if WLAN_VENDOR_CISCO</div><div class='del'>-</div><div class='del'>-config AIRO</div><div class='del'>-	tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards"</div><div class='del'>-	depends on CFG80211 &amp;&amp; (PCI || BROKEN)</div><div class='del'>-	select WIRELESS_EXT</div><div class='del'>-	select CRYPTO</div><div class='del'>-	select CRYPTO_SKCIPHER</div><div class='del'>-	select WEXT_SPY</div><div class='del'>-	select WEXT_PRIV</div><div class='del'>-	help</div><div class='del'>-	  This is the standard Linux driver to support Cisco/Aironet ISA and</div><div class='del'>-	  PCI 802.11 wireless cards.</div><div class='del'>-	  It supports the new 802.11b cards from Cisco (Cisco 34X, Cisco 35X</div><div class='del'>-	  - with or without encryption) as well as card before the Cisco</div><div class='del'>-	  acquisition (Aironet 4500, Aironet 4800, Aironet 4800B).</div><div class='del'>-</div><div class='del'>-	  This driver support both the standard Linux Wireless Extensions</div><div class='del'>-	  and Cisco proprietary API, so both the Linux Wireless Tools and the</div><div class='del'>-	  Cisco Linux utilities can be used to configure the card.</div><div class='del'>-</div><div class='del'>-	  The driver can be compiled as a module and will be named "airo".</div><div class='del'>-</div><div class='del'>-config AIRO_CS</div><div class='del'>-	tristate "Cisco/Aironet 34X/35X/4500/4800 PCMCIA cards"</div><div class='del'>-	depends on CFG80211 &amp;&amp; PCMCIA</div><div class='del'>-	select WIRELESS_EXT</div><div class='del'>-	select WEXT_SPY</div><div class='del'>-	select WEXT_PRIV</div><div class='del'>-	select CRYPTO</div><div class='del'>-	select CRYPTO_AES</div><div class='del'>-	select CRYPTO_CTR</div><div class='del'>-	help</div><div class='del'>-	  This is the standard Linux driver to support Cisco/Aironet PCMCIA</div><div class='del'>-	  802.11 wireless cards.  This driver is the same as the Aironet</div><div class='del'>-	  driver part of the Linux Pcmcia package.</div><div class='del'>-	  It supports the new 802.11b cards from Cisco (Cisco 34X, Cisco 35X</div><div class='del'>-	  - with or without encryption) as well as card before the Cisco</div><div class='del'>-	  acquisition (Aironet 4500, Aironet 4800, Aironet 4800B). It also</div><div class='del'>-	  supports OEM of Cisco such as the DELL TrueMobile 4800 and Xircom</div><div class='del'>-	  802.11b cards.</div><div class='del'>-</div><div class='del'>-	  This driver support both the standard Linux Wireless Extensions</div><div class='del'>-	  and Cisco proprietary API, so both the Linux Wireless Tools and the</div><div class='del'>-	  Cisco Linux utilities can be used to configure the card.</div><div class='del'>-</div><div class='del'>-endif # WLAN_VENDOR_CISCO</div><div class='head'>diff --git a/drivers/net/wireless/cisco/Makefile b/drivers/net/wireless/cisco/Makefile<br/>deleted file mode 100644<br/>index 506a19ce375f..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/cisco/Makefile?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/cisco/Makefile</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,3 +0,0 @@</div><div class='del'>-# SPDX-License-Identifier: GPL-2.0-only</div><div class='del'>-obj-$(CONFIG_AIRO)		+= airo.o</div><div class='del'>-obj-$(CONFIG_AIRO_CS)		+= airo_cs.o airo.o</div><div class='head'>diff --git a/drivers/net/wireless/cisco/airo.c b/drivers/net/wireless/cisco/airo.c<br/>deleted file mode 100644<br/>index dbd13f7aa3e6..000000000000<br/>--- a/<a href='/cgit/linux.git/tree/drivers/net/wireless/cisco/airo.c?id=aeb262c353354eab81ab0d3242afa70984b7dc34'>drivers/net/wireless/cisco/airo.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,8288 +0,0 @@</div><div class='del'>-/*======================================================================</div><div class='del'>-</div><div class='del'>-    Aironet driver for 4500 and 4800 series cards</div><div class='del'>-</div><div class='del'>-    This code is released under both the GPL version 2 and BSD licenses.</div><div class='del'>-    Either license may be used.  The respective licenses are found at</div><div class='del'>-    the end of this file.</div><div class='del'>-</div><div class='del'>-    This code was developed by Benjamin Reed &lt;breed@users.sourceforge.net&gt;</div><div class='del'>-    including portions of which come from the Aironet PC4500</div><div class='del'>-    Developer's Reference Manual and used with permission.  Copyright</div><div class='del'>-    (C) 1999 Benjamin Reed.  All Rights Reserved.  Permission to use</div><div class='del'>-    code in the Developer's manual was granted for this driver by</div><div class='del'>-    Aironet.  Major code contributions were received from Javier Achirica</div><div class='del'>-    &lt;achirica@users.sourceforge.net&gt; and Jean Tourrilhes &lt;jt@hpl.hp.com&gt;.</div><div class='del'>-    Code was also integrated from the Cisco Aironet driver for Linux.</div><div class='del'>-    Support for MPI350 cards was added by Fabrice Bellet</div><div class='del'>-    &lt;fabrice@bellet.info&gt;.</div><div class='del'>-</div><div class='del'>-======================================================================*/</div><div class='del'>-</div><div class='del'>-#include &lt;linux/err.h&gt;</div><div class='del'>-#include &lt;linux/init.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;linux/kernel.h&gt;</div><div class='del'>-#include &lt;linux/module.h&gt;</div><div class='del'>-#include &lt;linux/proc_fs.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;linux/sched.h&gt;</div><div class='del'>-#include &lt;linux/ptrace.h&gt;</div><div class='del'>-#include &lt;linux/slab.h&gt;</div><div class='del'>-#include &lt;linux/string.h&gt;</div><div class='del'>-#include &lt;linux/timer.h&gt;</div><div class='del'>-#include &lt;linux/interrupt.h&gt;</div><div class='del'>-#include &lt;linux/in.h&gt;</div><div class='del'>-#include &lt;linux/bitops.h&gt;</div><div class='del'>-#include &lt;linux/scatterlist.h&gt;</div><div class='del'>-#include &lt;linux/crypto.h&gt;</div><div class='del'>-#include &lt;linux/io.h&gt;</div><div class='del'>-#include &lt;asm/unaligned.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;linux/netdevice.h&gt;</div><div class='del'>-#include &lt;linux/etherdevice.h&gt;</div><div class='del'>-#include &lt;linux/skbuff.h&gt;</div><div class='del'>-#include &lt;linux/if_arp.h&gt;</div><div class='del'>-#include &lt;linux/ioport.h&gt;</div><div class='del'>-#include &lt;linux/pci.h&gt;</div><div class='del'>-#include &lt;linux/uaccess.h&gt;</div><div class='del'>-#include &lt;linux/kthread.h&gt;</div><div class='del'>-#include &lt;linux/freezer.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;crypto/aes.h&gt;</div><div class='del'>-#include &lt;crypto/skcipher.h&gt;</div><div class='del'>-</div><div class='del'>-#include &lt;net/cfg80211.h&gt;</div><div class='del'>-#include &lt;net/iw_handler.h&gt;</div><div class='del'>-</div><div class='del'>-#include "airo.h"</div><div class='del'>-</div><div class='del'>-#define DRV_NAME "airo"</div><div class='del'>-</div><div class='del'>-#ifdef CONFIG_PCI</div><div class='del'>-static const struct pci_device_id card_ids[] = {</div><div class='del'>-	{ 0x14b9, 1, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0x14b9, 0x4500, PCI_ANY_ID, PCI_ANY_ID },</div><div class='del'>-	{ 0x14b9, 0x4800, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0x14b9, 0x0340, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0x14b9, 0x0350, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0x14b9, 0x5000, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0x14b9, 0xa504, PCI_ANY_ID, PCI_ANY_ID, },</div><div class='del'>-	{ 0, }</div><div class='del'>-};</div><div class='del'>-MODULE_DEVICE_TABLE(pci, card_ids);</div><div class='del'>-</div><div class='del'>-static int airo_pci_probe(struct pci_dev *, const struct pci_device_id *);</div><div class='del'>-static void airo_pci_remove(struct pci_dev *);</div><div class='del'>-static int __maybe_unused airo_pci_suspend(struct device *dev);</div><div class='del'>-static int __maybe_unused airo_pci_resume(struct device *dev);</div><div class='del'>-</div><div class='del'>-static SIMPLE_DEV_PM_OPS(airo_pci_pm_ops,</div><div class='del'>-			 airo_pci_suspend,</div><div class='del'>-			 airo_pci_resume);</div><div class='del'>-</div><div class='del'>-static struct pci_driver airo_driver = {</div><div class='del'>-	.name      = DRV_NAME,</div><div class='del'>-	.id_table  = card_ids,</div><div class='del'>-	.probe     = airo_pci_probe,</div><div class='del'>-	.remove    = airo_pci_remove,</div><div class='del'>-	.driver.pm = &amp;airo_pci_pm_ops,</div><div class='del'>-};</div><div class='del'>-#endif /* CONFIG_PCI */</div><div class='del'>-</div><div class='del'>-/* Include Wireless Extension definition and check version - Jean II */</div><div class='del'>-#include &lt;linux/wireless.h&gt;</div><div class='del'>-#define WIRELESS_SPY		/* enable iwspy support */</div><div class='del'>-</div><div class='del'>-#define CISCO_EXT		/* enable Cisco extensions */</div><div class='del'>-#ifdef CISCO_EXT</div><div class='del'>-#include &lt;linux/delay.h&gt;</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-/* Hack to do some power saving */</div><div class='del'>-#define POWER_ON_DOWN</div><div class='del'>-</div><div class='del'>-/* As you can see this list is HUGH!</div><div class='del'>-   I really don't know what a lot of these counts are about, but they</div><div class='del'>-   are all here for completeness.  If the IGNLABEL macro is put in</div><div class='del'>-   infront of the label, that statistic will not be included in the list</div><div class='del'>-   of statistics in the /proc filesystem */</div><div class='del'>-</div><div class='del'>-#define IGNLABEL(comment) NULL</div><div class='del'>-static const char *statsLabels[] = {</div><div class='del'>-	"RxOverrun",</div><div class='del'>-	IGNLABEL("RxPlcpCrcErr"),</div><div class='del'>-	IGNLABEL("RxPlcpFormatErr"),</div><div class='del'>-	IGNLABEL("RxPlcpLengthErr"),</div><div class='del'>-	"RxMacCrcErr",</div><div class='del'>-	"RxMacCrcOk",</div><div class='del'>-	"RxWepErr",</div><div class='del'>-	"RxWepOk",</div><div class='del'>-	"RetryLong",</div><div class='del'>-	"RetryShort",</div><div class='del'>-	"MaxRetries",</div><div class='del'>-	"NoAck",</div><div class='del'>-	"NoCts",</div><div class='del'>-	"RxAck",</div><div class='del'>-	"RxCts",</div><div class='del'>-	"TxAck",</div><div class='del'>-	"TxRts",</div><div class='del'>-	"TxCts",</div><div class='del'>-	"TxMc",</div><div class='del'>-	"TxBc",</div><div class='del'>-	"TxUcFrags",</div><div class='del'>-	"TxUcPackets",</div><div class='del'>-	"TxBeacon",</div><div class='del'>-	"RxBeacon",</div><div class='del'>-	"TxSinColl",</div><div class='del'>-	"TxMulColl",</div><div class='del'>-	"DefersNo",</div><div class='del'>-	"DefersProt",</div><div class='del'>-	"DefersEngy",</div><div class='del'>-	"DupFram",</div><div class='del'>-	"RxFragDisc",</div><div class='del'>-	"TxAged",</div><div class='del'>-	"RxAged",</div><div class='del'>-	"LostSync-MaxRetry",</div><div class='del'>-	"LostSync-MissedBeacons",</div><div class='del'>-	"LostSync-ArlExceeded",</div><div class='del'>-	"LostSync-Deauth",</div><div class='del'>-	"LostSync-Disassoced",</div><div class='del'>-	"LostSync-TsfTiming",</div><div class='del'>-	"HostTxMc",</div><div class='del'>-	"HostTxBc",</div><div class='del'>-	"HostTxUc",</div><div class='del'>-	"HostTxFail",</div><div class='del'>-	"HostRxMc",</div><div class='del'>-	"HostRxBc",</div><div class='del'>-	"HostRxUc",</div><div class='del'>-	"HostRxDiscard",</div><div class='del'>-	IGNLABEL("HmacTxMc"),</div><div class='del'>-	IGNLABEL("HmacTxBc"),</div><div class='del'>-	IGNLABEL("HmacTxUc"),</div><div class='del'>-	IGNLABEL("HmacTxFail"),</div><div class='del'>-	IGNLABEL("HmacRxMc"),</div><div class='del'>-	IGNLABEL("HmacRxBc"),</div><div class='del'>-	IGNLABEL("HmacRxUc"),</div><div class='del'>-	IGNLABEL("HmacRxDiscard"),</div><div class='del'>-	IGNLABEL("HmacRxAccepted"),</div><div class='del'>-	"SsidMismatch",</div><div class='del'>-	"ApMismatch",</div><div class='del'>-	"RatesMismatch",</div><div class='del'>-	"AuthReject",</div><div class='del'>-	"AuthTimeout",</div><div class='del'>-	"AssocReject",</div><div class='del'>-	"AssocTimeout",</div><div class='del'>-	IGNLABEL("ReasonOutsideTable"),</div><div class='del'>-	IGNLABEL("ReasonStatus1"),</div><div class='del'>-	IGNLABEL("ReasonStatus2"),</div><div class='del'>-	IGNLABEL("ReasonStatus3"),</div><div class='del'>-	IGNLABEL("ReasonStatus4"),</div><div class='del'>-	IGNLABEL("ReasonStatus5"),</div><div class='del'>-	IGNLABEL("ReasonStatus6"),</div><div class='del'>-	IGNLABEL("ReasonStatus7"),</div><div class='del'>-	IGNLABEL("ReasonStatus8"),</div><div class='del'>-	IGNLABEL("ReasonStatus9"),</div><div class='del'>-	IGNLABEL("ReasonStatus10"),</div><div class='del'>-	IGNLABEL("ReasonStatus11"),</div><div class='del'>-	IGNLABEL("ReasonStatus12"),</div><div class='del'>-	IGNLABEL("ReasonStatus13"),</div><div class='del'>-	IGNLABEL("ReasonStatus14"),</div><div class='del'>-	IGNLABEL("ReasonStatus15"),</div><div class='del'>-	IGNLABEL("ReasonStatus16"),</div><div class='del'>-	IGNLABEL("ReasonStatus17"),</div><div class='del'>-	IGNLABEL("ReasonStatus18"),</div><div class='del'>-	IGNLABEL("ReasonStatus19"),</div><div class='del'>-	"RxMan",</div><div class='del'>-	"TxMan",</div><div class='del'>-	"RxRefresh",</div><div class='del'>-	"TxRefresh",</div><div class='del'>-	"RxPoll",</div><div class='del'>-	"TxPoll",</div><div class='del'>-	"HostRetries",</div><div class='del'>-	"LostSync-HostReq",</div><div class='del'>-	"HostTxBytes",</div><div class='del'>-	"HostRxBytes",</div><div class='del'>-	"ElapsedUsec",</div><div class='del'>-	"ElapsedSec",</div><div class='del'>-	"LostSyncBetterAP",</div><div class='del'>-	"PrivacyMismatch",</div><div class='del'>-	"Jammed",</div><div class='del'>-	"DiscRxNotWepped",</div><div class='del'>-	"PhyEleMismatch",</div><div class='del'>-	(char*)-1 };</div><div class='del'>-#ifndef RUN_AT</div><div class='del'>-#define RUN_AT(x) (jiffies+(x))</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/* These variables are for insmod, since it seems that the rates</div><div class='del'>-   can only be set in setup_card.  Rates should be a comma separated</div><div class='del'>-   (no spaces) list of rates (up to 8). */</div><div class='del'>-</div><div class='del'>-static int rates[8];</div><div class='del'>-static char *ssids[3];</div><div class='del'>-</div><div class='del'>-static int io[4];</div><div class='del'>-static int irq[4];</div><div class='del'>-</div><div class='del'>-static</div><div class='del'>-int maxencrypt /* = 0 */; /* The highest rate that the card can encrypt at.</div><div class='del'>-		       0 means no limit.  For old cards this was 4 */</div><div class='del'>-</div><div class='del'>-static int auto_wep /* = 0 */; /* If set, it tries to figure out the wep mode */</div><div class='del'>-static int aux_bap /* = 0 */; /* Checks to see if the aux ports are needed to read</div><div class='del'>-		    the bap, needed on some older cards and buses. */</div><div class='del'>-static int adhoc;</div><div class='del'>-</div><div class='del'>-static int probe = 1;</div><div class='del'>-</div><div class='del'>-static kuid_t proc_kuid;</div><div class='del'>-static int proc_uid /* = 0 */;</div><div class='del'>-</div><div class='del'>-static kgid_t proc_kgid;</div><div class='del'>-static int proc_gid /* = 0 */;</div><div class='del'>-</div><div class='del'>-static int airo_perm = 0555;</div><div class='del'>-</div><div class='del'>-static int proc_perm = 0644;</div><div class='del'>-</div><div class='del'>-MODULE_AUTHOR("Benjamin Reed");</div><div class='del'>-MODULE_DESCRIPTION("Support for Cisco/Aironet 802.11 wireless ethernet cards.  "</div><div class='del'>-		   "Direct support for ISA/PCI/MPI cards and support for PCMCIA when used with airo_cs.");</div><div class='del'>-MODULE_LICENSE("Dual BSD/GPL");</div><div class='del'>-module_param_hw_array(io, int, ioport, NULL, 0);</div><div class='del'>-module_param_hw_array(irq, int, irq, NULL, 0);</div><div class='del'>-module_param_array(rates, int, NULL, 0);</div><div class='del'>-module_param_array(ssids, charp, NULL, 0);</div><div class='del'>-module_param(auto_wep, int, 0);</div><div class='del'>-MODULE_PARM_DESC(auto_wep,</div><div class='del'>-		 "If non-zero, the driver will keep looping through the authentication options until an association is made.  "</div><div class='del'>-		 "The value of auto_wep is number of the wep keys to check.  "</div><div class='del'>-		 "A value of 2 will try using the key at index 0 and index 1.");</div><div class='del'>-module_param(aux_bap, int, 0);</div><div class='del'>-MODULE_PARM_DESC(aux_bap,</div><div class='del'>-		 "If non-zero, the driver will switch into a mode that seems to work better for older cards with some older buses.  "</div><div class='del'>-		 "Before switching it checks that the switch is needed.");</div><div class='del'>-module_param(maxencrypt, int, 0);</div><div class='del'>-MODULE_PARM_DESC(maxencrypt,</div><div class='del'>-		 "The maximum speed that the card can do encryption.  "</div><div class='del'>-		 "Units are in 512kbs.  "</div><div class='del'>-		 "Zero (default) means there is no limit.  "</div><div class='del'>-		 "Older cards used to be limited to 2mbs (4).");</div><div class='del'>-module_param(adhoc, int, 0);</div><div class='del'>-MODULE_PARM_DESC(adhoc, "If non-zero, the card will start in adhoc mode.");</div><div class='del'>-module_param(probe, int, 0);</div><div class='del'>-MODULE_PARM_DESC(probe, "If zero, the driver won't start the card.");</div><div class='del'>-</div><div class='del'>-module_param(proc_uid, int, 0);</div><div class='del'>-MODULE_PARM_DESC(proc_uid, "The uid that the /proc files will belong to.");</div><div class='del'>-module_param(proc_gid, int, 0);</div><div class='del'>-MODULE_PARM_DESC(proc_gid, "The gid that the /proc files will belong to.");</div><div class='del'>-module_param(airo_perm, int, 0);</div><div class='del'>-MODULE_PARM_DESC(airo_perm, "The permission bits of /proc/[driver/]aironet.");</div><div class='del'>-module_param(proc_perm, int, 0);</div><div class='del'>-MODULE_PARM_DESC(proc_perm, "The permission bits of the files in /proc");</div><div class='del'>-</div><div class='del'>-/* This is a kind of sloppy hack to get this information to OUT4500 and</div><div class='del'>-   IN4500.  I would be extremely interested in the situation where this</div><div class='del'>-   doesn't work though!!! */</div><div class='del'>-static int do8bitIO /* = 0 */;</div><div class='del'>-</div><div class='del'>-/* Return codes */</div><div class='del'>-#define SUCCESS 0</div><div class='del'>-#define ERROR -1</div><div class='del'>-#define NO_PACKET -2</div><div class='del'>-</div><div class='del'>-/* Commands */</div><div class='del'>-#define NOP2		0x0000</div><div class='del'>-#define MAC_ENABLE	0x0001</div><div class='del'>-#define MAC_DISABLE	0x0002</div><div class='del'>-#define CMD_LOSE_SYNC	0x0003 /* Not sure what this does... */</div><div class='del'>-#define CMD_SOFTRESET	0x0004</div><div class='del'>-#define HOSTSLEEP	0x0005</div><div class='del'>-#define CMD_MAGIC_PKT	0x0006</div><div class='del'>-#define CMD_SETWAKEMASK	0x0007</div><div class='del'>-#define CMD_READCFG	0x0008</div><div class='del'>-#define CMD_SETMODE	0x0009</div><div class='del'>-#define CMD_ALLOCATETX	0x000a</div><div class='del'>-#define CMD_TRANSMIT	0x000b</div><div class='del'>-#define CMD_DEALLOCATETX 0x000c</div><div class='del'>-#define NOP		0x0010</div><div class='del'>-#define CMD_WORKAROUND	0x0011</div><div class='del'>-#define CMD_ALLOCATEAUX 0x0020</div><div class='del'>-#define CMD_ACCESS	0x0021</div><div class='del'>-#define CMD_PCIBAP	0x0022</div><div class='del'>-#define CMD_PCIAUX	0x0023</div><div class='del'>-#define CMD_ALLOCBUF	0x0028</div><div class='del'>-#define CMD_GETTLV	0x0029</div><div class='del'>-#define CMD_PUTTLV	0x002a</div><div class='del'>-#define CMD_DELTLV	0x002b</div><div class='del'>-#define CMD_FINDNEXTTLV	0x002c</div><div class='del'>-#define CMD_PSPNODES	0x0030</div><div class='del'>-#define CMD_SETCW	0x0031</div><div class='del'>-#define CMD_SETPCF	0x0032</div><div class='del'>-#define CMD_SETPHYREG	0x003e</div><div class='del'>-#define CMD_TXTEST	0x003f</div><div class='del'>-#define MAC_ENABLETX	0x0101</div><div class='del'>-#define CMD_LISTBSS	0x0103</div><div class='del'>-#define CMD_SAVECFG	0x0108</div><div class='del'>-#define CMD_ENABLEAUX	0x0111</div><div class='del'>-#define CMD_WRITERID	0x0121</div><div class='del'>-#define CMD_USEPSPNODES	0x0130</div><div class='del'>-#define MAC_ENABLERX	0x0201</div><div class='del'>-</div><div class='del'>-/* Command errors */</div><div class='del'>-#define ERROR_QUALIF 0x00</div><div class='del'>-#define ERROR_ILLCMD 0x01</div><div class='del'>-#define ERROR_ILLFMT 0x02</div><div class='del'>-#define ERROR_INVFID 0x03</div><div class='del'>-#define ERROR_INVRID 0x04</div><div class='del'>-#define ERROR_LARGE 0x05</div><div class='del'>-#define ERROR_NDISABL 0x06</div><div class='del'>-#define ERROR_ALLOCBSY 0x07</div><div class='del'>-#define ERROR_NORD 0x0B</div><div class='del'>-#define ERROR_NOWR 0x0C</div><div class='del'>-#define ERROR_INVFIDTX 0x0D</div><div class='del'>-#define ERROR_TESTACT 0x0E</div><div class='del'>-#define ERROR_TAGNFND 0x12</div><div class='del'>-#define ERROR_DECODE 0x20</div><div class='del'>-#define ERROR_DESCUNAV 0x21</div><div class='del'>-#define ERROR_BADLEN 0x22</div><div class='del'>-#define ERROR_MODE 0x80</div><div class='del'>-#define ERROR_HOP 0x81</div><div class='del'>-#define ERROR_BINTER 0x82</div><div class='del'>-#define ERROR_RXMODE 0x83</div><div class='del'>-#define ERROR_MACADDR 0x84</div><div class='del'>-#define ERROR_RATES 0x85</div><div class='del'>-#define ERROR_ORDER 0x86</div><div class='del'>-#define ERROR_SCAN 0x87</div><div class='del'>-#define ERROR_AUTH 0x88</div><div class='del'>-#define ERROR_PSMODE 0x89</div><div class='del'>-#define ERROR_RTYPE 0x8A</div><div class='del'>-#define ERROR_DIVER 0x8B</div><div class='del'>-#define ERROR_SSID 0x8C</div><div class='del'>-#define ERROR_APLIST 0x8D</div><div class='del'>-#define ERROR_AUTOWAKE 0x8E</div><div class='del'>-#define ERROR_LEAP 0x8F</div><div class='del'>-</div><div class='del'>-/* Registers */</div><div class='del'>-#define COMMAND 0x00</div><div class='del'>-#define PARAM0 0x02</div><div class='del'>-#define PARAM1 0x04</div><div class='del'>-#define PARAM2 0x06</div><div class='del'>-#define STATUS 0x08</div><div class='del'>-#define RESP0 0x0a</div><div class='del'>-#define RESP1 0x0c</div><div class='del'>-#define RESP2 0x0e</div><div class='del'>-#define LINKSTAT 0x10</div><div class='del'>-#define SELECT0 0x18</div><div class='del'>-#define OFFSET0 0x1c</div><div class='del'>-#define RXFID 0x20</div><div class='del'>-#define TXALLOCFID 0x22</div><div class='del'>-#define TXCOMPLFID 0x24</div><div class='del'>-#define DATA0 0x36</div><div class='del'>-#define EVSTAT 0x30</div><div class='del'>-#define EVINTEN 0x32</div><div class='del'>-#define EVACK 0x34</div><div class='del'>-#define SWS0 0x28</div><div class='del'>-#define SWS1 0x2a</div><div class='del'>-#define SWS2 0x2c</div><div class='del'>-#define SWS3 0x2e</div><div class='del'>-#define AUXPAGE 0x3A</div><div class='del'>-#define AUXOFF 0x3C</div><div class='del'>-#define AUXDATA 0x3E</div><div class='del'>-</div><div class='del'>-#define FID_TX 1</div><div class='del'>-#define FID_RX 2</div><div class='del'>-/* Offset into aux memory for descriptors */</div><div class='del'>-#define AUX_OFFSET 0x800</div><div class='del'>-/* Size of allocated packets */</div><div class='del'>-#define PKTSIZE 1840</div><div class='del'>-#define RIDSIZE 2048</div><div class='del'>-/* Size of the transmit queue */</div><div class='del'>-#define MAXTXQ 64</div><div class='del'>-</div><div class='del'>-/* BAP selectors */</div><div class='del'>-#define BAP0 0 /* Used for receiving packets */</div><div class='del'>-#define BAP1 2 /* Used for xmiting packets and working with RIDS */</div><div class='del'>-</div><div class='del'>-/* Flags */</div><div class='del'>-#define COMMAND_BUSY 0x8000</div><div class='del'>-</div><div class='del'>-#define BAP_BUSY 0x8000</div><div class='del'>-#define BAP_ERR 0x4000</div><div class='del'>-#define BAP_DONE 0x2000</div><div class='del'>-</div><div class='del'>-#define PROMISC 0xffff</div><div class='del'>-#define NOPROMISC 0x0000</div><div class='del'>-</div><div class='del'>-#define EV_CMD 0x10</div><div class='del'>-#define EV_CLEARCOMMANDBUSY 0x4000</div><div class='del'>-#define EV_RX 0x01</div><div class='del'>-#define EV_TX 0x02</div><div class='del'>-#define EV_TXEXC 0x04</div><div class='del'>-#define EV_ALLOC 0x08</div><div class='del'>-#define EV_LINK 0x80</div><div class='del'>-#define EV_AWAKE 0x100</div><div class='del'>-#define EV_TXCPY 0x400</div><div class='del'>-#define EV_UNKNOWN 0x800</div><div class='del'>-#define EV_MIC 0x1000 /* Message Integrity Check Interrupt */</div><div class='del'>-#define EV_AWAKEN 0x2000</div><div class='del'>-#define STATUS_INTS (EV_AWAKE|EV_LINK|EV_TXEXC|EV_TX|EV_TXCPY|EV_RX|EV_MIC)</div><div class='del'>-</div><div class='del'>-#ifdef CHECK_UNKNOWN_INTS</div><div class='del'>-#define IGNORE_INTS (EV_CMD | EV_UNKNOWN)</div><div class='del'>-#else</div><div class='del'>-#define IGNORE_INTS (~STATUS_INTS)</div><div class='del'>-#endif</div><div class='del'>-</div><div class='del'>-/* RID TYPES */</div><div class='del'>-#define RID_RW 0x20</div><div class='del'>-</div><div class='del'>-/* The RIDs */</div><div class='del'>-#define RID_CAPABILITIES 0xFF00</div><div class='del'>-#define RID_APINFO     0xFF01</div><div class='del'>-#define RID_RADIOINFO  0xFF02</div><div class='del'>-#define RID_UNKNOWN3   0xFF03</div><div class='del'>-#define RID_RSSI       0xFF04</div><div class='del'>-#define RID_CONFIG     0xFF10</div><div class='del'>-#define RID_SSID       0xFF11</div><div class='del'>-#define RID_APLIST     0xFF12</div><div class='del'>-#define RID_DRVNAME    0xFF13</div><div class='del'>-#define RID_ETHERENCAP 0xFF14</div><div class='del'>-#define RID_WEP_TEMP   0xFF15</div><div class='del'>-#define RID_WEP_PERM   0xFF16</div><div class='del'>-#define RID_MODULATION 0xFF17</div><div class='del'>-#define RID_OPTIONS    0xFF18</div><div class='del'>-#define RID_ACTUALCONFIG 0xFF20 /*readonly*/</div><div class='del'>-#define RID_FACTORYCONFIG 0xFF21</div><div class='del'>-#define RID_UNKNOWN22  0xFF22</div><div class='del'>-#define RID_LEAPUSERNAME 0xFF23</div><div class='del'>-#define RID_LEAPPASSWORD 0xFF24</div><div class='del'>-#define RID_STATUS     0xFF50</div><div class='del'>-#define RID_BEACON_HST 0xFF51</div><div class='del'>-#define RID_BUSY_HST   0xFF52</div><div class='del'>-#define RID_RETRIES_HST 0xFF53</div><div class='del'>-#define RID_UNKNOWN54  0xFF54</div><div class='del'>-#define RID_UNKNOWN55  0xFF55</div><div class='del'>-#define RID_UNKNOWN56  0xFF56</div><div class='del'>-#define RID_MIC        0xFF57</div><div class='del'>-#define RID_STATS16    0xFF60</div><div class='del'>-#define RID_STATS16DELTA 0xFF61</div><div class='del'>-#define RID_STATS16DELTACLEAR 0xFF62</div><div class='del'>-#define RID_STATS      0xFF68</div><div class='del'>-#define RID_STATSDELTA 0xFF69</div><div class='del'>-#define RID_STATSDELTACLEAR 0xFF6A</div><div class='del'>-#define RID_ECHOTEST_RID 0xFF70</div><div class='del'>-#define RID_ECHOTEST_RESULTS 0xFF71</div><div class='del'>-#define RID_BSSLISTFIRST 0xFF72</div><div class='del'>-#define RID_BSSLISTNEXT  0xFF73</div><div class='del'>-#define RID_WPA_BSSLISTFIRST 0xFF74</div><div class='del'>-#define RID_WPA_BSSLISTNEXT  0xFF75</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	u16 cmd;</div><div class='del'>-	u16 parm0;</div><div class='del'>-	u16 parm1;</div><div class='del'>-	u16 parm2;</div><div class='del'>-} Cmd;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	u16 status;</div><div class='del'>-	u16 rsp0;</div><div class='del'>-	u16 rsp1;</div><div class='del'>-	u16 rsp2;</div><div class='del'>-} Resp;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Rids and endian-ness:  The Rids will always be in cpu endian, since</div><div class='del'>- * this all the patches from the big-endian guys end up doing that.</div><div class='del'>- * so all rid access should use the read/writeXXXRid routines.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/* This structure came from an email sent to me from an engineer at</div><div class='del'>-   aironet for inclusion into this driver */</div><div class='del'>-typedef struct WepKeyRid WepKeyRid;</div><div class='del'>-struct WepKeyRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	__le16 kindex;</div><div class='del'>-	u8 mac[ETH_ALEN];</div><div class='del'>-	__le16 klen;</div><div class='del'>-	u8 key[16];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-/* These structures are from the Aironet's PC4500 Developers Manual */</div><div class='del'>-typedef struct Ssid Ssid;</div><div class='del'>-struct Ssid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	u8 ssid[32];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct SsidRid SsidRid;</div><div class='del'>-struct SsidRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	Ssid ssids[3];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct ModulationRid ModulationRid;</div><div class='del'>-struct ModulationRid {</div><div class='del'>-        __le16 len;</div><div class='del'>-        __le16 modulation;</div><div class='del'>-#define MOD_DEFAULT cpu_to_le16(0)</div><div class='del'>-#define MOD_CCK cpu_to_le16(1)</div><div class='del'>-#define MOD_MOK cpu_to_le16(2)</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct ConfigRid ConfigRid;</div><div class='del'>-struct ConfigRid {</div><div class='del'>-	__le16 len; /* sizeof(ConfigRid) */</div><div class='del'>-	__le16 opmode; /* operating mode */</div><div class='del'>-#define MODE_STA_IBSS cpu_to_le16(0)</div><div class='del'>-#define MODE_STA_ESS cpu_to_le16(1)</div><div class='del'>-#define MODE_AP cpu_to_le16(2)</div><div class='del'>-#define MODE_AP_RPTR cpu_to_le16(3)</div><div class='del'>-#define MODE_CFG_MASK cpu_to_le16(0xff)</div><div class='del'>-#define MODE_ETHERNET_HOST cpu_to_le16(0&lt;&lt;8) /* rx payloads converted */</div><div class='del'>-#define MODE_LLC_HOST cpu_to_le16(1&lt;&lt;8) /* rx payloads left as is */</div><div class='del'>-#define MODE_AIRONET_EXTEND cpu_to_le16(1&lt;&lt;9) /* enable Aironet extensions */</div><div class='del'>-#define MODE_AP_INTERFACE cpu_to_le16(1&lt;&lt;10) /* enable ap interface extensions */</div><div class='del'>-#define MODE_ANTENNA_ALIGN cpu_to_le16(1&lt;&lt;11) /* enable antenna alignment */</div><div class='del'>-#define MODE_ETHER_LLC cpu_to_le16(1&lt;&lt;12) /* enable ethernet LLC */</div><div class='del'>-#define MODE_LEAF_NODE cpu_to_le16(1&lt;&lt;13) /* enable leaf node bridge */</div><div class='del'>-#define MODE_CF_POLLABLE cpu_to_le16(1&lt;&lt;14) /* enable CF pollable */</div><div class='del'>-#define MODE_MIC cpu_to_le16(1&lt;&lt;15) /* enable MIC */</div><div class='del'>-	__le16 rmode; /* receive mode */</div><div class='del'>-#define RXMODE_BC_MC_ADDR cpu_to_le16(0)</div><div class='del'>-#define RXMODE_BC_ADDR cpu_to_le16(1) /* ignore multicasts */</div><div class='del'>-#define RXMODE_ADDR cpu_to_le16(2) /* ignore multicast and broadcast */</div><div class='del'>-#define RXMODE_RFMON cpu_to_le16(3) /* wireless monitor mode */</div><div class='del'>-#define RXMODE_RFMON_ANYBSS cpu_to_le16(4)</div><div class='del'>-#define RXMODE_LANMON cpu_to_le16(5) /* lan style monitor -- data packets only */</div><div class='del'>-#define RXMODE_MASK cpu_to_le16(255)</div><div class='del'>-#define RXMODE_DISABLE_802_3_HEADER cpu_to_le16(1&lt;&lt;8) /* disables 802.3 header on rx */</div><div class='del'>-#define RXMODE_FULL_MASK (RXMODE_MASK | RXMODE_DISABLE_802_3_HEADER)</div><div class='del'>-#define RXMODE_NORMALIZED_RSSI cpu_to_le16(1&lt;&lt;9) /* return normalized RSSI */</div><div class='del'>-	__le16 fragThresh;</div><div class='del'>-	__le16 rtsThres;</div><div class='del'>-	u8 macAddr[ETH_ALEN];</div><div class='del'>-	u8 rates[8];</div><div class='del'>-	__le16 shortRetryLimit;</div><div class='del'>-	__le16 longRetryLimit;</div><div class='del'>-	__le16 txLifetime; /* in kusec */</div><div class='del'>-	__le16 rxLifetime; /* in kusec */</div><div class='del'>-	__le16 stationary;</div><div class='del'>-	__le16 ordering;</div><div class='del'>-	__le16 u16deviceType; /* for overriding device type */</div><div class='del'>-	__le16 cfpRate;</div><div class='del'>-	__le16 cfpDuration;</div><div class='del'>-	__le16 _reserved1[3];</div><div class='del'>-	/*---------- Scanning/Associating ----------*/</div><div class='del'>-	__le16 scanMode;</div><div class='del'>-#define SCANMODE_ACTIVE cpu_to_le16(0)</div><div class='del'>-#define SCANMODE_PASSIVE cpu_to_le16(1)</div><div class='del'>-#define SCANMODE_AIROSCAN cpu_to_le16(2)</div><div class='del'>-	__le16 probeDelay; /* in kusec */</div><div class='del'>-	__le16 probeEnergyTimeout; /* in kusec */</div><div class='del'>-        __le16 probeResponseTimeout;</div><div class='del'>-	__le16 beaconListenTimeout;</div><div class='del'>-	__le16 joinNetTimeout;</div><div class='del'>-	__le16 authTimeout;</div><div class='del'>-	__le16 authType;</div><div class='del'>-#define AUTH_OPEN cpu_to_le16(0x1)</div><div class='del'>-#define AUTH_ENCRYPT cpu_to_le16(0x101)</div><div class='del'>-#define AUTH_SHAREDKEY cpu_to_le16(0x102)</div><div class='del'>-#define AUTH_ALLOW_UNENCRYPTED cpu_to_le16(0x200)</div><div class='del'>-	__le16 associationTimeout;</div><div class='del'>-	__le16 specifiedApTimeout;</div><div class='del'>-	__le16 offlineScanInterval;</div><div class='del'>-	__le16 offlineScanDuration;</div><div class='del'>-	__le16 linkLossDelay;</div><div class='del'>-	__le16 maxBeaconLostTime;</div><div class='del'>-	__le16 refreshInterval;</div><div class='del'>-#define DISABLE_REFRESH cpu_to_le16(0xFFFF)</div><div class='del'>-	__le16 _reserved1a[1];</div><div class='del'>-	/*---------- Power save operation ----------*/</div><div class='del'>-	__le16 powerSaveMode;</div><div class='del'>-#define POWERSAVE_CAM cpu_to_le16(0)</div><div class='del'>-#define POWERSAVE_PSP cpu_to_le16(1)</div><div class='del'>-#define POWERSAVE_PSPCAM cpu_to_le16(2)</div><div class='del'>-	__le16 sleepForDtims;</div><div class='del'>-	__le16 listenInterval;</div><div class='del'>-	__le16 fastListenInterval;</div><div class='del'>-	__le16 listenDecay;</div><div class='del'>-	__le16 fastListenDelay;</div><div class='del'>-	__le16 _reserved2[2];</div><div class='del'>-	/*---------- Ap/Ibss config items ----------*/</div><div class='del'>-	__le16 beaconPeriod;</div><div class='del'>-	__le16 atimDuration;</div><div class='del'>-	__le16 hopPeriod;</div><div class='del'>-	__le16 channelSet;</div><div class='del'>-	__le16 channel;</div><div class='del'>-	__le16 dtimPeriod;</div><div class='del'>-	__le16 bridgeDistance;</div><div class='del'>-	__le16 radioID;</div><div class='del'>-	/*---------- Radio configuration ----------*/</div><div class='del'>-	__le16 radioType;</div><div class='del'>-#define RADIOTYPE_DEFAULT cpu_to_le16(0)</div><div class='del'>-#define RADIOTYPE_802_11 cpu_to_le16(1)</div><div class='del'>-#define RADIOTYPE_LEGACY cpu_to_le16(2)</div><div class='del'>-	u8 rxDiversity;</div><div class='del'>-	u8 txDiversity;</div><div class='del'>-	__le16 txPower;</div><div class='del'>-#define TXPOWER_DEFAULT 0</div><div class='del'>-	__le16 rssiThreshold;</div><div class='del'>-#define RSSI_DEFAULT 0</div><div class='del'>-        __le16 modulation;</div><div class='del'>-#define PREAMBLE_AUTO cpu_to_le16(0)</div><div class='del'>-#define PREAMBLE_LONG cpu_to_le16(1)</div><div class='del'>-#define PREAMBLE_SHORT cpu_to_le16(2)</div><div class='del'>-	__le16 preamble;</div><div class='del'>-	__le16 homeProduct;</div><div class='del'>-	__le16 radioSpecific;</div><div class='del'>-	/*---------- Aironet Extensions ----------*/</div><div class='del'>-	u8 nodeName[16];</div><div class='del'>-	__le16 arlThreshold;</div><div class='del'>-	__le16 arlDecay;</div><div class='del'>-	__le16 arlDelay;</div><div class='del'>-	__le16 _reserved4[1];</div><div class='del'>-	/*---------- Aironet Extensions ----------*/</div><div class='del'>-	u8 magicAction;</div><div class='del'>-#define MAGIC_ACTION_STSCHG 1</div><div class='del'>-#define MAGIC_ACTION_RESUME 2</div><div class='del'>-#define MAGIC_IGNORE_MCAST (1&lt;&lt;8)</div><div class='del'>-#define MAGIC_IGNORE_BCAST (1&lt;&lt;9)</div><div class='del'>-#define MAGIC_SWITCH_TO_PSP (0&lt;&lt;10)</div><div class='del'>-#define MAGIC_STAY_IN_CAM (1&lt;&lt;10)</div><div class='del'>-	u8 magicControl;</div><div class='del'>-	__le16 autoWake;</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct StatusRid StatusRid;</div><div class='del'>-struct StatusRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	u8 mac[ETH_ALEN];</div><div class='del'>-	__le16 mode;</div><div class='del'>-	__le16 errorCode;</div><div class='del'>-	__le16 sigQuality;</div><div class='del'>-	__le16 SSIDlen;</div><div class='del'>-	char SSID[32];</div><div class='del'>-	char apName[16];</div><div class='del'>-	u8 bssid[4][ETH_ALEN];</div><div class='del'>-	__le16 beaconPeriod;</div><div class='del'>-	__le16 dimPeriod;</div><div class='del'>-	__le16 atimDuration;</div><div class='del'>-	__le16 hopPeriod;</div><div class='del'>-	__le16 channelSet;</div><div class='del'>-	__le16 channel;</div><div class='del'>-	__le16 hopsToBackbone;</div><div class='del'>-	__le16 apTotalLoad;</div><div class='del'>-	__le16 generatedLoad;</div><div class='del'>-	__le16 accumulatedArl;</div><div class='del'>-	__le16 signalQuality;</div><div class='del'>-	__le16 currentXmitRate;</div><div class='del'>-	__le16 apDevExtensions;</div><div class='del'>-	__le16 normalizedSignalStrength;</div><div class='del'>-	__le16 shortPreamble;</div><div class='del'>-	u8 apIP[4];</div><div class='del'>-	u8 noisePercent; /* Noise percent in last second */</div><div class='del'>-	u8 noisedBm; /* Noise dBm in last second */</div><div class='del'>-	u8 noiseAvePercent; /* Noise percent in last minute */</div><div class='del'>-	u8 noiseAvedBm; /* Noise dBm in last minute */</div><div class='del'>-	u8 noiseMaxPercent; /* Highest noise percent in last minute */</div><div class='del'>-	u8 noiseMaxdBm; /* Highest noise dbm in last minute */</div><div class='del'>-	__le16 load;</div><div class='del'>-	u8 carrier[4];</div><div class='del'>-	__le16 assocStatus;</div><div class='del'>-#define STAT_NOPACKETS 0</div><div class='del'>-#define STAT_NOCARRIERSET 10</div><div class='del'>-#define STAT_GOTCARRIERSET 11</div><div class='del'>-#define STAT_WRONGSSID 20</div><div class='del'>-#define STAT_BADCHANNEL 25</div><div class='del'>-#define STAT_BADBITRATES 30</div><div class='del'>-#define STAT_BADPRIVACY 35</div><div class='del'>-#define STAT_APFOUND 40</div><div class='del'>-#define STAT_APREJECTED 50</div><div class='del'>-#define STAT_AUTHENTICATING 60</div><div class='del'>-#define STAT_DEAUTHENTICATED 61</div><div class='del'>-#define STAT_AUTHTIMEOUT 62</div><div class='del'>-#define STAT_ASSOCIATING 70</div><div class='del'>-#define STAT_DEASSOCIATED 71</div><div class='del'>-#define STAT_ASSOCTIMEOUT 72</div><div class='del'>-#define STAT_NOTAIROAP 73</div><div class='del'>-#define STAT_ASSOCIATED 80</div><div class='del'>-#define STAT_LEAPING 90</div><div class='del'>-#define STAT_LEAPFAILED 91</div><div class='del'>-#define STAT_LEAPTIMEDOUT 92</div><div class='del'>-#define STAT_LEAPCOMPLETE 93</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct StatsRid StatsRid;</div><div class='del'>-struct StatsRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	__le16 spacer;</div><div class='del'>-	__le32 vals[100];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct APListRid APListRid;</div><div class='del'>-struct APListRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	u8 ap[4][ETH_ALEN];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct CapabilityRid CapabilityRid;</div><div class='del'>-struct CapabilityRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	char oui[3];</div><div class='del'>-	char zero;</div><div class='del'>-	__le16 prodNum;</div><div class='del'>-	char manName[32];</div><div class='del'>-	char prodName[16];</div><div class='del'>-	char prodVer[8];</div><div class='del'>-	char factoryAddr[ETH_ALEN];</div><div class='del'>-	char aironetAddr[ETH_ALEN];</div><div class='del'>-	__le16 radioType;</div><div class='del'>-	__le16 country;</div><div class='del'>-	char callid[ETH_ALEN];</div><div class='del'>-	char supportedRates[8];</div><div class='del'>-	char rxDiversity;</div><div class='del'>-	char txDiversity;</div><div class='del'>-	__le16 txPowerLevels[8];</div><div class='del'>-	__le16 hardVer;</div><div class='del'>-	__le16 hardCap;</div><div class='del'>-	__le16 tempRange;</div><div class='del'>-	__le16 softVer;</div><div class='del'>-	__le16 softSubVer;</div><div class='del'>-	__le16 interfaceVer;</div><div class='del'>-	__le16 softCap;</div><div class='del'>-	__le16 bootBlockVer;</div><div class='del'>-	__le16 requiredHard;</div><div class='del'>-	__le16 extSoftCap;</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-/* Only present on firmware &gt;= 5.30.17 */</div><div class='del'>-typedef struct BSSListRidExtra BSSListRidExtra;</div><div class='del'>-struct BSSListRidExtra {</div><div class='del'>-  __le16 unknown[4];</div><div class='del'>-  u8 fixed[12]; /* WLAN management frame */</div><div class='del'>-  u8 iep[624];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct BSSListRid BSSListRid;</div><div class='del'>-struct BSSListRid {</div><div class='del'>-  __le16 len;</div><div class='del'>-  __le16 index; /* First is 0 and 0xffff means end of list */</div><div class='del'>-#define RADIO_FH 1 /* Frequency hopping radio type */</div><div class='del'>-#define RADIO_DS 2 /* Direct sequence radio type */</div><div class='del'>-#define RADIO_TMA 4 /* Proprietary radio used in old cards (2500) */</div><div class='del'>-  __le16 radioType;</div><div class='del'>-  u8 bssid[ETH_ALEN]; /* Mac address of the BSS */</div><div class='del'>-  u8 zero;</div><div class='del'>-  u8 ssidLen;</div><div class='del'>-  u8 ssid[32];</div><div class='del'>-  __le16 dBm;</div><div class='del'>-#define CAP_ESS cpu_to_le16(1&lt;&lt;0)</div><div class='del'>-#define CAP_IBSS cpu_to_le16(1&lt;&lt;1)</div><div class='del'>-#define CAP_PRIVACY cpu_to_le16(1&lt;&lt;4)</div><div class='del'>-#define CAP_SHORTHDR cpu_to_le16(1&lt;&lt;5)</div><div class='del'>-  __le16 cap;</div><div class='del'>-  __le16 beaconInterval;</div><div class='del'>-  u8 rates[8]; /* Same as rates for config rid */</div><div class='del'>-  struct { /* For frequency hopping only */</div><div class='del'>-    __le16 dwell;</div><div class='del'>-    u8 hopSet;</div><div class='del'>-    u8 hopPattern;</div><div class='del'>-    u8 hopIndex;</div><div class='del'>-    u8 fill;</div><div class='del'>-  } fh;</div><div class='del'>-  __le16 dsChannel;</div><div class='del'>-  __le16 atimWindow;</div><div class='del'>-</div><div class='del'>-  /* Only present on firmware &gt;= 5.30.17 */</div><div class='del'>-  BSSListRidExtra extra;</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-  BSSListRid bss;</div><div class='del'>-  struct list_head list;</div><div class='del'>-} BSSListElement;</div><div class='del'>-</div><div class='del'>-typedef struct tdsRssiEntry tdsRssiEntry;</div><div class='del'>-struct tdsRssiEntry {</div><div class='del'>-  u8 rssipct;</div><div class='del'>-  u8 rssidBm;</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct tdsRssiRid tdsRssiRid;</div><div class='del'>-struct tdsRssiRid {</div><div class='del'>-  u16 len;</div><div class='del'>-  tdsRssiEntry x[256];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct MICRid MICRid;</div><div class='del'>-struct MICRid {</div><div class='del'>-	__le16 len;</div><div class='del'>-	__le16 state;</div><div class='del'>-	__le16 multicastValid;</div><div class='del'>-	u8  multicast[16];</div><div class='del'>-	__le16 unicastValid;</div><div class='del'>-	u8  unicast[16];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct MICBuffer MICBuffer;</div><div class='del'>-struct MICBuffer {</div><div class='del'>-	__be16 typelen;</div><div class='del'>-</div><div class='del'>-	union {</div><div class='del'>-	    u8 snap[8];</div><div class='del'>-	    struct {</div><div class='del'>-		u8 dsap;</div><div class='del'>-		u8 ssap;</div><div class='del'>-		u8 control;</div><div class='del'>-		u8 orgcode[3];</div><div class='del'>-		u8 fieldtype[2];</div><div class='del'>-	    } llc;</div><div class='del'>-	} u;</div><div class='del'>-	__be32 mic;</div><div class='del'>-	__be32 seq;</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	u8 da[ETH_ALEN];</div><div class='del'>-	u8 sa[ETH_ALEN];</div><div class='del'>-} etherHead;</div><div class='del'>-</div><div class='del'>-#define TXCTL_TXOK (1&lt;&lt;1) /* report if tx is ok */</div><div class='del'>-#define TXCTL_TXEX (1&lt;&lt;2) /* report if tx fails */</div><div class='del'>-#define TXCTL_802_3 (0&lt;&lt;3) /* 802.3 packet */</div><div class='del'>-#define TXCTL_802_11 (1&lt;&lt;3) /* 802.11 mac packet */</div><div class='del'>-#define TXCTL_ETHERNET (0&lt;&lt;4) /* payload has ethertype */</div><div class='del'>-#define TXCTL_LLC (1&lt;&lt;4) /* payload is llc */</div><div class='del'>-#define TXCTL_RELEASE (0&lt;&lt;5) /* release after completion */</div><div class='del'>-#define TXCTL_NORELEASE (1&lt;&lt;5) /* on completion returns to host */</div><div class='del'>-</div><div class='del'>-#define BUSY_FID 0x10000</div><div class='del'>-</div><div class='del'>-#ifdef CISCO_EXT</div><div class='del'>-#define AIROMAGIC	0xa55a</div><div class='del'>-/* Warning : SIOCDEVPRIVATE may disapear during 2.5.X - Jean II */</div><div class='del'>-#ifdef SIOCIWFIRSTPRIV</div><div class='del'>-#ifdef SIOCDEVPRIVATE</div><div class='del'>-#define AIROOLDIOCTL	SIOCDEVPRIVATE</div><div class='del'>-#define AIROOLDIDIFC 	AIROOLDIOCTL + 1</div><div class='del'>-#endif /* SIOCDEVPRIVATE */</div><div class='del'>-#else /* SIOCIWFIRSTPRIV */</div><div class='del'>-#define SIOCIWFIRSTPRIV SIOCDEVPRIVATE</div><div class='del'>-#endif /* SIOCIWFIRSTPRIV */</div><div class='del'>-/* This may be wrong. When using the new SIOCIWFIRSTPRIV range, we probably</div><div class='del'>- * should use only "GET" ioctls (last bit set to 1). "SET" ioctls are root</div><div class='del'>- * only and don't return the modified struct ifreq to the application which</div><div class='del'>- * is usually a problem. - Jean II */</div><div class='del'>-#define AIROIOCTL	SIOCIWFIRSTPRIV</div><div class='del'>-#define AIROIDIFC 	AIROIOCTL + 1</div><div class='del'>-</div><div class='del'>-/* Ioctl constants to be used in airo_ioctl.command */</div><div class='del'>-</div><div class='del'>-#define	AIROGCAP  		0	// Capability rid</div><div class='del'>-#define AIROGCFG		1       // USED A LOT</div><div class='del'>-#define AIROGSLIST		2	// System ID list</div><div class='del'>-#define AIROGVLIST		3       // List of specified AP's</div><div class='del'>-#define AIROGDRVNAM		4	//  NOTUSED</div><div class='del'>-#define AIROGEHTENC		5	// NOTUSED</div><div class='del'>-#define AIROGWEPKTMP		6</div><div class='del'>-#define AIROGWEPKNV		7</div><div class='del'>-#define AIROGSTAT		8</div><div class='del'>-#define AIROGSTATSC32		9</div><div class='del'>-#define AIROGSTATSD32		10</div><div class='del'>-#define AIROGMICRID		11</div><div class='del'>-#define AIROGMICSTATS		12</div><div class='del'>-#define AIROGFLAGS		13</div><div class='del'>-#define AIROGID			14</div><div class='del'>-#define AIRORRID		15</div><div class='del'>-#define AIRORSWVERSION		17</div><div class='del'>-</div><div class='del'>-/* Leave gap of 40 commands after AIROGSTATSD32 for future */</div><div class='del'>-</div><div class='del'>-#define AIROPCAP               	AIROGSTATSD32 + 40</div><div class='del'>-#define AIROPVLIST              AIROPCAP      + 1</div><div class='del'>-#define AIROPSLIST		AIROPVLIST    + 1</div><div class='del'>-#define AIROPCFG		AIROPSLIST    + 1</div><div class='del'>-#define AIROPSIDS		AIROPCFG      + 1</div><div class='del'>-#define AIROPAPLIST		AIROPSIDS     + 1</div><div class='del'>-#define AIROPMACON		AIROPAPLIST   + 1	/* Enable mac  */</div><div class='del'>-#define AIROPMACOFF		AIROPMACON    + 1 	/* Disable mac */</div><div class='del'>-#define AIROPSTCLR		AIROPMACOFF   + 1</div><div class='del'>-#define AIROPWEPKEY		AIROPSTCLR    + 1</div><div class='del'>-#define AIROPWEPKEYNV		AIROPWEPKEY   + 1</div><div class='del'>-#define AIROPLEAPPWD            AIROPWEPKEYNV + 1</div><div class='del'>-#define AIROPLEAPUSR            AIROPLEAPPWD  + 1</div><div class='del'>-</div><div class='del'>-/* Flash codes */</div><div class='del'>-</div><div class='del'>-#define AIROFLSHRST	       AIROPWEPKEYNV  + 40</div><div class='del'>-#define AIROFLSHGCHR           AIROFLSHRST    + 1</div><div class='del'>-#define AIROFLSHSTFL           AIROFLSHGCHR   + 1</div><div class='del'>-#define AIROFLSHPCHR           AIROFLSHSTFL   + 1</div><div class='del'>-#define AIROFLPUTBUF           AIROFLSHPCHR   + 1</div><div class='del'>-#define AIRORESTART            AIROFLPUTBUF   + 1</div><div class='del'>-</div><div class='del'>-#define FLASHSIZE	32768</div><div class='del'>-#define AUXMEMSIZE	(256 * 1024)</div><div class='del'>-</div><div class='del'>-typedef struct aironet_ioctl {</div><div class='del'>-	unsigned short command;		// What to do</div><div class='del'>-	unsigned short len;		// Len of data</div><div class='del'>-	unsigned short ridnum;		// rid number</div><div class='del'>-	unsigned char __user *data;	// d-data</div><div class='del'>-} aironet_ioctl;</div><div class='del'>-</div><div class='del'>-static const char swversion[] = "2.1";</div><div class='del'>-#endif /* CISCO_EXT */</div><div class='del'>-</div><div class='del'>-#define NUM_MODULES       2</div><div class='del'>-#define MIC_MSGLEN_MAX    2400</div><div class='del'>-#define EMMH32_MSGLEN_MAX MIC_MSGLEN_MAX</div><div class='del'>-#define AIRO_DEF_MTU      2312</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	u32   size;            // size</div><div class='del'>-	u8    enabled;         // MIC enabled or not</div><div class='del'>-	u32   rxSuccess;       // successful packets received</div><div class='del'>-	u32   rxIncorrectMIC;  // pkts dropped due to incorrect MIC comparison</div><div class='del'>-	u32   rxNotMICed;      // pkts dropped due to not being MIC'd</div><div class='del'>-	u32   rxMICPlummed;    // pkts dropped due to not having a MIC plummed</div><div class='del'>-	u32   rxWrongSequence; // pkts dropped due to sequence number violation</div><div class='del'>-	u32   reserve[32];</div><div class='del'>-} mic_statistics;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	__be32 coeff[((EMMH32_MSGLEN_MAX)+3)&gt;&gt;2];</div><div class='del'>-	u64 accum;	// accumulated mic, reduced to u32 in final()</div><div class='del'>-	int position;	// current position (byte offset) in message</div><div class='del'>-	union {</div><div class='del'>-		u8  d8[4];</div><div class='del'>-		__be32 d32;</div><div class='del'>-	} part;	// saves partial message word across update() calls</div><div class='del'>-} emmh32_context;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	emmh32_context seed;	    // Context - the seed</div><div class='del'>-	u32		 rx;	    // Received sequence number</div><div class='del'>-	u32		 tx;	    // Tx sequence number</div><div class='del'>-	u32		 window;    // Start of window</div><div class='del'>-	u8		 valid;	    // Flag to say if context is valid or not</div><div class='del'>-	u8		 key[16];</div><div class='del'>-} miccntx;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	miccntx mCtx;		// Multicast context</div><div class='del'>-	miccntx uCtx;		// Unicast context</div><div class='del'>-} mic_module;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned int  rid: 16;</div><div class='del'>-	unsigned int  len: 15;</div><div class='del'>-	unsigned int  valid: 1;</div><div class='del'>-	dma_addr_t host_addr;</div><div class='del'>-} Rid;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned int  offset: 15;</div><div class='del'>-	unsigned int  eoc: 1;</div><div class='del'>-	unsigned int  len: 15;</div><div class='del'>-	unsigned int  valid: 1;</div><div class='del'>-	dma_addr_t host_addr;</div><div class='del'>-} TxFid;</div><div class='del'>-</div><div class='del'>-struct rx_hdr {</div><div class='del'>-	__le16 status, len;</div><div class='del'>-	u8 rssi[2];</div><div class='del'>-	u8 rate;</div><div class='del'>-	u8 freq;</div><div class='del'>-	__le16 tmp[4];</div><div class='del'>-} __packed;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned int  ctl: 15;</div><div class='del'>-	unsigned int  rdy: 1;</div><div class='del'>-	unsigned int  len: 15;</div><div class='del'>-	unsigned int  valid: 1;</div><div class='del'>-	dma_addr_t host_addr;</div><div class='del'>-} RxFid;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Host receive descriptor</div><div class='del'>- */</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned char __iomem *card_ram_off; /* offset into card memory of the</div><div class='del'>-						desc */</div><div class='del'>-	RxFid         rx_desc;		     /* card receive descriptor */</div><div class='del'>-	char          *virtual_host_addr;    /* virtual address of host receive</div><div class='del'>-					        buffer */</div><div class='del'>-	int           pending;</div><div class='del'>-} HostRxDesc;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Host transmit descriptor</div><div class='del'>- */</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned char __iomem *card_ram_off;	     /* offset into card memory of the</div><div class='del'>-						desc */</div><div class='del'>-	TxFid         tx_desc;		     /* card transmit descriptor */</div><div class='del'>-	char          *virtual_host_addr;    /* virtual address of host receive</div><div class='del'>-					        buffer */</div><div class='del'>-	int           pending;</div><div class='del'>-} HostTxDesc;</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Host RID descriptor</div><div class='del'>- */</div><div class='del'>-typedef struct {</div><div class='del'>-	unsigned char __iomem *card_ram_off;      /* offset into card memory of the</div><div class='del'>-					     descriptor */</div><div class='del'>-	Rid           rid_desc;		  /* card RID descriptor */</div><div class='del'>-	char          *virtual_host_addr; /* virtual address of host receive</div><div class='del'>-					     buffer */</div><div class='del'>-} HostRidDesc;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	u16 sw0;</div><div class='del'>-	u16 sw1;</div><div class='del'>-	u16 status;</div><div class='del'>-	u16 len;</div><div class='del'>-#define HOST_SET (1 &lt;&lt; 0)</div><div class='del'>-#define HOST_INT_TX (1 &lt;&lt; 1) /* Interrupt on successful TX */</div><div class='del'>-#define HOST_INT_TXERR (1 &lt;&lt; 2) /* Interrupt on unseccessful TX */</div><div class='del'>-#define HOST_LCC_PAYLOAD (1 &lt;&lt; 4) /* LLC payload, 0 = Ethertype */</div><div class='del'>-#define HOST_DONT_RLSE (1 &lt;&lt; 5) /* Don't release buffer when done */</div><div class='del'>-#define HOST_DONT_RETRY (1 &lt;&lt; 6) /* Don't retry trasmit */</div><div class='del'>-#define HOST_CLR_AID (1 &lt;&lt; 7) /* clear AID failure */</div><div class='del'>-#define HOST_RTS (1 &lt;&lt; 9) /* Force RTS use */</div><div class='del'>-#define HOST_SHORT (1 &lt;&lt; 10) /* Do short preamble */</div><div class='del'>-	u16 ctl;</div><div class='del'>-	u16 aid;</div><div class='del'>-	u16 retries;</div><div class='del'>-	u16 fill;</div><div class='del'>-} TxCtlHdr;</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-        u16 ctl;</div><div class='del'>-        u16 duration;</div><div class='del'>-        char addr1[6];</div><div class='del'>-        char addr2[6];</div><div class='del'>-        char addr3[6];</div><div class='del'>-        u16 seq;</div><div class='del'>-        char addr4[6];</div><div class='del'>-} WifiHdr;</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-typedef struct {</div><div class='del'>-	TxCtlHdr ctlhdr;</div><div class='del'>-	u16 fill1;</div><div class='del'>-	u16 fill2;</div><div class='del'>-	WifiHdr wifihdr;</div><div class='del'>-	u16 gaplen;</div><div class='del'>-	u16 status;</div><div class='del'>-} WifiCtlHdr;</div><div class='del'>-</div><div class='del'>-static WifiCtlHdr wifictlhdr8023 = {</div><div class='del'>-	.ctlhdr = {</div><div class='del'>-		.ctl	= HOST_DONT_RLSE,</div><div class='del'>-	}</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-// A few details needed for WEP (Wireless Equivalent Privacy)</div><div class='del'>-#define MAX_KEY_SIZE 13			// 128 (?) bits</div><div class='del'>-#define MIN_KEY_SIZE  5			// 40 bits RC4 - WEP</div><div class='del'>-typedef struct wep_key_t {</div><div class='del'>-	u16	len;</div><div class='del'>-	u8	key[16];	/* 40-bit and 104-bit keys */</div><div class='del'>-} wep_key_t;</div><div class='del'>-</div><div class='del'>-/* List of Wireless Handlers (new API) */</div><div class='del'>-static const struct iw_handler_def	airo_handler_def;</div><div class='del'>-</div><div class='del'>-static const char version[] = "airo.c 0.6 (Ben Reed &amp; Javier Achirica)";</div><div class='del'>-</div><div class='del'>-struct airo_info;</div><div class='del'>-</div><div class='del'>-static int get_dec_u16(char *buffer, int *start, int limit);</div><div class='del'>-static void OUT4500(struct airo_info *, u16 reg, u16 value);</div><div class='del'>-static unsigned short IN4500(struct airo_info *, u16 reg);</div><div class='del'>-static u16 setup_card(struct airo_info*, struct net_device *dev, int lock);</div><div class='del'>-static int enable_MAC(struct airo_info *ai, int lock);</div><div class='del'>-static void disable_MAC(struct airo_info *ai, int lock);</div><div class='del'>-static void enable_interrupts(struct airo_info*);</div><div class='del'>-static void disable_interrupts(struct airo_info*);</div><div class='del'>-static u16 issuecommand(struct airo_info*, Cmd *pCmd, Resp *pRsp,</div><div class='del'>-			bool may_sleep);</div><div class='del'>-static int bap_setup(struct airo_info*, u16 rid, u16 offset, int whichbap);</div><div class='del'>-static int aux_bap_read(struct airo_info*, __le16 *pu16Dst, int bytelen,</div><div class='del'>-			int whichbap);</div><div class='del'>-static int fast_bap_read(struct airo_info*, __le16 *pu16Dst, int bytelen,</div><div class='del'>-			 int whichbap);</div><div class='del'>-static int bap_write(struct airo_info*, const __le16 *pu16Src, int bytelen,</div><div class='del'>-		     int whichbap);</div><div class='del'>-static int PC4500_accessrid(struct airo_info*, u16 rid, u16 accmd);</div><div class='del'>-static int PC4500_readrid(struct airo_info*, u16 rid, void *pBuf, int len, int lock);</div><div class='del'>-static int PC4500_writerid(struct airo_info*, u16 rid, const void</div><div class='del'>-			   *pBuf, int len, int lock);</div><div class='del'>-static int do_writerid(struct airo_info*, u16 rid, const void *rid_data,</div><div class='del'>-			int len, int dummy);</div><div class='del'>-static u16 transmit_allocate(struct airo_info*, int lenPayload, int raw);</div><div class='del'>-static int transmit_802_3_packet(struct airo_info*, int len, char *pPacket,</div><div class='del'>-				 bool may_sleep);</div><div class='del'>-static int transmit_802_11_packet(struct airo_info*, int len, char *pPacket,</div><div class='del'>-				  bool may_sleep);</div><div class='del'>-</div><div class='del'>-static int mpi_send_packet(struct net_device *dev);</div><div class='del'>-static void mpi_unmap_card(struct pci_dev *pci);</div><div class='del'>-static void mpi_receive_802_3(struct airo_info *ai);</div><div class='del'>-static void mpi_receive_802_11(struct airo_info *ai);</div><div class='del'>-static int waitbusy(struct airo_info *ai);</div><div class='del'>-</div><div class='del'>-static irqreturn_t airo_interrupt(int irq, void* dev_id);</div><div class='del'>-static int airo_thread(void *data);</div><div class='del'>-static void timer_func(struct net_device *dev);</div><div class='del'>-static int airo_siocdevprivate(struct net_device *dev, struct ifreq *rq, void __user *, int cmd);</div><div class='del'>-static struct iw_statistics *airo_get_wireless_stats(struct net_device *dev);</div><div class='del'>-#ifdef CISCO_EXT</div><div class='del'>-static int readrids(struct net_device *dev, aironet_ioctl *comp);</div><div class='del'>-static int writerids(struct net_device *dev, aironet_ioctl *comp);</div><div class='del'>-static int flashcard(struct net_device *dev, aironet_ioctl *comp);</div><div class='del'>-#endif /* CISCO_EXT */</div><div class='del'>-static void micinit(struct airo_info *ai);</div><div class='del'>-static int micsetup(struct airo_info *ai);</div><div class='del'>-static int encapsulate(struct airo_info *ai, etherHead *pPacket, MICBuffer *buffer, int len);</div><div class='del'>-static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *pPacket, u16 payLen);</div><div class='del'>-</div><div class='del'>-static u8 airo_rssi_to_dbm(tdsRssiEntry *rssi_rid, u8 rssi);</div><div class='del'>-static u8 airo_dbm_to_pct(tdsRssiEntry *rssi_rid, u8 dbm);</div><div class='del'>-</div><div class='del'>-static void airo_networks_free(struct airo_info *ai);</div><div class='del'>-</div><div class='del'>-struct airo_info {</div><div class='del'>-	struct net_device             *dev;</div><div class='del'>-	struct list_head              dev_list;</div><div class='del'>-	/* Note, we can have MAX_FIDS outstanding.  FIDs are 16-bits, so we</div><div class='del'>-	   use the high bit to mark whether it is in use. */</div><div class='del'>-#define MAX_FIDS 6</div><div class='del'>-#define MPI_MAX_FIDS 1</div><div class='del'>-	u32                           fids[MAX_FIDS];</div><div class='del'>-	ConfigRid config;</div><div class='del'>-	char keyindex; // Used with auto wep</div><div class='del'>-	char defindex; // Used with auto wep</div><div class='del'>-	struct proc_dir_entry *proc_entry;</div><div class='del'>-        spinlock_t aux_lock;</div><div class='del'>-#define FLAG_RADIO_OFF	0	/* User disabling of MAC */</div><div class='del'>-#define FLAG_RADIO_DOWN	1	/* ifup/ifdown disabling of MAC */</div><div class='del'>-#define FLAG_RADIO_MASK 0x03</div><div class='del'>-#define FLAG_ENABLED	2</div><div class='del'>-#define FLAG_ADHOC	3	/* Needed by MIC */</div><div class='del'>-#define FLAG_MIC_CAPABLE 4</div><div class='del'>-#define FLAG_UPDATE_MULTI 5</div><div class='del'>-#define FLAG_UPDATE_UNI 6</div><div class='del'>-#define FLAG_802_11	7</div><div class='del'>-#define FLAG_PROMISC	8	/* IFF_PROMISC 0x100 - include/linux/if.h */</div><div class='del'>-#define FLAG_PENDING_XMIT 9</div><div class='del'>-#define FLAG_PENDING_XMIT11 10</div><div class='del'>-#define FLAG_MPI	11</div><div class='del'>-#define FLAG_REGISTERED	12</div><div class='del'>-#define FLAG_COMMIT	13</div><div class='del'>-#define FLAG_RESET	14</div><div class='del'>-#define FLAG_FLASHING	15</div><div class='del'>-#define FLAG_WPA_CAPABLE	16</div><div class='del'>-	unsigned long flags;</div><div class='del'>-#define JOB_DIE	0</div><div class='del'>-#define JOB_XMIT	1</div><div class='del'>-#define JOB_XMIT11	2</div><div class='del'>-#define JOB_STATS	3</div><div class='del'>-#define JOB_PROMISC	4</div><div class='del'>-#define JOB_MIC	5</div><div class='del'>-#define JOB_EVENT	6</div><div class='del'>-#define JOB_AUTOWEP	7</div><div class='del'>-#define JOB_SCAN_RESULTS  9</div><div class='del'>-	unsigned long jobs;</div><div class='del'>-	int (*bap_read)(struct airo_info*, __le16 *pu16Dst, int bytelen,</div><div class='del'>-			int whichbap);</div><div class='del'>-	unsigned short *flash;</div><div class='del'>-	tdsRssiEntry *rssi;</div><div class='del'>-	struct task_struct *list_bss_task;</div><div class='del'>-	struct task_struct *airo_thread_task;</div><div class='del'>-	struct semaphore sem;</div><div class='del'>-	wait_queue_head_t thr_wait;</div><div class='del'>-	unsigned long expires;</div><div class='del'>-	struct {</div><div class='del'>-		struct sk_buff *skb;</div><div class='del'>-		int fid;</div><div class='del'>-	} xmit, xmit11;</div><div class='del'>-	struct net_device *wifidev;</div><div class='del'>-	struct iw_statistics	wstats;		// wireless stats</div><div class='del'>-	unsigned long		scan_timeout;	/* Time scan should be read */</div><div class='del'>-	struct iw_spy_data	spy_data;</div><div class='del'>-	struct iw_public_data	wireless_data;</div><div class='del'>-	/* MIC stuff */</div><div class='del'>-	struct crypto_sync_skcipher	*tfm;</div><div class='del'>-	mic_module		mod[2];</div><div class='del'>-	mic_statistics		micstats;</div><div class='del'>-	HostRxDesc rxfids[MPI_MAX_FIDS]; // rx/tx/config MPI350 descriptors</div><div class='del'>-	HostTxDesc txfids[MPI_MAX_FIDS];</div><div class='del'>-	HostRidDesc config_desc;</div><div class='del'>-	unsigned long ridbus; // phys addr of config_desc</div><div class='del'>-	struct sk_buff_head txq;// tx queue used by mpi350 code</div><div class='del'>-	struct pci_dev          *pci;</div><div class='del'>-	unsigned char		__iomem *pcimem;</div><div class='del'>-	unsigned char		__iomem *pciaux;</div><div class='del'>-	unsigned char		*shared;</div><div class='del'>-	dma_addr_t		shared_dma;</div><div class='del'>-	pm_message_t		power;</div><div class='del'>-	SsidRid			*SSID;</div><div class='del'>-	APListRid		APList;</div><div class='del'>-#define	PCI_SHARED_LEN		2*MPI_MAX_FIDS*PKTSIZE+RIDSIZE</div><div class='del'>-	char			proc_name[IFNAMSIZ];</div><div class='del'>-</div><div class='del'>-	int			wep_capable;</div><div class='del'>-	int			max_wep_idx;</div><div class='del'>-	int			last_auth;</div><div class='del'>-</div><div class='del'>-	/* WPA-related stuff */</div><div class='del'>-	unsigned int bssListFirst;</div><div class='del'>-	unsigned int bssListNext;</div><div class='del'>-	unsigned int bssListRidLen;</div><div class='del'>-</div><div class='del'>-	struct list_head network_list;</div><div class='del'>-	struct list_head network_free_list;</div><div class='del'>-	BSSListElement *networks;</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static inline int bap_read(struct airo_info *ai, __le16 *pu16Dst, int bytelen,</div><div class='del'>-			   int whichbap)</div><div class='del'>-{</div><div class='del'>-	return ai-&gt;bap_read(ai, pu16Dst, bytelen, whichbap);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int setup_proc_entry(struct net_device *dev,</div><div class='del'>-			     struct airo_info *apriv);</div><div class='del'>-static int takedown_proc_entry(struct net_device *dev,</div><div class='del'>-				struct airo_info *apriv);</div><div class='del'>-</div><div class='del'>-static int cmdreset(struct airo_info *ai);</div><div class='del'>-static int setflashmode(struct airo_info *ai);</div><div class='del'>-static int flashgchar(struct airo_info *ai, int matchbyte, int dwelltime);</div><div class='del'>-static int flashputbuf(struct airo_info *ai);</div><div class='del'>-static int flashrestart(struct airo_info *ai, struct net_device *dev);</div><div class='del'>-</div><div class='del'>-#define airo_print(type, name, fmt, args...) \</div><div class='del'>-	printk(type DRV_NAME "(%s): " fmt "\n", name, ##args)</div><div class='del'>-</div><div class='del'>-#define airo_print_info(name, fmt, args...) \</div><div class='del'>-	airo_print(KERN_INFO, name, fmt, ##args)</div><div class='del'>-</div><div class='del'>-#define airo_print_dbg(name, fmt, args...) \</div><div class='del'>-	airo_print(KERN_DEBUG, name, fmt, ##args)</div><div class='del'>-</div><div class='del'>-#define airo_print_warn(name, fmt, args...) \</div><div class='del'>-	airo_print(KERN_WARNING, name, fmt, ##args)</div><div class='del'>-</div><div class='del'>-#define airo_print_err(name, fmt, args...) \</div><div class='del'>-	airo_print(KERN_ERR, name, fmt, ##args)</div><div class='del'>-</div><div class='del'>-#define AIRO_FLASH(dev) (((struct airo_info *)dev-&gt;ml_priv)-&gt;flash)</div><div class='del'>-</div><div class='del'>-/***********************************************************************</div><div class='del'>- *                              MIC ROUTINES                           *</div><div class='del'>- ***********************************************************************</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static int RxSeqValid(struct airo_info *ai, miccntx *context, int mcast, u32 micSeq);</div><div class='del'>-static void MoveWindow(miccntx *context, u32 micSeq);</div><div class='del'>-static void emmh32_setseed(emmh32_context *context, u8 *pkey, int keylen,</div><div class='del'>-			   struct crypto_sync_skcipher *tfm);</div><div class='del'>-static void emmh32_init(emmh32_context *context);</div><div class='del'>-static void emmh32_update(emmh32_context *context, u8 *pOctets, int len);</div><div class='del'>-static void emmh32_final(emmh32_context *context, u8 digest[4]);</div><div class='del'>-static int flashpchar(struct airo_info *ai, int byte, int dwelltime);</div><div class='del'>-</div><div class='del'>-static void age_mic_context(miccntx *cur, miccntx *old, u8 *key, int key_len,</div><div class='del'>-			    struct crypto_sync_skcipher *tfm)</div><div class='del'>-{</div><div class='del'>-	/* If the current MIC context is valid and its key is the same as</div><div class='del'>-	 * the MIC register, there's nothing to do.</div><div class='del'>-	 */</div><div class='del'>-	if (cur-&gt;valid &amp;&amp; (memcmp(cur-&gt;key, key, key_len) == 0))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	/* Age current mic Context */</div><div class='del'>-	memcpy(old, cur, sizeof(*cur));</div><div class='del'>-</div><div class='del'>-	/* Initialize new context */</div><div class='del'>-	memcpy(cur-&gt;key, key, key_len);</div><div class='del'>-	cur-&gt;window  = 33; /* Window always points to the middle */</div><div class='del'>-	cur-&gt;rx      = 0;  /* Rx Sequence numbers */</div><div class='del'>-	cur-&gt;tx      = 0;  /* Tx sequence numbers */</div><div class='del'>-	cur-&gt;valid   = 1;  /* Key is now valid */</div><div class='del'>-</div><div class='del'>-	/* Give key to mic seed */</div><div class='del'>-	emmh32_setseed(&amp;cur-&gt;seed, key, key_len, tfm);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* micinit - Initialize mic seed */</div><div class='del'>-</div><div class='del'>-static void micinit(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	MICRid mic_rid;</div><div class='del'>-</div><div class='del'>-	clear_bit(JOB_MIC, &amp;ai-&gt;jobs);</div><div class='del'>-	PC4500_readrid(ai, RID_MIC, &amp;mic_rid, sizeof(mic_rid), 0);</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-</div><div class='del'>-	ai-&gt;micstats.enabled = (le16_to_cpu(mic_rid.state) &amp; 0x00FF) ? 1 : 0;</div><div class='del'>-	if (!ai-&gt;micstats.enabled) {</div><div class='del'>-		/* So next time we have a valid key and mic is enabled, we will</div><div class='del'>-		 * update the sequence number if the key is the same as before.</div><div class='del'>-		 */</div><div class='del'>-		ai-&gt;mod[0].uCtx.valid = 0;</div><div class='del'>-		ai-&gt;mod[0].mCtx.valid = 0;</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (mic_rid.multicastValid) {</div><div class='del'>-		age_mic_context(&amp;ai-&gt;mod[0].mCtx, &amp;ai-&gt;mod[1].mCtx,</div><div class='del'>-		                mic_rid.multicast, sizeof(mic_rid.multicast),</div><div class='del'>-		                ai-&gt;tfm);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (mic_rid.unicastValid) {</div><div class='del'>-		age_mic_context(&amp;ai-&gt;mod[0].uCtx, &amp;ai-&gt;mod[1].uCtx,</div><div class='del'>-				mic_rid.unicast, sizeof(mic_rid.unicast),</div><div class='del'>-				ai-&gt;tfm);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* micsetup - Get ready for business */</div><div class='del'>-</div><div class='del'>-static int micsetup(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (ai-&gt;tfm == NULL)</div><div class='del'>-		ai-&gt;tfm = crypto_alloc_sync_skcipher("ctr(aes)", 0, 0);</div><div class='del'>-</div><div class='del'>-        if (IS_ERR(ai-&gt;tfm)) {</div><div class='del'>-                airo_print_err(ai-&gt;dev-&gt;name, "failed to load transform for AES");</div><div class='del'>-                ai-&gt;tfm = NULL;</div><div class='del'>-                return ERROR;</div><div class='del'>-        }</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; NUM_MODULES; i++) {</div><div class='del'>-		memset(&amp;ai-&gt;mod[i].mCtx, 0, sizeof(miccntx));</div><div class='del'>-		memset(&amp;ai-&gt;mod[i].uCtx, 0, sizeof(miccntx));</div><div class='del'>-	}</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const u8 micsnap[] = {0xAA, 0xAA, 0x03, 0x00, 0x40, 0x96, 0x00, 0x02};</div><div class='del'>-</div><div class='del'>-/*===========================================================================</div><div class='del'>- * Description: Mic a packet</div><div class='del'>- *</div><div class='del'>- *      Inputs: etherHead * pointer to an 802.3 frame</div><div class='del'>- *</div><div class='del'>- *     Returns: BOOLEAN if successful, otherwise false.</div><div class='del'>- *             PacketTxLen will be updated with the mic'd packets size.</div><div class='del'>- *</div><div class='del'>- *    Caveats: It is assumed that the frame buffer will already</div><div class='del'>- *             be big enough to hold the largets mic message possible.</div><div class='del'>- *            (No memory allocation is done here).</div><div class='del'>- *</div><div class='del'>- *    Author: sbraneky (10/15/01)</div><div class='del'>- *    Merciless hacks by rwilcher (1/14/02)</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static int encapsulate(struct airo_info *ai, etherHead *frame, MICBuffer *mic, int payLen)</div><div class='del'>-{</div><div class='del'>-	miccntx   *context;</div><div class='del'>-</div><div class='del'>-	// Determine correct context</div><div class='del'>-	// If not adhoc, always use unicast key</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_ADHOC, &amp;ai-&gt;flags) &amp;&amp; (frame-&gt;da[0] &amp; 0x1))</div><div class='del'>-		context = &amp;ai-&gt;mod[0].mCtx;</div><div class='del'>-	else</div><div class='del'>-		context = &amp;ai-&gt;mod[0].uCtx;</div><div class='del'>-</div><div class='del'>-	if (!context-&gt;valid)</div><div class='del'>-		return ERROR;</div><div class='del'>-</div><div class='del'>-	mic-&gt;typelen = htons(payLen + 16); //Length of Mic'd packet</div><div class='del'>-</div><div class='del'>-	memcpy(&amp;mic-&gt;u.snap, micsnap, sizeof(micsnap)); // Add Snap</div><div class='del'>-</div><div class='del'>-	// Add Tx sequence</div><div class='del'>-	mic-&gt;seq = htonl(context-&gt;tx);</div><div class='del'>-	context-&gt;tx += 2;</div><div class='del'>-</div><div class='del'>-	emmh32_init(&amp;context-&gt;seed); // Mic the packet</div><div class='del'>-	emmh32_update(&amp;context-&gt;seed, frame-&gt;da, ETH_ALEN * 2); // DA, SA</div><div class='del'>-	emmh32_update(&amp;context-&gt;seed, (u8*)&amp;mic-&gt;typelen, 10); // Type/Length and Snap</div><div class='del'>-	emmh32_update(&amp;context-&gt;seed, (u8*)&amp;mic-&gt;seq, sizeof(mic-&gt;seq)); //SEQ</div><div class='del'>-	emmh32_update(&amp;context-&gt;seed, (u8*)(frame + 1), payLen); //payload</div><div class='del'>-	emmh32_final(&amp;context-&gt;seed, (u8*)&amp;mic-&gt;mic);</div><div class='del'>-</div><div class='del'>-	/*    New Type/length ?????????? */</div><div class='del'>-	mic-&gt;typelen = 0; //Let NIC know it could be an oversized packet</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-typedef enum {</div><div class='del'>-    NONE,</div><div class='del'>-    NOMIC,</div><div class='del'>-    NOMICPLUMMED,</div><div class='del'>-    SEQUENCE,</div><div class='del'>-    INCORRECTMIC,</div><div class='del'>-} mic_error;</div><div class='del'>-</div><div class='del'>-/*===========================================================================</div><div class='del'>- *  Description: Decapsulates a MIC'd packet and returns the 802.3 packet</div><div class='del'>- *               (removes the MIC stuff) if packet is a valid packet.</div><div class='del'>- *</div><div class='del'>- *       Inputs: etherHead  pointer to the 802.3 packet</div><div class='del'>- *</div><div class='del'>- *      Returns: BOOLEAN - TRUE if packet should be dropped otherwise FALSE</div><div class='del'>- *</div><div class='del'>- *      Author: sbraneky (10/15/01)</div><div class='del'>- *    Merciless hacks by rwilcher (1/14/02)</div><div class='del'>- *---------------------------------------------------------------------------</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *eth, u16 payLen)</div><div class='del'>-{</div><div class='del'>-	int      i;</div><div class='del'>-	u32      micSEQ;</div><div class='del'>-	miccntx  *context;</div><div class='del'>-	u8       digest[4];</div><div class='del'>-	mic_error micError = NONE;</div><div class='del'>-</div><div class='del'>-	// Check if the packet is a Mic'd packet</div><div class='del'>-</div><div class='del'>-	if (!ai-&gt;micstats.enabled) {</div><div class='del'>-		//No Mic set or Mic OFF but we received a MIC'd packet.</div><div class='del'>-		if (memcmp ((u8*)eth + 14, micsnap, sizeof(micsnap)) == 0) {</div><div class='del'>-			ai-&gt;micstats.rxMICPlummed++;</div><div class='del'>-			return ERROR;</div><div class='del'>-		}</div><div class='del'>-		return SUCCESS;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ntohs(mic-&gt;typelen) == 0x888E)</div><div class='del'>-		return SUCCESS;</div><div class='del'>-</div><div class='del'>-	if (memcmp (mic-&gt;u.snap, micsnap, sizeof(micsnap)) != 0) {</div><div class='del'>-	    // Mic enabled but packet isn't Mic'd</div><div class='del'>-		ai-&gt;micstats.rxMICPlummed++;</div><div class='del'>-	    	return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	micSEQ = ntohl(mic-&gt;seq);            //store SEQ as CPU order</div><div class='del'>-</div><div class='del'>-	//At this point we a have a mic'd packet and mic is enabled</div><div class='del'>-	//Now do the mic error checking.</div><div class='del'>-</div><div class='del'>-	//Receive seq must be odd</div><div class='del'>-	if ((micSEQ &amp; 1) == 0) {</div><div class='del'>-		ai-&gt;micstats.rxWrongSequence++;</div><div class='del'>-		return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; NUM_MODULES; i++) {</div><div class='del'>-		int mcast = eth-&gt;da[0] &amp; 1;</div><div class='del'>-		//Determine proper context</div><div class='del'>-		context = mcast ? &amp;ai-&gt;mod[i].mCtx : &amp;ai-&gt;mod[i].uCtx;</div><div class='del'>-</div><div class='del'>-		//Make sure context is valid</div><div class='del'>-		if (!context-&gt;valid) {</div><div class='del'>-			if (i == 0)</div><div class='del'>-				micError = NOMICPLUMMED;</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-		//DeMic it</div><div class='del'>-</div><div class='del'>-		if (!mic-&gt;typelen)</div><div class='del'>-			mic-&gt;typelen = htons(payLen + sizeof(MICBuffer) - 2);</div><div class='del'>-</div><div class='del'>-		emmh32_init(&amp;context-&gt;seed);</div><div class='del'>-		emmh32_update(&amp;context-&gt;seed, eth-&gt;da, ETH_ALEN*2);</div><div class='del'>-		emmh32_update(&amp;context-&gt;seed, (u8 *)&amp;mic-&gt;typelen, sizeof(mic-&gt;typelen)+sizeof(mic-&gt;u.snap));</div><div class='del'>-		emmh32_update(&amp;context-&gt;seed, (u8 *)&amp;mic-&gt;seq, sizeof(mic-&gt;seq));</div><div class='del'>-		emmh32_update(&amp;context-&gt;seed, (u8 *)(eth + 1), payLen);</div><div class='del'>-		//Calculate MIC</div><div class='del'>-		emmh32_final(&amp;context-&gt;seed, digest);</div><div class='del'>-</div><div class='del'>-		if (memcmp(digest, &amp;mic-&gt;mic, 4)) { //Make sure the mics match</div><div class='del'>-		  //Invalid Mic</div><div class='del'>-			if (i == 0)</div><div class='del'>-				micError = INCORRECTMIC;</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		//Check Sequence number if mics pass</div><div class='del'>-		if (RxSeqValid(ai, context, mcast, micSEQ) == SUCCESS) {</div><div class='del'>-			ai-&gt;micstats.rxSuccess++;</div><div class='del'>-			return SUCCESS;</div><div class='del'>-		}</div><div class='del'>-		if (i == 0)</div><div class='del'>-			micError = SEQUENCE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	// Update statistics</div><div class='del'>-	switch (micError) {</div><div class='del'>-		case NOMICPLUMMED: ai-&gt;micstats.rxMICPlummed++;   break;</div><div class='del'>-		case SEQUENCE:    ai-&gt;micstats.rxWrongSequence++; break;</div><div class='del'>-		case INCORRECTMIC: ai-&gt;micstats.rxIncorrectMIC++; break;</div><div class='del'>-		case NONE:  break;</div><div class='del'>-		case NOMIC: break;</div><div class='del'>-	}</div><div class='del'>-	return ERROR;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*===========================================================================</div><div class='del'>- * Description:  Checks the Rx Seq number to make sure it is valid</div><div class='del'>- *               and hasn't already been received</div><div class='del'>- *</div><div class='del'>- *     Inputs: miccntx - mic context to check seq against</div><div class='del'>- *             micSeq  - the Mic seq number</div><div class='del'>- *</div><div class='del'>- *    Returns: TRUE if valid otherwise FALSE.</div><div class='del'>- *</div><div class='del'>- *    Author: sbraneky (10/15/01)</div><div class='del'>- *    Merciless hacks by rwilcher (1/14/02)</div><div class='del'>- *---------------------------------------------------------------------------</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static int RxSeqValid(struct airo_info *ai, miccntx *context, int mcast, u32 micSeq)</div><div class='del'>-{</div><div class='del'>-	u32 seq, index;</div><div class='del'>-</div><div class='del'>-	//Allow for the ap being rebooted - if it is then use the next</div><div class='del'>-	//sequence number of the current sequence number - might go backwards</div><div class='del'>-</div><div class='del'>-	if (mcast) {</div><div class='del'>-		if (test_bit(FLAG_UPDATE_MULTI, &amp;ai-&gt;flags)) {</div><div class='del'>-			clear_bit (FLAG_UPDATE_MULTI, &amp;ai-&gt;flags);</div><div class='del'>-			context-&gt;window = (micSeq &gt; 33) ? micSeq : 33;</div><div class='del'>-			context-&gt;rx     = 0;        // Reset rx</div><div class='del'>-		}</div><div class='del'>-	} else if (test_bit(FLAG_UPDATE_UNI, &amp;ai-&gt;flags)) {</div><div class='del'>-		clear_bit (FLAG_UPDATE_UNI, &amp;ai-&gt;flags);</div><div class='del'>-		context-&gt;window = (micSeq &gt; 33) ? micSeq : 33; // Move window</div><div class='del'>-		context-&gt;rx     = 0;        // Reset rx</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	//Make sequence number relative to START of window</div><div class='del'>-	seq = micSeq - (context-&gt;window - 33);</div><div class='del'>-</div><div class='del'>-	//Too old of a SEQ number to check.</div><div class='del'>-	if ((s32)seq &lt; 0)</div><div class='del'>-		return ERROR;</div><div class='del'>-</div><div class='del'>-	if (seq &gt; 64) {</div><div class='del'>-		//Window is infinite forward</div><div class='del'>-		MoveWindow(context, micSeq);</div><div class='del'>-		return SUCCESS;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	// We are in the window. Now check the context rx bit to see if it was already sent</div><div class='del'>-	seq &gt;&gt;= 1;         //divide by 2 because we only have odd numbers</div><div class='del'>-	index = 1 &lt;&lt; seq;  //Get an index number</div><div class='del'>-</div><div class='del'>-	if (!(context-&gt;rx &amp; index)) {</div><div class='del'>-		//micSEQ falls inside the window.</div><div class='del'>-		//Add seqence number to the list of received numbers.</div><div class='del'>-		context-&gt;rx |= index;</div><div class='del'>-</div><div class='del'>-		MoveWindow(context, micSeq);</div><div class='del'>-</div><div class='del'>-		return SUCCESS;</div><div class='del'>-	}</div><div class='del'>-	return ERROR;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void MoveWindow(miccntx *context, u32 micSeq)</div><div class='del'>-{</div><div class='del'>-	u32 shift;</div><div class='del'>-</div><div class='del'>-	//Move window if seq greater than the middle of the window</div><div class='del'>-	if (micSeq &gt; context-&gt;window) {</div><div class='del'>-		shift = (micSeq - context-&gt;window) &gt;&gt; 1;</div><div class='del'>-</div><div class='del'>-		    //Shift out old</div><div class='del'>-		if (shift &lt; 32)</div><div class='del'>-			context-&gt;rx &gt;&gt;= shift;</div><div class='del'>-		else</div><div class='del'>-			context-&gt;rx = 0;</div><div class='del'>-</div><div class='del'>-		context-&gt;window = micSeq;      //Move window</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*==============================================*/</div><div class='del'>-/*========== EMMH ROUTINES  ====================*/</div><div class='del'>-/*==============================================*/</div><div class='del'>-</div><div class='del'>-/* mic accumulate */</div><div class='del'>-#define MIC_ACCUM(val)	\</div><div class='del'>-	context-&gt;accum += (u64)(val) * be32_to_cpu(context-&gt;coeff[coeff_position++]);</div><div class='del'>-</div><div class='del'>-/* expand the key to fill the MMH coefficient array */</div><div class='del'>-static void emmh32_setseed(emmh32_context *context, u8 *pkey, int keylen,</div><div class='del'>-			   struct crypto_sync_skcipher *tfm)</div><div class='del'>-{</div><div class='del'>-  /* take the keying material, expand if necessary, truncate at 16-bytes */</div><div class='del'>-  /* run through AES counter mode to generate context-&gt;coeff[] */</div><div class='del'>-</div><div class='del'>-	SYNC_SKCIPHER_REQUEST_ON_STACK(req, tfm);</div><div class='del'>-	struct scatterlist sg;</div><div class='del'>-	u8 iv[AES_BLOCK_SIZE] = {};</div><div class='del'>-	int ret;</div><div class='del'>-</div><div class='del'>-	crypto_sync_skcipher_setkey(tfm, pkey, 16);</div><div class='del'>-</div><div class='del'>-	memset(context-&gt;coeff, 0, sizeof(context-&gt;coeff));</div><div class='del'>-	sg_init_one(&amp;sg, context-&gt;coeff, sizeof(context-&gt;coeff));</div><div class='del'>-</div><div class='del'>-	skcipher_request_set_sync_tfm(req, tfm);</div><div class='del'>-	skcipher_request_set_callback(req, 0, NULL, NULL);</div><div class='del'>-	skcipher_request_set_crypt(req, &amp;sg, &amp;sg, sizeof(context-&gt;coeff), iv);</div><div class='del'>-</div><div class='del'>-	ret = crypto_skcipher_encrypt(req);</div><div class='del'>-	WARN_ON_ONCE(ret);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* prepare for calculation of a new mic */</div><div class='del'>-static void emmh32_init(emmh32_context *context)</div><div class='del'>-{</div><div class='del'>-	/* prepare for new mic calculation */</div><div class='del'>-	context-&gt;accum = 0;</div><div class='del'>-	context-&gt;position = 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* add some bytes to the mic calculation */</div><div class='del'>-static void emmh32_update(emmh32_context *context, u8 *pOctets, int len)</div><div class='del'>-{</div><div class='del'>-	int	coeff_position, byte_position;</div><div class='del'>-</div><div class='del'>-	if (len == 0) return;</div><div class='del'>-</div><div class='del'>-	coeff_position = context-&gt;position &gt;&gt; 2;</div><div class='del'>-</div><div class='del'>-	/* deal with partial 32-bit word left over from last update */</div><div class='del'>-	byte_position = context-&gt;position &amp; 3;</div><div class='del'>-	if (byte_position) {</div><div class='del'>-		/* have a partial word in part to deal with */</div><div class='del'>-		do {</div><div class='del'>-			if (len == 0) return;</div><div class='del'>-			context-&gt;part.d8[byte_position++] = *pOctets++;</div><div class='del'>-			context-&gt;position++;</div><div class='del'>-			len--;</div><div class='del'>-		} while (byte_position &lt; 4);</div><div class='del'>-		MIC_ACCUM(ntohl(context-&gt;part.d32));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* deal with full 32-bit words */</div><div class='del'>-	while (len &gt;= 4) {</div><div class='del'>-		MIC_ACCUM(ntohl(*(__be32 *)pOctets));</div><div class='del'>-		context-&gt;position += 4;</div><div class='del'>-		pOctets += 4;</div><div class='del'>-		len -= 4;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* deal with partial 32-bit word that will be left over from this update */</div><div class='del'>-	byte_position = 0;</div><div class='del'>-	while (len &gt; 0) {</div><div class='del'>-		context-&gt;part.d8[byte_position++] = *pOctets++;</div><div class='del'>-		context-&gt;position++;</div><div class='del'>-		len--;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* mask used to zero empty bytes for final partial word */</div><div class='del'>-static u32 mask32[4] = { 0x00000000L, 0xFF000000L, 0xFFFF0000L, 0xFFFFFF00L };</div><div class='del'>-</div><div class='del'>-/* calculate the mic */</div><div class='del'>-static void emmh32_final(emmh32_context *context, u8 digest[4])</div><div class='del'>-{</div><div class='del'>-	int	coeff_position, byte_position;</div><div class='del'>-	u32	val;</div><div class='del'>-</div><div class='del'>-	u64 sum, utmp;</div><div class='del'>-	s64 stmp;</div><div class='del'>-</div><div class='del'>-	coeff_position = context-&gt;position &gt;&gt; 2;</div><div class='del'>-</div><div class='del'>-	/* deal with partial 32-bit word left over from last update */</div><div class='del'>-	byte_position = context-&gt;position &amp; 3;</div><div class='del'>-	if (byte_position) {</div><div class='del'>-		/* have a partial word in part to deal with */</div><div class='del'>-		val = ntohl(context-&gt;part.d32);</div><div class='del'>-		MIC_ACCUM(val &amp; mask32[byte_position]);	/* zero empty bytes */</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* reduce the accumulated u64 to a 32-bit MIC */</div><div class='del'>-	sum = context-&gt;accum;</div><div class='del'>-	stmp = (sum  &amp; 0xffffffffLL) - ((sum &gt;&gt; 32)  * 15);</div><div class='del'>-	utmp = (stmp &amp; 0xffffffffLL) - ((stmp &gt;&gt; 32) * 15);</div><div class='del'>-	sum = utmp &amp; 0xffffffffLL;</div><div class='del'>-	if (utmp &gt; 0x10000000fLL)</div><div class='del'>-		sum -= 15;</div><div class='del'>-</div><div class='del'>-	val = (u32)sum;</div><div class='del'>-	digest[0] = (val&gt;&gt;24) &amp; 0xFF;</div><div class='del'>-	digest[1] = (val&gt;&gt;16) &amp; 0xFF;</div><div class='del'>-	digest[2] = (val&gt;&gt;8) &amp; 0xFF;</div><div class='del'>-	digest[3] = val &amp; 0xFF;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readBSSListRid(struct airo_info *ai, int first,</div><div class='del'>-		      BSSListRid *list)</div><div class='del'>-{</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-</div><div class='del'>-	if (first == 1) {</div><div class='del'>-		if (ai-&gt;flags &amp; FLAG_RADIO_MASK) return -ENETDOWN;</div><div class='del'>-		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-		cmd.cmd = CMD_LISTBSS;</div><div class='del'>-		if (down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-			return -ERESTARTSYS;</div><div class='del'>-		ai-&gt;list_bss_task = current;</div><div class='del'>-		issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-		/* Let the command take effect */</div><div class='del'>-		schedule_timeout_uninterruptible(3 * HZ);</div><div class='del'>-		ai-&gt;list_bss_task = NULL;</div><div class='del'>-	}</div><div class='del'>-	return PC4500_readrid(ai, first ? ai-&gt;bssListFirst : ai-&gt;bssListNext,</div><div class='del'>-			    list, ai-&gt;bssListRidLen, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readWepKeyRid(struct airo_info *ai, WepKeyRid *wkr, int temp, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_readrid(ai, temp ? RID_WEP_TEMP : RID_WEP_PERM,</div><div class='del'>-				wkr, sizeof(*wkr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int writeWepKeyRid(struct airo_info *ai, WepKeyRid *wkr, int perm, int lock)</div><div class='del'>-{</div><div class='del'>-	int rc;</div><div class='del'>-	rc = PC4500_writerid(ai, RID_WEP_TEMP, wkr, sizeof(*wkr), lock);</div><div class='del'>-	if (rc!=SUCCESS)</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "WEP_TEMP set %x", rc);</div><div class='del'>-	if (perm) {</div><div class='del'>-		rc = PC4500_writerid(ai, RID_WEP_PERM, wkr, sizeof(*wkr), lock);</div><div class='del'>-		if (rc!=SUCCESS)</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name, "WEP_PERM set %x", rc);</div><div class='del'>-	}</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readSsidRid(struct airo_info*ai, SsidRid *ssidr)</div><div class='del'>-{</div><div class='del'>-	return PC4500_readrid(ai, RID_SSID, ssidr, sizeof(*ssidr), 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int writeSsidRid(struct airo_info*ai, SsidRid *pssidr, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_writerid(ai, RID_SSID, pssidr, sizeof(*pssidr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readConfigRid(struct airo_info *ai, int lock)</div><div class='del'>-{</div><div class='del'>-	int rc;</div><div class='del'>-	ConfigRid cfg;</div><div class='del'>-</div><div class='del'>-	if (ai-&gt;config.len)</div><div class='del'>-		return SUCCESS;</div><div class='del'>-</div><div class='del'>-	rc = PC4500_readrid(ai, RID_ACTUALCONFIG, &amp;cfg, sizeof(cfg), lock);</div><div class='del'>-	if (rc != SUCCESS)</div><div class='del'>-		return rc;</div><div class='del'>-</div><div class='del'>-	ai-&gt;config = cfg;</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void checkThrottle(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-/* Old hardware had a limit on encryption speed */</div><div class='del'>-	if (ai-&gt;config.authType != AUTH_OPEN &amp;&amp; maxencrypt) {</div><div class='del'>-		for (i = 0; i&lt;8; i++) {</div><div class='del'>-			if (ai-&gt;config.rates[i] &gt; maxencrypt) {</div><div class='del'>-				ai-&gt;config.rates[i] = 0;</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int writeConfigRid(struct airo_info *ai, int lock)</div><div class='del'>-{</div><div class='del'>-	ConfigRid cfgr;</div><div class='del'>-</div><div class='del'>-	if (!test_bit (FLAG_COMMIT, &amp;ai-&gt;flags))</div><div class='del'>-		return SUCCESS;</div><div class='del'>-</div><div class='del'>-	clear_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-	clear_bit (FLAG_RESET, &amp;ai-&gt;flags);</div><div class='del'>-	checkThrottle(ai);</div><div class='del'>-	cfgr = ai-&gt;config;</div><div class='del'>-</div><div class='del'>-	if ((cfgr.opmode &amp; MODE_CFG_MASK) == MODE_STA_IBSS)</div><div class='del'>-		set_bit(FLAG_ADHOC, &amp;ai-&gt;flags);</div><div class='del'>-	else</div><div class='del'>-		clear_bit(FLAG_ADHOC, &amp;ai-&gt;flags);</div><div class='del'>-</div><div class='del'>-	return PC4500_writerid(ai, RID_CONFIG, &amp;cfgr, sizeof(cfgr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readStatusRid(struct airo_info *ai, StatusRid *statr, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_readrid(ai, RID_STATUS, statr, sizeof(*statr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int writeAPListRid(struct airo_info *ai, APListRid *aplr, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_writerid(ai, RID_APLIST, aplr, sizeof(*aplr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readCapabilityRid(struct airo_info *ai, CapabilityRid *capr, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_readrid(ai, RID_CAPABILITIES, capr, sizeof(*capr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int readStatsRid(struct airo_info*ai, StatsRid *sr, int rid, int lock)</div><div class='del'>-{</div><div class='del'>-	return PC4500_readrid(ai, rid, sr, sizeof(*sr), lock);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void try_auto_wep(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	if (auto_wep &amp;&amp; !test_bit(FLAG_RADIO_DOWN, &amp;ai-&gt;flags)) {</div><div class='del'>-		ai-&gt;expires = RUN_AT(3*HZ);</div><div class='del'>-		wake_up_interruptible(&amp;ai-&gt;thr_wait);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int airo_open(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int rc = 0;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_FLASHING, &amp;ai-&gt;flags))</div><div class='del'>-		return -EIO;</div><div class='del'>-</div><div class='del'>-	/* Make sure the card is configured.</div><div class='del'>-	 * Wireless Extensions may postpone config changes until the card</div><div class='del'>-	 * is open (to pipeline changes and speed-up card setup). If</div><div class='del'>-	 * those changes are not yet committed, do it now - Jean II */</div><div class='del'>-	if (test_bit(FLAG_COMMIT, &amp;ai-&gt;flags)) {</div><div class='del'>-		disable_MAC(ai, 1);</div><div class='del'>-		writeConfigRid(ai, 1);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (ai-&gt;wifidev != dev) {</div><div class='del'>-		clear_bit(JOB_DIE, &amp;ai-&gt;jobs);</div><div class='del'>-		ai-&gt;airo_thread_task = kthread_run(airo_thread, dev, "%s",</div><div class='del'>-						   dev-&gt;name);</div><div class='del'>-		if (IS_ERR(ai-&gt;airo_thread_task))</div><div class='del'>-			return (int)PTR_ERR(ai-&gt;airo_thread_task);</div><div class='del'>-</div><div class='del'>-		rc = request_irq(dev-&gt;irq, airo_interrupt, IRQF_SHARED,</div><div class='del'>-			dev-&gt;name, dev);</div><div class='del'>-		if (rc) {</div><div class='del'>-			airo_print_err(dev-&gt;name,</div><div class='del'>-				"register interrupt %d failed, rc %d",</div><div class='del'>-				dev-&gt;irq, rc);</div><div class='del'>-			set_bit(JOB_DIE, &amp;ai-&gt;jobs);</div><div class='del'>-			kthread_stop(ai-&gt;airo_thread_task);</div><div class='del'>-			return rc;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Power on the MAC controller (which may have been disabled) */</div><div class='del'>-		clear_bit(FLAG_RADIO_DOWN, &amp;ai-&gt;flags);</div><div class='del'>-		enable_interrupts(ai);</div><div class='del'>-</div><div class='del'>-		try_auto_wep(ai);</div><div class='del'>-	}</div><div class='del'>-	enable_MAC(ai, 1);</div><div class='del'>-</div><div class='del'>-	netif_start_queue(dev);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static netdev_tx_t mpi_start_xmit(struct sk_buff *skb,</div><div class='del'>-					struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	int npacks, pending;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	if (!skb) {</div><div class='del'>-		airo_print_err(dev-&gt;name, "%s: skb == NULL!",__func__);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-	if (skb_padto(skb, ETH_ZLEN)) {</div><div class='del'>-		dev-&gt;stats.tx_dropped++;</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-	npacks = skb_queue_len (&amp;ai-&gt;txq);</div><div class='del'>-</div><div class='del'>-	if (npacks &gt;= MAXTXQ - 1) {</div><div class='del'>-		netif_stop_queue (dev);</div><div class='del'>-		if (npacks &gt; MAXTXQ) {</div><div class='del'>-			dev-&gt;stats.tx_fifo_errors++;</div><div class='del'>-			return NETDEV_TX_BUSY;</div><div class='del'>-		}</div><div class='del'>-		skb_queue_tail (&amp;ai-&gt;txq, skb);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-	skb_queue_tail (&amp;ai-&gt;txq, skb);</div><div class='del'>-	pending = test_bit(FLAG_PENDING_XMIT, &amp;ai-&gt;flags);</div><div class='del'>-	spin_unlock_irqrestore(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-	netif_wake_queue (dev);</div><div class='del'>-</div><div class='del'>-	if (pending == 0) {</div><div class='del'>-		set_bit(FLAG_PENDING_XMIT, &amp;ai-&gt;flags);</div><div class='del'>-		mpi_send_packet (dev);</div><div class='del'>-	}</div><div class='del'>-	return NETDEV_TX_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * @mpi_send_packet</div><div class='del'>- *</div><div class='del'>- * Attempt to transmit a packet. Can be called from interrupt</div><div class='del'>- * or transmit . return number of packets we tried to send</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static int mpi_send_packet (struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct sk_buff *skb;</div><div class='del'>-	unsigned char *buffer;</div><div class='del'>-	s16 len;</div><div class='del'>-	__le16 *payloadLen;</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	u8 *sendbuf;</div><div class='del'>-</div><div class='del'>-	/* get a packet to send */</div><div class='del'>-</div><div class='del'>-	if ((skb = skb_dequeue(&amp;ai-&gt;txq)) == NULL) {</div><div class='del'>-		airo_print_err(dev-&gt;name,</div><div class='del'>-			"%s: Dequeue'd zero in send_packet()",</div><div class='del'>-			__func__);</div><div class='del'>-		return 0;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* check min length*/</div><div class='del'>-	len = ETH_ZLEN &lt; skb-&gt;len ? skb-&gt;len : ETH_ZLEN;</div><div class='del'>-	buffer = skb-&gt;data;</div><div class='del'>-</div><div class='del'>-	ai-&gt;txfids[0].tx_desc.offset = 0;</div><div class='del'>-	ai-&gt;txfids[0].tx_desc.valid = 1;</div><div class='del'>-	ai-&gt;txfids[0].tx_desc.eoc = 1;</div><div class='del'>-	ai-&gt;txfids[0].tx_desc.len =len+sizeof(WifiHdr);</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * Magic, the cards firmware needs a length count (2 bytes) in the host buffer</div><div class='del'>- * right after  TXFID_HDR.The TXFID_HDR contains the status short so payloadlen</div><div class='del'>- * is immediately after it. ------------------------------------------------</div><div class='del'>- *                         |TXFIDHDR+STATUS|PAYLOADLEN|802.3HDR|PACKETDATA|</div><div class='del'>- *                         ------------------------------------------------</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-	memcpy(ai-&gt;txfids[0].virtual_host_addr,</div><div class='del'>-		(char *)&amp;wifictlhdr8023, sizeof(wifictlhdr8023));</div><div class='del'>-</div><div class='del'>-	payloadLen = (__le16 *)(ai-&gt;txfids[0].virtual_host_addr +</div><div class='del'>-		sizeof(wifictlhdr8023));</div><div class='del'>-	sendbuf = ai-&gt;txfids[0].virtual_host_addr +</div><div class='del'>-		sizeof(wifictlhdr8023) + 2 ;</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Firmware automatically puts 802 header on so</div><div class='del'>-	 * we don't need to account for it in the length</div><div class='del'>-	 */</div><div class='del'>-	if (test_bit(FLAG_MIC_CAPABLE, &amp;ai-&gt;flags) &amp;&amp; ai-&gt;micstats.enabled &amp;&amp;</div><div class='del'>-		(ntohs(((__be16 *)buffer)[6]) != 0x888E)) {</div><div class='del'>-		MICBuffer pMic;</div><div class='del'>-</div><div class='del'>-		if (encapsulate(ai, (etherHead *)buffer, &amp;pMic, len - sizeof(etherHead)) != SUCCESS)</div><div class='del'>-			return ERROR;</div><div class='del'>-</div><div class='del'>-		*payloadLen = cpu_to_le16(len-sizeof(etherHead)+sizeof(pMic));</div><div class='del'>-		ai-&gt;txfids[0].tx_desc.len += sizeof(pMic);</div><div class='del'>-		/* copy data into airo dma buffer */</div><div class='del'>-		memcpy (sendbuf, buffer, sizeof(etherHead));</div><div class='del'>-		buffer += sizeof(etherHead);</div><div class='del'>-		sendbuf += sizeof(etherHead);</div><div class='del'>-		memcpy (sendbuf, &amp;pMic, sizeof(pMic));</div><div class='del'>-		sendbuf += sizeof(pMic);</div><div class='del'>-		memcpy (sendbuf, buffer, len - sizeof(etherHead));</div><div class='del'>-	} else {</div><div class='del'>-		*payloadLen = cpu_to_le16(len - sizeof(etherHead));</div><div class='del'>-</div><div class='del'>-		netif_trans_update(dev);</div><div class='del'>-</div><div class='del'>-		/* copy data into airo dma buffer */</div><div class='del'>-		memcpy(sendbuf, buffer, len);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memcpy_toio(ai-&gt;txfids[0].card_ram_off,</div><div class='del'>-		&amp;ai-&gt;txfids[0].tx_desc, sizeof(TxFid));</div><div class='del'>-</div><div class='del'>-	OUT4500(ai, EVACK, 8);</div><div class='del'>-</div><div class='del'>-	dev_kfree_skb_any(skb);</div><div class='del'>-	return 1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void get_tx_error(struct airo_info *ai, s32 fid)</div><div class='del'>-{</div><div class='del'>-	__le16 status;</div><div class='del'>-</div><div class='del'>-	if (fid &lt; 0)</div><div class='del'>-		status = ((WifiCtlHdr *)ai-&gt;txfids[0].virtual_host_addr)-&gt;ctlhdr.status;</div><div class='del'>-	else {</div><div class='del'>-		if (bap_setup(ai, ai-&gt;fids[fid] &amp; 0xffff, 4, BAP0) != SUCCESS)</div><div class='del'>-			return;</div><div class='del'>-		bap_read(ai, &amp;status, 2, BAP0);</div><div class='del'>-	}</div><div class='del'>-	if (le16_to_cpu(status) &amp; 2) /* Too many retries */</div><div class='del'>-		ai-&gt;dev-&gt;stats.tx_aborted_errors++;</div><div class='del'>-	if (le16_to_cpu(status) &amp; 4) /* Transmit lifetime exceeded */</div><div class='del'>-		ai-&gt;dev-&gt;stats.tx_heartbeat_errors++;</div><div class='del'>-	if (le16_to_cpu(status) &amp; 8) /* Aid fail */</div><div class='del'>-		{ }</div><div class='del'>-	if (le16_to_cpu(status) &amp; 0x10) /* MAC disabled */</div><div class='del'>-		ai-&gt;dev-&gt;stats.tx_carrier_errors++;</div><div class='del'>-	if (le16_to_cpu(status) &amp; 0x20) /* Association lost */</div><div class='del'>-		{ }</div><div class='del'>-	/* We produce a TXDROP event only for retry or lifetime</div><div class='del'>-	 * exceeded, because that's the only status that really mean</div><div class='del'>-	 * that this particular node went away.</div><div class='del'>-	 * Other errors means that *we* screwed up. - Jean II */</div><div class='del'>-	if ((le16_to_cpu(status) &amp; 2) ||</div><div class='del'>-	     (le16_to_cpu(status) &amp; 4)) {</div><div class='del'>-		union iwreq_data	wrqu;</div><div class='del'>-		char junk[0x18];</div><div class='del'>-</div><div class='del'>-		/* Faster to skip over useless data than to do</div><div class='del'>-		 * another bap_setup(). We are at offset 0x6 and</div><div class='del'>-		 * need to go to 0x18 and read 6 bytes - Jean II */</div><div class='del'>-		bap_read(ai, (__le16 *) junk, 0x18, BAP0);</div><div class='del'>-</div><div class='del'>-		/* Copy 802.11 dest address.</div><div class='del'>-		 * We use the 802.11 header because the frame may</div><div class='del'>-		 * not be 802.3 or may be mangled...</div><div class='del'>-		 * In Ad-Hoc mode, it will be the node address.</div><div class='del'>-		 * In managed mode, it will be most likely the AP addr</div><div class='del'>-		 * User space will figure out how to convert it to</div><div class='del'>-		 * whatever it needs (IP address or else).</div><div class='del'>-		 * - Jean II */</div><div class='del'>-		memcpy(wrqu.addr.sa_data, junk + 0x12, ETH_ALEN);</div><div class='del'>-		wrqu.addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-</div><div class='del'>-		/* Send event to user space */</div><div class='del'>-		wireless_send_event(ai-&gt;dev, IWEVTXDROP, &amp;wrqu, NULL);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_end_xmit(struct net_device *dev, bool may_sleep)</div><div class='del'>-{</div><div class='del'>-	u16 status;</div><div class='del'>-	int i;</div><div class='del'>-	struct airo_info *priv = dev-&gt;ml_priv;</div><div class='del'>-	struct sk_buff *skb = priv-&gt;xmit.skb;</div><div class='del'>-	int fid = priv-&gt;xmit.fid;</div><div class='del'>-	u32 *fids = priv-&gt;fids;</div><div class='del'>-</div><div class='del'>-	clear_bit(JOB_XMIT, &amp;priv-&gt;jobs);</div><div class='del'>-	clear_bit(FLAG_PENDING_XMIT, &amp;priv-&gt;flags);</div><div class='del'>-	status = transmit_802_3_packet(priv, fids[fid], skb-&gt;data, may_sleep);</div><div class='del'>-	up(&amp;priv-&gt;sem);</div><div class='del'>-</div><div class='del'>-	i = 0;</div><div class='del'>-	if (status == SUCCESS) {</div><div class='del'>-		netif_trans_update(dev);</div><div class='del'>-		for (; i &lt; MAX_FIDS / 2 &amp;&amp; (priv-&gt;fids[i] &amp; 0xffff0000); i++);</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;fids[fid] &amp;= 0xffff;</div><div class='del'>-		dev-&gt;stats.tx_window_errors++;</div><div class='del'>-	}</div><div class='del'>-	if (i &lt; MAX_FIDS / 2)</div><div class='del'>-		netif_wake_queue(dev);</div><div class='del'>-	dev_kfree_skb(skb);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static netdev_tx_t airo_start_xmit(struct sk_buff *skb,</div><div class='del'>-					 struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	s16 len;</div><div class='del'>-	int i, j;</div><div class='del'>-	struct airo_info *priv = dev-&gt;ml_priv;</div><div class='del'>-	u32 *fids = priv-&gt;fids;</div><div class='del'>-</div><div class='del'>-	if (skb == NULL) {</div><div class='del'>-		airo_print_err(dev-&gt;name, "%s: skb == NULL!", __func__);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-	if (skb_padto(skb, ETH_ZLEN)) {</div><div class='del'>-		dev-&gt;stats.tx_dropped++;</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Find a vacant FID */</div><div class='del'>-	for (i = 0; i &lt; MAX_FIDS / 2 &amp;&amp; (fids[i] &amp; 0xffff0000); i++);</div><div class='del'>-	for (j = i + 1; j &lt; MAX_FIDS / 2 &amp;&amp; (fids[j] &amp; 0xffff0000); j++);</div><div class='del'>-</div><div class='del'>-	if (j &gt;= MAX_FIDS / 2) {</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-</div><div class='del'>-		if (i == MAX_FIDS / 2) {</div><div class='del'>-			dev-&gt;stats.tx_fifo_errors++;</div><div class='del'>-			return NETDEV_TX_BUSY;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	/* check min length*/</div><div class='del'>-	len = ETH_ZLEN &lt; skb-&gt;len ? skb-&gt;len : ETH_ZLEN;</div><div class='del'>-        /* Mark fid as used &amp; save length for later */</div><div class='del'>-	fids[i] |= (len &lt;&lt; 16);</div><div class='del'>-	priv-&gt;xmit.skb = skb;</div><div class='del'>-	priv-&gt;xmit.fid = i;</div><div class='del'>-	if (down_trylock(&amp;priv-&gt;sem) != 0) {</div><div class='del'>-		set_bit(FLAG_PENDING_XMIT, &amp;priv-&gt;flags);</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-		set_bit(JOB_XMIT, &amp;priv-&gt;jobs);</div><div class='del'>-		wake_up_interruptible(&amp;priv-&gt;thr_wait);</div><div class='del'>-	} else</div><div class='del'>-		airo_end_xmit(dev, false);</div><div class='del'>-	return NETDEV_TX_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_end_xmit11(struct net_device *dev, bool may_sleep)</div><div class='del'>-{</div><div class='del'>-	u16 status;</div><div class='del'>-	int i;</div><div class='del'>-	struct airo_info *priv = dev-&gt;ml_priv;</div><div class='del'>-	struct sk_buff *skb = priv-&gt;xmit11.skb;</div><div class='del'>-	int fid = priv-&gt;xmit11.fid;</div><div class='del'>-	u32 *fids = priv-&gt;fids;</div><div class='del'>-</div><div class='del'>-	clear_bit(JOB_XMIT11, &amp;priv-&gt;jobs);</div><div class='del'>-	clear_bit(FLAG_PENDING_XMIT11, &amp;priv-&gt;flags);</div><div class='del'>-	status = transmit_802_11_packet(priv, fids[fid], skb-&gt;data, may_sleep);</div><div class='del'>-	up(&amp;priv-&gt;sem);</div><div class='del'>-</div><div class='del'>-	i = MAX_FIDS / 2;</div><div class='del'>-	if (status == SUCCESS) {</div><div class='del'>-		netif_trans_update(dev);</div><div class='del'>-		for (; i &lt; MAX_FIDS &amp;&amp; (priv-&gt;fids[i] &amp; 0xffff0000); i++);</div><div class='del'>-	} else {</div><div class='del'>-		priv-&gt;fids[fid] &amp;= 0xffff;</div><div class='del'>-		dev-&gt;stats.tx_window_errors++;</div><div class='del'>-	}</div><div class='del'>-	if (i &lt; MAX_FIDS)</div><div class='del'>-		netif_wake_queue(dev);</div><div class='del'>-	dev_kfree_skb(skb);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static netdev_tx_t airo_start_xmit11(struct sk_buff *skb,</div><div class='del'>-					   struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	s16 len;</div><div class='del'>-	int i, j;</div><div class='del'>-	struct airo_info *priv = dev-&gt;ml_priv;</div><div class='del'>-	u32 *fids = priv-&gt;fids;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MPI, &amp;priv-&gt;flags)) {</div><div class='del'>-		/* Not implemented yet for MPI350 */</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-		dev_kfree_skb_any(skb);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (skb == NULL) {</div><div class='del'>-		airo_print_err(dev-&gt;name, "%s: skb == NULL!", __func__);</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-	if (skb_padto(skb, ETH_ZLEN)) {</div><div class='del'>-		dev-&gt;stats.tx_dropped++;</div><div class='del'>-		return NETDEV_TX_OK;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Find a vacant FID */</div><div class='del'>-	for (i = MAX_FIDS / 2; i &lt; MAX_FIDS &amp;&amp; (fids[i] &amp; 0xffff0000); i++);</div><div class='del'>-	for (j = i + 1; j &lt; MAX_FIDS &amp;&amp; (fids[j] &amp; 0xffff0000); j++);</div><div class='del'>-</div><div class='del'>-	if (j &gt;= MAX_FIDS) {</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-</div><div class='del'>-		if (i == MAX_FIDS) {</div><div class='del'>-			dev-&gt;stats.tx_fifo_errors++;</div><div class='del'>-			return NETDEV_TX_BUSY;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	/* check min length*/</div><div class='del'>-	len = ETH_ZLEN &lt; skb-&gt;len ? skb-&gt;len : ETH_ZLEN;</div><div class='del'>-        /* Mark fid as used &amp; save length for later */</div><div class='del'>-	fids[i] |= (len &lt;&lt; 16);</div><div class='del'>-	priv-&gt;xmit11.skb = skb;</div><div class='del'>-	priv-&gt;xmit11.fid = i;</div><div class='del'>-	if (down_trylock(&amp;priv-&gt;sem) != 0) {</div><div class='del'>-		set_bit(FLAG_PENDING_XMIT11, &amp;priv-&gt;flags);</div><div class='del'>-		netif_stop_queue(dev);</div><div class='del'>-		set_bit(JOB_XMIT11, &amp;priv-&gt;jobs);</div><div class='del'>-		wake_up_interruptible(&amp;priv-&gt;thr_wait);</div><div class='del'>-	} else</div><div class='del'>-		airo_end_xmit11(dev, false);</div><div class='del'>-	return NETDEV_TX_OK;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_read_stats(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	StatsRid stats_rid;</div><div class='del'>-	__le32 *vals = stats_rid.vals;</div><div class='del'>-</div><div class='del'>-	clear_bit(JOB_STATS, &amp;ai-&gt;jobs);</div><div class='del'>-	if (ai-&gt;power.event) {</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-	readStatsRid(ai, &amp;stats_rid, RID_STATS, 0);</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-</div><div class='del'>-	dev-&gt;stats.rx_packets = le32_to_cpu(vals[43]) + le32_to_cpu(vals[44]) +</div><div class='del'>-			       le32_to_cpu(vals[45]);</div><div class='del'>-	dev-&gt;stats.tx_packets = le32_to_cpu(vals[39]) + le32_to_cpu(vals[40]) +</div><div class='del'>-			       le32_to_cpu(vals[41]);</div><div class='del'>-	dev-&gt;stats.rx_bytes = le32_to_cpu(vals[92]);</div><div class='del'>-	dev-&gt;stats.tx_bytes = le32_to_cpu(vals[91]);</div><div class='del'>-	dev-&gt;stats.rx_errors = le32_to_cpu(vals[0]) + le32_to_cpu(vals[2]) +</div><div class='del'>-			      le32_to_cpu(vals[3]) + le32_to_cpu(vals[4]);</div><div class='del'>-	dev-&gt;stats.tx_errors = le32_to_cpu(vals[42]) +</div><div class='del'>-			      dev-&gt;stats.tx_fifo_errors;</div><div class='del'>-	dev-&gt;stats.multicast = le32_to_cpu(vals[43]);</div><div class='del'>-	dev-&gt;stats.collisions = le32_to_cpu(vals[89]);</div><div class='del'>-</div><div class='del'>-	/* detailed rx_errors: */</div><div class='del'>-	dev-&gt;stats.rx_length_errors = le32_to_cpu(vals[3]);</div><div class='del'>-	dev-&gt;stats.rx_crc_errors = le32_to_cpu(vals[4]);</div><div class='del'>-	dev-&gt;stats.rx_frame_errors = le32_to_cpu(vals[2]);</div><div class='del'>-	dev-&gt;stats.rx_fifo_errors = le32_to_cpu(vals[0]);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct net_device_stats *airo_get_stats(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *local =  dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	if (!test_bit(JOB_STATS, &amp;local-&gt;jobs)) {</div><div class='del'>-		set_bit(JOB_STATS, &amp;local-&gt;jobs);</div><div class='del'>-		wake_up_interruptible(&amp;local-&gt;thr_wait);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return &amp;dev-&gt;stats;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_set_promisc(struct airo_info *ai, bool may_sleep)</div><div class='del'>-{</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.cmd = CMD_SETMODE;</div><div class='del'>-	clear_bit(JOB_PROMISC, &amp;ai-&gt;jobs);</div><div class='del'>-	cmd.parm0=(ai-&gt;flags&amp;IFF_PROMISC) ? PROMISC : NOPROMISC;</div><div class='del'>-	issuecommand(ai, &amp;cmd, &amp;rsp, may_sleep);</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_set_multicast_list(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	if ((dev-&gt;flags ^ ai-&gt;flags) &amp; IFF_PROMISC) {</div><div class='del'>-		change_bit(FLAG_PROMISC, &amp;ai-&gt;flags);</div><div class='del'>-		if (down_trylock(&amp;ai-&gt;sem) != 0) {</div><div class='del'>-			set_bit(JOB_PROMISC, &amp;ai-&gt;jobs);</div><div class='del'>-			wake_up_interruptible(&amp;ai-&gt;thr_wait);</div><div class='del'>-		} else</div><div class='del'>-			airo_set_promisc(ai, false);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if ((dev-&gt;flags&amp;IFF_ALLMULTI) || !netdev_mc_empty(dev)) {</div><div class='del'>-		/* Turn on multicast.  (Should be already setup...) */</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int airo_set_mac_address(struct net_device *dev, void *p)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	struct sockaddr *addr = p;</div><div class='del'>-</div><div class='del'>-	readConfigRid(ai, 1);</div><div class='del'>-	memcpy (ai-&gt;config.macAddr, addr-&gt;sa_data, dev-&gt;addr_len);</div><div class='del'>-	set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-	disable_MAC(ai, 1);</div><div class='del'>-	writeConfigRid (ai, 1);</div><div class='del'>-	enable_MAC(ai, 1);</div><div class='del'>-	dev_addr_set(ai-&gt;dev, addr-&gt;sa_data);</div><div class='del'>-	if (ai-&gt;wifidev)</div><div class='del'>-		dev_addr_set(ai-&gt;wifidev, addr-&gt;sa_data);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static LIST_HEAD(airo_devices);</div><div class='del'>-</div><div class='del'>-static void add_airo_dev(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	/* Upper layers already keep track of PCI devices,</div><div class='del'>-	 * so we only need to remember our non-PCI cards. */</div><div class='del'>-	if (!ai-&gt;pci)</div><div class='del'>-		list_add_tail(&amp;ai-&gt;dev_list, &amp;airo_devices);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void del_airo_dev(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	if (!ai-&gt;pci)</div><div class='del'>-		list_del(&amp;ai-&gt;dev_list);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int airo_close(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	netif_stop_queue(dev);</div><div class='del'>-</div><div class='del'>-	if (ai-&gt;wifidev != dev) {</div><div class='del'>-#ifdef POWER_ON_DOWN</div><div class='del'>-		/* Shut power to the card. The idea is that the user can save</div><div class='del'>-		 * power when he doesn't need the card with "ifconfig down".</div><div class='del'>-		 * That's the method that is most friendly towards the network</div><div class='del'>-		 * stack (i.e. the network stack won't try to broadcast</div><div class='del'>-		 * anything on the interface and routes are gone. Jean II */</div><div class='del'>-		set_bit(FLAG_RADIO_DOWN, &amp;ai-&gt;flags);</div><div class='del'>-		disable_MAC(ai, 1);</div><div class='del'>-#endif</div><div class='del'>-		disable_interrupts(ai);</div><div class='del'>-</div><div class='del'>-		free_irq(dev-&gt;irq, dev);</div><div class='del'>-</div><div class='del'>-		set_bit(JOB_DIE, &amp;ai-&gt;jobs);</div><div class='del'>-		kthread_stop(ai-&gt;airo_thread_task);</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-void stop_airo_card(struct net_device *dev, int freeres)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	set_bit(FLAG_RADIO_DOWN, &amp;ai-&gt;flags);</div><div class='del'>-	disable_MAC(ai, 1);</div><div class='del'>-	disable_interrupts(ai);</div><div class='del'>-	takedown_proc_entry(dev, ai);</div><div class='del'>-	if (test_bit(FLAG_REGISTERED, &amp;ai-&gt;flags)) {</div><div class='del'>-		unregister_netdev(dev);</div><div class='del'>-		if (ai-&gt;wifidev) {</div><div class='del'>-			unregister_netdev(ai-&gt;wifidev);</div><div class='del'>-			free_netdev(ai-&gt;wifidev);</div><div class='del'>-			ai-&gt;wifidev = NULL;</div><div class='del'>-		}</div><div class='del'>-		clear_bit(FLAG_REGISTERED, &amp;ai-&gt;flags);</div><div class='del'>-	}</div><div class='del'>-	/*</div><div class='del'>-	 * Clean out tx queue</div><div class='del'>-	 */</div><div class='del'>-	if (test_bit(FLAG_MPI, &amp;ai-&gt;flags) &amp;&amp; !skb_queue_empty(&amp;ai-&gt;txq)) {</div><div class='del'>-		struct sk_buff *skb = NULL;</div><div class='del'>-		for (;(skb = skb_dequeue(&amp;ai-&gt;txq));)</div><div class='del'>-			dev_kfree_skb(skb);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	airo_networks_free (ai);</div><div class='del'>-</div><div class='del'>-	kfree(ai-&gt;flash);</div><div class='del'>-	kfree(ai-&gt;rssi);</div><div class='del'>-	kfree(ai-&gt;SSID);</div><div class='del'>-	if (freeres) {</div><div class='del'>-		/* PCMCIA frees this stuff, so only for PCI and ISA */</div><div class='del'>-		release_region(dev-&gt;base_addr, 64);</div><div class='del'>-		if (test_bit(FLAG_MPI, &amp;ai-&gt;flags)) {</div><div class='del'>-			if (ai-&gt;pci)</div><div class='del'>-				mpi_unmap_card(ai-&gt;pci);</div><div class='del'>-			if (ai-&gt;pcimem)</div><div class='del'>-				iounmap(ai-&gt;pcimem);</div><div class='del'>-			if (ai-&gt;pciaux)</div><div class='del'>-				iounmap(ai-&gt;pciaux);</div><div class='del'>-			dma_free_coherent(&amp;ai-&gt;pci-&gt;dev, PCI_SHARED_LEN,</div><div class='del'>-					  ai-&gt;shared, ai-&gt;shared_dma);</div><div class='del'>-		}</div><div class='del'>-        }</div><div class='del'>-	crypto_free_sync_skcipher(ai-&gt;tfm);</div><div class='del'>-	del_airo_dev(ai);</div><div class='del'>-	free_netdev(dev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(stop_airo_card);</div><div class='del'>-</div><div class='del'>-static int wll_header_parse(const struct sk_buff *skb, unsigned char *haddr)</div><div class='del'>-{</div><div class='del'>-	memcpy(haddr, skb_mac_header(skb) + 10, ETH_ALEN);</div><div class='del'>-	return ETH_ALEN;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mpi_unmap_card(struct pci_dev *pci)</div><div class='del'>-{</div><div class='del'>-	unsigned long mem_start = pci_resource_start(pci, 1);</div><div class='del'>-	unsigned long mem_len = pci_resource_len(pci, 1);</div><div class='del'>-	unsigned long aux_start = pci_resource_start(pci, 2);</div><div class='del'>-	unsigned long aux_len = AUXMEMSIZE;</div><div class='del'>-</div><div class='del'>-	release_mem_region(aux_start, aux_len);</div><div class='del'>-	release_mem_region(mem_start, mem_len);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*************************************************************</div><div class='del'>- *  This routine assumes that descriptors have been setup .</div><div class='del'>- *  Run at insmod time or after reset when the descriptors</div><div class='del'>- *  have been initialized . Returns 0 if all is well nz</div><div class='del'>- *  otherwise . Does not allocate memory but sets up card</div><div class='del'>- *  using previously allocated descriptors.</div><div class='del'>- */</div><div class='del'>-static int mpi_init_descriptors (struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-	int i;</div><div class='del'>-	int rc = SUCCESS;</div><div class='del'>-</div><div class='del'>-	/* Alloc  card RX descriptors */</div><div class='del'>-	netif_stop_queue(ai-&gt;dev);</div><div class='del'>-</div><div class='del'>-	memset(&amp;rsp, 0, sizeof(rsp));</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-</div><div class='del'>-	cmd.cmd = CMD_ALLOCATEAUX;</div><div class='del'>-	cmd.parm0 = FID_RX;</div><div class='del'>-	cmd.parm1 = (ai-&gt;rxfids[0].card_ram_off - ai-&gt;pciaux);</div><div class='del'>-	cmd.parm2 = MPI_MAX_FIDS;</div><div class='del'>-	rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-	if (rc != SUCCESS) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Couldn't allocate RX FID");</div><div class='del'>-		return rc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i&lt;MPI_MAX_FIDS; i++) {</div><div class='del'>-		memcpy_toio(ai-&gt;rxfids[i].card_ram_off,</div><div class='del'>-			&amp;ai-&gt;rxfids[i].rx_desc, sizeof(RxFid));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Alloc card TX descriptors */</div><div class='del'>-</div><div class='del'>-	memset(&amp;rsp, 0, sizeof(rsp));</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-</div><div class='del'>-	cmd.cmd = CMD_ALLOCATEAUX;</div><div class='del'>-	cmd.parm0 = FID_TX;</div><div class='del'>-	cmd.parm1 = (ai-&gt;txfids[0].card_ram_off - ai-&gt;pciaux);</div><div class='del'>-	cmd.parm2 = MPI_MAX_FIDS;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i&lt;MPI_MAX_FIDS; i++) {</div><div class='del'>-		ai-&gt;txfids[i].tx_desc.valid = 1;</div><div class='del'>-		memcpy_toio(ai-&gt;txfids[i].card_ram_off,</div><div class='del'>-			&amp;ai-&gt;txfids[i].tx_desc, sizeof(TxFid));</div><div class='del'>-	}</div><div class='del'>-	ai-&gt;txfids[i-1].tx_desc.eoc = 1; /* Last descriptor has EOC set */</div><div class='del'>-</div><div class='del'>-	rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-	if (rc != SUCCESS) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Couldn't allocate TX FID");</div><div class='del'>-		return rc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Alloc card Rid descriptor */</div><div class='del'>-	memset(&amp;rsp, 0, sizeof(rsp));</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-</div><div class='del'>-	cmd.cmd = CMD_ALLOCATEAUX;</div><div class='del'>-	cmd.parm0 = RID_RW;</div><div class='del'>-	cmd.parm1 = (ai-&gt;config_desc.card_ram_off - ai-&gt;pciaux);</div><div class='del'>-	cmd.parm2 = 1; /* Magic number... */</div><div class='del'>-	rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-	if (rc != SUCCESS) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Couldn't allocate RID");</div><div class='del'>-		return rc;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	memcpy_toio(ai-&gt;config_desc.card_ram_off,</div><div class='del'>-		&amp;ai-&gt;config_desc.rid_desc, sizeof(Rid));</div><div class='del'>-</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- * We are setting up three things here:</div><div class='del'>- * 1) Map AUX memory for descriptors: Rid, TxFid, or RxFid.</div><div class='del'>- * 2) Map PCI memory for issuing commands.</div><div class='del'>- * 3) Allocate memory (shared) to send and receive ethernet frames.</div><div class='del'>- */</div><div class='del'>-static int mpi_map_card(struct airo_info *ai, struct pci_dev *pci)</div><div class='del'>-{</div><div class='del'>-	unsigned long mem_start, mem_len, aux_start, aux_len;</div><div class='del'>-	int rc = -1;</div><div class='del'>-	int i;</div><div class='del'>-	dma_addr_t busaddroff;</div><div class='del'>-	unsigned char *vpackoff;</div><div class='del'>-	unsigned char __iomem *pciaddroff;</div><div class='del'>-</div><div class='del'>-	mem_start = pci_resource_start(pci, 1);</div><div class='del'>-	mem_len = pci_resource_len(pci, 1);</div><div class='del'>-	aux_start = pci_resource_start(pci, 2);</div><div class='del'>-	aux_len = AUXMEMSIZE;</div><div class='del'>-</div><div class='del'>-	if (!request_mem_region(mem_start, mem_len, DRV_NAME)) {</div><div class='del'>-		airo_print_err("", "Couldn't get region %x[%x]",</div><div class='del'>-			(int)mem_start, (int)mem_len);</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-	if (!request_mem_region(aux_start, aux_len, DRV_NAME)) {</div><div class='del'>-		airo_print_err("", "Couldn't get region %x[%x]",</div><div class='del'>-			(int)aux_start, (int)aux_len);</div><div class='del'>-		goto free_region1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ai-&gt;pcimem = ioremap(mem_start, mem_len);</div><div class='del'>-	if (!ai-&gt;pcimem) {</div><div class='del'>-		airo_print_err("", "Couldn't map region %x[%x]",</div><div class='del'>-			(int)mem_start, (int)mem_len);</div><div class='del'>-		goto free_region2;</div><div class='del'>-	}</div><div class='del'>-	ai-&gt;pciaux = ioremap(aux_start, aux_len);</div><div class='del'>-	if (!ai-&gt;pciaux) {</div><div class='del'>-		airo_print_err("", "Couldn't map region %x[%x]",</div><div class='del'>-			(int)aux_start, (int)aux_len);</div><div class='del'>-		goto free_memmap;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Reserve PKTSIZE for each fid and 2K for the Rids */</div><div class='del'>-	ai-&gt;shared = dma_alloc_coherent(&amp;pci-&gt;dev, PCI_SHARED_LEN,</div><div class='del'>-					&amp;ai-&gt;shared_dma, GFP_KERNEL);</div><div class='del'>-	if (!ai-&gt;shared) {</div><div class='del'>-		airo_print_err("", "Couldn't alloc_coherent %d",</div><div class='del'>-			PCI_SHARED_LEN);</div><div class='del'>-		goto free_auxmap;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/*</div><div class='del'>-	 * Setup descriptor RX, TX, CONFIG</div><div class='del'>-	 */</div><div class='del'>-	busaddroff = ai-&gt;shared_dma;</div><div class='del'>-	pciaddroff = ai-&gt;pciaux + AUX_OFFSET;</div><div class='del'>-	vpackoff   = ai-&gt;shared;</div><div class='del'>-</div><div class='del'>-	/* RX descriptor setup */</div><div class='del'>-	for (i = 0; i &lt; MPI_MAX_FIDS; i++) {</div><div class='del'>-		ai-&gt;rxfids[i].pending = 0;</div><div class='del'>-		ai-&gt;rxfids[i].card_ram_off = pciaddroff;</div><div class='del'>-		ai-&gt;rxfids[i].virtual_host_addr = vpackoff;</div><div class='del'>-		ai-&gt;rxfids[i].rx_desc.host_addr = busaddroff;</div><div class='del'>-		ai-&gt;rxfids[i].rx_desc.valid = 1;</div><div class='del'>-		ai-&gt;rxfids[i].rx_desc.len = PKTSIZE;</div><div class='del'>-		ai-&gt;rxfids[i].rx_desc.rdy = 0;</div><div class='del'>-</div><div class='del'>-		pciaddroff += sizeof(RxFid);</div><div class='del'>-		busaddroff += PKTSIZE;</div><div class='del'>-		vpackoff   += PKTSIZE;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* TX descriptor setup */</div><div class='del'>-	for (i = 0; i &lt; MPI_MAX_FIDS; i++) {</div><div class='del'>-		ai-&gt;txfids[i].card_ram_off = pciaddroff;</div><div class='del'>-		ai-&gt;txfids[i].virtual_host_addr = vpackoff;</div><div class='del'>-		ai-&gt;txfids[i].tx_desc.valid = 1;</div><div class='del'>-		ai-&gt;txfids[i].tx_desc.host_addr = busaddroff;</div><div class='del'>-		memcpy(ai-&gt;txfids[i].virtual_host_addr,</div><div class='del'>-			&amp;wifictlhdr8023, sizeof(wifictlhdr8023));</div><div class='del'>-</div><div class='del'>-		pciaddroff += sizeof(TxFid);</div><div class='del'>-		busaddroff += PKTSIZE;</div><div class='del'>-		vpackoff   += PKTSIZE;</div><div class='del'>-	}</div><div class='del'>-	ai-&gt;txfids[i-1].tx_desc.eoc = 1; /* Last descriptor has EOC set */</div><div class='del'>-</div><div class='del'>-	/* Rid descriptor setup */</div><div class='del'>-	ai-&gt;config_desc.card_ram_off = pciaddroff;</div><div class='del'>-	ai-&gt;config_desc.virtual_host_addr = vpackoff;</div><div class='del'>-	ai-&gt;config_desc.rid_desc.host_addr = busaddroff;</div><div class='del'>-	ai-&gt;ridbus = busaddroff;</div><div class='del'>-	ai-&gt;config_desc.rid_desc.rid = 0;</div><div class='del'>-	ai-&gt;config_desc.rid_desc.len = RIDSIZE;</div><div class='del'>-	ai-&gt;config_desc.rid_desc.valid = 1;</div><div class='del'>-	pciaddroff += sizeof(Rid);</div><div class='del'>-	busaddroff += RIDSIZE;</div><div class='del'>-	vpackoff   += RIDSIZE;</div><div class='del'>-</div><div class='del'>-	/* Tell card about descriptors */</div><div class='del'>-	if (mpi_init_descriptors (ai) != SUCCESS)</div><div class='del'>-		goto free_shared;</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>- free_shared:</div><div class='del'>-	dma_free_coherent(&amp;pci-&gt;dev, PCI_SHARED_LEN, ai-&gt;shared,</div><div class='del'>-			  ai-&gt;shared_dma);</div><div class='del'>- free_auxmap:</div><div class='del'>-	iounmap(ai-&gt;pciaux);</div><div class='del'>- free_memmap:</div><div class='del'>-	iounmap(ai-&gt;pcimem);</div><div class='del'>- free_region2:</div><div class='del'>-	release_mem_region(aux_start, aux_len);</div><div class='del'>- free_region1:</div><div class='del'>-	release_mem_region(mem_start, mem_len);</div><div class='del'>- out:</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct header_ops airo_header_ops = {</div><div class='del'>-	.parse = wll_header_parse,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct net_device_ops airo11_netdev_ops = {</div><div class='del'>-	.ndo_open 		= airo_open,</div><div class='del'>-	.ndo_stop 		= airo_close,</div><div class='del'>-	.ndo_start_xmit 	= airo_start_xmit11,</div><div class='del'>-	.ndo_get_stats 		= airo_get_stats,</div><div class='del'>-	.ndo_set_mac_address	= airo_set_mac_address,</div><div class='del'>-	.ndo_siocdevprivate	= airo_siocdevprivate,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static void wifi_setup(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	dev-&gt;netdev_ops = &amp;airo11_netdev_ops;</div><div class='del'>-	dev-&gt;header_ops = &amp;airo_header_ops;</div><div class='del'>-	dev-&gt;wireless_handlers = &amp;airo_handler_def;</div><div class='del'>-</div><div class='del'>-	dev-&gt;type               = ARPHRD_IEEE80211;</div><div class='del'>-	dev-&gt;hard_header_len    = ETH_HLEN;</div><div class='del'>-	dev-&gt;mtu                = AIRO_DEF_MTU;</div><div class='del'>-	dev-&gt;min_mtu            = 68;</div><div class='del'>-	dev-&gt;max_mtu            = MIC_MSGLEN_MAX;</div><div class='del'>-	dev-&gt;addr_len           = ETH_ALEN;</div><div class='del'>-	dev-&gt;tx_queue_len       = 100;</div><div class='del'>-</div><div class='del'>-	eth_broadcast_addr(dev-&gt;broadcast);</div><div class='del'>-</div><div class='del'>-	dev-&gt;flags              = IFF_BROADCAST|IFF_MULTICAST;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static struct net_device *init_wifidev(struct airo_info *ai,</div><div class='del'>-					struct net_device *ethdev)</div><div class='del'>-{</div><div class='del'>-	int err;</div><div class='del'>-	struct net_device *dev = alloc_netdev(0, "wifi%d", NET_NAME_UNKNOWN,</div><div class='del'>-					      wifi_setup);</div><div class='del'>-	if (!dev)</div><div class='del'>-		return NULL;</div><div class='del'>-	dev-&gt;ml_priv = ethdev-&gt;ml_priv;</div><div class='del'>-	dev-&gt;irq = ethdev-&gt;irq;</div><div class='del'>-	dev-&gt;base_addr = ethdev-&gt;base_addr;</div><div class='del'>-	dev-&gt;wireless_data = ethdev-&gt;wireless_data;</div><div class='del'>-	SET_NETDEV_DEV(dev, ethdev-&gt;dev.parent);</div><div class='del'>-	eth_hw_addr_inherit(dev, ethdev);</div><div class='del'>-	err = register_netdev(dev);</div><div class='del'>-	if (err&lt;0) {</div><div class='del'>-		free_netdev(dev);</div><div class='del'>-		return NULL;</div><div class='del'>-	}</div><div class='del'>-	return dev;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int reset_card(struct net_device *dev, int lock)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	if (lock &amp;&amp; down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-		return -1;</div><div class='del'>-	waitbusy (ai);</div><div class='del'>-	OUT4500(ai, COMMAND, CMD_SOFTRESET);</div><div class='del'>-	msleep(200);</div><div class='del'>-	waitbusy (ai);</div><div class='del'>-	msleep(200);</div><div class='del'>-	if (lock)</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-#define AIRO_MAX_NETWORK_COUNT	64</div><div class='del'>-static int airo_networks_allocate(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	if (ai-&gt;networks)</div><div class='del'>-		return 0;</div><div class='del'>-</div><div class='del'>-	ai-&gt;networks = kcalloc(AIRO_MAX_NETWORK_COUNT, sizeof(BSSListElement),</div><div class='del'>-			       GFP_KERNEL);</div><div class='del'>-	if (!ai-&gt;networks) {</div><div class='del'>-		airo_print_warn("", "Out of memory allocating beacons");</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_networks_free(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	kfree(ai-&gt;networks);</div><div class='del'>-	ai-&gt;networks = NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_networks_initialize(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	INIT_LIST_HEAD(&amp;ai-&gt;network_free_list);</div><div class='del'>-	INIT_LIST_HEAD(&amp;ai-&gt;network_list);</div><div class='del'>-	for (i = 0; i &lt; AIRO_MAX_NETWORK_COUNT; i++)</div><div class='del'>-		list_add_tail(&amp;ai-&gt;networks[i].list,</div><div class='del'>-			      &amp;ai-&gt;network_free_list);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const struct net_device_ops airo_netdev_ops = {</div><div class='del'>-	.ndo_open		= airo_open,</div><div class='del'>-	.ndo_stop		= airo_close,</div><div class='del'>-	.ndo_start_xmit		= airo_start_xmit,</div><div class='del'>-	.ndo_get_stats		= airo_get_stats,</div><div class='del'>-	.ndo_set_rx_mode	= airo_set_multicast_list,</div><div class='del'>-	.ndo_set_mac_address	= airo_set_mac_address,</div><div class='del'>-	.ndo_siocdevprivate	= airo_siocdevprivate,</div><div class='del'>-	.ndo_validate_addr	= eth_validate_addr,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct net_device_ops mpi_netdev_ops = {</div><div class='del'>-	.ndo_open		= airo_open,</div><div class='del'>-	.ndo_stop		= airo_close,</div><div class='del'>-	.ndo_start_xmit		= mpi_start_xmit,</div><div class='del'>-	.ndo_get_stats		= airo_get_stats,</div><div class='del'>-	.ndo_set_rx_mode	= airo_set_multicast_list,</div><div class='del'>-	.ndo_set_mac_address	= airo_set_mac_address,</div><div class='del'>-	.ndo_siocdevprivate	= airo_siocdevprivate,</div><div class='del'>-	.ndo_validate_addr	= eth_validate_addr,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static struct net_device *_init_airo_card(unsigned short irq, int port,</div><div class='del'>-					   int is_pcmcia, struct pci_dev *pci,</div><div class='del'>-					   struct device *dmdev)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev;</div><div class='del'>-	struct airo_info *ai;</div><div class='del'>-	int i, rc;</div><div class='del'>-	CapabilityRid cap_rid;</div><div class='del'>-</div><div class='del'>-	/* Create the network device object. */</div><div class='del'>-	dev = alloc_netdev(sizeof(*ai), "", NET_NAME_UNKNOWN, ether_setup);</div><div class='del'>-	if (!dev) {</div><div class='del'>-		airo_print_err("", "Couldn't alloc_etherdev");</div><div class='del'>-		return NULL;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	ai = dev-&gt;ml_priv = netdev_priv(dev);</div><div class='del'>-	ai-&gt;wifidev = NULL;</div><div class='del'>-	ai-&gt;flags = 1 &lt;&lt; FLAG_RADIO_DOWN;</div><div class='del'>-	ai-&gt;jobs = 0;</div><div class='del'>-	ai-&gt;dev = dev;</div><div class='del'>-	if (pci &amp;&amp; (pci-&gt;device == 0x5000 || pci-&gt;device == 0xa504)) {</div><div class='del'>-		airo_print_dbg("", "Found an MPI350 card");</div><div class='del'>-		set_bit(FLAG_MPI, &amp;ai-&gt;flags);</div><div class='del'>-	}</div><div class='del'>-	spin_lock_init(&amp;ai-&gt;aux_lock);</div><div class='del'>-	sema_init(&amp;ai-&gt;sem, 1);</div><div class='del'>-	ai-&gt;config.len = 0;</div><div class='del'>-	ai-&gt;pci = pci;</div><div class='del'>-	init_waitqueue_head (&amp;ai-&gt;thr_wait);</div><div class='del'>-	ai-&gt;tfm = NULL;</div><div class='del'>-	add_airo_dev(ai);</div><div class='del'>-	ai-&gt;APList.len = cpu_to_le16(sizeof(struct APListRid));</div><div class='del'>-</div><div class='del'>-	if (airo_networks_allocate (ai))</div><div class='del'>-		goto err_out_free;</div><div class='del'>-	airo_networks_initialize (ai);</div><div class='del'>-</div><div class='del'>-	skb_queue_head_init (&amp;ai-&gt;txq);</div><div class='del'>-</div><div class='del'>-	/* The Airo-specific entries in the device structure. */</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags))</div><div class='del'>-		dev-&gt;netdev_ops = &amp;mpi_netdev_ops;</div><div class='del'>-	else</div><div class='del'>-		dev-&gt;netdev_ops = &amp;airo_netdev_ops;</div><div class='del'>-	dev-&gt;wireless_handlers = &amp;airo_handler_def;</div><div class='del'>-	ai-&gt;wireless_data.spy_data = &amp;ai-&gt;spy_data;</div><div class='del'>-	dev-&gt;wireless_data = &amp;ai-&gt;wireless_data;</div><div class='del'>-	dev-&gt;irq = irq;</div><div class='del'>-	dev-&gt;base_addr = port;</div><div class='del'>-	dev-&gt;priv_flags &amp;= ~IFF_TX_SKB_SHARING;</div><div class='del'>-	dev-&gt;max_mtu = MIC_MSGLEN_MAX;</div><div class='del'>-</div><div class='del'>-	SET_NETDEV_DEV(dev, dmdev);</div><div class='del'>-</div><div class='del'>-	reset_card (dev, 1);</div><div class='del'>-	msleep(400);</div><div class='del'>-</div><div class='del'>-	if (!is_pcmcia) {</div><div class='del'>-		if (!request_region(dev-&gt;base_addr, 64, DRV_NAME)) {</div><div class='del'>-			rc = -EBUSY;</div><div class='del'>-			airo_print_err(dev-&gt;name, "Couldn't request region");</div><div class='del'>-			goto err_out_nets;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags)) {</div><div class='del'>-		if (mpi_map_card(ai, pci)) {</div><div class='del'>-			airo_print_err("", "Could not map memory");</div><div class='del'>-			goto err_out_res;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (probe) {</div><div class='del'>-		if (setup_card(ai, dev, 1) != SUCCESS) {</div><div class='del'>-			airo_print_err(dev-&gt;name, "MAC could not be enabled");</div><div class='del'>-			rc = -EIO;</div><div class='del'>-			goto err_out_map;</div><div class='del'>-		}</div><div class='del'>-	} else if (!test_bit(FLAG_MPI,&amp;ai-&gt;flags)) {</div><div class='del'>-		ai-&gt;bap_read = fast_bap_read;</div><div class='del'>-		set_bit(FLAG_FLASHING, &amp;ai-&gt;flags);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	strcpy(dev-&gt;name, "eth%d");</div><div class='del'>-	rc = register_netdev(dev);</div><div class='del'>-	if (rc) {</div><div class='del'>-		airo_print_err(dev-&gt;name, "Couldn't register_netdev");</div><div class='del'>-		goto err_out_map;</div><div class='del'>-	}</div><div class='del'>-	ai-&gt;wifidev = init_wifidev(ai, dev);</div><div class='del'>-	if (!ai-&gt;wifidev)</div><div class='del'>-		goto err_out_reg;</div><div class='del'>-</div><div class='del'>-	rc = readCapabilityRid(ai, &amp;cap_rid, 1);</div><div class='del'>-	if (rc != SUCCESS) {</div><div class='del'>-		rc = -EIO;</div><div class='del'>-		goto err_out_wifi;</div><div class='del'>-	}</div><div class='del'>-	/* WEP capability discovery */</div><div class='del'>-	ai-&gt;wep_capable = (cap_rid.softCap &amp; cpu_to_le16(0x02)) ? 1 : 0;</div><div class='del'>-	ai-&gt;max_wep_idx = (cap_rid.softCap &amp; cpu_to_le16(0x80)) ? 3 : 0;</div><div class='del'>-</div><div class='del'>-	airo_print_info(dev-&gt;name, "Firmware version %x.%x.%02d",</div><div class='del'>-	                ((le16_to_cpu(cap_rid.softVer) &gt;&gt; 8) &amp; 0xF),</div><div class='del'>-	                (le16_to_cpu(cap_rid.softVer) &amp; 0xFF),</div><div class='del'>-	                le16_to_cpu(cap_rid.softSubVer));</div><div class='del'>-</div><div class='del'>-	/* Test for WPA support */</div><div class='del'>-	/* Only firmware versions 5.30.17 or better can do WPA */</div><div class='del'>-	if (le16_to_cpu(cap_rid.softVer) &gt; 0x530</div><div class='del'>-	 || (le16_to_cpu(cap_rid.softVer) == 0x530</div><div class='del'>-	      &amp;&amp; le16_to_cpu(cap_rid.softSubVer) &gt;= 17)) {</div><div class='del'>-		airo_print_info(ai-&gt;dev-&gt;name, "WPA supported.");</div><div class='del'>-</div><div class='del'>-		set_bit(FLAG_WPA_CAPABLE, &amp;ai-&gt;flags);</div><div class='del'>-		ai-&gt;bssListFirst = RID_WPA_BSSLISTFIRST;</div><div class='del'>-		ai-&gt;bssListNext = RID_WPA_BSSLISTNEXT;</div><div class='del'>-		ai-&gt;bssListRidLen = sizeof(BSSListRid);</div><div class='del'>-	} else {</div><div class='del'>-		airo_print_info(ai-&gt;dev-&gt;name, "WPA unsupported with firmware "</div><div class='del'>-			"versions older than 5.30.17.");</div><div class='del'>-</div><div class='del'>-		ai-&gt;bssListFirst = RID_BSSLISTFIRST;</div><div class='del'>-		ai-&gt;bssListNext = RID_BSSLISTNEXT;</div><div class='del'>-		ai-&gt;bssListRidLen = sizeof(BSSListRid) - sizeof(BSSListRidExtra);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	set_bit(FLAG_REGISTERED,&amp;ai-&gt;flags);</div><div class='del'>-	airo_print_info(dev-&gt;name, "MAC enabled %pM", dev-&gt;dev_addr);</div><div class='del'>-</div><div class='del'>-	/* Allocate the transmit buffers */</div><div class='del'>-	if (probe &amp;&amp; !test_bit(FLAG_MPI,&amp;ai-&gt;flags))</div><div class='del'>-		for (i = 0; i &lt; MAX_FIDS; i++)</div><div class='del'>-			ai-&gt;fids[i] = transmit_allocate(ai, AIRO_DEF_MTU, i&gt;=MAX_FIDS/2);</div><div class='del'>-</div><div class='del'>-	if (setup_proc_entry(dev, dev-&gt;ml_priv) &lt; 0)</div><div class='del'>-		goto err_out_wifi;</div><div class='del'>-</div><div class='del'>-	return dev;</div><div class='del'>-</div><div class='del'>-err_out_wifi:</div><div class='del'>-	unregister_netdev(ai-&gt;wifidev);</div><div class='del'>-	free_netdev(ai-&gt;wifidev);</div><div class='del'>-err_out_reg:</div><div class='del'>-	unregister_netdev(dev);</div><div class='del'>-err_out_map:</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags) &amp;&amp; pci) {</div><div class='del'>-		dma_free_coherent(&amp;pci-&gt;dev, PCI_SHARED_LEN, ai-&gt;shared,</div><div class='del'>-				  ai-&gt;shared_dma);</div><div class='del'>-		iounmap(ai-&gt;pciaux);</div><div class='del'>-		iounmap(ai-&gt;pcimem);</div><div class='del'>-		mpi_unmap_card(ai-&gt;pci);</div><div class='del'>-	}</div><div class='del'>-err_out_res:</div><div class='del'>-	if (!is_pcmcia)</div><div class='del'>-		release_region(dev-&gt;base_addr, 64);</div><div class='del'>-err_out_nets:</div><div class='del'>-	airo_networks_free(ai);</div><div class='del'>-err_out_free:</div><div class='del'>-	del_airo_dev(ai);</div><div class='del'>-	free_netdev(dev);</div><div class='del'>-	return NULL;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-struct net_device *init_airo_card(unsigned short irq, int port, int is_pcmcia,</div><div class='del'>-				  struct device *dmdev)</div><div class='del'>-{</div><div class='del'>-	return _init_airo_card (irq, port, is_pcmcia, NULL, dmdev);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(init_airo_card);</div><div class='del'>-</div><div class='del'>-static int waitbusy (struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	int delay = 0;</div><div class='del'>-	while ((IN4500(ai, COMMAND) &amp; COMMAND_BUSY) &amp;&amp; (delay &lt; 10000)) {</div><div class='del'>-		udelay (10);</div><div class='del'>-		if ((++delay % 20) == 0)</div><div class='del'>-			OUT4500(ai, EVACK, EV_CLEARCOMMANDBUSY);</div><div class='del'>-	}</div><div class='del'>-	return delay &lt; 10000;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-int reset_airo_card(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	int i;</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-</div><div class='del'>-	if (reset_card (dev, 1))</div><div class='del'>-		return -1;</div><div class='del'>-</div><div class='del'>-	if (setup_card(ai, dev, 1) != SUCCESS) {</div><div class='del'>-		airo_print_err(dev-&gt;name, "MAC could not be enabled");</div><div class='del'>-		return -1;</div><div class='del'>-	}</div><div class='del'>-	airo_print_info(dev-&gt;name, "MAC enabled %pM", dev-&gt;dev_addr);</div><div class='del'>-	/* Allocate the transmit buffers if needed */</div><div class='del'>-	if (!test_bit(FLAG_MPI,&amp;ai-&gt;flags))</div><div class='del'>-		for (i = 0; i &lt; MAX_FIDS; i++)</div><div class='del'>-			ai-&gt;fids[i] = transmit_allocate (ai, AIRO_DEF_MTU, i&gt;=MAX_FIDS/2);</div><div class='del'>-</div><div class='del'>-	enable_interrupts(ai);</div><div class='del'>-	netif_wake_queue(dev);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-EXPORT_SYMBOL(reset_airo_card);</div><div class='del'>-</div><div class='del'>-static void airo_send_event(struct net_device *dev)</div><div class='del'>-{</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	union iwreq_data wrqu;</div><div class='del'>-	StatusRid status_rid;</div><div class='del'>-</div><div class='del'>-	clear_bit(JOB_EVENT, &amp;ai-&gt;jobs);</div><div class='del'>-	PC4500_readrid(ai, RID_STATUS, &amp;status_rid, sizeof(status_rid), 0);</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-	wrqu.data.length = 0;</div><div class='del'>-	wrqu.data.flags = 0;</div><div class='del'>-	memcpy(wrqu.ap_addr.sa_data, status_rid.bssid[0], ETH_ALEN);</div><div class='del'>-	wrqu.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-</div><div class='del'>-	/* Send event to user space */</div><div class='del'>-	wireless_send_event(dev, SIOCGIWAP, &amp;wrqu, NULL);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_process_scan_results (struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	union iwreq_data	wrqu;</div><div class='del'>-	BSSListRid bss;</div><div class='del'>-	int rc;</div><div class='del'>-	BSSListElement * loop_net;</div><div class='del'>-	BSSListElement * tmp_net;</div><div class='del'>-</div><div class='del'>-	/* Blow away current list of scan results */</div><div class='del'>-	list_for_each_entry_safe (loop_net, tmp_net, &amp;ai-&gt;network_list, list) {</div><div class='del'>-		list_move_tail (&amp;loop_net-&gt;list, &amp;ai-&gt;network_free_list);</div><div class='del'>-		/* Don't blow away -&gt;list, just BSS data */</div><div class='del'>-		memset (loop_net, 0, sizeof (loop_net-&gt;bss));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Try to read the first entry of the scan result */</div><div class='del'>-	rc = PC4500_readrid(ai, ai-&gt;bssListFirst, &amp;bss, ai-&gt;bssListRidLen, 0);</div><div class='del'>-	if ((rc) || (bss.index == cpu_to_le16(0xffff))) {</div><div class='del'>-		/* No scan results */</div><div class='del'>-		goto out;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Read and parse all entries */</div><div class='del'>-	tmp_net = NULL;</div><div class='del'>-	while ((!rc) &amp;&amp; (bss.index != cpu_to_le16(0xffff))) {</div><div class='del'>-		/* Grab a network off the free list */</div><div class='del'>-		if (!list_empty(&amp;ai-&gt;network_free_list)) {</div><div class='del'>-			tmp_net = list_entry(ai-&gt;network_free_list.next,</div><div class='del'>-					    BSSListElement, list);</div><div class='del'>-			list_del(ai-&gt;network_free_list.next);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (tmp_net != NULL) {</div><div class='del'>-			memcpy(tmp_net, &amp;bss, sizeof(tmp_net-&gt;bss));</div><div class='del'>-			list_add_tail(&amp;tmp_net-&gt;list, &amp;ai-&gt;network_list);</div><div class='del'>-			tmp_net = NULL;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Read next entry */</div><div class='del'>-		rc = PC4500_readrid(ai, ai-&gt;bssListNext,</div><div class='del'>-				    &amp;bss, ai-&gt;bssListRidLen, 0);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-out:</div><div class='del'>-	/* write APList back (we cleared it in airo_set_scan) */</div><div class='del'>-	disable_MAC(ai, 2);</div><div class='del'>-	writeAPListRid(ai, &amp;ai-&gt;APList, 0);</div><div class='del'>-	enable_MAC(ai, 0);</div><div class='del'>-</div><div class='del'>-	ai-&gt;scan_timeout = 0;</div><div class='del'>-	clear_bit(JOB_SCAN_RESULTS, &amp;ai-&gt;jobs);</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-</div><div class='del'>-	/* Send an empty event to user space.</div><div class='del'>-	 * We don't send the received data on</div><div class='del'>-	 * the event because it would require</div><div class='del'>-	 * us to do complex transcoding, and</div><div class='del'>-	 * we want to minimise the work done in</div><div class='del'>-	 * the irq handler. Use a request to</div><div class='del'>-	 * extract the data - Jean II */</div><div class='del'>-	wrqu.data.length = 0;</div><div class='del'>-	wrqu.data.flags = 0;</div><div class='del'>-	wireless_send_event(ai-&gt;dev, SIOCGIWSCAN, &amp;wrqu, NULL);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int airo_thread(void *data)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev = data;</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int locked;</div><div class='del'>-</div><div class='del'>-	set_freezable();</div><div class='del'>-	while (1) {</div><div class='del'>-		/* make swsusp happy with our thread */</div><div class='del'>-		try_to_freeze();</div><div class='del'>-</div><div class='del'>-		if (test_bit(JOB_DIE, &amp;ai-&gt;jobs))</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		if (ai-&gt;jobs) {</div><div class='del'>-			locked = down_interruptible(&amp;ai-&gt;sem);</div><div class='del'>-		} else {</div><div class='del'>-			wait_queue_entry_t wait;</div><div class='del'>-</div><div class='del'>-			init_waitqueue_entry(&amp;wait, current);</div><div class='del'>-			add_wait_queue(&amp;ai-&gt;thr_wait, &amp;wait);</div><div class='del'>-			for (;;) {</div><div class='del'>-				set_current_state(TASK_INTERRUPTIBLE);</div><div class='del'>-				if (ai-&gt;jobs)</div><div class='del'>-					break;</div><div class='del'>-				if (ai-&gt;expires || ai-&gt;scan_timeout) {</div><div class='del'>-					if (ai-&gt;scan_timeout &amp;&amp;</div><div class='del'>-							time_after_eq(jiffies, ai-&gt;scan_timeout)) {</div><div class='del'>-						set_bit(JOB_SCAN_RESULTS, &amp;ai-&gt;jobs);</div><div class='del'>-						break;</div><div class='del'>-					} else if (ai-&gt;expires &amp;&amp;</div><div class='del'>-							time_after_eq(jiffies, ai-&gt;expires)) {</div><div class='del'>-						set_bit(JOB_AUTOWEP, &amp;ai-&gt;jobs);</div><div class='del'>-						break;</div><div class='del'>-					}</div><div class='del'>-					if (!kthread_should_stop() &amp;&amp;</div><div class='del'>-					    !freezing(current)) {</div><div class='del'>-						unsigned long wake_at;</div><div class='del'>-						if (!ai-&gt;expires || !ai-&gt;scan_timeout) {</div><div class='del'>-							wake_at = max(ai-&gt;expires,</div><div class='del'>-								ai-&gt;scan_timeout);</div><div class='del'>-						} else {</div><div class='del'>-							wake_at = min(ai-&gt;expires,</div><div class='del'>-								ai-&gt;scan_timeout);</div><div class='del'>-						}</div><div class='del'>-						schedule_timeout(wake_at - jiffies);</div><div class='del'>-						continue;</div><div class='del'>-					}</div><div class='del'>-				} else if (!kthread_should_stop() &amp;&amp;</div><div class='del'>-					   !freezing(current)) {</div><div class='del'>-					schedule();</div><div class='del'>-					continue;</div><div class='del'>-				}</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-			__set_current_state(TASK_RUNNING);</div><div class='del'>-			remove_wait_queue(&amp;ai-&gt;thr_wait, &amp;wait);</div><div class='del'>-			locked = 1;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (locked)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		if (test_bit(JOB_DIE, &amp;ai-&gt;jobs)) {</div><div class='del'>-			up(&amp;ai-&gt;sem);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (ai-&gt;power.event || test_bit(FLAG_FLASHING, &amp;ai-&gt;flags)) {</div><div class='del'>-			up(&amp;ai-&gt;sem);</div><div class='del'>-			continue;</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (test_bit(JOB_XMIT, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_end_xmit(dev, true);</div><div class='del'>-		else if (test_bit(JOB_XMIT11, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_end_xmit11(dev, true);</div><div class='del'>-		else if (test_bit(JOB_STATS, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_read_stats(dev);</div><div class='del'>-		else if (test_bit(JOB_PROMISC, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_set_promisc(ai, true);</div><div class='del'>-		else if (test_bit(JOB_MIC, &amp;ai-&gt;jobs))</div><div class='del'>-			micinit(ai);</div><div class='del'>-		else if (test_bit(JOB_EVENT, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_send_event(dev);</div><div class='del'>-		else if (test_bit(JOB_AUTOWEP, &amp;ai-&gt;jobs))</div><div class='del'>-			timer_func(dev);</div><div class='del'>-		else if (test_bit(JOB_SCAN_RESULTS, &amp;ai-&gt;jobs))</div><div class='del'>-			airo_process_scan_results(ai);</div><div class='del'>-		else  /* Shouldn't get here, but we make sure to unlock */</div><div class='del'>-			up(&amp;ai-&gt;sem);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int header_len(__le16 ctl)</div><div class='del'>-{</div><div class='del'>-	u16 fc = le16_to_cpu(ctl);</div><div class='del'>-	switch (fc &amp; 0xc) {</div><div class='del'>-	case 4:</div><div class='del'>-		if ((fc &amp; 0xe0) == 0xc0)</div><div class='del'>-			return 10;	/* one-address control packet */</div><div class='del'>-		return 16;	/* two-address control packet */</div><div class='del'>-	case 8:</div><div class='del'>-		if ((fc &amp; 0x300) == 0x300)</div><div class='del'>-			return 30;	/* WDS packet */</div><div class='del'>-	}</div><div class='del'>-	return 24;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_handle_cisco_mic(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	if (test_bit(FLAG_MIC_CAPABLE, &amp;ai-&gt;flags)) {</div><div class='del'>-		set_bit(JOB_MIC, &amp;ai-&gt;jobs);</div><div class='del'>-		wake_up_interruptible(&amp;ai-&gt;thr_wait);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Airo Status codes */</div><div class='del'>-#define STAT_NOBEACON	0x8000 /* Loss of sync - missed beacons */</div><div class='del'>-#define STAT_MAXRETRIES	0x8001 /* Loss of sync - max retries */</div><div class='del'>-#define STAT_MAXARL	0x8002 /* Loss of sync - average retry level exceeded*/</div><div class='del'>-#define STAT_FORCELOSS	0x8003 /* Loss of sync - host request */</div><div class='del'>-#define STAT_TSFSYNC	0x8004 /* Loss of sync - TSF synchronization */</div><div class='del'>-#define STAT_DEAUTH	0x8100 /* low byte is 802.11 reason code */</div><div class='del'>-#define STAT_DISASSOC	0x8200 /* low byte is 802.11 reason code */</div><div class='del'>-#define STAT_ASSOC_FAIL	0x8400 /* low byte is 802.11 reason code */</div><div class='del'>-#define STAT_AUTH_FAIL	0x0300 /* low byte is 802.11 reason code */</div><div class='del'>-#define STAT_ASSOC	0x0400 /* Associated */</div><div class='del'>-#define STAT_REASSOC    0x0600 /* Reassociated?  Only on firmware &gt;= 5.30.17 */</div><div class='del'>-</div><div class='del'>-static void airo_print_status(const char *devname, u16 status)</div><div class='del'>-{</div><div class='del'>-	u8 reason = status &amp; 0xFF;</div><div class='del'>-</div><div class='del'>-	switch (status &amp; 0xFF00) {</div><div class='del'>-	case STAT_NOBEACON:</div><div class='del'>-		switch (status) {</div><div class='del'>-		case STAT_NOBEACON:</div><div class='del'>-			airo_print_dbg(devname, "link lost (missed beacons)");</div><div class='del'>-			break;</div><div class='del'>-		case STAT_MAXRETRIES:</div><div class='del'>-		case STAT_MAXARL:</div><div class='del'>-			airo_print_dbg(devname, "link lost (max retries)");</div><div class='del'>-			break;</div><div class='del'>-		case STAT_FORCELOSS:</div><div class='del'>-			airo_print_dbg(devname, "link lost (local choice)");</div><div class='del'>-			break;</div><div class='del'>-		case STAT_TSFSYNC:</div><div class='del'>-			airo_print_dbg(devname, "link lost (TSF sync lost)");</div><div class='del'>-			break;</div><div class='del'>-		default:</div><div class='del'>-			airo_print_dbg(devname, "unknown status %x\n", status);</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-		break;</div><div class='del'>-	case STAT_DEAUTH:</div><div class='del'>-		airo_print_dbg(devname, "deauthenticated (reason: %d)", reason);</div><div class='del'>-		break;</div><div class='del'>-	case STAT_DISASSOC:</div><div class='del'>-		airo_print_dbg(devname, "disassociated (reason: %d)", reason);</div><div class='del'>-		break;</div><div class='del'>-	case STAT_ASSOC_FAIL:</div><div class='del'>-		airo_print_dbg(devname, "association failed (reason: %d)",</div><div class='del'>-			       reason);</div><div class='del'>-		break;</div><div class='del'>-	case STAT_AUTH_FAIL:</div><div class='del'>-		airo_print_dbg(devname, "authentication failed (reason: %d)",</div><div class='del'>-			       reason);</div><div class='del'>-		break;</div><div class='del'>-	case STAT_ASSOC:</div><div class='del'>-	case STAT_REASSOC:</div><div class='del'>-		break;</div><div class='del'>-	default:</div><div class='del'>-		airo_print_dbg(devname, "unknown status %x\n", status);</div><div class='del'>-		break;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_handle_link(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	union iwreq_data wrqu;</div><div class='del'>-	int scan_forceloss = 0;</div><div class='del'>-	u16 status;</div><div class='del'>-</div><div class='del'>-	/* Get new status and acknowledge the link change */</div><div class='del'>-	status = le16_to_cpu(IN4500(ai, LINKSTAT));</div><div class='del'>-	OUT4500(ai, EVACK, EV_LINK);</div><div class='del'>-</div><div class='del'>-	if ((status == STAT_FORCELOSS) &amp;&amp; (ai-&gt;scan_timeout &gt; 0))</div><div class='del'>-		scan_forceloss = 1;</div><div class='del'>-</div><div class='del'>-	airo_print_status(ai-&gt;dev-&gt;name, status);</div><div class='del'>-</div><div class='del'>-	if ((status == STAT_ASSOC) || (status == STAT_REASSOC)) {</div><div class='del'>-		if (auto_wep)</div><div class='del'>-			ai-&gt;expires = 0;</div><div class='del'>-		if (ai-&gt;list_bss_task)</div><div class='del'>-			wake_up_process(ai-&gt;list_bss_task);</div><div class='del'>-		set_bit(FLAG_UPDATE_UNI, &amp;ai-&gt;flags);</div><div class='del'>-		set_bit(FLAG_UPDATE_MULTI, &amp;ai-&gt;flags);</div><div class='del'>-</div><div class='del'>-		set_bit(JOB_EVENT, &amp;ai-&gt;jobs);</div><div class='del'>-		wake_up_interruptible(&amp;ai-&gt;thr_wait);</div><div class='del'>-</div><div class='del'>-		netif_carrier_on(ai-&gt;dev);</div><div class='del'>-	} else if (!scan_forceloss) {</div><div class='del'>-		if (auto_wep &amp;&amp; !ai-&gt;expires) {</div><div class='del'>-			ai-&gt;expires = RUN_AT(3*HZ);</div><div class='del'>-			wake_up_interruptible(&amp;ai-&gt;thr_wait);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Send event to user space */</div><div class='del'>-		eth_zero_addr(wrqu.ap_addr.sa_data);</div><div class='del'>-		wrqu.ap_addr.sa_family = ARPHRD_ETHER;</div><div class='del'>-		wireless_send_event(ai-&gt;dev, SIOCGIWAP, &amp;wrqu, NULL);</div><div class='del'>-		netif_carrier_off(ai-&gt;dev);</div><div class='del'>-	} else {</div><div class='del'>-		netif_carrier_off(ai-&gt;dev);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_handle_rx(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	struct sk_buff *skb = NULL;</div><div class='del'>-	__le16 fc, v, *buffer, tmpbuf[4];</div><div class='del'>-	u16 len, hdrlen = 0, gap, fid;</div><div class='del'>-	struct rx_hdr hdr;</div><div class='del'>-	int success = 0;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MPI, &amp;ai-&gt;flags)) {</div><div class='del'>-		if (test_bit(FLAG_802_11, &amp;ai-&gt;flags))</div><div class='del'>-			mpi_receive_802_11(ai);</div><div class='del'>-		else</div><div class='del'>-			mpi_receive_802_3(ai);</div><div class='del'>-		OUT4500(ai, EVACK, EV_RX);</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	fid = IN4500(ai, RXFID);</div><div class='del'>-</div><div class='del'>-	/* Get the packet length */</div><div class='del'>-	if (test_bit(FLAG_802_11, &amp;ai-&gt;flags)) {</div><div class='del'>-		bap_setup (ai, fid, 4, BAP0);</div><div class='del'>-		bap_read (ai, (__le16*)&amp;hdr, sizeof(hdr), BAP0);</div><div class='del'>-		/* Bad CRC. Ignore packet */</div><div class='del'>-		if (le16_to_cpu(hdr.status) &amp; 2)</div><div class='del'>-			hdr.len = 0;</div><div class='del'>-		if (ai-&gt;wifidev == NULL)</div><div class='del'>-			hdr.len = 0;</div><div class='del'>-	} else {</div><div class='del'>-		bap_setup(ai, fid, 0x36, BAP0);</div><div class='del'>-		bap_read(ai, &amp;hdr.len, 2, BAP0);</div><div class='del'>-	}</div><div class='del'>-	len = le16_to_cpu(hdr.len);</div><div class='del'>-</div><div class='del'>-	if (len &gt; AIRO_DEF_MTU) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Bad size %d", len);</div><div class='del'>-		goto done;</div><div class='del'>-	}</div><div class='del'>-	if (len == 0)</div><div class='del'>-		goto done;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_802_11, &amp;ai-&gt;flags)) {</div><div class='del'>-		bap_read(ai, &amp;fc, sizeof (fc), BAP0);</div><div class='del'>-		hdrlen = header_len(fc);</div><div class='del'>-	} else</div><div class='del'>-		hdrlen = ETH_ALEN * 2;</div><div class='del'>-</div><div class='del'>-	skb = dev_alloc_skb(len + hdrlen + 2 + 2);</div><div class='del'>-	if (!skb) {</div><div class='del'>-		ai-&gt;dev-&gt;stats.rx_dropped++;</div><div class='del'>-		goto done;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	skb_reserve(skb, 2); /* This way the IP header is aligned */</div><div class='del'>-	buffer = skb_put(skb, len + hdrlen);</div><div class='del'>-	if (test_bit(FLAG_802_11, &amp;ai-&gt;flags)) {</div><div class='del'>-		buffer[0] = fc;</div><div class='del'>-		bap_read(ai, buffer + 1, hdrlen - 2, BAP0);</div><div class='del'>-		if (hdrlen == 24)</div><div class='del'>-			bap_read(ai, tmpbuf, 6, BAP0);</div><div class='del'>-</div><div class='del'>-		bap_read(ai, &amp;v, sizeof(v), BAP0);</div><div class='del'>-		gap = le16_to_cpu(v);</div><div class='del'>-		if (gap) {</div><div class='del'>-			if (gap &lt;= 8) {</div><div class='del'>-				bap_read(ai, tmpbuf, gap, BAP0);</div><div class='del'>-			} else {</div><div class='del'>-				airo_print_err(ai-&gt;dev-&gt;name, "gaplen too "</div><div class='del'>-					"big. Problems will follow...");</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		bap_read(ai, buffer + hdrlen/2, len, BAP0);</div><div class='del'>-	} else {</div><div class='del'>-		MICBuffer micbuf;</div><div class='del'>-</div><div class='del'>-		bap_read(ai, buffer, ETH_ALEN * 2, BAP0);</div><div class='del'>-		if (ai-&gt;micstats.enabled) {</div><div class='del'>-			bap_read(ai, (__le16 *) &amp;micbuf, sizeof (micbuf), BAP0);</div><div class='del'>-			if (ntohs(micbuf.typelen) &gt; 0x05DC)</div><div class='del'>-				bap_setup(ai, fid, 0x44, BAP0);</div><div class='del'>-			else {</div><div class='del'>-				if (len &lt;= sizeof (micbuf)) {</div><div class='del'>-					dev_kfree_skb_irq(skb);</div><div class='del'>-					goto done;</div><div class='del'>-				}</div><div class='del'>-</div><div class='del'>-				len -= sizeof(micbuf);</div><div class='del'>-				skb_trim(skb, len + hdrlen);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		bap_read(ai, buffer + ETH_ALEN, len, BAP0);</div><div class='del'>-		if (decapsulate(ai, &amp;micbuf, (etherHead*) buffer, len))</div><div class='del'>-			dev_kfree_skb_irq (skb);</div><div class='del'>-		else</div><div class='del'>-			success = 1;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-#ifdef WIRELESS_SPY</div><div class='del'>-	if (success &amp;&amp; (ai-&gt;spy_data.spy_number &gt; 0)) {</div><div class='del'>-		char *sa;</div><div class='del'>-		struct iw_quality wstats;</div><div class='del'>-</div><div class='del'>-		/* Prepare spy data : addr + qual */</div><div class='del'>-		if (!test_bit(FLAG_802_11, &amp;ai-&gt;flags)) {</div><div class='del'>-			sa = (char *) buffer + 6;</div><div class='del'>-			bap_setup(ai, fid, 8, BAP0);</div><div class='del'>-			bap_read(ai, (__le16 *) hdr.rssi, 2, BAP0);</div><div class='del'>-		} else</div><div class='del'>-			sa = (char *) buffer + 10;</div><div class='del'>-		wstats.qual = hdr.rssi[0];</div><div class='del'>-		if (ai-&gt;rssi)</div><div class='del'>-			wstats.level = 0x100 - ai-&gt;rssi[hdr.rssi[1]].rssidBm;</div><div class='del'>-		else</div><div class='del'>-			wstats.level = (hdr.rssi[1] + 321) / 2;</div><div class='del'>-		wstats.noise = ai-&gt;wstats.qual.noise;</div><div class='del'>-		wstats.updated =  IW_QUAL_LEVEL_UPDATED</div><div class='del'>-				| IW_QUAL_QUAL_UPDATED</div><div class='del'>-				| IW_QUAL_DBM;</div><div class='del'>-		/* Update spy records */</div><div class='del'>-		wireless_spy_update(ai-&gt;dev, sa, &amp;wstats);</div><div class='del'>-	}</div><div class='del'>-#endif /* WIRELESS_SPY */</div><div class='del'>-</div><div class='del'>-done:</div><div class='del'>-	OUT4500(ai, EVACK, EV_RX);</div><div class='del'>-</div><div class='del'>-	if (success) {</div><div class='del'>-		if (test_bit(FLAG_802_11, &amp;ai-&gt;flags)) {</div><div class='del'>-			skb_reset_mac_header(skb);</div><div class='del'>-			skb-&gt;pkt_type = PACKET_OTHERHOST;</div><div class='del'>-			skb-&gt;dev = ai-&gt;wifidev;</div><div class='del'>-			skb-&gt;protocol = htons(ETH_P_802_2);</div><div class='del'>-		} else</div><div class='del'>-			skb-&gt;protocol = eth_type_trans(skb, ai-&gt;dev);</div><div class='del'>-		skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='del'>-</div><div class='del'>-		netif_rx(skb);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void airo_handle_tx(struct airo_info *ai, u16 status)</div><div class='del'>-{</div><div class='del'>-	int i, index = -1;</div><div class='del'>-	u16 fid;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MPI, &amp;ai-&gt;flags)) {</div><div class='del'>-		unsigned long flags;</div><div class='del'>-</div><div class='del'>-		if (status &amp; EV_TXEXC)</div><div class='del'>-			get_tx_error(ai, -1);</div><div class='del'>-</div><div class='del'>-		spin_lock_irqsave(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-		if (!skb_queue_empty(&amp;ai-&gt;txq)) {</div><div class='del'>-			spin_unlock_irqrestore(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-			mpi_send_packet(ai-&gt;dev);</div><div class='del'>-		} else {</div><div class='del'>-			clear_bit(FLAG_PENDING_XMIT, &amp;ai-&gt;flags);</div><div class='del'>-			spin_unlock_irqrestore(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-			netif_wake_queue(ai-&gt;dev);</div><div class='del'>-		}</div><div class='del'>-		OUT4500(ai, EVACK, status &amp; (EV_TX | EV_TXCPY | EV_TXEXC));</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	fid = IN4500(ai, TXCOMPLFID);</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; MAX_FIDS; i++) {</div><div class='del'>-		if ((ai-&gt;fids[i] &amp; 0xffff) == fid)</div><div class='del'>-			index = i;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (index != -1) {</div><div class='del'>-		if (status &amp; EV_TXEXC)</div><div class='del'>-			get_tx_error(ai, index);</div><div class='del'>-</div><div class='del'>-		OUT4500(ai, EVACK, status &amp; (EV_TX | EV_TXEXC));</div><div class='del'>-</div><div class='del'>-		/* Set up to be used again */</div><div class='del'>-		ai-&gt;fids[index] &amp;= 0xffff;</div><div class='del'>-		if (index &lt; MAX_FIDS / 2) {</div><div class='del'>-			if (!test_bit(FLAG_PENDING_XMIT, &amp;ai-&gt;flags))</div><div class='del'>-				netif_wake_queue(ai-&gt;dev);</div><div class='del'>-		} else {</div><div class='del'>-			if (!test_bit(FLAG_PENDING_XMIT11, &amp;ai-&gt;flags))</div><div class='del'>-				netif_wake_queue(ai-&gt;wifidev);</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		OUT4500(ai, EVACK, status &amp; (EV_TX | EV_TXCPY | EV_TXEXC));</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Unallocated FID was used to xmit");</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static irqreturn_t airo_interrupt(int irq, void *dev_id)</div><div class='del'>-{</div><div class='del'>-	struct net_device *dev = dev_id;</div><div class='del'>-	u16 status, savedInterrupts = 0;</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int handled = 0;</div><div class='del'>-</div><div class='del'>-	if (!netif_device_present(dev))</div><div class='del'>-		return IRQ_NONE;</div><div class='del'>-</div><div class='del'>-	for (;;) {</div><div class='del'>-		status = IN4500(ai, EVSTAT);</div><div class='del'>-		if (!(status &amp; STATUS_INTS) || (status == 0xffff))</div><div class='del'>-			break;</div><div class='del'>-</div><div class='del'>-		handled = 1;</div><div class='del'>-</div><div class='del'>-		if (status &amp; EV_AWAKE) {</div><div class='del'>-			OUT4500(ai, EVACK, EV_AWAKE);</div><div class='del'>-			OUT4500(ai, EVACK, EV_AWAKE);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (!savedInterrupts) {</div><div class='del'>-			savedInterrupts = IN4500(ai, EVINTEN);</div><div class='del'>-			OUT4500(ai, EVINTEN, 0);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (status &amp; EV_MIC) {</div><div class='del'>-			OUT4500(ai, EVACK, EV_MIC);</div><div class='del'>-			airo_handle_cisco_mic(ai);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		if (status &amp; EV_LINK) {</div><div class='del'>-			/* Link status changed */</div><div class='del'>-			airo_handle_link(ai);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-		/* Check to see if there is something to receive */</div><div class='del'>-		if (status &amp; EV_RX)</div><div class='del'>-			airo_handle_rx(ai);</div><div class='del'>-</div><div class='del'>-		/* Check to see if a packet has been transmitted */</div><div class='del'>-		if (status &amp; (EV_TX | EV_TXCPY | EV_TXEXC))</div><div class='del'>-			airo_handle_tx(ai, status);</div><div class='del'>-</div><div class='del'>-		if (status &amp; ~STATUS_INTS &amp; ~IGNORE_INTS) {</div><div class='del'>-			airo_print_warn(ai-&gt;dev-&gt;name, "Got weird status %x",</div><div class='del'>-				status &amp; ~STATUS_INTS &amp; ~IGNORE_INTS);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (savedInterrupts)</div><div class='del'>-		OUT4500(ai, EVINTEN, savedInterrupts);</div><div class='del'>-</div><div class='del'>-	return IRQ_RETVAL(handled);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  Routines to talk to the card</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  This was originally written for the 4500, hence the name</div><div class='del'>- *  NOTE:  If use with 8bit mode and SMP bad things will happen!</div><div class='del'>- *         Why would some one do 8 bit IO in an SMP machine?!?</div><div class='del'>- */</div><div class='del'>-static void OUT4500(struct airo_info *ai, u16 reg, u16 val)</div><div class='del'>-{</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags))</div><div class='del'>-		reg &lt;&lt;= 1;</div><div class='del'>-	if (!do8bitIO)</div><div class='del'>-		outw(val, ai-&gt;dev-&gt;base_addr + reg);</div><div class='del'>-	else {</div><div class='del'>-		outb(val &amp; 0xff, ai-&gt;dev-&gt;base_addr + reg);</div><div class='del'>-		outb(val &gt;&gt; 8, ai-&gt;dev-&gt;base_addr + reg + 1);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u16 IN4500(struct airo_info *ai, u16 reg)</div><div class='del'>-{</div><div class='del'>-	unsigned short rc;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags))</div><div class='del'>-		reg &lt;&lt;= 1;</div><div class='del'>-	if (!do8bitIO)</div><div class='del'>-		rc = inw(ai-&gt;dev-&gt;base_addr + reg);</div><div class='del'>-	else {</div><div class='del'>-		rc = inb(ai-&gt;dev-&gt;base_addr + reg);</div><div class='del'>-		rc += ((int)inb(ai-&gt;dev-&gt;base_addr + reg + 1)) &lt;&lt; 8;</div><div class='del'>-	}</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int enable_MAC(struct airo_info *ai, int lock)</div><div class='del'>-{</div><div class='del'>-	int rc;</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-</div><div class='del'>-	/* FLAG_RADIO_OFF : Radio disabled via /proc or Wireless Extensions</div><div class='del'>-	 * FLAG_RADIO_DOWN : Radio disabled via "ifconfig ethX down"</div><div class='del'>-	 * Note : we could try to use !netif_running(dev) in enable_MAC()</div><div class='del'>-	 * instead of this flag, but I don't trust it *within* the</div><div class='del'>-	 * open/close functions, and testing both flags together is</div><div class='del'>-	 * "cheaper" - Jean II */</div><div class='del'>-	if (ai-&gt;flags &amp; FLAG_RADIO_MASK) return SUCCESS;</div><div class='del'>-</div><div class='del'>-	if (lock &amp;&amp; down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-		return -ERESTARTSYS;</div><div class='del'>-</div><div class='del'>-	if (!test_bit(FLAG_ENABLED, &amp;ai-&gt;flags)) {</div><div class='del'>-		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-		cmd.cmd = MAC_ENABLE;</div><div class='del'>-		rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-		if (rc == SUCCESS)</div><div class='del'>-			set_bit(FLAG_ENABLED, &amp;ai-&gt;flags);</div><div class='del'>-	} else</div><div class='del'>-		rc = SUCCESS;</div><div class='del'>-</div><div class='del'>-	if (lock)</div><div class='del'>-	    up(&amp;ai-&gt;sem);</div><div class='del'>-</div><div class='del'>-	if (rc)</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Cannot enable MAC");</div><div class='del'>-	else if ((rsp.status &amp; 0xFF00) != 0) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Bad MAC enable reason=%x, "</div><div class='del'>-			"rid=%x, offset=%d", rsp.rsp0, rsp.rsp1, rsp.rsp2);</div><div class='del'>-		rc = ERROR;</div><div class='del'>-	}</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void disable_MAC(struct airo_info *ai, int lock)</div><div class='del'>-{</div><div class='del'>-        Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-</div><div class='del'>-	if (lock == 1 &amp;&amp; down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_ENABLED, &amp;ai-&gt;flags)) {</div><div class='del'>-		if (lock != 2) /* lock == 2 means don't disable carrier */</div><div class='del'>-			netif_carrier_off(ai-&gt;dev);</div><div class='del'>-		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-		cmd.cmd = MAC_DISABLE; // disable in case already enabled</div><div class='del'>-		issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-		clear_bit(FLAG_ENABLED, &amp;ai-&gt;flags);</div><div class='del'>-	}</div><div class='del'>-	if (lock == 1)</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void enable_interrupts(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	/* Enable the interrupts */</div><div class='del'>-	OUT4500(ai, EVINTEN, STATUS_INTS);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void disable_interrupts(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	OUT4500(ai, EVINTEN, 0);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mpi_receive_802_3(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	RxFid rxd;</div><div class='del'>-	int len = 0;</div><div class='del'>-	struct sk_buff *skb;</div><div class='del'>-	char *buffer;</div><div class='del'>-	int off = 0;</div><div class='del'>-	MICBuffer micbuf;</div><div class='del'>-</div><div class='del'>-	memcpy_fromio(&amp;rxd, ai-&gt;rxfids[0].card_ram_off, sizeof(rxd));</div><div class='del'>-	/* Make sure we got something */</div><div class='del'>-	if (rxd.rdy &amp;&amp; rxd.valid == 0) {</div><div class='del'>-		len = rxd.len + 12;</div><div class='del'>-		if (len &lt; 12 || len &gt; 2048)</div><div class='del'>-			goto badrx;</div><div class='del'>-</div><div class='del'>-		skb = dev_alloc_skb(len);</div><div class='del'>-		if (!skb) {</div><div class='del'>-			ai-&gt;dev-&gt;stats.rx_dropped++;</div><div class='del'>-			goto badrx;</div><div class='del'>-		}</div><div class='del'>-		buffer = skb_put(skb, len);</div><div class='del'>-		memcpy(buffer, ai-&gt;rxfids[0].virtual_host_addr, ETH_ALEN * 2);</div><div class='del'>-		if (ai-&gt;micstats.enabled) {</div><div class='del'>-			memcpy(&amp;micbuf,</div><div class='del'>-				ai-&gt;rxfids[0].virtual_host_addr + ETH_ALEN * 2,</div><div class='del'>-				sizeof(micbuf));</div><div class='del'>-			if (ntohs(micbuf.typelen) &lt;= 0x05DC) {</div><div class='del'>-				if (len &lt;= sizeof(micbuf) + ETH_ALEN * 2)</div><div class='del'>-					goto badmic;</div><div class='del'>-</div><div class='del'>-				off = sizeof(micbuf);</div><div class='del'>-				skb_trim (skb, len - off);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-		memcpy(buffer + ETH_ALEN * 2,</div><div class='del'>-			ai-&gt;rxfids[0].virtual_host_addr + ETH_ALEN * 2 + off,</div><div class='del'>-			len - ETH_ALEN * 2 - off);</div><div class='del'>-		if (decapsulate (ai, &amp;micbuf, (etherHead*)buffer, len - off - ETH_ALEN * 2)) {</div><div class='del'>-badmic:</div><div class='del'>-			dev_kfree_skb_irq (skb);</div><div class='del'>-			goto badrx;</div><div class='del'>-		}</div><div class='del'>-#ifdef WIRELESS_SPY</div><div class='del'>-		if (ai-&gt;spy_data.spy_number &gt; 0) {</div><div class='del'>-			char *sa;</div><div class='del'>-			struct iw_quality wstats;</div><div class='del'>-			/* Prepare spy data : addr + qual */</div><div class='del'>-			sa = buffer + ETH_ALEN;</div><div class='del'>-			wstats.qual = 0; /* XXX Where do I get that info from ??? */</div><div class='del'>-			wstats.level = 0;</div><div class='del'>-			wstats.updated = 0;</div><div class='del'>-			/* Update spy records */</div><div class='del'>-			wireless_spy_update(ai-&gt;dev, sa, &amp;wstats);</div><div class='del'>-		}</div><div class='del'>-#endif /* WIRELESS_SPY */</div><div class='del'>-</div><div class='del'>-		skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='del'>-		skb-&gt;protocol = eth_type_trans(skb, ai-&gt;dev);</div><div class='del'>-		netif_rx(skb);</div><div class='del'>-	}</div><div class='del'>-badrx:</div><div class='del'>-	if (rxd.valid == 0) {</div><div class='del'>-		rxd.valid = 1;</div><div class='del'>-		rxd.rdy = 0;</div><div class='del'>-		rxd.len = PKTSIZE;</div><div class='del'>-		memcpy_toio(ai-&gt;rxfids[0].card_ram_off, &amp;rxd, sizeof(rxd));</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void mpi_receive_802_11(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	RxFid rxd;</div><div class='del'>-	struct sk_buff *skb = NULL;</div><div class='del'>-	u16 len, hdrlen = 0;</div><div class='del'>-	__le16 fc;</div><div class='del'>-	struct rx_hdr hdr;</div><div class='del'>-	u16 gap;</div><div class='del'>-	u16 *buffer;</div><div class='del'>-	char *ptr = ai-&gt;rxfids[0].virtual_host_addr + 4;</div><div class='del'>-</div><div class='del'>-	memcpy_fromio(&amp;rxd, ai-&gt;rxfids[0].card_ram_off, sizeof(rxd));</div><div class='del'>-	memcpy ((char *)&amp;hdr, ptr, sizeof(hdr));</div><div class='del'>-	ptr += sizeof(hdr);</div><div class='del'>-	/* Bad CRC. Ignore packet */</div><div class='del'>-	if (le16_to_cpu(hdr.status) &amp; 2)</div><div class='del'>-		hdr.len = 0;</div><div class='del'>-	if (ai-&gt;wifidev == NULL)</div><div class='del'>-		hdr.len = 0;</div><div class='del'>-	len = le16_to_cpu(hdr.len);</div><div class='del'>-	if (len &gt; AIRO_DEF_MTU) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "Bad size %d", len);</div><div class='del'>-		goto badrx;</div><div class='del'>-	}</div><div class='del'>-	if (len == 0)</div><div class='del'>-		goto badrx;</div><div class='del'>-</div><div class='del'>-	fc = get_unaligned((__le16 *)ptr);</div><div class='del'>-	hdrlen = header_len(fc);</div><div class='del'>-</div><div class='del'>-	skb = dev_alloc_skb(len + hdrlen + 2);</div><div class='del'>-	if (!skb) {</div><div class='del'>-		ai-&gt;dev-&gt;stats.rx_dropped++;</div><div class='del'>-		goto badrx;</div><div class='del'>-	}</div><div class='del'>-	buffer = skb_put(skb, len + hdrlen);</div><div class='del'>-	memcpy ((char *)buffer, ptr, hdrlen);</div><div class='del'>-	ptr += hdrlen;</div><div class='del'>-	if (hdrlen == 24)</div><div class='del'>-		ptr += 6;</div><div class='del'>-	gap = get_unaligned_le16(ptr);</div><div class='del'>-	ptr += sizeof(__le16);</div><div class='del'>-	if (gap) {</div><div class='del'>-		if (gap &lt;= 8)</div><div class='del'>-			ptr += gap;</div><div class='del'>-		else</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-			    "gaplen too big. Problems will follow...");</div><div class='del'>-	}</div><div class='del'>-	memcpy ((char *)buffer + hdrlen, ptr, len);</div><div class='del'>-	ptr += len;</div><div class='del'>-#ifdef IW_WIRELESS_SPY	  /* defined in iw_handler.h */</div><div class='del'>-	if (ai-&gt;spy_data.spy_number &gt; 0) {</div><div class='del'>-		char *sa;</div><div class='del'>-		struct iw_quality wstats;</div><div class='del'>-		/* Prepare spy data : addr + qual */</div><div class='del'>-		sa = (char*)buffer + 10;</div><div class='del'>-		wstats.qual = hdr.rssi[0];</div><div class='del'>-		if (ai-&gt;rssi)</div><div class='del'>-			wstats.level = 0x100 - ai-&gt;rssi[hdr.rssi[1]].rssidBm;</div><div class='del'>-		else</div><div class='del'>-			wstats.level = (hdr.rssi[1] + 321) / 2;</div><div class='del'>-		wstats.noise = ai-&gt;wstats.qual.noise;</div><div class='del'>-		wstats.updated = IW_QUAL_QUAL_UPDATED</div><div class='del'>-			| IW_QUAL_LEVEL_UPDATED</div><div class='del'>-			| IW_QUAL_DBM;</div><div class='del'>-		/* Update spy records */</div><div class='del'>-		wireless_spy_update(ai-&gt;dev, sa, &amp;wstats);</div><div class='del'>-	}</div><div class='del'>-#endif /* IW_WIRELESS_SPY */</div><div class='del'>-	skb_reset_mac_header(skb);</div><div class='del'>-	skb-&gt;pkt_type = PACKET_OTHERHOST;</div><div class='del'>-	skb-&gt;dev = ai-&gt;wifidev;</div><div class='del'>-	skb-&gt;protocol = htons(ETH_P_802_2);</div><div class='del'>-	skb-&gt;ip_summed = CHECKSUM_NONE;</div><div class='del'>-	netif_rx(skb);</div><div class='del'>-</div><div class='del'>-badrx:</div><div class='del'>-	if (rxd.valid == 0) {</div><div class='del'>-		rxd.valid = 1;</div><div class='del'>-		rxd.rdy = 0;</div><div class='del'>-		rxd.len = PKTSIZE;</div><div class='del'>-		memcpy_toio(ai-&gt;rxfids[0].card_ram_off, &amp;rxd, sizeof(rxd));</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static inline void set_auth_type(struct airo_info *local, int auth_type)</div><div class='del'>-{</div><div class='del'>-	local-&gt;config.authType = auth_type;</div><div class='del'>-	/* Cache the last auth type used (of AUTH_OPEN and AUTH_ENCRYPT).</div><div class='del'>-	 * Used by airo_set_auth()</div><div class='del'>-	 */</div><div class='del'>-	if (auth_type == AUTH_OPEN || auth_type == AUTH_ENCRYPT)</div><div class='del'>-		local-&gt;last_auth = auth_type;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int noinline_for_stack airo_readconfig(struct airo_info *ai,</div><div class='del'>-					      struct net_device *dev, int lock)</div><div class='del'>-{</div><div class='del'>-	int i, status;</div><div class='del'>-	/* large variables, so don't inline this function,</div><div class='del'>-	 * maybe change to kmalloc</div><div class='del'>-	 */</div><div class='del'>-	tdsRssiRid rssi_rid;</div><div class='del'>-	CapabilityRid cap_rid;</div><div class='del'>-</div><div class='del'>-	kfree(ai-&gt;SSID);</div><div class='del'>-	ai-&gt;SSID = NULL;</div><div class='del'>-	// general configuration (read/modify/write)</div><div class='del'>-	status = readConfigRid(ai, lock);</div><div class='del'>-	if (status != SUCCESS) return ERROR;</div><div class='del'>-</div><div class='del'>-	status = readCapabilityRid(ai, &amp;cap_rid, lock);</div><div class='del'>-	if (status != SUCCESS) return ERROR;</div><div class='del'>-</div><div class='del'>-	status = PC4500_readrid(ai, RID_RSSI, &amp;rssi_rid, sizeof(rssi_rid), lock);</div><div class='del'>-	if (status == SUCCESS) {</div><div class='del'>-		if (ai-&gt;rssi || (ai-&gt;rssi = kmalloc(512, GFP_KERNEL)) != NULL)</div><div class='del'>-			memcpy(ai-&gt;rssi, (u8*)&amp;rssi_rid + 2, 512); /* Skip RID length member */</div><div class='del'>-	}</div><div class='del'>-	else {</div><div class='del'>-		kfree(ai-&gt;rssi);</div><div class='del'>-		ai-&gt;rssi = NULL;</div><div class='del'>-		if (cap_rid.softCap &amp; cpu_to_le16(8))</div><div class='del'>-			ai-&gt;config.rmode |= RXMODE_NORMALIZED_RSSI;</div><div class='del'>-		else</div><div class='del'>-			airo_print_warn(ai-&gt;dev-&gt;name, "unknown received signal "</div><div class='del'>-					"level scale");</div><div class='del'>-	}</div><div class='del'>-	ai-&gt;config.opmode = adhoc ? MODE_STA_IBSS : MODE_STA_ESS;</div><div class='del'>-	set_auth_type(ai, AUTH_OPEN);</div><div class='del'>-	ai-&gt;config.modulation = MOD_CCK;</div><div class='del'>-</div><div class='del'>-	if (le16_to_cpu(cap_rid.len) &gt;= sizeof(cap_rid) &amp;&amp;</div><div class='del'>-	    (cap_rid.extSoftCap &amp; cpu_to_le16(1)) &amp;&amp;</div><div class='del'>-	    micsetup(ai) == SUCCESS) {</div><div class='del'>-		ai-&gt;config.opmode |= MODE_MIC;</div><div class='del'>-		set_bit(FLAG_MIC_CAPABLE, &amp;ai-&gt;flags);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Save off the MAC */</div><div class='del'>-	eth_hw_addr_set(dev, ai-&gt;config.macAddr);</div><div class='del'>-</div><div class='del'>-	/* Check to see if there are any insmod configured</div><div class='del'>-	   rates to add */</div><div class='del'>-	if (rates[0]) {</div><div class='del'>-		memset(ai-&gt;config.rates, 0, sizeof(ai-&gt;config.rates));</div><div class='del'>-		for (i = 0; i &lt; 8 &amp;&amp; rates[i]; i++) {</div><div class='del'>-			ai-&gt;config.rates[i] = rates[i];</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-static u16 setup_card(struct airo_info *ai, struct net_device *dev, int lock)</div><div class='del'>-{</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-	int status;</div><div class='del'>-	SsidRid mySsid;</div><div class='del'>-	__le16 lastindex;</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	memset(&amp;mySsid, 0, sizeof(mySsid));</div><div class='del'>-	kfree (ai-&gt;flash);</div><div class='del'>-	ai-&gt;flash = NULL;</div><div class='del'>-</div><div class='del'>-	/* The NOP is the first step in getting the card going */</div><div class='del'>-	cmd.cmd = NOP;</div><div class='del'>-	cmd.parm0 = cmd.parm1 = cmd.parm2 = 0;</div><div class='del'>-	if (lock &amp;&amp; down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-		return ERROR;</div><div class='del'>-	if (issuecommand(ai, &amp;cmd, &amp;rsp, true) != SUCCESS) {</div><div class='del'>-		if (lock)</div><div class='del'>-			up(&amp;ai-&gt;sem);</div><div class='del'>-		return ERROR;</div><div class='del'>-	}</div><div class='del'>-	disable_MAC(ai, 0);</div><div class='del'>-</div><div class='del'>-	// Let's figure out if we need to use the AUX port</div><div class='del'>-	if (!test_bit(FLAG_MPI,&amp;ai-&gt;flags)) {</div><div class='del'>-		cmd.cmd = CMD_ENABLEAUX;</div><div class='del'>-		if (issuecommand(ai, &amp;cmd, &amp;rsp, true) != SUCCESS) {</div><div class='del'>-			if (lock)</div><div class='del'>-				up(&amp;ai-&gt;sem);</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name, "Error checking for AUX port");</div><div class='del'>-			return ERROR;</div><div class='del'>-		}</div><div class='del'>-		if (!aux_bap || rsp.status &amp; 0xff00) {</div><div class='del'>-			ai-&gt;bap_read = fast_bap_read;</div><div class='del'>-			airo_print_dbg(ai-&gt;dev-&gt;name, "Doing fast bap_reads");</div><div class='del'>-		} else {</div><div class='del'>-			ai-&gt;bap_read = aux_bap_read;</div><div class='del'>-			airo_print_dbg(ai-&gt;dev-&gt;name, "Doing AUX bap_reads");</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	if (lock)</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-	if (ai-&gt;config.len == 0) {</div><div class='del'>-		status = airo_readconfig(ai, dev, lock);</div><div class='del'>-		if (status != SUCCESS)</div><div class='del'>-			return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* Setup the SSIDs if present */</div><div class='del'>-	if (ssids[0]) {</div><div class='del'>-		int i;</div><div class='del'>-		for (i = 0; i &lt; 3 &amp;&amp; ssids[i]; i++) {</div><div class='del'>-			size_t len = strlen(ssids[i]);</div><div class='del'>-			if (len &gt; 32)</div><div class='del'>-				len = 32;</div><div class='del'>-			mySsid.ssids[i].len = cpu_to_le16(len);</div><div class='del'>-			memcpy(mySsid.ssids[i].ssid, ssids[i], len);</div><div class='del'>-		}</div><div class='del'>-		mySsid.len = cpu_to_le16(sizeof(mySsid));</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	status = writeConfigRid(ai, lock);</div><div class='del'>-	if (status != SUCCESS) return ERROR;</div><div class='del'>-</div><div class='del'>-	/* Set up the SSID list */</div><div class='del'>-	if (ssids[0]) {</div><div class='del'>-		status = writeSsidRid(ai, &amp;mySsid, lock);</div><div class='del'>-		if (status != SUCCESS) return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	status = enable_MAC(ai, lock);</div><div class='del'>-	if (status != SUCCESS)</div><div class='del'>-		return ERROR;</div><div class='del'>-</div><div class='del'>-	/* Grab the initial wep key, we gotta save it for auto_wep */</div><div class='del'>-	rc = readWepKeyRid(ai, &amp;wkr, 1, lock);</div><div class='del'>-	if (rc == SUCCESS) do {</div><div class='del'>-		lastindex = wkr.kindex;</div><div class='del'>-		if (wkr.kindex == cpu_to_le16(0xffff)) {</div><div class='del'>-			ai-&gt;defindex = wkr.mac[0];</div><div class='del'>-		}</div><div class='del'>-		rc = readWepKeyRid(ai, &amp;wkr, 0, lock);</div><div class='del'>-	} while (lastindex != wkr.kindex);</div><div class='del'>-</div><div class='del'>-	try_auto_wep(ai);</div><div class='del'>-</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static u16 issuecommand(struct airo_info *ai, Cmd *pCmd, Resp *pRsp,</div><div class='del'>-			bool may_sleep)</div><div class='del'>-{</div><div class='del'>-        // Im really paranoid about letting it run forever!</div><div class='del'>-	int max_tries = 600000;</div><div class='del'>-</div><div class='del'>-	if (IN4500(ai, EVSTAT) &amp; EV_CMD)</div><div class='del'>-		OUT4500(ai, EVACK, EV_CMD);</div><div class='del'>-</div><div class='del'>-	OUT4500(ai, PARAM0, pCmd-&gt;parm0);</div><div class='del'>-	OUT4500(ai, PARAM1, pCmd-&gt;parm1);</div><div class='del'>-	OUT4500(ai, PARAM2, pCmd-&gt;parm2);</div><div class='del'>-	OUT4500(ai, COMMAND, pCmd-&gt;cmd);</div><div class='del'>-</div><div class='del'>-	while (max_tries-- &amp;&amp; (IN4500(ai, EVSTAT) &amp; EV_CMD) == 0) {</div><div class='del'>-		if ((IN4500(ai, COMMAND)) == pCmd-&gt;cmd)</div><div class='del'>-			// PC4500 didn't notice command, try again</div><div class='del'>-			OUT4500(ai, COMMAND, pCmd-&gt;cmd);</div><div class='del'>-		if (may_sleep &amp;&amp; (max_tries &amp; 255) == 0)</div><div class='del'>-			cond_resched();</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	if (max_tries == -1) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-			"Max tries exceeded when issuing command");</div><div class='del'>-		if (IN4500(ai, COMMAND) &amp; COMMAND_BUSY)</div><div class='del'>-			OUT4500(ai, EVACK, EV_CLEARCOMMANDBUSY);</div><div class='del'>-		return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	// command completed</div><div class='del'>-	pRsp-&gt;status = IN4500(ai, STATUS);</div><div class='del'>-	pRsp-&gt;rsp0 = IN4500(ai, RESP0);</div><div class='del'>-	pRsp-&gt;rsp1 = IN4500(ai, RESP1);</div><div class='del'>-	pRsp-&gt;rsp2 = IN4500(ai, RESP2);</div><div class='del'>-	if ((pRsp-&gt;status &amp; 0xff00)!=0 &amp;&amp; pCmd-&gt;cmd != CMD_SOFTRESET)</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-			"cmd:%x status:%x rsp0:%x rsp1:%x rsp2:%x",</div><div class='del'>-			pCmd-&gt;cmd, pRsp-&gt;status, pRsp-&gt;rsp0, pRsp-&gt;rsp1,</div><div class='del'>-			pRsp-&gt;rsp2);</div><div class='del'>-</div><div class='del'>-	// clear stuck command busy if necessary</div><div class='del'>-	if (IN4500(ai, COMMAND) &amp; COMMAND_BUSY) {</div><div class='del'>-		OUT4500(ai, EVACK, EV_CLEARCOMMANDBUSY);</div><div class='del'>-	}</div><div class='del'>-	// acknowledge processing the status/response</div><div class='del'>-	OUT4500(ai, EVACK, EV_CMD);</div><div class='del'>-</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Sets up the bap to start exchange data.  whichbap should</div><div class='del'>- * be one of the BAP0 or BAP1 defines.  Locks should be held before</div><div class='del'>- * calling! */</div><div class='del'>-static int bap_setup(struct airo_info *ai, u16 rid, u16 offset, int whichbap)</div><div class='del'>-{</div><div class='del'>-	int timeout = 50;</div><div class='del'>-	int max_tries = 3;</div><div class='del'>-</div><div class='del'>-	OUT4500(ai, SELECT0+whichbap, rid);</div><div class='del'>-	OUT4500(ai, OFFSET0+whichbap, offset);</div><div class='del'>-	while (1) {</div><div class='del'>-		int status = IN4500(ai, OFFSET0+whichbap);</div><div class='del'>-		if (status &amp; BAP_BUSY) {</div><div class='del'>-                        /* This isn't really a timeout, but its kinda</div><div class='del'>-			   close */</div><div class='del'>-			if (timeout--) {</div><div class='del'>-				continue;</div><div class='del'>-			}</div><div class='del'>-		} else if (status &amp; BAP_ERR) {</div><div class='del'>-			/* invalid rid or offset */</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name, "BAP error %x %d",</div><div class='del'>-				status, whichbap);</div><div class='del'>-			return ERROR;</div><div class='del'>-		} else if (status &amp; BAP_DONE) { // success</div><div class='del'>-			return SUCCESS;</div><div class='del'>-		}</div><div class='del'>-		if (!(max_tries--)) {</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-				"BAP setup error too many retries\n");</div><div class='del'>-			return ERROR;</div><div class='del'>-		}</div><div class='del'>-		// -- PC4500 missed it, try again</div><div class='del'>-		OUT4500(ai, SELECT0+whichbap, rid);</div><div class='del'>-		OUT4500(ai, OFFSET0+whichbap, offset);</div><div class='del'>-		timeout = 50;</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* should only be called by aux_bap_read.  This aux function and the</div><div class='del'>-   following use concepts not documented in the developers guide.  I</div><div class='del'>-   got them from a patch given to my by Aironet */</div><div class='del'>-static u16 aux_setup(struct airo_info *ai, u16 page,</div><div class='del'>-		     u16 offset, u16 *len)</div><div class='del'>-{</div><div class='del'>-	u16 next;</div><div class='del'>-</div><div class='del'>-	OUT4500(ai, AUXPAGE, page);</div><div class='del'>-	OUT4500(ai, AUXOFF, 0);</div><div class='del'>-	next = IN4500(ai, AUXDATA);</div><div class='del'>-	*len = IN4500(ai, AUXDATA)&amp;0xff;</div><div class='del'>-	if (offset != 4) OUT4500(ai, AUXOFF, offset);</div><div class='del'>-	return next;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* requires call to bap_setup() first */</div><div class='del'>-static int aux_bap_read(struct airo_info *ai, __le16 *pu16Dst,</div><div class='del'>-			int bytelen, int whichbap)</div><div class='del'>-{</div><div class='del'>-	u16 len;</div><div class='del'>-	u16 page;</div><div class='del'>-	u16 offset;</div><div class='del'>-	u16 next;</div><div class='del'>-	int words;</div><div class='del'>-	int i;</div><div class='del'>-	unsigned long flags;</div><div class='del'>-</div><div class='del'>-	spin_lock_irqsave(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-	page = IN4500(ai, SWS0+whichbap);</div><div class='del'>-	offset = IN4500(ai, SWS2+whichbap);</div><div class='del'>-	next = aux_setup(ai, page, offset, &amp;len);</div><div class='del'>-	words = (bytelen+1)&gt;&gt;1;</div><div class='del'>-</div><div class='del'>-	for (i = 0; i&lt;words;) {</div><div class='del'>-		int count;</div><div class='del'>-		count = (len&gt;&gt;1) &lt; (words-i) ? (len&gt;&gt;1) : (words-i);</div><div class='del'>-		if (!do8bitIO)</div><div class='del'>-			insw(ai-&gt;dev-&gt;base_addr+DATA0+whichbap,</div><div class='del'>-			      pu16Dst+i, count);</div><div class='del'>-		else</div><div class='del'>-			insb(ai-&gt;dev-&gt;base_addr+DATA0+whichbap,</div><div class='del'>-			      pu16Dst+i, count &lt;&lt; 1);</div><div class='del'>-		i += count;</div><div class='del'>-		if (i&lt;words) {</div><div class='del'>-			next = aux_setup(ai, next, 4, &amp;len);</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-	spin_unlock_irqrestore(&amp;ai-&gt;aux_lock, flags);</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-</div><div class='del'>-/* requires call to bap_setup() first */</div><div class='del'>-static int fast_bap_read(struct airo_info *ai, __le16 *pu16Dst,</div><div class='del'>-			 int bytelen, int whichbap)</div><div class='del'>-{</div><div class='del'>-	bytelen = (bytelen + 1) &amp; (~1); // round up to even value</div><div class='del'>-	if (!do8bitIO)</div><div class='del'>-		insw(ai-&gt;dev-&gt;base_addr+DATA0+whichbap, pu16Dst, bytelen&gt;&gt;1);</div><div class='del'>-	else</div><div class='del'>-		insb(ai-&gt;dev-&gt;base_addr+DATA0+whichbap, pu16Dst, bytelen);</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* requires call to bap_setup() first */</div><div class='del'>-static int bap_write(struct airo_info *ai, const __le16 *pu16Src,</div><div class='del'>-		     int bytelen, int whichbap)</div><div class='del'>-{</div><div class='del'>-	bytelen = (bytelen + 1) &amp; (~1); // round up to even value</div><div class='del'>-	if (!do8bitIO)</div><div class='del'>-		outsw(ai-&gt;dev-&gt;base_addr+DATA0+whichbap,</div><div class='del'>-		       pu16Src, bytelen&gt;&gt;1);</div><div class='del'>-	else</div><div class='del'>-		outsb(ai-&gt;dev-&gt;base_addr+DATA0+whichbap, pu16Src, bytelen);</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int PC4500_accessrid(struct airo_info *ai, u16 rid, u16 accmd)</div><div class='del'>-{</div><div class='del'>-	Cmd cmd; /* for issuing commands */</div><div class='del'>-	Resp rsp; /* response from commands */</div><div class='del'>-	u16 status;</div><div class='del'>-</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.cmd = accmd;</div><div class='del'>-	cmd.parm0 = rid;</div><div class='del'>-	status = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-	if (status != 0) return status;</div><div class='del'>-	if ((rsp.status &amp; 0x7F00) != 0) {</div><div class='del'>-		return (accmd &lt;&lt; 8) + (rsp.rsp0 &amp; 0xFF);</div><div class='del'>-	}</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*  Note, that we are using BAP1 which is also used by transmit, so</div><div class='del'>- *  we must get a lock. */</div><div class='del'>-static int PC4500_readrid(struct airo_info *ai, u16 rid, void *pBuf, int len, int lock)</div><div class='del'>-{</div><div class='del'>-	u16 status;</div><div class='del'>-        int rc = SUCCESS;</div><div class='del'>-</div><div class='del'>-	if (lock) {</div><div class='del'>-		if (down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-			return ERROR;</div><div class='del'>-	}</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags)) {</div><div class='del'>-		Cmd cmd;</div><div class='del'>-		Resp rsp;</div><div class='del'>-</div><div class='del'>-		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-		memset(&amp;rsp, 0, sizeof(rsp));</div><div class='del'>-		ai-&gt;config_desc.rid_desc.valid = 1;</div><div class='del'>-		ai-&gt;config_desc.rid_desc.len = RIDSIZE;</div><div class='del'>-		ai-&gt;config_desc.rid_desc.rid = 0;</div><div class='del'>-		ai-&gt;config_desc.rid_desc.host_addr = ai-&gt;ridbus;</div><div class='del'>-</div><div class='del'>-		cmd.cmd = CMD_ACCESS;</div><div class='del'>-		cmd.parm0 = rid;</div><div class='del'>-</div><div class='del'>-		memcpy_toio(ai-&gt;config_desc.card_ram_off,</div><div class='del'>-			&amp;ai-&gt;config_desc.rid_desc, sizeof(Rid));</div><div class='del'>-</div><div class='del'>-		rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-</div><div class='del'>-		if (rsp.status &amp; 0x7f00)</div><div class='del'>-			rc = rsp.rsp0;</div><div class='del'>-		if (!rc)</div><div class='del'>-			memcpy(pBuf, ai-&gt;config_desc.virtual_host_addr, len);</div><div class='del'>-		goto done;</div><div class='del'>-	} else {</div><div class='del'>-		if ((status = PC4500_accessrid(ai, rid, CMD_ACCESS))!=SUCCESS) {</div><div class='del'>-	                rc = status;</div><div class='del'>-	                goto done;</div><div class='del'>-	        }</div><div class='del'>-		if (bap_setup(ai, rid, 0, BAP1) != SUCCESS) {</div><div class='del'>-			rc = ERROR;</div><div class='del'>-	                goto done;</div><div class='del'>-	        }</div><div class='del'>-		// read the rid length field</div><div class='del'>-		bap_read(ai, pBuf, 2, BAP1);</div><div class='del'>-		// length for remaining part of rid</div><div class='del'>-		len = min(len, (int)le16_to_cpu(*(__le16*)pBuf)) - 2;</div><div class='del'>-</div><div class='del'>-		if (len &lt;= 2) {</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-				"Rid %x has a length of %d which is too short",</div><div class='del'>-				(int)rid, (int)len);</div><div class='del'>-			rc = ERROR;</div><div class='del'>-	                goto done;</div><div class='del'>-		}</div><div class='del'>-		// read remainder of the rid</div><div class='del'>-		rc = bap_read(ai, ((__le16*)pBuf)+1, len, BAP1);</div><div class='del'>-	}</div><div class='del'>-done:</div><div class='del'>-	if (lock)</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*  Note, that we are using BAP1 which is also used by transmit, so</div><div class='del'>- *  make sure this isn't called when a transmit is happening */</div><div class='del'>-static int PC4500_writerid(struct airo_info *ai, u16 rid,</div><div class='del'>-			   const void *pBuf, int len, int lock)</div><div class='del'>-{</div><div class='del'>-	u16 status;</div><div class='del'>-	int rc = SUCCESS;</div><div class='del'>-</div><div class='del'>-	*(__le16*)pBuf = cpu_to_le16((u16)len);</div><div class='del'>-</div><div class='del'>-	if (lock) {</div><div class='del'>-		if (down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-			return ERROR;</div><div class='del'>-	}</div><div class='del'>-	if (test_bit(FLAG_MPI,&amp;ai-&gt;flags)) {</div><div class='del'>-		Cmd cmd;</div><div class='del'>-		Resp rsp;</div><div class='del'>-</div><div class='del'>-		if (test_bit(FLAG_ENABLED, &amp;ai-&gt;flags) &amp;&amp; (RID_WEP_TEMP != rid))</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name,</div><div class='del'>-				"%s: MAC should be disabled (rid=%04x)",</div><div class='del'>-				__func__, rid);</div><div class='del'>-		memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-		memset(&amp;rsp, 0, sizeof(rsp));</div><div class='del'>-</div><div class='del'>-		ai-&gt;config_desc.rid_desc.valid = 1;</div><div class='del'>-		ai-&gt;config_desc.rid_desc.len = *((u16 *)pBuf);</div><div class='del'>-		ai-&gt;config_desc.rid_desc.rid = 0;</div><div class='del'>-</div><div class='del'>-		cmd.cmd = CMD_WRITERID;</div><div class='del'>-		cmd.parm0 = rid;</div><div class='del'>-</div><div class='del'>-		memcpy_toio(ai-&gt;config_desc.card_ram_off,</div><div class='del'>-			&amp;ai-&gt;config_desc.rid_desc, sizeof(Rid));</div><div class='del'>-</div><div class='del'>-		if (len &lt; 4 || len &gt; 2047) {</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name, "%s: len=%d", __func__, len);</div><div class='del'>-			rc = -1;</div><div class='del'>-		} else {</div><div class='del'>-			memcpy(ai-&gt;config_desc.virtual_host_addr,</div><div class='del'>-				pBuf, len);</div><div class='del'>-</div><div class='del'>-			rc = issuecommand(ai, &amp;cmd, &amp;rsp, true);</div><div class='del'>-			if ((rc &amp; 0xff00) != 0) {</div><div class='del'>-				airo_print_err(ai-&gt;dev-&gt;name, "%s: Write rid Error %d",</div><div class='del'>-						__func__, rc);</div><div class='del'>-				airo_print_err(ai-&gt;dev-&gt;name, "%s: Cmd=%04x",</div><div class='del'>-						__func__, cmd.cmd);</div><div class='del'>-			}</div><div class='del'>-</div><div class='del'>-			if ((rsp.status &amp; 0x7f00))</div><div class='del'>-				rc = rsp.rsp0;</div><div class='del'>-		}</div><div class='del'>-	} else {</div><div class='del'>-		// --- first access so that we can write the rid data</div><div class='del'>-		if ((status = PC4500_accessrid(ai, rid, CMD_ACCESS)) != 0) {</div><div class='del'>-	                rc = status;</div><div class='del'>-	                goto done;</div><div class='del'>-	        }</div><div class='del'>-		// --- now write the rid data</div><div class='del'>-		if (bap_setup(ai, rid, 0, BAP1) != SUCCESS) {</div><div class='del'>-	                rc = ERROR;</div><div class='del'>-	                goto done;</div><div class='del'>-	        }</div><div class='del'>-		bap_write(ai, pBuf, len, BAP1);</div><div class='del'>-		// ---now commit the rid data</div><div class='del'>-		rc = PC4500_accessrid(ai, rid, 0x100|CMD_ACCESS);</div><div class='del'>-	}</div><div class='del'>-done:</div><div class='del'>-	if (lock)</div><div class='del'>-		up(&amp;ai-&gt;sem);</div><div class='del'>-        return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Allocates a FID to be used for transmitting packets.  We only use</div><div class='del'>-   one for now. */</div><div class='del'>-static u16 transmit_allocate(struct airo_info *ai, int lenPayload, int raw)</div><div class='del'>-{</div><div class='del'>-	unsigned int loop = 3000;</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-	u16 txFid;</div><div class='del'>-	__le16 txControl;</div><div class='del'>-</div><div class='del'>-	cmd.cmd = CMD_ALLOCATETX;</div><div class='del'>-	cmd.parm0 = lenPayload;</div><div class='del'>-	if (down_interruptible(&amp;ai-&gt;sem))</div><div class='del'>-		return ERROR;</div><div class='del'>-	if (issuecommand(ai, &amp;cmd, &amp;rsp, true) != SUCCESS) {</div><div class='del'>-		txFid = ERROR;</div><div class='del'>-		goto done;</div><div class='del'>-	}</div><div class='del'>-	if ((rsp.status &amp; 0xFF00) != 0) {</div><div class='del'>-		txFid = ERROR;</div><div class='del'>-		goto done;</div><div class='del'>-	}</div><div class='del'>-	/* wait for the allocate event/indication</div><div class='del'>-	 * It makes me kind of nervous that this can just sit here and spin,</div><div class='del'>-	 * but in practice it only loops like four times. */</div><div class='del'>-	while (((IN4500(ai, EVSTAT) &amp; EV_ALLOC) == 0) &amp;&amp; --loop);</div><div class='del'>-	if (!loop) {</div><div class='del'>-		txFid = ERROR;</div><div class='del'>-		goto done;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	// get the allocated fid and acknowledge</div><div class='del'>-	txFid = IN4500(ai, TXALLOCFID);</div><div class='del'>-	OUT4500(ai, EVACK, EV_ALLOC);</div><div class='del'>-</div><div class='del'>-	/*  The CARD is pretty cool since it converts the ethernet packet</div><div class='del'>-	 *  into 802.11.  Also note that we don't release the FID since we</div><div class='del'>-	 *  will be using the same one over and over again. */</div><div class='del'>-	/*  We only have to setup the control once since we are not</div><div class='del'>-	 *  releasing the fid. */</div><div class='del'>-	if (raw)</div><div class='del'>-		txControl = cpu_to_le16(TXCTL_TXOK | TXCTL_TXEX | TXCTL_802_11</div><div class='del'>-			| TXCTL_ETHERNET | TXCTL_NORELEASE);</div><div class='del'>-	else</div><div class='del'>-		txControl = cpu_to_le16(TXCTL_TXOK | TXCTL_TXEX | TXCTL_802_3</div><div class='del'>-			| TXCTL_ETHERNET | TXCTL_NORELEASE);</div><div class='del'>-	if (bap_setup(ai, txFid, 0x0008, BAP1) != SUCCESS)</div><div class='del'>-		txFid = ERROR;</div><div class='del'>-	else</div><div class='del'>-		bap_write(ai, &amp;txControl, sizeof(txControl), BAP1);</div><div class='del'>-</div><div class='del'>-done:</div><div class='del'>-	up(&amp;ai-&gt;sem);</div><div class='del'>-</div><div class='del'>-	return txFid;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* In general BAP1 is dedicated to transmiting packets.  However,</div><div class='del'>-   since we need a BAP when accessing RIDs, we also use BAP1 for that.</div><div class='del'>-   Make sure the BAP1 spinlock is held when this is called. */</div><div class='del'>-static int transmit_802_3_packet(struct airo_info *ai, int len, char *pPacket,</div><div class='del'>-				 bool may_sleep)</div><div class='del'>-{</div><div class='del'>-	__le16 payloadLen;</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-	int miclen = 0;</div><div class='del'>-	u16 txFid = len;</div><div class='del'>-	MICBuffer pMic;</div><div class='del'>-</div><div class='del'>-	len &gt;&gt;= 16;</div><div class='del'>-</div><div class='del'>-	if (len &lt;= ETH_ALEN * 2) {</div><div class='del'>-		airo_print_warn(ai-&gt;dev-&gt;name, "Short packet %d", len);</div><div class='del'>-		return ERROR;</div><div class='del'>-	}</div><div class='del'>-	len -= ETH_ALEN * 2;</div><div class='del'>-</div><div class='del'>-	if (test_bit(FLAG_MIC_CAPABLE, &amp;ai-&gt;flags) &amp;&amp; ai-&gt;micstats.enabled &amp;&amp;</div><div class='del'>-	    (ntohs(((__be16 *)pPacket)[6]) != 0x888E)) {</div><div class='del'>-		if (encapsulate(ai, (etherHead *)pPacket,&amp;pMic, len) != SUCCESS)</div><div class='del'>-			return ERROR;</div><div class='del'>-		miclen = sizeof(pMic);</div><div class='del'>-	}</div><div class='del'>-	// packet is destination[6], source[6], payload[len-12]</div><div class='del'>-	// write the payload length and dst/src/payload</div><div class='del'>-	if (bap_setup(ai, txFid, 0x0036, BAP1) != SUCCESS) return ERROR;</div><div class='del'>-	/* The hardware addresses aren't counted as part of the payload, so</div><div class='del'>-	 * we have to subtract the 12 bytes for the addresses off */</div><div class='del'>-	payloadLen = cpu_to_le16(len + miclen);</div><div class='del'>-	bap_write(ai, &amp;payloadLen, sizeof(payloadLen), BAP1);</div><div class='del'>-	bap_write(ai, (__le16*)pPacket, sizeof(etherHead), BAP1);</div><div class='del'>-	if (miclen)</div><div class='del'>-		bap_write(ai, (__le16*)&amp;pMic, miclen, BAP1);</div><div class='del'>-	bap_write(ai, (__le16*)(pPacket + sizeof(etherHead)), len, BAP1);</div><div class='del'>-	// issue the transmit command</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.cmd = CMD_TRANSMIT;</div><div class='del'>-	cmd.parm0 = txFid;</div><div class='del'>-	if (issuecommand(ai, &amp;cmd, &amp;rsp, may_sleep) != SUCCESS)</div><div class='del'>-		return ERROR;</div><div class='del'>-	if ((rsp.status &amp; 0xFF00) != 0) return ERROR;</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int transmit_802_11_packet(struct airo_info *ai, int len, char *pPacket,</div><div class='del'>-				  bool may_sleep)</div><div class='del'>-{</div><div class='del'>-	__le16 fc, payloadLen;</div><div class='del'>-	Cmd cmd;</div><div class='del'>-	Resp rsp;</div><div class='del'>-	int hdrlen;</div><div class='del'>-	static u8 tail[(30-10) + 2 + 6] = {[30-10] = 6};</div><div class='del'>-	/* padding of header to full size + le16 gaplen (6) + gaplen bytes */</div><div class='del'>-	u16 txFid = len;</div><div class='del'>-	len &gt;&gt;= 16;</div><div class='del'>-</div><div class='del'>-	fc = *(__le16*)pPacket;</div><div class='del'>-	hdrlen = header_len(fc);</div><div class='del'>-</div><div class='del'>-	if (len &lt; hdrlen) {</div><div class='del'>-		airo_print_warn(ai-&gt;dev-&gt;name, "Short packet %d", len);</div><div class='del'>-		return ERROR;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	/* packet is 802.11 header +  payload</div><div class='del'>-	 * write the payload length and dst/src/payload */</div><div class='del'>-	if (bap_setup(ai, txFid, 6, BAP1) != SUCCESS) return ERROR;</div><div class='del'>-	/* The 802.11 header aren't counted as part of the payload, so</div><div class='del'>-	 * we have to subtract the header bytes off */</div><div class='del'>-	payloadLen = cpu_to_le16(len-hdrlen);</div><div class='del'>-	bap_write(ai, &amp;payloadLen, sizeof(payloadLen), BAP1);</div><div class='del'>-	if (bap_setup(ai, txFid, 0x0014, BAP1) != SUCCESS) return ERROR;</div><div class='del'>-	bap_write(ai, (__le16 *)pPacket, hdrlen, BAP1);</div><div class='del'>-	bap_write(ai, (__le16 *)(tail + (hdrlen - 10)), 38 - hdrlen, BAP1);</div><div class='del'>-</div><div class='del'>-	bap_write(ai, (__le16 *)(pPacket + hdrlen), len - hdrlen, BAP1);</div><div class='del'>-	// issue the transmit command</div><div class='del'>-	memset(&amp;cmd, 0, sizeof(cmd));</div><div class='del'>-	cmd.cmd = CMD_TRANSMIT;</div><div class='del'>-	cmd.parm0 = txFid;</div><div class='del'>-	if (issuecommand(ai, &amp;cmd, &amp;rsp, may_sleep) != SUCCESS)</div><div class='del'>-		return ERROR;</div><div class='del'>-	if ((rsp.status &amp; 0xFF00) != 0) return ERROR;</div><div class='del'>-	return SUCCESS;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  This is the proc_fs routines.  It is a bit messier than I would</div><div class='del'>- *  like!  Feel free to clean it up!</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-static ssize_t proc_read(struct file *file,</div><div class='del'>-			  char __user *buffer,</div><div class='del'>-			  size_t len,</div><div class='del'>-			  loff_t *offset);</div><div class='del'>-</div><div class='del'>-static ssize_t proc_write(struct file *file,</div><div class='del'>-			   const char __user *buffer,</div><div class='del'>-			   size_t len,</div><div class='del'>-			   loff_t *offset);</div><div class='del'>-static int proc_close(struct inode *inode, struct file *file);</div><div class='del'>-</div><div class='del'>-static int proc_stats_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_statsdelta_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_status_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_SSID_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_APList_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_BSSList_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_config_open(struct inode *inode, struct file *file);</div><div class='del'>-static int proc_wepkey_open(struct inode *inode, struct file *file);</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_statsdelta_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_open	= proc_statsdelta_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_stats_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_open	= proc_stats_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_status_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_open	= proc_status_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_SSID_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_write	= proc_write,</div><div class='del'>-	.proc_open	= proc_SSID_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_BSSList_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_write	= proc_write,</div><div class='del'>-	.proc_open	= proc_BSSList_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_APList_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_write	= proc_write,</div><div class='del'>-	.proc_open	= proc_APList_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_config_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_write	= proc_write,</div><div class='del'>-	.proc_open	= proc_config_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static const struct proc_ops proc_wepkey_ops = {</div><div class='del'>-	.proc_read	= proc_read,</div><div class='del'>-	.proc_write	= proc_write,</div><div class='del'>-	.proc_open	= proc_wepkey_open,</div><div class='del'>-	.proc_release	= proc_close,</div><div class='del'>-	.proc_lseek	= default_llseek,</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static struct proc_dir_entry *airo_entry;</div><div class='del'>-</div><div class='del'>-struct proc_data {</div><div class='del'>-	int release_buffer;</div><div class='del'>-	int readlen;</div><div class='del'>-	char *rbuffer;</div><div class='del'>-	int writelen;</div><div class='del'>-	int maxwritelen;</div><div class='del'>-	char *wbuffer;</div><div class='del'>-	void (*on_close) (struct inode *, struct file *);</div><div class='del'>-};</div><div class='del'>-</div><div class='del'>-static int setup_proc_entry(struct net_device *dev,</div><div class='del'>-			     struct airo_info *apriv)</div><div class='del'>-{</div><div class='del'>-	struct proc_dir_entry *entry;</div><div class='del'>-</div><div class='del'>-	/* First setup the device directory */</div><div class='del'>-	strcpy(apriv-&gt;proc_name, dev-&gt;name);</div><div class='del'>-	apriv-&gt;proc_entry = proc_mkdir_mode(apriv-&gt;proc_name, airo_perm,</div><div class='del'>-					    airo_entry);</div><div class='del'>-	if (!apriv-&gt;proc_entry)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	proc_set_user(apriv-&gt;proc_entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the StatsDelta */</div><div class='del'>-	entry = proc_create_data("StatsDelta", 0444 &amp; proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_statsdelta_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the Stats */</div><div class='del'>-	entry = proc_create_data("Stats", 0444 &amp; proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_stats_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the Status */</div><div class='del'>-	entry = proc_create_data("Status", 0444 &amp; proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_status_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the Config */</div><div class='del'>-	entry = proc_create_data("Config", proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_config_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the SSID */</div><div class='del'>-	entry = proc_create_data("SSID", proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_SSID_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the APList */</div><div class='del'>-	entry = proc_create_data("APList", proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_APList_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the BSSList */</div><div class='del'>-	entry = proc_create_data("BSSList", proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_BSSList_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-</div><div class='del'>-	/* Setup the WepKey */</div><div class='del'>-	entry = proc_create_data("WepKey", proc_perm,</div><div class='del'>-				 apriv-&gt;proc_entry, &amp;proc_wepkey_ops, dev);</div><div class='del'>-	if (!entry)</div><div class='del'>-		goto fail;</div><div class='del'>-	proc_set_user(entry, proc_kuid, proc_kgid);</div><div class='del'>-	return 0;</div><div class='del'>-</div><div class='del'>-fail:</div><div class='del'>-	remove_proc_subtree(apriv-&gt;proc_name, airo_entry);</div><div class='del'>-	return -ENOMEM;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int takedown_proc_entry(struct net_device *dev,</div><div class='del'>-				struct airo_info *apriv)</div><div class='del'>-{</div><div class='del'>-	remove_proc_subtree(apriv-&gt;proc_name, airo_entry);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  What we want from the proc_fs is to be able to efficiently read</div><div class='del'>- *  and write the configuration.  To do this, we want to read the</div><div class='del'>- *  configuration when the file is opened and write it when the file is</div><div class='del'>- *  closed.  So basically we allocate a read buffer at open and fill it</div><div class='del'>- *  with data, and allocate a write buffer and read it at close.</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  The read routine is generic, it relies on the preallocated rbuffer</div><div class='del'>- *  to supply the data.</div><div class='del'>- */</div><div class='del'>-static ssize_t proc_read(struct file *file,</div><div class='del'>-			  char __user *buffer,</div><div class='del'>-			  size_t len,</div><div class='del'>-			  loff_t *offset)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *priv = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;rbuffer)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	return simple_read_from_buffer(buffer, len, offset, priv-&gt;rbuffer,</div><div class='del'>-					priv-&gt;readlen);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/*</div><div class='del'>- *  The write routine is generic, it fills in a preallocated rbuffer</div><div class='del'>- *  to supply the data.</div><div class='del'>- */</div><div class='del'>-static ssize_t proc_write(struct file *file,</div><div class='del'>-			   const char __user *buffer,</div><div class='del'>-			   size_t len,</div><div class='del'>-			   loff_t *offset)</div><div class='del'>-{</div><div class='del'>-	ssize_t ret;</div><div class='del'>-	struct proc_data *priv = file-&gt;private_data;</div><div class='del'>-</div><div class='del'>-	if (!priv-&gt;wbuffer)</div><div class='del'>-		return -EINVAL;</div><div class='del'>-</div><div class='del'>-	ret = simple_write_to_buffer(priv-&gt;wbuffer, priv-&gt;maxwritelen, offset,</div><div class='del'>-					buffer, len);</div><div class='del'>-	if (ret &gt; 0)</div><div class='del'>-		priv-&gt;writelen = max_t(int, priv-&gt;writelen, *offset);</div><div class='del'>-</div><div class='del'>-	return ret;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_status_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *apriv = dev-&gt;ml_priv;</div><div class='del'>-	CapabilityRid cap_rid;</div><div class='del'>-	StatusRid status_rid;</div><div class='del'>-	u16 mode;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kmalloc(2048, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	readStatusRid(apriv, &amp;status_rid, 1);</div><div class='del'>-	readCapabilityRid(apriv, &amp;cap_rid, 1);</div><div class='del'>-</div><div class='del'>-	mode = le16_to_cpu(status_rid.mode);</div><div class='del'>-</div><div class='del'>-        i = sprintf(data-&gt;rbuffer, "Status: %s%s%s%s%s%s%s%s%s\n",</div><div class='del'>-                    mode &amp; 1 ? "CFG ": "",</div><div class='del'>-                    mode &amp; 2 ? "ACT ": "",</div><div class='del'>-                    mode &amp; 0x10 ? "SYN ": "",</div><div class='del'>-                    mode &amp; 0x20 ? "LNK ": "",</div><div class='del'>-                    mode &amp; 0x40 ? "LEAP ": "",</div><div class='del'>-                    mode &amp; 0x80 ? "PRIV ": "",</div><div class='del'>-                    mode &amp; 0x100 ? "KEY ": "",</div><div class='del'>-                    mode &amp; 0x200 ? "WEP ": "",</div><div class='del'>-                    mode &amp; 0x8000 ? "ERR ": "");</div><div class='del'>-	sprintf(data-&gt;rbuffer+i, "Mode: %x\n"</div><div class='del'>-		 "Signal Strength: %d\n"</div><div class='del'>-		 "Signal Quality: %d\n"</div><div class='del'>-		 "SSID: %-.*s\n"</div><div class='del'>-		 "AP: %-.16s\n"</div><div class='del'>-		 "Freq: %d\n"</div><div class='del'>-		 "BitRate: %dmbs\n"</div><div class='del'>-		 "Driver Version: %s\n"</div><div class='del'>-		 "Device: %s\nManufacturer: %s\nFirmware Version: %s\n"</div><div class='del'>-		 "Radio type: %x\nCountry: %x\nHardware Version: %x\n"</div><div class='del'>-		 "Software Version: %x\nSoftware Subversion: %x\n"</div><div class='del'>-		 "Boot block version: %x\n",</div><div class='del'>-		 le16_to_cpu(status_rid.mode),</div><div class='del'>-		 le16_to_cpu(status_rid.normalizedSignalStrength),</div><div class='del'>-		 le16_to_cpu(status_rid.signalQuality),</div><div class='del'>-		 le16_to_cpu(status_rid.SSIDlen),</div><div class='del'>-		 status_rid.SSID,</div><div class='del'>-		 status_rid.apName,</div><div class='del'>-		 le16_to_cpu(status_rid.channel),</div><div class='del'>-		 le16_to_cpu(status_rid.currentXmitRate) / 2,</div><div class='del'>-		 version,</div><div class='del'>-		 cap_rid.prodName,</div><div class='del'>-		 cap_rid.manName,</div><div class='del'>-		 cap_rid.prodVer,</div><div class='del'>-		 le16_to_cpu(cap_rid.radioType),</div><div class='del'>-		 le16_to_cpu(cap_rid.country),</div><div class='del'>-		 le16_to_cpu(cap_rid.hardVer),</div><div class='del'>-		 le16_to_cpu(cap_rid.softVer),</div><div class='del'>-		 le16_to_cpu(cap_rid.softSubVer),</div><div class='del'>-		 le16_to_cpu(cap_rid.bootBlockVer));</div><div class='del'>-	data-&gt;readlen = strlen(data-&gt;rbuffer);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_stats_rid_open(struct inode*, struct file*, u16);</div><div class='del'>-static int proc_statsdelta_open(struct inode *inode,</div><div class='del'>-				 struct file *file)</div><div class='del'>-{</div><div class='del'>-	if (file-&gt;f_mode&amp;FMODE_WRITE) {</div><div class='del'>-		return proc_stats_rid_open(inode, file, RID_STATSDELTACLEAR);</div><div class='del'>-	}</div><div class='del'>-	return proc_stats_rid_open(inode, file, RID_STATSDELTA);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_stats_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	return proc_stats_rid_open(inode, file, RID_STATS);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_stats_rid_open(struct inode *inode,</div><div class='del'>-				struct file *file,</div><div class='del'>-				u16 rid)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *apriv = dev-&gt;ml_priv;</div><div class='del'>-	StatsRid stats;</div><div class='del'>-	int i, j;</div><div class='del'>-	__le32 *vals = stats.vals;</div><div class='del'>-	int len;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kmalloc(4096, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	readStatsRid(apriv, &amp;stats, rid, 1);</div><div class='del'>-	len = le16_to_cpu(stats.len);</div><div class='del'>-</div><div class='del'>-        j = 0;</div><div class='del'>-	for (i = 0; statsLabels[i]!=(char *)-1 &amp;&amp; i*4&lt;len; i++) {</div><div class='del'>-		if (!statsLabels[i]) continue;</div><div class='del'>-		if (j+strlen(statsLabels[i])+16&gt;4096) {</div><div class='del'>-			airo_print_warn(apriv-&gt;dev-&gt;name,</div><div class='del'>-			       "Potentially disastrous buffer overflow averted!");</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-		j+=sprintf(data-&gt;rbuffer+j, "%s: %u\n", statsLabels[i],</div><div class='del'>-				le32_to_cpu(vals[i]));</div><div class='del'>-	}</div><div class='del'>-	if (i*4 &gt;= len) {</div><div class='del'>-		airo_print_warn(apriv-&gt;dev-&gt;name, "Got a short rid");</div><div class='del'>-	}</div><div class='del'>-	data-&gt;readlen = j;</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int get_dec_u16(char *buffer, int *start, int limit)</div><div class='del'>-{</div><div class='del'>-	u16 value;</div><div class='del'>-	int valid = 0;</div><div class='del'>-	for (value = 0; *start &lt; limit &amp;&amp; buffer[*start] &gt;= '0' &amp;&amp;</div><div class='del'>-			buffer[*start] &lt;= '9'; (*start)++) {</div><div class='del'>-		valid = 1;</div><div class='del'>-		value *= 10;</div><div class='del'>-		value += buffer[*start] - '0';</div><div class='del'>-	}</div><div class='del'>-	if (!valid) return -1;</div><div class='del'>-	return value;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int airo_config_commit(struct net_device *dev,</div><div class='del'>-			      struct iw_request_info *info,</div><div class='del'>-			      union iwreq_data *wrqu,</div><div class='del'>-			      char *extra);</div><div class='del'>-</div><div class='del'>-static inline int sniffing_mode(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	return (le16_to_cpu(ai-&gt;config.rmode) &amp; le16_to_cpu(RXMODE_MASK)) &gt;=</div><div class='del'>-		le16_to_cpu(RXMODE_RFMON);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void proc_config_on_close(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data = file-&gt;private_data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	char *line;</div><div class='del'>-</div><div class='del'>-	if (!data-&gt;writelen) return;</div><div class='del'>-</div><div class='del'>-	readConfigRid(ai, 1);</div><div class='del'>-	set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-</div><div class='del'>-	line = data-&gt;wbuffer;</div><div class='del'>-	while (line[0]) {</div><div class='del'>-/*** Mode processing */</div><div class='del'>-		if (!strncmp(line, "Mode: ", 6)) {</div><div class='del'>-			line += 6;</div><div class='del'>-			if (sniffing_mode(ai))</div><div class='del'>-				set_bit (FLAG_RESET, &amp;ai-&gt;flags);</div><div class='del'>-			ai-&gt;config.rmode &amp;= ~RXMODE_FULL_MASK;</div><div class='del'>-			clear_bit (FLAG_802_11, &amp;ai-&gt;flags);</div><div class='del'>-			ai-&gt;config.opmode &amp;= ~MODE_CFG_MASK;</div><div class='del'>-			ai-&gt;config.scanMode = SCANMODE_ACTIVE;</div><div class='del'>-			if (line[0] == 'a') {</div><div class='del'>-				ai-&gt;config.opmode |= MODE_STA_IBSS;</div><div class='del'>-			} else {</div><div class='del'>-				ai-&gt;config.opmode |= MODE_STA_ESS;</div><div class='del'>-				if (line[0] == 'r') {</div><div class='del'>-					ai-&gt;config.rmode |= RXMODE_RFMON | RXMODE_DISABLE_802_3_HEADER;</div><div class='del'>-					ai-&gt;config.scanMode = SCANMODE_PASSIVE;</div><div class='del'>-					set_bit (FLAG_802_11, &amp;ai-&gt;flags);</div><div class='del'>-				} else if (line[0] == 'y') {</div><div class='del'>-					ai-&gt;config.rmode |= RXMODE_RFMON_ANYBSS | RXMODE_DISABLE_802_3_HEADER;</div><div class='del'>-					ai-&gt;config.scanMode = SCANMODE_PASSIVE;</div><div class='del'>-					set_bit (FLAG_802_11, &amp;ai-&gt;flags);</div><div class='del'>-				} else if (line[0] == 'l')</div><div class='del'>-					ai-&gt;config.rmode |= RXMODE_LANMON;</div><div class='del'>-			}</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-/*** Radio status */</div><div class='del'>-		else if (!strncmp(line,"Radio: ", 7)) {</div><div class='del'>-			line += 7;</div><div class='del'>-			if (!strncmp(line,"off", 3)) {</div><div class='del'>-				set_bit (FLAG_RADIO_OFF, &amp;ai-&gt;flags);</div><div class='del'>-			} else {</div><div class='del'>-				clear_bit (FLAG_RADIO_OFF, &amp;ai-&gt;flags);</div><div class='del'>-			}</div><div class='del'>-		}</div><div class='del'>-/*** NodeName processing */</div><div class='del'>-		else if (!strncmp(line, "NodeName: ", 10)) {</div><div class='del'>-			int j;</div><div class='del'>-</div><div class='del'>-			line += 10;</div><div class='del'>-			memset(ai-&gt;config.nodeName, 0, 16);</div><div class='del'>-/* Do the name, assume a space between the mode and node name */</div><div class='del'>-			for (j = 0; j &lt; 16 &amp;&amp; line[j] != '\n'; j++) {</div><div class='del'>-				ai-&gt;config.nodeName[j] = line[j];</div><div class='del'>-			}</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		}</div><div class='del'>-</div><div class='del'>-/*** PowerMode processing */</div><div class='del'>-		else if (!strncmp(line, "PowerMode: ", 11)) {</div><div class='del'>-			line += 11;</div><div class='del'>-			if (!strncmp(line, "PSPCAM", 6)) {</div><div class='del'>-				ai-&gt;config.powerSaveMode = POWERSAVE_PSPCAM;</div><div class='del'>-				set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-			} else if (!strncmp(line, "PSP", 3)) {</div><div class='del'>-				ai-&gt;config.powerSaveMode = POWERSAVE_PSP;</div><div class='del'>-				set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-			} else {</div><div class='del'>-				ai-&gt;config.powerSaveMode = POWERSAVE_CAM;</div><div class='del'>-				set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-			}</div><div class='del'>-		} else if (!strncmp(line, "DataRates: ", 11)) {</div><div class='del'>-			int v, i = 0, k = 0; /* i is index into line,</div><div class='del'>-						k is index to rates */</div><div class='del'>-</div><div class='del'>-			line += 11;</div><div class='del'>-			while ((v = get_dec_u16(line, &amp;i, 3))!=-1) {</div><div class='del'>-				ai-&gt;config.rates[k++] = (u8)v;</div><div class='del'>-				line += i + 1;</div><div class='del'>-				i = 0;</div><div class='del'>-			}</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "Channel: ", 9)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-			line += 9;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, i+3);</div><div class='del'>-			if (v != -1) {</div><div class='del'>-				ai-&gt;config.channelSet = cpu_to_le16(v);</div><div class='del'>-				set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-			}</div><div class='del'>-		} else if (!strncmp(line, "XmitPower: ", 11)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-			line += 11;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, i+3);</div><div class='del'>-			if (v != -1) {</div><div class='del'>-				ai-&gt;config.txPower = cpu_to_le16(v);</div><div class='del'>-				set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-			}</div><div class='del'>-		} else if (!strncmp(line, "WEP: ", 5)) {</div><div class='del'>-			line += 5;</div><div class='del'>-			switch(line[0]) {</div><div class='del'>-			case 's':</div><div class='del'>-				set_auth_type(ai, AUTH_SHAREDKEY);</div><div class='del'>-				break;</div><div class='del'>-			case 'e':</div><div class='del'>-				set_auth_type(ai, AUTH_ENCRYPT);</div><div class='del'>-				break;</div><div class='del'>-			default:</div><div class='del'>-				set_auth_type(ai, AUTH_OPEN);</div><div class='del'>-				break;</div><div class='del'>-			}</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "LongRetryLimit: ", 16)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 16;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 3);</div><div class='del'>-			v = (v&lt;0) ? 0 : ((v&gt;255) ? 255 : v);</div><div class='del'>-			ai-&gt;config.longRetryLimit = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "ShortRetryLimit: ", 17)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 17;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 3);</div><div class='del'>-			v = (v&lt;0) ? 0 : ((v&gt;255) ? 255 : v);</div><div class='del'>-			ai-&gt;config.shortRetryLimit = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "RTSThreshold: ", 14)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 14;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 4);</div><div class='del'>-			v = (v&lt;0) ? 0 : ((v&gt;AIRO_DEF_MTU) ? AIRO_DEF_MTU : v);</div><div class='del'>-			ai-&gt;config.rtsThres = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "TXMSDULifetime: ", 16)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 16;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 5);</div><div class='del'>-			v = (v&lt;0) ? 0 : v;</div><div class='del'>-			ai-&gt;config.txLifetime = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "RXMSDULifetime: ", 16)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 16;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 5);</div><div class='del'>-			v = (v&lt;0) ? 0 : v;</div><div class='del'>-			ai-&gt;config.rxLifetime = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "TXDiversity: ", 13)) {</div><div class='del'>-			ai-&gt;config.txDiversity =</div><div class='del'>-				(line[13]=='l') ? 1 :</div><div class='del'>-				((line[13]=='r')? 2: 3);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "RXDiversity: ", 13)) {</div><div class='del'>-			ai-&gt;config.rxDiversity =</div><div class='del'>-				(line[13]=='l') ? 1 :</div><div class='del'>-				((line[13]=='r')? 2: 3);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "FragThreshold: ", 15)) {</div><div class='del'>-			int v, i = 0;</div><div class='del'>-</div><div class='del'>-			line += 15;</div><div class='del'>-			v = get_dec_u16(line, &amp;i, 4);</div><div class='del'>-			v = (v&lt;256) ? 256 : ((v&gt;AIRO_DEF_MTU) ? AIRO_DEF_MTU : v);</div><div class='del'>-			v = v &amp; 0xfffe; /* Make sure its even */</div><div class='del'>-			ai-&gt;config.fragThresh = cpu_to_le16(v);</div><div class='del'>-			set_bit (FLAG_COMMIT, &amp;ai-&gt;flags);</div><div class='del'>-		} else if (!strncmp(line, "Modulation: ", 12)) {</div><div class='del'>-			line += 12;</div><div class='del'>-			switch(*line) {</div><div class='del'>-			case 'd':  ai-&gt;config.modulation = MOD_DEFAULT; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			case 'c':  ai-&gt;config.modulation = MOD_CCK; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			case 'm':  ai-&gt;config.modulation = MOD_MOK; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			default: airo_print_warn(ai-&gt;dev-&gt;name, "Unknown modulation");</div><div class='del'>-			}</div><div class='del'>-		} else if (!strncmp(line, "Preamble: ", 10)) {</div><div class='del'>-			line += 10;</div><div class='del'>-			switch(*line) {</div><div class='del'>-			case 'a': ai-&gt;config.preamble = PREAMBLE_AUTO; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			case 'l': ai-&gt;config.preamble = PREAMBLE_LONG; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			case 's': ai-&gt;config.preamble = PREAMBLE_SHORT; set_bit(FLAG_COMMIT, &amp;ai-&gt;flags); break;</div><div class='del'>-			default: airo_print_warn(ai-&gt;dev-&gt;name, "Unknown preamble");</div><div class='del'>-			}</div><div class='del'>-		} else {</div><div class='del'>-			airo_print_warn(ai-&gt;dev-&gt;name, "Couldn't figure out %s", line);</div><div class='del'>-		}</div><div class='del'>-		while (line[0] &amp;&amp; line[0] != '\n') line++;</div><div class='del'>-		if (line[0]) line++;</div><div class='del'>-	}</div><div class='del'>-	airo_config_commit(dev, NULL, NULL, NULL);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static const char *get_rmode(__le16 mode)</div><div class='del'>-{</div><div class='del'>-        switch(mode &amp; RXMODE_MASK) {</div><div class='del'>-        case RXMODE_RFMON:  return "rfmon";</div><div class='del'>-        case RXMODE_RFMON_ANYBSS:  return "yna (any) bss rfmon";</div><div class='del'>-        case RXMODE_LANMON:  return "lanmon";</div><div class='del'>-        }</div><div class='del'>-        return "ESS";</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_config_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int i;</div><div class='del'>-	__le16 mode;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kmalloc(2048, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	if ((data-&gt;wbuffer = kzalloc(2048, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (data-&gt;rbuffer);</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	data-&gt;maxwritelen = 2048;</div><div class='del'>-	data-&gt;on_close = proc_config_on_close;</div><div class='del'>-</div><div class='del'>-	readConfigRid(ai, 1);</div><div class='del'>-</div><div class='del'>-	mode = ai-&gt;config.opmode &amp; MODE_CFG_MASK;</div><div class='del'>-	i = sprintf(data-&gt;rbuffer,</div><div class='del'>-		     "Mode: %s\n"</div><div class='del'>-		     "Radio: %s\n"</div><div class='del'>-		     "NodeName: %-16s\n"</div><div class='del'>-		     "PowerMode: %s\n"</div><div class='del'>-		     "DataRates: %d %d %d %d %d %d %d %d\n"</div><div class='del'>-		     "Channel: %d\n"</div><div class='del'>-		     "XmitPower: %d\n",</div><div class='del'>-		     mode == MODE_STA_IBSS ? "adhoc" :</div><div class='del'>-		     mode == MODE_STA_ESS ? get_rmode(ai-&gt;config.rmode):</div><div class='del'>-		     mode == MODE_AP ? "AP" :</div><div class='del'>-		     mode == MODE_AP_RPTR ? "AP RPTR" : "Error",</div><div class='del'>-		     test_bit(FLAG_RADIO_OFF, &amp;ai-&gt;flags) ? "off" : "on",</div><div class='del'>-		     ai-&gt;config.nodeName,</div><div class='del'>-		     ai-&gt;config.powerSaveMode == POWERSAVE_CAM ? "CAM" :</div><div class='del'>-		     ai-&gt;config.powerSaveMode == POWERSAVE_PSP ? "PSP" :</div><div class='del'>-		     ai-&gt;config.powerSaveMode == POWERSAVE_PSPCAM ? "PSPCAM" :</div><div class='del'>-		     "Error",</div><div class='del'>-		     (int)ai-&gt;config.rates[0],</div><div class='del'>-		     (int)ai-&gt;config.rates[1],</div><div class='del'>-		     (int)ai-&gt;config.rates[2],</div><div class='del'>-		     (int)ai-&gt;config.rates[3],</div><div class='del'>-		     (int)ai-&gt;config.rates[4],</div><div class='del'>-		     (int)ai-&gt;config.rates[5],</div><div class='del'>-		     (int)ai-&gt;config.rates[6],</div><div class='del'>-		     (int)ai-&gt;config.rates[7],</div><div class='del'>-		     le16_to_cpu(ai-&gt;config.channelSet),</div><div class='del'>-		     le16_to_cpu(ai-&gt;config.txPower)</div><div class='del'>-		);</div><div class='del'>-	sprintf(data-&gt;rbuffer + i,</div><div class='del'>-		 "LongRetryLimit: %d\n"</div><div class='del'>-		 "ShortRetryLimit: %d\n"</div><div class='del'>-		 "RTSThreshold: %d\n"</div><div class='del'>-		 "TXMSDULifetime: %d\n"</div><div class='del'>-		 "RXMSDULifetime: %d\n"</div><div class='del'>-		 "TXDiversity: %s\n"</div><div class='del'>-		 "RXDiversity: %s\n"</div><div class='del'>-		 "FragThreshold: %d\n"</div><div class='del'>-		 "WEP: %s\n"</div><div class='del'>-		 "Modulation: %s\n"</div><div class='del'>-		 "Preamble: %s\n",</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.longRetryLimit),</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.shortRetryLimit),</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.rtsThres),</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.txLifetime),</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.rxLifetime),</div><div class='del'>-		 ai-&gt;config.txDiversity == 1 ? "left" :</div><div class='del'>-		 ai-&gt;config.txDiversity == 2 ? "right" : "both",</div><div class='del'>-		 ai-&gt;config.rxDiversity == 1 ? "left" :</div><div class='del'>-		 ai-&gt;config.rxDiversity == 2 ? "right" : "both",</div><div class='del'>-		 le16_to_cpu(ai-&gt;config.fragThresh),</div><div class='del'>-		 ai-&gt;config.authType == AUTH_ENCRYPT ? "encrypt" :</div><div class='del'>-		 ai-&gt;config.authType == AUTH_SHAREDKEY ? "shared" : "open",</div><div class='del'>-		 ai-&gt;config.modulation == MOD_DEFAULT ? "default" :</div><div class='del'>-		 ai-&gt;config.modulation == MOD_CCK ? "cck" :</div><div class='del'>-		 ai-&gt;config.modulation == MOD_MOK ? "mok" : "error",</div><div class='del'>-		 ai-&gt;config.preamble == PREAMBLE_AUTO ? "auto" :</div><div class='del'>-		 ai-&gt;config.preamble == PREAMBLE_LONG ? "long" :</div><div class='del'>-		 ai-&gt;config.preamble == PREAMBLE_SHORT ? "short" : "error"</div><div class='del'>-		);</div><div class='del'>-	data-&gt;readlen = strlen(data-&gt;rbuffer);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void proc_SSID_on_close(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data = file-&gt;private_data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	SsidRid SSID_rid;</div><div class='del'>-	int i;</div><div class='del'>-	char *p = data-&gt;wbuffer;</div><div class='del'>-	char *end = p + data-&gt;writelen;</div><div class='del'>-</div><div class='del'>-	if (!data-&gt;writelen)</div><div class='del'>-		return;</div><div class='del'>-</div><div class='del'>-	*end = '\n'; /* sentinel; we have space for it */</div><div class='del'>-</div><div class='del'>-	memset(&amp;SSID_rid, 0, sizeof(SSID_rid));</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 3 &amp;&amp; p &lt; end; i++) {</div><div class='del'>-		int j = 0;</div><div class='del'>-		/* copy up to 32 characters from this line */</div><div class='del'>-		while (*p != '\n' &amp;&amp; j &lt; 32)</div><div class='del'>-			SSID_rid.ssids[i].ssid[j++] = *p++;</div><div class='del'>-		if (j == 0)</div><div class='del'>-			break;</div><div class='del'>-		SSID_rid.ssids[i].len = cpu_to_le16(j);</div><div class='del'>-		/* skip to the beginning of the next line */</div><div class='del'>-		while (*p++ != '\n')</div><div class='del'>-			;</div><div class='del'>-	}</div><div class='del'>-	if (i)</div><div class='del'>-		SSID_rid.len = cpu_to_le16(sizeof(SSID_rid));</div><div class='del'>-	disable_MAC(ai, 1);</div><div class='del'>-	writeSsidRid(ai, &amp;SSID_rid, 1);</div><div class='del'>-	enable_MAC(ai, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void proc_APList_on_close(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data = file-&gt;private_data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	APListRid *APList_rid = &amp;ai-&gt;APList;</div><div class='del'>-	int i;</div><div class='del'>-</div><div class='del'>-	if (!data-&gt;writelen) return;</div><div class='del'>-</div><div class='del'>-	memset(APList_rid, 0, sizeof(*APList_rid));</div><div class='del'>-	APList_rid-&gt;len = cpu_to_le16(sizeof(*APList_rid));</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 4 &amp;&amp; data-&gt;writelen &gt;= (i + 1) * 6 * 3; i++)</div><div class='del'>-		mac_pton(data-&gt;wbuffer + i * 6 * 3, APList_rid-&gt;ap[i]);</div><div class='del'>-</div><div class='del'>-	disable_MAC(ai, 1);</div><div class='del'>-	writeAPListRid(ai, APList_rid, 1);</div><div class='del'>-	enable_MAC(ai, 1);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* This function wraps PC4500_writerid with a MAC disable */</div><div class='del'>-static int do_writerid(struct airo_info *ai, u16 rid, const void *rid_data,</div><div class='del'>-			int len, int dummy)</div><div class='del'>-{</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	disable_MAC(ai, 1);</div><div class='del'>-	rc = PC4500_writerid(ai, rid, rid_data, len, 1);</div><div class='del'>-	enable_MAC(ai, 1);</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-/* Returns the WEP key at the specified index, or -1 if that key does</div><div class='del'>- * not exist.  The buffer is assumed to be at least 16 bytes in length.</div><div class='del'>- */</div><div class='del'>-static int get_wep_key(struct airo_info *ai, u16 index, char *buf, u16 buflen)</div><div class='del'>-{</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	int rc;</div><div class='del'>-	__le16 lastindex;</div><div class='del'>-</div><div class='del'>-	rc = readWepKeyRid(ai, &amp;wkr, 1, 1);</div><div class='del'>-	if (rc != SUCCESS)</div><div class='del'>-		return -1;</div><div class='del'>-	do {</div><div class='del'>-		lastindex = wkr.kindex;</div><div class='del'>-		if (le16_to_cpu(wkr.kindex) == index) {</div><div class='del'>-			int klen = min_t(int, buflen, le16_to_cpu(wkr.klen));</div><div class='del'>-			memcpy(buf, wkr.key, klen);</div><div class='del'>-			return klen;</div><div class='del'>-		}</div><div class='del'>-		rc = readWepKeyRid(ai, &amp;wkr, 0, 1);</div><div class='del'>-		if (rc != SUCCESS)</div><div class='del'>-			return -1;</div><div class='del'>-	} while (lastindex != wkr.kindex);</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int get_wep_tx_idx(struct airo_info *ai)</div><div class='del'>-{</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	int rc;</div><div class='del'>-	__le16 lastindex;</div><div class='del'>-</div><div class='del'>-	rc = readWepKeyRid(ai, &amp;wkr, 1, 1);</div><div class='del'>-	if (rc != SUCCESS)</div><div class='del'>-		return -1;</div><div class='del'>-	do {</div><div class='del'>-		lastindex = wkr.kindex;</div><div class='del'>-		if (wkr.kindex == cpu_to_le16(0xffff))</div><div class='del'>-			return wkr.mac[0];</div><div class='del'>-		rc = readWepKeyRid(ai, &amp;wkr, 0, 1);</div><div class='del'>-		if (rc != SUCCESS)</div><div class='del'>-			return -1;</div><div class='del'>-	} while (lastindex != wkr.kindex);</div><div class='del'>-	return -1;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int set_wep_key(struct airo_info *ai, u16 index, const u8 *key,</div><div class='del'>-		       u16 keylen, int perm, int lock)</div><div class='del'>-{</div><div class='del'>-	static const unsigned char macaddr[ETH_ALEN] = { 0x01, 0, 0, 0, 0, 0 };</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	if (WARN_ON(keylen == 0))</div><div class='del'>-		return -1;</div><div class='del'>-</div><div class='del'>-	memset(&amp;wkr, 0, sizeof(wkr));</div><div class='del'>-	wkr.len = cpu_to_le16(sizeof(wkr));</div><div class='del'>-	wkr.kindex = cpu_to_le16(index);</div><div class='del'>-	wkr.klen = cpu_to_le16(keylen);</div><div class='del'>-	memcpy(wkr.key, key, keylen);</div><div class='del'>-	memcpy(wkr.mac, macaddr, ETH_ALEN);</div><div class='del'>-</div><div class='del'>-	if (perm) disable_MAC(ai, lock);</div><div class='del'>-	rc = writeWepKeyRid(ai, &amp;wkr, perm, lock);</div><div class='del'>-	if (perm) enable_MAC(ai, lock);</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int set_wep_tx_idx(struct airo_info *ai, u16 index, int perm, int lock)</div><div class='del'>-{</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	memset(&amp;wkr, 0, sizeof(wkr));</div><div class='del'>-	wkr.len = cpu_to_le16(sizeof(wkr));</div><div class='del'>-	wkr.kindex = cpu_to_le16(0xffff);</div><div class='del'>-	wkr.mac[0] = (char)index;</div><div class='del'>-</div><div class='del'>-	if (perm) {</div><div class='del'>-		ai-&gt;defindex = (char)index;</div><div class='del'>-		disable_MAC(ai, lock);</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rc = writeWepKeyRid(ai, &amp;wkr, perm, lock);</div><div class='del'>-</div><div class='del'>-	if (perm)</div><div class='del'>-		enable_MAC(ai, lock);</div><div class='del'>-	return rc;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void proc_wepkey_on_close(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int i, rc;</div><div class='del'>-	u8 key[16];</div><div class='del'>-	u16 index = 0;</div><div class='del'>-	int j = 0;</div><div class='del'>-</div><div class='del'>-	memset(key, 0, sizeof(key));</div><div class='del'>-</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if (!data-&gt;writelen) return;</div><div class='del'>-</div><div class='del'>-	if (data-&gt;wbuffer[0] &gt;= '0' &amp;&amp; data-&gt;wbuffer[0] &lt;= '3' &amp;&amp;</div><div class='del'>-	    (data-&gt;wbuffer[1] == ' ' || data-&gt;wbuffer[1] == '\n')) {</div><div class='del'>-		index = data-&gt;wbuffer[0] - '0';</div><div class='del'>-		if (data-&gt;wbuffer[1] == '\n') {</div><div class='del'>-			rc = set_wep_tx_idx(ai, index, 1, 1);</div><div class='del'>-			if (rc &lt; 0) {</div><div class='del'>-				airo_print_err(ai-&gt;dev-&gt;name, "failed to set "</div><div class='del'>-				               "WEP transmit index to %d: %d.",</div><div class='del'>-				               index, rc);</div><div class='del'>-			}</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-		j = 2;</div><div class='del'>-	} else {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "WepKey passed invalid key index");</div><div class='del'>-		return;</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	for (i = 0; i &lt; 16*3 &amp;&amp; data-&gt;wbuffer[i+j]; i++) {</div><div class='del'>-		int val;</div><div class='del'>-</div><div class='del'>-		if (i % 3 == 2)</div><div class='del'>-			continue;</div><div class='del'>-</div><div class='del'>-		val = hex_to_bin(data-&gt;wbuffer[i+j]);</div><div class='del'>-		if (val &lt; 0) {</div><div class='del'>-			airo_print_err(ai-&gt;dev-&gt;name, "WebKey passed invalid key hex");</div><div class='del'>-			return;</div><div class='del'>-		}</div><div class='del'>-		switch(i%3) {</div><div class='del'>-		case 0:</div><div class='del'>-			key[i/3] = (u8)val &lt;&lt; 4;</div><div class='del'>-			break;</div><div class='del'>-		case 1:</div><div class='del'>-			key[i/3] |= (u8)val;</div><div class='del'>-			break;</div><div class='del'>-		}</div><div class='del'>-	}</div><div class='del'>-</div><div class='del'>-	rc = set_wep_key(ai, index, key, i/3, 1, 1);</div><div class='del'>-	if (rc &lt; 0) {</div><div class='del'>-		airo_print_err(ai-&gt;dev-&gt;name, "failed to set WEP key at index "</div><div class='del'>-		               "%d: %d.", index, rc);</div><div class='del'>-	}</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_wepkey_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	char *ptr;</div><div class='del'>-	WepKeyRid wkr;</div><div class='del'>-	__le16 lastindex;</div><div class='del'>-	int j = 0;</div><div class='del'>-	int rc;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	memset(&amp;wkr, 0, sizeof(wkr));</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kzalloc(180, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	data-&gt;writelen = 0;</div><div class='del'>-	data-&gt;maxwritelen = 80;</div><div class='del'>-	if ((data-&gt;wbuffer = kzalloc(80, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (data-&gt;rbuffer);</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	data-&gt;on_close = proc_wepkey_on_close;</div><div class='del'>-</div><div class='del'>-	ptr = data-&gt;rbuffer;</div><div class='del'>-	strcpy(ptr, "No wep keys\n");</div><div class='del'>-	rc = readWepKeyRid(ai, &amp;wkr, 1, 1);</div><div class='del'>-	if (rc == SUCCESS) do {</div><div class='del'>-		lastindex = wkr.kindex;</div><div class='del'>-		if (wkr.kindex == cpu_to_le16(0xffff)) {</div><div class='del'>-			j += sprintf(ptr+j, "Tx key = %d\n",</div><div class='del'>-				     (int)wkr.mac[0]);</div><div class='del'>-		} else {</div><div class='del'>-			j += sprintf(ptr+j, "Key %d set with length = %d\n",</div><div class='del'>-				     le16_to_cpu(wkr.kindex),</div><div class='del'>-				     le16_to_cpu(wkr.klen));</div><div class='del'>-		}</div><div class='del'>-		readWepKeyRid(ai, &amp;wkr, 0, 1);</div><div class='del'>-	} while ((lastindex != wkr.kindex) &amp;&amp; (j &lt; 180-30));</div><div class='del'>-</div><div class='del'>-	data-&gt;readlen = strlen(data-&gt;rbuffer);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_SSID_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int i;</div><div class='del'>-	char *ptr;</div><div class='del'>-	SsidRid SSID_rid;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kmalloc(104, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	data-&gt;writelen = 0;</div><div class='del'>-	data-&gt;maxwritelen = 33*3;</div><div class='del'>-	/* allocate maxwritelen + 1; we'll want a sentinel */</div><div class='del'>-	if ((data-&gt;wbuffer = kzalloc(33*3 + 1, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (data-&gt;rbuffer);</div><div class='del'>-		kfree (file-&gt;private_data);</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	}</div><div class='del'>-	data-&gt;on_close = proc_SSID_on_close;</div><div class='del'>-</div><div class='del'>-	readSsidRid(ai, &amp;SSID_rid);</div><div class='del'>-	ptr = data-&gt;rbuffer;</div><div class='del'>-	for (i = 0; i &lt; 3; i++) {</div><div class='del'>-		int j;</div><div class='del'>-		size_t len = le16_to_cpu(SSID_rid.ssids[i].len);</div><div class='del'>-		if (!len)</div><div class='del'>-			break;</div><div class='del'>-		if (len &gt; 32)</div><div class='del'>-			len = 32;</div><div class='del'>-		for (j = 0; j &lt; len &amp;&amp; SSID_rid.ssids[i].ssid[j]; j++)</div><div class='del'>-			*ptr++ = SSID_rid.ssids[i].ssid[j];</div><div class='del'>-		*ptr++ = '\n';</div><div class='del'>-	}</div><div class='del'>-	*ptr = '\0';</div><div class='del'>-	data-&gt;readlen = strlen(data-&gt;rbuffer);</div><div class='del'>-	return 0;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int proc_APList_open(struct inode *inode, struct file *file)</div><div class='del'>-{</div><div class='del'>-	struct proc_data *data;</div><div class='del'>-	struct net_device *dev = pde_data(inode);</div><div class='del'>-	struct airo_info *ai = dev-&gt;ml_priv;</div><div class='del'>-	int i;</div><div class='del'>-	char *ptr;</div><div class='del'>-	APListRid *APList_rid = &amp;ai-&gt;APList;</div><div class='del'>-</div><div class='del'>-	if ((file-&gt;private_data = kzalloc(sizeof(struct proc_data), GFP_KERNEL)) == NULL)</div><div class='del'>-		return -ENOMEM;</div><div class='del'>-	data = file-&gt;private_data;</div><div class='del'>-	if ((data-&gt;rbuffer = kmalloc(104, GFP_KERNEL)) == NULL) {</div><div class='del'>-		kfree (file-&gt;